From 51bd5eac70e92207a5a147b32ad82790a06554c8 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Mon, 12 Nov 2018 02:59:36 +0000 Subject: [PATCH] Updating DB based on "Merge pull request #229 from mcmasterg/k7_bits". See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell --- Info.md | 251 +- artix7/settings.sh | 12 +- kintex7/element_counts.csv | 9 + kintex7/mask_bram_l.db | 8222 + kintex7/mask_bram_r.db | 8222 + kintex7/mask_clbll_l.db | 30 + kintex7/mask_clbll_r.db | 139 + kintex7/mask_clblm_l.db | 20 + kintex7/mask_clblm_r.db | 22 + kintex7/mask_dsp_l.db | 8030 + kintex7/mask_dsp_r.db | 8030 + kintex7/mask_hclk_l.db | 104 + kintex7/mask_hclk_r.db | 104 + kintex7/ppips_clbll_l.db | 146 + kintex7/ppips_clbll_r.db | 146 + kintex7/ppips_clblm_l.db | 151 + kintex7/ppips_clblm_r.db | 151 + kintex7/ppips_hclk_l.db | 8 + kintex7/ppips_hclk_r.db | 8 + kintex7/ppips_int_l.db | 44 + kintex7/ppips_int_r.db | 44 + kintex7/segbits_bram_l.block_ram.db | 0 kintex7/segbits_bram_l.db | 192 + kintex7/segbits_bram_r.block_ram.db | 0 kintex7/segbits_bram_r.db | 192 + kintex7/segbits_clbll_l.db | 121 + kintex7/segbits_clbll_r.db | 121 + kintex7/segbits_clblm_l.db | 127 + kintex7/segbits_clblm_r.db | 127 + kintex7/segbits_hclk_l.db | 196 + kintex7/segbits_hclk_r.db | 200 + kintex7/segbits_int_l.db | 154 + kintex7/segbits_int_r.db | 154 + kintex7/settings.sh | 7 +- kintex7/site_type_BSCAN.json | 39 + kintex7/site_type_BUFGCTRL.json | 82 + kintex7/site_type_BUFHCE.json | 24 + kintex7/site_type_BUFIO.json | 12 + kintex7/site_type_BUFMRCE.json | 24 + kintex7/site_type_BUFR.json | 18 + kintex7/site_type_CAPTURE.json | 12 + kintex7/site_type_DCIRESET.json | 12 + kintex7/site_type_DNA_PORT.json | 21 + kintex7/site_type_DSP48E1.json | 1402 + kintex7/site_type_EFUSE_USR.json | 102 + kintex7/site_type_FIFO18E1.json | 537 + kintex7/site_type_FRAME_ECC.json | 171 + kintex7/site_type_GTXE2_CHANNEL.json | 2195 + kintex7/site_type_GTXE2_COMMON.json | 447 + kintex7/site_type_IBUFDS_GTE2.json | 33 + kintex7/site_type_ICAP.json | 207 + kintex7/site_type_IDELAYCTRL.json | 27 + kintex7/site_type_IDELAYE2.json | 100 + kintex7/site_type_IDELAYE2_FINEDELAY.json | 100 + kintex7/site_type_ILOGICE2.json | 184 + kintex7/site_type_ILOGICE3.json | 208 + kintex7/site_type_IN_FIFO.json | 453 + kintex7/site_type_IOB18.json | 94 + kintex7/site_type_IOB18M.json | 106 + kintex7/site_type_IOB18S.json | 114 + kintex7/site_type_IOB33.json | 94 + kintex7/site_type_IOB33M.json | 106 + kintex7/site_type_IOB33S.json | 114 + kintex7/site_type_IPAD.json | 9 + kintex7/site_type_MMCME2_ADV.json | 545 + kintex7/site_type_ODELAYE2.json | 92 + kintex7/site_type_OLOGICE2.json | 210 + kintex7/site_type_OLOGICE3.json | 210 + kintex7/site_type_OPAD.json | 9 + kintex7/site_type_OUT_FIFO.json | 453 + kintex7/site_type_PCIE_2_1.json | 6753 + kintex7/site_type_PHASER_IN_PHY.json | 291 + kintex7/site_type_PHASER_OUT_PHY.json | 246 + kintex7/site_type_PHASER_REF.json | 89 + kintex7/site_type_PHY_CONTROL.json | 318 + kintex7/site_type_PLLE2_ADV.json | 493 + kintex7/site_type_PMV2.json | 27 + kintex7/site_type_RAMB18E1.json | 561 + kintex7/site_type_RAMBFIFO36E1.json | 1235 + kintex7/site_type_SLICEL.json | 694 + kintex7/site_type_SLICEM.json | 769 + kintex7/site_type_STARTUP.json | 45 + kintex7/site_type_TIEOFF.json | 12 + kintex7/site_type_USR_ACCESS.json | 108 + kintex7/site_type_XADC.json | 683 + kintex7/tile_type_BRAM_INT_INTERFACE_L.json | 476 + kintex7/tile_type_BRAM_INT_INTERFACE_R.json | 476 + kintex7/tile_type_BRAM_L.json | 9834 + kintex7/tile_type_BRAM_R.json | 9834 + kintex7/tile_type_BRKH_BRAM.json | 71 + kintex7/tile_type_BRKH_B_TERM_INT.json | 125 + kintex7/tile_type_BRKH_CLB.json | 11 + kintex7/tile_type_BRKH_CLK.json | 135 + kintex7/tile_type_BRKH_CMT.json | 16 + kintex7/tile_type_BRKH_DSP_L.json | 105 + kintex7/tile_type_BRKH_DSP_R.json | 105 + kintex7/tile_type_BRKH_GTX.json | 104 + kintex7/tile_type_BRKH_INT.json | 367 + kintex7/tile_type_BRKH_TERM_INT.json | 124 + kintex7/tile_type_B_TERM_INT.json | 125 + kintex7/tile_type_CFG_CENTER_BOT.json | 4513 + kintex7/tile_type_CFG_CENTER_MID.json | 7187 + kintex7/tile_type_CFG_CENTER_TOP.json | 2590 + kintex7/tile_type_CLBLL_L.json | 1449 + kintex7/tile_type_CLBLL_R.json | 1449 + kintex7/tile_type_CLBLM_L.json | 1494 + kintex7/tile_type_CLBLM_R.json | 1494 + kintex7/tile_type_CLK_BUFG_BOT_R.json | 3569 + kintex7/tile_type_CLK_BUFG_REBUF.json | 1188 + kintex7/tile_type_CLK_BUFG_TOP_R.json | 3569 + kintex7/tile_type_CLK_FEED.json | 261 + kintex7/tile_type_CLK_HROW_BOT_R.json | 22381 + kintex7/tile_type_CLK_HROW_TOP_R.json | 22381 + kintex7/tile_type_CLK_MTBF2.json | 365 + kintex7/tile_type_CLK_PMV.json | 1671 + kintex7/tile_type_CLK_PMV2.json | 377 + kintex7/tile_type_CLK_PMV2_SVT.json | 360 + kintex7/tile_type_CLK_PMVIOB.json | 359 + kintex7/tile_type_CLK_TERM.json | 71 + kintex7/tile_type_CMT_FIFO_L.json | 5261 + kintex7/tile_type_CMT_FIFO_R.json | 5261 + kintex7/tile_type_CMT_PMV.json | 230 + kintex7/tile_type_CMT_PMV_L.json | 230 + kintex7/tile_type_CMT_TOP_L_LOWER_B.json | 5450 + kintex7/tile_type_CMT_TOP_L_LOWER_T.json | 4823 + kintex7/tile_type_CMT_TOP_L_UPPER_B.json | 6524 + kintex7/tile_type_CMT_TOP_L_UPPER_T.json | 4422 + kintex7/tile_type_CMT_TOP_R_LOWER_B.json | 5450 + kintex7/tile_type_CMT_TOP_R_LOWER_T.json | 4823 + kintex7/tile_type_CMT_TOP_R_UPPER_B.json | 6524 + kintex7/tile_type_CMT_TOP_R_UPPER_T.json | 4422 + kintex7/tile_type_DSP_L.json | 8474 + kintex7/tile_type_DSP_R.json | 8474 + kintex7/tile_type_GTX_CHANNEL_0.json | 6854 + kintex7/tile_type_GTX_CHANNEL_1.json | 6854 + kintex7/tile_type_GTX_CHANNEL_2.json | 6854 + kintex7/tile_type_GTX_CHANNEL_3.json | 6854 + kintex7/tile_type_GTX_COMMON.json | 1873 + kintex7/tile_type_GTX_INT_INTERFACE.json | 1526 + kintex7/tile_type_HCLK_BRAM.json | 108 + kintex7/tile_type_HCLK_CLB.json | 49 + kintex7/tile_type_HCLK_CMT.json | 7067 + kintex7/tile_type_HCLK_CMT_L.json | 7047 + kintex7/tile_type_HCLK_DSP_L.json | 135 + kintex7/tile_type_HCLK_DSP_R.json | 135 + kintex7/tile_type_HCLK_FEEDTHRU_1.json | 37 + kintex7/tile_type_HCLK_FEEDTHRU_2.json | 37 + kintex7/tile_type_HCLK_FIFO_L.json | 45 + kintex7/tile_type_HCLK_GTX.json | 21 + kintex7/tile_type_HCLK_INT_INTERFACE.json | 49 + kintex7/tile_type_HCLK_IOB.json | 41 + kintex7/tile_type_HCLK_IOI.json | 1967 + kintex7/tile_type_HCLK_IOI3.json | 1954 + kintex7/tile_type_HCLK_L.json | 1695 + kintex7/tile_type_HCLK_L_BOT_UTURN.json | 908 + kintex7/tile_type_HCLK_R.json | 1695 + kintex7/tile_type_HCLK_R_BOT_UTURN.json | 908 + kintex7/tile_type_HCLK_TERM.json | 45 + kintex7/tile_type_HCLK_TERM_GTX.json | 21 + kintex7/tile_type_HCLK_VBRK.json | 45 + kintex7/tile_type_HCLK_VFRAME.json | 37 + kintex7/tile_type_INT_FEEDTHRU_1.json | 133 + kintex7/tile_type_INT_FEEDTHRU_2.json | 133 + kintex7/tile_type_INT_INTERFACE_L.json | 428 + kintex7/tile_type_INT_INTERFACE_R.json | 428 + kintex7/tile_type_INT_L.json | 26779 + kintex7/tile_type_INT_R.json | 26779 + kintex7/tile_type_IO_INT_INTERFACE_L.json | 428 + kintex7/tile_type_IO_INT_INTERFACE_R.json | 428 + kintex7/tile_type_LIOB33.json | 415 + kintex7/tile_type_LIOB33_SING.json | 175 + kintex7/tile_type_LIOI3.json | 3928 + kintex7/tile_type_LIOI3_SING.json | 1878 + kintex7/tile_type_LIOI3_TBYTESRC.json | 3893 + kintex7/tile_type_LIOI3_TBYTETERM.json | 3879 + kintex7/tile_type_L_TERM_INT.json | 173 + kintex7/tile_type_MONITOR_BOT_FUJI2.json | 3457 + kintex7/tile_type_MONITOR_MID_FUJI2.json | 2304 + kintex7/tile_type_MONITOR_TOP_FUJI2.json | 1172 + kintex7/tile_type_NULL.json | 8 + kintex7/tile_type_PCIE_BOT.json | 23028 + kintex7/tile_type_PCIE_INT_INTERFACE_L.json | 1526 + kintex7/tile_type_PCIE_INT_INTERFACE_R.json | 1526 + kintex7/tile_type_PCIE_NULL.json | 8 + kintex7/tile_type_PCIE_TOP.json | 5132 + kintex7/tile_type_RIOB18.json | 415 + kintex7/tile_type_RIOB18_SING.json | 175 + kintex7/tile_type_RIOI.json | 4314 + kintex7/tile_type_RIOI_SING.json | 2071 + kintex7/tile_type_RIOI_TBYTESRC.json | 4279 + kintex7/tile_type_RIOI_TBYTETERM.json | 4265 + kintex7/tile_type_R_TERM_INT.json | 173 + kintex7/tile_type_R_TERM_INT_GTX.json | 161 + kintex7/tile_type_TERM_CMT.json | 11 + kintex7/tile_type_T_TERM_INT.json | 124 + kintex7/tile_type_VBRK.json | 133 + kintex7/tile_type_VBRK_EXT.json | 99 + kintex7/tile_type_VFRAME.json | 229 + kintex7/tileconn.json | 477302 +++++++++++++++++ kintex7/tilegrid.json | 262533 ++++++++- kintex7/xc7k70tfbg676-2.yaml | 2570 +- 201 files changed, 1123390 insertions(+), 23741 deletions(-) create mode 100644 kintex7/element_counts.csv create mode 100644 kintex7/mask_bram_l.db create mode 100644 kintex7/mask_bram_r.db create mode 100644 kintex7/mask_dsp_l.db create mode 100644 kintex7/mask_dsp_r.db create mode 100644 kintex7/mask_hclk_l.db create mode 100644 kintex7/mask_hclk_r.db create mode 100644 kintex7/ppips_clbll_l.db create mode 100644 kintex7/ppips_clbll_r.db create mode 100644 kintex7/ppips_clblm_l.db create mode 100644 kintex7/ppips_clblm_r.db create mode 100644 kintex7/ppips_hclk_l.db create mode 100644 kintex7/ppips_hclk_r.db create mode 100644 kintex7/ppips_int_l.db create mode 100644 kintex7/ppips_int_r.db create mode 100644 kintex7/segbits_bram_l.block_ram.db create mode 100644 kintex7/segbits_bram_l.db create mode 100644 kintex7/segbits_bram_r.block_ram.db create mode 100644 kintex7/segbits_bram_r.db create mode 100644 kintex7/segbits_hclk_l.db create mode 100644 kintex7/segbits_hclk_r.db create mode 100644 kintex7/site_type_BSCAN.json create mode 100644 kintex7/site_type_BUFGCTRL.json create mode 100644 kintex7/site_type_BUFHCE.json create mode 100644 kintex7/site_type_BUFIO.json create mode 100644 kintex7/site_type_BUFMRCE.json create mode 100644 kintex7/site_type_BUFR.json create mode 100644 kintex7/site_type_CAPTURE.json create mode 100644 kintex7/site_type_DCIRESET.json create mode 100644 kintex7/site_type_DNA_PORT.json create mode 100644 kintex7/site_type_DSP48E1.json create mode 100644 kintex7/site_type_EFUSE_USR.json create mode 100644 kintex7/site_type_FIFO18E1.json create mode 100644 kintex7/site_type_FRAME_ECC.json create mode 100644 kintex7/site_type_GTXE2_CHANNEL.json create mode 100644 kintex7/site_type_GTXE2_COMMON.json create mode 100644 kintex7/site_type_IBUFDS_GTE2.json create mode 100644 kintex7/site_type_ICAP.json create mode 100644 kintex7/site_type_IDELAYCTRL.json create mode 100644 kintex7/site_type_IDELAYE2.json create mode 100644 kintex7/site_type_IDELAYE2_FINEDELAY.json create mode 100644 kintex7/site_type_ILOGICE2.json create mode 100644 kintex7/site_type_ILOGICE3.json create mode 100644 kintex7/site_type_IN_FIFO.json create mode 100644 kintex7/site_type_IOB18.json create mode 100644 kintex7/site_type_IOB18M.json create mode 100644 kintex7/site_type_IOB18S.json create mode 100644 kintex7/site_type_IOB33.json create mode 100644 kintex7/site_type_IOB33M.json create mode 100644 kintex7/site_type_IOB33S.json create mode 100644 kintex7/site_type_IPAD.json create mode 100644 kintex7/site_type_MMCME2_ADV.json create mode 100644 kintex7/site_type_ODELAYE2.json create mode 100644 kintex7/site_type_OLOGICE2.json create mode 100644 kintex7/site_type_OLOGICE3.json create mode 100644 kintex7/site_type_OPAD.json create mode 100644 kintex7/site_type_OUT_FIFO.json create mode 100644 kintex7/site_type_PCIE_2_1.json create mode 100644 kintex7/site_type_PHASER_IN_PHY.json create mode 100644 kintex7/site_type_PHASER_OUT_PHY.json create mode 100644 kintex7/site_type_PHASER_REF.json create mode 100644 kintex7/site_type_PHY_CONTROL.json create mode 100644 kintex7/site_type_PLLE2_ADV.json create mode 100644 kintex7/site_type_PMV2.json create mode 100644 kintex7/site_type_RAMB18E1.json create mode 100644 kintex7/site_type_RAMBFIFO36E1.json create mode 100644 kintex7/site_type_SLICEL.json create mode 100644 kintex7/site_type_SLICEM.json create mode 100644 kintex7/site_type_STARTUP.json create mode 100644 kintex7/site_type_TIEOFF.json create mode 100644 kintex7/site_type_USR_ACCESS.json create mode 100644 kintex7/site_type_XADC.json create mode 100644 kintex7/tile_type_BRAM_INT_INTERFACE_L.json create mode 100644 kintex7/tile_type_BRAM_INT_INTERFACE_R.json create mode 100644 kintex7/tile_type_BRAM_L.json create mode 100644 kintex7/tile_type_BRAM_R.json create mode 100644 kintex7/tile_type_BRKH_BRAM.json create mode 100644 kintex7/tile_type_BRKH_B_TERM_INT.json create mode 100644 kintex7/tile_type_BRKH_CLB.json create mode 100644 kintex7/tile_type_BRKH_CLK.json create mode 100644 kintex7/tile_type_BRKH_CMT.json create mode 100644 kintex7/tile_type_BRKH_DSP_L.json create mode 100644 kintex7/tile_type_BRKH_DSP_R.json create mode 100644 kintex7/tile_type_BRKH_GTX.json create mode 100644 kintex7/tile_type_BRKH_INT.json create mode 100644 kintex7/tile_type_BRKH_TERM_INT.json create mode 100644 kintex7/tile_type_B_TERM_INT.json create mode 100644 kintex7/tile_type_CFG_CENTER_BOT.json create mode 100644 kintex7/tile_type_CFG_CENTER_MID.json create mode 100644 kintex7/tile_type_CFG_CENTER_TOP.json create mode 100644 kintex7/tile_type_CLBLL_L.json create mode 100644 kintex7/tile_type_CLBLL_R.json create mode 100644 kintex7/tile_type_CLBLM_L.json create mode 100644 kintex7/tile_type_CLBLM_R.json create mode 100644 kintex7/tile_type_CLK_BUFG_BOT_R.json create mode 100644 kintex7/tile_type_CLK_BUFG_REBUF.json create mode 100644 kintex7/tile_type_CLK_BUFG_TOP_R.json create mode 100644 kintex7/tile_type_CLK_FEED.json create mode 100644 kintex7/tile_type_CLK_HROW_BOT_R.json create mode 100644 kintex7/tile_type_CLK_HROW_TOP_R.json create mode 100644 kintex7/tile_type_CLK_MTBF2.json create mode 100644 kintex7/tile_type_CLK_PMV.json create mode 100644 kintex7/tile_type_CLK_PMV2.json create mode 100644 kintex7/tile_type_CLK_PMV2_SVT.json create mode 100644 kintex7/tile_type_CLK_PMVIOB.json create mode 100644 kintex7/tile_type_CLK_TERM.json create mode 100644 kintex7/tile_type_CMT_FIFO_L.json create mode 100644 kintex7/tile_type_CMT_FIFO_R.json create mode 100644 kintex7/tile_type_CMT_PMV.json create mode 100644 kintex7/tile_type_CMT_PMV_L.json create mode 100644 kintex7/tile_type_CMT_TOP_L_LOWER_B.json create mode 100644 kintex7/tile_type_CMT_TOP_L_LOWER_T.json create mode 100644 kintex7/tile_type_CMT_TOP_L_UPPER_B.json create mode 100644 kintex7/tile_type_CMT_TOP_L_UPPER_T.json create mode 100644 kintex7/tile_type_CMT_TOP_R_LOWER_B.json create mode 100644 kintex7/tile_type_CMT_TOP_R_LOWER_T.json create mode 100644 kintex7/tile_type_CMT_TOP_R_UPPER_B.json create mode 100644 kintex7/tile_type_CMT_TOP_R_UPPER_T.json create mode 100644 kintex7/tile_type_DSP_L.json create mode 100644 kintex7/tile_type_DSP_R.json create mode 100644 kintex7/tile_type_GTX_CHANNEL_0.json create mode 100644 kintex7/tile_type_GTX_CHANNEL_1.json create mode 100644 kintex7/tile_type_GTX_CHANNEL_2.json create mode 100644 kintex7/tile_type_GTX_CHANNEL_3.json create mode 100644 kintex7/tile_type_GTX_COMMON.json create mode 100644 kintex7/tile_type_GTX_INT_INTERFACE.json create mode 100644 kintex7/tile_type_HCLK_BRAM.json create mode 100644 kintex7/tile_type_HCLK_CLB.json create mode 100644 kintex7/tile_type_HCLK_CMT.json create mode 100644 kintex7/tile_type_HCLK_CMT_L.json create mode 100644 kintex7/tile_type_HCLK_DSP_L.json create mode 100644 kintex7/tile_type_HCLK_DSP_R.json create mode 100644 kintex7/tile_type_HCLK_FEEDTHRU_1.json create mode 100644 kintex7/tile_type_HCLK_FEEDTHRU_2.json create mode 100644 kintex7/tile_type_HCLK_FIFO_L.json create mode 100644 kintex7/tile_type_HCLK_GTX.json create mode 100644 kintex7/tile_type_HCLK_INT_INTERFACE.json create mode 100644 kintex7/tile_type_HCLK_IOB.json create mode 100644 kintex7/tile_type_HCLK_IOI.json create mode 100644 kintex7/tile_type_HCLK_IOI3.json create mode 100644 kintex7/tile_type_HCLK_L.json create mode 100644 kintex7/tile_type_HCLK_L_BOT_UTURN.json create mode 100644 kintex7/tile_type_HCLK_R.json create mode 100644 kintex7/tile_type_HCLK_R_BOT_UTURN.json create mode 100644 kintex7/tile_type_HCLK_TERM.json create mode 100644 kintex7/tile_type_HCLK_TERM_GTX.json create mode 100644 kintex7/tile_type_HCLK_VBRK.json create mode 100644 kintex7/tile_type_HCLK_VFRAME.json create mode 100644 kintex7/tile_type_INT_FEEDTHRU_1.json create mode 100644 kintex7/tile_type_INT_FEEDTHRU_2.json create mode 100644 kintex7/tile_type_INT_INTERFACE_L.json create mode 100644 kintex7/tile_type_INT_INTERFACE_R.json create mode 100644 kintex7/tile_type_INT_L.json create mode 100644 kintex7/tile_type_INT_R.json create mode 100644 kintex7/tile_type_IO_INT_INTERFACE_L.json create mode 100644 kintex7/tile_type_IO_INT_INTERFACE_R.json create mode 100644 kintex7/tile_type_LIOB33.json create mode 100644 kintex7/tile_type_LIOB33_SING.json create mode 100644 kintex7/tile_type_LIOI3.json create mode 100644 kintex7/tile_type_LIOI3_SING.json create mode 100644 kintex7/tile_type_LIOI3_TBYTESRC.json create mode 100644 kintex7/tile_type_LIOI3_TBYTETERM.json create mode 100644 kintex7/tile_type_L_TERM_INT.json create mode 100644 kintex7/tile_type_MONITOR_BOT_FUJI2.json create mode 100644 kintex7/tile_type_MONITOR_MID_FUJI2.json create mode 100644 kintex7/tile_type_MONITOR_TOP_FUJI2.json create mode 100644 kintex7/tile_type_NULL.json create mode 100644 kintex7/tile_type_PCIE_BOT.json create mode 100644 kintex7/tile_type_PCIE_INT_INTERFACE_L.json create mode 100644 kintex7/tile_type_PCIE_INT_INTERFACE_R.json create mode 100644 kintex7/tile_type_PCIE_NULL.json create mode 100644 kintex7/tile_type_PCIE_TOP.json create mode 100644 kintex7/tile_type_RIOB18.json create mode 100644 kintex7/tile_type_RIOB18_SING.json create mode 100644 kintex7/tile_type_RIOI.json create mode 100644 kintex7/tile_type_RIOI_SING.json create mode 100644 kintex7/tile_type_RIOI_TBYTESRC.json create mode 100644 kintex7/tile_type_RIOI_TBYTETERM.json create mode 100644 kintex7/tile_type_R_TERM_INT.json create mode 100644 kintex7/tile_type_R_TERM_INT_GTX.json create mode 100644 kintex7/tile_type_TERM_CMT.json create mode 100644 kintex7/tile_type_T_TERM_INT.json create mode 100644 kintex7/tile_type_VBRK.json create mode 100644 kintex7/tile_type_VBRK_EXT.json create mode 100644 kintex7/tile_type_VFRAME.json create mode 100644 kintex7/tileconn.json diff --git a/Info.md b/Info.md index f1a6b42..610d79e 100644 --- a/Info.md +++ b/Info.md @@ -37,37 +37,39 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING). # Details -Last updated on Thu Oct 25 23:18:25 UTC 2018 (2018-10-25T23:18:25+00:00). +Last updated on Mon Nov 12 02:59:35 UTC 2018 (2018-11-12T02:59:35+00:00). -Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-903-ga0cfca8](https://github.com/SymbiFlow/prjxray/commit/a0cfca860872a99ac81b223ee1e5e9ae567b9590). +Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-984-gb43bf35](https://github.com/SymbiFlow/prjxray/commit/b43bf3539f51ed8a755ae245682cd660ca23d813). Latest commit was; ``` -commit a0cfca860872a99ac81b223ee1e5e9ae567b9590 -Merge: d33fdb7 3247963 +commit b43bf3539f51ed8a755ae245682cd660ca23d813 +Merge: b5d691c e2e236e Author: Tim Ansell -Date: Wed Oct 24 17:00:19 2018 -0700 +Date: Tue Nov 6 15:11:29 2018 -0800 - Merge pull request #191 from mithro/master + Merge pull request #229 from mcmasterg/k7_bits - minitests/roi_harness: Add XRAY_PIN values valid for Arty. + k7: use all bitstream bits, format settings.sh alike ``` ## Database for [artix7](artix7/) ### Settings -Created using following [settings.sh (sha256: cb777c1e854d877556482ff2067eff348386ce627caa0ef5617a6e5dea01dc6a)](https://github.com/SymbiFlow/prjxray/blob/a0cfca860872a99ac81b223ee1e5e9ae567b9590/database/artix7/settings.sh) +Created using following [settings.sh (sha256: d77b40f729b66962f0197a5e31b43860326401b6116ac36e727411319adac0f2)](https://github.com/SymbiFlow/prjxray/blob/b43bf3539f51ed8a755ae245682cd660ca23d813/database/artix7/settings.sh) ```shell export XRAY_DATABASE="artix7" export XRAY_PART="xc7a50tfgg484-1" -export XRAY_ROI="SLICE_X12Y100:SLICE_X27Y149" export XRAY_ROI_FRAMES="0x00000000:0xffffffff" -# Leave some CLBs to the left to allow easy ROI entering -export XRAY_ROI="SLICE_X8Y100:SLICE_X27Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59" -export XRAY_ROI_GRID_X1="18" -export XRAY_ROI_GRID_X2="47" +# All CLB's in part, all BRAM's in part, all DSP's in part. +export XRAY_ROI="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59" + +# Most of CMT X0Y2. +export XRAY_ROI_GRID_X1="9" +export XRAY_ROI_GRID_X2="58" +# Include VBRK / VTERM export XRAY_ROI_GRID_Y1="0" export XRAY_ROI_GRID_Y2="52" @@ -127,7 +129,7 @@ Results have checksums; * [`5e22f758a04eab3185b2453c9994aa2fa48f50ca8a6b49bf82e8fc4351f23a5c ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db) * [`08dee581e565abbd09db559f9226139ba5a253f8aec4f3492152d8df8a87bbab ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db) * [`13bc58bf4a42029adf4f9b06ffd7c9436e2294bf4fdc16cdaa70505c28a2a7b7 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db) - * [`cb777c1e854d877556482ff2067eff348386ce627caa0ef5617a6e5dea01dc6a ./artix7/settings.sh`](./artix7/settings.sh) + * [`d77b40f729b66962f0197a5e31b43860326401b6116ac36e727411319adac0f2 ./artix7/settings.sh`](./artix7/settings.sh) * [`3f6ab41214df9776a9cd8ea63cca60adab925abf08a3204549fa956ef87270de ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json) * [`b1e326e9c93fa1d239423b681aa22a1f999994280a6ef94626eafeb855d93571 ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json) * [`04a2cffb41ec815914fc361cb527df69cb36e4db74f25de6792c59f6ce97f6d3 ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json) @@ -294,16 +296,21 @@ Results have checksums; ### Settings -Created using following [settings.sh (sha256: 2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18)](https://github.com/SymbiFlow/prjxray/blob/a0cfca860872a99ac81b223ee1e5e9ae567b9590/database/kintex7/settings.sh) +Created using following [settings.sh (sha256: 555d484e8c10c35897ac446eb7a1bbebf0606c56dcd19caa9c8d916bb77cad64)](https://github.com/SymbiFlow/prjxray/blob/b43bf3539f51ed8a755ae245682cd660ca23d813/database/kintex7/settings.sh) ```shell export XRAY_DATABASE="kintex7" export XRAY_PART="xc7k70tfbg676-2" +export XRAY_ROI_FRAMES="0x00000000:0xffffffff" + export XRAY_ROI="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19" -export XRAY_ROI_FRAMES="0x00400100:0x004006ff" + +# Part of CMT X0Y1 export XRAY_ROI_GRID_X1="9" export XRAY_ROI_GRID_X2="38" +# Include VBRK / VTERM export XRAY_ROI_GRID_Y1="104" export XRAY_ROI_GRID_Y2="156" + # Choose the first N High Range I/Os export XRAY_PIN_00="K25" export XRAY_PIN_01="K26" @@ -320,6 +327,7 @@ source $(dirname ${BASH_SOURCE[0]})/../../utils/environment.sh Results have checksums; + * [`d154b5fc62e0ae17091b880050a7302f4f75fed1008967eb88e2c1e3f13f4792 ./kintex7/element_counts.csv`](./kintex7/element_counts.csv) * [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_bram0_l.db`](./kintex7/mask_bram0_l.db) * [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_bram0_r.db`](./kintex7/mask_bram0_r.db) * [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_bram1_l.db`](./kintex7/mask_bram1_l.db) @@ -330,10 +338,12 @@ Results have checksums; * [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_bram3_r.db`](./kintex7/mask_bram3_r.db) * [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_bram4_l.db`](./kintex7/mask_bram4_l.db) * [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_bram4_r.db`](./kintex7/mask_bram4_r.db) - * [`03fe7af3125c25f3d84bd8e874525c83275a6c3b6736d0b01134b5f982721f5b ./kintex7/mask_clbll_l.db`](./kintex7/mask_clbll_l.db) - * [`be34841c9aa64527e5f84d1819abbac1d324047367003b6fdc1402cd695481de ./kintex7/mask_clbll_r.db`](./kintex7/mask_clbll_r.db) - * [`fec2e4a94efd8b4e9d29d52689d406482f842e6f718ab671131b5e9ac2e0805b ./kintex7/mask_clblm_l.db`](./kintex7/mask_clblm_l.db) - * [`7b68fbcb19382d54bdc57971dd7eb9b0cbb4318f9b6053b301f3384f7ee4bb75 ./kintex7/mask_clblm_r.db`](./kintex7/mask_clblm_r.db) + * [`5d8e00a868cba3369bf2d5696d6871695967cb2a42f6464cb366dcef5d7d48e7 ./kintex7/mask_bram_l.db`](./kintex7/mask_bram_l.db) + * [`5d8e00a868cba3369bf2d5696d6871695967cb2a42f6464cb366dcef5d7d48e7 ./kintex7/mask_bram_r.db`](./kintex7/mask_bram_r.db) + * [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clbll_l.db`](./kintex7/mask_clbll_l.db) + * [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clbll_r.db`](./kintex7/mask_clbll_r.db) + * [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clblm_l.db`](./kintex7/mask_clblm_l.db) + * [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clblm_r.db`](./kintex7/mask_clblm_r.db) * [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_dsp0_l.db`](./kintex7/mask_dsp0_l.db) * [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_dsp0_r.db`](./kintex7/mask_dsp0_r.db) * [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_dsp1_l.db`](./kintex7/mask_dsp1_l.db) @@ -344,13 +354,196 @@ Results have checksums; * [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_dsp3_r.db`](./kintex7/mask_dsp3_r.db) * [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_dsp4_l.db`](./kintex7/mask_dsp4_l.db) * [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_dsp4_r.db`](./kintex7/mask_dsp4_r.db) - * [`3e3b19a2d49a1d0f25937bc5d0b33f0269c22c5e8ae3cfe52e4ff5c65843b134 ./kintex7/segbits_clbll_l.db`](./kintex7/segbits_clbll_l.db) - * [`fdb5499b9e2aa9d1796332279f0b5dc881a5ad0796698e8ef3af40ddc98df26b ./kintex7/segbits_clbll_r.db`](./kintex7/segbits_clbll_r.db) - * [`0b79670cc5a03b7580f73dc162a8bad048ade2f50971622138e0d0a5759899b6 ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db) - * [`e7f5d16940fde9397f69d5f52c2a6339641191dc9dba4466e8b7f9e5f6a735bf ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db) - * [`9ed8769618df03902c73e78312467108c7b74b903ac61d1bbbba1fd9710e6d3b ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db) - * [`dbf6cba5bbba95d7d78d9b51d236d8819dc776c2ebc540521e5b48d3a2c1390f ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db) - * [`2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18 ./kintex7/settings.sh`](./kintex7/settings.sh) - * [`8f5b7a7924adec5132208cf8e851e81bcb01a5c61f8839eb5a5de0b20b924510 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json) - * [`68426295ab4a35e367c9dff93e4f9b807afd43fe83418cb2da7465cd4d7177a2 ./kintex7/xc7k70tfbg676-2.yaml`](./kintex7/xc7k70tfbg676-2.yaml) + * [`76a9286b89fa91babd4ab8b59156b12a7024130d66f9f08da290797d00a115e6 ./kintex7/mask_dsp_l.db`](./kintex7/mask_dsp_l.db) + * [`76a9286b89fa91babd4ab8b59156b12a7024130d66f9f08da290797d00a115e6 ./kintex7/mask_dsp_r.db`](./kintex7/mask_dsp_r.db) + * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_l.db`](./kintex7/mask_hclk_l.db) + * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db) + * [`6baea72435613b87334f95cfe2b1ab36da4d57ada20b71a7dd870715b3e430c4 ./kintex7/ppips_clbll_l.db`](./kintex7/ppips_clbll_l.db) + * [`3955d590e8ee64c843bb80f911a08781c1bac63e71b577436ae1f44195a88e22 ./kintex7/ppips_clbll_r.db`](./kintex7/ppips_clbll_r.db) + * [`29f175153821dc13989eb580676ff0007e108d911275a74e7ebe45e819c14eaf ./kintex7/ppips_clblm_l.db`](./kintex7/ppips_clblm_l.db) + * [`52b53ae735d40632403283ab720db2172794a22c5245b3da7693b264d69a122d ./kintex7/ppips_clblm_r.db`](./kintex7/ppips_clblm_r.db) + * [`6d35b568a51f9b6761da2470a71738b2477ef72c16068a529ae8eb52b65bf17a ./kintex7/ppips_hclk_l.db`](./kintex7/ppips_hclk_l.db) + * [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./kintex7/ppips_hclk_r.db`](./kintex7/ppips_hclk_r.db) + * [`be617c15d1ec311b6249791414bbd69380fe90b476353cbb2fc2a7cb06f5029d ./kintex7/ppips_int_l.db`](./kintex7/ppips_int_l.db) + * [`a1423859c97a82dcfb114644f50b991db4ca7e0996e6d1ae4d2c97bfdfcb723d ./kintex7/ppips_int_r.db`](./kintex7/ppips_int_r.db) + * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/segbits_bram_l.block_ram.db`](./kintex7/segbits_bram_l.block_ram.db) + * [`b3011b6a49b05f1f0a40b499537d0f3eb208a51b87d6d97811911df50d4ad2d2 ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db) + * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/segbits_bram_r.block_ram.db`](./kintex7/segbits_bram_r.block_ram.db) + * [`ac4e1c029ed8e623985ca2665e7aa1fae57aa2b33defb5f8cfa17d34d160e4b1 ./kintex7/segbits_bram_r.db`](./kintex7/segbits_bram_r.db) + * [`7591abf4d35e031e0d35cb8fdfe77c2b7d0f2840625c105977108e08451857f4 ./kintex7/segbits_clbll_l.db`](./kintex7/segbits_clbll_l.db) + * [`9a23ca5a568841b282c0207ed4cfe70925b0d5c4bbf232e5ee5697123082078c ./kintex7/segbits_clbll_r.db`](./kintex7/segbits_clbll_r.db) + * [`10f499474dc8b6c4b051291d70aedadfb9902219079553eefbbc64dabfd78a06 ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db) + * [`4c3a3a92b4bb860098596ce8d4a6fd869aff59705dc5d5049ce97ee70f6d39ac ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db) + * [`df496c4d335fac0c379497ff0a75ba4f5c5c25bcce79f9c7a72d5f08066310db ./kintex7/segbits_hclk_l.db`](./kintex7/segbits_hclk_l.db) + * [`5e22f758a04eab3185b2453c9994aa2fa48f50ca8a6b49bf82e8fc4351f23a5c ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db) + * [`51b25643ef3b8a7a90181ad61199cd70ac8c5baa18ee1aacd2e81ff50ccdbfcf ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db) + * [`05d1165f911881b3600b01f86cad9a6618c8b0dadb7014def3145f9254fd0c45 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db) + * [`555d484e8c10c35897ac446eb7a1bbebf0606c56dcd19caa9c8d916bb77cad64 ./kintex7/settings.sh`](./kintex7/settings.sh) + * [`3d3390a265afd578bb096a995b3cd820b910712e6392d8abf6c4d90ba77cf3bd ./kintex7/site_type_BSCAN.json`](./kintex7/site_type_BSCAN.json) + * [`b4fd720cdfda56436ae275c9b96eac3b02d1eb46cc7ed67bcdbe02a22288f96a ./kintex7/site_type_BUFGCTRL.json`](./kintex7/site_type_BUFGCTRL.json) + * [`de586b421d77a904b9814921ad04b9dd37bf55dccbcb457d2cd5b7bd2059e408 ./kintex7/site_type_BUFHCE.json`](./kintex7/site_type_BUFHCE.json) + * [`b8fba943d1daba4bf68b60662ecd54d15d2e420844b3c365fccbbf540397e04f ./kintex7/site_type_BUFIO.json`](./kintex7/site_type_BUFIO.json) + * [`12f445c57c357a516bee5821b4432afa3428cc2435485fe4760d9f9d71df01da ./kintex7/site_type_BUFMRCE.json`](./kintex7/site_type_BUFMRCE.json) + * [`7f74df4f448f0688ff77300ca3a78f43d850876f50974dd99fa3e4b2b9eb93c4 ./kintex7/site_type_BUFR.json`](./kintex7/site_type_BUFR.json) + * [`918f7d1fa92e0781305ce37ec4a4803efbb19472b165b7a56fa78f254f5df8dc ./kintex7/site_type_CAPTURE.json`](./kintex7/site_type_CAPTURE.json) + * [`74c501f8de850d82eb3f3c9b1e50dfb0c29ead2449b03d85378bef0483219e0f ./kintex7/site_type_DCIRESET.json`](./kintex7/site_type_DCIRESET.json) + * [`e7e73464183458595a02afa7da58537dffd3dcd098c0e96dcce7ec197ac8afa7 ./kintex7/site_type_DNA_PORT.json`](./kintex7/site_type_DNA_PORT.json) + * [`0f696a78a57fab8995671dba639ac73d61013f4ec7aa65239662362be50a06ae ./kintex7/site_type_DSP48E1.json`](./kintex7/site_type_DSP48E1.json) + * [`ad1f2dc2bc5629fdc3a4308b045d103d76f38612d04c9dc8bde50339575d8d40 ./kintex7/site_type_EFUSE_USR.json`](./kintex7/site_type_EFUSE_USR.json) + * [`ae4b06dee05c810b85a6385d605d4bbf65ac169161b6fc3fe0199eb7737169a2 ./kintex7/site_type_FIFO18E1.json`](./kintex7/site_type_FIFO18E1.json) + * [`653cd09ce90f58d1e2be7ecc5522f058b30a7ec2b95ed549cf5f053d982a4ef7 ./kintex7/site_type_FRAME_ECC.json`](./kintex7/site_type_FRAME_ECC.json) + * [`16b0e88823f0490f8faa0f20cd175e06de645daf15397754c747570626f7737d ./kintex7/site_type_GTXE2_CHANNEL.json`](./kintex7/site_type_GTXE2_CHANNEL.json) + * [`e95bb4dcf5840cb482468f1a7d7160e1905a93c7f56a4d07891a671d250986b1 ./kintex7/site_type_GTXE2_COMMON.json`](./kintex7/site_type_GTXE2_COMMON.json) + * [`334f26f9d610cf1527cd3debabb454ce0db96130bf263a3efbe7ffddbcc5872c ./kintex7/site_type_IBUFDS_GTE2.json`](./kintex7/site_type_IBUFDS_GTE2.json) + * [`de547e93791ca92f8679a8a7d606505ceaa04436f82bdac851035d1836c60f59 ./kintex7/site_type_ICAP.json`](./kintex7/site_type_ICAP.json) + * [`a50c2bc260b5359aa96658a7191fa85212b12363b68cfcb6a75230392b35eefb ./kintex7/site_type_IDELAYCTRL.json`](./kintex7/site_type_IDELAYCTRL.json) + * [`ac42f477f213fc05f118b8f24c51ed01cbcf1c4dfd7ef3fe71ea3415cc4eb98d ./kintex7/site_type_IDELAYE2_FINEDELAY.json`](./kintex7/site_type_IDELAYE2_FINEDELAY.json) + * [`4eafb55d1b61747fd9ef8196454bb0a5df9d0784aeaef7a8e6da67dc1e51668e ./kintex7/site_type_IDELAYE2.json`](./kintex7/site_type_IDELAYE2.json) + * [`b572d4069bb6289d79baa673237a86a5e7d28b0efc6122e9505e31476144ca5d ./kintex7/site_type_ILOGICE2.json`](./kintex7/site_type_ILOGICE2.json) + * [`97cce70ba181e41b8a0ca9076b470ce49dfefae95f588837d73686f82d4305c8 ./kintex7/site_type_ILOGICE3.json`](./kintex7/site_type_ILOGICE3.json) + * [`dbd9354873d1673301b9779a04c23db947c325280fdefc05fec5fec974d25e69 ./kintex7/site_type_IN_FIFO.json`](./kintex7/site_type_IN_FIFO.json) + * [`9cd9d19d9805453ff7319c84f7e092e7af999c054cf11eb4f4839015b599dbee ./kintex7/site_type_IOB18.json`](./kintex7/site_type_IOB18.json) + * [`126b44af8a35bf0fc2a981bd240169a4ce12371f4db48d71bfafd2fb714a54f5 ./kintex7/site_type_IOB18M.json`](./kintex7/site_type_IOB18M.json) + * [`6f850e2eb9ff74e61dc8ee43296ffbba1e195951bba7ab9b195c72bc0c765f20 ./kintex7/site_type_IOB18S.json`](./kintex7/site_type_IOB18S.json) + * [`8d88647b1059737d103ec85b97fc2ea4c1acf871c20feacc7df9e3074ed0e54b ./kintex7/site_type_IOB33.json`](./kintex7/site_type_IOB33.json) + * [`d4ad99dabcca0c2040f348634e8758f9335f4e4b3f97ff7c53d67a929a5252be ./kintex7/site_type_IOB33M.json`](./kintex7/site_type_IOB33M.json) + * [`f875e1ba42bb51dd6ae044223e196c763bd19bfcec40384343a4b6bee5b7cd4f ./kintex7/site_type_IOB33S.json`](./kintex7/site_type_IOB33S.json) + * [`6922af5e94c020bf330e088a74c09ad7be09b4264756154dea5769d5631e22bf ./kintex7/site_type_IPAD.json`](./kintex7/site_type_IPAD.json) + * [`c6536a1020e7164cd3e596c01526c5e3365a73cdfd9c1a6f2cf3616544eced1d ./kintex7/site_type_MMCME2_ADV.json`](./kintex7/site_type_MMCME2_ADV.json) + * [`437ef6ec381eb246a9df43bf6e2e7232a4246bbf87deab3980910b627221e17d ./kintex7/site_type_ODELAYE2.json`](./kintex7/site_type_ODELAYE2.json) + * [`b51e1d6cf2e8874843e19afbddda3c8ba4dac5801890c389cb21b474c4c3b19d ./kintex7/site_type_OLOGICE2.json`](./kintex7/site_type_OLOGICE2.json) + * [`1567aa8832b40e8706ce45da566f681a101ea3ca581a308f0fc0cea40f8e9c20 ./kintex7/site_type_OLOGICE3.json`](./kintex7/site_type_OLOGICE3.json) + * [`26a864898c5fccc0713e6c50cc1d979b85c7f80ef283ad7f4bebc390b272a0a0 ./kintex7/site_type_OPAD.json`](./kintex7/site_type_OPAD.json) + * [`83dd093773549002cf7a1c7b0f4a1aa9309006f4954d5d44986aa9a4c0dd070a ./kintex7/site_type_OUT_FIFO.json`](./kintex7/site_type_OUT_FIFO.json) + * [`a1e6a8c61bd25f4022d8fcd7516d3d81cdde6985b32fd82104f007460cff04f9 ./kintex7/site_type_PCIE_2_1.json`](./kintex7/site_type_PCIE_2_1.json) + * [`aff4c1cecba401965587250c873f7c2a144b6472416ac4623b34dbce6b393aa0 ./kintex7/site_type_PHASER_IN_PHY.json`](./kintex7/site_type_PHASER_IN_PHY.json) + * [`1b18d9c78eb215d6e93c994128c1522fd4227c339f000fa3207e02f2a9a78137 ./kintex7/site_type_PHASER_OUT_PHY.json`](./kintex7/site_type_PHASER_OUT_PHY.json) + * [`3c74a6c5775b46fedb0f870bd9cfacdba57fe7699d4784e9e485425030675dbf ./kintex7/site_type_PHASER_REF.json`](./kintex7/site_type_PHASER_REF.json) + * [`397270675c85b40f5b749c6939fe6209005b6201a26434c743f294ef25d5ca98 ./kintex7/site_type_PHY_CONTROL.json`](./kintex7/site_type_PHY_CONTROL.json) + * [`be572d2892f943ab8a69d03924da674b0f64bf61ad69ff7968242743609e21f3 ./kintex7/site_type_PLLE2_ADV.json`](./kintex7/site_type_PLLE2_ADV.json) + * [`cabec9a6d1e017ff751a80c2ec10d0b0b76ef014d1ba73f6ea6793e3ec2ff2dc ./kintex7/site_type_PMV2.json`](./kintex7/site_type_PMV2.json) + * [`1a869b379e657531322f061b568950595a8fb6030c32f5fea82bfdc19df50120 ./kintex7/site_type_RAMB18E1.json`](./kintex7/site_type_RAMB18E1.json) + * [`a9c86c49d3287782468a28f710fa1334fe2c5a69bb8b20cc804caf112e703148 ./kintex7/site_type_RAMBFIFO36E1.json`](./kintex7/site_type_RAMBFIFO36E1.json) + * [`51804af3230d43c989f909b2a305c67e1c7cc8bafefda5d912864e1fb74a4d14 ./kintex7/site_type_SLICEL.json`](./kintex7/site_type_SLICEL.json) + * [`1ad52d9cf41a20610535e24cd352b7c9cd85e33dd3d0f57580ab56063eb184a5 ./kintex7/site_type_SLICEM.json`](./kintex7/site_type_SLICEM.json) + * [`ba727d2d69816bcace78fd39fd3431ff2a4d89ef94c5401380b475bd49f11ca5 ./kintex7/site_type_STARTUP.json`](./kintex7/site_type_STARTUP.json) + * [`7329766c3d005888d7c26e2971eede01b5868561ebf3a2fd79418ede9b8eea7e ./kintex7/site_type_TIEOFF.json`](./kintex7/site_type_TIEOFF.json) + * [`8630a9324f0e03108cde9c677bd86d0bde54576467691b225e0428948b44d526 ./kintex7/site_type_USR_ACCESS.json`](./kintex7/site_type_USR_ACCESS.json) + * [`dfcdd7535d3da5d3e3fd5ab6487490eacbb697d28058d9a59d6d053b56a348f4 ./kintex7/site_type_XADC.json`](./kintex7/site_type_XADC.json) + * [`fcc005f080da4cebe34427d6ffdab475fa1e994e06ae865cada7556a33a5caa5 ./kintex7/tileconn.json`](./kintex7/tileconn.json) + * [`2ccb101556ecee8ad729fbdd2dcbca296beb0cddc1755f649de3255cbaa51b2f ./kintex7/tilegrid.json`](./kintex7/tilegrid.json) + * [`e41553a434c96945d188d8f4c9479b2c8cdcc266aecedcaec808ce3313a90838 ./kintex7/tile_type_BRAM_INT_INTERFACE_L.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_L.json) + * [`bcdc2360681535c7bd1059bc7589563ee13658a0054e6e7bdc9e2c666f32c161 ./kintex7/tile_type_BRAM_INT_INTERFACE_R.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_R.json) + * [`c02f17fd75d3f9c51cdee987c564623ec7a260a4189b5762fb8ce52ac37403a8 ./kintex7/tile_type_BRAM_L.json`](./kintex7/tile_type_BRAM_L.json) + * [`4860e2e56b17e157efdd9a05e8dd8929bb4b302ba610754d6749eb57cd9707d7 ./kintex7/tile_type_BRAM_R.json`](./kintex7/tile_type_BRAM_R.json) + * [`a2c7168fac50a80ba1ffd64533b079b2f6c7cf3ebfa506f7dd28c42ad102e605 ./kintex7/tile_type_BRKH_BRAM.json`](./kintex7/tile_type_BRKH_BRAM.json) + * [`3147439b966fd3ca65030a80e8cd78de68bfb8493db6adcaddda0dd195edc1d8 ./kintex7/tile_type_BRKH_B_TERM_INT.json`](./kintex7/tile_type_BRKH_B_TERM_INT.json) + * [`21f2bf31f07964e8f4d8878ff6ad90f7c956f91c1ffdfa3775f46935e907676e ./kintex7/tile_type_BRKH_CLB.json`](./kintex7/tile_type_BRKH_CLB.json) + * [`d1c4672ad9c1bcff94d597847751abb6fbac92584c22598abc08ac7c7af8021b ./kintex7/tile_type_BRKH_CLK.json`](./kintex7/tile_type_BRKH_CLK.json) + * [`5578b9e473da648aea8413aee1003f0472dd2826327eb65ec42848ed96735ecc ./kintex7/tile_type_BRKH_CMT.json`](./kintex7/tile_type_BRKH_CMT.json) + * [`ea3e20731602dc5096ca43000f46ec5ecfa01aa91d166b2c6503b37530b06ac5 ./kintex7/tile_type_BRKH_DSP_L.json`](./kintex7/tile_type_BRKH_DSP_L.json) + * [`8e4dd08bb2ca3fce962e6b34a2133f122a96e5e1ae16c2d969c2078c049687b5 ./kintex7/tile_type_BRKH_DSP_R.json`](./kintex7/tile_type_BRKH_DSP_R.json) + * [`4914b83cd7fb2ff11eeaa679fbafcfcc59b5e089e02890b9d99cf703c719a820 ./kintex7/tile_type_BRKH_GTX.json`](./kintex7/tile_type_BRKH_GTX.json) + * [`5fe2c1814b8fac0bc28f32205ea620dff25be4dd9754122a0185d1395b354c5f ./kintex7/tile_type_BRKH_INT.json`](./kintex7/tile_type_BRKH_INT.json) + * [`3d438a6e8f9a7abaf7ec414d67f786fb9b1fa58cdc91649bef84688c00df85c1 ./kintex7/tile_type_BRKH_TERM_INT.json`](./kintex7/tile_type_BRKH_TERM_INT.json) + * [`9ea642a0684cc8102c865e7d6c486a888c88e102dc873f13e7f6d46d47e00047 ./kintex7/tile_type_B_TERM_INT.json`](./kintex7/tile_type_B_TERM_INT.json) + * [`0000c209ed73d7f807258ae042ff63c39c259b1239675d19454b3b000ea71ac2 ./kintex7/tile_type_CFG_CENTER_BOT.json`](./kintex7/tile_type_CFG_CENTER_BOT.json) + * [`32b33effc6925a1af80e119159f536dd768bdea60336fcad5a8d6d081a2372dc ./kintex7/tile_type_CFG_CENTER_MID.json`](./kintex7/tile_type_CFG_CENTER_MID.json) + * [`020ae47321f03311f5897f2c79c569368315a816a42549289d009570a2d76c4a ./kintex7/tile_type_CFG_CENTER_TOP.json`](./kintex7/tile_type_CFG_CENTER_TOP.json) + * [`a49fcafa32e32533ded2d3425d1b0b072e841f932747e6169118837bcf2b59d1 ./kintex7/tile_type_CLBLL_L.json`](./kintex7/tile_type_CLBLL_L.json) + * [`fadf83bf66fb1597816743f59567e632c494495545e00b0d02aa6207691a85b2 ./kintex7/tile_type_CLBLL_R.json`](./kintex7/tile_type_CLBLL_R.json) + * [`063337506d9f67a776b79b480f744830321ff3d5acfdb667d431e1c80a0bb8f9 ./kintex7/tile_type_CLBLM_L.json`](./kintex7/tile_type_CLBLM_L.json) + * [`5bc4d0154647a684fc9d29f68ce9df390ed2fcd7ce3fd45592013ec26934fa5f ./kintex7/tile_type_CLBLM_R.json`](./kintex7/tile_type_CLBLM_R.json) + * [`bfc9e3df22c7a99e9af69c7110b1c404fe607c84c3dc77b8004273b630e35fb8 ./kintex7/tile_type_CLK_BUFG_BOT_R.json`](./kintex7/tile_type_CLK_BUFG_BOT_R.json) + * [`666b6bc037b409912132e3cff9ae3fe752f9f9dc32d8a46fbc63603e8a610bde ./kintex7/tile_type_CLK_BUFG_REBUF.json`](./kintex7/tile_type_CLK_BUFG_REBUF.json) + * [`868b04aab06f4d7285980fb76f87ccb1479966667a525858fed1f2c9216e9c9e ./kintex7/tile_type_CLK_BUFG_TOP_R.json`](./kintex7/tile_type_CLK_BUFG_TOP_R.json) + * [`9c2af1c0da6184efb136bd14308401459a411c95bdb2ffc1a51c42fed96b6146 ./kintex7/tile_type_CLK_FEED.json`](./kintex7/tile_type_CLK_FEED.json) + * [`fa1be3fdfd71f9b1cc10bfd7ddc926801e55fc72632baad0a255e96bada68d0d ./kintex7/tile_type_CLK_HROW_BOT_R.json`](./kintex7/tile_type_CLK_HROW_BOT_R.json) + * [`d2ee4dfc7b939cfa99feab874bd23d247e7305c0d303fc068eb6871e987c2c7b ./kintex7/tile_type_CLK_HROW_TOP_R.json`](./kintex7/tile_type_CLK_HROW_TOP_R.json) + * [`f7c3840af1472567372deba23095e1c611599c9b8b2b324d724f475ede4a1fd2 ./kintex7/tile_type_CLK_MTBF2.json`](./kintex7/tile_type_CLK_MTBF2.json) + * [`27fcefe864e7f7e94ecc0e93562598d4f9893c2781b0898c00d1e248eb57bafb ./kintex7/tile_type_CLK_PMV2.json`](./kintex7/tile_type_CLK_PMV2.json) + * [`4c322a13547b7541c6bfacfabd022732f18c2d631155f420b2581d33ef6c4fe8 ./kintex7/tile_type_CLK_PMV2_SVT.json`](./kintex7/tile_type_CLK_PMV2_SVT.json) + * [`c6a4ea7ebb2c777757db340988b102cdf40ac41b047122a1f4a78acad6615363 ./kintex7/tile_type_CLK_PMVIOB.json`](./kintex7/tile_type_CLK_PMVIOB.json) + * [`0d720ca3564a20b00f765b8434411ed005278d5dac53a2ba9824382dec34f91a ./kintex7/tile_type_CLK_PMV.json`](./kintex7/tile_type_CLK_PMV.json) + * [`acbd313bd0e8fa6bc14d913035d9f48c44bdc694b44b80af81003230b6b43bc3 ./kintex7/tile_type_CLK_TERM.json`](./kintex7/tile_type_CLK_TERM.json) + * [`7ebaf8de3ac6d90a54f7bba8ad9296f711e495d31faff3d69d7fa5a738536345 ./kintex7/tile_type_CMT_FIFO_L.json`](./kintex7/tile_type_CMT_FIFO_L.json) + * [`f5a063540d3cfa2448ad9dbdd159eb1556639bd25c1a1a13e5c4b20bdb3705fb ./kintex7/tile_type_CMT_FIFO_R.json`](./kintex7/tile_type_CMT_FIFO_R.json) + * [`eb15ba5757944c16d529084037357a3caf65f261f4b96e2224502d5bbd3ff385 ./kintex7/tile_type_CMT_PMV.json`](./kintex7/tile_type_CMT_PMV.json) + * [`40e69910d395ab4490c52cd7164d340979fa75b8bf6038ec6ad632434327d1c4 ./kintex7/tile_type_CMT_PMV_L.json`](./kintex7/tile_type_CMT_PMV_L.json) + * [`bf3185ece81d8b23884efb2ec6a679da17503d40dbca626d77a3120fe25b7dc0 ./kintex7/tile_type_CMT_TOP_L_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_B.json) + * [`7c214c04796b00a899239386dbf96a3374526d4f598260a66a17528df2c25490 ./kintex7/tile_type_CMT_TOP_L_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_T.json) + * [`1fecfa3bd69bf4052fd03b8e6befeefffd4497fd8a26304e2203d5015dfdd96e ./kintex7/tile_type_CMT_TOP_L_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_B.json) + * [`71ec5188a2672ca580fde960587162e824910bf5ca442ed0667b04ed8f8ec658 ./kintex7/tile_type_CMT_TOP_L_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_T.json) + * [`290c5b101ab12b3aee3f21ea2e0b49d9c4eb2ba12fe163b67d0325b3f113cede ./kintex7/tile_type_CMT_TOP_R_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_B.json) + * [`df0721000e697f028e7b19885f707083aca76fe9770325c4c3ac21f335ad1213 ./kintex7/tile_type_CMT_TOP_R_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_T.json) + * [`7b04421048a84bb525184a825dafb7434ce34ad5b5aaa25d03682471f07d409a ./kintex7/tile_type_CMT_TOP_R_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_B.json) + * [`81cc5f8cc02f8d03dbcb2099d5a6d6abf6d535923cd5d110bf1a14c5881ac2f7 ./kintex7/tile_type_CMT_TOP_R_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_T.json) + * [`d9b3ed62399b13be64de5189e7073cb4a9bb9d6138c518bd0bdfa117be5f8d25 ./kintex7/tile_type_DSP_L.json`](./kintex7/tile_type_DSP_L.json) + * [`c94c9737ea45ca39c9c5f93b0e15f73d5f0ba0a9657e1aa092360c6afbdb502c ./kintex7/tile_type_DSP_R.json`](./kintex7/tile_type_DSP_R.json) + * [`143ef93a6d36530005f72fb35c5c6d329a77ee89fda3f9b49a5384a748e33130 ./kintex7/tile_type_GTX_CHANNEL_0.json`](./kintex7/tile_type_GTX_CHANNEL_0.json) + * [`635967c5bd4e17f217b04163bc6f093b96258df49bd70f52772a2d6ecfe9f09b ./kintex7/tile_type_GTX_CHANNEL_1.json`](./kintex7/tile_type_GTX_CHANNEL_1.json) + * [`dc56bd7a0b202176c881376a25d606a652c6fc2628e14d0e33f04c687a87902e ./kintex7/tile_type_GTX_CHANNEL_2.json`](./kintex7/tile_type_GTX_CHANNEL_2.json) + * [`1b3214d207350e3ea4735d1c4d7281c961203de23e6b69c135db4374d36a422f ./kintex7/tile_type_GTX_CHANNEL_3.json`](./kintex7/tile_type_GTX_CHANNEL_3.json) + * [`816700f8baad2f8bc5a65149662d274169ff3508512bb60b241f1b744c895ef8 ./kintex7/tile_type_GTX_COMMON.json`](./kintex7/tile_type_GTX_COMMON.json) + * [`20a27c3adf87bee51238e3f5855c48e305d370faf3cf221086f2a39a0c6fb601 ./kintex7/tile_type_GTX_INT_INTERFACE.json`](./kintex7/tile_type_GTX_INT_INTERFACE.json) + * [`e2f1b81b49be2e71ba2a80ffb217bcbeffffeabefe97b5d09811c4ff4c617e36 ./kintex7/tile_type_HCLK_BRAM.json`](./kintex7/tile_type_HCLK_BRAM.json) + * [`64b5e77fffa455fee7ffdf8d4fc0ec0c5770c59cf2c7d3cfdf3352baa70417a1 ./kintex7/tile_type_HCLK_CLB.json`](./kintex7/tile_type_HCLK_CLB.json) + * [`c92ea55ecb7c2fb73c1ed2f4b9cd884724001bfdd92de5fc4bf10a2e5abc39e5 ./kintex7/tile_type_HCLK_CMT.json`](./kintex7/tile_type_HCLK_CMT.json) + * [`8df99aa03d4e77f5a9acdc5770a1b294f022eb69b838328fc8d367614a8c2daa ./kintex7/tile_type_HCLK_CMT_L.json`](./kintex7/tile_type_HCLK_CMT_L.json) + * [`f41d0d6065a4c247c9742a7f564f062a18582e8c928ec9d9140648b99503d92e ./kintex7/tile_type_HCLK_DSP_L.json`](./kintex7/tile_type_HCLK_DSP_L.json) + * [`c923a360ae2c99bb443282431b03ba8b8fba68d05b82a0ff797b716f34bfc251 ./kintex7/tile_type_HCLK_DSP_R.json`](./kintex7/tile_type_HCLK_DSP_R.json) + * [`dde046196e4a4d4da476226fd9667483f82d39cef00bf9dc38cef5f17ab1c914 ./kintex7/tile_type_HCLK_FEEDTHRU_1.json`](./kintex7/tile_type_HCLK_FEEDTHRU_1.json) + * [`9bbb0a7d24a5d02ad01c0e39039130ccc909e879abc349a92f597cbe469dd49d ./kintex7/tile_type_HCLK_FEEDTHRU_2.json`](./kintex7/tile_type_HCLK_FEEDTHRU_2.json) + * [`84c757904074b41d7c14fbbba37ce47a9f72f998e9e623eb206d15d5b78d1d41 ./kintex7/tile_type_HCLK_FIFO_L.json`](./kintex7/tile_type_HCLK_FIFO_L.json) + * [`8425afb4d0a2d98e1dfd1d26393aa80a74e51f56d1e9aef8935a7970f04bf14d ./kintex7/tile_type_HCLK_GTX.json`](./kintex7/tile_type_HCLK_GTX.json) + * [`81407bfaf8f2526850bd6d4e715895af022f0408c91484608b8381fc12393df2 ./kintex7/tile_type_HCLK_INT_INTERFACE.json`](./kintex7/tile_type_HCLK_INT_INTERFACE.json) + * [`4c1f24d434ce7b48dae3d9b4d06bd64af7e1e5837d0dc0bc792d42e76bf113cb ./kintex7/tile_type_HCLK_IOB.json`](./kintex7/tile_type_HCLK_IOB.json) + * [`76260e86d5ecdd6b1f114ffe05ac2a959afcaca4be25635c2d4ecf3f76ff6986 ./kintex7/tile_type_HCLK_IOI3.json`](./kintex7/tile_type_HCLK_IOI3.json) + * [`d39f1659520b0538d275a30d56a24eb176174e10f43fd8817363cc26ddca1f0c ./kintex7/tile_type_HCLK_IOI.json`](./kintex7/tile_type_HCLK_IOI.json) + * [`34f7588770dde88264dfa413b3a56d724001efcf8a70b696a44ac87810150ec6 ./kintex7/tile_type_HCLK_L_BOT_UTURN.json`](./kintex7/tile_type_HCLK_L_BOT_UTURN.json) + * [`574450912455e0c9088b68833d6e535b8868f34deee4c25387301b1de9296a00 ./kintex7/tile_type_HCLK_L.json`](./kintex7/tile_type_HCLK_L.json) + * [`037972ef07a8be72225783db245097c0037b4fd4a42c3551b60114b65968973a ./kintex7/tile_type_HCLK_R_BOT_UTURN.json`](./kintex7/tile_type_HCLK_R_BOT_UTURN.json) + * [`064f051fd195837ec3dd8560bb555be5ce1b66bd8eec94e8b709e365a1fcc2d5 ./kintex7/tile_type_HCLK_R.json`](./kintex7/tile_type_HCLK_R.json) + * [`52aff0ffab55a41d78b9a276dee0b9decc97022c020c74c5a96ad3d92bed5863 ./kintex7/tile_type_HCLK_TERM_GTX.json`](./kintex7/tile_type_HCLK_TERM_GTX.json) + * [`eb62ef0efc2a718ccf84321087ad832ab0467b3203d680adc701179fadc91bf6 ./kintex7/tile_type_HCLK_TERM.json`](./kintex7/tile_type_HCLK_TERM.json) + * [`220b12b284dddb2c238552b0218797d0ba3457ed18175ab70cef8415f0c0201a ./kintex7/tile_type_HCLK_VBRK.json`](./kintex7/tile_type_HCLK_VBRK.json) + * [`46330a09e75de3b349d69a0083b9304822f7fbf8ae1a5fb763da4784973dd240 ./kintex7/tile_type_HCLK_VFRAME.json`](./kintex7/tile_type_HCLK_VFRAME.json) + * [`7f09e309e6653af7118d7fc931fe31b246b7cc8531923861496eedf3dc77b5be ./kintex7/tile_type_INT_FEEDTHRU_1.json`](./kintex7/tile_type_INT_FEEDTHRU_1.json) + * [`28b7ecc94f160d54bc79368c562fe4df0e843509e5434771ed8f6b55f18b6bf4 ./kintex7/tile_type_INT_FEEDTHRU_2.json`](./kintex7/tile_type_INT_FEEDTHRU_2.json) + * [`6aa23f8918efc454795ab7822e52e3999edb1c198eddd8e6aa0c2f653d40d1e4 ./kintex7/tile_type_INT_INTERFACE_L.json`](./kintex7/tile_type_INT_INTERFACE_L.json) + * [`0b317673faf61ae014f66ceb9db46191c8e4f3c8b0a14cc017982ef283e4395e ./kintex7/tile_type_INT_INTERFACE_R.json`](./kintex7/tile_type_INT_INTERFACE_R.json) + * [`26700b39a04bd369ee5563ca9e84ac01f87895c05da73e0ce6046336cc8852ce ./kintex7/tile_type_INT_L.json`](./kintex7/tile_type_INT_L.json) + * [`2e37a5d868bd73ddc1a7d1ecf90df3e8710e6bbbb9f972c14129116326a6b4e4 ./kintex7/tile_type_INT_R.json`](./kintex7/tile_type_INT_R.json) + * [`aa66ce19f9ad6b965241375bfb47bd89e2a1348a58c968368e86281931b44590 ./kintex7/tile_type_IO_INT_INTERFACE_L.json`](./kintex7/tile_type_IO_INT_INTERFACE_L.json) + * [`0b1638c1d020419c7cd893f6f0777fe7e9b31f59cd3df806a04a1d8a75236ca4 ./kintex7/tile_type_IO_INT_INTERFACE_R.json`](./kintex7/tile_type_IO_INT_INTERFACE_R.json) + * [`834aeafff58ab00c55362bcb5b8f57a0c4eba75bed850857396f451005de25b7 ./kintex7/tile_type_LIOB33.json`](./kintex7/tile_type_LIOB33.json) + * [`1cd4802b53f8b51ebda08cb505216bd2359ebe8a25b9b25f0a47009e7bd50a0e ./kintex7/tile_type_LIOB33_SING.json`](./kintex7/tile_type_LIOB33_SING.json) + * [`197d350086961d53460b275c6d38f58dff6b9ddc4022498c1ba7462e975167b6 ./kintex7/tile_type_LIOI3.json`](./kintex7/tile_type_LIOI3.json) + * [`fcee806a19995fefb66d1abf203cabe4551ca5a1555b74438ddb9ebde743a3b7 ./kintex7/tile_type_LIOI3_SING.json`](./kintex7/tile_type_LIOI3_SING.json) + * [`72d291224c4e6a7c875a3985731909c51c7e912670215ce3102129b879d4237d ./kintex7/tile_type_LIOI3_TBYTESRC.json`](./kintex7/tile_type_LIOI3_TBYTESRC.json) + * [`afb7e0c93c96a5f1390d9ea8a7a1427f13a523949ccc3cfb4e73c8a95ecdecf8 ./kintex7/tile_type_LIOI3_TBYTETERM.json`](./kintex7/tile_type_LIOI3_TBYTETERM.json) + * [`916025d46555f5911087f1f062d9af1fb5f8fc69df39cc5d230d448098ff32e6 ./kintex7/tile_type_L_TERM_INT.json`](./kintex7/tile_type_L_TERM_INT.json) + * [`76c1cd952c48be9fc23f284bccaef7fc45589ec023aee73266984877c034d8f7 ./kintex7/tile_type_MONITOR_BOT_FUJI2.json`](./kintex7/tile_type_MONITOR_BOT_FUJI2.json) + * [`6ba81b6b8cc26d484121a92431e780fb60a4fcf3fc5fb87c057281a671b01536 ./kintex7/tile_type_MONITOR_MID_FUJI2.json`](./kintex7/tile_type_MONITOR_MID_FUJI2.json) + * [`86b81044a371a36deeb7c2ba96f2ae7c109a2a81dede577d887e32b129c5f18a ./kintex7/tile_type_MONITOR_TOP_FUJI2.json`](./kintex7/tile_type_MONITOR_TOP_FUJI2.json) + * [`5d1de70987a005e1b8b2fa0589cd53a201e1f2c9836921e6040a000b9484a228 ./kintex7/tile_type_NULL.json`](./kintex7/tile_type_NULL.json) + * [`1ecb8c465ca2a8586c69e79c3d8ec072b9c2c875df10bd1de4decb8bc92f9d55 ./kintex7/tile_type_PCIE_BOT.json`](./kintex7/tile_type_PCIE_BOT.json) + * [`aa7b93e6c781119b8d5f87a10fc48ebaa73a4eead078e93132b7ddaa33dc88c3 ./kintex7/tile_type_PCIE_INT_INTERFACE_L.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_L.json) + * [`0ec7eb6ac887ffd60a1cce398c2b221bcbfb0fc7b4cdff1127beecc48197e3a7 ./kintex7/tile_type_PCIE_INT_INTERFACE_R.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_R.json) + * [`f8abe2a7f48b0b15d56403fe33643420508dfb0b864fb2dd1318705bae67eeb0 ./kintex7/tile_type_PCIE_NULL.json`](./kintex7/tile_type_PCIE_NULL.json) + * [`0f42ceb80f80cdead3214dd5082582573d861183720c3f68aa9efe6510c81252 ./kintex7/tile_type_PCIE_TOP.json`](./kintex7/tile_type_PCIE_TOP.json) + * [`e7ba0a1160e8ca8a9a99ca17b5c624dc75858ae448adb1ff1e1dadd90d9cd602 ./kintex7/tile_type_RIOB18.json`](./kintex7/tile_type_RIOB18.json) + * [`e3e6fcf61bcdee2fd8b46d6e9669b4c73feb8f19e6796762f9ccbad14e5448fe ./kintex7/tile_type_RIOB18_SING.json`](./kintex7/tile_type_RIOB18_SING.json) + * [`41e9510b0f26afe800182bbd33f9bd595c62da90e5240513ba45acae935e15b2 ./kintex7/tile_type_RIOI.json`](./kintex7/tile_type_RIOI.json) + * [`f49c630e38cdae7604634429d94f3f366fdaa7633d8839db2ce981c88aa42f53 ./kintex7/tile_type_RIOI_SING.json`](./kintex7/tile_type_RIOI_SING.json) + * [`f9f803ced00d2affd7f15055757ff71010f336622c023ba96d55afdb1e93df2e ./kintex7/tile_type_RIOI_TBYTESRC.json`](./kintex7/tile_type_RIOI_TBYTESRC.json) + * [`b451e9504276aa50b8ab30db52de2b0c90e539d93565e0fa2fd1286c9fe9701c ./kintex7/tile_type_RIOI_TBYTETERM.json`](./kintex7/tile_type_RIOI_TBYTETERM.json) + * [`8b67fcc25ba2c2a2fc6e40e02b9c937a2f24a15cf341b76f185505e3de8b1f30 ./kintex7/tile_type_R_TERM_INT_GTX.json`](./kintex7/tile_type_R_TERM_INT_GTX.json) + * [`e4fb30a3dbc933eb7329ae159d273d3c1812db2cc687a96ff9593723978b3aa8 ./kintex7/tile_type_R_TERM_INT.json`](./kintex7/tile_type_R_TERM_INT.json) + * [`f9376a728ef3da4da5cabdc092004a3147ad5ef4f23fb35b123c808ca8cf70c4 ./kintex7/tile_type_TERM_CMT.json`](./kintex7/tile_type_TERM_CMT.json) + * [`05c16b5d98372ae3c77cdd752aaf56fa2eb9f935a976c93cbc1228e5e2c79f22 ./kintex7/tile_type_T_TERM_INT.json`](./kintex7/tile_type_T_TERM_INT.json) + * [`3c16819ae98be7cb228351b295b569dd44f9783f76dd986c230c9627b2051479 ./kintex7/tile_type_VBRK_EXT.json`](./kintex7/tile_type_VBRK_EXT.json) + * [`b1df8c22d9d53b06c1e99cef0671c426c5b6b07af2a829b5a6ba4d135b4190d7 ./kintex7/tile_type_VBRK.json`](./kintex7/tile_type_VBRK.json) + * [`29958122ee0af5d22e10da2fca1ebd680c7aeda1f600ebeeab71d350de8c4a55 ./kintex7/tile_type_VFRAME.json`](./kintex7/tile_type_VFRAME.json) + * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg676-2.yaml`](./kintex7/xc7k70tfbg676-2.yaml) diff --git a/artix7/settings.sh b/artix7/settings.sh index f247d6f..98984ea 100644 --- a/artix7/settings.sh +++ b/artix7/settings.sh @@ -1,12 +1,14 @@ export XRAY_DATABASE="artix7" export XRAY_PART="xc7a50tfgg484-1" -export XRAY_ROI="SLICE_X12Y100:SLICE_X27Y149" export XRAY_ROI_FRAMES="0x00000000:0xffffffff" -# Leave some CLBs to the left to allow easy ROI entering -export XRAY_ROI="SLICE_X8Y100:SLICE_X27Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59" -export XRAY_ROI_GRID_X1="18" -export XRAY_ROI_GRID_X2="47" +# All CLB's in part, all BRAM's in part, all DSP's in part. +export XRAY_ROI="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59" + +# Most of CMT X0Y2. +export XRAY_ROI_GRID_X1="9" +export XRAY_ROI_GRID_X2="58" +# Include VBRK / VTERM export XRAY_ROI_GRID_Y1="0" export XRAY_ROI_GRID_Y2="52" diff --git a/kintex7/element_counts.csv b/kintex7/element_counts.csv new file mode 100644 index 0000000..d930950 --- /dev/null +++ b/kintex7/element_counts.csv @@ -0,0 +1,9 @@ +type,count +tiles,24453 +sites,20251 +site_pins,740913 +site_pips,1505860 +pips,29424910 +package_pins,676 +nodes,2663055 +wires,8339126 diff --git a/kintex7/mask_bram_l.db b/kintex7/mask_bram_l.db new file mode 100644 index 0000000..7eeea48 --- /dev/null +++ b/kintex7/mask_bram_l.db @@ -0,0 +1,8222 @@ +bit 00_01 +bit 00_02 +bit 00_03 +bit 00_05 +bit 00_06 +bit 00_07 +bit 00_09 +bit 00_10 +bit 00_101 +bit 00_102 +bit 00_103 +bit 00_105 +bit 00_106 +bit 00_107 +bit 00_109 +bit 00_11 +bit 00_110 +bit 00_111 +bit 00_113 +bit 00_114 +bit 00_115 +bit 00_117 +bit 00_118 +bit 00_119 +bit 00_121 +bit 00_122 +bit 00_123 +bit 00_125 +bit 00_126 +bit 00_127 +bit 00_129 +bit 00_13 +bit 00_130 +bit 00_131 +bit 00_133 +bit 00_134 +bit 00_135 +bit 00_137 +bit 00_138 +bit 00_139 +bit 00_14 +bit 00_141 +bit 00_142 +bit 00_143 +bit 00_145 +bit 00_146 +bit 00_147 +bit 00_149 +bit 00_15 +bit 00_150 +bit 00_151 +bit 00_153 +bit 00_154 +bit 00_155 +bit 00_157 +bit 00_158 +bit 00_161 +bit 00_162 +bit 00_163 +bit 00_165 +bit 00_166 +bit 00_167 +bit 00_169 +bit 00_17 +bit 00_170 +bit 00_171 +bit 00_173 +bit 00_174 +bit 00_175 +bit 00_177 +bit 00_178 +bit 00_179 +bit 00_18 +bit 00_181 +bit 00_182 +bit 00_183 +bit 00_185 +bit 00_186 +bit 00_187 +bit 00_189 +bit 00_19 +bit 00_190 +bit 00_191 +bit 00_193 +bit 00_194 +bit 00_195 +bit 00_197 +bit 00_198 +bit 00_199 +bit 00_201 +bit 00_202 +bit 00_203 +bit 00_205 +bit 00_206 +bit 00_207 +bit 00_209 +bit 00_21 +bit 00_210 +bit 00_211 +bit 00_213 +bit 00_214 +bit 00_215 +bit 00_217 +bit 00_218 +bit 00_219 +bit 00_22 +bit 00_221 +bit 00_222 +bit 00_225 +bit 00_226 +bit 00_227 +bit 00_229 +bit 00_23 +bit 00_230 +bit 00_231 +bit 00_233 +bit 00_234 +bit 00_235 +bit 00_237 +bit 00_238 +bit 00_239 +bit 00_241 +bit 00_242 +bit 00_243 +bit 00_245 +bit 00_246 +bit 00_247 +bit 00_249 +bit 00_25 +bit 00_250 +bit 00_251 +bit 00_253 +bit 00_254 +bit 00_255 +bit 00_257 +bit 00_258 +bit 00_259 +bit 00_26 +bit 00_261 +bit 00_262 +bit 00_263 +bit 00_265 +bit 00_266 +bit 00_267 +bit 00_269 +bit 00_27 +bit 00_270 +bit 00_271 +bit 00_273 +bit 00_274 +bit 00_275 +bit 00_277 +bit 00_278 +bit 00_279 +bit 00_281 +bit 00_282 +bit 00_283 +bit 00_285 +bit 00_286 +bit 00_289 +bit 00_29 +bit 00_290 +bit 00_291 +bit 00_293 +bit 00_294 +bit 00_295 +bit 00_297 +bit 00_298 +bit 00_299 +bit 00_30 +bit 00_301 +bit 00_302 +bit 00_303 +bit 00_305 +bit 00_306 +bit 00_307 +bit 00_309 +bit 00_310 +bit 00_311 +bit 00_313 +bit 00_314 +bit 00_315 +bit 00_317 +bit 00_318 +bit 00_319 +bit 00_33 +bit 00_34 +bit 00_35 +bit 00_37 +bit 00_38 +bit 00_39 +bit 00_41 +bit 00_42 +bit 00_43 +bit 00_45 +bit 00_46 +bit 00_47 +bit 00_49 +bit 00_50 +bit 00_51 +bit 00_53 +bit 00_54 +bit 00_55 +bit 00_57 +bit 00_58 +bit 00_59 +bit 00_61 +bit 00_62 +bit 00_63 +bit 00_65 +bit 00_66 +bit 00_67 +bit 00_69 +bit 00_70 +bit 00_71 +bit 00_73 +bit 00_74 +bit 00_75 +bit 00_77 +bit 00_78 +bit 00_79 +bit 00_81 +bit 00_82 +bit 00_83 +bit 00_85 +bit 00_86 +bit 00_87 +bit 00_89 +bit 00_90 +bit 00_91 +bit 00_93 +bit 00_94 +bit 00_97 +bit 00_98 +bit 00_99 +bit 01_00 +bit 01_01 +bit 01_02 +bit 01_04 +bit 01_05 +bit 01_06 +bit 01_08 +bit 01_09 +bit 01_10 +bit 01_100 +bit 01_101 +bit 01_102 +bit 01_104 +bit 01_105 +bit 01_106 +bit 01_108 +bit 01_109 +bit 01_110 +bit 01_112 +bit 01_113 +bit 01_114 +bit 01_116 +bit 01_117 +bit 01_118 +bit 01_12 +bit 01_120 +bit 01_121 +bit 01_122 +bit 01_124 +bit 01_125 +bit 01_126 +bit 01_128 +bit 01_129 +bit 01_13 +bit 01_130 +bit 01_132 +bit 01_133 +bit 01_134 +bit 01_136 +bit 01_137 +bit 01_138 +bit 01_14 +bit 01_140 +bit 01_141 +bit 01_142 +bit 01_144 +bit 01_145 +bit 01_146 +bit 01_148 +bit 01_149 +bit 01_150 +bit 01_152 +bit 01_153 +bit 01_154 +bit 01_156 +bit 01_157 +bit 01_16 +bit 01_160 +bit 01_161 +bit 01_162 +bit 01_164 +bit 01_165 +bit 01_166 +bit 01_168 +bit 01_169 +bit 01_17 +bit 01_170 +bit 01_172 +bit 01_173 +bit 01_174 +bit 01_176 +bit 01_177 +bit 01_178 +bit 01_18 +bit 01_180 +bit 01_181 +bit 01_182 +bit 01_184 +bit 01_185 +bit 01_186 +bit 01_188 +bit 01_189 +bit 01_190 +bit 01_192 +bit 01_193 +bit 01_194 +bit 01_196 +bit 01_197 +bit 01_198 +bit 01_20 +bit 01_200 +bit 01_201 +bit 01_202 +bit 01_204 +bit 01_205 +bit 01_206 +bit 01_208 +bit 01_209 +bit 01_21 +bit 01_210 +bit 01_212 +bit 01_213 +bit 01_214 +bit 01_216 +bit 01_217 +bit 01_218 +bit 01_22 +bit 01_220 +bit 01_221 +bit 01_224 +bit 01_225 +bit 01_226 +bit 01_228 +bit 01_229 +bit 01_230 +bit 01_232 +bit 01_233 +bit 01_234 +bit 01_236 +bit 01_237 +bit 01_238 +bit 01_24 +bit 01_240 +bit 01_241 +bit 01_242 +bit 01_244 +bit 01_245 +bit 01_246 +bit 01_248 +bit 01_249 +bit 01_25 +bit 01_250 +bit 01_252 +bit 01_253 +bit 01_254 +bit 01_256 +bit 01_257 +bit 01_258 +bit 01_26 +bit 01_260 +bit 01_261 +bit 01_262 +bit 01_264 +bit 01_265 +bit 01_266 +bit 01_268 +bit 01_269 +bit 01_270 +bit 01_272 +bit 01_273 +bit 01_274 +bit 01_276 +bit 01_277 +bit 01_278 +bit 01_28 +bit 01_280 +bit 01_281 +bit 01_282 +bit 01_284 +bit 01_285 +bit 01_288 +bit 01_289 +bit 01_29 +bit 01_290 +bit 01_292 +bit 01_293 +bit 01_294 +bit 01_296 +bit 01_297 +bit 01_298 +bit 01_300 +bit 01_301 +bit 01_302 +bit 01_304 +bit 01_305 +bit 01_306 +bit 01_308 +bit 01_309 +bit 01_310 +bit 01_312 +bit 01_313 +bit 01_314 +bit 01_316 +bit 01_317 +bit 01_318 +bit 01_32 +bit 01_33 +bit 01_34 +bit 01_36 +bit 01_37 +bit 01_38 +bit 01_40 +bit 01_41 +bit 01_42 +bit 01_44 +bit 01_45 +bit 01_46 +bit 01_48 +bit 01_49 +bit 01_50 +bit 01_52 +bit 01_53 +bit 01_54 +bit 01_56 +bit 01_57 +bit 01_58 +bit 01_60 +bit 01_61 +bit 01_62 +bit 01_64 +bit 01_65 +bit 01_66 +bit 01_68 +bit 01_69 +bit 01_70 +bit 01_72 +bit 01_73 +bit 01_74 +bit 01_76 +bit 01_77 +bit 01_78 +bit 01_80 +bit 01_81 +bit 01_82 +bit 01_84 +bit 01_85 +bit 01_86 +bit 01_88 +bit 01_89 +bit 01_90 +bit 01_92 +bit 01_93 +bit 01_96 +bit 01_97 +bit 01_98 +bit 02_01 +bit 02_02 +bit 02_03 +bit 02_05 +bit 02_06 +bit 02_07 +bit 02_09 +bit 02_10 +bit 02_101 +bit 02_102 +bit 02_103 +bit 02_105 +bit 02_106 +bit 02_107 +bit 02_109 +bit 02_11 +bit 02_110 +bit 02_111 +bit 02_113 +bit 02_114 +bit 02_115 +bit 02_117 +bit 02_118 +bit 02_119 +bit 02_121 +bit 02_122 +bit 02_123 +bit 02_125 +bit 02_126 +bit 02_127 +bit 02_129 +bit 02_13 +bit 02_130 +bit 02_131 +bit 02_133 +bit 02_134 +bit 02_135 +bit 02_137 +bit 02_138 +bit 02_139 +bit 02_14 +bit 02_141 +bit 02_142 +bit 02_143 +bit 02_145 +bit 02_146 +bit 02_147 +bit 02_149 +bit 02_15 +bit 02_150 +bit 02_151 +bit 02_153 +bit 02_154 +bit 02_155 +bit 02_157 +bit 02_158 +bit 02_159 +bit 02_161 +bit 02_162 +bit 02_163 +bit 02_165 +bit 02_166 +bit 02_167 +bit 02_169 +bit 02_17 +bit 02_170 +bit 02_171 +bit 02_173 +bit 02_174 +bit 02_175 +bit 02_177 +bit 02_178 +bit 02_179 +bit 02_18 +bit 02_181 +bit 02_182 +bit 02_183 +bit 02_185 +bit 02_186 +bit 02_187 +bit 02_189 +bit 02_19 +bit 02_190 +bit 02_191 +bit 02_193 +bit 02_194 +bit 02_195 +bit 02_197 +bit 02_198 +bit 02_199 +bit 02_201 +bit 02_202 +bit 02_203 +bit 02_205 +bit 02_206 +bit 02_207 +bit 02_209 +bit 02_21 +bit 02_210 +bit 02_211 +bit 02_213 +bit 02_214 +bit 02_215 +bit 02_217 +bit 02_218 +bit 02_219 +bit 02_22 +bit 02_221 +bit 02_222 +bit 02_223 +bit 02_225 +bit 02_226 +bit 02_227 +bit 02_229 +bit 02_23 +bit 02_230 +bit 02_231 +bit 02_233 +bit 02_234 +bit 02_235 +bit 02_237 +bit 02_238 +bit 02_239 +bit 02_241 +bit 02_242 +bit 02_243 +bit 02_245 +bit 02_246 +bit 02_247 +bit 02_249 +bit 02_25 +bit 02_250 +bit 02_251 +bit 02_253 +bit 02_254 +bit 02_255 +bit 02_257 +bit 02_258 +bit 02_259 +bit 02_26 +bit 02_261 +bit 02_262 +bit 02_263 +bit 02_265 +bit 02_266 +bit 02_267 +bit 02_269 +bit 02_27 +bit 02_270 +bit 02_271 +bit 02_273 +bit 02_274 +bit 02_275 +bit 02_277 +bit 02_278 +bit 02_279 +bit 02_281 +bit 02_282 +bit 02_283 +bit 02_285 +bit 02_286 +bit 02_287 +bit 02_289 +bit 02_29 +bit 02_290 +bit 02_291 +bit 02_293 +bit 02_294 +bit 02_295 +bit 02_297 +bit 02_298 +bit 02_299 +bit 02_30 +bit 02_301 +bit 02_302 +bit 02_303 +bit 02_305 +bit 02_306 +bit 02_307 +bit 02_309 +bit 02_31 +bit 02_310 +bit 02_311 +bit 02_313 +bit 02_314 +bit 02_315 +bit 02_317 +bit 02_318 +bit 02_319 +bit 02_33 +bit 02_34 +bit 02_35 +bit 02_37 +bit 02_38 +bit 02_39 +bit 02_41 +bit 02_42 +bit 02_43 +bit 02_45 +bit 02_46 +bit 02_47 +bit 02_49 +bit 02_50 +bit 02_51 +bit 02_53 +bit 02_54 +bit 02_55 +bit 02_57 +bit 02_58 +bit 02_59 +bit 02_61 +bit 02_62 +bit 02_63 +bit 02_65 +bit 02_66 +bit 02_67 +bit 02_69 +bit 02_70 +bit 02_71 +bit 02_73 +bit 02_74 +bit 02_75 +bit 02_77 +bit 02_78 +bit 02_79 +bit 02_81 +bit 02_82 +bit 02_83 +bit 02_85 +bit 02_86 +bit 02_87 +bit 02_89 +bit 02_90 +bit 02_91 +bit 02_93 +bit 02_94 +bit 02_95 +bit 02_97 +bit 02_98 +bit 02_99 +bit 03_00 +bit 03_01 +bit 03_02 +bit 03_04 +bit 03_05 +bit 03_06 +bit 03_08 +bit 03_09 +bit 03_10 +bit 03_100 +bit 03_101 +bit 03_102 +bit 03_104 +bit 03_105 +bit 03_106 +bit 03_108 +bit 03_109 +bit 03_110 +bit 03_112 +bit 03_113 +bit 03_114 +bit 03_116 +bit 03_117 +bit 03_118 +bit 03_12 +bit 03_120 +bit 03_121 +bit 03_122 +bit 03_124 +bit 03_125 +bit 03_126 +bit 03_128 +bit 03_129 +bit 03_13 +bit 03_130 +bit 03_132 +bit 03_133 +bit 03_134 +bit 03_136 +bit 03_137 +bit 03_138 +bit 03_14 +bit 03_140 +bit 03_141 +bit 03_142 +bit 03_144 +bit 03_145 +bit 03_146 +bit 03_148 +bit 03_149 +bit 03_150 +bit 03_152 +bit 03_153 +bit 03_154 +bit 03_156 +bit 03_157 +bit 03_158 +bit 03_16 +bit 03_160 +bit 03_161 +bit 03_162 +bit 03_164 +bit 03_165 +bit 03_166 +bit 03_168 +bit 03_169 +bit 03_17 +bit 03_170 +bit 03_172 +bit 03_173 +bit 03_174 +bit 03_176 +bit 03_177 +bit 03_178 +bit 03_18 +bit 03_180 +bit 03_181 +bit 03_182 +bit 03_184 +bit 03_185 +bit 03_186 +bit 03_188 +bit 03_189 +bit 03_190 +bit 03_192 +bit 03_193 +bit 03_194 +bit 03_196 +bit 03_197 +bit 03_198 +bit 03_20 +bit 03_200 +bit 03_201 +bit 03_202 +bit 03_204 +bit 03_205 +bit 03_206 +bit 03_208 +bit 03_209 +bit 03_21 +bit 03_210 +bit 03_212 +bit 03_213 +bit 03_214 +bit 03_216 +bit 03_217 +bit 03_218 +bit 03_22 +bit 03_220 +bit 03_221 +bit 03_222 +bit 03_224 +bit 03_225 +bit 03_226 +bit 03_228 +bit 03_229 +bit 03_230 +bit 03_232 +bit 03_233 +bit 03_234 +bit 03_236 +bit 03_237 +bit 03_238 +bit 03_24 +bit 03_240 +bit 03_241 +bit 03_242 +bit 03_244 +bit 03_245 +bit 03_246 +bit 03_248 +bit 03_249 +bit 03_25 +bit 03_250 +bit 03_252 +bit 03_253 +bit 03_254 +bit 03_256 +bit 03_257 +bit 03_258 +bit 03_26 +bit 03_260 +bit 03_261 +bit 03_262 +bit 03_264 +bit 03_265 +bit 03_266 +bit 03_268 +bit 03_269 +bit 03_270 +bit 03_272 +bit 03_273 +bit 03_274 +bit 03_276 +bit 03_277 +bit 03_278 +bit 03_28 +bit 03_280 +bit 03_281 +bit 03_282 +bit 03_284 +bit 03_285 +bit 03_286 +bit 03_288 +bit 03_289 +bit 03_29 +bit 03_290 +bit 03_292 +bit 03_293 +bit 03_294 +bit 03_296 +bit 03_297 +bit 03_298 +bit 03_30 +bit 03_300 +bit 03_301 +bit 03_302 +bit 03_304 +bit 03_305 +bit 03_306 +bit 03_308 +bit 03_309 +bit 03_310 +bit 03_312 +bit 03_313 +bit 03_314 +bit 03_316 +bit 03_317 +bit 03_318 +bit 03_32 +bit 03_33 +bit 03_34 +bit 03_36 +bit 03_37 +bit 03_38 +bit 03_40 +bit 03_41 +bit 03_42 +bit 03_44 +bit 03_45 +bit 03_46 +bit 03_48 +bit 03_49 +bit 03_50 +bit 03_52 +bit 03_53 +bit 03_54 +bit 03_56 +bit 03_57 +bit 03_58 +bit 03_60 +bit 03_61 +bit 03_62 +bit 03_64 +bit 03_65 +bit 03_66 +bit 03_68 +bit 03_69 +bit 03_70 +bit 03_72 +bit 03_73 +bit 03_74 +bit 03_76 +bit 03_77 +bit 03_78 +bit 03_80 +bit 03_81 +bit 03_82 +bit 03_84 +bit 03_85 +bit 03_86 +bit 03_88 +bit 03_89 +bit 03_90 +bit 03_92 +bit 03_93 +bit 03_94 +bit 03_96 +bit 03_97 +bit 03_98 +bit 04_00 +bit 04_01 +bit 04_02 +bit 04_03 +bit 04_04 +bit 04_05 +bit 04_06 +bit 04_07 +bit 04_08 +bit 04_09 +bit 04_10 +bit 04_100 +bit 04_101 +bit 04_102 +bit 04_103 +bit 04_104 +bit 04_105 +bit 04_106 +bit 04_107 +bit 04_108 +bit 04_109 +bit 04_11 +bit 04_110 +bit 04_111 +bit 04_112 +bit 04_113 +bit 04_114 +bit 04_115 +bit 04_116 +bit 04_117 +bit 04_118 +bit 04_119 +bit 04_12 +bit 04_120 +bit 04_121 +bit 04_122 +bit 04_123 +bit 04_124 +bit 04_125 +bit 04_126 +bit 04_127 +bit 04_128 +bit 04_129 +bit 04_13 +bit 04_130 +bit 04_131 +bit 04_132 +bit 04_133 +bit 04_134 +bit 04_135 +bit 04_136 +bit 04_137 +bit 04_138 +bit 04_139 +bit 04_14 +bit 04_140 +bit 04_141 +bit 04_142 +bit 04_143 +bit 04_144 +bit 04_145 +bit 04_146 +bit 04_147 +bit 04_148 +bit 04_149 +bit 04_15 +bit 04_150 +bit 04_151 +bit 04_152 +bit 04_153 +bit 04_154 +bit 04_155 +bit 04_156 +bit 04_157 +bit 04_158 +bit 04_159 +bit 04_16 +bit 04_160 +bit 04_161 +bit 04_162 +bit 04_163 +bit 04_164 +bit 04_165 +bit 04_166 +bit 04_167 +bit 04_168 +bit 04_169 +bit 04_17 +bit 04_170 +bit 04_171 +bit 04_172 +bit 04_173 +bit 04_174 +bit 04_175 +bit 04_176 +bit 04_177 +bit 04_178 +bit 04_179 +bit 04_18 +bit 04_180 +bit 04_181 +bit 04_182 +bit 04_183 +bit 04_184 +bit 04_185 +bit 04_186 +bit 04_187 +bit 04_188 +bit 04_189 +bit 04_19 +bit 04_190 +bit 04_191 +bit 04_192 +bit 04_193 +bit 04_194 +bit 04_195 +bit 04_196 +bit 04_197 +bit 04_198 +bit 04_199 +bit 04_20 +bit 04_200 +bit 04_201 +bit 04_202 +bit 04_203 +bit 04_204 +bit 04_205 +bit 04_206 +bit 04_207 +bit 04_208 +bit 04_209 +bit 04_21 +bit 04_210 +bit 04_211 +bit 04_212 +bit 04_213 +bit 04_214 +bit 04_215 +bit 04_216 +bit 04_217 +bit 04_218 +bit 04_219 +bit 04_22 +bit 04_220 +bit 04_221 +bit 04_222 +bit 04_223 +bit 04_224 +bit 04_225 +bit 04_226 +bit 04_227 +bit 04_228 +bit 04_229 +bit 04_23 +bit 04_230 +bit 04_231 +bit 04_232 +bit 04_233 +bit 04_234 +bit 04_235 +bit 04_236 +bit 04_237 +bit 04_238 +bit 04_239 +bit 04_24 +bit 04_240 +bit 04_241 +bit 04_242 +bit 04_243 +bit 04_244 +bit 04_245 +bit 04_246 +bit 04_247 +bit 04_248 +bit 04_249 +bit 04_25 +bit 04_250 +bit 04_251 +bit 04_252 +bit 04_253 +bit 04_254 +bit 04_255 +bit 04_256 +bit 04_257 +bit 04_258 +bit 04_259 +bit 04_26 +bit 04_260 +bit 04_261 +bit 04_262 +bit 04_263 +bit 04_264 +bit 04_265 +bit 04_266 +bit 04_267 +bit 04_268 +bit 04_269 +bit 04_27 +bit 04_270 +bit 04_271 +bit 04_272 +bit 04_273 +bit 04_274 +bit 04_275 +bit 04_276 +bit 04_277 +bit 04_278 +bit 04_279 +bit 04_28 +bit 04_280 +bit 04_281 +bit 04_282 +bit 04_283 +bit 04_284 +bit 04_285 +bit 04_286 +bit 04_287 +bit 04_288 +bit 04_289 +bit 04_29 +bit 04_290 +bit 04_291 +bit 04_292 +bit 04_293 +bit 04_294 +bit 04_295 +bit 04_296 +bit 04_297 +bit 04_298 +bit 04_299 +bit 04_30 +bit 04_300 +bit 04_301 +bit 04_302 +bit 04_303 +bit 04_304 +bit 04_305 +bit 04_306 +bit 04_307 +bit 04_308 +bit 04_309 +bit 04_31 +bit 04_310 +bit 04_311 +bit 04_312 +bit 04_313 +bit 04_314 +bit 04_315 +bit 04_316 +bit 04_317 +bit 04_318 +bit 04_319 +bit 04_32 +bit 04_33 +bit 04_34 +bit 04_35 +bit 04_36 +bit 04_37 +bit 04_38 +bit 04_39 +bit 04_40 +bit 04_41 +bit 04_42 +bit 04_43 +bit 04_44 +bit 04_45 +bit 04_46 +bit 04_47 +bit 04_48 +bit 04_49 +bit 04_50 +bit 04_51 +bit 04_52 +bit 04_53 +bit 04_54 +bit 04_55 +bit 04_56 +bit 04_57 +bit 04_58 +bit 04_59 +bit 04_60 +bit 04_61 +bit 04_62 +bit 04_63 +bit 04_64 +bit 04_65 +bit 04_66 +bit 04_67 +bit 04_68 +bit 04_69 +bit 04_70 +bit 04_71 +bit 04_72 +bit 04_73 +bit 04_74 +bit 04_75 +bit 04_76 +bit 04_77 +bit 04_78 +bit 04_79 +bit 04_80 +bit 04_81 +bit 04_82 +bit 04_83 +bit 04_84 +bit 04_85 +bit 04_86 +bit 04_87 +bit 04_88 +bit 04_89 +bit 04_90 +bit 04_91 +bit 04_92 +bit 04_93 +bit 04_94 +bit 04_95 +bit 04_96 +bit 04_97 +bit 04_98 +bit 04_99 +bit 05_00 +bit 05_01 +bit 05_02 +bit 05_03 +bit 05_04 +bit 05_05 +bit 05_06 +bit 05_07 +bit 05_08 +bit 05_09 +bit 05_10 +bit 05_100 +bit 05_101 +bit 05_102 +bit 05_103 +bit 05_104 +bit 05_105 +bit 05_106 +bit 05_107 +bit 05_108 +bit 05_109 +bit 05_11 +bit 05_110 +bit 05_111 +bit 05_112 +bit 05_113 +bit 05_114 +bit 05_115 +bit 05_116 +bit 05_117 +bit 05_118 +bit 05_119 +bit 05_12 +bit 05_120 +bit 05_121 +bit 05_122 +bit 05_123 +bit 05_124 +bit 05_125 +bit 05_126 +bit 05_127 +bit 05_128 +bit 05_129 +bit 05_13 +bit 05_130 +bit 05_131 +bit 05_132 +bit 05_133 +bit 05_134 +bit 05_135 +bit 05_136 +bit 05_137 +bit 05_138 +bit 05_139 +bit 05_14 +bit 05_140 +bit 05_141 +bit 05_142 +bit 05_143 +bit 05_144 +bit 05_145 +bit 05_146 +bit 05_147 +bit 05_148 +bit 05_149 +bit 05_15 +bit 05_150 +bit 05_151 +bit 05_152 +bit 05_153 +bit 05_154 +bit 05_155 +bit 05_156 +bit 05_157 +bit 05_158 +bit 05_159 +bit 05_16 +bit 05_160 +bit 05_161 +bit 05_162 +bit 05_163 +bit 05_164 +bit 05_165 +bit 05_166 +bit 05_167 +bit 05_168 +bit 05_169 +bit 05_17 +bit 05_170 +bit 05_171 +bit 05_172 +bit 05_173 +bit 05_174 +bit 05_175 +bit 05_176 +bit 05_177 +bit 05_178 +bit 05_179 +bit 05_18 +bit 05_180 +bit 05_181 +bit 05_182 +bit 05_183 +bit 05_184 +bit 05_185 +bit 05_186 +bit 05_187 +bit 05_188 +bit 05_189 +bit 05_19 +bit 05_190 +bit 05_191 +bit 05_192 +bit 05_193 +bit 05_194 +bit 05_195 +bit 05_196 +bit 05_197 +bit 05_198 +bit 05_199 +bit 05_20 +bit 05_200 +bit 05_201 +bit 05_202 +bit 05_203 +bit 05_204 +bit 05_205 +bit 05_206 +bit 05_207 +bit 05_208 +bit 05_209 +bit 05_21 +bit 05_210 +bit 05_211 +bit 05_212 +bit 05_213 +bit 05_214 +bit 05_215 +bit 05_216 +bit 05_217 +bit 05_218 +bit 05_219 +bit 05_22 +bit 05_220 +bit 05_221 +bit 05_222 +bit 05_223 +bit 05_224 +bit 05_225 +bit 05_226 +bit 05_227 +bit 05_228 +bit 05_229 +bit 05_23 +bit 05_230 +bit 05_231 +bit 05_232 +bit 05_233 +bit 05_234 +bit 05_235 +bit 05_236 +bit 05_237 +bit 05_238 +bit 05_239 +bit 05_24 +bit 05_240 +bit 05_241 +bit 05_242 +bit 05_243 +bit 05_244 +bit 05_245 +bit 05_246 +bit 05_247 +bit 05_248 +bit 05_249 +bit 05_25 +bit 05_250 +bit 05_251 +bit 05_252 +bit 05_253 +bit 05_254 +bit 05_255 +bit 05_256 +bit 05_257 +bit 05_258 +bit 05_259 +bit 05_26 +bit 05_260 +bit 05_261 +bit 05_262 +bit 05_263 +bit 05_264 +bit 05_265 +bit 05_266 +bit 05_267 +bit 05_268 +bit 05_269 +bit 05_27 +bit 05_270 +bit 05_271 +bit 05_272 +bit 05_273 +bit 05_274 +bit 05_275 +bit 05_276 +bit 05_277 +bit 05_278 +bit 05_279 +bit 05_28 +bit 05_280 +bit 05_281 +bit 05_282 +bit 05_283 +bit 05_284 +bit 05_285 +bit 05_286 +bit 05_287 +bit 05_288 +bit 05_289 +bit 05_29 +bit 05_290 +bit 05_291 +bit 05_292 +bit 05_293 +bit 05_294 +bit 05_295 +bit 05_296 +bit 05_297 +bit 05_298 +bit 05_299 +bit 05_30 +bit 05_300 +bit 05_301 +bit 05_302 +bit 05_303 +bit 05_304 +bit 05_305 +bit 05_306 +bit 05_307 +bit 05_308 +bit 05_309 +bit 05_31 +bit 05_310 +bit 05_311 +bit 05_312 +bit 05_313 +bit 05_314 +bit 05_315 +bit 05_316 +bit 05_317 +bit 05_318 +bit 05_319 +bit 05_32 +bit 05_33 +bit 05_34 +bit 05_35 +bit 05_36 +bit 05_37 +bit 05_38 +bit 05_39 +bit 05_40 +bit 05_41 +bit 05_42 +bit 05_43 +bit 05_44 +bit 05_45 +bit 05_46 +bit 05_47 +bit 05_48 +bit 05_49 +bit 05_50 +bit 05_51 +bit 05_52 +bit 05_53 +bit 05_54 +bit 05_55 +bit 05_56 +bit 05_57 +bit 05_58 +bit 05_59 +bit 05_60 +bit 05_61 +bit 05_62 +bit 05_63 +bit 05_64 +bit 05_65 +bit 05_66 +bit 05_67 +bit 05_68 +bit 05_69 +bit 05_70 +bit 05_71 +bit 05_72 +bit 05_73 +bit 05_74 +bit 05_75 +bit 05_76 +bit 05_77 +bit 05_78 +bit 05_79 +bit 05_80 +bit 05_81 +bit 05_82 +bit 05_83 +bit 05_84 +bit 05_85 +bit 05_86 +bit 05_87 +bit 05_88 +bit 05_89 +bit 05_90 +bit 05_91 +bit 05_92 +bit 05_93 +bit 05_94 +bit 05_95 +bit 05_96 +bit 05_97 +bit 05_98 +bit 05_99 +bit 06_00 +bit 06_01 +bit 06_02 +bit 06_03 +bit 06_04 +bit 06_05 +bit 06_06 +bit 06_07 +bit 06_08 +bit 06_09 +bit 06_10 +bit 06_100 +bit 06_101 +bit 06_102 +bit 06_103 +bit 06_104 +bit 06_105 +bit 06_106 +bit 06_107 +bit 06_108 +bit 06_109 +bit 06_11 +bit 06_110 +bit 06_111 +bit 06_112 +bit 06_113 +bit 06_114 +bit 06_115 +bit 06_116 +bit 06_117 +bit 06_118 +bit 06_119 +bit 06_12 +bit 06_120 +bit 06_121 +bit 06_122 +bit 06_123 +bit 06_124 +bit 06_125 +bit 06_126 +bit 06_127 +bit 06_128 +bit 06_129 +bit 06_13 +bit 06_130 +bit 06_131 +bit 06_132 +bit 06_133 +bit 06_134 +bit 06_135 +bit 06_136 +bit 06_137 +bit 06_138 +bit 06_139 +bit 06_14 +bit 06_140 +bit 06_141 +bit 06_142 +bit 06_143 +bit 06_144 +bit 06_145 +bit 06_146 +bit 06_147 +bit 06_148 +bit 06_149 +bit 06_15 +bit 06_150 +bit 06_151 +bit 06_152 +bit 06_153 +bit 06_154 +bit 06_155 +bit 06_156 +bit 06_157 +bit 06_158 +bit 06_159 +bit 06_16 +bit 06_160 +bit 06_161 +bit 06_162 +bit 06_163 +bit 06_164 +bit 06_165 +bit 06_166 +bit 06_167 +bit 06_168 +bit 06_169 +bit 06_17 +bit 06_170 +bit 06_171 +bit 06_172 +bit 06_173 +bit 06_174 +bit 06_175 +bit 06_176 +bit 06_177 +bit 06_178 +bit 06_179 +bit 06_18 +bit 06_180 +bit 06_181 +bit 06_182 +bit 06_183 +bit 06_184 +bit 06_185 +bit 06_186 +bit 06_187 +bit 06_188 +bit 06_189 +bit 06_19 +bit 06_190 +bit 06_191 +bit 06_192 +bit 06_193 +bit 06_194 +bit 06_195 +bit 06_196 +bit 06_197 +bit 06_198 +bit 06_199 +bit 06_20 +bit 06_200 +bit 06_201 +bit 06_202 +bit 06_203 +bit 06_204 +bit 06_205 +bit 06_206 +bit 06_207 +bit 06_208 +bit 06_209 +bit 06_21 +bit 06_210 +bit 06_211 +bit 06_212 +bit 06_213 +bit 06_214 +bit 06_215 +bit 06_216 +bit 06_217 +bit 06_218 +bit 06_219 +bit 06_22 +bit 06_220 +bit 06_221 +bit 06_222 +bit 06_223 +bit 06_224 +bit 06_225 +bit 06_226 +bit 06_227 +bit 06_228 +bit 06_229 +bit 06_23 +bit 06_230 +bit 06_231 +bit 06_232 +bit 06_233 +bit 06_234 +bit 06_235 +bit 06_236 +bit 06_237 +bit 06_238 +bit 06_239 +bit 06_24 +bit 06_240 +bit 06_241 +bit 06_242 +bit 06_243 +bit 06_244 +bit 06_245 +bit 06_246 +bit 06_247 +bit 06_248 +bit 06_249 +bit 06_25 +bit 06_250 +bit 06_251 +bit 06_252 +bit 06_253 +bit 06_254 +bit 06_255 +bit 06_256 +bit 06_257 +bit 06_258 +bit 06_259 +bit 06_26 +bit 06_260 +bit 06_261 +bit 06_262 +bit 06_263 +bit 06_264 +bit 06_265 +bit 06_266 +bit 06_267 +bit 06_268 +bit 06_269 +bit 06_27 +bit 06_270 +bit 06_271 +bit 06_272 +bit 06_273 +bit 06_274 +bit 06_275 +bit 06_276 +bit 06_277 +bit 06_278 +bit 06_279 +bit 06_28 +bit 06_280 +bit 06_281 +bit 06_282 +bit 06_283 +bit 06_284 +bit 06_285 +bit 06_286 +bit 06_287 +bit 06_288 +bit 06_289 +bit 06_29 +bit 06_290 +bit 06_291 +bit 06_292 +bit 06_293 +bit 06_294 +bit 06_295 +bit 06_296 +bit 06_297 +bit 06_298 +bit 06_299 +bit 06_30 +bit 06_300 +bit 06_301 +bit 06_302 +bit 06_303 +bit 06_304 +bit 06_305 +bit 06_306 +bit 06_307 +bit 06_308 +bit 06_309 +bit 06_31 +bit 06_310 +bit 06_311 +bit 06_312 +bit 06_313 +bit 06_314 +bit 06_315 +bit 06_316 +bit 06_317 +bit 06_318 +bit 06_319 +bit 06_32 +bit 06_33 +bit 06_34 +bit 06_35 +bit 06_36 +bit 06_37 +bit 06_38 +bit 06_39 +bit 06_40 +bit 06_41 +bit 06_42 +bit 06_43 +bit 06_44 +bit 06_45 +bit 06_46 +bit 06_47 +bit 06_48 +bit 06_49 +bit 06_50 +bit 06_51 +bit 06_52 +bit 06_53 +bit 06_54 +bit 06_55 +bit 06_56 +bit 06_57 +bit 06_58 +bit 06_59 +bit 06_60 +bit 06_61 +bit 06_62 +bit 06_63 +bit 06_64 +bit 06_65 +bit 06_66 +bit 06_67 +bit 06_68 +bit 06_69 +bit 06_70 +bit 06_71 +bit 06_72 +bit 06_73 +bit 06_74 +bit 06_75 +bit 06_76 +bit 06_77 +bit 06_78 +bit 06_79 +bit 06_80 +bit 06_81 +bit 06_82 +bit 06_83 +bit 06_84 +bit 06_85 +bit 06_86 +bit 06_87 +bit 06_88 +bit 06_89 +bit 06_90 +bit 06_91 +bit 06_92 +bit 06_93 +bit 06_94 +bit 06_95 +bit 06_96 +bit 06_97 +bit 06_98 +bit 06_99 +bit 07_00 +bit 07_01 +bit 07_02 +bit 07_03 +bit 07_04 +bit 07_05 +bit 07_06 +bit 07_07 +bit 07_08 +bit 07_09 +bit 07_10 +bit 07_100 +bit 07_101 +bit 07_102 +bit 07_103 +bit 07_104 +bit 07_105 +bit 07_106 +bit 07_107 +bit 07_108 +bit 07_109 +bit 07_11 +bit 07_110 +bit 07_111 +bit 07_112 +bit 07_113 +bit 07_114 +bit 07_115 +bit 07_116 +bit 07_117 +bit 07_118 +bit 07_119 +bit 07_12 +bit 07_120 +bit 07_121 +bit 07_122 +bit 07_123 +bit 07_124 +bit 07_125 +bit 07_126 +bit 07_127 +bit 07_128 +bit 07_129 +bit 07_13 +bit 07_130 +bit 07_131 +bit 07_132 +bit 07_133 +bit 07_134 +bit 07_135 +bit 07_136 +bit 07_137 +bit 07_138 +bit 07_139 +bit 07_14 +bit 07_140 +bit 07_141 +bit 07_142 +bit 07_143 +bit 07_144 +bit 07_145 +bit 07_146 +bit 07_147 +bit 07_148 +bit 07_149 +bit 07_15 +bit 07_150 +bit 07_151 +bit 07_152 +bit 07_153 +bit 07_154 +bit 07_155 +bit 07_156 +bit 07_157 +bit 07_158 +bit 07_159 +bit 07_16 +bit 07_160 +bit 07_161 +bit 07_162 +bit 07_163 +bit 07_164 +bit 07_165 +bit 07_166 +bit 07_167 +bit 07_168 +bit 07_169 +bit 07_17 +bit 07_170 +bit 07_171 +bit 07_172 +bit 07_173 +bit 07_174 +bit 07_175 +bit 07_176 +bit 07_177 +bit 07_178 +bit 07_179 +bit 07_18 +bit 07_180 +bit 07_181 +bit 07_182 +bit 07_183 +bit 07_184 +bit 07_185 +bit 07_186 +bit 07_187 +bit 07_188 +bit 07_189 +bit 07_19 +bit 07_190 +bit 07_191 +bit 07_192 +bit 07_193 +bit 07_194 +bit 07_195 +bit 07_196 +bit 07_197 +bit 07_198 +bit 07_199 +bit 07_20 +bit 07_200 +bit 07_201 +bit 07_202 +bit 07_203 +bit 07_204 +bit 07_205 +bit 07_206 +bit 07_207 +bit 07_208 +bit 07_209 +bit 07_21 +bit 07_210 +bit 07_211 +bit 07_212 +bit 07_213 +bit 07_214 +bit 07_215 +bit 07_216 +bit 07_217 +bit 07_218 +bit 07_219 +bit 07_22 +bit 07_220 +bit 07_221 +bit 07_222 +bit 07_223 +bit 07_224 +bit 07_225 +bit 07_226 +bit 07_227 +bit 07_228 +bit 07_229 +bit 07_23 +bit 07_230 +bit 07_231 +bit 07_232 +bit 07_233 +bit 07_234 +bit 07_235 +bit 07_236 +bit 07_237 +bit 07_238 +bit 07_239 +bit 07_24 +bit 07_240 +bit 07_241 +bit 07_242 +bit 07_243 +bit 07_244 +bit 07_245 +bit 07_246 +bit 07_247 +bit 07_248 +bit 07_249 +bit 07_25 +bit 07_250 +bit 07_251 +bit 07_252 +bit 07_253 +bit 07_254 +bit 07_255 +bit 07_256 +bit 07_257 +bit 07_258 +bit 07_259 +bit 07_26 +bit 07_260 +bit 07_261 +bit 07_262 +bit 07_263 +bit 07_264 +bit 07_265 +bit 07_266 +bit 07_267 +bit 07_268 +bit 07_269 +bit 07_27 +bit 07_270 +bit 07_271 +bit 07_272 +bit 07_273 +bit 07_274 +bit 07_275 +bit 07_276 +bit 07_277 +bit 07_278 +bit 07_279 +bit 07_28 +bit 07_280 +bit 07_281 +bit 07_282 +bit 07_283 +bit 07_284 +bit 07_285 +bit 07_286 +bit 07_287 +bit 07_288 +bit 07_289 +bit 07_29 +bit 07_290 +bit 07_291 +bit 07_292 +bit 07_293 +bit 07_294 +bit 07_295 +bit 07_296 +bit 07_297 +bit 07_298 +bit 07_299 +bit 07_30 +bit 07_300 +bit 07_301 +bit 07_302 +bit 07_303 +bit 07_304 +bit 07_305 +bit 07_306 +bit 07_307 +bit 07_308 +bit 07_309 +bit 07_31 +bit 07_310 +bit 07_311 +bit 07_312 +bit 07_313 +bit 07_314 +bit 07_315 +bit 07_316 +bit 07_317 +bit 07_318 +bit 07_319 +bit 07_32 +bit 07_33 +bit 07_34 +bit 07_35 +bit 07_36 +bit 07_37 +bit 07_38 +bit 07_39 +bit 07_40 +bit 07_41 +bit 07_42 +bit 07_43 +bit 07_44 +bit 07_45 +bit 07_46 +bit 07_47 +bit 07_48 +bit 07_49 +bit 07_50 +bit 07_51 +bit 07_52 +bit 07_53 +bit 07_54 +bit 07_55 +bit 07_56 +bit 07_57 +bit 07_58 +bit 07_59 +bit 07_60 +bit 07_61 +bit 07_62 +bit 07_63 +bit 07_64 +bit 07_65 +bit 07_66 +bit 07_67 +bit 07_68 +bit 07_69 +bit 07_70 +bit 07_71 +bit 07_72 +bit 07_73 +bit 07_74 +bit 07_75 +bit 07_76 +bit 07_77 +bit 07_78 +bit 07_79 +bit 07_80 +bit 07_81 +bit 07_82 +bit 07_83 +bit 07_84 +bit 07_85 +bit 07_86 +bit 07_87 +bit 07_88 +bit 07_89 +bit 07_90 +bit 07_91 +bit 07_92 +bit 07_93 +bit 07_94 +bit 07_95 +bit 07_96 +bit 07_97 +bit 07_98 +bit 07_99 +bit 08_00 +bit 08_01 +bit 08_02 +bit 08_03 +bit 08_04 +bit 08_05 +bit 08_06 +bit 08_07 +bit 08_08 +bit 08_09 +bit 08_10 +bit 08_100 +bit 08_101 +bit 08_102 +bit 08_103 +bit 08_104 +bit 08_105 +bit 08_106 +bit 08_107 +bit 08_108 +bit 08_109 +bit 08_11 +bit 08_110 +bit 08_111 +bit 08_112 +bit 08_113 +bit 08_114 +bit 08_115 +bit 08_116 +bit 08_117 +bit 08_118 +bit 08_119 +bit 08_12 +bit 08_120 +bit 08_121 +bit 08_122 +bit 08_123 +bit 08_124 +bit 08_125 +bit 08_126 +bit 08_127 +bit 08_128 +bit 08_129 +bit 08_13 +bit 08_130 +bit 08_131 +bit 08_132 +bit 08_133 +bit 08_134 +bit 08_135 +bit 08_136 +bit 08_137 +bit 08_138 +bit 08_139 +bit 08_14 +bit 08_140 +bit 08_141 +bit 08_142 +bit 08_143 +bit 08_144 +bit 08_145 +bit 08_146 +bit 08_147 +bit 08_148 +bit 08_149 +bit 08_15 +bit 08_150 +bit 08_151 +bit 08_152 +bit 08_153 +bit 08_154 +bit 08_155 +bit 08_156 +bit 08_157 +bit 08_158 +bit 08_159 +bit 08_16 +bit 08_160 +bit 08_161 +bit 08_162 +bit 08_163 +bit 08_164 +bit 08_165 +bit 08_166 +bit 08_167 +bit 08_168 +bit 08_169 +bit 08_17 +bit 08_170 +bit 08_171 +bit 08_172 +bit 08_173 +bit 08_174 +bit 08_175 +bit 08_176 +bit 08_177 +bit 08_178 +bit 08_179 +bit 08_18 +bit 08_180 +bit 08_181 +bit 08_182 +bit 08_183 +bit 08_184 +bit 08_185 +bit 08_186 +bit 08_187 +bit 08_188 +bit 08_189 +bit 08_19 +bit 08_190 +bit 08_191 +bit 08_192 +bit 08_193 +bit 08_194 +bit 08_195 +bit 08_196 +bit 08_197 +bit 08_198 +bit 08_199 +bit 08_20 +bit 08_200 +bit 08_201 +bit 08_202 +bit 08_203 +bit 08_204 +bit 08_205 +bit 08_206 +bit 08_207 +bit 08_208 +bit 08_209 +bit 08_21 +bit 08_210 +bit 08_211 +bit 08_212 +bit 08_213 +bit 08_214 +bit 08_215 +bit 08_216 +bit 08_217 +bit 08_218 +bit 08_219 +bit 08_22 +bit 08_220 +bit 08_221 +bit 08_222 +bit 08_223 +bit 08_224 +bit 08_225 +bit 08_226 +bit 08_227 +bit 08_228 +bit 08_229 +bit 08_23 +bit 08_230 +bit 08_231 +bit 08_232 +bit 08_233 +bit 08_234 +bit 08_235 +bit 08_236 +bit 08_237 +bit 08_238 +bit 08_239 +bit 08_24 +bit 08_240 +bit 08_241 +bit 08_242 +bit 08_243 +bit 08_244 +bit 08_245 +bit 08_246 +bit 08_247 +bit 08_248 +bit 08_249 +bit 08_25 +bit 08_250 +bit 08_251 +bit 08_252 +bit 08_253 +bit 08_254 +bit 08_255 +bit 08_256 +bit 08_257 +bit 08_258 +bit 08_259 +bit 08_26 +bit 08_260 +bit 08_261 +bit 08_262 +bit 08_263 +bit 08_264 +bit 08_265 +bit 08_266 +bit 08_267 +bit 08_268 +bit 08_269 +bit 08_27 +bit 08_270 +bit 08_271 +bit 08_272 +bit 08_273 +bit 08_274 +bit 08_275 +bit 08_276 +bit 08_277 +bit 08_278 +bit 08_279 +bit 08_28 +bit 08_280 +bit 08_281 +bit 08_282 +bit 08_283 +bit 08_284 +bit 08_285 +bit 08_286 +bit 08_287 +bit 08_288 +bit 08_289 +bit 08_29 +bit 08_290 +bit 08_291 +bit 08_292 +bit 08_293 +bit 08_294 +bit 08_295 +bit 08_296 +bit 08_297 +bit 08_298 +bit 08_299 +bit 08_30 +bit 08_300 +bit 08_301 +bit 08_302 +bit 08_303 +bit 08_304 +bit 08_305 +bit 08_306 +bit 08_307 +bit 08_308 +bit 08_309 +bit 08_31 +bit 08_310 +bit 08_311 +bit 08_312 +bit 08_313 +bit 08_314 +bit 08_315 +bit 08_316 +bit 08_317 +bit 08_318 +bit 08_319 +bit 08_32 +bit 08_33 +bit 08_34 +bit 08_35 +bit 08_36 +bit 08_37 +bit 08_38 +bit 08_39 +bit 08_40 +bit 08_41 +bit 08_42 +bit 08_43 +bit 08_44 +bit 08_45 +bit 08_46 +bit 08_47 +bit 08_48 +bit 08_49 +bit 08_50 +bit 08_51 +bit 08_52 +bit 08_53 +bit 08_54 +bit 08_55 +bit 08_56 +bit 08_57 +bit 08_58 +bit 08_59 +bit 08_60 +bit 08_61 +bit 08_62 +bit 08_63 +bit 08_64 +bit 08_65 +bit 08_66 +bit 08_67 +bit 08_68 +bit 08_69 +bit 08_70 +bit 08_71 +bit 08_72 +bit 08_73 +bit 08_74 +bit 08_75 +bit 08_76 +bit 08_77 +bit 08_78 +bit 08_79 +bit 08_80 +bit 08_81 +bit 08_82 +bit 08_83 +bit 08_84 +bit 08_85 +bit 08_86 +bit 08_87 +bit 08_88 +bit 08_89 +bit 08_90 +bit 08_91 +bit 08_92 +bit 08_93 +bit 08_94 +bit 08_95 +bit 08_96 +bit 08_97 +bit 08_98 +bit 08_99 +bit 09_00 +bit 09_01 +bit 09_02 +bit 09_03 +bit 09_04 +bit 09_05 +bit 09_06 +bit 09_07 +bit 09_08 +bit 09_09 +bit 09_10 +bit 09_100 +bit 09_101 +bit 09_102 +bit 09_103 +bit 09_104 +bit 09_105 +bit 09_106 +bit 09_107 +bit 09_108 +bit 09_109 +bit 09_11 +bit 09_110 +bit 09_111 +bit 09_112 +bit 09_113 +bit 09_114 +bit 09_115 +bit 09_116 +bit 09_117 +bit 09_118 +bit 09_119 +bit 09_12 +bit 09_120 +bit 09_121 +bit 09_122 +bit 09_123 +bit 09_124 +bit 09_125 +bit 09_126 +bit 09_127 +bit 09_128 +bit 09_129 +bit 09_13 +bit 09_130 +bit 09_131 +bit 09_132 +bit 09_133 +bit 09_134 +bit 09_135 +bit 09_136 +bit 09_137 +bit 09_138 +bit 09_139 +bit 09_14 +bit 09_140 +bit 09_141 +bit 09_142 +bit 09_143 +bit 09_144 +bit 09_145 +bit 09_146 +bit 09_147 +bit 09_148 +bit 09_149 +bit 09_15 +bit 09_150 +bit 09_151 +bit 09_152 +bit 09_153 +bit 09_154 +bit 09_155 +bit 09_156 +bit 09_157 +bit 09_158 +bit 09_159 +bit 09_16 +bit 09_160 +bit 09_161 +bit 09_162 +bit 09_163 +bit 09_164 +bit 09_165 +bit 09_166 +bit 09_167 +bit 09_168 +bit 09_169 +bit 09_17 +bit 09_170 +bit 09_171 +bit 09_172 +bit 09_173 +bit 09_174 +bit 09_175 +bit 09_176 +bit 09_177 +bit 09_178 +bit 09_179 +bit 09_18 +bit 09_180 +bit 09_181 +bit 09_182 +bit 09_183 +bit 09_184 +bit 09_185 +bit 09_186 +bit 09_187 +bit 09_188 +bit 09_189 +bit 09_19 +bit 09_190 +bit 09_191 +bit 09_192 +bit 09_193 +bit 09_194 +bit 09_195 +bit 09_196 +bit 09_197 +bit 09_198 +bit 09_199 +bit 09_20 +bit 09_200 +bit 09_201 +bit 09_202 +bit 09_203 +bit 09_204 +bit 09_205 +bit 09_206 +bit 09_207 +bit 09_208 +bit 09_209 +bit 09_21 +bit 09_210 +bit 09_211 +bit 09_212 +bit 09_213 +bit 09_214 +bit 09_215 +bit 09_216 +bit 09_217 +bit 09_218 +bit 09_219 +bit 09_22 +bit 09_220 +bit 09_221 +bit 09_222 +bit 09_223 +bit 09_224 +bit 09_225 +bit 09_226 +bit 09_227 +bit 09_228 +bit 09_229 +bit 09_23 +bit 09_230 +bit 09_231 +bit 09_232 +bit 09_233 +bit 09_234 +bit 09_235 +bit 09_236 +bit 09_237 +bit 09_238 +bit 09_239 +bit 09_24 +bit 09_240 +bit 09_241 +bit 09_242 +bit 09_243 +bit 09_244 +bit 09_245 +bit 09_246 +bit 09_247 +bit 09_248 +bit 09_249 +bit 09_25 +bit 09_250 +bit 09_251 +bit 09_252 +bit 09_253 +bit 09_254 +bit 09_255 +bit 09_256 +bit 09_257 +bit 09_258 +bit 09_259 +bit 09_26 +bit 09_260 +bit 09_261 +bit 09_262 +bit 09_263 +bit 09_264 +bit 09_265 +bit 09_266 +bit 09_267 +bit 09_268 +bit 09_269 +bit 09_27 +bit 09_270 +bit 09_271 +bit 09_272 +bit 09_273 +bit 09_274 +bit 09_275 +bit 09_276 +bit 09_277 +bit 09_278 +bit 09_279 +bit 09_28 +bit 09_280 +bit 09_281 +bit 09_282 +bit 09_283 +bit 09_284 +bit 09_285 +bit 09_286 +bit 09_287 +bit 09_288 +bit 09_289 +bit 09_29 +bit 09_290 +bit 09_291 +bit 09_292 +bit 09_293 +bit 09_294 +bit 09_295 +bit 09_296 +bit 09_297 +bit 09_298 +bit 09_299 +bit 09_30 +bit 09_300 +bit 09_301 +bit 09_302 +bit 09_303 +bit 09_304 +bit 09_305 +bit 09_306 +bit 09_307 +bit 09_308 +bit 09_309 +bit 09_31 +bit 09_310 +bit 09_311 +bit 09_312 +bit 09_313 +bit 09_314 +bit 09_315 +bit 09_316 +bit 09_317 +bit 09_318 +bit 09_319 +bit 09_32 +bit 09_33 +bit 09_34 +bit 09_35 +bit 09_36 +bit 09_37 +bit 09_38 +bit 09_39 +bit 09_40 +bit 09_41 +bit 09_42 +bit 09_43 +bit 09_44 +bit 09_45 +bit 09_46 +bit 09_47 +bit 09_48 +bit 09_49 +bit 09_50 +bit 09_51 +bit 09_52 +bit 09_53 +bit 09_54 +bit 09_55 +bit 09_56 +bit 09_57 +bit 09_58 +bit 09_59 +bit 09_60 +bit 09_61 +bit 09_62 +bit 09_63 +bit 09_64 +bit 09_65 +bit 09_66 +bit 09_67 +bit 09_68 +bit 09_69 +bit 09_70 +bit 09_71 +bit 09_72 +bit 09_73 +bit 09_74 +bit 09_75 +bit 09_76 +bit 09_77 +bit 09_78 +bit 09_79 +bit 09_80 +bit 09_81 +bit 09_82 +bit 09_83 +bit 09_84 +bit 09_85 +bit 09_86 +bit 09_87 +bit 09_88 +bit 09_89 +bit 09_90 +bit 09_91 +bit 09_92 +bit 09_93 +bit 09_94 +bit 09_95 +bit 09_96 +bit 09_97 +bit 09_98 +bit 09_99 +bit 10_00 +bit 10_01 +bit 10_02 +bit 10_03 +bit 10_04 +bit 10_05 +bit 10_06 +bit 10_07 +bit 10_08 +bit 10_09 +bit 10_10 +bit 10_100 +bit 10_101 +bit 10_102 +bit 10_103 +bit 10_104 +bit 10_105 +bit 10_106 +bit 10_107 +bit 10_108 +bit 10_109 +bit 10_11 +bit 10_110 +bit 10_111 +bit 10_112 +bit 10_113 +bit 10_114 +bit 10_115 +bit 10_116 +bit 10_117 +bit 10_118 +bit 10_119 +bit 10_12 +bit 10_120 +bit 10_121 +bit 10_122 +bit 10_123 +bit 10_124 +bit 10_125 +bit 10_126 +bit 10_127 +bit 10_128 +bit 10_129 +bit 10_13 +bit 10_130 +bit 10_131 +bit 10_132 +bit 10_133 +bit 10_134 +bit 10_135 +bit 10_136 +bit 10_137 +bit 10_138 +bit 10_139 +bit 10_14 +bit 10_140 +bit 10_141 +bit 10_142 +bit 10_143 +bit 10_144 +bit 10_145 +bit 10_146 +bit 10_147 +bit 10_148 +bit 10_149 +bit 10_15 +bit 10_150 +bit 10_151 +bit 10_152 +bit 10_153 +bit 10_154 +bit 10_155 +bit 10_156 +bit 10_157 +bit 10_158 +bit 10_159 +bit 10_16 +bit 10_160 +bit 10_161 +bit 10_162 +bit 10_163 +bit 10_164 +bit 10_165 +bit 10_166 +bit 10_167 +bit 10_168 +bit 10_169 +bit 10_17 +bit 10_170 +bit 10_171 +bit 10_172 +bit 10_173 +bit 10_174 +bit 10_175 +bit 10_176 +bit 10_177 +bit 10_178 +bit 10_179 +bit 10_18 +bit 10_180 +bit 10_181 +bit 10_182 +bit 10_183 +bit 10_184 +bit 10_185 +bit 10_186 +bit 10_187 +bit 10_188 +bit 10_189 +bit 10_19 +bit 10_190 +bit 10_191 +bit 10_192 +bit 10_193 +bit 10_194 +bit 10_195 +bit 10_196 +bit 10_197 +bit 10_198 +bit 10_199 +bit 10_20 +bit 10_200 +bit 10_201 +bit 10_202 +bit 10_203 +bit 10_204 +bit 10_205 +bit 10_206 +bit 10_207 +bit 10_208 +bit 10_209 +bit 10_21 +bit 10_210 +bit 10_211 +bit 10_212 +bit 10_213 +bit 10_214 +bit 10_215 +bit 10_216 +bit 10_217 +bit 10_218 +bit 10_219 +bit 10_22 +bit 10_220 +bit 10_221 +bit 10_222 +bit 10_223 +bit 10_224 +bit 10_225 +bit 10_226 +bit 10_227 +bit 10_228 +bit 10_229 +bit 10_23 +bit 10_230 +bit 10_231 +bit 10_232 +bit 10_233 +bit 10_234 +bit 10_235 +bit 10_236 +bit 10_237 +bit 10_238 +bit 10_239 +bit 10_24 +bit 10_240 +bit 10_241 +bit 10_242 +bit 10_243 +bit 10_244 +bit 10_245 +bit 10_246 +bit 10_247 +bit 10_248 +bit 10_249 +bit 10_25 +bit 10_250 +bit 10_251 +bit 10_252 +bit 10_253 +bit 10_254 +bit 10_255 +bit 10_256 +bit 10_257 +bit 10_258 +bit 10_259 +bit 10_26 +bit 10_260 +bit 10_261 +bit 10_262 +bit 10_263 +bit 10_264 +bit 10_265 +bit 10_266 +bit 10_267 +bit 10_268 +bit 10_269 +bit 10_27 +bit 10_270 +bit 10_271 +bit 10_272 +bit 10_273 +bit 10_274 +bit 10_275 +bit 10_276 +bit 10_277 +bit 10_278 +bit 10_279 +bit 10_28 +bit 10_280 +bit 10_281 +bit 10_282 +bit 10_283 +bit 10_284 +bit 10_285 +bit 10_286 +bit 10_287 +bit 10_288 +bit 10_289 +bit 10_29 +bit 10_290 +bit 10_291 +bit 10_292 +bit 10_293 +bit 10_294 +bit 10_295 +bit 10_296 +bit 10_297 +bit 10_298 +bit 10_299 +bit 10_30 +bit 10_300 +bit 10_301 +bit 10_302 +bit 10_303 +bit 10_304 +bit 10_305 +bit 10_306 +bit 10_307 +bit 10_308 +bit 10_309 +bit 10_31 +bit 10_310 +bit 10_311 +bit 10_312 +bit 10_313 +bit 10_314 +bit 10_315 +bit 10_316 +bit 10_317 +bit 10_318 +bit 10_319 +bit 10_32 +bit 10_33 +bit 10_34 +bit 10_35 +bit 10_36 +bit 10_37 +bit 10_38 +bit 10_39 +bit 10_40 +bit 10_41 +bit 10_42 +bit 10_43 +bit 10_44 +bit 10_45 +bit 10_46 +bit 10_47 +bit 10_48 +bit 10_49 +bit 10_50 +bit 10_51 +bit 10_52 +bit 10_53 +bit 10_54 +bit 10_55 +bit 10_56 +bit 10_57 +bit 10_58 +bit 10_59 +bit 10_60 +bit 10_61 +bit 10_62 +bit 10_63 +bit 10_64 +bit 10_65 +bit 10_66 +bit 10_67 +bit 10_68 +bit 10_69 +bit 10_70 +bit 10_71 +bit 10_72 +bit 10_73 +bit 10_74 +bit 10_75 +bit 10_76 +bit 10_77 +bit 10_78 +bit 10_79 +bit 10_80 +bit 10_81 +bit 10_82 +bit 10_83 +bit 10_84 +bit 10_85 +bit 10_86 +bit 10_87 +bit 10_88 +bit 10_89 +bit 10_90 +bit 10_91 +bit 10_92 +bit 10_93 +bit 10_94 +bit 10_95 +bit 10_96 +bit 10_97 +bit 10_98 +bit 10_99 +bit 11_00 +bit 11_01 +bit 11_02 +bit 11_03 +bit 11_04 +bit 11_05 +bit 11_06 +bit 11_07 +bit 11_08 +bit 11_09 +bit 11_10 +bit 11_100 +bit 11_101 +bit 11_102 +bit 11_103 +bit 11_104 +bit 11_105 +bit 11_106 +bit 11_107 +bit 11_108 +bit 11_109 +bit 11_11 +bit 11_110 +bit 11_111 +bit 11_112 +bit 11_113 +bit 11_114 +bit 11_115 +bit 11_116 +bit 11_117 +bit 11_118 +bit 11_119 +bit 11_12 +bit 11_120 +bit 11_121 +bit 11_122 +bit 11_123 +bit 11_124 +bit 11_125 +bit 11_126 +bit 11_127 +bit 11_128 +bit 11_129 +bit 11_13 +bit 11_130 +bit 11_131 +bit 11_132 +bit 11_133 +bit 11_134 +bit 11_135 +bit 11_136 +bit 11_137 +bit 11_138 +bit 11_139 +bit 11_14 +bit 11_140 +bit 11_141 +bit 11_142 +bit 11_143 +bit 11_144 +bit 11_145 +bit 11_146 +bit 11_147 +bit 11_148 +bit 11_149 +bit 11_15 +bit 11_150 +bit 11_151 +bit 11_152 +bit 11_153 +bit 11_154 +bit 11_155 +bit 11_156 +bit 11_157 +bit 11_158 +bit 11_159 +bit 11_16 +bit 11_160 +bit 11_161 +bit 11_162 +bit 11_163 +bit 11_164 +bit 11_165 +bit 11_166 +bit 11_167 +bit 11_168 +bit 11_169 +bit 11_17 +bit 11_170 +bit 11_171 +bit 11_172 +bit 11_173 +bit 11_174 +bit 11_175 +bit 11_176 +bit 11_177 +bit 11_178 +bit 11_179 +bit 11_18 +bit 11_180 +bit 11_181 +bit 11_182 +bit 11_183 +bit 11_184 +bit 11_185 +bit 11_186 +bit 11_187 +bit 11_188 +bit 11_189 +bit 11_19 +bit 11_190 +bit 11_191 +bit 11_192 +bit 11_193 +bit 11_194 +bit 11_195 +bit 11_196 +bit 11_197 +bit 11_198 +bit 11_199 +bit 11_20 +bit 11_200 +bit 11_201 +bit 11_202 +bit 11_203 +bit 11_204 +bit 11_205 +bit 11_206 +bit 11_207 +bit 11_208 +bit 11_209 +bit 11_21 +bit 11_210 +bit 11_211 +bit 11_212 +bit 11_213 +bit 11_214 +bit 11_215 +bit 11_216 +bit 11_217 +bit 11_218 +bit 11_219 +bit 11_22 +bit 11_220 +bit 11_221 +bit 11_222 +bit 11_223 +bit 11_224 +bit 11_225 +bit 11_226 +bit 11_227 +bit 11_228 +bit 11_229 +bit 11_23 +bit 11_230 +bit 11_231 +bit 11_232 +bit 11_233 +bit 11_234 +bit 11_235 +bit 11_236 +bit 11_237 +bit 11_238 +bit 11_239 +bit 11_24 +bit 11_240 +bit 11_241 +bit 11_242 +bit 11_243 +bit 11_244 +bit 11_245 +bit 11_246 +bit 11_247 +bit 11_248 +bit 11_249 +bit 11_25 +bit 11_250 +bit 11_251 +bit 11_252 +bit 11_253 +bit 11_254 +bit 11_255 +bit 11_256 +bit 11_257 +bit 11_258 +bit 11_259 +bit 11_26 +bit 11_260 +bit 11_261 +bit 11_262 +bit 11_263 +bit 11_264 +bit 11_265 +bit 11_266 +bit 11_267 +bit 11_268 +bit 11_269 +bit 11_27 +bit 11_270 +bit 11_271 +bit 11_272 +bit 11_273 +bit 11_274 +bit 11_275 +bit 11_276 +bit 11_277 +bit 11_278 +bit 11_279 +bit 11_28 +bit 11_280 +bit 11_281 +bit 11_282 +bit 11_283 +bit 11_284 +bit 11_285 +bit 11_286 +bit 11_287 +bit 11_288 +bit 11_289 +bit 11_29 +bit 11_290 +bit 11_291 +bit 11_292 +bit 11_293 +bit 11_294 +bit 11_295 +bit 11_296 +bit 11_297 +bit 11_298 +bit 11_299 +bit 11_30 +bit 11_300 +bit 11_301 +bit 11_302 +bit 11_303 +bit 11_304 +bit 11_305 +bit 11_306 +bit 11_307 +bit 11_308 +bit 11_309 +bit 11_31 +bit 11_310 +bit 11_311 +bit 11_312 +bit 11_313 +bit 11_314 +bit 11_315 +bit 11_316 +bit 11_317 +bit 11_318 +bit 11_319 +bit 11_32 +bit 11_33 +bit 11_34 +bit 11_35 +bit 11_36 +bit 11_37 +bit 11_38 +bit 11_39 +bit 11_40 +bit 11_41 +bit 11_42 +bit 11_43 +bit 11_44 +bit 11_45 +bit 11_46 +bit 11_47 +bit 11_48 +bit 11_49 +bit 11_50 +bit 11_51 +bit 11_52 +bit 11_53 +bit 11_54 +bit 11_55 +bit 11_56 +bit 11_57 +bit 11_58 +bit 11_59 +bit 11_60 +bit 11_61 +bit 11_62 +bit 11_63 +bit 11_64 +bit 11_65 +bit 11_66 +bit 11_67 +bit 11_68 +bit 11_69 +bit 11_70 +bit 11_71 +bit 11_72 +bit 11_73 +bit 11_74 +bit 11_75 +bit 11_76 +bit 11_77 +bit 11_78 +bit 11_79 +bit 11_80 +bit 11_81 +bit 11_82 +bit 11_83 +bit 11_84 +bit 11_85 +bit 11_86 +bit 11_87 +bit 11_88 +bit 11_89 +bit 11_90 +bit 11_91 +bit 11_92 +bit 11_93 +bit 11_94 +bit 11_95 +bit 11_96 +bit 11_97 +bit 11_98 +bit 11_99 +bit 12_00 +bit 12_01 +bit 12_02 +bit 12_03 +bit 12_04 +bit 12_05 +bit 12_06 +bit 12_07 +bit 12_08 +bit 12_09 +bit 12_10 +bit 12_100 +bit 12_101 +bit 12_102 +bit 12_103 +bit 12_104 +bit 12_105 +bit 12_106 +bit 12_107 +bit 12_108 +bit 12_109 +bit 12_11 +bit 12_110 +bit 12_111 +bit 12_112 +bit 12_113 +bit 12_114 +bit 12_115 +bit 12_116 +bit 12_117 +bit 12_118 +bit 12_119 +bit 12_12 +bit 12_120 +bit 12_121 +bit 12_122 +bit 12_123 +bit 12_124 +bit 12_125 +bit 12_126 +bit 12_127 +bit 12_128 +bit 12_129 +bit 12_13 +bit 12_130 +bit 12_131 +bit 12_132 +bit 12_133 +bit 12_134 +bit 12_135 +bit 12_136 +bit 12_137 +bit 12_138 +bit 12_139 +bit 12_14 +bit 12_140 +bit 12_141 +bit 12_142 +bit 12_143 +bit 12_144 +bit 12_145 +bit 12_146 +bit 12_147 +bit 12_148 +bit 12_149 +bit 12_15 +bit 12_150 +bit 12_151 +bit 12_152 +bit 12_153 +bit 12_154 +bit 12_155 +bit 12_156 +bit 12_157 +bit 12_158 +bit 12_159 +bit 12_16 +bit 12_160 +bit 12_161 +bit 12_162 +bit 12_163 +bit 12_164 +bit 12_165 +bit 12_166 +bit 12_167 +bit 12_168 +bit 12_169 +bit 12_17 +bit 12_170 +bit 12_171 +bit 12_172 +bit 12_173 +bit 12_174 +bit 12_175 +bit 12_176 +bit 12_177 +bit 12_178 +bit 12_179 +bit 12_18 +bit 12_180 +bit 12_181 +bit 12_182 +bit 12_183 +bit 12_184 +bit 12_185 +bit 12_186 +bit 12_187 +bit 12_188 +bit 12_189 +bit 12_19 +bit 12_190 +bit 12_191 +bit 12_192 +bit 12_193 +bit 12_194 +bit 12_195 +bit 12_196 +bit 12_197 +bit 12_198 +bit 12_199 +bit 12_20 +bit 12_200 +bit 12_201 +bit 12_202 +bit 12_203 +bit 12_204 +bit 12_205 +bit 12_206 +bit 12_207 +bit 12_208 +bit 12_209 +bit 12_21 +bit 12_210 +bit 12_211 +bit 12_212 +bit 12_213 +bit 12_214 +bit 12_215 +bit 12_216 +bit 12_217 +bit 12_218 +bit 12_219 +bit 12_22 +bit 12_220 +bit 12_221 +bit 12_222 +bit 12_223 +bit 12_224 +bit 12_225 +bit 12_226 +bit 12_227 +bit 12_228 +bit 12_229 +bit 12_23 +bit 12_230 +bit 12_231 +bit 12_232 +bit 12_233 +bit 12_234 +bit 12_235 +bit 12_236 +bit 12_237 +bit 12_238 +bit 12_239 +bit 12_24 +bit 12_240 +bit 12_241 +bit 12_242 +bit 12_243 +bit 12_244 +bit 12_245 +bit 12_246 +bit 12_247 +bit 12_248 +bit 12_249 +bit 12_25 +bit 12_250 +bit 12_251 +bit 12_252 +bit 12_253 +bit 12_254 +bit 12_255 +bit 12_256 +bit 12_257 +bit 12_258 +bit 12_259 +bit 12_26 +bit 12_260 +bit 12_261 +bit 12_262 +bit 12_263 +bit 12_264 +bit 12_265 +bit 12_266 +bit 12_267 +bit 12_268 +bit 12_269 +bit 12_27 +bit 12_270 +bit 12_271 +bit 12_272 +bit 12_273 +bit 12_274 +bit 12_275 +bit 12_276 +bit 12_277 +bit 12_278 +bit 12_279 +bit 12_28 +bit 12_280 +bit 12_281 +bit 12_282 +bit 12_283 +bit 12_284 +bit 12_285 +bit 12_286 +bit 12_287 +bit 12_288 +bit 12_289 +bit 12_29 +bit 12_290 +bit 12_291 +bit 12_292 +bit 12_293 +bit 12_294 +bit 12_295 +bit 12_296 +bit 12_297 +bit 12_298 +bit 12_299 +bit 12_30 +bit 12_300 +bit 12_301 +bit 12_302 +bit 12_303 +bit 12_304 +bit 12_305 +bit 12_306 +bit 12_307 +bit 12_308 +bit 12_309 +bit 12_31 +bit 12_310 +bit 12_311 +bit 12_312 +bit 12_313 +bit 12_314 +bit 12_315 +bit 12_316 +bit 12_317 +bit 12_318 +bit 12_319 +bit 12_32 +bit 12_33 +bit 12_34 +bit 12_35 +bit 12_36 +bit 12_37 +bit 12_38 +bit 12_39 +bit 12_40 +bit 12_41 +bit 12_42 +bit 12_43 +bit 12_44 +bit 12_45 +bit 12_46 +bit 12_47 +bit 12_48 +bit 12_49 +bit 12_50 +bit 12_51 +bit 12_52 +bit 12_53 +bit 12_54 +bit 12_55 +bit 12_56 +bit 12_57 +bit 12_58 +bit 12_59 +bit 12_60 +bit 12_61 +bit 12_62 +bit 12_63 +bit 12_64 +bit 12_65 +bit 12_66 +bit 12_67 +bit 12_68 +bit 12_69 +bit 12_70 +bit 12_71 +bit 12_72 +bit 12_73 +bit 12_74 +bit 12_75 +bit 12_76 +bit 12_77 +bit 12_78 +bit 12_79 +bit 12_80 +bit 12_81 +bit 12_82 +bit 12_83 +bit 12_84 +bit 12_85 +bit 12_86 +bit 12_87 +bit 12_88 +bit 12_89 +bit 12_90 +bit 12_91 +bit 12_92 +bit 12_93 +bit 12_94 +bit 12_95 +bit 12_96 +bit 12_97 +bit 12_98 +bit 12_99 +bit 13_00 +bit 13_01 +bit 13_02 +bit 13_03 +bit 13_04 +bit 13_05 +bit 13_06 +bit 13_07 +bit 13_08 +bit 13_09 +bit 13_10 +bit 13_100 +bit 13_101 +bit 13_102 +bit 13_103 +bit 13_104 +bit 13_105 +bit 13_106 +bit 13_107 +bit 13_108 +bit 13_109 +bit 13_11 +bit 13_110 +bit 13_111 +bit 13_112 +bit 13_113 +bit 13_114 +bit 13_115 +bit 13_116 +bit 13_117 +bit 13_118 +bit 13_119 +bit 13_12 +bit 13_120 +bit 13_121 +bit 13_122 +bit 13_123 +bit 13_124 +bit 13_125 +bit 13_126 +bit 13_127 +bit 13_128 +bit 13_129 +bit 13_13 +bit 13_130 +bit 13_131 +bit 13_132 +bit 13_133 +bit 13_134 +bit 13_135 +bit 13_136 +bit 13_137 +bit 13_138 +bit 13_139 +bit 13_14 +bit 13_140 +bit 13_141 +bit 13_142 +bit 13_143 +bit 13_144 +bit 13_145 +bit 13_146 +bit 13_147 +bit 13_148 +bit 13_149 +bit 13_15 +bit 13_150 +bit 13_151 +bit 13_152 +bit 13_153 +bit 13_154 +bit 13_155 +bit 13_156 +bit 13_157 +bit 13_158 +bit 13_159 +bit 13_16 +bit 13_160 +bit 13_161 +bit 13_162 +bit 13_163 +bit 13_164 +bit 13_165 +bit 13_166 +bit 13_167 +bit 13_168 +bit 13_169 +bit 13_17 +bit 13_170 +bit 13_171 +bit 13_172 +bit 13_173 +bit 13_174 +bit 13_175 +bit 13_176 +bit 13_177 +bit 13_178 +bit 13_179 +bit 13_18 +bit 13_180 +bit 13_181 +bit 13_182 +bit 13_183 +bit 13_184 +bit 13_185 +bit 13_186 +bit 13_187 +bit 13_188 +bit 13_189 +bit 13_19 +bit 13_190 +bit 13_191 +bit 13_192 +bit 13_193 +bit 13_194 +bit 13_195 +bit 13_196 +bit 13_197 +bit 13_198 +bit 13_199 +bit 13_20 +bit 13_200 +bit 13_201 +bit 13_202 +bit 13_203 +bit 13_204 +bit 13_205 +bit 13_206 +bit 13_207 +bit 13_208 +bit 13_209 +bit 13_21 +bit 13_210 +bit 13_211 +bit 13_212 +bit 13_213 +bit 13_214 +bit 13_215 +bit 13_216 +bit 13_217 +bit 13_218 +bit 13_219 +bit 13_22 +bit 13_220 +bit 13_221 +bit 13_222 +bit 13_223 +bit 13_224 +bit 13_225 +bit 13_226 +bit 13_227 +bit 13_228 +bit 13_229 +bit 13_23 +bit 13_230 +bit 13_231 +bit 13_232 +bit 13_233 +bit 13_234 +bit 13_235 +bit 13_236 +bit 13_237 +bit 13_238 +bit 13_239 +bit 13_24 +bit 13_240 +bit 13_241 +bit 13_242 +bit 13_243 +bit 13_244 +bit 13_245 +bit 13_246 +bit 13_247 +bit 13_248 +bit 13_249 +bit 13_25 +bit 13_250 +bit 13_251 +bit 13_252 +bit 13_253 +bit 13_254 +bit 13_255 +bit 13_256 +bit 13_257 +bit 13_258 +bit 13_259 +bit 13_26 +bit 13_260 +bit 13_261 +bit 13_262 +bit 13_263 +bit 13_264 +bit 13_265 +bit 13_266 +bit 13_267 +bit 13_268 +bit 13_269 +bit 13_27 +bit 13_270 +bit 13_271 +bit 13_272 +bit 13_273 +bit 13_274 +bit 13_275 +bit 13_276 +bit 13_277 +bit 13_278 +bit 13_279 +bit 13_28 +bit 13_280 +bit 13_281 +bit 13_282 +bit 13_283 +bit 13_284 +bit 13_285 +bit 13_286 +bit 13_287 +bit 13_288 +bit 13_289 +bit 13_29 +bit 13_290 +bit 13_291 +bit 13_292 +bit 13_293 +bit 13_294 +bit 13_295 +bit 13_296 +bit 13_297 +bit 13_298 +bit 13_299 +bit 13_30 +bit 13_300 +bit 13_301 +bit 13_302 +bit 13_303 +bit 13_304 +bit 13_305 +bit 13_306 +bit 13_307 +bit 13_308 +bit 13_309 +bit 13_31 +bit 13_310 +bit 13_311 +bit 13_312 +bit 13_313 +bit 13_314 +bit 13_315 +bit 13_316 +bit 13_317 +bit 13_318 +bit 13_319 +bit 13_32 +bit 13_33 +bit 13_34 +bit 13_35 +bit 13_36 +bit 13_37 +bit 13_38 +bit 13_39 +bit 13_40 +bit 13_41 +bit 13_42 +bit 13_43 +bit 13_44 +bit 13_45 +bit 13_46 +bit 13_47 +bit 13_48 +bit 13_49 +bit 13_50 +bit 13_51 +bit 13_52 +bit 13_53 +bit 13_54 +bit 13_55 +bit 13_56 +bit 13_57 +bit 13_58 +bit 13_59 +bit 13_60 +bit 13_61 +bit 13_62 +bit 13_63 +bit 13_64 +bit 13_65 +bit 13_66 +bit 13_67 +bit 13_68 +bit 13_69 +bit 13_70 +bit 13_71 +bit 13_72 +bit 13_73 +bit 13_74 +bit 13_75 +bit 13_76 +bit 13_77 +bit 13_78 +bit 13_79 +bit 13_80 +bit 13_81 +bit 13_82 +bit 13_83 +bit 13_84 +bit 13_85 +bit 13_86 +bit 13_87 +bit 13_88 +bit 13_89 +bit 13_90 +bit 13_91 +bit 13_92 +bit 13_93 +bit 13_94 +bit 13_95 +bit 13_96 +bit 13_97 +bit 13_98 +bit 13_99 +bit 14_00 +bit 14_01 +bit 14_02 +bit 14_03 +bit 14_04 +bit 14_05 +bit 14_06 +bit 14_07 +bit 14_08 +bit 14_09 +bit 14_10 +bit 14_100 +bit 14_101 +bit 14_102 +bit 14_103 +bit 14_104 +bit 14_105 +bit 14_106 +bit 14_107 +bit 14_108 +bit 14_109 +bit 14_11 +bit 14_110 +bit 14_111 +bit 14_112 +bit 14_113 +bit 14_114 +bit 14_115 +bit 14_116 +bit 14_117 +bit 14_118 +bit 14_119 +bit 14_12 +bit 14_120 +bit 14_121 +bit 14_122 +bit 14_123 +bit 14_124 +bit 14_125 +bit 14_126 +bit 14_127 +bit 14_128 +bit 14_129 +bit 14_13 +bit 14_130 +bit 14_131 +bit 14_132 +bit 14_133 +bit 14_134 +bit 14_135 +bit 14_136 +bit 14_137 +bit 14_138 +bit 14_139 +bit 14_14 +bit 14_140 +bit 14_141 +bit 14_142 +bit 14_143 +bit 14_144 +bit 14_145 +bit 14_146 +bit 14_147 +bit 14_148 +bit 14_149 +bit 14_15 +bit 14_150 +bit 14_151 +bit 14_152 +bit 14_153 +bit 14_154 +bit 14_155 +bit 14_156 +bit 14_157 +bit 14_158 +bit 14_159 +bit 14_16 +bit 14_160 +bit 14_161 +bit 14_162 +bit 14_163 +bit 14_164 +bit 14_165 +bit 14_166 +bit 14_167 +bit 14_168 +bit 14_169 +bit 14_17 +bit 14_170 +bit 14_171 +bit 14_172 +bit 14_173 +bit 14_174 +bit 14_175 +bit 14_176 +bit 14_177 +bit 14_178 +bit 14_179 +bit 14_18 +bit 14_180 +bit 14_181 +bit 14_182 +bit 14_183 +bit 14_184 +bit 14_185 +bit 14_186 +bit 14_187 +bit 14_188 +bit 14_189 +bit 14_19 +bit 14_190 +bit 14_191 +bit 14_192 +bit 14_193 +bit 14_194 +bit 14_195 +bit 14_196 +bit 14_197 +bit 14_198 +bit 14_199 +bit 14_20 +bit 14_200 +bit 14_201 +bit 14_202 +bit 14_203 +bit 14_204 +bit 14_205 +bit 14_206 +bit 14_207 +bit 14_208 +bit 14_209 +bit 14_21 +bit 14_210 +bit 14_211 +bit 14_212 +bit 14_213 +bit 14_214 +bit 14_215 +bit 14_216 +bit 14_217 +bit 14_218 +bit 14_219 +bit 14_22 +bit 14_220 +bit 14_221 +bit 14_222 +bit 14_223 +bit 14_224 +bit 14_225 +bit 14_226 +bit 14_227 +bit 14_228 +bit 14_229 +bit 14_23 +bit 14_230 +bit 14_231 +bit 14_232 +bit 14_233 +bit 14_234 +bit 14_235 +bit 14_236 +bit 14_237 +bit 14_238 +bit 14_239 +bit 14_24 +bit 14_240 +bit 14_241 +bit 14_242 +bit 14_243 +bit 14_244 +bit 14_245 +bit 14_246 +bit 14_247 +bit 14_248 +bit 14_249 +bit 14_25 +bit 14_250 +bit 14_251 +bit 14_252 +bit 14_253 +bit 14_254 +bit 14_255 +bit 14_256 +bit 14_257 +bit 14_258 +bit 14_259 +bit 14_26 +bit 14_260 +bit 14_261 +bit 14_262 +bit 14_263 +bit 14_264 +bit 14_265 +bit 14_266 +bit 14_267 +bit 14_268 +bit 14_269 +bit 14_27 +bit 14_270 +bit 14_271 +bit 14_272 +bit 14_273 +bit 14_274 +bit 14_275 +bit 14_276 +bit 14_277 +bit 14_278 +bit 14_279 +bit 14_28 +bit 14_280 +bit 14_281 +bit 14_282 +bit 14_283 +bit 14_284 +bit 14_285 +bit 14_286 +bit 14_287 +bit 14_288 +bit 14_289 +bit 14_29 +bit 14_290 +bit 14_291 +bit 14_292 +bit 14_293 +bit 14_294 +bit 14_295 +bit 14_296 +bit 14_297 +bit 14_298 +bit 14_299 +bit 14_30 +bit 14_300 +bit 14_301 +bit 14_302 +bit 14_303 +bit 14_304 +bit 14_305 +bit 14_306 +bit 14_307 +bit 14_308 +bit 14_309 +bit 14_31 +bit 14_310 +bit 14_311 +bit 14_312 +bit 14_313 +bit 14_314 +bit 14_315 +bit 14_316 +bit 14_317 +bit 14_318 +bit 14_319 +bit 14_32 +bit 14_33 +bit 14_34 +bit 14_35 +bit 14_36 +bit 14_37 +bit 14_38 +bit 14_39 +bit 14_40 +bit 14_41 +bit 14_42 +bit 14_43 +bit 14_44 +bit 14_45 +bit 14_46 +bit 14_47 +bit 14_48 +bit 14_49 +bit 14_50 +bit 14_51 +bit 14_52 +bit 14_53 +bit 14_54 +bit 14_55 +bit 14_56 +bit 14_57 +bit 14_58 +bit 14_59 +bit 14_60 +bit 14_61 +bit 14_62 +bit 14_63 +bit 14_64 +bit 14_65 +bit 14_66 +bit 14_67 +bit 14_68 +bit 14_69 +bit 14_70 +bit 14_71 +bit 14_72 +bit 14_73 +bit 14_74 +bit 14_75 +bit 14_76 +bit 14_77 +bit 14_78 +bit 14_79 +bit 14_80 +bit 14_81 +bit 14_82 +bit 14_83 +bit 14_84 +bit 14_85 +bit 14_86 +bit 14_87 +bit 14_88 +bit 14_89 +bit 14_90 +bit 14_91 +bit 14_92 +bit 14_93 +bit 14_94 +bit 14_95 +bit 14_96 +bit 14_97 +bit 14_98 +bit 14_99 +bit 15_00 +bit 15_01 +bit 15_02 +bit 15_03 +bit 15_04 +bit 15_05 +bit 15_06 +bit 15_07 +bit 15_08 +bit 15_09 +bit 15_10 +bit 15_100 +bit 15_101 +bit 15_102 +bit 15_103 +bit 15_104 +bit 15_105 +bit 15_106 +bit 15_107 +bit 15_108 +bit 15_109 +bit 15_11 +bit 15_110 +bit 15_111 +bit 15_112 +bit 15_113 +bit 15_114 +bit 15_115 +bit 15_116 +bit 15_117 +bit 15_118 +bit 15_119 +bit 15_12 +bit 15_120 +bit 15_121 +bit 15_122 +bit 15_123 +bit 15_124 +bit 15_125 +bit 15_126 +bit 15_127 +bit 15_128 +bit 15_129 +bit 15_13 +bit 15_130 +bit 15_131 +bit 15_132 +bit 15_133 +bit 15_134 +bit 15_135 +bit 15_136 +bit 15_137 +bit 15_138 +bit 15_139 +bit 15_14 +bit 15_140 +bit 15_141 +bit 15_142 +bit 15_143 +bit 15_144 +bit 15_145 +bit 15_146 +bit 15_147 +bit 15_148 +bit 15_149 +bit 15_15 +bit 15_150 +bit 15_151 +bit 15_152 +bit 15_153 +bit 15_154 +bit 15_155 +bit 15_156 +bit 15_157 +bit 15_158 +bit 15_159 +bit 15_16 +bit 15_160 +bit 15_161 +bit 15_162 +bit 15_163 +bit 15_164 +bit 15_165 +bit 15_166 +bit 15_167 +bit 15_168 +bit 15_169 +bit 15_17 +bit 15_170 +bit 15_171 +bit 15_172 +bit 15_173 +bit 15_174 +bit 15_175 +bit 15_176 +bit 15_177 +bit 15_178 +bit 15_179 +bit 15_18 +bit 15_180 +bit 15_181 +bit 15_182 +bit 15_183 +bit 15_184 +bit 15_185 +bit 15_186 +bit 15_187 +bit 15_188 +bit 15_189 +bit 15_19 +bit 15_190 +bit 15_191 +bit 15_192 +bit 15_193 +bit 15_194 +bit 15_195 +bit 15_196 +bit 15_197 +bit 15_198 +bit 15_199 +bit 15_20 +bit 15_200 +bit 15_201 +bit 15_202 +bit 15_203 +bit 15_204 +bit 15_205 +bit 15_206 +bit 15_207 +bit 15_208 +bit 15_209 +bit 15_21 +bit 15_210 +bit 15_211 +bit 15_212 +bit 15_213 +bit 15_214 +bit 15_215 +bit 15_216 +bit 15_217 +bit 15_218 +bit 15_219 +bit 15_22 +bit 15_220 +bit 15_221 +bit 15_222 +bit 15_223 +bit 15_224 +bit 15_225 +bit 15_226 +bit 15_227 +bit 15_228 +bit 15_229 +bit 15_23 +bit 15_230 +bit 15_231 +bit 15_232 +bit 15_233 +bit 15_234 +bit 15_235 +bit 15_236 +bit 15_237 +bit 15_238 +bit 15_239 +bit 15_24 +bit 15_240 +bit 15_241 +bit 15_242 +bit 15_243 +bit 15_244 +bit 15_245 +bit 15_246 +bit 15_247 +bit 15_248 +bit 15_249 +bit 15_25 +bit 15_250 +bit 15_251 +bit 15_252 +bit 15_253 +bit 15_254 +bit 15_255 +bit 15_256 +bit 15_257 +bit 15_258 +bit 15_259 +bit 15_26 +bit 15_260 +bit 15_261 +bit 15_262 +bit 15_263 +bit 15_264 +bit 15_265 +bit 15_266 +bit 15_267 +bit 15_268 +bit 15_269 +bit 15_27 +bit 15_270 +bit 15_271 +bit 15_272 +bit 15_273 +bit 15_274 +bit 15_275 +bit 15_276 +bit 15_277 +bit 15_278 +bit 15_279 +bit 15_28 +bit 15_280 +bit 15_281 +bit 15_282 +bit 15_283 +bit 15_284 +bit 15_285 +bit 15_286 +bit 15_287 +bit 15_288 +bit 15_289 +bit 15_29 +bit 15_290 +bit 15_291 +bit 15_292 +bit 15_293 +bit 15_294 +bit 15_295 +bit 15_296 +bit 15_297 +bit 15_298 +bit 15_299 +bit 15_30 +bit 15_300 +bit 15_301 +bit 15_302 +bit 15_303 +bit 15_304 +bit 15_305 +bit 15_306 +bit 15_307 +bit 15_308 +bit 15_309 +bit 15_31 +bit 15_310 +bit 15_311 +bit 15_312 +bit 15_313 +bit 15_314 +bit 15_315 +bit 15_316 +bit 15_317 +bit 15_318 +bit 15_319 +bit 15_32 +bit 15_33 +bit 15_34 +bit 15_35 +bit 15_36 +bit 15_37 +bit 15_38 +bit 15_39 +bit 15_40 +bit 15_41 +bit 15_42 +bit 15_43 +bit 15_44 +bit 15_45 +bit 15_46 +bit 15_47 +bit 15_48 +bit 15_49 +bit 15_50 +bit 15_51 +bit 15_52 +bit 15_53 +bit 15_54 +bit 15_55 +bit 15_56 +bit 15_57 +bit 15_58 +bit 15_59 +bit 15_60 +bit 15_61 +bit 15_62 +bit 15_63 +bit 15_64 +bit 15_65 +bit 15_66 +bit 15_67 +bit 15_68 +bit 15_69 +bit 15_70 +bit 15_71 +bit 15_72 +bit 15_73 +bit 15_74 +bit 15_75 +bit 15_76 +bit 15_77 +bit 15_78 +bit 15_79 +bit 15_80 +bit 15_81 +bit 15_82 +bit 15_83 +bit 15_84 +bit 15_85 +bit 15_86 +bit 15_87 +bit 15_88 +bit 15_89 +bit 15_90 +bit 15_91 +bit 15_92 +bit 15_93 +bit 15_94 +bit 15_95 +bit 15_96 +bit 15_97 +bit 15_98 +bit 15_99 +bit 16_00 +bit 16_01 +bit 16_02 +bit 16_03 +bit 16_04 +bit 16_05 +bit 16_06 +bit 16_07 +bit 16_08 +bit 16_09 +bit 16_10 +bit 16_100 +bit 16_101 +bit 16_102 +bit 16_103 +bit 16_104 +bit 16_105 +bit 16_106 +bit 16_107 +bit 16_108 +bit 16_109 +bit 16_11 +bit 16_110 +bit 16_111 +bit 16_112 +bit 16_113 +bit 16_114 +bit 16_115 +bit 16_116 +bit 16_117 +bit 16_118 +bit 16_119 +bit 16_12 +bit 16_120 +bit 16_121 +bit 16_122 +bit 16_123 +bit 16_124 +bit 16_125 +bit 16_126 +bit 16_127 +bit 16_128 +bit 16_129 +bit 16_13 +bit 16_130 +bit 16_131 +bit 16_132 +bit 16_133 +bit 16_134 +bit 16_135 +bit 16_136 +bit 16_137 +bit 16_138 +bit 16_139 +bit 16_14 +bit 16_140 +bit 16_141 +bit 16_142 +bit 16_143 +bit 16_144 +bit 16_145 +bit 16_146 +bit 16_147 +bit 16_148 +bit 16_149 +bit 16_15 +bit 16_150 +bit 16_151 +bit 16_152 +bit 16_153 +bit 16_154 +bit 16_155 +bit 16_156 +bit 16_157 +bit 16_158 +bit 16_159 +bit 16_16 +bit 16_160 +bit 16_161 +bit 16_162 +bit 16_163 +bit 16_164 +bit 16_165 +bit 16_166 +bit 16_167 +bit 16_168 +bit 16_169 +bit 16_17 +bit 16_170 +bit 16_171 +bit 16_172 +bit 16_173 +bit 16_174 +bit 16_175 +bit 16_176 +bit 16_177 +bit 16_178 +bit 16_179 +bit 16_18 +bit 16_180 +bit 16_181 +bit 16_182 +bit 16_183 +bit 16_184 +bit 16_185 +bit 16_186 +bit 16_187 +bit 16_188 +bit 16_189 +bit 16_19 +bit 16_190 +bit 16_191 +bit 16_192 +bit 16_193 +bit 16_194 +bit 16_195 +bit 16_196 +bit 16_197 +bit 16_198 +bit 16_199 +bit 16_20 +bit 16_200 +bit 16_201 +bit 16_202 +bit 16_203 +bit 16_204 +bit 16_205 +bit 16_206 +bit 16_207 +bit 16_208 +bit 16_209 +bit 16_21 +bit 16_210 +bit 16_211 +bit 16_212 +bit 16_213 +bit 16_214 +bit 16_215 +bit 16_216 +bit 16_217 +bit 16_218 +bit 16_219 +bit 16_22 +bit 16_220 +bit 16_221 +bit 16_222 +bit 16_223 +bit 16_224 +bit 16_225 +bit 16_226 +bit 16_227 +bit 16_228 +bit 16_229 +bit 16_23 +bit 16_230 +bit 16_231 +bit 16_232 +bit 16_233 +bit 16_234 +bit 16_235 +bit 16_236 +bit 16_237 +bit 16_238 +bit 16_239 +bit 16_24 +bit 16_240 +bit 16_241 +bit 16_242 +bit 16_243 +bit 16_244 +bit 16_245 +bit 16_246 +bit 16_247 +bit 16_248 +bit 16_249 +bit 16_25 +bit 16_250 +bit 16_251 +bit 16_252 +bit 16_253 +bit 16_254 +bit 16_255 +bit 16_256 +bit 16_257 +bit 16_258 +bit 16_259 +bit 16_26 +bit 16_260 +bit 16_261 +bit 16_262 +bit 16_263 +bit 16_264 +bit 16_265 +bit 16_266 +bit 16_267 +bit 16_268 +bit 16_269 +bit 16_27 +bit 16_270 +bit 16_271 +bit 16_272 +bit 16_273 +bit 16_274 +bit 16_275 +bit 16_276 +bit 16_277 +bit 16_278 +bit 16_279 +bit 16_28 +bit 16_280 +bit 16_281 +bit 16_282 +bit 16_283 +bit 16_284 +bit 16_285 +bit 16_286 +bit 16_287 +bit 16_288 +bit 16_289 +bit 16_29 +bit 16_290 +bit 16_291 +bit 16_292 +bit 16_293 +bit 16_294 +bit 16_295 +bit 16_296 +bit 16_297 +bit 16_298 +bit 16_299 +bit 16_30 +bit 16_300 +bit 16_301 +bit 16_302 +bit 16_303 +bit 16_304 +bit 16_305 +bit 16_306 +bit 16_307 +bit 16_308 +bit 16_309 +bit 16_31 +bit 16_310 +bit 16_311 +bit 16_312 +bit 16_313 +bit 16_314 +bit 16_315 +bit 16_316 +bit 16_317 +bit 16_318 +bit 16_319 +bit 16_32 +bit 16_33 +bit 16_34 +bit 16_35 +bit 16_36 +bit 16_37 +bit 16_38 +bit 16_39 +bit 16_40 +bit 16_41 +bit 16_42 +bit 16_43 +bit 16_44 +bit 16_45 +bit 16_46 +bit 16_47 +bit 16_48 +bit 16_49 +bit 16_50 +bit 16_51 +bit 16_52 +bit 16_53 +bit 16_54 +bit 16_55 +bit 16_56 +bit 16_57 +bit 16_58 +bit 16_59 +bit 16_60 +bit 16_61 +bit 16_62 +bit 16_63 +bit 16_64 +bit 16_65 +bit 16_66 +bit 16_67 +bit 16_68 +bit 16_69 +bit 16_70 +bit 16_71 +bit 16_72 +bit 16_73 +bit 16_74 +bit 16_75 +bit 16_76 +bit 16_77 +bit 16_78 +bit 16_79 +bit 16_80 +bit 16_81 +bit 16_82 +bit 16_83 +bit 16_84 +bit 16_85 +bit 16_86 +bit 16_87 +bit 16_88 +bit 16_89 +bit 16_90 +bit 16_91 +bit 16_92 +bit 16_93 +bit 16_94 +bit 16_95 +bit 16_96 +bit 16_97 +bit 16_98 +bit 16_99 +bit 17_00 +bit 17_01 +bit 17_02 +bit 17_03 +bit 17_04 +bit 17_05 +bit 17_06 +bit 17_07 +bit 17_08 +bit 17_09 +bit 17_10 +bit 17_100 +bit 17_101 +bit 17_102 +bit 17_103 +bit 17_104 +bit 17_105 +bit 17_106 +bit 17_107 +bit 17_108 +bit 17_109 +bit 17_11 +bit 17_110 +bit 17_111 +bit 17_112 +bit 17_113 +bit 17_114 +bit 17_115 +bit 17_116 +bit 17_117 +bit 17_118 +bit 17_119 +bit 17_12 +bit 17_120 +bit 17_121 +bit 17_122 +bit 17_123 +bit 17_124 +bit 17_125 +bit 17_126 +bit 17_127 +bit 17_128 +bit 17_129 +bit 17_13 +bit 17_130 +bit 17_131 +bit 17_132 +bit 17_133 +bit 17_134 +bit 17_135 +bit 17_136 +bit 17_137 +bit 17_138 +bit 17_139 +bit 17_14 +bit 17_140 +bit 17_141 +bit 17_142 +bit 17_143 +bit 17_144 +bit 17_145 +bit 17_146 +bit 17_147 +bit 17_148 +bit 17_149 +bit 17_15 +bit 17_150 +bit 17_151 +bit 17_152 +bit 17_153 +bit 17_154 +bit 17_155 +bit 17_156 +bit 17_157 +bit 17_158 +bit 17_159 +bit 17_16 +bit 17_160 +bit 17_161 +bit 17_162 +bit 17_163 +bit 17_164 +bit 17_165 +bit 17_166 +bit 17_167 +bit 17_168 +bit 17_169 +bit 17_17 +bit 17_170 +bit 17_171 +bit 17_172 +bit 17_173 +bit 17_174 +bit 17_175 +bit 17_176 +bit 17_177 +bit 17_178 +bit 17_179 +bit 17_18 +bit 17_180 +bit 17_181 +bit 17_182 +bit 17_183 +bit 17_184 +bit 17_185 +bit 17_186 +bit 17_187 +bit 17_188 +bit 17_189 +bit 17_19 +bit 17_190 +bit 17_191 +bit 17_192 +bit 17_193 +bit 17_194 +bit 17_195 +bit 17_196 +bit 17_197 +bit 17_198 +bit 17_199 +bit 17_20 +bit 17_200 +bit 17_201 +bit 17_202 +bit 17_203 +bit 17_204 +bit 17_205 +bit 17_206 +bit 17_207 +bit 17_208 +bit 17_209 +bit 17_21 +bit 17_210 +bit 17_211 +bit 17_212 +bit 17_213 +bit 17_214 +bit 17_215 +bit 17_216 +bit 17_217 +bit 17_218 +bit 17_219 +bit 17_22 +bit 17_220 +bit 17_221 +bit 17_222 +bit 17_223 +bit 17_224 +bit 17_225 +bit 17_226 +bit 17_227 +bit 17_228 +bit 17_229 +bit 17_23 +bit 17_230 +bit 17_231 +bit 17_232 +bit 17_233 +bit 17_234 +bit 17_235 +bit 17_236 +bit 17_237 +bit 17_238 +bit 17_239 +bit 17_24 +bit 17_240 +bit 17_241 +bit 17_242 +bit 17_243 +bit 17_244 +bit 17_245 +bit 17_246 +bit 17_247 +bit 17_248 +bit 17_249 +bit 17_25 +bit 17_250 +bit 17_251 +bit 17_252 +bit 17_253 +bit 17_254 +bit 17_255 +bit 17_256 +bit 17_257 +bit 17_258 +bit 17_259 +bit 17_26 +bit 17_260 +bit 17_261 +bit 17_262 +bit 17_263 +bit 17_264 +bit 17_265 +bit 17_266 +bit 17_267 +bit 17_268 +bit 17_269 +bit 17_27 +bit 17_270 +bit 17_271 +bit 17_272 +bit 17_273 +bit 17_274 +bit 17_275 +bit 17_276 +bit 17_277 +bit 17_278 +bit 17_279 +bit 17_28 +bit 17_280 +bit 17_281 +bit 17_282 +bit 17_283 +bit 17_284 +bit 17_285 +bit 17_286 +bit 17_287 +bit 17_288 +bit 17_289 +bit 17_29 +bit 17_290 +bit 17_291 +bit 17_292 +bit 17_293 +bit 17_294 +bit 17_295 +bit 17_296 +bit 17_297 +bit 17_298 +bit 17_299 +bit 17_30 +bit 17_300 +bit 17_301 +bit 17_302 +bit 17_303 +bit 17_304 +bit 17_305 +bit 17_306 +bit 17_307 +bit 17_308 +bit 17_309 +bit 17_31 +bit 17_310 +bit 17_311 +bit 17_312 +bit 17_313 +bit 17_314 +bit 17_315 +bit 17_316 +bit 17_317 +bit 17_318 +bit 17_319 +bit 17_32 +bit 17_33 +bit 17_34 +bit 17_35 +bit 17_36 +bit 17_37 +bit 17_38 +bit 17_39 +bit 17_40 +bit 17_41 +bit 17_42 +bit 17_43 +bit 17_44 +bit 17_45 +bit 17_46 +bit 17_47 +bit 17_48 +bit 17_49 +bit 17_50 +bit 17_51 +bit 17_52 +bit 17_53 +bit 17_54 +bit 17_55 +bit 17_56 +bit 17_57 +bit 17_58 +bit 17_59 +bit 17_60 +bit 17_61 +bit 17_62 +bit 17_63 +bit 17_64 +bit 17_65 +bit 17_66 +bit 17_67 +bit 17_68 +bit 17_69 +bit 17_70 +bit 17_71 +bit 17_72 +bit 17_73 +bit 17_74 +bit 17_75 +bit 17_76 +bit 17_77 +bit 17_78 +bit 17_79 +bit 17_80 +bit 17_81 +bit 17_82 +bit 17_83 +bit 17_84 +bit 17_85 +bit 17_86 +bit 17_87 +bit 17_88 +bit 17_89 +bit 17_90 +bit 17_91 +bit 17_92 +bit 17_93 +bit 17_94 +bit 17_95 +bit 17_96 +bit 17_97 +bit 17_98 +bit 17_99 +bit 18_00 +bit 18_01 +bit 18_02 +bit 18_03 +bit 18_04 +bit 18_05 +bit 18_06 +bit 18_07 +bit 18_08 +bit 18_09 +bit 18_10 +bit 18_100 +bit 18_101 +bit 18_102 +bit 18_103 +bit 18_104 +bit 18_105 +bit 18_106 +bit 18_107 +bit 18_108 +bit 18_109 +bit 18_11 +bit 18_110 +bit 18_111 +bit 18_112 +bit 18_113 +bit 18_114 +bit 18_115 +bit 18_116 +bit 18_117 +bit 18_118 +bit 18_119 +bit 18_12 +bit 18_120 +bit 18_121 +bit 18_122 +bit 18_123 +bit 18_124 +bit 18_125 +bit 18_126 +bit 18_127 +bit 18_128 +bit 18_129 +bit 18_13 +bit 18_130 +bit 18_131 +bit 18_132 +bit 18_133 +bit 18_134 +bit 18_135 +bit 18_136 +bit 18_137 +bit 18_138 +bit 18_139 +bit 18_14 +bit 18_140 +bit 18_141 +bit 18_142 +bit 18_143 +bit 18_144 +bit 18_145 +bit 18_146 +bit 18_147 +bit 18_148 +bit 18_149 +bit 18_15 +bit 18_150 +bit 18_151 +bit 18_152 +bit 18_153 +bit 18_154 +bit 18_155 +bit 18_156 +bit 18_157 +bit 18_158 +bit 18_159 +bit 18_16 +bit 18_160 +bit 18_161 +bit 18_162 +bit 18_163 +bit 18_164 +bit 18_165 +bit 18_166 +bit 18_167 +bit 18_168 +bit 18_169 +bit 18_17 +bit 18_170 +bit 18_171 +bit 18_172 +bit 18_173 +bit 18_174 +bit 18_175 +bit 18_176 +bit 18_177 +bit 18_178 +bit 18_179 +bit 18_18 +bit 18_180 +bit 18_181 +bit 18_182 +bit 18_183 +bit 18_184 +bit 18_185 +bit 18_186 +bit 18_187 +bit 18_188 +bit 18_189 +bit 18_19 +bit 18_190 +bit 18_191 +bit 18_192 +bit 18_193 +bit 18_194 +bit 18_195 +bit 18_196 +bit 18_197 +bit 18_198 +bit 18_199 +bit 18_20 +bit 18_200 +bit 18_201 +bit 18_202 +bit 18_203 +bit 18_204 +bit 18_205 +bit 18_206 +bit 18_207 +bit 18_208 +bit 18_209 +bit 18_21 +bit 18_210 +bit 18_211 +bit 18_212 +bit 18_213 +bit 18_214 +bit 18_215 +bit 18_216 +bit 18_217 +bit 18_218 +bit 18_219 +bit 18_22 +bit 18_220 +bit 18_221 +bit 18_222 +bit 18_223 +bit 18_224 +bit 18_225 +bit 18_226 +bit 18_227 +bit 18_228 +bit 18_229 +bit 18_23 +bit 18_230 +bit 18_231 +bit 18_232 +bit 18_233 +bit 18_234 +bit 18_235 +bit 18_236 +bit 18_237 +bit 18_238 +bit 18_239 +bit 18_24 +bit 18_240 +bit 18_241 +bit 18_242 +bit 18_243 +bit 18_244 +bit 18_245 +bit 18_246 +bit 18_247 +bit 18_248 +bit 18_249 +bit 18_25 +bit 18_250 +bit 18_251 +bit 18_252 +bit 18_253 +bit 18_254 +bit 18_255 +bit 18_256 +bit 18_257 +bit 18_258 +bit 18_259 +bit 18_26 +bit 18_260 +bit 18_261 +bit 18_262 +bit 18_263 +bit 18_264 +bit 18_265 +bit 18_266 +bit 18_267 +bit 18_268 +bit 18_269 +bit 18_27 +bit 18_270 +bit 18_271 +bit 18_272 +bit 18_273 +bit 18_274 +bit 18_275 +bit 18_276 +bit 18_277 +bit 18_278 +bit 18_279 +bit 18_28 +bit 18_280 +bit 18_281 +bit 18_282 +bit 18_283 +bit 18_284 +bit 18_285 +bit 18_286 +bit 18_287 +bit 18_288 +bit 18_289 +bit 18_29 +bit 18_290 +bit 18_291 +bit 18_292 +bit 18_293 +bit 18_294 +bit 18_295 +bit 18_296 +bit 18_297 +bit 18_298 +bit 18_299 +bit 18_30 +bit 18_300 +bit 18_301 +bit 18_302 +bit 18_303 +bit 18_304 +bit 18_305 +bit 18_306 +bit 18_307 +bit 18_308 +bit 18_309 +bit 18_31 +bit 18_310 +bit 18_311 +bit 18_312 +bit 18_313 +bit 18_314 +bit 18_315 +bit 18_316 +bit 18_317 +bit 18_318 +bit 18_319 +bit 18_32 +bit 18_33 +bit 18_34 +bit 18_35 +bit 18_36 +bit 18_37 +bit 18_38 +bit 18_39 +bit 18_40 +bit 18_41 +bit 18_42 +bit 18_43 +bit 18_44 +bit 18_45 +bit 18_46 +bit 18_47 +bit 18_48 +bit 18_49 +bit 18_50 +bit 18_51 +bit 18_52 +bit 18_53 +bit 18_54 +bit 18_55 +bit 18_56 +bit 18_57 +bit 18_58 +bit 18_59 +bit 18_60 +bit 18_61 +bit 18_62 +bit 18_63 +bit 18_64 +bit 18_65 +bit 18_66 +bit 18_67 +bit 18_68 +bit 18_69 +bit 18_70 +bit 18_71 +bit 18_72 +bit 18_73 +bit 18_74 +bit 18_75 +bit 18_76 +bit 18_77 +bit 18_78 +bit 18_79 +bit 18_80 +bit 18_81 +bit 18_82 +bit 18_83 +bit 18_84 +bit 18_85 +bit 18_86 +bit 18_87 +bit 18_88 +bit 18_89 +bit 18_90 +bit 18_91 +bit 18_92 +bit 18_93 +bit 18_94 +bit 18_95 +bit 18_96 +bit 18_97 +bit 18_98 +bit 18_99 +bit 19_00 +bit 19_01 +bit 19_02 +bit 19_03 +bit 19_04 +bit 19_05 +bit 19_06 +bit 19_07 +bit 19_08 +bit 19_09 +bit 19_10 +bit 19_100 +bit 19_101 +bit 19_102 +bit 19_103 +bit 19_104 +bit 19_105 +bit 19_106 +bit 19_107 +bit 19_108 +bit 19_109 +bit 19_11 +bit 19_110 +bit 19_111 +bit 19_112 +bit 19_113 +bit 19_114 +bit 19_115 +bit 19_116 +bit 19_117 +bit 19_118 +bit 19_119 +bit 19_12 +bit 19_120 +bit 19_121 +bit 19_122 +bit 19_123 +bit 19_124 +bit 19_125 +bit 19_126 +bit 19_127 +bit 19_128 +bit 19_129 +bit 19_13 +bit 19_130 +bit 19_131 +bit 19_132 +bit 19_133 +bit 19_134 +bit 19_135 +bit 19_136 +bit 19_137 +bit 19_138 +bit 19_139 +bit 19_14 +bit 19_140 +bit 19_141 +bit 19_142 +bit 19_143 +bit 19_144 +bit 19_145 +bit 19_146 +bit 19_147 +bit 19_148 +bit 19_149 +bit 19_15 +bit 19_150 +bit 19_151 +bit 19_152 +bit 19_153 +bit 19_154 +bit 19_155 +bit 19_156 +bit 19_157 +bit 19_158 +bit 19_159 +bit 19_16 +bit 19_160 +bit 19_161 +bit 19_162 +bit 19_163 +bit 19_164 +bit 19_165 +bit 19_166 +bit 19_167 +bit 19_168 +bit 19_169 +bit 19_17 +bit 19_170 +bit 19_171 +bit 19_172 +bit 19_173 +bit 19_174 +bit 19_175 +bit 19_176 +bit 19_177 +bit 19_178 +bit 19_179 +bit 19_18 +bit 19_180 +bit 19_181 +bit 19_182 +bit 19_183 +bit 19_184 +bit 19_185 +bit 19_186 +bit 19_187 +bit 19_188 +bit 19_189 +bit 19_19 +bit 19_190 +bit 19_191 +bit 19_192 +bit 19_193 +bit 19_194 +bit 19_195 +bit 19_196 +bit 19_197 +bit 19_198 +bit 19_199 +bit 19_20 +bit 19_200 +bit 19_201 +bit 19_202 +bit 19_203 +bit 19_204 +bit 19_205 +bit 19_206 +bit 19_207 +bit 19_208 +bit 19_209 +bit 19_21 +bit 19_210 +bit 19_211 +bit 19_212 +bit 19_213 +bit 19_214 +bit 19_215 +bit 19_216 +bit 19_217 +bit 19_218 +bit 19_219 +bit 19_22 +bit 19_220 +bit 19_221 +bit 19_222 +bit 19_223 +bit 19_224 +bit 19_225 +bit 19_226 +bit 19_227 +bit 19_228 +bit 19_229 +bit 19_23 +bit 19_230 +bit 19_231 +bit 19_232 +bit 19_233 +bit 19_234 +bit 19_235 +bit 19_236 +bit 19_237 +bit 19_238 +bit 19_239 +bit 19_24 +bit 19_240 +bit 19_241 +bit 19_242 +bit 19_243 +bit 19_244 +bit 19_245 +bit 19_246 +bit 19_247 +bit 19_248 +bit 19_249 +bit 19_25 +bit 19_250 +bit 19_251 +bit 19_252 +bit 19_253 +bit 19_254 +bit 19_255 +bit 19_256 +bit 19_257 +bit 19_258 +bit 19_259 +bit 19_26 +bit 19_260 +bit 19_261 +bit 19_262 +bit 19_263 +bit 19_264 +bit 19_265 +bit 19_266 +bit 19_267 +bit 19_268 +bit 19_269 +bit 19_27 +bit 19_270 +bit 19_271 +bit 19_272 +bit 19_273 +bit 19_274 +bit 19_275 +bit 19_276 +bit 19_277 +bit 19_278 +bit 19_279 +bit 19_28 +bit 19_280 +bit 19_281 +bit 19_282 +bit 19_283 +bit 19_284 +bit 19_285 +bit 19_286 +bit 19_287 +bit 19_288 +bit 19_289 +bit 19_29 +bit 19_290 +bit 19_291 +bit 19_292 +bit 19_293 +bit 19_294 +bit 19_295 +bit 19_296 +bit 19_297 +bit 19_298 +bit 19_299 +bit 19_30 +bit 19_300 +bit 19_301 +bit 19_302 +bit 19_303 +bit 19_304 +bit 19_305 +bit 19_306 +bit 19_307 +bit 19_308 +bit 19_309 +bit 19_31 +bit 19_310 +bit 19_311 +bit 19_312 +bit 19_313 +bit 19_314 +bit 19_315 +bit 19_316 +bit 19_317 +bit 19_318 +bit 19_319 +bit 19_32 +bit 19_33 +bit 19_34 +bit 19_35 +bit 19_36 +bit 19_37 +bit 19_38 +bit 19_39 +bit 19_40 +bit 19_41 +bit 19_42 +bit 19_43 +bit 19_44 +bit 19_45 +bit 19_46 +bit 19_47 +bit 19_48 +bit 19_49 +bit 19_50 +bit 19_51 +bit 19_52 +bit 19_53 +bit 19_54 +bit 19_55 +bit 19_56 +bit 19_57 +bit 19_58 +bit 19_59 +bit 19_60 +bit 19_61 +bit 19_62 +bit 19_63 +bit 19_64 +bit 19_65 +bit 19_66 +bit 19_67 +bit 19_68 +bit 19_69 +bit 19_70 +bit 19_71 +bit 19_72 +bit 19_73 +bit 19_74 +bit 19_75 +bit 19_76 +bit 19_77 +bit 19_78 +bit 19_79 +bit 19_80 +bit 19_81 +bit 19_82 +bit 19_83 +bit 19_84 +bit 19_85 +bit 19_86 +bit 19_87 +bit 19_88 +bit 19_89 +bit 19_90 +bit 19_91 +bit 19_92 +bit 19_93 +bit 19_94 +bit 19_95 +bit 19_96 +bit 19_97 +bit 19_98 +bit 19_99 +bit 20_00 +bit 20_01 +bit 20_02 +bit 20_03 +bit 20_04 +bit 20_05 +bit 20_06 +bit 20_07 +bit 20_08 +bit 20_09 +bit 20_10 +bit 20_100 +bit 20_101 +bit 20_102 +bit 20_103 +bit 20_104 +bit 20_105 +bit 20_106 +bit 20_107 +bit 20_108 +bit 20_109 +bit 20_11 +bit 20_110 +bit 20_111 +bit 20_112 +bit 20_113 +bit 20_114 +bit 20_115 +bit 20_116 +bit 20_117 +bit 20_118 +bit 20_119 +bit 20_12 +bit 20_120 +bit 20_121 +bit 20_122 +bit 20_123 +bit 20_124 +bit 20_125 +bit 20_126 +bit 20_127 +bit 20_128 +bit 20_129 +bit 20_13 +bit 20_130 +bit 20_131 +bit 20_132 +bit 20_133 +bit 20_134 +bit 20_135 +bit 20_136 +bit 20_137 +bit 20_138 +bit 20_139 +bit 20_14 +bit 20_140 +bit 20_141 +bit 20_142 +bit 20_143 +bit 20_144 +bit 20_145 +bit 20_146 +bit 20_147 +bit 20_148 +bit 20_149 +bit 20_15 +bit 20_150 +bit 20_151 +bit 20_152 +bit 20_153 +bit 20_154 +bit 20_155 +bit 20_156 +bit 20_157 +bit 20_158 +bit 20_159 +bit 20_16 +bit 20_160 +bit 20_161 +bit 20_162 +bit 20_163 +bit 20_164 +bit 20_165 +bit 20_166 +bit 20_167 +bit 20_168 +bit 20_169 +bit 20_17 +bit 20_170 +bit 20_171 +bit 20_172 +bit 20_173 +bit 20_174 +bit 20_175 +bit 20_176 +bit 20_177 +bit 20_178 +bit 20_179 +bit 20_18 +bit 20_180 +bit 20_181 +bit 20_182 +bit 20_183 +bit 20_184 +bit 20_185 +bit 20_186 +bit 20_187 +bit 20_188 +bit 20_189 +bit 20_19 +bit 20_190 +bit 20_191 +bit 20_192 +bit 20_193 +bit 20_194 +bit 20_195 +bit 20_196 +bit 20_197 +bit 20_198 +bit 20_199 +bit 20_20 +bit 20_200 +bit 20_201 +bit 20_202 +bit 20_203 +bit 20_204 +bit 20_205 +bit 20_206 +bit 20_207 +bit 20_208 +bit 20_209 +bit 20_21 +bit 20_210 +bit 20_211 +bit 20_212 +bit 20_213 +bit 20_214 +bit 20_215 +bit 20_216 +bit 20_217 +bit 20_218 +bit 20_219 +bit 20_22 +bit 20_220 +bit 20_221 +bit 20_222 +bit 20_223 +bit 20_224 +bit 20_225 +bit 20_226 +bit 20_227 +bit 20_228 +bit 20_229 +bit 20_23 +bit 20_230 +bit 20_231 +bit 20_232 +bit 20_233 +bit 20_234 +bit 20_235 +bit 20_236 +bit 20_237 +bit 20_238 +bit 20_239 +bit 20_24 +bit 20_240 +bit 20_241 +bit 20_242 +bit 20_243 +bit 20_244 +bit 20_245 +bit 20_246 +bit 20_247 +bit 20_248 +bit 20_249 +bit 20_25 +bit 20_250 +bit 20_251 +bit 20_252 +bit 20_253 +bit 20_254 +bit 20_255 +bit 20_256 +bit 20_257 +bit 20_258 +bit 20_259 +bit 20_26 +bit 20_260 +bit 20_261 +bit 20_262 +bit 20_263 +bit 20_264 +bit 20_265 +bit 20_266 +bit 20_267 +bit 20_268 +bit 20_269 +bit 20_27 +bit 20_270 +bit 20_271 +bit 20_272 +bit 20_273 +bit 20_274 +bit 20_275 +bit 20_276 +bit 20_277 +bit 20_278 +bit 20_279 +bit 20_28 +bit 20_280 +bit 20_281 +bit 20_282 +bit 20_283 +bit 20_284 +bit 20_285 +bit 20_286 +bit 20_287 +bit 20_288 +bit 20_289 +bit 20_29 +bit 20_290 +bit 20_291 +bit 20_292 +bit 20_293 +bit 20_294 +bit 20_295 +bit 20_296 +bit 20_297 +bit 20_298 +bit 20_299 +bit 20_30 +bit 20_300 +bit 20_301 +bit 20_302 +bit 20_303 +bit 20_304 +bit 20_305 +bit 20_306 +bit 20_307 +bit 20_308 +bit 20_309 +bit 20_31 +bit 20_310 +bit 20_311 +bit 20_312 +bit 20_313 +bit 20_314 +bit 20_315 +bit 20_316 +bit 20_317 +bit 20_318 +bit 20_319 +bit 20_32 +bit 20_33 +bit 20_34 +bit 20_35 +bit 20_36 +bit 20_37 +bit 20_38 +bit 20_39 +bit 20_40 +bit 20_41 +bit 20_42 +bit 20_43 +bit 20_44 +bit 20_45 +bit 20_46 +bit 20_47 +bit 20_48 +bit 20_49 +bit 20_50 +bit 20_51 +bit 20_52 +bit 20_53 +bit 20_54 +bit 20_55 +bit 20_56 +bit 20_57 +bit 20_58 +bit 20_59 +bit 20_60 +bit 20_61 +bit 20_62 +bit 20_63 +bit 20_64 +bit 20_65 +bit 20_66 +bit 20_67 +bit 20_68 +bit 20_69 +bit 20_70 +bit 20_71 +bit 20_72 +bit 20_73 +bit 20_74 +bit 20_75 +bit 20_76 +bit 20_77 +bit 20_78 +bit 20_79 +bit 20_80 +bit 20_81 +bit 20_82 +bit 20_83 +bit 20_84 +bit 20_85 +bit 20_86 +bit 20_87 +bit 20_88 +bit 20_89 +bit 20_90 +bit 20_91 +bit 20_92 +bit 20_93 +bit 20_94 +bit 20_95 +bit 20_96 +bit 20_97 +bit 20_98 +bit 20_99 +bit 21_00 +bit 21_01 +bit 21_02 +bit 21_03 +bit 21_04 +bit 21_05 +bit 21_06 +bit 21_07 +bit 21_08 +bit 21_09 +bit 21_10 +bit 21_100 +bit 21_101 +bit 21_102 +bit 21_103 +bit 21_104 +bit 21_105 +bit 21_106 +bit 21_107 +bit 21_108 +bit 21_109 +bit 21_11 +bit 21_110 +bit 21_111 +bit 21_112 +bit 21_113 +bit 21_114 +bit 21_115 +bit 21_116 +bit 21_117 +bit 21_118 +bit 21_119 +bit 21_12 +bit 21_120 +bit 21_121 +bit 21_122 +bit 21_123 +bit 21_124 +bit 21_125 +bit 21_126 +bit 21_127 +bit 21_128 +bit 21_129 +bit 21_13 +bit 21_130 +bit 21_131 +bit 21_132 +bit 21_133 +bit 21_134 +bit 21_135 +bit 21_136 +bit 21_137 +bit 21_138 +bit 21_139 +bit 21_14 +bit 21_140 +bit 21_141 +bit 21_142 +bit 21_143 +bit 21_144 +bit 21_145 +bit 21_146 +bit 21_147 +bit 21_148 +bit 21_149 +bit 21_15 +bit 21_150 +bit 21_151 +bit 21_152 +bit 21_153 +bit 21_154 +bit 21_155 +bit 21_156 +bit 21_157 +bit 21_158 +bit 21_159 +bit 21_16 +bit 21_160 +bit 21_161 +bit 21_162 +bit 21_163 +bit 21_164 +bit 21_165 +bit 21_166 +bit 21_167 +bit 21_168 +bit 21_169 +bit 21_17 +bit 21_170 +bit 21_171 +bit 21_172 +bit 21_173 +bit 21_174 +bit 21_175 +bit 21_176 +bit 21_177 +bit 21_178 +bit 21_179 +bit 21_18 +bit 21_180 +bit 21_181 +bit 21_182 +bit 21_183 +bit 21_184 +bit 21_185 +bit 21_186 +bit 21_187 +bit 21_188 +bit 21_189 +bit 21_19 +bit 21_190 +bit 21_191 +bit 21_192 +bit 21_193 +bit 21_194 +bit 21_195 +bit 21_196 +bit 21_197 +bit 21_198 +bit 21_199 +bit 21_20 +bit 21_200 +bit 21_201 +bit 21_202 +bit 21_203 +bit 21_204 +bit 21_205 +bit 21_206 +bit 21_207 +bit 21_208 +bit 21_209 +bit 21_21 +bit 21_210 +bit 21_211 +bit 21_212 +bit 21_213 +bit 21_214 +bit 21_215 +bit 21_216 +bit 21_217 +bit 21_218 +bit 21_219 +bit 21_22 +bit 21_220 +bit 21_221 +bit 21_222 +bit 21_223 +bit 21_224 +bit 21_225 +bit 21_226 +bit 21_227 +bit 21_228 +bit 21_229 +bit 21_23 +bit 21_230 +bit 21_231 +bit 21_232 +bit 21_233 +bit 21_234 +bit 21_235 +bit 21_236 +bit 21_237 +bit 21_238 +bit 21_239 +bit 21_24 +bit 21_240 +bit 21_241 +bit 21_242 +bit 21_243 +bit 21_244 +bit 21_245 +bit 21_246 +bit 21_247 +bit 21_248 +bit 21_249 +bit 21_25 +bit 21_250 +bit 21_251 +bit 21_252 +bit 21_253 +bit 21_254 +bit 21_255 +bit 21_256 +bit 21_257 +bit 21_258 +bit 21_259 +bit 21_26 +bit 21_260 +bit 21_261 +bit 21_262 +bit 21_263 +bit 21_264 +bit 21_265 +bit 21_266 +bit 21_267 +bit 21_268 +bit 21_269 +bit 21_27 +bit 21_270 +bit 21_271 +bit 21_272 +bit 21_273 +bit 21_274 +bit 21_275 +bit 21_276 +bit 21_277 +bit 21_278 +bit 21_279 +bit 21_28 +bit 21_280 +bit 21_281 +bit 21_282 +bit 21_283 +bit 21_284 +bit 21_285 +bit 21_286 +bit 21_287 +bit 21_288 +bit 21_289 +bit 21_29 +bit 21_290 +bit 21_291 +bit 21_292 +bit 21_293 +bit 21_294 +bit 21_295 +bit 21_296 +bit 21_297 +bit 21_298 +bit 21_299 +bit 21_30 +bit 21_300 +bit 21_301 +bit 21_302 +bit 21_303 +bit 21_304 +bit 21_305 +bit 21_306 +bit 21_307 +bit 21_308 +bit 21_309 +bit 21_31 +bit 21_310 +bit 21_311 +bit 21_312 +bit 21_313 +bit 21_314 +bit 21_315 +bit 21_316 +bit 21_317 +bit 21_318 +bit 21_319 +bit 21_32 +bit 21_33 +bit 21_34 +bit 21_35 +bit 21_36 +bit 21_37 +bit 21_38 +bit 21_39 +bit 21_40 +bit 21_41 +bit 21_42 +bit 21_43 +bit 21_44 +bit 21_45 +bit 21_46 +bit 21_47 +bit 21_48 +bit 21_49 +bit 21_50 +bit 21_51 +bit 21_52 +bit 21_53 +bit 21_54 +bit 21_55 +bit 21_56 +bit 21_57 +bit 21_58 +bit 21_59 +bit 21_60 +bit 21_61 +bit 21_62 +bit 21_63 +bit 21_64 +bit 21_65 +bit 21_66 +bit 21_67 +bit 21_68 +bit 21_69 +bit 21_70 +bit 21_71 +bit 21_72 +bit 21_73 +bit 21_74 +bit 21_75 +bit 21_76 +bit 21_77 +bit 21_78 +bit 21_79 +bit 21_80 +bit 21_81 +bit 21_82 +bit 21_83 +bit 21_84 +bit 21_85 +bit 21_86 +bit 21_87 +bit 21_88 +bit 21_89 +bit 21_90 +bit 21_91 +bit 21_92 +bit 21_93 +bit 21_94 +bit 21_95 +bit 21_96 +bit 21_97 +bit 21_98 +bit 21_99 +bit 22_00 +bit 22_01 +bit 22_02 +bit 22_03 +bit 22_04 +bit 22_05 +bit 22_06 +bit 22_07 +bit 22_08 +bit 22_09 +bit 22_10 +bit 22_100 +bit 22_101 +bit 22_102 +bit 22_103 +bit 22_104 +bit 22_105 +bit 22_106 +bit 22_107 +bit 22_108 +bit 22_109 +bit 22_11 +bit 22_110 +bit 22_111 +bit 22_112 +bit 22_113 +bit 22_114 +bit 22_115 +bit 22_116 +bit 22_117 +bit 22_118 +bit 22_119 +bit 22_12 +bit 22_120 +bit 22_121 +bit 22_122 +bit 22_123 +bit 22_124 +bit 22_125 +bit 22_126 +bit 22_127 +bit 22_128 +bit 22_129 +bit 22_13 +bit 22_130 +bit 22_131 +bit 22_132 +bit 22_133 +bit 22_134 +bit 22_135 +bit 22_136 +bit 22_137 +bit 22_138 +bit 22_139 +bit 22_14 +bit 22_140 +bit 22_141 +bit 22_142 +bit 22_143 +bit 22_144 +bit 22_145 +bit 22_146 +bit 22_147 +bit 22_148 +bit 22_149 +bit 22_15 +bit 22_150 +bit 22_151 +bit 22_152 +bit 22_153 +bit 22_154 +bit 22_155 +bit 22_156 +bit 22_157 +bit 22_158 +bit 22_159 +bit 22_16 +bit 22_160 +bit 22_161 +bit 22_162 +bit 22_163 +bit 22_164 +bit 22_165 +bit 22_166 +bit 22_167 +bit 22_168 +bit 22_169 +bit 22_17 +bit 22_170 +bit 22_171 +bit 22_172 +bit 22_173 +bit 22_174 +bit 22_175 +bit 22_176 +bit 22_177 +bit 22_178 +bit 22_179 +bit 22_18 +bit 22_180 +bit 22_181 +bit 22_182 +bit 22_183 +bit 22_184 +bit 22_185 +bit 22_186 +bit 22_187 +bit 22_188 +bit 22_189 +bit 22_19 +bit 22_190 +bit 22_191 +bit 22_192 +bit 22_193 +bit 22_194 +bit 22_195 +bit 22_196 +bit 22_197 +bit 22_198 +bit 22_199 +bit 22_20 +bit 22_200 +bit 22_201 +bit 22_202 +bit 22_203 +bit 22_204 +bit 22_205 +bit 22_206 +bit 22_207 +bit 22_208 +bit 22_209 +bit 22_21 +bit 22_210 +bit 22_211 +bit 22_212 +bit 22_213 +bit 22_214 +bit 22_215 +bit 22_216 +bit 22_217 +bit 22_218 +bit 22_219 +bit 22_22 +bit 22_220 +bit 22_221 +bit 22_222 +bit 22_223 +bit 22_224 +bit 22_225 +bit 22_226 +bit 22_227 +bit 22_228 +bit 22_229 +bit 22_23 +bit 22_230 +bit 22_231 +bit 22_232 +bit 22_233 +bit 22_234 +bit 22_235 +bit 22_236 +bit 22_237 +bit 22_238 +bit 22_239 +bit 22_24 +bit 22_240 +bit 22_241 +bit 22_242 +bit 22_243 +bit 22_244 +bit 22_245 +bit 22_246 +bit 22_247 +bit 22_248 +bit 22_249 +bit 22_25 +bit 22_250 +bit 22_251 +bit 22_252 +bit 22_253 +bit 22_254 +bit 22_255 +bit 22_256 +bit 22_257 +bit 22_258 +bit 22_259 +bit 22_26 +bit 22_260 +bit 22_261 +bit 22_262 +bit 22_263 +bit 22_264 +bit 22_265 +bit 22_266 +bit 22_267 +bit 22_268 +bit 22_269 +bit 22_27 +bit 22_270 +bit 22_271 +bit 22_272 +bit 22_273 +bit 22_274 +bit 22_275 +bit 22_276 +bit 22_277 +bit 22_278 +bit 22_279 +bit 22_28 +bit 22_280 +bit 22_281 +bit 22_282 +bit 22_283 +bit 22_284 +bit 22_285 +bit 22_286 +bit 22_287 +bit 22_288 +bit 22_289 +bit 22_29 +bit 22_290 +bit 22_291 +bit 22_292 +bit 22_293 +bit 22_294 +bit 22_295 +bit 22_296 +bit 22_297 +bit 22_298 +bit 22_299 +bit 22_30 +bit 22_300 +bit 22_301 +bit 22_302 +bit 22_303 +bit 22_304 +bit 22_305 +bit 22_306 +bit 22_307 +bit 22_308 +bit 22_309 +bit 22_31 +bit 22_310 +bit 22_311 +bit 22_312 +bit 22_313 +bit 22_314 +bit 22_315 +bit 22_316 +bit 22_317 +bit 22_318 +bit 22_319 +bit 22_32 +bit 22_33 +bit 22_34 +bit 22_35 +bit 22_36 +bit 22_37 +bit 22_38 +bit 22_39 +bit 22_40 +bit 22_41 +bit 22_42 +bit 22_43 +bit 22_44 +bit 22_45 +bit 22_46 +bit 22_47 +bit 22_48 +bit 22_49 +bit 22_50 +bit 22_51 +bit 22_52 +bit 22_53 +bit 22_54 +bit 22_55 +bit 22_56 +bit 22_57 +bit 22_58 +bit 22_59 +bit 22_60 +bit 22_61 +bit 22_62 +bit 22_63 +bit 22_64 +bit 22_65 +bit 22_66 +bit 22_67 +bit 22_68 +bit 22_69 +bit 22_70 +bit 22_71 +bit 22_72 +bit 22_73 +bit 22_74 +bit 22_75 +bit 22_76 +bit 22_77 +bit 22_78 +bit 22_79 +bit 22_80 +bit 22_81 +bit 22_82 +bit 22_83 +bit 22_84 +bit 22_85 +bit 22_86 +bit 22_87 +bit 22_88 +bit 22_89 +bit 22_90 +bit 22_91 +bit 22_92 +bit 22_93 +bit 22_94 +bit 22_95 +bit 22_96 +bit 22_97 +bit 22_98 +bit 22_99 +bit 23_00 +bit 23_01 +bit 23_02 +bit 23_03 +bit 23_04 +bit 23_05 +bit 23_06 +bit 23_07 +bit 23_08 +bit 23_09 +bit 23_10 +bit 23_100 +bit 23_101 +bit 23_102 +bit 23_103 +bit 23_104 +bit 23_105 +bit 23_106 +bit 23_107 +bit 23_108 +bit 23_109 +bit 23_11 +bit 23_110 +bit 23_111 +bit 23_112 +bit 23_113 +bit 23_114 +bit 23_115 +bit 23_116 +bit 23_117 +bit 23_118 +bit 23_119 +bit 23_12 +bit 23_120 +bit 23_121 +bit 23_122 +bit 23_123 +bit 23_124 +bit 23_125 +bit 23_126 +bit 23_127 +bit 23_128 +bit 23_129 +bit 23_13 +bit 23_130 +bit 23_131 +bit 23_132 +bit 23_133 +bit 23_134 +bit 23_135 +bit 23_136 +bit 23_137 +bit 23_138 +bit 23_139 +bit 23_14 +bit 23_140 +bit 23_141 +bit 23_142 +bit 23_143 +bit 23_144 +bit 23_145 +bit 23_146 +bit 23_147 +bit 23_148 +bit 23_149 +bit 23_15 +bit 23_150 +bit 23_151 +bit 23_152 +bit 23_153 +bit 23_154 +bit 23_155 +bit 23_156 +bit 23_157 +bit 23_158 +bit 23_159 +bit 23_16 +bit 23_160 +bit 23_161 +bit 23_162 +bit 23_163 +bit 23_164 +bit 23_165 +bit 23_166 +bit 23_167 +bit 23_168 +bit 23_169 +bit 23_17 +bit 23_170 +bit 23_171 +bit 23_172 +bit 23_173 +bit 23_174 +bit 23_175 +bit 23_176 +bit 23_177 +bit 23_178 +bit 23_179 +bit 23_18 +bit 23_180 +bit 23_181 +bit 23_182 +bit 23_183 +bit 23_184 +bit 23_185 +bit 23_186 +bit 23_187 +bit 23_188 +bit 23_189 +bit 23_19 +bit 23_190 +bit 23_191 +bit 23_192 +bit 23_193 +bit 23_194 +bit 23_195 +bit 23_196 +bit 23_197 +bit 23_198 +bit 23_199 +bit 23_20 +bit 23_200 +bit 23_201 +bit 23_202 +bit 23_203 +bit 23_204 +bit 23_205 +bit 23_206 +bit 23_207 +bit 23_208 +bit 23_209 +bit 23_21 +bit 23_210 +bit 23_211 +bit 23_212 +bit 23_213 +bit 23_214 +bit 23_215 +bit 23_216 +bit 23_217 +bit 23_218 +bit 23_219 +bit 23_22 +bit 23_220 +bit 23_221 +bit 23_222 +bit 23_223 +bit 23_224 +bit 23_225 +bit 23_226 +bit 23_227 +bit 23_228 +bit 23_229 +bit 23_23 +bit 23_230 +bit 23_231 +bit 23_232 +bit 23_233 +bit 23_234 +bit 23_235 +bit 23_236 +bit 23_237 +bit 23_238 +bit 23_239 +bit 23_24 +bit 23_240 +bit 23_241 +bit 23_242 +bit 23_243 +bit 23_244 +bit 23_245 +bit 23_246 +bit 23_247 +bit 23_248 +bit 23_249 +bit 23_25 +bit 23_250 +bit 23_251 +bit 23_252 +bit 23_253 +bit 23_254 +bit 23_255 +bit 23_256 +bit 23_257 +bit 23_258 +bit 23_259 +bit 23_26 +bit 23_260 +bit 23_261 +bit 23_262 +bit 23_263 +bit 23_264 +bit 23_265 +bit 23_266 +bit 23_267 +bit 23_268 +bit 23_269 +bit 23_27 +bit 23_270 +bit 23_271 +bit 23_272 +bit 23_273 +bit 23_274 +bit 23_275 +bit 23_276 +bit 23_277 +bit 23_278 +bit 23_279 +bit 23_28 +bit 23_280 +bit 23_281 +bit 23_282 +bit 23_283 +bit 23_284 +bit 23_285 +bit 23_286 +bit 23_287 +bit 23_288 +bit 23_289 +bit 23_29 +bit 23_290 +bit 23_291 +bit 23_292 +bit 23_293 +bit 23_294 +bit 23_295 +bit 23_296 +bit 23_297 +bit 23_298 +bit 23_299 +bit 23_30 +bit 23_300 +bit 23_301 +bit 23_302 +bit 23_303 +bit 23_304 +bit 23_305 +bit 23_306 +bit 23_307 +bit 23_308 +bit 23_309 +bit 23_31 +bit 23_310 +bit 23_311 +bit 23_312 +bit 23_313 +bit 23_314 +bit 23_315 +bit 23_316 +bit 23_317 +bit 23_318 +bit 23_319 +bit 23_32 +bit 23_33 +bit 23_34 +bit 23_35 +bit 23_36 +bit 23_37 +bit 23_38 +bit 23_39 +bit 23_40 +bit 23_41 +bit 23_42 +bit 23_43 +bit 23_44 +bit 23_45 +bit 23_46 +bit 23_47 +bit 23_48 +bit 23_49 +bit 23_50 +bit 23_51 +bit 23_52 +bit 23_53 +bit 23_54 +bit 23_55 +bit 23_56 +bit 23_57 +bit 23_58 +bit 23_59 +bit 23_60 +bit 23_61 +bit 23_62 +bit 23_63 +bit 23_64 +bit 23_65 +bit 23_66 +bit 23_67 +bit 23_68 +bit 23_69 +bit 23_70 +bit 23_71 +bit 23_72 +bit 23_73 +bit 23_74 +bit 23_75 +bit 23_76 +bit 23_77 +bit 23_78 +bit 23_79 +bit 23_80 +bit 23_81 +bit 23_82 +bit 23_83 +bit 23_84 +bit 23_85 +bit 23_86 +bit 23_87 +bit 23_88 +bit 23_89 +bit 23_90 +bit 23_91 +bit 23_92 +bit 23_93 +bit 23_94 +bit 23_95 +bit 23_96 +bit 23_97 +bit 23_98 +bit 23_99 +bit 24_00 +bit 24_01 +bit 24_02 +bit 24_03 +bit 24_04 +bit 24_05 +bit 24_06 +bit 24_07 +bit 24_08 +bit 24_09 +bit 24_10 +bit 24_100 +bit 24_101 +bit 24_102 +bit 24_103 +bit 24_104 +bit 24_105 +bit 24_106 +bit 24_107 +bit 24_108 +bit 24_109 +bit 24_11 +bit 24_110 +bit 24_111 +bit 24_112 +bit 24_113 +bit 24_114 +bit 24_115 +bit 24_116 +bit 24_117 +bit 24_118 +bit 24_119 +bit 24_12 +bit 24_120 +bit 24_121 +bit 24_122 +bit 24_123 +bit 24_124 +bit 24_125 +bit 24_126 +bit 24_127 +bit 24_128 +bit 24_129 +bit 24_13 +bit 24_130 +bit 24_131 +bit 24_132 +bit 24_133 +bit 24_134 +bit 24_135 +bit 24_136 +bit 24_137 +bit 24_138 +bit 24_139 +bit 24_14 +bit 24_140 +bit 24_141 +bit 24_142 +bit 24_143 +bit 24_144 +bit 24_145 +bit 24_146 +bit 24_147 +bit 24_148 +bit 24_149 +bit 24_15 +bit 24_150 +bit 24_151 +bit 24_152 +bit 24_153 +bit 24_154 +bit 24_155 +bit 24_156 +bit 24_157 +bit 24_158 +bit 24_159 +bit 24_16 +bit 24_160 +bit 24_161 +bit 24_162 +bit 24_163 +bit 24_164 +bit 24_165 +bit 24_166 +bit 24_167 +bit 24_168 +bit 24_169 +bit 24_17 +bit 24_170 +bit 24_171 +bit 24_172 +bit 24_173 +bit 24_174 +bit 24_175 +bit 24_176 +bit 24_177 +bit 24_178 +bit 24_179 +bit 24_18 +bit 24_180 +bit 24_181 +bit 24_182 +bit 24_183 +bit 24_184 +bit 24_185 +bit 24_186 +bit 24_187 +bit 24_188 +bit 24_189 +bit 24_19 +bit 24_190 +bit 24_191 +bit 24_192 +bit 24_193 +bit 24_194 +bit 24_195 +bit 24_196 +bit 24_197 +bit 24_198 +bit 24_199 +bit 24_20 +bit 24_200 +bit 24_201 +bit 24_202 +bit 24_203 +bit 24_204 +bit 24_205 +bit 24_206 +bit 24_207 +bit 24_208 +bit 24_209 +bit 24_21 +bit 24_210 +bit 24_211 +bit 24_212 +bit 24_213 +bit 24_214 +bit 24_215 +bit 24_216 +bit 24_217 +bit 24_218 +bit 24_219 +bit 24_22 +bit 24_220 +bit 24_221 +bit 24_222 +bit 24_223 +bit 24_224 +bit 24_225 +bit 24_226 +bit 24_227 +bit 24_228 +bit 24_229 +bit 24_23 +bit 24_230 +bit 24_231 +bit 24_232 +bit 24_233 +bit 24_234 +bit 24_235 +bit 24_236 +bit 24_237 +bit 24_238 +bit 24_239 +bit 24_24 +bit 24_240 +bit 24_241 +bit 24_242 +bit 24_243 +bit 24_244 +bit 24_245 +bit 24_246 +bit 24_247 +bit 24_248 +bit 24_249 +bit 24_25 +bit 24_250 +bit 24_251 +bit 24_252 +bit 24_253 +bit 24_254 +bit 24_255 +bit 24_256 +bit 24_257 +bit 24_258 +bit 24_259 +bit 24_26 +bit 24_260 +bit 24_261 +bit 24_262 +bit 24_263 +bit 24_264 +bit 24_265 +bit 24_266 +bit 24_267 +bit 24_268 +bit 24_269 +bit 24_27 +bit 24_270 +bit 24_271 +bit 24_272 +bit 24_273 +bit 24_274 +bit 24_275 +bit 24_276 +bit 24_277 +bit 24_278 +bit 24_279 +bit 24_28 +bit 24_280 +bit 24_281 +bit 24_282 +bit 24_283 +bit 24_284 +bit 24_285 +bit 24_286 +bit 24_287 +bit 24_288 +bit 24_289 +bit 24_29 +bit 24_290 +bit 24_291 +bit 24_292 +bit 24_293 +bit 24_294 +bit 24_295 +bit 24_296 +bit 24_297 +bit 24_298 +bit 24_299 +bit 24_30 +bit 24_300 +bit 24_301 +bit 24_302 +bit 24_303 +bit 24_304 +bit 24_305 +bit 24_306 +bit 24_307 +bit 24_308 +bit 24_309 +bit 24_31 +bit 24_310 +bit 24_311 +bit 24_312 +bit 24_313 +bit 24_314 +bit 24_315 +bit 24_316 +bit 24_317 +bit 24_318 +bit 24_319 +bit 24_32 +bit 24_33 +bit 24_34 +bit 24_35 +bit 24_36 +bit 24_37 +bit 24_38 +bit 24_39 +bit 24_40 +bit 24_41 +bit 24_42 +bit 24_43 +bit 24_44 +bit 24_45 +bit 24_46 +bit 24_47 +bit 24_48 +bit 24_49 +bit 24_50 +bit 24_51 +bit 24_52 +bit 24_53 +bit 24_54 +bit 24_55 +bit 24_56 +bit 24_57 +bit 24_58 +bit 24_59 +bit 24_60 +bit 24_61 +bit 24_62 +bit 24_63 +bit 24_64 +bit 24_65 +bit 24_66 +bit 24_67 +bit 24_68 +bit 24_69 +bit 24_70 +bit 24_71 +bit 24_72 +bit 24_73 +bit 24_74 +bit 24_75 +bit 24_76 +bit 24_77 +bit 24_78 +bit 24_79 +bit 24_80 +bit 24_81 +bit 24_82 +bit 24_83 +bit 24_84 +bit 24_85 +bit 24_86 +bit 24_87 +bit 24_88 +bit 24_89 +bit 24_90 +bit 24_91 +bit 24_92 +bit 24_93 +bit 24_94 +bit 24_95 +bit 24_96 +bit 24_97 +bit 24_98 +bit 24_99 +bit 25_00 +bit 25_01 +bit 25_02 +bit 25_03 +bit 25_04 +bit 25_05 +bit 25_06 +bit 25_07 +bit 25_08 +bit 25_09 +bit 25_10 +bit 25_100 +bit 25_101 +bit 25_102 +bit 25_103 +bit 25_104 +bit 25_105 +bit 25_106 +bit 25_107 +bit 25_108 +bit 25_109 +bit 25_11 +bit 25_110 +bit 25_111 +bit 25_112 +bit 25_113 +bit 25_114 +bit 25_115 +bit 25_116 +bit 25_117 +bit 25_118 +bit 25_119 +bit 25_12 +bit 25_120 +bit 25_121 +bit 25_122 +bit 25_123 +bit 25_124 +bit 25_125 +bit 25_126 +bit 25_127 +bit 25_128 +bit 25_129 +bit 25_13 +bit 25_130 +bit 25_131 +bit 25_132 +bit 25_133 +bit 25_134 +bit 25_135 +bit 25_136 +bit 25_137 +bit 25_138 +bit 25_139 +bit 25_14 +bit 25_140 +bit 25_141 +bit 25_142 +bit 25_143 +bit 25_144 +bit 25_145 +bit 25_146 +bit 25_147 +bit 25_148 +bit 25_149 +bit 25_15 +bit 25_150 +bit 25_151 +bit 25_152 +bit 25_153 +bit 25_154 +bit 25_155 +bit 25_156 +bit 25_157 +bit 25_158 +bit 25_159 +bit 25_16 +bit 25_160 +bit 25_161 +bit 25_162 +bit 25_163 +bit 25_164 +bit 25_165 +bit 25_166 +bit 25_167 +bit 25_168 +bit 25_169 +bit 25_17 +bit 25_170 +bit 25_171 +bit 25_172 +bit 25_173 +bit 25_174 +bit 25_175 +bit 25_176 +bit 25_177 +bit 25_178 +bit 25_179 +bit 25_18 +bit 25_180 +bit 25_181 +bit 25_182 +bit 25_183 +bit 25_184 +bit 25_185 +bit 25_186 +bit 25_187 +bit 25_188 +bit 25_189 +bit 25_19 +bit 25_190 +bit 25_191 +bit 25_192 +bit 25_193 +bit 25_194 +bit 25_195 +bit 25_196 +bit 25_197 +bit 25_198 +bit 25_199 +bit 25_20 +bit 25_200 +bit 25_201 +bit 25_202 +bit 25_203 +bit 25_204 +bit 25_205 +bit 25_206 +bit 25_207 +bit 25_208 +bit 25_209 +bit 25_21 +bit 25_210 +bit 25_211 +bit 25_212 +bit 25_213 +bit 25_214 +bit 25_215 +bit 25_216 +bit 25_217 +bit 25_218 +bit 25_219 +bit 25_22 +bit 25_220 +bit 25_221 +bit 25_222 +bit 25_223 +bit 25_224 +bit 25_225 +bit 25_226 +bit 25_227 +bit 25_228 +bit 25_229 +bit 25_23 +bit 25_230 +bit 25_231 +bit 25_232 +bit 25_233 +bit 25_234 +bit 25_235 +bit 25_236 +bit 25_237 +bit 25_238 +bit 25_239 +bit 25_24 +bit 25_240 +bit 25_241 +bit 25_242 +bit 25_243 +bit 25_244 +bit 25_245 +bit 25_246 +bit 25_247 +bit 25_248 +bit 25_249 +bit 25_25 +bit 25_250 +bit 25_251 +bit 25_252 +bit 25_253 +bit 25_254 +bit 25_255 +bit 25_256 +bit 25_257 +bit 25_258 +bit 25_259 +bit 25_26 +bit 25_260 +bit 25_261 +bit 25_262 +bit 25_263 +bit 25_264 +bit 25_265 +bit 25_266 +bit 25_267 +bit 25_268 +bit 25_269 +bit 25_27 +bit 25_270 +bit 25_271 +bit 25_272 +bit 25_273 +bit 25_274 +bit 25_275 +bit 25_276 +bit 25_277 +bit 25_278 +bit 25_279 +bit 25_28 +bit 25_280 +bit 25_281 +bit 25_282 +bit 25_283 +bit 25_284 +bit 25_285 +bit 25_286 +bit 25_287 +bit 25_288 +bit 25_289 +bit 25_29 +bit 25_290 +bit 25_291 +bit 25_292 +bit 25_293 +bit 25_294 +bit 25_295 +bit 25_296 +bit 25_297 +bit 25_298 +bit 25_299 +bit 25_30 +bit 25_300 +bit 25_301 +bit 25_302 +bit 25_303 +bit 25_304 +bit 25_305 +bit 25_306 +bit 25_307 +bit 25_308 +bit 25_309 +bit 25_31 +bit 25_310 +bit 25_311 +bit 25_312 +bit 25_313 +bit 25_314 +bit 25_315 +bit 25_316 +bit 25_317 +bit 25_318 +bit 25_319 +bit 25_32 +bit 25_33 +bit 25_34 +bit 25_35 +bit 25_36 +bit 25_37 +bit 25_38 +bit 25_39 +bit 25_40 +bit 25_41 +bit 25_42 +bit 25_43 +bit 25_44 +bit 25_45 +bit 25_46 +bit 25_47 +bit 25_48 +bit 25_49 +bit 25_50 +bit 25_51 +bit 25_52 +bit 25_53 +bit 25_54 +bit 25_55 +bit 25_56 +bit 25_57 +bit 25_58 +bit 25_59 +bit 25_60 +bit 25_61 +bit 25_62 +bit 25_63 +bit 25_64 +bit 25_65 +bit 25_66 +bit 25_67 +bit 25_68 +bit 25_69 +bit 25_70 +bit 25_71 +bit 25_72 +bit 25_73 +bit 25_74 +bit 25_75 +bit 25_76 +bit 25_77 +bit 25_78 +bit 25_79 +bit 25_80 +bit 25_81 +bit 25_82 +bit 25_83 +bit 25_84 +bit 25_85 +bit 25_86 +bit 25_87 +bit 25_88 +bit 25_89 +bit 25_90 +bit 25_91 +bit 25_92 +bit 25_93 +bit 25_94 +bit 25_95 +bit 25_96 +bit 25_97 +bit 25_98 +bit 25_99 +bit 27_01 +bit 27_02 +bit 27_06 +bit 27_07 +bit 27_09 +bit 27_10 +bit 27_102 +bit 27_103 +bit 27_105 +bit 27_106 +bit 27_107 +bit 27_109 +bit 27_110 +bit 27_111 +bit 27_112 +bit 27_113 +bit 27_114 +bit 27_115 +bit 27_116 +bit 27_117 +bit 27_118 +bit 27_119 +bit 27_120 +bit 27_121 +bit 27_122 +bit 27_123 +bit 27_126 +bit 27_127 +bit 27_129 +bit 27_130 +bit 27_134 +bit 27_135 +bit 27_137 +bit 27_138 +bit 27_14 +bit 27_142 +bit 27_143 +bit 27_15 +bit 27_17 +bit 27_177 +bit 27_178 +bit 27_18 +bit 27_182 +bit 27_183 +bit 27_185 +bit 27_186 +bit 27_190 +bit 27_191 +bit 27_193 +bit 27_194 +bit 27_197 +bit 27_198 +bit 27_199 +bit 27_200 +bit 27_201 +bit 27_202 +bit 27_203 +bit 27_204 +bit 27_205 +bit 27_206 +bit 27_207 +bit 27_208 +bit 27_209 +bit 27_210 +bit 27_211 +bit 27_213 +bit 27_214 +bit 27_215 +bit 27_217 +bit 27_218 +bit 27_22 +bit 27_222 +bit 27_223 +bit 27_225 +bit 27_226 +bit 27_23 +bit 27_230 +bit 27_231 +bit 27_233 +bit 27_234 +bit 27_238 +bit 27_239 +bit 27_241 +bit 27_242 +bit 27_246 +bit 27_247 +bit 27_249 +bit 27_25 +bit 27_250 +bit 27_252 +bit 27_253 +bit 27_254 +bit 27_255 +bit 27_256 +bit 27_257 +bit 27_258 +bit 27_259 +bit 27_26 +bit 27_260 +bit 27_261 +bit 27_262 +bit 27_263 +bit 27_264 +bit 27_265 +bit 27_266 +bit 27_267 +bit 27_268 +bit 27_269 +bit 27_270 +bit 27_271 +bit 27_273 +bit 27_274 +bit 27_275 +bit 27_276 +bit 27_277 +bit 27_278 +bit 27_279 +bit 27_281 +bit 27_282 +bit 27_283 +bit 27_284 +bit 27_285 +bit 27_286 +bit 27_287 +bit 27_289 +bit 27_290 +bit 27_294 +bit 27_295 +bit 27_297 +bit 27_298 +bit 27_30 +bit 27_302 +bit 27_303 +bit 27_305 +bit 27_306 +bit 27_31 +bit 27_310 +bit 27_311 +bit 27_313 +bit 27_314 +bit 27_318 +bit 27_319 +bit 27_33 +bit 27_34 +bit 27_35 +bit 27_36 +bit 27_37 +bit 27_38 +bit 27_39 +bit 27_41 +bit 27_42 +bit 27_43 +bit 27_44 +bit 27_45 +bit 27_46 +bit 27_47 +bit 27_49 +bit 27_50 +bit 27_51 +bit 27_52 +bit 27_53 +bit 27_54 +bit 27_55 +bit 27_56 +bit 27_57 +bit 27_58 +bit 27_59 +bit 27_60 +bit 27_61 +bit 27_62 +bit 27_63 +bit 27_64 +bit 27_65 +bit 27_66 +bit 27_67 +bit 27_68 +bit 27_70 +bit 27_71 +bit 27_73 +bit 27_74 +bit 27_78 +bit 27_79 +bit 27_81 +bit 27_82 +bit 27_86 +bit 27_87 +bit 27_89 +bit 27_90 +bit 27_94 +bit 27_95 +bit 27_97 +bit 27_98 +bit 30_02 +bit 30_101 +bit 30_124 +bit 30_130 +bit 30_153 +bit 30_165 +bit 30_188 +bit 30_194 +bit 30_217 +bit 30_229 +bit 30_25 +bit 30_252 +bit 30_258 +bit 30_281 +bit 30_293 +bit 30_316 +bit 30_37 +bit 30_60 +bit 30_66 +bit 30_89 +bit 31_02 +bit 31_101 +bit 31_126 +bit 31_130 +bit 31_154 +bit 31_165 +bit 31_190 +bit 31_194 +bit 31_218 +bit 31_229 +bit 31_254 +bit 31_258 +bit 31_26 +bit 31_282 +bit 31_293 +bit 31_318 +bit 31_37 +bit 31_62 +bit 31_66 +bit 31_90 diff --git a/kintex7/mask_bram_r.db b/kintex7/mask_bram_r.db new file mode 100644 index 0000000..7eeea48 --- /dev/null +++ b/kintex7/mask_bram_r.db @@ -0,0 +1,8222 @@ +bit 00_01 +bit 00_02 +bit 00_03 +bit 00_05 +bit 00_06 +bit 00_07 +bit 00_09 +bit 00_10 +bit 00_101 +bit 00_102 +bit 00_103 +bit 00_105 +bit 00_106 +bit 00_107 +bit 00_109 +bit 00_11 +bit 00_110 +bit 00_111 +bit 00_113 +bit 00_114 +bit 00_115 +bit 00_117 +bit 00_118 +bit 00_119 +bit 00_121 +bit 00_122 +bit 00_123 +bit 00_125 +bit 00_126 +bit 00_127 +bit 00_129 +bit 00_13 +bit 00_130 +bit 00_131 +bit 00_133 +bit 00_134 +bit 00_135 +bit 00_137 +bit 00_138 +bit 00_139 +bit 00_14 +bit 00_141 +bit 00_142 +bit 00_143 +bit 00_145 +bit 00_146 +bit 00_147 +bit 00_149 +bit 00_15 +bit 00_150 +bit 00_151 +bit 00_153 +bit 00_154 +bit 00_155 +bit 00_157 +bit 00_158 +bit 00_161 +bit 00_162 +bit 00_163 +bit 00_165 +bit 00_166 +bit 00_167 +bit 00_169 +bit 00_17 +bit 00_170 +bit 00_171 +bit 00_173 +bit 00_174 +bit 00_175 +bit 00_177 +bit 00_178 +bit 00_179 +bit 00_18 +bit 00_181 +bit 00_182 +bit 00_183 +bit 00_185 +bit 00_186 +bit 00_187 +bit 00_189 +bit 00_19 +bit 00_190 +bit 00_191 +bit 00_193 +bit 00_194 +bit 00_195 +bit 00_197 +bit 00_198 +bit 00_199 +bit 00_201 +bit 00_202 +bit 00_203 +bit 00_205 +bit 00_206 +bit 00_207 +bit 00_209 +bit 00_21 +bit 00_210 +bit 00_211 +bit 00_213 +bit 00_214 +bit 00_215 +bit 00_217 +bit 00_218 +bit 00_219 +bit 00_22 +bit 00_221 +bit 00_222 +bit 00_225 +bit 00_226 +bit 00_227 +bit 00_229 +bit 00_23 +bit 00_230 +bit 00_231 +bit 00_233 +bit 00_234 +bit 00_235 +bit 00_237 +bit 00_238 +bit 00_239 +bit 00_241 +bit 00_242 +bit 00_243 +bit 00_245 +bit 00_246 +bit 00_247 +bit 00_249 +bit 00_25 +bit 00_250 +bit 00_251 +bit 00_253 +bit 00_254 +bit 00_255 +bit 00_257 +bit 00_258 +bit 00_259 +bit 00_26 +bit 00_261 +bit 00_262 +bit 00_263 +bit 00_265 +bit 00_266 +bit 00_267 +bit 00_269 +bit 00_27 +bit 00_270 +bit 00_271 +bit 00_273 +bit 00_274 +bit 00_275 +bit 00_277 +bit 00_278 +bit 00_279 +bit 00_281 +bit 00_282 +bit 00_283 +bit 00_285 +bit 00_286 +bit 00_289 +bit 00_29 +bit 00_290 +bit 00_291 +bit 00_293 +bit 00_294 +bit 00_295 +bit 00_297 +bit 00_298 +bit 00_299 +bit 00_30 +bit 00_301 +bit 00_302 +bit 00_303 +bit 00_305 +bit 00_306 +bit 00_307 +bit 00_309 +bit 00_310 +bit 00_311 +bit 00_313 +bit 00_314 +bit 00_315 +bit 00_317 +bit 00_318 +bit 00_319 +bit 00_33 +bit 00_34 +bit 00_35 +bit 00_37 +bit 00_38 +bit 00_39 +bit 00_41 +bit 00_42 +bit 00_43 +bit 00_45 +bit 00_46 +bit 00_47 +bit 00_49 +bit 00_50 +bit 00_51 +bit 00_53 +bit 00_54 +bit 00_55 +bit 00_57 +bit 00_58 +bit 00_59 +bit 00_61 +bit 00_62 +bit 00_63 +bit 00_65 +bit 00_66 +bit 00_67 +bit 00_69 +bit 00_70 +bit 00_71 +bit 00_73 +bit 00_74 +bit 00_75 +bit 00_77 +bit 00_78 +bit 00_79 +bit 00_81 +bit 00_82 +bit 00_83 +bit 00_85 +bit 00_86 +bit 00_87 +bit 00_89 +bit 00_90 +bit 00_91 +bit 00_93 +bit 00_94 +bit 00_97 +bit 00_98 +bit 00_99 +bit 01_00 +bit 01_01 +bit 01_02 +bit 01_04 +bit 01_05 +bit 01_06 +bit 01_08 +bit 01_09 +bit 01_10 +bit 01_100 +bit 01_101 +bit 01_102 +bit 01_104 +bit 01_105 +bit 01_106 +bit 01_108 +bit 01_109 +bit 01_110 +bit 01_112 +bit 01_113 +bit 01_114 +bit 01_116 +bit 01_117 +bit 01_118 +bit 01_12 +bit 01_120 +bit 01_121 +bit 01_122 +bit 01_124 +bit 01_125 +bit 01_126 +bit 01_128 +bit 01_129 +bit 01_13 +bit 01_130 +bit 01_132 +bit 01_133 +bit 01_134 +bit 01_136 +bit 01_137 +bit 01_138 +bit 01_14 +bit 01_140 +bit 01_141 +bit 01_142 +bit 01_144 +bit 01_145 +bit 01_146 +bit 01_148 +bit 01_149 +bit 01_150 +bit 01_152 +bit 01_153 +bit 01_154 +bit 01_156 +bit 01_157 +bit 01_16 +bit 01_160 +bit 01_161 +bit 01_162 +bit 01_164 +bit 01_165 +bit 01_166 +bit 01_168 +bit 01_169 +bit 01_17 +bit 01_170 +bit 01_172 +bit 01_173 +bit 01_174 +bit 01_176 +bit 01_177 +bit 01_178 +bit 01_18 +bit 01_180 +bit 01_181 +bit 01_182 +bit 01_184 +bit 01_185 +bit 01_186 +bit 01_188 +bit 01_189 +bit 01_190 +bit 01_192 +bit 01_193 +bit 01_194 +bit 01_196 +bit 01_197 +bit 01_198 +bit 01_20 +bit 01_200 +bit 01_201 +bit 01_202 +bit 01_204 +bit 01_205 +bit 01_206 +bit 01_208 +bit 01_209 +bit 01_21 +bit 01_210 +bit 01_212 +bit 01_213 +bit 01_214 +bit 01_216 +bit 01_217 +bit 01_218 +bit 01_22 +bit 01_220 +bit 01_221 +bit 01_224 +bit 01_225 +bit 01_226 +bit 01_228 +bit 01_229 +bit 01_230 +bit 01_232 +bit 01_233 +bit 01_234 +bit 01_236 +bit 01_237 +bit 01_238 +bit 01_24 +bit 01_240 +bit 01_241 +bit 01_242 +bit 01_244 +bit 01_245 +bit 01_246 +bit 01_248 +bit 01_249 +bit 01_25 +bit 01_250 +bit 01_252 +bit 01_253 +bit 01_254 +bit 01_256 +bit 01_257 +bit 01_258 +bit 01_26 +bit 01_260 +bit 01_261 +bit 01_262 +bit 01_264 +bit 01_265 +bit 01_266 +bit 01_268 +bit 01_269 +bit 01_270 +bit 01_272 +bit 01_273 +bit 01_274 +bit 01_276 +bit 01_277 +bit 01_278 +bit 01_28 +bit 01_280 +bit 01_281 +bit 01_282 +bit 01_284 +bit 01_285 +bit 01_288 +bit 01_289 +bit 01_29 +bit 01_290 +bit 01_292 +bit 01_293 +bit 01_294 +bit 01_296 +bit 01_297 +bit 01_298 +bit 01_300 +bit 01_301 +bit 01_302 +bit 01_304 +bit 01_305 +bit 01_306 +bit 01_308 +bit 01_309 +bit 01_310 +bit 01_312 +bit 01_313 +bit 01_314 +bit 01_316 +bit 01_317 +bit 01_318 +bit 01_32 +bit 01_33 +bit 01_34 +bit 01_36 +bit 01_37 +bit 01_38 +bit 01_40 +bit 01_41 +bit 01_42 +bit 01_44 +bit 01_45 +bit 01_46 +bit 01_48 +bit 01_49 +bit 01_50 +bit 01_52 +bit 01_53 +bit 01_54 +bit 01_56 +bit 01_57 +bit 01_58 +bit 01_60 +bit 01_61 +bit 01_62 +bit 01_64 +bit 01_65 +bit 01_66 +bit 01_68 +bit 01_69 +bit 01_70 +bit 01_72 +bit 01_73 +bit 01_74 +bit 01_76 +bit 01_77 +bit 01_78 +bit 01_80 +bit 01_81 +bit 01_82 +bit 01_84 +bit 01_85 +bit 01_86 +bit 01_88 +bit 01_89 +bit 01_90 +bit 01_92 +bit 01_93 +bit 01_96 +bit 01_97 +bit 01_98 +bit 02_01 +bit 02_02 +bit 02_03 +bit 02_05 +bit 02_06 +bit 02_07 +bit 02_09 +bit 02_10 +bit 02_101 +bit 02_102 +bit 02_103 +bit 02_105 +bit 02_106 +bit 02_107 +bit 02_109 +bit 02_11 +bit 02_110 +bit 02_111 +bit 02_113 +bit 02_114 +bit 02_115 +bit 02_117 +bit 02_118 +bit 02_119 +bit 02_121 +bit 02_122 +bit 02_123 +bit 02_125 +bit 02_126 +bit 02_127 +bit 02_129 +bit 02_13 +bit 02_130 +bit 02_131 +bit 02_133 +bit 02_134 +bit 02_135 +bit 02_137 +bit 02_138 +bit 02_139 +bit 02_14 +bit 02_141 +bit 02_142 +bit 02_143 +bit 02_145 +bit 02_146 +bit 02_147 +bit 02_149 +bit 02_15 +bit 02_150 +bit 02_151 +bit 02_153 +bit 02_154 +bit 02_155 +bit 02_157 +bit 02_158 +bit 02_159 +bit 02_161 +bit 02_162 +bit 02_163 +bit 02_165 +bit 02_166 +bit 02_167 +bit 02_169 +bit 02_17 +bit 02_170 +bit 02_171 +bit 02_173 +bit 02_174 +bit 02_175 +bit 02_177 +bit 02_178 +bit 02_179 +bit 02_18 +bit 02_181 +bit 02_182 +bit 02_183 +bit 02_185 +bit 02_186 +bit 02_187 +bit 02_189 +bit 02_19 +bit 02_190 +bit 02_191 +bit 02_193 +bit 02_194 +bit 02_195 +bit 02_197 +bit 02_198 +bit 02_199 +bit 02_201 +bit 02_202 +bit 02_203 +bit 02_205 +bit 02_206 +bit 02_207 +bit 02_209 +bit 02_21 +bit 02_210 +bit 02_211 +bit 02_213 +bit 02_214 +bit 02_215 +bit 02_217 +bit 02_218 +bit 02_219 +bit 02_22 +bit 02_221 +bit 02_222 +bit 02_223 +bit 02_225 +bit 02_226 +bit 02_227 +bit 02_229 +bit 02_23 +bit 02_230 +bit 02_231 +bit 02_233 +bit 02_234 +bit 02_235 +bit 02_237 +bit 02_238 +bit 02_239 +bit 02_241 +bit 02_242 +bit 02_243 +bit 02_245 +bit 02_246 +bit 02_247 +bit 02_249 +bit 02_25 +bit 02_250 +bit 02_251 +bit 02_253 +bit 02_254 +bit 02_255 +bit 02_257 +bit 02_258 +bit 02_259 +bit 02_26 +bit 02_261 +bit 02_262 +bit 02_263 +bit 02_265 +bit 02_266 +bit 02_267 +bit 02_269 +bit 02_27 +bit 02_270 +bit 02_271 +bit 02_273 +bit 02_274 +bit 02_275 +bit 02_277 +bit 02_278 +bit 02_279 +bit 02_281 +bit 02_282 +bit 02_283 +bit 02_285 +bit 02_286 +bit 02_287 +bit 02_289 +bit 02_29 +bit 02_290 +bit 02_291 +bit 02_293 +bit 02_294 +bit 02_295 +bit 02_297 +bit 02_298 +bit 02_299 +bit 02_30 +bit 02_301 +bit 02_302 +bit 02_303 +bit 02_305 +bit 02_306 +bit 02_307 +bit 02_309 +bit 02_31 +bit 02_310 +bit 02_311 +bit 02_313 +bit 02_314 +bit 02_315 +bit 02_317 +bit 02_318 +bit 02_319 +bit 02_33 +bit 02_34 +bit 02_35 +bit 02_37 +bit 02_38 +bit 02_39 +bit 02_41 +bit 02_42 +bit 02_43 +bit 02_45 +bit 02_46 +bit 02_47 +bit 02_49 +bit 02_50 +bit 02_51 +bit 02_53 +bit 02_54 +bit 02_55 +bit 02_57 +bit 02_58 +bit 02_59 +bit 02_61 +bit 02_62 +bit 02_63 +bit 02_65 +bit 02_66 +bit 02_67 +bit 02_69 +bit 02_70 +bit 02_71 +bit 02_73 +bit 02_74 +bit 02_75 +bit 02_77 +bit 02_78 +bit 02_79 +bit 02_81 +bit 02_82 +bit 02_83 +bit 02_85 +bit 02_86 +bit 02_87 +bit 02_89 +bit 02_90 +bit 02_91 +bit 02_93 +bit 02_94 +bit 02_95 +bit 02_97 +bit 02_98 +bit 02_99 +bit 03_00 +bit 03_01 +bit 03_02 +bit 03_04 +bit 03_05 +bit 03_06 +bit 03_08 +bit 03_09 +bit 03_10 +bit 03_100 +bit 03_101 +bit 03_102 +bit 03_104 +bit 03_105 +bit 03_106 +bit 03_108 +bit 03_109 +bit 03_110 +bit 03_112 +bit 03_113 +bit 03_114 +bit 03_116 +bit 03_117 +bit 03_118 +bit 03_12 +bit 03_120 +bit 03_121 +bit 03_122 +bit 03_124 +bit 03_125 +bit 03_126 +bit 03_128 +bit 03_129 +bit 03_13 +bit 03_130 +bit 03_132 +bit 03_133 +bit 03_134 +bit 03_136 +bit 03_137 +bit 03_138 +bit 03_14 +bit 03_140 +bit 03_141 +bit 03_142 +bit 03_144 +bit 03_145 +bit 03_146 +bit 03_148 +bit 03_149 +bit 03_150 +bit 03_152 +bit 03_153 +bit 03_154 +bit 03_156 +bit 03_157 +bit 03_158 +bit 03_16 +bit 03_160 +bit 03_161 +bit 03_162 +bit 03_164 +bit 03_165 +bit 03_166 +bit 03_168 +bit 03_169 +bit 03_17 +bit 03_170 +bit 03_172 +bit 03_173 +bit 03_174 +bit 03_176 +bit 03_177 +bit 03_178 +bit 03_18 +bit 03_180 +bit 03_181 +bit 03_182 +bit 03_184 +bit 03_185 +bit 03_186 +bit 03_188 +bit 03_189 +bit 03_190 +bit 03_192 +bit 03_193 +bit 03_194 +bit 03_196 +bit 03_197 +bit 03_198 +bit 03_20 +bit 03_200 +bit 03_201 +bit 03_202 +bit 03_204 +bit 03_205 +bit 03_206 +bit 03_208 +bit 03_209 +bit 03_21 +bit 03_210 +bit 03_212 +bit 03_213 +bit 03_214 +bit 03_216 +bit 03_217 +bit 03_218 +bit 03_22 +bit 03_220 +bit 03_221 +bit 03_222 +bit 03_224 +bit 03_225 +bit 03_226 +bit 03_228 +bit 03_229 +bit 03_230 +bit 03_232 +bit 03_233 +bit 03_234 +bit 03_236 +bit 03_237 +bit 03_238 +bit 03_24 +bit 03_240 +bit 03_241 +bit 03_242 +bit 03_244 +bit 03_245 +bit 03_246 +bit 03_248 +bit 03_249 +bit 03_25 +bit 03_250 +bit 03_252 +bit 03_253 +bit 03_254 +bit 03_256 +bit 03_257 +bit 03_258 +bit 03_26 +bit 03_260 +bit 03_261 +bit 03_262 +bit 03_264 +bit 03_265 +bit 03_266 +bit 03_268 +bit 03_269 +bit 03_270 +bit 03_272 +bit 03_273 +bit 03_274 +bit 03_276 +bit 03_277 +bit 03_278 +bit 03_28 +bit 03_280 +bit 03_281 +bit 03_282 +bit 03_284 +bit 03_285 +bit 03_286 +bit 03_288 +bit 03_289 +bit 03_29 +bit 03_290 +bit 03_292 +bit 03_293 +bit 03_294 +bit 03_296 +bit 03_297 +bit 03_298 +bit 03_30 +bit 03_300 +bit 03_301 +bit 03_302 +bit 03_304 +bit 03_305 +bit 03_306 +bit 03_308 +bit 03_309 +bit 03_310 +bit 03_312 +bit 03_313 +bit 03_314 +bit 03_316 +bit 03_317 +bit 03_318 +bit 03_32 +bit 03_33 +bit 03_34 +bit 03_36 +bit 03_37 +bit 03_38 +bit 03_40 +bit 03_41 +bit 03_42 +bit 03_44 +bit 03_45 +bit 03_46 +bit 03_48 +bit 03_49 +bit 03_50 +bit 03_52 +bit 03_53 +bit 03_54 +bit 03_56 +bit 03_57 +bit 03_58 +bit 03_60 +bit 03_61 +bit 03_62 +bit 03_64 +bit 03_65 +bit 03_66 +bit 03_68 +bit 03_69 +bit 03_70 +bit 03_72 +bit 03_73 +bit 03_74 +bit 03_76 +bit 03_77 +bit 03_78 +bit 03_80 +bit 03_81 +bit 03_82 +bit 03_84 +bit 03_85 +bit 03_86 +bit 03_88 +bit 03_89 +bit 03_90 +bit 03_92 +bit 03_93 +bit 03_94 +bit 03_96 +bit 03_97 +bit 03_98 +bit 04_00 +bit 04_01 +bit 04_02 +bit 04_03 +bit 04_04 +bit 04_05 +bit 04_06 +bit 04_07 +bit 04_08 +bit 04_09 +bit 04_10 +bit 04_100 +bit 04_101 +bit 04_102 +bit 04_103 +bit 04_104 +bit 04_105 +bit 04_106 +bit 04_107 +bit 04_108 +bit 04_109 +bit 04_11 +bit 04_110 +bit 04_111 +bit 04_112 +bit 04_113 +bit 04_114 +bit 04_115 +bit 04_116 +bit 04_117 +bit 04_118 +bit 04_119 +bit 04_12 +bit 04_120 +bit 04_121 +bit 04_122 +bit 04_123 +bit 04_124 +bit 04_125 +bit 04_126 +bit 04_127 +bit 04_128 +bit 04_129 +bit 04_13 +bit 04_130 +bit 04_131 +bit 04_132 +bit 04_133 +bit 04_134 +bit 04_135 +bit 04_136 +bit 04_137 +bit 04_138 +bit 04_139 +bit 04_14 +bit 04_140 +bit 04_141 +bit 04_142 +bit 04_143 +bit 04_144 +bit 04_145 +bit 04_146 +bit 04_147 +bit 04_148 +bit 04_149 +bit 04_15 +bit 04_150 +bit 04_151 +bit 04_152 +bit 04_153 +bit 04_154 +bit 04_155 +bit 04_156 +bit 04_157 +bit 04_158 +bit 04_159 +bit 04_16 +bit 04_160 +bit 04_161 +bit 04_162 +bit 04_163 +bit 04_164 +bit 04_165 +bit 04_166 +bit 04_167 +bit 04_168 +bit 04_169 +bit 04_17 +bit 04_170 +bit 04_171 +bit 04_172 +bit 04_173 +bit 04_174 +bit 04_175 +bit 04_176 +bit 04_177 +bit 04_178 +bit 04_179 +bit 04_18 +bit 04_180 +bit 04_181 +bit 04_182 +bit 04_183 +bit 04_184 +bit 04_185 +bit 04_186 +bit 04_187 +bit 04_188 +bit 04_189 +bit 04_19 +bit 04_190 +bit 04_191 +bit 04_192 +bit 04_193 +bit 04_194 +bit 04_195 +bit 04_196 +bit 04_197 +bit 04_198 +bit 04_199 +bit 04_20 +bit 04_200 +bit 04_201 +bit 04_202 +bit 04_203 +bit 04_204 +bit 04_205 +bit 04_206 +bit 04_207 +bit 04_208 +bit 04_209 +bit 04_21 +bit 04_210 +bit 04_211 +bit 04_212 +bit 04_213 +bit 04_214 +bit 04_215 +bit 04_216 +bit 04_217 +bit 04_218 +bit 04_219 +bit 04_22 +bit 04_220 +bit 04_221 +bit 04_222 +bit 04_223 +bit 04_224 +bit 04_225 +bit 04_226 +bit 04_227 +bit 04_228 +bit 04_229 +bit 04_23 +bit 04_230 +bit 04_231 +bit 04_232 +bit 04_233 +bit 04_234 +bit 04_235 +bit 04_236 +bit 04_237 +bit 04_238 +bit 04_239 +bit 04_24 +bit 04_240 +bit 04_241 +bit 04_242 +bit 04_243 +bit 04_244 +bit 04_245 +bit 04_246 +bit 04_247 +bit 04_248 +bit 04_249 +bit 04_25 +bit 04_250 +bit 04_251 +bit 04_252 +bit 04_253 +bit 04_254 +bit 04_255 +bit 04_256 +bit 04_257 +bit 04_258 +bit 04_259 +bit 04_26 +bit 04_260 +bit 04_261 +bit 04_262 +bit 04_263 +bit 04_264 +bit 04_265 +bit 04_266 +bit 04_267 +bit 04_268 +bit 04_269 +bit 04_27 +bit 04_270 +bit 04_271 +bit 04_272 +bit 04_273 +bit 04_274 +bit 04_275 +bit 04_276 +bit 04_277 +bit 04_278 +bit 04_279 +bit 04_28 +bit 04_280 +bit 04_281 +bit 04_282 +bit 04_283 +bit 04_284 +bit 04_285 +bit 04_286 +bit 04_287 +bit 04_288 +bit 04_289 +bit 04_29 +bit 04_290 +bit 04_291 +bit 04_292 +bit 04_293 +bit 04_294 +bit 04_295 +bit 04_296 +bit 04_297 +bit 04_298 +bit 04_299 +bit 04_30 +bit 04_300 +bit 04_301 +bit 04_302 +bit 04_303 +bit 04_304 +bit 04_305 +bit 04_306 +bit 04_307 +bit 04_308 +bit 04_309 +bit 04_31 +bit 04_310 +bit 04_311 +bit 04_312 +bit 04_313 +bit 04_314 +bit 04_315 +bit 04_316 +bit 04_317 +bit 04_318 +bit 04_319 +bit 04_32 +bit 04_33 +bit 04_34 +bit 04_35 +bit 04_36 +bit 04_37 +bit 04_38 +bit 04_39 +bit 04_40 +bit 04_41 +bit 04_42 +bit 04_43 +bit 04_44 +bit 04_45 +bit 04_46 +bit 04_47 +bit 04_48 +bit 04_49 +bit 04_50 +bit 04_51 +bit 04_52 +bit 04_53 +bit 04_54 +bit 04_55 +bit 04_56 +bit 04_57 +bit 04_58 +bit 04_59 +bit 04_60 +bit 04_61 +bit 04_62 +bit 04_63 +bit 04_64 +bit 04_65 +bit 04_66 +bit 04_67 +bit 04_68 +bit 04_69 +bit 04_70 +bit 04_71 +bit 04_72 +bit 04_73 +bit 04_74 +bit 04_75 +bit 04_76 +bit 04_77 +bit 04_78 +bit 04_79 +bit 04_80 +bit 04_81 +bit 04_82 +bit 04_83 +bit 04_84 +bit 04_85 +bit 04_86 +bit 04_87 +bit 04_88 +bit 04_89 +bit 04_90 +bit 04_91 +bit 04_92 +bit 04_93 +bit 04_94 +bit 04_95 +bit 04_96 +bit 04_97 +bit 04_98 +bit 04_99 +bit 05_00 +bit 05_01 +bit 05_02 +bit 05_03 +bit 05_04 +bit 05_05 +bit 05_06 +bit 05_07 +bit 05_08 +bit 05_09 +bit 05_10 +bit 05_100 +bit 05_101 +bit 05_102 +bit 05_103 +bit 05_104 +bit 05_105 +bit 05_106 +bit 05_107 +bit 05_108 +bit 05_109 +bit 05_11 +bit 05_110 +bit 05_111 +bit 05_112 +bit 05_113 +bit 05_114 +bit 05_115 +bit 05_116 +bit 05_117 +bit 05_118 +bit 05_119 +bit 05_12 +bit 05_120 +bit 05_121 +bit 05_122 +bit 05_123 +bit 05_124 +bit 05_125 +bit 05_126 +bit 05_127 +bit 05_128 +bit 05_129 +bit 05_13 +bit 05_130 +bit 05_131 +bit 05_132 +bit 05_133 +bit 05_134 +bit 05_135 +bit 05_136 +bit 05_137 +bit 05_138 +bit 05_139 +bit 05_14 +bit 05_140 +bit 05_141 +bit 05_142 +bit 05_143 +bit 05_144 +bit 05_145 +bit 05_146 +bit 05_147 +bit 05_148 +bit 05_149 +bit 05_15 +bit 05_150 +bit 05_151 +bit 05_152 +bit 05_153 +bit 05_154 +bit 05_155 +bit 05_156 +bit 05_157 +bit 05_158 +bit 05_159 +bit 05_16 +bit 05_160 +bit 05_161 +bit 05_162 +bit 05_163 +bit 05_164 +bit 05_165 +bit 05_166 +bit 05_167 +bit 05_168 +bit 05_169 +bit 05_17 +bit 05_170 +bit 05_171 +bit 05_172 +bit 05_173 +bit 05_174 +bit 05_175 +bit 05_176 +bit 05_177 +bit 05_178 +bit 05_179 +bit 05_18 +bit 05_180 +bit 05_181 +bit 05_182 +bit 05_183 +bit 05_184 +bit 05_185 +bit 05_186 +bit 05_187 +bit 05_188 +bit 05_189 +bit 05_19 +bit 05_190 +bit 05_191 +bit 05_192 +bit 05_193 +bit 05_194 +bit 05_195 +bit 05_196 +bit 05_197 +bit 05_198 +bit 05_199 +bit 05_20 +bit 05_200 +bit 05_201 +bit 05_202 +bit 05_203 +bit 05_204 +bit 05_205 +bit 05_206 +bit 05_207 +bit 05_208 +bit 05_209 +bit 05_21 +bit 05_210 +bit 05_211 +bit 05_212 +bit 05_213 +bit 05_214 +bit 05_215 +bit 05_216 +bit 05_217 +bit 05_218 +bit 05_219 +bit 05_22 +bit 05_220 +bit 05_221 +bit 05_222 +bit 05_223 +bit 05_224 +bit 05_225 +bit 05_226 +bit 05_227 +bit 05_228 +bit 05_229 +bit 05_23 +bit 05_230 +bit 05_231 +bit 05_232 +bit 05_233 +bit 05_234 +bit 05_235 +bit 05_236 +bit 05_237 +bit 05_238 +bit 05_239 +bit 05_24 +bit 05_240 +bit 05_241 +bit 05_242 +bit 05_243 +bit 05_244 +bit 05_245 +bit 05_246 +bit 05_247 +bit 05_248 +bit 05_249 +bit 05_25 +bit 05_250 +bit 05_251 +bit 05_252 +bit 05_253 +bit 05_254 +bit 05_255 +bit 05_256 +bit 05_257 +bit 05_258 +bit 05_259 +bit 05_26 +bit 05_260 +bit 05_261 +bit 05_262 +bit 05_263 +bit 05_264 +bit 05_265 +bit 05_266 +bit 05_267 +bit 05_268 +bit 05_269 +bit 05_27 +bit 05_270 +bit 05_271 +bit 05_272 +bit 05_273 +bit 05_274 +bit 05_275 +bit 05_276 +bit 05_277 +bit 05_278 +bit 05_279 +bit 05_28 +bit 05_280 +bit 05_281 +bit 05_282 +bit 05_283 +bit 05_284 +bit 05_285 +bit 05_286 +bit 05_287 +bit 05_288 +bit 05_289 +bit 05_29 +bit 05_290 +bit 05_291 +bit 05_292 +bit 05_293 +bit 05_294 +bit 05_295 +bit 05_296 +bit 05_297 +bit 05_298 +bit 05_299 +bit 05_30 +bit 05_300 +bit 05_301 +bit 05_302 +bit 05_303 +bit 05_304 +bit 05_305 +bit 05_306 +bit 05_307 +bit 05_308 +bit 05_309 +bit 05_31 +bit 05_310 +bit 05_311 +bit 05_312 +bit 05_313 +bit 05_314 +bit 05_315 +bit 05_316 +bit 05_317 +bit 05_318 +bit 05_319 +bit 05_32 +bit 05_33 +bit 05_34 +bit 05_35 +bit 05_36 +bit 05_37 +bit 05_38 +bit 05_39 +bit 05_40 +bit 05_41 +bit 05_42 +bit 05_43 +bit 05_44 +bit 05_45 +bit 05_46 +bit 05_47 +bit 05_48 +bit 05_49 +bit 05_50 +bit 05_51 +bit 05_52 +bit 05_53 +bit 05_54 +bit 05_55 +bit 05_56 +bit 05_57 +bit 05_58 +bit 05_59 +bit 05_60 +bit 05_61 +bit 05_62 +bit 05_63 +bit 05_64 +bit 05_65 +bit 05_66 +bit 05_67 +bit 05_68 +bit 05_69 +bit 05_70 +bit 05_71 +bit 05_72 +bit 05_73 +bit 05_74 +bit 05_75 +bit 05_76 +bit 05_77 +bit 05_78 +bit 05_79 +bit 05_80 +bit 05_81 +bit 05_82 +bit 05_83 +bit 05_84 +bit 05_85 +bit 05_86 +bit 05_87 +bit 05_88 +bit 05_89 +bit 05_90 +bit 05_91 +bit 05_92 +bit 05_93 +bit 05_94 +bit 05_95 +bit 05_96 +bit 05_97 +bit 05_98 +bit 05_99 +bit 06_00 +bit 06_01 +bit 06_02 +bit 06_03 +bit 06_04 +bit 06_05 +bit 06_06 +bit 06_07 +bit 06_08 +bit 06_09 +bit 06_10 +bit 06_100 +bit 06_101 +bit 06_102 +bit 06_103 +bit 06_104 +bit 06_105 +bit 06_106 +bit 06_107 +bit 06_108 +bit 06_109 +bit 06_11 +bit 06_110 +bit 06_111 +bit 06_112 +bit 06_113 +bit 06_114 +bit 06_115 +bit 06_116 +bit 06_117 +bit 06_118 +bit 06_119 +bit 06_12 +bit 06_120 +bit 06_121 +bit 06_122 +bit 06_123 +bit 06_124 +bit 06_125 +bit 06_126 +bit 06_127 +bit 06_128 +bit 06_129 +bit 06_13 +bit 06_130 +bit 06_131 +bit 06_132 +bit 06_133 +bit 06_134 +bit 06_135 +bit 06_136 +bit 06_137 +bit 06_138 +bit 06_139 +bit 06_14 +bit 06_140 +bit 06_141 +bit 06_142 +bit 06_143 +bit 06_144 +bit 06_145 +bit 06_146 +bit 06_147 +bit 06_148 +bit 06_149 +bit 06_15 +bit 06_150 +bit 06_151 +bit 06_152 +bit 06_153 +bit 06_154 +bit 06_155 +bit 06_156 +bit 06_157 +bit 06_158 +bit 06_159 +bit 06_16 +bit 06_160 +bit 06_161 +bit 06_162 +bit 06_163 +bit 06_164 +bit 06_165 +bit 06_166 +bit 06_167 +bit 06_168 +bit 06_169 +bit 06_17 +bit 06_170 +bit 06_171 +bit 06_172 +bit 06_173 +bit 06_174 +bit 06_175 +bit 06_176 +bit 06_177 +bit 06_178 +bit 06_179 +bit 06_18 +bit 06_180 +bit 06_181 +bit 06_182 +bit 06_183 +bit 06_184 +bit 06_185 +bit 06_186 +bit 06_187 +bit 06_188 +bit 06_189 +bit 06_19 +bit 06_190 +bit 06_191 +bit 06_192 +bit 06_193 +bit 06_194 +bit 06_195 +bit 06_196 +bit 06_197 +bit 06_198 +bit 06_199 +bit 06_20 +bit 06_200 +bit 06_201 +bit 06_202 +bit 06_203 +bit 06_204 +bit 06_205 +bit 06_206 +bit 06_207 +bit 06_208 +bit 06_209 +bit 06_21 +bit 06_210 +bit 06_211 +bit 06_212 +bit 06_213 +bit 06_214 +bit 06_215 +bit 06_216 +bit 06_217 +bit 06_218 +bit 06_219 +bit 06_22 +bit 06_220 +bit 06_221 +bit 06_222 +bit 06_223 +bit 06_224 +bit 06_225 +bit 06_226 +bit 06_227 +bit 06_228 +bit 06_229 +bit 06_23 +bit 06_230 +bit 06_231 +bit 06_232 +bit 06_233 +bit 06_234 +bit 06_235 +bit 06_236 +bit 06_237 +bit 06_238 +bit 06_239 +bit 06_24 +bit 06_240 +bit 06_241 +bit 06_242 +bit 06_243 +bit 06_244 +bit 06_245 +bit 06_246 +bit 06_247 +bit 06_248 +bit 06_249 +bit 06_25 +bit 06_250 +bit 06_251 +bit 06_252 +bit 06_253 +bit 06_254 +bit 06_255 +bit 06_256 +bit 06_257 +bit 06_258 +bit 06_259 +bit 06_26 +bit 06_260 +bit 06_261 +bit 06_262 +bit 06_263 +bit 06_264 +bit 06_265 +bit 06_266 +bit 06_267 +bit 06_268 +bit 06_269 +bit 06_27 +bit 06_270 +bit 06_271 +bit 06_272 +bit 06_273 +bit 06_274 +bit 06_275 +bit 06_276 +bit 06_277 +bit 06_278 +bit 06_279 +bit 06_28 +bit 06_280 +bit 06_281 +bit 06_282 +bit 06_283 +bit 06_284 +bit 06_285 +bit 06_286 +bit 06_287 +bit 06_288 +bit 06_289 +bit 06_29 +bit 06_290 +bit 06_291 +bit 06_292 +bit 06_293 +bit 06_294 +bit 06_295 +bit 06_296 +bit 06_297 +bit 06_298 +bit 06_299 +bit 06_30 +bit 06_300 +bit 06_301 +bit 06_302 +bit 06_303 +bit 06_304 +bit 06_305 +bit 06_306 +bit 06_307 +bit 06_308 +bit 06_309 +bit 06_31 +bit 06_310 +bit 06_311 +bit 06_312 +bit 06_313 +bit 06_314 +bit 06_315 +bit 06_316 +bit 06_317 +bit 06_318 +bit 06_319 +bit 06_32 +bit 06_33 +bit 06_34 +bit 06_35 +bit 06_36 +bit 06_37 +bit 06_38 +bit 06_39 +bit 06_40 +bit 06_41 +bit 06_42 +bit 06_43 +bit 06_44 +bit 06_45 +bit 06_46 +bit 06_47 +bit 06_48 +bit 06_49 +bit 06_50 +bit 06_51 +bit 06_52 +bit 06_53 +bit 06_54 +bit 06_55 +bit 06_56 +bit 06_57 +bit 06_58 +bit 06_59 +bit 06_60 +bit 06_61 +bit 06_62 +bit 06_63 +bit 06_64 +bit 06_65 +bit 06_66 +bit 06_67 +bit 06_68 +bit 06_69 +bit 06_70 +bit 06_71 +bit 06_72 +bit 06_73 +bit 06_74 +bit 06_75 +bit 06_76 +bit 06_77 +bit 06_78 +bit 06_79 +bit 06_80 +bit 06_81 +bit 06_82 +bit 06_83 +bit 06_84 +bit 06_85 +bit 06_86 +bit 06_87 +bit 06_88 +bit 06_89 +bit 06_90 +bit 06_91 +bit 06_92 +bit 06_93 +bit 06_94 +bit 06_95 +bit 06_96 +bit 06_97 +bit 06_98 +bit 06_99 +bit 07_00 +bit 07_01 +bit 07_02 +bit 07_03 +bit 07_04 +bit 07_05 +bit 07_06 +bit 07_07 +bit 07_08 +bit 07_09 +bit 07_10 +bit 07_100 +bit 07_101 +bit 07_102 +bit 07_103 +bit 07_104 +bit 07_105 +bit 07_106 +bit 07_107 +bit 07_108 +bit 07_109 +bit 07_11 +bit 07_110 +bit 07_111 +bit 07_112 +bit 07_113 +bit 07_114 +bit 07_115 +bit 07_116 +bit 07_117 +bit 07_118 +bit 07_119 +bit 07_12 +bit 07_120 +bit 07_121 +bit 07_122 +bit 07_123 +bit 07_124 +bit 07_125 +bit 07_126 +bit 07_127 +bit 07_128 +bit 07_129 +bit 07_13 +bit 07_130 +bit 07_131 +bit 07_132 +bit 07_133 +bit 07_134 +bit 07_135 +bit 07_136 +bit 07_137 +bit 07_138 +bit 07_139 +bit 07_14 +bit 07_140 +bit 07_141 +bit 07_142 +bit 07_143 +bit 07_144 +bit 07_145 +bit 07_146 +bit 07_147 +bit 07_148 +bit 07_149 +bit 07_15 +bit 07_150 +bit 07_151 +bit 07_152 +bit 07_153 +bit 07_154 +bit 07_155 +bit 07_156 +bit 07_157 +bit 07_158 +bit 07_159 +bit 07_16 +bit 07_160 +bit 07_161 +bit 07_162 +bit 07_163 +bit 07_164 +bit 07_165 +bit 07_166 +bit 07_167 +bit 07_168 +bit 07_169 +bit 07_17 +bit 07_170 +bit 07_171 +bit 07_172 +bit 07_173 +bit 07_174 +bit 07_175 +bit 07_176 +bit 07_177 +bit 07_178 +bit 07_179 +bit 07_18 +bit 07_180 +bit 07_181 +bit 07_182 +bit 07_183 +bit 07_184 +bit 07_185 +bit 07_186 +bit 07_187 +bit 07_188 +bit 07_189 +bit 07_19 +bit 07_190 +bit 07_191 +bit 07_192 +bit 07_193 +bit 07_194 +bit 07_195 +bit 07_196 +bit 07_197 +bit 07_198 +bit 07_199 +bit 07_20 +bit 07_200 +bit 07_201 +bit 07_202 +bit 07_203 +bit 07_204 +bit 07_205 +bit 07_206 +bit 07_207 +bit 07_208 +bit 07_209 +bit 07_21 +bit 07_210 +bit 07_211 +bit 07_212 +bit 07_213 +bit 07_214 +bit 07_215 +bit 07_216 +bit 07_217 +bit 07_218 +bit 07_219 +bit 07_22 +bit 07_220 +bit 07_221 +bit 07_222 +bit 07_223 +bit 07_224 +bit 07_225 +bit 07_226 +bit 07_227 +bit 07_228 +bit 07_229 +bit 07_23 +bit 07_230 +bit 07_231 +bit 07_232 +bit 07_233 +bit 07_234 +bit 07_235 +bit 07_236 +bit 07_237 +bit 07_238 +bit 07_239 +bit 07_24 +bit 07_240 +bit 07_241 +bit 07_242 +bit 07_243 +bit 07_244 +bit 07_245 +bit 07_246 +bit 07_247 +bit 07_248 +bit 07_249 +bit 07_25 +bit 07_250 +bit 07_251 +bit 07_252 +bit 07_253 +bit 07_254 +bit 07_255 +bit 07_256 +bit 07_257 +bit 07_258 +bit 07_259 +bit 07_26 +bit 07_260 +bit 07_261 +bit 07_262 +bit 07_263 +bit 07_264 +bit 07_265 +bit 07_266 +bit 07_267 +bit 07_268 +bit 07_269 +bit 07_27 +bit 07_270 +bit 07_271 +bit 07_272 +bit 07_273 +bit 07_274 +bit 07_275 +bit 07_276 +bit 07_277 +bit 07_278 +bit 07_279 +bit 07_28 +bit 07_280 +bit 07_281 +bit 07_282 +bit 07_283 +bit 07_284 +bit 07_285 +bit 07_286 +bit 07_287 +bit 07_288 +bit 07_289 +bit 07_29 +bit 07_290 +bit 07_291 +bit 07_292 +bit 07_293 +bit 07_294 +bit 07_295 +bit 07_296 +bit 07_297 +bit 07_298 +bit 07_299 +bit 07_30 +bit 07_300 +bit 07_301 +bit 07_302 +bit 07_303 +bit 07_304 +bit 07_305 +bit 07_306 +bit 07_307 +bit 07_308 +bit 07_309 +bit 07_31 +bit 07_310 +bit 07_311 +bit 07_312 +bit 07_313 +bit 07_314 +bit 07_315 +bit 07_316 +bit 07_317 +bit 07_318 +bit 07_319 +bit 07_32 +bit 07_33 +bit 07_34 +bit 07_35 +bit 07_36 +bit 07_37 +bit 07_38 +bit 07_39 +bit 07_40 +bit 07_41 +bit 07_42 +bit 07_43 +bit 07_44 +bit 07_45 +bit 07_46 +bit 07_47 +bit 07_48 +bit 07_49 +bit 07_50 +bit 07_51 +bit 07_52 +bit 07_53 +bit 07_54 +bit 07_55 +bit 07_56 +bit 07_57 +bit 07_58 +bit 07_59 +bit 07_60 +bit 07_61 +bit 07_62 +bit 07_63 +bit 07_64 +bit 07_65 +bit 07_66 +bit 07_67 +bit 07_68 +bit 07_69 +bit 07_70 +bit 07_71 +bit 07_72 +bit 07_73 +bit 07_74 +bit 07_75 +bit 07_76 +bit 07_77 +bit 07_78 +bit 07_79 +bit 07_80 +bit 07_81 +bit 07_82 +bit 07_83 +bit 07_84 +bit 07_85 +bit 07_86 +bit 07_87 +bit 07_88 +bit 07_89 +bit 07_90 +bit 07_91 +bit 07_92 +bit 07_93 +bit 07_94 +bit 07_95 +bit 07_96 +bit 07_97 +bit 07_98 +bit 07_99 +bit 08_00 +bit 08_01 +bit 08_02 +bit 08_03 +bit 08_04 +bit 08_05 +bit 08_06 +bit 08_07 +bit 08_08 +bit 08_09 +bit 08_10 +bit 08_100 +bit 08_101 +bit 08_102 +bit 08_103 +bit 08_104 +bit 08_105 +bit 08_106 +bit 08_107 +bit 08_108 +bit 08_109 +bit 08_11 +bit 08_110 +bit 08_111 +bit 08_112 +bit 08_113 +bit 08_114 +bit 08_115 +bit 08_116 +bit 08_117 +bit 08_118 +bit 08_119 +bit 08_12 +bit 08_120 +bit 08_121 +bit 08_122 +bit 08_123 +bit 08_124 +bit 08_125 +bit 08_126 +bit 08_127 +bit 08_128 +bit 08_129 +bit 08_13 +bit 08_130 +bit 08_131 +bit 08_132 +bit 08_133 +bit 08_134 +bit 08_135 +bit 08_136 +bit 08_137 +bit 08_138 +bit 08_139 +bit 08_14 +bit 08_140 +bit 08_141 +bit 08_142 +bit 08_143 +bit 08_144 +bit 08_145 +bit 08_146 +bit 08_147 +bit 08_148 +bit 08_149 +bit 08_15 +bit 08_150 +bit 08_151 +bit 08_152 +bit 08_153 +bit 08_154 +bit 08_155 +bit 08_156 +bit 08_157 +bit 08_158 +bit 08_159 +bit 08_16 +bit 08_160 +bit 08_161 +bit 08_162 +bit 08_163 +bit 08_164 +bit 08_165 +bit 08_166 +bit 08_167 +bit 08_168 +bit 08_169 +bit 08_17 +bit 08_170 +bit 08_171 +bit 08_172 +bit 08_173 +bit 08_174 +bit 08_175 +bit 08_176 +bit 08_177 +bit 08_178 +bit 08_179 +bit 08_18 +bit 08_180 +bit 08_181 +bit 08_182 +bit 08_183 +bit 08_184 +bit 08_185 +bit 08_186 +bit 08_187 +bit 08_188 +bit 08_189 +bit 08_19 +bit 08_190 +bit 08_191 +bit 08_192 +bit 08_193 +bit 08_194 +bit 08_195 +bit 08_196 +bit 08_197 +bit 08_198 +bit 08_199 +bit 08_20 +bit 08_200 +bit 08_201 +bit 08_202 +bit 08_203 +bit 08_204 +bit 08_205 +bit 08_206 +bit 08_207 +bit 08_208 +bit 08_209 +bit 08_21 +bit 08_210 +bit 08_211 +bit 08_212 +bit 08_213 +bit 08_214 +bit 08_215 +bit 08_216 +bit 08_217 +bit 08_218 +bit 08_219 +bit 08_22 +bit 08_220 +bit 08_221 +bit 08_222 +bit 08_223 +bit 08_224 +bit 08_225 +bit 08_226 +bit 08_227 +bit 08_228 +bit 08_229 +bit 08_23 +bit 08_230 +bit 08_231 +bit 08_232 +bit 08_233 +bit 08_234 +bit 08_235 +bit 08_236 +bit 08_237 +bit 08_238 +bit 08_239 +bit 08_24 +bit 08_240 +bit 08_241 +bit 08_242 +bit 08_243 +bit 08_244 +bit 08_245 +bit 08_246 +bit 08_247 +bit 08_248 +bit 08_249 +bit 08_25 +bit 08_250 +bit 08_251 +bit 08_252 +bit 08_253 +bit 08_254 +bit 08_255 +bit 08_256 +bit 08_257 +bit 08_258 +bit 08_259 +bit 08_26 +bit 08_260 +bit 08_261 +bit 08_262 +bit 08_263 +bit 08_264 +bit 08_265 +bit 08_266 +bit 08_267 +bit 08_268 +bit 08_269 +bit 08_27 +bit 08_270 +bit 08_271 +bit 08_272 +bit 08_273 +bit 08_274 +bit 08_275 +bit 08_276 +bit 08_277 +bit 08_278 +bit 08_279 +bit 08_28 +bit 08_280 +bit 08_281 +bit 08_282 +bit 08_283 +bit 08_284 +bit 08_285 +bit 08_286 +bit 08_287 +bit 08_288 +bit 08_289 +bit 08_29 +bit 08_290 +bit 08_291 +bit 08_292 +bit 08_293 +bit 08_294 +bit 08_295 +bit 08_296 +bit 08_297 +bit 08_298 +bit 08_299 +bit 08_30 +bit 08_300 +bit 08_301 +bit 08_302 +bit 08_303 +bit 08_304 +bit 08_305 +bit 08_306 +bit 08_307 +bit 08_308 +bit 08_309 +bit 08_31 +bit 08_310 +bit 08_311 +bit 08_312 +bit 08_313 +bit 08_314 +bit 08_315 +bit 08_316 +bit 08_317 +bit 08_318 +bit 08_319 +bit 08_32 +bit 08_33 +bit 08_34 +bit 08_35 +bit 08_36 +bit 08_37 +bit 08_38 +bit 08_39 +bit 08_40 +bit 08_41 +bit 08_42 +bit 08_43 +bit 08_44 +bit 08_45 +bit 08_46 +bit 08_47 +bit 08_48 +bit 08_49 +bit 08_50 +bit 08_51 +bit 08_52 +bit 08_53 +bit 08_54 +bit 08_55 +bit 08_56 +bit 08_57 +bit 08_58 +bit 08_59 +bit 08_60 +bit 08_61 +bit 08_62 +bit 08_63 +bit 08_64 +bit 08_65 +bit 08_66 +bit 08_67 +bit 08_68 +bit 08_69 +bit 08_70 +bit 08_71 +bit 08_72 +bit 08_73 +bit 08_74 +bit 08_75 +bit 08_76 +bit 08_77 +bit 08_78 +bit 08_79 +bit 08_80 +bit 08_81 +bit 08_82 +bit 08_83 +bit 08_84 +bit 08_85 +bit 08_86 +bit 08_87 +bit 08_88 +bit 08_89 +bit 08_90 +bit 08_91 +bit 08_92 +bit 08_93 +bit 08_94 +bit 08_95 +bit 08_96 +bit 08_97 +bit 08_98 +bit 08_99 +bit 09_00 +bit 09_01 +bit 09_02 +bit 09_03 +bit 09_04 +bit 09_05 +bit 09_06 +bit 09_07 +bit 09_08 +bit 09_09 +bit 09_10 +bit 09_100 +bit 09_101 +bit 09_102 +bit 09_103 +bit 09_104 +bit 09_105 +bit 09_106 +bit 09_107 +bit 09_108 +bit 09_109 +bit 09_11 +bit 09_110 +bit 09_111 +bit 09_112 +bit 09_113 +bit 09_114 +bit 09_115 +bit 09_116 +bit 09_117 +bit 09_118 +bit 09_119 +bit 09_12 +bit 09_120 +bit 09_121 +bit 09_122 +bit 09_123 +bit 09_124 +bit 09_125 +bit 09_126 +bit 09_127 +bit 09_128 +bit 09_129 +bit 09_13 +bit 09_130 +bit 09_131 +bit 09_132 +bit 09_133 +bit 09_134 +bit 09_135 +bit 09_136 +bit 09_137 +bit 09_138 +bit 09_139 +bit 09_14 +bit 09_140 +bit 09_141 +bit 09_142 +bit 09_143 +bit 09_144 +bit 09_145 +bit 09_146 +bit 09_147 +bit 09_148 +bit 09_149 +bit 09_15 +bit 09_150 +bit 09_151 +bit 09_152 +bit 09_153 +bit 09_154 +bit 09_155 +bit 09_156 +bit 09_157 +bit 09_158 +bit 09_159 +bit 09_16 +bit 09_160 +bit 09_161 +bit 09_162 +bit 09_163 +bit 09_164 +bit 09_165 +bit 09_166 +bit 09_167 +bit 09_168 +bit 09_169 +bit 09_17 +bit 09_170 +bit 09_171 +bit 09_172 +bit 09_173 +bit 09_174 +bit 09_175 +bit 09_176 +bit 09_177 +bit 09_178 +bit 09_179 +bit 09_18 +bit 09_180 +bit 09_181 +bit 09_182 +bit 09_183 +bit 09_184 +bit 09_185 +bit 09_186 +bit 09_187 +bit 09_188 +bit 09_189 +bit 09_19 +bit 09_190 +bit 09_191 +bit 09_192 +bit 09_193 +bit 09_194 +bit 09_195 +bit 09_196 +bit 09_197 +bit 09_198 +bit 09_199 +bit 09_20 +bit 09_200 +bit 09_201 +bit 09_202 +bit 09_203 +bit 09_204 +bit 09_205 +bit 09_206 +bit 09_207 +bit 09_208 +bit 09_209 +bit 09_21 +bit 09_210 +bit 09_211 +bit 09_212 +bit 09_213 +bit 09_214 +bit 09_215 +bit 09_216 +bit 09_217 +bit 09_218 +bit 09_219 +bit 09_22 +bit 09_220 +bit 09_221 +bit 09_222 +bit 09_223 +bit 09_224 +bit 09_225 +bit 09_226 +bit 09_227 +bit 09_228 +bit 09_229 +bit 09_23 +bit 09_230 +bit 09_231 +bit 09_232 +bit 09_233 +bit 09_234 +bit 09_235 +bit 09_236 +bit 09_237 +bit 09_238 +bit 09_239 +bit 09_24 +bit 09_240 +bit 09_241 +bit 09_242 +bit 09_243 +bit 09_244 +bit 09_245 +bit 09_246 +bit 09_247 +bit 09_248 +bit 09_249 +bit 09_25 +bit 09_250 +bit 09_251 +bit 09_252 +bit 09_253 +bit 09_254 +bit 09_255 +bit 09_256 +bit 09_257 +bit 09_258 +bit 09_259 +bit 09_26 +bit 09_260 +bit 09_261 +bit 09_262 +bit 09_263 +bit 09_264 +bit 09_265 +bit 09_266 +bit 09_267 +bit 09_268 +bit 09_269 +bit 09_27 +bit 09_270 +bit 09_271 +bit 09_272 +bit 09_273 +bit 09_274 +bit 09_275 +bit 09_276 +bit 09_277 +bit 09_278 +bit 09_279 +bit 09_28 +bit 09_280 +bit 09_281 +bit 09_282 +bit 09_283 +bit 09_284 +bit 09_285 +bit 09_286 +bit 09_287 +bit 09_288 +bit 09_289 +bit 09_29 +bit 09_290 +bit 09_291 +bit 09_292 +bit 09_293 +bit 09_294 +bit 09_295 +bit 09_296 +bit 09_297 +bit 09_298 +bit 09_299 +bit 09_30 +bit 09_300 +bit 09_301 +bit 09_302 +bit 09_303 +bit 09_304 +bit 09_305 +bit 09_306 +bit 09_307 +bit 09_308 +bit 09_309 +bit 09_31 +bit 09_310 +bit 09_311 +bit 09_312 +bit 09_313 +bit 09_314 +bit 09_315 +bit 09_316 +bit 09_317 +bit 09_318 +bit 09_319 +bit 09_32 +bit 09_33 +bit 09_34 +bit 09_35 +bit 09_36 +bit 09_37 +bit 09_38 +bit 09_39 +bit 09_40 +bit 09_41 +bit 09_42 +bit 09_43 +bit 09_44 +bit 09_45 +bit 09_46 +bit 09_47 +bit 09_48 +bit 09_49 +bit 09_50 +bit 09_51 +bit 09_52 +bit 09_53 +bit 09_54 +bit 09_55 +bit 09_56 +bit 09_57 +bit 09_58 +bit 09_59 +bit 09_60 +bit 09_61 +bit 09_62 +bit 09_63 +bit 09_64 +bit 09_65 +bit 09_66 +bit 09_67 +bit 09_68 +bit 09_69 +bit 09_70 +bit 09_71 +bit 09_72 +bit 09_73 +bit 09_74 +bit 09_75 +bit 09_76 +bit 09_77 +bit 09_78 +bit 09_79 +bit 09_80 +bit 09_81 +bit 09_82 +bit 09_83 +bit 09_84 +bit 09_85 +bit 09_86 +bit 09_87 +bit 09_88 +bit 09_89 +bit 09_90 +bit 09_91 +bit 09_92 +bit 09_93 +bit 09_94 +bit 09_95 +bit 09_96 +bit 09_97 +bit 09_98 +bit 09_99 +bit 10_00 +bit 10_01 +bit 10_02 +bit 10_03 +bit 10_04 +bit 10_05 +bit 10_06 +bit 10_07 +bit 10_08 +bit 10_09 +bit 10_10 +bit 10_100 +bit 10_101 +bit 10_102 +bit 10_103 +bit 10_104 +bit 10_105 +bit 10_106 +bit 10_107 +bit 10_108 +bit 10_109 +bit 10_11 +bit 10_110 +bit 10_111 +bit 10_112 +bit 10_113 +bit 10_114 +bit 10_115 +bit 10_116 +bit 10_117 +bit 10_118 +bit 10_119 +bit 10_12 +bit 10_120 +bit 10_121 +bit 10_122 +bit 10_123 +bit 10_124 +bit 10_125 +bit 10_126 +bit 10_127 +bit 10_128 +bit 10_129 +bit 10_13 +bit 10_130 +bit 10_131 +bit 10_132 +bit 10_133 +bit 10_134 +bit 10_135 +bit 10_136 +bit 10_137 +bit 10_138 +bit 10_139 +bit 10_14 +bit 10_140 +bit 10_141 +bit 10_142 +bit 10_143 +bit 10_144 +bit 10_145 +bit 10_146 +bit 10_147 +bit 10_148 +bit 10_149 +bit 10_15 +bit 10_150 +bit 10_151 +bit 10_152 +bit 10_153 +bit 10_154 +bit 10_155 +bit 10_156 +bit 10_157 +bit 10_158 +bit 10_159 +bit 10_16 +bit 10_160 +bit 10_161 +bit 10_162 +bit 10_163 +bit 10_164 +bit 10_165 +bit 10_166 +bit 10_167 +bit 10_168 +bit 10_169 +bit 10_17 +bit 10_170 +bit 10_171 +bit 10_172 +bit 10_173 +bit 10_174 +bit 10_175 +bit 10_176 +bit 10_177 +bit 10_178 +bit 10_179 +bit 10_18 +bit 10_180 +bit 10_181 +bit 10_182 +bit 10_183 +bit 10_184 +bit 10_185 +bit 10_186 +bit 10_187 +bit 10_188 +bit 10_189 +bit 10_19 +bit 10_190 +bit 10_191 +bit 10_192 +bit 10_193 +bit 10_194 +bit 10_195 +bit 10_196 +bit 10_197 +bit 10_198 +bit 10_199 +bit 10_20 +bit 10_200 +bit 10_201 +bit 10_202 +bit 10_203 +bit 10_204 +bit 10_205 +bit 10_206 +bit 10_207 +bit 10_208 +bit 10_209 +bit 10_21 +bit 10_210 +bit 10_211 +bit 10_212 +bit 10_213 +bit 10_214 +bit 10_215 +bit 10_216 +bit 10_217 +bit 10_218 +bit 10_219 +bit 10_22 +bit 10_220 +bit 10_221 +bit 10_222 +bit 10_223 +bit 10_224 +bit 10_225 +bit 10_226 +bit 10_227 +bit 10_228 +bit 10_229 +bit 10_23 +bit 10_230 +bit 10_231 +bit 10_232 +bit 10_233 +bit 10_234 +bit 10_235 +bit 10_236 +bit 10_237 +bit 10_238 +bit 10_239 +bit 10_24 +bit 10_240 +bit 10_241 +bit 10_242 +bit 10_243 +bit 10_244 +bit 10_245 +bit 10_246 +bit 10_247 +bit 10_248 +bit 10_249 +bit 10_25 +bit 10_250 +bit 10_251 +bit 10_252 +bit 10_253 +bit 10_254 +bit 10_255 +bit 10_256 +bit 10_257 +bit 10_258 +bit 10_259 +bit 10_26 +bit 10_260 +bit 10_261 +bit 10_262 +bit 10_263 +bit 10_264 +bit 10_265 +bit 10_266 +bit 10_267 +bit 10_268 +bit 10_269 +bit 10_27 +bit 10_270 +bit 10_271 +bit 10_272 +bit 10_273 +bit 10_274 +bit 10_275 +bit 10_276 +bit 10_277 +bit 10_278 +bit 10_279 +bit 10_28 +bit 10_280 +bit 10_281 +bit 10_282 +bit 10_283 +bit 10_284 +bit 10_285 +bit 10_286 +bit 10_287 +bit 10_288 +bit 10_289 +bit 10_29 +bit 10_290 +bit 10_291 +bit 10_292 +bit 10_293 +bit 10_294 +bit 10_295 +bit 10_296 +bit 10_297 +bit 10_298 +bit 10_299 +bit 10_30 +bit 10_300 +bit 10_301 +bit 10_302 +bit 10_303 +bit 10_304 +bit 10_305 +bit 10_306 +bit 10_307 +bit 10_308 +bit 10_309 +bit 10_31 +bit 10_310 +bit 10_311 +bit 10_312 +bit 10_313 +bit 10_314 +bit 10_315 +bit 10_316 +bit 10_317 +bit 10_318 +bit 10_319 +bit 10_32 +bit 10_33 +bit 10_34 +bit 10_35 +bit 10_36 +bit 10_37 +bit 10_38 +bit 10_39 +bit 10_40 +bit 10_41 +bit 10_42 +bit 10_43 +bit 10_44 +bit 10_45 +bit 10_46 +bit 10_47 +bit 10_48 +bit 10_49 +bit 10_50 +bit 10_51 +bit 10_52 +bit 10_53 +bit 10_54 +bit 10_55 +bit 10_56 +bit 10_57 +bit 10_58 +bit 10_59 +bit 10_60 +bit 10_61 +bit 10_62 +bit 10_63 +bit 10_64 +bit 10_65 +bit 10_66 +bit 10_67 +bit 10_68 +bit 10_69 +bit 10_70 +bit 10_71 +bit 10_72 +bit 10_73 +bit 10_74 +bit 10_75 +bit 10_76 +bit 10_77 +bit 10_78 +bit 10_79 +bit 10_80 +bit 10_81 +bit 10_82 +bit 10_83 +bit 10_84 +bit 10_85 +bit 10_86 +bit 10_87 +bit 10_88 +bit 10_89 +bit 10_90 +bit 10_91 +bit 10_92 +bit 10_93 +bit 10_94 +bit 10_95 +bit 10_96 +bit 10_97 +bit 10_98 +bit 10_99 +bit 11_00 +bit 11_01 +bit 11_02 +bit 11_03 +bit 11_04 +bit 11_05 +bit 11_06 +bit 11_07 +bit 11_08 +bit 11_09 +bit 11_10 +bit 11_100 +bit 11_101 +bit 11_102 +bit 11_103 +bit 11_104 +bit 11_105 +bit 11_106 +bit 11_107 +bit 11_108 +bit 11_109 +bit 11_11 +bit 11_110 +bit 11_111 +bit 11_112 +bit 11_113 +bit 11_114 +bit 11_115 +bit 11_116 +bit 11_117 +bit 11_118 +bit 11_119 +bit 11_12 +bit 11_120 +bit 11_121 +bit 11_122 +bit 11_123 +bit 11_124 +bit 11_125 +bit 11_126 +bit 11_127 +bit 11_128 +bit 11_129 +bit 11_13 +bit 11_130 +bit 11_131 +bit 11_132 +bit 11_133 +bit 11_134 +bit 11_135 +bit 11_136 +bit 11_137 +bit 11_138 +bit 11_139 +bit 11_14 +bit 11_140 +bit 11_141 +bit 11_142 +bit 11_143 +bit 11_144 +bit 11_145 +bit 11_146 +bit 11_147 +bit 11_148 +bit 11_149 +bit 11_15 +bit 11_150 +bit 11_151 +bit 11_152 +bit 11_153 +bit 11_154 +bit 11_155 +bit 11_156 +bit 11_157 +bit 11_158 +bit 11_159 +bit 11_16 +bit 11_160 +bit 11_161 +bit 11_162 +bit 11_163 +bit 11_164 +bit 11_165 +bit 11_166 +bit 11_167 +bit 11_168 +bit 11_169 +bit 11_17 +bit 11_170 +bit 11_171 +bit 11_172 +bit 11_173 +bit 11_174 +bit 11_175 +bit 11_176 +bit 11_177 +bit 11_178 +bit 11_179 +bit 11_18 +bit 11_180 +bit 11_181 +bit 11_182 +bit 11_183 +bit 11_184 +bit 11_185 +bit 11_186 +bit 11_187 +bit 11_188 +bit 11_189 +bit 11_19 +bit 11_190 +bit 11_191 +bit 11_192 +bit 11_193 +bit 11_194 +bit 11_195 +bit 11_196 +bit 11_197 +bit 11_198 +bit 11_199 +bit 11_20 +bit 11_200 +bit 11_201 +bit 11_202 +bit 11_203 +bit 11_204 +bit 11_205 +bit 11_206 +bit 11_207 +bit 11_208 +bit 11_209 +bit 11_21 +bit 11_210 +bit 11_211 +bit 11_212 +bit 11_213 +bit 11_214 +bit 11_215 +bit 11_216 +bit 11_217 +bit 11_218 +bit 11_219 +bit 11_22 +bit 11_220 +bit 11_221 +bit 11_222 +bit 11_223 +bit 11_224 +bit 11_225 +bit 11_226 +bit 11_227 +bit 11_228 +bit 11_229 +bit 11_23 +bit 11_230 +bit 11_231 +bit 11_232 +bit 11_233 +bit 11_234 +bit 11_235 +bit 11_236 +bit 11_237 +bit 11_238 +bit 11_239 +bit 11_24 +bit 11_240 +bit 11_241 +bit 11_242 +bit 11_243 +bit 11_244 +bit 11_245 +bit 11_246 +bit 11_247 +bit 11_248 +bit 11_249 +bit 11_25 +bit 11_250 +bit 11_251 +bit 11_252 +bit 11_253 +bit 11_254 +bit 11_255 +bit 11_256 +bit 11_257 +bit 11_258 +bit 11_259 +bit 11_26 +bit 11_260 +bit 11_261 +bit 11_262 +bit 11_263 +bit 11_264 +bit 11_265 +bit 11_266 +bit 11_267 +bit 11_268 +bit 11_269 +bit 11_27 +bit 11_270 +bit 11_271 +bit 11_272 +bit 11_273 +bit 11_274 +bit 11_275 +bit 11_276 +bit 11_277 +bit 11_278 +bit 11_279 +bit 11_28 +bit 11_280 +bit 11_281 +bit 11_282 +bit 11_283 +bit 11_284 +bit 11_285 +bit 11_286 +bit 11_287 +bit 11_288 +bit 11_289 +bit 11_29 +bit 11_290 +bit 11_291 +bit 11_292 +bit 11_293 +bit 11_294 +bit 11_295 +bit 11_296 +bit 11_297 +bit 11_298 +bit 11_299 +bit 11_30 +bit 11_300 +bit 11_301 +bit 11_302 +bit 11_303 +bit 11_304 +bit 11_305 +bit 11_306 +bit 11_307 +bit 11_308 +bit 11_309 +bit 11_31 +bit 11_310 +bit 11_311 +bit 11_312 +bit 11_313 +bit 11_314 +bit 11_315 +bit 11_316 +bit 11_317 +bit 11_318 +bit 11_319 +bit 11_32 +bit 11_33 +bit 11_34 +bit 11_35 +bit 11_36 +bit 11_37 +bit 11_38 +bit 11_39 +bit 11_40 +bit 11_41 +bit 11_42 +bit 11_43 +bit 11_44 +bit 11_45 +bit 11_46 +bit 11_47 +bit 11_48 +bit 11_49 +bit 11_50 +bit 11_51 +bit 11_52 +bit 11_53 +bit 11_54 +bit 11_55 +bit 11_56 +bit 11_57 +bit 11_58 +bit 11_59 +bit 11_60 +bit 11_61 +bit 11_62 +bit 11_63 +bit 11_64 +bit 11_65 +bit 11_66 +bit 11_67 +bit 11_68 +bit 11_69 +bit 11_70 +bit 11_71 +bit 11_72 +bit 11_73 +bit 11_74 +bit 11_75 +bit 11_76 +bit 11_77 +bit 11_78 +bit 11_79 +bit 11_80 +bit 11_81 +bit 11_82 +bit 11_83 +bit 11_84 +bit 11_85 +bit 11_86 +bit 11_87 +bit 11_88 +bit 11_89 +bit 11_90 +bit 11_91 +bit 11_92 +bit 11_93 +bit 11_94 +bit 11_95 +bit 11_96 +bit 11_97 +bit 11_98 +bit 11_99 +bit 12_00 +bit 12_01 +bit 12_02 +bit 12_03 +bit 12_04 +bit 12_05 +bit 12_06 +bit 12_07 +bit 12_08 +bit 12_09 +bit 12_10 +bit 12_100 +bit 12_101 +bit 12_102 +bit 12_103 +bit 12_104 +bit 12_105 +bit 12_106 +bit 12_107 +bit 12_108 +bit 12_109 +bit 12_11 +bit 12_110 +bit 12_111 +bit 12_112 +bit 12_113 +bit 12_114 +bit 12_115 +bit 12_116 +bit 12_117 +bit 12_118 +bit 12_119 +bit 12_12 +bit 12_120 +bit 12_121 +bit 12_122 +bit 12_123 +bit 12_124 +bit 12_125 +bit 12_126 +bit 12_127 +bit 12_128 +bit 12_129 +bit 12_13 +bit 12_130 +bit 12_131 +bit 12_132 +bit 12_133 +bit 12_134 +bit 12_135 +bit 12_136 +bit 12_137 +bit 12_138 +bit 12_139 +bit 12_14 +bit 12_140 +bit 12_141 +bit 12_142 +bit 12_143 +bit 12_144 +bit 12_145 +bit 12_146 +bit 12_147 +bit 12_148 +bit 12_149 +bit 12_15 +bit 12_150 +bit 12_151 +bit 12_152 +bit 12_153 +bit 12_154 +bit 12_155 +bit 12_156 +bit 12_157 +bit 12_158 +bit 12_159 +bit 12_16 +bit 12_160 +bit 12_161 +bit 12_162 +bit 12_163 +bit 12_164 +bit 12_165 +bit 12_166 +bit 12_167 +bit 12_168 +bit 12_169 +bit 12_17 +bit 12_170 +bit 12_171 +bit 12_172 +bit 12_173 +bit 12_174 +bit 12_175 +bit 12_176 +bit 12_177 +bit 12_178 +bit 12_179 +bit 12_18 +bit 12_180 +bit 12_181 +bit 12_182 +bit 12_183 +bit 12_184 +bit 12_185 +bit 12_186 +bit 12_187 +bit 12_188 +bit 12_189 +bit 12_19 +bit 12_190 +bit 12_191 +bit 12_192 +bit 12_193 +bit 12_194 +bit 12_195 +bit 12_196 +bit 12_197 +bit 12_198 +bit 12_199 +bit 12_20 +bit 12_200 +bit 12_201 +bit 12_202 +bit 12_203 +bit 12_204 +bit 12_205 +bit 12_206 +bit 12_207 +bit 12_208 +bit 12_209 +bit 12_21 +bit 12_210 +bit 12_211 +bit 12_212 +bit 12_213 +bit 12_214 +bit 12_215 +bit 12_216 +bit 12_217 +bit 12_218 +bit 12_219 +bit 12_22 +bit 12_220 +bit 12_221 +bit 12_222 +bit 12_223 +bit 12_224 +bit 12_225 +bit 12_226 +bit 12_227 +bit 12_228 +bit 12_229 +bit 12_23 +bit 12_230 +bit 12_231 +bit 12_232 +bit 12_233 +bit 12_234 +bit 12_235 +bit 12_236 +bit 12_237 +bit 12_238 +bit 12_239 +bit 12_24 +bit 12_240 +bit 12_241 +bit 12_242 +bit 12_243 +bit 12_244 +bit 12_245 +bit 12_246 +bit 12_247 +bit 12_248 +bit 12_249 +bit 12_25 +bit 12_250 +bit 12_251 +bit 12_252 +bit 12_253 +bit 12_254 +bit 12_255 +bit 12_256 +bit 12_257 +bit 12_258 +bit 12_259 +bit 12_26 +bit 12_260 +bit 12_261 +bit 12_262 +bit 12_263 +bit 12_264 +bit 12_265 +bit 12_266 +bit 12_267 +bit 12_268 +bit 12_269 +bit 12_27 +bit 12_270 +bit 12_271 +bit 12_272 +bit 12_273 +bit 12_274 +bit 12_275 +bit 12_276 +bit 12_277 +bit 12_278 +bit 12_279 +bit 12_28 +bit 12_280 +bit 12_281 +bit 12_282 +bit 12_283 +bit 12_284 +bit 12_285 +bit 12_286 +bit 12_287 +bit 12_288 +bit 12_289 +bit 12_29 +bit 12_290 +bit 12_291 +bit 12_292 +bit 12_293 +bit 12_294 +bit 12_295 +bit 12_296 +bit 12_297 +bit 12_298 +bit 12_299 +bit 12_30 +bit 12_300 +bit 12_301 +bit 12_302 +bit 12_303 +bit 12_304 +bit 12_305 +bit 12_306 +bit 12_307 +bit 12_308 +bit 12_309 +bit 12_31 +bit 12_310 +bit 12_311 +bit 12_312 +bit 12_313 +bit 12_314 +bit 12_315 +bit 12_316 +bit 12_317 +bit 12_318 +bit 12_319 +bit 12_32 +bit 12_33 +bit 12_34 +bit 12_35 +bit 12_36 +bit 12_37 +bit 12_38 +bit 12_39 +bit 12_40 +bit 12_41 +bit 12_42 +bit 12_43 +bit 12_44 +bit 12_45 +bit 12_46 +bit 12_47 +bit 12_48 +bit 12_49 +bit 12_50 +bit 12_51 +bit 12_52 +bit 12_53 +bit 12_54 +bit 12_55 +bit 12_56 +bit 12_57 +bit 12_58 +bit 12_59 +bit 12_60 +bit 12_61 +bit 12_62 +bit 12_63 +bit 12_64 +bit 12_65 +bit 12_66 +bit 12_67 +bit 12_68 +bit 12_69 +bit 12_70 +bit 12_71 +bit 12_72 +bit 12_73 +bit 12_74 +bit 12_75 +bit 12_76 +bit 12_77 +bit 12_78 +bit 12_79 +bit 12_80 +bit 12_81 +bit 12_82 +bit 12_83 +bit 12_84 +bit 12_85 +bit 12_86 +bit 12_87 +bit 12_88 +bit 12_89 +bit 12_90 +bit 12_91 +bit 12_92 +bit 12_93 +bit 12_94 +bit 12_95 +bit 12_96 +bit 12_97 +bit 12_98 +bit 12_99 +bit 13_00 +bit 13_01 +bit 13_02 +bit 13_03 +bit 13_04 +bit 13_05 +bit 13_06 +bit 13_07 +bit 13_08 +bit 13_09 +bit 13_10 +bit 13_100 +bit 13_101 +bit 13_102 +bit 13_103 +bit 13_104 +bit 13_105 +bit 13_106 +bit 13_107 +bit 13_108 +bit 13_109 +bit 13_11 +bit 13_110 +bit 13_111 +bit 13_112 +bit 13_113 +bit 13_114 +bit 13_115 +bit 13_116 +bit 13_117 +bit 13_118 +bit 13_119 +bit 13_12 +bit 13_120 +bit 13_121 +bit 13_122 +bit 13_123 +bit 13_124 +bit 13_125 +bit 13_126 +bit 13_127 +bit 13_128 +bit 13_129 +bit 13_13 +bit 13_130 +bit 13_131 +bit 13_132 +bit 13_133 +bit 13_134 +bit 13_135 +bit 13_136 +bit 13_137 +bit 13_138 +bit 13_139 +bit 13_14 +bit 13_140 +bit 13_141 +bit 13_142 +bit 13_143 +bit 13_144 +bit 13_145 +bit 13_146 +bit 13_147 +bit 13_148 +bit 13_149 +bit 13_15 +bit 13_150 +bit 13_151 +bit 13_152 +bit 13_153 +bit 13_154 +bit 13_155 +bit 13_156 +bit 13_157 +bit 13_158 +bit 13_159 +bit 13_16 +bit 13_160 +bit 13_161 +bit 13_162 +bit 13_163 +bit 13_164 +bit 13_165 +bit 13_166 +bit 13_167 +bit 13_168 +bit 13_169 +bit 13_17 +bit 13_170 +bit 13_171 +bit 13_172 +bit 13_173 +bit 13_174 +bit 13_175 +bit 13_176 +bit 13_177 +bit 13_178 +bit 13_179 +bit 13_18 +bit 13_180 +bit 13_181 +bit 13_182 +bit 13_183 +bit 13_184 +bit 13_185 +bit 13_186 +bit 13_187 +bit 13_188 +bit 13_189 +bit 13_19 +bit 13_190 +bit 13_191 +bit 13_192 +bit 13_193 +bit 13_194 +bit 13_195 +bit 13_196 +bit 13_197 +bit 13_198 +bit 13_199 +bit 13_20 +bit 13_200 +bit 13_201 +bit 13_202 +bit 13_203 +bit 13_204 +bit 13_205 +bit 13_206 +bit 13_207 +bit 13_208 +bit 13_209 +bit 13_21 +bit 13_210 +bit 13_211 +bit 13_212 +bit 13_213 +bit 13_214 +bit 13_215 +bit 13_216 +bit 13_217 +bit 13_218 +bit 13_219 +bit 13_22 +bit 13_220 +bit 13_221 +bit 13_222 +bit 13_223 +bit 13_224 +bit 13_225 +bit 13_226 +bit 13_227 +bit 13_228 +bit 13_229 +bit 13_23 +bit 13_230 +bit 13_231 +bit 13_232 +bit 13_233 +bit 13_234 +bit 13_235 +bit 13_236 +bit 13_237 +bit 13_238 +bit 13_239 +bit 13_24 +bit 13_240 +bit 13_241 +bit 13_242 +bit 13_243 +bit 13_244 +bit 13_245 +bit 13_246 +bit 13_247 +bit 13_248 +bit 13_249 +bit 13_25 +bit 13_250 +bit 13_251 +bit 13_252 +bit 13_253 +bit 13_254 +bit 13_255 +bit 13_256 +bit 13_257 +bit 13_258 +bit 13_259 +bit 13_26 +bit 13_260 +bit 13_261 +bit 13_262 +bit 13_263 +bit 13_264 +bit 13_265 +bit 13_266 +bit 13_267 +bit 13_268 +bit 13_269 +bit 13_27 +bit 13_270 +bit 13_271 +bit 13_272 +bit 13_273 +bit 13_274 +bit 13_275 +bit 13_276 +bit 13_277 +bit 13_278 +bit 13_279 +bit 13_28 +bit 13_280 +bit 13_281 +bit 13_282 +bit 13_283 +bit 13_284 +bit 13_285 +bit 13_286 +bit 13_287 +bit 13_288 +bit 13_289 +bit 13_29 +bit 13_290 +bit 13_291 +bit 13_292 +bit 13_293 +bit 13_294 +bit 13_295 +bit 13_296 +bit 13_297 +bit 13_298 +bit 13_299 +bit 13_30 +bit 13_300 +bit 13_301 +bit 13_302 +bit 13_303 +bit 13_304 +bit 13_305 +bit 13_306 +bit 13_307 +bit 13_308 +bit 13_309 +bit 13_31 +bit 13_310 +bit 13_311 +bit 13_312 +bit 13_313 +bit 13_314 +bit 13_315 +bit 13_316 +bit 13_317 +bit 13_318 +bit 13_319 +bit 13_32 +bit 13_33 +bit 13_34 +bit 13_35 +bit 13_36 +bit 13_37 +bit 13_38 +bit 13_39 +bit 13_40 +bit 13_41 +bit 13_42 +bit 13_43 +bit 13_44 +bit 13_45 +bit 13_46 +bit 13_47 +bit 13_48 +bit 13_49 +bit 13_50 +bit 13_51 +bit 13_52 +bit 13_53 +bit 13_54 +bit 13_55 +bit 13_56 +bit 13_57 +bit 13_58 +bit 13_59 +bit 13_60 +bit 13_61 +bit 13_62 +bit 13_63 +bit 13_64 +bit 13_65 +bit 13_66 +bit 13_67 +bit 13_68 +bit 13_69 +bit 13_70 +bit 13_71 +bit 13_72 +bit 13_73 +bit 13_74 +bit 13_75 +bit 13_76 +bit 13_77 +bit 13_78 +bit 13_79 +bit 13_80 +bit 13_81 +bit 13_82 +bit 13_83 +bit 13_84 +bit 13_85 +bit 13_86 +bit 13_87 +bit 13_88 +bit 13_89 +bit 13_90 +bit 13_91 +bit 13_92 +bit 13_93 +bit 13_94 +bit 13_95 +bit 13_96 +bit 13_97 +bit 13_98 +bit 13_99 +bit 14_00 +bit 14_01 +bit 14_02 +bit 14_03 +bit 14_04 +bit 14_05 +bit 14_06 +bit 14_07 +bit 14_08 +bit 14_09 +bit 14_10 +bit 14_100 +bit 14_101 +bit 14_102 +bit 14_103 +bit 14_104 +bit 14_105 +bit 14_106 +bit 14_107 +bit 14_108 +bit 14_109 +bit 14_11 +bit 14_110 +bit 14_111 +bit 14_112 +bit 14_113 +bit 14_114 +bit 14_115 +bit 14_116 +bit 14_117 +bit 14_118 +bit 14_119 +bit 14_12 +bit 14_120 +bit 14_121 +bit 14_122 +bit 14_123 +bit 14_124 +bit 14_125 +bit 14_126 +bit 14_127 +bit 14_128 +bit 14_129 +bit 14_13 +bit 14_130 +bit 14_131 +bit 14_132 +bit 14_133 +bit 14_134 +bit 14_135 +bit 14_136 +bit 14_137 +bit 14_138 +bit 14_139 +bit 14_14 +bit 14_140 +bit 14_141 +bit 14_142 +bit 14_143 +bit 14_144 +bit 14_145 +bit 14_146 +bit 14_147 +bit 14_148 +bit 14_149 +bit 14_15 +bit 14_150 +bit 14_151 +bit 14_152 +bit 14_153 +bit 14_154 +bit 14_155 +bit 14_156 +bit 14_157 +bit 14_158 +bit 14_159 +bit 14_16 +bit 14_160 +bit 14_161 +bit 14_162 +bit 14_163 +bit 14_164 +bit 14_165 +bit 14_166 +bit 14_167 +bit 14_168 +bit 14_169 +bit 14_17 +bit 14_170 +bit 14_171 +bit 14_172 +bit 14_173 +bit 14_174 +bit 14_175 +bit 14_176 +bit 14_177 +bit 14_178 +bit 14_179 +bit 14_18 +bit 14_180 +bit 14_181 +bit 14_182 +bit 14_183 +bit 14_184 +bit 14_185 +bit 14_186 +bit 14_187 +bit 14_188 +bit 14_189 +bit 14_19 +bit 14_190 +bit 14_191 +bit 14_192 +bit 14_193 +bit 14_194 +bit 14_195 +bit 14_196 +bit 14_197 +bit 14_198 +bit 14_199 +bit 14_20 +bit 14_200 +bit 14_201 +bit 14_202 +bit 14_203 +bit 14_204 +bit 14_205 +bit 14_206 +bit 14_207 +bit 14_208 +bit 14_209 +bit 14_21 +bit 14_210 +bit 14_211 +bit 14_212 +bit 14_213 +bit 14_214 +bit 14_215 +bit 14_216 +bit 14_217 +bit 14_218 +bit 14_219 +bit 14_22 +bit 14_220 +bit 14_221 +bit 14_222 +bit 14_223 +bit 14_224 +bit 14_225 +bit 14_226 +bit 14_227 +bit 14_228 +bit 14_229 +bit 14_23 +bit 14_230 +bit 14_231 +bit 14_232 +bit 14_233 +bit 14_234 +bit 14_235 +bit 14_236 +bit 14_237 +bit 14_238 +bit 14_239 +bit 14_24 +bit 14_240 +bit 14_241 +bit 14_242 +bit 14_243 +bit 14_244 +bit 14_245 +bit 14_246 +bit 14_247 +bit 14_248 +bit 14_249 +bit 14_25 +bit 14_250 +bit 14_251 +bit 14_252 +bit 14_253 +bit 14_254 +bit 14_255 +bit 14_256 +bit 14_257 +bit 14_258 +bit 14_259 +bit 14_26 +bit 14_260 +bit 14_261 +bit 14_262 +bit 14_263 +bit 14_264 +bit 14_265 +bit 14_266 +bit 14_267 +bit 14_268 +bit 14_269 +bit 14_27 +bit 14_270 +bit 14_271 +bit 14_272 +bit 14_273 +bit 14_274 +bit 14_275 +bit 14_276 +bit 14_277 +bit 14_278 +bit 14_279 +bit 14_28 +bit 14_280 +bit 14_281 +bit 14_282 +bit 14_283 +bit 14_284 +bit 14_285 +bit 14_286 +bit 14_287 +bit 14_288 +bit 14_289 +bit 14_29 +bit 14_290 +bit 14_291 +bit 14_292 +bit 14_293 +bit 14_294 +bit 14_295 +bit 14_296 +bit 14_297 +bit 14_298 +bit 14_299 +bit 14_30 +bit 14_300 +bit 14_301 +bit 14_302 +bit 14_303 +bit 14_304 +bit 14_305 +bit 14_306 +bit 14_307 +bit 14_308 +bit 14_309 +bit 14_31 +bit 14_310 +bit 14_311 +bit 14_312 +bit 14_313 +bit 14_314 +bit 14_315 +bit 14_316 +bit 14_317 +bit 14_318 +bit 14_319 +bit 14_32 +bit 14_33 +bit 14_34 +bit 14_35 +bit 14_36 +bit 14_37 +bit 14_38 +bit 14_39 +bit 14_40 +bit 14_41 +bit 14_42 +bit 14_43 +bit 14_44 +bit 14_45 +bit 14_46 +bit 14_47 +bit 14_48 +bit 14_49 +bit 14_50 +bit 14_51 +bit 14_52 +bit 14_53 +bit 14_54 +bit 14_55 +bit 14_56 +bit 14_57 +bit 14_58 +bit 14_59 +bit 14_60 +bit 14_61 +bit 14_62 +bit 14_63 +bit 14_64 +bit 14_65 +bit 14_66 +bit 14_67 +bit 14_68 +bit 14_69 +bit 14_70 +bit 14_71 +bit 14_72 +bit 14_73 +bit 14_74 +bit 14_75 +bit 14_76 +bit 14_77 +bit 14_78 +bit 14_79 +bit 14_80 +bit 14_81 +bit 14_82 +bit 14_83 +bit 14_84 +bit 14_85 +bit 14_86 +bit 14_87 +bit 14_88 +bit 14_89 +bit 14_90 +bit 14_91 +bit 14_92 +bit 14_93 +bit 14_94 +bit 14_95 +bit 14_96 +bit 14_97 +bit 14_98 +bit 14_99 +bit 15_00 +bit 15_01 +bit 15_02 +bit 15_03 +bit 15_04 +bit 15_05 +bit 15_06 +bit 15_07 +bit 15_08 +bit 15_09 +bit 15_10 +bit 15_100 +bit 15_101 +bit 15_102 +bit 15_103 +bit 15_104 +bit 15_105 +bit 15_106 +bit 15_107 +bit 15_108 +bit 15_109 +bit 15_11 +bit 15_110 +bit 15_111 +bit 15_112 +bit 15_113 +bit 15_114 +bit 15_115 +bit 15_116 +bit 15_117 +bit 15_118 +bit 15_119 +bit 15_12 +bit 15_120 +bit 15_121 +bit 15_122 +bit 15_123 +bit 15_124 +bit 15_125 +bit 15_126 +bit 15_127 +bit 15_128 +bit 15_129 +bit 15_13 +bit 15_130 +bit 15_131 +bit 15_132 +bit 15_133 +bit 15_134 +bit 15_135 +bit 15_136 +bit 15_137 +bit 15_138 +bit 15_139 +bit 15_14 +bit 15_140 +bit 15_141 +bit 15_142 +bit 15_143 +bit 15_144 +bit 15_145 +bit 15_146 +bit 15_147 +bit 15_148 +bit 15_149 +bit 15_15 +bit 15_150 +bit 15_151 +bit 15_152 +bit 15_153 +bit 15_154 +bit 15_155 +bit 15_156 +bit 15_157 +bit 15_158 +bit 15_159 +bit 15_16 +bit 15_160 +bit 15_161 +bit 15_162 +bit 15_163 +bit 15_164 +bit 15_165 +bit 15_166 +bit 15_167 +bit 15_168 +bit 15_169 +bit 15_17 +bit 15_170 +bit 15_171 +bit 15_172 +bit 15_173 +bit 15_174 +bit 15_175 +bit 15_176 +bit 15_177 +bit 15_178 +bit 15_179 +bit 15_18 +bit 15_180 +bit 15_181 +bit 15_182 +bit 15_183 +bit 15_184 +bit 15_185 +bit 15_186 +bit 15_187 +bit 15_188 +bit 15_189 +bit 15_19 +bit 15_190 +bit 15_191 +bit 15_192 +bit 15_193 +bit 15_194 +bit 15_195 +bit 15_196 +bit 15_197 +bit 15_198 +bit 15_199 +bit 15_20 +bit 15_200 +bit 15_201 +bit 15_202 +bit 15_203 +bit 15_204 +bit 15_205 +bit 15_206 +bit 15_207 +bit 15_208 +bit 15_209 +bit 15_21 +bit 15_210 +bit 15_211 +bit 15_212 +bit 15_213 +bit 15_214 +bit 15_215 +bit 15_216 +bit 15_217 +bit 15_218 +bit 15_219 +bit 15_22 +bit 15_220 +bit 15_221 +bit 15_222 +bit 15_223 +bit 15_224 +bit 15_225 +bit 15_226 +bit 15_227 +bit 15_228 +bit 15_229 +bit 15_23 +bit 15_230 +bit 15_231 +bit 15_232 +bit 15_233 +bit 15_234 +bit 15_235 +bit 15_236 +bit 15_237 +bit 15_238 +bit 15_239 +bit 15_24 +bit 15_240 +bit 15_241 +bit 15_242 +bit 15_243 +bit 15_244 +bit 15_245 +bit 15_246 +bit 15_247 +bit 15_248 +bit 15_249 +bit 15_25 +bit 15_250 +bit 15_251 +bit 15_252 +bit 15_253 +bit 15_254 +bit 15_255 +bit 15_256 +bit 15_257 +bit 15_258 +bit 15_259 +bit 15_26 +bit 15_260 +bit 15_261 +bit 15_262 +bit 15_263 +bit 15_264 +bit 15_265 +bit 15_266 +bit 15_267 +bit 15_268 +bit 15_269 +bit 15_27 +bit 15_270 +bit 15_271 +bit 15_272 +bit 15_273 +bit 15_274 +bit 15_275 +bit 15_276 +bit 15_277 +bit 15_278 +bit 15_279 +bit 15_28 +bit 15_280 +bit 15_281 +bit 15_282 +bit 15_283 +bit 15_284 +bit 15_285 +bit 15_286 +bit 15_287 +bit 15_288 +bit 15_289 +bit 15_29 +bit 15_290 +bit 15_291 +bit 15_292 +bit 15_293 +bit 15_294 +bit 15_295 +bit 15_296 +bit 15_297 +bit 15_298 +bit 15_299 +bit 15_30 +bit 15_300 +bit 15_301 +bit 15_302 +bit 15_303 +bit 15_304 +bit 15_305 +bit 15_306 +bit 15_307 +bit 15_308 +bit 15_309 +bit 15_31 +bit 15_310 +bit 15_311 +bit 15_312 +bit 15_313 +bit 15_314 +bit 15_315 +bit 15_316 +bit 15_317 +bit 15_318 +bit 15_319 +bit 15_32 +bit 15_33 +bit 15_34 +bit 15_35 +bit 15_36 +bit 15_37 +bit 15_38 +bit 15_39 +bit 15_40 +bit 15_41 +bit 15_42 +bit 15_43 +bit 15_44 +bit 15_45 +bit 15_46 +bit 15_47 +bit 15_48 +bit 15_49 +bit 15_50 +bit 15_51 +bit 15_52 +bit 15_53 +bit 15_54 +bit 15_55 +bit 15_56 +bit 15_57 +bit 15_58 +bit 15_59 +bit 15_60 +bit 15_61 +bit 15_62 +bit 15_63 +bit 15_64 +bit 15_65 +bit 15_66 +bit 15_67 +bit 15_68 +bit 15_69 +bit 15_70 +bit 15_71 +bit 15_72 +bit 15_73 +bit 15_74 +bit 15_75 +bit 15_76 +bit 15_77 +bit 15_78 +bit 15_79 +bit 15_80 +bit 15_81 +bit 15_82 +bit 15_83 +bit 15_84 +bit 15_85 +bit 15_86 +bit 15_87 +bit 15_88 +bit 15_89 +bit 15_90 +bit 15_91 +bit 15_92 +bit 15_93 +bit 15_94 +bit 15_95 +bit 15_96 +bit 15_97 +bit 15_98 +bit 15_99 +bit 16_00 +bit 16_01 +bit 16_02 +bit 16_03 +bit 16_04 +bit 16_05 +bit 16_06 +bit 16_07 +bit 16_08 +bit 16_09 +bit 16_10 +bit 16_100 +bit 16_101 +bit 16_102 +bit 16_103 +bit 16_104 +bit 16_105 +bit 16_106 +bit 16_107 +bit 16_108 +bit 16_109 +bit 16_11 +bit 16_110 +bit 16_111 +bit 16_112 +bit 16_113 +bit 16_114 +bit 16_115 +bit 16_116 +bit 16_117 +bit 16_118 +bit 16_119 +bit 16_12 +bit 16_120 +bit 16_121 +bit 16_122 +bit 16_123 +bit 16_124 +bit 16_125 +bit 16_126 +bit 16_127 +bit 16_128 +bit 16_129 +bit 16_13 +bit 16_130 +bit 16_131 +bit 16_132 +bit 16_133 +bit 16_134 +bit 16_135 +bit 16_136 +bit 16_137 +bit 16_138 +bit 16_139 +bit 16_14 +bit 16_140 +bit 16_141 +bit 16_142 +bit 16_143 +bit 16_144 +bit 16_145 +bit 16_146 +bit 16_147 +bit 16_148 +bit 16_149 +bit 16_15 +bit 16_150 +bit 16_151 +bit 16_152 +bit 16_153 +bit 16_154 +bit 16_155 +bit 16_156 +bit 16_157 +bit 16_158 +bit 16_159 +bit 16_16 +bit 16_160 +bit 16_161 +bit 16_162 +bit 16_163 +bit 16_164 +bit 16_165 +bit 16_166 +bit 16_167 +bit 16_168 +bit 16_169 +bit 16_17 +bit 16_170 +bit 16_171 +bit 16_172 +bit 16_173 +bit 16_174 +bit 16_175 +bit 16_176 +bit 16_177 +bit 16_178 +bit 16_179 +bit 16_18 +bit 16_180 +bit 16_181 +bit 16_182 +bit 16_183 +bit 16_184 +bit 16_185 +bit 16_186 +bit 16_187 +bit 16_188 +bit 16_189 +bit 16_19 +bit 16_190 +bit 16_191 +bit 16_192 +bit 16_193 +bit 16_194 +bit 16_195 +bit 16_196 +bit 16_197 +bit 16_198 +bit 16_199 +bit 16_20 +bit 16_200 +bit 16_201 +bit 16_202 +bit 16_203 +bit 16_204 +bit 16_205 +bit 16_206 +bit 16_207 +bit 16_208 +bit 16_209 +bit 16_21 +bit 16_210 +bit 16_211 +bit 16_212 +bit 16_213 +bit 16_214 +bit 16_215 +bit 16_216 +bit 16_217 +bit 16_218 +bit 16_219 +bit 16_22 +bit 16_220 +bit 16_221 +bit 16_222 +bit 16_223 +bit 16_224 +bit 16_225 +bit 16_226 +bit 16_227 +bit 16_228 +bit 16_229 +bit 16_23 +bit 16_230 +bit 16_231 +bit 16_232 +bit 16_233 +bit 16_234 +bit 16_235 +bit 16_236 +bit 16_237 +bit 16_238 +bit 16_239 +bit 16_24 +bit 16_240 +bit 16_241 +bit 16_242 +bit 16_243 +bit 16_244 +bit 16_245 +bit 16_246 +bit 16_247 +bit 16_248 +bit 16_249 +bit 16_25 +bit 16_250 +bit 16_251 +bit 16_252 +bit 16_253 +bit 16_254 +bit 16_255 +bit 16_256 +bit 16_257 +bit 16_258 +bit 16_259 +bit 16_26 +bit 16_260 +bit 16_261 +bit 16_262 +bit 16_263 +bit 16_264 +bit 16_265 +bit 16_266 +bit 16_267 +bit 16_268 +bit 16_269 +bit 16_27 +bit 16_270 +bit 16_271 +bit 16_272 +bit 16_273 +bit 16_274 +bit 16_275 +bit 16_276 +bit 16_277 +bit 16_278 +bit 16_279 +bit 16_28 +bit 16_280 +bit 16_281 +bit 16_282 +bit 16_283 +bit 16_284 +bit 16_285 +bit 16_286 +bit 16_287 +bit 16_288 +bit 16_289 +bit 16_29 +bit 16_290 +bit 16_291 +bit 16_292 +bit 16_293 +bit 16_294 +bit 16_295 +bit 16_296 +bit 16_297 +bit 16_298 +bit 16_299 +bit 16_30 +bit 16_300 +bit 16_301 +bit 16_302 +bit 16_303 +bit 16_304 +bit 16_305 +bit 16_306 +bit 16_307 +bit 16_308 +bit 16_309 +bit 16_31 +bit 16_310 +bit 16_311 +bit 16_312 +bit 16_313 +bit 16_314 +bit 16_315 +bit 16_316 +bit 16_317 +bit 16_318 +bit 16_319 +bit 16_32 +bit 16_33 +bit 16_34 +bit 16_35 +bit 16_36 +bit 16_37 +bit 16_38 +bit 16_39 +bit 16_40 +bit 16_41 +bit 16_42 +bit 16_43 +bit 16_44 +bit 16_45 +bit 16_46 +bit 16_47 +bit 16_48 +bit 16_49 +bit 16_50 +bit 16_51 +bit 16_52 +bit 16_53 +bit 16_54 +bit 16_55 +bit 16_56 +bit 16_57 +bit 16_58 +bit 16_59 +bit 16_60 +bit 16_61 +bit 16_62 +bit 16_63 +bit 16_64 +bit 16_65 +bit 16_66 +bit 16_67 +bit 16_68 +bit 16_69 +bit 16_70 +bit 16_71 +bit 16_72 +bit 16_73 +bit 16_74 +bit 16_75 +bit 16_76 +bit 16_77 +bit 16_78 +bit 16_79 +bit 16_80 +bit 16_81 +bit 16_82 +bit 16_83 +bit 16_84 +bit 16_85 +bit 16_86 +bit 16_87 +bit 16_88 +bit 16_89 +bit 16_90 +bit 16_91 +bit 16_92 +bit 16_93 +bit 16_94 +bit 16_95 +bit 16_96 +bit 16_97 +bit 16_98 +bit 16_99 +bit 17_00 +bit 17_01 +bit 17_02 +bit 17_03 +bit 17_04 +bit 17_05 +bit 17_06 +bit 17_07 +bit 17_08 +bit 17_09 +bit 17_10 +bit 17_100 +bit 17_101 +bit 17_102 +bit 17_103 +bit 17_104 +bit 17_105 +bit 17_106 +bit 17_107 +bit 17_108 +bit 17_109 +bit 17_11 +bit 17_110 +bit 17_111 +bit 17_112 +bit 17_113 +bit 17_114 +bit 17_115 +bit 17_116 +bit 17_117 +bit 17_118 +bit 17_119 +bit 17_12 +bit 17_120 +bit 17_121 +bit 17_122 +bit 17_123 +bit 17_124 +bit 17_125 +bit 17_126 +bit 17_127 +bit 17_128 +bit 17_129 +bit 17_13 +bit 17_130 +bit 17_131 +bit 17_132 +bit 17_133 +bit 17_134 +bit 17_135 +bit 17_136 +bit 17_137 +bit 17_138 +bit 17_139 +bit 17_14 +bit 17_140 +bit 17_141 +bit 17_142 +bit 17_143 +bit 17_144 +bit 17_145 +bit 17_146 +bit 17_147 +bit 17_148 +bit 17_149 +bit 17_15 +bit 17_150 +bit 17_151 +bit 17_152 +bit 17_153 +bit 17_154 +bit 17_155 +bit 17_156 +bit 17_157 +bit 17_158 +bit 17_159 +bit 17_16 +bit 17_160 +bit 17_161 +bit 17_162 +bit 17_163 +bit 17_164 +bit 17_165 +bit 17_166 +bit 17_167 +bit 17_168 +bit 17_169 +bit 17_17 +bit 17_170 +bit 17_171 +bit 17_172 +bit 17_173 +bit 17_174 +bit 17_175 +bit 17_176 +bit 17_177 +bit 17_178 +bit 17_179 +bit 17_18 +bit 17_180 +bit 17_181 +bit 17_182 +bit 17_183 +bit 17_184 +bit 17_185 +bit 17_186 +bit 17_187 +bit 17_188 +bit 17_189 +bit 17_19 +bit 17_190 +bit 17_191 +bit 17_192 +bit 17_193 +bit 17_194 +bit 17_195 +bit 17_196 +bit 17_197 +bit 17_198 +bit 17_199 +bit 17_20 +bit 17_200 +bit 17_201 +bit 17_202 +bit 17_203 +bit 17_204 +bit 17_205 +bit 17_206 +bit 17_207 +bit 17_208 +bit 17_209 +bit 17_21 +bit 17_210 +bit 17_211 +bit 17_212 +bit 17_213 +bit 17_214 +bit 17_215 +bit 17_216 +bit 17_217 +bit 17_218 +bit 17_219 +bit 17_22 +bit 17_220 +bit 17_221 +bit 17_222 +bit 17_223 +bit 17_224 +bit 17_225 +bit 17_226 +bit 17_227 +bit 17_228 +bit 17_229 +bit 17_23 +bit 17_230 +bit 17_231 +bit 17_232 +bit 17_233 +bit 17_234 +bit 17_235 +bit 17_236 +bit 17_237 +bit 17_238 +bit 17_239 +bit 17_24 +bit 17_240 +bit 17_241 +bit 17_242 +bit 17_243 +bit 17_244 +bit 17_245 +bit 17_246 +bit 17_247 +bit 17_248 +bit 17_249 +bit 17_25 +bit 17_250 +bit 17_251 +bit 17_252 +bit 17_253 +bit 17_254 +bit 17_255 +bit 17_256 +bit 17_257 +bit 17_258 +bit 17_259 +bit 17_26 +bit 17_260 +bit 17_261 +bit 17_262 +bit 17_263 +bit 17_264 +bit 17_265 +bit 17_266 +bit 17_267 +bit 17_268 +bit 17_269 +bit 17_27 +bit 17_270 +bit 17_271 +bit 17_272 +bit 17_273 +bit 17_274 +bit 17_275 +bit 17_276 +bit 17_277 +bit 17_278 +bit 17_279 +bit 17_28 +bit 17_280 +bit 17_281 +bit 17_282 +bit 17_283 +bit 17_284 +bit 17_285 +bit 17_286 +bit 17_287 +bit 17_288 +bit 17_289 +bit 17_29 +bit 17_290 +bit 17_291 +bit 17_292 +bit 17_293 +bit 17_294 +bit 17_295 +bit 17_296 +bit 17_297 +bit 17_298 +bit 17_299 +bit 17_30 +bit 17_300 +bit 17_301 +bit 17_302 +bit 17_303 +bit 17_304 +bit 17_305 +bit 17_306 +bit 17_307 +bit 17_308 +bit 17_309 +bit 17_31 +bit 17_310 +bit 17_311 +bit 17_312 +bit 17_313 +bit 17_314 +bit 17_315 +bit 17_316 +bit 17_317 +bit 17_318 +bit 17_319 +bit 17_32 +bit 17_33 +bit 17_34 +bit 17_35 +bit 17_36 +bit 17_37 +bit 17_38 +bit 17_39 +bit 17_40 +bit 17_41 +bit 17_42 +bit 17_43 +bit 17_44 +bit 17_45 +bit 17_46 +bit 17_47 +bit 17_48 +bit 17_49 +bit 17_50 +bit 17_51 +bit 17_52 +bit 17_53 +bit 17_54 +bit 17_55 +bit 17_56 +bit 17_57 +bit 17_58 +bit 17_59 +bit 17_60 +bit 17_61 +bit 17_62 +bit 17_63 +bit 17_64 +bit 17_65 +bit 17_66 +bit 17_67 +bit 17_68 +bit 17_69 +bit 17_70 +bit 17_71 +bit 17_72 +bit 17_73 +bit 17_74 +bit 17_75 +bit 17_76 +bit 17_77 +bit 17_78 +bit 17_79 +bit 17_80 +bit 17_81 +bit 17_82 +bit 17_83 +bit 17_84 +bit 17_85 +bit 17_86 +bit 17_87 +bit 17_88 +bit 17_89 +bit 17_90 +bit 17_91 +bit 17_92 +bit 17_93 +bit 17_94 +bit 17_95 +bit 17_96 +bit 17_97 +bit 17_98 +bit 17_99 +bit 18_00 +bit 18_01 +bit 18_02 +bit 18_03 +bit 18_04 +bit 18_05 +bit 18_06 +bit 18_07 +bit 18_08 +bit 18_09 +bit 18_10 +bit 18_100 +bit 18_101 +bit 18_102 +bit 18_103 +bit 18_104 +bit 18_105 +bit 18_106 +bit 18_107 +bit 18_108 +bit 18_109 +bit 18_11 +bit 18_110 +bit 18_111 +bit 18_112 +bit 18_113 +bit 18_114 +bit 18_115 +bit 18_116 +bit 18_117 +bit 18_118 +bit 18_119 +bit 18_12 +bit 18_120 +bit 18_121 +bit 18_122 +bit 18_123 +bit 18_124 +bit 18_125 +bit 18_126 +bit 18_127 +bit 18_128 +bit 18_129 +bit 18_13 +bit 18_130 +bit 18_131 +bit 18_132 +bit 18_133 +bit 18_134 +bit 18_135 +bit 18_136 +bit 18_137 +bit 18_138 +bit 18_139 +bit 18_14 +bit 18_140 +bit 18_141 +bit 18_142 +bit 18_143 +bit 18_144 +bit 18_145 +bit 18_146 +bit 18_147 +bit 18_148 +bit 18_149 +bit 18_15 +bit 18_150 +bit 18_151 +bit 18_152 +bit 18_153 +bit 18_154 +bit 18_155 +bit 18_156 +bit 18_157 +bit 18_158 +bit 18_159 +bit 18_16 +bit 18_160 +bit 18_161 +bit 18_162 +bit 18_163 +bit 18_164 +bit 18_165 +bit 18_166 +bit 18_167 +bit 18_168 +bit 18_169 +bit 18_17 +bit 18_170 +bit 18_171 +bit 18_172 +bit 18_173 +bit 18_174 +bit 18_175 +bit 18_176 +bit 18_177 +bit 18_178 +bit 18_179 +bit 18_18 +bit 18_180 +bit 18_181 +bit 18_182 +bit 18_183 +bit 18_184 +bit 18_185 +bit 18_186 +bit 18_187 +bit 18_188 +bit 18_189 +bit 18_19 +bit 18_190 +bit 18_191 +bit 18_192 +bit 18_193 +bit 18_194 +bit 18_195 +bit 18_196 +bit 18_197 +bit 18_198 +bit 18_199 +bit 18_20 +bit 18_200 +bit 18_201 +bit 18_202 +bit 18_203 +bit 18_204 +bit 18_205 +bit 18_206 +bit 18_207 +bit 18_208 +bit 18_209 +bit 18_21 +bit 18_210 +bit 18_211 +bit 18_212 +bit 18_213 +bit 18_214 +bit 18_215 +bit 18_216 +bit 18_217 +bit 18_218 +bit 18_219 +bit 18_22 +bit 18_220 +bit 18_221 +bit 18_222 +bit 18_223 +bit 18_224 +bit 18_225 +bit 18_226 +bit 18_227 +bit 18_228 +bit 18_229 +bit 18_23 +bit 18_230 +bit 18_231 +bit 18_232 +bit 18_233 +bit 18_234 +bit 18_235 +bit 18_236 +bit 18_237 +bit 18_238 +bit 18_239 +bit 18_24 +bit 18_240 +bit 18_241 +bit 18_242 +bit 18_243 +bit 18_244 +bit 18_245 +bit 18_246 +bit 18_247 +bit 18_248 +bit 18_249 +bit 18_25 +bit 18_250 +bit 18_251 +bit 18_252 +bit 18_253 +bit 18_254 +bit 18_255 +bit 18_256 +bit 18_257 +bit 18_258 +bit 18_259 +bit 18_26 +bit 18_260 +bit 18_261 +bit 18_262 +bit 18_263 +bit 18_264 +bit 18_265 +bit 18_266 +bit 18_267 +bit 18_268 +bit 18_269 +bit 18_27 +bit 18_270 +bit 18_271 +bit 18_272 +bit 18_273 +bit 18_274 +bit 18_275 +bit 18_276 +bit 18_277 +bit 18_278 +bit 18_279 +bit 18_28 +bit 18_280 +bit 18_281 +bit 18_282 +bit 18_283 +bit 18_284 +bit 18_285 +bit 18_286 +bit 18_287 +bit 18_288 +bit 18_289 +bit 18_29 +bit 18_290 +bit 18_291 +bit 18_292 +bit 18_293 +bit 18_294 +bit 18_295 +bit 18_296 +bit 18_297 +bit 18_298 +bit 18_299 +bit 18_30 +bit 18_300 +bit 18_301 +bit 18_302 +bit 18_303 +bit 18_304 +bit 18_305 +bit 18_306 +bit 18_307 +bit 18_308 +bit 18_309 +bit 18_31 +bit 18_310 +bit 18_311 +bit 18_312 +bit 18_313 +bit 18_314 +bit 18_315 +bit 18_316 +bit 18_317 +bit 18_318 +bit 18_319 +bit 18_32 +bit 18_33 +bit 18_34 +bit 18_35 +bit 18_36 +bit 18_37 +bit 18_38 +bit 18_39 +bit 18_40 +bit 18_41 +bit 18_42 +bit 18_43 +bit 18_44 +bit 18_45 +bit 18_46 +bit 18_47 +bit 18_48 +bit 18_49 +bit 18_50 +bit 18_51 +bit 18_52 +bit 18_53 +bit 18_54 +bit 18_55 +bit 18_56 +bit 18_57 +bit 18_58 +bit 18_59 +bit 18_60 +bit 18_61 +bit 18_62 +bit 18_63 +bit 18_64 +bit 18_65 +bit 18_66 +bit 18_67 +bit 18_68 +bit 18_69 +bit 18_70 +bit 18_71 +bit 18_72 +bit 18_73 +bit 18_74 +bit 18_75 +bit 18_76 +bit 18_77 +bit 18_78 +bit 18_79 +bit 18_80 +bit 18_81 +bit 18_82 +bit 18_83 +bit 18_84 +bit 18_85 +bit 18_86 +bit 18_87 +bit 18_88 +bit 18_89 +bit 18_90 +bit 18_91 +bit 18_92 +bit 18_93 +bit 18_94 +bit 18_95 +bit 18_96 +bit 18_97 +bit 18_98 +bit 18_99 +bit 19_00 +bit 19_01 +bit 19_02 +bit 19_03 +bit 19_04 +bit 19_05 +bit 19_06 +bit 19_07 +bit 19_08 +bit 19_09 +bit 19_10 +bit 19_100 +bit 19_101 +bit 19_102 +bit 19_103 +bit 19_104 +bit 19_105 +bit 19_106 +bit 19_107 +bit 19_108 +bit 19_109 +bit 19_11 +bit 19_110 +bit 19_111 +bit 19_112 +bit 19_113 +bit 19_114 +bit 19_115 +bit 19_116 +bit 19_117 +bit 19_118 +bit 19_119 +bit 19_12 +bit 19_120 +bit 19_121 +bit 19_122 +bit 19_123 +bit 19_124 +bit 19_125 +bit 19_126 +bit 19_127 +bit 19_128 +bit 19_129 +bit 19_13 +bit 19_130 +bit 19_131 +bit 19_132 +bit 19_133 +bit 19_134 +bit 19_135 +bit 19_136 +bit 19_137 +bit 19_138 +bit 19_139 +bit 19_14 +bit 19_140 +bit 19_141 +bit 19_142 +bit 19_143 +bit 19_144 +bit 19_145 +bit 19_146 +bit 19_147 +bit 19_148 +bit 19_149 +bit 19_15 +bit 19_150 +bit 19_151 +bit 19_152 +bit 19_153 +bit 19_154 +bit 19_155 +bit 19_156 +bit 19_157 +bit 19_158 +bit 19_159 +bit 19_16 +bit 19_160 +bit 19_161 +bit 19_162 +bit 19_163 +bit 19_164 +bit 19_165 +bit 19_166 +bit 19_167 +bit 19_168 +bit 19_169 +bit 19_17 +bit 19_170 +bit 19_171 +bit 19_172 +bit 19_173 +bit 19_174 +bit 19_175 +bit 19_176 +bit 19_177 +bit 19_178 +bit 19_179 +bit 19_18 +bit 19_180 +bit 19_181 +bit 19_182 +bit 19_183 +bit 19_184 +bit 19_185 +bit 19_186 +bit 19_187 +bit 19_188 +bit 19_189 +bit 19_19 +bit 19_190 +bit 19_191 +bit 19_192 +bit 19_193 +bit 19_194 +bit 19_195 +bit 19_196 +bit 19_197 +bit 19_198 +bit 19_199 +bit 19_20 +bit 19_200 +bit 19_201 +bit 19_202 +bit 19_203 +bit 19_204 +bit 19_205 +bit 19_206 +bit 19_207 +bit 19_208 +bit 19_209 +bit 19_21 +bit 19_210 +bit 19_211 +bit 19_212 +bit 19_213 +bit 19_214 +bit 19_215 +bit 19_216 +bit 19_217 +bit 19_218 +bit 19_219 +bit 19_22 +bit 19_220 +bit 19_221 +bit 19_222 +bit 19_223 +bit 19_224 +bit 19_225 +bit 19_226 +bit 19_227 +bit 19_228 +bit 19_229 +bit 19_23 +bit 19_230 +bit 19_231 +bit 19_232 +bit 19_233 +bit 19_234 +bit 19_235 +bit 19_236 +bit 19_237 +bit 19_238 +bit 19_239 +bit 19_24 +bit 19_240 +bit 19_241 +bit 19_242 +bit 19_243 +bit 19_244 +bit 19_245 +bit 19_246 +bit 19_247 +bit 19_248 +bit 19_249 +bit 19_25 +bit 19_250 +bit 19_251 +bit 19_252 +bit 19_253 +bit 19_254 +bit 19_255 +bit 19_256 +bit 19_257 +bit 19_258 +bit 19_259 +bit 19_26 +bit 19_260 +bit 19_261 +bit 19_262 +bit 19_263 +bit 19_264 +bit 19_265 +bit 19_266 +bit 19_267 +bit 19_268 +bit 19_269 +bit 19_27 +bit 19_270 +bit 19_271 +bit 19_272 +bit 19_273 +bit 19_274 +bit 19_275 +bit 19_276 +bit 19_277 +bit 19_278 +bit 19_279 +bit 19_28 +bit 19_280 +bit 19_281 +bit 19_282 +bit 19_283 +bit 19_284 +bit 19_285 +bit 19_286 +bit 19_287 +bit 19_288 +bit 19_289 +bit 19_29 +bit 19_290 +bit 19_291 +bit 19_292 +bit 19_293 +bit 19_294 +bit 19_295 +bit 19_296 +bit 19_297 +bit 19_298 +bit 19_299 +bit 19_30 +bit 19_300 +bit 19_301 +bit 19_302 +bit 19_303 +bit 19_304 +bit 19_305 +bit 19_306 +bit 19_307 +bit 19_308 +bit 19_309 +bit 19_31 +bit 19_310 +bit 19_311 +bit 19_312 +bit 19_313 +bit 19_314 +bit 19_315 +bit 19_316 +bit 19_317 +bit 19_318 +bit 19_319 +bit 19_32 +bit 19_33 +bit 19_34 +bit 19_35 +bit 19_36 +bit 19_37 +bit 19_38 +bit 19_39 +bit 19_40 +bit 19_41 +bit 19_42 +bit 19_43 +bit 19_44 +bit 19_45 +bit 19_46 +bit 19_47 +bit 19_48 +bit 19_49 +bit 19_50 +bit 19_51 +bit 19_52 +bit 19_53 +bit 19_54 +bit 19_55 +bit 19_56 +bit 19_57 +bit 19_58 +bit 19_59 +bit 19_60 +bit 19_61 +bit 19_62 +bit 19_63 +bit 19_64 +bit 19_65 +bit 19_66 +bit 19_67 +bit 19_68 +bit 19_69 +bit 19_70 +bit 19_71 +bit 19_72 +bit 19_73 +bit 19_74 +bit 19_75 +bit 19_76 +bit 19_77 +bit 19_78 +bit 19_79 +bit 19_80 +bit 19_81 +bit 19_82 +bit 19_83 +bit 19_84 +bit 19_85 +bit 19_86 +bit 19_87 +bit 19_88 +bit 19_89 +bit 19_90 +bit 19_91 +bit 19_92 +bit 19_93 +bit 19_94 +bit 19_95 +bit 19_96 +bit 19_97 +bit 19_98 +bit 19_99 +bit 20_00 +bit 20_01 +bit 20_02 +bit 20_03 +bit 20_04 +bit 20_05 +bit 20_06 +bit 20_07 +bit 20_08 +bit 20_09 +bit 20_10 +bit 20_100 +bit 20_101 +bit 20_102 +bit 20_103 +bit 20_104 +bit 20_105 +bit 20_106 +bit 20_107 +bit 20_108 +bit 20_109 +bit 20_11 +bit 20_110 +bit 20_111 +bit 20_112 +bit 20_113 +bit 20_114 +bit 20_115 +bit 20_116 +bit 20_117 +bit 20_118 +bit 20_119 +bit 20_12 +bit 20_120 +bit 20_121 +bit 20_122 +bit 20_123 +bit 20_124 +bit 20_125 +bit 20_126 +bit 20_127 +bit 20_128 +bit 20_129 +bit 20_13 +bit 20_130 +bit 20_131 +bit 20_132 +bit 20_133 +bit 20_134 +bit 20_135 +bit 20_136 +bit 20_137 +bit 20_138 +bit 20_139 +bit 20_14 +bit 20_140 +bit 20_141 +bit 20_142 +bit 20_143 +bit 20_144 +bit 20_145 +bit 20_146 +bit 20_147 +bit 20_148 +bit 20_149 +bit 20_15 +bit 20_150 +bit 20_151 +bit 20_152 +bit 20_153 +bit 20_154 +bit 20_155 +bit 20_156 +bit 20_157 +bit 20_158 +bit 20_159 +bit 20_16 +bit 20_160 +bit 20_161 +bit 20_162 +bit 20_163 +bit 20_164 +bit 20_165 +bit 20_166 +bit 20_167 +bit 20_168 +bit 20_169 +bit 20_17 +bit 20_170 +bit 20_171 +bit 20_172 +bit 20_173 +bit 20_174 +bit 20_175 +bit 20_176 +bit 20_177 +bit 20_178 +bit 20_179 +bit 20_18 +bit 20_180 +bit 20_181 +bit 20_182 +bit 20_183 +bit 20_184 +bit 20_185 +bit 20_186 +bit 20_187 +bit 20_188 +bit 20_189 +bit 20_19 +bit 20_190 +bit 20_191 +bit 20_192 +bit 20_193 +bit 20_194 +bit 20_195 +bit 20_196 +bit 20_197 +bit 20_198 +bit 20_199 +bit 20_20 +bit 20_200 +bit 20_201 +bit 20_202 +bit 20_203 +bit 20_204 +bit 20_205 +bit 20_206 +bit 20_207 +bit 20_208 +bit 20_209 +bit 20_21 +bit 20_210 +bit 20_211 +bit 20_212 +bit 20_213 +bit 20_214 +bit 20_215 +bit 20_216 +bit 20_217 +bit 20_218 +bit 20_219 +bit 20_22 +bit 20_220 +bit 20_221 +bit 20_222 +bit 20_223 +bit 20_224 +bit 20_225 +bit 20_226 +bit 20_227 +bit 20_228 +bit 20_229 +bit 20_23 +bit 20_230 +bit 20_231 +bit 20_232 +bit 20_233 +bit 20_234 +bit 20_235 +bit 20_236 +bit 20_237 +bit 20_238 +bit 20_239 +bit 20_24 +bit 20_240 +bit 20_241 +bit 20_242 +bit 20_243 +bit 20_244 +bit 20_245 +bit 20_246 +bit 20_247 +bit 20_248 +bit 20_249 +bit 20_25 +bit 20_250 +bit 20_251 +bit 20_252 +bit 20_253 +bit 20_254 +bit 20_255 +bit 20_256 +bit 20_257 +bit 20_258 +bit 20_259 +bit 20_26 +bit 20_260 +bit 20_261 +bit 20_262 +bit 20_263 +bit 20_264 +bit 20_265 +bit 20_266 +bit 20_267 +bit 20_268 +bit 20_269 +bit 20_27 +bit 20_270 +bit 20_271 +bit 20_272 +bit 20_273 +bit 20_274 +bit 20_275 +bit 20_276 +bit 20_277 +bit 20_278 +bit 20_279 +bit 20_28 +bit 20_280 +bit 20_281 +bit 20_282 +bit 20_283 +bit 20_284 +bit 20_285 +bit 20_286 +bit 20_287 +bit 20_288 +bit 20_289 +bit 20_29 +bit 20_290 +bit 20_291 +bit 20_292 +bit 20_293 +bit 20_294 +bit 20_295 +bit 20_296 +bit 20_297 +bit 20_298 +bit 20_299 +bit 20_30 +bit 20_300 +bit 20_301 +bit 20_302 +bit 20_303 +bit 20_304 +bit 20_305 +bit 20_306 +bit 20_307 +bit 20_308 +bit 20_309 +bit 20_31 +bit 20_310 +bit 20_311 +bit 20_312 +bit 20_313 +bit 20_314 +bit 20_315 +bit 20_316 +bit 20_317 +bit 20_318 +bit 20_319 +bit 20_32 +bit 20_33 +bit 20_34 +bit 20_35 +bit 20_36 +bit 20_37 +bit 20_38 +bit 20_39 +bit 20_40 +bit 20_41 +bit 20_42 +bit 20_43 +bit 20_44 +bit 20_45 +bit 20_46 +bit 20_47 +bit 20_48 +bit 20_49 +bit 20_50 +bit 20_51 +bit 20_52 +bit 20_53 +bit 20_54 +bit 20_55 +bit 20_56 +bit 20_57 +bit 20_58 +bit 20_59 +bit 20_60 +bit 20_61 +bit 20_62 +bit 20_63 +bit 20_64 +bit 20_65 +bit 20_66 +bit 20_67 +bit 20_68 +bit 20_69 +bit 20_70 +bit 20_71 +bit 20_72 +bit 20_73 +bit 20_74 +bit 20_75 +bit 20_76 +bit 20_77 +bit 20_78 +bit 20_79 +bit 20_80 +bit 20_81 +bit 20_82 +bit 20_83 +bit 20_84 +bit 20_85 +bit 20_86 +bit 20_87 +bit 20_88 +bit 20_89 +bit 20_90 +bit 20_91 +bit 20_92 +bit 20_93 +bit 20_94 +bit 20_95 +bit 20_96 +bit 20_97 +bit 20_98 +bit 20_99 +bit 21_00 +bit 21_01 +bit 21_02 +bit 21_03 +bit 21_04 +bit 21_05 +bit 21_06 +bit 21_07 +bit 21_08 +bit 21_09 +bit 21_10 +bit 21_100 +bit 21_101 +bit 21_102 +bit 21_103 +bit 21_104 +bit 21_105 +bit 21_106 +bit 21_107 +bit 21_108 +bit 21_109 +bit 21_11 +bit 21_110 +bit 21_111 +bit 21_112 +bit 21_113 +bit 21_114 +bit 21_115 +bit 21_116 +bit 21_117 +bit 21_118 +bit 21_119 +bit 21_12 +bit 21_120 +bit 21_121 +bit 21_122 +bit 21_123 +bit 21_124 +bit 21_125 +bit 21_126 +bit 21_127 +bit 21_128 +bit 21_129 +bit 21_13 +bit 21_130 +bit 21_131 +bit 21_132 +bit 21_133 +bit 21_134 +bit 21_135 +bit 21_136 +bit 21_137 +bit 21_138 +bit 21_139 +bit 21_14 +bit 21_140 +bit 21_141 +bit 21_142 +bit 21_143 +bit 21_144 +bit 21_145 +bit 21_146 +bit 21_147 +bit 21_148 +bit 21_149 +bit 21_15 +bit 21_150 +bit 21_151 +bit 21_152 +bit 21_153 +bit 21_154 +bit 21_155 +bit 21_156 +bit 21_157 +bit 21_158 +bit 21_159 +bit 21_16 +bit 21_160 +bit 21_161 +bit 21_162 +bit 21_163 +bit 21_164 +bit 21_165 +bit 21_166 +bit 21_167 +bit 21_168 +bit 21_169 +bit 21_17 +bit 21_170 +bit 21_171 +bit 21_172 +bit 21_173 +bit 21_174 +bit 21_175 +bit 21_176 +bit 21_177 +bit 21_178 +bit 21_179 +bit 21_18 +bit 21_180 +bit 21_181 +bit 21_182 +bit 21_183 +bit 21_184 +bit 21_185 +bit 21_186 +bit 21_187 +bit 21_188 +bit 21_189 +bit 21_19 +bit 21_190 +bit 21_191 +bit 21_192 +bit 21_193 +bit 21_194 +bit 21_195 +bit 21_196 +bit 21_197 +bit 21_198 +bit 21_199 +bit 21_20 +bit 21_200 +bit 21_201 +bit 21_202 +bit 21_203 +bit 21_204 +bit 21_205 +bit 21_206 +bit 21_207 +bit 21_208 +bit 21_209 +bit 21_21 +bit 21_210 +bit 21_211 +bit 21_212 +bit 21_213 +bit 21_214 +bit 21_215 +bit 21_216 +bit 21_217 +bit 21_218 +bit 21_219 +bit 21_22 +bit 21_220 +bit 21_221 +bit 21_222 +bit 21_223 +bit 21_224 +bit 21_225 +bit 21_226 +bit 21_227 +bit 21_228 +bit 21_229 +bit 21_23 +bit 21_230 +bit 21_231 +bit 21_232 +bit 21_233 +bit 21_234 +bit 21_235 +bit 21_236 +bit 21_237 +bit 21_238 +bit 21_239 +bit 21_24 +bit 21_240 +bit 21_241 +bit 21_242 +bit 21_243 +bit 21_244 +bit 21_245 +bit 21_246 +bit 21_247 +bit 21_248 +bit 21_249 +bit 21_25 +bit 21_250 +bit 21_251 +bit 21_252 +bit 21_253 +bit 21_254 +bit 21_255 +bit 21_256 +bit 21_257 +bit 21_258 +bit 21_259 +bit 21_26 +bit 21_260 +bit 21_261 +bit 21_262 +bit 21_263 +bit 21_264 +bit 21_265 +bit 21_266 +bit 21_267 +bit 21_268 +bit 21_269 +bit 21_27 +bit 21_270 +bit 21_271 +bit 21_272 +bit 21_273 +bit 21_274 +bit 21_275 +bit 21_276 +bit 21_277 +bit 21_278 +bit 21_279 +bit 21_28 +bit 21_280 +bit 21_281 +bit 21_282 +bit 21_283 +bit 21_284 +bit 21_285 +bit 21_286 +bit 21_287 +bit 21_288 +bit 21_289 +bit 21_29 +bit 21_290 +bit 21_291 +bit 21_292 +bit 21_293 +bit 21_294 +bit 21_295 +bit 21_296 +bit 21_297 +bit 21_298 +bit 21_299 +bit 21_30 +bit 21_300 +bit 21_301 +bit 21_302 +bit 21_303 +bit 21_304 +bit 21_305 +bit 21_306 +bit 21_307 +bit 21_308 +bit 21_309 +bit 21_31 +bit 21_310 +bit 21_311 +bit 21_312 +bit 21_313 +bit 21_314 +bit 21_315 +bit 21_316 +bit 21_317 +bit 21_318 +bit 21_319 +bit 21_32 +bit 21_33 +bit 21_34 +bit 21_35 +bit 21_36 +bit 21_37 +bit 21_38 +bit 21_39 +bit 21_40 +bit 21_41 +bit 21_42 +bit 21_43 +bit 21_44 +bit 21_45 +bit 21_46 +bit 21_47 +bit 21_48 +bit 21_49 +bit 21_50 +bit 21_51 +bit 21_52 +bit 21_53 +bit 21_54 +bit 21_55 +bit 21_56 +bit 21_57 +bit 21_58 +bit 21_59 +bit 21_60 +bit 21_61 +bit 21_62 +bit 21_63 +bit 21_64 +bit 21_65 +bit 21_66 +bit 21_67 +bit 21_68 +bit 21_69 +bit 21_70 +bit 21_71 +bit 21_72 +bit 21_73 +bit 21_74 +bit 21_75 +bit 21_76 +bit 21_77 +bit 21_78 +bit 21_79 +bit 21_80 +bit 21_81 +bit 21_82 +bit 21_83 +bit 21_84 +bit 21_85 +bit 21_86 +bit 21_87 +bit 21_88 +bit 21_89 +bit 21_90 +bit 21_91 +bit 21_92 +bit 21_93 +bit 21_94 +bit 21_95 +bit 21_96 +bit 21_97 +bit 21_98 +bit 21_99 +bit 22_00 +bit 22_01 +bit 22_02 +bit 22_03 +bit 22_04 +bit 22_05 +bit 22_06 +bit 22_07 +bit 22_08 +bit 22_09 +bit 22_10 +bit 22_100 +bit 22_101 +bit 22_102 +bit 22_103 +bit 22_104 +bit 22_105 +bit 22_106 +bit 22_107 +bit 22_108 +bit 22_109 +bit 22_11 +bit 22_110 +bit 22_111 +bit 22_112 +bit 22_113 +bit 22_114 +bit 22_115 +bit 22_116 +bit 22_117 +bit 22_118 +bit 22_119 +bit 22_12 +bit 22_120 +bit 22_121 +bit 22_122 +bit 22_123 +bit 22_124 +bit 22_125 +bit 22_126 +bit 22_127 +bit 22_128 +bit 22_129 +bit 22_13 +bit 22_130 +bit 22_131 +bit 22_132 +bit 22_133 +bit 22_134 +bit 22_135 +bit 22_136 +bit 22_137 +bit 22_138 +bit 22_139 +bit 22_14 +bit 22_140 +bit 22_141 +bit 22_142 +bit 22_143 +bit 22_144 +bit 22_145 +bit 22_146 +bit 22_147 +bit 22_148 +bit 22_149 +bit 22_15 +bit 22_150 +bit 22_151 +bit 22_152 +bit 22_153 +bit 22_154 +bit 22_155 +bit 22_156 +bit 22_157 +bit 22_158 +bit 22_159 +bit 22_16 +bit 22_160 +bit 22_161 +bit 22_162 +bit 22_163 +bit 22_164 +bit 22_165 +bit 22_166 +bit 22_167 +bit 22_168 +bit 22_169 +bit 22_17 +bit 22_170 +bit 22_171 +bit 22_172 +bit 22_173 +bit 22_174 +bit 22_175 +bit 22_176 +bit 22_177 +bit 22_178 +bit 22_179 +bit 22_18 +bit 22_180 +bit 22_181 +bit 22_182 +bit 22_183 +bit 22_184 +bit 22_185 +bit 22_186 +bit 22_187 +bit 22_188 +bit 22_189 +bit 22_19 +bit 22_190 +bit 22_191 +bit 22_192 +bit 22_193 +bit 22_194 +bit 22_195 +bit 22_196 +bit 22_197 +bit 22_198 +bit 22_199 +bit 22_20 +bit 22_200 +bit 22_201 +bit 22_202 +bit 22_203 +bit 22_204 +bit 22_205 +bit 22_206 +bit 22_207 +bit 22_208 +bit 22_209 +bit 22_21 +bit 22_210 +bit 22_211 +bit 22_212 +bit 22_213 +bit 22_214 +bit 22_215 +bit 22_216 +bit 22_217 +bit 22_218 +bit 22_219 +bit 22_22 +bit 22_220 +bit 22_221 +bit 22_222 +bit 22_223 +bit 22_224 +bit 22_225 +bit 22_226 +bit 22_227 +bit 22_228 +bit 22_229 +bit 22_23 +bit 22_230 +bit 22_231 +bit 22_232 +bit 22_233 +bit 22_234 +bit 22_235 +bit 22_236 +bit 22_237 +bit 22_238 +bit 22_239 +bit 22_24 +bit 22_240 +bit 22_241 +bit 22_242 +bit 22_243 +bit 22_244 +bit 22_245 +bit 22_246 +bit 22_247 +bit 22_248 +bit 22_249 +bit 22_25 +bit 22_250 +bit 22_251 +bit 22_252 +bit 22_253 +bit 22_254 +bit 22_255 +bit 22_256 +bit 22_257 +bit 22_258 +bit 22_259 +bit 22_26 +bit 22_260 +bit 22_261 +bit 22_262 +bit 22_263 +bit 22_264 +bit 22_265 +bit 22_266 +bit 22_267 +bit 22_268 +bit 22_269 +bit 22_27 +bit 22_270 +bit 22_271 +bit 22_272 +bit 22_273 +bit 22_274 +bit 22_275 +bit 22_276 +bit 22_277 +bit 22_278 +bit 22_279 +bit 22_28 +bit 22_280 +bit 22_281 +bit 22_282 +bit 22_283 +bit 22_284 +bit 22_285 +bit 22_286 +bit 22_287 +bit 22_288 +bit 22_289 +bit 22_29 +bit 22_290 +bit 22_291 +bit 22_292 +bit 22_293 +bit 22_294 +bit 22_295 +bit 22_296 +bit 22_297 +bit 22_298 +bit 22_299 +bit 22_30 +bit 22_300 +bit 22_301 +bit 22_302 +bit 22_303 +bit 22_304 +bit 22_305 +bit 22_306 +bit 22_307 +bit 22_308 +bit 22_309 +bit 22_31 +bit 22_310 +bit 22_311 +bit 22_312 +bit 22_313 +bit 22_314 +bit 22_315 +bit 22_316 +bit 22_317 +bit 22_318 +bit 22_319 +bit 22_32 +bit 22_33 +bit 22_34 +bit 22_35 +bit 22_36 +bit 22_37 +bit 22_38 +bit 22_39 +bit 22_40 +bit 22_41 +bit 22_42 +bit 22_43 +bit 22_44 +bit 22_45 +bit 22_46 +bit 22_47 +bit 22_48 +bit 22_49 +bit 22_50 +bit 22_51 +bit 22_52 +bit 22_53 +bit 22_54 +bit 22_55 +bit 22_56 +bit 22_57 +bit 22_58 +bit 22_59 +bit 22_60 +bit 22_61 +bit 22_62 +bit 22_63 +bit 22_64 +bit 22_65 +bit 22_66 +bit 22_67 +bit 22_68 +bit 22_69 +bit 22_70 +bit 22_71 +bit 22_72 +bit 22_73 +bit 22_74 +bit 22_75 +bit 22_76 +bit 22_77 +bit 22_78 +bit 22_79 +bit 22_80 +bit 22_81 +bit 22_82 +bit 22_83 +bit 22_84 +bit 22_85 +bit 22_86 +bit 22_87 +bit 22_88 +bit 22_89 +bit 22_90 +bit 22_91 +bit 22_92 +bit 22_93 +bit 22_94 +bit 22_95 +bit 22_96 +bit 22_97 +bit 22_98 +bit 22_99 +bit 23_00 +bit 23_01 +bit 23_02 +bit 23_03 +bit 23_04 +bit 23_05 +bit 23_06 +bit 23_07 +bit 23_08 +bit 23_09 +bit 23_10 +bit 23_100 +bit 23_101 +bit 23_102 +bit 23_103 +bit 23_104 +bit 23_105 +bit 23_106 +bit 23_107 +bit 23_108 +bit 23_109 +bit 23_11 +bit 23_110 +bit 23_111 +bit 23_112 +bit 23_113 +bit 23_114 +bit 23_115 +bit 23_116 +bit 23_117 +bit 23_118 +bit 23_119 +bit 23_12 +bit 23_120 +bit 23_121 +bit 23_122 +bit 23_123 +bit 23_124 +bit 23_125 +bit 23_126 +bit 23_127 +bit 23_128 +bit 23_129 +bit 23_13 +bit 23_130 +bit 23_131 +bit 23_132 +bit 23_133 +bit 23_134 +bit 23_135 +bit 23_136 +bit 23_137 +bit 23_138 +bit 23_139 +bit 23_14 +bit 23_140 +bit 23_141 +bit 23_142 +bit 23_143 +bit 23_144 +bit 23_145 +bit 23_146 +bit 23_147 +bit 23_148 +bit 23_149 +bit 23_15 +bit 23_150 +bit 23_151 +bit 23_152 +bit 23_153 +bit 23_154 +bit 23_155 +bit 23_156 +bit 23_157 +bit 23_158 +bit 23_159 +bit 23_16 +bit 23_160 +bit 23_161 +bit 23_162 +bit 23_163 +bit 23_164 +bit 23_165 +bit 23_166 +bit 23_167 +bit 23_168 +bit 23_169 +bit 23_17 +bit 23_170 +bit 23_171 +bit 23_172 +bit 23_173 +bit 23_174 +bit 23_175 +bit 23_176 +bit 23_177 +bit 23_178 +bit 23_179 +bit 23_18 +bit 23_180 +bit 23_181 +bit 23_182 +bit 23_183 +bit 23_184 +bit 23_185 +bit 23_186 +bit 23_187 +bit 23_188 +bit 23_189 +bit 23_19 +bit 23_190 +bit 23_191 +bit 23_192 +bit 23_193 +bit 23_194 +bit 23_195 +bit 23_196 +bit 23_197 +bit 23_198 +bit 23_199 +bit 23_20 +bit 23_200 +bit 23_201 +bit 23_202 +bit 23_203 +bit 23_204 +bit 23_205 +bit 23_206 +bit 23_207 +bit 23_208 +bit 23_209 +bit 23_21 +bit 23_210 +bit 23_211 +bit 23_212 +bit 23_213 +bit 23_214 +bit 23_215 +bit 23_216 +bit 23_217 +bit 23_218 +bit 23_219 +bit 23_22 +bit 23_220 +bit 23_221 +bit 23_222 +bit 23_223 +bit 23_224 +bit 23_225 +bit 23_226 +bit 23_227 +bit 23_228 +bit 23_229 +bit 23_23 +bit 23_230 +bit 23_231 +bit 23_232 +bit 23_233 +bit 23_234 +bit 23_235 +bit 23_236 +bit 23_237 +bit 23_238 +bit 23_239 +bit 23_24 +bit 23_240 +bit 23_241 +bit 23_242 +bit 23_243 +bit 23_244 +bit 23_245 +bit 23_246 +bit 23_247 +bit 23_248 +bit 23_249 +bit 23_25 +bit 23_250 +bit 23_251 +bit 23_252 +bit 23_253 +bit 23_254 +bit 23_255 +bit 23_256 +bit 23_257 +bit 23_258 +bit 23_259 +bit 23_26 +bit 23_260 +bit 23_261 +bit 23_262 +bit 23_263 +bit 23_264 +bit 23_265 +bit 23_266 +bit 23_267 +bit 23_268 +bit 23_269 +bit 23_27 +bit 23_270 +bit 23_271 +bit 23_272 +bit 23_273 +bit 23_274 +bit 23_275 +bit 23_276 +bit 23_277 +bit 23_278 +bit 23_279 +bit 23_28 +bit 23_280 +bit 23_281 +bit 23_282 +bit 23_283 +bit 23_284 +bit 23_285 +bit 23_286 +bit 23_287 +bit 23_288 +bit 23_289 +bit 23_29 +bit 23_290 +bit 23_291 +bit 23_292 +bit 23_293 +bit 23_294 +bit 23_295 +bit 23_296 +bit 23_297 +bit 23_298 +bit 23_299 +bit 23_30 +bit 23_300 +bit 23_301 +bit 23_302 +bit 23_303 +bit 23_304 +bit 23_305 +bit 23_306 +bit 23_307 +bit 23_308 +bit 23_309 +bit 23_31 +bit 23_310 +bit 23_311 +bit 23_312 +bit 23_313 +bit 23_314 +bit 23_315 +bit 23_316 +bit 23_317 +bit 23_318 +bit 23_319 +bit 23_32 +bit 23_33 +bit 23_34 +bit 23_35 +bit 23_36 +bit 23_37 +bit 23_38 +bit 23_39 +bit 23_40 +bit 23_41 +bit 23_42 +bit 23_43 +bit 23_44 +bit 23_45 +bit 23_46 +bit 23_47 +bit 23_48 +bit 23_49 +bit 23_50 +bit 23_51 +bit 23_52 +bit 23_53 +bit 23_54 +bit 23_55 +bit 23_56 +bit 23_57 +bit 23_58 +bit 23_59 +bit 23_60 +bit 23_61 +bit 23_62 +bit 23_63 +bit 23_64 +bit 23_65 +bit 23_66 +bit 23_67 +bit 23_68 +bit 23_69 +bit 23_70 +bit 23_71 +bit 23_72 +bit 23_73 +bit 23_74 +bit 23_75 +bit 23_76 +bit 23_77 +bit 23_78 +bit 23_79 +bit 23_80 +bit 23_81 +bit 23_82 +bit 23_83 +bit 23_84 +bit 23_85 +bit 23_86 +bit 23_87 +bit 23_88 +bit 23_89 +bit 23_90 +bit 23_91 +bit 23_92 +bit 23_93 +bit 23_94 +bit 23_95 +bit 23_96 +bit 23_97 +bit 23_98 +bit 23_99 +bit 24_00 +bit 24_01 +bit 24_02 +bit 24_03 +bit 24_04 +bit 24_05 +bit 24_06 +bit 24_07 +bit 24_08 +bit 24_09 +bit 24_10 +bit 24_100 +bit 24_101 +bit 24_102 +bit 24_103 +bit 24_104 +bit 24_105 +bit 24_106 +bit 24_107 +bit 24_108 +bit 24_109 +bit 24_11 +bit 24_110 +bit 24_111 +bit 24_112 +bit 24_113 +bit 24_114 +bit 24_115 +bit 24_116 +bit 24_117 +bit 24_118 +bit 24_119 +bit 24_12 +bit 24_120 +bit 24_121 +bit 24_122 +bit 24_123 +bit 24_124 +bit 24_125 +bit 24_126 +bit 24_127 +bit 24_128 +bit 24_129 +bit 24_13 +bit 24_130 +bit 24_131 +bit 24_132 +bit 24_133 +bit 24_134 +bit 24_135 +bit 24_136 +bit 24_137 +bit 24_138 +bit 24_139 +bit 24_14 +bit 24_140 +bit 24_141 +bit 24_142 +bit 24_143 +bit 24_144 +bit 24_145 +bit 24_146 +bit 24_147 +bit 24_148 +bit 24_149 +bit 24_15 +bit 24_150 +bit 24_151 +bit 24_152 +bit 24_153 +bit 24_154 +bit 24_155 +bit 24_156 +bit 24_157 +bit 24_158 +bit 24_159 +bit 24_16 +bit 24_160 +bit 24_161 +bit 24_162 +bit 24_163 +bit 24_164 +bit 24_165 +bit 24_166 +bit 24_167 +bit 24_168 +bit 24_169 +bit 24_17 +bit 24_170 +bit 24_171 +bit 24_172 +bit 24_173 +bit 24_174 +bit 24_175 +bit 24_176 +bit 24_177 +bit 24_178 +bit 24_179 +bit 24_18 +bit 24_180 +bit 24_181 +bit 24_182 +bit 24_183 +bit 24_184 +bit 24_185 +bit 24_186 +bit 24_187 +bit 24_188 +bit 24_189 +bit 24_19 +bit 24_190 +bit 24_191 +bit 24_192 +bit 24_193 +bit 24_194 +bit 24_195 +bit 24_196 +bit 24_197 +bit 24_198 +bit 24_199 +bit 24_20 +bit 24_200 +bit 24_201 +bit 24_202 +bit 24_203 +bit 24_204 +bit 24_205 +bit 24_206 +bit 24_207 +bit 24_208 +bit 24_209 +bit 24_21 +bit 24_210 +bit 24_211 +bit 24_212 +bit 24_213 +bit 24_214 +bit 24_215 +bit 24_216 +bit 24_217 +bit 24_218 +bit 24_219 +bit 24_22 +bit 24_220 +bit 24_221 +bit 24_222 +bit 24_223 +bit 24_224 +bit 24_225 +bit 24_226 +bit 24_227 +bit 24_228 +bit 24_229 +bit 24_23 +bit 24_230 +bit 24_231 +bit 24_232 +bit 24_233 +bit 24_234 +bit 24_235 +bit 24_236 +bit 24_237 +bit 24_238 +bit 24_239 +bit 24_24 +bit 24_240 +bit 24_241 +bit 24_242 +bit 24_243 +bit 24_244 +bit 24_245 +bit 24_246 +bit 24_247 +bit 24_248 +bit 24_249 +bit 24_25 +bit 24_250 +bit 24_251 +bit 24_252 +bit 24_253 +bit 24_254 +bit 24_255 +bit 24_256 +bit 24_257 +bit 24_258 +bit 24_259 +bit 24_26 +bit 24_260 +bit 24_261 +bit 24_262 +bit 24_263 +bit 24_264 +bit 24_265 +bit 24_266 +bit 24_267 +bit 24_268 +bit 24_269 +bit 24_27 +bit 24_270 +bit 24_271 +bit 24_272 +bit 24_273 +bit 24_274 +bit 24_275 +bit 24_276 +bit 24_277 +bit 24_278 +bit 24_279 +bit 24_28 +bit 24_280 +bit 24_281 +bit 24_282 +bit 24_283 +bit 24_284 +bit 24_285 +bit 24_286 +bit 24_287 +bit 24_288 +bit 24_289 +bit 24_29 +bit 24_290 +bit 24_291 +bit 24_292 +bit 24_293 +bit 24_294 +bit 24_295 +bit 24_296 +bit 24_297 +bit 24_298 +bit 24_299 +bit 24_30 +bit 24_300 +bit 24_301 +bit 24_302 +bit 24_303 +bit 24_304 +bit 24_305 +bit 24_306 +bit 24_307 +bit 24_308 +bit 24_309 +bit 24_31 +bit 24_310 +bit 24_311 +bit 24_312 +bit 24_313 +bit 24_314 +bit 24_315 +bit 24_316 +bit 24_317 +bit 24_318 +bit 24_319 +bit 24_32 +bit 24_33 +bit 24_34 +bit 24_35 +bit 24_36 +bit 24_37 +bit 24_38 +bit 24_39 +bit 24_40 +bit 24_41 +bit 24_42 +bit 24_43 +bit 24_44 +bit 24_45 +bit 24_46 +bit 24_47 +bit 24_48 +bit 24_49 +bit 24_50 +bit 24_51 +bit 24_52 +bit 24_53 +bit 24_54 +bit 24_55 +bit 24_56 +bit 24_57 +bit 24_58 +bit 24_59 +bit 24_60 +bit 24_61 +bit 24_62 +bit 24_63 +bit 24_64 +bit 24_65 +bit 24_66 +bit 24_67 +bit 24_68 +bit 24_69 +bit 24_70 +bit 24_71 +bit 24_72 +bit 24_73 +bit 24_74 +bit 24_75 +bit 24_76 +bit 24_77 +bit 24_78 +bit 24_79 +bit 24_80 +bit 24_81 +bit 24_82 +bit 24_83 +bit 24_84 +bit 24_85 +bit 24_86 +bit 24_87 +bit 24_88 +bit 24_89 +bit 24_90 +bit 24_91 +bit 24_92 +bit 24_93 +bit 24_94 +bit 24_95 +bit 24_96 +bit 24_97 +bit 24_98 +bit 24_99 +bit 25_00 +bit 25_01 +bit 25_02 +bit 25_03 +bit 25_04 +bit 25_05 +bit 25_06 +bit 25_07 +bit 25_08 +bit 25_09 +bit 25_10 +bit 25_100 +bit 25_101 +bit 25_102 +bit 25_103 +bit 25_104 +bit 25_105 +bit 25_106 +bit 25_107 +bit 25_108 +bit 25_109 +bit 25_11 +bit 25_110 +bit 25_111 +bit 25_112 +bit 25_113 +bit 25_114 +bit 25_115 +bit 25_116 +bit 25_117 +bit 25_118 +bit 25_119 +bit 25_12 +bit 25_120 +bit 25_121 +bit 25_122 +bit 25_123 +bit 25_124 +bit 25_125 +bit 25_126 +bit 25_127 +bit 25_128 +bit 25_129 +bit 25_13 +bit 25_130 +bit 25_131 +bit 25_132 +bit 25_133 +bit 25_134 +bit 25_135 +bit 25_136 +bit 25_137 +bit 25_138 +bit 25_139 +bit 25_14 +bit 25_140 +bit 25_141 +bit 25_142 +bit 25_143 +bit 25_144 +bit 25_145 +bit 25_146 +bit 25_147 +bit 25_148 +bit 25_149 +bit 25_15 +bit 25_150 +bit 25_151 +bit 25_152 +bit 25_153 +bit 25_154 +bit 25_155 +bit 25_156 +bit 25_157 +bit 25_158 +bit 25_159 +bit 25_16 +bit 25_160 +bit 25_161 +bit 25_162 +bit 25_163 +bit 25_164 +bit 25_165 +bit 25_166 +bit 25_167 +bit 25_168 +bit 25_169 +bit 25_17 +bit 25_170 +bit 25_171 +bit 25_172 +bit 25_173 +bit 25_174 +bit 25_175 +bit 25_176 +bit 25_177 +bit 25_178 +bit 25_179 +bit 25_18 +bit 25_180 +bit 25_181 +bit 25_182 +bit 25_183 +bit 25_184 +bit 25_185 +bit 25_186 +bit 25_187 +bit 25_188 +bit 25_189 +bit 25_19 +bit 25_190 +bit 25_191 +bit 25_192 +bit 25_193 +bit 25_194 +bit 25_195 +bit 25_196 +bit 25_197 +bit 25_198 +bit 25_199 +bit 25_20 +bit 25_200 +bit 25_201 +bit 25_202 +bit 25_203 +bit 25_204 +bit 25_205 +bit 25_206 +bit 25_207 +bit 25_208 +bit 25_209 +bit 25_21 +bit 25_210 +bit 25_211 +bit 25_212 +bit 25_213 +bit 25_214 +bit 25_215 +bit 25_216 +bit 25_217 +bit 25_218 +bit 25_219 +bit 25_22 +bit 25_220 +bit 25_221 +bit 25_222 +bit 25_223 +bit 25_224 +bit 25_225 +bit 25_226 +bit 25_227 +bit 25_228 +bit 25_229 +bit 25_23 +bit 25_230 +bit 25_231 +bit 25_232 +bit 25_233 +bit 25_234 +bit 25_235 +bit 25_236 +bit 25_237 +bit 25_238 +bit 25_239 +bit 25_24 +bit 25_240 +bit 25_241 +bit 25_242 +bit 25_243 +bit 25_244 +bit 25_245 +bit 25_246 +bit 25_247 +bit 25_248 +bit 25_249 +bit 25_25 +bit 25_250 +bit 25_251 +bit 25_252 +bit 25_253 +bit 25_254 +bit 25_255 +bit 25_256 +bit 25_257 +bit 25_258 +bit 25_259 +bit 25_26 +bit 25_260 +bit 25_261 +bit 25_262 +bit 25_263 +bit 25_264 +bit 25_265 +bit 25_266 +bit 25_267 +bit 25_268 +bit 25_269 +bit 25_27 +bit 25_270 +bit 25_271 +bit 25_272 +bit 25_273 +bit 25_274 +bit 25_275 +bit 25_276 +bit 25_277 +bit 25_278 +bit 25_279 +bit 25_28 +bit 25_280 +bit 25_281 +bit 25_282 +bit 25_283 +bit 25_284 +bit 25_285 +bit 25_286 +bit 25_287 +bit 25_288 +bit 25_289 +bit 25_29 +bit 25_290 +bit 25_291 +bit 25_292 +bit 25_293 +bit 25_294 +bit 25_295 +bit 25_296 +bit 25_297 +bit 25_298 +bit 25_299 +bit 25_30 +bit 25_300 +bit 25_301 +bit 25_302 +bit 25_303 +bit 25_304 +bit 25_305 +bit 25_306 +bit 25_307 +bit 25_308 +bit 25_309 +bit 25_31 +bit 25_310 +bit 25_311 +bit 25_312 +bit 25_313 +bit 25_314 +bit 25_315 +bit 25_316 +bit 25_317 +bit 25_318 +bit 25_319 +bit 25_32 +bit 25_33 +bit 25_34 +bit 25_35 +bit 25_36 +bit 25_37 +bit 25_38 +bit 25_39 +bit 25_40 +bit 25_41 +bit 25_42 +bit 25_43 +bit 25_44 +bit 25_45 +bit 25_46 +bit 25_47 +bit 25_48 +bit 25_49 +bit 25_50 +bit 25_51 +bit 25_52 +bit 25_53 +bit 25_54 +bit 25_55 +bit 25_56 +bit 25_57 +bit 25_58 +bit 25_59 +bit 25_60 +bit 25_61 +bit 25_62 +bit 25_63 +bit 25_64 +bit 25_65 +bit 25_66 +bit 25_67 +bit 25_68 +bit 25_69 +bit 25_70 +bit 25_71 +bit 25_72 +bit 25_73 +bit 25_74 +bit 25_75 +bit 25_76 +bit 25_77 +bit 25_78 +bit 25_79 +bit 25_80 +bit 25_81 +bit 25_82 +bit 25_83 +bit 25_84 +bit 25_85 +bit 25_86 +bit 25_87 +bit 25_88 +bit 25_89 +bit 25_90 +bit 25_91 +bit 25_92 +bit 25_93 +bit 25_94 +bit 25_95 +bit 25_96 +bit 25_97 +bit 25_98 +bit 25_99 +bit 27_01 +bit 27_02 +bit 27_06 +bit 27_07 +bit 27_09 +bit 27_10 +bit 27_102 +bit 27_103 +bit 27_105 +bit 27_106 +bit 27_107 +bit 27_109 +bit 27_110 +bit 27_111 +bit 27_112 +bit 27_113 +bit 27_114 +bit 27_115 +bit 27_116 +bit 27_117 +bit 27_118 +bit 27_119 +bit 27_120 +bit 27_121 +bit 27_122 +bit 27_123 +bit 27_126 +bit 27_127 +bit 27_129 +bit 27_130 +bit 27_134 +bit 27_135 +bit 27_137 +bit 27_138 +bit 27_14 +bit 27_142 +bit 27_143 +bit 27_15 +bit 27_17 +bit 27_177 +bit 27_178 +bit 27_18 +bit 27_182 +bit 27_183 +bit 27_185 +bit 27_186 +bit 27_190 +bit 27_191 +bit 27_193 +bit 27_194 +bit 27_197 +bit 27_198 +bit 27_199 +bit 27_200 +bit 27_201 +bit 27_202 +bit 27_203 +bit 27_204 +bit 27_205 +bit 27_206 +bit 27_207 +bit 27_208 +bit 27_209 +bit 27_210 +bit 27_211 +bit 27_213 +bit 27_214 +bit 27_215 +bit 27_217 +bit 27_218 +bit 27_22 +bit 27_222 +bit 27_223 +bit 27_225 +bit 27_226 +bit 27_23 +bit 27_230 +bit 27_231 +bit 27_233 +bit 27_234 +bit 27_238 +bit 27_239 +bit 27_241 +bit 27_242 +bit 27_246 +bit 27_247 +bit 27_249 +bit 27_25 +bit 27_250 +bit 27_252 +bit 27_253 +bit 27_254 +bit 27_255 +bit 27_256 +bit 27_257 +bit 27_258 +bit 27_259 +bit 27_26 +bit 27_260 +bit 27_261 +bit 27_262 +bit 27_263 +bit 27_264 +bit 27_265 +bit 27_266 +bit 27_267 +bit 27_268 +bit 27_269 +bit 27_270 +bit 27_271 +bit 27_273 +bit 27_274 +bit 27_275 +bit 27_276 +bit 27_277 +bit 27_278 +bit 27_279 +bit 27_281 +bit 27_282 +bit 27_283 +bit 27_284 +bit 27_285 +bit 27_286 +bit 27_287 +bit 27_289 +bit 27_290 +bit 27_294 +bit 27_295 +bit 27_297 +bit 27_298 +bit 27_30 +bit 27_302 +bit 27_303 +bit 27_305 +bit 27_306 +bit 27_31 +bit 27_310 +bit 27_311 +bit 27_313 +bit 27_314 +bit 27_318 +bit 27_319 +bit 27_33 +bit 27_34 +bit 27_35 +bit 27_36 +bit 27_37 +bit 27_38 +bit 27_39 +bit 27_41 +bit 27_42 +bit 27_43 +bit 27_44 +bit 27_45 +bit 27_46 +bit 27_47 +bit 27_49 +bit 27_50 +bit 27_51 +bit 27_52 +bit 27_53 +bit 27_54 +bit 27_55 +bit 27_56 +bit 27_57 +bit 27_58 +bit 27_59 +bit 27_60 +bit 27_61 +bit 27_62 +bit 27_63 +bit 27_64 +bit 27_65 +bit 27_66 +bit 27_67 +bit 27_68 +bit 27_70 +bit 27_71 +bit 27_73 +bit 27_74 +bit 27_78 +bit 27_79 +bit 27_81 +bit 27_82 +bit 27_86 +bit 27_87 +bit 27_89 +bit 27_90 +bit 27_94 +bit 27_95 +bit 27_97 +bit 27_98 +bit 30_02 +bit 30_101 +bit 30_124 +bit 30_130 +bit 30_153 +bit 30_165 +bit 30_188 +bit 30_194 +bit 30_217 +bit 30_229 +bit 30_25 +bit 30_252 +bit 30_258 +bit 30_281 +bit 30_293 +bit 30_316 +bit 30_37 +bit 30_60 +bit 30_66 +bit 30_89 +bit 31_02 +bit 31_101 +bit 31_126 +bit 31_130 +bit 31_154 +bit 31_165 +bit 31_190 +bit 31_194 +bit 31_218 +bit 31_229 +bit 31_254 +bit 31_258 +bit 31_26 +bit 31_282 +bit 31_293 +bit 31_318 +bit 31_37 +bit 31_62 +bit 31_66 +bit 31_90 diff --git a/kintex7/mask_clbll_l.db b/kintex7/mask_clbll_l.db index a5498cc..1426eb6 100644 --- a/kintex7/mask_clbll_l.db +++ b/kintex7/mask_clbll_l.db @@ -1,6 +1,8 @@ +bit 00_00 bit 00_01 bit 00_02 bit 00_03 +bit 00_04 bit 00_05 bit 00_06 bit 00_07 @@ -16,12 +18,15 @@ bit 00_16 bit 00_17 bit 00_18 bit 00_19 +bit 00_20 bit 00_21 bit 00_22 bit 00_23 +bit 00_24 bit 00_25 bit 00_26 bit 00_27 +bit 00_28 bit 00_29 bit 00_30 bit 00_32 @@ -32,6 +37,7 @@ bit 00_36 bit 00_37 bit 00_38 bit 00_39 +bit 00_40 bit 00_41 bit 00_42 bit 00_43 @@ -42,12 +48,18 @@ bit 00_47 bit 00_48 bit 00_49 bit 00_50 +bit 00_51 bit 00_52 bit 00_53 +bit 00_54 bit 00_55 bit 00_56 +bit 00_57 +bit 00_58 +bit 00_59 bit 00_61 bit 00_62 +bit 00_63 bit 01_00 bit 01_01 bit 01_02 @@ -71,9 +83,11 @@ bit 01_19 bit 01_20 bit 01_21 bit 01_22 +bit 01_23 bit 01_24 bit 01_25 bit 01_26 +bit 01_27 bit 01_28 bit 01_29 bit 01_31 @@ -88,6 +102,7 @@ bit 01_39 bit 01_40 bit 01_41 bit 01_42 +bit 01_43 bit 01_44 bit 01_45 bit 01_46 @@ -98,7 +113,14 @@ bit 01_50 bit 01_51 bit 01_52 bit 01_53 +bit 01_54 bit 01_55 +bit 01_56 +bit 01_57 +bit 01_58 +bit 01_59 +bit 01_60 +bit 01_61 bit 01_62 bit 02_01 bit 02_02 @@ -1876,6 +1898,8 @@ bit 30_12 bit 30_13 bit 30_14 bit 30_15 +bit 30_16 +bit 30_17 bit 30_18 bit 30_19 bit 30_20 @@ -1903,6 +1927,8 @@ bit 30_42 bit 30_43 bit 30_44 bit 30_45 +bit 30_46 +bit 30_47 bit 30_48 bit 30_49 bit 30_50 @@ -1934,6 +1960,8 @@ bit 31_12 bit 31_13 bit 31_14 bit 31_15 +bit 31_16 +bit 31_17 bit 31_18 bit 31_19 bit 31_20 @@ -1961,6 +1989,8 @@ bit 31_42 bit 31_43 bit 31_44 bit 31_45 +bit 31_46 +bit 31_47 bit 31_48 bit 31_49 bit 31_50 diff --git a/kintex7/mask_clbll_r.db b/kintex7/mask_clbll_r.db index cabaf0b..1426eb6 100644 --- a/kintex7/mask_clbll_r.db +++ b/kintex7/mask_clbll_r.db @@ -1,4 +1,13 @@ +bit 00_00 +bit 00_01 +bit 00_02 +bit 00_03 +bit 00_04 +bit 00_05 +bit 00_06 +bit 00_07 bit 00_08 +bit 00_09 bit 00_10 bit 00_11 bit 00_12 @@ -9,12 +18,15 @@ bit 00_16 bit 00_17 bit 00_18 bit 00_19 +bit 00_20 bit 00_21 bit 00_22 bit 00_23 +bit 00_24 bit 00_25 bit 00_26 bit 00_27 +bit 00_28 bit 00_29 bit 00_30 bit 00_32 @@ -25,14 +37,38 @@ bit 00_36 bit 00_37 bit 00_38 bit 00_39 +bit 00_40 bit 00_41 bit 00_42 +bit 00_43 bit 00_44 +bit 00_45 +bit 00_46 +bit 00_47 bit 00_48 +bit 00_49 +bit 00_50 +bit 00_51 bit 00_52 +bit 00_53 +bit 00_54 +bit 00_55 bit 00_56 +bit 00_57 +bit 00_58 +bit 00_59 +bit 00_61 +bit 00_62 +bit 00_63 +bit 01_00 +bit 01_01 +bit 01_02 bit 01_03 +bit 01_04 +bit 01_05 +bit 01_06 bit 01_07 +bit 01_08 bit 01_09 bit 01_10 bit 01_11 @@ -47,9 +83,11 @@ bit 01_19 bit 01_20 bit 01_21 bit 01_22 +bit 01_23 bit 01_24 bit 01_25 bit 01_26 +bit 01_27 bit 01_28 bit 01_29 bit 01_31 @@ -63,9 +101,27 @@ bit 01_38 bit 01_39 bit 01_40 bit 01_41 +bit 01_42 +bit 01_43 +bit 01_44 +bit 01_45 +bit 01_46 bit 01_47 +bit 01_48 +bit 01_49 +bit 01_50 bit 01_51 +bit 01_52 +bit 01_53 +bit 01_54 bit 01_55 +bit 01_56 +bit 01_57 +bit 01_58 +bit 01_59 +bit 01_60 +bit 01_61 +bit 01_62 bit 02_01 bit 02_02 bit 02_03 @@ -1826,47 +1882,130 @@ bit 29_60 bit 29_61 bit 29_62 bit 29_63 +bit 30_00 +bit 30_01 +bit 30_02 +bit 30_03 +bit 30_04 +bit 30_05 +bit 30_06 +bit 30_07 +bit 30_08 +bit 30_09 +bit 30_10 +bit 30_11 bit 30_12 bit 30_13 bit 30_14 bit 30_15 +bit 30_16 +bit 30_17 +bit 30_18 +bit 30_19 +bit 30_20 +bit 30_21 +bit 30_22 +bit 30_23 +bit 30_24 +bit 30_25 +bit 30_26 +bit 30_27 +bit 30_28 +bit 30_29 bit 30_30 bit 30_32 bit 30_33 bit 30_34 +bit 30_35 +bit 30_36 +bit 30_37 +bit 30_38 +bit 30_39 +bit 30_40 +bit 30_41 +bit 30_42 +bit 30_43 +bit 30_44 bit 30_45 +bit 30_46 +bit 30_47 bit 30_48 bit 30_49 bit 30_50 +bit 30_51 +bit 30_52 +bit 30_53 +bit 30_54 +bit 30_55 bit 30_56 +bit 30_57 +bit 30_58 +bit 30_59 +bit 30_60 +bit 30_61 +bit 30_62 +bit 31_00 +bit 31_01 +bit 31_02 bit 31_03 bit 31_04 bit 31_05 bit 31_06 +bit 31_07 +bit 31_08 bit 31_09 +bit 31_10 +bit 31_11 bit 31_12 bit 31_13 bit 31_14 bit 31_15 +bit 31_16 +bit 31_17 +bit 31_18 +bit 31_19 +bit 31_20 +bit 31_21 bit 31_22 bit 31_23 +bit 31_24 +bit 31_25 +bit 31_26 +bit 31_27 bit 31_28 bit 31_29 bit 31_30 bit 31_32 bit 31_33 bit 31_34 +bit 31_35 +bit 31_36 +bit 31_37 +bit 31_38 +bit 31_39 +bit 31_40 bit 31_41 bit 31_42 bit 31_43 +bit 31_44 +bit 31_45 +bit 31_46 +bit 31_47 bit 31_48 bit 31_49 bit 31_50 bit 31_51 bit 31_52 +bit 31_53 +bit 31_54 +bit 31_55 bit 31_56 +bit 31_57 bit 31_58 bit 31_59 +bit 31_60 +bit 31_61 +bit 31_62 bit 32_00 bit 32_01 bit 32_02 diff --git a/kintex7/mask_clblm_l.db b/kintex7/mask_clblm_l.db index 22a37a2..1426eb6 100644 --- a/kintex7/mask_clblm_l.db +++ b/kintex7/mask_clblm_l.db @@ -37,6 +37,7 @@ bit 00_36 bit 00_37 bit 00_38 bit 00_39 +bit 00_40 bit 00_41 bit 00_42 bit 00_43 @@ -45,12 +46,20 @@ bit 00_45 bit 00_46 bit 00_47 bit 00_48 +bit 00_49 bit 00_50 bit 00_51 bit 00_52 bit 00_53 +bit 00_54 +bit 00_55 bit 00_56 +bit 00_57 +bit 00_58 +bit 00_59 +bit 00_61 bit 00_62 +bit 00_63 bit 01_00 bit 01_01 bit 01_02 @@ -78,6 +87,7 @@ bit 01_23 bit 01_24 bit 01_25 bit 01_26 +bit 01_27 bit 01_28 bit 01_29 bit 01_31 @@ -103,8 +113,14 @@ bit 01_50 bit 01_51 bit 01_52 bit 01_53 +bit 01_54 bit 01_55 +bit 01_56 +bit 01_57 +bit 01_58 bit 01_59 +bit 01_60 +bit 01_61 bit 01_62 bit 02_01 bit 02_02 @@ -1882,6 +1898,8 @@ bit 30_12 bit 30_13 bit 30_14 bit 30_15 +bit 30_16 +bit 30_17 bit 30_18 bit 30_19 bit 30_20 @@ -1909,6 +1927,8 @@ bit 30_42 bit 30_43 bit 30_44 bit 30_45 +bit 30_46 +bit 30_47 bit 30_48 bit 30_49 bit 30_50 diff --git a/kintex7/mask_clblm_r.db b/kintex7/mask_clblm_r.db index 11cd78c..1426eb6 100644 --- a/kintex7/mask_clblm_r.db +++ b/kintex7/mask_clblm_r.db @@ -37,6 +37,7 @@ bit 00_36 bit 00_37 bit 00_38 bit 00_39 +bit 00_40 bit 00_41 bit 00_42 bit 00_43 @@ -45,11 +46,20 @@ bit 00_45 bit 00_46 bit 00_47 bit 00_48 +bit 00_49 bit 00_50 +bit 00_51 bit 00_52 bit 00_53 bit 00_54 +bit 00_55 bit 00_56 +bit 00_57 +bit 00_58 +bit 00_59 +bit 00_61 +bit 00_62 +bit 00_63 bit 01_00 bit 01_01 bit 01_02 @@ -77,6 +87,7 @@ bit 01_23 bit 01_24 bit 01_25 bit 01_26 +bit 01_27 bit 01_28 bit 01_29 bit 01_31 @@ -102,8 +113,15 @@ bit 01_50 bit 01_51 bit 01_52 bit 01_53 +bit 01_54 bit 01_55 +bit 01_56 +bit 01_57 +bit 01_58 bit 01_59 +bit 01_60 +bit 01_61 +bit 01_62 bit 02_01 bit 02_02 bit 02_03 @@ -1880,6 +1898,8 @@ bit 30_12 bit 30_13 bit 30_14 bit 30_15 +bit 30_16 +bit 30_17 bit 30_18 bit 30_19 bit 30_20 @@ -1907,6 +1927,8 @@ bit 30_42 bit 30_43 bit 30_44 bit 30_45 +bit 30_46 +bit 30_47 bit 30_48 bit 30_49 bit 30_50 diff --git a/kintex7/mask_dsp_l.db b/kintex7/mask_dsp_l.db new file mode 100644 index 0000000..0913b8d --- /dev/null +++ b/kintex7/mask_dsp_l.db @@ -0,0 +1,8030 @@ +bit 00_01 +bit 00_02 +bit 00_03 +bit 00_05 +bit 00_06 +bit 00_07 +bit 00_09 +bit 00_10 +bit 00_101 +bit 00_102 +bit 00_103 +bit 00_105 +bit 00_106 +bit 00_107 +bit 00_109 +bit 00_11 +bit 00_110 +bit 00_111 +bit 00_113 +bit 00_114 +bit 00_115 +bit 00_117 +bit 00_118 +bit 00_119 +bit 00_121 +bit 00_122 +bit 00_123 +bit 00_125 +bit 00_126 +bit 00_127 +bit 00_129 +bit 00_13 +bit 00_130 +bit 00_131 +bit 00_133 +bit 00_134 +bit 00_135 +bit 00_137 +bit 00_138 +bit 00_139 +bit 00_14 +bit 00_141 +bit 00_142 +bit 00_143 +bit 00_145 +bit 00_146 +bit 00_147 +bit 00_149 +bit 00_15 +bit 00_150 +bit 00_151 +bit 00_153 +bit 00_154 +bit 00_155 +bit 00_157 +bit 00_158 +bit 00_161 +bit 00_162 +bit 00_163 +bit 00_165 +bit 00_166 +bit 00_167 +bit 00_169 +bit 00_17 +bit 00_170 +bit 00_171 +bit 00_173 +bit 00_174 +bit 00_175 +bit 00_177 +bit 00_178 +bit 00_179 +bit 00_18 +bit 00_181 +bit 00_182 +bit 00_183 +bit 00_185 +bit 00_186 +bit 00_187 +bit 00_189 +bit 00_19 +bit 00_190 +bit 00_191 +bit 00_193 +bit 00_194 +bit 00_195 +bit 00_197 +bit 00_198 +bit 00_199 +bit 00_201 +bit 00_202 +bit 00_203 +bit 00_205 +bit 00_206 +bit 00_207 +bit 00_209 +bit 00_21 +bit 00_210 +bit 00_211 +bit 00_213 +bit 00_214 +bit 00_215 +bit 00_217 +bit 00_218 +bit 00_219 +bit 00_22 +bit 00_221 +bit 00_222 +bit 00_225 +bit 00_226 +bit 00_227 +bit 00_229 +bit 00_23 +bit 00_230 +bit 00_231 +bit 00_233 +bit 00_234 +bit 00_235 +bit 00_237 +bit 00_238 +bit 00_239 +bit 00_241 +bit 00_242 +bit 00_243 +bit 00_245 +bit 00_246 +bit 00_247 +bit 00_249 +bit 00_25 +bit 00_250 +bit 00_251 +bit 00_253 +bit 00_254 +bit 00_255 +bit 00_257 +bit 00_258 +bit 00_259 +bit 00_26 +bit 00_261 +bit 00_262 +bit 00_263 +bit 00_265 +bit 00_266 +bit 00_267 +bit 00_269 +bit 00_27 +bit 00_270 +bit 00_271 +bit 00_273 +bit 00_274 +bit 00_275 +bit 00_277 +bit 00_278 +bit 00_279 +bit 00_281 +bit 00_282 +bit 00_283 +bit 00_285 +bit 00_286 +bit 00_289 +bit 00_29 +bit 00_290 +bit 00_291 +bit 00_293 +bit 00_294 +bit 00_295 +bit 00_297 +bit 00_298 +bit 00_299 +bit 00_30 +bit 00_301 +bit 00_302 +bit 00_303 +bit 00_305 +bit 00_306 +bit 00_307 +bit 00_309 +bit 00_310 +bit 00_311 +bit 00_313 +bit 00_314 +bit 00_315 +bit 00_317 +bit 00_318 +bit 00_319 +bit 00_33 +bit 00_34 +bit 00_35 +bit 00_37 +bit 00_38 +bit 00_39 +bit 00_41 +bit 00_42 +bit 00_43 +bit 00_45 +bit 00_46 +bit 00_47 +bit 00_49 +bit 00_50 +bit 00_51 +bit 00_53 +bit 00_54 +bit 00_55 +bit 00_57 +bit 00_58 +bit 00_59 +bit 00_61 +bit 00_62 +bit 00_63 +bit 00_65 +bit 00_66 +bit 00_67 +bit 00_69 +bit 00_70 +bit 00_71 +bit 00_73 +bit 00_74 +bit 00_75 +bit 00_77 +bit 00_78 +bit 00_79 +bit 00_81 +bit 00_82 +bit 00_83 +bit 00_85 +bit 00_86 +bit 00_87 +bit 00_89 +bit 00_90 +bit 00_91 +bit 00_93 +bit 00_94 +bit 00_97 +bit 00_98 +bit 00_99 +bit 01_00 +bit 01_01 +bit 01_02 +bit 01_04 +bit 01_05 +bit 01_06 +bit 01_08 +bit 01_09 +bit 01_10 +bit 01_100 +bit 01_101 +bit 01_102 +bit 01_104 +bit 01_105 +bit 01_106 +bit 01_108 +bit 01_109 +bit 01_110 +bit 01_112 +bit 01_113 +bit 01_114 +bit 01_116 +bit 01_117 +bit 01_118 +bit 01_12 +bit 01_120 +bit 01_121 +bit 01_122 +bit 01_124 +bit 01_125 +bit 01_126 +bit 01_128 +bit 01_129 +bit 01_13 +bit 01_130 +bit 01_132 +bit 01_133 +bit 01_134 +bit 01_136 +bit 01_137 +bit 01_138 +bit 01_14 +bit 01_140 +bit 01_141 +bit 01_142 +bit 01_144 +bit 01_145 +bit 01_146 +bit 01_148 +bit 01_149 +bit 01_150 +bit 01_152 +bit 01_153 +bit 01_154 +bit 01_156 +bit 01_157 +bit 01_16 +bit 01_160 +bit 01_161 +bit 01_162 +bit 01_164 +bit 01_165 +bit 01_166 +bit 01_168 +bit 01_169 +bit 01_17 +bit 01_170 +bit 01_172 +bit 01_173 +bit 01_174 +bit 01_176 +bit 01_177 +bit 01_178 +bit 01_18 +bit 01_180 +bit 01_181 +bit 01_182 +bit 01_184 +bit 01_185 +bit 01_186 +bit 01_188 +bit 01_189 +bit 01_190 +bit 01_192 +bit 01_193 +bit 01_194 +bit 01_196 +bit 01_197 +bit 01_198 +bit 01_20 +bit 01_200 +bit 01_201 +bit 01_202 +bit 01_204 +bit 01_205 +bit 01_206 +bit 01_208 +bit 01_209 +bit 01_21 +bit 01_210 +bit 01_212 +bit 01_213 +bit 01_214 +bit 01_216 +bit 01_217 +bit 01_218 +bit 01_22 +bit 01_220 +bit 01_221 +bit 01_224 +bit 01_225 +bit 01_226 +bit 01_228 +bit 01_229 +bit 01_230 +bit 01_232 +bit 01_233 +bit 01_234 +bit 01_236 +bit 01_237 +bit 01_238 +bit 01_24 +bit 01_240 +bit 01_241 +bit 01_242 +bit 01_244 +bit 01_245 +bit 01_246 +bit 01_248 +bit 01_249 +bit 01_25 +bit 01_250 +bit 01_252 +bit 01_253 +bit 01_254 +bit 01_256 +bit 01_257 +bit 01_258 +bit 01_26 +bit 01_260 +bit 01_261 +bit 01_262 +bit 01_264 +bit 01_265 +bit 01_266 +bit 01_268 +bit 01_269 +bit 01_270 +bit 01_272 +bit 01_273 +bit 01_274 +bit 01_276 +bit 01_277 +bit 01_278 +bit 01_28 +bit 01_280 +bit 01_281 +bit 01_282 +bit 01_284 +bit 01_285 +bit 01_288 +bit 01_289 +bit 01_29 +bit 01_290 +bit 01_292 +bit 01_293 +bit 01_294 +bit 01_296 +bit 01_297 +bit 01_298 +bit 01_300 +bit 01_301 +bit 01_302 +bit 01_304 +bit 01_305 +bit 01_306 +bit 01_308 +bit 01_309 +bit 01_310 +bit 01_312 +bit 01_313 +bit 01_314 +bit 01_316 +bit 01_317 +bit 01_318 +bit 01_32 +bit 01_33 +bit 01_34 +bit 01_36 +bit 01_37 +bit 01_38 +bit 01_40 +bit 01_41 +bit 01_42 +bit 01_44 +bit 01_45 +bit 01_46 +bit 01_48 +bit 01_49 +bit 01_50 +bit 01_52 +bit 01_53 +bit 01_54 +bit 01_56 +bit 01_57 +bit 01_58 +bit 01_60 +bit 01_61 +bit 01_62 +bit 01_64 +bit 01_65 +bit 01_66 +bit 01_68 +bit 01_69 +bit 01_70 +bit 01_72 +bit 01_73 +bit 01_74 +bit 01_76 +bit 01_77 +bit 01_78 +bit 01_80 +bit 01_81 +bit 01_82 +bit 01_84 +bit 01_85 +bit 01_86 +bit 01_88 +bit 01_89 +bit 01_90 +bit 01_92 +bit 01_93 +bit 01_96 +bit 01_97 +bit 01_98 +bit 02_01 +bit 02_02 +bit 02_03 +bit 02_05 +bit 02_06 +bit 02_07 +bit 02_09 +bit 02_10 +bit 02_101 +bit 02_102 +bit 02_103 +bit 02_105 +bit 02_106 +bit 02_107 +bit 02_109 +bit 02_11 +bit 02_110 +bit 02_111 +bit 02_113 +bit 02_114 +bit 02_115 +bit 02_117 +bit 02_118 +bit 02_119 +bit 02_121 +bit 02_122 +bit 02_123 +bit 02_125 +bit 02_126 +bit 02_127 +bit 02_129 +bit 02_13 +bit 02_130 +bit 02_131 +bit 02_133 +bit 02_134 +bit 02_135 +bit 02_137 +bit 02_138 +bit 02_139 +bit 02_14 +bit 02_141 +bit 02_142 +bit 02_143 +bit 02_145 +bit 02_146 +bit 02_147 +bit 02_149 +bit 02_15 +bit 02_150 +bit 02_151 +bit 02_153 +bit 02_154 +bit 02_155 +bit 02_157 +bit 02_158 +bit 02_159 +bit 02_161 +bit 02_162 +bit 02_163 +bit 02_165 +bit 02_166 +bit 02_167 +bit 02_169 +bit 02_17 +bit 02_170 +bit 02_171 +bit 02_173 +bit 02_174 +bit 02_175 +bit 02_177 +bit 02_178 +bit 02_179 +bit 02_18 +bit 02_181 +bit 02_182 +bit 02_183 +bit 02_185 +bit 02_186 +bit 02_187 +bit 02_189 +bit 02_19 +bit 02_190 +bit 02_191 +bit 02_193 +bit 02_194 +bit 02_195 +bit 02_197 +bit 02_198 +bit 02_199 +bit 02_201 +bit 02_202 +bit 02_203 +bit 02_205 +bit 02_206 +bit 02_207 +bit 02_209 +bit 02_21 +bit 02_210 +bit 02_211 +bit 02_213 +bit 02_214 +bit 02_215 +bit 02_217 +bit 02_218 +bit 02_219 +bit 02_22 +bit 02_221 +bit 02_222 +bit 02_223 +bit 02_225 +bit 02_226 +bit 02_227 +bit 02_229 +bit 02_23 +bit 02_230 +bit 02_231 +bit 02_233 +bit 02_234 +bit 02_235 +bit 02_237 +bit 02_238 +bit 02_239 +bit 02_241 +bit 02_242 +bit 02_243 +bit 02_245 +bit 02_246 +bit 02_247 +bit 02_249 +bit 02_25 +bit 02_250 +bit 02_251 +bit 02_253 +bit 02_254 +bit 02_255 +bit 02_257 +bit 02_258 +bit 02_259 +bit 02_26 +bit 02_261 +bit 02_262 +bit 02_263 +bit 02_265 +bit 02_266 +bit 02_267 +bit 02_269 +bit 02_27 +bit 02_270 +bit 02_271 +bit 02_273 +bit 02_274 +bit 02_275 +bit 02_277 +bit 02_278 +bit 02_279 +bit 02_281 +bit 02_282 +bit 02_283 +bit 02_285 +bit 02_286 +bit 02_287 +bit 02_289 +bit 02_29 +bit 02_290 +bit 02_291 +bit 02_293 +bit 02_294 +bit 02_295 +bit 02_297 +bit 02_298 +bit 02_299 +bit 02_30 +bit 02_301 +bit 02_302 +bit 02_303 +bit 02_305 +bit 02_306 +bit 02_307 +bit 02_309 +bit 02_31 +bit 02_310 +bit 02_311 +bit 02_313 +bit 02_314 +bit 02_315 +bit 02_317 +bit 02_318 +bit 02_319 +bit 02_33 +bit 02_34 +bit 02_35 +bit 02_37 +bit 02_38 +bit 02_39 +bit 02_41 +bit 02_42 +bit 02_43 +bit 02_45 +bit 02_46 +bit 02_47 +bit 02_49 +bit 02_50 +bit 02_51 +bit 02_53 +bit 02_54 +bit 02_55 +bit 02_57 +bit 02_58 +bit 02_59 +bit 02_61 +bit 02_62 +bit 02_63 +bit 02_65 +bit 02_66 +bit 02_67 +bit 02_69 +bit 02_70 +bit 02_71 +bit 02_73 +bit 02_74 +bit 02_75 +bit 02_77 +bit 02_78 +bit 02_79 +bit 02_81 +bit 02_82 +bit 02_83 +bit 02_85 +bit 02_86 +bit 02_87 +bit 02_89 +bit 02_90 +bit 02_91 +bit 02_93 +bit 02_94 +bit 02_95 +bit 02_97 +bit 02_98 +bit 02_99 +bit 03_00 +bit 03_01 +bit 03_02 +bit 03_04 +bit 03_05 +bit 03_06 +bit 03_08 +bit 03_09 +bit 03_10 +bit 03_100 +bit 03_101 +bit 03_102 +bit 03_104 +bit 03_105 +bit 03_106 +bit 03_108 +bit 03_109 +bit 03_110 +bit 03_112 +bit 03_113 +bit 03_114 +bit 03_116 +bit 03_117 +bit 03_118 +bit 03_12 +bit 03_120 +bit 03_121 +bit 03_122 +bit 03_124 +bit 03_125 +bit 03_126 +bit 03_128 +bit 03_129 +bit 03_13 +bit 03_130 +bit 03_132 +bit 03_133 +bit 03_134 +bit 03_136 +bit 03_137 +bit 03_138 +bit 03_14 +bit 03_140 +bit 03_141 +bit 03_142 +bit 03_144 +bit 03_145 +bit 03_146 +bit 03_148 +bit 03_149 +bit 03_150 +bit 03_152 +bit 03_153 +bit 03_154 +bit 03_156 +bit 03_157 +bit 03_158 +bit 03_16 +bit 03_160 +bit 03_161 +bit 03_162 +bit 03_164 +bit 03_165 +bit 03_166 +bit 03_168 +bit 03_169 +bit 03_17 +bit 03_170 +bit 03_172 +bit 03_173 +bit 03_174 +bit 03_176 +bit 03_177 +bit 03_178 +bit 03_18 +bit 03_180 +bit 03_181 +bit 03_182 +bit 03_184 +bit 03_185 +bit 03_186 +bit 03_188 +bit 03_189 +bit 03_190 +bit 03_192 +bit 03_193 +bit 03_194 +bit 03_196 +bit 03_197 +bit 03_198 +bit 03_20 +bit 03_200 +bit 03_201 +bit 03_202 +bit 03_204 +bit 03_205 +bit 03_206 +bit 03_208 +bit 03_209 +bit 03_21 +bit 03_210 +bit 03_212 +bit 03_213 +bit 03_214 +bit 03_216 +bit 03_217 +bit 03_218 +bit 03_22 +bit 03_220 +bit 03_221 +bit 03_222 +bit 03_224 +bit 03_225 +bit 03_226 +bit 03_228 +bit 03_229 +bit 03_230 +bit 03_232 +bit 03_233 +bit 03_234 +bit 03_236 +bit 03_237 +bit 03_238 +bit 03_24 +bit 03_240 +bit 03_241 +bit 03_242 +bit 03_244 +bit 03_245 +bit 03_246 +bit 03_248 +bit 03_249 +bit 03_25 +bit 03_250 +bit 03_252 +bit 03_253 +bit 03_254 +bit 03_256 +bit 03_257 +bit 03_258 +bit 03_26 +bit 03_260 +bit 03_261 +bit 03_262 +bit 03_264 +bit 03_265 +bit 03_266 +bit 03_268 +bit 03_269 +bit 03_270 +bit 03_272 +bit 03_273 +bit 03_274 +bit 03_276 +bit 03_277 +bit 03_278 +bit 03_28 +bit 03_280 +bit 03_281 +bit 03_282 +bit 03_284 +bit 03_285 +bit 03_286 +bit 03_288 +bit 03_289 +bit 03_29 +bit 03_290 +bit 03_292 +bit 03_293 +bit 03_294 +bit 03_296 +bit 03_297 +bit 03_298 +bit 03_30 +bit 03_300 +bit 03_301 +bit 03_302 +bit 03_304 +bit 03_305 +bit 03_306 +bit 03_308 +bit 03_309 +bit 03_310 +bit 03_312 +bit 03_313 +bit 03_314 +bit 03_316 +bit 03_317 +bit 03_318 +bit 03_32 +bit 03_33 +bit 03_34 +bit 03_36 +bit 03_37 +bit 03_38 +bit 03_40 +bit 03_41 +bit 03_42 +bit 03_44 +bit 03_45 +bit 03_46 +bit 03_48 +bit 03_49 +bit 03_50 +bit 03_52 +bit 03_53 +bit 03_54 +bit 03_56 +bit 03_57 +bit 03_58 +bit 03_60 +bit 03_61 +bit 03_62 +bit 03_64 +bit 03_65 +bit 03_66 +bit 03_68 +bit 03_69 +bit 03_70 +bit 03_72 +bit 03_73 +bit 03_74 +bit 03_76 +bit 03_77 +bit 03_78 +bit 03_80 +bit 03_81 +bit 03_82 +bit 03_84 +bit 03_85 +bit 03_86 +bit 03_88 +bit 03_89 +bit 03_90 +bit 03_92 +bit 03_93 +bit 03_94 +bit 03_96 +bit 03_97 +bit 03_98 +bit 04_00 +bit 04_01 +bit 04_02 +bit 04_03 +bit 04_04 +bit 04_05 +bit 04_06 +bit 04_07 +bit 04_08 +bit 04_09 +bit 04_10 +bit 04_100 +bit 04_101 +bit 04_102 +bit 04_103 +bit 04_104 +bit 04_105 +bit 04_106 +bit 04_107 +bit 04_108 +bit 04_109 +bit 04_11 +bit 04_110 +bit 04_111 +bit 04_112 +bit 04_113 +bit 04_114 +bit 04_115 +bit 04_116 +bit 04_117 +bit 04_118 +bit 04_119 +bit 04_12 +bit 04_120 +bit 04_121 +bit 04_122 +bit 04_123 +bit 04_124 +bit 04_125 +bit 04_126 +bit 04_127 +bit 04_128 +bit 04_129 +bit 04_13 +bit 04_130 +bit 04_131 +bit 04_132 +bit 04_133 +bit 04_134 +bit 04_135 +bit 04_136 +bit 04_137 +bit 04_138 +bit 04_139 +bit 04_14 +bit 04_140 +bit 04_141 +bit 04_142 +bit 04_143 +bit 04_144 +bit 04_145 +bit 04_146 +bit 04_147 +bit 04_148 +bit 04_149 +bit 04_15 +bit 04_150 +bit 04_151 +bit 04_152 +bit 04_153 +bit 04_154 +bit 04_155 +bit 04_156 +bit 04_157 +bit 04_158 +bit 04_159 +bit 04_16 +bit 04_160 +bit 04_161 +bit 04_162 +bit 04_163 +bit 04_164 +bit 04_165 +bit 04_166 +bit 04_167 +bit 04_168 +bit 04_169 +bit 04_17 +bit 04_170 +bit 04_171 +bit 04_172 +bit 04_173 +bit 04_174 +bit 04_175 +bit 04_176 +bit 04_177 +bit 04_178 +bit 04_179 +bit 04_18 +bit 04_180 +bit 04_181 +bit 04_182 +bit 04_183 +bit 04_184 +bit 04_185 +bit 04_186 +bit 04_187 +bit 04_188 +bit 04_189 +bit 04_19 +bit 04_190 +bit 04_191 +bit 04_192 +bit 04_193 +bit 04_194 +bit 04_195 +bit 04_196 +bit 04_197 +bit 04_198 +bit 04_199 +bit 04_20 +bit 04_200 +bit 04_201 +bit 04_202 +bit 04_203 +bit 04_204 +bit 04_205 +bit 04_206 +bit 04_207 +bit 04_208 +bit 04_209 +bit 04_21 +bit 04_210 +bit 04_211 +bit 04_212 +bit 04_213 +bit 04_214 +bit 04_215 +bit 04_216 +bit 04_217 +bit 04_218 +bit 04_219 +bit 04_22 +bit 04_220 +bit 04_221 +bit 04_222 +bit 04_223 +bit 04_224 +bit 04_225 +bit 04_226 +bit 04_227 +bit 04_228 +bit 04_229 +bit 04_23 +bit 04_230 +bit 04_231 +bit 04_232 +bit 04_233 +bit 04_234 +bit 04_235 +bit 04_236 +bit 04_237 +bit 04_238 +bit 04_239 +bit 04_24 +bit 04_240 +bit 04_241 +bit 04_242 +bit 04_243 +bit 04_244 +bit 04_245 +bit 04_246 +bit 04_247 +bit 04_248 +bit 04_249 +bit 04_25 +bit 04_250 +bit 04_251 +bit 04_252 +bit 04_253 +bit 04_254 +bit 04_255 +bit 04_256 +bit 04_257 +bit 04_258 +bit 04_259 +bit 04_26 +bit 04_260 +bit 04_261 +bit 04_262 +bit 04_263 +bit 04_264 +bit 04_265 +bit 04_266 +bit 04_267 +bit 04_268 +bit 04_269 +bit 04_27 +bit 04_270 +bit 04_271 +bit 04_272 +bit 04_273 +bit 04_274 +bit 04_275 +bit 04_276 +bit 04_277 +bit 04_278 +bit 04_279 +bit 04_28 +bit 04_280 +bit 04_281 +bit 04_282 +bit 04_283 +bit 04_284 +bit 04_285 +bit 04_286 +bit 04_287 +bit 04_288 +bit 04_289 +bit 04_29 +bit 04_290 +bit 04_291 +bit 04_292 +bit 04_293 +bit 04_294 +bit 04_295 +bit 04_296 +bit 04_297 +bit 04_298 +bit 04_299 +bit 04_30 +bit 04_300 +bit 04_301 +bit 04_302 +bit 04_303 +bit 04_304 +bit 04_305 +bit 04_306 +bit 04_307 +bit 04_308 +bit 04_309 +bit 04_31 +bit 04_310 +bit 04_311 +bit 04_312 +bit 04_313 +bit 04_314 +bit 04_315 +bit 04_316 +bit 04_317 +bit 04_318 +bit 04_319 +bit 04_32 +bit 04_33 +bit 04_34 +bit 04_35 +bit 04_36 +bit 04_37 +bit 04_38 +bit 04_39 +bit 04_40 +bit 04_41 +bit 04_42 +bit 04_43 +bit 04_44 +bit 04_45 +bit 04_46 +bit 04_47 +bit 04_48 +bit 04_49 +bit 04_50 +bit 04_51 +bit 04_52 +bit 04_53 +bit 04_54 +bit 04_55 +bit 04_56 +bit 04_57 +bit 04_58 +bit 04_59 +bit 04_60 +bit 04_61 +bit 04_62 +bit 04_63 +bit 04_64 +bit 04_65 +bit 04_66 +bit 04_67 +bit 04_68 +bit 04_69 +bit 04_70 +bit 04_71 +bit 04_72 +bit 04_73 +bit 04_74 +bit 04_75 +bit 04_76 +bit 04_77 +bit 04_78 +bit 04_79 +bit 04_80 +bit 04_81 +bit 04_82 +bit 04_83 +bit 04_84 +bit 04_85 +bit 04_86 +bit 04_87 +bit 04_88 +bit 04_89 +bit 04_90 +bit 04_91 +bit 04_92 +bit 04_93 +bit 04_94 +bit 04_95 +bit 04_96 +bit 04_97 +bit 04_98 +bit 04_99 +bit 05_00 +bit 05_01 +bit 05_02 +bit 05_03 +bit 05_04 +bit 05_05 +bit 05_06 +bit 05_07 +bit 05_08 +bit 05_09 +bit 05_10 +bit 05_100 +bit 05_101 +bit 05_102 +bit 05_103 +bit 05_104 +bit 05_105 +bit 05_106 +bit 05_107 +bit 05_108 +bit 05_109 +bit 05_11 +bit 05_110 +bit 05_111 +bit 05_112 +bit 05_113 +bit 05_114 +bit 05_115 +bit 05_116 +bit 05_117 +bit 05_118 +bit 05_119 +bit 05_12 +bit 05_120 +bit 05_121 +bit 05_122 +bit 05_123 +bit 05_124 +bit 05_125 +bit 05_126 +bit 05_127 +bit 05_128 +bit 05_129 +bit 05_13 +bit 05_130 +bit 05_131 +bit 05_132 +bit 05_133 +bit 05_134 +bit 05_135 +bit 05_136 +bit 05_137 +bit 05_138 +bit 05_139 +bit 05_14 +bit 05_140 +bit 05_141 +bit 05_142 +bit 05_143 +bit 05_144 +bit 05_145 +bit 05_146 +bit 05_147 +bit 05_148 +bit 05_149 +bit 05_15 +bit 05_150 +bit 05_151 +bit 05_152 +bit 05_153 +bit 05_154 +bit 05_155 +bit 05_156 +bit 05_157 +bit 05_158 +bit 05_159 +bit 05_16 +bit 05_160 +bit 05_161 +bit 05_162 +bit 05_163 +bit 05_164 +bit 05_165 +bit 05_166 +bit 05_167 +bit 05_168 +bit 05_169 +bit 05_17 +bit 05_170 +bit 05_171 +bit 05_172 +bit 05_173 +bit 05_174 +bit 05_175 +bit 05_176 +bit 05_177 +bit 05_178 +bit 05_179 +bit 05_18 +bit 05_180 +bit 05_181 +bit 05_182 +bit 05_183 +bit 05_184 +bit 05_185 +bit 05_186 +bit 05_187 +bit 05_188 +bit 05_189 +bit 05_19 +bit 05_190 +bit 05_191 +bit 05_192 +bit 05_193 +bit 05_194 +bit 05_195 +bit 05_196 +bit 05_197 +bit 05_198 +bit 05_199 +bit 05_20 +bit 05_200 +bit 05_201 +bit 05_202 +bit 05_203 +bit 05_204 +bit 05_205 +bit 05_206 +bit 05_207 +bit 05_208 +bit 05_209 +bit 05_21 +bit 05_210 +bit 05_211 +bit 05_212 +bit 05_213 +bit 05_214 +bit 05_215 +bit 05_216 +bit 05_217 +bit 05_218 +bit 05_219 +bit 05_22 +bit 05_220 +bit 05_221 +bit 05_222 +bit 05_223 +bit 05_224 +bit 05_225 +bit 05_226 +bit 05_227 +bit 05_228 +bit 05_229 +bit 05_23 +bit 05_230 +bit 05_231 +bit 05_232 +bit 05_233 +bit 05_234 +bit 05_235 +bit 05_236 +bit 05_237 +bit 05_238 +bit 05_239 +bit 05_24 +bit 05_240 +bit 05_241 +bit 05_242 +bit 05_243 +bit 05_244 +bit 05_245 +bit 05_246 +bit 05_247 +bit 05_248 +bit 05_249 +bit 05_25 +bit 05_250 +bit 05_251 +bit 05_252 +bit 05_253 +bit 05_254 +bit 05_255 +bit 05_256 +bit 05_257 +bit 05_258 +bit 05_259 +bit 05_26 +bit 05_260 +bit 05_261 +bit 05_262 +bit 05_263 +bit 05_264 +bit 05_265 +bit 05_266 +bit 05_267 +bit 05_268 +bit 05_269 +bit 05_27 +bit 05_270 +bit 05_271 +bit 05_272 +bit 05_273 +bit 05_274 +bit 05_275 +bit 05_276 +bit 05_277 +bit 05_278 +bit 05_279 +bit 05_28 +bit 05_280 +bit 05_281 +bit 05_282 +bit 05_283 +bit 05_284 +bit 05_285 +bit 05_286 +bit 05_287 +bit 05_288 +bit 05_289 +bit 05_29 +bit 05_290 +bit 05_291 +bit 05_292 +bit 05_293 +bit 05_294 +bit 05_295 +bit 05_296 +bit 05_297 +bit 05_298 +bit 05_299 +bit 05_30 +bit 05_300 +bit 05_301 +bit 05_302 +bit 05_303 +bit 05_304 +bit 05_305 +bit 05_306 +bit 05_307 +bit 05_308 +bit 05_309 +bit 05_31 +bit 05_310 +bit 05_311 +bit 05_312 +bit 05_313 +bit 05_314 +bit 05_315 +bit 05_316 +bit 05_317 +bit 05_318 +bit 05_319 +bit 05_32 +bit 05_33 +bit 05_34 +bit 05_35 +bit 05_36 +bit 05_37 +bit 05_38 +bit 05_39 +bit 05_40 +bit 05_41 +bit 05_42 +bit 05_43 +bit 05_44 +bit 05_45 +bit 05_46 +bit 05_47 +bit 05_48 +bit 05_49 +bit 05_50 +bit 05_51 +bit 05_52 +bit 05_53 +bit 05_54 +bit 05_55 +bit 05_56 +bit 05_57 +bit 05_58 +bit 05_59 +bit 05_60 +bit 05_61 +bit 05_62 +bit 05_63 +bit 05_64 +bit 05_65 +bit 05_66 +bit 05_67 +bit 05_68 +bit 05_69 +bit 05_70 +bit 05_71 +bit 05_72 +bit 05_73 +bit 05_74 +bit 05_75 +bit 05_76 +bit 05_77 +bit 05_78 +bit 05_79 +bit 05_80 +bit 05_81 +bit 05_82 +bit 05_83 +bit 05_84 +bit 05_85 +bit 05_86 +bit 05_87 +bit 05_88 +bit 05_89 +bit 05_90 +bit 05_91 +bit 05_92 +bit 05_93 +bit 05_94 +bit 05_95 +bit 05_96 +bit 05_97 +bit 05_98 +bit 05_99 +bit 06_00 +bit 06_01 +bit 06_02 +bit 06_03 +bit 06_04 +bit 06_05 +bit 06_06 +bit 06_07 +bit 06_08 +bit 06_09 +bit 06_10 +bit 06_100 +bit 06_101 +bit 06_102 +bit 06_103 +bit 06_104 +bit 06_105 +bit 06_106 +bit 06_107 +bit 06_108 +bit 06_109 +bit 06_11 +bit 06_110 +bit 06_111 +bit 06_112 +bit 06_113 +bit 06_114 +bit 06_115 +bit 06_116 +bit 06_117 +bit 06_118 +bit 06_119 +bit 06_12 +bit 06_120 +bit 06_121 +bit 06_122 +bit 06_123 +bit 06_124 +bit 06_125 +bit 06_126 +bit 06_127 +bit 06_128 +bit 06_129 +bit 06_13 +bit 06_130 +bit 06_131 +bit 06_132 +bit 06_133 +bit 06_134 +bit 06_135 +bit 06_136 +bit 06_137 +bit 06_138 +bit 06_139 +bit 06_14 +bit 06_140 +bit 06_141 +bit 06_142 +bit 06_143 +bit 06_144 +bit 06_145 +bit 06_146 +bit 06_147 +bit 06_148 +bit 06_149 +bit 06_15 +bit 06_150 +bit 06_151 +bit 06_152 +bit 06_153 +bit 06_154 +bit 06_155 +bit 06_156 +bit 06_157 +bit 06_158 +bit 06_159 +bit 06_16 +bit 06_160 +bit 06_161 +bit 06_162 +bit 06_163 +bit 06_164 +bit 06_165 +bit 06_166 +bit 06_167 +bit 06_168 +bit 06_169 +bit 06_17 +bit 06_170 +bit 06_171 +bit 06_172 +bit 06_173 +bit 06_174 +bit 06_175 +bit 06_176 +bit 06_177 +bit 06_178 +bit 06_179 +bit 06_18 +bit 06_180 +bit 06_181 +bit 06_182 +bit 06_183 +bit 06_184 +bit 06_185 +bit 06_186 +bit 06_187 +bit 06_188 +bit 06_189 +bit 06_19 +bit 06_190 +bit 06_191 +bit 06_192 +bit 06_193 +bit 06_194 +bit 06_195 +bit 06_196 +bit 06_197 +bit 06_198 +bit 06_199 +bit 06_20 +bit 06_200 +bit 06_201 +bit 06_202 +bit 06_203 +bit 06_204 +bit 06_205 +bit 06_206 +bit 06_207 +bit 06_208 +bit 06_209 +bit 06_21 +bit 06_210 +bit 06_211 +bit 06_212 +bit 06_213 +bit 06_214 +bit 06_215 +bit 06_216 +bit 06_217 +bit 06_218 +bit 06_219 +bit 06_22 +bit 06_220 +bit 06_221 +bit 06_222 +bit 06_223 +bit 06_224 +bit 06_225 +bit 06_226 +bit 06_227 +bit 06_228 +bit 06_229 +bit 06_23 +bit 06_230 +bit 06_231 +bit 06_232 +bit 06_233 +bit 06_234 +bit 06_235 +bit 06_236 +bit 06_237 +bit 06_238 +bit 06_239 +bit 06_24 +bit 06_240 +bit 06_241 +bit 06_242 +bit 06_243 +bit 06_244 +bit 06_245 +bit 06_246 +bit 06_247 +bit 06_248 +bit 06_249 +bit 06_25 +bit 06_250 +bit 06_251 +bit 06_252 +bit 06_253 +bit 06_254 +bit 06_255 +bit 06_256 +bit 06_257 +bit 06_258 +bit 06_259 +bit 06_26 +bit 06_260 +bit 06_261 +bit 06_262 +bit 06_263 +bit 06_264 +bit 06_265 +bit 06_266 +bit 06_267 +bit 06_268 +bit 06_269 +bit 06_27 +bit 06_270 +bit 06_271 +bit 06_272 +bit 06_273 +bit 06_274 +bit 06_275 +bit 06_276 +bit 06_277 +bit 06_278 +bit 06_279 +bit 06_28 +bit 06_280 +bit 06_281 +bit 06_282 +bit 06_283 +bit 06_284 +bit 06_285 +bit 06_286 +bit 06_287 +bit 06_288 +bit 06_289 +bit 06_29 +bit 06_290 +bit 06_291 +bit 06_292 +bit 06_293 +bit 06_294 +bit 06_295 +bit 06_296 +bit 06_297 +bit 06_298 +bit 06_299 +bit 06_30 +bit 06_300 +bit 06_301 +bit 06_302 +bit 06_303 +bit 06_304 +bit 06_305 +bit 06_306 +bit 06_307 +bit 06_308 +bit 06_309 +bit 06_31 +bit 06_310 +bit 06_311 +bit 06_312 +bit 06_313 +bit 06_314 +bit 06_315 +bit 06_316 +bit 06_317 +bit 06_318 +bit 06_319 +bit 06_32 +bit 06_33 +bit 06_34 +bit 06_35 +bit 06_36 +bit 06_37 +bit 06_38 +bit 06_39 +bit 06_40 +bit 06_41 +bit 06_42 +bit 06_43 +bit 06_44 +bit 06_45 +bit 06_46 +bit 06_47 +bit 06_48 +bit 06_49 +bit 06_50 +bit 06_51 +bit 06_52 +bit 06_53 +bit 06_54 +bit 06_55 +bit 06_56 +bit 06_57 +bit 06_58 +bit 06_59 +bit 06_60 +bit 06_61 +bit 06_62 +bit 06_63 +bit 06_64 +bit 06_65 +bit 06_66 +bit 06_67 +bit 06_68 +bit 06_69 +bit 06_70 +bit 06_71 +bit 06_72 +bit 06_73 +bit 06_74 +bit 06_75 +bit 06_76 +bit 06_77 +bit 06_78 +bit 06_79 +bit 06_80 +bit 06_81 +bit 06_82 +bit 06_83 +bit 06_84 +bit 06_85 +bit 06_86 +bit 06_87 +bit 06_88 +bit 06_89 +bit 06_90 +bit 06_91 +bit 06_92 +bit 06_93 +bit 06_94 +bit 06_95 +bit 06_96 +bit 06_97 +bit 06_98 +bit 06_99 +bit 07_00 +bit 07_01 +bit 07_02 +bit 07_03 +bit 07_04 +bit 07_05 +bit 07_06 +bit 07_07 +bit 07_08 +bit 07_09 +bit 07_10 +bit 07_100 +bit 07_101 +bit 07_102 +bit 07_103 +bit 07_104 +bit 07_105 +bit 07_106 +bit 07_107 +bit 07_108 +bit 07_109 +bit 07_11 +bit 07_110 +bit 07_111 +bit 07_112 +bit 07_113 +bit 07_114 +bit 07_115 +bit 07_116 +bit 07_117 +bit 07_118 +bit 07_119 +bit 07_12 +bit 07_120 +bit 07_121 +bit 07_122 +bit 07_123 +bit 07_124 +bit 07_125 +bit 07_126 +bit 07_127 +bit 07_128 +bit 07_129 +bit 07_13 +bit 07_130 +bit 07_131 +bit 07_132 +bit 07_133 +bit 07_134 +bit 07_135 +bit 07_136 +bit 07_137 +bit 07_138 +bit 07_139 +bit 07_14 +bit 07_140 +bit 07_141 +bit 07_142 +bit 07_143 +bit 07_144 +bit 07_145 +bit 07_146 +bit 07_147 +bit 07_148 +bit 07_149 +bit 07_15 +bit 07_150 +bit 07_151 +bit 07_152 +bit 07_153 +bit 07_154 +bit 07_155 +bit 07_156 +bit 07_157 +bit 07_158 +bit 07_159 +bit 07_16 +bit 07_160 +bit 07_161 +bit 07_162 +bit 07_163 +bit 07_164 +bit 07_165 +bit 07_166 +bit 07_167 +bit 07_168 +bit 07_169 +bit 07_17 +bit 07_170 +bit 07_171 +bit 07_172 +bit 07_173 +bit 07_174 +bit 07_175 +bit 07_176 +bit 07_177 +bit 07_178 +bit 07_179 +bit 07_18 +bit 07_180 +bit 07_181 +bit 07_182 +bit 07_183 +bit 07_184 +bit 07_185 +bit 07_186 +bit 07_187 +bit 07_188 +bit 07_189 +bit 07_19 +bit 07_190 +bit 07_191 +bit 07_192 +bit 07_193 +bit 07_194 +bit 07_195 +bit 07_196 +bit 07_197 +bit 07_198 +bit 07_199 +bit 07_20 +bit 07_200 +bit 07_201 +bit 07_202 +bit 07_203 +bit 07_204 +bit 07_205 +bit 07_206 +bit 07_207 +bit 07_208 +bit 07_209 +bit 07_21 +bit 07_210 +bit 07_211 +bit 07_212 +bit 07_213 +bit 07_214 +bit 07_215 +bit 07_216 +bit 07_217 +bit 07_218 +bit 07_219 +bit 07_22 +bit 07_220 +bit 07_221 +bit 07_222 +bit 07_223 +bit 07_224 +bit 07_225 +bit 07_226 +bit 07_227 +bit 07_228 +bit 07_229 +bit 07_23 +bit 07_230 +bit 07_231 +bit 07_232 +bit 07_233 +bit 07_234 +bit 07_235 +bit 07_236 +bit 07_237 +bit 07_238 +bit 07_239 +bit 07_24 +bit 07_240 +bit 07_241 +bit 07_242 +bit 07_243 +bit 07_244 +bit 07_245 +bit 07_246 +bit 07_247 +bit 07_248 +bit 07_249 +bit 07_25 +bit 07_250 +bit 07_251 +bit 07_252 +bit 07_253 +bit 07_254 +bit 07_255 +bit 07_256 +bit 07_257 +bit 07_258 +bit 07_259 +bit 07_26 +bit 07_260 +bit 07_261 +bit 07_262 +bit 07_263 +bit 07_264 +bit 07_265 +bit 07_266 +bit 07_267 +bit 07_268 +bit 07_269 +bit 07_27 +bit 07_270 +bit 07_271 +bit 07_272 +bit 07_273 +bit 07_274 +bit 07_275 +bit 07_276 +bit 07_277 +bit 07_278 +bit 07_279 +bit 07_28 +bit 07_280 +bit 07_281 +bit 07_282 +bit 07_283 +bit 07_284 +bit 07_285 +bit 07_286 +bit 07_287 +bit 07_288 +bit 07_289 +bit 07_29 +bit 07_290 +bit 07_291 +bit 07_292 +bit 07_293 +bit 07_294 +bit 07_295 +bit 07_296 +bit 07_297 +bit 07_298 +bit 07_299 +bit 07_30 +bit 07_300 +bit 07_301 +bit 07_302 +bit 07_303 +bit 07_304 +bit 07_305 +bit 07_306 +bit 07_307 +bit 07_308 +bit 07_309 +bit 07_31 +bit 07_310 +bit 07_311 +bit 07_312 +bit 07_313 +bit 07_314 +bit 07_315 +bit 07_316 +bit 07_317 +bit 07_318 +bit 07_319 +bit 07_32 +bit 07_33 +bit 07_34 +bit 07_35 +bit 07_36 +bit 07_37 +bit 07_38 +bit 07_39 +bit 07_40 +bit 07_41 +bit 07_42 +bit 07_43 +bit 07_44 +bit 07_45 +bit 07_46 +bit 07_47 +bit 07_48 +bit 07_49 +bit 07_50 +bit 07_51 +bit 07_52 +bit 07_53 +bit 07_54 +bit 07_55 +bit 07_56 +bit 07_57 +bit 07_58 +bit 07_59 +bit 07_60 +bit 07_61 +bit 07_62 +bit 07_63 +bit 07_64 +bit 07_65 +bit 07_66 +bit 07_67 +bit 07_68 +bit 07_69 +bit 07_70 +bit 07_71 +bit 07_72 +bit 07_73 +bit 07_74 +bit 07_75 +bit 07_76 +bit 07_77 +bit 07_78 +bit 07_79 +bit 07_80 +bit 07_81 +bit 07_82 +bit 07_83 +bit 07_84 +bit 07_85 +bit 07_86 +bit 07_87 +bit 07_88 +bit 07_89 +bit 07_90 +bit 07_91 +bit 07_92 +bit 07_93 +bit 07_94 +bit 07_95 +bit 07_96 +bit 07_97 +bit 07_98 +bit 07_99 +bit 08_00 +bit 08_01 +bit 08_02 +bit 08_03 +bit 08_04 +bit 08_05 +bit 08_06 +bit 08_07 +bit 08_08 +bit 08_09 +bit 08_10 +bit 08_100 +bit 08_101 +bit 08_102 +bit 08_103 +bit 08_104 +bit 08_105 +bit 08_106 +bit 08_107 +bit 08_108 +bit 08_109 +bit 08_11 +bit 08_110 +bit 08_111 +bit 08_112 +bit 08_113 +bit 08_114 +bit 08_115 +bit 08_116 +bit 08_117 +bit 08_118 +bit 08_119 +bit 08_12 +bit 08_120 +bit 08_121 +bit 08_122 +bit 08_123 +bit 08_124 +bit 08_125 +bit 08_126 +bit 08_127 +bit 08_128 +bit 08_129 +bit 08_13 +bit 08_130 +bit 08_131 +bit 08_132 +bit 08_133 +bit 08_134 +bit 08_135 +bit 08_136 +bit 08_137 +bit 08_138 +bit 08_139 +bit 08_14 +bit 08_140 +bit 08_141 +bit 08_142 +bit 08_143 +bit 08_144 +bit 08_145 +bit 08_146 +bit 08_147 +bit 08_148 +bit 08_149 +bit 08_15 +bit 08_150 +bit 08_151 +bit 08_152 +bit 08_153 +bit 08_154 +bit 08_155 +bit 08_156 +bit 08_157 +bit 08_158 +bit 08_159 +bit 08_16 +bit 08_160 +bit 08_161 +bit 08_162 +bit 08_163 +bit 08_164 +bit 08_165 +bit 08_166 +bit 08_167 +bit 08_168 +bit 08_169 +bit 08_17 +bit 08_170 +bit 08_171 +bit 08_172 +bit 08_173 +bit 08_174 +bit 08_175 +bit 08_176 +bit 08_177 +bit 08_178 +bit 08_179 +bit 08_18 +bit 08_180 +bit 08_181 +bit 08_182 +bit 08_183 +bit 08_184 +bit 08_185 +bit 08_186 +bit 08_187 +bit 08_188 +bit 08_189 +bit 08_19 +bit 08_190 +bit 08_191 +bit 08_192 +bit 08_193 +bit 08_194 +bit 08_195 +bit 08_196 +bit 08_197 +bit 08_198 +bit 08_199 +bit 08_20 +bit 08_200 +bit 08_201 +bit 08_202 +bit 08_203 +bit 08_204 +bit 08_205 +bit 08_206 +bit 08_207 +bit 08_208 +bit 08_209 +bit 08_21 +bit 08_210 +bit 08_211 +bit 08_212 +bit 08_213 +bit 08_214 +bit 08_215 +bit 08_216 +bit 08_217 +bit 08_218 +bit 08_219 +bit 08_22 +bit 08_220 +bit 08_221 +bit 08_222 +bit 08_223 +bit 08_224 +bit 08_225 +bit 08_226 +bit 08_227 +bit 08_228 +bit 08_229 +bit 08_23 +bit 08_230 +bit 08_231 +bit 08_232 +bit 08_233 +bit 08_234 +bit 08_235 +bit 08_236 +bit 08_237 +bit 08_238 +bit 08_239 +bit 08_24 +bit 08_240 +bit 08_241 +bit 08_242 +bit 08_243 +bit 08_244 +bit 08_245 +bit 08_246 +bit 08_247 +bit 08_248 +bit 08_249 +bit 08_25 +bit 08_250 +bit 08_251 +bit 08_252 +bit 08_253 +bit 08_254 +bit 08_255 +bit 08_256 +bit 08_257 +bit 08_258 +bit 08_259 +bit 08_26 +bit 08_260 +bit 08_261 +bit 08_262 +bit 08_263 +bit 08_264 +bit 08_265 +bit 08_266 +bit 08_267 +bit 08_268 +bit 08_269 +bit 08_27 +bit 08_270 +bit 08_271 +bit 08_272 +bit 08_273 +bit 08_274 +bit 08_275 +bit 08_276 +bit 08_277 +bit 08_278 +bit 08_279 +bit 08_28 +bit 08_280 +bit 08_281 +bit 08_282 +bit 08_283 +bit 08_284 +bit 08_285 +bit 08_286 +bit 08_287 +bit 08_288 +bit 08_289 +bit 08_29 +bit 08_290 +bit 08_291 +bit 08_292 +bit 08_293 +bit 08_294 +bit 08_295 +bit 08_296 +bit 08_297 +bit 08_298 +bit 08_299 +bit 08_30 +bit 08_300 +bit 08_301 +bit 08_302 +bit 08_303 +bit 08_304 +bit 08_305 +bit 08_306 +bit 08_307 +bit 08_308 +bit 08_309 +bit 08_31 +bit 08_310 +bit 08_311 +bit 08_312 +bit 08_313 +bit 08_314 +bit 08_315 +bit 08_316 +bit 08_317 +bit 08_318 +bit 08_319 +bit 08_32 +bit 08_33 +bit 08_34 +bit 08_35 +bit 08_36 +bit 08_37 +bit 08_38 +bit 08_39 +bit 08_40 +bit 08_41 +bit 08_42 +bit 08_43 +bit 08_44 +bit 08_45 +bit 08_46 +bit 08_47 +bit 08_48 +bit 08_49 +bit 08_50 +bit 08_51 +bit 08_52 +bit 08_53 +bit 08_54 +bit 08_55 +bit 08_56 +bit 08_57 +bit 08_58 +bit 08_59 +bit 08_60 +bit 08_61 +bit 08_62 +bit 08_63 +bit 08_64 +bit 08_65 +bit 08_66 +bit 08_67 +bit 08_68 +bit 08_69 +bit 08_70 +bit 08_71 +bit 08_72 +bit 08_73 +bit 08_74 +bit 08_75 +bit 08_76 +bit 08_77 +bit 08_78 +bit 08_79 +bit 08_80 +bit 08_81 +bit 08_82 +bit 08_83 +bit 08_84 +bit 08_85 +bit 08_86 +bit 08_87 +bit 08_88 +bit 08_89 +bit 08_90 +bit 08_91 +bit 08_92 +bit 08_93 +bit 08_94 +bit 08_95 +bit 08_96 +bit 08_97 +bit 08_98 +bit 08_99 +bit 09_00 +bit 09_01 +bit 09_02 +bit 09_03 +bit 09_04 +bit 09_05 +bit 09_06 +bit 09_07 +bit 09_08 +bit 09_09 +bit 09_10 +bit 09_100 +bit 09_101 +bit 09_102 +bit 09_103 +bit 09_104 +bit 09_105 +bit 09_106 +bit 09_107 +bit 09_108 +bit 09_109 +bit 09_11 +bit 09_110 +bit 09_111 +bit 09_112 +bit 09_113 +bit 09_114 +bit 09_115 +bit 09_116 +bit 09_117 +bit 09_118 +bit 09_119 +bit 09_12 +bit 09_120 +bit 09_121 +bit 09_122 +bit 09_123 +bit 09_124 +bit 09_125 +bit 09_126 +bit 09_127 +bit 09_128 +bit 09_129 +bit 09_13 +bit 09_130 +bit 09_131 +bit 09_132 +bit 09_133 +bit 09_134 +bit 09_135 +bit 09_136 +bit 09_137 +bit 09_138 +bit 09_139 +bit 09_14 +bit 09_140 +bit 09_141 +bit 09_142 +bit 09_143 +bit 09_144 +bit 09_145 +bit 09_146 +bit 09_147 +bit 09_148 +bit 09_149 +bit 09_15 +bit 09_150 +bit 09_151 +bit 09_152 +bit 09_153 +bit 09_154 +bit 09_155 +bit 09_156 +bit 09_157 +bit 09_158 +bit 09_159 +bit 09_16 +bit 09_160 +bit 09_161 +bit 09_162 +bit 09_163 +bit 09_164 +bit 09_165 +bit 09_166 +bit 09_167 +bit 09_168 +bit 09_169 +bit 09_17 +bit 09_170 +bit 09_171 +bit 09_172 +bit 09_173 +bit 09_174 +bit 09_175 +bit 09_176 +bit 09_177 +bit 09_178 +bit 09_179 +bit 09_18 +bit 09_180 +bit 09_181 +bit 09_182 +bit 09_183 +bit 09_184 +bit 09_185 +bit 09_186 +bit 09_187 +bit 09_188 +bit 09_189 +bit 09_19 +bit 09_190 +bit 09_191 +bit 09_192 +bit 09_193 +bit 09_194 +bit 09_195 +bit 09_196 +bit 09_197 +bit 09_198 +bit 09_199 +bit 09_20 +bit 09_200 +bit 09_201 +bit 09_202 +bit 09_203 +bit 09_204 +bit 09_205 +bit 09_206 +bit 09_207 +bit 09_208 +bit 09_209 +bit 09_21 +bit 09_210 +bit 09_211 +bit 09_212 +bit 09_213 +bit 09_214 +bit 09_215 +bit 09_216 +bit 09_217 +bit 09_218 +bit 09_219 +bit 09_22 +bit 09_220 +bit 09_221 +bit 09_222 +bit 09_223 +bit 09_224 +bit 09_225 +bit 09_226 +bit 09_227 +bit 09_228 +bit 09_229 +bit 09_23 +bit 09_230 +bit 09_231 +bit 09_232 +bit 09_233 +bit 09_234 +bit 09_235 +bit 09_236 +bit 09_237 +bit 09_238 +bit 09_239 +bit 09_24 +bit 09_240 +bit 09_241 +bit 09_242 +bit 09_243 +bit 09_244 +bit 09_245 +bit 09_246 +bit 09_247 +bit 09_248 +bit 09_249 +bit 09_25 +bit 09_250 +bit 09_251 +bit 09_252 +bit 09_253 +bit 09_254 +bit 09_255 +bit 09_256 +bit 09_257 +bit 09_258 +bit 09_259 +bit 09_26 +bit 09_260 +bit 09_261 +bit 09_262 +bit 09_263 +bit 09_264 +bit 09_265 +bit 09_266 +bit 09_267 +bit 09_268 +bit 09_269 +bit 09_27 +bit 09_270 +bit 09_271 +bit 09_272 +bit 09_273 +bit 09_274 +bit 09_275 +bit 09_276 +bit 09_277 +bit 09_278 +bit 09_279 +bit 09_28 +bit 09_280 +bit 09_281 +bit 09_282 +bit 09_283 +bit 09_284 +bit 09_285 +bit 09_286 +bit 09_287 +bit 09_288 +bit 09_289 +bit 09_29 +bit 09_290 +bit 09_291 +bit 09_292 +bit 09_293 +bit 09_294 +bit 09_295 +bit 09_296 +bit 09_297 +bit 09_298 +bit 09_299 +bit 09_30 +bit 09_300 +bit 09_301 +bit 09_302 +bit 09_303 +bit 09_304 +bit 09_305 +bit 09_306 +bit 09_307 +bit 09_308 +bit 09_309 +bit 09_31 +bit 09_310 +bit 09_311 +bit 09_312 +bit 09_313 +bit 09_314 +bit 09_315 +bit 09_316 +bit 09_317 +bit 09_318 +bit 09_319 +bit 09_32 +bit 09_33 +bit 09_34 +bit 09_35 +bit 09_36 +bit 09_37 +bit 09_38 +bit 09_39 +bit 09_40 +bit 09_41 +bit 09_42 +bit 09_43 +bit 09_44 +bit 09_45 +bit 09_46 +bit 09_47 +bit 09_48 +bit 09_49 +bit 09_50 +bit 09_51 +bit 09_52 +bit 09_53 +bit 09_54 +bit 09_55 +bit 09_56 +bit 09_57 +bit 09_58 +bit 09_59 +bit 09_60 +bit 09_61 +bit 09_62 +bit 09_63 +bit 09_64 +bit 09_65 +bit 09_66 +bit 09_67 +bit 09_68 +bit 09_69 +bit 09_70 +bit 09_71 +bit 09_72 +bit 09_73 +bit 09_74 +bit 09_75 +bit 09_76 +bit 09_77 +bit 09_78 +bit 09_79 +bit 09_80 +bit 09_81 +bit 09_82 +bit 09_83 +bit 09_84 +bit 09_85 +bit 09_86 +bit 09_87 +bit 09_88 +bit 09_89 +bit 09_90 +bit 09_91 +bit 09_92 +bit 09_93 +bit 09_94 +bit 09_95 +bit 09_96 +bit 09_97 +bit 09_98 +bit 09_99 +bit 10_00 +bit 10_01 +bit 10_02 +bit 10_03 +bit 10_04 +bit 10_05 +bit 10_06 +bit 10_07 +bit 10_08 +bit 10_09 +bit 10_10 +bit 10_100 +bit 10_101 +bit 10_102 +bit 10_103 +bit 10_104 +bit 10_105 +bit 10_106 +bit 10_107 +bit 10_108 +bit 10_109 +bit 10_11 +bit 10_110 +bit 10_111 +bit 10_112 +bit 10_113 +bit 10_114 +bit 10_115 +bit 10_116 +bit 10_117 +bit 10_118 +bit 10_119 +bit 10_12 +bit 10_120 +bit 10_121 +bit 10_122 +bit 10_123 +bit 10_124 +bit 10_125 +bit 10_126 +bit 10_127 +bit 10_128 +bit 10_129 +bit 10_13 +bit 10_130 +bit 10_131 +bit 10_132 +bit 10_133 +bit 10_134 +bit 10_135 +bit 10_136 +bit 10_137 +bit 10_138 +bit 10_139 +bit 10_14 +bit 10_140 +bit 10_141 +bit 10_142 +bit 10_143 +bit 10_144 +bit 10_145 +bit 10_146 +bit 10_147 +bit 10_148 +bit 10_149 +bit 10_15 +bit 10_150 +bit 10_151 +bit 10_152 +bit 10_153 +bit 10_154 +bit 10_155 +bit 10_156 +bit 10_157 +bit 10_158 +bit 10_159 +bit 10_16 +bit 10_160 +bit 10_161 +bit 10_162 +bit 10_163 +bit 10_164 +bit 10_165 +bit 10_166 +bit 10_167 +bit 10_168 +bit 10_169 +bit 10_17 +bit 10_170 +bit 10_171 +bit 10_172 +bit 10_173 +bit 10_174 +bit 10_175 +bit 10_176 +bit 10_177 +bit 10_178 +bit 10_179 +bit 10_18 +bit 10_180 +bit 10_181 +bit 10_182 +bit 10_183 +bit 10_184 +bit 10_185 +bit 10_186 +bit 10_187 +bit 10_188 +bit 10_189 +bit 10_19 +bit 10_190 +bit 10_191 +bit 10_192 +bit 10_193 +bit 10_194 +bit 10_195 +bit 10_196 +bit 10_197 +bit 10_198 +bit 10_199 +bit 10_20 +bit 10_200 +bit 10_201 +bit 10_202 +bit 10_203 +bit 10_204 +bit 10_205 +bit 10_206 +bit 10_207 +bit 10_208 +bit 10_209 +bit 10_21 +bit 10_210 +bit 10_211 +bit 10_212 +bit 10_213 +bit 10_214 +bit 10_215 +bit 10_216 +bit 10_217 +bit 10_218 +bit 10_219 +bit 10_22 +bit 10_220 +bit 10_221 +bit 10_222 +bit 10_223 +bit 10_224 +bit 10_225 +bit 10_226 +bit 10_227 +bit 10_228 +bit 10_229 +bit 10_23 +bit 10_230 +bit 10_231 +bit 10_232 +bit 10_233 +bit 10_234 +bit 10_235 +bit 10_236 +bit 10_237 +bit 10_238 +bit 10_239 +bit 10_24 +bit 10_240 +bit 10_241 +bit 10_242 +bit 10_243 +bit 10_244 +bit 10_245 +bit 10_246 +bit 10_247 +bit 10_248 +bit 10_249 +bit 10_25 +bit 10_250 +bit 10_251 +bit 10_252 +bit 10_253 +bit 10_254 +bit 10_255 +bit 10_256 +bit 10_257 +bit 10_258 +bit 10_259 +bit 10_26 +bit 10_260 +bit 10_261 +bit 10_262 +bit 10_263 +bit 10_264 +bit 10_265 +bit 10_266 +bit 10_267 +bit 10_268 +bit 10_269 +bit 10_27 +bit 10_270 +bit 10_271 +bit 10_272 +bit 10_273 +bit 10_274 +bit 10_275 +bit 10_276 +bit 10_277 +bit 10_278 +bit 10_279 +bit 10_28 +bit 10_280 +bit 10_281 +bit 10_282 +bit 10_283 +bit 10_284 +bit 10_285 +bit 10_286 +bit 10_287 +bit 10_288 +bit 10_289 +bit 10_29 +bit 10_290 +bit 10_291 +bit 10_292 +bit 10_293 +bit 10_294 +bit 10_295 +bit 10_296 +bit 10_297 +bit 10_298 +bit 10_299 +bit 10_30 +bit 10_300 +bit 10_301 +bit 10_302 +bit 10_303 +bit 10_304 +bit 10_305 +bit 10_306 +bit 10_307 +bit 10_308 +bit 10_309 +bit 10_31 +bit 10_310 +bit 10_311 +bit 10_312 +bit 10_313 +bit 10_314 +bit 10_315 +bit 10_316 +bit 10_317 +bit 10_318 +bit 10_319 +bit 10_32 +bit 10_33 +bit 10_34 +bit 10_35 +bit 10_36 +bit 10_37 +bit 10_38 +bit 10_39 +bit 10_40 +bit 10_41 +bit 10_42 +bit 10_43 +bit 10_44 +bit 10_45 +bit 10_46 +bit 10_47 +bit 10_48 +bit 10_49 +bit 10_50 +bit 10_51 +bit 10_52 +bit 10_53 +bit 10_54 +bit 10_55 +bit 10_56 +bit 10_57 +bit 10_58 +bit 10_59 +bit 10_60 +bit 10_61 +bit 10_62 +bit 10_63 +bit 10_64 +bit 10_65 +bit 10_66 +bit 10_67 +bit 10_68 +bit 10_69 +bit 10_70 +bit 10_71 +bit 10_72 +bit 10_73 +bit 10_74 +bit 10_75 +bit 10_76 +bit 10_77 +bit 10_78 +bit 10_79 +bit 10_80 +bit 10_81 +bit 10_82 +bit 10_83 +bit 10_84 +bit 10_85 +bit 10_86 +bit 10_87 +bit 10_88 +bit 10_89 +bit 10_90 +bit 10_91 +bit 10_92 +bit 10_93 +bit 10_94 +bit 10_95 +bit 10_96 +bit 10_97 +bit 10_98 +bit 10_99 +bit 11_00 +bit 11_01 +bit 11_02 +bit 11_03 +bit 11_04 +bit 11_05 +bit 11_06 +bit 11_07 +bit 11_08 +bit 11_09 +bit 11_10 +bit 11_100 +bit 11_101 +bit 11_102 +bit 11_103 +bit 11_104 +bit 11_105 +bit 11_106 +bit 11_107 +bit 11_108 +bit 11_109 +bit 11_11 +bit 11_110 +bit 11_111 +bit 11_112 +bit 11_113 +bit 11_114 +bit 11_115 +bit 11_116 +bit 11_117 +bit 11_118 +bit 11_119 +bit 11_12 +bit 11_120 +bit 11_121 +bit 11_122 +bit 11_123 +bit 11_124 +bit 11_125 +bit 11_126 +bit 11_127 +bit 11_128 +bit 11_129 +bit 11_13 +bit 11_130 +bit 11_131 +bit 11_132 +bit 11_133 +bit 11_134 +bit 11_135 +bit 11_136 +bit 11_137 +bit 11_138 +bit 11_139 +bit 11_14 +bit 11_140 +bit 11_141 +bit 11_142 +bit 11_143 +bit 11_144 +bit 11_145 +bit 11_146 +bit 11_147 +bit 11_148 +bit 11_149 +bit 11_15 +bit 11_150 +bit 11_151 +bit 11_152 +bit 11_153 +bit 11_154 +bit 11_155 +bit 11_156 +bit 11_157 +bit 11_158 +bit 11_159 +bit 11_16 +bit 11_160 +bit 11_161 +bit 11_162 +bit 11_163 +bit 11_164 +bit 11_165 +bit 11_166 +bit 11_167 +bit 11_168 +bit 11_169 +bit 11_17 +bit 11_170 +bit 11_171 +bit 11_172 +bit 11_173 +bit 11_174 +bit 11_175 +bit 11_176 +bit 11_177 +bit 11_178 +bit 11_179 +bit 11_18 +bit 11_180 +bit 11_181 +bit 11_182 +bit 11_183 +bit 11_184 +bit 11_185 +bit 11_186 +bit 11_187 +bit 11_188 +bit 11_189 +bit 11_19 +bit 11_190 +bit 11_191 +bit 11_192 +bit 11_193 +bit 11_194 +bit 11_195 +bit 11_196 +bit 11_197 +bit 11_198 +bit 11_199 +bit 11_20 +bit 11_200 +bit 11_201 +bit 11_202 +bit 11_203 +bit 11_204 +bit 11_205 +bit 11_206 +bit 11_207 +bit 11_208 +bit 11_209 +bit 11_21 +bit 11_210 +bit 11_211 +bit 11_212 +bit 11_213 +bit 11_214 +bit 11_215 +bit 11_216 +bit 11_217 +bit 11_218 +bit 11_219 +bit 11_22 +bit 11_220 +bit 11_221 +bit 11_222 +bit 11_223 +bit 11_224 +bit 11_225 +bit 11_226 +bit 11_227 +bit 11_228 +bit 11_229 +bit 11_23 +bit 11_230 +bit 11_231 +bit 11_232 +bit 11_233 +bit 11_234 +bit 11_235 +bit 11_236 +bit 11_237 +bit 11_238 +bit 11_239 +bit 11_24 +bit 11_240 +bit 11_241 +bit 11_242 +bit 11_243 +bit 11_244 +bit 11_245 +bit 11_246 +bit 11_247 +bit 11_248 +bit 11_249 +bit 11_25 +bit 11_250 +bit 11_251 +bit 11_252 +bit 11_253 +bit 11_254 +bit 11_255 +bit 11_256 +bit 11_257 +bit 11_258 +bit 11_259 +bit 11_26 +bit 11_260 +bit 11_261 +bit 11_262 +bit 11_263 +bit 11_264 +bit 11_265 +bit 11_266 +bit 11_267 +bit 11_268 +bit 11_269 +bit 11_27 +bit 11_270 +bit 11_271 +bit 11_272 +bit 11_273 +bit 11_274 +bit 11_275 +bit 11_276 +bit 11_277 +bit 11_278 +bit 11_279 +bit 11_28 +bit 11_280 +bit 11_281 +bit 11_282 +bit 11_283 +bit 11_284 +bit 11_285 +bit 11_286 +bit 11_287 +bit 11_288 +bit 11_289 +bit 11_29 +bit 11_290 +bit 11_291 +bit 11_292 +bit 11_293 +bit 11_294 +bit 11_295 +bit 11_296 +bit 11_297 +bit 11_298 +bit 11_299 +bit 11_30 +bit 11_300 +bit 11_301 +bit 11_302 +bit 11_303 +bit 11_304 +bit 11_305 +bit 11_306 +bit 11_307 +bit 11_308 +bit 11_309 +bit 11_31 +bit 11_310 +bit 11_311 +bit 11_312 +bit 11_313 +bit 11_314 +bit 11_315 +bit 11_316 +bit 11_317 +bit 11_318 +bit 11_319 +bit 11_32 +bit 11_33 +bit 11_34 +bit 11_35 +bit 11_36 +bit 11_37 +bit 11_38 +bit 11_39 +bit 11_40 +bit 11_41 +bit 11_42 +bit 11_43 +bit 11_44 +bit 11_45 +bit 11_46 +bit 11_47 +bit 11_48 +bit 11_49 +bit 11_50 +bit 11_51 +bit 11_52 +bit 11_53 +bit 11_54 +bit 11_55 +bit 11_56 +bit 11_57 +bit 11_58 +bit 11_59 +bit 11_60 +bit 11_61 +bit 11_62 +bit 11_63 +bit 11_64 +bit 11_65 +bit 11_66 +bit 11_67 +bit 11_68 +bit 11_69 +bit 11_70 +bit 11_71 +bit 11_72 +bit 11_73 +bit 11_74 +bit 11_75 +bit 11_76 +bit 11_77 +bit 11_78 +bit 11_79 +bit 11_80 +bit 11_81 +bit 11_82 +bit 11_83 +bit 11_84 +bit 11_85 +bit 11_86 +bit 11_87 +bit 11_88 +bit 11_89 +bit 11_90 +bit 11_91 +bit 11_92 +bit 11_93 +bit 11_94 +bit 11_95 +bit 11_96 +bit 11_97 +bit 11_98 +bit 11_99 +bit 12_00 +bit 12_01 +bit 12_02 +bit 12_03 +bit 12_04 +bit 12_05 +bit 12_06 +bit 12_07 +bit 12_08 +bit 12_09 +bit 12_10 +bit 12_100 +bit 12_101 +bit 12_102 +bit 12_103 +bit 12_104 +bit 12_105 +bit 12_106 +bit 12_107 +bit 12_108 +bit 12_109 +bit 12_11 +bit 12_110 +bit 12_111 +bit 12_112 +bit 12_113 +bit 12_114 +bit 12_115 +bit 12_116 +bit 12_117 +bit 12_118 +bit 12_119 +bit 12_12 +bit 12_120 +bit 12_121 +bit 12_122 +bit 12_123 +bit 12_124 +bit 12_125 +bit 12_126 +bit 12_127 +bit 12_128 +bit 12_129 +bit 12_13 +bit 12_130 +bit 12_131 +bit 12_132 +bit 12_133 +bit 12_134 +bit 12_135 +bit 12_136 +bit 12_137 +bit 12_138 +bit 12_139 +bit 12_14 +bit 12_140 +bit 12_141 +bit 12_142 +bit 12_143 +bit 12_144 +bit 12_145 +bit 12_146 +bit 12_147 +bit 12_148 +bit 12_149 +bit 12_15 +bit 12_150 +bit 12_151 +bit 12_152 +bit 12_153 +bit 12_154 +bit 12_155 +bit 12_156 +bit 12_157 +bit 12_158 +bit 12_159 +bit 12_16 +bit 12_160 +bit 12_161 +bit 12_162 +bit 12_163 +bit 12_164 +bit 12_165 +bit 12_166 +bit 12_167 +bit 12_168 +bit 12_169 +bit 12_17 +bit 12_170 +bit 12_171 +bit 12_172 +bit 12_173 +bit 12_174 +bit 12_175 +bit 12_176 +bit 12_177 +bit 12_178 +bit 12_179 +bit 12_18 +bit 12_180 +bit 12_181 +bit 12_182 +bit 12_183 +bit 12_184 +bit 12_185 +bit 12_186 +bit 12_187 +bit 12_188 +bit 12_189 +bit 12_19 +bit 12_190 +bit 12_191 +bit 12_192 +bit 12_193 +bit 12_194 +bit 12_195 +bit 12_196 +bit 12_197 +bit 12_198 +bit 12_199 +bit 12_20 +bit 12_200 +bit 12_201 +bit 12_202 +bit 12_203 +bit 12_204 +bit 12_205 +bit 12_206 +bit 12_207 +bit 12_208 +bit 12_209 +bit 12_21 +bit 12_210 +bit 12_211 +bit 12_212 +bit 12_213 +bit 12_214 +bit 12_215 +bit 12_216 +bit 12_217 +bit 12_218 +bit 12_219 +bit 12_22 +bit 12_220 +bit 12_221 +bit 12_222 +bit 12_223 +bit 12_224 +bit 12_225 +bit 12_226 +bit 12_227 +bit 12_228 +bit 12_229 +bit 12_23 +bit 12_230 +bit 12_231 +bit 12_232 +bit 12_233 +bit 12_234 +bit 12_235 +bit 12_236 +bit 12_237 +bit 12_238 +bit 12_239 +bit 12_24 +bit 12_240 +bit 12_241 +bit 12_242 +bit 12_243 +bit 12_244 +bit 12_245 +bit 12_246 +bit 12_247 +bit 12_248 +bit 12_249 +bit 12_25 +bit 12_250 +bit 12_251 +bit 12_252 +bit 12_253 +bit 12_254 +bit 12_255 +bit 12_256 +bit 12_257 +bit 12_258 +bit 12_259 +bit 12_26 +bit 12_260 +bit 12_261 +bit 12_262 +bit 12_263 +bit 12_264 +bit 12_265 +bit 12_266 +bit 12_267 +bit 12_268 +bit 12_269 +bit 12_27 +bit 12_270 +bit 12_271 +bit 12_272 +bit 12_273 +bit 12_274 +bit 12_275 +bit 12_276 +bit 12_277 +bit 12_278 +bit 12_279 +bit 12_28 +bit 12_280 +bit 12_281 +bit 12_282 +bit 12_283 +bit 12_284 +bit 12_285 +bit 12_286 +bit 12_287 +bit 12_288 +bit 12_289 +bit 12_29 +bit 12_290 +bit 12_291 +bit 12_292 +bit 12_293 +bit 12_294 +bit 12_295 +bit 12_296 +bit 12_297 +bit 12_298 +bit 12_299 +bit 12_30 +bit 12_300 +bit 12_301 +bit 12_302 +bit 12_303 +bit 12_304 +bit 12_305 +bit 12_306 +bit 12_307 +bit 12_308 +bit 12_309 +bit 12_31 +bit 12_310 +bit 12_311 +bit 12_312 +bit 12_313 +bit 12_314 +bit 12_315 +bit 12_316 +bit 12_317 +bit 12_318 +bit 12_319 +bit 12_32 +bit 12_33 +bit 12_34 +bit 12_35 +bit 12_36 +bit 12_37 +bit 12_38 +bit 12_39 +bit 12_40 +bit 12_41 +bit 12_42 +bit 12_43 +bit 12_44 +bit 12_45 +bit 12_46 +bit 12_47 +bit 12_48 +bit 12_49 +bit 12_50 +bit 12_51 +bit 12_52 +bit 12_53 +bit 12_54 +bit 12_55 +bit 12_56 +bit 12_57 +bit 12_58 +bit 12_59 +bit 12_60 +bit 12_61 +bit 12_62 +bit 12_63 +bit 12_64 +bit 12_65 +bit 12_66 +bit 12_67 +bit 12_68 +bit 12_69 +bit 12_70 +bit 12_71 +bit 12_72 +bit 12_73 +bit 12_74 +bit 12_75 +bit 12_76 +bit 12_77 +bit 12_78 +bit 12_79 +bit 12_80 +bit 12_81 +bit 12_82 +bit 12_83 +bit 12_84 +bit 12_85 +bit 12_86 +bit 12_87 +bit 12_88 +bit 12_89 +bit 12_90 +bit 12_91 +bit 12_92 +bit 12_93 +bit 12_94 +bit 12_95 +bit 12_96 +bit 12_97 +bit 12_98 +bit 12_99 +bit 13_00 +bit 13_01 +bit 13_02 +bit 13_03 +bit 13_04 +bit 13_05 +bit 13_06 +bit 13_07 +bit 13_08 +bit 13_09 +bit 13_10 +bit 13_100 +bit 13_101 +bit 13_102 +bit 13_103 +bit 13_104 +bit 13_105 +bit 13_106 +bit 13_107 +bit 13_108 +bit 13_109 +bit 13_11 +bit 13_110 +bit 13_111 +bit 13_112 +bit 13_113 +bit 13_114 +bit 13_115 +bit 13_116 +bit 13_117 +bit 13_118 +bit 13_119 +bit 13_12 +bit 13_120 +bit 13_121 +bit 13_122 +bit 13_123 +bit 13_124 +bit 13_125 +bit 13_126 +bit 13_127 +bit 13_128 +bit 13_129 +bit 13_13 +bit 13_130 +bit 13_131 +bit 13_132 +bit 13_133 +bit 13_134 +bit 13_135 +bit 13_136 +bit 13_137 +bit 13_138 +bit 13_139 +bit 13_14 +bit 13_140 +bit 13_141 +bit 13_142 +bit 13_143 +bit 13_144 +bit 13_145 +bit 13_146 +bit 13_147 +bit 13_148 +bit 13_149 +bit 13_15 +bit 13_150 +bit 13_151 +bit 13_152 +bit 13_153 +bit 13_154 +bit 13_155 +bit 13_156 +bit 13_157 +bit 13_158 +bit 13_159 +bit 13_16 +bit 13_160 +bit 13_161 +bit 13_162 +bit 13_163 +bit 13_164 +bit 13_165 +bit 13_166 +bit 13_167 +bit 13_168 +bit 13_169 +bit 13_17 +bit 13_170 +bit 13_171 +bit 13_172 +bit 13_173 +bit 13_174 +bit 13_175 +bit 13_176 +bit 13_177 +bit 13_178 +bit 13_179 +bit 13_18 +bit 13_180 +bit 13_181 +bit 13_182 +bit 13_183 +bit 13_184 +bit 13_185 +bit 13_186 +bit 13_187 +bit 13_188 +bit 13_189 +bit 13_19 +bit 13_190 +bit 13_191 +bit 13_192 +bit 13_193 +bit 13_194 +bit 13_195 +bit 13_196 +bit 13_197 +bit 13_198 +bit 13_199 +bit 13_20 +bit 13_200 +bit 13_201 +bit 13_202 +bit 13_203 +bit 13_204 +bit 13_205 +bit 13_206 +bit 13_207 +bit 13_208 +bit 13_209 +bit 13_21 +bit 13_210 +bit 13_211 +bit 13_212 +bit 13_213 +bit 13_214 +bit 13_215 +bit 13_216 +bit 13_217 +bit 13_218 +bit 13_219 +bit 13_22 +bit 13_220 +bit 13_221 +bit 13_222 +bit 13_223 +bit 13_224 +bit 13_225 +bit 13_226 +bit 13_227 +bit 13_228 +bit 13_229 +bit 13_23 +bit 13_230 +bit 13_231 +bit 13_232 +bit 13_233 +bit 13_234 +bit 13_235 +bit 13_236 +bit 13_237 +bit 13_238 +bit 13_239 +bit 13_24 +bit 13_240 +bit 13_241 +bit 13_242 +bit 13_243 +bit 13_244 +bit 13_245 +bit 13_246 +bit 13_247 +bit 13_248 +bit 13_249 +bit 13_25 +bit 13_250 +bit 13_251 +bit 13_252 +bit 13_253 +bit 13_254 +bit 13_255 +bit 13_256 +bit 13_257 +bit 13_258 +bit 13_259 +bit 13_26 +bit 13_260 +bit 13_261 +bit 13_262 +bit 13_263 +bit 13_264 +bit 13_265 +bit 13_266 +bit 13_267 +bit 13_268 +bit 13_269 +bit 13_27 +bit 13_270 +bit 13_271 +bit 13_272 +bit 13_273 +bit 13_274 +bit 13_275 +bit 13_276 +bit 13_277 +bit 13_278 +bit 13_279 +bit 13_28 +bit 13_280 +bit 13_281 +bit 13_282 +bit 13_283 +bit 13_284 +bit 13_285 +bit 13_286 +bit 13_287 +bit 13_288 +bit 13_289 +bit 13_29 +bit 13_290 +bit 13_291 +bit 13_292 +bit 13_293 +bit 13_294 +bit 13_295 +bit 13_296 +bit 13_297 +bit 13_298 +bit 13_299 +bit 13_30 +bit 13_300 +bit 13_301 +bit 13_302 +bit 13_303 +bit 13_304 +bit 13_305 +bit 13_306 +bit 13_307 +bit 13_308 +bit 13_309 +bit 13_31 +bit 13_310 +bit 13_311 +bit 13_312 +bit 13_313 +bit 13_314 +bit 13_315 +bit 13_316 +bit 13_317 +bit 13_318 +bit 13_319 +bit 13_32 +bit 13_33 +bit 13_34 +bit 13_35 +bit 13_36 +bit 13_37 +bit 13_38 +bit 13_39 +bit 13_40 +bit 13_41 +bit 13_42 +bit 13_43 +bit 13_44 +bit 13_45 +bit 13_46 +bit 13_47 +bit 13_48 +bit 13_49 +bit 13_50 +bit 13_51 +bit 13_52 +bit 13_53 +bit 13_54 +bit 13_55 +bit 13_56 +bit 13_57 +bit 13_58 +bit 13_59 +bit 13_60 +bit 13_61 +bit 13_62 +bit 13_63 +bit 13_64 +bit 13_65 +bit 13_66 +bit 13_67 +bit 13_68 +bit 13_69 +bit 13_70 +bit 13_71 +bit 13_72 +bit 13_73 +bit 13_74 +bit 13_75 +bit 13_76 +bit 13_77 +bit 13_78 +bit 13_79 +bit 13_80 +bit 13_81 +bit 13_82 +bit 13_83 +bit 13_84 +bit 13_85 +bit 13_86 +bit 13_87 +bit 13_88 +bit 13_89 +bit 13_90 +bit 13_91 +bit 13_92 +bit 13_93 +bit 13_94 +bit 13_95 +bit 13_96 +bit 13_97 +bit 13_98 +bit 13_99 +bit 14_00 +bit 14_01 +bit 14_02 +bit 14_03 +bit 14_04 +bit 14_05 +bit 14_06 +bit 14_07 +bit 14_08 +bit 14_09 +bit 14_10 +bit 14_100 +bit 14_101 +bit 14_102 +bit 14_103 +bit 14_104 +bit 14_105 +bit 14_106 +bit 14_107 +bit 14_108 +bit 14_109 +bit 14_11 +bit 14_110 +bit 14_111 +bit 14_112 +bit 14_113 +bit 14_114 +bit 14_115 +bit 14_116 +bit 14_117 +bit 14_118 +bit 14_119 +bit 14_12 +bit 14_120 +bit 14_121 +bit 14_122 +bit 14_123 +bit 14_124 +bit 14_125 +bit 14_126 +bit 14_127 +bit 14_128 +bit 14_129 +bit 14_13 +bit 14_130 +bit 14_131 +bit 14_132 +bit 14_133 +bit 14_134 +bit 14_135 +bit 14_136 +bit 14_137 +bit 14_138 +bit 14_139 +bit 14_14 +bit 14_140 +bit 14_141 +bit 14_142 +bit 14_143 +bit 14_144 +bit 14_145 +bit 14_146 +bit 14_147 +bit 14_148 +bit 14_149 +bit 14_15 +bit 14_150 +bit 14_151 +bit 14_152 +bit 14_153 +bit 14_154 +bit 14_155 +bit 14_156 +bit 14_157 +bit 14_158 +bit 14_159 +bit 14_16 +bit 14_160 +bit 14_161 +bit 14_162 +bit 14_163 +bit 14_164 +bit 14_165 +bit 14_166 +bit 14_167 +bit 14_168 +bit 14_169 +bit 14_17 +bit 14_170 +bit 14_171 +bit 14_172 +bit 14_173 +bit 14_174 +bit 14_175 +bit 14_176 +bit 14_177 +bit 14_178 +bit 14_179 +bit 14_18 +bit 14_180 +bit 14_181 +bit 14_182 +bit 14_183 +bit 14_184 +bit 14_185 +bit 14_186 +bit 14_187 +bit 14_188 +bit 14_189 +bit 14_19 +bit 14_190 +bit 14_191 +bit 14_192 +bit 14_193 +bit 14_194 +bit 14_195 +bit 14_196 +bit 14_197 +bit 14_198 +bit 14_199 +bit 14_20 +bit 14_200 +bit 14_201 +bit 14_202 +bit 14_203 +bit 14_204 +bit 14_205 +bit 14_206 +bit 14_207 +bit 14_208 +bit 14_209 +bit 14_21 +bit 14_210 +bit 14_211 +bit 14_212 +bit 14_213 +bit 14_214 +bit 14_215 +bit 14_216 +bit 14_217 +bit 14_218 +bit 14_219 +bit 14_22 +bit 14_220 +bit 14_221 +bit 14_222 +bit 14_223 +bit 14_224 +bit 14_225 +bit 14_226 +bit 14_227 +bit 14_228 +bit 14_229 +bit 14_23 +bit 14_230 +bit 14_231 +bit 14_232 +bit 14_233 +bit 14_234 +bit 14_235 +bit 14_236 +bit 14_237 +bit 14_238 +bit 14_239 +bit 14_24 +bit 14_240 +bit 14_241 +bit 14_242 +bit 14_243 +bit 14_244 +bit 14_245 +bit 14_246 +bit 14_247 +bit 14_248 +bit 14_249 +bit 14_25 +bit 14_250 +bit 14_251 +bit 14_252 +bit 14_253 +bit 14_254 +bit 14_255 +bit 14_256 +bit 14_257 +bit 14_258 +bit 14_259 +bit 14_26 +bit 14_260 +bit 14_261 +bit 14_262 +bit 14_263 +bit 14_264 +bit 14_265 +bit 14_266 +bit 14_267 +bit 14_268 +bit 14_269 +bit 14_27 +bit 14_270 +bit 14_271 +bit 14_272 +bit 14_273 +bit 14_274 +bit 14_275 +bit 14_276 +bit 14_277 +bit 14_278 +bit 14_279 +bit 14_28 +bit 14_280 +bit 14_281 +bit 14_282 +bit 14_283 +bit 14_284 +bit 14_285 +bit 14_286 +bit 14_287 +bit 14_288 +bit 14_289 +bit 14_29 +bit 14_290 +bit 14_291 +bit 14_292 +bit 14_293 +bit 14_294 +bit 14_295 +bit 14_296 +bit 14_297 +bit 14_298 +bit 14_299 +bit 14_30 +bit 14_300 +bit 14_301 +bit 14_302 +bit 14_303 +bit 14_304 +bit 14_305 +bit 14_306 +bit 14_307 +bit 14_308 +bit 14_309 +bit 14_31 +bit 14_310 +bit 14_311 +bit 14_312 +bit 14_313 +bit 14_314 +bit 14_315 +bit 14_316 +bit 14_317 +bit 14_318 +bit 14_319 +bit 14_32 +bit 14_33 +bit 14_34 +bit 14_35 +bit 14_36 +bit 14_37 +bit 14_38 +bit 14_39 +bit 14_40 +bit 14_41 +bit 14_42 +bit 14_43 +bit 14_44 +bit 14_45 +bit 14_46 +bit 14_47 +bit 14_48 +bit 14_49 +bit 14_50 +bit 14_51 +bit 14_52 +bit 14_53 +bit 14_54 +bit 14_55 +bit 14_56 +bit 14_57 +bit 14_58 +bit 14_59 +bit 14_60 +bit 14_61 +bit 14_62 +bit 14_63 +bit 14_64 +bit 14_65 +bit 14_66 +bit 14_67 +bit 14_68 +bit 14_69 +bit 14_70 +bit 14_71 +bit 14_72 +bit 14_73 +bit 14_74 +bit 14_75 +bit 14_76 +bit 14_77 +bit 14_78 +bit 14_79 +bit 14_80 +bit 14_81 +bit 14_82 +bit 14_83 +bit 14_84 +bit 14_85 +bit 14_86 +bit 14_87 +bit 14_88 +bit 14_89 +bit 14_90 +bit 14_91 +bit 14_92 +bit 14_93 +bit 14_94 +bit 14_95 +bit 14_96 +bit 14_97 +bit 14_98 +bit 14_99 +bit 15_00 +bit 15_01 +bit 15_02 +bit 15_03 +bit 15_04 +bit 15_05 +bit 15_06 +bit 15_07 +bit 15_08 +bit 15_09 +bit 15_10 +bit 15_100 +bit 15_101 +bit 15_102 +bit 15_103 +bit 15_104 +bit 15_105 +bit 15_106 +bit 15_107 +bit 15_108 +bit 15_109 +bit 15_11 +bit 15_110 +bit 15_111 +bit 15_112 +bit 15_113 +bit 15_114 +bit 15_115 +bit 15_116 +bit 15_117 +bit 15_118 +bit 15_119 +bit 15_12 +bit 15_120 +bit 15_121 +bit 15_122 +bit 15_123 +bit 15_124 +bit 15_125 +bit 15_126 +bit 15_127 +bit 15_128 +bit 15_129 +bit 15_13 +bit 15_130 +bit 15_131 +bit 15_132 +bit 15_133 +bit 15_134 +bit 15_135 +bit 15_136 +bit 15_137 +bit 15_138 +bit 15_139 +bit 15_14 +bit 15_140 +bit 15_141 +bit 15_142 +bit 15_143 +bit 15_144 +bit 15_145 +bit 15_146 +bit 15_147 +bit 15_148 +bit 15_149 +bit 15_15 +bit 15_150 +bit 15_151 +bit 15_152 +bit 15_153 +bit 15_154 +bit 15_155 +bit 15_156 +bit 15_157 +bit 15_158 +bit 15_159 +bit 15_16 +bit 15_160 +bit 15_161 +bit 15_162 +bit 15_163 +bit 15_164 +bit 15_165 +bit 15_166 +bit 15_167 +bit 15_168 +bit 15_169 +bit 15_17 +bit 15_170 +bit 15_171 +bit 15_172 +bit 15_173 +bit 15_174 +bit 15_175 +bit 15_176 +bit 15_177 +bit 15_178 +bit 15_179 +bit 15_18 +bit 15_180 +bit 15_181 +bit 15_182 +bit 15_183 +bit 15_184 +bit 15_185 +bit 15_186 +bit 15_187 +bit 15_188 +bit 15_189 +bit 15_19 +bit 15_190 +bit 15_191 +bit 15_192 +bit 15_193 +bit 15_194 +bit 15_195 +bit 15_196 +bit 15_197 +bit 15_198 +bit 15_199 +bit 15_20 +bit 15_200 +bit 15_201 +bit 15_202 +bit 15_203 +bit 15_204 +bit 15_205 +bit 15_206 +bit 15_207 +bit 15_208 +bit 15_209 +bit 15_21 +bit 15_210 +bit 15_211 +bit 15_212 +bit 15_213 +bit 15_214 +bit 15_215 +bit 15_216 +bit 15_217 +bit 15_218 +bit 15_219 +bit 15_22 +bit 15_220 +bit 15_221 +bit 15_222 +bit 15_223 +bit 15_224 +bit 15_225 +bit 15_226 +bit 15_227 +bit 15_228 +bit 15_229 +bit 15_23 +bit 15_230 +bit 15_231 +bit 15_232 +bit 15_233 +bit 15_234 +bit 15_235 +bit 15_236 +bit 15_237 +bit 15_238 +bit 15_239 +bit 15_24 +bit 15_240 +bit 15_241 +bit 15_242 +bit 15_243 +bit 15_244 +bit 15_245 +bit 15_246 +bit 15_247 +bit 15_248 +bit 15_249 +bit 15_25 +bit 15_250 +bit 15_251 +bit 15_252 +bit 15_253 +bit 15_254 +bit 15_255 +bit 15_256 +bit 15_257 +bit 15_258 +bit 15_259 +bit 15_26 +bit 15_260 +bit 15_261 +bit 15_262 +bit 15_263 +bit 15_264 +bit 15_265 +bit 15_266 +bit 15_267 +bit 15_268 +bit 15_269 +bit 15_27 +bit 15_270 +bit 15_271 +bit 15_272 +bit 15_273 +bit 15_274 +bit 15_275 +bit 15_276 +bit 15_277 +bit 15_278 +bit 15_279 +bit 15_28 +bit 15_280 +bit 15_281 +bit 15_282 +bit 15_283 +bit 15_284 +bit 15_285 +bit 15_286 +bit 15_287 +bit 15_288 +bit 15_289 +bit 15_29 +bit 15_290 +bit 15_291 +bit 15_292 +bit 15_293 +bit 15_294 +bit 15_295 +bit 15_296 +bit 15_297 +bit 15_298 +bit 15_299 +bit 15_30 +bit 15_300 +bit 15_301 +bit 15_302 +bit 15_303 +bit 15_304 +bit 15_305 +bit 15_306 +bit 15_307 +bit 15_308 +bit 15_309 +bit 15_31 +bit 15_310 +bit 15_311 +bit 15_312 +bit 15_313 +bit 15_314 +bit 15_315 +bit 15_316 +bit 15_317 +bit 15_318 +bit 15_319 +bit 15_32 +bit 15_33 +bit 15_34 +bit 15_35 +bit 15_36 +bit 15_37 +bit 15_38 +bit 15_39 +bit 15_40 +bit 15_41 +bit 15_42 +bit 15_43 +bit 15_44 +bit 15_45 +bit 15_46 +bit 15_47 +bit 15_48 +bit 15_49 +bit 15_50 +bit 15_51 +bit 15_52 +bit 15_53 +bit 15_54 +bit 15_55 +bit 15_56 +bit 15_57 +bit 15_58 +bit 15_59 +bit 15_60 +bit 15_61 +bit 15_62 +bit 15_63 +bit 15_64 +bit 15_65 +bit 15_66 +bit 15_67 +bit 15_68 +bit 15_69 +bit 15_70 +bit 15_71 +bit 15_72 +bit 15_73 +bit 15_74 +bit 15_75 +bit 15_76 +bit 15_77 +bit 15_78 +bit 15_79 +bit 15_80 +bit 15_81 +bit 15_82 +bit 15_83 +bit 15_84 +bit 15_85 +bit 15_86 +bit 15_87 +bit 15_88 +bit 15_89 +bit 15_90 +bit 15_91 +bit 15_92 +bit 15_93 +bit 15_94 +bit 15_95 +bit 15_96 +bit 15_97 +bit 15_98 +bit 15_99 +bit 16_00 +bit 16_01 +bit 16_02 +bit 16_03 +bit 16_04 +bit 16_05 +bit 16_06 +bit 16_07 +bit 16_08 +bit 16_09 +bit 16_10 +bit 16_100 +bit 16_101 +bit 16_102 +bit 16_103 +bit 16_104 +bit 16_105 +bit 16_106 +bit 16_107 +bit 16_108 +bit 16_109 +bit 16_11 +bit 16_110 +bit 16_111 +bit 16_112 +bit 16_113 +bit 16_114 +bit 16_115 +bit 16_116 +bit 16_117 +bit 16_118 +bit 16_119 +bit 16_12 +bit 16_120 +bit 16_121 +bit 16_122 +bit 16_123 +bit 16_124 +bit 16_125 +bit 16_126 +bit 16_127 +bit 16_128 +bit 16_129 +bit 16_13 +bit 16_130 +bit 16_131 +bit 16_132 +bit 16_133 +bit 16_134 +bit 16_135 +bit 16_136 +bit 16_137 +bit 16_138 +bit 16_139 +bit 16_14 +bit 16_140 +bit 16_141 +bit 16_142 +bit 16_143 +bit 16_144 +bit 16_145 +bit 16_146 +bit 16_147 +bit 16_148 +bit 16_149 +bit 16_15 +bit 16_150 +bit 16_151 +bit 16_152 +bit 16_153 +bit 16_154 +bit 16_155 +bit 16_156 +bit 16_157 +bit 16_158 +bit 16_159 +bit 16_16 +bit 16_160 +bit 16_161 +bit 16_162 +bit 16_163 +bit 16_164 +bit 16_165 +bit 16_166 +bit 16_167 +bit 16_168 +bit 16_169 +bit 16_17 +bit 16_170 +bit 16_171 +bit 16_172 +bit 16_173 +bit 16_174 +bit 16_175 +bit 16_176 +bit 16_177 +bit 16_178 +bit 16_179 +bit 16_18 +bit 16_180 +bit 16_181 +bit 16_182 +bit 16_183 +bit 16_184 +bit 16_185 +bit 16_186 +bit 16_187 +bit 16_188 +bit 16_189 +bit 16_19 +bit 16_190 +bit 16_191 +bit 16_192 +bit 16_193 +bit 16_194 +bit 16_195 +bit 16_196 +bit 16_197 +bit 16_198 +bit 16_199 +bit 16_20 +bit 16_200 +bit 16_201 +bit 16_202 +bit 16_203 +bit 16_204 +bit 16_205 +bit 16_206 +bit 16_207 +bit 16_208 +bit 16_209 +bit 16_21 +bit 16_210 +bit 16_211 +bit 16_212 +bit 16_213 +bit 16_214 +bit 16_215 +bit 16_216 +bit 16_217 +bit 16_218 +bit 16_219 +bit 16_22 +bit 16_220 +bit 16_221 +bit 16_222 +bit 16_223 +bit 16_224 +bit 16_225 +bit 16_226 +bit 16_227 +bit 16_228 +bit 16_229 +bit 16_23 +bit 16_230 +bit 16_231 +bit 16_232 +bit 16_233 +bit 16_234 +bit 16_235 +bit 16_236 +bit 16_237 +bit 16_238 +bit 16_239 +bit 16_24 +bit 16_240 +bit 16_241 +bit 16_242 +bit 16_243 +bit 16_244 +bit 16_245 +bit 16_246 +bit 16_247 +bit 16_248 +bit 16_249 +bit 16_25 +bit 16_250 +bit 16_251 +bit 16_252 +bit 16_253 +bit 16_254 +bit 16_255 +bit 16_256 +bit 16_257 +bit 16_258 +bit 16_259 +bit 16_26 +bit 16_260 +bit 16_261 +bit 16_262 +bit 16_263 +bit 16_264 +bit 16_265 +bit 16_266 +bit 16_267 +bit 16_268 +bit 16_269 +bit 16_27 +bit 16_270 +bit 16_271 +bit 16_272 +bit 16_273 +bit 16_274 +bit 16_275 +bit 16_276 +bit 16_277 +bit 16_278 +bit 16_279 +bit 16_28 +bit 16_280 +bit 16_281 +bit 16_282 +bit 16_283 +bit 16_284 +bit 16_285 +bit 16_286 +bit 16_287 +bit 16_288 +bit 16_289 +bit 16_29 +bit 16_290 +bit 16_291 +bit 16_292 +bit 16_293 +bit 16_294 +bit 16_295 +bit 16_296 +bit 16_297 +bit 16_298 +bit 16_299 +bit 16_30 +bit 16_300 +bit 16_301 +bit 16_302 +bit 16_303 +bit 16_304 +bit 16_305 +bit 16_306 +bit 16_307 +bit 16_308 +bit 16_309 +bit 16_31 +bit 16_310 +bit 16_311 +bit 16_312 +bit 16_313 +bit 16_314 +bit 16_315 +bit 16_316 +bit 16_317 +bit 16_318 +bit 16_319 +bit 16_32 +bit 16_33 +bit 16_34 +bit 16_35 +bit 16_36 +bit 16_37 +bit 16_38 +bit 16_39 +bit 16_40 +bit 16_41 +bit 16_42 +bit 16_43 +bit 16_44 +bit 16_45 +bit 16_46 +bit 16_47 +bit 16_48 +bit 16_49 +bit 16_50 +bit 16_51 +bit 16_52 +bit 16_53 +bit 16_54 +bit 16_55 +bit 16_56 +bit 16_57 +bit 16_58 +bit 16_59 +bit 16_60 +bit 16_61 +bit 16_62 +bit 16_63 +bit 16_64 +bit 16_65 +bit 16_66 +bit 16_67 +bit 16_68 +bit 16_69 +bit 16_70 +bit 16_71 +bit 16_72 +bit 16_73 +bit 16_74 +bit 16_75 +bit 16_76 +bit 16_77 +bit 16_78 +bit 16_79 +bit 16_80 +bit 16_81 +bit 16_82 +bit 16_83 +bit 16_84 +bit 16_85 +bit 16_86 +bit 16_87 +bit 16_88 +bit 16_89 +bit 16_90 +bit 16_91 +bit 16_92 +bit 16_93 +bit 16_94 +bit 16_95 +bit 16_96 +bit 16_97 +bit 16_98 +bit 16_99 +bit 17_00 +bit 17_01 +bit 17_02 +bit 17_03 +bit 17_04 +bit 17_05 +bit 17_06 +bit 17_07 +bit 17_08 +bit 17_09 +bit 17_10 +bit 17_100 +bit 17_101 +bit 17_102 +bit 17_103 +bit 17_104 +bit 17_105 +bit 17_106 +bit 17_107 +bit 17_108 +bit 17_109 +bit 17_11 +bit 17_110 +bit 17_111 +bit 17_112 +bit 17_113 +bit 17_114 +bit 17_115 +bit 17_116 +bit 17_117 +bit 17_118 +bit 17_119 +bit 17_12 +bit 17_120 +bit 17_121 +bit 17_122 +bit 17_123 +bit 17_124 +bit 17_125 +bit 17_126 +bit 17_127 +bit 17_128 +bit 17_129 +bit 17_13 +bit 17_130 +bit 17_131 +bit 17_132 +bit 17_133 +bit 17_134 +bit 17_135 +bit 17_136 +bit 17_137 +bit 17_138 +bit 17_139 +bit 17_14 +bit 17_140 +bit 17_141 +bit 17_142 +bit 17_143 +bit 17_144 +bit 17_145 +bit 17_146 +bit 17_147 +bit 17_148 +bit 17_149 +bit 17_15 +bit 17_150 +bit 17_151 +bit 17_152 +bit 17_153 +bit 17_154 +bit 17_155 +bit 17_156 +bit 17_157 +bit 17_158 +bit 17_159 +bit 17_16 +bit 17_160 +bit 17_161 +bit 17_162 +bit 17_163 +bit 17_164 +bit 17_165 +bit 17_166 +bit 17_167 +bit 17_168 +bit 17_169 +bit 17_17 +bit 17_170 +bit 17_171 +bit 17_172 +bit 17_173 +bit 17_174 +bit 17_175 +bit 17_176 +bit 17_177 +bit 17_178 +bit 17_179 +bit 17_18 +bit 17_180 +bit 17_181 +bit 17_182 +bit 17_183 +bit 17_184 +bit 17_185 +bit 17_186 +bit 17_187 +bit 17_188 +bit 17_189 +bit 17_19 +bit 17_190 +bit 17_191 +bit 17_192 +bit 17_193 +bit 17_194 +bit 17_195 +bit 17_196 +bit 17_197 +bit 17_198 +bit 17_199 +bit 17_20 +bit 17_200 +bit 17_201 +bit 17_202 +bit 17_203 +bit 17_204 +bit 17_205 +bit 17_206 +bit 17_207 +bit 17_208 +bit 17_209 +bit 17_21 +bit 17_210 +bit 17_211 +bit 17_212 +bit 17_213 +bit 17_214 +bit 17_215 +bit 17_216 +bit 17_217 +bit 17_218 +bit 17_219 +bit 17_22 +bit 17_220 +bit 17_221 +bit 17_222 +bit 17_223 +bit 17_224 +bit 17_225 +bit 17_226 +bit 17_227 +bit 17_228 +bit 17_229 +bit 17_23 +bit 17_230 +bit 17_231 +bit 17_232 +bit 17_233 +bit 17_234 +bit 17_235 +bit 17_236 +bit 17_237 +bit 17_238 +bit 17_239 +bit 17_24 +bit 17_240 +bit 17_241 +bit 17_242 +bit 17_243 +bit 17_244 +bit 17_245 +bit 17_246 +bit 17_247 +bit 17_248 +bit 17_249 +bit 17_25 +bit 17_250 +bit 17_251 +bit 17_252 +bit 17_253 +bit 17_254 +bit 17_255 +bit 17_256 +bit 17_257 +bit 17_258 +bit 17_259 +bit 17_26 +bit 17_260 +bit 17_261 +bit 17_262 +bit 17_263 +bit 17_264 +bit 17_265 +bit 17_266 +bit 17_267 +bit 17_268 +bit 17_269 +bit 17_27 +bit 17_270 +bit 17_271 +bit 17_272 +bit 17_273 +bit 17_274 +bit 17_275 +bit 17_276 +bit 17_277 +bit 17_278 +bit 17_279 +bit 17_28 +bit 17_280 +bit 17_281 +bit 17_282 +bit 17_283 +bit 17_284 +bit 17_285 +bit 17_286 +bit 17_287 +bit 17_288 +bit 17_289 +bit 17_29 +bit 17_290 +bit 17_291 +bit 17_292 +bit 17_293 +bit 17_294 +bit 17_295 +bit 17_296 +bit 17_297 +bit 17_298 +bit 17_299 +bit 17_30 +bit 17_300 +bit 17_301 +bit 17_302 +bit 17_303 +bit 17_304 +bit 17_305 +bit 17_306 +bit 17_307 +bit 17_308 +bit 17_309 +bit 17_31 +bit 17_310 +bit 17_311 +bit 17_312 +bit 17_313 +bit 17_314 +bit 17_315 +bit 17_316 +bit 17_317 +bit 17_318 +bit 17_319 +bit 17_32 +bit 17_33 +bit 17_34 +bit 17_35 +bit 17_36 +bit 17_37 +bit 17_38 +bit 17_39 +bit 17_40 +bit 17_41 +bit 17_42 +bit 17_43 +bit 17_44 +bit 17_45 +bit 17_46 +bit 17_47 +bit 17_48 +bit 17_49 +bit 17_50 +bit 17_51 +bit 17_52 +bit 17_53 +bit 17_54 +bit 17_55 +bit 17_56 +bit 17_57 +bit 17_58 +bit 17_59 +bit 17_60 +bit 17_61 +bit 17_62 +bit 17_63 +bit 17_64 +bit 17_65 +bit 17_66 +bit 17_67 +bit 17_68 +bit 17_69 +bit 17_70 +bit 17_71 +bit 17_72 +bit 17_73 +bit 17_74 +bit 17_75 +bit 17_76 +bit 17_77 +bit 17_78 +bit 17_79 +bit 17_80 +bit 17_81 +bit 17_82 +bit 17_83 +bit 17_84 +bit 17_85 +bit 17_86 +bit 17_87 +bit 17_88 +bit 17_89 +bit 17_90 +bit 17_91 +bit 17_92 +bit 17_93 +bit 17_94 +bit 17_95 +bit 17_96 +bit 17_97 +bit 17_98 +bit 17_99 +bit 18_00 +bit 18_01 +bit 18_02 +bit 18_03 +bit 18_04 +bit 18_05 +bit 18_06 +bit 18_07 +bit 18_08 +bit 18_09 +bit 18_10 +bit 18_100 +bit 18_101 +bit 18_102 +bit 18_103 +bit 18_104 +bit 18_105 +bit 18_106 +bit 18_107 +bit 18_108 +bit 18_109 +bit 18_11 +bit 18_110 +bit 18_111 +bit 18_112 +bit 18_113 +bit 18_114 +bit 18_115 +bit 18_116 +bit 18_117 +bit 18_118 +bit 18_119 +bit 18_12 +bit 18_120 +bit 18_121 +bit 18_122 +bit 18_123 +bit 18_124 +bit 18_125 +bit 18_126 +bit 18_127 +bit 18_128 +bit 18_129 +bit 18_13 +bit 18_130 +bit 18_131 +bit 18_132 +bit 18_133 +bit 18_134 +bit 18_135 +bit 18_136 +bit 18_137 +bit 18_138 +bit 18_139 +bit 18_14 +bit 18_140 +bit 18_141 +bit 18_142 +bit 18_143 +bit 18_144 +bit 18_145 +bit 18_146 +bit 18_147 +bit 18_148 +bit 18_149 +bit 18_15 +bit 18_150 +bit 18_151 +bit 18_152 +bit 18_153 +bit 18_154 +bit 18_155 +bit 18_156 +bit 18_157 +bit 18_158 +bit 18_159 +bit 18_16 +bit 18_160 +bit 18_161 +bit 18_162 +bit 18_163 +bit 18_164 +bit 18_165 +bit 18_166 +bit 18_167 +bit 18_168 +bit 18_169 +bit 18_17 +bit 18_170 +bit 18_171 +bit 18_172 +bit 18_173 +bit 18_174 +bit 18_175 +bit 18_176 +bit 18_177 +bit 18_178 +bit 18_179 +bit 18_18 +bit 18_180 +bit 18_181 +bit 18_182 +bit 18_183 +bit 18_184 +bit 18_185 +bit 18_186 +bit 18_187 +bit 18_188 +bit 18_189 +bit 18_19 +bit 18_190 +bit 18_191 +bit 18_192 +bit 18_193 +bit 18_194 +bit 18_195 +bit 18_196 +bit 18_197 +bit 18_198 +bit 18_199 +bit 18_20 +bit 18_200 +bit 18_201 +bit 18_202 +bit 18_203 +bit 18_204 +bit 18_205 +bit 18_206 +bit 18_207 +bit 18_208 +bit 18_209 +bit 18_21 +bit 18_210 +bit 18_211 +bit 18_212 +bit 18_213 +bit 18_214 +bit 18_215 +bit 18_216 +bit 18_217 +bit 18_218 +bit 18_219 +bit 18_22 +bit 18_220 +bit 18_221 +bit 18_222 +bit 18_223 +bit 18_224 +bit 18_225 +bit 18_226 +bit 18_227 +bit 18_228 +bit 18_229 +bit 18_23 +bit 18_230 +bit 18_231 +bit 18_232 +bit 18_233 +bit 18_234 +bit 18_235 +bit 18_236 +bit 18_237 +bit 18_238 +bit 18_239 +bit 18_24 +bit 18_240 +bit 18_241 +bit 18_242 +bit 18_243 +bit 18_244 +bit 18_245 +bit 18_246 +bit 18_247 +bit 18_248 +bit 18_249 +bit 18_25 +bit 18_250 +bit 18_251 +bit 18_252 +bit 18_253 +bit 18_254 +bit 18_255 +bit 18_256 +bit 18_257 +bit 18_258 +bit 18_259 +bit 18_26 +bit 18_260 +bit 18_261 +bit 18_262 +bit 18_263 +bit 18_264 +bit 18_265 +bit 18_266 +bit 18_267 +bit 18_268 +bit 18_269 +bit 18_27 +bit 18_270 +bit 18_271 +bit 18_272 +bit 18_273 +bit 18_274 +bit 18_275 +bit 18_276 +bit 18_277 +bit 18_278 +bit 18_279 +bit 18_28 +bit 18_280 +bit 18_281 +bit 18_282 +bit 18_283 +bit 18_284 +bit 18_285 +bit 18_286 +bit 18_287 +bit 18_288 +bit 18_289 +bit 18_29 +bit 18_290 +bit 18_291 +bit 18_292 +bit 18_293 +bit 18_294 +bit 18_295 +bit 18_296 +bit 18_297 +bit 18_298 +bit 18_299 +bit 18_30 +bit 18_300 +bit 18_301 +bit 18_302 +bit 18_303 +bit 18_304 +bit 18_305 +bit 18_306 +bit 18_307 +bit 18_308 +bit 18_309 +bit 18_31 +bit 18_310 +bit 18_311 +bit 18_312 +bit 18_313 +bit 18_314 +bit 18_315 +bit 18_316 +bit 18_317 +bit 18_318 +bit 18_319 +bit 18_32 +bit 18_33 +bit 18_34 +bit 18_35 +bit 18_36 +bit 18_37 +bit 18_38 +bit 18_39 +bit 18_40 +bit 18_41 +bit 18_42 +bit 18_43 +bit 18_44 +bit 18_45 +bit 18_46 +bit 18_47 +bit 18_48 +bit 18_49 +bit 18_50 +bit 18_51 +bit 18_52 +bit 18_53 +bit 18_54 +bit 18_55 +bit 18_56 +bit 18_57 +bit 18_58 +bit 18_59 +bit 18_60 +bit 18_61 +bit 18_62 +bit 18_63 +bit 18_64 +bit 18_65 +bit 18_66 +bit 18_67 +bit 18_68 +bit 18_69 +bit 18_70 +bit 18_71 +bit 18_72 +bit 18_73 +bit 18_74 +bit 18_75 +bit 18_76 +bit 18_77 +bit 18_78 +bit 18_79 +bit 18_80 +bit 18_81 +bit 18_82 +bit 18_83 +bit 18_84 +bit 18_85 +bit 18_86 +bit 18_87 +bit 18_88 +bit 18_89 +bit 18_90 +bit 18_91 +bit 18_92 +bit 18_93 +bit 18_94 +bit 18_95 +bit 18_96 +bit 18_97 +bit 18_98 +bit 18_99 +bit 19_00 +bit 19_01 +bit 19_02 +bit 19_03 +bit 19_04 +bit 19_05 +bit 19_06 +bit 19_07 +bit 19_08 +bit 19_09 +bit 19_10 +bit 19_100 +bit 19_101 +bit 19_102 +bit 19_103 +bit 19_104 +bit 19_105 +bit 19_106 +bit 19_107 +bit 19_108 +bit 19_109 +bit 19_11 +bit 19_110 +bit 19_111 +bit 19_112 +bit 19_113 +bit 19_114 +bit 19_115 +bit 19_116 +bit 19_117 +bit 19_118 +bit 19_119 +bit 19_12 +bit 19_120 +bit 19_121 +bit 19_122 +bit 19_123 +bit 19_124 +bit 19_125 +bit 19_126 +bit 19_127 +bit 19_128 +bit 19_129 +bit 19_13 +bit 19_130 +bit 19_131 +bit 19_132 +bit 19_133 +bit 19_134 +bit 19_135 +bit 19_136 +bit 19_137 +bit 19_138 +bit 19_139 +bit 19_14 +bit 19_140 +bit 19_141 +bit 19_142 +bit 19_143 +bit 19_144 +bit 19_145 +bit 19_146 +bit 19_147 +bit 19_148 +bit 19_149 +bit 19_15 +bit 19_150 +bit 19_151 +bit 19_152 +bit 19_153 +bit 19_154 +bit 19_155 +bit 19_156 +bit 19_157 +bit 19_158 +bit 19_159 +bit 19_16 +bit 19_160 +bit 19_161 +bit 19_162 +bit 19_163 +bit 19_164 +bit 19_165 +bit 19_166 +bit 19_167 +bit 19_168 +bit 19_169 +bit 19_17 +bit 19_170 +bit 19_171 +bit 19_172 +bit 19_173 +bit 19_174 +bit 19_175 +bit 19_176 +bit 19_177 +bit 19_178 +bit 19_179 +bit 19_18 +bit 19_180 +bit 19_181 +bit 19_182 +bit 19_183 +bit 19_184 +bit 19_185 +bit 19_186 +bit 19_187 +bit 19_188 +bit 19_189 +bit 19_19 +bit 19_190 +bit 19_191 +bit 19_192 +bit 19_193 +bit 19_194 +bit 19_195 +bit 19_196 +bit 19_197 +bit 19_198 +bit 19_199 +bit 19_20 +bit 19_200 +bit 19_201 +bit 19_202 +bit 19_203 +bit 19_204 +bit 19_205 +bit 19_206 +bit 19_207 +bit 19_208 +bit 19_209 +bit 19_21 +bit 19_210 +bit 19_211 +bit 19_212 +bit 19_213 +bit 19_214 +bit 19_215 +bit 19_216 +bit 19_217 +bit 19_218 +bit 19_219 +bit 19_22 +bit 19_220 +bit 19_221 +bit 19_222 +bit 19_223 +bit 19_224 +bit 19_225 +bit 19_226 +bit 19_227 +bit 19_228 +bit 19_229 +bit 19_23 +bit 19_230 +bit 19_231 +bit 19_232 +bit 19_233 +bit 19_234 +bit 19_235 +bit 19_236 +bit 19_237 +bit 19_238 +bit 19_239 +bit 19_24 +bit 19_240 +bit 19_241 +bit 19_242 +bit 19_243 +bit 19_244 +bit 19_245 +bit 19_246 +bit 19_247 +bit 19_248 +bit 19_249 +bit 19_25 +bit 19_250 +bit 19_251 +bit 19_252 +bit 19_253 +bit 19_254 +bit 19_255 +bit 19_256 +bit 19_257 +bit 19_258 +bit 19_259 +bit 19_26 +bit 19_260 +bit 19_261 +bit 19_262 +bit 19_263 +bit 19_264 +bit 19_265 +bit 19_266 +bit 19_267 +bit 19_268 +bit 19_269 +bit 19_27 +bit 19_270 +bit 19_271 +bit 19_272 +bit 19_273 +bit 19_274 +bit 19_275 +bit 19_276 +bit 19_277 +bit 19_278 +bit 19_279 +bit 19_28 +bit 19_280 +bit 19_281 +bit 19_282 +bit 19_283 +bit 19_284 +bit 19_285 +bit 19_286 +bit 19_287 +bit 19_288 +bit 19_289 +bit 19_29 +bit 19_290 +bit 19_291 +bit 19_292 +bit 19_293 +bit 19_294 +bit 19_295 +bit 19_296 +bit 19_297 +bit 19_298 +bit 19_299 +bit 19_30 +bit 19_300 +bit 19_301 +bit 19_302 +bit 19_303 +bit 19_304 +bit 19_305 +bit 19_306 +bit 19_307 +bit 19_308 +bit 19_309 +bit 19_31 +bit 19_310 +bit 19_311 +bit 19_312 +bit 19_313 +bit 19_314 +bit 19_315 +bit 19_316 +bit 19_317 +bit 19_318 +bit 19_319 +bit 19_32 +bit 19_33 +bit 19_34 +bit 19_35 +bit 19_36 +bit 19_37 +bit 19_38 +bit 19_39 +bit 19_40 +bit 19_41 +bit 19_42 +bit 19_43 +bit 19_44 +bit 19_45 +bit 19_46 +bit 19_47 +bit 19_48 +bit 19_49 +bit 19_50 +bit 19_51 +bit 19_52 +bit 19_53 +bit 19_54 +bit 19_55 +bit 19_56 +bit 19_57 +bit 19_58 +bit 19_59 +bit 19_60 +bit 19_61 +bit 19_62 +bit 19_63 +bit 19_64 +bit 19_65 +bit 19_66 +bit 19_67 +bit 19_68 +bit 19_69 +bit 19_70 +bit 19_71 +bit 19_72 +bit 19_73 +bit 19_74 +bit 19_75 +bit 19_76 +bit 19_77 +bit 19_78 +bit 19_79 +bit 19_80 +bit 19_81 +bit 19_82 +bit 19_83 +bit 19_84 +bit 19_85 +bit 19_86 +bit 19_87 +bit 19_88 +bit 19_89 +bit 19_90 +bit 19_91 +bit 19_92 +bit 19_93 +bit 19_94 +bit 19_95 +bit 19_96 +bit 19_97 +bit 19_98 +bit 19_99 +bit 20_00 +bit 20_01 +bit 20_02 +bit 20_03 +bit 20_04 +bit 20_05 +bit 20_06 +bit 20_07 +bit 20_08 +bit 20_09 +bit 20_10 +bit 20_100 +bit 20_101 +bit 20_102 +bit 20_103 +bit 20_104 +bit 20_105 +bit 20_106 +bit 20_107 +bit 20_108 +bit 20_109 +bit 20_11 +bit 20_110 +bit 20_111 +bit 20_112 +bit 20_113 +bit 20_114 +bit 20_115 +bit 20_116 +bit 20_117 +bit 20_118 +bit 20_119 +bit 20_12 +bit 20_120 +bit 20_121 +bit 20_122 +bit 20_123 +bit 20_124 +bit 20_125 +bit 20_126 +bit 20_127 +bit 20_128 +bit 20_129 +bit 20_13 +bit 20_130 +bit 20_131 +bit 20_132 +bit 20_133 +bit 20_134 +bit 20_135 +bit 20_136 +bit 20_137 +bit 20_138 +bit 20_139 +bit 20_14 +bit 20_140 +bit 20_141 +bit 20_142 +bit 20_143 +bit 20_144 +bit 20_145 +bit 20_146 +bit 20_147 +bit 20_148 +bit 20_149 +bit 20_15 +bit 20_150 +bit 20_151 +bit 20_152 +bit 20_153 +bit 20_154 +bit 20_155 +bit 20_156 +bit 20_157 +bit 20_158 +bit 20_159 +bit 20_16 +bit 20_160 +bit 20_161 +bit 20_162 +bit 20_163 +bit 20_164 +bit 20_165 +bit 20_166 +bit 20_167 +bit 20_168 +bit 20_169 +bit 20_17 +bit 20_170 +bit 20_171 +bit 20_172 +bit 20_173 +bit 20_174 +bit 20_175 +bit 20_176 +bit 20_177 +bit 20_178 +bit 20_179 +bit 20_18 +bit 20_180 +bit 20_181 +bit 20_182 +bit 20_183 +bit 20_184 +bit 20_185 +bit 20_186 +bit 20_187 +bit 20_188 +bit 20_189 +bit 20_19 +bit 20_190 +bit 20_191 +bit 20_192 +bit 20_193 +bit 20_194 +bit 20_195 +bit 20_196 +bit 20_197 +bit 20_198 +bit 20_199 +bit 20_20 +bit 20_200 +bit 20_201 +bit 20_202 +bit 20_203 +bit 20_204 +bit 20_205 +bit 20_206 +bit 20_207 +bit 20_208 +bit 20_209 +bit 20_21 +bit 20_210 +bit 20_211 +bit 20_212 +bit 20_213 +bit 20_214 +bit 20_215 +bit 20_216 +bit 20_217 +bit 20_218 +bit 20_219 +bit 20_22 +bit 20_220 +bit 20_221 +bit 20_222 +bit 20_223 +bit 20_224 +bit 20_225 +bit 20_226 +bit 20_227 +bit 20_228 +bit 20_229 +bit 20_23 +bit 20_230 +bit 20_231 +bit 20_232 +bit 20_233 +bit 20_234 +bit 20_235 +bit 20_236 +bit 20_237 +bit 20_238 +bit 20_239 +bit 20_24 +bit 20_240 +bit 20_241 +bit 20_242 +bit 20_243 +bit 20_244 +bit 20_245 +bit 20_246 +bit 20_247 +bit 20_248 +bit 20_249 +bit 20_25 +bit 20_250 +bit 20_251 +bit 20_252 +bit 20_253 +bit 20_254 +bit 20_255 +bit 20_256 +bit 20_257 +bit 20_258 +bit 20_259 +bit 20_26 +bit 20_260 +bit 20_261 +bit 20_262 +bit 20_263 +bit 20_264 +bit 20_265 +bit 20_266 +bit 20_267 +bit 20_268 +bit 20_269 +bit 20_27 +bit 20_270 +bit 20_271 +bit 20_272 +bit 20_273 +bit 20_274 +bit 20_275 +bit 20_276 +bit 20_277 +bit 20_278 +bit 20_279 +bit 20_28 +bit 20_280 +bit 20_281 +bit 20_282 +bit 20_283 +bit 20_284 +bit 20_285 +bit 20_286 +bit 20_287 +bit 20_288 +bit 20_289 +bit 20_29 +bit 20_290 +bit 20_291 +bit 20_292 +bit 20_293 +bit 20_294 +bit 20_295 +bit 20_296 +bit 20_297 +bit 20_298 +bit 20_299 +bit 20_30 +bit 20_300 +bit 20_301 +bit 20_302 +bit 20_303 +bit 20_304 +bit 20_305 +bit 20_306 +bit 20_307 +bit 20_308 +bit 20_309 +bit 20_31 +bit 20_310 +bit 20_311 +bit 20_312 +bit 20_313 +bit 20_314 +bit 20_315 +bit 20_316 +bit 20_317 +bit 20_318 +bit 20_319 +bit 20_32 +bit 20_33 +bit 20_34 +bit 20_35 +bit 20_36 +bit 20_37 +bit 20_38 +bit 20_39 +bit 20_40 +bit 20_41 +bit 20_42 +bit 20_43 +bit 20_44 +bit 20_45 +bit 20_46 +bit 20_47 +bit 20_48 +bit 20_49 +bit 20_50 +bit 20_51 +bit 20_52 +bit 20_53 +bit 20_54 +bit 20_55 +bit 20_56 +bit 20_57 +bit 20_58 +bit 20_59 +bit 20_60 +bit 20_61 +bit 20_62 +bit 20_63 +bit 20_64 +bit 20_65 +bit 20_66 +bit 20_67 +bit 20_68 +bit 20_69 +bit 20_70 +bit 20_71 +bit 20_72 +bit 20_73 +bit 20_74 +bit 20_75 +bit 20_76 +bit 20_77 +bit 20_78 +bit 20_79 +bit 20_80 +bit 20_81 +bit 20_82 +bit 20_83 +bit 20_84 +bit 20_85 +bit 20_86 +bit 20_87 +bit 20_88 +bit 20_89 +bit 20_90 +bit 20_91 +bit 20_92 +bit 20_93 +bit 20_94 +bit 20_95 +bit 20_96 +bit 20_97 +bit 20_98 +bit 20_99 +bit 21_00 +bit 21_01 +bit 21_02 +bit 21_03 +bit 21_04 +bit 21_05 +bit 21_06 +bit 21_07 +bit 21_08 +bit 21_09 +bit 21_10 +bit 21_100 +bit 21_101 +bit 21_102 +bit 21_103 +bit 21_104 +bit 21_105 +bit 21_106 +bit 21_107 +bit 21_108 +bit 21_109 +bit 21_11 +bit 21_110 +bit 21_111 +bit 21_112 +bit 21_113 +bit 21_114 +bit 21_115 +bit 21_116 +bit 21_117 +bit 21_118 +bit 21_119 +bit 21_12 +bit 21_120 +bit 21_121 +bit 21_122 +bit 21_123 +bit 21_124 +bit 21_125 +bit 21_126 +bit 21_127 +bit 21_128 +bit 21_129 +bit 21_13 +bit 21_130 +bit 21_131 +bit 21_132 +bit 21_133 +bit 21_134 +bit 21_135 +bit 21_136 +bit 21_137 +bit 21_138 +bit 21_139 +bit 21_14 +bit 21_140 +bit 21_141 +bit 21_142 +bit 21_143 +bit 21_144 +bit 21_145 +bit 21_146 +bit 21_147 +bit 21_148 +bit 21_149 +bit 21_15 +bit 21_150 +bit 21_151 +bit 21_152 +bit 21_153 +bit 21_154 +bit 21_155 +bit 21_156 +bit 21_157 +bit 21_158 +bit 21_159 +bit 21_16 +bit 21_160 +bit 21_161 +bit 21_162 +bit 21_163 +bit 21_164 +bit 21_165 +bit 21_166 +bit 21_167 +bit 21_168 +bit 21_169 +bit 21_17 +bit 21_170 +bit 21_171 +bit 21_172 +bit 21_173 +bit 21_174 +bit 21_175 +bit 21_176 +bit 21_177 +bit 21_178 +bit 21_179 +bit 21_18 +bit 21_180 +bit 21_181 +bit 21_182 +bit 21_183 +bit 21_184 +bit 21_185 +bit 21_186 +bit 21_187 +bit 21_188 +bit 21_189 +bit 21_19 +bit 21_190 +bit 21_191 +bit 21_192 +bit 21_193 +bit 21_194 +bit 21_195 +bit 21_196 +bit 21_197 +bit 21_198 +bit 21_199 +bit 21_20 +bit 21_200 +bit 21_201 +bit 21_202 +bit 21_203 +bit 21_204 +bit 21_205 +bit 21_206 +bit 21_207 +bit 21_208 +bit 21_209 +bit 21_21 +bit 21_210 +bit 21_211 +bit 21_212 +bit 21_213 +bit 21_214 +bit 21_215 +bit 21_216 +bit 21_217 +bit 21_218 +bit 21_219 +bit 21_22 +bit 21_220 +bit 21_221 +bit 21_222 +bit 21_223 +bit 21_224 +bit 21_225 +bit 21_226 +bit 21_227 +bit 21_228 +bit 21_229 +bit 21_23 +bit 21_230 +bit 21_231 +bit 21_232 +bit 21_233 +bit 21_234 +bit 21_235 +bit 21_236 +bit 21_237 +bit 21_238 +bit 21_239 +bit 21_24 +bit 21_240 +bit 21_241 +bit 21_242 +bit 21_243 +bit 21_244 +bit 21_245 +bit 21_246 +bit 21_247 +bit 21_248 +bit 21_249 +bit 21_25 +bit 21_250 +bit 21_251 +bit 21_252 +bit 21_253 +bit 21_254 +bit 21_255 +bit 21_256 +bit 21_257 +bit 21_258 +bit 21_259 +bit 21_26 +bit 21_260 +bit 21_261 +bit 21_262 +bit 21_263 +bit 21_264 +bit 21_265 +bit 21_266 +bit 21_267 +bit 21_268 +bit 21_269 +bit 21_27 +bit 21_270 +bit 21_271 +bit 21_272 +bit 21_273 +bit 21_274 +bit 21_275 +bit 21_276 +bit 21_277 +bit 21_278 +bit 21_279 +bit 21_28 +bit 21_280 +bit 21_281 +bit 21_282 +bit 21_283 +bit 21_284 +bit 21_285 +bit 21_286 +bit 21_287 +bit 21_288 +bit 21_289 +bit 21_29 +bit 21_290 +bit 21_291 +bit 21_292 +bit 21_293 +bit 21_294 +bit 21_295 +bit 21_296 +bit 21_297 +bit 21_298 +bit 21_299 +bit 21_30 +bit 21_300 +bit 21_301 +bit 21_302 +bit 21_303 +bit 21_304 +bit 21_305 +bit 21_306 +bit 21_307 +bit 21_308 +bit 21_309 +bit 21_31 +bit 21_310 +bit 21_311 +bit 21_312 +bit 21_313 +bit 21_314 +bit 21_315 +bit 21_316 +bit 21_317 +bit 21_318 +bit 21_319 +bit 21_32 +bit 21_33 +bit 21_34 +bit 21_35 +bit 21_36 +bit 21_37 +bit 21_38 +bit 21_39 +bit 21_40 +bit 21_41 +bit 21_42 +bit 21_43 +bit 21_44 +bit 21_45 +bit 21_46 +bit 21_47 +bit 21_48 +bit 21_49 +bit 21_50 +bit 21_51 +bit 21_52 +bit 21_53 +bit 21_54 +bit 21_55 +bit 21_56 +bit 21_57 +bit 21_58 +bit 21_59 +bit 21_60 +bit 21_61 +bit 21_62 +bit 21_63 +bit 21_64 +bit 21_65 +bit 21_66 +bit 21_67 +bit 21_68 +bit 21_69 +bit 21_70 +bit 21_71 +bit 21_72 +bit 21_73 +bit 21_74 +bit 21_75 +bit 21_76 +bit 21_77 +bit 21_78 +bit 21_79 +bit 21_80 +bit 21_81 +bit 21_82 +bit 21_83 +bit 21_84 +bit 21_85 +bit 21_86 +bit 21_87 +bit 21_88 +bit 21_89 +bit 21_90 +bit 21_91 +bit 21_92 +bit 21_93 +bit 21_94 +bit 21_95 +bit 21_96 +bit 21_97 +bit 21_98 +bit 21_99 +bit 22_00 +bit 22_01 +bit 22_02 +bit 22_03 +bit 22_04 +bit 22_05 +bit 22_06 +bit 22_07 +bit 22_08 +bit 22_09 +bit 22_10 +bit 22_100 +bit 22_101 +bit 22_102 +bit 22_103 +bit 22_104 +bit 22_105 +bit 22_106 +bit 22_107 +bit 22_108 +bit 22_109 +bit 22_11 +bit 22_110 +bit 22_111 +bit 22_112 +bit 22_113 +bit 22_114 +bit 22_115 +bit 22_116 +bit 22_117 +bit 22_118 +bit 22_119 +bit 22_12 +bit 22_120 +bit 22_121 +bit 22_122 +bit 22_123 +bit 22_124 +bit 22_125 +bit 22_126 +bit 22_127 +bit 22_128 +bit 22_129 +bit 22_13 +bit 22_130 +bit 22_131 +bit 22_132 +bit 22_133 +bit 22_134 +bit 22_135 +bit 22_136 +bit 22_137 +bit 22_138 +bit 22_139 +bit 22_14 +bit 22_140 +bit 22_141 +bit 22_142 +bit 22_143 +bit 22_144 +bit 22_145 +bit 22_146 +bit 22_147 +bit 22_148 +bit 22_149 +bit 22_15 +bit 22_150 +bit 22_151 +bit 22_152 +bit 22_153 +bit 22_154 +bit 22_155 +bit 22_156 +bit 22_157 +bit 22_158 +bit 22_159 +bit 22_16 +bit 22_160 +bit 22_161 +bit 22_162 +bit 22_163 +bit 22_164 +bit 22_165 +bit 22_166 +bit 22_167 +bit 22_168 +bit 22_169 +bit 22_17 +bit 22_170 +bit 22_171 +bit 22_172 +bit 22_173 +bit 22_174 +bit 22_175 +bit 22_176 +bit 22_177 +bit 22_178 +bit 22_179 +bit 22_18 +bit 22_180 +bit 22_181 +bit 22_182 +bit 22_183 +bit 22_184 +bit 22_185 +bit 22_186 +bit 22_187 +bit 22_188 +bit 22_189 +bit 22_19 +bit 22_190 +bit 22_191 +bit 22_192 +bit 22_193 +bit 22_194 +bit 22_195 +bit 22_196 +bit 22_197 +bit 22_198 +bit 22_199 +bit 22_20 +bit 22_200 +bit 22_201 +bit 22_202 +bit 22_203 +bit 22_204 +bit 22_205 +bit 22_206 +bit 22_207 +bit 22_208 +bit 22_209 +bit 22_21 +bit 22_210 +bit 22_211 +bit 22_212 +bit 22_213 +bit 22_214 +bit 22_215 +bit 22_216 +bit 22_217 +bit 22_218 +bit 22_219 +bit 22_22 +bit 22_220 +bit 22_221 +bit 22_222 +bit 22_223 +bit 22_224 +bit 22_225 +bit 22_226 +bit 22_227 +bit 22_228 +bit 22_229 +bit 22_23 +bit 22_230 +bit 22_231 +bit 22_232 +bit 22_233 +bit 22_234 +bit 22_235 +bit 22_236 +bit 22_237 +bit 22_238 +bit 22_239 +bit 22_24 +bit 22_240 +bit 22_241 +bit 22_242 +bit 22_243 +bit 22_244 +bit 22_245 +bit 22_246 +bit 22_247 +bit 22_248 +bit 22_249 +bit 22_25 +bit 22_250 +bit 22_251 +bit 22_252 +bit 22_253 +bit 22_254 +bit 22_255 +bit 22_256 +bit 22_257 +bit 22_258 +bit 22_259 +bit 22_26 +bit 22_260 +bit 22_261 +bit 22_262 +bit 22_263 +bit 22_264 +bit 22_265 +bit 22_266 +bit 22_267 +bit 22_268 +bit 22_269 +bit 22_27 +bit 22_270 +bit 22_271 +bit 22_272 +bit 22_273 +bit 22_274 +bit 22_275 +bit 22_276 +bit 22_277 +bit 22_278 +bit 22_279 +bit 22_28 +bit 22_280 +bit 22_281 +bit 22_282 +bit 22_283 +bit 22_284 +bit 22_285 +bit 22_286 +bit 22_287 +bit 22_288 +bit 22_289 +bit 22_29 +bit 22_290 +bit 22_291 +bit 22_292 +bit 22_293 +bit 22_294 +bit 22_295 +bit 22_296 +bit 22_297 +bit 22_298 +bit 22_299 +bit 22_30 +bit 22_300 +bit 22_301 +bit 22_302 +bit 22_303 +bit 22_304 +bit 22_305 +bit 22_306 +bit 22_307 +bit 22_308 +bit 22_309 +bit 22_31 +bit 22_310 +bit 22_311 +bit 22_312 +bit 22_313 +bit 22_314 +bit 22_315 +bit 22_316 +bit 22_317 +bit 22_318 +bit 22_319 +bit 22_32 +bit 22_33 +bit 22_34 +bit 22_35 +bit 22_36 +bit 22_37 +bit 22_38 +bit 22_39 +bit 22_40 +bit 22_41 +bit 22_42 +bit 22_43 +bit 22_44 +bit 22_45 +bit 22_46 +bit 22_47 +bit 22_48 +bit 22_49 +bit 22_50 +bit 22_51 +bit 22_52 +bit 22_53 +bit 22_54 +bit 22_55 +bit 22_56 +bit 22_57 +bit 22_58 +bit 22_59 +bit 22_60 +bit 22_61 +bit 22_62 +bit 22_63 +bit 22_64 +bit 22_65 +bit 22_66 +bit 22_67 +bit 22_68 +bit 22_69 +bit 22_70 +bit 22_71 +bit 22_72 +bit 22_73 +bit 22_74 +bit 22_75 +bit 22_76 +bit 22_77 +bit 22_78 +bit 22_79 +bit 22_80 +bit 22_81 +bit 22_82 +bit 22_83 +bit 22_84 +bit 22_85 +bit 22_86 +bit 22_87 +bit 22_88 +bit 22_89 +bit 22_90 +bit 22_91 +bit 22_92 +bit 22_93 +bit 22_94 +bit 22_95 +bit 22_96 +bit 22_97 +bit 22_98 +bit 22_99 +bit 23_00 +bit 23_01 +bit 23_02 +bit 23_03 +bit 23_04 +bit 23_05 +bit 23_06 +bit 23_07 +bit 23_08 +bit 23_09 +bit 23_10 +bit 23_100 +bit 23_101 +bit 23_102 +bit 23_103 +bit 23_104 +bit 23_105 +bit 23_106 +bit 23_107 +bit 23_108 +bit 23_109 +bit 23_11 +bit 23_110 +bit 23_111 +bit 23_112 +bit 23_113 +bit 23_114 +bit 23_115 +bit 23_116 +bit 23_117 +bit 23_118 +bit 23_119 +bit 23_12 +bit 23_120 +bit 23_121 +bit 23_122 +bit 23_123 +bit 23_124 +bit 23_125 +bit 23_126 +bit 23_127 +bit 23_128 +bit 23_129 +bit 23_13 +bit 23_130 +bit 23_131 +bit 23_132 +bit 23_133 +bit 23_134 +bit 23_135 +bit 23_136 +bit 23_137 +bit 23_138 +bit 23_139 +bit 23_14 +bit 23_140 +bit 23_141 +bit 23_142 +bit 23_143 +bit 23_144 +bit 23_145 +bit 23_146 +bit 23_147 +bit 23_148 +bit 23_149 +bit 23_15 +bit 23_150 +bit 23_151 +bit 23_152 +bit 23_153 +bit 23_154 +bit 23_155 +bit 23_156 +bit 23_157 +bit 23_158 +bit 23_159 +bit 23_16 +bit 23_160 +bit 23_161 +bit 23_162 +bit 23_163 +bit 23_164 +bit 23_165 +bit 23_166 +bit 23_167 +bit 23_168 +bit 23_169 +bit 23_17 +bit 23_170 +bit 23_171 +bit 23_172 +bit 23_173 +bit 23_174 +bit 23_175 +bit 23_176 +bit 23_177 +bit 23_178 +bit 23_179 +bit 23_18 +bit 23_180 +bit 23_181 +bit 23_182 +bit 23_183 +bit 23_184 +bit 23_185 +bit 23_186 +bit 23_187 +bit 23_188 +bit 23_189 +bit 23_19 +bit 23_190 +bit 23_191 +bit 23_192 +bit 23_193 +bit 23_194 +bit 23_195 +bit 23_196 +bit 23_197 +bit 23_198 +bit 23_199 +bit 23_20 +bit 23_200 +bit 23_201 +bit 23_202 +bit 23_203 +bit 23_204 +bit 23_205 +bit 23_206 +bit 23_207 +bit 23_208 +bit 23_209 +bit 23_21 +bit 23_210 +bit 23_211 +bit 23_212 +bit 23_213 +bit 23_214 +bit 23_215 +bit 23_216 +bit 23_217 +bit 23_218 +bit 23_219 +bit 23_22 +bit 23_220 +bit 23_221 +bit 23_222 +bit 23_223 +bit 23_224 +bit 23_225 +bit 23_226 +bit 23_227 +bit 23_228 +bit 23_229 +bit 23_23 +bit 23_230 +bit 23_231 +bit 23_232 +bit 23_233 +bit 23_234 +bit 23_235 +bit 23_236 +bit 23_237 +bit 23_238 +bit 23_239 +bit 23_24 +bit 23_240 +bit 23_241 +bit 23_242 +bit 23_243 +bit 23_244 +bit 23_245 +bit 23_246 +bit 23_247 +bit 23_248 +bit 23_249 +bit 23_25 +bit 23_250 +bit 23_251 +bit 23_252 +bit 23_253 +bit 23_254 +bit 23_255 +bit 23_256 +bit 23_257 +bit 23_258 +bit 23_259 +bit 23_26 +bit 23_260 +bit 23_261 +bit 23_262 +bit 23_263 +bit 23_264 +bit 23_265 +bit 23_266 +bit 23_267 +bit 23_268 +bit 23_269 +bit 23_27 +bit 23_270 +bit 23_271 +bit 23_272 +bit 23_273 +bit 23_274 +bit 23_275 +bit 23_276 +bit 23_277 +bit 23_278 +bit 23_279 +bit 23_28 +bit 23_280 +bit 23_281 +bit 23_282 +bit 23_283 +bit 23_284 +bit 23_285 +bit 23_286 +bit 23_287 +bit 23_288 +bit 23_289 +bit 23_29 +bit 23_290 +bit 23_291 +bit 23_292 +bit 23_293 +bit 23_294 +bit 23_295 +bit 23_296 +bit 23_297 +bit 23_298 +bit 23_299 +bit 23_30 +bit 23_300 +bit 23_301 +bit 23_302 +bit 23_303 +bit 23_304 +bit 23_305 +bit 23_306 +bit 23_307 +bit 23_308 +bit 23_309 +bit 23_31 +bit 23_310 +bit 23_311 +bit 23_312 +bit 23_313 +bit 23_314 +bit 23_315 +bit 23_316 +bit 23_317 +bit 23_318 +bit 23_319 +bit 23_32 +bit 23_33 +bit 23_34 +bit 23_35 +bit 23_36 +bit 23_37 +bit 23_38 +bit 23_39 +bit 23_40 +bit 23_41 +bit 23_42 +bit 23_43 +bit 23_44 +bit 23_45 +bit 23_46 +bit 23_47 +bit 23_48 +bit 23_49 +bit 23_50 +bit 23_51 +bit 23_52 +bit 23_53 +bit 23_54 +bit 23_55 +bit 23_56 +bit 23_57 +bit 23_58 +bit 23_59 +bit 23_60 +bit 23_61 +bit 23_62 +bit 23_63 +bit 23_64 +bit 23_65 +bit 23_66 +bit 23_67 +bit 23_68 +bit 23_69 +bit 23_70 +bit 23_71 +bit 23_72 +bit 23_73 +bit 23_74 +bit 23_75 +bit 23_76 +bit 23_77 +bit 23_78 +bit 23_79 +bit 23_80 +bit 23_81 +bit 23_82 +bit 23_83 +bit 23_84 +bit 23_85 +bit 23_86 +bit 23_87 +bit 23_88 +bit 23_89 +bit 23_90 +bit 23_91 +bit 23_92 +bit 23_93 +bit 23_94 +bit 23_95 +bit 23_96 +bit 23_97 +bit 23_98 +bit 23_99 +bit 24_00 +bit 24_01 +bit 24_02 +bit 24_03 +bit 24_04 +bit 24_05 +bit 24_06 +bit 24_07 +bit 24_08 +bit 24_09 +bit 24_10 +bit 24_100 +bit 24_101 +bit 24_102 +bit 24_103 +bit 24_104 +bit 24_105 +bit 24_106 +bit 24_107 +bit 24_108 +bit 24_109 +bit 24_11 +bit 24_110 +bit 24_111 +bit 24_112 +bit 24_113 +bit 24_114 +bit 24_115 +bit 24_116 +bit 24_117 +bit 24_118 +bit 24_119 +bit 24_12 +bit 24_120 +bit 24_121 +bit 24_122 +bit 24_123 +bit 24_124 +bit 24_125 +bit 24_126 +bit 24_127 +bit 24_128 +bit 24_129 +bit 24_13 +bit 24_130 +bit 24_131 +bit 24_132 +bit 24_133 +bit 24_134 +bit 24_135 +bit 24_136 +bit 24_137 +bit 24_138 +bit 24_139 +bit 24_14 +bit 24_140 +bit 24_141 +bit 24_142 +bit 24_143 +bit 24_144 +bit 24_145 +bit 24_146 +bit 24_147 +bit 24_148 +bit 24_149 +bit 24_15 +bit 24_150 +bit 24_151 +bit 24_152 +bit 24_153 +bit 24_154 +bit 24_155 +bit 24_156 +bit 24_157 +bit 24_158 +bit 24_159 +bit 24_16 +bit 24_160 +bit 24_161 +bit 24_162 +bit 24_163 +bit 24_164 +bit 24_165 +bit 24_166 +bit 24_167 +bit 24_168 +bit 24_169 +bit 24_17 +bit 24_170 +bit 24_171 +bit 24_172 +bit 24_173 +bit 24_174 +bit 24_175 +bit 24_176 +bit 24_177 +bit 24_178 +bit 24_179 +bit 24_18 +bit 24_180 +bit 24_181 +bit 24_182 +bit 24_183 +bit 24_184 +bit 24_185 +bit 24_186 +bit 24_187 +bit 24_188 +bit 24_189 +bit 24_19 +bit 24_190 +bit 24_191 +bit 24_192 +bit 24_193 +bit 24_194 +bit 24_195 +bit 24_196 +bit 24_197 +bit 24_198 +bit 24_199 +bit 24_20 +bit 24_200 +bit 24_201 +bit 24_202 +bit 24_203 +bit 24_204 +bit 24_205 +bit 24_206 +bit 24_207 +bit 24_208 +bit 24_209 +bit 24_21 +bit 24_210 +bit 24_211 +bit 24_212 +bit 24_213 +bit 24_214 +bit 24_215 +bit 24_216 +bit 24_217 +bit 24_218 +bit 24_219 +bit 24_22 +bit 24_220 +bit 24_221 +bit 24_222 +bit 24_223 +bit 24_224 +bit 24_225 +bit 24_226 +bit 24_227 +bit 24_228 +bit 24_229 +bit 24_23 +bit 24_230 +bit 24_231 +bit 24_232 +bit 24_233 +bit 24_234 +bit 24_235 +bit 24_236 +bit 24_237 +bit 24_238 +bit 24_239 +bit 24_24 +bit 24_240 +bit 24_241 +bit 24_242 +bit 24_243 +bit 24_244 +bit 24_245 +bit 24_246 +bit 24_247 +bit 24_248 +bit 24_249 +bit 24_25 +bit 24_250 +bit 24_251 +bit 24_252 +bit 24_253 +bit 24_254 +bit 24_255 +bit 24_256 +bit 24_257 +bit 24_258 +bit 24_259 +bit 24_26 +bit 24_260 +bit 24_261 +bit 24_262 +bit 24_263 +bit 24_264 +bit 24_265 +bit 24_266 +bit 24_267 +bit 24_268 +bit 24_269 +bit 24_27 +bit 24_270 +bit 24_271 +bit 24_272 +bit 24_273 +bit 24_274 +bit 24_275 +bit 24_276 +bit 24_277 +bit 24_278 +bit 24_279 +bit 24_28 +bit 24_280 +bit 24_281 +bit 24_282 +bit 24_283 +bit 24_284 +bit 24_285 +bit 24_286 +bit 24_287 +bit 24_288 +bit 24_289 +bit 24_29 +bit 24_290 +bit 24_291 +bit 24_292 +bit 24_293 +bit 24_294 +bit 24_295 +bit 24_296 +bit 24_297 +bit 24_298 +bit 24_299 +bit 24_30 +bit 24_300 +bit 24_301 +bit 24_302 +bit 24_303 +bit 24_304 +bit 24_305 +bit 24_306 +bit 24_307 +bit 24_308 +bit 24_309 +bit 24_31 +bit 24_310 +bit 24_311 +bit 24_312 +bit 24_313 +bit 24_314 +bit 24_315 +bit 24_316 +bit 24_317 +bit 24_318 +bit 24_319 +bit 24_32 +bit 24_33 +bit 24_34 +bit 24_35 +bit 24_36 +bit 24_37 +bit 24_38 +bit 24_39 +bit 24_40 +bit 24_41 +bit 24_42 +bit 24_43 +bit 24_44 +bit 24_45 +bit 24_46 +bit 24_47 +bit 24_48 +bit 24_49 +bit 24_50 +bit 24_51 +bit 24_52 +bit 24_53 +bit 24_54 +bit 24_55 +bit 24_56 +bit 24_57 +bit 24_58 +bit 24_59 +bit 24_60 +bit 24_61 +bit 24_62 +bit 24_63 +bit 24_64 +bit 24_65 +bit 24_66 +bit 24_67 +bit 24_68 +bit 24_69 +bit 24_70 +bit 24_71 +bit 24_72 +bit 24_73 +bit 24_74 +bit 24_75 +bit 24_76 +bit 24_77 +bit 24_78 +bit 24_79 +bit 24_80 +bit 24_81 +bit 24_82 +bit 24_83 +bit 24_84 +bit 24_85 +bit 24_86 +bit 24_87 +bit 24_88 +bit 24_89 +bit 24_90 +bit 24_91 +bit 24_92 +bit 24_93 +bit 24_94 +bit 24_95 +bit 24_96 +bit 24_97 +bit 24_98 +bit 24_99 +bit 25_00 +bit 25_01 +bit 25_02 +bit 25_03 +bit 25_04 +bit 25_05 +bit 25_06 +bit 25_07 +bit 25_08 +bit 25_09 +bit 25_10 +bit 25_100 +bit 25_101 +bit 25_102 +bit 25_103 +bit 25_104 +bit 25_105 +bit 25_106 +bit 25_107 +bit 25_108 +bit 25_109 +bit 25_11 +bit 25_110 +bit 25_111 +bit 25_112 +bit 25_113 +bit 25_114 +bit 25_115 +bit 25_116 +bit 25_117 +bit 25_118 +bit 25_119 +bit 25_12 +bit 25_120 +bit 25_121 +bit 25_122 +bit 25_123 +bit 25_124 +bit 25_125 +bit 25_126 +bit 25_127 +bit 25_128 +bit 25_129 +bit 25_13 +bit 25_130 +bit 25_131 +bit 25_132 +bit 25_133 +bit 25_134 +bit 25_135 +bit 25_136 +bit 25_137 +bit 25_138 +bit 25_139 +bit 25_14 +bit 25_140 +bit 25_141 +bit 25_142 +bit 25_143 +bit 25_144 +bit 25_145 +bit 25_146 +bit 25_147 +bit 25_148 +bit 25_149 +bit 25_15 +bit 25_150 +bit 25_151 +bit 25_152 +bit 25_153 +bit 25_154 +bit 25_155 +bit 25_156 +bit 25_157 +bit 25_158 +bit 25_159 +bit 25_16 +bit 25_160 +bit 25_161 +bit 25_162 +bit 25_163 +bit 25_164 +bit 25_165 +bit 25_166 +bit 25_167 +bit 25_168 +bit 25_169 +bit 25_17 +bit 25_170 +bit 25_171 +bit 25_172 +bit 25_173 +bit 25_174 +bit 25_175 +bit 25_176 +bit 25_177 +bit 25_178 +bit 25_179 +bit 25_18 +bit 25_180 +bit 25_181 +bit 25_182 +bit 25_183 +bit 25_184 +bit 25_185 +bit 25_186 +bit 25_187 +bit 25_188 +bit 25_189 +bit 25_19 +bit 25_190 +bit 25_191 +bit 25_192 +bit 25_193 +bit 25_194 +bit 25_195 +bit 25_196 +bit 25_197 +bit 25_198 +bit 25_199 +bit 25_20 +bit 25_200 +bit 25_201 +bit 25_202 +bit 25_203 +bit 25_204 +bit 25_205 +bit 25_206 +bit 25_207 +bit 25_208 +bit 25_209 +bit 25_21 +bit 25_210 +bit 25_211 +bit 25_212 +bit 25_213 +bit 25_214 +bit 25_215 +bit 25_216 +bit 25_217 +bit 25_218 +bit 25_219 +bit 25_22 +bit 25_220 +bit 25_221 +bit 25_222 +bit 25_223 +bit 25_224 +bit 25_225 +bit 25_226 +bit 25_227 +bit 25_228 +bit 25_229 +bit 25_23 +bit 25_230 +bit 25_231 +bit 25_232 +bit 25_233 +bit 25_234 +bit 25_235 +bit 25_236 +bit 25_237 +bit 25_238 +bit 25_239 +bit 25_24 +bit 25_240 +bit 25_241 +bit 25_242 +bit 25_243 +bit 25_244 +bit 25_245 +bit 25_246 +bit 25_247 +bit 25_248 +bit 25_249 +bit 25_25 +bit 25_250 +bit 25_251 +bit 25_252 +bit 25_253 +bit 25_254 +bit 25_255 +bit 25_256 +bit 25_257 +bit 25_258 +bit 25_259 +bit 25_26 +bit 25_260 +bit 25_261 +bit 25_262 +bit 25_263 +bit 25_264 +bit 25_265 +bit 25_266 +bit 25_267 +bit 25_268 +bit 25_269 +bit 25_27 +bit 25_270 +bit 25_271 +bit 25_272 +bit 25_273 +bit 25_274 +bit 25_275 +bit 25_276 +bit 25_277 +bit 25_278 +bit 25_279 +bit 25_28 +bit 25_280 +bit 25_281 +bit 25_282 +bit 25_283 +bit 25_284 +bit 25_285 +bit 25_286 +bit 25_287 +bit 25_288 +bit 25_289 +bit 25_29 +bit 25_290 +bit 25_291 +bit 25_292 +bit 25_293 +bit 25_294 +bit 25_295 +bit 25_296 +bit 25_297 +bit 25_298 +bit 25_299 +bit 25_30 +bit 25_300 +bit 25_301 +bit 25_302 +bit 25_303 +bit 25_304 +bit 25_305 +bit 25_306 +bit 25_307 +bit 25_308 +bit 25_309 +bit 25_31 +bit 25_310 +bit 25_311 +bit 25_312 +bit 25_313 +bit 25_314 +bit 25_315 +bit 25_316 +bit 25_317 +bit 25_318 +bit 25_319 +bit 25_32 +bit 25_33 +bit 25_34 +bit 25_35 +bit 25_36 +bit 25_37 +bit 25_38 +bit 25_39 +bit 25_40 +bit 25_41 +bit 25_42 +bit 25_43 +bit 25_44 +bit 25_45 +bit 25_46 +bit 25_47 +bit 25_48 +bit 25_49 +bit 25_50 +bit 25_51 +bit 25_52 +bit 25_53 +bit 25_54 +bit 25_55 +bit 25_56 +bit 25_57 +bit 25_58 +bit 25_59 +bit 25_60 +bit 25_61 +bit 25_62 +bit 25_63 +bit 25_64 +bit 25_65 +bit 25_66 +bit 25_67 +bit 25_68 +bit 25_69 +bit 25_70 +bit 25_71 +bit 25_72 +bit 25_73 +bit 25_74 +bit 25_75 +bit 25_76 +bit 25_77 +bit 25_78 +bit 25_79 +bit 25_80 +bit 25_81 +bit 25_82 +bit 25_83 +bit 25_84 +bit 25_85 +bit 25_86 +bit 25_87 +bit 25_88 +bit 25_89 +bit 25_90 +bit 25_91 +bit 25_92 +bit 25_93 +bit 25_94 +bit 25_95 +bit 25_96 +bit 25_97 +bit 25_98 +bit 25_99 +bit 30_02 +bit 30_101 +bit 30_124 +bit 30_130 +bit 30_153 +bit 30_165 +bit 30_188 +bit 30_194 +bit 30_217 +bit 30_229 +bit 30_25 +bit 30_252 +bit 30_258 +bit 30_281 +bit 30_293 +bit 30_316 +bit 30_37 +bit 30_60 +bit 30_66 +bit 30_89 +bit 31_02 +bit 31_101 +bit 31_126 +bit 31_130 +bit 31_154 +bit 31_165 +bit 31_190 +bit 31_194 +bit 31_218 +bit 31_229 +bit 31_254 +bit 31_258 +bit 31_26 +bit 31_282 +bit 31_293 +bit 31_318 +bit 31_37 +bit 31_62 +bit 31_66 +bit 31_90 diff --git a/kintex7/mask_dsp_r.db b/kintex7/mask_dsp_r.db new file mode 100644 index 0000000..0913b8d --- /dev/null +++ b/kintex7/mask_dsp_r.db @@ -0,0 +1,8030 @@ +bit 00_01 +bit 00_02 +bit 00_03 +bit 00_05 +bit 00_06 +bit 00_07 +bit 00_09 +bit 00_10 +bit 00_101 +bit 00_102 +bit 00_103 +bit 00_105 +bit 00_106 +bit 00_107 +bit 00_109 +bit 00_11 +bit 00_110 +bit 00_111 +bit 00_113 +bit 00_114 +bit 00_115 +bit 00_117 +bit 00_118 +bit 00_119 +bit 00_121 +bit 00_122 +bit 00_123 +bit 00_125 +bit 00_126 +bit 00_127 +bit 00_129 +bit 00_13 +bit 00_130 +bit 00_131 +bit 00_133 +bit 00_134 +bit 00_135 +bit 00_137 +bit 00_138 +bit 00_139 +bit 00_14 +bit 00_141 +bit 00_142 +bit 00_143 +bit 00_145 +bit 00_146 +bit 00_147 +bit 00_149 +bit 00_15 +bit 00_150 +bit 00_151 +bit 00_153 +bit 00_154 +bit 00_155 +bit 00_157 +bit 00_158 +bit 00_161 +bit 00_162 +bit 00_163 +bit 00_165 +bit 00_166 +bit 00_167 +bit 00_169 +bit 00_17 +bit 00_170 +bit 00_171 +bit 00_173 +bit 00_174 +bit 00_175 +bit 00_177 +bit 00_178 +bit 00_179 +bit 00_18 +bit 00_181 +bit 00_182 +bit 00_183 +bit 00_185 +bit 00_186 +bit 00_187 +bit 00_189 +bit 00_19 +bit 00_190 +bit 00_191 +bit 00_193 +bit 00_194 +bit 00_195 +bit 00_197 +bit 00_198 +bit 00_199 +bit 00_201 +bit 00_202 +bit 00_203 +bit 00_205 +bit 00_206 +bit 00_207 +bit 00_209 +bit 00_21 +bit 00_210 +bit 00_211 +bit 00_213 +bit 00_214 +bit 00_215 +bit 00_217 +bit 00_218 +bit 00_219 +bit 00_22 +bit 00_221 +bit 00_222 +bit 00_225 +bit 00_226 +bit 00_227 +bit 00_229 +bit 00_23 +bit 00_230 +bit 00_231 +bit 00_233 +bit 00_234 +bit 00_235 +bit 00_237 +bit 00_238 +bit 00_239 +bit 00_241 +bit 00_242 +bit 00_243 +bit 00_245 +bit 00_246 +bit 00_247 +bit 00_249 +bit 00_25 +bit 00_250 +bit 00_251 +bit 00_253 +bit 00_254 +bit 00_255 +bit 00_257 +bit 00_258 +bit 00_259 +bit 00_26 +bit 00_261 +bit 00_262 +bit 00_263 +bit 00_265 +bit 00_266 +bit 00_267 +bit 00_269 +bit 00_27 +bit 00_270 +bit 00_271 +bit 00_273 +bit 00_274 +bit 00_275 +bit 00_277 +bit 00_278 +bit 00_279 +bit 00_281 +bit 00_282 +bit 00_283 +bit 00_285 +bit 00_286 +bit 00_289 +bit 00_29 +bit 00_290 +bit 00_291 +bit 00_293 +bit 00_294 +bit 00_295 +bit 00_297 +bit 00_298 +bit 00_299 +bit 00_30 +bit 00_301 +bit 00_302 +bit 00_303 +bit 00_305 +bit 00_306 +bit 00_307 +bit 00_309 +bit 00_310 +bit 00_311 +bit 00_313 +bit 00_314 +bit 00_315 +bit 00_317 +bit 00_318 +bit 00_319 +bit 00_33 +bit 00_34 +bit 00_35 +bit 00_37 +bit 00_38 +bit 00_39 +bit 00_41 +bit 00_42 +bit 00_43 +bit 00_45 +bit 00_46 +bit 00_47 +bit 00_49 +bit 00_50 +bit 00_51 +bit 00_53 +bit 00_54 +bit 00_55 +bit 00_57 +bit 00_58 +bit 00_59 +bit 00_61 +bit 00_62 +bit 00_63 +bit 00_65 +bit 00_66 +bit 00_67 +bit 00_69 +bit 00_70 +bit 00_71 +bit 00_73 +bit 00_74 +bit 00_75 +bit 00_77 +bit 00_78 +bit 00_79 +bit 00_81 +bit 00_82 +bit 00_83 +bit 00_85 +bit 00_86 +bit 00_87 +bit 00_89 +bit 00_90 +bit 00_91 +bit 00_93 +bit 00_94 +bit 00_97 +bit 00_98 +bit 00_99 +bit 01_00 +bit 01_01 +bit 01_02 +bit 01_04 +bit 01_05 +bit 01_06 +bit 01_08 +bit 01_09 +bit 01_10 +bit 01_100 +bit 01_101 +bit 01_102 +bit 01_104 +bit 01_105 +bit 01_106 +bit 01_108 +bit 01_109 +bit 01_110 +bit 01_112 +bit 01_113 +bit 01_114 +bit 01_116 +bit 01_117 +bit 01_118 +bit 01_12 +bit 01_120 +bit 01_121 +bit 01_122 +bit 01_124 +bit 01_125 +bit 01_126 +bit 01_128 +bit 01_129 +bit 01_13 +bit 01_130 +bit 01_132 +bit 01_133 +bit 01_134 +bit 01_136 +bit 01_137 +bit 01_138 +bit 01_14 +bit 01_140 +bit 01_141 +bit 01_142 +bit 01_144 +bit 01_145 +bit 01_146 +bit 01_148 +bit 01_149 +bit 01_150 +bit 01_152 +bit 01_153 +bit 01_154 +bit 01_156 +bit 01_157 +bit 01_16 +bit 01_160 +bit 01_161 +bit 01_162 +bit 01_164 +bit 01_165 +bit 01_166 +bit 01_168 +bit 01_169 +bit 01_17 +bit 01_170 +bit 01_172 +bit 01_173 +bit 01_174 +bit 01_176 +bit 01_177 +bit 01_178 +bit 01_18 +bit 01_180 +bit 01_181 +bit 01_182 +bit 01_184 +bit 01_185 +bit 01_186 +bit 01_188 +bit 01_189 +bit 01_190 +bit 01_192 +bit 01_193 +bit 01_194 +bit 01_196 +bit 01_197 +bit 01_198 +bit 01_20 +bit 01_200 +bit 01_201 +bit 01_202 +bit 01_204 +bit 01_205 +bit 01_206 +bit 01_208 +bit 01_209 +bit 01_21 +bit 01_210 +bit 01_212 +bit 01_213 +bit 01_214 +bit 01_216 +bit 01_217 +bit 01_218 +bit 01_22 +bit 01_220 +bit 01_221 +bit 01_224 +bit 01_225 +bit 01_226 +bit 01_228 +bit 01_229 +bit 01_230 +bit 01_232 +bit 01_233 +bit 01_234 +bit 01_236 +bit 01_237 +bit 01_238 +bit 01_24 +bit 01_240 +bit 01_241 +bit 01_242 +bit 01_244 +bit 01_245 +bit 01_246 +bit 01_248 +bit 01_249 +bit 01_25 +bit 01_250 +bit 01_252 +bit 01_253 +bit 01_254 +bit 01_256 +bit 01_257 +bit 01_258 +bit 01_26 +bit 01_260 +bit 01_261 +bit 01_262 +bit 01_264 +bit 01_265 +bit 01_266 +bit 01_268 +bit 01_269 +bit 01_270 +bit 01_272 +bit 01_273 +bit 01_274 +bit 01_276 +bit 01_277 +bit 01_278 +bit 01_28 +bit 01_280 +bit 01_281 +bit 01_282 +bit 01_284 +bit 01_285 +bit 01_288 +bit 01_289 +bit 01_29 +bit 01_290 +bit 01_292 +bit 01_293 +bit 01_294 +bit 01_296 +bit 01_297 +bit 01_298 +bit 01_300 +bit 01_301 +bit 01_302 +bit 01_304 +bit 01_305 +bit 01_306 +bit 01_308 +bit 01_309 +bit 01_310 +bit 01_312 +bit 01_313 +bit 01_314 +bit 01_316 +bit 01_317 +bit 01_318 +bit 01_32 +bit 01_33 +bit 01_34 +bit 01_36 +bit 01_37 +bit 01_38 +bit 01_40 +bit 01_41 +bit 01_42 +bit 01_44 +bit 01_45 +bit 01_46 +bit 01_48 +bit 01_49 +bit 01_50 +bit 01_52 +bit 01_53 +bit 01_54 +bit 01_56 +bit 01_57 +bit 01_58 +bit 01_60 +bit 01_61 +bit 01_62 +bit 01_64 +bit 01_65 +bit 01_66 +bit 01_68 +bit 01_69 +bit 01_70 +bit 01_72 +bit 01_73 +bit 01_74 +bit 01_76 +bit 01_77 +bit 01_78 +bit 01_80 +bit 01_81 +bit 01_82 +bit 01_84 +bit 01_85 +bit 01_86 +bit 01_88 +bit 01_89 +bit 01_90 +bit 01_92 +bit 01_93 +bit 01_96 +bit 01_97 +bit 01_98 +bit 02_01 +bit 02_02 +bit 02_03 +bit 02_05 +bit 02_06 +bit 02_07 +bit 02_09 +bit 02_10 +bit 02_101 +bit 02_102 +bit 02_103 +bit 02_105 +bit 02_106 +bit 02_107 +bit 02_109 +bit 02_11 +bit 02_110 +bit 02_111 +bit 02_113 +bit 02_114 +bit 02_115 +bit 02_117 +bit 02_118 +bit 02_119 +bit 02_121 +bit 02_122 +bit 02_123 +bit 02_125 +bit 02_126 +bit 02_127 +bit 02_129 +bit 02_13 +bit 02_130 +bit 02_131 +bit 02_133 +bit 02_134 +bit 02_135 +bit 02_137 +bit 02_138 +bit 02_139 +bit 02_14 +bit 02_141 +bit 02_142 +bit 02_143 +bit 02_145 +bit 02_146 +bit 02_147 +bit 02_149 +bit 02_15 +bit 02_150 +bit 02_151 +bit 02_153 +bit 02_154 +bit 02_155 +bit 02_157 +bit 02_158 +bit 02_159 +bit 02_161 +bit 02_162 +bit 02_163 +bit 02_165 +bit 02_166 +bit 02_167 +bit 02_169 +bit 02_17 +bit 02_170 +bit 02_171 +bit 02_173 +bit 02_174 +bit 02_175 +bit 02_177 +bit 02_178 +bit 02_179 +bit 02_18 +bit 02_181 +bit 02_182 +bit 02_183 +bit 02_185 +bit 02_186 +bit 02_187 +bit 02_189 +bit 02_19 +bit 02_190 +bit 02_191 +bit 02_193 +bit 02_194 +bit 02_195 +bit 02_197 +bit 02_198 +bit 02_199 +bit 02_201 +bit 02_202 +bit 02_203 +bit 02_205 +bit 02_206 +bit 02_207 +bit 02_209 +bit 02_21 +bit 02_210 +bit 02_211 +bit 02_213 +bit 02_214 +bit 02_215 +bit 02_217 +bit 02_218 +bit 02_219 +bit 02_22 +bit 02_221 +bit 02_222 +bit 02_223 +bit 02_225 +bit 02_226 +bit 02_227 +bit 02_229 +bit 02_23 +bit 02_230 +bit 02_231 +bit 02_233 +bit 02_234 +bit 02_235 +bit 02_237 +bit 02_238 +bit 02_239 +bit 02_241 +bit 02_242 +bit 02_243 +bit 02_245 +bit 02_246 +bit 02_247 +bit 02_249 +bit 02_25 +bit 02_250 +bit 02_251 +bit 02_253 +bit 02_254 +bit 02_255 +bit 02_257 +bit 02_258 +bit 02_259 +bit 02_26 +bit 02_261 +bit 02_262 +bit 02_263 +bit 02_265 +bit 02_266 +bit 02_267 +bit 02_269 +bit 02_27 +bit 02_270 +bit 02_271 +bit 02_273 +bit 02_274 +bit 02_275 +bit 02_277 +bit 02_278 +bit 02_279 +bit 02_281 +bit 02_282 +bit 02_283 +bit 02_285 +bit 02_286 +bit 02_287 +bit 02_289 +bit 02_29 +bit 02_290 +bit 02_291 +bit 02_293 +bit 02_294 +bit 02_295 +bit 02_297 +bit 02_298 +bit 02_299 +bit 02_30 +bit 02_301 +bit 02_302 +bit 02_303 +bit 02_305 +bit 02_306 +bit 02_307 +bit 02_309 +bit 02_31 +bit 02_310 +bit 02_311 +bit 02_313 +bit 02_314 +bit 02_315 +bit 02_317 +bit 02_318 +bit 02_319 +bit 02_33 +bit 02_34 +bit 02_35 +bit 02_37 +bit 02_38 +bit 02_39 +bit 02_41 +bit 02_42 +bit 02_43 +bit 02_45 +bit 02_46 +bit 02_47 +bit 02_49 +bit 02_50 +bit 02_51 +bit 02_53 +bit 02_54 +bit 02_55 +bit 02_57 +bit 02_58 +bit 02_59 +bit 02_61 +bit 02_62 +bit 02_63 +bit 02_65 +bit 02_66 +bit 02_67 +bit 02_69 +bit 02_70 +bit 02_71 +bit 02_73 +bit 02_74 +bit 02_75 +bit 02_77 +bit 02_78 +bit 02_79 +bit 02_81 +bit 02_82 +bit 02_83 +bit 02_85 +bit 02_86 +bit 02_87 +bit 02_89 +bit 02_90 +bit 02_91 +bit 02_93 +bit 02_94 +bit 02_95 +bit 02_97 +bit 02_98 +bit 02_99 +bit 03_00 +bit 03_01 +bit 03_02 +bit 03_04 +bit 03_05 +bit 03_06 +bit 03_08 +bit 03_09 +bit 03_10 +bit 03_100 +bit 03_101 +bit 03_102 +bit 03_104 +bit 03_105 +bit 03_106 +bit 03_108 +bit 03_109 +bit 03_110 +bit 03_112 +bit 03_113 +bit 03_114 +bit 03_116 +bit 03_117 +bit 03_118 +bit 03_12 +bit 03_120 +bit 03_121 +bit 03_122 +bit 03_124 +bit 03_125 +bit 03_126 +bit 03_128 +bit 03_129 +bit 03_13 +bit 03_130 +bit 03_132 +bit 03_133 +bit 03_134 +bit 03_136 +bit 03_137 +bit 03_138 +bit 03_14 +bit 03_140 +bit 03_141 +bit 03_142 +bit 03_144 +bit 03_145 +bit 03_146 +bit 03_148 +bit 03_149 +bit 03_150 +bit 03_152 +bit 03_153 +bit 03_154 +bit 03_156 +bit 03_157 +bit 03_158 +bit 03_16 +bit 03_160 +bit 03_161 +bit 03_162 +bit 03_164 +bit 03_165 +bit 03_166 +bit 03_168 +bit 03_169 +bit 03_17 +bit 03_170 +bit 03_172 +bit 03_173 +bit 03_174 +bit 03_176 +bit 03_177 +bit 03_178 +bit 03_18 +bit 03_180 +bit 03_181 +bit 03_182 +bit 03_184 +bit 03_185 +bit 03_186 +bit 03_188 +bit 03_189 +bit 03_190 +bit 03_192 +bit 03_193 +bit 03_194 +bit 03_196 +bit 03_197 +bit 03_198 +bit 03_20 +bit 03_200 +bit 03_201 +bit 03_202 +bit 03_204 +bit 03_205 +bit 03_206 +bit 03_208 +bit 03_209 +bit 03_21 +bit 03_210 +bit 03_212 +bit 03_213 +bit 03_214 +bit 03_216 +bit 03_217 +bit 03_218 +bit 03_22 +bit 03_220 +bit 03_221 +bit 03_222 +bit 03_224 +bit 03_225 +bit 03_226 +bit 03_228 +bit 03_229 +bit 03_230 +bit 03_232 +bit 03_233 +bit 03_234 +bit 03_236 +bit 03_237 +bit 03_238 +bit 03_24 +bit 03_240 +bit 03_241 +bit 03_242 +bit 03_244 +bit 03_245 +bit 03_246 +bit 03_248 +bit 03_249 +bit 03_25 +bit 03_250 +bit 03_252 +bit 03_253 +bit 03_254 +bit 03_256 +bit 03_257 +bit 03_258 +bit 03_26 +bit 03_260 +bit 03_261 +bit 03_262 +bit 03_264 +bit 03_265 +bit 03_266 +bit 03_268 +bit 03_269 +bit 03_270 +bit 03_272 +bit 03_273 +bit 03_274 +bit 03_276 +bit 03_277 +bit 03_278 +bit 03_28 +bit 03_280 +bit 03_281 +bit 03_282 +bit 03_284 +bit 03_285 +bit 03_286 +bit 03_288 +bit 03_289 +bit 03_29 +bit 03_290 +bit 03_292 +bit 03_293 +bit 03_294 +bit 03_296 +bit 03_297 +bit 03_298 +bit 03_30 +bit 03_300 +bit 03_301 +bit 03_302 +bit 03_304 +bit 03_305 +bit 03_306 +bit 03_308 +bit 03_309 +bit 03_310 +bit 03_312 +bit 03_313 +bit 03_314 +bit 03_316 +bit 03_317 +bit 03_318 +bit 03_32 +bit 03_33 +bit 03_34 +bit 03_36 +bit 03_37 +bit 03_38 +bit 03_40 +bit 03_41 +bit 03_42 +bit 03_44 +bit 03_45 +bit 03_46 +bit 03_48 +bit 03_49 +bit 03_50 +bit 03_52 +bit 03_53 +bit 03_54 +bit 03_56 +bit 03_57 +bit 03_58 +bit 03_60 +bit 03_61 +bit 03_62 +bit 03_64 +bit 03_65 +bit 03_66 +bit 03_68 +bit 03_69 +bit 03_70 +bit 03_72 +bit 03_73 +bit 03_74 +bit 03_76 +bit 03_77 +bit 03_78 +bit 03_80 +bit 03_81 +bit 03_82 +bit 03_84 +bit 03_85 +bit 03_86 +bit 03_88 +bit 03_89 +bit 03_90 +bit 03_92 +bit 03_93 +bit 03_94 +bit 03_96 +bit 03_97 +bit 03_98 +bit 04_00 +bit 04_01 +bit 04_02 +bit 04_03 +bit 04_04 +bit 04_05 +bit 04_06 +bit 04_07 +bit 04_08 +bit 04_09 +bit 04_10 +bit 04_100 +bit 04_101 +bit 04_102 +bit 04_103 +bit 04_104 +bit 04_105 +bit 04_106 +bit 04_107 +bit 04_108 +bit 04_109 +bit 04_11 +bit 04_110 +bit 04_111 +bit 04_112 +bit 04_113 +bit 04_114 +bit 04_115 +bit 04_116 +bit 04_117 +bit 04_118 +bit 04_119 +bit 04_12 +bit 04_120 +bit 04_121 +bit 04_122 +bit 04_123 +bit 04_124 +bit 04_125 +bit 04_126 +bit 04_127 +bit 04_128 +bit 04_129 +bit 04_13 +bit 04_130 +bit 04_131 +bit 04_132 +bit 04_133 +bit 04_134 +bit 04_135 +bit 04_136 +bit 04_137 +bit 04_138 +bit 04_139 +bit 04_14 +bit 04_140 +bit 04_141 +bit 04_142 +bit 04_143 +bit 04_144 +bit 04_145 +bit 04_146 +bit 04_147 +bit 04_148 +bit 04_149 +bit 04_15 +bit 04_150 +bit 04_151 +bit 04_152 +bit 04_153 +bit 04_154 +bit 04_155 +bit 04_156 +bit 04_157 +bit 04_158 +bit 04_159 +bit 04_16 +bit 04_160 +bit 04_161 +bit 04_162 +bit 04_163 +bit 04_164 +bit 04_165 +bit 04_166 +bit 04_167 +bit 04_168 +bit 04_169 +bit 04_17 +bit 04_170 +bit 04_171 +bit 04_172 +bit 04_173 +bit 04_174 +bit 04_175 +bit 04_176 +bit 04_177 +bit 04_178 +bit 04_179 +bit 04_18 +bit 04_180 +bit 04_181 +bit 04_182 +bit 04_183 +bit 04_184 +bit 04_185 +bit 04_186 +bit 04_187 +bit 04_188 +bit 04_189 +bit 04_19 +bit 04_190 +bit 04_191 +bit 04_192 +bit 04_193 +bit 04_194 +bit 04_195 +bit 04_196 +bit 04_197 +bit 04_198 +bit 04_199 +bit 04_20 +bit 04_200 +bit 04_201 +bit 04_202 +bit 04_203 +bit 04_204 +bit 04_205 +bit 04_206 +bit 04_207 +bit 04_208 +bit 04_209 +bit 04_21 +bit 04_210 +bit 04_211 +bit 04_212 +bit 04_213 +bit 04_214 +bit 04_215 +bit 04_216 +bit 04_217 +bit 04_218 +bit 04_219 +bit 04_22 +bit 04_220 +bit 04_221 +bit 04_222 +bit 04_223 +bit 04_224 +bit 04_225 +bit 04_226 +bit 04_227 +bit 04_228 +bit 04_229 +bit 04_23 +bit 04_230 +bit 04_231 +bit 04_232 +bit 04_233 +bit 04_234 +bit 04_235 +bit 04_236 +bit 04_237 +bit 04_238 +bit 04_239 +bit 04_24 +bit 04_240 +bit 04_241 +bit 04_242 +bit 04_243 +bit 04_244 +bit 04_245 +bit 04_246 +bit 04_247 +bit 04_248 +bit 04_249 +bit 04_25 +bit 04_250 +bit 04_251 +bit 04_252 +bit 04_253 +bit 04_254 +bit 04_255 +bit 04_256 +bit 04_257 +bit 04_258 +bit 04_259 +bit 04_26 +bit 04_260 +bit 04_261 +bit 04_262 +bit 04_263 +bit 04_264 +bit 04_265 +bit 04_266 +bit 04_267 +bit 04_268 +bit 04_269 +bit 04_27 +bit 04_270 +bit 04_271 +bit 04_272 +bit 04_273 +bit 04_274 +bit 04_275 +bit 04_276 +bit 04_277 +bit 04_278 +bit 04_279 +bit 04_28 +bit 04_280 +bit 04_281 +bit 04_282 +bit 04_283 +bit 04_284 +bit 04_285 +bit 04_286 +bit 04_287 +bit 04_288 +bit 04_289 +bit 04_29 +bit 04_290 +bit 04_291 +bit 04_292 +bit 04_293 +bit 04_294 +bit 04_295 +bit 04_296 +bit 04_297 +bit 04_298 +bit 04_299 +bit 04_30 +bit 04_300 +bit 04_301 +bit 04_302 +bit 04_303 +bit 04_304 +bit 04_305 +bit 04_306 +bit 04_307 +bit 04_308 +bit 04_309 +bit 04_31 +bit 04_310 +bit 04_311 +bit 04_312 +bit 04_313 +bit 04_314 +bit 04_315 +bit 04_316 +bit 04_317 +bit 04_318 +bit 04_319 +bit 04_32 +bit 04_33 +bit 04_34 +bit 04_35 +bit 04_36 +bit 04_37 +bit 04_38 +bit 04_39 +bit 04_40 +bit 04_41 +bit 04_42 +bit 04_43 +bit 04_44 +bit 04_45 +bit 04_46 +bit 04_47 +bit 04_48 +bit 04_49 +bit 04_50 +bit 04_51 +bit 04_52 +bit 04_53 +bit 04_54 +bit 04_55 +bit 04_56 +bit 04_57 +bit 04_58 +bit 04_59 +bit 04_60 +bit 04_61 +bit 04_62 +bit 04_63 +bit 04_64 +bit 04_65 +bit 04_66 +bit 04_67 +bit 04_68 +bit 04_69 +bit 04_70 +bit 04_71 +bit 04_72 +bit 04_73 +bit 04_74 +bit 04_75 +bit 04_76 +bit 04_77 +bit 04_78 +bit 04_79 +bit 04_80 +bit 04_81 +bit 04_82 +bit 04_83 +bit 04_84 +bit 04_85 +bit 04_86 +bit 04_87 +bit 04_88 +bit 04_89 +bit 04_90 +bit 04_91 +bit 04_92 +bit 04_93 +bit 04_94 +bit 04_95 +bit 04_96 +bit 04_97 +bit 04_98 +bit 04_99 +bit 05_00 +bit 05_01 +bit 05_02 +bit 05_03 +bit 05_04 +bit 05_05 +bit 05_06 +bit 05_07 +bit 05_08 +bit 05_09 +bit 05_10 +bit 05_100 +bit 05_101 +bit 05_102 +bit 05_103 +bit 05_104 +bit 05_105 +bit 05_106 +bit 05_107 +bit 05_108 +bit 05_109 +bit 05_11 +bit 05_110 +bit 05_111 +bit 05_112 +bit 05_113 +bit 05_114 +bit 05_115 +bit 05_116 +bit 05_117 +bit 05_118 +bit 05_119 +bit 05_12 +bit 05_120 +bit 05_121 +bit 05_122 +bit 05_123 +bit 05_124 +bit 05_125 +bit 05_126 +bit 05_127 +bit 05_128 +bit 05_129 +bit 05_13 +bit 05_130 +bit 05_131 +bit 05_132 +bit 05_133 +bit 05_134 +bit 05_135 +bit 05_136 +bit 05_137 +bit 05_138 +bit 05_139 +bit 05_14 +bit 05_140 +bit 05_141 +bit 05_142 +bit 05_143 +bit 05_144 +bit 05_145 +bit 05_146 +bit 05_147 +bit 05_148 +bit 05_149 +bit 05_15 +bit 05_150 +bit 05_151 +bit 05_152 +bit 05_153 +bit 05_154 +bit 05_155 +bit 05_156 +bit 05_157 +bit 05_158 +bit 05_159 +bit 05_16 +bit 05_160 +bit 05_161 +bit 05_162 +bit 05_163 +bit 05_164 +bit 05_165 +bit 05_166 +bit 05_167 +bit 05_168 +bit 05_169 +bit 05_17 +bit 05_170 +bit 05_171 +bit 05_172 +bit 05_173 +bit 05_174 +bit 05_175 +bit 05_176 +bit 05_177 +bit 05_178 +bit 05_179 +bit 05_18 +bit 05_180 +bit 05_181 +bit 05_182 +bit 05_183 +bit 05_184 +bit 05_185 +bit 05_186 +bit 05_187 +bit 05_188 +bit 05_189 +bit 05_19 +bit 05_190 +bit 05_191 +bit 05_192 +bit 05_193 +bit 05_194 +bit 05_195 +bit 05_196 +bit 05_197 +bit 05_198 +bit 05_199 +bit 05_20 +bit 05_200 +bit 05_201 +bit 05_202 +bit 05_203 +bit 05_204 +bit 05_205 +bit 05_206 +bit 05_207 +bit 05_208 +bit 05_209 +bit 05_21 +bit 05_210 +bit 05_211 +bit 05_212 +bit 05_213 +bit 05_214 +bit 05_215 +bit 05_216 +bit 05_217 +bit 05_218 +bit 05_219 +bit 05_22 +bit 05_220 +bit 05_221 +bit 05_222 +bit 05_223 +bit 05_224 +bit 05_225 +bit 05_226 +bit 05_227 +bit 05_228 +bit 05_229 +bit 05_23 +bit 05_230 +bit 05_231 +bit 05_232 +bit 05_233 +bit 05_234 +bit 05_235 +bit 05_236 +bit 05_237 +bit 05_238 +bit 05_239 +bit 05_24 +bit 05_240 +bit 05_241 +bit 05_242 +bit 05_243 +bit 05_244 +bit 05_245 +bit 05_246 +bit 05_247 +bit 05_248 +bit 05_249 +bit 05_25 +bit 05_250 +bit 05_251 +bit 05_252 +bit 05_253 +bit 05_254 +bit 05_255 +bit 05_256 +bit 05_257 +bit 05_258 +bit 05_259 +bit 05_26 +bit 05_260 +bit 05_261 +bit 05_262 +bit 05_263 +bit 05_264 +bit 05_265 +bit 05_266 +bit 05_267 +bit 05_268 +bit 05_269 +bit 05_27 +bit 05_270 +bit 05_271 +bit 05_272 +bit 05_273 +bit 05_274 +bit 05_275 +bit 05_276 +bit 05_277 +bit 05_278 +bit 05_279 +bit 05_28 +bit 05_280 +bit 05_281 +bit 05_282 +bit 05_283 +bit 05_284 +bit 05_285 +bit 05_286 +bit 05_287 +bit 05_288 +bit 05_289 +bit 05_29 +bit 05_290 +bit 05_291 +bit 05_292 +bit 05_293 +bit 05_294 +bit 05_295 +bit 05_296 +bit 05_297 +bit 05_298 +bit 05_299 +bit 05_30 +bit 05_300 +bit 05_301 +bit 05_302 +bit 05_303 +bit 05_304 +bit 05_305 +bit 05_306 +bit 05_307 +bit 05_308 +bit 05_309 +bit 05_31 +bit 05_310 +bit 05_311 +bit 05_312 +bit 05_313 +bit 05_314 +bit 05_315 +bit 05_316 +bit 05_317 +bit 05_318 +bit 05_319 +bit 05_32 +bit 05_33 +bit 05_34 +bit 05_35 +bit 05_36 +bit 05_37 +bit 05_38 +bit 05_39 +bit 05_40 +bit 05_41 +bit 05_42 +bit 05_43 +bit 05_44 +bit 05_45 +bit 05_46 +bit 05_47 +bit 05_48 +bit 05_49 +bit 05_50 +bit 05_51 +bit 05_52 +bit 05_53 +bit 05_54 +bit 05_55 +bit 05_56 +bit 05_57 +bit 05_58 +bit 05_59 +bit 05_60 +bit 05_61 +bit 05_62 +bit 05_63 +bit 05_64 +bit 05_65 +bit 05_66 +bit 05_67 +bit 05_68 +bit 05_69 +bit 05_70 +bit 05_71 +bit 05_72 +bit 05_73 +bit 05_74 +bit 05_75 +bit 05_76 +bit 05_77 +bit 05_78 +bit 05_79 +bit 05_80 +bit 05_81 +bit 05_82 +bit 05_83 +bit 05_84 +bit 05_85 +bit 05_86 +bit 05_87 +bit 05_88 +bit 05_89 +bit 05_90 +bit 05_91 +bit 05_92 +bit 05_93 +bit 05_94 +bit 05_95 +bit 05_96 +bit 05_97 +bit 05_98 +bit 05_99 +bit 06_00 +bit 06_01 +bit 06_02 +bit 06_03 +bit 06_04 +bit 06_05 +bit 06_06 +bit 06_07 +bit 06_08 +bit 06_09 +bit 06_10 +bit 06_100 +bit 06_101 +bit 06_102 +bit 06_103 +bit 06_104 +bit 06_105 +bit 06_106 +bit 06_107 +bit 06_108 +bit 06_109 +bit 06_11 +bit 06_110 +bit 06_111 +bit 06_112 +bit 06_113 +bit 06_114 +bit 06_115 +bit 06_116 +bit 06_117 +bit 06_118 +bit 06_119 +bit 06_12 +bit 06_120 +bit 06_121 +bit 06_122 +bit 06_123 +bit 06_124 +bit 06_125 +bit 06_126 +bit 06_127 +bit 06_128 +bit 06_129 +bit 06_13 +bit 06_130 +bit 06_131 +bit 06_132 +bit 06_133 +bit 06_134 +bit 06_135 +bit 06_136 +bit 06_137 +bit 06_138 +bit 06_139 +bit 06_14 +bit 06_140 +bit 06_141 +bit 06_142 +bit 06_143 +bit 06_144 +bit 06_145 +bit 06_146 +bit 06_147 +bit 06_148 +bit 06_149 +bit 06_15 +bit 06_150 +bit 06_151 +bit 06_152 +bit 06_153 +bit 06_154 +bit 06_155 +bit 06_156 +bit 06_157 +bit 06_158 +bit 06_159 +bit 06_16 +bit 06_160 +bit 06_161 +bit 06_162 +bit 06_163 +bit 06_164 +bit 06_165 +bit 06_166 +bit 06_167 +bit 06_168 +bit 06_169 +bit 06_17 +bit 06_170 +bit 06_171 +bit 06_172 +bit 06_173 +bit 06_174 +bit 06_175 +bit 06_176 +bit 06_177 +bit 06_178 +bit 06_179 +bit 06_18 +bit 06_180 +bit 06_181 +bit 06_182 +bit 06_183 +bit 06_184 +bit 06_185 +bit 06_186 +bit 06_187 +bit 06_188 +bit 06_189 +bit 06_19 +bit 06_190 +bit 06_191 +bit 06_192 +bit 06_193 +bit 06_194 +bit 06_195 +bit 06_196 +bit 06_197 +bit 06_198 +bit 06_199 +bit 06_20 +bit 06_200 +bit 06_201 +bit 06_202 +bit 06_203 +bit 06_204 +bit 06_205 +bit 06_206 +bit 06_207 +bit 06_208 +bit 06_209 +bit 06_21 +bit 06_210 +bit 06_211 +bit 06_212 +bit 06_213 +bit 06_214 +bit 06_215 +bit 06_216 +bit 06_217 +bit 06_218 +bit 06_219 +bit 06_22 +bit 06_220 +bit 06_221 +bit 06_222 +bit 06_223 +bit 06_224 +bit 06_225 +bit 06_226 +bit 06_227 +bit 06_228 +bit 06_229 +bit 06_23 +bit 06_230 +bit 06_231 +bit 06_232 +bit 06_233 +bit 06_234 +bit 06_235 +bit 06_236 +bit 06_237 +bit 06_238 +bit 06_239 +bit 06_24 +bit 06_240 +bit 06_241 +bit 06_242 +bit 06_243 +bit 06_244 +bit 06_245 +bit 06_246 +bit 06_247 +bit 06_248 +bit 06_249 +bit 06_25 +bit 06_250 +bit 06_251 +bit 06_252 +bit 06_253 +bit 06_254 +bit 06_255 +bit 06_256 +bit 06_257 +bit 06_258 +bit 06_259 +bit 06_26 +bit 06_260 +bit 06_261 +bit 06_262 +bit 06_263 +bit 06_264 +bit 06_265 +bit 06_266 +bit 06_267 +bit 06_268 +bit 06_269 +bit 06_27 +bit 06_270 +bit 06_271 +bit 06_272 +bit 06_273 +bit 06_274 +bit 06_275 +bit 06_276 +bit 06_277 +bit 06_278 +bit 06_279 +bit 06_28 +bit 06_280 +bit 06_281 +bit 06_282 +bit 06_283 +bit 06_284 +bit 06_285 +bit 06_286 +bit 06_287 +bit 06_288 +bit 06_289 +bit 06_29 +bit 06_290 +bit 06_291 +bit 06_292 +bit 06_293 +bit 06_294 +bit 06_295 +bit 06_296 +bit 06_297 +bit 06_298 +bit 06_299 +bit 06_30 +bit 06_300 +bit 06_301 +bit 06_302 +bit 06_303 +bit 06_304 +bit 06_305 +bit 06_306 +bit 06_307 +bit 06_308 +bit 06_309 +bit 06_31 +bit 06_310 +bit 06_311 +bit 06_312 +bit 06_313 +bit 06_314 +bit 06_315 +bit 06_316 +bit 06_317 +bit 06_318 +bit 06_319 +bit 06_32 +bit 06_33 +bit 06_34 +bit 06_35 +bit 06_36 +bit 06_37 +bit 06_38 +bit 06_39 +bit 06_40 +bit 06_41 +bit 06_42 +bit 06_43 +bit 06_44 +bit 06_45 +bit 06_46 +bit 06_47 +bit 06_48 +bit 06_49 +bit 06_50 +bit 06_51 +bit 06_52 +bit 06_53 +bit 06_54 +bit 06_55 +bit 06_56 +bit 06_57 +bit 06_58 +bit 06_59 +bit 06_60 +bit 06_61 +bit 06_62 +bit 06_63 +bit 06_64 +bit 06_65 +bit 06_66 +bit 06_67 +bit 06_68 +bit 06_69 +bit 06_70 +bit 06_71 +bit 06_72 +bit 06_73 +bit 06_74 +bit 06_75 +bit 06_76 +bit 06_77 +bit 06_78 +bit 06_79 +bit 06_80 +bit 06_81 +bit 06_82 +bit 06_83 +bit 06_84 +bit 06_85 +bit 06_86 +bit 06_87 +bit 06_88 +bit 06_89 +bit 06_90 +bit 06_91 +bit 06_92 +bit 06_93 +bit 06_94 +bit 06_95 +bit 06_96 +bit 06_97 +bit 06_98 +bit 06_99 +bit 07_00 +bit 07_01 +bit 07_02 +bit 07_03 +bit 07_04 +bit 07_05 +bit 07_06 +bit 07_07 +bit 07_08 +bit 07_09 +bit 07_10 +bit 07_100 +bit 07_101 +bit 07_102 +bit 07_103 +bit 07_104 +bit 07_105 +bit 07_106 +bit 07_107 +bit 07_108 +bit 07_109 +bit 07_11 +bit 07_110 +bit 07_111 +bit 07_112 +bit 07_113 +bit 07_114 +bit 07_115 +bit 07_116 +bit 07_117 +bit 07_118 +bit 07_119 +bit 07_12 +bit 07_120 +bit 07_121 +bit 07_122 +bit 07_123 +bit 07_124 +bit 07_125 +bit 07_126 +bit 07_127 +bit 07_128 +bit 07_129 +bit 07_13 +bit 07_130 +bit 07_131 +bit 07_132 +bit 07_133 +bit 07_134 +bit 07_135 +bit 07_136 +bit 07_137 +bit 07_138 +bit 07_139 +bit 07_14 +bit 07_140 +bit 07_141 +bit 07_142 +bit 07_143 +bit 07_144 +bit 07_145 +bit 07_146 +bit 07_147 +bit 07_148 +bit 07_149 +bit 07_15 +bit 07_150 +bit 07_151 +bit 07_152 +bit 07_153 +bit 07_154 +bit 07_155 +bit 07_156 +bit 07_157 +bit 07_158 +bit 07_159 +bit 07_16 +bit 07_160 +bit 07_161 +bit 07_162 +bit 07_163 +bit 07_164 +bit 07_165 +bit 07_166 +bit 07_167 +bit 07_168 +bit 07_169 +bit 07_17 +bit 07_170 +bit 07_171 +bit 07_172 +bit 07_173 +bit 07_174 +bit 07_175 +bit 07_176 +bit 07_177 +bit 07_178 +bit 07_179 +bit 07_18 +bit 07_180 +bit 07_181 +bit 07_182 +bit 07_183 +bit 07_184 +bit 07_185 +bit 07_186 +bit 07_187 +bit 07_188 +bit 07_189 +bit 07_19 +bit 07_190 +bit 07_191 +bit 07_192 +bit 07_193 +bit 07_194 +bit 07_195 +bit 07_196 +bit 07_197 +bit 07_198 +bit 07_199 +bit 07_20 +bit 07_200 +bit 07_201 +bit 07_202 +bit 07_203 +bit 07_204 +bit 07_205 +bit 07_206 +bit 07_207 +bit 07_208 +bit 07_209 +bit 07_21 +bit 07_210 +bit 07_211 +bit 07_212 +bit 07_213 +bit 07_214 +bit 07_215 +bit 07_216 +bit 07_217 +bit 07_218 +bit 07_219 +bit 07_22 +bit 07_220 +bit 07_221 +bit 07_222 +bit 07_223 +bit 07_224 +bit 07_225 +bit 07_226 +bit 07_227 +bit 07_228 +bit 07_229 +bit 07_23 +bit 07_230 +bit 07_231 +bit 07_232 +bit 07_233 +bit 07_234 +bit 07_235 +bit 07_236 +bit 07_237 +bit 07_238 +bit 07_239 +bit 07_24 +bit 07_240 +bit 07_241 +bit 07_242 +bit 07_243 +bit 07_244 +bit 07_245 +bit 07_246 +bit 07_247 +bit 07_248 +bit 07_249 +bit 07_25 +bit 07_250 +bit 07_251 +bit 07_252 +bit 07_253 +bit 07_254 +bit 07_255 +bit 07_256 +bit 07_257 +bit 07_258 +bit 07_259 +bit 07_26 +bit 07_260 +bit 07_261 +bit 07_262 +bit 07_263 +bit 07_264 +bit 07_265 +bit 07_266 +bit 07_267 +bit 07_268 +bit 07_269 +bit 07_27 +bit 07_270 +bit 07_271 +bit 07_272 +bit 07_273 +bit 07_274 +bit 07_275 +bit 07_276 +bit 07_277 +bit 07_278 +bit 07_279 +bit 07_28 +bit 07_280 +bit 07_281 +bit 07_282 +bit 07_283 +bit 07_284 +bit 07_285 +bit 07_286 +bit 07_287 +bit 07_288 +bit 07_289 +bit 07_29 +bit 07_290 +bit 07_291 +bit 07_292 +bit 07_293 +bit 07_294 +bit 07_295 +bit 07_296 +bit 07_297 +bit 07_298 +bit 07_299 +bit 07_30 +bit 07_300 +bit 07_301 +bit 07_302 +bit 07_303 +bit 07_304 +bit 07_305 +bit 07_306 +bit 07_307 +bit 07_308 +bit 07_309 +bit 07_31 +bit 07_310 +bit 07_311 +bit 07_312 +bit 07_313 +bit 07_314 +bit 07_315 +bit 07_316 +bit 07_317 +bit 07_318 +bit 07_319 +bit 07_32 +bit 07_33 +bit 07_34 +bit 07_35 +bit 07_36 +bit 07_37 +bit 07_38 +bit 07_39 +bit 07_40 +bit 07_41 +bit 07_42 +bit 07_43 +bit 07_44 +bit 07_45 +bit 07_46 +bit 07_47 +bit 07_48 +bit 07_49 +bit 07_50 +bit 07_51 +bit 07_52 +bit 07_53 +bit 07_54 +bit 07_55 +bit 07_56 +bit 07_57 +bit 07_58 +bit 07_59 +bit 07_60 +bit 07_61 +bit 07_62 +bit 07_63 +bit 07_64 +bit 07_65 +bit 07_66 +bit 07_67 +bit 07_68 +bit 07_69 +bit 07_70 +bit 07_71 +bit 07_72 +bit 07_73 +bit 07_74 +bit 07_75 +bit 07_76 +bit 07_77 +bit 07_78 +bit 07_79 +bit 07_80 +bit 07_81 +bit 07_82 +bit 07_83 +bit 07_84 +bit 07_85 +bit 07_86 +bit 07_87 +bit 07_88 +bit 07_89 +bit 07_90 +bit 07_91 +bit 07_92 +bit 07_93 +bit 07_94 +bit 07_95 +bit 07_96 +bit 07_97 +bit 07_98 +bit 07_99 +bit 08_00 +bit 08_01 +bit 08_02 +bit 08_03 +bit 08_04 +bit 08_05 +bit 08_06 +bit 08_07 +bit 08_08 +bit 08_09 +bit 08_10 +bit 08_100 +bit 08_101 +bit 08_102 +bit 08_103 +bit 08_104 +bit 08_105 +bit 08_106 +bit 08_107 +bit 08_108 +bit 08_109 +bit 08_11 +bit 08_110 +bit 08_111 +bit 08_112 +bit 08_113 +bit 08_114 +bit 08_115 +bit 08_116 +bit 08_117 +bit 08_118 +bit 08_119 +bit 08_12 +bit 08_120 +bit 08_121 +bit 08_122 +bit 08_123 +bit 08_124 +bit 08_125 +bit 08_126 +bit 08_127 +bit 08_128 +bit 08_129 +bit 08_13 +bit 08_130 +bit 08_131 +bit 08_132 +bit 08_133 +bit 08_134 +bit 08_135 +bit 08_136 +bit 08_137 +bit 08_138 +bit 08_139 +bit 08_14 +bit 08_140 +bit 08_141 +bit 08_142 +bit 08_143 +bit 08_144 +bit 08_145 +bit 08_146 +bit 08_147 +bit 08_148 +bit 08_149 +bit 08_15 +bit 08_150 +bit 08_151 +bit 08_152 +bit 08_153 +bit 08_154 +bit 08_155 +bit 08_156 +bit 08_157 +bit 08_158 +bit 08_159 +bit 08_16 +bit 08_160 +bit 08_161 +bit 08_162 +bit 08_163 +bit 08_164 +bit 08_165 +bit 08_166 +bit 08_167 +bit 08_168 +bit 08_169 +bit 08_17 +bit 08_170 +bit 08_171 +bit 08_172 +bit 08_173 +bit 08_174 +bit 08_175 +bit 08_176 +bit 08_177 +bit 08_178 +bit 08_179 +bit 08_18 +bit 08_180 +bit 08_181 +bit 08_182 +bit 08_183 +bit 08_184 +bit 08_185 +bit 08_186 +bit 08_187 +bit 08_188 +bit 08_189 +bit 08_19 +bit 08_190 +bit 08_191 +bit 08_192 +bit 08_193 +bit 08_194 +bit 08_195 +bit 08_196 +bit 08_197 +bit 08_198 +bit 08_199 +bit 08_20 +bit 08_200 +bit 08_201 +bit 08_202 +bit 08_203 +bit 08_204 +bit 08_205 +bit 08_206 +bit 08_207 +bit 08_208 +bit 08_209 +bit 08_21 +bit 08_210 +bit 08_211 +bit 08_212 +bit 08_213 +bit 08_214 +bit 08_215 +bit 08_216 +bit 08_217 +bit 08_218 +bit 08_219 +bit 08_22 +bit 08_220 +bit 08_221 +bit 08_222 +bit 08_223 +bit 08_224 +bit 08_225 +bit 08_226 +bit 08_227 +bit 08_228 +bit 08_229 +bit 08_23 +bit 08_230 +bit 08_231 +bit 08_232 +bit 08_233 +bit 08_234 +bit 08_235 +bit 08_236 +bit 08_237 +bit 08_238 +bit 08_239 +bit 08_24 +bit 08_240 +bit 08_241 +bit 08_242 +bit 08_243 +bit 08_244 +bit 08_245 +bit 08_246 +bit 08_247 +bit 08_248 +bit 08_249 +bit 08_25 +bit 08_250 +bit 08_251 +bit 08_252 +bit 08_253 +bit 08_254 +bit 08_255 +bit 08_256 +bit 08_257 +bit 08_258 +bit 08_259 +bit 08_26 +bit 08_260 +bit 08_261 +bit 08_262 +bit 08_263 +bit 08_264 +bit 08_265 +bit 08_266 +bit 08_267 +bit 08_268 +bit 08_269 +bit 08_27 +bit 08_270 +bit 08_271 +bit 08_272 +bit 08_273 +bit 08_274 +bit 08_275 +bit 08_276 +bit 08_277 +bit 08_278 +bit 08_279 +bit 08_28 +bit 08_280 +bit 08_281 +bit 08_282 +bit 08_283 +bit 08_284 +bit 08_285 +bit 08_286 +bit 08_287 +bit 08_288 +bit 08_289 +bit 08_29 +bit 08_290 +bit 08_291 +bit 08_292 +bit 08_293 +bit 08_294 +bit 08_295 +bit 08_296 +bit 08_297 +bit 08_298 +bit 08_299 +bit 08_30 +bit 08_300 +bit 08_301 +bit 08_302 +bit 08_303 +bit 08_304 +bit 08_305 +bit 08_306 +bit 08_307 +bit 08_308 +bit 08_309 +bit 08_31 +bit 08_310 +bit 08_311 +bit 08_312 +bit 08_313 +bit 08_314 +bit 08_315 +bit 08_316 +bit 08_317 +bit 08_318 +bit 08_319 +bit 08_32 +bit 08_33 +bit 08_34 +bit 08_35 +bit 08_36 +bit 08_37 +bit 08_38 +bit 08_39 +bit 08_40 +bit 08_41 +bit 08_42 +bit 08_43 +bit 08_44 +bit 08_45 +bit 08_46 +bit 08_47 +bit 08_48 +bit 08_49 +bit 08_50 +bit 08_51 +bit 08_52 +bit 08_53 +bit 08_54 +bit 08_55 +bit 08_56 +bit 08_57 +bit 08_58 +bit 08_59 +bit 08_60 +bit 08_61 +bit 08_62 +bit 08_63 +bit 08_64 +bit 08_65 +bit 08_66 +bit 08_67 +bit 08_68 +bit 08_69 +bit 08_70 +bit 08_71 +bit 08_72 +bit 08_73 +bit 08_74 +bit 08_75 +bit 08_76 +bit 08_77 +bit 08_78 +bit 08_79 +bit 08_80 +bit 08_81 +bit 08_82 +bit 08_83 +bit 08_84 +bit 08_85 +bit 08_86 +bit 08_87 +bit 08_88 +bit 08_89 +bit 08_90 +bit 08_91 +bit 08_92 +bit 08_93 +bit 08_94 +bit 08_95 +bit 08_96 +bit 08_97 +bit 08_98 +bit 08_99 +bit 09_00 +bit 09_01 +bit 09_02 +bit 09_03 +bit 09_04 +bit 09_05 +bit 09_06 +bit 09_07 +bit 09_08 +bit 09_09 +bit 09_10 +bit 09_100 +bit 09_101 +bit 09_102 +bit 09_103 +bit 09_104 +bit 09_105 +bit 09_106 +bit 09_107 +bit 09_108 +bit 09_109 +bit 09_11 +bit 09_110 +bit 09_111 +bit 09_112 +bit 09_113 +bit 09_114 +bit 09_115 +bit 09_116 +bit 09_117 +bit 09_118 +bit 09_119 +bit 09_12 +bit 09_120 +bit 09_121 +bit 09_122 +bit 09_123 +bit 09_124 +bit 09_125 +bit 09_126 +bit 09_127 +bit 09_128 +bit 09_129 +bit 09_13 +bit 09_130 +bit 09_131 +bit 09_132 +bit 09_133 +bit 09_134 +bit 09_135 +bit 09_136 +bit 09_137 +bit 09_138 +bit 09_139 +bit 09_14 +bit 09_140 +bit 09_141 +bit 09_142 +bit 09_143 +bit 09_144 +bit 09_145 +bit 09_146 +bit 09_147 +bit 09_148 +bit 09_149 +bit 09_15 +bit 09_150 +bit 09_151 +bit 09_152 +bit 09_153 +bit 09_154 +bit 09_155 +bit 09_156 +bit 09_157 +bit 09_158 +bit 09_159 +bit 09_16 +bit 09_160 +bit 09_161 +bit 09_162 +bit 09_163 +bit 09_164 +bit 09_165 +bit 09_166 +bit 09_167 +bit 09_168 +bit 09_169 +bit 09_17 +bit 09_170 +bit 09_171 +bit 09_172 +bit 09_173 +bit 09_174 +bit 09_175 +bit 09_176 +bit 09_177 +bit 09_178 +bit 09_179 +bit 09_18 +bit 09_180 +bit 09_181 +bit 09_182 +bit 09_183 +bit 09_184 +bit 09_185 +bit 09_186 +bit 09_187 +bit 09_188 +bit 09_189 +bit 09_19 +bit 09_190 +bit 09_191 +bit 09_192 +bit 09_193 +bit 09_194 +bit 09_195 +bit 09_196 +bit 09_197 +bit 09_198 +bit 09_199 +bit 09_20 +bit 09_200 +bit 09_201 +bit 09_202 +bit 09_203 +bit 09_204 +bit 09_205 +bit 09_206 +bit 09_207 +bit 09_208 +bit 09_209 +bit 09_21 +bit 09_210 +bit 09_211 +bit 09_212 +bit 09_213 +bit 09_214 +bit 09_215 +bit 09_216 +bit 09_217 +bit 09_218 +bit 09_219 +bit 09_22 +bit 09_220 +bit 09_221 +bit 09_222 +bit 09_223 +bit 09_224 +bit 09_225 +bit 09_226 +bit 09_227 +bit 09_228 +bit 09_229 +bit 09_23 +bit 09_230 +bit 09_231 +bit 09_232 +bit 09_233 +bit 09_234 +bit 09_235 +bit 09_236 +bit 09_237 +bit 09_238 +bit 09_239 +bit 09_24 +bit 09_240 +bit 09_241 +bit 09_242 +bit 09_243 +bit 09_244 +bit 09_245 +bit 09_246 +bit 09_247 +bit 09_248 +bit 09_249 +bit 09_25 +bit 09_250 +bit 09_251 +bit 09_252 +bit 09_253 +bit 09_254 +bit 09_255 +bit 09_256 +bit 09_257 +bit 09_258 +bit 09_259 +bit 09_26 +bit 09_260 +bit 09_261 +bit 09_262 +bit 09_263 +bit 09_264 +bit 09_265 +bit 09_266 +bit 09_267 +bit 09_268 +bit 09_269 +bit 09_27 +bit 09_270 +bit 09_271 +bit 09_272 +bit 09_273 +bit 09_274 +bit 09_275 +bit 09_276 +bit 09_277 +bit 09_278 +bit 09_279 +bit 09_28 +bit 09_280 +bit 09_281 +bit 09_282 +bit 09_283 +bit 09_284 +bit 09_285 +bit 09_286 +bit 09_287 +bit 09_288 +bit 09_289 +bit 09_29 +bit 09_290 +bit 09_291 +bit 09_292 +bit 09_293 +bit 09_294 +bit 09_295 +bit 09_296 +bit 09_297 +bit 09_298 +bit 09_299 +bit 09_30 +bit 09_300 +bit 09_301 +bit 09_302 +bit 09_303 +bit 09_304 +bit 09_305 +bit 09_306 +bit 09_307 +bit 09_308 +bit 09_309 +bit 09_31 +bit 09_310 +bit 09_311 +bit 09_312 +bit 09_313 +bit 09_314 +bit 09_315 +bit 09_316 +bit 09_317 +bit 09_318 +bit 09_319 +bit 09_32 +bit 09_33 +bit 09_34 +bit 09_35 +bit 09_36 +bit 09_37 +bit 09_38 +bit 09_39 +bit 09_40 +bit 09_41 +bit 09_42 +bit 09_43 +bit 09_44 +bit 09_45 +bit 09_46 +bit 09_47 +bit 09_48 +bit 09_49 +bit 09_50 +bit 09_51 +bit 09_52 +bit 09_53 +bit 09_54 +bit 09_55 +bit 09_56 +bit 09_57 +bit 09_58 +bit 09_59 +bit 09_60 +bit 09_61 +bit 09_62 +bit 09_63 +bit 09_64 +bit 09_65 +bit 09_66 +bit 09_67 +bit 09_68 +bit 09_69 +bit 09_70 +bit 09_71 +bit 09_72 +bit 09_73 +bit 09_74 +bit 09_75 +bit 09_76 +bit 09_77 +bit 09_78 +bit 09_79 +bit 09_80 +bit 09_81 +bit 09_82 +bit 09_83 +bit 09_84 +bit 09_85 +bit 09_86 +bit 09_87 +bit 09_88 +bit 09_89 +bit 09_90 +bit 09_91 +bit 09_92 +bit 09_93 +bit 09_94 +bit 09_95 +bit 09_96 +bit 09_97 +bit 09_98 +bit 09_99 +bit 10_00 +bit 10_01 +bit 10_02 +bit 10_03 +bit 10_04 +bit 10_05 +bit 10_06 +bit 10_07 +bit 10_08 +bit 10_09 +bit 10_10 +bit 10_100 +bit 10_101 +bit 10_102 +bit 10_103 +bit 10_104 +bit 10_105 +bit 10_106 +bit 10_107 +bit 10_108 +bit 10_109 +bit 10_11 +bit 10_110 +bit 10_111 +bit 10_112 +bit 10_113 +bit 10_114 +bit 10_115 +bit 10_116 +bit 10_117 +bit 10_118 +bit 10_119 +bit 10_12 +bit 10_120 +bit 10_121 +bit 10_122 +bit 10_123 +bit 10_124 +bit 10_125 +bit 10_126 +bit 10_127 +bit 10_128 +bit 10_129 +bit 10_13 +bit 10_130 +bit 10_131 +bit 10_132 +bit 10_133 +bit 10_134 +bit 10_135 +bit 10_136 +bit 10_137 +bit 10_138 +bit 10_139 +bit 10_14 +bit 10_140 +bit 10_141 +bit 10_142 +bit 10_143 +bit 10_144 +bit 10_145 +bit 10_146 +bit 10_147 +bit 10_148 +bit 10_149 +bit 10_15 +bit 10_150 +bit 10_151 +bit 10_152 +bit 10_153 +bit 10_154 +bit 10_155 +bit 10_156 +bit 10_157 +bit 10_158 +bit 10_159 +bit 10_16 +bit 10_160 +bit 10_161 +bit 10_162 +bit 10_163 +bit 10_164 +bit 10_165 +bit 10_166 +bit 10_167 +bit 10_168 +bit 10_169 +bit 10_17 +bit 10_170 +bit 10_171 +bit 10_172 +bit 10_173 +bit 10_174 +bit 10_175 +bit 10_176 +bit 10_177 +bit 10_178 +bit 10_179 +bit 10_18 +bit 10_180 +bit 10_181 +bit 10_182 +bit 10_183 +bit 10_184 +bit 10_185 +bit 10_186 +bit 10_187 +bit 10_188 +bit 10_189 +bit 10_19 +bit 10_190 +bit 10_191 +bit 10_192 +bit 10_193 +bit 10_194 +bit 10_195 +bit 10_196 +bit 10_197 +bit 10_198 +bit 10_199 +bit 10_20 +bit 10_200 +bit 10_201 +bit 10_202 +bit 10_203 +bit 10_204 +bit 10_205 +bit 10_206 +bit 10_207 +bit 10_208 +bit 10_209 +bit 10_21 +bit 10_210 +bit 10_211 +bit 10_212 +bit 10_213 +bit 10_214 +bit 10_215 +bit 10_216 +bit 10_217 +bit 10_218 +bit 10_219 +bit 10_22 +bit 10_220 +bit 10_221 +bit 10_222 +bit 10_223 +bit 10_224 +bit 10_225 +bit 10_226 +bit 10_227 +bit 10_228 +bit 10_229 +bit 10_23 +bit 10_230 +bit 10_231 +bit 10_232 +bit 10_233 +bit 10_234 +bit 10_235 +bit 10_236 +bit 10_237 +bit 10_238 +bit 10_239 +bit 10_24 +bit 10_240 +bit 10_241 +bit 10_242 +bit 10_243 +bit 10_244 +bit 10_245 +bit 10_246 +bit 10_247 +bit 10_248 +bit 10_249 +bit 10_25 +bit 10_250 +bit 10_251 +bit 10_252 +bit 10_253 +bit 10_254 +bit 10_255 +bit 10_256 +bit 10_257 +bit 10_258 +bit 10_259 +bit 10_26 +bit 10_260 +bit 10_261 +bit 10_262 +bit 10_263 +bit 10_264 +bit 10_265 +bit 10_266 +bit 10_267 +bit 10_268 +bit 10_269 +bit 10_27 +bit 10_270 +bit 10_271 +bit 10_272 +bit 10_273 +bit 10_274 +bit 10_275 +bit 10_276 +bit 10_277 +bit 10_278 +bit 10_279 +bit 10_28 +bit 10_280 +bit 10_281 +bit 10_282 +bit 10_283 +bit 10_284 +bit 10_285 +bit 10_286 +bit 10_287 +bit 10_288 +bit 10_289 +bit 10_29 +bit 10_290 +bit 10_291 +bit 10_292 +bit 10_293 +bit 10_294 +bit 10_295 +bit 10_296 +bit 10_297 +bit 10_298 +bit 10_299 +bit 10_30 +bit 10_300 +bit 10_301 +bit 10_302 +bit 10_303 +bit 10_304 +bit 10_305 +bit 10_306 +bit 10_307 +bit 10_308 +bit 10_309 +bit 10_31 +bit 10_310 +bit 10_311 +bit 10_312 +bit 10_313 +bit 10_314 +bit 10_315 +bit 10_316 +bit 10_317 +bit 10_318 +bit 10_319 +bit 10_32 +bit 10_33 +bit 10_34 +bit 10_35 +bit 10_36 +bit 10_37 +bit 10_38 +bit 10_39 +bit 10_40 +bit 10_41 +bit 10_42 +bit 10_43 +bit 10_44 +bit 10_45 +bit 10_46 +bit 10_47 +bit 10_48 +bit 10_49 +bit 10_50 +bit 10_51 +bit 10_52 +bit 10_53 +bit 10_54 +bit 10_55 +bit 10_56 +bit 10_57 +bit 10_58 +bit 10_59 +bit 10_60 +bit 10_61 +bit 10_62 +bit 10_63 +bit 10_64 +bit 10_65 +bit 10_66 +bit 10_67 +bit 10_68 +bit 10_69 +bit 10_70 +bit 10_71 +bit 10_72 +bit 10_73 +bit 10_74 +bit 10_75 +bit 10_76 +bit 10_77 +bit 10_78 +bit 10_79 +bit 10_80 +bit 10_81 +bit 10_82 +bit 10_83 +bit 10_84 +bit 10_85 +bit 10_86 +bit 10_87 +bit 10_88 +bit 10_89 +bit 10_90 +bit 10_91 +bit 10_92 +bit 10_93 +bit 10_94 +bit 10_95 +bit 10_96 +bit 10_97 +bit 10_98 +bit 10_99 +bit 11_00 +bit 11_01 +bit 11_02 +bit 11_03 +bit 11_04 +bit 11_05 +bit 11_06 +bit 11_07 +bit 11_08 +bit 11_09 +bit 11_10 +bit 11_100 +bit 11_101 +bit 11_102 +bit 11_103 +bit 11_104 +bit 11_105 +bit 11_106 +bit 11_107 +bit 11_108 +bit 11_109 +bit 11_11 +bit 11_110 +bit 11_111 +bit 11_112 +bit 11_113 +bit 11_114 +bit 11_115 +bit 11_116 +bit 11_117 +bit 11_118 +bit 11_119 +bit 11_12 +bit 11_120 +bit 11_121 +bit 11_122 +bit 11_123 +bit 11_124 +bit 11_125 +bit 11_126 +bit 11_127 +bit 11_128 +bit 11_129 +bit 11_13 +bit 11_130 +bit 11_131 +bit 11_132 +bit 11_133 +bit 11_134 +bit 11_135 +bit 11_136 +bit 11_137 +bit 11_138 +bit 11_139 +bit 11_14 +bit 11_140 +bit 11_141 +bit 11_142 +bit 11_143 +bit 11_144 +bit 11_145 +bit 11_146 +bit 11_147 +bit 11_148 +bit 11_149 +bit 11_15 +bit 11_150 +bit 11_151 +bit 11_152 +bit 11_153 +bit 11_154 +bit 11_155 +bit 11_156 +bit 11_157 +bit 11_158 +bit 11_159 +bit 11_16 +bit 11_160 +bit 11_161 +bit 11_162 +bit 11_163 +bit 11_164 +bit 11_165 +bit 11_166 +bit 11_167 +bit 11_168 +bit 11_169 +bit 11_17 +bit 11_170 +bit 11_171 +bit 11_172 +bit 11_173 +bit 11_174 +bit 11_175 +bit 11_176 +bit 11_177 +bit 11_178 +bit 11_179 +bit 11_18 +bit 11_180 +bit 11_181 +bit 11_182 +bit 11_183 +bit 11_184 +bit 11_185 +bit 11_186 +bit 11_187 +bit 11_188 +bit 11_189 +bit 11_19 +bit 11_190 +bit 11_191 +bit 11_192 +bit 11_193 +bit 11_194 +bit 11_195 +bit 11_196 +bit 11_197 +bit 11_198 +bit 11_199 +bit 11_20 +bit 11_200 +bit 11_201 +bit 11_202 +bit 11_203 +bit 11_204 +bit 11_205 +bit 11_206 +bit 11_207 +bit 11_208 +bit 11_209 +bit 11_21 +bit 11_210 +bit 11_211 +bit 11_212 +bit 11_213 +bit 11_214 +bit 11_215 +bit 11_216 +bit 11_217 +bit 11_218 +bit 11_219 +bit 11_22 +bit 11_220 +bit 11_221 +bit 11_222 +bit 11_223 +bit 11_224 +bit 11_225 +bit 11_226 +bit 11_227 +bit 11_228 +bit 11_229 +bit 11_23 +bit 11_230 +bit 11_231 +bit 11_232 +bit 11_233 +bit 11_234 +bit 11_235 +bit 11_236 +bit 11_237 +bit 11_238 +bit 11_239 +bit 11_24 +bit 11_240 +bit 11_241 +bit 11_242 +bit 11_243 +bit 11_244 +bit 11_245 +bit 11_246 +bit 11_247 +bit 11_248 +bit 11_249 +bit 11_25 +bit 11_250 +bit 11_251 +bit 11_252 +bit 11_253 +bit 11_254 +bit 11_255 +bit 11_256 +bit 11_257 +bit 11_258 +bit 11_259 +bit 11_26 +bit 11_260 +bit 11_261 +bit 11_262 +bit 11_263 +bit 11_264 +bit 11_265 +bit 11_266 +bit 11_267 +bit 11_268 +bit 11_269 +bit 11_27 +bit 11_270 +bit 11_271 +bit 11_272 +bit 11_273 +bit 11_274 +bit 11_275 +bit 11_276 +bit 11_277 +bit 11_278 +bit 11_279 +bit 11_28 +bit 11_280 +bit 11_281 +bit 11_282 +bit 11_283 +bit 11_284 +bit 11_285 +bit 11_286 +bit 11_287 +bit 11_288 +bit 11_289 +bit 11_29 +bit 11_290 +bit 11_291 +bit 11_292 +bit 11_293 +bit 11_294 +bit 11_295 +bit 11_296 +bit 11_297 +bit 11_298 +bit 11_299 +bit 11_30 +bit 11_300 +bit 11_301 +bit 11_302 +bit 11_303 +bit 11_304 +bit 11_305 +bit 11_306 +bit 11_307 +bit 11_308 +bit 11_309 +bit 11_31 +bit 11_310 +bit 11_311 +bit 11_312 +bit 11_313 +bit 11_314 +bit 11_315 +bit 11_316 +bit 11_317 +bit 11_318 +bit 11_319 +bit 11_32 +bit 11_33 +bit 11_34 +bit 11_35 +bit 11_36 +bit 11_37 +bit 11_38 +bit 11_39 +bit 11_40 +bit 11_41 +bit 11_42 +bit 11_43 +bit 11_44 +bit 11_45 +bit 11_46 +bit 11_47 +bit 11_48 +bit 11_49 +bit 11_50 +bit 11_51 +bit 11_52 +bit 11_53 +bit 11_54 +bit 11_55 +bit 11_56 +bit 11_57 +bit 11_58 +bit 11_59 +bit 11_60 +bit 11_61 +bit 11_62 +bit 11_63 +bit 11_64 +bit 11_65 +bit 11_66 +bit 11_67 +bit 11_68 +bit 11_69 +bit 11_70 +bit 11_71 +bit 11_72 +bit 11_73 +bit 11_74 +bit 11_75 +bit 11_76 +bit 11_77 +bit 11_78 +bit 11_79 +bit 11_80 +bit 11_81 +bit 11_82 +bit 11_83 +bit 11_84 +bit 11_85 +bit 11_86 +bit 11_87 +bit 11_88 +bit 11_89 +bit 11_90 +bit 11_91 +bit 11_92 +bit 11_93 +bit 11_94 +bit 11_95 +bit 11_96 +bit 11_97 +bit 11_98 +bit 11_99 +bit 12_00 +bit 12_01 +bit 12_02 +bit 12_03 +bit 12_04 +bit 12_05 +bit 12_06 +bit 12_07 +bit 12_08 +bit 12_09 +bit 12_10 +bit 12_100 +bit 12_101 +bit 12_102 +bit 12_103 +bit 12_104 +bit 12_105 +bit 12_106 +bit 12_107 +bit 12_108 +bit 12_109 +bit 12_11 +bit 12_110 +bit 12_111 +bit 12_112 +bit 12_113 +bit 12_114 +bit 12_115 +bit 12_116 +bit 12_117 +bit 12_118 +bit 12_119 +bit 12_12 +bit 12_120 +bit 12_121 +bit 12_122 +bit 12_123 +bit 12_124 +bit 12_125 +bit 12_126 +bit 12_127 +bit 12_128 +bit 12_129 +bit 12_13 +bit 12_130 +bit 12_131 +bit 12_132 +bit 12_133 +bit 12_134 +bit 12_135 +bit 12_136 +bit 12_137 +bit 12_138 +bit 12_139 +bit 12_14 +bit 12_140 +bit 12_141 +bit 12_142 +bit 12_143 +bit 12_144 +bit 12_145 +bit 12_146 +bit 12_147 +bit 12_148 +bit 12_149 +bit 12_15 +bit 12_150 +bit 12_151 +bit 12_152 +bit 12_153 +bit 12_154 +bit 12_155 +bit 12_156 +bit 12_157 +bit 12_158 +bit 12_159 +bit 12_16 +bit 12_160 +bit 12_161 +bit 12_162 +bit 12_163 +bit 12_164 +bit 12_165 +bit 12_166 +bit 12_167 +bit 12_168 +bit 12_169 +bit 12_17 +bit 12_170 +bit 12_171 +bit 12_172 +bit 12_173 +bit 12_174 +bit 12_175 +bit 12_176 +bit 12_177 +bit 12_178 +bit 12_179 +bit 12_18 +bit 12_180 +bit 12_181 +bit 12_182 +bit 12_183 +bit 12_184 +bit 12_185 +bit 12_186 +bit 12_187 +bit 12_188 +bit 12_189 +bit 12_19 +bit 12_190 +bit 12_191 +bit 12_192 +bit 12_193 +bit 12_194 +bit 12_195 +bit 12_196 +bit 12_197 +bit 12_198 +bit 12_199 +bit 12_20 +bit 12_200 +bit 12_201 +bit 12_202 +bit 12_203 +bit 12_204 +bit 12_205 +bit 12_206 +bit 12_207 +bit 12_208 +bit 12_209 +bit 12_21 +bit 12_210 +bit 12_211 +bit 12_212 +bit 12_213 +bit 12_214 +bit 12_215 +bit 12_216 +bit 12_217 +bit 12_218 +bit 12_219 +bit 12_22 +bit 12_220 +bit 12_221 +bit 12_222 +bit 12_223 +bit 12_224 +bit 12_225 +bit 12_226 +bit 12_227 +bit 12_228 +bit 12_229 +bit 12_23 +bit 12_230 +bit 12_231 +bit 12_232 +bit 12_233 +bit 12_234 +bit 12_235 +bit 12_236 +bit 12_237 +bit 12_238 +bit 12_239 +bit 12_24 +bit 12_240 +bit 12_241 +bit 12_242 +bit 12_243 +bit 12_244 +bit 12_245 +bit 12_246 +bit 12_247 +bit 12_248 +bit 12_249 +bit 12_25 +bit 12_250 +bit 12_251 +bit 12_252 +bit 12_253 +bit 12_254 +bit 12_255 +bit 12_256 +bit 12_257 +bit 12_258 +bit 12_259 +bit 12_26 +bit 12_260 +bit 12_261 +bit 12_262 +bit 12_263 +bit 12_264 +bit 12_265 +bit 12_266 +bit 12_267 +bit 12_268 +bit 12_269 +bit 12_27 +bit 12_270 +bit 12_271 +bit 12_272 +bit 12_273 +bit 12_274 +bit 12_275 +bit 12_276 +bit 12_277 +bit 12_278 +bit 12_279 +bit 12_28 +bit 12_280 +bit 12_281 +bit 12_282 +bit 12_283 +bit 12_284 +bit 12_285 +bit 12_286 +bit 12_287 +bit 12_288 +bit 12_289 +bit 12_29 +bit 12_290 +bit 12_291 +bit 12_292 +bit 12_293 +bit 12_294 +bit 12_295 +bit 12_296 +bit 12_297 +bit 12_298 +bit 12_299 +bit 12_30 +bit 12_300 +bit 12_301 +bit 12_302 +bit 12_303 +bit 12_304 +bit 12_305 +bit 12_306 +bit 12_307 +bit 12_308 +bit 12_309 +bit 12_31 +bit 12_310 +bit 12_311 +bit 12_312 +bit 12_313 +bit 12_314 +bit 12_315 +bit 12_316 +bit 12_317 +bit 12_318 +bit 12_319 +bit 12_32 +bit 12_33 +bit 12_34 +bit 12_35 +bit 12_36 +bit 12_37 +bit 12_38 +bit 12_39 +bit 12_40 +bit 12_41 +bit 12_42 +bit 12_43 +bit 12_44 +bit 12_45 +bit 12_46 +bit 12_47 +bit 12_48 +bit 12_49 +bit 12_50 +bit 12_51 +bit 12_52 +bit 12_53 +bit 12_54 +bit 12_55 +bit 12_56 +bit 12_57 +bit 12_58 +bit 12_59 +bit 12_60 +bit 12_61 +bit 12_62 +bit 12_63 +bit 12_64 +bit 12_65 +bit 12_66 +bit 12_67 +bit 12_68 +bit 12_69 +bit 12_70 +bit 12_71 +bit 12_72 +bit 12_73 +bit 12_74 +bit 12_75 +bit 12_76 +bit 12_77 +bit 12_78 +bit 12_79 +bit 12_80 +bit 12_81 +bit 12_82 +bit 12_83 +bit 12_84 +bit 12_85 +bit 12_86 +bit 12_87 +bit 12_88 +bit 12_89 +bit 12_90 +bit 12_91 +bit 12_92 +bit 12_93 +bit 12_94 +bit 12_95 +bit 12_96 +bit 12_97 +bit 12_98 +bit 12_99 +bit 13_00 +bit 13_01 +bit 13_02 +bit 13_03 +bit 13_04 +bit 13_05 +bit 13_06 +bit 13_07 +bit 13_08 +bit 13_09 +bit 13_10 +bit 13_100 +bit 13_101 +bit 13_102 +bit 13_103 +bit 13_104 +bit 13_105 +bit 13_106 +bit 13_107 +bit 13_108 +bit 13_109 +bit 13_11 +bit 13_110 +bit 13_111 +bit 13_112 +bit 13_113 +bit 13_114 +bit 13_115 +bit 13_116 +bit 13_117 +bit 13_118 +bit 13_119 +bit 13_12 +bit 13_120 +bit 13_121 +bit 13_122 +bit 13_123 +bit 13_124 +bit 13_125 +bit 13_126 +bit 13_127 +bit 13_128 +bit 13_129 +bit 13_13 +bit 13_130 +bit 13_131 +bit 13_132 +bit 13_133 +bit 13_134 +bit 13_135 +bit 13_136 +bit 13_137 +bit 13_138 +bit 13_139 +bit 13_14 +bit 13_140 +bit 13_141 +bit 13_142 +bit 13_143 +bit 13_144 +bit 13_145 +bit 13_146 +bit 13_147 +bit 13_148 +bit 13_149 +bit 13_15 +bit 13_150 +bit 13_151 +bit 13_152 +bit 13_153 +bit 13_154 +bit 13_155 +bit 13_156 +bit 13_157 +bit 13_158 +bit 13_159 +bit 13_16 +bit 13_160 +bit 13_161 +bit 13_162 +bit 13_163 +bit 13_164 +bit 13_165 +bit 13_166 +bit 13_167 +bit 13_168 +bit 13_169 +bit 13_17 +bit 13_170 +bit 13_171 +bit 13_172 +bit 13_173 +bit 13_174 +bit 13_175 +bit 13_176 +bit 13_177 +bit 13_178 +bit 13_179 +bit 13_18 +bit 13_180 +bit 13_181 +bit 13_182 +bit 13_183 +bit 13_184 +bit 13_185 +bit 13_186 +bit 13_187 +bit 13_188 +bit 13_189 +bit 13_19 +bit 13_190 +bit 13_191 +bit 13_192 +bit 13_193 +bit 13_194 +bit 13_195 +bit 13_196 +bit 13_197 +bit 13_198 +bit 13_199 +bit 13_20 +bit 13_200 +bit 13_201 +bit 13_202 +bit 13_203 +bit 13_204 +bit 13_205 +bit 13_206 +bit 13_207 +bit 13_208 +bit 13_209 +bit 13_21 +bit 13_210 +bit 13_211 +bit 13_212 +bit 13_213 +bit 13_214 +bit 13_215 +bit 13_216 +bit 13_217 +bit 13_218 +bit 13_219 +bit 13_22 +bit 13_220 +bit 13_221 +bit 13_222 +bit 13_223 +bit 13_224 +bit 13_225 +bit 13_226 +bit 13_227 +bit 13_228 +bit 13_229 +bit 13_23 +bit 13_230 +bit 13_231 +bit 13_232 +bit 13_233 +bit 13_234 +bit 13_235 +bit 13_236 +bit 13_237 +bit 13_238 +bit 13_239 +bit 13_24 +bit 13_240 +bit 13_241 +bit 13_242 +bit 13_243 +bit 13_244 +bit 13_245 +bit 13_246 +bit 13_247 +bit 13_248 +bit 13_249 +bit 13_25 +bit 13_250 +bit 13_251 +bit 13_252 +bit 13_253 +bit 13_254 +bit 13_255 +bit 13_256 +bit 13_257 +bit 13_258 +bit 13_259 +bit 13_26 +bit 13_260 +bit 13_261 +bit 13_262 +bit 13_263 +bit 13_264 +bit 13_265 +bit 13_266 +bit 13_267 +bit 13_268 +bit 13_269 +bit 13_27 +bit 13_270 +bit 13_271 +bit 13_272 +bit 13_273 +bit 13_274 +bit 13_275 +bit 13_276 +bit 13_277 +bit 13_278 +bit 13_279 +bit 13_28 +bit 13_280 +bit 13_281 +bit 13_282 +bit 13_283 +bit 13_284 +bit 13_285 +bit 13_286 +bit 13_287 +bit 13_288 +bit 13_289 +bit 13_29 +bit 13_290 +bit 13_291 +bit 13_292 +bit 13_293 +bit 13_294 +bit 13_295 +bit 13_296 +bit 13_297 +bit 13_298 +bit 13_299 +bit 13_30 +bit 13_300 +bit 13_301 +bit 13_302 +bit 13_303 +bit 13_304 +bit 13_305 +bit 13_306 +bit 13_307 +bit 13_308 +bit 13_309 +bit 13_31 +bit 13_310 +bit 13_311 +bit 13_312 +bit 13_313 +bit 13_314 +bit 13_315 +bit 13_316 +bit 13_317 +bit 13_318 +bit 13_319 +bit 13_32 +bit 13_33 +bit 13_34 +bit 13_35 +bit 13_36 +bit 13_37 +bit 13_38 +bit 13_39 +bit 13_40 +bit 13_41 +bit 13_42 +bit 13_43 +bit 13_44 +bit 13_45 +bit 13_46 +bit 13_47 +bit 13_48 +bit 13_49 +bit 13_50 +bit 13_51 +bit 13_52 +bit 13_53 +bit 13_54 +bit 13_55 +bit 13_56 +bit 13_57 +bit 13_58 +bit 13_59 +bit 13_60 +bit 13_61 +bit 13_62 +bit 13_63 +bit 13_64 +bit 13_65 +bit 13_66 +bit 13_67 +bit 13_68 +bit 13_69 +bit 13_70 +bit 13_71 +bit 13_72 +bit 13_73 +bit 13_74 +bit 13_75 +bit 13_76 +bit 13_77 +bit 13_78 +bit 13_79 +bit 13_80 +bit 13_81 +bit 13_82 +bit 13_83 +bit 13_84 +bit 13_85 +bit 13_86 +bit 13_87 +bit 13_88 +bit 13_89 +bit 13_90 +bit 13_91 +bit 13_92 +bit 13_93 +bit 13_94 +bit 13_95 +bit 13_96 +bit 13_97 +bit 13_98 +bit 13_99 +bit 14_00 +bit 14_01 +bit 14_02 +bit 14_03 +bit 14_04 +bit 14_05 +bit 14_06 +bit 14_07 +bit 14_08 +bit 14_09 +bit 14_10 +bit 14_100 +bit 14_101 +bit 14_102 +bit 14_103 +bit 14_104 +bit 14_105 +bit 14_106 +bit 14_107 +bit 14_108 +bit 14_109 +bit 14_11 +bit 14_110 +bit 14_111 +bit 14_112 +bit 14_113 +bit 14_114 +bit 14_115 +bit 14_116 +bit 14_117 +bit 14_118 +bit 14_119 +bit 14_12 +bit 14_120 +bit 14_121 +bit 14_122 +bit 14_123 +bit 14_124 +bit 14_125 +bit 14_126 +bit 14_127 +bit 14_128 +bit 14_129 +bit 14_13 +bit 14_130 +bit 14_131 +bit 14_132 +bit 14_133 +bit 14_134 +bit 14_135 +bit 14_136 +bit 14_137 +bit 14_138 +bit 14_139 +bit 14_14 +bit 14_140 +bit 14_141 +bit 14_142 +bit 14_143 +bit 14_144 +bit 14_145 +bit 14_146 +bit 14_147 +bit 14_148 +bit 14_149 +bit 14_15 +bit 14_150 +bit 14_151 +bit 14_152 +bit 14_153 +bit 14_154 +bit 14_155 +bit 14_156 +bit 14_157 +bit 14_158 +bit 14_159 +bit 14_16 +bit 14_160 +bit 14_161 +bit 14_162 +bit 14_163 +bit 14_164 +bit 14_165 +bit 14_166 +bit 14_167 +bit 14_168 +bit 14_169 +bit 14_17 +bit 14_170 +bit 14_171 +bit 14_172 +bit 14_173 +bit 14_174 +bit 14_175 +bit 14_176 +bit 14_177 +bit 14_178 +bit 14_179 +bit 14_18 +bit 14_180 +bit 14_181 +bit 14_182 +bit 14_183 +bit 14_184 +bit 14_185 +bit 14_186 +bit 14_187 +bit 14_188 +bit 14_189 +bit 14_19 +bit 14_190 +bit 14_191 +bit 14_192 +bit 14_193 +bit 14_194 +bit 14_195 +bit 14_196 +bit 14_197 +bit 14_198 +bit 14_199 +bit 14_20 +bit 14_200 +bit 14_201 +bit 14_202 +bit 14_203 +bit 14_204 +bit 14_205 +bit 14_206 +bit 14_207 +bit 14_208 +bit 14_209 +bit 14_21 +bit 14_210 +bit 14_211 +bit 14_212 +bit 14_213 +bit 14_214 +bit 14_215 +bit 14_216 +bit 14_217 +bit 14_218 +bit 14_219 +bit 14_22 +bit 14_220 +bit 14_221 +bit 14_222 +bit 14_223 +bit 14_224 +bit 14_225 +bit 14_226 +bit 14_227 +bit 14_228 +bit 14_229 +bit 14_23 +bit 14_230 +bit 14_231 +bit 14_232 +bit 14_233 +bit 14_234 +bit 14_235 +bit 14_236 +bit 14_237 +bit 14_238 +bit 14_239 +bit 14_24 +bit 14_240 +bit 14_241 +bit 14_242 +bit 14_243 +bit 14_244 +bit 14_245 +bit 14_246 +bit 14_247 +bit 14_248 +bit 14_249 +bit 14_25 +bit 14_250 +bit 14_251 +bit 14_252 +bit 14_253 +bit 14_254 +bit 14_255 +bit 14_256 +bit 14_257 +bit 14_258 +bit 14_259 +bit 14_26 +bit 14_260 +bit 14_261 +bit 14_262 +bit 14_263 +bit 14_264 +bit 14_265 +bit 14_266 +bit 14_267 +bit 14_268 +bit 14_269 +bit 14_27 +bit 14_270 +bit 14_271 +bit 14_272 +bit 14_273 +bit 14_274 +bit 14_275 +bit 14_276 +bit 14_277 +bit 14_278 +bit 14_279 +bit 14_28 +bit 14_280 +bit 14_281 +bit 14_282 +bit 14_283 +bit 14_284 +bit 14_285 +bit 14_286 +bit 14_287 +bit 14_288 +bit 14_289 +bit 14_29 +bit 14_290 +bit 14_291 +bit 14_292 +bit 14_293 +bit 14_294 +bit 14_295 +bit 14_296 +bit 14_297 +bit 14_298 +bit 14_299 +bit 14_30 +bit 14_300 +bit 14_301 +bit 14_302 +bit 14_303 +bit 14_304 +bit 14_305 +bit 14_306 +bit 14_307 +bit 14_308 +bit 14_309 +bit 14_31 +bit 14_310 +bit 14_311 +bit 14_312 +bit 14_313 +bit 14_314 +bit 14_315 +bit 14_316 +bit 14_317 +bit 14_318 +bit 14_319 +bit 14_32 +bit 14_33 +bit 14_34 +bit 14_35 +bit 14_36 +bit 14_37 +bit 14_38 +bit 14_39 +bit 14_40 +bit 14_41 +bit 14_42 +bit 14_43 +bit 14_44 +bit 14_45 +bit 14_46 +bit 14_47 +bit 14_48 +bit 14_49 +bit 14_50 +bit 14_51 +bit 14_52 +bit 14_53 +bit 14_54 +bit 14_55 +bit 14_56 +bit 14_57 +bit 14_58 +bit 14_59 +bit 14_60 +bit 14_61 +bit 14_62 +bit 14_63 +bit 14_64 +bit 14_65 +bit 14_66 +bit 14_67 +bit 14_68 +bit 14_69 +bit 14_70 +bit 14_71 +bit 14_72 +bit 14_73 +bit 14_74 +bit 14_75 +bit 14_76 +bit 14_77 +bit 14_78 +bit 14_79 +bit 14_80 +bit 14_81 +bit 14_82 +bit 14_83 +bit 14_84 +bit 14_85 +bit 14_86 +bit 14_87 +bit 14_88 +bit 14_89 +bit 14_90 +bit 14_91 +bit 14_92 +bit 14_93 +bit 14_94 +bit 14_95 +bit 14_96 +bit 14_97 +bit 14_98 +bit 14_99 +bit 15_00 +bit 15_01 +bit 15_02 +bit 15_03 +bit 15_04 +bit 15_05 +bit 15_06 +bit 15_07 +bit 15_08 +bit 15_09 +bit 15_10 +bit 15_100 +bit 15_101 +bit 15_102 +bit 15_103 +bit 15_104 +bit 15_105 +bit 15_106 +bit 15_107 +bit 15_108 +bit 15_109 +bit 15_11 +bit 15_110 +bit 15_111 +bit 15_112 +bit 15_113 +bit 15_114 +bit 15_115 +bit 15_116 +bit 15_117 +bit 15_118 +bit 15_119 +bit 15_12 +bit 15_120 +bit 15_121 +bit 15_122 +bit 15_123 +bit 15_124 +bit 15_125 +bit 15_126 +bit 15_127 +bit 15_128 +bit 15_129 +bit 15_13 +bit 15_130 +bit 15_131 +bit 15_132 +bit 15_133 +bit 15_134 +bit 15_135 +bit 15_136 +bit 15_137 +bit 15_138 +bit 15_139 +bit 15_14 +bit 15_140 +bit 15_141 +bit 15_142 +bit 15_143 +bit 15_144 +bit 15_145 +bit 15_146 +bit 15_147 +bit 15_148 +bit 15_149 +bit 15_15 +bit 15_150 +bit 15_151 +bit 15_152 +bit 15_153 +bit 15_154 +bit 15_155 +bit 15_156 +bit 15_157 +bit 15_158 +bit 15_159 +bit 15_16 +bit 15_160 +bit 15_161 +bit 15_162 +bit 15_163 +bit 15_164 +bit 15_165 +bit 15_166 +bit 15_167 +bit 15_168 +bit 15_169 +bit 15_17 +bit 15_170 +bit 15_171 +bit 15_172 +bit 15_173 +bit 15_174 +bit 15_175 +bit 15_176 +bit 15_177 +bit 15_178 +bit 15_179 +bit 15_18 +bit 15_180 +bit 15_181 +bit 15_182 +bit 15_183 +bit 15_184 +bit 15_185 +bit 15_186 +bit 15_187 +bit 15_188 +bit 15_189 +bit 15_19 +bit 15_190 +bit 15_191 +bit 15_192 +bit 15_193 +bit 15_194 +bit 15_195 +bit 15_196 +bit 15_197 +bit 15_198 +bit 15_199 +bit 15_20 +bit 15_200 +bit 15_201 +bit 15_202 +bit 15_203 +bit 15_204 +bit 15_205 +bit 15_206 +bit 15_207 +bit 15_208 +bit 15_209 +bit 15_21 +bit 15_210 +bit 15_211 +bit 15_212 +bit 15_213 +bit 15_214 +bit 15_215 +bit 15_216 +bit 15_217 +bit 15_218 +bit 15_219 +bit 15_22 +bit 15_220 +bit 15_221 +bit 15_222 +bit 15_223 +bit 15_224 +bit 15_225 +bit 15_226 +bit 15_227 +bit 15_228 +bit 15_229 +bit 15_23 +bit 15_230 +bit 15_231 +bit 15_232 +bit 15_233 +bit 15_234 +bit 15_235 +bit 15_236 +bit 15_237 +bit 15_238 +bit 15_239 +bit 15_24 +bit 15_240 +bit 15_241 +bit 15_242 +bit 15_243 +bit 15_244 +bit 15_245 +bit 15_246 +bit 15_247 +bit 15_248 +bit 15_249 +bit 15_25 +bit 15_250 +bit 15_251 +bit 15_252 +bit 15_253 +bit 15_254 +bit 15_255 +bit 15_256 +bit 15_257 +bit 15_258 +bit 15_259 +bit 15_26 +bit 15_260 +bit 15_261 +bit 15_262 +bit 15_263 +bit 15_264 +bit 15_265 +bit 15_266 +bit 15_267 +bit 15_268 +bit 15_269 +bit 15_27 +bit 15_270 +bit 15_271 +bit 15_272 +bit 15_273 +bit 15_274 +bit 15_275 +bit 15_276 +bit 15_277 +bit 15_278 +bit 15_279 +bit 15_28 +bit 15_280 +bit 15_281 +bit 15_282 +bit 15_283 +bit 15_284 +bit 15_285 +bit 15_286 +bit 15_287 +bit 15_288 +bit 15_289 +bit 15_29 +bit 15_290 +bit 15_291 +bit 15_292 +bit 15_293 +bit 15_294 +bit 15_295 +bit 15_296 +bit 15_297 +bit 15_298 +bit 15_299 +bit 15_30 +bit 15_300 +bit 15_301 +bit 15_302 +bit 15_303 +bit 15_304 +bit 15_305 +bit 15_306 +bit 15_307 +bit 15_308 +bit 15_309 +bit 15_31 +bit 15_310 +bit 15_311 +bit 15_312 +bit 15_313 +bit 15_314 +bit 15_315 +bit 15_316 +bit 15_317 +bit 15_318 +bit 15_319 +bit 15_32 +bit 15_33 +bit 15_34 +bit 15_35 +bit 15_36 +bit 15_37 +bit 15_38 +bit 15_39 +bit 15_40 +bit 15_41 +bit 15_42 +bit 15_43 +bit 15_44 +bit 15_45 +bit 15_46 +bit 15_47 +bit 15_48 +bit 15_49 +bit 15_50 +bit 15_51 +bit 15_52 +bit 15_53 +bit 15_54 +bit 15_55 +bit 15_56 +bit 15_57 +bit 15_58 +bit 15_59 +bit 15_60 +bit 15_61 +bit 15_62 +bit 15_63 +bit 15_64 +bit 15_65 +bit 15_66 +bit 15_67 +bit 15_68 +bit 15_69 +bit 15_70 +bit 15_71 +bit 15_72 +bit 15_73 +bit 15_74 +bit 15_75 +bit 15_76 +bit 15_77 +bit 15_78 +bit 15_79 +bit 15_80 +bit 15_81 +bit 15_82 +bit 15_83 +bit 15_84 +bit 15_85 +bit 15_86 +bit 15_87 +bit 15_88 +bit 15_89 +bit 15_90 +bit 15_91 +bit 15_92 +bit 15_93 +bit 15_94 +bit 15_95 +bit 15_96 +bit 15_97 +bit 15_98 +bit 15_99 +bit 16_00 +bit 16_01 +bit 16_02 +bit 16_03 +bit 16_04 +bit 16_05 +bit 16_06 +bit 16_07 +bit 16_08 +bit 16_09 +bit 16_10 +bit 16_100 +bit 16_101 +bit 16_102 +bit 16_103 +bit 16_104 +bit 16_105 +bit 16_106 +bit 16_107 +bit 16_108 +bit 16_109 +bit 16_11 +bit 16_110 +bit 16_111 +bit 16_112 +bit 16_113 +bit 16_114 +bit 16_115 +bit 16_116 +bit 16_117 +bit 16_118 +bit 16_119 +bit 16_12 +bit 16_120 +bit 16_121 +bit 16_122 +bit 16_123 +bit 16_124 +bit 16_125 +bit 16_126 +bit 16_127 +bit 16_128 +bit 16_129 +bit 16_13 +bit 16_130 +bit 16_131 +bit 16_132 +bit 16_133 +bit 16_134 +bit 16_135 +bit 16_136 +bit 16_137 +bit 16_138 +bit 16_139 +bit 16_14 +bit 16_140 +bit 16_141 +bit 16_142 +bit 16_143 +bit 16_144 +bit 16_145 +bit 16_146 +bit 16_147 +bit 16_148 +bit 16_149 +bit 16_15 +bit 16_150 +bit 16_151 +bit 16_152 +bit 16_153 +bit 16_154 +bit 16_155 +bit 16_156 +bit 16_157 +bit 16_158 +bit 16_159 +bit 16_16 +bit 16_160 +bit 16_161 +bit 16_162 +bit 16_163 +bit 16_164 +bit 16_165 +bit 16_166 +bit 16_167 +bit 16_168 +bit 16_169 +bit 16_17 +bit 16_170 +bit 16_171 +bit 16_172 +bit 16_173 +bit 16_174 +bit 16_175 +bit 16_176 +bit 16_177 +bit 16_178 +bit 16_179 +bit 16_18 +bit 16_180 +bit 16_181 +bit 16_182 +bit 16_183 +bit 16_184 +bit 16_185 +bit 16_186 +bit 16_187 +bit 16_188 +bit 16_189 +bit 16_19 +bit 16_190 +bit 16_191 +bit 16_192 +bit 16_193 +bit 16_194 +bit 16_195 +bit 16_196 +bit 16_197 +bit 16_198 +bit 16_199 +bit 16_20 +bit 16_200 +bit 16_201 +bit 16_202 +bit 16_203 +bit 16_204 +bit 16_205 +bit 16_206 +bit 16_207 +bit 16_208 +bit 16_209 +bit 16_21 +bit 16_210 +bit 16_211 +bit 16_212 +bit 16_213 +bit 16_214 +bit 16_215 +bit 16_216 +bit 16_217 +bit 16_218 +bit 16_219 +bit 16_22 +bit 16_220 +bit 16_221 +bit 16_222 +bit 16_223 +bit 16_224 +bit 16_225 +bit 16_226 +bit 16_227 +bit 16_228 +bit 16_229 +bit 16_23 +bit 16_230 +bit 16_231 +bit 16_232 +bit 16_233 +bit 16_234 +bit 16_235 +bit 16_236 +bit 16_237 +bit 16_238 +bit 16_239 +bit 16_24 +bit 16_240 +bit 16_241 +bit 16_242 +bit 16_243 +bit 16_244 +bit 16_245 +bit 16_246 +bit 16_247 +bit 16_248 +bit 16_249 +bit 16_25 +bit 16_250 +bit 16_251 +bit 16_252 +bit 16_253 +bit 16_254 +bit 16_255 +bit 16_256 +bit 16_257 +bit 16_258 +bit 16_259 +bit 16_26 +bit 16_260 +bit 16_261 +bit 16_262 +bit 16_263 +bit 16_264 +bit 16_265 +bit 16_266 +bit 16_267 +bit 16_268 +bit 16_269 +bit 16_27 +bit 16_270 +bit 16_271 +bit 16_272 +bit 16_273 +bit 16_274 +bit 16_275 +bit 16_276 +bit 16_277 +bit 16_278 +bit 16_279 +bit 16_28 +bit 16_280 +bit 16_281 +bit 16_282 +bit 16_283 +bit 16_284 +bit 16_285 +bit 16_286 +bit 16_287 +bit 16_288 +bit 16_289 +bit 16_29 +bit 16_290 +bit 16_291 +bit 16_292 +bit 16_293 +bit 16_294 +bit 16_295 +bit 16_296 +bit 16_297 +bit 16_298 +bit 16_299 +bit 16_30 +bit 16_300 +bit 16_301 +bit 16_302 +bit 16_303 +bit 16_304 +bit 16_305 +bit 16_306 +bit 16_307 +bit 16_308 +bit 16_309 +bit 16_31 +bit 16_310 +bit 16_311 +bit 16_312 +bit 16_313 +bit 16_314 +bit 16_315 +bit 16_316 +bit 16_317 +bit 16_318 +bit 16_319 +bit 16_32 +bit 16_33 +bit 16_34 +bit 16_35 +bit 16_36 +bit 16_37 +bit 16_38 +bit 16_39 +bit 16_40 +bit 16_41 +bit 16_42 +bit 16_43 +bit 16_44 +bit 16_45 +bit 16_46 +bit 16_47 +bit 16_48 +bit 16_49 +bit 16_50 +bit 16_51 +bit 16_52 +bit 16_53 +bit 16_54 +bit 16_55 +bit 16_56 +bit 16_57 +bit 16_58 +bit 16_59 +bit 16_60 +bit 16_61 +bit 16_62 +bit 16_63 +bit 16_64 +bit 16_65 +bit 16_66 +bit 16_67 +bit 16_68 +bit 16_69 +bit 16_70 +bit 16_71 +bit 16_72 +bit 16_73 +bit 16_74 +bit 16_75 +bit 16_76 +bit 16_77 +bit 16_78 +bit 16_79 +bit 16_80 +bit 16_81 +bit 16_82 +bit 16_83 +bit 16_84 +bit 16_85 +bit 16_86 +bit 16_87 +bit 16_88 +bit 16_89 +bit 16_90 +bit 16_91 +bit 16_92 +bit 16_93 +bit 16_94 +bit 16_95 +bit 16_96 +bit 16_97 +bit 16_98 +bit 16_99 +bit 17_00 +bit 17_01 +bit 17_02 +bit 17_03 +bit 17_04 +bit 17_05 +bit 17_06 +bit 17_07 +bit 17_08 +bit 17_09 +bit 17_10 +bit 17_100 +bit 17_101 +bit 17_102 +bit 17_103 +bit 17_104 +bit 17_105 +bit 17_106 +bit 17_107 +bit 17_108 +bit 17_109 +bit 17_11 +bit 17_110 +bit 17_111 +bit 17_112 +bit 17_113 +bit 17_114 +bit 17_115 +bit 17_116 +bit 17_117 +bit 17_118 +bit 17_119 +bit 17_12 +bit 17_120 +bit 17_121 +bit 17_122 +bit 17_123 +bit 17_124 +bit 17_125 +bit 17_126 +bit 17_127 +bit 17_128 +bit 17_129 +bit 17_13 +bit 17_130 +bit 17_131 +bit 17_132 +bit 17_133 +bit 17_134 +bit 17_135 +bit 17_136 +bit 17_137 +bit 17_138 +bit 17_139 +bit 17_14 +bit 17_140 +bit 17_141 +bit 17_142 +bit 17_143 +bit 17_144 +bit 17_145 +bit 17_146 +bit 17_147 +bit 17_148 +bit 17_149 +bit 17_15 +bit 17_150 +bit 17_151 +bit 17_152 +bit 17_153 +bit 17_154 +bit 17_155 +bit 17_156 +bit 17_157 +bit 17_158 +bit 17_159 +bit 17_16 +bit 17_160 +bit 17_161 +bit 17_162 +bit 17_163 +bit 17_164 +bit 17_165 +bit 17_166 +bit 17_167 +bit 17_168 +bit 17_169 +bit 17_17 +bit 17_170 +bit 17_171 +bit 17_172 +bit 17_173 +bit 17_174 +bit 17_175 +bit 17_176 +bit 17_177 +bit 17_178 +bit 17_179 +bit 17_18 +bit 17_180 +bit 17_181 +bit 17_182 +bit 17_183 +bit 17_184 +bit 17_185 +bit 17_186 +bit 17_187 +bit 17_188 +bit 17_189 +bit 17_19 +bit 17_190 +bit 17_191 +bit 17_192 +bit 17_193 +bit 17_194 +bit 17_195 +bit 17_196 +bit 17_197 +bit 17_198 +bit 17_199 +bit 17_20 +bit 17_200 +bit 17_201 +bit 17_202 +bit 17_203 +bit 17_204 +bit 17_205 +bit 17_206 +bit 17_207 +bit 17_208 +bit 17_209 +bit 17_21 +bit 17_210 +bit 17_211 +bit 17_212 +bit 17_213 +bit 17_214 +bit 17_215 +bit 17_216 +bit 17_217 +bit 17_218 +bit 17_219 +bit 17_22 +bit 17_220 +bit 17_221 +bit 17_222 +bit 17_223 +bit 17_224 +bit 17_225 +bit 17_226 +bit 17_227 +bit 17_228 +bit 17_229 +bit 17_23 +bit 17_230 +bit 17_231 +bit 17_232 +bit 17_233 +bit 17_234 +bit 17_235 +bit 17_236 +bit 17_237 +bit 17_238 +bit 17_239 +bit 17_24 +bit 17_240 +bit 17_241 +bit 17_242 +bit 17_243 +bit 17_244 +bit 17_245 +bit 17_246 +bit 17_247 +bit 17_248 +bit 17_249 +bit 17_25 +bit 17_250 +bit 17_251 +bit 17_252 +bit 17_253 +bit 17_254 +bit 17_255 +bit 17_256 +bit 17_257 +bit 17_258 +bit 17_259 +bit 17_26 +bit 17_260 +bit 17_261 +bit 17_262 +bit 17_263 +bit 17_264 +bit 17_265 +bit 17_266 +bit 17_267 +bit 17_268 +bit 17_269 +bit 17_27 +bit 17_270 +bit 17_271 +bit 17_272 +bit 17_273 +bit 17_274 +bit 17_275 +bit 17_276 +bit 17_277 +bit 17_278 +bit 17_279 +bit 17_28 +bit 17_280 +bit 17_281 +bit 17_282 +bit 17_283 +bit 17_284 +bit 17_285 +bit 17_286 +bit 17_287 +bit 17_288 +bit 17_289 +bit 17_29 +bit 17_290 +bit 17_291 +bit 17_292 +bit 17_293 +bit 17_294 +bit 17_295 +bit 17_296 +bit 17_297 +bit 17_298 +bit 17_299 +bit 17_30 +bit 17_300 +bit 17_301 +bit 17_302 +bit 17_303 +bit 17_304 +bit 17_305 +bit 17_306 +bit 17_307 +bit 17_308 +bit 17_309 +bit 17_31 +bit 17_310 +bit 17_311 +bit 17_312 +bit 17_313 +bit 17_314 +bit 17_315 +bit 17_316 +bit 17_317 +bit 17_318 +bit 17_319 +bit 17_32 +bit 17_33 +bit 17_34 +bit 17_35 +bit 17_36 +bit 17_37 +bit 17_38 +bit 17_39 +bit 17_40 +bit 17_41 +bit 17_42 +bit 17_43 +bit 17_44 +bit 17_45 +bit 17_46 +bit 17_47 +bit 17_48 +bit 17_49 +bit 17_50 +bit 17_51 +bit 17_52 +bit 17_53 +bit 17_54 +bit 17_55 +bit 17_56 +bit 17_57 +bit 17_58 +bit 17_59 +bit 17_60 +bit 17_61 +bit 17_62 +bit 17_63 +bit 17_64 +bit 17_65 +bit 17_66 +bit 17_67 +bit 17_68 +bit 17_69 +bit 17_70 +bit 17_71 +bit 17_72 +bit 17_73 +bit 17_74 +bit 17_75 +bit 17_76 +bit 17_77 +bit 17_78 +bit 17_79 +bit 17_80 +bit 17_81 +bit 17_82 +bit 17_83 +bit 17_84 +bit 17_85 +bit 17_86 +bit 17_87 +bit 17_88 +bit 17_89 +bit 17_90 +bit 17_91 +bit 17_92 +bit 17_93 +bit 17_94 +bit 17_95 +bit 17_96 +bit 17_97 +bit 17_98 +bit 17_99 +bit 18_00 +bit 18_01 +bit 18_02 +bit 18_03 +bit 18_04 +bit 18_05 +bit 18_06 +bit 18_07 +bit 18_08 +bit 18_09 +bit 18_10 +bit 18_100 +bit 18_101 +bit 18_102 +bit 18_103 +bit 18_104 +bit 18_105 +bit 18_106 +bit 18_107 +bit 18_108 +bit 18_109 +bit 18_11 +bit 18_110 +bit 18_111 +bit 18_112 +bit 18_113 +bit 18_114 +bit 18_115 +bit 18_116 +bit 18_117 +bit 18_118 +bit 18_119 +bit 18_12 +bit 18_120 +bit 18_121 +bit 18_122 +bit 18_123 +bit 18_124 +bit 18_125 +bit 18_126 +bit 18_127 +bit 18_128 +bit 18_129 +bit 18_13 +bit 18_130 +bit 18_131 +bit 18_132 +bit 18_133 +bit 18_134 +bit 18_135 +bit 18_136 +bit 18_137 +bit 18_138 +bit 18_139 +bit 18_14 +bit 18_140 +bit 18_141 +bit 18_142 +bit 18_143 +bit 18_144 +bit 18_145 +bit 18_146 +bit 18_147 +bit 18_148 +bit 18_149 +bit 18_15 +bit 18_150 +bit 18_151 +bit 18_152 +bit 18_153 +bit 18_154 +bit 18_155 +bit 18_156 +bit 18_157 +bit 18_158 +bit 18_159 +bit 18_16 +bit 18_160 +bit 18_161 +bit 18_162 +bit 18_163 +bit 18_164 +bit 18_165 +bit 18_166 +bit 18_167 +bit 18_168 +bit 18_169 +bit 18_17 +bit 18_170 +bit 18_171 +bit 18_172 +bit 18_173 +bit 18_174 +bit 18_175 +bit 18_176 +bit 18_177 +bit 18_178 +bit 18_179 +bit 18_18 +bit 18_180 +bit 18_181 +bit 18_182 +bit 18_183 +bit 18_184 +bit 18_185 +bit 18_186 +bit 18_187 +bit 18_188 +bit 18_189 +bit 18_19 +bit 18_190 +bit 18_191 +bit 18_192 +bit 18_193 +bit 18_194 +bit 18_195 +bit 18_196 +bit 18_197 +bit 18_198 +bit 18_199 +bit 18_20 +bit 18_200 +bit 18_201 +bit 18_202 +bit 18_203 +bit 18_204 +bit 18_205 +bit 18_206 +bit 18_207 +bit 18_208 +bit 18_209 +bit 18_21 +bit 18_210 +bit 18_211 +bit 18_212 +bit 18_213 +bit 18_214 +bit 18_215 +bit 18_216 +bit 18_217 +bit 18_218 +bit 18_219 +bit 18_22 +bit 18_220 +bit 18_221 +bit 18_222 +bit 18_223 +bit 18_224 +bit 18_225 +bit 18_226 +bit 18_227 +bit 18_228 +bit 18_229 +bit 18_23 +bit 18_230 +bit 18_231 +bit 18_232 +bit 18_233 +bit 18_234 +bit 18_235 +bit 18_236 +bit 18_237 +bit 18_238 +bit 18_239 +bit 18_24 +bit 18_240 +bit 18_241 +bit 18_242 +bit 18_243 +bit 18_244 +bit 18_245 +bit 18_246 +bit 18_247 +bit 18_248 +bit 18_249 +bit 18_25 +bit 18_250 +bit 18_251 +bit 18_252 +bit 18_253 +bit 18_254 +bit 18_255 +bit 18_256 +bit 18_257 +bit 18_258 +bit 18_259 +bit 18_26 +bit 18_260 +bit 18_261 +bit 18_262 +bit 18_263 +bit 18_264 +bit 18_265 +bit 18_266 +bit 18_267 +bit 18_268 +bit 18_269 +bit 18_27 +bit 18_270 +bit 18_271 +bit 18_272 +bit 18_273 +bit 18_274 +bit 18_275 +bit 18_276 +bit 18_277 +bit 18_278 +bit 18_279 +bit 18_28 +bit 18_280 +bit 18_281 +bit 18_282 +bit 18_283 +bit 18_284 +bit 18_285 +bit 18_286 +bit 18_287 +bit 18_288 +bit 18_289 +bit 18_29 +bit 18_290 +bit 18_291 +bit 18_292 +bit 18_293 +bit 18_294 +bit 18_295 +bit 18_296 +bit 18_297 +bit 18_298 +bit 18_299 +bit 18_30 +bit 18_300 +bit 18_301 +bit 18_302 +bit 18_303 +bit 18_304 +bit 18_305 +bit 18_306 +bit 18_307 +bit 18_308 +bit 18_309 +bit 18_31 +bit 18_310 +bit 18_311 +bit 18_312 +bit 18_313 +bit 18_314 +bit 18_315 +bit 18_316 +bit 18_317 +bit 18_318 +bit 18_319 +bit 18_32 +bit 18_33 +bit 18_34 +bit 18_35 +bit 18_36 +bit 18_37 +bit 18_38 +bit 18_39 +bit 18_40 +bit 18_41 +bit 18_42 +bit 18_43 +bit 18_44 +bit 18_45 +bit 18_46 +bit 18_47 +bit 18_48 +bit 18_49 +bit 18_50 +bit 18_51 +bit 18_52 +bit 18_53 +bit 18_54 +bit 18_55 +bit 18_56 +bit 18_57 +bit 18_58 +bit 18_59 +bit 18_60 +bit 18_61 +bit 18_62 +bit 18_63 +bit 18_64 +bit 18_65 +bit 18_66 +bit 18_67 +bit 18_68 +bit 18_69 +bit 18_70 +bit 18_71 +bit 18_72 +bit 18_73 +bit 18_74 +bit 18_75 +bit 18_76 +bit 18_77 +bit 18_78 +bit 18_79 +bit 18_80 +bit 18_81 +bit 18_82 +bit 18_83 +bit 18_84 +bit 18_85 +bit 18_86 +bit 18_87 +bit 18_88 +bit 18_89 +bit 18_90 +bit 18_91 +bit 18_92 +bit 18_93 +bit 18_94 +bit 18_95 +bit 18_96 +bit 18_97 +bit 18_98 +bit 18_99 +bit 19_00 +bit 19_01 +bit 19_02 +bit 19_03 +bit 19_04 +bit 19_05 +bit 19_06 +bit 19_07 +bit 19_08 +bit 19_09 +bit 19_10 +bit 19_100 +bit 19_101 +bit 19_102 +bit 19_103 +bit 19_104 +bit 19_105 +bit 19_106 +bit 19_107 +bit 19_108 +bit 19_109 +bit 19_11 +bit 19_110 +bit 19_111 +bit 19_112 +bit 19_113 +bit 19_114 +bit 19_115 +bit 19_116 +bit 19_117 +bit 19_118 +bit 19_119 +bit 19_12 +bit 19_120 +bit 19_121 +bit 19_122 +bit 19_123 +bit 19_124 +bit 19_125 +bit 19_126 +bit 19_127 +bit 19_128 +bit 19_129 +bit 19_13 +bit 19_130 +bit 19_131 +bit 19_132 +bit 19_133 +bit 19_134 +bit 19_135 +bit 19_136 +bit 19_137 +bit 19_138 +bit 19_139 +bit 19_14 +bit 19_140 +bit 19_141 +bit 19_142 +bit 19_143 +bit 19_144 +bit 19_145 +bit 19_146 +bit 19_147 +bit 19_148 +bit 19_149 +bit 19_15 +bit 19_150 +bit 19_151 +bit 19_152 +bit 19_153 +bit 19_154 +bit 19_155 +bit 19_156 +bit 19_157 +bit 19_158 +bit 19_159 +bit 19_16 +bit 19_160 +bit 19_161 +bit 19_162 +bit 19_163 +bit 19_164 +bit 19_165 +bit 19_166 +bit 19_167 +bit 19_168 +bit 19_169 +bit 19_17 +bit 19_170 +bit 19_171 +bit 19_172 +bit 19_173 +bit 19_174 +bit 19_175 +bit 19_176 +bit 19_177 +bit 19_178 +bit 19_179 +bit 19_18 +bit 19_180 +bit 19_181 +bit 19_182 +bit 19_183 +bit 19_184 +bit 19_185 +bit 19_186 +bit 19_187 +bit 19_188 +bit 19_189 +bit 19_19 +bit 19_190 +bit 19_191 +bit 19_192 +bit 19_193 +bit 19_194 +bit 19_195 +bit 19_196 +bit 19_197 +bit 19_198 +bit 19_199 +bit 19_20 +bit 19_200 +bit 19_201 +bit 19_202 +bit 19_203 +bit 19_204 +bit 19_205 +bit 19_206 +bit 19_207 +bit 19_208 +bit 19_209 +bit 19_21 +bit 19_210 +bit 19_211 +bit 19_212 +bit 19_213 +bit 19_214 +bit 19_215 +bit 19_216 +bit 19_217 +bit 19_218 +bit 19_219 +bit 19_22 +bit 19_220 +bit 19_221 +bit 19_222 +bit 19_223 +bit 19_224 +bit 19_225 +bit 19_226 +bit 19_227 +bit 19_228 +bit 19_229 +bit 19_23 +bit 19_230 +bit 19_231 +bit 19_232 +bit 19_233 +bit 19_234 +bit 19_235 +bit 19_236 +bit 19_237 +bit 19_238 +bit 19_239 +bit 19_24 +bit 19_240 +bit 19_241 +bit 19_242 +bit 19_243 +bit 19_244 +bit 19_245 +bit 19_246 +bit 19_247 +bit 19_248 +bit 19_249 +bit 19_25 +bit 19_250 +bit 19_251 +bit 19_252 +bit 19_253 +bit 19_254 +bit 19_255 +bit 19_256 +bit 19_257 +bit 19_258 +bit 19_259 +bit 19_26 +bit 19_260 +bit 19_261 +bit 19_262 +bit 19_263 +bit 19_264 +bit 19_265 +bit 19_266 +bit 19_267 +bit 19_268 +bit 19_269 +bit 19_27 +bit 19_270 +bit 19_271 +bit 19_272 +bit 19_273 +bit 19_274 +bit 19_275 +bit 19_276 +bit 19_277 +bit 19_278 +bit 19_279 +bit 19_28 +bit 19_280 +bit 19_281 +bit 19_282 +bit 19_283 +bit 19_284 +bit 19_285 +bit 19_286 +bit 19_287 +bit 19_288 +bit 19_289 +bit 19_29 +bit 19_290 +bit 19_291 +bit 19_292 +bit 19_293 +bit 19_294 +bit 19_295 +bit 19_296 +bit 19_297 +bit 19_298 +bit 19_299 +bit 19_30 +bit 19_300 +bit 19_301 +bit 19_302 +bit 19_303 +bit 19_304 +bit 19_305 +bit 19_306 +bit 19_307 +bit 19_308 +bit 19_309 +bit 19_31 +bit 19_310 +bit 19_311 +bit 19_312 +bit 19_313 +bit 19_314 +bit 19_315 +bit 19_316 +bit 19_317 +bit 19_318 +bit 19_319 +bit 19_32 +bit 19_33 +bit 19_34 +bit 19_35 +bit 19_36 +bit 19_37 +bit 19_38 +bit 19_39 +bit 19_40 +bit 19_41 +bit 19_42 +bit 19_43 +bit 19_44 +bit 19_45 +bit 19_46 +bit 19_47 +bit 19_48 +bit 19_49 +bit 19_50 +bit 19_51 +bit 19_52 +bit 19_53 +bit 19_54 +bit 19_55 +bit 19_56 +bit 19_57 +bit 19_58 +bit 19_59 +bit 19_60 +bit 19_61 +bit 19_62 +bit 19_63 +bit 19_64 +bit 19_65 +bit 19_66 +bit 19_67 +bit 19_68 +bit 19_69 +bit 19_70 +bit 19_71 +bit 19_72 +bit 19_73 +bit 19_74 +bit 19_75 +bit 19_76 +bit 19_77 +bit 19_78 +bit 19_79 +bit 19_80 +bit 19_81 +bit 19_82 +bit 19_83 +bit 19_84 +bit 19_85 +bit 19_86 +bit 19_87 +bit 19_88 +bit 19_89 +bit 19_90 +bit 19_91 +bit 19_92 +bit 19_93 +bit 19_94 +bit 19_95 +bit 19_96 +bit 19_97 +bit 19_98 +bit 19_99 +bit 20_00 +bit 20_01 +bit 20_02 +bit 20_03 +bit 20_04 +bit 20_05 +bit 20_06 +bit 20_07 +bit 20_08 +bit 20_09 +bit 20_10 +bit 20_100 +bit 20_101 +bit 20_102 +bit 20_103 +bit 20_104 +bit 20_105 +bit 20_106 +bit 20_107 +bit 20_108 +bit 20_109 +bit 20_11 +bit 20_110 +bit 20_111 +bit 20_112 +bit 20_113 +bit 20_114 +bit 20_115 +bit 20_116 +bit 20_117 +bit 20_118 +bit 20_119 +bit 20_12 +bit 20_120 +bit 20_121 +bit 20_122 +bit 20_123 +bit 20_124 +bit 20_125 +bit 20_126 +bit 20_127 +bit 20_128 +bit 20_129 +bit 20_13 +bit 20_130 +bit 20_131 +bit 20_132 +bit 20_133 +bit 20_134 +bit 20_135 +bit 20_136 +bit 20_137 +bit 20_138 +bit 20_139 +bit 20_14 +bit 20_140 +bit 20_141 +bit 20_142 +bit 20_143 +bit 20_144 +bit 20_145 +bit 20_146 +bit 20_147 +bit 20_148 +bit 20_149 +bit 20_15 +bit 20_150 +bit 20_151 +bit 20_152 +bit 20_153 +bit 20_154 +bit 20_155 +bit 20_156 +bit 20_157 +bit 20_158 +bit 20_159 +bit 20_16 +bit 20_160 +bit 20_161 +bit 20_162 +bit 20_163 +bit 20_164 +bit 20_165 +bit 20_166 +bit 20_167 +bit 20_168 +bit 20_169 +bit 20_17 +bit 20_170 +bit 20_171 +bit 20_172 +bit 20_173 +bit 20_174 +bit 20_175 +bit 20_176 +bit 20_177 +bit 20_178 +bit 20_179 +bit 20_18 +bit 20_180 +bit 20_181 +bit 20_182 +bit 20_183 +bit 20_184 +bit 20_185 +bit 20_186 +bit 20_187 +bit 20_188 +bit 20_189 +bit 20_19 +bit 20_190 +bit 20_191 +bit 20_192 +bit 20_193 +bit 20_194 +bit 20_195 +bit 20_196 +bit 20_197 +bit 20_198 +bit 20_199 +bit 20_20 +bit 20_200 +bit 20_201 +bit 20_202 +bit 20_203 +bit 20_204 +bit 20_205 +bit 20_206 +bit 20_207 +bit 20_208 +bit 20_209 +bit 20_21 +bit 20_210 +bit 20_211 +bit 20_212 +bit 20_213 +bit 20_214 +bit 20_215 +bit 20_216 +bit 20_217 +bit 20_218 +bit 20_219 +bit 20_22 +bit 20_220 +bit 20_221 +bit 20_222 +bit 20_223 +bit 20_224 +bit 20_225 +bit 20_226 +bit 20_227 +bit 20_228 +bit 20_229 +bit 20_23 +bit 20_230 +bit 20_231 +bit 20_232 +bit 20_233 +bit 20_234 +bit 20_235 +bit 20_236 +bit 20_237 +bit 20_238 +bit 20_239 +bit 20_24 +bit 20_240 +bit 20_241 +bit 20_242 +bit 20_243 +bit 20_244 +bit 20_245 +bit 20_246 +bit 20_247 +bit 20_248 +bit 20_249 +bit 20_25 +bit 20_250 +bit 20_251 +bit 20_252 +bit 20_253 +bit 20_254 +bit 20_255 +bit 20_256 +bit 20_257 +bit 20_258 +bit 20_259 +bit 20_26 +bit 20_260 +bit 20_261 +bit 20_262 +bit 20_263 +bit 20_264 +bit 20_265 +bit 20_266 +bit 20_267 +bit 20_268 +bit 20_269 +bit 20_27 +bit 20_270 +bit 20_271 +bit 20_272 +bit 20_273 +bit 20_274 +bit 20_275 +bit 20_276 +bit 20_277 +bit 20_278 +bit 20_279 +bit 20_28 +bit 20_280 +bit 20_281 +bit 20_282 +bit 20_283 +bit 20_284 +bit 20_285 +bit 20_286 +bit 20_287 +bit 20_288 +bit 20_289 +bit 20_29 +bit 20_290 +bit 20_291 +bit 20_292 +bit 20_293 +bit 20_294 +bit 20_295 +bit 20_296 +bit 20_297 +bit 20_298 +bit 20_299 +bit 20_30 +bit 20_300 +bit 20_301 +bit 20_302 +bit 20_303 +bit 20_304 +bit 20_305 +bit 20_306 +bit 20_307 +bit 20_308 +bit 20_309 +bit 20_31 +bit 20_310 +bit 20_311 +bit 20_312 +bit 20_313 +bit 20_314 +bit 20_315 +bit 20_316 +bit 20_317 +bit 20_318 +bit 20_319 +bit 20_32 +bit 20_33 +bit 20_34 +bit 20_35 +bit 20_36 +bit 20_37 +bit 20_38 +bit 20_39 +bit 20_40 +bit 20_41 +bit 20_42 +bit 20_43 +bit 20_44 +bit 20_45 +bit 20_46 +bit 20_47 +bit 20_48 +bit 20_49 +bit 20_50 +bit 20_51 +bit 20_52 +bit 20_53 +bit 20_54 +bit 20_55 +bit 20_56 +bit 20_57 +bit 20_58 +bit 20_59 +bit 20_60 +bit 20_61 +bit 20_62 +bit 20_63 +bit 20_64 +bit 20_65 +bit 20_66 +bit 20_67 +bit 20_68 +bit 20_69 +bit 20_70 +bit 20_71 +bit 20_72 +bit 20_73 +bit 20_74 +bit 20_75 +bit 20_76 +bit 20_77 +bit 20_78 +bit 20_79 +bit 20_80 +bit 20_81 +bit 20_82 +bit 20_83 +bit 20_84 +bit 20_85 +bit 20_86 +bit 20_87 +bit 20_88 +bit 20_89 +bit 20_90 +bit 20_91 +bit 20_92 +bit 20_93 +bit 20_94 +bit 20_95 +bit 20_96 +bit 20_97 +bit 20_98 +bit 20_99 +bit 21_00 +bit 21_01 +bit 21_02 +bit 21_03 +bit 21_04 +bit 21_05 +bit 21_06 +bit 21_07 +bit 21_08 +bit 21_09 +bit 21_10 +bit 21_100 +bit 21_101 +bit 21_102 +bit 21_103 +bit 21_104 +bit 21_105 +bit 21_106 +bit 21_107 +bit 21_108 +bit 21_109 +bit 21_11 +bit 21_110 +bit 21_111 +bit 21_112 +bit 21_113 +bit 21_114 +bit 21_115 +bit 21_116 +bit 21_117 +bit 21_118 +bit 21_119 +bit 21_12 +bit 21_120 +bit 21_121 +bit 21_122 +bit 21_123 +bit 21_124 +bit 21_125 +bit 21_126 +bit 21_127 +bit 21_128 +bit 21_129 +bit 21_13 +bit 21_130 +bit 21_131 +bit 21_132 +bit 21_133 +bit 21_134 +bit 21_135 +bit 21_136 +bit 21_137 +bit 21_138 +bit 21_139 +bit 21_14 +bit 21_140 +bit 21_141 +bit 21_142 +bit 21_143 +bit 21_144 +bit 21_145 +bit 21_146 +bit 21_147 +bit 21_148 +bit 21_149 +bit 21_15 +bit 21_150 +bit 21_151 +bit 21_152 +bit 21_153 +bit 21_154 +bit 21_155 +bit 21_156 +bit 21_157 +bit 21_158 +bit 21_159 +bit 21_16 +bit 21_160 +bit 21_161 +bit 21_162 +bit 21_163 +bit 21_164 +bit 21_165 +bit 21_166 +bit 21_167 +bit 21_168 +bit 21_169 +bit 21_17 +bit 21_170 +bit 21_171 +bit 21_172 +bit 21_173 +bit 21_174 +bit 21_175 +bit 21_176 +bit 21_177 +bit 21_178 +bit 21_179 +bit 21_18 +bit 21_180 +bit 21_181 +bit 21_182 +bit 21_183 +bit 21_184 +bit 21_185 +bit 21_186 +bit 21_187 +bit 21_188 +bit 21_189 +bit 21_19 +bit 21_190 +bit 21_191 +bit 21_192 +bit 21_193 +bit 21_194 +bit 21_195 +bit 21_196 +bit 21_197 +bit 21_198 +bit 21_199 +bit 21_20 +bit 21_200 +bit 21_201 +bit 21_202 +bit 21_203 +bit 21_204 +bit 21_205 +bit 21_206 +bit 21_207 +bit 21_208 +bit 21_209 +bit 21_21 +bit 21_210 +bit 21_211 +bit 21_212 +bit 21_213 +bit 21_214 +bit 21_215 +bit 21_216 +bit 21_217 +bit 21_218 +bit 21_219 +bit 21_22 +bit 21_220 +bit 21_221 +bit 21_222 +bit 21_223 +bit 21_224 +bit 21_225 +bit 21_226 +bit 21_227 +bit 21_228 +bit 21_229 +bit 21_23 +bit 21_230 +bit 21_231 +bit 21_232 +bit 21_233 +bit 21_234 +bit 21_235 +bit 21_236 +bit 21_237 +bit 21_238 +bit 21_239 +bit 21_24 +bit 21_240 +bit 21_241 +bit 21_242 +bit 21_243 +bit 21_244 +bit 21_245 +bit 21_246 +bit 21_247 +bit 21_248 +bit 21_249 +bit 21_25 +bit 21_250 +bit 21_251 +bit 21_252 +bit 21_253 +bit 21_254 +bit 21_255 +bit 21_256 +bit 21_257 +bit 21_258 +bit 21_259 +bit 21_26 +bit 21_260 +bit 21_261 +bit 21_262 +bit 21_263 +bit 21_264 +bit 21_265 +bit 21_266 +bit 21_267 +bit 21_268 +bit 21_269 +bit 21_27 +bit 21_270 +bit 21_271 +bit 21_272 +bit 21_273 +bit 21_274 +bit 21_275 +bit 21_276 +bit 21_277 +bit 21_278 +bit 21_279 +bit 21_28 +bit 21_280 +bit 21_281 +bit 21_282 +bit 21_283 +bit 21_284 +bit 21_285 +bit 21_286 +bit 21_287 +bit 21_288 +bit 21_289 +bit 21_29 +bit 21_290 +bit 21_291 +bit 21_292 +bit 21_293 +bit 21_294 +bit 21_295 +bit 21_296 +bit 21_297 +bit 21_298 +bit 21_299 +bit 21_30 +bit 21_300 +bit 21_301 +bit 21_302 +bit 21_303 +bit 21_304 +bit 21_305 +bit 21_306 +bit 21_307 +bit 21_308 +bit 21_309 +bit 21_31 +bit 21_310 +bit 21_311 +bit 21_312 +bit 21_313 +bit 21_314 +bit 21_315 +bit 21_316 +bit 21_317 +bit 21_318 +bit 21_319 +bit 21_32 +bit 21_33 +bit 21_34 +bit 21_35 +bit 21_36 +bit 21_37 +bit 21_38 +bit 21_39 +bit 21_40 +bit 21_41 +bit 21_42 +bit 21_43 +bit 21_44 +bit 21_45 +bit 21_46 +bit 21_47 +bit 21_48 +bit 21_49 +bit 21_50 +bit 21_51 +bit 21_52 +bit 21_53 +bit 21_54 +bit 21_55 +bit 21_56 +bit 21_57 +bit 21_58 +bit 21_59 +bit 21_60 +bit 21_61 +bit 21_62 +bit 21_63 +bit 21_64 +bit 21_65 +bit 21_66 +bit 21_67 +bit 21_68 +bit 21_69 +bit 21_70 +bit 21_71 +bit 21_72 +bit 21_73 +bit 21_74 +bit 21_75 +bit 21_76 +bit 21_77 +bit 21_78 +bit 21_79 +bit 21_80 +bit 21_81 +bit 21_82 +bit 21_83 +bit 21_84 +bit 21_85 +bit 21_86 +bit 21_87 +bit 21_88 +bit 21_89 +bit 21_90 +bit 21_91 +bit 21_92 +bit 21_93 +bit 21_94 +bit 21_95 +bit 21_96 +bit 21_97 +bit 21_98 +bit 21_99 +bit 22_00 +bit 22_01 +bit 22_02 +bit 22_03 +bit 22_04 +bit 22_05 +bit 22_06 +bit 22_07 +bit 22_08 +bit 22_09 +bit 22_10 +bit 22_100 +bit 22_101 +bit 22_102 +bit 22_103 +bit 22_104 +bit 22_105 +bit 22_106 +bit 22_107 +bit 22_108 +bit 22_109 +bit 22_11 +bit 22_110 +bit 22_111 +bit 22_112 +bit 22_113 +bit 22_114 +bit 22_115 +bit 22_116 +bit 22_117 +bit 22_118 +bit 22_119 +bit 22_12 +bit 22_120 +bit 22_121 +bit 22_122 +bit 22_123 +bit 22_124 +bit 22_125 +bit 22_126 +bit 22_127 +bit 22_128 +bit 22_129 +bit 22_13 +bit 22_130 +bit 22_131 +bit 22_132 +bit 22_133 +bit 22_134 +bit 22_135 +bit 22_136 +bit 22_137 +bit 22_138 +bit 22_139 +bit 22_14 +bit 22_140 +bit 22_141 +bit 22_142 +bit 22_143 +bit 22_144 +bit 22_145 +bit 22_146 +bit 22_147 +bit 22_148 +bit 22_149 +bit 22_15 +bit 22_150 +bit 22_151 +bit 22_152 +bit 22_153 +bit 22_154 +bit 22_155 +bit 22_156 +bit 22_157 +bit 22_158 +bit 22_159 +bit 22_16 +bit 22_160 +bit 22_161 +bit 22_162 +bit 22_163 +bit 22_164 +bit 22_165 +bit 22_166 +bit 22_167 +bit 22_168 +bit 22_169 +bit 22_17 +bit 22_170 +bit 22_171 +bit 22_172 +bit 22_173 +bit 22_174 +bit 22_175 +bit 22_176 +bit 22_177 +bit 22_178 +bit 22_179 +bit 22_18 +bit 22_180 +bit 22_181 +bit 22_182 +bit 22_183 +bit 22_184 +bit 22_185 +bit 22_186 +bit 22_187 +bit 22_188 +bit 22_189 +bit 22_19 +bit 22_190 +bit 22_191 +bit 22_192 +bit 22_193 +bit 22_194 +bit 22_195 +bit 22_196 +bit 22_197 +bit 22_198 +bit 22_199 +bit 22_20 +bit 22_200 +bit 22_201 +bit 22_202 +bit 22_203 +bit 22_204 +bit 22_205 +bit 22_206 +bit 22_207 +bit 22_208 +bit 22_209 +bit 22_21 +bit 22_210 +bit 22_211 +bit 22_212 +bit 22_213 +bit 22_214 +bit 22_215 +bit 22_216 +bit 22_217 +bit 22_218 +bit 22_219 +bit 22_22 +bit 22_220 +bit 22_221 +bit 22_222 +bit 22_223 +bit 22_224 +bit 22_225 +bit 22_226 +bit 22_227 +bit 22_228 +bit 22_229 +bit 22_23 +bit 22_230 +bit 22_231 +bit 22_232 +bit 22_233 +bit 22_234 +bit 22_235 +bit 22_236 +bit 22_237 +bit 22_238 +bit 22_239 +bit 22_24 +bit 22_240 +bit 22_241 +bit 22_242 +bit 22_243 +bit 22_244 +bit 22_245 +bit 22_246 +bit 22_247 +bit 22_248 +bit 22_249 +bit 22_25 +bit 22_250 +bit 22_251 +bit 22_252 +bit 22_253 +bit 22_254 +bit 22_255 +bit 22_256 +bit 22_257 +bit 22_258 +bit 22_259 +bit 22_26 +bit 22_260 +bit 22_261 +bit 22_262 +bit 22_263 +bit 22_264 +bit 22_265 +bit 22_266 +bit 22_267 +bit 22_268 +bit 22_269 +bit 22_27 +bit 22_270 +bit 22_271 +bit 22_272 +bit 22_273 +bit 22_274 +bit 22_275 +bit 22_276 +bit 22_277 +bit 22_278 +bit 22_279 +bit 22_28 +bit 22_280 +bit 22_281 +bit 22_282 +bit 22_283 +bit 22_284 +bit 22_285 +bit 22_286 +bit 22_287 +bit 22_288 +bit 22_289 +bit 22_29 +bit 22_290 +bit 22_291 +bit 22_292 +bit 22_293 +bit 22_294 +bit 22_295 +bit 22_296 +bit 22_297 +bit 22_298 +bit 22_299 +bit 22_30 +bit 22_300 +bit 22_301 +bit 22_302 +bit 22_303 +bit 22_304 +bit 22_305 +bit 22_306 +bit 22_307 +bit 22_308 +bit 22_309 +bit 22_31 +bit 22_310 +bit 22_311 +bit 22_312 +bit 22_313 +bit 22_314 +bit 22_315 +bit 22_316 +bit 22_317 +bit 22_318 +bit 22_319 +bit 22_32 +bit 22_33 +bit 22_34 +bit 22_35 +bit 22_36 +bit 22_37 +bit 22_38 +bit 22_39 +bit 22_40 +bit 22_41 +bit 22_42 +bit 22_43 +bit 22_44 +bit 22_45 +bit 22_46 +bit 22_47 +bit 22_48 +bit 22_49 +bit 22_50 +bit 22_51 +bit 22_52 +bit 22_53 +bit 22_54 +bit 22_55 +bit 22_56 +bit 22_57 +bit 22_58 +bit 22_59 +bit 22_60 +bit 22_61 +bit 22_62 +bit 22_63 +bit 22_64 +bit 22_65 +bit 22_66 +bit 22_67 +bit 22_68 +bit 22_69 +bit 22_70 +bit 22_71 +bit 22_72 +bit 22_73 +bit 22_74 +bit 22_75 +bit 22_76 +bit 22_77 +bit 22_78 +bit 22_79 +bit 22_80 +bit 22_81 +bit 22_82 +bit 22_83 +bit 22_84 +bit 22_85 +bit 22_86 +bit 22_87 +bit 22_88 +bit 22_89 +bit 22_90 +bit 22_91 +bit 22_92 +bit 22_93 +bit 22_94 +bit 22_95 +bit 22_96 +bit 22_97 +bit 22_98 +bit 22_99 +bit 23_00 +bit 23_01 +bit 23_02 +bit 23_03 +bit 23_04 +bit 23_05 +bit 23_06 +bit 23_07 +bit 23_08 +bit 23_09 +bit 23_10 +bit 23_100 +bit 23_101 +bit 23_102 +bit 23_103 +bit 23_104 +bit 23_105 +bit 23_106 +bit 23_107 +bit 23_108 +bit 23_109 +bit 23_11 +bit 23_110 +bit 23_111 +bit 23_112 +bit 23_113 +bit 23_114 +bit 23_115 +bit 23_116 +bit 23_117 +bit 23_118 +bit 23_119 +bit 23_12 +bit 23_120 +bit 23_121 +bit 23_122 +bit 23_123 +bit 23_124 +bit 23_125 +bit 23_126 +bit 23_127 +bit 23_128 +bit 23_129 +bit 23_13 +bit 23_130 +bit 23_131 +bit 23_132 +bit 23_133 +bit 23_134 +bit 23_135 +bit 23_136 +bit 23_137 +bit 23_138 +bit 23_139 +bit 23_14 +bit 23_140 +bit 23_141 +bit 23_142 +bit 23_143 +bit 23_144 +bit 23_145 +bit 23_146 +bit 23_147 +bit 23_148 +bit 23_149 +bit 23_15 +bit 23_150 +bit 23_151 +bit 23_152 +bit 23_153 +bit 23_154 +bit 23_155 +bit 23_156 +bit 23_157 +bit 23_158 +bit 23_159 +bit 23_16 +bit 23_160 +bit 23_161 +bit 23_162 +bit 23_163 +bit 23_164 +bit 23_165 +bit 23_166 +bit 23_167 +bit 23_168 +bit 23_169 +bit 23_17 +bit 23_170 +bit 23_171 +bit 23_172 +bit 23_173 +bit 23_174 +bit 23_175 +bit 23_176 +bit 23_177 +bit 23_178 +bit 23_179 +bit 23_18 +bit 23_180 +bit 23_181 +bit 23_182 +bit 23_183 +bit 23_184 +bit 23_185 +bit 23_186 +bit 23_187 +bit 23_188 +bit 23_189 +bit 23_19 +bit 23_190 +bit 23_191 +bit 23_192 +bit 23_193 +bit 23_194 +bit 23_195 +bit 23_196 +bit 23_197 +bit 23_198 +bit 23_199 +bit 23_20 +bit 23_200 +bit 23_201 +bit 23_202 +bit 23_203 +bit 23_204 +bit 23_205 +bit 23_206 +bit 23_207 +bit 23_208 +bit 23_209 +bit 23_21 +bit 23_210 +bit 23_211 +bit 23_212 +bit 23_213 +bit 23_214 +bit 23_215 +bit 23_216 +bit 23_217 +bit 23_218 +bit 23_219 +bit 23_22 +bit 23_220 +bit 23_221 +bit 23_222 +bit 23_223 +bit 23_224 +bit 23_225 +bit 23_226 +bit 23_227 +bit 23_228 +bit 23_229 +bit 23_23 +bit 23_230 +bit 23_231 +bit 23_232 +bit 23_233 +bit 23_234 +bit 23_235 +bit 23_236 +bit 23_237 +bit 23_238 +bit 23_239 +bit 23_24 +bit 23_240 +bit 23_241 +bit 23_242 +bit 23_243 +bit 23_244 +bit 23_245 +bit 23_246 +bit 23_247 +bit 23_248 +bit 23_249 +bit 23_25 +bit 23_250 +bit 23_251 +bit 23_252 +bit 23_253 +bit 23_254 +bit 23_255 +bit 23_256 +bit 23_257 +bit 23_258 +bit 23_259 +bit 23_26 +bit 23_260 +bit 23_261 +bit 23_262 +bit 23_263 +bit 23_264 +bit 23_265 +bit 23_266 +bit 23_267 +bit 23_268 +bit 23_269 +bit 23_27 +bit 23_270 +bit 23_271 +bit 23_272 +bit 23_273 +bit 23_274 +bit 23_275 +bit 23_276 +bit 23_277 +bit 23_278 +bit 23_279 +bit 23_28 +bit 23_280 +bit 23_281 +bit 23_282 +bit 23_283 +bit 23_284 +bit 23_285 +bit 23_286 +bit 23_287 +bit 23_288 +bit 23_289 +bit 23_29 +bit 23_290 +bit 23_291 +bit 23_292 +bit 23_293 +bit 23_294 +bit 23_295 +bit 23_296 +bit 23_297 +bit 23_298 +bit 23_299 +bit 23_30 +bit 23_300 +bit 23_301 +bit 23_302 +bit 23_303 +bit 23_304 +bit 23_305 +bit 23_306 +bit 23_307 +bit 23_308 +bit 23_309 +bit 23_31 +bit 23_310 +bit 23_311 +bit 23_312 +bit 23_313 +bit 23_314 +bit 23_315 +bit 23_316 +bit 23_317 +bit 23_318 +bit 23_319 +bit 23_32 +bit 23_33 +bit 23_34 +bit 23_35 +bit 23_36 +bit 23_37 +bit 23_38 +bit 23_39 +bit 23_40 +bit 23_41 +bit 23_42 +bit 23_43 +bit 23_44 +bit 23_45 +bit 23_46 +bit 23_47 +bit 23_48 +bit 23_49 +bit 23_50 +bit 23_51 +bit 23_52 +bit 23_53 +bit 23_54 +bit 23_55 +bit 23_56 +bit 23_57 +bit 23_58 +bit 23_59 +bit 23_60 +bit 23_61 +bit 23_62 +bit 23_63 +bit 23_64 +bit 23_65 +bit 23_66 +bit 23_67 +bit 23_68 +bit 23_69 +bit 23_70 +bit 23_71 +bit 23_72 +bit 23_73 +bit 23_74 +bit 23_75 +bit 23_76 +bit 23_77 +bit 23_78 +bit 23_79 +bit 23_80 +bit 23_81 +bit 23_82 +bit 23_83 +bit 23_84 +bit 23_85 +bit 23_86 +bit 23_87 +bit 23_88 +bit 23_89 +bit 23_90 +bit 23_91 +bit 23_92 +bit 23_93 +bit 23_94 +bit 23_95 +bit 23_96 +bit 23_97 +bit 23_98 +bit 23_99 +bit 24_00 +bit 24_01 +bit 24_02 +bit 24_03 +bit 24_04 +bit 24_05 +bit 24_06 +bit 24_07 +bit 24_08 +bit 24_09 +bit 24_10 +bit 24_100 +bit 24_101 +bit 24_102 +bit 24_103 +bit 24_104 +bit 24_105 +bit 24_106 +bit 24_107 +bit 24_108 +bit 24_109 +bit 24_11 +bit 24_110 +bit 24_111 +bit 24_112 +bit 24_113 +bit 24_114 +bit 24_115 +bit 24_116 +bit 24_117 +bit 24_118 +bit 24_119 +bit 24_12 +bit 24_120 +bit 24_121 +bit 24_122 +bit 24_123 +bit 24_124 +bit 24_125 +bit 24_126 +bit 24_127 +bit 24_128 +bit 24_129 +bit 24_13 +bit 24_130 +bit 24_131 +bit 24_132 +bit 24_133 +bit 24_134 +bit 24_135 +bit 24_136 +bit 24_137 +bit 24_138 +bit 24_139 +bit 24_14 +bit 24_140 +bit 24_141 +bit 24_142 +bit 24_143 +bit 24_144 +bit 24_145 +bit 24_146 +bit 24_147 +bit 24_148 +bit 24_149 +bit 24_15 +bit 24_150 +bit 24_151 +bit 24_152 +bit 24_153 +bit 24_154 +bit 24_155 +bit 24_156 +bit 24_157 +bit 24_158 +bit 24_159 +bit 24_16 +bit 24_160 +bit 24_161 +bit 24_162 +bit 24_163 +bit 24_164 +bit 24_165 +bit 24_166 +bit 24_167 +bit 24_168 +bit 24_169 +bit 24_17 +bit 24_170 +bit 24_171 +bit 24_172 +bit 24_173 +bit 24_174 +bit 24_175 +bit 24_176 +bit 24_177 +bit 24_178 +bit 24_179 +bit 24_18 +bit 24_180 +bit 24_181 +bit 24_182 +bit 24_183 +bit 24_184 +bit 24_185 +bit 24_186 +bit 24_187 +bit 24_188 +bit 24_189 +bit 24_19 +bit 24_190 +bit 24_191 +bit 24_192 +bit 24_193 +bit 24_194 +bit 24_195 +bit 24_196 +bit 24_197 +bit 24_198 +bit 24_199 +bit 24_20 +bit 24_200 +bit 24_201 +bit 24_202 +bit 24_203 +bit 24_204 +bit 24_205 +bit 24_206 +bit 24_207 +bit 24_208 +bit 24_209 +bit 24_21 +bit 24_210 +bit 24_211 +bit 24_212 +bit 24_213 +bit 24_214 +bit 24_215 +bit 24_216 +bit 24_217 +bit 24_218 +bit 24_219 +bit 24_22 +bit 24_220 +bit 24_221 +bit 24_222 +bit 24_223 +bit 24_224 +bit 24_225 +bit 24_226 +bit 24_227 +bit 24_228 +bit 24_229 +bit 24_23 +bit 24_230 +bit 24_231 +bit 24_232 +bit 24_233 +bit 24_234 +bit 24_235 +bit 24_236 +bit 24_237 +bit 24_238 +bit 24_239 +bit 24_24 +bit 24_240 +bit 24_241 +bit 24_242 +bit 24_243 +bit 24_244 +bit 24_245 +bit 24_246 +bit 24_247 +bit 24_248 +bit 24_249 +bit 24_25 +bit 24_250 +bit 24_251 +bit 24_252 +bit 24_253 +bit 24_254 +bit 24_255 +bit 24_256 +bit 24_257 +bit 24_258 +bit 24_259 +bit 24_26 +bit 24_260 +bit 24_261 +bit 24_262 +bit 24_263 +bit 24_264 +bit 24_265 +bit 24_266 +bit 24_267 +bit 24_268 +bit 24_269 +bit 24_27 +bit 24_270 +bit 24_271 +bit 24_272 +bit 24_273 +bit 24_274 +bit 24_275 +bit 24_276 +bit 24_277 +bit 24_278 +bit 24_279 +bit 24_28 +bit 24_280 +bit 24_281 +bit 24_282 +bit 24_283 +bit 24_284 +bit 24_285 +bit 24_286 +bit 24_287 +bit 24_288 +bit 24_289 +bit 24_29 +bit 24_290 +bit 24_291 +bit 24_292 +bit 24_293 +bit 24_294 +bit 24_295 +bit 24_296 +bit 24_297 +bit 24_298 +bit 24_299 +bit 24_30 +bit 24_300 +bit 24_301 +bit 24_302 +bit 24_303 +bit 24_304 +bit 24_305 +bit 24_306 +bit 24_307 +bit 24_308 +bit 24_309 +bit 24_31 +bit 24_310 +bit 24_311 +bit 24_312 +bit 24_313 +bit 24_314 +bit 24_315 +bit 24_316 +bit 24_317 +bit 24_318 +bit 24_319 +bit 24_32 +bit 24_33 +bit 24_34 +bit 24_35 +bit 24_36 +bit 24_37 +bit 24_38 +bit 24_39 +bit 24_40 +bit 24_41 +bit 24_42 +bit 24_43 +bit 24_44 +bit 24_45 +bit 24_46 +bit 24_47 +bit 24_48 +bit 24_49 +bit 24_50 +bit 24_51 +bit 24_52 +bit 24_53 +bit 24_54 +bit 24_55 +bit 24_56 +bit 24_57 +bit 24_58 +bit 24_59 +bit 24_60 +bit 24_61 +bit 24_62 +bit 24_63 +bit 24_64 +bit 24_65 +bit 24_66 +bit 24_67 +bit 24_68 +bit 24_69 +bit 24_70 +bit 24_71 +bit 24_72 +bit 24_73 +bit 24_74 +bit 24_75 +bit 24_76 +bit 24_77 +bit 24_78 +bit 24_79 +bit 24_80 +bit 24_81 +bit 24_82 +bit 24_83 +bit 24_84 +bit 24_85 +bit 24_86 +bit 24_87 +bit 24_88 +bit 24_89 +bit 24_90 +bit 24_91 +bit 24_92 +bit 24_93 +bit 24_94 +bit 24_95 +bit 24_96 +bit 24_97 +bit 24_98 +bit 24_99 +bit 25_00 +bit 25_01 +bit 25_02 +bit 25_03 +bit 25_04 +bit 25_05 +bit 25_06 +bit 25_07 +bit 25_08 +bit 25_09 +bit 25_10 +bit 25_100 +bit 25_101 +bit 25_102 +bit 25_103 +bit 25_104 +bit 25_105 +bit 25_106 +bit 25_107 +bit 25_108 +bit 25_109 +bit 25_11 +bit 25_110 +bit 25_111 +bit 25_112 +bit 25_113 +bit 25_114 +bit 25_115 +bit 25_116 +bit 25_117 +bit 25_118 +bit 25_119 +bit 25_12 +bit 25_120 +bit 25_121 +bit 25_122 +bit 25_123 +bit 25_124 +bit 25_125 +bit 25_126 +bit 25_127 +bit 25_128 +bit 25_129 +bit 25_13 +bit 25_130 +bit 25_131 +bit 25_132 +bit 25_133 +bit 25_134 +bit 25_135 +bit 25_136 +bit 25_137 +bit 25_138 +bit 25_139 +bit 25_14 +bit 25_140 +bit 25_141 +bit 25_142 +bit 25_143 +bit 25_144 +bit 25_145 +bit 25_146 +bit 25_147 +bit 25_148 +bit 25_149 +bit 25_15 +bit 25_150 +bit 25_151 +bit 25_152 +bit 25_153 +bit 25_154 +bit 25_155 +bit 25_156 +bit 25_157 +bit 25_158 +bit 25_159 +bit 25_16 +bit 25_160 +bit 25_161 +bit 25_162 +bit 25_163 +bit 25_164 +bit 25_165 +bit 25_166 +bit 25_167 +bit 25_168 +bit 25_169 +bit 25_17 +bit 25_170 +bit 25_171 +bit 25_172 +bit 25_173 +bit 25_174 +bit 25_175 +bit 25_176 +bit 25_177 +bit 25_178 +bit 25_179 +bit 25_18 +bit 25_180 +bit 25_181 +bit 25_182 +bit 25_183 +bit 25_184 +bit 25_185 +bit 25_186 +bit 25_187 +bit 25_188 +bit 25_189 +bit 25_19 +bit 25_190 +bit 25_191 +bit 25_192 +bit 25_193 +bit 25_194 +bit 25_195 +bit 25_196 +bit 25_197 +bit 25_198 +bit 25_199 +bit 25_20 +bit 25_200 +bit 25_201 +bit 25_202 +bit 25_203 +bit 25_204 +bit 25_205 +bit 25_206 +bit 25_207 +bit 25_208 +bit 25_209 +bit 25_21 +bit 25_210 +bit 25_211 +bit 25_212 +bit 25_213 +bit 25_214 +bit 25_215 +bit 25_216 +bit 25_217 +bit 25_218 +bit 25_219 +bit 25_22 +bit 25_220 +bit 25_221 +bit 25_222 +bit 25_223 +bit 25_224 +bit 25_225 +bit 25_226 +bit 25_227 +bit 25_228 +bit 25_229 +bit 25_23 +bit 25_230 +bit 25_231 +bit 25_232 +bit 25_233 +bit 25_234 +bit 25_235 +bit 25_236 +bit 25_237 +bit 25_238 +bit 25_239 +bit 25_24 +bit 25_240 +bit 25_241 +bit 25_242 +bit 25_243 +bit 25_244 +bit 25_245 +bit 25_246 +bit 25_247 +bit 25_248 +bit 25_249 +bit 25_25 +bit 25_250 +bit 25_251 +bit 25_252 +bit 25_253 +bit 25_254 +bit 25_255 +bit 25_256 +bit 25_257 +bit 25_258 +bit 25_259 +bit 25_26 +bit 25_260 +bit 25_261 +bit 25_262 +bit 25_263 +bit 25_264 +bit 25_265 +bit 25_266 +bit 25_267 +bit 25_268 +bit 25_269 +bit 25_27 +bit 25_270 +bit 25_271 +bit 25_272 +bit 25_273 +bit 25_274 +bit 25_275 +bit 25_276 +bit 25_277 +bit 25_278 +bit 25_279 +bit 25_28 +bit 25_280 +bit 25_281 +bit 25_282 +bit 25_283 +bit 25_284 +bit 25_285 +bit 25_286 +bit 25_287 +bit 25_288 +bit 25_289 +bit 25_29 +bit 25_290 +bit 25_291 +bit 25_292 +bit 25_293 +bit 25_294 +bit 25_295 +bit 25_296 +bit 25_297 +bit 25_298 +bit 25_299 +bit 25_30 +bit 25_300 +bit 25_301 +bit 25_302 +bit 25_303 +bit 25_304 +bit 25_305 +bit 25_306 +bit 25_307 +bit 25_308 +bit 25_309 +bit 25_31 +bit 25_310 +bit 25_311 +bit 25_312 +bit 25_313 +bit 25_314 +bit 25_315 +bit 25_316 +bit 25_317 +bit 25_318 +bit 25_319 +bit 25_32 +bit 25_33 +bit 25_34 +bit 25_35 +bit 25_36 +bit 25_37 +bit 25_38 +bit 25_39 +bit 25_40 +bit 25_41 +bit 25_42 +bit 25_43 +bit 25_44 +bit 25_45 +bit 25_46 +bit 25_47 +bit 25_48 +bit 25_49 +bit 25_50 +bit 25_51 +bit 25_52 +bit 25_53 +bit 25_54 +bit 25_55 +bit 25_56 +bit 25_57 +bit 25_58 +bit 25_59 +bit 25_60 +bit 25_61 +bit 25_62 +bit 25_63 +bit 25_64 +bit 25_65 +bit 25_66 +bit 25_67 +bit 25_68 +bit 25_69 +bit 25_70 +bit 25_71 +bit 25_72 +bit 25_73 +bit 25_74 +bit 25_75 +bit 25_76 +bit 25_77 +bit 25_78 +bit 25_79 +bit 25_80 +bit 25_81 +bit 25_82 +bit 25_83 +bit 25_84 +bit 25_85 +bit 25_86 +bit 25_87 +bit 25_88 +bit 25_89 +bit 25_90 +bit 25_91 +bit 25_92 +bit 25_93 +bit 25_94 +bit 25_95 +bit 25_96 +bit 25_97 +bit 25_98 +bit 25_99 +bit 30_02 +bit 30_101 +bit 30_124 +bit 30_130 +bit 30_153 +bit 30_165 +bit 30_188 +bit 30_194 +bit 30_217 +bit 30_229 +bit 30_25 +bit 30_252 +bit 30_258 +bit 30_281 +bit 30_293 +bit 30_316 +bit 30_37 +bit 30_60 +bit 30_66 +bit 30_89 +bit 31_02 +bit 31_101 +bit 31_126 +bit 31_130 +bit 31_154 +bit 31_165 +bit 31_190 +bit 31_194 +bit 31_218 +bit 31_229 +bit 31_254 +bit 31_258 +bit 31_26 +bit 31_282 +bit 31_293 +bit 31_318 +bit 31_37 +bit 31_62 +bit 31_66 +bit 31_90 diff --git a/kintex7/mask_hclk_l.db b/kintex7/mask_hclk_l.db new file mode 100644 index 0000000..bd3dec1 --- /dev/null +++ b/kintex7/mask_hclk_l.db @@ -0,0 +1,104 @@ +bit 00_14 +bit 00_15 +bit 00_16 +bit 00_17 +bit 00_18 +bit 00_20 +bit 00_21 +bit 00_22 +bit 00_23 +bit 00_24 +bit 00_25 +bit 00_26 +bit 00_28 +bit 00_29 +bit 00_30 +bit 00_31 +bit 01_14 +bit 01_15 +bit 01_16 +bit 01_17 +bit 01_19 +bit 01_20 +bit 01_21 +bit 01_22 +bit 01_23 +bit 01_24 +bit 01_25 +bit 01_26 +bit 01_28 +bit 01_29 +bit 01_30 +bit 01_31 +bit 02_14 +bit 02_15 +bit 02_16 +bit 02_17 +bit 02_18 +bit 02_19 +bit 02_20 +bit 02_21 +bit 02_22 +bit 02_23 +bit 02_24 +bit 02_25 +bit 02_26 +bit 02_27 +bit 02_28 +bit 02_29 +bit 02_30 +bit 02_31 +bit 03_14 +bit 03_15 +bit 03_16 +bit 03_17 +bit 03_18 +bit 03_19 +bit 03_20 +bit 03_21 +bit 03_22 +bit 03_23 +bit 03_24 +bit 03_25 +bit 03_26 +bit 03_27 +bit 03_28 +bit 03_29 +bit 03_30 +bit 03_31 +bit 04_14 +bit 04_15 +bit 04_16 +bit 04_17 +bit 04_18 +bit 04_19 +bit 04_20 +bit 04_21 +bit 04_22 +bit 04_23 +bit 04_24 +bit 04_25 +bit 04_26 +bit 04_27 +bit 04_28 +bit 04_29 +bit 04_30 +bit 04_31 +bit 05_14 +bit 05_15 +bit 05_16 +bit 05_17 +bit 05_18 +bit 05_19 +bit 05_20 +bit 05_21 +bit 05_22 +bit 05_23 +bit 05_24 +bit 05_25 +bit 05_26 +bit 05_27 +bit 05_28 +bit 05_29 +bit 05_30 +bit 05_31 diff --git a/kintex7/mask_hclk_r.db b/kintex7/mask_hclk_r.db new file mode 100644 index 0000000..bd3dec1 --- /dev/null +++ b/kintex7/mask_hclk_r.db @@ -0,0 +1,104 @@ +bit 00_14 +bit 00_15 +bit 00_16 +bit 00_17 +bit 00_18 +bit 00_20 +bit 00_21 +bit 00_22 +bit 00_23 +bit 00_24 +bit 00_25 +bit 00_26 +bit 00_28 +bit 00_29 +bit 00_30 +bit 00_31 +bit 01_14 +bit 01_15 +bit 01_16 +bit 01_17 +bit 01_19 +bit 01_20 +bit 01_21 +bit 01_22 +bit 01_23 +bit 01_24 +bit 01_25 +bit 01_26 +bit 01_28 +bit 01_29 +bit 01_30 +bit 01_31 +bit 02_14 +bit 02_15 +bit 02_16 +bit 02_17 +bit 02_18 +bit 02_19 +bit 02_20 +bit 02_21 +bit 02_22 +bit 02_23 +bit 02_24 +bit 02_25 +bit 02_26 +bit 02_27 +bit 02_28 +bit 02_29 +bit 02_30 +bit 02_31 +bit 03_14 +bit 03_15 +bit 03_16 +bit 03_17 +bit 03_18 +bit 03_19 +bit 03_20 +bit 03_21 +bit 03_22 +bit 03_23 +bit 03_24 +bit 03_25 +bit 03_26 +bit 03_27 +bit 03_28 +bit 03_29 +bit 03_30 +bit 03_31 +bit 04_14 +bit 04_15 +bit 04_16 +bit 04_17 +bit 04_18 +bit 04_19 +bit 04_20 +bit 04_21 +bit 04_22 +bit 04_23 +bit 04_24 +bit 04_25 +bit 04_26 +bit 04_27 +bit 04_28 +bit 04_29 +bit 04_30 +bit 04_31 +bit 05_14 +bit 05_15 +bit 05_16 +bit 05_17 +bit 05_18 +bit 05_19 +bit 05_20 +bit 05_21 +bit 05_22 +bit 05_23 +bit 05_24 +bit 05_25 +bit 05_26 +bit 05_27 +bit 05_28 +bit 05_29 +bit 05_30 +bit 05_31 diff --git a/kintex7/ppips_clbll_l.db b/kintex7/ppips_clbll_l.db new file mode 100644 index 0000000..bebd189 --- /dev/null +++ b/kintex7/ppips_clbll_l.db @@ -0,0 +1,146 @@ +CLBLL_L.CLBLL_L_AX.CLBLL_BYP0 always +CLBLL_L.CLBLL_LL_AX.CLBLL_BYP1 always +CLBLL_L.CLBLL_L_CX.CLBLL_BYP2 always +CLBLL_L.CLBLL_LL_CX.CLBLL_BYP3 always +CLBLL_L.CLBLL_LL_BX.CLBLL_BYP4 always +CLBLL_L.CLBLL_L_BX.CLBLL_BYP5 always +CLBLL_L.CLBLL_LL_DX.CLBLL_BYP6 always +CLBLL_L.CLBLL_L_DX.CLBLL_BYP7 always +CLBLL_L.CLBLL_L_CLK.CLBLL_CLK0 always +CLBLL_L.CLBLL_LL_CLK.CLBLL_CLK1 always +CLBLL_L.CLBLL_L_SR.CLBLL_CTRL0 always +CLBLL_L.CLBLL_LL_SR.CLBLL_CTRL1 always +CLBLL_L.CLBLL_L_CE.CLBLL_FAN6 always +CLBLL_L.CLBLL_LL_CE.CLBLL_FAN7 always +CLBLL_L.CLBLL_L_A3.CLBLL_IMUX0 always +CLBLL_L.CLBLL_L_A2.CLBLL_IMUX3 always +CLBLL_L.CLBLL_L_A6.CLBLL_IMUX5 always +CLBLL_L.CLBLL_L_A1.CLBLL_IMUX6 always +CLBLL_L.CLBLL_L_A5.CLBLL_IMUX9 always +CLBLL_L.CLBLL_L_A4.CLBLL_IMUX10 always +CLBLL_L.CLBLL_LL_A3.CLBLL_IMUX1 always +CLBLL_L.CLBLL_LL_A2.CLBLL_IMUX2 always +CLBLL_L.CLBLL_LL_A6.CLBLL_IMUX4 always +CLBLL_L.CLBLL_LL_A1.CLBLL_IMUX7 always +CLBLL_L.CLBLL_LL_A5.CLBLL_IMUX8 always +CLBLL_L.CLBLL_LL_A4.CLBLL_IMUX11 always +CLBLL_L.CLBLL_LL_B6.CLBLL_IMUX12 always +CLBLL_L.CLBLL_LL_B1.CLBLL_IMUX15 always +CLBLL_L.CLBLL_LL_B3.CLBLL_IMUX17 always +CLBLL_L.CLBLL_LL_B2.CLBLL_IMUX18 always +CLBLL_L.CLBLL_LL_B5.CLBLL_IMUX24 always +CLBLL_L.CLBLL_LL_B4.CLBLL_IMUX27 always +CLBLL_L.CLBLL_L_B6.CLBLL_IMUX13 always +CLBLL_L.CLBLL_L_B1.CLBLL_IMUX14 always +CLBLL_L.CLBLL_L_B3.CLBLL_IMUX16 always +CLBLL_L.CLBLL_L_B2.CLBLL_IMUX19 always +CLBLL_L.CLBLL_L_B5.CLBLL_IMUX25 always +CLBLL_L.CLBLL_L_B4.CLBLL_IMUX26 always +CLBLL_L.CLBLL_L_C2.CLBLL_IMUX20 always +CLBLL_L.CLBLL_L_C4.CLBLL_IMUX21 always +CLBLL_L.CLBLL_L_C3.CLBLL_IMUX23 always +CLBLL_L.CLBLL_L_C5.CLBLL_IMUX30 always +CLBLL_L.CLBLL_L_C1.CLBLL_IMUX33 always +CLBLL_L.CLBLL_L_C6.CLBLL_IMUX34 always +CLBLL_L.CLBLL_LL_C3.CLBLL_IMUX22 always +CLBLL_L.CLBLL_LL_C4.CLBLL_IMUX28 always +CLBLL_L.CLBLL_LL_C2.CLBLL_IMUX29 always +CLBLL_L.CLBLL_LL_C5.CLBLL_IMUX31 always +CLBLL_L.CLBLL_LL_C1.CLBLL_IMUX32 always +CLBLL_L.CLBLL_LL_C6.CLBLL_IMUX35 always +CLBLL_L.CLBLL_L_D2.CLBLL_IMUX36 always +CLBLL_L.CLBLL_L_D4.CLBLL_IMUX37 always +CLBLL_L.CLBLL_L_D3.CLBLL_IMUX39 always +CLBLL_L.CLBLL_L_D1.CLBLL_IMUX41 always +CLBLL_L.CLBLL_L_D6.CLBLL_IMUX42 always +CLBLL_L.CLBLL_L_D5.CLBLL_IMUX46 always +CLBLL_L.CLBLL_LL_D3.CLBLL_IMUX38 always +CLBLL_L.CLBLL_LL_D1.CLBLL_IMUX40 always +CLBLL_L.CLBLL_LL_D6.CLBLL_IMUX43 always +CLBLL_L.CLBLL_LL_D4.CLBLL_IMUX44 always +CLBLL_L.CLBLL_LL_D2.CLBLL_IMUX45 always +CLBLL_L.CLBLL_LL_D5.CLBLL_IMUX47 always +CLBLL_L.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always +CLBLL_L.CLBLL_LL_AMUX.CLBLL_LL_A hint +CLBLL_L.CLBLL_LL_A.CLBLL_LL_A1 hint +CLBLL_L.CLBLL_LL_A.CLBLL_LL_A2 hint +CLBLL_L.CLBLL_LL_A.CLBLL_LL_A3 hint +CLBLL_L.CLBLL_LL_A.CLBLL_LL_A4 hint +CLBLL_L.CLBLL_LL_A.CLBLL_LL_A5 hint +CLBLL_L.CLBLL_LL_A.CLBLL_LL_A6 hint +CLBLL_L.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always +CLBLL_L.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always +CLBLL_L.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always +CLBLL_L.CLBLL_LL_BMUX.CLBLL_LL_B hint +CLBLL_L.CLBLL_LL_B.CLBLL_LL_B1 hint +CLBLL_L.CLBLL_LL_B.CLBLL_LL_B2 hint +CLBLL_L.CLBLL_LL_B.CLBLL_LL_B3 hint +CLBLL_L.CLBLL_LL_B.CLBLL_LL_B4 hint +CLBLL_L.CLBLL_LL_B.CLBLL_LL_B5 hint +CLBLL_L.CLBLL_LL_B.CLBLL_LL_B6 hint +CLBLL_L.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always +CLBLL_L.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always +CLBLL_L.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always +CLBLL_L.CLBLL_LL_CMUX.CLBLL_LL_C hint +CLBLL_L.CLBLL_LL_C.CLBLL_LL_C1 hint +CLBLL_L.CLBLL_LL_C.CLBLL_LL_C2 hint +CLBLL_L.CLBLL_LL_C.CLBLL_LL_C3 hint +CLBLL_L.CLBLL_LL_C.CLBLL_LL_C4 hint +CLBLL_L.CLBLL_LL_C.CLBLL_LL_C5 hint +CLBLL_L.CLBLL_LL_C.CLBLL_LL_C6 hint +CLBLL_L.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always +CLBLL_L.CLBLL_LL_COUT_N.CLBLL_LL_COUT always +CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_COUT hint +CLBLL_L.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always +CLBLL_L.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always +CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_D hint +CLBLL_L.CLBLL_LL_D.CLBLL_LL_D1 hint +CLBLL_L.CLBLL_LL_D.CLBLL_LL_D2 hint +CLBLL_L.CLBLL_LL_D.CLBLL_LL_D3 hint +CLBLL_L.CLBLL_LL_D.CLBLL_LL_D4 hint +CLBLL_L.CLBLL_LL_D.CLBLL_LL_D5 hint +CLBLL_L.CLBLL_LL_D.CLBLL_LL_D6 hint +CLBLL_L.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always +CLBLL_L.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always +CLBLL_L.CLBLL_LOGIC_OUTS8.CLBLL_L_A always +CLBLL_L.CLBLL_L_AMUX.CLBLL_L_A hint +CLBLL_L.CLBLL_L_A.CLBLL_L_A1 hint +CLBLL_L.CLBLL_L_A.CLBLL_L_A2 hint +CLBLL_L.CLBLL_L_A.CLBLL_L_A3 hint +CLBLL_L.CLBLL_L_A.CLBLL_L_A4 hint +CLBLL_L.CLBLL_L_A.CLBLL_L_A5 hint +CLBLL_L.CLBLL_L_A.CLBLL_L_A6 hint +CLBLL_L.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always +CLBLL_L.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always +CLBLL_L.CLBLL_LOGIC_OUTS9.CLBLL_L_B always +CLBLL_L.CLBLL_L_BMUX.CLBLL_L_B hint +CLBLL_L.CLBLL_L_B.CLBLL_L_B1 hint +CLBLL_L.CLBLL_L_B.CLBLL_L_B2 hint +CLBLL_L.CLBLL_L_B.CLBLL_L_B3 hint +CLBLL_L.CLBLL_L_B.CLBLL_L_B4 hint +CLBLL_L.CLBLL_L_B.CLBLL_L_B5 hint +CLBLL_L.CLBLL_L_B.CLBLL_L_B6 hint +CLBLL_L.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always +CLBLL_L.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always +CLBLL_L.CLBLL_LOGIC_OUTS10.CLBLL_L_C always +CLBLL_L.CLBLL_L_CMUX.CLBLL_L_C hint +CLBLL_L.CLBLL_L_C.CLBLL_L_C1 hint +CLBLL_L.CLBLL_L_C.CLBLL_L_C2 hint +CLBLL_L.CLBLL_L_C.CLBLL_L_C3 hint +CLBLL_L.CLBLL_L_C.CLBLL_L_C4 hint +CLBLL_L.CLBLL_L_C.CLBLL_L_C5 hint +CLBLL_L.CLBLL_L_C.CLBLL_L_C6 hint +CLBLL_L.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always +CLBLL_L.CLBLL_L_COUT_N.CLBLL_L_COUT always +CLBLL_L.CLBLL_L_DMUX.CLBLL_L_COUT hint +CLBLL_L.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always +CLBLL_L.CLBLL_LOGIC_OUTS11.CLBLL_L_D always +CLBLL_L.CLBLL_L_DMUX.CLBLL_L_D hint +CLBLL_L.CLBLL_L_D.CLBLL_L_D1 hint +CLBLL_L.CLBLL_L_D.CLBLL_L_D2 hint +CLBLL_L.CLBLL_L_D.CLBLL_L_D3 hint +CLBLL_L.CLBLL_L_D.CLBLL_L_D4 hint +CLBLL_L.CLBLL_L_D.CLBLL_L_D5 hint +CLBLL_L.CLBLL_L_D.CLBLL_L_D6 hint +CLBLL_L.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always +CLBLL_L.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always diff --git a/kintex7/ppips_clbll_r.db b/kintex7/ppips_clbll_r.db new file mode 100644 index 0000000..e65a962 --- /dev/null +++ b/kintex7/ppips_clbll_r.db @@ -0,0 +1,146 @@ +CLBLL_R.CLBLL_L_AX.CLBLL_BYP0 always +CLBLL_R.CLBLL_LL_AX.CLBLL_BYP1 always +CLBLL_R.CLBLL_L_CX.CLBLL_BYP2 always +CLBLL_R.CLBLL_LL_CX.CLBLL_BYP3 always +CLBLL_R.CLBLL_LL_BX.CLBLL_BYP4 always +CLBLL_R.CLBLL_L_BX.CLBLL_BYP5 always +CLBLL_R.CLBLL_LL_DX.CLBLL_BYP6 always +CLBLL_R.CLBLL_L_DX.CLBLL_BYP7 always +CLBLL_R.CLBLL_L_CLK.CLBLL_CLK0 always +CLBLL_R.CLBLL_LL_CLK.CLBLL_CLK1 always +CLBLL_R.CLBLL_L_SR.CLBLL_CTRL0 always +CLBLL_R.CLBLL_LL_SR.CLBLL_CTRL1 always +CLBLL_R.CLBLL_L_CE.CLBLL_FAN6 always +CLBLL_R.CLBLL_LL_CE.CLBLL_FAN7 always +CLBLL_R.CLBLL_L_A3.CLBLL_IMUX0 always +CLBLL_R.CLBLL_L_A2.CLBLL_IMUX3 always +CLBLL_R.CLBLL_L_A6.CLBLL_IMUX5 always +CLBLL_R.CLBLL_L_A1.CLBLL_IMUX6 always +CLBLL_R.CLBLL_L_A5.CLBLL_IMUX9 always +CLBLL_R.CLBLL_L_A4.CLBLL_IMUX10 always +CLBLL_R.CLBLL_LL_A3.CLBLL_IMUX1 always +CLBLL_R.CLBLL_LL_A2.CLBLL_IMUX2 always +CLBLL_R.CLBLL_LL_A6.CLBLL_IMUX4 always +CLBLL_R.CLBLL_LL_A1.CLBLL_IMUX7 always +CLBLL_R.CLBLL_LL_A5.CLBLL_IMUX8 always +CLBLL_R.CLBLL_LL_A4.CLBLL_IMUX11 always +CLBLL_R.CLBLL_LL_B6.CLBLL_IMUX12 always +CLBLL_R.CLBLL_LL_B1.CLBLL_IMUX15 always +CLBLL_R.CLBLL_LL_B3.CLBLL_IMUX17 always +CLBLL_R.CLBLL_LL_B2.CLBLL_IMUX18 always +CLBLL_R.CLBLL_LL_B5.CLBLL_IMUX24 always +CLBLL_R.CLBLL_LL_B4.CLBLL_IMUX27 always +CLBLL_R.CLBLL_L_B6.CLBLL_IMUX13 always +CLBLL_R.CLBLL_L_B1.CLBLL_IMUX14 always +CLBLL_R.CLBLL_L_B3.CLBLL_IMUX16 always +CLBLL_R.CLBLL_L_B2.CLBLL_IMUX19 always +CLBLL_R.CLBLL_L_B5.CLBLL_IMUX25 always +CLBLL_R.CLBLL_L_B4.CLBLL_IMUX26 always +CLBLL_R.CLBLL_L_C2.CLBLL_IMUX20 always +CLBLL_R.CLBLL_L_C4.CLBLL_IMUX21 always +CLBLL_R.CLBLL_L_C3.CLBLL_IMUX23 always +CLBLL_R.CLBLL_L_C5.CLBLL_IMUX30 always +CLBLL_R.CLBLL_L_C1.CLBLL_IMUX33 always +CLBLL_R.CLBLL_L_C6.CLBLL_IMUX34 always +CLBLL_R.CLBLL_LL_C3.CLBLL_IMUX22 always +CLBLL_R.CLBLL_LL_C4.CLBLL_IMUX28 always +CLBLL_R.CLBLL_LL_C2.CLBLL_IMUX29 always +CLBLL_R.CLBLL_LL_C5.CLBLL_IMUX31 always +CLBLL_R.CLBLL_LL_C1.CLBLL_IMUX32 always +CLBLL_R.CLBLL_LL_C6.CLBLL_IMUX35 always +CLBLL_R.CLBLL_L_D2.CLBLL_IMUX36 always +CLBLL_R.CLBLL_L_D4.CLBLL_IMUX37 always +CLBLL_R.CLBLL_L_D3.CLBLL_IMUX39 always +CLBLL_R.CLBLL_L_D1.CLBLL_IMUX41 always +CLBLL_R.CLBLL_L_D6.CLBLL_IMUX42 always +CLBLL_R.CLBLL_L_D5.CLBLL_IMUX46 always +CLBLL_R.CLBLL_LL_D3.CLBLL_IMUX38 always +CLBLL_R.CLBLL_LL_D1.CLBLL_IMUX40 always +CLBLL_R.CLBLL_LL_D6.CLBLL_IMUX43 always +CLBLL_R.CLBLL_LL_D4.CLBLL_IMUX44 always +CLBLL_R.CLBLL_LL_D2.CLBLL_IMUX45 always +CLBLL_R.CLBLL_LL_D5.CLBLL_IMUX47 always +CLBLL_R.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always +CLBLL_R.CLBLL_LL_AMUX.CLBLL_LL_A hint +CLBLL_R.CLBLL_LL_A.CLBLL_LL_A1 hint +CLBLL_R.CLBLL_LL_A.CLBLL_LL_A2 hint +CLBLL_R.CLBLL_LL_A.CLBLL_LL_A3 hint +CLBLL_R.CLBLL_LL_A.CLBLL_LL_A4 hint +CLBLL_R.CLBLL_LL_A.CLBLL_LL_A5 hint +CLBLL_R.CLBLL_LL_A.CLBLL_LL_A6 hint +CLBLL_R.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always +CLBLL_R.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always +CLBLL_R.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always +CLBLL_R.CLBLL_LL_BMUX.CLBLL_LL_B hint +CLBLL_R.CLBLL_LL_B.CLBLL_LL_B1 hint +CLBLL_R.CLBLL_LL_B.CLBLL_LL_B2 hint +CLBLL_R.CLBLL_LL_B.CLBLL_LL_B3 hint +CLBLL_R.CLBLL_LL_B.CLBLL_LL_B4 hint +CLBLL_R.CLBLL_LL_B.CLBLL_LL_B5 hint +CLBLL_R.CLBLL_LL_B.CLBLL_LL_B6 hint +CLBLL_R.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always +CLBLL_R.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always +CLBLL_R.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always +CLBLL_R.CLBLL_LL_CMUX.CLBLL_LL_C hint +CLBLL_R.CLBLL_LL_C.CLBLL_LL_C1 hint +CLBLL_R.CLBLL_LL_C.CLBLL_LL_C2 hint +CLBLL_R.CLBLL_LL_C.CLBLL_LL_C3 hint +CLBLL_R.CLBLL_LL_C.CLBLL_LL_C4 hint +CLBLL_R.CLBLL_LL_C.CLBLL_LL_C5 hint +CLBLL_R.CLBLL_LL_C.CLBLL_LL_C6 hint +CLBLL_R.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always +CLBLL_R.CLBLL_LL_COUT_N.CLBLL_LL_COUT always +CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_COUT hint +CLBLL_R.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always +CLBLL_R.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always +CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_D hint +CLBLL_R.CLBLL_LL_D.CLBLL_LL_D1 hint +CLBLL_R.CLBLL_LL_D.CLBLL_LL_D2 hint +CLBLL_R.CLBLL_LL_D.CLBLL_LL_D3 hint +CLBLL_R.CLBLL_LL_D.CLBLL_LL_D4 hint +CLBLL_R.CLBLL_LL_D.CLBLL_LL_D5 hint +CLBLL_R.CLBLL_LL_D.CLBLL_LL_D6 hint +CLBLL_R.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always +CLBLL_R.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always +CLBLL_R.CLBLL_LOGIC_OUTS8.CLBLL_L_A always +CLBLL_R.CLBLL_L_AMUX.CLBLL_L_A hint +CLBLL_R.CLBLL_L_A.CLBLL_L_A1 hint +CLBLL_R.CLBLL_L_A.CLBLL_L_A2 hint +CLBLL_R.CLBLL_L_A.CLBLL_L_A3 hint +CLBLL_R.CLBLL_L_A.CLBLL_L_A4 hint +CLBLL_R.CLBLL_L_A.CLBLL_L_A5 hint +CLBLL_R.CLBLL_L_A.CLBLL_L_A6 hint +CLBLL_R.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always +CLBLL_R.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always +CLBLL_R.CLBLL_LOGIC_OUTS9.CLBLL_L_B always +CLBLL_R.CLBLL_L_BMUX.CLBLL_L_B hint +CLBLL_R.CLBLL_L_B.CLBLL_L_B1 hint +CLBLL_R.CLBLL_L_B.CLBLL_L_B2 hint +CLBLL_R.CLBLL_L_B.CLBLL_L_B3 hint +CLBLL_R.CLBLL_L_B.CLBLL_L_B4 hint +CLBLL_R.CLBLL_L_B.CLBLL_L_B5 hint +CLBLL_R.CLBLL_L_B.CLBLL_L_B6 hint +CLBLL_R.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always +CLBLL_R.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always +CLBLL_R.CLBLL_LOGIC_OUTS10.CLBLL_L_C always +CLBLL_R.CLBLL_L_CMUX.CLBLL_L_C hint +CLBLL_R.CLBLL_L_C.CLBLL_L_C1 hint +CLBLL_R.CLBLL_L_C.CLBLL_L_C2 hint +CLBLL_R.CLBLL_L_C.CLBLL_L_C3 hint +CLBLL_R.CLBLL_L_C.CLBLL_L_C4 hint +CLBLL_R.CLBLL_L_C.CLBLL_L_C5 hint +CLBLL_R.CLBLL_L_C.CLBLL_L_C6 hint +CLBLL_R.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always +CLBLL_R.CLBLL_L_COUT_N.CLBLL_L_COUT always +CLBLL_R.CLBLL_L_DMUX.CLBLL_L_COUT hint +CLBLL_R.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always +CLBLL_R.CLBLL_LOGIC_OUTS11.CLBLL_L_D always +CLBLL_R.CLBLL_L_DMUX.CLBLL_L_D hint +CLBLL_R.CLBLL_L_D.CLBLL_L_D1 hint +CLBLL_R.CLBLL_L_D.CLBLL_L_D2 hint +CLBLL_R.CLBLL_L_D.CLBLL_L_D3 hint +CLBLL_R.CLBLL_L_D.CLBLL_L_D4 hint +CLBLL_R.CLBLL_L_D.CLBLL_L_D5 hint +CLBLL_R.CLBLL_L_D.CLBLL_L_D6 hint +CLBLL_R.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always +CLBLL_R.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always diff --git a/kintex7/ppips_clblm_l.db b/kintex7/ppips_clblm_l.db new file mode 100644 index 0000000..a185ea1 --- /dev/null +++ b/kintex7/ppips_clblm_l.db @@ -0,0 +1,151 @@ +CLBLM_L.CLBLM_L_AX.CLBLM_BYP0 always +CLBLM_L.CLBLM_M_AX.CLBLM_BYP1 always +CLBLM_L.CLBLM_L_CX.CLBLM_BYP2 always +CLBLM_L.CLBLM_M_CX.CLBLM_BYP3 always +CLBLM_L.CLBLM_M_BX.CLBLM_BYP4 always +CLBLM_L.CLBLM_L_BX.CLBLM_BYP5 always +CLBLM_L.CLBLM_M_DX.CLBLM_BYP6 always +CLBLM_L.CLBLM_L_DX.CLBLM_BYP7 always +CLBLM_L.CLBLM_L_CLK.CLBLM_CLK0 always +CLBLM_L.CLBLM_M_CLK.CLBLM_CLK1 always +CLBLM_L.CLBLM_L_SR.CLBLM_CTRL0 always +CLBLM_L.CLBLM_M_SR.CLBLM_CTRL1 always +CLBLM_L.CLBLM_M_AI.CLBLM_FAN0 always +CLBLM_L.CLBLM_M_BI.CLBLM_FAN2 always +CLBLM_L.CLBLM_M_DI.CLBLM_FAN3 always +CLBLM_L.CLBLM_M_WE.CLBLM_FAN4 always +CLBLM_L.CLBLM_M_CI.CLBLM_FAN5 always +CLBLM_L.CLBLM_L_CE.CLBLM_FAN6 always +CLBLM_L.CLBLM_M_CE.CLBLM_FAN7 always +CLBLM_L.CLBLM_L_A3.CLBLM_IMUX0 always +CLBLM_L.CLBLM_L_A2.CLBLM_IMUX3 always +CLBLM_L.CLBLM_L_A6.CLBLM_IMUX5 always +CLBLM_L.CLBLM_L_A1.CLBLM_IMUX6 always +CLBLM_L.CLBLM_L_A5.CLBLM_IMUX9 always +CLBLM_L.CLBLM_L_A4.CLBLM_IMUX10 always +CLBLM_L.CLBLM_M_A3.CLBLM_IMUX1 always +CLBLM_L.CLBLM_M_A2.CLBLM_IMUX2 always +CLBLM_L.CLBLM_M_A6.CLBLM_IMUX4 always +CLBLM_L.CLBLM_M_A1.CLBLM_IMUX7 always +CLBLM_L.CLBLM_M_A5.CLBLM_IMUX8 always +CLBLM_L.CLBLM_M_A4.CLBLM_IMUX11 always +CLBLM_L.CLBLM_M_B6.CLBLM_IMUX12 always +CLBLM_L.CLBLM_M_B1.CLBLM_IMUX15 always +CLBLM_L.CLBLM_M_B3.CLBLM_IMUX17 always +CLBLM_L.CLBLM_M_B2.CLBLM_IMUX18 always +CLBLM_L.CLBLM_M_B5.CLBLM_IMUX24 always +CLBLM_L.CLBLM_M_B4.CLBLM_IMUX27 always +CLBLM_L.CLBLM_L_B6.CLBLM_IMUX13 always +CLBLM_L.CLBLM_L_B1.CLBLM_IMUX14 always +CLBLM_L.CLBLM_L_B3.CLBLM_IMUX16 always +CLBLM_L.CLBLM_L_B2.CLBLM_IMUX19 always +CLBLM_L.CLBLM_L_B5.CLBLM_IMUX25 always +CLBLM_L.CLBLM_L_B4.CLBLM_IMUX26 always +CLBLM_L.CLBLM_L_C2.CLBLM_IMUX20 always +CLBLM_L.CLBLM_L_C4.CLBLM_IMUX21 always +CLBLM_L.CLBLM_L_C3.CLBLM_IMUX23 always +CLBLM_L.CLBLM_L_C5.CLBLM_IMUX30 always +CLBLM_L.CLBLM_L_C1.CLBLM_IMUX33 always +CLBLM_L.CLBLM_L_C6.CLBLM_IMUX34 always +CLBLM_L.CLBLM_M_C3.CLBLM_IMUX22 always +CLBLM_L.CLBLM_M_C4.CLBLM_IMUX28 always +CLBLM_L.CLBLM_M_C2.CLBLM_IMUX29 always +CLBLM_L.CLBLM_M_C5.CLBLM_IMUX31 always +CLBLM_L.CLBLM_M_C1.CLBLM_IMUX32 always +CLBLM_L.CLBLM_M_C6.CLBLM_IMUX35 always +CLBLM_L.CLBLM_L_D2.CLBLM_IMUX36 always +CLBLM_L.CLBLM_L_D4.CLBLM_IMUX37 always +CLBLM_L.CLBLM_L_D3.CLBLM_IMUX39 always +CLBLM_L.CLBLM_L_D1.CLBLM_IMUX41 always +CLBLM_L.CLBLM_L_D6.CLBLM_IMUX42 always +CLBLM_L.CLBLM_L_D5.CLBLM_IMUX46 always +CLBLM_L.CLBLM_M_D3.CLBLM_IMUX38 always +CLBLM_L.CLBLM_M_D1.CLBLM_IMUX40 always +CLBLM_L.CLBLM_M_D6.CLBLM_IMUX43 always +CLBLM_L.CLBLM_M_D4.CLBLM_IMUX44 always +CLBLM_L.CLBLM_M_D2.CLBLM_IMUX45 always +CLBLM_L.CLBLM_M_D5.CLBLM_IMUX47 always +CLBLM_L.CLBLM_LOGIC_OUTS8.CLBLM_L_A always +CLBLM_L.CLBLM_L_AMUX.CLBLM_L_A hint +CLBLM_L.CLBLM_L_A.CLBLM_L_A1 hint +CLBLM_L.CLBLM_L_A.CLBLM_L_A2 hint +CLBLM_L.CLBLM_L_A.CLBLM_L_A3 hint +CLBLM_L.CLBLM_L_A.CLBLM_L_A4 hint +CLBLM_L.CLBLM_L_A.CLBLM_L_A5 hint +CLBLM_L.CLBLM_L_A.CLBLM_L_A6 hint +CLBLM_L.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always +CLBLM_L.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always +CLBLM_L.CLBLM_LOGIC_OUTS9.CLBLM_L_B always +CLBLM_L.CLBLM_L_BMUX.CLBLM_L_B hint +CLBLM_L.CLBLM_L_B.CLBLM_L_B1 hint +CLBLM_L.CLBLM_L_B.CLBLM_L_B2 hint +CLBLM_L.CLBLM_L_B.CLBLM_L_B3 hint +CLBLM_L.CLBLM_L_B.CLBLM_L_B4 hint +CLBLM_L.CLBLM_L_B.CLBLM_L_B5 hint +CLBLM_L.CLBLM_L_B.CLBLM_L_B6 hint +CLBLM_L.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always +CLBLM_L.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always +CLBLM_L.CLBLM_LOGIC_OUTS10.CLBLM_L_C always +CLBLM_L.CLBLM_L_CMUX.CLBLM_L_C hint +CLBLM_L.CLBLM_L_C.CLBLM_L_C1 hint +CLBLM_L.CLBLM_L_C.CLBLM_L_C2 hint +CLBLM_L.CLBLM_L_C.CLBLM_L_C3 hint +CLBLM_L.CLBLM_L_C.CLBLM_L_C4 hint +CLBLM_L.CLBLM_L_C.CLBLM_L_C5 hint +CLBLM_L.CLBLM_L_C.CLBLM_L_C6 hint +CLBLM_L.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always +CLBLM_L.CLBLM_L_COUT_N.CLBLM_L_COUT always +CLBLM_L.CLBLM_L_DMUX.CLBLM_L_COUT hint +CLBLM_L.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always +CLBLM_L.CLBLM_LOGIC_OUTS11.CLBLM_L_D always +CLBLM_L.CLBLM_L_DMUX.CLBLM_L_D hint +CLBLM_L.CLBLM_L_D.CLBLM_L_D1 hint +CLBLM_L.CLBLM_L_D.CLBLM_L_D2 hint +CLBLM_L.CLBLM_L_D.CLBLM_L_D3 hint +CLBLM_L.CLBLM_L_D.CLBLM_L_D4 hint +CLBLM_L.CLBLM_L_D.CLBLM_L_D5 hint +CLBLM_L.CLBLM_L_D.CLBLM_L_D6 hint +CLBLM_L.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always +CLBLM_L.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always +CLBLM_L.CLBLM_LOGIC_OUTS12.CLBLM_M_A always +CLBLM_L.CLBLM_M_AMUX.CLBLM_M_A hint +CLBLM_L.CLBLM_M_A.CLBLM_M_A1 hint +CLBLM_L.CLBLM_M_A.CLBLM_M_A2 hint +CLBLM_L.CLBLM_M_A.CLBLM_M_A3 hint +CLBLM_L.CLBLM_M_A.CLBLM_M_A4 hint +CLBLM_L.CLBLM_M_A.CLBLM_M_A5 hint +CLBLM_L.CLBLM_M_A.CLBLM_M_A6 hint +CLBLM_L.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always +CLBLM_L.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always +CLBLM_L.CLBLM_LOGIC_OUTS13.CLBLM_M_B always +CLBLM_L.CLBLM_M_BMUX.CLBLM_M_B hint +CLBLM_L.CLBLM_M_B.CLBLM_M_B1 hint +CLBLM_L.CLBLM_M_B.CLBLM_M_B2 hint +CLBLM_L.CLBLM_M_B.CLBLM_M_B3 hint +CLBLM_L.CLBLM_M_B.CLBLM_M_B4 hint +CLBLM_L.CLBLM_M_B.CLBLM_M_B5 hint +CLBLM_L.CLBLM_M_B.CLBLM_M_B6 hint +CLBLM_L.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always +CLBLM_L.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always +CLBLM_L.CLBLM_LOGIC_OUTS14.CLBLM_M_C always +CLBLM_L.CLBLM_M_CMUX.CLBLM_M_C hint +CLBLM_L.CLBLM_M_C.CLBLM_M_C1 hint +CLBLM_L.CLBLM_M_C.CLBLM_M_C2 hint +CLBLM_L.CLBLM_M_C.CLBLM_M_C3 hint +CLBLM_L.CLBLM_M_C.CLBLM_M_C4 hint +CLBLM_L.CLBLM_M_C.CLBLM_M_C5 hint +CLBLM_L.CLBLM_M_C.CLBLM_M_C6 hint +CLBLM_L.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always +CLBLM_L.CLBLM_M_COUT_N.CLBLM_M_COUT always +CLBLM_L.CLBLM_M_DMUX.CLBLM_M_COUT hint +CLBLM_L.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always +CLBLM_L.CLBLM_LOGIC_OUTS15.CLBLM_M_D always +CLBLM_L.CLBLM_M_DMUX.CLBLM_M_D hint +CLBLM_L.CLBLM_M_D.CLBLM_M_D1 hint +CLBLM_L.CLBLM_M_D.CLBLM_M_D2 hint +CLBLM_L.CLBLM_M_D.CLBLM_M_D3 hint +CLBLM_L.CLBLM_M_D.CLBLM_M_D4 hint +CLBLM_L.CLBLM_M_D.CLBLM_M_D5 hint +CLBLM_L.CLBLM_M_D.CLBLM_M_D6 hint +CLBLM_L.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always +CLBLM_L.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always diff --git a/kintex7/ppips_clblm_r.db b/kintex7/ppips_clblm_r.db new file mode 100644 index 0000000..4c3f3d5 --- /dev/null +++ b/kintex7/ppips_clblm_r.db @@ -0,0 +1,151 @@ +CLBLM_R.CLBLM_L_AX.CLBLM_BYP0 always +CLBLM_R.CLBLM_M_AX.CLBLM_BYP1 always +CLBLM_R.CLBLM_L_CX.CLBLM_BYP2 always +CLBLM_R.CLBLM_M_CX.CLBLM_BYP3 always +CLBLM_R.CLBLM_M_BX.CLBLM_BYP4 always +CLBLM_R.CLBLM_L_BX.CLBLM_BYP5 always +CLBLM_R.CLBLM_M_DX.CLBLM_BYP6 always +CLBLM_R.CLBLM_L_DX.CLBLM_BYP7 always +CLBLM_R.CLBLM_L_CLK.CLBLM_CLK0 always +CLBLM_R.CLBLM_M_CLK.CLBLM_CLK1 always +CLBLM_R.CLBLM_L_SR.CLBLM_CTRL0 always +CLBLM_R.CLBLM_M_SR.CLBLM_CTRL1 always +CLBLM_R.CLBLM_M_AI.CLBLM_FAN0 always +CLBLM_R.CLBLM_M_BI.CLBLM_FAN2 always +CLBLM_R.CLBLM_M_DI.CLBLM_FAN3 always +CLBLM_R.CLBLM_M_WE.CLBLM_FAN4 always +CLBLM_R.CLBLM_M_CI.CLBLM_FAN5 always +CLBLM_R.CLBLM_L_CE.CLBLM_FAN6 always +CLBLM_R.CLBLM_M_CE.CLBLM_FAN7 always +CLBLM_R.CLBLM_L_A3.CLBLM_IMUX0 always +CLBLM_R.CLBLM_L_A2.CLBLM_IMUX3 always +CLBLM_R.CLBLM_L_A6.CLBLM_IMUX5 always +CLBLM_R.CLBLM_L_A1.CLBLM_IMUX6 always +CLBLM_R.CLBLM_L_A5.CLBLM_IMUX9 always +CLBLM_R.CLBLM_L_A4.CLBLM_IMUX10 always +CLBLM_R.CLBLM_M_A3.CLBLM_IMUX1 always +CLBLM_R.CLBLM_M_A2.CLBLM_IMUX2 always +CLBLM_R.CLBLM_M_A6.CLBLM_IMUX4 always +CLBLM_R.CLBLM_M_A1.CLBLM_IMUX7 always +CLBLM_R.CLBLM_M_A5.CLBLM_IMUX8 always +CLBLM_R.CLBLM_M_A4.CLBLM_IMUX11 always +CLBLM_R.CLBLM_M_B6.CLBLM_IMUX12 always +CLBLM_R.CLBLM_M_B1.CLBLM_IMUX15 always +CLBLM_R.CLBLM_M_B3.CLBLM_IMUX17 always +CLBLM_R.CLBLM_M_B2.CLBLM_IMUX18 always +CLBLM_R.CLBLM_M_B5.CLBLM_IMUX24 always +CLBLM_R.CLBLM_M_B4.CLBLM_IMUX27 always +CLBLM_R.CLBLM_L_B6.CLBLM_IMUX13 always +CLBLM_R.CLBLM_L_B1.CLBLM_IMUX14 always +CLBLM_R.CLBLM_L_B3.CLBLM_IMUX16 always +CLBLM_R.CLBLM_L_B2.CLBLM_IMUX19 always +CLBLM_R.CLBLM_L_B5.CLBLM_IMUX25 always +CLBLM_R.CLBLM_L_B4.CLBLM_IMUX26 always +CLBLM_R.CLBLM_L_C2.CLBLM_IMUX20 always +CLBLM_R.CLBLM_L_C4.CLBLM_IMUX21 always +CLBLM_R.CLBLM_L_C3.CLBLM_IMUX23 always +CLBLM_R.CLBLM_L_C5.CLBLM_IMUX30 always +CLBLM_R.CLBLM_L_C1.CLBLM_IMUX33 always +CLBLM_R.CLBLM_L_C6.CLBLM_IMUX34 always +CLBLM_R.CLBLM_M_C3.CLBLM_IMUX22 always +CLBLM_R.CLBLM_M_C4.CLBLM_IMUX28 always +CLBLM_R.CLBLM_M_C2.CLBLM_IMUX29 always +CLBLM_R.CLBLM_M_C5.CLBLM_IMUX31 always +CLBLM_R.CLBLM_M_C1.CLBLM_IMUX32 always +CLBLM_R.CLBLM_M_C6.CLBLM_IMUX35 always +CLBLM_R.CLBLM_L_D2.CLBLM_IMUX36 always +CLBLM_R.CLBLM_L_D4.CLBLM_IMUX37 always +CLBLM_R.CLBLM_L_D3.CLBLM_IMUX39 always +CLBLM_R.CLBLM_L_D1.CLBLM_IMUX41 always +CLBLM_R.CLBLM_L_D6.CLBLM_IMUX42 always +CLBLM_R.CLBLM_L_D5.CLBLM_IMUX46 always +CLBLM_R.CLBLM_M_D3.CLBLM_IMUX38 always +CLBLM_R.CLBLM_M_D1.CLBLM_IMUX40 always +CLBLM_R.CLBLM_M_D6.CLBLM_IMUX43 always +CLBLM_R.CLBLM_M_D4.CLBLM_IMUX44 always +CLBLM_R.CLBLM_M_D2.CLBLM_IMUX45 always +CLBLM_R.CLBLM_M_D5.CLBLM_IMUX47 always +CLBLM_R.CLBLM_LOGIC_OUTS8.CLBLM_L_A always +CLBLM_R.CLBLM_L_AMUX.CLBLM_L_A hint +CLBLM_R.CLBLM_L_A.CLBLM_L_A1 hint +CLBLM_R.CLBLM_L_A.CLBLM_L_A2 hint +CLBLM_R.CLBLM_L_A.CLBLM_L_A3 hint +CLBLM_R.CLBLM_L_A.CLBLM_L_A4 hint +CLBLM_R.CLBLM_L_A.CLBLM_L_A5 hint +CLBLM_R.CLBLM_L_A.CLBLM_L_A6 hint +CLBLM_R.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always +CLBLM_R.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always +CLBLM_R.CLBLM_LOGIC_OUTS9.CLBLM_L_B always +CLBLM_R.CLBLM_L_BMUX.CLBLM_L_B hint +CLBLM_R.CLBLM_L_B.CLBLM_L_B1 hint +CLBLM_R.CLBLM_L_B.CLBLM_L_B2 hint +CLBLM_R.CLBLM_L_B.CLBLM_L_B3 hint +CLBLM_R.CLBLM_L_B.CLBLM_L_B4 hint +CLBLM_R.CLBLM_L_B.CLBLM_L_B5 hint +CLBLM_R.CLBLM_L_B.CLBLM_L_B6 hint +CLBLM_R.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always +CLBLM_R.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always +CLBLM_R.CLBLM_LOGIC_OUTS10.CLBLM_L_C always +CLBLM_R.CLBLM_L_CMUX.CLBLM_L_C hint +CLBLM_R.CLBLM_L_C.CLBLM_L_C1 hint +CLBLM_R.CLBLM_L_C.CLBLM_L_C2 hint +CLBLM_R.CLBLM_L_C.CLBLM_L_C3 hint +CLBLM_R.CLBLM_L_C.CLBLM_L_C4 hint +CLBLM_R.CLBLM_L_C.CLBLM_L_C5 hint +CLBLM_R.CLBLM_L_C.CLBLM_L_C6 hint +CLBLM_R.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always +CLBLM_R.CLBLM_L_COUT_N.CLBLM_L_COUT always +CLBLM_R.CLBLM_L_DMUX.CLBLM_L_COUT hint +CLBLM_R.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always +CLBLM_R.CLBLM_LOGIC_OUTS11.CLBLM_L_D always +CLBLM_R.CLBLM_L_DMUX.CLBLM_L_D hint +CLBLM_R.CLBLM_L_D.CLBLM_L_D1 hint +CLBLM_R.CLBLM_L_D.CLBLM_L_D2 hint +CLBLM_R.CLBLM_L_D.CLBLM_L_D3 hint +CLBLM_R.CLBLM_L_D.CLBLM_L_D4 hint +CLBLM_R.CLBLM_L_D.CLBLM_L_D5 hint +CLBLM_R.CLBLM_L_D.CLBLM_L_D6 hint +CLBLM_R.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always +CLBLM_R.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always +CLBLM_R.CLBLM_LOGIC_OUTS12.CLBLM_M_A always +CLBLM_R.CLBLM_M_AMUX.CLBLM_M_A hint +CLBLM_R.CLBLM_M_A.CLBLM_M_A1 hint +CLBLM_R.CLBLM_M_A.CLBLM_M_A2 hint +CLBLM_R.CLBLM_M_A.CLBLM_M_A3 hint +CLBLM_R.CLBLM_M_A.CLBLM_M_A4 hint +CLBLM_R.CLBLM_M_A.CLBLM_M_A5 hint +CLBLM_R.CLBLM_M_A.CLBLM_M_A6 hint +CLBLM_R.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always +CLBLM_R.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always +CLBLM_R.CLBLM_LOGIC_OUTS13.CLBLM_M_B always +CLBLM_R.CLBLM_M_BMUX.CLBLM_M_B hint +CLBLM_R.CLBLM_M_B.CLBLM_M_B1 hint +CLBLM_R.CLBLM_M_B.CLBLM_M_B2 hint +CLBLM_R.CLBLM_M_B.CLBLM_M_B3 hint +CLBLM_R.CLBLM_M_B.CLBLM_M_B4 hint +CLBLM_R.CLBLM_M_B.CLBLM_M_B5 hint +CLBLM_R.CLBLM_M_B.CLBLM_M_B6 hint +CLBLM_R.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always +CLBLM_R.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always +CLBLM_R.CLBLM_LOGIC_OUTS14.CLBLM_M_C always +CLBLM_R.CLBLM_M_CMUX.CLBLM_M_C hint +CLBLM_R.CLBLM_M_C.CLBLM_M_C1 hint +CLBLM_R.CLBLM_M_C.CLBLM_M_C2 hint +CLBLM_R.CLBLM_M_C.CLBLM_M_C3 hint +CLBLM_R.CLBLM_M_C.CLBLM_M_C4 hint +CLBLM_R.CLBLM_M_C.CLBLM_M_C5 hint +CLBLM_R.CLBLM_M_C.CLBLM_M_C6 hint +CLBLM_R.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always +CLBLM_R.CLBLM_M_COUT_N.CLBLM_M_COUT always +CLBLM_R.CLBLM_M_DMUX.CLBLM_M_COUT hint +CLBLM_R.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always +CLBLM_R.CLBLM_LOGIC_OUTS15.CLBLM_M_D always +CLBLM_R.CLBLM_M_DMUX.CLBLM_M_D hint +CLBLM_R.CLBLM_M_D.CLBLM_M_D1 hint +CLBLM_R.CLBLM_M_D.CLBLM_M_D2 hint +CLBLM_R.CLBLM_M_D.CLBLM_M_D3 hint +CLBLM_R.CLBLM_M_D.CLBLM_M_D4 hint +CLBLM_R.CLBLM_M_D.CLBLM_M_D5 hint +CLBLM_R.CLBLM_M_D.CLBLM_M_D6 hint +CLBLM_R.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always +CLBLM_R.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always diff --git a/kintex7/ppips_hclk_l.db b/kintex7/ppips_hclk_l.db new file mode 100644 index 0000000..6959965 --- /dev/null +++ b/kintex7/ppips_hclk_l.db @@ -0,0 +1,8 @@ +HCLK.HCLK_CK_INOUT_L0.HCLK_CK_BUFHCLK8 always +HCLK.HCLK_CK_INOUT_L1.HCLK_CK_BUFHCLK9 always +HCLK.HCLK_CK_INOUT_L2.HCLK_CK_BUFHCLK10 always +HCLK.HCLK_CK_INOUT_L3.HCLK_CK_BUFHCLK11 always +HCLK.HCLK_CK_INOUT_L4.HCLK_CK_BUFRCLK0 always +HCLK.HCLK_CK_INOUT_L5.HCLK_CK_BUFRCLK1 always +HCLK.HCLK_CK_INOUT_L6.HCLK_CK_BUFRCLK2 always +HCLK.HCLK_CK_INOUT_L7.HCLK_CK_BUFRCLK3 always diff --git a/kintex7/ppips_hclk_r.db b/kintex7/ppips_hclk_r.db new file mode 100644 index 0000000..45231f3 --- /dev/null +++ b/kintex7/ppips_hclk_r.db @@ -0,0 +1,8 @@ +HCLK.HCLK_CK_INOUT_R0.HCLK_CK_BUFHCLK0 always +HCLK.HCLK_CK_INOUT_R1.HCLK_CK_BUFHCLK1 always +HCLK.HCLK_CK_INOUT_R2.HCLK_CK_BUFHCLK2 always +HCLK.HCLK_CK_INOUT_R3.HCLK_CK_BUFHCLK3 always +HCLK.HCLK_CK_INOUT_R4.HCLK_CK_BUFHCLK4 always +HCLK.HCLK_CK_INOUT_R5.HCLK_CK_BUFHCLK5 always +HCLK.HCLK_CK_INOUT_R6.HCLK_CK_BUFHCLK6 always +HCLK.HCLK_CK_INOUT_R7.HCLK_CK_BUFHCLK7 always diff --git a/kintex7/ppips_int_l.db b/kintex7/ppips_int_l.db new file mode 100644 index 0000000..816dd86 --- /dev/null +++ b/kintex7/ppips_int_l.db @@ -0,0 +1,44 @@ +INT_L.BYP_BOUNCE0.BYP_ALT0 always +INT_L.BYP_BOUNCE1.BYP_ALT1 always +INT_L.BYP_BOUNCE2.BYP_ALT2 always +INT_L.BYP_BOUNCE3.BYP_ALT3 always +INT_L.BYP_BOUNCE4.BYP_ALT4 always +INT_L.BYP_BOUNCE5.BYP_ALT5 always +INT_L.BYP_BOUNCE6.BYP_ALT6 always +INT_L.BYP_BOUNCE7.BYP_ALT7 always +INT_L.BYP_L0.BYP_ALT0 always +INT_L.BYP_L1.BYP_ALT1 always +INT_L.BYP_L2.BYP_ALT2 always +INT_L.BYP_L3.BYP_ALT3 always +INT_L.BYP_L4.BYP_ALT4 always +INT_L.BYP_L5.BYP_ALT5 always +INT_L.BYP_L6.BYP_ALT6 always +INT_L.BYP_L7.BYP_ALT7 always +INT_L.FAN_BOUNCE0.FAN_ALT0 always +INT_L.FAN_BOUNCE1.FAN_ALT1 always +INT_L.FAN_BOUNCE2.FAN_ALT2 always +INT_L.FAN_BOUNCE3.FAN_ALT3 always +INT_L.FAN_BOUNCE4.FAN_ALT4 always +INT_L.FAN_BOUNCE5.FAN_ALT5 always +INT_L.FAN_BOUNCE6.FAN_ALT6 always +INT_L.FAN_BOUNCE7.FAN_ALT7 always +INT_L.FAN_L0.FAN_ALT0 always +INT_L.FAN_L1.FAN_ALT1 always +INT_L.FAN_L2.FAN_ALT2 always +INT_L.FAN_L3.FAN_ALT3 always +INT_L.FAN_L4.FAN_ALT4 always +INT_L.FAN_L5.FAN_ALT5 always +INT_L.FAN_L6.FAN_ALT6 always +INT_L.FAN_L7.FAN_ALT7 always +INT_L.GCLK_L_B10_WEST.GCLK_L_B10 always +INT_L.GCLK_L_B10_EAST.GCLK_L_B10 always +INT_L.GCLK_L_B11_WEST.GCLK_L_B11 always +INT_L.GCLK_L_B11_EAST.GCLK_L_B11 always +INT_L.GCLK_L_B6_WEST.GCLK_L_B6 always +INT_L.GCLK_L_B6_EAST.GCLK_L_B6 always +INT_L.GCLK_L_B7_WEST.GCLK_L_B7 always +INT_L.GCLK_L_B7_EAST.GCLK_L_B7 always +INT_L.GCLK_L_B8_WEST.GCLK_L_B8 always +INT_L.GCLK_L_B8_EAST.GCLK_L_B8 always +INT_L.GCLK_L_B9_WEST.GCLK_L_B9 always +INT_L.GCLK_L_B9_EAST.GCLK_L_B9 always diff --git a/kintex7/ppips_int_r.db b/kintex7/ppips_int_r.db new file mode 100644 index 0000000..3af54a9 --- /dev/null +++ b/kintex7/ppips_int_r.db @@ -0,0 +1,44 @@ +INT_R.BYP_BOUNCE0.BYP_ALT0 always +INT_R.BYP_BOUNCE1.BYP_ALT1 always +INT_R.BYP_BOUNCE2.BYP_ALT2 always +INT_R.BYP_BOUNCE3.BYP_ALT3 always +INT_R.BYP_BOUNCE4.BYP_ALT4 always +INT_R.BYP_BOUNCE5.BYP_ALT5 always +INT_R.BYP_BOUNCE6.BYP_ALT6 always +INT_R.BYP_BOUNCE7.BYP_ALT7 always +INT_R.BYP0.BYP_ALT0 always +INT_R.BYP1.BYP_ALT1 always +INT_R.BYP2.BYP_ALT2 always +INT_R.BYP3.BYP_ALT3 always +INT_R.BYP4.BYP_ALT4 always +INT_R.BYP5.BYP_ALT5 always +INT_R.BYP6.BYP_ALT6 always +INT_R.BYP7.BYP_ALT7 always +INT_R.FAN_BOUNCE0.FAN_ALT0 always +INT_R.FAN_BOUNCE1.FAN_ALT1 always +INT_R.FAN_BOUNCE2.FAN_ALT2 always +INT_R.FAN_BOUNCE3.FAN_ALT3 always +INT_R.FAN_BOUNCE4.FAN_ALT4 always +INT_R.FAN_BOUNCE5.FAN_ALT5 always +INT_R.FAN_BOUNCE6.FAN_ALT6 always +INT_R.FAN_BOUNCE7.FAN_ALT7 always +INT_R.FAN0.FAN_ALT0 always +INT_R.FAN1.FAN_ALT1 always +INT_R.FAN2.FAN_ALT2 always +INT_R.FAN3.FAN_ALT3 always +INT_R.FAN4.FAN_ALT4 always +INT_R.FAN5.FAN_ALT5 always +INT_R.FAN6.FAN_ALT6 always +INT_R.FAN7.FAN_ALT7 always +INT_R.GCLK_B0_EAST.GCLK_B0 always +INT_R.GCLK_B0_WEST.GCLK_B0 always +INT_R.GCLK_B1_EAST.GCLK_B1 always +INT_R.GCLK_B1_WEST.GCLK_B1 always +INT_R.GCLK_B2_EAST.GCLK_B2 always +INT_R.GCLK_B2_WEST.GCLK_B2 always +INT_R.GCLK_B3_EAST.GCLK_B3 always +INT_R.GCLK_B3_WEST.GCLK_B3 always +INT_R.GCLK_B4_EAST.GCLK_B4 always +INT_R.GCLK_B4_WEST.GCLK_B4 always +INT_R.GCLK_B5_EAST.GCLK_B5 always +INT_R.GCLK_B5_WEST.GCLK_B5 always diff --git a/kintex7/segbits_bram_l.block_ram.db b/kintex7/segbits_bram_l.block_ram.db new file mode 100644 index 0000000..e69de29 diff --git a/kintex7/segbits_bram_l.db b/kintex7/segbits_bram_l.db new file mode 100644 index 0000000..f7b08c0 --- /dev/null +++ b/kintex7/segbits_bram_l.db @@ -0,0 +1,192 @@ +BRAM_L.RAMB18_Y0.INIT_A[0] 27_73 +BRAM_L.RAMB18_Y0.INIT_A[10] 27_129 +BRAM_L.RAMB18_Y0.INIT_A[11] 27_113 +BRAM_L.RAMB18_Y0.INIT_A[12] 27_97 +BRAM_L.RAMB18_Y0.INIT_A[1] 27_65 +BRAM_L.RAMB18_Y0.INIT_A[13] 27_81 +BRAM_L.RAMB18_Y0.INIT_A[14] 27_49 +BRAM_L.RAMB18_Y0.INIT_A[15] 27_33 +BRAM_L.RAMB18_Y0.INIT_A[16] 27_17 +BRAM_L.RAMB18_Y0.INIT_A[17] 27_01 +BRAM_L.RAMB18_Y0.INIT_A[2] 27_137 +BRAM_L.RAMB18_Y0.INIT_A[3] 27_121 +BRAM_L.RAMB18_Y0.INIT_A[4] 27_105 +BRAM_L.RAMB18_Y0.INIT_A[5] 27_89 +BRAM_L.RAMB18_Y0.INIT_A[6] 27_57 +BRAM_L.RAMB18_Y0.INIT_A[7] 27_41 +BRAM_L.RAMB18_Y0.INIT_A[8] 27_25 +BRAM_L.RAMB18_Y0.INIT_A[9] 27_09 +BRAM_L.RAMB18_Y0.INIT_B[0] 27_79 +BRAM_L.RAMB18_Y0.INIT_B[10] 27_135 +BRAM_L.RAMB18_Y0.INIT_B[11] 27_119 +BRAM_L.RAMB18_Y0.INIT_B[12] 27_103 +BRAM_L.RAMB18_Y0.INIT_B[1] 27_71 +BRAM_L.RAMB18_Y0.INIT_B[13] 27_87 +BRAM_L.RAMB18_Y0.INIT_B[14] 27_55 +BRAM_L.RAMB18_Y0.INIT_B[15] 27_39 +BRAM_L.RAMB18_Y0.INIT_B[16] 27_23 +BRAM_L.RAMB18_Y0.INIT_B[17] 27_07 +BRAM_L.RAMB18_Y0.INIT_B[2] 27_143 +BRAM_L.RAMB18_Y0.INIT_B[3] 27_127 +BRAM_L.RAMB18_Y0.INIT_B[4] 27_111 +BRAM_L.RAMB18_Y0.INIT_B[5] 27_95 +BRAM_L.RAMB18_Y0.INIT_B[6] 27_63 +BRAM_L.RAMB18_Y0.INIT_B[7] 27_47 +BRAM_L.RAMB18_Y0.INIT_B[8] 27_31 +BRAM_L.RAMB18_Y0.INIT_B[9] 27_15 +BRAM_L.RAMB18_Y0.READ_WIDTH_A_B0 27_35 +BRAM_L.RAMB18_Y0.READ_WIDTH_A_B1 27_36 +BRAM_L.RAMB18_Y0.READ_WIDTH_A_B2 27_37 +BRAM_L.RAMB18_Y0.READ_WIDTH_B_B0 27_43 +BRAM_L.RAMB18_Y0.READ_WIDTH_B_B1 27_44 +BRAM_L.RAMB18_Y0.READ_WIDTH_B_B2 27_45 +BRAM_L.RAMB18_Y0.SRVAL_A[0] 27_74 +BRAM_L.RAMB18_Y0.SRVAL_A[10] 27_130 +BRAM_L.RAMB18_Y0.SRVAL_A[11] 27_114 +BRAM_L.RAMB18_Y0.SRVAL_A[12] 27_98 +BRAM_L.RAMB18_Y0.SRVAL_A[1] 27_66 +BRAM_L.RAMB18_Y0.SRVAL_A[13] 27_82 +BRAM_L.RAMB18_Y0.SRVAL_A[14] 27_50 +BRAM_L.RAMB18_Y0.SRVAL_A[15] 27_34 +BRAM_L.RAMB18_Y0.SRVAL_A[16] 27_18 +BRAM_L.RAMB18_Y0.SRVAL_A[17] 27_02 +BRAM_L.RAMB18_Y0.SRVAL_A[2] 27_138 +BRAM_L.RAMB18_Y0.SRVAL_A[3] 27_122 +BRAM_L.RAMB18_Y0.SRVAL_A[4] 27_106 +BRAM_L.RAMB18_Y0.SRVAL_A[5] 27_90 +BRAM_L.RAMB18_Y0.SRVAL_A[6] 27_58 +BRAM_L.RAMB18_Y0.SRVAL_A[7] 27_42 +BRAM_L.RAMB18_Y0.SRVAL_A[8] 27_26 +BRAM_L.RAMB18_Y0.SRVAL_A[9] 27_10 +BRAM_L.RAMB18_Y0.SRVAL_B[0] 27_78 +BRAM_L.RAMB18_Y0.SRVAL_B[10] 27_134 +BRAM_L.RAMB18_Y0.SRVAL_B[11] 27_118 +BRAM_L.RAMB18_Y0.SRVAL_B[12] 27_102 +BRAM_L.RAMB18_Y0.SRVAL_B[1] 27_70 +BRAM_L.RAMB18_Y0.SRVAL_B[13] 27_86 +BRAM_L.RAMB18_Y0.SRVAL_B[14] 27_54 +BRAM_L.RAMB18_Y0.SRVAL_B[15] 27_38 +BRAM_L.RAMB18_Y0.SRVAL_B[16] 27_22 +BRAM_L.RAMB18_Y0.SRVAL_B[17] 27_06 +BRAM_L.RAMB18_Y0.SRVAL_B[2] 27_142 +BRAM_L.RAMB18_Y0.SRVAL_B[3] 27_126 +BRAM_L.RAMB18_Y0.SRVAL_B[4] 27_110 +BRAM_L.RAMB18_Y0.SRVAL_B[5] 27_94 +BRAM_L.RAMB18_Y0.SRVAL_B[6] 27_62 +BRAM_L.RAMB18_Y0.SRVAL_B[7] 27_46 +BRAM_L.RAMB18_Y0.SRVAL_B[8] 27_30 +BRAM_L.RAMB18_Y0.SRVAL_B[9] 27_14 +BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64 +BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56 +BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68 +BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B0 27_51 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B1 27_52 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B2 27_53 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B0 27_59 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B1 27_60 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B2 27_61 +BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107 +BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109 +BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112 +BRAM_L.RAMB18_Y0.ZINV_ENBWREN 27_115 +BRAM_L.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116 +BRAM_L.RAMB18_Y0.ZINV_RSTRAMB 27_117 +BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120 +BRAM_L.RAMB18_Y0.ZINV_RSTREGB 27_123 +BRAM_L.RAMB18_Y1.INIT_A[0] 27_249 +BRAM_L.RAMB18_Y1.INIT_A[10] 27_305 +BRAM_L.RAMB18_Y1.INIT_A[11] 27_289 +BRAM_L.RAMB18_Y1.INIT_A[12] 27_273 +BRAM_L.RAMB18_Y1.INIT_A[1] 27_241 +BRAM_L.RAMB18_Y1.INIT_A[13] 27_257 +BRAM_L.RAMB18_Y1.INIT_A[14] 27_225 +BRAM_L.RAMB18_Y1.INIT_A[15] 27_209 +BRAM_L.RAMB18_Y1.INIT_A[16] 27_193 +BRAM_L.RAMB18_Y1.INIT_A[17] 27_177 +BRAM_L.RAMB18_Y1.INIT_A[2] 27_313 +BRAM_L.RAMB18_Y1.INIT_A[3] 27_297 +BRAM_L.RAMB18_Y1.INIT_A[4] 27_281 +BRAM_L.RAMB18_Y1.INIT_A[5] 27_265 +BRAM_L.RAMB18_Y1.INIT_A[6] 27_233 +BRAM_L.RAMB18_Y1.INIT_A[7] 27_217 +BRAM_L.RAMB18_Y1.INIT_A[8] 27_201 +BRAM_L.RAMB18_Y1.INIT_A[9] 27_185 +BRAM_L.RAMB18_Y1.INIT_B[0] 27_255 +BRAM_L.RAMB18_Y1.INIT_B[10] 27_311 +BRAM_L.RAMB18_Y1.INIT_B[11] 27_295 +BRAM_L.RAMB18_Y1.INIT_B[12] 27_279 +BRAM_L.RAMB18_Y1.INIT_B[1] 27_247 +BRAM_L.RAMB18_Y1.INIT_B[13] 27_263 +BRAM_L.RAMB18_Y1.INIT_B[14] 27_231 +BRAM_L.RAMB18_Y1.INIT_B[15] 27_215 +BRAM_L.RAMB18_Y1.INIT_B[16] 27_199 +BRAM_L.RAMB18_Y1.INIT_B[17] 27_183 +BRAM_L.RAMB18_Y1.INIT_B[2] 27_319 +BRAM_L.RAMB18_Y1.INIT_B[3] 27_303 +BRAM_L.RAMB18_Y1.INIT_B[4] 27_287 +BRAM_L.RAMB18_Y1.INIT_B[5] 27_271 +BRAM_L.RAMB18_Y1.INIT_B[6] 27_239 +BRAM_L.RAMB18_Y1.INIT_B[7] 27_223 +BRAM_L.RAMB18_Y1.INIT_B[8] 27_207 +BRAM_L.RAMB18_Y1.INIT_B[9] 27_191 +BRAM_L.RAMB18_Y1.READ_WIDTH_A_B0 27_285 +BRAM_L.RAMB18_Y1.READ_WIDTH_A_B1 27_284 +BRAM_L.RAMB18_Y1.READ_WIDTH_A_B2 27_283 +BRAM_L.RAMB18_Y1.READ_WIDTH_B_B0 27_277 +BRAM_L.RAMB18_Y1.READ_WIDTH_B_B1 27_276 +BRAM_L.RAMB18_Y1.READ_WIDTH_B_B2 27_275 +BRAM_L.RAMB18_Y1.SRVAL_A[0] 27_250 +BRAM_L.RAMB18_Y1.SRVAL_A[10] 27_306 +BRAM_L.RAMB18_Y1.SRVAL_A[11] 27_290 +BRAM_L.RAMB18_Y1.SRVAL_A[12] 27_274 +BRAM_L.RAMB18_Y1.SRVAL_A[1] 27_242 +BRAM_L.RAMB18_Y1.SRVAL_A[13] 27_258 +BRAM_L.RAMB18_Y1.SRVAL_A[14] 27_226 +BRAM_L.RAMB18_Y1.SRVAL_A[15] 27_210 +BRAM_L.RAMB18_Y1.SRVAL_A[16] 27_194 +BRAM_L.RAMB18_Y1.SRVAL_A[17] 27_178 +BRAM_L.RAMB18_Y1.SRVAL_A[2] 27_314 +BRAM_L.RAMB18_Y1.SRVAL_A[3] 27_298 +BRAM_L.RAMB18_Y1.SRVAL_A[4] 27_282 +BRAM_L.RAMB18_Y1.SRVAL_A[5] 27_266 +BRAM_L.RAMB18_Y1.SRVAL_A[6] 27_234 +BRAM_L.RAMB18_Y1.SRVAL_A[7] 27_218 +BRAM_L.RAMB18_Y1.SRVAL_A[8] 27_202 +BRAM_L.RAMB18_Y1.SRVAL_A[9] 27_186 +BRAM_L.RAMB18_Y1.SRVAL_B[0] 27_254 +BRAM_L.RAMB18_Y1.SRVAL_B[10] 27_310 +BRAM_L.RAMB18_Y1.SRVAL_B[11] 27_294 +BRAM_L.RAMB18_Y1.SRVAL_B[12] 27_278 +BRAM_L.RAMB18_Y1.SRVAL_B[1] 27_246 +BRAM_L.RAMB18_Y1.SRVAL_B[13] 27_262 +BRAM_L.RAMB18_Y1.SRVAL_B[14] 27_230 +BRAM_L.RAMB18_Y1.SRVAL_B[15] 27_214 +BRAM_L.RAMB18_Y1.SRVAL_B[16] 27_198 +BRAM_L.RAMB18_Y1.SRVAL_B[17] 27_182 +BRAM_L.RAMB18_Y1.SRVAL_B[2] 27_318 +BRAM_L.RAMB18_Y1.SRVAL_B[3] 27_302 +BRAM_L.RAMB18_Y1.SRVAL_B[4] 27_286 +BRAM_L.RAMB18_Y1.SRVAL_B[5] 27_270 +BRAM_L.RAMB18_Y1.SRVAL_B[6] 27_238 +BRAM_L.RAMB18_Y1.SRVAL_B[7] 27_222 +BRAM_L.RAMB18_Y1.SRVAL_B[8] 27_206 +BRAM_L.RAMB18_Y1.SRVAL_B[9] 27_190 +BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256 +BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264 +BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252 +BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B0 27_269 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B1 27_268 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B2 27_267 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B0 27_261 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B1 27_260 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B2 27_259 +BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213 +BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211 +BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208 +BRAM_L.RAMB18_Y1.ZINV_ENBWREN 27_205 +BRAM_L.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204 +BRAM_L.RAMB18_Y1.ZINV_RSTRAMB 27_203 +BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200 +BRAM_L.RAMB18_Y1.ZINV_RSTREGB 27_197 diff --git a/kintex7/segbits_bram_r.block_ram.db b/kintex7/segbits_bram_r.block_ram.db new file mode 100644 index 0000000..e69de29 diff --git a/kintex7/segbits_bram_r.db b/kintex7/segbits_bram_r.db new file mode 100644 index 0000000..60fe5c5 --- /dev/null +++ b/kintex7/segbits_bram_r.db @@ -0,0 +1,192 @@ +BRAM_R.RAMB18_Y0.INIT_A[0] 27_73 +BRAM_R.RAMB18_Y0.INIT_A[10] 27_129 +BRAM_R.RAMB18_Y0.INIT_A[11] 27_113 +BRAM_R.RAMB18_Y0.INIT_A[12] 27_97 +BRAM_R.RAMB18_Y0.INIT_A[1] 27_65 +BRAM_R.RAMB18_Y0.INIT_A[13] 27_81 +BRAM_R.RAMB18_Y0.INIT_A[14] 27_49 +BRAM_R.RAMB18_Y0.INIT_A[15] 27_33 +BRAM_R.RAMB18_Y0.INIT_A[16] 27_17 +BRAM_R.RAMB18_Y0.INIT_A[17] 27_01 +BRAM_R.RAMB18_Y0.INIT_A[2] 27_137 +BRAM_R.RAMB18_Y0.INIT_A[3] 27_121 +BRAM_R.RAMB18_Y0.INIT_A[4] 27_105 +BRAM_R.RAMB18_Y0.INIT_A[5] 27_89 +BRAM_R.RAMB18_Y0.INIT_A[6] 27_57 +BRAM_R.RAMB18_Y0.INIT_A[7] 27_41 +BRAM_R.RAMB18_Y0.INIT_A[8] 27_25 +BRAM_R.RAMB18_Y0.INIT_A[9] 27_09 +BRAM_R.RAMB18_Y0.INIT_B[0] 27_79 +BRAM_R.RAMB18_Y0.INIT_B[10] 27_135 +BRAM_R.RAMB18_Y0.INIT_B[11] 27_119 +BRAM_R.RAMB18_Y0.INIT_B[12] 27_103 +BRAM_R.RAMB18_Y0.INIT_B[1] 27_71 +BRAM_R.RAMB18_Y0.INIT_B[13] 27_87 +BRAM_R.RAMB18_Y0.INIT_B[14] 27_55 +BRAM_R.RAMB18_Y0.INIT_B[15] 27_39 +BRAM_R.RAMB18_Y0.INIT_B[16] 27_23 +BRAM_R.RAMB18_Y0.INIT_B[17] 27_07 +BRAM_R.RAMB18_Y0.INIT_B[2] 27_143 +BRAM_R.RAMB18_Y0.INIT_B[3] 27_127 +BRAM_R.RAMB18_Y0.INIT_B[4] 27_111 +BRAM_R.RAMB18_Y0.INIT_B[5] 27_95 +BRAM_R.RAMB18_Y0.INIT_B[6] 27_63 +BRAM_R.RAMB18_Y0.INIT_B[7] 27_47 +BRAM_R.RAMB18_Y0.INIT_B[8] 27_31 +BRAM_R.RAMB18_Y0.INIT_B[9] 27_15 +BRAM_R.RAMB18_Y0.READ_WIDTH_A_B0 27_35 +BRAM_R.RAMB18_Y0.READ_WIDTH_A_B1 27_36 +BRAM_R.RAMB18_Y0.READ_WIDTH_A_B2 27_37 +BRAM_R.RAMB18_Y0.READ_WIDTH_B_B0 27_43 +BRAM_R.RAMB18_Y0.READ_WIDTH_B_B1 27_44 +BRAM_R.RAMB18_Y0.READ_WIDTH_B_B2 27_45 +BRAM_R.RAMB18_Y0.SRVAL_A[0] 27_74 +BRAM_R.RAMB18_Y0.SRVAL_A[10] 27_130 +BRAM_R.RAMB18_Y0.SRVAL_A[11] 27_114 +BRAM_R.RAMB18_Y0.SRVAL_A[12] 27_98 +BRAM_R.RAMB18_Y0.SRVAL_A[1] 27_66 +BRAM_R.RAMB18_Y0.SRVAL_A[13] 27_82 +BRAM_R.RAMB18_Y0.SRVAL_A[14] 27_50 +BRAM_R.RAMB18_Y0.SRVAL_A[15] 27_34 +BRAM_R.RAMB18_Y0.SRVAL_A[16] 27_18 +BRAM_R.RAMB18_Y0.SRVAL_A[17] 27_02 +BRAM_R.RAMB18_Y0.SRVAL_A[2] 27_138 +BRAM_R.RAMB18_Y0.SRVAL_A[3] 27_122 +BRAM_R.RAMB18_Y0.SRVAL_A[4] 27_106 +BRAM_R.RAMB18_Y0.SRVAL_A[5] 27_90 +BRAM_R.RAMB18_Y0.SRVAL_A[6] 27_58 +BRAM_R.RAMB18_Y0.SRVAL_A[7] 27_42 +BRAM_R.RAMB18_Y0.SRVAL_A[8] 27_26 +BRAM_R.RAMB18_Y0.SRVAL_A[9] 27_10 +BRAM_R.RAMB18_Y0.SRVAL_B[0] 27_78 +BRAM_R.RAMB18_Y0.SRVAL_B[10] 27_134 +BRAM_R.RAMB18_Y0.SRVAL_B[11] 27_118 +BRAM_R.RAMB18_Y0.SRVAL_B[12] 27_102 +BRAM_R.RAMB18_Y0.SRVAL_B[1] 27_70 +BRAM_R.RAMB18_Y0.SRVAL_B[13] 27_86 +BRAM_R.RAMB18_Y0.SRVAL_B[14] 27_54 +BRAM_R.RAMB18_Y0.SRVAL_B[15] 27_38 +BRAM_R.RAMB18_Y0.SRVAL_B[16] 27_22 +BRAM_R.RAMB18_Y0.SRVAL_B[17] 27_06 +BRAM_R.RAMB18_Y0.SRVAL_B[2] 27_142 +BRAM_R.RAMB18_Y0.SRVAL_B[3] 27_126 +BRAM_R.RAMB18_Y0.SRVAL_B[4] 27_110 +BRAM_R.RAMB18_Y0.SRVAL_B[5] 27_94 +BRAM_R.RAMB18_Y0.SRVAL_B[6] 27_62 +BRAM_R.RAMB18_Y0.SRVAL_B[7] 27_46 +BRAM_R.RAMB18_Y0.SRVAL_B[8] 27_30 +BRAM_R.RAMB18_Y0.SRVAL_B[9] 27_14 +BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64 +BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56 +BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68 +BRAM_R.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B0 27_51 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B1 27_52 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B2 27_53 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B0 27_59 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B1 27_60 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B2 27_61 +BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107 +BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109 +BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112 +BRAM_R.RAMB18_Y0.ZINV_ENBWREN 27_115 +BRAM_R.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116 +BRAM_R.RAMB18_Y0.ZINV_RSTRAMB 27_117 +BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120 +BRAM_R.RAMB18_Y0.ZINV_RSTREGB 27_123 +BRAM_R.RAMB18_Y1.INIT_A[0] 27_249 +BRAM_R.RAMB18_Y1.INIT_A[10] 27_305 +BRAM_R.RAMB18_Y1.INIT_A[11] 27_289 +BRAM_R.RAMB18_Y1.INIT_A[12] 27_273 +BRAM_R.RAMB18_Y1.INIT_A[1] 27_241 +BRAM_R.RAMB18_Y1.INIT_A[13] 27_257 +BRAM_R.RAMB18_Y1.INIT_A[14] 27_225 +BRAM_R.RAMB18_Y1.INIT_A[15] 27_209 +BRAM_R.RAMB18_Y1.INIT_A[16] 27_193 +BRAM_R.RAMB18_Y1.INIT_A[17] 27_177 +BRAM_R.RAMB18_Y1.INIT_A[2] 27_313 +BRAM_R.RAMB18_Y1.INIT_A[3] 27_297 +BRAM_R.RAMB18_Y1.INIT_A[4] 27_281 +BRAM_R.RAMB18_Y1.INIT_A[5] 27_265 +BRAM_R.RAMB18_Y1.INIT_A[6] 27_233 +BRAM_R.RAMB18_Y1.INIT_A[7] 27_217 +BRAM_R.RAMB18_Y1.INIT_A[8] 27_201 +BRAM_R.RAMB18_Y1.INIT_A[9] 27_185 +BRAM_R.RAMB18_Y1.INIT_B[0] 27_255 +BRAM_R.RAMB18_Y1.INIT_B[10] 27_311 +BRAM_R.RAMB18_Y1.INIT_B[11] 27_295 +BRAM_R.RAMB18_Y1.INIT_B[12] 27_279 +BRAM_R.RAMB18_Y1.INIT_B[1] 27_247 +BRAM_R.RAMB18_Y1.INIT_B[13] 27_263 +BRAM_R.RAMB18_Y1.INIT_B[14] 27_231 +BRAM_R.RAMB18_Y1.INIT_B[15] 27_215 +BRAM_R.RAMB18_Y1.INIT_B[16] 27_199 +BRAM_R.RAMB18_Y1.INIT_B[17] 27_183 +BRAM_R.RAMB18_Y1.INIT_B[2] 27_319 +BRAM_R.RAMB18_Y1.INIT_B[3] 27_303 +BRAM_R.RAMB18_Y1.INIT_B[4] 27_287 +BRAM_R.RAMB18_Y1.INIT_B[5] 27_271 +BRAM_R.RAMB18_Y1.INIT_B[6] 27_239 +BRAM_R.RAMB18_Y1.INIT_B[7] 27_223 +BRAM_R.RAMB18_Y1.INIT_B[8] 27_207 +BRAM_R.RAMB18_Y1.INIT_B[9] 27_191 +BRAM_R.RAMB18_Y1.READ_WIDTH_A_B0 27_285 +BRAM_R.RAMB18_Y1.READ_WIDTH_A_B1 27_284 +BRAM_R.RAMB18_Y1.READ_WIDTH_A_B2 27_283 +BRAM_R.RAMB18_Y1.READ_WIDTH_B_B0 27_277 +BRAM_R.RAMB18_Y1.READ_WIDTH_B_B1 27_276 +BRAM_R.RAMB18_Y1.READ_WIDTH_B_B2 27_275 +BRAM_R.RAMB18_Y1.SRVAL_A[0] 27_250 +BRAM_R.RAMB18_Y1.SRVAL_A[10] 27_306 +BRAM_R.RAMB18_Y1.SRVAL_A[11] 27_290 +BRAM_R.RAMB18_Y1.SRVAL_A[12] 27_274 +BRAM_R.RAMB18_Y1.SRVAL_A[1] 27_242 +BRAM_R.RAMB18_Y1.SRVAL_A[13] 27_258 +BRAM_R.RAMB18_Y1.SRVAL_A[14] 27_226 +BRAM_R.RAMB18_Y1.SRVAL_A[15] 27_210 +BRAM_R.RAMB18_Y1.SRVAL_A[16] 27_194 +BRAM_R.RAMB18_Y1.SRVAL_A[17] 27_178 +BRAM_R.RAMB18_Y1.SRVAL_A[2] 27_314 +BRAM_R.RAMB18_Y1.SRVAL_A[3] 27_298 +BRAM_R.RAMB18_Y1.SRVAL_A[4] 27_282 +BRAM_R.RAMB18_Y1.SRVAL_A[5] 27_266 +BRAM_R.RAMB18_Y1.SRVAL_A[6] 27_234 +BRAM_R.RAMB18_Y1.SRVAL_A[7] 27_218 +BRAM_R.RAMB18_Y1.SRVAL_A[8] 27_202 +BRAM_R.RAMB18_Y1.SRVAL_A[9] 27_186 +BRAM_R.RAMB18_Y1.SRVAL_B[0] 27_254 +BRAM_R.RAMB18_Y1.SRVAL_B[10] 27_310 +BRAM_R.RAMB18_Y1.SRVAL_B[11] 27_294 +BRAM_R.RAMB18_Y1.SRVAL_B[12] 27_278 +BRAM_R.RAMB18_Y1.SRVAL_B[1] 27_246 +BRAM_R.RAMB18_Y1.SRVAL_B[13] 27_262 +BRAM_R.RAMB18_Y1.SRVAL_B[14] 27_230 +BRAM_R.RAMB18_Y1.SRVAL_B[15] 27_214 +BRAM_R.RAMB18_Y1.SRVAL_B[16] 27_198 +BRAM_R.RAMB18_Y1.SRVAL_B[17] 27_182 +BRAM_R.RAMB18_Y1.SRVAL_B[2] 27_318 +BRAM_R.RAMB18_Y1.SRVAL_B[3] 27_302 +BRAM_R.RAMB18_Y1.SRVAL_B[4] 27_286 +BRAM_R.RAMB18_Y1.SRVAL_B[5] 27_270 +BRAM_R.RAMB18_Y1.SRVAL_B[6] 27_238 +BRAM_R.RAMB18_Y1.SRVAL_B[7] 27_222 +BRAM_R.RAMB18_Y1.SRVAL_B[8] 27_206 +BRAM_R.RAMB18_Y1.SRVAL_B[9] 27_190 +BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256 +BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264 +BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252 +BRAM_R.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B0 27_269 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B1 27_268 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B2 27_267 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B0 27_261 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B1 27_260 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B2 27_259 +BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213 +BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211 +BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208 +BRAM_R.RAMB18_Y1.ZINV_ENBWREN 27_205 +BRAM_R.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204 +BRAM_R.RAMB18_Y1.ZINV_RSTRAMB 27_203 +BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200 +BRAM_R.RAMB18_Y1.ZINV_RSTREGB 27_197 diff --git a/kintex7/segbits_clbll_l.db b/kintex7/segbits_clbll_l.db index c76b538..5524c1e 100644 --- a/kintex7/segbits_clbll_l.db +++ b/kintex7/segbits_clbll_l.db @@ -1,7 +1,15 @@ CLBLL_L.SLICEL_X0.A5FF.ZINI 31_06 CLBLL_L.SLICEL_X0.A5FF.ZRST 01_07 +CLBLL_L.SLICEL_X0.A5FFMUX.IN_A 30_09 +CLBLL_L.SLICEL_X0.A5FFMUX.IN_B 30_10 CLBLL_L.SLICEL_X0.AFF.ZINI 31_03 CLBLL_L.SLICEL_X0.AFF.ZRST 30_12 +CLBLL_L.SLICEL_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01 +CLBLL_L.SLICEL_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02 +CLBLL_L.SLICEL_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01 +CLBLL_L.SLICEL_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03 +CLBLL_L.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03 +CLBLL_L.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02 CLBLL_L.SLICEL_X0.ALUT.INIT[00] 32_15 CLBLL_L.SLICEL_X0.ALUT.INIT[01] 33_15 CLBLL_L.SLICEL_X0.ALUT.INIT[02] 32_14 @@ -66,10 +74,26 @@ CLBLL_L.SLICEL_X0.ALUT.INIT[60] 35_01 CLBLL_L.SLICEL_X0.ALUT.INIT[61] 34_01 CLBLL_L.SLICEL_X0.ALUT.INIT[62] 35_00 CLBLL_L.SLICEL_X0.ALUT.INIT[63] 34_00 +CLBLL_L.SLICEL_X0.ALUT.RAM 31_16 +CLBLL_L.SLICEL_X0.ALUT.SMALL 00_04 +CLBLL_L.SLICEL_X0.ALUT.SRL 30_16 +CLBLL_L.SLICEL_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07 +CLBLL_L.SLICEL_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08 +CLBLL_L.SLICEL_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07 +CLBLL_L.SLICEL_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11 +CLBLL_L.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08 CLBLL_L.SLICEL_X0.B5FF.ZINI 31_22 CLBLL_L.SLICEL_X0.B5FF.ZRST 01_19 +CLBLL_L.SLICEL_X0.B5FFMUX.IN_A 30_19 +CLBLL_L.SLICEL_X0.B5FFMUX.IN_B 30_18 CLBLL_L.SLICEL_X0.BFF.ZINI 31_28 CLBLL_L.SLICEL_X0.BFF.ZRST 30_30 +CLBLL_L.SLICEL_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26 +CLBLL_L.SLICEL_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27 +CLBLL_L.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27 +CLBLL_L.SLICEL_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27 +CLBLL_L.SLICEL_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24 +CLBLL_L.SLICEL_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25 CLBLL_L.SLICEL_X0.BLUT.INIT[00] 32_31 CLBLL_L.SLICEL_X0.BLUT.INIT[01] 33_31 CLBLL_L.SLICEL_X0.BLUT.INIT[02] 32_30 @@ -134,15 +158,34 @@ CLBLL_L.SLICEL_X0.BLUT.INIT[60] 35_17 CLBLL_L.SLICEL_X0.BLUT.INIT[61] 34_17 CLBLL_L.SLICEL_X0.BLUT.INIT[62] 35_16 CLBLL_L.SLICEL_X0.BLUT.INIT[63] 34_16 +CLBLL_L.SLICEL_X0.BLUT.RAM 31_17 +CLBLL_L.SLICEL_X0.BLUT.SMALL 00_24 +CLBLL_L.SLICEL_X0.BLUT.SRL 30_17 +CLBLL_L.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23 +CLBLL_L.SLICEL_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22 +CLBLL_L.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23 +CLBLL_L.SLICEL_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22 +CLBLL_L.SLICEL_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21 CLBLL_L.SLICEL_X0.C5FF.ZINI 31_41 CLBLL_L.SLICEL_X0.C5FF.ZRST 01_47 +CLBLL_L.SLICEL_X0.C5FFMUX.IN_A 31_45 +CLBLL_L.SLICEL_X0.C5FFMUX.IN_B 30_39 +CLBLL_L.SLICEL_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03 CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15 +CLBLL_L.SLICEL_X0.CARRY4.BCY0 !30_24 !30_25 !30_27 01_15 30_26 30_30 31_28 CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15 +CLBLL_L.SLICEL_X0.CARRY4.CCY0 !30_35 !30_37 !30_38 30_33 30_36 30_48 31_33 CLBLL_L.SLICEL_X0.CARRY4.CCY0 30_48 CLBLL_L.SLICEL_X0.CARRY4.DCY0 30_49 CLBLL_L.SLICEL_X0.CEUSEDMUX 01_39 CLBLL_L.SLICEL_X0.CFF.ZINI 31_33 CLBLL_L.SLICEL_X0.CFF.ZRST 30_33 +CLBLL_L.SLICEL_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36 +CLBLL_L.SLICEL_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37 +CLBLL_L.SLICEL_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36 +CLBLL_L.SLICEL_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38 +CLBLL_L.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38 +CLBLL_L.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37 CLBLL_L.SLICEL_X0.CLKINV 01_51 CLBLL_L.SLICEL_X0.CLUT.INIT[00] 32_47 CLBLL_L.SLICEL_X0.CLUT.INIT[01] 33_47 @@ -208,10 +251,25 @@ CLBLL_L.SLICEL_X0.CLUT.INIT[60] 35_33 CLBLL_L.SLICEL_X0.CLUT.INIT[61] 34_33 CLBLL_L.SLICEL_X0.CLUT.INIT[62] 35_32 CLBLL_L.SLICEL_X0.CLUT.INIT[63] 34_32 +CLBLL_L.SLICEL_X0.CLUT.RAM 31_46 +CLBLL_L.SLICEL_X0.CLUT.SMALL 00_28 +CLBLL_L.SLICEL_X0.CLUT.SRL 30_46 +CLBLL_L.SLICEL_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43 +CLBLL_L.SLICEL_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44 +CLBLL_L.SLICEL_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43 +CLBLL_L.SLICEL_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45 +CLBLL_L.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44 CLBLL_L.SLICEL_X0.D5FF.ZINI 31_51 CLBLL_L.SLICEL_X0.D5FF.ZRST 01_55 +CLBLL_L.SLICEL_X0.D5FFMUX.IN_A 30_55 +CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 30_54 CLBLL_L.SLICEL_X0.DFF.ZINI 31_58 CLBLL_L.SLICEL_X0.DFF.ZRST 30_50 +CLBLL_L.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62 +CLBLL_L.SLICEL_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61 +CLBLL_L.SLICEL_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62 +CLBLL_L.SLICEL_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59 +CLBLL_L.SLICEL_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60 CLBLL_L.SLICEL_X0.DLUT.INIT[00] 32_63 CLBLL_L.SLICEL_X0.DLUT.INIT[01] 33_63 CLBLL_L.SLICEL_X0.DLUT.INIT[02] 32_62 @@ -276,16 +334,34 @@ CLBLL_L.SLICEL_X0.DLUT.INIT[60] 35_49 CLBLL_L.SLICEL_X0.DLUT.INIT[61] 34_49 CLBLL_L.SLICEL_X0.DLUT.INIT[62] 35_48 CLBLL_L.SLICEL_X0.DLUT.INIT[63] 34_48 +CLBLL_L.SLICEL_X0.DLUT.RAM 31_47 +CLBLL_L.SLICEL_X0.DLUT.SMALL 01_59 +CLBLL_L.SLICEL_X0.DLUT.SRL 30_47 +CLBLL_L.SLICEL_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52 +CLBLL_L.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57 +CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56 +CLBLL_L.SLICEL_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51 CLBLL_L.SLICEL_X0.FFSYNC 00_48 CLBLL_L.SLICEL_X0.LATCH 30_32 CLBLL_L.SLICEL_X0.PRECYINIT.1 00_12 CLBLL_L.SLICEL_X0.PRECYINIT.AX 30_14 CLBLL_L.SLICEL_X0.PRECYINIT.CIN 30_13 CLBLL_L.SLICEL_X0.SRUSEDMUX 01_35 +CLBLL_L.SLICEL_X0.WA7USED 00_40 +CLBLL_L.SLICEL_X0.WA8USED 01_27 +CLBLL_L.SLICEL_X0.WEMUX.CE 01_23 CLBLL_L.SLICEL_X1.A5FF.ZINI 31_05 CLBLL_L.SLICEL_X1.A5FF.ZRST 01_03 +CLBLL_L.SLICEL_X1.A5FFMUX.IN_A 31_08 +CLBLL_L.SLICEL_X1.A5FFMUX.IN_B 31_11 CLBLL_L.SLICEL_X1.AFF.ZINI 31_04 CLBLL_L.SLICEL_X1.AFF.ZRST 31_15 +CLBLL_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01 +CLBLL_L.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02 +CLBLL_L.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01 +CLBLL_L.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00 +CLBLL_L.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04 +CLBLL_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02 CLBLL_L.SLICEL_X1.ALUT.INIT[00] 26_15 CLBLL_L.SLICEL_X1.ALUT.INIT[01] 27_15 CLBLL_L.SLICEL_X1.ALUT.INIT[02] 26_14 @@ -350,10 +426,23 @@ CLBLL_L.SLICEL_X1.ALUT.INIT[60] 29_01 CLBLL_L.SLICEL_X1.ALUT.INIT[61] 28_01 CLBLL_L.SLICEL_X1.ALUT.INIT[62] 29_00 CLBLL_L.SLICEL_X1.ALUT.INIT[63] 28_00 +CLBLL_L.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05 +CLBLL_L.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10 +CLBLL_L.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10 +CLBLL_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10 +CLBLL_L.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07 CLBLL_L.SLICEL_X1.B5FF.ZINI 31_23 CLBLL_L.SLICEL_X1.B5FF.ZRST 00_16 +CLBLL_L.SLICEL_X1.B5FFMUX.IN_A 31_19 +CLBLL_L.SLICEL_X1.B5FFMUX.IN_B 31_18 CLBLL_L.SLICEL_X1.BFF.ZINI 31_29 CLBLL_L.SLICEL_X1.BFF.ZRST 31_30 +CLBLL_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27 +CLBLL_L.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26 +CLBLL_L.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27 +CLBLL_L.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25 +CLBLL_L.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24 +CLBLL_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26 CLBLL_L.SLICEL_X1.BLUT.INIT[00] 26_31 CLBLL_L.SLICEL_X1.BLUT.INIT[01] 27_31 CLBLL_L.SLICEL_X1.BLUT.INIT[02] 26_30 @@ -418,15 +507,31 @@ CLBLL_L.SLICEL_X1.BLUT.INIT[60] 29_17 CLBLL_L.SLICEL_X1.BLUT.INIT[61] 28_17 CLBLL_L.SLICEL_X1.BLUT.INIT[62] 29_16 CLBLL_L.SLICEL_X1.BLUT.INIT[63] 28_16 +CLBLL_L.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29 +CLBLL_L.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21 +CLBLL_L.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21 +CLBLL_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21 +CLBLL_L.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28 CLBLL_L.SLICEL_X1.C5FF.ZINI 31_42 CLBLL_L.SLICEL_X1.C5FF.ZRST 00_44 +CLBLL_L.SLICEL_X1.C5FFMUX.IN_A 31_44 +CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39 +CLBLL_L.SLICEL_X1.CARRY4.ACY0 !30_04 !31_00 !31_02 31_01 31_04 31_14 31_15 CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14 +CLBLL_L.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30 CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08 +CLBLL_L.SLICEL_X1.CARRY4.CCY0 !31_35 !31_36 !31_37 30_34 31_34 31_38 31_48 CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48 CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49 CLBLL_L.SLICEL_X1.CEUSEDMUX 00_36 CLBLL_L.SLICEL_X1.CFF.ZINI 31_34 CLBLL_L.SLICEL_X1.CFF.ZRST 30_34 +CLBLL_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38 +CLBLL_L.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37 +CLBLL_L.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38 +CLBLL_L.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36 +CLBLL_L.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36 +CLBLL_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37 CLBLL_L.SLICEL_X1.CLKINV 00_52 CLBLL_L.SLICEL_X1.CLUT.INIT[00] 26_47 CLBLL_L.SLICEL_X1.CLUT.INIT[01] 27_47 @@ -492,10 +597,22 @@ CLBLL_L.SLICEL_X1.CLUT.INIT[60] 29_33 CLBLL_L.SLICEL_X1.CLUT.INIT[61] 28_33 CLBLL_L.SLICEL_X1.CLUT.INIT[62] 29_32 CLBLL_L.SLICEL_X1.CLUT.INIT[63] 28_32 +CLBLL_L.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41 +CLBLL_L.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40 +CLBLL_L.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40 +CLBLL_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43 +CLBLL_L.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42 CLBLL_L.SLICEL_X1.D5FF.ZINI 31_52 CLBLL_L.SLICEL_X1.D5FF.ZRST 00_56 +CLBLL_L.SLICEL_X1.D5FFMUX.IN_A 31_55 +CLBLL_L.SLICEL_X1.D5FFMUX.IN_B 31_54 CLBLL_L.SLICEL_X1.DFF.ZINI 31_59 CLBLL_L.SLICEL_X1.DFF.ZRST 31_50 +CLBLL_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62 +CLBLL_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61 +CLBLL_L.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60 +CLBLL_L.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60 +CLBLL_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62 CLBLL_L.SLICEL_X1.DLUT.INIT[00] 26_63 CLBLL_L.SLICEL_X1.DLUT.INIT[01] 27_63 CLBLL_L.SLICEL_X1.DLUT.INIT[02] 26_62 @@ -560,6 +677,10 @@ CLBLL_L.SLICEL_X1.DLUT.INIT[60] 29_49 CLBLL_L.SLICEL_X1.DLUT.INIT[61] 28_49 CLBLL_L.SLICEL_X1.DLUT.INIT[62] 29_48 CLBLL_L.SLICEL_X1.DLUT.INIT[63] 28_48 +CLBLL_L.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57 +CLBLL_L.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53 +CLBLL_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57 +CLBLL_L.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53 CLBLL_L.SLICEL_X1.FFSYNC 01_31 CLBLL_L.SLICEL_X1.LATCH 31_32 CLBLL_L.SLICEL_X1.PRECYINIT.1 01_11 diff --git a/kintex7/segbits_clbll_r.db b/kintex7/segbits_clbll_r.db index d0567e5..170cf46 100644 --- a/kintex7/segbits_clbll_r.db +++ b/kintex7/segbits_clbll_r.db @@ -1,7 +1,15 @@ CLBLL_R.SLICEL_X0.A5FF.ZINI 31_06 CLBLL_R.SLICEL_X0.A5FF.ZRST 01_07 +CLBLL_R.SLICEL_X0.A5FFMUX.IN_A 30_09 +CLBLL_R.SLICEL_X0.A5FFMUX.IN_B 30_10 CLBLL_R.SLICEL_X0.AFF.ZINI 31_03 CLBLL_R.SLICEL_X0.AFF.ZRST 30_12 +CLBLL_R.SLICEL_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01 +CLBLL_R.SLICEL_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02 +CLBLL_R.SLICEL_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01 +CLBLL_R.SLICEL_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03 +CLBLL_R.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03 +CLBLL_R.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02 CLBLL_R.SLICEL_X0.ALUT.INIT[00] 32_15 CLBLL_R.SLICEL_X0.ALUT.INIT[01] 33_15 CLBLL_R.SLICEL_X0.ALUT.INIT[02] 32_14 @@ -66,10 +74,26 @@ CLBLL_R.SLICEL_X0.ALUT.INIT[60] 35_01 CLBLL_R.SLICEL_X0.ALUT.INIT[61] 34_01 CLBLL_R.SLICEL_X0.ALUT.INIT[62] 35_00 CLBLL_R.SLICEL_X0.ALUT.INIT[63] 34_00 +CLBLL_R.SLICEL_X0.ALUT.RAM 31_16 +CLBLL_R.SLICEL_X0.ALUT.SMALL 00_04 +CLBLL_R.SLICEL_X0.ALUT.SRL 30_16 +CLBLL_R.SLICEL_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07 +CLBLL_R.SLICEL_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08 +CLBLL_R.SLICEL_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07 +CLBLL_R.SLICEL_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11 +CLBLL_R.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08 CLBLL_R.SLICEL_X0.B5FF.ZINI 31_22 CLBLL_R.SLICEL_X0.B5FF.ZRST 01_19 +CLBLL_R.SLICEL_X0.B5FFMUX.IN_A 30_19 +CLBLL_R.SLICEL_X0.B5FFMUX.IN_B 30_18 CLBLL_R.SLICEL_X0.BFF.ZINI 31_28 CLBLL_R.SLICEL_X0.BFF.ZRST 30_30 +CLBLL_R.SLICEL_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26 +CLBLL_R.SLICEL_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27 +CLBLL_R.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27 +CLBLL_R.SLICEL_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27 +CLBLL_R.SLICEL_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24 +CLBLL_R.SLICEL_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25 CLBLL_R.SLICEL_X0.BLUT.INIT[00] 32_31 CLBLL_R.SLICEL_X0.BLUT.INIT[01] 33_31 CLBLL_R.SLICEL_X0.BLUT.INIT[02] 32_30 @@ -134,15 +158,34 @@ CLBLL_R.SLICEL_X0.BLUT.INIT[60] 35_17 CLBLL_R.SLICEL_X0.BLUT.INIT[61] 34_17 CLBLL_R.SLICEL_X0.BLUT.INIT[62] 35_16 CLBLL_R.SLICEL_X0.BLUT.INIT[63] 34_16 +CLBLL_R.SLICEL_X0.BLUT.RAM 31_17 +CLBLL_R.SLICEL_X0.BLUT.SMALL 00_24 +CLBLL_R.SLICEL_X0.BLUT.SRL 30_17 +CLBLL_R.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23 +CLBLL_R.SLICEL_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22 +CLBLL_R.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23 +CLBLL_R.SLICEL_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22 +CLBLL_R.SLICEL_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21 CLBLL_R.SLICEL_X0.C5FF.ZINI 31_41 CLBLL_R.SLICEL_X0.C5FF.ZRST 01_47 +CLBLL_R.SLICEL_X0.C5FFMUX.IN_A 31_45 +CLBLL_R.SLICEL_X0.C5FFMUX.IN_B 30_39 +CLBLL_R.SLICEL_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03 CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15 +CLBLL_R.SLICEL_X0.CARRY4.BCY0 !30_24 !30_25 !30_27 01_15 30_26 30_30 31_28 CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15 +CLBLL_R.SLICEL_X0.CARRY4.CCY0 !30_35 !30_37 !30_38 30_33 30_36 30_48 31_33 CLBLL_R.SLICEL_X0.CARRY4.CCY0 30_48 CLBLL_R.SLICEL_X0.CARRY4.DCY0 30_49 CLBLL_R.SLICEL_X0.CEUSEDMUX 01_39 CLBLL_R.SLICEL_X0.CFF.ZINI 31_33 CLBLL_R.SLICEL_X0.CFF.ZRST 30_33 +CLBLL_R.SLICEL_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36 +CLBLL_R.SLICEL_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37 +CLBLL_R.SLICEL_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36 +CLBLL_R.SLICEL_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38 +CLBLL_R.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38 +CLBLL_R.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37 CLBLL_R.SLICEL_X0.CLKINV 01_51 CLBLL_R.SLICEL_X0.CLUT.INIT[00] 32_47 CLBLL_R.SLICEL_X0.CLUT.INIT[01] 33_47 @@ -208,10 +251,25 @@ CLBLL_R.SLICEL_X0.CLUT.INIT[60] 35_33 CLBLL_R.SLICEL_X0.CLUT.INIT[61] 34_33 CLBLL_R.SLICEL_X0.CLUT.INIT[62] 35_32 CLBLL_R.SLICEL_X0.CLUT.INIT[63] 34_32 +CLBLL_R.SLICEL_X0.CLUT.RAM 31_46 +CLBLL_R.SLICEL_X0.CLUT.SMALL 00_28 +CLBLL_R.SLICEL_X0.CLUT.SRL 30_46 +CLBLL_R.SLICEL_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43 +CLBLL_R.SLICEL_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44 +CLBLL_R.SLICEL_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43 +CLBLL_R.SLICEL_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45 +CLBLL_R.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44 CLBLL_R.SLICEL_X0.D5FF.ZINI 31_51 CLBLL_R.SLICEL_X0.D5FF.ZRST 01_55 +CLBLL_R.SLICEL_X0.D5FFMUX.IN_A 30_55 +CLBLL_R.SLICEL_X0.D5FFMUX.IN_B 30_54 CLBLL_R.SLICEL_X0.DFF.ZINI 31_58 CLBLL_R.SLICEL_X0.DFF.ZRST 30_50 +CLBLL_R.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62 +CLBLL_R.SLICEL_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61 +CLBLL_R.SLICEL_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62 +CLBLL_R.SLICEL_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59 +CLBLL_R.SLICEL_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60 CLBLL_R.SLICEL_X0.DLUT.INIT[00] 32_63 CLBLL_R.SLICEL_X0.DLUT.INIT[01] 33_63 CLBLL_R.SLICEL_X0.DLUT.INIT[02] 32_62 @@ -276,16 +334,34 @@ CLBLL_R.SLICEL_X0.DLUT.INIT[60] 35_49 CLBLL_R.SLICEL_X0.DLUT.INIT[61] 34_49 CLBLL_R.SLICEL_X0.DLUT.INIT[62] 35_48 CLBLL_R.SLICEL_X0.DLUT.INIT[63] 34_48 +CLBLL_R.SLICEL_X0.DLUT.RAM 31_47 +CLBLL_R.SLICEL_X0.DLUT.SMALL 01_59 +CLBLL_R.SLICEL_X0.DLUT.SRL 30_47 +CLBLL_R.SLICEL_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52 +CLBLL_R.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57 +CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56 +CLBLL_R.SLICEL_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51 CLBLL_R.SLICEL_X0.FFSYNC 00_48 CLBLL_R.SLICEL_X0.LATCH 30_32 CLBLL_R.SLICEL_X0.PRECYINIT.1 00_12 CLBLL_R.SLICEL_X0.PRECYINIT.AX 30_14 CLBLL_R.SLICEL_X0.PRECYINIT.CIN 30_13 CLBLL_R.SLICEL_X0.SRUSEDMUX 01_35 +CLBLL_R.SLICEL_X0.WA7USED 00_40 +CLBLL_R.SLICEL_X0.WA8USED 01_27 +CLBLL_R.SLICEL_X0.WEMUX.CE 01_23 CLBLL_R.SLICEL_X1.A5FF.ZINI 31_05 CLBLL_R.SLICEL_X1.A5FF.ZRST 01_03 +CLBLL_R.SLICEL_X1.A5FFMUX.IN_A 31_08 +CLBLL_R.SLICEL_X1.A5FFMUX.IN_B 31_11 CLBLL_R.SLICEL_X1.AFF.ZINI 31_04 CLBLL_R.SLICEL_X1.AFF.ZRST 31_15 +CLBLL_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01 +CLBLL_R.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02 +CLBLL_R.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01 +CLBLL_R.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00 +CLBLL_R.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04 +CLBLL_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02 CLBLL_R.SLICEL_X1.ALUT.INIT[00] 26_15 CLBLL_R.SLICEL_X1.ALUT.INIT[01] 27_15 CLBLL_R.SLICEL_X1.ALUT.INIT[02] 26_14 @@ -350,10 +426,23 @@ CLBLL_R.SLICEL_X1.ALUT.INIT[60] 29_01 CLBLL_R.SLICEL_X1.ALUT.INIT[61] 28_01 CLBLL_R.SLICEL_X1.ALUT.INIT[62] 29_00 CLBLL_R.SLICEL_X1.ALUT.INIT[63] 28_00 +CLBLL_R.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05 +CLBLL_R.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10 +CLBLL_R.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10 +CLBLL_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10 +CLBLL_R.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07 CLBLL_R.SLICEL_X1.B5FF.ZINI 31_23 CLBLL_R.SLICEL_X1.B5FF.ZRST 00_16 +CLBLL_R.SLICEL_X1.B5FFMUX.IN_A 31_19 +CLBLL_R.SLICEL_X1.B5FFMUX.IN_B 31_18 CLBLL_R.SLICEL_X1.BFF.ZINI 31_29 CLBLL_R.SLICEL_X1.BFF.ZRST 31_30 +CLBLL_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27 +CLBLL_R.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26 +CLBLL_R.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27 +CLBLL_R.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25 +CLBLL_R.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24 +CLBLL_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26 CLBLL_R.SLICEL_X1.BLUT.INIT[00] 26_31 CLBLL_R.SLICEL_X1.BLUT.INIT[01] 27_31 CLBLL_R.SLICEL_X1.BLUT.INIT[02] 26_30 @@ -418,15 +507,31 @@ CLBLL_R.SLICEL_X1.BLUT.INIT[60] 29_17 CLBLL_R.SLICEL_X1.BLUT.INIT[61] 28_17 CLBLL_R.SLICEL_X1.BLUT.INIT[62] 29_16 CLBLL_R.SLICEL_X1.BLUT.INIT[63] 28_16 +CLBLL_R.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29 +CLBLL_R.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21 +CLBLL_R.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21 +CLBLL_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21 +CLBLL_R.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28 CLBLL_R.SLICEL_X1.C5FF.ZINI 31_42 CLBLL_R.SLICEL_X1.C5FF.ZRST 00_44 +CLBLL_R.SLICEL_X1.C5FFMUX.IN_A 31_44 +CLBLL_R.SLICEL_X1.C5FFMUX.IN_B 31_39 +CLBLL_R.SLICEL_X1.CARRY4.ACY0 !30_04 !31_00 !31_02 31_01 31_04 31_14 31_15 CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14 +CLBLL_R.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30 CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08 +CLBLL_R.SLICEL_X1.CARRY4.CCY0 !31_35 !31_36 !31_37 30_34 31_34 31_38 31_48 CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48 CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49 CLBLL_R.SLICEL_X1.CEUSEDMUX 00_36 CLBLL_R.SLICEL_X1.CFF.ZINI 31_34 CLBLL_R.SLICEL_X1.CFF.ZRST 30_34 +CLBLL_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38 +CLBLL_R.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37 +CLBLL_R.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38 +CLBLL_R.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36 +CLBLL_R.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36 +CLBLL_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37 CLBLL_R.SLICEL_X1.CLKINV 00_52 CLBLL_R.SLICEL_X1.CLUT.INIT[00] 26_47 CLBLL_R.SLICEL_X1.CLUT.INIT[01] 27_47 @@ -492,10 +597,22 @@ CLBLL_R.SLICEL_X1.CLUT.INIT[60] 29_33 CLBLL_R.SLICEL_X1.CLUT.INIT[61] 28_33 CLBLL_R.SLICEL_X1.CLUT.INIT[62] 29_32 CLBLL_R.SLICEL_X1.CLUT.INIT[63] 28_32 +CLBLL_R.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41 +CLBLL_R.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40 +CLBLL_R.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40 +CLBLL_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43 +CLBLL_R.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42 CLBLL_R.SLICEL_X1.D5FF.ZINI 31_52 CLBLL_R.SLICEL_X1.D5FF.ZRST 00_56 +CLBLL_R.SLICEL_X1.D5FFMUX.IN_A 31_55 +CLBLL_R.SLICEL_X1.D5FFMUX.IN_B 31_54 CLBLL_R.SLICEL_X1.DFF.ZINI 31_59 CLBLL_R.SLICEL_X1.DFF.ZRST 31_50 +CLBLL_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62 +CLBLL_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61 +CLBLL_R.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60 +CLBLL_R.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60 +CLBLL_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62 CLBLL_R.SLICEL_X1.DLUT.INIT[00] 26_63 CLBLL_R.SLICEL_X1.DLUT.INIT[01] 27_63 CLBLL_R.SLICEL_X1.DLUT.INIT[02] 26_62 @@ -560,6 +677,10 @@ CLBLL_R.SLICEL_X1.DLUT.INIT[60] 29_49 CLBLL_R.SLICEL_X1.DLUT.INIT[61] 28_49 CLBLL_R.SLICEL_X1.DLUT.INIT[62] 29_48 CLBLL_R.SLICEL_X1.DLUT.INIT[63] 28_48 +CLBLL_R.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57 +CLBLL_R.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53 +CLBLL_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57 +CLBLL_R.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53 CLBLL_R.SLICEL_X1.FFSYNC 01_31 CLBLL_R.SLICEL_X1.LATCH 31_32 CLBLL_R.SLICEL_X1.PRECYINIT.1 01_11 diff --git a/kintex7/segbits_clblm_l.db b/kintex7/segbits_clblm_l.db index 9d9d4e7..ce2228c 100644 --- a/kintex7/segbits_clblm_l.db +++ b/kintex7/segbits_clblm_l.db @@ -1,7 +1,15 @@ CLBLM_L.SLICEL_X1.A5FF.ZINI 31_05 CLBLM_L.SLICEL_X1.A5FF.ZRST 01_03 +CLBLM_L.SLICEL_X1.A5FFMUX.IN_A 31_08 +CLBLM_L.SLICEL_X1.A5FFMUX.IN_B 31_11 CLBLM_L.SLICEL_X1.AFF.ZINI 31_04 CLBLM_L.SLICEL_X1.AFF.ZRST 31_15 +CLBLM_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01 +CLBLM_L.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02 +CLBLM_L.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01 +CLBLM_L.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00 +CLBLM_L.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04 +CLBLM_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02 CLBLM_L.SLICEL_X1.ALUT.INIT[00] 26_15 CLBLM_L.SLICEL_X1.ALUT.INIT[01] 27_15 CLBLM_L.SLICEL_X1.ALUT.INIT[02] 26_14 @@ -66,10 +74,23 @@ CLBLM_L.SLICEL_X1.ALUT.INIT[60] 29_01 CLBLM_L.SLICEL_X1.ALUT.INIT[61] 28_01 CLBLM_L.SLICEL_X1.ALUT.INIT[62] 29_00 CLBLM_L.SLICEL_X1.ALUT.INIT[63] 28_00 +CLBLM_L.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05 +CLBLM_L.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10 +CLBLM_L.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10 +CLBLM_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10 +CLBLM_L.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07 CLBLM_L.SLICEL_X1.B5FF.ZINI 31_23 CLBLM_L.SLICEL_X1.B5FF.ZRST 00_16 +CLBLM_L.SLICEL_X1.B5FFMUX.IN_A 31_19 +CLBLM_L.SLICEL_X1.B5FFMUX.IN_B 31_18 CLBLM_L.SLICEL_X1.BFF.ZINI 31_29 CLBLM_L.SLICEL_X1.BFF.ZRST 31_30 +CLBLM_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27 +CLBLM_L.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26 +CLBLM_L.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27 +CLBLM_L.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25 +CLBLM_L.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24 +CLBLM_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26 CLBLM_L.SLICEL_X1.BLUT.INIT[00] 26_31 CLBLM_L.SLICEL_X1.BLUT.INIT[01] 27_31 CLBLM_L.SLICEL_X1.BLUT.INIT[02] 26_30 @@ -134,15 +155,31 @@ CLBLM_L.SLICEL_X1.BLUT.INIT[60] 29_17 CLBLM_L.SLICEL_X1.BLUT.INIT[61] 28_17 CLBLM_L.SLICEL_X1.BLUT.INIT[62] 29_16 CLBLM_L.SLICEL_X1.BLUT.INIT[63] 28_16 +CLBLM_L.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29 +CLBLM_L.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21 +CLBLM_L.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21 +CLBLM_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21 +CLBLM_L.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28 CLBLM_L.SLICEL_X1.C5FF.ZINI 31_42 CLBLM_L.SLICEL_X1.C5FF.ZRST 00_44 +CLBLM_L.SLICEL_X1.C5FFMUX.IN_A 31_44 +CLBLM_L.SLICEL_X1.C5FFMUX.IN_B 31_39 +CLBLM_L.SLICEL_X1.CARRY4.ACY0 !30_04 !31_00 !31_02 31_01 31_04 31_14 31_15 CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14 +CLBLM_L.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30 CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08 +CLBLM_L.SLICEL_X1.CARRY4.CCY0 !31_35 !31_36 !31_37 30_34 31_34 31_38 31_48 CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48 CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49 CLBLM_L.SLICEL_X1.CEUSEDMUX 00_36 CLBLM_L.SLICEL_X1.CFF.ZINI 31_34 CLBLM_L.SLICEL_X1.CFF.ZRST 30_34 +CLBLM_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38 +CLBLM_L.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37 +CLBLM_L.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38 +CLBLM_L.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36 +CLBLM_L.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36 +CLBLM_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37 CLBLM_L.SLICEL_X1.CLKINV 00_52 CLBLM_L.SLICEL_X1.CLUT.INIT[00] 26_47 CLBLM_L.SLICEL_X1.CLUT.INIT[01] 27_47 @@ -208,10 +245,22 @@ CLBLM_L.SLICEL_X1.CLUT.INIT[60] 29_33 CLBLM_L.SLICEL_X1.CLUT.INIT[61] 28_33 CLBLM_L.SLICEL_X1.CLUT.INIT[62] 29_32 CLBLM_L.SLICEL_X1.CLUT.INIT[63] 28_32 +CLBLM_L.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41 +CLBLM_L.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40 +CLBLM_L.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40 +CLBLM_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43 +CLBLM_L.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42 CLBLM_L.SLICEL_X1.D5FF.ZINI 31_52 CLBLM_L.SLICEL_X1.D5FF.ZRST 00_56 +CLBLM_L.SLICEL_X1.D5FFMUX.IN_A 31_55 +CLBLM_L.SLICEL_X1.D5FFMUX.IN_B 31_54 CLBLM_L.SLICEL_X1.DFF.ZINI 31_59 CLBLM_L.SLICEL_X1.DFF.ZRST 31_50 +CLBLM_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62 +CLBLM_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61 +CLBLM_L.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60 +CLBLM_L.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60 +CLBLM_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62 CLBLM_L.SLICEL_X1.DLUT.INIT[00] 26_63 CLBLM_L.SLICEL_X1.DLUT.INIT[01] 27_63 CLBLM_L.SLICEL_X1.DLUT.INIT[02] 26_62 @@ -276,6 +325,10 @@ CLBLM_L.SLICEL_X1.DLUT.INIT[60] 29_49 CLBLM_L.SLICEL_X1.DLUT.INIT[61] 28_49 CLBLM_L.SLICEL_X1.DLUT.INIT[62] 29_48 CLBLM_L.SLICEL_X1.DLUT.INIT[63] 28_48 +CLBLM_L.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57 +CLBLM_L.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53 +CLBLM_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57 +CLBLM_L.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53 CLBLM_L.SLICEL_X1.FFSYNC 01_31 CLBLM_L.SLICEL_X1.LATCH 31_32 CLBLM_L.SLICEL_X1.PRECYINIT.1 01_11 @@ -284,8 +337,18 @@ CLBLM_L.SLICEL_X1.PRECYINIT.CIN 31_12 CLBLM_L.SLICEL_X1.SRUSEDMUX 00_32 CLBLM_L.SLICEM_X0.A5FF.ZINI 31_06 CLBLM_L.SLICEM_X0.A5FF.ZRST 01_07 +CLBLM_L.SLICEM_X0.A5FFMUX.IN_A 30_09 +CLBLM_L.SLICEM_X0.A5FFMUX.IN_B 30_10 +CLBLM_L.SLICEM_X0.ADI1MUX.AI !22_00 !23_00 !24_00 00_00 25_00 CLBLM_L.SLICEM_X0.AFF.ZINI 31_03 CLBLM_L.SLICEM_X0.AFF.ZRST 30_12 +CLBLM_L.SLICEM_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01 +CLBLM_L.SLICEM_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02 +CLBLM_L.SLICEM_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01 +CLBLM_L.SLICEM_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03 +CLBLM_L.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03 +CLBLM_L.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02 +CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI 00_00 CLBLM_L.SLICEM_X0.ALUT.INIT[00] 34_15 CLBLM_L.SLICEM_X0.ALUT.INIT[01] 35_15 CLBLM_L.SLICEM_X0.ALUT.INIT[02] 34_14 @@ -350,10 +413,28 @@ CLBLM_L.SLICEM_X0.ALUT.INIT[60] 32_01 CLBLM_L.SLICEM_X0.ALUT.INIT[61] 33_01 CLBLM_L.SLICEM_X0.ALUT.INIT[62] 32_00 CLBLM_L.SLICEM_X0.ALUT.INIT[63] 33_00 +CLBLM_L.SLICEM_X0.ALUT.RAM 31_16 +CLBLM_L.SLICEM_X0.ALUT.SMALL 00_04 +CLBLM_L.SLICEM_X0.ALUT.SRL 30_16 +CLBLM_L.SLICEM_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07 +CLBLM_L.SLICEM_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08 +CLBLM_L.SLICEM_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07 +CLBLM_L.SLICEM_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11 +CLBLM_L.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08 CLBLM_L.SLICEM_X0.B5FF.ZINI 31_22 CLBLM_L.SLICEM_X0.B5FF.ZRST 01_19 +CLBLM_L.SLICEM_X0.B5FFMUX.IN_A 30_19 +CLBLM_L.SLICEM_X0.B5FFMUX.IN_B 30_18 +CLBLM_L.SLICEM_X0.BDI1MUX.BI 00_20 CLBLM_L.SLICEM_X0.BFF.ZINI 31_28 CLBLM_L.SLICEM_X0.BFF.ZRST 30_30 +CLBLM_L.SLICEM_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26 +CLBLM_L.SLICEM_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27 +CLBLM_L.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27 +CLBLM_L.SLICEM_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27 +CLBLM_L.SLICEM_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24 +CLBLM_L.SLICEM_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25 +CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI 00_20 CLBLM_L.SLICEM_X0.BLUT.INIT[00] 34_31 CLBLM_L.SLICEM_X0.BLUT.INIT[01] 35_31 CLBLM_L.SLICEM_X0.BLUT.INIT[02] 34_30 @@ -418,16 +499,37 @@ CLBLM_L.SLICEM_X0.BLUT.INIT[60] 32_17 CLBLM_L.SLICEM_X0.BLUT.INIT[61] 33_17 CLBLM_L.SLICEM_X0.BLUT.INIT[62] 32_16 CLBLM_L.SLICEM_X0.BLUT.INIT[63] 33_16 +CLBLM_L.SLICEM_X0.BLUT.RAM 31_17 +CLBLM_L.SLICEM_X0.BLUT.SMALL 00_24 +CLBLM_L.SLICEM_X0.BLUT.SRL 30_17 +CLBLM_L.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23 +CLBLM_L.SLICEM_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22 +CLBLM_L.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23 +CLBLM_L.SLICEM_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22 +CLBLM_L.SLICEM_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21 CLBLM_L.SLICEM_X0.C5FF.ZINI 31_41 CLBLM_L.SLICEM_X0.C5FF.ZRST 01_47 +CLBLM_L.SLICEM_X0.C5FFMUX.IN_A 31_45 +CLBLM_L.SLICEM_X0.C5FFMUX.IN_B 30_39 +CLBLM_L.SLICEM_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03 CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_15 +CLBLM_L.SLICEM_X0.CARRY4.BCY0 !30_24 !30_25 !30_27 01_15 30_26 30_30 31_28 CLBLM_L.SLICEM_X0.CARRY4.BCY0 01_15 +CLBLM_L.SLICEM_X0.CARRY4.CCY0 !30_35 !30_37 !30_38 30_33 30_36 30_48 31_33 CLBLM_L.SLICEM_X0.CARRY4.CCY0 30_48 CLBLM_L.SLICEM_X0.CARRY4.DCY0 30_49 +CLBLM_L.SLICEM_X0.CDI1MUX.CI 01_43 CLBLM_L.SLICEM_X0.CEUSEDMUX 01_39 CLBLM_L.SLICEM_X0.CFF.ZINI 31_33 CLBLM_L.SLICEM_X0.CFF.ZRST 30_33 +CLBLM_L.SLICEM_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36 +CLBLM_L.SLICEM_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37 +CLBLM_L.SLICEM_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36 +CLBLM_L.SLICEM_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38 +CLBLM_L.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38 +CLBLM_L.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37 CLBLM_L.SLICEM_X0.CLKINV 01_51 +CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI 01_43 CLBLM_L.SLICEM_X0.CLUT.INIT[00] 34_47 CLBLM_L.SLICEM_X0.CLUT.INIT[01] 35_47 CLBLM_L.SLICEM_X0.CLUT.INIT[02] 34_46 @@ -492,10 +594,25 @@ CLBLM_L.SLICEM_X0.CLUT.INIT[60] 32_33 CLBLM_L.SLICEM_X0.CLUT.INIT[61] 33_33 CLBLM_L.SLICEM_X0.CLUT.INIT[62] 32_32 CLBLM_L.SLICEM_X0.CLUT.INIT[63] 33_32 +CLBLM_L.SLICEM_X0.CLUT.RAM 31_46 +CLBLM_L.SLICEM_X0.CLUT.SMALL 00_28 +CLBLM_L.SLICEM_X0.CLUT.SRL 30_46 +CLBLM_L.SLICEM_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43 +CLBLM_L.SLICEM_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44 +CLBLM_L.SLICEM_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43 +CLBLM_L.SLICEM_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45 +CLBLM_L.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44 CLBLM_L.SLICEM_X0.D5FF.ZINI 31_51 CLBLM_L.SLICEM_X0.D5FF.ZRST 01_55 +CLBLM_L.SLICEM_X0.D5FFMUX.IN_A 30_55 +CLBLM_L.SLICEM_X0.D5FFMUX.IN_B 30_54 CLBLM_L.SLICEM_X0.DFF.ZINI 31_58 CLBLM_L.SLICEM_X0.DFF.ZRST 30_50 +CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62 +CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61 +CLBLM_L.SLICEM_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62 +CLBLM_L.SLICEM_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59 +CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60 CLBLM_L.SLICEM_X0.DLUT.INIT[00] 34_63 CLBLM_L.SLICEM_X0.DLUT.INIT[01] 35_63 CLBLM_L.SLICEM_X0.DLUT.INIT[02] 34_62 @@ -560,9 +677,19 @@ CLBLM_L.SLICEM_X0.DLUT.INIT[60] 32_49 CLBLM_L.SLICEM_X0.DLUT.INIT[61] 33_49 CLBLM_L.SLICEM_X0.DLUT.INIT[62] 32_48 CLBLM_L.SLICEM_X0.DLUT.INIT[63] 33_48 +CLBLM_L.SLICEM_X0.DLUT.RAM 31_47 +CLBLM_L.SLICEM_X0.DLUT.SMALL 01_59 +CLBLM_L.SLICEM_X0.DLUT.SRL 30_47 +CLBLM_L.SLICEM_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52 +CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57 +CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56 +CLBLM_L.SLICEM_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51 CLBLM_L.SLICEM_X0.FFSYNC 00_48 CLBLM_L.SLICEM_X0.LATCH 30_32 CLBLM_L.SLICEM_X0.PRECYINIT.1 00_12 CLBLM_L.SLICEM_X0.PRECYINIT.AX 30_14 CLBLM_L.SLICEM_X0.PRECYINIT.CIN 30_13 CLBLM_L.SLICEM_X0.SRUSEDMUX 01_35 +CLBLM_L.SLICEM_X0.WA7USED 00_40 +CLBLM_L.SLICEM_X0.WA8USED 01_27 +CLBLM_L.SLICEM_X0.WEMUX.CE 01_23 diff --git a/kintex7/segbits_clblm_r.db b/kintex7/segbits_clblm_r.db index ab96ca1..85e3b5d 100644 --- a/kintex7/segbits_clblm_r.db +++ b/kintex7/segbits_clblm_r.db @@ -1,7 +1,15 @@ CLBLM_R.SLICEL_X1.A5FF.ZINI 31_05 CLBLM_R.SLICEL_X1.A5FF.ZRST 01_03 +CLBLM_R.SLICEL_X1.A5FFMUX.IN_A 31_08 +CLBLM_R.SLICEL_X1.A5FFMUX.IN_B 31_11 CLBLM_R.SLICEL_X1.AFF.ZINI 31_04 CLBLM_R.SLICEL_X1.AFF.ZRST 31_15 +CLBLM_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01 +CLBLM_R.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02 +CLBLM_R.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01 +CLBLM_R.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00 +CLBLM_R.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04 +CLBLM_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02 CLBLM_R.SLICEL_X1.ALUT.INIT[00] 26_15 CLBLM_R.SLICEL_X1.ALUT.INIT[01] 27_15 CLBLM_R.SLICEL_X1.ALUT.INIT[02] 26_14 @@ -66,10 +74,23 @@ CLBLM_R.SLICEL_X1.ALUT.INIT[60] 29_01 CLBLM_R.SLICEL_X1.ALUT.INIT[61] 28_01 CLBLM_R.SLICEL_X1.ALUT.INIT[62] 29_00 CLBLM_R.SLICEL_X1.ALUT.INIT[63] 28_00 +CLBLM_R.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05 +CLBLM_R.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10 +CLBLM_R.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10 +CLBLM_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10 +CLBLM_R.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07 CLBLM_R.SLICEL_X1.B5FF.ZINI 31_23 CLBLM_R.SLICEL_X1.B5FF.ZRST 00_16 +CLBLM_R.SLICEL_X1.B5FFMUX.IN_A 31_19 +CLBLM_R.SLICEL_X1.B5FFMUX.IN_B 31_18 CLBLM_R.SLICEL_X1.BFF.ZINI 31_29 CLBLM_R.SLICEL_X1.BFF.ZRST 31_30 +CLBLM_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27 +CLBLM_R.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26 +CLBLM_R.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27 +CLBLM_R.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25 +CLBLM_R.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24 +CLBLM_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26 CLBLM_R.SLICEL_X1.BLUT.INIT[00] 26_31 CLBLM_R.SLICEL_X1.BLUT.INIT[01] 27_31 CLBLM_R.SLICEL_X1.BLUT.INIT[02] 26_30 @@ -134,15 +155,31 @@ CLBLM_R.SLICEL_X1.BLUT.INIT[60] 29_17 CLBLM_R.SLICEL_X1.BLUT.INIT[61] 28_17 CLBLM_R.SLICEL_X1.BLUT.INIT[62] 29_16 CLBLM_R.SLICEL_X1.BLUT.INIT[63] 28_16 +CLBLM_R.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29 +CLBLM_R.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21 +CLBLM_R.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21 +CLBLM_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21 +CLBLM_R.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28 CLBLM_R.SLICEL_X1.C5FF.ZINI 31_42 CLBLM_R.SLICEL_X1.C5FF.ZRST 00_44 +CLBLM_R.SLICEL_X1.C5FFMUX.IN_A 31_44 +CLBLM_R.SLICEL_X1.C5FFMUX.IN_B 31_39 +CLBLM_R.SLICEL_X1.CARRY4.ACY0 !30_04 !31_00 !31_02 31_01 31_04 31_14 31_15 CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14 +CLBLM_R.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30 CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08 +CLBLM_R.SLICEL_X1.CARRY4.CCY0 !31_35 !31_36 !31_37 30_34 31_34 31_38 31_48 CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48 CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49 CLBLM_R.SLICEL_X1.CEUSEDMUX 00_36 CLBLM_R.SLICEL_X1.CFF.ZINI 31_34 CLBLM_R.SLICEL_X1.CFF.ZRST 30_34 +CLBLM_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38 +CLBLM_R.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37 +CLBLM_R.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38 +CLBLM_R.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36 +CLBLM_R.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36 +CLBLM_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37 CLBLM_R.SLICEL_X1.CLKINV 00_52 CLBLM_R.SLICEL_X1.CLUT.INIT[00] 26_47 CLBLM_R.SLICEL_X1.CLUT.INIT[01] 27_47 @@ -208,10 +245,22 @@ CLBLM_R.SLICEL_X1.CLUT.INIT[60] 29_33 CLBLM_R.SLICEL_X1.CLUT.INIT[61] 28_33 CLBLM_R.SLICEL_X1.CLUT.INIT[62] 29_32 CLBLM_R.SLICEL_X1.CLUT.INIT[63] 28_32 +CLBLM_R.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41 +CLBLM_R.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40 +CLBLM_R.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40 +CLBLM_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43 +CLBLM_R.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42 CLBLM_R.SLICEL_X1.D5FF.ZINI 31_52 CLBLM_R.SLICEL_X1.D5FF.ZRST 00_56 +CLBLM_R.SLICEL_X1.D5FFMUX.IN_A 31_55 +CLBLM_R.SLICEL_X1.D5FFMUX.IN_B 31_54 CLBLM_R.SLICEL_X1.DFF.ZINI 31_59 CLBLM_R.SLICEL_X1.DFF.ZRST 31_50 +CLBLM_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62 +CLBLM_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61 +CLBLM_R.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60 +CLBLM_R.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60 +CLBLM_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62 CLBLM_R.SLICEL_X1.DLUT.INIT[00] 26_63 CLBLM_R.SLICEL_X1.DLUT.INIT[01] 27_63 CLBLM_R.SLICEL_X1.DLUT.INIT[02] 26_62 @@ -276,6 +325,10 @@ CLBLM_R.SLICEL_X1.DLUT.INIT[60] 29_49 CLBLM_R.SLICEL_X1.DLUT.INIT[61] 28_49 CLBLM_R.SLICEL_X1.DLUT.INIT[62] 29_48 CLBLM_R.SLICEL_X1.DLUT.INIT[63] 28_48 +CLBLM_R.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57 +CLBLM_R.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53 +CLBLM_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57 +CLBLM_R.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53 CLBLM_R.SLICEL_X1.FFSYNC 01_31 CLBLM_R.SLICEL_X1.LATCH 31_32 CLBLM_R.SLICEL_X1.PRECYINIT.1 01_11 @@ -284,8 +337,18 @@ CLBLM_R.SLICEL_X1.PRECYINIT.CIN 31_12 CLBLM_R.SLICEL_X1.SRUSEDMUX 00_32 CLBLM_R.SLICEM_X0.A5FF.ZINI 31_06 CLBLM_R.SLICEM_X0.A5FF.ZRST 01_07 +CLBLM_R.SLICEM_X0.A5FFMUX.IN_A 30_09 +CLBLM_R.SLICEM_X0.A5FFMUX.IN_B 30_10 +CLBLM_R.SLICEM_X0.ADI1MUX.AI !22_00 !23_00 !24_00 00_00 25_00 CLBLM_R.SLICEM_X0.AFF.ZINI 31_03 CLBLM_R.SLICEM_X0.AFF.ZRST 30_12 +CLBLM_R.SLICEM_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01 +CLBLM_R.SLICEM_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02 +CLBLM_R.SLICEM_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01 +CLBLM_R.SLICEM_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03 +CLBLM_R.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03 +CLBLM_R.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02 +CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI 00_00 CLBLM_R.SLICEM_X0.ALUT.INIT[00] 34_15 CLBLM_R.SLICEM_X0.ALUT.INIT[01] 35_15 CLBLM_R.SLICEM_X0.ALUT.INIT[02] 34_14 @@ -350,10 +413,28 @@ CLBLM_R.SLICEM_X0.ALUT.INIT[60] 32_01 CLBLM_R.SLICEM_X0.ALUT.INIT[61] 33_01 CLBLM_R.SLICEM_X0.ALUT.INIT[62] 32_00 CLBLM_R.SLICEM_X0.ALUT.INIT[63] 33_00 +CLBLM_R.SLICEM_X0.ALUT.RAM 31_16 +CLBLM_R.SLICEM_X0.ALUT.SMALL 00_04 +CLBLM_R.SLICEM_X0.ALUT.SRL 30_16 +CLBLM_R.SLICEM_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07 +CLBLM_R.SLICEM_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08 +CLBLM_R.SLICEM_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07 +CLBLM_R.SLICEM_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11 +CLBLM_R.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08 CLBLM_R.SLICEM_X0.B5FF.ZINI 31_22 CLBLM_R.SLICEM_X0.B5FF.ZRST 01_19 +CLBLM_R.SLICEM_X0.B5FFMUX.IN_A 30_19 +CLBLM_R.SLICEM_X0.B5FFMUX.IN_B 30_18 +CLBLM_R.SLICEM_X0.BDI1MUX.BI 00_20 CLBLM_R.SLICEM_X0.BFF.ZINI 31_28 CLBLM_R.SLICEM_X0.BFF.ZRST 30_30 +CLBLM_R.SLICEM_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26 +CLBLM_R.SLICEM_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27 +CLBLM_R.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27 +CLBLM_R.SLICEM_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27 +CLBLM_R.SLICEM_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24 +CLBLM_R.SLICEM_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25 +CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI 00_20 CLBLM_R.SLICEM_X0.BLUT.INIT[00] 34_31 CLBLM_R.SLICEM_X0.BLUT.INIT[01] 35_31 CLBLM_R.SLICEM_X0.BLUT.INIT[02] 34_30 @@ -418,16 +499,37 @@ CLBLM_R.SLICEM_X0.BLUT.INIT[60] 32_17 CLBLM_R.SLICEM_X0.BLUT.INIT[61] 33_17 CLBLM_R.SLICEM_X0.BLUT.INIT[62] 32_16 CLBLM_R.SLICEM_X0.BLUT.INIT[63] 33_16 +CLBLM_R.SLICEM_X0.BLUT.RAM 31_17 +CLBLM_R.SLICEM_X0.BLUT.SMALL 00_24 +CLBLM_R.SLICEM_X0.BLUT.SRL 30_17 +CLBLM_R.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23 +CLBLM_R.SLICEM_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22 +CLBLM_R.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23 +CLBLM_R.SLICEM_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22 +CLBLM_R.SLICEM_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21 CLBLM_R.SLICEM_X0.C5FF.ZINI 31_41 CLBLM_R.SLICEM_X0.C5FF.ZRST 01_47 +CLBLM_R.SLICEM_X0.C5FFMUX.IN_A 31_45 +CLBLM_R.SLICEM_X0.C5FFMUX.IN_B 30_39 +CLBLM_R.SLICEM_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03 CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_15 +CLBLM_R.SLICEM_X0.CARRY4.BCY0 !30_24 !30_25 !30_27 01_15 30_26 30_30 31_28 CLBLM_R.SLICEM_X0.CARRY4.BCY0 01_15 +CLBLM_R.SLICEM_X0.CARRY4.CCY0 !30_35 !30_37 !30_38 30_33 30_36 30_48 31_33 CLBLM_R.SLICEM_X0.CARRY4.CCY0 30_48 CLBLM_R.SLICEM_X0.CARRY4.DCY0 30_49 +CLBLM_R.SLICEM_X0.CDI1MUX.CI 01_43 CLBLM_R.SLICEM_X0.CEUSEDMUX 01_39 CLBLM_R.SLICEM_X0.CFF.ZINI 31_33 CLBLM_R.SLICEM_X0.CFF.ZRST 30_33 +CLBLM_R.SLICEM_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36 +CLBLM_R.SLICEM_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37 +CLBLM_R.SLICEM_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36 +CLBLM_R.SLICEM_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38 +CLBLM_R.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38 +CLBLM_R.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37 CLBLM_R.SLICEM_X0.CLKINV 01_51 +CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI 01_43 CLBLM_R.SLICEM_X0.CLUT.INIT[00] 34_47 CLBLM_R.SLICEM_X0.CLUT.INIT[01] 35_47 CLBLM_R.SLICEM_X0.CLUT.INIT[02] 34_46 @@ -492,10 +594,25 @@ CLBLM_R.SLICEM_X0.CLUT.INIT[60] 32_33 CLBLM_R.SLICEM_X0.CLUT.INIT[61] 33_33 CLBLM_R.SLICEM_X0.CLUT.INIT[62] 32_32 CLBLM_R.SLICEM_X0.CLUT.INIT[63] 33_32 +CLBLM_R.SLICEM_X0.CLUT.RAM 31_46 +CLBLM_R.SLICEM_X0.CLUT.SMALL 00_28 +CLBLM_R.SLICEM_X0.CLUT.SRL 30_46 +CLBLM_R.SLICEM_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43 +CLBLM_R.SLICEM_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44 +CLBLM_R.SLICEM_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43 +CLBLM_R.SLICEM_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45 +CLBLM_R.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44 CLBLM_R.SLICEM_X0.D5FF.ZINI 31_51 CLBLM_R.SLICEM_X0.D5FF.ZRST 01_55 +CLBLM_R.SLICEM_X0.D5FFMUX.IN_A 30_55 +CLBLM_R.SLICEM_X0.D5FFMUX.IN_B 30_54 CLBLM_R.SLICEM_X0.DFF.ZINI 31_58 CLBLM_R.SLICEM_X0.DFF.ZRST 30_50 +CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62 +CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61 +CLBLM_R.SLICEM_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62 +CLBLM_R.SLICEM_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59 +CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60 CLBLM_R.SLICEM_X0.DLUT.INIT[00] 34_63 CLBLM_R.SLICEM_X0.DLUT.INIT[01] 35_63 CLBLM_R.SLICEM_X0.DLUT.INIT[02] 34_62 @@ -560,9 +677,19 @@ CLBLM_R.SLICEM_X0.DLUT.INIT[60] 32_49 CLBLM_R.SLICEM_X0.DLUT.INIT[61] 33_49 CLBLM_R.SLICEM_X0.DLUT.INIT[62] 32_48 CLBLM_R.SLICEM_X0.DLUT.INIT[63] 33_48 +CLBLM_R.SLICEM_X0.DLUT.RAM 31_47 +CLBLM_R.SLICEM_X0.DLUT.SMALL 01_59 +CLBLM_R.SLICEM_X0.DLUT.SRL 30_47 +CLBLM_R.SLICEM_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52 +CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57 +CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56 +CLBLM_R.SLICEM_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51 CLBLM_R.SLICEM_X0.FFSYNC 00_48 CLBLM_R.SLICEM_X0.LATCH 30_32 CLBLM_R.SLICEM_X0.PRECYINIT.1 00_12 CLBLM_R.SLICEM_X0.PRECYINIT.AX 30_14 CLBLM_R.SLICEM_X0.PRECYINIT.CIN 30_13 CLBLM_R.SLICEM_X0.SRUSEDMUX 01_35 +CLBLM_R.SLICEM_X0.WA7USED 00_40 +CLBLM_R.SLICEM_X0.WA8USED 01_27 +CLBLM_R.SLICEM_X0.WEMUX.CE 01_23 diff --git a/kintex7/segbits_hclk_l.db b/kintex7/segbits_hclk_l.db new file mode 100644 index 0000000..28bca80 --- /dev/null +++ b/kintex7/segbits_hclk_l.db @@ -0,0 +1,196 @@ +HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK10 00_22 +HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK11 01_22 +HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK8 00_14 +HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK9 01_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK10 01_15 04_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK11 01_15 03_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK8 01_15 04_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK9 01_15 03_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK0 00_16 04_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK1 00_16 03_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK2 00_16 04_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK3 00_16 03_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L0 01_14 04_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L1 01_14 03_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L2 01_14 04_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L3 01_14 03_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L4 00_15 04_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L5 00_15 03_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L6 00_15 04_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L7 00_15 03_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK10 02_15 04_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK11 04_16 05_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK8 02_14 04_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK9 04_16 05_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK0 02_14 02_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK1 02_16 05_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK2 02_15 02_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK3 02_16 05_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L0 02_14 03_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L1 03_16 05_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L2 02_15 03_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L3 03_16 05_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L4 02_14 05_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L5 05_14 05_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L6 02_15 05_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L7 05_15 05_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK10 00_17 05_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK11 00_17 02_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK8 00_17 05_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK9 00_17 02_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK0 01_16 05_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK1 01_16 02_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK2 01_16 05_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK3 01_16 02_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L0 00_18 05_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L1 00_18 02_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L2 00_18 05_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L3 00_18 02_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L4 01_17 05_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L5 01_17 02_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L6 01_17 05_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L7 01_17 02_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK10 03_18 05_17 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK11 04_18 05_17 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK8 03_19 05_17 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK9 04_19 05_17 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK0 03_17 03_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK1 03_17 04_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK2 03_17 03_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK3 03_17 04_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L0 02_17 03_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L1 02_17 04_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L2 02_17 03_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L3 02_17 04_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L4 03_19 04_17 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L5 04_17 04_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L6 03_18 04_17 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L7 04_17 04_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK10 00_21 04_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK11 00_21 03_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK8 00_21 04_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK9 00_21 03_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK0 01_21 04_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK1 01_21 03_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK2 01_21 04_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK3 01_21 03_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L0 00_20 04_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L1 00_20 03_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L2 00_20 04_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L3 00_20 03_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L4 01_20 04_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L5 01_20 03_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L6 01_20 04_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L7 01_20 03_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK10 02_21 04_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK11 04_22 05_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK8 02_20 04_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK9 04_22 05_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK0 02_20 02_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK1 02_22 05_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK2 02_21 02_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK3 02_22 05_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L0 02_20 03_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L1 03_22 05_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L2 02_21 03_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L3 03_22 05_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L4 02_20 05_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L5 05_20 05_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L6 02_21 05_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L7 05_21 05_22 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK10 01_29 05_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK11 01_29 02_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK8 01_29 05_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK9 01_29 02_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK0 00_29 05_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK1 00_29 02_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK2 00_29 05_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK3 00_29 02_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L0 01_30 05_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L1 01_30 02_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L2 01_30 05_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L3 01_30 02_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L4 00_30 05_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L5 00_30 02_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L6 00_30 05_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L7 00_30 02_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK10 03_30 05_29 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK11 04_30 05_29 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK8 03_31 05_29 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK9 04_31 05_29 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK0 03_29 03_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK1 03_29 04_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK2 03_29 03_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK3 03_29 04_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L0 02_29 03_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L1 02_29 04_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L2 02_29 03_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L3 02_29 04_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L4 03_31 04_29 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L5 04_29 04_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L6 03_30 04_29 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L7 04_29 04_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK10 00_28 04_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK11 00_28 03_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK8 00_28 04_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK9 00_28 03_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK0 01_28 04_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK1 01_28 03_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK2 01_28 04_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK3 01_28 03_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L0 00_26 04_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L1 00_26 03_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L2 00_26 04_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L3 00_26 03_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L4 01_26 04_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L5 01_26 03_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L6 01_26 04_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L7 01_26 03_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK10 02_27 04_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK11 04_28 05_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK8 02_26 04_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK9 04_28 05_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK0 02_26 02_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK1 02_28 05_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK2 02_27 02_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK3 02_28 05_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L0 02_26 03_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L1 03_28 05_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L2 02_27 03_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L3 03_28 05_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L4 02_26 05_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L5 05_26 05_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L6 02_27 05_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L7 05_27 05_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK10 01_24 05_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK11 01_24 02_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK8 01_24 05_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK9 01_24 02_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK0 00_24 05_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK1 00_24 02_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK2 00_24 05_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK3 00_24 02_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L0 01_25 05_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L1 01_25 02_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L2 01_25 05_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L3 01_25 02_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L4 00_25 05_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L5 00_25 02_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L6 00_25 05_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L7 00_25 02_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK10 03_24 05_23 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK11 04_24 05_23 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK8 03_25 05_23 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK9 04_25 05_23 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK0 03_23 03_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK1 03_23 04_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK2 03_23 03_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK3 03_23 04_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L0 02_23 03_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L1 02_23 04_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L2 02_23 03_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L3 02_23 04_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L4 03_25 04_23 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L5 04_23 04_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L6 03_24 04_23 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L7 04_23 04_24 diff --git a/kintex7/segbits_hclk_r.db b/kintex7/segbits_hclk_r.db new file mode 100644 index 0000000..ebd0373 --- /dev/null +++ b/kintex7/segbits_hclk_r.db @@ -0,0 +1,200 @@ +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK0 00_14 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK1 01_19 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK2 00_22 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK3 01_22 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK4 00_23 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK5 01_23 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK6 00_31 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK7 01_31 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK0 01_14 04_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK1 01_14 03_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK2 01_14 04_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK3 01_14 03_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK4 00_15 04_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK5 00_15 03_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK6 00_15 04_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK7 00_15 03_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R0 00_16 04_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R1 00_16 03_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R2 00_16 04_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R3 00_16 03_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R4 01_15 04_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R5 01_15 03_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R6 01_15 04_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R7 01_15 03_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK0 02_14 03_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK1 03_16 05_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK2 02_15 03_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK3 03_16 05_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK4 02_14 05_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK5 05_14 05_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK6 02_15 05_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK7 05_15 05_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R0 02_14 02_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R1 02_16 05_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R2 02_15 02_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R3 02_16 05_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R4 02_14 04_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R5 04_16 05_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R6 02_15 04_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R7 04_16 05_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK0 00_18 05_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK1 00_18 02_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK2 00_18 05_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK3 00_18 02_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK4 01_17 05_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK5 01_17 02_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK6 01_17 05_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK7 01_17 02_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R0 01_16 05_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R1 01_16 02_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R2 01_16 05_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R3 01_16 02_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R4 00_17 05_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R5 00_17 02_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R6 00_17 05_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R7 00_17 02_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK0 02_17 03_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK1 02_17 04_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK2 02_17 03_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK3 02_17 04_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK4 03_19 04_17 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK5 04_17 04_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK6 03_18 04_17 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK7 04_17 04_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R0 03_17 03_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R1 03_17 04_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R2 03_17 03_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R3 03_17 04_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R4 03_19 05_17 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R5 04_19 05_17 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R6 03_18 05_17 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R7 04_18 05_17 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK0 00_20 04_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK1 00_20 03_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK2 00_20 04_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK3 00_20 03_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK4 01_20 04_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK5 01_20 03_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK6 01_20 04_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK7 01_20 03_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R0 01_21 04_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R1 01_21 03_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R2 01_21 04_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R3 01_21 03_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R4 00_21 04_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R5 00_21 03_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R6 00_21 04_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R7 00_21 03_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK0 02_20 03_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK1 03_22 05_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK2 02_21 03_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK3 03_22 05_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK4 02_20 05_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK5 05_20 05_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK6 02_21 05_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK7 05_21 05_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R0 02_20 02_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R1 02_22 05_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R2 02_21 02_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R3 02_22 05_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R4 02_20 04_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R5 04_22 05_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R6 02_21 04_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R7 04_22 05_21 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK0 01_30 05_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK1 01_30 02_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK2 01_30 05_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK3 01_30 02_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK4 00_30 05_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK5 00_30 02_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK6 00_30 05_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK7 00_30 02_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R0 00_29 05_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R1 00_29 02_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R2 00_29 05_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R3 00_29 02_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R4 01_29 05_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R5 01_29 02_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R6 01_29 05_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R7 01_29 02_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK0 02_29 03_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK1 02_29 04_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK2 02_29 03_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK3 02_29 04_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK4 03_31 04_29 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK5 04_29 04_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK6 03_30 04_29 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK7 04_29 04_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R0 03_29 03_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R1 03_29 04_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R2 03_29 03_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R3 03_29 04_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R4 03_31 05_29 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R5 04_31 05_29 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R6 03_30 05_29 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R7 04_30 05_29 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK0 00_26 04_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK1 00_26 03_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK2 00_26 04_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK3 00_26 03_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK4 01_26 04_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK5 01_26 03_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK6 01_26 04_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK7 01_26 03_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R0 01_28 04_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R1 01_28 03_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R2 01_28 04_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R3 01_28 03_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R4 00_28 04_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R5 00_28 03_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R6 00_28 04_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R7 00_28 03_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK0 02_26 03_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK1 03_28 05_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK2 02_27 03_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK3 03_28 05_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK4 02_26 05_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK5 05_26 05_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK6 02_27 05_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK7 05_27 05_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R0 02_26 02_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R1 02_28 05_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R2 02_27 02_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R3 02_28 05_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R4 02_26 04_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R5 04_28 05_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R6 02_27 04_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R7 04_28 05_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK0 01_25 05_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK1 01_25 02_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK2 01_25 05_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK3 01_25 02_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK4 00_25 05_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK5 00_25 02_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK6 00_25 05_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK7 00_25 02_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R0 00_24 05_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R1 00_24 02_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R2 00_24 05_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R3 00_24 02_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R4 01_24 05_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R5 01_24 02_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R6 01_24 05_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R7 01_24 02_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK0 02_23 03_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK1 02_23 04_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK2 02_23 03_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK3 02_23 04_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK4 03_25 04_23 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK5 04_23 04_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK6 03_24 04_23 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK7 04_23 04_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R0 03_23 03_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R1 03_23 04_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R2 03_23 03_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R3 03_23 04_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R4 03_25 05_23 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R5 04_25 05_23 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R6 03_24 05_23 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R7 04_24 05_23 diff --git a/kintex7/segbits_int_l.db b/kintex7/segbits_int_l.db index 347134c..4a84ad1 100644 --- a/kintex7/segbits_int_l.db +++ b/kintex7/segbits_int_l.db @@ -19,6 +19,7 @@ INT_L.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07 INT_L.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07 INT_L.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07 INT_L.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07 +INT_L.BYP_ALT0.VCC_WIRE !30_04 !30_58 !31_00 !31_01 !31_24 !31_25 !31_27 !31_35 !31_36 !31_38 !31_60 !31_61 31_02 31_26 31_37 31_62 INT_L.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07 INT_L.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07 INT_L.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07 @@ -43,6 +44,7 @@ INT_L.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15 INT_L.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15 INT_L.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15 INT_L.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15 +INT_L.BYP_ALT1.VCC_WIRE !30_00 !30_01 !30_03 !30_24 !30_26 !30_27 !30_35 !30_36 !30_38 !30_59 !30_61 !30_62 30_02 30_25 30_37 30_60 INT_L.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15 INT_L.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15 INT_L.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15 @@ -336,12 +338,14 @@ INT_L.EE2BEG3.SS2END3 09_55 14_54 INT_L.EE2BEG3.SS6END3 09_55 13_54 INT_L.EE4BEG0.EE2END0 03_08 03_09 INT_L.EE4BEG0.EE4END0 03_09 05_08 +INT_L.EE4BEG0.LH12 05_08 07_09 INT_L.EE4BEG0.LOGIC_OUTS_L0 02_09 04_10 INT_L.EE4BEG0.LOGIC_OUTS_L12 03_08 04_10 INT_L.EE4BEG0.LOGIC_OUTS_L18 06_08 07_09 INT_L.EE4BEG0.LOGIC_OUTS_L22 04_10 06_08 INT_L.EE4BEG0.LOGIC_OUTS_L4 02_09 07_09 INT_L.EE4BEG0.LOGIC_OUTS_L8 03_08 07_09 +INT_L.EE4BEG0.LV_L0 04_10 05_08 INT_L.EE4BEG0.NE2END0 02_09 04_09 INT_L.EE4BEG0.NE6END0 04_09 05_08 INT_L.EE4BEG0.NN2END0 03_08 04_09 @@ -354,12 +358,14 @@ INT_L.EE4BEG0.SW2END0 02_09 05_11 INT_L.EE4BEG0.SW6END0 05_08 05_11 INT_L.EE4BEG1.EE2END1 03_24 03_25 INT_L.EE4BEG1.EE4END1 03_25 05_24 +INT_L.EE4BEG1.LH6 05_24 07_25 INT_L.EE4BEG1.LOGIC_OUTS_L1 02_25 07_25 INT_L.EE4BEG1.LOGIC_OUTS_L13 03_24 07_25 INT_L.EE4BEG1.LOGIC_OUTS_L19 04_26 06_24 INT_L.EE4BEG1.LOGIC_OUTS_L23 06_24 07_25 INT_L.EE4BEG1.LOGIC_OUTS_L5 02_25 04_26 INT_L.EE4BEG1.LOGIC_OUTS_L9 03_24 04_26 +INT_L.EE4BEG1.LV_L9 04_26 05_24 INT_L.EE4BEG1.NE2END1 02_25 04_25 INT_L.EE4BEG1.NE6END1 04_25 05_24 INT_L.EE4BEG1.NN2END1 03_24 04_25 @@ -378,6 +384,8 @@ INT_L.EE4BEG2.LOGIC_OUTS_L16 06_40 07_41 INT_L.EE4BEG2.LOGIC_OUTS_L2 02_41 04_42 INT_L.EE4BEG2.LOGIC_OUTS_L20 04_42 06_40 INT_L.EE4BEG2.LOGIC_OUTS_L6 02_41 07_41 +INT_L.EE4BEG2.LVB_L0 04_42 05_40 +INT_L.EE4BEG2.LVB_L12 05_40 07_41 INT_L.EE4BEG2.NE2END2 02_41 04_41 INT_L.EE4BEG2.NE6END2 04_41 05_40 INT_L.EE4BEG2.NN2END2 03_40 04_41 @@ -390,12 +398,14 @@ INT_L.EE4BEG2.SW2END2 02_41 05_43 INT_L.EE4BEG2.SW6END2 05_40 05_43 INT_L.EE4BEG3.EE2END3 03_56 03_57 INT_L.EE4BEG3.EE4END3 03_57 05_56 +INT_L.EE4BEG3.LH0 04_58 05_56 INT_L.EE4BEG3.LOGIC_OUTS_L11 03_56 04_58 INT_L.EE4BEG3.LOGIC_OUTS_L15 03_56 07_57 INT_L.EE4BEG3.LOGIC_OUTS_L17 04_58 06_56 INT_L.EE4BEG3.LOGIC_OUTS_L21 06_56 07_57 INT_L.EE4BEG3.LOGIC_OUTS_L3 02_57 07_57 INT_L.EE4BEG3.LOGIC_OUTS_L7 02_57 04_58 +INT_L.EE4BEG3.LV_L18 05_56 07_57 INT_L.EE4BEG3.NE2END3 02_57 04_57 INT_L.EE4BEG3.NE6END3 04_57 05_56 INT_L.EE4BEG3.NN2END3 03_56 04_57 @@ -597,6 +607,7 @@ INT_L.FAN_ALT1.EL1END3 !22_48 17_48 23_48 24_48 25_48 INT_L.FAN_ALT1.ER1END2 !23_48 16_48 22_48 24_48 25_48 INT_L.FAN_ALT1.FAN_BOUNCE3 !22_48 20_48 23_48 24_48 25_48 INT_L.FAN_ALT1.FAN_BOUNCE_S3_4 !23_48 20_48 22_48 24_48 25_48 +INT_L.FAN_ALT1.GFAN1 !00_18 !00_19 !01_13 !22_48 !23_48 !24_48 00_14 00_17 21_48 25_48 INT_L.FAN_ALT1.LOGIC_OUTS_L11 !22_48 21_48 23_48 24_48 25_48 INT_L.FAN_ALT1.LOGIC_OUTS_L17 !22_48 !23_48 !25_48 21_48 24_48 INT_L.FAN_ALT1.LOGIC_OUTS_L7 !23_48 21_48 22_48 24_48 25_48 @@ -692,6 +703,7 @@ INT_L.FAN_ALT5.EL1END2 !22_40 16_40 23_40 24_40 25_40 INT_L.FAN_ALT5.ER1END2 !23_40 17_40 22_40 24_40 25_40 INT_L.FAN_ALT5.FAN_BOUNCE1 !22_40 20_40 23_40 24_40 25_40 INT_L.FAN_ALT5.FAN_BOUNCE_S3_0 !23_40 20_40 22_40 24_40 25_40 +INT_L.FAN_ALT5.GFAN1 !00_18 !00_19 !01_13 !22_40 !23_40 !24_40 00_14 00_17 21_40 25_40 INT_L.FAN_ALT5.LOGIC_OUTS_L10 !22_40 21_40 23_40 24_40 25_40 INT_L.FAN_ALT5.LOGIC_OUTS_L16 !22_40 !23_40 !25_40 21_40 24_40 INT_L.FAN_ALT5.LOGIC_OUTS_L6 !23_40 21_40 22_40 24_40 25_40 @@ -769,6 +781,7 @@ INT_L.GFAN0.GCLK_L_B6_WEST !00_10 !00_11 !01_09 01_10 01_18 INT_L.GFAN0.GCLK_L_B7_WEST !00_10 !01_09 !01_10 00_11 01_18 INT_L.GFAN0.GCLK_L_B8_WEST !01_09 00_10 00_11 01_10 01_16 INT_L.GFAN0.GCLK_L_B9_WEST !00_10 00_11 01_09 01_10 01_16 +INT_L.GFAN0.GND_WIRE !00_10 !01_09 !01_10 00_11 01_14 INT_L.GFAN0.NR1END1 !00_10 00_11 01_09 01_10 01_14 INT_L.GFAN0.WW4END1 !00_10 !00_11 !01_09 01_10 01_14 INT_L.GFAN1.BYP_BOUNCE1 !00_19 00_14 00_17 00_18 01_13 @@ -784,6 +797,7 @@ INT_L.GFAN1.GCLK_L_B6_WEST !00_18 !00_19 !01_13 00_14 00_15 INT_L.GFAN1.GCLK_L_B7_WEST !00_14 !00_18 !00_19 00_15 01_13 INT_L.GFAN1.GCLK_L_B8_WEST !00_19 00_14 00_18 01_13 01_17 INT_L.GFAN1.GCLK_L_B9_WEST !00_18 00_14 00_19 01_13 01_17 +INT_L.GFAN1.GND_WIRE !00_14 !00_18 !00_19 00_17 01_13 INT_L.GFAN1.NR1END1 !00_18 00_14 00_17 00_19 01_13 INT_L.GFAN1.WW4END1 !00_18 !00_19 !01_13 00_14 00_17 INT_L.IMUX_L0.BYP_BOUNCE_N3_2 !22_01 !23_01 !24_01 21_01 25_01 @@ -1938,6 +1952,90 @@ INT_L.IMUX_L9.SW2END0 !22_10 !23_10 !25_10 17_10 24_10 INT_L.IMUX_L9.WL1END0 !22_10 18_11 23_10 24_10 25_10 INT_L.IMUX_L9.WR1END0 !23_10 17_10 22_10 24_10 25_10 INT_L.IMUX_L9.WW2END0 !22_10 !23_10 !24_10 18_11 25_10 +INT_L.LH0.EE4END3 00_58 01_61 +INT_L.LH0.ER1END3 00_57 01_54 +INT_L.LH0.LH12 01_54 01_56 +INT_L.LH0.LV_L0 01_56 01_58 +INT_L.LH0.LV_L18 01_56 01_61 +INT_L.LH0.LV_L9 00_59 01_56 +INT_L.LH0.NE2END3 00_58 00_59 +INT_L.LH0.NE6END3 00_58 01_58 +INT_L.LH0.NW2END3 00_58 01_54 +INT_L.LH0.SR1END3 00_57 00_59 +INT_L.LH0.SS6END3 00_57 01_58 +INT_L.LH0.SW6END3 00_57 01_61 +INT_L.LH12.EE4END3 01_60 01_62 +INT_L.LH12.ER1END3 00_63 01_60 +INT_L.LH12.LH0 00_61 00_63 +INT_L.LH12.LV_L0 00_55 00_62 +INT_L.LH12.LV_L18 00_62 01_62 +INT_L.LH12.LV_L9 00_62 01_57 +INT_L.LH12.NE2END3 01_57 01_60 +INT_L.LH12.NE6END3 00_55 01_60 +INT_L.LH12.NW2END3 00_62 00_63 +INT_L.LH12.SR1END3 00_61 01_57 +INT_L.LH12.SS6END3 00_55 00_61 +INT_L.LH12.SW6END3 00_61 01_62 +INT_L.LVB_L0.LH0 00_43 00_51 +INT_L.LVB_L0.LH12 00_50 00_51 +INT_L.LVB_L0.LH6 00_51 00_53 +INT_L.LVB_L0.LVB_L12 00_51 00_54 +INT_L.LVB_L0.LV_L0 00_47 01_52 +INT_L.LVB_L0.LV_L18 01_42 01_52 +INT_L.LVB_L0.NE2END2 00_53 01_52 +INT_L.LVB_L0.NN6END3 00_50 01_50 +INT_L.LVB_L0.NR1END3 00_47 01_50 +INT_L.LVB_L0.NW2END2 00_43 01_52 +INT_L.LVB_L0.NW6END3 00_43 01_50 +INT_L.LVB_L0.SE2END3 00_51 01_42 +INT_L.LVB_L0.SE6END3 00_54 01_50 +INT_L.LVB_L0.SW2END2 00_50 01_52 +INT_L.LVB_L0.SW2END3 00_47 00_51 +INT_L.LVB_L0.SW6END2 00_54 01_52 +INT_L.LVB_L0.WR1END3 01_42 01_50 +INT_L.LVB_L0.WW4END3 00_53 01_50 +INT_L.LVB_L12.LH0 00_46 00_49 +INT_L.LVB_L12.LH12 00_46 01_53 +INT_L.LVB_L12.LH6 00_46 01_49 +INT_L.LVB_L12.LVB_L0 00_45 01_45 +INT_L.LVB_L12.LV_L0 00_45 01_44 +INT_L.LVB_L12.LV_L18 00_45 01_48 +INT_L.LVB_L12.NE2END2 00_45 01_49 +INT_L.LVB_L12.NN6END3 01_46 01_53 +INT_L.LVB_L12.NR1END3 01_44 01_46 +INT_L.LVB_L12.NW2END2 00_45 00_49 +INT_L.LVB_L12.NW6END3 00_49 01_46 +INT_L.LVB_L12.SE2END3 00_46 01_48 +INT_L.LVB_L12.SE6END3 00_46 01_45 +INT_L.LVB_L12.SW2END2 00_45 01_53 +INT_L.LVB_L12.SW2END3 00_46 01_44 +INT_L.LVB_L12.SW6END2 01_45 01_46 +INT_L.LVB_L12.WR1END3 01_46 01_48 +INT_L.LVB_L12.WW4END3 01_46 01_49 +INT_L.LV_L0.ER1END0 01_04 01_05 +INT_L.LV_L0.LH0 00_02 01_06 +INT_L.LV_L0.LH12 00_05 01_06 +INT_L.LV_L0.LH6 01_04 01_06 +INT_L.LV_L0.LV_L18 00_09 01_06 +INT_L.LV_L0.NN6END0 00_07 00_09 +INT_L.LV_L0.NR1END0 00_02 01_05 +INT_L.LV_L0.NW6END0 00_07 01_04 +INT_L.LV_L0.SR1BEG_S0 00_05 01_05 +INT_L.LV_L0.SW6END0 00_09 01_05 +INT_L.LV_L0.WR1END0 00_02 00_07 +INT_L.LV_L0.WW4END0 00_05 00_07 +INT_L.LV_L18.ER1END0 00_03 00_06 +INT_L.LV_L18.LH0 00_01 01_02 +INT_L.LV_L18.LH12 01_02 +INT_L.LV_L18.LH6 00_06 01_02 +INT_L.LV_L18.LV_L0 01_00 01_01 +INT_L.LV_L18.NN6END0 00_03 01_00 +INT_L.LV_L18.NR1END0 00_01 00_03 +INT_L.LV_L18.NW6END0 00_06 01_01 +INT_L.LV_L18.SR1BEG_S0 00_03 01_08 +INT_L.LV_L18.SW6END0 01_00 01_02 +INT_L.LV_L18.WR1END0 00_01 01_01 +INT_L.LV_L18.WW4END0 01_01 01_08 INT_L.NE2BEG0.EE2END0 09_04 14_04 INT_L.NE2BEG0.EE4END0 09_04 13_04 INT_L.NE2BEG0.EL1END0 09_05 12_04 @@ -2020,12 +2118,14 @@ INT_L.NE2BEG3.SE2END3 09_53 14_52 INT_L.NE2BEG3.SE6END3 09_53 13_52 INT_L.NE6BEG0.EE2END0 03_04 05_07 INT_L.NE6BEG0.EE4END0 05_04 05_07 +INT_L.NE6BEG0.LH12 05_04 07_05 INT_L.NE6BEG0.LOGIC_OUTS_L0 02_05 07_05 INT_L.NE6BEG0.LOGIC_OUTS_L12 03_04 07_05 INT_L.NE6BEG0.LOGIC_OUTS_L18 04_06 06_04 INT_L.NE6BEG0.LOGIC_OUTS_L22 06_04 07_05 INT_L.NE6BEG0.LOGIC_OUTS_L4 02_05 04_06 INT_L.NE6BEG0.LOGIC_OUTS_L8 03_04 04_06 +INT_L.NE6BEG0.LV_L0 04_06 05_04 INT_L.NE6BEG0.NE2END0 02_05 03_05 INT_L.NE6BEG0.NE6END0 03_05 05_04 INT_L.NE6BEG0.NN2END0 03_04 03_05 @@ -2038,12 +2138,14 @@ INT_L.NE6BEG0.WW2END_N0_3 03_04 04_05 INT_L.NE6BEG0.WW4END0 04_05 05_04 INT_L.NE6BEG1.EE2END1 03_20 05_23 INT_L.NE6BEG1.EE4END1 05_20 05_23 +INT_L.NE6BEG1.LH6 05_20 07_21 INT_L.NE6BEG1.LOGIC_OUTS_L1 02_21 04_22 INT_L.NE6BEG1.LOGIC_OUTS_L13 03_20 04_22 INT_L.NE6BEG1.LOGIC_OUTS_L19 06_20 07_21 INT_L.NE6BEG1.LOGIC_OUTS_L23 04_22 06_20 INT_L.NE6BEG1.LOGIC_OUTS_L5 02_21 07_21 INT_L.NE6BEG1.LOGIC_OUTS_L9 03_20 07_21 +INT_L.NE6BEG1.LV_L9 04_22 05_20 INT_L.NE6BEG1.NE2END1 02_21 03_21 INT_L.NE6BEG1.NE6END1 03_21 05_20 INT_L.NE6BEG1.NN2END1 03_20 03_21 @@ -2062,6 +2164,8 @@ INT_L.NE6BEG2.LOGIC_OUTS_L16 04_38 06_36 INT_L.NE6BEG2.LOGIC_OUTS_L2 02_37 07_37 INT_L.NE6BEG2.LOGIC_OUTS_L20 06_36 07_37 INT_L.NE6BEG2.LOGIC_OUTS_L6 02_37 04_38 +INT_L.NE6BEG2.LVB_L0 04_38 05_36 +INT_L.NE6BEG2.LVB_L12 05_36 07_37 INT_L.NE6BEG2.NE2END2 02_37 03_37 INT_L.NE6BEG2.NE6END2 03_37 05_36 INT_L.NE6BEG2.NN2END2 03_36 03_37 @@ -2074,12 +2178,14 @@ INT_L.NE6BEG2.WW2END1 03_36 04_37 INT_L.NE6BEG2.WW4END2 04_37 05_36 INT_L.NE6BEG3.EE2END3 03_52 05_55 INT_L.NE6BEG3.EE4END3 05_52 05_55 +INT_L.NE6BEG3.LH0 04_54 05_52 INT_L.NE6BEG3.LOGIC_OUTS_L11 03_52 07_53 INT_L.NE6BEG3.LOGIC_OUTS_L15 03_52 04_54 INT_L.NE6BEG3.LOGIC_OUTS_L17 06_52 07_53 INT_L.NE6BEG3.LOGIC_OUTS_L21 04_54 06_52 INT_L.NE6BEG3.LOGIC_OUTS_L3 02_53 04_54 INT_L.NE6BEG3.LOGIC_OUTS_L7 02_53 07_53 +INT_L.NE6BEG3.LV_L18 05_52 07_53 INT_L.NE6BEG3.NE2END3 02_53 03_53 INT_L.NE6BEG3.NE6END3 03_53 05_52 INT_L.NE6BEG3.NN2END3 03_52 03_53 @@ -2252,12 +2358,14 @@ INT_L.NN2BEG3.WW2END2 10_50 14_50 INT_L.NN2BEG3.WW4END3 10_50 13_50 INT_L.NN6BEG0.EE2END0 02_07 05_06 INT_L.NN6BEG0.EE4END0 04_07 05_06 +INT_L.NN6BEG0.LH12 04_07 05_05 INT_L.NN6BEG0.LOGIC_OUTS_L0 03_06 05_05 INT_L.NN6BEG0.LOGIC_OUTS_L12 02_07 05_05 INT_L.NN6BEG0.LOGIC_OUTS_L18 06_06 07_07 INT_L.NN6BEG0.LOGIC_OUTS_L22 05_05 07_07 INT_L.NN6BEG0.LOGIC_OUTS_L4 03_06 06_06 INT_L.NN6BEG0.LOGIC_OUTS_L8 02_07 06_06 +INT_L.NN6BEG0.LV_L0 04_07 06_06 INT_L.NN6BEG0.NE2END0 02_06 03_06 INT_L.NN6BEG0.NE6END0 02_06 04_07 INT_L.NN6BEG0.NN2END0 02_06 02_07 @@ -2270,12 +2378,14 @@ INT_L.NN6BEG0.WW2END_N0_3 02_07 04_04 INT_L.NN6BEG0.WW4END0 04_04 04_07 INT_L.NN6BEG1.EE2END1 02_23 05_22 INT_L.NN6BEG1.EE4END1 04_23 05_22 +INT_L.NN6BEG1.LH6 04_23 05_21 INT_L.NN6BEG1.LOGIC_OUTS_L1 03_22 06_22 INT_L.NN6BEG1.LOGIC_OUTS_L13 02_23 06_22 INT_L.NN6BEG1.LOGIC_OUTS_L19 05_21 07_23 INT_L.NN6BEG1.LOGIC_OUTS_L23 06_22 07_23 INT_L.NN6BEG1.LOGIC_OUTS_L5 03_22 05_21 INT_L.NN6BEG1.LOGIC_OUTS_L9 02_23 05_21 +INT_L.NN6BEG1.LV_L9 04_23 06_22 INT_L.NN6BEG1.NE2END1 02_22 03_22 INT_L.NN6BEG1.NE6END1 02_22 04_23 INT_L.NN6BEG1.NN2END1 02_22 02_23 @@ -2294,6 +2404,8 @@ INT_L.NN6BEG2.LOGIC_OUTS_L16 06_38 07_39 INT_L.NN6BEG2.LOGIC_OUTS_L2 03_38 05_37 INT_L.NN6BEG2.LOGIC_OUTS_L20 05_37 07_39 INT_L.NN6BEG2.LOGIC_OUTS_L6 03_38 06_38 +INT_L.NN6BEG2.LVB_L0 04_39 06_38 +INT_L.NN6BEG2.LVB_L12 04_39 05_37 INT_L.NN6BEG2.NE2END2 02_38 03_38 INT_L.NN6BEG2.NE6END2 02_38 04_39 INT_L.NN6BEG2.NN2END2 02_38 02_39 @@ -2306,12 +2418,14 @@ INT_L.NN6BEG2.WW2END1 02_39 04_36 INT_L.NN6BEG2.WW4END2 04_36 04_39 INT_L.NN6BEG3.EE2END3 02_55 05_54 INT_L.NN6BEG3.EE4END3 04_55 05_54 +INT_L.NN6BEG3.LH0 04_55 06_54 INT_L.NN6BEG3.LOGIC_OUTS_L11 02_55 05_53 INT_L.NN6BEG3.LOGIC_OUTS_L15 02_55 06_54 INT_L.NN6BEG3.LOGIC_OUTS_L17 05_53 07_55 INT_L.NN6BEG3.LOGIC_OUTS_L21 06_54 07_55 INT_L.NN6BEG3.LOGIC_OUTS_L3 03_54 06_54 INT_L.NN6BEG3.LOGIC_OUTS_L7 03_54 05_53 +INT_L.NN6BEG3.LV_L18 04_55 05_53 INT_L.NN6BEG3.NE2END3 02_54 03_54 INT_L.NN6BEG3.NE6END3 02_54 04_55 INT_L.NN6BEG3.NN2END3 02_54 02_55 @@ -2482,12 +2596,14 @@ INT_L.NW2BEG3.WL1END2 10_48 12_48 INT_L.NW2BEG3.WR1END3 09_48 12_48 INT_L.NW2BEG3.WW2END2 06_49 14_48 INT_L.NW2BEG3.WW4END3 06_49 13_48 +INT_L.NW6BEG0.LH12 04_03 05_01 INT_L.NW6BEG0.LOGIC_OUTS_L0 03_02 06_02 INT_L.NW6BEG0.LOGIC_OUTS_L12 02_03 06_02 INT_L.NW6BEG0.LOGIC_OUTS_L18 05_01 07_03 INT_L.NW6BEG0.LOGIC_OUTS_L22 06_02 07_03 INT_L.NW6BEG0.LOGIC_OUTS_L4 03_02 05_01 INT_L.NW6BEG0.LOGIC_OUTS_L8 02_03 05_01 +INT_L.NW6BEG0.LV_L0 04_03 06_02 INT_L.NW6BEG0.NE2END0 03_02 05_02 INT_L.NW6BEG0.NE6END0 04_03 05_02 INT_L.NW6BEG0.NN2END0 02_03 05_02 @@ -2500,12 +2616,14 @@ INT_L.NW6BEG0.SW2END_N0_3 03_02 04_00 INT_L.NW6BEG0.SW6END_N0_3 04_00 04_03 INT_L.NW6BEG0.WW2END_N0_3 02_02 02_03 INT_L.NW6BEG0.WW4END0 02_02 04_03 +INT_L.NW6BEG1.LH6 04_19 05_17 INT_L.NW6BEG1.LOGIC_OUTS_L1 03_18 05_17 INT_L.NW6BEG1.LOGIC_OUTS_L13 02_19 05_17 INT_L.NW6BEG1.LOGIC_OUTS_L19 06_18 07_19 INT_L.NW6BEG1.LOGIC_OUTS_L23 05_17 07_19 INT_L.NW6BEG1.LOGIC_OUTS_L5 03_18 06_18 INT_L.NW6BEG1.LOGIC_OUTS_L9 02_19 06_18 +INT_L.NW6BEG1.LV_L9 04_19 06_18 INT_L.NW6BEG1.NE2END1 03_18 05_18 INT_L.NW6BEG1.NE6END1 04_19 05_18 INT_L.NW6BEG1.NN2END1 02_19 05_18 @@ -2524,6 +2642,8 @@ INT_L.NW6BEG2.LOGIC_OUTS_L16 05_33 07_35 INT_L.NW6BEG2.LOGIC_OUTS_L2 03_34 06_34 INT_L.NW6BEG2.LOGIC_OUTS_L20 06_34 07_35 INT_L.NW6BEG2.LOGIC_OUTS_L6 03_34 05_33 +INT_L.NW6BEG2.LVB_L0 04_35 06_34 +INT_L.NW6BEG2.LVB_L12 04_35 05_33 INT_L.NW6BEG2.NE2END2 03_34 05_34 INT_L.NW6BEG2.NE6END2 04_35 05_34 INT_L.NW6BEG2.NN2END2 02_35 05_34 @@ -2536,12 +2656,14 @@ INT_L.NW6BEG2.SW2END1 03_34 04_32 INT_L.NW6BEG2.SW6END1 04_32 04_35 INT_L.NW6BEG2.WW2END1 02_34 02_35 INT_L.NW6BEG2.WW4END2 02_34 04_35 +INT_L.NW6BEG3.LH0 04_51 06_50 INT_L.NW6BEG3.LOGIC_OUTS_L11 02_51 06_50 INT_L.NW6BEG3.LOGIC_OUTS_L15 02_51 05_49 INT_L.NW6BEG3.LOGIC_OUTS_L17 06_50 07_51 INT_L.NW6BEG3.LOGIC_OUTS_L21 05_49 07_51 INT_L.NW6BEG3.LOGIC_OUTS_L3 03_50 05_49 INT_L.NW6BEG3.LOGIC_OUTS_L7 03_50 06_50 +INT_L.NW6BEG3.LV_L18 04_51 05_49 INT_L.NW6BEG3.NE2END3 03_50 05_50 INT_L.NW6BEG3.NE6END3 04_51 05_50 INT_L.NW6BEG3.NN2END3 02_51 05_50 @@ -2636,12 +2758,14 @@ INT_L.SE2BEG3.SW2END3 09_57 14_56 INT_L.SE2BEG3.SW6END3 09_57 13_56 INT_L.SE6BEG0.EE2END0 02_10 02_11 INT_L.SE6BEG0.EE4END0 02_10 04_11 +INT_L.SE6BEG0.LH12 04_11 05_09 INT_L.SE6BEG0.LOGIC_OUTS_L0 03_10 06_10 INT_L.SE6BEG0.LOGIC_OUTS_L12 02_11 06_10 INT_L.SE6BEG0.LOGIC_OUTS_L18 05_09 07_11 INT_L.SE6BEG0.LOGIC_OUTS_L22 06_10 07_11 INT_L.SE6BEG0.LOGIC_OUTS_L4 03_10 05_09 INT_L.SE6BEG0.LOGIC_OUTS_L8 02_11 05_09 +INT_L.SE6BEG0.LV_L0 04_11 06_10 INT_L.SE6BEG0.NE2END0 03_10 04_08 INT_L.SE6BEG0.NE6END0 04_08 04_11 INT_L.SE6BEG0.NN2END0 02_11 04_08 @@ -2654,12 +2778,14 @@ INT_L.SE6BEG0.SW2END0 03_10 05_10 INT_L.SE6BEG0.SW6END0 04_11 05_10 INT_L.SE6BEG1.EE2END1 02_26 02_27 INT_L.SE6BEG1.EE4END1 02_26 04_27 +INT_L.SE6BEG1.LH6 04_27 05_25 INT_L.SE6BEG1.LOGIC_OUTS_L1 03_26 05_25 INT_L.SE6BEG1.LOGIC_OUTS_L13 02_27 05_25 INT_L.SE6BEG1.LOGIC_OUTS_L19 06_26 07_27 INT_L.SE6BEG1.LOGIC_OUTS_L23 05_25 07_27 INT_L.SE6BEG1.LOGIC_OUTS_L5 03_26 06_26 INT_L.SE6BEG1.LOGIC_OUTS_L9 02_27 06_26 +INT_L.SE6BEG1.LV_L9 04_27 06_26 INT_L.SE6BEG1.NE2END1 03_26 04_24 INT_L.SE6BEG1.NE6END1 04_24 04_27 INT_L.SE6BEG1.NN2END1 02_27 04_24 @@ -2678,6 +2804,8 @@ INT_L.SE6BEG2.LOGIC_OUTS_L16 05_41 07_43 INT_L.SE6BEG2.LOGIC_OUTS_L2 03_42 06_42 INT_L.SE6BEG2.LOGIC_OUTS_L20 06_42 07_43 INT_L.SE6BEG2.LOGIC_OUTS_L6 03_42 05_41 +INT_L.SE6BEG2.LVB_L0 04_43 06_42 +INT_L.SE6BEG2.LVB_L12 04_43 05_41 INT_L.SE6BEG2.NE2END2 03_42 04_40 INT_L.SE6BEG2.NE6END2 04_40 04_43 INT_L.SE6BEG2.NN2END2 02_43 04_40 @@ -2690,12 +2818,14 @@ INT_L.SE6BEG2.SW2END2 03_42 05_42 INT_L.SE6BEG2.SW6END2 04_43 05_42 INT_L.SE6BEG3.EE2END3 02_58 02_59 INT_L.SE6BEG3.EE4END3 02_58 04_59 +INT_L.SE6BEG3.LH0 04_59 06_58 INT_L.SE6BEG3.LOGIC_OUTS_L11 02_59 06_58 INT_L.SE6BEG3.LOGIC_OUTS_L15 02_59 05_57 INT_L.SE6BEG3.LOGIC_OUTS_L17 06_58 07_59 INT_L.SE6BEG3.LOGIC_OUTS_L21 05_57 07_59 INT_L.SE6BEG3.LOGIC_OUTS_L3 03_58 05_57 INT_L.SE6BEG3.LOGIC_OUTS_L7 03_58 06_58 +INT_L.SE6BEG3.LV_L18 04_59 05_57 INT_L.SE6BEG3.NE2END3 03_58 04_56 INT_L.SE6BEG3.NE6END3 04_56 04_59 INT_L.SE6BEG3.NN2END3 02_59 04_56 @@ -2948,12 +3078,14 @@ INT_L.SS2BEG3.WW2END3 09_59 14_58 INT_L.SS2BEG3.WW4END_S0_0 09_59 13_58 INT_L.SS6BEG0.EE2END0 02_15 04_12 INT_L.SS6BEG0.EE4END0 04_12 04_15 +INT_L.SS6BEG0.LH12 04_15 05_13 INT_L.SS6BEG0.LOGIC_OUTS_L0 03_14 05_13 INT_L.SS6BEG0.LOGIC_OUTS_L12 02_15 05_13 INT_L.SS6BEG0.LOGIC_OUTS_L18 06_14 07_15 INT_L.SS6BEG0.LOGIC_OUTS_L22 05_13 07_15 INT_L.SS6BEG0.LOGIC_OUTS_L4 03_14 06_14 INT_L.SS6BEG0.LOGIC_OUTS_L8 02_15 06_14 +INT_L.SS6BEG0.LV_L0 04_15 06_14 INT_L.SS6BEG0.NW2END1 03_14 05_14 INT_L.SS6BEG0.NW6END1 05_14 07_15 INT_L.SS6BEG0.SE2END0 03_14 04_12 @@ -2966,12 +3098,14 @@ INT_L.SS6BEG0.WW2END0 02_15 05_14 INT_L.SS6BEG0.WW4END1 04_15 05_14 INT_L.SS6BEG1.EE2END1 02_31 04_28 INT_L.SS6BEG1.EE4END1 04_28 04_31 +INT_L.SS6BEG1.LH6 04_31 05_29 INT_L.SS6BEG1.LOGIC_OUTS_L1 03_30 06_30 INT_L.SS6BEG1.LOGIC_OUTS_L13 02_31 06_30 INT_L.SS6BEG1.LOGIC_OUTS_L19 05_29 07_31 INT_L.SS6BEG1.LOGIC_OUTS_L23 06_30 07_31 INT_L.SS6BEG1.LOGIC_OUTS_L5 03_30 05_29 INT_L.SS6BEG1.LOGIC_OUTS_L9 02_31 05_29 +INT_L.SS6BEG1.LV_L9 04_31 06_30 INT_L.SS6BEG1.NW2END2 03_30 05_30 INT_L.SS6BEG1.NW6END2 05_30 07_31 INT_L.SS6BEG1.SE2END1 03_30 04_28 @@ -2990,6 +3124,8 @@ INT_L.SS6BEG2.LOGIC_OUTS_L16 06_46 07_47 INT_L.SS6BEG2.LOGIC_OUTS_L2 03_46 05_45 INT_L.SS6BEG2.LOGIC_OUTS_L20 05_45 07_47 INT_L.SS6BEG2.LOGIC_OUTS_L6 03_46 06_46 +INT_L.SS6BEG2.LVB_L0 04_47 06_46 +INT_L.SS6BEG2.LVB_L12 04_47 05_45 INT_L.SS6BEG2.NW2END3 03_46 05_46 INT_L.SS6BEG2.NW6END3 05_46 07_47 INT_L.SS6BEG2.SE2END2 03_46 04_44 @@ -3002,12 +3138,14 @@ INT_L.SS6BEG2.WW2END2 02_47 05_46 INT_L.SS6BEG2.WW4END3 04_47 05_46 INT_L.SS6BEG3.EE2END3 02_63 04_60 INT_L.SS6BEG3.EE4END3 04_60 04_63 +INT_L.SS6BEG3.LH0 04_63 06_62 INT_L.SS6BEG3.LOGIC_OUTS_L11 02_63 05_61 INT_L.SS6BEG3.LOGIC_OUTS_L15 02_63 06_62 INT_L.SS6BEG3.LOGIC_OUTS_L17 05_61 07_63 INT_L.SS6BEG3.LOGIC_OUTS_L21 06_62 07_63 INT_L.SS6BEG3.LOGIC_OUTS_L3 03_62 06_62 INT_L.SS6BEG3.LOGIC_OUTS_L7 03_62 05_61 +INT_L.SS6BEG3.LV_L18 04_63 05_61 INT_L.SS6BEG3.NW2END_S0_0 03_62 05_62 INT_L.SS6BEG3.NW6END_S0_0 05_62 07_63 INT_L.SS6BEG3.SE2END3 03_62 04_60 @@ -3100,12 +3238,14 @@ INT_L.SW2BEG3.WW2END3 09_60 14_60 INT_L.SW2BEG3.WW4END_S0_0 09_60 13_60 INT_L.SW6BEG0.EE2END0 03_12 04_13 INT_L.SW6BEG0.EE4END0 04_13 05_12 +INT_L.SW6BEG0.LH12 05_12 07_13 INT_L.SW6BEG0.LOGIC_OUTS_L0 02_13 07_13 INT_L.SW6BEG0.LOGIC_OUTS_L12 03_12 07_13 INT_L.SW6BEG0.LOGIC_OUTS_L18 04_14 06_12 INT_L.SW6BEG0.LOGIC_OUTS_L22 06_12 07_13 INT_L.SW6BEG0.LOGIC_OUTS_L4 02_13 04_14 INT_L.SW6BEG0.LOGIC_OUTS_L8 03_12 04_14 +INT_L.SW6BEG0.LV_L0 04_14 05_12 INT_L.SW6BEG0.NW2END1 02_13 05_15 INT_L.SW6BEG0.NW6END1 05_15 06_12 INT_L.SW6BEG0.SE2END0 02_13 04_13 @@ -3118,12 +3258,14 @@ INT_L.SW6BEG0.WW2END0 03_12 05_15 INT_L.SW6BEG0.WW4END1 05_12 05_15 INT_L.SW6BEG1.EE2END1 03_28 04_29 INT_L.SW6BEG1.EE4END1 04_29 05_28 +INT_L.SW6BEG1.LH6 05_28 07_29 INT_L.SW6BEG1.LOGIC_OUTS_L1 02_29 04_30 INT_L.SW6BEG1.LOGIC_OUTS_L13 03_28 04_30 INT_L.SW6BEG1.LOGIC_OUTS_L19 06_28 07_29 INT_L.SW6BEG1.LOGIC_OUTS_L23 04_30 06_28 INT_L.SW6BEG1.LOGIC_OUTS_L5 02_29 07_29 INT_L.SW6BEG1.LOGIC_OUTS_L9 03_28 07_29 +INT_L.SW6BEG1.LV_L9 04_30 05_28 INT_L.SW6BEG1.NW2END2 02_29 05_31 INT_L.SW6BEG1.NW6END2 05_31 06_28 INT_L.SW6BEG1.SE2END1 02_29 04_29 @@ -3142,6 +3284,8 @@ INT_L.SW6BEG2.LOGIC_OUTS_L16 04_46 06_44 INT_L.SW6BEG2.LOGIC_OUTS_L2 02_45 07_45 INT_L.SW6BEG2.LOGIC_OUTS_L20 06_44 07_45 INT_L.SW6BEG2.LOGIC_OUTS_L6 02_45 04_46 +INT_L.SW6BEG2.LVB_L0 04_46 05_44 +INT_L.SW6BEG2.LVB_L12 05_44 07_45 INT_L.SW6BEG2.NW2END3 02_45 05_47 INT_L.SW6BEG2.NW6END3 05_47 06_44 INT_L.SW6BEG2.SE2END2 02_45 04_45 @@ -3154,12 +3298,14 @@ INT_L.SW6BEG2.WW2END2 03_44 05_47 INT_L.SW6BEG2.WW4END3 05_44 05_47 INT_L.SW6BEG3.EE2END3 03_60 04_61 INT_L.SW6BEG3.EE4END3 04_61 05_60 +INT_L.SW6BEG3.LH0 04_62 05_60 INT_L.SW6BEG3.LOGIC_OUTS_L11 03_60 07_61 INT_L.SW6BEG3.LOGIC_OUTS_L15 03_60 04_62 INT_L.SW6BEG3.LOGIC_OUTS_L17 06_60 07_61 INT_L.SW6BEG3.LOGIC_OUTS_L21 04_62 06_60 INT_L.SW6BEG3.LOGIC_OUTS_L3 02_61 04_62 INT_L.SW6BEG3.LOGIC_OUTS_L7 02_61 07_61 +INT_L.SW6BEG3.LV_L18 05_60 07_61 INT_L.SW6BEG3.NW2END_S0_0 02_61 05_63 INT_L.SW6BEG3.NW6END_S0_0 05_63 06_60 INT_L.SW6BEG3.SE2END3 02_61 04_61 @@ -3410,12 +3556,14 @@ INT_L.WW2BEG3.WL1END3 09_63 12_62 INT_L.WW2BEG3.WR1END_S1_0 09_62 12_62 INT_L.WW2BEG3.WW2END3 11_62 14_62 INT_L.WW2BEG3.WW4END_S0_0 11_62 13_62 +INT_L.WW4BEG0.LH12 05_00 07_01 INT_L.WW4BEG0.LOGIC_OUTS_L0 02_01 04_02 INT_L.WW4BEG0.LOGIC_OUTS_L12 03_00 04_02 INT_L.WW4BEG0.LOGIC_OUTS_L18 06_00 07_01 INT_L.WW4BEG0.LOGIC_OUTS_L22 04_02 06_00 INT_L.WW4BEG0.LOGIC_OUTS_L4 02_01 07_01 INT_L.WW4BEG0.LOGIC_OUTS_L8 03_00 07_01 +INT_L.WW4BEG0.LV_L0 04_02 05_00 INT_L.WW4BEG0.NE2END0 02_01 05_03 INT_L.WW4BEG0.NE6END0 05_00 05_03 INT_L.WW4BEG0.NN2END0 03_00 05_03 @@ -3428,12 +3576,14 @@ INT_L.WW4BEG0.SW2END_N0_3 02_01 04_01 INT_L.WW4BEG0.SW6END_N0_3 04_01 05_00 INT_L.WW4BEG0.WW2END_N0_3 03_00 03_01 INT_L.WW4BEG0.WW4END0 03_01 05_00 +INT_L.WW4BEG1.LH6 05_16 07_17 INT_L.WW4BEG1.LOGIC_OUTS_L1 02_17 07_17 INT_L.WW4BEG1.LOGIC_OUTS_L13 03_16 07_17 INT_L.WW4BEG1.LOGIC_OUTS_L19 04_18 06_16 INT_L.WW4BEG1.LOGIC_OUTS_L23 06_16 07_17 INT_L.WW4BEG1.LOGIC_OUTS_L5 02_17 04_18 INT_L.WW4BEG1.LOGIC_OUTS_L9 03_16 04_18 +INT_L.WW4BEG1.LV_L9 04_18 05_16 INT_L.WW4BEG1.NE2END1 02_17 05_19 INT_L.WW4BEG1.NE6END1 05_16 05_19 INT_L.WW4BEG1.NN2END1 03_16 05_19 @@ -3452,6 +3602,8 @@ INT_L.WW4BEG2.LOGIC_OUTS_L16 06_32 07_33 INT_L.WW4BEG2.LOGIC_OUTS_L2 02_33 04_34 INT_L.WW4BEG2.LOGIC_OUTS_L20 04_34 06_32 INT_L.WW4BEG2.LOGIC_OUTS_L6 02_33 07_33 +INT_L.WW4BEG2.LVB_L0 04_34 05_32 +INT_L.WW4BEG2.LVB_L12 05_32 07_33 INT_L.WW4BEG2.NE2END2 02_33 05_35 INT_L.WW4BEG2.NE6END2 05_32 05_35 INT_L.WW4BEG2.NN2END2 03_32 05_35 @@ -3464,12 +3616,14 @@ INT_L.WW4BEG2.SW2END1 02_33 04_33 INT_L.WW4BEG2.SW6END1 04_33 05_32 INT_L.WW4BEG2.WW2END1 03_32 03_33 INT_L.WW4BEG2.WW4END2 03_33 05_32 +INT_L.WW4BEG3.LH0 04_50 05_48 INT_L.WW4BEG3.LOGIC_OUTS_L11 03_48 04_50 INT_L.WW4BEG3.LOGIC_OUTS_L15 03_48 07_49 INT_L.WW4BEG3.LOGIC_OUTS_L17 04_50 06_48 INT_L.WW4BEG3.LOGIC_OUTS_L21 06_48 07_49 INT_L.WW4BEG3.LOGIC_OUTS_L3 02_49 07_49 INT_L.WW4BEG3.LOGIC_OUTS_L7 02_49 04_50 +INT_L.WW4BEG3.LV_L18 05_48 07_49 INT_L.WW4BEG3.NE2END3 02_49 05_51 INT_L.WW4BEG3.NE6END3 05_48 05_51 INT_L.WW4BEG3.NN2END3 03_48 05_51 diff --git a/kintex7/segbits_int_r.db b/kintex7/segbits_int_r.db index 002daa6..ca534dc 100644 --- a/kintex7/segbits_int_r.db +++ b/kintex7/segbits_int_r.db @@ -19,6 +19,7 @@ INT_R.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07 INT_R.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07 INT_R.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07 INT_R.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07 +INT_R.BYP_ALT0.VCC_WIRE !30_04 !30_58 !31_00 !31_01 !31_24 !31_25 !31_27 !31_35 !31_36 !31_38 !31_60 !31_61 31_02 31_26 31_37 31_62 INT_R.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07 INT_R.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07 INT_R.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07 @@ -43,6 +44,7 @@ INT_R.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15 INT_R.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15 INT_R.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15 INT_R.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15 +INT_R.BYP_ALT1.VCC_WIRE !30_00 !30_01 !30_03 !30_24 !30_26 !30_27 !30_35 !30_36 !30_38 !30_59 !30_61 !30_62 30_02 30_25 30_37 30_60 INT_R.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15 INT_R.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15 INT_R.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15 @@ -336,12 +338,14 @@ INT_R.EE2BEG3.SS2END3 09_55 14_54 INT_R.EE2BEG3.SS6END3 09_55 13_54 INT_R.EE4BEG0.EE2END0 03_08 03_09 INT_R.EE4BEG0.EE4END0 03_09 05_08 +INT_R.EE4BEG0.LH12 05_08 07_09 INT_R.EE4BEG0.LOGIC_OUTS0 02_09 04_10 INT_R.EE4BEG0.LOGIC_OUTS12 03_08 04_10 INT_R.EE4BEG0.LOGIC_OUTS18 06_08 07_09 INT_R.EE4BEG0.LOGIC_OUTS22 04_10 06_08 INT_R.EE4BEG0.LOGIC_OUTS4 02_09 07_09 INT_R.EE4BEG0.LOGIC_OUTS8 03_08 07_09 +INT_R.EE4BEG0.LV0 04_10 05_08 INT_R.EE4BEG0.NE2END0 02_09 04_09 INT_R.EE4BEG0.NE6END0 04_09 05_08 INT_R.EE4BEG0.NN2END0 03_08 04_09 @@ -354,12 +358,14 @@ INT_R.EE4BEG0.SW2END0 02_09 05_11 INT_R.EE4BEG0.SW6END0 05_08 05_11 INT_R.EE4BEG1.EE2END1 03_24 03_25 INT_R.EE4BEG1.EE4END1 03_25 05_24 +INT_R.EE4BEG1.LH6 05_24 07_25 INT_R.EE4BEG1.LOGIC_OUTS1 02_25 07_25 INT_R.EE4BEG1.LOGIC_OUTS13 03_24 07_25 INT_R.EE4BEG1.LOGIC_OUTS19 04_26 06_24 INT_R.EE4BEG1.LOGIC_OUTS23 06_24 07_25 INT_R.EE4BEG1.LOGIC_OUTS5 02_25 04_26 INT_R.EE4BEG1.LOGIC_OUTS9 03_24 04_26 +INT_R.EE4BEG1.LV9 04_26 05_24 INT_R.EE4BEG1.NE2END1 02_25 04_25 INT_R.EE4BEG1.NE6END1 04_25 05_24 INT_R.EE4BEG1.NN2END1 03_24 04_25 @@ -378,6 +384,8 @@ INT_R.EE4BEG2.LOGIC_OUTS16 06_40 07_41 INT_R.EE4BEG2.LOGIC_OUTS2 02_41 04_42 INT_R.EE4BEG2.LOGIC_OUTS20 04_42 06_40 INT_R.EE4BEG2.LOGIC_OUTS6 02_41 07_41 +INT_R.EE4BEG2.LVB0 04_42 05_40 +INT_R.EE4BEG2.LVB12 05_40 07_41 INT_R.EE4BEG2.NE2END2 02_41 04_41 INT_R.EE4BEG2.NE6END2 04_41 05_40 INT_R.EE4BEG2.NN2END2 03_40 04_41 @@ -390,12 +398,14 @@ INT_R.EE4BEG2.SW2END2 02_41 05_43 INT_R.EE4BEG2.SW6END2 05_40 05_43 INT_R.EE4BEG3.EE2END3 03_56 03_57 INT_R.EE4BEG3.EE4END3 03_57 05_56 +INT_R.EE4BEG3.LH0 04_58 05_56 INT_R.EE4BEG3.LOGIC_OUTS11 03_56 04_58 INT_R.EE4BEG3.LOGIC_OUTS15 03_56 07_57 INT_R.EE4BEG3.LOGIC_OUTS17 04_58 06_56 INT_R.EE4BEG3.LOGIC_OUTS21 06_56 07_57 INT_R.EE4BEG3.LOGIC_OUTS3 02_57 07_57 INT_R.EE4BEG3.LOGIC_OUTS7 02_57 04_58 +INT_R.EE4BEG3.LV18 05_56 07_57 INT_R.EE4BEG3.NE2END3 02_57 04_57 INT_R.EE4BEG3.NE6END3 04_57 05_56 INT_R.EE4BEG3.NN2END3 03_56 04_57 @@ -597,6 +607,7 @@ INT_R.FAN_ALT1.EL1END3 !22_48 17_48 23_48 24_48 25_48 INT_R.FAN_ALT1.ER1END2 !23_48 16_48 22_48 24_48 25_48 INT_R.FAN_ALT1.FAN_BOUNCE3 !22_48 20_48 23_48 24_48 25_48 INT_R.FAN_ALT1.FAN_BOUNCE_S3_4 !23_48 20_48 22_48 24_48 25_48 +INT_R.FAN_ALT1.GFAN1 !00_18 !00_19 !01_13 !22_48 !23_48 !24_48 00_14 00_17 21_48 25_48 INT_R.FAN_ALT1.LOGIC_OUTS11 !22_48 21_48 23_48 24_48 25_48 INT_R.FAN_ALT1.LOGIC_OUTS17 !22_48 !23_48 !25_48 21_48 24_48 INT_R.FAN_ALT1.LOGIC_OUTS7 !23_48 21_48 22_48 24_48 25_48 @@ -692,6 +703,7 @@ INT_R.FAN_ALT5.EL1END2 !22_40 16_40 23_40 24_40 25_40 INT_R.FAN_ALT5.ER1END2 !23_40 17_40 22_40 24_40 25_40 INT_R.FAN_ALT5.FAN_BOUNCE1 !22_40 20_40 23_40 24_40 25_40 INT_R.FAN_ALT5.FAN_BOUNCE_S3_0 !23_40 20_40 22_40 24_40 25_40 +INT_R.FAN_ALT5.GFAN1 !22_40 !23_40 !24_40 21_40 25_40 INT_R.FAN_ALT5.LOGIC_OUTS10 !22_40 21_40 23_40 24_40 25_40 INT_R.FAN_ALT5.LOGIC_OUTS16 !22_40 !23_40 !25_40 21_40 24_40 INT_R.FAN_ALT5.LOGIC_OUTS6 !23_40 21_40 22_40 24_40 25_40 @@ -769,6 +781,7 @@ INT_R.GFAN0.GCLK_B6 !00_10 !00_11 !01_09 01_10 01_18 INT_R.GFAN0.GCLK_B7 !00_10 !01_09 !01_10 00_11 01_18 INT_R.GFAN0.GCLK_B8 !01_09 00_10 00_11 01_10 01_16 INT_R.GFAN0.GCLK_B9 !00_10 00_11 01_09 01_10 01_16 +INT_R.GFAN0.GND_WIRE !00_10 !01_09 !01_10 00_11 01_14 INT_R.GFAN0.NR1END1 !00_10 00_11 01_09 01_10 01_14 INT_R.GFAN0.WW4END1 !00_10 !00_11 !01_09 01_10 01_14 INT_R.GFAN1.BYP_BOUNCE1 !00_19 00_14 00_17 00_18 01_13 @@ -784,6 +797,7 @@ INT_R.GFAN1.GCLK_B6 !00_18 !00_19 !01_13 00_14 00_15 INT_R.GFAN1.GCLK_B7 !00_14 !00_18 !00_19 00_15 01_13 INT_R.GFAN1.GCLK_B8 !00_19 00_14 00_18 01_13 01_17 INT_R.GFAN1.GCLK_B9 !00_18 00_14 00_19 01_13 01_17 +INT_R.GFAN1.GND_WIRE !00_14 !00_18 !00_19 00_17 01_13 INT_R.GFAN1.NR1END1 !00_18 00_14 00_17 00_19 01_13 INT_R.GFAN1.WW4END1 !00_18 !00_19 !01_13 00_14 00_17 INT_R.IMUX0.BYP_BOUNCE_N3_2 !22_01 !23_01 !24_01 21_01 25_01 @@ -1938,6 +1952,90 @@ INT_R.IMUX9.SW2END0 !22_10 !23_10 !25_10 17_10 24_10 INT_R.IMUX9.WL1END0 !22_10 18_11 23_10 24_10 25_10 INT_R.IMUX9.WR1END0 !23_10 17_10 22_10 24_10 25_10 INT_R.IMUX9.WW2END0 !22_10 !23_10 !24_10 18_11 25_10 +INT_R.LH0.EE4END3 00_58 01_61 +INT_R.LH0.ER1END3 00_57 01_54 +INT_R.LH0.LH12 01_54 01_56 +INT_R.LH0.LV0 01_56 01_58 +INT_R.LH0.LV18 01_56 01_61 +INT_R.LH0.LV9 00_59 01_56 +INT_R.LH0.NE2END3 00_58 00_59 +INT_R.LH0.NE6END3 00_58 01_58 +INT_R.LH0.NW2END3 00_58 01_54 +INT_R.LH0.SR1END3 00_57 00_59 +INT_R.LH0.SS6END3 00_57 01_58 +INT_R.LH0.SW6END3 00_57 01_61 +INT_R.LH12.EE4END3 01_60 01_62 +INT_R.LH12.ER1END3 00_63 01_60 +INT_R.LH12.LH0 00_61 00_63 +INT_R.LH12.LV0 00_55 00_62 +INT_R.LH12.LV18 00_62 01_62 +INT_R.LH12.LV9 00_62 01_57 +INT_R.LH12.NE2END3 01_57 01_60 +INT_R.LH12.NE6END3 00_55 01_60 +INT_R.LH12.NW2END3 00_62 00_63 +INT_R.LH12.SR1END3 00_61 01_57 +INT_R.LH12.SS6END3 00_55 00_61 +INT_R.LH12.SW6END3 00_61 01_62 +INT_R.LV0.ER1END0 01_04 01_05 +INT_R.LV0.LH0 00_02 01_06 +INT_R.LV0.LH12 00_05 01_06 +INT_R.LV0.LH6 01_04 01_06 +INT_R.LV0.LV18 00_09 01_06 +INT_R.LV0.NN6END0 00_07 00_09 +INT_R.LV0.NR1END0 00_02 01_05 +INT_R.LV0.NW6END0 00_07 01_04 +INT_R.LV0.SR1BEG_S0 00_05 01_05 +INT_R.LV0.SW6END0 00_09 01_05 +INT_R.LV0.WR1END0 00_02 00_07 +INT_R.LV0.WW4END0 00_05 00_07 +INT_R.LV18.ER1END0 00_03 00_06 +INT_R.LV18.LH0 00_01 01_02 +INT_R.LV18.LH12 01_02 01_08 +INT_R.LV18.LH6 00_06 01_02 +INT_R.LV18.LV0 01_00 01_01 +INT_R.LV18.NN6END0 00_03 01_00 +INT_R.LV18.NR1END0 00_01 00_03 +INT_R.LV18.NW6END0 00_06 01_01 +INT_R.LV18.SR1BEG_S0 00_03 01_08 +INT_R.LV18.SW6END0 01_00 01_02 +INT_R.LV18.WR1END0 00_01 01_01 +INT_R.LV18.WW4END0 01_01 01_08 +INT_R.LVB0.LH0 00_43 00_51 +INT_R.LVB0.LH12 00_50 00_51 +INT_R.LVB0.LH6 00_51 00_53 +INT_R.LVB0.LV0 00_47 01_52 +INT_R.LVB0.LV18 01_42 01_52 +INT_R.LVB0.LVB12 00_51 00_54 +INT_R.LVB0.NE2END2 00_53 01_52 +INT_R.LVB0.NN6END3 00_50 01_50 +INT_R.LVB0.NR1END3 00_47 01_50 +INT_R.LVB0.NW2END2 00_43 01_52 +INT_R.LVB0.NW6END3 00_43 01_50 +INT_R.LVB0.SE2END3 00_51 01_42 +INT_R.LVB0.SE6END3 00_54 01_50 +INT_R.LVB0.SW2END2 00_50 01_52 +INT_R.LVB0.SW2END3 00_47 00_51 +INT_R.LVB0.SW6END2 00_54 01_52 +INT_R.LVB0.WR1END3 01_42 01_50 +INT_R.LVB0.WW4END3 00_53 01_50 +INT_R.LVB12.LH0 00_46 00_49 +INT_R.LVB12.LH12 00_46 01_53 +INT_R.LVB12.LH6 00_46 01_49 +INT_R.LVB12.LV0 00_45 01_44 +INT_R.LVB12.LV18 00_45 01_48 +INT_R.LVB12.LVB0 00_45 01_45 +INT_R.LVB12.NE2END2 00_45 01_49 +INT_R.LVB12.NN6END3 01_46 01_53 +INT_R.LVB12.NR1END3 01_44 01_46 +INT_R.LVB12.NW2END2 00_45 00_49 +INT_R.LVB12.NW6END3 00_49 01_46 +INT_R.LVB12.SE2END3 00_46 01_48 +INT_R.LVB12.SE6END3 00_46 01_45 +INT_R.LVB12.SW2END2 00_45 01_53 +INT_R.LVB12.SW2END3 00_46 01_44 +INT_R.LVB12.SW6END2 01_45 01_46 +INT_R.LVB12.WR1END3 01_46 01_48 +INT_R.LVB12.WW4END3 01_46 01_49 INT_R.NE2BEG0.EE2END0 09_04 14_04 INT_R.NE2BEG0.EE4END0 09_04 13_04 INT_R.NE2BEG0.EL1END0 09_05 12_04 @@ -2020,12 +2118,14 @@ INT_R.NE2BEG3.SE2END3 09_53 14_52 INT_R.NE2BEG3.SE6END3 09_53 13_52 INT_R.NE6BEG0.EE2END0 03_04 05_07 INT_R.NE6BEG0.EE4END0 05_04 05_07 +INT_R.NE6BEG0.LH12 05_04 07_05 INT_R.NE6BEG0.LOGIC_OUTS0 02_05 07_05 INT_R.NE6BEG0.LOGIC_OUTS12 03_04 07_05 INT_R.NE6BEG0.LOGIC_OUTS18 04_06 06_04 INT_R.NE6BEG0.LOGIC_OUTS22 06_04 07_05 INT_R.NE6BEG0.LOGIC_OUTS4 02_05 04_06 INT_R.NE6BEG0.LOGIC_OUTS8 03_04 04_06 +INT_R.NE6BEG0.LV0 04_06 05_04 INT_R.NE6BEG0.NE2END0 02_05 03_05 INT_R.NE6BEG0.NE6END0 03_05 05_04 INT_R.NE6BEG0.NN2END0 03_04 03_05 @@ -2038,12 +2138,14 @@ INT_R.NE6BEG0.WW2END_N0_3 03_04 04_05 INT_R.NE6BEG0.WW4END0 04_05 05_04 INT_R.NE6BEG1.EE2END1 03_20 05_23 INT_R.NE6BEG1.EE4END1 05_20 05_23 +INT_R.NE6BEG1.LH6 05_20 07_21 INT_R.NE6BEG1.LOGIC_OUTS1 02_21 04_22 INT_R.NE6BEG1.LOGIC_OUTS13 03_20 04_22 INT_R.NE6BEG1.LOGIC_OUTS19 06_20 07_21 INT_R.NE6BEG1.LOGIC_OUTS23 04_22 06_20 INT_R.NE6BEG1.LOGIC_OUTS5 02_21 07_21 INT_R.NE6BEG1.LOGIC_OUTS9 03_20 07_21 +INT_R.NE6BEG1.LV9 04_22 05_20 INT_R.NE6BEG1.NE2END1 02_21 03_21 INT_R.NE6BEG1.NE6END1 03_21 05_20 INT_R.NE6BEG1.NN2END1 03_20 03_21 @@ -2062,6 +2164,8 @@ INT_R.NE6BEG2.LOGIC_OUTS16 04_38 06_36 INT_R.NE6BEG2.LOGIC_OUTS2 02_37 07_37 INT_R.NE6BEG2.LOGIC_OUTS20 06_36 07_37 INT_R.NE6BEG2.LOGIC_OUTS6 02_37 04_38 +INT_R.NE6BEG2.LVB0 04_38 05_36 +INT_R.NE6BEG2.LVB12 05_36 07_37 INT_R.NE6BEG2.NE2END2 02_37 03_37 INT_R.NE6BEG2.NE6END2 03_37 05_36 INT_R.NE6BEG2.NN2END2 03_36 03_37 @@ -2074,12 +2178,14 @@ INT_R.NE6BEG2.WW2END1 03_36 04_37 INT_R.NE6BEG2.WW4END2 04_37 05_36 INT_R.NE6BEG3.EE2END3 03_52 05_55 INT_R.NE6BEG3.EE4END3 05_52 05_55 +INT_R.NE6BEG3.LH0 04_54 05_52 INT_R.NE6BEG3.LOGIC_OUTS11 03_52 07_53 INT_R.NE6BEG3.LOGIC_OUTS15 03_52 04_54 INT_R.NE6BEG3.LOGIC_OUTS17 06_52 07_53 INT_R.NE6BEG3.LOGIC_OUTS21 04_54 06_52 INT_R.NE6BEG3.LOGIC_OUTS3 02_53 04_54 INT_R.NE6BEG3.LOGIC_OUTS7 02_53 07_53 +INT_R.NE6BEG3.LV18 05_52 07_53 INT_R.NE6BEG3.NE2END3 02_53 03_53 INT_R.NE6BEG3.NE6END3 03_53 05_52 INT_R.NE6BEG3.NN2END3 03_52 03_53 @@ -2252,12 +2358,14 @@ INT_R.NN2BEG3.WW2END2 10_50 14_50 INT_R.NN2BEG3.WW4END3 10_50 13_50 INT_R.NN6BEG0.EE2END0 02_07 05_06 INT_R.NN6BEG0.EE4END0 04_07 05_06 +INT_R.NN6BEG0.LH12 04_07 05_05 INT_R.NN6BEG0.LOGIC_OUTS0 03_06 05_05 INT_R.NN6BEG0.LOGIC_OUTS12 02_07 05_05 INT_R.NN6BEG0.LOGIC_OUTS18 06_06 07_07 INT_R.NN6BEG0.LOGIC_OUTS22 05_05 07_07 INT_R.NN6BEG0.LOGIC_OUTS4 03_06 06_06 INT_R.NN6BEG0.LOGIC_OUTS8 02_07 06_06 +INT_R.NN6BEG0.LV0 04_07 06_06 INT_R.NN6BEG0.NE2END0 02_06 03_06 INT_R.NN6BEG0.NE6END0 02_06 04_07 INT_R.NN6BEG0.NN2END0 02_06 02_07 @@ -2270,12 +2378,14 @@ INT_R.NN6BEG0.WW2END_N0_3 02_07 04_04 INT_R.NN6BEG0.WW4END0 04_04 04_07 INT_R.NN6BEG1.EE2END1 02_23 05_22 INT_R.NN6BEG1.EE4END1 04_23 05_22 +INT_R.NN6BEG1.LH6 04_23 05_21 INT_R.NN6BEG1.LOGIC_OUTS1 03_22 06_22 INT_R.NN6BEG1.LOGIC_OUTS13 02_23 06_22 INT_R.NN6BEG1.LOGIC_OUTS19 05_21 07_23 INT_R.NN6BEG1.LOGIC_OUTS23 06_22 07_23 INT_R.NN6BEG1.LOGIC_OUTS5 03_22 05_21 INT_R.NN6BEG1.LOGIC_OUTS9 02_23 05_21 +INT_R.NN6BEG1.LV9 04_23 06_22 INT_R.NN6BEG1.NE2END1 02_22 03_22 INT_R.NN6BEG1.NE6END1 02_22 04_23 INT_R.NN6BEG1.NN2END1 02_22 02_23 @@ -2294,6 +2404,8 @@ INT_R.NN6BEG2.LOGIC_OUTS16 06_38 07_39 INT_R.NN6BEG2.LOGIC_OUTS2 03_38 05_37 INT_R.NN6BEG2.LOGIC_OUTS20 05_37 07_39 INT_R.NN6BEG2.LOGIC_OUTS6 03_38 06_38 +INT_R.NN6BEG2.LVB0 04_39 06_38 +INT_R.NN6BEG2.LVB12 04_39 05_37 INT_R.NN6BEG2.NE2END2 02_38 03_38 INT_R.NN6BEG2.NE6END2 02_38 04_39 INT_R.NN6BEG2.NN2END2 02_38 02_39 @@ -2306,12 +2418,14 @@ INT_R.NN6BEG2.WW2END1 02_39 04_36 INT_R.NN6BEG2.WW4END2 04_36 04_39 INT_R.NN6BEG3.EE2END3 02_55 05_54 INT_R.NN6BEG3.EE4END3 04_55 05_54 +INT_R.NN6BEG3.LH0 04_55 06_54 INT_R.NN6BEG3.LOGIC_OUTS11 02_55 05_53 INT_R.NN6BEG3.LOGIC_OUTS15 02_55 06_54 INT_R.NN6BEG3.LOGIC_OUTS17 05_53 07_55 INT_R.NN6BEG3.LOGIC_OUTS21 06_54 07_55 INT_R.NN6BEG3.LOGIC_OUTS3 03_54 06_54 INT_R.NN6BEG3.LOGIC_OUTS7 03_54 05_53 +INT_R.NN6BEG3.LV18 04_55 05_53 INT_R.NN6BEG3.NE2END3 02_54 03_54 INT_R.NN6BEG3.NE6END3 02_54 04_55 INT_R.NN6BEG3.NN2END3 02_54 02_55 @@ -2482,12 +2596,14 @@ INT_R.NW2BEG3.WL1END2 10_48 12_48 INT_R.NW2BEG3.WR1END3 09_48 12_48 INT_R.NW2BEG3.WW2END2 06_49 14_48 INT_R.NW2BEG3.WW4END3 06_49 13_48 +INT_R.NW6BEG0.LH12 04_03 05_01 INT_R.NW6BEG0.LOGIC_OUTS0 03_02 06_02 INT_R.NW6BEG0.LOGIC_OUTS12 02_03 06_02 INT_R.NW6BEG0.LOGIC_OUTS18 05_01 07_03 INT_R.NW6BEG0.LOGIC_OUTS22 06_02 07_03 INT_R.NW6BEG0.LOGIC_OUTS4 03_02 05_01 INT_R.NW6BEG0.LOGIC_OUTS8 02_03 05_01 +INT_R.NW6BEG0.LV0 04_03 06_02 INT_R.NW6BEG0.NE2END0 03_02 05_02 INT_R.NW6BEG0.NE6END0 04_03 05_02 INT_R.NW6BEG0.NN2END0 02_03 05_02 @@ -2500,12 +2616,14 @@ INT_R.NW6BEG0.SW2END_N0_3 03_02 04_00 INT_R.NW6BEG0.SW6END_N0_3 04_00 04_03 INT_R.NW6BEG0.WW2END_N0_3 02_02 02_03 INT_R.NW6BEG0.WW4END0 02_02 04_03 +INT_R.NW6BEG1.LH6 04_19 05_17 INT_R.NW6BEG1.LOGIC_OUTS1 03_18 05_17 INT_R.NW6BEG1.LOGIC_OUTS13 02_19 05_17 INT_R.NW6BEG1.LOGIC_OUTS19 06_18 07_19 INT_R.NW6BEG1.LOGIC_OUTS23 05_17 07_19 INT_R.NW6BEG1.LOGIC_OUTS5 03_18 06_18 INT_R.NW6BEG1.LOGIC_OUTS9 02_19 06_18 +INT_R.NW6BEG1.LV9 04_19 06_18 INT_R.NW6BEG1.NE2END1 03_18 05_18 INT_R.NW6BEG1.NE6END1 04_19 05_18 INT_R.NW6BEG1.NN2END1 02_19 05_18 @@ -2524,6 +2642,8 @@ INT_R.NW6BEG2.LOGIC_OUTS16 05_33 07_35 INT_R.NW6BEG2.LOGIC_OUTS2 03_34 06_34 INT_R.NW6BEG2.LOGIC_OUTS20 06_34 07_35 INT_R.NW6BEG2.LOGIC_OUTS6 03_34 05_33 +INT_R.NW6BEG2.LVB0 04_35 06_34 +INT_R.NW6BEG2.LVB12 04_35 05_33 INT_R.NW6BEG2.NE2END2 03_34 05_34 INT_R.NW6BEG2.NE6END2 04_35 05_34 INT_R.NW6BEG2.NN2END2 02_35 05_34 @@ -2536,12 +2656,14 @@ INT_R.NW6BEG2.SW2END1 03_34 04_32 INT_R.NW6BEG2.SW6END1 04_32 04_35 INT_R.NW6BEG2.WW2END1 02_34 02_35 INT_R.NW6BEG2.WW4END2 02_34 04_35 +INT_R.NW6BEG3.LH0 04_51 06_50 INT_R.NW6BEG3.LOGIC_OUTS11 02_51 06_50 INT_R.NW6BEG3.LOGIC_OUTS15 02_51 05_49 INT_R.NW6BEG3.LOGIC_OUTS17 06_50 07_51 INT_R.NW6BEG3.LOGIC_OUTS21 05_49 07_51 INT_R.NW6BEG3.LOGIC_OUTS3 03_50 05_49 INT_R.NW6BEG3.LOGIC_OUTS7 03_50 06_50 +INT_R.NW6BEG3.LV18 04_51 05_49 INT_R.NW6BEG3.NE2END3 03_50 05_50 INT_R.NW6BEG3.NE6END3 04_51 05_50 INT_R.NW6BEG3.NN2END3 02_51 05_50 @@ -2636,12 +2758,14 @@ INT_R.SE2BEG3.SW2END3 09_57 14_56 INT_R.SE2BEG3.SW6END3 09_57 13_56 INT_R.SE6BEG0.EE2END0 02_10 02_11 INT_R.SE6BEG0.EE4END0 02_10 04_11 +INT_R.SE6BEG0.LH12 04_11 05_09 INT_R.SE6BEG0.LOGIC_OUTS0 03_10 06_10 INT_R.SE6BEG0.LOGIC_OUTS12 02_11 06_10 INT_R.SE6BEG0.LOGIC_OUTS18 05_09 07_11 INT_R.SE6BEG0.LOGIC_OUTS22 06_10 07_11 INT_R.SE6BEG0.LOGIC_OUTS4 03_10 05_09 INT_R.SE6BEG0.LOGIC_OUTS8 02_11 05_09 +INT_R.SE6BEG0.LV0 04_11 06_10 INT_R.SE6BEG0.NE2END0 03_10 04_08 INT_R.SE6BEG0.NE6END0 04_08 04_11 INT_R.SE6BEG0.NN2END0 02_11 04_08 @@ -2654,12 +2778,14 @@ INT_R.SE6BEG0.SW2END0 03_10 05_10 INT_R.SE6BEG0.SW6END0 04_11 05_10 INT_R.SE6BEG1.EE2END1 02_26 02_27 INT_R.SE6BEG1.EE4END1 02_26 04_27 +INT_R.SE6BEG1.LH6 04_27 05_25 INT_R.SE6BEG1.LOGIC_OUTS1 03_26 05_25 INT_R.SE6BEG1.LOGIC_OUTS13 02_27 05_25 INT_R.SE6BEG1.LOGIC_OUTS19 06_26 07_27 INT_R.SE6BEG1.LOGIC_OUTS23 05_25 07_27 INT_R.SE6BEG1.LOGIC_OUTS5 03_26 06_26 INT_R.SE6BEG1.LOGIC_OUTS9 02_27 06_26 +INT_R.SE6BEG1.LV9 04_27 06_26 INT_R.SE6BEG1.NE2END1 03_26 04_24 INT_R.SE6BEG1.NE6END1 04_24 04_27 INT_R.SE6BEG1.NN2END1 02_27 04_24 @@ -2678,6 +2804,8 @@ INT_R.SE6BEG2.LOGIC_OUTS16 05_41 07_43 INT_R.SE6BEG2.LOGIC_OUTS2 03_42 06_42 INT_R.SE6BEG2.LOGIC_OUTS20 06_42 07_43 INT_R.SE6BEG2.LOGIC_OUTS6 03_42 05_41 +INT_R.SE6BEG2.LVB0 04_43 06_42 +INT_R.SE6BEG2.LVB12 04_43 05_41 INT_R.SE6BEG2.NE2END2 03_42 04_40 INT_R.SE6BEG2.NE6END2 04_40 04_43 INT_R.SE6BEG2.NN2END2 02_43 04_40 @@ -2690,12 +2818,14 @@ INT_R.SE6BEG2.SW2END2 03_42 05_42 INT_R.SE6BEG2.SW6END2 04_43 05_42 INT_R.SE6BEG3.EE2END3 02_58 02_59 INT_R.SE6BEG3.EE4END3 02_58 04_59 +INT_R.SE6BEG3.LH0 04_59 06_58 INT_R.SE6BEG3.LOGIC_OUTS11 02_59 06_58 INT_R.SE6BEG3.LOGIC_OUTS15 02_59 05_57 INT_R.SE6BEG3.LOGIC_OUTS17 06_58 07_59 INT_R.SE6BEG3.LOGIC_OUTS21 05_57 07_59 INT_R.SE6BEG3.LOGIC_OUTS3 03_58 05_57 INT_R.SE6BEG3.LOGIC_OUTS7 03_58 06_58 +INT_R.SE6BEG3.LV18 04_59 05_57 INT_R.SE6BEG3.NE2END3 03_58 04_56 INT_R.SE6BEG3.NE6END3 04_56 04_59 INT_R.SE6BEG3.NN2END3 02_59 04_56 @@ -2948,12 +3078,14 @@ INT_R.SS2BEG3.WW2END3 09_59 14_58 INT_R.SS2BEG3.WW4END_S0_0 09_59 13_58 INT_R.SS6BEG0.EE2END0 02_15 04_12 INT_R.SS6BEG0.EE4END0 04_12 04_15 +INT_R.SS6BEG0.LH12 04_15 05_13 INT_R.SS6BEG0.LOGIC_OUTS0 03_14 05_13 INT_R.SS6BEG0.LOGIC_OUTS12 02_15 05_13 INT_R.SS6BEG0.LOGIC_OUTS18 06_14 07_15 INT_R.SS6BEG0.LOGIC_OUTS22 05_13 07_15 INT_R.SS6BEG0.LOGIC_OUTS4 03_14 06_14 INT_R.SS6BEG0.LOGIC_OUTS8 02_15 06_14 +INT_R.SS6BEG0.LV0 04_15 06_14 INT_R.SS6BEG0.NW2END1 03_14 05_14 INT_R.SS6BEG0.NW6END1 05_14 07_15 INT_R.SS6BEG0.SE2END0 03_14 04_12 @@ -2966,12 +3098,14 @@ INT_R.SS6BEG0.WW2END0 02_15 05_14 INT_R.SS6BEG0.WW4END1 04_15 05_14 INT_R.SS6BEG1.EE2END1 02_31 04_28 INT_R.SS6BEG1.EE4END1 04_28 04_31 +INT_R.SS6BEG1.LH6 04_31 05_29 INT_R.SS6BEG1.LOGIC_OUTS1 03_30 06_30 INT_R.SS6BEG1.LOGIC_OUTS13 02_31 06_30 INT_R.SS6BEG1.LOGIC_OUTS19 05_29 07_31 INT_R.SS6BEG1.LOGIC_OUTS23 06_30 07_31 INT_R.SS6BEG1.LOGIC_OUTS5 03_30 05_29 INT_R.SS6BEG1.LOGIC_OUTS9 02_31 05_29 +INT_R.SS6BEG1.LV9 04_31 06_30 INT_R.SS6BEG1.NW2END2 03_30 05_30 INT_R.SS6BEG1.NW6END2 05_30 07_31 INT_R.SS6BEG1.SE2END1 03_30 04_28 @@ -2990,6 +3124,8 @@ INT_R.SS6BEG2.LOGIC_OUTS16 06_46 07_47 INT_R.SS6BEG2.LOGIC_OUTS2 03_46 05_45 INT_R.SS6BEG2.LOGIC_OUTS20 05_45 07_47 INT_R.SS6BEG2.LOGIC_OUTS6 03_46 06_46 +INT_R.SS6BEG2.LVB0 04_47 06_46 +INT_R.SS6BEG2.LVB12 04_47 05_45 INT_R.SS6BEG2.NW2END3 03_46 05_46 INT_R.SS6BEG2.NW6END3 05_46 07_47 INT_R.SS6BEG2.SE2END2 03_46 04_44 @@ -3002,12 +3138,14 @@ INT_R.SS6BEG2.WW2END2 02_47 05_46 INT_R.SS6BEG2.WW4END3 04_47 05_46 INT_R.SS6BEG3.EE2END3 02_63 04_60 INT_R.SS6BEG3.EE4END3 04_60 04_63 +INT_R.SS6BEG3.LH0 04_63 06_62 INT_R.SS6BEG3.LOGIC_OUTS11 02_63 05_61 INT_R.SS6BEG3.LOGIC_OUTS15 02_63 06_62 INT_R.SS6BEG3.LOGIC_OUTS17 05_61 07_63 INT_R.SS6BEG3.LOGIC_OUTS21 06_62 07_63 INT_R.SS6BEG3.LOGIC_OUTS3 03_62 06_62 INT_R.SS6BEG3.LOGIC_OUTS7 03_62 05_61 +INT_R.SS6BEG3.LV18 04_63 05_61 INT_R.SS6BEG3.NW2END_S0_0 03_62 05_62 INT_R.SS6BEG3.NW6END_S0_0 05_62 07_63 INT_R.SS6BEG3.SE2END3 03_62 04_60 @@ -3100,12 +3238,14 @@ INT_R.SW2BEG3.WW2END3 09_60 14_60 INT_R.SW2BEG3.WW4END_S0_0 09_60 13_60 INT_R.SW6BEG0.EE2END0 03_12 04_13 INT_R.SW6BEG0.EE4END0 04_13 05_12 +INT_R.SW6BEG0.LH12 05_12 07_13 INT_R.SW6BEG0.LOGIC_OUTS0 02_13 07_13 INT_R.SW6BEG0.LOGIC_OUTS12 03_12 07_13 INT_R.SW6BEG0.LOGIC_OUTS18 04_14 06_12 INT_R.SW6BEG0.LOGIC_OUTS22 06_12 07_13 INT_R.SW6BEG0.LOGIC_OUTS4 02_13 04_14 INT_R.SW6BEG0.LOGIC_OUTS8 03_12 04_14 +INT_R.SW6BEG0.LV0 04_14 05_12 INT_R.SW6BEG0.NW2END1 02_13 05_15 INT_R.SW6BEG0.NW6END1 05_15 06_12 INT_R.SW6BEG0.SE2END0 02_13 04_13 @@ -3118,12 +3258,14 @@ INT_R.SW6BEG0.WW2END0 03_12 05_15 INT_R.SW6BEG0.WW4END1 05_12 05_15 INT_R.SW6BEG1.EE2END1 03_28 04_29 INT_R.SW6BEG1.EE4END1 04_29 05_28 +INT_R.SW6BEG1.LH6 05_28 07_29 INT_R.SW6BEG1.LOGIC_OUTS1 02_29 04_30 INT_R.SW6BEG1.LOGIC_OUTS13 03_28 04_30 INT_R.SW6BEG1.LOGIC_OUTS19 06_28 07_29 INT_R.SW6BEG1.LOGIC_OUTS23 04_30 06_28 INT_R.SW6BEG1.LOGIC_OUTS5 02_29 07_29 INT_R.SW6BEG1.LOGIC_OUTS9 03_28 07_29 +INT_R.SW6BEG1.LV9 04_30 05_28 INT_R.SW6BEG1.NW2END2 02_29 05_31 INT_R.SW6BEG1.NW6END2 05_31 06_28 INT_R.SW6BEG1.SE2END1 02_29 04_29 @@ -3142,6 +3284,8 @@ INT_R.SW6BEG2.LOGIC_OUTS16 04_46 06_44 INT_R.SW6BEG2.LOGIC_OUTS2 02_45 07_45 INT_R.SW6BEG2.LOGIC_OUTS20 06_44 07_45 INT_R.SW6BEG2.LOGIC_OUTS6 02_45 04_46 +INT_R.SW6BEG2.LVB0 04_46 05_44 +INT_R.SW6BEG2.LVB12 05_44 07_45 INT_R.SW6BEG2.NW2END3 02_45 05_47 INT_R.SW6BEG2.NW6END3 05_47 06_44 INT_R.SW6BEG2.SE2END2 02_45 04_45 @@ -3154,12 +3298,14 @@ INT_R.SW6BEG2.WW2END2 03_44 05_47 INT_R.SW6BEG2.WW4END3 05_44 05_47 INT_R.SW6BEG3.EE2END3 03_60 04_61 INT_R.SW6BEG3.EE4END3 04_61 05_60 +INT_R.SW6BEG3.LH0 04_62 05_60 INT_R.SW6BEG3.LOGIC_OUTS11 03_60 07_61 INT_R.SW6BEG3.LOGIC_OUTS15 03_60 04_62 INT_R.SW6BEG3.LOGIC_OUTS17 06_60 07_61 INT_R.SW6BEG3.LOGIC_OUTS21 04_62 06_60 INT_R.SW6BEG3.LOGIC_OUTS3 02_61 04_62 INT_R.SW6BEG3.LOGIC_OUTS7 02_61 07_61 +INT_R.SW6BEG3.LV18 05_60 07_61 INT_R.SW6BEG3.NW2END_S0_0 02_61 05_63 INT_R.SW6BEG3.NW6END_S0_0 05_63 06_60 INT_R.SW6BEG3.SE2END3 02_61 04_61 @@ -3410,12 +3556,14 @@ INT_R.WW2BEG3.WL1END3 09_63 12_62 INT_R.WW2BEG3.WR1END_S1_0 09_62 12_62 INT_R.WW2BEG3.WW2END3 11_62 14_62 INT_R.WW2BEG3.WW4END_S0_0 11_62 13_62 +INT_R.WW4BEG0.LH12 05_00 07_01 INT_R.WW4BEG0.LOGIC_OUTS0 02_01 04_02 INT_R.WW4BEG0.LOGIC_OUTS12 03_00 04_02 INT_R.WW4BEG0.LOGIC_OUTS18 06_00 07_01 INT_R.WW4BEG0.LOGIC_OUTS22 04_02 06_00 INT_R.WW4BEG0.LOGIC_OUTS4 02_01 07_01 INT_R.WW4BEG0.LOGIC_OUTS8 03_00 07_01 +INT_R.WW4BEG0.LV0 04_02 05_00 INT_R.WW4BEG0.NE2END0 02_01 05_03 INT_R.WW4BEG0.NE6END0 05_00 05_03 INT_R.WW4BEG0.NN2END0 03_00 05_03 @@ -3428,12 +3576,14 @@ INT_R.WW4BEG0.SW2END_N0_3 02_01 04_01 INT_R.WW4BEG0.SW6END_N0_3 04_01 05_00 INT_R.WW4BEG0.WW2END_N0_3 03_00 03_01 INT_R.WW4BEG0.WW4END0 03_01 05_00 +INT_R.WW4BEG1.LH6 05_16 07_17 INT_R.WW4BEG1.LOGIC_OUTS1 02_17 07_17 INT_R.WW4BEG1.LOGIC_OUTS13 03_16 07_17 INT_R.WW4BEG1.LOGIC_OUTS19 04_18 06_16 INT_R.WW4BEG1.LOGIC_OUTS23 06_16 07_17 INT_R.WW4BEG1.LOGIC_OUTS5 02_17 04_18 INT_R.WW4BEG1.LOGIC_OUTS9 03_16 04_18 +INT_R.WW4BEG1.LV9 04_18 05_16 INT_R.WW4BEG1.NE2END1 02_17 05_19 INT_R.WW4BEG1.NE6END1 05_16 05_19 INT_R.WW4BEG1.NN2END1 03_16 05_19 @@ -3452,6 +3602,8 @@ INT_R.WW4BEG2.LOGIC_OUTS16 06_32 07_33 INT_R.WW4BEG2.LOGIC_OUTS2 02_33 04_34 INT_R.WW4BEG2.LOGIC_OUTS20 04_34 06_32 INT_R.WW4BEG2.LOGIC_OUTS6 02_33 07_33 +INT_R.WW4BEG2.LVB0 04_34 05_32 +INT_R.WW4BEG2.LVB12 05_32 07_33 INT_R.WW4BEG2.NE2END2 02_33 05_35 INT_R.WW4BEG2.NE6END2 05_32 05_35 INT_R.WW4BEG2.NN2END2 03_32 05_35 @@ -3464,12 +3616,14 @@ INT_R.WW4BEG2.SW2END1 02_33 04_33 INT_R.WW4BEG2.SW6END1 04_33 05_32 INT_R.WW4BEG2.WW2END1 03_32 03_33 INT_R.WW4BEG2.WW4END2 03_33 05_32 +INT_R.WW4BEG3.LH0 04_50 05_48 INT_R.WW4BEG3.LOGIC_OUTS11 03_48 04_50 INT_R.WW4BEG3.LOGIC_OUTS15 03_48 07_49 INT_R.WW4BEG3.LOGIC_OUTS17 04_50 06_48 INT_R.WW4BEG3.LOGIC_OUTS21 06_48 07_49 INT_R.WW4BEG3.LOGIC_OUTS3 02_49 07_49 INT_R.WW4BEG3.LOGIC_OUTS7 02_49 04_50 +INT_R.WW4BEG3.LV18 05_48 07_49 INT_R.WW4BEG3.NE2END3 02_49 05_51 INT_R.WW4BEG3.NE6END3 05_48 05_51 INT_R.WW4BEG3.NN2END3 03_48 05_51 diff --git a/kintex7/settings.sh b/kintex7/settings.sh index b4632b7..05952db 100644 --- a/kintex7/settings.sh +++ b/kintex7/settings.sh @@ -1,11 +1,16 @@ export XRAY_DATABASE="kintex7" export XRAY_PART="xc7k70tfbg676-2" +export XRAY_ROI_FRAMES="0x00000000:0xffffffff" + export XRAY_ROI="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19" -export XRAY_ROI_FRAMES="0x00400100:0x004006ff" + +# Part of CMT X0Y1 export XRAY_ROI_GRID_X1="9" export XRAY_ROI_GRID_X2="38" +# Include VBRK / VTERM export XRAY_ROI_GRID_Y1="104" export XRAY_ROI_GRID_Y2="156" + # Choose the first N High Range I/Os export XRAY_PIN_00="K25" export XRAY_PIN_01="K26" diff --git a/kintex7/site_type_BSCAN.json b/kintex7/site_type_BSCAN.json new file mode 100644 index 0000000..1507c32 --- /dev/null +++ b/kintex7/site_type_BSCAN.json @@ -0,0 +1,39 @@ +{ + "type": "BSCAN", + "site_pips": {}, + "site_pins": { + "TMS": { + "direction": "OUT" + }, + "CAPTURE": { + "direction": "OUT" + }, + "TDO": { + "direction": "IN" + }, + "SHIFT": { + "direction": "OUT" + }, + "SEL": { + "direction": "OUT" + }, + "UPDATE": { + "direction": "OUT" + }, + "TCK": { + "direction": "OUT" + }, + "TDI": { + "direction": "OUT" + }, + "RESET": { + "direction": "OUT" + }, + "RUNTEST": { + "direction": "OUT" + }, + "DRCK": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_BUFGCTRL.json b/kintex7/site_type_BUFGCTRL.json new file mode 100644 index 0000000..a9291ac --- /dev/null +++ b/kintex7/site_type_BUFGCTRL.json @@ -0,0 +1,82 @@ +{ + "type": "BUFGCTRL", + "site_pips": { + "CE1INV:CE1_B": { + "from_pin": "CE1_B", + "to_pin": "OUT" + }, + "IGNORE1INV:IGNORE1_B": { + "from_pin": "IGNORE1_B", + "to_pin": "OUT" + }, + "S0INV:S0_B": { + "from_pin": "S0_B", + "to_pin": "OUT" + }, + "CE1INV:CE1": { + "from_pin": "CE1", + "to_pin": "OUT" + }, + "CE0INV:CE0": { + "from_pin": "CE0", + "to_pin": "OUT" + }, + "IGNORE1INV:IGNORE1": { + "from_pin": "IGNORE1", + "to_pin": "OUT" + }, + "S1INV:S1_B": { + "from_pin": "S1_B", + "to_pin": "OUT" + }, + "CE0INV:CE0_B": { + "from_pin": "CE0_B", + "to_pin": "OUT" + }, + "IGNORE0INV:IGNORE0": { + "from_pin": "IGNORE0", + "to_pin": "OUT" + }, + "S1INV:S1": { + "from_pin": "S1", + "to_pin": "OUT" + }, + "S0INV:S0": { + "from_pin": "S0", + "to_pin": "OUT" + }, + "IGNORE0INV:IGNORE0_B": { + "from_pin": "IGNORE0_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "IGNORE1": { + "direction": "IN" + }, + "S1": { + "direction": "IN" + }, + "I1": { + "direction": "IN" + }, + "CE0": { + "direction": "IN" + }, + "I0": { + "direction": "IN" + }, + "CE1": { + "direction": "IN" + }, + "S0": { + "direction": "IN" + }, + "O": { + "direction": "OUT" + }, + "IGNORE0": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_BUFHCE.json b/kintex7/site_type_BUFHCE.json new file mode 100644 index 0000000..d0f2ebf --- /dev/null +++ b/kintex7/site_type_BUFHCE.json @@ -0,0 +1,24 @@ +{ + "type": "BUFHCE", + "site_pips": { + "CEINV:CE": { + "from_pin": "CE", + "to_pin": "OUT" + }, + "CEINV:CE_B": { + "from_pin": "CE_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "CE": { + "direction": "IN" + }, + "I": { + "direction": "IN" + }, + "O": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_BUFIO.json b/kintex7/site_type_BUFIO.json new file mode 100644 index 0000000..b152cdc --- /dev/null +++ b/kintex7/site_type_BUFIO.json @@ -0,0 +1,12 @@ +{ + "type": "BUFIO", + "site_pips": {}, + "site_pins": { + "I": { + "direction": "IN" + }, + "O": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_BUFMRCE.json b/kintex7/site_type_BUFMRCE.json new file mode 100644 index 0000000..e76506a --- /dev/null +++ b/kintex7/site_type_BUFMRCE.json @@ -0,0 +1,24 @@ +{ + "type": "BUFMRCE", + "site_pips": { + "CEINV:CE": { + "from_pin": "CE", + "to_pin": "OUT" + }, + "CEINV:CE_B": { + "from_pin": "CE_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "CE": { + "direction": "IN" + }, + "I": { + "direction": "IN" + }, + "O": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_BUFR.json b/kintex7/site_type_BUFR.json new file mode 100644 index 0000000..0e2e7ff --- /dev/null +++ b/kintex7/site_type_BUFR.json @@ -0,0 +1,18 @@ +{ + "type": "BUFR", + "site_pips": {}, + "site_pins": { + "CE": { + "direction": "IN" + }, + "I": { + "direction": "IN" + }, + "CLR": { + "direction": "IN" + }, + "O": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_CAPTURE.json b/kintex7/site_type_CAPTURE.json new file mode 100644 index 0000000..8c6c0dc --- /dev/null +++ b/kintex7/site_type_CAPTURE.json @@ -0,0 +1,12 @@ +{ + "type": "CAPTURE", + "site_pips": {}, + "site_pins": { + "CLK": { + "direction": "IN" + }, + "CAP": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_DCIRESET.json b/kintex7/site_type_DCIRESET.json new file mode 100644 index 0000000..b1e4d52 --- /dev/null +++ b/kintex7/site_type_DCIRESET.json @@ -0,0 +1,12 @@ +{ + "type": "DCIRESET", + "site_pips": {}, + "site_pins": { + "RST": { + "direction": "IN" + }, + "LOCKED": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_DNA_PORT.json b/kintex7/site_type_DNA_PORT.json new file mode 100644 index 0000000..b7a6993 --- /dev/null +++ b/kintex7/site_type_DNA_PORT.json @@ -0,0 +1,21 @@ +{ + "type": "DNA_PORT", + "site_pips": {}, + "site_pins": { + "DOUT": { + "direction": "OUT" + }, + "CLK": { + "direction": "IN" + }, + "DIN": { + "direction": "IN" + }, + "READ": { + "direction": "IN" + }, + "SHIFT": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_DSP48E1.json b/kintex7/site_type_DSP48E1.json new file mode 100644 index 0000000..672bad8 --- /dev/null +++ b/kintex7/site_type_DSP48E1.json @@ -0,0 +1,1402 @@ +{ + "type": "DSP48E1", + "site_pips": { + "OPMODE5INV:OPMODE5_B": { + "from_pin": "OPMODE5_B", + "to_pin": "OUT" + }, + "OPMODE4INV:OPMODE4_B": { + "from_pin": "OPMODE4_B", + "to_pin": "OUT" + }, + "OPMODE1INV:OPMODE1": { + "from_pin": "OPMODE1", + "to_pin": "OUT" + }, + "ALUMODE1INV:ALUMODE1": { + "from_pin": "ALUMODE1", + "to_pin": "OUT" + }, + "OPMODE2INV:OPMODE2": { + "from_pin": "OPMODE2", + "to_pin": "OUT" + }, + "OPMODE4INV:OPMODE4": { + "from_pin": "OPMODE4", + "to_pin": "OUT" + }, + "ALUMODE2INV:ALUMODE2_B": { + "from_pin": "ALUMODE2_B", + "to_pin": "OUT" + }, + "CARRYININV:CARRYIN": { + "from_pin": "CARRYIN", + "to_pin": "OUT" + }, + "OPMODE2INV:OPMODE2_B": { + "from_pin": "OPMODE2_B", + "to_pin": "OUT" + }, + "OPMODE6INV:OPMODE6_B": { + "from_pin": "OPMODE6_B", + "to_pin": "OUT" + }, + "INMODE0INV:INMODE0_B": { + "from_pin": "INMODE0_B", + "to_pin": "OUT" + }, + "ALUMODE0INV:ALUMODE0": { + "from_pin": "ALUMODE0", + "to_pin": "OUT" + }, + "INMODE1INV:INMODE1_B": { + "from_pin": "INMODE1_B", + "to_pin": "OUT" + }, + "CARRYININV:CARRYIN_B": { + "from_pin": "CARRYIN_B", + "to_pin": "OUT" + }, + "INMODE3INV:INMODE3_B": { + "from_pin": "INMODE3_B", + "to_pin": "OUT" + }, + "ALUMODE3INV:ALUMODE3_B": { + "from_pin": "ALUMODE3_B", + "to_pin": "OUT" + }, + "OPMODE5INV:OPMODE5": { + "from_pin": "OPMODE5", + "to_pin": "OUT" + }, + "ALUMODE2INV:ALUMODE2": { + "from_pin": "ALUMODE2", + "to_pin": "OUT" + }, + "CLKINV:CLK": { + "from_pin": "CLK", + "to_pin": "OUT" + }, + "OPMODE3INV:OPMODE3_B": { + "from_pin": "OPMODE3_B", + "to_pin": "OUT" + }, + "INMODE2INV:INMODE2": { + "from_pin": "INMODE2", + "to_pin": "OUT" + }, + "OPMODE1INV:OPMODE1_B": { + "from_pin": "OPMODE1_B", + "to_pin": "OUT" + }, + "OPMODE6INV:OPMODE6": { + "from_pin": "OPMODE6", + "to_pin": "OUT" + }, + "INMODE2INV:INMODE2_B": { + "from_pin": "INMODE2_B", + "to_pin": "OUT" + }, + "OPMODE0INV:OPMODE0_B": { + "from_pin": "OPMODE0_B", + "to_pin": "OUT" + }, + "OPMODE0INV:OPMODE0": { + "from_pin": "OPMODE0", + "to_pin": "OUT" + }, + "ALUMODE1INV:ALUMODE1_B": { + "from_pin": "ALUMODE1_B", + "to_pin": "OUT" + }, + "ALUMODE0INV:ALUMODE0_B": { + "from_pin": "ALUMODE0_B", + "to_pin": "OUT" + }, + "INMODE0INV:INMODE0": { + "from_pin": "INMODE0", + "to_pin": "OUT" + }, + "INMODE3INV:INMODE3": { + "from_pin": "INMODE3", + "to_pin": "OUT" + }, + "INMODE1INV:INMODE1": { + "from_pin": "INMODE1", + "to_pin": "OUT" + }, + "ALUMODE3INV:ALUMODE3": { + "from_pin": "ALUMODE3", + "to_pin": "OUT" + }, + "INMODE4INV:INMODE4_B": { + "from_pin": "INMODE4_B", + "to_pin": "OUT" + }, + "CLKINV:CLK_B": { + "from_pin": "CLK_B", + "to_pin": "OUT" + }, + "INMODE4INV:INMODE4": { + "from_pin": "INMODE4", + "to_pin": "OUT" + }, + "OPMODE3INV:OPMODE3": { + "from_pin": "OPMODE3", + "to_pin": "OUT" + } + }, + "site_pins": { + "MULTSIGNOUT": { + "direction": "OUT" + }, + "MULTSIGNIN": { + "direction": "IN" + }, + "A19": { + "direction": "IN" + }, + "P30": { + "direction": "OUT" + }, + "P44": { + "direction": "OUT" + }, + "ACOUT8": { + "direction": "OUT" + }, + "PCOUT21": { + "direction": "OUT" + }, + "C16": { + "direction": "IN" + }, + "ACIN0": { + "direction": "IN" + }, + "P41": { + "direction": "OUT" + }, + "ACOUT21": { + "direction": "OUT" + }, + "PCOUT8": { + "direction": "OUT" + }, + "PATTERNBDETECT": { + "direction": "OUT" + }, + "P35": { + "direction": "OUT" + }, + "P21": { + "direction": "OUT" + }, + "ACOUT7": { + "direction": "OUT" + }, + "P11": { + "direction": "OUT" + }, + "OPMODE4": { + "direction": "IN" + }, + "C28": { + "direction": "IN" + }, + "PCOUT1": { + "direction": "OUT" + }, + "B10": { + "direction": "IN" + }, + "P7": { + "direction": "OUT" + }, + "PCOUT20": { + "direction": "OUT" + }, + "P46": { + "direction": "OUT" + }, + "BCOUT2": { + "direction": "OUT" + }, + "PCOUT25": { + "direction": "OUT" + }, + "C35": { + "direction": "IN" + }, + "ACOUT2": { + "direction": "OUT" + }, + "RSTINMODE": { + "direction": "IN" + }, + "ACOUT10": { + "direction": "OUT" + }, + "CARRYOUT2": { + "direction": "OUT" + }, + "BCOUT12": { + "direction": "OUT" + }, + "PCIN5": { + "direction": "IN" + }, + "PCIN23": { + "direction": "IN" + }, + "INMODE4": { + "direction": "IN" + }, + "PCIN40": { + "direction": "IN" + }, + "C0": { + "direction": "IN" + }, + "PCOUT3": { + "direction": "OUT" + }, + "PCIN1": { + "direction": "IN" + }, + "P32": { + "direction": "OUT" + }, + "C24": { + "direction": "IN" + }, + "ACIN23": { + "direction": "IN" + }, + "BCIN2": { + "direction": "IN" + }, + "ACIN1": { + "direction": "IN" + }, + "BCIN5": { + "direction": "IN" + }, + "PCOUT22": { + "direction": "OUT" + }, + "PCOUT45": { + "direction": "OUT" + }, + "BCOUT4": { + "direction": "OUT" + }, + "B17": { + "direction": "IN" + }, + "C7": { + "direction": "IN" + }, + "BCOUT13": { + "direction": "OUT" + }, + "P37": { + "direction": "OUT" + }, + "RSTA": { + "direction": "IN" + }, + "D14": { + "direction": "IN" + }, + "PCOUT11": { + "direction": "OUT" + }, + "P34": { + "direction": "OUT" + }, + "PCIN32": { + "direction": "IN" + }, + "C33": { + "direction": "IN" + }, + "CARRYOUT1": { + "direction": "OUT" + }, + "OVERFLOW": { + "direction": "OUT" + }, + "C17": { + "direction": "IN" + }, + "A28": { + "direction": "IN" + }, + "D18": { + "direction": "IN" + }, + "INMODE2": { + "direction": "IN" + }, + "C29": { + "direction": "IN" + }, + "ACIN17": { + "direction": "IN" + }, + "BCOUT10": { + "direction": "OUT" + }, + "C46": { + "direction": "IN" + }, + "ACIN10": { + "direction": "IN" + }, + "A29": { + "direction": "IN" + }, + "P4": { + "direction": "OUT" + }, + "B3": { + "direction": "IN" + }, + "P15": { + "direction": "OUT" + }, + "PCOUT15": { + "direction": "OUT" + }, + "BCOUT6": { + "direction": "OUT" + }, + "ACOUT9": { + "direction": "OUT" + }, + "A16": { + "direction": "IN" + }, + "ACOUT16": { + "direction": "OUT" + }, + "C37": { + "direction": "IN" + }, + "CARRYCASCOUT": { + "direction": "OUT" + }, + "ACOUT5": { + "direction": "OUT" + }, + "P33": { + "direction": "OUT" + }, + "B13": { + "direction": "IN" + }, + "P8": { + "direction": "OUT" + }, + "UNDERFLOW": { + "direction": "OUT" + }, + "P39": { + "direction": "OUT" + }, + "C2": { + "direction": "IN" + }, + "PCOUT37": { + "direction": "OUT" + }, + "PCOUT30": { + "direction": "OUT" + }, + "RSTB": { + "direction": "IN" + }, + "C45": { + "direction": "IN" + }, + "A8": { + "direction": "IN" + }, + "P14": { + "direction": "OUT" + }, + "PCOUT42": { + "direction": "OUT" + }, + "BCOUT7": { + "direction": "OUT" + }, + "D24": { + "direction": "IN" + }, + "PCOUT13": { + "direction": "OUT" + }, + "B5": { + "direction": "IN" + }, + "OPMODE5": { + "direction": "IN" + }, + "CEALUMODE": { + "direction": "IN" + }, + "ALUMODE3": { + "direction": "IN" + }, + "C34": { + "direction": "IN" + }, + "D13": { + "direction": "IN" + }, + "ACOUT24": { + "direction": "OUT" + }, + "P2": { + "direction": "OUT" + }, + "ACOUT20": { + "direction": "OUT" + }, + "C32": { + "direction": "IN" + }, + "C40": { + "direction": "IN" + }, + "PCIN43": { + "direction": "IN" + }, + "D1": { + "direction": "IN" + }, + "BCOUT11": { + "direction": "OUT" + }, + "CEAD": { + "direction": "IN" + }, + "ACIN11": { + "direction": "IN" + }, + "D9": { + "direction": "IN" + }, + "A24": { + "direction": "IN" + }, + "RSTC": { + "direction": "IN" + }, + "ACIN24": { + "direction": "IN" + }, + "A4": { + "direction": "IN" + }, + "PCOUT18": { + "direction": "OUT" + }, + "ACIN7": { + "direction": "IN" + }, + "ACIN8": { + "direction": "IN" + }, + "PCOUT28": { + "direction": "OUT" + }, + "PCIN20": { + "direction": "IN" + }, + "A20": { + "direction": "IN" + }, + "BCOUT17": { + "direction": "OUT" + }, + "A5": { + "direction": "IN" + }, + "CARRYCASCIN": { + "direction": "IN" + }, + "INMODE1": { + "direction": "IN" + }, + "P20": { + "direction": "OUT" + }, + "B14": { + "direction": "IN" + }, + "ACIN28": { + "direction": "IN" + }, + "PCIN3": { + "direction": "IN" + }, + "CARRYINSEL0": { + "direction": "IN" + }, + "CEP": { + "direction": "IN" + }, + "C21": { + "direction": "IN" + }, + "PCOUT24": { + "direction": "OUT" + }, + "RSTALUMODE": { + "direction": "IN" + }, + "P12": { + "direction": "OUT" + }, + "C47": { + "direction": "IN" + }, + "ACIN19": { + "direction": "IN" + }, + "BCOUT15": { + "direction": "OUT" + }, + "ACIN16": { + "direction": "IN" + }, + "P43": { + "direction": "OUT" + }, + "OPMODE0": { + "direction": "IN" + }, + "B8": { + "direction": "IN" + }, + "P5": { + "direction": "OUT" + }, + "A2": { + "direction": "IN" + }, + "PCOUT41": { + "direction": "OUT" + }, + "P13": { + "direction": "OUT" + }, + "D7": { + "direction": "IN" + }, + "BCIN0": { + "direction": "IN" + }, + "A27": { + "direction": "IN" + }, + "BCOUT0": { + "direction": "OUT" + }, + "B16": { + "direction": "IN" + }, + "P10": { + "direction": "OUT" + }, + "PCIN30": { + "direction": "IN" + }, + "P6": { + "direction": "OUT" + }, + "ALUMODE1": { + "direction": "IN" + }, + "P27": { + "direction": "OUT" + }, + "C25": { + "direction": "IN" + }, + "CEA2": { + "direction": "IN" + }, + "ACIN5": { + "direction": "IN" + }, + "ACOUT17": { + "direction": "OUT" + }, + "CECARRYIN": { + "direction": "IN" + }, + "PCIN25": { + "direction": "IN" + }, + "C26": { + "direction": "IN" + }, + "A13": { + "direction": "IN" + }, + "PCIN39": { + "direction": "IN" + }, + "PCOUT0": { + "direction": "OUT" + }, + "C14": { + "direction": "IN" + }, + "ACIN9": { + "direction": "IN" + }, + "CARRYINSEL1": { + "direction": "IN" + }, + "B11": { + "direction": "IN" + }, + "PCOUT31": { + "direction": "OUT" + }, + "A10": { + "direction": "IN" + }, + "BCIN8": { + "direction": "IN" + }, + "A6": { + "direction": "IN" + }, + "A3": { + "direction": "IN" + }, + "ACIN27": { + "direction": "IN" + }, + "PCIN34": { + "direction": "IN" + }, + "D21": { + "direction": "IN" + }, + "PCOUT39": { + "direction": "OUT" + }, + "A14": { + "direction": "IN" + }, + "CEB2": { + "direction": "IN" + }, + "PCOUT47": { + "direction": "OUT" + }, + "D10": { + "direction": "IN" + }, + "BCIN15": { + "direction": "IN" + }, + "PCIN33": { + "direction": "IN" + }, + "C44": { + "direction": "IN" + }, + "D8": { + "direction": "IN" + }, + "D17": { + "direction": "IN" + }, + "PCIN8": { + "direction": "IN" + }, + "C39": { + "direction": "IN" + }, + "PCOUT10": { + "direction": "OUT" + }, + "P19": { + "direction": "OUT" + }, + "ACIN15": { + "direction": "IN" + }, + "PCIN31": { + "direction": "IN" + }, + "PCOUT17": { + "direction": "OUT" + }, + "CARRYOUT0": { + "direction": "OUT" + }, + "OPMODE3": { + "direction": "IN" + }, + "P40": { + "direction": "OUT" + }, + "PCIN0": { + "direction": "IN" + }, + "C9": { + "direction": "IN" + }, + "PCIN10": { + "direction": "IN" + }, + "ACOUT14": { + "direction": "OUT" + }, + "PCIN16": { + "direction": "IN" + }, + "BCIN3": { + "direction": "IN" + }, + "P22": { + "direction": "OUT" + }, + "PCOUT14": { + "direction": "OUT" + }, + "D20": { + "direction": "IN" + }, + "C18": { + "direction": "IN" + }, + "B2": { + "direction": "IN" + }, + "ACIN6": { + "direction": "IN" + }, + "P45": { + "direction": "OUT" + }, + "CEINMODE": { + "direction": "IN" + }, + "OPMODE1": { + "direction": "IN" + }, + "BCIN16": { + "direction": "IN" + }, + "C4": { + "direction": "IN" + }, + "BCOUT14": { + "direction": "OUT" + }, + "ACOUT19": { + "direction": "OUT" + }, + "PCIN12": { + "direction": "IN" + }, + "ALUMODE2": { + "direction": "IN" + }, + "C27": { + "direction": "IN" + }, + "PCIN24": { + "direction": "IN" + }, + "PCIN46": { + "direction": "IN" + }, + "A18": { + "direction": "IN" + }, + "C3": { + "direction": "IN" + }, + "A22": { + "direction": "IN" + }, + "PCOUT4": { + "direction": "OUT" + }, + "BCIN6": { + "direction": "IN" + }, + "D16": { + "direction": "IN" + }, + "P42": { + "direction": "OUT" + }, + "BCIN9": { + "direction": "IN" + }, + "A21": { + "direction": "IN" + }, + "RSTCTRL": { + "direction": "IN" + }, + "P31": { + "direction": "OUT" + }, + "ACOUT12": { + "direction": "OUT" + }, + "PCIN2": { + "direction": "IN" + }, + "CEM": { + "direction": "IN" + }, + "P18": { + "direction": "OUT" + }, + "PCOUT6": { + "direction": "OUT" + }, + "C38": { + "direction": "IN" + }, + "PCIN11": { + "direction": "IN" + }, + "BCOUT3": { + "direction": "OUT" + }, + "CED": { + "direction": "IN" + }, + "PCIN18": { + "direction": "IN" + }, + "ACOUT22": { + "direction": "OUT" + }, + "ACOUT27": { + "direction": "OUT" + }, + "PCOUT2": { + "direction": "OUT" + }, + "PCOUT12": { + "direction": "OUT" + }, + "ACIN21": { + "direction": "IN" + }, + "A15": { + "direction": "IN" + }, + "PCIN41": { + "direction": "IN" + }, + "ACOUT11": { + "direction": "OUT" + }, + "B4": { + "direction": "IN" + }, + "A11": { + "direction": "IN" + }, + "PCIN17": { + "direction": "IN" + }, + "PCOUT5": { + "direction": "OUT" + }, + "ACOUT18": { + "direction": "OUT" + }, + "ACIN29": { + "direction": "IN" + }, + "C41": { + "direction": "IN" + }, + "D23": { + "direction": "IN" + }, + "A12": { + "direction": "IN" + }, + "ACOUT1": { + "direction": "OUT" + }, + "PCIN9": { + "direction": "IN" + }, + "CARRYINSEL2": { + "direction": "IN" + }, + "PCOUT26": { + "direction": "OUT" + }, + "ACOUT28": { + "direction": "OUT" + }, + "D5": { + "direction": "IN" + }, + "BCIN12": { + "direction": "IN" + }, + "ACIN18": { + "direction": "IN" + }, + "ACOUT13": { + "direction": "OUT" + }, + "CEB1": { + "direction": "IN" + }, + "P16": { + "direction": "OUT" + }, + "P23": { + "direction": "OUT" + }, + "C6": { + "direction": "IN" + }, + "D6": { + "direction": "IN" + }, + "PCIN6": { + "direction": "IN" + }, + "PCIN26": { + "direction": "IN" + }, + "ALUMODE0": { + "direction": "IN" + }, + "B12": { + "direction": "IN" + }, + "BCOUT1": { + "direction": "OUT" + }, + "P24": { + "direction": "OUT" + }, + "P3": { + "direction": "OUT" + }, + "ACIN25": { + "direction": "IN" + }, + "ACOUT0": { + "direction": "OUT" + }, + "D0": { + "direction": "IN" + }, + "P17": { + "direction": "OUT" + }, + "PCOUT38": { + "direction": "OUT" + }, + "A26": { + "direction": "IN" + }, + "PCIN37": { + "direction": "IN" + }, + "PCOUT32": { + "direction": "OUT" + }, + "PCOUT29": { + "direction": "OUT" + }, + "ACIN2": { + "direction": "IN" + }, + "PCIN38": { + "direction": "IN" + }, + "C20": { + "direction": "IN" + }, + "C15": { + "direction": "IN" + }, + "BCIN4": { + "direction": "IN" + }, + "C36": { + "direction": "IN" + }, + "PCOUT43": { + "direction": "OUT" + }, + "C11": { + "direction": "IN" + }, + "BCOUT9": { + "direction": "OUT" + }, + "PCOUT7": { + "direction": "OUT" + }, + "D15": { + "direction": "IN" + }, + "ACIN20": { + "direction": "IN" + }, + "CEA1": { + "direction": "IN" + }, + "PCOUT16": { + "direction": "OUT" + }, + "D19": { + "direction": "IN" + }, + "C31": { + "direction": "IN" + }, + "PCIN45": { + "direction": "IN" + }, + "BCIN14": { + "direction": "IN" + }, + "PCIN15": { + "direction": "IN" + }, + "D3": { + "direction": "IN" + }, + "P38": { + "direction": "OUT" + }, + "PCIN47": { + "direction": "IN" + }, + "PCIN35": { + "direction": "IN" + }, + "BCIN17": { + "direction": "IN" + }, + "PCOUT36": { + "direction": "OUT" + }, + "PCOUT27": { + "direction": "OUT" + }, + "ACOUT6": { + "direction": "OUT" + }, + "C23": { + "direction": "IN" + }, + "PCOUT19": { + "direction": "OUT" + }, + "P25": { + "direction": "OUT" + }, + "ACOUT15": { + "direction": "OUT" + }, + "C10": { + "direction": "IN" + }, + "P9": { + "direction": "OUT" + }, + "RSTALLCARRYIN": { + "direction": "IN" + }, + "PCOUT33": { + "direction": "OUT" + }, + "C19": { + "direction": "IN" + }, + "P1": { + "direction": "OUT" + }, + "PCIN44": { + "direction": "IN" + }, + "ACOUT26": { + "direction": "OUT" + }, + "A17": { + "direction": "IN" + }, + "P26": { + "direction": "OUT" + }, + "PCOUT9": { + "direction": "OUT" + }, + "PCIN28": { + "direction": "IN" + }, + "PCOUT44": { + "direction": "OUT" + }, + "ACIN4": { + "direction": "IN" + }, + "P36": { + "direction": "OUT" + }, + "A9": { + "direction": "IN" + }, + "B9": { + "direction": "IN" + }, + "ACOUT25": { + "direction": "OUT" + }, + "ACIN12": { + "direction": "IN" + }, + "INMODE0": { + "direction": "IN" + }, + "PCIN13": { + "direction": "IN" + }, + "PCIN4": { + "direction": "IN" + }, + "ACOUT29": { + "direction": "OUT" + }, + "C12": { + "direction": "IN" + }, + "ACIN3": { + "direction": "IN" + }, + "C43": { + "direction": "IN" + }, + "CLK": { + "direction": "IN" + }, + "BCIN11": { + "direction": "IN" + }, + "PCOUT23": { + "direction": "OUT" + }, + "BCOUT8": { + "direction": "OUT" + }, + "P29": { + "direction": "OUT" + }, + "PCIN27": { + "direction": "IN" + }, + "PCIN22": { + "direction": "IN" + }, + "D11": { + "direction": "IN" + }, + "C42": { + "direction": "IN" + }, + "RSTP": { + "direction": "IN" + }, + "D4": { + "direction": "IN" + }, + "PCOUT34": { + "direction": "OUT" + }, + "A0": { + "direction": "IN" + }, + "P28": { + "direction": "OUT" + }, + "ACIN26": { + "direction": "IN" + }, + "BCOUT5": { + "direction": "OUT" + }, + "PCIN7": { + "direction": "IN" + }, + "D12": { + "direction": "IN" + }, + "B6": { + "direction": "IN" + }, + "PCIN19": { + "direction": "IN" + }, + "PCIN29": { + "direction": "IN" + }, + "D2": { + "direction": "IN" + }, + "CARRYOUT3": { + "direction": "OUT" + }, + "ACOUT23": { + "direction": "OUT" + }, + "A7": { + "direction": "IN" + }, + "A23": { + "direction": "IN" + }, + "ACIN14": { + "direction": "IN" + }, + "ACIN22": { + "direction": "IN" + }, + "B1": { + "direction": "IN" + }, + "INMODE3": { + "direction": "IN" + }, + "P0": { + "direction": "OUT" + }, + "A1": { + "direction": "IN" + }, + "C5": { + "direction": "IN" + }, + "B15": { + "direction": "IN" + }, + "PATTERNDETECT": { + "direction": "OUT" + }, + "PCIN21": { + "direction": "IN" + }, + "ACOUT3": { + "direction": "OUT" + }, + "ACOUT4": { + "direction": "OUT" + }, + "P47": { + "direction": "OUT" + }, + "C13": { + "direction": "IN" + }, + "B7": { + "direction": "IN" + }, + "RSTD": { + "direction": "IN" + }, + "D22": { + "direction": "IN" + }, + "CECTRL": { + "direction": "IN" + }, + "RSTM": { + "direction": "IN" + }, + "CARRYIN": { + "direction": "IN" + }, + "PCOUT35": { + "direction": "OUT" + }, + "BCIN7": { + "direction": "IN" + }, + "ACIN13": { + "direction": "IN" + }, + "BCIN13": { + "direction": "IN" + }, + "C1": { + "direction": "IN" + }, + "B0": { + "direction": "IN" + }, + "PCOUT40": { + "direction": "OUT" + }, + "BCIN10": { + "direction": "IN" + }, + "C8": { + "direction": "IN" + }, + "BCIN1": { + "direction": "IN" + }, + "C22": { + "direction": "IN" + }, + "PCIN14": { + "direction": "IN" + }, + "C30": { + "direction": "IN" + }, + "A25": { + "direction": "IN" + }, + "PCOUT46": { + "direction": "OUT" + }, + "CEC": { + "direction": "IN" + }, + "PCIN36": { + "direction": "IN" + }, + "BCOUT16": { + "direction": "OUT" + }, + "OPMODE6": { + "direction": "IN" + }, + "OPMODE2": { + "direction": "IN" + }, + "PCIN42": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_EFUSE_USR.json b/kintex7/site_type_EFUSE_USR.json new file mode 100644 index 0000000..ec95327 --- /dev/null +++ b/kintex7/site_type_EFUSE_USR.json @@ -0,0 +1,102 @@ +{ + "type": "EFUSE_USR", + "site_pips": {}, + "site_pins": { + "EFUSEUSR2": { + "direction": "OUT" + }, + "EFUSEUSR25": { + "direction": "OUT" + }, + "EFUSEUSR30": { + "direction": "OUT" + }, + "EFUSEUSR28": { + "direction": "OUT" + }, + "EFUSEUSR4": { + "direction": "OUT" + }, + "EFUSEUSR7": { + "direction": "OUT" + }, + "EFUSEUSR0": { + "direction": "OUT" + }, + "EFUSEUSR1": { + "direction": "OUT" + }, + "EFUSEUSR6": { + "direction": "OUT" + }, + "EFUSEUSR18": { + "direction": "OUT" + }, + "EFUSEUSR29": { + "direction": "OUT" + }, + "EFUSEUSR21": { + "direction": "OUT" + }, + "EFUSEUSR22": { + "direction": "OUT" + }, + "EFUSEUSR16": { + "direction": "OUT" + }, + "EFUSEUSR9": { + "direction": "OUT" + }, + "EFUSEUSR13": { + "direction": "OUT" + }, + "EFUSEUSR11": { + "direction": "OUT" + }, + "EFUSEUSR17": { + "direction": "OUT" + }, + "EFUSEUSR27": { + "direction": "OUT" + }, + "EFUSEUSR15": { + "direction": "OUT" + }, + "EFUSEUSR8": { + "direction": "OUT" + }, + "EFUSEUSR20": { + "direction": "OUT" + }, + "EFUSEUSR3": { + "direction": "OUT" + }, + "EFUSEUSR23": { + "direction": "OUT" + }, + "EFUSEUSR12": { + "direction": "OUT" + }, + "EFUSEUSR5": { + "direction": "OUT" + }, + "EFUSEUSR24": { + "direction": "OUT" + }, + "EFUSEUSR10": { + "direction": "OUT" + }, + "EFUSEUSR14": { + "direction": "OUT" + }, + "EFUSEUSR26": { + "direction": "OUT" + }, + "EFUSEUSR19": { + "direction": "OUT" + }, + "EFUSEUSR31": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_FIFO18E1.json b/kintex7/site_type_FIFO18E1.json new file mode 100644 index 0000000..07114a7 --- /dev/null +++ b/kintex7/site_type_FIFO18E1.json @@ -0,0 +1,537 @@ +{ + "type": "FIFO18E1", + "site_pips": { + "RSTREGINV:RSTREG": { + "from_pin": "RSTREG", + "to_pin": "OUT" + }, + "WRCLKINV:WRCLK": { + "from_pin": "WRCLK", + "to_pin": "OUT" + }, + "RDENINV:RDEN_B": { + "from_pin": "RDEN_B", + "to_pin": "OUT" + }, + "WRCLKINV:WRCLK_B": { + "from_pin": "WRCLK_B", + "to_pin": "OUT" + }, + "RSTREGINV:RSTREG_B": { + "from_pin": "RSTREG_B", + "to_pin": "OUT" + }, + "RDCLKINV:RDCLK": { + "from_pin": "RDCLK", + "to_pin": "OUT" + }, + "RDCLKINV:RDCLK_B": { + "from_pin": "RDCLK_B", + "to_pin": "OUT" + }, + "WRENINV:WREN_B": { + "from_pin": "WREN_B", + "to_pin": "OUT" + }, + "RSTINV:RST": { + "from_pin": "RST", + "to_pin": "OUT" + }, + "RDENINV:RDEN": { + "from_pin": "RDEN", + "to_pin": "OUT" + }, + "RDRCLKINV:RDRCLK_B": { + "from_pin": "RDRCLK_B", + "to_pin": "OUT" + }, + "WRENINV:WREN": { + "from_pin": "WREN", + "to_pin": "OUT" + }, + "RDRCLKINV:RDRCLK": { + "from_pin": "RDRCLK", + "to_pin": "OUT" + }, + "RSTINV:RST_B": { + "from_pin": "RST_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "ALMOSTEMPTY": { + "direction": "OUT" + }, + "DIADI6": { + "direction": "IN" + }, + "WEBWE5": { + "direction": "IN" + }, + "ADDRARDADDR8": { + "direction": "IN" + }, + "WRCOUNT0": { + "direction": "OUT" + }, + "WEA0": { + "direction": "IN" + }, + "DO21": { + "direction": "OUT" + }, + "ADDRARDADDR5": { + "direction": "IN" + }, + "WEA1": { + "direction": "IN" + }, + "DOP1": { + "direction": "OUT" + }, + "DIADI0": { + "direction": "IN" + }, + "RST": { + "direction": "IN" + }, + "RSTREG": { + "direction": "IN" + }, + "DIBDI8": { + "direction": "IN" + }, + "RSTREGB": { + "direction": "IN" + }, + "ADDRARDADDR13": { + "direction": "IN" + }, + "WREN": { + "direction": "IN" + }, + "ADDRBWRADDR9": { + "direction": "IN" + }, + "RDCOUNT9": { + "direction": "OUT" + }, + "DIADI1": { + "direction": "IN" + }, + "DIADI15": { + "direction": "IN" + }, + "REGCE": { + "direction": "IN" + }, + "DIBDI5": { + "direction": "IN" + }, + "DIBDI12": { + "direction": "IN" + }, + "DO30": { + "direction": "OUT" + }, + "ADDRBWRADDR0": { + "direction": "IN" + }, + "ADDRBTIEHIGH1": { + "direction": "IN" + }, + "DO18": { + "direction": "OUT" + }, + "ADDRATIEHIGH1": { + "direction": "IN" + }, + "RDCOUNT7": { + "direction": "OUT" + }, + "RDERR": { + "direction": "OUT" + }, + "DO12": { + "direction": "OUT" + }, + "DIBDI13": { + "direction": "IN" + }, + "DO28": { + "direction": "OUT" + }, + "RDCOUNT1": { + "direction": "OUT" + }, + "WRERR": { + "direction": "OUT" + }, + "DO24": { + "direction": "OUT" + }, + "WRCOUNT1": { + "direction": "OUT" + }, + "WRCOUNT10": { + "direction": "OUT" + }, + "RDCOUNT10": { + "direction": "OUT" + }, + "DIBDI7": { + "direction": "IN" + }, + "DO27": { + "direction": "OUT" + }, + "WRCOUNT7": { + "direction": "OUT" + }, + "DIADI5": { + "direction": "IN" + }, + "DIADI10": { + "direction": "IN" + }, + "DO8": { + "direction": "OUT" + }, + "DIADI7": { + "direction": "IN" + }, + "DO3": { + "direction": "OUT" + }, + "DIPBDIP1": { + "direction": "IN" + }, + "WEBWE4": { + "direction": "IN" + }, + "RDCOUNT11": { + "direction": "OUT" + }, + "WEBWE0": { + "direction": "IN" + }, + "ADDRARDADDR1": { + "direction": "IN" + }, + "DIBDI4": { + "direction": "IN" + }, + "EMPTY": { + "direction": "OUT" + }, + "DO4": { + "direction": "OUT" + }, + "DO31": { + "direction": "OUT" + }, + "DO19": { + "direction": "OUT" + }, + "RDCLK": { + "direction": "IN" + }, + "RDCOUNT8": { + "direction": "OUT" + }, + "ADDRBWRADDR6": { + "direction": "IN" + }, + "ADDRBWRADDR10": { + "direction": "IN" + }, + "DIBDI2": { + "direction": "IN" + }, + "ADDRBWRADDR2": { + "direction": "IN" + }, + "DO13": { + "direction": "OUT" + }, + "WRCOUNT4": { + "direction": "OUT" + }, + "ADDRARDADDR10": { + "direction": "IN" + }, + "RSTRAMB": { + "direction": "IN" + }, + "DO1": { + "direction": "OUT" + }, + "DIADI14": { + "direction": "IN" + }, + "ADDRARDADDR11": { + "direction": "IN" + }, + "DIBDI1": { + "direction": "IN" + }, + "DIBDI6": { + "direction": "IN" + }, + "WEBWE2": { + "direction": "IN" + }, + "FULL": { + "direction": "OUT" + }, + "RDEN": { + "direction": "IN" + }, + "ADDRBTIEHIGH0": { + "direction": "IN" + }, + "DO16": { + "direction": "OUT" + }, + "RDCOUNT0": { + "direction": "OUT" + }, + "DOP0": { + "direction": "OUT" + }, + "RDCOUNT5": { + "direction": "OUT" + }, + "DIBDI9": { + "direction": "IN" + }, + "ADDRBWRADDR8": { + "direction": "IN" + }, + "DOP3": { + "direction": "OUT" + }, + "DIBDI3": { + "direction": "IN" + }, + "WEA2": { + "direction": "IN" + }, + "RDRCLK": { + "direction": "IN" + }, + "DIPADIP1": { + "direction": "IN" + }, + "WRCOUNT11": { + "direction": "OUT" + }, + "DIPBDIP0": { + "direction": "IN" + }, + "WRCOUNT9": { + "direction": "OUT" + }, + "DO0": { + "direction": "OUT" + }, + "DO17": { + "direction": "OUT" + }, + "WRCOUNT2": { + "direction": "OUT" + }, + "DOP2": { + "direction": "OUT" + }, + "WRCOUNT6": { + "direction": "OUT" + }, + "DIBDI11": { + "direction": "IN" + }, + "DO22": { + "direction": "OUT" + }, + "ADDRBWRADDR11": { + "direction": "IN" + }, + "ADDRARDADDR9": { + "direction": "IN" + }, + "DO15": { + "direction": "OUT" + }, + "REGCEB": { + "direction": "IN" + }, + "ALMOSTFULL": { + "direction": "OUT" + }, + "WEBWE1": { + "direction": "IN" + }, + "WEBWE3": { + "direction": "IN" + }, + "DO26": { + "direction": "OUT" + }, + "RDCOUNT2": { + "direction": "OUT" + }, + "DO14": { + "direction": "OUT" + }, + "WRCLK": { + "direction": "IN" + }, + "WRCOUNT5": { + "direction": "OUT" + }, + "WEBWE7": { + "direction": "IN" + }, + "ADDRARDADDR7": { + "direction": "IN" + }, + "ADDRARDADDR3": { + "direction": "IN" + }, + "DIADI11": { + "direction": "IN" + }, + "ADDRBWRADDR4": { + "direction": "IN" + }, + "DIADI12": { + "direction": "IN" + }, + "DO7": { + "direction": "OUT" + }, + "RDCOUNT6": { + "direction": "OUT" + }, + "ADDRARDADDR12": { + "direction": "IN" + }, + "ADDRBWRADDR13": { + "direction": "IN" + }, + "RDCOUNT4": { + "direction": "OUT" + }, + "DIADI13": { + "direction": "IN" + }, + "DO10": { + "direction": "OUT" + }, + "DIADI4": { + "direction": "IN" + }, + "DO23": { + "direction": "OUT" + }, + "DIADI8": { + "direction": "IN" + }, + "DO29": { + "direction": "OUT" + }, + "ADDRARDADDR2": { + "direction": "IN" + }, + "ADDRBWRADDR7": { + "direction": "IN" + }, + "DIADI2": { + "direction": "IN" + }, + "DO25": { + "direction": "OUT" + }, + "ADDRARDADDR4": { + "direction": "IN" + }, + "WRCOUNT3": { + "direction": "OUT" + }, + "DO9": { + "direction": "OUT" + }, + "DO6": { + "direction": "OUT" + }, + "WEA3": { + "direction": "IN" + }, + "ADDRATIEHIGH0": { + "direction": "IN" + }, + "DO20": { + "direction": "OUT" + }, + "DO2": { + "direction": "OUT" + }, + "ADDRBWRADDR5": { + "direction": "IN" + }, + "ADDRBWRADDR3": { + "direction": "IN" + }, + "DIADI9": { + "direction": "IN" + }, + "DIPADIP0": { + "direction": "IN" + }, + "WEBWE6": { + "direction": "IN" + }, + "DIBDI0": { + "direction": "IN" + }, + "ADDRBWRADDR12": { + "direction": "IN" + }, + "REGCLKB": { + "direction": "IN" + }, + "DIBDI15": { + "direction": "IN" + }, + "DO11": { + "direction": "OUT" + }, + "WRCOUNT8": { + "direction": "OUT" + }, + "DO5": { + "direction": "OUT" + }, + "ADDRARDADDR6": { + "direction": "IN" + }, + "DIBDI14": { + "direction": "IN" + }, + "ADDRBWRADDR1": { + "direction": "IN" + }, + "DIADI3": { + "direction": "IN" + }, + "RDCOUNT3": { + "direction": "OUT" + }, + "ADDRARDADDR0": { + "direction": "IN" + }, + "DIBDI10": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_FRAME_ECC.json b/kintex7/site_type_FRAME_ECC.json new file mode 100644 index 0000000..687c128 --- /dev/null +++ b/kintex7/site_type_FRAME_ECC.json @@ -0,0 +1,171 @@ +{ + "type": "FRAME_ECC", + "site_pips": {}, + "site_pins": { + "FAR19": { + "direction": "OUT" + }, + "SYNDROME5": { + "direction": "OUT" + }, + "CRCERROR": { + "direction": "OUT" + }, + "SYNDROME6": { + "direction": "OUT" + }, + "FAR2": { + "direction": "OUT" + }, + "FAR11": { + "direction": "OUT" + }, + "FAR0": { + "direction": "OUT" + }, + "FAR17": { + "direction": "OUT" + }, + "SYNWORD6": { + "direction": "OUT" + }, + "SYNWORD0": { + "direction": "OUT" + }, + "SYNDROME3": { + "direction": "OUT" + }, + "FAR23": { + "direction": "OUT" + }, + "SYNBIT0": { + "direction": "OUT" + }, + "SYNDROME1": { + "direction": "OUT" + }, + "FAR13": { + "direction": "OUT" + }, + "FAR7": { + "direction": "OUT" + }, + "SYNWORD5": { + "direction": "OUT" + }, + "FAR20": { + "direction": "OUT" + }, + "SYNWORD4": { + "direction": "OUT" + }, + "SYNBIT4": { + "direction": "OUT" + }, + "SYNDROME11": { + "direction": "OUT" + }, + "FAR15": { + "direction": "OUT" + }, + "FAR1": { + "direction": "OUT" + }, + "FAR24": { + "direction": "OUT" + }, + "SYNBIT2": { + "direction": "OUT" + }, + "FAR12": { + "direction": "OUT" + }, + "SYNDROME12": { + "direction": "OUT" + }, + "SYNDROME0": { + "direction": "OUT" + }, + "FAR5": { + "direction": "OUT" + }, + "FAR10": { + "direction": "OUT" + }, + "SYNDROME8": { + "direction": "OUT" + }, + "SYNDROMEVALID": { + "direction": "OUT" + }, + "FAR8": { + "direction": "OUT" + }, + "FAR6": { + "direction": "OUT" + }, + "ECCERROR": { + "direction": "OUT" + }, + "SYNWORD1": { + "direction": "OUT" + }, + "FAR14": { + "direction": "OUT" + }, + "SYNBIT3": { + "direction": "OUT" + }, + "SYNDROME9": { + "direction": "OUT" + }, + "FAR3": { + "direction": "OUT" + }, + "SYNWORD2": { + "direction": "OUT" + }, + "SYNWORD3": { + "direction": "OUT" + }, + "SYNDROME2": { + "direction": "OUT" + }, + "SYNDROME4": { + "direction": "OUT" + }, + "FAR16": { + "direction": "OUT" + }, + "SYNBIT1": { + "direction": "OUT" + }, + "FAR9": { + "direction": "OUT" + }, + "FAR22": { + "direction": "OUT" + }, + "FAR25": { + "direction": "OUT" + }, + "SYNDROME10": { + "direction": "OUT" + }, + "FAR21": { + "direction": "OUT" + }, + "FAR4": { + "direction": "OUT" + }, + "FAR18": { + "direction": "OUT" + }, + "SYNDROME7": { + "direction": "OUT" + }, + "ECCERRORSINGLE": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_GTXE2_CHANNEL.json b/kintex7/site_type_GTXE2_CHANNEL.json new file mode 100644 index 0000000..00efe0f --- /dev/null +++ b/kintex7/site_type_GTXE2_CHANNEL.json @@ -0,0 +1,2195 @@ +{ + "type": "GTXE2_CHANNEL", + "site_pips": { + "TSTCLK1INV:TSTCLK1": { + "from_pin": "TSTCLK1", + "to_pin": "OUT" + }, + "DRPCLKINV:DRPCLK": { + "from_pin": "DRPCLK", + "to_pin": "OUT" + }, + "TXUSRCLK2INV:TXUSRCLK2_B": { + "from_pin": "TXUSRCLK2_B", + "to_pin": "OUT" + }, + "TXUSRCLKINV:TXUSRCLK": { + "from_pin": "TXUSRCLK", + "to_pin": "OUT" + }, + "PMASCANCLK1INV:PMASCANCLK1": { + "from_pin": "PMASCANCLK1", + "to_pin": "OUT" + }, + "SCANCLKINV:SCANCLK_B": { + "from_pin": "SCANCLK_B", + "to_pin": "OUT" + }, + "TXUSRCLK2INV:TXUSRCLK2": { + "from_pin": "TXUSRCLK2", + "to_pin": "OUT" + }, + "PMASCANCLK0INV:PMASCANCLK0_B": { + "from_pin": "PMASCANCLK0_B", + "to_pin": "OUT" + }, + "TSTCLK0INV:TSTCLK0": { + "from_pin": "TSTCLK0", + "to_pin": "OUT" + }, + "TXUSRCLKINV:TXUSRCLK_B": { + "from_pin": "TXUSRCLK_B", + "to_pin": "OUT" + }, + "SCANCLKINV:SCANCLK": { + "from_pin": "SCANCLK", + "to_pin": "OUT" + }, + "PMASCANCLK2INV:PMASCANCLK2_B": { + "from_pin": "PMASCANCLK2_B", + "to_pin": "OUT" + }, + "PMASCANCLK3INV:PMASCANCLK3": { + "from_pin": "PMASCANCLK3", + "to_pin": "OUT" + }, + "PMASCANCLK0INV:PMASCANCLK0": { + "from_pin": "PMASCANCLK0", + "to_pin": "OUT" + }, + "TSTCLK0INV:TSTCLK0_B": { + "from_pin": "TSTCLK0_B", + "to_pin": "OUT" + }, + "RXUSRCLKINV:RXUSRCLK": { + "from_pin": "RXUSRCLK", + "to_pin": "OUT" + }, + "TXPHDLYTSTCLKINV:TXPHDLYTSTCLK": { + "from_pin": "TXPHDLYTSTCLK", + "to_pin": "OUT" + }, + "DRPCLKINV:DRPCLK_B": { + "from_pin": "DRPCLK_B", + "to_pin": "OUT" + }, + "RXUSRCLK2INV:RXUSRCLK2": { + "from_pin": "RXUSRCLK2", + "to_pin": "OUT" + }, + "PMASCANCLK2INV:PMASCANCLK2": { + "from_pin": "PMASCANCLK2", + "to_pin": "OUT" + }, + "GTGREFCLKINV:GTGREFCLK": { + "from_pin": "GTGREFCLK", + "to_pin": "OUT" + }, + "GTGREFCLKINV:GTGREFCLK_B": { + "from_pin": "GTGREFCLK_B", + "to_pin": "OUT" + }, + "CPLLLOCKDETCLKINV:CPLLLOCKDETCLK_B": { + "from_pin": "CPLLLOCKDETCLK_B", + "to_pin": "OUT" + }, + "RXUSRCLKINV:RXUSRCLK_B": { + "from_pin": "RXUSRCLK_B", + "to_pin": "OUT" + }, + "EDTCLOCKINV:EDTCLOCK_B": { + "from_pin": "EDTCLOCK_B", + "to_pin": "OUT" + }, + "EDTCLOCKINV:EDTCLOCK": { + "from_pin": "EDTCLOCK", + "to_pin": "OUT" + }, + "CPLLLOCKDETCLKINV:CPLLLOCKDETCLK": { + "from_pin": "CPLLLOCKDETCLK", + "to_pin": "OUT" + }, + "PMASCANCLK4INV:PMASCANCLK4": { + "from_pin": "PMASCANCLK4", + "to_pin": "OUT" + }, + "TXPHDLYTSTCLKINV:TXPHDLYTSTCLK_B": { + "from_pin": "TXPHDLYTSTCLK_B", + "to_pin": "OUT" + }, + "PMASCANCLK1INV:PMASCANCLK1_B": { + "from_pin": "PMASCANCLK1_B", + "to_pin": "OUT" + }, + "PMASCANCLK4INV:PMASCANCLK4_B": { + "from_pin": "PMASCANCLK4_B", + "to_pin": "OUT" + }, + "TSTCLK1INV:TSTCLK1_B": { + "from_pin": "TSTCLK1_B", + "to_pin": "OUT" + }, + "RXUSRCLK2INV:RXUSRCLK2_B": { + "from_pin": "RXUSRCLK2_B", + "to_pin": "OUT" + }, + "PMASCANCLK3INV:PMASCANCLK3_B": { + "from_pin": "PMASCANCLK3_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "TXCHARDISPMODE7": { + "direction": "IN" + }, + "RXMONITOROUT0": { + "direction": "OUT" + }, + "RXCDRLOCK": { + "direction": "OUT" + }, + "RXCDRRESETRSV": { + "direction": "IN" + }, + "RXDATA3": { + "direction": "OUT" + }, + "RXHEADERVALID": { + "direction": "OUT" + }, + "PCSRSVDIN9": { + "direction": "IN" + }, + "RXDFETAP3OVRDEN": { + "direction": "IN" + }, + "PMARSVDIN1": { + "direction": "IN" + }, + "TXDATA61": { + "direction": "IN" + }, + "TSTIN15": { + "direction": "IN" + }, + "TXDIFFPD": { + "direction": "IN" + }, + "RXPHALIGNDONE": { + "direction": "OUT" + }, + "PCSRSVDIN15": { + "direction": "IN" + }, + "TXDATA34": { + "direction": "IN" + }, + "TXDATA35": { + "direction": "IN" + }, + "TXCOMWAKE": { + "direction": "IN" + }, + "RXDISPERR2": { + "direction": "OUT" + }, + "TSTIN6": { + "direction": "IN" + }, + "RXELECIDLEMODE1": { + "direction": "IN" + }, + "EYESCANTRIGGER": { + "direction": "IN" + }, + "RXDLYTESTENB": { + "direction": "IN" + }, + "PCSRSVDIN7": { + "direction": "IN" + }, + "TXDATA17": { + "direction": "IN" + }, + "TXPCSRESET": { + "direction": "IN" + }, + "RXDATA9": { + "direction": "OUT" + }, + "RXNOTINTABLE0": { + "direction": "OUT" + }, + "PCSRSVDOUT9": { + "direction": "OUT" + }, + "DRPDI0": { + "direction": "IN" + }, + "RXDFETAP3HOLD": { + "direction": "IN" + }, + "TXDATA49": { + "direction": "IN" + }, + "TXDLYTESTENB": { + "direction": "IN" + }, + "RXCHARISCOMMA4": { + "direction": "OUT" + }, + "TSTOUT1": { + "direction": "OUT" + }, + "RXPOLARITY": { + "direction": "IN" + }, + "TSTCLK0": { + "direction": "IN" + }, + "GTSOUTHREFCLK1": { + "direction": "IN" + }, + "TXCHARDISPMODE4": { + "direction": "IN" + }, + "PMASCANOUT4": { + "direction": "OUT" + }, + "TXMAINCURSOR3": { + "direction": "IN" + }, + "RXDATA20": { + "direction": "OUT" + }, + "RXOUTCLKPCS": { + "direction": "OUT" + }, + "RXDATA2": { + "direction": "OUT" + }, + "RXDFETAP2HOLD": { + "direction": "IN" + }, + "RXMONITORSEL0": { + "direction": "IN" + }, + "PCSRSVDIN14": { + "direction": "IN" + }, + "RXDATA62": { + "direction": "OUT" + }, + "TX8B10BBYPASS1": { + "direction": "IN" + }, + "EYESCANMODE": { + "direction": "IN" + }, + "RXMCOMMAALIGNEN": { + "direction": "IN" + }, + "TXOUTCLKSEL2": { + "direction": "IN" + }, + "TXPRECURSOR2": { + "direction": "IN" + }, + "TSTIN9": { + "direction": "IN" + }, + "RXOOBRESET": { + "direction": "IN" + }, + "TXCHARDISPVAL5": { + "direction": "IN" + }, + "PCSRSVDIN0": { + "direction": "IN" + }, + "RXDATA50": { + "direction": "OUT" + }, + "TSTOUT2": { + "direction": "OUT" + }, + "TXDLYHOLD": { + "direction": "IN" + }, + "TXHEADER1": { + "direction": "IN" + }, + "TSTOUT7": { + "direction": "OUT" + }, + "DRPDO4": { + "direction": "OUT" + }, + "RXMONITOROUT3": { + "direction": "OUT" + }, + "TXOUTCLKFABRIC": { + "direction": "OUT" + }, + "RXQPIEN": { + "direction": "IN" + }, + "RXPHOVRDEN": { + "direction": "IN" + }, + "RXDATA57": { + "direction": "OUT" + }, + "DMONITOROUT0": { + "direction": "OUT" + }, + "RXCHARISK6": { + "direction": "OUT" + }, + "TXDEEMPH": { + "direction": "IN" + }, + "RXRATE2": { + "direction": "IN" + }, + "DRPDI15": { + "direction": "IN" + }, + "PCSRSVDOUT8": { + "direction": "OUT" + }, + "DRPDI8": { + "direction": "IN" + }, + "CLKRSVD0": { + "direction": "IN" + }, + "RXQPISENN": { + "direction": "OUT" + }, + "TXDATA14": { + "direction": "IN" + }, + "RXDISPERR7": { + "direction": "OUT" + }, + "RXDFETAP5OVRDEN": { + "direction": "IN" + }, + "GTREFCLK0": { + "direction": "IN" + }, + "PMASCANCLK1": { + "direction": "IN" + }, + "RXCHBONDI0": { + "direction": "IN" + }, + "TXDATA42": { + "direction": "IN" + }, + "PCSRSVDIN12": { + "direction": "IN" + }, + "TXDATA26": { + "direction": "IN" + }, + "TX8B10BBYPASS5": { + "direction": "IN" + }, + "TXPHDLYTSTCLK": { + "direction": "IN" + }, + "RXPHMONITOR4": { + "direction": "OUT" + }, + "TXRUNDISP0": { + "direction": "OUT" + }, + "TSTPD0": { + "direction": "IN" + }, + "TXPHDLYRESET": { + "direction": "IN" + }, + "RXRATE0": { + "direction": "IN" + }, + "PCSRSVDOUT11": { + "direction": "OUT" + }, + "RXLPMLFKLOVRDEN": { + "direction": "IN" + }, + "DMONITOROUT4": { + "direction": "OUT" + }, + "TXELECIDLE": { + "direction": "IN" + }, + "RXDFELPMRESET": { + "direction": "IN" + }, + "TSTCLK1": { + "direction": "IN" + }, + "TXCHARDISPMODE6": { + "direction": "IN" + }, + "RXPRBSERR": { + "direction": "OUT" + }, + "TXCHARDISPVAL4": { + "direction": "IN" + }, + "DRPDO0": { + "direction": "OUT" + }, + "RXSYSCLKSEL0": { + "direction": "IN" + }, + "RXCHBONDLEVEL1": { + "direction": "IN" + }, + "RXPHMONITOR2": { + "direction": "OUT" + }, + "RXBUFSTATUS1": { + "direction": "OUT" + }, + "SCANENB": { + "direction": "IN" + }, + "TXQPISENN": { + "direction": "OUT" + }, + "EDTBYPASS": { + "direction": "IN" + }, + "RXCHARISCOMMA7": { + "direction": "OUT" + }, + "DRPDI9": { + "direction": "IN" + }, + "RXDATA60": { + "direction": "OUT" + }, + "PCSRSVDIN11": { + "direction": "IN" + }, + "TXCHARDISPVAL7": { + "direction": "IN" + }, + "TXDATA3": { + "direction": "IN" + }, + "SCANIN0": { + "direction": "IN" + }, + "RXVALID": { + "direction": "OUT" + }, + "PMASCANCLK3": { + "direction": "IN" + }, + "TXSEQUENCE6": { + "direction": "IN" + }, + "RXDATA59": { + "direction": "OUT" + }, + "DRPADDR0": { + "direction": "IN" + }, + "SCANIN1": { + "direction": "IN" + }, + "RXDATA21": { + "direction": "OUT" + }, + "RXPHSLIPMONITOR1": { + "direction": "OUT" + }, + "TXBUFDIFFCTRL2": { + "direction": "IN" + }, + "TXPD1": { + "direction": "IN" + }, + "TXRUNDISP3": { + "direction": "OUT" + }, + "RXDFEXYDEN": { + "direction": "IN" + }, + "RXCHARISK5": { + "direction": "OUT" + }, + "TXDATA16": { + "direction": "IN" + }, + "PMARSVDIN21": { + "direction": "IN" + }, + "RXCOMMADETEN": { + "direction": "IN" + }, + "RXPHSLIPMONITOR2": { + "direction": "OUT" + }, + "GTRSVD11": { + "direction": "IN" + }, + "PCSRSVDIN2": { + "direction": "IN" + }, + "TXDATA20": { + "direction": "IN" + }, + "RXPHSLIPMONITOR0": { + "direction": "OUT" + }, + "SCANIN2": { + "direction": "IN" + }, + "RXCHBONDSLAVE": { + "direction": "IN" + }, + "RXDATA22": { + "direction": "OUT" + }, + "TXMAINCURSOR2": { + "direction": "IN" + }, + "RXNOTINTABLE4": { + "direction": "OUT" + }, + "RXDATA35": { + "direction": "OUT" + }, + "DRPEN": { + "direction": "IN" + }, + "GTRSVD5": { + "direction": "IN" + }, + "RXDATA29": { + "direction": "OUT" + }, + "RXDATA33": { + "direction": "OUT" + }, + "TXDLYUPDOWN": { + "direction": "IN" + }, + "TXDATA46": { + "direction": "IN" + }, + "TXCHARISK1": { + "direction": "IN" + }, + "PCSRSVDIN22": { + "direction": "IN" + }, + "TXMARGIN1": { + "direction": "IN" + }, + "TXRUNDISP7": { + "direction": "OUT" + }, + "RXDATA32": { + "direction": "OUT" + }, + "GTNORTHREFCLK0": { + "direction": "IN" + }, + "RXCDRRESET": { + "direction": "IN" + }, + "PMASCANIN0": { + "direction": "IN" + }, + "RXDFEUTOVRDEN": { + "direction": "IN" + }, + "RXDATA36": { + "direction": "OUT" + }, + "DRPDI6": { + "direction": "IN" + }, + "SETERRSTATUS": { + "direction": "IN" + }, + "CPLLREFCLKLOST": { + "direction": "OUT" + }, + "RXCHANISALIGNED": { + "direction": "OUT" + }, + "RXDFEAGCOVRDEN": { + "direction": "IN" + }, + "TSTPDOVRDB": { + "direction": "IN" + }, + "TSTPD2": { + "direction": "IN" + }, + "RESETOVRD": { + "direction": "IN" + }, + "RXDATA5": { + "direction": "OUT" + }, + "RXCOMWAKEDET": { + "direction": "OUT" + }, + "TXMAINCURSOR0": { + "direction": "IN" + }, + "RXPCOMMAALIGNEN": { + "direction": "IN" + }, + "RXPHDLYRESET": { + "direction": "IN" + }, + "PCSRSVDIN5": { + "direction": "IN" + }, + "RXOSOVRDEN": { + "direction": "IN" + }, + "DRPDO8": { + "direction": "OUT" + }, + "TXPRECURSOR3": { + "direction": "IN" + }, + "RXDISPERR1": { + "direction": "OUT" + }, + "PMASCANMODEB": { + "direction": "IN" + }, + "TXPOLARITY": { + "direction": "IN" + }, + "GTRSVD0": { + "direction": "IN" + }, + "TXCHARISK7": { + "direction": "IN" + }, + "RXCHBONDO2": { + "direction": "OUT" + }, + "RXCHBONDLEVEL2": { + "direction": "IN" + }, + "TSTIN2": { + "direction": "IN" + }, + "RXDATA17": { + "direction": "OUT" + }, + "SCANOUT1": { + "direction": "OUT" + }, + "RXDATA46": { + "direction": "OUT" + }, + "TXCHARISK0": { + "direction": "IN" + }, + "RXCHBONDEN": { + "direction": "IN" + }, + "TXCOMSAS": { + "direction": "IN" + }, + "CPLLREFCLKSEL1": { + "direction": "IN" + }, + "SCANOUT0": { + "direction": "OUT" + }, + "RXDFETAP4OVRDEN": { + "direction": "IN" + }, + "TXPRBSFORCEERR": { + "direction": "IN" + }, + "RXCHARISCOMMA3": { + "direction": "OUT" + }, + "RXDEBUGPULSE": { + "direction": "IN" + }, + "TXDATA11": { + "direction": "IN" + }, + "RXBUFSTATUS0": { + "direction": "OUT" + }, + "RXCOMINITDET": { + "direction": "OUT" + }, + "TXQPISENP": { + "direction": "OUT" + }, + "TXPHINIT": { + "direction": "IN" + }, + "RXCHARISK3": { + "direction": "OUT" + }, + "RXMONITOROUT6": { + "direction": "OUT" + }, + "RXCHARISK4": { + "direction": "OUT" + }, + "RXDATA43": { + "direction": "OUT" + }, + "TSTIN4": { + "direction": "IN" + }, + "RXSTARTOFSEQ": { + "direction": "OUT" + }, + "TXMAINCURSOR4": { + "direction": "IN" + }, + "TXBUFDIFFCTRL1": { + "direction": "IN" + }, + "RXDATA6": { + "direction": "OUT" + }, + "TXPDELECIDLEMODE": { + "direction": "IN" + }, + "TXDATA36": { + "direction": "IN" + }, + "GTSOUTHREFCLK0": { + "direction": "IN" + }, + "TXDATA59": { + "direction": "IN" + }, + "DRPADDR5": { + "direction": "IN" + }, + "RXDISPERR4": { + "direction": "OUT" + }, + "GTXRXP": { + "direction": "IN" + }, + "RXCHARISK2": { + "direction": "OUT" + }, + "DRPDO7": { + "direction": "OUT" + }, + "TXOUTCLKSEL0": { + "direction": "IN" + }, + "RXBYTEISALIGNED": { + "direction": "OUT" + }, + "DRPDI14": { + "direction": "IN" + }, + "GTRSVD4": { + "direction": "IN" + }, + "TXRUNDISP2": { + "direction": "OUT" + }, + "RXSYSCLKSEL1": { + "direction": "IN" + }, + "TXPOSTCURSOR3": { + "direction": "IN" + }, + "LOOPBACK2": { + "direction": "IN" + }, + "TXCHARDISPVAL1": { + "direction": "IN" + }, + "RXLPMEN": { + "direction": "IN" + }, + "TXDATA18": { + "direction": "IN" + }, + "PCSRSVDOUT5": { + "direction": "OUT" + }, + "GTRSVD6": { + "direction": "IN" + }, + "RXCHARISCOMMA1": { + "direction": "OUT" + }, + "RXDLYBYPASS": { + "direction": "IN" + }, + "RXSTATUS2": { + "direction": "OUT" + }, + "RXCHBONDI2": { + "direction": "IN" + }, + "GTREFCLKMONITOR": { + "direction": "OUT" + }, + "CPLLPD": { + "direction": "IN" + }, + "TXDATA29": { + "direction": "IN" + }, + "GTRSVD14": { + "direction": "IN" + }, + "RXPHALIGNEN": { + "direction": "IN" + }, + "CPLLLOCKDETCLK": { + "direction": "IN" + }, + "TXDATA41": { + "direction": "IN" + }, + "TSTOUT3": { + "direction": "OUT" + }, + "TXPOSTCURSOR0": { + "direction": "IN" + }, + "TXOUTCLKSEL1": { + "direction": "IN" + }, + "TXDATA21": { + "direction": "IN" + }, + "RXHEADER1": { + "direction": "OUT" + }, + "CPLLREFCLKSEL0": { + "direction": "IN" + }, + "PMARSVDIN20": { + "direction": "IN" + }, + "RXDATA28": { + "direction": "OUT" + }, + "RXDATA56": { + "direction": "OUT" + }, + "TXCHARISK4": { + "direction": "IN" + }, + "TXDATA56": { + "direction": "IN" + }, + "RXCOMSASDET": { + "direction": "OUT" + }, + "DRPDI4": { + "direction": "IN" + }, + "PMASCANOUT1": { + "direction": "OUT" + }, + "TXCOMINIT": { + "direction": "IN" + }, + "TXDATA31": { + "direction": "IN" + }, + "PMASCANOUT0": { + "direction": "OUT" + }, + "DMONITOROUT1": { + "direction": "OUT" + }, + "TSTIN18": { + "direction": "IN" + }, + "DRPADDR4": { + "direction": "IN" + }, + "TXRATE2": { + "direction": "IN" + }, + "RXUSERRDY": { + "direction": "IN" + }, + "RXPRBSCNTRESET": { + "direction": "IN" + }, + "CPLLLOCKEN": { + "direction": "IN" + }, + "RXDFELFHOLD": { + "direction": "IN" + }, + "DRPADDR8": { + "direction": "IN" + }, + "RX8B10BEN": { + "direction": "IN" + }, + "SCANOUT4": { + "direction": "OUT" + }, + "TXOUTCLKPCS": { + "direction": "OUT" + }, + "RXCHBONDO4": { + "direction": "OUT" + }, + "DRPWE": { + "direction": "IN" + }, + "RXDATA27": { + "direction": "OUT" + }, + "TXQPISTRONGPDOWN": { + "direction": "IN" + }, + "RXSTATUS1": { + "direction": "OUT" + }, + "TXDATA44": { + "direction": "IN" + }, + "RXCHARISCOMMA6": { + "direction": "OUT" + }, + "PMARSVDIN22": { + "direction": "IN" + }, + "TSTOUT8": { + "direction": "OUT" + }, + "RXCHARISK7": { + "direction": "OUT" + }, + "TSTOUT4": { + "direction": "OUT" + }, + "TXCHARISK6": { + "direction": "IN" + }, + "TXSEQUENCE1": { + "direction": "IN" + }, + "TSTIN7": { + "direction": "IN" + }, + "TXDATA38": { + "direction": "IN" + }, + "TX8B10BBYPASS3": { + "direction": "IN" + }, + "TXCHARDISPMODE3": { + "direction": "IN" + }, + "RXDATA23": { + "direction": "OUT" + }, + "RXDATA16": { + "direction": "OUT" + }, + "RXDFEXYDHOLD": { + "direction": "IN" + }, + "DRPDI2": { + "direction": "IN" + }, + "RXDATA13": { + "direction": "OUT" + }, + "TXUSERRDY": { + "direction": "IN" + }, + "TXRATE0": { + "direction": "IN" + }, + "TXDATA13": { + "direction": "IN" + }, + "TXDATA4": { + "direction": "IN" + }, + "DMONITOROUT5": { + "direction": "OUT" + }, + "RXLPMHFOVRDEN": { + "direction": "IN" + }, + "RXRATE1": { + "direction": "IN" + }, + "RXDLYSRESET": { + "direction": "IN" + }, + "RXDLYEN": { + "direction": "IN" + }, + "RXELECIDLEMODE0": { + "direction": "IN" + }, + "EYESCANDATAERROR": { + "direction": "OUT" + }, + "TXDATA53": { + "direction": "IN" + }, + "DRPDO15": { + "direction": "OUT" + }, + "TXQPIBIASEN": { + "direction": "IN" + }, + "DRPDO10": { + "direction": "OUT" + }, + "TXDIFFCTRL3": { + "direction": "IN" + }, + "RXELECIDLE": { + "direction": "OUT" + }, + "RXDFEUTHOLD": { + "direction": "IN" + }, + "TXHEADER2": { + "direction": "IN" + }, + "PMASCANCLK2": { + "direction": "IN" + }, + "RXDATA45": { + "direction": "OUT" + }, + "RXDLYSRESETDONE": { + "direction": "OUT" + }, + "EDTCONFIGURATION": { + "direction": "IN" + }, + "TXDATA0": { + "direction": "IN" + }, + "RXDATA54": { + "direction": "OUT" + }, + "GTRSVD15": { + "direction": "IN" + }, + "RXDATA44": { + "direction": "OUT" + }, + "RXNOTINTABLE5": { + "direction": "OUT" + }, + "TXQPIWEAKPUP": { + "direction": "IN" + }, + "PCSRSVDOUT7": { + "direction": "OUT" + }, + "TXDATA2": { + "direction": "IN" + }, + "RXDATA48": { + "direction": "OUT" + }, + "TXDATA43": { + "direction": "IN" + }, + "RXDATA4": { + "direction": "OUT" + }, + "RXPD1": { + "direction": "IN" + }, + "RXPRBSSEL2": { + "direction": "IN" + }, + "TXDATA28": { + "direction": "IN" + }, + "TSTIN19": { + "direction": "IN" + }, + "RXDATA38": { + "direction": "OUT" + }, + "PHYSTATUS": { + "direction": "OUT" + }, + "RXDISPERR3": { + "direction": "OUT" + }, + "TXMAINCURSOR1": { + "direction": "IN" + }, + "TXDATA47": { + "direction": "IN" + }, + "PCSRSVDOUT2": { + "direction": "OUT" + }, + "TXRUNDISP6": { + "direction": "OUT" + }, + "SCANOUT3": { + "direction": "OUT" + }, + "TSTPD3": { + "direction": "IN" + }, + "RXHEADER0": { + "direction": "OUT" + }, + "PCSRSVDOUT3": { + "direction": "OUT" + }, + "TXDATA8": { + "direction": "IN" + }, + "PMASCANCLK0": { + "direction": "IN" + }, + "RXNOTINTABLE2": { + "direction": "OUT" + }, + "TSTIN3": { + "direction": "IN" + }, + "RXDATA52": { + "direction": "OUT" + }, + "RXBUFSTATUS2": { + "direction": "OUT" + }, + "TXCHARDISPMODE5": { + "direction": "IN" + }, + "TXPRBSSEL0": { + "direction": "IN" + }, + "RXDATA7": { + "direction": "OUT" + }, + "RXDLYOVRDEN": { + "direction": "IN" + }, + "DRPADDR2": { + "direction": "IN" + }, + "TXDATA58": { + "direction": "IN" + }, + "RXDFEVPHOLD": { + "direction": "IN" + }, + "PCSRSVDOUT10": { + "direction": "OUT" + }, + "GTXRXN": { + "direction": "IN" + }, + "PMASCANIN1": { + "direction": "IN" + }, + "RXRATEDONE": { + "direction": "OUT" + }, + "PCSRSVDIN8": { + "direction": "IN" + }, + "DRPDI11": { + "direction": "IN" + }, + "GTRESETSEL": { + "direction": "IN" + }, + "RXDATA19": { + "direction": "OUT" + }, + "TXOUTCLK": { + "direction": "OUT" + }, + "TXDATA52": { + "direction": "IN" + }, + "TXDATA23": { + "direction": "IN" + }, + "DRPDO3": { + "direction": "OUT" + }, + "RXDATA55": { + "direction": "OUT" + }, + "RXDATA37": { + "direction": "OUT" + }, + "RXCHANBONDSEQ": { + "direction": "OUT" + }, + "RXDATA0": { + "direction": "OUT" + }, + "RXCHANREALIGN": { + "direction": "OUT" + }, + "PCSRSVDOUT12": { + "direction": "OUT" + }, + "RXOUTCLKSEL2": { + "direction": "IN" + }, + "TXPOSTCURSOR4": { + "direction": "IN" + }, + "PCSRSVDIN13": { + "direction": "IN" + }, + "TXPRECURSORINV": { + "direction": "IN" + }, + "CLKRSVD2": { + "direction": "IN" + }, + "EDTCLOCK": { + "direction": "IN" + }, + "EDTSINGLEBYPASSCHAIN": { + "direction": "IN" + }, + "TXSTARTSEQ": { + "direction": "IN" + }, + "RXMONITORSEL1": { + "direction": "IN" + }, + "TXMARGIN0": { + "direction": "IN" + }, + "TSTIN10": { + "direction": "IN" + }, + "RXCHARISCOMMA0": { + "direction": "OUT" + }, + "RXGEARBOXSLIP": { + "direction": "IN" + }, + "TXRESETDONE": { + "direction": "OUT" + }, + "SCANMODEB": { + "direction": "IN" + }, + "TXDIFFCTRL1": { + "direction": "IN" + }, + "LOOPBACK0": { + "direction": "IN" + }, + "TXDLYSRESETDONE": { + "direction": "OUT" + }, + "SCANIN4": { + "direction": "IN" + }, + "GTRSVD9": { + "direction": "IN" + }, + "TXDATA60": { + "direction": "IN" + }, + "RXCHARISCOMMA2": { + "direction": "OUT" + }, + "RXDATA15": { + "direction": "OUT" + }, + "DRPADDR6": { + "direction": "IN" + }, + "TXPHALIGNDONE": { + "direction": "OUT" + }, + "TSTIN11": { + "direction": "IN" + }, + "GTRSVD13": { + "direction": "IN" + }, + "GTRSVD10": { + "direction": "IN" + }, + "TXDATA24": { + "direction": "IN" + }, + "DRPDO2": { + "direction": "OUT" + }, + "DRPRDY": { + "direction": "OUT" + }, + "RXBUFRESET": { + "direction": "IN" + }, + "TXPRBSSEL2": { + "direction": "IN" + }, + "RXPHSLIPMONITOR3": { + "direction": "OUT" + }, + "RXDATA14": { + "direction": "OUT" + }, + "PMARSVDIN2": { + "direction": "IN" + }, + "RXDISPERR0": { + "direction": "OUT" + }, + "TSTPD1": { + "direction": "IN" + }, + "RXDATA26": { + "direction": "OUT" + }, + "PCSRSVDOUT14": { + "direction": "OUT" + }, + "TXDATA9": { + "direction": "IN" + }, + "TSTIN16": { + "direction": "IN" + }, + "RXDFEAGCHOLD": { + "direction": "IN" + }, + "DRPCLK": { + "direction": "IN" + }, + "PCSRSVDIN1": { + "direction": "IN" + }, + "RXCHARISK0": { + "direction": "OUT" + }, + "RXDATA12": { + "direction": "OUT" + }, + "RXDATA40": { + "direction": "OUT" + }, + "SCANOUT2": { + "direction": "OUT" + }, + "TX8B10BBYPASS7": { + "direction": "IN" + }, + "RXCHBONDI3": { + "direction": "IN" + }, + "PMASCANIN4": { + "direction": "IN" + }, + "LOOPBACK1": { + "direction": "IN" + }, + "RXPHMONITOR3": { + "direction": "OUT" + }, + "RXLPMHFHOLD": { + "direction": "IN" + }, + "TX8B10BBYPASS2": { + "direction": "IN" + }, + "PMASCANIN3": { + "direction": "IN" + }, + "RXPMARESET": { + "direction": "IN" + }, + "TXRUNDISP4": { + "direction": "OUT" + }, + "GTRSVD12": { + "direction": "IN" + }, + "PCSRSVDIN6": { + "direction": "IN" + }, + "GTTXRESET": { + "direction": "IN" + }, + "TXSEQUENCE4": { + "direction": "IN" + }, + "TXPHALIGN": { + "direction": "IN" + }, + "RXDATA11": { + "direction": "OUT" + }, + "PMARSVDIN24": { + "direction": "IN" + }, + "CLKRSVD3": { + "direction": "IN" + }, + "TXSWING": { + "direction": "IN" + }, + "DRPADDR7": { + "direction": "IN" + }, + "GTRSVD8": { + "direction": "IN" + }, + "CPLLREFCLKSEL2": { + "direction": "IN" + }, + "TXPD0": { + "direction": "IN" + }, + "RXCHBONDO1": { + "direction": "OUT" + }, + "TXDATA55": { + "direction": "IN" + }, + "TX8B10BBYPASS4": { + "direction": "IN" + }, + "PMASCANOUT2": { + "direction": "OUT" + }, + "RXDFELFOVRDEN": { + "direction": "IN" + }, + "RXPHDLYPD": { + "direction": "IN" + }, + "TXDATA30": { + "direction": "IN" + }, + "TXCHARDISPVAL2": { + "direction": "IN" + }, + "GTNORTHREFCLK1": { + "direction": "IN" + }, + "GTRSVD2": { + "direction": "IN" + }, + "TXDATA48": { + "direction": "IN" + }, + "TXPOSTCURSOR2": { + "direction": "IN" + }, + "RXCLKCORCNT0": { + "direction": "OUT" + }, + "TXPHALIGNEN": { + "direction": "IN" + }, + "TXBUFSTATUS0": { + "direction": "OUT" + }, + "TXPOSTCURSORINV": { + "direction": "IN" + }, + "EDTUPDATE": { + "direction": "IN" + }, + "DRPDO14": { + "direction": "OUT" + }, + "QPLLREFCLK": { + "direction": "IN" + }, + "RXDFEVSEN": { + "direction": "IN" + }, + "RXDISPERR5": { + "direction": "OUT" + }, + "TX8B10BBYPASS6": { + "direction": "IN" + }, + "DRPDO9": { + "direction": "OUT" + }, + "TXDATA32": { + "direction": "IN" + }, + "TXDATA50": { + "direction": "IN" + }, + "TXCOMFINISH": { + "direction": "OUT" + }, + "TSTIN13": { + "direction": "IN" + }, + "TXMAINCURSOR5": { + "direction": "IN" + }, + "RXDATA30": { + "direction": "OUT" + }, + "RXMONITOROUT1": { + "direction": "OUT" + }, + "PCSRSVDIN24": { + "direction": "IN" + }, + "PCSRSVDOUT13": { + "direction": "OUT" + }, + "RXCHBONDI4": { + "direction": "IN" + }, + "SCANIN3": { + "direction": "IN" + }, + "GTRSVD1": { + "direction": "IN" + }, + "TXSEQUENCE0": { + "direction": "IN" + }, + "PMASCANIN2": { + "direction": "IN" + }, + "TSTOUT6": { + "direction": "OUT" + }, + "PMASCANENB": { + "direction": "IN" + }, + "RXNOTINTABLE7": { + "direction": "OUT" + }, + "DRPADDR3": { + "direction": "IN" + }, + "TXSYSCLKSEL0": { + "direction": "IN" + }, + "DRPDI3": { + "direction": "IN" + }, + "RXDATA10": { + "direction": "OUT" + }, + "TXDATA62": { + "direction": "IN" + }, + "RXCHBONDO3": { + "direction": "OUT" + }, + "RXPHSLIPMONITOR4": { + "direction": "OUT" + }, + "TXDLYOVRDEN": { + "direction": "IN" + }, + "TXDATA33": { + "direction": "IN" + }, + "TXDATA12": { + "direction": "IN" + }, + "TXDATA7": { + "direction": "IN" + }, + "RXOUTCLKFABRIC": { + "direction": "OUT" + }, + "TXBUFDIFFCTRL0": { + "direction": "IN" + }, + "RXDFETAP2OVRDEN": { + "direction": "IN" + }, + "PCSRSVDIN20": { + "direction": "IN" + }, + "RXPD0": { + "direction": "IN" + }, + "TSTIN8": { + "direction": "IN" + }, + "TXPRECURSOR1": { + "direction": "IN" + }, + "GTREFCLK1": { + "direction": "IN" + }, + "TSTIN0": { + "direction": "IN" + }, + "TXPOSTCURSOR1": { + "direction": "IN" + }, + "DMONITOROUT3": { + "direction": "OUT" + }, + "CLKRSVD1": { + "direction": "IN" + }, + "TXDATA1": { + "direction": "IN" + }, + "RXQPISENP": { + "direction": "OUT" + }, + "TXRATE1": { + "direction": "IN" + }, + "RXDFEVPOVRDEN": { + "direction": "IN" + }, + "RXDATA47": { + "direction": "OUT" + }, + "TXCHARISK3": { + "direction": "IN" + }, + "TXRUNDISP5": { + "direction": "OUT" + }, + "TXDATA6": { + "direction": "IN" + }, + "RXPHMONITOR1": { + "direction": "OUT" + }, + "TXDATA5": { + "direction": "IN" + }, + "RXCDROVRDEN": { + "direction": "IN" + }, + "TXDLYSRESET": { + "direction": "IN" + }, + "DMONITOROUT2": { + "direction": "OUT" + }, + "RXDATA51": { + "direction": "OUT" + }, + "RXDATA41": { + "direction": "OUT" + }, + "TXDATA51": { + "direction": "IN" + }, + "TXDATA54": { + "direction": "IN" + }, + "PMASCANOUT3": { + "direction": "OUT" + }, + "RXCDRHOLD": { + "direction": "IN" + }, + "GTRSVD3": { + "direction": "IN" + }, + "TX8B10BBYPASS0": { + "direction": "IN" + }, + "TXPHINITDONE": { + "direction": "OUT" + }, + "RXDATA53": { + "direction": "OUT" + }, + "PCSRSVDOUT4": { + "direction": "OUT" + }, + "TXCHARDISPMODE2": { + "direction": "IN" + }, + "RXDATA49": { + "direction": "OUT" + }, + "TXDATA25": { + "direction": "IN" + }, + "RXMONITOROUT2": { + "direction": "OUT" + }, + "DRPDI7": { + "direction": "IN" + }, + "TXUSRCLK2": { + "direction": "IN" + }, + "RXDATA61": { + "direction": "OUT" + }, + "PMARSVDIN23": { + "direction": "IN" + }, + "TSTIN1": { + "direction": "IN" + }, + "PCSRSVDOUT15": { + "direction": "OUT" + }, + "QPLLCLK": { + "direction": "IN" + }, + "RXSLIDE": { + "direction": "IN" + }, + "PCSRSVDIN10": { + "direction": "IN" + }, + "PMASCANRSTEN": { + "direction": "IN" + }, + "RXDATA34": { + "direction": "OUT" + }, + "RXRESETDONE": { + "direction": "OUT" + }, + "TXDATA19": { + "direction": "IN" + }, + "TXPHDLYPD": { + "direction": "IN" + }, + "EYESCANRESET": { + "direction": "IN" + }, + "RXDFECM1EN": { + "direction": "IN" + }, + "RXCDRFREQRESET": { + "direction": "IN" + }, + "TSTOUT0": { + "direction": "OUT" + }, + "TXDATA39": { + "direction": "IN" + }, + "TXHEADER0": { + "direction": "IN" + }, + "TXINHIBIT": { + "direction": "IN" + }, + "TXDETECTRX": { + "direction": "IN" + }, + "DRPDI13": { + "direction": "IN" + }, + "TXCHARDISPVAL6": { + "direction": "IN" + }, + "RXDATA25": { + "direction": "OUT" + }, + "RXDATA8": { + "direction": "OUT" + }, + "DRPADDR1": { + "direction": "IN" + }, + "RXCOMMADET": { + "direction": "OUT" + }, + "GTGREFCLK": { + "direction": "IN" + }, + "DRPDI1": { + "direction": "IN" + }, + "CPLLFBCLKLOST": { + "direction": "OUT" + }, + "RXOUTCLK": { + "direction": "OUT" + }, + "TXRATEDONE": { + "direction": "OUT" + }, + "TXDIFFCTRL2": { + "direction": "IN" + }, + "PMARSVDIN4": { + "direction": "IN" + }, + "DRPDI10": { + "direction": "IN" + }, + "TXMAINCURSOR6": { + "direction": "IN" + }, + "PCSRSVDIN23": { + "direction": "IN" + }, + "RXDATA1": { + "direction": "OUT" + }, + "CFGRESET": { + "direction": "IN" + }, + "RXSTATUS0": { + "direction": "OUT" + }, + "TXSEQUENCE2": { + "direction": "IN" + }, + "TXBUFSTATUS1": { + "direction": "OUT" + }, + "TXDATA45": { + "direction": "IN" + }, + "PCSRSVDOUT0": { + "direction": "OUT" + }, + "RXPRBSSEL1": { + "direction": "IN" + }, + "PCSRSVDIN4": { + "direction": "IN" + }, + "RXLPMLFHOLD": { + "direction": "IN" + }, + "DRPDI12": { + "direction": "IN" + }, + "TXPISOPD": { + "direction": "IN" + }, + "TXCHARISK5": { + "direction": "IN" + }, + "TSTOUT9": { + "direction": "OUT" + }, + "GTXTXP": { + "direction": "OUT" + }, + "RXDATA58": { + "direction": "OUT" + }, + "RXDATA42": { + "direction": "OUT" + }, + "RXDISPERR6": { + "direction": "OUT" + }, + "RXPCD1DONE": { + "direction": "OUT" + }, + "RXOSHOLD": { + "direction": "IN" + }, + "DRPDO5": { + "direction": "OUT" + }, + "TXRUNDISP1": { + "direction": "OUT" + }, + "TXDATA22": { + "direction": "IN" + }, + "TXDATA63": { + "direction": "IN" + }, + "TXDATA57": { + "direction": "IN" + }, + "GTRSVD7": { + "direction": "IN" + }, + "TXDATA40": { + "direction": "IN" + }, + "TX8B10BEN": { + "direction": "IN" + }, + "CPLLRESET": { + "direction": "IN" + }, + "RXDATA39": { + "direction": "OUT" + }, + "TXDATA27": { + "direction": "IN" + }, + "TXCHARDISPMODE0": { + "direction": "IN" + }, + "RXDATA18": { + "direction": "OUT" + }, + "RXDATA31": { + "direction": "OUT" + }, + "PCSRSVDOUT1": { + "direction": "OUT" + }, + "TSTIN14": { + "direction": "IN" + }, + "DRPDO13": { + "direction": "OUT" + }, + "TSTIN17": { + "direction": "IN" + }, + "TXPRECURSOR4": { + "direction": "IN" + }, + "RXCHARISCOMMA5": { + "direction": "OUT" + }, + "RXBYTEREALIGN": { + "direction": "OUT" + }, + "TXDATA37": { + "direction": "IN" + }, + "RXDATA63": { + "direction": "OUT" + }, + "DRPDO11": { + "direction": "OUT" + }, + "TXCHARISK2": { + "direction": "IN" + }, + "TXSEQUENCE5": { + "direction": "IN" + }, + "TXCHARDISPMODE1": { + "direction": "IN" + }, + "TXDLYEN": { + "direction": "IN" + }, + "TXPHOVRDEN": { + "direction": "IN" + }, + "TSTIN5": { + "direction": "IN" + }, + "TSTIN12": { + "direction": "IN" + }, + "RXMONITOROUT4": { + "direction": "OUT" + }, + "TXUSRCLK": { + "direction": "IN" + }, + "RXDFETAP5HOLD": { + "direction": "IN" + }, + "RXNOTINTABLE6": { + "direction": "OUT" + }, + "DMONITOROUT6": { + "direction": "OUT" + }, + "RXPRBSSEL0": { + "direction": "IN" + }, + "RXOUTCLKSEL0": { + "direction": "IN" + }, + "RXDATA24": { + "direction": "OUT" + }, + "TXSEQUENCE3": { + "direction": "IN" + }, + "TXPRBSSEL1": { + "direction": "IN" + }, + "RXUSRCLK": { + "direction": "IN" + }, + "GTXTXN": { + "direction": "OUT" + }, + "TSTOUT5": { + "direction": "OUT" + }, + "TXCHARDISPVAL0": { + "direction": "IN" + }, + "RXDFETAP4HOLD": { + "direction": "IN" + }, + "RXUSRCLK2": { + "direction": "IN" + }, + "CPLLLOCK": { + "direction": "OUT" + }, + "DRPDO1": { + "direction": "OUT" + }, + "PMARSVDIN3": { + "direction": "IN" + }, + "RXNOTINTABLE1": { + "direction": "OUT" + }, + "DRPDI5": { + "direction": "IN" + }, + "RXCHBONDMASTER": { + "direction": "IN" + }, + "RXDATAVALID": { + "direction": "OUT" + }, + "DRPDO12": { + "direction": "OUT" + }, + "TXPRECURSOR0": { + "direction": "IN" + }, + "RXOUTCLKSEL1": { + "direction": "IN" + }, + "GTRXRESET": { + "direction": "IN" + }, + "TXDIFFCTRL0": { + "direction": "IN" + }, + "RXCHBONDI1": { + "direction": "IN" + }, + "RXPHALIGN": { + "direction": "IN" + }, + "PMASCANCLK4": { + "direction": "IN" + }, + "TXDATA10": { + "direction": "IN" + }, + "RXCHARISK1": { + "direction": "OUT" + }, + "RXMONITOROUT5": { + "direction": "OUT" + }, + "RXHEADER2": { + "direction": "OUT" + }, + "PCSRSVDIN21": { + "direction": "IN" + }, + "TXSYSCLKSEL1": { + "direction": "IN" + }, + "DRPDO6": { + "direction": "OUT" + }, + "RXPCSRESET": { + "direction": "IN" + }, + "RXPHMONITOR0": { + "direction": "OUT" + }, + "RXNOTINTABLE3": { + "direction": "OUT" + }, + "TXCHARDISPVAL3": { + "direction": "IN" + }, + "RXDFEXYDOVRDEN": { + "direction": "IN" + }, + "TXDATA15": { + "direction": "IN" + }, + "RXCHBONDLEVEL0": { + "direction": "IN" + }, + "RXDDIEN": { + "direction": "IN" + }, + "SCANCLK": { + "direction": "IN" + }, + "TXPMARESET": { + "direction": "IN" + }, + "DMONITOROUT7": { + "direction": "OUT" + }, + "TXDLYBYPASS": { + "direction": "IN" + }, + "TXGEARBOXREADY": { + "direction": "OUT" + }, + "RXCLKCORCNT1": { + "direction": "OUT" + }, + "PMARSVDIN0": { + "direction": "IN" + }, + "TXMARGIN2": { + "direction": "IN" + }, + "PCSRSVDOUT6": { + "direction": "OUT" + }, + "RXCHBONDO0": { + "direction": "OUT" + }, + "PCSRSVDIN3": { + "direction": "IN" + }, + "TSTPD4": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_GTXE2_COMMON.json b/kintex7/site_type_GTXE2_COMMON.json new file mode 100644 index 0000000..d4eaba8 --- /dev/null +++ b/kintex7/site_type_GTXE2_COMMON.json @@ -0,0 +1,447 @@ +{ + "type": "GTXE2_COMMON", + "site_pips": { + "DRPCLKINV:DRPCLK": { + "from_pin": "DRPCLK", + "to_pin": "OUT" + }, + "QPLLCLKSPARE0INV:QPLLCLKSPARE0": { + "from_pin": "QPLLCLKSPARE0", + "to_pin": "OUT" + }, + "DRPCLKINV:DRPCLK_B": { + "from_pin": "DRPCLK_B", + "to_pin": "OUT" + }, + "PMASCANCLK1INV:PMASCANCLK1": { + "from_pin": "PMASCANCLK1", + "to_pin": "OUT" + }, + "QPLLCLKSPARE1INV:QPLLCLKSPARE1_B": { + "from_pin": "QPLLCLKSPARE1_B", + "to_pin": "OUT" + }, + "PMASCANCLK0INV:PMASCANCLK0_B": { + "from_pin": "PMASCANCLK0_B", + "to_pin": "OUT" + }, + "GTGREFCLKINV:GTGREFCLK": { + "from_pin": "GTGREFCLK", + "to_pin": "OUT" + }, + "QPLLLOCKDETCLKINV:QPLLLOCKDETCLK_B": { + "from_pin": "QPLLLOCKDETCLK_B", + "to_pin": "OUT" + }, + "QPLLLOCKDETCLKINV:QPLLLOCKDETCLK": { + "from_pin": "QPLLLOCKDETCLK", + "to_pin": "OUT" + }, + "GTGREFCLKINV:GTGREFCLK_B": { + "from_pin": "GTGREFCLK_B", + "to_pin": "OUT" + }, + "QPLLCLKSPARE0INV:QPLLCLKSPARE0_B": { + "from_pin": "QPLLCLKSPARE0_B", + "to_pin": "OUT" + }, + "PMASCANCLK1INV:PMASCANCLK1_B": { + "from_pin": "PMASCANCLK1_B", + "to_pin": "OUT" + }, + "PMASCANCLK0INV:PMASCANCLK0": { + "from_pin": "PMASCANCLK0", + "to_pin": "OUT" + }, + "QPLLCLKSPARE1INV:QPLLCLKSPARE1": { + "from_pin": "QPLLCLKSPARE1", + "to_pin": "OUT" + } + }, + "site_pins": { + "QPLLLOCKEN": { + "direction": "IN" + }, + "QPLLRSVD23": { + "direction": "IN" + }, + "PMASCANOUT3": { + "direction": "OUT" + }, + "BGPDB": { + "direction": "IN" + }, + "QPLLRSVD111": { + "direction": "IN" + }, + "QPLLREFCLKSEL2": { + "direction": "IN" + }, + "BGMONITORENB": { + "direction": "IN" + }, + "QPLLREFCLKSEL1": { + "direction": "IN" + }, + "QPLLDMONITOR5": { + "direction": "OUT" + }, + "DRPDO8": { + "direction": "OUT" + }, + "QPLLCLKSPARE0": { + "direction": "IN" + }, + "DRPDO5": { + "direction": "OUT" + }, + "BGRCALOVRD0": { + "direction": "IN" + }, + "QPLLDMONITOR2": { + "direction": "OUT" + }, + "QPLLRSVD12": { + "direction": "IN" + }, + "QPLLRSVD22": { + "direction": "IN" + }, + "DRPDI4": { + "direction": "IN" + }, + "BGRCALOVRD2": { + "direction": "IN" + }, + "QPLLOUTREFCLK": { + "direction": "OUT" + }, + "QDPMASCANMODEB": { + "direction": "IN" + }, + "PMASCANIN0": { + "direction": "IN" + }, + "DRPDO2": { + "direction": "OUT" + }, + "PMASCANOUT0": { + "direction": "OUT" + }, + "QPLLLOCK": { + "direction": "OUT" + }, + "QPLLRSVD20": { + "direction": "IN" + }, + "QPLLRSVD21": { + "direction": "IN" + }, + "DRPADDR4": { + "direction": "IN" + }, + "QPLLRESET": { + "direction": "IN" + }, + "QPLLDMONITOR6": { + "direction": "OUT" + }, + "DRPADDR7": { + "direction": "IN" + }, + "DRPDO0": { + "direction": "OUT" + }, + "QPLLRSVD14": { + "direction": "IN" + }, + "QPLLLOCKDETCLK": { + "direction": "IN" + }, + "PMARSVD5": { + "direction": "IN" + }, + "QPLLRSVD15": { + "direction": "IN" + }, + "PMASCANIN1": { + "direction": "IN" + }, + "DRPDO12": { + "direction": "OUT" + }, + "DRPDO13": { + "direction": "OUT" + }, + "QPLLRSVD19": { + "direction": "IN" + }, + "PMASCANIN4": { + "direction": "IN" + }, + "DRPDI11": { + "direction": "IN" + }, + "DRPDI7": { + "direction": "IN" + }, + "QPLLREFCLKSEL0": { + "direction": "IN" + }, + "PMARSVD1": { + "direction": "IN" + }, + "DRPDO11": { + "direction": "OUT" + }, + "QPLLRSVD10": { + "direction": "IN" + }, + "DRPADDR2": { + "direction": "IN" + }, + "DRPDI0": { + "direction": "IN" + }, + "DRPDO3": { + "direction": "OUT" + }, + "BGBYPASSB": { + "direction": "IN" + }, + "GTSOUTHREFCLK1": { + "direction": "IN" + }, + "PMARSVD7": { + "direction": "IN" + }, + "GTREFCLK0": { + "direction": "IN" + }, + "QPLLOUTRESET": { + "direction": "IN" + }, + "PMASCANOUT4": { + "direction": "OUT" + }, + "GTNORTHREFCLK1": { + "direction": "IN" + }, + "QPLLOUTCLK": { + "direction": "OUT" + }, + "QPLLRSVD18": { + "direction": "IN" + }, + "DRPADDR0": { + "direction": "IN" + }, + "QPLLDMONITOR4": { + "direction": "OUT" + }, + "QPLLDMONITOR0": { + "direction": "OUT" + }, + "QPLLRSVD115": { + "direction": "IN" + }, + "PMARSVD0": { + "direction": "IN" + }, + "PMASCANOUT2": { + "direction": "OUT" + }, + "DRPADDR3": { + "direction": "IN" + }, + "DRPDO14": { + "direction": "OUT" + }, + "BGRCALOVRD3": { + "direction": "IN" + }, + "DRPDI13": { + "direction": "IN" + }, + "DRPDI9": { + "direction": "IN" + }, + "DRPDO9": { + "direction": "OUT" + }, + "DRPDO10": { + "direction": "OUT" + }, + "GTSOUTHREFCLK0": { + "direction": "IN" + }, + "QPLLREFCLKLOST": { + "direction": "OUT" + }, + "QPLLRSVD112": { + "direction": "IN" + }, + "QPLLDMONITOR7": { + "direction": "OUT" + }, + "PMARSVD6": { + "direction": "IN" + }, + "DRPADDR1": { + "direction": "IN" + }, + "DRPADDR5": { + "direction": "IN" + }, + "PMARSVD3": { + "direction": "IN" + }, + "QPLLRSVD24": { + "direction": "IN" + }, + "QPLLRSVD13": { + "direction": "IN" + }, + "DRPDO1": { + "direction": "OUT" + }, + "PMARSVD2": { + "direction": "IN" + }, + "DRPDI1": { + "direction": "IN" + }, + "DRPDO7": { + "direction": "OUT" + }, + "QPLLRSVD113": { + "direction": "IN" + }, + "BGRCALOVRD4": { + "direction": "IN" + }, + "DRPDI5": { + "direction": "IN" + }, + "DRPEN": { + "direction": "IN" + }, + "QPLLFBCLKLOST": { + "direction": "OUT" + }, + "QPLLDMONITOR3": { + "direction": "OUT" + }, + "PMASCANCLK0": { + "direction": "IN" + }, + "DRPDI10": { + "direction": "IN" + }, + "PMASCANENB": { + "direction": "IN" + }, + "DRPDI14": { + "direction": "IN" + }, + "PMASCANOUT1": { + "direction": "OUT" + }, + "DRPDO15": { + "direction": "OUT" + }, + "QPLLRSVD17": { + "direction": "IN" + }, + "QPLLRSVD110": { + "direction": "IN" + }, + "DRPADDR6": { + "direction": "IN" + }, + "DRPDI3": { + "direction": "IN" + }, + "GTGREFCLK": { + "direction": "IN" + }, + "QPLLRSVD11": { + "direction": "IN" + }, + "RCALENB": { + "direction": "IN" + }, + "QPLLRSVD114": { + "direction": "IN" + }, + "PMARSVD4": { + "direction": "IN" + }, + "QPLLPD": { + "direction": "IN" + }, + "DRPDI15": { + "direction": "IN" + }, + "DRPDI8": { + "direction": "IN" + }, + "DRPCLK": { + "direction": "IN" + }, + "GTNORTHREFCLK0": { + "direction": "IN" + }, + "QPLLRSVD16": { + "direction": "IN" + }, + "QPLLCLKSPARE1": { + "direction": "IN" + }, + "DRPRDY": { + "direction": "OUT" + }, + "DRPDO6": { + "direction": "OUT" + }, + "REFCLKOUTMONITOR": { + "direction": "OUT" + }, + "DRPDI12": { + "direction": "IN" + }, + "QDPMASCANRSTEN": { + "direction": "IN" + }, + "DRPDI6": { + "direction": "IN" + }, + "QPLLDMONITOR1": { + "direction": "OUT" + }, + "DRPWE": { + "direction": "IN" + }, + "PMASCANCLK1": { + "direction": "IN" + }, + "GTREFCLK1": { + "direction": "IN" + }, + "DRPDI2": { + "direction": "IN" + }, + "PMASCANIN3": { + "direction": "IN" + }, + "PMASCANIN2": { + "direction": "IN" + }, + "BGRCALOVRD1": { + "direction": "IN" + }, + "DRPDO4": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_IBUFDS_GTE2.json b/kintex7/site_type_IBUFDS_GTE2.json new file mode 100644 index 0000000..79ed2ab --- /dev/null +++ b/kintex7/site_type_IBUFDS_GTE2.json @@ -0,0 +1,33 @@ +{ + "type": "IBUFDS_GTE2", + "site_pips": { + "CLKTESTSIGINV:CLKTESTSIG_B": { + "from_pin": "CLKTESTSIG_B", + "to_pin": "OUT" + }, + "CLKTESTSIGINV:CLKTESTSIG": { + "from_pin": "CLKTESTSIG", + "to_pin": "OUT" + } + }, + "site_pins": { + "I": { + "direction": "IN" + }, + "CEB": { + "direction": "IN" + }, + "ODIV2": { + "direction": "OUT" + }, + "IB": { + "direction": "IN" + }, + "O": { + "direction": "OUT" + }, + "CLKTESTSIG": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_ICAP.json b/kintex7/site_type_ICAP.json new file mode 100644 index 0000000..7d2bc62 --- /dev/null +++ b/kintex7/site_type_ICAP.json @@ -0,0 +1,207 @@ +{ + "type": "ICAP", + "site_pips": {}, + "site_pins": { + "O13": { + "direction": "OUT" + }, + "I8": { + "direction": "IN" + }, + "I4": { + "direction": "IN" + }, + "O14": { + "direction": "OUT" + }, + "O4": { + "direction": "OUT" + }, + "O22": { + "direction": "OUT" + }, + "O7": { + "direction": "OUT" + }, + "O9": { + "direction": "OUT" + }, + "I25": { + "direction": "IN" + }, + "O6": { + "direction": "OUT" + }, + "I14": { + "direction": "IN" + }, + "O12": { + "direction": "OUT" + }, + "I31": { + "direction": "IN" + }, + "I2": { + "direction": "IN" + }, + "I13": { + "direction": "IN" + }, + "I21": { + "direction": "IN" + }, + "O1": { + "direction": "OUT" + }, + "O20": { + "direction": "OUT" + }, + "I5": { + "direction": "IN" + }, + "O25": { + "direction": "OUT" + }, + "I1": { + "direction": "IN" + }, + "I29": { + "direction": "IN" + }, + "I19": { + "direction": "IN" + }, + "I23": { + "direction": "IN" + }, + "O28": { + "direction": "OUT" + }, + "O0": { + "direction": "OUT" + }, + "O5": { + "direction": "OUT" + }, + "O23": { + "direction": "OUT" + }, + "CLK": { + "direction": "IN" + }, + "I10": { + "direction": "IN" + }, + "I9": { + "direction": "IN" + }, + "O10": { + "direction": "OUT" + }, + "I24": { + "direction": "IN" + }, + "I17": { + "direction": "IN" + }, + "O2": { + "direction": "OUT" + }, + "O19": { + "direction": "OUT" + }, + "O27": { + "direction": "OUT" + }, + "I6": { + "direction": "IN" + }, + "O30": { + "direction": "OUT" + }, + "I27": { + "direction": "IN" + }, + "I18": { + "direction": "IN" + }, + "O8": { + "direction": "OUT" + }, + "I16": { + "direction": "IN" + }, + "RDWRB": { + "direction": "IN" + }, + "O15": { + "direction": "OUT" + }, + "I20": { + "direction": "IN" + }, + "I12": { + "direction": "IN" + }, + "I28": { + "direction": "IN" + }, + "I3": { + "direction": "IN" + }, + "I30": { + "direction": "IN" + }, + "O29": { + "direction": "OUT" + }, + "O31": { + "direction": "OUT" + }, + "I22": { + "direction": "IN" + }, + "O18": { + "direction": "OUT" + }, + "CSIB": { + "direction": "IN" + }, + "O21": { + "direction": "OUT" + }, + "O26": { + "direction": "OUT" + }, + "O17": { + "direction": "OUT" + }, + "O3": { + "direction": "OUT" + }, + "O24": { + "direction": "OUT" + }, + "I11": { + "direction": "IN" + }, + "O11": { + "direction": "OUT" + }, + "I0": { + "direction": "IN" + }, + "I15": { + "direction": "IN" + }, + "I26": { + "direction": "IN" + }, + "I7": { + "direction": "IN" + }, + "O16": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_IDELAYCTRL.json b/kintex7/site_type_IDELAYCTRL.json new file mode 100644 index 0000000..cfe9f3a --- /dev/null +++ b/kintex7/site_type_IDELAYCTRL.json @@ -0,0 +1,27 @@ +{ + "type": "IDELAYCTRL", + "site_pips": {}, + "site_pins": { + "UPPULSEOUT": { + "direction": "OUT" + }, + "RST": { + "direction": "IN" + }, + "RDY": { + "direction": "OUT" + }, + "OUTN65": { + "direction": "OUT" + }, + "OUTN1": { + "direction": "OUT" + }, + "DNPULSEOUT": { + "direction": "OUT" + }, + "REFCLK": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_IDELAYE2.json b/kintex7/site_type_IDELAYE2.json new file mode 100644 index 0000000..1e35999 --- /dev/null +++ b/kintex7/site_type_IDELAYE2.json @@ -0,0 +1,100 @@ +{ + "type": "IDELAYE2", + "site_pips": { + "IDATAININV:IDATAIN": { + "from_pin": "IDATAIN", + "to_pin": "OUT" + }, + "CINV:C_B": { + "from_pin": "C_B", + "to_pin": "OUT" + }, + "DATAININV:DATAIN": { + "from_pin": "DATAIN", + "to_pin": "OUT" + }, + "DATAININV:DATAIN_B": { + "from_pin": "DATAIN_B", + "to_pin": "OUT" + }, + "CINV:C": { + "from_pin": "C", + "to_pin": "OUT" + }, + "IDATAININV:IDATAIN_B": { + "from_pin": "IDATAIN_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "CNTVALUEOUT1": { + "direction": "OUT" + }, + "IFDLY0": { + "direction": "IN" + }, + "DATAIN": { + "direction": "IN" + }, + "CNTVALUEIN1": { + "direction": "IN" + }, + "CE": { + "direction": "IN" + }, + "IDATAIN": { + "direction": "IN" + }, + "DATAOUT": { + "direction": "OUT" + }, + "CNTVALUEIN0": { + "direction": "IN" + }, + "C": { + "direction": "IN" + }, + "CNTVALUEOUT2": { + "direction": "OUT" + }, + "CNTVALUEIN4": { + "direction": "IN" + }, + "CNTVALUEOUT0": { + "direction": "OUT" + }, + "CNTVALUEIN2": { + "direction": "IN" + }, + "LDPIPEEN": { + "direction": "IN" + }, + "IFDLY1": { + "direction": "IN" + }, + "CINVCTRL": { + "direction": "IN" + }, + "CNTVALUEOUT3": { + "direction": "OUT" + }, + "INC": { + "direction": "IN" + }, + "REGRST": { + "direction": "IN" + }, + "CNTVALUEIN3": { + "direction": "IN" + }, + "CNTVALUEOUT4": { + "direction": "OUT" + }, + "IFDLY2": { + "direction": "IN" + }, + "LD": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_IDELAYE2_FINEDELAY.json b/kintex7/site_type_IDELAYE2_FINEDELAY.json new file mode 100644 index 0000000..ff95305 --- /dev/null +++ b/kintex7/site_type_IDELAYE2_FINEDELAY.json @@ -0,0 +1,100 @@ +{ + "type": "IDELAYE2_FINEDELAY", + "site_pips": { + "IDATAININV:IDATAIN": { + "from_pin": "IDATAIN", + "to_pin": "OUT" + }, + "CINV:C_B": { + "from_pin": "C_B", + "to_pin": "OUT" + }, + "DATAININV:DATAIN": { + "from_pin": "DATAIN", + "to_pin": "OUT" + }, + "DATAININV:DATAIN_B": { + "from_pin": "DATAIN_B", + "to_pin": "OUT" + }, + "CINV:C": { + "from_pin": "C", + "to_pin": "OUT" + }, + "IDATAININV:IDATAIN_B": { + "from_pin": "IDATAIN_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "CNTVALUEOUT1": { + "direction": "OUT" + }, + "IFDLY0": { + "direction": "IN" + }, + "DATAIN": { + "direction": "IN" + }, + "CNTVALUEIN1": { + "direction": "IN" + }, + "CE": { + "direction": "IN" + }, + "IDATAIN": { + "direction": "IN" + }, + "DATAOUT": { + "direction": "OUT" + }, + "CNTVALUEIN0": { + "direction": "IN" + }, + "C": { + "direction": "IN" + }, + "CNTVALUEOUT2": { + "direction": "OUT" + }, + "CNTVALUEIN4": { + "direction": "IN" + }, + "CNTVALUEOUT0": { + "direction": "OUT" + }, + "CNTVALUEIN2": { + "direction": "IN" + }, + "LDPIPEEN": { + "direction": "IN" + }, + "IFDLY1": { + "direction": "IN" + }, + "CINVCTRL": { + "direction": "IN" + }, + "CNTVALUEOUT3": { + "direction": "OUT" + }, + "INC": { + "direction": "IN" + }, + "REGRST": { + "direction": "IN" + }, + "CNTVALUEIN3": { + "direction": "IN" + }, + "CNTVALUEOUT4": { + "direction": "OUT" + }, + "IFDLY2": { + "direction": "IN" + }, + "LD": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_ILOGICE2.json b/kintex7/site_type_ILOGICE2.json new file mode 100644 index 0000000..9ed450a --- /dev/null +++ b/kintex7/site_type_ILOGICE2.json @@ -0,0 +1,184 @@ +{ + "type": "ILOGICE2", + "site_pips": { + "CLKINV:CLK": { + "from_pin": "CLK", + "to_pin": "OUT" + }, + "REVUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "CLKBINV:CLKB_B": { + "from_pin": "CLKB_B", + "to_pin": "OUT" + }, + "D2OFFBYP_SEL:T": { + "from_pin": "T", + "to_pin": "OUT" + }, + "IDELMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "D2OBYP_SEL:T": { + "from_pin": "T", + "to_pin": "OUT" + }, + "DINV:D": { + "from_pin": "D", + "to_pin": "OUT" + }, + "CLKBINV:CLKB": { + "from_pin": "CLKB", + "to_pin": "OUT" + }, + "SRUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "CE1USED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "DINV:D_B": { + "from_pin": "D_B", + "to_pin": "OUT" + }, + "IFFDELMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "D2OBYP_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + }, + "IFFMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "IMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IFFDELMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "IDELMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "IFFMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "CLKINV:CLK_B": { + "from_pin": "CLK_B", + "to_pin": "OUT" + }, + "D2OFFBYP_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + } + }, + "site_pins": { + "REV": { + "direction": "IN" + }, + "BITSLIP": { + "direction": "IN" + }, + "OFB": { + "direction": "IN" + }, + "TFB": { + "direction": "IN" + }, + "OCLK": { + "direction": "IN" + }, + "Q4": { + "direction": "OUT" + }, + "DYNCLKSEL": { + "direction": "IN" + }, + "SHIFTOUT1": { + "direction": "OUT" + }, + "CLKDIV": { + "direction": "IN" + }, + "CLKB": { + "direction": "IN" + }, + "Q5": { + "direction": "OUT" + }, + "Q8": { + "direction": "OUT" + }, + "SHIFTIN2": { + "direction": "IN" + }, + "SHIFTIN1": { + "direction": "IN" + }, + "CE1": { + "direction": "IN" + }, + "Q1": { + "direction": "OUT" + }, + "SHIFTOUT2": { + "direction": "OUT" + }, + "D": { + "direction": "IN" + }, + "DYNCLKDIVSEL": { + "direction": "IN" + }, + "DYNCLKDIVPSEL": { + "direction": "IN" + }, + "Q3": { + "direction": "OUT" + }, + "OCLKB": { + "direction": "IN" + }, + "Q6": { + "direction": "OUT" + }, + "Q2": { + "direction": "OUT" + }, + "CLK": { + "direction": "IN" + }, + "Q7": { + "direction": "OUT" + }, + "SR": { + "direction": "IN" + }, + "CLKDIVP": { + "direction": "IN" + }, + "DDLY": { + "direction": "IN" + }, + "O": { + "direction": "OUT" + }, + "CE2": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_ILOGICE3.json b/kintex7/site_type_ILOGICE3.json new file mode 100644 index 0000000..ac93018 --- /dev/null +++ b/kintex7/site_type_ILOGICE3.json @@ -0,0 +1,208 @@ +{ + "type": "ILOGICE3", + "site_pips": { + "CLKBINV:CLKB_B": { + "from_pin": "CLKB_B", + "to_pin": "OUT" + }, + "CLKINV:CLK": { + "from_pin": "CLK", + "to_pin": "OUT" + }, + "D2OBYP_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + }, + "IMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IDELMUXE3:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "DINV:D": { + "from_pin": "D", + "to_pin": "OUT" + }, + "DINV:D_B": { + "from_pin": "D_B", + "to_pin": "OUT" + }, + "D2OFFBYP_SEL:T": { + "from_pin": "T", + "to_pin": "OUT" + }, + "IFFDELMUXE3:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "CE1USED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "ZHOLD_FABRIC_INV:D": { + "from_pin": "D", + "to_pin": "OUT" + }, + "REVUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IDELMUXE3:2": { + "from_pin": "2", + "to_pin": "OUT" + }, + "ZHOLD_IFF_INV:D": { + "from_pin": "D", + "to_pin": "OUT" + }, + "D2OBYP_SEL:T": { + "from_pin": "T", + "to_pin": "OUT" + }, + "CLKBINV:CLKB": { + "from_pin": "CLKB", + "to_pin": "OUT" + }, + "SRUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "CLKINV:CLK_B": { + "from_pin": "CLK_B", + "to_pin": "OUT" + }, + "IMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "IDELMUXE3:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "IFFDELMUXE3:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IFFMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "ZHOLD_FABRIC_INV:D_B": { + "from_pin": "D_B", + "to_pin": "OUT" + }, + "IFFMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "D2OFFBYP_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + }, + "ZHOLD_IFF_INV:D_B": { + "from_pin": "D_B", + "to_pin": "OUT" + }, + "IFFDELMUXE3:2": { + "from_pin": "2", + "to_pin": "OUT" + } + }, + "site_pins": { + "REV": { + "direction": "IN" + }, + "BITSLIP": { + "direction": "IN" + }, + "OFB": { + "direction": "IN" + }, + "TFB": { + "direction": "IN" + }, + "OCLK": { + "direction": "IN" + }, + "Q4": { + "direction": "OUT" + }, + "DYNCLKSEL": { + "direction": "IN" + }, + "SHIFTOUT1": { + "direction": "OUT" + }, + "CLKDIV": { + "direction": "IN" + }, + "CLKB": { + "direction": "IN" + }, + "Q5": { + "direction": "OUT" + }, + "Q8": { + "direction": "OUT" + }, + "SHIFTIN2": { + "direction": "IN" + }, + "SHIFTIN1": { + "direction": "IN" + }, + "CE1": { + "direction": "IN" + }, + "Q1": { + "direction": "OUT" + }, + "SHIFTOUT2": { + "direction": "OUT" + }, + "D": { + "direction": "IN" + }, + "DYNCLKDIVSEL": { + "direction": "IN" + }, + "DYNCLKDIVPSEL": { + "direction": "IN" + }, + "Q3": { + "direction": "OUT" + }, + "OCLKB": { + "direction": "IN" + }, + "Q6": { + "direction": "OUT" + }, + "Q2": { + "direction": "OUT" + }, + "CLK": { + "direction": "IN" + }, + "Q7": { + "direction": "OUT" + }, + "SR": { + "direction": "IN" + }, + "CLKDIVP": { + "direction": "IN" + }, + "DDLY": { + "direction": "IN" + }, + "O": { + "direction": "OUT" + }, + "CE2": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_IN_FIFO.json b/kintex7/site_type_IN_FIFO.json new file mode 100644 index 0000000..1252987 --- /dev/null +++ b/kintex7/site_type_IN_FIFO.json @@ -0,0 +1,453 @@ +{ + "type": "IN_FIFO", + "site_pips": {}, + "site_pins": { + "Q53": { + "direction": "OUT" + }, + "ALMOSTEMPTY": { + "direction": "OUT" + }, + "Q80": { + "direction": "OUT" + }, + "D53": { + "direction": "IN" + }, + "D23": { + "direction": "IN" + }, + "D73": { + "direction": "IN" + }, + "D56": { + "direction": "IN" + }, + "Q64": { + "direction": "OUT" + }, + "Q57": { + "direction": "OUT" + }, + "Q12": { + "direction": "OUT" + }, + "D66": { + "direction": "IN" + }, + "Q44": { + "direction": "OUT" + }, + "Q41": { + "direction": "OUT" + }, + "FULL": { + "direction": "OUT" + }, + "SCANOUT3": { + "direction": "OUT" + }, + "Q22": { + "direction": "OUT" + }, + "D67": { + "direction": "IN" + }, + "Q21": { + "direction": "OUT" + }, + "WREN": { + "direction": "IN" + }, + "D31": { + "direction": "IN" + }, + "Q15": { + "direction": "OUT" + }, + "D60": { + "direction": "IN" + }, + "WRCLK": { + "direction": "IN" + }, + "Q65": { + "direction": "OUT" + }, + "Q93": { + "direction": "OUT" + }, + "Q03": { + "direction": "OUT" + }, + "D41": { + "direction": "IN" + }, + "SCANOUT1": { + "direction": "OUT" + }, + "Q76": { + "direction": "OUT" + }, + "Q60": { + "direction": "OUT" + }, + "D54": { + "direction": "IN" + }, + "TESTMODEB": { + "direction": "IN" + }, + "Q32": { + "direction": "OUT" + }, + "Q77": { + "direction": "OUT" + }, + "Q90": { + "direction": "OUT" + }, + "Q24": { + "direction": "OUT" + }, + "SCANENB": { + "direction": "IN" + }, + "Q82": { + "direction": "OUT" + }, + "Q37": { + "direction": "OUT" + }, + "Q47": { + "direction": "OUT" + }, + "Q04": { + "direction": "OUT" + }, + "Q06": { + "direction": "OUT" + }, + "Q46": { + "direction": "OUT" + }, + "D57": { + "direction": "IN" + }, + "D30": { + "direction": "IN" + }, + "D11": { + "direction": "IN" + }, + "Q23": { + "direction": "OUT" + }, + "Q40": { + "direction": "OUT" + }, + "Q34": { + "direction": "OUT" + }, + "Q95": { + "direction": "OUT" + }, + "TESTWRITEDISB": { + "direction": "IN" + }, + "Q33": { + "direction": "OUT" + }, + "EMPTY": { + "direction": "OUT" + }, + "Q26": { + "direction": "OUT" + }, + "Q84": { + "direction": "OUT" + }, + "Q16": { + "direction": "OUT" + }, + "SCANIN0": { + "direction": "IN" + }, + "D65": { + "direction": "IN" + }, + "D93": { + "direction": "IN" + }, + "Q30": { + "direction": "OUT" + }, + "D42": { + "direction": "IN" + }, + "Q71": { + "direction": "OUT" + }, + "Q50": { + "direction": "OUT" + }, + "RDCLK": { + "direction": "IN" + }, + "D92": { + "direction": "IN" + }, + "Q20": { + "direction": "OUT" + }, + "D72": { + "direction": "IN" + }, + "Q10": { + "direction": "OUT" + }, + "D91": { + "direction": "IN" + }, + "SCANIN1": { + "direction": "IN" + }, + "Q97": { + "direction": "OUT" + }, + "D80": { + "direction": "IN" + }, + "Q05": { + "direction": "OUT" + }, + "Q94": { + "direction": "OUT" + }, + "RDEN": { + "direction": "IN" + }, + "D81": { + "direction": "IN" + }, + "D50": { + "direction": "IN" + }, + "D55": { + "direction": "IN" + }, + "Q92": { + "direction": "OUT" + }, + "Q35": { + "direction": "OUT" + }, + "Q54": { + "direction": "OUT" + }, + "D33": { + "direction": "IN" + }, + "D64": { + "direction": "IN" + }, + "Q63": { + "direction": "OUT" + }, + "D12": { + "direction": "IN" + }, + "Q31": { + "direction": "OUT" + }, + "Q14": { + "direction": "OUT" + }, + "Q56": { + "direction": "OUT" + }, + "Q75": { + "direction": "OUT" + }, + "Q36": { + "direction": "OUT" + }, + "Q86": { + "direction": "OUT" + }, + "SCANIN2": { + "direction": "IN" + }, + "SCANOUT0": { + "direction": "OUT" + }, + "Q45": { + "direction": "OUT" + }, + "Q07": { + "direction": "OUT" + }, + "D21": { + "direction": "IN" + }, + "D32": { + "direction": "IN" + }, + "Q00": { + "direction": "OUT" + }, + "Q85": { + "direction": "OUT" + }, + "D71": { + "direction": "IN" + }, + "SCANIN3": { + "direction": "IN" + }, + "D10": { + "direction": "IN" + }, + "Q67": { + "direction": "OUT" + }, + "D01": { + "direction": "IN" + }, + "D40": { + "direction": "IN" + }, + "D22": { + "direction": "IN" + }, + "D00": { + "direction": "IN" + }, + "Q13": { + "direction": "OUT" + }, + "Q96": { + "direction": "OUT" + }, + "D52": { + "direction": "IN" + }, + "Q43": { + "direction": "OUT" + }, + "Q27": { + "direction": "OUT" + }, + "Q01": { + "direction": "OUT" + }, + "D82": { + "direction": "IN" + }, + "D83": { + "direction": "IN" + }, + "Q87": { + "direction": "OUT" + }, + "D03": { + "direction": "IN" + }, + "Q91": { + "direction": "OUT" + }, + "ALMOSTFULL": { + "direction": "OUT" + }, + "D62": { + "direction": "IN" + }, + "D13": { + "direction": "IN" + }, + "Q55": { + "direction": "OUT" + }, + "RESET": { + "direction": "IN" + }, + "Q51": { + "direction": "OUT" + }, + "Q25": { + "direction": "OUT" + }, + "Q52": { + "direction": "OUT" + }, + "D02": { + "direction": "IN" + }, + "Q62": { + "direction": "OUT" + }, + "D63": { + "direction": "IN" + }, + "Q61": { + "direction": "OUT" + }, + "Q70": { + "direction": "OUT" + }, + "Q02": { + "direction": "OUT" + }, + "Q74": { + "direction": "OUT" + }, + "Q66": { + "direction": "OUT" + }, + "D70": { + "direction": "IN" + }, + "Q83": { + "direction": "OUT" + }, + "D61": { + "direction": "IN" + }, + "D43": { + "direction": "IN" + }, + "Q73": { + "direction": "OUT" + }, + "SCANOUT2": { + "direction": "OUT" + }, + "D51": { + "direction": "IN" + }, + "Q42": { + "direction": "OUT" + }, + "Q17": { + "direction": "OUT" + }, + "Q11": { + "direction": "OUT" + }, + "TESTREADDISB": { + "direction": "IN" + }, + "Q72": { + "direction": "OUT" + }, + "D20": { + "direction": "IN" + }, + "D90": { + "direction": "IN" + }, + "Q81": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_IOB18.json b/kintex7/site_type_IOB18.json new file mode 100644 index 0000000..8aeed35 --- /dev/null +++ b/kintex7/site_type_IOB18.json @@ -0,0 +1,94 @@ +{ + "type": "IOB18", + "site_pips": { + "DCITERMDISABLE_SEL:I": { + "from_pin": "I", + "to_pin": "OUT" + }, + "IBUFDISABLE_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + }, + "IUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "TUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "DIFFI_INUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IBUFDISABLE_SEL:I": { + "from_pin": "I", + "to_pin": "OUT" + }, + "PADOUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "DCITERMDISABLE_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + } + }, + "site_pins": { + "KEEPER_INT_EN": { + "direction": "IN" + }, + "I": { + "direction": "OUT" + }, + "T": { + "direction": "IN" + }, + "DIFFI_IN": { + "direction": "IN" + }, + "T_IN": { + "direction": "IN" + }, + "PD_INT_EN": { + "direction": "IN" + }, + "O_OUT": { + "direction": "OUT" + }, + "DCITERMDISABLE": { + "direction": "IN" + }, + "DIFFO_IN": { + "direction": "IN" + }, + "DIFFO_OUT": { + "direction": "OUT" + }, + "PADOUT": { + "direction": "OUT" + }, + "O_IN": { + "direction": "IN" + }, + "T_OUT": { + "direction": "OUT" + }, + "DIFF_TERM_INT_EN": { + "direction": "IN" + }, + "IBUFDISABLE": { + "direction": "IN" + }, + "PU_INT_EN": { + "direction": "IN" + }, + "O": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_IOB18M.json b/kintex7/site_type_IOB18M.json new file mode 100644 index 0000000..d4b3a96 --- /dev/null +++ b/kintex7/site_type_IOB18M.json @@ -0,0 +1,106 @@ +{ + "type": "IOB18M", + "site_pips": { + "IBUFDISABLE_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + }, + "DIFFO_OUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "T_OUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "DIFFI_INUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "DCITERMDISABLE_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + }, + "DCITERMDISABLE_SEL:I": { + "from_pin": "I", + "to_pin": "OUT" + }, + "O_OUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "TUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "PADOUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IBUFDISABLE_SEL:I": { + "from_pin": "I", + "to_pin": "OUT" + } + }, + "site_pins": { + "KEEPER_INT_EN": { + "direction": "IN" + }, + "I": { + "direction": "OUT" + }, + "T": { + "direction": "IN" + }, + "DIFFI_IN": { + "direction": "IN" + }, + "T_IN": { + "direction": "IN" + }, + "PD_INT_EN": { + "direction": "IN" + }, + "O_OUT": { + "direction": "OUT" + }, + "DCITERMDISABLE": { + "direction": "IN" + }, + "DIFFO_IN": { + "direction": "IN" + }, + "DIFFO_OUT": { + "direction": "OUT" + }, + "PADOUT": { + "direction": "OUT" + }, + "O_IN": { + "direction": "IN" + }, + "T_OUT": { + "direction": "OUT" + }, + "DIFF_TERM_INT_EN": { + "direction": "IN" + }, + "IBUFDISABLE": { + "direction": "IN" + }, + "PU_INT_EN": { + "direction": "IN" + }, + "O": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_IOB18S.json b/kintex7/site_type_IOB18S.json new file mode 100644 index 0000000..60ecf5c --- /dev/null +++ b/kintex7/site_type_IOB18S.json @@ -0,0 +1,114 @@ +{ + "type": "IOB18S", + "site_pips": { + "OUTMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "TINMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IBUFDISABLE_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + }, + "DIFFI_INUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IBUFDISABLE_SEL:I": { + "from_pin": "I", + "to_pin": "OUT" + }, + "OINMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OINMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "DIFFO_INUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OUTMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "DCITERMDISABLE_SEL:I": { + "from_pin": "I", + "to_pin": "OUT" + }, + "IUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "TINMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "PADOUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "DCITERMDISABLE_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + } + }, + "site_pins": { + "KEEPER_INT_EN": { + "direction": "IN" + }, + "I": { + "direction": "OUT" + }, + "T": { + "direction": "IN" + }, + "DIFFI_IN": { + "direction": "IN" + }, + "T_IN": { + "direction": "IN" + }, + "PD_INT_EN": { + "direction": "IN" + }, + "O_OUT": { + "direction": "OUT" + }, + "DCITERMDISABLE": { + "direction": "IN" + }, + "DIFFO_IN": { + "direction": "IN" + }, + "DIFFO_OUT": { + "direction": "OUT" + }, + "PADOUT": { + "direction": "OUT" + }, + "O_IN": { + "direction": "IN" + }, + "T_OUT": { + "direction": "OUT" + }, + "DIFF_TERM_INT_EN": { + "direction": "IN" + }, + "IBUFDISABLE": { + "direction": "IN" + }, + "PU_INT_EN": { + "direction": "IN" + }, + "O": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_IOB33.json b/kintex7/site_type_IOB33.json new file mode 100644 index 0000000..b02832d --- /dev/null +++ b/kintex7/site_type_IOB33.json @@ -0,0 +1,94 @@ +{ + "type": "IOB33", + "site_pips": { + "INTERMDISABLE_SEL:I": { + "from_pin": "I", + "to_pin": "OUT" + }, + "IBUFDISABLE_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + }, + "IUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "TUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "INTERMDISABLE_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + }, + "DIFFI_INUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "PADOUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IBUFDISABLE_SEL:I": { + "from_pin": "I", + "to_pin": "OUT" + } + }, + "site_pins": { + "KEEPER_INT_EN": { + "direction": "IN" + }, + "I": { + "direction": "OUT" + }, + "INTERMDISABLE": { + "direction": "IN" + }, + "T": { + "direction": "IN" + }, + "DIFFI_IN": { + "direction": "IN" + }, + "T_IN": { + "direction": "IN" + }, + "PD_INT_EN": { + "direction": "IN" + }, + "O_OUT": { + "direction": "OUT" + }, + "DIFFO_IN": { + "direction": "IN" + }, + "DIFFO_OUT": { + "direction": "OUT" + }, + "PADOUT": { + "direction": "OUT" + }, + "O_IN": { + "direction": "IN" + }, + "T_OUT": { + "direction": "OUT" + }, + "DIFF_TERM_INT_EN": { + "direction": "IN" + }, + "IBUFDISABLE": { + "direction": "IN" + }, + "PU_INT_EN": { + "direction": "IN" + }, + "O": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_IOB33M.json b/kintex7/site_type_IOB33M.json new file mode 100644 index 0000000..c945587 --- /dev/null +++ b/kintex7/site_type_IOB33M.json @@ -0,0 +1,106 @@ +{ + "type": "IOB33M", + "site_pips": { + "IBUFDISABLE_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + }, + "DIFFO_OUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "T_OUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "INTERMDISABLE_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + }, + "DIFFI_INUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "INTERMDISABLE_SEL:I": { + "from_pin": "I", + "to_pin": "OUT" + }, + "O_OUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "TUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "PADOUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IBUFDISABLE_SEL:I": { + "from_pin": "I", + "to_pin": "OUT" + } + }, + "site_pins": { + "KEEPER_INT_EN": { + "direction": "IN" + }, + "I": { + "direction": "OUT" + }, + "INTERMDISABLE": { + "direction": "IN" + }, + "T": { + "direction": "IN" + }, + "DIFFI_IN": { + "direction": "IN" + }, + "T_IN": { + "direction": "IN" + }, + "PD_INT_EN": { + "direction": "IN" + }, + "O_OUT": { + "direction": "OUT" + }, + "DIFFO_IN": { + "direction": "IN" + }, + "DIFFO_OUT": { + "direction": "OUT" + }, + "PADOUT": { + "direction": "OUT" + }, + "O_IN": { + "direction": "IN" + }, + "T_OUT": { + "direction": "OUT" + }, + "DIFF_TERM_INT_EN": { + "direction": "IN" + }, + "IBUFDISABLE": { + "direction": "IN" + }, + "PU_INT_EN": { + "direction": "IN" + }, + "O": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_IOB33S.json b/kintex7/site_type_IOB33S.json new file mode 100644 index 0000000..d69dfce --- /dev/null +++ b/kintex7/site_type_IOB33S.json @@ -0,0 +1,114 @@ +{ + "type": "IOB33S", + "site_pips": { + "OUTMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "TINMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IBUFDISABLE_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + }, + "INTERMDISABLE_SEL:GND": { + "from_pin": "GND", + "to_pin": "OUT" + }, + "DIFFI_INUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OINMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "DIFFO_INUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OUTMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "INTERMDISABLE_SEL:I": { + "from_pin": "I", + "to_pin": "OUT" + }, + "OINMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "IUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "TINMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "PADOUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "IBUFDISABLE_SEL:I": { + "from_pin": "I", + "to_pin": "OUT" + } + }, + "site_pins": { + "KEEPER_INT_EN": { + "direction": "IN" + }, + "I": { + "direction": "OUT" + }, + "INTERMDISABLE": { + "direction": "IN" + }, + "T": { + "direction": "IN" + }, + "DIFFI_IN": { + "direction": "IN" + }, + "T_IN": { + "direction": "IN" + }, + "PD_INT_EN": { + "direction": "IN" + }, + "O_OUT": { + "direction": "OUT" + }, + "DIFFO_IN": { + "direction": "IN" + }, + "DIFFO_OUT": { + "direction": "OUT" + }, + "PADOUT": { + "direction": "OUT" + }, + "O_IN": { + "direction": "IN" + }, + "T_OUT": { + "direction": "OUT" + }, + "DIFF_TERM_INT_EN": { + "direction": "IN" + }, + "IBUFDISABLE": { + "direction": "IN" + }, + "PU_INT_EN": { + "direction": "IN" + }, + "O": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_IPAD.json b/kintex7/site_type_IPAD.json new file mode 100644 index 0000000..c3d5c12 --- /dev/null +++ b/kintex7/site_type_IPAD.json @@ -0,0 +1,9 @@ +{ + "type": "IPAD", + "site_pips": {}, + "site_pins": { + "O": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_MMCME2_ADV.json b/kintex7/site_type_MMCME2_ADV.json new file mode 100644 index 0000000..13bea34 --- /dev/null +++ b/kintex7/site_type_MMCME2_ADV.json @@ -0,0 +1,545 @@ +{ + "type": "MMCME2_ADV", + "site_pips": { + "RSTINV:RST": { + "from_pin": "RST", + "to_pin": "OUT" + }, + "CLKINSELINV:CLKINSEL_B": { + "from_pin": "CLKINSEL_B", + "to_pin": "OUT" + }, + "PSENINV:PSEN_B": { + "from_pin": "PSEN_B", + "to_pin": "OUT" + }, + "CLKINSELINV:CLKINSEL": { + "from_pin": "CLKINSEL", + "to_pin": "OUT" + }, + "PWRDWNINV:PWRDWN_B": { + "from_pin": "PWRDWN_B", + "to_pin": "OUT" + }, + "RSTINV:RST_B": { + "from_pin": "RST_B", + "to_pin": "OUT" + }, + "PSINCDECINV:PSINCDEC": { + "from_pin": "PSINCDEC", + "to_pin": "OUT" + }, + "PWRDWNINV:PWRDWN": { + "from_pin": "PWRDWN", + "to_pin": "OUT" + }, + "PSENINV:PSEN": { + "from_pin": "PSEN", + "to_pin": "OUT" + }, + "PSINCDECINV:PSINCDEC_B": { + "from_pin": "PSINCDEC_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "CLKOUT2B": { + "direction": "OUT" + }, + "TESTOUT1": { + "direction": "OUT" + }, + "TESTOUT51": { + "direction": "OUT" + }, + "TESTOUT56": { + "direction": "OUT" + }, + "TESTIN11": { + "direction": "IN" + }, + "CLKOUT6": { + "direction": "OUT" + }, + "TESTOUT31": { + "direction": "OUT" + }, + "TESTOUT26": { + "direction": "OUT" + }, + "DCLK": { + "direction": "IN" + }, + "TESTOUT7": { + "direction": "OUT" + }, + "TESTIN31": { + "direction": "IN" + }, + "TESTIN14": { + "direction": "IN" + }, + "TESTOUT53": { + "direction": "OUT" + }, + "RST": { + "direction": "IN" + }, + "TESTIN18": { + "direction": "IN" + }, + "TESTIN6": { + "direction": "IN" + }, + "TESTOUT42": { + "direction": "OUT" + }, + "TESTOUT28": { + "direction": "OUT" + }, + "TESTIN9": { + "direction": "IN" + }, + "TESTOUT43": { + "direction": "OUT" + }, + "TESTOUT59": { + "direction": "OUT" + }, + "CLKOUT5": { + "direction": "OUT" + }, + "CLKOUT2": { + "direction": "OUT" + }, + "TESTIN29": { + "direction": "IN" + }, + "CLKFBOUT": { + "direction": "OUT" + }, + "TESTIN30": { + "direction": "IN" + }, + "PSCLK": { + "direction": "IN" + }, + "CLKFBSTOPPED": { + "direction": "OUT" + }, + "TESTIN23": { + "direction": "IN" + }, + "TESTOUT11": { + "direction": "OUT" + }, + "TESTIN21": { + "direction": "IN" + }, + "TESTOUT41": { + "direction": "OUT" + }, + "DADDR5": { + "direction": "IN" + }, + "TESTIN22": { + "direction": "IN" + }, + "TESTOUT32": { + "direction": "OUT" + }, + "TESTIN19": { + "direction": "IN" + }, + "TESTOUT5": { + "direction": "OUT" + }, + "TESTIN1": { + "direction": "IN" + }, + "CLKFBIN": { + "direction": "IN" + }, + "TESTOUT29": { + "direction": "OUT" + }, + "TESTOUT15": { + "direction": "OUT" + }, + "DO12": { + "direction": "OUT" + }, + "TESTOUT44": { + "direction": "OUT" + }, + "TESTOUT35": { + "direction": "OUT" + }, + "DI2": { + "direction": "IN" + }, + "CLKINSEL": { + "direction": "IN" + }, + "DI13": { + "direction": "IN" + }, + "TESTOUT27": { + "direction": "OUT" + }, + "TESTOUT4": { + "direction": "OUT" + }, + "DRDY": { + "direction": "OUT" + }, + "TESTIN20": { + "direction": "IN" + }, + "TESTOUT22": { + "direction": "OUT" + }, + "DO5": { + "direction": "OUT" + }, + "TESTOUT49": { + "direction": "OUT" + }, + "TESTIN17": { + "direction": "IN" + }, + "TESTOUT19": { + "direction": "OUT" + }, + "DO8": { + "direction": "OUT" + }, + "DADDR3": { + "direction": "IN" + }, + "DO3": { + "direction": "OUT" + }, + "TESTIN8": { + "direction": "IN" + }, + "DI8": { + "direction": "IN" + }, + "TESTOUT61": { + "direction": "OUT" + }, + "TESTOUT12": { + "direction": "OUT" + }, + "TESTOUT57": { + "direction": "OUT" + }, + "TESTOUT18": { + "direction": "OUT" + }, + "TESTOUT9": { + "direction": "OUT" + }, + "DO4": { + "direction": "OUT" + }, + "TESTOUT3": { + "direction": "OUT" + }, + "TESTOUT6": { + "direction": "OUT" + }, + "TESTOUT17": { + "direction": "OUT" + }, + "TESTOUT40": { + "direction": "OUT" + }, + "TESTOUT2": { + "direction": "OUT" + }, + "DI0": { + "direction": "IN" + }, + "DI11": { + "direction": "IN" + }, + "CLKFBOUTB": { + "direction": "OUT" + }, + "DWE": { + "direction": "IN" + }, + "TESTOUT16": { + "direction": "OUT" + }, + "TESTIN13": { + "direction": "IN" + }, + "DI6": { + "direction": "IN" + }, + "TMUXOUT": { + "direction": "OUT" + }, + "DADDR2": { + "direction": "IN" + }, + "TESTOUT13": { + "direction": "OUT" + }, + "DADDR1": { + "direction": "IN" + }, + "DO1": { + "direction": "OUT" + }, + "TESTOUT23": { + "direction": "OUT" + }, + "TESTIN2": { + "direction": "IN" + }, + "TESTOUT8": { + "direction": "OUT" + }, + "CLKOUT0": { + "direction": "OUT" + }, + "DO11": { + "direction": "OUT" + }, + "TESTOUT47": { + "direction": "OUT" + }, + "TESTOUT21": { + "direction": "OUT" + }, + "DO7": { + "direction": "OUT" + }, + "DI10": { + "direction": "IN" + }, + "TESTOUT38": { + "direction": "OUT" + }, + "TESTIN28": { + "direction": "IN" + }, + "TESTOUT63": { + "direction": "OUT" + }, + "TESTOUT33": { + "direction": "OUT" + }, + "TESTOUT52": { + "direction": "OUT" + }, + "TESTOUT20": { + "direction": "OUT" + }, + "CLKOUT3": { + "direction": "OUT" + }, + "DO0": { + "direction": "OUT" + }, + "TESTOUT34": { + "direction": "OUT" + }, + "DO13": { + "direction": "OUT" + }, + "TESTOUT24": { + "direction": "OUT" + }, + "TESTIN27": { + "direction": "IN" + }, + "TESTOUT58": { + "direction": "OUT" + }, + "TESTIN3": { + "direction": "IN" + }, + "TESTOUT0": { + "direction": "OUT" + }, + "DO15": { + "direction": "OUT" + }, + "DI1": { + "direction": "IN" + }, + "CLKOUT0B": { + "direction": "OUT" + }, + "DADDR4": { + "direction": "IN" + }, + "TESTOUT55": { + "direction": "OUT" + }, + "TESTOUT10": { + "direction": "OUT" + }, + "TESTIN15": { + "direction": "IN" + }, + "TESTIN25": { + "direction": "IN" + }, + "TESTOUT37": { + "direction": "OUT" + }, + "DEN": { + "direction": "IN" + }, + "DI14": { + "direction": "IN" + }, + "TESTOUT62": { + "direction": "OUT" + }, + "DI9": { + "direction": "IN" + }, + "DI7": { + "direction": "IN" + }, + "TESTIN10": { + "direction": "IN" + }, + "TESTOUT36": { + "direction": "OUT" + }, + "DI4": { + "direction": "IN" + }, + "DI5": { + "direction": "IN" + }, + "DI12": { + "direction": "IN" + }, + "TESTIN0": { + "direction": "IN" + }, + "TESTOUT46": { + "direction": "OUT" + }, + "TESTIN7": { + "direction": "IN" + }, + "CLKOUT3B": { + "direction": "OUT" + }, + "DO10": { + "direction": "OUT" + }, + "TESTOUT14": { + "direction": "OUT" + }, + "LOCKED": { + "direction": "OUT" + }, + "DO14": { + "direction": "OUT" + }, + "CLKOUT1": { + "direction": "OUT" + }, + "TESTOUT54": { + "direction": "OUT" + }, + "PSEN": { + "direction": "IN" + }, + "TESTIN4": { + "direction": "IN" + }, + "CLKIN2": { + "direction": "IN" + }, + "CLKIN1": { + "direction": "IN" + }, + "TESTOUT50": { + "direction": "OUT" + }, + "CLKOUT4": { + "direction": "OUT" + }, + "DO9": { + "direction": "OUT" + }, + "DO6": { + "direction": "OUT" + }, + "DADDR6": { + "direction": "IN" + }, + "PWRDWN": { + "direction": "IN" + }, + "DI15": { + "direction": "IN" + }, + "DO2": { + "direction": "OUT" + }, + "TESTOUT39": { + "direction": "OUT" + }, + "TESTOUT48": { + "direction": "OUT" + }, + "DADDR0": { + "direction": "IN" + }, + "TESTIN26": { + "direction": "IN" + }, + "CLKINSTOPPED": { + "direction": "OUT" + }, + "PSDONE": { + "direction": "OUT" + }, + "DI3": { + "direction": "IN" + }, + "TESTOUT30": { + "direction": "OUT" + }, + "TESTOUT25": { + "direction": "OUT" + }, + "PSINCDEC": { + "direction": "IN" + }, + "TESTIN12": { + "direction": "IN" + }, + "TESTIN24": { + "direction": "IN" + }, + "TESTOUT60": { + "direction": "OUT" + }, + "TESTIN16": { + "direction": "IN" + }, + "CLKOUT1B": { + "direction": "OUT" + }, + "TESTIN5": { + "direction": "IN" + }, + "TESTOUT45": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_ODELAYE2.json b/kintex7/site_type_ODELAYE2.json new file mode 100644 index 0000000..a573454 --- /dev/null +++ b/kintex7/site_type_ODELAYE2.json @@ -0,0 +1,92 @@ +{ + "type": "ODELAYE2", + "site_pips": { + "ODATAININV:ODATAIN_B": { + "from_pin": "ODATAIN_B", + "to_pin": "OUT" + }, + "ODATAININV:ODATAIN": { + "from_pin": "ODATAIN", + "to_pin": "OUT" + }, + "CINV:C": { + "from_pin": "C", + "to_pin": "OUT" + }, + "CINV:C_B": { + "from_pin": "C_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "CLKIN": { + "direction": "IN" + }, + "CNTVALUEOUT1": { + "direction": "OUT" + }, + "CNTVALUEIN1": { + "direction": "IN" + }, + "ODATAIN": { + "direction": "IN" + }, + "OFDLY0": { + "direction": "IN" + }, + "CE": { + "direction": "IN" + }, + "DATAOUT": { + "direction": "OUT" + }, + "CNTVALUEIN0": { + "direction": "IN" + }, + "CNTVALUEIN4": { + "direction": "IN" + }, + "CNTVALUEOUT2": { + "direction": "OUT" + }, + "C": { + "direction": "IN" + }, + "CNTVALUEOUT0": { + "direction": "OUT" + }, + "CNTVALUEIN2": { + "direction": "IN" + }, + "OFDLY2": { + "direction": "IN" + }, + "LDPIPEEN": { + "direction": "IN" + }, + "CINVCTRL": { + "direction": "IN" + }, + "CNTVALUEOUT3": { + "direction": "OUT" + }, + "INC": { + "direction": "IN" + }, + "CNTVALUEOUT4": { + "direction": "OUT" + }, + "CNTVALUEIN3": { + "direction": "IN" + }, + "OFDLY1": { + "direction": "IN" + }, + "REGRST": { + "direction": "IN" + }, + "LD": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_OLOGICE2.json b/kintex7/site_type_OLOGICE2.json new file mode 100644 index 0000000..69ab59f --- /dev/null +++ b/kintex7/site_type_OLOGICE2.json @@ -0,0 +1,210 @@ +{ + "type": "OLOGICE2", + "site_pips": { + "TMUX:TFF": { + "from_pin": "TFF", + "to_pin": "OUT" + }, + "CLKINV:CLK": { + "from_pin": "CLK", + "to_pin": "OUT" + }, + "D1INV:D1_B": { + "from_pin": "D1_B", + "to_pin": "OUT" + }, + "O1USED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "TCEUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "D2INV:D2": { + "from_pin": "D2", + "to_pin": "OUT" + }, + "T2INV:T2": { + "from_pin": "T2", + "to_pin": "OUT" + }, + "OREVUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OMUX:OUTFF": { + "from_pin": "OUTFF", + "to_pin": "OUT" + }, + "TQUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "T1INV:T1_B": { + "from_pin": "T1_B", + "to_pin": "OUT" + }, + "OSRUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "D2INV:D2_B": { + "from_pin": "D2_B", + "to_pin": "OUT" + }, + "OCEUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "T1INV:T1": { + "from_pin": "T1", + "to_pin": "OUT" + }, + "OFBUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OMUX:D1": { + "from_pin": "D1", + "to_pin": "OUT" + }, + "TFBUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "TSRUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "TMUX:T1": { + "from_pin": "T1", + "to_pin": "OUT" + }, + "T1USED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "D1INV:D1": { + "from_pin": "D1", + "to_pin": "OUT" + }, + "T2INV:T2_B": { + "from_pin": "T2_B", + "to_pin": "OUT" + }, + "TREVUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OQUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "CLKINV:CLK_B": { + "from_pin": "CLK_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "T1": { + "direction": "IN" + }, + "T2": { + "direction": "IN" + }, + "TQ": { + "direction": "OUT" + }, + "OFB": { + "direction": "OUT" + }, + "TBYTEOUT": { + "direction": "OUT" + }, + "REV": { + "direction": "IN" + }, + "CLKDIVFB": { + "direction": "IN" + }, + "TBYTEIN": { + "direction": "IN" + }, + "CLKDIVF": { + "direction": "IN" + }, + "SHIFTOUT1": { + "direction": "OUT" + }, + "CLKDIV": { + "direction": "IN" + }, + "CLKB": { + "direction": "IN" + }, + "D7": { + "direction": "IN" + }, + "TFB": { + "direction": "OUT" + }, + "SHIFTIN1": { + "direction": "IN" + }, + "CLK": { + "direction": "IN" + }, + "SHIFTOUT2": { + "direction": "OUT" + }, + "SHIFTIN2": { + "direction": "IN" + }, + "D3": { + "direction": "IN" + }, + "T4": { + "direction": "IN" + }, + "D6": { + "direction": "IN" + }, + "D4": { + "direction": "IN" + }, + "OQ": { + "direction": "OUT" + }, + "OCE": { + "direction": "IN" + }, + "T3": { + "direction": "IN" + }, + "D1": { + "direction": "IN" + }, + "TCE": { + "direction": "IN" + }, + "IOCLKGLITCH": { + "direction": "OUT" + }, + "SR": { + "direction": "IN" + }, + "CLKDIVB": { + "direction": "IN" + }, + "D2": { + "direction": "IN" + }, + "D5": { + "direction": "IN" + }, + "D8": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_OLOGICE3.json b/kintex7/site_type_OLOGICE3.json new file mode 100644 index 0000000..550c837 --- /dev/null +++ b/kintex7/site_type_OLOGICE3.json @@ -0,0 +1,210 @@ +{ + "type": "OLOGICE3", + "site_pips": { + "TMUX:TFF": { + "from_pin": "TFF", + "to_pin": "OUT" + }, + "CLKINV:CLK": { + "from_pin": "CLK", + "to_pin": "OUT" + }, + "D1INV:D1_B": { + "from_pin": "D1_B", + "to_pin": "OUT" + }, + "O1USED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "TCEUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "D2INV:D2": { + "from_pin": "D2", + "to_pin": "OUT" + }, + "T2INV:T2": { + "from_pin": "T2", + "to_pin": "OUT" + }, + "OREVUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OMUX:OUTFF": { + "from_pin": "OUTFF", + "to_pin": "OUT" + }, + "TQUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "T1INV:T1_B": { + "from_pin": "T1_B", + "to_pin": "OUT" + }, + "OSRUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "D2INV:D2_B": { + "from_pin": "D2_B", + "to_pin": "OUT" + }, + "OCEUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "T1INV:T1": { + "from_pin": "T1", + "to_pin": "OUT" + }, + "OFBUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OMUX:D1": { + "from_pin": "D1", + "to_pin": "OUT" + }, + "TFBUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "TSRUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "TMUX:T1": { + "from_pin": "T1", + "to_pin": "OUT" + }, + "T1USED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "D1INV:D1": { + "from_pin": "D1", + "to_pin": "OUT" + }, + "T2INV:T2_B": { + "from_pin": "T2_B", + "to_pin": "OUT" + }, + "TREVUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "OQUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "CLKINV:CLK_B": { + "from_pin": "CLK_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "T1": { + "direction": "IN" + }, + "T2": { + "direction": "IN" + }, + "TQ": { + "direction": "OUT" + }, + "OFB": { + "direction": "OUT" + }, + "TBYTEOUT": { + "direction": "OUT" + }, + "REV": { + "direction": "IN" + }, + "CLKDIVFB": { + "direction": "IN" + }, + "TBYTEIN": { + "direction": "IN" + }, + "CLKDIVF": { + "direction": "IN" + }, + "SHIFTOUT1": { + "direction": "OUT" + }, + "CLKDIV": { + "direction": "IN" + }, + "CLKB": { + "direction": "IN" + }, + "D7": { + "direction": "IN" + }, + "TFB": { + "direction": "OUT" + }, + "SHIFTIN1": { + "direction": "IN" + }, + "CLK": { + "direction": "IN" + }, + "SHIFTOUT2": { + "direction": "OUT" + }, + "SHIFTIN2": { + "direction": "IN" + }, + "D3": { + "direction": "IN" + }, + "T4": { + "direction": "IN" + }, + "D6": { + "direction": "IN" + }, + "D4": { + "direction": "IN" + }, + "OQ": { + "direction": "OUT" + }, + "OCE": { + "direction": "IN" + }, + "T3": { + "direction": "IN" + }, + "D1": { + "direction": "IN" + }, + "TCE": { + "direction": "IN" + }, + "IOCLKGLITCH": { + "direction": "OUT" + }, + "SR": { + "direction": "IN" + }, + "CLKDIVB": { + "direction": "IN" + }, + "D2": { + "direction": "IN" + }, + "D5": { + "direction": "IN" + }, + "D8": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_OPAD.json b/kintex7/site_type_OPAD.json new file mode 100644 index 0000000..c671fb7 --- /dev/null +++ b/kintex7/site_type_OPAD.json @@ -0,0 +1,9 @@ +{ + "type": "OPAD", + "site_pips": {}, + "site_pins": { + "I": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_OUT_FIFO.json b/kintex7/site_type_OUT_FIFO.json new file mode 100644 index 0000000..72efbe2 --- /dev/null +++ b/kintex7/site_type_OUT_FIFO.json @@ -0,0 +1,453 @@ +{ + "type": "OUT_FIFO", + "site_pips": {}, + "site_pins": { + "Q53": { + "direction": "OUT" + }, + "ALMOSTEMPTY": { + "direction": "OUT" + }, + "D53": { + "direction": "IN" + }, + "D31": { + "direction": "IN" + }, + "D77": { + "direction": "IN" + }, + "D16": { + "direction": "IN" + }, + "D73": { + "direction": "IN" + }, + "D56": { + "direction": "IN" + }, + "Q64": { + "direction": "OUT" + }, + "Q57": { + "direction": "OUT" + }, + "Q12": { + "direction": "OUT" + }, + "D66": { + "direction": "IN" + }, + "D51": { + "direction": "IN" + }, + "Q41": { + "direction": "OUT" + }, + "FULL": { + "direction": "OUT" + }, + "D71": { + "direction": "IN" + }, + "SCANOUT3": { + "direction": "OUT" + }, + "Q22": { + "direction": "OUT" + }, + "D26": { + "direction": "IN" + }, + "D67": { + "direction": "IN" + }, + "D25": { + "direction": "IN" + }, + "D13": { + "direction": "IN" + }, + "WREN": { + "direction": "IN" + }, + "D87": { + "direction": "IN" + }, + "D85": { + "direction": "IN" + }, + "D86": { + "direction": "IN" + }, + "Q65": { + "direction": "OUT" + }, + "D95": { + "direction": "IN" + }, + "Q03": { + "direction": "OUT" + }, + "D41": { + "direction": "IN" + }, + "Q62": { + "direction": "OUT" + }, + "SCANOUT1": { + "direction": "OUT" + }, + "D00": { + "direction": "IN" + }, + "Q60": { + "direction": "OUT" + }, + "D54": { + "direction": "IN" + }, + "Q32": { + "direction": "OUT" + }, + "D45": { + "direction": "IN" + }, + "Q90": { + "direction": "OUT" + }, + "D07": { + "direction": "IN" + }, + "SCANENB": { + "direction": "IN" + }, + "SCANOUT0": { + "direction": "OUT" + }, + "D84": { + "direction": "IN" + }, + "D50": { + "direction": "IN" + }, + "D63": { + "direction": "IN" + }, + "D46": { + "direction": "IN" + }, + "D62": { + "direction": "IN" + }, + "D30": { + "direction": "IN" + }, + "D11": { + "direction": "IN" + }, + "Q23": { + "direction": "OUT" + }, + "D23": { + "direction": "IN" + }, + "TESTWRITEDISB": { + "direction": "IN" + }, + "Q33": { + "direction": "OUT" + }, + "D22": { + "direction": "IN" + }, + "D47": { + "direction": "IN" + }, + "SCANIN0": { + "direction": "IN" + }, + "Q20": { + "direction": "OUT" + }, + "D93": { + "direction": "IN" + }, + "Q30": { + "direction": "OUT" + }, + "D42": { + "direction": "IN" + }, + "Q71": { + "direction": "OUT" + }, + "Q13": { + "direction": "OUT" + }, + "D44": { + "direction": "IN" + }, + "D92": { + "direction": "IN" + }, + "Q40": { + "direction": "OUT" + }, + "D14": { + "direction": "IN" + }, + "D91": { + "direction": "IN" + }, + "SCANIN1": { + "direction": "IN" + }, + "D80": { + "direction": "IN" + }, + "Q43": { + "direction": "OUT" + }, + "D24": { + "direction": "IN" + }, + "D72": { + "direction": "IN" + }, + "D81": { + "direction": "IN" + }, + "D06": { + "direction": "IN" + }, + "Q91": { + "direction": "OUT" + }, + "D55": { + "direction": "IN" + }, + "Q92": { + "direction": "OUT" + }, + "D36": { + "direction": "IN" + }, + "Q54": { + "direction": "OUT" + }, + "D33": { + "direction": "IN" + }, + "D64": { + "direction": "IN" + }, + "Q63": { + "direction": "OUT" + }, + "D12": { + "direction": "IN" + }, + "Q31": { + "direction": "OUT" + }, + "D76": { + "direction": "IN" + }, + "D94": { + "direction": "IN" + }, + "D43": { + "direction": "IN" + }, + "SCANIN2": { + "direction": "IN" + }, + "D35": { + "direction": "IN" + }, + "Q82": { + "direction": "OUT" + }, + "D05": { + "direction": "IN" + }, + "ALMOSTFULL": { + "direction": "OUT" + }, + "D74": { + "direction": "IN" + }, + "D21": { + "direction": "IN" + }, + "SCANOUT2": { + "direction": "OUT" + }, + "Q00": { + "direction": "OUT" + }, + "Q21": { + "direction": "OUT" + }, + "D03": { + "direction": "IN" + }, + "WRCLK": { + "direction": "IN" + }, + "SCANIN3": { + "direction": "IN" + }, + "D27": { + "direction": "IN" + }, + "D10": { + "direction": "IN" + }, + "Q67": { + "direction": "OUT" + }, + "D01": { + "direction": "IN" + }, + "D40": { + "direction": "IN" + }, + "EMPTY": { + "direction": "OUT" + }, + "D65": { + "direction": "IN" + }, + "Q50": { + "direction": "OUT" + }, + "Q10": { + "direction": "OUT" + }, + "D52": { + "direction": "IN" + }, + "D17": { + "direction": "IN" + }, + "D34": { + "direction": "IN" + }, + "Q01": { + "direction": "OUT" + }, + "D82": { + "direction": "IN" + }, + "D83": { + "direction": "IN" + }, + "D32": { + "direction": "IN" + }, + "D15": { + "direction": "IN" + }, + "D96": { + "direction": "IN" + }, + "Q66": { + "direction": "OUT" + }, + "TESTMODEB": { + "direction": "IN" + }, + "D37": { + "direction": "IN" + }, + "Q55": { + "direction": "OUT" + }, + "RESET": { + "direction": "IN" + }, + "D97": { + "direction": "IN" + }, + "Q52": { + "direction": "OUT" + }, + "D75": { + "direction": "IN" + }, + "D02": { + "direction": "IN" + }, + "D60": { + "direction": "IN" + }, + "Q72": { + "direction": "OUT" + }, + "Q61": { + "direction": "OUT" + }, + "Q70": { + "direction": "OUT" + }, + "Q02": { + "direction": "OUT" + }, + "Q80": { + "direction": "OUT" + }, + "RDCLK": { + "direction": "IN" + }, + "D70": { + "direction": "IN" + }, + "Q83": { + "direction": "OUT" + }, + "D61": { + "direction": "IN" + }, + "RDEN": { + "direction": "IN" + }, + "Q73": { + "direction": "OUT" + }, + "D04": { + "direction": "IN" + }, + "Q56": { + "direction": "OUT" + }, + "Q42": { + "direction": "OUT" + }, + "Q93": { + "direction": "OUT" + }, + "Q11": { + "direction": "OUT" + }, + "TESTREADDISB": { + "direction": "IN" + }, + "D57": { + "direction": "IN" + }, + "D20": { + "direction": "IN" + }, + "D90": { + "direction": "IN" + }, + "Q81": { + "direction": "OUT" + }, + "Q51": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_PCIE_2_1.json b/kintex7/site_type_PCIE_2_1.json new file mode 100644 index 0000000..0afa559 --- /dev/null +++ b/kintex7/site_type_PCIE_2_1.json @@ -0,0 +1,6753 @@ +{ + "type": "PCIE_2_1", + "site_pips": {}, + "site_pins": { + "MIMTXWDATA19": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG112": { + "direction": "IN" + }, + "CFGINTERRUPTDI3": { + "direction": "IN" + }, + "DBGVECC9": { + "direction": "OUT" + }, + "MIMTXRADDR1": { + "direction": "OUT" + }, + "PIPERX4DATA13": { + "direction": "IN" + }, + "PLDIRECTEDLINKCHANGE0": { + "direction": "IN" + }, + "PIPERX6POLARITY": { + "direction": "OUT" + }, + "CFGPCIECAPINTERRUPTMSGNUM4": { + "direction": "IN" + }, + "TL2ERRHDR21": { + "direction": "OUT" + }, + "PIPERX6VALID": { + "direction": "IN" + }, + "TRNRDLLPDATA33": { + "direction": "OUT" + }, + "TRNRD114": { + "direction": "OUT" + }, + "CMSTICKYRSTN": { + "direction": "IN" + }, + "TL2ERRHDR46": { + "direction": "OUT" + }, + "MIMRXRDATA25": { + "direction": "IN" + }, + "CFGMGMTDI31": { + "direction": "IN" + }, + "DBGVECB43": { + "direction": "OUT" + }, + "CFGDEVCONTROLMAXREADREQ0": { + "direction": "OUT" + }, + "DBGVECC3": { + "direction": "OUT" + }, + "TL2ERRHDR58": { + "direction": "OUT" + }, + "CFGLINKSTATUSLINKTRAINING": { + "direction": "OUT" + }, + "CFGREVID4": { + "direction": "IN" + }, + "CFGDSN48": { + "direction": "IN" + }, + "CFGSUBSYSID0": { + "direction": "IN" + }, + "TRNRSOF": { + "direction": "OUT" + }, + "CFGDSN63": { + "direction": "IN" + }, + "MIMTXWDATA52": { + "direction": "OUT" + }, + "LL2TFCINIT1SEQ": { + "direction": "OUT" + }, + "TRNRD85": { + "direction": "OUT" + }, + "DBGVECC1": { + "direction": "OUT" + }, + "MIMTXWADDR8": { + "direction": "OUT" + }, + "CFGERRECRCN": { + "direction": "IN" + }, + "PIPETX4DATA11": { + "direction": "OUT" + }, + "TRNTD120": { + "direction": "IN" + }, + "MIMTXRDATA27": { + "direction": "IN" + }, + "TRNTD88": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG124": { + "direction": "IN" + }, + "MIMTXWDATA35": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG42": { + "direction": "IN" + }, + "MIMRXRDATA54": { + "direction": "IN" + }, + "PLDBGMODE0": { + "direction": "IN" + }, + "EDTCHANNELSOUT8": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG49": { + "direction": "IN" + }, + "CFGDSN47": { + "direction": "IN" + }, + "CFGPMRCVREQACKN": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDERRCOR": { + "direction": "OUT" + }, + "MIMRXWDATA43": { + "direction": "OUT" + }, + "TRNTD109": { + "direction": "IN" + }, + "TL2ERRHDR6": { + "direction": "OUT" + }, + "MIMRXWDATA51": { + "direction": "OUT" + }, + "CFGMGMTDI20": { + "direction": "IN" + }, + "TRNTD42": { + "direction": "IN" + }, + "TRNRD52": { + "direction": "OUT" + }, + "CFGREVID2": { + "direction": "IN" + }, + "TRNRBARHIT5": { + "direction": "OUT" + }, + "PIPERX7ELECIDLE": { + "direction": "IN" + }, + "DBGVECA54": { + "direction": "OUT" + }, + "TRNREOF": { + "direction": "OUT" + }, + "MIMTXRDATA20": { + "direction": "IN" + }, + "TRNFCNPH2": { + "direction": "OUT" + }, + "DBGVECB15": { + "direction": "OUT" + }, + "CFGDSN25": { + "direction": "IN" + }, + "PIPERX6STATUS2": { + "direction": "IN" + }, + "PIPETX0DATA3": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG94": { + "direction": "IN" + }, + "PLDBGVEC7": { + "direction": "OUT" + }, + "DBGVECA63": { + "direction": "OUT" + }, + "XILUNCONNOUT20": { + "direction": "OUT" + }, + "PIPETX2DATA0": { + "direction": "OUT" + }, + "CFGMGMTDI29": { + "direction": "IN" + }, + "MIMTXWDATA62": { + "direction": "OUT" + }, + "PIPERX2DATA12": { + "direction": "IN" + }, + "XILUNCONNOUT1": { + "direction": "OUT" + }, + "PIPERX5CHANISALIGNED": { + "direction": "IN" + }, + "TRNRDLLPDATA27": { + "direction": "OUT" + }, + "CFGDSN3": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG83": { + "direction": "IN" + }, + "PIPERX4DATA1": { + "direction": "IN" + }, + "CFGMGMTDI26": { + "direction": "IN" + }, + "TRNFCCPLH6": { + "direction": "OUT" + }, + "MIMRXWDATA1": { + "direction": "OUT" + }, + "TL2ERRHDR61": { + "direction": "OUT" + }, + "PIPETX0CHARISK1": { + "direction": "OUT" + }, + "XILUNCONNOUT38": { + "direction": "OUT" + }, + "TL2ERRHDR24": { + "direction": "OUT" + }, + "TRNRD76": { + "direction": "OUT" + }, + "MIMTXRDATA22": { + "direction": "IN" + }, + "PIPETX7DATA8": { + "direction": "OUT" + }, + "PIPETX2CHARISK0": { + "direction": "OUT" + }, + "DBGVECA31": { + "direction": "OUT" + }, + "TRNTD79": { + "direction": "IN" + }, + "CFGSUBSYSID8": { + "direction": "IN" + }, + "CFGDSN22": { + "direction": "IN" + }, + "DBGVECB18": { + "direction": "OUT" + }, + "PIPERX0DATA10": { + "direction": "IN" + }, + "TRNRD16": { + "direction": "OUT" + }, + "PLDBGVEC3": { + "direction": "OUT" + }, + "PIPERX7CHARISK1": { + "direction": "IN" + }, + "PLINITIALLINKWIDTH1": { + "direction": "OUT" + }, + "PL2LINKUP": { + "direction": "OUT" + }, + "PIPERX4DATA8": { + "direction": "IN" + }, + "MIMTXWADDR12": { + "direction": "OUT" + }, + "MIMTXWDATA9": { + "direction": "OUT" + }, + "MIMRXWDATA54": { + "direction": "OUT" + }, + "PIPETX2DATA5": { + "direction": "OUT" + }, + "CFGMGMTDWADDR5": { + "direction": "IN" + }, + "DBGVECB28": { + "direction": "OUT" + }, + "PIPERX6PHYSTATUS": { + "direction": "IN" + }, + "CFGDSDEVICENUMBER0": { + "direction": "IN" + }, + "PIPERX3PHYSTATUS": { + "direction": "IN" + }, + "MIMTXWDATA31": { + "direction": "OUT" + }, + "PIPETX0DATA5": { + "direction": "OUT" + }, + "TRNLNKUP": { + "direction": "OUT" + }, + "PL2RECOVERY": { + "direction": "OUT" + }, + "PIPERX4DATA7": { + "direction": "IN" + }, + "MIMRXRDATA13": { + "direction": "IN" + }, + "TL2ERRHDR7": { + "direction": "OUT" + }, + "DBGVECA61": { + "direction": "OUT" + }, + "CFGERRACSN": { + "direction": "IN" + }, + "CFGDSN14": { + "direction": "IN" + }, + "MIMTXRDATA55": { + "direction": "IN" + }, + "CFGDSN12": { + "direction": "IN" + }, + "DBGVECA25": { + "direction": "OUT" + }, + "TRNRD53": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDDEASSERTINTB": { + "direction": "OUT" + }, + "MIMRXRDATA7": { + "direction": "IN" + }, + "PIPETXRCVRDET": { + "direction": "OUT" + }, + "MIMRXWADDR9": { + "direction": "OUT" + }, + "CFGSUBSYSVENDID15": { + "direction": "IN" + }, + "TRNRD66": { + "direction": "OUT" + }, + "PIPETX2POWERDOWN0": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER43": { + "direction": "IN" + }, + "DBGVECC5": { + "direction": "OUT" + }, + "PIPERX3DATA12": { + "direction": "IN" + }, + "CFGSUBSYSVENDID8": { + "direction": "IN" + }, + "TRNRBARHIT7": { + "direction": "OUT" + }, + "TL2ERRHDR44": { + "direction": "OUT" + }, + "MIMTXRDATA18": { + "direction": "IN" + }, + "TRNRDLLPDATA47": { + "direction": "OUT" + }, + "TRNTDLLPDATA11": { + "direction": "IN" + }, + "PIPETX2DATA14": { + "direction": "OUT" + }, + "TRNFCCPLD1": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER20": { + "direction": "IN" + }, + "TRNTBUFAV1": { + "direction": "OUT" + }, + "PIPETX0DATA6": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG119": { + "direction": "IN" + }, + "TRNTD2": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG55": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER6": { + "direction": "IN" + }, + "TRNFCPH6": { + "direction": "OUT" + }, + "MIMTXRDATA5": { + "direction": "IN" + }, + "CFGAERROOTERRCORRERRREPORTINGEN": { + "direction": "OUT" + }, + "DBGVECA1": { + "direction": "OUT" + }, + "CFGDSN62": { + "direction": "IN" + }, + "TRNRDLLPDATA48": { + "direction": "OUT" + }, + "PLLTSSMSTATE3": { + "direction": "OUT" + }, + "DBGSCLRF": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDPMPME": { + "direction": "OUT" + }, + "CFGERRATOMICEGRESSBLOCKEDN": { + "direction": "IN" + }, + "CFGAERECRCCHECKEN": { + "direction": "OUT" + }, + "TRNFCPD0": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG14": { + "direction": "IN" + }, + "CFGLINKSTATUSNEGOTIATEDWIDTH0": { + "direction": "OUT" + }, + "TRNFCPH0": { + "direction": "OUT" + }, + "PIPERX2DATA10": { + "direction": "IN" + }, + "EDTCHANNELSIN8": { + "direction": "IN" + }, + "TRNRD10": { + "direction": "OUT" + }, + "CFGVENDID1": { + "direction": "IN" + }, + "CFGMGMTDI3": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG82": { + "direction": "IN" + }, + "MIMRXWDATA23": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG72": { + "direction": "IN" + }, + "TRNTD67": { + "direction": "IN" + }, + "MIMRXWDATA60": { + "direction": "OUT" + }, + "MIMTXWDATA54": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER42": { + "direction": "IN" + }, + "CFGMGMTWRREADONLYN": { + "direction": "IN" + }, + "EDTBYPASS": { + "direction": "IN" + }, + "DBGVECB62": { + "direction": "OUT" + }, + "PIPERX5DATA5": { + "direction": "IN" + }, + "TRNTDSTRDY0": { + "direction": "OUT" + }, + "PIPERX6DATA6": { + "direction": "IN" + }, + "MIMRXRDATA49": { + "direction": "IN" + }, + "CFGDEVCONTROL2CPLTIMEOUTVAL2": { + "direction": "OUT" + }, + "DBGVECA9": { + "direction": "OUT" + }, + "DBGVECA51": { + "direction": "OUT" + }, + "MIMTXRDATA38": { + "direction": "IN" + }, + "MIMTXWDATA7": { + "direction": "OUT" + }, + "MIMRXWDATA8": { + "direction": "OUT" + }, + "PIPETX1DATA3": { + "direction": "OUT" + }, + "CFGERRCORN": { + "direction": "IN" + }, + "PIPETX1DATA1": { + "direction": "OUT" + }, + "PIPETX2DATA1": { + "direction": "OUT" + }, + "PIPETX3DATA4": { + "direction": "OUT" + }, + "DBGVECA39": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER9": { + "direction": "IN" + }, + "MIMRXWDATA61": { + "direction": "OUT" + }, + "XILUNCONNOUT29": { + "direction": "OUT" + }, + "PIPERX1DATA4": { + "direction": "IN" + }, + "MIMRXWDATA41": { + "direction": "OUT" + }, + "MIMTXRDATA6": { + "direction": "IN" + }, + "PIPERX5DATA3": { + "direction": "IN" + }, + "TL2ERRHDR47": { + "direction": "OUT" + }, + "TRNRD22": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG70": { + "direction": "IN" + }, + "CFGFORCEMPS1": { + "direction": "IN" + }, + "TRNTD57": { + "direction": "IN" + }, + "USERCLKPREBUF": { + "direction": "IN" + }, + "TRNFCNPH6": { + "direction": "OUT" + }, + "PIPETX1DATA13": { + "direction": "OUT" + }, + "XILUNCONNOUT0": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG12": { + "direction": "IN" + }, + "MIMTXWDATA46": { + "direction": "OUT" + }, + "PIPERX3DATA13": { + "direction": "IN" + }, + "TRNFCPD8": { + "direction": "OUT" + }, + "PIPERX0CHANISALIGNED": { + "direction": "IN" + }, + "TRNTD107": { + "direction": "IN" + }, + "MIMRXRADDR12": { + "direction": "OUT" + }, + "XILUNCONNOUT17": { + "direction": "OUT" + }, + "PIPERX0STATUS0": { + "direction": "IN" + }, + "DBGVECC2": { + "direction": "OUT" + }, + "DRPDI9": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER21": { + "direction": "IN" + }, + "MIMTXWADDR9": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER39": { + "direction": "IN" + }, + "DRPDI7": { + "direction": "IN" + }, + "TRNTD8": { + "direction": "IN" + }, + "MIMTXRDATA57": { + "direction": "IN" + }, + "DBGSCLRH": { + "direction": "OUT" + }, + "CFGMGMTDO15": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG24": { + "direction": "IN" + }, + "CFGERRPOSTEDN": { + "direction": "IN" + }, + "DBGVECA57": { + "direction": "OUT" + }, + "SCANMODEN": { + "direction": "IN" + }, + "PIPERX2VALID": { + "direction": "IN" + }, + "CFGMGMTBYTEENN3": { + "direction": "IN" + }, + "TRNTD108": { + "direction": "IN" + }, + "TRNTD110": { + "direction": "IN" + }, + "CFGINTERRUPTDI0": { + "direction": "IN" + }, + "TRNFCCPLD11": { + "direction": "OUT" + }, + "TRNRD102": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER25": { + "direction": "IN" + }, + "PIPERX5PHYSTATUS": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG96": { + "direction": "IN" + }, + "CFGMGMTDO20": { + "direction": "OUT" + }, + "PIPETX1DATA7": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG91": { + "direction": "IN" + }, + "DBGVECA13": { + "direction": "OUT" + }, + "MIMTXREN": { + "direction": "OUT" + }, + "CFGPMFORCESTATEENN": { + "direction": "IN" + }, + "DRPDI0": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG27": { + "direction": "IN" + }, + "CFGMGMTDO12": { + "direction": "OUT" + }, + "PLINITIALLINKWIDTH0": { + "direction": "OUT" + }, + "PIPETX5CHARISK1": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG44": { + "direction": "IN" + }, + "CFGREVID6": { + "direction": "IN" + }, + "TRNFCSEL1": { + "direction": "IN" + }, + "CFGFORCECOMMONCLOCKOFF": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG78": { + "direction": "IN" + }, + "TRNRDLLPDATA22": { + "direction": "OUT" + }, + "CFGFORCEMPS0": { + "direction": "IN" + }, + "PIPETX2DATA2": { + "direction": "OUT" + }, + "PIPETX5DATA5": { + "direction": "OUT" + }, + "DBGSCLRI": { + "direction": "OUT" + }, + "PIPETX6DATA13": { + "direction": "OUT" + }, + "MIMRXWDATA32": { + "direction": "OUT" + }, + "TRNRBARHIT1": { + "direction": "OUT" + }, + "DLRSTN": { + "direction": "IN" + }, + "MIMRXRDATA40": { + "direction": "IN" + }, + "DRPDI6": { + "direction": "IN" + }, + "DBGVECB48": { + "direction": "OUT" + }, + "TRNTDLLPDATA18": { + "direction": "IN" + }, + "PIPERX5DATA2": { + "direction": "IN" + }, + "DBGVECA30": { + "direction": "OUT" + }, + "TRNFCCPLD5": { + "direction": "OUT" + }, + "CFGDEVCONTROL2ATOMICREQUESTEREN": { + "direction": "OUT" + }, + "CFGMGMTDI22": { + "direction": "IN" + }, + "TRNTDLLPDSTRDY": { + "direction": "OUT" + }, + "TRNTD36": { + "direction": "IN" + }, + "MIMTXRADDR2": { + "direction": "OUT" + }, + "MIMTXRDATA4": { + "direction": "IN" + }, + "MIMRXRDATA18": { + "direction": "IN" + }, + "MIMRXRDATA45": { + "direction": "IN" + }, + "TRNTD73": { + "direction": "IN" + }, + "TRNRD78": { + "direction": "OUT" + }, + "TRNTD18": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG65": { + "direction": "IN" + }, + "CFGDSN49": { + "direction": "IN" + }, + "TRNRD12": { + "direction": "OUT" + }, + "PIPETX7DATA10": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG33": { + "direction": "IN" + }, + "PIPETX6ELECIDLE": { + "direction": "OUT" + }, + "TRNRD116": { + "direction": "OUT" + }, + "CFGMGMTDO3": { + "direction": "OUT" + }, + "CFGINTERRUPTDO4": { + "direction": "OUT" + }, + "PIPERX5DATA12": { + "direction": "IN" + }, + "MIMTXWDATA26": { + "direction": "OUT" + }, + "DRPDO8": { + "direction": "OUT" + }, + "MIMTXRDATA46": { + "direction": "IN" + }, + "DBGVECB29": { + "direction": "OUT" + }, + "CFGMGMTDO22": { + "direction": "OUT" + }, + "CFGDSN4": { + "direction": "IN" + }, + "CFGPORTNUMBER0": { + "direction": "IN" + }, + "MIMRXRDATA65": { + "direction": "IN" + }, + "CFGMGMTDO18": { + "direction": "OUT" + }, + "CFGPMRCVASREQL1N": { + "direction": "OUT" + }, + "PIPERX0ELECIDLE": { + "direction": "IN" + }, + "MIMTXWDATA48": { + "direction": "OUT" + }, + "MIMRXWADDR11": { + "direction": "OUT" + }, + "TRNRDLLPDATA9": { + "direction": "OUT" + }, + "TRNTD113": { + "direction": "IN" + }, + "MIMRXWDATA7": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG98": { + "direction": "IN" + }, + "PIPETX3DATA5": { + "direction": "OUT" + }, + "PIPERX7DATA0": { + "direction": "IN" + }, + "TRNTD43": { + "direction": "IN" + }, + "MIMRXRDATA46": { + "direction": "IN" + }, + "PIPETX3POWERDOWN0": { + "direction": "OUT" + }, + "MIMTXWDATA4": { + "direction": "OUT" + }, + "MIMRXWDATA9": { + "direction": "OUT" + }, + "DBGVECA15": { + "direction": "OUT" + }, + "CFGERRLOCKEDN": { + "direction": "IN" + }, + "CFGSUBSYSVENDID11": { + "direction": "IN" + }, + "TRNTD27": { + "direction": "IN" + }, + "EDTCHANNELSIN7": { + "direction": "IN" + }, + "CFGMGMTDI12": { + "direction": "IN" + }, + "TRNRD38": { + "direction": "OUT" + }, + "PIPETX5DATA14": { + "direction": "OUT" + }, + "TRNRDLLPDATA29": { + "direction": "OUT" + }, + "LL2SUSPENDNOW": { + "direction": "IN" + }, + "DBGVECA38": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG39": { + "direction": "IN" + }, + "CFGMGMTDI10": { + "direction": "IN" + }, + "PIPERX2ELECIDLE": { + "direction": "IN" + }, + "MIMRXRDATA30": { + "direction": "IN" + }, + "TRNTD105": { + "direction": "IN" + }, + "PIPERX7DATA8": { + "direction": "IN" + }, + "CFGPCIECAPINTERRUPTMSGNUM1": { + "direction": "IN" + }, + "PL2RXELECIDLE": { + "direction": "OUT" + }, + "DBGVECB3": { + "direction": "OUT" + }, + "TRNFCNPD2": { + "direction": "OUT" + }, + "MIMRXWADDR12": { + "direction": "OUT" + }, + "PIPERX5DATA13": { + "direction": "IN" + }, + "PIPETX5DATA0": { + "direction": "OUT" + }, + "PIPETX2COMPLIANCE": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER44": { + "direction": "IN" + }, + "PIPERX4STATUS1": { + "direction": "IN" + }, + "MIMTXRDATA45": { + "direction": "IN" + }, + "PIPETX1DATA12": { + "direction": "OUT" + }, + "PLLINKPARTNERGEN2SUPPORTED": { + "direction": "OUT" + }, + "DBGVECB2": { + "direction": "OUT" + }, + "CFGMSGDATA14": { + "direction": "OUT" + }, + "CFGAERROOTERRCORRERRRECEIVED": { + "direction": "OUT" + }, + "TL2ASPMSUSPENDREQ": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER35": { + "direction": "IN" + }, + "CFGVCTCVCMAP6": { + "direction": "OUT" + }, + "MIMTXRDATA2": { + "direction": "IN" + }, + "MIMTXWADDR0": { + "direction": "OUT" + }, + "CFGSUBSYSVENDID4": { + "direction": "IN" + }, + "DBGVECB11": { + "direction": "OUT" + }, + "CFGDSN44": { + "direction": "IN" + }, + "TRNFCPD4": { + "direction": "OUT" + }, + "TRNFCNPH4": { + "direction": "OUT" + }, + "MIMRXWDATA0": { + "direction": "OUT" + }, + "PIPERX0DATA0": { + "direction": "IN" + }, + "CFGMGMTDWADDR6": { + "direction": "IN" + }, + "PIPETX7COMPLIANCE": { + "direction": "OUT" + }, + "TRNRDLLPDATA1": { + "direction": "OUT" + }, + "PIPERX5CHARISK1": { + "direction": "IN" + }, + "TRNRD32": { + "direction": "OUT" + }, + "TRNRDLLPDATA52": { + "direction": "OUT" + }, + "CFGDSN24": { + "direction": "IN" + }, + "TRNRD109": { + "direction": "OUT" + }, + "CFGDSN17": { + "direction": "IN" + }, + "PLDIRECTEDLINKWIDTH1": { + "direction": "IN" + }, + "PIPERX0DATA4": { + "direction": "IN" + }, + "PIPERX7DATA3": { + "direction": "IN" + }, + "CFGPORTNUMBER5": { + "direction": "IN" + }, + "LL2BADTLPERR": { + "direction": "OUT" + }, + "TL2ERRHDR33": { + "direction": "OUT" + }, + "MIMRXWDATA44": { + "direction": "OUT" + }, + "TL2ERRFCPE": { + "direction": "OUT" + }, + "TRNTD127": { + "direction": "IN" + }, + "TRNRD28": { + "direction": "OUT" + }, + "XILUNCONNOUT32": { + "direction": "OUT" + }, + "TL2ERRHDR27": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG120": { + "direction": "IN" + }, + "LL2REPLAYTOERR": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG127": { + "direction": "IN" + }, + "MIMRXRADDR10": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG37": { + "direction": "IN" + }, + "XILUNCONNOUT34": { + "direction": "OUT" + }, + "MIMRXRDATA28": { + "direction": "IN" + }, + "CFGMSGRECEIVED": { + "direction": "OUT" + }, + "CFGSUBSYSVENDID1": { + "direction": "IN" + }, + "PLLANEREVERSALMODE0": { + "direction": "OUT" + }, + "TRNFCCPLH4": { + "direction": "OUT" + }, + "PIPERX6STATUS0": { + "direction": "IN" + }, + "MIMTXRDATA14": { + "direction": "IN" + }, + "MIMTXRDATA66": { + "direction": "IN" + }, + "TRNRD74": { + "direction": "OUT" + }, + "MIMTXWDATA56": { + "direction": "OUT" + }, + "PIPERX2STATUS1": { + "direction": "IN" + }, + "PLSELLNKRATE": { + "direction": "OUT" + }, + "TRNRD80": { + "direction": "OUT" + }, + "PIPETX6DATA7": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG11": { + "direction": "IN" + }, + "CFGMSGDATA11": { + "direction": "OUT" + }, + "CFGLINKSTATUSCURRENTSPEED1": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG23": { + "direction": "IN" + }, + "CFGDSN52": { + "direction": "IN" + }, + "DBGVECA52": { + "direction": "OUT" + }, + "MIMTXWDATA1": { + "direction": "OUT" + }, + "MIMTXRADDR12": { + "direction": "OUT" + }, + "MIMRXWDATA42": { + "direction": "OUT" + }, + "MIMTXWADDR3": { + "direction": "OUT" + }, + "MIMRXWDATA38": { + "direction": "OUT" + }, + "TRNRDLLPDATA0": { + "direction": "OUT" + }, + "PIPERX3DATA10": { + "direction": "IN" + }, + "TRNTD85": { + "direction": "IN" + }, + "MIMTXWDATA47": { + "direction": "OUT" + }, + "PIPETX0DATA14": { + "direction": "OUT" + }, + "TRNRD123": { + "direction": "OUT" + }, + "PIPERX7DATA7": { + "direction": "IN" + }, + "CFGDSDEVICENUMBER4": { + "direction": "IN" + }, + "CFGDSN16": { + "direction": "IN" + }, + "CFGDEVCONTROLPHANTOMEN": { + "direction": "OUT" + }, + "TRNRD42": { + "direction": "OUT" + }, + "PIPETX5ELECIDLE": { + "direction": "OUT" + }, + "DBGVECB36": { + "direction": "OUT" + }, + "PIPETX4COMPLIANCE": { + "direction": "OUT" + }, + "PLDOWNSTREAMDEEMPHSOURCE": { + "direction": "IN" + }, + "TRNRD68": { + "direction": "OUT" + }, + "TRNRD117": { + "direction": "OUT" + }, + "PIPERX3DATA7": { + "direction": "IN" + }, + "PIPETX5DATA13": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG32": { + "direction": "IN" + }, + "DBGVECC0": { + "direction": "OUT" + }, + "CFGDSN60": { + "direction": "IN" + }, + "TRNRDLLPDATA61": { + "direction": "OUT" + }, + "USERRSTN": { + "direction": "OUT" + }, + "MIMRXWDATA14": { + "direction": "OUT" + }, + "DRPDI4": { + "direction": "IN" + }, + "MIMRXWDATA59": { + "direction": "OUT" + }, + "PIPETX2DATA11": { + "direction": "OUT" + }, + "DBGVECA43": { + "direction": "OUT" + }, + "TRNFCCPLD3": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDASSERTINTD": { + "direction": "OUT" + }, + "CFGMGMTDO25": { + "direction": "OUT" + }, + "CFGDEVID7": { + "direction": "IN" + }, + "PIPERX1PHYSTATUS": { + "direction": "IN" + }, + "TRNRD101": { + "direction": "OUT" + }, + "TRNTBUFAV3": { + "direction": "OUT" + }, + "PIPETX1CHARISK0": { + "direction": "OUT" + }, + "TRNRDLLPDATA42": { + "direction": "OUT" + }, + "PIPERX0DATA3": { + "direction": "IN" + }, + "MIMTXRADDR4": { + "direction": "OUT" + }, + "MIMRXWDATA37": { + "direction": "OUT" + }, + "CFGDSN51": { + "direction": "IN" + }, + "TRNRD55": { + "direction": "OUT" + }, + "CFGDEVCONTROL2IDOCPLEN": { + "direction": "OUT" + }, + "MIMTXRDATA23": { + "direction": "IN" + }, + "CFGSUBSYSVENDID10": { + "direction": "IN" + }, + "PIPETXRATE": { + "direction": "OUT" + }, + "TRNTD63": { + "direction": "IN" + }, + "TRNRD86": { + "direction": "OUT" + }, + "MIMTXWDATA58": { + "direction": "OUT" + }, + "TRNRD43": { + "direction": "OUT" + }, + "CFGREVID1": { + "direction": "IN" + }, + "MIMRXRDATA22": { + "direction": "IN" + }, + "PIPETX1COMPLIANCE": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER15": { + "direction": "IN" + }, + "PIPERX7STATUS2": { + "direction": "IN" + }, + "XILUNCONNOUT16": { + "direction": "OUT" + }, + "CFGDEVCONTROL2CPLTIMEOUTVAL0": { + "direction": "OUT" + }, + "TRNTD97": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER32": { + "direction": "IN" + }, + "TRNRD65": { + "direction": "OUT" + }, + "MIMRXRDATA5": { + "direction": "IN" + }, + "PIPETX6DATA14": { + "direction": "OUT" + }, + "MIMTXWDATA66": { + "direction": "OUT" + }, + "TRNTDSTRDY2": { + "direction": "OUT" + }, + "TRNFCPD10": { + "direction": "OUT" + }, + "TRNTDLLPDATA10": { + "direction": "IN" + }, + "PMVENABLEN": { + "direction": "IN" + }, + "CFGLINKCONTROLEXTENDEDSYNC": { + "direction": "OUT" + }, + "TRNTD1": { + "direction": "IN" + }, + "CFGPCIECAPINTERRUPTMSGNUM2": { + "direction": "IN" + }, + "TL2ERRHDR18": { + "direction": "OUT" + }, + "DBGVECB23": { + "direction": "OUT" + }, + "TL2ERRHDR26": { + "direction": "OUT" + }, + "MIMTXRDATA44": { + "direction": "IN" + }, + "CFGDSBUSNUMBER7": { + "direction": "IN" + }, + "PIPETX0DATA4": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDERRNONFATAL": { + "direction": "OUT" + }, + "MIMTXWDATA34": { + "direction": "OUT" + }, + "PLTXPMSTATE0": { + "direction": "OUT" + }, + "PLUPSTREAMPREFERDEEMPH": { + "direction": "IN" + }, + "TRNTD95": { + "direction": "IN" + }, + "TRNTD124": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG2": { + "direction": "IN" + }, + "CFGMSGDATA12": { + "direction": "OUT" + }, + "CFGTRANSACTIONADDR0": { + "direction": "OUT" + }, + "DBGVECA21": { + "direction": "OUT" + }, + "TRNRDLLPDATA44": { + "direction": "OUT" + }, + "PIPETX7DATA6": { + "direction": "OUT" + }, + "PL2DIRECTEDLSTATE3": { + "direction": "IN" + }, + "PIPETX7DATA15": { + "direction": "OUT" + }, + "DBGVECA17": { + "direction": "OUT" + }, + "CFGCOMMANDBUSMASTERENABLE": { + "direction": "OUT" + }, + "PIPERX1DATA12": { + "direction": "IN" + }, + "TRNTBUFAV4": { + "direction": "OUT" + }, + "CFGLINKSTATUSNEGOTIATEDWIDTH1": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG17": { + "direction": "IN" + }, + "PIPETX3POWERDOWN1": { + "direction": "OUT" + }, + "MIMRXRDATA56": { + "direction": "IN" + }, + "CFGAERINTERRUPTMSGNUM1": { + "direction": "IN" + }, + "CFGDSN38": { + "direction": "IN" + }, + "PIPETX2POWERDOWN1": { + "direction": "OUT" + }, + "PIPETX0DATA13": { + "direction": "OUT" + }, + "MIMRXRDATA29": { + "direction": "IN" + }, + "MIMTXRDATA60": { + "direction": "IN" + }, + "PIPETX5DATA6": { + "direction": "OUT" + }, + "MIMTXWDATA63": { + "direction": "OUT" + }, + "MIMTXWADDR1": { + "direction": "OUT" + }, + "CFGMSGDATA6": { + "direction": "OUT" + }, + "MIMRXWDATA21": { + "direction": "OUT" + }, + "TL2ERRHDR23": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG21": { + "direction": "IN" + }, + "MIMTXRDATA0": { + "direction": "IN" + }, + "CFGMSGRECEIVEDDEASSERTINTC": { + "direction": "OUT" + }, + "TRNRD119": { + "direction": "OUT" + }, + "CFGERRURN": { + "direction": "IN" + }, + "CFGLINKSTATUSBANDWIDTHSTATUS": { + "direction": "OUT" + }, + "TRNRDLLPDATA30": { + "direction": "OUT" + }, + "MIMRXWDATA39": { + "direction": "OUT" + }, + "PIPETX4DATA7": { + "direction": "OUT" + }, + "TL2ERRHDR15": { + "direction": "OUT" + }, + "TRNTD76": { + "direction": "IN" + }, + "CFGROOTCONTROLPMEINTEN": { + "direction": "OUT" + }, + "MIMRXWDATA50": { + "direction": "OUT" + }, + "PIPERX5VALID": { + "direction": "IN" + }, + "TRNTD115": { + "direction": "IN" + }, + "CFGMGMTDO16": { + "direction": "OUT" + }, + "MIMRXWDATA25": { + "direction": "OUT" + }, + "MIMTXWDATA65": { + "direction": "OUT" + }, + "CFGDSN20": { + "direction": "IN" + }, + "TRNTDLLPDATA5": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG110": { + "direction": "IN" + }, + "CFGMGMTDO5": { + "direction": "OUT" + }, + "PIPERX6CHARISK1": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG99": { + "direction": "IN" + }, + "PIPERX3DATA5": { + "direction": "IN" + }, + "MIMRXRDATA35": { + "direction": "IN" + }, + "PIPERX1CHARISK0": { + "direction": "IN" + }, + "DBGVECA42": { + "direction": "OUT" + }, + "MIMTXRDATA13": { + "direction": "IN" + }, + "TRNTD81": { + "direction": "IN" + }, + "DBGVECB19": { + "direction": "OUT" + }, + "DBGVECA46": { + "direction": "OUT" + }, + "MIMRXRDATA53": { + "direction": "IN" + }, + "MIMTXRDATA7": { + "direction": "IN" + }, + "TRNRD111": { + "direction": "OUT" + }, + "MIMRXRDATA3": { + "direction": "IN" + }, + "LL2TXIDLE": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG69": { + "direction": "IN" + }, + "DBGVECB44": { + "direction": "OUT" + }, + "PIPETX5DATA12": { + "direction": "OUT" + }, + "PIPETX6DATA11": { + "direction": "OUT" + }, + "TRNRDLLPDATA34": { + "direction": "OUT" + }, + "CFGMGMTDWADDR4": { + "direction": "IN" + }, + "EDTCHANNELSOUT7": { + "direction": "OUT" + }, + "PIPERX4DATA11": { + "direction": "IN" + }, + "MIMRXWDATA16": { + "direction": "OUT" + }, + "CFGINTERRUPTDI2": { + "direction": "IN" + }, + "MIMTXRDATA24": { + "direction": "IN" + }, + "CFGMSGDATA0": { + "direction": "OUT" + }, + "XILUNCONNOUT39": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER2": { + "direction": "IN" + }, + "CFGVENDID15": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG77": { + "direction": "IN" + }, + "DBGVECA37": { + "direction": "OUT" + }, + "PIPETX0CHARISK0": { + "direction": "OUT" + }, + "PIPERX1DATA6": { + "direction": "IN" + }, + "TRNRDLLPSRCRDY0": { + "direction": "OUT" + }, + "MIMTXWDATA11": { + "direction": "OUT" + }, + "CFGDSN31": { + "direction": "IN" + }, + "PIPETX6POWERDOWN0": { + "direction": "OUT" + }, + "MIMRXRADDR11": { + "direction": "OUT" + }, + "DBGVECA24": { + "direction": "OUT" + }, + "PIPERX6CHANISALIGNED": { + "direction": "IN" + }, + "TRNTD70": { + "direction": "IN" + }, + "TRNRDLLPDATA31": { + "direction": "OUT" + }, + "TRNRD98": { + "direction": "OUT" + }, + "PIPETX7DATA14": { + "direction": "OUT" + }, + "TRNTD22": { + "direction": "IN" + }, + "TRNTSTR": { + "direction": "IN" + }, + "MIMRXWDATA26": { + "direction": "OUT" + }, + "CFGVENDID11": { + "direction": "IN" + }, + "PLDIRECTEDLINKCHANGE1": { + "direction": "IN" + }, + "DRPDI11": { + "direction": "IN" + }, + "PLDIRECTEDLTSSMNEWVLD": { + "direction": "IN" + }, + "TRNRD95": { + "direction": "OUT" + }, + "PLRXPMSTATE0": { + "direction": "OUT" + }, + "TRNRD83": { + "direction": "OUT" + }, + "EDTCHANNELSIN5": { + "direction": "IN" + }, + "TRNTD5": { + "direction": "IN" + }, + "TRNRDLLPDATA45": { + "direction": "OUT" + }, + "PIPETXRESET": { + "direction": "OUT" + }, + "PIPETX3DATA9": { + "direction": "OUT" + }, + "MIMTXWDATA6": { + "direction": "OUT" + }, + "TL2ERRHDR41": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG38": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG71": { + "direction": "IN" + }, + "TRNTD119": { + "direction": "IN" + }, + "CFGVENDID8": { + "direction": "IN" + }, + "PIPETX5DATA4": { + "direction": "OUT" + }, + "DBGVECB39": { + "direction": "OUT" + }, + "PIPERX1DATA7": { + "direction": "IN" + }, + "CFGTRANSACTIONADDR6": { + "direction": "OUT" + }, + "PLRXPMSTATE1": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG50": { + "direction": "IN" + }, + "PIPETX2CHARISK1": { + "direction": "OUT" + }, + "PIPETX3DATA2": { + "direction": "OUT" + }, + "CFGLINKSTATUSNEGOTIATEDWIDTH3": { + "direction": "OUT" + }, + "MIMTXRADDR0": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER7": { + "direction": "IN" + }, + "DBGVECA4": { + "direction": "OUT" + }, + "CFGDSBUSNUMBER1": { + "direction": "IN" + }, + "EDTSINGLEBYPASSCHAIN": { + "direction": "IN" + }, + "CFGINTERRUPTASSERTN": { + "direction": "IN" + }, + "CFGMGMTDI19": { + "direction": "IN" + }, + "PIPERX7DATA6": { + "direction": "IN" + }, + "TRNRD126": { + "direction": "OUT" + }, + "TRNRD122": { + "direction": "OUT" + }, + "MIMTXWDATA5": { + "direction": "OUT" + }, + "MIMRXRDATA44": { + "direction": "IN" + }, + "MIMTXWDATA57": { + "direction": "OUT" + }, + "CFGDSN8": { + "direction": "IN" + }, + "TRNFCNPD10": { + "direction": "OUT" + }, + "CFGINTERRUPTDI5": { + "direction": "IN" + }, + "PLDBGVEC2": { + "direction": "OUT" + }, + "TRNRDLLPDATA2": { + "direction": "OUT" + }, + "TRNRDLLPDATA4": { + "direction": "OUT" + }, + "PIPETX4DATA3": { + "direction": "OUT" + }, + "MIMTXRADDR7": { + "direction": "OUT" + }, + "PIPERX6CHARISK0": { + "direction": "IN" + }, + "PIPETX5COMPLIANCE": { + "direction": "OUT" + }, + "MIMTXRDATA63": { + "direction": "IN" + }, + "MIMRXRADDR2": { + "direction": "OUT" + }, + "MIMRXRDATA12": { + "direction": "IN" + }, + "TRNTD91": { + "direction": "IN" + }, + "PIPERX0DATA14": { + "direction": "IN" + }, + "XILUNCONNOUT5": { + "direction": "OUT" + }, + "PIPETX1POWERDOWN1": { + "direction": "OUT" + }, + "CFGMGMTDO6": { + "direction": "OUT" + }, + "MIMTXRDATA49": { + "direction": "IN" + }, + "TRNTDLLPSRCRDY": { + "direction": "IN" + }, + "CFGINTERRUPTDI1": { + "direction": "IN" + }, + "DBGMODE1": { + "direction": "IN" + }, + "PIPECLK": { + "direction": "IN" + }, + "TRNTDSTRDY3": { + "direction": "OUT" + }, + "TRNRD15": { + "direction": "OUT" + }, + "CFGDSN50": { + "direction": "IN" + }, + "TRNRD106": { + "direction": "OUT" + }, + "TRNRD60": { + "direction": "OUT" + }, + "MIMRXRDATA64": { + "direction": "IN" + }, + "CFGDEVSTATUSFATALERRDETECTED": { + "direction": "OUT" + }, + "PIPERX3DATA6": { + "direction": "IN" + }, + "DRPCLK": { + "direction": "IN" + }, + "XILUNCONNOUT14": { + "direction": "OUT" + }, + "CFGFORCEMPS2": { + "direction": "IN" + }, + "MIMRXWDATA19": { + "direction": "OUT" + }, + "DRPDO2": { + "direction": "OUT" + }, + "PIPERX7DATA9": { + "direction": "IN" + }, + "MIMTXRDATA37": { + "direction": "IN" + }, + "CFGMGMTDWADDR3": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG113": { + "direction": "IN" + }, + "CFGAERROOTERRFATALERRREPORTINGEN": { + "direction": "OUT" + }, + "DRPDI15": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER10": { + "direction": "IN" + }, + "LL2SUSPENDOK": { + "direction": "OUT" + }, + "PIPETX3DATA1": { + "direction": "OUT" + }, + "PIPERX2DATA6": { + "direction": "IN" + }, + "MIMTXWDATA61": { + "direction": "OUT" + }, + "PIPETX6DATA9": { + "direction": "OUT" + }, + "TRNTD84": { + "direction": "IN" + }, + "CFGERRCPLRDYN": { + "direction": "OUT" + }, + "PIPETX7DATA1": { + "direction": "OUT" + }, + "TRNTD64": { + "direction": "IN" + }, + "MIMTXWDATA55": { + "direction": "OUT" + }, + "MIMTXWDATA42": { + "direction": "OUT" + }, + "TRNTDLLPDATA20": { + "direction": "IN" + }, + "DBGVECA44": { + "direction": "OUT" + }, + "XILUNCONNOUT13": { + "direction": "OUT" + }, + "DRPDO10": { + "direction": "OUT" + }, + "TRNTD75": { + "direction": "IN" + }, + "MIMTXWDATA2": { + "direction": "OUT" + }, + "CFGMGMTDI30": { + "direction": "IN" + }, + "TRNRDLLPDATA55": { + "direction": "OUT" + }, + "MIMTXRDATA26": { + "direction": "IN" + }, + "TL2ERRHDR16": { + "direction": "OUT" + }, + "TRNRD104": { + "direction": "OUT" + }, + "CFGTRANSACTIONADDR4": { + "direction": "OUT" + }, + "PIPETX3DATA14": { + "direction": "OUT" + }, + "MIMRXRDATA33": { + "direction": "IN" + }, + "TRNRD90": { + "direction": "OUT" + }, + "MIMTXWDATA28": { + "direction": "OUT" + }, + "CFGSUBSYSID11": { + "direction": "IN" + }, + "MIMTXWDATA37": { + "direction": "OUT" + }, + "MIMTXRDATA30": { + "direction": "IN" + }, + "TRNTDLLPDATA7": { + "direction": "IN" + }, + "TRNRDLLPDATA54": { + "direction": "OUT" + }, + "CFGVENDID7": { + "direction": "IN" + }, + "CFGMGMTDI21": { + "direction": "IN" + }, + "MIMTXRDATA3": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER26": { + "direction": "IN" + }, + "TRNRDLLPDATA28": { + "direction": "OUT" + }, + "CFGDSN26": { + "direction": "IN" + }, + "PIPETX1DATA10": { + "direction": "OUT" + }, + "MIMRXWDATA55": { + "direction": "OUT" + }, + "TRNFCPH2": { + "direction": "OUT" + }, + "TRNTD20": { + "direction": "IN" + }, + "MIMTXRDATA47": { + "direction": "IN" + }, + "PLLINKGEN2CAP": { + "direction": "OUT" + }, + "CFGSUBSYSVENDID3": { + "direction": "IN" + }, + "TRNRDLLPDATA23": { + "direction": "OUT" + }, + "CFGBRIDGESERREN": { + "direction": "OUT" + }, + "MIMTXRDATA62": { + "direction": "IN" + }, + "DBGVECA40": { + "direction": "OUT" + }, + "MIMRXRDATA31": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG51": { + "direction": "IN" + }, + "TRNRD70": { + "direction": "OUT" + }, + "CFGINTERRUPTN": { + "direction": "IN" + }, + "DRPDO12": { + "direction": "OUT" + }, + "TRNRD45": { + "direction": "OUT" + }, + "PIPERX2STATUS0": { + "direction": "IN" + }, + "MIMTXRADDR8": { + "direction": "OUT" + }, + "PIPETX0ELECIDLE": { + "direction": "OUT" + }, + "PLRSTN": { + "direction": "IN" + }, + "MIMTXWDATA43": { + "direction": "OUT" + }, + "TRNRSRCRDY": { + "direction": "OUT" + }, + "MIMRXRDATA59": { + "direction": "IN" + }, + "CFGDSN7": { + "direction": "IN" + }, + "CFGMGMTDI1": { + "direction": "IN" + }, + "TRNRD58": { + "direction": "OUT" + }, + "TRNTD28": { + "direction": "IN" + }, + "PIPETX2DATA3": { + "direction": "OUT" + }, + "PIPERX6DATA10": { + "direction": "IN" + }, + "MIMTXWDATA40": { + "direction": "OUT" + }, + "TRNTDLLPDATA19": { + "direction": "IN" + }, + "PIPERX0CHARISK0": { + "direction": "IN" + }, + "CFGLINKCONTROLBANDWIDTHINTEN": { + "direction": "OUT" + }, + "PL2DIRECTEDLSTATE4": { + "direction": "IN" + }, + "PIPERX6DATA2": { + "direction": "IN" + }, + "DBGVECC11": { + "direction": "OUT" + }, + "MIMTXWDATA14": { + "direction": "OUT" + }, + "CFGMGMTRDWRDONEN": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER36": { + "direction": "IN" + }, + "PIPETX6DATA12": { + "direction": "OUT" + }, + "TRNFCPH4": { + "direction": "OUT" + }, + "EDTUPDATE": { + "direction": "IN" + }, + "CFGDEVID4": { + "direction": "IN" + }, + "TRNRD0": { + "direction": "OUT" + }, + "TRNFCNPH1": { + "direction": "OUT" + }, + "DRPDO14": { + "direction": "OUT" + }, + "MIMTXWDATA16": { + "direction": "OUT" + }, + "CFGSUBSYSVENDID0": { + "direction": "IN" + }, + "TRNTDLLPDATA23": { + "direction": "IN" + }, + "TRNTDLLPDATA25": { + "direction": "IN" + }, + "MIMRXWDATA63": { + "direction": "OUT" + }, + "PIPETX4DATA2": { + "direction": "OUT" + }, + "XILUNCONNOUT3": { + "direction": "OUT" + }, + "TRNRD34": { + "direction": "OUT" + }, + "MIMTXWADDR11": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG115": { + "direction": "IN" + }, + "TRNTEOF": { + "direction": "IN" + }, + "DBGSCLRD": { + "direction": "OUT" + }, + "TRNTD122": { + "direction": "IN" + }, + "TRNTD26": { + "direction": "IN" + }, + "PL2DIRECTEDLSTATE1": { + "direction": "IN" + }, + "MIMTXWDATA49": { + "direction": "OUT" + }, + "PIPERX2DATA2": { + "direction": "IN" + }, + "DBGVECA48": { + "direction": "OUT" + }, + "PIPERX2DATA11": { + "direction": "IN" + }, + "TRNFCCPLH0": { + "direction": "OUT" + }, + "CFGMGMTDO27": { + "direction": "OUT" + }, + "PIPERX4DATA12": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER18": { + "direction": "IN" + }, + "PIPERX2DATA4": { + "direction": "IN" + }, + "CFGMSGRECEIVEDDEASSERTINTD": { + "direction": "OUT" + }, + "PIPETX2DATA15": { + "direction": "OUT" + }, + "CFGLINKCONTROLRETRAINLINK": { + "direction": "OUT" + }, + "DRPDI3": { + "direction": "IN" + }, + "PIPETX4DATA9": { + "direction": "OUT" + }, + "PIPERX7CHANISALIGNED": { + "direction": "IN" + }, + "PIPETX2DATA4": { + "direction": "OUT" + }, + "PIPERX3CHARISK0": { + "direction": "IN" + }, + "PIPETX6DATA3": { + "direction": "OUT" + }, + "PIPERX2DATA9": { + "direction": "IN" + }, + "CFGSUBSYSID4": { + "direction": "IN" + }, + "TRNTD93": { + "direction": "IN" + }, + "CFGSUBSYSVENDID6": { + "direction": "IN" + }, + "DBGSCLRA": { + "direction": "OUT" + }, + "DBGVECB6": { + "direction": "OUT" + }, + "TRNRDLLPDATA15": { + "direction": "OUT" + }, + "CFGMSGDATA7": { + "direction": "OUT" + }, + "CMRSTN": { + "direction": "IN" + }, + "PLDIRECTEDCHANGEDONE": { + "direction": "OUT" + }, + "MIMRXRADDR3": { + "direction": "OUT" + }, + "TL2ERRHDR10": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG76": { + "direction": "IN" + }, + "TRNRDLLPDATA21": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDUNLOCK": { + "direction": "OUT" + }, + "MIMRXWADDR10": { + "direction": "OUT" + }, + "CFGTRANSACTIONTYPE": { + "direction": "OUT" + }, + "PIPERX6DATA0": { + "direction": "IN" + }, + "TRNRDLLPDATA43": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER30": { + "direction": "IN" + }, + "CFGLINKCONTROLCLOCKPMEN": { + "direction": "OUT" + }, + "TRNRDLLPDATA56": { + "direction": "OUT" + }, + "CFGDEVID15": { + "direction": "IN" + }, + "PIPERX7DATA1": { + "direction": "IN" + }, + "CFGINTERRUPTMSIXENABLE": { + "direction": "OUT" + }, + "PIPERX2DATA15": { + "direction": "IN" + }, + "PIPERX4STATUS2": { + "direction": "IN" + }, + "MIMTXWDATA23": { + "direction": "OUT" + }, + "PIPERX1DATA0": { + "direction": "IN" + }, + "PIPERX0DATA2": { + "direction": "IN" + }, + "TRNRD2": { + "direction": "OUT" + }, + "MIMRXWDATA33": { + "direction": "OUT" + }, + "CFGDEVCONTROLNONFATALREPORTINGEN": { + "direction": "OUT" + }, + "TRNRDLLPDATA32": { + "direction": "OUT" + }, + "PIPETX7DATA0": { + "direction": "OUT" + }, + "CFGDEVID0": { + "direction": "IN" + }, + "MIMRXWADDR1": { + "direction": "OUT" + }, + "PIPERX5STATUS0": { + "direction": "IN" + }, + "PIPETX2DATA7": { + "direction": "OUT" + }, + "TRNFCPD2": { + "direction": "OUT" + }, + "CFGPMFORCESTATE1": { + "direction": "IN" + }, + "DBGVECB41": { + "direction": "OUT" + }, + "DBGVECA35": { + "direction": "OUT" + }, + "MIMRXWADDR2": { + "direction": "OUT" + }, + "PL2SUSPENDOK": { + "direction": "OUT" + }, + "DBGVECA3": { + "direction": "OUT" + }, + "DBGVECB17": { + "direction": "OUT" + }, + "DBGVECB31": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG10": { + "direction": "IN" + }, + "TRNFCNPH7": { + "direction": "OUT" + }, + "TRNTD10": { + "direction": "IN" + }, + "TL2ERRHDR8": { + "direction": "OUT" + }, + "MIMTXWADDR7": { + "direction": "OUT" + }, + "DBGSCLRC": { + "direction": "OUT" + }, + "EDTCHANNELSIN4": { + "direction": "IN" + }, + "TRNRD25": { + "direction": "OUT" + }, + "TRNFCPD3": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER3": { + "direction": "IN" + }, + "DBGVECB49": { + "direction": "OUT" + }, + "CFGVCTCVCMAP3": { + "direction": "OUT" + }, + "DRPADDR7": { + "direction": "IN" + }, + "MIMTXWDATA10": { + "direction": "OUT" + }, + "EDTCHANNELSOUT6": { + "direction": "OUT" + }, + "CFGMGMTDI11": { + "direction": "IN" + }, + "CFGMGMTDI28": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG6": { + "direction": "IN" + }, + "PIPERX3CHARISK1": { + "direction": "IN" + }, + "DBGVECC7": { + "direction": "OUT" + }, + "MIMRXWDATA30": { + "direction": "OUT" + }, + "TRNTD19": { + "direction": "IN" + }, + "CFGDSN34": { + "direction": "IN" + }, + "MIMRXWDATA47": { + "direction": "OUT" + }, + "TRNTD44": { + "direction": "IN" + }, + "TRNRD61": { + "direction": "OUT" + }, + "CFGSUBSYSVENDID12": { + "direction": "IN" + }, + "CFGDEVCONTROLEXTTAGEN": { + "direction": "OUT" + }, + "PIPERX4DATA2": { + "direction": "IN" + }, + "CFGMGMTDO17": { + "direction": "OUT" + }, + "DBGVECB37": { + "direction": "OUT" + }, + "PIPETX6DATA5": { + "direction": "OUT" + }, + "DBGVECB54": { + "direction": "OUT" + }, + "PIPERX4CHARISK1": { + "direction": "IN" + }, + "PIPETX4DATA4": { + "direction": "OUT" + }, + "PIPERX1DATA1": { + "direction": "IN" + }, + "CFGDSN40": { + "direction": "IN" + }, + "CFGROOTCONTROLSYSERRCORRERREN": { + "direction": "OUT" + }, + "TRNRD91": { + "direction": "OUT" + }, + "TRNTD33": { + "direction": "IN" + }, + "TRNTD17": { + "direction": "IN" + }, + "PLDBGVEC5": { + "direction": "OUT" + }, + "TRNRD11": { + "direction": "OUT" + }, + "MIMRXRADDR6": { + "direction": "OUT" + }, + "PIPERX1DATA9": { + "direction": "IN" + }, + "PIPETX3DATA3": { + "direction": "OUT" + }, + "CFGDEVCONTROLNOSNOOPEN": { + "direction": "OUT" + }, + "TRNFCPH5": { + "direction": "OUT" + }, + "XILUNCONNOUT22": { + "direction": "OUT" + }, + "MIMTXRDATA42": { + "direction": "IN" + }, + "CFGSUBSYSID3": { + "direction": "IN" + }, + "TL2ERRHDR11": { + "direction": "OUT" + }, + "PIPETX1DATA0": { + "direction": "OUT" + }, + "MIMTXRDATA61": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER45": { + "direction": "IN" + }, + "PIPERX5DATA8": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER13": { + "direction": "IN" + }, + "CFGPCIELINKSTATE1": { + "direction": "OUT" + }, + "MIMTXWADDR6": { + "direction": "OUT" + }, + "MIMRXRDATA50": { + "direction": "IN" + }, + "TRNFCPH7": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDPMETO": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG3": { + "direction": "IN" + }, + "MIMRXRDATA48": { + "direction": "IN" + }, + "TRNRNPREQ": { + "direction": "IN" + }, + "DBGVECB27": { + "direction": "OUT" + }, + "TRNTD35": { + "direction": "IN" + }, + "MIMTXRDATA53": { + "direction": "IN" + }, + "CFGMGMTRDENN": { + "direction": "IN" + }, + "MIMTXWDATA67": { + "direction": "OUT" + }, + "TRNRECRCERR": { + "direction": "OUT" + }, + "MIMRXRDATA57": { + "direction": "IN" + }, + "DBGVECB4": { + "direction": "OUT" + }, + "TRNTDLLPDATA14": { + "direction": "IN" + }, + "CFGDSDEVICENUMBER1": { + "direction": "IN" + }, + "TRNTCFGGNT": { + "direction": "IN" + }, + "DRPADDR1": { + "direction": "IN" + }, + "CFGAERINTERRUPTMSGNUM2": { + "direction": "IN" + }, + "TRNFCNPD0": { + "direction": "OUT" + }, + "PIPETX4DATA6": { + "direction": "OUT" + }, + "CFGDSN6": { + "direction": "IN" + }, + "CFGERRAERHEADERLOGSETN": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG89": { + "direction": "IN" + }, + "CFGDEVID10": { + "direction": "IN" + }, + "CFGSLOTCONTROLELECTROMECHILCTLPULSE": { + "direction": "OUT" + }, + "TRNTD78": { + "direction": "IN" + }, + "CFGDSN56": { + "direction": "IN" + }, + "CFGMGMTDO13": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG92": { + "direction": "IN" + }, + "CFGPMTURNOFFOKN": { + "direction": "IN" + }, + "CFGERRMALFORMEDN": { + "direction": "IN" + }, + "TL2ERRHDR55": { + "direction": "OUT" + }, + "CFGINTERRUPTMMENABLE0": { + "direction": "OUT" + }, + "TRNRDLLPDATA40": { + "direction": "OUT" + }, + "MIMRXRDATA14": { + "direction": "IN" + }, + "PIPERX6DATA7": { + "direction": "IN" + }, + "TRNTERRFWD": { + "direction": "IN" + }, + "PIPETX7POWERDOWN1": { + "direction": "OUT" + }, + "TRNTD40": { + "direction": "IN" + }, + "PIPETX0DATA12": { + "direction": "OUT" + }, + "TRNRBARHIT0": { + "direction": "OUT" + }, + "TRNFCPD1": { + "direction": "OUT" + }, + "DBGVECB32": { + "direction": "OUT" + }, + "MIMTXRADDR5": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG13": { + "direction": "IN" + }, + "PIPERX4CHARISK0": { + "direction": "IN" + }, + "DBGVECA32": { + "direction": "OUT" + }, + "DRPDI12": { + "direction": "IN" + }, + "PMVSELECT1": { + "direction": "IN" + }, + "CFGDSN9": { + "direction": "IN" + }, + "CFGLINKCONTROLRCB": { + "direction": "OUT" + }, + "DBGVECB21": { + "direction": "OUT" + }, + "TRNRD27": { + "direction": "OUT" + }, + "PIPETX7CHARISK0": { + "direction": "OUT" + }, + "TRNTDLLPDATA9": { + "direction": "IN" + }, + "PIPERX5DATA10": { + "direction": "IN" + }, + "PIPERX5DATA9": { + "direction": "IN" + }, + "TRNRDLLPDATA51": { + "direction": "OUT" + }, + "TL2ERRHDR45": { + "direction": "OUT" + }, + "TL2ERRHDR38": { + "direction": "OUT" + }, + "MIMRXRDATA32": { + "direction": "IN" + }, + "TL2ERRHDR50": { + "direction": "OUT" + }, + "CFGMGMTWRENN": { + "direction": "IN" + }, + "EDTCHANNELSOUT4": { + "direction": "OUT" + }, + "EDTCHANNELSOUT1": { + "direction": "OUT" + }, + "TRNRD96": { + "direction": "OUT" + }, + "PL2RECEIVERERR": { + "direction": "OUT" + }, + "MIMRXRADDR5": { + "direction": "OUT" + }, + "CFGDSBUSNUMBER6": { + "direction": "IN" + }, + "CFGPMRCVENTERL1N": { + "direction": "OUT" + }, + "CFGMGMTDWADDR8": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG7": { + "direction": "IN" + }, + "CFGSUBSYSVENDID7": { + "direction": "IN" + }, + "TRNRD87": { + "direction": "OUT" + }, + "TRNRDLLPDATA14": { + "direction": "OUT" + }, + "TRNRDLLPDATA7": { + "direction": "OUT" + }, + "MIMRXRADDR1": { + "direction": "OUT" + }, + "TL2ERRHDR20": { + "direction": "OUT" + }, + "CFGSUBSYSID5": { + "direction": "IN" + }, + "CFGSUBSYSID14": { + "direction": "IN" + }, + "PIPETX2DATA12": { + "direction": "OUT" + }, + "CFGDSN10": { + "direction": "IN" + }, + "CFGMGMTDI17": { + "direction": "IN" + }, + "DBGVECB5": { + "direction": "OUT" + }, + "CFGINTERRUPTDO2": { + "direction": "OUT" + }, + "TRNRD103": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDSETSLOTPOWERLIMIT": { + "direction": "OUT" + }, + "PIPETX6POWERDOWN1": { + "direction": "OUT" + }, + "LL2TFCINIT2SEQ": { + "direction": "OUT" + }, + "MIMRXRADDR7": { + "direction": "OUT" + }, + "LL2PROTOCOLERR": { + "direction": "OUT" + }, + "CFGAERINTERRUPTMSGNUM3": { + "direction": "IN" + }, + "CFGDEVCONTROL2ATOMICEGRESSBLOCK": { + "direction": "OUT" + }, + "PIPERX6DATA8": { + "direction": "IN" + }, + "TRNRD35": { + "direction": "OUT" + }, + "TL2ERRHDR52": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG5": { + "direction": "IN" + }, + "MIMRXRDATA23": { + "direction": "IN" + }, + "MIMRXRDATA17": { + "direction": "IN" + }, + "TRNTDLLPDATA26": { + "direction": "IN" + }, + "PIPERX7POLARITY": { + "direction": "OUT" + }, + "PIPERX3ELECIDLE": { + "direction": "IN" + }, + "LL2RECEIVERERR": { + "direction": "OUT" + }, + "PIPERX1DATA11": { + "direction": "IN" + }, + "TRNRDLLPDATA24": { + "direction": "OUT" + }, + "TRNTDLLPDATA27": { + "direction": "IN" + }, + "PIPETX4DATA13": { + "direction": "OUT" + }, + "PLDIRECTEDLINKSPEED": { + "direction": "IN" + }, + "CFGDEVID8": { + "direction": "IN" + }, + "CFGDEVID2": { + "direction": "IN" + }, + "CFGDSN58": { + "direction": "IN" + }, + "TRNTD24": { + "direction": "IN" + }, + "PL2L0REQ": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG107": { + "direction": "IN" + }, + "CFGDEVSTATUSCORRERRDETECTED": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER5": { + "direction": "IN" + }, + "PIPERX3DATA11": { + "direction": "IN" + }, + "MIMTXWDATA38": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDPMETOACK": { + "direction": "OUT" + }, + "TRNTD48": { + "direction": "IN" + }, + "PIPERX1CHANISALIGNED": { + "direction": "IN" + }, + "MIMTXRADDR3": { + "direction": "OUT" + }, + "DBGVECB13": { + "direction": "OUT" + }, + "PIPERX4STATUS0": { + "direction": "IN" + }, + "DRPDO11": { + "direction": "OUT" + }, + "MIMRXRDATA58": { + "direction": "IN" + }, + "PLPHYLNKUPN": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER11": { + "direction": "IN" + }, + "DRPADDR2": { + "direction": "IN" + }, + "CFGMSGDATA4": { + "direction": "OUT" + }, + "TRNRD18": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG61": { + "direction": "IN" + }, + "CFGDEVID13": { + "direction": "IN" + }, + "CFGDSN54": { + "direction": "IN" + }, + "DRPDI5": { + "direction": "IN" + }, + "MIMTXWDATA68": { + "direction": "OUT" + }, + "TRNRD121": { + "direction": "OUT" + }, + "CFGERRPOISONEDN": { + "direction": "IN" + }, + "PIPERX2DATA8": { + "direction": "IN" + }, + "DBGVECB20": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER19": { + "direction": "IN" + }, + "TL2ERRHDR25": { + "direction": "OUT" + }, + "CFGTRNPENDINGN": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG30": { + "direction": "IN" + }, + "CFGDSN61": { + "direction": "IN" + }, + "DBGSCLRE": { + "direction": "OUT" + }, + "MIMRXRDATA20": { + "direction": "IN" + }, + "PIPERX7DATA15": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG108": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG22": { + "direction": "IN" + }, + "PLDBGVEC4": { + "direction": "OUT" + }, + "CFGINTERRUPTDO5": { + "direction": "OUT" + }, + "CFGMGMTDWADDR9": { + "direction": "IN" + }, + "CFGSUBSYSVENDID9": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG90": { + "direction": "IN" + }, + "TRNRD26": { + "direction": "OUT" + }, + "PIPERX0DATA5": { + "direction": "IN" + }, + "CFGMGMTDI6": { + "direction": "IN" + }, + "TRNTD114": { + "direction": "IN" + }, + "PIPETX6DATA0": { + "direction": "OUT" + }, + "PIPETX7DATA3": { + "direction": "OUT" + }, + "MIMRXRDATA61": { + "direction": "IN" + }, + "TRNTD38": { + "direction": "IN" + }, + "TRNTDLLPDATA15": { + "direction": "IN" + }, + "TRNTD117": { + "direction": "IN" + }, + "TRNRBARHIT3": { + "direction": "OUT" + }, + "TL2ERRHDR42": { + "direction": "OUT" + }, + "TRNRD57": { + "direction": "OUT" + }, + "PIPETX4CHARISK1": { + "direction": "OUT" + }, + "CFGDEVCONTROLCORRERRREPORTINGEN": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG75": { + "direction": "IN" + }, + "CFGSUBSYSID13": { + "direction": "IN" + }, + "MIMRXWDATA34": { + "direction": "OUT" + }, + "MIMTXWDATA18": { + "direction": "OUT" + }, + "PIPETX7DATA12": { + "direction": "OUT" + }, + "MIMRXWDATA53": { + "direction": "OUT" + }, + "CFGDSBUSNUMBER2": { + "direction": "IN" + }, + "TRNRREM1": { + "direction": "OUT" + }, + "MIMRXRDATA39": { + "direction": "IN" + }, + "LL2LINKSTATUS1": { + "direction": "OUT" + }, + "PIPETX6DATA2": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG56": { + "direction": "IN" + }, + "MIMRXWADDR3": { + "direction": "OUT" + }, + "TRNTD92": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG62": { + "direction": "IN" + }, + "EDTCHANNELSIN2": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG20": { + "direction": "IN" + }, + "TRNTD103": { + "direction": "IN" + }, + "PIPERX4CHANISALIGNED": { + "direction": "IN" + }, + "CFGMSGRECEIVEDASSERTINTC": { + "direction": "OUT" + }, + "CFGMSGDATA10": { + "direction": "OUT" + }, + "TL2ERRHDR13": { + "direction": "OUT" + }, + "CFGMGMTDI7": { + "direction": "IN" + }, + "PLDBGVEC1": { + "direction": "OUT" + }, + "TRNRDLLPDATA37": { + "direction": "OUT" + }, + "CFGDSFUNCTIONNUMBER0": { + "direction": "IN" + }, + "MIMRXWDATA5": { + "direction": "OUT" + }, + "MIMRXWDATA24": { + "direction": "OUT" + }, + "DRPDO6": { + "direction": "OUT" + }, + "TRNTD86": { + "direction": "IN" + }, + "PIPERX4DATA5": { + "direction": "IN" + }, + "CFGMGMTDO4": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG0": { + "direction": "IN" + }, + "MIMTXWDATA24": { + "direction": "OUT" + }, + "FUNCLVLRSTN": { + "direction": "IN" + }, + "TRNTD50": { + "direction": "IN" + }, + "TRNFCSEL0": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG1": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG103": { + "direction": "IN" + }, + "MIMTXRDATA41": { + "direction": "IN" + }, + "PIPERX3DATA3": { + "direction": "IN" + }, + "MIMTXRDATA31": { + "direction": "IN" + }, + "TL2ERRHDR39": { + "direction": "OUT" + }, + "CFGMGMTDO29": { + "direction": "OUT" + }, + "CFGDSN29": { + "direction": "IN" + }, + "TRNRREM0": { + "direction": "OUT" + }, + "CFGREVID3": { + "direction": "IN" + }, + "DBGVECC4": { + "direction": "OUT" + }, + "TRNRDLLPSRCRDY1": { + "direction": "OUT" + }, + "DBGVECB52": { + "direction": "OUT" + }, + "MIMTXWDATA30": { + "direction": "OUT" + }, + "MIMTXRDATA68": { + "direction": "IN" + }, + "DBGSUBMODE": { + "direction": "IN" + }, + "TRNRDLLPDATA62": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDDEASSERTINTA": { + "direction": "OUT" + }, + "TL2ERRHDR3": { + "direction": "OUT" + }, + "TRNTD54": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG81": { + "direction": "IN" + }, + "TRNTD101": { + "direction": "IN" + }, + "CFGDSN15": { + "direction": "IN" + }, + "CFGDEVCONTROL2TLPPREFIXBLOCK": { + "direction": "OUT" + }, + "PIPETX7CHARISK1": { + "direction": "OUT" + }, + "DBGVECA58": { + "direction": "OUT" + }, + "PIPETX4DATA12": { + "direction": "OUT" + }, + "DBGVECB30": { + "direction": "OUT" + }, + "PIPERX2PHYSTATUS": { + "direction": "IN" + }, + "TRNFCCPLH7": { + "direction": "OUT" + }, + "TRNRD50": { + "direction": "OUT" + }, + "TRNRD82": { + "direction": "OUT" + }, + "PIPETX0DATA10": { + "direction": "OUT" + }, + "TRNFCCPLH1": { + "direction": "OUT" + }, + "MIMTXWEN": { + "direction": "OUT" + }, + "LL2SENDENTERL23": { + "direction": "IN" + }, + "TRNTDLLPDATA8": { + "direction": "IN" + }, + "TRNTD89": { + "direction": "IN" + }, + "CFGMGMTDO9": { + "direction": "OUT" + }, + "EDTCHANNELSOUT2": { + "direction": "OUT" + }, + "MIMTXRDATA25": { + "direction": "IN" + }, + "MIMRXWDATA2": { + "direction": "OUT" + }, + "CFGDEVID5": { + "direction": "IN" + }, + "MIMTXWADDR4": { + "direction": "OUT" + }, + "PMVSELECT2": { + "direction": "IN" + }, + "MIMRXWADDR0": { + "direction": "OUT" + }, + "TRNFCPH1": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDERRFATAL": { + "direction": "OUT" + }, + "CFGDSN19": { + "direction": "IN" + }, + "CFGDEVCONTROLMAXPAYLOAD2": { + "direction": "OUT" + }, + "PIPERX6DATA14": { + "direction": "IN" + }, + "EDTCHANNELSOUT5": { + "direction": "OUT" + }, + "TRNRD33": { + "direction": "OUT" + }, + "CFGERRCPLTIMEOUTN": { + "direction": "IN" + }, + "PIPETX5CHARISK0": { + "direction": "OUT" + }, + "TRNRDLLPDATA13": { + "direction": "OUT" + }, + "TRNRD17": { + "direction": "OUT" + }, + "TL2ERRHDR9": { + "direction": "OUT" + }, + "CFGMGMTDI14": { + "direction": "IN" + }, + "CFGMSGDATA5": { + "direction": "OUT" + }, + "PIPERX5STATUS1": { + "direction": "IN" + }, + "PIPERX0DATA15": { + "direction": "IN" + }, + "CFGSUBSYSID9": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG45": { + "direction": "IN" + }, + "SYSRSTN": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER1": { + "direction": "IN" + }, + "CFGLINKCONTROLLINKDISABLE": { + "direction": "OUT" + }, + "DBGVECA36": { + "direction": "OUT" + }, + "PIPERX1DATA14": { + "direction": "IN" + }, + "CFGMGMTDO30": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER38": { + "direction": "IN" + }, + "TRNRD71": { + "direction": "OUT" + }, + "TL2ERRHDR40": { + "direction": "OUT" + }, + "TRNRD20": { + "direction": "OUT" + }, + "MIMTXRADDR6": { + "direction": "OUT" + }, + "TRNRD29": { + "direction": "OUT" + }, + "MIMRXWADDR6": { + "direction": "OUT" + }, + "MIMRXWADDR4": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG80": { + "direction": "IN" + }, + "CFGDSN42": { + "direction": "IN" + }, + "PLDBGVEC11": { + "direction": "OUT" + }, + "TRNFCCPLH5": { + "direction": "OUT" + }, + "PLLANEREVERSALMODE1": { + "direction": "OUT" + }, + "MIMRXRDATA62": { + "direction": "IN" + }, + "CFGDEVCONTROLMAXPAYLOAD0": { + "direction": "OUT" + }, + "CFGDSN35": { + "direction": "IN" + }, + "TRNTD66": { + "direction": "IN" + }, + "TL2ERRHDR30": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG111": { + "direction": "IN" + }, + "PIPETX5DATA2": { + "direction": "OUT" + }, + "CFGDSFUNCTIONNUMBER2": { + "direction": "IN" + }, + "PIPERX4ELECIDLE": { + "direction": "IN" + }, + "CFGDEVCONTROL2LTREN": { + "direction": "OUT" + }, + "XILUNCONNOUT24": { + "direction": "OUT" + }, + "MIMTXWDATA15": { + "direction": "OUT" + }, + "TRNFCNPD11": { + "direction": "OUT" + }, + "TRNTD125": { + "direction": "IN" + }, + "TL2ERRHDR32": { + "direction": "OUT" + }, + "PIPERX4DATA6": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG93": { + "direction": "IN" + }, + "PIPETXMARGIN2": { + "direction": "OUT" + }, + "PIPERX7DATA4": { + "direction": "IN" + }, + "MIMTXWDATA21": { + "direction": "OUT" + }, + "DRPDO4": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG19": { + "direction": "IN" + }, + "TL2ERRHDR1": { + "direction": "OUT" + }, + "MIMRXRDATA47": { + "direction": "IN" + }, + "TRNRD41": { + "direction": "OUT" + }, + "PIPETX3COMPLIANCE": { + "direction": "OUT" + }, + "CFGINTERRUPTMSIENABLE": { + "direction": "OUT" + }, + "CFGMGMTDO7": { + "direction": "OUT" + }, + "TRNRD56": { + "direction": "OUT" + }, + "TRNRD97": { + "direction": "OUT" + }, + "PIPETX1DATA5": { + "direction": "OUT" + }, + "DBGVECB40": { + "direction": "OUT" + }, + "PIPETX0DATA15": { + "direction": "OUT" + }, + "TL2PPMSUSPENDOK": { + "direction": "OUT" + }, + "PIPETX7DATA5": { + "direction": "OUT" + }, + "PIPERX4DATA9": { + "direction": "IN" + }, + "PIPERX1DATA8": { + "direction": "IN" + }, + "PIPETX6CHARISK0": { + "direction": "OUT" + }, + "MIMTXWDATA39": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER29": { + "direction": "IN" + }, + "TRNTDLLPDATA4": { + "direction": "IN" + }, + "DRPDI8": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER17": { + "direction": "IN" + }, + "PIPETX4POWERDOWN1": { + "direction": "OUT" + }, + "CFGMSGDATA8": { + "direction": "OUT" + }, + "DRPADDR5": { + "direction": "IN" + }, + "TRNTD71": { + "direction": "IN" + }, + "TRNRD63": { + "direction": "OUT" + }, + "MIMRXRDATA24": { + "direction": "IN" + }, + "PLTXPMSTATE1": { + "direction": "OUT" + }, + "MIMRXWDATA22": { + "direction": "OUT" + }, + "XILUNCONNOUT35": { + "direction": "OUT" + }, + "PIPERX2CHARISK0": { + "direction": "IN" + }, + "CFGLINKSTATUSCURRENTSPEED0": { + "direction": "OUT" + }, + "CFGPMCSRPOWERSTATE1": { + "direction": "OUT" + }, + "MIMRXRDATA6": { + "direction": "IN" + }, + "MIMRXWDATA12": { + "direction": "OUT" + }, + "EDTCHANNELSIN1": { + "direction": "IN" + }, + "TRNRDLLPDATA17": { + "direction": "OUT" + }, + "CFGDEVCONTROL2ARIFORWARDEN": { + "direction": "OUT" + }, + "TRNTD68": { + "direction": "IN" + }, + "CFGMSGDATA15": { + "direction": "OUT" + }, + "USERCLK2": { + "direction": "IN" + }, + "MIMRXWDATA13": { + "direction": "OUT" + }, + "CFGREVID5": { + "direction": "IN" + }, + "TRNTD16": { + "direction": "IN" + }, + "MIMRXRDATA2": { + "direction": "IN" + }, + "PIPERX3CHANISALIGNED": { + "direction": "IN" + }, + "TRNTSOF": { + "direction": "IN" + }, + "PIPERX0POLARITY": { + "direction": "OUT" + }, + "TRNTDLLPDATA31": { + "direction": "IN" + }, + "DRPWE": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG116": { + "direction": "IN" + }, + "TRNRD48": { + "direction": "OUT" + }, + "DBGVECA11": { + "direction": "OUT" + }, + "PL2DIRECTEDLSTATE2": { + "direction": "IN" + }, + "MIMTXRADDR11": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER4": { + "direction": "IN" + }, + "LL2LINKSTATUS4": { + "direction": "OUT" + }, + "TRNRD47": { + "direction": "OUT" + }, + "CFGDSN57": { + "direction": "IN" + }, + "MIMRXRDATA55": { + "direction": "IN" + }, + "MIMRXRDATA11": { + "direction": "IN" + }, + "CFGDSN33": { + "direction": "IN" + }, + "CFGPMHALTASPML0SN": { + "direction": "IN" + }, + "TRNTD98": { + "direction": "IN" + }, + "CFGSUBSYSVENDID2": { + "direction": "IN" + }, + "TRNTD6": { + "direction": "IN" + }, + "TRNTD74": { + "direction": "IN" + }, + "DBGVECB58": { + "direction": "OUT" + }, + "LL2LINKSTATUS2": { + "direction": "OUT" + }, + "DBGVECA20": { + "direction": "OUT" + }, + "CFGDSBUSNUMBER4": { + "direction": "IN" + }, + "PIPERX2CHARISK1": { + "direction": "IN" + }, + "DBGVECB35": { + "direction": "OUT" + }, + "TRNRD100": { + "direction": "OUT" + }, + "TL2ERRHDR59": { + "direction": "OUT" + }, + "MIMRXRDATA9": { + "direction": "IN" + }, + "TRNTD14": { + "direction": "IN" + }, + "CFGDEVID3": { + "direction": "IN" + }, + "CFGMGMTDO0": { + "direction": "OUT" + }, + "CFGMGMTDWADDR2": { + "direction": "IN" + }, + "CFGDEVCONTROL2CPLTIMEOUTDIS": { + "direction": "OUT" + }, + "LL2SENDENTERL1": { + "direction": "IN" + }, + "TL2ERRHDR14": { + "direction": "OUT" + }, + "TRNTBUFAV5": { + "direction": "OUT" + }, + "TRNRD24": { + "direction": "OUT" + }, + "PIPETX4DATA14": { + "direction": "OUT" + }, + "CFGMGMTDO14": { + "direction": "OUT" + }, + "PIPETX5DATA15": { + "direction": "OUT" + }, + "TRNTSRCDSC": { + "direction": "IN" + }, + "CFGMGMTBYTEENN0": { + "direction": "IN" + }, + "PIPERX3POLARITY": { + "direction": "OUT" + }, + "DBGVECA5": { + "direction": "OUT" + }, + "PIPERX0DATA13": { + "direction": "IN" + }, + "PIPETX1DATA14": { + "direction": "OUT" + }, + "PIPERX1POLARITY": { + "direction": "OUT" + }, + "TL2ERRHDR19": { + "direction": "OUT" + }, + "TRNRDLLPDATA60": { + "direction": "OUT" + }, + "PIPETX1ELECIDLE": { + "direction": "OUT" + }, + "CFGINTERRUPTRDYN": { + "direction": "OUT" + }, + "PLINITIALLINKWIDTH2": { + "direction": "OUT" + }, + "PIPERX5DATA6": { + "direction": "IN" + }, + "MIMTXWDATA0": { + "direction": "OUT" + }, + "DRPADDR0": { + "direction": "IN" + }, + "CFGINTERRUPTSTATN": { + "direction": "IN" + }, + "PIPERX2DATA3": { + "direction": "IN" + }, + "CFGLINKCONTROLCOMMONCLOCK": { + "direction": "OUT" + }, + "TRNRD99": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG125": { + "direction": "IN" + }, + "CFGMGMTDI13": { + "direction": "IN" + }, + "TRNTD25": { + "direction": "IN" + }, + "CFGERRMCBLOCKEDN": { + "direction": "IN" + }, + "PIPERX7PHYSTATUS": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG63": { + "direction": "IN" + }, + "CFGDSN0": { + "direction": "IN" + }, + "CFGPMCSRPMEEN": { + "direction": "OUT" + }, + "MIMTXRDATA19": { + "direction": "IN" + }, + "PIPETX1POWERDOWN0": { + "direction": "OUT" + }, + "PIPERX1STATUS2": { + "direction": "IN" + }, + "CFGERRCPLUNEXPECTN": { + "direction": "IN" + }, + "XILUNCONNOUT7": { + "direction": "OUT" + }, + "TRNTDLLPDATA13": { + "direction": "IN" + }, + "DBGVECA19": { + "direction": "OUT" + }, + "CFGMGMTDWADDR7": { + "direction": "IN" + }, + "TRNFCCPLH2": { + "direction": "OUT" + }, + "MIMTXRDATA32": { + "direction": "IN" + }, + "TL2ERRHDR56": { + "direction": "OUT" + }, + "PIPETX2DATA13": { + "direction": "OUT" + }, + "RECEIVEDFUNCLVLRSTN": { + "direction": "OUT" + }, + "CFGDSN32": { + "direction": "IN" + }, + "PIPETX6DATA15": { + "direction": "OUT" + }, + "PIPETX2DATA9": { + "direction": "OUT" + }, + "TRNTD83": { + "direction": "IN" + }, + "DBGVECB53": { + "direction": "OUT" + }, + "MIMTXRDATA51": { + "direction": "IN" + }, + "PLLTSSMSTATE4": { + "direction": "OUT" + }, + "CFGVENDID13": { + "direction": "IN" + }, + "PLTRANSMITHOTRST": { + "direction": "IN" + }, + "CFGDSN5": { + "direction": "IN" + }, + "TL2ASPMSUSPENDCREDITCHECK": { + "direction": "IN" + }, + "PIPERX2DATA1": { + "direction": "IN" + }, + "CFGMSGRECEIVEDASSERTINTB": { + "direction": "OUT" + }, + "TRNRD92": { + "direction": "OUT" + }, + "DRPEN": { + "direction": "IN" + }, + "PLDIRECTEDLTSSMNEW1": { + "direction": "IN" + }, + "USERCLK": { + "direction": "IN" + }, + "PLDIRECTEDLINKWIDTH0": { + "direction": "IN" + }, + "PLDBGMODE1": { + "direction": "IN" + }, + "CFGTRANSACTIONADDR5": { + "direction": "OUT" + }, + "DBGVECA14": { + "direction": "OUT" + }, + "CFGDSN28": { + "direction": "IN" + }, + "TRNTDSTRDY1": { + "direction": "OUT" + }, + "TRNRDLLPDATA10": { + "direction": "OUT" + }, + "TRNRD6": { + "direction": "OUT" + }, + "PIPERX5DATA15": { + "direction": "IN" + }, + "CFGDSBUSNUMBER0": { + "direction": "IN" + }, + "TRNRDLLPDATA49": { + "direction": "OUT" + }, + "MIMRXRDATA10": { + "direction": "IN" + }, + "DBGVECB12": { + "direction": "OUT" + }, + "CFGDSN41": { + "direction": "IN" + }, + "TL2ERRHDR34": { + "direction": "OUT" + }, + "TRNFCPD9": { + "direction": "OUT" + }, + "DBGVECB33": { + "direction": "OUT" + }, + "TLRSTN": { + "direction": "IN" + }, + "DBGVECB0": { + "direction": "OUT" + }, + "TRNRBARHIT6": { + "direction": "OUT" + }, + "TL2ERRHDR36": { + "direction": "OUT" + }, + "DBGVECB60": { + "direction": "OUT" + }, + "MIMTXWDATA33": { + "direction": "OUT" + }, + "DBGVECA41": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG58": { + "direction": "IN" + }, + "CFGDEVSTATUSURDETECTED": { + "direction": "OUT" + }, + "TRNTDLLPDATA24": { + "direction": "IN" + }, + "TL2ERRHDR22": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER12": { + "direction": "IN" + }, + "CFGINTERRUPTDI4": { + "direction": "IN" + }, + "MIMTXWDATA25": { + "direction": "OUT" + }, + "CFGMGMTWRRW1CASRWN": { + "direction": "IN" + }, + "TRNFCPD6": { + "direction": "OUT" + }, + "CFGSUBSYSID10": { + "direction": "IN" + }, + "LNKCLKEN": { + "direction": "OUT" + }, + "PIPETX5DATA10": { + "direction": "OUT" + }, + "TRNFCNPD3": { + "direction": "OUT" + }, + "DBGVECA34": { + "direction": "OUT" + }, + "MIMTXRDATA43": { + "direction": "IN" + }, + "TRNRDLLPDATA58": { + "direction": "OUT" + }, + "TRNTD61": { + "direction": "IN" + }, + "TRNTD111": { + "direction": "IN" + }, + "TRNFCCPLD9": { + "direction": "OUT" + }, + "TRNRD37": { + "direction": "OUT" + }, + "CFGINTERRUPTMMENABLE1": { + "direction": "OUT" + }, + "PIPETX0POWERDOWN0": { + "direction": "OUT" + }, + "TRNRD77": { + "direction": "OUT" + }, + "CFGDSN53": { + "direction": "IN" + }, + "PIPERX4POLARITY": { + "direction": "OUT" + }, + "PIPERX3DATA14": { + "direction": "IN" + }, + "CFGPORTNUMBER4": { + "direction": "IN" + }, + "PIPETXMARGIN0": { + "direction": "OUT" + }, + "XILUNCONNOUT33": { + "direction": "OUT" + }, + "PIPERX1DATA15": { + "direction": "IN" + }, + "TRNTD94": { + "direction": "IN" + }, + "PIPERX0DATA7": { + "direction": "IN" + }, + "CFGVCTCVCMAP5": { + "direction": "OUT" + }, + "DBGVECC6": { + "direction": "OUT" + }, + "MIMTXRDATA65": { + "direction": "IN" + }, + "XILUNCONNOUT28": { + "direction": "OUT" + }, + "CFGAERINTERRUPTMSGNUM0": { + "direction": "IN" + }, + "CFGDEVCONTROLMAXREADREQ1": { + "direction": "OUT" + }, + "TRNRD40": { + "direction": "OUT" + }, + "TRNRD89": { + "direction": "OUT" + }, + "TRNRDLLPDATA18": { + "direction": "OUT" + }, + "MIMTXRDATA58": { + "direction": "IN" + }, + "PIPERX2DATA0": { + "direction": "IN" + }, + "TRNTERRDROP": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER46": { + "direction": "IN" + }, + "PIPETXDEEMPH": { + "direction": "OUT" + }, + "CFGSUBSYSID1": { + "direction": "IN" + }, + "TRNTD106": { + "direction": "IN" + }, + "CFGFORCEEXTENDEDSYNCON": { + "direction": "IN" + }, + "MIMRXWDATA28": { + "direction": "OUT" + }, + "MIMTXRDATA8": { + "direction": "IN" + }, + "PIPERX2POLARITY": { + "direction": "OUT" + }, + "PIPETX3CHARISK1": { + "direction": "OUT" + }, + "TRNRSRCDSC": { + "direction": "OUT" + }, + "MIMTXWDATA13": { + "direction": "OUT" + }, + "LL2TLPRCV": { + "direction": "IN" + }, + "MIMTXRDATA10": { + "direction": "IN" + }, + "CFGDSN2": { + "direction": "IN" + }, + "PIPETX5DATA9": { + "direction": "OUT" + }, + "DBGVECA50": { + "direction": "OUT" + }, + "DBGVECA28": { + "direction": "OUT" + }, + "PIPETX2DATA6": { + "direction": "OUT" + }, + "TRNRD19": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER37": { + "direction": "IN" + }, + "PIPERX4DATA14": { + "direction": "IN" + }, + "MIMTXRDATA52": { + "direction": "IN" + }, + "TRNRD14": { + "direction": "OUT" + }, + "PIPERX6DATA15": { + "direction": "IN" + }, + "TRNTD58": { + "direction": "IN" + }, + "TRNTD13": { + "direction": "IN" + }, + "TRNRD23": { + "direction": "OUT" + }, + "CFGROOTCONTROLSYSERRFATALERREN": { + "direction": "OUT" + }, + "MIMTXRDATA50": { + "direction": "IN" + }, + "EDTCHANNELSIN3": { + "direction": "IN" + }, + "CFGMGMTDI16": { + "direction": "IN" + }, + "TL2ASPMSUSPENDCREDITCHECKOK": { + "direction": "OUT" + }, + "CFGERRINTERNALUNCORN": { + "direction": "IN" + }, + "TRNRDLLPDATA36": { + "direction": "OUT" + }, + "MIMTXRDATA54": { + "direction": "IN" + }, + "TRNRDLLPDATA11": { + "direction": "OUT" + }, + "CFGLINKCONTROLHWAUTOWIDTHDIS": { + "direction": "OUT" + }, + "PIPERX0DATA8": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER41": { + "direction": "IN" + }, + "TRNTD3": { + "direction": "IN" + }, + "TRNFCCPLD8": { + "direction": "OUT" + }, + "CFGMGMTDO1": { + "direction": "OUT" + }, + "PIPETX3DATA15": { + "direction": "OUT" + }, + "TRNTD72": { + "direction": "IN" + }, + "PLLTSSMSTATE5": { + "direction": "OUT" + }, + "TRNTD56": { + "direction": "IN" + }, + "PIPERX1DATA3": { + "direction": "IN" + }, + "PIPERX7DATA13": { + "direction": "IN" + }, + "MIMTXRDATA39": { + "direction": "IN" + }, + "TRNTDLLPDATA2": { + "direction": "IN" + }, + "PLSELLNKWIDTH0": { + "direction": "OUT" + }, + "PIPERX6DATA3": { + "direction": "IN" + }, + "PIPERX0VALID": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG28": { + "direction": "IN" + }, + "MIMRXRADDR4": { + "direction": "OUT" + }, + "TL2ERRHDR28": { + "direction": "OUT" + }, + "DBGMODE0": { + "direction": "IN" + }, + "MIMTXWDATA20": { + "direction": "OUT" + }, + "DBGVECB55": { + "direction": "OUT" + }, + "TRNTDLLPDATA30": { + "direction": "IN" + }, + "PIPERX6DATA11": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG47": { + "direction": "IN" + }, + "TRNTD62": { + "direction": "IN" + }, + "DBGVECB50": { + "direction": "OUT" + }, + "DBGVECB8": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDPMASNAK": { + "direction": "OUT" + }, + "TRNRBARHIT2": { + "direction": "OUT" + }, + "TRNTD52": { + "direction": "IN" + }, + "TL2ERRHDR57": { + "direction": "OUT" + }, + "DRPDO7": { + "direction": "OUT" + }, + "TRNRD73": { + "direction": "OUT" + }, + "CFGPMRCVENTERL23N": { + "direction": "OUT" + }, + "TL2ERRHDR48": { + "direction": "OUT" + }, + "TRNRDLLPDATA20": { + "direction": "OUT" + }, + "CFGPMHALTASPML1N": { + "direction": "IN" + }, + "TRNRD108": { + "direction": "OUT" + }, + "CFGMGMTDO28": { + "direction": "OUT" + }, + "TRNFCCPLD0": { + "direction": "OUT" + }, + "CFGDSN13": { + "direction": "IN" + }, + "CFGDSN30": { + "direction": "IN" + }, + "MIMRXRDATA63": { + "direction": "IN" + }, + "DRPDI14": { + "direction": "IN" + }, + "DBGVECB38": { + "direction": "OUT" + }, + "PIPERX6DATA13": { + "direction": "IN" + }, + "TRNRD54": { + "direction": "OUT" + }, + "TRNTD96": { + "direction": "IN" + }, + "PIPERX6DATA9": { + "direction": "IN" + }, + "TRNTD53": { + "direction": "IN" + }, + "MIMRXWDATA27": { + "direction": "OUT" + }, + "CFGAERINTERRUPTMSGNUM4": { + "direction": "IN" + }, + "CFGVCTCVCMAP0": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG109": { + "direction": "IN" + }, + "TL2ERRHDR2": { + "direction": "OUT" + }, + "MIMTXWADDR10": { + "direction": "OUT" + }, + "CFGINTERRUPTMSIXFM": { + "direction": "OUT" + }, + "XILUNCONNOUT15": { + "direction": "OUT" + }, + "MIMTXWDATA60": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER24": { + "direction": "IN" + }, + "CFGMGMTDI15": { + "direction": "IN" + }, + "MIMRXRDATA37": { + "direction": "IN" + }, + "PIPERX5DATA1": { + "direction": "IN" + }, + "TRNRD69": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG105": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG46": { + "direction": "IN" + }, + "MIMRXWADDR8": { + "direction": "OUT" + }, + "MIMTXWDATA53": { + "direction": "OUT" + }, + "MIMTXRDATA67": { + "direction": "IN" + }, + "DBGVECB25": { + "direction": "OUT" + }, + "MIMRXRDATA60": { + "direction": "IN" + }, + "PIPERX7DATA5": { + "direction": "IN" + }, + "PIPERX0STATUS2": { + "direction": "IN" + }, + "MIMTXRDATA56": { + "direction": "IN" + }, + "PIPETX5DATA11": { + "direction": "OUT" + }, + "CFGPMFORCESTATE0": { + "direction": "IN" + }, + "PIPERX5STATUS2": { + "direction": "IN" + }, + "TRNTD23": { + "direction": "IN" + }, + "TRNRDLLPDATA46": { + "direction": "OUT" + }, + "MIMRXWDATA49": { + "direction": "OUT" + }, + "MIMRXWDATA64": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG79": { + "direction": "IN" + }, + "TRNFCNPD5": { + "direction": "OUT" + }, + "TL2ERRHDR49": { + "direction": "OUT" + }, + "MIMTXWDATA17": { + "direction": "OUT" + }, + "TRNRDLLPDATA53": { + "direction": "OUT" + }, + "TRNRDLLPDATA3": { + "direction": "OUT" + }, + "TRNRDLLPDATA57": { + "direction": "OUT" + }, + "CFGDSN18": { + "direction": "IN" + }, + "PIPERX1DATA10": { + "direction": "IN" + }, + "PIPETX5DATA1": { + "direction": "OUT" + }, + "CFGREVID0": { + "direction": "IN" + }, + "CFGPORTNUMBER2": { + "direction": "IN" + }, + "PIPETX7DATA13": { + "direction": "OUT" + }, + "MIMRXRDATA38": { + "direction": "IN" + }, + "CFGPMWAKEN": { + "direction": "IN" + }, + "MIMTXRDATA29": { + "direction": "IN" + }, + "PIPETX4CHARISK0": { + "direction": "OUT" + }, + "TRNFCNPH0": { + "direction": "OUT" + }, + "MIMRXRADDR8": { + "direction": "OUT" + }, + "CFGVCTCVCMAP4": { + "direction": "OUT" + }, + "CFGDEVSTATUSNONFATALERRDETECTED": { + "direction": "OUT" + }, + "CFGINTERRUPTDO3": { + "direction": "OUT" + }, + "MIMTXWDATA29": { + "direction": "OUT" + }, + "TRNRD79": { + "direction": "OUT" + }, + "TRNRDLLPDATA25": { + "direction": "OUT" + }, + "TRNRD115": { + "direction": "OUT" + }, + "PIPETX6DATA4": { + "direction": "OUT" + }, + "PL2RXPMSTATE0": { + "direction": "OUT" + }, + "TRNTD90": { + "direction": "IN" + }, + "CFGLINKCONTROLAUTOBANDWIDTHINTEN": { + "direction": "OUT" + }, + "CFGPORTNUMBER1": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG16": { + "direction": "IN" + }, + "TRNTSRCRDY": { + "direction": "IN" + }, + "PIPETX6DATA1": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG88": { + "direction": "IN" + }, + "CFGMGMTDO26": { + "direction": "OUT" + }, + "CFGDSN37": { + "direction": "IN" + }, + "DRPADDR4": { + "direction": "IN" + }, + "PIPETX1DATA9": { + "direction": "OUT" + }, + "PIPERX6STATUS1": { + "direction": "IN" + }, + "PLLTSSMSTATE2": { + "direction": "OUT" + }, + "DBGVECB24": { + "direction": "OUT" + }, + "TRNTDLLPDATA29": { + "direction": "IN" + }, + "DRPADDR8": { + "direction": "IN" + }, + "CFGREVID7": { + "direction": "IN" + }, + "TRNRD46": { + "direction": "OUT" + }, + "PIPETX5DATA3": { + "direction": "OUT" + }, + "PIPERX1STATUS1": { + "direction": "IN" + }, + "CFGPCIELINKSTATE2": { + "direction": "OUT" + }, + "PLRECEIVEDHOTRST": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG18": { + "direction": "IN" + }, + "PIPETX3DATA10": { + "direction": "OUT" + }, + "PIPERX3STATUS1": { + "direction": "IN" + }, + "PIPERX0DATA1": { + "direction": "IN" + }, + "CFGVENDID12": { + "direction": "IN" + }, + "CFGCOMMANDMEMENABLE": { + "direction": "OUT" + }, + "CFGLINKCONTROLASPMCONTROL1": { + "direction": "OUT" + }, + "DBGVECA53": { + "direction": "OUT" + }, + "CFGMGMTDI25": { + "direction": "IN" + }, + "MIMTXWDATA45": { + "direction": "OUT" + }, + "TRNFCNPD6": { + "direction": "OUT" + }, + "PMVOUT": { + "direction": "OUT" + }, + "MIMRXRDATA66": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG41": { + "direction": "IN" + }, + "CFGDEVID12": { + "direction": "IN" + }, + "PIPETX7DATA4": { + "direction": "OUT" + }, + "TRNRFCPRET": { + "direction": "IN" + }, + "MIMTXWDATA22": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG85": { + "direction": "IN" + }, + "CFGINTERRUPTDO0": { + "direction": "OUT" + }, + "TRNRDLLPDATA12": { + "direction": "OUT" + }, + "PLDBGVEC0": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG31": { + "direction": "IN" + }, + "MIMRXRDATA43": { + "direction": "IN" + }, + "CFGVENDID3": { + "direction": "IN" + }, + "TRNRD81": { + "direction": "OUT" + }, + "CFGSUBSYSID15": { + "direction": "IN" + }, + "PIPETX1DATA8": { + "direction": "OUT" + }, + "TRNTD46": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG66": { + "direction": "IN" + }, + "TRNFCNPD1": { + "direction": "OUT" + }, + "MIMTXWDATA32": { + "direction": "OUT" + }, + "XILUNCONNOUT12": { + "direction": "OUT" + }, + "DBGSCLRG": { + "direction": "OUT" + }, + "CFGDEVCONTROL2CPLTIMEOUTVAL1": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG68": { + "direction": "IN" + }, + "CFGAERROOTERRNONFATALERRRECEIVED": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG73": { + "direction": "IN" + }, + "PIPETX4DATA5": { + "direction": "OUT" + }, + "PIPETX1DATA6": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG59": { + "direction": "IN" + }, + "PIPERX4DATA4": { + "direction": "IN" + }, + "TRNFCCPLD6": { + "direction": "OUT" + }, + "PIPETX0DATA11": { + "direction": "OUT" + }, + "CFGPCIELINKSTATE0": { + "direction": "OUT" + }, + "TRNTD34": { + "direction": "IN" + }, + "TRNRDLLPDATA5": { + "direction": "OUT" + }, + "TRNRNPOK": { + "direction": "IN" + }, + "CFGPCIECAPINTERRUPTMSGNUM3": { + "direction": "IN" + }, + "TL2ERRHDR54": { + "direction": "OUT" + }, + "DBGVECB61": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER34": { + "direction": "IN" + }, + "CFGDEVID14": { + "direction": "IN" + }, + "DRPDO15": { + "direction": "OUT" + }, + "MIMRXWDATA10": { + "direction": "OUT" + }, + "PIPERX7STATUS0": { + "direction": "IN" + }, + "DRPDO13": { + "direction": "OUT" + }, + "PIPERX3STATUS2": { + "direction": "IN" + }, + "XILUNCONNOUT36": { + "direction": "OUT" + }, + "CFGLINKCONTROLASPMCONTROL0": { + "direction": "OUT" + }, + "CFGDSDEVICENUMBER2": { + "direction": "IN" + }, + "CFGSUBSYSID12": { + "direction": "IN" + }, + "CFGMGMTDO19": { + "direction": "OUT" + }, + "MIMTXRADDR10": { + "direction": "OUT" + }, + "PIPERX5DATA4": { + "direction": "IN" + }, + "TRNRD3": { + "direction": "OUT" + }, + "MIMRXRADDR9": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG53": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER33": { + "direction": "IN" + }, + "PIPETX5DATA7": { + "direction": "OUT" + }, + "CFGDSFUNCTIONNUMBER1": { + "direction": "IN" + }, + "EDTCONFIGURATION": { + "direction": "IN" + }, + "PIPERX0DATA11": { + "direction": "IN" + }, + "TRNTD116": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG84": { + "direction": "IN" + }, + "TRNTD31": { + "direction": "IN" + }, + "PMVDIVIDE0": { + "direction": "IN" + }, + "PIPERX4VALID": { + "direction": "IN" + }, + "PIPERX5DATA7": { + "direction": "IN" + }, + "CFGVENDID5": { + "direction": "IN" + }, + "PIPERX3DATA2": { + "direction": "IN" + }, + "DBGVECA55": { + "direction": "OUT" + }, + "PIPETX7ELECIDLE": { + "direction": "OUT" + }, + "MIMTXWDATA8": { + "direction": "OUT" + }, + "CFGAERROOTERRNONFATALERRREPORTINGEN": { + "direction": "OUT" + }, + "TRNTD49": { + "direction": "IN" + }, + "TRNTREM1": { + "direction": "IN" + }, + "PMVDIVIDE1": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER0": { + "direction": "IN" + }, + "CFGDSN55": { + "direction": "IN" + }, + "TRNRD93": { + "direction": "OUT" + }, + "PIPETX3DATA11": { + "direction": "OUT" + }, + "TRNTD51": { + "direction": "IN" + }, + "PIPETX2DATA10": { + "direction": "OUT" + }, + "PIPETX7POWERDOWN0": { + "direction": "OUT" + }, + "TRNFCCPLD7": { + "direction": "OUT" + }, + "MIMRXRDATA4": { + "direction": "IN" + }, + "TL2ERRHDR51": { + "direction": "OUT" + }, + "DBGVECC8": { + "direction": "OUT" + }, + "PLLINKUPCFGCAP": { + "direction": "OUT" + }, + "TRNTECRCGEN": { + "direction": "IN" + }, + "MIMTXRDATA21": { + "direction": "IN" + }, + "PIPETX6DATA10": { + "direction": "OUT" + }, + "TRNRD113": { + "direction": "OUT" + }, + "PIPETX0DATA0": { + "direction": "OUT" + }, + "CFGMGMTDO11": { + "direction": "OUT" + }, + "PIPETX7DATA11": { + "direction": "OUT" + }, + "TRNRD59": { + "direction": "OUT" + }, + "MIMTXRDATA48": { + "direction": "IN" + }, + "TRNTD126": { + "direction": "IN" + }, + "MIMRXWDATA17": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG102": { + "direction": "IN" + }, + "MIMRXWDATA62": { + "direction": "OUT" + }, + "CFGDSN1": { + "direction": "IN" + }, + "MIMRXRDATA41": { + "direction": "IN" + }, + "PIPERX7STATUS1": { + "direction": "IN" + }, + "TRNTD45": { + "direction": "IN" + }, + "CFGDSN36": { + "direction": "IN" + }, + "CFGTRANSACTIONADDR1": { + "direction": "OUT" + }, + "TRNTD55": { + "direction": "IN" + }, + "DRPDO0": { + "direction": "OUT" + }, + "MIMRXRDATA36": { + "direction": "IN" + }, + "PIPERX1STATUS0": { + "direction": "IN" + }, + "MIMRXWDATA36": { + "direction": "OUT" + }, + "PIPERX1CHARISK1": { + "direction": "IN" + }, + "PIPERX7DATA2": { + "direction": "IN" + }, + "DBGVECA23": { + "direction": "OUT" + }, + "PIPERX6DATA12": { + "direction": "IN" + }, + "PIPETX6CHARISK1": { + "direction": "OUT" + }, + "CFGERRCPLABORTN": { + "direction": "IN" + }, + "CFGLINKSTATUSNEGOTIATEDWIDTH2": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG54": { + "direction": "IN" + }, + "MIMRXWDATA58": { + "direction": "OUT" + }, + "TRNTD82": { + "direction": "IN" + }, + "CFGMGMTDI2": { + "direction": "IN" + }, + "PIPETX7DATA2": { + "direction": "OUT" + }, + "TRNRD49": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG122": { + "direction": "IN" + }, + "TL2PPMSUSPENDREQ": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG64": { + "direction": "IN" + }, + "PLDIRECTEDLTSSMNEW4": { + "direction": "IN" + }, + "CFGMGMTDO21": { + "direction": "OUT" + }, + "CFGMGMTDWADDR0": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG25": { + "direction": "IN" + }, + "PIPERX5CHARISK0": { + "direction": "IN" + }, + "TRNFCNPD9": { + "direction": "OUT" + }, + "DRPDO3": { + "direction": "OUT" + }, + "CFGPMCSRPMESTATUS": { + "direction": "OUT" + }, + "CFGMGMTDI23": { + "direction": "IN" + }, + "MIMRXWDATA4": { + "direction": "OUT" + }, + "PIPERX1ELECIDLE": { + "direction": "IN" + }, + "PLDIRECTEDLTSSMSTALL": { + "direction": "IN" + }, + "CFGVENDID2": { + "direction": "IN" + }, + "TRNRD112": { + "direction": "OUT" + }, + "TRNTD9": { + "direction": "IN" + }, + "CFGDSN59": { + "direction": "IN" + }, + "PLDBGVEC6": { + "direction": "OUT" + }, + "MIMRXRDATA27": { + "direction": "IN" + }, + "TRNTDLLPDATA3": { + "direction": "IN" + }, + "TRNTD21": { + "direction": "IN" + }, + "MIMRXWDATA52": { + "direction": "OUT" + }, + "PLDIRECTEDLTSSMNEW3": { + "direction": "IN" + }, + "MIMRXWDATA48": { + "direction": "OUT" + }, + "XILUNCONNOUT25": { + "direction": "OUT" + }, + "DBGVECA7": { + "direction": "OUT" + }, + "TRNTD39": { + "direction": "IN" + }, + "CFGMGMTDO2": { + "direction": "OUT" + }, + "LL2SENDASREQL1": { + "direction": "IN" + }, + "CFGDSBUSNUMBER3": { + "direction": "IN" + }, + "TRNTD37": { + "direction": "IN" + }, + "TRNTDLLPDATA16": { + "direction": "IN" + }, + "SCANENABLEN": { + "direction": "IN" + }, + "TRNTD69": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG118": { + "direction": "IN" + }, + "DRPADDR6": { + "direction": "IN" + }, + "XILUNCONNOUT27": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG86": { + "direction": "IN" + }, + "CFGDSBUSNUMBER5": { + "direction": "IN" + }, + "DBGVECA10": { + "direction": "OUT" + }, + "PIPETX2DATA8": { + "direction": "OUT" + }, + "MIMRXRDATA8": { + "direction": "IN" + }, + "CFGDEVCONTROLURERRREPORTINGEN": { + "direction": "OUT" + }, + "MIMTXRDATA17": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG95": { + "direction": "IN" + }, + "DBGVECB26": { + "direction": "OUT" + }, + "XILUNCONNOUT19": { + "direction": "OUT" + }, + "CFGDSN21": { + "direction": "IN" + }, + "TRNRD88": { + "direction": "OUT" + }, + "TRNRD62": { + "direction": "OUT" + }, + "CFGPORTNUMBER3": { + "direction": "IN" + }, + "PIPERX3DATA1": { + "direction": "IN" + }, + "CFGDEVID6": { + "direction": "IN" + }, + "PIPETX0COMPLIANCE": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG9": { + "direction": "IN" + }, + "PIPETX4DATA10": { + "direction": "OUT" + }, + "CFGROOTCONTROLSYSERRNONFATALERREN": { + "direction": "OUT" + }, + "CFGPMSENDPMETON": { + "direction": "IN" + }, + "MIMTXRDATA12": { + "direction": "IN" + }, + "DBGVECA29": { + "direction": "OUT" + }, + "CFGMGMTDO10": { + "direction": "OUT" + }, + "CFGMGMTDI27": { + "direction": "IN" + }, + "CFGSUBSYSVENDID13": { + "direction": "IN" + }, + "TRNTD0": { + "direction": "IN" + }, + "USERCLKPREBUFEN": { + "direction": "IN" + }, + "CFGSUBSYSID6": { + "direction": "IN" + }, + "CFGVENDID0": { + "direction": "IN" + }, + "CFGPMCSRPOWERSTATE0": { + "direction": "OUT" + }, + "CFGDSN46": { + "direction": "IN" + }, + "CFGVCTCVCMAP1": { + "direction": "OUT" + }, + "PIPERX3DATA0": { + "direction": "IN" + }, + "TRNTDLLPDATA28": { + "direction": "IN" + }, + "TRNRD13": { + "direction": "OUT" + }, + "MIMTXRDATA1": { + "direction": "IN" + }, + "CFGTRANSACTIONADDR2": { + "direction": "OUT" + }, + "PIPETX1CHARISK1": { + "direction": "OUT" + }, + "MIMRXWDATA67": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER28": { + "direction": "IN" + }, + "MIMRXWDATA29": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG106": { + "direction": "IN" + }, + "DBGVECA33": { + "direction": "OUT" + }, + "PIPETX4DATA1": { + "direction": "OUT" + }, + "DBGVECB56": { + "direction": "OUT" + }, + "CFGMGMTDI4": { + "direction": "IN" + }, + "CFGINTERRUPTDO1": { + "direction": "OUT" + }, + "PIPERX3STATUS0": { + "direction": "IN" + }, + "MIMTXRDATA34": { + "direction": "IN" + }, + "TRNTD32": { + "direction": "IN" + }, + "TRNTDLLPDATA6": { + "direction": "IN" + }, + "PIPERX6DATA5": { + "direction": "IN" + }, + "MIMRXRDATA21": { + "direction": "IN" + }, + "TRNTDLLPDATA0": { + "direction": "IN" + }, + "MIMRXWDATA57": { + "direction": "OUT" + }, + "TRNTDLLPDATA21": { + "direction": "IN" + }, + "TRNRD84": { + "direction": "OUT" + }, + "TRNTD80": { + "direction": "IN" + }, + "PLTXPMSTATE2": { + "direction": "OUT" + }, + "PIPETX1DATA11": { + "direction": "OUT" + }, + "MIMRXRDATA19": { + "direction": "IN" + }, + "EDTCHANNELSIN6": { + "direction": "IN" + }, + "TRNRD120": { + "direction": "OUT" + }, + "TRNRDLLPDATA26": { + "direction": "OUT" + }, + "TRNRD31": { + "direction": "OUT" + }, + "CFGDEVCONTROLENABLERO": { + "direction": "OUT" + }, + "CFGDEVCONTROL2CPLTIMEOUTVAL3": { + "direction": "OUT" + }, + "PLDIRECTEDLINKAUTON": { + "direction": "IN" + }, + "PIPERX0STATUS1": { + "direction": "IN" + }, + "PIPERX5DATA11": { + "direction": "IN" + }, + "DBGVECA22": { + "direction": "OUT" + }, + "PLDBGVEC8": { + "direction": "OUT" + }, + "CFGDSN45": { + "direction": "IN" + }, + "DBGVECB10": { + "direction": "OUT" + }, + "DBGSCLRB": { + "direction": "OUT" + }, + "TRNRDLLPDATA39": { + "direction": "OUT" + }, + "DBGVECC10": { + "direction": "OUT" + }, + "DBGVECA59": { + "direction": "OUT" + }, + "PIPERX6ELECIDLE": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG121": { + "direction": "IN" + }, + "PIPETX0POWERDOWN1": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER31": { + "direction": "IN" + }, + "PIPETX1DATA15": { + "direction": "OUT" + }, + "PLDBGVEC10": { + "direction": "OUT" + }, + "CFGVENDID14": { + "direction": "IN" + }, + "CFGINTERRUPTDO7": { + "direction": "OUT" + }, + "PIPERX7DATA14": { + "direction": "IN" + }, + "TRNRD105": { + "direction": "OUT" + }, + "TRNRERRFWD": { + "direction": "OUT" + }, + "CFGINTERRUPTDI6": { + "direction": "IN" + }, + "PIPETX7DATA7": { + "direction": "OUT" + }, + "TRNRD1": { + "direction": "OUT" + }, + "DRPRDY": { + "direction": "OUT" + }, + "TRNFCPH3": { + "direction": "OUT" + }, + "TL2ERRHDR17": { + "direction": "OUT" + }, + "TRNRD72": { + "direction": "OUT" + }, + "PIPERX1DATA13": { + "direction": "IN" + }, + "MIMRXWDATA66": { + "direction": "OUT" + }, + "TRNTD30": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG100": { + "direction": "IN" + }, + "TRNRD94": { + "direction": "OUT" + }, + "CFGERRNORECOVERYN": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER27": { + "direction": "IN" + }, + "DBGVECA62": { + "direction": "OUT" + }, + "PIPETX0DATA2": { + "direction": "OUT" + }, + "TRNTD123": { + "direction": "IN" + }, + "MIMTXWADDR2": { + "direction": "OUT" + }, + "TRNFCPD5": { + "direction": "OUT" + }, + "MIMRXRDATA52": { + "direction": "IN" + }, + "TRNRD110": { + "direction": "OUT" + }, + "TL2ERRHDR53": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG48": { + "direction": "IN" + }, + "PLLTSSMSTATE1": { + "direction": "OUT" + }, + "TRNRDLLPDATA63": { + "direction": "OUT" + }, + "MIMRXRDATA42": { + "direction": "IN" + }, + "TRNFCNPD7": { + "direction": "OUT" + }, + "PMVSELECT0": { + "direction": "IN" + }, + "TL2ERRHDR5": { + "direction": "OUT" + }, + "TRNFCCPLH3": { + "direction": "OUT" + }, + "TRNRD51": { + "direction": "OUT" + }, + "TRNRDLLPDATA16": { + "direction": "OUT" + }, + "DBGVECA56": { + "direction": "OUT" + }, + "MIMRXRDATA15": { + "direction": "IN" + }, + "PIPERX3DATA8": { + "direction": "IN" + }, + "DBGVECB47": { + "direction": "OUT" + }, + "CFGMSGDATA1": { + "direction": "OUT" + }, + "CFGTRANSACTIONADDR3": { + "direction": "OUT" + }, + "DBGVECA27": { + "direction": "OUT" + }, + "XILUNCONNOUT37": { + "direction": "OUT" + }, + "CFGMSGDATA13": { + "direction": "OUT" + }, + "PIPETX3DATA12": { + "direction": "OUT" + }, + "MIMTXRDATA59": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER40": { + "direction": "IN" + }, + "TRNFCNPH5": { + "direction": "OUT" + }, + "DBGVECA18": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER22": { + "direction": "IN" + }, + "PIPERX0CHARISK1": { + "direction": "IN" + }, + "DRPDO9": { + "direction": "OUT" + }, + "TRNTD41": { + "direction": "IN" + }, + "TL2ERRHDR12": { + "direction": "OUT" + }, + "TRNFCNPH3": { + "direction": "OUT" + }, + "CFGCOMMANDSERREN": { + "direction": "OUT" + }, + "TRNTCFGREQ": { + "direction": "OUT" + }, + "CFGSUBSYSVENDID14": { + "direction": "IN" + }, + "TRNRD127": { + "direction": "OUT" + }, + "TRNFCCPLD10": { + "direction": "OUT" + }, + "XILUNCONNOUT23": { + "direction": "OUT" + }, + "TRNTD12": { + "direction": "IN" + }, + "CFGLINKSTATUSAUTOBANDWIDTHSTATUS": { + "direction": "OUT" + }, + "PIPETX3ELECIDLE": { + "direction": "OUT" + }, + "TRNFCNPD8": { + "direction": "OUT" + }, + "MIMTXRDATA9": { + "direction": "IN" + }, + "MIMRXWADDR5": { + "direction": "OUT" + }, + "CFGMGMTDO24": { + "direction": "OUT" + }, + "TRNTDLLPDATA22": { + "direction": "IN" + }, + "CFGVENDID9": { + "direction": "IN" + }, + "MIMRXWDATA56": { + "direction": "OUT" + }, + "CFGDSN11": { + "direction": "IN" + }, + "TRNRD39": { + "direction": "OUT" + }, + "MIMRXRDATA34": { + "direction": "IN" + }, + "CFGMSGDATA9": { + "direction": "OUT" + }, + "DBGVECB14": { + "direction": "OUT" + }, + "TRNRD4": { + "direction": "OUT" + }, + "CFGMGMTDO31": { + "direction": "OUT" + }, + "PL2RXPMSTATE1": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG34": { + "direction": "IN" + }, + "MIMRXWEN": { + "direction": "OUT" + }, + "DRPADDR3": { + "direction": "IN" + }, + "PIPERX3DATA4": { + "direction": "IN" + }, + "DBGVECA60": { + "direction": "OUT" + }, + "CFGDEVCONTROLAUXPOWEREN": { + "direction": "OUT" + }, + "MIMTXWDATA36": { + "direction": "OUT" + }, + "MIMTXRDATA64": { + "direction": "IN" + }, + "TRNRD75": { + "direction": "OUT" + }, + "EDTCLK": { + "direction": "IN" + }, + "CFGERRINTERNALCORN": { + "direction": "IN" + }, + "TRNFCNPD4": { + "direction": "OUT" + }, + "MIMRXRDATA67": { + "direction": "IN" + }, + "PIPETX3CHARISK0": { + "direction": "OUT" + }, + "CFGDEVID9": { + "direction": "IN" + }, + "TRNTD15": { + "direction": "IN" + }, + "TRNTD60": { + "direction": "IN" + }, + "PIPERX1DATA5": { + "direction": "IN" + }, + "MIMRXRDATA26": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG36": { + "direction": "IN" + }, + "PIPETX4DATA8": { + "direction": "OUT" + }, + "TRNTBUFAV2": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG60": { + "direction": "IN" + }, + "PIPERX1VALID": { + "direction": "IN" + }, + "XILUNCONNOUT31": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG123": { + "direction": "IN" + }, + "CFGDSN27": { + "direction": "IN" + }, + "DRPDI2": { + "direction": "IN" + }, + "TRNRD7": { + "direction": "OUT" + }, + "PIPERX6DATA1": { + "direction": "IN" + }, + "PIPERX3DATA15": { + "direction": "IN" + }, + "PL2DIRECTEDLSTATE0": { + "direction": "IN" + }, + "TL2ERRRXOVERFLOW": { + "direction": "OUT" + }, + "TRNTD102": { + "direction": "IN" + }, + "PLLTSSMSTATE0": { + "direction": "OUT" + }, + "TRNTD112": { + "direction": "IN" + }, + "CFGMGMTDI24": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER8": { + "direction": "IN" + }, + "PIPETX1DATA2": { + "direction": "OUT" + }, + "MIMTXRDATA28": { + "direction": "IN" + }, + "PIPETX4DATA15": { + "direction": "OUT" + }, + "PIPERX2STATUS2": { + "direction": "IN" + }, + "MIMRXRDATA16": { + "direction": "IN" + }, + "CFGSUBSYSID2": { + "direction": "IN" + }, + "MIMTXRADDR9": { + "direction": "OUT" + }, + "PIPERX7VALID": { + "direction": "IN" + }, + "MIMRXRADDR0": { + "direction": "OUT" + }, + "TRNFCCPLD2": { + "direction": "OUT" + }, + "MIMTXWDATA50": { + "direction": "OUT" + }, + "MIMTXWDATA12": { + "direction": "OUT" + }, + "TL2ERRHDR29": { + "direction": "OUT" + }, + "TRNTDLLPDATA12": { + "direction": "IN" + }, + "CFGMSGDATA2": { + "direction": "OUT" + }, + "PIPERX0DATA9": { + "direction": "IN" + }, + "CFGDSDEVICENUMBER3": { + "direction": "IN" + }, + "TRNFCSEL2": { + "direction": "IN" + }, + "TRNTD47": { + "direction": "IN" + }, + "TRNTDLLPDATA1": { + "direction": "IN" + }, + "TRNRD124": { + "direction": "OUT" + }, + "LL2SENDPMACK": { + "direction": "IN" + }, + "PIPETX5DATA8": { + "direction": "OUT" + }, + "DBGVECB34": { + "direction": "OUT" + }, + "PIPERX4PHYSTATUS": { + "direction": "IN" + }, + "PIPETX7DATA9": { + "direction": "OUT" + }, + "PIPETX5POWERDOWN0": { + "direction": "OUT" + }, + "TL2ERRHDR62": { + "direction": "OUT" + }, + "CFGDSN39": { + "direction": "IN" + }, + "DBGVECB7": { + "direction": "OUT" + }, + "TL2ERRHDR60": { + "direction": "OUT" + }, + "MIMTXWDATA51": { + "direction": "OUT" + }, + "XILUNCONNOUT6": { + "direction": "OUT" + }, + "MIMTXWADDR5": { + "direction": "OUT" + }, + "PIPERX2DATA13": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG97": { + "direction": "IN" + }, + "PLDIRECTEDLTSSMNEW2": { + "direction": "IN" + }, + "MIMRXWDATA18": { + "direction": "OUT" + }, + "MIMRXRDATA0": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG8": { + "direction": "IN" + }, + "PIPERX7DATA10": { + "direction": "IN" + }, + "DBGVECB42": { + "direction": "OUT" + }, + "TRNRD125": { + "direction": "OUT" + }, + "PIPETXMARGIN1": { + "direction": "OUT" + }, + "TRNRD44": { + "direction": "OUT" + }, + "PIPETX3DATA13": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG101": { + "direction": "IN" + }, + "PIPERX4DATA3": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG57": { + "direction": "IN" + }, + "TRNRD36": { + "direction": "OUT" + }, + "PIPERX1DATA2": { + "direction": "IN" + }, + "CFGDEVID1": { + "direction": "IN" + }, + "TRNTD4": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG87": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG4": { + "direction": "IN" + }, + "PIPERX5DATA14": { + "direction": "IN" + }, + "PIPETX4ELECIDLE": { + "direction": "OUT" + }, + "DBGVECB16": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG74": { + "direction": "IN" + }, + "CFGDSN43": { + "direction": "IN" + }, + "MIMRXWDATA15": { + "direction": "OUT" + }, + "MIMTXRDATA33": { + "direction": "IN" + }, + "TRNTD118": { + "direction": "IN" + }, + "CFGAERECRCGENEN": { + "direction": "OUT" + }, + "TRNTD59": { + "direction": "IN" + }, + "TRNRDLLPDATA50": { + "direction": "OUT" + }, + "CFGPCIECAPINTERRUPTMSGNUM0": { + "direction": "IN" + }, + "TL2ERRHDR31": { + "direction": "OUT" + }, + "TRNRDSTRDY": { + "direction": "IN" + }, + "XILUNCONNOUT2": { + "direction": "OUT" + }, + "TRNTD77": { + "direction": "IN" + }, + "PIPERX7DATA11": { + "direction": "IN" + }, + "PIPERX2DATA14": { + "direction": "IN" + }, + "XILUNCONNOUT21": { + "direction": "OUT" + }, + "MIMRXWDATA65": { + "direction": "OUT" + }, + "CFGAERROOTERRFATALERRRECEIVED": { + "direction": "OUT" + }, + "MIMTXRDATA36": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG67": { + "direction": "IN" + }, + "TRNTD11": { + "direction": "IN" + }, + "TRNRD118": { + "direction": "OUT" + }, + "CFGDEVCONTROLMAXPAYLOAD1": { + "direction": "OUT" + }, + "MIMRXWDATA20": { + "direction": "OUT" + }, + "CFGDEVCONTROLFATALERRREPORTINGEN": { + "direction": "OUT" + }, + "CFGDEVCONTROL2IDOREQEN": { + "direction": "OUT" + }, + "DRPDI1": { + "direction": "IN" + }, + "TRNRD64": { + "direction": "OUT" + }, + "MIMTXWDATA64": { + "direction": "OUT" + }, + "DBGSCLRJ": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG26": { + "direction": "IN" + }, + "CFGVENDID4": { + "direction": "IN" + }, + "DRPDI10": { + "direction": "IN" + }, + "MIMRXRDATA51": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER47": { + "direction": "IN" + }, + "TRNTD121": { + "direction": "IN" + }, + "XILUNCONNOUT10": { + "direction": "OUT" + }, + "CFGINTERRUPTDO6": { + "direction": "OUT" + }, + "TRNRDLLPDATA35": { + "direction": "OUT" + }, + "TRNTBUFAV0": { + "direction": "OUT" + }, + "DBGVECB9": { + "direction": "OUT" + }, + "MIMRXWDATA45": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG126": { + "direction": "IN" + }, + "PIPERX2CHANISALIGNED": { + "direction": "IN" + }, + "TRNRD30": { + "direction": "OUT" + }, + "DBGVECB45": { + "direction": "OUT" + }, + "TRNFCPD11": { + "direction": "OUT" + }, + "TRNTD100": { + "direction": "IN" + }, + "PLDIRECTEDLTSSMNEW5": { + "direction": "IN" + }, + "MIMTXRDATA11": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG40": { + "direction": "IN" + }, + "PIPETX4POWERDOWN0": { + "direction": "OUT" + }, + "CFGINTERRUPTDI7": { + "direction": "IN" + }, + "TRNRD67": { + "direction": "OUT" + }, + "DBGVECA47": { + "direction": "OUT" + }, + "DBGVECA2": { + "direction": "OUT" + }, + "MIMTXWDATA27": { + "direction": "OUT" + }, + "PLDBGMODE2": { + "direction": "IN" + }, + "PIPERX7CHARISK0": { + "direction": "IN" + }, + "CFGDEVID11": { + "direction": "IN" + }, + "TRNRD107": { + "direction": "OUT" + }, + "TRNTD29": { + "direction": "IN" + }, + "PIPETX3DATA7": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG52": { + "direction": "IN" + }, + "TRNRDLLPDATA8": { + "direction": "OUT" + }, + "PIPETX0DATA9": { + "direction": "OUT" + }, + "DBGVECB57": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG43": { + "direction": "IN" + }, + "LL2REPLAYROERR": { + "direction": "OUT" + }, + "MIMTXRDATA16": { + "direction": "IN" + }, + "DBGVECB22": { + "direction": "OUT" + }, + "TL2ERRHDR43": { + "direction": "OUT" + }, + "CFGVCTCVCMAP2": { + "direction": "OUT" + }, + "MIMRXWDATA40": { + "direction": "OUT" + }, + "CFGMGMTDO23": { + "direction": "OUT" + }, + "CFGMGMTBYTEENN2": { + "direction": "IN" + }, + "CFGMGMTDWADDR1": { + "direction": "IN" + }, + "CFGPORTNUMBER6": { + "direction": "IN" + }, + "DRPDI13": { + "direction": "IN" + }, + "CFGMGMTDI5": { + "direction": "IN" + }, + "PIPERX5ELECIDLE": { + "direction": "IN" + }, + "TRNFCPD7": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG35": { + "direction": "IN" + }, + "TRNRD8": { + "direction": "OUT" + }, + "CFGMGMTDI0": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER14": { + "direction": "IN" + }, + "DRPDO5": { + "direction": "OUT" + }, + "DBGVECB63": { + "direction": "OUT" + }, + "PIPETX4DATA0": { + "direction": "OUT" + }, + "PLDIRECTEDLTSSMNEW0": { + "direction": "IN" + }, + "CFGDEVCONTROLMAXREADREQ2": { + "direction": "OUT" + }, + "XILUNCONNOUT30": { + "direction": "OUT" + }, + "PIPERX6DATA4": { + "direction": "IN" + }, + "TRNTD7": { + "direction": "IN" + }, + "MIMRXWDATA6": { + "direction": "OUT" + }, + "CFGCOMMANDIOENABLE": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG114": { + "direction": "IN" + }, + "PIPERX0DATA12": { + "direction": "IN" + }, + "DBGVECA0": { + "direction": "OUT" + }, + "PIPETX0DATA7": { + "direction": "OUT" + }, + "MIMTXWDATA59": { + "direction": "OUT" + }, + "MIMRXWDATA46": { + "direction": "OUT" + }, + "PIPETX0DATA1": { + "direction": "OUT" + }, + "DBGVECB59": { + "direction": "OUT" + }, + "DBGVECA6": { + "direction": "OUT" + }, + "XILUNCONNOUT18": { + "direction": "OUT" + }, + "XILUNCONNOUT11": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG15": { + "direction": "IN" + }, + "PIPERX7DATA12": { + "direction": "IN" + }, + "TRNRD21": { + "direction": "OUT" + }, + "XILUNCONNOUT8": { + "direction": "OUT" + }, + "MIMTXWDATA41": { + "direction": "OUT" + }, + "TRNTDLLPDATA17": { + "direction": "IN" + }, + "MIMTXWDATA3": { + "direction": "OUT" + }, + "LL2BADDLLPERR": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER16": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG104": { + "direction": "IN" + }, + "PIPETX5POWERDOWN1": { + "direction": "OUT" + }, + "TRNTREM0": { + "direction": "IN" + }, + "PIPERX2DATA7": { + "direction": "IN" + }, + "TL2ERRMALFORMED": { + "direction": "OUT" + }, + "TRNRDLLPDATA41": { + "direction": "OUT" + }, + "DBGSCLRK": { + "direction": "OUT" + }, + "PIPETX3DATA6": { + "direction": "OUT" + }, + "CFGCOMMANDINTERRUPTDISABLE": { + "direction": "OUT" + }, + "TL2ERRHDR37": { + "direction": "OUT" + }, + "CFGMSGDATA3": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER23": { + "direction": "IN" + }, + "TRNRDLLPDATA38": { + "direction": "OUT" + }, + "TL2ERRHDR35": { + "direction": "OUT" + }, + "PIPETX6DATA8": { + "direction": "OUT" + }, + "MIMRXWDATA35": { + "direction": "OUT" + }, + "CFGMGMTBYTEENN1": { + "direction": "IN" + }, + "LL2LINKSTATUS0": { + "direction": "OUT" + }, + "CFGVENDID6": { + "direction": "IN" + }, + "MIMRXWDATA3": { + "direction": "OUT" + }, + "DBGVECB51": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDASSERTINTA": { + "direction": "OUT" + }, + "CFGSUBSYSID7": { + "direction": "IN" + }, + "DBGVECA26": { + "direction": "OUT" + }, + "TRNTD65": { + "direction": "IN" + }, + "DBGVECB46": { + "direction": "OUT" + }, + "TRNRD5": { + "direction": "OUT" + }, + "TRNRDLLPDATA59": { + "direction": "OUT" + }, + "DBGVECA49": { + "direction": "OUT" + }, + "PIPERX0PHYSTATUS": { + "direction": "IN" + }, + "CFGMGMTDI18": { + "direction": "IN" + }, + "CFGLINKSTATUSDLLACTIVE": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG29": { + "direction": "IN" + }, + "PIPETX1DATA4": { + "direction": "OUT" + }, + "TRNRBARHIT4": { + "direction": "OUT" + }, + "PIPERX2DATA5": { + "direction": "IN" + }, + "CFGDSN23": { + "direction": "IN" + }, + "TRNTD87": { + "direction": "IN" + }, + "CFGTRANSACTION": { + "direction": "OUT" + }, + "TRNRDLLPDATA6": { + "direction": "OUT" + }, + "PIPETX3DATA0": { + "direction": "OUT" + }, + "CFGPORTNUMBER7": { + "direction": "IN" + }, + "PIPERX5POLARITY": { + "direction": "OUT" + }, + "EDTCHANNELSOUT3": { + "direction": "OUT" + }, + "MIMTXRDATA40": { + "direction": "IN" + }, + "PLSELLNKWIDTH1": { + "direction": "OUT" + }, + "PIPETX6DATA6": { + "direction": "OUT" + }, + "LL2LINKSTATUS3": { + "direction": "OUT" + }, + "CFGINTERRUPTMMENABLE2": { + "direction": "OUT" + }, + "MIMRXRDATA1": { + "direction": "IN" + }, + "TRNRDLLPDATA19": { + "direction": "OUT" + }, + "PIPETX6COMPLIANCE": { + "direction": "OUT" + }, + "TRNRD9": { + "direction": "OUT" + }, + "DRPDO1": { + "direction": "OUT" + }, + "XILUNCONNOUT9": { + "direction": "OUT" + }, + "PIPERX0DATA6": { + "direction": "IN" + }, + "TL2ERRHDR4": { + "direction": "OUT" + }, + "PIPERX4DATA10": { + "direction": "IN" + }, + "CFGMGMTDI8": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG117": { + "direction": "IN" + }, + "CFGVENDID10": { + "direction": "IN" + }, + "DBGVECA16": { + "direction": "OUT" + }, + "MIMRXWDATA11": { + "direction": "OUT" + }, + "MIMRXREN": { + "direction": "OUT" + }, + "DBGVECA45": { + "direction": "OUT" + }, + "MIMTXRDATA35": { + "direction": "IN" + }, + "PIPETX0DATA8": { + "direction": "OUT" + }, + "PIPERX3DATA9": { + "direction": "IN" + }, + "TRNTD104": { + "direction": "IN" + }, + "XILUNCONNOUT4": { + "direction": "OUT" + }, + "MIMRXWDATA31": { + "direction": "OUT" + }, + "XILUNCONNOUT26": { + "direction": "OUT" + }, + "DBGVECA8": { + "direction": "OUT" + }, + "PIPETX3DATA8": { + "direction": "OUT" + }, + "PIPETX2ELECIDLE": { + "direction": "OUT" + }, + "CFGMGMTDO8": { + "direction": "OUT" + }, + "PIPERX4DATA0": { + "direction": "IN" + }, + "TL2ERRHDR0": { + "direction": "OUT" + }, + "PIPERX5DATA0": { + "direction": "IN" + }, + "TRNFCCPLD4": { + "direction": "OUT" + }, + "MIMTXRDATA15": { + "direction": "IN" + }, + "DBGVECB1": { + "direction": "OUT" + }, + "PIPERX4DATA15": { + "direction": "IN" + }, + "PLDBGVEC9": { + "direction": "OUT" + }, + "TL2ERRHDR63": { + "direction": "OUT" + }, + "CFGSUBSYSVENDID5": { + "direction": "IN" + }, + "CFGMGMTDI9": { + "direction": "IN" + }, + "TRNTD99": { + "direction": "IN" + }, + "MIMTXWDATA44": { + "direction": "OUT" + }, + "DBGVECA12": { + "direction": "OUT" + }, + "MIMRXWADDR7": { + "direction": "OUT" + }, + "PIPERX3VALID": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_PHASER_IN_PHY.json b/kintex7/site_type_PHASER_IN_PHY.json new file mode 100644 index 0000000..62738a9 --- /dev/null +++ b/kintex7/site_type_PHASER_IN_PHY.json @@ -0,0 +1,291 @@ +{ + "type": "PHASER_IN_PHY", + "site_pips": { + "RSTINV:RST": { + "from_pin": "RST", + "to_pin": "OUT" + }, + "RSTINV:RST_B": { + "from_pin": "RST_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "TESTOUT1": { + "direction": "OUT" + }, + "TESTIN11": { + "direction": "IN" + }, + "ISERDESRST": { + "direction": "OUT" + }, + "COUNTERLOADEN": { + "direction": "IN" + }, + "STG1REGL1": { + "direction": "IN" + }, + "TESTIN0": { + "direction": "IN" + }, + "RST": { + "direction": "IN" + }, + "TESTIN6": { + "direction": "IN" + }, + "STG1REGR1": { + "direction": "OUT" + }, + "TESTIN9": { + "direction": "IN" + }, + "COUNTERLOADVAL2": { + "direction": "IN" + }, + "SCANMODEB": { + "direction": "IN" + }, + "COUNTERREADVAL1": { + "direction": "OUT" + }, + "COUNTERLOADVAL1": { + "direction": "IN" + }, + "COUNTERREADVAL2": { + "direction": "OUT" + }, + "STG1REGR8": { + "direction": "OUT" + }, + "ENSTG1ADJUSTB": { + "direction": "IN" + }, + "BURSTPENDINGPHY": { + "direction": "IN" + }, + "COUNTERREADVAL5": { + "direction": "OUT" + }, + "RCLK": { + "direction": "OUT" + }, + "DQSFOUND": { + "direction": "OUT" + }, + "TESTIN1": { + "direction": "IN" + }, + "STG1REGR6": { + "direction": "OUT" + }, + "FINEENABLE": { + "direction": "IN" + }, + "SCANENB": { + "direction": "IN" + }, + "STG1REGL4": { + "direction": "IN" + }, + "ICLK": { + "direction": "OUT" + }, + "STG1REGR2": { + "direction": "OUT" + }, + "STG1INCDEC": { + "direction": "IN" + }, + "RANKSEL0": { + "direction": "IN" + }, + "BURSTPENDING": { + "direction": "IN" + }, + "FINEOVERFLOW": { + "direction": "OUT" + }, + "TESTIN8": { + "direction": "IN" + }, + "COUNTERLOADVAL3": { + "direction": "IN" + }, + "STG1REGR5": { + "direction": "OUT" + }, + "COUNTERLOADVAL0": { + "direction": "IN" + }, + "COUNTERREADVAL4": { + "direction": "OUT" + }, + "TESTOUT2": { + "direction": "OUT" + }, + "STG1REGR0": { + "direction": "OUT" + }, + "COUNTERLOADVAL4": { + "direction": "IN" + }, + "COUNTERREADVAL3": { + "direction": "OUT" + }, + "SYSCLK": { + "direction": "IN" + }, + "STG1OVERFLOW": { + "direction": "OUT" + }, + "COUNTERREADEN": { + "direction": "IN" + }, + "TESTIN12": { + "direction": "IN" + }, + "FINEINC": { + "direction": "IN" + }, + "TESTIN3": { + "direction": "IN" + }, + "SCANIN": { + "direction": "IN" + }, + "COUNTERREADVAL0": { + "direction": "OUT" + }, + "RANKSELPHY1": { + "direction": "IN" + }, + "EDGEADV": { + "direction": "IN" + }, + "SELCALORSTG1": { + "direction": "IN" + }, + "SCANOUT": { + "direction": "OUT" + }, + "ICLKDIV": { + "direction": "OUT" + }, + "TESTOUT0": { + "direction": "OUT" + }, + "MEMREFCLK": { + "direction": "IN" + }, + "COUNTERLOADVAL5": { + "direction": "IN" + }, + "RANKSEL1": { + "direction": "IN" + }, + "STG1REGL6": { + "direction": "IN" + }, + "STG1REGR4": { + "direction": "OUT" + }, + "ENCALIBPHY1": { + "direction": "IN" + }, + "STG1REGL0": { + "direction": "IN" + }, + "DIVIDERST": { + "direction": "IN" + }, + "TESTIN10": { + "direction": "IN" + }, + "WRENABLE": { + "direction": "OUT" + }, + "STG1REGR7": { + "direction": "OUT" + }, + "TESTIN7": { + "direction": "IN" + }, + "PHASELOCKED": { + "direction": "OUT" + }, + "RSTDQSFIND": { + "direction": "IN" + }, + "STG1REGL3": { + "direction": "IN" + }, + "RANKSELPHY0": { + "direction": "IN" + }, + "SYNCIN": { + "direction": "IN" + }, + "TESTOUT3": { + "direction": "OUT" + }, + "STG1LOAD": { + "direction": "IN" + }, + "ENCALIB0": { + "direction": "IN" + }, + "STG1REGL8": { + "direction": "IN" + }, + "ENCALIB1": { + "direction": "IN" + }, + "ENSTG1": { + "direction": "IN" + }, + "STG1REGL7": { + "direction": "IN" + }, + "STG1REGL5": { + "direction": "IN" + }, + "TESTIN4": { + "direction": "IN" + }, + "STG1REGL2": { + "direction": "IN" + }, + "FREQREFCLK": { + "direction": "IN" + }, + "TESTIN13": { + "direction": "IN" + }, + "SCANCLK": { + "direction": "IN" + }, + "ENCALIBPHY0": { + "direction": "IN" + }, + "STG1READ": { + "direction": "IN" + }, + "PHASEREFCLK": { + "direction": "IN" + }, + "TESTIN2": { + "direction": "IN" + }, + "STG1REGR3": { + "direction": "OUT" + }, + "TESTIN5": { + "direction": "IN" + }, + "DQSOUTOFRANGE": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_PHASER_OUT_PHY.json b/kintex7/site_type_PHASER_OUT_PHY.json new file mode 100644 index 0000000..e4df7b2 --- /dev/null +++ b/kintex7/site_type_PHASER_OUT_PHY.json @@ -0,0 +1,246 @@ +{ + "type": "PHASER_OUT_PHY", + "site_pips": { + "RSTINV:RST": { + "from_pin": "RST", + "to_pin": "OUT" + }, + "RSTINV:RST_B": { + "from_pin": "RST_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "TESTOUT1": { + "direction": "OUT" + }, + "FINEINC": { + "direction": "IN" + }, + "SCANIN": { + "direction": "IN" + }, + "COUNTERREADVAL0": { + "direction": "OUT" + }, + "COUNTERLOADVAL8": { + "direction": "IN" + }, + "TESTOUT3": { + "direction": "OUT" + }, + "EDGEADV": { + "direction": "IN" + }, + "COUNTERLOADVAL7": { + "direction": "IN" + }, + "SCANOUT": { + "direction": "OUT" + }, + "DTSBUS1": { + "direction": "OUT" + }, + "DQSBUS1": { + "direction": "OUT" + }, + "TESTIN14": { + "direction": "IN" + }, + "TESTIN0": { + "direction": "IN" + }, + "RST": { + "direction": "IN" + }, + "TESTIN6": { + "direction": "IN" + }, + "TESTIN9": { + "direction": "IN" + }, + "COUNTERLOADVAL2": { + "direction": "IN" + }, + "TESTIN3": { + "direction": "IN" + }, + "TESTOUT0": { + "direction": "OUT" + }, + "COARSEOVERFLOW": { + "direction": "OUT" + }, + "COARSEINC": { + "direction": "IN" + }, + "SCANMODEB": { + "direction": "IN" + }, + "CTSBUS0": { + "direction": "OUT" + }, + "COUNTERREADVAL1": { + "direction": "OUT" + }, + "COUNTERLOADVAL1": { + "direction": "IN" + }, + "COUNTERLOADVAL5": { + "direction": "IN" + }, + "COUNTERREADVAL2": { + "direction": "OUT" + }, + "OCLKDIV": { + "direction": "OUT" + }, + "ENCALIBPHY1": { + "direction": "IN" + }, + "DIVIDERST": { + "direction": "IN" + }, + "TESTIN10": { + "direction": "IN" + }, + "COUNTERREADVAL5": { + "direction": "OUT" + }, + "TESTIN1": { + "direction": "IN" + }, + "DQSBUS0": { + "direction": "OUT" + }, + "FINEENABLE": { + "direction": "IN" + }, + "TESTIN7": { + "direction": "IN" + }, + "TESTIN12": { + "direction": "IN" + }, + "COUNTERLOADEN": { + "direction": "IN" + }, + "SCANENB": { + "direction": "IN" + }, + "OCLK": { + "direction": "OUT" + }, + "SELFINEOCLKDELAY": { + "direction": "IN" + }, + "DTSBUS0": { + "direction": "OUT" + }, + "COUNTERREADVAL8": { + "direction": "OUT" + }, + "MEMREFCLK": { + "direction": "IN" + }, + "TESTIN4": { + "direction": "IN" + }, + "SYNCIN": { + "direction": "IN" + }, + "FINEOVERFLOW": { + "direction": "OUT" + }, + "TESTIN8": { + "direction": "IN" + }, + "TESTIN11": { + "direction": "IN" + }, + "COUNTERLOADVAL3": { + "direction": "IN" + }, + "ENCALIB0": { + "direction": "IN" + }, + "ENCALIB1": { + "direction": "IN" + }, + "COUNTERLOADVAL6": { + "direction": "IN" + }, + "OSERDESRST": { + "direction": "OUT" + }, + "COUNTERLOADVAL0": { + "direction": "IN" + }, + "RDENABLE": { + "direction": "OUT" + }, + "COUNTERREADVAL4": { + "direction": "OUT" + }, + "TESTOUT2": { + "direction": "OUT" + }, + "COUNTERLOADVAL4": { + "direction": "IN" + }, + "COARSEENABLE": { + "direction": "IN" + }, + "OCLKDELAYED": { + "direction": "OUT" + }, + "FREQREFCLK": { + "direction": "IN" + }, + "TESTIN13": { + "direction": "IN" + }, + "COUNTERREADVAL3": { + "direction": "OUT" + }, + "SCANCLK": { + "direction": "IN" + }, + "SYSCLK": { + "direction": "IN" + }, + "BURSTPENDINGPHY": { + "direction": "IN" + }, + "ENCALIBPHY0": { + "direction": "IN" + }, + "BURSTPENDING": { + "direction": "IN" + }, + "PHASEREFCLK": { + "direction": "IN" + }, + "TESTIN15": { + "direction": "IN" + }, + "COUNTERREADEN": { + "direction": "IN" + }, + "COUNTERREADVAL6": { + "direction": "OUT" + }, + "COUNTERREADVAL7": { + "direction": "OUT" + }, + "TESTIN5": { + "direction": "IN" + }, + "TESTIN2": { + "direction": "IN" + }, + "CTSBUS1": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_PHASER_REF.json b/kintex7/site_type_PHASER_REF.json new file mode 100644 index 0000000..0b3561e --- /dev/null +++ b/kintex7/site_type_PHASER_REF.json @@ -0,0 +1,89 @@ +{ + "type": "PHASER_REF", + "site_pips": { + "RSTINV:RST": { + "from_pin": "RST", + "to_pin": "OUT" + }, + "PWRDWNINV:PWRDWN_B": { + "from_pin": "PWRDWN_B", + "to_pin": "OUT" + }, + "PWRDWNINV:PWRDWN": { + "from_pin": "PWRDWN", + "to_pin": "OUT" + }, + "RSTINV:RST_B": { + "from_pin": "RST_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "TESTIN7": { + "direction": "IN" + }, + "TESTOUT1": { + "direction": "OUT" + }, + "TESTOUT4": { + "direction": "OUT" + }, + "TESTIN0": { + "direction": "IN" + }, + "LOCKED": { + "direction": "OUT" + }, + "TESTOUT7": { + "direction": "OUT" + }, + "TESTIN4": { + "direction": "IN" + }, + "CLKOUT": { + "direction": "OUT" + }, + "RST": { + "direction": "IN" + }, + "TESTOUT3": { + "direction": "OUT" + }, + "TESTIN6": { + "direction": "IN" + }, + "CLKIN": { + "direction": "IN" + }, + "TESTIN3": { + "direction": "IN" + }, + "TESTOUT0": { + "direction": "OUT" + }, + "TMUXOUT": { + "direction": "OUT" + }, + "TESTOUT2": { + "direction": "OUT" + }, + "PWRDWN": { + "direction": "IN" + }, + "TESTOUT6": { + "direction": "OUT" + }, + "TESTOUT5": { + "direction": "OUT" + }, + "TESTIN1": { + "direction": "IN" + }, + "TESTIN5": { + "direction": "IN" + }, + "TESTIN2": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_PHY_CONTROL.json b/kintex7/site_type_PHY_CONTROL.json new file mode 100644 index 0000000..5dd5417 --- /dev/null +++ b/kintex7/site_type_PHY_CONTROL.json @@ -0,0 +1,318 @@ +{ + "type": "PHY_CONTROL", + "site_pips": {}, + "site_pins": { + "TESTINPUT2": { + "direction": "IN" + }, + "TESTOUTPUT3": { + "direction": "OUT" + }, + "TESTOUTPUT0": { + "direction": "OUT" + }, + "PHYCTLWD9": { + "direction": "IN" + }, + "PHYCTLWD20": { + "direction": "IN" + }, + "TESTOUTPUT7": { + "direction": "OUT" + }, + "TESTOUTPUT1": { + "direction": "OUT" + }, + "OUTBURSTPENDING2": { + "direction": "OUT" + }, + "INBURSTPENDING2": { + "direction": "OUT" + }, + "TESTINPUT8": { + "direction": "IN" + }, + "REFDLLLOCK": { + "direction": "IN" + }, + "OUTBURSTPENDING1": { + "direction": "OUT" + }, + "PHYCTLWD6": { + "direction": "IN" + }, + "PHYCTLWD17": { + "direction": "IN" + }, + "WRITECALIBENABLE": { + "direction": "IN" + }, + "PHYCTLEMPTY": { + "direction": "OUT" + }, + "INRANKA1": { + "direction": "OUT" + }, + "PHYCTLFULL": { + "direction": "OUT" + }, + "AUXOUTPUT0": { + "direction": "OUT" + }, + "TESTOUTPUT2": { + "direction": "OUT" + }, + "PHYCTLWD19": { + "direction": "IN" + }, + "INRANKD1": { + "direction": "OUT" + }, + "PHYCTLWD10": { + "direction": "IN" + }, + "PHYCTLWD14": { + "direction": "IN" + }, + "PCENABLECALIB0": { + "direction": "OUT" + }, + "TESTOUTPUT12": { + "direction": "OUT" + }, + "TESTINPUT7": { + "direction": "IN" + }, + "TESTSELECT2": { + "direction": "IN" + }, + "TESTOUTPUT15": { + "direction": "OUT" + }, + "PHYCTLWD11": { + "direction": "IN" + }, + "PHYCLK": { + "direction": "IN" + }, + "TESTINPUT13": { + "direction": "IN" + }, + "AUXOUTPUT2": { + "direction": "OUT" + }, + "INRANKB0": { + "direction": "OUT" + }, + "TESTINPUT12": { + "direction": "IN" + }, + "TESTINPUT11": { + "direction": "IN" + }, + "PHYCTLREADY": { + "direction": "OUT" + }, + "TESTSELECT0": { + "direction": "IN" + }, + "TESTINPUT0": { + "direction": "IN" + }, + "INRANKD0": { + "direction": "OUT" + }, + "PHYCTLWD7": { + "direction": "IN" + }, + "TESTINPUT10": { + "direction": "IN" + }, + "PHYCTLWD5": { + "direction": "IN" + }, + "INBURSTPENDING3": { + "direction": "OUT" + }, + "PHYCTLWD13": { + "direction": "IN" + }, + "PHYCTLWD4": { + "direction": "IN" + }, + "TESTOUTPUT11": { + "direction": "OUT" + }, + "TESTINPUT5": { + "direction": "IN" + }, + "PLLLOCK": { + "direction": "IN" + }, + "INBURSTPENDING1": { + "direction": "OUT" + }, + "PHYCTLWD26": { + "direction": "IN" + }, + "PHYCTLWD1": { + "direction": "IN" + }, + "OUTBURSTPENDING0": { + "direction": "OUT" + }, + "INBURSTPENDING0": { + "direction": "OUT" + }, + "TESTOUTPUT8": { + "direction": "OUT" + }, + "PCENABLECALIB1": { + "direction": "OUT" + }, + "PHYCTLWD31": { + "direction": "IN" + }, + "PHYCTLWD22": { + "direction": "IN" + }, + "PHYCTLWD16": { + "direction": "IN" + }, + "SCANENABLEN": { + "direction": "IN" + }, + "INRANKC0": { + "direction": "OUT" + }, + "PHYCTLWD15": { + "direction": "IN" + }, + "AUXOUTPUT1": { + "direction": "OUT" + }, + "PHYCTLWD27": { + "direction": "IN" + }, + "TESTINPUT3": { + "direction": "IN" + }, + "INRANKB1": { + "direction": "OUT" + }, + "TESTOUTPUT13": { + "direction": "OUT" + }, + "PHYCTLWD0": { + "direction": "IN" + }, + "MEMREFCLK": { + "direction": "IN" + }, + "TESTOUTPUT4": { + "direction": "OUT" + }, + "TESTINPUT4": { + "direction": "IN" + }, + "PHYCTLWD25": { + "direction": "IN" + }, + "INRANKA0": { + "direction": "OUT" + }, + "PHYCTLWD30": { + "direction": "IN" + }, + "PHYCTLWD21": { + "direction": "IN" + }, + "TESTINPUT15": { + "direction": "IN" + }, + "PHYCTLWD12": { + "direction": "IN" + }, + "PHYCTLWD3": { + "direction": "IN" + }, + "PHYCTLWD2": { + "direction": "IN" + }, + "PHYCTLWD8": { + "direction": "IN" + }, + "TESTSELECT1": { + "direction": "IN" + }, + "SYNCIN": { + "direction": "IN" + }, + "TESTOUTPUT14": { + "direction": "OUT" + }, + "PHYCTLWD23": { + "direction": "IN" + }, + "PHYCTLWRENABLE": { + "direction": "IN" + }, + "AUXOUTPUT3": { + "direction": "OUT" + }, + "TESTINPUT9": { + "direction": "IN" + }, + "TESTOUTPUT9": { + "direction": "OUT" + }, + "TESTOUTPUT10": { + "direction": "OUT" + }, + "TESTINPUT1": { + "direction": "IN" + }, + "PHYCTLWD28": { + "direction": "IN" + }, + "TESTOUTPUT5": { + "direction": "OUT" + }, + "TESTINPUT6": { + "direction": "IN" + }, + "TESTOUTPUT6": { + "direction": "OUT" + }, + "PHYCTLWD24": { + "direction": "IN" + }, + "INRANKC1": { + "direction": "OUT" + }, + "TESTINPUT14": { + "direction": "IN" + }, + "PHYCTLWD29": { + "direction": "IN" + }, + "PHYCTLMSTREMPTY": { + "direction": "IN" + }, + "RESET": { + "direction": "IN" + }, + "READCALIBENABLE": { + "direction": "IN" + }, + "PHYCTLALMOSTFULL": { + "direction": "OUT" + }, + "PHYCTLWD18": { + "direction": "IN" + }, + "OUTBURSTPENDING3": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_PLLE2_ADV.json b/kintex7/site_type_PLLE2_ADV.json new file mode 100644 index 0000000..232a324 --- /dev/null +++ b/kintex7/site_type_PLLE2_ADV.json @@ -0,0 +1,493 @@ +{ + "type": "PLLE2_ADV", + "site_pips": { + "RSTINV:RST": { + "from_pin": "RST", + "to_pin": "OUT" + }, + "CLKINSELINV:CLKINSEL_B": { + "from_pin": "CLKINSEL_B", + "to_pin": "OUT" + }, + "PWRDWNINV:PWRDWN_B": { + "from_pin": "PWRDWN_B", + "to_pin": "OUT" + }, + "PWRDWNINV:PWRDWN": { + "from_pin": "PWRDWN", + "to_pin": "OUT" + }, + "CLKINSELINV:CLKINSEL": { + "from_pin": "CLKINSEL", + "to_pin": "OUT" + }, + "RSTINV:RST_B": { + "from_pin": "RST_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "TESTOUT31": { + "direction": "OUT" + }, + "TESTOUT51": { + "direction": "OUT" + }, + "TESTOUT56": { + "direction": "OUT" + }, + "DO9": { + "direction": "OUT" + }, + "TESTOUT26": { + "direction": "OUT" + }, + "TESTOUT7": { + "direction": "OUT" + }, + "TESTIN31": { + "direction": "IN" + }, + "TESTIN14": { + "direction": "IN" + }, + "TESTOUT53": { + "direction": "OUT" + }, + "RST": { + "direction": "IN" + }, + "TESTIN18": { + "direction": "IN" + }, + "TESTIN6": { + "direction": "IN" + }, + "TESTOUT28": { + "direction": "OUT" + }, + "TESTIN9": { + "direction": "IN" + }, + "TESTOUT9": { + "direction": "OUT" + }, + "TESTOUT59": { + "direction": "OUT" + }, + "TESTOUT35": { + "direction": "OUT" + }, + "CLKOUT2": { + "direction": "OUT" + }, + "TESTIN29": { + "direction": "IN" + }, + "CLKFBOUT": { + "direction": "OUT" + }, + "TESTIN30": { + "direction": "IN" + }, + "TESTIN23": { + "direction": "IN" + }, + "TESTOUT11": { + "direction": "OUT" + }, + "TESTIN21": { + "direction": "IN" + }, + "TESTOUT41": { + "direction": "OUT" + }, + "TESTOUT43": { + "direction": "OUT" + }, + "TESTIN22": { + "direction": "IN" + }, + "TESTOUT32": { + "direction": "OUT" + }, + "TESTIN19": { + "direction": "IN" + }, + "TESTOUT5": { + "direction": "OUT" + }, + "TESTIN1": { + "direction": "IN" + }, + "CLKFBIN": { + "direction": "IN" + }, + "DI11": { + "direction": "IN" + }, + "TESTOUT15": { + "direction": "OUT" + }, + "DO12": { + "direction": "OUT" + }, + "TESTOUT44": { + "direction": "OUT" + }, + "DI2": { + "direction": "IN" + }, + "CLKINSEL": { + "direction": "IN" + }, + "DI13": { + "direction": "IN" + }, + "TESTOUT27": { + "direction": "OUT" + }, + "TESTOUT4": { + "direction": "OUT" + }, + "DRDY": { + "direction": "OUT" + }, + "TESTIN20": { + "direction": "IN" + }, + "TESTOUT22": { + "direction": "OUT" + }, + "DO5": { + "direction": "OUT" + }, + "TESTOUT49": { + "direction": "OUT" + }, + "TESTIN17": { + "direction": "IN" + }, + "TESTOUT19": { + "direction": "OUT" + }, + "DI4": { + "direction": "IN" + }, + "DADDR0": { + "direction": "IN" + }, + "DADDR3": { + "direction": "IN" + }, + "DO3": { + "direction": "OUT" + }, + "TESTIN8": { + "direction": "IN" + }, + "DI8": { + "direction": "IN" + }, + "TESTOUT61": { + "direction": "OUT" + }, + "TESTOUT12": { + "direction": "OUT" + }, + "TESTOUT57": { + "direction": "OUT" + }, + "TESTOUT42": { + "direction": "OUT" + }, + "DO4": { + "direction": "OUT" + }, + "TESTOUT3": { + "direction": "OUT" + }, + "TESTOUT17": { + "direction": "OUT" + }, + "TESTOUT40": { + "direction": "OUT" + }, + "TESTOUT2": { + "direction": "OUT" + }, + "DI0": { + "direction": "IN" + }, + "DADDR4": { + "direction": "IN" + }, + "DWE": { + "direction": "IN" + }, + "TESTOUT16": { + "direction": "OUT" + }, + "DCLK": { + "direction": "IN" + }, + "DI6": { + "direction": "IN" + }, + "TMUXOUT": { + "direction": "OUT" + }, + "DADDR2": { + "direction": "IN" + }, + "TESTOUT13": { + "direction": "OUT" + }, + "DADDR1": { + "direction": "IN" + }, + "DO1": { + "direction": "OUT" + }, + "TESTOUT23": { + "direction": "OUT" + }, + "TESTIN2": { + "direction": "IN" + }, + "TESTOUT8": { + "direction": "OUT" + }, + "CLKOUT0": { + "direction": "OUT" + }, + "DO11": { + "direction": "OUT" + }, + "TESTOUT47": { + "direction": "OUT" + }, + "TESTOUT21": { + "direction": "OUT" + }, + "DADDR5": { + "direction": "IN" + }, + "DI10": { + "direction": "IN" + }, + "TESTOUT6": { + "direction": "OUT" + }, + "TESTIN28": { + "direction": "IN" + }, + "TESTOUT63": { + "direction": "OUT" + }, + "TESTOUT33": { + "direction": "OUT" + }, + "TESTOUT52": { + "direction": "OUT" + }, + "TESTOUT20": { + "direction": "OUT" + }, + "CLKOUT3": { + "direction": "OUT" + }, + "DO0": { + "direction": "OUT" + }, + "TESTOUT34": { + "direction": "OUT" + }, + "DO13": { + "direction": "OUT" + }, + "TESTOUT24": { + "direction": "OUT" + }, + "TESTOUT18": { + "direction": "OUT" + }, + "TESTOUT54": { + "direction": "OUT" + }, + "TESTOUT58": { + "direction": "OUT" + }, + "TESTIN3": { + "direction": "IN" + }, + "TESTOUT0": { + "direction": "OUT" + }, + "DO15": { + "direction": "OUT" + }, + "DI1": { + "direction": "IN" + }, + "DI5": { + "direction": "IN" + }, + "TESTOUT55": { + "direction": "OUT" + }, + "TESTOUT10": { + "direction": "OUT" + }, + "TESTIN15": { + "direction": "IN" + }, + "TESTIN25": { + "direction": "IN" + }, + "TESTOUT37": { + "direction": "OUT" + }, + "DEN": { + "direction": "IN" + }, + "DI14": { + "direction": "IN" + }, + "TESTOUT62": { + "direction": "OUT" + }, + "DI9": { + "direction": "IN" + }, + "TESTOUT1": { + "direction": "OUT" + }, + "DI7": { + "direction": "IN" + }, + "TESTIN10": { + "direction": "IN" + }, + "TESTOUT36": { + "direction": "OUT" + }, + "CLKOUT5": { + "direction": "OUT" + }, + "DO7": { + "direction": "OUT" + }, + "DI12": { + "direction": "IN" + }, + "TESTIN0": { + "direction": "IN" + }, + "TESTOUT46": { + "direction": "OUT" + }, + "TESTIN7": { + "direction": "IN" + }, + "TESTOUT38": { + "direction": "OUT" + }, + "DO10": { + "direction": "OUT" + }, + "LOCKED": { + "direction": "OUT" + }, + "DO14": { + "direction": "OUT" + }, + "CLKOUT1": { + "direction": "OUT" + }, + "TESTIN27": { + "direction": "IN" + }, + "TESTOUT14": { + "direction": "OUT" + }, + "TESTIN4": { + "direction": "IN" + }, + "CLKIN2": { + "direction": "IN" + }, + "CLKIN1": { + "direction": "IN" + }, + "TESTOUT50": { + "direction": "OUT" + }, + "CLKOUT4": { + "direction": "OUT" + }, + "TESTIN11": { + "direction": "IN" + }, + "DO6": { + "direction": "OUT" + }, + "TESTOUT29": { + "direction": "OUT" + }, + "DADDR6": { + "direction": "IN" + }, + "PWRDWN": { + "direction": "IN" + }, + "DI15": { + "direction": "IN" + }, + "DO2": { + "direction": "OUT" + }, + "TESTOUT39": { + "direction": "OUT" + }, + "TESTOUT48": { + "direction": "OUT" + }, + "DO8": { + "direction": "OUT" + }, + "TESTIN26": { + "direction": "IN" + }, + "TESTIN13": { + "direction": "IN" + }, + "DI3": { + "direction": "IN" + }, + "TESTOUT30": { + "direction": "OUT" + }, + "TESTOUT25": { + "direction": "OUT" + }, + "TESTIN12": { + "direction": "IN" + }, + "TESTIN24": { + "direction": "IN" + }, + "TESTOUT60": { + "direction": "OUT" + }, + "TESTIN16": { + "direction": "IN" + }, + "TESTIN5": { + "direction": "IN" + }, + "TESTOUT45": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_PMV2.json b/kintex7/site_type_PMV2.json new file mode 100644 index 0000000..7252cbe --- /dev/null +++ b/kintex7/site_type_PMV2.json @@ -0,0 +1,27 @@ +{ + "type": "PMV2", + "site_pips": {}, + "site_pins": { + "A1": { + "direction": "IN" + }, + "EN": { + "direction": "IN" + }, + "ODIV2": { + "direction": "OUT" + }, + "ODIV4": { + "direction": "OUT" + }, + "A0": { + "direction": "IN" + }, + "A2": { + "direction": "IN" + }, + "O": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_RAMB18E1.json b/kintex7/site_type_RAMB18E1.json new file mode 100644 index 0000000..f06d5d4 --- /dev/null +++ b/kintex7/site_type_RAMB18E1.json @@ -0,0 +1,561 @@ +{ + "type": "RAMB18E1", + "site_pips": { + "RSTRAMBINV:RSTRAMB": { + "from_pin": "RSTRAMB", + "to_pin": "OUT" + }, + "RSTREGBINV:RSTREGB": { + "from_pin": "RSTREGB", + "to_pin": "OUT" + }, + "CLKBWRCLKINV:CLKBWRCLK": { + "from_pin": "CLKBWRCLK", + "to_pin": "OUT" + }, + "REGCLKARDRCLKINV:REGCLKARDRCLK_B": { + "from_pin": "REGCLKARDRCLK_B", + "to_pin": "OUT" + }, + "REGCLKBINV:REGCLKB": { + "from_pin": "REGCLKB", + "to_pin": "OUT" + }, + "ENARDENINV:ENARDEN": { + "from_pin": "ENARDEN", + "to_pin": "OUT" + }, + "REGCLKBINV:REGCLKB_B": { + "from_pin": "REGCLKB_B", + "to_pin": "OUT" + }, + "RSTREGARSTREGINV:RSTREGARSTREG_B": { + "from_pin": "RSTREGARSTREG_B", + "to_pin": "OUT" + }, + "REGCLKARDRCLKINV:REGCLKARDRCLK": { + "from_pin": "REGCLKARDRCLK", + "to_pin": "OUT" + }, + "ENBWRENINV:ENBWREN_B": { + "from_pin": "ENBWREN_B", + "to_pin": "OUT" + }, + "CLKARDCLKINV:CLKARDCLK_B": { + "from_pin": "CLKARDCLK_B", + "to_pin": "OUT" + }, + "CLKBWRCLKINV:CLKBWRCLK_B": { + "from_pin": "CLKBWRCLK_B", + "to_pin": "OUT" + }, + "RSTREGARSTREGINV:RSTREGARSTREG": { + "from_pin": "RSTREGARSTREG", + "to_pin": "OUT" + }, + "RSTRAMBINV:RSTRAMB_B": { + "from_pin": "RSTRAMB_B", + "to_pin": "OUT" + }, + "RSTREGBINV:RSTREGB_B": { + "from_pin": "RSTREGB_B", + "to_pin": "OUT" + }, + "CLKARDCLKINV:CLKARDCLK": { + "from_pin": "CLKARDCLK", + "to_pin": "OUT" + }, + "ENBWRENINV:ENBWREN": { + "from_pin": "ENBWREN", + "to_pin": "OUT" + }, + "RSTRAMARSTRAMINV:RSTRAMARSTRAM_B": { + "from_pin": "RSTRAMARSTRAM_B", + "to_pin": "OUT" + }, + "ENARDENINV:ENARDEN_B": { + "from_pin": "ENARDEN_B", + "to_pin": "OUT" + }, + "RSTRAMARSTRAMINV:RSTRAMARSTRAM": { + "from_pin": "RSTRAMARSTRAM", + "to_pin": "OUT" + } + }, + "site_pins": { + "DOADO5": { + "direction": "OUT" + }, + "DIADI6": { + "direction": "IN" + }, + "WEBWE5": { + "direction": "IN" + }, + "ADDRARDADDR8": { + "direction": "IN" + }, + "WRCOUNT0": { + "direction": "OUT" + }, + "ENBWREN": { + "direction": "IN" + }, + "DIADI15": { + "direction": "IN" + }, + "ADDRARDADDR5": { + "direction": "IN" + }, + "WEA1": { + "direction": "IN" + }, + "DOBDO11": { + "direction": "OUT" + }, + "DOPADOP1": { + "direction": "OUT" + }, + "DOPBDOP0": { + "direction": "OUT" + }, + "DOADO3": { + "direction": "OUT" + }, + "WEBWE7": { + "direction": "IN" + }, + "DOADO6": { + "direction": "OUT" + }, + "DOBDO12": { + "direction": "OUT" + }, + "ADDRARDADDR13": { + "direction": "IN" + }, + "DIADI13": { + "direction": "IN" + }, + "ADDRBWRADDR9": { + "direction": "IN" + }, + "DOADO4": { + "direction": "OUT" + }, + "DOBDO6": { + "direction": "OUT" + }, + "DOPADOP0": { + "direction": "OUT" + }, + "WRCOUNT4": { + "direction": "OUT" + }, + "ALMOSTEMPTY": { + "direction": "OUT" + }, + "WRCOUNT8": { + "direction": "OUT" + }, + "DIBDI4": { + "direction": "IN" + }, + "ADDRBWRADDR0": { + "direction": "IN" + }, + "ADDRBTIEHIGH1": { + "direction": "IN" + }, + "WEA2": { + "direction": "IN" + }, + "RDCOUNT7": { + "direction": "OUT" + }, + "DOBDO5": { + "direction": "OUT" + }, + "CLKBWRCLK": { + "direction": "IN" + }, + "RSTREGARSTREG": { + "direction": "IN" + }, + "DOADO0": { + "direction": "OUT" + }, + "DIBDI13": { + "direction": "IN" + }, + "DOADO9": { + "direction": "OUT" + }, + "DOBDO2": { + "direction": "OUT" + }, + "RDCOUNT1": { + "direction": "OUT" + }, + "DIBDI5": { + "direction": "IN" + }, + "ADDRATIEHIGH1": { + "direction": "IN" + }, + "DOADO11": { + "direction": "OUT" + }, + "WRCOUNT1": { + "direction": "OUT" + }, + "RDCOUNT10": { + "direction": "OUT" + }, + "DIBDI7": { + "direction": "IN" + }, + "RSTRAMB": { + "direction": "IN" + }, + "DIADI2": { + "direction": "IN" + }, + "DIADI5": { + "direction": "IN" + }, + "DIADI10": { + "direction": "IN" + }, + "DIADI7": { + "direction": "IN" + }, + "DIPBDIP1": { + "direction": "IN" + }, + "WEBWE4": { + "direction": "IN" + }, + "DOBDO13": { + "direction": "OUT" + }, + "RDCOUNT11": { + "direction": "OUT" + }, + "WEBWE0": { + "direction": "IN" + }, + "DOADO1": { + "direction": "OUT" + }, + "DOBDO10": { + "direction": "OUT" + }, + "ADDRBWRADDR13": { + "direction": "IN" + }, + "DOBDO7": { + "direction": "OUT" + }, + "ADDRBWRADDR1": { + "direction": "IN" + }, + "DIADI9": { + "direction": "IN" + }, + "RDCOUNT8": { + "direction": "OUT" + }, + "ADDRBWRADDR6": { + "direction": "IN" + }, + "ADDRBWRADDR10": { + "direction": "IN" + }, + "RSTREGB": { + "direction": "IN" + }, + "WRCOUNT10": { + "direction": "OUT" + }, + "ADDRARDADDR1": { + "direction": "IN" + }, + "DOBDO9": { + "direction": "OUT" + }, + "ADDRARDADDR10": { + "direction": "IN" + }, + "DOBDO3": { + "direction": "OUT" + }, + "REGCEAREGCE": { + "direction": "IN" + }, + "ADDRARDADDR12": { + "direction": "IN" + }, + "DIBDI1": { + "direction": "IN" + }, + "DIBDI6": { + "direction": "IN" + }, + "WEBWE2": { + "direction": "IN" + }, + "FULL": { + "direction": "OUT" + }, + "DIBDI9": { + "direction": "IN" + }, + "ADDRATIEHIGH0": { + "direction": "IN" + }, + "WRERR": { + "direction": "OUT" + }, + "ADDRBTIEHIGH0": { + "direction": "IN" + }, + "DOBDO14": { + "direction": "OUT" + }, + "WEA0": { + "direction": "IN" + }, + "RDCOUNT0": { + "direction": "OUT" + }, + "DIBDI2": { + "direction": "IN" + }, + "RDCOUNT5": { + "direction": "OUT" + }, + "RDERR": { + "direction": "OUT" + }, + "ADDRBWRADDR8": { + "direction": "IN" + }, + "ENARDEN": { + "direction": "IN" + }, + "DIADI0": { + "direction": "IN" + }, + "ADDRBWRADDR2": { + "direction": "IN" + }, + "DOADO10": { + "direction": "OUT" + }, + "DIBDI3": { + "direction": "IN" + }, + "WEBWE1": { + "direction": "IN" + }, + "DIPADIP1": { + "direction": "IN" + }, + "WRCOUNT11": { + "direction": "OUT" + }, + "DIBDI8": { + "direction": "IN" + }, + "WRCOUNT9": { + "direction": "OUT" + }, + "WRCOUNT2": { + "direction": "OUT" + }, + "DOADO13": { + "direction": "OUT" + }, + "WRCOUNT6": { + "direction": "OUT" + }, + "DIBDI11": { + "direction": "IN" + }, + "ADDRBWRADDR11": { + "direction": "IN" + }, + "ADDRARDADDR9": { + "direction": "IN" + }, + "REGCEB": { + "direction": "IN" + }, + "ALMOSTFULL": { + "direction": "OUT" + }, + "WEBWE3": { + "direction": "IN" + }, + "REGCLKARDRCLK": { + "direction": "IN" + }, + "RDCOUNT2": { + "direction": "OUT" + }, + "WRCOUNT5": { + "direction": "OUT" + }, + "DOADO15": { + "direction": "OUT" + }, + "ADDRARDADDR7": { + "direction": "IN" + }, + "ADDRARDADDR3": { + "direction": "IN" + }, + "DIPBDIP0": { + "direction": "IN" + }, + "DOPBDOP1": { + "direction": "OUT" + }, + "DIADI11": { + "direction": "IN" + }, + "ADDRBWRADDR4": { + "direction": "IN" + }, + "DIADI12": { + "direction": "IN" + }, + "EMPTY": { + "direction": "OUT" + }, + "RDCOUNT6": { + "direction": "OUT" + }, + "ADDRARDADDR11": { + "direction": "IN" + }, + "DOADO12": { + "direction": "OUT" + }, + "RDCOUNT4": { + "direction": "OUT" + }, + "DIADI4": { + "direction": "IN" + }, + "RSTRAMARSTRAM": { + "direction": "IN" + }, + "DIADI8": { + "direction": "IN" + }, + "RDCOUNT9": { + "direction": "OUT" + }, + "DOBDO15": { + "direction": "OUT" + }, + "ADDRARDADDR2": { + "direction": "IN" + }, + "ADDRBWRADDR7": { + "direction": "IN" + }, + "WRCOUNT7": { + "direction": "OUT" + }, + "DOBDO8": { + "direction": "OUT" + }, + "DIADI1": { + "direction": "IN" + }, + "ADDRARDADDR4": { + "direction": "IN" + }, + "WRCOUNT3": { + "direction": "OUT" + }, + "DOADO14": { + "direction": "OUT" + }, + "CLKARDCLK": { + "direction": "IN" + }, + "WEA3": { + "direction": "IN" + }, + "DIADI14": { + "direction": "IN" + }, + "DOBDO4": { + "direction": "OUT" + }, + "ADDRBWRADDR5": { + "direction": "IN" + }, + "ADDRBWRADDR3": { + "direction": "IN" + }, + "DOBDO0": { + "direction": "OUT" + }, + "DIPADIP0": { + "direction": "IN" + }, + "WEBWE6": { + "direction": "IN" + }, + "DIBDI0": { + "direction": "IN" + }, + "ADDRBWRADDR12": { + "direction": "IN" + }, + "REGCLKB": { + "direction": "IN" + }, + "DOADO7": { + "direction": "OUT" + }, + "DOADO8": { + "direction": "OUT" + }, + "DIBDI15": { + "direction": "IN" + }, + "DOBDO1": { + "direction": "OUT" + }, + "ADDRARDADDR6": { + "direction": "IN" + }, + "DOADO2": { + "direction": "OUT" + }, + "DIBDI14": { + "direction": "IN" + }, + "DIBDI12": { + "direction": "IN" + }, + "DIADI3": { + "direction": "IN" + }, + "RDCOUNT3": { + "direction": "OUT" + }, + "ADDRARDADDR0": { + "direction": "IN" + }, + "DIBDI10": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_RAMBFIFO36E1.json b/kintex7/site_type_RAMBFIFO36E1.json new file mode 100644 index 0000000..730c82f --- /dev/null +++ b/kintex7/site_type_RAMBFIFO36E1.json @@ -0,0 +1,1235 @@ +{ + "type": "RAMBFIFO36E1", + "site_pips": { + "REGCLKBUINV:REGCLKBU": { + "from_pin": "REGCLKBU", + "to_pin": "OUT" + }, + "REGCLKARDRCLKLINV:REGCLKARDRCLKL_B": { + "from_pin": "REGCLKARDRCLKL_B", + "to_pin": "OUT" + }, + "REGCLKBUINV:REGCLKBU_B": { + "from_pin": "REGCLKBU_B", + "to_pin": "OUT" + }, + "ENBWRENUINV:ENBWRENU": { + "from_pin": "ENBWRENU", + "to_pin": "OUT" + }, + "RSTRAMARSTRAMUINV:RSTRAMARSTRAMU": { + "from_pin": "RSTRAMARSTRAMU", + "to_pin": "OUT" + }, + "REGCLKARDRCLKLINV:REGCLKARDRCLKL": { + "from_pin": "REGCLKARDRCLKL", + "to_pin": "OUT" + }, + "CLKARDCLKUINV:CLKARDCLKU_B": { + "from_pin": "CLKARDCLKU_B", + "to_pin": "OUT" + }, + "RSTREGBUINV:RSTREGBU_B": { + "from_pin": "RSTREGBU_B", + "to_pin": "OUT" + }, + "RSTRAMARSTRAMLRSTINV:RSTRAMARSTRAMLRST": { + "from_pin": "RSTRAMARSTRAMLRST", + "to_pin": "OUT" + }, + "RSTREGARSTREGUINV:RSTREGARSTREGU_B": { + "from_pin": "RSTREGARSTREGU_B", + "to_pin": "OUT" + }, + "CLKBWRCLKUINV:CLKBWRCLKU_B": { + "from_pin": "CLKBWRCLKU_B", + "to_pin": "OUT" + }, + "RSTREGBLINV:RSTREGBL": { + "from_pin": "RSTREGBL", + "to_pin": "OUT" + }, + "CLKBWRCLKLINV:CLKBWRCLKL_B": { + "from_pin": "CLKBWRCLKL_B", + "to_pin": "OUT" + }, + "ENARDENLINV:ENARDENL_B": { + "from_pin": "ENARDENL_B", + "to_pin": "OUT" + }, + "RSTREGARSTREGUINV:RSTREGARSTREGU": { + "from_pin": "RSTREGARSTREGU", + "to_pin": "OUT" + }, + "RSTREGARSTREGLINV:RSTREGARSTREGL_B": { + "from_pin": "RSTREGARSTREGL_B", + "to_pin": "OUT" + }, + "ENBWRENLINV:ENBWRENL": { + "from_pin": "ENBWRENL", + "to_pin": "OUT" + }, + "RSTREGARSTREGLINV:RSTREGARSTREGL": { + "from_pin": "RSTREGARSTREGL", + "to_pin": "OUT" + }, + "REGCLKARDRCLKUINV:REGCLKARDRCLKU": { + "from_pin": "REGCLKARDRCLKU", + "to_pin": "OUT" + }, + "CLKARDCLKLINV:CLKARDCLKL_B": { + "from_pin": "CLKARDCLKL_B", + "to_pin": "OUT" + }, + "CLKARDCLKLINV:CLKARDCLKL": { + "from_pin": "CLKARDCLKL", + "to_pin": "OUT" + }, + "REGCLKBLINV:REGCLKBL_B": { + "from_pin": "REGCLKBL_B", + "to_pin": "OUT" + }, + "CLKBWRCLKLINV:CLKBWRCLKL": { + "from_pin": "CLKBWRCLKL", + "to_pin": "OUT" + }, + "RSTRAMBUINV:RSTRAMBU": { + "from_pin": "RSTRAMBU", + "to_pin": "OUT" + }, + "ENARDENLINV:ENARDENL": { + "from_pin": "ENARDENL", + "to_pin": "OUT" + }, + "RSTRAMARSTRAMUINV:RSTRAMARSTRAMU_B": { + "from_pin": "RSTRAMARSTRAMU_B", + "to_pin": "OUT" + }, + "ENARDENUINV:ENARDENU": { + "from_pin": "ENARDENU", + "to_pin": "OUT" + }, + "RSTREGBLINV:RSTREGBL_B": { + "from_pin": "RSTREGBL_B", + "to_pin": "OUT" + }, + "CLKARDCLKUINV:CLKARDCLKU": { + "from_pin": "CLKARDCLKU", + "to_pin": "OUT" + }, + "RSTRAMBUINV:RSTRAMBU_B": { + "from_pin": "RSTRAMBU_B", + "to_pin": "OUT" + }, + "RSTRAMBLINV:RSTRAMBL": { + "from_pin": "RSTRAMBL", + "to_pin": "OUT" + }, + "RSTREGBUINV:RSTREGBU": { + "from_pin": "RSTREGBU", + "to_pin": "OUT" + }, + "REGCLKARDRCLKUINV:REGCLKARDRCLKU_B": { + "from_pin": "REGCLKARDRCLKU_B", + "to_pin": "OUT" + }, + "ENBWRENUINV:ENBWRENU_B": { + "from_pin": "ENBWRENU_B", + "to_pin": "OUT" + }, + "REGCLKBLINV:REGCLKBL": { + "from_pin": "REGCLKBL", + "to_pin": "OUT" + }, + "ENBWRENLINV:ENBWRENL_B": { + "from_pin": "ENBWRENL_B", + "to_pin": "OUT" + }, + "RSTRAMBLINV:RSTRAMBL_B": { + "from_pin": "RSTRAMBL_B", + "to_pin": "OUT" + }, + "CLKBWRCLKUINV:CLKBWRCLKU": { + "from_pin": "CLKBWRCLKU", + "to_pin": "OUT" + }, + "ENARDENUINV:ENARDENU_B": { + "from_pin": "ENARDENU_B", + "to_pin": "OUT" + }, + "RSTRAMARSTRAMLRSTINV:RSTRAMARSTRAMLRST_B": { + "from_pin": "RSTRAMARSTRAMLRST_B", + "to_pin": "OUT" + } + }, + "site_pins": { + "DOADO5": { + "direction": "OUT" + }, + "DIADI6": { + "direction": "IN" + }, + "WEAL3": { + "direction": "IN" + }, + "WRCOUNT0": { + "direction": "OUT" + }, + "CLKARDCLKU": { + "direction": "IN" + }, + "DOBDO21": { + "direction": "OUT" + }, + "WEAU1": { + "direction": "IN" + }, + "DOADO16": { + "direction": "OUT" + }, + "DIBDI29": { + "direction": "IN" + }, + "DOBDO26": { + "direction": "OUT" + }, + "ADDRARDADDRU9": { + "direction": "IN" + }, + "WEBWEL5": { + "direction": "IN" + }, + "TSTIN3": { + "direction": "IN" + }, + "WRCOUNT8": { + "direction": "OUT" + }, + "RSTREGBU": { + "direction": "IN" + }, + "DOADO17": { + "direction": "OUT" + }, + "ADDRARDADDRU3": { + "direction": "IN" + }, + "RDCOUNT5": { + "direction": "OUT" + }, + "DIBDI16": { + "direction": "IN" + }, + "DIBDI13": { + "direction": "IN" + }, + "DIBDI24": { + "direction": "IN" + }, + "ADDRARDADDRL0": { + "direction": "IN" + }, + "WEBWEU7": { + "direction": "IN" + }, + "DBITERR": { + "direction": "OUT" + }, + "TSTWROS7": { + "direction": "IN" + }, + "ADDRBWRADDRL3": { + "direction": "IN" + }, + "WEAL1": { + "direction": "IN" + }, + "TSTCNT7": { + "direction": "IN" + }, + "TSTWROS9": { + "direction": "IN" + }, + "WEAU3": { + "direction": "IN" + }, + "RDCOUNT11": { + "direction": "OUT" + }, + "ADDRARDADDRL12": { + "direction": "IN" + }, + "WEBWEU4": { + "direction": "IN" + }, + "DOADO23": { + "direction": "OUT" + }, + "TSTOUT1": { + "direction": "OUT" + }, + "TSTWROS6": { + "direction": "IN" + }, + "DIADI9": { + "direction": "IN" + }, + "DOBDO28": { + "direction": "OUT" + }, + "WRCOUNT10": { + "direction": "OUT" + }, + "ECCPARITY3": { + "direction": "OUT" + }, + "DOBDO22": { + "direction": "OUT" + }, + "DIBDI1": { + "direction": "IN" + }, + "TSTRDOS7": { + "direction": "IN" + }, + "DOADO14": { + "direction": "OUT" + }, + "DOADO27": { + "direction": "OUT" + }, + "TSTWROS0": { + "direction": "IN" + }, + "ADDRBWRADDRU2": { + "direction": "IN" + }, + "ECCPARITY6": { + "direction": "OUT" + }, + "DOADO18": { + "direction": "OUT" + }, + "DIBDI27": { + "direction": "IN" + }, + "WEAU2": { + "direction": "IN" + }, + "DOBDO29": { + "direction": "OUT" + }, + "TSTRDOS10": { + "direction": "IN" + }, + "DIADI4": { + "direction": "IN" + }, + "DOBDO27": { + "direction": "OUT" + }, + "TSTOUT2": { + "direction": "OUT" + }, + "ADDRBWRADDRU10": { + "direction": "IN" + }, + "RSTRAMBL": { + "direction": "IN" + }, + "RSTRAMARSTRAMU": { + "direction": "IN" + }, + "DIADI22": { + "direction": "IN" + }, + "DOPBDOP1": { + "direction": "OUT" + }, + "DIBDI26": { + "direction": "IN" + }, + "DOADO24": { + "direction": "OUT" + }, + "INJECTDBITERR": { + "direction": "IN" + }, + "TSTWROS2": { + "direction": "IN" + }, + "DOADO26": { + "direction": "OUT" + }, + "DIADI30": { + "direction": "IN" + }, + "INJECTSBITERR": { + "direction": "IN" + }, + "DOBDO17": { + "direction": "OUT" + }, + "ADDRARDADDRL11": { + "direction": "IN" + }, + "ADDRARDADDRL3": { + "direction": "IN" + }, + "WRCOUNT3": { + "direction": "OUT" + }, + "TSTWROS10": { + "direction": "IN" + }, + "TSTRDOS9": { + "direction": "IN" + }, + "RSTRAMBU": { + "direction": "IN" + }, + "TSTOFF": { + "direction": "IN" + }, + "ECCPARITY2": { + "direction": "OUT" + }, + "DOBDO0": { + "direction": "OUT" + }, + "TSTRDOS8": { + "direction": "IN" + }, + "ADDRARDADDRU11": { + "direction": "IN" + }, + "DOADO7": { + "direction": "OUT" + }, + "TSTRDOS11": { + "direction": "IN" + }, + "DIADI28": { + "direction": "IN" + }, + "DOADO28": { + "direction": "OUT" + }, + "DIPBDIP2": { + "direction": "IN" + }, + "ADDRBWRADDRU4": { + "direction": "IN" + }, + "WEBWEL2": { + "direction": "IN" + }, + "WEAU0": { + "direction": "IN" + }, + "TSTCNT8": { + "direction": "IN" + }, + "WEBWEL3": { + "direction": "IN" + }, + "DIBDI20": { + "direction": "IN" + }, + "TSTRDOS4": { + "direction": "IN" + }, + "ADDRARDADDRL6": { + "direction": "IN" + }, + "DOADO3": { + "direction": "OUT" + }, + "RSTREGARSTREGU": { + "direction": "IN" + }, + "DOADO6": { + "direction": "OUT" + }, + "DOADO10": { + "direction": "OUT" + }, + "DIBDI9": { + "direction": "IN" + }, + "DOBDO6": { + "direction": "OUT" + }, + "DOPADOP0": { + "direction": "OUT" + }, + "ALMOSTEMPTY": { + "direction": "OUT" + }, + "DIBDI5": { + "direction": "IN" + }, + "DIADI14": { + "direction": "IN" + }, + "ADDRBWRADDRU5": { + "direction": "IN" + }, + "DIBDI23": { + "direction": "IN" + }, + "ADDRBWRADDRU13": { + "direction": "IN" + }, + "ADDRBWRADDRU6": { + "direction": "IN" + }, + "DOBDO5": { + "direction": "OUT" + }, + "RDCOUNT12": { + "direction": "OUT" + }, + "ADDRARDADDRU1": { + "direction": "IN" + }, + "ADDRARDADDRU4": { + "direction": "IN" + }, + "DOBDO23": { + "direction": "OUT" + }, + "DIBDI14": { + "direction": "IN" + }, + "RDCOUNT10": { + "direction": "OUT" + }, + "DIPBDIP1": { + "direction": "IN" + }, + "REGCLKARDRCLKU": { + "direction": "IN" + }, + "DOBDO10": { + "direction": "OUT" + }, + "WRCOUNT11": { + "direction": "OUT" + }, + "DOBDO7": { + "direction": "OUT" + }, + "DOADO9": { + "direction": "OUT" + }, + "TSTRDOS2": { + "direction": "IN" + }, + "ADDRARDADDRU7": { + "direction": "IN" + }, + "WEBWEU5": { + "direction": "IN" + }, + "DIBDI2": { + "direction": "IN" + }, + "DIBDI22": { + "direction": "IN" + }, + "DIBDI21": { + "direction": "IN" + }, + "DIBDI6": { + "direction": "IN" + }, + "DIBDI19": { + "direction": "IN" + }, + "CLKBWRCLKU": { + "direction": "IN" + }, + "DIBDI17": { + "direction": "IN" + }, + "DOBDO14": { + "direction": "OUT" + }, + "RDCOUNT0": { + "direction": "OUT" + }, + "DOBDO12": { + "direction": "OUT" + }, + "WRERR": { + "direction": "OUT" + }, + "DIADI24": { + "direction": "IN" + }, + "ADDRARDADDRU12": { + "direction": "IN" + }, + "DOADO11": { + "direction": "OUT" + }, + "TSTCNT10": { + "direction": "IN" + }, + "TSTCNT5": { + "direction": "IN" + }, + "DIBDI11": { + "direction": "IN" + }, + "TSTCNT0": { + "direction": "IN" + }, + "TSTWRCNTOFF": { + "direction": "IN" + }, + "REGCEAREGCEL": { + "direction": "IN" + }, + "ALMOSTFULL": { + "direction": "OUT" + }, + "ADDRBWRADDRU7": { + "direction": "IN" + }, + "DOPADOP3": { + "direction": "OUT" + }, + "DIPADIP3": { + "direction": "IN" + }, + "DIADI11": { + "direction": "IN" + }, + "REGCLKBL": { + "direction": "IN" + }, + "REGCLKARDRCLKL": { + "direction": "IN" + }, + "ADDRBWRADDRL6": { + "direction": "IN" + }, + "REGCEAREGCEU": { + "direction": "IN" + }, + "EMPTY": { + "direction": "OUT" + }, + "ENARDENU": { + "direction": "IN" + }, + "ADDRARDADDRU2": { + "direction": "IN" + }, + "DOBDO19": { + "direction": "OUT" + }, + "TSTRDOS12": { + "direction": "IN" + }, + "RDCOUNT9": { + "direction": "OUT" + }, + "DOBDO8": { + "direction": "OUT" + }, + "ENARDENL": { + "direction": "IN" + }, + "DOBDO31": { + "direction": "OUT" + }, + "DOADO2": { + "direction": "OUT" + }, + "TSTCNT1": { + "direction": "IN" + }, + "DOBDO20": { + "direction": "OUT" + }, + "ECCPARITY4": { + "direction": "OUT" + }, + "DIPADIP0": { + "direction": "IN" + }, + "RSTRAMARSTRAMLRST": { + "direction": "IN" + }, + "DIADI31": { + "direction": "IN" + }, + "WEBWEL1": { + "direction": "IN" + }, + "TSTWROS4": { + "direction": "IN" + }, + "DOADO19": { + "direction": "OUT" + }, + "ADDRBWRADDRU3": { + "direction": "IN" + }, + "REGCEBU": { + "direction": "IN" + }, + "RDCOUNT3": { + "direction": "OUT" + }, + "TSTWROS11": { + "direction": "IN" + }, + "DIBDI10": { + "direction": "IN" + }, + "ADDRBWRADDRU11": { + "direction": "IN" + }, + "WEBWEL6": { + "direction": "IN" + }, + "WEBWEL4": { + "direction": "IN" + }, + "DOADO29": { + "direction": "OUT" + }, + "ADDRARDADDRL8": { + "direction": "IN" + }, + "DIADI10": { + "direction": "IN" + }, + "DIADI26": { + "direction": "IN" + }, + "FULL": { + "direction": "OUT" + }, + "TSTFLAGIN": { + "direction": "IN" + }, + "DOADO22": { + "direction": "OUT" + }, + "ADDRARDADDRL1": { + "direction": "IN" + }, + "DOADO1": { + "direction": "OUT" + }, + "CASCADEOUTA": { + "direction": "OUT" + }, + "DIADI1": { + "direction": "IN" + }, + "DIBDI12": { + "direction": "IN" + }, + "ADDRARDADDRU5": { + "direction": "IN" + }, + "WEBWEU3": { + "direction": "IN" + }, + "DIBDI25": { + "direction": "IN" + }, + "TSTIN2": { + "direction": "IN" + }, + "RDCOUNT7": { + "direction": "OUT" + }, + "DIBDI30": { + "direction": "IN" + }, + "DOADO0": { + "direction": "OUT" + }, + "WEBWEU6": { + "direction": "IN" + }, + "RDCOUNT1": { + "direction": "OUT" + }, + "ADDRBWRADDRL8": { + "direction": "IN" + }, + "ADDRARDADDRL4": { + "direction": "IN" + }, + "ECCPARITY0": { + "direction": "OUT" + }, + "DIADI19": { + "direction": "IN" + }, + "DIBDI7": { + "direction": "IN" + }, + "DIADI2": { + "direction": "IN" + }, + "DIADI5": { + "direction": "IN" + }, + "ADDRARDADDRL5": { + "direction": "IN" + }, + "DIADI7": { + "direction": "IN" + }, + "WEBWEL7": { + "direction": "IN" + }, + "DOBDO13": { + "direction": "OUT" + }, + "DIADI0": { + "direction": "IN" + }, + "TSTIN1": { + "direction": "IN" + }, + "ADDRBWRADDRU8": { + "direction": "IN" + }, + "DOADO21": { + "direction": "OUT" + }, + "TSTWROS12": { + "direction": "IN" + }, + "ECCPARITY1": { + "direction": "OUT" + }, + "DOBDO9": { + "direction": "OUT" + }, + "TSTRDOS6": { + "direction": "IN" + }, + "DOBDO18": { + "direction": "OUT" + }, + "TSTIN4": { + "direction": "IN" + }, + "TSTOUT0": { + "direction": "OUT" + }, + "ADDRARDADDRU6": { + "direction": "IN" + }, + "DOADO31": { + "direction": "OUT" + }, + "DOPBDOP0": { + "direction": "OUT" + }, + "ADDRARDADDRL15": { + "direction": "IN" + }, + "ADDRBWRADDRL10": { + "direction": "IN" + }, + "TSTWROS1": { + "direction": "IN" + }, + "ADDRBWRADDRL0": { + "direction": "IN" + }, + "DIBDI3": { + "direction": "IN" + }, + "ADDRBWRADDRU9": { + "direction": "IN" + }, + "TSTRDOS5": { + "direction": "IN" + }, + "DIADI25": { + "direction": "IN" + }, + "DOADO13": { + "direction": "OUT" + }, + "WRCOUNT6": { + "direction": "OUT" + }, + "ADDRBWRADDRL7": { + "direction": "IN" + }, + "WEBWEU0": { + "direction": "IN" + }, + "WEBWEU1": { + "direction": "IN" + }, + "ENBWRENU": { + "direction": "IN" + }, + "DIADI8": { + "direction": "IN" + }, + "DIADI21": { + "direction": "IN" + }, + "RDCOUNT2": { + "direction": "OUT" + }, + "WRCOUNT5": { + "direction": "OUT" + }, + "DOADO15": { + "direction": "OUT" + }, + "DIBDI18": { + "direction": "IN" + }, + "CLKBWRCLKL": { + "direction": "IN" + }, + "DOBDO30": { + "direction": "OUT" + }, + "ADDRBWRADDRU14": { + "direction": "IN" + }, + "TSTCNT11": { + "direction": "IN" + }, + "ENBWRENL": { + "direction": "IN" + }, + "DIADI12": { + "direction": "IN" + }, + "DIADI23": { + "direction": "IN" + }, + "ADDRBWRADDRL5": { + "direction": "IN" + }, + "DIADI18": { + "direction": "IN" + }, + "CASCADEOUTB": { + "direction": "OUT" + }, + "DOBDO16": { + "direction": "OUT" + }, + "WEBWEU2": { + "direction": "IN" + }, + "RDCOUNT8": { + "direction": "OUT" + }, + "REGCEBL": { + "direction": "IN" + }, + "DIBDI0": { + "direction": "IN" + }, + "WEAL2": { + "direction": "IN" + }, + "DOADO25": { + "direction": "OUT" + }, + "DIPADIP2": { + "direction": "IN" + }, + "DOBDO1": { + "direction": "OUT" + }, + "DIBDI28": { + "direction": "IN" + }, + "TSTOUT3": { + "direction": "OUT" + }, + "DIADI3": { + "direction": "IN" + }, + "RSTREGBL": { + "direction": "IN" + }, + "TSTCNT9": { + "direction": "IN" + }, + "TSTWROS3": { + "direction": "IN" + }, + "DIADI17": { + "direction": "IN" + }, + "ADDRARDADDRU13": { + "direction": "IN" + }, + "ADDRBWRADDRL15": { + "direction": "IN" + }, + "ECCPARITY7": { + "direction": "OUT" + }, + "ADDRBWRADDRU12": { + "direction": "IN" + }, + "DOBDO11": { + "direction": "OUT" + }, + "DOPADOP1": { + "direction": "OUT" + }, + "ADDRARDADDRL14": { + "direction": "IN" + }, + "DIBDI8": { + "direction": "IN" + }, + "ADDRARDADDRL9": { + "direction": "IN" + }, + "DIADI13": { + "direction": "IN" + }, + "RDCOUNT6": { + "direction": "OUT" + }, + "DIADI16": { + "direction": "IN" + }, + "DOADO4": { + "direction": "OUT" + }, + "DIADI15": { + "direction": "IN" + }, + "WRCOUNT4": { + "direction": "OUT" + }, + "DOADO8": { + "direction": "OUT" + }, + "TSTRDOS3": { + "direction": "IN" + }, + "TSTCNT3": { + "direction": "IN" + }, + "TSTCNT12": { + "direction": "IN" + }, + "CASCADEINA": { + "direction": "IN" + }, + "WEBWEL0": { + "direction": "IN" + }, + "WRCOUNT1": { + "direction": "OUT" + }, + "DIADI27": { + "direction": "IN" + }, + "ADDRBWRADDRL12": { + "direction": "IN" + }, + "DOPADOP2": { + "direction": "OUT" + }, + "WRCOUNT7": { + "direction": "OUT" + }, + "DIPBDIP3": { + "direction": "IN" + }, + "ECCPARITY5": { + "direction": "OUT" + }, + "ADDRBWRADDRL4": { + "direction": "IN" + }, + "DOPBDOP2": { + "direction": "OUT" + }, + "DOBDO2": { + "direction": "OUT" + }, + "DIBDI4": { + "direction": "IN" + }, + "WRCOUNT12": { + "direction": "OUT" + }, + "ADDRARDADDRU14": { + "direction": "IN" + }, + "RSTREGARSTREGL": { + "direction": "IN" + }, + "DOBDO3": { + "direction": "OUT" + }, + "TSTOUT4": { + "direction": "OUT" + }, + "CASCADEINB": { + "direction": "IN" + }, + "ADDRBWRADDRL14": { + "direction": "IN" + }, + "DOBDO15": { + "direction": "OUT" + }, + "ADDRBWRADDRL11": { + "direction": "IN" + }, + "WEAL0": { + "direction": "IN" + }, + "DOADO30": { + "direction": "OUT" + }, + "REGCLKBU": { + "direction": "IN" + }, + "TSTWROS5": { + "direction": "IN" + }, + "RDERR": { + "direction": "OUT" + }, + "TSTCNT4": { + "direction": "IN" + }, + "TSTBRAMRST": { + "direction": "IN" + }, + "DIPADIP1": { + "direction": "IN" + }, + "WRCOUNT9": { + "direction": "OUT" + }, + "ADDRARDADDRU0": { + "direction": "IN" + }, + "WRCOUNT2": { + "direction": "OUT" + }, + "ADDRBWRADDRL9": { + "direction": "IN" + }, + "ADDRARDADDRL10": { + "direction": "IN" + }, + "DIPBDIP0": { + "direction": "IN" + }, + "ADDRARDADDRL13": { + "direction": "IN" + }, + "DIADI29": { + "direction": "IN" + }, + "TSTIN0": { + "direction": "IN" + }, + "DIBDI31": { + "direction": "IN" + }, + "DOBDO25": { + "direction": "OUT" + }, + "DOBDO24": { + "direction": "OUT" + }, + "TSTCNT2": { + "direction": "IN" + }, + "ADDRBWRADDRL13": { + "direction": "IN" + }, + "ADDRBWRADDRL2": { + "direction": "IN" + }, + "TSTRDOS1": { + "direction": "IN" + }, + "DOADO12": { + "direction": "OUT" + }, + "RDCOUNT4": { + "direction": "OUT" + }, + "ADDRARDADDRL7": { + "direction": "IN" + }, + "DIADI20": { + "direction": "IN" + }, + "ADDRARDADDRU10": { + "direction": "IN" + }, + "SBITERR": { + "direction": "OUT" + }, + "ADDRBWRADDRU0": { + "direction": "IN" + }, + "TSTCNT6": { + "direction": "IN" + }, + "DOBDO4": { + "direction": "OUT" + }, + "TSTRDOS0": { + "direction": "IN" + }, + "CLKARDCLKL": { + "direction": "IN" + }, + "ADDRBWRADDRL1": { + "direction": "IN" + }, + "DIBDI15": { + "direction": "IN" + }, + "DOADO20": { + "direction": "OUT" + }, + "ADDRARDADDRU8": { + "direction": "IN" + }, + "ADDRARDADDRL2": { + "direction": "IN" + }, + "DOPBDOP3": { + "direction": "OUT" + }, + "TSTRDCNTOFF": { + "direction": "IN" + }, + "ADDRBWRADDRU1": { + "direction": "IN" + }, + "TSTWROS8": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_SLICEL.json b/kintex7/site_type_SLICEL.json new file mode 100644 index 0000000..ccbf17d --- /dev/null +++ b/kintex7/site_type_SLICEL.json @@ -0,0 +1,694 @@ +{ + "type": "SLICEL", + "site_pips": { + "DOUTMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "A5FFMUX:IN_A": { + "from_pin": "IN_A", + "to_pin": "OUT" + }, + "B6LUT:A4": { + "from_pin": "A4", + "to_pin": "O6" + }, + "D5LUT:A3": { + "from_pin": "A3", + "to_pin": "O5" + }, + "A6LUT:A4": { + "from_pin": "A4", + "to_pin": "O6" + }, + "C5LUT:A5": { + "from_pin": "A5", + "to_pin": "O5" + }, + "D6LUT:A4": { + "from_pin": "A4", + "to_pin": "O6" + }, + "A5LUT:A5": { + "from_pin": "A5", + "to_pin": "O5" + }, + "A6LUT:A2": { + "from_pin": "A2", + "to_pin": "O6" + }, + "AOUTMUX:A5Q": { + "from_pin": "A5Q", + "to_pin": "OUT" + }, + "D6LUT:A5": { + "from_pin": "A5", + "to_pin": "O6" + }, + "BCY0:BX": { + "from_pin": "BX", + "to_pin": "OUT" + }, + "CCY0:CX": { + "from_pin": "CX", + "to_pin": "OUT" + }, + "AOUTMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "AFFMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "SRUSEDMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "DFFMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "A5LUT:A3": { + "from_pin": "A3", + "to_pin": "O5" + }, + "BOUTMUX:B5Q": { + "from_pin": "B5Q", + "to_pin": "OUT" + }, + "BOUTMUX:F8": { + "from_pin": "F8", + "to_pin": "OUT" + }, + "DFFMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "DOUTMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "AFFMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "DFFMUX:DX": { + "from_pin": "DX", + "to_pin": "OUT" + }, + "BUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "DOUTMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "BFFMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "BFFMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "BFFMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "D5LUT:A4": { + "from_pin": "A4", + "to_pin": "O5" + }, + "D5LUT:A2": { + "from_pin": "A2", + "to_pin": "O5" + }, + "COUTMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "D6LUT:A1": { + "from_pin": "A1", + "to_pin": "O6" + }, + "CLKINV:CLK_B": { + "from_pin": "CLK_B", + "to_pin": "OUT" + }, + "B6LUT:A1": { + "from_pin": "A1", + "to_pin": "O6" + }, + "BOUTMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "AOUTMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "B6LUT:A6": { + "from_pin": "A6", + "to_pin": "O6" + }, + "C6LUT:A4": { + "from_pin": "A4", + "to_pin": "O6" + }, + "C6LUT:A1": { + "from_pin": "A1", + "to_pin": "O6" + }, + "BOUTMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "B5FFMUX:IN_B": { + "from_pin": "IN_B", + "to_pin": "OUT" + }, + "CFFMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "DFFMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "D5FFMUX:IN_B": { + "from_pin": "IN_B", + "to_pin": "OUT" + }, + "AFFMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "ACY0:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "CFFMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "BOUTMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "DOUTMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "DOUTMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "DFFMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "A6LUT:A6": { + "from_pin": "A6", + "to_pin": "O6" + }, + "DOUTMUX:D5Q": { + "from_pin": "D5Q", + "to_pin": "OUT" + }, + "PRECYINIT:CIN": { + "from_pin": "CIN", + "to_pin": "OUT" + }, + "AOUTMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "DCY0:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "A5LUT:A2": { + "from_pin": "A2", + "to_pin": "O5" + }, + "A5LUT:A1": { + "from_pin": "A1", + "to_pin": "O5" + }, + "C5LUT:A3": { + "from_pin": "A3", + "to_pin": "O5" + }, + "PRECYINIT:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "B6LUT:A2": { + "from_pin": "A2", + "to_pin": "O6" + }, + "A6LUT:A3": { + "from_pin": "A3", + "to_pin": "O6" + }, + "BOUTMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "PRECYINIT:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "ACY0:AX": { + "from_pin": "AX", + "to_pin": "OUT" + }, + "C5FFMUX:IN_A": { + "from_pin": "IN_A", + "to_pin": "OUT" + }, + "COUTUSED:CARRY4_0": { + "from_pin": "CARRY4_0", + "to_pin": "OUT" + }, + "B5LUT:A4": { + "from_pin": "A4", + "to_pin": "O5" + }, + "CFFMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "D5LUT:A5": { + "from_pin": "A5", + "to_pin": "O5" + }, + "C5FFMUX:IN_B": { + "from_pin": "IN_B", + "to_pin": "OUT" + }, + "BFFMUX:F8": { + "from_pin": "F8", + "to_pin": "OUT" + }, + "BFFMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "AOUTMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "CFFMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "DUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "AFFMUX:AX": { + "from_pin": "AX", + "to_pin": "OUT" + }, + "AFFMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "SRUSEDMUX:IN": { + "from_pin": "IN", + "to_pin": "OUT" + }, + "B6LUT:A3": { + "from_pin": "A3", + "to_pin": "O6" + }, + "AOUTMUX:F7": { + "from_pin": "F7", + "to_pin": "OUT" + }, + "C5LUT:A4": { + "from_pin": "A4", + "to_pin": "O5" + }, + "BFFMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "AFFMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "A5LUT:A4": { + "from_pin": "A4", + "to_pin": "O5" + }, + "C6LUT:A3": { + "from_pin": "A3", + "to_pin": "O6" + }, + "DFFMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "DOUTMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "B5LUT:A5": { + "from_pin": "A5", + "to_pin": "O5" + }, + "D6LUT:A3": { + "from_pin": "A3", + "to_pin": "O6" + }, + "CCY0:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "C5LUT:A1": { + "from_pin": "A1", + "to_pin": "O5" + }, + "COUTMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "CFFMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "BFFMUX:BX": { + "from_pin": "BX", + "to_pin": "OUT" + }, + "CFFMUX:F7": { + "from_pin": "F7", + "to_pin": "OUT" + }, + "COUTMUX:C5Q": { + "from_pin": "C5Q", + "to_pin": "OUT" + }, + "AFFMUX:F7": { + "from_pin": "F7", + "to_pin": "OUT" + }, + "AOUTMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "D6LUT:A2": { + "from_pin": "A2", + "to_pin": "O6" + }, + "B5LUT:A1": { + "from_pin": "A1", + "to_pin": "O5" + }, + "B5LUT:A2": { + "from_pin": "A2", + "to_pin": "O5" + }, + "AUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "C6LUT:A2": { + "from_pin": "A2", + "to_pin": "O6" + }, + "PRECYINIT:AX": { + "from_pin": "AX", + "to_pin": "OUT" + }, + "BCY0:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "BFFMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "CEUSEDMUX:IN": { + "from_pin": "IN", + "to_pin": "OUT" + }, + "CFFMUX:CX": { + "from_pin": "CX", + "to_pin": "OUT" + }, + "C6LUT:A6": { + "from_pin": "A6", + "to_pin": "O6" + }, + "D5LUT:A1": { + "from_pin": "A1", + "to_pin": "O5" + }, + "D5FFMUX:IN_A": { + "from_pin": "IN_A", + "to_pin": "OUT" + }, + "COUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "A6LUT:A1": { + "from_pin": "A1", + "to_pin": "O6" + }, + "B6LUT:A5": { + "from_pin": "A5", + "to_pin": "O6" + }, + "CFFMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "A6LUT:A5": { + "from_pin": "A5", + "to_pin": "O6" + }, + "D6LUT:A6": { + "from_pin": "A6", + "to_pin": "O6" + }, + "CLKINV:CLK": { + "from_pin": "CLK", + "to_pin": "OUT" + }, + "COUTMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "A5FFMUX:IN_B": { + "from_pin": "IN_B", + "to_pin": "OUT" + }, + "AOUTMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "DFFMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "COUTMUX:F7": { + "from_pin": "F7", + "to_pin": "OUT" + }, + "DCY0:DX": { + "from_pin": "DX", + "to_pin": "OUT" + }, + "BOUTMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "AFFMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "C6LUT:A5": { + "from_pin": "A5", + "to_pin": "O6" + }, + "B5FFMUX:IN_A": { + "from_pin": "IN_A", + "to_pin": "OUT" + }, + "CEUSEDMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "COUTMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "BOUTMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "CUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "B5LUT:A3": { + "from_pin": "A3", + "to_pin": "O5" + }, + "COUTMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "C5LUT:A2": { + "from_pin": "A2", + "to_pin": "O5" + }, + "COUTMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + } + }, + "site_pins": { + "C6": { + "direction": "IN" + }, + "B": { + "direction": "OUT" + }, + "AQ": { + "direction": "OUT" + }, + "D1": { + "direction": "IN" + }, + "A4": { + "direction": "IN" + }, + "DX": { + "direction": "IN" + }, + "BQ": { + "direction": "OUT" + }, + "COUT": { + "direction": "OUT" + }, + "B6": { + "direction": "IN" + }, + "A": { + "direction": "OUT" + }, + "CE": { + "direction": "IN" + }, + "C": { + "direction": "OUT" + }, + "BMUX": { + "direction": "OUT" + }, + "A1": { + "direction": "IN" + }, + "DMUX": { + "direction": "OUT" + }, + "A5": { + "direction": "IN" + }, + "CLK": { + "direction": "IN" + }, + "AX": { + "direction": "IN" + }, + "BX": { + "direction": "IN" + }, + "A6": { + "direction": "IN" + }, + "B3": { + "direction": "IN" + }, + "A3": { + "direction": "IN" + }, + "SR": { + "direction": "IN" + }, + "B4": { + "direction": "IN" + }, + "AMUX": { + "direction": "OUT" + }, + "CQ": { + "direction": "OUT" + }, + "C1": { + "direction": "IN" + }, + "CX": { + "direction": "IN" + }, + "A2": { + "direction": "IN" + }, + "D": { + "direction": "OUT" + }, + "D3": { + "direction": "IN" + }, + "D6": { + "direction": "IN" + }, + "D4": { + "direction": "IN" + }, + "B2": { + "direction": "IN" + }, + "D5": { + "direction": "IN" + }, + "B5": { + "direction": "IN" + }, + "C4": { + "direction": "IN" + }, + "DQ": { + "direction": "OUT" + }, + "C5": { + "direction": "IN" + }, + "CMUX": { + "direction": "OUT" + }, + "CIN": { + "direction": "IN" + }, + "D2": { + "direction": "IN" + }, + "C2": { + "direction": "IN" + }, + "C3": { + "direction": "IN" + }, + "B1": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_SLICEM.json b/kintex7/site_type_SLICEM.json new file mode 100644 index 0000000..af2e199 --- /dev/null +++ b/kintex7/site_type_SLICEM.json @@ -0,0 +1,769 @@ +{ + "type": "SLICEM", + "site_pips": { + "A5FFMUX:IN_A": { + "from_pin": "IN_A", + "to_pin": "OUT" + }, + "COUTMUX:C5Q": { + "from_pin": "C5Q", + "to_pin": "OUT" + }, + "B6LUT:A4": { + "from_pin": "A4", + "to_pin": "O6" + }, + "D5LUT:A3": { + "from_pin": "A3", + "to_pin": "O5" + }, + "A6LUT:A4": { + "from_pin": "A4", + "to_pin": "O6" + }, + "C5LUT:A5": { + "from_pin": "A5", + "to_pin": "O5" + }, + "BOUTMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "D6LUT:A4": { + "from_pin": "A4", + "to_pin": "O6" + }, + "A5LUT:A5": { + "from_pin": "A5", + "to_pin": "O5" + }, + "A6LUT:A2": { + "from_pin": "A2", + "to_pin": "O6" + }, + "AOUTMUX:A5Q": { + "from_pin": "A5Q", + "to_pin": "OUT" + }, + "D6LUT:A5": { + "from_pin": "A5", + "to_pin": "O6" + }, + "WA8USED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "CCY0:CX": { + "from_pin": "CX", + "to_pin": "OUT" + }, + "AOUTMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "SRUSEDMUX:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "DFFMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "A5LUT:A3": { + "from_pin": "A3", + "to_pin": "O5" + }, + "BOUTMUX:B5Q": { + "from_pin": "B5Q", + "to_pin": "OUT" + }, + "ADI1MUX:BMC31": { + "from_pin": "BMC31", + "to_pin": "OUT" + }, + "BOUTMUX:F8": { + "from_pin": "F8", + "to_pin": "OUT" + }, + "WEMUX:CE": { + "from_pin": "CE", + "to_pin": "OUT" + }, + "AFFMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "BFFMUX:BX": { + "from_pin": "BX", + "to_pin": "OUT" + }, + "AFFMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "DFFMUX:DX": { + "from_pin": "DX", + "to_pin": "OUT" + }, + "BUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "DOUTMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "BDI1MUX:DI": { + "from_pin": "DI", + "to_pin": "OUT" + }, + "BFFMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "BFFMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "D5LUT:A4": { + "from_pin": "A4", + "to_pin": "O5" + }, + "BFFMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "COUTMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "D6LUT:A1": { + "from_pin": "A1", + "to_pin": "O6" + }, + "DOUTMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "CLKINV:CLK_B": { + "from_pin": "CLK_B", + "to_pin": "OUT" + }, + "B6LUT:A1": { + "from_pin": "A1", + "to_pin": "O6" + }, + "BOUTMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "AOUTMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "B6LUT:A6": { + "from_pin": "A6", + "to_pin": "O6" + }, + "C6LUT:A4": { + "from_pin": "A4", + "to_pin": "O6" + }, + "C6LUT:A1": { + "from_pin": "A1", + "to_pin": "O6" + }, + "BOUTMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "B5FFMUX:IN_B": { + "from_pin": "IN_B", + "to_pin": "OUT" + }, + "CFFMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "DFFMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "DOUTMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "D5FFMUX:IN_B": { + "from_pin": "IN_B", + "to_pin": "OUT" + }, + "AFFMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "ACY0:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "DOUTMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "CFFMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "BOUTMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "DFFMUX:MC31": { + "from_pin": "MC31", + "to_pin": "OUT" + }, + "D5LUT:A2": { + "from_pin": "A2", + "to_pin": "O5" + }, + "DOUTMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "DFFMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "A6LUT:A6": { + "from_pin": "A6", + "to_pin": "O6" + }, + "DOUTMUX:D5Q": { + "from_pin": "D5Q", + "to_pin": "OUT" + }, + "PRECYINIT:CIN": { + "from_pin": "CIN", + "to_pin": "OUT" + }, + "AOUTMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "DCY0:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "ADI1MUX:BDI1": { + "from_pin": "BDI1", + "to_pin": "OUT" + }, + "A5LUT:A2": { + "from_pin": "A2", + "to_pin": "O5" + }, + "A5LUT:A1": { + "from_pin": "A1", + "to_pin": "O5" + }, + "C5LUT:A3": { + "from_pin": "A3", + "to_pin": "O5" + }, + "PRECYINIT:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "B6LUT:A2": { + "from_pin": "A2", + "to_pin": "O6" + }, + "A6LUT:A3": { + "from_pin": "A3", + "to_pin": "O6" + }, + "BOUTMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "PRECYINIT:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "BCY0:BX": { + "from_pin": "BX", + "to_pin": "OUT" + }, + "C5FFMUX:IN_A": { + "from_pin": "IN_A", + "to_pin": "OUT" + }, + "COUTUSED:CARRY4_0": { + "from_pin": "CARRY4_0", + "to_pin": "OUT" + }, + "B5LUT:A4": { + "from_pin": "A4", + "to_pin": "O5" + }, + "DCY0:DX": { + "from_pin": "DX", + "to_pin": "OUT" + }, + "AFFMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "C5FFMUX:IN_B": { + "from_pin": "IN_B", + "to_pin": "OUT" + }, + "BFFMUX:F8": { + "from_pin": "F8", + "to_pin": "OUT" + }, + "BDI1MUX:BI": { + "from_pin": "BI", + "to_pin": "OUT" + }, + "BFFMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "ADI1MUX:AI": { + "from_pin": "AI", + "to_pin": "OUT" + }, + "CFFMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "DUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "AOUTMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "WA7USED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "SRUSEDMUX:IN": { + "from_pin": "IN", + "to_pin": "OUT" + }, + "B6LUT:A3": { + "from_pin": "A3", + "to_pin": "O6" + }, + "AOUTMUX:F7": { + "from_pin": "F7", + "to_pin": "OUT" + }, + "BDI1MUX:CMC31": { + "from_pin": "CMC31", + "to_pin": "OUT" + }, + "C5LUT:A4": { + "from_pin": "A4", + "to_pin": "O5" + }, + "WEMUX:WE": { + "from_pin": "WE", + "to_pin": "OUT" + }, + "BFFMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "AFFMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "A5LUT:A4": { + "from_pin": "A4", + "to_pin": "O5" + }, + "C6LUT:A3": { + "from_pin": "A3", + "to_pin": "O6" + }, + "A6LUT:A1": { + "from_pin": "A1", + "to_pin": "O6" + }, + "DOUTMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "B5LUT:A5": { + "from_pin": "A5", + "to_pin": "O5" + }, + "D6LUT:A3": { + "from_pin": "A3", + "to_pin": "O6" + }, + "CCY0:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "C5LUT:A1": { + "from_pin": "A1", + "to_pin": "O5" + }, + "COUTMUX:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "CFFMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "D6LUT:A6": { + "from_pin": "A6", + "to_pin": "O6" + }, + "DOUTMUX:MC31": { + "from_pin": "MC31", + "to_pin": "OUT" + }, + "CFFMUX:F7": { + "from_pin": "F7", + "to_pin": "OUT" + }, + "D5LUT:A5": { + "from_pin": "A5", + "to_pin": "O5" + }, + "AFFMUX:F7": { + "from_pin": "F7", + "to_pin": "OUT" + }, + "AOUTMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "D6LUT:A2": { + "from_pin": "A2", + "to_pin": "O6" + }, + "BOUTMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "B5LUT:A2": { + "from_pin": "A2", + "to_pin": "O5" + }, + "AUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "C6LUT:A2": { + "from_pin": "A2", + "to_pin": "O6" + }, + "PRECYINIT:AX": { + "from_pin": "AX", + "to_pin": "OUT" + }, + "BCY0:O5": { + "from_pin": "O5", + "to_pin": "OUT" + }, + "BFFMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "CEUSEDMUX:IN": { + "from_pin": "IN", + "to_pin": "OUT" + }, + "CFFMUX:CX": { + "from_pin": "CX", + "to_pin": "OUT" + }, + "C6LUT:A6": { + "from_pin": "A6", + "to_pin": "O6" + }, + "D5LUT:A1": { + "from_pin": "A1", + "to_pin": "O5" + }, + "D5FFMUX:IN_A": { + "from_pin": "IN_A", + "to_pin": "OUT" + }, + "ACY0:AX": { + "from_pin": "AX", + "to_pin": "OUT" + }, + "COUTUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "B6LUT:A5": { + "from_pin": "A5", + "to_pin": "O6" + }, + "CFFMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "A6LUT:A5": { + "from_pin": "A5", + "to_pin": "O6" + }, + "CDI1MUX:CI": { + "from_pin": "CI", + "to_pin": "OUT" + }, + "CLKINV:CLK": { + "from_pin": "CLK", + "to_pin": "OUT" + }, + "CDI1MUX:DI": { + "from_pin": "DI", + "to_pin": "OUT" + }, + "COUTMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "A5FFMUX:IN_B": { + "from_pin": "IN_B", + "to_pin": "OUT" + }, + "AOUTMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "CDI1MUX:DMC31": { + "from_pin": "DMC31", + "to_pin": "OUT" + }, + "DFFMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + }, + "COUTMUX:F7": { + "from_pin": "F7", + "to_pin": "OUT" + }, + "CFFMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "AFFMUX:AX": { + "from_pin": "AX", + "to_pin": "OUT" + }, + "AFFMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "C6LUT:A5": { + "from_pin": "A5", + "to_pin": "O6" + }, + "B5FFMUX:IN_A": { + "from_pin": "IN_A", + "to_pin": "OUT" + }, + "CEUSEDMUX:1": { + "from_pin": "1", + "to_pin": "OUT" + }, + "COUTMUX:CARRY4_XOR": { + "from_pin": "CARRY4_XOR", + "to_pin": "OUT" + }, + "B5LUT:A1": { + "from_pin": "A1", + "to_pin": "O5" + }, + "DFFMUX:O6": { + "from_pin": "O6", + "to_pin": "OUT" + }, + "CUSED:0": { + "from_pin": "0", + "to_pin": "OUT" + }, + "B5LUT:A3": { + "from_pin": "A3", + "to_pin": "O5" + }, + "DFFMUX:CARRY4_MUX": { + "from_pin": "CARRY4_MUX", + "to_pin": "OUT" + }, + "COUTMUX:XOR": { + "from_pin": "XOR", + "to_pin": "OUT" + }, + "C5LUT:A2": { + "from_pin": "A2", + "to_pin": "O5" + }, + "COUTMUX:CY": { + "from_pin": "CY", + "to_pin": "OUT" + } + }, + "site_pins": { + "C6": { + "direction": "IN" + }, + "BI": { + "direction": "IN" + }, + "B6": { + "direction": "IN" + }, + "D1": { + "direction": "IN" + }, + "B5": { + "direction": "IN" + }, + "A4": { + "direction": "IN" + }, + "AI": { + "direction": "IN" + }, + "DX": { + "direction": "IN" + }, + "BQ": { + "direction": "OUT" + }, + "CI": { + "direction": "IN" + }, + "COUT": { + "direction": "OUT" + }, + "A": { + "direction": "OUT" + }, + "CE": { + "direction": "IN" + }, + "C": { + "direction": "OUT" + }, + "BMUX": { + "direction": "OUT" + }, + "A1": { + "direction": "IN" + }, + "DMUX": { + "direction": "OUT" + }, + "A5": { + "direction": "IN" + }, + "CLK": { + "direction": "IN" + }, + "AX": { + "direction": "IN" + }, + "BX": { + "direction": "IN" + }, + "A6": { + "direction": "IN" + }, + "B3": { + "direction": "IN" + }, + "A3": { + "direction": "IN" + }, + "CIN": { + "direction": "IN" + }, + "B4": { + "direction": "IN" + }, + "AMUX": { + "direction": "OUT" + }, + "D6": { + "direction": "IN" + }, + "CQ": { + "direction": "OUT" + }, + "C1": { + "direction": "IN" + }, + "CX": { + "direction": "IN" + }, + "A2": { + "direction": "IN" + }, + "D": { + "direction": "OUT" + }, + "D3": { + "direction": "IN" + }, + "B": { + "direction": "OUT" + }, + "D4": { + "direction": "IN" + }, + "AQ": { + "direction": "OUT" + }, + "B2": { + "direction": "IN" + }, + "D5": { + "direction": "IN" + }, + "DI": { + "direction": "IN" + }, + "C4": { + "direction": "IN" + }, + "DQ": { + "direction": "OUT" + }, + "C5": { + "direction": "IN" + }, + "CMUX": { + "direction": "OUT" + }, + "WE": { + "direction": "IN" + }, + "SR": { + "direction": "IN" + }, + "D2": { + "direction": "IN" + }, + "C2": { + "direction": "IN" + }, + "C3": { + "direction": "IN" + }, + "B1": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_STARTUP.json b/kintex7/site_type_STARTUP.json new file mode 100644 index 0000000..85c8027 --- /dev/null +++ b/kintex7/site_type_STARTUP.json @@ -0,0 +1,45 @@ +{ + "type": "STARTUP", + "site_pips": {}, + "site_pins": { + "USRDONETS": { + "direction": "IN" + }, + "PREQ": { + "direction": "OUT" + }, + "CFGMCLK": { + "direction": "OUT" + }, + "GSR": { + "direction": "IN" + }, + "GTS": { + "direction": "IN" + }, + "PACK": { + "direction": "IN" + }, + "CFGCLK": { + "direction": "OUT" + }, + "CLK": { + "direction": "IN" + }, + "USRDONEO": { + "direction": "IN" + }, + "EOS": { + "direction": "OUT" + }, + "USRCCLKO": { + "direction": "IN" + }, + "KEYCLEARB": { + "direction": "IN" + }, + "USRCCLKTS": { + "direction": "IN" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_TIEOFF.json b/kintex7/site_type_TIEOFF.json new file mode 100644 index 0000000..954593d --- /dev/null +++ b/kintex7/site_type_TIEOFF.json @@ -0,0 +1,12 @@ +{ + "type": "TIEOFF", + "site_pips": {}, + "site_pins": { + "HARD1": { + "direction": "OUT" + }, + "HARD0": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_USR_ACCESS.json b/kintex7/site_type_USR_ACCESS.json new file mode 100644 index 0000000..5054f34 --- /dev/null +++ b/kintex7/site_type_USR_ACCESS.json @@ -0,0 +1,108 @@ +{ + "type": "USR_ACCESS", + "site_pips": {}, + "site_pins": { + "DATA3": { + "direction": "OUT" + }, + "DATA1": { + "direction": "OUT" + }, + "CFGCLK": { + "direction": "OUT" + }, + "DATA14": { + "direction": "OUT" + }, + "DATA26": { + "direction": "OUT" + }, + "DATA11": { + "direction": "OUT" + }, + "DATA4": { + "direction": "OUT" + }, + "DATA30": { + "direction": "OUT" + }, + "DATA13": { + "direction": "OUT" + }, + "DATA15": { + "direction": "OUT" + }, + "DATA5": { + "direction": "OUT" + }, + "DATA27": { + "direction": "OUT" + }, + "DATAVALID": { + "direction": "OUT" + }, + "DATA24": { + "direction": "OUT" + }, + "DATA12": { + "direction": "OUT" + }, + "DATA29": { + "direction": "OUT" + }, + "DATA10": { + "direction": "OUT" + }, + "DATA9": { + "direction": "OUT" + }, + "DATA7": { + "direction": "OUT" + }, + "DATA8": { + "direction": "OUT" + }, + "DATA17": { + "direction": "OUT" + }, + "DATA0": { + "direction": "OUT" + }, + "DATA18": { + "direction": "OUT" + }, + "DATA19": { + "direction": "OUT" + }, + "DATA6": { + "direction": "OUT" + }, + "DATA22": { + "direction": "OUT" + }, + "DATA20": { + "direction": "OUT" + }, + "DATA16": { + "direction": "OUT" + }, + "DATA21": { + "direction": "OUT" + }, + "DATA25": { + "direction": "OUT" + }, + "DATA2": { + "direction": "OUT" + }, + "DATA28": { + "direction": "OUT" + }, + "DATA23": { + "direction": "OUT" + }, + "DATA31": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/site_type_XADC.json b/kintex7/site_type_XADC.json new file mode 100644 index 0000000..5441e11 --- /dev/null +++ b/kintex7/site_type_XADC.json @@ -0,0 +1,683 @@ +{ + "type": "XADC", + "site_pips": { + "DCLKINV:DCLK_B": { + "from_pin": "DCLK_B", + "to_pin": "OUT" + }, + "DCLKINV:DCLK": { + "from_pin": "DCLK", + "to_pin": "OUT" + }, + "CONVSTCLKINV:CONVSTCLK_B": { + "from_pin": "CONVSTCLK_B", + "to_pin": "OUT" + }, + "CONVSTCLKINV:CONVSTCLK": { + "from_pin": "CONVSTCLK", + "to_pin": "OUT" + } + }, + "site_pins": { + "TESTDB5": { + "direction": "OUT" + }, + "DO12": { + "direction": "OUT" + }, + "DEN": { + "direction": "IN" + }, + "VAUXN11": { + "direction": "IN" + }, + "VN": { + "direction": "IN" + }, + "VAUXP0": { + "direction": "IN" + }, + "TESTADCOUT3": { + "direction": "OUT" + }, + "DI0": { + "direction": "IN" + }, + "TESTADCIN19": { + "direction": "IN" + }, + "TESTSCANCLK3": { + "direction": "IN" + }, + "JTAGMODIFIED": { + "direction": "OUT" + }, + "VAUXN1": { + "direction": "IN" + }, + "TESTSE1": { + "direction": "IN" + }, + "TESTSCANMODE0": { + "direction": "IN" + }, + "MUXADDR1": { + "direction": "OUT" + }, + "DO7": { + "direction": "OUT" + }, + "TESTADCIN3": { + "direction": "IN" + }, + "VAUXN8": { + "direction": "IN" + }, + "TESTADCOUT17": { + "direction": "OUT" + }, + "TESTSCANMODE4": { + "direction": "IN" + }, + "TESTADCCLK0": { + "direction": "IN" + }, + "TESTDB14": { + "direction": "OUT" + }, + "VAUXP6": { + "direction": "IN" + }, + "OT": { + "direction": "OUT" + }, + "VAUXN14": { + "direction": "IN" + }, + "TESTADCIN217": { + "direction": "IN" + }, + "TESTADCOUT16": { + "direction": "OUT" + }, + "TESTSE4": { + "direction": "IN" + }, + "TESTADCOUT6": { + "direction": "OUT" + }, + "VAUXN0": { + "direction": "IN" + }, + "TESTADCIN18": { + "direction": "IN" + }, + "TESTADCOUT9": { + "direction": "OUT" + }, + "VP": { + "direction": "IN" + }, + "TESTDB9": { + "direction": "OUT" + }, + "DO3": { + "direction": "OUT" + }, + "TESTADCIN4": { + "direction": "IN" + }, + "VAUXN7": { + "direction": "IN" + }, + "DI8": { + "direction": "IN" + }, + "VAUXP2": { + "direction": "IN" + }, + "DO4": { + "direction": "OUT" + }, + "VAUXP1": { + "direction": "IN" + }, + "TESTDB0": { + "direction": "OUT" + }, + "TESTSEL": { + "direction": "IN" + }, + "TESTSO2": { + "direction": "OUT" + }, + "TESTADCIN29": { + "direction": "IN" + }, + "TESTADCOUT13": { + "direction": "OUT" + }, + "TESTADCIN12": { + "direction": "IN" + }, + "TESTDB2": { + "direction": "OUT" + }, + "CHANNEL1": { + "direction": "OUT" + }, + "DI14": { + "direction": "IN" + }, + "TESTENJTAG": { + "direction": "IN" + }, + "TESTSI0": { + "direction": "IN" + }, + "DADDR1": { + "direction": "IN" + }, + "TESTADCOUT12": { + "direction": "OUT" + }, + "TESTADCIN5": { + "direction": "IN" + }, + "TESTDB7": { + "direction": "OUT" + }, + "TESTADCIN20": { + "direction": "IN" + }, + "TESTDB3": { + "direction": "OUT" + }, + "ALM0": { + "direction": "OUT" + }, + "TESTTDO": { + "direction": "OUT" + }, + "TESTSCANCLK1": { + "direction": "IN" + }, + "DO5": { + "direction": "OUT" + }, + "DWE": { + "direction": "IN" + }, + "DO0": { + "direction": "OUT" + }, + "DO13": { + "direction": "OUT" + }, + "TESTADCOUT0": { + "direction": "OUT" + }, + "ALM6": { + "direction": "OUT" + }, + "TESTSO0": { + "direction": "OUT" + }, + "EOS": { + "direction": "OUT" + }, + "TESTADCIN2": { + "direction": "IN" + }, + "DI5": { + "direction": "IN" + }, + "TESTSCANMODE1": { + "direction": "IN" + }, + "TESTADCOUT14": { + "direction": "OUT" + }, + "TESTSCANCLK2": { + "direction": "IN" + }, + "VAUXN12": { + "direction": "IN" + }, + "DO14": { + "direction": "OUT" + }, + "TESTADCOUT5": { + "direction": "OUT" + }, + "DI6": { + "direction": "IN" + }, + "TESTADCIN213": { + "direction": "IN" + }, + "ALM7": { + "direction": "OUT" + }, + "DO1": { + "direction": "OUT" + }, + "VAUXN9": { + "direction": "IN" + }, + "VAUXP8": { + "direction": "IN" + }, + "JTAGLOCKED": { + "direction": "OUT" + }, + "VAUXN2": { + "direction": "IN" + }, + "CHANNEL2": { + "direction": "OUT" + }, + "TESTSO3": { + "direction": "OUT" + }, + "TESTSI4": { + "direction": "IN" + }, + "DO10": { + "direction": "OUT" + }, + "DI3": { + "direction": "IN" + }, + "VAUXP12": { + "direction": "IN" + }, + "TESTADCIN212": { + "direction": "IN" + }, + "TESTADCOUT15": { + "direction": "OUT" + }, + "VAUXN3": { + "direction": "IN" + }, + "TESTADCIN15": { + "direction": "IN" + }, + "DO9": { + "direction": "OUT" + }, + "TESTADCIN216": { + "direction": "IN" + }, + "DO6": { + "direction": "OUT" + }, + "TESTADCOUT4": { + "direction": "OUT" + }, + "TESTADCIN27": { + "direction": "IN" + }, + "DI15": { + "direction": "IN" + }, + "TESTADCOUT7": { + "direction": "OUT" + }, + "MUXADDR4": { + "direction": "OUT" + }, + "TESTSHIFT": { + "direction": "IN" + }, + "DI13": { + "direction": "IN" + }, + "ALM3": { + "direction": "OUT" + }, + "TESTADCIN23": { + "direction": "IN" + }, + "TESTADCOUT8": { + "direction": "OUT" + }, + "TESTADCIN10": { + "direction": "IN" + }, + "TESTADCIN219": { + "direction": "IN" + }, + "TESTADCIN210": { + "direction": "IN" + }, + "TESTSCANCLK0": { + "direction": "IN" + }, + "TESTSE3": { + "direction": "IN" + }, + "TESTSE2": { + "direction": "IN" + }, + "TESTSCANMODE2": { + "direction": "IN" + }, + "TESTDB6": { + "direction": "OUT" + }, + "TESTADCIN16": { + "direction": "IN" + }, + "TESTADCIN8": { + "direction": "IN" + }, + "VAUXN15": { + "direction": "IN" + }, + "TESTDB12": { + "direction": "OUT" + }, + "DO2": { + "direction": "OUT" + }, + "EOC": { + "direction": "OUT" + }, + "VAUXP15": { + "direction": "IN" + }, + "TESTADCIN9": { + "direction": "IN" + }, + "VAUXP7": { + "direction": "IN" + }, + "TESTADCIN11": { + "direction": "IN" + }, + "DI11": { + "direction": "IN" + }, + "VAUXN4": { + "direction": "IN" + }, + "TESTTDI": { + "direction": "IN" + }, + "DI2": { + "direction": "IN" + }, + "TESTRST": { + "direction": "IN" + }, + "VAUXP4": { + "direction": "IN" + }, + "CONVST": { + "direction": "IN" + }, + "DRDY": { + "direction": "OUT" + }, + "VAUXP3": { + "direction": "IN" + }, + "ALM2": { + "direction": "OUT" + }, + "VAUXP10": { + "direction": "IN" + }, + "TESTDB13": { + "direction": "OUT" + }, + "MUXADDR3": { + "direction": "OUT" + }, + "TESTSI1": { + "direction": "IN" + }, + "TESTADCIN6": { + "direction": "IN" + }, + "DADDR3": { + "direction": "IN" + }, + "TESTDB8": { + "direction": "OUT" + }, + "BUSY": { + "direction": "OUT" + }, + "MUXADDR2": { + "direction": "OUT" + }, + "TESTADCIN17": { + "direction": "IN" + }, + "ALM5": { + "direction": "OUT" + }, + "TESTSCANCLK4": { + "direction": "IN" + }, + "VAUXN13": { + "direction": "IN" + }, + "TESTDB1": { + "direction": "OUT" + }, + "DADDR4": { + "direction": "IN" + }, + "TESTADCOUT19": { + "direction": "OUT" + }, + "TESTADCIN1": { + "direction": "IN" + }, + "TESTADCOUT2": { + "direction": "OUT" + }, + "TESTADCOUT1": { + "direction": "OUT" + }, + "TESTSE0": { + "direction": "IN" + }, + "DADDR0": { + "direction": "IN" + }, + "TESTADCIN28": { + "direction": "IN" + }, + "TESTDRCK": { + "direction": "IN" + }, + "TESTUPDATE": { + "direction": "IN" + }, + "CONVSTCLK": { + "direction": "IN" + }, + "TESTADCIN14": { + "direction": "IN" + }, + "VAUXP13": { + "direction": "IN" + }, + "VAUXN10": { + "direction": "IN" + }, + "TESTSI3": { + "direction": "IN" + }, + "DO11": { + "direction": "OUT" + }, + "DI9": { + "direction": "IN" + }, + "DADDR5": { + "direction": "IN" + }, + "DI10": { + "direction": "IN" + }, + "VAUXN6": { + "direction": "IN" + }, + "TESTADCOUT18": { + "direction": "OUT" + }, + "VAUXN5": { + "direction": "IN" + }, + "VAUXP11": { + "direction": "IN" + }, + "TESTSCANRESET": { + "direction": "IN" + }, + "ALM1": { + "direction": "OUT" + }, + "VAUXP9": { + "direction": "IN" + }, + "DO15": { + "direction": "OUT" + }, + "DI1": { + "direction": "IN" + }, + "TESTADCIN218": { + "direction": "IN" + }, + "TESTADCCLK2": { + "direction": "IN" + }, + "VAUXP5": { + "direction": "IN" + }, + "TESTSO1": { + "direction": "OUT" + }, + "ALM4": { + "direction": "OUT" + }, + "CHANNEL0": { + "direction": "OUT" + }, + "TESTADCOUT10": { + "direction": "OUT" + }, + "TESTADCIN22": { + "direction": "IN" + }, + "CHANNEL4": { + "direction": "OUT" + }, + "DI7": { + "direction": "IN" + }, + "TESTADCOUT11": { + "direction": "OUT" + }, + "TESTSCANMODE3": { + "direction": "IN" + }, + "DI4": { + "direction": "IN" + }, + "MUXADDR0": { + "direction": "OUT" + }, + "TESTADCIN215": { + "direction": "IN" + }, + "DCLK": { + "direction": "IN" + }, + "DADDR2": { + "direction": "IN" + }, + "TESTDB10": { + "direction": "OUT" + }, + "TESTADCIN26": { + "direction": "IN" + }, + "TESTADCIN214": { + "direction": "IN" + }, + "TESTADCIN0": { + "direction": "IN" + }, + "TESTDB4": { + "direction": "OUT" + }, + "TESTADCIN24": { + "direction": "IN" + }, + "DI12": { + "direction": "IN" + }, + "RESET": { + "direction": "IN" + }, + "VAUXP14": { + "direction": "IN" + }, + "TESTCAPTURE": { + "direction": "IN" + }, + "DADDR6": { + "direction": "IN" + }, + "TESTADCCLK3": { + "direction": "IN" + }, + "TESTADCCLK1": { + "direction": "IN" + }, + "JTAGBUSY": { + "direction": "OUT" + }, + "TESTSO4": { + "direction": "OUT" + }, + "TESTDB15": { + "direction": "OUT" + }, + "DO8": { + "direction": "OUT" + }, + "TESTADCIN7": { + "direction": "IN" + }, + "TESTADCIN25": { + "direction": "IN" + }, + "TESTADCIN13": { + "direction": "IN" + }, + "TESTDB11": { + "direction": "OUT" + }, + "TESTSI2": { + "direction": "IN" + }, + "TESTADCIN21": { + "direction": "IN" + }, + "TESTADCIN211": { + "direction": "IN" + }, + "CHANNEL3": { + "direction": "OUT" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_BRAM_INT_INTERFACE_L.json b/kintex7/tile_type_BRAM_INT_INTERFACE_L.json new file mode 100644 index 0000000..370d95b --- /dev/null +++ b/kintex7/tile_type_BRAM_INT_INTERFACE_L.json @@ -0,0 +1,476 @@ +{ + "tile_type": "BRAM_INT_INTERFACE_L", + "sites": [], + "wires": [ + "INT_INTERFACE_LOGIC_OUTS_L15", + "INT_INTERFACE_BRAM_UTURN_IMUX47", + "INT_INTERFACE_EE4C1", + "INT_INTERFACE_BRAM_UTURN_IMUX7", + "INT_INTERFACE_BRAM_IMUX14", + "INT_INTERFACE_BRAM_UTURN_IMUX43", + "INT_INTERFACE_BRAM_IMUX19", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_BRAM_UTURN_IMUX30", + "INT_INTERFACE_BRAM_UTURN_IMUX19", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_WW4C2", + "INT_INTERFACE_LH7", + "INT_INTERFACE_BRAM_IMUX37", + "INT_INTERFACE_EE4C3", + "INT_INTERFACE_BRAM_UTURN_IMUX28", + "INT_INTERFACE_BRAM_UTURN_IMUX36", + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "INT_INTERFACE_BRAM_UTURN_IMUX16", + "INT_INTERFACE_BRAM_UTURN_IMUX5", + "INT_INTERFACE_LOGIC_OUTS_L11", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "INT_INTERFACE_BLOCK_OUTS_L_B3", + "INT_INTERFACE_BRAM_IMUX13", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "INT_INTERFACE_BRAM_IMUX44", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_BRAM_IMUX34", + "INT_INTERFACE_LOGIC_OUTS_L23", + "INT_INTERFACE_BRAM_IMUX17", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "INT_INTERFACE_BRAM_UTURN_IMUX39", + "INT_INTERFACE_LOGIC_OUTS_L7", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_LOGIC_OUTS_L3", + "INT_INTERFACE_BRAM_IMUX39", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_BRAM_IMUX4", + "INT_INTERFACE_LH11", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_BRAM_UTURN_IMUX6", + "INT_INTERFACE_SE2A2", + "INT_INTERFACE_BRAM_IMUX16", + "INT_INTERFACE_BRAM_IMUX27", + "INT_INTERFACE_WW4C1", + "INT_INTERFACE_BRAM_UTURN_IMUX10", + "INT_INTERFACE_SW2A3", + "INT_INTERFACE_BRAM_UTURN_IMUX35", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_BRAM_UTURN_IMUX44", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_EL1BEG3", + "INT_INTERFACE_BRAM_IMUX1", + "L_INT_INTER_DQS_IOTOPHASER", + "INT_INTERFACE_LH5", + "INT_INTERFACE_BRAM_IMUX12", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_BRAM_IMUX43", + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "INT_INTERFACE_SE4BEG3", + "INT_INTERFACE_BRAM_UTURN_IMUX8", + "INT_INTERFACE_BRAM_IMUX29", + "INT_INTERFACE_BRAM_UTURN_IMUX31", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_BRAM_UTURN_IMUX9", + "INT_INTERFACE_BRAM_UTURN_IMUX27", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_BRAM_UTURN_IMUX25", + "INT_INTERFACE_LOGIC_OUTS_L13", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_WL1END1", + "INT_INTERFACE_BRAM_UTURN_IMUX21", + "INT_INTERFACE_BRAM_UTURN_IMUX2", + "INT_INTERFACE_BRAM_IMUX15", + "INT_INTERFACE_BRAM_UTURN_IMUX11", + "INT_INTERFACE_BRAM_UTURN_IMUX24", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "INT_INTERFACE_BRAM_IMUX11", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_LH10", + "INT_INTERFACE_LOGIC_OUTS_L22", + "INT_INTERFACE_BRAM_IMUX42", + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_BRAM_IMUX7", + "INT_INTERFACE_LOGIC_OUTS_L4", + "INT_INTERFACE_BRAM_IMUX0", + "INT_INTERFACE_BRAM_UTURN_IMUX45", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_BRAM_IMUX46", + "INT_INTERFACE_BRAM_IMUX28", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_BRAM_IMUX9", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_BRAM_UTURN_IMUX12", + "INT_INTERFACE_BRAM_IMUX21", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_LH2", + "INT_INTERFACE_BRAM_IMUX31", + "INT_INTERFACE_BLOCK_OUTS_L_B0", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_BRAM_IMUX33", + "INT_INTERFACE_BRAM_UTURN_IMUX29", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_BRAM_IMUX22", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_LH1", + "INT_INTERFACE_LOGIC_OUTS_L6", + "INT_INTERFACE_BRAM_UTURN_IMUX41", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_LH9", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_LH8", + "INT_INTERFACE_BRAM_UTURN_IMUX17", + "INT_INTERFACE_LH4", + "INT_INTERFACE_BRAM_UTURN_IMUX33", + "INT_INTERFACE_LOGIC_OUTS_L19", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_BRAM_IMUX3", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_BRAM_UTURN_IMUX18", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_BRAM_IMUX32", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_LOGIC_OUTS_L12", + "INT_INTERFACE_BRAM_IMUX24", + "INT_INTERFACE_BRAM_UTURN_IMUX23", + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_BRAM_IMUX8", + "INT_INTERFACE_BLOCK_OUTS_L_B1", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LH3", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_LOGIC_OUTS_L18", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "INT_INTERFACE_LOGIC_OUTS_L1", + "INT_INTERFACE_BRAM_UTURN_IMUX1", + "INT_INTERFACE_LOGIC_OUTS_L2", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_BRAM_UTURN_IMUX3", + "INT_INTERFACE_BRAM_IMUX30", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_BRAM_IMUX6", + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "INT_INTERFACE_BRAM_UTURN_IMUX13", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_FAN5", + "INT_INTERFACE_LOGIC_OUTS_L8", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_LOGIC_OUTS_L21", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_BRAM_UTURN_IMUX20", + "INT_INTERFACE_BYP5", + "INT_INTERFACE_BRAM_UTURN_IMUX34", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_BRAM_IMUX47", + "INT_INTERFACE_LOGIC_OUTS_L14", + "INT_INTERFACE_BRAM_UTURN_IMUX14", + "INT_INTERFACE_LOGIC_OUTS_L10", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_BRAM_IMUX35", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_BRAM_UTURN_IMUX37", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_BRAM_UTURN_IMUX22", + "INT_INTERFACE_WW4B1", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_BRAM_UTURN_IMUX38", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_BRAM_IMUX10", + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_BRAM_IMUX2", + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "INT_INTERFACE_WW4A1", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_BRAM_IMUX41", + "INT_INTERFACE_LOGIC_OUTS_L16", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_BRAM_IMUX45", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_BRAM_UTURN_IMUX15", + "INT_INTERFACE_LH6", + "INT_INTERFACE_BRAM_IMUX20", + "INT_INTERFACE_BRAM_UTURN_IMUX0", + "INT_INTERFACE_BRAM_IMUX36", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_BRAM_UTURN_IMUX32", + "INT_INTERFACE_LH12", + "INT_INTERFACE_LOGIC_OUTS_L20", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "INT_INTERFACE_WR1END1", + "INT_INTERFACE_BRAM_UTURN_IMUX40", + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_BRAM_IMUX40", + "INT_INTERFACE_BRAM_IMUX5", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_BRAM_IMUX26", + "INT_INTERFACE_WW4END0", + "INT_INTERFACE_BRAM_UTURN_IMUX26", + "INT_INTERFACE_BRAM_UTURN_IMUX42", + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_BRAM_IMUX25", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_BRAM_UTURN_IMUX46", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_EE2A3", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_BRAM_IMUX23", + "INT_INTERFACE_BRAM_IMUX18", + "INT_INTERFACE_LOGIC_OUTS_L5", + "INT_INTERFACE_BRAM_UTURN_IMUX4", + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_LOGIC_OUTS_L9", + "INT_INTERFACE_BYP7", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_BRAM_IMUX38", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_BLOCK_OUTS_L_B2", + "INT_INTERFACE_LOGIC_OUTS_L17", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_LOGIC_OUTS_L0" + ], + "pips": { + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_BRAM_INT_INTERFACE_R.json b/kintex7/tile_type_BRAM_INT_INTERFACE_R.json new file mode 100644 index 0000000..c5c2cbb --- /dev/null +++ b/kintex7/tile_type_BRAM_INT_INTERFACE_R.json @@ -0,0 +1,476 @@ +{ + "tile_type": "BRAM_INT_INTERFACE_R", + "sites": [], + "wires": [ + "INT_INTERFACE_EE4C1", + "INT_INTERFACE_BRAM_UTURN_R_IMUX19", + "INT_INTERFACE_BRAM_IMUX14", + "INT_INTERFACE_BRAM_IMUX19", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX39", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_WW4C2", + "INT_INTERFACE_LH7", + "INT_INTERFACE_BRAM_IMUX37", + "INT_INTERFACE_EE4C3", + "INT_INTERFACE_BRAM_UTURN_R_IMUX41", + "INT_INTERFACE_BRAM_UTURN_R_IMUX0", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_LOGIC_OUTS_B22", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_LOGIC_OUTS16", + "INT_INTERFACE_BRAM_IMUX13", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_LOGIC_OUTS3", + "INT_INTERFACE_BRAM_IMUX44", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_LOGIC_OUTS20", + "INT_INTERFACE_LOGIC_OUTS22", + "INT_INTERFACE_BRAM_IMUX34", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_BRAM_IMUX17", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_LH8", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_LH11", + "INT_INTERFACE_BRAM_IMUX39", + "INT_INTERFACE_BRAM_IMUX4", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_LOGIC_OUTS1", + "INT_INTERFACE_BRAM_UTURN_R_IMUX33", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_LOGIC_OUTS0", + "INT_INTERFACE_BLOCK_OUTS_B0", + "INT_INTERFACE_SE2A2", + "INT_INTERFACE_BRAM_IMUX16", + "INT_INTERFACE_BRAM_UTURN_R_IMUX24", + "INT_INTERFACE_BRAM_IMUX27", + "INT_INTERFACE_BRAM_UTURN_R_IMUX18", + "INT_INTERFACE_BRAM_UTURN_R_IMUX10", + "INT_INTERFACE_WW4C1", + "INT_INTERFACE_BRAM_UTURN_R_IMUX6", + "INT_INTERFACE_SW2A3", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_EL1BEG3", + "INT_INTERFACE_BRAM_UTURN_R_IMUX26", + "INT_INTERFACE_BRAM_IMUX1", + "L_INT_INTER_DQS_IOTOPHASER", + "INT_INTERFACE_LH5", + "INT_INTERFACE_BRAM_UTURN_R_IMUX28", + "INT_INTERFACE_BRAM_IMUX12", + "INT_INTERFACE_BLOCK_OUTS_B3", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_BRAM_IMUX43", + "INT_INTERFACE_BRAM_UTURN_R_IMUX5", + "INT_INTERFACE_BRAM_UTURN_R_IMUX25", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_SE4BEG3", + "INT_INTERFACE_BRAM_IMUX29", + "INT_INTERFACE_LOGIC_OUTS_B2", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_LOGIC_OUTS_B20", + "INT_INTERFACE_BRAM_UTURN_R_IMUX7", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_BRAM_UTURN_R_IMUX42", + "INT_INTERFACE_BRAM_UTURN_R_IMUX16", + "INT_INTERFACE_WL1END1", + "INT_INTERFACE_BRAM_IMUX15", + "INT_INTERFACE_LOGIC_OUTS_B23", + "INT_INTERFACE_BRAM_UTURN_R_IMUX9", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_BRAM_UTURN_R_IMUX29", + "INT_INTERFACE_BRAM_UTURN_R_IMUX1", + "INT_INTERFACE_BRAM_IMUX11", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_LH10", + "INT_INTERFACE_BRAM_IMUX42", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_BRAM_IMUX7", + "INT_INTERFACE_LOGIC_OUTS_B6", + "INT_INTERFACE_BRAM_IMUX0", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_BRAM_UTURN_R_IMUX31", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_BRAM_IMUX46", + "INT_INTERFACE_LOGIC_OUTS18", + "INT_INTERFACE_BRAM_UTURN_R_IMUX35", + "INT_INTERFACE_BRAM_IMUX28", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_BRAM_IMUX9", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_BRAM_IMUX21", + "INT_INTERFACE_LOGIC_OUTS_B16", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_LH2", + "INT_INTERFACE_BRAM_IMUX31", + "INT_INTERFACE_LOGIC_OUTS_B14", + "INT_INTERFACE_BRAM_UTURN_R_IMUX21", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_BRAM_UTURN_R_IMUX37", + "INT_INTERFACE_BRAM_IMUX33", + "INT_INTERFACE_BRAM_UTURN_R_IMUX27", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_BRAM_UTURN_R_IMUX4", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_BRAM_UTURN_R_IMUX45", + "INT_INTERFACE_LOGIC_OUTS23", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_BRAM_IMUX22", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_BRAM_UTURN_R_IMUX11", + "INT_INTERFACE_LH1", + "INT_INTERFACE_BRAM_UTURN_R_IMUX17", + "INT_INTERFACE_LOGIC_OUTS5", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_LH9", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_LH4", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_BRAM_IMUX3", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_BRAM_IMUX32", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_LOGIC_OUTS15", + "INT_INTERFACE_BRAM_IMUX24", + "INT_INTERFACE_LOGIC_OUTS_B19", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_BRAM_UTURN_R_IMUX43", + "INT_INTERFACE_LOGIC_OUTS11", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_BRAM_IMUX8", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LOGIC_OUTS_B17", + "INT_INTERFACE_LH3", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_LOGIC_OUTS_B15", + "INT_INTERFACE_LOGIC_OUTS_B9", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_LOGIC_OUTS_B0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX12", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_BLOCK_OUTS_B1", + "INT_INTERFACE_LOGIC_OUTS_B7", + "INT_INTERFACE_BRAM_UTURN_R_IMUX14", + "INT_INTERFACE_LOGIC_OUTS_B8", + "INT_INTERFACE_LOGIC_OUTS14", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_LOGIC_OUTS8", + "INT_INTERFACE_BRAM_IMUX30", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_BRAM_IMUX6", + "INT_INTERFACE_LOGIC_OUTS12", + "INT_INTERFACE_BRAM_UTURN_R_IMUX36", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_LOGIC_OUTS4", + "INT_INTERFACE_BRAM_UTURN_R_IMUX2", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_LOGIC_OUTS_B3", + "INT_INTERFACE_LOGIC_OUTS21", + "INT_INTERFACE_FAN5", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_BRAM_UTURN_R_IMUX46", + "INT_INTERFACE_LOGIC_OUTS7", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_BRAM_UTURN_R_IMUX30", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_LOGIC_OUTS_B18", + "INT_INTERFACE_BYP5", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_BRAM_IMUX47", + "INT_INTERFACE_BRAM_UTURN_R_IMUX38", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_BRAM_IMUX35", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_LOGIC_OUTS_B4", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_WW4B1", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_LOGIC_OUTS_B21", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_BRAM_IMUX10", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX23", + "INT_INTERFACE_WW4A1", + "INT_INTERFACE_BRAM_IMUX2", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_BRAM_IMUX41", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_BRAM_IMUX45", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX8", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_LH6", + "INT_INTERFACE_BRAM_IMUX20", + "INT_INTERFACE_BRAM_IMUX36", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_LH12", + "INT_INTERFACE_BRAM_UTURN_R_IMUX40", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_WR1END1", + "INT_INTERFACE_LOGIC_OUTS10", + "INT_INTERFACE_BRAM_UTURN_R_IMUX3", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_LOGIC_OUTS13", + "INT_INTERFACE_BRAM_UTURN_R_IMUX47", + "INT_INTERFACE_BRAM_UTURN_R_IMUX44", + "INT_INTERFACE_LOGIC_OUTS_B11", + "INT_INTERFACE_LOGIC_OUTS9", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_BRAM_IMUX40", + "INT_INTERFACE_BRAM_IMUX5", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX13", + "INT_INTERFACE_LOGIC_OUTS_B10", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_LOGIC_OUTS_B5", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_LOGIC_OUTS19", + "INT_INTERFACE_BRAM_UTURN_R_IMUX20", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_BRAM_IMUX26", + "INT_INTERFACE_BLOCK_OUTS_B2", + "INT_INTERFACE_WW4END0", + "INT_INTERFACE_LOGIC_OUTS17", + "INT_INTERFACE_BRAM_IMUX25", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_LOGIC_OUTS_B13", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_EE2A3", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_BRAM_IMUX23", + "INT_INTERFACE_BRAM_IMUX18", + "INT_INTERFACE_LOGIC_OUTS2", + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_BRAM_UTURN_R_IMUX34", + "INT_INTERFACE_LOGIC_OUTS6", + "INT_INTERFACE_BYP7", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_BRAM_IMUX38", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_BRAM_UTURN_R_IMUX32", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX15", + "INT_INTERFACE_LOGIC_OUTS_B12", + "INT_INTERFACE_BRAM_UTURN_R_IMUX22", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + "pips": { + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B2", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B19", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS19", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B4", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B6", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B0", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B21", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS21", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B15", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B22", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS22", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B14", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B5", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B11", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B12", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B16", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS16", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B9", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B23", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS23", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B7", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B13", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B10", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B17", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS17", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B20", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS20", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B8", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B3", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B18", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS18", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_BRAM_L.json b/kintex7/tile_type_BRAM_L.json new file mode 100644 index 0000000..76c8553 --- /dev/null +++ b/kintex7/tile_type_BRAM_L.json @@ -0,0 +1,9834 @@ +{ + "tile_type": "BRAM_L", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "RAMB36", + "type": "RAMBFIFO36E1", + "site_pins": { + "DIADI7": "BRAM_FIFO36_DIADIU3", + "DOBDO10": "BRAM_FIFO36_DOBDOL5", + "WEBWEU4": "BRAM_FIFO36_WEBWEU4", + "TSTCNT5": "BRAM_FIFO36_TSTCNT5", + "DOADO21": "BRAM_FIFO36_DOADOU10", + "DOADO15": "BRAM_FIFO36_DOADOU7", + "DIADI22": "BRAM_FIFO36_DIADIL11", + "ADDRARDADDRU14": "BRAM_FIFO36_ADDRARDADDRU14", + "WEBWEU6": "BRAM_FIFO36_WEBWEU6", + "DOADO23": "BRAM_FIFO36_DOADOU11", + "ADDRBWRADDRL2": "BRAM_FIFO36_ADDRBWRADDRL2", + "DOADO31": "BRAM_FIFO36_DOADOU15", + "DOBDO1": "BRAM_FIFO36_DOBDOU0", + "WEAU3": "BRAM_FIFO36_WEAU3", + "DOBDO21": "BRAM_FIFO36_DOBDOU10", + "ADDRARDADDRL14": "BRAM_FIFO36_ADDRARDADDRL14", + "DOADO27": "BRAM_FIFO36_DOADOU13", + "CLKARDCLKL": "BRAM_FIFO36_CLKARDCLKL", + "DIBDI18": "BRAM_FIFO36_DIBDIL9", + "RDCOUNT2": "BRAM_FIFO36_RDCOUNT2", + "ADDRBWRADDRU11": "BRAM_FIFO36_ADDRBWRADDRU11", + "ADDRARDADDRL11": "BRAM_FIFO36_ADDRARDADDRL11", + "DOADO2": "BRAM_FIFO36_DOADOL1", + "DIBDI6": "BRAM_FIFO36_DIBDIL3", + "WEAU2": "BRAM_FIFO36_WEAU2", + "DIBDI2": "BRAM_FIFO36_DIBDIL1", + "DOADO11": "BRAM_FIFO36_DOADOU5", + "TSTCNT11": "BRAM_FIFO36_TSTCNT11", + "ADDRBWRADDRU14": "BRAM_FIFO36_ADDRBWRADDRU14", + "INJECTDBITERR": "BRAM_FIFO36_INJECTDBITERR", + "DIADI29": "BRAM_FIFO36_DIADIU14", + "ADDRBWRADDRL8": "BRAM_FIFO36_ADDRBWRADDRL8", + "ADDRARDADDRL7": "BRAM_FIFO36_ADDRARDADDRL7", + "WEBWEU3": "BRAM_FIFO36_WEBWEU3", + "TSTRDOS0": "BRAM_FIFO36_TSTRDOS0", + "DOADO19": "BRAM_FIFO36_DOADOU9", + "DIADI8": "BRAM_FIFO36_DIADIL4", + "DIADI13": "BRAM_FIFO36_DIADIU6", + "DIBDI29": "BRAM_FIFO36_DIBDIU14", + "ADDRBWRADDRU12": "BRAM_FIFO36_ADDRBWRADDRU12", + "DOADO24": "BRAM_FIFO36_DOADOL12", + "DIADI27": "BRAM_FIFO36_DIADIU13", + "DIBDI7": "BRAM_FIFO36_DIBDIU3", + "DOADO29": "BRAM_FIFO36_DOADOU14", + "DIADI11": "BRAM_FIFO36_DIADIU5", + "ADDRBWRADDRU1": "BRAM_FIFO36_ADDRBWRADDRU1", + "DIADI31": "BRAM_FIFO36_DIADIU15", + "REGCLKBL": "BRAM_FIFO36_REGCLKBL", + "DOBDO27": "BRAM_FIFO36_DOBDOU13", + "TSTWROS11": "BRAM_FIFO36_TSTWROS11", + "DOBDO23": "BRAM_FIFO36_DOBDOU11", + "RDCOUNT10": "BRAM_FIFO36_RDCOUNT10", + "TSTIN0": "BRAM_FIFO36_TSTIN0", + "DIPADIP1": "BRAM_FIFO36_DIPADIPU0", + "WEBWEL5": "BRAM_FIFO36_WEBWEL5", + "ADDRARDADDRU13": "BRAM_FIFO36_ADDRARDADDRU13", + "REGCEBL": "BRAM_FIFO36_REGCEBL", + "DOADO6": "BRAM_FIFO36_DOADOL3", + "TSTOUT0": "BRAM_FIFO36_TSTOUT0", + "DOBDO0": "BRAM_FIFO36_DOBDOL0", + "RSTRAMARSTRAMU": "BRAM_FIFO36_RSTRAMARSTRAMU", + "WEBWEU2": "BRAM_FIFO36_WEBWEU2", + "RSTRAMBU": "BRAM_FIFO36_RSTRAMBU", + "DIPADIP3": "BRAM_FIFO36_DIPADIPU1", + "DIBDI5": "BRAM_FIFO36_DIBDIU2", + "WRCOUNT12": "BRAM_FIFO36_WRCOUNT12", + "ADDRARDADDRL9": "BRAM_FIFO36_ADDRARDADDRL9", + "ADDRARDADDRL2": "BRAM_FIFO36_ADDRARDADDRL2", + "TSTRDOS2": "BRAM_FIFO36_TSTRDOS2", + "DIBDI13": "BRAM_FIFO36_DIBDIU6", + "DIPADIP2": "BRAM_FIFO36_DIPADIPL1", + "DOADO7": "BRAM_FIFO36_DOADOU3", + "ADDRBWRADDRU6": "BRAM_FIFO36_ADDRBWRADDRU6", + "ADDRBWRADDRU5": "BRAM_FIFO36_ADDRBWRADDRU5", + "TSTWROS1": "BRAM_FIFO36_TSTWROS1", + "DOBDO26": "BRAM_FIFO36_DOBDOL13", + "TSTBRAMRST": "BRAM_FIFO36_TSTBRAMRST", + "REGCLKARDRCLKL": "BRAM_FIFO36_REGCLKARDRCLKL", + "TSTIN2": "BRAM_FIFO36_TSTIN2", + "DIADI14": "BRAM_FIFO36_DIADIL7", + "TSTWROS3": "BRAM_FIFO36_TSTWROS3", + "DIADI21": "BRAM_FIFO36_DIADIU10", + "DOADO3": "BRAM_FIFO36_DOADOU1", + "TSTOUT1": "BRAM_FIFO36_TSTOUT1", + "ECCPARITY7": "BRAM_FIFO36_ECCPARITY7", + "ADDRBWRADDRU9": "BRAM_FIFO36_ADDRBWRADDRU9", + "DOBDO30": "BRAM_FIFO36_DOBDOL15", + "CASCADEOUTB": "BRAM_FIFO36_CASCADEOUTB", + "DIADI28": "BRAM_FIFO36_DIADIL14", + "ADDRARDADDRU4": "BRAM_FIFO36_ADDRARDADDRU4", + "ADDRBWRADDRU2": "BRAM_FIFO36_ADDRBWRADDRU2", + "DIBDI23": "BRAM_FIFO36_DIBDIU11", + "DIBDI8": "BRAM_FIFO36_DIBDIL4", + "DOADO25": "BRAM_FIFO36_DOADOU12", + "DIADI26": "BRAM_FIFO36_DIADIL13", + "ECCPARITY1": "BRAM_FIFO36_ECCPARITY1", + "REGCLKBU": "BRAM_FIFO36_REGCLKBU", + "DOPADOP1": "BRAM_FIFO36_DOPADOPU0", + "TSTRDOS5": "BRAM_FIFO36_TSTRDOS5", + "CASCADEOUTA": "BRAM_FIFO36_CASCADEOUTA", + "ADDRBWRADDRU0": "BRAM_FIFO36_ADDRBWRADDRU0", + "DOBDO12": "BRAM_FIFO36_DOBDOL6", + "WEBWEU7": "BRAM_FIFO36_WEBWEU7", + "DIBDI4": "BRAM_FIFO36_DIBDIL2", + "RSTREGBU": "BRAM_FIFO36_RSTREGBU", + "WEBWEL1": "BRAM_FIFO36_WEBWEL1", + "DIADI19": "BRAM_FIFO36_DIADIU9", + "TSTRDOS3": "BRAM_FIFO36_TSTRDOS3", + "DOADO1": "BRAM_FIFO36_DOADOU0", + "TSTRDCNTOFF": "BRAM_FIFO36_TSTRDCNTOFF", + "DOADO4": "BRAM_FIFO36_DOADOL2", + "RDCOUNT4": "BRAM_FIFO36_RDCOUNT4", + "DIBDI19": "BRAM_FIFO36_DIBDIU9", + "INJECTSBITERR": "BRAM_FIFO36_INJECTSBITERR", + "DOADO30": "BRAM_FIFO36_DOADOL15", + "ADDRBWRADDRL9": "BRAM_FIFO36_ADDRBWRADDRL9", + "DIADI5": "BRAM_FIFO36_DIADIU2", + "DIADI24": "BRAM_FIFO36_DIADIL12", + "DIPBDIP1": "BRAM_FIFO36_DIPBDIPU0", + "DIBDI9": "BRAM_FIFO36_DIBDIU4", + "ADDRARDADDRU8": "BRAM_FIFO36_ADDRARDADDRU8", + "ADDRARDADDRU2": "BRAM_FIFO36_ADDRARDADDRU2", + "DIADI25": "BRAM_FIFO36_DIADIU12", + "ADDRARDADDRU6": "BRAM_FIFO36_ADDRARDADDRU6", + "TSTCNT7": "BRAM_FIFO36_TSTCNT7", + "TSTWROS8": "BRAM_FIFO36_TSTWROS8", + "DOADO14": "BRAM_FIFO36_DOADOL7", + "WRCOUNT4": "BRAM_FIFO36_WRCOUNT4", + "TSTCNT10": "BRAM_FIFO36_TSTCNT10", + "DOPADOP0": "BRAM_FIFO36_DOPADOPL0", + "TSTWROS5": "BRAM_FIFO36_TSTWROS5", + "ADDRARDADDRL13": "BRAM_FIFO36_ADDRARDADDRL13", + "ADDRBWRADDRU3": "BRAM_FIFO36_ADDRBWRADDRU3", + "DOADO22": "BRAM_FIFO36_DOADOL11", + "TSTCNT4": "BRAM_FIFO36_TSTCNT4", + "WEBWEL0": "BRAM_FIFO36_WEBWEL0", + "DOBDO13": "BRAM_FIFO36_DOBDOU6", + "DIADI1": "BRAM_FIFO36_DIADIU0", + "SBITERR": "BRAM_FIFO36_SBITERR", + "TSTWROS9": "BRAM_FIFO36_TSTWROS9", + "WEBWEL7": "BRAM_FIFO36_WEBWEL7", + "WRCOUNT5": "BRAM_FIFO36_WRCOUNT5", + "ADDRARDADDRL12": "BRAM_FIFO36_ADDRARDADDRL12", + "CLKBWRCLKL": "BRAM_FIFO36_CLKBWRCLKL", + "TSTWROS0": "BRAM_FIFO36_TSTWROS0", + "TSTWROS4": "BRAM_FIFO36_TSTWROS4", + "WRCOUNT2": "BRAM_FIFO36_WRCOUNT2", + "ADDRBWRADDRL3": "BRAM_FIFO36_ADDRBWRADDRL3", + "WEBWEL2": "BRAM_FIFO36_WEBWEL2", + "DIPBDIP2": "BRAM_FIFO36_DIPBDIPL1", + "ADDRBWRADDRL10": "BRAM_FIFO36_ADDRBWRADDRL10", + "ADDRBWRADDRL7": "BRAM_FIFO36_ADDRBWRADDRL7", + "ADDRARDADDRU9": "BRAM_FIFO36_ADDRARDADDRU9", + "TSTIN4": "BRAM_FIFO36_TSTIN4", + "ADDRBWRADDRU4": "BRAM_FIFO36_ADDRBWRADDRU4", + "DIBDI14": "BRAM_FIFO36_DIBDIL7", + "ADDRARDADDRL6": "BRAM_FIFO36_ADDRARDADDRL6", + "DIBDI28": "BRAM_FIFO36_DIBDIL14", + "DOBDO31": "BRAM_FIFO36_DOBDOU15", + "WRCOUNT7": "BRAM_FIFO36_WRCOUNT7", + "DIBDI21": "BRAM_FIFO36_DIBDIU10", + "EMPTY": "BRAM_FIFO36_EMPTY", + "WEAU0": "BRAM_FIFO36_WEAU0", + "ADDRARDADDRU7": "BRAM_FIFO36_ADDRARDADDRU7", + "DOBDO28": "BRAM_FIFO36_DOBDOL14", + "TSTCNT9": "BRAM_FIFO36_TSTCNT9", + "DIBDI22": "BRAM_FIFO36_DIBDIL11", + "ADDRBWRADDRU8": "BRAM_FIFO36_ADDRBWRADDRU8", + "ADDRARDADDRU11": "BRAM_FIFO36_ADDRARDADDRU11", + "ENARDENU": "BRAM_FIFO36_ENARDENU", + "TSTFLAGIN": "BRAM_FIFO36_TSTFLAGIN", + "TSTCNT3": "BRAM_FIFO36_TSTCNT3", + "ECCPARITY2": "BRAM_FIFO36_ECCPARITY2", + "ADDRBWRADDRL4": "BRAM_FIFO36_ADDRBWRADDRL4", + "TSTCNT2": "BRAM_FIFO36_TSTCNT2", + "DIADI30": "BRAM_FIFO36_DIADIL15", + "ENARDENL": "BRAM_FIFO36_ENARDENL", + "DIADI23": "BRAM_FIFO36_DIADIU11", + "TSTIN1": "BRAM_FIFO36_TSTIN1", + "WEAL1": "BRAM_FIFO36_WEAL1", + "ALMOSTFULL": "BRAM_FIFO36_ALMOSTFULL", + "DOBDO25": "BRAM_FIFO36_DOBDOU12", + "RDCOUNT8": "BRAM_FIFO36_RDCOUNT8", + "ADDRBWRADDRU10": "BRAM_FIFO36_ADDRBWRADDRU10", + "DOBDO6": "BRAM_FIFO36_DOBDOL3", + "WRCOUNT9": "BRAM_FIFO36_WRCOUNT9", + "RDCOUNT11": "BRAM_FIFO36_RDCOUNT11", + "DOPADOP2": "BRAM_FIFO36_DOPADOPL1", + "WEBWEL4": "BRAM_FIFO36_WEBWEL4", + "DOBDO16": "BRAM_FIFO36_DOBDOL8", + "ADDRBWRADDRL14": "BRAM_FIFO36_ADDRBWRADDRL14", + "DOBDO14": "BRAM_FIFO36_DOBDOL7", + "WEAL0": "BRAM_FIFO36_WEAL0", + "CLKARDCLKU": "BRAM_FIFO36_CLKARDCLKU", + "ADDRARDADDRL10": "BRAM_FIFO36_ADDRARDADDRL10", + "WRCOUNT8": "BRAM_FIFO36_WRCOUNT8", + "DIBDI11": "BRAM_FIFO36_DIBDIU5", + "DIADI3": "BRAM_FIFO36_DIADIU1", + "DOADO12": "BRAM_FIFO36_DOADOL6", + "ADDRBWRADDRL13": "BRAM_FIFO36_ADDRBWRADDRL13", + "WEBWEU0": "BRAM_FIFO36_WEBWEU0", + "ADDRARDADDRU5": "BRAM_FIFO36_ADDRARDADDRU5", + "DIBDI3": "BRAM_FIFO36_DIBDIU1", + "RDCOUNT6": "BRAM_FIFO36_RDCOUNT6", + "REGCLKARDRCLKU": "BRAM_FIFO36_REGCLKARDRCLKU", + "DIPBDIP3": "BRAM_FIFO36_DIPBDIPU1", + "DOBDO3": "BRAM_FIFO36_DOBDOU1", + "WRCOUNT1": "BRAM_FIFO36_WRCOUNT1", + "DIPADIP0": "BRAM_FIFO36_DIPADIPL0", + "TSTOUT4": "BRAM_FIFO36_TSTOUT4", + "DIADI2": "BRAM_FIFO36_DIADIL1", + "TSTWROS2": "BRAM_FIFO36_TSTWROS2", + "RSTREGARSTREGL": "BRAM_FIFO36_RSTREGARSTREGL", + "DIADI4": "BRAM_FIFO36_DIADIL2", + "ADDRARDADDRL0": "BRAM_FIFO36_ADDRARDADDRL0", + "DIADI18": "BRAM_FIFO36_DIADIL9", + "ECCPARITY3": "BRAM_FIFO36_ECCPARITY3", + "RDERR": "BRAM_FIFO36_RDERR", + "DIBDI30": "BRAM_FIFO36_DIBDIL15", + "FULL": "BRAM_FIFO36_FULL", + "RSTRAMARSTRAMLRST": "BRAM_FIFO36_RSTRAMARSTRAMLRST", + "DIBDI10": "BRAM_FIFO36_DIBDIL5", + "DOADO13": "BRAM_FIFO36_DOADOU6", + "ADDRARDADDRL5": "BRAM_FIFO36_ADDRARDADDRL5", + "TSTRDOS4": "BRAM_FIFO36_TSTRDOS4", + "ECCPARITY6": "BRAM_FIFO36_ECCPARITY6", + "DOBDO7": "BRAM_FIFO36_DOBDOU3", + "TSTIN3": "BRAM_FIFO36_TSTIN3", + "ENBWRENL": "BRAM_FIFO36_ENBWRENL", + "DIADI10": "BRAM_FIFO36_DIADIL5", + "ADDRBWRADDRL6": "BRAM_FIFO36_ADDRBWRADDRL6", + "ECCPARITY0": "BRAM_FIFO36_ECCPARITY0", + "TSTOUT2": "BRAM_FIFO36_TSTOUT2", + "ADDRARDADDRU3": "BRAM_FIFO36_ADDRARDADDRU3", + "DIBDI20": "BRAM_FIFO36_DIBDIL10", + "REGCEAREGCEL": "BRAM_FIFO36_REGCEAREGCEL", + "DOADO26": "BRAM_FIFO36_DOADOL13", + "ADDRBWRADDRL0": "BRAM_FIFO36_ADDRBWRADDRL0", + "TSTRDOS12": "BRAM_FIFO36_TSTRDOS12", + "DOADO10": "BRAM_FIFO36_DOADOL5", + "DOBDO22": "BRAM_FIFO36_DOBDOL11", + "DOADO17": "BRAM_FIFO36_DOADOU8", + "DOADO16": "BRAM_FIFO36_DOADOL8", + "TSTWROS6": "BRAM_FIFO36_TSTWROS6", + "ADDRBWRADDRL15": "BRAM_FIFO36_ADDRBWRADDRL15", + "DBITERR": "BRAM_FIFO36_DBITERR", + "TSTRDOS6": "BRAM_FIFO36_TSTRDOS6", + "TSTCNT8": "BRAM_FIFO36_TSTCNT8", + "DOBDO2": "BRAM_FIFO36_DOBDOL1", + "DOBDO19": "BRAM_FIFO36_DOBDOU9", + "DIADI9": "BRAM_FIFO36_DIADIU4", + "WEBWEL6": "BRAM_FIFO36_WEBWEL6", + "ADDRBWRADDRL12": "BRAM_FIFO36_ADDRBWRADDRL12", + "DIBDI26": "BRAM_FIFO36_DIBDIL13", + "DOADO18": "BRAM_FIFO36_DOADOL9", + "WRCOUNT10": "BRAM_FIFO36_WRCOUNT10", + "RSTRAMBL": "BRAM_FIFO36_RSTRAMBL", + "TSTOUT3": "BRAM_FIFO36_TSTOUT3", + "WRCOUNT0": "BRAM_FIFO36_WRCOUNT0", + "WEAL3": "BRAM_FIFO36_WEAL3", + "DOADO20": "BRAM_FIFO36_DOADOL10", + "WEBWEL3": "BRAM_FIFO36_WEBWEL3", + "DOBDO18": "BRAM_FIFO36_DOBDOL9", + "ADDRARDADDRL1": "BRAM_FIFO36_ADDRARDADDRL1", + "ADDRARDADDRL3": "BRAM_FIFO36_ADDRARDADDRL3", + "ADDRBWRADDRL11": "BRAM_FIFO36_ADDRBWRADDRL11", + "TSTWRCNTOFF": "BRAM_FIFO36_TSTWRCNTOFF", + "DOADO28": "BRAM_FIFO36_DOADOL14", + "WRCOUNT3": "BRAM_FIFO36_WRCOUNT3", + "DOBDO15": "BRAM_FIFO36_DOBDOU7", + "ENBWRENU": "BRAM_FIFO36_ENBWRENU", + "DOBDO17": "BRAM_FIFO36_DOBDOU8", + "DIBDI0": "BRAM_FIFO36_DIBDIL0", + "ECCPARITY5": "BRAM_FIFO36_ECCPARITY5", + "WRERR": "BRAM_FIFO36_WRERR", + "RDCOUNT1": "BRAM_FIFO36_RDCOUNT1", + "RSTREGBL": "BRAM_FIFO36_RSTREGBL", + "TSTCNT6": "BRAM_FIFO36_TSTCNT6", + "RDCOUNT7": "BRAM_FIFO36_RDCOUNT7", + "DOADO8": "BRAM_FIFO36_DOADOL4", + "DOADO5": "BRAM_FIFO36_DOADOU2", + "TSTRDOS8": "BRAM_FIFO36_TSTRDOS8", + "ADDRARDADDRU12": "BRAM_FIFO36_ADDRARDADDRU12", + "ADDRBWRADDRL1": "BRAM_FIFO36_ADDRBWRADDRL1", + "TSTWROS10": "BRAM_FIFO36_TSTWROS10", + "DIBDI31": "BRAM_FIFO36_DIBDIU15", + "ADDRARDADDRU0": "BRAM_FIFO36_ADDRARDADDRU0", + "CASCADEINA": "BRAM_FIFO36_CASCADEINA", + "DIBDI16": "BRAM_FIFO36_DIBDIL8", + "DIADI6": "BRAM_FIFO36_DIADIL3", + "RDCOUNT3": "BRAM_FIFO36_RDCOUNT3", + "DIBDI27": "BRAM_FIFO36_DIBDIU13", + "WRCOUNT11": "BRAM_FIFO36_WRCOUNT11", + "WEAU1": "BRAM_FIFO36_WEAU1", + "TSTCNT0": "BRAM_FIFO36_TSTCNT0", + "DIBDI25": "BRAM_FIFO36_DIBDIU12", + "DIBDI12": "BRAM_FIFO36_DIBDIL6", + "TSTRDOS11": "BRAM_FIFO36_TSTRDOS11", + "RDCOUNT5": "BRAM_FIFO36_RDCOUNT5", + "RDCOUNT9": "BRAM_FIFO36_RDCOUNT9", + "DIBDI17": "BRAM_FIFO36_DIBDIU8", + "DOPBDOP2": "BRAM_FIFO36_DOPBDOPL1", + "CASCADEINB": "BRAM_FIFO36_CASCADEINB", + "ECCPARITY4": "BRAM_FIFO36_ECCPARITY4", + "ADDRBWRADDRU7": "BRAM_FIFO36_ADDRBWRADDRU7", + "TSTWROS12": "BRAM_FIFO36_TSTWROS12", + "ADDRARDADDRL4": "BRAM_FIFO36_ADDRARDADDRL4", + "DOPBDOP3": "BRAM_FIFO36_DOPBDOPU1", + "WEAL2": "BRAM_FIFO36_WEAL2", + "WRCOUNT6": "BRAM_FIFO36_WRCOUNT6", + "DOBDO29": "BRAM_FIFO36_DOBDOU14", + "DOBDO5": "BRAM_FIFO36_DOBDOU2", + "ADDRARDADDRL15": "BRAM_FIFO36_ADDRARDADDRL15", + "DOPBDOP0": "BRAM_FIFO36_DOPBDOPL0", + "WEBWEU1": "BRAM_FIFO36_WEBWEU1", + "DIADI20": "BRAM_FIFO36_DIADIL10", + "RDCOUNT0": "BRAM_FIFO36_RDCOUNT0", + "DOBDO11": "BRAM_FIFO36_DOBDOU5", + "ADDRARDADDRU10": "BRAM_FIFO36_ADDRARDADDRU10", + "DOBDO24": "BRAM_FIFO36_DOBDOL12", + "TSTRDOS10": "BRAM_FIFO36_TSTRDOS10", + "TSTCNT12": "BRAM_FIFO36_TSTCNT12", + "DIPBDIP0": "BRAM_FIFO36_DIPBDIPL0", + "ADDRARDADDRL8": "BRAM_FIFO36_ADDRARDADDRL8", + "ADDRBWRADDRU13": "BRAM_FIFO36_ADDRBWRADDRU13", + "DOBDO8": "BRAM_FIFO36_DOBDOL4", + "DIADI17": "BRAM_FIFO36_DIADIU8", + "RSTREGARSTREGU": "BRAM_FIFO36_RSTREGARSTREGU", + "REGCEBU": "BRAM_FIFO36_REGCEBU", + "TSTRDOS1": "BRAM_FIFO36_TSTRDOS1", + "DIADI0": "BRAM_FIFO36_DIADIL0", + "DIBDI1": "BRAM_FIFO36_DIBDIU0", + "ADDRARDADDRU1": "BRAM_FIFO36_ADDRARDADDRU1", + "DOBDO9": "BRAM_FIFO36_DOBDOU4", + "TSTRDOS9": "BRAM_FIFO36_TSTRDOS9", + "DOADO9": "BRAM_FIFO36_DOADOU4", + "ALMOSTEMPTY": "BRAM_FIFO36_ALMOSTEMPTY", + "DIADI16": "BRAM_FIFO36_DIADIL8", + "DOPBDOP1": "BRAM_FIFO36_DOPBDOPU0", + "DOADO0": "BRAM_FIFO36_DOADOL0", + "ADDRBWRADDRL5": "BRAM_FIFO36_ADDRBWRADDRL5", + "DIBDI15": "BRAM_FIFO36_DIBDIU7", + "CLKBWRCLKU": "BRAM_FIFO36_CLKBWRCLKU", + "TSTOFF": "BRAM_FIFO36_TSTOFF", + "DOBDO4": "BRAM_FIFO36_DOBDOL2", + "TSTCNT1": "BRAM_FIFO36_TSTCNT1", + "DOPADOP3": "BRAM_FIFO36_DOPADOPU1", + "DOBDO20": "BRAM_FIFO36_DOBDOL10", + "REGCEAREGCEU": "BRAM_FIFO36_REGCEAREGCEU", + "RDCOUNT12": "BRAM_FIFO36_RDCOUNT12", + "DIADI15": "BRAM_FIFO36_DIADIU7", + "TSTRDOS7": "BRAM_FIFO36_TSTRDOS7", + "DIBDI24": "BRAM_FIFO36_DIBDIL12", + "DIADI12": "BRAM_FIFO36_DIADIL6", + "TSTWROS7": "BRAM_FIFO36_TSTWROS7", + "WEBWEU5": "BRAM_FIFO36_WEBWEU5" + }, + "x_coord": 0 + }, + { + "y_coord": 39, + "name": "X0Y39", + "prefix": "RAMB18", + "type": "FIFO18E1", + "site_pins": { + "WREN": "BRAM_FIFO18_ENBWREN", + "REGCEB": "BRAM_FIFO18_REGCEB", + "DIADI7": "BRAM_FIFO18_DIADI7", + "ADDRBTIEHIGH0": "BRAM_FIFO18_ADDRBTIEHIGH0", + "RDCOUNT2": "BRAM_FIFO18_RDCOUNT2", + "WRCOUNT3": "BRAM_FIFO18_WRCOUNT3", + "WRCLK": "BRAM_FIFO18_CLKBWRCLK", + "DO2": "BRAM_FIFO18_DOADO2", + "DIBDI3": "BRAM_FIFO18_DIBDI3", + "RDCOUNT0": "BRAM_FIFO18_RDCOUNT0", + "ADDRBWRADDR10": "BRAM_FIFO18_ADDRBWRADDR10", + "DIBDI1": "BRAM_FIFO18_DIBDI1", + "ADDRARDADDR8": "BRAM_FIFO18_ADDRARDADDR8", + "WEBWE5": "BRAM_FIFO18_WEBWE5", + "ADDRBWRADDR13": "BRAM_FIFO18_ADDRBWRADDR13", + "RSTREGB": "BRAM_FIFO18_RSTREGB", + "WRERR": "BRAM_FIFO18_WRERR", + "ALMOSTFULL": "BRAM_FIFO18_ALMOSTFULL", + "RDCOUNT8": "BRAM_FIFO18_RDCOUNT8", + "DO8": "BRAM_FIFO18_DOADO8", + "RDCOUNT7": "BRAM_FIFO18_RDCOUNT7", + "RDCOUNT5": "BRAM_FIFO18_RDCOUNT5", + "ADDRBTIEHIGH1": "BRAM_FIFO18_ADDRBTIEHIGH1", + "WRCOUNT9": "BRAM_FIFO18_WRCOUNT9", + "ADDRBWRADDR5": "BRAM_FIFO18_ADDRBWRADDR5", + "ADDRBWRADDR3": "BRAM_FIFO18_ADDRBWRADDR3", + "DIBDI0": "BRAM_FIFO18_DIBDI0", + "ADDRARDADDR6": "BRAM_FIFO18_ADDRARDADDR6", + "DO23": "BRAM_FIFO18_DOBDO7", + "REGCLKB": "BRAM_FIFO18_REGCLKB", + "RDCOUNT11": "BRAM_FIFO18_RDCOUNT11", + "DIBDI9": "BRAM_FIFO18_DIBDI9", + "DO29": "BRAM_FIFO18_DOBDO13", + "ADDRARDADDR13": "BRAM_FIFO18_ADDRARDADDR13", + "RSTREG": "BRAM_FIFO18_RSTREGARSTREG", + "RDCOUNT9": "BRAM_FIFO18_RDCOUNT9", + "WEA1": "BRAM_FIFO18_WEA1", + "DO9": "BRAM_FIFO18_DOADO9", + "ADDRBWRADDR6": "BRAM_FIFO18_ADDRBWRADDR6", + "RDRCLK": "BRAM_FIFO18_REGCLKARDRCLK", + "DO15": "BRAM_FIFO18_DOADO15", + "DIADI6": "BRAM_FIFO18_DIADI6", + "RDCOUNT4": "BRAM_FIFO18_RDCOUNT4", + "WEBWE4": "BRAM_FIFO18_WEBWE4", + "DIBDI6": "BRAM_FIFO18_DIBDI6", + "WRCOUNT8": "BRAM_FIFO18_WRCOUNT8", + "DIBDI11": "BRAM_FIFO18_DIBDI11", + "ADDRBWRADDR8": "BRAM_FIFO18_ADDRBWRADDR8", + "DIADI3": "BRAM_FIFO18_DIADI3", + "DIADI5": "BRAM_FIFO18_DIADI5", + "DIBDI2": "BRAM_FIFO18_DIBDI2", + "ADDRARDADDR1": "BRAM_FIFO18_ADDRARDADDR1", + "DIBDI12": "BRAM_FIFO18_DIBDI12", + "ADDRARDADDR5": "BRAM_FIFO18_ADDRARDADDR5", + "RDEN": "BRAM_FIFO18_ENARDEN", + "WEBWE6": "BRAM_FIFO18_WEBWE6", + "DIPBDIP1": "BRAM_FIFO18_DIPBDIP1", + "ADDRBWRADDR0": "BRAM_FIFO18_ADDRBWRADDR0", + "RDCOUNT6": "BRAM_FIFO18_RDCOUNT6", + "ADDRBWRADDR12": "BRAM_FIFO18_ADDRBWRADDR12", + "DO27": "BRAM_FIFO18_DOBDO11", + "DO25": "BRAM_FIFO18_DOBDO9", + "ADDRBWRADDR11": "BRAM_FIFO18_ADDRBWRADDR11", + "DO26": "BRAM_FIFO18_DOBDO10", + "WEBWE3": "BRAM_FIFO18_WEBWE3", + "ADDRBWRADDR4": "BRAM_FIFO18_ADDRBWRADDR4", + "WRCOUNT7": "BRAM_FIFO18_WRCOUNT7", + "WRCOUNT1": "BRAM_FIFO18_WRCOUNT1", + "DIPADIP0": "BRAM_FIFO18_DIPADIP0", + "DIADI2": "BRAM_FIFO18_DIADI2", + "ADDRARDADDR2": "BRAM_FIFO18_ADDRARDADDR2", + "ADDRBWRADDR7": "BRAM_FIFO18_ADDRBWRADDR7", + "DIBDI5": "BRAM_FIFO18_DIBDI5", + "DO10": "BRAM_FIFO18_DOADO10", + "DIADI8": "BRAM_FIFO18_DIADI8", + "DO16": "BRAM_FIFO18_DOBDO0", + "DIADI13": "BRAM_FIFO18_DIADI13", + "ADDRARDADDR4": "BRAM_FIFO18_ADDRARDADDR4", + "DO11": "BRAM_FIFO18_DOADO11", + "DO0": "BRAM_FIFO18_DOADO0", + "DO18": "BRAM_FIFO18_DOBDO2", + "DIADI14": "BRAM_FIFO18_DIADI14", + "ADDRBWRADDR2": "BRAM_FIFO18_ADDRBWRADDR2", + "ADDRARDADDR10": "BRAM_FIFO18_ADDRARDADDR10", + "DOP3": "BRAM_FIFO18_DOPBDOP1", + "ADDRARDADDR9": "BRAM_FIFO18_ADDRARDADDR9", + "RDERR": "BRAM_FIFO18_RDERR", + "DO6": "BRAM_FIFO18_DOADO6", + "FULL": "BRAM_FIFO18_FULL", + "DO24": "BRAM_FIFO18_DOBDO8", + "DIBDI10": "BRAM_FIFO18_DIBDI10", + "DIBDI7": "BRAM_FIFO18_DIBDI7", + "WEA3": "BRAM_FIFO18_WEA3", + "DIADI0": "BRAM_FIFO18_DIADI0", + "DO20": "BRAM_FIFO18_DOBDO4", + "WEBWE1": "BRAM_FIFO18_WEBWE1", + "ADDRBWRADDR9": "BRAM_FIFO18_ADDRBWRADDR9", + "ADDRBWRADDR1": "BRAM_FIFO18_ADDRBWRADDR1", + "DO21": "BRAM_FIFO18_DOBDO5", + "DIADI10": "BRAM_FIFO18_DIADI10", + "DO14": "BRAM_FIFO18_DOADO14", + "DO12": "BRAM_FIFO18_DOADO12", + "DO22": "BRAM_FIFO18_DOBDO6", + "DIADI12": "BRAM_FIFO18_DIADI12", + "DO17": "BRAM_FIFO18_DOBDO1", + "DO13": "BRAM_FIFO18_DOADO13", + "DO19": "BRAM_FIFO18_DOBDO3", + "DOP1": "BRAM_FIFO18_DOPADOP1", + "DIBDI14": "BRAM_FIFO18_DIBDI14", + "DIBDI8": "BRAM_FIFO18_DIBDI8", + "DOP2": "BRAM_FIFO18_DOPBDOP0", + "RDCOUNT3": "BRAM_FIFO18_RDCOUNT3", + "RDCLK": "BRAM_FIFO18_CLKARDCLK", + "WEBWE2": "BRAM_FIFO18_WEBWE2", + "RDCOUNT10": "BRAM_FIFO18_RDCOUNT10", + "DOP0": "BRAM_FIFO18_DOPADOP0", + "WRCOUNT5": "BRAM_FIFO18_WRCOUNT5", + "ADDRATIEHIGH1": "BRAM_FIFO18_ADDRATIEHIGH1", + "DIPADIP1": "BRAM_FIFO18_DIPADIP1", + "DIBDI4": "BRAM_FIFO18_DIBDI4", + "ALMOSTEMPTY": "BRAM_FIFO18_ALMOSTEMPTY", + "WRCOUNT2": "BRAM_FIFO18_WRCOUNT2", + "DIADI11": "BRAM_FIFO18_DIADI11", + "ADDRARDADDR3": "BRAM_FIFO18_ADDRARDADDR3", + "WRCOUNT11": "BRAM_FIFO18_WRCOUNT11", + "DO1": "BRAM_FIFO18_DOADO1", + "ADDRARDADDR12": "BRAM_FIFO18_ADDRARDADDR12", + "WEBWE0": "BRAM_FIFO18_WEBWE0", + "ADDRARDADDR7": "BRAM_FIFO18_ADDRARDADDR7", + "DO31": "BRAM_FIFO18_DOBDO15", + "DO5": "BRAM_FIFO18_DOADO5", + "ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0", + "RDCOUNT1": "BRAM_FIFO18_RDCOUNT1", + "RST": "BRAM_FIFO18_RSTRAMARSTRAM", + "WEBWE7": "BRAM_FIFO18_WEBWE7", + "ADDRARDADDR11": "BRAM_FIFO18_ADDRARDADDR11", + "WEA0": "BRAM_FIFO18_WEA0", + "DIADI9": "BRAM_FIFO18_DIADI9", + "REGCE": "BRAM_FIFO18_REGCEAREGCE", + "DIBDI15": "BRAM_FIFO18_DIBDI15", + "DO4": "BRAM_FIFO18_DOADO4", + "RSTRAMB": "BRAM_FIFO18_RSTRAMB", + "DO7": "BRAM_FIFO18_DOADO7", + "WRCOUNT10": "BRAM_FIFO18_WRCOUNT10", + "DIBDI13": "BRAM_FIFO18_DIBDI13", + "DIADI4": "BRAM_FIFO18_DIADI4", + "DO3": "BRAM_FIFO18_DOADO3", + "DIADI1": "BRAM_FIFO18_DIADI1", + "WEA2": "BRAM_FIFO18_WEA2", + "DO30": "BRAM_FIFO18_DOBDO14", + "WRCOUNT4": "BRAM_FIFO18_WRCOUNT4", + "EMPTY": "BRAM_FIFO18_EMPTY", + "WRCOUNT6": "BRAM_FIFO18_WRCOUNT6", + "WRCOUNT0": "BRAM_FIFO18_WRCOUNT0", + "DIADI15": "BRAM_FIFO18_DIADI15", + "DIPBDIP0": "BRAM_FIFO18_DIPBDIP0", + "ADDRATIEHIGH0": "BRAM_FIFO18_ADDRATIEHIGH0", + "DO28": "BRAM_FIFO18_DOBDO12" + }, + "x_coord": 0 + }, + { + "y_coord": 40, + "name": "X0Y40", + "prefix": "RAMB18", + "type": "RAMB18E1", + "site_pins": { + "DOADO5": "BRAM_RAMB18_DOADO5", + "REGCEB": "BRAM_RAMB18_REGCEB", + "ADDRATIEHIGH0": "BRAM_RAMB18_ADDRATIEHIGH0", + "ADDRARDADDR11": "BRAM_RAMB18_ADDRARDADDR11", + "DIADI14": "BRAM_RAMB18_DIADI14", + "DOBDO10": "BRAM_RAMB18_DOBDO10", + "ADDRBTIEHIGH0": "BRAM_RAMB18_ADDRBTIEHIGH0", + "RDCOUNT2": "BRAM_RAMB18_RDCOUNT2", + "WRCOUNT3": "BRAM_RAMB18_WRCOUNT3", + "WEA2": "BRAM_RAMB18_WEA2", + "DIBDI3": "BRAM_RAMB18_DIBDI3", + "DOADO3": "BRAM_RAMB18_DOADO3", + "DOADO15": "BRAM_RAMB18_DOADO15", + "DIADI6": "BRAM_RAMB18_DIADI6", + "ADDRBWRADDR10": "BRAM_RAMB18_ADDRBWRADDR10", + "DOADO8": "BRAM_RAMB18_DOADO8", + "DOBDO15": "BRAM_RAMB18_DOBDO15", + "ADDRARDADDR8": "BRAM_RAMB18_ADDRARDADDR8", + "WEBWE5": "BRAM_RAMB18_WEBWE5", + "DIBDI0": "BRAM_RAMB18_DIBDI0", + "DOADO6": "BRAM_RAMB18_DOADO6", + "ADDRBWRADDR13": "BRAM_RAMB18_ADDRBWRADDR13", + "RSTREGB": "BRAM_RAMB18_RSTREGB", + "WRERR": "BRAM_RAMB18_WRERR", + "ALMOSTFULL": "BRAM_RAMB18_ALMOSTFULL", + "RDCOUNT8": "BRAM_RAMB18_RDCOUNT8", + "RDCOUNT7": "BRAM_RAMB18_RDCOUNT7", + "DOBDO6": "BRAM_RAMB18_DOBDO6", + "ADDRBTIEHIGH1": "BRAM_RAMB18_ADDRBTIEHIGH1", + "WRCOUNT9": "BRAM_RAMB18_WRCOUNT9", + "ADDRBWRADDR5": "BRAM_RAMB18_ADDRBWRADDR5", + "ADDRBWRADDR3": "BRAM_RAMB18_ADDRBWRADDR3", + "DIBDI9": "BRAM_RAMB18_DIBDI9", + "DOBDO1": "BRAM_RAMB18_DOBDO1", + "RSTREGARSTREG": "BRAM_RAMB18_RSTREGARSTREG", + "DOBDO12": "BRAM_RAMB18_DOBDO12", + "DOBDO9": "BRAM_RAMB18_DOBDO9", + "REGCLKB": "BRAM_RAMB18_REGCLKB", + "RDCOUNT11": "BRAM_RAMB18_RDCOUNT11", + "DIBDI4": "BRAM_RAMB18_DIBDI4", + "ADDRARDADDR13": "BRAM_RAMB18_ADDRARDADDR13", + "REGCLKARDRCLK": "BRAM_RAMB18_REGCLKARDRCLK", + "RDCOUNT9": "BRAM_RAMB18_RDCOUNT9", + "WEA1": "BRAM_RAMB18_WEA1", + "DOBDO14": "BRAM_RAMB18_DOBDO14", + "ADDRBWRADDR6": "BRAM_RAMB18_ADDRBWRADDR6", + "DOADO1": "BRAM_RAMB18_DOADO1", + "DIBDI7": "BRAM_RAMB18_DIBDI7", + "DOADO2": "BRAM_RAMB18_DOADO2", + "RDCOUNT4": "BRAM_RAMB18_RDCOUNT4", + "WEBWE4": "BRAM_RAMB18_WEBWE4", + "DIBDI6": "BRAM_RAMB18_DIBDI6", + "WRCOUNT8": "BRAM_RAMB18_WRCOUNT8", + "DIBDI11": "BRAM_RAMB18_DIBDI11", + "ADDRBWRADDR8": "BRAM_RAMB18_ADDRBWRADDR8", + "DIADI3": "BRAM_RAMB18_DIADI3", + "DOADO12": "BRAM_RAMB18_DOADO12", + "DIBDI2": "BRAM_RAMB18_DIBDI2", + "ADDRARDADDR1": "BRAM_RAMB18_ADDRARDADDR1", + "DOADO11": "BRAM_RAMB18_DOADO11", + "DIBDI12": "BRAM_RAMB18_DIBDI12", + "ADDRARDADDR5": "BRAM_RAMB18_ADDRARDADDR5", + "WEBWE6": "BRAM_RAMB18_WEBWE6", + "DIPBDIP1": "BRAM_RAMB18_DIPBDIP1", + "ADDRBWRADDR0": "BRAM_RAMB18_ADDRBWRADDR0", + "RDCOUNT6": "BRAM_RAMB18_RDCOUNT6", + "ADDRBWRADDR12": "BRAM_RAMB18_ADDRBWRADDR12", + "ADDRBWRADDR11": "BRAM_RAMB18_ADDRBWRADDR11", + "WEBWE3": "BRAM_RAMB18_WEBWE3", + "DOBDO3": "BRAM_RAMB18_DOBDO3", + "WRCOUNT7": "BRAM_RAMB18_WRCOUNT7", + "WRCOUNT1": "BRAM_RAMB18_WRCOUNT1", + "ADDRBWRADDR4": "BRAM_RAMB18_ADDRBWRADDR4", + "DIPADIP0": "BRAM_RAMB18_DIPADIP0", + "REGCEAREGCE": "BRAM_RAMB18_REGCEAREGCE", + "DIADI2": "BRAM_RAMB18_DIADI2", + "DOADO14": "BRAM_RAMB18_DOADO14", + "ADDRBWRADDR7": "BRAM_RAMB18_ADDRBWRADDR7", + "ADDRARDADDR12": "BRAM_RAMB18_ADDRARDADDR12", + "DIADI8": "BRAM_RAMB18_DIADI8", + "DIADI13": "BRAM_RAMB18_DIADI13", + "ADDRARDADDR4": "BRAM_RAMB18_ADDRARDADDR4", + "DIADI4": "BRAM_RAMB18_DIADI4", + "DOADO7": "BRAM_RAMB18_DOADO7", + "DOBDO7": "BRAM_RAMB18_DOBDO7", + "DOBDO5": "BRAM_RAMB18_DOBDO5", + "ADDRBWRADDR2": "BRAM_RAMB18_ADDRBWRADDR2", + "ADDRARDADDR10": "BRAM_RAMB18_ADDRARDADDR10", + "ADDRARDADDR9": "BRAM_RAMB18_ADDRARDADDR9", + "RDERR": "BRAM_RAMB18_RDERR", + "FULL": "BRAM_RAMB18_FULL", + "RDCOUNT0": "BRAM_RAMB18_RDCOUNT0", + "DIBDI10": "BRAM_RAMB18_DIBDI10", + "DOADO13": "BRAM_RAMB18_DOADO13", + "WEA3": "BRAM_RAMB18_WEA3", + "DIADI0": "BRAM_RAMB18_DIADI0", + "ADDRBWRADDR1": "BRAM_RAMB18_ADDRBWRADDR1", + "WEBWE1": "BRAM_RAMB18_WEBWE1", + "ADDRBWRADDR9": "BRAM_RAMB18_ADDRBWRADDR9", + "DIADI7": "BRAM_RAMB18_DIADI7", + "RDCOUNT1": "BRAM_RAMB18_RDCOUNT1", + "DIADI10": "BRAM_RAMB18_DIADI10", + "DOADO10": "BRAM_RAMB18_DOADO10", + "DOBDO8": "BRAM_RAMB18_DOBDO8", + "DIBDI14": "BRAM_RAMB18_DIBDI14", + "DOADO0": "BRAM_RAMB18_DOADO0", + "DOADO4": "BRAM_RAMB18_DOADO4", + "DIADI1": "BRAM_RAMB18_DIADI1", + "WRCOUNT11": "BRAM_RAMB18_WRCOUNT11", + "DIBDI8": "BRAM_RAMB18_DIBDI8", + "DIBDI1": "BRAM_RAMB18_DIBDI1", + "RDCOUNT3": "BRAM_RAMB18_RDCOUNT3", + "ADDRARDADDR2": "BRAM_RAMB18_ADDRARDADDR2", + "WEBWE2": "BRAM_RAMB18_WEBWE2", + "ENARDEN": "BRAM_RAMB18_ENARDEN", + "RDCOUNT10": "BRAM_RAMB18_RDCOUNT10", + "DOPBDOP0": "BRAM_RAMB18_DOPBDOP0", + "DOADO9": "BRAM_RAMB18_DOADO9", + "WRCOUNT5": "BRAM_RAMB18_WRCOUNT5", + "ADDRATIEHIGH1": "BRAM_RAMB18_ADDRATIEHIGH1", + "DIPADIP1": "BRAM_RAMB18_DIPADIP1", + "ALMOSTEMPTY": "BRAM_RAMB18_ALMOSTEMPTY", + "WRCOUNT2": "BRAM_RAMB18_WRCOUNT2", + "DIADI11": "BRAM_RAMB18_DIADI11", + "DOPBDOP1": "BRAM_RAMB18_DOPBDOP1", + "ADDRARDADDR3": "BRAM_RAMB18_ADDRARDADDR3", + "WRCOUNT6": "BRAM_RAMB18_WRCOUNT6", + "WEBWE0": "BRAM_RAMB18_WEBWE0", + "DOBDO13": "BRAM_RAMB18_DOBDO13", + "DOBDO0": "BRAM_RAMB18_DOBDO0", + "ADDRARDADDR7": "BRAM_RAMB18_ADDRARDADDR7", + "DOPADOP0": "BRAM_RAMB18_DOPADOP0", + "ADDRARDADDR0": "BRAM_RAMB18_ADDRARDADDR0", + "CLKARDCLK": "BRAM_RAMB18_CLKARDCLK", + "WEA0": "BRAM_RAMB18_WEA0", + "ADDRARDADDR6": "BRAM_RAMB18_ADDRARDADDR6", + "WEBWE7": "BRAM_RAMB18_WEBWE7", + "DOBDO2": "BRAM_RAMB18_DOBDO2", + "DOBDO11": "BRAM_RAMB18_DOBDO11", + "DIADI9": "BRAM_RAMB18_DIADI9", + "DIBDI5": "BRAM_RAMB18_DIBDI5", + "DIBDI15": "BRAM_RAMB18_DIBDI15", + "CLKBWRCLK": "BRAM_RAMB18_CLKBWRCLK", + "DIADI5": "BRAM_RAMB18_DIADI5", + "RSTRAMB": "BRAM_RAMB18_RSTRAMB", + "DOBDO4": "BRAM_RAMB18_DOBDO4", + "WRCOUNT10": "BRAM_RAMB18_WRCOUNT10", + "DIBDI13": "BRAM_RAMB18_DIBDI13", + "WRCOUNT4": "BRAM_RAMB18_WRCOUNT4", + "EMPTY": "BRAM_RAMB18_EMPTY", + "RDCOUNT5": "BRAM_RAMB18_RDCOUNT5", + "WRCOUNT0": "BRAM_RAMB18_WRCOUNT0", + "DIADI15": "BRAM_RAMB18_DIADI15", + "DIPBDIP0": "BRAM_RAMB18_DIPBDIP0", + "DOPADOP1": "BRAM_RAMB18_DOPADOP1", + "RSTRAMARSTRAM": "BRAM_RAMB18_RSTRAMARSTRAM", + "DIADI12": "BRAM_RAMB18_DIADI12", + "ENBWREN": "BRAM_RAMB18_ENBWREN" + }, + "x_coord": 0 + } + ], + "wires": [ + "BRAM_EE4BEG1_2", + "BRAM_IMUX34_4", + "BRAM_IMUX31_1", + "BRAM_CASCOUT_ADDRARDADDRU8", + "BRAM_IMUX7_1", + "BRAM_IMUX26_3", + "BRAM_IMUX22_UTURN_0", + "BRAM_IMUX21_UTURN_0", + "BRAM_WW2END1_1", + "BRAM_IMUX36_1", + "BRAM_LH6_2", + "BRAM_FIFO36_ADDRARDADDRU6", + "BRAM_IMUX30_UTURN_2", + "BRAM_FIFO36_TSTCNT2", + "BRAM_FIFO36_TSTIN2", + "BRAM_WW4B2_1", + "BRAM_EL1BEG0_3", + "BRAM_WW4A1_4", + "BRAM_FIFO18_ADDRARDADDR8", + "BRAM_IMUX25_UTURN_4", + "BRAM_FIFO18_ADDRATIEHIGH0", + "BRAM_SE4BEG0_0", + "BRAM_SW2A0_4", + "BRAM_CTRL1_0", + "BRAM_FIFO36_DOBDOU7", + "BRAM_IMUX16_1", + "BRAM_FIFO18_ADDRBWRADDR12", + "BRAM_WW2A2_1", + "BRAM_FIFO36_DOBDOU14", + "BRAM_ER1BEG3_1", + "BRAM_EE2BEG3_4", + "BRAM_IMUX3_UTURN_3", + "BRAM_FIFO36_WRCOUNT2", + "BRAM_SW2A2_3", + "BRAM_WW2END2_4", + "BRAM_IMUX_ADDRARDADDRU14", + "BRAM_IMUX43_UTURN_4", + "BRAM_IMUX13_2", + "BRAM_FIFO36_DIBDIU11", + "BRAM_FIFO36_DIADIU6", + "BRAM_IMUX_ADDRBWRADDRL3", + "BRAM_FIFO36_DIPADIPL0", + "BRAM_FIFO36_ADDRBWRADDRU11", + "BRAM_IMUX25_0", + "BRAM_WL1END1_2", + "BRAM_BLOCK_OUTS_L_B3_3", + "BRAM_EE2BEG2_4", + "BRAM_FIFO36_ADDRBWRADDRL10", + "BRAM_BYP5_0", + "BRAM_FAN7_4", + "BRAM_RAMB18_DOADO8", + "BRAM_FIFO36_ADDRBWRADDRL7", + "BRAM_CASCINTOP_ADDRARDADDRU6", + "BRAM_FIFO36_DOADOU6", + "BRAM_RAMB18_DIPBDIP1", + "BRAM_RAMB18_ADDRARDADDR7", + "BRAM_NE4C2_0", + "BRAM_WL1END1_1", + "BRAM_EL1BEG3_4", + "BRAM_IMUX_ADDRBWRADDRL1", + "BRAM_EE2BEG2_0", + "BRAM_FIFO36_TSTOUT1", + "BRAM_LOGIC_OUTS_B13_1", + "BRAM_FIFO36_TSTCNT0", + "BRAM_EE2A2_0", + "BRAM_EE2BEG0_2", + "BRAM_LH9_4", + "BRAM_IMUX1_1", + "BRAM_UTURN_ADDRARDADDRU3", + "BRAM_UTURN_ADDRBWRADDRL3", + "BRAM_LH12_1", + "BRAM_IMUX13_0", + "BRAM_IMUX31_4", + "BRAM_RAMB18_DOPBDOP0", + "BRAM_ADDRARDADDRU10", + "BRAM_EE4A2_1", + "BRAM_IMUX11_UTURN_1", + "BRAM_RAMB18_DOBDO4", + "BRAM_FIFO18_DIBDI13", + "BRAM_FIFO36_WEBWEL1", + "BRAM_IMUX38_UTURN_3", + "BRAM_EE2BEG2_2", + "BRAM_WW2END3_2", + "BRAM_BYP0_4", + "BRAM_IMUX1_UTURN_2", + "BRAM_RAMB18_RDCOUNT8", + "BRAM_EE4B3_1", + "BRAM_BYP6_4", + "BRAM_ADDRARDADDRL8", + "BRAM_FIFO18_DOBDO0", + "BRAM_NE2A1_0", + "BRAM_FIFO18_DIBDI9", + "BRAM_SE4BEG3_4", + "BRAM_BLOCK_OUTS_L_B2_2", + "BRAM_LOGIC_OUTS_B18_4", + "BRAM_IMUX9_UTURN_4", + "BRAM_IMUX16_UTURN_0", + "BRAM_FIFO18_DIBDI10", + "BRAM_EL1BEG2_0", + "BRAM_FIFO36_DBITERR", + "BRAM_CTRL0_0", + "BRAM_FIFO18_ADDRARDADDR0", + "BRAM_NW4A0_0", + "BRAM_IMUX6_0", + "BRAM_IMUX46_UTURN_0", + "BRAM_IMUX16_UTURN_1", + "BRAM_CASCOUT_ADDRARDADDRU12", + "BRAM_WW4C0_4", + "BRAM_IMUX23_UTURN_2", + "BRAM_IMUX25_3", + "BRAM_IMUX_ADDRARDADDRU3", + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "BRAM_IMUX0_UTURN_2", + "BRAM_BLOCK_OUTS_L_B2_3", + "BRAM_ADDRARDADDRU1", + "BRAM_FIFO36_WEBWEU2", + "BRAM_IMUX38_UTURN_2", + "BRAM_FIFO36_DIBDIU8", + "BRAM_IMUX5_3", + "BRAM_SW4A3_0", + "BRAM_LH11_0", + "BRAM_IMUX26_4", + "BRAM_MONITOR_N_4", + "BRAM_LOGIC_OUTS_B23_3", + "BRAM_UTURN_ADDRARDADDRL3", + "BRAM_EE4C3_4", + "BRAM_FIFO18_RDCOUNT6", + "BRAM_IMUX37_UTURN_0", + "BRAM_IMUX2_1", + "BRAM_WR1END3_2", + "BRAM_CASCINTOP_ADDRARDADDRU11", + "BRAM_NE4BEG2_0", + "BRAM_FIFO36_WEAU0", + "BRAM_IMUX15_3", + "BRAM_FIFO18_ADDRBWRADDR3", + "BRAM_IMUX31_2", + "BRAM_IMUX10_0", + "BRAM_WW2END1_4", + "BRAM_LOGIC_OUTS_B5_2", + "BRAM_FIFO36_DOADOU1", + "BRAM_NW4A0_1", + "BRAM_FIFO36_DIBDIL1", + "BRAM_NW4END0_3", + "BRAM_FIFO36_ADDRBWRADDRU12", + "BRAM_SE4C0_4", + "BRAM_FIFO36_TSTIN4", + "BRAM_FIFO36_WEAL3", + "BRAM_FIFO36_DIBDIL2", + "BRAM_CASCINTOP_ADDRARDADDRU0", + "BRAM_WL1END2_4", + "BRAM_FIFO36_DIBDIL7", + "BRAM_BYP4_0", + "BRAM_NW4END0_4", + "BRAM_CLK0_3", + "BRAM_BYP1_2", + "BRAM_UTURN_ADDRBWRADDRU6", + "BRAM_EE4A0_4", + "BRAM_SE4BEG2_4", + "BRAM_NE2A2_3", + "BRAM_SW4END0_1", + "BRAM_IMUX24_UTURN_0", + "BRAM_SW2A2_2", + "BRAM_WW4C0_2", + "BRAM_IMUX_ADDRARDADDRU1", + "BRAM_FIFO36_ADDRARDADDRL1", + "BRAM_WW4END2_1", + "BRAM_FIFO36_DIADIL9", + "BRAM_WW4A3_2", + "BRAM_ADDRARDADDRL9", + "BRAM_IMUX27_UTURN_4", + "BRAM_RAMB18_DOADO0", + "BRAM_NW2A1_2", + "BRAM_LH5_2", + "BRAM_IMUX_ADDRARDADDRL7", + "BRAM_CASCOUT_ADDRBWRADDRU3", + "BRAM_SE4BEG1_3", + "BRAM_FIFO36_DIADIL13", + "BRAM_IMUX6_UTURN_3", + "BRAM_EE2A3_0", + "BRAM_FIFO36_ADDRARDADDRL10", + "BRAM_IMUX_ADDRARDADDRU4", + "BRAM_FIFO36_ADDRARDADDRL6", + "BRAM_SE4C2_4", + "BRAM_EE2A3_1", + "BRAM_FIFO36_DOADOU9", + "BRAM_UTURN_ADDRARDADDRL6", + "BRAM_FIFO36_RDCOUNT6", + "BRAM_RAMB18_WRERR", + "BRAM_UTURN_ADDRARDADDRU2", + "BRAM_IMUX35_2", + "BRAM_BYP4_2", + "BRAM_IMUX26_UTURN_4", + "BRAM_FIFO36_DOADOL14", + "BRAM_RAMB18_ADDRBWRADDR2", + "BRAM_RAMB18_WEA2", + "BRAM_FIFO18_ENARDEN", + "BRAM_NW4END3_0", + "BRAM_EE4C3_1", + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "BRAM_FIFO18_RSTREGB", + "BRAM_IMUX40_UTURN_4", + "BRAM_UTURN_ADDRBWRADDRL12", + "BRAM_WW2END1_0", + "BRAM_FIFO18_WRCOUNT11", + "BRAM_FIFO18_WRCOUNT1", + "BRAM_EE4A1_3", + "BRAM_LOGIC_OUTS_B9_0", + "BRAM_SE2A0_3", + "BRAM_LOGIC_OUTS_B9_4", + "BRAM_WR1END2_4", + "BRAM_UTURN_ADDRBWRADDRL6", + "BRAM_FIFO36_TSTWROS3", + "BRAM_IMUX20_1", + "BRAM_LOGIC_OUTS_B22_0", + "BRAM_NW4END0_2", + "BRAM_CASCINTOP_ADDRARDADDRU12", + "BRAM_IMUX47_4", + "BRAM_FIFO36_DOBDOU4", + "BRAM_IMUX26_2", + "BRAM_LH1_4", + "BRAM_NE4C1_0", + "BRAM_UTURN_ADDRARDADDRL10", + "BRAM_IMUX_ADDRBWRADDRL8", + "BRAM_IMUX5_0", + "BRAM_LH9_2", + "BRAM_FIFO18_ADDRARDADDR4", + "BRAM_LOGIC_OUTS_B9_2", + "BRAM_LOGIC_OUTS_B20_1", + "BRAM_RAMB18_RDCOUNT2", + "BRAM_IMUX36_3", + "BRAM_IMUX44_UTURN_1", + "BRAM_FIFO18_DIBDI12", + "BRAM_IMUX34_UTURN_1", + "BRAM_IMUX44_3", + "BRAM_BYP7_2", + "BRAM_RAMB18_DOADO13", + "BRAM_IMUX_ADDRARDADDRL13", + "BRAM_FIFO36_DOBDOU15", + "BRAM_FIFO18_DOBDO15", + "BRAM_FIFO36_DOBDOL10", + "BRAM_RAMB18_DOBDO8", + "BRAM_IMUX_ADDRARDADDRL12", + "BRAM_FIFO36_RDCOUNT4", + "BRAM_SE4C2_1", + "BRAM_CLK0_4", + "BRAM_FIFO36_DOADOU10", + "BRAM_SW4A0_3", + "BRAM_IMUX36_0", + "BRAM_IMUX41_UTURN_4", + "BRAM_NE4BEG3_4", + "BRAM_NW2A0_1", + "BRAM_FIFO36_WRCOUNT8", + "BRAM_LH6_1", + "BRAM_EE4C2_3", + "BRAM_FIFO36_CLKARDCLKL", + "BRAM_IMUX31_UTURN_1", + "BRAM_NW4END2_1", + "BRAM_EE4B2_3", + "BRAM_FIFO36_TSTOUT0", + "BRAM_WW4END2_4", + "BRAM_IMUX44_UTURN_0", + "BRAM_FAN0_2", + "BRAM_IMUX28_UTURN_1", + "BRAM_WW4B3_2", + "BRAM_WW4C3_1", + "BRAM_IMUX41_2", + "BRAM_SE2A3_0", + "BRAM_IMUX15_UTURN_0", + "BRAM_EE4C0_1", + "BRAM_IMUX41_UTURN_2", + "BRAM_FIFO36_DIBDIL9", + "BRAM_IMUX5_UTURN_0", + "BRAM_LOGIC_OUTS_B0_1", + "BRAM_RAMB18_DIADI3", + "BRAM_IMUX_ADDRARDADDRL2", + "BRAM_FIFO36_DIADIU15", + "BRAM_LOGIC_OUTS_B16_3", + "BRAM_WL1END2_2", + "BRAM_IMUX32_4", + "BRAM_IMUX5_2", + "BRAM_NW2A2_0", + "BRAM_UTURN_ADDRBWRADDRL8", + "BRAM_NE4BEG1_2", + "BRAM_FIFO36_DIADIU0", + "BRAM_FIFO36_WEBWEU7", + "BRAM_FIFO36_DOBDOU6", + "BRAM_IMUX31_3", + "BRAM_IMUX4_UTURN_0", + "BRAM_IMUX_ADDRARDADDRU7", + "BRAM_FIFO36_DIPBDIPL0", + "BRAM_IMUX2_3", + "BRAM_IMUX24_0", + "BRAM_EE2BEG1_3", + "BRAM_LH3_1", + "BRAM_FAN5_0", + "BRAM_MONITOR_N_1", + "BRAM_FIFO36_TSTWRCNTOFF", + "BRAM_FIFO36_ADDRBWRADDRL3", + "BRAM_IMUX34_UTURN_4", + "BRAM_IMUX_ADDRARDADDRL11", + "BRAM_WW4A2_2", + "BRAM_LH3_2", + "BRAM_EE2BEG2_1", + "BRAM_ADDRARDADDRL3", + "BRAM_FAN6_2", + "BRAM_FIFO36_DOADOL2", + "BRAM_NW4END3_4", + "BRAM_FIFO36_TSTWROS2", + "BRAM_BYP7_3", + "BRAM_WW4C0_0", + "BRAM_IMUX3_4", + "BRAM_FIFO36_DOPBDOPL1", + "BRAM_IMUX41_UTURN_3", + "BRAM_FIFO36_DIPBDIPL1", + "BRAM_FIFO18_DIBDI5", + "BRAM_FIFO36_DIADIL8", + "BRAM_IMUX21_1", + "BRAM_SW4A3_4", + "BRAM_LH4_2", + "BRAM_CASCINTOP_ADDRARDADDRU8", + "BRAM_IMUX9_UTURN_2", + "BRAM_ER1BEG3_2", + "BRAM_EE4B3_0", + "BRAM_UTURN_ADDRBWRADDRU3", + "BRAM_FIFO36_ADDRARDADDRL3", + "BRAM_NW4A2_0", + "BRAM_SE4BEG1_1", + "BRAM_FIFO36_ADDRARDADDRL5", + "BRAM_IMUX28_1", + "BRAM_WW4A0_1", + "BRAM_WW2END0_4", + "BRAM_LH1_0", + "BRAM_CASCINBOT_ADDRARDADDRU7", + "BRAM_FIFO36_DOADOU3", + "BRAM_FIFO36_DOADOU13", + "BRAM_FIFO36_ADDRARDADDRL7", + "BRAM_EE2A1_3", + "BRAM_IMUX18_UTURN_3", + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "BRAM_FIFO36_WEAU3", + "BRAM_FIFO36_ADDRBWRADDRU6", + "BRAM_FIFO18_DIADI0", + "BRAM_UTURN_ADDRARDADDRL7", + "BRAM_FAN1_4", + "BRAM_FIFO18_DOADO4", + "BRAM_FIFO36_TSTRDOS12", + "BRAM_IMUX23_2", + "BRAM_ER1BEG3_3", + "BRAM_IMUX29_1", + "BRAM_FIFO36_ADDRBWRADDRL8", + "BRAM_RAMB18_ADDRBWRADDR6", + "BRAM_NW4END1_3", + "BRAM_IMUX7_UTURN_4", + "BRAM_SW4END2_0", + "BRAM_WW4END1_4", + "BRAM_RAMB18_ADDRBWRADDR13", + "BRAM_IMUX12_3", + "BRAM_BYP0_2", + "BRAM_SW2A0_3", + "BRAM_FIFO18_DOBDO6", + "BRAM_UTURN_ADDRBWRADDRL13", + "BRAM_IMUX6_2", + "BRAM_WR1END2_2", + "BRAM_EE2BEG1_1", + "BRAM_WW2END2_1", + "BRAM_IMUX21_UTURN_2", + "BRAM_IMUX36_4", + "BRAM_NW4END2_3", + "BRAM_CTRL1_1", + "BRAM_IMUX8_2", + "BRAM_IMUX_ADDRBWRADDRU3", + "BRAM_PMVBRAM_SELECT3", + "BRAM_LOGIC_OUTS_B7_3", + "BRAM_FIFO36_DIADIL1", + "BRAM_IMUX27_4", + "BRAM_IMUX9_2", + "BRAM_LOGIC_OUTS_B19_1", + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "BRAM_WW4END0_1", + "BRAM_IMUX39_UTURN_3", + "BRAM_RAMB18_DIADI4", + "BRAM_RAMB18_DOADO6", + "BRAM_ADDRARDADDRL0", + "BRAM_IMUX9_UTURN_1", + "BRAM_IMUX28_0", + "BRAM_LH6_0", + "BRAM_FIFO36_DIADIL5", + "BRAM_LOGIC_OUTS_B4_0", + "BRAM_FIFO18_ADDRBWRADDR1", + "BRAM_FIFO36_DOBDOL14", + "BRAM_RAMB18_WRCOUNT5", + "BRAM_IMUX_ADDRARDADDRU9", + "BRAM_RAMB18_ADDRARDADDR10", + "BRAM_IMUX33_0", + "BRAM_SW2A3_2", + "BRAM_IMUX8_UTURN_4", + "BRAM_LH4_0", + "BRAM_LOGIC_OUTS_B5_1", + "BRAM_CASCOUT_ADDRBWRADDRU1", + "BRAM_IMUX40_3", + "BRAM_IMUX8_UTURN_3", + "BRAM_FIFO36_ADDRBWRADDRL15", + "BRAM_FIFO18_DOADO0", + "BRAM_FIFO36_WEAL1", + "BRAM_IMUX13_UTURN_4", + "BRAM_EE4BEG0_3", + "BRAM_IMUX3_UTURN_1", + "BRAM_IMUX4_1", + "BRAM_FIFO18_WRCOUNT7", + "BRAM_IMUX16_2", + "BRAM_IMUX47_UTURN_2", + "BRAM_FIFO36_FULL", + "BRAM_IMUX21_UTURN_4", + "BRAM_NE4C1_3", + "BRAM_RAMB18_DOBDO13", + "BRAM_IMUX32_UTURN_4", + "BRAM_FAN5_1", + "BRAM_FIFO36_DOADOU7", + "BRAM_FIFO18_DIBDI15", + "BRAM_WW2A1_3", + "BRAM_IMUX14_4", + "BRAM_BYP5_1", + "BRAM_RAMB18_DOPADOP0", + "BRAM_FIFO36_ADDRARDADDRL8", + "BRAM_IMUX24_UTURN_1", + "BRAM_FIFO36_ADDRARDADDRU13", + "BRAM_CASCOUT_ADDRBWRADDRU4", + "BRAM_EE4A1_1", + "BRAM_FAN4_1", + "BRAM_FIFO36_ADDRARDADDRU12", + "BRAM_LOGIC_OUTS_B17_3", + "BRAM_FIFO18_DOPBDOP0", + "BRAM_IMUX_ADDRBWRADDRU7", + "BRAM_LOGIC_OUTS_B11_1", + "BRAM_RAMB18_WEBWE3", + "BRAM_FIFO36_DOADOL15", + "BRAM_IMUX39_4", + "BRAM_IMUX4_4", + "BRAM_FIFO36_WEBWEL5", + "BRAM_IMUX11_2", + "BRAM_FIFO18_ADDRBWRADDR2", + "BRAM_FIFO18_REGCLKB", + "BRAM_UTURN_ADDRBWRADDRU7", + "BRAM_LOGIC_OUTS_B4_4", + "BRAM_NW4A3_3", + "BRAM_IMUX43_UTURN_0", + "BRAM_IMUX1_0", + "BRAM_WW4END0_0", + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "BRAM_LH7_1", + "BRAM_CLK1_1", + "BRAM_FIFO18_DOBDO7", + "BRAM_IMUX15_4", + "BRAM_EE4BEG3_3", + "BRAM_RAMB18_ADDRBWRADDR10", + "BRAM_FIFO36_RDCOUNT9", + "BRAM_FIFO36_ECCPARITY5", + "BRAM_SW4END3_2", + "BRAM_CASCOUT_ADDRARDADDRU3", + "BRAM_FIFO36_DIADIL11", + "BRAM_UTURN_ADDRARDADDRL8", + "BRAM_IMUX42_UTURN_4", + "BRAM_IMUX22_4", + "BRAM_EE4A0_2", + "BRAM_EE4C3_0", + "BRAM_UTURN_ADDRBWRADDRU2", + "BRAM_LH9_1", + "BRAM_FIFO36_DIPBDIPU1", + "BRAM_NE4C3_0", + "BRAM_IMUX43_3", + "BRAM_WW4C1_0", + "BRAM_SE4C3_0", + "BRAM_WW2END0_3", + "BRAM_PMVBRAM_ODIV4", + "BRAM_SE2A1_1", + "BRAM_IMUX40_1", + "BRAM_RAMB18_ADDRBWRADDR11", + "BRAM_EE4B2_0", + "BRAM_IMUX9_1", + "BRAM_FAN3_1", + "BRAM_MONITOR_P_2", + "BRAM_IMUX_ADDRARDADDRL0", + "BRAM_ADDRBWRADDRL0", + "BRAM_IMUX_ADDRARDADDRL14", + "BRAM_RAMB18_DOBDO9", + "BRAM_FIFO18_DIBDI11", + "BRAM_FIFO18_WEBWE6", + "BRAM_FIFO36_ADDRBWRADDRU13", + "BRAM_IMUX6_UTURN_0", + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "BRAM_IMUX29_2", + "BRAM_RAMB18_DIADI14", + "BRAM_IMUX2_UTURN_0", + "BRAM_SE4C0_0", + "BRAM_LOGIC_OUTS_B18_0", + "BRAM_RAMB18_ADDRBWRADDR3", + "BRAM_CASCINBOT_ADDRARDADDRU12", + "BRAM_IMUX8_UTURN_1", + "BRAM_LOGIC_OUTS_B1_3", + "BRAM_IMUX45_UTURN_2", + "BRAM_RAMB18_DIADI9", + "BRAM_WW2A0_4", + "BRAM_IMUX5_UTURN_2", + "BRAM_EE4B2_1", + "BRAM_CASCINTOP_ADDRARDADDRU9", + "BRAM_LOGIC_OUTS_B21_4", + "BRAM_NW2A3_2", + "BRAM_NW2A1_4", + "BRAM_IMUX33_UTURN_0", + "BRAM_LOGIC_OUTS_B15_0", + "BRAM_IMUX46_UTURN_2", + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "BRAM_RAMB18_RSTREGB", + "BRAM_EE4A1_2", + "BRAM_NE4C0_0", + "BRAM_IMUX7_3", + "BRAM_IMUX40_UTURN_3", + "BRAM_LOGIC_OUTS_B23_1", + "BRAM_IMUX0_UTURN_4", + "BRAM_NE4C2_1", + "BRAM_IMUX13_UTURN_2", + "BRAM_ADDRBWRADDRL11", + "BRAM_RAMB18_DOADO14", + "BRAM_LOGIC_OUTS_B14_2", + "BRAM_IMUX3_3", + "BRAM_SW4A3_3", + "BRAM_LOGIC_OUTS_B14_0", + "BRAM_FIFO36_DOBDOL5", + "BRAM_FIFO36_DOPADOPU0", + "BRAM_WW4B1_4", + "BRAM_EE4C1_1", + "BRAM_ADDRARDADDRU4", + "BRAM_EL1BEG2_4", + "BRAM_FIFO36_ECCPARITY4", + "BRAM_EE2BEG0_3", + "BRAM_FIFO18_DIADI15", + "BRAM_WW4A1_3", + "BRAM_IMUX47_UTURN_3", + "BRAM_IMUX_ADDRBWRADDRU9", + "BRAM_IMUX_ADDRBWRADDRU1", + "BRAM_FIFO36_ADDRBWRADDRL0", + "BRAM_IMUX17_4", + "BRAM_UTURN_ADDRARDADDRU10", + "BRAM_LH10_4", + "BRAM_FIFO18_WRCOUNT4", + "BRAM_NW4A2_3", + "BRAM_ADDRBWRADDRL10", + "BRAM_LOGIC_OUTS_B19_2", + "BRAM_NE4C3_2", + "BRAM_IMUX9_4", + "BRAM_FIFO36_DOBDOL7", + "BRAM_IMUX33_3", + "BRAM_IMUX14_3", + "BRAM_IMUX20_0", + "BRAM_WW4B1_0", + "BRAM_WW4END3_2", + "BRAM_FIFO36_TSTWROS9", + "BRAM_IMUX32_0", + "BRAM_EE2BEG1_0", + "BRAM_IMUX32_UTURN_3", + "BRAM_IMUX_ADDRBWRADDRL13", + "BRAM_FIFO36_ADDRBWRADDRL12", + "BRAM_LH2_2", + "BRAM_LOGIC_OUTS_B23_2", + "BRAM_WW4END2_2", + "BRAM_LOGIC_OUTS_B20_0", + "BRAM_NE4BEG2_4", + "BRAM_WW4A0_4", + "BRAM_SW2A3_4", + "BRAM_IMUX18_UTURN_1", + "BRAM_FIFO18_DOBDO5", + "BRAM_SE4BEG0_1", + "BRAM_WL1END1_3", + "BRAM_RAMB18_DIADI11", + "BRAM_BYP6_3", + "BRAM_FIFO36_DIBDIU9", + "BRAM_BYP4_4", + "BRAM_IMUX15_UTURN_3", + "BRAM_LH9_3", + "BRAM_IMUX43_0", + "BRAM_FIFO36_REGCLKBU", + "BRAM_FIFO18_RDCOUNT1", + "BRAM_IMUX37_4", + "BRAM_FIFO36_TSTCNT5", + "BRAM_IMUX42_2", + "BRAM_IMUX22_UTURN_1", + "BRAM_WW4C2_3", + "BRAM_WR1END1_1", + "BRAM_EE4A0_1", + "BRAM_IMUX_ADDRARDADDRU12", + "BRAM_FAN2_2", + "BRAM_EE4C2_4", + "BRAM_IMUX19_1", + "BRAM_SW4A0_0", + "BRAM_IMUX7_UTURN_3", + "BRAM_IMUX42_4", + "BRAM_NE2A2_2", + "BRAM_FIFO18_DIADI9", + "BRAM_LOGIC_OUTS_B11_2", + "BRAM_IMUX24_1", + "BRAM_BLOCK_OUTS_L_B3_4", + "BRAM_IMUX30_UTURN_1", + "BRAM_RAMB18_WRCOUNT0", + "BRAM_SE4C1_3", + "BRAM_CASCOUT_ADDRARDADDRU10", + "BRAM_RAMB18_RDCOUNT7", + "BRAM_FIFO36_CASCADEOUTB", + "BRAM_SW4A1_3", + "BRAM_FIFO36_ADDRARDADDRU10", + "BRAM_FAN5_2", + "BRAM_SW2A2_4", + "BRAM_UTURN_ADDRARDADDRL0", + "BRAM_UTURN_ADDRBWRADDRL7", + "BRAM_IMUX37_0", + "BRAM_IMUX26_UTURN_3", + "BRAM_IMUX16_0", + "BRAM_EE4C0_3", + "BRAM_FIFO36_TSTWROS11", + "BRAM_FIFO36_WRCOUNT5", + "BRAM_IMUX36_2", + "BRAM_FIFO36_DOADOL1", + "BRAM_NE2A3_3", + "BRAM_UTURN_ADDRBWRADDRL1", + "BRAM_CASCINTOP_ADDRARDADDRU13", + "BRAM_CASCINBOT_ADDRARDADDRU13", + "BRAM_FIFO18_DIBDI4", + "BRAM_IMUX13_1", + "BRAM_LOGIC_OUTS_B21_3", + "BRAM_FIFO36_RSTREGARSTREGU", + "BRAM_EE4A2_4", + "BRAM_FIFO36_DIADIU3", + "BRAM_RAMB18_RDCOUNT9", + "BRAM_SW4A2_3", + "BRAM_UTURN_ADDRARDADDRU8", + "BRAM_ADDRARDADDRL2", + "BRAM_FIFO36_ECCPARITY1", + "BRAM_IMUX41_0", + "BRAM_BYP1_1", + "BRAM_FIFO18_RDCOUNT0", + "BRAM_IMUX37_2", + "BRAM_FIFO36_DIBDIU5", + "BRAM_FIFO18_ADDRBWRADDR6", + "BRAM_RAMB18_DOADO15", + "BRAM_FIFO18_ADDRBWRADDR13", + "BRAM_WR1END2_3", + "BRAM_FIFO18_RDCOUNT7", + "BRAM_IMUX13_UTURN_3", + "BRAM_WR1END3_1", + "BRAM_UTURN_ADDRARDADDRL12", + "BRAM_RAMB18_WEA1", + "BRAM_FIFO36_ADDRBWRADDRU3", + "BRAM_WW2A0_0", + "BRAM_IMUX0_3", + "BRAM_RAMB18_DIADI15", + "BRAM_ER1BEG2_4", + "BRAM_FIFO36_DOADOU15", + "BRAM_LH2_1", + "BRAM_WL1END0_3", + "BRAM_IMUX47_2", + "BRAM_SE2A2_0", + "BRAM_LH7_4", + "BRAM_EE4C1_3", + "BRAM_EE4A3_0", + "BRAM_EE4A2_3", + "BRAM_NW4END2_0", + "BRAM_FIFO36_DIADIU8", + "BRAM_WW4C3_3", + "BRAM_WR1END2_0", + "BRAM_NE2A1_3", + "BRAM_IMUX38_1", + "BRAM_FIFO18_RSTREGARSTREG", + "BRAM_CASCINTOP_ADDRARDADDRU5", + "BRAM_RAMB18_DIBDI8", + "BRAM_FIFO36_RSTREGBL", + "BRAM_IMUX32_1", + "BRAM_IMUX28_4", + "BRAM_IMUX_ADDRARDADDRU8", + "BRAM_IMUX19_3", + "BRAM_LOGIC_OUTS_B11_4", + "BRAM_RAMB18_DOBDO0", + "BRAM_CASCOUT_ADDRARDADDRU11", + "BRAM_SW4A2_4", + "BRAM_IMUX_ADDRBWRADDRU6", + "BRAM_RAMB18_DOPBDOP1", + "BRAM_EE2BEG1_2", + "BRAM_EE4BEG3_4", + "BRAM_FIFO36_TSTRDOS6", + "BRAM_EL1BEG3_2", + "BRAM_LOGIC_OUTS_B12_2", + "BRAM_NW2A0_3", + "BRAM_SW2A0_1", + "BRAM_IMUX32_UTURN_0", + "BRAM_FIFO36_RDCOUNT0", + "BRAM_WR1END3_3", + "BRAM_SW4END2_1", + "BRAM_BYP4_1", + "BRAM_IMUX20_UTURN_1", + "BRAM_BYP6_0", + "BRAM_IMUX45_UTURN_4", + "BRAM_FIFO36_ADDRBWRADDRU5", + "BRAM_CASCOUT_ADDRBWRADDRU6", + "BRAM_SW2A1_0", + "BRAM_IMUX42_UTURN_1", + "BRAM_SE4BEG0_4", + "BRAM_LH10_0", + "BRAM_ADDRBWRADDRL1", + "BRAM_FIFO36_DIADIU10", + "BRAM_FIFO36_REGCEBU", + "BRAM_LOGIC_OUTS_B1_4", + "BRAM_ER1BEG1_1", + "BRAM_FIFO36_DOBDOU8", + "BRAM_FIFO18_ADDRARDADDR11", + "BRAM_IMUX11_0", + "BRAM_WW4B3_4", + "BRAM_IMUX38_0", + "BRAM_EE4BEG2_0", + "BRAM_CASCOUT_ADDRARDADDRU2", + "BRAM_RAMB18_DIPBDIP0", + "BRAM_FIFO36_TSTOUT4", + "BRAM_IMUX_ADDRARDADDRL6", + "BRAM_FIFO36_DIADIL4", + "BRAM_FIFO36_DIBDIL8", + "BRAM_EE2A2_1", + "BRAM_FIFO18_DIPBDIP0", + "BRAM_FIFO18_CLKBWRCLK", + "BRAM_IMUX33_UTURN_4", + "BRAM_IMUX11_4", + "BRAM_RAMB18_ADDRBTIEHIGH0", + "BRAM_IMUX9_UTURN_0", + "BRAM_CASCOUT_ADDRARDADDRU1", + "BRAM_BLOCK_OUTS_L_B3_1", + "BRAM_FIFO18_RDERR", + "BRAM_ADDRBWRADDRU9", + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "BRAM_SW2A1_4", + "BRAM_FIFO18_ADDRBWRADDR10", + "BRAM_FIFO36_DIADIU9", + "BRAM_FIFO18_ADDRARDADDR5", + "BRAM_IMUX11_UTURN_4", + "BRAM_FIFO18_ADDRARDADDR12", + "BRAM_IMUX12_2", + "BRAM_FAN4_0", + "BRAM_FIFO36_DIADIU12", + "BRAM_RAMB18_WEBWE1", + "BRAM_FIFO36_ADDRARDADDRL15", + "BRAM_IMUX_ADDRBWRADDRL7", + "BRAM_FAN2_1", + "BRAM_BLOCK_OUTS_L_B0_2", + "BRAM_RAMB18_RDCOUNT11", + "BRAM_EE2A0_1", + "BRAM_IMUX0_UTURN_0", + "BRAM_IMUX45_3", + "BRAM_FIFO18_DOADO13", + "BRAM_IMUX7_UTURN_1", + "BRAM_FIFO36_ADDRARDADDRU1", + "BRAM_RAMB18_WRCOUNT1", + "BRAM_ADDRARDADDRL10", + "BRAM_IMUX45_UTURN_0", + "BRAM_FIFO36_ECCPARITY0", + "BRAM_IMUX38_UTURN_1", + "BRAM_FIFO36_TSTRDOS1", + "BRAM_FIFO36_TSTCNT6", + "BRAM_FIFO36_RSTREGARSTREGL", + "BRAM_FIFO18_DIADI8", + "BRAM_IMUX_ADDRBWRADDRL5", + "BRAM_WL1END1_4", + "BRAM_ER1BEG1_4", + "BRAM_WR1END3_0", + "BRAM_FIFO18_DOADO5", + "BRAM_FIFO36_CLKBWRCLKL", + "BRAM_FIFO36_TSTWROS12", + "BRAM_IMUX39_UTURN_0", + "BRAM_IMUX22_UTURN_3", + "BRAM_FIFO36_DIADIL15", + "BRAM_IMUX19_UTURN_1", + "BRAM_FAN6_3", + "BRAM_SE2A3_3", + "BRAM_IMUX4_UTURN_2", + "BRAM_ADDRBWRADDRU6", + "BRAM_FIFO36_REGCEBL", + "BRAM_LOGIC_OUTS_B21_2", + "BRAM_IMUX25_UTURN_0", + "BRAM_FIFO36_DIADIU11", + "BRAM_LOGIC_OUTS_B16_4", + "BRAM_FIFO36_TSTRDOS2", + "BRAM_RAMB18_DOADO5", + "BRAM_EE2A2_2", + "BRAM_IMUX41_3", + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "BRAM_EL1BEG0_1", + "BRAM_ER1BEG1_2", + "BRAM_LH8_3", + "BRAM_EE2A3_4", + "BRAM_FIFO36_ADDRARDADDRL4", + "BRAM_NW4A3_4", + "BRAM_FIFO36_DOADOL6", + "BRAM_NW4A1_2", + "BRAM_IMUX0_UTURN_1", + "BRAM_IMUX12_UTURN_4", + "BRAM_LOGIC_OUTS_B14_1", + "BRAM_WW4C0_1", + "BRAM_UTURN_ADDRBWRADDRU1", + "BRAM_FIFO36_RSTREGBU", + "BRAM_IMUX_ADDRBWRADDRL2", + "BRAM_CASCOUT_ADDRBWRADDRU5", + "BRAM_WW2A0_1", + "BRAM_FIFO36_ADDRBWRADDRL4", + "BRAM_LOGIC_OUTS_B11_0", + "BRAM_ADDRARDADDRL12", + "BRAM_IMUX18_UTURN_4", + "BRAM_WW2END2_3", + "BRAM_IMUX38_3", + "BRAM_FIFO36_TSTRDOS0", + "BRAM_FIFO36_CASCADEOUTB_1", + "BRAM_NE2A3_2", + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "BRAM_IMUX10_1", + "BRAM_WL1END3_1", + "BRAM_LH4_3", + "BRAM_IMUX10_UTURN_0", + "BRAM_IMUX_ADDRBWRADDRL11", + "BRAM_SW2A2_1", + "BRAM_SE4BEG3_2", + "BRAM_FIFO36_DIADIU13", + "BRAM_CASCINBOT_ADDRARDADDRU10", + "BRAM_IMUX11_1", + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "BRAM_RAMB18_ADDRBWRADDR8", + "BRAM_NW4END0_1", + "BRAM_EE2A3_3", + "BRAM_FIFO36_ADDRBWRADDRL13", + "BRAM_RAMB18_ADDRATIEHIGH0", + "BRAM_ADDRARDADDRL6", + "BRAM_NW2A2_4", + "BRAM_FIFO36_ADDRBWRADDRU7", + "BRAM_FIFO18_DOADO11", + "BRAM_FIFO18_RDCOUNT3", + "BRAM_IMUX27_2", + "BRAM_FIFO36_DOBDOL3", + "BRAM_IMUX42_3", + "BRAM_EE4C1_0", + "BRAM_IMUX40_0", + "BRAM_LOGIC_OUTS_B8_1", + "BRAM_SE4C3_4", + "BRAM_FIFO36_DIADIL6", + "BRAM_CASCINTOP_ADDRARDADDRU10", + "BRAM_ADDRBWRADDRL3", + "BRAM_ADDRBWRADDRU3", + "BRAM_FIFO36_ADDRBWRADDRU0", + "BRAM_IMUX17_UTURN_2", + "BRAM_RAMB18_RDCOUNT6", + "BRAM_UTURN_ADDRBWRADDRU5", + "BRAM_IMUX37_3", + "BRAM_ADDRARDADDRU5", + "BRAM_WW4C3_4", + "BRAM_FIFO36_TSTCNT3", + "BRAM_RAMB18_ADDRARDADDR4", + "BRAM_WW2A1_4", + "BRAM_SW4A0_4", + "BRAM_IMUX2_UTURN_3", + "BRAM_RAMB18_DOADO9", + "BRAM_ADDRARDADDRU0", + "BRAM_IMUX_ADDRBWRADDRU5", + "BRAM_EE2A3_2", + "BRAM_IMUX43_1", + "BRAM_IMUX33_4", + "BRAM_FIFO36_ADDRARDADDRL12", + "BRAM_IMUX19_UTURN_3", + "BRAM_IMUX1_UTURN_4", + "BRAM_FIFO18_ADDRARDADDR10", + "BRAM_FIFO18_WEBWE4", + "BRAM_SW4A1_2", + "BRAM_NE4C1_1", + "BRAM_FIFO18_ADDRBWRADDR4", + "BRAM_NW2A3_4", + "BRAM_LOGIC_OUTS_B22_2", + "BRAM_IMUX38_4", + "BRAM_EE2A2_3", + "BRAM_FIFO36_ADDRARDADDRU7", + "BRAM_IMUX26_UTURN_1", + "BRAM_FIFO36_EMPTY", + "BRAM_FIFO18_RDCOUNT9", + "BRAM_LH4_4", + "BRAM_RAMB18_EMPTY", + "BRAM_RAMB18_DIBDI11", + "BRAM_SE4BEG2_3", + "BRAM_RAMB18_DOBDO7", + "BRAM_BYP3_4", + "BRAM_EE4B0_2", + "BRAM_FIFO18_DOBDO2", + "BRAM_FIFO18_DOADO3", + "BRAM_IMUX39_0", + "BRAM_FIFO36_ENBWRENL", + "BRAM_SE2A2_3", + "BRAM_WW4END2_3", + "BRAM_FIFO36_DIPADIPU0", + "BRAM_NW2A0_0", + "BRAM_UTURN_ADDRARDADDRL9", + "BRAM_LOGIC_OUTS_B12_4", + "BRAM_BYP0_1", + "BRAM_WW4END1_0", + "BRAM_FIFO18_ADDRBWRADDR9", + "BRAM_RAMB18_ADDRARDADDR13", + "BRAM_CLK1_4", + "BRAM_ADDRARDADDRU7", + "BRAM_SW4END2_3", + "BRAM_LOGIC_OUTS_B0_2", + "BRAM_SE4BEG2_2", + "BRAM_IMUX43_UTURN_2", + "BRAM_WW4A3_0", + "BRAM_FIFO36_DIADIL3", + "BRAM_IMUX18_0", + "BRAM_FIFO36_DOADOU14", + "BRAM_FIFO18_DIBDI0", + "BRAM_NE2A0_4", + "BRAM_EL1BEG0_4", + "BRAM_RAMB18_DOBDO11", + "BRAM_FIFO36_WRCOUNT12", + "BRAM_SW4END1_0", + "BRAM_ADDRARDADDRL14", + "BRAM_FIFO18_DOPBDOP1", + "BRAM_LOGIC_OUTS_B6_2", + "BRAM_IMUX39_UTURN_1", + "BRAM_FIFO36_ADDRARDADDRL13", + "BRAM_IMUX8_0", + "BRAM_WW4C2_4", + "BRAM_CASCINTOP_ADDRARDADDRU3", + "BRAM_SE2A0_1", + "BRAM_WW2A3_0", + "BRAM_IMUX22_UTURN_2", + "BRAM_IMUX24_2", + "BRAM_RAMB18_DOPADOP1", + "BRAM_WW4C3_0", + "BRAM_WW2A2_0", + "BRAM_EE4A3_1", + "BRAM_FIFO18_REGCLKARDRCLK", + "BRAM_LOGIC_OUTS_B5_3", + "BRAM_UTURN_ADDRARDADDRL5", + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "BRAM_IMUX4_3", + "BRAM_IMUX_ADDRBWRADDRL10", + "BRAM_IMUX31_UTURN_4", + "BRAM_LOGIC_OUTS_B12_1", + "BRAM_LOGIC_OUTS_B8_4", + "BRAM_FIFO36_DOPADOPL1", + "BRAM_EE4C2_1", + "BRAM_IMUX37_UTURN_4", + "BRAM_IMUX25_UTURN_1", + "BRAM_WW4END1_1", + "BRAM_LOGIC_OUTS_B15_4", + "BRAM_FIFO18_RDCOUNT5", + "BRAM_LOGIC_OUTS_B6_1", + "BRAM_SE4C1_2", + "BRAM_IMUX5_UTURN_1", + "BRAM_FIFO36_DIADIU4", + "BRAM_MONITOR_N_2", + "BRAM_NE2A1_1", + "BRAM_CTRL1_3", + "BRAM_IMUX35_UTURN_0", + "BRAM_WW4C2_1", + "BRAM_IMUX26_0", + "BRAM_ADDRBWRADDRU13", + "BRAM_NW4A1_0", + "BRAM_IMUX46_3", + "BRAM_EE4BEG1_3", + "BRAM_UTURN_ADDRARDADDRL15", + "BRAM_IMUX1_3", + "BRAM_RAMB18_REGCLKARDRCLK", + "BRAM_UTURN_ADDRARDADDRL11", + "BRAM_RAMB18_ADDRARDADDR8", + "BRAM_WW4A0_2", + "BRAM_IMUX35_1", + "BRAM_LOGIC_OUTS_B19_0", + "BRAM_FIFO36_WRCOUNT7", + "BRAM_IMUX13_4", + "BRAM_ADDRBWRADDRL7", + "BRAM_IMUX11_UTURN_2", + "BRAM_EL1BEG1_0", + "BRAM_NE4BEG3_3", + "BRAM_CLK0_2", + "BRAM_FIFO36_WRCOUNT10", + "BRAM_FIFO36_ADDRARDADDRU14", + "BRAM_LOGIC_OUTS_B12_3", + "BRAM_IMUX1_4", + "BRAM_NE4BEG0_0", + "BRAM_EE4B0_0", + "BRAM_FIFO36_RSTRAMBL", + "BRAM_UTURN_ADDRBWRADDRL11", + "BRAM_RAMB18_DIBDI10", + "BRAM_UTURN_ADDRBWRADDRU14", + "BRAM_WW2END1_2", + "BRAM_IMUX27_UTURN_3", + "BRAM_WW2A3_1", + "BRAM_IMUX41_UTURN_0", + "BRAM_FIFO36_DIBDIL3", + "BRAM_NE4C3_3", + "BRAM_IMUX3_UTURN_4", + "BRAM_IMUX24_UTURN_4", + "BRAM_IMUX39_2", + "BRAM_IMUX13_3", + "BRAM_IMUX_ADDRBWRADDRU10", + "BRAM_IMUX44_UTURN_3", + "BRAM_FIFO18_ADDRBWRADDR5", + "BRAM_IMUX1_UTURN_0", + "BRAM_EE4A3_2", + "BRAM_NE4C0_3", + "BRAM_NW4A2_1", + "BRAM_SE4BEG1_2", + "BRAM_NE4BEG0_1", + "BRAM_LH6_4", + "BRAM_IMUX42_UTURN_2", + "BRAM_SE4BEG2_0", + "BRAM_RAMB18_DIBDI1", + "BRAM_WR1END1_2", + "BRAM_FAN3_4", + "BRAM_FIFO36_DIADIL2", + "BRAM_UTURN_ADDRBWRADDRL5", + "BRAM_NW4END1_1", + "BRAM_CASCOUT_ADDRBWRADDRU7", + "BRAM_FIFO36_WRCOUNT9", + "BRAM_FIFO36_DOADOL10", + "BRAM_IMUX29_UTURN_1", + "BRAM_IMUX18_1", + "BRAM_RAMB18_WEBWE4", + "BRAM_LOGIC_OUTS_B0_4", + "BRAM_SW4END0_4", + "BRAM_FIFO36_DOADOU12", + "BRAM_IMUX40_UTURN_1", + "BRAM_FIFO18_ADDRBWRADDR11", + "BRAM_IMUX7_UTURN_0", + "BRAM_CASCOUT_ADDRARDADDRU4", + "BRAM_LOGIC_OUTS_B11_3", + "BRAM_FIFO36_DOBDOU13", + "BRAM_SE4BEG3_1", + "BRAM_LOGIC_OUTS_B15_2", + "BRAM_IMUX45_0", + "BRAM_CASCOUT_ADDRBWRADDRU14", + "BRAM_FAN0_4", + "BRAM_EE4B3_3", + "BRAM_FIFO18_ENBWREN", + "BRAM_IMUX14_UTURN_1", + "BRAM_UTURN_ADDRBWRADDRU13", + "BRAM_IMUX44_UTURN_2", + "BRAM_FIFO36_DIBDIL6", + "BRAM_SE2A3_4", + "BRAM_IMUX_ADDRBWRADDRU14", + "BRAM_IMUX8_UTURN_2", + "BRAM_EL1BEG1_2", + "BRAM_WL1END2_0", + "BRAM_FIFO36_DIBDIU10", + "BRAM_FIFO36_TSTWROS6", + "BRAM_FIFO36_WRCOUNT4", + "BRAM_IMUX6_UTURN_1", + "BRAM_FIFO18_DOBDO9", + "BRAM_SW2A0_0", + "BRAM_FIFO18_RDCOUNT4", + "BRAM_IMUX0_2", + "BRAM_IMUX30_UTURN_0", + "BRAM_RAMB18_DIPADIP0", + "BRAM_FIFO36_DOADOU8", + "BRAM_UTURN_ADDRARDADDRL13", + "BRAM_IMUX33_1", + "BRAM_NW2A0_4", + "BRAM_IMUX21_UTURN_1", + "BRAM_IMUX30_2", + "BRAM_FIFO36_TSTWROS1", + "BRAM_EE4BEG2_2", + "BRAM_IMUX28_UTURN_3", + "BRAM_FIFO36_RDCOUNT12", + "BRAM_EE4C2_0", + "BRAM_FIFO36_ADDRARDADDRU4", + "BRAM_FIFO36_DOADOL9", + "BRAM_BYP2_2", + "BRAM_FIFO18_ADDRBWRADDR8", + "BRAM_RAMB18_DIBDI14", + "BRAM_EE4B0_3", + "BRAM_FIFO36_WEBWEU0", + "BRAM_PMVBRAM_ODIV2_1", + "BRAM_RAMB18_WEBWE2", + "BRAM_FIFO36_RDCOUNT11", + "BRAM_FIFO18_DIBDI14", + "BRAM_IMUX10_UTURN_2", + "BRAM_LOGIC_OUTS_B17_4", + "BRAM_FIFO36_DIBDIL13", + "BRAM_RAMB18_DIBDI0", + "BRAM_LOGIC_OUTS_B19_4", + "BRAM_UTURN_ADDRARDADDRU13", + "BRAM_FIFO36_RDCOUNT7", + "BRAM_IMUX30_3", + "BRAM_FAN5_3", + "BRAM_WL1END2_3", + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "BRAM_FIFO18_DIADI4", + "BRAM_FIFO36_CASCADEINB", + "BRAM_IMUX_ADDRARDADDRU10", + "BRAM_NW4A0_4", + "BRAM_FIFO36_RSTRAMARSTRAMLRST", + "BRAM_WR1END2_1", + "BRAM_IMUX21_2", + "BRAM_IMUX28_2", + "BRAM_IMUX_ADDRARDADDRU6", + "BRAM_SW4END0_0", + "BRAM_NE2A0_1", + "BRAM_LOGIC_OUTS_B7_2", + "BRAM_CASCINBOT_ADDRARDADDRU11", + "BRAM_IMUX33_2", + "BRAM_IMUX3_2", + "BRAM_EE4A3_3", + "BRAM_NW4A3_0", + "BRAM_FIFO36_WEAU1", + "BRAM_NW4END2_4", + "BRAM_IMUX12_0", + "BRAM_EE2A1_1", + "BRAM_FIFO36_DIBDIU1", + "BRAM_WW4A2_0", + "BRAM_RAMB18_DIBDI12", + "BRAM_FIFO36_WEBWEU5", + "BRAM_FIFO36_DOBDOL0", + "BRAM_IMUX18_UTURN_0", + "BRAM_FIFO36_DIBDIU4", + "BRAM_FAN3_2", + "BRAM_FIFO36_ECCPARITY6", + "BRAM_NW4END1_0", + "BRAM_IMUX20_UTURN_4", + "BRAM_LOGIC_OUTS_B21_0", + "BRAM_IMUX44_0", + "BRAM_RAMB18_ADDRATIEHIGH1", + "BRAM_IMUX31_UTURN_3", + "BRAM_RAMB18_WRCOUNT4", + "BRAM_FIFO36_DIBDIU3", + "BRAM_FIFO18_DOBDO8", + "BRAM_RAMB18_ADDRARDADDR11", + "BRAM_LOGIC_OUTS_B20_2", + "BRAM_IMUX_ADDRARDADDRU0", + "BRAM_IMUX39_1", + "BRAM_FIFO18_ADDRARDADDR1", + "BRAM_RAMB18_DIBDI4", + "BRAM_NE2A2_4", + "BRAM_ADDRARDADDRU8", + "BRAM_FIFO18_ADDRBTIEHIGH0", + "BRAM_IMUX_ADDRBWRADDRL9", + "BRAM_WR1END1_3", + "BRAM_IMUX40_4", + "BRAM_EE4C2_2", + "BRAM_RAMB18_RDCOUNT4", + "BRAM_BYP6_1", + "BRAM_IMUX1_UTURN_3", + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "BRAM_WW2END3_3", + "BRAM_IMUX34_UTURN_3", + "BRAM_CASCINTOP_ADDRARDADDRU2", + "BRAM_ER1BEG0_4", + "BRAM_FIFO36_ADDRARDADDRU3", + "BRAM_LOGIC_OUTS_B7_0", + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "BRAM_EE4BEG2_4", + "BRAM_FIFO36_DOBDOU11", + "BRAM_BYP3_2", + "BRAM_FIFO36_DOPADOPU1", + "BRAM_IMUX18_UTURN_2", + "BRAM_IMUX_ADDRBWRADDRL15", + "BRAM_BYP2_3", + "BRAM_ER1BEG2_1", + "BRAM_IMUX27_UTURN_0", + "BRAM_FIFO36_DIBDIU7", + "BRAM_LH3_0", + "BRAM_IMUX2_UTURN_4", + "BRAM_IMUX45_1", + "BRAM_ADDRBWRADDRU10", + "BRAM_FIFO36_ADDRBWRADDRU2", + "BRAM_FIFO36_DIBDIL12", + "BRAM_EE4BEG3_1", + "BRAM_FIFO36_TSTWROS4", + "BRAM_RAMB18_DOADO3", + "BRAM_IMUX23_UTURN_1", + "BRAM_FIFO36_ADDRBWRADDRL11", + "BRAM_UTURN_ADDRARDADDRU5", + "BRAM_NW2A2_3", + "BRAM_RAMB18_DOADO2", + "BRAM_LOGIC_OUTS_B18_2", + "BRAM_FIFO36_ADDRBWRADDRU9", + "BRAM_LOGIC_OUTS_B1_1", + "BRAM_IMUX27_UTURN_2", + "BRAM_FIFO36_TSTIN0", + "BRAM_IMUX28_UTURN_4", + "BRAM_IMUX23_UTURN_0", + "BRAM_EE2A0_4", + "BRAM_WW2END3_0", + "BRAM_WW4B1_3", + "BRAM_FIFO36_DIPADIPL1", + "BRAM_SE4C1_4", + "BRAM_FIFO36_DIADIU5", + "BRAM_EE4BEG0_0", + "BRAM_IMUX26_UTURN_2", + "BRAM_IMUX28_3", + "BRAM_ADDRARDADDRL4", + "BRAM_LOGIC_OUTS_B3_3", + "BRAM_FIFO36_DIADIL7", + "BRAM_IMUX36_UTURN_1", + "BRAM_CASCOUT_ADDRBWRADDRU0", + "BRAM_IMUX33_UTURN_2", + "BRAM_FIFO36_DOBDOU3", + "BRAM_RAMB18_WRCOUNT3", + "BRAM_SW4A3_2", + "BRAM_EE2A0_2", + "BRAM_WW2END0_2", + "BRAM_RAMB18_ADDRBWRADDR0", + "BRAM_FIFO18_DIBDI2", + "BRAM_BYP1_4", + "BRAM_IMUX39_UTURN_4", + "BRAM_BLOCK_OUTS_L_B2_1", + "BRAM_CASCOUT_ADDRARDADDRU14", + "BRAM_MONITOR_N_3", + "BRAM_FIFO36_DOADOL11", + "BRAM_RAMB18_WEBWE6", + "BRAM_FIFO36_RDERR", + "BRAM_IMUX20_4", + "BRAM_CASCINBOT_ADDRARDADDRU6", + "BRAM_LOGIC_OUTS_B23_4", + "BRAM_IMUX27_1", + "BRAM_UTURN_ADDRARDADDRL1", + "BRAM_IMUX_ADDRARDADDRU2", + "BRAM_BYP7_4", + "BRAM_FIFO18_DOBDO11", + "BRAM_IMUX19_UTURN_2", + "BRAM_WW4END0_3", + "BRAM_NE2A3_4", + "BRAM_IMUX21_3", + "BRAM_RAMB18_ALMOSTEMPTY", + "BRAM_EE4B2_4", + "BRAM_WR1END0_0", + "BRAM_FIFO18_DIADI13", + "BRAM_IMUX_ADDRARDADDRL9", + "BRAM_FAN7_2", + "BRAM_IMUX4_0", + "BRAM_EE4A2_2", + "BRAM_FIFO18_DOADO7", + "BRAM_LH11_2", + "BRAM_BYP2_4", + "BRAM_LH2_0", + "BRAM_IMUX43_UTURN_1", + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "BRAM_BYP3_0", + "BRAM_WW4END1_3", + "BRAM_LOGIC_OUTS_B22_1", + "BRAM_SW4A2_1", + "BRAM_FIFO18_WEA0", + "BRAM_WW4A3_3", + "BRAM_FAN7_3", + "BRAM_FIFO18_DIPBDIP1", + "BRAM_FIFO36_DIBDIL0", + "BRAM_NW4END1_4", + "BRAM_BYP4_3", + "BRAM_IMUX44_UTURN_4", + "BRAM_CLK0_1", + "BRAM_UTURN_ADDRBWRADDRU9", + "BRAM_FIFO18_DIADI10", + "BRAM_WW4END3_3", + "BRAM_IMUX40_2", + "BRAM_ER1BEG1_3", + "BRAM_RAMB18_ADDRARDADDR5", + "BRAM_IMUX22_3", + "BRAM_RAMB18_RDCOUNT10", + "BRAM_WW4B2_2", + "BRAM_EE4B2_2", + "BRAM_IMUX37_UTURN_2", + "BRAM_LOGIC_OUTS_B6_0", + "BRAM_FIFO18_RSTRAMB", + "BRAM_NW2A1_3", + "BRAM_IMUX23_3", + "BRAM_FIFO36_TSTBRAMRST", + "BRAM_FIFO18_WEBWE2", + "BRAM_IMUX9_UTURN_3", + "BRAM_FIFO18_DOBDO10", + "BRAM_FIFO36_WRCOUNT3", + "BRAM_CTRL1_4", + "BRAM_NE4C1_2", + "BRAM_WW4A1_0", + "BRAM_IMUX32_3", + "BRAM_FIFO36_DOADOU5", + "BRAM_SW4END3_3", + "BRAM_SW4A1_0", + "BRAM_EL1BEG2_3", + "BRAM_RAMB18_REGCEB", + "BRAM_FIFO36_DOADOL7", + "BRAM_RAMB18_ADDRBWRADDR1", + "BRAM_SE2A2_2", + "BRAM_IMUX2_4", + "BRAM_SW4END1_4", + "BRAM_EE4BEG2_3", + "BRAM_FIFO36_DOBDOU5", + "BRAM_FIFO18_DIADI5", + "BRAM_FIFO36_DOADOL4", + "BRAM_LH1_3", + "BRAM_FIFO36_DOBDOL4", + "BRAM_LOGIC_OUTS_B16_1", + "BRAM_EE2BEG0_0", + "BRAM_FIFO18_WEBWE0", + "BRAM_FIFO36_TSTCNT10", + "BRAM_IMUX11_UTURN_0", + "BRAM_RAMB18_DIADI5", + "BRAM_WW2A0_2", + "BRAM_FIFO18_DOBDO4", + "BRAM_FIFO36_ADDRARDADDRL9", + "BRAM_WL1END3_3", + "BRAM_BYP1_0", + "BRAM_UTURN_ADDRBWRADDRL2", + "BRAM_WW4C1_1", + "BRAM_IMUX29_UTURN_2", + "BRAM_RAMB18_RSTREGARSTREG", + "BRAM_FIFO36_RSTRAMBU", + "BRAM_IMUX3_0", + "BRAM_IMUX37_1", + "BRAM_EE2BEG1_4", + "BRAM_SE4BEG2_1", + "BRAM_UTURN_ADDRARDADDRL2", + "BRAM_FAN0_3", + "BRAM_IMUX21_0", + "BRAM_FIFO18_WRCOUNT5", + "BRAM_FIFO36_TSTWROS5", + "BRAM_FIFO36_DIADIU14", + "BRAM_IMUX22_2", + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "BRAM_WL1END3_4", + "BRAM_FIFO36_ECCPARITY3", + "BRAM_SW2A1_3", + "BRAM_LOGIC_OUTS_B4_3", + "BRAM_BLOCK_OUTS_L_B0_4", + "BRAM_FIFO36_DOPBDOPU1", + "BRAM_FIFO36_TSTRDCNTOFF", + "BRAM_FIFO36_ADDRBWRADDRL14", + "BRAM_LOGIC_OUTS_B10_1", + "BRAM_IMUX17_UTURN_1", + "BRAM_RAMB18_DIBDI7", + "BRAM_FIFO36_ADDRARDADDRU9", + "BRAM_EE4BEG1_4", + "BRAM_IMUX3_UTURN_0", + "BRAM_FIFO36_TSTRDOS4", + "BRAM_WW4C2_0", + "BRAM_IMUX15_UTURN_1", + "BRAM_FIFO18_DOBDO13", + "BRAM_FIFO36_ADDRARDADDRL0", + "BRAM_WW4C0_3", + "BRAM_EE2BEG0_4", + "BRAM_LOGIC_OUTS_B17_2", + "BRAM_IMUX36_UTURN_0", + "BRAM_ADDRARDADDRL5", + "BRAM_EE4B3_4", + "BRAM_NE4BEG0_4", + "BRAM_RAMB18_DIBDI13", + "BRAM_NE4C2_4", + "BRAM_WL1END1_0", + "BRAM_ADDRBWRADDRU0", + "BRAM_NW2A1_1", + "BRAM_RAMB18_DOADO12", + "BRAM_CTRL0_1", + "BRAM_RAMB18_DOBDO6", + "BRAM_FIFO36_ADDRARDADDRL11", + "BRAM_SW2A1_2", + "BRAM_IMUX10_3", + "BRAM_SW4A1_1", + "BRAM_BLOCK_OUTS_L_B3_2", + "BRAM_BLOCK_OUTS_L_B0_0", + "BRAM_LOGIC_OUTS_B13_4", + "BRAM_EE2BEG3_3", + "BRAM_ADDRARDADDRU14", + "BRAM_FIFO36_DOADOL5", + "BRAM_FAN6_0", + "BRAM_FAN2_0", + "BRAM_FAN1_3", + "BRAM_UTURN_ADDRBWRADDRL9", + "BRAM_LH8_2", + "BRAM_MONITOR_P_3", + "BRAM_FIFO36_RDCOUNT1", + "BRAM_FIFO36_DIADIL0", + "BRAM_BLOCK_OUTS_L_B2_0", + "BRAM_FIFO18_DIADI14", + "BRAM_FIFO36_DIBDIU2", + "BRAM_RAMB18_DOBDO2", + "BRAM_IMUX30_UTURN_3", + "BRAM_FIFO18_DOADO6", + "BRAM_LH8_4", + "BRAM_FIFO18_DOADO10", + "BRAM_RAMB18_ADDRARDADDR6", + "BRAM_FIFO18_DOBDO3", + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "BRAM_FIFO18_WRCOUNT3", + "BRAM_FIFO18_DIADI3", + "BRAM_SW4A2_0", + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "BRAM_WW4END0_2", + "BRAM_IMUX0_1", + "BRAM_LH12_3", + "BRAM_FIFO36_TSTCNT7", + "BRAM_IMUX_ADDRARDADDRU11", + "BRAM_SE4BEG0_3", + "BRAM_FIFO18_ALMOSTEMPTY", + "BRAM_ADDRBWRADDRL5", + "BRAM_IMUX46_UTURN_1", + "BRAM_FIFO36_WEBWEL3", + "BRAM_IMUX46_4", + "BRAM_RAMB18_REGCEAREGCE", + "BRAM_IMUX_ADDRBWRADDRU11", + "BRAM_FIFO36_DOBDOL11", + "BRAM_SE4C2_3", + "BRAM_NE2A2_1", + "BRAM_FAN4_2", + "BRAM_FIFO36_ADDRBWRADDRL9", + "BRAM_IMUX34_2", + "BRAM_FIFO18_RDCOUNT10", + "BRAM_FIFO36_TSTCNT12", + "BRAM_WL1END3_0", + "BRAM_WW2A1_1", + "BRAM_RAMB18_ADDRARDADDR9", + "BRAM_FIFO18_WRCOUNT6", + "BRAM_IMUX11_3", + "BRAM_IMUX_ADDRARDADDRL4", + "BRAM_ADDRBWRADDRU12", + "BRAM_IMUX17_2", + "BRAM_WW4B0_0", + "BRAM_UTURN_ADDRBWRADDRL0", + "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRAM_MONITOR_P_1", + "BRAM_EE4B1_3", + "BRAM_FIFO18_DIADI2", + "BRAM_FAN6_1", + "BRAM_IMUX8_UTURN_0", + "BRAM_SW4A3_1", + "BRAM_RAMB18_DIPADIP1", + "BRAM_ER1BEG1_0", + "BRAM_LOGIC_OUTS_B22_4", + "BRAM_EE4BEG3_2", + "BRAM_IMUX17_3", + "BRAM_CASCOUT_ADDRBWRADDRU2", + "BRAM_SW2A3_1", + "BRAM_WW4END1_2", + "BRAM_EE2A1_4", + "BRAM_IMUX18_3", + "BRAM_WW4A3_4", + "BRAM_IMUX22_1", + "BRAM_RAMB18_WEA0", + "BRAM_FIFO18_DIBDI1", + "BRAM_LH11_1", + "BRAM_BYP7_1", + "BRAM_FIFO36_DIBDIL5", + "BRAM_NE4BEG0_3", + "BRAM_FAN1_1", + "BRAM_FIFO36_DOPADOPL0", + "BRAM_WW2END0_0", + "BRAM_IMUX24_UTURN_2", + "BRAM_CLK1_2", + "BRAM_LOGIC_OUTS_B3_2", + "BRAM_RAMB18_DOADO11", + "BRAM_IMUX2_UTURN_2", + "BRAM_IMUX15_0", + "BRAM_IMUX6_UTURN_4", + "BRAM_IMUX36_UTURN_4", + "BRAM_FIFO36_DIADIL12", + "BRAM_FIFO36_RDCOUNT5", + "BRAM_RAMB18_ENARDEN", + "BRAM_IMUX27_3", + "BRAM_FIFO36_DOADOL12", + "BRAM_IMUX5_UTURN_4", + "BRAM_SW4END3_0", + "BRAM_RAMB18_WEBWE7", + "BRAM_IMUX1_2", + "BRAM_IMUX46_2", + "BRAM_IMUX45_UTURN_3", + "BRAM_WW4B1_2", + "BRAM_IMUX28_UTURN_0", + "BRAM_IMUX20_2", + "BRAM_LH9_0", + "BRAM_IMUX32_2", + "BRAM_FIFO36_DOADOL3", + "BRAM_IMUX_ADDRBWRADDRU13", + "BRAM_CASCOUT_ADDRARDADDRU9", + "BRAM_FAN5_4", + "BRAM_IMUX6_1", + "BRAM_LOGIC_OUTS_B3_0", + "BRAM_WW2END3_1", + "BRAM_SW2A0_2", + "BRAM_FIFO36_ADDRBWRADDRU10", + "BRAM_SE4C0_1", + "BRAM_FAN7_1", + "BRAM_IMUX14_UTURN_3", + "BRAM_RAMB18_DIADI8", + "BRAM_FIFO36_TSTCNT11", + "BRAM_CASCOUT_ADDRBWRADDRU8", + "BRAM_FIFO18_DIADI6", + "BRAM_LH10_1", + "BRAM_LOGIC_OUTS_B18_3", + "BRAM_FIFO36_REGCLKARDRCLKU", + "BRAM_FIFO36_WEBWEL6", + "BRAM_SW4END2_4", + "BRAM_CASCINBOT_ADDRARDADDRU1", + "BRAM_RAMB18_ADDRBWRADDR5", + "BRAM_FIFO36_ADDRARDADDRL14", + "BRAM_SW2A1_1", + "BRAM_FIFO18_RDCOUNT11", + "BRAM_IMUX12_UTURN_3", + "BRAM_IMUX16_4", + "BRAM_UTURN_ADDRARDADDRU14", + "BRAM_NE2A3_1", + "BRAM_UTURN_ADDRARDADDRU7", + "BRAM_CASCOUT_ADDRARDADDRU7", + "BRAM_SW4A0_2", + "BRAM_LOGIC_OUTS_B19_3", + "BRAM_IMUX46_UTURN_3", + "BRAM_IMUX18_2", + "BRAM_ADDRARDADDRU13", + "BRAM_FIFO18_RSTRAMARSTRAM", + "BRAM_RAMB18_DOBDO1", + "BRAM_FIFO18_DOADO1", + "BRAM_FIFO36_WEBWEU1", + "BRAM_FAN6_4", + "BRAM_NW4A1_3", + "BRAM_FIFO36_ENARDENL", + "BRAM_NW2A2_2", + "BRAM_IMUX20_UTURN_2", + "BRAM_FIFO36_ADDRBWRADDRU1", + "BRAM_FIFO18_DOBDO12", + "BRAM_ADDRBWRADDRU5", + "BRAM_ADDRBWRADDRU2", + "BRAM_FIFO36_ENBWRENU", + "BRAM_LH11_3", + "BRAM_RAMB18_ADDRBWRADDR7", + "BRAM_LOGIC_OUTS_B6_4", + "BRAM_LH10_3", + "BRAM_NW2A3_0", + "BRAM_EL1BEG1_1", + "BRAM_LH3_3", + "BRAM_IMUX_ADDRARDADDRU5", + "BRAM_IMUX_ADDRARDADDRL8", + "BRAM_FIFO36_ALMOSTEMPTY", + "BRAM_IMUX41_UTURN_1", + "BRAM_EE2BEG3_2", + "BRAM_IMUX38_UTURN_0", + "BRAM_FIFO36_RDCOUNT10", + "BRAM_LOGIC_OUTS_B0_0", + "BRAM_FIFO36_ADDRARDADDRU11", + "BRAM_NW4END3_3", + "BRAM_FIFO36_DOBDOL13", + "BRAM_ER1BEG2_0", + "BRAM_ADDRBWRADDRL6", + "BRAM_IMUX47_UTURN_1", + "BRAM_FIFO36_DOADOU2", + "BRAM_FIFO36_CLKARDCLKU", + "BRAM_FIFO36_DIPADIPU1", + "BRAM_FIFO36_DIBDIU12", + "BRAM_IMUX8_3", + "BRAM_EE4B1_0", + "BRAM_FIFO36_ADDRARDADDRU2", + "BRAM_NW2A0_2", + "BRAM_SW2A3_0", + "BRAM_BYP0_3", + "BRAM_NW4END0_0", + "BRAM_FIFO36_DOBDOL1", + "BRAM_IMUX19_0", + "BRAM_BLOCK_OUTS_L_B1_4", + "BRAM_LOGIC_OUTS_B9_1", + "BRAM_WW4END3_1", + "BRAM_IMUX44_2", + "BRAM_FIFO18_DIPADIP1", + "BRAM_IMUX21_UTURN_3", + "BRAM_IMUX17_0", + "BRAM_PMVBRAM_ODIV2", + "BRAM_RAMB18_ADDRARDADDR3", + "BRAM_IMUX45_2", + "BRAM_EE4BEG0_2", + "BRAM_NW2A2_1", + "BRAM_NE2A3_0", + "BRAM_LOGIC_OUTS_B12_0", + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "BRAM_FIFO36_WEAL0", + "BRAM_FIFO18_EMPTY", + "BRAM_ADDRARDADDRL11", + "BRAM_WW4END0_4", + "BRAM_WL1END3_2", + "BRAM_RAMB18_RDCOUNT0", + "BRAM_EE4C0_0", + "BRAM_IMUX35_UTURN_1", + "BRAM_IMUX29_0", + "BRAM_FIFO18_ADDRBTIEHIGH1", + "BRAM_WW4A2_3", + "BRAM_IMUX33_UTURN_3", + "BRAM_UTURN_ADDRARDADDRU9", + "BRAM_WW4A2_1", + "BRAM_EE4B0_4", + "BRAM_LH12_0", + "BRAM_FIFO36_TSTWROS7", + "BRAM_FAN4_3", + "BRAM_LOGIC_OUTS_B13_0", + "BRAM_IMUX14_UTURN_4", + "BRAM_EE4B1_1", + "BRAM_RAMB18_DOBDO12", + "BRAM_RAMB18_DIADI1", + "BRAM_IMUX32_UTURN_1", + "BRAM_IMUX35_0", + "BRAM_FIFO18_WRCOUNT8", + "BRAM_SE4C3_1", + "BRAM_WW4C2_2", + "BRAM_FAN1_0", + "BRAM_CASCINBOT_ADDRARDADDRU2", + "BRAM_IMUX34_UTURN_0", + "BRAM_RAMB18_DOBDO15", + "BRAM_IMUX6_3", + "BRAM_UTURN_ADDRBWRADDRU4", + "BRAM_LH8_1", + "BRAM_IMUX_ADDRBWRADDRU8", + "BRAM_IMUX35_4", + "BRAM_LH5_0", + "BRAM_IMUX8_4", + "BRAM_ER1BEG3_4", + "BRAM_IMUX29_UTURN_3", + "BRAM_IMUX13_UTURN_1", + "BRAM_EE4A0_3", + "BRAM_IMUX5_4", + "BRAM_FIFO36_TSTWROS8", + "BRAM_FIFO36_DOBDOU2", + "BRAM_IMUX37_UTURN_1", + "BRAM_EE2A2_4", + "BRAM_FIFO18_WRCOUNT2", + "BRAM_SW4END3_1", + "BRAM_FIFO36_DIBDIL4", + "BRAM_SE4BEG3_3", + "BRAM_FIFO18_DOPADOP1", + "BRAM_WW4A2_4", + "BRAM_WW4A1_2", + "BRAM_CASCOUT_ADDRARDADDRU6", + "BRAM_FIFO36_DOBDOL6", + "BRAM_RAMB18_ADDRARDADDR2", + "BRAM_IMUX10_2", + "BRAM_FIFO36_CLKBWRCLKU", + "BRAM_FIFO36_DOBDOU0", + "BRAM_IMUX31_0", + "BRAM_EE2BEG3_0", + "BRAM_IMUX5_UTURN_3", + "BRAM_IMUX_ADDRARDADDRU13", + "BRAM_FIFO36_ECCPARITY2", + "BRAM_WL1END0_0", + "BRAM_NE4BEG1_0", + "BRAM_EL1BEG3_3", + "BRAM_EE4BEG0_4", + "BRAM_FIFO36_DIBDIU6", + "BRAM_IMUX17_UTURN_0", + "BRAM_LOGIC_OUTS_B23_0", + "BRAM_SW4END0_2", + "BRAM_LOGIC_OUTS_B8_0", + "BRAM_UTURN_ADDRBWRADDRU8", + "BRAM_SW2A2_0", + "BRAM_IMUX_ADDRBWRADDRU4", + "BRAM_IMUX16_3", + "BRAM_IMUX23_0", + "BRAM_SE2A0_0", + "BRAM_BYP5_3", + "BRAM_IMUX16_UTURN_3", + "BRAM_FIFO36_DOADOL0", + "BRAM_RAMB18_ENBWREN", + "BRAM_IMUX16_UTURN_2", + "BRAM_ER1BEG0_0", + "BRAM_IMUX6_4", + "BRAM_EE4B3_2", + "BRAM_IMUX_ADDRBWRADDRL4", + "BRAM_IMUX17_1", + "BRAM_FIFO36_TSTOFF", + "BRAM_FIFO36_DOADOU11", + "BRAM_CASCINBOT_ADDRARDADDRU3", + "BRAM_FIFO18_DOADO2", + "BRAM_LOGIC_OUTS_B22_3", + "BRAM_IMUX_ADDRBWRADDRU0", + "BRAM_IMUX31_UTURN_0", + "BRAM_LOGIC_OUTS_B8_2", + "BRAM_FAN0_0", + "BRAM_WR1END1_4", + "BRAM_LOGIC_OUTS_B17_1", + "BRAM_FIFO18_FULL", + "BRAM_FIFO18_WEBWE1", + "BRAM_IMUX12_1", + "BRAM_IMUX34_3", + "BRAM_WR1END0_3", + "BRAM_NW4END3_1", + "BRAM_FIFO36_TSTOUT2", + "BRAM_LOGIC_OUTS_B2_4", + "BRAM_IMUX11_UTURN_3", + "BRAM_SW4END1_3", + "BRAM_UTURN_ADDRARDADDRU11", + "BRAM_WW2END0_1", + "BRAM_FIFO36_DOBDOL2", + "BRAM_LH5_1", + "BRAM_IMUX17_UTURN_4", + "BRAM_SE2A0_2", + "BRAM_WW4B0_1", + "BRAM_UTURN_ADDRBWRADDRU0", + "BRAM_FIFO36_WEAU2", + "BRAM_FIFO36_REGCEAREGCEU", + "BRAM_LOGIC_OUTS_B9_3", + "BRAM_EE2BEG3_1", + "BRAM_LH5_4", + "BRAM_IMUX2_0", + "BRAM_IMUX_ADDRARDADDRL15", + "BRAM_RAMB18_FULL", + "BRAM_EE4BEG1_0", + "BRAM_ER1BEG0_1", + "BRAM_RAMB18_DOADO4", + "BRAM_NW4A1_4", + "BRAM_IMUX22_UTURN_4", + "BRAM_FIFO36_DOBDOL9", + "BRAM_FIFO18_WRCOUNT10", + "BRAM_WW4B3_1", + "BRAM_NE4BEG2_1", + "BRAM_CASCOUT_ADDRARDADDRU13", + "BRAM_IMUX4_2", + "BRAM_IMUX30_UTURN_4", + "BRAM_LOGIC_OUTS_B8_3", + "BRAM_CLK1_0", + "BRAM_LOGIC_OUTS_B20_4", + "BRAM_FIFO36_DIADIL10", + "BRAM_EE2A1_0", + "BRAM_RAMB18_CLKARDCLK", + "BRAM_IMUX19_4", + "BRAM_IMUX14_2", + "BRAM_ADDRARDADDRU12", + "BRAM_RAMB18_RDCOUNT5", + "BRAM_LOGIC_OUTS_B7_4", + "BRAM_LOGIC_OUTS_B18_1", + "BRAM_FIFO36_TSTRDOS3", + "BRAM_LH4_1", + "BRAM_IMUX27_0", + "BRAM_FIFO36_RDCOUNT8", + "BRAM_LH12_2", + "BRAM_FIFO36_WRCOUNT6", + "BRAM_IMUX43_4", + "BRAM_RAMB18_DOBDO14", + "BRAM_RAMB18_DOBDO10", + "BRAM_IMUX25_1", + "BRAM_SW4END2_2", + "BRAM_IMUX38_UTURN_4", + "BRAM_FIFO18_DIBDI3", + "BRAM_BLOCK_OUTS_L_B0_3", + "BRAM_IMUX9_3", + "BRAM_IMUX23_UTURN_4", + "BRAM_RAMB18_DOADO10", + "BRAM_RAMB18_DIADI12", + "BRAM_WR1END3_4", + "BRAM_PMVBRAM_SELECT2", + "BRAM_FIFO36_DIADIU7", + "BRAM_FIFO18_DOADO14", + "BRAM_SE4C3_3", + "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRAM_CASCOUT_ADDRBWRADDRU10", + "BRAM_IMUX0_4", + "BRAM_IMUX36_UTURN_3", + "BRAM_LOGIC_OUTS_B15_1", + "BRAM_IMUX0_0", + "BRAM_CASCINBOT_ADDRARDADDRU5", + "BRAM_BYP3_1", + "BRAM_FIFO36_TSTCNT8", + "BRAM_LOGIC_OUTS_B14_3", + "BRAM_RAMB18_WRCOUNT10", + "BRAM_SW4END1_2", + "BRAM_FIFO36_ADDRBWRADDRL6", + "BRAM_NE2A0_3", + "BRAM_FIFO36_CASCADEOUTA_1", + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "BRAM_IMUX35_UTURN_3", + "BRAM_NE4BEG1_4", + "BRAM_MONITOR_P_0", + "BRAM_EE4BEG1_1", + "BRAM_FIFO36_DOBDOU12", + "BRAM_RAMB18_ADDRBWRADDR4", + "BRAM_PMVBRAM_SELECT4", + "BRAM_LH10_2", + "BRAM_FIFO36_DIBDIU14", + "BRAM_NE4C3_1", + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "BRAM_ADDRARDADDRU3", + "BRAM_FIFO36_DIBDIL14", + "BRAM_ADDRBWRADDRL8", + "BRAM_ADDRARDADDRU2", + "BRAM_NW4A2_4", + "BRAM_NE2A0_2", + "BRAM_WW4B2_4", + "BRAM_RAMB18_DIADI0", + "BRAM_EE4B1_2", + "BRAM_FAN1_2", + "BRAM_FIFO36_CASCADEINA", + "BRAM_ADDRBWRADDRL4", + "BRAM_UTURN_ADDRARDADDRL14", + "BRAM_CASCOUT_ADDRBWRADDRU11", + "BRAM_LOGIC_OUTS_B7_1", + "BRAM_FIFO36_DIBDIU13", + "BRAM_IMUX15_1", + "BRAM_NE2A1_4", + "BRAM_ADDRBWRADDRL2", + "BRAM_FIFO36_ADDRBWRADDRU8", + "BRAM_FIFO36_ADDRBWRADDRL5", + "BRAM_NW4A3_2", + "BRAM_WW4C1_2", + "BRAM_LOGIC_OUTS_B13_2", + "BRAM_WW4A0_0", + "BRAM_FIFO18_REGCEB", + "BRAM_FIFO36_TSTCNT4", + "BRAM_FIFO36_REGCLKBL", + "BRAM_LOGIC_OUTS_B4_2", + "BRAM_RAMB18_DOADO1", + "BRAM_RAMB18_WRCOUNT7", + "BRAM_IMUX44_1", + "BRAM_ADDRBWRADDRL12", + "BRAM_FIFO18_ADDRARDADDR7", + "BRAM_FIFO36_TSTWROS0", + "BRAM_SE2A3_1", + "BRAM_IMUX7_0", + "BRAM_EE4C0_2", + "BRAM_IMUX17_UTURN_3", + "BRAM_UTURN_ADDRBWRADDRU10", + "BRAM_WW4END2_0", + "BRAM_LOGIC_OUTS_B2_1", + "BRAM_RAMB18_WRCOUNT9", + "BRAM_FIFO36_DOPBDOPU0", + "BRAM_ADDRARDADDRL13", + "BRAM_EL1BEG2_2", + "BRAM_WW4B1_1", + "BRAM_FIFO36_DIADIU1", + "BRAM_WW4A0_3", + "BRAM_RAMB18_ALMOSTFULL", + "BRAM_IMUX12_UTURN_0", + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "BRAM_BLOCK_OUTS_L_B1_0", + "BRAM_BLOCK_OUTS_L_B0_1", + "BRAM_EE4C1_4", + "BRAM_IMUX12_UTURN_1", + "BRAM_IMUX35_3", + "BRAM_NE4C0_4", + "BRAM_BYP5_2", + "BRAM_FAN3_0", + "BRAM_FIFO36_DIBDIL11", + "BRAM_SW2A3_3", + "BRAM_FIFO36_ADDRARDADDRU8", + "BRAM_LH8_0", + "BRAM_IMUX4_UTURN_4", + "BRAM_IMUX_ADDRBWRADDRL14", + "BRAM_IMUX_ADDRARDADDRL3", + "BRAM_LOGIC_OUTS_B5_4", + "BRAM_FIFO36_WRCOUNT11", + "BRAM_FIFO36_DIBDIL10", + "BRAM_NE4BEG0_2", + "BRAM_IMUX47_3", + "BRAM_LOGIC_OUTS_B16_0", + "BRAM_IMUX24_4", + "BRAM_FAN3_3", + "BRAM_FIFO18_ADDRARDADDR2", + "BRAM_FIFO36_DOBDOL8", + "BRAM_FIFO36_INJECTSBITERR", + "BRAM_FIFO36_REGCEAREGCEL", + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "BRAM_IMUX20_3", + "BRAM_IMUX35_UTURN_2", + "BRAM_RAMB18_RSTRAMB", + "BRAM_IMUX29_4", + "BRAM_SE2A3_2", + "BRAM_FIFO36_DOBDOL12", + "BRAM_BYP5_4", + "BRAM_SE4C3_2", + "BRAM_ADDRARDADDRU9", + "BRAM_CASCOUT_ADDRBWRADDRU12", + "BRAM_IMUX39_UTURN_2", + "BRAM_FIFO36_ADDRARDADDRU0", + "BRAM_IMUX15_UTURN_4", + "BRAM_FIFO18_DOADO9", + "BRAM_IMUX42_0", + "BRAM_RAMB18_DIADI6", + "BRAM_ADDRBWRADDRL9", + "BRAM_FIFO18_ADDRARDADDR9", + "BRAM_FIFO18_DOADO8", + "BRAM_SW4END1_1", + "BRAM_WW2A1_2", + "BRAM_IMUX_ADDRBWRADDRU2", + "BRAM_FIFO18_DOADO12", + "BRAM_CASCINBOT_ADDRARDADDRU9", + "BRAM_IMUX7_2", + "BRAM_UTURN_ADDRARDADDRL4", + "BRAM_BYP3_3", + "BRAM_FIFO36_TSTRDOS7", + "BRAM_FIFO36_RDCOUNT2", + "BRAM_FIFO18_DIBDI8", + "BRAM_ADDRBWRADDRU1", + "BRAM_IMUX35_UTURN_4", + "BRAM_IMUX46_0", + "BRAM_LOGIC_OUTS_B17_0", + "BRAM_IMUX10_UTURN_1", + "BRAM_SE2A2_4", + "BRAM_IMUX43_2", + "BRAM_IMUX9_0", + "BRAM_RAMB18_ADDRARDADDR1", + "BRAM_FIFO36_TSTFLAGIN", + "BRAM_FIFO36_DOPBDOPL0", + "BRAM_EL1BEG2_1", + "BRAM_FIFO18_WEBWE7", + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "BRAM_SW4END0_3", + "BRAM_IMUX27_UTURN_1", + "BRAM_UTURN_ADDRARDADDRU6", + "BRAM_CASCINBOT_ADDRARDADDRU8", + "BRAM_UTURN_ADDRBWRADDRU11", + "BRAM_FIFO18_DOPADOP0", + "BRAM_SE4C2_0", + "BRAM_SE4C0_3", + "BRAM_NE4BEG2_3", + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "BRAM_IMUX_ADDRBWRADDRL6", + "BRAM_LOGIC_OUTS_B3_1", + "BRAM_IMUX6_UTURN_2", + "BRAM_LOGIC_OUTS_B14_4", + "BRAM_FIFO36_ADDRBWRADDRL2", + "BRAM_EE4A0_0", + "BRAM_EE2BEG2_3", + "BRAM_LH11_4", + "BRAM_IMUX25_UTURN_2", + "BRAM_ADDRBWRADDRU7", + "BRAM_FIFO36_DOBDOU10", + "BRAM_LOGIC_OUTS_B5_0", + "BRAM_IMUX14_UTURN_0", + "BRAM_NE4C1_4", + "BRAM_SE2A0_4", + "BRAM_NE4BEG2_2", + "BRAM_FAN7_0", + "BRAM_SW4END3_4", + "BRAM_IMUX23_UTURN_3", + "BRAM_WW4A1_1", + "BRAM_LH12_4", + "BRAM_EE4C0_4", + "BRAM_FIFO18_WEBWE3", + "BRAM_SE4C0_2", + "BRAM_FIFO36_DOADOL8", + "BRAM_FIFO36_TSTRDOS11", + "BRAM_IMUX10_UTURN_4", + "BRAM_WW4B0_2", + "BRAM_FIFO18_ADDRATIEHIGH1", + "BRAM_FIFO18_ADDRARDADDR3", + "BRAM_IMUX24_UTURN_3", + "BRAM_IMUX38_2", + "BRAM_WW4B0_4", + "BRAM_WW4C1_3", + "BRAM_IMUX36_UTURN_2", + "BRAM_CTRL0_3", + "BRAM_SE4BEG1_4", + "BRAM_FIFO36_SBITERR", + "BRAM_IMUX41_1", + "BRAM_LOGIC_OUTS_B10_0", + "BRAM_FIFO36_TSTCNT1", + "BRAM_IMUX7_UTURN_2", + "BRAM_IMUX7_4", + "BRAM_FIFO36_TSTRDOS8", + "BRAM_IMUX3_1", + "BRAM_WW2END1_3", + "BRAM_WW2A3_3", + "BRAM_WW4B2_0", + "BRAM_RAMB18_DIADI2", + "BRAM_ER1BEG3_0", + "BRAM_WW2END3_4", + "BRAM_ADDRBWRADDRL14", + "BRAM_SE4BEG3_0", + "BRAM_RAMB18_RSTRAMARSTRAM", + "BRAM_FIFO18_DOADO15", + "BRAM_ER1BEG0_3", + "BRAM_FIFO36_ADDRBWRADDRU4", + "BRAM_FIFO18_WEA2", + "BRAM_FIFO36_ALMOSTFULL", + "BRAM_WL1END2_1", + "BRAM_NE4BEG3_0", + "BRAM_RAMB18_DOBDO5", + "BRAM_FIFO18_DIBDI7", + "BRAM_RAMB18_DIBDI15", + "BRAM_IMUX4_UTURN_3", + "BRAM_NW4A0_2", + "BRAM_FIFO18_WRERR", + "BRAM_FIFO36_WEBWEL4", + "BRAM_SE2A1_0", + "BRAM_CASCINBOT_ADDRARDADDRU14", + "BRAM_IMUX4_UTURN_1", + "BRAM_FIFO36_WEBWEL2", + "BRAM_PMVBRAM_O_2", + "BRAM_EE2BEG0_1", + "BRAM_IMUX5_1", + "BRAM_IMUX21_4", + "BRAM_FIFO36_TSTRDOS9", + "BRAM_LH7_2", + "BRAM_FIFO36_WEBWEU4", + "BRAM_ADDRBWRADDRU11", + "BRAM_IMUX12_UTURN_2", + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "BRAM_NW2A1_0", + "BRAM_RAMB18_DIBDI6", + "BRAM_IMUX20_UTURN_0", + "BRAM_IMUX41_4", + "BRAM_WW2END2_2", + "BRAM_MONITOR_P_4", + "BRAM_EE2A1_2", + "BRAM_BLOCK_OUTS_L_B1_1", + "BRAM_RAMB18_DIBDI5", + "BRAM_FIFO36_DIADIL14", + "BRAM_ER1BEG0_2", + "BRAM_FIFO36_WEBWEU6", + "BRAM_IMUX10_UTURN_3", + "BRAM_UTURN_ADDRARDADDRU1", + "BRAM_PMVBRAM_O", + "BRAM_LOGIC_OUTS_B1_2", + "BRAM_WR1END0_1", + "BRAM_IMUX_ADDRARDADDRL5", + "BRAM_FIFO18_WEA3", + "BRAM_IMUX45_4", + "BRAM_WW2A0_3", + "BRAM_LOGIC_OUTS_B1_0", + "BRAM_IMUX23_1", + "BRAM_IMUX_ADDRBWRADDRU12", + "BRAM_FIFO36_TSTCNT9", + "BRAM_UTURN_ADDRBWRADDRL15", + "BRAM_NE4C0_1", + "BRAM_IMUX20_UTURN_3", + "BRAM_BYP2_0", + "BRAM_CASCOUT_ADDRBWRADDRU9", + "BRAM_FIFO36_DIADIU2", + "BRAM_RAMB18_DIADI10", + "BRAM_LOGIC_OUTS_B10_3", + "BRAM_IMUX14_1", + "BRAM_WW4B0_3", + "BRAM_FIFO36_WRCOUNT1", + "BRAM_IMUX31_UTURN_2", + "BRAM_FIFO36_DIBDIL15", + "BRAM_IMUX0_UTURN_3", + "BRAM_CLK0_0", + "BRAM_WW2A2_3", + "BRAM_WW4END3_0", + "BRAM_FIFO36_DIPBDIPU0", + "BRAM_LH7_0", + "BRAM_IMUX47_UTURN_0", + "BRAM_FIFO18_DIADI11", + "BRAM_IMUX25_4", + "BRAM_IMUX26_1", + "BRAM_MONITOR_N_0", + "BRAM_WW4B3_3", + "BRAM_CLK1_3", + "BRAM_RAMB18_DIADI7", + "BRAM_CTRL1_2", + "BRAM_LOGIC_OUTS_B10_2", + "BRAM_IMUX42_UTURN_0", + "BRAM_NE2A2_0", + "BRAM_WR1END0_4", + "BRAM_FIFO18_REGCEAREGCE", + "BRAM_FAN4_4", + "BRAM_LOGIC_OUTS_B0_3", + "BRAM_PMVBRAM_SELECT1", + "BRAM_IMUX34_1", + "BRAM_EL1BEG0_2", + "BRAM_UTURN_ADDRBWRADDRL4", + "BRAM_FIFO18_RDCOUNT2", + "BRAM_RAMB18_DIBDI3", + "BRAM_LH1_2", + "BRAM_FIFO18_WEA1", + "BRAM_EE4A1_4", + "BRAM_EL1BEG3_0", + "BRAM_IMUX28_UTURN_2", + "BRAM_IMUX15_2", + "BRAM_EE4BEG0_1", + "BRAM_RAMB18_RDCOUNT3", + "BRAM_IMUX_ADDRBWRADDRL0", + "BRAM_IMUX46_1", + "BRAM_RAMB18_REGCLKB", + "BRAM_IMUX15_UTURN_2", + "BRAM_EE4A1_0", + "BRAM_FIFO18_DIADI1", + "BRAM_RAMB18_ADDRBWRADDR12", + "BRAM_LH1_1", + "BRAM_IMUX2_UTURN_1", + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "BRAM_LOGIC_OUTS_B13_3", + "BRAM_FIFO18_WRCOUNT9", + "BRAM_FIFO18_RDCOUNT8", + "BRAM_FIFO18_ADDRBWRADDR0", + "BRAM_LH7_3", + "BRAM_NE4C2_3", + "BRAM_NE4BEG3_1", + "BRAM_NW4END1_2", + "BRAM_IMUX23_4", + "BRAM_EE4A2_0", + "BRAM_FIFO18_WRCOUNT0", + "BRAM_RAMB18_WRCOUNT2", + "BRAM_LH3_4", + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "BRAM_FIFO36_DOADOL13", + "BRAM_LOGIC_OUTS_B16_2", + "BRAM_FIFO36_TSTOUT3", + "BRAM_IMUX25_2", + "BRAM_SE4C1_1", + "BRAM_LOGIC_OUTS_B20_3", + "BRAM_FIFO18_ADDRBWRADDR7", + "BRAM_NW2A3_3", + "BRAM_WW2END2_0", + "BRAM_IMUX19_2", + "BRAM_ADDRARDADDRL1", + "BRAM_NW2A3_1", + "BRAM_FIFO18_DIADI12", + "BRAM_EE2A0_3", + "BRAM_EE4B1_4", + "BRAM_ADDRARDADDRU11", + "BRAM_CASCOUT_ADDRARDADDRU0", + "BRAM_UTURN_ADDRBWRADDRU12", + "BRAM_EE4BEG3_0", + "BRAM_SE4BEG0_2", + "BRAM_FIFO36_DOADOU4", + "BRAM_ADDRARDADDRL7", + "BRAM_WR1END1_0", + "BRAM_LOGIC_OUTS_B3_4", + "BRAM_BLOCK_OUTS_L_B3_0", + "BRAM_IMUX29_UTURN_0", + "BRAM_IMUX2_2", + "BRAM_EE4C1_2", + "BRAM_IMUX14_0", + "BRAM_RAMB18_DIBDI2", + "BRAM_IMUX13_UTURN_0", + "BRAM_CASCINBOT_ADDRARDADDRU0", + "BRAM_WW2A2_4", + "BRAM_IMUX37_UTURN_3", + "BRAM_RAMB18_DOADO7", + "BRAM_FIFO36_ADDRARDADDRU5", + "BRAM_IMUX29_UTURN_4", + "BRAM_WW2A3_4", + "BRAM_BLOCK_OUTS_L_B1_2", + "BRAM_FIFO36_DIBDIU0", + "BRAM_BYP0_0", + "BRAM_FIFO36_TSTRDOS10", + "BRAM_NE4C3_4", + "BRAM_LH2_4", + "BRAM_RAMB18_DOBDO3", + "BRAM_LOGIC_OUTS_B2_3", + "BRAM_BYP7_0", + "BRAM_FIFO36_ADDRBWRADDRU14", + "BRAM_IMUX47_0", + "BRAM_CASCOUT_ADDRARDADDRU5", + "BRAM_FIFO36_TSTIN1", + "BRAM_FIFO36_DOBDOL15", + "BRAM_SE4C2_2", + "BRAM_RAMB18_WRCOUNT6", + "BRAM_FIFO18_DOBDO1", + "BRAM_SW4A0_1", + "BRAM_FIFO36_REGCLKARDRCLKL", + "BRAM_FIFO36_RSTRAMARSTRAMU", + "BRAM_UTURN_ADDRARDADDRU4", + "BRAM_PMVBRAM_O_1", + "BRAM_RAMB18_RDERR", + "BRAM_NW4END2_2", + "BRAM_IMUX_ADDRBWRADDRL12", + "BRAM_IMUX34_UTURN_2", + "BRAM_FIFO36_WEBWEU3", + "BRAM_IMUX30_0", + "BRAM_IMUX19_UTURN_4", + "BRAM_IMUX8_1", + "BRAM_ER1BEG2_3", + "BRAM_EE4A3_4", + "BRAM_IMUX33_UTURN_1", + "BRAM_NE4C0_2", + "BRAM_UTURN_ADDRARDADDRU12", + "BRAM_RAMB18_WRCOUNT8", + "BRAM_IMUX24_3", + "BRAM_EE2A0_0", + "BRAM_IMUX43_UTURN_3", + "BRAM_RAMB18_WEA3", + "BRAM_IMUX47_1", + "BRAM_IMUX39_3", + "BRAM_IMUX47_UTURN_4", + "BRAM_EL1BEG1_3", + "BRAM_IMUX3_UTURN_2", + "BRAM_FIFO18_ADDRARDADDR6", + "BRAM_NW4A1_1", + "BRAM_RAMB18_ADDRBTIEHIGH1", + "BRAM_IMUX18_4", + "BRAM_CTRL0_2", + "BRAM_NW4A2_2", + "BRAM_NE2A1_2", + "BRAM_LH6_3", + "BRAM_SE4BEG1_0", + "BRAM_FIFO36_CASCADEOUTA", + "BRAM_WW2A2_2", + "BRAM_RAMB18_DIBDI9", + "BRAM_FIFO18_DIADI7", + "BRAM_FIFO36_WEBWEL0", + "BRAM_UTURN_ADDRARDADDRU0", + "BRAM_WL1END0_2", + "BRAM_EL1BEG3_1", + "BRAM_LOGIC_OUTS_B10_4", + "BRAM_FIFO36_TSTRDOS5", + "BRAM_WW2A3_2", + "BRAM_WL1END0_1", + "BRAM_WW4B3_0", + "BRAM_FIFO36_DOBDOU1", + "BRAM_LH5_3", + "BRAM_IMUX30_1", + "BRAM_SE4C1_0", + "BRAM_IMUX40_UTURN_0", + "BRAM_BLOCK_OUTS_L_B1_3", + "BRAM_ADDRBWRADDRL13", + "BRAM_NE4BEG3_2", + "BRAM_WW2A1_0", + "BRAM_WW4END3_4", + "BRAM_ADDRBWRADDRU8", + "BRAM_FIFO18_DOBDO14", + "BRAM_FIFO18_ADDRARDADDR13", + "BRAM_FIFO36_WEAL2", + "BRAM_FIFO36_TSTWROS10", + "BRAM_IMUX42_UTURN_3", + "BRAM_IMUX40_UTURN_2", + "BRAM_FIFO36_WEBWEL7", + "BRAM_IMUX44_4", + "BRAM_RAMB18_WEBWE0", + "BRAM_SE2A2_1", + "BRAM_FIFO36_DIBDIU15", + "BRAM_IMUX25_UTURN_3", + "BRAM_WW4B2_3", + "BRAM_BYP6_2", + "BRAM_RAMB18_DIADI13", + "BRAM_IMUX_ADDRARDADDRL1", + "BRAM_FIFO18_DIPADIP0", + "BRAM_WR1END0_2", + "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRAM_NW4A0_3", + "BRAM_FIFO18_WEBWE5", + "BRAM_RAMB18_ADDRARDADDR12", + "BRAM_RAMB18_WRCOUNT11", + "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRAM_SE2A1_2", + "BRAM_SE2A1_4", + "BRAM_LOGIC_OUTS_B2_2", + "BRAM_IMUX32_UTURN_2", + "BRAM_NE4BEG1_1", + "BRAM_CASCOUT_ADDRBWRADDRU13", + "BRAM_IMUX14_UTURN_2", + "BRAM_FIFO36_ENARDENU", + "BRAM_IMUX22_0", + "BRAM_EE4BEG2_1", + "BRAM_EE4B0_1", + "BRAM_RAMB18_WEBWE5", + "BRAM_FIFO36_DOADOU0", + "BRAM_SW4A2_2", + "BRAM_SW4A1_4", + "BRAM_IMUX16_UTURN_4", + "BRAM_UTURN_ADDRBWRADDRL14", + "BRAM_WL1END0_4", + "BRAM_EL1BEG0_0", + "BRAM_NE2A0_0", + "BRAM_RAMB18_CLKBWRCLK", + "BRAM_IMUX29_3", + "BRAM_LOGIC_OUTS_B6_3", + "BRAM_IMUX_ADDRARDADDRL10", + "BRAM_NE4BEG1_3", + "BRAM_IMUX42_1", + "BRAM_FIFO36_ADDRBWRADDRL1", + "BRAM_FAN0_1", + "BRAM_IMUX1_UTURN_1", + "BRAM_WW4A3_1", + "BRAM_IMUX19_UTURN_0", + "BRAM_CASCINBOT_ADDRARDADDRU4", + "BRAM_FIFO36_ADDRARDADDRL2", + "BRAM_BYP2_1", + "BRAM_IMUX34_0", + "BRAM_EL1BEG1_4", + "BRAM_LOGIC_OUTS_B21_1", + "BRAM_IMUX45_UTURN_1", + "BRAM_FIFO36_INJECTDBITERR", + "BRAM_FIFO18_DIBDI6", + "BRAM_LH2_3", + "BRAM_CTRL0_4", + "BRAM_FAN2_4", + "BRAM_RAMB18_ADDRBWRADDR9", + "BRAM_EE4C3_3", + "BRAM_LOGIC_OUTS_B2_0", + "BRAM_NE4C2_2", + "BRAM_ADDRARDADDRU6", + "BRAM_SE2A1_3", + "BRAM_FIFO36_WRCOUNT0", + "BRAM_IMUX30_4", + "BRAM_FAN2_3", + "BRAM_NW4A3_1", + "BRAM_IMUX26_UTURN_0", + "BRAM_FIFO36_WRERR", + "BRAM_RAMB18_ADDRARDADDR0", + "BRAM_WW4C3_2", + "BRAM_FIFO36_TSTIN3", + "BRAM_RAMB18_RDCOUNT1", + "BRAM_FIFO18_CLKARDCLK", + "BRAM_WW4C1_4", + "BRAM_LOGIC_OUTS_B4_1", + "BRAM_ADDRBWRADDRU4", + "BRAM_ER1BEG2_2", + "BRAM_FIFO36_RDCOUNT3", + "BRAM_FIFO36_ECCPARITY7", + "BRAM_IMUX10_4", + "BRAM_BYP1_3", + "BRAM_NW4END3_2", + "BRAM_ADDRBWRADDRU14", + "BRAM_IMUX46_UTURN_4", + "BRAM_LOGIC_OUTS_B15_3", + "BRAM_FIFO18_ALMOSTFULL", + "BRAM_IMUX12_4", + "BRAM_UTURN_ADDRBWRADDRL10", + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "BRAM_BLOCK_OUTS_L_B2_4", + "BRAM_FIFO36_DOBDOU9", + "BRAM_EE4C3_2" + ], + "pips": { + "BRAM_L.BRAM_IMUX37_0->BRAM_FIFO18_DIBDI10": { + "src_wire": "BRAM_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK0_3->BRAM_FIFO18_CLKARDCLK": { + "src_wire": "BRAM_CLK0_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_CLKARDCLK", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX45_3->BRAM_RAMB18_DIADI11": { + "src_wire": "BRAM_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOPADOPL1->BRAM_LOGIC_OUTS_B0_1": { + "src_wire": "BRAM_FIFO36_DOPADOPL1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO8->BRAM_LOGIC_OUTS_B0_0": { + "src_wire": "BRAM_FIFO18_DOADO8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL1->BRAM_LOGIC_OUTS_B1_0": { + "src_wire": "BRAM_FIFO36_DOBDOL1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY0->BRAM_LOGIC_OUTS_B18_3": { + "src_wire": "BRAM_FIFO36_ECCPARITY0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_RAMB18_ADDRBWRADDR5": { + "src_wire": "BRAM_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX32_1->BRAM_FIFO36_DIBDIL0": { + "src_wire": "BRAM_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK1_3->BRAM_FIFO36_CLKARDCLKU": { + "src_wire": "BRAM_CLK1_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKARDCLKU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO0->BRAM_LOGIC_OUTS_B3_2": { + "src_wire": "BRAM_RAMB18_DOBDO0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX10_4->BRAM_FIFO36_DIADIU5": { + "src_wire": "BRAM_IMUX10_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK1_4->BRAM_RAMB18_REGCLKARDRCLK": { + "src_wire": "BRAM_CLK1_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCLKARDRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { + "src_wire": "BRAM_FIFO18_WRCOUNT3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_RAMB18_ADDRBWRADDR12": { + "src_wire": "BRAM_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX30_4->BRAM_FIFO36_TSTCNT12": { + "src_wire": "BRAM_IMUX30_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL9->>BRAM_FIFO36_ADDRARDADDRL9": { + "src_wire": "BRAM_ADDRARDADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_CASCOUT_ADDRBWRADDRU1": { + "src_wire": "BRAM_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX1_3->BRAM_FIFO36_DIBDIU1": { + "src_wire": "BRAM_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX1_1->BRAM_FIFO18_DIPBDIP1": { + "src_wire": "BRAM_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPBDIP1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRERR->BRAM_LOGIC_OUTS_B23_2": { + "src_wire": "BRAM_FIFO36_WRERR", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOPBDOP1->BRAM_LOGIC_OUTS_B17_3": { + "src_wire": "BRAM_RAMB18_DOPBDOP1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL13->BRAM_ADDRBWRADDRL13": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { + "src_wire": "BRAM_FIFO18_WRCOUNT6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_CASCOUT_ADDRARDADDRU11": { + "src_wire": "BRAM_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX46_1->BRAM_FIFO36_DIADIL14": { + "src_wire": "BRAM_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL1_3->BRAM_RAMB18_RSTRAMARSTRAM": { + "src_wire": "BRAM_CTRL1_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTRAMARSTRAM", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX29_0->BRAM_FIFO36_DIADIL10": { + "src_wire": "BRAM_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_BYP6_2->BRAM_FIFO18_WEBWE7": { + "src_wire": "BRAM_BYP6_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX3_1->BRAM_FIFO18_DIBDI12": { + "src_wire": "BRAM_IMUX3_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX31_2->BRAM_FIFO36_INJECTDBITERR": { + "src_wire": "BRAM_IMUX31_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_INJECTDBITERR", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { + "src_wire": "BRAM_FIFO36_RDCOUNT3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL5->>BRAM_FIFO18_ADDRARDADDR4": { + "src_wire": "BRAM_ADDRARDADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO1->BRAM_LOGIC_OUTS_B13_0": { + "src_wire": "BRAM_FIFO18_DOADO1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL12->>BRAM_UTURN_ADDRARDADDRL12": { + "src_wire": "BRAM_ADDRARDADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL6->>BRAM_FIFO36_ADDRARDADDRL6": { + "src_wire": "BRAM_ADDRARDADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_UTURN_ADDRARDADDRU14": { + "src_wire": "BRAM_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX10_2->BRAM_FIFO36_ENARDENU": { + "src_wire": "BRAM_IMUX10_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENARDENU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_FIFO18_ADDRATIEHIGH0": { + "src_wire": "BRAM_ADDRARDADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_UTURN_ADDRARDADDRU7": { + "src_wire": "BRAM_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX25_0->BRAM_FIFO18_DIADI8": { + "src_wire": "BRAM_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU7->BRAM_LOGIC_OUTS_B15_4": { + "src_wire": "BRAM_FIFO36_DOADOU7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX44_3->BRAM_RAMB18_DIADI3": { + "src_wire": "BRAM_IMUX44_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO6->BRAM_LOGIC_OUTS_B3_1": { + "src_wire": "BRAM_FIFO18_DOBDO6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX24_4->BRAM_FIFO36_TSTCNT6": { + "src_wire": "BRAM_IMUX24_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX20_4->BRAM_FIFO36_DIBDIU6": { + "src_wire": "BRAM_IMUX20_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL0_4->BRAM_FIFO36_RSTREGARSTREGL": { + "src_wire": "BRAM_CTRL0_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGARSTREGL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK0_0->BRAM_FIFO36_REGCLKBL": { + "src_wire": "BRAM_CLK0_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKBL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_FIFO36_ADDRBWRADDRU10": { + "src_wire": "BRAM_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL13->>BRAM_FIFO18_ADDRARDADDR12": { + "src_wire": "BRAM_ADDRARDADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_RAMB18_ADDRARDADDR0": { + "src_wire": "BRAM_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO3->BRAM_LOGIC_OUTS_B15_0": { + "src_wire": "BRAM_FIFO18_DOADO3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX39_2->BRAM_FIFO36_INJECTSBITERR": { + "src_wire": "BRAM_IMUX39_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_INJECTSBITERR", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX5_1->BRAM_FIFO18_DIBDI13": { + "src_wire": "BRAM_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL2->>BRAM_UTURN_ADDRBWRADDRL2": { + "src_wire": "BRAM_ADDRBWRADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_CASCOUT_ADDRARDADDRU0": { + "src_wire": "BRAM_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_RAMB18_ADDRARDADDR8": { + "src_wire": "BRAM_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL7->>BRAM_FIFO18_ADDRBWRADDR6": { + "src_wire": "BRAM_ADDRBWRADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_EMPTY->BRAM_LOGIC_OUTS_B6_2": { + "src_wire": "BRAM_FIFO36_EMPTY", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_CASCOUT_ADDRBWRADDRU14": { + "src_wire": "BRAM_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL5->BRAM_LOGIC_OUTS_B10_1": { + "src_wire": "BRAM_FIFO36_DOADOL5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX29_3->BRAM_IMUX_ADDRBWRADDRU12": { + "src_wire": "BRAM_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { + "src_wire": "BRAM_FIFO36_WRCOUNT7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL2->BRAM_ADDRARDADDRL2": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU5->BRAM_LOGIC_OUTS_B13_4": { + "src_wire": "BRAM_FIFO36_DOADOU5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_RAMB18_ADDRBTIEHIGH0": { + "src_wire": "BRAM_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX42_1->BRAM_FIFO18_DIADI12": { + "src_wire": "BRAM_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL9->BRAM_ADDRBWRADDRL9": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX44_3->BRAM_FIFO36_DIADIU3": { + "src_wire": "BRAM_IMUX44_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL14->>BRAM_UTURN_ADDRARDADDRL14": { + "src_wire": "BRAM_ADDRARDADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX38_4->BRAM_FIFO36_TSTRDOS12": { + "src_wire": "BRAM_IMUX38_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_UTURN_ADDRBWRADDRU14": { + "src_wire": "BRAM_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO13->BRAM_LOGIC_OUTS_B19_4": { + "src_wire": "BRAM_RAMB18_DOBDO13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_FIFO36_ADDRBWRADDRU1": { + "src_wire": "BRAM_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX14_0->BRAM_FIFO36_TSTCNT4": { + "src_wire": "BRAM_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL3->>BRAM_FIFO18_ADDRBWRADDR2": { + "src_wire": "BRAM_ADDRBWRADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX17_2->BRAM_FIFO36_WEAL2": { + "src_wire": "BRAM_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL4->>BRAM_FIFO36_ADDRBWRADDRL4": { + "src_wire": "BRAM_ADDRBWRADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO6->BRAM_LOGIC_OUTS_B10_4": { + "src_wire": "BRAM_RAMB18_DOADO6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL15->BRAM_LOGIC_OUTS_B22_2": { + "src_wire": "BRAM_FIFO36_DOBDOL15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOPBDOP0->BRAM_LOGIC_OUTS_B3_3": { + "src_wire": "BRAM_RAMB18_DOPBDOP0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX5_3->BRAM_RAMB18_DIBDI3": { + "src_wire": "BRAM_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK0_4->BRAM_FIFO18_REGCLKARDRCLK": { + "src_wire": "BRAM_CLK0_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCLKARDRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX26_1->BRAM_IMUX_ADDRBWRADDRU1": { + "src_wire": "BRAM_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_RAMB18_ADDRARDADDR3": { + "src_wire": "BRAM_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL10->>BRAM_FIFO36_ADDRBWRADDRL10": { + "src_wire": "BRAM_ADDRBWRADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { + "src_wire": "BRAM_FIFO36_WRCOUNT2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX45_1->BRAM_FIFO36_DIADIL6": { + "src_wire": "BRAM_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_RAMB18_ADDRBWRADDR2": { + "src_wire": "BRAM_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL5->BRAM_ADDRARDADDRL5": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL4->BRAM_ADDRBWRADDRL4": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { + "src_wire": "BRAM_FIFO36_WRCOUNT11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL2->>BRAM_FIFO36_ADDRBWRADDRL2": { + "src_wire": "BRAM_ADDRBWRADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX15_0->BRAM_FIFO36_TSTCNT5": { + "src_wire": "BRAM_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU6->BRAM_LOGIC_OUTS_B6_4": { + "src_wire": "BRAM_FIFO36_DOBDOU6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { + "src_wire": "BRAM_FIFO18_RDCOUNT5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX34_0->BRAM_FIFO18_DIBDI1": { + "src_wire": "BRAM_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_FIFO36_ADDRARDADDRU7": { + "src_wire": "BRAM_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_UTURN_ADDRBWRADDRU7": { + "src_wire": "BRAM_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO5->BRAM_LOGIC_OUTS_B1_4": { + "src_wire": "BRAM_RAMB18_DOBDO5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY7->BRAM_LOGIC_OUTS_B11_3": { + "src_wire": "BRAM_FIFO36_ECCPARITY7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_FIFO36_ADDRARDADDRL0": { + "src_wire": "BRAM_ADDRARDADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_FIFO36_ADDRBWRADDRU3": { + "src_wire": "BRAM_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL8->>BRAM_FIFO18_ADDRARDADDR7": { + "src_wire": "BRAM_ADDRARDADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL12->BRAM_LOGIC_OUTS_B19_1": { + "src_wire": "BRAM_FIFO36_DOBDOL12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL1_1->BRAM_FIFO36_RSTRAMBU": { + "src_wire": "BRAM_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMBU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL12->BRAM_ADDRBWRADDRL12": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX11_4->BRAM_FIFO36_DIADIU13": { + "src_wire": "BRAM_IMUX11_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX4_1->BRAM_FIFO36_DIBDIL5": { + "src_wire": "BRAM_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { + "src_wire": "BRAM_FIFO36_RDCOUNT8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX36_3->BRAM_IMUX_ADDRBWRADDRL5": { + "src_wire": "BRAM_IMUX36_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX21_4->BRAM_RAMB18_DIBDI14": { + "src_wire": "BRAM_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL0_0->BRAM_FIFO36_RSTREGBL": { + "src_wire": "BRAM_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGBL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_UTURN_ADDRARDADDRU13": { + "src_wire": "BRAM_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL10->BRAM_ADDRBWRADDRL10": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_UTURN_ADDRARDADDRL0": { + "src_wire": "BRAM_ADDRARDADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_CASCOUT_ADDRARDADDRU3": { + "src_wire": "BRAM_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL4->BRAM_ADDRARDADDRL4": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL13->>BRAM_UTURN_ADDRARDADDRL13": { + "src_wire": "BRAM_ADDRARDADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX10_1->BRAM_IMUX_ADDRARDADDRU1": { + "src_wire": "BRAM_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL8->BRAM_LOGIC_OUTS_B22_0": { + "src_wire": "BRAM_FIFO36_DOBDOL8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX19_0->BRAM_FIFO36_TSTRDOS1": { + "src_wire": "BRAM_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_FIFO36_ADDRBWRADDRU6": { + "src_wire": "BRAM_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK1_1->BRAM_RAMB18_CLKBWRCLK": { + "src_wire": "BRAM_CLK1_1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_CLKBWRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO12->BRAM_LOGIC_OUTS_B19_1": { + "src_wire": "BRAM_FIFO18_DOBDO12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL1_0->BRAM_RAMB18_RSTREGB": { + "src_wire": "BRAM_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTREGB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX34_3->BRAM_IMUX_ADDRBWRADDRL3": { + "src_wire": "BRAM_IMUX34_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_CASCOUT_ADDRBWRADDRU10": { + "src_wire": "BRAM_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO12->BRAM_LOGIC_OUTS_B0_4": { + "src_wire": "BRAM_RAMB18_DOADO12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX39_0->BRAM_FIFO36_DIBDIL11": { + "src_wire": "BRAM_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX22_0->BRAM_FIFO36_TSTRDOS4": { + "src_wire": "BRAM_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX13_3->BRAM_IMUX_ADDRARDADDRU12": { + "src_wire": "BRAM_IMUX13_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX28_3->BRAM_IMUX_ADDRBWRADDRU5": { + "src_wire": "BRAM_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_UTURN_ADDRBWRADDRU0": { + "src_wire": "BRAM_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL3->BRAM_LOGIC_OUTS_B3_0": { + "src_wire": "BRAM_FIFO36_DOBDOL3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL3->>BRAM_FIFO36_ADDRBWRADDRL3": { + "src_wire": "BRAM_ADDRBWRADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX18_0->BRAM_FIFO36_TSTRDOS0": { + "src_wire": "BRAM_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { + "src_wire": "BRAM_FIFO36_WRCOUNT5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_UTURN_ADDRBWRADDRU12": { + "src_wire": "BRAM_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX45_2->BRAM_FIFO36_WEBWEU3": { + "src_wire": "BRAM_IMUX45_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { + "src_wire": "BRAM_FIFO18_ALMOSTEMPTY", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOPBDOPL0->BRAM_LOGIC_OUTS_B4_1": { + "src_wire": "BRAM_FIFO36_DOPBDOPL0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO6->BRAM_LOGIC_OUTS_B6_4": { + "src_wire": "BRAM_RAMB18_DOBDO6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK0_3->BRAM_FIFO36_CLKARDCLKL": { + "src_wire": "BRAM_CLK0_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKARDCLKL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL13->>BRAM_FIFO36_ADDRBWRADDRL13": { + "src_wire": "BRAM_ADDRBWRADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_CASCOUT_ADDRBWRADDRU4": { + "src_wire": "BRAM_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX42_3->BRAM_RAMB18_DIADI2": { + "src_wire": "BRAM_IMUX42_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO13->BRAM_LOGIC_OUTS_B20_1": { + "src_wire": "BRAM_FIFO18_DOBDO13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK1_0->BRAM_RAMB18_REGCLKB": { + "src_wire": "BRAM_CLK1_0", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU2->BRAM_LOGIC_OUTS_B13_3": { + "src_wire": "BRAM_FIFO36_DOADOU2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY5->BRAM_LOGIC_OUTS_B20_2": { + "src_wire": "BRAM_FIFO36_ECCPARITY5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK0_4->BRAM_FIFO36_REGCLKARDRCLKL": { + "src_wire": "BRAM_CLK0_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO7->BRAM_LOGIC_OUTS_B3_4": { + "src_wire": "BRAM_RAMB18_DOBDO7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU0->BRAM_LOGIC_OUTS_B3_2": { + "src_wire": "BRAM_FIFO36_DOBDOU0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX4_4->BRAM_FIFO36_TSTIN2": { + "src_wire": "BRAM_IMUX4_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU4->BRAM_LOGIC_OUTS_B8_4": { + "src_wire": "BRAM_FIFO36_DOADOU4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL0_4->BRAM_FIFO18_RSTREGARSTREG": { + "src_wire": "BRAM_CTRL0_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTREGARSTREG", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { + "src_wire": "BRAM_FIFO18_RDCOUNT0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO10->BRAM_LOGIC_OUTS_B20_0": { + "src_wire": "BRAM_FIFO18_DOBDO10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { + "src_wire": "BRAM_FIFO18_WRCOUNT0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX1_3->BRAM_RAMB18_DIBDI1": { + "src_wire": "BRAM_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL6->BRAM_ADDRBWRADDRL6": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX10_2->BRAM_RAMB18_ENARDEN": { + "src_wire": "BRAM_IMUX10_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ENARDEN", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL8->>BRAM_UTURN_ADDRBWRADDRL8": { + "src_wire": "BRAM_ADDRBWRADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX35_3->BRAM_IMUX_ADDRBWRADDRL9": { + "src_wire": "BRAM_IMUX35_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX25_0->BRAM_FIFO36_DIADIL8": { + "src_wire": "BRAM_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX30_2->BRAM_FIFO36_WEBWEU6": { + "src_wire": "BRAM_IMUX30_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_FIFO36_ADDRARDADDRU10": { + "src_wire": "BRAM_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU13->BRAM_LOGIC_OUTS_B5_4": { + "src_wire": "BRAM_FIFO36_DOADOU13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_UTURN_ADDRBWRADDRU9": { + "src_wire": "BRAM_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX16_1->BRAM_FIFO18_DIADI0": { + "src_wire": "BRAM_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX46_1->BRAM_FIFO18_DIADI14": { + "src_wire": "BRAM_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX13_2->BRAM_FIFO36_WEBWEU1": { + "src_wire": "BRAM_IMUX13_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_CASCOUT_ADDRBWRADDRU3": { + "src_wire": "BRAM_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX33_1->BRAM_IMUX_ADDRBWRADDRL0": { + "src_wire": "BRAM_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL13->>BRAM_FIFO18_ADDRBWRADDR12": { + "src_wire": "BRAM_ADDRBWRADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { + "src_wire": "BRAM_FIFO18_WRCOUNT4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_FIFO18_ADDRBTIEHIGH1": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOPBDOPU0->BRAM_LOGIC_OUTS_B3_3": { + "src_wire": "BRAM_FIFO36_DOPBDOPU0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL14->>BRAM_FIFO36_ADDRARDADDRL14": { + "src_wire": "BRAM_ADDRARDADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO8->BRAM_LOGIC_OUTS_B7_2": { + "src_wire": "BRAM_RAMB18_DOADO8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX6_2->BRAM_FIFO18_WEBWE4": { + "src_wire": "BRAM_IMUX6_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY4->BRAM_LOGIC_OUTS_B10_2": { + "src_wire": "BRAM_FIFO36_ECCPARITY4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX9_3->BRAM_IMUX_ADDRARDADDRU7": { + "src_wire": "BRAM_IMUX9_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_FIFO36_ADDRARDADDRU5": { + "src_wire": "BRAM_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX27_2->BRAM_RAMB18_REGCEB": { + "src_wire": "BRAM_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCEB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_RAMB18_ADDRBWRADDR8": { + "src_wire": "BRAM_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOPBDOP0->BRAM_LOGIC_OUTS_B4_1": { + "src_wire": "BRAM_FIFO18_DOPBDOP0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX40_1->BRAM_FIFO18_DIPADIP1": { + "src_wire": "BRAM_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPADIP1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX30_1->BRAM_IMUX_ADDRBWRADDRU11": { + "src_wire": "BRAM_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX8_4->BRAM_FIFO36_DIADIU4": { + "src_wire": "BRAM_IMUX8_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX29_2->BRAM_RAMB18_WEBWE2": { + "src_wire": "BRAM_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_RAMB18_ADDRARDADDR10": { + "src_wire": "BRAM_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL2->BRAM_LOGIC_OUTS_B10_0": { + "src_wire": "BRAM_FIFO36_DOADOL2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX41_2->BRAM_FIFO36_DIADIL15": { + "src_wire": "BRAM_IMUX41_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_UTURN_ADDRARDADDRU10": { + "src_wire": "BRAM_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX26_2->BRAM_FIFO36_ENBWRENU": { + "src_wire": "BRAM_IMUX26_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENBWRENU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX24_1->BRAM_FIFO36_DIBDIU0": { + "src_wire": "BRAM_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_CASCOUT_ADDRARDADDRU6": { + "src_wire": "BRAM_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_FULL->BRAM_LOGIC_OUTS_B5_2": { + "src_wire": "BRAM_FIFO18_FULL", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_CASCOUT_ADDRARDADDRU9": { + "src_wire": "BRAM_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL11->>BRAM_UTURN_ADDRARDADDRL11": { + "src_wire": "BRAM_ADDRARDADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX41_4->BRAM_FIFO36_TSTWROS7": { + "src_wire": "BRAM_IMUX41_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX21_2->BRAM_FIFO18_WEBWE1": { + "src_wire": "BRAM_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_TSTOUT3->BRAM_LOGIC_OUTS_B11_1": { + "src_wire": "BRAM_FIFO36_TSTOUT3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX24_2->BRAM_RAMB18_WEA1": { + "src_wire": "BRAM_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX3_3->BRAM_FIFO36_DIBDIU2": { + "src_wire": "BRAM_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { + "src_wire": "BRAM_FIFO36_RDCOUNT0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL6->>BRAM_FIFO18_ADDRARDADDR5": { + "src_wire": "BRAM_ADDRARDADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_RAMB18_ADDRATIEHIGH1": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO1->BRAM_LOGIC_OUTS_B1_0": { + "src_wire": "BRAM_FIFO18_DOBDO1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_BYP3_2->BRAM_FIFO18_WEBWE3": { + "src_wire": "BRAM_BYP3_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU1->BRAM_LOGIC_OUTS_B8_3": { + "src_wire": "BRAM_FIFO36_DOADOU1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_CASCOUT_ADDRARDADDRU10": { + "src_wire": "BRAM_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_FIFO36_ADDRBWRADDRU0": { + "src_wire": "BRAM_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX23_1->BRAM_IMUX_ADDRARDADDRL13": { + "src_wire": "BRAM_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX25_3->BRAM_IMUX_ADDRBWRADDRU7": { + "src_wire": "BRAM_IMUX25_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { + "src_wire": "BRAM_FIFO36_WRCOUNT6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL10->>BRAM_UTURN_ADDRBWRADDRL10": { + "src_wire": "BRAM_ADDRBWRADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX32_4->BRAM_FIFO36_TSTRDOS6": { + "src_wire": "BRAM_IMUX32_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_CASCOUT_ADDRARDADDRU8": { + "src_wire": "BRAM_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_FIFO36_ADDRARDADDRU12": { + "src_wire": "BRAM_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX21_1->BRAM_IMUX_ADDRARDADDRL4": { + "src_wire": "BRAM_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX23_2->BRAM_FIFO36_DIBDIU8": { + "src_wire": "BRAM_IMUX23_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_UTURN_ADDRARDADDRU11": { + "src_wire": "BRAM_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU14->BRAM_LOGIC_OUTS_B20_4": { + "src_wire": "BRAM_FIFO36_DOBDOU14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_RAMB18_ADDRARDADDR7": { + "src_wire": "BRAM_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { + "src_wire": "BRAM_FIFO18_WRCOUNT5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX34_2->BRAM_FIFO18_ENBWREN": { + "src_wire": "BRAM_IMUX34_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ENBWREN", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX4_2->BRAM_FIFO36_DIPBDIPL0": { + "src_wire": "BRAM_IMUX4_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX23_0->BRAM_FIFO36_TSTRDOS5": { + "src_wire": "BRAM_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX14_3->BRAM_IMUX_ADDRARDADDRU14": { + "src_wire": "BRAM_IMUX14_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL2->>BRAM_FIFO18_ADDRBWRADDR1": { + "src_wire": "BRAM_ADDRBWRADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_CASCOUT_ADDRARDADDRU1": { + "src_wire": "BRAM_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX32_1->BRAM_FIFO18_DIBDI0": { + "src_wire": "BRAM_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_UTURN_ADDRBWRADDRU3": { + "src_wire": "BRAM_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX31_0->BRAM_FIFO36_DIADIL11": { + "src_wire": "BRAM_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK1_3->BRAM_RAMB18_CLKARDCLK": { + "src_wire": "BRAM_CLK1_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_CLKARDCLK", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX36_0->BRAM_FIFO36_DIBDIL2": { + "src_wire": "BRAM_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_CASCOUT_ADDRBWRADDRU6": { + "src_wire": "BRAM_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_RAMB18_ADDRBWRADDR10": { + "src_wire": "BRAM_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX30_0->BRAM_FIFO18_DIADI3": { + "src_wire": "BRAM_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOPBDOPL1->BRAM_LOGIC_OUTS_B22_1": { + "src_wire": "BRAM_FIFO36_DOPBDOPL1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX16_2->BRAM_FIFO36_WEAL0": { + "src_wire": "BRAM_IMUX16_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX45_1->BRAM_FIFO18_DIADI6": { + "src_wire": "BRAM_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX15_4->BRAM_FIFO36_DIADIU15": { + "src_wire": "BRAM_IMUX15_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO10->BRAM_LOGIC_OUTS_B19_3": { + "src_wire": "BRAM_RAMB18_DOBDO10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX16_2->BRAM_FIFO18_WEA0": { + "src_wire": "BRAM_IMUX16_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { + "src_wire": "BRAM_FIFO18_RDCOUNT11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL1->BRAM_LOGIC_OUTS_B13_0": { + "src_wire": "BRAM_FIFO36_DOADOL1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL7->>BRAM_FIFO18_ADDRARDADDR6": { + "src_wire": "BRAM_ADDRARDADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_CASCOUT_ADDRBWRADDRU12": { + "src_wire": "BRAM_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_UTURN_ADDRBWRADDRU1": { + "src_wire": "BRAM_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX12_0->BRAM_FIFO36_TSTCNT2": { + "src_wire": "BRAM_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO3->BRAM_LOGIC_OUTS_B3_0": { + "src_wire": "BRAM_FIFO18_DOBDO3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { + "src_wire": "BRAM_FIFO36_ALMOSTEMPTY", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT12->BRAM_LOGIC_OUTS_B23_4": { + "src_wire": "BRAM_FIFO36_WRCOUNT12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL6->>BRAM_FIFO18_ADDRBWRADDR5": { + "src_wire": "BRAM_ADDRBWRADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL7->>BRAM_UTURN_ADDRBWRADDRL7": { + "src_wire": "BRAM_ADDRBWRADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { + "src_wire": "BRAM_FIFO18_RDCOUNT9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_FIFO36_ADDRBWRADDRU8": { + "src_wire": "BRAM_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_CASCOUT_ADDRBWRADDRU5": { + "src_wire": "BRAM_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX15_1->BRAM_IMUX_ADDRARDADDRU13": { + "src_wire": "BRAM_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX4_1->BRAM_FIFO18_DIBDI5": { + "src_wire": "BRAM_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { + "src_wire": "BRAM_FIFO18_WRCOUNT10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX33_0->BRAM_FIFO36_DIBDIL8": { + "src_wire": "BRAM_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL5->>BRAM_UTURN_ADDRARDADDRL5": { + "src_wire": "BRAM_ADDRARDADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX17_1->BRAM_IMUX_ADDRARDADDRL0": { + "src_wire": "BRAM_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO9->BRAM_LOGIC_OUTS_B22_3": { + "src_wire": "BRAM_RAMB18_DOBDO9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU3->BRAM_LOGIC_OUTS_B10_3": { + "src_wire": "BRAM_FIFO36_DOADOU3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX28_0->BRAM_FIFO18_DIADI2": { + "src_wire": "BRAM_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX19_2->BRAM_FIFO36_REGCEAREGCEL": { + "src_wire": "BRAM_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEAREGCEL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX44_4->BRAM_FIFO36_TSTWROS10": { + "src_wire": "BRAM_IMUX44_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL14->>BRAM_FIFO36_ADDRBWRADDRL14": { + "src_wire": "BRAM_ADDRBWRADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_CASCOUT_ADDRARDADDRU7": { + "src_wire": "BRAM_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX25_1->BRAM_IMUX_ADDRBWRADDRU0": { + "src_wire": "BRAM_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU4->BRAM_LOGIC_OUTS_B4_4": { + "src_wire": "BRAM_FIFO36_DOBDOU4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX26_0->BRAM_FIFO18_DIADI1": { + "src_wire": "BRAM_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX13_4->BRAM_FIFO36_DIADIU14": { + "src_wire": "BRAM_IMUX13_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL0->>BRAM_FIFO36_ADDRBWRADDRL0": { + "src_wire": "BRAM_ADDRBWRADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOPADOP0->BRAM_LOGIC_OUTS_B8_1": { + "src_wire": "BRAM_FIFO18_DOPADOP0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_FIFO36_ADDRARDADDRU14": { + "src_wire": "BRAM_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX5_2->BRAM_FIFO36_WEBWEL0": { + "src_wire": "BRAM_IMUX5_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU3->BRAM_LOGIC_OUTS_B6_3": { + "src_wire": "BRAM_FIFO36_DOBDOU3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX19_4->BRAM_FIFO36_DIBDIU13": { + "src_wire": "BRAM_IMUX19_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL7->BRAM_ADDRBWRADDRL7": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX15_4->BRAM_RAMB18_DIADI15": { + "src_wire": "BRAM_IMUX15_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL4->BRAM_LOGIC_OUTS_B1_1": { + "src_wire": "BRAM_FIFO36_DOBDOL4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { + "src_wire": "BRAM_FIFO36_WRCOUNT1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX38_3->BRAM_IMUX_ADDRBWRADDRL14": { + "src_wire": "BRAM_IMUX38_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX31_1->BRAM_IMUX_ADDRBWRADDRU13": { + "src_wire": "BRAM_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_UTURN_ADDRBWRADDRU5": { + "src_wire": "BRAM_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX3_0->BRAM_FIFO36_TSTWRCNTOFF": { + "src_wire": "BRAM_IMUX3_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWRCNTOFF", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX38_0->BRAM_FIFO36_DIBDIL3": { + "src_wire": "BRAM_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_RAMB18_ADDRARDADDR4": { + "src_wire": "BRAM_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX21_3->BRAM_IMUX_ADDRARDADDRL12": { + "src_wire": "BRAM_IMUX21_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_RAMB18_ADDRARDADDR9": { + "src_wire": "BRAM_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_FIFO36_ADDRARDADDRU1": { + "src_wire": "BRAM_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL5->>BRAM_FIFO36_ADDRARDADDRL5": { + "src_wire": "BRAM_ADDRARDADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL14->BRAM_ADDRARDADDRL14": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO2->BRAM_LOGIC_OUTS_B13_3": { + "src_wire": "BRAM_RAMB18_DOADO2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL4->>BRAM_UTURN_ADDRBWRADDRL4": { + "src_wire": "BRAM_ADDRBWRADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX18_2->BRAM_FIFO18_ENARDEN": { + "src_wire": "BRAM_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ENARDEN", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX3_1->BRAM_FIFO36_DIBDIL12": { + "src_wire": "BRAM_IMUX3_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX6_2->BRAM_FIFO36_WEBWEL4": { + "src_wire": "BRAM_IMUX6_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_UTURN_ADDRARDADDRU6": { + "src_wire": "BRAM_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX41_0->BRAM_FIFO36_TSTIN4": { + "src_wire": "BRAM_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_FIFO36_ADDRARDADDRL1": { + "src_wire": "BRAM_ADDRARDADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL6->>BRAM_FIFO36_ADDRBWRADDRL6": { + "src_wire": "BRAM_ADDRBWRADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL1_3->BRAM_FIFO36_RSTRAMARSTRAMU": { + "src_wire": "BRAM_CTRL1_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_SBITERR->BRAM_LOGIC_OUTS_B9_2": { + "src_wire": "BRAM_FIFO36_SBITERR", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO0->BRAM_LOGIC_OUTS_B4_0": { + "src_wire": "BRAM_FIFO18_DOBDO0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX29_1->BRAM_IMUX_ADDRBWRADDRU4": { + "src_wire": "BRAM_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX37_0->BRAM_FIFO36_DIBDIL10": { + "src_wire": "BRAM_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL8->>BRAM_FIFO36_ADDRBWRADDRL8": { + "src_wire": "BRAM_ADDRBWRADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL8->>BRAM_UTURN_ADDRARDADDRL8": { + "src_wire": "BRAM_ADDRARDADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FAN1_2->BRAM_RAMB18_WEBWE4": { + "src_wire": "BRAM_FAN1_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_FIFO36_ADDRBWRADDRU13": { + "src_wire": "BRAM_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX11_3->BRAM_IMUX_ADDRARDADDRU9": { + "src_wire": "BRAM_IMUX11_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_UTURN_ADDRBWRADDRU4": { + "src_wire": "BRAM_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL8->BRAM_ADDRBWRADDRL8": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX40_2->BRAM_FIFO36_DIADIL7": { + "src_wire": "BRAM_IMUX40_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK0_1->BRAM_FIFO18_CLKBWRCLK": { + "src_wire": "BRAM_CLK0_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_CLKBWRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL12->>BRAM_UTURN_ADDRBWRADDRL12": { + "src_wire": "BRAM_ADDRBWRADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL12->>BRAM_FIFO18_ADDRBWRADDR11": { + "src_wire": "BRAM_ADDRBWRADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL6->BRAM_LOGIC_OUTS_B3_1": { + "src_wire": "BRAM_FIFO36_DOBDOL6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_FIFO36_ADDRARDADDRU4": { + "src_wire": "BRAM_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX9_4->BRAM_FIFO36_DIADIU12": { + "src_wire": "BRAM_IMUX9_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_RAMB18_ADDRBWRADDR3": { + "src_wire": "BRAM_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL8->>BRAM_FIFO36_ADDRARDADDRL8": { + "src_wire": "BRAM_ADDRARDADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX3_2->BRAM_FIFO18_DIPADIP0": { + "src_wire": "BRAM_IMUX3_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPADIP0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL0->BRAM_LOGIC_OUTS_B8_0": { + "src_wire": "BRAM_FIFO36_DOADOL0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX10_0->BRAM_FIFO36_TSTCNT0": { + "src_wire": "BRAM_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL14->>BRAM_FIFO18_ADDRARDADDR13": { + "src_wire": "BRAM_ADDRARDADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL4->>BRAM_FIFO18_ADDRARDADDR3": { + "src_wire": "BRAM_ADDRARDADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX40_3->BRAM_RAMB18_DIADI1": { + "src_wire": "BRAM_IMUX40_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_FIFO36_ADDRBWRADDRU7": { + "src_wire": "BRAM_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX5_0->BRAM_FIFO36_TSTFLAGIN": { + "src_wire": "BRAM_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTFLAGIN", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU14->BRAM_LOGIC_OUTS_B2_4": { + "src_wire": "BRAM_FIFO36_DOADOU14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { + "src_wire": "BRAM_FIFO18_WRCOUNT1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL14->BRAM_LOGIC_OUTS_B17_1": { + "src_wire": "BRAM_FIFO36_DOBDOL14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL8->BRAM_LOGIC_OUTS_B0_0": { + "src_wire": "BRAM_FIFO36_DOADOL8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX14_4->BRAM_RAMB18_DIADI7": { + "src_wire": "BRAM_IMUX14_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX34_0->BRAM_FIFO36_DIBDIL1": { + "src_wire": "BRAM_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO6->BRAM_LOGIC_OUTS_B15_1": { + "src_wire": "BRAM_FIFO18_DOADO6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { + "src_wire": "BRAM_FIFO18_WRCOUNT2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX1_1->BRAM_FIFO36_DIPBDIPL1": { + "src_wire": "BRAM_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_RAMB18_ADDRBWRADDR13": { + "src_wire": "BRAM_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_RAMB18_ADDRARDADDR11": { + "src_wire": "BRAM_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL14->BRAM_LOGIC_OUTS_B7_1": { + "src_wire": "BRAM_FIFO36_DOADOL14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL4->>BRAM_FIFO18_ADDRBWRADDR3": { + "src_wire": "BRAM_ADDRBWRADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX25_2->BRAM_RAMB18_WEA3": { + "src_wire": "BRAM_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_CASCOUT_ADDRBWRADDRU9": { + "src_wire": "BRAM_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { + "src_wire": "BRAM_FIFO36_RDCOUNT4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_UTURN_ADDRARDADDRL15": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_EMPTY->BRAM_LOGIC_OUTS_B6_2": { + "src_wire": "BRAM_FIFO18_EMPTY", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX12_3->BRAM_IMUX_ADDRARDADDRU5": { + "src_wire": "BRAM_IMUX12_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO15->BRAM_LOGIC_OUTS_B0_2": { + "src_wire": "BRAM_FIFO18_DOADO15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_UTURN_ADDRARDADDRU5": { + "src_wire": "BRAM_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX8_4->BRAM_RAMB18_DIADI4": { + "src_wire": "BRAM_IMUX8_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_FIFO36_ADDRBWRADDRL15": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX33_3->BRAM_IMUX_ADDRBWRADDRL7": { + "src_wire": "BRAM_IMUX33_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX32_2->BRAM_FIFO36_WEAL1": { + "src_wire": "BRAM_IMUX32_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO10->BRAM_LOGIC_OUTS_B2_0": { + "src_wire": "BRAM_FIFO18_DOADO10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL10->BRAM_LOGIC_OUTS_B20_0": { + "src_wire": "BRAM_FIFO36_DOBDOL10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO3->BRAM_LOGIC_OUTS_B6_3": { + "src_wire": "BRAM_RAMB18_DOBDO3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_RAMB18_ADDRBWRADDR0": { + "src_wire": "BRAM_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_FIFO36_ADDRARDADDRU6": { + "src_wire": "BRAM_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX34_2->BRAM_FIFO36_ENBWRENL": { + "src_wire": "BRAM_IMUX34_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENBWRENL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO14->BRAM_LOGIC_OUTS_B17_1": { + "src_wire": "BRAM_FIFO18_DOBDO14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL1->>BRAM_FIFO18_ADDRBWRADDR0": { + "src_wire": "BRAM_ADDRBWRADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO11->BRAM_LOGIC_OUTS_B17_0": { + "src_wire": "BRAM_FIFO18_DOBDO11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL12->>BRAM_FIFO36_ADDRBWRADDRL12": { + "src_wire": "BRAM_ADDRBWRADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_FIFO36_ADDRARDADDRU11": { + "src_wire": "BRAM_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX46_4->BRAM_FIFO36_TSTWROS12": { + "src_wire": "BRAM_IMUX46_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX26_0->BRAM_FIFO36_DIADIL1": { + "src_wire": "BRAM_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY1->BRAM_LOGIC_OUTS_B12_3": { + "src_wire": "BRAM_FIFO36_ECCPARITY1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX22_1->BRAM_IMUX_ADDRARDADDRL11": { + "src_wire": "BRAM_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_CASCOUT_ADDRBWRADDRU13": { + "src_wire": "BRAM_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_TSTOUT0->BRAM_LOGIC_OUTS_B18_1": { + "src_wire": "BRAM_FIFO36_TSTOUT0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL11->>BRAM_FIFO18_ADDRBWRADDR10": { + "src_wire": "BRAM_ADDRBWRADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL7->BRAM_LOGIC_OUTS_B4_2": { + "src_wire": "BRAM_FIFO36_DOBDOL7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY2->BRAM_LOGIC_OUTS_B13_2": { + "src_wire": "BRAM_FIFO36_ECCPARITY2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX18_1->BRAM_IMUX_ADDRARDADDRL1": { + "src_wire": "BRAM_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL0_3->BRAM_FIFO18_RSTRAMARSTRAM": { + "src_wire": "BRAM_CTRL0_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTRAMARSTRAM", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL13->>BRAM_UTURN_ADDRBWRADDRL13": { + "src_wire": "BRAM_ADDRBWRADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX14_1->BRAM_IMUX_ADDRARDADDRU11": { + "src_wire": "BRAM_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_UTURN_ADDRARDADDRU12": { + "src_wire": "BRAM_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { + "src_wire": "BRAM_FIFO18_WRCOUNT7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_RAMB18_ADDRBWRADDR9": { + "src_wire": "BRAM_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { + "src_wire": "BRAM_FIFO36_RDCOUNT1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_FIFO36_ADDRBWRADDRU9": { + "src_wire": "BRAM_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { + "src_wire": "BRAM_FIFO36_RDCOUNT10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX22_2->BRAM_FIFO36_WEBWEL5": { + "src_wire": "BRAM_IMUX22_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX24_3->BRAM_IMUX_ADDRBWRADDRU6": { + "src_wire": "BRAM_IMUX24_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX24_2->BRAM_FIFO36_WEAU1": { + "src_wire": "BRAM_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL11->>BRAM_UTURN_ADDRBWRADDRL11": { + "src_wire": "BRAM_ADDRBWRADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX45_2->BRAM_RAMB18_WEBWE3": { + "src_wire": "BRAM_IMUX45_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU10->BRAM_LOGIC_OUTS_B19_3": { + "src_wire": "BRAM_FIFO36_DOBDOU10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL3->BRAM_LOGIC_OUTS_B15_0": { + "src_wire": "BRAM_FIFO36_DOADOL3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL3->>BRAM_UTURN_ADDRARDADDRL3": { + "src_wire": "BRAM_ADDRARDADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_CASCOUT_ADDRBWRADDRU0": { + "src_wire": "BRAM_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_CASCOUT_ADDRARDADDRU14": { + "src_wire": "BRAM_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { + "src_wire": "BRAM_FIFO18_RDCOUNT1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL4->BRAM_LOGIC_OUTS_B13_1": { + "src_wire": "BRAM_FIFO36_DOADOL4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_FIFO36_ADDRARDADDRU9": { + "src_wire": "BRAM_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL5->BRAM_LOGIC_OUTS_B6_1": { + "src_wire": "BRAM_FIFO36_DOBDOL5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX43_4->BRAM_FIFO36_TSTWROS9": { + "src_wire": "BRAM_IMUX43_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX34_1->BRAM_IMUX_ADDRBWRADDRL1": { + "src_wire": "BRAM_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO13->BRAM_LOGIC_OUTS_B5_4": { + "src_wire": "BRAM_RAMB18_DOADO13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOPADOP1->BRAM_LOGIC_OUTS_B0_1": { + "src_wire": "BRAM_FIFO18_DOPADOP1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL8->BRAM_ADDRARDADDRL8": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_WRERR->BRAM_LOGIC_OUTS_B23_2": { + "src_wire": "BRAM_FIFO18_WRERR", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOPADOPL0->BRAM_LOGIC_OUTS_B8_1": { + "src_wire": "BRAM_FIFO36_DOPADOPL0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { + "src_wire": "BRAM_FIFO18_RDCOUNT10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX30_3->BRAM_IMUX_ADDRBWRADDRU14": { + "src_wire": "BRAM_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX9_4->BRAM_RAMB18_DIADI12": { + "src_wire": "BRAM_IMUX9_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_CASCOUT_ADDRARDADDRU2": { + "src_wire": "BRAM_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX27_1->BRAM_IMUX_ADDRBWRADDRU2": { + "src_wire": "BRAM_IMUX27_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL0_1->BRAM_FIFO36_RSTRAMBL": { + "src_wire": "BRAM_CTRL0_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMBL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX3_2->BRAM_FIFO36_DIPADIPL0": { + "src_wire": "BRAM_IMUX3_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOPBDOPU1->BRAM_LOGIC_OUTS_B17_3": { + "src_wire": "BRAM_FIFO36_DOPBDOPU1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_CASCOUT_ADDRBWRADDRU7": { + "src_wire": "BRAM_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX13_4->BRAM_RAMB18_DIADI14": { + "src_wire": "BRAM_IMUX13_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX27_4->BRAM_FIFO36_TSTCNT9": { + "src_wire": "BRAM_IMUX27_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_RAMB18_ADDRARDADDR6": { + "src_wire": "BRAM_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { + "src_wire": "BRAM_FIFO36_WRCOUNT0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DBITERR->BRAM_LOGIC_OUTS_B16_2": { + "src_wire": "BRAM_FIFO36_DBITERR", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { + "src_wire": "BRAM_FIFO18_WRCOUNT8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX16_0->BRAM_FIFO36_TSTIN1": { + "src_wire": "BRAM_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX2_0->BRAM_FIFO36_TSTRDCNTOFF": { + "src_wire": "BRAM_IMUX2_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDCNTOFF", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO11->BRAM_LOGIC_OUTS_B7_0": { + "src_wire": "BRAM_FIFO18_DOADO11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX42_4->BRAM_FIFO36_TSTWROS8": { + "src_wire": "BRAM_IMUX42_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU11->BRAM_LOGIC_OUTS_B2_3": { + "src_wire": "BRAM_FIFO36_DOADOU11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX32_2->BRAM_FIFO18_WEA1": { + "src_wire": "BRAM_IMUX32_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX33_4->BRAM_FIFO36_TSTRDOS7": { + "src_wire": "BRAM_IMUX33_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FAN1_2->BRAM_FIFO36_WEBWEU4": { + "src_wire": "BRAM_FAN1_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL2->>BRAM_FIFO36_ADDRARDADDRL2": { + "src_wire": "BRAM_ADDRARDADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX21_2->BRAM_FIFO36_WEBWEL1": { + "src_wire": "BRAM_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX5_3->BRAM_FIFO36_DIBDIU3": { + "src_wire": "BRAM_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL13->>BRAM_FIFO36_ADDRARDADDRL13": { + "src_wire": "BRAM_ADDRARDADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX39_1->BRAM_IMUX_ADDRBWRADDRL13": { + "src_wire": "BRAM_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX36_4->BRAM_FIFO36_TSTRDOS10": { + "src_wire": "BRAM_IMUX36_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX16_1->BRAM_FIFO36_DIADIL0": { + "src_wire": "BRAM_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_CASCOUT_ADDRARDADDRU5": { + "src_wire": "BRAM_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX15_2->BRAM_FIFO36_DIADIU8": { + "src_wire": "BRAM_IMUX15_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { + "src_wire": "BRAM_FIFO18_RDCOUNT2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX44_1->BRAM_FIFO18_DIADI13": { + "src_wire": "BRAM_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL1_0->BRAM_FIFO36_RSTREGBU": { + "src_wire": "BRAM_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGBU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL5->>BRAM_FIFO36_ADDRBWRADDRL5": { + "src_wire": "BRAM_ADDRBWRADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX12_4->BRAM_FIFO36_DIADIU6": { + "src_wire": "BRAM_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX19_1->BRAM_IMUX_ADDRARDADDRL2": { + "src_wire": "BRAM_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX27_3->BRAM_IMUX_ADDRBWRADDRU9": { + "src_wire": "BRAM_IMUX27_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL5->>BRAM_FIFO18_ADDRBWRADDR4": { + "src_wire": "BRAM_ADDRBWRADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { + "src_wire": "BRAM_FIFO18_ALMOSTFULL", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK1_1->BRAM_FIFO36_CLKBWRCLKU": { + "src_wire": "BRAM_CLK1_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKBWRCLKU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL3->BRAM_ADDRBWRADDRL3": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX42_1->BRAM_FIFO36_DIADIL12": { + "src_wire": "BRAM_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX12_2->BRAM_IMUX_ADDRARDADDRU10": { + "src_wire": "BRAM_IMUX12_2", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO1->BRAM_LOGIC_OUTS_B4_3": { + "src_wire": "BRAM_RAMB18_DOBDO1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { + "src_wire": "BRAM_FIFO36_RDCOUNT9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO13->BRAM_LOGIC_OUTS_B2_1": { + "src_wire": "BRAM_FIFO18_DOADO13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL12->>BRAM_FIFO36_ADDRARDADDRL12": { + "src_wire": "BRAM_ADDRARDADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_UTURN_ADDRARDADDRU0": { + "src_wire": "BRAM_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU13->BRAM_LOGIC_OUTS_B19_4": { + "src_wire": "BRAM_FIFO36_DOBDOU13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX10_3->BRAM_IMUX_ADDRARDADDRU3": { + "src_wire": "BRAM_IMUX10_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL9->>BRAM_FIFO18_ADDRBWRADDR8": { + "src_wire": "BRAM_ADDRBWRADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX20_3->BRAM_IMUX_ADDRARDADDRL5": { + "src_wire": "BRAM_IMUX20_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO14->BRAM_LOGIC_OUTS_B7_1": { + "src_wire": "BRAM_FIFO18_DOADO14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX22_2->BRAM_FIFO18_WEBWE5": { + "src_wire": "BRAM_IMUX22_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX44_0->BRAM_FIFO36_TSTWROS2": { + "src_wire": "BRAM_IMUX44_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_RAMB18_ADDRBWRADDR1": { + "src_wire": "BRAM_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX4_3->BRAM_RAMB18_DIBDI10": { + "src_wire": "BRAM_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX9_1->BRAM_IMUX_ADDRARDADDRU0": { + "src_wire": "BRAM_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX26_4->BRAM_FIFO36_TSTCNT8": { + "src_wire": "BRAM_IMUX26_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL7->>BRAM_FIFO36_ADDRARDADDRL7": { + "src_wire": "BRAM_ADDRARDADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_UTURN_ADDRARDADDRU3": { + "src_wire": "BRAM_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL8->>BRAM_FIFO18_ADDRBWRADDR7": { + "src_wire": "BRAM_ADDRBWRADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU9->BRAM_LOGIC_OUTS_B22_3": { + "src_wire": "BRAM_FIFO36_DOBDOU9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOPBDOP1->BRAM_LOGIC_OUTS_B22_1": { + "src_wire": "BRAM_FIFO18_DOPBDOP1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX28_1->BRAM_IMUX_ADDRBWRADDRU8": { + "src_wire": "BRAM_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX47_0->BRAM_FIFO36_TSTWROS5": { + "src_wire": "BRAM_IMUX47_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL14->BRAM_ADDRBWRADDRL14": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_CASCOUT_ADDRARDADDRU13": { + "src_wire": "BRAM_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { + "src_wire": "BRAM_FIFO18_RDCOUNT3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL10->BRAM_LOGIC_OUTS_B2_0": { + "src_wire": "BRAM_FIFO36_DOADOL10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX22_4->BRAM_RAMB18_DIBDI7": { + "src_wire": "BRAM_IMUX22_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU10->BRAM_LOGIC_OUTS_B5_3": { + "src_wire": "BRAM_FIFO36_DOADOU10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX23_3->BRAM_FIFO36_DIPBDIPU1": { + "src_wire": "BRAM_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL6->BRAM_ADDRARDADDRL6": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_RAMB18_ADDRARDADDR1": { + "src_wire": "BRAM_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { + "src_wire": "BRAM_FIFO36_WRCOUNT9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL0_0->BRAM_FIFO18_RSTREGB": { + "src_wire": "BRAM_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTREGB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { + "src_wire": "BRAM_FIFO36_WRCOUNT3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { + "src_wire": "BRAM_FIFO36_WRCOUNT10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX8_1->BRAM_FIFO36_DIADIU0": { + "src_wire": "BRAM_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO5->BRAM_LOGIC_OUTS_B10_1": { + "src_wire": "BRAM_FIFO18_DOADO5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL13->BRAM_LOGIC_OUTS_B20_1": { + "src_wire": "BRAM_FIFO36_DOBDOL13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX37_1->BRAM_IMUX_ADDRBWRADDRL4": { + "src_wire": "BRAM_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_FIFO36_ADDRBWRADDRU4": { + "src_wire": "BRAM_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX46_2->BRAM_RAMB18_WEBWE7": { + "src_wire": "BRAM_IMUX46_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX40_4->BRAM_FIFO36_TSTWROS6": { + "src_wire": "BRAM_IMUX40_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX35_2->BRAM_FIFO18_REGCEB": { + "src_wire": "BRAM_IMUX35_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCEB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX37_4->BRAM_FIFO36_TSTRDOS11": { + "src_wire": "BRAM_IMUX37_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL11->>BRAM_FIFO36_ADDRBWRADDRL11": { + "src_wire": "BRAM_ADDRBWRADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL12->BRAM_ADDRARDADDRL12": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX36_2->BRAM_IMUX_ADDRBWRADDRL10": { + "src_wire": "BRAM_IMUX36_2", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL7->BRAM_ADDRARDADDRL7": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX45_0->BRAM_FIFO36_TSTWROS3": { + "src_wire": "BRAM_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO0->BRAM_LOGIC_OUTS_B8_0": { + "src_wire": "BRAM_FIFO18_DOADO0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX43_1->BRAM_FIFO36_DIADIL5": { + "src_wire": "BRAM_IMUX43_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX35_1->BRAM_IMUX_ADDRBWRADDRL2": { + "src_wire": "BRAM_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL1_1->BRAM_RAMB18_RSTRAMB": { + "src_wire": "BRAM_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTRAMB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX21_0->BRAM_FIFO36_TSTRDOS3": { + "src_wire": "BRAM_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL11->BRAM_ADDRARDADDRL11": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL2->>BRAM_FIFO18_ADDRARDADDR1": { + "src_wire": "BRAM_ADDRARDADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_UTURN_ADDRARDADDRL1": { + "src_wire": "BRAM_ADDRARDADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX1_2->BRAM_FIFO18_DIBDI7": { + "src_wire": "BRAM_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_TSTOUT1->BRAM_LOGIC_OUTS_B18_0": { + "src_wire": "BRAM_FIFO36_TSTOUT1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_FIFO36_ADDRARDADDRU0": { + "src_wire": "BRAM_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO4->BRAM_LOGIC_OUTS_B1_1": { + "src_wire": "BRAM_FIFO18_DOBDO4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO15->BRAM_LOGIC_OUTS_B17_4": { + "src_wire": "BRAM_RAMB18_DOBDO15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO9->BRAM_LOGIC_OUTS_B19_0": { + "src_wire": "BRAM_FIFO18_DOBDO9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX8_0->BRAM_FIFO36_TSTIN3": { + "src_wire": "BRAM_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX31_3->BRAM_IMUX_ADDRARDADDRL15": { + "src_wire": "BRAM_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL9->>BRAM_UTURN_ADDRARDADDRL9": { + "src_wire": "BRAM_ADDRARDADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX18_3->BRAM_IMUX_ADDRARDADDRL3": { + "src_wire": "BRAM_IMUX18_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL11->BRAM_ADDRBWRADDRL11": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL0->>BRAM_UTURN_ADDRBWRADDRL0": { + "src_wire": "BRAM_ADDRBWRADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU7->BRAM_LOGIC_OUTS_B3_4": { + "src_wire": "BRAM_FIFO36_DOBDOU7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_RAMB18_ADDRBWRADDR11": { + "src_wire": "BRAM_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_FIFO36_ADDRBWRADDRU14": { + "src_wire": "BRAM_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY3->BRAM_LOGIC_OUTS_B19_2": { + "src_wire": "BRAM_FIFO36_ECCPARITY3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX4_3->BRAM_FIFO36_DIBDIU10": { + "src_wire": "BRAM_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX15_3->BRAM_FIFO36_DIPADIPU1": { + "src_wire": "BRAM_IMUX15_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX16_3->BRAM_IMUX_ADDRARDADDRL6": { + "src_wire": "BRAM_IMUX16_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL0_3->BRAM_FIFO36_RSTRAMARSTRAMLRST": { + "src_wire": "BRAM_CTRL0_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMLRST", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX27_2->BRAM_FIFO36_REGCEBU": { + "src_wire": "BRAM_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEBU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX43_0->BRAM_FIFO36_TSTWROS1": { + "src_wire": "BRAM_IMUX43_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_FIFO36_ADDRARDADDRL15": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_BYP3_2->BRAM_FIFO36_WEBWEL3": { + "src_wire": "BRAM_BYP3_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO5->BRAM_LOGIC_OUTS_B6_1": { + "src_wire": "BRAM_FIFO18_DOBDO5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO10->BRAM_LOGIC_OUTS_B5_3": { + "src_wire": "BRAM_RAMB18_DOADO10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX43_3->BRAM_RAMB18_DIADI10": { + "src_wire": "BRAM_IMUX43_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL0->BRAM_LOGIC_OUTS_B4_0": { + "src_wire": "BRAM_FIFO36_DOBDOL0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { + "src_wire": "BRAM_FIFO36_WRCOUNT8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_FIFO36_ADDRARDADDRU8": { + "src_wire": "BRAM_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_RAMB18_ADDRARDADDR12": { + "src_wire": "BRAM_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_CASCADEOUTB->BRAM_FIFO36_CASCADEOUTB_1": { + "src_wire": "BRAM_FIFO36_CASCADEOUTB", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CASCADEOUTB_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_RAMB18_ADDRARDADDR13": { + "src_wire": "BRAM_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX43_1->BRAM_FIFO18_DIADI5": { + "src_wire": "BRAM_IMUX43_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDERR->BRAM_LOGIC_OUTS_B14_2": { + "src_wire": "BRAM_FIFO36_RDERR", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU12->BRAM_LOGIC_OUTS_B22_4": { + "src_wire": "BRAM_FIFO36_DOBDOU12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX11_0->BRAM_FIFO36_TSTCNT1": { + "src_wire": "BRAM_IMUX11_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO2->BRAM_LOGIC_OUTS_B10_0": { + "src_wire": "BRAM_FIFO18_DOADO2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU8->BRAM_LOGIC_OUTS_B7_2": { + "src_wire": "BRAM_FIFO36_DOADOU8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX7_1->BRAM_FIFO18_DIBDI14": { + "src_wire": "BRAM_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL11->>BRAM_FIFO36_ADDRARDADDRL11": { + "src_wire": "BRAM_ADDRARDADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX37_3->BRAM_IMUX_ADDRBWRADDRL12": { + "src_wire": "BRAM_IMUX37_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO11->BRAM_LOGIC_OUTS_B2_3": { + "src_wire": "BRAM_RAMB18_DOADO11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX36_0->BRAM_FIFO18_DIBDI2": { + "src_wire": "BRAM_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX33_2->BRAM_FIFO18_WEA3": { + "src_wire": "BRAM_IMUX33_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT12->BRAM_LOGIC_OUTS_B21_4": { + "src_wire": "BRAM_FIFO36_RDCOUNT12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX40_3->BRAM_FIFO36_DIADIU1": { + "src_wire": "BRAM_IMUX40_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX17_2->BRAM_FIFO18_WEA2": { + "src_wire": "BRAM_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FAN5_2->BRAM_RAMB18_WEBWE0": { + "src_wire": "BRAM_FAN5_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX35_4->BRAM_FIFO36_TSTRDOS9": { + "src_wire": "BRAM_IMUX35_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_RAMB18_ADDRARDADDR2": { + "src_wire": "BRAM_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_CASCOUT_ADDRARDADDRU12": { + "src_wire": "BRAM_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU8->BRAM_LOGIC_OUTS_B17_2": { + "src_wire": "BRAM_FIFO36_DOBDOU8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX2_1->BRAM_FIFO18_DIBDI4": { + "src_wire": "BRAM_IMUX2_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX19_4->BRAM_RAMB18_DIBDI13": { + "src_wire": "BRAM_IMUX19_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX27_0->BRAM_FIFO18_DIADI9": { + "src_wire": "BRAM_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL9->>BRAM_UTURN_ADDRBWRADDRL9": { + "src_wire": "BRAM_ADDRBWRADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_FIFO36_ADDRBWRADDRU2": { + "src_wire": "BRAM_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX45_3->BRAM_FIFO36_DIADIU11": { + "src_wire": "BRAM_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL0_1->BRAM_FIFO18_RSTRAMB": { + "src_wire": "BRAM_CTRL0_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTRAMB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX18_4->BRAM_RAMB18_DIBDI5": { + "src_wire": "BRAM_IMUX18_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU11->BRAM_LOGIC_OUTS_B20_3": { + "src_wire": "BRAM_FIFO36_DOBDOU11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL9->BRAM_LOGIC_OUTS_B5_0": { + "src_wire": "BRAM_FIFO36_DOADOL9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX23_4->BRAM_FIFO36_DIBDIU15": { + "src_wire": "BRAM_IMUX23_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX17_4->BRAM_FIFO36_DIBDIU12": { + "src_wire": "BRAM_IMUX17_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX8_2->BRAM_RAMB18_WEA0": { + "src_wire": "BRAM_IMUX8_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX38_2->BRAM_FIFO36_WEBWEL6": { + "src_wire": "BRAM_IMUX38_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO2->BRAM_LOGIC_OUTS_B1_3": { + "src_wire": "BRAM_RAMB18_DOBDO2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX34_4->BRAM_FIFO36_TSTRDOS8": { + "src_wire": "BRAM_IMUX34_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX7_1->BRAM_FIFO36_DIBDIL14": { + "src_wire": "BRAM_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX20_0->BRAM_FIFO36_TSTRDOS2": { + "src_wire": "BRAM_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO8->BRAM_LOGIC_OUTS_B22_0": { + "src_wire": "BRAM_FIFO18_DOBDO8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX33_2->BRAM_FIFO36_WEAL3": { + "src_wire": "BRAM_IMUX33_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { + "src_wire": "BRAM_FIFO36_RDCOUNT5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX42_2->BRAM_RAMB18_DIPADIP0": { + "src_wire": "BRAM_IMUX42_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPADIP0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO15->BRAM_LOGIC_OUTS_B22_2": { + "src_wire": "BRAM_FIFO18_DOBDO15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL10->>BRAM_UTURN_ADDRARDADDRL10": { + "src_wire": "BRAM_ADDRARDADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL3->>BRAM_UTURN_ADDRBWRADDRL3": { + "src_wire": "BRAM_ADDRBWRADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX29_2->BRAM_FIFO36_WEBWEU2": { + "src_wire": "BRAM_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX1_2->BRAM_FIFO36_DIBDIL7": { + "src_wire": "BRAM_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_UTURN_ADDRBWRADDRU6": { + "src_wire": "BRAM_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX38_1->BRAM_IMUX_ADDRBWRADDRL11": { + "src_wire": "BRAM_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { + "src_wire": "BRAM_FIFO36_RDCOUNT7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { + "src_wire": "BRAM_FIFO36_RDCOUNT2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU12->BRAM_LOGIC_OUTS_B0_4": { + "src_wire": "BRAM_FIFO36_DOADOU12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_RAMB18_ADDRATIEHIGH0": { + "src_wire": "BRAM_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO14->BRAM_LOGIC_OUTS_B2_4": { + "src_wire": "BRAM_RAMB18_DOADO14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX35_2->BRAM_FIFO36_REGCEBL": { + "src_wire": "BRAM_IMUX35_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEBL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL9->BRAM_LOGIC_OUTS_B19_0": { + "src_wire": "BRAM_FIFO36_DOBDOL9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_RAMB18_ADDRARDADDR5": { + "src_wire": "BRAM_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { + "src_wire": "BRAM_FIFO36_RDCOUNT6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX13_0->BRAM_FIFO36_TSTCNT3": { + "src_wire": "BRAM_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO4->BRAM_LOGIC_OUTS_B4_4": { + "src_wire": "BRAM_RAMB18_DOBDO4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU9->BRAM_LOGIC_OUTS_B0_3": { + "src_wire": "BRAM_FIFO36_DOADOU9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX43_2->BRAM_FIFO36_DIPBDIPU0": { + "src_wire": "BRAM_IMUX43_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU15->BRAM_LOGIC_OUTS_B7_4": { + "src_wire": "BRAM_FIFO36_DOADOU15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_UTURN_ADDRBWRADDRU13": { + "src_wire": "BRAM_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO7->BRAM_LOGIC_OUTS_B15_4": { + "src_wire": "BRAM_RAMB18_DOADO7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { + "src_wire": "BRAM_FIFO18_RDCOUNT6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOPADOPU1->BRAM_LOGIC_OUTS_B7_3": { + "src_wire": "BRAM_FIFO36_DOPADOPU1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX11_4->BRAM_RAMB18_DIADI13": { + "src_wire": "BRAM_IMUX11_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_CASCOUT_ADDRBWRADDRU2": { + "src_wire": "BRAM_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX46_0->BRAM_FIFO36_TSTWROS4": { + "src_wire": "BRAM_IMUX46_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX4_0->BRAM_FIFO36_TSTOFF": { + "src_wire": "BRAM_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTOFF", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL2->BRAM_LOGIC_OUTS_B6_0": { + "src_wire": "BRAM_FIFO36_DOBDOL2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX5_4->BRAM_FIFO36_TSTIN0": { + "src_wire": "BRAM_IMUX5_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK1_4->BRAM_FIFO36_REGCLKARDRCLKU": { + "src_wire": "BRAM_CLK1_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO12->BRAM_LOGIC_OUTS_B5_1": { + "src_wire": "BRAM_FIFO18_DOADO12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX42_3->BRAM_FIFO36_DIADIU2": { + "src_wire": "BRAM_IMUX42_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX12_4->BRAM_RAMB18_DIADI6": { + "src_wire": "BRAM_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU6->BRAM_LOGIC_OUTS_B10_4": { + "src_wire": "BRAM_FIFO36_DOADOU6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX9_2->BRAM_FIFO36_WEAU2": { + "src_wire": "BRAM_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL0->BRAM_ADDRBWRADDRL0": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX22_3->BRAM_IMUX_ADDRARDADDRL14": { + "src_wire": "BRAM_IMUX22_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX14_2->BRAM_RAMB18_WEBWE5": { + "src_wire": "BRAM_IMUX14_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL7->>BRAM_FIFO36_ADDRBWRADDRL7": { + "src_wire": "BRAM_ADDRBWRADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX36_1->BRAM_IMUX_ADDRBWRADDRL8": { + "src_wire": "BRAM_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_CASCOUT_ADDRBWRADDRU8": { + "src_wire": "BRAM_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX39_0->BRAM_FIFO18_DIBDI11": { + "src_wire": "BRAM_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL1->>BRAM_UTURN_ADDRBWRADDRL1": { + "src_wire": "BRAM_ADDRBWRADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX6_3->BRAM_RAMB18_DIBDI11": { + "src_wire": "BRAM_IMUX6_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL2->>BRAM_UTURN_ADDRARDADDRL2": { + "src_wire": "BRAM_ADDRARDADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX20_2->BRAM_IMUX_ADDRARDADDRL10": { + "src_wire": "BRAM_IMUX20_2", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX41_3->BRAM_FIFO36_DIADIU9": { + "src_wire": "BRAM_IMUX41_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL14->>BRAM_FIFO18_ADDRBWRADDR13": { + "src_wire": "BRAM_ADDRBWRADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO11->BRAM_LOGIC_OUTS_B20_3": { + "src_wire": "BRAM_RAMB18_DOBDO11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX27_0->BRAM_FIFO36_DIADIL9": { + "src_wire": "BRAM_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX31_0->BRAM_FIFO18_DIADI11": { + "src_wire": "BRAM_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX26_2->BRAM_RAMB18_ENBWREN": { + "src_wire": "BRAM_IMUX26_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ENBWREN", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX2_3->BRAM_FIFO36_DIBDIU9": { + "src_wire": "BRAM_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_RAMB18_ADDRBWRADDR7": { + "src_wire": "BRAM_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX30_2->BRAM_RAMB18_WEBWE6": { + "src_wire": "BRAM_IMUX30_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_UTURN_ADDRARDADDRU4": { + "src_wire": "BRAM_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX21_4->BRAM_FIFO36_DIBDIU14": { + "src_wire": "BRAM_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX6_3->BRAM_FIFO36_DIBDIU11": { + "src_wire": "BRAM_IMUX6_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL1->BRAM_ADDRBWRADDRL1": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_FIFO18_ADDRARDADDR0": { + "src_wire": "BRAM_ADDRARDADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX6_1->BRAM_FIFO18_DIBDI6": { + "src_wire": "BRAM_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL15->BRAM_LOGIC_OUTS_B0_2": { + "src_wire": "BRAM_FIFO36_DOADOL15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL0->BRAM_ADDRARDADDRL0": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX17_4->BRAM_RAMB18_DIBDI12": { + "src_wire": "BRAM_IMUX17_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_UTURN_ADDRBWRADDRU10": { + "src_wire": "BRAM_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_RAMB18_ADDRBWRADDR6": { + "src_wire": "BRAM_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX32_3->BRAM_IMUX_ADDRBWRADDRL6": { + "src_wire": "BRAM_IMUX32_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX19_2->BRAM_FIFO18_REGCEAREGCE": { + "src_wire": "BRAM_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCEAREGCE", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX20_1->BRAM_IMUX_ADDRARDADDRL8": { + "src_wire": "BRAM_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_FIFO36_ADDRBWRADDRU11": { + "src_wire": "BRAM_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL6->>BRAM_UTURN_ADDRARDADDRL6": { + "src_wire": "BRAM_ADDRARDADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU2->BRAM_LOGIC_OUTS_B1_3": { + "src_wire": "BRAM_FIFO36_DOBDOU2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_FIFO36_ADDRBWRADDRU5": { + "src_wire": "BRAM_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX45_4->BRAM_FIFO36_TSTWROS11": { + "src_wire": "BRAM_IMUX45_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { + "src_wire": "BRAM_FIFO36_ALMOSTFULL", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX42_2->BRAM_FIFO36_DIPADIPU0": { + "src_wire": "BRAM_IMUX42_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL3->>BRAM_FIFO18_ADDRARDADDR2": { + "src_wire": "BRAM_ADDRARDADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU5->BRAM_LOGIC_OUTS_B1_4": { + "src_wire": "BRAM_FIFO36_DOBDOU5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_UTURN_ADDRARDADDRU8": { + "src_wire": "BRAM_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_CASCOUT_ADDRBWRADDRU11": { + "src_wire": "BRAM_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX11_2->BRAM_FIFO36_REGCEAREGCEU": { + "src_wire": "BRAM_IMUX11_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEAREGCEU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX39_3->BRAM_IMUX_ADDRBWRADDRL15": { + "src_wire": "BRAM_IMUX39_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL13->BRAM_ADDRARDADDRL13": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { + "src_wire": "BRAM_FIFO18_RDCOUNT7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO1->BRAM_LOGIC_OUTS_B8_3": { + "src_wire": "BRAM_RAMB18_DOADO1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL6->BRAM_LOGIC_OUTS_B15_1": { + "src_wire": "BRAM_FIFO36_DOADOL6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_CASCADEOUTA->BRAM_FIFO36_CASCADEOUTA_1": { + "src_wire": "BRAM_FIFO36_CASCADEOUTA", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CASCADEOUTA_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX5_2->BRAM_FIFO18_WEBWE0": { + "src_wire": "BRAM_IMUX5_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_FULL->BRAM_LOGIC_OUTS_B5_2": { + "src_wire": "BRAM_FIFO36_FULL", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL4->>BRAM_FIFO36_ADDRARDADDRL4": { + "src_wire": "BRAM_ADDRARDADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL10->BRAM_ADDRARDADDRL10": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX28_2->BRAM_IMUX_ADDRBWRADDRU10": { + "src_wire": "BRAM_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL13->BRAM_LOGIC_OUTS_B2_1": { + "src_wire": "BRAM_FIFO36_DOADOL13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { + "src_wire": "BRAM_FIFO18_RDCOUNT8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_FIFO36_ADDRARDADDRU2": { + "src_wire": "BRAM_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX22_4->BRAM_FIFO36_DIBDIU7": { + "src_wire": "BRAM_IMUX22_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX40_2->BRAM_FIFO18_DIADI7": { + "src_wire": "BRAM_IMUX40_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL2->BRAM_ADDRBWRADDRL2": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL3->>BRAM_FIFO36_ADDRARDADDRL3": { + "src_wire": "BRAM_ADDRARDADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOPADOPU0->BRAM_LOGIC_OUTS_B15_3": { + "src_wire": "BRAM_FIFO36_DOPADOPU0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU0->BRAM_LOGIC_OUTS_B15_2": { + "src_wire": "BRAM_FIFO36_DOADOU0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX25_4->BRAM_FIFO36_TSTCNT7": { + "src_wire": "BRAM_IMUX25_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_TSTOUT4->BRAM_LOGIC_OUTS_B11_0": { + "src_wire": "BRAM_FIFO36_TSTOUT4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL9->BRAM_ADDRARDADDRL9": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX23_3->BRAM_RAMB18_DIPBDIP1": { + "src_wire": "BRAM_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPBDIP1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX18_4->BRAM_FIFO36_DIBDIU5": { + "src_wire": "BRAM_IMUX18_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX18_2->BRAM_FIFO36_ENARDENL": { + "src_wire": "BRAM_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENARDENL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX13_1->BRAM_IMUX_ADDRARDADDRU4": { + "src_wire": "BRAM_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL10->>BRAM_FIFO18_ADDRARDADDR9": { + "src_wire": "BRAM_ADDRARDADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX5_1->BRAM_FIFO36_DIBDIL13": { + "src_wire": "BRAM_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX2_3->BRAM_RAMB18_DIBDI9": { + "src_wire": "BRAM_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL12->>BRAM_FIFO18_ADDRARDADDR11": { + "src_wire": "BRAM_ADDRARDADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL1_4->BRAM_FIFO36_RSTREGARSTREGU": { + "src_wire": "BRAM_CTRL1_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGARSTREGU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL6->>BRAM_UTURN_ADDRBWRADDRL6": { + "src_wire": "BRAM_ADDRBWRADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX8_3->BRAM_IMUX_ADDRARDADDRU6": { + "src_wire": "BRAM_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_RAMB18_ADDRBTIEHIGH1": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY6->BRAM_LOGIC_OUTS_B21_3": { + "src_wire": "BRAM_FIFO36_ECCPARITY6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL10->>BRAM_FIFO18_ADDRBWRADDR9": { + "src_wire": "BRAM_ADDRBWRADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL11->>BRAM_FIFO18_ADDRARDADDR10": { + "src_wire": "BRAM_ADDRARDADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO12->BRAM_LOGIC_OUTS_B22_4": { + "src_wire": "BRAM_RAMB18_DOBDO12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_FIFO36_ADDRARDADDRU13": { + "src_wire": "BRAM_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_FIFO36_ADDRBWRADDRU12": { + "src_wire": "BRAM_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX23_4->BRAM_RAMB18_DIBDI15": { + "src_wire": "BRAM_IMUX23_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CTRL1_4->BRAM_RAMB18_RSTREGARSTREG": { + "src_wire": "BRAM_CTRL1_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTREGARSTREG", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO9->BRAM_LOGIC_OUTS_B5_0": { + "src_wire": "BRAM_FIFO18_DOADO9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX12_1->BRAM_IMUX_ADDRARDADDRU8": { + "src_wire": "BRAM_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { + "src_wire": "BRAM_FIFO36_RDCOUNT11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL12->BRAM_LOGIC_OUTS_B5_1": { + "src_wire": "BRAM_FIFO36_DOADOL12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_UTURN_ADDRBWRADDRL15": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { + "src_wire": "BRAM_FIFO18_RDCOUNT4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX28_0->BRAM_FIFO36_DIADIL2": { + "src_wire": "BRAM_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO0->BRAM_LOGIC_OUTS_B15_2": { + "src_wire": "BRAM_RAMB18_DOADO0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX4_2->BRAM_FIFO18_DIPBDIP0": { + "src_wire": "BRAM_IMUX4_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPBDIP0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX41_1->BRAM_FIFO36_DIADIL4": { + "src_wire": "BRAM_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX44_1->BRAM_FIFO36_DIADIL13": { + "src_wire": "BRAM_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX23_2->BRAM_RAMB18_DIBDI8": { + "src_wire": "BRAM_IMUX23_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX28_4->BRAM_FIFO36_TSTCNT10": { + "src_wire": "BRAM_IMUX28_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX42_0->BRAM_FIFO36_TSTWROS0": { + "src_wire": "BRAM_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_UTURN_ADDRBWRADDRU11": { + "src_wire": "BRAM_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX41_1->BRAM_FIFO18_DIADI4": { + "src_wire": "BRAM_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL4->>BRAM_UTURN_ADDRARDADDRL4": { + "src_wire": "BRAM_ADDRARDADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL1->BRAM_ADDRARDADDRL1": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX33_0->BRAM_FIFO18_DIBDI8": { + "src_wire": "BRAM_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO7->BRAM_LOGIC_OUTS_B8_2": { + "src_wire": "BRAM_FIFO18_DOADO7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL0->>BRAM_FIFO18_ADDRBTIEHIGH0": { + "src_wire": "BRAM_ADDRBWRADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX37_2->BRAM_FIFO18_WEBWE2": { + "src_wire": "BRAM_IMUX37_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU15->BRAM_LOGIC_OUTS_B17_4": { + "src_wire": "BRAM_FIFO36_DOBDOU15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_CASCOUT_ADDRARDADDRU4": { + "src_wire": "BRAM_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX14_2->BRAM_FIFO36_WEBWEU5": { + "src_wire": "BRAM_IMUX14_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX8_2->BRAM_FIFO36_WEAU0": { + "src_wire": "BRAM_IMUX8_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_RDERR->BRAM_LOGIC_OUTS_B14_2": { + "src_wire": "BRAM_FIFO18_RDERR", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL3->BRAM_ADDRARDADDRL3": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO7->BRAM_LOGIC_OUTS_B4_2": { + "src_wire": "BRAM_FIFO18_DOBDO7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL11->BRAM_LOGIC_OUTS_B17_0": { + "src_wire": "BRAM_FIFO36_DOBDOL11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_UTURN_ADDRARDADDRU1": { + "src_wire": "BRAM_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL7->BRAM_LOGIC_OUTS_B8_2": { + "src_wire": "BRAM_FIFO36_DOADOL7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX26_3->BRAM_IMUX_ADDRBWRADDRU3": { + "src_wire": "BRAM_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_UTURN_ADDRBWRADDRU8": { + "src_wire": "BRAM_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL9->>BRAM_FIFO36_ADDRBWRADDRL9": { + "src_wire": "BRAM_ADDRBWRADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX2_2->BRAM_FIFO18_DIBDI15": { + "src_wire": "BRAM_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX25_2->BRAM_FIFO36_WEAU3": { + "src_wire": "BRAM_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { + "src_wire": "BRAM_FIFO18_WRCOUNT9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX11_1->BRAM_IMUX_ADDRARDADDRU2": { + "src_wire": "BRAM_IMUX11_1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_BYP6_2->BRAM_FIFO36_WEBWEL7": { + "src_wire": "BRAM_BYP6_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FAN5_2->BRAM_FIFO36_WEBWEU0": { + "src_wire": "BRAM_FAN5_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU1->BRAM_LOGIC_OUTS_B4_3": { + "src_wire": "BRAM_FIFO36_DOBDOU1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX46_2->BRAM_FIFO36_WEBWEU7": { + "src_wire": "BRAM_IMUX46_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX15_2->BRAM_RAMB18_DIADI8": { + "src_wire": "BRAM_IMUX15_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX16_4->BRAM_RAMB18_DIBDI4": { + "src_wire": "BRAM_IMUX16_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL11->BRAM_LOGIC_OUTS_B7_0": { + "src_wire": "BRAM_FIFO36_DOADOL11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_TSTOUT2->BRAM_LOGIC_OUTS_B11_4": { + "src_wire": "BRAM_FIFO36_TSTOUT2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_UTURN_ADDRARDADDRU9": { + "src_wire": "BRAM_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO14->BRAM_LOGIC_OUTS_B20_4": { + "src_wire": "BRAM_RAMB18_DOBDO14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX11_2->BRAM_RAMB18_REGCEAREGCE": { + "src_wire": "BRAM_IMUX11_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCEAREGCE", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { + "src_wire": "BRAM_FIFO36_WRCOUNT4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_FIFO18_ADDRATIEHIGH1": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOPADOP1->BRAM_LOGIC_OUTS_B7_3": { + "src_wire": "BRAM_RAMB18_DOPADOP1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX41_2->BRAM_FIFO18_DIADI15": { + "src_wire": "BRAM_IMUX41_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX2_2->BRAM_FIFO36_DIBDIL15": { + "src_wire": "BRAM_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { + "src_wire": "BRAM_FIFO18_WRCOUNT11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX41_3->BRAM_RAMB18_DIADI9": { + "src_wire": "BRAM_IMUX41_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK1_0->BRAM_FIFO36_REGCLKBU": { + "src_wire": "BRAM_CLK1_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKBU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX2_1->BRAM_FIFO36_DIBDIL4": { + "src_wire": "BRAM_IMUX2_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO4->BRAM_LOGIC_OUTS_B8_4": { + "src_wire": "BRAM_RAMB18_DOADO4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX10_4->BRAM_RAMB18_DIADI5": { + "src_wire": "BRAM_IMUX10_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX38_2->BRAM_FIFO18_WEBWE6": { + "src_wire": "BRAM_IMUX38_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX37_2->BRAM_FIFO36_WEBWEL2": { + "src_wire": "BRAM_IMUX37_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX16_4->BRAM_FIFO36_DIBDIU4": { + "src_wire": "BRAM_IMUX16_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL9->>BRAM_FIFO18_ADDRARDADDR8": { + "src_wire": "BRAM_ADDRARDADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX38_0->BRAM_FIFO18_DIBDI3": { + "src_wire": "BRAM_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO9->BRAM_LOGIC_OUTS_B0_3": { + "src_wire": "BRAM_RAMB18_DOADO9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO2->BRAM_LOGIC_OUTS_B6_0": { + "src_wire": "BRAM_FIFO18_DOBDO2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL5->>BRAM_UTURN_ADDRBWRADDRL5": { + "src_wire": "BRAM_ADDRBWRADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX43_2->BRAM_RAMB18_DIPBDIP0": { + "src_wire": "BRAM_IMUX43_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPBDIP0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL5->BRAM_ADDRBWRADDRL5": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX19_3->BRAM_IMUX_ADDRARDADDRL9": { + "src_wire": "BRAM_IMUX19_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_RAMB18_ADDRBWRADDR4": { + "src_wire": "BRAM_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK0_0->BRAM_FIFO18_REGCLKB": { + "src_wire": "BRAM_CLK0_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX15_3->BRAM_RAMB18_DIPADIP1": { + "src_wire": "BRAM_IMUX15_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPADIP1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX20_4->BRAM_RAMB18_DIBDI6": { + "src_wire": "BRAM_IMUX20_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_UTURN_ADDRBWRADDRU2": { + "src_wire": "BRAM_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_FIFO18_DOADO4->BRAM_LOGIC_OUTS_B13_1": { + "src_wire": "BRAM_FIFO18_DOADO4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CLK0_1->BRAM_FIFO36_CLKBWRCLKL": { + "src_wire": "BRAM_CLK0_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKBWRCLKL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX14_4->BRAM_FIFO36_DIADIU7": { + "src_wire": "BRAM_IMUX14_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL14->>BRAM_UTURN_ADDRBWRADDRL14": { + "src_wire": "BRAM_ADDRBWRADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX35_0->BRAM_FIFO36_DIBDIL9": { + "src_wire": "BRAM_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO5->BRAM_LOGIC_OUTS_B13_4": { + "src_wire": "BRAM_RAMB18_DOADO5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX0_0->BRAM_FIFO36_TSTBRAMRST": { + "src_wire": "BRAM_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTBRAMRST", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX43_3->BRAM_FIFO36_DIADIU10": { + "src_wire": "BRAM_IMUX43_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOBDO8->BRAM_LOGIC_OUTS_B17_2": { + "src_wire": "BRAM_RAMB18_DOBDO8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX24_1->BRAM_RAMB18_DIBDI0": { + "src_wire": "BRAM_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_UTURN_ADDRARDADDRU2": { + "src_wire": "BRAM_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX3_3->BRAM_RAMB18_DIBDI2": { + "src_wire": "BRAM_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX13_2->BRAM_RAMB18_WEBWE1": { + "src_wire": "BRAM_IMUX13_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX8_1->BRAM_RAMB18_DIADI0": { + "src_wire": "BRAM_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO15->BRAM_LOGIC_OUTS_B7_4": { + "src_wire": "BRAM_RAMB18_DOADO15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_FIFO36_ADDRARDADDRU3": { + "src_wire": "BRAM_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX9_2->BRAM_RAMB18_WEA2": { + "src_wire": "BRAM_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX35_0->BRAM_FIFO18_DIBDI9": { + "src_wire": "BRAM_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOPADOP0->BRAM_LOGIC_OUTS_B15_3": { + "src_wire": "BRAM_RAMB18_DOPADOP0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX6_1->BRAM_FIFO36_DIBDIL6": { + "src_wire": "BRAM_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL1->>BRAM_FIFO36_ADDRBWRADDRL1": { + "src_wire": "BRAM_ADDRBWRADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_RAMB18_DOADO3->BRAM_LOGIC_OUTS_B10_3": { + "src_wire": "BRAM_RAMB18_DOADO3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL7->>BRAM_UTURN_ADDRARDADDRL7": { + "src_wire": "BRAM_ADDRARDADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX29_0->BRAM_FIFO18_DIADI10": { + "src_wire": "BRAM_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX17_3->BRAM_IMUX_ADDRARDADDRL7": { + "src_wire": "BRAM_IMUX17_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX29_4->BRAM_FIFO36_TSTCNT11": { + "src_wire": "BRAM_IMUX29_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX40_1->BRAM_FIFO36_DIPADIPL1": { + "src_wire": "BRAM_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_IMUX30_0->BRAM_FIFO36_DIADIL3": { + "src_wire": "BRAM_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_L.BRAM_ADDRARDADDRL10->>BRAM_FIFO36_ADDRARDADDRL10": { + "src_wire": "BRAM_ADDRARDADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL10", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_BRAM_R.json b/kintex7/tile_type_BRAM_R.json new file mode 100644 index 0000000..20ff7ff --- /dev/null +++ b/kintex7/tile_type_BRAM_R.json @@ -0,0 +1,9834 @@ +{ + "tile_type": "BRAM_R", + "sites": [ + { + "y_coord": 39, + "name": "X0Y39", + "prefix": "RAMB18", + "type": "FIFO18E1", + "site_pins": { + "WREN": "BRAM_FIFO18_ENBWREN", + "REGCEB": "BRAM_FIFO18_REGCEB", + "DIADI7": "BRAM_FIFO18_DIADI7", + "ADDRBTIEHIGH0": "BRAM_FIFO18_ADDRBTIEHIGH0", + "RDCOUNT2": "BRAM_FIFO18_RDCOUNT2", + "WRCOUNT3": "BRAM_FIFO18_WRCOUNT3", + "WRCLK": "BRAM_FIFO18_CLKBWRCLK", + "DO2": "BRAM_FIFO18_DOADO2", + "DIBDI3": "BRAM_FIFO18_DIBDI3", + "RDCOUNT0": "BRAM_FIFO18_RDCOUNT0", + "ADDRBWRADDR10": "BRAM_FIFO18_ADDRBWRADDR10", + "DIBDI1": "BRAM_FIFO18_DIBDI1", + "ADDRARDADDR8": "BRAM_FIFO18_ADDRARDADDR8", + "WEBWE5": "BRAM_FIFO18_WEBWE5", + "ADDRBWRADDR13": "BRAM_FIFO18_ADDRBWRADDR13", + "RSTREGB": "BRAM_FIFO18_RSTREGB", + "WRERR": "BRAM_FIFO18_WRERR", + "ALMOSTFULL": "BRAM_FIFO18_ALMOSTFULL", + "RDCOUNT8": "BRAM_FIFO18_RDCOUNT8", + "DO8": "BRAM_FIFO18_DOADO8", + "RDCOUNT7": "BRAM_FIFO18_RDCOUNT7", + "RDCOUNT5": "BRAM_FIFO18_RDCOUNT5", + "ADDRBTIEHIGH1": "BRAM_FIFO18_ADDRBTIEHIGH1", + "WRCOUNT9": "BRAM_FIFO18_WRCOUNT9", + "ADDRBWRADDR5": "BRAM_FIFO18_ADDRBWRADDR5", + "ADDRBWRADDR3": "BRAM_FIFO18_ADDRBWRADDR3", + "DIBDI0": "BRAM_FIFO18_DIBDI0", + "ADDRARDADDR6": "BRAM_FIFO18_ADDRARDADDR6", + "DO23": "BRAM_FIFO18_DOBDO7", + "REGCLKB": "BRAM_FIFO18_REGCLKB", + "RDCOUNT11": "BRAM_FIFO18_RDCOUNT11", + "DIBDI9": "BRAM_FIFO18_DIBDI9", + "DO29": "BRAM_FIFO18_DOBDO13", + "ADDRARDADDR13": "BRAM_FIFO18_ADDRARDADDR13", + "RSTREG": "BRAM_FIFO18_RSTREGARSTREG", + "RDCOUNT9": "BRAM_FIFO18_RDCOUNT9", + "WEA1": "BRAM_FIFO18_WEA1", + "DO9": "BRAM_FIFO18_DOADO9", + "ADDRBWRADDR6": "BRAM_FIFO18_ADDRBWRADDR6", + "RDRCLK": "BRAM_FIFO18_REGCLKARDRCLK", + "DO15": "BRAM_FIFO18_DOADO15", + "DIADI6": "BRAM_FIFO18_DIADI6", + "RDCOUNT4": "BRAM_FIFO18_RDCOUNT4", + "WEBWE4": "BRAM_FIFO18_WEBWE4", + "DIBDI6": "BRAM_FIFO18_DIBDI6", + "WRCOUNT8": "BRAM_FIFO18_WRCOUNT8", + "DIBDI11": "BRAM_FIFO18_DIBDI11", + "ADDRBWRADDR8": "BRAM_FIFO18_ADDRBWRADDR8", + "DIADI3": "BRAM_FIFO18_DIADI3", + "DIADI5": "BRAM_FIFO18_DIADI5", + "DIBDI2": "BRAM_FIFO18_DIBDI2", + "ADDRARDADDR1": "BRAM_FIFO18_ADDRARDADDR1", + "DIBDI12": "BRAM_FIFO18_DIBDI12", + "ADDRARDADDR5": "BRAM_FIFO18_ADDRARDADDR5", + "RDEN": "BRAM_FIFO18_ENARDEN", + "WEBWE6": "BRAM_FIFO18_WEBWE6", + "DIPBDIP1": "BRAM_FIFO18_DIPBDIP1", + "ADDRBWRADDR0": "BRAM_FIFO18_ADDRBWRADDR0", + "RDCOUNT6": "BRAM_FIFO18_RDCOUNT6", + "ADDRBWRADDR12": "BRAM_FIFO18_ADDRBWRADDR12", + "DO27": "BRAM_FIFO18_DOBDO11", + "DO25": "BRAM_FIFO18_DOBDO9", + "ADDRBWRADDR11": "BRAM_FIFO18_ADDRBWRADDR11", + "DO26": "BRAM_FIFO18_DOBDO10", + "WEBWE3": "BRAM_FIFO18_WEBWE3", + "ADDRBWRADDR4": "BRAM_FIFO18_ADDRBWRADDR4", + "WRCOUNT7": "BRAM_FIFO18_WRCOUNT7", + "WRCOUNT1": "BRAM_FIFO18_WRCOUNT1", + "DIPADIP0": "BRAM_FIFO18_DIPADIP0", + "DIADI2": "BRAM_FIFO18_DIADI2", + "ADDRARDADDR2": "BRAM_FIFO18_ADDRARDADDR2", + "ADDRBWRADDR7": "BRAM_FIFO18_ADDRBWRADDR7", + "DIBDI5": "BRAM_FIFO18_DIBDI5", + "DO10": "BRAM_FIFO18_DOADO10", + "DIADI8": "BRAM_FIFO18_DIADI8", + "DO16": "BRAM_FIFO18_DOBDO0", + "DIADI13": "BRAM_FIFO18_DIADI13", + "ADDRARDADDR4": "BRAM_FIFO18_ADDRARDADDR4", + "DO11": "BRAM_FIFO18_DOADO11", + "DO0": "BRAM_FIFO18_DOADO0", + "DO18": "BRAM_FIFO18_DOBDO2", + "DIADI14": "BRAM_FIFO18_DIADI14", + "ADDRBWRADDR2": "BRAM_FIFO18_ADDRBWRADDR2", + "ADDRARDADDR10": "BRAM_FIFO18_ADDRARDADDR10", + "DOP3": "BRAM_FIFO18_DOPBDOP1", + "ADDRARDADDR9": "BRAM_FIFO18_ADDRARDADDR9", + "RDERR": "BRAM_FIFO18_RDERR", + "DO6": "BRAM_FIFO18_DOADO6", + "FULL": "BRAM_FIFO18_FULL", + "DO24": "BRAM_FIFO18_DOBDO8", + "DIBDI10": "BRAM_FIFO18_DIBDI10", + "DIBDI7": "BRAM_FIFO18_DIBDI7", + "WEA3": "BRAM_FIFO18_WEA3", + "DIADI0": "BRAM_FIFO18_DIADI0", + "DO20": "BRAM_FIFO18_DOBDO4", + "WEBWE1": "BRAM_FIFO18_WEBWE1", + "ADDRBWRADDR9": "BRAM_FIFO18_ADDRBWRADDR9", + "ADDRBWRADDR1": "BRAM_FIFO18_ADDRBWRADDR1", + "DO21": "BRAM_FIFO18_DOBDO5", + "DIADI10": "BRAM_FIFO18_DIADI10", + "DO14": "BRAM_FIFO18_DOADO14", + "DO12": "BRAM_FIFO18_DOADO12", + "DO22": "BRAM_FIFO18_DOBDO6", + "DIADI12": "BRAM_FIFO18_DIADI12", + "DO17": "BRAM_FIFO18_DOBDO1", + "DO13": "BRAM_FIFO18_DOADO13", + "DO19": "BRAM_FIFO18_DOBDO3", + "DOP1": "BRAM_FIFO18_DOPADOP1", + "DIBDI14": "BRAM_FIFO18_DIBDI14", + "DIBDI8": "BRAM_FIFO18_DIBDI8", + "DOP2": "BRAM_FIFO18_DOPBDOP0", + "RDCOUNT3": "BRAM_FIFO18_RDCOUNT3", + "RDCLK": "BRAM_FIFO18_CLKARDCLK", + "WEBWE2": "BRAM_FIFO18_WEBWE2", + "RDCOUNT10": "BRAM_FIFO18_RDCOUNT10", + "DOP0": "BRAM_FIFO18_DOPADOP0", + "WRCOUNT5": "BRAM_FIFO18_WRCOUNT5", + "ADDRATIEHIGH1": "BRAM_FIFO18_ADDRATIEHIGH1", + "DIPADIP1": "BRAM_FIFO18_DIPADIP1", + "DIBDI4": "BRAM_FIFO18_DIBDI4", + "ALMOSTEMPTY": "BRAM_FIFO18_ALMOSTEMPTY", + "WRCOUNT2": "BRAM_FIFO18_WRCOUNT2", + "DIADI11": "BRAM_FIFO18_DIADI11", + "ADDRARDADDR3": "BRAM_FIFO18_ADDRARDADDR3", + "WRCOUNT11": "BRAM_FIFO18_WRCOUNT11", + "DO1": "BRAM_FIFO18_DOADO1", + "ADDRARDADDR12": "BRAM_FIFO18_ADDRARDADDR12", + "WEBWE0": "BRAM_FIFO18_WEBWE0", + "ADDRARDADDR7": "BRAM_FIFO18_ADDRARDADDR7", + "DO31": "BRAM_FIFO18_DOBDO15", + "DO5": "BRAM_FIFO18_DOADO5", + "ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0", + "RDCOUNT1": "BRAM_FIFO18_RDCOUNT1", + "RST": "BRAM_FIFO18_RSTRAMARSTRAM", + "WEBWE7": "BRAM_FIFO18_WEBWE7", + "ADDRARDADDR11": "BRAM_FIFO18_ADDRARDADDR11", + "WEA0": "BRAM_FIFO18_WEA0", + "DIADI9": "BRAM_FIFO18_DIADI9", + "REGCE": "BRAM_FIFO18_REGCEAREGCE", + "DIBDI15": "BRAM_FIFO18_DIBDI15", + "DO4": "BRAM_FIFO18_DOADO4", + "RSTRAMB": "BRAM_FIFO18_RSTRAMB", + "DO7": "BRAM_FIFO18_DOADO7", + "WRCOUNT10": "BRAM_FIFO18_WRCOUNT10", + "DIBDI13": "BRAM_FIFO18_DIBDI13", + "DIADI4": "BRAM_FIFO18_DIADI4", + "DO3": "BRAM_FIFO18_DOADO3", + "DIADI1": "BRAM_FIFO18_DIADI1", + "WEA2": "BRAM_FIFO18_WEA2", + "DO30": "BRAM_FIFO18_DOBDO14", + "WRCOUNT4": "BRAM_FIFO18_WRCOUNT4", + "EMPTY": "BRAM_FIFO18_EMPTY", + "WRCOUNT6": "BRAM_FIFO18_WRCOUNT6", + "WRCOUNT0": "BRAM_FIFO18_WRCOUNT0", + "DIADI15": "BRAM_FIFO18_DIADI15", + "DIPBDIP0": "BRAM_FIFO18_DIPBDIP0", + "ADDRATIEHIGH0": "BRAM_FIFO18_ADDRATIEHIGH0", + "DO28": "BRAM_FIFO18_DOBDO12" + }, + "x_coord": 0 + }, + { + "y_coord": 40, + "name": "X0Y40", + "prefix": "RAMB18", + "type": "RAMB18E1", + "site_pins": { + "DOADO5": "BRAM_RAMB18_DOADO5", + "REGCEB": "BRAM_RAMB18_REGCEB", + "ADDRATIEHIGH0": "BRAM_RAMB18_ADDRATIEHIGH0", + "ADDRARDADDR11": "BRAM_RAMB18_ADDRARDADDR11", + "DIADI14": "BRAM_RAMB18_DIADI14", + "DOBDO10": "BRAM_RAMB18_DOBDO10", + "ADDRBTIEHIGH0": "BRAM_RAMB18_ADDRBTIEHIGH0", + "RDCOUNT2": "BRAM_RAMB18_RDCOUNT2", + "WRCOUNT3": "BRAM_RAMB18_WRCOUNT3", + "WEA2": "BRAM_RAMB18_WEA2", + "DIBDI3": "BRAM_RAMB18_DIBDI3", + "DOADO3": "BRAM_RAMB18_DOADO3", + "DOADO15": "BRAM_RAMB18_DOADO15", + "DIADI6": "BRAM_RAMB18_DIADI6", + "ADDRBWRADDR10": "BRAM_RAMB18_ADDRBWRADDR10", + "DOADO8": "BRAM_RAMB18_DOADO8", + "DOBDO15": "BRAM_RAMB18_DOBDO15", + "ADDRARDADDR8": "BRAM_RAMB18_ADDRARDADDR8", + "WEBWE5": "BRAM_RAMB18_WEBWE5", + "DIBDI0": "BRAM_RAMB18_DIBDI0", + "DOADO6": "BRAM_RAMB18_DOADO6", + "ADDRBWRADDR13": "BRAM_RAMB18_ADDRBWRADDR13", + "RSTREGB": "BRAM_RAMB18_RSTREGB", + "WRERR": "BRAM_RAMB18_WRERR", + "ALMOSTFULL": "BRAM_RAMB18_ALMOSTFULL", + "RDCOUNT8": "BRAM_RAMB18_RDCOUNT8", + "RDCOUNT7": "BRAM_RAMB18_RDCOUNT7", + "DOBDO6": "BRAM_RAMB18_DOBDO6", + "ADDRBTIEHIGH1": "BRAM_RAMB18_ADDRBTIEHIGH1", + "WRCOUNT9": "BRAM_RAMB18_WRCOUNT9", + "ADDRBWRADDR5": "BRAM_RAMB18_ADDRBWRADDR5", + "ADDRBWRADDR3": "BRAM_RAMB18_ADDRBWRADDR3", + "DIBDI9": "BRAM_RAMB18_DIBDI9", + "DOBDO1": "BRAM_RAMB18_DOBDO1", + "RSTREGARSTREG": "BRAM_RAMB18_RSTREGARSTREG", + "DOBDO12": "BRAM_RAMB18_DOBDO12", + "DOBDO9": "BRAM_RAMB18_DOBDO9", + "REGCLKB": "BRAM_RAMB18_REGCLKB", + "RDCOUNT11": "BRAM_RAMB18_RDCOUNT11", + "DIBDI4": "BRAM_RAMB18_DIBDI4", + "ADDRARDADDR13": "BRAM_RAMB18_ADDRARDADDR13", + "REGCLKARDRCLK": "BRAM_RAMB18_REGCLKARDRCLK", + "RDCOUNT9": "BRAM_RAMB18_RDCOUNT9", + "WEA1": "BRAM_RAMB18_WEA1", + "DOBDO14": "BRAM_RAMB18_DOBDO14", + "ADDRBWRADDR6": "BRAM_RAMB18_ADDRBWRADDR6", + "DOADO1": "BRAM_RAMB18_DOADO1", + "DIBDI7": "BRAM_RAMB18_DIBDI7", + "DOADO2": "BRAM_RAMB18_DOADO2", + "RDCOUNT4": "BRAM_RAMB18_RDCOUNT4", + "WEBWE4": "BRAM_RAMB18_WEBWE4", + "DIBDI6": "BRAM_RAMB18_DIBDI6", + "WRCOUNT8": "BRAM_RAMB18_WRCOUNT8", + "DIBDI11": "BRAM_RAMB18_DIBDI11", + "ADDRBWRADDR8": "BRAM_RAMB18_ADDRBWRADDR8", + "DIADI3": "BRAM_RAMB18_DIADI3", + "DOADO12": "BRAM_RAMB18_DOADO12", + "DIBDI2": "BRAM_RAMB18_DIBDI2", + "ADDRARDADDR1": "BRAM_RAMB18_ADDRARDADDR1", + "DOADO11": "BRAM_RAMB18_DOADO11", + "DIBDI12": "BRAM_RAMB18_DIBDI12", + "ADDRARDADDR5": "BRAM_RAMB18_ADDRARDADDR5", + "WEBWE6": "BRAM_RAMB18_WEBWE6", + "DIPBDIP1": "BRAM_RAMB18_DIPBDIP1", + "ADDRBWRADDR0": "BRAM_RAMB18_ADDRBWRADDR0", + "RDCOUNT6": "BRAM_RAMB18_RDCOUNT6", + "ADDRBWRADDR12": "BRAM_RAMB18_ADDRBWRADDR12", + "ADDRBWRADDR11": "BRAM_RAMB18_ADDRBWRADDR11", + "WEBWE3": "BRAM_RAMB18_WEBWE3", + "DOBDO3": "BRAM_RAMB18_DOBDO3", + "WRCOUNT7": "BRAM_RAMB18_WRCOUNT7", + "WRCOUNT1": "BRAM_RAMB18_WRCOUNT1", + "ADDRBWRADDR4": "BRAM_RAMB18_ADDRBWRADDR4", + "DIPADIP0": "BRAM_RAMB18_DIPADIP0", + "REGCEAREGCE": "BRAM_RAMB18_REGCEAREGCE", + "DIADI2": "BRAM_RAMB18_DIADI2", + "DOADO14": "BRAM_RAMB18_DOADO14", + "ADDRBWRADDR7": "BRAM_RAMB18_ADDRBWRADDR7", + "ADDRARDADDR12": "BRAM_RAMB18_ADDRARDADDR12", + "DIADI8": "BRAM_RAMB18_DIADI8", + "DIADI13": "BRAM_RAMB18_DIADI13", + "ADDRARDADDR4": "BRAM_RAMB18_ADDRARDADDR4", + "DIADI4": "BRAM_RAMB18_DIADI4", + "DOADO7": "BRAM_RAMB18_DOADO7", + "DOBDO7": "BRAM_RAMB18_DOBDO7", + "DOBDO5": "BRAM_RAMB18_DOBDO5", + "ADDRBWRADDR2": "BRAM_RAMB18_ADDRBWRADDR2", + "ADDRARDADDR10": "BRAM_RAMB18_ADDRARDADDR10", + "ADDRARDADDR9": "BRAM_RAMB18_ADDRARDADDR9", + "RDERR": "BRAM_RAMB18_RDERR", + "FULL": "BRAM_RAMB18_FULL", + "RDCOUNT0": "BRAM_RAMB18_RDCOUNT0", + "DIBDI10": "BRAM_RAMB18_DIBDI10", + "DOADO13": "BRAM_RAMB18_DOADO13", + "WEA3": "BRAM_RAMB18_WEA3", + "DIADI0": "BRAM_RAMB18_DIADI0", + "ADDRBWRADDR1": "BRAM_RAMB18_ADDRBWRADDR1", + "WEBWE1": "BRAM_RAMB18_WEBWE1", + "ADDRBWRADDR9": "BRAM_RAMB18_ADDRBWRADDR9", + "DIADI7": "BRAM_RAMB18_DIADI7", + "RDCOUNT1": "BRAM_RAMB18_RDCOUNT1", + "DIADI10": "BRAM_RAMB18_DIADI10", + "DOADO10": "BRAM_RAMB18_DOADO10", + "DOBDO8": "BRAM_RAMB18_DOBDO8", + "DIBDI14": "BRAM_RAMB18_DIBDI14", + "DOADO0": "BRAM_RAMB18_DOADO0", + "DOADO4": "BRAM_RAMB18_DOADO4", + "DIADI1": "BRAM_RAMB18_DIADI1", + "WRCOUNT11": "BRAM_RAMB18_WRCOUNT11", + "DIBDI8": "BRAM_RAMB18_DIBDI8", + "DIBDI1": "BRAM_RAMB18_DIBDI1", + "RDCOUNT3": "BRAM_RAMB18_RDCOUNT3", + "ADDRARDADDR2": "BRAM_RAMB18_ADDRARDADDR2", + "WEBWE2": "BRAM_RAMB18_WEBWE2", + "ENARDEN": "BRAM_RAMB18_ENARDEN", + "RDCOUNT10": "BRAM_RAMB18_RDCOUNT10", + "DOPBDOP0": "BRAM_RAMB18_DOPBDOP0", + "DOADO9": "BRAM_RAMB18_DOADO9", + "WRCOUNT5": "BRAM_RAMB18_WRCOUNT5", + "ADDRATIEHIGH1": "BRAM_RAMB18_ADDRATIEHIGH1", + "DIPADIP1": "BRAM_RAMB18_DIPADIP1", + "ALMOSTEMPTY": "BRAM_RAMB18_ALMOSTEMPTY", + "WRCOUNT2": "BRAM_RAMB18_WRCOUNT2", + "DIADI11": "BRAM_RAMB18_DIADI11", + "DOPBDOP1": "BRAM_RAMB18_DOPBDOP1", + "ADDRARDADDR3": "BRAM_RAMB18_ADDRARDADDR3", + "WRCOUNT6": "BRAM_RAMB18_WRCOUNT6", + "WEBWE0": "BRAM_RAMB18_WEBWE0", + "DOBDO13": "BRAM_RAMB18_DOBDO13", + "DOBDO0": "BRAM_RAMB18_DOBDO0", + "ADDRARDADDR7": "BRAM_RAMB18_ADDRARDADDR7", + "DOPADOP0": "BRAM_RAMB18_DOPADOP0", + "ADDRARDADDR0": "BRAM_RAMB18_ADDRARDADDR0", + "CLKARDCLK": "BRAM_RAMB18_CLKARDCLK", + "WEA0": "BRAM_RAMB18_WEA0", + "ADDRARDADDR6": "BRAM_RAMB18_ADDRARDADDR6", + "WEBWE7": "BRAM_RAMB18_WEBWE7", + "DOBDO2": "BRAM_RAMB18_DOBDO2", + "DOBDO11": "BRAM_RAMB18_DOBDO11", + "DIADI9": "BRAM_RAMB18_DIADI9", + "DIBDI5": "BRAM_RAMB18_DIBDI5", + "DIBDI15": "BRAM_RAMB18_DIBDI15", + "CLKBWRCLK": "BRAM_RAMB18_CLKBWRCLK", + "DIADI5": "BRAM_RAMB18_DIADI5", + "RSTRAMB": "BRAM_RAMB18_RSTRAMB", + "DOBDO4": "BRAM_RAMB18_DOBDO4", + "WRCOUNT10": "BRAM_RAMB18_WRCOUNT10", + "DIBDI13": "BRAM_RAMB18_DIBDI13", + "WRCOUNT4": "BRAM_RAMB18_WRCOUNT4", + "EMPTY": "BRAM_RAMB18_EMPTY", + "RDCOUNT5": "BRAM_RAMB18_RDCOUNT5", + "WRCOUNT0": "BRAM_RAMB18_WRCOUNT0", + "DIADI15": "BRAM_RAMB18_DIADI15", + "DIPBDIP0": "BRAM_RAMB18_DIPBDIP0", + "DOPADOP1": "BRAM_RAMB18_DOPADOP1", + "RSTRAMARSTRAM": "BRAM_RAMB18_RSTRAMARSTRAM", + "DIADI12": "BRAM_RAMB18_DIADI12", + "ENBWREN": "BRAM_RAMB18_ENBWREN" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "RAMB36", + "type": "RAMBFIFO36E1", + "site_pins": { + "DIADI7": "BRAM_FIFO36_DIADIU3", + "DOBDO10": "BRAM_FIFO36_DOBDOL5", + "WEBWEU4": "BRAM_FIFO36_WEBWEU4", + "TSTCNT5": "BRAM_FIFO36_TSTCNT5", + "DOADO21": "BRAM_FIFO36_DOADOU10", + "DOADO15": "BRAM_FIFO36_DOADOU7", + "DIADI22": "BRAM_FIFO36_DIADIL11", + "ADDRARDADDRU14": "BRAM_FIFO36_ADDRARDADDRU14", + "WEBWEU6": "BRAM_FIFO36_WEBWEU6", + "DOADO23": "BRAM_FIFO36_DOADOU11", + "ADDRBWRADDRL2": "BRAM_FIFO36_ADDRBWRADDRL2", + "DOADO31": "BRAM_FIFO36_DOADOU15", + "DOBDO1": "BRAM_FIFO36_DOBDOU0", + "WEAU3": "BRAM_FIFO36_WEAU3", + "DOBDO21": "BRAM_FIFO36_DOBDOU10", + "ADDRARDADDRL14": "BRAM_FIFO36_ADDRARDADDRL14", + "DOADO27": "BRAM_FIFO36_DOADOU13", + "CLKARDCLKL": "BRAM_FIFO36_CLKARDCLKL", + "DIBDI18": "BRAM_FIFO36_DIBDIL9", + "RDCOUNT2": "BRAM_FIFO36_RDCOUNT2", + "ADDRBWRADDRU11": "BRAM_FIFO36_ADDRBWRADDRU11", + "ADDRARDADDRL11": "BRAM_FIFO36_ADDRARDADDRL11", + "DOADO2": "BRAM_FIFO36_DOADOL1", + "DIBDI6": "BRAM_FIFO36_DIBDIL3", + "WEAU2": "BRAM_FIFO36_WEAU2", + "DIBDI2": "BRAM_FIFO36_DIBDIL1", + "DOADO11": "BRAM_FIFO36_DOADOU5", + "TSTCNT11": "BRAM_FIFO36_TSTCNT11", + "ADDRBWRADDRU14": "BRAM_FIFO36_ADDRBWRADDRU14", + "INJECTDBITERR": "BRAM_FIFO36_INJECTDBITERR", + "DIADI29": "BRAM_FIFO36_DIADIU14", + "ADDRBWRADDRL8": "BRAM_FIFO36_ADDRBWRADDRL8", + "ADDRARDADDRL7": "BRAM_FIFO36_ADDRARDADDRL7", + "WEBWEU3": "BRAM_FIFO36_WEBWEU3", + "TSTRDOS0": "BRAM_FIFO36_TSTRDOS0", + "DOADO19": "BRAM_FIFO36_DOADOU9", + "DIADI8": "BRAM_FIFO36_DIADIL4", + "DIADI13": "BRAM_FIFO36_DIADIU6", + "DIBDI29": "BRAM_FIFO36_DIBDIU14", + "ADDRBWRADDRU12": "BRAM_FIFO36_ADDRBWRADDRU12", + "DOADO24": "BRAM_FIFO36_DOADOL12", + "DIADI27": "BRAM_FIFO36_DIADIU13", + "DIBDI7": "BRAM_FIFO36_DIBDIU3", + "DOADO29": "BRAM_FIFO36_DOADOU14", + "DIADI11": "BRAM_FIFO36_DIADIU5", + "ADDRBWRADDRU1": "BRAM_FIFO36_ADDRBWRADDRU1", + "DIADI31": "BRAM_FIFO36_DIADIU15", + "REGCLKBL": "BRAM_FIFO36_REGCLKBL", + "DOBDO27": "BRAM_FIFO36_DOBDOU13", + "TSTWROS11": "BRAM_FIFO36_TSTWROS11", + "DOBDO23": "BRAM_FIFO36_DOBDOU11", + "RDCOUNT10": "BRAM_FIFO36_RDCOUNT10", + "TSTIN0": "BRAM_FIFO36_TSTIN0", + "DIPADIP1": "BRAM_FIFO36_DIPADIPU0", + "WEBWEL5": "BRAM_FIFO36_WEBWEL5", + "ADDRARDADDRU13": "BRAM_FIFO36_ADDRARDADDRU13", + "REGCEBL": "BRAM_FIFO36_REGCEBL", + "DOADO6": "BRAM_FIFO36_DOADOL3", + "TSTOUT0": "BRAM_FIFO36_TSTOUT0", + "DOBDO0": "BRAM_FIFO36_DOBDOL0", + "RSTRAMARSTRAMU": "BRAM_FIFO36_RSTRAMARSTRAMU", + "WEBWEU2": "BRAM_FIFO36_WEBWEU2", + "RSTRAMBU": "BRAM_FIFO36_RSTRAMBU", + "DIPADIP3": "BRAM_FIFO36_DIPADIPU1", + "DIBDI5": "BRAM_FIFO36_DIBDIU2", + "WRCOUNT12": "BRAM_FIFO36_WRCOUNT12", + "ADDRARDADDRL9": "BRAM_FIFO36_ADDRARDADDRL9", + "ADDRARDADDRL2": "BRAM_FIFO36_ADDRARDADDRL2", + "TSTRDOS2": "BRAM_FIFO36_TSTRDOS2", + "DIBDI13": "BRAM_FIFO36_DIBDIU6", + "DIPADIP2": "BRAM_FIFO36_DIPADIPL1", + "DOADO7": "BRAM_FIFO36_DOADOU3", + "ADDRBWRADDRU6": "BRAM_FIFO36_ADDRBWRADDRU6", + "ADDRBWRADDRU5": "BRAM_FIFO36_ADDRBWRADDRU5", + "TSTWROS1": "BRAM_FIFO36_TSTWROS1", + "DOBDO26": "BRAM_FIFO36_DOBDOL13", + "TSTBRAMRST": "BRAM_FIFO36_TSTBRAMRST", + "REGCLKARDRCLKL": "BRAM_FIFO36_REGCLKARDRCLKL", + "TSTIN2": "BRAM_FIFO36_TSTIN2", + "DIADI14": "BRAM_FIFO36_DIADIL7", + "TSTWROS3": "BRAM_FIFO36_TSTWROS3", + "DIADI21": "BRAM_FIFO36_DIADIU10", + "DOADO3": "BRAM_FIFO36_DOADOU1", + "TSTOUT1": "BRAM_FIFO36_TSTOUT1", + "ECCPARITY7": "BRAM_FIFO36_ECCPARITY7", + "ADDRBWRADDRU9": "BRAM_FIFO36_ADDRBWRADDRU9", + "DOBDO30": "BRAM_FIFO36_DOBDOL15", + "CASCADEOUTB": "BRAM_FIFO36_CASCADEOUTA", + "DIADI28": "BRAM_FIFO36_DIADIL14", + "ADDRARDADDRU4": "BRAM_FIFO36_ADDRARDADDRU4", + "ADDRBWRADDRU2": "BRAM_FIFO36_ADDRBWRADDRU2", + "DIBDI23": "BRAM_FIFO36_DIBDIU11", + "DIBDI8": "BRAM_FIFO36_DIBDIL4", + "DOADO25": "BRAM_FIFO36_DOADOU12", + "DIADI26": "BRAM_FIFO36_DIADIL13", + "ECCPARITY1": "BRAM_FIFO36_ECCPARITY1", + "REGCLKBU": "BRAM_FIFO36_REGCLKBU", + "DOPADOP1": "BRAM_FIFO36_DOPADOPU0", + "TSTRDOS5": "BRAM_FIFO36_TSTRDOS5", + "CASCADEOUTA": "BRAM_FIFO36_CASCADEOUTB", + "ADDRBWRADDRU0": "BRAM_FIFO36_ADDRBWRADDRU0", + "DOBDO12": "BRAM_FIFO36_DOBDOL6", + "WEBWEU7": "BRAM_FIFO36_WEBWEU7", + "DIBDI4": "BRAM_FIFO36_DIBDIL2", + "RSTREGBU": "BRAM_FIFO36_RSTREGBU", + "WEBWEL1": "BRAM_FIFO36_WEBWEL1", + "DIADI19": "BRAM_FIFO36_DIADIU9", + "TSTRDOS3": "BRAM_FIFO36_TSTRDOS3", + "DOADO1": "BRAM_FIFO36_DOADOU0", + "TSTRDCNTOFF": "BRAM_FIFO36_TSTRDCNTOFF", + "DOADO4": "BRAM_FIFO36_DOADOL2", + "RDCOUNT4": "BRAM_FIFO36_RDCOUNT4", + "DIBDI19": "BRAM_FIFO36_DIBDIU9", + "INJECTSBITERR": "BRAM_FIFO36_INJECTSBITERR", + "DOADO30": "BRAM_FIFO36_DOADOL15", + "ADDRBWRADDRL9": "BRAM_FIFO36_ADDRBWRADDRL9", + "DIADI5": "BRAM_FIFO36_DIADIU2", + "DIADI24": "BRAM_FIFO36_DIADIL12", + "DIPBDIP1": "BRAM_FIFO36_DIPBDIPU0", + "DIBDI9": "BRAM_FIFO36_DIBDIU4", + "ADDRARDADDRU8": "BRAM_FIFO36_ADDRARDADDRU8", + "ADDRARDADDRU2": "BRAM_FIFO36_ADDRARDADDRU2", + "DIADI25": "BRAM_FIFO36_DIADIU12", + "ADDRARDADDRU6": "BRAM_FIFO36_ADDRARDADDRU6", + "TSTCNT7": "BRAM_FIFO36_TSTCNT7", + "TSTWROS8": "BRAM_FIFO36_TSTWROS8", + "DOADO14": "BRAM_FIFO36_DOADOL7", + "WRCOUNT4": "BRAM_FIFO36_WRCOUNT4", + "TSTCNT10": "BRAM_FIFO36_TSTCNT10", + "DOPADOP0": "BRAM_FIFO36_DOPADOPL0", + "TSTWROS5": "BRAM_FIFO36_TSTWROS5", + "ADDRARDADDRL13": "BRAM_FIFO36_ADDRARDADDRL13", + "ADDRBWRADDRU3": "BRAM_FIFO36_ADDRBWRADDRU3", + "DOADO22": "BRAM_FIFO36_DOADOL11", + "TSTCNT4": "BRAM_FIFO36_TSTCNT4", + "WEBWEL0": "BRAM_FIFO36_WEBWEL0", + "DOBDO13": "BRAM_FIFO36_DOBDOU6", + "DIADI1": "BRAM_FIFO36_DIADIU0", + "SBITERR": "BRAM_FIFO36_SBITERR", + "TSTWROS9": "BRAM_FIFO36_TSTWROS9", + "WEBWEL7": "BRAM_FIFO36_WEBWEL7", + "WRCOUNT5": "BRAM_FIFO36_WRCOUNT5", + "ADDRARDADDRL12": "BRAM_FIFO36_ADDRARDADDRL12", + "CLKBWRCLKL": "BRAM_FIFO36_CLKBWRCLKL", + "TSTWROS0": "BRAM_FIFO36_TSTWROS0", + "TSTWROS4": "BRAM_FIFO36_TSTWROS4", + "WRCOUNT2": "BRAM_FIFO36_WRCOUNT2", + "ADDRBWRADDRL3": "BRAM_FIFO36_ADDRBWRADDRL3", + "WEBWEL2": "BRAM_FIFO36_WEBWEL2", + "DIPBDIP2": "BRAM_FIFO36_DIPBDIPL1", + "ADDRBWRADDRL10": "BRAM_FIFO36_ADDRBWRADDRL10", + "ADDRBWRADDRL7": "BRAM_FIFO36_ADDRBWRADDRL7", + "ADDRARDADDRU9": "BRAM_FIFO36_ADDRARDADDRU9", + "TSTIN4": "BRAM_FIFO36_TSTIN4", + "ADDRBWRADDRU4": "BRAM_FIFO36_ADDRBWRADDRU4", + "DIBDI14": "BRAM_FIFO36_DIBDIL7", + "ADDRARDADDRL6": "BRAM_FIFO36_ADDRARDADDRL6", + "DIBDI28": "BRAM_FIFO36_DIBDIL14", + "DOBDO31": "BRAM_FIFO36_DOBDOU15", + "WRCOUNT7": "BRAM_FIFO36_WRCOUNT7", + "DIBDI21": "BRAM_FIFO36_DIBDIU10", + "EMPTY": "BRAM_FIFO36_EMPTY", + "WEAU0": "BRAM_FIFO36_WEAU0", + "ADDRARDADDRU7": "BRAM_FIFO36_ADDRARDADDRU7", + "DOBDO28": "BRAM_FIFO36_DOBDOL14", + "TSTCNT9": "BRAM_FIFO36_TSTCNT9", + "DIBDI22": "BRAM_FIFO36_DIBDIL11", + "ADDRBWRADDRU8": "BRAM_FIFO36_ADDRBWRADDRU8", + "ADDRARDADDRU11": "BRAM_FIFO36_ADDRARDADDRU11", + "ENARDENU": "BRAM_FIFO36_ENARDENU", + "TSTFLAGIN": "BRAM_FIFO36_TSTFLAGIN", + "TSTCNT3": "BRAM_FIFO36_TSTCNT3", + "ECCPARITY2": "BRAM_FIFO36_ECCPARITY2", + "ADDRBWRADDRL4": "BRAM_FIFO36_ADDRBWRADDRL4", + "TSTCNT2": "BRAM_FIFO36_TSTCNT2", + "DIADI30": "BRAM_FIFO36_DIADIL15", + "ENARDENL": "BRAM_FIFO36_ENARDENL", + "DIADI23": "BRAM_FIFO36_DIADIU11", + "TSTIN1": "BRAM_FIFO36_TSTIN1", + "WEAL1": "BRAM_FIFO36_WEAL1", + "ALMOSTFULL": "BRAM_FIFO36_ALMOSTFULL", + "DOBDO25": "BRAM_FIFO36_DOBDOU12", + "RDCOUNT8": "BRAM_FIFO36_RDCOUNT8", + "ADDRBWRADDRU10": "BRAM_FIFO36_ADDRBWRADDRU10", + "DOBDO6": "BRAM_FIFO36_DOBDOL3", + "WRCOUNT9": "BRAM_FIFO36_WRCOUNT9", + "RDCOUNT11": "BRAM_FIFO36_RDCOUNT11", + "DOPADOP2": "BRAM_FIFO36_DOPADOPL1", + "WEBWEL4": "BRAM_FIFO36_WEBWEL4", + "DOBDO16": "BRAM_FIFO36_DOBDOL8", + "ADDRBWRADDRL14": "BRAM_FIFO36_ADDRBWRADDRL14", + "DOBDO14": "BRAM_FIFO36_DOBDOL7", + "WEAL0": "BRAM_FIFO36_WEAL0", + "CLKARDCLKU": "BRAM_FIFO36_CLKARDCLKU", + "ADDRARDADDRL10": "BRAM_FIFO36_ADDRARDADDRL10", + "WRCOUNT8": "BRAM_FIFO36_WRCOUNT8", + "DIBDI11": "BRAM_FIFO36_DIBDIU5", + "DIADI3": "BRAM_FIFO36_DIADIU1", + "DOADO12": "BRAM_FIFO36_DOADOL6", + "ADDRBWRADDRL13": "BRAM_FIFO36_ADDRBWRADDRL13", + "WEBWEU0": "BRAM_FIFO36_WEBWEU0", + "ADDRARDADDRU5": "BRAM_FIFO36_ADDRARDADDRU5", + "DIBDI3": "BRAM_FIFO36_DIBDIU1", + "RDCOUNT6": "BRAM_FIFO36_RDCOUNT6", + "REGCLKARDRCLKU": "BRAM_FIFO36_REGCLKARDRCLKU", + "DIPBDIP3": "BRAM_FIFO36_DIPBDIPU1", + "DOBDO3": "BRAM_FIFO36_DOBDOU1", + "WRCOUNT1": "BRAM_FIFO36_WRCOUNT1", + "DIPADIP0": "BRAM_FIFO36_DIPADIPL0", + "TSTOUT4": "BRAM_FIFO36_TSTOUT4", + "DIADI2": "BRAM_FIFO36_DIADIL1", + "TSTWROS2": "BRAM_FIFO36_TSTWROS2", + "RSTREGARSTREGL": "BRAM_FIFO36_RSTREGARSTREGL", + "DIADI4": "BRAM_FIFO36_DIADIL2", + "ADDRARDADDRL0": "BRAM_FIFO36_ADDRARDADDRL0", + "DIADI18": "BRAM_FIFO36_DIADIL9", + "ECCPARITY3": "BRAM_FIFO36_ECCPARITY3", + "RDERR": "BRAM_FIFO36_RDERR", + "DIBDI30": "BRAM_FIFO36_DIBDIL15", + "FULL": "BRAM_FIFO36_FULL", + "RSTRAMARSTRAMLRST": "BRAM_FIFO36_RSTRAMARSTRAMLRST", + "DIBDI10": "BRAM_FIFO36_DIBDIL5", + "DOADO13": "BRAM_FIFO36_DOADOU6", + "ADDRARDADDRL5": "BRAM_FIFO36_ADDRARDADDRL5", + "TSTRDOS4": "BRAM_FIFO36_TSTRDOS4", + "ECCPARITY6": "BRAM_FIFO36_ECCPARITY6", + "DOBDO7": "BRAM_FIFO36_DOBDOU3", + "TSTIN3": "BRAM_FIFO36_TSTIN3", + "ENBWRENL": "BRAM_FIFO36_ENBWRENL", + "DIADI10": "BRAM_FIFO36_DIADIL5", + "ADDRBWRADDRL6": "BRAM_FIFO36_ADDRBWRADDRL6", + "ECCPARITY0": "BRAM_FIFO36_ECCPARITY0", + "TSTOUT2": "BRAM_FIFO36_TSTOUT2", + "ADDRARDADDRU3": "BRAM_FIFO36_ADDRARDADDRU3", + "DIBDI20": "BRAM_FIFO36_DIBDIL10", + "REGCEAREGCEL": "BRAM_FIFO36_REGCEAREGCEL", + "DOADO26": "BRAM_FIFO36_DOADOL13", + "ADDRBWRADDRL0": "BRAM_FIFO36_ADDRBWRADDRL0", + "TSTRDOS12": "BRAM_FIFO36_TSTRDOS12", + "DOADO10": "BRAM_FIFO36_DOADOL5", + "DOBDO22": "BRAM_FIFO36_DOBDOL11", + "DOADO17": "BRAM_FIFO36_DOADOU8", + "DOADO16": "BRAM_FIFO36_DOADOL8", + "TSTWROS6": "BRAM_FIFO36_TSTWROS6", + "ADDRBWRADDRL15": "BRAM_FIFO36_ADDRBWRADDRL15", + "DBITERR": "BRAM_FIFO36_DBITERR", + "TSTRDOS6": "BRAM_FIFO36_TSTRDOS6", + "TSTCNT8": "BRAM_FIFO36_TSTCNT8", + "DOBDO2": "BRAM_FIFO36_DOBDOL1", + "DOBDO19": "BRAM_FIFO36_DOBDOU9", + "DIADI9": "BRAM_FIFO36_DIADIU4", + "WEBWEL6": "BRAM_FIFO36_WEBWEL6", + "ADDRBWRADDRL12": "BRAM_FIFO36_ADDRBWRADDRL12", + "DIBDI26": "BRAM_FIFO36_DIBDIL13", + "DOADO18": "BRAM_FIFO36_DOADOL9", + "WRCOUNT10": "BRAM_FIFO36_WRCOUNT10", + "RSTRAMBL": "BRAM_FIFO36_RSTRAMBL", + "TSTOUT3": "BRAM_FIFO36_TSTOUT3", + "WRCOUNT0": "BRAM_FIFO36_WRCOUNT0", + "WEAL3": "BRAM_FIFO36_WEAL3", + "DOADO20": "BRAM_FIFO36_DOADOL10", + "WEBWEL3": "BRAM_FIFO36_WEBWEL3", + "DOBDO18": "BRAM_FIFO36_DOBDOL9", + "ADDRARDADDRL1": "BRAM_FIFO36_ADDRARDADDRL1", + "ADDRARDADDRL3": "BRAM_FIFO36_ADDRARDADDRL3", + "ADDRBWRADDRL11": "BRAM_FIFO36_ADDRBWRADDRL11", + "TSTWRCNTOFF": "BRAM_FIFO36_TSTWRCNTOFF", + "DOADO28": "BRAM_FIFO36_DOADOL14", + "WRCOUNT3": "BRAM_FIFO36_WRCOUNT3", + "DOBDO15": "BRAM_FIFO36_DOBDOU7", + "ENBWRENU": "BRAM_FIFO36_ENBWRENU", + "DOBDO17": "BRAM_FIFO36_DOBDOU8", + "DIBDI0": "BRAM_FIFO36_DIBDIL0", + "ECCPARITY5": "BRAM_FIFO36_ECCPARITY5", + "WRERR": "BRAM_FIFO36_WRERR", + "RDCOUNT1": "BRAM_FIFO36_RDCOUNT1", + "RSTREGBL": "BRAM_FIFO36_RSTREGBL", + "TSTCNT6": "BRAM_FIFO36_TSTCNT6", + "RDCOUNT7": "BRAM_FIFO36_RDCOUNT7", + "DOADO8": "BRAM_FIFO36_DOADOL4", + "DOADO5": "BRAM_FIFO36_DOADOU2", + "TSTRDOS8": "BRAM_FIFO36_TSTRDOS8", + "ADDRARDADDRU12": "BRAM_FIFO36_ADDRARDADDRU12", + "ADDRBWRADDRL1": "BRAM_FIFO36_ADDRBWRADDRL1", + "TSTWROS10": "BRAM_FIFO36_TSTWROS10", + "DIBDI31": "BRAM_FIFO36_DIBDIU15", + "ADDRARDADDRU0": "BRAM_FIFO36_ADDRARDADDRU0", + "CASCADEINA": "BRAM_FIFO36_CASCADEINB", + "DIBDI16": "BRAM_FIFO36_DIBDIL8", + "DIADI6": "BRAM_FIFO36_DIADIL3", + "RDCOUNT3": "BRAM_FIFO36_RDCOUNT3", + "DIBDI27": "BRAM_FIFO36_DIBDIU13", + "WRCOUNT11": "BRAM_FIFO36_WRCOUNT11", + "WEAU1": "BRAM_FIFO36_WEAU1", + "TSTCNT0": "BRAM_FIFO36_TSTCNT0", + "DIBDI25": "BRAM_FIFO36_DIBDIU12", + "DIBDI12": "BRAM_FIFO36_DIBDIL6", + "TSTRDOS11": "BRAM_FIFO36_TSTRDOS11", + "RDCOUNT5": "BRAM_FIFO36_RDCOUNT5", + "RDCOUNT9": "BRAM_FIFO36_RDCOUNT9", + "DIBDI17": "BRAM_FIFO36_DIBDIU8", + "DOPBDOP2": "BRAM_FIFO36_DOPBDOPL1", + "CASCADEINB": "BRAM_FIFO36_CASCADEINA", + "ECCPARITY4": "BRAM_FIFO36_ECCPARITY4", + "ADDRBWRADDRU7": "BRAM_FIFO36_ADDRBWRADDRU7", + "TSTWROS12": "BRAM_FIFO36_TSTWROS12", + "ADDRARDADDRL4": "BRAM_FIFO36_ADDRARDADDRL4", + "DOPBDOP3": "BRAM_FIFO36_DOPBDOPU1", + "WEAL2": "BRAM_FIFO36_WEAL2", + "WRCOUNT6": "BRAM_FIFO36_WRCOUNT6", + "DOBDO29": "BRAM_FIFO36_DOBDOU14", + "DOBDO5": "BRAM_FIFO36_DOBDOU2", + "ADDRARDADDRL15": "BRAM_FIFO36_ADDRARDADDRL15", + "DOPBDOP0": "BRAM_FIFO36_DOPBDOPL0", + "WEBWEU1": "BRAM_FIFO36_WEBWEU1", + "DIADI20": "BRAM_FIFO36_DIADIL10", + "RDCOUNT0": "BRAM_FIFO36_RDCOUNT0", + "DOBDO11": "BRAM_FIFO36_DOBDOU5", + "ADDRARDADDRU10": "BRAM_FIFO36_ADDRARDADDRU10", + "DOBDO24": "BRAM_FIFO36_DOBDOL12", + "TSTRDOS10": "BRAM_FIFO36_TSTRDOS10", + "TSTCNT12": "BRAM_FIFO36_TSTCNT12", + "DIPBDIP0": "BRAM_FIFO36_DIPBDIPL0", + "ADDRARDADDRL8": "BRAM_FIFO36_ADDRARDADDRL8", + "ADDRBWRADDRU13": "BRAM_FIFO36_ADDRBWRADDRU13", + "DOBDO8": "BRAM_FIFO36_DOBDOL4", + "DIADI17": "BRAM_FIFO36_DIADIU8", + "RSTREGARSTREGU": "BRAM_FIFO36_RSTREGARSTREGU", + "REGCEBU": "BRAM_FIFO36_REGCEBU", + "TSTRDOS1": "BRAM_FIFO36_TSTRDOS1", + "DIADI0": "BRAM_FIFO36_DIADIL0", + "DIBDI1": "BRAM_FIFO36_DIBDIU0", + "ADDRARDADDRU1": "BRAM_FIFO36_ADDRARDADDRU1", + "DOBDO9": "BRAM_FIFO36_DOBDOU4", + "TSTRDOS9": "BRAM_FIFO36_TSTRDOS9", + "DOADO9": "BRAM_FIFO36_DOADOU4", + "ALMOSTEMPTY": "BRAM_FIFO36_ALMOSTEMPTY", + "DIADI16": "BRAM_FIFO36_DIADIL8", + "DOPBDOP1": "BRAM_FIFO36_DOPBDOPU0", + "DOADO0": "BRAM_FIFO36_DOADOL0", + "ADDRBWRADDRL5": "BRAM_FIFO36_ADDRBWRADDRL5", + "DIBDI15": "BRAM_FIFO36_DIBDIU7", + "CLKBWRCLKU": "BRAM_FIFO36_CLKBWRCLKU", + "TSTOFF": "BRAM_FIFO36_TSTOFF", + "DOBDO4": "BRAM_FIFO36_DOBDOL2", + "TSTCNT1": "BRAM_FIFO36_TSTCNT1", + "DOPADOP3": "BRAM_FIFO36_DOPADOPU1", + "DOBDO20": "BRAM_FIFO36_DOBDOL10", + "REGCEAREGCEU": "BRAM_FIFO36_REGCEAREGCEU", + "RDCOUNT12": "BRAM_FIFO36_RDCOUNT12", + "DIADI15": "BRAM_FIFO36_DIADIU7", + "TSTRDOS7": "BRAM_FIFO36_TSTRDOS7", + "DIBDI24": "BRAM_FIFO36_DIBDIL12", + "DIADI12": "BRAM_FIFO36_DIADIL6", + "TSTWROS7": "BRAM_FIFO36_TSTWROS7", + "WEBWEU5": "BRAM_FIFO36_WEBWEU5" + }, + "x_coord": 0 + } + ], + "wires": [ + "BRAM_EE4BEG1_2", + "BRAM_R_IMUX_ADDRBWRADDRL5", + "BRAM_IMUX34_4", + "BRAM_IMUX31_1", + "BRAM_CASCOUT_ADDRARDADDRU8", + "BRAM_IMUX7_1", + "BRAM_IMUX26_3", + "BRAM_IMUX22_UTURN_0", + "BRAM_IMUX21_UTURN_0", + "BRAM_WW2END1_1", + "BRAM_IMUX36_1", + "BRAM_LH6_2", + "BRAM_FIFO36_ADDRARDADDRU6", + "BRAM_IMUX30_UTURN_2", + "BRAM_FIFO36_TSTCNT2", + "BRAM_FIFO36_TSTIN2", + "BRAM_WW4B2_1", + "BRAM_EL1BEG0_3", + "BRAM_WW4A1_4", + "BRAM_FIFO18_ADDRARDADDR8", + "BRAM_IMUX25_UTURN_4", + "BRAM_FIFO18_ADDRATIEHIGH0", + "BRAM_SW2A0_4", + "BRAM_SE4BEG0_0", + "BRAM_CTRL1_0", + "BRAM_FIFO36_DOBDOU7", + "BRAM_IMUX16_1", + "BRAM_FIFO18_ADDRBWRADDR12", + "BRAM_WW2A2_1", + "BRAM_FIFO36_DOBDOU14", + "BRAM_ER1BEG3_1", + "BRAM_EE2BEG3_4", + "BRAM_IMUX3_UTURN_3", + "BRAM_FIFO36_WRCOUNT2", + "BRAM_SW2A2_3", + "BRAM_WW2END2_4", + "BRAM_IMUX43_UTURN_4", + "BRAM_IMUX13_2", + "BRAM_FIFO36_DIBDIU11", + "BRAM_FIFO36_DIADIU6", + "BRAM_BLOCK_OUTS_L_B3_3", + "BRAM_FIFO36_DIPADIPL0", + "BRAM_FIFO36_ADDRBWRADDRU11", + "BRAM_IMUX25_0", + "BRAM_WL1END1_2", + "BRAM_EE2BEG2_4", + "BRAM_FIFO36_ADDRBWRADDRL10", + "BRAM_BYP5_0", + "BRAM_FAN7_4", + "BRAM_RAMB18_DOADO8", + "BRAM_R_IMUX_ADDRBWRADDRU3", + "BRAM_FIFO36_ADDRBWRADDRL7", + "BRAM_CASCINTOP_ADDRARDADDRU6", + "BRAM_FIFO36_DOADOU6", + "BRAM_RAMB18_ADDRARDADDR7", + "BRAM_RAMB18_DIPBDIP1", + "BRAM_NE4C2_0", + "BRAM_WL1END1_1", + "BRAM_EL1BEG3_4", + "BRAM_EE2BEG2_0", + "BRAM_FIFO36_TSTOUT1", + "BRAM_LOGIC_OUTS_B13_1", + "BRAM_FIFO36_TSTCNT0", + "BRAM_EE2A2_0", + "BRAM_EE2BEG0_2", + "BRAM_LH9_4", + "BRAM_IMUX1_1", + "BRAM_UTURN_ADDRARDADDRU3", + "BRAM_UTURN_ADDRBWRADDRL3", + "BRAM_LH12_1", + "BRAM_IMUX13_0", + "BRAM_IMUX31_4", + "BRAM_RAMB18_DOPBDOP0", + "BRAM_ADDRARDADDRU10", + "BRAM_EE4A2_1", + "BRAM_IMUX11_UTURN_1", + "BRAM_RAMB18_DOBDO4", + "BRAM_FIFO18_DIBDI13", + "BRAM_FIFO36_WEBWEL1", + "BRAM_IMUX38_UTURN_3", + "BRAM_EE2BEG2_2", + "BRAM_WW2END3_2", + "BRAM_BYP0_4", + "BRAM_IMUX1_UTURN_2", + "BRAM_RAMB18_RDCOUNT8", + "BRAM_EE4B3_1", + "BRAM_BYP6_4", + "BRAM_ADDRARDADDRL8", + "BRAM_FIFO18_DOBDO0", + "BRAM_NE2A1_0", + "BRAM_FIFO18_DIBDI9", + "BRAM_SE4BEG3_4", + "BRAM_BLOCK_OUTS_L_B2_2", + "BRAM_LOGIC_OUTS_B18_4", + "BRAM_IMUX9_UTURN_4", + "BRAM_IMUX16_UTURN_0", + "BRAM_FIFO18_DIBDI10", + "BRAM_EL1BEG2_0", + "BRAM_FIFO36_DBITERR", + "BRAM_CTRL0_0", + "BRAM_FIFO18_ADDRARDADDR0", + "BRAM_NW4A0_0", + "BRAM_IMUX6_0", + "BRAM_IMUX46_UTURN_0", + "BRAM_IMUX16_UTURN_1", + "BRAM_CASCOUT_ADDRARDADDRU12", + "BRAM_WW4C0_4", + "BRAM_IMUX23_UTURN_2", + "BRAM_IMUX25_3", + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "BRAM_IMUX0_UTURN_2", + "BRAM_BLOCK_OUTS_L_B2_3", + "BRAM_ADDRARDADDRU1", + "BRAM_FIFO36_WEBWEU2", + "BRAM_IMUX38_UTURN_2", + "BRAM_FIFO36_DIBDIU8", + "BRAM_IMUX5_3", + "BRAM_SW4A3_0", + "BRAM_LH11_0", + "BRAM_IMUX26_4", + "BRAM_MONITOR_N_4", + "BRAM_LOGIC_OUTS_B23_3", + "BRAM_UTURN_ADDRARDADDRL3", + "BRAM_EE4C3_4", + "BRAM_FIFO18_RDCOUNT6", + "BRAM_IMUX37_UTURN_0", + "BRAM_IMUX2_1", + "BRAM_WR1END3_2", + "BRAM_CASCINTOP_ADDRARDADDRU11", + "BRAM_NE4BEG2_0", + "BRAM_FIFO36_WEAU0", + "BRAM_IMUX15_3", + "BRAM_FIFO18_ADDRBWRADDR3", + "BRAM_IMUX31_2", + "BRAM_IMUX10_0", + "BRAM_WW2END1_4", + "BRAM_LOGIC_OUTS_B5_2", + "BRAM_FIFO36_DOADOU1", + "BRAM_NW4A0_1", + "BRAM_FIFO36_DIBDIL1", + "BRAM_NW4END0_3", + "BRAM_FIFO36_ADDRBWRADDRU12", + "BRAM_SE4C0_4", + "BRAM_FIFO36_TSTIN4", + "BRAM_FIFO36_WEAL3", + "BRAM_FIFO36_DIBDIL2", + "BRAM_CASCINTOP_ADDRARDADDRU0", + "BRAM_WL1END2_4", + "BRAM_FIFO36_DIBDIL7", + "BRAM_BYP4_0", + "BRAM_NW4END0_4", + "BRAM_CLK0_3", + "BRAM_BYP1_2", + "BRAM_UTURN_ADDRBWRADDRU6", + "BRAM_EE4A0_4", + "BRAM_SE4BEG2_4", + "BRAM_NE2A2_3", + "BRAM_SW4END0_1", + "BRAM_IMUX24_UTURN_0", + "BRAM_R_IMUX_ADDRBWRADDRU11", + "BRAM_SW2A2_2", + "BRAM_WW4C0_2", + "BRAM_FIFO36_ADDRARDADDRL1", + "BRAM_WW4END2_1", + "BRAM_FIFO36_DIADIL9", + "BRAM_WW4A3_2", + "BRAM_ADDRARDADDRL9", + "BRAM_IMUX27_UTURN_4", + "BRAM_RAMB18_DOADO0", + "BRAM_NW2A1_2", + "BRAM_LH5_2", + "BRAM_CASCOUT_ADDRBWRADDRU3", + "BRAM_SE4BEG1_3", + "BRAM_FIFO36_DIADIL13", + "BRAM_IMUX6_UTURN_3", + "BRAM_EE2A3_0", + "BRAM_FIFO36_ADDRARDADDRL10", + "BRAM_FIFO36_ADDRARDADDRL6", + "BRAM_SE4C2_4", + "BRAM_EE2A3_1", + "BRAM_FIFO36_DOADOU9", + "BRAM_UTURN_ADDRARDADDRL6", + "BRAM_FIFO36_RDCOUNT6", + "BRAM_RAMB18_WRERR", + "BRAM_UTURN_ADDRARDADDRU2", + "BRAM_IMUX35_2", + "BRAM_BYP4_2", + "BRAM_IMUX26_UTURN_4", + "BRAM_FIFO36_DOADOL14", + "BRAM_RAMB18_ADDRBWRADDR2", + "BRAM_RAMB18_WEA2", + "BRAM_FIFO18_ENARDEN", + "BRAM_NW4END3_0", + "BRAM_EE4C3_1", + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "BRAM_FIFO18_RSTREGB", + "BRAM_IMUX40_UTURN_4", + "BRAM_UTURN_ADDRBWRADDRL12", + "BRAM_WW2END1_0", + "BRAM_FIFO18_WRCOUNT11", + "BRAM_FIFO18_WRCOUNT1", + "BRAM_R_IMUX_ADDRBWRADDRL10", + "BRAM_EE4A1_3", + "BRAM_LOGIC_OUTS_B9_0", + "BRAM_SE2A0_3", + "BRAM_LOGIC_OUTS_B9_4", + "BRAM_WR1END2_4", + "BRAM_UTURN_ADDRBWRADDRL6", + "BRAM_FIFO36_TSTWROS3", + "BRAM_IMUX20_1", + "BRAM_LOGIC_OUTS_B22_0", + "BRAM_NW4END0_2", + "BRAM_CASCINTOP_ADDRARDADDRU12", + "BRAM_IMUX47_4", + "BRAM_FIFO36_DOBDOU4", + "BRAM_IMUX26_2", + "BRAM_LH1_4", + "BRAM_NE4C1_0", + "BRAM_UTURN_ADDRARDADDRL10", + "BRAM_R_IMUX_ADDRBWRADDRU4", + "BRAM_IMUX5_0", + "BRAM_LH9_2", + "BRAM_FIFO18_ADDRARDADDR4", + "BRAM_LOGIC_OUTS_B9_2", + "BRAM_LOGIC_OUTS_B20_1", + "BRAM_RAMB18_RDCOUNT2", + "BRAM_IMUX36_3", + "BRAM_IMUX44_UTURN_1", + "BRAM_FIFO18_DIBDI12", + "BRAM_IMUX34_UTURN_1", + "BRAM_IMUX44_3", + "BRAM_R_IMUX_ADDRBWRADDRL14", + "BRAM_BYP7_2", + "BRAM_RAMB18_DOADO13", + "BRAM_FIFO36_DOBDOU15", + "BRAM_FIFO18_DOBDO15", + "BRAM_FIFO36_DOBDOL10", + "BRAM_RAMB18_DOBDO8", + "BRAM_FIFO36_RDCOUNT4", + "BRAM_SE4C2_1", + "BRAM_CLK0_4", + "BRAM_FIFO36_DOADOU10", + "BRAM_SW4A0_3", + "BRAM_R_IMUX_ADDRARDADDRU3", + "BRAM_IMUX36_0", + "BRAM_IMUX41_UTURN_4", + "BRAM_NE4BEG3_4", + "BRAM_NW2A0_1", + "BRAM_FIFO36_WRCOUNT8", + "BRAM_LH6_1", + "BRAM_EE4C2_3", + "BRAM_FIFO36_CLKARDCLKL", + "BRAM_IMUX31_UTURN_1", + "BRAM_NW4END2_1", + "BRAM_EE4B2_3", + "BRAM_FIFO36_TSTOUT0", + "BRAM_WW4END2_4", + "BRAM_IMUX44_UTURN_0", + "BRAM_FAN0_2", + "BRAM_IMUX28_UTURN_1", + "BRAM_WW4B3_2", + "BRAM_WW4C3_1", + "BRAM_IMUX41_2", + "BRAM_SE2A3_0", + "BRAM_IMUX15_UTURN_0", + "BRAM_EE4C0_1", + "BRAM_IMUX41_UTURN_2", + "BRAM_FIFO36_DIBDIL9", + "BRAM_IMUX5_UTURN_0", + "BRAM_LOGIC_OUTS_B0_1", + "BRAM_RAMB18_DIADI3", + "BRAM_FIFO36_DIADIU15", + "BRAM_LOGIC_OUTS_B16_3", + "BRAM_WL1END2_2", + "BRAM_IMUX32_4", + "BRAM_IMUX5_2", + "BRAM_NW2A2_0", + "BRAM_UTURN_ADDRBWRADDRL8", + "BRAM_NE4BEG1_2", + "BRAM_FIFO36_DIADIU0", + "BRAM_FIFO36_WEBWEU7", + "BRAM_FIFO36_DOBDOU6", + "BRAM_IMUX31_3", + "BRAM_IMUX4_UTURN_0", + "BRAM_FIFO36_DIPBDIPL0", + "BRAM_IMUX2_3", + "BRAM_IMUX24_0", + "BRAM_EE2BEG1_3", + "BRAM_LH3_1", + "BRAM_FAN5_0", + "BRAM_MONITOR_N_1", + "BRAM_FIFO36_TSTWRCNTOFF", + "BRAM_FIFO36_ADDRBWRADDRL3", + "BRAM_IMUX34_UTURN_4", + "BRAM_WW4A2_2", + "BRAM_LH3_2", + "BRAM_EE2BEG2_1", + "BRAM_ADDRARDADDRL3", + "BRAM_FAN6_2", + "BRAM_FIFO36_DOADOL2", + "BRAM_NW4END3_4", + "BRAM_FIFO36_TSTWROS2", + "BRAM_BYP7_3", + "BRAM_WW4C0_0", + "BRAM_IMUX3_4", + "BRAM_FIFO36_DOPBDOPL1", + "BRAM_IMUX41_UTURN_3", + "BRAM_FIFO18_DIBDI5", + "BRAM_FIFO36_DIPBDIPL1", + "BRAM_FIFO36_DIADIL8", + "BRAM_IMUX21_1", + "BRAM_SW4A3_4", + "BRAM_LH4_2", + "BRAM_CASCINTOP_ADDRARDADDRU8", + "BRAM_IMUX9_UTURN_2", + "BRAM_ER1BEG3_2", + "BRAM_EE4B3_0", + "BRAM_UTURN_ADDRBWRADDRU3", + "BRAM_FIFO36_ADDRARDADDRL3", + "BRAM_NW4A2_0", + "BRAM_SE4BEG1_1", + "BRAM_R_IMUX_ADDRBWRADDRL12", + "BRAM_FIFO36_ADDRARDADDRL5", + "BRAM_IMUX28_1", + "BRAM_WW4A0_1", + "BRAM_WW2END0_4", + "BRAM_LH1_0", + "BRAM_CASCINBOT_ADDRARDADDRU7", + "BRAM_FIFO36_DOADOU3", + "BRAM_FIFO36_DOADOU13", + "BRAM_FIFO36_ADDRARDADDRL7", + "BRAM_EE2A1_3", + "BRAM_IMUX18_UTURN_3", + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "BRAM_FIFO36_WEAU3", + "BRAM_FIFO36_ADDRBWRADDRU6", + "BRAM_FIFO18_DIADI0", + "BRAM_UTURN_ADDRARDADDRL7", + "BRAM_FAN1_4", + "BRAM_FIFO18_DOADO4", + "BRAM_FIFO36_TSTRDOS12", + "BRAM_IMUX23_2", + "BRAM_ER1BEG3_3", + "BRAM_IMUX29_1", + "BRAM_FIFO36_ADDRBWRADDRL8", + "BRAM_RAMB18_ADDRBWRADDR6", + "BRAM_NW4END1_3", + "BRAM_IMUX7_UTURN_4", + "BRAM_R_IMUX_ADDRARDADDRU1", + "BRAM_SW4END2_0", + "BRAM_WW4END1_4", + "BRAM_RAMB18_ADDRBWRADDR13", + "BRAM_IMUX12_3", + "BRAM_R_IMUX_ADDRBWRADDRU12", + "BRAM_BYP0_2", + "BRAM_SW2A0_3", + "BRAM_FIFO18_DOBDO6", + "BRAM_UTURN_ADDRBWRADDRL13", + "BRAM_IMUX6_2", + "BRAM_WR1END2_2", + "BRAM_EE2BEG1_1", + "BRAM_WW2END2_1", + "BRAM_IMUX21_UTURN_2", + "BRAM_IMUX36_4", + "BRAM_NW4END2_3", + "BRAM_CTRL1_1", + "BRAM_IMUX8_2", + "BRAM_IMUX27_4", + "BRAM_PMVBRAM_SELECT3", + "BRAM_LOGIC_OUTS_B7_3", + "BRAM_FIFO36_DIADIL1", + "BRAM_IMUX9_2", + "BRAM_LOGIC_OUTS_B19_1", + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "BRAM_WW4END0_1", + "BRAM_IMUX39_UTURN_3", + "BRAM_R_IMUX_ADDRBWRADDRU2", + "BRAM_RAMB18_DIADI4", + "BRAM_RAMB18_DOADO6", + "BRAM_ADDRARDADDRL0", + "BRAM_IMUX9_UTURN_1", + "BRAM_IMUX28_0", + "BRAM_LH6_0", + "BRAM_FIFO36_DIADIL5", + "BRAM_LOGIC_OUTS_B4_0", + "BRAM_FIFO18_ADDRBWRADDR1", + "BRAM_FIFO36_DOBDOL14", + "BRAM_RAMB18_WRCOUNT5", + "BRAM_RAMB18_ADDRARDADDR10", + "BRAM_IMUX33_0", + "BRAM_R_IMUX_ADDRARDADDRU14", + "BRAM_SW2A3_2", + "BRAM_IMUX8_UTURN_4", + "BRAM_LH4_0", + "BRAM_LOGIC_OUTS_B5_1", + "BRAM_CASCOUT_ADDRBWRADDRU1", + "BRAM_IMUX40_3", + "BRAM_IMUX8_UTURN_3", + "BRAM_FIFO36_ADDRBWRADDRL15", + "BRAM_FIFO18_DOADO0", + "BRAM_FIFO36_WEAL1", + "BRAM_IMUX13_UTURN_4", + "BRAM_EE4BEG0_3", + "BRAM_IMUX3_UTURN_1", + "BRAM_IMUX4_1", + "BRAM_FIFO18_WRCOUNT7", + "BRAM_IMUX16_2", + "BRAM_IMUX47_UTURN_2", + "BRAM_FIFO36_FULL", + "BRAM_IMUX21_UTURN_4", + "BRAM_NE4C1_3", + "BRAM_RAMB18_DOBDO13", + "BRAM_IMUX32_UTURN_4", + "BRAM_R_IMUX_ADDRBWRADDRL4", + "BRAM_FAN5_1", + "BRAM_FIFO36_DOADOU7", + "BRAM_FIFO18_DIBDI15", + "BRAM_WW2A1_3", + "BRAM_IMUX14_4", + "BRAM_BYP5_1", + "BRAM_RAMB18_DOPADOP0", + "BRAM_FIFO36_ADDRARDADDRL8", + "BRAM_IMUX24_UTURN_1", + "BRAM_FIFO36_ADDRARDADDRU13", + "BRAM_CASCOUT_ADDRBWRADDRU4", + "BRAM_EE4A1_1", + "BRAM_FAN4_1", + "BRAM_R_IMUX_ADDRBWRADDRU14", + "BRAM_FIFO36_ADDRARDADDRU12", + "BRAM_LOGIC_OUTS_B17_3", + "BRAM_FIFO18_DOPBDOP0", + "BRAM_LOGIC_OUTS_B11_1", + "BRAM_RAMB18_WEBWE3", + "BRAM_FIFO36_DOADOL15", + "BRAM_IMUX39_4", + "BRAM_IMUX4_4", + "BRAM_FIFO36_WEBWEL5", + "BRAM_IMUX11_2", + "BRAM_FIFO18_ADDRBWRADDR2", + "BRAM_FIFO18_REGCLKB", + "BRAM_UTURN_ADDRBWRADDRU7", + "BRAM_LOGIC_OUTS_B4_4", + "BRAM_NW4A3_3", + "BRAM_IMUX43_UTURN_0", + "BRAM_IMUX1_0", + "BRAM_WW4END0_0", + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "BRAM_LH7_1", + "BRAM_CLK1_1", + "BRAM_FIFO18_DOBDO7", + "BRAM_IMUX15_4", + "BRAM_EE4BEG3_3", + "BRAM_RAMB18_ADDRBWRADDR10", + "BRAM_FIFO36_RDCOUNT9", + "BRAM_FIFO36_ECCPARITY5", + "BRAM_SW4END3_2", + "BRAM_CASCOUT_ADDRARDADDRU3", + "BRAM_FIFO36_DIADIL11", + "BRAM_UTURN_ADDRARDADDRL8", + "BRAM_IMUX42_UTURN_4", + "BRAM_IMUX22_4", + "BRAM_EE4A0_2", + "BRAM_EE4C3_0", + "BRAM_R_IMUX_ADDRARDADDRL10", + "BRAM_UTURN_ADDRBWRADDRU2", + "BRAM_LH9_1", + "BRAM_FIFO36_DIPBDIPU1", + "BRAM_NE4C3_0", + "BRAM_IMUX43_3", + "BRAM_WW4C1_0", + "BRAM_SE4C3_0", + "BRAM_WW2END0_3", + "BRAM_PMVBRAM_ODIV4", + "BRAM_SE2A1_1", + "BRAM_IMUX40_1", + "BRAM_RAMB18_ADDRBWRADDR11", + "BRAM_EE4B2_0", + "BRAM_IMUX9_1", + "BRAM_FAN3_1", + "BRAM_R_IMUX_ADDRARDADDRL1", + "BRAM_MONITOR_P_2", + "BRAM_ADDRBWRADDRL0", + "BRAM_RAMB18_DOBDO9", + "BRAM_FIFO18_DIBDI11", + "BRAM_FIFO18_WEBWE6", + "BRAM_IMUX6_UTURN_0", + "BRAM_FIFO36_ADDRBWRADDRU13", + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "BRAM_IMUX29_2", + "BRAM_RAMB18_DIADI14", + "BRAM_IMUX2_UTURN_0", + "BRAM_SE4C0_0", + "BRAM_LOGIC_OUTS_B18_0", + "BRAM_RAMB18_ADDRBWRADDR3", + "BRAM_R_IMUX_ADDRBWRADDRL3", + "BRAM_CASCINBOT_ADDRARDADDRU12", + "BRAM_IMUX8_UTURN_1", + "BRAM_LOGIC_OUTS_B1_3", + "BRAM_IMUX45_UTURN_2", + "BRAM_RAMB18_DIADI9", + "BRAM_WW2A0_4", + "BRAM_IMUX5_UTURN_2", + "BRAM_EE4B2_1", + "BRAM_CASCINTOP_ADDRARDADDRU9", + "BRAM_LOGIC_OUTS_B21_4", + "BRAM_NW2A3_2", + "BRAM_NW2A1_4", + "BRAM_IMUX33_UTURN_0", + "BRAM_LOGIC_OUTS_B15_0", + "BRAM_IMUX46_UTURN_2", + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "BRAM_RAMB18_RSTREGB", + "BRAM_EE4A1_2", + "BRAM_NE4C0_0", + "BRAM_IMUX7_3", + "BRAM_IMUX40_UTURN_3", + "BRAM_LOGIC_OUTS_B23_1", + "BRAM_IMUX0_UTURN_4", + "BRAM_NE4C2_1", + "BRAM_IMUX13_UTURN_2", + "BRAM_ADDRBWRADDRL11", + "BRAM_RAMB18_DOADO14", + "BRAM_LOGIC_OUTS_B14_2", + "BRAM_IMUX3_3", + "BRAM_SW4A3_3", + "BRAM_LOGIC_OUTS_B14_0", + "BRAM_FIFO36_DOBDOL5", + "BRAM_FIFO36_DOPADOPU0", + "BRAM_WW4B1_4", + "BRAM_EE4C1_1", + "BRAM_ADDRARDADDRU4", + "BRAM_EL1BEG2_4", + "BRAM_FIFO36_ECCPARITY4", + "BRAM_EE2BEG0_3", + "BRAM_FIFO18_DIADI15", + "BRAM_WW4A1_3", + "BRAM_IMUX47_UTURN_3", + "BRAM_FIFO36_ADDRBWRADDRL0", + "BRAM_IMUX17_4", + "BRAM_UTURN_ADDRARDADDRU10", + "BRAM_LH10_4", + "BRAM_FIFO18_WRCOUNT4", + "BRAM_NW4A2_3", + "BRAM_ADDRBWRADDRL10", + "BRAM_LOGIC_OUTS_B19_2", + "BRAM_NE4C3_2", + "BRAM_IMUX9_4", + "BRAM_FIFO36_DOBDOL7", + "BRAM_IMUX33_3", + "BRAM_IMUX14_3", + "BRAM_IMUX20_0", + "BRAM_WW4B1_0", + "BRAM_WW4END3_2", + "BRAM_FIFO36_TSTWROS9", + "BRAM_IMUX32_0", + "BRAM_EE2BEG1_0", + "BRAM_IMUX32_UTURN_3", + "BRAM_FIFO36_ADDRBWRADDRL12", + "BRAM_LH2_2", + "BRAM_LOGIC_OUTS_B23_2", + "BRAM_WW4END2_2", + "BRAM_LOGIC_OUTS_B20_0", + "BRAM_NE4BEG2_4", + "BRAM_WW4A0_4", + "BRAM_SW2A3_4", + "BRAM_IMUX18_UTURN_1", + "BRAM_FIFO18_DOBDO5", + "BRAM_SE4BEG0_1", + "BRAM_WL1END1_3", + "BRAM_RAMB18_DIADI11", + "BRAM_BYP6_3", + "BRAM_FIFO36_DIBDIU9", + "BRAM_BYP4_4", + "BRAM_IMUX15_UTURN_3", + "BRAM_LH9_3", + "BRAM_IMUX43_0", + "BRAM_FIFO36_REGCLKBU", + "BRAM_FIFO18_RDCOUNT1", + "BRAM_IMUX37_4", + "BRAM_FIFO36_TSTCNT5", + "BRAM_IMUX42_2", + "BRAM_IMUX22_UTURN_1", + "BRAM_WW4C2_3", + "BRAM_WR1END1_1", + "BRAM_EE4A0_1", + "BRAM_FAN2_2", + "BRAM_EE4C2_4", + "BRAM_IMUX19_1", + "BRAM_SW4A0_0", + "BRAM_IMUX7_UTURN_3", + "BRAM_IMUX42_4", + "BRAM_NE2A2_2", + "BRAM_FIFO18_DIADI9", + "BRAM_LOGIC_OUTS_B11_2", + "BRAM_IMUX24_1", + "BRAM_BLOCK_OUTS_L_B3_4", + "BRAM_IMUX30_UTURN_1", + "BRAM_RAMB18_WRCOUNT0", + "BRAM_SE4C1_3", + "BRAM_CASCOUT_ADDRARDADDRU10", + "BRAM_RAMB18_RDCOUNT7", + "BRAM_FIFO36_CASCADEOUTB", + "BRAM_SW4A1_3", + "BRAM_FIFO36_ADDRARDADDRU10", + "BRAM_FAN5_2", + "BRAM_SW2A2_4", + "BRAM_UTURN_ADDRARDADDRL0", + "BRAM_UTURN_ADDRBWRADDRL7", + "BRAM_IMUX37_0", + "BRAM_IMUX26_UTURN_3", + "BRAM_IMUX16_0", + "BRAM_EE4C0_3", + "BRAM_FIFO36_TSTWROS11", + "BRAM_FIFO36_WRCOUNT5", + "BRAM_IMUX36_2", + "BRAM_FIFO36_DOADOL1", + "BRAM_NE2A3_3", + "BRAM_UTURN_ADDRBWRADDRL1", + "BRAM_CASCINTOP_ADDRARDADDRU13", + "BRAM_CASCINBOT_ADDRARDADDRU13", + "BRAM_FIFO18_DIBDI4", + "BRAM_IMUX13_1", + "BRAM_LOGIC_OUTS_B21_3", + "BRAM_FIFO36_RSTREGARSTREGU", + "BRAM_EE4A2_4", + "BRAM_FIFO36_DIADIU3", + "BRAM_RAMB18_RDCOUNT9", + "BRAM_SW4A2_3", + "BRAM_R_IMUX_ADDRARDADDRU8", + "BRAM_R_IMUX_ADDRARDADDRU11", + "BRAM_UTURN_ADDRARDADDRU8", + "BRAM_ADDRARDADDRL2", + "BRAM_FIFO36_ECCPARITY1", + "BRAM_IMUX41_0", + "BRAM_BYP1_1", + "BRAM_FIFO18_RDCOUNT0", + "BRAM_IMUX37_2", + "BRAM_FIFO36_DIBDIU5", + "BRAM_FIFO18_ADDRBWRADDR6", + "BRAM_RAMB18_DOADO15", + "BRAM_FIFO18_ADDRBWRADDR13", + "BRAM_WR1END2_3", + "BRAM_FIFO18_RDCOUNT7", + "BRAM_IMUX13_UTURN_3", + "BRAM_WR1END3_1", + "BRAM_UTURN_ADDRARDADDRL12", + "BRAM_RAMB18_WEA1", + "BRAM_FIFO36_ADDRBWRADDRU3", + "BRAM_WW2A0_0", + "BRAM_IMUX0_3", + "BRAM_RAMB18_DIADI15", + "BRAM_ER1BEG2_4", + "BRAM_FIFO36_DOADOU15", + "BRAM_LH2_1", + "BRAM_WL1END0_3", + "BRAM_IMUX47_2", + "BRAM_SE2A2_0", + "BRAM_LH7_4", + "BRAM_EE4C1_3", + "BRAM_EE4A3_0", + "BRAM_EE4A2_3", + "BRAM_NW4END2_0", + "BRAM_FIFO36_DIADIU8", + "BRAM_WW4C3_3", + "BRAM_WR1END2_0", + "BRAM_R_IMUX_ADDRARDADDRL8", + "BRAM_NE2A1_3", + "BRAM_IMUX38_1", + "BRAM_FIFO18_RSTREGARSTREG", + "BRAM_CASCINTOP_ADDRARDADDRU5", + "BRAM_RAMB18_DIBDI8", + "BRAM_FIFO36_RSTREGBL", + "BRAM_IMUX32_1", + "BRAM_IMUX28_4", + "BRAM_IMUX19_3", + "BRAM_LOGIC_OUTS_B11_4", + "BRAM_RAMB18_DOBDO0", + "BRAM_CASCOUT_ADDRARDADDRU11", + "BRAM_SW4A2_4", + "BRAM_RAMB18_DOPBDOP1", + "BRAM_EE2BEG1_2", + "BRAM_EE4BEG3_4", + "BRAM_FIFO36_TSTRDOS6", + "BRAM_EL1BEG3_2", + "BRAM_LOGIC_OUTS_B12_2", + "BRAM_NW2A0_3", + "BRAM_SW2A0_1", + "BRAM_R_IMUX_ADDRARDADDRL9", + "BRAM_IMUX32_UTURN_0", + "BRAM_FIFO36_RDCOUNT0", + "BRAM_WR1END3_3", + "BRAM_SW4END2_1", + "BRAM_BYP4_1", + "BRAM_IMUX20_UTURN_1", + "BRAM_BYP6_0", + "BRAM_IMUX45_UTURN_4", + "BRAM_FIFO36_ADDRBWRADDRU5", + "BRAM_CASCOUT_ADDRBWRADDRU6", + "BRAM_SW2A1_0", + "BRAM_IMUX42_UTURN_1", + "BRAM_SE4BEG0_4", + "BRAM_LH10_0", + "BRAM_ADDRBWRADDRL1", + "BRAM_FIFO36_DIADIU10", + "BRAM_FIFO36_REGCEBU", + "BRAM_LOGIC_OUTS_B1_4", + "BRAM_ER1BEG1_1", + "BRAM_FIFO36_DOBDOU8", + "BRAM_FIFO18_ADDRARDADDR11", + "BRAM_IMUX11_0", + "BRAM_WW4B3_4", + "BRAM_IMUX38_0", + "BRAM_EE4BEG2_0", + "BRAM_CASCOUT_ADDRARDADDRU2", + "BRAM_R_IMUX_ADDRBWRADDRU6", + "BRAM_R_IMUX_ADDRBWRADDRL2", + "BRAM_RAMB18_DIPBDIP0", + "BRAM_FIFO36_TSTOUT4", + "BRAM_FIFO36_DIADIL4", + "BRAM_FIFO36_DIBDIL8", + "BRAM_EE2A2_1", + "BRAM_FIFO18_DIPBDIP0", + "BRAM_FIFO18_CLKBWRCLK", + "BRAM_IMUX33_UTURN_4", + "BRAM_IMUX11_4", + "BRAM_RAMB18_ADDRBTIEHIGH0", + "BRAM_IMUX9_UTURN_0", + "BRAM_CASCOUT_ADDRARDADDRU1", + "BRAM_BLOCK_OUTS_L_B3_1", + "BRAM_FIFO18_RDERR", + "BRAM_ADDRBWRADDRU9", + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "BRAM_SW2A1_4", + "BRAM_FIFO18_ADDRBWRADDR10", + "BRAM_FIFO36_DIADIU9", + "BRAM_FIFO18_ADDRARDADDR5", + "BRAM_IMUX11_UTURN_4", + "BRAM_FIFO18_ADDRARDADDR12", + "BRAM_IMUX12_2", + "BRAM_FAN4_0", + "BRAM_FIFO36_DIADIU12", + "BRAM_RAMB18_WEBWE1", + "BRAM_FIFO36_ADDRARDADDRL15", + "BRAM_FAN2_1", + "BRAM_BLOCK_OUTS_L_B0_2", + "BRAM_RAMB18_RDCOUNT11", + "BRAM_EE2A0_1", + "BRAM_IMUX0_UTURN_0", + "BRAM_IMUX45_3", + "BRAM_FIFO18_DOADO13", + "BRAM_IMUX7_UTURN_1", + "BRAM_FIFO36_ADDRARDADDRU1", + "BRAM_RAMB18_WRCOUNT1", + "BRAM_ADDRARDADDRL10", + "BRAM_IMUX45_UTURN_0", + "BRAM_FIFO36_ECCPARITY0", + "BRAM_IMUX38_UTURN_1", + "BRAM_FIFO36_TSTRDOS1", + "BRAM_FIFO36_TSTCNT6", + "BRAM_FIFO36_RSTREGARSTREGL", + "BRAM_FIFO18_DIADI8", + "BRAM_WL1END1_4", + "BRAM_ER1BEG1_4", + "BRAM_WR1END3_0", + "BRAM_FIFO18_DOADO5", + "BRAM_FIFO36_CLKBWRCLKL", + "BRAM_FIFO36_TSTWROS12", + "BRAM_IMUX39_UTURN_0", + "BRAM_IMUX22_UTURN_3", + "BRAM_FIFO36_DIADIL15", + "BRAM_IMUX19_UTURN_1", + "BRAM_FAN6_3", + "BRAM_SE2A3_3", + "BRAM_IMUX4_UTURN_2", + "BRAM_ADDRBWRADDRU6", + "BRAM_FIFO36_REGCEBL", + "BRAM_LOGIC_OUTS_B21_2", + "BRAM_IMUX25_UTURN_0", + "BRAM_FIFO36_DIADIU11", + "BRAM_R_IMUX_ADDRBWRADDRL7", + "BRAM_LOGIC_OUTS_B16_4", + "BRAM_FIFO36_TSTRDOS2", + "BRAM_RAMB18_DOADO5", + "BRAM_EE2A2_2", + "BRAM_IMUX41_3", + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "BRAM_EL1BEG0_1", + "BRAM_LH8_3", + "BRAM_ER1BEG1_2", + "BRAM_EE2A3_4", + "BRAM_FIFO36_ADDRARDADDRL4", + "BRAM_NW4A3_4", + "BRAM_FIFO36_DOADOL6", + "BRAM_NW4A1_2", + "BRAM_IMUX0_UTURN_1", + "BRAM_IMUX12_UTURN_4", + "BRAM_LOGIC_OUTS_B14_1", + "BRAM_WW4C0_1", + "BRAM_UTURN_ADDRBWRADDRU1", + "BRAM_FIFO36_RSTREGBU", + "BRAM_WW2A0_1", + "BRAM_CASCOUT_ADDRBWRADDRU5", + "BRAM_FIFO36_ADDRBWRADDRL4", + "BRAM_LOGIC_OUTS_B11_0", + "BRAM_ADDRARDADDRL12", + "BRAM_IMUX18_UTURN_4", + "BRAM_WW2END2_3", + "BRAM_IMUX38_3", + "BRAM_FIFO36_TSTRDOS0", + "BRAM_FIFO36_CASCADEOUTB_1", + "BRAM_NE2A3_2", + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "BRAM_IMUX10_1", + "BRAM_WL1END3_1", + "BRAM_LH4_3", + "BRAM_IMUX10_UTURN_0", + "BRAM_SW2A2_1", + "BRAM_SE4BEG3_2", + "BRAM_FIFO36_DIADIU13", + "BRAM_CASCINBOT_ADDRARDADDRU10", + "BRAM_IMUX11_1", + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "BRAM_RAMB18_ADDRBWRADDR8", + "BRAM_NW4END0_1", + "BRAM_EE2A3_3", + "BRAM_FIFO36_ADDRBWRADDRL13", + "BRAM_RAMB18_ADDRATIEHIGH0", + "BRAM_ADDRARDADDRL6", + "BRAM_NW2A2_4", + "BRAM_FIFO36_ADDRBWRADDRU7", + "BRAM_FIFO18_DOADO11", + "BRAM_FIFO18_RDCOUNT3", + "BRAM_IMUX27_2", + "BRAM_FIFO36_DOBDOL3", + "BRAM_IMUX42_3", + "BRAM_EE4C1_0", + "BRAM_IMUX40_0", + "BRAM_LOGIC_OUTS_B8_1", + "BRAM_SE4C3_4", + "BRAM_FIFO36_DIADIL6", + "BRAM_CASCINTOP_ADDRARDADDRU10", + "BRAM_ADDRBWRADDRL3", + "BRAM_ADDRBWRADDRU3", + "BRAM_FIFO36_ADDRBWRADDRU0", + "BRAM_IMUX17_UTURN_2", + "BRAM_RAMB18_RDCOUNT6", + "BRAM_UTURN_ADDRBWRADDRU5", + "BRAM_IMUX37_3", + "BRAM_ADDRARDADDRU5", + "BRAM_WW4C3_4", + "BRAM_FIFO36_TSTCNT3", + "BRAM_RAMB18_ADDRARDADDR4", + "BRAM_WW2A1_4", + "BRAM_SW4A0_4", + "BRAM_IMUX2_UTURN_3", + "BRAM_RAMB18_DOADO9", + "BRAM_ADDRARDADDRU0", + "BRAM_EE2A3_2", + "BRAM_IMUX43_1", + "BRAM_IMUX33_4", + "BRAM_FIFO36_ADDRARDADDRL12", + "BRAM_IMUX19_UTURN_3", + "BRAM_IMUX1_UTURN_4", + "BRAM_FIFO18_ADDRARDADDR10", + "BRAM_FIFO18_WEBWE4", + "BRAM_SW4A1_2", + "BRAM_R_IMUX_ADDRBWRADDRL0", + "BRAM_NE4C1_1", + "BRAM_FIFO18_ADDRBWRADDR4", + "BRAM_NW2A3_4", + "BRAM_LOGIC_OUTS_B22_2", + "BRAM_IMUX38_4", + "BRAM_EE2A2_3", + "BRAM_FIFO36_ADDRARDADDRU7", + "BRAM_IMUX26_UTURN_1", + "BRAM_FIFO36_EMPTY", + "BRAM_FIFO18_RDCOUNT9", + "BRAM_LH4_4", + "BRAM_RAMB18_EMPTY", + "BRAM_RAMB18_DIBDI11", + "BRAM_SE4BEG2_3", + "BRAM_RAMB18_DOBDO7", + "BRAM_BYP3_4", + "BRAM_EE4B0_2", + "BRAM_FIFO18_DOBDO2", + "BRAM_FIFO18_DOADO3", + "BRAM_IMUX39_0", + "BRAM_FIFO36_ENBWRENL", + "BRAM_WW4END2_3", + "BRAM_SE2A2_3", + "BRAM_FIFO36_DIPADIPU0", + "BRAM_NW2A0_0", + "BRAM_UTURN_ADDRARDADDRL9", + "BRAM_LOGIC_OUTS_B12_4", + "BRAM_BYP0_1", + "BRAM_WW4END1_0", + "BRAM_FIFO18_ADDRBWRADDR9", + "BRAM_RAMB18_ADDRARDADDR13", + "BRAM_CLK1_4", + "BRAM_ADDRARDADDRU7", + "BRAM_SW4END2_3", + "BRAM_LOGIC_OUTS_B0_2", + "BRAM_SE4BEG2_2", + "BRAM_IMUX43_UTURN_2", + "BRAM_WW4A3_0", + "BRAM_FIFO36_DIADIL3", + "BRAM_IMUX18_0", + "BRAM_FIFO36_DOADOU14", + "BRAM_FIFO18_DIBDI0", + "BRAM_NE2A0_4", + "BRAM_EL1BEG0_4", + "BRAM_RAMB18_DOBDO11", + "BRAM_FIFO36_WRCOUNT12", + "BRAM_SW4END1_0", + "BRAM_ADDRARDADDRL14", + "BRAM_FIFO18_DOPBDOP1", + "BRAM_LOGIC_OUTS_B6_2", + "BRAM_IMUX39_UTURN_1", + "BRAM_FIFO36_ADDRARDADDRL13", + "BRAM_IMUX8_0", + "BRAM_WW4C2_4", + "BRAM_CASCINTOP_ADDRARDADDRU3", + "BRAM_SE2A0_1", + "BRAM_WW2A3_0", + "BRAM_IMUX22_UTURN_2", + "BRAM_IMUX24_2", + "BRAM_RAMB18_DOPADOP1", + "BRAM_WW4C3_0", + "BRAM_WW2A2_0", + "BRAM_EE4A3_1", + "BRAM_FIFO18_REGCLKARDRCLK", + "BRAM_LOGIC_OUTS_B5_3", + "BRAM_UTURN_ADDRARDADDRL5", + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "BRAM_IMUX4_3", + "BRAM_IMUX31_UTURN_4", + "BRAM_LOGIC_OUTS_B8_4", + "BRAM_LOGIC_OUTS_B12_1", + "BRAM_FIFO36_DOPADOPL1", + "BRAM_EE4C2_1", + "BRAM_IMUX37_UTURN_4", + "BRAM_IMUX25_UTURN_1", + "BRAM_WW4END1_1", + "BRAM_LOGIC_OUTS_B15_4", + "BRAM_FIFO18_RDCOUNT5", + "BRAM_LOGIC_OUTS_B6_1", + "BRAM_SE4C1_2", + "BRAM_IMUX5_UTURN_1", + "BRAM_FIFO36_DIADIU4", + "BRAM_MONITOR_N_2", + "BRAM_NE2A1_1", + "BRAM_CTRL1_3", + "BRAM_IMUX35_UTURN_0", + "BRAM_WW4C2_1", + "BRAM_IMUX26_0", + "BRAM_ADDRBWRADDRU13", + "BRAM_NW4A1_0", + "BRAM_IMUX46_3", + "BRAM_EE4BEG1_3", + "BRAM_UTURN_ADDRARDADDRL15", + "BRAM_IMUX1_3", + "BRAM_RAMB18_REGCLKARDRCLK", + "BRAM_UTURN_ADDRARDADDRL11", + "BRAM_RAMB18_ADDRARDADDR8", + "BRAM_WW4A0_2", + "BRAM_IMUX35_1", + "BRAM_LOGIC_OUTS_B19_0", + "BRAM_IMUX13_4", + "BRAM_FIFO36_WRCOUNT7", + "BRAM_ADDRBWRADDRL7", + "BRAM_IMUX11_UTURN_2", + "BRAM_EL1BEG1_0", + "BRAM_NE4BEG3_3", + "BRAM_CLK0_2", + "BRAM_FIFO36_WRCOUNT10", + "BRAM_FIFO36_ADDRARDADDRU14", + "BRAM_R_IMUX_ADDRBWRADDRL1", + "BRAM_LOGIC_OUTS_B12_3", + "BRAM_IMUX1_4", + "BRAM_NE4BEG0_0", + "BRAM_EE4B0_0", + "BRAM_FIFO36_RSTRAMBL", + "BRAM_UTURN_ADDRBWRADDRL11", + "BRAM_RAMB18_DIBDI10", + "BRAM_UTURN_ADDRBWRADDRU14", + "BRAM_WW2END1_2", + "BRAM_IMUX27_UTURN_3", + "BRAM_WW2A3_1", + "BRAM_IMUX41_UTURN_0", + "BRAM_FIFO36_DIBDIL3", + "BRAM_NE4C3_3", + "BRAM_IMUX3_UTURN_4", + "BRAM_IMUX24_UTURN_4", + "BRAM_IMUX39_2", + "BRAM_IMUX13_3", + "BRAM_IMUX44_UTURN_3", + "BRAM_FIFO18_ADDRBWRADDR5", + "BRAM_IMUX1_UTURN_0", + "BRAM_NE4C0_3", + "BRAM_EE4A3_2", + "BRAM_NW4A2_1", + "BRAM_SE4BEG1_2", + "BRAM_NE4BEG0_1", + "BRAM_LH6_4", + "BRAM_IMUX42_UTURN_2", + "BRAM_SE4BEG2_0", + "BRAM_RAMB18_DIBDI1", + "BRAM_WR1END1_2", + "BRAM_FAN3_4", + "BRAM_R_IMUX_ADDRARDADDRU10", + "BRAM_FIFO36_DIADIL2", + "BRAM_UTURN_ADDRBWRADDRL5", + "BRAM_NW4END1_1", + "BRAM_CASCOUT_ADDRBWRADDRU7", + "BRAM_FIFO36_WRCOUNT9", + "BRAM_FIFO36_DOADOL10", + "BRAM_IMUX29_UTURN_1", + "BRAM_IMUX18_1", + "BRAM_RAMB18_WEBWE4", + "BRAM_LOGIC_OUTS_B0_4", + "BRAM_SW4END0_4", + "BRAM_FIFO36_DOADOU12", + "BRAM_IMUX40_UTURN_1", + "BRAM_FIFO18_ADDRBWRADDR11", + "BRAM_IMUX7_UTURN_0", + "BRAM_CASCOUT_ADDRARDADDRU4", + "BRAM_LOGIC_OUTS_B11_3", + "BRAM_FIFO36_DOBDOU13", + "BRAM_SE4BEG3_1", + "BRAM_LOGIC_OUTS_B15_2", + "BRAM_IMUX45_0", + "BRAM_CASCOUT_ADDRBWRADDRU14", + "BRAM_FAN0_4", + "BRAM_EE4B3_3", + "BRAM_FIFO18_ENBWREN", + "BRAM_IMUX14_UTURN_1", + "BRAM_UTURN_ADDRBWRADDRU13", + "BRAM_IMUX44_UTURN_2", + "BRAM_FIFO36_DIBDIL6", + "BRAM_SE2A3_4", + "BRAM_EL1BEG1_2", + "BRAM_IMUX8_UTURN_2", + "BRAM_WL1END2_0", + "BRAM_FIFO36_DIBDIU10", + "BRAM_FIFO36_TSTWROS6", + "BRAM_FIFO36_WRCOUNT4", + "BRAM_IMUX6_UTURN_1", + "BRAM_FIFO18_DOBDO9", + "BRAM_SW2A0_0", + "BRAM_FIFO18_RDCOUNT4", + "BRAM_IMUX0_2", + "BRAM_IMUX30_UTURN_0", + "BRAM_RAMB18_DIPADIP0", + "BRAM_FIFO36_DOADOU8", + "BRAM_UTURN_ADDRARDADDRL13", + "BRAM_IMUX33_1", + "BRAM_NW2A0_4", + "BRAM_IMUX21_UTURN_1", + "BRAM_IMUX30_2", + "BRAM_FIFO36_TSTWROS1", + "BRAM_EE4BEG2_2", + "BRAM_IMUX28_UTURN_3", + "BRAM_FIFO36_RDCOUNT12", + "BRAM_EE4C2_0", + "BRAM_FIFO36_ADDRARDADDRU4", + "BRAM_FIFO36_DOADOL9", + "BRAM_BYP2_2", + "BRAM_FIFO18_ADDRBWRADDR8", + "BRAM_RAMB18_DIBDI14", + "BRAM_EE4B0_3", + "BRAM_FIFO36_WEBWEU0", + "BRAM_PMVBRAM_ODIV2_1", + "BRAM_RAMB18_WEBWE2", + "BRAM_FIFO36_RDCOUNT11", + "BRAM_FIFO18_DIBDI14", + "BRAM_IMUX10_UTURN_2", + "BRAM_LOGIC_OUTS_B17_4", + "BRAM_FIFO36_DIBDIL13", + "BRAM_RAMB18_DIBDI0", + "BRAM_LOGIC_OUTS_B19_4", + "BRAM_UTURN_ADDRARDADDRU13", + "BRAM_FIFO36_RDCOUNT7", + "BRAM_R_IMUX_ADDRARDADDRU0", + "BRAM_IMUX30_3", + "BRAM_FAN5_3", + "BRAM_WL1END2_3", + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "BRAM_FIFO18_DIADI4", + "BRAM_FIFO36_CASCADEINB", + "BRAM_NW4A0_4", + "BRAM_R_IMUX_ADDRARDADDRL6", + "BRAM_FIFO36_RSTRAMARSTRAMLRST", + "BRAM_WR1END2_1", + "BRAM_IMUX21_2", + "BRAM_IMUX28_2", + "BRAM_SW4END0_0", + "BRAM_NE2A0_1", + "BRAM_LOGIC_OUTS_B7_2", + "BRAM_CASCINBOT_ADDRARDADDRU11", + "BRAM_IMUX33_2", + "BRAM_IMUX3_2", + "BRAM_EE4A3_3", + "BRAM_NW4A3_0", + "BRAM_FIFO36_WEAU1", + "BRAM_NW4END2_4", + "BRAM_IMUX12_0", + "BRAM_EE2A1_1", + "BRAM_FIFO36_DIBDIU1", + "BRAM_WW4A2_0", + "BRAM_RAMB18_DIBDI12", + "BRAM_FIFO36_WEBWEU5", + "BRAM_FIFO36_DOBDOL0", + "BRAM_IMUX18_UTURN_0", + "BRAM_FIFO36_DIBDIU4", + "BRAM_FAN3_2", + "BRAM_R_IMUX_ADDRBWRADDRU5", + "BRAM_FIFO36_ECCPARITY6", + "BRAM_NW4END1_0", + "BRAM_IMUX20_UTURN_4", + "BRAM_LOGIC_OUTS_B21_0", + "BRAM_IMUX44_0", + "BRAM_RAMB18_ADDRATIEHIGH1", + "BRAM_IMUX31_UTURN_3", + "BRAM_RAMB18_WRCOUNT4", + "BRAM_FIFO36_DIBDIU3", + "BRAM_FIFO18_DOBDO8", + "BRAM_RAMB18_ADDRARDADDR11", + "BRAM_LOGIC_OUTS_B20_2", + "BRAM_IMUX39_1", + "BRAM_FIFO18_ADDRARDADDR1", + "BRAM_RAMB18_DIBDI4", + "BRAM_NE2A2_4", + "BRAM_ADDRARDADDRU8", + "BRAM_FIFO18_ADDRBTIEHIGH0", + "BRAM_WR1END1_3", + "BRAM_IMUX40_4", + "BRAM_EE4C2_2", + "BRAM_RAMB18_RDCOUNT4", + "BRAM_BYP6_1", + "BRAM_IMUX1_UTURN_3", + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "BRAM_WW2END3_3", + "BRAM_IMUX34_UTURN_3", + "BRAM_CASCINTOP_ADDRARDADDRU2", + "BRAM_ER1BEG0_4", + "BRAM_FIFO36_ADDRARDADDRU3", + "BRAM_LOGIC_OUTS_B7_0", + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "BRAM_EE4BEG2_4", + "BRAM_FIFO36_DOBDOU11", + "BRAM_BYP3_2", + "BRAM_FIFO36_DOPADOPU1", + "BRAM_IMUX18_UTURN_2", + "BRAM_BYP2_3", + "BRAM_ER1BEG2_1", + "BRAM_IMUX27_UTURN_0", + "BRAM_FIFO36_DIBDIU7", + "BRAM_LH3_0", + "BRAM_IMUX2_UTURN_4", + "BRAM_IMUX45_1", + "BRAM_ADDRBWRADDRU10", + "BRAM_FIFO36_ADDRBWRADDRU2", + "BRAM_FIFO36_DIBDIL12", + "BRAM_EE4BEG3_1", + "BRAM_FIFO36_TSTWROS4", + "BRAM_RAMB18_DOADO3", + "BRAM_IMUX23_UTURN_1", + "BRAM_FIFO36_ADDRBWRADDRL11", + "BRAM_UTURN_ADDRARDADDRU5", + "BRAM_NW2A2_3", + "BRAM_RAMB18_DOADO2", + "BRAM_LOGIC_OUTS_B18_2", + "BRAM_FIFO36_ADDRBWRADDRU9", + "BRAM_LOGIC_OUTS_B1_1", + "BRAM_IMUX27_UTURN_2", + "BRAM_FIFO36_TSTIN0", + "BRAM_IMUX28_UTURN_4", + "BRAM_IMUX23_UTURN_0", + "BRAM_EE2A0_4", + "BRAM_WW2END3_0", + "BRAM_WW4B1_3", + "BRAM_FIFO36_DIPADIPL1", + "BRAM_SE4C1_4", + "BRAM_FIFO36_DIADIU5", + "BRAM_EE4BEG0_0", + "BRAM_IMUX26_UTURN_2", + "BRAM_IMUX28_3", + "BRAM_ADDRARDADDRL4", + "BRAM_LOGIC_OUTS_B3_3", + "BRAM_FIFO36_DIADIL7", + "BRAM_IMUX36_UTURN_1", + "BRAM_CASCOUT_ADDRBWRADDRU0", + "BRAM_IMUX33_UTURN_2", + "BRAM_FIFO36_DOBDOU3", + "BRAM_RAMB18_WRCOUNT3", + "BRAM_SW4A3_2", + "BRAM_EE2A0_2", + "BRAM_R_IMUX_ADDRARDADDRU12", + "BRAM_WW2END0_2", + "BRAM_RAMB18_ADDRBWRADDR0", + "BRAM_FIFO18_DIBDI2", + "BRAM_BYP1_4", + "BRAM_IMUX39_UTURN_4", + "BRAM_BLOCK_OUTS_L_B2_1", + "BRAM_R_IMUX_ADDRBWRADDRL6", + "BRAM_CASCOUT_ADDRARDADDRU14", + "BRAM_MONITOR_N_3", + "BRAM_FIFO36_DOADOL11", + "BRAM_RAMB18_WEBWE6", + "BRAM_FIFO36_RDERR", + "BRAM_IMUX20_4", + "BRAM_CASCINBOT_ADDRARDADDRU6", + "BRAM_LOGIC_OUTS_B23_4", + "BRAM_IMUX27_1", + "BRAM_UTURN_ADDRARDADDRL1", + "BRAM_BYP7_4", + "BRAM_FIFO18_DOBDO11", + "BRAM_IMUX19_UTURN_2", + "BRAM_WW4END0_3", + "BRAM_NE2A3_4", + "BRAM_IMUX21_3", + "BRAM_RAMB18_ALMOSTEMPTY", + "BRAM_EE4B2_4", + "BRAM_WR1END0_0", + "BRAM_FIFO18_DIADI13", + "BRAM_FAN7_2", + "BRAM_IMUX4_0", + "BRAM_EE4A2_2", + "BRAM_FIFO18_DOADO7", + "BRAM_LH11_2", + "BRAM_BYP2_4", + "BRAM_LH2_0", + "BRAM_IMUX43_UTURN_1", + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "BRAM_BYP3_0", + "BRAM_WW4END1_3", + "BRAM_LOGIC_OUTS_B22_1", + "BRAM_SW4A2_1", + "BRAM_FIFO18_WEA0", + "BRAM_WW4A3_3", + "BRAM_FAN7_3", + "BRAM_FIFO18_DIPBDIP1", + "BRAM_FIFO36_DIBDIL0", + "BRAM_NW4END1_4", + "BRAM_BYP4_3", + "BRAM_IMUX44_UTURN_4", + "BRAM_CLK0_1", + "BRAM_UTURN_ADDRBWRADDRU9", + "BRAM_R_IMUX_ADDRARDADDRL0", + "BRAM_FIFO18_DIADI10", + "BRAM_WW4END3_3", + "BRAM_IMUX40_2", + "BRAM_ER1BEG1_3", + "BRAM_RAMB18_ADDRARDADDR5", + "BRAM_IMUX22_3", + "BRAM_RAMB18_RDCOUNT10", + "BRAM_WW4B2_2", + "BRAM_EE4B2_2", + "BRAM_IMUX37_UTURN_2", + "BRAM_LOGIC_OUTS_B6_0", + "BRAM_FIFO18_RSTRAMB", + "BRAM_NW2A1_3", + "BRAM_IMUX23_3", + "BRAM_FIFO36_TSTBRAMRST", + "BRAM_FIFO18_WEBWE2", + "BRAM_IMUX9_UTURN_3", + "BRAM_FIFO18_DOBDO10", + "BRAM_FIFO36_WRCOUNT3", + "BRAM_CTRL1_4", + "BRAM_NE4C1_2", + "BRAM_WW4A1_0", + "BRAM_IMUX32_3", + "BRAM_FIFO36_DOADOU5", + "BRAM_SW4END3_3", + "BRAM_SW4A1_0", + "BRAM_EL1BEG2_3", + "BRAM_RAMB18_REGCEB", + "BRAM_FIFO36_DOADOL7", + "BRAM_RAMB18_ADDRBWRADDR1", + "BRAM_SE2A2_2", + "BRAM_IMUX2_4", + "BRAM_SW4END1_4", + "BRAM_EE4BEG2_3", + "BRAM_FIFO36_DOBDOU5", + "BRAM_FIFO18_DIADI5", + "BRAM_FIFO36_DOADOL4", + "BRAM_LH1_3", + "BRAM_FIFO36_DOBDOL4", + "BRAM_LOGIC_OUTS_B16_1", + "BRAM_EE2BEG0_0", + "BRAM_FIFO18_WEBWE0", + "BRAM_FIFO36_TSTCNT10", + "BRAM_IMUX11_UTURN_0", + "BRAM_RAMB18_DIADI5", + "BRAM_WW2A0_2", + "BRAM_FIFO18_DOBDO4", + "BRAM_FIFO36_ADDRARDADDRL9", + "BRAM_R_IMUX_ADDRARDADDRL11", + "BRAM_WL1END3_3", + "BRAM_BYP1_0", + "BRAM_UTURN_ADDRBWRADDRL2", + "BRAM_WW4C1_1", + "BRAM_IMUX29_UTURN_2", + "BRAM_RAMB18_RSTREGARSTREG", + "BRAM_FIFO36_RSTRAMBU", + "BRAM_IMUX3_0", + "BRAM_IMUX37_1", + "BRAM_EE2BEG1_4", + "BRAM_SE4BEG2_1", + "BRAM_UTURN_ADDRARDADDRL2", + "BRAM_FAN0_3", + "BRAM_IMUX21_0", + "BRAM_FIFO18_WRCOUNT5", + "BRAM_FIFO36_TSTWROS5", + "BRAM_FIFO36_DIADIU14", + "BRAM_FIFO36_ECCPARITY3", + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "BRAM_IMUX22_2", + "BRAM_WL1END3_4", + "BRAM_SW2A1_3", + "BRAM_LOGIC_OUTS_B4_3", + "BRAM_BLOCK_OUTS_L_B0_4", + "BRAM_R_IMUX_ADDRARDADDRU13", + "BRAM_FIFO36_DOPBDOPU1", + "BRAM_FIFO36_TSTRDCNTOFF", + "BRAM_FIFO36_ADDRBWRADDRL14", + "BRAM_LOGIC_OUTS_B10_1", + "BRAM_IMUX17_UTURN_1", + "BRAM_RAMB18_DIBDI7", + "BRAM_FIFO36_ADDRARDADDRU9", + "BRAM_EE4BEG1_4", + "BRAM_IMUX3_UTURN_0", + "BRAM_FIFO36_TSTRDOS4", + "BRAM_WW4C2_0", + "BRAM_IMUX15_UTURN_1", + "BRAM_FIFO18_DOBDO13", + "BRAM_FIFO36_ADDRARDADDRL0", + "BRAM_WW4C0_3", + "BRAM_EE2BEG0_4", + "BRAM_LOGIC_OUTS_B17_2", + "BRAM_IMUX36_UTURN_0", + "BRAM_ADDRARDADDRL5", + "BRAM_EE4B3_4", + "BRAM_NE4BEG0_4", + "BRAM_RAMB18_DIBDI13", + "BRAM_NE4C2_4", + "BRAM_WL1END1_0", + "BRAM_ADDRBWRADDRU0", + "BRAM_NW2A1_1", + "BRAM_RAMB18_DOADO12", + "BRAM_CTRL0_1", + "BRAM_RAMB18_DOBDO6", + "BRAM_FIFO36_ADDRARDADDRL11", + "BRAM_SW2A1_2", + "BRAM_R_IMUX_ADDRARDADDRU9", + "BRAM_IMUX10_3", + "BRAM_SW4A1_1", + "BRAM_BLOCK_OUTS_L_B3_2", + "BRAM_BLOCK_OUTS_L_B0_0", + "BRAM_LOGIC_OUTS_B13_4", + "BRAM_EE2BEG3_3", + "BRAM_ADDRARDADDRU14", + "BRAM_FIFO36_DOADOL5", + "BRAM_FAN6_0", + "BRAM_FAN2_0", + "BRAM_FAN1_3", + "BRAM_UTURN_ADDRBWRADDRL9", + "BRAM_LH8_2", + "BRAM_MONITOR_P_3", + "BRAM_FIFO36_RDCOUNT1", + "BRAM_R_IMUX_ADDRARDADDRL5", + "BRAM_FIFO36_DIADIL0", + "BRAM_BLOCK_OUTS_L_B2_0", + "BRAM_FIFO18_DIADI14", + "BRAM_FIFO36_DIBDIU2", + "BRAM_RAMB18_DOBDO2", + "BRAM_IMUX30_UTURN_3", + "BRAM_FIFO18_DOADO6", + "BRAM_LH8_4", + "BRAM_FIFO18_DOADO10", + "BRAM_RAMB18_ADDRARDADDR6", + "BRAM_FIFO18_DOBDO3", + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "BRAM_FIFO18_WRCOUNT3", + "BRAM_FIFO18_DIADI3", + "BRAM_SW4A2_0", + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "BRAM_WW4END0_2", + "BRAM_IMUX0_1", + "BRAM_LH12_3", + "BRAM_FIFO36_TSTCNT7", + "BRAM_SE4BEG0_3", + "BRAM_FIFO18_ALMOSTEMPTY", + "BRAM_ADDRBWRADDRL5", + "BRAM_IMUX46_UTURN_1", + "BRAM_FIFO36_WEBWEL3", + "BRAM_IMUX46_4", + "BRAM_RAMB18_REGCEAREGCE", + "BRAM_FIFO36_DOBDOL11", + "BRAM_SE4C2_3", + "BRAM_NE2A2_1", + "BRAM_FAN4_2", + "BRAM_FIFO36_ADDRBWRADDRL9", + "BRAM_IMUX34_2", + "BRAM_FIFO18_RDCOUNT10", + "BRAM_FIFO36_TSTCNT12", + "BRAM_WL1END3_0", + "BRAM_WW2A1_1", + "BRAM_RAMB18_ADDRARDADDR9", + "BRAM_FIFO18_WRCOUNT6", + "BRAM_IMUX11_3", + "BRAM_ADDRBWRADDRU12", + "BRAM_IMUX17_2", + "BRAM_WW4B0_0", + "BRAM_UTURN_ADDRBWRADDRL0", + "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRAM_MONITOR_P_1", + "BRAM_EE4B1_3", + "BRAM_FIFO18_DIADI2", + "BRAM_FAN6_1", + "BRAM_IMUX8_UTURN_0", + "BRAM_SW4A3_1", + "BRAM_RAMB18_DIPADIP1", + "BRAM_ER1BEG1_0", + "BRAM_LOGIC_OUTS_B22_4", + "BRAM_EE4BEG3_2", + "BRAM_IMUX17_3", + "BRAM_CASCOUT_ADDRBWRADDRU2", + "BRAM_SW2A3_1", + "BRAM_WW4END1_2", + "BRAM_EE2A1_4", + "BRAM_IMUX18_3", + "BRAM_WW4A3_4", + "BRAM_IMUX22_1", + "BRAM_RAMB18_WEA0", + "BRAM_FIFO18_DIBDI1", + "BRAM_LH11_1", + "BRAM_BYP7_1", + "BRAM_FIFO36_DIBDIL5", + "BRAM_NE4BEG0_3", + "BRAM_FAN1_1", + "BRAM_FIFO36_DOPADOPL0", + "BRAM_WW2END0_0", + "BRAM_IMUX24_UTURN_2", + "BRAM_CLK1_2", + "BRAM_LOGIC_OUTS_B3_2", + "BRAM_RAMB18_DOADO11", + "BRAM_IMUX2_UTURN_2", + "BRAM_IMUX15_0", + "BRAM_IMUX6_UTURN_4", + "BRAM_IMUX36_UTURN_4", + "BRAM_FIFO36_DIADIL12", + "BRAM_FIFO36_RDCOUNT5", + "BRAM_RAMB18_ENARDEN", + "BRAM_IMUX27_3", + "BRAM_FIFO36_DOADOL12", + "BRAM_IMUX5_UTURN_4", + "BRAM_SW4END3_0", + "BRAM_RAMB18_WEBWE7", + "BRAM_IMUX1_2", + "BRAM_IMUX46_2", + "BRAM_IMUX45_UTURN_3", + "BRAM_WW4B1_2", + "BRAM_IMUX28_UTURN_0", + "BRAM_IMUX20_2", + "BRAM_LH9_0", + "BRAM_IMUX32_2", + "BRAM_FIFO36_DOADOL3", + "BRAM_CASCOUT_ADDRARDADDRU9", + "BRAM_FAN5_4", + "BRAM_IMUX6_1", + "BRAM_LOGIC_OUTS_B3_0", + "BRAM_WW2END3_1", + "BRAM_SW2A0_2", + "BRAM_FIFO36_ADDRBWRADDRU10", + "BRAM_SE4C0_1", + "BRAM_FAN7_1", + "BRAM_IMUX14_UTURN_3", + "BRAM_RAMB18_DIADI8", + "BRAM_R_IMUX_ADDRARDADDRL13", + "BRAM_FIFO36_TSTCNT11", + "BRAM_CASCOUT_ADDRBWRADDRU8", + "BRAM_FIFO18_DIADI6", + "BRAM_LH10_1", + "BRAM_LOGIC_OUTS_B18_3", + "BRAM_FIFO36_REGCLKARDRCLKU", + "BRAM_FIFO36_WEBWEL6", + "BRAM_SW4END2_4", + "BRAM_CASCINBOT_ADDRARDADDRU1", + "BRAM_RAMB18_ADDRBWRADDR5", + "BRAM_FIFO36_ADDRARDADDRL14", + "BRAM_SW2A1_1", + "BRAM_FIFO18_RDCOUNT11", + "BRAM_IMUX12_UTURN_3", + "BRAM_IMUX16_4", + "BRAM_UTURN_ADDRARDADDRU14", + "BRAM_NE2A3_1", + "BRAM_UTURN_ADDRARDADDRU7", + "BRAM_CASCOUT_ADDRARDADDRU7", + "BRAM_SW4A0_2", + "BRAM_LOGIC_OUTS_B19_3", + "BRAM_IMUX46_UTURN_3", + "BRAM_IMUX18_2", + "BRAM_ADDRARDADDRU13", + "BRAM_FIFO18_RSTRAMARSTRAM", + "BRAM_RAMB18_DOBDO1", + "BRAM_FIFO18_DOADO1", + "BRAM_FIFO36_WEBWEU1", + "BRAM_FAN6_4", + "BRAM_NW4A1_3", + "BRAM_FIFO36_ENARDENL", + "BRAM_NW2A2_2", + "BRAM_IMUX20_UTURN_2", + "BRAM_FIFO36_ADDRBWRADDRU1", + "BRAM_FIFO18_DOBDO12", + "BRAM_ADDRBWRADDRU5", + "BRAM_ADDRBWRADDRU2", + "BRAM_FIFO36_ENBWRENU", + "BRAM_LH11_3", + "BRAM_RAMB18_ADDRBWRADDR7", + "BRAM_LOGIC_OUTS_B6_4", + "BRAM_LH10_3", + "BRAM_NW2A3_0", + "BRAM_EL1BEG1_1", + "BRAM_LH3_3", + "BRAM_FIFO36_ALMOSTEMPTY", + "BRAM_IMUX41_UTURN_1", + "BRAM_EE2BEG3_2", + "BRAM_R_IMUX_ADDRBWRADDRU0", + "BRAM_IMUX38_UTURN_0", + "BRAM_FIFO36_RDCOUNT10", + "BRAM_LOGIC_OUTS_B0_0", + "BRAM_FIFO36_ADDRARDADDRU11", + "BRAM_NW4END3_3", + "BRAM_FIFO36_DOBDOL13", + "BRAM_ER1BEG2_0", + "BRAM_ADDRBWRADDRL6", + "BRAM_IMUX47_UTURN_1", + "BRAM_FIFO36_DOADOU2", + "BRAM_FIFO36_CLKARDCLKU", + "BRAM_FIFO36_DIPADIPU1", + "BRAM_FIFO36_DIBDIU12", + "BRAM_IMUX8_3", + "BRAM_EE4B1_0", + "BRAM_FIFO36_ADDRARDADDRU2", + "BRAM_NW2A0_2", + "BRAM_SW2A3_0", + "BRAM_BYP0_3", + "BRAM_NW4END0_0", + "BRAM_FIFO36_DOBDOL1", + "BRAM_IMUX19_0", + "BRAM_BLOCK_OUTS_L_B1_4", + "BRAM_LOGIC_OUTS_B9_1", + "BRAM_WW4END3_1", + "BRAM_IMUX44_2", + "BRAM_FIFO18_DIPADIP1", + "BRAM_IMUX21_UTURN_3", + "BRAM_IMUX17_0", + "BRAM_PMVBRAM_ODIV2", + "BRAM_RAMB18_ADDRARDADDR3", + "BRAM_IMUX45_2", + "BRAM_EE4BEG0_2", + "BRAM_NW2A2_1", + "BRAM_NE2A3_0", + "BRAM_LOGIC_OUTS_B12_0", + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "BRAM_FIFO36_WEAL0", + "BRAM_FIFO18_EMPTY", + "BRAM_ADDRARDADDRL11", + "BRAM_WW4END0_4", + "BRAM_WL1END3_2", + "BRAM_RAMB18_RDCOUNT0", + "BRAM_EE4C0_0", + "BRAM_IMUX35_UTURN_1", + "BRAM_IMUX29_0", + "BRAM_FIFO18_ADDRBTIEHIGH1", + "BRAM_WW4A2_3", + "BRAM_IMUX33_UTURN_3", + "BRAM_UTURN_ADDRARDADDRU9", + "BRAM_WW4A2_1", + "BRAM_EE4B0_4", + "BRAM_LH12_0", + "BRAM_FIFO36_TSTWROS7", + "BRAM_FAN4_3", + "BRAM_LOGIC_OUTS_B13_0", + "BRAM_IMUX14_UTURN_4", + "BRAM_EE4B1_1", + "BRAM_RAMB18_DOBDO12", + "BRAM_RAMB18_DIADI1", + "BRAM_IMUX32_UTURN_1", + "BRAM_IMUX35_0", + "BRAM_FIFO18_WRCOUNT8", + "BRAM_SE4C3_1", + "BRAM_WW4C2_2", + "BRAM_FAN1_0", + "BRAM_CASCINBOT_ADDRARDADDRU2", + "BRAM_IMUX34_UTURN_0", + "BRAM_RAMB18_DOBDO15", + "BRAM_IMUX6_3", + "BRAM_UTURN_ADDRBWRADDRU4", + "BRAM_LH8_1", + "BRAM_IMUX35_4", + "BRAM_LH5_0", + "BRAM_IMUX8_4", + "BRAM_ER1BEG3_4", + "BRAM_IMUX29_UTURN_3", + "BRAM_IMUX13_UTURN_1", + "BRAM_EE4A0_3", + "BRAM_IMUX5_4", + "BRAM_FIFO36_TSTWROS8", + "BRAM_FIFO36_DOBDOU2", + "BRAM_IMUX37_UTURN_1", + "BRAM_EE2A2_4", + "BRAM_FIFO18_WRCOUNT2", + "BRAM_SW4END3_1", + "BRAM_FIFO36_DIBDIL4", + "BRAM_R_IMUX_ADDRARDADDRL12", + "BRAM_R_IMUX_ADDRARDADDRU6", + "BRAM_SE4BEG3_3", + "BRAM_FIFO18_DOPADOP1", + "BRAM_WW4A2_4", + "BRAM_WW4A1_2", + "BRAM_CASCOUT_ADDRARDADDRU6", + "BRAM_FIFO36_DOBDOL6", + "BRAM_RAMB18_ADDRARDADDR2", + "BRAM_IMUX10_2", + "BRAM_FIFO36_CLKBWRCLKU", + "BRAM_FIFO36_DOBDOU0", + "BRAM_IMUX31_0", + "BRAM_R_IMUX_ADDRBWRADDRU7", + "BRAM_EE2BEG3_0", + "BRAM_IMUX5_UTURN_3", + "BRAM_FIFO36_ECCPARITY2", + "BRAM_WL1END0_0", + "BRAM_NE4BEG1_0", + "BRAM_EL1BEG3_3", + "BRAM_EE4BEG0_4", + "BRAM_FIFO36_DIBDIU6", + "BRAM_IMUX17_UTURN_0", + "BRAM_LOGIC_OUTS_B23_0", + "BRAM_SW4END0_2", + "BRAM_LOGIC_OUTS_B8_0", + "BRAM_UTURN_ADDRBWRADDRU8", + "BRAM_SW2A2_0", + "BRAM_IMUX16_3", + "BRAM_IMUX23_0", + "BRAM_SE2A0_0", + "BRAM_BYP5_3", + "BRAM_IMUX16_UTURN_3", + "BRAM_FIFO36_DOADOL0", + "BRAM_RAMB18_ENBWREN", + "BRAM_IMUX16_UTURN_2", + "BRAM_ER1BEG0_0", + "BRAM_IMUX6_4", + "BRAM_EE4B3_2", + "BRAM_IMUX17_1", + "BRAM_FIFO36_TSTOFF", + "BRAM_FIFO36_DOADOU11", + "BRAM_CASCINBOT_ADDRARDADDRU3", + "BRAM_FIFO18_DOADO2", + "BRAM_LOGIC_OUTS_B22_3", + "BRAM_IMUX31_UTURN_0", + "BRAM_LOGIC_OUTS_B8_2", + "BRAM_FAN0_0", + "BRAM_WR1END1_4", + "BRAM_LOGIC_OUTS_B17_1", + "BRAM_FIFO18_FULL", + "BRAM_FIFO18_WEBWE1", + "BRAM_IMUX34_3", + "BRAM_IMUX12_1", + "BRAM_WR1END0_3", + "BRAM_NW4END3_1", + "BRAM_FIFO36_TSTOUT2", + "BRAM_LOGIC_OUTS_B2_4", + "BRAM_R_IMUX_ADDRBWRADDRU10", + "BRAM_IMUX11_UTURN_3", + "BRAM_SW4END1_3", + "BRAM_UTURN_ADDRARDADDRU11", + "BRAM_WW2END0_1", + "BRAM_FIFO36_DOBDOL2", + "BRAM_LH5_1", + "BRAM_IMUX17_UTURN_4", + "BRAM_SE2A0_2", + "BRAM_WW4B0_1", + "BRAM_UTURN_ADDRBWRADDRU0", + "BRAM_FIFO36_WEAU2", + "BRAM_FIFO36_REGCEAREGCEU", + "BRAM_LOGIC_OUTS_B9_3", + "BRAM_EE2BEG3_1", + "BRAM_R_IMUX_ADDRBWRADDRU8", + "BRAM_LH5_4", + "BRAM_IMUX2_0", + "BRAM_RAMB18_FULL", + "BRAM_EE4BEG1_0", + "BRAM_ER1BEG0_1", + "BRAM_RAMB18_DOADO4", + "BRAM_NW4A1_4", + "BRAM_IMUX22_UTURN_4", + "BRAM_FIFO36_DOBDOL9", + "BRAM_FIFO18_WRCOUNT10", + "BRAM_WW4B3_1", + "BRAM_NE4BEG2_1", + "BRAM_CASCOUT_ADDRARDADDRU13", + "BRAM_IMUX4_2", + "BRAM_IMUX30_UTURN_4", + "BRAM_LOGIC_OUTS_B8_3", + "BRAM_CLK1_0", + "BRAM_LOGIC_OUTS_B20_4", + "BRAM_FIFO36_DIADIL10", + "BRAM_EE2A1_0", + "BRAM_RAMB18_CLKARDCLK", + "BRAM_IMUX19_4", + "BRAM_R_IMUX_ADDRBWRADDRL11", + "BRAM_IMUX14_2", + "BRAM_ADDRARDADDRU12", + "BRAM_R_IMUX_ADDRARDADDRL14", + "BRAM_RAMB18_RDCOUNT5", + "BRAM_LOGIC_OUTS_B7_4", + "BRAM_LOGIC_OUTS_B18_1", + "BRAM_FIFO36_TSTRDOS3", + "BRAM_LH4_1", + "BRAM_IMUX27_0", + "BRAM_FIFO36_RDCOUNT8", + "BRAM_LH12_2", + "BRAM_FIFO36_WRCOUNT6", + "BRAM_IMUX43_4", + "BRAM_RAMB18_DOBDO14", + "BRAM_RAMB18_DOBDO10", + "BRAM_IMUX25_1", + "BRAM_SW4END2_2", + "BRAM_IMUX38_UTURN_4", + "BRAM_FIFO18_DIBDI3", + "BRAM_BLOCK_OUTS_L_B0_3", + "BRAM_IMUX9_3", + "BRAM_IMUX23_UTURN_4", + "BRAM_RAMB18_DOADO10", + "BRAM_RAMB18_DIADI12", + "BRAM_WR1END3_4", + "BRAM_R_IMUX_ADDRARDADDRU4", + "BRAM_PMVBRAM_SELECT2", + "BRAM_R_IMUX_ADDRARDADDRL2", + "BRAM_FIFO36_DIADIU7", + "BRAM_FIFO18_DOADO14", + "BRAM_SE4C3_3", + "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRAM_CASCOUT_ADDRBWRADDRU10", + "BRAM_IMUX0_4", + "BRAM_IMUX36_UTURN_3", + "BRAM_LOGIC_OUTS_B15_1", + "BRAM_CASCINBOT_ADDRARDADDRU5", + "BRAM_IMUX0_0", + "BRAM_BYP3_1", + "BRAM_FIFO36_TSTCNT8", + "BRAM_LOGIC_OUTS_B14_3", + "BRAM_RAMB18_WRCOUNT10", + "BRAM_SW4END1_2", + "BRAM_FIFO36_ADDRBWRADDRL6", + "BRAM_NE2A0_3", + "BRAM_FIFO36_CASCADEOUTA_1", + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "BRAM_IMUX35_UTURN_3", + "BRAM_NE4BEG1_4", + "BRAM_MONITOR_P_0", + "BRAM_EE4BEG1_1", + "BRAM_FIFO36_DOBDOU12", + "BRAM_RAMB18_ADDRBWRADDR4", + "BRAM_PMVBRAM_SELECT4", + "BRAM_LH10_2", + "BRAM_FIFO36_DIBDIU14", + "BRAM_NE4C3_1", + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "BRAM_ADDRARDADDRU3", + "BRAM_FIFO36_DIBDIL14", + "BRAM_ADDRBWRADDRL8", + "BRAM_ADDRARDADDRU2", + "BRAM_NW4A2_4", + "BRAM_NE2A0_2", + "BRAM_WW4B2_4", + "BRAM_RAMB18_DIADI0", + "BRAM_EE4B1_2", + "BRAM_FAN1_2", + "BRAM_FIFO36_CASCADEINA", + "BRAM_ADDRBWRADDRL4", + "BRAM_UTURN_ADDRARDADDRL14", + "BRAM_CASCOUT_ADDRBWRADDRU11", + "BRAM_LOGIC_OUTS_B7_1", + "BRAM_FIFO36_DIBDIU13", + "BRAM_IMUX15_1", + "BRAM_NE2A1_4", + "BRAM_ADDRBWRADDRL2", + "BRAM_FIFO36_ADDRBWRADDRU8", + "BRAM_FIFO36_ADDRBWRADDRL5", + "BRAM_NW4A3_2", + "BRAM_WW4C1_2", + "BRAM_LOGIC_OUTS_B13_2", + "BRAM_WW4A0_0", + "BRAM_FIFO18_REGCEB", + "BRAM_R_IMUX_ADDRARDADDRL7", + "BRAM_FIFO36_TSTCNT4", + "BRAM_FIFO36_REGCLKBL", + "BRAM_LOGIC_OUTS_B4_2", + "BRAM_RAMB18_WRCOUNT7", + "BRAM_RAMB18_DOADO1", + "BRAM_IMUX44_1", + "BRAM_ADDRBWRADDRL12", + "BRAM_FIFO18_ADDRARDADDR7", + "BRAM_FIFO36_TSTWROS0", + "BRAM_SE2A3_1", + "BRAM_IMUX7_0", + "BRAM_EE4C0_2", + "BRAM_IMUX17_UTURN_3", + "BRAM_UTURN_ADDRBWRADDRU10", + "BRAM_WW4END2_0", + "BRAM_LOGIC_OUTS_B2_1", + "BRAM_IMUX_R_ADDRARDADDRL15", + "BRAM_FIFO36_DOPBDOPU0", + "BRAM_RAMB18_WRCOUNT9", + "BRAM_ADDRARDADDRL13", + "BRAM_EL1BEG2_2", + "BRAM_WW4B1_1", + "BRAM_FIFO36_DIADIU1", + "BRAM_R_IMUX_ADDRARDADDRL3", + "BRAM_WW4A0_3", + "BRAM_RAMB18_ALMOSTFULL", + "BRAM_IMUX12_UTURN_0", + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "BRAM_BLOCK_OUTS_L_B1_0", + "BRAM_BLOCK_OUTS_L_B0_1", + "BRAM_R_IMUX_ADDRBWRADDRU9", + "BRAM_EE4C1_4", + "BRAM_IMUX12_UTURN_1", + "BRAM_IMUX35_3", + "BRAM_NE4C0_4", + "BRAM_BYP5_2", + "BRAM_FAN3_0", + "BRAM_FIFO36_DIBDIL11", + "BRAM_SW2A3_3", + "BRAM_FIFO36_ADDRARDADDRU8", + "BRAM_LH8_0", + "BRAM_IMUX4_UTURN_4", + "BRAM_FIFO36_WRCOUNT11", + "BRAM_LOGIC_OUTS_B5_4", + "BRAM_FIFO36_DIBDIL10", + "BRAM_NE4BEG0_2", + "BRAM_IMUX47_3", + "BRAM_LOGIC_OUTS_B16_0", + "BRAM_IMUX24_4", + "BRAM_FAN3_3", + "BRAM_FIFO18_ADDRARDADDR2", + "BRAM_FIFO36_DOBDOL8", + "BRAM_FIFO36_INJECTSBITERR", + "BRAM_FIFO36_REGCEAREGCEL", + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "BRAM_IMUX20_3", + "BRAM_IMUX35_UTURN_2", + "BRAM_RAMB18_RSTRAMB", + "BRAM_IMUX29_4", + "BRAM_SE2A3_2", + "BRAM_FIFO36_DOBDOL12", + "BRAM_BYP5_4", + "BRAM_SE4C3_2", + "BRAM_ADDRARDADDRU9", + "BRAM_CASCOUT_ADDRBWRADDRU12", + "BRAM_IMUX39_UTURN_2", + "BRAM_FIFO36_ADDRARDADDRU0", + "BRAM_IMUX15_UTURN_4", + "BRAM_FIFO18_DOADO9", + "BRAM_IMUX42_0", + "BRAM_RAMB18_DIADI6", + "BRAM_ADDRBWRADDRL9", + "BRAM_FIFO18_ADDRARDADDR9", + "BRAM_FIFO18_DOADO8", + "BRAM_SW4END1_1", + "BRAM_WW2A1_2", + "BRAM_FIFO18_DOADO12", + "BRAM_CASCINBOT_ADDRARDADDRU9", + "BRAM_IMUX7_2", + "BRAM_UTURN_ADDRARDADDRL4", + "BRAM_BYP3_3", + "BRAM_FIFO36_TSTRDOS7", + "BRAM_FIFO36_RDCOUNT2", + "BRAM_FIFO18_DIBDI8", + "BRAM_ADDRBWRADDRU1", + "BRAM_IMUX35_UTURN_4", + "BRAM_IMUX46_0", + "BRAM_LOGIC_OUTS_B17_0", + "BRAM_IMUX10_UTURN_1", + "BRAM_SE2A2_4", + "BRAM_IMUX43_2", + "BRAM_IMUX9_0", + "BRAM_RAMB18_ADDRARDADDR1", + "BRAM_FIFO36_TSTFLAGIN", + "BRAM_FIFO36_DOPBDOPL0", + "BRAM_EL1BEG2_1", + "BRAM_FIFO18_WEBWE7", + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "BRAM_R_IMUX_ADDRBWRADDRL8", + "BRAM_SW4END0_3", + "BRAM_IMUX27_UTURN_1", + "BRAM_UTURN_ADDRARDADDRU6", + "BRAM_CASCINBOT_ADDRARDADDRU8", + "BRAM_UTURN_ADDRBWRADDRU11", + "BRAM_FIFO18_DOPADOP0", + "BRAM_SE4C2_0", + "BRAM_SE4C0_3", + "BRAM_NE4BEG2_3", + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "BRAM_R_IMUX_ADDRBWRADDRU13", + "BRAM_LOGIC_OUTS_B3_1", + "BRAM_IMUX6_UTURN_2", + "BRAM_LOGIC_OUTS_B14_4", + "BRAM_FIFO36_ADDRBWRADDRL2", + "BRAM_EE4A0_0", + "BRAM_EE2BEG2_3", + "BRAM_LH11_4", + "BRAM_IMUX25_UTURN_2", + "BRAM_ADDRBWRADDRU7", + "BRAM_FIFO36_DOBDOU10", + "BRAM_LOGIC_OUTS_B5_0", + "BRAM_IMUX14_UTURN_0", + "BRAM_NE4C1_4", + "BRAM_SE2A0_4", + "BRAM_NE4BEG2_2", + "BRAM_FAN7_0", + "BRAM_SW4END3_4", + "BRAM_IMUX23_UTURN_3", + "BRAM_WW4A1_1", + "BRAM_LH12_4", + "BRAM_EE4C0_4", + "BRAM_FIFO18_WEBWE3", + "BRAM_SE4C0_2", + "BRAM_FIFO36_DOADOL8", + "BRAM_FIFO36_TSTRDOS11", + "BRAM_IMUX10_UTURN_4", + "BRAM_WW4B0_2", + "BRAM_FIFO18_ADDRATIEHIGH1", + "BRAM_FIFO18_ADDRARDADDR3", + "BRAM_IMUX24_UTURN_3", + "BRAM_IMUX38_2", + "BRAM_WW4B0_4", + "BRAM_WW4C1_3", + "BRAM_IMUX36_UTURN_2", + "BRAM_CTRL0_3", + "BRAM_SE4BEG1_4", + "BRAM_FIFO36_SBITERR", + "BRAM_IMUX41_1", + "BRAM_LOGIC_OUTS_B10_0", + "BRAM_R_IMUX_ADDRARDADDRU2", + "BRAM_FIFO36_TSTCNT1", + "BRAM_IMUX7_UTURN_2", + "BRAM_IMUX7_4", + "BRAM_FIFO36_TSTRDOS8", + "BRAM_IMUX3_1", + "BRAM_WW2END1_3", + "BRAM_WW2A3_3", + "BRAM_WW4B2_0", + "BRAM_RAMB18_DIADI2", + "BRAM_ER1BEG3_0", + "BRAM_WW2END3_4", + "BRAM_ADDRBWRADDRL14", + "BRAM_SE4BEG3_0", + "BRAM_RAMB18_RSTRAMARSTRAM", + "BRAM_FIFO18_DOADO15", + "BRAM_ER1BEG0_3", + "BRAM_FIFO36_ADDRBWRADDRU4", + "BRAM_FIFO18_WEA2", + "BRAM_FIFO36_ALMOSTFULL", + "BRAM_WL1END2_1", + "BRAM_NE4BEG3_0", + "BRAM_RAMB18_DOBDO5", + "BRAM_FIFO18_DIBDI7", + "BRAM_RAMB18_DIBDI15", + "BRAM_IMUX4_UTURN_3", + "BRAM_NW4A0_2", + "BRAM_FIFO18_WRERR", + "BRAM_FIFO36_WEBWEL4", + "BRAM_SE2A1_0", + "BRAM_CASCINBOT_ADDRARDADDRU14", + "BRAM_IMUX4_UTURN_1", + "BRAM_FIFO36_WEBWEL2", + "BRAM_PMVBRAM_O_2", + "BRAM_EE2BEG0_1", + "BRAM_IMUX5_1", + "BRAM_IMUX21_4", + "BRAM_FIFO36_TSTRDOS9", + "BRAM_LH7_2", + "BRAM_FIFO36_WEBWEU4", + "BRAM_ADDRBWRADDRU11", + "BRAM_IMUX12_UTURN_2", + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "BRAM_NW2A1_0", + "BRAM_RAMB18_DIBDI6", + "BRAM_IMUX20_UTURN_0", + "BRAM_IMUX41_4", + "BRAM_WW2END2_2", + "BRAM_MONITOR_P_4", + "BRAM_EE2A1_2", + "BRAM_BLOCK_OUTS_L_B1_1", + "BRAM_RAMB18_DIBDI5", + "BRAM_FIFO36_DIADIL14", + "BRAM_ER1BEG0_2", + "BRAM_FIFO36_WEBWEU6", + "BRAM_IMUX10_UTURN_3", + "BRAM_UTURN_ADDRARDADDRU1", + "BRAM_PMVBRAM_O", + "BRAM_LOGIC_OUTS_B1_2", + "BRAM_WR1END0_1", + "BRAM_FIFO18_WEA3", + "BRAM_IMUX45_4", + "BRAM_WW2A0_3", + "BRAM_LOGIC_OUTS_B1_0", + "BRAM_IMUX23_1", + "BRAM_FIFO36_TSTCNT9", + "BRAM_UTURN_ADDRBWRADDRL15", + "BRAM_NE4C0_1", + "BRAM_IMUX20_UTURN_3", + "BRAM_BYP2_0", + "BRAM_CASCOUT_ADDRBWRADDRU9", + "BRAM_FIFO36_DIADIU2", + "BRAM_RAMB18_DIADI10", + "BRAM_LOGIC_OUTS_B10_3", + "BRAM_IMUX14_1", + "BRAM_WW4B0_3", + "BRAM_FIFO36_WRCOUNT1", + "BRAM_IMUX31_UTURN_2", + "BRAM_FIFO36_DIBDIL15", + "BRAM_IMUX0_UTURN_3", + "BRAM_CLK0_0", + "BRAM_WW2A2_3", + "BRAM_WW4END3_0", + "BRAM_R_IMUX_ADDRBWRADDRU1", + "BRAM_FIFO36_DIPBDIPU0", + "BRAM_LH7_0", + "BRAM_IMUX47_UTURN_0", + "BRAM_FIFO18_DIADI11", + "BRAM_IMUX25_4", + "BRAM_IMUX26_1", + "BRAM_MONITOR_N_0", + "BRAM_WW4B3_3", + "BRAM_CLK1_3", + "BRAM_RAMB18_DIADI7", + "BRAM_CTRL1_2", + "BRAM_LOGIC_OUTS_B10_2", + "BRAM_IMUX42_UTURN_0", + "BRAM_NE2A2_0", + "BRAM_WR1END0_4", + "BRAM_FIFO18_REGCEAREGCE", + "BRAM_FAN4_4", + "BRAM_LOGIC_OUTS_B0_3", + "BRAM_PMVBRAM_SELECT1", + "BRAM_IMUX34_1", + "BRAM_EL1BEG0_2", + "BRAM_UTURN_ADDRBWRADDRL4", + "BRAM_FIFO18_RDCOUNT2", + "BRAM_RAMB18_DIBDI3", + "BRAM_LH1_2", + "BRAM_FIFO18_WEA1", + "BRAM_EE4A1_4", + "BRAM_EL1BEG3_0", + "BRAM_IMUX28_UTURN_2", + "BRAM_R_IMUX_ADDRARDADDRL4", + "BRAM_IMUX15_2", + "BRAM_EE4BEG0_1", + "BRAM_RAMB18_RDCOUNT3", + "BRAM_IMUX46_1", + "BRAM_RAMB18_REGCLKB", + "BRAM_IMUX15_UTURN_2", + "BRAM_EE4A1_0", + "BRAM_FIFO18_DIADI1", + "BRAM_RAMB18_ADDRBWRADDR12", + "BRAM_R_IMUX_ADDRARDADDRU7", + "BRAM_LH1_1", + "BRAM_IMUX2_UTURN_1", + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "BRAM_LOGIC_OUTS_B13_3", + "BRAM_FIFO18_WRCOUNT9", + "BRAM_FIFO18_RDCOUNT8", + "BRAM_FIFO18_ADDRBWRADDR0", + "BRAM_LH7_3", + "BRAM_NE4C2_3", + "BRAM_NE4BEG3_1", + "BRAM_NW4END1_2", + "BRAM_IMUX23_4", + "BRAM_EE4A2_0", + "BRAM_FIFO18_WRCOUNT0", + "BRAM_RAMB18_WRCOUNT2", + "BRAM_LH3_4", + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "BRAM_FIFO36_DOADOL13", + "BRAM_LOGIC_OUTS_B16_2", + "BRAM_FIFO36_TSTOUT3", + "BRAM_IMUX25_2", + "BRAM_SE4C1_1", + "BRAM_LOGIC_OUTS_B20_3", + "BRAM_FIFO18_ADDRBWRADDR7", + "BRAM_NW2A3_3", + "BRAM_WW2END2_0", + "BRAM_IMUX19_2", + "BRAM_ADDRARDADDRL1", + "BRAM_NW2A3_1", + "BRAM_FIFO18_DIADI12", + "BRAM_EE2A0_3", + "BRAM_EE4B1_4", + "BRAM_ADDRARDADDRU11", + "BRAM_CASCOUT_ADDRARDADDRU0", + "BRAM_UTURN_ADDRBWRADDRU12", + "BRAM_EE4BEG3_0", + "BRAM_SE4BEG0_2", + "BRAM_FIFO36_DOADOU4", + "BRAM_ADDRARDADDRL7", + "BRAM_WR1END1_0", + "BRAM_LOGIC_OUTS_B3_4", + "BRAM_BLOCK_OUTS_L_B3_0", + "BRAM_IMUX29_UTURN_0", + "BRAM_IMUX2_2", + "BRAM_EE4C1_2", + "BRAM_IMUX14_0", + "BRAM_RAMB18_DIBDI2", + "BRAM_IMUX13_UTURN_0", + "BRAM_CASCINBOT_ADDRARDADDRU0", + "BRAM_WW2A2_4", + "BRAM_IMUX37_UTURN_3", + "BRAM_RAMB18_DOADO7", + "BRAM_FIFO36_ADDRARDADDRU5", + "BRAM_IMUX29_UTURN_4", + "BRAM_WW2A3_4", + "BRAM_BLOCK_OUTS_L_B1_2", + "BRAM_FIFO36_DIBDIU0", + "BRAM_BYP0_0", + "BRAM_FIFO36_TSTRDOS10", + "BRAM_NE4C3_4", + "BRAM_LH2_4", + "BRAM_RAMB18_DOBDO3", + "BRAM_LOGIC_OUTS_B2_3", + "BRAM_BYP7_0", + "BRAM_FIFO36_ADDRBWRADDRU14", + "BRAM_IMUX47_0", + "BRAM_CASCOUT_ADDRARDADDRU5", + "BRAM_FIFO36_TSTIN1", + "BRAM_FIFO36_DOBDOL15", + "BRAM_SE4C2_2", + "BRAM_RAMB18_WRCOUNT6", + "BRAM_FIFO18_DOBDO1", + "BRAM_SW4A0_1", + "BRAM_FIFO36_REGCLKARDRCLKL", + "BRAM_FIFO36_RSTRAMARSTRAMU", + "BRAM_UTURN_ADDRARDADDRU4", + "BRAM_PMVBRAM_O_1", + "BRAM_RAMB18_RDERR", + "BRAM_NW4END2_2", + "BRAM_IMUX34_UTURN_2", + "BRAM_R_IMUX_ADDRBWRADDRL9", + "BRAM_FIFO36_WEBWEU3", + "BRAM_IMUX30_0", + "BRAM_IMUX19_UTURN_4", + "BRAM_IMUX8_1", + "BRAM_ER1BEG2_3", + "BRAM_EE4A3_4", + "BRAM_IMUX33_UTURN_1", + "BRAM_NE4C0_2", + "BRAM_UTURN_ADDRARDADDRU12", + "BRAM_RAMB18_WRCOUNT8", + "BRAM_IMUX24_3", + "BRAM_EE2A0_0", + "BRAM_IMUX43_UTURN_3", + "BRAM_R_IMUX_ADDRBWRADDRL13", + "BRAM_RAMB18_WEA3", + "BRAM_IMUX47_1", + "BRAM_IMUX39_3", + "BRAM_IMUX47_UTURN_4", + "BRAM_EL1BEG1_3", + "BRAM_IMUX3_UTURN_2", + "BRAM_FIFO18_ADDRARDADDR6", + "BRAM_NW4A1_1", + "BRAM_RAMB18_ADDRBTIEHIGH1", + "BRAM_IMUX18_4", + "BRAM_CTRL0_2", + "BRAM_NW4A2_2", + "BRAM_NE2A1_2", + "BRAM_LH6_3", + "BRAM_SE4BEG1_0", + "BRAM_FIFO36_CASCADEOUTA", + "BRAM_WW2A2_2", + "BRAM_RAMB18_DIBDI9", + "BRAM_FIFO18_DIADI7", + "BRAM_FIFO36_WEBWEL0", + "BRAM_UTURN_ADDRARDADDRU0", + "BRAM_WL1END0_2", + "BRAM_EL1BEG3_1", + "BRAM_LOGIC_OUTS_B10_4", + "BRAM_FIFO36_TSTRDOS5", + "BRAM_WW2A3_2", + "BRAM_WL1END0_1", + "BRAM_WW4B3_0", + "BRAM_FIFO36_DOBDOU1", + "BRAM_LH5_3", + "BRAM_IMUX30_1", + "BRAM_SE4C1_0", + "BRAM_IMUX40_UTURN_0", + "BRAM_BLOCK_OUTS_L_B1_3", + "BRAM_ADDRBWRADDRL13", + "BRAM_NE4BEG3_2", + "BRAM_WW2A1_0", + "BRAM_WW4END3_4", + "BRAM_ADDRBWRADDRU8", + "BRAM_FIFO18_DOBDO14", + "BRAM_FIFO18_ADDRARDADDR13", + "BRAM_FIFO36_WEAL2", + "BRAM_FIFO36_TSTWROS10", + "BRAM_IMUX42_UTURN_3", + "BRAM_IMUX40_UTURN_2", + "BRAM_FIFO36_WEBWEL7", + "BRAM_IMUX44_4", + "BRAM_RAMB18_WEBWE0", + "BRAM_SE2A2_1", + "BRAM_FIFO36_DIBDIU15", + "BRAM_IMUX25_UTURN_3", + "BRAM_WW4B2_3", + "BRAM_BYP6_2", + "BRAM_RAMB18_DIADI13", + "BRAM_FIFO18_DIPADIP0", + "BRAM_WR1END0_2", + "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRAM_NW4A0_3", + "BRAM_FIFO18_WEBWE5", + "BRAM_RAMB18_ADDRARDADDR12", + "BRAM_RAMB18_WRCOUNT11", + "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRAM_SE2A1_2", + "BRAM_SE2A1_4", + "BRAM_LOGIC_OUTS_B2_2", + "BRAM_IMUX32_UTURN_2", + "BRAM_NE4BEG1_1", + "BRAM_CASCOUT_ADDRBWRADDRU13", + "BRAM_IMUX14_UTURN_2", + "BRAM_FIFO36_ENARDENU", + "BRAM_IMUX22_0", + "BRAM_EE4BEG2_1", + "BRAM_EE4B0_1", + "BRAM_R_IMUX_ADDRARDADDRU5", + "BRAM_RAMB18_WEBWE5", + "BRAM_FIFO36_DOADOU0", + "BRAM_SW4A2_2", + "BRAM_SW4A1_4", + "BRAM_IMUX16_UTURN_4", + "BRAM_UTURN_ADDRBWRADDRL14", + "BRAM_WL1END0_4", + "BRAM_EL1BEG0_0", + "BRAM_NE2A0_0", + "BRAM_RAMB18_CLKBWRCLK", + "BRAM_IMUX29_3", + "BRAM_LOGIC_OUTS_B6_3", + "BRAM_NE4BEG1_3", + "BRAM_IMUX42_1", + "BRAM_FIFO36_ADDRBWRADDRL1", + "BRAM_FAN0_1", + "BRAM_IMUX1_UTURN_1", + "BRAM_WW4A3_1", + "BRAM_IMUX19_UTURN_0", + "BRAM_CASCINBOT_ADDRARDADDRU4", + "BRAM_FIFO36_ADDRARDADDRL2", + "BRAM_BYP2_1", + "BRAM_IMUX34_0", + "BRAM_EL1BEG1_4", + "BRAM_LOGIC_OUTS_B21_1", + "BRAM_IMUX45_UTURN_1", + "BRAM_FIFO36_INJECTDBITERR", + "BRAM_FIFO18_DIBDI6", + "BRAM_LH2_3", + "BRAM_CTRL0_4", + "BRAM_FAN2_4", + "BRAM_RAMB18_ADDRBWRADDR9", + "BRAM_EE4C3_3", + "BRAM_LOGIC_OUTS_B2_0", + "BRAM_NE4C2_2", + "BRAM_ADDRARDADDRU6", + "BRAM_SE2A1_3", + "BRAM_FIFO36_WRCOUNT0", + "BRAM_IMUX30_4", + "BRAM_FAN2_3", + "BRAM_NW4A3_1", + "BRAM_IMUX26_UTURN_0", + "BRAM_FIFO36_WRERR", + "BRAM_RAMB18_ADDRARDADDR0", + "BRAM_WW4C3_2", + "BRAM_FIFO36_TSTIN3", + "BRAM_RAMB18_RDCOUNT1", + "BRAM_FIFO18_CLKARDCLK", + "BRAM_WW4C1_4", + "BRAM_LOGIC_OUTS_B4_1", + "BRAM_ADDRBWRADDRU4", + "BRAM_ER1BEG2_2", + "BRAM_FIFO36_RDCOUNT3", + "BRAM_FIFO36_ECCPARITY7", + "BRAM_IMUX10_4", + "BRAM_BYP1_3", + "BRAM_NW4END3_2", + "BRAM_ADDRBWRADDRU14", + "BRAM_IMUX46_UTURN_4", + "BRAM_LOGIC_OUTS_B15_3", + "BRAM_FIFO18_ALMOSTFULL", + "BRAM_IMUX_R_ADDRBWRADDRL15", + "BRAM_IMUX12_4", + "BRAM_UTURN_ADDRBWRADDRL10", + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "BRAM_BLOCK_OUTS_L_B2_4", + "BRAM_FIFO36_DOBDOU9", + "BRAM_EE4C3_2" + ], + "pips": { + "BRAM_R.BRAM_FIFO18_DOADO0->BRAM_LOGIC_OUTS_B8_0": { + "src_wire": "BRAM_FIFO18_DOADO0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU2->>BRAM_CASCOUT_ADDRBWRADDRU2": { + "src_wire": "BRAM_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX34_0->BRAM_FIFO36_DIBDIL1": { + "src_wire": "BRAM_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX46_2->BRAM_RAMB18_WEBWE7": { + "src_wire": "BRAM_IMUX46_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { + "src_wire": "BRAM_FIFO36_RDCOUNT1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX12_2->BRAM_R_IMUX_ADDRARDADDRU10": { + "src_wire": "BRAM_IMUX12_2", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO6->BRAM_LOGIC_OUTS_B6_4": { + "src_wire": "BRAM_RAMB18_DOBDO6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO10->BRAM_LOGIC_OUTS_B2_0": { + "src_wire": "BRAM_FIFO18_DOADO10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX41_4->BRAM_FIFO36_TSTWROS7": { + "src_wire": "BRAM_IMUX41_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU2->>BRAM_RAMB18_ADDRARDADDR1": { + "src_wire": "BRAM_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX41_2->BRAM_FIFO36_DIADIL15": { + "src_wire": "BRAM_IMUX41_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL14->BRAM_ADDRARDADDRL14": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU12->>BRAM_CASCOUT_ADDRBWRADDRU12": { + "src_wire": "BRAM_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { + "src_wire": "BRAM_FIFO18_WRCOUNT3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK1_4->BRAM_RAMB18_REGCLKARDRCLK": { + "src_wire": "BRAM_CLK1_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCLKARDRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU1->>BRAM_CASCOUT_ADDRARDADDRU1": { + "src_wire": "BRAM_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX43_4->BRAM_FIFO36_TSTWROS9": { + "src_wire": "BRAM_IMUX43_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU4->BRAM_LOGIC_OUTS_B8_4": { + "src_wire": "BRAM_FIFO36_DOADOU4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX14_4->BRAM_RAMB18_DIADI7": { + "src_wire": "BRAM_IMUX14_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX18_0->BRAM_FIFO36_TSTRDOS0": { + "src_wire": "BRAM_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX15_4->BRAM_FIFO36_DIADIU15": { + "src_wire": "BRAM_IMUX15_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU10->BRAM_LOGIC_OUTS_B5_3": { + "src_wire": "BRAM_FIFO36_DOADOU10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL4->BRAM_LOGIC_OUTS_B13_1": { + "src_wire": "BRAM_FIFO36_DOADOL4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY6->BRAM_LOGIC_OUTS_B21_3": { + "src_wire": "BRAM_FIFO36_ECCPARITY6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FAN1_2->BRAM_FIFO36_WEBWEU4": { + "src_wire": "BRAM_FAN1_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX24_1->BRAM_FIFO36_DIBDIU0": { + "src_wire": "BRAM_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX8_4->BRAM_RAMB18_DIADI4": { + "src_wire": "BRAM_IMUX8_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU2->>BRAM_UTURN_ADDRBWRADDRU2": { + "src_wire": "BRAM_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL8->BRAM_ADDRBWRADDRL8": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO2->BRAM_LOGIC_OUTS_B13_3": { + "src_wire": "BRAM_RAMB18_DOADO2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU9->>BRAM_UTURN_ADDRARDADDRU9": { + "src_wire": "BRAM_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { + "src_wire": "BRAM_FIFO36_WRCOUNT8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL4->>BRAM_UTURN_ADDRBWRADDRL4": { + "src_wire": "BRAM_ADDRBWRADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL8->>BRAM_FIFO18_ADDRARDADDR7": { + "src_wire": "BRAM_ADDRARDADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK0_0->BRAM_FIFO18_REGCLKB": { + "src_wire": "BRAM_CLK0_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_RAMB18_ADDRBWRADDR7": { + "src_wire": "BRAM_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX37_2->BRAM_FIFO18_WEBWE2": { + "src_wire": "BRAM_IMUX37_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX41_3->BRAM_RAMB18_DIADI9": { + "src_wire": "BRAM_IMUX41_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX24_4->BRAM_FIFO36_TSTCNT6": { + "src_wire": "BRAM_IMUX24_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX5_2->BRAM_FIFO36_WEBWEL0": { + "src_wire": "BRAM_IMUX5_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL5->>BRAM_FIFO18_ADDRBWRADDR4": { + "src_wire": "BRAM_ADDRBWRADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL1->>BRAM_FIFO18_ADDRARDADDR0": { + "src_wire": "BRAM_ADDRARDADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { + "src_wire": "BRAM_FIFO36_RDCOUNT8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOPADOPL0->BRAM_LOGIC_OUTS_B8_1": { + "src_wire": "BRAM_FIFO36_DOPADOPL0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX32_4->BRAM_FIFO36_TSTRDOS6": { + "src_wire": "BRAM_IMUX32_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO10->BRAM_LOGIC_OUTS_B20_0": { + "src_wire": "BRAM_FIFO18_DOBDO10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL13->>BRAM_FIFO36_ADDRBWRADDRL13": { + "src_wire": "BRAM_ADDRBWRADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL7->BRAM_LOGIC_OUTS_B8_2": { + "src_wire": "BRAM_FIFO36_DOADOL7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO14->BRAM_LOGIC_OUTS_B20_4": { + "src_wire": "BRAM_RAMB18_DOBDO14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX18_4->BRAM_RAMB18_DIBDI5": { + "src_wire": "BRAM_IMUX18_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL7->>BRAM_FIFO36_ADDRARDADDRL7": { + "src_wire": "BRAM_ADDRARDADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL5->>BRAM_FIFO36_ADDRBWRADDRL5": { + "src_wire": "BRAM_ADDRBWRADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL1->BRAM_LOGIC_OUTS_B13_0": { + "src_wire": "BRAM_FIFO36_DOADOL1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU1->>BRAM_UTURN_ADDRBWRADDRU1": { + "src_wire": "BRAM_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU1->>BRAM_RAMB18_ADDRBWRADDR0": { + "src_wire": "BRAM_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU1->BRAM_LOGIC_OUTS_B8_3": { + "src_wire": "BRAM_FIFO36_DOADOU1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL8->BRAM_LOGIC_OUTS_B0_0": { + "src_wire": "BRAM_FIFO36_DOADOL8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU10->>BRAM_UTURN_ADDRARDADDRU10": { + "src_wire": "BRAM_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX38_2->BRAM_FIFO36_WEBWEL6": { + "src_wire": "BRAM_IMUX38_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU10->>BRAM_UTURN_ADDRBWRADDRU10": { + "src_wire": "BRAM_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { + "src_wire": "BRAM_FIFO18_RDCOUNT2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX13_2->BRAM_FIFO36_WEBWEU1": { + "src_wire": "BRAM_IMUX13_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX37_0->BRAM_FIFO18_DIBDI10": { + "src_wire": "BRAM_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX25_2->BRAM_RAMB18_WEA3": { + "src_wire": "BRAM_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX26_2->BRAM_RAMB18_ENBWREN": { + "src_wire": "BRAM_IMUX26_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ENBWREN", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX1_3->BRAM_FIFO36_DIBDIU1": { + "src_wire": "BRAM_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX2_2->BRAM_FIFO18_DIBDI15": { + "src_wire": "BRAM_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU5->>BRAM_RAMB18_ADDRARDADDR4": { + "src_wire": "BRAM_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX12_4->BRAM_FIFO36_DIADIU6": { + "src_wire": "BRAM_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU12->>BRAM_RAMB18_ADDRARDADDR11": { + "src_wire": "BRAM_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX17_3->BRAM_R_IMUX_ADDRARDADDRL7": { + "src_wire": "BRAM_IMUX17_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { + "src_wire": "BRAM_FIFO36_RDCOUNT3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU4->>BRAM_UTURN_ADDRARDADDRU4": { + "src_wire": "BRAM_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX36_0->BRAM_FIFO18_DIBDI2": { + "src_wire": "BRAM_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX25_0->BRAM_FIFO18_DIADI8": { + "src_wire": "BRAM_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU4->>BRAM_RAMB18_ADDRBWRADDR3": { + "src_wire": "BRAM_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX16_3->BRAM_R_IMUX_ADDRARDADDRL6": { + "src_wire": "BRAM_IMUX16_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO11->BRAM_LOGIC_OUTS_B7_0": { + "src_wire": "BRAM_FIFO18_DOADO11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL13->BRAM_ADDRBWRADDRL13": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX44_3->BRAM_FIFO36_DIADIU3": { + "src_wire": "BRAM_IMUX44_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO11->BRAM_LOGIC_OUTS_B2_3": { + "src_wire": "BRAM_RAMB18_DOADO11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU13->>BRAM_CASCOUT_ADDRARDADDRU13": { + "src_wire": "BRAM_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { + "src_wire": "BRAM_FIFO36_ALMOSTFULL", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL1_3->BRAM_FIFO36_RSTRAMARSTRAMU": { + "src_wire": "BRAM_CTRL1_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL0_0->BRAM_FIFO18_RSTREGB": { + "src_wire": "BRAM_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTREGB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX14_4->BRAM_FIFO36_DIADIU7": { + "src_wire": "BRAM_IMUX14_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX23_2->BRAM_RAMB18_DIBDI8": { + "src_wire": "BRAM_IMUX23_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX35_2->BRAM_FIFO18_REGCEB": { + "src_wire": "BRAM_IMUX35_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCEB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO3->BRAM_LOGIC_OUTS_B10_3": { + "src_wire": "BRAM_RAMB18_DOADO3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { + "src_wire": "BRAM_FIFO18_RDCOUNT7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL3->BRAM_LOGIC_OUTS_B3_0": { + "src_wire": "BRAM_FIFO36_DOBDOL3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL1_4->BRAM_RAMB18_RSTREGARSTREG": { + "src_wire": "BRAM_CTRL1_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTREGARSTREG", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { + "src_wire": "BRAM_FIFO18_RDCOUNT3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX42_3->BRAM_RAMB18_DIADI2": { + "src_wire": "BRAM_IMUX42_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX18_4->BRAM_FIFO36_DIBDIU5": { + "src_wire": "BRAM_IMUX18_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL4->>BRAM_FIFO18_ADDRBWRADDR3": { + "src_wire": "BRAM_ADDRBWRADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX8_1->BRAM_RAMB18_DIADI0": { + "src_wire": "BRAM_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX19_4->BRAM_FIFO36_DIBDIU13": { + "src_wire": "BRAM_IMUX19_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX4_3->BRAM_FIFO36_DIBDIU10": { + "src_wire": "BRAM_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK1_1->BRAM_RAMB18_CLKBWRCLK": { + "src_wire": "BRAM_CLK1_1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_CLKBWRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX16_4->BRAM_RAMB18_DIBDI4": { + "src_wire": "BRAM_IMUX16_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX5_2->BRAM_FIFO18_WEBWE0": { + "src_wire": "BRAM_IMUX5_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO13->BRAM_LOGIC_OUTS_B20_1": { + "src_wire": "BRAM_FIFO18_DOBDO13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU5->>BRAM_CASCOUT_ADDRBWRADDRU5": { + "src_wire": "BRAM_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_RAMB18_ADDRBWRADDR8": { + "src_wire": "BRAM_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOPADOPU0->BRAM_LOGIC_OUTS_B15_3": { + "src_wire": "BRAM_FIFO36_DOPADOPU0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_FIFO36_ADDRBWRADDRL15": { + "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL15->BRAM_LOGIC_OUTS_B22_2": { + "src_wire": "BRAM_FIFO36_DOBDOL15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX46_1->BRAM_FIFO36_DIADIL14": { + "src_wire": "BRAM_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_CASCOUT_ADDRBWRADDRU8": { + "src_wire": "BRAM_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL0->BRAM_LOGIC_OUTS_B4_0": { + "src_wire": "BRAM_FIFO36_DOBDOL0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { + "src_wire": "BRAM_FIFO18_WRCOUNT11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX42_3->BRAM_FIFO36_DIADIU2": { + "src_wire": "BRAM_IMUX42_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU0->>BRAM_RAMB18_ADDRATIEHIGH0": { + "src_wire": "BRAM_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU12->>BRAM_CASCOUT_ADDRARDADDRU12": { + "src_wire": "BRAM_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL10->>BRAM_UTURN_ADDRBWRADDRL10": { + "src_wire": "BRAM_ADDRBWRADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU0->>BRAM_CASCOUT_ADDRBWRADDRU0": { + "src_wire": "BRAM_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_TSTOUT4->BRAM_LOGIC_OUTS_B11_0": { + "src_wire": "BRAM_FIFO36_TSTOUT4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU11->>BRAM_UTURN_ADDRARDADDRU11": { + "src_wire": "BRAM_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX11_3->BRAM_R_IMUX_ADDRARDADDRU9": { + "src_wire": "BRAM_IMUX11_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU13->>BRAM_FIFO36_ADDRARDADDRU13": { + "src_wire": "BRAM_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL0->>BRAM_FIFO18_ADDRATIEHIGH0": { + "src_wire": "BRAM_ADDRARDADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX40_3->BRAM_RAMB18_DIADI1": { + "src_wire": "BRAM_IMUX40_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOPADOPU1->BRAM_LOGIC_OUTS_B7_3": { + "src_wire": "BRAM_FIFO36_DOPADOPU1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_FULL->BRAM_LOGIC_OUTS_B5_2": { + "src_wire": "BRAM_FIFO18_FULL", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU15->BRAM_LOGIC_OUTS_B7_4": { + "src_wire": "BRAM_FIFO36_DOADOU15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX31_0->BRAM_FIFO18_DIADI11": { + "src_wire": "BRAM_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX14_2->BRAM_FIFO36_WEBWEU5": { + "src_wire": "BRAM_IMUX14_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { + "src_wire": "BRAM_FIFO18_RDCOUNT0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU11->>BRAM_UTURN_ADDRBWRADDRU11": { + "src_wire": "BRAM_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL12->BRAM_ADDRBWRADDRL12": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO14->BRAM_LOGIC_OUTS_B17_1": { + "src_wire": "BRAM_FIFO18_DOBDO14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL6->>BRAM_FIFO18_ADDRARDADDR5": { + "src_wire": "BRAM_ADDRARDADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL3->>BRAM_UTURN_ADDRBWRADDRL3": { + "src_wire": "BRAM_ADDRBWRADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX11_0->BRAM_FIFO36_TSTCNT1": { + "src_wire": "BRAM_IMUX11_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { + "src_wire": "BRAM_FIFO36_WRCOUNT10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX2_1->BRAM_FIFO36_DIBDIL4": { + "src_wire": "BRAM_IMUX2_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK1_0->BRAM_FIFO36_REGCLKBU": { + "src_wire": "BRAM_CLK1_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKBU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX21_3->BRAM_R_IMUX_ADDRARDADDRL12": { + "src_wire": "BRAM_IMUX21_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX3_0->BRAM_FIFO36_TSTWRCNTOFF": { + "src_wire": "BRAM_IMUX3_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWRCNTOFF", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY1->BRAM_LOGIC_OUTS_B12_3": { + "src_wire": "BRAM_FIFO36_ECCPARITY1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX4_1->BRAM_FIFO18_DIBDI5": { + "src_wire": "BRAM_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY3->BRAM_LOGIC_OUTS_B19_2": { + "src_wire": "BRAM_FIFO36_ECCPARITY3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO9->BRAM_LOGIC_OUTS_B22_3": { + "src_wire": "BRAM_RAMB18_DOBDO9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL11->BRAM_ADDRARDADDRL11": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO8->BRAM_LOGIC_OUTS_B0_0": { + "src_wire": "BRAM_FIFO18_DOADO8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX14_2->BRAM_RAMB18_WEBWE5": { + "src_wire": "BRAM_IMUX14_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOPBDOP0->BRAM_LOGIC_OUTS_B3_3": { + "src_wire": "BRAM_RAMB18_DOPBDOP0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX34_1->BRAM_R_IMUX_ADDRBWRADDRL1": { + "src_wire": "BRAM_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX30_0->BRAM_FIFO18_DIADI3": { + "src_wire": "BRAM_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { + "src_wire": "BRAM_FIFO36_RDCOUNT2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU2->>BRAM_FIFO36_ADDRARDADDRU2": { + "src_wire": "BRAM_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL1_1->BRAM_RAMB18_RSTRAMB": { + "src_wire": "BRAM_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTRAMB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU10->>BRAM_RAMB18_ADDRBWRADDR9": { + "src_wire": "BRAM_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_BYP3_2->BRAM_FIFO18_WEBWE3": { + "src_wire": "BRAM_BYP3_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL3->>BRAM_UTURN_ADDRARDADDRL3": { + "src_wire": "BRAM_ADDRARDADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { + "src_wire": "BRAM_FIFO18_ALMOSTFULL", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX42_2->BRAM_FIFO36_DIPADIPU0": { + "src_wire": "BRAM_IMUX42_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX39_0->BRAM_FIFO36_DIBDIL11": { + "src_wire": "BRAM_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU15->BRAM_LOGIC_OUTS_B17_4": { + "src_wire": "BRAM_FIFO36_DOBDOU15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX22_2->BRAM_FIFO18_WEBWE5": { + "src_wire": "BRAM_IMUX22_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX37_0->BRAM_FIFO36_DIBDIL10": { + "src_wire": "BRAM_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX27_1->BRAM_R_IMUX_ADDRBWRADDRU2": { + "src_wire": "BRAM_IMUX27_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX45_4->BRAM_FIFO36_TSTWROS11": { + "src_wire": "BRAM_IMUX45_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU5->>BRAM_CASCOUT_ADDRARDADDRU5": { + "src_wire": "BRAM_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX10_1->BRAM_R_IMUX_ADDRARDADDRU1": { + "src_wire": "BRAM_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX39_2->BRAM_FIFO36_INJECTSBITERR": { + "src_wire": "BRAM_IMUX39_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_INJECTSBITERR", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL14->>BRAM_FIFO36_ADDRBWRADDRL14": { + "src_wire": "BRAM_ADDRBWRADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX42_2->BRAM_RAMB18_DIPADIP0": { + "src_wire": "BRAM_IMUX42_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPADIP0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO15->BRAM_LOGIC_OUTS_B22_2": { + "src_wire": "BRAM_FIFO18_DOBDO15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU10->>BRAM_FIFO36_ADDRBWRADDRU10": { + "src_wire": "BRAM_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX47_0->BRAM_FIFO36_TSTWROS5": { + "src_wire": "BRAM_IMUX47_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_UTURN_ADDRBWRADDRU8": { + "src_wire": "BRAM_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX9_4->BRAM_FIFO36_DIADIU12": { + "src_wire": "BRAM_IMUX9_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX21_0->BRAM_FIFO36_TSTRDOS3": { + "src_wire": "BRAM_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU11->>BRAM_FIFO36_ADDRARDADDRU11": { + "src_wire": "BRAM_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU4->>BRAM_CASCOUT_ADDRBWRADDRU4": { + "src_wire": "BRAM_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX8_2->BRAM_RAMB18_WEA0": { + "src_wire": "BRAM_IMUX8_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX8_1->BRAM_FIFO36_DIADIU0": { + "src_wire": "BRAM_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX26_4->BRAM_FIFO36_TSTCNT8": { + "src_wire": "BRAM_IMUX26_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL11->>BRAM_FIFO36_ADDRARDADDRL11": { + "src_wire": "BRAM_ADDRARDADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU8->>BRAM_RAMB18_ADDRARDADDR7": { + "src_wire": "BRAM_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX29_2->BRAM_FIFO36_WEBWEU2": { + "src_wire": "BRAM_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL14->BRAM_ADDRBWRADDRL14": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX20_4->BRAM_FIFO36_DIBDIU6": { + "src_wire": "BRAM_IMUX20_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU6->>BRAM_CASCOUT_ADDRARDADDRU6": { + "src_wire": "BRAM_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO5->BRAM_LOGIC_OUTS_B13_4": { + "src_wire": "BRAM_RAMB18_DOADO5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { + "src_wire": "BRAM_FIFO18_WRCOUNT4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL2->>BRAM_FIFO18_ADDRARDADDR1": { + "src_wire": "BRAM_ADDRARDADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX11_1->BRAM_R_IMUX_ADDRARDADDRU2": { + "src_wire": "BRAM_IMUX11_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX35_2->BRAM_FIFO36_REGCEBL": { + "src_wire": "BRAM_IMUX35_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEBL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX33_1->BRAM_R_IMUX_ADDRBWRADDRL0": { + "src_wire": "BRAM_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU11->>BRAM_RAMB18_ADDRBWRADDR10": { + "src_wire": "BRAM_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU11->>BRAM_RAMB18_ADDRARDADDR10": { + "src_wire": "BRAM_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU0->>BRAM_FIFO36_ADDRBWRADDRU0": { + "src_wire": "BRAM_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX35_0->BRAM_FIFO36_DIBDIL9": { + "src_wire": "BRAM_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_UTURN_ADDRBWRADDRL15": { + "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX24_1->BRAM_RAMB18_DIBDI0": { + "src_wire": "BRAM_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX5_1->BRAM_FIFO18_DIBDI13": { + "src_wire": "BRAM_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL12->BRAM_ADDRARDADDRL12": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL1_0->BRAM_FIFO36_RSTREGBU": { + "src_wire": "BRAM_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGBU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU11->>BRAM_CASCOUT_ADDRBWRADDRU11": { + "src_wire": "BRAM_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU6->>BRAM_RAMB18_ADDRBWRADDR5": { + "src_wire": "BRAM_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX10_4->BRAM_RAMB18_DIADI5": { + "src_wire": "BRAM_IMUX10_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU6->>BRAM_UTURN_ADDRBWRADDRU6": { + "src_wire": "BRAM_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL11->>BRAM_FIFO18_ADDRARDADDR10": { + "src_wire": "BRAM_ADDRARDADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX45_0->BRAM_FIFO36_TSTWROS3": { + "src_wire": "BRAM_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX29_4->BRAM_FIFO36_TSTCNT11": { + "src_wire": "BRAM_IMUX29_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO15->BRAM_LOGIC_OUTS_B0_2": { + "src_wire": "BRAM_FIFO18_DOADO15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX26_3->BRAM_R_IMUX_ADDRBWRADDRU3": { + "src_wire": "BRAM_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL0->BRAM_LOGIC_OUTS_B8_0": { + "src_wire": "BRAM_FIFO36_DOADOL0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU7->>BRAM_UTURN_ADDRARDADDRU7": { + "src_wire": "BRAM_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX28_3->BRAM_R_IMUX_ADDRBWRADDRU5": { + "src_wire": "BRAM_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { + "src_wire": "BRAM_FIFO18_WRCOUNT5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX31_3->BRAM_IMUX_R_ADDRARDADDRL15": { + "src_wire": "BRAM_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_R_ADDRARDADDRL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX12_1->BRAM_R_IMUX_ADDRARDADDRU8": { + "src_wire": "BRAM_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { + "src_wire": "BRAM_FIFO18_WRCOUNT9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_FIFO18_ADDRBTIEHIGH1": { + "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX46_0->BRAM_FIFO36_TSTWROS4": { + "src_wire": "BRAM_IMUX46_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { + "src_wire": "BRAM_FIFO36_WRCOUNT6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { + "src_wire": "BRAM_FIFO18_WRCOUNT10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK0_0->BRAM_FIFO36_REGCLKBL": { + "src_wire": "BRAM_CLK0_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKBL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL8->>BRAM_FIFO18_ADDRBWRADDR7": { + "src_wire": "BRAM_ADDRBWRADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOPBDOPL1->BRAM_LOGIC_OUTS_B22_1": { + "src_wire": "BRAM_FIFO36_DOPBDOPL1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX15_4->BRAM_RAMB18_DIADI15": { + "src_wire": "BRAM_IMUX15_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { + "src_wire": "BRAM_FIFO18_WRCOUNT6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX4_4->BRAM_FIFO36_TSTIN2": { + "src_wire": "BRAM_IMUX4_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL0_0->BRAM_FIFO36_RSTREGBL": { + "src_wire": "BRAM_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGBL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO6->BRAM_LOGIC_OUTS_B10_4": { + "src_wire": "BRAM_RAMB18_DOADO6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU4->>BRAM_FIFO36_ADDRBWRADDRU4": { + "src_wire": "BRAM_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX23_3->BRAM_RAMB18_DIPBDIP1": { + "src_wire": "BRAM_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPBDIP1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX13_2->BRAM_RAMB18_WEBWE1": { + "src_wire": "BRAM_IMUX13_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK0_4->BRAM_FIFO36_REGCLKARDRCLKL": { + "src_wire": "BRAM_CLK0_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO10->BRAM_LOGIC_OUTS_B5_3": { + "src_wire": "BRAM_RAMB18_DOADO10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL6->>BRAM_UTURN_ADDRBWRADDRL6": { + "src_wire": "BRAM_ADDRBWRADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL4->BRAM_LOGIC_OUTS_B1_1": { + "src_wire": "BRAM_FIFO36_DOBDOL4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL2->BRAM_LOGIC_OUTS_B10_0": { + "src_wire": "BRAM_FIFO36_DOADOL2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX19_3->BRAM_R_IMUX_ADDRARDADDRL9": { + "src_wire": "BRAM_IMUX19_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { + "src_wire": "BRAM_FIFO36_WRCOUNT7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_RAMB18_ADDRATIEHIGH1": { + "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU12->>BRAM_FIFO36_ADDRARDADDRU12": { + "src_wire": "BRAM_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX8_3->BRAM_R_IMUX_ADDRARDADDRU6": { + "src_wire": "BRAM_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU3->>BRAM_RAMB18_ADDRARDADDR2": { + "src_wire": "BRAM_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX15_3->BRAM_FIFO36_DIPADIPU1": { + "src_wire": "BRAM_IMUX15_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOPBDOP0->BRAM_LOGIC_OUTS_B4_1": { + "src_wire": "BRAM_FIFO18_DOPBDOP0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU5->BRAM_LOGIC_OUTS_B1_4": { + "src_wire": "BRAM_FIFO36_DOBDOU5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { + "src_wire": "BRAM_FIFO18_WRCOUNT2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL4->>BRAM_FIFO18_ADDRARDADDR3": { + "src_wire": "BRAM_ADDRARDADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL13->BRAM_LOGIC_OUTS_B2_1": { + "src_wire": "BRAM_FIFO36_DOADOL13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { + "src_wire": "BRAM_FIFO36_WRCOUNT3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_CASCADEOUTB->BRAM_FIFO36_CASCADEOUTB_1": { + "src_wire": "BRAM_FIFO36_CASCADEOUTB", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CASCADEOUTB_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX4_0->BRAM_FIFO36_TSTOFF": { + "src_wire": "BRAM_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTOFF", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX26_1->BRAM_R_IMUX_ADDRBWRADDRU1": { + "src_wire": "BRAM_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL0->>BRAM_UTURN_ADDRARDADDRL0": { + "src_wire": "BRAM_ADDRARDADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU3->>BRAM_FIFO36_ADDRBWRADDRU3": { + "src_wire": "BRAM_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX15_3->BRAM_RAMB18_DIPADIP1": { + "src_wire": "BRAM_IMUX15_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPADIP1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL1_1->BRAM_FIFO36_RSTRAMBU": { + "src_wire": "BRAM_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMBU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL2->BRAM_ADDRARDADDRL2": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { + "src_wire": "BRAM_FIFO18_RDCOUNT5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX34_3->BRAM_R_IMUX_ADDRBWRADDRL3": { + "src_wire": "BRAM_IMUX34_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_RAMB18_ADDRBTIEHIGH1": { + "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL8->>BRAM_FIFO36_ADDRBWRADDRL8": { + "src_wire": "BRAM_ADDRBWRADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX5_1->BRAM_FIFO36_DIBDIL13": { + "src_wire": "BRAM_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX3_1->BRAM_FIFO36_DIBDIL12": { + "src_wire": "BRAM_IMUX3_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX15_2->BRAM_FIFO36_DIADIU8": { + "src_wire": "BRAM_IMUX15_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL14->>BRAM_UTURN_ADDRBWRADDRL14": { + "src_wire": "BRAM_ADDRBWRADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX40_1->BRAM_FIFO36_DIPADIPL1": { + "src_wire": "BRAM_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU13->>BRAM_CASCOUT_ADDRBWRADDRU13": { + "src_wire": "BRAM_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX16_1->BRAM_FIFO18_DIADI0": { + "src_wire": "BRAM_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { + "src_wire": "BRAM_FIFO36_WRCOUNT4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL15->BRAM_LOGIC_OUTS_B0_2": { + "src_wire": "BRAM_FIFO36_DOADOL15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { + "src_wire": "BRAM_FIFO18_RDCOUNT9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL4->BRAM_ADDRBWRADDRL4": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK0_3->BRAM_FIFO18_CLKARDCLK": { + "src_wire": "BRAM_CLK0_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_CLKARDCLK", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX36_1->BRAM_R_IMUX_ADDRBWRADDRL8": { + "src_wire": "BRAM_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL1_3->BRAM_RAMB18_RSTRAMARSTRAM": { + "src_wire": "BRAM_CTRL1_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTRAMARSTRAM", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL9->>BRAM_FIFO36_ADDRARDADDRL9": { + "src_wire": "BRAM_ADDRARDADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU7->>BRAM_FIFO36_ADDRBWRADDRU7": { + "src_wire": "BRAM_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK0_1->BRAM_FIFO36_CLKBWRCLKL": { + "src_wire": "BRAM_CLK0_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKBWRCLKL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU6->>BRAM_FIFO36_ADDRARDADDRU6": { + "src_wire": "BRAM_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX21_2->BRAM_FIFO18_WEBWE1": { + "src_wire": "BRAM_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX29_0->BRAM_FIFO18_DIADI10": { + "src_wire": "BRAM_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX18_1->BRAM_R_IMUX_ADDRARDADDRL1": { + "src_wire": "BRAM_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO6->BRAM_LOGIC_OUTS_B15_1": { + "src_wire": "BRAM_FIFO18_DOADO6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { + "src_wire": "BRAM_FIFO18_RDCOUNT8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU3->>BRAM_UTURN_ADDRARDADDRU3": { + "src_wire": "BRAM_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX27_4->BRAM_FIFO36_TSTCNT9": { + "src_wire": "BRAM_IMUX27_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX25_2->BRAM_FIFO36_WEAU3": { + "src_wire": "BRAM_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL0->BRAM_ADDRBWRADDRL0": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO12->BRAM_LOGIC_OUTS_B19_1": { + "src_wire": "BRAM_FIFO18_DOBDO12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL8->BRAM_ADDRARDADDRL8": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_UTURN_ADDRARDADDRL15": { + "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL13->>BRAM_UTURN_ADDRARDADDRL13": { + "src_wire": "BRAM_ADDRARDADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX12_3->BRAM_R_IMUX_ADDRARDADDRU5": { + "src_wire": "BRAM_IMUX12_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX34_2->BRAM_FIFO36_ENBWRENL": { + "src_wire": "BRAM_IMUX34_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENBWRENL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU0->>BRAM_CASCOUT_ADDRARDADDRU0": { + "src_wire": "BRAM_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL5->BRAM_ADDRARDADDRL5": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { + "src_wire": "BRAM_FIFO36_WRCOUNT11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL2->>BRAM_UTURN_ADDRARDADDRL2": { + "src_wire": "BRAM_ADDRARDADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL11->>BRAM_UTURN_ADDRBWRADDRL11": { + "src_wire": "BRAM_ADDRBWRADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU0->>BRAM_FIFO36_ADDRARDADDRU0": { + "src_wire": "BRAM_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU5->>BRAM_FIFO36_ADDRARDADDRU5": { + "src_wire": "BRAM_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU1->>BRAM_RAMB18_ADDRARDADDR0": { + "src_wire": "BRAM_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX41_1->BRAM_FIFO18_DIADI4": { + "src_wire": "BRAM_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO1->BRAM_LOGIC_OUTS_B13_0": { + "src_wire": "BRAM_FIFO18_DOADO1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX43_1->BRAM_FIFO36_DIADIL5": { + "src_wire": "BRAM_IMUX43_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX2_0->BRAM_FIFO36_TSTRDCNTOFF": { + "src_wire": "BRAM_IMUX2_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDCNTOFF", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_FIFO36_ADDRBWRADDRU9": { + "src_wire": "BRAM_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL0->>BRAM_FIFO36_ADDRBWRADDRL0": { + "src_wire": "BRAM_ADDRBWRADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL7->BRAM_ADDRARDADDRL7": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL0_4->BRAM_FIFO18_RSTREGARSTREG": { + "src_wire": "BRAM_CTRL0_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTREGARSTREG", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK1_0->BRAM_RAMB18_REGCLKB": { + "src_wire": "BRAM_CLK1_0", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL4->BRAM_ADDRARDADDRL4": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU13->BRAM_LOGIC_OUTS_B5_4": { + "src_wire": "BRAM_FIFO36_DOADOU13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU6->>BRAM_UTURN_ADDRARDADDRU6": { + "src_wire": "BRAM_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX34_2->BRAM_FIFO18_ENBWREN": { + "src_wire": "BRAM_IMUX34_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ENBWREN", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX0_0->BRAM_FIFO36_TSTBRAMRST": { + "src_wire": "BRAM_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTBRAMRST", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DBITERR->BRAM_LOGIC_OUTS_B16_2": { + "src_wire": "BRAM_FIFO36_DBITERR", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL0_3->BRAM_FIFO18_RSTRAMARSTRAM": { + "src_wire": "BRAM_CTRL0_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTRAMARSTRAM", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL3->>BRAM_FIFO36_ADDRARDADDRL3": { + "src_wire": "BRAM_ADDRARDADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL1_4->BRAM_FIFO36_RSTREGARSTREGU": { + "src_wire": "BRAM_CTRL1_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGARSTREGU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX41_1->BRAM_FIFO36_DIADIL4": { + "src_wire": "BRAM_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL10->>BRAM_FIFO18_ADDRARDADDR9": { + "src_wire": "BRAM_ADDRARDADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX3_3->BRAM_FIFO36_DIBDIU2": { + "src_wire": "BRAM_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU6->BRAM_LOGIC_OUTS_B10_4": { + "src_wire": "BRAM_FIFO36_DOADOU6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { + "src_wire": "BRAM_FIFO18_ALMOSTEMPTY", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX15_0->BRAM_FIFO36_TSTCNT5": { + "src_wire": "BRAM_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX36_2->BRAM_R_IMUX_ADDRBWRADDRL10": { + "src_wire": "BRAM_IMUX36_2", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO7->BRAM_LOGIC_OUTS_B4_2": { + "src_wire": "BRAM_FIFO18_DOBDO7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL2->BRAM_ADDRBWRADDRL2": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU1->>BRAM_UTURN_ADDRARDADDRU1": { + "src_wire": "BRAM_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU10->BRAM_LOGIC_OUTS_B19_3": { + "src_wire": "BRAM_FIFO36_DOBDOU10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX3_2->BRAM_FIFO18_DIPADIP0": { + "src_wire": "BRAM_IMUX3_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPADIP0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX18_2->BRAM_FIFO36_ENARDENL": { + "src_wire": "BRAM_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENARDENL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU12->BRAM_LOGIC_OUTS_B0_4": { + "src_wire": "BRAM_FIFO36_DOADOU12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOPADOP1->BRAM_LOGIC_OUTS_B7_3": { + "src_wire": "BRAM_RAMB18_DOPADOP1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL3->>BRAM_FIFO18_ADDRARDADDR2": { + "src_wire": "BRAM_ADDRARDADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX27_0->BRAM_FIFO36_DIADIL9": { + "src_wire": "BRAM_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX3_1->BRAM_FIFO18_DIBDI12": { + "src_wire": "BRAM_IMUX3_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX10_4->BRAM_FIFO36_DIADIU5": { + "src_wire": "BRAM_IMUX10_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK0_3->BRAM_FIFO36_CLKARDCLKL": { + "src_wire": "BRAM_CLK0_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKARDCLKL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FAN5_2->BRAM_FIFO36_WEBWEU0": { + "src_wire": "BRAM_FAN5_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX2_3->BRAM_FIFO36_DIBDIU9": { + "src_wire": "BRAM_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL1->>BRAM_FIFO18_ADDRBWRADDR0": { + "src_wire": "BRAM_ADDRBWRADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU7->>BRAM_FIFO36_ADDRARDADDRU7": { + "src_wire": "BRAM_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL14->>BRAM_FIFO36_ADDRARDADDRL14": { + "src_wire": "BRAM_ADDRARDADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX9_3->BRAM_R_IMUX_ADDRARDADDRU7": { + "src_wire": "BRAM_IMUX9_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX4_2->BRAM_FIFO36_DIPBDIPL0": { + "src_wire": "BRAM_IMUX4_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU13->BRAM_LOGIC_OUTS_B19_4": { + "src_wire": "BRAM_FIFO36_DOBDOU13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL1_0->BRAM_RAMB18_RSTREGB": { + "src_wire": "BRAM_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTREGB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU5->BRAM_LOGIC_OUTS_B13_4": { + "src_wire": "BRAM_FIFO36_DOADOU5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL7->BRAM_LOGIC_OUTS_B4_2": { + "src_wire": "BRAM_FIFO36_DOBDOL7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU3->>BRAM_CASCOUT_ADDRARDADDRU3": { + "src_wire": "BRAM_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU1->BRAM_LOGIC_OUTS_B4_3": { + "src_wire": "BRAM_FIFO36_DOBDOU1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX39_1->BRAM_R_IMUX_ADDRBWRADDRL13": { + "src_wire": "BRAM_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU9->BRAM_LOGIC_OUTS_B22_3": { + "src_wire": "BRAM_FIFO36_DOBDOU9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO4->BRAM_LOGIC_OUTS_B1_1": { + "src_wire": "BRAM_FIFO18_DOBDO4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX6_2->BRAM_FIFO18_WEBWE4": { + "src_wire": "BRAM_IMUX6_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_FIFO36_ADDRARDADDRL15": { + "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX1_1->BRAM_FIFO36_DIPBDIPL1": { + "src_wire": "BRAM_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL3->BRAM_ADDRARDADDRL3": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX19_2->BRAM_FIFO36_REGCEAREGCEL": { + "src_wire": "BRAM_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEAREGCEL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO15->BRAM_LOGIC_OUTS_B7_4": { + "src_wire": "BRAM_RAMB18_DOADO15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX2_1->BRAM_FIFO18_DIBDI4": { + "src_wire": "BRAM_IMUX2_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_BYP3_2->BRAM_FIFO36_WEBWEL3": { + "src_wire": "BRAM_BYP3_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL10->BRAM_LOGIC_OUTS_B20_0": { + "src_wire": "BRAM_FIFO36_DOBDOL10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU14->>BRAM_RAMB18_ADDRBWRADDR13": { + "src_wire": "BRAM_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX30_2->BRAM_RAMB18_WEBWE6": { + "src_wire": "BRAM_IMUX30_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX37_2->BRAM_FIFO36_WEBWEL2": { + "src_wire": "BRAM_IMUX37_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO8->BRAM_LOGIC_OUTS_B7_2": { + "src_wire": "BRAM_RAMB18_DOADO8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU0->>BRAM_UTURN_ADDRARDADDRU0": { + "src_wire": "BRAM_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO2->BRAM_LOGIC_OUTS_B1_3": { + "src_wire": "BRAM_RAMB18_DOBDO2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL14->BRAM_LOGIC_OUTS_B7_1": { + "src_wire": "BRAM_FIFO36_DOADOL14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL1->BRAM_LOGIC_OUTS_B1_0": { + "src_wire": "BRAM_FIFO36_DOBDOL1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL0_3->BRAM_FIFO36_RSTRAMARSTRAMLRST": { + "src_wire": "BRAM_CTRL0_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMLRST", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX41_2->BRAM_FIFO18_DIADI15": { + "src_wire": "BRAM_IMUX41_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO2->BRAM_LOGIC_OUTS_B6_0": { + "src_wire": "BRAM_FIFO18_DOBDO2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU8->>BRAM_FIFO36_ADDRARDADDRU8": { + "src_wire": "BRAM_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX40_2->BRAM_FIFO18_DIADI7": { + "src_wire": "BRAM_IMUX40_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL13->>BRAM_FIFO18_ADDRARDADDR12": { + "src_wire": "BRAM_ADDRARDADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL11->>BRAM_FIFO36_ADDRBWRADDRL11": { + "src_wire": "BRAM_ADDRBWRADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX32_3->BRAM_R_IMUX_ADDRBWRADDRL6": { + "src_wire": "BRAM_IMUX32_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU6->>BRAM_RAMB18_ADDRARDADDR5": { + "src_wire": "BRAM_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL9->BRAM_LOGIC_OUTS_B19_0": { + "src_wire": "BRAM_FIFO36_DOBDOL9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX20_2->BRAM_R_IMUX_ADDRARDADDRL10": { + "src_wire": "BRAM_IMUX20_2", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { + "src_wire": "BRAM_FIFO18_RDCOUNT11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL4->>BRAM_UTURN_ADDRARDADDRL4": { + "src_wire": "BRAM_ADDRARDADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL0->>BRAM_UTURN_ADDRBWRADDRL0": { + "src_wire": "BRAM_ADDRBWRADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL0->>BRAM_FIFO18_ADDRBTIEHIGH0": { + "src_wire": "BRAM_ADDRBWRADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX37_1->BRAM_R_IMUX_ADDRBWRADDRL4": { + "src_wire": "BRAM_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL9->>BRAM_UTURN_ADDRARDADDRL9": { + "src_wire": "BRAM_ADDRARDADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL9->>BRAM_FIFO36_ADDRBWRADDRL9": { + "src_wire": "BRAM_ADDRBWRADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL7->>BRAM_FIFO36_ADDRBWRADDRL7": { + "src_wire": "BRAM_ADDRBWRADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX28_2->BRAM_R_IMUX_ADDRBWRADDRU10": { + "src_wire": "BRAM_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU4->>BRAM_FIFO36_ADDRARDADDRU4": { + "src_wire": "BRAM_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX29_3->BRAM_R_IMUX_ADDRBWRADDRU12": { + "src_wire": "BRAM_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX29_1->BRAM_R_IMUX_ADDRBWRADDRU4": { + "src_wire": "BRAM_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX44_1->BRAM_FIFO18_DIADI13": { + "src_wire": "BRAM_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX20_0->BRAM_FIFO36_TSTRDOS2": { + "src_wire": "BRAM_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU13->>BRAM_RAMB18_ADDRBWRADDR12": { + "src_wire": "BRAM_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX3_2->BRAM_FIFO36_DIPADIPL0": { + "src_wire": "BRAM_IMUX3_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX28_4->BRAM_FIFO36_TSTCNT10": { + "src_wire": "BRAM_IMUX28_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX13_3->BRAM_R_IMUX_ADDRARDADDRU12": { + "src_wire": "BRAM_IMUX13_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_EMPTY->BRAM_LOGIC_OUTS_B6_2": { + "src_wire": "BRAM_FIFO18_EMPTY", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX32_1->BRAM_FIFO18_DIBDI0": { + "src_wire": "BRAM_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU0->>BRAM_RAMB18_ADDRBTIEHIGH0": { + "src_wire": "BRAM_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX10_3->BRAM_R_IMUX_ADDRARDADDRU3": { + "src_wire": "BRAM_IMUX10_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX23_3->BRAM_FIFO36_DIPBDIPU1": { + "src_wire": "BRAM_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO3->BRAM_LOGIC_OUTS_B3_0": { + "src_wire": "BRAM_FIFO18_DOBDO3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { + "src_wire": "BRAM_FIFO18_RDCOUNT6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX16_2->BRAM_FIFO18_WEA0": { + "src_wire": "BRAM_IMUX16_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX17_1->BRAM_R_IMUX_ADDRARDADDRL0": { + "src_wire": "BRAM_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_RDERR->BRAM_LOGIC_OUTS_B14_2": { + "src_wire": "BRAM_FIFO18_RDERR", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX17_2->BRAM_FIFO18_WEA2": { + "src_wire": "BRAM_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL1->BRAM_ADDRBWRADDRL1": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU2->>BRAM_UTURN_ADDRARDADDRU2": { + "src_wire": "BRAM_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY5->BRAM_LOGIC_OUTS_B20_2": { + "src_wire": "BRAM_FIFO36_ECCPARITY5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL3->BRAM_LOGIC_OUTS_B15_0": { + "src_wire": "BRAM_FIFO36_DOADOL3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOPADOP0->BRAM_LOGIC_OUTS_B15_3": { + "src_wire": "BRAM_RAMB18_DOPADOP0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL11->>BRAM_FIFO18_ADDRBWRADDR10": { + "src_wire": "BRAM_ADDRBWRADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL6->>BRAM_FIFO36_ADDRBWRADDRL6": { + "src_wire": "BRAM_ADDRBWRADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX39_0->BRAM_FIFO18_DIBDI11": { + "src_wire": "BRAM_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL9->>BRAM_UTURN_ADDRBWRADDRL9": { + "src_wire": "BRAM_ADDRBWRADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO5->BRAM_LOGIC_OUTS_B1_4": { + "src_wire": "BRAM_RAMB18_DOBDO5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX35_4->BRAM_FIFO36_TSTRDOS9": { + "src_wire": "BRAM_IMUX35_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL4->>BRAM_FIFO36_ADDRBWRADDRL4": { + "src_wire": "BRAM_ADDRBWRADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FAN5_2->BRAM_RAMB18_WEBWE0": { + "src_wire": "BRAM_FAN5_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU3->BRAM_LOGIC_OUTS_B10_3": { + "src_wire": "BRAM_FIFO36_DOADOU3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX42_1->BRAM_FIFO18_DIADI12": { + "src_wire": "BRAM_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX44_4->BRAM_FIFO36_TSTWROS10": { + "src_wire": "BRAM_IMUX44_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU9->>BRAM_FIFO36_ADDRARDADDRU9": { + "src_wire": "BRAM_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL10->BRAM_LOGIC_OUTS_B2_0": { + "src_wire": "BRAM_FIFO36_DOADOL10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX38_2->BRAM_FIFO18_WEBWE6": { + "src_wire": "BRAM_IMUX38_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL0_4->BRAM_FIFO36_RSTREGARSTREGL": { + "src_wire": "BRAM_CTRL0_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGARSTREGL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX42_1->BRAM_FIFO36_DIADIL12": { + "src_wire": "BRAM_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX45_3->BRAM_RAMB18_DIADI11": { + "src_wire": "BRAM_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX42_4->BRAM_FIFO36_TSTWROS8": { + "src_wire": "BRAM_IMUX42_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX16_2->BRAM_FIFO36_WEAL0": { + "src_wire": "BRAM_IMUX16_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL12->>BRAM_UTURN_ADDRBWRADDRL12": { + "src_wire": "BRAM_ADDRBWRADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU6->>BRAM_CASCOUT_ADDRBWRADDRU6": { + "src_wire": "BRAM_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX6_1->BRAM_FIFO36_DIBDIL6": { + "src_wire": "BRAM_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL0->BRAM_ADDRARDADDRL0": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX25_0->BRAM_FIFO36_DIADIL8": { + "src_wire": "BRAM_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_SBITERR->BRAM_LOGIC_OUTS_B9_2": { + "src_wire": "BRAM_FIFO36_SBITERR", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU4->>BRAM_UTURN_ADDRBWRADDRU4": { + "src_wire": "BRAM_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL6->BRAM_ADDRARDADDRL6": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO7->BRAM_LOGIC_OUTS_B8_2": { + "src_wire": "BRAM_FIFO18_DOADO7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL7->>BRAM_FIFO18_ADDRARDADDR6": { + "src_wire": "BRAM_ADDRARDADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { + "src_wire": "BRAM_FIFO36_RDCOUNT9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO12->BRAM_LOGIC_OUTS_B5_1": { + "src_wire": "BRAM_FIFO18_DOADO12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX30_2->BRAM_FIFO36_WEBWEU6": { + "src_wire": "BRAM_IMUX30_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU2->>BRAM_RAMB18_ADDRBWRADDR1": { + "src_wire": "BRAM_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX19_0->BRAM_FIFO36_TSTRDOS1": { + "src_wire": "BRAM_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX30_4->BRAM_FIFO36_TSTCNT12": { + "src_wire": "BRAM_IMUX30_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO7->BRAM_LOGIC_OUTS_B3_4": { + "src_wire": "BRAM_RAMB18_DOBDO7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX19_4->BRAM_RAMB18_DIBDI13": { + "src_wire": "BRAM_IMUX19_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX42_0->BRAM_FIFO36_TSTWROS0": { + "src_wire": "BRAM_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX25_1->BRAM_R_IMUX_ADDRBWRADDRU0": { + "src_wire": "BRAM_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO9->BRAM_LOGIC_OUTS_B0_3": { + "src_wire": "BRAM_RAMB18_DOADO9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { + "src_wire": "BRAM_FIFO36_RDCOUNT10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX8_4->BRAM_FIFO36_DIADIU4": { + "src_wire": "BRAM_IMUX8_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX40_1->BRAM_FIFO18_DIPADIP1": { + "src_wire": "BRAM_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPADIP1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX9_1->BRAM_R_IMUX_ADDRARDADDRU0": { + "src_wire": "BRAM_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU3->>BRAM_RAMB18_ADDRBWRADDR2": { + "src_wire": "BRAM_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX24_3->BRAM_R_IMUX_ADDRBWRADDRU6": { + "src_wire": "BRAM_IMUX24_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { + "src_wire": "BRAM_FIFO18_RDCOUNT4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL4->>BRAM_FIFO36_ADDRARDADDRL4": { + "src_wire": "BRAM_ADDRARDADDRL4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX4_1->BRAM_FIFO36_DIBDIL5": { + "src_wire": "BRAM_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX9_2->BRAM_FIFO36_WEAU2": { + "src_wire": "BRAM_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX13_4->BRAM_FIFO36_DIADIU14": { + "src_wire": "BRAM_IMUX13_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT12->BRAM_LOGIC_OUTS_B23_4": { + "src_wire": "BRAM_FIFO36_WRCOUNT12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU14->BRAM_LOGIC_OUTS_B20_4": { + "src_wire": "BRAM_FIFO36_DOBDOU14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX14_1->BRAM_R_IMUX_ADDRARDADDRU11": { + "src_wire": "BRAM_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX12_0->BRAM_FIFO36_TSTCNT2": { + "src_wire": "BRAM_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL12->>BRAM_FIFO18_ADDRARDADDR11": { + "src_wire": "BRAM_ADDRARDADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL11->BRAM_LOGIC_OUTS_B7_0": { + "src_wire": "BRAM_FIFO36_DOADOL11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL2->>BRAM_FIFO18_ADDRBWRADDR1": { + "src_wire": "BRAM_ADDRBWRADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO1->BRAM_LOGIC_OUTS_B1_0": { + "src_wire": "BRAM_FIFO18_DOBDO1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL3->>BRAM_FIFO18_ADDRBWRADDR2": { + "src_wire": "BRAM_ADDRBWRADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX2_3->BRAM_RAMB18_DIBDI9": { + "src_wire": "BRAM_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL1->>BRAM_FIFO36_ADDRARDADDRL1": { + "src_wire": "BRAM_ADDRARDADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX18_2->BRAM_FIFO18_ENARDEN": { + "src_wire": "BRAM_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ENARDEN", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_FIFO36_ADDRBWRADDRU8": { + "src_wire": "BRAM_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL12->>BRAM_FIFO36_ADDRARDADDRL12": { + "src_wire": "BRAM_ADDRARDADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU0->>BRAM_UTURN_ADDRBWRADDRU0": { + "src_wire": "BRAM_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL5->>BRAM_UTURN_ADDRARDADDRL5": { + "src_wire": "BRAM_ADDRARDADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU2->>BRAM_FIFO36_ADDRBWRADDRU2": { + "src_wire": "BRAM_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX45_2->BRAM_FIFO36_WEBWEU3": { + "src_wire": "BRAM_IMUX45_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU13->>BRAM_UTURN_ADDRARDADDRU13": { + "src_wire": "BRAM_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX1_2->BRAM_FIFO36_DIBDIL7": { + "src_wire": "BRAM_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL9->BRAM_ADDRARDADDRL9": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU14->>BRAM_UTURN_ADDRBWRADDRU14": { + "src_wire": "BRAM_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX11_2->BRAM_FIFO36_REGCEAREGCEU": { + "src_wire": "BRAM_IMUX11_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEAREGCEU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL8->>BRAM_FIFO36_ADDRARDADDRL8": { + "src_wire": "BRAM_ADDRARDADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU14->>BRAM_CASCOUT_ADDRARDADDRU14": { + "src_wire": "BRAM_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { + "src_wire": "BRAM_FIFO36_RDCOUNT5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX27_3->BRAM_R_IMUX_ADDRBWRADDRU9": { + "src_wire": "BRAM_IMUX27_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO4->BRAM_LOGIC_OUTS_B4_4": { + "src_wire": "BRAM_RAMB18_DOBDO4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX43_2->BRAM_RAMB18_DIPBDIP0": { + "src_wire": "BRAM_IMUX43_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPBDIP0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL5->>BRAM_FIFO36_ADDRARDADDRL5": { + "src_wire": "BRAM_ADDRARDADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU1->>BRAM_FIFO36_ADDRARDADDRU1": { + "src_wire": "BRAM_ADDRARDADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU5->>BRAM_UTURN_ADDRARDADDRU5": { + "src_wire": "BRAM_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX12_4->BRAM_RAMB18_DIADI6": { + "src_wire": "BRAM_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL1->BRAM_ADDRARDADDRL1": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { + "src_wire": "BRAM_FIFO36_RDCOUNT4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU10->>BRAM_RAMB18_ADDRARDADDR9": { + "src_wire": "BRAM_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO13->BRAM_LOGIC_OUTS_B19_4": { + "src_wire": "BRAM_RAMB18_DOBDO13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX20_4->BRAM_RAMB18_DIBDI6": { + "src_wire": "BRAM_IMUX20_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX27_2->BRAM_FIFO36_REGCEBU": { + "src_wire": "BRAM_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEBU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL14->>BRAM_FIFO18_ADDRARDADDR13": { + "src_wire": "BRAM_ADDRARDADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL13->>BRAM_FIFO36_ADDRARDADDRL13": { + "src_wire": "BRAM_ADDRARDADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL10->BRAM_ADDRARDADDRL10": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL10->BRAM_ADDRBWRADDRL10": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO12->BRAM_LOGIC_OUTS_B0_4": { + "src_wire": "BRAM_RAMB18_DOADO12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK1_1->BRAM_FIFO36_CLKBWRCLKU": { + "src_wire": "BRAM_CLK1_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKBWRCLKU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX28_1->BRAM_R_IMUX_ADDRBWRADDRU8": { + "src_wire": "BRAM_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL11->BRAM_LOGIC_OUTS_B17_0": { + "src_wire": "BRAM_FIFO36_DOBDOL11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_TSTOUT2->BRAM_LOGIC_OUTS_B11_4": { + "src_wire": "BRAM_FIFO36_TSTOUT2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX10_2->BRAM_FIFO36_ENARDENU": { + "src_wire": "BRAM_IMUX10_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENARDENU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU5->>BRAM_RAMB18_ADDRBWRADDR4": { + "src_wire": "BRAM_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL13->>BRAM_FIFO18_ADDRBWRADDR12": { + "src_wire": "BRAM_ADDRBWRADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_BYP6_2->BRAM_FIFO18_WEBWE7": { + "src_wire": "BRAM_BYP6_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { + "src_wire": "BRAM_FIFO18_WRCOUNT1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX29_0->BRAM_FIFO36_DIADIL10": { + "src_wire": "BRAM_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX36_0->BRAM_FIFO36_DIBDIL2": { + "src_wire": "BRAM_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO0->BRAM_LOGIC_OUTS_B3_2": { + "src_wire": "BRAM_RAMB18_DOBDO0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDERR->BRAM_LOGIC_OUTS_B14_2": { + "src_wire": "BRAM_FIFO36_RDERR", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { + "src_wire": "BRAM_FIFO18_WRCOUNT0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX22_2->BRAM_FIFO36_WEBWEL5": { + "src_wire": "BRAM_IMUX22_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX29_2->BRAM_RAMB18_WEBWE2": { + "src_wire": "BRAM_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL5->>BRAM_FIFO18_ADDRARDADDR4": { + "src_wire": "BRAM_ADDRARDADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU4->BRAM_LOGIC_OUTS_B4_4": { + "src_wire": "BRAM_FIFO36_DOBDOU4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { + "src_wire": "BRAM_FIFO36_RDCOUNT11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO14->BRAM_LOGIC_OUTS_B2_4": { + "src_wire": "BRAM_RAMB18_DOADO14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX1_2->BRAM_FIFO18_DIBDI7": { + "src_wire": "BRAM_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL10->>BRAM_FIFO18_ADDRBWRADDR9": { + "src_wire": "BRAM_ADDRBWRADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX43_2->BRAM_FIFO36_DIPBDIPU0": { + "src_wire": "BRAM_IMUX43_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX20_1->BRAM_R_IMUX_ADDRARDADDRL8": { + "src_wire": "BRAM_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU7->>BRAM_CASCOUT_ADDRBWRADDRU7": { + "src_wire": "BRAM_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX19_1->BRAM_R_IMUX_ADDRARDADDRL2": { + "src_wire": "BRAM_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOPBDOP1->BRAM_LOGIC_OUTS_B22_1": { + "src_wire": "BRAM_FIFO18_DOPBDOP1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU14->>BRAM_FIFO36_ADDRBWRADDRU14": { + "src_wire": "BRAM_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU3->>BRAM_CASCOUT_ADDRBWRADDRU3": { + "src_wire": "BRAM_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL1->>BRAM_FIFO36_ADDRBWRADDRL1": { + "src_wire": "BRAM_ADDRBWRADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO0->BRAM_LOGIC_OUTS_B4_0": { + "src_wire": "BRAM_FIFO18_DOBDO0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOPBDOPL0->BRAM_LOGIC_OUTS_B4_1": { + "src_wire": "BRAM_FIFO36_DOPBDOPL0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU11->>BRAM_CASCOUT_ADDRARDADDRU11": { + "src_wire": "BRAM_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX23_0->BRAM_FIFO36_TSTRDOS5": { + "src_wire": "BRAM_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO14->BRAM_LOGIC_OUTS_B7_1": { + "src_wire": "BRAM_FIFO18_DOADO14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX35_0->BRAM_FIFO18_DIBDI9": { + "src_wire": "BRAM_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX45_3->BRAM_FIFO36_DIADIU11": { + "src_wire": "BRAM_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL3->BRAM_ADDRBWRADDRL3": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_EMPTY->BRAM_LOGIC_OUTS_B6_2": { + "src_wire": "BRAM_FIFO36_EMPTY", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL13->>BRAM_UTURN_ADDRBWRADDRL13": { + "src_wire": "BRAM_ADDRBWRADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO5->BRAM_LOGIC_OUTS_B10_1": { + "src_wire": "BRAM_FIFO18_DOADO5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX33_3->BRAM_R_IMUX_ADDRBWRADDRL7": { + "src_wire": "BRAM_IMUX33_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX41_0->BRAM_FIFO36_TSTIN4": { + "src_wire": "BRAM_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX9_2->BRAM_RAMB18_WEA2": { + "src_wire": "BRAM_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX33_2->BRAM_FIFO36_WEAL3": { + "src_wire": "BRAM_IMUX33_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX33_4->BRAM_FIFO36_TSTRDOS7": { + "src_wire": "BRAM_IMUX33_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU10->>BRAM_CASCOUT_ADDRARDADDRU10": { + "src_wire": "BRAM_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU12->BRAM_LOGIC_OUTS_B22_4": { + "src_wire": "BRAM_FIFO36_DOBDOU12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOPADOP1->BRAM_LOGIC_OUTS_B0_1": { + "src_wire": "BRAM_FIFO18_DOPADOP1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL13->BRAM_ADDRARDADDRL13": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { + "src_wire": "BRAM_FIFO18_RDCOUNT1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX38_4->BRAM_FIFO36_TSTRDOS12": { + "src_wire": "BRAM_IMUX38_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX4_3->BRAM_RAMB18_DIBDI10": { + "src_wire": "BRAM_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL2->>BRAM_FIFO36_ADDRBWRADDRL2": { + "src_wire": "BRAM_ADDRBWRADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL11->>BRAM_UTURN_ADDRARDADDRL11": { + "src_wire": "BRAM_ADDRARDADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY2->BRAM_LOGIC_OUTS_B13_2": { + "src_wire": "BRAM_FIFO36_ECCPARITY2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX14_3->BRAM_R_IMUX_ADDRARDADDRU14": { + "src_wire": "BRAM_IMUX14_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX17_2->BRAM_FIFO36_WEAL2": { + "src_wire": "BRAM_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT12->BRAM_LOGIC_OUTS_B21_4": { + "src_wire": "BRAM_FIFO36_RDCOUNT12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX33_0->BRAM_FIFO18_DIBDI8": { + "src_wire": "BRAM_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK1_3->BRAM_FIFO36_CLKARDCLKU": { + "src_wire": "BRAM_CLK1_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKARDCLKU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX7_1->BRAM_FIFO18_DIBDI14": { + "src_wire": "BRAM_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX38_3->BRAM_R_IMUX_ADDRBWRADDRL14": { + "src_wire": "BRAM_IMUX38_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX15_1->BRAM_R_IMUX_ADDRARDADDRU13": { + "src_wire": "BRAM_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL6->BRAM_LOGIC_OUTS_B15_1": { + "src_wire": "BRAM_FIFO36_DOADOL6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX5_3->BRAM_FIFO36_DIBDIU3": { + "src_wire": "BRAM_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX41_3->BRAM_FIFO36_DIADIU9": { + "src_wire": "BRAM_IMUX41_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL12->BRAM_LOGIC_OUTS_B19_1": { + "src_wire": "BRAM_FIFO36_DOBDOL12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL5->BRAM_ADDRBWRADDRL5": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX21_4->BRAM_FIFO36_DIBDIU14": { + "src_wire": "BRAM_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX20_3->BRAM_R_IMUX_ADDRARDADDRL5": { + "src_wire": "BRAM_IMUX20_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX43_1->BRAM_FIFO18_DIADI5": { + "src_wire": "BRAM_IMUX43_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU1->>BRAM_FIFO36_ADDRBWRADDRU1": { + "src_wire": "BRAM_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX1_3->BRAM_RAMB18_DIBDI1": { + "src_wire": "BRAM_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL7->>BRAM_FIFO18_ADDRBWRADDR6": { + "src_wire": "BRAM_ADDRBWRADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX30_0->BRAM_FIFO36_DIADIL3": { + "src_wire": "BRAM_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU9->BRAM_LOGIC_OUTS_B0_3": { + "src_wire": "BRAM_FIFO36_DOADOU9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO11->BRAM_LOGIC_OUTS_B20_3": { + "src_wire": "BRAM_RAMB18_DOBDO11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO4->BRAM_LOGIC_OUTS_B13_1": { + "src_wire": "BRAM_FIFO18_DOADO4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX43_0->BRAM_FIFO36_TSTWROS1": { + "src_wire": "BRAM_IMUX43_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX14_0->BRAM_FIFO36_TSTCNT4": { + "src_wire": "BRAM_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX38_0->BRAM_FIFO36_DIBDIL3": { + "src_wire": "BRAM_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL14->>BRAM_UTURN_ADDRARDADDRL14": { + "src_wire": "BRAM_ADDRARDADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL5->BRAM_LOGIC_OUTS_B6_1": { + "src_wire": "BRAM_FIFO36_DOBDOL5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU13->>BRAM_UTURN_ADDRBWRADDRU13": { + "src_wire": "BRAM_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU0->BRAM_LOGIC_OUTS_B15_2": { + "src_wire": "BRAM_FIFO36_DOADOU0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU14->>BRAM_FIFO36_ADDRARDADDRU14": { + "src_wire": "BRAM_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX44_0->BRAM_FIFO36_TSTWROS2": { + "src_wire": "BRAM_IMUX44_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO8->BRAM_LOGIC_OUTS_B17_2": { + "src_wire": "BRAM_RAMB18_DOBDO8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL8->>BRAM_UTURN_ADDRBWRADDRL8": { + "src_wire": "BRAM_ADDRBWRADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX16_0->BRAM_FIFO36_TSTIN1": { + "src_wire": "BRAM_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO3->BRAM_LOGIC_OUTS_B6_3": { + "src_wire": "BRAM_RAMB18_DOBDO3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU7->BRAM_LOGIC_OUTS_B3_4": { + "src_wire": "BRAM_FIFO36_DOBDOU7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU7->>BRAM_CASCOUT_ADDRARDADDRU7": { + "src_wire": "BRAM_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX36_4->BRAM_FIFO36_TSTRDOS10": { + "src_wire": "BRAM_IMUX36_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX40_3->BRAM_FIFO36_DIADIU1": { + "src_wire": "BRAM_IMUX40_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX17_4->BRAM_RAMB18_DIBDI12": { + "src_wire": "BRAM_IMUX17_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_CASCADEOUTA->BRAM_FIFO36_CASCADEOUTA_1": { + "src_wire": "BRAM_FIFO36_CASCADEOUTA", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CASCADEOUTA_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX40_2->BRAM_FIFO36_DIADIL7": { + "src_wire": "BRAM_IMUX40_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO13->BRAM_LOGIC_OUTS_B2_1": { + "src_wire": "BRAM_FIFO18_DOADO13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX23_4->BRAM_RAMB18_DIBDI15": { + "src_wire": "BRAM_IMUX23_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX24_2->BRAM_FIFO36_WEAU1": { + "src_wire": "BRAM_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL7->>BRAM_UTURN_ADDRBWRADDRL7": { + "src_wire": "BRAM_ADDRBWRADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_FULL->BRAM_LOGIC_OUTS_B5_2": { + "src_wire": "BRAM_FIFO36_FULL", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU6->>BRAM_FIFO36_ADDRBWRADDRU6": { + "src_wire": "BRAM_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU4->>BRAM_RAMB18_ADDRARDADDR3": { + "src_wire": "BRAM_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU2->BRAM_LOGIC_OUTS_B1_3": { + "src_wire": "BRAM_FIFO36_DOBDOU2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU2->BRAM_LOGIC_OUTS_B13_3": { + "src_wire": "BRAM_FIFO36_DOADOU2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX10_0->BRAM_FIFO36_TSTCNT0": { + "src_wire": "BRAM_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX23_1->BRAM_R_IMUX_ADDRARDADDRL13": { + "src_wire": "BRAM_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX28_0->BRAM_FIFO18_DIADI2": { + "src_wire": "BRAM_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO9->BRAM_LOGIC_OUTS_B5_0": { + "src_wire": "BRAM_FIFO18_DOADO9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX44_3->BRAM_RAMB18_DIADI3": { + "src_wire": "BRAM_IMUX44_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOPBDOPU0->BRAM_LOGIC_OUTS_B3_3": { + "src_wire": "BRAM_FIFO36_DOPBDOPU0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL5->BRAM_LOGIC_OUTS_B10_1": { + "src_wire": "BRAM_FIFO36_DOADOL5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX6_1->BRAM_FIFO18_DIBDI6": { + "src_wire": "BRAM_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU14->BRAM_LOGIC_OUTS_B2_4": { + "src_wire": "BRAM_FIFO36_DOADOU14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU13->>BRAM_RAMB18_ADDRARDADDR12": { + "src_wire": "BRAM_ADDRARDADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_FIFO18_ADDRATIEHIGH1": { + "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL12->>BRAM_FIFO36_ADDRBWRADDRL12": { + "src_wire": "BRAM_ADDRBWRADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX33_0->BRAM_FIFO36_DIBDIL8": { + "src_wire": "BRAM_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX5_0->BRAM_FIFO36_TSTFLAGIN": { + "src_wire": "BRAM_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTFLAGIN", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX45_1->BRAM_FIFO36_DIADIL6": { + "src_wire": "BRAM_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO5->BRAM_LOGIC_OUTS_B6_1": { + "src_wire": "BRAM_FIFO18_DOBDO5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU0->BRAM_LOGIC_OUTS_B3_2": { + "src_wire": "BRAM_FIFO36_DOBDOU0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL10->>BRAM_FIFO36_ADDRBWRADDRL10": { + "src_wire": "BRAM_ADDRBWRADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX22_3->BRAM_R_IMUX_ADDRARDADDRL14": { + "src_wire": "BRAM_IMUX22_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU3->>BRAM_FIFO36_ADDRARDADDRU3": { + "src_wire": "BRAM_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX5_4->BRAM_FIFO36_TSTIN0": { + "src_wire": "BRAM_IMUX5_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX23_4->BRAM_FIFO36_DIBDIU15": { + "src_wire": "BRAM_IMUX23_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX34_4->BRAM_FIFO36_TSTRDOS8": { + "src_wire": "BRAM_IMUX34_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO3->BRAM_LOGIC_OUTS_B15_0": { + "src_wire": "BRAM_FIFO18_DOADO3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_WRERR->BRAM_LOGIC_OUTS_B23_2": { + "src_wire": "BRAM_FIFO18_WRERR", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL3->>BRAM_FIFO36_ADDRBWRADDRL3": { + "src_wire": "BRAM_ADDRBWRADDRL3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO8->BRAM_LOGIC_OUTS_B22_0": { + "src_wire": "BRAM_FIFO18_DOBDO8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU4->>BRAM_CASCOUT_ADDRARDADDRU4": { + "src_wire": "BRAM_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { + "src_wire": "BRAM_FIFO36_WRCOUNT0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX19_2->BRAM_FIFO18_REGCEAREGCE": { + "src_wire": "BRAM_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCEAREGCE", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU3->BRAM_LOGIC_OUTS_B6_3": { + "src_wire": "BRAM_FIFO36_DOBDOU3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL7->>BRAM_UTURN_ADDRARDADDRL7": { + "src_wire": "BRAM_ADDRARDADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU14->>BRAM_CASCOUT_ADDRBWRADDRU14": { + "src_wire": "BRAM_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX44_1->BRAM_FIFO36_DIADIL13": { + "src_wire": "BRAM_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX46_4->BRAM_FIFO36_TSTWROS12": { + "src_wire": "BRAM_IMUX46_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOPADOP0->BRAM_LOGIC_OUTS_B8_1": { + "src_wire": "BRAM_FIFO18_DOPADOP0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL9->>BRAM_FIFO18_ADDRARDADDR8": { + "src_wire": "BRAM_ADDRARDADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL0_1->BRAM_FIFO18_RSTRAMB": { + "src_wire": "BRAM_CTRL0_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTRAMB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX38_1->BRAM_R_IMUX_ADDRBWRADDRL11": { + "src_wire": "BRAM_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU8->BRAM_LOGIC_OUTS_B17_2": { + "src_wire": "BRAM_FIFO36_DOBDOU8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL14->>BRAM_FIFO18_ADDRBWRADDR13": { + "src_wire": "BRAM_ADDRBWRADDRL14", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX45_2->BRAM_RAMB18_WEBWE3": { + "src_wire": "BRAM_IMUX45_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX26_0->BRAM_FIFO36_DIADIL1": { + "src_wire": "BRAM_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU12->>BRAM_FIFO36_ADDRBWRADDRU12": { + "src_wire": "BRAM_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL12->>BRAM_UTURN_ADDRARDADDRL12": { + "src_wire": "BRAM_ADDRARDADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX25_4->BRAM_FIFO36_TSTCNT7": { + "src_wire": "BRAM_IMUX25_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX21_2->BRAM_FIFO36_WEBWEL1": { + "src_wire": "BRAM_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU12->>BRAM_UTURN_ADDRBWRADDRU12": { + "src_wire": "BRAM_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX11_2->BRAM_RAMB18_REGCEAREGCE": { + "src_wire": "BRAM_IMUX11_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCEAREGCE", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL5->>BRAM_UTURN_ADDRBWRADDRL5": { + "src_wire": "BRAM_ADDRBWRADDRL5", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX13_1->BRAM_R_IMUX_ADDRARDADDRU4": { + "src_wire": "BRAM_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { + "src_wire": "BRAM_FIFO36_RDCOUNT6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX43_3->BRAM_RAMB18_DIADI10": { + "src_wire": "BRAM_IMUX43_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL2->BRAM_LOGIC_OUTS_B6_0": { + "src_wire": "BRAM_FIFO36_DOBDOL2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX32_2->BRAM_FIFO18_WEA1": { + "src_wire": "BRAM_IMUX32_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX8_0->BRAM_FIFO36_TSTIN3": { + "src_wire": "BRAM_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU6->BRAM_LOGIC_OUTS_B6_4": { + "src_wire": "BRAM_FIFO36_DOBDOU6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX15_2->BRAM_RAMB18_DIADI8": { + "src_wire": "BRAM_IMUX15_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOPBDOPU1->BRAM_LOGIC_OUTS_B17_3": { + "src_wire": "BRAM_FIFO36_DOPBDOPU1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU2->>BRAM_CASCOUT_ADDRARDADDRU2": { + "src_wire": "BRAM_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU11->BRAM_LOGIC_OUTS_B2_3": { + "src_wire": "BRAM_FIFO36_DOADOU11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX28_0->BRAM_FIFO36_DIADIL2": { + "src_wire": "BRAM_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO15->BRAM_LOGIC_OUTS_B17_4": { + "src_wire": "BRAM_RAMB18_DOBDO15", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { + "src_wire": "BRAM_FIFO36_ALMOSTEMPTY", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOPADOPL1->BRAM_LOGIC_OUTS_B0_1": { + "src_wire": "BRAM_FIFO36_DOPADOPL1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU11->>BRAM_FIFO36_ADDRBWRADDRU11": { + "src_wire": "BRAM_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU7->>BRAM_RAMB18_ADDRARDADDR6": { + "src_wire": "BRAM_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU1->>BRAM_CASCOUT_ADDRBWRADDRU1": { + "src_wire": "BRAM_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX46_1->BRAM_FIFO18_DIADI14": { + "src_wire": "BRAM_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU13->>BRAM_FIFO36_ADDRBWRADDRU13": { + "src_wire": "BRAM_ADDRBWRADDRU13", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { + "src_wire": "BRAM_FIFO18_RDCOUNT10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX16_4->BRAM_FIFO36_DIBDIU4": { + "src_wire": "BRAM_IMUX16_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOPBDOP1->BRAM_LOGIC_OUTS_B17_3": { + "src_wire": "BRAM_RAMB18_DOPBDOP1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU8->>BRAM_CASCOUT_ADDRARDADDRU8": { + "src_wire": "BRAM_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX30_3->BRAM_R_IMUX_ADDRBWRADDRU14": { + "src_wire": "BRAM_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX45_1->BRAM_FIFO18_DIADI6": { + "src_wire": "BRAM_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU11->BRAM_LOGIC_OUTS_B20_3": { + "src_wire": "BRAM_FIFO36_DOBDOU11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO11->BRAM_LOGIC_OUTS_B17_0": { + "src_wire": "BRAM_FIFO18_DOBDO11", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX18_3->BRAM_R_IMUX_ADDRARDADDRL3": { + "src_wire": "BRAM_IMUX18_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { + "src_wire": "BRAM_FIFO36_WRCOUNT2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU8->BRAM_LOGIC_OUTS_B7_2": { + "src_wire": "BRAM_FIFO36_DOADOU8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL12->>BRAM_FIFO18_ADDRBWRADDR11": { + "src_wire": "BRAM_ADDRBWRADDRL12", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FAN1_2->BRAM_RAMB18_WEBWE4": { + "src_wire": "BRAM_FAN1_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX2_2->BRAM_FIFO36_DIBDIL15": { + "src_wire": "BRAM_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX30_1->BRAM_R_IMUX_ADDRBWRADDRU11": { + "src_wire": "BRAM_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK0_1->BRAM_FIFO18_CLKBWRCLK": { + "src_wire": "BRAM_CLK0_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_CLKBWRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_TSTOUT0->BRAM_LOGIC_OUTS_B18_1": { + "src_wire": "BRAM_FIFO36_TSTOUT0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU12->>BRAM_UTURN_ADDRARDADDRU12": { + "src_wire": "BRAM_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY0->BRAM_LOGIC_OUTS_B18_3": { + "src_wire": "BRAM_FIFO36_ECCPARITY0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU5->>BRAM_FIFO36_ADDRBWRADDRU5": { + "src_wire": "BRAM_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL9->BRAM_ADDRBWRADDRL9": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX11_4->BRAM_RAMB18_DIADI13": { + "src_wire": "BRAM_IMUX11_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO10->BRAM_LOGIC_OUTS_B19_3": { + "src_wire": "BRAM_RAMB18_DOBDO10", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX25_3->BRAM_R_IMUX_ADDRBWRADDRU7": { + "src_wire": "BRAM_IMUX25_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU10->>BRAM_FIFO36_ADDRARDADDRU10": { + "src_wire": "BRAM_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX11_4->BRAM_FIFO36_DIADIU13": { + "src_wire": "BRAM_IMUX11_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { + "src_wire": "BRAM_FIFO18_WRCOUNT8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX13_0->BRAM_FIFO36_TSTCNT3": { + "src_wire": "BRAM_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU7->>BRAM_UTURN_ADDRBWRADDRU7": { + "src_wire": "BRAM_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL9->>BRAM_FIFO18_ADDRBWRADDR8": { + "src_wire": "BRAM_ADDRBWRADDRL9", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL6->>BRAM_UTURN_ADDRARDADDRL6": { + "src_wire": "BRAM_ADDRARDADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK1_4->BRAM_FIFO36_REGCLKARDRCLKU": { + "src_wire": "BRAM_CLK1_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX6_2->BRAM_FIFO36_WEBWEL4": { + "src_wire": "BRAM_IMUX6_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL6->>BRAM_FIFO36_ADDRARDADDRL6": { + "src_wire": "BRAM_ADDRARDADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX31_2->BRAM_FIFO36_INJECTDBITERR": { + "src_wire": "BRAM_IMUX31_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_INJECTDBITERR", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU10->>BRAM_CASCOUT_ADDRBWRADDRU10": { + "src_wire": "BRAM_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO13->BRAM_LOGIC_OUTS_B5_4": { + "src_wire": "BRAM_RAMB18_DOADO13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX22_4->BRAM_RAMB18_DIBDI7": { + "src_wire": "BRAM_IMUX22_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY4->BRAM_LOGIC_OUTS_B10_2": { + "src_wire": "BRAM_FIFO36_ECCPARITY4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_CASCOUT_ADDRBWRADDRU9": { + "src_wire": "BRAM_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { + "src_wire": "BRAM_FIFO36_WRCOUNT1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU9->>BRAM_CASCOUT_ADDRARDADDRU9": { + "src_wire": "BRAM_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX16_1->BRAM_FIFO36_DIADIL0": { + "src_wire": "BRAM_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL6->BRAM_LOGIC_OUTS_B3_1": { + "src_wire": "BRAM_FIFO36_DOBDOL6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX10_2->BRAM_RAMB18_ENARDEN": { + "src_wire": "BRAM_IMUX10_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ENARDEN", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU3->>BRAM_UTURN_ADDRBWRADDRU3": { + "src_wire": "BRAM_ADDRBWRADDRU3", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX35_3->BRAM_R_IMUX_ADDRBWRADDRL9": { + "src_wire": "BRAM_IMUX35_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX37_3->BRAM_R_IMUX_ADDRBWRADDRL12": { + "src_wire": "BRAM_IMUX37_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX22_4->BRAM_FIFO36_DIBDIU7": { + "src_wire": "BRAM_IMUX22_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO9->BRAM_LOGIC_OUTS_B19_0": { + "src_wire": "BRAM_FIFO18_DOBDO9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY7->BRAM_LOGIC_OUTS_B11_3": { + "src_wire": "BRAM_FIFO36_ECCPARITY7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX9_4->BRAM_RAMB18_DIADI12": { + "src_wire": "BRAM_IMUX9_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL2->>BRAM_FIFO36_ADDRARDADDRL2": { + "src_wire": "BRAM_ADDRARDADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX46_2->BRAM_FIFO36_WEBWEU7": { + "src_wire": "BRAM_IMUX46_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK1_3->BRAM_RAMB18_CLKARDCLK": { + "src_wire": "BRAM_CLK1_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_CLKARDCLK", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX6_3->BRAM_FIFO36_DIBDIU11": { + "src_wire": "BRAM_IMUX6_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX1_1->BRAM_FIFO18_DIPBDIP1": { + "src_wire": "BRAM_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPBDIP1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL0->>BRAM_FIFO36_ADDRARDADDRL0": { + "src_wire": "BRAM_ADDRARDADDRL0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX35_1->BRAM_R_IMUX_ADDRBWRADDRL2": { + "src_wire": "BRAM_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL10->>BRAM_FIFO36_ADDRARDADDRL10": { + "src_wire": "BRAM_ADDRARDADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX22_0->BRAM_FIFO36_TSTRDOS4": { + "src_wire": "BRAM_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL8->BRAM_LOGIC_OUTS_B22_0": { + "src_wire": "BRAM_FIFO36_DOBDOL8", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX26_2->BRAM_FIFO36_ENBWRENU": { + "src_wire": "BRAM_IMUX26_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENBWRENU", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX38_0->BRAM_FIFO18_DIBDI3": { + "src_wire": "BRAM_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO4->BRAM_LOGIC_OUTS_B8_4": { + "src_wire": "BRAM_RAMB18_DOADO4", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL1->>BRAM_UTURN_ADDRARDADDRL1": { + "src_wire": "BRAM_ADDRARDADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU7->BRAM_LOGIC_OUTS_B15_4": { + "src_wire": "BRAM_FIFO36_DOADOU7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_TSTOUT1->BRAM_LOGIC_OUTS_B18_0": { + "src_wire": "BRAM_FIFO36_TSTOUT1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX3_3->BRAM_RAMB18_DIBDI2": { + "src_wire": "BRAM_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU8->>BRAM_UTURN_ADDRARDADDRU8": { + "src_wire": "BRAM_ADDRARDADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO12->BRAM_LOGIC_OUTS_B22_4": { + "src_wire": "BRAM_RAMB18_DOBDO12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_TSTOUT3->BRAM_LOGIC_OUTS_B11_1": { + "src_wire": "BRAM_FIFO36_TSTOUT3", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX32_1->BRAM_FIFO36_DIBDIL0": { + "src_wire": "BRAM_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX17_4->BRAM_FIFO36_DIBDIU12": { + "src_wire": "BRAM_IMUX17_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX22_1->BRAM_R_IMUX_ADDRARDADDRL11": { + "src_wire": "BRAM_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { + "src_wire": "BRAM_FIFO36_WRCOUNT5", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL2->>BRAM_UTURN_ADDRBWRADDRL2": { + "src_wire": "BRAM_ADDRBWRADDRL2", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL14->BRAM_LOGIC_OUTS_B17_1": { + "src_wire": "BRAM_FIFO36_DOBDOL14", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX31_0->BRAM_FIFO36_DIADIL11": { + "src_wire": "BRAM_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO0->BRAM_LOGIC_OUTS_B15_2": { + "src_wire": "BRAM_RAMB18_DOADO0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX43_3->BRAM_FIFO36_DIADIU10": { + "src_wire": "BRAM_IMUX43_3", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { + "src_wire": "BRAM_FIFO18_WRCOUNT7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CTRL0_1->BRAM_FIFO36_RSTRAMBL": { + "src_wire": "BRAM_CTRL0_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMBL", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL11->BRAM_ADDRBWRADDRL11": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL11", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX8_2->BRAM_FIFO36_WEAU0": { + "src_wire": "BRAM_IMUX8_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX6_3->BRAM_RAMB18_DIBDI11": { + "src_wire": "BRAM_IMUX6_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX36_3->BRAM_R_IMUX_ADDRBWRADDRL5": { + "src_wire": "BRAM_IMUX36_3", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX4_2->BRAM_FIFO18_DIPBDIP0": { + "src_wire": "BRAM_IMUX4_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPBDIP0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX34_0->BRAM_FIFO18_DIBDI1": { + "src_wire": "BRAM_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX26_0->BRAM_FIFO18_DIADI1": { + "src_wire": "BRAM_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX33_2->BRAM_FIFO18_WEA3": { + "src_wire": "BRAM_IMUX33_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRERR->BRAM_LOGIC_OUTS_B23_2": { + "src_wire": "BRAM_FIFO36_WRERR", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX23_2->BRAM_FIFO36_DIBDIU8": { + "src_wire": "BRAM_IMUX23_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOADO2->BRAM_LOGIC_OUTS_B10_0": { + "src_wire": "BRAM_FIFO18_DOADO2", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOBDO1->BRAM_LOGIC_OUTS_B4_3": { + "src_wire": "BRAM_RAMB18_DOBDO1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL13->BRAM_LOGIC_OUTS_B20_1": { + "src_wire": "BRAM_FIFO36_DOBDOL13", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_BYP6_2->BRAM_FIFO36_WEBWEL7": { + "src_wire": "BRAM_BYP6_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL8->>BRAM_UTURN_ADDRARDADDRL8": { + "src_wire": "BRAM_ADDRARDADDRL8", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL6->BRAM_ADDRBWRADDRL6": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX21_1->BRAM_R_IMUX_ADDRARDADDRL4": { + "src_wire": "BRAM_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX21_4->BRAM_RAMB18_DIBDI14": { + "src_wire": "BRAM_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX39_3->BRAM_IMUX_R_ADDRBWRADDRL15": { + "src_wire": "BRAM_IMUX39_3", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU12->>BRAM_RAMB18_ADDRBWRADDR11": { + "src_wire": "BRAM_ADDRBWRADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { + "src_wire": "BRAM_FIFO36_RDCOUNT7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU8", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX40_4->BRAM_FIFO36_TSTWROS6": { + "src_wire": "BRAM_IMUX40_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL1->>BRAM_UTURN_ADDRBWRADDRL1": { + "src_wire": "BRAM_ADDRBWRADDRL1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { + "src_wire": "BRAM_FIFO36_WRCOUNT9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU12", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL9->BRAM_LOGIC_OUTS_B5_0": { + "src_wire": "BRAM_FIFO36_DOADOL9", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL7->BRAM_ADDRBWRADDRL7": { + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL7", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL7", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX37_4->BRAM_FIFO36_TSTRDOS11": { + "src_wire": "BRAM_IMUX37_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS11", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX31_1->BRAM_R_IMUX_ADDRBWRADDRU13": { + "src_wire": "BRAM_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU5->>BRAM_UTURN_ADDRBWRADDRU5": { + "src_wire": "BRAM_ADDRBWRADDRU5", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX32_2->BRAM_FIFO36_WEAL1": { + "src_wire": "BRAM_IMUX32_2", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX27_2->BRAM_RAMB18_REGCEB": { + "src_wire": "BRAM_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCEB", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU14->>BRAM_RAMB18_ADDRARDADDR13": { + "src_wire": "BRAM_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR13", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX24_2->BRAM_RAMB18_WEA1": { + "src_wire": "BRAM_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX13_4->BRAM_RAMB18_DIADI14": { + "src_wire": "BRAM_IMUX13_4", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU9->>BRAM_RAMB18_ADDRARDADDR8": { + "src_wire": "BRAM_ADDRARDADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX7_1->BRAM_FIFO36_DIBDIL14": { + "src_wire": "BRAM_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX27_0->BRAM_FIFO18_DIADI9": { + "src_wire": "BRAM_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO7->BRAM_LOGIC_OUTS_B15_4": { + "src_wire": "BRAM_RAMB18_DOADO7", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_4", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRU14->>BRAM_UTURN_ADDRARDADDRU14": { + "src_wire": "BRAM_ADDRARDADDRU14", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU14", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { + "src_wire": "BRAM_FIFO36_RDCOUNT0", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL12->BRAM_LOGIC_OUTS_B5_1": { + "src_wire": "BRAM_FIFO36_DOADOL12", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_UTURN_ADDRBWRADDRU9": { + "src_wire": "BRAM_ADDRBWRADDRU9", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU9", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_IMUX5_3->BRAM_RAMB18_DIBDI3": { + "src_wire": "BRAM_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI3", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU0", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU7->>BRAM_RAMB18_ADDRBWRADDR6": { + "src_wire": "BRAM_ADDRBWRADDRU7", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO6->BRAM_LOGIC_OUTS_B3_1": { + "src_wire": "BRAM_FIFO18_DOBDO6", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_1", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL6->>BRAM_FIFO18_ADDRBWRADDR5": { + "src_wire": "BRAM_ADDRBWRADDRL6", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CLK0_4->BRAM_FIFO18_REGCLKARDRCLK": { + "src_wire": "BRAM_CLK0_4", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCLKARDRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_ADDRARDADDRL10->>BRAM_UTURN_ADDRARDADDRL10": { + "src_wire": "BRAM_ADDRARDADDRL10", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL10", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL2", + "is_directional": "1", + "can_invert": "0" + }, + "BRAM_R.BRAM_RAMB18_DOADO1->BRAM_LOGIC_OUTS_B8_3": { + "src_wire": "BRAM_RAMB18_DOADO1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_3", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_BRKH_BRAM.json b/kintex7/tile_type_BRKH_BRAM.json new file mode 100644 index 0000000..4493e69 --- /dev/null +++ b/kintex7/tile_type_BRKH_BRAM.json @@ -0,0 +1,71 @@ +{ + "tile_type": "BRKH_BRAM", + "sites": [], + "wires": [ + "BRKH_BRAM_CASCADEA_L", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1", + "BRKH_BRAM_CASCADEA_R", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9", + "BRKH_BRAM_CASCADEB_L", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12", + "BRKH_BRAM_CASCADEB_R", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_BRKH_B_TERM_INT.json b/kintex7/tile_type_BRKH_B_TERM_INT.json new file mode 100644 index 0000000..fc617f4 --- /dev/null +++ b/kintex7/tile_type_BRKH_B_TERM_INT.json @@ -0,0 +1,125 @@ +{ + "tile_type": "BRKH_B_TERM_INT", + "sites": [], + "wires": [ + "B_TERM_UTURN_INT_SW6D0", + "B_TERM_UTURN_INT_SS6A1", + "B_TERM_UTURN_INT_LVB5", + "B_TERM_UTURN_INT_SS2BEG2", + "B_TERM_UTURN_INT_LV8", + "B_TERM_UTURN_INT_SW2BEG2", + "B_TERM_UTURN_INT_SS6E0", + "B_TERM_UTURN_INT_SE6A0", + "B_TERM_UTURN_INT_SS6B3", + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "B_TERM_UTURN_INT_SS6A2", + "B_TERM_UTURN_INT_LV9", + "B_TERM_UTURN_INT_SS6B0", + "B_TERM_UTURN_INT_SR1BEG3", + "B_TERM_UTURN_INT_LV_L2", + "B_TERM_UTURN_INT_SS6BEG3", + "B_TERM_UTURN_INT_LVB_L4", + "B_TERM_UTURN_INT_SW6A2", + "B_TERM_UTURN_INT_SE6C0", + "B_TERM_UTURN_INT_LVB_L5", + "B_TERM_UTURN_INT_ER1BEG0", + "B_TERM_UTURN_INT_LVB1", + "B_TERM_UTURN_INT_LVB_L3", + "B_TERM_UTURN_INT_SE6C3", + "B_TERM_UTURN_INT_SS6C3", + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "B_TERM_UTURN_INT_LV_L9", + "B_TERM_UTURN_INT_SS6D0", + "B_TERM_UTURN_INT_LV2", + "B_TERM_UTURN_INT_LVB_L1", + "B_TERM_UTURN_INT_SS6E2", + "B_TERM_UTURN_INT_SE6D3", + "B_TERM_UTURN_INT_SW6D3", + "B_TERM_UTURN_INT_LVB0", + "B_TERM_UTURN_INT_SS2BEG0", + "B_TERM_UTURN_INT_SS6D2", + "B_TERM_UTURN_INT_SR1BEG1", + "B_TERM_UTURN_INT_SS6E3", + "B_TERM_UTURN_INT_SW2BEG0", + "B_TERM_UTURN_INT_SS6D1", + "B_TERM_UTURN_INT_LVB2", + "B_TERM_UTURN_INT_SS6BEG1", + "B_TERM_UTURN_INT_SE6D2", + "B_TERM_UTURN_INT_SR1BEG2", + "B_TERM_UTURN_INT_SL1BEG1", + "B_TERM_UTURN_INT_SE6B1", + "B_TERM_UTURN_INT_LV_L7", + "B_TERM_UTURN_INT_LVB_L2", + "B_TERM_UTURN_INT_SW6A0", + "B_TERM_UTURN_INT_SW6A1", + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "B_TERM_UTURN_INT_LV_L8", + "B_TERM_UTURN_INT_SW6C3", + "B_TERM_UTURN_INT_SW6B2", + "B_TERM_UTURN_INT_SS6B2", + "B_TERM_UTURN_INT_SS6BEG2", + "B_TERM_UTURN_INT_SS6BEG0", + "B_TERM_UTURN_INT_LVB3", + "B_TERM_UTURN_INT_SE6B3", + "B_TERM_UTURN_INT_SS2BEG3", + "B_TERM_UTURN_INT_SS2A0", + "B_TERM_UTURN_INT_LV3", + "B_TERM_UTURN_INT_SW6C1", + "B_TERM_UTURN_INT_LV7", + "B_TERM_UTURN_INT_SS6C0", + "B_TERM_UTURN_INT_LV_L5", + "B_TERM_UTURN_INT_SE6B0", + "B_TERM_UTURN_INT_SE2BEG1", + "B_TERM_UTURN_INT_SE6A3", + "B_TERM_UTURN_INT_SW6B1", + "B_TERM_UTURN_INT_SW6A3", + "B_TERM_UTURN_INT_SE2BEG0", + "B_TERM_UTURN_INT_SS6B1", + "B_TERM_UTURN_INT_SE6C2", + "B_TERM_UTURN_INT_SW6D2", + "B_TERM_UTURN_INT_SW2BEG1", + "B_TERM_UTURN_INT_SE6B2", + "B_TERM_UTURN_INT_SW6D1", + "B_TERM_UTURN_INT_SW6C0", + "B_TERM_UTURN_INT_ER1END_N3_3", + "B_TERM_UTURN_INT_SE6A2", + "B_TERM_UTURN_INT_LV_L4", + "B_TERM_UTURN_INT_SW2BEG3", + "B_TERM_UTURN_INT_SS6A3", + "B_TERM_UTURN_INT_SL1BEG0", + "B_TERM_UTURN_INT_SE6A1", + "B_TERM_UTURN_INT_LV4", + "B_TERM_UTURN_INT_SS2A2", + "B_TERM_UTURN_INT_SE6C1", + "B_TERM_UTURN_INT_SS2BEG1", + "B_TERM_UTURN_INT_LVB_L0", + "B_TERM_UTURN_INT_SS6A0", + "B_TERM_UTURN_INT_SE6D1", + "B_TERM_UTURN_INT_SE2BEG3", + "B_TERM_UTURN_INT_SL1BEG3", + "B_TERM_UTURN_INT_LV_L3", + "B_TERM_UTURN_INT_SW6B0", + "B_TERM_UTURN_INT_LV5", + "B_TERM_UTURN_INT_LVB4", + "B_TERM_UTURN_INT_WR1END0", + "B_TERM_UTURN_INT_LV_L6", + "B_TERM_UTURN_INT_LV_L18", + "B_TERM_UTURN_INT_SE2BEG2", + "B_TERM_UTURN_INT_SS2A3", + "B_TERM_UTURN_INT_SW6B3", + "B_TERM_UTURN_INT_SS6C1", + "B_TERM_UTURN_INT_WR1BEG0", + "B_TERM_UTURN_INT_SE6D0", + "B_TERM_UTURN_INT_SL1BEG2", + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "B_TERM_UTURN_INT_SW6END_N0_3", + "B_TERM_UTURN_INT_SS6E1", + "B_TERM_UTURN_INT_SS6C2", + "B_TERM_UTURN_INT_SS6D3", + "B_TERM_UTURN_INT_LV6", + "B_TERM_UTURN_INT_SS2A1", + "B_TERM_UTURN_INT_SW6C2", + "B_TERM_UTURN_INT_LV18" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_BRKH_CLB.json b/kintex7/tile_type_BRKH_CLB.json new file mode 100644 index 0000000..129d073 --- /dev/null +++ b/kintex7/tile_type_BRKH_CLB.json @@ -0,0 +1,11 @@ +{ + "tile_type": "BRKH_CLB", + "sites": [], + "wires": [ + "BRKH_CLB_COUT1_R", + "BRKH_CLB_COUT0_R", + "BRKH_CLB_COUT0_L", + "BRKH_CLB_COUT1_L" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_BRKH_CLK.json b/kintex7/tile_type_BRKH_CLK.json new file mode 100644 index 0000000..2f98d99 --- /dev/null +++ b/kintex7/tile_type_BRKH_CLK.json @@ -0,0 +1,135 @@ +{ + "tile_type": "BRKH_CLK", + "sites": [], + "wires": [ + "BRKH_CLK_CK_BUFG_CASC28", + "BRKH_CLK_R_CK_BUFG_CASC8", + "BRKH_CLK_R_CK_BUFG_CASC19", + "BRKH_CLK_CK_GCLK16", + "BRKH_CLK_CK_GCLK13", + "BRKH_CLK_R_CK_BUFG_CASC29", + "BRKH_CLK_R_CK_GCLK2", + "BRKH_CLK_R_CK_GCLK27", + "BRKH_CLK_CK_BUFG_CASC10", + "BRKH_CLK_CK_GCLK22", + "BRKH_CLK_R_CK_BUFG_CASC11", + "BRKH_CLK_R_CK_BUFG_CASC3", + "BRKH_CLK_CK_GCLK10", + "BRKH_CLK_R_CK_GCLK13", + "BRKH_CLK_CK_GCLK0", + "BRKH_CLK_CK_BUFG_CASC17", + "BRKH_CLK_R_CK_GCLK11", + "BRKH_CLK_CK_GCLK30", + "BRKH_CLK_CK_BUFG_CASC30", + "BRKH_CLK_CK_BUFG_CASC18", + "BRKH_CLK_CK_BUFG_CASC26", + "BRKH_CLK_R_CK_BUFG_CASC1", + "BRKH_CLK_CK_BUFG_CASC11", + "BRKH_CLK_CK_GCLK29", + "BRKH_CLK_CK_GCLK26", + "BRKH_CLK_CK_BUFG_CASC31", + "BRKH_CLK_R_CK_GCLK10", + "BRKH_CLK_R_CK_GCLK15", + "BRKH_CLK_CK_BUFG_CASC20", + "BRKH_CLK_R_CK_BUFG_CASC17", + "BRKH_CLK_R_CK_GCLK24", + "BRKH_CLK_R_CK_BUFG_CASC15", + "BRKH_CLK_R_CK_BUFG_CASC10", + "BRKH_CLK_R_CK_BUFG_CASC16", + "BRKH_CLK_CK_BUFG_CASC14", + "BRKH_CLK_CK_GCLK15", + "BRKH_CLK_CK_GCLK1", + "BRKH_CLK_R_CK_BUFG_CASC2", + "BRKH_CLK_R_CK_BUFG_CASC13", + "BRKH_CLK_CK_BUFG_CASC3", + "BRKH_CLK_R_CK_GCLK29", + "BRKH_CLK_CK_BUFG_CASC5", + "BRKH_CLK_CK_BUFG_CASC1", + "BRKH_CLK_R_CK_BUFG_CASC14", + "BRKH_CLK_R_CK_GCLK31", + "BRKH_CLK_R_CK_BUFG_CASC27", + "BRKH_CLK_R_CK_GCLK18", + "BRKH_CLK_R_CK_BUFG_CASC21", + "BRKH_CLK_CK_BUFG_CASC6", + "BRKH_CLK_CK_BUFG_CASC8", + "BRKH_CLK_R_CK_GCLK25", + "BRKH_CLK_CK_GCLK4", + "BRKH_CLK_CK_GCLK23", + "BRKH_CLK_CK_GCLK6", + "BRKH_CLK_CK_GCLK3", + "BRKH_CLK_R_CK_BUFG_CASC20", + "BRKH_CLK_CK_BUFG_CASC16", + "BRKH_CLK_R_CK_BUFG_CASC28", + "BRKH_CLK_R_CK_BUFG_CASC30", + "BRKH_CLK_CK_GCLK14", + "BRKH_CLK_R_CK_GCLK17", + "BRKH_CLK_CK_BUFG_CASC21", + "BRKH_CLK_CK_BUFG_CASC29", + "BRKH_CLK_CK_GCLK5", + "BRKH_CLK_R_CK_BUFG_CASC26", + "BRKH_CLK_R_CK_GCLK28", + "BRKH_CLK_R_CK_BUFG_CASC12", + "BRKH_CLK_CK_BUFG_CASC12", + "BRKH_CLK_CK_GCLK12", + "BRKH_CLK_R_CK_GCLK4", + "BRKH_CLK_R_CK_GCLK3", + "BRKH_CLK_CK_BUFG_CASC13", + "BRKH_CLK_CK_GCLK9", + "BRKH_CLK_R_CK_GCLK7", + "BRKH_CLK_CK_GCLK24", + "BRKH_CLK_CK_BUFG_CASC7", + "BRKH_CLK_CK_GCLK7", + "BRKH_CLK_CK_BUFG_CASC25", + "BRKH_CLK_R_CK_GCLK19", + "BRKH_CLK_R_CK_GCLK23", + "BRKH_CLK_R_CK_BUFG_CASC5", + "BRKH_CLK_R_CK_GCLK20", + "BRKH_CLK_R_CK_GCLK0", + "BRKH_CLK_R_CK_GCLK16", + "BRKH_CLK_R_CK_GCLK6", + "BRKH_CLK_CK_GCLK27", + "BRKH_CLK_R_CK_BUFG_CASC6", + "BRKH_CLK_R_CK_BUFG_CASC22", + "BRKH_CLK_CK_GCLK28", + "BRKH_CLK_CK_BUFG_CASC22", + "BRKH_CLK_R_CK_BUFG_CASC18", + "BRKH_CLK_R_CK_BUFG_CASC24", + "BRKH_CLK_R_CK_GCLK5", + "BRKH_CLK_R_CK_GCLK9", + "BRKH_CLK_R_CK_BUFG_CASC7", + "BRKH_CLK_CK_GCLK17", + "BRKH_CLK_CK_GCLK19", + "BRKH_CLK_CK_BUFG_CASC2", + "BRKH_CLK_CK_BUFG_CASC19", + "BRKH_CLK_CK_BUFG_CASC9", + "BRKH_CLK_CK_GCLK21", + "BRKH_CLK_CK_GCLK31", + "BRKH_CLK_CK_GCLK20", + "BRKH_CLK_R_CK_BUFG_CASC23", + "BRKH_CLK_CK_BUFG_CASC4", + "BRKH_CLK_CK_GCLK2", + "BRKH_CLK_R_CK_BUFG_CASC9", + "BRKH_CLK_R_CK_GCLK21", + "BRKH_CLK_R_CK_BUFG_CASC25", + "BRKH_CLK_R_CK_GCLK1", + "BRKH_CLK_R_CK_BUFG_CASC4", + "BRKH_CLK_CK_GCLK18", + "BRKH_CLK_R_CK_GCLK14", + "BRKH_CLK_CK_BUFG_CASC24", + "BRKH_CLK_CK_BUFG_CASC0", + "BRKH_CLK_R_CK_GCLK12", + "BRKH_CLK_CK_BUFG_CASC15", + "BRKH_CLK_R_CK_GCLK8", + "BRKH_CLK_CK_GCLK11", + "BRKH_CLK_CK_GCLK8", + "BRKH_CLK_R_CK_GCLK26", + "BRKH_CLK_CK_GCLK25", + "BRKH_CLK_R_CK_BUFG_CASC31", + "BRKH_CLK_CK_BUFG_CASC23", + "BRKH_CLK_R_CK_BUFG_CASC0", + "BRKH_CLK_R_CK_GCLK22", + "BRKH_CLK_CK_BUFG_CASC27", + "BRKH_CLK_R_CK_GCLK30" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_BRKH_CMT.json b/kintex7/tile_type_BRKH_CMT.json new file mode 100644 index 0000000..f08b844 --- /dev/null +++ b/kintex7/tile_type_BRKH_CMT.json @@ -0,0 +1,16 @@ +{ + "tile_type": "BRKH_CMT", + "sites": [], + "wires": [ + "BRKH_CMT_FREQ_REF_NS3", + "BRKH_CMT_FREQ_REF_NS2", + "BRKH_CMT_PHYCTRL_SYNC_BB", + "BRKH_CMT_PHASEREF_BELOW1", + "BRKH_CMT_FREQ_REF_NS1", + "BRKH_CMT_FREQ_REF_NS0", + "BRKH_CMT_PHASEREF0", + "BRKH_CMT_PHASEREF1", + "BRKH_CMT_PHASEREF_BELOW0" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_BRKH_DSP_L.json b/kintex7/tile_type_BRKH_DSP_L.json new file mode 100644 index 0000000..b6b2351 --- /dev/null +++ b/kintex7/tile_type_BRKH_DSP_L.json @@ -0,0 +1,105 @@ +{ + "tile_type": "BRKH_DSP_L", + "sites": [], + "wires": [ + "BRKH_DSP_PCIN20", + "BRKH_DSP_ACIN7", + "BRKH_DSP_PCIN16", + "BRKH_DSP_PCIN3", + "BRKH_DSP_BCIN5", + "BRKH_DSP_PCIN25", + "BRKH_DSP_PCIN39", + "BRKH_DSP_PCIN30", + "BRKH_DSP_ACIN25", + "BRKH_DSP_PCIN6", + "BRKH_DSP_PCIN35", + "BRKH_DSP_BCIN14", + "BRKH_DSP_BCIN17", + "BRKH_DSP_PCIN14", + "BRKH_DSP_PCIN7", + "BRKH_DSP_BCIN3", + "BRKH_DSP_ACIN28", + "BRKH_DSP_BCIN8", + "BRKH_DSP_ACIN17", + "BRKH_DSP_BCIN15", + "BRKH_DSP_BCIN12", + "BRKH_DSP_ACIN20", + "BRKH_DSP_PCIN28", + "BRKH_DSP_ACIN1", + "BRKH_DSP_ACIN8", + "BRKH_DSP_PCIN40", + "BRKH_DSP_PCIN19", + "BRKH_DSP_BCIN13", + "BRKH_DSP_ACIN13", + "BRKH_DSP_BCIN0", + "BRKH_DSP_ACIN24", + "BRKH_DSP_PCIN46", + "BRKH_DSP_PCIN24", + "BRKH_DSP_PCIN21", + "BRKH_DSP_BCIN1", + "BRKH_DSP_PCIN23", + "BRKH_DSP_PCIN4", + "BRKH_DSP_BCIN16", + "BRKH_DSP_ACIN16", + "BRKH_DSP_BCIN6", + "BRKH_DSP_PCIN11", + "BRKH_DSP_PCIN8", + "BRKH_DSP_ACIN5", + "BRKH_DSP_ACIN11", + "BRKH_DSP_ACIN4", + "BRKH_DSP_ACIN26", + "BRKH_DSP_PCIN10", + "BRKH_DSP_ACIN29", + "BRKH_DSP_MULTSIGNIN", + "BRKH_DSP_PCIN12", + "BRKH_DSP_PCIN18", + "BRKH_DSP_PCIN15", + "BRKH_DSP_BCIN11", + "BRKH_DSP_PCIN17", + "BRKH_DSP_PCIN32", + "BRKH_DSP_PCIN37", + "BRKH_DSP_ACIN23", + "BRKH_DSP_PCIN13", + "BRKH_DSP_PCIN5", + "BRKH_DSP_ACIN10", + "BRKH_DSP_PCIN34", + "BRKH_DSP_ACIN14", + "BRKH_DSP_PCIN26", + "BRKH_DSP_PCIN0", + "BRKH_DSP_PCIN1", + "BRKH_DSP_ACIN2", + "BRKH_DSP_CARRYCASCIN", + "BRKH_DSP_PCIN33", + "BRKH_DSP_ACIN12", + "BRKH_DSP_ACIN3", + "BRKH_DSP_PCIN27", + "BRKH_DSP_BCIN7", + "BRKH_DSP_PCIN42", + "BRKH_DSP_PCIN31", + "BRKH_DSP_ACIN9", + "BRKH_DSP_ACIN27", + "BRKH_DSP_PCIN47", + "BRKH_DSP_PCIN41", + "BRKH_DSP_PCIN38", + "BRKH_DSP_BCIN10", + "BRKH_DSP_ACIN21", + "BRKH_DSP_ACIN15", + "BRKH_DSP_ACIN18", + "BRKH_DSP_ACIN22", + "BRKH_DSP_PCIN29", + "BRKH_DSP_BCIN9", + "BRKH_DSP_PCIN9", + "BRKH_DSP_PCIN43", + "BRKH_DSP_ACIN0", + "BRKH_DSP_PCIN44", + "BRKH_DSP_BCIN2", + "BRKH_DSP_PCIN45", + "BRKH_DSP_BCIN4", + "BRKH_DSP_PCIN22", + "BRKH_DSP_ACIN19", + "BRKH_DSP_ACIN6", + "BRKH_DSP_PCIN2", + "BRKH_DSP_PCIN36" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_BRKH_DSP_R.json b/kintex7/tile_type_BRKH_DSP_R.json new file mode 100644 index 0000000..e5d0b1d --- /dev/null +++ b/kintex7/tile_type_BRKH_DSP_R.json @@ -0,0 +1,105 @@ +{ + "tile_type": "BRKH_DSP_R", + "sites": [], + "wires": [ + "BRKH_DSP_PCIN20", + "BRKH_DSP_ACIN7", + "BRKH_DSP_PCIN16", + "BRKH_DSP_PCIN3", + "BRKH_DSP_BCIN5", + "BRKH_DSP_PCIN25", + "BRKH_DSP_PCIN39", + "BRKH_DSP_PCIN30", + "BRKH_DSP_ACIN25", + "BRKH_DSP_PCIN6", + "BRKH_DSP_PCIN35", + "BRKH_DSP_BCIN14", + "BRKH_DSP_BCIN17", + "BRKH_DSP_PCIN14", + "BRKH_DSP_PCIN7", + "BRKH_DSP_BCIN3", + "BRKH_DSP_ACIN28", + "BRKH_DSP_BCIN8", + "BRKH_DSP_ACIN17", + "BRKH_DSP_BCIN15", + "BRKH_DSP_BCIN12", + "BRKH_DSP_ACIN20", + "BRKH_DSP_PCIN28", + "BRKH_DSP_ACIN1", + "BRKH_DSP_ACIN8", + "BRKH_DSP_PCIN40", + "BRKH_DSP_PCIN19", + "BRKH_DSP_BCIN13", + "BRKH_DSP_ACIN13", + "BRKH_DSP_BCIN0", + "BRKH_DSP_ACIN24", + "BRKH_DSP_PCIN46", + "BRKH_DSP_PCIN24", + "BRKH_DSP_PCIN21", + "BRKH_DSP_BCIN1", + "BRKH_DSP_PCIN23", + "BRKH_DSP_PCIN4", + "BRKH_DSP_BCIN16", + "BRKH_DSP_ACIN16", + "BRKH_DSP_BCIN6", + "BRKH_DSP_PCIN11", + "BRKH_DSP_PCIN8", + "BRKH_DSP_ACIN5", + "BRKH_DSP_ACIN11", + "BRKH_DSP_ACIN4", + "BRKH_DSP_ACIN26", + "BRKH_DSP_PCIN10", + "BRKH_DSP_ACIN29", + "BRKH_DSP_MULTSIGNIN", + "BRKH_DSP_PCIN12", + "BRKH_DSP_PCIN18", + "BRKH_DSP_PCIN15", + "BRKH_DSP_BCIN11", + "BRKH_DSP_PCIN17", + "BRKH_DSP_PCIN32", + "BRKH_DSP_PCIN37", + "BRKH_DSP_ACIN23", + "BRKH_DSP_PCIN13", + "BRKH_DSP_PCIN5", + "BRKH_DSP_ACIN10", + "BRKH_DSP_PCIN34", + "BRKH_DSP_ACIN14", + "BRKH_DSP_PCIN26", + "BRKH_DSP_PCIN0", + "BRKH_DSP_PCIN1", + "BRKH_DSP_ACIN2", + "BRKH_DSP_CARRYCASCIN", + "BRKH_DSP_PCIN33", + "BRKH_DSP_ACIN12", + "BRKH_DSP_ACIN3", + "BRKH_DSP_PCIN27", + "BRKH_DSP_BCIN7", + "BRKH_DSP_PCIN42", + "BRKH_DSP_PCIN31", + "BRKH_DSP_ACIN9", + "BRKH_DSP_ACIN27", + "BRKH_DSP_PCIN47", + "BRKH_DSP_PCIN41", + "BRKH_DSP_PCIN38", + "BRKH_DSP_BCIN10", + "BRKH_DSP_ACIN21", + "BRKH_DSP_ACIN15", + "BRKH_DSP_ACIN18", + "BRKH_DSP_ACIN22", + "BRKH_DSP_PCIN29", + "BRKH_DSP_BCIN9", + "BRKH_DSP_PCIN9", + "BRKH_DSP_PCIN43", + "BRKH_DSP_ACIN0", + "BRKH_DSP_PCIN44", + "BRKH_DSP_BCIN2", + "BRKH_DSP_PCIN45", + "BRKH_DSP_BCIN4", + "BRKH_DSP_PCIN22", + "BRKH_DSP_ACIN19", + "BRKH_DSP_ACIN6", + "BRKH_DSP_PCIN2", + "BRKH_DSP_PCIN36" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_BRKH_GTX.json b/kintex7/tile_type_BRKH_GTX.json new file mode 100644 index 0000000..a8f0c54 --- /dev/null +++ b/kintex7/tile_type_BRKH_GTX.json @@ -0,0 +1,104 @@ +{ + "tile_type": "BRKH_GTX", + "sites": [], + "wires": [ + "BRKH_GTX_NORTHREFCLK0_UPPER", + "BRKH_GTX_REFCLK0_LOWER", + "BRKH_GTX_REFCLK1_LOWER", + "BRKH_GTX_NORTHREFCLK0_LOWER", + "BRKH_GTX_SOUTHREFCLK1_UPPER", + "BRKH_GTX_SOUTHREFCLK0_LOWER", + "BRKH_GTX_NORTHREFCLK1_LOWER", + "BRKH_GTX_REFCLK0_UPPER", + "BRKH_GTX_NORTHREFCLK1_UPPER", + "BRKH_GTX_SOUTHREFCLK1_LOWER", + "BRKH_GTX_REFCLK1_UPPER", + "BRKH_GTX_SOUTHREFCLK0_UPPER" + ], + "pips": { + "BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": { + "src_wire": "BRKH_GTX_REFCLK1_LOWER", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": { + "src_wire": "BRKH_GTX_REFCLK0_UPPER", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": { + "src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": { + "src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": { + "src_wire": "BRKH_GTX_REFCLK1_UPPER", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_GTX.BRKH_GTX_NORTHREFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": { + "src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_GTX.BRKH_GTX_NORTHREFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": { + "src_wire": "BRKH_GTX_NORTHREFCLK1_LOWER", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": { + "src_wire": "BRKH_GTX_REFCLK0_LOWER", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": { + "src_wire": "BRKH_GTX_REFCLK0_LOWER", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": { + "src_wire": "BRKH_GTX_REFCLK1_LOWER", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": { + "src_wire": "BRKH_GTX_REFCLK1_UPPER", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": { + "src_wire": "BRKH_GTX_REFCLK0_UPPER", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_BRKH_INT.json b/kintex7/tile_type_BRKH_INT.json new file mode 100644 index 0000000..f8cb6ba --- /dev/null +++ b/kintex7/tile_type_BRKH_INT.json @@ -0,0 +1,367 @@ +{ + "tile_type": "BRKH_INT", + "sites": [], + "wires": [ + "BRKH_INT_LV14", + "BRKH_INT_NR1BEG1", + "BRKH_INT_SE2A3", + "BRKH_INT_NE6B0", + "BRKH_INT_L_LV0", + "BRKH_INT_NE6C0", + "BRKH_INT_SS6E2", + "BRKH_INT_NE6A3", + "BRKH_INT_SS6END3", + "BRKH_INT_LVB11", + "BRKH_INT_NE2BEG0", + "BRKH_INT_NE2END_S3_0", + "BRKH_INT_SW6E0", + "BRKH_INT_SW6E3", + "BRKH_INT_SW6C1", + "BRKH_INT_L_LV2", + "BRKH_INT_SS6D3", + "BRKH_INT_SE6E0", + "BRKH_INT_LVB5", + "BRKH_INT_LV15", + "BRKH_INT_NL1BEG0", + "BRKH_INT_NN6BEG2", + "BRKH_INT_SS2END_N0_3", + "BRKH_INT_SW6E1", + "BRKH_INT_FAN_BOUNCE_S3_0", + "BRKH_INT_NL1BEG1", + "BRKH_INT_LVB2", + "BRKH_INT_L_LV7", + "BRKH_INT_SW2A2", + "BRKH_INT_WL1BEG3", + "BRKH_INT_NW2BEG2", + "BRKH_INT_SE6B2", + "BRKH_INT_NW6END_S0_0", + "BRKH_INT_SE6B3", + "BRKH_INT_SS6D1", + "BRKH_INT_NE6A0", + "BRKH_INT_ER1BEG_S0", + "BRKH_INT_NW6A1", + "BRKH_INT_NN6E3", + "BRKH_INT_NR1BEG1_SLOW", + "BRKH_INT_LV3", + "BRKH_INT_WW4END_S0_0", + "BRKH_INT_WL1END3", + "BRKH_INT_NN6B0", + "BRKH_INT_WW2END3", + "BRKH_INT_NN6C3", + "BRKH_INT_SR1END3", + "BRKH_INT_LVB4", + "BRKH_INT_LV9", + "BRKH_INT_SS6E3", + "BRKH_INT_NN6BEG0", + "BRKH_INT_SW6D0", + "BRKH_INT_NW6B0", + "BRKH_INT_SS6C0", + "BRKH_INT_LV12", + "BRKH_INT_LVB_L7", + "BRKH_INT_L_LV10", + "BRKH_INT_NN6D0", + "BRKH_INT_SS6B3", + "BRKH_INT_NN2BEG2", + "BRKH_INT_L_LV13", + "BRKH_INT_NW6B1", + "BRKH_INT_SS6C1", + "BRKH_INT_NE2BEG1", + "BRKH_INT_NE2BEG2", + "BRKH_INT_SS2A0", + "BRKH_INT_NR1BEG0_SLOW", + "BRKH_INT_SW6D3", + "BRKH_INT_NW6C1", + "BRKH_INT_LVB_L3", + "BRKH_INT_NN6D1", + "BRKH_INT_NL1BEG2", + "BRKH_INT_LVB9", + "BRKH_INT_NW6A0", + "BRKH_INT_EL1BEG3", + "BRKH_INT_SS2END0", + "BRKH_INT_NN2A0", + "BRKH_INT_NW6D0", + "BRKH_INT_SS2END1", + "BRKH_INT_NW6A2", + "BRKH_INT_SS6A2", + "BRKH_INT_SS2A3", + "BRKH_INT_L_LV3", + "BRKH_INT_SE2A0", + "BRKH_INT_SS2END2", + "BRKH_INT_SE6C3", + "BRKH_INT_LVB_L11", + "BRKH_INT_NN6BEG1", + "BRKH_INT_LVB_L2", + "BRKH_INT_L_LV5", + "BRKH_INT_SE6B1", + "BRKH_INT_SW2A1", + "BRKH_INT_SE6C2", + "BRKH_INT_BYP_BOUNCE6", + "BRKH_INT_L_LV14", + "BRKH_INT_SE6D2", + "BRKH_INT_NR1BEG0", + "BRKH_INT_NN6D2", + "BRKH_INT_NW6A3", + "BRKH_INT_L_LV15", + "BRKH_INT_NE6C3", + "BRKH_INT_SE6C1", + "BRKH_INT_LV10", + "BRKH_INT_LV11", + "BRKH_INT_SR1END1", + "BRKH_INT_NN6E1", + "BRKH_INT_SS6C3", + "BRKH_INT_SS6END0", + "BRKH_INT_LVB7", + "BRKH_INT_LVB8", + "BRKH_INT_LVB_L9", + "BRKH_INT_SE6C0", + "BRKH_INT_NN2BEG0", + "BRKH_INT_NR1BEG2_SLOW", + "BRKH_INT_SW2END3", + "BRKH_INT_SS6B1", + "BRKH_INT_NL1BEG2_SLOW", + "BRKH_INT_EL1END_S3_0", + "BRKH_INT_NE2BEG3", + "BRKH_INT_NE6A2", + "BRKH_INT_LVB_L6", + "BRKH_INT_L_LV16", + "BRKH_INT_NN2BEG3", + "BRKH_INT_L_LV9", + "BRKH_INT_LVB3", + "BRKH_INT_NN6A3", + "BRKH_INT_L_LV8", + "BRKH_INT_NL1BEG1_SLOW", + "BRKH_INT_SR1END2_SLOW", + "BRKH_INT_SS6C2", + "BRKH_INT_LVB_L4", + "BRKH_INT_LV13", + "BRKH_INT_SR1END3_SLOW", + "BRKH_INT_SW2A3", + "BRKH_INT_NN6B1", + "BRKH_INT_SE6E3", + "BRKH_INT_LV5", + "BRKH_INT_SE2A1", + "BRKH_INT_L_LV17", + "BRKH_INT_LV16", + "BRKH_INT_NE6B2", + "BRKH_INT_FAN_BOUNCE_S3_4", + "BRKH_INT_SW2A0", + "BRKH_INT_SS6A1", + "BRKH_INT_SW6C2", + "BRKH_INT_LV0", + "BRKH_INT_LV7", + "BRKH_INT_LVB_L12", + "BRKH_INT_SR1END1_SLOW", + "BRKH_INT_SR1END_N3_3", + "BRKH_INT_NL1BEG0_SLOW", + "BRKH_INT_L_LV4", + "BRKH_INT_SE6D3", + "BRKH_INT_SW6B0", + "BRKH_INT_BYP_BOUNCE2", + "BRKH_INT_NN2BEG1", + "BRKH_INT_SS6B0", + "BRKH_INT_SS6D2", + "BRKH_INT_ER1END3", + "BRKH_INT_SL1END3", + "BRKH_INT_NW6D3", + "BRKH_INT_SL1END3_SLOW", + "BRKH_INT_SW6C0", + "BRKH_INT_NW6D2", + "BRKH_INT_SL1END1_SLOW", + "BRKH_INT_NN6A1", + "BRKH_INT_NE6D3", + "BRKH_INT_LVB10", + "BRKH_INT_FAN_BOUNCE_S3_2", + "BRKH_INT_SR1END2", + "BRKH_INT_SS6D0", + "BRKH_INT_LVB1", + "BRKH_INT_NE6A1", + "BRKH_INT_SS6A0", + "BRKH_INT_NN6C1", + "BRKH_INT_NN6E2", + "BRKH_INT_SL1END2_SLOW", + "BRKH_INT_SE6D0", + "BRKH_INT_SE6B0", + "BRKH_INT_LVB_L5", + "BRKH_INT_SS2END3", + "BRKH_INT_NW6B2", + "BRKH_INT_NR1BEG3_SLOW", + "BRKH_INT_SW6B2", + "BRKH_INT_LVB6", + "BRKH_INT_SS2A1", + "BRKH_INT_LV17", + "BRKH_INT_BYP_BOUNCE7", + "BRKH_INT_NN2END_S2_0", + "BRKH_INT_LV6", + "BRKH_INT_NN6B2", + "BRKH_INT_LVB_L8", + "BRKH_INT_SW6B3", + "BRKH_INT_NN6E0", + "BRKH_INT_NE6D1", + "BRKH_INT_FAN_BOUNCE_S3_6", + "BRKH_INT_NW6D1", + "BRKH_INT_LV4", + "BRKH_INT_NW6C0", + "BRKH_INT_SW6B1", + "BRKH_INT_NE6D2", + "BRKH_INT_LVB12", + "BRKH_INT_SW6E2", + "BRKH_INT_NN6A2", + "BRKH_INT_NN6BEG3", + "BRKH_INT_SE6E2", + "BRKH_INT_NN6END_S1_0", + "BRKH_INT_NW6C3", + "BRKH_INT_WR1END_S1_0", + "BRKH_INT_SW6C3", + "BRKH_INT_NL1END_S3_0", + "BRKH_INT_NN2A1", + "BRKH_INT_NN6A0", + "BRKH_INT_LVB_L10", + "BRKH_INT_NE6C2", + "BRKH_INT_SS2A2", + "BRKH_INT_NN6C0", + "BRKH_INT_NW2BEG1", + "BRKH_INT_NW2BEG0", + "BRKH_INT_SS6B2", + "BRKH_INT_SW6END3", + "BRKH_INT_SS6END1", + "BRKH_INT_NE6D0", + "BRKH_INT_NW2END_S0_0", + "BRKH_INT_SS6END_N0_3", + "BRKH_INT_NW2BEG3", + "BRKH_INT_SS6E1", + "BRKH_INT_LV8", + "BRKH_INT_SL1END2", + "BRKH_INT_SS6END2", + "BRKH_INT_SL1END0", + "BRKH_INT_NE6B3", + "BRKH_INT_NE6B1", + "BRKH_INT_WR1BEG_S0", + "BRKH_INT_NN6B3", + "BRKH_INT_NW6C2", + "BRKH_INT_SE6D1", + "BRKH_INT_NW6B3", + "BRKH_INT_LVB_L1", + "BRKH_INT_NN2A3", + "BRKH_INT_NN2A2", + "BRKH_INT_L_LV1", + "BRKH_INT_SL1END1", + "BRKH_INT_L_LV12", + "BRKH_INT_NE6C1", + "BRKH_INT_NR1BEG2", + "BRKH_INT_SE6E1", + "BRKH_INT_SE2A2", + "BRKH_INT_SS6A3", + "BRKH_INT_LV2", + "BRKH_INT_NR1BEG3", + "BRKH_INT_SS6E0", + "BRKH_INT_SW6D1", + "BRKH_INT_LV1", + "BRKH_INT_SL1END0_SLOW", + "BRKH_INT_NN6D3", + "BRKH_INT_SW6D2", + "BRKH_INT_NN6C2", + "BRKH_INT_L_LV6", + "BRKH_INT_BYP_BOUNCE3", + "BRKH_INT_L_LV11" + ], + "pips": { + "BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": { + "src_wire": "BRKH_INT_SR1END1_SLOW", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SR1END1", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": { + "src_wire": "BRKH_INT_SR1END3_SLOW", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SR1END3", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": { + "src_wire": "BRKH_INT_NL1BEG1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NL1BEG1_SLOW", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_INT.BRKH_INT_SL1END1_SLOW->>BRKH_INT_SL1END1": { + "src_wire": "BRKH_INT_SL1END1_SLOW", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SL1END1", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": { + "src_wire": "BRKH_INT_NR1BEG3", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NR1BEG3_SLOW", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_INT.BRKH_INT_SL1END3_SLOW->>BRKH_INT_SL1END3": { + "src_wire": "BRKH_INT_SL1END3_SLOW", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SL1END3", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": { + "src_wire": "BRKH_INT_NR1BEG2", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NR1BEG2_SLOW", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": { + "src_wire": "BRKH_INT_SL1END0_SLOW", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SL1END0", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": { + "src_wire": "BRKH_INT_SL1END2_SLOW", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SL1END2", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": { + "src_wire": "BRKH_INT_NR1BEG0", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NR1BEG0_SLOW", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": { + "src_wire": "BRKH_INT_NL1BEG2", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NL1BEG2_SLOW", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": { + "src_wire": "BRKH_INT_NL1BEG0", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NL1BEG0_SLOW", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": { + "src_wire": "BRKH_INT_SR1END2_SLOW", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SR1END2", + "is_directional": "1", + "can_invert": "0" + }, + "BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": { + "src_wire": "BRKH_INT_NR1BEG1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NR1BEG1_SLOW", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_BRKH_TERM_INT.json b/kintex7/tile_type_BRKH_TERM_INT.json new file mode 100644 index 0000000..2b81606 --- /dev/null +++ b/kintex7/tile_type_BRKH_TERM_INT.json @@ -0,0 +1,124 @@ +{ + "tile_type": "BRKH_TERM_INT", + "sites": [], + "wires": [ + "T_TERM_UTURN_INT_SE6D1", + "T_TERM_UTURN_INT_SW6E2", + "T_TERM_INT_UTURN_LV_R7", + "T_TERM_UTURN_INT_SW6C0", + "T_TERM_UTURN_INT_SW6D1", + "T_TERM_UTURN_INT_LV_L3", + "T_TERM_UTURN_INT_SW6E3", + "T_TERM_INT_UTURN_LV_R17", + "T_TERM_UTURN_INT_SS6A3", + "T_TERM_UTURN_INT_SE6E2", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", + "T_TERM_UTURN_INT_SS2END3", + "T_TERM_UTURN_INT_SS6A0", + "T_TERM_UTURN_INT_LVB2", + "T_TERM_UTURN_INT_SE6B3", + "T_TERM_UTURN_INT_SS6E2", + "T_TERM_UTURN_INT_SW2A1", + "T_TERM_UTURN_INT_LVB1", + "T_TERM_UTURN_INT_SS2A1", + "T_TERM_UTURN_INT_SS6E3", + "T_TERM_UTURN_INT_SS6END3", + "T_TERM_UTURN_INT_SW6C3", + "T_TERM_UTURN_INT_SE6E0", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", + "T_TERM_UTURN_INT_SS6D3", + "T_TERM_UTURN_INT_SW2A0", + "T_TERM_UTURN_INT_SE6B1", + "T_TERM_UTURN_INT_SS6END0", + "T_TERM_UTURN_INT_SL1END0_SLOW", + "T_TERM_UTURN_INT_SE6B0", + "T_TERM_UTURN_INT_LV_L5", + "T_TERM_UTURN_INT_LV_L17", + "T_TERM_UTURN_INT_SS6D1", + "T_TERM_UTURN_INT_SE2A2", + "T_TERM_UTURN_INT_SE6C1", + "T_TERM_UTURN_INT_LV_L6", + "T_TERM_UTURN_INT_SS6C3", + "T_TERM_UTURN_INT_SW6C2", + "T_TERM_UTURN_INT_SR1END1_SLOW", + "T_TERM_UTURN_INT_SE2A3", + "T_TERM_UTURN_INT_SS2END0", + "T_TERM_UTURN_INT_SL1END1_SLOW", + "T_TERM_UTURN_INT_SW6D0", + "T_TERM_UTURN_INT_LVB_L4", + "T_TERM_UTURN_INT_SW6E0", + "T_TERM_UTURN_INT_SW2A3", + "T_TERM_UTURN_INT_LV_L16", + "T_TERM_UTURN_INT_LV_L9", + "T_TERM_UTURN_INT_SE6D2", + "T_TERM_UTURN_INT_SS2A0", + "T_TERM_UTURN_INT_SE6C0", + "T_TERM_UTURN_INT_SS2END2", + "T_TERM_UTURN_INT_LVB3", + "T_TERM_UTURN_INT_SL1END2_SLOW", + "T_TERM_UTURN_INT_SS6D0", + "T_TERM_UTURN_INT_SE2A0", + "T_TERM_UTURN_INT_SS6E1", + "T_TERM_UTURN_INT_SR1END2_SLOW", + "T_TERM_UTURN_INT_SE6E3", + "T_TERM_UTURN_INT_ER1BEG_S0", + "T_TERM_UTURN_INT_LVB4", + "T_TERM_UTURN_INT_SE6D3", + "T_TERM_UTURN_INT_SS6END2", + "T_TERM_UTURN_INT_LV_L7", + "T_TERM_UTURN_INT_SS6B2", + "T_TERM_UTURN_INT_LVB_L5", + "T_TERM_UTURN_INT_SS6B3", + "T_TERM_UTURN_INT_LVB5", + "T_TERM_UTURN_INT_SW6D3", + "T_TERM_INT_UTURN_LV_R5", + "T_TERM_UTURN_INT_SS6C0", + "T_TERM_UTURN_INT_SS2END1", + "T_TERM_UTURN_INT_SS6B0", + "T_TERM_INT_UTURN_LV_R16", + "T_TERM_UTURN_INT_SS2A3", + "T_TERM_UTURN_INT_SW6B1", + "T_TERM_UTURN_INT_SW6B2", + "T_TERM_INT_UTURN_LV_R3", + "T_TERM_UTURN_INT_SW6E1", + "T_TERM_INT_UTURN_LV_R6", + "T_TERM_UTURN_INT_SE6C2", + "T_TERM_UTURN_INT_SL1END3_SLOW", + "T_TERM_UTURN_INT_LVB_L0", + "T_TERM_INT_UTURN_LV_R4", + "T_TERM_UTURN_INT_SS6E0", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", + "T_TERM_UTURN_INT_WR1END_S1_0", + "T_TERM_UTURN_INT_ER1END3", + "T_TERM_UTURN_INT_SS6A1", + "T_TERM_UTURN_INT_SS6B1", + "T_TERM_UTURN_INT_SS6A2", + "T_TERM_UTURN_INT_SS6D2", + "T_TERM_UTURN_INT_SW2A2", + "T_TERM_UTURN_INT_LVB_L2", + "T_TERM_UTURN_INT_SE6D0", + "T_TERM_UTURN_INT_SW6B3", + "T_TERM_INT_UTURN_LV_R9", + "T_TERM_INT_UTURN_LV_R2", + "T_TERM_UTURN_INT_SE6E1", + "T_TERM_UTURN_INT_SW6D2", + "T_TERM_UTURN_INT_SS2A2", + "T_TERM_UTURN_INT_LV_L2", + "T_TERM_UTURN_INT_SE2A1", + "T_TERM_UTURN_INT_SS6C1", + "T_TERM_UTURN_INT_SS6END1", + "T_TERM_UTURN_INT_LV_L4", + "T_TERM_UTURN_INT_WR1BEG_S0", + "T_TERM_UTURN_INT_SE6B2", + "T_TERM_UTURN_INT_SE6C3", + "T_TERM_UTURN_INT_SS6C2", + "T_TERM_UTURN_INT_LVB0", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", + "T_TERM_UTURN_INT_SR1END3_SLOW", + "T_TERM_UTURN_INT_LVB_L3", + "T_TERM_UTURN_INT_SW6B0", + "T_TERM_UTURN_INT_LVB_L1", + "T_TERM_UTURN_INT_SW6C1" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_B_TERM_INT.json b/kintex7/tile_type_B_TERM_INT.json new file mode 100644 index 0000000..0b511c5 --- /dev/null +++ b/kintex7/tile_type_B_TERM_INT.json @@ -0,0 +1,125 @@ +{ + "tile_type": "B_TERM_INT", + "sites": [], + "wires": [ + "B_TERM_UTURN_INT_SW6D0", + "B_TERM_UTURN_INT_SS6A1", + "B_TERM_UTURN_INT_LVB5", + "B_TERM_UTURN_INT_SS2BEG2", + "B_TERM_UTURN_INT_LV8", + "B_TERM_UTURN_INT_SW2BEG2", + "B_TERM_UTURN_INT_SS6E0", + "B_TERM_UTURN_INT_SE6A0", + "B_TERM_UTURN_INT_SS6B3", + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "B_TERM_UTURN_INT_SS6A2", + "B_TERM_UTURN_INT_LV9", + "B_TERM_UTURN_INT_SR1BEG3", + "B_TERM_UTURN_INT_LV_L2", + "B_TERM_UTURN_INT_SS6BEG3", + "B_TERM_UTURN_INT_LVB_L4", + "B_TERM_UTURN_INT_SW6A2", + "B_TERM_UTURN_INT_SE6C0", + "B_TERM_UTURN_INT_LVB_L5", + "B_TERM_UTURN_INT_ER1BEG0", + "B_TERM_UTURN_INT_LVB1", + "B_TERM_UTURN_INT_LVB_L3", + "B_TERM_UTURN_INT_SE6C3", + "B_TERM_UTURN_INT_SS6C3", + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "B_TERM_UTURN_INT_LV_L9", + "B_TERM_UTURN_INT_SS6D0", + "B_TERM_UTURN_INT_LV2", + "B_TERM_UTURN_INT_LVB_L1", + "B_TERM_UTURN_INT_SS6E2", + "B_TERM_UTURN_INT_SE6D3", + "B_TERM_UTURN_INT_SW6D3", + "B_TERM_UTURN_INT_LVB0", + "B_TERM_UTURN_INT_SS2BEG0", + "B_TERM_UTURN_INT_SS6D2", + "B_TERM_UTURN_INT_SR1BEG1", + "B_TERM_UTURN_INT_SS6E3", + "B_TERM_UTURN_INT_SW2BEG0", + "B_TERM_UTURN_INT_SS6D1", + "B_TERM_UTURN_INT_LVB2", + "B_TERM_UTURN_INT_SS6BEG1", + "B_TERM_UTURN_INT_SE6D2", + "B_TERM_UTURN_INT_SR1BEG2", + "B_TERM_UTURN_INT_SL1BEG1", + "B_TERM_UTURN_INT_SE6B1", + "B_TERM_UTURN_INT_LV_L7", + "B_TERM_UTURN_INT_LVB_L2", + "B_TERM_UTURN_INT_SW6A0", + "B_TERM_UTURN_INT_SW6A1", + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "B_TERM_UTURN_INT_LV_L8", + "B_TERM_UTURN_INT_SW6C3", + "B_TERM_UTURN_INT_SW6B2", + "B_TERM_UTURN_INT_SS6B2", + "B_TERM_UTURN_INT_SS6BEG2", + "B_TERM_UTURN_INT_SS6BEG0", + "B_TERM_UTURN_INT_LVB3", + "B_TERM_UTURN_INT_SE6B3", + "B_TERM_UTURN_INT_SS2BEG3", + "B_TERM_UTURN_INT_SS2A0", + "B_TERM_UTURN_INT_LV3", + "B_TERM_UTURN_INT_SW6C1", + "B_TERM_UTURN_INT_LV7", + "B_TERM_UTURN_INT_SS6C0", + "B_TERM_UTURN_INT_LV_L5", + "B_TERM_UTURN_INT_SE6B0", + "B_TERM_UTURN_INT_SE2BEG1", + "B_TERM_UTURN_INT_SE6A3", + "B_TERM_UTURN_INT_SW6B1", + "B_TERM_UTURN_INT_SW6A3", + "B_TERM_UTURN_INT_SE2BEG0", + "B_TERM_UTURN_INT_SS6B1", + "B_TERM_UTURN_INT_SE6C2", + "B_TERM_UTURN_INT_SW6D2", + "B_TERM_UTURN_INT_SW2BEG1", + "B_TERM_UTURN_INT_SE6B2", + "B_TERM_UTURN_INT_SW6D1", + "B_TERM_UTURN_INT_SW6C0", + "B_TERM_UTURN_INT_ER1END_N3_3", + "B_TERM_UTURN_INT_SE6A2", + "B_TERM_UTURN_INT_LV_L4", + "B_TERM_UTURN_INT_SW2BEG3", + "B_TERM_UTURN_INT_SW6C2", + "B_TERM_UTURN_INT_SS6A3", + "B_TERM_UTURN_INT_SL1BEG0", + "B_TERM_UTURN_INT_SE6A1", + "B_TERM_UTURN_INT_LV4", + "B_TERM_UTURN_INT_SS2A2", + "B_TERM_UTURN_INT_SE6C1", + "B_TERM_UTURN_INT_SS2BEG1", + "B_TERM_UTURN_INT_LVB_L0", + "B_TERM_UTURN_INT_SS6A0", + "B_TERM_UTURN_INT_SE6D1", + "B_TERM_UTURN_INT_SE2BEG3", + "B_TERM_UTURN_INT_SL1BEG3", + "B_TERM_UTURN_INT_LV_L3", + "B_TERM_UTURN_INT_SW6B0", + "B_TERM_UTURN_INT_LV5", + "B_TERM_UTURN_INT_LVB4", + "B_TERM_UTURN_INT_WR1END0", + "B_TERM_UTURN_INT_LV_L6", + "B_TERM_UTURN_INT_LV_L18", + "B_TERM_UTURN_INT_SE2BEG2", + "B_TERM_UTURN_INT_SS2A3", + "B_TERM_UTURN_INT_SW6B3", + "B_TERM_UTURN_INT_SS6C1", + "B_TERM_UTURN_INT_WR1BEG0", + "B_TERM_UTURN_INT_SE6D0", + "B_TERM_UTURN_INT_SL1BEG2", + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "B_TERM_UTURN_INT_SW6END_N0_3", + "B_TERM_UTURN_INT_SS6E1", + "B_TERM_UTURN_INT_SS6C2", + "B_TERM_UTURN_INT_SS6D3", + "B_TERM_UTURN_INT_LV6", + "B_TERM_UTURN_INT_SS2A1", + "B_TERM_UTURN_INT_SS6B0", + "B_TERM_UTURN_INT_LV18" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_CFG_CENTER_BOT.json b/kintex7/tile_type_CFG_CENTER_BOT.json new file mode 100644 index 0000000..a35b0ad --- /dev/null +++ b/kintex7/tile_type_CFG_CENTER_BOT.json @@ -0,0 +1,4513 @@ +{ + "tile_type": "CFG_CENTER_BOT", + "sites": [], + "wires": [ + "CFG_CENTER_EL1BEG2_0", + "CFG_CENTER_IMUX45_18", + "CFG_CENTER_NW4END3_8", + "CFG_CENTER_SW2A0_16", + "CFG_CENTER_WL1END2_17", + "CFG_CENTER_LOGIC_OUTS_B4_13", + "CFG_CENTER_LOGIC_OUTS_B22_10", + "CFG_CENTER_IMUX16_4", + "CFG_CENTER_EE4C2_4", + "CFG_CENTER_WW4END1_5", + "CFG_CENTER_IMUX2_14", + "CFG_CENTER_FAN5_19", + "CFG_CENTER_IMUX20_15", + "CFG_CENTER_ER1BEG1_19", + "CFG_CENTER_LOGIC_OUTS_B5_14", + "CFG_CENTER_SE2A3_11", + "CFG_CENTER_LOGIC_OUTS_B23_16", + "CFG_CENTER_SE4C0_16", + "CFG_CENTER_EL1BEG1_0", + "CFG_CENTER_EE4B0_12", + "CFG_CENTER_IMUX37_9", + "CFG_CENTER_WW4A0_10", + "CFG_CENTER_BYP4_2", + "CFG_CENTER_EE4A0_9", + "CFG_CENTER_BYP0_14", + "CFG_CENTER_IMUX11_8", + "CFG_CENTER_IMUX14_4", + "CFG_CENTER_SE2A0_12", + "CFG_CENTER_NE2A3_14", + "CFG_CENTER_BLOCK_OUTS_B1_3", + "CFG_CENTER_SW2A2_12", + "CFG_CENTER_WW2END3_13", + "CFG_CENTER_IMUX9_14", + "CFG_CENTER_NW4END1_11", + "CFG_CENTER_SE4C0_4", + "CFG_CENTER_IMUX42_18", + "CFG_CENTER_CTRL1_1", + "CFG_CENTER_IMUX18_1", + "CFG_CENTER_EE4BEG0_17", + "CFG_CENTER_LOGIC_OUTS_B11_9", + "CFG_CENTER_IMUX38_6", + "CFG_CENTER_SW2A2_9", + "CFG_CENTER_NE4BEG2_17", + "CFG_CENTER_WW4A1_14", + "CFG_CENTER_LOGIC_OUTS_B18_5", + "CFG_CENTER_IMUX9_5", + "CFG_CENTER_SW2A3_17", + "CFG_CENTER_WW4A1_9", + "CFG_CENTER_LOGIC_OUTS_B13_16", + "CFG_CENTER_FAN1_15", + "CFG_CENTER_NE2A0_19", + "CFG_CENTER_NW4END0_15", + "CFG_CENTER_LOGIC_OUTS_B10_16", + "CFG_CENTER_LH1_17", + "CFG_CENTER_BYP3_3", + "CFG_CENTER_IMUX38_1", + "CFG_CENTER_EE2A1_14", + "CFG_CENTER_IMUX5_13", + "CFG_CENTER_FAN6_17", + "CFG_CENTER_IMUX6_2", + "CFG_CENTER_IMUX25_7", + "CFG_CENTER_WW2A0_7", + "CFG_CENTER_SE2A2_7", + "CFG_CENTER_FAN2_9", + "CFG_CENTER_SE4C2_19", + "CFG_CENTER_EE4BEG0_19", + "CFG_CENTER_NE4C3_14", + "CFG_CENTER_WL1END0_5", + "CFG_CENTER_WW4B2_4", + "CFG_CENTER_IMUX32_5", + "CFG_CENTER_NE4BEG1_13", + "CFG_CENTER_LOGIC_OUTS_B5_5", + "CFG_CENTER_LOGIC_OUTS_B4_8", + "CFG_CENTER_LH1_7", + "CFG_CENTER_NE4C0_8", + "CFG_CENTER_IMUX24_3", + "CFG_CENTER_LOGIC_OUTS_B1_5", + "CFG_CENTER_NE2A1_8", + "CFG_CENTER_WW4C3_3", + "CFG_CENTER_LOGIC_OUTS_B14_4", + "CFG_CENTER_LOGIC_OUTS_B14_2", + "CFG_CENTER_IMUX36_13", + "CFG_CENTER_EE4C2_8", + "CFG_CENTER_WW4B1_12", + "CFG_CENTER_WW2A2_1", + "CFG_CENTER_EE2BEG0_6", + "CFG_CENTER_WW4B1_18", + "CFG_CENTER_IMUX9_9", + "CFG_CENTER_WW4B3_1", + "CFG_CENTER_ER1BEG2_8", + "CFG_CENTER_LOGIC_OUTS_B1_7", + "CFG_CENTER_WW4A0_18", + "CFG_CENTER_WW2END1_15", + "CFG_CENTER_SE4BEG0_10", + "CFG_CENTER_LOGIC_OUTS_B18_14", + "CFG_CENTER_FAN6_19", + "CFG_CENTER_NE2A0_9", + "CFG_CENTER_LOGIC_OUTS_B7_1", + "CFG_CENTER_IMUX31_5", + "CFG_CENTER_BYP7_3", + "CFG_CENTER_IMUX30_17", + "CFG_CENTER_SE4BEG2_11", + "CFG_CENTER_WL1END3_16", + "CFG_CENTER_LOGIC_OUTS_B8_2", + "CFG_CENTER_WR1END1_9", + "CFG_CENTER_IMUX15_10", + "CFG_CENTER_LOGIC_OUTS_B11_0", + "CFG_CENTER_IMUX14_18", + "CFG_CENTER_WW4B1_5", + "CFG_CENTER_BLOCK_OUTS_B2_16", + "CFG_CENTER_IMUX11_0", + "CFG_CENTER_SE2A1_17", + "CFG_CENTER_WW4B2_19", + "CFG_CENTER_EE4BEG2_8", + "CFG_CENTER_EL1BEG0_19", + "CFG_CENTER_IMUX3_17", + "CFG_CENTER_EE4C3_19", + "CFG_CENTER_ER1BEG3_15", + "CFG_CENTER_CLK0_15", + "CFG_CENTER_NW4A0_2", + "CFG_CENTER_LOGIC_OUTS_B4_4", + "CFG_CENTER_SE4BEG2_0", + "CFG_CENTER_LOGIC_OUTS_B16_13", + "CFG_CENTER_SW4END2_3", + "CFG_CENTER_WW2A0_6", + "CFG_CENTER_LOGIC_OUTS_B14_1", + "CFG_CENTER_NW2A0_5", + "CFG_CENTER_BLOCK_OUTS_B2_0", + "CFG_CENTER_LOGIC_OUTS_B4_3", + "CFG_CENTER_IMUX15_17", + "CFG_CENTER_IMUX2_2", + "CFG_CENTER_SE4BEG1_19", + "CFG_CENTER_IMUX8_3", + "CFG_CENTER_LOGIC_OUTS_B5_19", + "CFG_CENTER_IMUX35_17", + "CFG_CENTER_SW4END0_8", + "CFG_CENTER_LOGIC_OUTS_B23_14", + "CFG_CENTER_IMUX5_9", + "CFG_CENTER_IMUX27_10", + "CFG_CENTER_IMUX26_3", + "CFG_CENTER_NE4C3_6", + "CFG_CENTER_EE2A2_7", + "CFG_CENTER_EE2BEG2_17", + "CFG_CENTER_IMUX5_10", + "CFG_CENTER_LH4_8", + "CFG_CENTER_FAN2_14", + "CFG_CENTER_IMUX3_11", + "CFG_CENTER_EE2BEG0_17", + "CFG_CENTER_LH1_2", + "CFG_CENTER_SE2A0_11", + "CFG_CENTER_IMUX18_6", + "CFG_CENTER_IMUX30_9", + "CFG_CENTER_EL1BEG3_18", + "CFG_CENTER_EE2BEG1_14", + "CFG_CENTER_IMUX27_1", + "CFG_CENTER_SE4C3_16", + "CFG_CENTER_WR1END2_4", + "CFG_CENTER_IMUX47_4", + "CFG_CENTER_NE2A3_8", + "CFG_CENTER_FAN2_7", + "CFG_CENTER_IMUX32_3", + "CFG_CENTER_NE2A2_0", + "CFG_CENTER_IMUX24_19", + "CFG_CENTER_BLOCK_OUTS_B1_11", + "CFG_CENTER_LOGIC_OUTS_B13_0", + "CFG_CENTER_IMUX23_14", + "CFG_CENTER_SW4A2_6", + "CFG_CENTER_LH7_7", + "CFG_CENTER_NW4A3_15", + "CFG_CENTER_LOGIC_OUTS_B17_16", + "CFG_CENTER_IMUX15_12", + "CFG_CENTER_EE2A1_0", + "CFG_CENTER_LOGIC_OUTS_B10_1", + "CFG_CENTER_IMUX36_11", + "CFG_CENTER_IMUX25_3", + "CFG_CENTER_IMUX17_11", + "CFG_CENTER_ER1BEG1_6", + "CFG_CENTER_FAN4_1", + "CFG_CENTER_NE4BEG3_13", + "CFG_CENTER_IMUX43_10", + "CFG_CENTER_IMUX47_7", + "CFG_CENTER_EE4BEG2_0", + "CFG_CENTER_FAN5_14", + "CFG_CENTER_BYP5_5", + "CFG_CENTER_SW4A1_2", + "CFG_CENTER_ER1BEG3_14", + "CFG_CENTER_FAN7_16", + "CFG_CENTER_EE2BEG1_7", + "CFG_CENTER_NW2A1_8", + "CFG_CENTER_SE4BEG2_3", + "CFG_CENTER_CLK1_18", + "CFG_CENTER_WL1END0_6", + "CFG_CENTER_BLOCK_OUTS_B3_12", + "CFG_CENTER_WL1END1_3", + "CFG_CENTER_EL1BEG3_0", + "CFG_CENTER_SE4BEG1_4", + "CFG_CENTER_FAN4_11", + "CFG_CENTER_IMUX39_0", + "CFG_CENTER_IMUX18_9", + "CFG_CENTER_NW4A1_9", + "CFG_CENTER_LOGIC_OUTS_B6_5", + "CFG_CENTER_NW4END1_12", + "CFG_CENTER_NE4BEG2_14", + "CFG_CENTER_WW4END2_7", + "CFG_CENTER_IMUX10_6", + "CFG_CENTER_NE4C1_19", + "CFG_CENTER_IMUX13_12", + "CFG_CENTER_IMUX19_5", + "CFG_CENTER_LOGIC_OUTS_B15_0", + "CFG_CENTER_IMUX24_16", + "CFG_CENTER_NE4C0_11", + "CFG_CENTER_SE2A0_13", + "CFG_CENTER_LH6_16", + "CFG_CENTER_EE2A0_13", + "CFG_CENTER_LOGIC_OUTS_B7_7", + "CFG_CENTER_WW4C3_0", + "CFG_CENTER_SE4BEG3_9", + "CFG_CENTER_IMUX35_4", + "CFG_CENTER_IMUX11_10", + "CFG_CENTER_IMUX12_4", + "CFG_CENTER_LOGIC_OUTS_B7_11", + "CFG_CENTER_SW4END2_15", + "CFG_CENTER_IMUX21_10", + "CFG_CENTER_IMUX16_1", + "CFG_CENTER_WW4B0_19", + "CFG_CENTER_IMUX11_15", + "CFG_CENTER_WL1END2_5", + "CFG_CENTER_BLOCK_OUTS_B1_5", + "CFG_CENTER_EE4A0_12", + "CFG_CENTER_LH2_15", + "CFG_CENTER_LOGIC_OUTS_B7_6", + "CFG_CENTER_SW4A1_14", + "CFG_CENTER_SE4BEG3_1", + "CFG_CENTER_WW2END3_3", + "CFG_CENTER_NW4A1_7", + "CFG_CENTER_CLK0_10", + "CFG_CENTER_EE4A3_16", + "CFG_CENTER_IMUX22_1", + "CFG_CENTER_IMUX25_9", + "CFG_CENTER_SW4END2_10", + "CFG_CENTER_BYP2_2", + "CFG_CENTER_IMUX39_3", + "CFG_CENTER_NE2A2_15", + "CFG_CENTER_SE4BEG2_18", + "CFG_CENTER_NE4C1_14", + "CFG_CENTER_WW4A1_5", + "CFG_CENTER_LOGIC_OUTS_B20_1", + "CFG_CENTER_WR1END2_13", + "CFG_CENTER_WW2END1_12", + "CFG_CENTER_SW4END2_8", + "CFG_CENTER_WW2END1_16", + "CFG_CENTER_WW4C1_8", + "CFG_CENTER_BYP1_16", + "CFG_CENTER_NW4A2_9", + "CFG_CENTER_LOGIC_OUTS_B20_7", + "CFG_CENTER_SW4END3_9", + "CFG_CENTER_NW4A3_10", + "CFG_CENTER_WL1END0_9", + "CFG_CENTER_SE2A0_14", + "CFG_CENTER_EE2A3_5", + "CFG_CENTER_WW2A3_6", + "CFG_CENTER_IMUX28_2", + "CFG_CENTER_BYP4_5", + "CFG_CENTER_EL1BEG1_4", + "CFG_CENTER_NE4C2_8", + "CFG_CENTER_LH8_13", + "CFG_CENTER_WW2END0_7", + "CFG_CENTER_WW2A0_5", + "CFG_CENTER_SW2A1_0", + "CFG_CENTER_IMUX13_2", + "CFG_CENTER_LOGIC_OUTS_B16_17", + "CFG_CENTER_WW4END3_11", + "CFG_CENTER_IMUX4_2", + "CFG_CENTER_LH10_3", + "CFG_CENTER_IMUX24_4", + "CFG_CENTER_LOGIC_OUTS_B5_8", + "CFG_CENTER_IMUX10_0", + "CFG_CENTER_EE4BEG1_0", + "CFG_CENTER_IMUX25_10", + "CFG_CENTER_IMUX12_1", + "CFG_CENTER_SW4END0_18", + "CFG_CENTER_FAN1_12", + "CFG_CENTER_LOGIC_OUTS_B5_18", + "CFG_CENTER_WW4END3_0", + "CFG_CENTER_EE4B2_16", + "CFG_CENTER_IMUX2_13", + "CFG_CENTER_LH7_17", + "CFG_CENTER_WW4A0_11", + "CFG_CENTER_LOGIC_OUTS_B6_0", + "CFG_CENTER_SE2A1_4", + "CFG_CENTER_FAN2_8", + "CFG_CENTER_SE4C2_5", + "CFG_CENTER_FAN5_8", + "CFG_CENTER_BYP5_7", + "CFG_CENTER_LOGIC_OUTS_B14_18", + "CFG_CENTER_IMUX46_4", + "CFG_CENTER_WW4C1_13", + "CFG_CENTER_LOGIC_OUTS_B6_9", + "CFG_CENTER_WW2A2_15", + "CFG_CENTER_SE2A2_13", + "CFG_CENTER_IMUX4_16", + "CFG_CENTER_EE4B0_15", + "CFG_CENTER_LOGIC_OUTS_B2_19", + "CFG_CENTER_SE4C0_1", + "CFG_CENTER_NW4END3_11", + "CFG_CENTER_LOGIC_OUTS_B2_14", + "CFG_CENTER_WW4A0_16", + "CFG_CENTER_IMUX34_10", + "CFG_CENTER_CLK1_4", + "CFG_CENTER_WR1END0_11", + "CFG_CENTER_WW4END2_15", + "CFG_CENTER_LH6_11", + "CFG_CENTER_LOGIC_OUTS_B23_2", + "CFG_CENTER_IMUX17_17", + "CFG_CENTER_IMUX32_6", + "CFG_CENTER_CTRL0_11", + "CFG_CENTER_IMUX30_6", + "CFG_CENTER_BYP4_15", + "CFG_CENTER_NE4C2_15", + "CFG_CENTER_EE4B3_10", + "CFG_CENTER_LH7_11", + "CFG_CENTER_SW4END0_17", + "CFG_CENTER_LH7_14", + "CFG_CENTER_LOGIC_OUTS_B14_10", + "CFG_CENTER_SW2A0_1", + "CFG_CENTER_FAN0_11", + "CFG_CENTER_NW4END2_2", + "CFG_CENTER_NW2A2_12", + "CFG_CENTER_NW4A0_5", + "CFG_CENTER_BLOCK_OUTS_B3_10", + "CFG_CENTER_LOGIC_OUTS_B17_19", + "CFG_CENTER_WW4END1_13", + "CFG_CENTER_IMUX28_15", + "CFG_CENTER_WR1END3_3", + "CFG_CENTER_WL1END0_10", + "CFG_CENTER_EE4A0_2", + "CFG_CENTER_EE4C1_19", + "CFG_CENTER_WW2END3_7", + "CFG_CENTER_LOGIC_OUTS_B6_6", + "CFG_CENTER_IMUX37_14", + "CFG_CENTER_SE4C3_15", + "CFG_CENTER_NE4C2_0", + "CFG_CENTER_LH12_13", + "CFG_CENTER_SW4A1_19", + "CFG_CENTER_NE4C2_6", + "CFG_CENTER_EE4BEG1_5", + "CFG_CENTER_NE2A0_16", + "CFG_CENTER_IMUX32_7", + "CFG_CENTER_SE2A2_19", + "CFG_CENTER_WL1END0_7", + "CFG_CENTER_WW4END0_3", + "CFG_CENTER_IMUX27_17", + "CFG_CENTER_LOGIC_OUTS_B15_12", + "CFG_CENTER_EE4C3_15", + "CFG_CENTER_NW4END1_0", + "CFG_CENTER_NW4A3_11", + "CFG_CENTER_NE4BEG2_11", + "CFG_CENTER_LOGIC_OUTS_B8_15", + "CFG_CENTER_SE4C2_11", + "CFG_CENTER_LH11_17", + "CFG_CENTER_IMUX25_18", + "CFG_CENTER_IMUX41_12", + "CFG_CENTER_WW2A1_18", + "CFG_CENTER_LOGIC_OUTS_B22_9", + "CFG_CENTER_SE4C0_2", + "CFG_CENTER_NE2A0_6", + "CFG_CENTER_BYP6_12", + "CFG_CENTER_NE4BEG1_16", + "CFG_CENTER_SE2A1_19", + "CFG_CENTER_IMUX34_0", + "CFG_CENTER_SE4BEG0_14", + "CFG_CENTER_EE2A0_4", + "CFG_CENTER_BYP6_9", + "CFG_CENTER_SE4BEG2_16", + "CFG_CENTER_WR1END0_8", + "CFG_CENTER_NE2A1_5", + "CFG_CENTER_SW2A2_19", + "CFG_CENTER_WW4A0_0", + "CFG_CENTER_WW4B2_13", + "CFG_CENTER_NW4END3_2", + "CFG_CENTER_WW4A0_5", + "CFG_CENTER_WW4B3_15", + "CFG_CENTER_LOGIC_OUTS_B18_13", + "CFG_CENTER_EE2A0_19", + "CFG_CENTER_IMUX26_14", + "CFG_CENTER_LH4_0", + "CFG_CENTER_SW2A1_5", + "CFG_CENTER_EE4BEG1_6", + "CFG_CENTER_IMUX42_15", + "CFG_CENTER_WR1END0_18", + "CFG_CENTER_BLOCK_OUTS_B3_14", + "CFG_CENTER_NW4A2_10", + "CFG_CENTER_IMUX41_16", + "CFG_CENTER_NE4BEG1_2", + "CFG_CENTER_IMUX41_17", + "CFG_CENTER_WW4C3_15", + "CFG_CENTER_BYP6_18", + "CFG_CENTER_LOGIC_OUTS_B15_3", + "CFG_CENTER_SE4C1_3", + "CFG_CENTER_LOGIC_OUTS_B9_5", + "CFG_CENTER_SE4C1_16", + "CFG_CENTER_IMUX27_3", + "CFG_CENTER_LOGIC_OUTS_B23_3", + "CFG_CENTER_SE2A1_1", + "CFG_CENTER_IMUX9_16", + "CFG_CENTER_EE4BEG1_4", + "CFG_CENTER_WW2END0_17", + "CFG_CENTER_EE4C0_18", + "CFG_CENTER_CLK0_0", + "CFG_CENTER_NE2A1_10", + "CFG_CENTER_LOGIC_OUTS_B12_7", + "CFG_CENTER_LOGIC_OUTS_B22_12", + "CFG_CENTER_SE2A3_19", + "CFG_CENTER_NW2A1_15", + "CFG_CENTER_NE4BEG0_7", + "CFG_CENTER_LH11_5", + "CFG_CENTER_NW2A1_14", + "CFG_CENTER_EE4BEG2_16", + "CFG_CENTER_WL1END2_4", + "CFG_CENTER_LH4_16", + "CFG_CENTER_WW2A2_7", + "CFG_CENTER_EE4C1_5", + "CFG_CENTER_IMUX16_15", + "CFG_CENTER_EE2BEG2_5", + "CFG_CENTER_LH1_3", + "CFG_CENTER_FAN5_15", + "CFG_CENTER_NE4C2_10", + "CFG_CENTER_NW4A2_3", + "CFG_CENTER_IMUX24_6", + "CFG_CENTER_IMUX26_12", + "CFG_CENTER_IMUX45_17", + "CFG_CENTER_IMUX24_1", + "CFG_CENTER_EE4BEG2_7", + "CFG_CENTER_IMUX47_19", + "CFG_CENTER_LOGIC_OUTS_B0_12", + "CFG_CENTER_NW4END1_19", + "CFG_CENTER_IMUX4_12", + "CFG_CENTER_LH9_13", + "CFG_CENTER_LH11_2", + "CFG_CENTER_WW4B2_12", + "CFG_CENTER_CLK1_2", + "CFG_CENTER_WR1END3_16", + "CFG_CENTER_SE4C2_2", + "CFG_CENTER_IMUX16_16", + "CFG_CENTER_NW4END2_6", + "CFG_CENTER_IMUX3_16", + "CFG_CENTER_IMUX2_12", + "CFG_CENTER_IMUX20_2", + "CFG_CENTER_IMUX11_19", + "CFG_CENTER_LOGIC_OUTS_B23_15", + "CFG_CENTER_WW4A0_17", + "CFG_CENTER_SE4C0_3", + "CFG_CENTER_NE4C1_12", + "CFG_CENTER_BYP1_7", + "CFG_CENTER_LH6_15", + "CFG_CENTER_IMUX31_17", + "CFG_CENTER_SW4A2_7", + "CFG_CENTER_IMUX21_15", + "CFG_CENTER_WW2END0_5", + "CFG_CENTER_IMUX43_6", + "CFG_CENTER_BLOCK_OUTS_B1_2", + "CFG_CENTER_LOGIC_OUTS_B8_13", + "CFG_CENTER_LOGIC_OUTS_B21_15", + "CFG_CENTER_EE4B2_5", + "CFG_CENTER_WW4END0_6", + "CFG_CENTER_LOGIC_OUTS_B13_5", + "CFG_CENTER_EE4A1_10", + "CFG_CENTER_LH1_12", + "CFG_CENTER_EE2BEG1_2", + "CFG_CENTER_IMUX24_14", + "CFG_CENTER_IMUX23_5", + "CFG_CENTER_LOGIC_OUTS_B19_19", + "CFG_CENTER_EE2A3_1", + "CFG_CENTER_NW4A2_6", + "CFG_CENTER_SE4BEG0_8", + "CFG_CENTER_EE2A2_8", + "CFG_CENTER_SE4BEG1_10", + "CFG_CENTER_LH1_4", + "CFG_CENTER_NW4A0_12", + "CFG_CENTER_SE4C0_12", + "CFG_CENTER_WL1END1_19", + "CFG_CENTER_IMUX13_16", + "CFG_CENTER_WW4END1_18", + "CFG_CENTER_LOGIC_OUTS_B10_8", + "CFG_CENTER_LOGIC_OUTS_B16_18", + "CFG_CENTER_WW4A1_13", + "CFG_CENTER_WW4END3_9", + "CFG_CENTER_WW2END2_0", + "CFG_CENTER_WW4B1_3", + "CFG_CENTER_WW4END3_13", + "CFG_CENTER_WW2END3_10", + "CFG_CENTER_SE4C2_0", + "CFG_CENTER_LOGIC_OUTS_B3_6", + "CFG_CENTER_NE4C3_17", + "CFG_CENTER_LOGIC_OUTS_B10_14", + "CFG_CENTER_IMUX44_1", + "CFG_CENTER_BYP7_10", + "CFG_CENTER_EE4B3_7", + "CFG_CENTER_EE2A1_1", + "CFG_CENTER_IMUX39_10", + "CFG_CENTER_SW4END1_7", + "CFG_CENTER_BYP0_9", + "CFG_CENTER_IMUX26_17", + "CFG_CENTER_EE2BEG0_1", + "CFG_CENTER_NE4C3_15", + "CFG_CENTER_LOGIC_OUTS_B14_6", + "CFG_CENTER_FAN4_7", + "CFG_CENTER_SE4C2_15", + "CFG_CENTER_SE4BEG0_12", + "CFG_CENTER_IMUX39_15", + "CFG_CENTER_IMUX2_1", + "CFG_CENTER_SW4END0_11", + "CFG_CENTER_IMUX41_4", + "CFG_CENTER_SE4BEG0_11", + "CFG_CENTER_IMUX14_3", + "CFG_CENTER_WW2END1_18", + "CFG_CENTER_EE4C2_0", + "CFG_CENTER_IMUX39_1", + "CFG_CENTER_EE4B1_11", + "CFG_CENTER_FAN6_0", + "CFG_CENTER_NE4BEG1_15", + "CFG_CENTER_IMUX11_13", + "CFG_CENTER_EE4A0_11", + "CFG_CENTER_CTRL0_10", + "CFG_CENTER_WW2A0_4", + "CFG_CENTER_WR1END3_0", + "CFG_CENTER_NE2A3_1", + "CFG_CENTER_WW4A2_6", + "CFG_CENTER_WW4B3_8", + "CFG_CENTER_IMUX24_10", + "CFG_CENTER_WW4C0_2", + "CFG_CENTER_BYP3_5", + "CFG_CENTER_BLOCK_OUTS_B3_19", + "CFG_CENTER_LOGIC_OUTS_B1_6", + "CFG_CENTER_NE4C0_12", + "CFG_CENTER_IMUX36_7", + "CFG_CENTER_NE2A3_13", + "CFG_CENTER_BLOCK_OUTS_B3_6", + "CFG_CENTER_WW4A1_4", + "CFG_CENTER_NE4BEG3_9", + "CFG_CENTER_LH11_9", + "CFG_CENTER_LOGIC_OUTS_B20_0", + "CFG_CENTER_ER1BEG2_1", + "CFG_CENTER_LH1_15", + "CFG_CENTER_SW4END3_18", + "CFG_CENTER_BYP5_17", + "CFG_CENTER_EL1BEG0_13", + "CFG_CENTER_SE4BEG1_18", + "CFG_CENTER_WW4END2_2", + "CFG_CENTER_LOGIC_OUTS_B4_11", + "CFG_CENTER_BLOCK_OUTS_B2_9", + "CFG_CENTER_BYP3_0", + "CFG_CENTER_NE2A2_3", + "CFG_CENTER_EE4A0_17", + "CFG_CENTER_NE4BEG0_6", + "CFG_CENTER_SW4A1_10", + "CFG_CENTER_SE4C0_11", + "CFG_CENTER_WL1END3_11", + "CFG_CENTER_NE4C1_13", + "CFG_CENTER_SE4C1_7", + "CFG_CENTER_SW4END2_18", + "CFG_CENTER_IMUX45_1", + "CFG_CENTER_WW4C3_12", + "CFG_CENTER_IMUX10_13", + "CFG_CENTER_IMUX1_5", + "CFG_CENTER_IMUX43_13", + "CFG_CENTER_SW4END3_14", + "CFG_CENTER_EE4B3_14", + "CFG_CENTER_IMUX41_6", + "CFG_CENTER_FAN3_1", + "CFG_CENTER_IMUX38_0", + "CFG_CENTER_EE2A1_16", + "CFG_CENTER_EE2A3_7", + "CFG_CENTER_EE2A3_15", + "CFG_CENTER_FAN5_10", + "CFG_CENTER_EE4B3_0", + "CFG_CENTER_SE4C0_5", + "CFG_CENTER_BYP5_15", + "CFG_CENTER_LOGIC_OUTS_B7_17", + "CFG_CENTER_WR1END2_2", + "CFG_CENTER_EE4A1_3", + "CFG_CENTER_EE4A3_12", + "CFG_CENTER_WR1END1_11", + "CFG_CENTER_BOT_USR_ACCESS_DATA5", + "CFG_CENTER_IMUX44_15", + "CFG_CENTER_IMUX41_2", + "CFG_CENTER_EE4B2_11", + "CFG_CENTER_WW2A1_19", + "CFG_CENTER_LOGIC_OUTS_B22_7", + "CFG_CENTER_IMUX27_15", + "CFG_CENTER_WW4C3_7", + "CFG_CENTER_WW4C2_14", + "CFG_CENTER_CLK0_17", + "CFG_CENTER_EL1BEG3_14", + "CFG_CENTER_WW4C0_13", + "CFG_CENTER_WW2A2_2", + "CFG_CENTER_WW4C2_0", + "CFG_CENTER_LOGIC_OUTS_B19_2", + "CFG_CENTER_EL1BEG0_3", + "CFG_CENTER_WW4C1_18", + "CFG_CENTER_FAN0_15", + "CFG_CENTER_BYP3_13", + "CFG_CENTER_WW2A3_13", + "CFG_CENTER_EE4B1_9", + "CFG_CENTER_IMUX11_4", + "CFG_CENTER_LOGIC_OUTS_B6_8", + "CFG_CENTER_SW4A0_12", + "CFG_CENTER_EE4C3_6", + "CFG_CENTER_SW4END1_10", + "CFG_CENTER_LOGIC_OUTS_B2_10", + "CFG_CENTER_SW2A2_7", + "CFG_CENTER_IMUX24_5", + "CFG_CENTER_SW2A1_14", + "CFG_CENTER_LH6_0", + "CFG_CENTER_WL1END3_2", + "CFG_CENTER_LOGIC_OUTS_B1_15", + "CFG_CENTER_EE4B3_5", + "CFG_CENTER_EE4C3_3", + "CFG_CENTER_SW4END1_5", + "CFG_CENTER_EL1BEG3_11", + "CFG_CENTER_NW4END3_0", + "CFG_CENTER_IMUX37_4", + "CFG_CENTER_EE2BEG3_0", + "CFG_CENTER_NW4A3_4", + "CFG_CENTER_IMUX41_3", + "CFG_CENTER_IMUX1_0", + "CFG_CENTER_ER1BEG3_3", + "CFG_CENTER_EE4A3_8", + "CFG_CENTER_BYP7_1", + "CFG_CENTER_LOGIC_OUTS_B9_19", + "CFG_CENTER_NW4END1_7", + "CFG_CENTER_WW4B1_0", + "CFG_CENTER_LOGIC_OUTS_B7_16", + "CFG_CENTER_EE2A0_14", + "CFG_CENTER_IMUX38_9", + "CFG_CENTER_SE4BEG3_11", + "CFG_CENTER_SE4C3_11", + "CFG_CENTER_SW4A3_9", + "CFG_CENTER_LH10_0", + "CFG_CENTER_ER1BEG2_15", + "CFG_CENTER_LOGIC_OUTS_B17_3", + "CFG_CENTER_EL1BEG2_17", + "CFG_CENTER_EE4A3_5", + "CFG_CENTER_WL1END1_16", + "CFG_CENTER_WR1END1_13", + "CFG_CENTER_LH12_15", + "CFG_CENTER_WW2A1_2", + "CFG_CENTER_WR1END2_3", + "CFG_CENTER_EE4B0_11", + "CFG_CENTER_IMUX37_1", + "CFG_CENTER_WL1END1_2", + "CFG_CENTER_EE2BEG2_3", + "CFG_CENTER_EE4A2_12", + "CFG_CENTER_EE4BEG1_19", + "CFG_CENTER_FAN4_4", + "CFG_CENTER_NW2A3_17", + "CFG_CENTER_WW2END1_4", + "CFG_CENTER_NE4C0_5", + "CFG_CENTER_EE2BEG0_2", + "CFG_CENTER_IMUX16_2", + "CFG_CENTER_CTRL0_2", + "CFG_CENTER_CLK0_8", + "CFG_CENTER_NW4A0_8", + "CFG_CENTER_LH5_0", + "CFG_CENTER_IMUX36_15", + "CFG_CENTER_ER1BEG2_4", + "CFG_CENTER_WW2END0_19", + "CFG_CENTER_LH8_17", + "CFG_CENTER_LOGIC_OUTS_B22_17", + "CFG_CENTER_NW2A2_18", + "CFG_CENTER_IMUX15_2", + "CFG_CENTER_EE4C3_16", + "CFG_CENTER_NW4A1_6", + "CFG_CENTER_IMUX0_2", + "CFG_CENTER_EE4BEG0_10", + "CFG_CENTER_IMUX19_6", + "CFG_CENTER_LOGIC_OUTS_B16_11", + "CFG_CENTER_SE2A3_13", + "CFG_CENTER_WL1END0_19", + "CFG_CENTER_SW4A1_13", + "CFG_CENTER_IMUX46_10", + "CFG_CENTER_SE4C3_14", + "CFG_CENTER_NW2A3_11", + "CFG_CENTER_WR1END3_7", + "CFG_CENTER_LH4_12", + "CFG_CENTER_CLK1_6", + "CFG_CENTER_LOGIC_OUTS_B0_15", + "CFG_CENTER_NE2A0_17", + "CFG_CENTER_IMUX42_19", + "CFG_CENTER_IMUX16_17", + "CFG_CENTER_EE4BEG0_9", + "CFG_CENTER_LOGIC_OUTS_B3_14", + "CFG_CENTER_LH11_19", + "CFG_CENTER_LH11_10", + "CFG_CENTER_EE4BEG0_2", + "CFG_CENTER_NE2A0_1", + "CFG_CENTER_EE4BEG1_3", + "CFG_CENTER_BYP3_7", + "CFG_CENTER_EE2A1_10", + "CFG_CENTER_IMUX19_17", + "CFG_CENTER_LOGIC_OUTS_B15_1", + "CFG_CENTER_NW4A1_17", + "CFG_CENTER_SE2A2_4", + "CFG_CENTER_IMUX43_14", + "CFG_CENTER_SW4A1_0", + "CFG_CENTER_IMUX20_1", + "CFG_CENTER_LOGIC_OUTS_B2_15", + "CFG_CENTER_WW4C1_9", + "CFG_CENTER_EE4C1_17", + "CFG_CENTER_WW4A1_17", + "CFG_CENTER_WW2END3_11", + "CFG_CENTER_WL1END2_16", + "CFG_CENTER_SW4END1_16", + "CFG_CENTER_SW4END3_1", + "CFG_CENTER_SW4A2_8", + "CFG_CENTER_WL1END2_8", + "CFG_CENTER_IMUX35_0", + "CFG_CENTER_LH5_15", + "CFG_CENTER_EE4BEG1_9", + "CFG_CENTER_EE2A2_16", + "CFG_CENTER_LH1_16", + "CFG_CENTER_IMUX6_12", + "CFG_CENTER_EE4C0_13", + "CFG_CENTER_CLK0_3", + "CFG_CENTER_WW2A2_14", + "CFG_CENTER_WW2END0_1", + "CFG_CENTER_WW4A3_12", + "CFG_CENTER_IMUX0_5", + "CFG_CENTER_ER1BEG0_0", + "CFG_CENTER_EE2A2_15", + "CFG_CENTER_LH2_1", + "CFG_CENTER_WW4B1_19", + "CFG_CENTER_IMUX14_16", + "CFG_CENTER_IMUX29_1", + "CFG_CENTER_EE4A2_11", + "CFG_CENTER_SW4A0_6", + "CFG_CENTER_EE2BEG0_10", + "CFG_CENTER_BYP3_1", + "CFG_CENTER_SE4BEG2_2", + "CFG_CENTER_FAN2_1", + "CFG_CENTER_EL1BEG3_12", + "CFG_CENTER_NW4A3_17", + "CFG_CENTER_IMUX20_5", + "CFG_CENTER_WW4C2_7", + "CFG_CENTER_LOGIC_OUTS_B16_7", + "CFG_CENTER_FAN5_6", + "CFG_CENTER_IMUX40_3", + "CFG_CENTER_IMUX7_6", + "CFG_CENTER_IMUX8_0", + "CFG_CENTER_IMUX25_14", + "CFG_CENTER_FAN3_11", + "CFG_CENTER_EL1BEG2_18", + "CFG_CENTER_EE4BEG1_2", + "CFG_CENTER_EL1BEG2_8", + "CFG_CENTER_BYP4_6", + "CFG_CENTER_BYP1_0", + "CFG_CENTER_SE2A3_4", + "CFG_CENTER_EE4BEG3_19", + "CFG_CENTER_FAN5_11", + "CFG_CENTER_IMUX35_1", + "CFG_CENTER_IMUX37_19", + "CFG_CENTER_WL1END3_1", + "CFG_CENTER_LOGIC_OUTS_B11_17", + "CFG_CENTER_WW4A2_8", + "CFG_CENTER_EE4A3_19", + "CFG_CENTER_LOGIC_OUTS_B10_17", + "CFG_CENTER_NW4END1_1", + "CFG_CENTER_SW4A1_6", + "CFG_CENTER_LOGIC_OUTS_B23_11", + "CFG_CENTER_WW2A0_10", + "CFG_CENTER_NW4A2_8", + "CFG_CENTER_WR1END2_18", + "CFG_CENTER_NE2A2_2", + "CFG_CENTER_WW4B1_6", + "CFG_CENTER_SW4END3_6", + "CFG_CENTER_WW4C2_17", + "CFG_CENTER_LOGIC_OUTS_B8_7", + "CFG_CENTER_LOGIC_OUTS_B3_4", + "CFG_CENTER_IMUX28_13", + "CFG_CENTER_WR1END1_16", + "CFG_CENTER_EE4B2_18", + "CFG_CENTER_IMUX23_8", + "CFG_CENTER_FAN5_12", + "CFG_CENTER_WW4B2_11", + "CFG_CENTER_IMUX17_4", + "CFG_CENTER_IMUX15_16", + "CFG_CENTER_WL1END0_8", + "CFG_CENTER_WW2END3_1", + "CFG_CENTER_LH12_4", + "CFG_CENTER_SE2A3_3", + "CFG_CENTER_LOGIC_OUTS_B12_9", + "CFG_CENTER_SE4C1_11", + "CFG_CENTER_WL1END1_9", + "CFG_CENTER_NW4END3_9", + "CFG_CENTER_NW4END2_17", + "CFG_CENTER_LOGIC_OUTS_B14_3", + "CFG_CENTER_WW4END1_9", + "CFG_CENTER_EE4A0_1", + "CFG_CENTER_IMUX23_11", + "CFG_CENTER_IMUX36_3", + "CFG_CENTER_NE4BEG1_11", + "CFG_CENTER_IMUX44_18", + "CFG_CENTER_IMUX8_12", + "CFG_CENTER_LOGIC_OUTS_B13_18", + "CFG_CENTER_SE4C0_7", + "CFG_CENTER_EE4C0_5", + "CFG_CENTER_EE4A2_4", + "CFG_CENTER_NE4BEG1_5", + "CFG_CENTER_SW4A2_17", + "CFG_CENTER_LH5_4", + "CFG_CENTER_IMUX21_5", + "CFG_CENTER_FAN7_1", + "CFG_CENTER_LOGIC_OUTS_B3_18", + "CFG_CENTER_WW4C0_14", + "CFG_CENTER_NW4END3_6", + "CFG_CENTER_NW4END1_4", + "CFG_CENTER_IMUX28_0", + "CFG_CENTER_EL1BEG1_5", + "CFG_CENTER_ER1BEG2_14", + "CFG_CENTER_LH9_4", + "CFG_CENTER_EE2BEG3_8", + "CFG_CENTER_NW4END3_12", + "CFG_CENTER_LOGIC_OUTS_B23_1", + "CFG_CENTER_WL1END2_7", + "CFG_CENTER_IMUX40_7", + "CFG_CENTER_FAN3_15", + "CFG_CENTER_FAN5_7", + "CFG_CENTER_NE2A1_18", + "CFG_CENTER_BLOCK_OUTS_B1_18", + "CFG_CENTER_WR1END2_8", + "CFG_CENTER_EE4BEG0_8", + "CFG_CENTER_BLOCK_OUTS_B3_11", + "CFG_CENTER_SW2A1_12", + "CFG_CENTER_SW4A0_15", + "CFG_CENTER_IMUX34_9", + "CFG_CENTER_LOGIC_OUTS_B20_13", + "CFG_CENTER_IMUX12_3", + "CFG_CENTER_IMUX4_17", + "CFG_CENTER_NE4BEG3_5", + "CFG_CENTER_FAN0_7", + "CFG_CENTER_SW4A0_8", + "CFG_CENTER_LOGIC_OUTS_B17_0", + "CFG_CENTER_IMUX44_4", + "CFG_CENTER_IMUX30_15", + "CFG_CENTER_SW4END2_9", + "CFG_CENTER_LOGIC_OUTS_B16_4", + "CFG_CENTER_IMUX34_18", + "CFG_CENTER_NW2A3_9", + "CFG_CENTER_SE4C0_10", + "CFG_CENTER_NE4C1_1", + "CFG_CENTER_BLOCK_OUTS_B1_13", + "CFG_CENTER_SE2A3_18", + "CFG_CENTER_SW2A1_17", + "CFG_CENTER_IMUX18_13", + "CFG_CENTER_EE4B1_5", + "CFG_CENTER_IMUX19_1", + "CFG_CENTER_CTRL0_5", + "CFG_CENTER_LH12_10", + "CFG_CENTER_BYP6_6", + "CFG_CENTER_IMUX37_3", + "CFG_CENTER_IMUX23_16", + "CFG_CENTER_SE4BEG0_6", + "CFG_CENTER_LH11_15", + "CFG_CENTER_NW4A2_0", + "CFG_CENTER_EE4BEG2_2", + "CFG_CENTER_SW4END3_7", + "CFG_CENTER_IMUX29_16", + "CFG_CENTER_LH12_6", + "CFG_CENTER_IMUX7_0", + "CFG_CENTER_IMUX34_1", + "CFG_CENTER_IMUX42_14", + "CFG_CENTER_BYP3_15", + "CFG_CENTER_IMUX41_7", + "CFG_CENTER_LH1_5", + "CFG_CENTER_WW4END0_7", + "CFG_CENTER_LOGIC_OUTS_B0_9", + "CFG_CENTER_NW2A3_15", + "CFG_CENTER_LOGIC_OUTS_B22_14", + "CFG_CENTER_EE4B2_8", + "CFG_CENTER_IMUX24_0", + "CFG_CENTER_LOGIC_OUTS_B4_2", + "CFG_CENTER_IMUX15_15", + "CFG_CENTER_SE2A2_17", + "CFG_CENTER_IMUX15_11", + "CFG_CENTER_CLK1_13", + "CFG_CENTER_EE2A2_5", + "CFG_CENTER_FAN3_9", + "CFG_CENTER_EE2BEG2_11", + "CFG_CENTER_IMUX28_1", + "CFG_CENTER_NE4BEG2_4", + "CFG_CENTER_BLOCK_OUTS_B1_9", + "CFG_CENTER_IMUX0_6", + "CFG_CENTER_LH3_7", + "CFG_CENTER_LH6_10", + "CFG_CENTER_WW4A3_18", + "CFG_CENTER_LOGIC_OUTS_B9_0", + "CFG_CENTER_SW2A1_18", + "CFG_CENTER_WW4C2_9", + "CFG_CENTER_IMUX42_17", + "CFG_CENTER_IMUX41_8", + "CFG_CENTER_FAN6_15", + "CFG_CENTER_IMUX1_19", + "CFG_CENTER_WW2END2_14", + "CFG_CENTER_EL1BEG0_10", + "CFG_CENTER_BYP4_17", + "CFG_CENTER_IMUX41_15", + "CFG_CENTER_IMUX27_5", + "CFG_CENTER_FAN7_12", + "CFG_CENTER_SW4END1_8", + "CFG_CENTER_NW4A2_13", + "CFG_CENTER_NW4END1_16", + "CFG_CENTER_LOGIC_OUTS_B9_14", + "CFG_CENTER_FAN3_2", + "CFG_CENTER_NW4A2_17", + "CFG_CENTER_WL1END1_12", + "CFG_CENTER_LOGIC_OUTS_B1_0", + "CFG_CENTER_SE4BEG1_14", + "CFG_CENTER_EE2BEG0_18", + "CFG_CENTER_IMUX3_2", + "CFG_CENTER_WW4A3_3", + "CFG_CENTER_FAN6_2", + "CFG_CENTER_SW4END1_6", + "CFG_CENTER_NE4BEG2_1", + "CFG_CENTER_BYP4_7", + "CFG_CENTER_NE4C3_12", + "CFG_CENTER_NE4BEG0_15", + "CFG_CENTER_IMUX47_17", + "CFG_CENTER_FAN4_0", + "CFG_CENTER_NE2A1_6", + "CFG_CENTER_WW2END3_15", + "CFG_CENTER_IMUX35_9", + "CFG_CENTER_IMUX18_11", + "CFG_CENTER_WW4A0_19", + "CFG_CENTER_ER1BEG0_3", + "CFG_CENTER_BYP3_16", + "CFG_CENTER_SW4A1_12", + "CFG_CENTER_SW4A3_8", + "CFG_CENTER_WW2END0_0", + "CFG_CENTER_LH6_9", + "CFG_CENTER_EE4BEG2_4", + "CFG_CENTER_LOGIC_OUTS_B3_19", + "CFG_CENTER_EE2BEG2_12", + "CFG_CENTER_WL1END0_14", + "CFG_CENTER_BLOCK_OUTS_B0_6", + "CFG_CENTER_IMUX46_14", + "CFG_CENTER_WW4END3_10", + "CFG_CENTER_SW2A3_16", + "CFG_CENTER_IMUX28_14", + "CFG_CENTER_EE2BEG0_11", + "CFG_CENTER_IMUX44_0", + "CFG_CENTER_ER1BEG2_18", + "CFG_CENTER_IMUX5_4", + "CFG_CENTER_NW4A2_7", + "CFG_CENTER_WW2A0_0", + "CFG_CENTER_NE2A0_10", + "CFG_CENTER_WW4C1_4", + "CFG_CENTER_LOGIC_OUTS_B17_2", + "CFG_CENTER_IMUX29_3", + "CFG_CENTER_BLOCK_OUTS_B1_10", + "CFG_CENTER_EE2BEG3_10", + "CFG_CENTER_WW4A1_16", + "CFG_CENTER_EE4A0_16", + "CFG_CENTER_IMUX15_0", + "CFG_CENTER_EE4C3_12", + "CFG_CENTER_IMUX44_13", + "CFG_CENTER_LH2_11", + "CFG_CENTER_EE4B2_12", + "CFG_CENTER_WW2A2_17", + "CFG_CENTER_BLOCK_OUTS_B0_8", + "CFG_CENTER_EE4A3_9", + "CFG_CENTER_EE4A3_17", + "CFG_CENTER_NE4BEG1_6", + "CFG_CENTER_WW2END2_5", + "CFG_CENTER_IMUX12_8", + "CFG_CENTER_NW2A2_10", + "CFG_CENTER_IMUX22_14", + "CFG_CENTER_WW4END1_7", + "CFG_CENTER_LOGIC_OUTS_B0_11", + "CFG_CENTER_WW2A1_3", + "CFG_CENTER_CLK1_17", + "CFG_CENTER_WW4C1_3", + "CFG_CENTER_IMUX11_7", + "CFG_CENTER_NE4BEG2_13", + "CFG_CENTER_BYP5_10", + "CFG_CENTER_IMUX16_6", + "CFG_CENTER_LOGIC_OUTS_B22_3", + "CFG_CENTER_IMUX33_6", + "CFG_CENTER_NE2A1_11", + "CFG_CENTER_WW4C0_0", + "CFG_CENTER_IMUX29_2", + "CFG_CENTER_BLOCK_OUTS_B2_14", + "CFG_CENTER_SE4C3_7", + "CFG_CENTER_SW2A0_18", + "CFG_CENTER_EE4C2_17", + "CFG_CENTER_LH5_9", + "CFG_CENTER_IMUX2_0", + "CFG_CENTER_EE4BEG2_9", + "CFG_CENTER_SW2A2_6", + "CFG_CENTER_IMUX11_2", + "CFG_CENTER_NE4BEG0_13", + "CFG_CENTER_WL1END2_15", + "CFG_CENTER_IMUX12_9", + "CFG_CENTER_IMUX25_12", + "CFG_CENTER_SW4A0_13", + "CFG_CENTER_SE2A0_2", + "CFG_CENTER_LH8_3", + "CFG_CENTER_EL1BEG0_8", + "CFG_CENTER_BYP7_12", + "CFG_CENTER_FAN7_11", + "CFG_CENTER_IMUX43_3", + "CFG_CENTER_EE4A3_6", + "CFG_CENTER_LOGIC_OUTS_B12_0", + "CFG_CENTER_LH7_13", + "CFG_CENTER_LOGIC_OUTS_B12_10", + "CFG_CENTER_EE2BEG3_13", + "CFG_CENTER_WW4A3_1", + "CFG_CENTER_SE4C1_12", + "CFG_CENTER_WW4B0_14", + "CFG_CENTER_WW4B2_0", + "CFG_CENTER_IMUX30_4", + "CFG_CENTER_SW2A0_2", + "CFG_CENTER_ER1BEG3_16", + "CFG_CENTER_LOGIC_OUTS_B13_4", + "CFG_CENTER_IMUX40_2", + "CFG_CENTER_FAN1_0", + "CFG_CENTER_LH10_11", + "CFG_CENTER_NE4C2_5", + "CFG_CENTER_NE2A0_18", + "CFG_CENTER_EE4A0_7", + "CFG_CENTER_LOGIC_OUTS_B9_16", + "CFG_CENTER_WW2END2_8", + "CFG_CENTER_WR1END1_5", + "CFG_CENTER_IMUX2_9", + "CFG_CENTER_NE2A3_17", + "CFG_CENTER_LOGIC_OUTS_B4_17", + "CFG_CENTER_EE2BEG0_9", + "CFG_CENTER_IMUX20_16", + "CFG_CENTER_SE2A3_14", + "CFG_CENTER_NE2A1_12", + "CFG_CENTER_WW2END3_19", + "CFG_CENTER_LOGIC_OUTS_B3_10", + "CFG_CENTER_EL1BEG3_13", + "CFG_CENTER_EE4C0_11", + "CFG_CENTER_FAN1_7", + "CFG_CENTER_NE4C2_1", + "CFG_CENTER_LOGIC_OUTS_B12_5", + "CFG_CENTER_EE4B0_18", + "CFG_CENTER_NW4A1_4", + "CFG_CENTER_BLOCK_OUTS_B2_12", + "CFG_CENTER_LOGIC_OUTS_B2_1", + "CFG_CENTER_WW2A0_11", + "CFG_CENTER_FAN6_9", + "CFG_CENTER_NE4C0_17", + "CFG_CENTER_IMUX15_1", + "CFG_CENTER_IMUX42_3", + "CFG_CENTER_WW4B0_10", + "CFG_CENTER_WW2A0_15", + "CFG_CENTER_SE2A1_15", + "CFG_CENTER_WW2A0_17", + "CFG_CENTER_IMUX21_17", + "CFG_CENTER_LOGIC_OUTS_B17_7", + "CFG_CENTER_NE4BEG1_14", + "CFG_CENTER_LH9_2", + "CFG_CENTER_IMUX45_10", + "CFG_CENTER_LOGIC_OUTS_B3_3", + "CFG_CENTER_FAN0_13", + "CFG_CENTER_WW2A3_7", + "CFG_CENTER_IMUX2_6", + "CFG_CENTER_IMUX19_13", + "CFG_CENTER_EL1BEG3_8", + "CFG_CENTER_IMUX26_0", + "CFG_CENTER_LOGIC_OUTS_B21_14", + "CFG_CENTER_EE2A1_4", + "CFG_CENTER_NE4BEG3_19", + "CFG_CENTER_SW2A3_2", + "CFG_CENTER_EE4BEG1_12", + "CFG_CENTER_NW4A0_4", + "CFG_CENTER_WW4C1_11", + "CFG_CENTER_WR1END1_6", + "CFG_CENTER_IMUX38_19", + "CFG_CENTER_SW4END2_4", + "CFG_CENTER_LOGIC_OUTS_B11_15", + "CFG_CENTER_IMUX12_14", + "CFG_CENTER_LH9_5", + "CFG_CENTER_IMUX36_12", + "CFG_CENTER_SW4A1_3", + "CFG_CENTER_FAN2_15", + "CFG_CENTER_LH6_6", + "CFG_CENTER_IMUX42_4", + "CFG_CENTER_IMUX7_16", + "CFG_CENTER_LOGIC_OUTS_B16_1", + "CFG_CENTER_WW4A0_2", + "CFG_CENTER_WW2A1_13", + "CFG_CENTER_LH3_15", + "CFG_CENTER_EE4C1_10", + "CFG_CENTER_BLOCK_OUTS_B0_18", + "CFG_CENTER_CLK1_9", + "CFG_CENTER_LH11_7", + "CFG_CENTER_BYP7_15", + "CFG_CENTER_WW4C2_1", + "CFG_CENTER_NW4A0_3", + "CFG_CENTER_IMUX8_14", + "CFG_CENTER_WW4C0_7", + "CFG_CENTER_WW2A1_5", + "CFG_CENTER_SW4END0_1", + "CFG_CENTER_NW4END3_18", + "CFG_CENTER_SW4A3_16", + "CFG_CENTER_EE4A3_15", + "CFG_CENTER_EL1BEG2_11", + "CFG_CENTER_IMUX14_10", + "CFG_CENTER_EE2BEG3_9", + "CFG_CENTER_SE2A0_1", + "CFG_CENTER_WL1END1_13", + "CFG_CENTER_WW2END1_0", + "CFG_CENTER_NW2A2_4", + "CFG_CENTER_SE4C0_13", + "CFG_CENTER_BYP0_1", + "CFG_CENTER_WW2A3_2", + "CFG_CENTER_LOGIC_OUTS_B5_13", + "CFG_CENTER_ER1BEG0_2", + "CFG_CENTER_WL1END3_14", + "CFG_CENTER_NE4BEG0_0", + "CFG_CENTER_LOGIC_OUTS_B4_6", + "CFG_CENTER_ER1BEG3_2", + "CFG_CENTER_IMUX40_9", + "CFG_CENTER_SE4C3_18", + "CFG_CENTER_SE4C2_18", + "CFG_CENTER_EE4B0_10", + "CFG_CENTER_LOGIC_OUTS_B3_11", + "CFG_CENTER_IMUX15_18", + "CFG_CENTER_IMUX19_4", + "CFG_CENTER_LOGIC_OUTS_B21_5", + "CFG_CENTER_EE4A0_14", + "CFG_CENTER_IMUX23_7", + "CFG_CENTER_IMUX34_5", + "CFG_CENTER_WW4A2_1", + "CFG_CENTER_IMUX13_14", + "CFG_CENTER_EE4B1_13", + "CFG_CENTER_IMUX16_7", + "CFG_CENTER_BLOCK_OUTS_B3_1", + "CFG_CENTER_WW4A3_7", + "CFG_CENTER_LOGIC_OUTS_B12_15", + "CFG_CENTER_NE4BEG3_6", + "CFG_CENTER_LOGIC_OUTS_B8_4", + "CFG_CENTER_WW4A1_10", + "CFG_CENTER_WW4B3_3", + "CFG_CENTER_FAN4_14", + "CFG_CENTER_SE2A2_12", + "CFG_CENTER_LOGIC_OUTS_B10_12", + "CFG_CENTER_WW4A2_0", + "CFG_CENTER_WW4B3_11", + "CFG_CENTER_IMUX42_8", + "CFG_CENTER_NE4C1_18", + "CFG_CENTER_NE2A2_1", + "CFG_CENTER_LH10_12", + "CFG_CENTER_NE2A0_2", + "CFG_CENTER_WW4END1_2", + "CFG_CENTER_IMUX43_8", + "CFG_CENTER_NE2A2_12", + "CFG_CENTER_EE2BEG1_9", + "CFG_CENTER_SE2A2_18", + "CFG_CENTER_FAN4_8", + "CFG_CENTER_LH9_6", + "CFG_CENTER_WW4END1_15", + "CFG_CENTER_WR1END0_9", + "CFG_CENTER_LH11_14", + "CFG_CENTER_SW4A0_11", + "CFG_CENTER_BLOCK_OUTS_B3_4", + "CFG_CENTER_IMUX2_4", + "CFG_CENTER_LOGIC_OUTS_B20_3", + "CFG_CENTER_EE4BEG0_0", + "CFG_CENTER_EL1BEG0_7", + "CFG_CENTER_WW2END3_12", + "CFG_CENTER_IMUX27_8", + "CFG_CENTER_EL1BEG2_1", + "CFG_CENTER_EE2A3_6", + "CFG_CENTER_LOGIC_OUTS_B13_2", + "CFG_CENTER_FAN0_0", + "CFG_CENTER_SE4C1_15", + "CFG_CENTER_WW2A3_10", + "CFG_CENTER_NW4END1_2", + "CFG_CENTER_NW2A2_7", + "CFG_CENTER_NW2A3_10", + "CFG_CENTER_LOGIC_OUTS_B21_10", + "CFG_CENTER_IMUX7_3", + "CFG_CENTER_IMUX21_9", + "CFG_CENTER_SW4END0_5", + "CFG_CENTER_IMUX19_7", + "CFG_CENTER_NE2A2_10", + "CFG_CENTER_IMUX6_6", + "CFG_CENTER_WW4B1_7", + "CFG_CENTER_SE4C3_2", + "CFG_CENTER_EE4BEG1_13", + "CFG_CENTER_IMUX7_14", + "CFG_CENTER_NE4BEG2_2", + "CFG_CENTER_ER1BEG0_15", + "CFG_CENTER_IMUX44_8", + "CFG_CENTER_SE4BEG3_18", + "CFG_CENTER_LOGIC_OUTS_B1_12", + "CFG_CENTER_FAN7_7", + "CFG_CENTER_EE2A3_10", + "CFG_CENTER_EL1BEG2_3", + "CFG_CENTER_NE2A2_14", + "CFG_CENTER_SE4BEG2_5", + "CFG_CENTER_BLOCK_OUTS_B1_4", + "CFG_CENTER_NE4BEG0_8", + "CFG_CENTER_EE4B1_12", + "CFG_CENTER_IMUX38_2", + "CFG_CENTER_IMUX1_9", + "CFG_CENTER_NE4BEG3_16", + "CFG_CENTER_WW4A2_12", + "CFG_CENTER_LOGIC_OUTS_B17_4", + "CFG_CENTER_WW2END0_4", + "CFG_CENTER_EE4C2_7", + "CFG_CENTER_LOGIC_OUTS_B19_0", + "CFG_CENTER_IMUX36_18", + "CFG_CENTER_LOGIC_OUTS_B20_16", + "CFG_CENTER_LH12_16", + "CFG_CENTER_BLOCK_OUTS_B0_7", + "CFG_CENTER_WW2A0_8", + "CFG_CENTER_LOGIC_OUTS_B22_18", + "CFG_CENTER_SW4A0_4", + "CFG_CENTER_WW2END2_18", + "CFG_CENTER_SE4BEG3_2", + "CFG_CENTER_EE4A0_6", + "CFG_CENTER_LOGIC_OUTS_B1_18", + "CFG_CENTER_SE2A3_8", + "CFG_CENTER_IMUX14_11", + "CFG_CENTER_SW2A0_3", + "CFG_CENTER_NE4C0_6", + "CFG_CENTER_EE2A3_2", + "CFG_CENTER_NE4C1_17", + "CFG_CENTER_LOGIC_OUTS_B19_14", + "CFG_CENTER_IMUX21_2", + "CFG_CENTER_WL1END2_14", + "CFG_CENTER_EE4C2_6", + "CFG_CENTER_IMUX19_2", + "CFG_CENTER_EE4BEG3_7", + "CFG_CENTER_IMUX40_17", + "CFG_CENTER_EE4BEG2_12", + "CFG_CENTER_IMUX44_6", + "CFG_CENTER_EE4C0_7", + "CFG_CENTER_CLK0_12", + "CFG_CENTER_SW4A3_0", + "CFG_CENTER_WW4B0_3", + "CFG_CENTER_WW4C2_6", + "CFG_CENTER_LOGIC_OUTS_B12_16", + "CFG_CENTER_WW4B2_17", + "CFG_CENTER_WW2END0_6", + "CFG_CENTER_IMUX42_5", + "CFG_CENTER_NE4BEG0_18", + "CFG_CENTER_NE2A0_7", + "CFG_CENTER_WR1END0_13", + "CFG_CENTER_SE2A1_13", + "CFG_CENTER_IMUX0_13", + "CFG_CENTER_EE4A3_10", + "CFG_CENTER_LOGIC_OUTS_B7_8", + "CFG_CENTER_SW4END0_12", + "CFG_CENTER_SW2A2_15", + "CFG_CENTER_FAN1_3", + "CFG_CENTER_WW4END0_4", + "CFG_CENTER_SW4END2_16", + "CFG_CENTER_IMUX43_2", + "CFG_CENTER_LOGIC_OUTS_B20_18", + "CFG_CENTER_SW4END3_19", + "CFG_CENTER_WL1END0_2", + "CFG_CENTER_LH6_7", + "CFG_CENTER_WW2A0_1", + "CFG_CENTER_IMUX27_19", + "CFG_CENTER_LOGIC_OUTS_B21_6", + "CFG_CENTER_IMUX41_11", + "CFG_CENTER_EE2BEG2_8", + "CFG_CENTER_LH11_16", + "CFG_CENTER_LOGIC_OUTS_B21_19", + "CFG_CENTER_NE4BEG1_12", + "CFG_CENTER_LOGIC_OUTS_B18_19", + "CFG_CENTER_IMUX17_15", + "CFG_CENTER_IMUX26_8", + "CFG_CENTER_EE4C2_3", + "CFG_CENTER_LH3_4", + "CFG_CENTER_WL1END0_15", + "CFG_CENTER_EE4C2_10", + "CFG_CENTER_WR1END0_10", + "CFG_CENTER_NE4C3_11", + "CFG_CENTER_WL1END1_17", + "CFG_CENTER_LH9_3", + "CFG_CENTER_BYP6_0", + "CFG_CENTER_SE4C1_14", + "CFG_CENTER_LH1_14", + "CFG_CENTER_EL1BEG0_16", + "CFG_CENTER_IMUX29_9", + "CFG_CENTER_LOGIC_OUTS_B11_13", + "CFG_CENTER_IMUX30_11", + "CFG_CENTER_SE4BEG0_16", + "CFG_CENTER_WR1END2_10", + "CFG_CENTER_BYP4_14", + "CFG_CENTER_EE4C3_1", + "CFG_CENTER_WW2END2_13", + "CFG_CENTER_IMUX22_0", + "CFG_CENTER_NE2A2_7", + "CFG_CENTER_EE2A0_18", + "CFG_CENTER_LOGIC_OUTS_B7_2", + "CFG_CENTER_EE2BEG0_19", + "CFG_CENTER_SE2A2_10", + "CFG_CENTER_IMUX9_3", + "CFG_CENTER_IMUX28_5", + "CFG_CENTER_BYP7_2", + "CFG_CENTER_IMUX26_18", + "CFG_CENTER_WL1END2_9", + "CFG_CENTER_IMUX35_5", + "CFG_CENTER_IMUX21_18", + "CFG_CENTER_WW4C0_18", + "CFG_CENTER_WL1END3_7", + "CFG_CENTER_WW2A3_15", + "CFG_CENTER_SW2A1_4", + "CFG_CENTER_IMUX13_17", + "CFG_CENTER_NE4BEG2_19", + "CFG_CENTER_BYP4_0", + "CFG_CENTER_NE4C1_2", + "CFG_CENTER_IMUX45_11", + "CFG_CENTER_LOGIC_OUTS_B4_16", + "CFG_CENTER_LOGIC_OUTS_B14_5", + "CFG_CENTER_WW4C0_8", + "CFG_CENTER_BOT_CFG_IO_ACCESS_VGGCOMPOUT", + "CFG_CENTER_LOGIC_OUTS_B16_14", + "CFG_CENTER_WW4B0_7", + "CFG_CENTER_LOGIC_OUTS_B10_10", + "CFG_CENTER_ER1BEG2_3", + "CFG_CENTER_WW4C0_16", + "CFG_CENTER_IMUX44_2", + "CFG_CENTER_EE4BEG1_8", + "CFG_CENTER_EL1BEG1_15", + "CFG_CENTER_ER1BEG1_14", + "CFG_CENTER_LOGIC_OUTS_B6_18", + "CFG_CENTER_IMUX45_19", + "CFG_CENTER_SE4BEG1_7", + "CFG_CENTER_LOGIC_OUTS_B13_6", + "CFG_CENTER_EE2BEG3_2", + "CFG_CENTER_CTRL1_11", + "CFG_CENTER_BYP5_8", + "CFG_CENTER_LOGIC_OUTS_B16_9", + "CFG_CENTER_WW4C1_6", + "CFG_CENTER_BYP6_7", + "CFG_CENTER_SE2A2_8", + "CFG_CENTER_WW2A2_11", + "CFG_CENTER_IMUX42_2", + "CFG_CENTER_EE4BEG0_4", + "CFG_CENTER_IMUX8_1", + "CFG_CENTER_NW2A1_16", + "CFG_CENTER_LOGIC_OUTS_B13_17", + "CFG_CENTER_EE2A0_12", + "CFG_CENTER_SE4BEG1_13", + "CFG_CENTER_SE4BEG3_10", + "CFG_CENTER_FAN7_15", + "CFG_CENTER_SE2A0_10", + "CFG_CENTER_EE4B1_8", + "CFG_CENTER_IMUX33_19", + "CFG_CENTER_BLOCK_OUTS_B2_15", + "CFG_CENTER_WW4A0_4", + "CFG_CENTER_IMUX44_17", + "CFG_CENTER_WW2A1_15", + "CFG_CENTER_IMUX7_18", + "CFG_CENTER_IMUX21_16", + "CFG_CENTER_LH7_8", + "CFG_CENTER_SW4A1_8", + "CFG_CENTER_LOGIC_OUTS_B7_0", + "CFG_CENTER_WW2END2_19", + "CFG_CENTER_EE4B3_1", + "CFG_CENTER_IMUX11_16", + "CFG_CENTER_IMUX29_14", + "CFG_CENTER_SE4BEG3_7", + "CFG_CENTER_IMUX12_18", + "CFG_CENTER_EE4B1_7", + "CFG_CENTER_EL1BEG2_2", + "CFG_CENTER_EE2A0_11", + "CFG_CENTER_FAN6_18", + "CFG_CENTER_LOGIC_OUTS_B23_6", + "CFG_CENTER_IMUX6_10", + "CFG_CENTER_NW4END0_0", + "CFG_CENTER_LOGIC_OUTS_B16_8", + "CFG_CENTER_BYP1_12", + "CFG_CENTER_FAN6_10", + "CFG_CENTER_LOGIC_OUTS_B11_7", + "CFG_CENTER_IMUX27_12", + "CFG_CENTER_CLK1_11", + "CFG_CENTER_IMUX13_8", + "CFG_CENTER_WW4END3_2", + "CFG_CENTER_IMUX8_15", + "CFG_CENTER_IMUX15_7", + "CFG_CENTER_LOGIC_OUTS_B12_8", + "CFG_CENTER_NE2A1_13", + "CFG_CENTER_WW2A1_12", + "CFG_CENTER_IMUX38_11", + "CFG_CENTER_IMUX14_1", + "CFG_CENTER_BYP7_9", + "CFG_CENTER_LH5_3", + "CFG_CENTER_NW2A3_19", + "CFG_CENTER_NE2A1_9", + "CFG_CENTER_NW4A0_9", + "CFG_CENTER_LOGIC_OUTS_B8_11", + "CFG_CENTER_SE2A1_3", + "CFG_CENTER_NW4A1_14", + "CFG_CENTER_IMUX21_1", + "CFG_CENTER_WR1END0_17", + "CFG_CENTER_SW4END1_14", + "CFG_CENTER_LOGIC_OUTS_B22_0", + "CFG_CENTER_IMUX38_16", + "CFG_CENTER_NW4END3_10", + "CFG_CENTER_WW4B2_1", + "CFG_CENTER_IMUX45_12", + "CFG_CENTER_BLOCK_OUTS_B0_11", + "CFG_CENTER_FAN1_4", + "CFG_CENTER_SW2A3_7", + "CFG_CENTER_WL1END1_18", + "CFG_CENTER_IMUX38_7", + "CFG_CENTER_NE4C1_4", + "CFG_CENTER_IMUX3_1", + "CFG_CENTER_IMUX34_13", + "CFG_CENTER_SW4A3_7", + "CFG_CENTER_EE4A1_11", + "CFG_CENTER_LOGIC_OUTS_B1_3", + "CFG_CENTER_SE2A0_6", + "CFG_CENTER_IMUX31_11", + "CFG_CENTER_FAN5_17", + "CFG_CENTER_EE4A0_4", + "CFG_CENTER_IMUX46_5", + "CFG_CENTER_IMUX39_16", + "CFG_CENTER_SW4A0_10", + "CFG_CENTER_CLK0_7", + "CFG_CENTER_WW4C0_10", + "CFG_CENTER_LOGIC_OUTS_B19_6", + "CFG_CENTER_WW2END2_17", + "CFG_CENTER_IMUX38_18", + "CFG_CENTER_WW4C0_3", + "CFG_CENTER_EE4C0_6", + "CFG_CENTER_CLK0_9", + "CFG_CENTER_WW2END3_16", + "CFG_CENTER_LOGIC_OUTS_B10_13", + "CFG_CENTER_WW2END3_4", + "CFG_CENTER_IMUX20_19", + "CFG_CENTER_SW4A3_11", + "CFG_CENTER_LOGIC_OUTS_B14_12", + "CFG_CENTER_EE4C0_14", + "CFG_CENTER_SW4END1_13", + "CFG_CENTER_IMUX32_4", + "CFG_CENTER_WW2A1_8", + "CFG_CENTER_WW4B2_2", + "CFG_CENTER_NE2A2_13", + "CFG_CENTER_EE2A2_4", + "CFG_CENTER_IMUX7_4", + "CFG_CENTER_NE4BEG3_11", + "CFG_CENTER_LOGIC_OUTS_B0_13", + "CFG_CENTER_IMUX13_4", + "CFG_CENTER_IMUX0_15", + "CFG_CENTER_LOGIC_OUTS_B8_18", + "CFG_CENTER_LOGIC_OUTS_B9_4", + "CFG_CENTER_LOGIC_OUTS_B23_0", + "CFG_CENTER_LOGIC_OUTS_B23_4", + "CFG_CENTER_NE4BEG3_4", + "CFG_CENTER_IMUX5_12", + "CFG_CENTER_WW2END3_14", + "CFG_CENTER_LOGIC_OUTS_B23_18", + "CFG_CENTER_SW4A0_18", + "CFG_CENTER_EE4C0_1", + "CFG_CENTER_LOGIC_OUTS_B14_14", + "CFG_CENTER_CTRL0_16", + "CFG_CENTER_IMUX4_6", + "CFG_CENTER_WW2END2_6", + "CFG_CENTER_NE4BEG3_12", + "CFG_CENTER_IMUX21_0", + "CFG_CENTER_NW4END1_6", + "CFG_CENTER_SE2A2_0", + "CFG_CENTER_ER1BEG3_7", + "CFG_CENTER_IMUX16_12", + "CFG_CENTER_NW4A0_16", + "CFG_CENTER_NW4END0_6", + "CFG_CENTER_WW4END3_1", + "CFG_CENTER_IMUX8_17", + "CFG_CENTER_SE4BEG2_19", + "CFG_CENTER_LOGIC_OUTS_B3_1", + "CFG_CENTER_BYP6_16", + "CFG_CENTER_BYP1_17", + "CFG_CENTER_BYP2_12", + "CFG_CENTER_LH1_9", + "CFG_CENTER_WW4C0_9", + "CFG_CENTER_LOGIC_OUTS_B16_12", + "CFG_CENTER_ER1BEG3_11", + "CFG_CENTER_LOGIC_OUTS_B12_17", + "CFG_CENTER_IMUX16_19", + "CFG_CENTER_NE4C3_9", + "CFG_CENTER_WW4END2_1", + "CFG_CENTER_IMUX31_4", + "CFG_CENTER_NW2A1_4", + "CFG_CENTER_EL1BEG0_6", + "CFG_CENTER_FAN0_4", + "CFG_CENTER_IMUX4_7", + "CFG_CENTER_SW2A0_7", + "CFG_CENTER_EE4BEG3_15", + "CFG_CENTER_NW4A0_6", + "CFG_CENTER_EE4A1_15", + "CFG_CENTER_IMUX21_4", + "CFG_CENTER_NW4A1_0", + "CFG_CENTER_ER1BEG2_17", + "CFG_CENTER_IMUX34_15", + "CFG_CENTER_WL1END3_5", + "CFG_CENTER_SE4C2_6", + "CFG_CENTER_SW4END3_3", + "CFG_CENTER_FAN2_6", + "CFG_CENTER_IMUX4_1", + "CFG_CENTER_BYP4_13", + "CFG_CENTER_BYP1_15", + "CFG_CENTER_BYP5_12", + "CFG_CENTER_LOGIC_OUTS_B15_4", + "CFG_CENTER_NW4END2_3", + "CFG_CENTER_EE4BEG3_14", + "CFG_CENTER_EE4A3_11", + "CFG_CENTER_IMUX29_5", + "CFG_CENTER_IMUX25_0", + "CFG_CENTER_IMUX33_12", + "CFG_CENTER_WW2END0_8", + "CFG_CENTER_SE2A1_14", + "CFG_CENTER_LH6_19", + "CFG_CENTER_LOGIC_OUTS_B5_4", + "CFG_CENTER_WL1END1_4", + "CFG_CENTER_LH2_6", + "CFG_CENTER_NW4A2_1", + "CFG_CENTER_BLOCK_OUTS_B0_17", + "CFG_CENTER_IMUX4_15", + "CFG_CENTER_IMUX32_10", + "CFG_CENTER_SW4END3_11", + "CFG_CENTER_WL1END2_2", + "CFG_CENTER_WW2END0_12", + "CFG_CENTER_WW4C3_8", + "CFG_CENTER_IMUX7_7", + "CFG_CENTER_IMUX27_0", + "CFG_CENTER_NW4A0_7", + "CFG_CENTER_IMUX40_8", + "CFG_CENTER_SE4BEG0_17", + "CFG_CENTER_EE4A2_6", + "CFG_CENTER_EE4BEG3_0", + "CFG_CENTER_SE4BEG3_0", + "CFG_CENTER_ER1BEG2_12", + "CFG_CENTER_IMUX7_11", + "CFG_CENTER_NE4BEG2_18", + "CFG_CENTER_NE4BEG0_14", + "CFG_CENTER_NW4A0_15", + "CFG_CENTER_LOGIC_OUTS_B10_6", + "CFG_CENTER_IMUX0_18", + "CFG_CENTER_SE4BEG0_18", + "CFG_CENTER_SE4C1_8", + "CFG_CENTER_EE2BEG3_12", + "CFG_CENTER_NW2A2_13", + "CFG_CENTER_BLOCK_OUTS_B2_5", + "CFG_CENTER_WW4C3_11", + "CFG_CENTER_LH3_19", + "CFG_CENTER_EE4A2_15", + "CFG_CENTER_NE4C2_14", + "CFG_CENTER_LOGIC_OUTS_B19_3", + "CFG_CENTER_EE4A0_5", + "CFG_CENTER_LOGIC_OUTS_B7_4", + "CFG_CENTER_IMUX6_11", + "CFG_CENTER_SW4A3_5", + "CFG_CENTER_EE2A1_7", + "CFG_CENTER_NE4BEG1_4", + "CFG_CENTER_LOGIC_OUTS_B11_8", + "CFG_CENTER_IMUX3_14", + "CFG_CENTER_LOGIC_OUTS_B22_5", + "CFG_CENTER_WW2END0_15", + "CFG_CENTER_SW2A1_3", + "CFG_CENTER_SE4BEG1_9", + "CFG_CENTER_WW4B0_18", + "CFG_CENTER_EE2BEG1_6", + "CFG_CENTER_LOGIC_OUTS_B17_13", + "CFG_CENTER_WW4C2_5", + "CFG_CENTER_NE2A3_7", + "CFG_CENTER_WW4C1_10", + "CFG_CENTER_WW2END2_2", + "CFG_CENTER_SW2A2_13", + "CFG_CENTER_IMUX33_14", + "CFG_CENTER_WR1END1_14", + "CFG_CENTER_NE2A0_3", + "CFG_CENTER_EE2A3_8", + "CFG_CENTER_LH8_11", + "CFG_CENTER_SW4END1_18", + "CFG_CENTER_LOGIC_OUTS_B10_4", + "CFG_CENTER_WW4END2_3", + "CFG_CENTER_ER1BEG2_0", + "CFG_CENTER_IMUX27_4", + "CFG_CENTER_EE4B1_16", + "CFG_CENTER_WW4END3_15", + "CFG_CENTER_EE2BEG0_5", + "CFG_CENTER_NW2A1_17", + "CFG_CENTER_EE4B1_0", + "CFG_CENTER_CTRL1_18", + "CFG_CENTER_NW4END0_19", + "CFG_CENTER_CTRL1_7", + "CFG_CENTER_IMUX0_1", + "CFG_CENTER_LH3_1", + "CFG_CENTER_IMUX3_15", + "CFG_CENTER_SW4A3_14", + "CFG_CENTER_NW4A3_2", + "CFG_CENTER_LOGIC_OUTS_B1_13", + "CFG_CENTER_EE4BEG2_15", + "CFG_CENTER_NW2A0_1", + "CFG_CENTER_EE4B0_0", + "CFG_CENTER_ER1BEG3_8", + "CFG_CENTER_EE4B1_4", + "CFG_CENTER_EE4A2_5", + "CFG_CENTER_LH3_11", + "CFG_CENTER_FAN4_19", + "CFG_CENTER_IMUX1_10", + "CFG_CENTER_SE2A1_5", + "CFG_CENTER_EE4B1_1", + "CFG_CENTER_LOGIC_OUTS_B18_16", + "CFG_CENTER_WW4B2_10", + "CFG_CENTER_NE4BEG2_15", + "CFG_CENTER_LOGIC_OUTS_B6_12", + "CFG_CENTER_EE4B2_19", + "CFG_CENTER_WW4A1_3", + "CFG_CENTER_NE2A1_3", + "CFG_CENTER_NE4BEG0_16", + "CFG_CENTER_WW4B3_9", + "CFG_CENTER_IMUX16_3", + "CFG_CENTER_SE4C3_1", + "CFG_CENTER_CLK1_8", + "CFG_CENTER_IMUX45_14", + "CFG_CENTER_LOGIC_OUTS_B7_13", + "CFG_CENTER_IMUX41_18", + "CFG_CENTER_LOGIC_OUTS_B14_17", + "CFG_CENTER_IMUX31_19", + "CFG_CENTER_LH9_7", + "CFG_CENTER_WR1END1_19", + "CFG_CENTER_EE4C2_1", + "CFG_CENTER_IMUX1_1", + "CFG_CENTER_CTRL1_15", + "CFG_CENTER_NW2A3_18", + "CFG_CENTER_CTRL1_3", + "CFG_CENTER_SE2A2_3", + "CFG_CENTER_SW2A2_5", + "CFG_CENTER_IMUX34_8", + "CFG_CENTER_SE4BEG1_15", + "CFG_CENTER_EL1BEG1_12", + "CFG_CENTER_LOGIC_OUTS_B21_18", + "CFG_CENTER_EE2BEG1_11", + "CFG_CENTER_BYP4_19", + "CFG_CENTER_LOGIC_OUTS_B0_17", + "CFG_CENTER_IMUX35_6", + "CFG_CENTER_IMUX37_10", + "CFG_CENTER_LOGIC_OUTS_B21_13", + "CFG_CENTER_BYP6_10", + "CFG_CENTER_WW4END2_17", + "CFG_CENTER_IMUX20_12", + "CFG_CENTER_IMUX20_10", + "CFG_CENTER_LH12_3", + "CFG_CENTER_IMUX30_18", + "CFG_CENTER_LOGIC_OUTS_B11_4", + "CFG_CENTER_IMUX18_5", + "CFG_CENTER_LOGIC_OUTS_B5_0", + "CFG_CENTER_CLK0_14", + "CFG_CENTER_EE4C1_2", + "CFG_CENTER_IMUX11_6", + "CFG_CENTER_SE4C3_10", + "CFG_CENTER_SE4C2_9", + "CFG_CENTER_WL1END1_15", + "CFG_CENTER_WW4C3_9", + "CFG_CENTER_BLOCK_OUTS_B1_14", + "CFG_CENTER_SW4END0_0", + "CFG_CENTER_IMUX7_13", + "CFG_CENTER_IMUX19_9", + "CFG_CENTER_NE4C3_18", + "CFG_CENTER_LOGIC_OUTS_B11_2", + "CFG_CENTER_LOGIC_OUTS_B15_6", + "CFG_CENTER_CTRL0_0", + "CFG_CENTER_BYP4_8", + "CFG_CENTER_NW2A0_13", + "CFG_CENTER_LOGIC_OUTS_B2_2", + "CFG_CENTER_IMUX11_5", + "CFG_CENTER_EE2BEG2_15", + "CFG_CENTER_NW4END1_5", + "CFG_CENTER_WW4B0_6", + "CFG_CENTER_EE4B1_15", + "CFG_CENTER_WR1END0_4", + "CFG_CENTER_LOGIC_OUTS_B14_0", + "CFG_CENTER_LH8_7", + "CFG_CENTER_SE4C1_4", + "CFG_CENTER_EL1BEG0_12", + "CFG_CENTER_LH2_16", + "CFG_CENTER_BYP2_13", + "CFG_CENTER_SW2A0_9", + "CFG_CENTER_NE4BEG1_18", + "CFG_CENTER_LOGIC_OUTS_B20_14", + "CFG_CENTER_IMUX46_6", + "CFG_CENTER_EE4BEG3_16", + "CFG_CENTER_WR1END0_15", + "CFG_CENTER_SE4C2_12", + "CFG_CENTER_WW2END0_3", + "CFG_CENTER_IMUX41_19", + "CFG_CENTER_WW4C3_6", + "CFG_CENTER_LOGIC_OUTS_B13_9", + "CFG_CENTER_IMUX2_8", + "CFG_CENTER_WW2A1_9", + "CFG_CENTER_WW4C2_13", + "CFG_CENTER_SE2A3_2", + "CFG_CENTER_BYP7_7", + "CFG_CENTER_SE2A0_16", + "CFG_CENTER_IMUX2_15", + "CFG_CENTER_LOGIC_OUTS_B11_16", + "CFG_CENTER_IMUX5_6", + "CFG_CENTER_IMUX32_15", + "CFG_CENTER_LH5_5", + "CFG_CENTER_ER1BEG1_15", + "CFG_CENTER_LOGIC_OUTS_B8_10", + "CFG_CENTER_FAN7_10", + "CFG_CENTER_NE4C3_7", + "CFG_CENTER_IMUX47_6", + "CFG_CENTER_SW4END1_0", + "CFG_CENTER_IMUX21_3", + "CFG_CENTER_BYP1_14", + "CFG_CENTER_EL1BEG3_3", + "CFG_CENTER_SE4BEG0_7", + "CFG_CENTER_SE4BEG2_14", + "CFG_CENTER_CLK0_4", + "CFG_CENTER_LH11_12", + "CFG_CENTER_WW4END2_13", + "CFG_CENTER_NW4A3_13", + "CFG_CENTER_IMUX27_9", + "CFG_CENTER_SW4A1_18", + "CFG_CENTER_EL1BEG0_0", + "CFG_CENTER_EE2BEG0_7", + "CFG_CENTER_LOGIC_OUTS_B8_0", + "CFG_CENTER_LOGIC_OUTS_B11_11", + "CFG_CENTER_EE4B0_2", + "CFG_CENTER_FAN5_3", + "CFG_CENTER_WL1END3_18", + "CFG_CENTER_LH12_9", + "CFG_CENTER_LH6_17", + "CFG_CENTER_EE4BEG0_13", + "CFG_CENTER_IMUX43_16", + "CFG_CENTER_EE4C2_11", + "CFG_CENTER_IMUX17_16", + "CFG_CENTER_NE4BEG0_3", + "CFG_CENTER_SE4C2_1", + "CFG_CENTER_SW2A2_14", + "CFG_CENTER_IMUX28_17", + "CFG_CENTER_EL1BEG0_2", + "CFG_CENTER_CTRL1_0", + "CFG_CENTER_FAN7_9", + "CFG_CENTER_LOGIC_OUTS_B19_4", + "CFG_CENTER_BLOCK_OUTS_B3_15", + "CFG_CENTER_NW4A0_0", + "CFG_CENTER_WW4B3_16", + "CFG_CENTER_IMUX6_1", + "CFG_CENTER_WW4C2_18", + "CFG_CENTER_IMUX39_4", + "CFG_CENTER_EE2BEG1_3", + "CFG_CENTER_EE4B3_19", + "CFG_CENTER_WW4END2_0", + "CFG_CENTER_SE2A3_10", + "CFG_CENTER_EE2A2_19", + "CFG_CENTER_IMUX26_10", + "CFG_CENTER_WW4END2_14", + "CFG_CENTER_NE2A3_6", + "CFG_CENTER_ER1BEG1_12", + "CFG_CENTER_CLK1_10", + "CFG_CENTER_WW4END0_14", + "CFG_CENTER_BLOCK_OUTS_B0_1", + "CFG_CENTER_SW4A1_16", + "CFG_CENTER_IMUX29_8", + "CFG_CENTER_IMUX37_13", + "CFG_CENTER_SW4END0_2", + "CFG_CENTER_IMUX40_10", + "CFG_CENTER_LH5_14", + "CFG_CENTER_LOGIC_OUTS_B10_9", + "CFG_CENTER_FAN1_9", + "CFG_CENTER_NW4A0_17", + "CFG_CENTER_WW4A2_11", + "CFG_CENTER_EE2A3_13", + "CFG_CENTER_LH3_8", + "CFG_CENTER_EL1BEG1_18", + "CFG_CENTER_NW4END0_5", + "CFG_CENTER_LOGIC_OUTS_B19_16", + "CFG_CENTER_SE4C1_1", + "CFG_CENTER_EL1BEG0_4", + "CFG_CENTER_EE2BEG1_18", + "CFG_CENTER_IMUX3_19", + "CFG_CENTER_LH10_14", + "CFG_CENTER_IMUX44_5", + "CFG_CENTER_WW4C1_16", + "CFG_CENTER_IMUX21_11", + "CFG_CENTER_IMUX35_15", + "CFG_CENTER_NE4C2_4", + "CFG_CENTER_BLOCK_OUTS_B0_0", + "CFG_CENTER_ER1BEG1_13", + "CFG_CENTER_SW4END2_7", + "CFG_CENTER_IMUX8_6", + "CFG_CENTER_WW4B3_17", + "CFG_CENTER_NW4A2_16", + "CFG_CENTER_ER1BEG2_7", + "CFG_CENTER_WW4A1_2", + "CFG_CENTER_LOGIC_OUTS_B4_12", + "CFG_CENTER_WW2A2_6", + "CFG_CENTER_IMUX5_14", + "CFG_CENTER_IMUX24_2", + "CFG_CENTER_EE4BEG3_9", + "CFG_CENTER_ER1BEG1_1", + "CFG_CENTER_BYP0_16", + "CFG_CENTER_EE4BEG0_18", + "CFG_CENTER_SW4A1_5", + "CFG_CENTER_IMUX2_11", + "CFG_CENTER_SW2A1_11", + "CFG_CENTER_ER1BEG1_2", + "CFG_CENTER_WR1END0_12", + "CFG_CENTER_IMUX10_16", + "CFG_CENTER_EL1BEG2_9", + "CFG_CENTER_NE4C3_3", + "CFG_CENTER_WR1END2_15", + "CFG_CENTER_IMUX31_6", + "CFG_CENTER_EE2BEG0_14", + "CFG_CENTER_BYP2_6", + "CFG_CENTER_SE4C1_0", + "CFG_CENTER_WW4B3_0", + "CFG_CENTER_FAN6_14", + "CFG_CENTER_CLK0_18", + "CFG_CENTER_FAN4_2", + "CFG_CENTER_WW4END1_16", + "CFG_CENTER_WW4END2_12", + "CFG_CENTER_WW4A3_15", + "CFG_CENTER_NW4A0_1", + "CFG_CENTER_SE2A3_17", + "CFG_CENTER_FAN0_2", + "CFG_CENTER_BYP5_13", + "CFG_CENTER_SE2A1_11", + "CFG_CENTER_LH7_1", + "CFG_CENTER_SE4BEG1_12", + "CFG_CENTER_BLOCK_OUTS_B2_19", + "CFG_CENTER_EE2BEG3_11", + "CFG_CENTER_WW4A1_19", + "CFG_CENTER_WW2END1_14", + "CFG_CENTER_BYP0_8", + "CFG_CENTER_WW2END1_17", + "CFG_CENTER_LH1_8", + "CFG_CENTER_LOGIC_OUTS_B21_12", + "CFG_CENTER_SW2A0_17", + "CFG_CENTER_BYP7_14", + "CFG_CENTER_WW2A3_19", + "CFG_CENTER_SE4BEG0_3", + "CFG_CENTER_IMUX22_11", + "CFG_CENTER_NW4A3_12", + "CFG_CENTER_SE4C1_10", + "CFG_CENTER_IMUX28_11", + "CFG_CENTER_EE2A3_3", + "CFG_CENTER_FAN7_13", + "CFG_CENTER_WW4B2_16", + "CFG_CENTER_SW4A0_16", + "CFG_CENTER_EE4C0_8", + "CFG_CENTER_ER1BEG1_3", + "CFG_CENTER_LH12_1", + "CFG_CENTER_WW4END0_5", + "CFG_CENTER_IMUX26_15", + "CFG_CENTER_EE4BEG2_6", + "CFG_CENTER_NW2A1_5", + "CFG_CENTER_LH3_14", + "CFG_CENTER_FAN6_16", + "CFG_CENTER_SE4BEG0_4", + "CFG_CENTER_LOGIC_OUTS_B5_3", + "CFG_CENTER_IMUX11_14", + "CFG_CENTER_WW2END3_8", + "CFG_CENTER_SW2A1_15", + "CFG_CENTER_WR1END3_17", + "CFG_CENTER_WW4END3_8", + "CFG_CENTER_SW4A2_4", + "CFG_CENTER_LOGIC_OUTS_B0_5", + "CFG_CENTER_IMUX31_15", + "CFG_CENTER_EE4A0_8", + "CFG_CENTER_IMUX15_9", + "CFG_CENTER_WW4B3_4", + "CFG_CENTER_NE4C1_3", + "CFG_CENTER_NW2A3_8", + "CFG_CENTER_LH5_17", + "CFG_CENTER_SE4C1_17", + "CFG_CENTER_IMUX47_0", + "CFG_CENTER_WL1END2_3", + "CFG_CENTER_LOGIC_OUTS_B12_3", + "CFG_CENTER_WW4B3_19", + "CFG_CENTER_LOGIC_OUTS_B2_16", + "CFG_CENTER_EE2BEG0_4", + "CFG_CENTER_BLOCK_OUTS_B3_18", + "CFG_CENTER_IMUX34_14", + "CFG_CENTER_LH7_5", + "CFG_CENTER_IMUX34_2", + "CFG_CENTER_SE4BEG3_13", + "CFG_CENTER_LH4_7", + "CFG_CENTER_IMUX2_18", + "CFG_CENTER_IMUX44_12", + "CFG_CENTER_ER1BEG3_17", + "CFG_CENTER_EE4B1_18", + "CFG_CENTER_BYP7_16", + "CFG_CENTER_WL1END3_19", + "CFG_CENTER_LH9_17", + "CFG_CENTER_WW4B3_13", + "CFG_CENTER_NE4C2_16", + "CFG_CENTER_EE4A1_4", + "CFG_CENTER_EE2A0_1", + "CFG_CENTER_BYP1_2", + "CFG_CENTER_IMUX37_12", + "CFG_CENTER_CTRL0_6", + "CFG_CENTER_IMUX36_19", + "CFG_CENTER_IMUX33_7", + "CFG_CENTER_NE4C1_8", + "CFG_CENTER_LH4_17", + "CFG_CENTER_EE2A1_12", + "CFG_CENTER_WW4C3_17", + "CFG_CENTER_WW4C1_7", + "CFG_CENTER_LH3_12", + "CFG_CENTER_WW2END0_14", + "CFG_CENTER_IMUX15_14", + "CFG_CENTER_NW4A2_11", + "CFG_CENTER_WW4A3_14", + "CFG_CENTER_LOGIC_OUTS_B3_17", + "CFG_CENTER_IMUX22_10", + "CFG_CENTER_CTRL1_12", + "CFG_CENTER_WW4A3_16", + "CFG_CENTER_WW4C0_19", + "CFG_CENTER_SW2A2_3", + "CFG_CENTER_IMUX17_1", + "CFG_CENTER_IMUX18_7", + "CFG_CENTER_EE4A1_18", + "CFG_CENTER_BYP4_11", + "CFG_CENTER_LOGIC_OUTS_B6_7", + "CFG_CENTER_SE2A3_5", + "CFG_CENTER_IMUX6_4", + "CFG_CENTER_NW4END1_8", + "CFG_CENTER_IMUX27_14", + "CFG_CENTER_NW4END0_1", + "CFG_CENTER_FAN2_0", + "CFG_CENTER_WW4B0_0", + "CFG_CENTER_BYP5_0", + "CFG_CENTER_NE4C2_7", + "CFG_CENTER_WL1END0_17", + "CFG_CENTER_BYP1_18", + "CFG_CENTER_WW4A2_18", + "CFG_CENTER_IMUX12_17", + "CFG_CENTER_BYP2_5", + "CFG_CENTER_LOGIC_OUTS_B15_8", + "CFG_CENTER_WW4A1_1", + "CFG_CENTER_IMUX21_7", + "CFG_CENTER_NE4C1_16", + "CFG_CENTER_CTRL0_4", + "CFG_CENTER_EL1BEG3_6", + "CFG_CENTER_LOGIC_OUTS_B3_16", + "CFG_CENTER_BLOCK_OUTS_B1_0", + "CFG_CENTER_IMUX1_4", + "CFG_CENTER_EE2BEG1_4", + "CFG_CENTER_BYP3_10", + "CFG_CENTER_WL1END2_13", + "CFG_CENTER_ER1BEG3_9", + "CFG_CENTER_WL1END0_1", + "CFG_CENTER_FAN0_18", + "CFG_CENTER_EL1BEG3_16", + "CFG_CENTER_LH10_9", + "CFG_CENTER_EE2BEG1_16", + "CFG_CENTER_SW4A0_3", + "CFG_CENTER_EE2BEG2_13", + "CFG_CENTER_IMUX46_8", + "CFG_CENTER_EL1BEG0_17", + "CFG_CENTER_EE4BEG1_18", + "CFG_CENTER_WW2END1_19", + "CFG_CENTER_WW4C1_1", + "CFG_CENTER_SE2A3_0", + "CFG_CENTER_SW4A2_16", + "CFG_CENTER_WW2A3_17", + "CFG_CENTER_WW4A3_4", + "CFG_CENTER_IMUX21_12", + "CFG_CENTER_WW4B0_11", + "CFG_CENTER_LOGIC_OUTS_B8_3", + "CFG_CENTER_IMUX12_10", + "CFG_CENTER_LOGIC_OUTS_B7_19", + "CFG_CENTER_IMUX6_3", + "CFG_CENTER_NW2A3_3", + "CFG_CENTER_WR1END0_3", + "CFG_CENTER_LOGIC_OUTS_B23_13", + "CFG_CENTER_EE2BEG2_10", + "CFG_CENTER_SW4A0_7", + "CFG_CENTER_WW4END1_6", + "CFG_CENTER_EE4C1_9", + "CFG_CENTER_LOGIC_OUTS_B3_13", + "CFG_CENTER_SW4END3_12", + "CFG_CENTER_LH3_9", + "CFG_CENTER_IMUX29_19", + "CFG_CENTER_BYP1_19", + "CFG_CENTER_IMUX18_17", + "CFG_CENTER_WW4B1_4", + "CFG_CENTER_BYP2_16", + "CFG_CENTER_NW4END2_13", + "CFG_CENTER_LH3_17", + "CFG_CENTER_IMUX13_10", + "CFG_CENTER_BOT_USR_ACCESS_DATA6", + "CFG_CENTER_LOGIC_OUTS_B0_2", + "CFG_CENTER_EE4B1_14", + "CFG_CENTER_IMUX33_5", + "CFG_CENTER_IMUX44_16", + "CFG_CENTER_IMUX24_15", + "CFG_CENTER_EE4A2_14", + "CFG_CENTER_NE4BEG0_17", + "CFG_CENTER_LH4_11", + "CFG_CENTER_EE4C2_9", + "CFG_CENTER_SW4A3_18", + "CFG_CENTER_SW4A3_13", + "CFG_CENTER_WR1END3_6", + "CFG_CENTER_WR1END3_8", + "CFG_CENTER_IMUX22_8", + "CFG_CENTER_NE2A0_0", + "CFG_CENTER_LOGIC_OUTS_B11_1", + "CFG_CENTER_LOGIC_OUTS_B15_13", + "CFG_CENTER_BYP4_1", + "CFG_CENTER_IMUX31_0", + "CFG_CENTER_BYP6_8", + "CFG_CENTER_SE2A0_8", + "CFG_CENTER_NW4END0_3", + "CFG_CENTER_LOGIC_OUTS_B6_14", + "CFG_CENTER_EE4BEG0_16", + "CFG_CENTER_LOGIC_OUTS_B2_3", + "CFG_CENTER_LOGIC_OUTS_B19_9", + "CFG_CENTER_IMUX13_9", + "CFG_CENTER_FAN1_18", + "CFG_CENTER_LOGIC_OUTS_B9_6", + "CFG_CENTER_EE2BEG3_17", + "CFG_CENTER_NW4A2_5", + "CFG_CENTER_LH9_0", + "CFG_CENTER_WL1END1_7", + "CFG_CENTER_IMUX26_13", + "CFG_CENTER_WW4C0_12", + "CFG_CENTER_WW4END3_3", + "CFG_CENTER_SW4END1_12", + "CFG_CENTER_EE4BEG2_5", + "CFG_CENTER_BYP0_12", + "CFG_CENTER_BYP5_1", + "CFG_CENTER_NE4BEG3_8", + "CFG_CENTER_IMUX26_2", + "CFG_CENTER_IMUX12_6", + "CFG_CENTER_BLOCK_OUTS_B3_13", + "CFG_CENTER_NE4BEG0_10", + "CFG_CENTER_LH2_3", + "CFG_CENTER_EE2BEG3_15", + "CFG_CENTER_NW4A2_2", + "CFG_CENTER_WW2END1_3", + "CFG_CENTER_FAN6_5", + "CFG_CENTER_WW2END1_11", + "CFG_CENTER_SE4C3_12", + "CFG_CENTER_EE2A3_14", + "CFG_CENTER_SW2A3_4", + "CFG_CENTER_FAN0_3", + "CFG_CENTER_IMUX37_2", + "CFG_CENTER_IMUX7_5", + "CFG_CENTER_EE4B3_9", + "CFG_CENTER_IMUX1_3", + "CFG_CENTER_IMUX26_9", + "CFG_CENTER_FAN0_10", + "CFG_CENTER_IMUX37_7", + "CFG_CENTER_NE4BEG0_19", + "CFG_CENTER_NE4BEG3_2", + "CFG_CENTER_FAN1_5", + "CFG_CENTER_LH3_6", + "CFG_CENTER_EE2A2_1", + "CFG_CENTER_NW4A0_13", + "CFG_CENTER_IMUX4_9", + "CFG_CENTER_ER1BEG0_5", + "CFG_CENTER_EE4B2_1", + "CFG_CENTER_EE4C1_6", + "CFG_CENTER_SE4BEG1_16", + "CFG_CENTER_IMUX26_16", + "CFG_CENTER_BYP2_19", + "CFG_CENTER_BYP5_18", + "CFG_CENTER_NW4END0_14", + "CFG_CENTER_EE2A2_0", + "CFG_CENTER_LOGIC_OUTS_B17_15", + "CFG_CENTER_SW4END1_2", + "CFG_CENTER_EE4C1_18", + "CFG_CENTER_LH6_14", + "CFG_CENTER_IMUX15_19", + "CFG_CENTER_LOGIC_OUTS_B13_15", + "CFG_CENTER_WR1END3_10", + "CFG_CENTER_EE2A1_6", + "CFG_CENTER_EE2BEG2_14", + "CFG_CENTER_EE4A3_4", + "CFG_CENTER_NE4BEG3_1", + "CFG_CENTER_EE4B0_16", + "CFG_CENTER_IMUX38_4", + "CFG_CENTER_IMUX39_11", + "CFG_CENTER_FAN7_3", + "CFG_CENTER_LOGIC_OUTS_B4_5", + "CFG_CENTER_IMUX47_9", + "CFG_CENTER_EE2A2_11", + "CFG_CENTER_LOGIC_OUTS_B4_15", + "CFG_CENTER_NW4END1_10", + "CFG_CENTER_EE2A3_11", + "CFG_CENTER_CLK0_13", + "CFG_CENTER_NW4END0_12", + "CFG_CENTER_LH8_14", + "CFG_CENTER_EE4BEG1_1", + "CFG_CENTER_ER1BEG1_7", + "CFG_CENTER_EL1BEG2_19", + "CFG_CENTER_WW4END0_2", + "CFG_CENTER_EE4C1_8", + "CFG_CENTER_LOGIC_OUTS_B22_15", + "CFG_CENTER_BYP3_4", + "CFG_CENTER_WW2A2_10", + "CFG_CENTER_LOGIC_OUTS_B3_0", + "CFG_CENTER_LOGIC_OUTS_B23_17", + "CFG_CENTER_IMUX16_13", + "CFG_CENTER_SW4A2_10", + "CFG_CENTER_IMUX1_17", + "CFG_CENTER_LOGIC_OUTS_B7_14", + "CFG_CENTER_FAN0_6", + "CFG_CENTER_EE4A0_18", + "CFG_CENTER_IMUX3_18", + "CFG_CENTER_IMUX7_9", + "CFG_CENTER_IMUX0_11", + "CFG_CENTER_IMUX33_4", + "CFG_CENTER_IMUX34_16", + "CFG_CENTER_IMUX20_9", + "CFG_CENTER_SW2A1_6", + "CFG_CENTER_LOGIC_OUTS_B11_3", + "CFG_CENTER_IMUX0_17", + "CFG_CENTER_IMUX34_11", + "CFG_CENTER_EE2A3_0", + "CFG_CENTER_LH5_6", + "CFG_CENTER_FAN7_18", + "CFG_CENTER_SW4END3_10", + "CFG_CENTER_NE4C3_2", + "CFG_CENTER_WW2A2_13", + "CFG_CENTER_NW4A3_9", + "CFG_CENTER_NE2A0_8", + "CFG_CENTER_EE4B2_17", + "CFG_CENTER_EE4B1_2", + "CFG_CENTER_LH1_18", + "CFG_CENTER_BYP3_2", + "CFG_CENTER_SE4BEG3_6", + "CFG_CENTER_FAN5_0", + "CFG_CENTER_LOGIC_OUTS_B23_7", + "CFG_CENTER_BYP2_4", + "CFG_CENTER_BLOCK_OUTS_B2_4", + "CFG_CENTER_WW2END2_11", + "CFG_CENTER_NW2A1_11", + "CFG_CENTER_IMUX10_2", + "CFG_CENTER_CTRL0_7", + "CFG_CENTER_IMUX33_11", + "CFG_CENTER_FAN3_8", + "CFG_CENTER_WW4C3_2", + "CFG_CENTER_EL1BEG2_12", + "CFG_CENTER_LOGIC_OUTS_B11_12", + "CFG_CENTER_EE4BEG3_11", + "CFG_CENTER_EE4A2_10", + "CFG_CENTER_IMUX25_1", + "CFG_CENTER_IMUX5_15", + "CFG_CENTER_BLOCK_OUTS_B2_18", + "CFG_CENTER_EE4A2_3", + "CFG_CENTER_EE4BEG2_14", + "CFG_CENTER_IMUX9_15", + "CFG_CENTER_WW2A2_18", + "CFG_CENTER_NW4END0_11", + "CFG_CENTER_NW4A2_14", + "CFG_CENTER_EE2A0_0", + "CFG_CENTER_WW2A3_14", + "CFG_CENTER_IMUX18_16", + "CFG_CENTER_LH2_17", + "CFG_CENTER_IMUX29_11", + "CFG_CENTER_ER1BEG0_18", + "CFG_CENTER_EE2A0_10", + "CFG_CENTER_EE4C3_10", + "CFG_CENTER_ER1BEG0_16", + "CFG_CENTER_LH5_10", + "CFG_CENTER_EE2A1_11", + "CFG_CENTER_IMUX47_16", + "CFG_CENTER_SE4C3_0", + "CFG_CENTER_BOT_USR_ACCESS_DATA13", + "CFG_CENTER_LH2_14", + "CFG_CENTER_NW2A2_6", + "CFG_CENTER_IMUX1_8", + "CFG_CENTER_IMUX31_2", + "CFG_CENTER_NE4BEG1_7", + "CFG_CENTER_EE4A1_16", + "CFG_CENTER_BYP4_9", + "CFG_CENTER_LOGIC_OUTS_B15_10", + "CFG_CENTER_BYP0_11", + "CFG_CENTER_IMUX5_19", + "CFG_CENTER_EE2BEG1_19", + "CFG_CENTER_SE4BEG2_9", + "CFG_CENTER_LOGIC_OUTS_B2_11", + "CFG_CENTER_NW4END3_14", + "CFG_CENTER_SW2A2_8", + "CFG_CENTER_EE2BEG3_5", + "CFG_CENTER_EE4A0_3", + "CFG_CENTER_LH1_0", + "CFG_CENTER_LOGIC_OUTS_B23_19", + "CFG_CENTER_ER1BEG2_19", + "CFG_CENTER_IMUX36_17", + "CFG_CENTER_BLOCK_OUTS_B3_2", + "CFG_CENTER_LOGIC_OUTS_B18_2", + "CFG_CENTER_IMUX8_18", + "CFG_CENTER_EE2BEG3_19", + "CFG_CENTER_IMUX40_19", + "CFG_CENTER_SW4END0_9", + "CFG_CENTER_EE2BEG3_7", + "CFG_CENTER_EL1BEG1_19", + "CFG_CENTER_WW2A2_19", + "CFG_CENTER_WW4C1_17", + "CFG_CENTER_LOGIC_OUTS_B10_18", + "CFG_CENTER_EE4C0_16", + "CFG_CENTER_NE4BEG1_19", + "CFG_CENTER_IMUX34_17", + "CFG_CENTER_LOGIC_OUTS_B2_5", + "CFG_CENTER_NW4END0_16", + "CFG_CENTER_EE4BEG1_16", + "CFG_CENTER_IMUX10_18", + "CFG_CENTER_LOGIC_OUTS_B8_1", + "CFG_CENTER_LOGIC_OUTS_B14_19", + "CFG_CENTER_NE4BEG2_12", + "CFG_CENTER_EE4B2_3", + "CFG_CENTER_IMUX5_11", + "CFG_CENTER_LH3_16", + "CFG_CENTER_LH3_0", + "CFG_CENTER_IMUX29_17", + "CFG_CENTER_LOGIC_OUTS_B16_16", + "CFG_CENTER_IMUX0_10", + "CFG_CENTER_EL1BEG2_14", + "CFG_CENTER_CTRL1_13", + "CFG_CENTER_IMUX29_13", + "CFG_CENTER_IMUX8_9", + "CFG_CENTER_IMUX23_2", + "CFG_CENTER_LOGIC_OUTS_B6_11", + "CFG_CENTER_WW4END1_1", + "CFG_CENTER_LOGIC_OUTS_B5_10", + "CFG_CENTER_IMUX42_13", + "CFG_CENTER_LH10_15", + "CFG_CENTER_NW2A0_19", + "CFG_CENTER_IMUX4_10", + "CFG_CENTER_LH6_1", + "CFG_CENTER_WW4B0_15", + "CFG_CENTER_LH6_3", + "CFG_CENTER_LOGIC_OUTS_B19_15", + "CFG_CENTER_LOGIC_OUTS_B2_9", + "CFG_CENTER_SE2A0_4", + "CFG_CENTER_SW4END3_4", + "CFG_CENTER_ER1BEG0_4", + "CFG_CENTER_IMUX18_18", + "CFG_CENTER_WR1END2_14", + "CFG_CENTER_EE4C2_16", + "CFG_CENTER_BYP4_10", + "CFG_CENTER_IMUX30_2", + "CFG_CENTER_IMUX43_4", + "CFG_CENTER_LOGIC_OUTS_B10_2", + "CFG_CENTER_IMUX5_1", + "CFG_CENTER_BYP6_17", + "CFG_CENTER_EE4A2_8", + "CFG_CENTER_NE4C3_8", + "CFG_CENTER_IMUX23_9", + "CFG_CENTER_EE4BEG3_12", + "CFG_CENTER_LH10_8", + "CFG_CENTER_LOGIC_OUTS_B2_7", + "CFG_CENTER_IMUX44_19", + "CFG_CENTER_WW4B1_2", + "CFG_CENTER_IMUX31_16", + "CFG_CENTER_IMUX2_7", + "CFG_CENTER_IMUX16_14", + "CFG_CENTER_IMUX10_14", + "CFG_CENTER_EE4C3_4", + "CFG_CENTER_FAN7_6", + "CFG_CENTER_SW4END0_10", + "CFG_CENTER_EE4A3_2", + "CFG_CENTER_WR1END1_17", + "CFG_CENTER_NE2A2_5", + "CFG_CENTER_WW2A3_5", + "CFG_CENTER_IMUX27_18", + "CFG_CENTER_IMUX18_15", + "CFG_CENTER_NW4A2_18", + "CFG_CENTER_LOGIC_OUTS_B15_15", + "CFG_CENTER_IMUX14_17", + "CFG_CENTER_FAN0_17", + "CFG_CENTER_LOGIC_OUTS_B6_10", + "CFG_CENTER_IMUX15_8", + "CFG_CENTER_BOT_USR_ACCESS_DATA11", + "CFG_CENTER_IMUX9_11", + "CFG_CENTER_WW4A0_12", + "CFG_CENTER_IMUX40_14", + "CFG_CENTER_IMUX30_5", + "CFG_CENTER_WW2A2_16", + "CFG_CENTER_WW4C0_5", + "CFG_CENTER_IMUX20_11", + "CFG_CENTER_ER1BEG0_19", + "CFG_CENTER_SE4BEG2_1", + "CFG_CENTER_LOGIC_OUTS_B9_10", + "CFG_CENTER_EL1BEG1_3", + "CFG_CENTER_WR1END1_0", + "CFG_CENTER_WW4B1_14", + "CFG_CENTER_WW4A0_14", + "CFG_CENTER_LOGIC_OUTS_B19_10", + "CFG_CENTER_FAN3_12", + "CFG_CENTER_IMUX41_0", + "CFG_CENTER_IMUX4_19", + "CFG_CENTER_NW2A2_17", + "CFG_CENTER_BLOCK_OUTS_B2_6", + "CFG_CENTER_SW2A1_8", + "CFG_CENTER_SW4A0_9", + "CFG_CENTER_LOGIC_OUTS_B21_9", + "CFG_CENTER_SE4BEG1_17", + "CFG_CENTER_IMUX40_6", + "CFG_CENTER_IMUX10_12", + "CFG_CENTER_CTRL0_19", + "CFG_CENTER_IMUX6_13", + "CFG_CENTER_SE4BEG2_15", + "CFG_CENTER_SE4C1_5", + "CFG_CENTER_LOGIC_OUTS_B0_0", + "CFG_CENTER_NW2A3_13", + "CFG_CENTER_FAN3_17", + "CFG_CENTER_WL1END2_11", + "CFG_CENTER_CLK0_19", + "CFG_CENTER_LH5_7", + "CFG_CENTER_WW4C1_14", + "CFG_CENTER_IMUX22_19", + "CFG_CENTER_IMUX14_0", + "CFG_CENTER_EE2BEG3_1", + "CFG_CENTER_SE2A3_16", + "CFG_CENTER_WL1END2_1", + "CFG_CENTER_IMUX40_4", + "CFG_CENTER_IMUX1_18", + "CFG_CENTER_IMUX42_9", + "CFG_CENTER_NW4A1_12", + "CFG_CENTER_NW4END3_5", + "CFG_CENTER_LOGIC_OUTS_B0_6", + "CFG_CENTER_LOGIC_OUTS_B11_5", + "CFG_CENTER_LH1_13", + "CFG_CENTER_WW4A3_6", + "CFG_CENTER_IMUX28_10", + "CFG_CENTER_BOT_USR_ACCESS_DATA7", + "CFG_CENTER_WW2A3_11", + "CFG_CENTER_LOGIC_OUTS_B21_8", + "CFG_CENTER_LOGIC_OUTS_B14_7", + "CFG_CENTER_LOGIC_OUTS_B7_5", + "CFG_CENTER_ER1BEG1_9", + "CFG_CENTER_SE2A2_1", + "CFG_CENTER_BYP5_19", + "CFG_CENTER_NW2A1_19", + "CFG_CENTER_SE4BEG2_6", + "CFG_CENTER_WW4B3_12", + "CFG_CENTER_WW4A3_19", + "CFG_CENTER_IMUX32_2", + "CFG_CENTER_LOGIC_OUTS_B17_10", + "CFG_CENTER_LOGIC_OUTS_B18_3", + "CFG_CENTER_SE4C2_7", + "CFG_CENTER_IMUX15_5", + "CFG_CENTER_CTRL1_5", + "CFG_CENTER_IMUX22_13", + "CFG_CENTER_IMUX30_19", + "CFG_CENTER_BYP2_8", + "CFG_CENTER_BYP5_11", + "CFG_CENTER_SW4A2_13", + "CFG_CENTER_IMUX35_14", + "CFG_CENTER_EE2A2_12", + "CFG_CENTER_LH4_1", + "CFG_CENTER_LOGIC_OUTS_B21_11", + "CFG_CENTER_WL1END3_10", + "CFG_CENTER_SE2A1_12", + "CFG_CENTER_LH4_3", + "CFG_CENTER_SE4BEG3_15", + "CFG_CENTER_EE4B0_8", + "CFG_CENTER_SE4C3_6", + "CFG_CENTER_EE4C3_0", + "CFG_CENTER_IMUX44_11", + "CFG_CENTER_IMUX40_11", + "CFG_CENTER_LOGIC_OUTS_B20_15", + "CFG_CENTER_WW4A1_0", + "CFG_CENTER_BLOCK_OUTS_B0_4", + "CFG_CENTER_WW4END1_11", + "CFG_CENTER_LOGIC_OUTS_B9_3", + "CFG_CENTER_BYP7_13", + "CFG_CENTER_EE4BEG3_6", + "CFG_CENTER_IMUX47_10", + "CFG_CENTER_LH10_16", + "CFG_CENTER_IMUX23_12", + "CFG_CENTER_SW4END3_16", + "CFG_CENTER_WW4END1_17", + "CFG_CENTER_SW4END2_12", + "CFG_CENTER_BYP1_4", + "CFG_CENTER_LOGIC_OUTS_B8_6", + "CFG_CENTER_SW4END3_8", + "CFG_CENTER_IMUX10_1", + "CFG_CENTER_LOGIC_OUTS_B5_12", + "CFG_CENTER_EE4C3_7", + "CFG_CENTER_LH4_13", + "CFG_CENTER_LOGIC_OUTS_B10_7", + "CFG_CENTER_SW2A3_5", + "CFG_CENTER_IMUX36_0", + "CFG_CENTER_CTRL1_8", + "CFG_CENTER_FAN2_12", + "CFG_CENTER_LOGIC_OUTS_B6_1", + "CFG_CENTER_SW4A3_4", + "CFG_CENTER_WW2A0_9", + "CFG_CENTER_BLOCK_OUTS_B3_16", + "CFG_CENTER_BYP4_3", + "CFG_CENTER_IMUX3_0", + "CFG_CENTER_LOGIC_OUTS_B15_19", + "CFG_CENTER_SE2A3_1", + "CFG_CENTER_BYP6_14", + "CFG_CENTER_EL1BEG1_9", + "CFG_CENTER_EE4A1_14", + "CFG_CENTER_LOGIC_OUTS_B3_7", + "CFG_CENTER_IMUX6_9", + "CFG_CENTER_EE4BEG2_13", + "CFG_CENTER_BYP1_13", + "CFG_CENTER_CTRL1_2", + "CFG_CENTER_IMUX33_2", + "CFG_CENTER_IMUX10_11", + "CFG_CENTER_BYP3_8", + "CFG_CENTER_LH7_0", + "CFG_CENTER_EE4A3_13", + "CFG_CENTER_FAN2_3", + "CFG_CENTER_LOGIC_OUTS_B13_7", + "CFG_CENTER_WW4C3_16", + "CFG_CENTER_SE4C1_13", + "CFG_CENTER_EE2A0_9", + "CFG_CENTER_BLOCK_OUTS_B1_8", + "CFG_CENTER_LOGIC_OUTS_B21_4", + "CFG_CENTER_IMUX3_5", + "CFG_CENTER_IMUX29_15", + "CFG_CENTER_NW4END2_18", + "CFG_CENTER_ER1BEG3_13", + "CFG_CENTER_LOGIC_OUTS_B9_17", + "CFG_CENTER_WW4C1_2", + "CFG_CENTER_SW2A3_18", + "CFG_CENTER_WR1END0_6", + "CFG_CENTER_SW2A0_6", + "CFG_CENTER_IMUX45_2", + "CFG_CENTER_IMUX14_5", + "CFG_CENTER_SW4A2_12", + "CFG_CENTER_SE4BEG1_6", + "CFG_CENTER_IMUX9_18", + "CFG_CENTER_SW4END3_0", + "CFG_CENTER_BYP6_2", + "CFG_CENTER_SW2A3_6", + "CFG_CENTER_LOGIC_OUTS_B4_19", + "CFG_CENTER_WW2A2_9", + "CFG_CENTER_SE4C3_3", + "CFG_CENTER_IMUX36_1", + "CFG_CENTER_FAN2_11", + "CFG_CENTER_LOGIC_OUTS_B13_3", + "CFG_CENTER_IMUX6_19", + "CFG_CENTER_IMUX28_18", + "CFG_CENTER_IMUX37_17", + "CFG_CENTER_NW4END2_14", + "CFG_CENTER_LOGIC_OUTS_B18_11", + "CFG_CENTER_NW4END3_4", + "CFG_CENTER_LOGIC_OUTS_B17_14", + "CFG_CENTER_LOGIC_OUTS_B0_16", + "CFG_CENTER_IMUX28_12", + "CFG_CENTER_WW4END0_8", + "CFG_CENTER_EE4BEG0_3", + "CFG_CENTER_WW4A0_7", + "CFG_CENTER_NW2A1_12", + "CFG_CENTER_LOGIC_OUTS_B2_0", + "CFG_CENTER_SW2A0_8", + "CFG_CENTER_SE2A2_5", + "CFG_CENTER_FAN5_5", + "CFG_CENTER_SW4END2_11", + "CFG_CENTER_LH9_16", + "CFG_CENTER_IMUX17_9", + "CFG_CENTER_NE4C2_3", + "CFG_CENTER_IMUX24_18", + "CFG_CENTER_IMUX32_19", + "CFG_CENTER_CLK1_15", + "CFG_CENTER_WW4B3_7", + "CFG_CENTER_IMUX37_5", + "CFG_CENTER_IMUX27_2", + "CFG_CENTER_IMUX2_16", + "CFG_CENTER_IMUX13_11", + "CFG_CENTER_LOGIC_OUTS_B17_6", + "CFG_CENTER_NW4A3_0", + "CFG_CENTER_EE4C3_11", + "CFG_CENTER_IMUX45_9", + "CFG_CENTER_IMUX17_7", + "CFG_CENTER_WL1END3_17", + "CFG_CENTER_LOGIC_OUTS_B15_16", + "CFG_CENTER_EE4BEG2_17", + "CFG_CENTER_LOGIC_OUTS_B14_9", + "CFG_CENTER_IMUX45_13", + "CFG_CENTER_IMUX5_8", + "CFG_CENTER_EE2BEG3_4", + "CFG_CENTER_IMUX18_4", + "CFG_CENTER_LOGIC_OUTS_B20_9", + "CFG_CENTER_LH12_12", + "CFG_CENTER_LOGIC_OUTS_B8_5", + "CFG_CENTER_SW2A2_0", + "CFG_CENTER_CLK1_5", + "CFG_CENTER_WW4C3_18", + "CFG_CENTER_ER1BEG3_18", + "CFG_CENTER_EE4BEG2_18", + "CFG_CENTER_EE4C3_8", + "CFG_CENTER_FAN1_6", + "CFG_CENTER_EE2BEG1_5", + "CFG_CENTER_WW4END0_10", + "CFG_CENTER_SW2A0_12", + "CFG_CENTER_EE2BEG1_10", + "CFG_CENTER_EE4B0_14", + "CFG_CENTER_EE2BEG1_0", + "CFG_CENTER_LH5_1", + "CFG_CENTER_IMUX16_8", + "CFG_CENTER_SW2A2_1", + "CFG_CENTER_IMUX32_0", + "CFG_CENTER_WR1END0_1", + "CFG_CENTER_IMUX11_3", + "CFG_CENTER_IMUX25_13", + "CFG_CENTER_IMUX25_11", + "CFG_CENTER_LOGIC_OUTS_B12_1", + "CFG_CENTER_LOGIC_OUTS_B20_11", + "CFG_CENTER_LOGIC_OUTS_B21_1", + "CFG_CENTER_WW4B1_1", + "CFG_CENTER_WW4A1_7", + "CFG_CENTER_IMUX5_5", + "CFG_CENTER_NW2A1_3", + "CFG_CENTER_NW2A0_11", + "CFG_CENTER_IMUX32_13", + "CFG_CENTER_IMUX23_4", + "CFG_CENTER_BYP3_11", + "CFG_CENTER_SE4C0_8", + "CFG_CENTER_LOGIC_OUTS_B4_18", + "CFG_CENTER_EE4BEG1_14", + "CFG_CENTER_EL1BEG3_17", + "CFG_CENTER_IMUX12_11", + "CFG_CENTER_IMUX23_18", + "CFG_CENTER_IMUX8_11", + "CFG_CENTER_NE4C0_0", + "CFG_CENTER_ER1BEG3_19", + "CFG_CENTER_LOGIC_OUTS_B2_13", + "CFG_CENTER_FAN7_14", + "CFG_CENTER_EE4B0_13", + "CFG_CENTER_SW4A3_2", + "CFG_CENTER_NW4END2_15", + "CFG_CENTER_WW2END1_7", + "CFG_CENTER_IMUX10_7", + "CFG_CENTER_SW2A0_10", + "CFG_CENTER_LH12_18", + "CFG_CENTER_LOGIC_OUTS_B7_18", + "CFG_CENTER_IMUX19_18", + "CFG_CENTER_WR1END3_2", + "CFG_CENTER_SE2A1_18", + "CFG_CENTER_SE4BEG3_16", + "CFG_CENTER_EE4B1_10", + "CFG_CENTER_LH9_9", + "CFG_CENTER_EE4BEG0_11", + "CFG_CENTER_IMUX1_7", + "CFG_CENTER_WW4END3_14", + "CFG_CENTER_IMUX38_3", + "CFG_CENTER_EE4B0_17", + "CFG_CENTER_WW4B3_5", + "CFG_CENTER_CLK1_14", + "CFG_CENTER_SE4BEG3_4", + "CFG_CENTER_IMUX2_5", + "CFG_CENTER_SW4END0_6", + "CFG_CENTER_SW4END2_0", + "CFG_CENTER_IMUX2_17", + "CFG_CENTER_WL1END1_14", + "CFG_CENTER_LOGIC_OUTS_B15_11", + "CFG_CENTER_EE4A3_1", + "CFG_CENTER_WL1END3_3", + "CFG_CENTER_CTRL0_12", + "CFG_CENTER_WW2A3_4", + "CFG_CENTER_BLOCK_OUTS_B0_9", + "CFG_CENTER_EL1BEG2_13", + "CFG_CENTER_NW4END0_4", + "CFG_CENTER_SE4C2_14", + "CFG_CENTER_IMUX34_6", + "CFG_CENTER_FAN4_3", + "CFG_CENTER_LH2_2", + "CFG_CENTER_LOGIC_OUTS_B0_14", + "CFG_CENTER_FAN6_11", + "CFG_CENTER_SE4BEG2_8", + "CFG_CENTER_FAN3_18", + "CFG_CENTER_SW4A2_18", + "CFG_CENTER_FAN0_19", + "CFG_CENTER_NE4C3_16", + "CFG_CENTER_WL1END0_18", + "CFG_CENTER_EE4B2_10", + "CFG_CENTER_IMUX10_5", + "CFG_CENTER_LOGIC_OUTS_B15_17", + "CFG_CENTER_EE4BEG3_8", + "CFG_CENTER_WR1END1_2", + "CFG_CENTER_WW4B3_10", + "CFG_CENTER_BLOCK_OUTS_B0_16", + "CFG_CENTER_LOGIC_OUTS_B16_19", + "CFG_CENTER_WW4B1_15", + "CFG_CENTER_BYP2_14", + "CFG_CENTER_LOGIC_OUTS_B12_6", + "CFG_CENTER_FAN0_1", + "CFG_CENTER_CLK1_12", + "CFG_CENTER_LH9_1", + "CFG_CENTER_IMUX46_15", + "CFG_CENTER_WW4A2_4", + "CFG_CENTER_IMUX22_15", + "CFG_CENTER_SE4BEG3_14", + "CFG_CENTER_NE2A3_15", + "CFG_CENTER_NE4BEG3_18", + "CFG_CENTER_SW2A2_18", + "CFG_CENTER_NW4A1_10", + "CFG_CENTER_WW4END3_19", + "CFG_CENTER_EE4B3_4", + "CFG_CENTER_FAN3_16", + "CFG_CENTER_IMUX45_6", + "CFG_CENTER_NW2A1_9", + "CFG_CENTER_EE2A3_4", + "CFG_CENTER_SE2A2_6", + "CFG_CENTER_LOGIC_OUTS_B17_9", + "CFG_CENTER_IMUX46_2", + "CFG_CENTER_EE4C1_15", + "CFG_CENTER_LOGIC_OUTS_B9_13", + "CFG_CENTER_LOGIC_OUTS_B6_19", + "CFG_CENTER_LOGIC_OUTS_B2_17", + "CFG_CENTER_WW4END2_8", + "CFG_CENTER_NW4A3_3", + "CFG_CENTER_NW4END2_4", + "CFG_CENTER_IMUX20_14", + "CFG_CENTER_LH12_19", + "CFG_CENTER_SE4C2_8", + "CFG_CENTER_LOGIC_OUTS_B5_6", + "CFG_CENTER_WW2A0_12", + "CFG_CENTER_IMUX35_19", + "CFG_CENTER_BYP1_3", + "CFG_CENTER_IMUX32_14", + "CFG_CENTER_LOGIC_OUTS_B19_7", + "CFG_CENTER_WW4C2_19", + "CFG_CENTER_WW4B1_9", + "CFG_CENTER_IMUX22_3", + "CFG_CENTER_IMUX22_18", + "CFG_CENTER_LOGIC_OUTS_B9_12", + "CFG_CENTER_WW4C1_15", + "CFG_CENTER_EE4A3_14", + "CFG_CENTER_SW4A3_3", + "CFG_CENTER_EE2A3_19", + "CFG_CENTER_NE4BEG2_7", + "CFG_CENTER_LOGIC_OUTS_B15_9", + "CFG_CENTER_FAN4_17", + "CFG_CENTER_EE4B0_6", + "CFG_CENTER_LOGIC_OUTS_B9_15", + "CFG_CENTER_NW4A1_8", + "CFG_CENTER_WW4A1_18", + "CFG_CENTER_LH4_9", + "CFG_CENTER_EE4B3_18", + "CFG_CENTER_WW4END3_6", + "CFG_CENTER_FAN4_12", + "CFG_CENTER_WW4B0_8", + "CFG_CENTER_WL1END1_0", + "CFG_CENTER_NE4C0_4", + "CFG_CENTER_WR1END2_1", + "CFG_CENTER_NW4A1_1", + "CFG_CENTER_IMUX10_9", + "CFG_CENTER_BYP5_3", + "CFG_CENTER_EE2BEG3_6", + "CFG_CENTER_BOT_USR_ACCESS_DATA2", + "CFG_CENTER_NW4END2_12", + "CFG_CENTER_EL1BEG3_7", + "CFG_CENTER_IMUX30_3", + "CFG_CENTER_FAN4_6", + "CFG_CENTER_BYP1_6", + "CFG_CENTER_EE2A3_16", + "CFG_CENTER_EE4BEG1_7", + "CFG_CENTER_LOGIC_OUTS_B11_19", + "CFG_CENTER_IMUX8_16", + "CFG_CENTER_LH10_13", + "CFG_CENTER_NW4A1_11", + "CFG_CENTER_LOGIC_OUTS_B6_16", + "CFG_CENTER_BYP0_4", + "CFG_CENTER_IMUX38_10", + "CFG_CENTER_IMUX14_6", + "CFG_CENTER_EL1BEG3_2", + "CFG_CENTER_WL1END1_8", + "CFG_CENTER_LH3_2", + "CFG_CENTER_BOT_USR_ACCESS_DATA4", + "CFG_CENTER_EE4C3_13", + "CFG_CENTER_ER1BEG0_11", + "CFG_CENTER_EE4BEG3_3", + "CFG_CENTER_LOGIC_OUTS_B12_19", + "CFG_CENTER_SE4BEG3_3", + "CFG_CENTER_CTRL0_3", + "CFG_CENTER_WW2A1_17", + "CFG_CENTER_BYP7_17", + "CFG_CENTER_IMUX16_18", + "CFG_CENTER_EE4B2_7", + "CFG_CENTER_BYP0_6", + "CFG_CENTER_SE4BEG2_12", + "CFG_CENTER_FAN4_16", + "CFG_CENTER_WW2A1_0", + "CFG_CENTER_EL1BEG1_2", + "CFG_CENTER_IMUX29_12", + "CFG_CENTER_SW2A3_9", + "CFG_CENTER_WW4B0_1", + "CFG_CENTER_WW2A3_8", + "CFG_CENTER_CTRL1_14", + "CFG_CENTER_LH5_16", + "CFG_CENTER_IMUX25_16", + "CFG_CENTER_IMUX33_16", + "CFG_CENTER_NE2A0_13", + "CFG_CENTER_LOGIC_OUTS_B9_18", + "CFG_CENTER_WR1END1_10", + "CFG_CENTER_LOGIC_OUTS_B18_7", + "CFG_CENTER_IMUX20_7", + "CFG_CENTER_EE4BEG3_5", + "CFG_CENTER_LH7_15", + "CFG_CENTER_LOGIC_OUTS_B3_9", + "CFG_CENTER_NW2A0_15", + "CFG_CENTER_BYP3_9", + "CFG_CENTER_LH11_18", + "CFG_CENTER_IMUX10_19", + "CFG_CENTER_NE4BEG3_0", + "CFG_CENTER_IMUX38_17", + "CFG_CENTER_WW4A1_8", + "CFG_CENTER_EE4B3_12", + "CFG_CENTER_EE4A2_0", + "CFG_CENTER_WW4A1_6", + "CFG_CENTER_WR1END2_12", + "CFG_CENTER_IMUX45_7", + "CFG_CENTER_NE2A3_12", + "CFG_CENTER_WW4A0_15", + "CFG_CENTER_IMUX47_18", + "CFG_CENTER_LOGIC_OUTS_B17_18", + "CFG_CENTER_BYP6_3", + "CFG_CENTER_EL1BEG1_7", + "CFG_CENTER_IMUX44_7", + "CFG_CENTER_NW4END0_7", + "CFG_CENTER_NE4C1_9", + "CFG_CENTER_LH8_5", + "CFG_CENTER_LOGIC_OUTS_B13_19", + "CFG_CENTER_LH6_5", + "CFG_CENTER_EE4C0_9", + "CFG_CENTER_LH5_8", + "CFG_CENTER_WW4END3_12", + "CFG_CENTER_IMUX18_2", + "CFG_CENTER_SE4BEG0_9", + "CFG_CENTER_WW4B0_4", + "CFG_CENTER_NE4BEG2_9", + "CFG_CENTER_LOGIC_OUTS_B19_18", + "CFG_CENTER_IMUX8_5", + "CFG_CENTER_LH2_18", + "CFG_CENTER_LOGIC_OUTS_B7_3", + "CFG_CENTER_FAN2_18", + "CFG_CENTER_EE2A0_2", + "CFG_CENTER_WW2END3_9", + "CFG_CENTER_IMUX9_19", + "CFG_CENTER_IMUX12_16", + "CFG_CENTER_WW4B2_8", + "CFG_CENTER_LOGIC_OUTS_B1_1", + "CFG_CENTER_EE4BEG3_1", + "CFG_CENTER_BOT_USR_ACCESS_DATA8", + "CFG_CENTER_SW4A2_1", + "CFG_CENTER_IMUX42_0", + "CFG_CENTER_IMUX8_2", + "CFG_CENTER_IMUX21_19", + "CFG_CENTER_WL1END0_3", + "CFG_CENTER_LH10_2", + "CFG_CENTER_SE4C3_9", + "CFG_CENTER_WR1END2_9", + "CFG_CENTER_NW4A2_12", + "CFG_CENTER_EE4B1_3", + "CFG_CENTER_IMUX17_13", + "CFG_CENTER_WR1END2_6", + "CFG_CENTER_IMUX33_10", + "CFG_CENTER_IMUX20_6", + "CFG_CENTER_LH4_18", + "CFG_CENTER_EE4A1_1", + "CFG_CENTER_NE4C2_9", + "CFG_CENTER_EL1BEG0_5", + "CFG_CENTER_IMUX9_4", + "CFG_CENTER_LH4_14", + "CFG_CENTER_EE4BEG0_6", + "CFG_CENTER_LOGIC_OUTS_B15_5", + "CFG_CENTER_EE4B0_7", + "CFG_CENTER_BYP2_7", + "CFG_CENTER_NW2A0_12", + "CFG_CENTER_EL1BEG0_15", + "CFG_CENTER_EE2BEG3_14", + "CFG_CENTER_WW4B2_15", + "CFG_CENTER_EE4A0_13", + "CFG_CENTER_FAN4_13", + "CFG_CENTER_EE4A1_2", + "CFG_CENTER_SE2A3_7", + "CFG_CENTER_WW4A3_2", + "CFG_CENTER_LOGIC_OUTS_B18_10", + "CFG_CENTER_BLOCK_OUTS_B3_0", + "CFG_CENTER_IMUX31_1", + "CFG_CENTER_SE4BEG3_19", + "CFG_CENTER_BLOCK_OUTS_B1_12", + "CFG_CENTER_IMUX26_5", + "CFG_CENTER_IMUX38_8", + "CFG_CENTER_IMUX37_8", + "CFG_CENTER_IMUX4_0", + "CFG_CENTER_LOGIC_OUTS_B22_1", + "CFG_CENTER_EE2BEG0_15", + "CFG_CENTER_WW4A0_8", + "CFG_CENTER_LOGIC_OUTS_B10_15", + "CFG_CENTER_BYP0_0", + "CFG_CENTER_IMUX35_7", + "CFG_CENTER_IMUX45_16", + "CFG_CENTER_WW2END0_9", + "CFG_CENTER_IMUX24_12", + "CFG_CENTER_IMUX47_1", + "CFG_CENTER_SE2A3_12", + "CFG_CENTER_NW2A0_0", + "CFG_CENTER_IMUX8_7", + "CFG_CENTER_NW4A1_13", + "CFG_CENTER_LOGIC_OUTS_B0_19", + "CFG_CENTER_LH10_7", + "CFG_CENTER_IMUX24_7", + "CFG_CENTER_SW2A0_0", + "CFG_CENTER_SW4A3_10", + "CFG_CENTER_LOGIC_OUTS_B16_6", + "CFG_CENTER_IMUX8_19", + "CFG_CENTER_NE2A3_2", + "CFG_CENTER_WW4END3_4", + "CFG_CENTER_NE4C1_5", + "CFG_CENTER_SE4BEG3_12", + "CFG_CENTER_LOGIC_OUTS_B11_14", + "CFG_CENTER_LOGIC_OUTS_B3_15", + "CFG_CENTER_IMUX20_18", + "CFG_CENTER_BLOCK_OUTS_B3_17", + "CFG_CENTER_NE2A2_4", + "CFG_CENTER_NE2A0_4", + "CFG_CENTER_EE4B0_4", + "CFG_CENTER_NE4C1_11", + "CFG_CENTER_BLOCK_OUTS_B1_7", + "CFG_CENTER_LH8_12", + "CFG_CENTER_NE4C0_19", + "CFG_CENTER_EE4BEG2_1", + "CFG_CENTER_IMUX32_11", + "CFG_CENTER_LOGIC_OUTS_B20_8", + "CFG_CENTER_EE4A2_13", + "CFG_CENTER_IMUX19_15", + "CFG_CENTER_EE4B3_11", + "CFG_CENTER_SE2A1_10", + "CFG_CENTER_FAN2_5", + "CFG_CENTER_LOGIC_OUTS_B1_14", + "CFG_CENTER_WW2A0_18", + "CFG_CENTER_IMUX36_2", + "CFG_CENTER_LOGIC_OUTS_B0_1", + "CFG_CENTER_WW4C1_19", + "CFG_CENTER_LOGIC_OUTS_B21_16", + "CFG_CENTER_LOGIC_OUTS_B20_5", + "CFG_CENTER_SE4C2_3", + "CFG_CENTER_IMUX33_3", + "CFG_CENTER_WW4B1_17", + "CFG_CENTER_WW4B1_16", + "CFG_CENTER_EE2BEG1_13", + "CFG_CENTER_SE4BEG1_2", + "CFG_CENTER_WW4A2_16", + "CFG_CENTER_ER1BEG2_16", + "CFG_CENTER_NW4A2_15", + "CFG_CENTER_IMUX10_4", + "CFG_CENTER_IMUX19_3", + "CFG_CENTER_IMUX7_10", + "CFG_CENTER_EE4BEG1_10", + "CFG_CENTER_WW4END0_0", + "CFG_CENTER_WW4END2_18", + "CFG_CENTER_ER1BEG1_4", + "CFG_CENTER_IMUX2_10", + "CFG_CENTER_IMUX0_3", + "CFG_CENTER_LH9_10", + "CFG_CENTER_BLOCK_OUTS_B3_8", + "CFG_CENTER_IMUX24_13", + "CFG_CENTER_WW4END2_11", + "CFG_CENTER_IMUX27_6", + "CFG_CENTER_NW2A0_14", + "CFG_CENTER_IMUX46_17", + "CFG_CENTER_WW2END3_6", + "CFG_CENTER_WW4B1_11", + "CFG_CENTER_EE2A0_6", + "CFG_CENTER_IMUX9_13", + "CFG_CENTER_LH1_10", + "CFG_CENTER_NW4A2_19", + "CFG_CENTER_SW4END1_19", + "CFG_CENTER_NW2A2_9", + "CFG_CENTER_LOGIC_OUTS_B14_11", + "CFG_CENTER_IMUX12_12", + "CFG_CENTER_WW2A1_4", + "CFG_CENTER_WL1END0_12", + "CFG_CENTER_WW4END1_3", + "CFG_CENTER_LOGIC_OUTS_B19_8", + "CFG_CENTER_IMUX25_2", + "CFG_CENTER_IMUX39_13", + "CFG_CENTER_BYP4_18", + "CFG_CENTER_IMUX35_12", + "CFG_CENTER_IMUX18_8", + "CFG_CENTER_LH11_11", + "CFG_CENTER_WW2END3_5", + "CFG_CENTER_IMUX36_5", + "CFG_CENTER_WW2A0_16", + "CFG_CENTER_EL1BEG1_8", + "CFG_CENTER_IMUX41_1", + "CFG_CENTER_EE4B3_8", + "CFG_CENTER_NW4END3_15", + "CFG_CENTER_NE2A3_10", + "CFG_CENTER_LOGIC_OUTS_B6_4", + "CFG_CENTER_WW4C1_5", + "CFG_CENTER_IMUX30_8", + "CFG_CENTER_NW4A1_15", + "CFG_CENTER_SE4C0_0", + "CFG_CENTER_EE4C3_18", + "CFG_CENTER_ER1BEG0_9", + "CFG_CENTER_NW2A1_7", + "CFG_CENTER_EE4B2_9", + "CFG_CENTER_IMUX41_9", + "CFG_CENTER_IMUX40_13", + "CFG_CENTER_IMUX43_7", + "CFG_CENTER_CLK1_0", + "CFG_CENTER_BLOCK_OUTS_B2_7", + "CFG_CENTER_NW4END3_19", + "CFG_CENTER_EE2A0_3", + "CFG_CENTER_NW4END3_3", + "CFG_CENTER_SW2A0_14", + "CFG_CENTER_IMUX11_9", + "CFG_CENTER_SW2A3_15", + "CFG_CENTER_ER1BEG2_13", + "CFG_CENTER_LOGIC_OUTS_B11_10", + "CFG_CENTER_WW4A2_2", + "CFG_CENTER_NW2A0_18", + "CFG_CENTER_IMUX17_10", + "CFG_CENTER_SE2A0_17", + "CFG_CENTER_SE4C3_5", + "CFG_CENTER_EE4C2_18", + "CFG_CENTER_IMUX6_8", + "CFG_CENTER_SW2A3_3", + "CFG_CENTER_IMUX46_3", + "CFG_CENTER_SW4END1_4", + "CFG_CENTER_LH9_19", + "CFG_CENTER_WW2A0_3", + "CFG_CENTER_SW4END3_2", + "CFG_CENTER_EE4B2_4", + "CFG_CENTER_IMUX18_19", + "CFG_CENTER_LH8_2", + "CFG_CENTER_IMUX30_14", + "CFG_CENTER_LOGIC_OUTS_B7_15", + "CFG_CENTER_LOGIC_OUTS_B20_2", + "CFG_CENTER_WW4A3_13", + "CFG_CENTER_WL1END1_1", + "CFG_CENTER_IMUX28_6", + "CFG_CENTER_SW2A0_5", + "CFG_CENTER_BYP3_6", + "CFG_CENTER_SE2A0_7", + "CFG_CENTER_LOGIC_OUTS_B16_10", + "CFG_CENTER_BYP0_10", + "CFG_CENTER_FAN0_12", + "CFG_CENTER_EE2BEG1_15", + "CFG_CENTER_SE4C1_2", + "CFG_CENTER_IMUX40_18", + "CFG_CENTER_WW2A2_4", + "CFG_CENTER_EE2A1_9", + "CFG_CENTER_EE4C3_17", + "CFG_CENTER_WR1END1_12", + "CFG_CENTER_FAN4_9", + "CFG_CENTER_WW2A2_12", + "CFG_CENTER_LOGIC_OUTS_B5_15", + "CFG_CENTER_LH11_0", + "CFG_CENTER_WW4A3_8", + "CFG_CENTER_LOGIC_OUTS_B16_15", + "CFG_CENTER_NE2A2_16", + "CFG_CENTER_LOGIC_OUTS_B21_3", + "CFG_CENTER_LOGIC_OUTS_B10_5", + "CFG_CENTER_BYP5_2", + "CFG_CENTER_LOGIC_OUTS_B9_2", + "CFG_CENTER_LOGIC_OUTS_B5_1", + "CFG_CENTER_WW4B0_12", + "CFG_CENTER_CLK1_16", + "CFG_CENTER_NW2A2_3", + "CFG_CENTER_IMUX12_7", + "CFG_CENTER_LOGIC_OUTS_B2_8", + "CFG_CENTER_LOGIC_OUTS_B4_10", + "CFG_CENTER_WW2A1_11", + "CFG_CENTER_FAN2_13", + "CFG_CENTER_EE4B0_5", + "CFG_CENTER_EE4B0_19", + "CFG_CENTER_WW4END1_14", + "CFG_CENTER_IMUX21_13", + "CFG_CENTER_NW4A3_19", + "CFG_CENTER_IMUX45_15", + "CFG_CENTER_LOGIC_OUTS_B5_7", + "CFG_CENTER_ER1BEG0_1", + "CFG_CENTER_WR1END3_4", + "CFG_CENTER_BLOCK_OUTS_B2_8", + "CFG_CENTER_IMUX47_5", + "CFG_CENTER_EE4B3_6", + "CFG_CENTER_BOT_USR_ACCESS_DATA10", + "CFG_CENTER_IMUX7_2", + "CFG_CENTER_LOGIC_OUTS_B0_4", + "CFG_CENTER_EE4C2_13", + "CFG_CENTER_IMUX39_7", + "CFG_CENTER_WW2A1_1", + "CFG_CENTER_WW4END3_7", + "CFG_CENTER_NW2A3_6", + "CFG_CENTER_SW2A1_2", + "CFG_CENTER_EE2BEG2_19", + "CFG_CENTER_LOGIC_OUTS_B8_8", + "CFG_CENTER_NW4END2_10", + "CFG_CENTER_WR1END3_11", + "CFG_CENTER_LOGIC_OUTS_B21_0", + "CFG_CENTER_NW4A3_8", + "CFG_CENTER_WW4C2_15", + "CFG_CENTER_NW4A1_2", + "CFG_CENTER_BLOCK_OUTS_B0_12", + "CFG_CENTER_SE2A2_11", + "CFG_CENTER_WR1END0_14", + "CFG_CENTER_BYP7_19", + "CFG_CENTER_SE2A3_9", + "CFG_CENTER_EE2A1_19", + "CFG_CENTER_LH6_18", + "CFG_CENTER_FAN3_19", + "CFG_CENTER_BYP7_11", + "CFG_CENTER_WW4END1_12", + "CFG_CENTER_SW4A1_17", + "CFG_CENTER_IMUX14_19", + "CFG_CENTER_EE4C2_5", + "CFG_CENTER_NW4END1_15", + "CFG_CENTER_LH1_19", + "CFG_CENTER_LOGIC_OUTS_B2_4", + "CFG_CENTER_NE2A2_17", + "CFG_CENTER_IMUX6_0", + "CFG_CENTER_SW4A0_1", + "CFG_CENTER_NW4A3_18", + "CFG_CENTER_SW4A2_5", + "CFG_CENTER_LH10_4", + "CFG_CENTER_LOGIC_OUTS_B13_1", + "CFG_CENTER_NE2A1_1", + "CFG_CENTER_EE4C1_12", + "CFG_CENTER_EE4C2_15", + "CFG_CENTER_LH9_12", + "CFG_CENTER_WW4END0_11", + "CFG_CENTER_LOGIC_OUTS_B14_8", + "CFG_CENTER_IMUX23_19", + "CFG_CENTER_IMUX24_8", + "CFG_CENTER_NE2A2_6", + "CFG_CENTER_LH8_1", + "CFG_CENTER_LOGIC_OUTS_B1_16", + "CFG_CENTER_LH7_19", + "CFG_CENTER_WW4END2_10", + "CFG_CENTER_LH4_4", + "CFG_CENTER_IMUX46_16", + "CFG_CENTER_NW2A0_6", + "CFG_CENTER_LH5_19", + "CFG_CENTER_NW2A3_16", + "CFG_CENTER_CLK0_2", + "CFG_CENTER_IMUX1_2", + "CFG_CENTER_LH9_18", + "CFG_CENTER_SE2A3_15", + "CFG_CENTER_IMUX13_13", + "CFG_CENTER_EE4A1_8", + "CFG_CENTER_WW4END0_1", + "CFG_CENTER_IMUX26_11", + "CFG_CENTER_LOGIC_OUTS_B1_9", + "CFG_CENTER_SW4END0_7", + "CFG_CENTER_NW2A2_16", + "CFG_CENTER_NE2A0_15", + "CFG_CENTER_EE4A1_7", + "CFG_CENTER_EE2A3_12", + "CFG_CENTER_IMUX39_9", + "CFG_CENTER_IMUX8_10", + "CFG_CENTER_FAN5_9", + "CFG_CENTER_EE4B0_3", + "CFG_CENTER_IMUX20_3", + "CFG_CENTER_SW4A1_1", + "CFG_CENTER_LOGIC_OUTS_B4_7", + "CFG_CENTER_LOGIC_OUTS_B19_1", + "CFG_CENTER_NE4BEG1_17", + "CFG_CENTER_IMUX44_9", + "CFG_CENTER_EE2A2_10", + "CFG_CENTER_SW4A3_6", + "CFG_CENTER_BYP6_5", + "CFG_CENTER_LH11_3", + "CFG_CENTER_IMUX7_17", + "CFG_CENTER_IMUX29_10", + "CFG_CENTER_LH2_9", + "CFG_CENTER_LOGIC_OUTS_B13_10", + "CFG_CENTER_ER1BEG0_13", + "CFG_CENTER_WR1END0_16", + "CFG_CENTER_IMUX5_18", + "CFG_CENTER_WR1END3_12", + "CFG_CENTER_WW4C3_10", + "CFG_CENTER_WW4B2_14", + "CFG_CENTER_IMUX35_8", + "CFG_CENTER_WW4END3_16", + "CFG_CENTER_CTRL0_18", + "CFG_CENTER_SW4A2_9", + "CFG_CENTER_NE4BEG0_1", + "CFG_CENTER_CTRL0_1", + "CFG_CENTER_BYP7_18", + "CFG_CENTER_IMUX38_13", + "CFG_CENTER_LH2_10", + "CFG_CENTER_LH8_6", + "CFG_CENTER_SW4END2_13", + "CFG_CENTER_LOGIC_OUTS_B7_12", + "CFG_CENTER_IMUX9_12", + "CFG_CENTER_WR1END1_7", + "CFG_CENTER_WW4END0_9", + "CFG_CENTER_WW4C2_2", + "CFG_CENTER_EL1BEG0_14", + "CFG_CENTER_EL1BEG1_16", + "CFG_CENTER_NW4A1_5", + "CFG_CENTER_IMUX34_19", + "CFG_CENTER_EL1BEG3_5", + "CFG_CENTER_BYP6_11", + "CFG_CENTER_WW4END2_19", + "CFG_CENTER_FAN5_18", + "CFG_CENTER_NE4C3_0", + "CFG_CENTER_BLOCK_OUTS_B0_15", + "CFG_CENTER_NE4C2_18", + "CFG_CENTER_BLOCK_OUTS_B2_11", + "CFG_CENTER_LOGIC_OUTS_B21_2", + "CFG_CENTER_FAN1_2", + "CFG_CENTER_NE4C0_2", + "CFG_CENTER_WW4END1_8", + "CFG_CENTER_LH10_1", + "CFG_CENTER_IMUX40_0", + "CFG_CENTER_NW2A0_7", + "CFG_CENTER_IMUX8_8", + "CFG_CENTER_LH6_2", + "CFG_CENTER_LOGIC_OUTS_B0_10", + "CFG_CENTER_WW2END2_1", + "CFG_CENTER_IMUX40_15", + "CFG_CENTER_LOGIC_OUTS_B2_18", + "CFG_CENTER_LH8_16", + "CFG_CENTER_BYP3_14", + "CFG_CENTER_CTRL1_4", + "CFG_CENTER_EE2BEG2_0", + "CFG_CENTER_BYP6_15", + "CFG_CENTER_NE4BEG0_4", + "CFG_CENTER_IMUX29_7", + "CFG_CENTER_LH11_8", + "CFG_CENTER_IMUX47_13", + "CFG_CENTER_LOGIC_OUTS_B22_13", + "CFG_CENTER_SW4END0_13", + "CFG_CENTER_LOGIC_OUTS_B18_6", + "CFG_CENTER_IMUX42_11", + "CFG_CENTER_SW2A0_11", + "CFG_CENTER_LOGIC_OUTS_B23_12", + "CFG_CENTER_LOGIC_OUTS_B1_11", + "CFG_CENTER_SW2A1_16", + "CFG_CENTER_NE2A3_9", + "CFG_CENTER_LH4_19", + "CFG_CENTER_SE4C2_13", + "CFG_CENTER_EE4BEG3_17", + "CFG_CENTER_EE4B2_14", + "CFG_CENTER_IMUX45_3", + "CFG_CENTER_IMUX14_9", + "CFG_CENTER_WW4C2_12", + "CFG_CENTER_LH5_18", + "CFG_CENTER_EE4C0_10", + "CFG_CENTER_IMUX43_19", + "CFG_CENTER_IMUX6_7", + "CFG_CENTER_LOGIC_OUTS_B18_1", + "CFG_CENTER_SW4A2_19", + "CFG_CENTER_IMUX17_0", + "CFG_CENTER_IMUX18_12", + "CFG_CENTER_LOGIC_OUTS_B8_17", + "CFG_CENTER_IMUX36_9", + "CFG_CENTER_IMUX31_3", + "CFG_CENTER_BYP0_2", + "CFG_CENTER_LH7_10", + "CFG_CENTER_WL1END3_9", + "CFG_CENTER_IMUX27_11", + "CFG_CENTER_LOGIC_OUTS_B4_14", + "CFG_CENTER_NW4END2_1", + "CFG_CENTER_EL1BEG0_1", + "CFG_CENTER_EE4BEG1_11", + "CFG_CENTER_BYP2_10", + "CFG_CENTER_IMUX30_10", + "CFG_CENTER_LOGIC_OUTS_B15_14", + "CFG_CENTER_LH8_8", + "CFG_CENTER_SW2A1_13", + "CFG_CENTER_IMUX9_6", + "CFG_CENTER_IMUX26_1", + "CFG_CENTER_LOGIC_OUTS_B23_9", + "CFG_CENTER_IMUX19_8", + "CFG_CENTER_SW4A0_14", + "CFG_CENTER_LOGIC_OUTS_B12_12", + "CFG_CENTER_LOGIC_OUTS_B22_8", + "CFG_CENTER_EE4B1_19", + "CFG_CENTER_EE2A1_17", + "CFG_CENTER_WW4A2_3", + "CFG_CENTER_IMUX42_6", + "CFG_CENTER_SW4END1_3", + "CFG_CENTER_NW2A2_19", + "CFG_CENTER_IMUX37_11", + "CFG_CENTER_NE4C2_11", + "CFG_CENTER_IMUX25_5", + "CFG_CENTER_EL1BEG0_11", + "CFG_CENTER_IMUX40_12", + "CFG_CENTER_WR1END0_0", + "CFG_CENTER_WW4C3_19", + "CFG_CENTER_EE2A2_18", + "CFG_CENTER_EE2BEG3_16", + "CFG_CENTER_NE4C0_18", + "CFG_CENTER_ER1BEG1_0", + "CFG_CENTER_SE4BEG2_17", + "CFG_CENTER_SE4C2_4", + "CFG_CENTER_IMUX0_12", + "CFG_CENTER_IMUX31_10", + "CFG_CENTER_ER1BEG1_8", + "CFG_CENTER_IMUX43_18", + "CFG_CENTER_LOGIC_OUTS_B8_16", + "CFG_CENTER_NW4END2_5", + "CFG_CENTER_WL1END0_16", + "CFG_CENTER_BYP1_5", + "CFG_CENTER_EE4A2_1", + "CFG_CENTER_IMUX25_19", + "CFG_CENTER_NE2A3_16", + "CFG_CENTER_IMUX22_5", + "CFG_CENTER_NE4C3_1", + "CFG_CENTER_IMUX41_13", + "CFG_CENTER_EE4BEG1_17", + "CFG_CENTER_FAN3_6", + "CFG_CENTER_LOGIC_OUTS_B13_13", + "CFG_CENTER_IMUX31_13", + "CFG_CENTER_IMUX31_8", + "CFG_CENTER_IMUX3_10", + "CFG_CENTER_NE4BEG3_10", + "CFG_CENTER_LOGIC_OUTS_B6_13", + "CFG_CENTER_CLK0_11", + "CFG_CENTER_LH12_17", + "CFG_CENTER_BLOCK_OUTS_B1_16", + "CFG_CENTER_NE4BEG3_7", + "CFG_CENTER_NE4BEG2_10", + "CFG_CENTER_IMUX11_1", + "CFG_CENTER_NE2A3_4", + "CFG_CENTER_NW2A2_1", + "CFG_CENTER_WW2END2_7", + "CFG_CENTER_EE4C1_7", + "CFG_CENTER_BYP7_4", + "CFG_CENTER_EE2BEG2_16", + "CFG_CENTER_WW4END0_19", + "CFG_CENTER_IMUX12_15", + "CFG_CENTER_LOGIC_OUTS_B1_2", + "CFG_CENTER_EE4C0_17", + "CFG_CENTER_WW4C0_6", + "CFG_CENTER_SW4A3_17", + "CFG_CENTER_IMUX35_10", + "CFG_CENTER_LH11_4", + "CFG_CENTER_FAN3_10", + "CFG_CENTER_EE4C0_12", + "CFG_CENTER_NE4C3_13", + "CFG_CENTER_LOGIC_OUTS_B8_14", + "CFG_CENTER_IMUX37_15", + "CFG_CENTER_EE2A3_9", + "CFG_CENTER_LOGIC_OUTS_B4_1", + "CFG_CENTER_IMUX33_1", + "CFG_CENTER_EE4A2_17", + "CFG_CENTER_WW4B2_3", + "CFG_CENTER_LOGIC_OUTS_B10_19", + "CFG_CENTER_LOGIC_OUTS_B7_10", + "CFG_CENTER_EL1BEG3_4", + "CFG_CENTER_IMUX26_7", + "CFG_CENTER_IMUX36_16", + "CFG_CENTER_LOGIC_OUTS_B22_16", + "CFG_CENTER_WW2END1_5", + "CFG_CENTER_WW4C1_12", + "CFG_CENTER_EE4C0_2", + "CFG_CENTER_FAN0_9", + "CFG_CENTER_WW2END2_15", + "CFG_CENTER_LH1_1", + "CFG_CENTER_WW2A3_16", + "CFG_CENTER_NE4BEG1_9", + "CFG_CENTER_ER1BEG2_9", + "CFG_CENTER_LH2_4", + "CFG_CENTER_FAN3_14", + "CFG_CENTER_SW4END1_17", + "CFG_CENTER_FAN2_16", + "CFG_CENTER_LOGIC_OUTS_B16_5", + "CFG_CENTER_IMUX21_8", + "CFG_CENTER_LOGIC_OUTS_B13_8", + "CFG_CENTER_CTRL0_15", + "CFG_CENTER_WL1END2_0", + "CFG_CENTER_IMUX23_1", + "CFG_CENTER_WW2A2_3", + "CFG_CENTER_SW4A0_19", + "CFG_CENTER_LH12_0", + "CFG_CENTER_LH4_5", + "CFG_CENTER_SE4BEG1_1", + "CFG_CENTER_LOGIC_OUTS_B14_13", + "CFG_CENTER_WL1END0_0", + "CFG_CENTER_ER1BEG3_10", + "CFG_CENTER_EE4B3_16", + "CFG_CENTER_SW4A3_1", + "CFG_CENTER_LOGIC_OUTS_B9_1", + "CFG_CENTER_IMUX19_16", + "CFG_CENTER_WW2END1_6", + "CFG_CENTER_IMUX9_17", + "CFG_CENTER_LOGIC_OUTS_B22_19", + "CFG_CENTER_NE4BEG2_0", + "CFG_CENTER_LOGIC_OUTS_B13_12", + "CFG_CENTER_LH5_13", + "CFG_CENTER_ER1BEG3_1", + "CFG_CENTER_LH3_18", + "CFG_CENTER_BYP0_18", + "CFG_CENTER_LH8_18", + "CFG_CENTER_NW2A3_12", + "CFG_CENTER_EE4BEG1_15", + "CFG_CENTER_BYP2_15", + "CFG_CENTER_NE2A3_0", + "CFG_CENTER_IMUX25_15", + "CFG_CENTER_SE4BEG0_13", + "CFG_CENTER_BOT_USR_ACCESS_DATA14", + "CFG_CENTER_LOGIC_OUTS_B17_12", + "CFG_CENTER_ER1BEG2_11", + "CFG_CENTER_NE4C1_10", + "CFG_CENTER_SW4END2_2", + "CFG_CENTER_EE2A2_13", + "CFG_CENTER_WW4C3_13", + "CFG_CENTER_ER1BEG1_17", + "CFG_CENTER_IMUX30_1", + "CFG_CENTER_NW4END2_19", + "CFG_CENTER_IMUX15_13", + "CFG_CENTER_EL1BEG0_18", + "CFG_CENTER_BLOCK_OUTS_B0_5", + "CFG_CENTER_LH8_19", + "CFG_CENTER_EE2A1_3", + "CFG_CENTER_EE4C3_9", + "CFG_CENTER_IMUX0_4", + "CFG_CENTER_BYP0_19", + "CFG_CENTER_IMUX16_9", + "CFG_CENTER_FAN4_10", + "CFG_CENTER_LOGIC_OUTS_B23_5", + "CFG_CENTER_SW2A3_8", + "CFG_CENTER_IMUX23_6", + "CFG_CENTER_NW4END3_1", + "CFG_CENTER_WR1END3_13", + "CFG_CENTER_EE4A3_18", + "CFG_CENTER_NE4C0_13", + "CFG_CENTER_IMUX46_9", + "CFG_CENTER_WW2END2_3", + "CFG_CENTER_FAN1_14", + "CFG_CENTER_IMUX46_13", + "CFG_CENTER_LOGIC_OUTS_B4_0", + "CFG_CENTER_WR1END0_7", + "CFG_CENTER_SE4BEG3_8", + "CFG_CENTER_NE4C2_12", + "CFG_CENTER_BYP2_18", + "CFG_CENTER_WL1END2_12", + "CFG_CENTER_IMUX14_7", + "CFG_CENTER_SE4C3_8", + "CFG_CENTER_IMUX0_16", + "CFG_CENTER_WL1END3_12", + "CFG_CENTER_BYP3_18", + "CFG_CENTER_NW2A0_3", + "CFG_CENTER_LOGIC_OUTS_B2_12", + "CFG_CENTER_WW4A3_5", + "CFG_CENTER_EL1BEG3_19", + "CFG_CENTER_BLOCK_OUTS_B1_1", + "CFG_CENTER_NE2A3_18", + "CFG_CENTER_BYP5_14", + "CFG_CENTER_EL1BEG2_10", + "CFG_CENTER_WW2END1_2", + "CFG_CENTER_LH8_9", + "CFG_CENTER_WW2END2_4", + "CFG_CENTER_IMUX29_6", + "CFG_CENTER_WW4B1_8", + "CFG_CENTER_ER1BEG3_5", + "CFG_CENTER_NW4END0_8", + "CFG_CENTER_NW4A0_14", + "CFG_CENTER_NW4END1_14", + "CFG_CENTER_IMUX17_3", + "CFG_CENTER_BLOCK_OUTS_B0_3", + "CFG_CENTER_IMUX32_12", + "CFG_CENTER_NW4A0_18", + "CFG_CENTER_EE4A3_0", + "CFG_CENTER_IMUX19_11", + "CFG_CENTER_EE4C0_19", + "CFG_CENTER_SW2A1_7", + "CFG_CENTER_LH3_13", + "CFG_CENTER_IMUX37_18", + "CFG_CENTER_EE4B2_0", + "CFG_CENTER_EE4A1_9", + "CFG_CENTER_LH12_7", + "CFG_CENTER_IMUX36_8", + "CFG_CENTER_WW4A3_10", + "CFG_CENTER_LOGIC_OUTS_B17_1", + "CFG_CENTER_LH4_15", + "CFG_CENTER_IMUX21_6", + "CFG_CENTER_LOGIC_OUTS_B18_17", + "CFG_CENTER_LOGIC_OUTS_B4_9", + "CFG_CENTER_NW4A3_6", + "CFG_CENTER_NW4END3_7", + "CFG_CENTER_LOGIC_OUTS_B2_6", + "CFG_CENTER_IMUX44_3", + "CFG_CENTER_WR1END1_4", + "CFG_CENTER_IMUX35_13", + "CFG_CENTER_NE4C0_16", + "CFG_CENTER_IMUX6_17", + "CFG_CENTER_SW2A2_4", + "CFG_CENTER_SW2A3_10", + "CFG_CENTER_NW4A1_3", + "CFG_CENTER_LOGIC_OUTS_B1_10", + "CFG_CENTER_NW2A2_0", + "CFG_CENTER_NW2A2_2", + "CFG_CENTER_IMUX12_19", + "CFG_CENTER_NE4BEG0_2", + "CFG_CENTER_NW4END0_9", + "CFG_CENTER_CLK1_19", + "CFG_CENTER_NW2A2_14", + "CFG_CENTER_SE2A3_6", + "CFG_CENTER_FAN6_6", + "CFG_CENTER_LH2_12", + "CFG_CENTER_CTRL0_9", + "CFG_CENTER_FAN6_8", + "CFG_CENTER_LOGIC_OUTS_B3_5", + "CFG_CENTER_IMUX0_0", + "CFG_CENTER_FAN5_1", + "CFG_CENTER_EE4BEG0_15", + "CFG_CENTER_SE4BEG2_10", + "CFG_CENTER_IMUX24_11", + "CFG_CENTER_WR1END1_1", + "CFG_CENTER_WR1END3_14", + "CFG_CENTER_SW4END3_15", + "CFG_CENTER_IMUX16_10", + "CFG_CENTER_NE4BEG3_14", + "CFG_CENTER_SW4A2_15", + "CFG_CENTER_SE4BEG3_5", + "CFG_CENTER_SE4BEG1_8", + "CFG_CENTER_IMUX24_9", + "CFG_CENTER_NW4END0_17", + "CFG_CENTER_WW2END2_10", + "CFG_CENTER_LOGIC_OUTS_B19_17", + "CFG_CENTER_EL1BEG1_14", + "CFG_CENTER_LH8_4", + "CFG_CENTER_LOGIC_OUTS_B18_8", + "CFG_CENTER_SW2A0_19", + "CFG_CENTER_EE2A1_2", + "CFG_CENTER_SE2A1_6", + "CFG_CENTER_WW4A2_7", + "CFG_CENTER_EE2A1_8", + "CFG_CENTER_ER1BEG1_18", + "CFG_CENTER_SE4C3_13", + "CFG_CENTER_LOGIC_OUTS_B6_2", + "CFG_CENTER_IMUX30_0", + "CFG_CENTER_WW4B0_13", + "CFG_CENTER_EE4A2_16", + "CFG_CENTER_IMUX3_4", + "CFG_CENTER_SW4A0_5", + "CFG_CENTER_WW4END1_0", + "CFG_CENTER_LOGIC_OUTS_B0_7", + "CFG_CENTER_SW4END1_11", + "CFG_CENTER_WW4C2_10", + "CFG_CENTER_BYP2_1", + "CFG_CENTER_IMUX20_8", + "CFG_CENTER_EE4BEG0_7", + "CFG_CENTER_NE4C0_3", + "CFG_CENTER_SE4C0_6", + "CFG_CENTER_NE2A0_12", + "CFG_CENTER_WR1END1_8", + "CFG_CENTER_IMUX46_11", + "CFG_CENTER_IMUX37_16", + "CFG_CENTER_EE4A3_7", + "CFG_CENTER_LH3_5", + "CFG_CENTER_IMUX38_14", + "CFG_CENTER_IMUX28_7", + "CFG_CENTER_CLK0_5", + "CFG_CENTER_LOGIC_OUTS_B3_8", + "CFG_CENTER_IMUX32_16", + "CFG_CENTER_IMUX39_14", + "CFG_CENTER_WW2END0_13", + "CFG_CENTER_SE4BEG0_2", + "CFG_CENTER_EE4BEG3_10", + "CFG_CENTER_IMUX33_9", + "CFG_CENTER_NE2A2_18", + "CFG_CENTER_LH12_2", + "CFG_CENTER_IMUX18_3", + "CFG_CENTER_EE2A2_6", + "CFG_CENTER_NW2A0_10", + "CFG_CENTER_IMUX43_11", + "CFG_CENTER_NE4C1_15", + "CFG_CENTER_EE4C0_3", + "CFG_CENTER_IMUX24_17", + "CFG_CENTER_LOGIC_OUTS_B12_18", + "CFG_CENTER_SW4END3_17", + "CFG_CENTER_IMUX6_5", + "CFG_CENTER_EE2BEG3_3", + "CFG_CENTER_SE2A2_16", + "CFG_CENTER_LH9_8", + "CFG_CENTER_EE4C2_12", + "CFG_CENTER_EE2BEG0_16", + "CFG_CENTER_SW2A3_12", + "CFG_CENTER_BYP6_13", + "CFG_CENTER_FAN3_0", + "CFG_CENTER_IMUX19_10", + "CFG_CENTER_IMUX41_14", + "CFG_CENTER_NE2A1_7", + "CFG_CENTER_EE4BEG3_18", + "CFG_CENTER_IMUX5_2", + "CFG_CENTER_IMUX32_8", + "CFG_CENTER_IMUX46_0", + "CFG_CENTER_EE4A2_18", + "CFG_CENTER_IMUX5_17", + "CFG_CENTER_WR1END2_7", + "CFG_CENTER_IMUX10_3", + "CFG_CENTER_IMUX29_18", + "CFG_CENTER_NE4BEG3_15", + "CFG_CENTER_IMUX34_7", + "CFG_CENTER_WW4B0_9", + "CFG_CENTER_SE4C0_17", + "CFG_CENTER_NW4END2_9", + "CFG_CENTER_NE4BEG3_17", + "CFG_CENTER_SE4BEG2_13", + "CFG_CENTER_ER1BEG0_6", + "CFG_CENTER_LOGIC_OUTS_B10_11", + "CFG_CENTER_IMUX12_2", + "CFG_CENTER_LH10_5", + "CFG_CENTER_EE2A3_18", + "CFG_CENTER_LOGIC_OUTS_B7_9", + "CFG_CENTER_WW4END3_17", + "CFG_CENTER_IMUX4_14", + "CFG_CENTER_EE4C2_14", + "CFG_CENTER_LH3_10", + "CFG_CENTER_IMUX5_7", + "CFG_CENTER_WW2A2_0", + "CFG_CENTER_IMUX21_14", + "CFG_CENTER_IMUX15_3", + "CFG_CENTER_WW2A2_8", + "CFG_CENTER_LOGIC_OUTS_B9_9", + "CFG_CENTER_SE4BEG3_17", + "CFG_CENTER_WW2A1_14", + "CFG_CENTER_IMUX34_4", + "CFG_CENTER_IMUX7_12", + "CFG_CENTER_EL1BEG2_16", + "CFG_CENTER_EE4BEG3_13", + "CFG_CENTER_LH12_14", + "CFG_CENTER_WW4A0_1", + "CFG_CENTER_IMUX13_19", + "CFG_CENTER_WW2END2_9", + "CFG_CENTER_IMUX35_16", + "CFG_CENTER_LOGIC_OUTS_B20_4", + "CFG_CENTER_EE2A2_2", + "CFG_CENTER_LH10_19", + "CFG_CENTER_EE2BEG1_12", + "CFG_CENTER_CTRL1_9", + "CFG_CENTER_EE2A0_15", + "CFG_CENTER_LH4_10", + "CFG_CENTER_EL1BEG3_1", + "CFG_CENTER_WW4C2_16", + "CFG_CENTER_IMUX0_8", + "CFG_CENTER_NW2A0_2", + "CFG_CENTER_WW4END1_4", + "CFG_CENTER_EE4C0_15", + "CFG_CENTER_EE2BEG2_2", + "CFG_CENTER_IMUX19_14", + "CFG_CENTER_SW2A3_13", + "CFG_CENTER_IMUX20_17", + "CFG_CENTER_IMUX30_13", + "CFG_CENTER_WW4A2_9", + "CFG_CENTER_IMUX10_10", + "CFG_CENTER_LH7_9", + "CFG_CENTER_EE4C1_14", + "CFG_CENTER_EE2BEG0_8", + "CFG_CENTER_FAN1_17", + "CFG_CENTER_IMUX5_3", + "CFG_CENTER_WW4A1_15", + "CFG_CENTER_LOGIC_OUTS_B18_15", + "CFG_CENTER_WR1END1_3", + "CFG_CENTER_NE2A3_5", + "CFG_CENTER_LH10_18", + "CFG_CENTER_LH9_15", + "CFG_CENTER_FAN2_19", + "CFG_CENTER_IMUX2_3", + "CFG_CENTER_IMUX38_15", + "CFG_CENTER_IMUX14_13", + "CFG_CENTER_SW4A0_0", + "CFG_CENTER_EE4B3_3", + "CFG_CENTER_IMUX17_5", + "CFG_CENTER_NE4BEG0_11", + "CFG_CENTER_LH6_8", + "CFG_CENTER_BYP1_8", + "CFG_CENTER_BLOCK_OUTS_B2_3", + "CFG_CENTER_LOGIC_OUTS_B12_4", + "CFG_CENTER_BYP7_0", + "CFG_CENTER_IMUX0_19", + "CFG_CENTER_NW2A1_1", + "CFG_CENTER_LOGIC_OUTS_B18_18", + "CFG_CENTER_WW4A2_13", + "CFG_CENTER_SE4BEG0_0", + "CFG_CENTER_IMUX13_5", + "CFG_CENTER_NW2A3_5", + "CFG_CENTER_EE2BEG0_3", + "CFG_CENTER_ER1BEG0_8", + "CFG_CENTER_WW2A3_12", + "CFG_CENTER_IMUX4_8", + "CFG_CENTER_EE4B3_2", + "CFG_CENTER_BYP2_3", + "CFG_CENTER_IMUX38_5", + "CFG_CENTER_EE4A1_6", + "CFG_CENTER_WW4C0_4", + "CFG_CENTER_EE2A1_18", + "CFG_CENTER_IMUX9_7", + "CFG_CENTER_IMUX23_13", + "CFG_CENTER_FAN7_19", + "CFG_CENTER_BYP2_9", + "CFG_CENTER_IMUX32_17", + "CFG_CENTER_SW4A3_12", + "CFG_CENTER_EE4BEG3_2", + "CFG_CENTER_SE4BEG1_0", + "CFG_CENTER_EE4B2_13", + "CFG_CENTER_WW2END0_2", + "CFG_CENTER_SE4BEG0_15", + "CFG_CENTER_LOGIC_OUTS_B22_11", + "CFG_CENTER_NW4END3_17", + "CFG_CENTER_SW4END1_15", + "CFG_CENTER_IMUX2_19", + "CFG_CENTER_SE4C3_19", + "CFG_CENTER_LOGIC_OUTS_B6_17", + "CFG_CENTER_IMUX29_0", + "CFG_CENTER_FAN1_13", + "CFG_CENTER_WW2A0_19", + "CFG_CENTER_SW4END3_13", + "CFG_CENTER_IMUX18_10", + "CFG_CENTER_EE4A0_0", + "CFG_CENTER_IMUX9_0", + "CFG_CENTER_ER1BEG3_6", + "CFG_CENTER_NW4END0_2", + "CFG_CENTER_NW2A3_14", + "CFG_CENTER_EE4BEG2_10", + "CFG_CENTER_ER1BEG0_10", + "CFG_CENTER_FAN6_12", + "CFG_CENTER_LOGIC_OUTS_B1_8", + "CFG_CENTER_NE4C1_0", + "CFG_CENTER_EE4A1_0", + "CFG_CENTER_LOGIC_OUTS_B12_2", + "CFG_CENTER_WW2END3_0", + "CFG_CENTER_SE4C2_17", + "CFG_CENTER_WW4END1_10", + "CFG_CENTER_FAN7_17", + "CFG_CENTER_LOGIC_OUTS_B14_16", + "CFG_CENTER_IMUX43_0", + "CFG_CENTER_IMUX3_8", + "CFG_CENTER_SW4A1_4", + "CFG_CENTER_NE4BEG1_3", + "CFG_CENTER_EE2A0_7", + "CFG_CENTER_IMUX0_7", + "CFG_CENTER_IMUX45_5", + "CFG_CENTER_EE4C1_4", + "CFG_CENTER_BLOCK_OUTS_B0_2", + "CFG_CENTER_IMUX43_1", + "CFG_CENTER_IMUX33_18", + "CFG_CENTER_NE2A0_5", + "CFG_CENTER_SE2A0_15", + "CFG_CENTER_SE2A2_2", + "CFG_CENTER_EE4A1_12", + "CFG_CENTER_NE4C2_17", + "CFG_CENTER_CTRL0_17", + "CFG_CENTER_SW4END2_19", + "CFG_CENTER_FAN7_8", + "CFG_CENTER_SW4A1_9", + "CFG_CENTER_WR1END3_15", + "CFG_CENTER_BYP7_5", + "CFG_CENTER_NE4BEG1_10", + "CFG_CENTER_NE2A2_11", + "CFG_CENTER_CTRL0_14", + "CFG_CENTER_LOGIC_OUTS_B16_0", + "CFG_CENTER_BOT_USR_ACCESS_DATA12", + "CFG_CENTER_EL1BEG2_5", + "CFG_CENTER_EE2A0_17", + "CFG_CENTER_EE4C0_0", + "CFG_CENTER_NE4BEG1_8", + "CFG_CENTER_IMUX13_6", + "CFG_CENTER_IMUX9_10", + "CFG_CENTER_NW2A3_0", + "CFG_CENTER_IMUX39_2", + "CFG_CENTER_FAN5_16", + "CFG_CENTER_LOGIC_OUTS_B11_6", + "CFG_CENTER_IMUX16_0", + "CFG_CENTER_WR1END0_5", + "CFG_CENTER_SW4A2_14", + "CFG_CENTER_SE4BEG0_5", + "CFG_CENTER_LOGIC_OUTS_B1_19", + "CFG_CENTER_ER1BEG1_11", + "CFG_CENTER_BLOCK_OUTS_B1_17", + "CFG_CENTER_IMUX23_17", + "CFG_CENTER_IMUX22_2", + "CFG_CENTER_NW4END2_8", + "CFG_CENTER_SE4BEG1_11", + "CFG_CENTER_FAN2_17", + "CFG_CENTER_IMUX43_15", + "CFG_CENTER_LOGIC_OUTS_B23_8", + "CFG_CENTER_FAN3_5", + "CFG_CENTER_FAN1_19", + "CFG_CENTER_WW4A3_11", + "CFG_CENTER_CLK1_3", + "CFG_CENTER_IMUX15_6", + "CFG_CENTER_LOGIC_OUTS_B20_10", + "CFG_CENTER_SW2A2_16", + "CFG_CENTER_SW2A1_1", + "CFG_CENTER_WL1END0_11", + "CFG_CENTER_WW4A2_15", + "CFG_CENTER_WL1END3_0", + "CFG_CENTER_FAN4_15", + "CFG_CENTER_IMUX36_6", + "CFG_CENTER_NW4A0_19", + "CFG_CENTER_LOGIC_OUTS_B22_4", + "CFG_CENTER_WL1END2_10", + "CFG_CENTER_BYP0_13", + "CFG_CENTER_NE4BEG2_8", + "CFG_CENTER_NE4BEG2_3", + "CFG_CENTER_IMUX10_8", + "CFG_CENTER_LOGIC_OUTS_B10_0", + "CFG_CENTER_WR1END2_16", + "CFG_CENTER_EL1BEG2_7", + "CFG_CENTER_WW2A3_18", + "CFG_CENTER_WW4B2_7", + "CFG_CENTER_IMUX10_17", + "CFG_CENTER_SW2A3_0", + "CFG_CENTER_LOGIC_OUTS_B9_7", + "CFG_CENTER_WW4B3_6", + "CFG_CENTER_WW4A2_17", + "CFG_CENTER_IMUX39_17", + "CFG_CENTER_SE4C0_18", + "CFG_CENTER_IMUX0_14", + "CFG_CENTER_LOGIC_OUTS_B18_12", + "CFG_CENTER_WW4END3_5", + "CFG_CENTER_EE4BEG2_3", + "CFG_CENTER_NW2A0_16", + "CFG_CENTER_NE2A1_17", + "CFG_CENTER_LH5_11", + "CFG_CENTER_IMUX17_6", + "CFG_CENTER_SW4END0_15", + "CFG_CENTER_NW4END1_13", + "CFG_CENTER_WL1END0_4", + "CFG_CENTER_WW2END1_1", + "CFG_CENTER_FAN4_5", + "CFG_CENTER_LOGIC_OUTS_B13_14", + "CFG_CENTER_BLOCK_OUTS_B3_5", + "CFG_CENTER_LH4_2", + "CFG_CENTER_FAN3_13", + "CFG_CENTER_WW2END1_9", + "CFG_CENTER_BLOCK_OUTS_B0_13", + "CFG_CENTER_BLOCK_OUTS_B2_17", + "CFG_CENTER_IMUX5_0", + "CFG_CENTER_WW4C2_3", + "CFG_CENTER_WW4C0_1", + "CFG_CENTER_NW2A3_7", + "CFG_CENTER_EE4A1_5", + "CFG_CENTER_CTRL1_19", + "CFG_CENTER_IMUX1_14", + "CFG_CENTER_IMUX33_8", + "CFG_CENTER_NE4BEG2_5", + "CFG_CENTER_EE4B1_6", + "CFG_CENTER_IMUX14_15", + "CFG_CENTER_IMUX7_8", + "CFG_CENTER_LOGIC_OUTS_B14_15", + "CFG_CENTER_WW4END1_19", + "CFG_CENTER_EE2A2_14", + "CFG_CENTER_ER1BEG1_10", + "CFG_CENTER_IMUX45_8", + "CFG_CENTER_NE2A0_14", + "CFG_CENTER_BYP2_17", + "CFG_CENTER_EE2BEG0_13", + "CFG_CENTER_CTRL1_17", + "CFG_CENTER_WW2A1_6", + "CFG_CENTER_SE4C1_6", + "CFG_CENTER_IMUX39_18", + "CFG_CENTER_SW4A2_0", + "CFG_CENTER_NE2A2_9", + "CFG_CENTER_IMUX11_17", + "CFG_CENTER_WL1END2_18", + "CFG_CENTER_EE4BEG0_12", + "CFG_CENTER_NE4BEG1_1", + "CFG_CENTER_IMUX39_6", + "CFG_CENTER_WL1END2_19", + "CFG_CENTER_EE4C3_5", + "CFG_CENTER_IMUX23_10", + "CFG_CENTER_NW2A0_17", + "CFG_CENTER_NE2A1_15", + "CFG_CENTER_BOT_USR_ACCESS_DATA9", + "CFG_CENTER_BLOCK_OUTS_B3_9", + "CFG_CENTER_SW4A0_17", + "CFG_CENTER_SE2A0_3", + "CFG_CENTER_NW2A1_2", + "CFG_CENTER_NW4END0_10", + "CFG_CENTER_BLOCK_OUTS_B1_15", + "CFG_CENTER_WW4B0_16", + "CFG_CENTER_BLOCK_OUTS_B3_7", + "CFG_CENTER_LOGIC_OUTS_B9_8", + "CFG_CENTER_IMUX4_11", + "CFG_CENTER_IMUX11_18", + "CFG_CENTER_NE2A3_11", + "CFG_CENTER_WW4C3_5", + "CFG_CENTER_BYP2_0", + "CFG_CENTER_EE2A0_16", + "CFG_CENTER_NE2A1_19", + "CFG_CENTER_EL1BEG0_9", + "CFG_CENTER_BLOCK_OUTS_B2_13", + "CFG_CENTER_BYP4_12", + "CFG_CENTER_IMUX47_3", + "CFG_CENTER_IMUX25_17", + "CFG_CENTER_EE4C2_2", + "CFG_CENTER_LOGIC_OUTS_B16_2", + "CFG_CENTER_LH7_18", + "CFG_CENTER_FAN0_14", + "CFG_CENTER_FAN6_3", + "CFG_CENTER_LOGIC_OUTS_B8_12", + "CFG_CENTER_SE4BEG2_4", + "CFG_CENTER_EE4B3_15", + "CFG_CENTER_WW4B2_6", + "CFG_CENTER_SE4C0_15", + "CFG_CENTER_NE4C2_19", + "CFG_CENTER_NE4C3_5", + "CFG_CENTER_EE4B2_6", + "CFG_CENTER_LOGIC_OUTS_B18_0", + "CFG_CENTER_IMUX23_15", + "CFG_CENTER_LOGIC_OUTS_B5_2", + "CFG_CENTER_BLOCK_OUTS_B1_19", + "CFG_CENTER_NW4A3_1", + "CFG_CENTER_SE4C2_10", + "CFG_CENTER_WW4B2_18", + "CFG_CENTER_SE4C1_19", + "CFG_CENTER_WR1END3_9", + "CFG_CENTER_EE4C2_19", + "CFG_CENTER_IMUX16_11", + "CFG_CENTER_EE4A2_2", + "CFG_CENTER_ER1BEG0_12", + "CFG_CENTER_SE2A1_0", + "CFG_CENTER_IMUX11_12", + "CFG_CENTER_CTRL1_10", + "CFG_CENTER_FAN7_4", + "CFG_CENTER_IMUX47_12", + "CFG_CENTER_WW4A2_10", + "CFG_CENTER_NW4A3_7", + "CFG_CENTER_SE4C3_17", + "CFG_CENTER_EL1BEG2_4", + "CFG_CENTER_WR1END2_11", + "CFG_CENTER_IMUX0_9", + "CFG_CENTER_NE4C3_19", + "CFG_CENTER_BYP6_19", + "CFG_CENTER_NE4BEG2_16", + "CFG_CENTER_LOGIC_OUTS_B11_18", + "CFG_CENTER_EE4C1_3", + "CFG_CENTER_WR1END3_1", + "CFG_CENTER_IMUX36_10", + "CFG_CENTER_IMUX47_11", + "CFG_CENTER_IMUX38_12", + "CFG_CENTER_IMUX13_0", + "CFG_CENTER_WW4B0_5", + "CFG_CENTER_CTRL0_8", + "CFG_CENTER_WW4END0_15", + "CFG_CENTER_WW4A0_9", + "CFG_CENTER_BYP6_4", + "CFG_CENTER_BLOCK_OUTS_B0_19", + "CFG_CENTER_SE2A2_9", + "CFG_CENTER_NW2A3_2", + "CFG_CENTER_LH8_10", + "CFG_CENTER_SE4C0_9", + "CFG_CENTER_IMUX20_4", + "CFG_CENTER_WW4C1_0", + "CFG_CENTER_BYP1_9", + "CFG_CENTER_IMUX47_8", + "CFG_CENTER_EE2BEG0_0", + "CFG_CENTER_LOGIC_OUTS_B12_13", + "CFG_CENTER_IMUX22_4", + "CFG_CENTER_IMUX15_4", + "CFG_CENTER_SW2A3_11", + "CFG_CENTER_NW2A3_1", + "CFG_CENTER_IMUX33_0", + "CFG_CENTER_IMUX13_3", + "CFG_CENTER_EL1BEG2_15", + "CFG_CENTER_WW2END0_11", + "CFG_CENTER_EL1BEG3_15", + "CFG_CENTER_BYP6_1", + "CFG_CENTER_EE2A2_17", + "CFG_CENTER_SW2A1_9", + "CFG_CENTER_ER1BEG2_6", + "CFG_CENTER_EE2BEG1_1", + "CFG_CENTER_LH1_11", + "CFG_CENTER_IMUX3_7", + "CFG_CENTER_EE4B3_17", + "CFG_CENTER_NW2A1_13", + "CFG_CENTER_LH12_8", + "CFG_CENTER_NE4C1_6", + "CFG_CENTER_SW2A0_15", + "CFG_CENTER_SW2A3_14", + "CFG_CENTER_IMUX17_14", + "CFG_CENTER_BYP0_5", + "CFG_CENTER_EL1BEG1_13", + "CFG_CENTER_WW2A0_13", + "CFG_CENTER_SE2A0_0", + "CFG_CENTER_SE2A0_9", + "CFG_CENTER_WR1END0_2", + "CFG_CENTER_EE4C1_13", + "CFG_CENTER_EL1BEG1_1", + "CFG_CENTER_NW4END1_17", + "CFG_CENTER_LOGIC_OUTS_B20_12", + "CFG_CENTER_LOGIC_OUTS_B6_3", + "CFG_CENTER_LOGIC_OUTS_B21_17", + "CFG_CENTER_WR1END2_5", + "CFG_CENTER_LOGIC_OUTS_B0_18", + "CFG_CENTER_IMUX7_15", + "CFG_CENTER_SW4END0_4", + "CFG_CENTER_IMUX6_15", + "CFG_CENTER_IMUX43_9", + "CFG_CENTER_NE4C3_10", + "CFG_CENTER_EE4A0_15", + "CFG_CENTER_IMUX18_0", + "CFG_CENTER_WW4C3_14", + "CFG_CENTER_CLK1_1", + "CFG_CENTER_LH1_6", + "CFG_CENTER_WL1END3_15", + "CFG_CENTER_SW4A1_15", + "CFG_CENTER_EE4C3_2", + "CFG_CENTER_SE4BEG0_1", + "CFG_CENTER_IMUX30_7", + "CFG_CENTER_FAN1_16", + "CFG_CENTER_WW4END3_18", + "CFG_CENTER_LH11_6", + "CFG_CENTER_LH3_3", + "CFG_CENTER_IMUX4_5", + "CFG_CENTER_IMUX13_1", + "CFG_CENTER_SE4C3_4", + "CFG_CENTER_CLK1_7", + "CFG_CENTER_NW4A1_18", + "CFG_CENTER_IMUX22_16", + "CFG_CENTER_EE4BEG0_1", + "CFG_CENTER_WW2A1_10", + "CFG_CENTER_LOGIC_OUTS_B15_7", + "CFG_CENTER_IMUX30_12", + "CFG_CENTER_IMUX1_13", + "CFG_CENTER_LOGIC_OUTS_B22_6", + "CFG_CENTER_SE4C1_18", + "CFG_CENTER_NW2A0_4", + "CFG_CENTER_IMUX19_0", + "CFG_CENTER_IMUX39_19", + "CFG_CENTER_NW4A3_14", + "CFG_CENTER_EE4A0_19", + "CFG_CENTER_IMUX28_3", + "CFG_CENTER_EE2A2_3", + "CFG_CENTER_LOGIC_OUTS_B20_19", + "CFG_CENTER_NW2A1_0", + "CFG_CENTER_IMUX28_9", + "CFG_CENTER_NW2A2_11", + "CFG_CENTER_IMUX4_13", + "CFG_CENTER_NW4END3_13", + "CFG_CENTER_NW4A2_4", + "CFG_CENTER_LOGIC_OUTS_B21_7", + "CFG_CENTER_FAN5_13", + "CFG_CENTER_ER1BEG0_17", + "CFG_CENTER_FAN5_2", + "CFG_CENTER_IMUX12_0", + "CFG_CENTER_IMUX32_18", + "CFG_CENTER_NW4A0_10", + "CFG_CENTER_SW2A0_13", + "CFG_CENTER_IMUX40_5", + "CFG_CENTER_IMUX22_17", + "CFG_CENTER_WW4B1_13", + "CFG_CENTER_IMUX19_19", + "CFG_CENTER_WW4END2_9", + "CFG_CENTER_SE4C0_14", + "CFG_CENTER_FAN6_13", + "CFG_CENTER_WW4A1_11", + "CFG_CENTER_SW2A2_11", + "CFG_CENTER_IMUX46_1", + "CFG_CENTER_BYP5_4", + "CFG_CENTER_WW2END1_13", + "CFG_CENTER_NE2A3_19", + "CFG_CENTER_NW4END2_7", + "CFG_CENTER_WW2A1_7", + "CFG_CENTER_NE2A2_8", + "CFG_CENTER_SW4END2_14", + "CFG_CENTER_EE2BEG2_1", + "CFG_CENTER_SW4A3_15", + "CFG_CENTER_WW4B0_17", + "CFG_CENTER_SW2A3_19", + "CFG_CENTER_LH11_1", + "CFG_CENTER_EE4BEG3_4", + "CFG_CENTER_SW2A0_4", + "CFG_CENTER_IMUX3_6", + "CFG_CENTER_LOGIC_OUTS_B18_9", + "CFG_CENTER_WW4A3_9", + "CFG_CENTER_SE4C2_16", + "CFG_CENTER_IMUX25_8", + "CFG_CENTER_LOGIC_OUTS_B5_9", + "CFG_CENTER_LOGIC_OUTS_B22_2", + "CFG_CENTER_IMUX8_4", + "CFG_CENTER_ER1BEG0_14", + "CFG_CENTER_EL1BEG1_11", + "CFG_CENTER_IMUX46_7", + "CFG_CENTER_NW4END1_18", + "CFG_CENTER_EE4B0_9", + "CFG_CENTER_NW4A1_16", + "CFG_CENTER_SE4BEG1_3", + "CFG_CENTER_EL1BEG3_10", + "CFG_CENTER_LH5_12", + "CFG_CENTER_IMUX7_19", + "CFG_CENTER_LOGIC_OUTS_B23_10", + "CFG_CENTER_BYP5_6", + "CFG_CENTER_IMUX28_19", + "CFG_CENTER_BYP4_16", + "CFG_CENTER_IMUX26_19", + "CFG_CENTER_EE4B1_17", + "CFG_CENTER_NE4C0_10", + "CFG_CENTER_IMUX17_12", + "CFG_CENTER_BYP1_1", + "CFG_CENTER_IMUX34_3", + "CFG_CENTER_SW4END0_16", + "CFG_CENTER_BLOCK_OUTS_B2_10", + "CFG_CENTER_LOGIC_OUTS_B12_14", + "CFG_CENTER_LH7_16", + "CFG_CENTER_FAN3_3", + "CFG_CENTER_IMUX46_12", + "CFG_CENTER_SW4A1_11", + "CFG_CENTER_EE4C3_14", + "CFG_CENTER_LH10_10", + "CFG_CENTER_BYP3_19", + "CFG_CENTER_LH2_0", + "CFG_CENTER_NE4C2_2", + "CFG_CENTER_BYP0_15", + "CFG_CENTER_IMUX43_17", + "CFG_CENTER_EE4A0_10", + "CFG_CENTER_FAN5_4", + "CFG_CENTER_NE2A1_4", + "CFG_CENTER_EE2A3_17", + "CFG_CENTER_IMUX42_12", + "CFG_CENTER_EE4B3_13", + "CFG_CENTER_LOGIC_OUTS_B19_12", + "CFG_CENTER_LOGIC_OUTS_B5_17", + "CFG_CENTER_IMUX28_8", + "CFG_CENTER_SW2A2_2", + "CFG_CENTER_SW4END2_17", + "CFG_CENTER_IMUX37_0", + "CFG_CENTER_WW4C0_15", + "CFG_CENTER_NW4A0_11", + "CFG_CENTER_WW2A3_9", + "CFG_CENTER_LOGIC_OUTS_B18_4", + "CFG_CENTER_IMUX40_16", + "CFG_CENTER_IMUX35_2", + "CFG_CENTER_IMUX28_4", + "CFG_CENTER_WW4B3_18", + "CFG_CENTER_FAN2_10", + "CFG_CENTER_WW4A0_6", + "CFG_CENTER_WW4A2_19", + "CFG_CENTER_BYP2_11", + "CFG_CENTER_EE4BEG0_14", + "CFG_CENTER_IMUX17_2", + "CFG_CENTER_SW2A2_10", + "CFG_CENTER_WL1END3_13", + "CFG_CENTER_WL1END2_6", + "CFG_CENTER_WW4END0_17", + "CFG_CENTER_EE4BEG2_19", + "CFG_CENTER_EE4B0_1", + "CFG_CENTER_IMUX31_14", + "CFG_CENTER_NE4BEG3_3", + "CFG_CENTER_LOGIC_OUTS_B20_6", + "CFG_CENTER_FAN7_5", + "CFG_CENTER_LOGIC_OUTS_B17_11", + "CFG_CENTER_WL1END0_13", + "CFG_CENTER_EE4A2_9", + "CFG_CENTER_LH7_2", + "CFG_CENTER_IMUX27_7", + "CFG_CENTER_BYP4_4", + "CFG_CENTER_NE4C0_9", + "CFG_CENTER_IMUX4_4", + "CFG_CENTER_IMUX9_2", + "CFG_CENTER_NW4END0_13", + "CFG_CENTER_WL1END3_4", + "CFG_CENTER_IMUX14_2", + "CFG_CENTER_NW4A3_16", + "CFG_CENTER_IMUX42_1", + "CFG_CENTER_NW2A3_4", + "CFG_CENTER_SE2A1_8", + "CFG_CENTER_FAN1_11", + "CFG_CENTER_NW2A1_6", + "CFG_CENTER_IMUX35_18", + "CFG_CENTER_IMUX47_15", + "CFG_CENTER_FAN1_8", + "CFG_CENTER_IMUX22_9", + "CFG_CENTER_WW2END2_16", + "CFG_CENTER_SW2A2_17", + "CFG_CENTER_IMUX10_15", + "CFG_CENTER_BLOCK_OUTS_B0_14", + "CFG_CENTER_EE4C1_11", + "CFG_CENTER_IMUX9_1", + "CFG_CENTER_IMUX11_11", + "CFG_CENTER_SW4END0_3", + "CFG_CENTER_WL1END3_6", + "CFG_CENTER_EE4B2_2", + "CFG_CENTER_EE4A2_7", + "CFG_CENTER_WW4A3_17", + "CFG_CENTER_WW4C3_4", + "CFG_CENTER_NW4END1_9", + "CFG_CENTER_WL1END1_10", + "CFG_CENTER_WW4END0_13", + "CFG_CENTER_NW4END0_18", + "CFG_CENTER_FAN3_4", + "CFG_CENTER_EE4C0_4", + "CFG_CENTER_LOGIC_OUTS_B1_4", + "CFG_CENTER_IMUX35_3", + "CFG_CENTER_LH9_14", + "CFG_CENTER_SW2A1_19", + "CFG_CENTER_EL1BEG3_9", + "CFG_CENTER_NE2A1_0", + "CFG_CENTER_IMUX9_8", + "CFG_CENTER_WW4B2_5", + "CFG_CENTER_LH6_13", + "CFG_CENTER_BYP5_16", + "CFG_CENTER_LH7_6", + "CFG_CENTER_FAN0_5", + "CFG_CENTER_WL1END3_8", + "CFG_CENTER_EE2A0_5", + "CFG_CENTER_LH7_4", + "CFG_CENTER_WW2END3_2", + "CFG_CENTER_LOGIC_OUTS_B15_18", + "CFG_CENTER_WR1END3_5", + "CFG_CENTER_BYP5_9", + "CFG_CENTER_EE4A1_17", + "CFG_CENTER_SW4END0_14", + "CFG_CENTER_LH2_7", + "CFG_CENTER_LOGIC_OUTS_B8_19", + "CFG_CENTER_BYP3_17", + "CFG_CENTER_LH7_12", + "CFG_CENTER_EL1BEG1_6", + "CFG_CENTER_NE4BEG0_5", + "CFG_CENTER_WW2END1_10", + "CFG_CENTER_IMUX31_12", + "CFG_CENTER_BYP7_6", + "CFG_CENTER_EE4A1_13", + "CFG_CENTER_LH4_6", + "CFG_CENTER_EE4C1_16", + "CFG_CENTER_NW2A1_18", + "CFG_CENTER_IMUX3_9", + "CFG_CENTER_SE4BEG2_7", + "CFG_CENTER_IMUX31_7", + "CFG_CENTER_IMUX35_11", + "CFG_CENTER_SW4A3_19", + "CFG_CENTER_WR1END0_19", + "CFG_CENTER_NW4END2_0", + "CFG_CENTER_WW2A0_2", + "CFG_CENTER_EE4BEG0_5", + "CFG_CENTER_NW4END3_16", + "CFG_CENTER_IMUX23_0", + "CFG_CENTER_NE4C1_7", + "CFG_CENTER_EE2BEG0_12", + "CFG_CENTER_ER1BEG2_5", + "CFG_CENTER_WW2A3_3", + "CFG_CENTER_BYP1_11", + "CFG_CENTER_ER1BEG3_12", + "CFG_CENTER_IMUX4_18", + "CFG_CENTER_IMUX44_14", + "CFG_CENTER_WR1END3_18", + "CFG_CENTER_IMUX27_13", + "CFG_CENTER_FAN6_1", + "CFG_CENTER_WW4C0_11", + "CFG_CENTER_NE2A1_14", + "CFG_CENTER_SW4A2_3", + "CFG_CENTER_SE4BEG1_5", + "CFG_CENTER_IMUX31_18", + "CFG_CENTER_CLK0_6", + "CFG_CENTER_WW2END3_17", + "CFG_CENTER_IMUX42_7", + "CFG_CENTER_WW4A2_5", + "CFG_CENTER_FAN4_18", + "CFG_CENTER_EE2BEG2_18", + "CFG_CENTER_LOGIC_OUTS_B0_8", + "CFG_CENTER_WW4B3_2", + "CFG_CENTER_WR1END2_0", + "CFG_CENTER_LOGIC_OUTS_B12_11", + "CFG_CENTER_IMUX22_7", + "CFG_CENTER_LOGIC_OUTS_B6_15", + "CFG_CENTER_NE4C0_14", + "CFG_CENTER_EE4A3_3", + "CFG_CENTER_IMUX7_1", + "CFG_CENTER_NE4BEG0_12", + "CFG_CENTER_IMUX25_6", + "CFG_CENTER_WW4B0_2", + "CFG_CENTER_NW4END1_3", + "CFG_CENTER_WR1END2_17", + "CFG_CENTER_WW4END2_4", + "CFG_CENTER_WW2END0_10", + "CFG_CENTER_ER1BEG0_7", + "CFG_CENTER_NE4C0_15", + "CFG_CENTER_EE2BEG2_4", + "CFG_CENTER_FAN2_4", + "CFG_CENTER_WW4C2_8", + "CFG_CENTER_BLOCK_OUTS_B2_1", + "CFG_CENTER_IMUX23_3", + "CFG_CENTER_IMUX14_14", + "CFG_CENTER_EE2BEG2_9", + "CFG_CENTER_IMUX31_9", + "CFG_CENTER_LOGIC_OUTS_B10_3", + "CFG_CENTER_WW4C3_1", + "CFG_CENTER_WW4C0_17", + "CFG_CENTER_IMUX13_15", + "CFG_CENTER_IMUX41_10", + "CFG_CENTER_CTRL1_6", + "CFG_CENTER_ER1BEG1_5", + "CFG_CENTER_IMUX45_0", + "CFG_CENTER_WL1END1_6", + "CFG_CENTER_NE2A0_11", + "CFG_CENTER_IMUX17_8", + "CFG_CENTER_EE2A0_8", + "CFG_CENTER_EE4C1_1", + "CFG_CENTER_WL1END1_11", + "CFG_CENTER_LH9_11", + "CFG_CENTER_IMUX29_4", + "CFG_CENTER_IMUX20_0", + "CFG_CENTER_IMUX1_16", + "CFG_CENTER_IMUX12_13", + "CFG_CENTER_IMUX42_16", + "CFG_CENTER_IMUX1_6", + "CFG_CENTER_LH5_2", + "CFG_CENTER_SE2A2_14", + "CFG_CENTER_IMUX3_12", + "CFG_CENTER_NE4C3_4", + "CFG_CENTER_LOGIC_OUTS_B19_5", + "CFG_CENTER_SE4BEG0_19", + "CFG_CENTER_IMUX41_5", + "CFG_CENTER_FAN0_8", + "CFG_CENTER_IMUX8_13", + "CFG_CENTER_IMUX6_14", + "CFG_CENTER_NE4BEG0_9", + "CFG_CENTER_IMUX46_19", + "CFG_CENTER_NE2A2_19", + "CFG_CENTER_SE2A1_16", + "CFG_CENTER_IMUX14_12", + "CFG_CENTER_NW2A0_9", + "CFG_CENTER_IMUX32_1", + "CFG_CENTER_FAN7_0", + "CFG_CENTER_IMUX22_12", + "CFG_CENTER_IMUX34_12", + "CFG_CENTER_SW4END1_9", + "CFG_CENTER_FAN2_2", + "CFG_CENTER_IMUX44_10", + "CFG_CENTER_BYP0_3", + "CFG_CENTER_LH12_11", + "CFG_CENTER_IMUX14_8", + "CFG_CENTER_LH2_8", + "CFG_CENTER_IMUX1_12", + "CFG_CENTER_NW4END2_11", + "CFG_CENTER_EE2A1_13", + "CFG_CENTER_EE2BEG3_18", + "CFG_CENTER_LH6_4", + "CFG_CENTER_SW2A3_1", + "CFG_CENTER_WW4A1_12", + "CFG_CENTER_SE4C0_19", + "CFG_CENTER_SW4A1_7", + "CFG_CENTER_IMUX13_7", + "CFG_CENTER_IMUX6_16", + "CFG_CENTER_IMUX39_12", + "CFG_CENTER_FAN0_16", + "CFG_CENTER_WW4END2_16", + "CFG_CENTER_FAN6_4", + "CFG_CENTER_NE4BEG1_0", + "CFG_CENTER_SE2A0_19", + "CFG_CENTER_SW4END2_6", + "CFG_CENTER_WW4END2_5", + "CFG_CENTER_WW2END0_18", + "CFG_CENTER_IMUX46_18", + "CFG_CENTER_LOGIC_OUTS_B5_16", + "CFG_CENTER_IMUX39_5", + "CFG_CENTER_BYP7_8", + "CFG_CENTER_LH6_12", + "CFG_CENTER_IMUX20_13", + "CFG_CENTER_SW4A2_2", + "CFG_CENTER_BYP0_7", + "CFG_CENTER_LOGIC_OUTS_B9_11", + "CFG_CENTER_WW4C2_11", + "CFG_CENTER_LOGIC_OUTS_B20_17", + "CFG_CENTER_CTRL1_16", + "CFG_CENTER_SW4END2_1", + "CFG_CENTER_IMUX40_1", + "CFG_CENTER_ER1BEG2_2", + "CFG_CENTER_LH2_19", + "CFG_CENTER_FAN1_1", + "CFG_CENTER_NE2A1_16", + "CFG_CENTER_SW4A2_11", + "CFG_CENTER_IMUX45_4", + "CFG_CENTER_LH8_15", + "CFG_CENTER_IMUX18_14", + "CFG_CENTER_LOGIC_OUTS_B13_11", + "CFG_CENTER_LOGIC_OUTS_B17_5", + "CFG_CENTER_LOGIC_OUTS_B3_12", + "CFG_CENTER_SW4END3_5", + "CFG_CENTER_IMUX32_9", + "CFG_CENTER_NW4A3_5", + "CFG_CENTER_EE4C1_0", + "CFG_CENTER_BLOCK_OUTS_B0_10", + "CFG_CENTER_NW2A2_15", + "CFG_CENTER_SE2A1_2", + "CFG_CENTER_WW4END0_16", + "CFG_CENTER_LH7_3", + "CFG_CENTER_EE2BEG1_8", + "CFG_CENTER_LH12_5", + "CFG_CENTER_LOGIC_OUTS_B16_3", + "CFG_CENTER_IMUX43_12", + "CFG_CENTER_WW2END3_18", + "CFG_CENTER_WR1END3_19", + "CFG_CENTER_SW4END1_1", + "CFG_CENTER_NW2A1_10", + "CFG_CENTER_EE4BEG2_11", + "CFG_CENTER_WL1END1_5", + "CFG_CENTER_IMUX47_2", + "CFG_CENTER_IMUX19_12", + "CFG_CENTER_WW2END2_12", + "CFG_CENTER_IMUX33_13", + "CFG_CENTER_LH2_13", + "CFG_CENTER_IMUX12_5", + "CFG_CENTER_IMUX22_6", + "CFG_CENTER_WW2A1_16", + "CFG_CENTER_IMUX36_4", + "CFG_CENTER_IMUX47_14", + "CFG_CENTER_LOGIC_OUTS_B17_17", + "CFG_CENTER_NE4C0_1", + "CFG_CENTER_IMUX6_18", + "CFG_CENTER_LOGIC_OUTS_B19_13", + "CFG_CENTER_WW4END2_6", + "CFG_CENTER_BLOCK_OUTS_B2_2", + "CFG_CENTER_BOT_USR_ACCESS_DATA3", + "CFG_CENTER_SE2A1_9", + "CFG_CENTER_IMUX26_6", + "CFG_CENTER_IMUX3_13", + "CFG_CENTER_NE2A1_2", + "CFG_CENTER_IMUX1_11", + "CFG_CENTER_SE4C1_9", + "CFG_CENTER_SW4A0_2", + "CFG_CENTER_SW4END2_5", + "CFG_CENTER_IMUX36_14", + "CFG_CENTER_WR1END2_19", + "CFG_CENTER_IMUX1_15", + "CFG_CENTER_CLK0_1", + "CFG_CENTER_IMUX37_6", + "CFG_CENTER_IMUX33_17", + "CFG_CENTER_WW2A3_0", + "CFG_CENTER_EE2BEG2_7", + "CFG_CENTER_ER1BEG1_16", + "CFG_CENTER_LOGIC_OUTS_B8_9", + "CFG_CENTER_NW2A0_8", + "CFG_CENTER_IMUX33_15", + "CFG_CENTER_SE2A2_15", + "CFG_CENTER_IMUX4_3", + "CFG_CENTER_IMUX16_5", + "CFG_CENTER_NE4C2_13", + "CFG_CENTER_NW4A1_19", + "CFG_CENTER_EL1BEG1_17", + "CFG_CENTER_NW2A2_5", + "CFG_CENTER_SE2A0_5", + "CFG_CENTER_FAN6_7", + "CFG_CENTER_IMUX13_18", + "CFG_CENTER_NW2A2_8", + "CFG_CENTER_LH2_5", + "CFG_CENTER_CLK0_16", + "CFG_CENTER_IMUX5_16", + "CFG_CENTER_IMUX30_16", + "CFG_CENTER_EE2BEG2_6", + "CFG_CENTER_IMUX17_18", + "CFG_CENTER_LH8_0", + "CFG_CENTER_IMUX39_8", + "CFG_CENTER_WW4B3_14", + "CFG_CENTER_ER1BEG3_4", + "CFG_CENTER_LOGIC_OUTS_B15_2", + "CFG_CENTER_LOGIC_OUTS_B19_11", + "CFG_CENTER_IMUX17_19", + "CFG_CENTER_WW2END1_8", + "CFG_CENTER_WW4A3_0", + "CFG_CENTER_LH11_13", + "CFG_CENTER_EE2A1_15", + "CFG_CENTER_ER1BEG2_10", + "CFG_CENTER_LOGIC_OUTS_B1_17", + "CFG_CENTER_WW2END0_16", + "CFG_CENTER_NW4END2_16", + "CFG_CENTER_EE4A2_19", + "CFG_CENTER_WW4END0_18", + "CFG_CENTER_NE4C0_7", + "CFG_CENTER_EE4B2_15", + "CFG_CENTER_IMUX25_4", + "CFG_CENTER_BLOCK_OUTS_B1_6", + "CFG_CENTER_CTRL0_13", + "CFG_CENTER_FAN7_2", + "CFG_CENTER_NE4BEG2_6", + "CFG_CENTER_LOGIC_OUTS_B5_11", + "CFG_CENTER_NE2A3_3", + "CFG_CENTER_LOGIC_OUTS_B17_8", + "CFG_CENTER_SW4END0_19", + "CFG_CENTER_FAN1_10", + "CFG_CENTER_WW2A2_5", + "CFG_CENTER_IMUX26_4", + "CFG_CENTER_WW4A2_14", + "CFG_CENTER_EE4A1_19", + "CFG_CENTER_WW4B2_9", + "CFG_CENTER_BLOCK_OUTS_B3_3", + "CFG_CENTER_WR1END1_18", + "CFG_CENTER_IMUX28_16", + "CFG_CENTER_FAN3_7", + "CFG_CENTER_WW4END0_12", + "CFG_CENTER_WW2A0_14", + "CFG_CENTER_EE2A2_9", + "CFG_CENTER_BYP1_10", + "CFG_CENTER_WW2A3_1", + "CFG_CENTER_IMUX43_5", + "CFG_CENTER_WW4B1_10", + "CFG_CENTER_WW4A0_13", + "CFG_CENTER_EE2A1_5", + "CFG_CENTER_BYP3_12", + "CFG_CENTER_IMUX27_16", + "CFG_CENTER_EL1BEG2_6", + "CFG_CENTER_LH10_17", + "CFG_CENTER_LOGIC_OUTS_B3_2", + "CFG_CENTER_SE2A0_18", + "CFG_CENTER_LOGIC_OUTS_B0_3", + "CFG_CENTER_EL1BEG1_10", + "CFG_CENTER_IMUX3_3", + "CFG_CENTER_ER1BEG3_0", + "CFG_CENTER_WW4C2_4", + "CFG_CENTER_EE2BEG1_17", + "CFG_CENTER_WW4A0_3", + "CFG_CENTER_SE2A1_7", + "CFG_CENTER_IMUX42_10", + "CFG_CENTER_LH10_6", + "CFG_CENTER_WR1END1_15", + "CFG_CENTER_SW2A1_10", + "CFG_CENTER_BYP0_17" + ], + "pips": { + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA4->CFG_CENTER_LOGIC_OUTS_B15_19": { + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA12->CFG_CENTER_LOGIC_OUTS_B23_19": { + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA13->CFG_CENTER_LOGIC_OUTS_B10_19": { + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA10->CFG_CENTER_LOGIC_OUTS_B21_19": { + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA10", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA9->CFG_CENTER_LOGIC_OUTS_B20_19": { + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA9", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA7->CFG_CENTER_LOGIC_OUTS_B18_19": { + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA7", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA11->CFG_CENTER_LOGIC_OUTS_B22_19": { + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA11", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA3->CFG_CENTER_LOGIC_OUTS_B14_19": { + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA3", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA2->CFG_CENTER_LOGIC_OUTS_B13_19": { + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA2", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA14->CFG_CENTER_LOGIC_OUTS_B11_19": { + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA14", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA8->CFG_CENTER_LOGIC_OUTS_B19_19": { + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA6->CFG_CENTER_LOGIC_OUTS_B17_19": { + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA6", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA5->CFG_CENTER_LOGIC_OUTS_B16_19": { + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_19", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CFG_CENTER_MID.json b/kintex7/tile_type_CFG_CENTER_MID.json new file mode 100644 index 0000000..eacbf8f --- /dev/null +++ b/kintex7/tile_type_CFG_CENTER_MID.json @@ -0,0 +1,7187 @@ +{ + "tile_type": "CFG_CENTER_MID", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "USR_ACCESS", + "type": "USR_ACCESS", + "site_pins": { + "DATA27": "CFG_CENTER_USR_ACCESS_DATA27", + "DATAVALID": "CFG_CENTER_USR_ACCESS_DATAVALID", + "DATA8": "CFG_CENTER_USR_ACCESS_DATA8", + "DATA10": "CFG_CENTER_USR_ACCESS_DATA10", + "DATA6": "CFG_CENTER_USR_ACCESS_DATA6", + "DATA26": "CFG_CENTER_USR_ACCESS_DATA26", + "DATA29": "CFG_CENTER_USR_ACCESS_DATA29", + "DATA28": "CFG_CENTER_USR_ACCESS_DATA28", + "DATA19": "CFG_CENTER_USR_ACCESS_DATA19", + "DATA20": "CFG_CENTER_USR_ACCESS_DATA20", + "DATA25": "CFG_CENTER_USR_ACCESS_DATA25", + "DATA18": "CFG_CENTER_USR_ACCESS_DATA18", + "DATA4": "CFG_CENTER_USR_ACCESS_DATA4", + "DATA21": "CFG_CENTER_USR_ACCESS_DATA21", + "DATA15": "CFG_CENTER_USR_ACCESS_DATA15", + "DATA2": "CFG_CENTER_USR_ACCESS_DATA2", + "DATA17": "CFG_CENTER_USR_ACCESS_DATA17", + "DATA0": "CFG_CENTER_USR_ACCESS_DATA0", + "DATA7": "CFG_CENTER_USR_ACCESS_DATA7", + "DATA16": "CFG_CENTER_USR_ACCESS_DATA16", + "DATA13": "CFG_CENTER_USR_ACCESS_DATA13", + "DATA22": "CFG_CENTER_USR_ACCESS_DATA22", + "CFGCLK": "CFG_CENTER_USR_ACCESS_CFGCLK", + "DATA31": "CFG_CENTER_USR_ACCESS_DATA31", + "DATA12": "CFG_CENTER_USR_ACCESS_DATA12", + "DATA23": "CFG_CENTER_USR_ACCESS_DATA23", + "DATA5": "CFG_CENTER_USR_ACCESS_DATA5", + "DATA30": "CFG_CENTER_USR_ACCESS_DATA30", + "DATA24": "CFG_CENTER_USR_ACCESS_DATA24", + "DATA3": "CFG_CENTER_USR_ACCESS_DATA3", + "DATA1": "CFG_CENTER_USR_ACCESS_DATA1", + "DATA14": "CFG_CENTER_USR_ACCESS_DATA14", + "DATA9": "CFG_CENTER_USR_ACCESS_DATA9", + "DATA11": "CFG_CENTER_USR_ACCESS_DATA11" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "BSCAN", + "type": "BSCAN", + "site_pins": { + "TMS": "CFG_CENTER_BSCAN1_TMS", + "TDO": "CFG_CENTER_BSCAN1_TDO", + "DRCK": "CFG_CENTER_BSCAN1_DRCK", + "RESET": "CFG_CENTER_BSCAN1_RESET", + "TCK": "CFG_CENTER_BSCAN1_TCK", + "SHIFT": "CFG_CENTER_BSCAN1_SHIFT", + "SEL": "CFG_CENTER_BSCAN1_SEL", + "TDI": "CFG_CENTER_BSCAN1_TDI", + "UPDATE": "CFG_CENTER_BSCAN1_UPDATE", + "CAPTURE": "CFG_CENTER_BSCAN1_CAPTURE", + "RUNTEST": "CFG_CENTER_BSCAN1_RUNTEST" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "BSCAN", + "type": "BSCAN", + "site_pins": { + "TMS": "CFG_CENTER_BSCAN2_TMS", + "TDO": "CFG_CENTER_BSCAN2_TDO", + "DRCK": "CFG_CENTER_BSCAN2_DRCK", + "RESET": "CFG_CENTER_BSCAN2_RESET", + "TCK": "CFG_CENTER_BSCAN2_TCK", + "SHIFT": "CFG_CENTER_BSCAN2_SHIFT", + "SEL": "CFG_CENTER_BSCAN2_SEL", + "TDI": "CFG_CENTER_BSCAN2_TDI", + "UPDATE": "CFG_CENTER_BSCAN2_UPDATE", + "CAPTURE": "CFG_CENTER_BSCAN2_CAPTURE", + "RUNTEST": "CFG_CENTER_BSCAN2_RUNTEST" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "ICAP", + "type": "ICAP", + "site_pins": { + "I10": "CFG_CENTER_ICAP0_I10", + "I29": "CFG_CENTER_ICAP0_I29", + "CSIB": "CFG_CENTER_ICAP0_CSIB", + "I27": "CFG_CENTER_ICAP0_I27", + "O19": "CFG_CENTER_ICAP0_O19", + "O11": "CFG_CENTER_ICAP0_O11", + "RDWRB": "CFG_CENTER_ICAP0_RDWRB", + "O30": "CFG_CENTER_ICAP0_O30", + "I14": "CFG_CENTER_ICAP0_I14", + "I7": "CFG_CENTER_ICAP0_I7", + "I20": "CFG_CENTER_ICAP0_I20", + "I13": "CFG_CENTER_ICAP0_I13", + "I26": "CFG_CENTER_ICAP0_I26", + "O31": "CFG_CENTER_ICAP0_O31", + "I23": "CFG_CENTER_ICAP0_I23", + "O5": "CFG_CENTER_ICAP0_O5", + "O17": "CFG_CENTER_ICAP0_O17", + "I4": "CFG_CENTER_ICAP0_I4", + "O0": "CFG_CENTER_ICAP0_O0", + "I15": "CFG_CENTER_ICAP0_I15", + "O25": "CFG_CENTER_ICAP0_O25", + "O4": "CFG_CENTER_ICAP0_O4", + "I24": "CFG_CENTER_ICAP0_I24", + "I3": "CFG_CENTER_ICAP0_I3", + "O6": "CFG_CENTER_ICAP0_O6", + "I31": "CFG_CENTER_ICAP0_I31", + "O15": "CFG_CENTER_ICAP0_O15", + "O24": "CFG_CENTER_ICAP0_O24", + "O21": "CFG_CENTER_ICAP0_O21", + "I5": "CFG_CENTER_ICAP0_I5", + "I25": "CFG_CENTER_ICAP0_I25", + "I21": "CFG_CENTER_ICAP0_I21", + "O27": "CFG_CENTER_ICAP0_O27", + "O22": "CFG_CENTER_ICAP0_O22", + "I9": "CFG_CENTER_ICAP0_I9", + "I12": "CFG_CENTER_ICAP0_I12", + "I2": "CFG_CENTER_ICAP0_I2", + "I16": "CFG_CENTER_ICAP0_I16", + "I22": "CFG_CENTER_ICAP0_I22", + "I11": "CFG_CENTER_ICAP0_I11", + "I1": "CFG_CENTER_ICAP0_I1", + "O7": "CFG_CENTER_ICAP0_O7", + "O8": "CFG_CENTER_ICAP0_O8", + "I19": "CFG_CENTER_ICAP0_I19", + "O12": "CFG_CENTER_ICAP0_O12", + "O13": "CFG_CENTER_ICAP0_O13", + "I6": "CFG_CENTER_ICAP0_I6", + "O23": "CFG_CENTER_ICAP0_O23", + "O1": "CFG_CENTER_ICAP0_O1", + "O29": "CFG_CENTER_ICAP0_O29", + "I17": "CFG_CENTER_ICAP0_I17", + "I30": "CFG_CENTER_ICAP0_I30", + "O3": "CFG_CENTER_ICAP0_O3", + "O14": "CFG_CENTER_ICAP0_O14", + "O20": "CFG_CENTER_ICAP0_O20", + "O26": "CFG_CENTER_ICAP0_O26", + "I0": "CFG_CENTER_ICAP0_I0", + "I8": "CFG_CENTER_ICAP0_I8", + "O16": "CFG_CENTER_ICAP0_O16", + "O28": "CFG_CENTER_ICAP0_O28", + "I28": "CFG_CENTER_ICAP0_I28", + "CLK": "CFG_CENTER_ICAP0_CLK", + "I18": "CFG_CENTER_ICAP0_I18", + "O9": "CFG_CENTER_ICAP0_O9", + "O18": "CFG_CENTER_ICAP0_O18", + "O2": "CFG_CENTER_ICAP0_O2", + "O10": "CFG_CENTER_ICAP0_O10" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "FRAME_ECC", + "type": "FRAME_ECC", + "site_pins": { + "SYNDROMEVALID": "CFG_CENTER_FRAME_ECC_SYNDROMEVALID", + "FAR3": "CFG_CENTER_FRAME_ECC_FAR3", + "SYNBIT2": "CFG_CENTER_FRAME_ECC_SYNBIT2", + "FAR14": "CFG_CENTER_FRAME_ECC_FAR14", + "FAR6": "CFG_CENTER_FRAME_ECC_FAR6", + "SYNWORD6": "CFG_CENTER_FRAME_ECC_SYNWORD6", + "FAR0": "CFG_CENTER_FRAME_ECC_FAR0", + "SYNWORD4": "CFG_CENTER_FRAME_ECC_SYNWORD4", + "FAR16": "CFG_CENTER_FRAME_ECC_FAR16", + "SYNDROME4": "CFG_CENTER_FRAME_ECC_SYNDROME4", + "SYNWORD5": "CFG_CENTER_FRAME_ECC_SYNWORD5", + "FAR8": "CFG_CENTER_FRAME_ECC_FAR8", + "SYNDROME3": "CFG_CENTER_FRAME_ECC_SYNDROME3", + "FAR2": "CFG_CENTER_FRAME_ECC_FAR2", + "FAR5": "CFG_CENTER_FRAME_ECC_FAR5", + "SYNBIT0": "CFG_CENTER_FRAME_ECC_SYNBIT0", + "SYNDROME9": "CFG_CENTER_FRAME_ECC_SYNDROME9", + "SYNDROME6": "CFG_CENTER_FRAME_ECC_SYNDROME6", + "SYNDROME5": "CFG_CENTER_FRAME_ECC_SYNDROME5", + "FAR17": "CFG_CENTER_FRAME_ECC_FAR17", + "FAR20": "CFG_CENTER_FRAME_ECC_FAR20", + "SYNDROME2": "CFG_CENTER_FRAME_ECC_SYNDROME2", + "FAR23": "CFG_CENTER_FRAME_ECC_FAR23", + "FAR10": "CFG_CENTER_FRAME_ECC_FAR10", + "SYNDROME10": "CFG_CENTER_FRAME_ECC_SYNDROME10", + "SYNWORD2": "CFG_CENTER_FRAME_ECC_SYNWORD2", + "SYNBIT4": "CFG_CENTER_FRAME_ECC_SYNBIT4", + "FAR13": "CFG_CENTER_FRAME_ECC_FAR13", + "FAR15": "CFG_CENTER_FRAME_ECC_FAR15", + "FAR7": "CFG_CENTER_FRAME_ECC_FAR7", + "ECCERRORSINGLE": "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE", + "SYNDROME11": "CFG_CENTER_FRAME_ECC_SYNDROME11", + "FAR25": "CFG_CENTER_FRAME_ECC_FAR25", + "FAR1": "CFG_CENTER_FRAME_ECC_FAR1", + "SYNBIT1": "CFG_CENTER_FRAME_ECC_SYNBIT1", + "FAR21": "CFG_CENTER_FRAME_ECC_FAR21", + "SYNDROME0": "CFG_CENTER_FRAME_ECC_SYNDROME0", + "FAR12": "CFG_CENTER_FRAME_ECC_FAR12", + "FAR19": "CFG_CENTER_FRAME_ECC_FAR19", + "FAR9": "CFG_CENTER_FRAME_ECC_FAR9", + "SYNDROME7": "CFG_CENTER_FRAME_ECC_SYNDROME7", + "SYNBIT3": "CFG_CENTER_FRAME_ECC_SYNBIT3", + "SYNWORD1": "CFG_CENTER_FRAME_ECC_SYNWORD1", + "FAR22": "CFG_CENTER_FRAME_ECC_FAR22", + "FAR24": "CFG_CENTER_FRAME_ECC_FAR24", + "FAR11": "CFG_CENTER_FRAME_ECC_FAR11", + "SYNWORD3": "CFG_CENTER_FRAME_ECC_SYNWORD3", + "SYNDROME12": "CFG_CENTER_FRAME_ECC_SYNDROME12", + "CRCERROR": "CFG_CENTER_FRAME_ECC_CRCERROR", + "FAR18": "CFG_CENTER_FRAME_ECC_FAR18", + "ECCERROR": "CFG_CENTER_FRAME_ECC_ECCERROR", + "SYNWORD0": "CFG_CENTER_FRAME_ECC_SYNWORD0", + "SYNDROME1": "CFG_CENTER_FRAME_ECC_SYNDROME1", + "SYNDROME8": "CFG_CENTER_FRAME_ECC_SYNDROME8", + "FAR4": "CFG_CENTER_FRAME_ECC_FAR4" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "STARTUP", + "type": "STARTUP", + "site_pins": { + "USRCCLKO": "CFG_CENTER_STARTUP_USRCCLKO", + "PREQ": "CFG_CENTER_STARTUP_PREQ", + "GTS": "CFG_CENTER_STARTUP_GTS", + "CLK": "CFG_CENTER_STARTUP_CLK", + "USRCCLKTS": "CFG_CENTER_STARTUP_USRCCLKTS", + "PACK": "CFG_CENTER_STARTUP_PACK", + "GSR": "CFG_CENTER_STARTUP_GSR", + "KEYCLEARB": "CFG_CENTER_STARTUP_KEYCLEARB", + "USRDONEO": "CFG_CENTER_STARTUP_USRDONEO", + "USRDONETS": "CFG_CENTER_STARTUP_USRDONETS", + "EOS": "CFG_CENTER_STARTUP_EOS", + "CFGMCLK": "CFG_CENTER_STARTUP_CFGMCLK", + "CFGCLK": "CFG_CENTER_STARTUP_CFGCLK" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "CAPTURE", + "type": "CAPTURE", + "site_pins": { + "CAP": "CFG_CENTER_CAPTURE_CAP", + "CLK": "CFG_CENTER_CAPTURE_CLK" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "DCIRESET", + "type": "DCIRESET", + "site_pins": { + "RST": "CFG_CENTER_DCIRESET_RST", + "LOCKED": "CFG_CENTER_DCIRESET_LOCKED" + }, + "x_coord": 0 + }, + { + "y_coord": 2, + "name": "X0Y2", + "prefix": "BSCAN", + "type": "BSCAN", + "site_pins": { + "TMS": "CFG_CENTER_BSCAN3_TMS", + "TDO": "CFG_CENTER_BSCAN3_TDO", + "DRCK": "CFG_CENTER_BSCAN3_DRCK", + "RESET": "CFG_CENTER_BSCAN3_RESET", + "TCK": "CFG_CENTER_BSCAN3_TCK", + "SHIFT": "CFG_CENTER_BSCAN3_SHIFT", + "SEL": "CFG_CENTER_BSCAN3_SEL", + "TDI": "CFG_CENTER_BSCAN3_TDI", + "UPDATE": "CFG_CENTER_BSCAN3_UPDATE", + "CAPTURE": "CFG_CENTER_BSCAN3_CAPTURE", + "RUNTEST": "CFG_CENTER_BSCAN3_RUNTEST" + }, + "x_coord": 0 + }, + { + "y_coord": 3, + "name": "X0Y3", + "prefix": "BSCAN", + "type": "BSCAN", + "site_pins": { + "TMS": "CFG_CENTER_BSCAN4_TMS", + "TDO": "CFG_CENTER_BSCAN4_TDO", + "DRCK": "CFG_CENTER_BSCAN4_DRCK", + "RESET": "CFG_CENTER_BSCAN4_RESET", + "TCK": "CFG_CENTER_BSCAN4_TCK", + "SHIFT": "CFG_CENTER_BSCAN4_SHIFT", + "SEL": "CFG_CENTER_BSCAN4_SEL", + "TDI": "CFG_CENTER_BSCAN4_TDI", + "UPDATE": "CFG_CENTER_BSCAN4_UPDATE", + "CAPTURE": "CFG_CENTER_BSCAN4_CAPTURE", + "RUNTEST": "CFG_CENTER_BSCAN4_RUNTEST" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "ICAP", + "type": "ICAP", + "site_pins": { + "I10": "CFG_CENTER_ICAP1_I10", + "I29": "CFG_CENTER_ICAP1_I29", + "CSIB": "CFG_CENTER_ICAP1_CSIB", + "I27": "CFG_CENTER_ICAP1_I27", + "O19": "CFG_CENTER_ICAP1_O19", + "O11": "CFG_CENTER_ICAP1_O11", + "RDWRB": "CFG_CENTER_ICAP1_RDWRB", + "O30": "CFG_CENTER_ICAP1_O30", + "I14": "CFG_CENTER_ICAP1_I14", + "I7": "CFG_CENTER_ICAP1_I7", + "I20": "CFG_CENTER_ICAP1_I20", + "I13": "CFG_CENTER_ICAP1_I13", + "I26": "CFG_CENTER_ICAP1_I26", + "O31": "CFG_CENTER_ICAP1_O31", + "I23": "CFG_CENTER_ICAP1_I23", + "O5": "CFG_CENTER_ICAP1_O5", + "O17": "CFG_CENTER_ICAP1_O17", + "I4": "CFG_CENTER_ICAP1_I4", + "O0": "CFG_CENTER_ICAP1_O0", + "I15": "CFG_CENTER_ICAP1_I15", + "O25": "CFG_CENTER_ICAP1_O25", + "O4": "CFG_CENTER_ICAP1_O4", + "I24": "CFG_CENTER_ICAP1_I24", + "I3": "CFG_CENTER_ICAP1_I3", + "O6": "CFG_CENTER_ICAP1_O6", + "I31": "CFG_CENTER_ICAP1_I31", + "O15": "CFG_CENTER_ICAP1_O15", + "O24": "CFG_CENTER_ICAP1_O24", + "O21": "CFG_CENTER_ICAP1_O21", + "I5": "CFG_CENTER_ICAP1_I5", + "I25": "CFG_CENTER_ICAP1_I25", + "I21": "CFG_CENTER_ICAP1_I21", + "O27": "CFG_CENTER_ICAP1_O27", + "O22": "CFG_CENTER_ICAP1_O22", + "I9": "CFG_CENTER_ICAP1_I9", + "I12": "CFG_CENTER_ICAP1_I12", + "I2": "CFG_CENTER_ICAP1_I2", + "I16": "CFG_CENTER_ICAP1_I16", + "I22": "CFG_CENTER_ICAP1_I22", + "I11": "CFG_CENTER_ICAP1_I11", + "I1": "CFG_CENTER_ICAP1_I1", + "O7": "CFG_CENTER_ICAP1_O7", + "O8": "CFG_CENTER_ICAP1_O8", + "I19": "CFG_CENTER_ICAP1_I19", + "O12": "CFG_CENTER_ICAP1_O12", + "O13": "CFG_CENTER_ICAP1_O13", + "I6": "CFG_CENTER_ICAP1_I6", + "O23": "CFG_CENTER_ICAP1_O23", + "O1": "CFG_CENTER_ICAP1_O1", + "O29": "CFG_CENTER_ICAP1_O29", + "I17": "CFG_CENTER_ICAP1_I17", + "I30": "CFG_CENTER_ICAP1_I30", + "O3": "CFG_CENTER_ICAP1_O3", + "O14": "CFG_CENTER_ICAP1_O14", + "O20": "CFG_CENTER_ICAP1_O20", + "O26": "CFG_CENTER_ICAP1_O26", + "I0": "CFG_CENTER_ICAP1_I0", + "I8": "CFG_CENTER_ICAP1_I8", + "O16": "CFG_CENTER_ICAP1_O16", + "O28": "CFG_CENTER_ICAP1_O28", + "I28": "CFG_CENTER_ICAP1_I28", + "CLK": "CFG_CENTER_ICAP1_CLK", + "I18": "CFG_CENTER_ICAP1_I18", + "O9": "CFG_CENTER_ICAP1_O9", + "O18": "CFG_CENTER_ICAP1_O18", + "O2": "CFG_CENTER_ICAP1_O2", + "O10": "CFG_CENTER_ICAP1_O10" + }, + "x_coord": 0 + } + ], + "wires": [ + "CFG_CENTER_EL1BEG2_0", + "CFG_CENTER_ICAP1_I31", + "CFG_CENTER_IMUX45_18", + "CFG_CENTER_USR_ACCESS_DATA23", + "CFG_CENTER_NW4END3_8", + "CFG_CENTER_SW2A0_16", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA12", + "CFG_CENTER_WL1END2_17", + "CFG_CENTER_LOGIC_OUTS_B4_13", + "CFG_CENTER_FRAME_ECC_SYNDROME8", + "CFG_CENTER_ICAP0_I1", + "CFG_CENTER_LOGIC_OUTS_B22_10", + "CFG_CENTER_IMUX16_4", + "CFG_CENTER_EE4C2_4", + "CFG_CENTER_WW4END1_5", + "CFG_CENTER_IMUX2_14", + "CFG_CENTER_FAN5_19", + "CFG_CENTER_IMUX20_15", + "CFG_CENTER_ER1BEG1_19", + "CFG_CENTER_LOGIC_OUTS_B5_14", + "CFG_CENTER_SE2A3_11", + "CFG_CENTER_LOGIC_OUTS_B23_16", + "CFG_CENTER_SE4C0_16", + "CFG_CENTER_EL1BEG1_0", + "CFG_CENTER_EE4B0_12", + "CFG_CENTER_IMUX37_9", + "CFG_CENTER_WW4A0_10", + "CFG_CENTER_BYP4_2", + "CFG_CENTER_EE4A0_9", + "CFG_CENTER_BYP0_14", + "CFG_CENTER_IMUX11_8", + "CFG_CENTER_IMUX14_4", + "CFG_CENTER_SE2A0_12", + "CFG_CENTER_NE2A3_14", + "CFG_CENTER_CFG_IO_ACCESS_PUDCB", + "CFG_CENTER_BLOCK_OUTS_B1_3", + "CFG_CENTER_SW2A2_12", + "CFG_CENTER_WW2END3_13", + "CFG_CENTER_IMUX9_14", + "CFG_CENTER_NW4END1_11", + "CFG_CENTER_SE4C0_4", + "CFG_CENTER_IMUX42_18", + "CFG_CENTER_CTRL1_1", + "CFG_CENTER_IMUX18_1", + "CFG_CENTER_EE4BEG0_17", + "CFG_CENTER_LOGIC_OUTS_B11_9", + "CFG_CENTER_IMUX38_6", + "CFG_CENTER_SW2A2_9", + "CFG_CENTER_BSCAN4_RESET", + "CFG_CENTER_NE4BEG2_17", + "CFG_CENTER_WW4A1_14", + "CFG_CENTER_LOGIC_OUTS_B18_5", + "CFG_CENTER_IMUX9_5", + "CFG_CENTER_SW2A3_17", + "CFG_CENTER_WW4A1_9", + "CFG_CENTER_LOGIC_OUTS_B13_16", + "CFG_CENTER_FAN1_15", + "CFG_CENTER_NE2A0_19", + "CFG_CENTER_NW4END0_15", + "CFG_CENTER_LOGIC_OUTS_B10_16", + "CFG_CENTER_LH1_17", + "CFG_CENTER_BYP3_3", + "CFG_CENTER_IMUX38_1", + "CFG_CENTER_EE2A1_14", + "CFG_CENTER_IMUX5_13", + "CFG_CENTER_FAN6_17", + "CFG_CENTER_IMUX6_2", + "CFG_CENTER_IMUX25_7", + "CFG_CENTER_WW2A0_7", + "CFG_CENTER_SE2A2_7", + "CFG_CENTER_FAN2_9", + "CFG_CENTER_SE4C2_19", + "CFG_CENTER_EE4BEG0_19", + "CFG_CENTER_NE4C3_14", + "CFG_CENTER_WL1END0_5", + "CFG_CENTER_IMUX32_5", + "CFG_CENTER_WW4B2_4", + "CFG_CENTER_NE4BEG1_13", + "CFG_CENTER_LOGIC_OUTS_B5_5", + "CFG_CENTER_LOGIC_OUTS_B4_8", + "CFG_CENTER_LH1_7", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA28", + "CFG_CENTER_NE4C0_8", + "CFG_CENTER_FRAME_ECC_FAR12", + "CFG_CENTER_IMUX24_3", + "CFG_CENTER_LOGIC_OUTS_B1_5", + "CFG_CENTER_NE2A1_8", + "CFG_CENTER_WW4C3_3", + "CFG_CENTER_LOGIC_OUTS_B14_4", + "CFG_CENTER_LOGIC_OUTS_B14_2", + "CFG_CENTER_IMUX36_13", + "CFG_CENTER_EE4C2_8", + "CFG_CENTER_WW4B1_12", + "CFG_CENTER_WW2A2_1", + "CFG_CENTER_EE2BEG0_6", + "CFG_CENTER_WW4B1_18", + "CFG_CENTER_IMUX9_9", + "CFG_CENTER_WW4B3_1", + "CFG_CENTER_ER1BEG2_8", + "CFG_CENTER_LOGIC_OUTS_B1_7", + "CFG_CENTER_WW4A0_18", + "CFG_CENTER_WW2END1_15", + "CFG_CENTER_SE4BEG0_10", + "CFG_CENTER_LOGIC_OUTS_B18_14", + "CFG_CENTER_FAN6_19", + "CFG_CENTER_NE2A0_9", + "CFG_CENTER_IMUX31_5", + "CFG_CENTER_LOGIC_OUTS_B7_1", + "CFG_CENTER_BYP7_3", + "CFG_CENTER_IMUX30_17", + "CFG_CENTER_SE4BEG2_11", + "CFG_CENTER_WL1END3_16", + "CFG_CENTER_LOGIC_OUTS_B8_2", + "CFG_CENTER_WR1END1_9", + "CFG_CENTER_IMUX15_10", + "CFG_CENTER_LOGIC_OUTS_B11_0", + "CFG_CENTER_IMUX14_18", + "CFG_CENTER_WW4B1_5", + "CFG_CENTER_BLOCK_OUTS_B2_16", + "CFG_CENTER_IMUX11_0", + "CFG_CENTER_SE2A1_17", + "CFG_CENTER_WW4B2_19", + "CFG_CENTER_EE4BEG2_8", + "CFG_CENTER_EL1BEG0_19", + "CFG_CENTER_IMUX3_17", + "CFG_CENTER_EE4C3_19", + "CFG_CENTER_ER1BEG3_15", + "CFG_CENTER_CLK0_15", + "CFG_CENTER_NW4A0_2", + "CFG_CENTER_LOGIC_OUTS_B4_4", + "CFG_CENTER_SE4BEG2_0", + "CFG_CENTER_LOGIC_OUTS_B16_13", + "CFG_CENTER_SW4END2_3", + "CFG_CENTER_WW2A0_6", + "CFG_CENTER_LOGIC_OUTS_B14_1", + "CFG_CENTER_NW2A0_5", + "CFG_CENTER_BLOCK_OUTS_B2_0", + "CFG_CENTER_LOGIC_OUTS_B4_3", + "CFG_CENTER_IMUX15_17", + "CFG_CENTER_IMUX2_2", + "CFG_CENTER_SE4BEG1_19", + "CFG_CENTER_IMUX8_3", + "CFG_CENTER_LOGIC_OUTS_B5_19", + "CFG_CENTER_IMUX35_17", + "CFG_CENTER_SW4END0_8", + "CFG_CENTER_LOGIC_OUTS_B23_14", + "CFG_CENTER_IMUX5_9", + "CFG_CENTER_IMUX27_10", + "CFG_CENTER_IMUX26_3", + "CFG_CENTER_NE4C3_6", + "CFG_CENTER_EE2A2_7", + "CFG_CENTER_EE2BEG2_17", + "CFG_CENTER_IMUX5_10", + "CFG_CENTER_LH4_8", + "CFG_CENTER_FAN2_14", + "CFG_CENTER_IMUX3_11", + "CFG_CENTER_EE2BEG0_17", + "CFG_CENTER_LH1_2", + "CFG_CENTER_SE2A0_11", + "CFG_CENTER_IMUX18_6", + "CFG_CENTER_IMUX30_9", + "CFG_CENTER_EL1BEG3_18", + "CFG_CENTER_EE2BEG1_14", + "CFG_CENTER_IMUX27_1", + "CFG_CENTER_SE4C3_16", + "CFG_CENTER_WR1END2_4", + "CFG_CENTER_IMUX47_4", + "CFG_CENTER_NE2A3_8", + "CFG_CENTER_FAN2_7", + "CFG_CENTER_IMUX32_3", + "CFG_CENTER_NE2A2_0", + "CFG_CENTER_IMUX24_19", + "CFG_CENTER_BLOCK_OUTS_B1_11", + "CFG_CENTER_LOGIC_OUTS_B13_0", + "CFG_CENTER_IMUX23_14", + "CFG_CENTER_SW4A2_6", + "CFG_CENTER_LH7_7", + "CFG_CENTER_NW4A3_15", + "CFG_CENTER_LOGIC_OUTS_B17_16", + "CFG_CENTER_IMUX15_12", + "CFG_CENTER_ICAP0_O1", + "CFG_CENTER_EE2A1_0", + "CFG_CENTER_LOGIC_OUTS_B10_1", + "CFG_CENTER_IMUX36_11", + "CFG_CENTER_IMUX25_3", + "CFG_CENTER_IMUX17_11", + "CFG_CENTER_BSCAN2_DRCK", + "CFG_CENTER_ER1BEG1_6", + "CFG_CENTER_FAN4_1", + "CFG_CENTER_NE4BEG3_13", + "CFG_CENTER_IMUX43_10", + "CFG_CENTER_IMUX47_7", + "CFG_CENTER_EE4BEG2_0", + "CFG_CENTER_FAN5_14", + "CFG_CENTER_BSCAN1_UPDATE", + "CFG_CENTER_BYP5_5", + "CFG_CENTER_SW4A1_2", + "CFG_CENTER_ER1BEG3_14", + "CFG_CENTER_FAN7_16", + "CFG_CENTER_EE2BEG1_7", + "CFG_CENTER_NW2A1_8", + "CFG_CENTER_SE4BEG2_3", + "CFG_CENTER_CLK1_18", + "CFG_CENTER_CK_BUFHCLK8", + "CFG_CENTER_WL1END0_6", + "CFG_CENTER_BLOCK_OUTS_B3_12", + "CFG_CENTER_CK_BUFHCLK0", + "CFG_CENTER_WL1END1_3", + "CFG_CENTER_EL1BEG3_0", + "CFG_CENTER_SE4BEG1_4", + "CFG_CENTER_FAN4_11", + "CFG_CENTER_CK_IN9", + "CFG_CENTER_IMUX39_0", + "CFG_CENTER_IMUX18_9", + "CFG_CENTER_NW4A1_9", + "CFG_CENTER_ICAP1_I30", + "CFG_CENTER_CK_IN2", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA1", + "CFG_CENTER_LOGIC_OUTS_B6_5", + "CFG_CENTER_NW4END1_12", + "CFG_CENTER_NE4BEG2_14", + "CFG_CENTER_WW4END2_7", + "CFG_CENTER_IMUX10_6", + "CFG_CENTER_NE4C1_19", + "CFG_CENTER_IMUX13_12", + "CFG_CENTER_IMUX19_5", + "CFG_CENTER_LOGIC_OUTS_B15_0", + "CFG_CENTER_IMUX24_16", + "CFG_CENTER_NE4C0_11", + "CFG_CENTER_SE2A0_13", + "CFG_CENTER_LH6_16", + "CFG_CENTER_EE2A0_13", + "CFG_CENTER_LOGIC_OUTS_B7_7", + "CFG_CENTER_WW4C3_0", + "CFG_CENTER_SE4BEG3_9", + "CFG_CENTER_IMUX35_4", + "CFG_CENTER_IMUX11_10", + "CFG_CENTER_IMUX12_4", + "CFG_CENTER_LOGIC_OUTS_B7_11", + "CFG_CENTER_SW4END2_15", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA24", + "CFG_CENTER_IMUX21_10", + "CFG_CENTER_IMUX16_1", + "CFG_CENTER_WW4B0_19", + "CFG_CENTER_IMUX11_15", + "CFG_CENTER_WL1END2_5", + "CFG_CENTER_ICAP0_O6", + "CFG_CENTER_BLOCK_OUTS_B1_5", + "CFG_CENTER_EE4A0_12", + "CFG_CENTER_LH2_15", + "CFG_CENTER_LOGIC_OUTS_B7_6", + "CFG_CENTER_SW4A1_14", + "CFG_CENTER_SE4BEG3_1", + "CFG_CENTER_WW2END3_3", + "CFG_CENTER_NW4A1_7", + "CFG_CENTER_CLK0_10", + "CFG_CENTER_EE4A3_16", + "CFG_CENTER_IMUX22_1", + "CFG_CENTER_IMUX25_9", + "CFG_CENTER_SW4END2_10", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA12", + "CFG_CENTER_BYP2_2", + "CFG_CENTER_ICAP0_O14", + "CFG_CENTER_IMUX39_3", + "CFG_CENTER_NE2A2_15", + "CFG_CENTER_SE4BEG2_18", + "CFG_CENTER_NE4C1_14", + "CFG_CENTER_WW4A1_5", + "CFG_CENTER_LOGIC_OUTS_B20_1", + "CFG_CENTER_WR1END2_13", + "CFG_CENTER_CK_IN13", + "CFG_CENTER_WW2END1_12", + "CFG_CENTER_BSCAN1_RESET", + "CFG_CENTER_SW4END2_8", + "CFG_CENTER_WW2END1_16", + "CFG_CENTER_WW4C1_8", + "CFG_CENTER_BYP1_16", + "CFG_CENTER_NW4A2_9", + "CFG_CENTER_LOGIC_OUTS_B20_7", + "CFG_CENTER_SW4END3_9", + "CFG_CENTER_NW4A3_10", + "CFG_CENTER_WL1END0_9", + "CFG_CENTER_SE2A0_14", + "CFG_CENTER_EE2A3_5", + "CFG_CENTER_WW2A3_6", + "CFG_CENTER_IMUX28_2", + "CFG_CENTER_BYP4_5", + "CFG_CENTER_EL1BEG1_4", + "CFG_CENTER_NE4C2_8", + "CFG_CENTER_LH8_13", + "CFG_CENTER_WW2END0_7", + "CFG_CENTER_WW2A0_5", + "CFG_CENTER_SW2A1_0", + "CFG_CENTER_IMUX13_2", + "CFG_CENTER_LOGIC_OUTS_B16_17", + "CFG_CENTER_WW4END3_11", + "CFG_CENTER_IMUX4_2", + "CFG_CENTER_LH10_3", + "CFG_CENTER_IMUX24_4", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA15", + "CFG_CENTER_LOGIC_OUTS_B5_8", + "CFG_CENTER_IMUX10_0", + "CFG_CENTER_EE4BEG1_0", + "CFG_CENTER_IMUX25_10", + "CFG_CENTER_IMUX12_1", + "CFG_CENTER_SW4END0_18", + "CFG_CENTER_FAN1_12", + "CFG_CENTER_LOGIC_OUTS_B5_18", + "CFG_CENTER_WW4END3_0", + "CFG_CENTER_EE4B2_16", + "CFG_CENTER_ICAP1_O16", + "CFG_CENTER_IMUX2_13", + "CFG_CENTER_LH7_17", + "CFG_CENTER_WW4A0_11", + "CFG_CENTER_LOGIC_OUTS_B6_0", + "CFG_CENTER_SE2A1_4", + "CFG_CENTER_FAN2_8", + "CFG_CENTER_SE4C2_5", + "CFG_CENTER_FAN5_8", + "CFG_CENTER_BYP5_7", + "CFG_CENTER_LOGIC_OUTS_B14_18", + "CFG_CENTER_IMUX46_4", + "CFG_CENTER_WW4C1_13", + "CFG_CENTER_LOGIC_OUTS_B6_9", + "CFG_CENTER_WW2A2_15", + "CFG_CENTER_SE2A2_13", + "CFG_CENTER_IMUX4_16", + "CFG_CENTER_EE4B0_15", + "CFG_CENTER_LOGIC_OUTS_B2_19", + "CFG_CENTER_SE4C0_1", + "CFG_CENTER_NW4END3_11", + "CFG_CENTER_LOGIC_OUTS_B2_14", + "CFG_CENTER_WW4A0_16", + "CFG_CENTER_IMUX34_10", + "CFG_CENTER_CLK1_4", + "CFG_CENTER_WR1END0_11", + "CFG_CENTER_WW4END2_15", + "CFG_CENTER_LH6_11", + "CFG_CENTER_LOGIC_OUTS_B23_2", + "CFG_CENTER_IMUX17_17", + "CFG_CENTER_IMUX32_6", + "CFG_CENTER_CTRL0_11", + "CFG_CENTER_IMUX30_6", + "CFG_CENTER_BYP4_15", + "CFG_CENTER_NE4C2_15", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA22", + "CFG_CENTER_BSCAN4_TCK", + "CFG_CENTER_EE4B3_10", + "CFG_CENTER_SW4END0_17", + "CFG_CENTER_LH7_11", + "CFG_CENTER_LH7_14", + "CFG_CENTER_LOGIC_OUTS_B14_10", + "CFG_CENTER_ICAP1_O3", + "CFG_CENTER_SW2A0_1", + "CFG_CENTER_FAN0_11", + "CFG_CENTER_NW4END2_2", + "CFG_CENTER_NW2A2_12", + "CFG_CENTER_ICAP0_I4", + "CFG_CENTER_NW4A0_5", + "CFG_CENTER_BLOCK_OUTS_B3_10", + "CFG_CENTER_LOGIC_OUTS_B17_19", + "CFG_CENTER_WW4END1_13", + "CFG_CENTER_IMUX28_15", + "CFG_CENTER_WR1END3_3", + "CFG_CENTER_WL1END0_10", + "CFG_CENTER_FRAME_ECC_ECCERROR", + "CFG_CENTER_EE4A0_2", + "CFG_CENTER_EE4C1_19", + "CFG_CENTER_WW2END3_7", + "CFG_CENTER_LOGIC_OUTS_B6_6", + "CFG_CENTER_IMUX37_14", + "CFG_CENTER_SE4C3_15", + "CFG_CENTER_NE4C2_0", + "CFG_CENTER_LH12_13", + "CFG_CENTER_SW4A1_19", + "CFG_CENTER_NE4C2_6", + "CFG_CENTER_EE4BEG1_5", + "CFG_CENTER_NE2A0_16", + "CFG_CENTER_IMUX32_7", + "CFG_CENTER_SE2A2_19", + "CFG_CENTER_WL1END0_7", + "CFG_CENTER_WW4END0_3", + "CFG_CENTER_IMUX27_17", + "CFG_CENTER_USR_ACCESS_DATA10", + "CFG_CENTER_LOGIC_OUTS_B15_12", + "CFG_CENTER_EE4C3_15", + "CFG_CENTER_NW4END1_0", + "CFG_CENTER_NW4A3_11", + "CFG_CENTER_NE4BEG2_11", + "CFG_CENTER_LOGIC_OUTS_B8_15", + "CFG_CENTER_SE4C2_11", + "CFG_CENTER_LH11_17", + "CFG_CENTER_IMUX25_18", + "CFG_CENTER_IMUX41_12", + "CFG_CENTER_WW2A1_18", + "CFG_CENTER_LOGIC_OUTS_B22_9", + "CFG_CENTER_SE4C0_2", + "CFG_CENTER_NE2A0_6", + "CFG_CENTER_BYP6_12", + "CFG_CENTER_NE4BEG1_16", + "CFG_CENTER_BSCAN2_SEL", + "CFG_CENTER_SE2A1_19", + "CFG_CENTER_IMUX34_0", + "CFG_CENTER_SE4BEG0_14", + "CFG_CENTER_EE2A0_4", + "CFG_CENTER_FRAME_ECC_FAR2", + "CFG_CENTER_BYP6_9", + "CFG_CENTER_SE4BEG2_16", + "CFG_CENTER_ICAP1_O17", + "CFG_CENTER_WR1END0_8", + "CFG_CENTER_NE2A1_5", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA28", + "CFG_CENTER_SW2A2_19", + "CFG_CENTER_WW4A0_0", + "CFG_CENTER_ICAP1_O7", + "CFG_CENTER_WW4B2_13", + "CFG_CENTER_MID_USR_ACCESS_DATA11", + "CFG_CENTER_NW4END3_2", + "CFG_CENTER_WW4A0_5", + "CFG_CENTER_WW4B3_15", + "CFG_CENTER_LOGIC_OUTS_B18_13", + "CFG_CENTER_EE2A0_19", + "CFG_CENTER_IMUX26_14", + "CFG_CENTER_SW2A1_5", + "CFG_CENTER_LH4_0", + "CFG_CENTER_EE4BEG1_6", + "CFG_CENTER_IMUX42_15", + "CFG_CENTER_STARTUP_KEYCLEARB", + "CFG_CENTER_WR1END0_18", + "CFG_CENTER_BLOCK_OUTS_B3_14", + "CFG_CENTER_NW4A2_10", + "CFG_CENTER_IMUX41_16", + "CFG_CENTER_NE4BEG1_2", + "CFG_CENTER_IMUX41_17", + "CFG_CENTER_WW4C3_15", + "CFG_CENTER_BYP6_18", + "CFG_CENTER_LOGIC_OUTS_B15_3", + "CFG_CENTER_SE4C1_3", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA31", + "CFG_CENTER_LOGIC_OUTS_B9_5", + "CFG_CENTER_ICAP0_O29", + "CFG_CENTER_SE4C1_16", + "CFG_CENTER_IMUX27_3", + "CFG_CENTER_LOGIC_OUTS_B23_3", + "CFG_CENTER_SE2A1_1", + "CFG_CENTER_FRAME_ECC_FAR0", + "CFG_CENTER_IMUX9_16", + "CFG_CENTER_EE4BEG1_4", + "CFG_CENTER_WW2END0_17", + "CFG_CENTER_EE4C0_18", + "CFG_CENTER_CLK0_0", + "CFG_CENTER_NE2A1_10", + "CFG_CENTER_LOGIC_OUTS_B12_7", + "CFG_CENTER_LOGIC_OUTS_B22_12", + "CFG_CENTER_CK_IN3", + "CFG_CENTER_SE2A3_19", + "CFG_CENTER_NW2A1_15", + "CFG_CENTER_NE4BEG0_7", + "CFG_CENTER_LH11_5", + "CFG_CENTER_NW2A1_14", + "CFG_CENTER_EE4BEG2_16", + "CFG_CENTER_WL1END2_4", + "CFG_CENTER_LH4_16", + "CFG_CENTER_WW2A2_7", + "CFG_CENTER_EE4C1_5", + "CFG_CENTER_IMUX16_15", + "CFG_CENTER_EE2BEG2_5", + "CFG_CENTER_LH1_3", + "CFG_CENTER_FAN5_15", + "CFG_CENTER_NE4C2_10", + "CFG_CENTER_NW4A2_3", + "CFG_CENTER_IMUX24_6", + "CFG_CENTER_IMUX26_12", + "CFG_CENTER_IMUX45_17", + "CFG_CENTER_IMUX24_1", + "CFG_CENTER_EE4BEG2_7", + "CFG_CENTER_PMVIOB_EN", + "CFG_CENTER_IMUX47_19", + "CFG_CENTER_LOGIC_OUTS_B0_12", + "CFG_CENTER_NW4END1_19", + "CFG_CENTER_IMUX4_12", + "CFG_CENTER_LH9_13", + "CFG_CENTER_LH11_2", + "CFG_CENTER_STARTUP_USRCCLKO", + "CFG_CENTER_WW4B2_12", + "CFG_CENTER_CLK1_2", + "CFG_CENTER_WR1END3_16", + "CFG_CENTER_SE4C2_2", + "CFG_CENTER_IMUX16_16", + "CFG_CENTER_NW4END2_6", + "CFG_CENTER_IMUX3_16", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA13", + "CFG_CENTER_IMUX2_12", + "CFG_CENTER_IMUX20_2", + "CFG_CENTER_IMUX11_19", + "CFG_CENTER_LOGIC_OUTS_B23_15", + "CFG_CENTER_WW4A0_17", + "CFG_CENTER_SE4C0_3", + "CFG_CENTER_NE4C1_12", + "CFG_CENTER_BYP1_7", + "CFG_CENTER_LH6_15", + "CFG_CENTER_IMUX31_17", + "CFG_CENTER_SW4A2_7", + "CFG_CENTER_IMUX21_15", + "CFG_CENTER_WW2END0_5", + "CFG_CENTER_IMUX43_6", + "CFG_CENTER_BLOCK_OUTS_B1_2", + "CFG_CENTER_LOGIC_OUTS_B8_13", + "CFG_CENTER_LOGIC_OUTS_B21_15", + "CFG_CENTER_ICAP1_O5", + "CFG_CENTER_EE4B2_5", + "CFG_CENTER_WW4END0_6", + "CFG_CENTER_LOGIC_OUTS_B13_5", + "CFG_CENTER_EE4A1_10", + "CFG_CENTER_LH1_12", + "CFG_CENTER_EE2BEG1_2", + "CFG_CENTER_IMUX24_14", + "CFG_CENTER_IMUX23_5", + "CFG_CENTER_LOGIC_OUTS_B19_19", + "CFG_CENTER_EE2A3_1", + "CFG_CENTER_NW4A2_6", + "CFG_CENTER_BSCAN2_TCK", + "CFG_CENTER_SE4BEG0_8", + "CFG_CENTER_EE2A2_8", + "CFG_CENTER_SE4BEG1_10", + "CFG_CENTER_LH1_4", + "CFG_CENTER_NW4A0_12", + "CFG_CENTER_SE4C0_12", + "CFG_CENTER_WL1END1_19", + "CFG_CENTER_IMUX13_16", + "CFG_CENTER_WW4END1_18", + "CFG_CENTER_LOGIC_OUTS_B10_8", + "CFG_CENTER_LOGIC_OUTS_B16_18", + "CFG_CENTER_WW4A1_13", + "CFG_CENTER_WW4END3_9", + "CFG_CENTER_WW2END2_0", + "CFG_CENTER_WW4B1_3", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA30", + "CFG_CENTER_FRAME_ECC_SYNDROME11", + "CFG_CENTER_WW4END3_13", + "CFG_CENTER_WW2END3_10", + "CFG_CENTER_SE4C2_0", + "CFG_CENTER_LOGIC_OUTS_B3_6", + "CFG_CENTER_NE4C3_17", + "CFG_CENTER_LOGIC_OUTS_B10_14", + "CFG_CENTER_IMUX44_1", + "CFG_CENTER_BYP7_10", + "CFG_CENTER_EE4B3_7", + "CFG_CENTER_ICAP0_I7", + "CFG_CENTER_EE2A1_1", + "CFG_CENTER_IMUX39_10", + "CFG_CENTER_SW4END1_7", + "CFG_CENTER_BYP0_9", + "CFG_CENTER_IMUX26_17", + "CFG_CENTER_EE2BEG0_1", + "CFG_CENTER_NE4C3_15", + "CFG_CENTER_LOGIC_OUTS_B14_6", + "CFG_CENTER_FAN4_7", + "CFG_CENTER_USR_ACCESS_DATA2", + "CFG_CENTER_SE4C2_15", + "CFG_CENTER_SE4BEG0_12", + "CFG_CENTER_IMUX39_15", + "CFG_CENTER_IMUX2_1", + "CFG_CENTER_SW4END0_11", + "CFG_CENTER_IMUX41_4", + "CFG_CENTER_SE4BEG0_11", + "CFG_CENTER_IMUX14_3", + "CFG_CENTER_WW2END1_18", + "CFG_CENTER_EE4C2_0", + "CFG_CENTER_IMUX39_1", + "CFG_CENTER_FRAME_ECC_FAR3", + "CFG_CENTER_EE4B1_11", + "CFG_CENTER_FAN6_0", + "CFG_CENTER_NE4BEG1_15", + "CFG_CENTER_IMUX11_13", + "CFG_CENTER_EE4A0_11", + "CFG_CENTER_CTRL0_10", + "CFG_CENTER_WW2A0_4", + "CFG_CENTER_WR1END3_0", + "CFG_CENTER_NE2A3_1", + "CFG_CENTER_WW4A2_6", + "CFG_CENTER_WW4B3_8", + "CFG_CENTER_IMUX24_10", + "CFG_CENTER_WW4C0_2", + "CFG_CENTER_BYP3_5", + "CFG_CENTER_BLOCK_OUTS_B3_19", + "CFG_CENTER_CFG_IO_ACCESS_TDO", + "CFG_CENTER_LOGIC_OUTS_B1_6", + "CFG_CENTER_NE4C0_12", + "CFG_CENTER_IMUX36_7", + "CFG_CENTER_NE2A3_13", + "CFG_CENTER_BLOCK_OUTS_B3_6", + "CFG_CENTER_WW4A1_4", + "CFG_CENTER_CK_BUFHCLK4", + "CFG_CENTER_NE4BEG3_9", + "CFG_CENTER_LH11_9", + "CFG_CENTER_LOGIC_OUTS_B20_0", + "CFG_CENTER_ER1BEG2_1", + "CFG_CENTER_CK_IN11", + "CFG_CENTER_LH1_15", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA11", + "CFG_CENTER_SW4END3_18", + "CFG_CENTER_BYP5_17", + "CFG_CENTER_EL1BEG0_13", + "CFG_CENTER_SE4BEG1_18", + "CFG_CENTER_WW4END2_2", + "CFG_CENTER_LOGIC_OUTS_B4_11", + "CFG_CENTER_BLOCK_OUTS_B2_9", + "CFG_CENTER_BYP3_0", + "CFG_CENTER_NE2A2_3", + "CFG_CENTER_EE4A0_17", + "CFG_CENTER_NE4BEG0_6", + "CFG_CENTER_SW4A1_10", + "CFG_CENTER_SE4C0_11", + "CFG_CENTER_WL1END3_11", + "CFG_CENTER_NE4C1_13", + "CFG_CENTER_SE4C1_7", + "CFG_CENTER_SW4END2_18", + "CFG_CENTER_IMUX45_1", + "CFG_CENTER_WW4C3_12", + "CFG_CENTER_IMUX10_13", + "CFG_CENTER_IMUX1_5", + "CFG_CENTER_IMUX43_13", + "CFG_CENTER_SW4END3_14", + "CFG_CENTER_EE4B3_14", + "CFG_CENTER_IMUX41_6", + "CFG_CENTER_ICAP0_I27", + "CFG_CENTER_FRAME_ECC_SYNWORD2", + "CFG_CENTER_FAN3_1", + "CFG_CENTER_IMUX38_0", + "CFG_CENTER_EE2A1_16", + "CFG_CENTER_EE2A3_7", + "CFG_CENTER_EE2A3_15", + "CFG_CENTER_FAN5_10", + "CFG_CENTER_EE4B3_0", + "CFG_CENTER_SE4C0_5", + "CFG_CENTER_BYP5_15", + "CFG_CENTER_LOGIC_OUTS_B7_17", + "CFG_CENTER_WR1END2_2", + "CFG_CENTER_EE4A1_3", + "CFG_CENTER_EE4A3_12", + "CFG_CENTER_WR1END1_11", + "CFG_CENTER_IMUX44_15", + "CFG_CENTER_IMUX41_2", + "CFG_CENTER_EE4B2_11", + "CFG_CENTER_WW2A1_19", + "CFG_CENTER_LOGIC_OUTS_B22_7", + "CFG_CENTER_IMUX27_15", + "CFG_CENTER_WW4C3_7", + "CFG_CENTER_WW4C2_14", + "CFG_CENTER_CLK0_17", + "CFG_CENTER_USR_ACCESS_DATA18", + "CFG_CENTER_EL1BEG3_14", + "CFG_CENTER_WW4C0_13", + "CFG_CENTER_ICAP1_I13", + "CFG_CENTER_WW2A2_2", + "CFG_CENTER_LOGIC_OUTS_B19_2", + "CFG_CENTER_WW4C2_0", + "CFG_CENTER_WW4C1_18", + "CFG_CENTER_EL1BEG0_3", + "CFG_CENTER_FAN0_15", + "CFG_CENTER_BYP3_13", + "CFG_CENTER_WW2A3_13", + "CFG_CENTER_EE4B1_9", + "CFG_CENTER_IMUX11_4", + "CFG_CENTER_LOGIC_OUTS_B6_8", + "CFG_CENTER_SW4A0_12", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA10", + "CFG_CENTER_EE4C3_6", + "CFG_CENTER_SW4END1_10", + "CFG_CENTER_LOGIC_OUTS_B2_10", + "CFG_CENTER_SW2A2_7", + "CFG_CENTER_IMUX24_5", + "CFG_CENTER_SW2A1_14", + "CFG_CENTER_LH6_0", + "CFG_CENTER_ICAP0_I5", + "CFG_CENTER_WL1END3_2", + "CFG_CENTER_LOGIC_OUTS_B1_15", + "CFG_CENTER_EE4B3_5", + "CFG_CENTER_EE4C3_3", + "CFG_CENTER_SW4END1_5", + "CFG_CENTER_EL1BEG3_11", + "CFG_CENTER_NW4END3_0", + "CFG_CENTER_IMUX37_4", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA21", + "CFG_CENTER_EE2BEG3_0", + "CFG_CENTER_NW4A3_4", + "CFG_CENTER_IMUX41_3", + "CFG_CENTER_IMUX1_0", + "CFG_CENTER_ER1BEG3_3", + "CFG_CENTER_EE4A3_8", + "CFG_CENTER_BYP7_1", + "CFG_CENTER_LOGIC_OUTS_B9_19", + "CFG_CENTER_NW4END1_7", + "CFG_CENTER_WW4B1_0", + "CFG_CENTER_LOGIC_OUTS_B7_16", + "CFG_CENTER_EE2A0_14", + "CFG_CENTER_IMUX38_9", + "CFG_CENTER_SE4BEG3_11", + "CFG_CENTER_ICAP1_O8", + "CFG_CENTER_SE4C3_11", + "CFG_CENTER_SW4A3_9", + "CFG_CENTER_LH10_0", + "CFG_CENTER_ER1BEG2_15", + "CFG_CENTER_LOGIC_OUTS_B17_3", + "CFG_CENTER_EE4A3_5", + "CFG_CENTER_EL1BEG2_17", + "CFG_CENTER_WL1END1_16", + "CFG_CENTER_WR1END1_13", + "CFG_CENTER_LH12_15", + "CFG_CENTER_WW2A1_2", + "CFG_CENTER_WR1END2_3", + "CFG_CENTER_EE4B0_11", + "CFG_CENTER_IMUX37_1", + "CFG_CENTER_WL1END1_2", + "CFG_CENTER_USR_ACCESS_DATA15", + "CFG_CENTER_EE2BEG2_3", + "CFG_CENTER_EE4A2_12", + "CFG_CENTER_EE4BEG1_19", + "CFG_CENTER_FAN4_4", + "CFG_CENTER_NW2A3_17", + "CFG_CENTER_WW2END1_4", + "CFG_CENTER_NE4C0_5", + "CFG_CENTER_EE2BEG0_2", + "CFG_CENTER_IMUX16_2", + "CFG_CENTER_CTRL0_2", + "CFG_CENTER_CLK0_8", + "CFG_CENTER_NW4A0_8", + "CFG_CENTER_LH5_0", + "CFG_CENTER_IMUX36_15", + "CFG_CENTER_ER1BEG2_4", + "CFG_CENTER_WW2END0_19", + "CFG_CENTER_LH8_17", + "CFG_CENTER_LOGIC_OUTS_B22_17", + "CFG_CENTER_NW2A2_18", + "CFG_CENTER_IMUX15_2", + "CFG_CENTER_EE4C3_16", + "CFG_CENTER_NW4A1_6", + "CFG_CENTER_IMUX0_2", + "CFG_CENTER_EE4BEG0_10", + "CFG_CENTER_CK_BUFRCLK2", + "CFG_CENTER_IMUX19_6", + "CFG_CENTER_LOGIC_OUTS_B16_11", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA20", + "CFG_CENTER_SE2A3_13", + "CFG_CENTER_WL1END0_19", + "CFG_CENTER_SW4A1_13", + "CFG_CENTER_IMUX46_10", + "CFG_CENTER_SE4C3_14", + "CFG_CENTER_NW2A3_11", + "CFG_CENTER_WR1END3_7", + "CFG_CENTER_CLK1_6", + "CFG_CENTER_LH4_12", + "CFG_CENTER_LOGIC_OUTS_B0_15", + "CFG_CENTER_NE2A0_17", + "CFG_CENTER_IMUX42_19", + "CFG_CENTER_IMUX16_17", + "CFG_CENTER_EE4BEG0_9", + "CFG_CENTER_LOGIC_OUTS_B3_14", + "CFG_CENTER_LH11_19", + "CFG_CENTER_LH11_10", + "CFG_CENTER_EE4BEG0_2", + "CFG_CENTER_NE2A0_1", + "CFG_CENTER_EE4BEG1_3", + "CFG_CENTER_BYP3_7", + "CFG_CENTER_EE2A1_10", + "CFG_CENTER_IMUX19_17", + "CFG_CENTER_LOGIC_OUTS_B15_1", + "CFG_CENTER_NW4A1_17", + "CFG_CENTER_SE2A2_4", + "CFG_CENTER_ICAP1_O29", + "CFG_CENTER_IMUX43_14", + "CFG_CENTER_BSCAN4_CAPTURE", + "CFG_CENTER_SW4A1_0", + "CFG_CENTER_LOGIC_OUTS_B2_15", + "CFG_CENTER_WW4C1_9", + "CFG_CENTER_EE4C1_17", + "CFG_CENTER_IMUX20_1", + "CFG_CENTER_WW4A1_17", + "CFG_CENTER_WW2END3_11", + "CFG_CENTER_WL1END2_16", + "CFG_CENTER_SW4END1_16", + "CFG_CENTER_SW4END3_1", + "CFG_CENTER_USR_ACCESS_DATA20", + "CFG_CENTER_SW4A2_8", + "CFG_CENTER_WL1END2_8", + "CFG_CENTER_IMUX35_0", + "CFG_CENTER_EE4BEG1_9", + "CFG_CENTER_LH5_15", + "CFG_CENTER_EE2A2_16", + "CFG_CENTER_LH1_16", + "CFG_CENTER_IMUX6_12", + "CFG_CENTER_EE4C0_13", + "CFG_CENTER_CLK0_3", + "CFG_CENTER_WW2A2_14", + "CFG_CENTER_WW2END0_1", + "CFG_CENTER_WW4A3_12", + "CFG_CENTER_IMUX0_5", + "CFG_CENTER_ER1BEG0_0", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA24", + "CFG_CENTER_EE2A2_15", + "CFG_CENTER_LH2_1", + "CFG_CENTER_WW4B1_19", + "CFG_CENTER_IMUX14_16", + "CFG_CENTER_IMUX29_1", + "CFG_CENTER_EE4A2_11", + "CFG_CENTER_SW4A0_6", + "CFG_CENTER_EE2BEG0_10", + "CFG_CENTER_BYP3_1", + "CFG_CENTER_SE4BEG2_2", + "CFG_CENTER_FAN2_1", + "CFG_CENTER_EL1BEG3_12", + "CFG_CENTER_NW4A3_17", + "CFG_CENTER_IMUX20_5", + "CFG_CENTER_WW4C2_7", + "CFG_CENTER_LOGIC_OUTS_B16_7", + "CFG_CENTER_FAN5_6", + "CFG_CENTER_IMUX40_3", + "CFG_CENTER_IMUX7_6", + "CFG_CENTER_IMUX8_0", + "CFG_CENTER_IMUX25_14", + "CFG_CENTER_FAN3_11", + "CFG_CENTER_EL1BEG2_18", + "CFG_CENTER_EE4BEG1_2", + "CFG_CENTER_EL1BEG2_8", + "CFG_CENTER_BYP4_6", + "CFG_CENTER_BYP1_0", + "CFG_CENTER_SE2A3_4", + "CFG_CENTER_EE4BEG3_19", + "CFG_CENTER_FAN5_11", + "CFG_CENTER_IMUX35_1", + "CFG_CENTER_IMUX37_19", + "CFG_CENTER_WL1END3_1", + "CFG_CENTER_LOGIC_OUTS_B11_17", + "CFG_CENTER_WW4A2_8", + "CFG_CENTER_EE4A3_19", + "CFG_CENTER_LOGIC_OUTS_B10_17", + "CFG_CENTER_NW4END1_1", + "CFG_CENTER_SW4A1_6", + "CFG_CENTER_LOGIC_OUTS_B23_11", + "CFG_CENTER_WW2A0_10", + "CFG_CENTER_NW4A2_8", + "CFG_CENTER_WR1END2_18", + "CFG_CENTER_NE2A2_2", + "CFG_CENTER_WW4B1_6", + "CFG_CENTER_SW4END3_6", + "CFG_CENTER_WW4C2_17", + "CFG_CENTER_LOGIC_OUTS_B8_7", + "CFG_CENTER_LOGIC_OUTS_B3_4", + "CFG_CENTER_IMUX28_13", + "CFG_CENTER_WR1END1_16", + "CFG_CENTER_EE4B2_18", + "CFG_CENTER_IMUX23_8", + "CFG_CENTER_FAN5_12", + "CFG_CENTER_WW4B2_11", + "CFG_CENTER_IMUX17_4", + "CFG_CENTER_IMUX15_16", + "CFG_CENTER_MID_USR_ACCESS_DATA5", + "CFG_CENTER_WW2END3_1", + "CFG_CENTER_WL1END0_8", + "CFG_CENTER_LH12_4", + "CFG_CENTER_CK_BUFHCLK9", + "CFG_CENTER_SE2A3_3", + "CFG_CENTER_LOGIC_OUTS_B12_9", + "CFG_CENTER_SE4C1_11", + "CFG_CENTER_WL1END1_9", + "CFG_CENTER_NW4END3_9", + "CFG_CENTER_LOGIC_OUTS_B14_3", + "CFG_CENTER_NW4END2_17", + "CFG_CENTER_WW4END1_9", + "CFG_CENTER_EE4A0_1", + "CFG_CENTER_IMUX23_11", + "CFG_CENTER_IMUX36_3", + "CFG_CENTER_NE4BEG1_11", + "CFG_CENTER_IMUX44_18", + "CFG_CENTER_IMUX8_12", + "CFG_CENTER_LOGIC_OUTS_B13_18", + "CFG_CENTER_SE4C0_7", + "CFG_CENTER_EE4C0_5", + "CFG_CENTER_EE4A2_4", + "CFG_CENTER_NE4BEG1_5", + "CFG_CENTER_SW4A2_17", + "CFG_CENTER_LH5_4", + "CFG_CENTER_IMUX21_5", + "CFG_CENTER_FAN7_1", + "CFG_CENTER_LOGIC_OUTS_B3_18", + "CFG_CENTER_WW4C0_14", + "CFG_CENTER_NW4END3_6", + "CFG_CENTER_NW4END1_4", + "CFG_CENTER_IMUX28_0", + "CFG_CENTER_EL1BEG1_5", + "CFG_CENTER_ER1BEG2_14", + "CFG_CENTER_LH9_4", + "CFG_CENTER_EE2BEG3_8", + "CFG_CENTER_LOGIC_OUTS_B23_1", + "CFG_CENTER_NW4END3_12", + "CFG_CENTER_WL1END2_7", + "CFG_CENTER_IMUX40_7", + "CFG_CENTER_FAN3_15", + "CFG_CENTER_FAN5_7", + "CFG_CENTER_NE2A1_18", + "CFG_CENTER_BLOCK_OUTS_B1_18", + "CFG_CENTER_WR1END2_8", + "CFG_CENTER_EE4BEG0_8", + "CFG_CENTER_BLOCK_OUTS_B3_11", + "CFG_CENTER_SW2A1_12", + "CFG_CENTER_SW4A0_15", + "CFG_CENTER_IMUX34_9", + "CFG_CENTER_LOGIC_OUTS_B20_13", + "CFG_CENTER_IMUX12_3", + "CFG_CENTER_IMUX4_17", + "CFG_CENTER_NE4BEG3_5", + "CFG_CENTER_FAN0_7", + "CFG_CENTER_SW4A0_8", + "CFG_CENTER_LOGIC_OUTS_B17_0", + "CFG_CENTER_IMUX44_4", + "CFG_CENTER_IMUX30_15", + "CFG_CENTER_SW4END2_9", + "CFG_CENTER_LOGIC_OUTS_B16_4", + "CFG_CENTER_IMUX34_18", + "CFG_CENTER_NW2A3_9", + "CFG_CENTER_SE4C0_10", + "CFG_CENTER_NE4C1_1", + "CFG_CENTER_BLOCK_OUTS_B1_13", + "CFG_CENTER_SE2A3_18", + "CFG_CENTER_SW2A1_17", + "CFG_CENTER_IMUX18_13", + "CFG_CENTER_EE4B1_5", + "CFG_CENTER_IMUX19_1", + "CFG_CENTER_CTRL0_5", + "CFG_CENTER_LH12_10", + "CFG_CENTER_BYP6_6", + "CFG_CENTER_IMUX37_3", + "CFG_CENTER_IMUX23_16", + "CFG_CENTER_SE4BEG0_6", + "CFG_CENTER_LH11_15", + "CFG_CENTER_NW4A2_0", + "CFG_CENTER_EE4BEG2_2", + "CFG_CENTER_SW4END3_7", + "CFG_CENTER_IMUX29_16", + "CFG_CENTER_IMUX7_0", + "CFG_CENTER_LH12_6", + "CFG_CENTER_IMUX34_1", + "CFG_CENTER_IMUX42_14", + "CFG_CENTER_BYP3_15", + "CFG_CENTER_IMUX41_7", + "CFG_CENTER_LH1_5", + "CFG_CENTER_WW4END0_7", + "CFG_CENTER_FRAME_ECC_FAR15", + "CFG_CENTER_LOGIC_OUTS_B0_9", + "CFG_CENTER_LOGIC_OUTS_B22_14", + "CFG_CENTER_NW2A3_15", + "CFG_CENTER_EE4B2_8", + "CFG_CENTER_IMUX24_0", + "CFG_CENTER_LOGIC_OUTS_B4_2", + "CFG_CENTER_IMUX15_15", + "CFG_CENTER_SE2A2_17", + "CFG_CENTER_IMUX15_11", + "CFG_CENTER_CLK1_13", + "CFG_CENTER_EE2A2_5", + "CFG_CENTER_FAN3_9", + "CFG_CENTER_EE2BEG2_11", + "CFG_CENTER_IMUX28_1", + "CFG_CENTER_NE4BEG2_4", + "CFG_CENTER_BLOCK_OUTS_B1_9", + "CFG_CENTER_IMUX0_6", + "CFG_CENTER_LH3_7", + "CFG_CENTER_WW4A3_18", + "CFG_CENTER_LH6_10", + "CFG_CENTER_LOGIC_OUTS_B9_0", + "CFG_CENTER_SW2A1_18", + "CFG_CENTER_WW4C2_9", + "CFG_CENTER_IMUX42_17", + "CFG_CENTER_ICAP0_I29", + "CFG_CENTER_IMUX41_8", + "CFG_CENTER_FAN6_15", + "CFG_CENTER_IMUX1_19", + "CFG_CENTER_WW2END2_14", + "CFG_CENTER_EL1BEG0_10", + "CFG_CENTER_BYP4_17", + "CFG_CENTER_ICAP0_O13", + "CFG_CENTER_IMUX27_5", + "CFG_CENTER_IMUX41_15", + "CFG_CENTER_FAN7_12", + "CFG_CENTER_SW4END1_8", + "CFG_CENTER_NW4A2_13", + "CFG_CENTER_NW4END1_16", + "CFG_CENTER_LOGIC_OUTS_B9_14", + "CFG_CENTER_FAN3_2", + "CFG_CENTER_NW4A2_17", + "CFG_CENTER_WL1END1_12", + "CFG_CENTER_LOGIC_OUTS_B1_0", + "CFG_CENTER_SE4BEG1_14", + "CFG_CENTER_STARTUP_USRCCLKTS", + "CFG_CENTER_EE2BEG0_18", + "CFG_CENTER_IMUX3_2", + "CFG_CENTER_WW4A3_3", + "CFG_CENTER_FAN6_2", + "CFG_CENTER_SW4END1_6", + "CFG_CENTER_NE4BEG2_1", + "CFG_CENTER_BYP4_7", + "CFG_CENTER_NE4C3_12", + "CFG_CENTER_NE4BEG0_15", + "CFG_CENTER_IMUX47_17", + "CFG_CENTER_FAN4_0", + "CFG_CENTER_NE2A1_6", + "CFG_CENTER_MID_USR_ACCESS_DATA7", + "CFG_CENTER_WW2END3_15", + "CFG_CENTER_IMUX35_9", + "CFG_CENTER_IMUX18_11", + "CFG_CENTER_WW4A0_19", + "CFG_CENTER_ER1BEG0_3", + "CFG_CENTER_BYP3_16", + "CFG_CENTER_SW4A1_12", + "CFG_CENTER_SW4A3_8", + "CFG_CENTER_WW2END0_0", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA23", + "CFG_CENTER_LH6_9", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA18", + "CFG_CENTER_EE4BEG2_4", + "CFG_CENTER_LOGIC_OUTS_B3_19", + "CFG_CENTER_EE2BEG2_12", + "CFG_CENTER_WL1END0_14", + "CFG_CENTER_BLOCK_OUTS_B0_6", + "CFG_CENTER_IMUX46_14", + "CFG_CENTER_WW4END3_10", + "CFG_CENTER_SW2A3_16", + "CFG_CENTER_IMUX28_14", + "CFG_CENTER_EE2BEG0_11", + "CFG_CENTER_IMUX44_0", + "CFG_CENTER_ER1BEG2_18", + "CFG_CENTER_IMUX5_4", + "CFG_CENTER_NW4A2_7", + "CFG_CENTER_WW2A0_0", + "CFG_CENTER_NE2A0_10", + "CFG_CENTER_WW4C1_4", + "CFG_CENTER_LOGIC_OUTS_B17_2", + "CFG_CENTER_IMUX29_3", + "CFG_CENTER_BLOCK_OUTS_B1_10", + "CFG_CENTER_EE2BEG3_10", + "CFG_CENTER_WW4A1_16", + "CFG_CENTER_EE4A0_16", + "CFG_CENTER_IMUX15_0", + "CFG_CENTER_EE4C3_12", + "CFG_CENTER_IMUX44_13", + "CFG_CENTER_LH2_11", + "CFG_CENTER_EE4B2_12", + "CFG_CENTER_WW2A2_17", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA17", + "CFG_CENTER_BLOCK_OUTS_B0_8", + "CFG_CENTER_EE4A3_9", + "CFG_CENTER_EE4A3_17", + "CFG_CENTER_NE4BEG1_6", + "CFG_CENTER_WW2END2_5", + "CFG_CENTER_IMUX12_8", + "CFG_CENTER_USR_ACCESS_DATA22", + "CFG_CENTER_NW2A2_10", + "CFG_CENTER_IMUX22_14", + "CFG_CENTER_WW4END1_7", + "CFG_CENTER_LOGIC_OUTS_B0_11", + "CFG_CENTER_WW2A1_3", + "CFG_CENTER_CLK1_17", + "CFG_CENTER_WW4C1_3", + "CFG_CENTER_IMUX11_7", + "CFG_CENTER_NE4BEG2_13", + "CFG_CENTER_BYP5_10", + "CFG_CENTER_IMUX16_6", + "CFG_CENTER_LOGIC_OUTS_B22_3", + "CFG_CENTER_IMUX33_6", + "CFG_CENTER_NE2A1_11", + "CFG_CENTER_WW4C0_0", + "CFG_CENTER_IMUX29_2", + "CFG_CENTER_BLOCK_OUTS_B2_14", + "CFG_CENTER_SE4C3_7", + "CFG_CENTER_SW2A0_18", + "CFG_CENTER_EE4C2_17", + "CFG_CENTER_LH5_9", + "CFG_CENTER_IMUX2_0", + "CFG_CENTER_EE4BEG2_9", + "CFG_CENTER_SW2A2_6", + "CFG_CENTER_IMUX11_2", + "CFG_CENTER_NE4BEG0_13", + "CFG_CENTER_WL1END2_15", + "CFG_CENTER_IMUX12_9", + "CFG_CENTER_IMUX25_12", + "CFG_CENTER_SW4A0_13", + "CFG_CENTER_USR_ACCESS_DATAVALID", + "CFG_CENTER_SE2A0_2", + "CFG_CENTER_LH8_3", + "CFG_CENTER_EL1BEG0_8", + "CFG_CENTER_BYP7_12", + "CFG_CENTER_FAN7_11", + "CFG_CENTER_IMUX43_3", + "CFG_CENTER_USR_ACCESS_DATA31", + "CFG_CENTER_EE4A3_6", + "CFG_CENTER_LOGIC_OUTS_B12_0", + "CFG_CENTER_LH7_13", + "CFG_CENTER_LOGIC_OUTS_B12_10", + "CFG_CENTER_EE2BEG3_13", + "CFG_CENTER_WW4A3_1", + "CFG_CENTER_SE4C1_12", + "CFG_CENTER_WW4B0_14", + "CFG_CENTER_WW4B2_0", + "CFG_CENTER_IMUX30_4", + "CFG_CENTER_SW2A0_2", + "CFG_CENTER_ER1BEG3_16", + "CFG_CENTER_LOGIC_OUTS_B13_4", + "CFG_CENTER_IMUX40_2", + "CFG_CENTER_FAN1_0", + "CFG_CENTER_ICAP1_O13", + "CFG_CENTER_LH10_11", + "CFG_CENTER_FRAME_ECC_FAR8", + "CFG_CENTER_NE4C2_5", + "CFG_CENTER_NE2A0_18", + "CFG_CENTER_EE4A0_7", + "CFG_CENTER_LOGIC_OUTS_B9_16", + "CFG_CENTER_WW2END2_8", + "CFG_CENTER_WR1END1_5", + "CFG_CENTER_IMUX2_9", + "CFG_CENTER_NE2A3_17", + "CFG_CENTER_LOGIC_OUTS_B4_17", + "CFG_CENTER_EE2BEG0_9", + "CFG_CENTER_IMUX20_16", + "CFG_CENTER_SE2A3_14", + "CFG_CENTER_NE2A1_12", + "CFG_CENTER_WW2END3_19", + "CFG_CENTER_LOGIC_OUTS_B3_10", + "CFG_CENTER_EL1BEG3_13", + "CFG_CENTER_EE4C0_11", + "CFG_CENTER_FAN1_7", + "CFG_CENTER_NE4C2_1", + "CFG_CENTER_LOGIC_OUTS_B12_5", + "CFG_CENTER_EE4B0_18", + "CFG_CENTER_ICAP1_I26", + "CFG_CENTER_NW4A1_4", + "CFG_CENTER_BLOCK_OUTS_B2_12", + "CFG_CENTER_LOGIC_OUTS_B2_1", + "CFG_CENTER_WW2A0_11", + "CFG_CENTER_FAN6_9", + "CFG_CENTER_NE4C0_17", + "CFG_CENTER_IMUX15_1", + "CFG_CENTER_IMUX42_3", + "CFG_CENTER_FRAME_ECC_FAR4", + "CFG_CENTER_WW4B0_10", + "CFG_CENTER_WW2A0_15", + "CFG_CENTER_SE2A1_15", + "CFG_CENTER_WW2A0_17", + "CFG_CENTER_IMUX21_17", + "CFG_CENTER_LOGIC_OUTS_B17_7", + "CFG_CENTER_NE4BEG1_14", + "CFG_CENTER_LH9_2", + "CFG_CENTER_IMUX45_10", + "CFG_CENTER_LOGIC_OUTS_B3_3", + "CFG_CENTER_FRAME_ECC_SYNDROME9", + "CFG_CENTER_FAN0_13", + "CFG_CENTER_WW2A3_7", + "CFG_CENTER_IMUX2_6", + "CFG_CENTER_IMUX19_13", + "CFG_CENTER_EL1BEG3_8", + "CFG_CENTER_IMUX26_0", + "CFG_CENTER_LOGIC_OUTS_B21_14", + "CFG_CENTER_EE2A1_4", + "CFG_CENTER_NE4BEG3_19", + "CFG_CENTER_SW2A3_2", + "CFG_CENTER_EE4BEG1_12", + "CFG_CENTER_NW4A0_4", + "CFG_CENTER_WW4C1_11", + "CFG_CENTER_WR1END1_6", + "CFG_CENTER_IMUX38_19", + "CFG_CENTER_SW4END2_4", + "CFG_CENTER_LOGIC_OUTS_B11_15", + "CFG_CENTER_IMUX12_14", + "CFG_CENTER_LH9_5", + "CFG_CENTER_IMUX36_12", + "CFG_CENTER_SW4A1_3", + "CFG_CENTER_ICAP0_I28", + "CFG_CENTER_FAN2_15", + "CFG_CENTER_LH6_6", + "CFG_CENTER_IMUX42_4", + "CFG_CENTER_IMUX7_16", + "CFG_CENTER_LOGIC_OUTS_B16_1", + "CFG_CENTER_WW4A0_2", + "CFG_CENTER_ICAP0_I13", + "CFG_CENTER_WW2A1_13", + "CFG_CENTER_LH3_15", + "CFG_CENTER_EE4C1_10", + "CFG_CENTER_BLOCK_OUTS_B0_18", + "CFG_CENTER_CLK1_9", + "CFG_CENTER_LH11_7", + "CFG_CENTER_BYP7_15", + "CFG_CENTER_WW4C2_1", + "CFG_CENTER_NW4A0_3", + "CFG_CENTER_IMUX8_14", + "CFG_CENTER_WW4C0_7", + "CFG_CENTER_WW2A1_5", + "CFG_CENTER_SW4END0_1", + "CFG_CENTER_NW4END3_18", + "CFG_CENTER_SW4A3_16", + "CFG_CENTER_BSCAN4_TDO", + "CFG_CENTER_EE4A3_15", + "CFG_CENTER_EL1BEG2_11", + "CFG_CENTER_IMUX14_10", + "CFG_CENTER_EE2BEG3_9", + "CFG_CENTER_SE2A0_1", + "CFG_CENTER_WL1END1_13", + "CFG_CENTER_WW2END1_0", + "CFG_CENTER_NW2A2_4", + "CFG_CENTER_SE4C0_13", + "CFG_CENTER_BYP0_1", + "CFG_CENTER_WW2A3_2", + "CFG_CENTER_LOGIC_OUTS_B5_13", + "CFG_CENTER_ER1BEG0_2", + "CFG_CENTER_WL1END3_14", + "CFG_CENTER_ICAP1_I5", + "CFG_CENTER_LOGIC_OUTS_B4_6", + "CFG_CENTER_NE4BEG0_0", + "CFG_CENTER_ER1BEG3_2", + "CFG_CENTER_IMUX40_9", + "CFG_CENTER_SE4C3_18", + "CFG_CENTER_SE4C2_18", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA25", + "CFG_CENTER_EE4B0_10", + "CFG_CENTER_LOGIC_OUTS_B3_11", + "CFG_CENTER_IMUX15_18", + "CFG_CENTER_IMUX19_4", + "CFG_CENTER_LOGIC_OUTS_B21_5", + "CFG_CENTER_EE4A0_14", + "CFG_CENTER_IMUX23_7", + "CFG_CENTER_IMUX34_5", + "CFG_CENTER_WW4A2_1", + "CFG_CENTER_IMUX13_14", + "CFG_CENTER_ICAP0_O21", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA14", + "CFG_CENTER_EE4B1_13", + "CFG_CENTER_IMUX16_7", + "CFG_CENTER_BLOCK_OUTS_B3_1", + "CFG_CENTER_WW4A3_7", + "CFG_CENTER_ICAP0_I24", + "CFG_CENTER_LOGIC_OUTS_B12_15", + "CFG_CENTER_NE4BEG3_6", + "CFG_CENTER_LOGIC_OUTS_B8_4", + "CFG_CENTER_WW4A1_10", + "CFG_CENTER_WW4B3_3", + "CFG_CENTER_BSCAN2_RUNTEST", + "CFG_CENTER_FAN4_14", + "CFG_CENTER_SE2A2_12", + "CFG_CENTER_LOGIC_OUTS_B10_12", + "CFG_CENTER_WW4A2_0", + "CFG_CENTER_WW4B3_11", + "CFG_CENTER_IMUX42_8", + "CFG_CENTER_NE4C1_18", + "CFG_CENTER_NE2A2_1", + "CFG_CENTER_LH10_12", + "CFG_CENTER_NE2A0_2", + "CFG_CENTER_WW4END1_2", + "CFG_CENTER_IMUX43_8", + "CFG_CENTER_NE2A2_12", + "CFG_CENTER_EE2BEG1_9", + "CFG_CENTER_SE2A2_18", + "CFG_CENTER_FAN4_8", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA4", + "CFG_CENTER_BSCAN1_SEL", + "CFG_CENTER_LH9_6", + "CFG_CENTER_WW4END1_15", + "CFG_CENTER_WR1END0_9", + "CFG_CENTER_LH11_14", + "CFG_CENTER_SW4A0_11", + "CFG_CENTER_BLOCK_OUTS_B3_4", + "CFG_CENTER_IMUX2_4", + "CFG_CENTER_LOGIC_OUTS_B20_3", + "CFG_CENTER_EE4BEG0_0", + "CFG_CENTER_EL1BEG0_7", + "CFG_CENTER_WW2END3_12", + "CFG_CENTER_IMUX27_8", + "CFG_CENTER_EL1BEG2_1", + "CFG_CENTER_EE2A3_6", + "CFG_CENTER_LOGIC_OUTS_B13_2", + "CFG_CENTER_FAN0_0", + "CFG_CENTER_ICAP0_O12", + "CFG_CENTER_SE4C1_15", + "CFG_CENTER_WW2A3_10", + "CFG_CENTER_NW2A2_7", + "CFG_CENTER_LOGIC_OUTS_B21_10", + "CFG_CENTER_NW2A3_10", + "CFG_CENTER_NW4END1_2", + "CFG_CENTER_IMUX7_3", + "CFG_CENTER_IMUX21_9", + "CFG_CENTER_SW4END0_5", + "CFG_CENTER_IMUX19_7", + "CFG_CENTER_ICAP1_O30", + "CFG_CENTER_ICAP1_O6", + "CFG_CENTER_NE2A2_10", + "CFG_CENTER_IMUX6_6", + "CFG_CENTER_WW4B1_7", + "CFG_CENTER_SE4C3_2", + "CFG_CENTER_EE4BEG1_13", + "CFG_CENTER_IMUX7_14", + "CFG_CENTER_NE4BEG2_2", + "CFG_CENTER_ER1BEG0_15", + "CFG_CENTER_IMUX44_8", + "CFG_CENTER_SE4BEG3_18", + "CFG_CENTER_PMVIOB_ODIV4", + "CFG_CENTER_LOGIC_OUTS_B1_12", + "CFG_CENTER_FAN7_7", + "CFG_CENTER_EE2A3_10", + "CFG_CENTER_EL1BEG2_3", + "CFG_CENTER_NE2A2_14", + "CFG_CENTER_SE4BEG2_5", + "CFG_CENTER_BLOCK_OUTS_B1_4", + "CFG_CENTER_NE4BEG0_8", + "CFG_CENTER_EE4B1_12", + "CFG_CENTER_IMUX38_2", + "CFG_CENTER_IMUX1_9", + "CFG_CENTER_NE4BEG3_16", + "CFG_CENTER_WW4A2_12", + "CFG_CENTER_LOGIC_OUTS_B17_4", + "CFG_CENTER_WW2END0_4", + "CFG_CENTER_EE4C2_7", + "CFG_CENTER_LOGIC_OUTS_B19_0", + "CFG_CENTER_IMUX36_18", + "CFG_CENTER_LOGIC_OUTS_B20_16", + "CFG_CENTER_LH12_16", + "CFG_CENTER_BLOCK_OUTS_B0_7", + "CFG_CENTER_WW2A0_8", + "CFG_CENTER_LOGIC_OUTS_B22_18", + "CFG_CENTER_SW4A0_4", + "CFG_CENTER_WW2END2_18", + "CFG_CENTER_SE4BEG3_2", + "CFG_CENTER_EE4A0_6", + "CFG_CENTER_LOGIC_OUTS_B1_18", + "CFG_CENTER_SE2A3_8", + "CFG_CENTER_IMUX14_11", + "CFG_CENTER_FRAME_ECC_FAR17", + "CFG_CENTER_SW2A0_3", + "CFG_CENTER_NE4C0_6", + "CFG_CENTER_EE2A3_2", + "CFG_CENTER_LOGIC_OUTS_B19_14", + "CFG_CENTER_NE4C1_17", + "CFG_CENTER_IMUX21_2", + "CFG_CENTER_WL1END2_14", + "CFG_CENTER_ICAP1_I23", + "CFG_CENTER_EE4C2_6", + "CFG_CENTER_IMUX19_2", + "CFG_CENTER_EE4BEG3_7", + "CFG_CENTER_IMUX40_17", + "CFG_CENTER_EE4BEG2_12", + "CFG_CENTER_IMUX44_6", + "CFG_CENTER_EE4C0_7", + "CFG_CENTER_CLK0_12", + "CFG_CENTER_SW4A3_0", + "CFG_CENTER_WW4B0_3", + "CFG_CENTER_WW4C2_6", + "CFG_CENTER_LOGIC_OUTS_B12_16", + "CFG_CENTER_WW4B2_17", + "CFG_CENTER_IMUX42_5", + "CFG_CENTER_WW2END0_6", + "CFG_CENTER_NE4BEG0_18", + "CFG_CENTER_NE2A0_7", + "CFG_CENTER_WR1END0_13", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA6", + "CFG_CENTER_SE2A1_13", + "CFG_CENTER_IMUX0_13", + "CFG_CENTER_EE4A3_10", + "CFG_CENTER_LOGIC_OUTS_B7_8", + "CFG_CENTER_SW4END0_12", + "CFG_CENTER_SW2A2_15", + "CFG_CENTER_FAN1_3", + "CFG_CENTER_WW4END0_4", + "CFG_CENTER_SW4END2_16", + "CFG_CENTER_FRAME_ECC_SYNBIT2", + "CFG_CENTER_IMUX43_2", + "CFG_CENTER_LOGIC_OUTS_B20_18", + "CFG_CENTER_SW4END3_19", + "CFG_CENTER_WL1END0_2", + "CFG_CENTER_LH6_7", + "CFG_CENTER_WW2A0_1", + "CFG_CENTER_IMUX27_19", + "CFG_CENTER_LOGIC_OUTS_B21_6", + "CFG_CENTER_IMUX41_11", + "CFG_CENTER_EE2BEG2_8", + "CFG_CENTER_LH11_16", + "CFG_CENTER_ICAP1_O28", + "CFG_CENTER_LOGIC_OUTS_B21_19", + "CFG_CENTER_ICAP1_O0", + "CFG_CENTER_NE4BEG1_12", + "CFG_CENTER_FRAME_ECC_FAR19", + "CFG_CENTER_LOGIC_OUTS_B18_19", + "CFG_CENTER_IMUX17_15", + "CFG_CENTER_IMUX26_8", + "CFG_CENTER_EE4C2_3", + "CFG_CENTER_LH3_4", + "CFG_CENTER_ICAP0_I22", + "CFG_CENTER_WL1END0_15", + "CFG_CENTER_EE4C2_10", + "CFG_CENTER_WR1END0_10", + "CFG_CENTER_NE4C3_11", + "CFG_CENTER_WL1END1_17", + "CFG_CENTER_STARTUP_EOS", + "CFG_CENTER_LH9_3", + "CFG_CENTER_BYP6_0", + "CFG_CENTER_SE4C1_14", + "CFG_CENTER_LH1_14", + "CFG_CENTER_EL1BEG0_16", + "CFG_CENTER_IMUX29_9", + "CFG_CENTER_LOGIC_OUTS_B11_13", + "CFG_CENTER_IMUX30_11", + "CFG_CENTER_SE4BEG0_16", + "CFG_CENTER_WR1END2_10", + "CFG_CENTER_BYP4_14", + "CFG_CENTER_EE4C3_1", + "CFG_CENTER_WW2END2_13", + "CFG_CENTER_IMUX22_0", + "CFG_CENTER_NE2A2_7", + "CFG_CENTER_EE2A0_18", + "CFG_CENTER_LOGIC_OUTS_B7_2", + "CFG_CENTER_EE2BEG0_19", + "CFG_CENTER_SE2A2_10", + "CFG_CENTER_IMUX9_3", + "CFG_CENTER_IMUX28_5", + "CFG_CENTER_BSCAN1_TDI", + "CFG_CENTER_BYP7_2", + "CFG_CENTER_IMUX26_18", + "CFG_CENTER_WL1END2_9", + "CFG_CENTER_ICAP0_I25", + "CFG_CENTER_FRAME_ECC_SYNWORD4", + "CFG_CENTER_IMUX35_5", + "CFG_CENTER_IMUX21_18", + "CFG_CENTER_WW4C0_18", + "CFG_CENTER_WL1END3_7", + "CFG_CENTER_WW2A3_15", + "CFG_CENTER_SW2A1_4", + "CFG_CENTER_CK_IN1", + "CFG_CENTER_NE4BEG2_19", + "CFG_CENTER_IMUX13_17", + "CFG_CENTER_BYP4_0", + "CFG_CENTER_FRAME_ECC_CRCERROR", + "CFG_CENTER_NE4C1_2", + "CFG_CENTER_IMUX45_11", + "CFG_CENTER_ICAP1_I28", + "CFG_CENTER_LOGIC_OUTS_B4_16", + "CFG_CENTER_LOGIC_OUTS_B14_5", + "CFG_CENTER_CK_BUFRCLK0", + "CFG_CENTER_WW4C0_8", + "CFG_CENTER_ICAP1_CSIB", + "CFG_CENTER_LOGIC_OUTS_B16_14", + "CFG_CENTER_WW4B0_7", + "CFG_CENTER_LOGIC_OUTS_B10_10", + "CFG_CENTER_ER1BEG2_3", + "CFG_CENTER_WW4C0_16", + "CFG_CENTER_IMUX44_2", + "CFG_CENTER_EE4BEG1_8", + "CFG_CENTER_EL1BEG1_15", + "CFG_CENTER_ER1BEG1_14", + "CFG_CENTER_LOGIC_OUTS_B6_18", + "CFG_CENTER_IMUX45_19", + "CFG_CENTER_SE4BEG1_7", + "CFG_CENTER_LOGIC_OUTS_B13_6", + "CFG_CENTER_EE2BEG3_2", + "CFG_CENTER_CTRL1_11", + "CFG_CENTER_ICAP1_O19", + "CFG_CENTER_BYP5_8", + "CFG_CENTER_LOGIC_OUTS_B16_9", + "CFG_CENTER_WW4C1_6", + "CFG_CENTER_BYP6_7", + "CFG_CENTER_SE2A2_8", + "CFG_CENTER_WW2A2_11", + "CFG_CENTER_IMUX42_2", + "CFG_CENTER_EE4BEG0_4", + "CFG_CENTER_IMUX8_1", + "CFG_CENTER_NW2A1_16", + "CFG_CENTER_LOGIC_OUTS_B13_17", + "CFG_CENTER_EE2A0_12", + "CFG_CENTER_SE4BEG1_13", + "CFG_CENTER_SE4BEG3_10", + "CFG_CENTER_FAN7_15", + "CFG_CENTER_SE2A0_10", + "CFG_CENTER_EE4B1_8", + "CFG_CENTER_IMUX33_19", + "CFG_CENTER_BLOCK_OUTS_B2_15", + "CFG_CENTER_WW4A0_4", + "CFG_CENTER_CK_IN0", + "CFG_CENTER_IMUX44_17", + "CFG_CENTER_WW2A1_15", + "CFG_CENTER_IMUX7_18", + "CFG_CENTER_IMUX21_16", + "CFG_CENTER_LH7_8", + "CFG_CENTER_SW4A1_8", + "CFG_CENTER_LOGIC_OUTS_B7_0", + "CFG_CENTER_WW2END2_19", + "CFG_CENTER_EE4B3_1", + "CFG_CENTER_IMUX11_16", + "CFG_CENTER_IMUX29_14", + "CFG_CENTER_SE4BEG3_7", + "CFG_CENTER_IMUX12_18", + "CFG_CENTER_EE4B1_7", + "CFG_CENTER_EL1BEG2_2", + "CFG_CENTER_EE2A0_11", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA29", + "CFG_CENTER_FAN6_18", + "CFG_CENTER_LOGIC_OUTS_B23_6", + "CFG_CENTER_IMUX6_10", + "CFG_CENTER_NW4END0_0", + "CFG_CENTER_LOGIC_OUTS_B16_8", + "CFG_CENTER_BYP1_12", + "CFG_CENTER_FAN6_10", + "CFG_CENTER_LOGIC_OUTS_B11_7", + "CFG_CENTER_IMUX27_12", + "CFG_CENTER_CLK1_11", + "CFG_CENTER_IMUX13_8", + "CFG_CENTER_WW4END3_2", + "CFG_CENTER_IMUX8_15", + "CFG_CENTER_IMUX15_7", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA15", + "CFG_CENTER_LOGIC_OUTS_B12_8", + "CFG_CENTER_NE2A1_13", + "CFG_CENTER_WW2A1_12", + "CFG_CENTER_IMUX38_11", + "CFG_CENTER_IMUX14_1", + "CFG_CENTER_BYP7_9", + "CFG_CENTER_LH5_3", + "CFG_CENTER_NW2A3_19", + "CFG_CENTER_NE2A1_9", + "CFG_CENTER_NW4A0_9", + "CFG_CENTER_LOGIC_OUTS_B8_11", + "CFG_CENTER_SE2A1_3", + "CFG_CENTER_NW4A1_14", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA30", + "CFG_CENTER_IMUX21_1", + "CFG_CENTER_WR1END0_17", + "CFG_CENTER_SW4END1_14", + "CFG_CENTER_LOGIC_OUTS_B22_0", + "CFG_CENTER_IMUX38_16", + "CFG_CENTER_NW4END3_10", + "CFG_CENTER_WW4B2_1", + "CFG_CENTER_IMUX45_12", + "CFG_CENTER_BLOCK_OUTS_B0_11", + "CFG_CENTER_FAN1_4", + "CFG_CENTER_SW2A3_7", + "CFG_CENTER_WL1END1_18", + "CFG_CENTER_IMUX38_7", + "CFG_CENTER_NE4C1_4", + "CFG_CENTER_FRAME_ECC_FAR1", + "CFG_CENTER_IMUX3_1", + "CFG_CENTER_IMUX34_13", + "CFG_CENTER_SW4A3_7", + "CFG_CENTER_EE4A1_11", + "CFG_CENTER_LOGIC_OUTS_B1_3", + "CFG_CENTER_SE2A0_6", + "CFG_CENTER_IMUX31_11", + "CFG_CENTER_FAN5_17", + "CFG_CENTER_EE4A0_4", + "CFG_CENTER_IMUX46_5", + "CFG_CENTER_IMUX39_16", + "CFG_CENTER_SW4A0_10", + "CFG_CENTER_CLK0_7", + "CFG_CENTER_WW4C0_10", + "CFG_CENTER_LOGIC_OUTS_B19_6", + "CFG_CENTER_WW2END2_17", + "CFG_CENTER_IMUX38_18", + "CFG_CENTER_WW4C0_3", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA14", + "CFG_CENTER_EE4C0_6", + "CFG_CENTER_CLK0_9", + "CFG_CENTER_WW2END3_16", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA27", + "CFG_CENTER_LOGIC_OUTS_B10_13", + "CFG_CENTER_WW2END3_4", + "CFG_CENTER_IMUX20_19", + "CFG_CENTER_SW4A3_11", + "CFG_CENTER_LOGIC_OUTS_B14_12", + "CFG_CENTER_EE4C0_14", + "CFG_CENTER_SW4END1_13", + "CFG_CENTER_IMUX32_4", + "CFG_CENTER_WW2A1_8", + "CFG_CENTER_WW4B2_2", + "CFG_CENTER_NE2A2_13", + "CFG_CENTER_EE2A2_4", + "CFG_CENTER_IMUX7_4", + "CFG_CENTER_FRAME_ECC_FAR25", + "CFG_CENTER_NE4BEG3_11", + "CFG_CENTER_ICAP0_O9", + "CFG_CENTER_LOGIC_OUTS_B0_13", + "CFG_CENTER_IMUX13_4", + "CFG_CENTER_IMUX0_15", + "CFG_CENTER_LOGIC_OUTS_B8_18", + "CFG_CENTER_LOGIC_OUTS_B9_4", + "CFG_CENTER_LOGIC_OUTS_B23_0", + "CFG_CENTER_LOGIC_OUTS_B23_4", + "CFG_CENTER_NE4BEG3_4", + "CFG_CENTER_IMUX5_12", + "CFG_CENTER_MID_USR_ACCESS_DATA6", + "CFG_CENTER_WW2END3_14", + "CFG_CENTER_LOGIC_OUTS_B23_18", + "CFG_CENTER_SW4A0_18", + "CFG_CENTER_EE4C0_1", + "CFG_CENTER_LOGIC_OUTS_B14_14", + "CFG_CENTER_ICAP1_CLK", + "CFG_CENTER_BSCAN2_RESET", + "CFG_CENTER_CTRL0_16", + "CFG_CENTER_IMUX4_6", + "CFG_CENTER_WW2END2_6", + "CFG_CENTER_NE4BEG3_12", + "CFG_CENTER_IMUX21_0", + "CFG_CENTER_NW4END1_6", + "CFG_CENTER_SE2A2_0", + "CFG_CENTER_ER1BEG3_7", + "CFG_CENTER_IMUX16_12", + "CFG_CENTER_NW4A0_16", + "CFG_CENTER_NW4END0_6", + "CFG_CENTER_WW4END3_1", + "CFG_CENTER_IMUX8_17", + "CFG_CENTER_SE4BEG2_19", + "CFG_CENTER_LOGIC_OUTS_B3_1", + "CFG_CENTER_BYP6_16", + "CFG_CENTER_BYP1_17", + "CFG_CENTER_BYP2_12", + "CFG_CENTER_LH1_9", + "CFG_CENTER_WW4C0_9", + "CFG_CENTER_LOGIC_OUTS_B16_12", + "CFG_CENTER_ER1BEG3_11", + "CFG_CENTER_LOGIC_OUTS_B12_17", + "CFG_CENTER_IMUX16_19", + "CFG_CENTER_NE4C3_9", + "CFG_CENTER_WW4END2_1", + "CFG_CENTER_IMUX31_4", + "CFG_CENTER_NW2A1_4", + "CFG_CENTER_FAN0_4", + "CFG_CENTER_EL1BEG0_6", + "CFG_CENTER_IMUX4_7", + "CFG_CENTER_SW2A0_7", + "CFG_CENTER_EE4BEG3_15", + "CFG_CENTER_NW4A0_6", + "CFG_CENTER_EE4A1_15", + "CFG_CENTER_IMUX21_4", + "CFG_CENTER_NW4A1_0", + "CFG_CENTER_ER1BEG2_17", + "CFG_CENTER_IMUX34_15", + "CFG_CENTER_WL1END3_5", + "CFG_CENTER_SE4C2_6", + "CFG_CENTER_SW4END3_3", + "CFG_CENTER_FAN2_6", + "CFG_CENTER_IMUX4_1", + "CFG_CENTER_BYP4_13", + "CFG_CENTER_BYP1_15", + "CFG_CENTER_BYP5_12", + "CFG_CENTER_LOGIC_OUTS_B15_4", + "CFG_CENTER_NW4END2_3", + "CFG_CENTER_EE4BEG3_14", + "CFG_CENTER_EE4A3_11", + "CFG_CENTER_IMUX29_5", + "CFG_CENTER_IMUX25_0", + "CFG_CENTER_IMUX33_12", + "CFG_CENTER_WW2END0_8", + "CFG_CENTER_SE2A1_14", + "CFG_CENTER_LH6_19", + "CFG_CENTER_LH2_6", + "CFG_CENTER_LOGIC_OUTS_B5_4", + "CFG_CENTER_WL1END1_4", + "CFG_CENTER_NW4A2_1", + "CFG_CENTER_BLOCK_OUTS_B0_17", + "CFG_CENTER_IMUX4_15", + "CFG_CENTER_IMUX32_10", + "CFG_CENTER_SW4END3_11", + "CFG_CENTER_WL1END2_2", + "CFG_CENTER_WW2END0_12", + "CFG_CENTER_WW4C3_8", + "CFG_CENTER_IMUX7_7", + "CFG_CENTER_IMUX27_0", + "CFG_CENTER_NW4A0_7", + "CFG_CENTER_IMUX40_8", + "CFG_CENTER_SE4BEG0_17", + "CFG_CENTER_EE4A2_6", + "CFG_CENTER_EE4BEG3_0", + "CFG_CENTER_SE4BEG3_0", + "CFG_CENTER_ER1BEG2_12", + "CFG_CENTER_IMUX7_11", + "CFG_CENTER_NE4BEG2_18", + "CFG_CENTER_NW4A0_15", + "CFG_CENTER_NE4BEG0_14", + "CFG_CENTER_LOGIC_OUTS_B10_6", + "CFG_CENTER_IMUX0_18", + "CFG_CENTER_SE4BEG0_18", + "CFG_CENTER_SE4C1_8", + "CFG_CENTER_EE2BEG3_12", + "CFG_CENTER_NW2A2_13", + "CFG_CENTER_BSCAN3_CAPTURE", + "CFG_CENTER_USR_ACCESS_DATA8", + "CFG_CENTER_BLOCK_OUTS_B2_5", + "CFG_CENTER_WW4C3_11", + "CFG_CENTER_LH3_19", + "CFG_CENTER_EE4A2_15", + "CFG_CENTER_NE4C2_14", + "CFG_CENTER_PMVIOB_A1", + "CFG_CENTER_LOGIC_OUTS_B19_3", + "CFG_CENTER_EE4A0_5", + "CFG_CENTER_LOGIC_OUTS_B7_4", + "CFG_CENTER_ICAP1_O26", + "CFG_CENTER_IMUX6_11", + "CFG_CENTER_ICAP1_I4", + "CFG_CENTER_SW4A3_5", + "CFG_CENTER_EE2A1_7", + "CFG_CENTER_NE4BEG1_4", + "CFG_CENTER_LOGIC_OUTS_B11_8", + "CFG_CENTER_IMUX3_14", + "CFG_CENTER_LOGIC_OUTS_B22_5", + "CFG_CENTER_WW2END0_15", + "CFG_CENTER_SW2A1_3", + "CFG_CENTER_SE4BEG1_9", + "CFG_CENTER_WW4B0_18", + "CFG_CENTER_EE2BEG1_6", + "CFG_CENTER_LOGIC_OUTS_B17_13", + "CFG_CENTER_WW4C2_5", + "CFG_CENTER_NE2A3_7", + "CFG_CENTER_WW4C1_10", + "CFG_CENTER_WW2END2_2", + "CFG_CENTER_SW2A2_13", + "CFG_CENTER_IMUX33_14", + "CFG_CENTER_WR1END1_14", + "CFG_CENTER_FRAME_ECC_FAR14", + "CFG_CENTER_NE2A0_3", + "CFG_CENTER_EE2A3_8", + "CFG_CENTER_LH8_11", + "CFG_CENTER_SW4END1_18", + "CFG_CENTER_LOGIC_OUTS_B10_4", + "CFG_CENTER_WW4END2_3", + "CFG_CENTER_ER1BEG2_0", + "CFG_CENTER_IMUX27_4", + "CFG_CENTER_EE4B1_16", + "CFG_CENTER_WW4END3_15", + "CFG_CENTER_EE2BEG0_5", + "CFG_CENTER_NW2A1_17", + "CFG_CENTER_EE4B1_0", + "CFG_CENTER_CTRL1_18", + "CFG_CENTER_NW4END0_19", + "CFG_CENTER_CTRL1_7", + "CFG_CENTER_IMUX0_1", + "CFG_CENTER_LH3_1", + "CFG_CENTER_IMUX3_15", + "CFG_CENTER_SW4A3_14", + "CFG_CENTER_NW4A3_2", + "CFG_CENTER_LOGIC_OUTS_B1_13", + "CFG_CENTER_EE4BEG2_15", + "CFG_CENTER_NW2A0_1", + "CFG_CENTER_EE4B0_0", + "CFG_CENTER_ER1BEG3_8", + "CFG_CENTER_EE4B1_4", + "CFG_CENTER_EE4A2_5", + "CFG_CENTER_LH3_11", + "CFG_CENTER_FAN4_19", + "CFG_CENTER_IMUX1_10", + "CFG_CENTER_SE2A1_5", + "CFG_CENTER_EE4B1_1", + "CFG_CENTER_LOGIC_OUTS_B18_16", + "CFG_CENTER_WW4B2_10", + "CFG_CENTER_NE4BEG2_15", + "CFG_CENTER_LOGIC_OUTS_B6_12", + "CFG_CENTER_EE4B2_19", + "CFG_CENTER_WW4A1_3", + "CFG_CENTER_ICAP0_I19", + "CFG_CENTER_NE2A1_3", + "CFG_CENTER_NE4BEG0_16", + "CFG_CENTER_ICAP0_I26", + "CFG_CENTER_WW4B3_9", + "CFG_CENTER_PMVIOB_A0", + "CFG_CENTER_IMUX16_3", + "CFG_CENTER_SE4C3_1", + "CFG_CENTER_CK_IN12", + "CFG_CENTER_CLK1_8", + "CFG_CENTER_IMUX45_14", + "CFG_CENTER_LOGIC_OUTS_B7_13", + "CFG_CENTER_IMUX41_18", + "CFG_CENTER_LOGIC_OUTS_B14_17", + "CFG_CENTER_IMUX31_19", + "CFG_CENTER_LH9_7", + "CFG_CENTER_WR1END1_19", + "CFG_CENTER_EE4C2_1", + "CFG_CENTER_IMUX1_1", + "CFG_CENTER_CTRL1_15", + "CFG_CENTER_NW2A3_18", + "CFG_CENTER_CTRL1_3", + "CFG_CENTER_SE2A2_3", + "CFG_CENTER_SW2A2_5", + "CFG_CENTER_IMUX34_8", + "CFG_CENTER_SE4BEG1_15", + "CFG_CENTER_EL1BEG1_12", + "CFG_CENTER_LOGIC_OUTS_B21_18", + "CFG_CENTER_EE2BEG1_11", + "CFG_CENTER_BYP4_19", + "CFG_CENTER_LOGIC_OUTS_B0_17", + "CFG_CENTER_IMUX37_10", + "CFG_CENTER_IMUX35_6", + "CFG_CENTER_LOGIC_OUTS_B21_13", + "CFG_CENTER_BYP6_10", + "CFG_CENTER_WW4END2_17", + "CFG_CENTER_IMUX20_12", + "CFG_CENTER_IMUX20_10", + "CFG_CENTER_LH12_3", + "CFG_CENTER_IMUX30_18", + "CFG_CENTER_LOGIC_OUTS_B11_4", + "CFG_CENTER_IMUX18_5", + "CFG_CENTER_LOGIC_OUTS_B5_0", + "CFG_CENTER_CLK0_14", + "CFG_CENTER_EE4C1_2", + "CFG_CENTER_IMUX11_6", + "CFG_CENTER_SE4C3_10", + "CFG_CENTER_SE4C2_9", + "CFG_CENTER_WL1END1_15", + "CFG_CENTER_WW4C3_9", + "CFG_CENTER_BLOCK_OUTS_B1_14", + "CFG_CENTER_SW4END0_0", + "CFG_CENTER_IMUX7_13", + "CFG_CENTER_IMUX19_9", + "CFG_CENTER_NE4C3_18", + "CFG_CENTER_LOGIC_OUTS_B11_2", + "CFG_CENTER_LOGIC_OUTS_B15_6", + "CFG_CENTER_ICAP0_O3", + "CFG_CENTER_CTRL0_0", + "CFG_CENTER_BYP4_8", + "CFG_CENTER_NW2A0_13", + "CFG_CENTER_LOGIC_OUTS_B2_2", + "CFG_CENTER_IMUX11_5", + "CFG_CENTER_BSCAN3_TCK", + "CFG_CENTER_EE2BEG2_15", + "CFG_CENTER_NW4END1_5", + "CFG_CENTER_WW4B0_6", + "CFG_CENTER_EE4B1_15", + "CFG_CENTER_WR1END0_4", + "CFG_CENTER_LOGIC_OUTS_B14_0", + "CFG_CENTER_BSCAN2_UPDATE", + "CFG_CENTER_LH8_7", + "CFG_CENTER_SE4C1_4", + "CFG_CENTER_EL1BEG0_12", + "CFG_CENTER_LH2_16", + "CFG_CENTER_ICAP0_I8", + "CFG_CENTER_BYP2_13", + "CFG_CENTER_SW2A0_9", + "CFG_CENTER_NE4BEG1_18", + "CFG_CENTER_LOGIC_OUTS_B20_14", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA3", + "CFG_CENTER_IMUX46_6", + "CFG_CENTER_EE4BEG3_16", + "CFG_CENTER_WR1END0_15", + "CFG_CENTER_SE4C2_12", + "CFG_CENTER_WW2END0_3", + "CFG_CENTER_IMUX41_19", + "CFG_CENTER_WW4C3_6", + "CFG_CENTER_LOGIC_OUTS_B13_9", + "CFG_CENTER_IMUX2_8", + "CFG_CENTER_WW2A1_9", + "CFG_CENTER_WW4C2_13", + "CFG_CENTER_SE2A3_2", + "CFG_CENTER_BYP7_7", + "CFG_CENTER_SE2A0_16", + "CFG_CENTER_IMUX2_15", + "CFG_CENTER_LOGIC_OUTS_B11_16", + "CFG_CENTER_IMUX5_6", + "CFG_CENTER_IMUX32_15", + "CFG_CENTER_LH5_5", + "CFG_CENTER_ER1BEG1_15", + "CFG_CENTER_LOGIC_OUTS_B8_10", + "CFG_CENTER_FAN7_10", + "CFG_CENTER_NE4C3_7", + "CFG_CENTER_IMUX47_6", + "CFG_CENTER_SW4END1_0", + "CFG_CENTER_IMUX21_3", + "CFG_CENTER_BYP1_14", + "CFG_CENTER_EL1BEG3_3", + "CFG_CENTER_SE4BEG2_14", + "CFG_CENTER_SE4BEG0_7", + "CFG_CENTER_CLK0_4", + "CFG_CENTER_LH11_12", + "CFG_CENTER_WW4END2_13", + "CFG_CENTER_NW4A3_13", + "CFG_CENTER_IMUX27_9", + "CFG_CENTER_SW4A1_18", + "CFG_CENTER_EL1BEG0_0", + "CFG_CENTER_EE2BEG0_7", + "CFG_CENTER_ICAP1_I25", + "CFG_CENTER_LOGIC_OUTS_B8_0", + "CFG_CENTER_ICAP0_O22", + "CFG_CENTER_LOGIC_OUTS_B11_11", + "CFG_CENTER_EE4B0_2", + "CFG_CENTER_FAN5_3", + "CFG_CENTER_WL1END3_18", + "CFG_CENTER_LH12_9", + "CFG_CENTER_LH6_17", + "CFG_CENTER_EE4BEG0_13", + "CFG_CENTER_IMUX43_16", + "CFG_CENTER_EE4C2_11", + "CFG_CENTER_IMUX17_16", + "CFG_CENTER_NE4BEG0_3", + "CFG_CENTER_SE4C2_1", + "CFG_CENTER_SW2A2_14", + "CFG_CENTER_IMUX28_17", + "CFG_CENTER_EL1BEG0_2", + "CFG_CENTER_CTRL1_0", + "CFG_CENTER_FAN7_9", + "CFG_CENTER_LOGIC_OUTS_B19_4", + "CFG_CENTER_BLOCK_OUTS_B3_15", + "CFG_CENTER_NW4A0_0", + "CFG_CENTER_WW4B3_16", + "CFG_CENTER_IMUX6_1", + "CFG_CENTER_WW4C2_18", + "CFG_CENTER_IMUX39_4", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA8", + "CFG_CENTER_FRAME_ECC_SYNDROME4", + "CFG_CENTER_CK_BUFHCLK7", + "CFG_CENTER_EE2BEG1_3", + "CFG_CENTER_EE4B3_19", + "CFG_CENTER_WW4END2_0", + "CFG_CENTER_SE2A3_10", + "CFG_CENTER_EE2A2_19", + "CFG_CENTER_USR_ACCESS_DATA11", + "CFG_CENTER_IMUX26_10", + "CFG_CENTER_WW4END2_14", + "CFG_CENTER_NE2A3_6", + "CFG_CENTER_ER1BEG1_12", + "CFG_CENTER_CLK1_10", + "CFG_CENTER_WW4END0_14", + "CFG_CENTER_BLOCK_OUTS_B0_1", + "CFG_CENTER_SW4A1_16", + "CFG_CENTER_IMUX29_8", + "CFG_CENTER_IMUX37_13", + "CFG_CENTER_SW4END0_2", + "CFG_CENTER_IMUX40_10", + "CFG_CENTER_LH5_14", + "CFG_CENTER_MID_USR_ACCESS_DATA14", + "CFG_CENTER_LOGIC_OUTS_B10_9", + "CFG_CENTER_FAN1_9", + "CFG_CENTER_NW4A0_17", + "CFG_CENTER_WW4A2_11", + "CFG_CENTER_EE2A3_13", + "CFG_CENTER_BSCAN2_TDI", + "CFG_CENTER_STARTUP_CFGCLK", + "CFG_CENTER_LH3_8", + "CFG_CENTER_FRAME_ECC_SYNBIT3", + "CFG_CENTER_EL1BEG1_18", + "CFG_CENTER_NW4END0_5", + "CFG_CENTER_LOGIC_OUTS_B19_16", + "CFG_CENTER_SE4C1_1", + "CFG_CENTER_EL1BEG0_4", + "CFG_CENTER_EE2BEG1_18", + "CFG_CENTER_IMUX3_19", + "CFG_CENTER_LH10_14", + "CFG_CENTER_USR_ACCESS_DATA21", + "CFG_CENTER_IMUX44_5", + "CFG_CENTER_WW4C1_16", + "CFG_CENTER_IMUX21_11", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA19", + "CFG_CENTER_IMUX35_15", + "CFG_CENTER_NE4C2_4", + "CFG_CENTER_BLOCK_OUTS_B0_0", + "CFG_CENTER_ER1BEG1_13", + "CFG_CENTER_SW4END2_7", + "CFG_CENTER_ICAP1_O14", + "CFG_CENTER_IMUX8_6", + "CFG_CENTER_WW4B3_17", + "CFG_CENTER_NW4A2_16", + "CFG_CENTER_ER1BEG2_7", + "CFG_CENTER_WW4A1_2", + "CFG_CENTER_LOGIC_OUTS_B4_12", + "CFG_CENTER_WW2A2_6", + "CFG_CENTER_IMUX5_14", + "CFG_CENTER_IMUX24_2", + "CFG_CENTER_EE4BEG3_9", + "CFG_CENTER_FRAME_ECC_FAR10", + "CFG_CENTER_ER1BEG1_1", + "CFG_CENTER_BYP0_16", + "CFG_CENTER_EE4BEG0_18", + "CFG_CENTER_SW4A1_5", + "CFG_CENTER_IMUX2_11", + "CFG_CENTER_SW2A1_11", + "CFG_CENTER_ER1BEG1_2", + "CFG_CENTER_WR1END0_12", + "CFG_CENTER_IMUX10_16", + "CFG_CENTER_EL1BEG2_9", + "CFG_CENTER_NE4C3_3", + "CFG_CENTER_WR1END2_15", + "CFG_CENTER_IMUX31_6", + "CFG_CENTER_EE2BEG0_14", + "CFG_CENTER_BYP2_6", + "CFG_CENTER_SE4C1_0", + "CFG_CENTER_WW4B3_0", + "CFG_CENTER_CLK0_18", + "CFG_CENTER_FAN6_14", + "CFG_CENTER_FAN4_2", + "CFG_CENTER_WW4END1_16", + "CFG_CENTER_WW4END2_12", + "CFG_CENTER_WW4A3_15", + "CFG_CENTER_FRAME_ECC_SYNDROME7", + "CFG_CENTER_NW4A0_1", + "CFG_CENTER_FRAME_ECC_FAR23", + "CFG_CENTER_SE2A3_17", + "CFG_CENTER_FAN0_2", + "CFG_CENTER_BYP5_13", + "CFG_CENTER_FRAME_ECC_SYNDROME6", + "CFG_CENTER_SE2A1_11", + "CFG_CENTER_LH7_1", + "CFG_CENTER_SE4BEG1_12", + "CFG_CENTER_BLOCK_OUTS_B2_19", + "CFG_CENTER_EE2BEG3_11", + "CFG_CENTER_WW4A1_19", + "CFG_CENTER_WW2END1_14", + "CFG_CENTER_BYP0_8", + "CFG_CENTER_WW2END1_17", + "CFG_CENTER_LH1_8", + "CFG_CENTER_LOGIC_OUTS_B21_12", + "CFG_CENTER_SW2A0_17", + "CFG_CENTER_BYP7_14", + "CFG_CENTER_WW2A3_19", + "CFG_CENTER_SE4BEG0_3", + "CFG_CENTER_IMUX22_11", + "CFG_CENTER_NW4A3_12", + "CFG_CENTER_SE4C1_10", + "CFG_CENTER_ICAP1_O15", + "CFG_CENTER_IMUX28_11", + "CFG_CENTER_EE2A3_3", + "CFG_CENTER_FAN7_13", + "CFG_CENTER_WW4B2_16", + "CFG_CENTER_SW4A0_16", + "CFG_CENTER_EE4C0_8", + "CFG_CENTER_ER1BEG1_3", + "CFG_CENTER_LH12_1", + "CFG_CENTER_PMVIOB_O", + "CFG_CENTER_WW4END0_5", + "CFG_CENTER_IMUX26_15", + "CFG_CENTER_EE4BEG2_6", + "CFG_CENTER_NW2A1_5", + "CFG_CENTER_LH3_14", + "CFG_CENTER_FAN6_16", + "CFG_CENTER_SE4BEG0_4", + "CFG_CENTER_LOGIC_OUTS_B5_3", + "CFG_CENTER_IMUX11_14", + "CFG_CENTER_ICAP1_I29", + "CFG_CENTER_WW2END3_8", + "CFG_CENTER_SW2A1_15", + "CFG_CENTER_WR1END3_17", + "CFG_CENTER_WW4END3_8", + "CFG_CENTER_IMUX31_15", + "CFG_CENTER_LOGIC_OUTS_B0_5", + "CFG_CENTER_SW4A2_4", + "CFG_CENTER_EE4A0_8", + "CFG_CENTER_IMUX15_9", + "CFG_CENTER_WW4B3_4", + "CFG_CENTER_NE4C1_3", + "CFG_CENTER_NW2A3_8", + "CFG_CENTER_LH5_17", + "CFG_CENTER_SE4C1_17", + "CFG_CENTER_IMUX47_0", + "CFG_CENTER_WL1END2_3", + "CFG_CENTER_ICAP1_I21", + "CFG_CENTER_LOGIC_OUTS_B12_3", + "CFG_CENTER_STARTUP_CLK", + "CFG_CENTER_WW4B3_19", + "CFG_CENTER_MID_CFG_IO_ACCESS_VGGCOMPOUT", + "CFG_CENTER_LOGIC_OUTS_B2_16", + "CFG_CENTER_EE2BEG0_4", + "CFG_CENTER_BLOCK_OUTS_B3_18", + "CFG_CENTER_IMUX34_14", + "CFG_CENTER_LH7_5", + "CFG_CENTER_IMUX34_2", + "CFG_CENTER_SE4BEG3_13", + "CFG_CENTER_LH4_7", + "CFG_CENTER_IMUX2_18", + "CFG_CENTER_BSCAN1_TDO", + "CFG_CENTER_IMUX44_12", + "CFG_CENTER_ER1BEG3_17", + "CFG_CENTER_EE4B1_18", + "CFG_CENTER_BYP7_16", + "CFG_CENTER_WL1END3_19", + "CFG_CENTER_LH9_17", + "CFG_CENTER_WW4B3_13", + "CFG_CENTER_BSCAN4_SEL", + "CFG_CENTER_NE4C2_16", + "CFG_CENTER_EE4A1_4", + "CFG_CENTER_EE2A0_1", + "CFG_CENTER_BYP1_2", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA19", + "CFG_CENTER_IMUX37_12", + "CFG_CENTER_CTRL0_6", + "CFG_CENTER_IMUX36_19", + "CFG_CENTER_IMUX33_7", + "CFG_CENTER_NE4C1_8", + "CFG_CENTER_LH4_17", + "CFG_CENTER_EE2A1_12", + "CFG_CENTER_WW4C3_17", + "CFG_CENTER_WW4C1_7", + "CFG_CENTER_LH3_12", + "CFG_CENTER_WW2END0_14", + "CFG_CENTER_IMUX15_14", + "CFG_CENTER_NW4A2_11", + "CFG_CENTER_WW4A3_14", + "CFG_CENTER_LOGIC_OUTS_B3_17", + "CFG_CENTER_IMUX22_10", + "CFG_CENTER_CTRL1_12", + "CFG_CENTER_WW4A3_16", + "CFG_CENTER_ICAP0_O16", + "CFG_CENTER_WW4C0_19", + "CFG_CENTER_SW2A2_3", + "CFG_CENTER_IMUX17_1", + "CFG_CENTER_IMUX18_7", + "CFG_CENTER_EE4A1_18", + "CFG_CENTER_BYP4_11", + "CFG_CENTER_LOGIC_OUTS_B6_7", + "CFG_CENTER_SE2A3_5", + "CFG_CENTER_IMUX6_4", + "CFG_CENTER_NW4END1_8", + "CFG_CENTER_IMUX27_14", + "CFG_CENTER_NW4END0_1", + "CFG_CENTER_FAN2_0", + "CFG_CENTER_WW4B0_0", + "CFG_CENTER_BYP5_0", + "CFG_CENTER_NE4C2_7", + "CFG_CENTER_WL1END0_17", + "CFG_CENTER_BYP1_18", + "CFG_CENTER_WW4A2_18", + "CFG_CENTER_MID_USR_ACCESS_DATA12", + "CFG_CENTER_IMUX12_17", + "CFG_CENTER_BYP2_5", + "CFG_CENTER_LOGIC_OUTS_B15_8", + "CFG_CENTER_WW4A1_1", + "CFG_CENTER_IMUX21_7", + "CFG_CENTER_NE4C1_16", + "CFG_CENTER_CTRL0_4", + "CFG_CENTER_EL1BEG3_6", + "CFG_CENTER_LOGIC_OUTS_B3_16", + "CFG_CENTER_BLOCK_OUTS_B1_0", + "CFG_CENTER_IMUX1_4", + "CFG_CENTER_EE2BEG1_4", + "CFG_CENTER_BYP3_10", + "CFG_CENTER_WL1END2_13", + "CFG_CENTER_ER1BEG3_9", + "CFG_CENTER_WL1END0_1", + "CFG_CENTER_FAN0_18", + "CFG_CENTER_EL1BEG3_16", + "CFG_CENTER_LH10_9", + "CFG_CENTER_EE2BEG1_16", + "CFG_CENTER_SW4A0_3", + "CFG_CENTER_EE2BEG2_13", + "CFG_CENTER_IMUX46_8", + "CFG_CENTER_EL1BEG0_17", + "CFG_CENTER_EE4BEG1_18", + "CFG_CENTER_WW2END1_19", + "CFG_CENTER_WW4C1_1", + "CFG_CENTER_SE2A3_0", + "CFG_CENTER_SW4A2_16", + "CFG_CENTER_WW2A3_17", + "CFG_CENTER_WW4A3_4", + "CFG_CENTER_IMUX21_12", + "CFG_CENTER_WW4B0_11", + "CFG_CENTER_LOGIC_OUTS_B8_3", + "CFG_CENTER_IMUX12_10", + "CFG_CENTER_LOGIC_OUTS_B7_19", + "CFG_CENTER_IMUX6_3", + "CFG_CENTER_NW2A3_3", + "CFG_CENTER_WR1END0_3", + "CFG_CENTER_LOGIC_OUTS_B23_13", + "CFG_CENTER_EE2BEG2_10", + "CFG_CENTER_SW4A0_7", + "CFG_CENTER_WW4END1_6", + "CFG_CENTER_EE4C1_9", + "CFG_CENTER_LOGIC_OUTS_B3_13", + "CFG_CENTER_SW4END3_12", + "CFG_CENTER_LH3_9", + "CFG_CENTER_IMUX29_19", + "CFG_CENTER_BYP1_19", + "CFG_CENTER_CK_IN5", + "CFG_CENTER_IMUX18_17", + "CFG_CENTER_WW4B1_4", + "CFG_CENTER_BYP2_16", + "CFG_CENTER_NW4END2_13", + "CFG_CENTER_LH3_17", + "CFG_CENTER_IMUX13_10", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA31", + "CFG_CENTER_LOGIC_OUTS_B0_2", + "CFG_CENTER_EE4B1_14", + "CFG_CENTER_IMUX33_5", + "CFG_CENTER_IMUX44_16", + "CFG_CENTER_IMUX24_15", + "CFG_CENTER_EE4A2_14", + "CFG_CENTER_NE4BEG0_17", + "CFG_CENTER_LH4_11", + "CFG_CENTER_EE4C2_9", + "CFG_CENTER_SW4A3_18", + "CFG_CENTER_SW4A3_13", + "CFG_CENTER_WR1END3_6", + "CFG_CENTER_WR1END3_8", + "CFG_CENTER_IMUX22_8", + "CFG_CENTER_NE2A0_0", + "CFG_CENTER_LOGIC_OUTS_B15_13", + "CFG_CENTER_LOGIC_OUTS_B11_1", + "CFG_CENTER_BYP4_1", + "CFG_CENTER_IMUX31_0", + "CFG_CENTER_BYP6_8", + "CFG_CENTER_SE2A0_8", + "CFG_CENTER_NW4END0_3", + "CFG_CENTER_LOGIC_OUTS_B6_14", + "CFG_CENTER_EE4BEG0_16", + "CFG_CENTER_LOGIC_OUTS_B2_3", + "CFG_CENTER_FRAME_ECC_SYNWORD0", + "CFG_CENTER_LOGIC_OUTS_B19_9", + "CFG_CENTER_IMUX13_9", + "CFG_CENTER_FAN1_18", + "CFG_CENTER_LOGIC_OUTS_B9_6", + "CFG_CENTER_EE2BEG3_17", + "CFG_CENTER_NW4A2_5", + "CFG_CENTER_ICAP0_RDWRB", + "CFG_CENTER_LH9_0", + "CFG_CENTER_WL1END1_7", + "CFG_CENTER_IMUX26_13", + "CFG_CENTER_WW4C0_12", + "CFG_CENTER_WW4END3_3", + "CFG_CENTER_SW4END1_12", + "CFG_CENTER_EE4BEG2_5", + "CFG_CENTER_BYP0_12", + "CFG_CENTER_BYP5_1", + "CFG_CENTER_FRAME_ECC_SYNBIT1", + "CFG_CENTER_NE4BEG3_8", + "CFG_CENTER_IMUX26_2", + "CFG_CENTER_IMUX12_6", + "CFG_CENTER_BLOCK_OUTS_B3_13", + "CFG_CENTER_NE4BEG0_10", + "CFG_CENTER_LH2_3", + "CFG_CENTER_EE2BEG3_15", + "CFG_CENTER_NW4A2_2", + "CFG_CENTER_WW2END1_3", + "CFG_CENTER_ICAP0_O2", + "CFG_CENTER_ICAP0_O17", + "CFG_CENTER_FAN6_5", + "CFG_CENTER_BSCAN4_DRCK", + "CFG_CENTER_WW2END1_11", + "CFG_CENTER_SE4C3_12", + "CFG_CENTER_IMUX37_2", + "CFG_CENTER_SW2A3_4", + "CFG_CENTER_FAN0_3", + "CFG_CENTER_EE2A3_14", + "CFG_CENTER_IMUX7_5", + "CFG_CENTER_EE4B3_9", + "CFG_CENTER_IMUX1_3", + "CFG_CENTER_IMUX26_9", + "CFG_CENTER_FAN0_10", + "CFG_CENTER_IMUX37_7", + "CFG_CENTER_NE4BEG0_19", + "CFG_CENTER_NE4BEG3_2", + "CFG_CENTER_FRAME_ECC_FAR21", + "CFG_CENTER_FAN1_5", + "CFG_CENTER_LH3_6", + "CFG_CENTER_EE2A2_1", + "CFG_CENTER_NW4A0_13", + "CFG_CENTER_ICAP1_I1", + "CFG_CENTER_IMUX4_9", + "CFG_CENTER_ER1BEG0_5", + "CFG_CENTER_EE4B2_1", + "CFG_CENTER_IMUX26_16", + "CFG_CENTER_EE4C1_6", + "CFG_CENTER_SE4BEG1_16", + "CFG_CENTER_BYP2_19", + "CFG_CENTER_BYP5_18", + "CFG_CENTER_NW4END0_14", + "CFG_CENTER_EE2A2_0", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA2", + "CFG_CENTER_LOGIC_OUTS_B17_15", + "CFG_CENTER_SW4END1_2", + "CFG_CENTER_EE4C1_18", + "CFG_CENTER_LH6_14", + "CFG_CENTER_IMUX15_19", + "CFG_CENTER_LOGIC_OUTS_B13_15", + "CFG_CENTER_WR1END3_10", + "CFG_CENTER_EE2A1_6", + "CFG_CENTER_EE2BEG2_14", + "CFG_CENTER_EE4A3_4", + "CFG_CENTER_NE4BEG3_1", + "CFG_CENTER_EE4B0_16", + "CFG_CENTER_ICAP1_O10", + "CFG_CENTER_IMUX38_4", + "CFG_CENTER_IMUX39_11", + "CFG_CENTER_FAN7_3", + "CFG_CENTER_LOGIC_OUTS_B4_5", + "CFG_CENTER_USR_ACCESS_DATA30", + "CFG_CENTER_IMUX47_9", + "CFG_CENTER_EE2A2_11", + "CFG_CENTER_BSCAN1_RUNTEST", + "CFG_CENTER_LOGIC_OUTS_B4_15", + "CFG_CENTER_NW4END1_10", + "CFG_CENTER_EE2A3_11", + "CFG_CENTER_CLK0_13", + "CFG_CENTER_NW4END0_12", + "CFG_CENTER_LH8_14", + "CFG_CENTER_EE4BEG1_1", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA25", + "CFG_CENTER_ER1BEG1_7", + "CFG_CENTER_EL1BEG2_19", + "CFG_CENTER_WW4END0_2", + "CFG_CENTER_EE4C1_8", + "CFG_CENTER_LOGIC_OUTS_B22_15", + "CFG_CENTER_BYP3_4", + "CFG_CENTER_WW2A2_10", + "CFG_CENTER_LOGIC_OUTS_B3_0", + "CFG_CENTER_LOGIC_OUTS_B23_17", + "CFG_CENTER_IMUX16_13", + "CFG_CENTER_SW4A2_10", + "CFG_CENTER_IMUX1_17", + "CFG_CENTER_LOGIC_OUTS_B7_14", + "CFG_CENTER_FAN0_6", + "CFG_CENTER_EE4A0_18", + "CFG_CENTER_IMUX3_18", + "CFG_CENTER_IMUX7_9", + "CFG_CENTER_IMUX0_11", + "CFG_CENTER_IMUX33_4", + "CFG_CENTER_IMUX34_16", + "CFG_CENTER_IMUX20_9", + "CFG_CENTER_SW2A1_6", + "CFG_CENTER_LOGIC_OUTS_B11_3", + "CFG_CENTER_IMUX0_17", + "CFG_CENTER_IMUX34_11", + "CFG_CENTER_EE2A3_0", + "CFG_CENTER_LH5_6", + "CFG_CENTER_FAN7_18", + "CFG_CENTER_SW4END3_10", + "CFG_CENTER_NE4C3_2", + "CFG_CENTER_WW2A2_13", + "CFG_CENTER_NW4A3_9", + "CFG_CENTER_NE2A0_8", + "CFG_CENTER_EE4B2_17", + "CFG_CENTER_EE4B1_2", + "CFG_CENTER_LH1_18", + "CFG_CENTER_BYP3_2", + "CFG_CENTER_SE4BEG3_6", + "CFG_CENTER_FAN5_0", + "CFG_CENTER_LOGIC_OUTS_B23_7", + "CFG_CENTER_BYP2_4", + "CFG_CENTER_ICAP1_I7", + "CFG_CENTER_BLOCK_OUTS_B2_4", + "CFG_CENTER_WW2END2_11", + "CFG_CENTER_ICAP1_I0", + "CFG_CENTER_NW2A1_11", + "CFG_CENTER_IMUX10_2", + "CFG_CENTER_CTRL0_7", + "CFG_CENTER_IMUX33_11", + "CFG_CENTER_FAN3_8", + "CFG_CENTER_WW4C3_2", + "CFG_CENTER_EL1BEG2_12", + "CFG_CENTER_LOGIC_OUTS_B11_12", + "CFG_CENTER_EE4BEG3_11", + "CFG_CENTER_EE4A2_10", + "CFG_CENTER_IMUX25_1", + "CFG_CENTER_IMUX5_15", + "CFG_CENTER_BLOCK_OUTS_B2_18", + "CFG_CENTER_EE4A2_3", + "CFG_CENTER_EE4BEG2_14", + "CFG_CENTER_IMUX9_15", + "CFG_CENTER_WW2A2_18", + "CFG_CENTER_NW4END0_11", + "CFG_CENTER_NW4A2_14", + "CFG_CENTER_EE2A0_0", + "CFG_CENTER_WW2A3_14", + "CFG_CENTER_IMUX18_16", + "CFG_CENTER_LH2_17", + "CFG_CENTER_IMUX29_11", + "CFG_CENTER_PMVIOB_ODIV2", + "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE", + "CFG_CENTER_ER1BEG0_18", + "CFG_CENTER_EE2A0_10", + "CFG_CENTER_EE4C3_10", + "CFG_CENTER_ER1BEG0_16", + "CFG_CENTER_LH5_10", + "CFG_CENTER_EE2A1_11", + "CFG_CENTER_IMUX47_16", + "CFG_CENTER_SE4C3_0", + "CFG_CENTER_LH2_14", + "CFG_CENTER_NW2A2_6", + "CFG_CENTER_IMUX1_8", + "CFG_CENTER_IMUX31_2", + "CFG_CENTER_NE4BEG1_7", + "CFG_CENTER_EE4A1_16", + "CFG_CENTER_BYP4_9", + "CFG_CENTER_ICAP1_O2", + "CFG_CENTER_LOGIC_OUTS_B15_10", + "CFG_CENTER_BYP0_11", + "CFG_CENTER_IMUX5_19", + "CFG_CENTER_EE2BEG1_19", + "CFG_CENTER_SE4BEG2_9", + "CFG_CENTER_LOGIC_OUTS_B2_11", + "CFG_CENTER_NW4END3_14", + "CFG_CENTER_SW2A2_8", + "CFG_CENTER_EE2BEG3_5", + "CFG_CENTER_EE4A0_3", + "CFG_CENTER_LH1_0", + "CFG_CENTER_LOGIC_OUTS_B23_19", + "CFG_CENTER_ER1BEG2_19", + "CFG_CENTER_IMUX36_17", + "CFG_CENTER_BLOCK_OUTS_B3_2", + "CFG_CENTER_LOGIC_OUTS_B18_2", + "CFG_CENTER_IMUX8_18", + "CFG_CENTER_CK_IN10", + "CFG_CENTER_EE2BEG3_19", + "CFG_CENTER_IMUX40_19", + "CFG_CENTER_MID_USR_ACCESS_DATA10", + "CFG_CENTER_SW4END0_9", + "CFG_CENTER_EE2BEG3_7", + "CFG_CENTER_EL1BEG1_19", + "CFG_CENTER_WW2A2_19", + "CFG_CENTER_WW4C1_17", + "CFG_CENTER_LOGIC_OUTS_B10_18", + "CFG_CENTER_EE4C0_16", + "CFG_CENTER_NE4BEG1_19", + "CFG_CENTER_IMUX34_17", + "CFG_CENTER_LOGIC_OUTS_B2_5", + "CFG_CENTER_NW4END0_16", + "CFG_CENTER_EE4BEG1_16", + "CFG_CENTER_IMUX10_18", + "CFG_CENTER_LOGIC_OUTS_B8_1", + "CFG_CENTER_LOGIC_OUTS_B14_19", + "CFG_CENTER_NE4BEG2_12", + "CFG_CENTER_EE4B2_3", + "CFG_CENTER_IMUX5_11", + "CFG_CENTER_LH3_16", + "CFG_CENTER_LH3_0", + "CFG_CENTER_IMUX29_17", + "CFG_CENTER_LOGIC_OUTS_B16_16", + "CFG_CENTER_IMUX0_10", + "CFG_CENTER_USR_ACCESS_DATA19", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA23", + "CFG_CENTER_EL1BEG2_14", + "CFG_CENTER_IMUX29_13", + "CFG_CENTER_CTRL1_13", + "CFG_CENTER_IMUX8_9", + "CFG_CENTER_IMUX23_2", + "CFG_CENTER_LOGIC_OUTS_B6_11", + "CFG_CENTER_WW4END1_1", + "CFG_CENTER_LOGIC_OUTS_B5_10", + "CFG_CENTER_ICAP0_O28", + "CFG_CENTER_IMUX42_13", + "CFG_CENTER_IMUX4_10", + "CFG_CENTER_NW2A0_19", + "CFG_CENTER_LH10_15", + "CFG_CENTER_USR_ACCESS_DATA4", + "CFG_CENTER_ICAP0_O24", + "CFG_CENTER_LH6_1", + "CFG_CENTER_WW4B0_15", + "CFG_CENTER_LH6_3", + "CFG_CENTER_LOGIC_OUTS_B19_15", + "CFG_CENTER_LOGIC_OUTS_B2_9", + "CFG_CENTER_SE2A0_4", + "CFG_CENTER_SW4END3_4", + "CFG_CENTER_ER1BEG0_4", + "CFG_CENTER_IMUX18_18", + "CFG_CENTER_WR1END2_14", + "CFG_CENTER_EE4C2_16", + "CFG_CENTER_BYP4_10", + "CFG_CENTER_IMUX30_2", + "CFG_CENTER_IMUX43_4", + "CFG_CENTER_LOGIC_OUTS_B10_2", + "CFG_CENTER_IMUX5_1", + "CFG_CENTER_BYP6_17", + "CFG_CENTER_EE4A2_8", + "CFG_CENTER_NE4C3_8", + "CFG_CENTER_IMUX23_9", + "CFG_CENTER_EE4BEG3_12", + "CFG_CENTER_LH10_8", + "CFG_CENTER_LOGIC_OUTS_B2_7", + "CFG_CENTER_IMUX44_19", + "CFG_CENTER_WW4B1_2", + "CFG_CENTER_IMUX31_16", + "CFG_CENTER_IMUX2_7", + "CFG_CENTER_IMUX16_14", + "CFG_CENTER_IMUX10_14", + "CFG_CENTER_EE4C3_4", + "CFG_CENTER_FAN7_6", + "CFG_CENTER_SW4END0_10", + "CFG_CENTER_EE4A3_2", + "CFG_CENTER_WR1END1_17", + "CFG_CENTER_NE2A2_5", + "CFG_CENTER_WW2A3_5", + "CFG_CENTER_IMUX27_18", + "CFG_CENTER_IMUX18_15", + "CFG_CENTER_CFG_IO_ACCESS_MODE0", + "CFG_CENTER_LOGIC_OUTS_B15_15", + "CFG_CENTER_NW4A2_18", + "CFG_CENTER_IMUX14_17", + "CFG_CENTER_FAN0_17", + "CFG_CENTER_LOGIC_OUTS_B6_10", + "CFG_CENTER_IMUX15_8", + "CFG_CENTER_IMUX9_11", + "CFG_CENTER_WW4A0_12", + "CFG_CENTER_IMUX40_14", + "CFG_CENTER_IMUX30_5", + "CFG_CENTER_WW2A2_16", + "CFG_CENTER_WW4C0_5", + "CFG_CENTER_IMUX20_11", + "CFG_CENTER_ER1BEG0_19", + "CFG_CENTER_SE4BEG2_1", + "CFG_CENTER_LOGIC_OUTS_B9_10", + "CFG_CENTER_EL1BEG1_3", + "CFG_CENTER_WR1END1_0", + "CFG_CENTER_WW4B1_14", + "CFG_CENTER_WW4A0_14", + "CFG_CENTER_ICAP0_I21", + "CFG_CENTER_LOGIC_OUTS_B19_10", + "CFG_CENTER_FAN3_12", + "CFG_CENTER_IMUX41_0", + "CFG_CENTER_IMUX4_19", + "CFG_CENTER_NW2A2_17", + "CFG_CENTER_BLOCK_OUTS_B2_6", + "CFG_CENTER_SW2A1_8", + "CFG_CENTER_SW4A0_9", + "CFG_CENTER_LOGIC_OUTS_B21_9", + "CFG_CENTER_SE4BEG1_17", + "CFG_CENTER_IMUX40_6", + "CFG_CENTER_ICAP1_I6", + "CFG_CENTER_IMUX10_12", + "CFG_CENTER_CTRL0_19", + "CFG_CENTER_IMUX6_13", + "CFG_CENTER_SE4BEG2_15", + "CFG_CENTER_SE4C1_5", + "CFG_CENTER_LOGIC_OUTS_B0_0", + "CFG_CENTER_NW2A3_13", + "CFG_CENTER_FAN3_17", + "CFG_CENTER_WL1END2_11", + "CFG_CENTER_CLK0_19", + "CFG_CENTER_LH5_7", + "CFG_CENTER_WW4C1_14", + "CFG_CENTER_IMUX22_19", + "CFG_CENTER_IMUX14_0", + "CFG_CENTER_ICAP1_O4", + "CFG_CENTER_ICAP0_O11", + "CFG_CENTER_EE2BEG3_1", + "CFG_CENTER_SE2A3_16", + "CFG_CENTER_WL1END2_1", + "CFG_CENTER_IMUX40_4", + "CFG_CENTER_IMUX1_18", + "CFG_CENTER_IMUX42_9", + "CFG_CENTER_NW4A1_12", + "CFG_CENTER_NW4END3_5", + "CFG_CENTER_LOGIC_OUTS_B0_6", + "CFG_CENTER_LOGIC_OUTS_B11_5", + "CFG_CENTER_LH1_13", + "CFG_CENTER_WW4A3_6", + "CFG_CENTER_IMUX28_10", + "CFG_CENTER_WW2A3_11", + "CFG_CENTER_LOGIC_OUTS_B21_8", + "CFG_CENTER_LOGIC_OUTS_B14_7", + "CFG_CENTER_LOGIC_OUTS_B7_5", + "CFG_CENTER_ER1BEG1_9", + "CFG_CENTER_SE2A2_1", + "CFG_CENTER_MID_USR_ACCESS_DATA9", + "CFG_CENTER_BYP5_19", + "CFG_CENTER_NW2A1_19", + "CFG_CENTER_SE4BEG2_6", + "CFG_CENTER_WW4B3_12", + "CFG_CENTER_WW4A3_19", + "CFG_CENTER_IMUX32_2", + "CFG_CENTER_LOGIC_OUTS_B17_10", + "CFG_CENTER_LOGIC_OUTS_B18_3", + "CFG_CENTER_SE4C2_7", + "CFG_CENTER_IMUX15_5", + "CFG_CENTER_CTRL1_5", + "CFG_CENTER_IMUX22_13", + "CFG_CENTER_IMUX30_19", + "CFG_CENTER_BYP2_8", + "CFG_CENTER_BYP5_11", + "CFG_CENTER_SW4A2_13", + "CFG_CENTER_IMUX35_14", + "CFG_CENTER_EE2A2_12", + "CFG_CENTER_LH4_1", + "CFG_CENTER_LOGIC_OUTS_B21_11", + "CFG_CENTER_ICAP0_I6", + "CFG_CENTER_WL1END3_10", + "CFG_CENTER_SE2A1_12", + "CFG_CENTER_EE4B0_8", + "CFG_CENTER_SE4BEG3_15", + "CFG_CENTER_LH4_3", + "CFG_CENTER_SE4C3_6", + "CFG_CENTER_EE4C3_0", + "CFG_CENTER_IMUX44_11", + "CFG_CENTER_IMUX40_11", + "CFG_CENTER_LOGIC_OUTS_B20_15", + "CFG_CENTER_WW4A1_0", + "CFG_CENTER_BLOCK_OUTS_B0_4", + "CFG_CENTER_WW4END1_11", + "CFG_CENTER_LOGIC_OUTS_B9_3", + "CFG_CENTER_BSCAN3_TDO", + "CFG_CENTER_BYP7_13", + "CFG_CENTER_FRAME_ECC_SYNWORD3", + "CFG_CENTER_EE4BEG3_6", + "CFG_CENTER_IMUX47_10", + "CFG_CENTER_LH10_16", + "CFG_CENTER_IMUX23_12", + "CFG_CENTER_SW4END3_16", + "CFG_CENTER_WW4END1_17", + "CFG_CENTER_SW4END2_12", + "CFG_CENTER_BYP1_4", + "CFG_CENTER_LOGIC_OUTS_B8_6", + "CFG_CENTER_FRAME_ECC_FAR18", + "CFG_CENTER_SW4END3_8", + "CFG_CENTER_IMUX10_1", + "CFG_CENTER_LOGIC_OUTS_B5_12", + "CFG_CENTER_EE4C3_7", + "CFG_CENTER_LH4_13", + "CFG_CENTER_LOGIC_OUTS_B10_7", + "CFG_CENTER_SW2A3_5", + "CFG_CENTER_IMUX36_0", + "CFG_CENTER_CTRL1_8", + "CFG_CENTER_FAN2_12", + "CFG_CENTER_ICAP1_I22", + "CFG_CENTER_LOGIC_OUTS_B6_1", + "CFG_CENTER_SW4A3_4", + "CFG_CENTER_WW2A0_9", + "CFG_CENTER_BLOCK_OUTS_B3_16", + "CFG_CENTER_BSCAN4_TDI", + "CFG_CENTER_BYP4_3", + "CFG_CENTER_IMUX3_0", + "CFG_CENTER_LOGIC_OUTS_B15_19", + "CFG_CENTER_SE2A3_1", + "CFG_CENTER_BYP6_14", + "CFG_CENTER_EL1BEG1_9", + "CFG_CENTER_EE4A1_14", + "CFG_CENTER_LOGIC_OUTS_B3_7", + "CFG_CENTER_IMUX6_9", + "CFG_CENTER_EE4BEG2_13", + "CFG_CENTER_BYP1_13", + "CFG_CENTER_CTRL1_2", + "CFG_CENTER_IMUX33_2", + "CFG_CENTER_IMUX10_11", + "CFG_CENTER_BYP3_8", + "CFG_CENTER_MID_DNA_PORT_CLK", + "CFG_CENTER_LH7_0", + "CFG_CENTER_EE4A3_13", + "CFG_CENTER_ICAP0_O4", + "CFG_CENTER_FRAME_ECC_SYNDROME3", + "CFG_CENTER_ICAP0_O18", + "CFG_CENTER_LOGIC_OUTS_B13_7", + "CFG_CENTER_ICAP1_I18", + "CFG_CENTER_WW4C3_16", + "CFG_CENTER_FAN2_3", + "CFG_CENTER_DCIRESET_LOCKED", + "CFG_CENTER_SE4C1_13", + "CFG_CENTER_EE2A0_9", + "CFG_CENTER_BLOCK_OUTS_B1_8", + "CFG_CENTER_LOGIC_OUTS_B21_4", + "CFG_CENTER_IMUX3_5", + "CFG_CENTER_IMUX29_15", + "CFG_CENTER_NW4END2_18", + "CFG_CENTER_CFG_IO_ACCESS_INITBI", + "CFG_CENTER_ER1BEG3_13", + "CFG_CENTER_LOGIC_OUTS_B9_17", + "CFG_CENTER_WW4C1_2", + "CFG_CENTER_SW2A3_18", + "CFG_CENTER_WR1END0_6", + "CFG_CENTER_SW2A0_6", + "CFG_CENTER_CK_IN4", + "CFG_CENTER_IMUX45_2", + "CFG_CENTER_IMUX14_5", + "CFG_CENTER_SW4A2_12", + "CFG_CENTER_SE4BEG1_6", + "CFG_CENTER_IMUX9_18", + "CFG_CENTER_SW4END3_0", + "CFG_CENTER_BYP6_2", + "CFG_CENTER_SW2A3_6", + "CFG_CENTER_LOGIC_OUTS_B4_19", + "CFG_CENTER_WW2A2_9", + "CFG_CENTER_SE4C3_3", + "CFG_CENTER_IMUX36_1", + "CFG_CENTER_FAN2_11", + "CFG_CENTER_LOGIC_OUTS_B13_3", + "CFG_CENTER_IMUX6_19", + "CFG_CENTER_IMUX28_18", + "CFG_CENTER_IMUX37_17", + "CFG_CENTER_LOGIC_OUTS_B18_11", + "CFG_CENTER_NW4END2_14", + "CFG_CENTER_NW4END3_4", + "CFG_CENTER_LOGIC_OUTS_B17_14", + "CFG_CENTER_LOGIC_OUTS_B0_16", + "CFG_CENTER_IMUX28_12", + "CFG_CENTER_WW4END0_8", + "CFG_CENTER_EE4BEG0_3", + "CFG_CENTER_WW4A0_7", + "CFG_CENTER_NW2A1_12", + "CFG_CENTER_LOGIC_OUTS_B2_0", + "CFG_CENTER_SW2A0_8", + "CFG_CENTER_SE2A2_5", + "CFG_CENTER_FAN5_5", + "CFG_CENTER_SW4END2_11", + "CFG_CENTER_LH9_16", + "CFG_CENTER_IMUX17_9", + "CFG_CENTER_NE4C2_3", + "CFG_CENTER_IMUX24_18", + "CFG_CENTER_IMUX32_19", + "CFG_CENTER_CLK1_15", + "CFG_CENTER_WW4B3_7", + "CFG_CENTER_IMUX37_5", + "CFG_CENTER_IMUX27_2", + "CFG_CENTER_IMUX2_16", + "CFG_CENTER_IMUX13_11", + "CFG_CENTER_LOGIC_OUTS_B17_6", + "CFG_CENTER_NW4A3_0", + "CFG_CENTER_EE4C3_11", + "CFG_CENTER_IMUX45_9", + "CFG_CENTER_IMUX17_7", + "CFG_CENTER_WL1END3_17", + "CFG_CENTER_LOGIC_OUTS_B15_16", + "CFG_CENTER_EE4BEG2_17", + "CFG_CENTER_LOGIC_OUTS_B14_9", + "CFG_CENTER_IMUX45_13", + "CFG_CENTER_IMUX5_8", + "CFG_CENTER_EE2BEG3_4", + "CFG_CENTER_IMUX18_4", + "CFG_CENTER_ICAP0_I30", + "CFG_CENTER_LOGIC_OUTS_B20_9", + "CFG_CENTER_LH12_12", + "CFG_CENTER_LOGIC_OUTS_B8_5", + "CFG_CENTER_SW2A2_0", + "CFG_CENTER_CLK1_5", + "CFG_CENTER_WW4C3_18", + "CFG_CENTER_ER1BEG3_18", + "CFG_CENTER_EE4BEG2_18", + "CFG_CENTER_EE4C3_8", + "CFG_CENTER_FAN1_6", + "CFG_CENTER_EE2BEG1_5", + "CFG_CENTER_WW4END0_10", + "CFG_CENTER_SW2A0_12", + "CFG_CENTER_EE2BEG1_10", + "CFG_CENTER_EE4B0_14", + "CFG_CENTER_EE2BEG1_0", + "CFG_CENTER_LH5_1", + "CFG_CENTER_IMUX16_8", + "CFG_CENTER_SW2A2_1", + "CFG_CENTER_IMUX32_0", + "CFG_CENTER_WR1END0_1", + "CFG_CENTER_BSCAN2_CAPTURE", + "CFG_CENTER_IMUX11_3", + "CFG_CENTER_IMUX25_13", + "CFG_CENTER_USR_ACCESS_DATA28", + "CFG_CENTER_IMUX25_11", + "CFG_CENTER_LOGIC_OUTS_B12_1", + "CFG_CENTER_LOGIC_OUTS_B20_11", + "CFG_CENTER_LOGIC_OUTS_B21_1", + "CFG_CENTER_WW4B1_1", + "CFG_CENTER_WW4A1_7", + "CFG_CENTER_IMUX5_5", + "CFG_CENTER_NW2A1_3", + "CFG_CENTER_NW2A0_11", + "CFG_CENTER_IMUX32_13", + "CFG_CENTER_IMUX23_4", + "CFG_CENTER_BYP3_11", + "CFG_CENTER_BSCAN2_TMS", + "CFG_CENTER_SE4C0_8", + "CFG_CENTER_LOGIC_OUTS_B4_18", + "CFG_CENTER_EE4BEG1_14", + "CFG_CENTER_EL1BEG3_17", + "CFG_CENTER_CK_BUFHCLK6", + "CFG_CENTER_IMUX12_11", + "CFG_CENTER_IMUX23_18", + "CFG_CENTER_IMUX8_11", + "CFG_CENTER_NE4C0_0", + "CFG_CENTER_ER1BEG3_19", + "CFG_CENTER_LOGIC_OUTS_B2_13", + "CFG_CENTER_FAN7_14", + "CFG_CENTER_EE4B0_13", + "CFG_CENTER_SW4A3_2", + "CFG_CENTER_NW4END2_15", + "CFG_CENTER_WW2END1_7", + "CFG_CENTER_IMUX10_7", + "CFG_CENTER_SW2A0_10", + "CFG_CENTER_LH12_18", + "CFG_CENTER_LOGIC_OUTS_B7_18", + "CFG_CENTER_IMUX19_18", + "CFG_CENTER_WR1END3_2", + "CFG_CENTER_SE4BEG3_16", + "CFG_CENTER_SE2A1_18", + "CFG_CENTER_EE4B1_10", + "CFG_CENTER_LH9_9", + "CFG_CENTER_EE4BEG0_11", + "CFG_CENTER_IMUX1_7", + "CFG_CENTER_CAPTURE_CAP", + "CFG_CENTER_WW4END3_14", + "CFG_CENTER_IMUX38_3", + "CFG_CENTER_EE4B0_17", + "CFG_CENTER_WW4B3_5", + "CFG_CENTER_USR_ACCESS_DATA25", + "CFG_CENTER_CLK1_14", + "CFG_CENTER_FRAME_ECC_FAR9", + "CFG_CENTER_SE4BEG3_4", + "CFG_CENTER_IMUX2_5", + "CFG_CENTER_FRAME_ECC_SYNDROME2", + "CFG_CENTER_SW4END0_6", + "CFG_CENTER_SW4END2_0", + "CFG_CENTER_IMUX2_17", + "CFG_CENTER_WL1END1_14", + "CFG_CENTER_LOGIC_OUTS_B15_11", + "CFG_CENTER_ICAP1_O18", + "CFG_CENTER_EE4A3_1", + "CFG_CENTER_WL1END3_3", + "CFG_CENTER_CTRL0_12", + "CFG_CENTER_ICAP1_O27", + "CFG_CENTER_WW2A3_4", + "CFG_CENTER_BLOCK_OUTS_B0_9", + "CFG_CENTER_EL1BEG2_13", + "CFG_CENTER_NW4END0_4", + "CFG_CENTER_SE4C2_14", + "CFG_CENTER_LH2_2", + "CFG_CENTER_FAN4_3", + "CFG_CENTER_IMUX34_6", + "CFG_CENTER_LOGIC_OUTS_B0_14", + "CFG_CENTER_FAN6_11", + "CFG_CENTER_SE4BEG2_8", + "CFG_CENTER_FAN3_18", + "CFG_CENTER_SW4A2_18", + "CFG_CENTER_FAN0_19", + "CFG_CENTER_NE4C3_16", + "CFG_CENTER_WL1END0_18", + "CFG_CENTER_EE4B2_10", + "CFG_CENTER_IMUX10_5", + "CFG_CENTER_LOGIC_OUTS_B15_17", + "CFG_CENTER_EE4BEG3_8", + "CFG_CENTER_WR1END1_2", + "CFG_CENTER_FRAME_ECC_FAR13", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA26", + "CFG_CENTER_WW4B3_10", + "CFG_CENTER_BLOCK_OUTS_B0_16", + "CFG_CENTER_BSCAN1_CAPTURE", + "CFG_CENTER_LOGIC_OUTS_B16_19", + "CFG_CENTER_WW4B1_15", + "CFG_CENTER_BYP2_14", + "CFG_CENTER_LOGIC_OUTS_B12_6", + "CFG_CENTER_FAN0_1", + "CFG_CENTER_CLK1_12", + "CFG_CENTER_LH9_1", + "CFG_CENTER_IMUX46_15", + "CFG_CENTER_WW4A2_4", + "CFG_CENTER_IMUX22_15", + "CFG_CENTER_SE4BEG3_14", + "CFG_CENTER_NE2A3_15", + "CFG_CENTER_NE4BEG3_18", + "CFG_CENTER_SW2A2_18", + "CFG_CENTER_NW4A1_10", + "CFG_CENTER_WW4END3_19", + "CFG_CENTER_EE4B3_4", + "CFG_CENTER_FAN3_16", + "CFG_CENTER_IMUX45_6", + "CFG_CENTER_NW2A1_9", + "CFG_CENTER_EE2A3_4", + "CFG_CENTER_SE2A2_6", + "CFG_CENTER_LOGIC_OUTS_B17_9", + "CFG_CENTER_CFG_IO_ACCESS_INITBO", + "CFG_CENTER_IMUX46_2", + "CFG_CENTER_EE4C1_15", + "CFG_CENTER_LOGIC_OUTS_B9_13", + "CFG_CENTER_LOGIC_OUTS_B6_19", + "CFG_CENTER_LOGIC_OUTS_B2_17", + "CFG_CENTER_WW4END2_8", + "CFG_CENTER_NW4A3_3", + "CFG_CENTER_NW4END2_4", + "CFG_CENTER_IMUX20_14", + "CFG_CENTER_ICAP0_O26", + "CFG_CENTER_LH12_19", + "CFG_CENTER_SE4C2_8", + "CFG_CENTER_LOGIC_OUTS_B5_6", + "CFG_CENTER_WW2A0_12", + "CFG_CENTER_IMUX35_19", + "CFG_CENTER_BYP1_3", + "CFG_CENTER_IMUX32_14", + "CFG_CENTER_LOGIC_OUTS_B19_7", + "CFG_CENTER_BSCAN4_UPDATE", + "CFG_CENTER_WW4C2_19", + "CFG_CENTER_WW4B1_9", + "CFG_CENTER_IMUX22_3", + "CFG_CENTER_IMUX22_18", + "CFG_CENTER_LOGIC_OUTS_B9_12", + "CFG_CENTER_WW4C1_15", + "CFG_CENTER_EE4A3_14", + "CFG_CENTER_SW4A3_3", + "CFG_CENTER_EE2A3_19", + "CFG_CENTER_LOGIC_OUTS_B15_9", + "CFG_CENTER_NE4BEG2_7", + "CFG_CENTER_FAN4_17", + "CFG_CENTER_CK_IN7", + "CFG_CENTER_EE4B0_6", + "CFG_CENTER_LOGIC_OUTS_B9_15", + "CFG_CENTER_NW4A1_8", + "CFG_CENTER_WW4A1_18", + "CFG_CENTER_EE4B3_18", + "CFG_CENTER_LH4_9", + "CFG_CENTER_FRAME_ECC_SYNWORD6", + "CFG_CENTER_WW4END3_6", + "CFG_CENTER_FAN4_12", + "CFG_CENTER_WW4B0_8", + "CFG_CENTER_WL1END1_0", + "CFG_CENTER_NE4C0_4", + "CFG_CENTER_WR1END2_1", + "CFG_CENTER_NW4A1_1", + "CFG_CENTER_IMUX10_9", + "CFG_CENTER_BYP5_3", + "CFG_CENTER_EE2BEG3_6", + "CFG_CENTER_NW4END2_12", + "CFG_CENTER_EL1BEG3_7", + "CFG_CENTER_IMUX30_3", + "CFG_CENTER_FAN4_6", + "CFG_CENTER_BYP1_6", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA29", + "CFG_CENTER_EE2A3_16", + "CFG_CENTER_EE4BEG1_7", + "CFG_CENTER_LOGIC_OUTS_B11_19", + "CFG_CENTER_IMUX8_16", + "CFG_CENTER_LH10_13", + "CFG_CENTER_NW4A1_11", + "CFG_CENTER_LOGIC_OUTS_B6_16", + "CFG_CENTER_BYP0_4", + "CFG_CENTER_IMUX38_10", + "CFG_CENTER_IMUX14_6", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA11", + "CFG_CENTER_EL1BEG3_2", + "CFG_CENTER_WL1END1_8", + "CFG_CENTER_LH3_2", + "CFG_CENTER_EE4C3_13", + "CFG_CENTER_ER1BEG0_11", + "CFG_CENTER_EE4BEG3_3", + "CFG_CENTER_LOGIC_OUTS_B12_19", + "CFG_CENTER_SE4BEG3_3", + "CFG_CENTER_CTRL0_3", + "CFG_CENTER_WW2A1_17", + "CFG_CENTER_BYP7_17", + "CFG_CENTER_IMUX16_18", + "CFG_CENTER_EE4B2_7", + "CFG_CENTER_BYP0_6", + "CFG_CENTER_SE4BEG2_12", + "CFG_CENTER_FAN4_16", + "CFG_CENTER_WW2A1_0", + "CFG_CENTER_EL1BEG1_2", + "CFG_CENTER_IMUX29_12", + "CFG_CENTER_SW2A3_9", + "CFG_CENTER_WW4B0_1", + "CFG_CENTER_WW2A3_8", + "CFG_CENTER_CTRL1_14", + "CFG_CENTER_BSCAN3_TDI", + "CFG_CENTER_LH5_16", + "CFG_CENTER_IMUX25_16", + "CFG_CENTER_IMUX33_16", + "CFG_CENTER_NE2A0_13", + "CFG_CENTER_LOGIC_OUTS_B9_18", + "CFG_CENTER_WR1END1_10", + "CFG_CENTER_LOGIC_OUTS_B18_7", + "CFG_CENTER_IMUX20_7", + "CFG_CENTER_EE4BEG3_5", + "CFG_CENTER_LH7_15", + "CFG_CENTER_LOGIC_OUTS_B3_9", + "CFG_CENTER_NW2A0_15", + "CFG_CENTER_BYP3_9", + "CFG_CENTER_LH11_18", + "CFG_CENTER_IMUX10_19", + "CFG_CENTER_NE4BEG3_0", + "CFG_CENTER_IMUX38_17", + "CFG_CENTER_WW4A1_8", + "CFG_CENTER_EE4B3_12", + "CFG_CENTER_EE4A2_0", + "CFG_CENTER_FRAME_ECC_SYNDROME0", + "CFG_CENTER_WW4A1_6", + "CFG_CENTER_WR1END2_12", + "CFG_CENTER_IMUX45_7", + "CFG_CENTER_NE2A3_12", + "CFG_CENTER_WW4A0_15", + "CFG_CENTER_IMUX47_18", + "CFG_CENTER_LOGIC_OUTS_B17_18", + "CFG_CENTER_BYP6_3", + "CFG_CENTER_EL1BEG1_7", + "CFG_CENTER_IMUX44_7", + "CFG_CENTER_NW4END0_7", + "CFG_CENTER_NE4C1_9", + "CFG_CENTER_LH8_5", + "CFG_CENTER_ICAP1_O24", + "CFG_CENTER_LOGIC_OUTS_B13_19", + "CFG_CENTER_EE4C0_9", + "CFG_CENTER_LH6_5", + "CFG_CENTER_LH5_8", + "CFG_CENTER_WW4END3_12", + "CFG_CENTER_IMUX18_2", + "CFG_CENTER_SE4BEG0_9", + "CFG_CENTER_WW4B0_4", + "CFG_CENTER_NE4BEG2_9", + "CFG_CENTER_LOGIC_OUTS_B19_18", + "CFG_CENTER_USR_ACCESS_DATA14", + "CFG_CENTER_IMUX8_5", + "CFG_CENTER_LH2_18", + "CFG_CENTER_LOGIC_OUTS_B7_3", + "CFG_CENTER_FAN2_18", + "CFG_CENTER_EE2A0_2", + "CFG_CENTER_WW2END3_9", + "CFG_CENTER_IMUX9_19", + "CFG_CENTER_IMUX12_16", + "CFG_CENTER_WW4B2_8", + "CFG_CENTER_LOGIC_OUTS_B1_1", + "CFG_CENTER_CFG_IO_ACCESS_MODE2", + "CFG_CENTER_USR_ACCESS_DATA13", + "CFG_CENTER_EE4BEG3_1", + "CFG_CENTER_SW4A2_1", + "CFG_CENTER_IMUX42_0", + "CFG_CENTER_IMUX8_2", + "CFG_CENTER_IMUX21_19", + "CFG_CENTER_ICAP1_O23", + "CFG_CENTER_WL1END0_3", + "CFG_CENTER_LH10_2", + "CFG_CENTER_ICAP0_CSIB", + "CFG_CENTER_SE4C3_9", + "CFG_CENTER_WR1END2_9", + "CFG_CENTER_NW4A2_12", + "CFG_CENTER_EE4B1_3", + "CFG_CENTER_IMUX17_13", + "CFG_CENTER_CFG_IO_ACCESS_VGGCOMPOUT", + "CFG_CENTER_WR1END2_6", + "CFG_CENTER_IMUX33_10", + "CFG_CENTER_IMUX20_6", + "CFG_CENTER_FRAME_ECC_SYNDROME10", + "CFG_CENTER_LH4_18", + "CFG_CENTER_EE4A1_1", + "CFG_CENTER_NE4C2_9", + "CFG_CENTER_EL1BEG0_5", + "CFG_CENTER_IMUX9_4", + "CFG_CENTER_EE4BEG0_6", + "CFG_CENTER_LH4_14", + "CFG_CENTER_LOGIC_OUTS_B15_5", + "CFG_CENTER_EE4B0_7", + "CFG_CENTER_BYP2_7", + "CFG_CENTER_NW2A0_12", + "CFG_CENTER_EL1BEG0_15", + "CFG_CENTER_EE2BEG3_14", + "CFG_CENTER_WW4B2_15", + "CFG_CENTER_EE4A0_13", + "CFG_CENTER_FAN4_13", + "CFG_CENTER_EE4A1_2", + "CFG_CENTER_CK_BUFHCLK1", + "CFG_CENTER_SE2A3_7", + "CFG_CENTER_WW4A3_2", + "CFG_CENTER_CK_IN6", + "CFG_CENTER_LOGIC_OUTS_B18_10", + "CFG_CENTER_BLOCK_OUTS_B3_0", + "CFG_CENTER_IMUX31_1", + "CFG_CENTER_SE4BEG3_19", + "CFG_CENTER_IMUX26_5", + "CFG_CENTER_BLOCK_OUTS_B1_12", + "CFG_CENTER_IMUX38_8", + "CFG_CENTER_IMUX37_8", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA16", + "CFG_CENTER_IMUX4_0", + "CFG_CENTER_LOGIC_OUTS_B22_1", + "CFG_CENTER_EE2BEG0_15", + "CFG_CENTER_LOGIC_OUTS_B10_15", + "CFG_CENTER_WW4A0_8", + "CFG_CENTER_BYP0_0", + "CFG_CENTER_IMUX35_7", + "CFG_CENTER_IMUX45_16", + "CFG_CENTER_WW2END0_9", + "CFG_CENTER_IMUX24_12", + "CFG_CENTER_IMUX47_1", + "CFG_CENTER_SE2A3_12", + "CFG_CENTER_NW2A0_0", + "CFG_CENTER_IMUX8_7", + "CFG_CENTER_NW4A1_13", + "CFG_CENTER_LOGIC_OUTS_B0_19", + "CFG_CENTER_LH10_7", + "CFG_CENTER_IMUX24_7", + "CFG_CENTER_SW2A0_0", + "CFG_CENTER_SW4A3_10", + "CFG_CENTER_LOGIC_OUTS_B16_6", + "CFG_CENTER_IMUX8_19", + "CFG_CENTER_NE2A3_2", + "CFG_CENTER_WW4END3_4", + "CFG_CENTER_NE4C1_5", + "CFG_CENTER_BSCAN3_DRCK", + "CFG_CENTER_SE4BEG3_12", + "CFG_CENTER_LOGIC_OUTS_B11_14", + "CFG_CENTER_FRAME_ECC_SYNDROME1", + "CFG_CENTER_LOGIC_OUTS_B3_15", + "CFG_CENTER_IMUX20_18", + "CFG_CENTER_BLOCK_OUTS_B3_17", + "CFG_CENTER_NE2A2_4", + "CFG_CENTER_NE2A0_4", + "CFG_CENTER_MID_USR_ACCESS_DATA13", + "CFG_CENTER_EE4B0_4", + "CFG_CENTER_NE4C1_11", + "CFG_CENTER_BLOCK_OUTS_B1_7", + "CFG_CENTER_LH8_12", + "CFG_CENTER_NE4C0_19", + "CFG_CENTER_EE4BEG2_1", + "CFG_CENTER_IMUX32_11", + "CFG_CENTER_LOGIC_OUTS_B20_8", + "CFG_CENTER_EE4A2_13", + "CFG_CENTER_IMUX19_15", + "CFG_CENTER_EE4B3_11", + "CFG_CENTER_SE2A1_10", + "CFG_CENTER_FAN2_5", + "CFG_CENTER_LOGIC_OUTS_B1_14", + "CFG_CENTER_WW2A0_18", + "CFG_CENTER_IMUX36_2", + "CFG_CENTER_LOGIC_OUTS_B0_1", + "CFG_CENTER_IMUX33_3", + "CFG_CENTER_LOGIC_OUTS_B21_16", + "CFG_CENTER_LOGIC_OUTS_B20_5", + "CFG_CENTER_WW4C1_19", + "CFG_CENTER_SE4C2_3", + "CFG_CENTER_WW4B1_17", + "CFG_CENTER_WW4B1_16", + "CFG_CENTER_EE2BEG1_13", + "CFG_CENTER_SE4BEG1_2", + "CFG_CENTER_ICAP1_I10", + "CFG_CENTER_WW4A2_16", + "CFG_CENTER_ER1BEG2_16", + "CFG_CENTER_NW4A2_15", + "CFG_CENTER_IMUX10_4", + "CFG_CENTER_IMUX19_3", + "CFG_CENTER_IMUX7_10", + "CFG_CENTER_EE4BEG1_10", + "CFG_CENTER_WW4END0_0", + "CFG_CENTER_WW4END2_18", + "CFG_CENTER_ER1BEG1_4", + "CFG_CENTER_IMUX2_10", + "CFG_CENTER_CAPTURE_CLK", + "CFG_CENTER_IMUX0_3", + "CFG_CENTER_LH9_10", + "CFG_CENTER_BLOCK_OUTS_B3_8", + "CFG_CENTER_IMUX24_13", + "CFG_CENTER_WW4END2_11", + "CFG_CENTER_IMUX27_6", + "CFG_CENTER_NW2A0_14", + "CFG_CENTER_IMUX46_17", + "CFG_CENTER_ICAP1_I3", + "CFG_CENTER_WW2END3_6", + "CFG_CENTER_WW4B1_11", + "CFG_CENTER_EE2A0_6", + "CFG_CENTER_IMUX9_13", + "CFG_CENTER_LH1_10", + "CFG_CENTER_NW4A2_19", + "CFG_CENTER_SW4END1_19", + "CFG_CENTER_NW2A2_9", + "CFG_CENTER_LOGIC_OUTS_B14_11", + "CFG_CENTER_IMUX12_12", + "CFG_CENTER_WW2A1_4", + "CFG_CENTER_WL1END0_12", + "CFG_CENTER_WW4END1_3", + "CFG_CENTER_LOGIC_OUTS_B19_8", + "CFG_CENTER_IMUX25_2", + "CFG_CENTER_IMUX39_13", + "CFG_CENTER_IMUX35_12", + "CFG_CENTER_BYP4_18", + "CFG_CENTER_CFG_IO_ACCESS_CCLK", + "CFG_CENTER_IMUX18_8", + "CFG_CENTER_LH11_11", + "CFG_CENTER_WW2END3_5", + "CFG_CENTER_IMUX36_5", + "CFG_CENTER_WW2A0_16", + "CFG_CENTER_EL1BEG1_8", + "CFG_CENTER_IMUX41_1", + "CFG_CENTER_USR_ACCESS_DATA5", + "CFG_CENTER_EE4B3_8", + "CFG_CENTER_NW4END3_15", + "CFG_CENTER_NE2A3_10", + "CFG_CENTER_LOGIC_OUTS_B6_4", + "CFG_CENTER_WW4C1_5", + "CFG_CENTER_IMUX30_8", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA16", + "CFG_CENTER_NW4A1_15", + "CFG_CENTER_SE4C0_0", + "CFG_CENTER_EE4C3_18", + "CFG_CENTER_ER1BEG0_9", + "CFG_CENTER_NW2A1_7", + "CFG_CENTER_EE4B2_9", + "CFG_CENTER_IMUX40_13", + "CFG_CENTER_IMUX43_7", + "CFG_CENTER_IMUX41_9", + "CFG_CENTER_CLK1_0", + "CFG_CENTER_BLOCK_OUTS_B2_7", + "CFG_CENTER_NW4END3_19", + "CFG_CENTER_EE2A0_3", + "CFG_CENTER_NW4END3_3", + "CFG_CENTER_SW2A0_14", + "CFG_CENTER_IMUX11_9", + "CFG_CENTER_SW2A3_15", + "CFG_CENTER_ER1BEG2_13", + "CFG_CENTER_LOGIC_OUTS_B11_10", + "CFG_CENTER_WW4A2_2", + "CFG_CENTER_NW2A0_18", + "CFG_CENTER_IMUX17_10", + "CFG_CENTER_SE2A0_17", + "CFG_CENTER_FRAME_ECC_SYNDROME12", + "CFG_CENTER_SE4C3_5", + "CFG_CENTER_EE4C2_18", + "CFG_CENTER_IMUX6_8", + "CFG_CENTER_SW2A3_3", + "CFG_CENTER_IMUX46_3", + "CFG_CENTER_SW4END1_4", + "CFG_CENTER_LH9_19", + "CFG_CENTER_WW2A0_3", + "CFG_CENTER_SW4END3_2", + "CFG_CENTER_EE4B2_4", + "CFG_CENTER_IMUX18_19", + "CFG_CENTER_LH8_2", + "CFG_CENTER_IMUX30_14", + "CFG_CENTER_LOGIC_OUTS_B7_15", + "CFG_CENTER_LOGIC_OUTS_B20_2", + "CFG_CENTER_ICAP0_O30", + "CFG_CENTER_WW4A3_13", + "CFG_CENTER_WL1END1_1", + "CFG_CENTER_IMUX28_6", + "CFG_CENTER_SW2A0_5", + "CFG_CENTER_BYP3_6", + "CFG_CENTER_LOGIC_OUTS_B16_10", + "CFG_CENTER_SE2A0_7", + "CFG_CENTER_BYP0_10", + "CFG_CENTER_FAN0_12", + "CFG_CENTER_ICAP1_O11", + "CFG_CENTER_EE2BEG1_15", + "CFG_CENTER_SE4C1_2", + "CFG_CENTER_IMUX40_18", + "CFG_CENTER_WW2A2_4", + "CFG_CENTER_EE2A1_9", + "CFG_CENTER_CFG_IO_ACCESS_MASTER", + "CFG_CENTER_EE4C3_17", + "CFG_CENTER_ICAP1_O31", + "CFG_CENTER_WR1END1_12", + "CFG_CENTER_FAN4_9", + "CFG_CENTER_WW2A2_12", + "CFG_CENTER_BSCAN3_RUNTEST", + "CFG_CENTER_LOGIC_OUTS_B5_15", + "CFG_CENTER_LH11_0", + "CFG_CENTER_WW4A3_8", + "CFG_CENTER_LOGIC_OUTS_B16_15", + "CFG_CENTER_NE2A2_16", + "CFG_CENTER_LOGIC_OUTS_B21_3", + "CFG_CENTER_LOGIC_OUTS_B10_5", + "CFG_CENTER_BSCAN3_RESET", + "CFG_CENTER_BYP5_2", + "CFG_CENTER_LOGIC_OUTS_B9_2", + "CFG_CENTER_LOGIC_OUTS_B5_1", + "CFG_CENTER_WW4B0_12", + "CFG_CENTER_CLK1_16", + "CFG_CENTER_NW2A2_3", + "CFG_CENTER_IMUX12_7", + "CFG_CENTER_LOGIC_OUTS_B2_8", + "CFG_CENTER_LOGIC_OUTS_B4_10", + "CFG_CENTER_WW2A1_11", + "CFG_CENTER_FAN2_13", + "CFG_CENTER_EE4B0_5", + "CFG_CENTER_ICAP0_O0", + "CFG_CENTER_WW4END1_14", + "CFG_CENTER_USR_ACCESS_DATA0", + "CFG_CENTER_EE4B0_19", + "CFG_CENTER_IMUX21_13", + "CFG_CENTER_NW4A3_19", + "CFG_CENTER_IMUX45_15", + "CFG_CENTER_LOGIC_OUTS_B5_7", + "CFG_CENTER_ER1BEG0_1", + "CFG_CENTER_WR1END3_4", + "CFG_CENTER_BLOCK_OUTS_B2_8", + "CFG_CENTER_ICAP0_O15", + "CFG_CENTER_IMUX47_5", + "CFG_CENTER_ICAP0_I9", + "CFG_CENTER_EE4B3_6", + "CFG_CENTER_IMUX7_2", + "CFG_CENTER_LOGIC_OUTS_B0_4", + "CFG_CENTER_EE4C2_13", + "CFG_CENTER_IMUX39_7", + "CFG_CENTER_WW2A1_1", + "CFG_CENTER_FRAME_ECC_FAR7", + "CFG_CENTER_WW4END3_7", + "CFG_CENTER_NW2A3_6", + "CFG_CENTER_SW2A1_2", + "CFG_CENTER_EE2BEG2_19", + "CFG_CENTER_LOGIC_OUTS_B8_8", + "CFG_CENTER_NW4END2_10", + "CFG_CENTER_WR1END3_11", + "CFG_CENTER_LOGIC_OUTS_B21_0", + "CFG_CENTER_NW4A3_8", + "CFG_CENTER_WW4C2_15", + "CFG_CENTER_NW4A1_2", + "CFG_CENTER_BLOCK_OUTS_B0_12", + "CFG_CENTER_SE2A2_11", + "CFG_CENTER_WR1END0_14", + "CFG_CENTER_BYP7_19", + "CFG_CENTER_SE2A3_9", + "CFG_CENTER_EE2A1_19", + "CFG_CENTER_LH6_18", + "CFG_CENTER_FAN3_19", + "CFG_CENTER_BSCAN1_DRCK", + "CFG_CENTER_BYP7_11", + "CFG_CENTER_WW4END1_12", + "CFG_CENTER_SW4A1_17", + "CFG_CENTER_IMUX14_19", + "CFG_CENTER_ICAP0_O7", + "CFG_CENTER_EE4C2_5", + "CFG_CENTER_NW4END1_15", + "CFG_CENTER_LH1_19", + "CFG_CENTER_LOGIC_OUTS_B2_4", + "CFG_CENTER_NE2A2_17", + "CFG_CENTER_IMUX6_0", + "CFG_CENTER_SW4A0_1", + "CFG_CENTER_ICAP0_I23", + "CFG_CENTER_NW4A3_18", + "CFG_CENTER_SW4A2_5", + "CFG_CENTER_LH10_4", + "CFG_CENTER_LOGIC_OUTS_B13_1", + "CFG_CENTER_NE2A1_1", + "CFG_CENTER_EE4C1_12", + "CFG_CENTER_EE4C2_15", + "CFG_CENTER_LH9_12", + "CFG_CENTER_WW4END0_11", + "CFG_CENTER_LOGIC_OUTS_B14_8", + "CFG_CENTER_IMUX23_19", + "CFG_CENTER_IMUX24_8", + "CFG_CENTER_NE2A2_6", + "CFG_CENTER_LOGIC_OUTS_B1_16", + "CFG_CENTER_LH8_1", + "CFG_CENTER_LH7_19", + "CFG_CENTER_WW4END2_10", + "CFG_CENTER_IMUX46_16", + "CFG_CENTER_LH4_4", + "CFG_CENTER_NW2A0_6", + "CFG_CENTER_LH5_19", + "CFG_CENTER_NW2A3_16", + "CFG_CENTER_CLK0_2", + "CFG_CENTER_IMUX1_2", + "CFG_CENTER_LH9_18", + "CFG_CENTER_SE2A3_15", + "CFG_CENTER_IMUX13_13", + "CFG_CENTER_EE4A1_8", + "CFG_CENTER_WW4END0_1", + "CFG_CENTER_IMUX26_11", + "CFG_CENTER_LOGIC_OUTS_B1_9", + "CFG_CENTER_SW4END0_7", + "CFG_CENTER_NW2A2_16", + "CFG_CENTER_NE2A0_15", + "CFG_CENTER_EE4A1_7", + "CFG_CENTER_EE2A3_12", + "CFG_CENTER_IMUX39_9", + "CFG_CENTER_IMUX8_10", + "CFG_CENTER_FAN5_9", + "CFG_CENTER_EE4B0_3", + "CFG_CENTER_IMUX20_3", + "CFG_CENTER_SW4A1_1", + "CFG_CENTER_LOGIC_OUTS_B19_1", + "CFG_CENTER_LOGIC_OUTS_B4_7", + "CFG_CENTER_NE4BEG1_17", + "CFG_CENTER_IMUX44_9", + "CFG_CENTER_EE2A2_10", + "CFG_CENTER_SW4A3_6", + "CFG_CENTER_BYP6_5", + "CFG_CENTER_IMUX7_17", + "CFG_CENTER_LH11_3", + "CFG_CENTER_FRAME_ECC_SYNBIT4", + "CFG_CENTER_IMUX29_10", + "CFG_CENTER_LH2_9", + "CFG_CENTER_LOGIC_OUTS_B13_10", + "CFG_CENTER_ER1BEG0_13", + "CFG_CENTER_WR1END0_16", + "CFG_CENTER_IMUX5_18", + "CFG_CENTER_WR1END3_12", + "CFG_CENTER_WW4C3_10", + "CFG_CENTER_WW4B2_14", + "CFG_CENTER_IMUX35_8", + "CFG_CENTER_WW4END3_16", + "CFG_CENTER_CTRL0_18", + "CFG_CENTER_SW4A2_9", + "CFG_CENTER_NE4BEG0_1", + "CFG_CENTER_CTRL0_1", + "CFG_CENTER_BYP7_18", + "CFG_CENTER_IMUX38_13", + "CFG_CENTER_LH2_10", + "CFG_CENTER_LH8_6", + "CFG_CENTER_SW4END2_13", + "CFG_CENTER_LOGIC_OUTS_B7_12", + "CFG_CENTER_IMUX9_12", + "CFG_CENTER_WR1END1_7", + "CFG_CENTER_WW4END0_9", + "CFG_CENTER_WW4C2_2", + "CFG_CENTER_EL1BEG0_14", + "CFG_CENTER_EL1BEG1_16", + "CFG_CENTER_NW4A1_5", + "CFG_CENTER_IMUX34_19", + "CFG_CENTER_EL1BEG3_5", + "CFG_CENTER_BYP6_11", + "CFG_CENTER_WW4END2_19", + "CFG_CENTER_FAN5_18", + "CFG_CENTER_NE4C3_0", + "CFG_CENTER_BLOCK_OUTS_B0_15", + "CFG_CENTER_NE4C2_18", + "CFG_CENTER_BLOCK_OUTS_B2_11", + "CFG_CENTER_LOGIC_OUTS_B21_2", + "CFG_CENTER_FAN1_2", + "CFG_CENTER_NE4C0_2", + "CFG_CENTER_WW4END1_8", + "CFG_CENTER_LH10_1", + "CFG_CENTER_IMUX40_0", + "CFG_CENTER_CK_BUFHCLK2", + "CFG_CENTER_NW2A0_7", + "CFG_CENTER_IMUX8_8", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA22", + "CFG_CENTER_LOGIC_OUTS_B0_10", + "CFG_CENTER_WW2END2_1", + "CFG_CENTER_IMUX40_15", + "CFG_CENTER_LH6_2", + "CFG_CENTER_LOGIC_OUTS_B2_18", + "CFG_CENTER_LH8_16", + "CFG_CENTER_BYP3_14", + "CFG_CENTER_CTRL1_4", + "CFG_CENTER_EE2BEG2_0", + "CFG_CENTER_BYP6_15", + "CFG_CENTER_NE4BEG0_4", + "CFG_CENTER_IMUX29_7", + "CFG_CENTER_FRAME_ECC_SYNWORD5", + "CFG_CENTER_LH11_8", + "CFG_CENTER_IMUX47_13", + "CFG_CENTER_LOGIC_OUTS_B22_13", + "CFG_CENTER_SW4END0_13", + "CFG_CENTER_LOGIC_OUTS_B18_6", + "CFG_CENTER_IMUX42_11", + "CFG_CENTER_SW2A0_11", + "CFG_CENTER_LOGIC_OUTS_B23_12", + "CFG_CENTER_LOGIC_OUTS_B1_11", + "CFG_CENTER_SW2A1_16", + "CFG_CENTER_NE2A3_9", + "CFG_CENTER_SE4C2_13", + "CFG_CENTER_EE4BEG3_17", + "CFG_CENTER_EE4B2_14", + "CFG_CENTER_IMUX45_3", + "CFG_CENTER_LH4_19", + "CFG_CENTER_IMUX14_9", + "CFG_CENTER_WW4C2_12", + "CFG_CENTER_LH5_18", + "CFG_CENTER_EE4C0_10", + "CFG_CENTER_IMUX43_19", + "CFG_CENTER_IMUX6_7", + "CFG_CENTER_LOGIC_OUTS_B18_1", + "CFG_CENTER_SW4A2_19", + "CFG_CENTER_IMUX17_0", + "CFG_CENTER_IMUX18_12", + "CFG_CENTER_ICAP0_O25", + "CFG_CENTER_LOGIC_OUTS_B8_17", + "CFG_CENTER_IMUX36_9", + "CFG_CENTER_IMUX31_3", + "CFG_CENTER_BYP0_2", + "CFG_CENTER_LH7_10", + "CFG_CENTER_WL1END3_9", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA27", + "CFG_CENTER_IMUX27_11", + "CFG_CENTER_LOGIC_OUTS_B4_14", + "CFG_CENTER_NW4END2_1", + "CFG_CENTER_EL1BEG0_1", + "CFG_CENTER_EE4BEG1_11", + "CFG_CENTER_CK_BUFHCLK3", + "CFG_CENTER_BYP2_10", + "CFG_CENTER_LOGIC_OUTS_B15_14", + "CFG_CENTER_LH8_8", + "CFG_CENTER_SW2A1_13", + "CFG_CENTER_IMUX30_10", + "CFG_CENTER_IMUX9_6", + "CFG_CENTER_IMUX26_1", + "CFG_CENTER_LOGIC_OUTS_B23_9", + "CFG_CENTER_IMUX19_8", + "CFG_CENTER_STARTUP_GTS", + "CFG_CENTER_SW4A0_14", + "CFG_CENTER_LOGIC_OUTS_B22_8", + "CFG_CENTER_LOGIC_OUTS_B12_12", + "CFG_CENTER_EE4B1_19", + "CFG_CENTER_EE2A1_17", + "CFG_CENTER_WW4A2_3", + "CFG_CENTER_IMUX42_6", + "CFG_CENTER_SW4END1_3", + "CFG_CENTER_USR_ACCESS_DATA1", + "CFG_CENTER_NW2A2_19", + "CFG_CENTER_IMUX37_11", + "CFG_CENTER_NE4C2_11", + "CFG_CENTER_STARTUP_PACK", + "CFG_CENTER_IMUX25_5", + "CFG_CENTER_EL1BEG0_11", + "CFG_CENTER_IMUX40_12", + "CFG_CENTER_WR1END0_0", + "CFG_CENTER_WW4C3_19", + "CFG_CENTER_EE2A2_18", + "CFG_CENTER_EE2BEG3_16", + "CFG_CENTER_NE4C0_18", + "CFG_CENTER_ER1BEG1_0", + "CFG_CENTER_SE4BEG2_17", + "CFG_CENTER_SE4C2_4", + "CFG_CENTER_IMUX0_12", + "CFG_CENTER_IMUX31_10", + "CFG_CENTER_ER1BEG1_8", + "CFG_CENTER_IMUX43_18", + "CFG_CENTER_LOGIC_OUTS_B8_16", + "CFG_CENTER_NW4END2_5", + "CFG_CENTER_WL1END0_16", + "CFG_CENTER_BYP1_5", + "CFG_CENTER_EE4A2_1", + "CFG_CENTER_FRAME_ECC_FAR20", + "CFG_CENTER_IMUX25_19", + "CFG_CENTER_NE2A3_16", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA13", + "CFG_CENTER_IMUX22_5", + "CFG_CENTER_ICAP1_I11", + "CFG_CENTER_NE4C3_1", + "CFG_CENTER_IMUX41_13", + "CFG_CENTER_IMUX31_13", + "CFG_CENTER_EE4BEG1_17", + "CFG_CENTER_LOGIC_OUTS_B13_13", + "CFG_CENTER_FAN3_6", + "CFG_CENTER_IMUX31_8", + "CFG_CENTER_ICAP1_O1", + "CFG_CENTER_IMUX3_10", + "CFG_CENTER_NE4BEG3_10", + "CFG_CENTER_LOGIC_OUTS_B6_13", + "CFG_CENTER_CLK0_11", + "CFG_CENTER_LH12_17", + "CFG_CENTER_BLOCK_OUTS_B1_16", + "CFG_CENTER_NE4BEG3_7", + "CFG_CENTER_NE4BEG2_10", + "CFG_CENTER_IMUX11_1", + "CFG_CENTER_NE2A3_4", + "CFG_CENTER_NW2A2_1", + "CFG_CENTER_WW2END2_7", + "CFG_CENTER_EE4C1_7", + "CFG_CENTER_BYP7_4", + "CFG_CENTER_EE2BEG2_16", + "CFG_CENTER_FRAME_ECC_FAR5", + "CFG_CENTER_WW4END0_19", + "CFG_CENTER_IMUX12_15", + "CFG_CENTER_ICAP1_I12", + "CFG_CENTER_LOGIC_OUTS_B1_2", + "CFG_CENTER_EE4C0_17", + "CFG_CENTER_WW4C0_6", + "CFG_CENTER_SW4A3_17", + "CFG_CENTER_IMUX35_10", + "CFG_CENTER_LH11_4", + "CFG_CENTER_FAN3_10", + "CFG_CENTER_EE4C0_12", + "CFG_CENTER_NE4C3_13", + "CFG_CENTER_LOGIC_OUTS_B8_14", + "CFG_CENTER_IMUX37_15", + "CFG_CENTER_EE2A3_9", + "CFG_CENTER_LOGIC_OUTS_B4_1", + "CFG_CENTER_IMUX33_1", + "CFG_CENTER_EE4A2_17", + "CFG_CENTER_WW4B2_3", + "CFG_CENTER_ICAP1_I2", + "CFG_CENTER_LOGIC_OUTS_B10_19", + "CFG_CENTER_LOGIC_OUTS_B7_10", + "CFG_CENTER_EL1BEG3_4", + "CFG_CENTER_IMUX26_7", + "CFG_CENTER_IMUX36_16", + "CFG_CENTER_LOGIC_OUTS_B22_16", + "CFG_CENTER_WW2END1_5", + "CFG_CENTER_WW4C1_12", + "CFG_CENTER_EE4C0_2", + "CFG_CENTER_FAN0_9", + "CFG_CENTER_MID_ICAP1_CLK", + "CFG_CENTER_WW2END2_15", + "CFG_CENTER_LH1_1", + "CFG_CENTER_WW2A3_16", + "CFG_CENTER_BSCAN1_TCK", + "CFG_CENTER_NE4BEG1_9", + "CFG_CENTER_ER1BEG2_9", + "CFG_CENTER_LH2_4", + "CFG_CENTER_FAN3_14", + "CFG_CENTER_SW4END1_17", + "CFG_CENTER_FAN2_16", + "CFG_CENTER_LOGIC_OUTS_B16_5", + "CFG_CENTER_IMUX21_8", + "CFG_CENTER_LOGIC_OUTS_B13_8", + "CFG_CENTER_CTRL0_15", + "CFG_CENTER_WL1END2_0", + "CFG_CENTER_IMUX23_1", + "CFG_CENTER_WW2A2_3", + "CFG_CENTER_SW4A0_19", + "CFG_CENTER_LH12_0", + "CFG_CENTER_SE4BEG1_1", + "CFG_CENTER_WL1END0_0", + "CFG_CENTER_LOGIC_OUTS_B14_13", + "CFG_CENTER_ER1BEG3_10", + "CFG_CENTER_LH4_5", + "CFG_CENTER_EE4B3_16", + "CFG_CENTER_SW4A3_1", + "CFG_CENTER_LOGIC_OUTS_B9_1", + "CFG_CENTER_IMUX19_16", + "CFG_CENTER_WW2END1_6", + "CFG_CENTER_IMUX9_17", + "CFG_CENTER_BSCAN3_SEL", + "CFG_CENTER_USR_ACCESS_DATA17", + "CFG_CENTER_LOGIC_OUTS_B22_19", + "CFG_CENTER_NE4BEG2_0", + "CFG_CENTER_LOGIC_OUTS_B13_12", + "CFG_CENTER_ER1BEG3_1", + "CFG_CENTER_LH3_18", + "CFG_CENTER_LH5_13", + "CFG_CENTER_BYP0_18", + "CFG_CENTER_LH8_18", + "CFG_CENTER_NW2A3_12", + "CFG_CENTER_EE4BEG1_15", + "CFG_CENTER_BYP2_15", + "CFG_CENTER_NE2A3_0", + "CFG_CENTER_IMUX25_15", + "CFG_CENTER_SE4BEG0_13", + "CFG_CENTER_LOGIC_OUTS_B17_12", + "CFG_CENTER_ER1BEG2_11", + "CFG_CENTER_NE4C1_10", + "CFG_CENTER_SW4END2_2", + "CFG_CENTER_BSCAN4_SHIFT", + "CFG_CENTER_EE2A2_13", + "CFG_CENTER_WW4C3_13", + "CFG_CENTER_ER1BEG1_17", + "CFG_CENTER_IMUX30_1", + "CFG_CENTER_NW4END2_19", + "CFG_CENTER_IMUX15_13", + "CFG_CENTER_EL1BEG0_18", + "CFG_CENTER_BLOCK_OUTS_B0_5", + "CFG_CENTER_LH8_19", + "CFG_CENTER_EE2A1_3", + "CFG_CENTER_EE4C3_9", + "CFG_CENTER_IMUX0_4", + "CFG_CENTER_BYP0_19", + "CFG_CENTER_IMUX16_9", + "CFG_CENTER_USR_ACCESS_DATA12", + "CFG_CENTER_FAN4_10", + "CFG_CENTER_LOGIC_OUTS_B23_5", + "CFG_CENTER_SW2A3_8", + "CFG_CENTER_IMUX23_6", + "CFG_CENTER_NW4END3_1", + "CFG_CENTER_WR1END3_13", + "CFG_CENTER_EE4A3_18", + "CFG_CENTER_NE4C0_13", + "CFG_CENTER_CK_BUFHCLK11", + "CFG_CENTER_IMUX46_9", + "CFG_CENTER_WW2END2_3", + "CFG_CENTER_FAN1_14", + "CFG_CENTER_IMUX46_13", + "CFG_CENTER_LOGIC_OUTS_B4_0", + "CFG_CENTER_WR1END0_7", + "CFG_CENTER_FRAME_ECC_FAR22", + "CFG_CENTER_SE4BEG3_8", + "CFG_CENTER_NE4C2_12", + "CFG_CENTER_BYP2_18", + "CFG_CENTER_WL1END2_12", + "CFG_CENTER_IMUX14_7", + "CFG_CENTER_ICAP0_I18", + "CFG_CENTER_SE4C3_8", + "CFG_CENTER_IMUX0_16", + "CFG_CENTER_WL1END3_12", + "CFG_CENTER_BYP3_18", + "CFG_CENTER_NW2A0_3", + "CFG_CENTER_LOGIC_OUTS_B2_12", + "CFG_CENTER_WW4A3_5", + "CFG_CENTER_EL1BEG3_19", + "CFG_CENTER_BLOCK_OUTS_B1_1", + "CFG_CENTER_NE2A3_18", + "CFG_CENTER_BYP5_14", + "CFG_CENTER_EL1BEG2_10", + "CFG_CENTER_FRAME_ECC_SYNDROME5", + "CFG_CENTER_WW2END1_2", + "CFG_CENTER_LH8_9", + "CFG_CENTER_WW2END2_4", + "CFG_CENTER_IMUX29_6", + "CFG_CENTER_ICAP0_O23", + "CFG_CENTER_WW4B1_8", + "CFG_CENTER_ER1BEG3_5", + "CFG_CENTER_NW4END0_8", + "CFG_CENTER_NW4A0_14", + "CFG_CENTER_NW4END1_14", + "CFG_CENTER_IMUX17_3", + "CFG_CENTER_BLOCK_OUTS_B0_3", + "CFG_CENTER_IMUX32_12", + "CFG_CENTER_NW4A0_18", + "CFG_CENTER_EE4A3_0", + "CFG_CENTER_IMUX19_11", + "CFG_CENTER_EE4C0_19", + "CFG_CENTER_SW2A1_7", + "CFG_CENTER_LH3_13", + "CFG_CENTER_IMUX37_18", + "CFG_CENTER_EE4B2_0", + "CFG_CENTER_EE4A1_9", + "CFG_CENTER_LH12_7", + "CFG_CENTER_IMUX36_8", + "CFG_CENTER_WW4A3_10", + "CFG_CENTER_LOGIC_OUTS_B17_1", + "CFG_CENTER_LH4_15", + "CFG_CENTER_IMUX21_6", + "CFG_CENTER_LOGIC_OUTS_B18_17", + "CFG_CENTER_LOGIC_OUTS_B4_9", + "CFG_CENTER_NW4A3_6", + "CFG_CENTER_NW4END3_7", + "CFG_CENTER_IMUX35_13", + "CFG_CENTER_LOGIC_OUTS_B2_6", + "CFG_CENTER_WR1END1_4", + "CFG_CENTER_IMUX44_3", + "CFG_CENTER_NE4C0_16", + "CFG_CENTER_IMUX6_17", + "CFG_CENTER_SW2A2_4", + "CFG_CENTER_SW2A3_10", + "CFG_CENTER_NW4A1_3", + "CFG_CENTER_LOGIC_OUTS_B1_10", + "CFG_CENTER_NW2A2_0", + "CFG_CENTER_NW2A2_2", + "CFG_CENTER_IMUX12_19", + "CFG_CENTER_NW4END0_9", + "CFG_CENTER_NE4BEG0_2", + "CFG_CENTER_CLK1_19", + "CFG_CENTER_NW2A2_14", + "CFG_CENTER_SE2A3_6", + "CFG_CENTER_FAN6_6", + "CFG_CENTER_LH2_12", + "CFG_CENTER_CTRL0_9", + "CFG_CENTER_FAN6_8", + "CFG_CENTER_LOGIC_OUTS_B3_5", + "CFG_CENTER_IMUX0_0", + "CFG_CENTER_FAN5_1", + "CFG_CENTER_EE4BEG0_15", + "CFG_CENTER_SE4BEG2_10", + "CFG_CENTER_IMUX24_11", + "CFG_CENTER_ICAP0_O8", + "CFG_CENTER_WR1END1_1", + "CFG_CENTER_WR1END3_14", + "CFG_CENTER_SW4END3_15", + "CFG_CENTER_IMUX16_10", + "CFG_CENTER_NE4BEG3_14", + "CFG_CENTER_SW4A2_15", + "CFG_CENTER_SE4BEG3_5", + "CFG_CENTER_SE4BEG1_8", + "CFG_CENTER_IMUX24_9", + "CFG_CENTER_CK_BUFHCLK10", + "CFG_CENTER_NW4END0_17", + "CFG_CENTER_WW2END2_10", + "CFG_CENTER_LOGIC_OUTS_B19_17", + "CFG_CENTER_EL1BEG1_14", + "CFG_CENTER_FRAME_ECC_FAR6", + "CFG_CENTER_LH8_4", + "CFG_CENTER_LOGIC_OUTS_B18_8", + "CFG_CENTER_SW2A0_19", + "CFG_CENTER_EE2A1_2", + "CFG_CENTER_SE2A1_6", + "CFG_CENTER_WW4A2_7", + "CFG_CENTER_EE2A1_8", + "CFG_CENTER_ER1BEG1_18", + "CFG_CENTER_SE4C3_13", + "CFG_CENTER_LOGIC_OUTS_B6_2", + "CFG_CENTER_IMUX30_0", + "CFG_CENTER_WW4B0_13", + "CFG_CENTER_EE4A2_16", + "CFG_CENTER_IMUX3_4", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA21", + "CFG_CENTER_WW4END1_0", + "CFG_CENTER_LOGIC_OUTS_B0_7", + "CFG_CENTER_SW4END1_11", + "CFG_CENTER_SW4A0_5", + "CFG_CENTER_WW4C2_10", + "CFG_CENTER_BYP2_1", + "CFG_CENTER_IMUX20_8", + "CFG_CENTER_ICAP1_I8", + "CFG_CENTER_EE4BEG0_7", + "CFG_CENTER_ICAP1_I14", + "CFG_CENTER_NE4C0_3", + "CFG_CENTER_SE4C0_6", + "CFG_CENTER_NE2A0_12", + "CFG_CENTER_WR1END1_8", + "CFG_CENTER_IMUX46_11", + "CFG_CENTER_IMUX37_16", + "CFG_CENTER_EE4A3_7", + "CFG_CENTER_LH3_5", + "CFG_CENTER_IMUX38_14", + "CFG_CENTER_STARTUP_USRDONETS", + "CFG_CENTER_IMUX28_7", + "CFG_CENTER_CLK0_5", + "CFG_CENTER_LOGIC_OUTS_B3_8", + "CFG_CENTER_IMUX32_16", + "CFG_CENTER_IMUX39_14", + "CFG_CENTER_WW2END0_13", + "CFG_CENTER_SE4BEG0_2", + "CFG_CENTER_EE4BEG3_10", + "CFG_CENTER_IMUX33_9", + "CFG_CENTER_NE2A2_18", + "CFG_CENTER_LH12_2", + "CFG_CENTER_ICAP0_O31", + "CFG_CENTER_IMUX18_3", + "CFG_CENTER_EE2A2_6", + "CFG_CENTER_IMUX43_11", + "CFG_CENTER_NW2A0_10", + "CFG_CENTER_NE4C1_15", + "CFG_CENTER_EE4C0_3", + "CFG_CENTER_IMUX24_17", + "CFG_CENTER_LOGIC_OUTS_B12_18", + "CFG_CENTER_SW4END3_17", + "CFG_CENTER_IMUX6_5", + "CFG_CENTER_EE2BEG3_3", + "CFG_CENTER_SE2A2_16", + "CFG_CENTER_LH9_8", + "CFG_CENTER_EE4C2_12", + "CFG_CENTER_EE2BEG0_16", + "CFG_CENTER_SW2A3_12", + "CFG_CENTER_BYP6_13", + "CFG_CENTER_ICAP0_O19", + "CFG_CENTER_FAN3_0", + "CFG_CENTER_IMUX19_10", + "CFG_CENTER_IMUX41_14", + "CFG_CENTER_NE2A1_7", + "CFG_CENTER_ICAP0_I20", + "CFG_CENTER_EE4BEG3_18", + "CFG_CENTER_IMUX5_2", + "CFG_CENTER_IMUX32_8", + "CFG_CENTER_IMUX46_0", + "CFG_CENTER_EE4A2_18", + "CFG_CENTER_IMUX5_17", + "CFG_CENTER_WR1END2_7", + "CFG_CENTER_IMUX10_3", + "CFG_CENTER_IMUX29_18", + "CFG_CENTER_NE4BEG3_15", + "CFG_CENTER_IMUX34_7", + "CFG_CENTER_WW4B0_9", + "CFG_CENTER_SE4C0_17", + "CFG_CENTER_NW4END2_9", + "CFG_CENTER_NE4BEG3_17", + "CFG_CENTER_SE4BEG2_13", + "CFG_CENTER_ER1BEG0_6", + "CFG_CENTER_LOGIC_OUTS_B10_11", + "CFG_CENTER_IMUX12_2", + "CFG_CENTER_LH10_5", + "CFG_CENTER_EE2A3_18", + "CFG_CENTER_LOGIC_OUTS_B7_9", + "CFG_CENTER_WW4END3_17", + "CFG_CENTER_IMUX4_14", + "CFG_CENTER_EE4C2_14", + "CFG_CENTER_LH3_10", + "CFG_CENTER_ICAP0_CLK", + "CFG_CENTER_IMUX5_7", + "CFG_CENTER_WW2A2_0", + "CFG_CENTER_IMUX21_14", + "CFG_CENTER_IMUX15_3", + "CFG_CENTER_WW2A2_8", + "CFG_CENTER_LOGIC_OUTS_B9_9", + "CFG_CENTER_SE4BEG3_17", + "CFG_CENTER_WW2A1_14", + "CFG_CENTER_IMUX34_4", + "CFG_CENTER_IMUX7_12", + "CFG_CENTER_EL1BEG2_16", + "CFG_CENTER_EE4BEG3_13", + "CFG_CENTER_LH12_14", + "CFG_CENTER_ICAP0_I16", + "CFG_CENTER_WW4A0_1", + "CFG_CENTER_IMUX13_19", + "CFG_CENTER_WW2END2_9", + "CFG_CENTER_IMUX35_16", + "CFG_CENTER_LOGIC_OUTS_B20_4", + "CFG_CENTER_EE2A2_2", + "CFG_CENTER_LH10_19", + "CFG_CENTER_EE2BEG1_12", + "CFG_CENTER_CTRL1_9", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA5", + "CFG_CENTER_EE2A0_15", + "CFG_CENTER_EL1BEG3_1", + "CFG_CENTER_LH4_10", + "CFG_CENTER_WW4C2_16", + "CFG_CENTER_IMUX0_8", + "CFG_CENTER_USR_ACCESS_DATA26", + "CFG_CENTER_MID_USR_ACCESS_DATA4", + "CFG_CENTER_NW2A0_2", + "CFG_CENTER_WW4END1_4", + "CFG_CENTER_EE4C0_15", + "CFG_CENTER_EE2BEG2_2", + "CFG_CENTER_IMUX19_14", + "CFG_CENTER_SW2A3_13", + "CFG_CENTER_IMUX20_17", + "CFG_CENTER_IMUX30_13", + "CFG_CENTER_CFG_IO_ACCESS_MODE1", + "CFG_CENTER_WW4A2_9", + "CFG_CENTER_IMUX10_10", + "CFG_CENTER_EE4C1_14", + "CFG_CENTER_LH7_9", + "CFG_CENTER_EE2BEG0_8", + "CFG_CENTER_FAN1_17", + "CFG_CENTER_ICAP1_O9", + "CFG_CENTER_WW4A1_15", + "CFG_CENTER_IMUX5_3", + "CFG_CENTER_LOGIC_OUTS_B18_15", + "CFG_CENTER_WR1END1_3", + "CFG_CENTER_NE2A3_5", + "CFG_CENTER_LH10_18", + "CFG_CENTER_LH9_15", + "CFG_CENTER_FAN2_19", + "CFG_CENTER_IMUX2_3", + "CFG_CENTER_IMUX38_15", + "CFG_CENTER_IMUX14_13", + "CFG_CENTER_SW4A0_0", + "CFG_CENTER_EE4B3_3", + "CFG_CENTER_IMUX17_5", + "CFG_CENTER_NE4BEG0_11", + "CFG_CENTER_BYP1_8", + "CFG_CENTER_LH6_8", + "CFG_CENTER_BLOCK_OUTS_B2_3", + "CFG_CENTER_LOGIC_OUTS_B12_4", + "CFG_CENTER_BYP7_0", + "CFG_CENTER_IMUX0_19", + "CFG_CENTER_ICAP1_I15", + "CFG_CENTER_NW2A1_1", + "CFG_CENTER_LOGIC_OUTS_B18_18", + "CFG_CENTER_WW4A2_13", + "CFG_CENTER_SE4BEG0_0", + "CFG_CENTER_IMUX13_5", + "CFG_CENTER_NW2A3_5", + "CFG_CENTER_EE2BEG0_3", + "CFG_CENTER_ER1BEG0_8", + "CFG_CENTER_WW2A3_12", + "CFG_CENTER_IMUX4_8", + "CFG_CENTER_EE4B3_2", + "CFG_CENTER_MID_USR_ACCESS_DATA8", + "CFG_CENTER_BYP2_3", + "CFG_CENTER_IMUX38_5", + "CFG_CENTER_EE4A1_6", + "CFG_CENTER_WW4C0_4", + "CFG_CENTER_EE2A1_18", + "CFG_CENTER_USR_ACCESS_DATA24", + "CFG_CENTER_IMUX9_7", + "CFG_CENTER_IMUX23_13", + "CFG_CENTER_FAN7_19", + "CFG_CENTER_BYP2_9", + "CFG_CENTER_IMUX32_17", + "CFG_CENTER_SW4A3_12", + "CFG_CENTER_EE4BEG3_2", + "CFG_CENTER_SE4BEG1_0", + "CFG_CENTER_EE4B2_13", + "CFG_CENTER_WW2END0_2", + "CFG_CENTER_SE4BEG0_15", + "CFG_CENTER_LOGIC_OUTS_B22_11", + "CFG_CENTER_NW4END3_17", + "CFG_CENTER_SW4END1_15", + "CFG_CENTER_IMUX2_19", + "CFG_CENTER_SE4C3_19", + "CFG_CENTER_LOGIC_OUTS_B6_17", + "CFG_CENTER_IMUX29_0", + "CFG_CENTER_FAN1_13", + "CFG_CENTER_WW2A0_19", + "CFG_CENTER_SW4END3_13", + "CFG_CENTER_IMUX18_10", + "CFG_CENTER_EE4A0_0", + "CFG_CENTER_IMUX9_0", + "CFG_CENTER_ER1BEG3_6", + "CFG_CENTER_NW4END0_2", + "CFG_CENTER_NW2A3_14", + "CFG_CENTER_EE4BEG2_10", + "CFG_CENTER_ER1BEG0_10", + "CFG_CENTER_FAN6_12", + "CFG_CENTER_LOGIC_OUTS_B1_8", + "CFG_CENTER_NE4C1_0", + "CFG_CENTER_EE4A1_0", + "CFG_CENTER_USR_ACCESS_DATA16", + "CFG_CENTER_LOGIC_OUTS_B12_2", + "CFG_CENTER_WW2END3_0", + "CFG_CENTER_SE4C2_17", + "CFG_CENTER_WW4END1_10", + "CFG_CENTER_ICAP0_O27", + "CFG_CENTER_FAN7_17", + "CFG_CENTER_LOGIC_OUTS_B14_16", + "CFG_CENTER_IMUX43_0", + "CFG_CENTER_IMUX3_8", + "CFG_CENTER_SW4A1_4", + "CFG_CENTER_NE4BEG1_3", + "CFG_CENTER_EE2A0_7", + "CFG_CENTER_IMUX0_7", + "CFG_CENTER_IMUX45_5", + "CFG_CENTER_EE4C1_4", + "CFG_CENTER_BLOCK_OUTS_B0_2", + "CFG_CENTER_IMUX43_1", + "CFG_CENTER_IMUX33_18", + "CFG_CENTER_NE2A0_5", + "CFG_CENTER_SE2A2_2", + "CFG_CENTER_SE2A0_15", + "CFG_CENTER_EE4A1_12", + "CFG_CENTER_NE4C2_17", + "CFG_CENTER_CTRL0_17", + "CFG_CENTER_SW4END2_19", + "CFG_CENTER_FAN7_8", + "CFG_CENTER_SW4A1_9", + "CFG_CENTER_WR1END3_15", + "CFG_CENTER_BYP7_5", + "CFG_CENTER_NE4BEG1_10", + "CFG_CENTER_NE2A2_11", + "CFG_CENTER_CTRL0_14", + "CFG_CENTER_LOGIC_OUTS_B16_0", + "CFG_CENTER_EL1BEG2_5", + "CFG_CENTER_EE2A0_17", + "CFG_CENTER_EE4C0_0", + "CFG_CENTER_NE4BEG1_8", + "CFG_CENTER_BSCAN4_TMS", + "CFG_CENTER_IMUX9_10", + "CFG_CENTER_IMUX13_6", + "CFG_CENTER_NW2A3_0", + "CFG_CENTER_IMUX39_2", + "CFG_CENTER_FAN5_16", + "CFG_CENTER_LOGIC_OUTS_B11_6", + "CFG_CENTER_IMUX16_0", + "CFG_CENTER_WR1END0_5", + "CFG_CENTER_SW4A2_14", + "CFG_CENTER_SE4BEG0_5", + "CFG_CENTER_LOGIC_OUTS_B1_19", + "CFG_CENTER_ER1BEG1_11", + "CFG_CENTER_BLOCK_OUTS_B1_17", + "CFG_CENTER_IMUX23_17", + "CFG_CENTER_IMUX22_2", + "CFG_CENTER_NW4END2_8", + "CFG_CENTER_USR_ACCESS_DATA7", + "CFG_CENTER_SE4BEG1_11", + "CFG_CENTER_FAN2_17", + "CFG_CENTER_IMUX43_15", + "CFG_CENTER_LOGIC_OUTS_B23_8", + "CFG_CENTER_FAN3_5", + "CFG_CENTER_FAN1_19", + "CFG_CENTER_WW4A3_11", + "CFG_CENTER_CLK1_3", + "CFG_CENTER_IMUX15_6", + "CFG_CENTER_BSCAN4_RUNTEST", + "CFG_CENTER_LOGIC_OUTS_B20_10", + "CFG_CENTER_SW2A2_16", + "CFG_CENTER_SW2A1_1", + "CFG_CENTER_WL1END3_0", + "CFG_CENTER_WW4A2_15", + "CFG_CENTER_WL1END0_11", + "CFG_CENTER_FAN4_15", + "CFG_CENTER_IMUX36_6", + "CFG_CENTER_NW4A0_19", + "CFG_CENTER_LOGIC_OUTS_B22_4", + "CFG_CENTER_WL1END2_10", + "CFG_CENTER_BYP0_13", + "CFG_CENTER_ICAP0_I3", + "CFG_CENTER_NE4BEG2_3", + "CFG_CENTER_NE4BEG2_8", + "CFG_CENTER_IMUX10_8", + "CFG_CENTER_LOGIC_OUTS_B10_0", + "CFG_CENTER_WR1END2_16", + "CFG_CENTER_EL1BEG2_7", + "CFG_CENTER_WW2A3_18", + "CFG_CENTER_WW4B2_7", + "CFG_CENTER_IMUX10_17", + "CFG_CENTER_SW2A3_0", + "CFG_CENTER_LOGIC_OUTS_B9_7", + "CFG_CENTER_WW4B3_6", + "CFG_CENTER_WW4A2_17", + "CFG_CENTER_IMUX39_17", + "CFG_CENTER_SE4C0_18", + "CFG_CENTER_IMUX0_14", + "CFG_CENTER_LOGIC_OUTS_B18_12", + "CFG_CENTER_WW4END3_5", + "CFG_CENTER_EE4BEG2_3", + "CFG_CENTER_NW2A0_16", + "CFG_CENTER_NE2A1_17", + "CFG_CENTER_LH5_11", + "CFG_CENTER_IMUX17_6", + "CFG_CENTER_SW4END0_15", + "CFG_CENTER_NW4END1_13", + "CFG_CENTER_WL1END0_4", + "CFG_CENTER_WW2END1_1", + "CFG_CENTER_FAN4_5", + "CFG_CENTER_LOGIC_OUTS_B13_14", + "CFG_CENTER_BLOCK_OUTS_B3_5", + "CFG_CENTER_LH4_2", + "CFG_CENTER_FAN3_13", + "CFG_CENTER_WW2END1_9", + "CFG_CENTER_BLOCK_OUTS_B0_13", + "CFG_CENTER_BLOCK_OUTS_B2_17", + "CFG_CENTER_IMUX5_0", + "CFG_CENTER_WW4C2_3", + "CFG_CENTER_WW4C0_1", + "CFG_CENTER_NW2A3_7", + "CFG_CENTER_EE4A1_5", + "CFG_CENTER_CTRL1_19", + "CFG_CENTER_IMUX1_14", + "CFG_CENTER_IMUX33_8", + "CFG_CENTER_NE4BEG2_5", + "CFG_CENTER_EE4B1_6", + "CFG_CENTER_IMUX14_15", + "CFG_CENTER_IMUX7_8", + "CFG_CENTER_STARTUP_CFGMCLK", + "CFG_CENTER_USR_ACCESS_DATA3", + "CFG_CENTER_LOGIC_OUTS_B14_15", + "CFG_CENTER_WW4END1_19", + "CFG_CENTER_EE2A2_14", + "CFG_CENTER_ER1BEG1_10", + "CFG_CENTER_IMUX45_8", + "CFG_CENTER_NE2A0_14", + "CFG_CENTER_BYP2_17", + "CFG_CENTER_EE2BEG0_13", + "CFG_CENTER_CTRL1_17", + "CFG_CENTER_WW2A1_6", + "CFG_CENTER_SE4C1_6", + "CFG_CENTER_IMUX39_18", + "CFG_CENTER_ICAP0_I15", + "CFG_CENTER_SW4A2_0", + "CFG_CENTER_NE2A2_9", + "CFG_CENTER_IMUX11_17", + "CFG_CENTER_WL1END2_18", + "CFG_CENTER_ICAP0_O5", + "CFG_CENTER_ICAP0_I0", + "CFG_CENTER_EE4BEG0_12", + "CFG_CENTER_NE4BEG1_1", + "CFG_CENTER_IMUX39_6", + "CFG_CENTER_WL1END2_19", + "CFG_CENTER_EE4C3_5", + "CFG_CENTER_IMUX23_10", + "CFG_CENTER_NW2A0_17", + "CFG_CENTER_NE2A1_15", + "CFG_CENTER_BLOCK_OUTS_B3_9", + "CFG_CENTER_SW4A0_17", + "CFG_CENTER_SE2A0_3", + "CFG_CENTER_NW2A1_2", + "CFG_CENTER_NW4END0_10", + "CFG_CENTER_BLOCK_OUTS_B1_15", + "CFG_CENTER_WW4B0_16", + "CFG_CENTER_BLOCK_OUTS_B3_7", + "CFG_CENTER_ICAP0_O10", + "CFG_CENTER_LOGIC_OUTS_B9_8", + "CFG_CENTER_IMUX4_11", + "CFG_CENTER_IMUX11_18", + "CFG_CENTER_NE2A3_11", + "CFG_CENTER_WW4C3_5", + "CFG_CENTER_BYP2_0", + "CFG_CENTER_EE2A0_16", + "CFG_CENTER_NE2A1_19", + "CFG_CENTER_EL1BEG0_9", + "CFG_CENTER_BLOCK_OUTS_B2_13", + "CFG_CENTER_BYP4_12", + "CFG_CENTER_IMUX47_3", + "CFG_CENTER_IMUX25_17", + "CFG_CENTER_EE4C2_2", + "CFG_CENTER_LOGIC_OUTS_B16_2", + "CFG_CENTER_LH7_18", + "CFG_CENTER_FAN0_14", + "CFG_CENTER_FAN6_3", + "CFG_CENTER_LOGIC_OUTS_B8_12", + "CFG_CENTER_SE4BEG2_4", + "CFG_CENTER_EE4B3_15", + "CFG_CENTER_WW4B2_6", + "CFG_CENTER_SE4C0_15", + "CFG_CENTER_NE4C2_19", + "CFG_CENTER_NE4C3_5", + "CFG_CENTER_EE4B2_6", + "CFG_CENTER_LOGIC_OUTS_B18_0", + "CFG_CENTER_IMUX23_15", + "CFG_CENTER_LOGIC_OUTS_B5_2", + "CFG_CENTER_MID_USR_ACCESS_DATA2", + "CFG_CENTER_BLOCK_OUTS_B1_19", + "CFG_CENTER_NW4A3_1", + "CFG_CENTER_SE4C2_10", + "CFG_CENTER_WW4B2_18", + "CFG_CENTER_SE4C1_19", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA9", + "CFG_CENTER_WR1END3_9", + "CFG_CENTER_EE4C2_19", + "CFG_CENTER_IMUX16_11", + "CFG_CENTER_EE4A2_2", + "CFG_CENTER_ER1BEG0_12", + "CFG_CENTER_SE2A1_0", + "CFG_CENTER_IMUX11_12", + "CFG_CENTER_ICAP1_I20", + "CFG_CENTER_CTRL1_10", + "CFG_CENTER_FAN7_4", + "CFG_CENTER_IMUX47_12", + "CFG_CENTER_WW4A2_10", + "CFG_CENTER_NW4A3_7", + "CFG_CENTER_SE4C3_17", + "CFG_CENTER_EL1BEG2_4", + "CFG_CENTER_WR1END2_11", + "CFG_CENTER_IMUX0_9", + "CFG_CENTER_NE4C3_19", + "CFG_CENTER_BYP6_19", + "CFG_CENTER_NE4BEG2_16", + "CFG_CENTER_LOGIC_OUTS_B11_18", + "CFG_CENTER_EE4C1_3", + "CFG_CENTER_WR1END3_1", + "CFG_CENTER_IMUX36_10", + "CFG_CENTER_IMUX47_11", + "CFG_CENTER_IMUX38_12", + "CFG_CENTER_IMUX13_0", + "CFG_CENTER_WW4B0_5", + "CFG_CENTER_CTRL0_8", + "CFG_CENTER_WW4END0_15", + "CFG_CENTER_WW4A0_9", + "CFG_CENTER_BYP6_4", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA0", + "CFG_CENTER_BLOCK_OUTS_B0_19", + "CFG_CENTER_SE2A2_9", + "CFG_CENTER_NW2A3_2", + "CFG_CENTER_USR_ACCESS_DATA29", + "CFG_CENTER_IMUX47_8", + "CFG_CENTER_IMUX20_4", + "CFG_CENTER_LH8_10", + "CFG_CENTER_WW4C1_0", + "CFG_CENTER_SE4C0_9", + "CFG_CENTER_BYP1_9", + "CFG_CENTER_EE2BEG0_0", + "CFG_CENTER_LOGIC_OUTS_B12_13", + "CFG_CENTER_IMUX22_4", + "CFG_CENTER_IMUX15_4", + "CFG_CENTER_SW2A3_11", + "CFG_CENTER_NW2A3_1", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA7", + "CFG_CENTER_IMUX33_0", + "CFG_CENTER_IMUX13_3", + "CFG_CENTER_EL1BEG2_15", + "CFG_CENTER_WW2END0_11", + "CFG_CENTER_CFG_IO_ACCESS_RDWRB", + "CFG_CENTER_EL1BEG3_15", + "CFG_CENTER_BYP6_1", + "CFG_CENTER_EE2A2_17", + "CFG_CENTER_SW2A1_9", + "CFG_CENTER_ICAP0_I2", + "CFG_CENTER_ER1BEG2_6", + "CFG_CENTER_EE2BEG1_1", + "CFG_CENTER_ICAP1_RDWRB", + "CFG_CENTER_LH1_11", + "CFG_CENTER_IMUX3_7", + "CFG_CENTER_EE4B3_17", + "CFG_CENTER_NW2A1_13", + "CFG_CENTER_LH12_8", + "CFG_CENTER_NE4C1_6", + "CFG_CENTER_SW2A0_15", + "CFG_CENTER_SW2A3_14", + "CFG_CENTER_IMUX17_14", + "CFG_CENTER_BYP0_5", + "CFG_CENTER_EL1BEG1_13", + "CFG_CENTER_WW2A0_13", + "CFG_CENTER_WR1END0_2", + "CFG_CENTER_SE2A0_9", + "CFG_CENTER_SE2A0_0", + "CFG_CENTER_EE4C1_13", + "CFG_CENTER_EL1BEG1_1", + "CFG_CENTER_NW4END1_17", + "CFG_CENTER_LOGIC_OUTS_B20_12", + "CFG_CENTER_LOGIC_OUTS_B6_3", + "CFG_CENTER_LOGIC_OUTS_B21_17", + "CFG_CENTER_WR1END2_5", + "CFG_CENTER_LOGIC_OUTS_B0_18", + "CFG_CENTER_IMUX7_15", + "CFG_CENTER_SW4END0_4", + "CFG_CENTER_IMUX6_15", + "CFG_CENTER_IMUX43_9", + "CFG_CENTER_NE4C3_10", + "CFG_CENTER_EE4A0_15", + "CFG_CENTER_IMUX18_0", + "CFG_CENTER_ICAP0_O20", + "CFG_CENTER_WW4C3_14", + "CFG_CENTER_CLK1_1", + "CFG_CENTER_ICAP0_I31", + "CFG_CENTER_ICAP1_I16", + "CFG_CENTER_LH1_6", + "CFG_CENTER_WL1END3_15", + "CFG_CENTER_SW4A1_15", + "CFG_CENTER_EE4C3_2", + "CFG_CENTER_BSCAN1_TMS", + "CFG_CENTER_SE4BEG0_1", + "CFG_CENTER_IMUX30_7", + "CFG_CENTER_FAN1_16", + "CFG_CENTER_WW4END3_18", + "CFG_CENTER_LH11_6", + "CFG_CENTER_LH3_3", + "CFG_CENTER_IMUX4_5", + "CFG_CENTER_IMUX13_1", + "CFG_CENTER_SE4C3_4", + "CFG_CENTER_CLK1_7", + "CFG_CENTER_NW4A1_18", + "CFG_CENTER_IMUX22_16", + "CFG_CENTER_EE4BEG0_1", + "CFG_CENTER_WW2A1_10", + "CFG_CENTER_LOGIC_OUTS_B15_7", + "CFG_CENTER_IMUX30_12", + "CFG_CENTER_IMUX1_13", + "CFG_CENTER_LOGIC_OUTS_B22_6", + "CFG_CENTER_SE4C1_18", + "CFG_CENTER_NW2A0_4", + "CFG_CENTER_IMUX19_0", + "CFG_CENTER_IMUX39_19", + "CFG_CENTER_NW4A3_14", + "CFG_CENTER_EE4A0_19", + "CFG_CENTER_IMUX28_3", + "CFG_CENTER_EE2A2_3", + "CFG_CENTER_LOGIC_OUTS_B20_19", + "CFG_CENTER_NW2A1_0", + "CFG_CENTER_IMUX28_9", + "CFG_CENTER_NW2A2_11", + "CFG_CENTER_IMUX4_13", + "CFG_CENTER_NW4END3_13", + "CFG_CENTER_NW4A2_4", + "CFG_CENTER_LOGIC_OUTS_B21_7", + "CFG_CENTER_FAN5_13", + "CFG_CENTER_ER1BEG0_17", + "CFG_CENTER_FAN5_2", + "CFG_CENTER_IMUX12_0", + "CFG_CENTER_ICAP1_O12", + "CFG_CENTER_IMUX32_18", + "CFG_CENTER_NW4A0_10", + "CFG_CENTER_SW2A0_13", + "CFG_CENTER_IMUX40_5", + "CFG_CENTER_IMUX22_17", + "CFG_CENTER_WW4B1_13", + "CFG_CENTER_ICAP1_O22", + "CFG_CENTER_IMUX19_19", + "CFG_CENTER_WW4END2_9", + "CFG_CENTER_SE4C0_14", + "CFG_CENTER_FAN6_13", + "CFG_CENTER_WW4A1_11", + "CFG_CENTER_SW2A2_11", + "CFG_CENTER_IMUX46_1", + "CFG_CENTER_BYP5_4", + "CFG_CENTER_WW2END1_13", + "CFG_CENTER_NE2A3_19", + "CFG_CENTER_NW4END2_7", + "CFG_CENTER_WW2A1_7", + "CFG_CENTER_CK_BUFHCLK5", + "CFG_CENTER_NE2A2_8", + "CFG_CENTER_SW4END2_14", + "CFG_CENTER_EE2BEG2_1", + "CFG_CENTER_SW4A3_15", + "CFG_CENTER_WW4B0_17", + "CFG_CENTER_SW2A3_19", + "CFG_CENTER_LH11_1", + "CFG_CENTER_EE4BEG3_4", + "CFG_CENTER_SW2A0_4", + "CFG_CENTER_BSCAN2_SHIFT", + "CFG_CENTER_IMUX3_6", + "CFG_CENTER_LOGIC_OUTS_B18_9", + "CFG_CENTER_WW4A3_9", + "CFG_CENTER_SE4C2_16", + "CFG_CENTER_IMUX25_8", + "CFG_CENTER_LOGIC_OUTS_B22_2", + "CFG_CENTER_LOGIC_OUTS_B5_9", + "CFG_CENTER_IMUX8_4", + "CFG_CENTER_ER1BEG0_14", + "CFG_CENTER_EL1BEG1_11", + "CFG_CENTER_IMUX46_7", + "CFG_CENTER_NW4END1_18", + "CFG_CENTER_EE4B0_9", + "CFG_CENTER_NW4A1_16", + "CFG_CENTER_SE4BEG1_3", + "CFG_CENTER_CK_BUFRCLK3", + "CFG_CENTER_EL1BEG3_10", + "CFG_CENTER_ICAP0_I12", + "CFG_CENTER_LH5_12", + "CFG_CENTER_IMUX7_19", + "CFG_CENTER_LOGIC_OUTS_B23_10", + "CFG_CENTER_BYP5_6", + "CFG_CENTER_IMUX28_19", + "CFG_CENTER_BYP4_16", + "CFG_CENTER_IMUX26_19", + "CFG_CENTER_EE4B1_17", + "CFG_CENTER_NE4C0_10", + "CFG_CENTER_STARTUP_GSR", + "CFG_CENTER_ICAP1_I27", + "CFG_CENTER_IMUX17_12", + "CFG_CENTER_IMUX34_3", + "CFG_CENTER_BYP1_1", + "CFG_CENTER_SW4END0_16", + "CFG_CENTER_BLOCK_OUTS_B2_10", + "CFG_CENTER_LOGIC_OUTS_B12_14", + "CFG_CENTER_DCIRESET_RST", + "CFG_CENTER_ICAP0_I14", + "CFG_CENTER_LH7_16", + "CFG_CENTER_FAN3_3", + "CFG_CENTER_IMUX46_12", + "CFG_CENTER_SW4A1_11", + "CFG_CENTER_EE4C3_14", + "CFG_CENTER_LH10_10", + "CFG_CENTER_BYP3_19", + "CFG_CENTER_LH2_0", + "CFG_CENTER_NE4C2_2", + "CFG_CENTER_BYP0_15", + "CFG_CENTER_IMUX43_17", + "CFG_CENTER_EE4A0_10", + "CFG_CENTER_FAN5_4", + "CFG_CENTER_NE2A1_4", + "CFG_CENTER_CK_IN8", + "CFG_CENTER_EE2A3_17", + "CFG_CENTER_IMUX42_12", + "CFG_CENTER_EE4B3_13", + "CFG_CENTER_LOGIC_OUTS_B19_12", + "CFG_CENTER_LOGIC_OUTS_B5_17", + "CFG_CENTER_IMUX28_8", + "CFG_CENTER_SW4END2_17", + "CFG_CENTER_SW2A2_2", + "CFG_CENTER_IMUX37_0", + "CFG_CENTER_WW4C0_15", + "CFG_CENTER_NW4A0_11", + "CFG_CENTER_WW2A3_9", + "CFG_CENTER_LOGIC_OUTS_B18_4", + "CFG_CENTER_USR_ACCESS_DATA9", + "CFG_CENTER_IMUX40_16", + "CFG_CENTER_FRAME_ECC_SYNWORD1", + "CFG_CENTER_IMUX35_2", + "CFG_CENTER_IMUX28_4", + "CFG_CENTER_WW4B3_18", + "CFG_CENTER_FAN2_10", + "CFG_CENTER_WW4A0_6", + "CFG_CENTER_WW4A2_19", + "CFG_CENTER_BYP2_11", + "CFG_CENTER_EE4BEG0_14", + "CFG_CENTER_IMUX17_2", + "CFG_CENTER_WL1END3_13", + "CFG_CENTER_SW2A2_10", + "CFG_CENTER_WL1END2_6", + "CFG_CENTER_WW4END0_17", + "CFG_CENTER_EE4BEG2_19", + "CFG_CENTER_EE4B0_1", + "CFG_CENTER_IMUX31_14", + "CFG_CENTER_NE4BEG3_3", + "CFG_CENTER_LOGIC_OUTS_B20_6", + "CFG_CENTER_FAN7_5", + "CFG_CENTER_LOGIC_OUTS_B17_11", + "CFG_CENTER_WL1END0_13", + "CFG_CENTER_EE4A2_9", + "CFG_CENTER_LH7_2", + "CFG_CENTER_IMUX27_7", + "CFG_CENTER_BYP4_4", + "CFG_CENTER_NE4C0_9", + "CFG_CENTER_IMUX4_4", + "CFG_CENTER_IMUX9_2", + "CFG_CENTER_NW4END0_13", + "CFG_CENTER_WL1END3_4", + "CFG_CENTER_IMUX14_2", + "CFG_CENTER_NW4A3_16", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA18", + "CFG_CENTER_IMUX42_1", + "CFG_CENTER_NW2A3_4", + "CFG_CENTER_ICAP0_I10", + "CFG_CENTER_SE2A1_8", + "CFG_CENTER_FAN1_11", + "CFG_CENTER_FRAME_ECC_SYNDROMEVALID", + "CFG_CENTER_NW2A1_6", + "CFG_CENTER_IMUX35_18", + "CFG_CENTER_IMUX47_15", + "CFG_CENTER_FAN1_8", + "CFG_CENTER_ICAP1_O25", + "CFG_CENTER_IMUX22_9", + "CFG_CENTER_WW2END2_16", + "CFG_CENTER_SW2A2_17", + "CFG_CENTER_IMUX10_15", + "CFG_CENTER_ICAP1_I24", + "CFG_CENTER_EE4C1_11", + "CFG_CENTER_BLOCK_OUTS_B0_14", + "CFG_CENTER_IMUX9_1", + "CFG_CENTER_IMUX11_11", + "CFG_CENTER_SW4END0_3", + "CFG_CENTER_WL1END3_6", + "CFG_CENTER_EE4B2_2", + "CFG_CENTER_EE4A2_7", + "CFG_CENTER_WW4A3_17", + "CFG_CENTER_FRAME_ECC_SYNBIT0", + "CFG_CENTER_WW4C3_4", + "CFG_CENTER_BSCAN3_TMS", + "CFG_CENTER_NW4END1_9", + "CFG_CENTER_WW4END0_13", + "CFG_CENTER_WL1END1_10", + "CFG_CENTER_NW4END0_18", + "CFG_CENTER_FAN3_4", + "CFG_CENTER_EE4C0_4", + "CFG_CENTER_LOGIC_OUTS_B1_4", + "CFG_CENTER_IMUX35_3", + "CFG_CENTER_LH9_14", + "CFG_CENTER_SW2A1_19", + "CFG_CENTER_EL1BEG3_9", + "CFG_CENTER_NE2A1_0", + "CFG_CENTER_USR_ACCESS_DATA27", + "CFG_CENTER_IMUX9_8", + "CFG_CENTER_WW4B2_5", + "CFG_CENTER_LH6_13", + "CFG_CENTER_BYP5_16", + "CFG_CENTER_LH7_6", + "CFG_CENTER_FAN0_5", + "CFG_CENTER_WL1END3_8", + "CFG_CENTER_EE2A0_5", + "CFG_CENTER_WW2END3_2", + "CFG_CENTER_LH7_4", + "CFG_CENTER_ICAP1_I17", + "CFG_CENTER_LOGIC_OUTS_B15_18", + "CFG_CENTER_WR1END3_5", + "CFG_CENTER_BYP5_9", + "CFG_CENTER_EE4A1_17", + "CFG_CENTER_SW4END0_14", + "CFG_CENTER_LH2_7", + "CFG_CENTER_LOGIC_OUTS_B8_19", + "CFG_CENTER_BYP3_17", + "CFG_CENTER_LH7_12", + "CFG_CENTER_EL1BEG1_6", + "CFG_CENTER_NE4BEG0_5", + "CFG_CENTER_WW2END1_10", + "CFG_CENTER_IMUX31_12", + "CFG_CENTER_BYP7_6", + "CFG_CENTER_EE4A1_13", + "CFG_CENTER_LH4_6", + "CFG_CENTER_EE4C1_16", + "CFG_CENTER_NW2A1_18", + "CFG_CENTER_IMUX3_9", + "CFG_CENTER_SE4BEG2_7", + "CFG_CENTER_ICAP0_I17", + "CFG_CENTER_IMUX31_7", + "CFG_CENTER_IMUX35_11", + "CFG_CENTER_SW4A3_19", + "CFG_CENTER_WR1END0_19", + "CFG_CENTER_NW4END2_0", + "CFG_CENTER_WW2A0_2", + "CFG_CENTER_EE4BEG0_5", + "CFG_CENTER_NW4END3_16", + "CFG_CENTER_IMUX23_0", + "CFG_CENTER_STARTUP_PREQ", + "CFG_CENTER_NE4C1_7", + "CFG_CENTER_EE2BEG0_12", + "CFG_CENTER_ER1BEG2_5", + "CFG_CENTER_WW2A3_3", + "CFG_CENTER_BYP1_11", + "CFG_CENTER_ER1BEG3_12", + "CFG_CENTER_IMUX4_18", + "CFG_CENTER_IMUX44_14", + "CFG_CENTER_WR1END3_18", + "CFG_CENTER_IMUX27_13", + "CFG_CENTER_FAN6_1", + "CFG_CENTER_WW4C0_11", + "CFG_CENTER_NE2A1_14", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA26", + "CFG_CENTER_SW4A2_3", + "CFG_CENTER_SE4BEG1_5", + "CFG_CENTER_IMUX31_18", + "CFG_CENTER_CLK0_6", + "CFG_CENTER_WW2END3_17", + "CFG_CENTER_IMUX42_7", + "CFG_CENTER_WW4A2_5", + "CFG_CENTER_FAN4_18", + "CFG_CENTER_EE2BEG2_18", + "CFG_CENTER_LOGIC_OUTS_B0_8", + "CFG_CENTER_WW4B3_2", + "CFG_CENTER_WR1END2_0", + "CFG_CENTER_LOGIC_OUTS_B12_11", + "CFG_CENTER_IMUX22_7", + "CFG_CENTER_LOGIC_OUTS_B6_15", + "CFG_CENTER_NE4C0_14", + "CFG_CENTER_EE4A3_3", + "CFG_CENTER_IMUX7_1", + "CFG_CENTER_NE4BEG0_12", + "CFG_CENTER_IMUX25_6", + "CFG_CENTER_WW4B0_2", + "CFG_CENTER_NW4END1_3", + "CFG_CENTER_WR1END2_17", + "CFG_CENTER_WW4END2_4", + "CFG_CENTER_WW2END0_10", + "CFG_CENTER_ER1BEG0_7", + "CFG_CENTER_NE4C0_15", + "CFG_CENTER_EE2BEG2_4", + "CFG_CENTER_FAN2_4", + "CFG_CENTER_WW4C2_8", + "CFG_CENTER_BLOCK_OUTS_B2_1", + "CFG_CENTER_IMUX23_3", + "CFG_CENTER_IMUX14_14", + "CFG_CENTER_EE2BEG2_9", + "CFG_CENTER_IMUX31_9", + "CFG_CENTER_LOGIC_OUTS_B10_3", + "CFG_CENTER_WW4C3_1", + "CFG_CENTER_WW4C0_17", + "CFG_CENTER_IMUX13_15", + "CFG_CENTER_IMUX41_10", + "CFG_CENTER_CTRL1_6", + "CFG_CENTER_ER1BEG1_5", + "CFG_CENTER_IMUX45_0", + "CFG_CENTER_WL1END1_6", + "CFG_CENTER_NE2A0_11", + "CFG_CENTER_IMUX17_8", + "CFG_CENTER_EE2A0_8", + "CFG_CENTER_EE4C1_1", + "CFG_CENTER_WL1END1_11", + "CFG_CENTER_LH9_11", + "CFG_CENTER_IMUX29_4", + "CFG_CENTER_IMUX20_0", + "CFG_CENTER_IMUX1_16", + "CFG_CENTER_IMUX12_13", + "CFG_CENTER_IMUX42_16", + "CFG_CENTER_IMUX1_6", + "CFG_CENTER_LH5_2", + "CFG_CENTER_SE2A2_14", + "CFG_CENTER_IMUX3_12", + "CFG_CENTER_NE4C3_4", + "CFG_CENTER_LOGIC_OUTS_B19_5", + "CFG_CENTER_SE4BEG0_19", + "CFG_CENTER_IMUX41_5", + "CFG_CENTER_FAN0_8", + "CFG_CENTER_IMUX8_13", + "CFG_CENTER_IMUX6_14", + "CFG_CENTER_NE4BEG0_9", + "CFG_CENTER_IMUX46_19", + "CFG_CENTER_ICAP0_I11", + "CFG_CENTER_NE2A2_19", + "CFG_CENTER_SE2A1_16", + "CFG_CENTER_IMUX14_12", + "CFG_CENTER_NW2A0_9", + "CFG_CENTER_IMUX32_1", + "CFG_CENTER_FAN7_0", + "CFG_CENTER_IMUX22_12", + "CFG_CENTER_IMUX34_12", + "CFG_CENTER_SW4END1_9", + "CFG_CENTER_FAN2_2", + "CFG_CENTER_FRAME_ECC_FAR11", + "CFG_CENTER_IMUX44_10", + "CFG_CENTER_BYP0_3", + "CFG_CENTER_LH12_11", + "CFG_CENTER_IMUX14_8", + "CFG_CENTER_CK_BUFRCLK1", + "CFG_CENTER_LH2_8", + "CFG_CENTER_IMUX1_12", + "CFG_CENTER_NW4END2_11", + "CFG_CENTER_EE2A1_13", + "CFG_CENTER_EE2BEG3_18", + "CFG_CENTER_SW2A3_1", + "CFG_CENTER_LH6_4", + "CFG_CENTER_WW4A1_12", + "CFG_CENTER_SE4C0_19", + "CFG_CENTER_SW4A1_7", + "CFG_CENTER_IMUX13_7", + "CFG_CENTER_ICAP1_I9", + "CFG_CENTER_IMUX6_16", + "CFG_CENTER_IMUX39_12", + "CFG_CENTER_FAN0_16", + "CFG_CENTER_WW4END2_16", + "CFG_CENTER_FAN6_4", + "CFG_CENTER_NE4BEG1_0", + "CFG_CENTER_SE2A0_19", + "CFG_CENTER_SW4END2_6", + "CFG_CENTER_MID_USR_ACCESS_DATA3", + "CFG_CENTER_WW4END2_5", + "CFG_CENTER_WW2END0_18", + "CFG_CENTER_IMUX46_18", + "CFG_CENTER_LOGIC_OUTS_B5_16", + "CFG_CENTER_IMUX39_5", + "CFG_CENTER_BYP7_8", + "CFG_CENTER_LH6_12", + "CFG_CENTER_IMUX20_13", + "CFG_CENTER_SW4A2_2", + "CFG_CENTER_BYP0_7", + "CFG_CENTER_LOGIC_OUTS_B9_11", + "CFG_CENTER_WW4C2_11", + "CFG_CENTER_LOGIC_OUTS_B20_17", + "CFG_CENTER_CTRL1_16", + "CFG_CENTER_SW4END2_1", + "CFG_CENTER_BSCAN3_SHIFT", + "CFG_CENTER_IMUX40_1", + "CFG_CENTER_ER1BEG2_2", + "CFG_CENTER_LH2_19", + "CFG_CENTER_FAN1_1", + "CFG_CENTER_NE2A1_16", + "CFG_CENTER_SW4A2_11", + "CFG_CENTER_IMUX45_4", + "CFG_CENTER_LH8_15", + "CFG_CENTER_IMUX18_14", + "CFG_CENTER_LOGIC_OUTS_B13_11", + "CFG_CENTER_LOGIC_OUTS_B17_5", + "CFG_CENTER_LOGIC_OUTS_B3_12", + "CFG_CENTER_SW4END3_5", + "CFG_CENTER_IMUX32_9", + "CFG_CENTER_NW4A3_5", + "CFG_CENTER_EE4C1_0", + "CFG_CENTER_BLOCK_OUTS_B0_10", + "CFG_CENTER_NW2A2_15", + "CFG_CENTER_SE2A1_2", + "CFG_CENTER_WW4END0_16", + "CFG_CENTER_LH7_3", + "CFG_CENTER_EE2BEG1_8", + "CFG_CENTER_LH12_5", + "CFG_CENTER_LOGIC_OUTS_B16_3", + "CFG_CENTER_BSCAN1_SHIFT", + "CFG_CENTER_IMUX43_12", + "CFG_CENTER_WW2END3_18", + "CFG_CENTER_ICAP1_I19", + "CFG_CENTER_WR1END3_19", + "CFG_CENTER_SW4END1_1", + "CFG_CENTER_NW2A1_10", + "CFG_CENTER_ICAP1_O20", + "CFG_CENTER_EE4BEG2_11", + "CFG_CENTER_WL1END1_5", + "CFG_CENTER_IMUX47_2", + "CFG_CENTER_IMUX19_12", + "CFG_CENTER_WW2END2_12", + "CFG_CENTER_IMUX33_13", + "CFG_CENTER_LH2_13", + "CFG_CENTER_IMUX12_5", + "CFG_CENTER_IMUX22_6", + "CFG_CENTER_WW2A1_16", + "CFG_CENTER_IMUX36_4", + "CFG_CENTER_IMUX47_14", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA20", + "CFG_CENTER_STARTUP_USRDONEO", + "CFG_CENTER_LOGIC_OUTS_B17_17", + "CFG_CENTER_NE4C0_1", + "CFG_CENTER_IMUX6_18", + "CFG_CENTER_LOGIC_OUTS_B19_13", + "CFG_CENTER_USR_ACCESS_CFGCLK", + "CFG_CENTER_WW4END2_6", + "CFG_CENTER_USR_ACCESS_DATA6", + "CFG_CENTER_BLOCK_OUTS_B2_2", + "CFG_CENTER_SE2A1_9", + "CFG_CENTER_IMUX26_6", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA17", + "CFG_CENTER_IMUX3_13", + "CFG_CENTER_FRAME_ECC_FAR24", + "CFG_CENTER_NE2A1_2", + "CFG_CENTER_IMUX1_11", + "CFG_CENTER_SE4C1_9", + "CFG_CENTER_SW4A0_2", + "CFG_CENTER_SW4END2_5", + "CFG_CENTER_IMUX36_14", + "CFG_CENTER_WR1END2_19", + "CFG_CENTER_IMUX1_15", + "CFG_CENTER_CLK0_1", + "CFG_CENTER_IMUX37_6", + "CFG_CENTER_IMUX33_17", + "CFG_CENTER_WW2A3_0", + "CFG_CENTER_EE2BEG2_7", + "CFG_CENTER_ER1BEG1_16", + "CFG_CENTER_NW2A0_8", + "CFG_CENTER_LOGIC_OUTS_B8_9", + "CFG_CENTER_IMUX33_15", + "CFG_CENTER_SE2A2_15", + "CFG_CENTER_IMUX4_3", + "CFG_CENTER_IMUX16_5", + "CFG_CENTER_NE4C2_13", + "CFG_CENTER_BSCAN2_TDO", + "CFG_CENTER_NW4A1_19", + "CFG_CENTER_EL1BEG1_17", + "CFG_CENTER_NW2A2_5", + "CFG_CENTER_SE2A0_5", + "CFG_CENTER_ICAP1_O21", + "CFG_CENTER_FAN6_7", + "CFG_CENTER_FRAME_ECC_FAR16", + "CFG_CENTER_IMUX13_18", + "CFG_CENTER_NW2A2_8", + "CFG_CENTER_LH2_5", + "CFG_CENTER_CLK0_16", + "CFG_CENTER_IMUX5_16", + "CFG_CENTER_IMUX30_16", + "CFG_CENTER_EE2BEG2_6", + "CFG_CENTER_IMUX17_18", + "CFG_CENTER_LH8_0", + "CFG_CENTER_IMUX39_8", + "CFG_CENTER_WW4B3_14", + "CFG_CENTER_ER1BEG3_4", + "CFG_CENTER_LOGIC_OUTS_B15_2", + "CFG_CENTER_LOGIC_OUTS_B19_11", + "CFG_CENTER_IMUX17_19", + "CFG_CENTER_WW2END1_8", + "CFG_CENTER_WW4A3_0", + "CFG_CENTER_LH11_13", + "CFG_CENTER_EE2A1_15", + "CFG_CENTER_ER1BEG2_10", + "CFG_CENTER_LOGIC_OUTS_B1_17", + "CFG_CENTER_WW2END0_16", + "CFG_CENTER_NW4END2_16", + "CFG_CENTER_EE4A2_19", + "CFG_CENTER_WW4END0_18", + "CFG_CENTER_NE4C0_7", + "CFG_CENTER_EE4B2_15", + "CFG_CENTER_IMUX25_4", + "CFG_CENTER_BLOCK_OUTS_B1_6", + "CFG_CENTER_CTRL0_13", + "CFG_CENTER_FAN7_2", + "CFG_CENTER_NE4BEG2_6", + "CFG_CENTER_LOGIC_OUTS_B5_11", + "CFG_CENTER_NE2A3_3", + "CFG_CENTER_LOGIC_OUTS_B17_8", + "CFG_CENTER_SW4END0_19", + "CFG_CENTER_FAN1_10", + "CFG_CENTER_WW2A2_5", + "CFG_CENTER_IMUX26_4", + "CFG_CENTER_WW4A2_14", + "CFG_CENTER_EE4A1_19", + "CFG_CENTER_WW4B2_9", + "CFG_CENTER_BLOCK_OUTS_B3_3", + "CFG_CENTER_WR1END1_18", + "CFG_CENTER_IMUX28_16", + "CFG_CENTER_FAN3_7", + "CFG_CENTER_WW4END0_12", + "CFG_CENTER_WW2A0_14", + "CFG_CENTER_EE2A2_9", + "CFG_CENTER_BYP1_10", + "CFG_CENTER_WW2A3_1", + "CFG_CENTER_IMUX43_5", + "CFG_CENTER_WW4B1_10", + "CFG_CENTER_WW4A0_13", + "CFG_CENTER_EE2A1_5", + "CFG_CENTER_BYP3_12", + "CFG_CENTER_IMUX27_16", + "CFG_CENTER_EL1BEG2_6", + "CFG_CENTER_LH10_17", + "CFG_CENTER_LOGIC_OUTS_B3_2", + "CFG_CENTER_BSCAN3_UPDATE", + "CFG_CENTER_SE2A0_18", + "CFG_CENTER_LOGIC_OUTS_B0_3", + "CFG_CENTER_EL1BEG1_10", + "CFG_CENTER_IMUX3_3", + "CFG_CENTER_ER1BEG3_0", + "CFG_CENTER_WW4C2_4", + "CFG_CENTER_EE2BEG1_17", + "CFG_CENTER_WW4A0_3", + "CFG_CENTER_SE2A1_7", + "CFG_CENTER_IMUX42_10", + "CFG_CENTER_LH10_6", + "CFG_CENTER_WR1END1_15", + "CFG_CENTER_SW2A1_10", + "CFG_CENTER_BYP0_17" + ], + "pips": { + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O31->CFG_CENTER_LOGIC_OUTS_B16_14": { + "src_wire": "CFG_CENTER_ICAP1_O31", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_14", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX40_13->CFG_CENTER_ICAP1_I28": { + "src_wire": "CFG_CENTER_IMUX40_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I28", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR6->CFG_CENTER_LOGIC_OUTS_B16_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR6", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O15->CFG_CENTER_LOGIC_OUTS_B14_13": { + "src_wire": "CFG_CENTER_ICAP1_O15", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_DRCK->CFG_CENTER_LOGIC_OUTS_B20_2": { + "src_wire": "CFG_CENTER_BSCAN1_DRCK", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_CAPTURE->CFG_CENTER_LOGIC_OUTS_B11_11": { + "src_wire": "CFG_CENTER_BSCAN3_CAPTURE", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX42_12->CFG_CENTER_ICAP1_I14": { + "src_wire": "CFG_CENTER_IMUX42_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I14", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_SEL->CFG_CENTER_LOGIC_OUTS_B16_10": { + "src_wire": "CFG_CENTER_BSCAN3_SEL", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_10", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O16->CFG_CENTER_LOGIC_OUTS_B15_13": { + "src_wire": "CFG_CENTER_ICAP1_O16", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA28->CFG_CENTER_LOGIC_OUTS_B23_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA28", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX39_13->CFG_CENTER_ICAP1_I27": { + "src_wire": "CFG_CENTER_IMUX39_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I27", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O21->CFG_CENTER_LOGIC_OUTS_B21_4": { + "src_wire": "CFG_CENTER_ICAP0_O21", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA31->CFG_CENTER_LOGIC_OUTS_B10_1": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA31", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME2->CFG_CENTER_LOGIC_OUTS_B16_1": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME2", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX37_12->CFG_CENTER_ICAP1_I9": { + "src_wire": "CFG_CENTER_IMUX37_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR1->CFG_CENTER_LOGIC_OUTS_B11_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TCK->CFG_CENTER_LOGIC_OUTS_B20_11": { + "src_wire": "CFG_CENTER_BSCAN4_TCK", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR17->CFG_CENTER_LOGIC_OUTS_B11_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR17", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX39_8->CFG_CENTER_STARTUP_GTS": { + "src_wire": "CFG_CENTER_IMUX39_8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_GTS", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA4->CFG_CENTER_MID_USR_ACCESS_DATA4": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX31_4->CFG_CENTER_ICAP0_I3": { + "src_wire": "CFG_CENTER_IMUX31_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX28_12->CFG_CENTER_ICAP1_I0": { + "src_wire": "CFG_CENTER_IMUX28_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O29->CFG_CENTER_LOGIC_OUTS_B14_14": { + "src_wire": "CFG_CENTER_ICAP1_O29", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_14", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR19->CFG_CENTER_LOGIC_OUTS_B13_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR19", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX29_5->CFG_CENTER_ICAP0_I18": { + "src_wire": "CFG_CENTER_IMUX29_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I18", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATAVALID->CFG_CENTER_LOGIC_OUTS_B13_1": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATAVALID", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX32_12->CFG_CENTER_ICAP1_I4": { + "src_wire": "CFG_CENTER_IMUX32_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O18->CFG_CENTER_LOGIC_OUTS_B17_13": { + "src_wire": "CFG_CENTER_ICAP1_O18", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O12->CFG_CENTER_LOGIC_OUTS_B12_4": { + "src_wire": "CFG_CENTER_ICAP0_O12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_STARTUP_PREQ->CFG_CENTER_LOGIC_OUTS_B22_9": { + "src_wire": "CFG_CENTER_STARTUP_PREQ", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_RUNTEST->CFG_CENTER_LOGIC_OUTS_B9_2": { + "src_wire": "CFG_CENTER_BSCAN2_RUNTEST", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O11->CFG_CENTER_LOGIC_OUTS_B11_4": { + "src_wire": "CFG_CENTER_ICAP0_O11", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX32_4->CFG_CENTER_ICAP0_I4": { + "src_wire": "CFG_CENTER_IMUX32_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX35_13->CFG_CENTER_ICAP1_I23": { + "src_wire": "CFG_CENTER_IMUX35_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I23", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX29_4->CFG_CENTER_ICAP0_I1": { + "src_wire": "CFG_CENTER_IMUX29_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR9->CFG_CENTER_LOGIC_OUTS_B19_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR9", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA8->CFG_CENTER_MID_USR_ACCESS_DATA8": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX37_13->CFG_CENTER_ICAP1_I25": { + "src_wire": "CFG_CENTER_IMUX37_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I25", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TDI->CFG_CENTER_LOGIC_OUTS_B12_3": { + "src_wire": "CFG_CENTER_BSCAN1_TDI", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME5->CFG_CENTER_LOGIC_OUTS_B19_1": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX29_12->CFG_CENTER_ICAP1_I1": { + "src_wire": "CFG_CENTER_IMUX29_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX34_5->CFG_CENTER_ICAP0_I23": { + "src_wire": "CFG_CENTER_IMUX34_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I23", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME4->CFG_CENTER_LOGIC_OUTS_B18_1": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR23->CFG_CENTER_LOGIC_OUTS_B17_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR23", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_DRCK->CFG_CENTER_LOGIC_OUTS_B23_10": { + "src_wire": "CFG_CENTER_BSCAN4_DRCK", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_10", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O20->CFG_CENTER_LOGIC_OUTS_B20_4": { + "src_wire": "CFG_CENTER_ICAP0_O20", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O18->CFG_CENTER_LOGIC_OUTS_B18_4": { + "src_wire": "CFG_CENTER_ICAP0_O18", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD4->CFG_CENTER_LOGIC_OUTS_B8_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR7->CFG_CENTER_LOGIC_OUTS_B17_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR7", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O0->CFG_CENTER_LOGIC_OUTS_B23_11": { + "src_wire": "CFG_CENTER_ICAP1_O0", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_CAPTURE->CFG_CENTER_LOGIC_OUTS_B12_11": { + "src_wire": "CFG_CENTER_BSCAN4_CAPTURE", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_RESET->CFG_CENTER_LOGIC_OUTS_B18_2": { + "src_wire": "CFG_CENTER_BSCAN1_RESET", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_SHIFT->CFG_CENTER_LOGIC_OUTS_B17_3": { + "src_wire": "CFG_CENTER_BSCAN2_SHIFT", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_CLK1_6->CFG_CENTER_ICAP0_CLK": { + "src_wire": "CFG_CENTER_CLK1_6", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_SHIFT->CFG_CENTER_LOGIC_OUTS_B21_11": { + "src_wire": "CFG_CENTER_BSCAN3_SHIFT", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O5->CFG_CENTER_LOGIC_OUTS_B21_3": { + "src_wire": "CFG_CENTER_ICAP0_O5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O10->CFG_CENTER_LOGIC_OUTS_B21_12": { + "src_wire": "CFG_CENTER_ICAP1_O10", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O8->CFG_CENTER_LOGIC_OUTS_B8_3": { + "src_wire": "CFG_CENTER_ICAP0_O8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX43_12->CFG_CENTER_ICAP1_I15": { + "src_wire": "CFG_CENTER_IMUX43_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I15", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX42_5->CFG_CENTER_ICAP0_I31": { + "src_wire": "CFG_CENTER_IMUX42_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I31", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX33_13->CFG_CENTER_ICAP1_I21": { + "src_wire": "CFG_CENTER_IMUX33_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I21", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD1->CFG_CENTER_LOGIC_OUTS_B21_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME12->CFG_CENTER_LOGIC_OUTS_B12_2": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX36_8->CFG_CENTER_STARTUP_KEYCLEARB": { + "src_wire": "CFG_CENTER_IMUX36_8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_KEYCLEARB", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O16->CFG_CENTER_LOGIC_OUTS_B16_5": { + "src_wire": "CFG_CENTER_ICAP0_O16", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA27->CFG_CENTER_LOGIC_OUTS_B22_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA27", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TMS->CFG_CENTER_LOGIC_OUTS_B15_11": { + "src_wire": "CFG_CENTER_BSCAN3_TMS", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR0->CFG_CENTER_LOGIC_OUTS_B10_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR0", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O4->CFG_CENTER_LOGIC_OUTS_B15_12": { + "src_wire": "CFG_CENTER_ICAP1_O4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O19->CFG_CENTER_LOGIC_OUTS_B18_13": { + "src_wire": "CFG_CENTER_ICAP1_O19", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT2->CFG_CENTER_LOGIC_OUTS_B20_8": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT2", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_STARTUP_CFGMCLK->CFG_CENTER_LOGIC_OUTS_B18_5": { + "src_wire": "CFG_CENTER_STARTUP_CFGMCLK", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_CRCERROR->CFG_CENTER_LOGIC_OUTS_B15_10": { + "src_wire": "CFG_CENTER_FRAME_ECC_CRCERROR", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_10", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX39_5->CFG_CENTER_ICAP0_I28": { + "src_wire": "CFG_CENTER_IMUX39_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I28", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O7->CFG_CENTER_LOGIC_OUTS_B18_12": { + "src_wire": "CFG_CENTER_ICAP1_O7", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX28_5->CFG_CENTER_ICAP0_I17": { + "src_wire": "CFG_CENTER_IMUX28_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I17", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O22->CFG_CENTER_LOGIC_OUTS_B21_13": { + "src_wire": "CFG_CENTER_ICAP1_O22", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX39_12->CFG_CENTER_ICAP1_I11": { + "src_wire": "CFG_CENTER_IMUX39_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_CAPTURE->CFG_CENTER_LOGIC_OUTS_B22_2": { + "src_wire": "CFG_CENTER_BSCAN1_CAPTURE", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR21->CFG_CENTER_LOGIC_OUTS_B15_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR21", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD5->CFG_CENTER_LOGIC_OUTS_B9_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_RESET->CFG_CENTER_LOGIC_OUTS_B20_10": { + "src_wire": "CFG_CENTER_BSCAN3_RESET", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_10", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROMEVALID->CFG_CENTER_LOGIC_OUTS_B13_2": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROMEVALID", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TCK->CFG_CENTER_LOGIC_OUTS_B14_3": { + "src_wire": "CFG_CENTER_BSCAN1_TCK", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT4->CFG_CENTER_LOGIC_OUTS_B22_8": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX41_12->CFG_CENTER_ICAP1_I13": { + "src_wire": "CFG_CENTER_IMUX41_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O21->CFG_CENTER_LOGIC_OUTS_B20_13": { + "src_wire": "CFG_CENTER_ICAP1_O21", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX30_4->CFG_CENTER_ICAP0_I2": { + "src_wire": "CFG_CENTER_IMUX30_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_DRCK->CFG_CENTER_LOGIC_OUTS_B21_2": { + "src_wire": "CFG_CENTER_BSCAN2_DRCK", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX43_13->CFG_CENTER_ICAP1_I31": { + "src_wire": "CFG_CENTER_IMUX43_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I31", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA12->CFG_CENTER_MID_USR_ACCESS_DATA12": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR8->CFG_CENTER_LOGIC_OUTS_B18_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX27_5->CFG_CENTER_ICAP0_I16": { + "src_wire": "CFG_CENTER_IMUX27_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I16", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O24->CFG_CENTER_LOGIC_OUTS_B8_4": { + "src_wire": "CFG_CENTER_ICAP0_O24", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA2->CFG_CENTER_MID_USR_ACCESS_DATA2": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA2", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_STARTUP_CFGCLK->CFG_CENTER_LOGIC_OUTS_B14_10": { + "src_wire": "CFG_CENTER_STARTUP_CFGCLK", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_10", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_CLK1_7->CFG_CENTER_STARTUP_USRCCLKO": { + "src_wire": "CFG_CENTER_CLK1_7", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_USRCCLKO", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_DRCK->CFG_CENTER_LOGIC_OUTS_B22_10": { + "src_wire": "CFG_CENTER_BSCAN3_DRCK", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_10", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX41_8->CFG_CENTER_STARTUP_USRDONETS": { + "src_wire": "CFG_CENTER_IMUX41_8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_USRDONETS", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O24->CFG_CENTER_LOGIC_OUTS_B23_13": { + "src_wire": "CFG_CENTER_ICAP1_O24", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR4->CFG_CENTER_LOGIC_OUTS_B14_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_SHIFT->CFG_CENTER_LOGIC_OUTS_B22_11": { + "src_wire": "CFG_CENTER_BSCAN4_SHIFT", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_SHIFT->CFG_CENTER_LOGIC_OUTS_B16_3": { + "src_wire": "CFG_CENTER_BSCAN1_SHIFT", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_UPDATE->CFG_CENTER_LOGIC_OUTS_B18_10": { + "src_wire": "CFG_CENTER_BSCAN3_UPDATE", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_10", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O1->CFG_CENTER_LOGIC_OUTS_B12_12": { + "src_wire": "CFG_CENTER_ICAP1_O1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME11->CFG_CENTER_LOGIC_OUTS_B11_2": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME11", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O23->CFG_CENTER_LOGIC_OUTS_B22_13": { + "src_wire": "CFG_CENTER_ICAP1_O23", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA29->CFG_CENTER_LOGIC_OUTS_B8_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA29", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O10->CFG_CENTER_LOGIC_OUTS_B10_4": { + "src_wire": "CFG_CENTER_ICAP0_O10", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX32_13->CFG_CENTER_ICAP1_I20": { + "src_wire": "CFG_CENTER_IMUX32_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I20", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_UPDATE->CFG_CENTER_LOGIC_OUTS_B16_2": { + "src_wire": "CFG_CENTER_BSCAN1_UPDATE", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX43_11->CFG_CENTER_ICAP1_CSIB": { + "src_wire": "CFG_CENTER_IMUX43_11", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_CSIB", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O28->CFG_CENTER_LOGIC_OUTS_B12_5": { + "src_wire": "CFG_CENTER_ICAP0_O28", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR11->CFG_CENTER_LOGIC_OUTS_B21_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR11", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR12->CFG_CENTER_LOGIC_OUTS_B22_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_CAPTURE->CFG_CENTER_LOGIC_OUTS_B23_2": { + "src_wire": "CFG_CENTER_BSCAN2_CAPTURE", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA19->CFG_CENTER_LOGIC_OUTS_B14_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA19", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TMS->CFG_CENTER_LOGIC_OUTS_B11_3": { + "src_wire": "CFG_CENTER_BSCAN2_TMS", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX31_5->CFG_CENTER_ICAP0_I20": { + "src_wire": "CFG_CENTER_IMUX31_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I20", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O3->CFG_CENTER_LOGIC_OUTS_B14_12": { + "src_wire": "CFG_CENTER_ICAP1_O3", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O2->CFG_CENTER_LOGIC_OUTS_B13_12": { + "src_wire": "CFG_CENTER_ICAP1_O2", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX33_12->CFG_CENTER_ICAP1_I5": { + "src_wire": "CFG_CENTER_IMUX33_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O13->CFG_CENTER_LOGIC_OUTS_B12_13": { + "src_wire": "CFG_CENTER_ICAP1_O13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME8->CFG_CENTER_LOGIC_OUTS_B22_1": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_DCIRESET_LOCKED->CFG_CENTER_LOGIC_OUTS_B21_9": { + "src_wire": "CFG_CENTER_DCIRESET_LOCKED", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX43_4->CFG_CENTER_ICAP0_I15": { + "src_wire": "CFG_CENTER_IMUX43_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I15", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_CLK1_9->CFG_CENTER_CAPTURE_CLK": { + "src_wire": "CFG_CENTER_CLK1_9", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_CAPTURE_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_RUNTEST->CFG_CENTER_LOGIC_OUTS_B14_11": { + "src_wire": "CFG_CENTER_BSCAN4_RUNTEST", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX28_13->CFG_CENTER_ICAP1_I16": { + "src_wire": "CFG_CENTER_IMUX28_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I16", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O30->CFG_CENTER_LOGIC_OUTS_B14_5": { + "src_wire": "CFG_CENTER_ICAP0_O30", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX33_5->CFG_CENTER_ICAP0_I22": { + "src_wire": "CFG_CENTER_IMUX33_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I22", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA16->CFG_CENTER_LOGIC_OUTS_B11_1": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA16", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT1->CFG_CENTER_LOGIC_OUTS_B19_8": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX38_5->CFG_CENTER_ICAP0_I27": { + "src_wire": "CFG_CENTER_IMUX38_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I27", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O3->CFG_CENTER_LOGIC_OUTS_B19_3": { + "src_wire": "CFG_CENTER_ICAP0_O3", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME6->CFG_CENTER_LOGIC_OUTS_B20_1": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME6", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD0->CFG_CENTER_LOGIC_OUTS_B20_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD0", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O7->CFG_CENTER_LOGIC_OUTS_B23_3": { + "src_wire": "CFG_CENTER_ICAP0_O7", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR22->CFG_CENTER_LOGIC_OUTS_B16_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR22", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_RUNTEST->CFG_CENTER_LOGIC_OUTS_B8_2": { + "src_wire": "CFG_CENTER_BSCAN1_RUNTEST", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA17->CFG_CENTER_LOGIC_OUTS_B12_1": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA17", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX40_8->CFG_CENTER_STARTUP_GSR": { + "src_wire": "CFG_CENTER_IMUX40_8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_GSR", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O29->CFG_CENTER_LOGIC_OUTS_B13_5": { + "src_wire": "CFG_CENTER_ICAP0_O29", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_MID_ICAP1_CLK->CFG_CENTER_ICAP1_CLK": { + "src_wire": "CFG_CENTER_MID_ICAP1_CLK", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_SEL->CFG_CENTER_LOGIC_OUTS_B17_10": { + "src_wire": "CFG_CENTER_BSCAN4_SEL", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_10", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR18->CFG_CENTER_LOGIC_OUTS_B12_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR18", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O2->CFG_CENTER_LOGIC_OUTS_B18_3": { + "src_wire": "CFG_CENTER_ICAP0_O2", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR5->CFG_CENTER_LOGIC_OUTS_B15_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX41_11->CFG_CENTER_ICAP0_RDWRB": { + "src_wire": "CFG_CENTER_IMUX41_11", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_RDWRB", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX35_12->CFG_CENTER_ICAP1_I7": { + "src_wire": "CFG_CENTER_IMUX35_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA1->CFG_CENTER_LOGIC_OUTS_B12_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX34_13->CFG_CENTER_ICAP1_I22": { + "src_wire": "CFG_CENTER_IMUX34_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I22", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA23->CFG_CENTER_LOGIC_OUTS_B18_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA23", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX31_13->CFG_CENTER_ICAP1_I19": { + "src_wire": "CFG_CENTER_IMUX31_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX29_13->CFG_CENTER_ICAP1_I17": { + "src_wire": "CFG_CENTER_IMUX29_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I17", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O25->CFG_CENTER_LOGIC_OUTS_B10_14": { + "src_wire": "CFG_CENTER_ICAP1_O25", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_14", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TMS->CFG_CENTER_LOGIC_OUTS_B10_3": { + "src_wire": "CFG_CENTER_BSCAN1_TMS", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O5->CFG_CENTER_LOGIC_OUTS_B16_12": { + "src_wire": "CFG_CENTER_ICAP1_O5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX40_4->CFG_CENTER_ICAP0_I12": { + "src_wire": "CFG_CENTER_IMUX40_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O12->CFG_CENTER_LOGIC_OUTS_B23_12": { + "src_wire": "CFG_CENTER_ICAP1_O12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX34_12->CFG_CENTER_ICAP1_I6": { + "src_wire": "CFG_CENTER_IMUX34_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX35_5->CFG_CENTER_ICAP0_I24": { + "src_wire": "CFG_CENTER_IMUX35_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I24", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX36_13->CFG_CENTER_ICAP1_I24": { + "src_wire": "CFG_CENTER_IMUX36_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I24", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX30_5->CFG_CENTER_ICAP0_I19": { + "src_wire": "CFG_CENTER_IMUX30_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I19", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA6->CFG_CENTER_MID_USR_ACCESS_DATA6": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA6", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA26->CFG_CENTER_LOGIC_OUTS_B21_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA26", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA30->CFG_CENTER_LOGIC_OUTS_B9_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA30", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX42_4->CFG_CENTER_ICAP0_I14": { + "src_wire": "CFG_CENTER_IMUX42_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I14", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O27->CFG_CENTER_LOGIC_OUTS_B12_14": { + "src_wire": "CFG_CENTER_ICAP1_O27", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_14", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR13->CFG_CENTER_LOGIC_OUTS_B23_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA25->CFG_CENTER_LOGIC_OUTS_B20_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA25", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT0->CFG_CENTER_LOGIC_OUTS_B18_8": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT0", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA14->CFG_CENTER_MID_USR_ACCESS_DATA14": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA14", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA14", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O15->CFG_CENTER_LOGIC_OUTS_B15_4": { + "src_wire": "CFG_CENTER_ICAP0_O15", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O19->CFG_CENTER_LOGIC_OUTS_B19_4": { + "src_wire": "CFG_CENTER_ICAP0_O19", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX33_4->CFG_CENTER_ICAP0_I5": { + "src_wire": "CFG_CENTER_IMUX33_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O28->CFG_CENTER_LOGIC_OUTS_B13_14": { + "src_wire": "CFG_CENTER_ICAP1_O28", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_14", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX42_11->CFG_CENTER_ICAP1_RDWRB": { + "src_wire": "CFG_CENTER_IMUX42_11", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_RDWRB", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX41_4->CFG_CENTER_ICAP0_I13": { + "src_wire": "CFG_CENTER_IMUX41_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_ECCERRORSINGLE->CFG_CENTER_LOGIC_OUTS_B23_8": { + "src_wire": "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O31->CFG_CENTER_LOGIC_OUTS_B15_5": { + "src_wire": "CFG_CENTER_ICAP0_O31", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA9->CFG_CENTER_MID_USR_ACCESS_DATA9": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA9", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O6->CFG_CENTER_LOGIC_OUTS_B17_12": { + "src_wire": "CFG_CENTER_ICAP1_O6", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX32_5->CFG_CENTER_ICAP0_I21": { + "src_wire": "CFG_CENTER_IMUX32_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I21", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME7->CFG_CENTER_LOGIC_OUTS_B21_1": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME7", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD6->CFG_CENTER_LOGIC_OUTS_B17_8": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD6", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_UPDATE->CFG_CENTER_LOGIC_OUTS_B19_10": { + "src_wire": "CFG_CENTER_BSCAN4_UPDATE", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_10", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX41_5->CFG_CENTER_ICAP0_I30": { + "src_wire": "CFG_CENTER_IMUX41_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I30", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O23->CFG_CENTER_LOGIC_OUTS_B23_4": { + "src_wire": "CFG_CENTER_ICAP0_O23", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX33_3->CFG_CENTER_BSCAN1_TDO": { + "src_wire": "CFG_CENTER_IMUX33_3", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_BSCAN1_TDO", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA21->CFG_CENTER_LOGIC_OUTS_B16_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA21", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O9->CFG_CENTER_LOGIC_OUTS_B9_3": { + "src_wire": "CFG_CENTER_ICAP0_O9", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O22->CFG_CENTER_LOGIC_OUTS_B22_4": { + "src_wire": "CFG_CENTER_ICAP0_O22", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O25->CFG_CENTER_LOGIC_OUTS_B9_4": { + "src_wire": "CFG_CENTER_ICAP0_O25", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O26->CFG_CENTER_LOGIC_OUTS_B10_5": { + "src_wire": "CFG_CENTER_ICAP0_O26", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR3->CFG_CENTER_LOGIC_OUTS_B13_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR3", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_RUNTEST->CFG_CENTER_LOGIC_OUTS_B13_11": { + "src_wire": "CFG_CENTER_BSCAN3_RUNTEST", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O20->CFG_CENTER_LOGIC_OUTS_B19_13": { + "src_wire": "CFG_CENTER_ICAP1_O20", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TMS->CFG_CENTER_LOGIC_OUTS_B16_11": { + "src_wire": "CFG_CENTER_BSCAN4_TMS", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O1->CFG_CENTER_LOGIC_OUTS_B17_4": { + "src_wire": "CFG_CENTER_ICAP0_O1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_SEL->CFG_CENTER_LOGIC_OUTS_B14_2": { + "src_wire": "CFG_CENTER_BSCAN1_SEL", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX38_13->CFG_CENTER_ICAP1_I26": { + "src_wire": "CFG_CENTER_IMUX38_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I26", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O26->CFG_CENTER_LOGIC_OUTS_B11_14": { + "src_wire": "CFG_CENTER_ICAP1_O26", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_14", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX38_4->CFG_CENTER_ICAP0_I10": { + "src_wire": "CFG_CENTER_IMUX38_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I10", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O11->CFG_CENTER_LOGIC_OUTS_B22_12": { + "src_wire": "CFG_CENTER_ICAP1_O11", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX39_11->CFG_CENTER_BSCAN4_TDO": { + "src_wire": "CFG_CENTER_IMUX39_11", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_BSCAN4_TDO", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA22->CFG_CENTER_LOGIC_OUTS_B17_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA22", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_ECCERROR->CFG_CENTER_LOGIC_OUTS_B20_9": { + "src_wire": "CFG_CENTER_FRAME_ECC_ECCERROR", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O27->CFG_CENTER_LOGIC_OUTS_B11_5": { + "src_wire": "CFG_CENTER_ICAP0_O27", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_RESET->CFG_CENTER_LOGIC_OUTS_B19_2": { + "src_wire": "CFG_CENTER_BSCAN2_RESET", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX35_8->CFG_CENTER_DCIRESET_RST": { + "src_wire": "CFG_CENTER_IMUX35_8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_DCIRESET_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O9->CFG_CENTER_LOGIC_OUTS_B20_12": { + "src_wire": "CFG_CENTER_ICAP1_O9", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA11->CFG_CENTER_MID_USR_ACCESS_DATA11": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA11", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_STARTUP_EOS->CFG_CENTER_LOGIC_OUTS_B23_9": { + "src_wire": "CFG_CENTER_STARTUP_EOS", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX40_5->CFG_CENTER_ICAP0_I29": { + "src_wire": "CFG_CENTER_IMUX40_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I29", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA24->CFG_CENTER_LOGIC_OUTS_B19_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA24", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR20->CFG_CENTER_LOGIC_OUTS_B14_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR20", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX35_4->CFG_CENTER_ICAP0_I7": { + "src_wire": "CFG_CENTER_IMUX35_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TDI->CFG_CENTER_LOGIC_OUTS_B13_3": { + "src_wire": "CFG_CENTER_BSCAN2_TDI", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX43_8->CFG_CENTER_STARTUP_PACK": { + "src_wire": "CFG_CENTER_IMUX43_8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_PACK", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX30_13->CFG_CENTER_ICAP1_I18": { + "src_wire": "CFG_CENTER_IMUX30_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I18", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR25->CFG_CENTER_LOGIC_OUTS_B19_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR25", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX30_12->CFG_CENTER_ICAP1_I2": { + "src_wire": "CFG_CENTER_IMUX30_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_CFGCLK->CFG_CENTER_LOGIC_OUTS_B9_5": { + "src_wire": "CFG_CENTER_USR_ACCESS_CFGCLK", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_UPDATE->CFG_CENTER_LOGIC_OUTS_B17_2": { + "src_wire": "CFG_CENTER_BSCAN2_UPDATE", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX40_11->CFG_CENTER_ICAP0_CSIB": { + "src_wire": "CFG_CENTER_IMUX40_11", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_CSIB", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TCK->CFG_CENTER_LOGIC_OUTS_B15_3": { + "src_wire": "CFG_CENTER_BSCAN2_TCK", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX42_8->CFG_CENTER_STARTUP_USRDONEO": { + "src_wire": "CFG_CENTER_IMUX42_8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_USRDONEO", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX34_4->CFG_CENTER_ICAP0_I6": { + "src_wire": "CFG_CENTER_IMUX34_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O14->CFG_CENTER_LOGIC_OUTS_B14_4": { + "src_wire": "CFG_CENTER_ICAP0_O14", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O30->CFG_CENTER_LOGIC_OUTS_B15_14": { + "src_wire": "CFG_CENTER_ICAP1_O30", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_14", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TDI->CFG_CENTER_LOGIC_OUTS_B17_11": { + "src_wire": "CFG_CENTER_BSCAN3_TDI", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX42_13->CFG_CENTER_ICAP1_I30": { + "src_wire": "CFG_CENTER_IMUX42_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I30", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR16->CFG_CENTER_LOGIC_OUTS_B10_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR16", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX31_12->CFG_CENTER_ICAP1_I3": { + "src_wire": "CFG_CENTER_IMUX31_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_SEL->CFG_CENTER_LOGIC_OUTS_B15_2": { + "src_wire": "CFG_CENTER_BSCAN2_SEL", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX28_4->CFG_CENTER_ICAP0_I0": { + "src_wire": "CFG_CENTER_IMUX28_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR15->CFG_CENTER_LOGIC_OUTS_B9_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR15", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TCK->CFG_CENTER_LOGIC_OUTS_B19_11": { + "src_wire": "CFG_CENTER_BSCAN3_TCK", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA0->CFG_CENTER_LOGIC_OUTS_B11_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA0", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME1->CFG_CENTER_LOGIC_OUTS_B15_1": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA3->CFG_CENTER_MID_USR_ACCESS_DATA3": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA3", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX37_5->CFG_CENTER_ICAP0_I26": { + "src_wire": "CFG_CENTER_IMUX37_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I26", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_RESET->CFG_CENTER_LOGIC_OUTS_B21_10": { + "src_wire": "CFG_CENTER_BSCAN4_RESET", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_10", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_CLK1_5->CFG_CENTER_STARTUP_CLK": { + "src_wire": "CFG_CENTER_CLK1_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX36_5->CFG_CENTER_ICAP0_I25": { + "src_wire": "CFG_CENTER_IMUX36_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I25", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX37_4->CFG_CENTER_ICAP0_I9": { + "src_wire": "CFG_CENTER_IMUX37_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O13->CFG_CENTER_LOGIC_OUTS_B13_4": { + "src_wire": "CFG_CENTER_ICAP0_O13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TDI->CFG_CENTER_LOGIC_OUTS_B18_11": { + "src_wire": "CFG_CENTER_BSCAN4_TDI", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O6->CFG_CENTER_LOGIC_OUTS_B22_3": { + "src_wire": "CFG_CENTER_ICAP0_O6", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA15->CFG_CENTER_LOGIC_OUTS_B10_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA15", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX39_4->CFG_CENTER_ICAP0_I11": { + "src_wire": "CFG_CENTER_IMUX39_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I11", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX40_12->CFG_CENTER_ICAP1_I12": { + "src_wire": "CFG_CENTER_IMUX40_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA7->CFG_CENTER_MID_USR_ACCESS_DATA7": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA7", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA13->CFG_CENTER_MID_USR_ACCESS_DATA13": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O17->CFG_CENTER_LOGIC_OUTS_B17_5": { + "src_wire": "CFG_CENTER_ICAP0_O17", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX36_4->CFG_CENTER_ICAP0_I8": { + "src_wire": "CFG_CENTER_IMUX36_4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD2->CFG_CENTER_LOGIC_OUTS_B22_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD2", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR14->CFG_CENTER_LOGIC_OUTS_B8_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR14", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX38_8->CFG_CENTER_STARTUP_USRCCLKTS": { + "src_wire": "CFG_CENTER_IMUX38_8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_USRCCLKTS", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O0->CFG_CENTER_LOGIC_OUTS_B16_4": { + "src_wire": "CFG_CENTER_ICAP0_O0", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA10->CFG_CENTER_MID_USR_ACCESS_DATA10": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA10", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA10", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA5->CFG_CENTER_MID_USR_ACCESS_DATA5": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX38_11->CFG_CENTER_BSCAN3_TDO": { + "src_wire": "CFG_CENTER_IMUX38_11", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_BSCAN3_TDO", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX38_12->CFG_CENTER_ICAP1_I10": { + "src_wire": "CFG_CENTER_IMUX38_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I10", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR2->CFG_CENTER_LOGIC_OUTS_B12_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR2", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME3->CFG_CENTER_LOGIC_OUTS_B17_1": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME3", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_CLK1_8->CFG_CENTER_MID_DNA_PORT_CLK": { + "src_wire": "CFG_CENTER_CLK1_8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_DNA_PORT_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME0->CFG_CENTER_LOGIC_OUTS_B14_1": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME0", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O14->CFG_CENTER_LOGIC_OUTS_B13_13": { + "src_wire": "CFG_CENTER_ICAP1_O14", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX34_3->CFG_CENTER_BSCAN2_TDO": { + "src_wire": "CFG_CENTER_IMUX34_3", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_BSCAN2_TDO", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT3->CFG_CENTER_LOGIC_OUTS_B21_8": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT3", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR10->CFG_CENTER_LOGIC_OUTS_B20_6": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR10", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME9->CFG_CENTER_LOGIC_OUTS_B23_1": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME9", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_1", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA18->CFG_CENTER_LOGIC_OUTS_B13_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA18", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD3->CFG_CENTER_LOGIC_OUTS_B23_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD3", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX41_13->CFG_CENTER_ICAP1_I29": { + "src_wire": "CFG_CENTER_IMUX41_13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I29", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA20->CFG_CENTER_LOGIC_OUTS_B15_0": { + "src_wire": "CFG_CENTER_USR_ACCESS_DATA20", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_0", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O4->CFG_CENTER_LOGIC_OUTS_B20_3": { + "src_wire": "CFG_CENTER_ICAP0_O4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_3", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O17->CFG_CENTER_LOGIC_OUTS_B16_13": { + "src_wire": "CFG_CENTER_ICAP1_O17", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_13", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME10->CFG_CENTER_LOGIC_OUTS_B10_2": { + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME10", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_2", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR24->CFG_CENTER_LOGIC_OUTS_B18_7": { + "src_wire": "CFG_CENTER_FRAME_ECC_FAR24", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX36_12->CFG_CENTER_ICAP1_I8": { + "src_wire": "CFG_CENTER_IMUX36_12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O8->CFG_CENTER_LOGIC_OUTS_B19_12": { + "src_wire": "CFG_CENTER_ICAP1_O8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_12", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX37_8->CFG_CENTER_CAPTURE_CAP": { + "src_wire": "CFG_CENTER_IMUX37_8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_CAPTURE_CAP", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CFG_CENTER_TOP.json b/kintex7/tile_type_CFG_CENTER_TOP.json new file mode 100644 index 0000000..d236e41 --- /dev/null +++ b/kintex7/tile_type_CFG_CENTER_TOP.json @@ -0,0 +1,2590 @@ +{ + "tile_type": "CFG_CENTER_TOP", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "DNA_PORT", + "type": "DNA_PORT", + "site_pins": { + "DOUT": "CFG_CENTER_DNA_PORT_DOUT", + "READ": "CFG_CENTER_DNA_PORT_READ", + "SHIFT": "CFG_CENTER_DNA_PORT_SHIFT", + "DIN": "CFG_CENTER_DNA_PORT_DIN", + "CLK": "CFG_CENTER_DNA_PORT_CLK" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "EFUSE_USR", + "type": "EFUSE_USR", + "site_pins": { + "EFUSEUSR13": "CFG_CENTER_EFUSE_USR_EFUSEUSR13", + "EFUSEUSR30": "CFG_CENTER_EFUSE_USR_EFUSEUSR30", + "EFUSEUSR0": "CFG_CENTER_EFUSE_USR_EFUSEUSR0", + "EFUSEUSR8": "CFG_CENTER_EFUSE_USR_EFUSEUSR8", + "EFUSEUSR4": "CFG_CENTER_EFUSE_USR_EFUSEUSR4", + "EFUSEUSR25": "CFG_CENTER_EFUSE_USR_EFUSEUSR25", + "EFUSEUSR21": "CFG_CENTER_EFUSE_USR_EFUSEUSR21", + "EFUSEUSR22": "CFG_CENTER_EFUSE_USR_EFUSEUSR22", + "EFUSEUSR11": "CFG_CENTER_EFUSE_USR_EFUSEUSR11", + "EFUSEUSR15": "CFG_CENTER_EFUSE_USR_EFUSEUSR15", + "EFUSEUSR9": "CFG_CENTER_EFUSE_USR_EFUSEUSR9", + "EFUSEUSR2": "CFG_CENTER_EFUSE_USR_EFUSEUSR2", + "EFUSEUSR18": "CFG_CENTER_EFUSE_USR_EFUSEUSR18", + "EFUSEUSR3": "CFG_CENTER_EFUSE_USR_EFUSEUSR3", + "EFUSEUSR12": "CFG_CENTER_EFUSE_USR_EFUSEUSR12", + "EFUSEUSR6": "CFG_CENTER_EFUSE_USR_EFUSEUSR6", + "EFUSEUSR23": "CFG_CENTER_EFUSE_USR_EFUSEUSR23", + "EFUSEUSR17": "CFG_CENTER_EFUSE_USR_EFUSEUSR17", + "EFUSEUSR31": "CFG_CENTER_EFUSE_USR_EFUSEUSR31", + "EFUSEUSR19": "CFG_CENTER_EFUSE_USR_EFUSEUSR19", + "EFUSEUSR27": "CFG_CENTER_EFUSE_USR_EFUSEUSR27", + "EFUSEUSR28": "CFG_CENTER_EFUSE_USR_EFUSEUSR28", + "EFUSEUSR7": "CFG_CENTER_EFUSE_USR_EFUSEUSR7", + "EFUSEUSR29": "CFG_CENTER_EFUSE_USR_EFUSEUSR29", + "EFUSEUSR14": "CFG_CENTER_EFUSE_USR_EFUSEUSR14", + "EFUSEUSR1": "CFG_CENTER_EFUSE_USR_EFUSEUSR1", + "EFUSEUSR26": "CFG_CENTER_EFUSE_USR_EFUSEUSR26", + "EFUSEUSR24": "CFG_CENTER_EFUSE_USR_EFUSEUSR24", + "EFUSEUSR16": "CFG_CENTER_EFUSE_USR_EFUSEUSR16", + "EFUSEUSR10": "CFG_CENTER_EFUSE_USR_EFUSEUSR10", + "EFUSEUSR20": "CFG_CENTER_EFUSE_USR_EFUSEUSR20", + "EFUSEUSR5": "CFG_CENTER_EFUSE_USR_EFUSEUSR5" + }, + "x_coord": 0 + } + ], + "wires": [ + "CFG_CENTER_EL1BEG2_0", + "CFG_CENTER_SE4BEG2_9", + "CFG_CENTER_NW4END3_8", + "CFG_CENTER_SW2A2_8", + "CFG_CENTER_EE2BEG3_5", + "CFG_CENTER_EE4A0_3", + "CFG_CENTER_LH1_0", + "CFG_CENTER_BLOCK_OUTS_B3_2", + "CFG_CENTER_LOGIC_OUTS_B18_2", + "CFG_CENTER_DNA_PORT_CLK", + "CFG_CENTER_IMUX16_4", + "CFG_CENTER_EE4C2_4", + "CFG_CENTER_SW4END0_9", + "CFG_CENTER_WW4END1_5", + "CFG_CENTER_EE2BEG3_7", + "CFG_CENTER_LOGIC_OUTS_B2_5", + "CFG_CENTER_EL1BEG1_0", + "CFG_CENTER_IMUX37_9", + "CFG_CENTER_BYP4_2", + "CFG_CENTER_LOGIC_OUTS_B8_1", + "CFG_CENTER_EE4A0_9", + "CFG_CENTER_IMUX11_8", + "CFG_CENTER_IMUX14_4", + "CFG_CENTER_EE4B2_3", + "CFG_CENTER_LH3_0", + "CFG_CENTER_BLOCK_OUTS_B1_3", + "CFG_CENTER_IMUX8_9", + "CFG_CENTER_IMUX23_2", + "CFG_CENTER_WW4END1_1", + "CFG_CENTER_SE4C0_4", + "CFG_CENTER_CTRL1_1", + "CFG_CENTER_IMUX18_1", + "CFG_CENTER_LOGIC_OUTS_B11_9", + "CFG_CENTER_IMUX38_6", + "CFG_CENTER_SW2A2_9", + "CFG_CENTER_EFUSE_USR_EFUSEUSR8", + "CFG_CENTER_LH6_1", + "CFG_CENTER_LH6_3", + "CFG_CENTER_LOGIC_OUTS_B18_5", + "CFG_CENTER_IMUX9_5", + "CFG_CENTER_LOGIC_OUTS_B2_9", + "CFG_CENTER_WW4A1_9", + "CFG_CENTER_SE2A0_4", + "CFG_CENTER_SW4END3_4", + "CFG_CENTER_ER1BEG0_4", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA28", + "CFG_CENTER_BYP3_3", + "CFG_CENTER_IMUX38_1", + "CFG_CENTER_IMUX43_4", + "CFG_CENTER_LOGIC_OUTS_B10_2", + "CFG_CENTER_IMUX30_2", + "CFG_CENTER_IMUX6_2", + "CFG_CENTER_IMUX25_7", + "CFG_CENTER_WW2A0_7", + "CFG_CENTER_SE2A2_7", + "CFG_CENTER_FAN2_9", + "CFG_CENTER_IMUX5_1", + "CFG_CENTER_WL1END0_5", + "CFG_CENTER_EE4A2_8", + "CFG_CENTER_NE4C3_8", + "CFG_CENTER_IMUX23_9", + "CFG_CENTER_WW4B2_4", + "CFG_CENTER_IMUX32_5", + "CFG_CENTER_LH10_8", + "CFG_CENTER_LOGIC_OUTS_B5_5", + "CFG_CENTER_LOGIC_OUTS_B2_7", + "CFG_CENTER_LOGIC_OUTS_B4_8", + "CFG_CENTER_WW4B1_2", + "CFG_CENTER_LH1_7", + "CFG_CENTER_NE4C0_8", + "CFG_CENTER_EFUSE_USR_EFUSEUSR24", + "CFG_CENTER_IMUX2_7", + "CFG_CENTER_IMUX24_3", + "CFG_CENTER_LOGIC_OUTS_B1_5", + "CFG_CENTER_EE4C3_4", + "CFG_CENTER_FAN7_6", + "CFG_CENTER_NE2A1_8", + "CFG_CENTER_WW4C3_3", + "CFG_CENTER_EE4A3_2", + "CFG_CENTER_NE2A2_5", + "CFG_CENTER_LOGIC_OUTS_B14_4", + "CFG_CENTER_LOGIC_OUTS_B14_2", + "CFG_CENTER_WW2A3_5", + "CFG_CENTER_EE4C2_8", + "CFG_CENTER_WW2A2_1", + "CFG_CENTER_EE2BEG0_6", + "CFG_CENTER_IMUX9_9", + "CFG_CENTER_WW4B3_1", + "CFG_CENTER_ER1BEG2_8", + "CFG_CENTER_LOGIC_OUTS_B1_7", + "CFG_CENTER_NE2A0_9", + "CFG_CENTER_LOGIC_OUTS_B7_1", + "CFG_CENTER_IMUX31_5", + "CFG_CENTER_BYP7_3", + "CFG_CENTER_IMUX15_8", + "CFG_CENTER_LOGIC_OUTS_B8_2", + "CFG_CENTER_WR1END1_9", + "CFG_CENTER_IMUX30_5", + "CFG_CENTER_WW4C0_5", + "CFG_CENTER_LOGIC_OUTS_B11_0", + "CFG_CENTER_WW4B1_5", + "CFG_CENTER_SE4BEG2_1", + "CFG_CENTER_IMUX11_0", + "CFG_CENTER_EL1BEG1_3", + "CFG_CENTER_WR1END1_0", + "CFG_CENTER_EE4BEG2_8", + "CFG_CENTER_IMUX41_0", + "CFG_CENTER_BLOCK_OUTS_B2_6", + "CFG_CENTER_NW4A0_2", + "CFG_CENTER_LOGIC_OUTS_B4_4", + "CFG_CENTER_SW2A1_8", + "CFG_CENTER_SW4A0_9", + "CFG_CENTER_SE4BEG2_0", + "CFG_CENTER_LOGIC_OUTS_B21_9", + "CFG_CENTER_SW4END2_3", + "CFG_CENTER_WW2A0_6", + "CFG_CENTER_IMUX40_6", + "CFG_CENTER_LOGIC_OUTS_B14_1", + "CFG_CENTER_NW2A0_5", + "CFG_CENTER_BLOCK_OUTS_B2_0", + "CFG_CENTER_LOGIC_OUTS_B4_3", + "CFG_CENTER_IMUX2_2", + "CFG_CENTER_IMUX8_3", + "CFG_CENTER_SW4END0_8", + "CFG_CENTER_IMUX5_9", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA23", + "CFG_CENTER_IMUX26_3", + "CFG_CENTER_NE4C3_6", + "CFG_CENTER_SE4C1_5", + "CFG_CENTER_EE2A2_7", + "CFG_CENTER_LOGIC_OUTS_B0_0", + "CFG_CENTER_LH4_8", + "CFG_CENTER_LH1_2", + "CFG_CENTER_IMUX18_6", + "CFG_CENTER_LH5_7", + "CFG_CENTER_IMUX30_9", + "CFG_CENTER_IMUX14_0", + "CFG_CENTER_IMUX27_1", + "CFG_CENTER_EE2BEG3_1", + "CFG_CENTER_WR1END2_4", + "CFG_CENTER_WL1END2_1", + "CFG_CENTER_IMUX47_4", + "CFG_CENTER_IMUX40_4", + "CFG_CENTER_NE2A3_8", + "CFG_CENTER_FAN2_7", + "CFG_CENTER_IMUX32_3", + "CFG_CENTER_NE2A2_0", + "CFG_CENTER_IMUX42_9", + "CFG_CENTER_LOGIC_OUTS_B0_6", + "CFG_CENTER_NW4END3_5", + "CFG_CENTER_LOGIC_OUTS_B13_0", + "CFG_CENTER_LOGIC_OUTS_B11_5", + "CFG_CENTER_WW4A3_6", + "CFG_CENTER_SW4A2_6", + "CFG_CENTER_LH7_7", + "CFG_CENTER_LOGIC_OUTS_B21_8", + "CFG_CENTER_EE2A1_0", + "CFG_CENTER_LOGIC_OUTS_B14_7", + "CFG_CENTER_LOGIC_OUTS_B10_1", + "CFG_CENTER_LOGIC_OUTS_B7_5", + "CFG_CENTER_ER1BEG1_9", + "CFG_CENTER_SE2A2_1", + "CFG_CENTER_ER1BEG1_6", + "CFG_CENTER_IMUX25_3", + "CFG_CENTER_FAN4_1", + "CFG_CENTER_IMUX47_7", + "CFG_CENTER_SE4BEG2_6", + "CFG_CENTER_EE4BEG2_0", + "CFG_CENTER_BYP5_5", + "CFG_CENTER_SW4A1_2", + "CFG_CENTER_EE2BEG1_7", + "CFG_CENTER_IMUX32_2", + "CFG_CENTER_NW2A1_8", + "CFG_CENTER_SE4BEG2_3", + "CFG_CENTER_WL1END0_6", + "CFG_CENTER_LOGIC_OUTS_B18_3", + "CFG_CENTER_WL1END1_3", + "CFG_CENTER_EL1BEG3_0", + "CFG_CENTER_SE4BEG1_4", + "CFG_CENTER_IMUX39_0", + "CFG_CENTER_IMUX18_9", + "CFG_CENTER_SE4C2_7", + "CFG_CENTER_NW4A1_9", + "CFG_CENTER_IMUX15_5", + "CFG_CENTER_CTRL1_5", + "CFG_CENTER_LOGIC_OUTS_B6_5", + "CFG_CENTER_WW4END2_7", + "CFG_CENTER_IMUX10_6", + "CFG_CENTER_BYP2_8", + "CFG_CENTER_IMUX19_5", + "CFG_CENTER_LOGIC_OUTS_B15_0", + "CFG_CENTER_LH4_1", + "CFG_CENTER_LOGIC_OUTS_B7_7", + "CFG_CENTER_WW4C3_0", + "CFG_CENTER_EE4B0_8", + "CFG_CENTER_LH4_3", + "CFG_CENTER_SE4BEG3_9", + "CFG_CENTER_IMUX35_4", + "CFG_CENTER_SE4C3_6", + "CFG_CENTER_EE4C3_0", + "CFG_CENTER_IMUX12_4", + "CFG_CENTER_EFUSE_USR_EFUSEUSR1", + "CFG_CENTER_WW4A1_0", + "CFG_CENTER_BLOCK_OUTS_B0_4", + "CFG_CENTER_LOGIC_OUTS_B9_3", + "CFG_CENTER_IMUX16_1", + "CFG_CENTER_EE4BEG3_6", + "CFG_CENTER_WL1END2_5", + "CFG_CENTER_BLOCK_OUTS_B1_5", + "CFG_CENTER_LOGIC_OUTS_B7_6", + "CFG_CENTER_SE4BEG3_1", + "CFG_CENTER_WW2END3_3", + "CFG_CENTER_NW4A1_7", + "CFG_CENTER_BYP1_4", + "CFG_CENTER_LOGIC_OUTS_B8_6", + "CFG_CENTER_SW4END3_8", + "CFG_CENTER_IMUX10_1", + "CFG_CENTER_EE4C3_7", + "CFG_CENTER_LOGIC_OUTS_B10_7", + "CFG_CENTER_SW2A3_5", + "CFG_CENTER_IMUX36_0", + "CFG_CENTER_IMUX22_1", + "CFG_CENTER_IMUX25_9", + "CFG_CENTER_CTRL1_8", + "CFG_CENTER_BYP2_2", + "CFG_CENTER_IMUX39_3", + "CFG_CENTER_LOGIC_OUTS_B6_1", + "CFG_CENTER_SW4A3_4", + "CFG_CENTER_WW2A0_9", + "CFG_CENTER_WW4A1_5", + "CFG_CENTER_LOGIC_OUTS_B20_1", + "CFG_CENTER_SW4END2_8", + "CFG_CENTER_WW4C1_8", + "CFG_CENTER_BYP4_3", + "CFG_CENTER_IMUX3_0", + "CFG_CENTER_NW4A2_9", + "CFG_CENTER_LOGIC_OUTS_B20_7", + "CFG_CENTER_SE2A3_1", + "CFG_CENTER_SW4END3_9", + "CFG_CENTER_WL1END0_9", + "CFG_CENTER_EE2A3_5", + "CFG_CENTER_WW2A3_6", + "CFG_CENTER_EL1BEG1_9", + "CFG_CENTER_IMUX28_2", + "CFG_CENTER_LOGIC_OUTS_B3_7", + "CFG_CENTER_IMUX6_9", + "CFG_CENTER_BYP4_5", + "CFG_CENTER_CTRL1_2", + "CFG_CENTER_IMUX33_2", + "CFG_CENTER_EL1BEG1_4", + "CFG_CENTER_BYP3_8", + "CFG_CENTER_NE4C2_8", + "CFG_CENTER_WW2END0_7", + "CFG_CENTER_WW2A0_5", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA26", + "CFG_CENTER_SW2A1_0", + "CFG_CENTER_IMUX13_2", + "CFG_CENTER_IMUX4_2", + "CFG_CENTER_LH7_0", + "CFG_CENTER_LH10_3", + "CFG_CENTER_IMUX24_4", + "CFG_CENTER_FAN2_3", + "CFG_CENTER_LOGIC_OUTS_B13_7", + "CFG_CENTER_LOGIC_OUTS_B5_8", + "CFG_CENTER_IMUX10_0", + "CFG_CENTER_EE4BEG1_0", + "CFG_CENTER_EE2A0_9", + "CFG_CENTER_BLOCK_OUTS_B1_8", + "CFG_CENTER_LOGIC_OUTS_B21_4", + "CFG_CENTER_IMUX3_5", + "CFG_CENTER_IMUX12_1", + "CFG_CENTER_WW4C1_2", + "CFG_CENTER_WR1END0_6", + "CFG_CENTER_WW4END3_0", + "CFG_CENTER_SW2A0_6", + "CFG_CENTER_LOGIC_OUTS_B6_0", + "CFG_CENTER_SE2A1_4", + "CFG_CENTER_FAN2_8", + "CFG_CENTER_SE4C2_5", + "CFG_CENTER_FAN5_8", + "CFG_CENTER_BYP5_7", + "CFG_CENTER_IMUX45_2", + "CFG_CENTER_IMUX14_5", + "CFG_CENTER_IMUX46_4", + "CFG_CENTER_LOGIC_OUTS_B6_9", + "CFG_CENTER_SE4BEG1_6", + "CFG_CENTER_SW4END3_0", + "CFG_CENTER_BYP6_2", + "CFG_CENTER_SE4C0_1", + "CFG_CENTER_SW2A3_6", + "CFG_CENTER_EFUSE_USR_EFUSEUSR4", + "CFG_CENTER_CLK1_4", + "CFG_CENTER_WW2A2_9", + "CFG_CENTER_LOGIC_OUTS_B23_2", + "CFG_CENTER_EFUSE_USR_EFUSEUSR31", + "CFG_CENTER_SE4C3_3", + "CFG_CENTER_IMUX32_6", + "CFG_CENTER_IMUX36_1", + "CFG_CENTER_LOGIC_OUTS_B13_3", + "CFG_CENTER_IMUX30_6", + "CFG_CENTER_NW4END3_4", + "CFG_CENTER_SW2A0_1", + "CFG_CENTER_NW4END2_2", + "CFG_CENTER_EE4BEG0_3", + "CFG_CENTER_WW4END0_8", + "CFG_CENTER_WW4A0_7", + "CFG_CENTER_LOGIC_OUTS_B2_0", + "CFG_CENTER_SW2A0_8", + "CFG_CENTER_SE2A2_5", + "CFG_CENTER_FAN5_5", + "CFG_CENTER_NW4A0_5", + "CFG_CENTER_IMUX17_9", + "CFG_CENTER_NE4C2_3", + "CFG_CENTER_EFUSE_USR_EFUSEUSR30", + "CFG_CENTER_WW4B3_7", + "CFG_CENTER_IMUX37_5", + "CFG_CENTER_WR1END3_3", + "CFG_CENTER_IMUX27_2", + "CFG_CENTER_EE4A0_2", + "CFG_CENTER_LOGIC_OUTS_B17_6", + "CFG_CENTER_NW4A3_0", + "CFG_CENTER_IMUX45_9", + "CFG_CENTER_IMUX17_7", + "CFG_CENTER_WW2END3_7", + "CFG_CENTER_LOGIC_OUTS_B6_6", + "CFG_CENTER_LOGIC_OUTS_B14_9", + "CFG_CENTER_NE4C2_0", + "CFG_CENTER_IMUX5_8", + "CFG_CENTER_EE2BEG3_4", + "CFG_CENTER_IMUX18_4", + "CFG_CENTER_LOGIC_OUTS_B20_9", + "CFG_CENTER_LOGIC_OUTS_B8_5", + "CFG_CENTER_SW2A2_0", + "CFG_CENTER_NE4C2_6", + "CFG_CENTER_EE4BEG1_5", + "CFG_CENTER_CLK1_5", + "CFG_CENTER_IMUX32_7", + "CFG_CENTER_EE2BEG1_5", + "CFG_CENTER_EE4C3_8", + "CFG_CENTER_FAN1_6", + "CFG_CENTER_WL1END0_7", + "CFG_CENTER_WW4END0_3", + "CFG_CENTER_EE2BEG1_0", + "CFG_CENTER_LH5_1", + "CFG_CENTER_IMUX16_8", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA18", + "CFG_CENTER_NW4END1_0", + "CFG_CENTER_SW2A2_1", + "CFG_CENTER_IMUX32_0", + "CFG_CENTER_WR1END0_1", + "CFG_CENTER_IMUX11_3", + "CFG_CENTER_LOGIC_OUTS_B12_1", + "CFG_CENTER_LOGIC_OUTS_B22_9", + "CFG_CENTER_SE4C0_2", + "CFG_CENTER_LOGIC_OUTS_B21_1", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA22", + "CFG_CENTER_NE2A0_6", + "CFG_CENTER_WW4B1_1", + "CFG_CENTER_WW4A1_7", + "CFG_CENTER_IMUX5_5", + "CFG_CENTER_NW2A1_3", + "CFG_CENTER_IMUX34_0", + "CFG_CENTER_IMUX23_4", + "CFG_CENTER_EE2A0_4", + "CFG_CENTER_SE4C0_8", + "CFG_CENTER_BYP6_9", + "CFG_CENTER_WR1END0_8", + "CFG_CENTER_NE2A1_5", + "CFG_CENTER_WW4A0_0", + "CFG_CENTER_NW4END3_2", + "CFG_CENTER_WW4A0_5", + "CFG_CENTER_NE4C0_0", + "CFG_CENTER_SW2A1_5", + "CFG_CENTER_LH4_0", + "CFG_CENTER_IMUX10_7", + "CFG_CENTER_SW4A3_2", + "CFG_CENTER_WW2END1_7", + "CFG_CENTER_EE4BEG1_6", + "CFG_CENTER_WR1END3_2", + "CFG_CENTER_NE4BEG1_2", + "CFG_CENTER_LH9_9", + "CFG_CENTER_IMUX1_7", + "CFG_CENTER_LOGIC_OUTS_B15_3", + "CFG_CENTER_SE4C1_3", + "CFG_CENTER_LOGIC_OUTS_B9_5", + "CFG_CENTER_IMUX27_3", + "CFG_CENTER_LOGIC_OUTS_B23_3", + "CFG_CENTER_IMUX38_3", + "CFG_CENTER_SE2A1_1", + "CFG_CENTER_WW4B3_5", + "CFG_CENTER_EE4BEG1_4", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA17", + "CFG_CENTER_SE4BEG3_4", + "CFG_CENTER_IMUX2_5", + "CFG_CENTER_SW4END0_6", + "CFG_CENTER_CLK0_0", + "CFG_CENTER_LOGIC_OUTS_B12_7", + "CFG_CENTER_SW4END2_0", + "CFG_CENTER_NE4BEG0_7", + "CFG_CENTER_LH11_5", + "CFG_CENTER_EE4A3_1", + "CFG_CENTER_WL1END3_3", + "CFG_CENTER_WW2A3_4", + "CFG_CENTER_WL1END2_4", + "CFG_CENTER_BLOCK_OUTS_B0_9", + "CFG_CENTER_WW2A2_7", + "CFG_CENTER_EE4C1_5", + "CFG_CENTER_NW4END0_4", + "CFG_CENTER_EE2BEG2_5", + "CFG_CENTER_IMUX34_6", + "CFG_CENTER_FAN4_3", + "CFG_CENTER_LH1_3", + "CFG_CENTER_LH2_2", + "CFG_CENTER_NW4A2_3", + "CFG_CENTER_IMUX24_6", + "CFG_CENTER_SE4BEG2_8", + "CFG_CENTER_IMUX24_1", + "CFG_CENTER_EE4BEG2_7", + "CFG_CENTER_IMUX10_5", + "CFG_CENTER_LH11_2", + "CFG_CENTER_EE4BEG3_8", + "CFG_CENTER_WR1END1_2", + "CFG_CENTER_CLK1_2", + "CFG_CENTER_SE4C2_2", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA24", + "CFG_CENTER_NW4END2_6", + "CFG_CENTER_LOGIC_OUTS_B12_6", + "CFG_CENTER_FAN0_1", + "CFG_CENTER_IMUX20_2", + "CFG_CENTER_LH9_1", + "CFG_CENTER_SE4C0_3", + "CFG_CENTER_WW4A2_4", + "CFG_CENTER_BYP1_7", + "CFG_CENTER_SW4A2_7", + "CFG_CENTER_WW2END0_5", + "CFG_CENTER_IMUX43_6", + "CFG_CENTER_BLOCK_OUTS_B1_2", + "CFG_CENTER_EE4B3_4", + "CFG_CENTER_IMUX45_6", + "CFG_CENTER_NW2A1_9", + "CFG_CENTER_EE4B2_5", + "CFG_CENTER_EE2A3_4", + "CFG_CENTER_WW4END0_6", + "CFG_CENTER_SE2A2_6", + "CFG_CENTER_LOGIC_OUTS_B17_9", + "CFG_CENTER_LOGIC_OUTS_B13_5", + "CFG_CENTER_IMUX46_2", + "CFG_CENTER_EE2BEG1_2", + "CFG_CENTER_IMUX23_5", + "CFG_CENTER_WW4END2_8", + "CFG_CENTER_EE2A3_1", + "CFG_CENTER_NW4A2_6", + "CFG_CENTER_SE4BEG0_8", + "CFG_CENTER_EE2A2_8", + "CFG_CENTER_NW4A3_3", + "CFG_CENTER_LH1_4", + "CFG_CENTER_NW4END2_4", + "CFG_CENTER_SE4C2_8", + "CFG_CENTER_LOGIC_OUTS_B10_8", + "CFG_CENTER_LOGIC_OUTS_B5_6", + "CFG_CENTER_BYP1_3", + "CFG_CENTER_LOGIC_OUTS_B19_7", + "CFG_CENTER_WW4END3_9", + "CFG_CENTER_WW4B1_9", + "CFG_CENTER_IMUX22_3", + "CFG_CENTER_WW2END2_0", + "CFG_CENTER_WW4B1_3", + "CFG_CENTER_SW4A3_3", + "CFG_CENTER_NE4BEG2_7", + "CFG_CENTER_LOGIC_OUTS_B15_9", + "CFG_CENTER_SE4C2_0", + "CFG_CENTER_LOGIC_OUTS_B3_6", + "CFG_CENTER_IMUX44_1", + "CFG_CENTER_EE4B3_7", + "CFG_CENTER_EE4B0_6", + "CFG_CENTER_EE2A1_1", + "CFG_CENTER_NW4A1_8", + "CFG_CENTER_LH4_9", + "CFG_CENTER_WW4END3_6", + "CFG_CENTER_WW4B0_8", + "CFG_CENTER_SW4END1_7", + "CFG_CENTER_WL1END1_0", + "CFG_CENTER_BYP0_9", + "CFG_CENTER_NE4C0_4", + "CFG_CENTER_WR1END2_1", + "CFG_CENTER_NW4A1_1", + "CFG_CENTER_IMUX10_9", + "CFG_CENTER_BYP5_3", + "CFG_CENTER_EE2BEG0_1", + "CFG_CENTER_EE2BEG3_6", + "CFG_CENTER_LOGIC_OUTS_B14_6", + "CFG_CENTER_FAN4_7", + "CFG_CENTER_EL1BEG3_7", + "CFG_CENTER_IMUX30_3", + "CFG_CENTER_FAN4_6", + "CFG_CENTER_BYP1_6", + "CFG_CENTER_IMUX2_1", + "CFG_CENTER_EE4BEG1_7", + "CFG_CENTER_EFUSE_USR_EFUSEUSR18", + "CFG_CENTER_IMUX41_4", + "CFG_CENTER_IMUX14_3", + "CFG_CENTER_BYP0_4", + "CFG_CENTER_IMUX14_6", + "CFG_CENTER_EE4C2_0", + "CFG_CENTER_IMUX39_1", + "CFG_CENTER_FAN6_0", + "CFG_CENTER_EL1BEG3_2", + "CFG_CENTER_WL1END1_8", + "CFG_CENTER_LH3_2", + "CFG_CENTER_WW2A0_4", + "CFG_CENTER_EE4BEG3_3", + "CFG_CENTER_WR1END3_0", + "CFG_CENTER_NE2A3_1", + "CFG_CENTER_SE4BEG3_3", + "CFG_CENTER_WW4A2_6", + "CFG_CENTER_WW4B3_8", + "CFG_CENTER_CTRL0_3", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA30", + "CFG_CENTER_WW4C0_2", + "CFG_CENTER_BYP3_5", + "CFG_CENTER_EE4B2_7", + "CFG_CENTER_BYP0_6", + "CFG_CENTER_LOGIC_OUTS_B1_6", + "CFG_CENTER_WW2A1_0", + "CFG_CENTER_EL1BEG1_2", + "CFG_CENTER_SW2A3_9", + "CFG_CENTER_WW4B0_1", + "CFG_CENTER_IMUX36_7", + "CFG_CENTER_WW2A3_8", + "CFG_CENTER_BLOCK_OUTS_B3_6", + "CFG_CENTER_WW4A1_4", + "CFG_CENTER_NE4BEG3_9", + "CFG_CENTER_LH11_9", + "CFG_CENTER_LOGIC_OUTS_B20_0", + "CFG_CENTER_ER1BEG2_1", + "CFG_CENTER_LOGIC_OUTS_B18_7", + "CFG_CENTER_IMUX20_7", + "CFG_CENTER_EE4BEG3_5", + "CFG_CENTER_LOGIC_OUTS_B3_9", + "CFG_CENTER_WW4END2_2", + "CFG_CENTER_BYP3_9", + "CFG_CENTER_BLOCK_OUTS_B2_9", + "CFG_CENTER_BYP3_0", + "CFG_CENTER_NE2A2_3", + "CFG_CENTER_NE4BEG3_0", + "CFG_CENTER_NE4BEG0_6", + "CFG_CENTER_WW4A1_8", + "CFG_CENTER_EE4A2_0", + "CFG_CENTER_SE4C1_7", + "CFG_CENTER_IMUX45_1", + "CFG_CENTER_WW4A1_6", + "CFG_CENTER_IMUX45_7", + "CFG_CENTER_IMUX1_5", + "CFG_CENTER_BYP6_3", + "CFG_CENTER_EL1BEG1_7", + "CFG_CENTER_IMUX44_7", + "CFG_CENTER_NW4END0_7", + "CFG_CENTER_NE4C1_9", + "CFG_CENTER_IMUX41_6", + "CFG_CENTER_LH8_5", + "CFG_CENTER_FAN3_1", + "CFG_CENTER_LH6_5", + "CFG_CENTER_EE4C0_9", + "CFG_CENTER_LH5_8", + "CFG_CENTER_IMUX38_0", + "CFG_CENTER_IMUX18_2", + "CFG_CENTER_SE4BEG0_9", + "CFG_CENTER_WW4B0_4", + "CFG_CENTER_EE2A3_7", + "CFG_CENTER_NE4BEG2_9", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA11", + "CFG_CENTER_IMUX8_5", + "CFG_CENTER_EE4B3_0", + "CFG_CENTER_SE4C0_5", + "CFG_CENTER_LOGIC_OUTS_B7_3", + "CFG_CENTER_EE2A0_2", + "CFG_CENTER_WW2END3_9", + "CFG_CENTER_WR1END2_2", + "CFG_CENTER_EE4A1_3", + "CFG_CENTER_WW4B2_8", + "CFG_CENTER_LOGIC_OUTS_B1_1", + "CFG_CENTER_EE4BEG3_1", + "CFG_CENTER_SW4A2_1", + "CFG_CENTER_IMUX41_2", + "CFG_CENTER_LOGIC_OUTS_B22_7", + "CFG_CENTER_IMUX42_0", + "CFG_CENTER_IMUX8_2", + "CFG_CENTER_WW4C3_7", + "CFG_CENTER_WL1END0_3", + "CFG_CENTER_LH10_2", + "CFG_CENTER_SE4C3_9", + "CFG_CENTER_WR1END2_9", + "CFG_CENTER_WW2A2_2", + "CFG_CENTER_WW4C2_0", + "CFG_CENTER_LOGIC_OUTS_B19_2", + "CFG_CENTER_EL1BEG0_3", + "CFG_CENTER_EE4B1_3", + "CFG_CENTER_EE4B1_9", + "CFG_CENTER_WR1END2_6", + "CFG_CENTER_IMUX11_4", + "CFG_CENTER_LOGIC_OUTS_B6_8", + "CFG_CENTER_IMUX20_6", + "CFG_CENTER_EE4A1_1", + "CFG_CENTER_NE4C2_9", + "CFG_CENTER_EL1BEG0_5", + "CFG_CENTER_EE4C3_6", + "CFG_CENTER_SW2A2_7", + "CFG_CENTER_IMUX9_4", + "CFG_CENTER_EE4BEG0_6", + "CFG_CENTER_LOGIC_OUTS_B15_5", + "CFG_CENTER_EE4B0_7", + "CFG_CENTER_BYP2_7", + "CFG_CENTER_IMUX24_5", + "CFG_CENTER_LH6_0", + "CFG_CENTER_WL1END3_2", + "CFG_CENTER_EE4B3_5", + "CFG_CENTER_EE4C3_3", + "CFG_CENTER_SW4END1_5", + "CFG_CENTER_NW4END3_0", + "CFG_CENTER_EFUSE_USR_EFUSEUSR23", + "CFG_CENTER_EE4A1_2", + "CFG_CENTER_IMUX37_4", + "CFG_CENTER_SE2A3_7", + "CFG_CENTER_WW4A3_2", + "CFG_CENTER_EE2BEG3_0", + "CFG_CENTER_NW4A3_4", + "CFG_CENTER_IMUX41_3", + "CFG_CENTER_BLOCK_OUTS_B3_0", + "CFG_CENTER_IMUX1_0", + "CFG_CENTER_IMUX31_1", + "CFG_CENTER_ER1BEG3_3", + "CFG_CENTER_EE4A3_8", + "CFG_CENTER_BYP7_1", + "CFG_CENTER_IMUX26_5", + "CFG_CENTER_IMUX38_8", + "CFG_CENTER_NW4END1_7", + "CFG_CENTER_IMUX37_8", + "CFG_CENTER_WW4B1_0", + "CFG_CENTER_IMUX4_0", + "CFG_CENTER_LOGIC_OUTS_B22_1", + "CFG_CENTER_IMUX35_7", + "CFG_CENTER_WW4A0_8", + "CFG_CENTER_BYP0_0", + "CFG_CENTER_IMUX38_9", + "CFG_CENTER_WW2END0_9", + "CFG_CENTER_IMUX47_1", + "CFG_CENTER_SW4A3_9", + "CFG_CENTER_LH10_0", + "CFG_CENTER_NW2A0_0", + "CFG_CENTER_LOGIC_OUTS_B17_3", + "CFG_CENTER_EE4A3_5", + "CFG_CENTER_IMUX8_7", + "CFG_CENTER_WW2A1_2", + "CFG_CENTER_LH10_7", + "CFG_CENTER_IMUX24_7", + "CFG_CENTER_WR1END2_3", + "CFG_CENTER_SW2A0_0", + "CFG_CENTER_IMUX37_1", + "CFG_CENTER_LOGIC_OUTS_B16_6", + "CFG_CENTER_WL1END1_2", + "CFG_CENTER_EFUSE_USR_EFUSEUSR5", + "CFG_CENTER_EE2BEG2_3", + "CFG_CENTER_NE2A3_2", + "CFG_CENTER_WW4END3_4", + "CFG_CENTER_NE4C1_5", + "CFG_CENTER_FAN4_4", + "CFG_CENTER_WW2END1_4", + "CFG_CENTER_NE4C0_5", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA20", + "CFG_CENTER_NE2A2_4", + "CFG_CENTER_NE2A0_4", + "CFG_CENTER_EE2BEG0_2", + "CFG_CENTER_IMUX16_2", + "CFG_CENTER_CTRL0_2", + "CFG_CENTER_CLK0_8", + "CFG_CENTER_EE4B0_4", + "CFG_CENTER_NW4A0_8", + "CFG_CENTER_LH5_0", + "CFG_CENTER_BLOCK_OUTS_B1_7", + "CFG_CENTER_ER1BEG2_4", + "CFG_CENTER_EE4BEG2_1", + "CFG_CENTER_LOGIC_OUTS_B20_8", + "CFG_CENTER_FAN2_5", + "CFG_CENTER_IMUX36_2", + "CFG_CENTER_LOGIC_OUTS_B0_1", + "CFG_CENTER_SE4C2_3", + "CFG_CENTER_IMUX33_3", + "CFG_CENTER_LOGIC_OUTS_B20_5", + "CFG_CENTER_IMUX15_2", + "CFG_CENTER_NW4A1_6", + "CFG_CENTER_IMUX0_2", + "CFG_CENTER_IMUX19_6", + "CFG_CENTER_SE4BEG1_2", + "CFG_CENTER_IMUX10_4", + "CFG_CENTER_IMUX19_3", + "CFG_CENTER_WW4END0_0", + "CFG_CENTER_WR1END3_7", + "CFG_CENTER_CLK1_6", + "CFG_CENTER_ER1BEG1_4", + "CFG_CENTER_IMUX0_3", + "CFG_CENTER_EE4BEG0_9", + "CFG_CENTER_BLOCK_OUTS_B3_8", + "CFG_CENTER_IMUX27_6", + "CFG_CENTER_EE4BEG0_2", + "CFG_CENTER_NE2A0_1", + "CFG_CENTER_WW2END3_6", + "CFG_CENTER_EE4BEG1_3", + "CFG_CENTER_BYP3_7", + "CFG_CENTER_EE2A0_6", + "CFG_CENTER_NW2A2_9", + "CFG_CENTER_LOGIC_OUTS_B15_1", + "CFG_CENTER_SE2A2_4", + "CFG_CENTER_WW2A1_4", + "CFG_CENTER_SW4A1_0", + "CFG_CENTER_WW4END1_3", + "CFG_CENTER_IMUX20_1", + "CFG_CENTER_LOGIC_OUTS_B19_8", + "CFG_CENTER_WW4C1_9", + "CFG_CENTER_IMUX25_2", + "CFG_CENTER_SW4END3_1", + "CFG_CENTER_IMUX18_8", + "CFG_CENTER_WW2END3_5", + "CFG_CENTER_IMUX36_5", + "CFG_CENTER_EL1BEG1_8", + "CFG_CENTER_IMUX41_1", + "CFG_CENTER_SW4A2_8", + "CFG_CENTER_WL1END2_8", + "CFG_CENTER_IMUX35_0", + "CFG_CENTER_EE4BEG1_9", + "CFG_CENTER_EE4B3_8", + "CFG_CENTER_LOGIC_OUTS_B6_4", + "CFG_CENTER_WW4C1_5", + "CFG_CENTER_IMUX30_8", + "CFG_CENTER_CLK0_3", + "CFG_CENTER_WW2END0_1", + "CFG_CENTER_SE4C0_0", + "CFG_CENTER_IMUX0_5", + "CFG_CENTER_ER1BEG0_0", + "CFG_CENTER_ER1BEG0_9", + "CFG_CENTER_NW2A1_7", + "CFG_CENTER_EE4B2_9", + "CFG_CENTER_IMUX43_7", + "CFG_CENTER_IMUX41_9", + "CFG_CENTER_LH2_1", + "CFG_CENTER_CLK1_0", + "CFG_CENTER_BLOCK_OUTS_B2_7", + "CFG_CENTER_IMUX29_1", + "CFG_CENTER_SW4A0_6", + "CFG_CENTER_BYP3_1", + "CFG_CENTER_SE4BEG2_2", + "CFG_CENTER_EE2A0_3", + "CFG_CENTER_FAN2_1", + "CFG_CENTER_NW4END3_3", + "CFG_CENTER_IMUX11_9", + "CFG_CENTER_WW4A2_2", + "CFG_CENTER_IMUX20_5", + "CFG_CENTER_WW4C2_7", + "CFG_CENTER_SE4C3_5", + "CFG_CENTER_LOGIC_OUTS_B16_7", + "CFG_CENTER_IMUX6_8", + "CFG_CENTER_SW2A3_3", + "CFG_CENTER_FAN5_6", + "CFG_CENTER_IMUX46_3", + "CFG_CENTER_EFUSE_USR_EFUSEUSR26", + "CFG_CENTER_IMUX40_3", + "CFG_CENTER_SW4END1_4", + "CFG_CENTER_IMUX7_6", + "CFG_CENTER_SW4END3_2", + "CFG_CENTER_WW2A0_3", + "CFG_CENTER_IMUX8_0", + "CFG_CENTER_EE4B2_4", + "CFG_CENTER_LH8_2", + "CFG_CENTER_LOGIC_OUTS_B20_2", + "CFG_CENTER_DNA_PORT_READ", + "CFG_CENTER_EE4BEG1_2", + "CFG_CENTER_EL1BEG2_8", + "CFG_CENTER_BYP4_6", + "CFG_CENTER_BYP1_0", + "CFG_CENTER_WL1END1_1", + "CFG_CENTER_SE2A3_4", + "CFG_CENTER_IMUX35_1", + "CFG_CENTER_WL1END3_1", + "CFG_CENTER_IMUX28_6", + "CFG_CENTER_EFUSE_USR_EFUSEUSR15", + "CFG_CENTER_SW2A0_5", + "CFG_CENTER_BYP3_6", + "CFG_CENTER_SE2A0_7", + "CFG_CENTER_TOP_DNA_PORT_CLK", + "CFG_CENTER_WW4A2_8", + "CFG_CENTER_NW4END1_1", + "CFG_CENTER_SW4A1_6", + "CFG_CENTER_SE4C1_2", + "CFG_CENTER_NW4A2_8", + "CFG_CENTER_NE2A2_2", + "CFG_CENTER_WW2A2_4", + "CFG_CENTER_WW4B1_6", + "CFG_CENTER_SW4END3_6", + "CFG_CENTER_EE2A1_9", + "CFG_CENTER_LOGIC_OUTS_B8_7", + "CFG_CENTER_LOGIC_OUTS_B3_4", + "CFG_CENTER_IMUX23_8", + "CFG_CENTER_FAN4_9", + "CFG_CENTER_IMUX17_4", + "CFG_CENTER_WL1END0_8", + "CFG_CENTER_WW2END3_1", + "CFG_CENTER_LH11_0", + "CFG_CENTER_LH12_4", + "CFG_CENTER_SE2A3_3", + "CFG_CENTER_LOGIC_OUTS_B12_9", + "CFG_CENTER_WL1END1_9", + "CFG_CENTER_NW4END3_9", + "CFG_CENTER_WW4A3_8", + "CFG_CENTER_LOGIC_OUTS_B14_3", + "CFG_CENTER_WW4END1_9", + "CFG_CENTER_EE4A0_1", + "CFG_CENTER_IMUX36_3", + "CFG_CENTER_LOGIC_OUTS_B21_3", + "CFG_CENTER_LOGIC_OUTS_B10_5", + "CFG_CENTER_SE4C0_7", + "CFG_CENTER_BYP5_2", + "CFG_CENTER_LOGIC_OUTS_B9_2", + "CFG_CENTER_LOGIC_OUTS_B5_1", + "CFG_CENTER_EE4C0_5", + "CFG_CENTER_EE4A2_4", + "CFG_CENTER_NE4BEG1_5", + "CFG_CENTER_NW2A2_3", + "CFG_CENTER_EFUSE_USR_EFUSEUSR11", + "CFG_CENTER_LH5_4", + "CFG_CENTER_IMUX21_5", + "CFG_CENTER_FAN7_1", + "CFG_CENTER_IMUX12_7", + "CFG_CENTER_LOGIC_OUTS_B2_8", + "CFG_CENTER_NW4END3_6", + "CFG_CENTER_NW4END1_4", + "CFG_CENTER_EE4B0_5", + "CFG_CENTER_IMUX28_0", + "CFG_CENTER_EL1BEG1_5", + "CFG_CENTER_LOGIC_OUTS_B5_7", + "CFG_CENTER_ER1BEG0_1", + "CFG_CENTER_LH9_4", + "CFG_CENTER_WR1END3_4", + "CFG_CENTER_LOGIC_OUTS_B23_1", + "CFG_CENTER_EE2BEG3_8", + "CFG_CENTER_WL1END2_7", + "CFG_CENTER_BLOCK_OUTS_B2_8", + "CFG_CENTER_IMUX40_7", + "CFG_CENTER_IMUX47_5", + "CFG_CENTER_FAN5_7", + "CFG_CENTER_EE4B3_6", + "CFG_CENTER_WR1END2_8", + "CFG_CENTER_TOP_ICAP1_CLK", + "CFG_CENTER_EE4BEG0_8", + "CFG_CENTER_IMUX7_2", + "CFG_CENTER_LOGIC_OUTS_B0_4", + "CFG_CENTER_IMUX34_9", + "CFG_CENTER_IMUX39_7", + "CFG_CENTER_WW2A1_1", + "CFG_CENTER_WW4END3_7", + "CFG_CENTER_NW2A3_6", + "CFG_CENTER_SW2A1_2", + "CFG_CENTER_IMUX12_3", + "CFG_CENTER_LOGIC_OUTS_B8_8", + "CFG_CENTER_NE4BEG3_5", + "CFG_CENTER_FAN0_7", + "CFG_CENTER_SW4A0_8", + "CFG_CENTER_LOGIC_OUTS_B21_0", + "CFG_CENTER_NW4A3_8", + "CFG_CENTER_NW4A1_2", + "CFG_CENTER_LOGIC_OUTS_B17_0", + "CFG_CENTER_IMUX44_4", + "CFG_CENTER_SE2A3_9", + "CFG_CENTER_SW4END2_9", + "CFG_CENTER_LOGIC_OUTS_B16_4", + "CFG_CENTER_NW2A3_9", + "CFG_CENTER_NE4C1_1", + "CFG_CENTER_EE4B1_5", + "CFG_CENTER_IMUX19_1", + "CFG_CENTER_CTRL0_5", + "CFG_CENTER_BYP6_6", + "CFG_CENTER_IMUX37_3", + "CFG_CENTER_EE4C2_5", + "CFG_CENTER_SE4BEG0_6", + "CFG_CENTER_LOGIC_OUTS_B2_4", + "CFG_CENTER_NW4A2_0", + "CFG_CENTER_EE4BEG2_2", + "CFG_CENTER_IMUX6_0", + "CFG_CENTER_SW4END3_7", + "CFG_CENTER_SW4A0_1", + "CFG_CENTER_SW4A2_5", + "CFG_CENTER_LH10_4", + "CFG_CENTER_LH12_6", + "CFG_CENTER_IMUX7_0", + "CFG_CENTER_IMUX34_1", + "CFG_CENTER_LOGIC_OUTS_B13_1", + "CFG_CENTER_IMUX41_7", + "CFG_CENTER_LH1_5", + "CFG_CENTER_WW4END0_7", + "CFG_CENTER_NE2A1_1", + "CFG_CENTER_LOGIC_OUTS_B0_9", + "CFG_CENTER_EE4B2_8", + "CFG_CENTER_IMUX24_0", + "CFG_CENTER_LOGIC_OUTS_B14_8", + "CFG_CENTER_IMUX24_8", + "CFG_CENTER_LOGIC_OUTS_B4_2", + "CFG_CENTER_NE2A2_6", + "CFG_CENTER_LH8_1", + "CFG_CENTER_EE2A2_5", + "CFG_CENTER_FAN3_9", + "CFG_CENTER_LH4_4", + "CFG_CENTER_NW2A0_6", + "CFG_CENTER_IMUX28_1", + "CFG_CENTER_CLK0_2", + "CFG_CENTER_NE4BEG2_4", + "CFG_CENTER_BLOCK_OUTS_B1_9", + "CFG_CENTER_IMUX0_6", + "CFG_CENTER_LH3_7", + "CFG_CENTER_IMUX1_2", + "CFG_CENTER_LOGIC_OUTS_B9_0", + "CFG_CENTER_WW4C2_9", + "CFG_CENTER_EE4A1_8", + "CFG_CENTER_WW4END0_1", + "CFG_CENTER_LOGIC_OUTS_B1_9", + "CFG_CENTER_SW4END0_7", + "CFG_CENTER_IMUX41_8", + "CFG_CENTER_EE4A1_7", + "CFG_CENTER_IMUX39_9", + "CFG_CENTER_FAN5_9", + "CFG_CENTER_EE4B0_3", + "CFG_CENTER_IMUX20_3", + "CFG_CENTER_SW4A1_1", + "CFG_CENTER_LOGIC_OUTS_B19_1", + "CFG_CENTER_LOGIC_OUTS_B4_7", + "CFG_CENTER_IMUX44_9", + "CFG_CENTER_LH11_3", + "CFG_CENTER_SW4A3_6", + "CFG_CENTER_BYP6_5", + "CFG_CENTER_IMUX27_5", + "CFG_CENTER_LH2_9", + "CFG_CENTER_SW4END1_8", + "CFG_CENTER_IMUX35_8", + "CFG_CENTER_SW4A2_9", + "CFG_CENTER_NE4BEG0_1", + "CFG_CENTER_CTRL0_1", + "CFG_CENTER_FAN3_2", + "CFG_CENTER_LH8_6", + "CFG_CENTER_LOGIC_OUTS_B1_0", + "CFG_CENTER_WR1END1_7", + "CFG_CENTER_WW4END0_9", + "CFG_CENTER_IMUX3_2", + "CFG_CENTER_WW4C2_2", + "CFG_CENTER_WW4A3_3", + "CFG_CENTER_FAN6_2", + "CFG_CENTER_SW4END1_6", + "CFG_CENTER_NE4BEG2_1", + "CFG_CENTER_NW4A1_5", + "CFG_CENTER_BYP4_7", + "CFG_CENTER_EL1BEG3_5", + "CFG_CENTER_NE4C3_0", + "CFG_CENTER_FAN4_0", + "CFG_CENTER_LOGIC_OUTS_B21_2", + "CFG_CENTER_NE2A1_6", + "CFG_CENTER_FAN1_2", + "CFG_CENTER_NE4C0_2", + "CFG_CENTER_WW4END1_8", + "CFG_CENTER_IMUX35_9", + "CFG_CENTER_LH10_1", + "CFG_CENTER_ER1BEG0_3", + "CFG_CENTER_IMUX40_0", + "CFG_CENTER_NW2A0_7", + "CFG_CENTER_SW4A3_8", + "CFG_CENTER_WW2END0_0", + "CFG_CENTER_IMUX8_8", + "CFG_CENTER_LH6_9", + "CFG_CENTER_EE4BEG2_4", + "CFG_CENTER_LH6_2", + "CFG_CENTER_WW2END2_1", + "CFG_CENTER_EFUSE_USR_EFUSEUSR20", + "CFG_CENTER_BLOCK_OUTS_B0_6", + "CFG_CENTER_CTRL1_4", + "CFG_CENTER_IMUX44_0", + "CFG_CENTER_IMUX5_4", + "CFG_CENTER_NW4A2_7", + "CFG_CENTER_WW2A0_0", + "CFG_CENTER_WW4C1_4", + "CFG_CENTER_LOGIC_OUTS_B17_2", + "CFG_CENTER_EE2BEG2_0", + "CFG_CENTER_IMUX29_3", + "CFG_CENTER_NE4BEG0_4", + "CFG_CENTER_IMUX29_7", + "CFG_CENTER_LH11_8", + "CFG_CENTER_IMUX15_0", + "CFG_CENTER_LOGIC_OUTS_B18_6", + "CFG_CENTER_EFUSE_USR_EFUSEUSR10", + "CFG_CENTER_IMUX14_9", + "CFG_CENTER_IMUX45_3", + "CFG_CENTER_NE2A3_9", + "CFG_CENTER_EFUSE_USR_EFUSEUSR25", + "CFG_CENTER_BLOCK_OUTS_B0_8", + "CFG_CENTER_EE4A3_9", + "CFG_CENTER_NE4BEG1_6", + "CFG_CENTER_WW2END2_5", + "CFG_CENTER_IMUX12_8", + "CFG_CENTER_IMUX6_7", + "CFG_CENTER_LOGIC_OUTS_B18_1", + "CFG_CENTER_IMUX17_0", + "CFG_CENTER_WW4END1_7", + "CFG_CENTER_IMUX36_9", + "CFG_CENTER_IMUX31_3", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA25", + "CFG_CENTER_BYP0_2", + "CFG_CENTER_WL1END3_9", + "CFG_CENTER_WW2A1_3", + "CFG_CENTER_EL1BEG0_1", + "CFG_CENTER_NW4END2_1", + "CFG_CENTER_WW4C1_3", + "CFG_CENTER_IMUX11_7", + "CFG_CENTER_LH8_8", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA12", + "CFG_CENTER_IMUX9_6", + "CFG_CENTER_IMUX16_6", + "CFG_CENTER_IMUX26_1", + "CFG_CENTER_LOGIC_OUTS_B23_9", + "CFG_CENTER_LOGIC_OUTS_B22_3", + "CFG_CENTER_IMUX19_8", + "CFG_CENTER_IMUX33_6", + "CFG_CENTER_WW4C0_0", + "CFG_CENTER_LOGIC_OUTS_B22_8", + "CFG_CENTER_IMUX29_2", + "CFG_CENTER_IMUX42_6", + "CFG_CENTER_WW4A2_3", + "CFG_CENTER_SE4C3_7", + "CFG_CENTER_SW4END1_3", + "CFG_CENTER_LH5_9", + "CFG_CENTER_IMUX2_0", + "CFG_CENTER_EE4BEG2_9", + "CFG_CENTER_SW2A2_6", + "CFG_CENTER_IMUX11_2", + "CFG_CENTER_IMUX12_9", + "CFG_CENTER_IMUX25_5", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA13", + "CFG_CENTER_WR1END0_0", + "CFG_CENTER_SE2A0_2", + "CFG_CENTER_LH8_3", + "CFG_CENTER_EL1BEG0_8", + "CFG_CENTER_IMUX43_3", + "CFG_CENTER_EE4A3_6", + "CFG_CENTER_LOGIC_OUTS_B12_0", + "CFG_CENTER_ER1BEG1_0", + "CFG_CENTER_SE4C2_4", + "CFG_CENTER_WW4A3_1", + "CFG_CENTER_WW4B2_0", + "CFG_CENTER_IMUX30_4", + "CFG_CENTER_SW2A0_2", + "CFG_CENTER_LOGIC_OUTS_B13_4", + "CFG_CENTER_ER1BEG1_8", + "CFG_CENTER_IMUX40_2", + "CFG_CENTER_NW4END2_5", + "CFG_CENTER_FAN1_0", + "CFG_CENTER_BYP1_5", + "CFG_CENTER_EE4A2_1", + "CFG_CENTER_IMUX22_5", + "CFG_CENTER_NE4C3_1", + "CFG_CENTER_NE4C2_5", + "CFG_CENTER_EE4A0_7", + "CFG_CENTER_WW2END2_8", + "CFG_CENTER_FAN3_6", + "CFG_CENTER_IMUX31_8", + "CFG_CENTER_WR1END1_5", + "CFG_CENTER_IMUX2_9", + "CFG_CENTER_EE2BEG0_9", + "CFG_CENTER_DNA_PORT_DOUT", + "CFG_CENTER_NE4BEG3_7", + "CFG_CENTER_FAN1_7", + "CFG_CENTER_IMUX11_1", + "CFG_CENTER_NE4C2_1", + "CFG_CENTER_LOGIC_OUTS_B12_5", + "CFG_CENTER_NE2A3_4", + "CFG_CENTER_NW2A2_1", + "CFG_CENTER_WW2END2_7", + "CFG_CENTER_EE4C1_7", + "CFG_CENTER_NW4A1_4", + "CFG_CENTER_BYP7_4", + "CFG_CENTER_LOGIC_OUTS_B1_2", + "CFG_CENTER_LOGIC_OUTS_B2_1", + "CFG_CENTER_FAN6_9", + "CFG_CENTER_WW4C0_6", + "CFG_CENTER_IMUX15_1", + "CFG_CENTER_IMUX42_3", + "CFG_CENTER_LH11_4", + "CFG_CENTER_LOGIC_OUTS_B17_7", + "CFG_CENTER_EE2A3_9", + "CFG_CENTER_LOGIC_OUTS_B4_1", + "CFG_CENTER_IMUX33_1", + "CFG_CENTER_WW4B2_3", + "CFG_CENTER_LH9_2", + "CFG_CENTER_LOGIC_OUTS_B3_3", + "CFG_CENTER_WW2A3_7", + "CFG_CENTER_EL1BEG3_4", + "CFG_CENTER_IMUX2_6", + "CFG_CENTER_EL1BEG3_8", + "CFG_CENTER_IMUX26_0", + "CFG_CENTER_IMUX26_7", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA15", + "CFG_CENTER_WW2END1_5", + "CFG_CENTER_EE4C0_2", + "CFG_CENTER_FAN0_9", + "CFG_CENTER_EE2A1_4", + "CFG_CENTER_SW2A3_2", + "CFG_CENTER_LH1_1", + "CFG_CENTER_NE4BEG1_9", + "CFG_CENTER_ER1BEG2_9", + "CFG_CENTER_NW4A0_4", + "CFG_CENTER_LH2_4", + "CFG_CENTER_WR1END1_6", + "CFG_CENTER_SW4END2_4", + "CFG_CENTER_LOGIC_OUTS_B16_5", + "CFG_CENTER_IMUX21_8", + "CFG_CENTER_LH9_5", + "CFG_CENTER_LOGIC_OUTS_B13_8", + "CFG_CENTER_WL1END2_0", + "CFG_CENTER_IMUX23_1", + "CFG_CENTER_SW4A1_3", + "CFG_CENTER_EFUSE_USR_EFUSEUSR14", + "CFG_CENTER_WW2A2_3", + "CFG_CENTER_LH12_0", + "CFG_CENTER_LH6_6", + "CFG_CENTER_IMUX42_4", + "CFG_CENTER_SE4BEG1_1", + "CFG_CENTER_WL1END0_0", + "CFG_CENTER_LH4_5", + "CFG_CENTER_SW4A3_1", + "CFG_CENTER_LOGIC_OUTS_B9_1", + "CFG_CENTER_LOGIC_OUTS_B16_1", + "CFG_CENTER_WW2END1_6", + "CFG_CENTER_WW4A0_2", + "CFG_CENTER_NE4BEG2_0", + "CFG_CENTER_CLK1_9", + "CFG_CENTER_LH11_7", + "CFG_CENTER_WW4C2_1", + "CFG_CENTER_NW4A0_3", + "CFG_CENTER_ER1BEG3_1", + "CFG_CENTER_WW4C0_7", + "CFG_CENTER_WW2A1_5", + "CFG_CENTER_SW4END0_1", + "CFG_CENTER_NE2A3_0", + "CFG_CENTER_SW4END2_2", + "CFG_CENTER_EE2BEG3_9", + "CFG_CENTER_IMUX30_1", + "CFG_CENTER_SE2A0_1", + "CFG_CENTER_WW2END1_0", + "CFG_CENTER_NW2A2_4", + "CFG_CENTER_BLOCK_OUTS_B0_5", + "CFG_CENTER_EE4C3_9", + "CFG_CENTER_EE2A1_3", + "CFG_CENTER_IMUX0_4", + "CFG_CENTER_IMUX16_9", + "CFG_CENTER_BYP0_1", + "CFG_CENTER_WW2A3_2", + "CFG_CENTER_LOGIC_OUTS_B23_5", + "CFG_CENTER_ER1BEG0_2", + "CFG_CENTER_SW2A3_8", + "CFG_CENTER_NE4BEG0_0", + "CFG_CENTER_LOGIC_OUTS_B4_6", + "CFG_CENTER_NW4END3_1", + "CFG_CENTER_ER1BEG3_2", + "CFG_CENTER_IMUX23_6", + "CFG_CENTER_IMUX40_9", + "CFG_CENTER_IMUX46_9", + "CFG_CENTER_WW2END2_3", + "CFG_CENTER_LOGIC_OUTS_B4_0", + "CFG_CENTER_WR1END0_7", + "CFG_CENTER_SE4BEG3_8", + "CFG_CENTER_IMUX19_4", + "CFG_CENTER_LOGIC_OUTS_B21_5", + "CFG_CENTER_IMUX14_7", + "CFG_CENTER_SE4C3_8", + "CFG_CENTER_IMUX23_7", + "CFG_CENTER_IMUX34_5", + "CFG_CENTER_WW4A2_1", + "CFG_CENTER_NW2A0_3", + "CFG_CENTER_IMUX16_7", + "CFG_CENTER_BLOCK_OUTS_B3_1", + "CFG_CENTER_WW4A3_5", + "CFG_CENTER_WW4A3_7", + "CFG_CENTER_BLOCK_OUTS_B1_1", + "CFG_CENTER_WW2END1_2", + "CFG_CENTER_LH8_9", + "CFG_CENTER_EFUSE_USR_EFUSEUSR21", + "CFG_CENTER_WW2END2_4", + "CFG_CENTER_NE4BEG3_6", + "CFG_CENTER_IMUX29_6", + "CFG_CENTER_LOGIC_OUTS_B8_4", + "CFG_CENTER_WW4B1_8", + "CFG_CENTER_ER1BEG3_5", + "CFG_CENTER_WW4B3_3", + "CFG_CENTER_NW4END0_8", + "CFG_CENTER_WW4A2_0", + "CFG_CENTER_BLOCK_OUTS_B0_3", + "CFG_CENTER_IMUX17_3", + "CFG_CENTER_EE4A3_0", + "CFG_CENTER_IMUX42_8", + "CFG_CENTER_NE2A2_1", + "CFG_CENTER_NE2A0_2", + "CFG_CENTER_WW4END1_2", + "CFG_CENTER_IMUX43_8", + "CFG_CENTER_SW2A1_7", + "CFG_CENTER_EE2BEG1_9", + "CFG_CENTER_FAN4_8", + "CFG_CENTER_LH9_6", + "CFG_CENTER_EE4B2_0", + "CFG_CENTER_EE4A1_9", + "CFG_CENTER_WR1END0_9", + "CFG_CENTER_LH12_7", + "CFG_CENTER_IMUX36_8", + "CFG_CENTER_LOGIC_OUTS_B17_1", + "CFG_CENTER_BLOCK_OUTS_B3_4", + "CFG_CENTER_IMUX21_6", + "CFG_CENTER_LOGIC_OUTS_B4_9", + "CFG_CENTER_NW4A3_6", + "CFG_CENTER_NW4END3_7", + "CFG_CENTER_LOGIC_OUTS_B20_3", + "CFG_CENTER_LOGIC_OUTS_B2_6", + "CFG_CENTER_WR1END1_4", + "CFG_CENTER_EE4BEG0_0", + "CFG_CENTER_IMUX44_3", + "CFG_CENTER_IMUX2_4", + "CFG_CENTER_EL1BEG0_7", + "CFG_CENTER_IMUX27_8", + "CFG_CENTER_SW2A2_4", + "CFG_CENTER_NW4A1_3", + "CFG_CENTER_EL1BEG2_1", + "CFG_CENTER_NW2A2_0", + "CFG_CENTER_EE2A3_6", + "CFG_CENTER_NW2A2_2", + "CFG_CENTER_LOGIC_OUTS_B13_2", + "CFG_CENTER_FAN0_0", + "CFG_CENTER_NE4BEG0_2", + "CFG_CENTER_NW4END0_9", + "CFG_CENTER_NW4END1_2", + "CFG_CENTER_NW2A2_7", + "CFG_CENTER_IMUX7_3", + "CFG_CENTER_IMUX21_9", + "CFG_CENTER_SE2A3_6", + "CFG_CENTER_FAN6_6", + "CFG_CENTER_CTRL0_9", + "CFG_CENTER_SW4END0_5", + "CFG_CENTER_IMUX19_7", + "CFG_CENTER_FAN6_8", + "CFG_CENTER_IMUX6_6", + "CFG_CENTER_WW4B1_7", + "CFG_CENTER_LOGIC_OUTS_B3_5", + "CFG_CENTER_SE4C3_2", + "CFG_CENTER_NE4BEG2_2", + "CFG_CENTER_IMUX0_0", + "CFG_CENTER_FAN5_1", + "CFG_CENTER_IMUX44_8", + "CFG_CENTER_FAN7_7", + "CFG_CENTER_EL1BEG2_3", + "CFG_CENTER_WR1END1_1", + "CFG_CENTER_SE4BEG2_5", + "CFG_CENTER_BLOCK_OUTS_B1_4", + "CFG_CENTER_NE4BEG0_8", + "CFG_CENTER_IMUX38_2", + "CFG_CENTER_IMUX1_9", + "CFG_CENTER_SE4BEG3_5", + "CFG_CENTER_SE4BEG1_8", + "CFG_CENTER_IMUX24_9", + "CFG_CENTER_LOGIC_OUTS_B17_4", + "CFG_CENTER_WW2END0_4", + "CFG_CENTER_EE4C2_7", + "CFG_CENTER_LOGIC_OUTS_B19_0", + "CFG_CENTER_BLOCK_OUTS_B0_7", + "CFG_CENTER_WW2A0_8", + "CFG_CENTER_LH8_4", + "CFG_CENTER_LOGIC_OUTS_B18_8", + "CFG_CENTER_EFUSE_USR_EFUSEUSR13", + "CFG_CENTER_SW4A0_4", + "CFG_CENTER_EE2A1_2", + "CFG_CENTER_SE4BEG3_2", + "CFG_CENTER_EE4A0_6", + "CFG_CENTER_SE2A1_6", + "CFG_CENTER_WW4A2_7", + "CFG_CENTER_SE2A3_8", + "CFG_CENTER_EE2A1_8", + "CFG_CENTER_SW2A0_3", + "CFG_CENTER_NE4C0_6", + "CFG_CENTER_EE2A3_2", + "CFG_CENTER_IMUX21_2", + "CFG_CENTER_LOGIC_OUTS_B6_2", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA19", + "CFG_CENTER_IMUX30_0", + "CFG_CENTER_EFUSE_USR_EFUSEUSR29", + "CFG_CENTER_EE4C2_6", + "CFG_CENTER_IMUX3_4", + "CFG_CENTER_IMUX19_2", + "CFG_CENTER_EE4BEG3_7", + "CFG_CENTER_IMUX44_6", + "CFG_CENTER_EE4C0_7", + "CFG_CENTER_SW4A3_0", + "CFG_CENTER_WW4B0_3", + "CFG_CENTER_WW4END1_0", + "CFG_CENTER_LOGIC_OUTS_B0_7", + "CFG_CENTER_WW4C2_6", + "CFG_CENTER_SW4A0_5", + "CFG_CENTER_BYP2_1", + "CFG_CENTER_IMUX20_8", + "CFG_CENTER_EE4BEG0_7", + "CFG_CENTER_IMUX42_5", + "CFG_CENTER_NE4C0_3", + "CFG_CENTER_WW2END0_6", + "CFG_CENTER_SE4C0_6", + "CFG_CENTER_NE2A0_7", + "CFG_CENTER_WR1END1_8", + "CFG_CENTER_LOGIC_OUTS_B7_8", + "CFG_CENTER_EE4A3_7", + "CFG_CENTER_LH3_5", + "CFG_CENTER_IMUX28_7", + "CFG_CENTER_CLK0_5", + "CFG_CENTER_LOGIC_OUTS_B3_8", + "CFG_CENTER_FAN1_3", + "CFG_CENTER_WW4END0_4", + "CFG_CENTER_IMUX43_2", + "CFG_CENTER_SE4BEG0_2", + "CFG_CENTER_WL1END0_2", + "CFG_CENTER_LH6_7", + "CFG_CENTER_IMUX33_9", + "CFG_CENTER_WW2A0_1", + "CFG_CENTER_LH12_2", + "CFG_CENTER_IMUX18_3", + "CFG_CENTER_LOGIC_OUTS_B21_6", + "CFG_CENTER_EE2A2_6", + "CFG_CENTER_EE2BEG2_8", + "CFG_CENTER_EE4C0_3", + "CFG_CENTER_IMUX26_8", + "CFG_CENTER_EE4C2_3", + "CFG_CENTER_LH3_4", + "CFG_CENTER_IMUX6_5", + "CFG_CENTER_LH9_3", + "CFG_CENTER_EE2BEG3_3", + "CFG_CENTER_BYP6_0", + "CFG_CENTER_LH9_8", + "CFG_CENTER_IMUX29_9", + "CFG_CENTER_FAN3_0", + "CFG_CENTER_EE4C3_1", + "CFG_CENTER_IMUX22_0", + "CFG_CENTER_NE2A2_7", + "CFG_CENTER_NE2A1_7", + "CFG_CENTER_LOGIC_OUTS_B7_2", + "CFG_CENTER_IMUX5_2", + "CFG_CENTER_IMUX9_3", + "CFG_CENTER_IMUX28_5", + "CFG_CENTER_EFUSE_USR_EFUSEUSR7", + "CFG_CENTER_IMUX32_8", + "CFG_CENTER_BYP7_2", + "CFG_CENTER_IMUX46_0", + "CFG_CENTER_WR1END2_7", + "CFG_CENTER_WL1END2_9", + "CFG_CENTER_IMUX10_3", + "CFG_CENTER_IMUX35_5", + "CFG_CENTER_IMUX34_7", + "CFG_CENTER_WL1END3_7", + "CFG_CENTER_WW4B0_9", + "CFG_CENTER_NW4END2_9", + "CFG_CENTER_SW2A1_4", + "CFG_CENTER_BYP4_0", + "CFG_CENTER_ER1BEG0_6", + "CFG_CENTER_NE4C1_2", + "CFG_CENTER_IMUX12_2", + "CFG_CENTER_LH10_5", + "CFG_CENTER_LOGIC_OUTS_B7_9", + "CFG_CENTER_LOGIC_OUTS_B14_5", + "CFG_CENTER_IMUX5_7", + "CFG_CENTER_WW2A2_0", + "CFG_CENTER_WW4C0_8", + "CFG_CENTER_IMUX15_3", + "CFG_CENTER_WW2A2_8", + "CFG_CENTER_LOGIC_OUTS_B9_9", + "CFG_CENTER_WW4B0_7", + "CFG_CENTER_ER1BEG2_3", + "CFG_CENTER_IMUX44_2", + "CFG_CENTER_EE4BEG1_8", + "CFG_CENTER_IMUX34_4", + "CFG_CENTER_SE4BEG1_7", + "CFG_CENTER_LOGIC_OUTS_B13_6", + "CFG_CENTER_WW4A0_1", + "CFG_CENTER_EE2BEG3_2", + "CFG_CENTER_WW2END2_9", + "CFG_CENTER_BYP5_8", + "CFG_CENTER_LOGIC_OUTS_B20_4", + "CFG_CENTER_EE2A2_2", + "CFG_CENTER_LOGIC_OUTS_B16_9", + "CFG_CENTER_WW4C1_6", + "CFG_CENTER_BYP6_7", + "CFG_CENTER_SE2A2_8", + "CFG_CENTER_CTRL1_9", + "CFG_CENTER_EL1BEG3_1", + "CFG_CENTER_IMUX0_8", + "CFG_CENTER_NW2A0_2", + "CFG_CENTER_WW4END1_4", + "CFG_CENTER_EE2BEG2_2", + "CFG_CENTER_IMUX42_2", + "CFG_CENTER_EE4BEG0_4", + "CFG_CENTER_IMUX8_1", + "CFG_CENTER_WW4A2_9", + "CFG_CENTER_EE4B1_8", + "CFG_CENTER_LH7_9", + "CFG_CENTER_EE2BEG0_8", + "CFG_CENTER_EFUSE_USR_EFUSEUSR17", + "CFG_CENTER_WW4A0_4", + "CFG_CENTER_IMUX5_3", + "CFG_CENTER_WR1END1_3", + "CFG_CENTER_NE2A3_5", + "CFG_CENTER_IMUX2_3", + "CFG_CENTER_LH7_8", + "CFG_CENTER_SW4A1_8", + "CFG_CENTER_LOGIC_OUTS_B7_0", + "CFG_CENTER_SW4A0_0", + "CFG_CENTER_EE4B3_3", + "CFG_CENTER_IMUX17_5", + "CFG_CENTER_LH6_8", + "CFG_CENTER_BYP1_8", + "CFG_CENTER_EE4B3_1", + "CFG_CENTER_BLOCK_OUTS_B2_3", + "CFG_CENTER_LOGIC_OUTS_B12_4", + "CFG_CENTER_SE4BEG3_7", + "CFG_CENTER_EE4B1_7", + "CFG_CENTER_BYP7_0", + "CFG_CENTER_EL1BEG2_2", + "CFG_CENTER_EFUSE_USR_EFUSEUSR9", + "CFG_CENTER_LOGIC_OUTS_B23_6", + "CFG_CENTER_NW4END0_0", + "CFG_CENTER_NW2A1_1", + "CFG_CENTER_LOGIC_OUTS_B16_8", + "CFG_CENTER_SE4BEG0_0", + "CFG_CENTER_IMUX13_5", + "CFG_CENTER_NW2A3_5", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA16", + "CFG_CENTER_EE2BEG0_3", + "CFG_CENTER_ER1BEG0_8", + "CFG_CENTER_IMUX4_8", + "CFG_CENTER_EE4B3_2", + "CFG_CENTER_LOGIC_OUTS_B11_7", + "CFG_CENTER_IMUX13_8", + "CFG_CENTER_BYP2_3", + "CFG_CENTER_EFUSE_USR_EFUSEUSR3", + "CFG_CENTER_IMUX38_5", + "CFG_CENTER_EE4A1_6", + "CFG_CENTER_WW4C0_4", + "CFG_CENTER_WW4END3_2", + "CFG_CENTER_IMUX15_7", + "CFG_CENTER_LOGIC_OUTS_B12_8", + "CFG_CENTER_IMUX9_7", + "CFG_CENTER_BYP2_9", + "CFG_CENTER_EE4BEG3_2", + "CFG_CENTER_EFUSE_USR_EFUSEUSR6", + "CFG_CENTER_SE4BEG1_0", + "CFG_CENTER_WW2END0_2", + "CFG_CENTER_IMUX14_1", + "CFG_CENTER_BYP7_9", + "CFG_CENTER_LH5_3", + "CFG_CENTER_IMUX29_0", + "CFG_CENTER_NE2A1_9", + "CFG_CENTER_EE4A0_0", + "CFG_CENTER_IMUX9_0", + "CFG_CENTER_ER1BEG3_6", + "CFG_CENTER_NW4A0_9", + "CFG_CENTER_NW4END0_2", + "CFG_CENTER_SE2A1_3", + "CFG_CENTER_LOGIC_OUTS_B1_8", + "CFG_CENTER_IMUX21_1", + "CFG_CENTER_NE4C1_0", + "CFG_CENTER_EE4A1_0", + "CFG_CENTER_LOGIC_OUTS_B12_2", + "CFG_CENTER_WW2END3_0", + "CFG_CENTER_LOGIC_OUTS_B22_0", + "CFG_CENTER_WW4B2_1", + "CFG_CENTER_IMUX43_0", + "CFG_CENTER_IMUX3_8", + "CFG_CENTER_FAN1_4", + "CFG_CENTER_SW4A1_4", + "CFG_CENTER_NE4BEG1_3", + "CFG_CENTER_EE2A0_7", + "CFG_CENTER_SW2A3_7", + "CFG_CENTER_IMUX38_7", + "CFG_CENTER_IMUX0_7", + "CFG_CENTER_IMUX45_5", + "CFG_CENTER_NE4C1_4", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA21", + "CFG_CENTER_IMUX3_1", + "CFG_CENTER_EE4C1_4", + "CFG_CENTER_BLOCK_OUTS_B0_2", + "CFG_CENTER_IMUX43_1", + "CFG_CENTER_SW4A3_7", + "CFG_CENTER_NE2A0_5", + "CFG_CENTER_SE2A2_2", + "CFG_CENTER_LOGIC_OUTS_B1_3", + "CFG_CENTER_SE2A0_6", + "CFG_CENTER_EE4A0_4", + "CFG_CENTER_IMUX46_5", + "CFG_CENTER_FAN7_8", + "CFG_CENTER_SW4A1_9", + "CFG_CENTER_BYP7_5", + "CFG_CENTER_LOGIC_OUTS_B16_0", + "CFG_CENTER_CLK0_7", + "CFG_CENTER_LOGIC_OUTS_B19_6", + "CFG_CENTER_EL1BEG2_5", + "CFG_CENTER_EE4C0_0", + "CFG_CENTER_NE4BEG1_8", + "CFG_CENTER_WW4C0_3", + "CFG_CENTER_IMUX13_6", + "CFG_CENTER_NW2A3_0", + "CFG_CENTER_EE4C0_6", + "CFG_CENTER_IMUX39_2", + "CFG_CENTER_CLK0_9", + "CFG_CENTER_LOGIC_OUTS_B11_6", + "CFG_CENTER_IMUX16_0", + "CFG_CENTER_WR1END0_5", + "CFG_CENTER_WW2END3_4", + "CFG_CENTER_SE4BEG0_5", + "CFG_CENTER_IMUX32_4", + "CFG_CENTER_WW2A1_8", + "CFG_CENTER_WW4B2_2", + "CFG_CENTER_EE2A2_4", + "CFG_CENTER_IMUX22_2", + "CFG_CENTER_IMUX7_4", + "CFG_CENTER_NW4END2_8", + "CFG_CENTER_LOGIC_OUTS_B23_8", + "CFG_CENTER_IMUX13_4", + "CFG_CENTER_FAN3_5", + "CFG_CENTER_CLK1_3", + "CFG_CENTER_IMUX15_6", + "CFG_CENTER_LOGIC_OUTS_B9_4", + "CFG_CENTER_LOGIC_OUTS_B23_0", + "CFG_CENTER_LOGIC_OUTS_B23_4", + "CFG_CENTER_SW2A1_1", + "CFG_CENTER_WL1END3_0", + "CFG_CENTER_NE4BEG3_4", + "CFG_CENTER_IMUX36_6", + "CFG_CENTER_LOGIC_OUTS_B22_4", + "CFG_CENTER_NE4BEG2_3", + "CFG_CENTER_NE4BEG2_8", + "CFG_CENTER_EE4C0_1", + "CFG_CENTER_IMUX10_8", + "CFG_CENTER_LOGIC_OUTS_B10_0", + "CFG_CENTER_EL1BEG2_7", + "CFG_CENTER_WW4B2_7", + "CFG_CENTER_SW2A3_0", + "CFG_CENTER_IMUX4_6", + "CFG_CENTER_WW2END2_6", + "CFG_CENTER_LOGIC_OUTS_B9_7", + "CFG_CENTER_WW4B3_6", + "CFG_CENTER_IMUX21_0", + "CFG_CENTER_WW4END3_5", + "CFG_CENTER_EE4BEG2_3", + "CFG_CENTER_NW4END1_6", + "CFG_CENTER_SE2A2_0", + "CFG_CENTER_ER1BEG3_7", + "CFG_CENTER_NW4END0_6", + "CFG_CENTER_WW4END3_1", + "CFG_CENTER_LOGIC_OUTS_B3_1", + "CFG_CENTER_IMUX17_6", + "CFG_CENTER_LH1_9", + "CFG_CENTER_WW4C0_9", + "CFG_CENTER_WL1END0_4", + "CFG_CENTER_WW2END1_1", + "CFG_CENTER_FAN4_5", + "CFG_CENTER_BLOCK_OUTS_B3_5", + "CFG_CENTER_LH4_2", + "CFG_CENTER_WW2END1_9", + "CFG_CENTER_NE4C3_9", + "CFG_CENTER_WW4END2_1", + "CFG_CENTER_IMUX5_0", + "CFG_CENTER_IMUX31_4", + "CFG_CENTER_WW4C2_3", + "CFG_CENTER_NW2A1_4", + "CFG_CENTER_WW4C0_1", + "CFG_CENTER_NW2A3_7", + "CFG_CENTER_EL1BEG0_6", + "CFG_CENTER_FAN0_4", + "CFG_CENTER_IMUX4_7", + "CFG_CENTER_EE4A1_5", + "CFG_CENTER_SW2A0_7", + "CFG_CENTER_IMUX33_8", + "CFG_CENTER_NE4BEG2_5", + "CFG_CENTER_EE4B1_6", + "CFG_CENTER_NW4A0_6", + "CFG_CENTER_IMUX7_8", + "CFG_CENTER_IMUX21_4", + "CFG_CENTER_NW4A1_0", + "CFG_CENTER_WL1END3_5", + "CFG_CENTER_SE4C2_6", + "CFG_CENTER_SW4END3_3", + "CFG_CENTER_FAN2_6", + "CFG_CENTER_IMUX4_1", + "CFG_CENTER_IMUX45_8", + "CFG_CENTER_LOGIC_OUTS_B15_4", + "CFG_CENTER_NW4END2_3", + "CFG_CENTER_IMUX29_5", + "CFG_CENTER_IMUX25_0", + "CFG_CENTER_WW2END0_8", + "CFG_CENTER_WW2A1_6", + "CFG_CENTER_SE4C1_6", + "CFG_CENTER_LH2_6", + "CFG_CENTER_LOGIC_OUTS_B5_4", + "CFG_CENTER_WL1END1_4", + "CFG_CENTER_NW4A2_1", + "CFG_CENTER_SW4A2_0", + "CFG_CENTER_NE2A2_9", + "CFG_CENTER_WL1END2_2", + "CFG_CENTER_NE4BEG1_1", + "CFG_CENTER_IMUX39_6", + "CFG_CENTER_WW4C3_8", + "CFG_CENTER_IMUX7_7", + "CFG_CENTER_EE4C3_5", + "CFG_CENTER_IMUX27_0", + "CFG_CENTER_BLOCK_OUTS_B3_9", + "CFG_CENTER_SE2A0_3", + "CFG_CENTER_NW4A0_7", + "CFG_CENTER_IMUX40_8", + "CFG_CENTER_NW2A1_2", + "CFG_CENTER_EE4A2_6", + "CFG_CENTER_EE4BEG3_0", + "CFG_CENTER_SE4BEG3_0", + "CFG_CENTER_BLOCK_OUTS_B3_7", + "CFG_CENTER_LOGIC_OUTS_B10_6", + "CFG_CENTER_LOGIC_OUTS_B9_8", + "CFG_CENTER_SE4C1_8", + "CFG_CENTER_WW4C3_5", + "CFG_CENTER_BLOCK_OUTS_B2_5", + "CFG_CENTER_BYP2_0", + "CFG_CENTER_EL1BEG0_9", + "CFG_CENTER_IMUX47_3", + "CFG_CENTER_EE4C2_2", + "CFG_CENTER_LOGIC_OUTS_B16_2", + "CFG_CENTER_LOGIC_OUTS_B19_3", + "CFG_CENTER_FAN6_3", + "CFG_CENTER_LOGIC_OUTS_B7_4", + "CFG_CENTER_EE4A0_5", + "CFG_CENTER_SE4BEG2_4", + "CFG_CENTER_SW4A3_5", + "CFG_CENTER_EE2A1_7", + "CFG_CENTER_NE4BEG1_4", + "CFG_CENTER_WW4B2_6", + "CFG_CENTER_LOGIC_OUTS_B11_8", + "CFG_CENTER_LOGIC_OUTS_B22_5", + "CFG_CENTER_NE4C3_5", + "CFG_CENTER_SW2A1_3", + "CFG_CENTER_EE4B2_6", + "CFG_CENTER_SE4BEG1_9", + "CFG_CENTER_LOGIC_OUTS_B18_0", + "CFG_CENTER_EE2BEG1_6", + "CFG_CENTER_WW4C2_5", + "CFG_CENTER_NE2A3_7", + "CFG_CENTER_LOGIC_OUTS_B5_2", + "CFG_CENTER_WW2END2_2", + "CFG_CENTER_NW4A3_1", + "CFG_CENTER_NE2A0_3", + "CFG_CENTER_EE2A3_8", + "CFG_CENTER_WR1END3_9", + "CFG_CENTER_LOGIC_OUTS_B10_4", + "CFG_CENTER_WW4END2_3", + "CFG_CENTER_ER1BEG2_0", + "CFG_CENTER_IMUX27_4", + "CFG_CENTER_EE4A2_2", + "CFG_CENTER_EE2BEG0_5", + "CFG_CENTER_SE2A1_0", + "CFG_CENTER_EE4B1_0", + "CFG_CENTER_FAN7_4", + "CFG_CENTER_CTRL1_7", + "CFG_CENTER_IMUX0_1", + "CFG_CENTER_LH3_1", + "CFG_CENTER_NW4A3_7", + "CFG_CENTER_NW4A3_2", + "CFG_CENTER_NW2A0_1", + "CFG_CENTER_EE4B0_0", + "CFG_CENTER_EL1BEG2_4", + "CFG_CENTER_ER1BEG3_8", + "CFG_CENTER_IMUX0_9", + "CFG_CENTER_EE4B1_4", + "CFG_CENTER_EE4A2_5", + "CFG_CENTER_EE4C1_3", + "CFG_CENTER_WR1END3_1", + "CFG_CENTER_SE2A1_5", + "CFG_CENTER_EE4B1_1", + "CFG_CENTER_IMUX13_0", + "CFG_CENTER_WW4B0_5", + "CFG_CENTER_CTRL0_8", + "CFG_CENTER_WW4A1_3", + "CFG_CENTER_NE2A1_3", + "CFG_CENTER_WW4A0_9", + "CFG_CENTER_WW4B3_9", + "CFG_CENTER_BYP6_4", + "CFG_CENTER_IMUX16_3", + "CFG_CENTER_SE4C3_1", + "CFG_CENTER_CLK1_8", + "CFG_CENTER_SE2A2_9", + "CFG_CENTER_NW2A3_2", + "CFG_CENTER_LH9_7", + "CFG_CENTER_SE4C0_9", + "CFG_CENTER_BYP1_9", + "CFG_CENTER_WW4C1_0", + "CFG_CENTER_IMUX47_8", + "CFG_CENTER_EE4C2_1", + "CFG_CENTER_IMUX20_4", + "CFG_CENTER_IMUX1_1", + "CFG_CENTER_EE2BEG0_0", + "CFG_CENTER_CTRL1_3", + "CFG_CENTER_IMUX22_4", + "CFG_CENTER_IMUX15_4", + "CFG_CENTER_NW2A3_1", + "CFG_CENTER_IMUX33_0", + "CFG_CENTER_SE2A2_3", + "CFG_CENTER_SW2A2_5", + "CFG_CENTER_IMUX13_3", + "CFG_CENTER_IMUX34_8", + "CFG_CENTER_BYP6_1", + "CFG_CENTER_SW2A1_9", + "CFG_CENTER_ER1BEG2_6", + "CFG_CENTER_IMUX35_6", + "CFG_CENTER_EE2BEG1_1", + "CFG_CENTER_LH12_3", + "CFG_CENTER_IMUX3_7", + "CFG_CENTER_LOGIC_OUTS_B11_4", + "CFG_CENTER_IMUX18_5", + "CFG_CENTER_LH12_8", + "CFG_CENTER_NE4C1_6", + "CFG_CENTER_LOGIC_OUTS_B5_0", + "CFG_CENTER_EE4C1_2", + "CFG_CENTER_IMUX11_6", + "CFG_CENTER_BYP0_5", + "CFG_CENTER_SE2A0_0", + "CFG_CENTER_SE2A0_9", + "CFG_CENTER_SE4C2_9", + "CFG_CENTER_WR1END0_2", + "CFG_CENTER_WW4C3_9", + "CFG_CENTER_EL1BEG1_1", + "CFG_CENTER_LOGIC_OUTS_B6_3", + "CFG_CENTER_SW4END0_0", + "CFG_CENTER_IMUX19_9", + "CFG_CENTER_LOGIC_OUTS_B11_2", + "CFG_CENTER_WR1END2_5", + "CFG_CENTER_LOGIC_OUTS_B15_6", + "CFG_CENTER_CTRL0_0", + "CFG_CENTER_BYP4_8", + "CFG_CENTER_LOGIC_OUTS_B2_2", + "CFG_CENTER_SW4END0_4", + "CFG_CENTER_IMUX11_5", + "CFG_CENTER_IMUX43_9", + "CFG_CENTER_NW4END1_5", + "CFG_CENTER_WW4B0_6", + "CFG_CENTER_WR1END0_4", + "CFG_CENTER_IMUX18_0", + "CFG_CENTER_LOGIC_OUTS_B14_0", + "CFG_CENTER_LH8_7", + "CFG_CENTER_SE4C1_4", + "CFG_CENTER_CLK1_1", + "CFG_CENTER_LH1_6", + "CFG_CENTER_EE4C3_2", + "CFG_CENTER_SE4BEG0_1", + "CFG_CENTER_IMUX30_7", + "CFG_CENTER_SW2A0_9", + "CFG_CENTER_IMUX46_6", + "CFG_CENTER_LH11_6", + "CFG_CENTER_LH3_3", + "CFG_CENTER_WW2END0_3", + "CFG_CENTER_IMUX4_5", + "CFG_CENTER_WW4C3_6", + "CFG_CENTER_IMUX13_1", + "CFG_CENTER_LOGIC_OUTS_B13_9", + "CFG_CENTER_SE4C3_4", + "CFG_CENTER_WW2A1_9", + "CFG_CENTER_IMUX2_8", + "CFG_CENTER_SE2A3_2", + "CFG_CENTER_BYP7_7", + "CFG_CENTER_CLK1_7", + "CFG_CENTER_IMUX5_6", + "CFG_CENTER_EE4BEG0_1", + "CFG_CENTER_LOGIC_OUTS_B15_7", + "CFG_CENTER_LH5_5", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA29", + "CFG_CENTER_LOGIC_OUTS_B22_6", + "CFG_CENTER_NE4C3_7", + "CFG_CENTER_SW4END1_0", + "CFG_CENTER_IMUX47_6", + "CFG_CENTER_IMUX21_3", + "CFG_CENTER_NW2A0_4", + "CFG_CENTER_EL1BEG3_3", + "CFG_CENTER_SE4BEG0_7", + "CFG_CENTER_CLK0_4", + "CFG_CENTER_EFUSE_USR_EFUSEUSR12", + "CFG_CENTER_IMUX19_0", + "CFG_CENTER_IMUX27_9", + "CFG_CENTER_EL1BEG0_0", + "CFG_CENTER_IMUX28_3", + "CFG_CENTER_EE2A2_3", + "CFG_CENTER_EE2BEG0_7", + "CFG_CENTER_NW2A1_0", + "CFG_CENTER_IMUX28_9", + "CFG_CENTER_LOGIC_OUTS_B8_0", + "CFG_CENTER_EE4B0_2", + "CFG_CENTER_FAN5_3", + "CFG_CENTER_NW4A2_4", + "CFG_CENTER_LOGIC_OUTS_B21_7", + "CFG_CENTER_FAN5_2", + "CFG_CENTER_EFUSE_USR_EFUSEUSR2", + "CFG_CENTER_IMUX12_0", + "CFG_CENTER_LH12_9", + "CFG_CENTER_IMUX40_5", + "CFG_CENTER_WW4END2_9", + "CFG_CENTER_IMUX46_1", + "CFG_CENTER_BYP5_4", + "CFG_CENTER_NE4BEG0_3", + "CFG_CENTER_SE4C2_1", + "CFG_CENTER_NW4END2_7", + "CFG_CENTER_EL1BEG0_2", + "CFG_CENTER_WW2A1_7", + "CFG_CENTER_NE2A2_8", + "CFG_CENTER_CTRL1_0", + "CFG_CENTER_FAN7_9", + "CFG_CENTER_LOGIC_OUTS_B19_4", + "CFG_CENTER_EE2BEG2_1", + "CFG_CENTER_NW4A0_0", + "CFG_CENTER_LH11_1", + "CFG_CENTER_EE4BEG3_4", + "CFG_CENTER_IMUX6_1", + "CFG_CENTER_IMUX39_4", + "CFG_CENTER_SW2A0_4", + "CFG_CENTER_IMUX3_6", + "CFG_CENTER_EE2BEG1_3", + "CFG_CENTER_WW4END2_0", + "CFG_CENTER_LOGIC_OUTS_B18_9", + "CFG_CENTER_WW4A3_9", + "CFG_CENTER_IMUX25_8", + "CFG_CENTER_NE2A3_6", + "CFG_CENTER_LOGIC_OUTS_B22_2", + "CFG_CENTER_LOGIC_OUTS_B5_9", + "CFG_CENTER_IMUX8_4", + "CFG_CENTER_BLOCK_OUTS_B0_1", + "CFG_CENTER_IMUX29_8", + "CFG_CENTER_IMUX46_7", + "CFG_CENTER_EE4B0_9", + "CFG_CENTER_SW4END0_2", + "CFG_CENTER_SE4BEG1_3", + "CFG_CENTER_LOGIC_OUTS_B10_9", + "CFG_CENTER_FAN1_9", + "CFG_CENTER_DNA_PORT_DIN", + "CFG_CENTER_BYP5_6", + "CFG_CENTER_LH3_8", + "CFG_CENTER_NW4END0_5", + "CFG_CENTER_SE4C1_1", + "CFG_CENTER_EL1BEG0_4", + "CFG_CENTER_BYP1_1", + "CFG_CENTER_IMUX44_5", + "CFG_CENTER_IMUX34_3", + "CFG_CENTER_NE4C2_4", + "CFG_CENTER_BLOCK_OUTS_B0_0", + "CFG_CENTER_SW4END2_7", + "CFG_CENTER_FAN3_3", + "CFG_CENTER_IMUX8_6", + "CFG_CENTER_LH2_0", + "CFG_CENTER_ER1BEG2_7", + "CFG_CENTER_NE4C2_2", + "CFG_CENTER_WW4A1_2", + "CFG_CENTER_WW2A2_6", + "CFG_CENTER_FAN5_4", + "CFG_CENTER_IMUX24_2", + "CFG_CENTER_EE4BEG3_9", + "CFG_CENTER_NE2A1_4", + "CFG_CENTER_ER1BEG1_1", + "CFG_CENTER_SW4A1_5", + "CFG_CENTER_ER1BEG1_2", + "CFG_CENTER_IMUX28_8", + "CFG_CENTER_SW2A2_2", + "CFG_CENTER_IMUX37_0", + "CFG_CENTER_EL1BEG2_9", + "CFG_CENTER_NE4C3_3", + "CFG_CENTER_IMUX31_6", + "CFG_CENTER_WW2A3_9", + "CFG_CENTER_LOGIC_OUTS_B18_4", + "CFG_CENTER_BYP2_6", + "CFG_CENTER_SE4C1_0", + "CFG_CENTER_WW4B3_0", + "CFG_CENTER_FAN4_2", + "CFG_CENTER_IMUX35_2", + "CFG_CENTER_EFUSE_USR_EFUSEUSR28", + "CFG_CENTER_IMUX28_4", + "CFG_CENTER_NW4A0_1", + "CFG_CENTER_WW4A0_6", + "CFG_CENTER_FAN0_2", + "CFG_CENTER_IMUX17_2", + "CFG_CENTER_LH7_1", + "CFG_CENTER_WL1END2_6", + "CFG_CENTER_EE4B0_1", + "CFG_CENTER_BYP0_8", + "CFG_CENTER_NE4BEG3_3", + "CFG_CENTER_LH1_8", + "CFG_CENTER_LOGIC_OUTS_B20_6", + "CFG_CENTER_FAN7_5", + "CFG_CENTER_EE4A2_9", + "CFG_CENTER_SE4BEG0_3", + "CFG_CENTER_LH7_2", + "CFG_CENTER_IMUX27_7", + "CFG_CENTER_BYP4_4", + "CFG_CENTER_NE4C0_9", + "CFG_CENTER_IMUX4_4", + "CFG_CENTER_IMUX9_2", + "CFG_CENTER_WL1END3_4", + "CFG_CENTER_IMUX14_2", + "CFG_CENTER_EE2A3_3", + "CFG_CENTER_IMUX42_1", + "CFG_CENTER_NW2A3_4", + "CFG_CENTER_SE2A1_8", + "CFG_CENTER_ER1BEG1_3", + "CFG_CENTER_LH12_1", + "CFG_CENTER_EE4C0_8", + "CFG_CENTER_NW2A1_6", + "CFG_CENTER_FAN1_8", + "CFG_CENTER_WW4END0_5", + "CFG_CENTER_IMUX22_9", + "CFG_CENTER_EE4BEG2_6", + "CFG_CENTER_NW2A1_5", + "CFG_CENTER_IMUX9_1", + "CFG_CENTER_SW4END0_3", + "CFG_CENTER_WL1END3_6", + "CFG_CENTER_EE4B2_2", + "CFG_CENTER_SE4BEG0_4", + "CFG_CENTER_EE4A2_7", + "CFG_CENTER_LOGIC_OUTS_B5_3", + "CFG_CENTER_WW4C3_4", + "CFG_CENTER_WW2END3_8", + "CFG_CENTER_NW4END1_9", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA27", + "CFG_CENTER_FAN3_4", + "CFG_CENTER_EE4C0_4", + "CFG_CENTER_LOGIC_OUTS_B1_4", + "CFG_CENTER_IMUX35_3", + "CFG_CENTER_WW4END3_8", + "CFG_CENTER_EL1BEG3_9", + "CFG_CENTER_NE2A1_0", + "CFG_CENTER_LOGIC_OUTS_B0_5", + "CFG_CENTER_SW4A2_4", + "CFG_CENTER_IMUX9_8", + "CFG_CENTER_WW4B2_5", + "CFG_CENTER_EE4A0_8", + "CFG_CENTER_IMUX15_9", + "CFG_CENTER_WW4B3_4", + "CFG_CENTER_NE4C1_3", + "CFG_CENTER_NW2A3_8", + "CFG_CENTER_LH7_6", + "CFG_CENTER_FAN0_5", + "CFG_CENTER_WL1END3_8", + "CFG_CENTER_EE2A0_5", + "CFG_CENTER_LH7_4", + "CFG_CENTER_WW2END3_2", + "CFG_CENTER_WR1END3_5", + "CFG_CENTER_BYP5_9", + "CFG_CENTER_IMUX47_0", + "CFG_CENTER_WL1END2_3", + "CFG_CENTER_LOGIC_OUTS_B12_3", + "CFG_CENTER_LH2_7", + "CFG_CENTER_EE2BEG0_4", + "CFG_CENTER_EL1BEG1_6", + "CFG_CENTER_NE4BEG0_5", + "CFG_CENTER_LH7_5", + "CFG_CENTER_IMUX34_2", + "CFG_CENTER_LH4_7", + "CFG_CENTER_BYP7_6", + "CFG_CENTER_LH4_6", + "CFG_CENTER_IMUX3_9", + "CFG_CENTER_SE4BEG2_7", + "CFG_CENTER_IMUX31_7", + "CFG_CENTER_NW4END2_0", + "CFG_CENTER_WW2A0_2", + "CFG_CENTER_EE4BEG0_5", + "CFG_CENTER_EE4A1_4", + "CFG_CENTER_EE2A0_1", + "CFG_CENTER_BYP1_2", + "CFG_CENTER_IMUX23_0", + "CFG_CENTER_NE4C1_7", + "CFG_CENTER_CTRL0_6", + "CFG_CENTER_ER1BEG2_5", + "CFG_CENTER_WW2A3_3", + "CFG_CENTER_IMUX33_7", + "CFG_CENTER_NE4C1_8", + "CFG_CENTER_WW4C1_7", + "CFG_CENTER_FAN6_1", + "CFG_CENTER_SW4A2_3", + "CFG_CENTER_SE4BEG1_5", + "CFG_CENTER_CLK0_6", + "CFG_CENTER_IMUX42_7", + "CFG_CENTER_WW4A2_5", + "CFG_CENTER_LOGIC_OUTS_B0_8", + "CFG_CENTER_WW4B3_2", + "CFG_CENTER_SW2A2_3", + "CFG_CENTER_IMUX17_1", + "CFG_CENTER_IMUX18_7", + "CFG_CENTER_LOGIC_OUTS_B6_7", + "CFG_CENTER_WR1END2_0", + "CFG_CENTER_SE2A3_5", + "CFG_CENTER_IMUX6_4", + "CFG_CENTER_NW4END1_8", + "CFG_CENTER_IMUX22_7", + "CFG_CENTER_NW4END0_1", + "CFG_CENTER_EFUSE_USR_EFUSEUSR22", + "CFG_CENTER_FAN2_0", + "CFG_CENTER_EE4A3_3", + "CFG_CENTER_IMUX7_1", + "CFG_CENTER_IMUX25_6", + "CFG_CENTER_WW4B0_2", + "CFG_CENTER_NW4END1_3", + "CFG_CENTER_WW4B0_0", + "CFG_CENTER_BYP5_0", + "CFG_CENTER_NE4C2_7", + "CFG_CENTER_WW4END2_4", + "CFG_CENTER_ER1BEG0_7", + "CFG_CENTER_EE2BEG2_4", + "CFG_CENTER_FAN2_4", + "CFG_CENTER_WW4C2_8", + "CFG_CENTER_BLOCK_OUTS_B2_1", + "CFG_CENTER_IMUX23_3", + "CFG_CENTER_BYP2_5", + "CFG_CENTER_EE2BEG2_9", + "CFG_CENTER_LOGIC_OUTS_B15_8", + "CFG_CENTER_WW4A1_1", + "CFG_CENTER_IMUX21_7", + "CFG_CENTER_IMUX31_9", + "CFG_CENTER_LOGIC_OUTS_B10_3", + "CFG_CENTER_WW4C3_1", + "CFG_CENTER_CTRL0_4", + "CFG_CENTER_EFUSE_USR_EFUSEUSR16", + "CFG_CENTER_EL1BEG3_6", + "CFG_CENTER_CTRL1_6", + "CFG_CENTER_ER1BEG1_5", + "CFG_CENTER_BLOCK_OUTS_B1_0", + "CFG_CENTER_IMUX45_0", + "CFG_CENTER_WL1END1_6", + "CFG_CENTER_IMUX1_4", + "CFG_CENTER_IMUX17_8", + "CFG_CENTER_EE2BEG1_4", + "CFG_CENTER_EE2A0_8", + "CFG_CENTER_EE4C1_1", + "CFG_CENTER_ER1BEG3_9", + "CFG_CENTER_IMUX29_4", + "CFG_CENTER_WL1END0_1", + "CFG_CENTER_IMUX20_0", + "CFG_CENTER_LH10_9", + "CFG_CENTER_SW4A0_3", + "CFG_CENTER_IMUX46_8", + "CFG_CENTER_WW4C1_1", + "CFG_CENTER_SE2A3_0", + "CFG_CENTER_IMUX1_6", + "CFG_CENTER_WW4A3_4", + "CFG_CENTER_LH5_2", + "CFG_CENTER_LOGIC_OUTS_B8_3", + "CFG_CENTER_NE4C3_4", + "CFG_CENTER_IMUX6_3", + "CFG_CENTER_LOGIC_OUTS_B19_5", + "CFG_CENTER_NW2A3_3", + "CFG_CENTER_IMUX41_5", + "CFG_CENTER_WR1END0_3", + "CFG_CENTER_FAN0_8", + "CFG_CENTER_SW4A0_7", + "CFG_CENTER_WW4END1_6", + "CFG_CENTER_EE4C1_9", + "CFG_CENTER_NE4BEG0_9", + "CFG_CENTER_LH3_9", + "CFG_CENTER_NW2A0_9", + "CFG_CENTER_WW4B1_4", + "CFG_CENTER_IMUX32_1", + "CFG_CENTER_FAN7_0", + "CFG_CENTER_SW4END1_9", + "CFG_CENTER_LOGIC_OUTS_B0_2", + "CFG_CENTER_FAN2_2", + "CFG_CENTER_IMUX33_5", + "CFG_CENTER_BYP0_3", + "CFG_CENTER_IMUX14_8", + "CFG_CENTER_LH2_8", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA14", + "CFG_CENTER_EE4C2_9", + "CFG_CENTER_LH6_4", + "CFG_CENTER_SW2A3_1", + "CFG_CENTER_WR1END3_6", + "CFG_CENTER_SW4A1_7", + "CFG_CENTER_WR1END3_8", + "CFG_CENTER_IMUX13_7", + "CFG_CENTER_NE2A0_0", + "CFG_CENTER_LOGIC_OUTS_B11_1", + "CFG_CENTER_BYP4_1", + "CFG_CENTER_IMUX22_8", + "CFG_CENTER_IMUX31_0", + "CFG_CENTER_BYP6_8", + "CFG_CENTER_SE2A0_8", + "CFG_CENTER_FAN6_4", + "CFG_CENTER_NE4BEG1_0", + "CFG_CENTER_SW4END2_6", + "CFG_CENTER_WW4END2_5", + "CFG_CENTER_NW4END0_3", + "CFG_CENTER_IMUX39_5", + "CFG_CENTER_BYP7_8", + "CFG_CENTER_EFUSE_USR_EFUSEUSR0", + "CFG_CENTER_LOGIC_OUTS_B2_3", + "CFG_CENTER_LOGIC_OUTS_B19_9", + "CFG_CENTER_SW4A2_2", + "CFG_CENTER_IMUX13_9", + "CFG_CENTER_LOGIC_OUTS_B9_6", + "CFG_CENTER_BYP0_7", + "CFG_CENTER_NW4A2_5", + "CFG_CENTER_LH9_0", + "CFG_CENTER_WL1END1_7", + "CFG_CENTER_SW4END2_1", + "CFG_CENTER_IMUX40_1", + "CFG_CENTER_ER1BEG2_2", + "CFG_CENTER_DNA_PORT_SHIFT", + "CFG_CENTER_WW4END3_3", + "CFG_CENTER_EE4BEG2_5", + "CFG_CENTER_BYP5_1", + "CFG_CENTER_FAN1_1", + "CFG_CENTER_NE4BEG3_8", + "CFG_CENTER_IMUX26_2", + "CFG_CENTER_IMUX45_4", + "CFG_CENTER_IMUX12_6", + "CFG_CENTER_LOGIC_OUTS_B17_5", + "CFG_CENTER_LH2_3", + "CFG_CENTER_SW4END3_5", + "CFG_CENTER_NW4A2_2", + "CFG_CENTER_NW4A3_5", + "CFG_CENTER_WW2END1_3", + "CFG_CENTER_IMUX32_9", + "CFG_CENTER_EE4C1_0", + "CFG_CENTER_SE2A1_2", + "CFG_CENTER_LH7_3", + "CFG_CENTER_EE2BEG1_8", + "CFG_CENTER_LH12_5", + "CFG_CENTER_LOGIC_OUTS_B16_3", + "CFG_CENTER_FAN6_5", + "CFG_CENTER_SW4END1_1", + "CFG_CENTER_SW2A3_4", + "CFG_CENTER_FAN0_3", + "CFG_CENTER_IMUX37_2", + "CFG_CENTER_IMUX7_5", + "CFG_CENTER_EE4B3_9", + "CFG_CENTER_IMUX1_3", + "CFG_CENTER_WL1END1_5", + "CFG_CENTER_IMUX47_2", + "CFG_CENTER_IMUX26_9", + "CFG_CENTER_IMUX37_7", + "CFG_CENTER_NE4BEG3_2", + "CFG_CENTER_FAN1_5", + "CFG_CENTER_LH3_6", + "CFG_CENTER_EE2A2_1", + "CFG_CENTER_IMUX12_5", + "CFG_CENTER_IMUX22_6", + "CFG_CENTER_IMUX4_9", + "CFG_CENTER_ER1BEG0_5", + "CFG_CENTER_IMUX36_4", + "CFG_CENTER_EE4B2_1", + "CFG_CENTER_EE4C1_6", + "CFG_CENTER_EE2A2_0", + "CFG_CENTER_NE4C0_1", + "CFG_CENTER_WW4END2_6", + "CFG_CENTER_SW4END1_2", + "CFG_CENTER_BLOCK_OUTS_B2_2", + "CFG_CENTER_SE2A1_9", + "CFG_CENTER_IMUX26_6", + "CFG_CENTER_EE2A1_6", + "CFG_CENTER_NE2A1_2", + "CFG_CENTER_EE4A3_4", + "CFG_CENTER_NE4BEG3_1", + "CFG_CENTER_SE4C1_9", + "CFG_CENTER_IMUX38_4", + "CFG_CENTER_SW4A0_2", + "CFG_CENTER_SW4END2_5", + "CFG_CENTER_CLK0_1", + "CFG_CENTER_FAN7_3", + "CFG_CENTER_IMUX37_6", + "CFG_CENTER_LOGIC_OUTS_B4_5", + "CFG_CENTER_WW2A3_0", + "CFG_CENTER_IMUX47_9", + "CFG_CENTER_EE2BEG2_7", + "CFG_CENTER_EFUSE_USR_EFUSEUSR27", + "CFG_CENTER_NW2A0_8", + "CFG_CENTER_LOGIC_OUTS_B8_9", + "CFG_CENTER_IMUX4_3", + "CFG_CENTER_IMUX16_5", + "CFG_CENTER_EE4BEG1_1", + "CFG_CENTER_ER1BEG1_7", + "CFG_CENTER_NW2A2_5", + "CFG_CENTER_SE2A0_5", + "CFG_CENTER_WW4END0_2", + "CFG_CENTER_EE4C1_8", + "CFG_CENTER_FAN6_7", + "CFG_CENTER_BYP3_4", + "CFG_CENTER_NW2A2_8", + "CFG_CENTER_LH2_5", + "CFG_CENTER_LOGIC_OUTS_B3_0", + "CFG_CENTER_EE2BEG2_6", + "CFG_CENTER_LH8_0", + "CFG_CENTER_FAN0_6", + "CFG_CENTER_IMUX39_8", + "CFG_CENTER_IMUX7_9", + "CFG_CENTER_ER1BEG3_4", + "CFG_CENTER_LOGIC_OUTS_B15_2", + "CFG_CENTER_IMUX33_4", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA31", + "CFG_CENTER_IMUX20_9", + "CFG_CENTER_SW2A1_6", + "CFG_CENTER_WW2END1_8", + "CFG_CENTER_LOGIC_OUTS_B11_3", + "CFG_CENTER_WW4A3_0", + "CFG_CENTER_EE2A3_0", + "CFG_CENTER_LH5_6", + "CFG_CENTER_NE4C3_2", + "CFG_CENTER_NW4A3_9", + "CFG_CENTER_NE2A0_8", + "CFG_CENTER_EE4B1_2", + "CFG_CENTER_BYP3_2", + "CFG_CENTER_EFUSE_USR_EFUSEUSR19", + "CFG_CENTER_SE4BEG3_6", + "CFG_CENTER_NE4C0_7", + "CFG_CENTER_FAN5_0", + "CFG_CENTER_IMUX25_4", + "CFG_CENTER_LOGIC_OUTS_B23_7", + "CFG_CENTER_BLOCK_OUTS_B1_6", + "CFG_CENTER_FAN7_2", + "CFG_CENTER_NE4BEG2_6", + "CFG_CENTER_BLOCK_OUTS_B2_4", + "CFG_CENTER_NE2A3_3", + "CFG_CENTER_BYP2_4", + "CFG_CENTER_LOGIC_OUTS_B17_8", + "CFG_CENTER_IMUX10_2", + "CFG_CENTER_CTRL0_7", + "CFG_CENTER_FAN3_8", + "CFG_CENTER_WW4C3_2", + "CFG_CENTER_WW2A2_5", + "CFG_CENTER_IMUX25_1", + "CFG_CENTER_IMUX26_4", + "CFG_CENTER_WW4B2_9", + "CFG_CENTER_BLOCK_OUTS_B3_3", + "CFG_CENTER_EE4A2_3", + "CFG_CENTER_FAN3_7", + "CFG_CENTER_EE2A2_9", + "CFG_CENTER_EE2A0_0", + "CFG_CENTER_WW2A3_1", + "CFG_CENTER_IMUX43_5", + "CFG_CENTER_EE2A1_5", + "CFG_CENTER_EL1BEG2_6", + "CFG_CENTER_LOGIC_OUTS_B3_2", + "CFG_CENTER_SE4C3_0", + "CFG_CENTER_NW2A2_6", + "CFG_CENTER_IMUX1_8", + "CFG_CENTER_IMUX31_2", + "CFG_CENTER_NE4BEG1_7", + "CFG_CENTER_LOGIC_OUTS_B0_3", + "CFG_CENTER_IMUX3_3", + "CFG_CENTER_ER1BEG3_0", + "CFG_CENTER_WW4C2_4", + "CFG_CENTER_WW4A0_3", + "CFG_CENTER_BYP4_9", + "CFG_CENTER_SE2A1_7", + "CFG_CENTER_LH10_6" + ], + "pips": { + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR6->CFG_CENTER_LOGIC_OUTS_B22_6": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR6", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR29->CFG_CENTER_LOGIC_OUTS_B21_9": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR29", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR7->CFG_CENTER_LOGIC_OUTS_B23_6": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR7", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_IMUX41_5->CFG_CENTER_DNA_PORT_READ": { + "src_wire": "CFG_CENTER_IMUX41_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_DNA_PORT_READ", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR13->CFG_CENTER_LOGIC_OUTS_B21_7": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR13", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR18->CFG_CENTER_LOGIC_OUTS_B18_8": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR18", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR0->CFG_CENTER_LOGIC_OUTS_B16_6": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR0", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR3->CFG_CENTER_LOGIC_OUTS_B19_6": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR3", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR9->CFG_CENTER_LOGIC_OUTS_B17_7": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR9", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR27->CFG_CENTER_LOGIC_OUTS_B19_9": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR27", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR28->CFG_CENTER_LOGIC_OUTS_B20_9": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR28", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR22->CFG_CENTER_LOGIC_OUTS_B22_8": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR22", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR12->CFG_CENTER_LOGIC_OUTS_B20_7": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR12", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR16->CFG_CENTER_LOGIC_OUTS_B16_8": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR16", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR14->CFG_CENTER_LOGIC_OUTS_B22_7": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR14", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR24->CFG_CENTER_LOGIC_OUTS_B16_9": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR24", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR11->CFG_CENTER_LOGIC_OUTS_B19_7": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR11", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR5->CFG_CENTER_LOGIC_OUTS_B21_6": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_CLK1_0->CFG_CENTER_TOP_ICAP1_CLK": { + "src_wire": "CFG_CENTER_CLK1_0", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_TOP_ICAP1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR10->CFG_CENTER_LOGIC_OUTS_B18_7": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR10", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR23->CFG_CENTER_LOGIC_OUTS_B23_8": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR23", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR26->CFG_CENTER_LOGIC_OUTS_B18_9": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR26", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR4->CFG_CENTER_LOGIC_OUTS_B20_6": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR4", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR8->CFG_CENTER_LOGIC_OUTS_B16_7": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR8", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR31->CFG_CENTER_LOGIC_OUTS_B23_9": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR31", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_TOP_DNA_PORT_CLK->CFG_CENTER_DNA_PORT_CLK": { + "src_wire": "CFG_CENTER_TOP_DNA_PORT_CLK", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_DNA_PORT_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_DNA_PORT_DOUT->CFG_CENTER_LOGIC_OUTS_B23_5": { + "src_wire": "CFG_CENTER_DNA_PORT_DOUT", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_5", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR15->CFG_CENTER_LOGIC_OUTS_B23_7": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR15", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_7", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR17->CFG_CENTER_LOGIC_OUTS_B17_8": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR17", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR19->CFG_CENTER_LOGIC_OUTS_B19_8": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR19", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_IMUX43_5->CFG_CENTER_DNA_PORT_DIN": { + "src_wire": "CFG_CENTER_IMUX43_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_DNA_PORT_DIN", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR25->CFG_CENTER_LOGIC_OUTS_B17_9": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR25", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR20->CFG_CENTER_LOGIC_OUTS_B20_8": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR20", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_IMUX42_5->CFG_CENTER_DNA_PORT_SHIFT": { + "src_wire": "CFG_CENTER_IMUX42_5", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_DNA_PORT_SHIFT", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR30->CFG_CENTER_LOGIC_OUTS_B22_9": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR30", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_9", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR21->CFG_CENTER_LOGIC_OUTS_B21_8": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR21", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_8", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR2->CFG_CENTER_LOGIC_OUTS_B18_6": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR2", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_6", + "is_directional": "1", + "can_invert": "0" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR1->CFG_CENTER_LOGIC_OUTS_B17_6": { + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_6", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CLBLL_L.json b/kintex7/tile_type_CLBLL_L.json new file mode 100644 index 0000000..528e23e --- /dev/null +++ b/kintex7/tile_type_CLBLL_L.json @@ -0,0 +1,1449 @@ +{ + "tile_type": "CLBLL_L", + "sites": [ + { + "y_coord": 0, + "name": "X1Y0", + "prefix": "SLICE", + "type": "SLICEL", + "site_pins": { + "BX": "CLBLL_L_BX", + "A3": "CLBLL_L_A3", + "D": "CLBLL_L_D", + "C": "CLBLL_L_C", + "DQ": "CLBLL_L_DQ", + "B2": "CLBLL_L_B2", + "C6": "CLBLL_L_C6", + "A2": "CLBLL_L_A2", + "SR": "CLBLL_L_SR", + "B6": "CLBLL_L_B6", + "D6": "CLBLL_L_D6", + "A5": "CLBLL_L_A5", + "B": "CLBLL_L_B", + "A4": "CLBLL_L_A4", + "B4": "CLBLL_L_B4", + "A6": "CLBLL_L_A6", + "C2": "CLBLL_L_C2", + "AQ": "CLBLL_L_AQ", + "A": "CLBLL_L_A", + "BQ": "CLBLL_L_BQ", + "D3": "CLBLL_L_D3", + "B1": "CLBLL_L_B1", + "COUT": "CLBLL_L_COUT", + "D4": "CLBLL_L_D4", + "AMUX": "CLBLL_L_AMUX", + "DMUX": "CLBLL_L_DMUX", + "AX": "CLBLL_L_AX", + "C1": "CLBLL_L_C1", + "C5": "CLBLL_L_C5", + "DX": "CLBLL_L_DX", + "CX": "CLBLL_L_CX", + "C3": "CLBLL_L_C3", + "CMUX": "CLBLL_L_CMUX", + "A1": "CLBLL_L_A1", + "D2": "CLBLL_L_D2", + "CQ": "CLBLL_L_CQ", + "CLK": "CLBLL_L_CLK", + "CIN": "CLBLL_L_CIN", + "BMUX": "CLBLL_L_BMUX", + "B3": "CLBLL_L_B3", + "D5": "CLBLL_L_D5", + "D1": "CLBLL_L_D1", + "CE": "CLBLL_L_CE", + "B5": "CLBLL_L_B5", + "C4": "CLBLL_L_C4" + }, + "x_coord": 1 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "SLICE", + "type": "SLICEL", + "site_pins": { + "BX": "CLBLL_LL_BX", + "A3": "CLBLL_LL_A3", + "D": "CLBLL_LL_D", + "C": "CLBLL_LL_C", + "DQ": "CLBLL_LL_DQ", + "B2": "CLBLL_LL_B2", + "C6": "CLBLL_LL_C6", + "A2": "CLBLL_LL_A2", + "SR": "CLBLL_LL_SR", + "B6": "CLBLL_LL_B6", + "D6": "CLBLL_LL_D6", + "A5": "CLBLL_LL_A5", + "B": "CLBLL_LL_B", + "A4": "CLBLL_LL_A4", + "B4": "CLBLL_LL_B4", + "A6": "CLBLL_LL_A6", + "C2": "CLBLL_LL_C2", + "AQ": "CLBLL_LL_AQ", + "A": "CLBLL_LL_A", + "BQ": "CLBLL_LL_BQ", + "D3": "CLBLL_LL_D3", + "B1": "CLBLL_LL_B1", + "COUT": "CLBLL_LL_COUT", + "D4": "CLBLL_LL_D4", + "AMUX": "CLBLL_LL_AMUX", + "DMUX": "CLBLL_LL_DMUX", + "AX": "CLBLL_LL_AX", + "C1": "CLBLL_LL_C1", + "C5": "CLBLL_LL_C5", + "DX": "CLBLL_LL_DX", + "CX": "CLBLL_LL_CX", + "C3": "CLBLL_LL_C3", + "CMUX": "CLBLL_LL_CMUX", + "A1": "CLBLL_LL_A1", + "D2": "CLBLL_LL_D2", + "CQ": "CLBLL_LL_CQ", + "CLK": "CLBLL_LL_CLK", + "CIN": "CLBLL_LL_CIN", + "BMUX": "CLBLL_LL_BMUX", + "B3": "CLBLL_LL_B3", + "D5": "CLBLL_LL_D5", + "D1": "CLBLL_LL_D1", + "CE": "CLBLL_LL_CE", + "B5": "CLBLL_LL_B5", + "C4": "CLBLL_LL_C4" + }, + "x_coord": 0 + } + ], + "wires": [ + "CLBLL_SE4BEG2", + "CLBLL_WR1END0", + "CLBLL_LH2", + "CLBLL_IMUX15", + "CLBLL_LL_CQ", + "CLBLL_SW4A2", + "CLBLL_LL_D4", + "CLBLL_IMUX16", + "CLBLL_SW4END0", + "CLBLL_LH11", + "CLBLL_L_B2", + "CLBLL_L_AX", + "CLBLL_LH8", + "CLBLL_MONITOR_N", + "CLBLL_NE2A1", + "CLBLL_WW4END2", + "CLBLL_LOGIC_OUTS20", + "CLBLL_IMUX3", + "CLBLL_SW4A1", + "CLBLL_IMUX17", + "CLBLL_LH7", + "CLBLL_L_CQ", + "CLBLL_L_B5", + "CLBLL_SE4BEG1", + "CLBLL_LL_COUT", + "CLBLL_LL_C3", + "CLBLL_SE4C2", + "CLBLL_LL_A6", + "CLBLL_IMUX38", + "CLBLL_LL_CIN", + "CLBLL_LL_COUT_N", + "CLBLL_L_AQ", + "CLBLL_EL1BEG1", + "CLBLL_WW4END3", + "CLBLL_L_DMUX", + "CLBLL_FAN1", + "CLBLL_L_D", + "CLBLL_IMUX30", + "CLBLL_LL_B1", + "CLBLL_WW4C3", + "CLBLL_IMUX6", + "CLBLL_LL_CE", + "CLBLL_EE4B1", + "CLBLL_SW2A2", + "CLBLL_CTRL1", + "CLBLL_LL_B", + "CLBLL_IMUX46", + "CLBLL_EL1BEG3", + "CLBLL_NE4C1", + "CLBLL_EE4B3", + "CLBLL_EE4A3", + "CLBLL_IMUX29", + "CLBLL_LOGIC_OUTS14", + "CLBLL_L_BQ", + "CLBLL_L_D2", + "CLBLL_SE4C1", + "CLBLL_WW4A2", + "CLBLL_WW2END0", + "CLBLL_LL_A1", + "CLBLL_L_DX", + "CLBLL_LL_A2", + "CLBLL_EE2A0", + "CLBLL_NE2A0", + "CLBLL_WW2END2", + "CLBLL_L_C4", + "CLBLL_EL1BEG0", + "CLBLL_WW2A2", + "CLBLL_LL_D", + "CLBLL_L_D3", + "CLBLL_LL_B2", + "CLBLL_SW2A0", + "CLBLL_L_A3", + "CLBLL_LL_D1", + "CLBLL_IMUX8", + "CLBLL_NW4END1", + "CLBLL_SW4END3", + "CLBLL_EE4C1", + "CLBLL_L_B1", + "CLBLL_IMUX14", + "CLBLL_L_B", + "CLBLL_L_D1", + "CLBLL_L_D6", + "CLBLL_NE4C2", + "CLBLL_LL_BQ", + "CLBLL_WW4B3", + "CLBLL_NE4BEG3", + "CLBLL_L_COUT_N", + "CLBLL_IMUX26", + "CLBLL_LH4", + "CLBLL_FAN3", + "CLBLL_NW4END2", + "CLBLL_NW4END3", + "CLBLL_NW4A0", + "CLBLL_EE4C0", + "CLBLL_EE4C3", + "CLBLL_NW4END0", + "CLBLL_LH6", + "CLBLL_LL_A3", + "CLBLL_LL_DX", + "CLBLL_WW2END3", + "CLBLL_NE4BEG0", + "CLBLL_SW2A1", + "CLBLL_NE4C0", + "CLBLL_L_A5", + "CLBLL_WW2END1", + "CLBLL_IMUX45", + "CLBLL_WW4B0", + "CLBLL_LL_AX", + "CLBLL_CTRL0", + "CLBLL_IMUX40", + "CLBLL_LL_B3", + "CLBLL_EE4BEG2", + "CLBLL_EE2A3", + "CLBLL_LL_C1", + "CLBLL_WW4A3", + "CLBLL_LOGIC_OUTS11", + "CLBLL_IMUX7", + "CLBLL_WW4END1", + "CLBLL_IMUX31", + "CLBLL_L_CIN", + "CLBLL_IMUX21", + "CLBLL_SE2A2", + "CLBLL_FAN4", + "CLBLL_LOGIC_OUTS2", + "CLBLL_FAN5", + "CLBLL_LOGIC_OUTS23", + "CLBLL_NW4A2", + "CLBLL_IMUX24", + "CLBLL_L_CX", + "CLBLL_LL_C5", + "CLBLL_LL_A5", + "CLBLL_SE2A3", + "CLBLL_WW2A0", + "CLBLL_NE4BEG2", + "CLBLL_IMUX36", + "CLBLL_WL1END1", + "CLBLL_L_C", + "CLBLL_L_C5", + "CLBLL_L_CLK", + "CLBLL_WW4C2", + "CLBLL_LOGIC_OUTS7", + "CLBLL_FAN2", + "CLBLL_L_CE", + "CLBLL_IMUX33", + "CLBLL_WW4END0", + "CLBLL_WR1END2", + "CLBLL_LL_B6", + "CLBLL_LOGIC_OUTS1", + "CLBLL_EE4B0", + "CLBLL_WW4B1", + "CLBLL_BYP6", + "CLBLL_L_D5", + "CLBLL_EE4BEG3", + "CLBLL_BYP1", + "CLBLL_NW4A1", + "CLBLL_WL1END0", + "CLBLL_LL_D5", + "CLBLL_L_BMUX", + "CLBLL_BYP5", + "CLBLL_IMUX25", + "CLBLL_ER1BEG3", + "CLBLL_NW4A3", + "CLBLL_EE2BEG3", + "CLBLL_NW2A1", + "CLBLL_LL_CX", + "CLBLL_WW4B2", + "CLBLL_L_C3", + "CLBLL_EE2BEG2", + "CLBLL_IMUX5", + "CLBLL_LL_D6", + "CLBLL_WW2A3", + "CLBLL_L_A1", + "CLBLL_LL_D2", + "CLBLL_L_SR", + "CLBLL_IMUX39", + "CLBLL_LOGIC_OUTS6", + "CLBLL_LOGIC_OUTS16", + "CLBLL_WW4A1", + "CLBLL_LH9", + "CLBLL_L_AMUX", + "CLBLL_LL_A4", + "CLBLL_BYP4", + "CLBLL_LH5", + "CLBLL_WW4A0", + "CLBLL_L_BX", + "CLBLL_L_C1", + "CLBLL_L_B6", + "CLBLL_NE4C3", + "CLBLL_WL1END2", + "CLBLL_IMUX44", + "CLBLL_LOGIC_OUTS5", + "CLBLL_LOGIC_OUTS12", + "CLBLL_LH1", + "CLBLL_EE2BEG0", + "CLBLL_LL_CMUX", + "CLBLL_LOGIC_OUTS9", + "CLBLL_IMUX27", + "CLBLL_NW2A0", + "CLBLL_LL_B4", + "CLBLL_IMUX4", + "CLBLL_EE2A2", + "CLBLL_L_C2", + "CLBLL_L_A4", + "CLBLL_ER1BEG1", + "CLBLL_WW4C0", + "CLBLL_LH10", + "CLBLL_L_A6", + "CLBLL_LOGIC_OUTS18", + "CLBLL_IMUX1", + "CLBLL_IMUX22", + "CLBLL_IMUX13", + "CLBLL_IMUX20", + "CLBLL_LOGIC_OUTS4", + "CLBLL_IMUX23", + "CLBLL_LOGIC_OUTS22", + "CLBLL_SW4END2", + "CLBLL_IMUX42", + "CLBLL_IMUX11", + "CLBLL_LOGIC_OUTS17", + "CLBLL_NE2A3", + "CLBLL_L_C6", + "CLBLL_SW2A3", + "CLBLL_LL_C6", + "CLBLL_EE4B2", + "CLBLL_FAN7", + "CLBLL_SE4C3", + "CLBLL_LL_AQ", + "CLBLL_L_D4", + "CLBLL_L_B4", + "CLBLL_NW2A3", + "CLBLL_NW2A2", + "CLBLL_LL_CLK", + "CLBLL_MONITOR_P", + "CLBLL_EE4BEG1", + "CLBLL_EE2A1", + "CLBLL_BYP3", + "CLBLL_LL_B5", + "CLBLL_LL_C4", + "CLBLL_LL_D3", + "CLBLL_WR1END1", + "CLBLL_LL_DMUX", + "CLBLL_IMUX43", + "CLBLL_LL_A", + "CLBLL_L_A", + "CLBLL_IMUX12", + "CLBLL_IMUX41", + "CLBLL_LH12", + "CLBLL_L_DQ", + "CLBLL_WR1END3", + "CLBLL_LOGIC_OUTS21", + "CLBLL_IMUX19", + "CLBLL_IMUX2", + "CLBLL_EE4A2", + "CLBLL_SE4C0", + "CLBLL_FAN0", + "CLBLL_BYP2", + "CLBLL_BYP0", + "CLBLL_BYP7", + "CLBLL_FAN6", + "CLBLL_LL_AMUX", + "CLBLL_LH3", + "CLBLL_LOGIC_OUTS8", + "CLBLL_ER1BEG0", + "CLBLL_WW4C1", + "CLBLL_LL_C", + "CLBLL_SW4A3", + "CLBLL_LL_BX", + "CLBLL_EE4A0", + "CLBLL_IMUX35", + "CLBLL_LOGIC_OUTS0", + "CLBLL_IMUX18", + "CLBLL_IMUX37", + "CLBLL_LOGIC_OUTS15", + "CLBLL_EE4BEG0", + "CLBLL_L_B3", + "CLBLL_SE4BEG0", + "CLBLL_SE2A1", + "CLBLL_IMUX32", + "CLBLL_SE2A0", + "CLBLL_SE4BEG3", + "CLBLL_EE4A1", + "CLBLL_EL1BEG2", + "CLBLL_LOGIC_OUTS13", + "CLBLL_IMUX9", + "CLBLL_LL_DQ", + "CLBLL_LL_SR", + "CLBLL_EE4C2", + "CLBLL_ER1BEG2", + "CLBLL_NE2A2", + "CLBLL_IMUX28", + "CLBLL_IMUX10", + "CLBLL_L_A2", + "CLBLL_L_COUT", + "CLBLL_CLK1", + "CLBLL_IMUX47", + "CLBLL_LL_BMUX", + "CLBLL_CLK0", + "CLBLL_LOGIC_OUTS10", + "CLBLL_NE4BEG1", + "CLBLL_L_CMUX", + "CLBLL_LL_C2", + "CLBLL_WL1END3", + "CLBLL_WW2A1", + "CLBLL_IMUX34", + "CLBLL_IMUX0", + "CLBLL_SW4A0", + "CLBLL_SW4END1", + "CLBLL_LOGIC_OUTS3", + "CLBLL_LOGIC_OUTS19", + "CLBLL_EE2BEG1" + ], + "pips": { + "CLBLL_L.CLBLL_IMUX11->CLBLL_LL_A4": { + "src_wire": "CLBLL_IMUX11", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX3->CLBLL_L_A2": { + "src_wire": "CLBLL_IMUX3", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_D6->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D6", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_B5->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B5", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_CMUX->CLBLL_LOGIC_OUTS18": { + "src_wire": "CLBLL_L_CMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS18", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_B2->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B2", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_BYP3->CLBLL_LL_CX": { + "src_wire": "CLBLL_BYP3", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_CX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_D1->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_C4->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C4", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_A2->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A2", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_C5->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C5", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX24->CLBLL_LL_B5": { + "src_wire": "CLBLL_IMUX24", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_DMUX->CLBLL_LOGIC_OUTS23": { + "src_wire": "CLBLL_LL_DMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS23", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX43->CLBLL_LL_D6": { + "src_wire": "CLBLL_IMUX43", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_C5->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C5", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_BQ->CLBLL_LOGIC_OUTS1": { + "src_wire": "CLBLL_L_BQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX39->CLBLL_L_D3": { + "src_wire": "CLBLL_IMUX39", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX33->CLBLL_L_C1": { + "src_wire": "CLBLL_IMUX33", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_COUT->>CLBLL_LL_DMUX": { + "src_wire": "CLBLL_LL_COUT", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX16->CLBLL_L_B3": { + "src_wire": "CLBLL_IMUX16", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_A4->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A4", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_C->>CLBLL_LL_CMUX": { + "src_wire": "CLBLL_LL_C", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_CMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX17->CLBLL_LL_B3": { + "src_wire": "CLBLL_IMUX17", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX22->CLBLL_LL_C3": { + "src_wire": "CLBLL_IMUX22", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_B->>CLBLL_L_BMUX": { + "src_wire": "CLBLL_L_B", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_BMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_B4->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B4", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_CTRL1->CLBLL_LL_SR": { + "src_wire": "CLBLL_CTRL1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_SR", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_AQ->CLBLL_LOGIC_OUTS0": { + "src_wire": "CLBLL_L_AQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS0", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_B->CLBLL_LOGIC_OUTS9": { + "src_wire": "CLBLL_L_B", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS9", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_A1->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_A6->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A6", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX28->CLBLL_LL_C4": { + "src_wire": "CLBLL_IMUX28", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX45->CLBLL_LL_D2": { + "src_wire": "CLBLL_IMUX45", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_FAN7->CLBLL_LL_CE": { + "src_wire": "CLBLL_FAN7", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_CE", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_C6->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C6", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX34->CLBLL_L_C6": { + "src_wire": "CLBLL_IMUX34", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_C->>CLBLL_L_CMUX": { + "src_wire": "CLBLL_L_C", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_CMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_C3->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C3", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX26->CLBLL_L_B4": { + "src_wire": "CLBLL_IMUX26", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX4->CLBLL_LL_A6": { + "src_wire": "CLBLL_IMUX4", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX8->CLBLL_LL_A5": { + "src_wire": "CLBLL_IMUX8", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_B3->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B3", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_A1->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX38->CLBLL_LL_D3": { + "src_wire": "CLBLL_IMUX38", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_A->>CLBLL_L_AMUX": { + "src_wire": "CLBLL_L_A", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_AMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_BYP4->CLBLL_LL_BX": { + "src_wire": "CLBLL_BYP4", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_BX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX47->CLBLL_LL_D5": { + "src_wire": "CLBLL_IMUX47", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_A6->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A6", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_C6->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C6", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX18->CLBLL_LL_B2": { + "src_wire": "CLBLL_IMUX18", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_C4->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C4", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX0->CLBLL_L_A3": { + "src_wire": "CLBLL_IMUX0", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_D5->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D5", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_C3->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C3", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX42->CLBLL_L_D6": { + "src_wire": "CLBLL_IMUX42", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_D->CLBLL_LOGIC_OUTS15": { + "src_wire": "CLBLL_LL_D", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS15", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX1->CLBLL_LL_A3": { + "src_wire": "CLBLL_IMUX1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_D4->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D4", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX36->CLBLL_L_D2": { + "src_wire": "CLBLL_IMUX36", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_DQ->CLBLL_LOGIC_OUTS3": { + "src_wire": "CLBLL_L_DQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_AMUX->CLBLL_LOGIC_OUTS20": { + "src_wire": "CLBLL_LL_AMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS20", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX5->CLBLL_L_A6": { + "src_wire": "CLBLL_IMUX5", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX12->CLBLL_LL_B6": { + "src_wire": "CLBLL_IMUX12", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX9->CLBLL_L_A5": { + "src_wire": "CLBLL_IMUX9", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX20->CLBLL_L_C2": { + "src_wire": "CLBLL_IMUX20", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_C->CLBLL_LOGIC_OUTS14": { + "src_wire": "CLBLL_LL_C", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS14", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX37->CLBLL_L_D4": { + "src_wire": "CLBLL_IMUX37", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_CTRL0->CLBLL_L_SR": { + "src_wire": "CLBLL_CTRL0", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_SR", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_B5->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B5", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX19->CLBLL_L_B2": { + "src_wire": "CLBLL_IMUX19", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX14->CLBLL_L_B1": { + "src_wire": "CLBLL_IMUX14", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_A5->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A5", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_A4->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A4", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_C1->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_BYP6->CLBLL_LL_DX": { + "src_wire": "CLBLL_BYP6", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_DX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX46->CLBLL_L_D5": { + "src_wire": "CLBLL_IMUX46", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX31->CLBLL_LL_C5": { + "src_wire": "CLBLL_IMUX31", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_A3->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A3", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_A5->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A5", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX13->CLBLL_L_B6": { + "src_wire": "CLBLL_IMUX13", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_B6->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B6", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_BYP1->CLBLL_LL_AX": { + "src_wire": "CLBLL_BYP1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_AX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_B4->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B4", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_A->CLBLL_LOGIC_OUTS8": { + "src_wire": "CLBLL_L_A", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS8", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_D1->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_CLK1->CLBLL_LL_CLK": { + "src_wire": "CLBLL_CLK1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX35->CLBLL_LL_C6": { + "src_wire": "CLBLL_IMUX35", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_BYP2->CLBLL_L_CX": { + "src_wire": "CLBLL_BYP2", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_CX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_D6->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D6", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX2->CLBLL_LL_A2": { + "src_wire": "CLBLL_IMUX2", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_CQ->CLBLL_LOGIC_OUTS6": { + "src_wire": "CLBLL_LL_CQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_CMUX->CLBLL_LOGIC_OUTS22": { + "src_wire": "CLBLL_LL_CMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS22", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_B1->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_A3->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A3", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX15->CLBLL_LL_B1": { + "src_wire": "CLBLL_IMUX15", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_D5->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D5", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_C->CLBLL_LOGIC_OUTS10": { + "src_wire": "CLBLL_L_C", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS10", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX25->CLBLL_L_B5": { + "src_wire": "CLBLL_IMUX25", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX23->CLBLL_L_C3": { + "src_wire": "CLBLL_IMUX23", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_COUT->CLBLL_LL_COUT_N": { + "src_wire": "CLBLL_LL_COUT", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_COUT_N", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_DMUX->CLBLL_LOGIC_OUTS19": { + "src_wire": "CLBLL_L_DMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS19", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_AMUX->CLBLL_LOGIC_OUTS16": { + "src_wire": "CLBLL_L_AMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS16", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_D->CLBLL_LOGIC_OUTS11": { + "src_wire": "CLBLL_L_D", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS11", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_DQ->CLBLL_LOGIC_OUTS7": { + "src_wire": "CLBLL_LL_DQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS7", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX29->CLBLL_LL_C2": { + "src_wire": "CLBLL_IMUX29", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_B->>CLBLL_LL_BMUX": { + "src_wire": "CLBLL_LL_B", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_BMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_D4->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D4", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_A->>CLBLL_LL_AMUX": { + "src_wire": "CLBLL_LL_A", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_AMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_B1->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX27->CLBLL_LL_B4": { + "src_wire": "CLBLL_IMUX27", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_C2->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C2", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX32->CLBLL_LL_C1": { + "src_wire": "CLBLL_IMUX32", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_B->CLBLL_LOGIC_OUTS13": { + "src_wire": "CLBLL_LL_B", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS13", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_D3->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D3", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_CLK0->CLBLL_L_CLK": { + "src_wire": "CLBLL_CLK0", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_FAN6->CLBLL_L_CE": { + "src_wire": "CLBLL_FAN6", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_CE", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_BYP7->CLBLL_L_DX": { + "src_wire": "CLBLL_BYP7", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_DX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX44->CLBLL_LL_D4": { + "src_wire": "CLBLL_IMUX44", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_A->CLBLL_LOGIC_OUTS12": { + "src_wire": "CLBLL_LL_A", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS12", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX7->CLBLL_LL_A1": { + "src_wire": "CLBLL_IMUX7", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX6->CLBLL_L_A1": { + "src_wire": "CLBLL_IMUX6", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_BYP0->CLBLL_L_AX": { + "src_wire": "CLBLL_BYP0", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_AX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_COUT->>CLBLL_L_DMUX": { + "src_wire": "CLBLL_L_COUT", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_B2->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B2", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_BMUX->CLBLL_LOGIC_OUTS21": { + "src_wire": "CLBLL_LL_BMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS21", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_COUT->CLBLL_L_COUT_N": { + "src_wire": "CLBLL_L_COUT", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_COUT_N", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX30->CLBLL_L_C5": { + "src_wire": "CLBLL_IMUX30", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_AQ->CLBLL_LOGIC_OUTS4": { + "src_wire": "CLBLL_LL_AQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_D3->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D3", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_BQ->CLBLL_LOGIC_OUTS5": { + "src_wire": "CLBLL_LL_BQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_B6->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B6", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_B3->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B3", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_D2->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D2", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_D->>CLBLL_L_DMUX": { + "src_wire": "CLBLL_L_D", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX41->CLBLL_L_D1": { + "src_wire": "CLBLL_IMUX41", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_A2->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A2", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX21->CLBLL_L_C4": { + "src_wire": "CLBLL_IMUX21", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_C1->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX10->CLBLL_L_A4": { + "src_wire": "CLBLL_IMUX10", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_IMUX40->CLBLL_LL_D1": { + "src_wire": "CLBLL_IMUX40", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_D2->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D2", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_LL_D->>CLBLL_LL_DMUX": { + "src_wire": "CLBLL_LL_D", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_BYP5->CLBLL_L_BX": { + "src_wire": "CLBLL_BYP5", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_BX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_CQ->CLBLL_LOGIC_OUTS2": { + "src_wire": "CLBLL_L_CQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_BMUX->CLBLL_LOGIC_OUTS17": { + "src_wire": "CLBLL_L_BMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS17", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_L.CLBLL_L_C2->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C2", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CLBLL_R.json b/kintex7/tile_type_CLBLL_R.json new file mode 100644 index 0000000..ddb02df --- /dev/null +++ b/kintex7/tile_type_CLBLL_R.json @@ -0,0 +1,1449 @@ +{ + "tile_type": "CLBLL_R", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "SLICE", + "type": "SLICEL", + "site_pins": { + "BX": "CLBLL_LL_BX", + "A3": "CLBLL_LL_A3", + "D": "CLBLL_LL_D", + "C": "CLBLL_LL_C", + "DQ": "CLBLL_LL_DQ", + "B2": "CLBLL_LL_B2", + "C6": "CLBLL_LL_C6", + "A2": "CLBLL_LL_A2", + "SR": "CLBLL_LL_SR", + "B6": "CLBLL_LL_B6", + "D6": "CLBLL_LL_D6", + "A5": "CLBLL_LL_A5", + "B": "CLBLL_LL_B", + "A4": "CLBLL_LL_A4", + "B4": "CLBLL_LL_B4", + "A6": "CLBLL_LL_A6", + "C2": "CLBLL_LL_C2", + "AQ": "CLBLL_LL_AQ", + "A": "CLBLL_LL_A", + "BQ": "CLBLL_LL_BQ", + "D3": "CLBLL_LL_D3", + "B1": "CLBLL_LL_B1", + "COUT": "CLBLL_LL_COUT", + "D4": "CLBLL_LL_D4", + "AMUX": "CLBLL_LL_AMUX", + "DMUX": "CLBLL_LL_DMUX", + "AX": "CLBLL_LL_AX", + "C1": "CLBLL_LL_C1", + "C5": "CLBLL_LL_C5", + "DX": "CLBLL_LL_DX", + "CX": "CLBLL_LL_CX", + "C3": "CLBLL_LL_C3", + "CMUX": "CLBLL_LL_CMUX", + "A1": "CLBLL_LL_A1", + "D2": "CLBLL_LL_D2", + "CQ": "CLBLL_LL_CQ", + "CLK": "CLBLL_LL_CLK", + "CIN": "CLBLL_LL_CIN", + "BMUX": "CLBLL_LL_BMUX", + "B3": "CLBLL_LL_B3", + "D5": "CLBLL_LL_D5", + "D1": "CLBLL_LL_D1", + "CE": "CLBLL_LL_CE", + "B5": "CLBLL_LL_B5", + "C4": "CLBLL_LL_C4" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X1Y0", + "prefix": "SLICE", + "type": "SLICEL", + "site_pins": { + "BX": "CLBLL_L_BX", + "A3": "CLBLL_L_A3", + "D": "CLBLL_L_D", + "C": "CLBLL_L_C", + "DQ": "CLBLL_L_DQ", + "B2": "CLBLL_L_B2", + "C6": "CLBLL_L_C6", + "A2": "CLBLL_L_A2", + "SR": "CLBLL_L_SR", + "B6": "CLBLL_L_B6", + "D6": "CLBLL_L_D6", + "A5": "CLBLL_L_A5", + "B": "CLBLL_L_B", + "A4": "CLBLL_L_A4", + "B4": "CLBLL_L_B4", + "A6": "CLBLL_L_A6", + "C2": "CLBLL_L_C2", + "AQ": "CLBLL_L_AQ", + "A": "CLBLL_L_A", + "BQ": "CLBLL_L_BQ", + "D3": "CLBLL_L_D3", + "B1": "CLBLL_L_B1", + "COUT": "CLBLL_L_COUT", + "D4": "CLBLL_L_D4", + "AMUX": "CLBLL_L_AMUX", + "DMUX": "CLBLL_L_DMUX", + "AX": "CLBLL_L_AX", + "C1": "CLBLL_L_C1", + "C5": "CLBLL_L_C5", + "DX": "CLBLL_L_DX", + "CX": "CLBLL_L_CX", + "C3": "CLBLL_L_C3", + "CMUX": "CLBLL_L_CMUX", + "A1": "CLBLL_L_A1", + "D2": "CLBLL_L_D2", + "CQ": "CLBLL_L_CQ", + "CLK": "CLBLL_L_CLK", + "CIN": "CLBLL_L_CIN", + "BMUX": "CLBLL_L_BMUX", + "B3": "CLBLL_L_B3", + "D5": "CLBLL_L_D5", + "D1": "CLBLL_L_D1", + "CE": "CLBLL_L_CE", + "B5": "CLBLL_L_B5", + "C4": "CLBLL_L_C4" + }, + "x_coord": 1 + } + ], + "wires": [ + "CLBLL_SE4BEG2", + "CLBLL_WR1END0", + "CLBLL_LH2", + "CLBLL_IMUX15", + "CLBLL_LL_CQ", + "CLBLL_SW4A2", + "CLBLL_LL_D4", + "CLBLL_IMUX16", + "CLBLL_SW4END0", + "CLBLL_LH11", + "CLBLL_L_B2", + "CLBLL_L_AX", + "CLBLL_LH8", + "CLBLL_MONITOR_N", + "CLBLL_NE2A1", + "CLBLL_WW4END2", + "CLBLL_LOGIC_OUTS20", + "CLBLL_IMUX3", + "CLBLL_SW4A1", + "CLBLL_IMUX17", + "CLBLL_LH7", + "CLBLL_L_CQ", + "CLBLL_L_B5", + "CLBLL_SE4BEG1", + "CLBLL_LL_COUT", + "CLBLL_LL_C3", + "CLBLL_SE4C2", + "CLBLL_LL_A6", + "CLBLL_IMUX38", + "CLBLL_LL_CIN", + "CLBLL_LL_COUT_N", + "CLBLL_L_AQ", + "CLBLL_EL1BEG1", + "CLBLL_WW4END3", + "CLBLL_L_DMUX", + "CLBLL_FAN1", + "CLBLL_L_D", + "CLBLL_IMUX30", + "CLBLL_LL_B1", + "CLBLL_WW4C3", + "CLBLL_IMUX6", + "CLBLL_LL_CE", + "CLBLL_EE4B1", + "CLBLL_SW2A2", + "CLBLL_CTRL1", + "CLBLL_LL_B", + "CLBLL_IMUX46", + "CLBLL_EL1BEG3", + "CLBLL_NE4C1", + "CLBLL_EE4B3", + "CLBLL_EE4A3", + "CLBLL_IMUX29", + "CLBLL_LOGIC_OUTS14", + "CLBLL_L_BQ", + "CLBLL_L_D2", + "CLBLL_SE4C1", + "CLBLL_WW4A2", + "CLBLL_WW2END0", + "CLBLL_LL_A1", + "CLBLL_L_DX", + "CLBLL_LL_A2", + "CLBLL_EE2A0", + "CLBLL_NE2A0", + "CLBLL_WW2END2", + "CLBLL_L_C4", + "CLBLL_EL1BEG0", + "CLBLL_WW2A2", + "CLBLL_LL_D", + "CLBLL_L_D3", + "CLBLL_LL_B2", + "CLBLL_SW2A0", + "CLBLL_L_A3", + "CLBLL_LL_D1", + "CLBLL_IMUX8", + "CLBLL_NW4END1", + "CLBLL_SW4END3", + "CLBLL_EE4C1", + "CLBLL_L_B1", + "CLBLL_IMUX14", + "CLBLL_L_B", + "CLBLL_L_D1", + "CLBLL_L_D6", + "CLBLL_NE4C2", + "CLBLL_LL_BQ", + "CLBLL_WW4B3", + "CLBLL_NE4BEG3", + "CLBLL_L_COUT_N", + "CLBLL_IMUX26", + "CLBLL_LH4", + "CLBLL_FAN3", + "CLBLL_NW4END2", + "CLBLL_NW4END3", + "CLBLL_NW4A0", + "CLBLL_EE4C0", + "CLBLL_EE4C3", + "CLBLL_NW4END0", + "CLBLL_LH6", + "CLBLL_LL_A3", + "CLBLL_LL_DX", + "CLBLL_WW2END3", + "CLBLL_NE4BEG0", + "CLBLL_SW2A1", + "CLBLL_NE4C0", + "CLBLL_L_A5", + "CLBLL_WW2END1", + "CLBLL_IMUX45", + "CLBLL_WW4B0", + "CLBLL_LL_AX", + "CLBLL_CTRL0", + "CLBLL_IMUX40", + "CLBLL_LL_B3", + "CLBLL_EE4BEG2", + "CLBLL_EE2A3", + "CLBLL_LL_C1", + "CLBLL_WW4A3", + "CLBLL_LOGIC_OUTS11", + "CLBLL_IMUX7", + "CLBLL_WW4END1", + "CLBLL_IMUX31", + "CLBLL_L_CIN", + "CLBLL_IMUX21", + "CLBLL_SE2A2", + "CLBLL_FAN4", + "CLBLL_LOGIC_OUTS2", + "CLBLL_FAN5", + "CLBLL_LOGIC_OUTS23", + "CLBLL_NW4A2", + "CLBLL_IMUX24", + "CLBLL_L_CX", + "CLBLL_LL_C5", + "CLBLL_LL_A5", + "CLBLL_SE2A3", + "CLBLL_WW2A0", + "CLBLL_NE4BEG2", + "CLBLL_IMUX36", + "CLBLL_WL1END1", + "CLBLL_L_C", + "CLBLL_L_C5", + "CLBLL_L_CLK", + "CLBLL_WW4C2", + "CLBLL_LOGIC_OUTS7", + "CLBLL_FAN2", + "CLBLL_L_CE", + "CLBLL_IMUX33", + "CLBLL_WW4END0", + "CLBLL_WR1END2", + "CLBLL_LL_B6", + "CLBLL_LOGIC_OUTS1", + "CLBLL_EE4B0", + "CLBLL_WW4B1", + "CLBLL_BYP6", + "CLBLL_L_D5", + "CLBLL_EE4BEG3", + "CLBLL_BYP1", + "CLBLL_NW4A1", + "CLBLL_WL1END0", + "CLBLL_LL_D5", + "CLBLL_L_BMUX", + "CLBLL_BYP5", + "CLBLL_IMUX25", + "CLBLL_ER1BEG3", + "CLBLL_NW4A3", + "CLBLL_EE2BEG3", + "CLBLL_NW2A1", + "CLBLL_LL_CX", + "CLBLL_WW4B2", + "CLBLL_L_C3", + "CLBLL_EE2BEG2", + "CLBLL_IMUX5", + "CLBLL_LL_D6", + "CLBLL_WW2A3", + "CLBLL_L_A1", + "CLBLL_LL_D2", + "CLBLL_L_SR", + "CLBLL_IMUX39", + "CLBLL_LOGIC_OUTS6", + "CLBLL_LOGIC_OUTS16", + "CLBLL_WW4A1", + "CLBLL_LH9", + "CLBLL_L_AMUX", + "CLBLL_LL_A4", + "CLBLL_BYP4", + "CLBLL_LH5", + "CLBLL_WW4A0", + "CLBLL_L_BX", + "CLBLL_L_C1", + "CLBLL_L_B6", + "CLBLL_NE4C3", + "CLBLL_WL1END2", + "CLBLL_IMUX44", + "CLBLL_LOGIC_OUTS5", + "CLBLL_LOGIC_OUTS12", + "CLBLL_LH1", + "CLBLL_EE2BEG0", + "CLBLL_LL_CMUX", + "CLBLL_LOGIC_OUTS9", + "CLBLL_IMUX27", + "CLBLL_NW2A0", + "CLBLL_LL_B4", + "CLBLL_IMUX4", + "CLBLL_EE2A2", + "CLBLL_L_C2", + "CLBLL_L_A4", + "CLBLL_ER1BEG1", + "CLBLL_WW4C0", + "CLBLL_LH10", + "CLBLL_L_A6", + "CLBLL_LOGIC_OUTS18", + "CLBLL_IMUX1", + "CLBLL_IMUX22", + "CLBLL_IMUX13", + "CLBLL_IMUX20", + "CLBLL_LOGIC_OUTS4", + "CLBLL_IMUX23", + "CLBLL_LOGIC_OUTS22", + "CLBLL_SW4END2", + "CLBLL_IMUX42", + "CLBLL_IMUX11", + "CLBLL_LOGIC_OUTS17", + "CLBLL_NE2A3", + "CLBLL_L_C6", + "CLBLL_SW2A3", + "CLBLL_LL_C6", + "CLBLL_EE4B2", + "CLBLL_FAN7", + "CLBLL_SE4C3", + "CLBLL_LL_AQ", + "CLBLL_L_D4", + "CLBLL_L_B4", + "CLBLL_NW2A3", + "CLBLL_NW2A2", + "CLBLL_LL_CLK", + "CLBLL_MONITOR_P", + "CLBLL_EE4BEG1", + "CLBLL_EE2A1", + "CLBLL_BYP3", + "CLBLL_LL_B5", + "CLBLL_LL_C4", + "CLBLL_LL_D3", + "CLBLL_WR1END1", + "CLBLL_LL_DMUX", + "CLBLL_IMUX43", + "CLBLL_LL_A", + "CLBLL_L_A", + "CLBLL_IMUX12", + "CLBLL_IMUX41", + "CLBLL_LH12", + "CLBLL_L_DQ", + "CLBLL_WR1END3", + "CLBLL_LOGIC_OUTS21", + "CLBLL_IMUX19", + "CLBLL_IMUX2", + "CLBLL_EE4A2", + "CLBLL_SE4C0", + "CLBLL_FAN0", + "CLBLL_BYP2", + "CLBLL_BYP0", + "CLBLL_BYP7", + "CLBLL_FAN6", + "CLBLL_LL_AMUX", + "CLBLL_LH3", + "CLBLL_LOGIC_OUTS8", + "CLBLL_ER1BEG0", + "CLBLL_WW4C1", + "CLBLL_LL_C", + "CLBLL_SW4A3", + "CLBLL_LL_BX", + "CLBLL_EE4A0", + "CLBLL_IMUX35", + "CLBLL_LOGIC_OUTS0", + "CLBLL_IMUX18", + "CLBLL_IMUX37", + "CLBLL_LOGIC_OUTS15", + "CLBLL_EE4BEG0", + "CLBLL_L_B3", + "CLBLL_SE4BEG0", + "CLBLL_SE2A1", + "CLBLL_IMUX32", + "CLBLL_SE2A0", + "CLBLL_SE4BEG3", + "CLBLL_EE4A1", + "CLBLL_EL1BEG2", + "CLBLL_LOGIC_OUTS13", + "CLBLL_IMUX9", + "CLBLL_LL_DQ", + "CLBLL_LL_SR", + "CLBLL_EE4C2", + "CLBLL_ER1BEG2", + "CLBLL_NE2A2", + "CLBLL_IMUX28", + "CLBLL_IMUX10", + "CLBLL_L_A2", + "CLBLL_L_COUT", + "CLBLL_CLK1", + "CLBLL_IMUX47", + "CLBLL_LL_BMUX", + "CLBLL_CLK0", + "CLBLL_LOGIC_OUTS10", + "CLBLL_NE4BEG1", + "CLBLL_L_CMUX", + "CLBLL_LL_C2", + "CLBLL_WL1END3", + "CLBLL_WW2A1", + "CLBLL_IMUX34", + "CLBLL_IMUX0", + "CLBLL_SW4A0", + "CLBLL_SW4END1", + "CLBLL_LOGIC_OUTS3", + "CLBLL_LOGIC_OUTS19", + "CLBLL_EE2BEG1" + ], + "pips": { + "CLBLL_R.CLBLL_LL_BMUX->CLBLL_LOGIC_OUTS21": { + "src_wire": "CLBLL_LL_BMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS21", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX37->CLBLL_L_D4": { + "src_wire": "CLBLL_IMUX37", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_D2->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D2", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX15->CLBLL_LL_B1": { + "src_wire": "CLBLL_IMUX15", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_C->CLBLL_LOGIC_OUTS14": { + "src_wire": "CLBLL_LL_C", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS14", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_A4->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A4", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_B1->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_C->>CLBLL_L_CMUX": { + "src_wire": "CLBLL_L_C", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_CMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_A4->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A4", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_D1->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_BMUX->CLBLL_LOGIC_OUTS17": { + "src_wire": "CLBLL_L_BMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS17", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_B2->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B2", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX29->CLBLL_LL_C2": { + "src_wire": "CLBLL_IMUX29", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX3->CLBLL_L_A2": { + "src_wire": "CLBLL_IMUX3", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_A2->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A2", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX21->CLBLL_L_C4": { + "src_wire": "CLBLL_IMUX21", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_DMUX->CLBLL_LOGIC_OUTS19": { + "src_wire": "CLBLL_L_DMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS19", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_D4->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D4", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX39->CLBLL_L_D3": { + "src_wire": "CLBLL_IMUX39", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX18->CLBLL_LL_B2": { + "src_wire": "CLBLL_IMUX18", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_D3->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D3", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_C1->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_D1->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_B1->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_AMUX->CLBLL_LOGIC_OUTS16": { + "src_wire": "CLBLL_L_AMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS16", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_C6->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C6", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_D6->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D6", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_A6->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A6", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_A5->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A5", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_BYP5->CLBLL_L_BX": { + "src_wire": "CLBLL_BYP5", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_BX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX44->CLBLL_LL_D4": { + "src_wire": "CLBLL_IMUX44", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_CMUX->CLBLL_LOGIC_OUTS22": { + "src_wire": "CLBLL_LL_CMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS22", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_B->CLBLL_LOGIC_OUTS9": { + "src_wire": "CLBLL_L_B", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS9", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_C2->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C2", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX1->CLBLL_LL_A3": { + "src_wire": "CLBLL_IMUX1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_CQ->CLBLL_LOGIC_OUTS2": { + "src_wire": "CLBLL_L_CQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX30->CLBLL_L_C5": { + "src_wire": "CLBLL_IMUX30", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX2->CLBLL_LL_A2": { + "src_wire": "CLBLL_IMUX2", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX16->CLBLL_L_B3": { + "src_wire": "CLBLL_IMUX16", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX41->CLBLL_L_D1": { + "src_wire": "CLBLL_IMUX41", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX45->CLBLL_LL_D2": { + "src_wire": "CLBLL_IMUX45", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX26->CLBLL_L_B4": { + "src_wire": "CLBLL_IMUX26", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_DQ->CLBLL_LOGIC_OUTS7": { + "src_wire": "CLBLL_LL_DQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS7", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_A2->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A2", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX7->CLBLL_LL_A1": { + "src_wire": "CLBLL_IMUX7", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_B3->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B3", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_A6->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A6", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_BYP0->CLBLL_L_AX": { + "src_wire": "CLBLL_BYP0", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_AX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX6->CLBLL_L_A1": { + "src_wire": "CLBLL_IMUX6", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_A->CLBLL_LOGIC_OUTS12": { + "src_wire": "CLBLL_LL_A", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS12", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_D->CLBLL_LOGIC_OUTS11": { + "src_wire": "CLBLL_L_D", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS11", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX23->CLBLL_L_C3": { + "src_wire": "CLBLL_IMUX23", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX33->CLBLL_L_C1": { + "src_wire": "CLBLL_IMUX33", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_B->CLBLL_LOGIC_OUTS13": { + "src_wire": "CLBLL_LL_B", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS13", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_FAN6->CLBLL_L_CE": { + "src_wire": "CLBLL_FAN6", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_CE", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX42->CLBLL_L_D6": { + "src_wire": "CLBLL_IMUX42", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_C4->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C4", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX4->CLBLL_LL_A6": { + "src_wire": "CLBLL_IMUX4", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_CTRL0->CLBLL_L_SR": { + "src_wire": "CLBLL_CTRL0", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_SR", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX11->CLBLL_LL_A4": { + "src_wire": "CLBLL_IMUX11", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_D5->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D5", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX20->CLBLL_L_C2": { + "src_wire": "CLBLL_IMUX20", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX13->CLBLL_L_B6": { + "src_wire": "CLBLL_IMUX13", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_CLK1->CLBLL_LL_CLK": { + "src_wire": "CLBLL_CLK1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_BYP4->CLBLL_LL_BX": { + "src_wire": "CLBLL_BYP4", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_BX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_C5->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C5", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_AMUX->CLBLL_LOGIC_OUTS20": { + "src_wire": "CLBLL_LL_AMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS20", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_C->CLBLL_LOGIC_OUTS10": { + "src_wire": "CLBLL_L_C", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS10", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_BYP6->CLBLL_LL_DX": { + "src_wire": "CLBLL_BYP6", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_DX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_COUT->>CLBLL_LL_DMUX": { + "src_wire": "CLBLL_LL_COUT", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_B6->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B6", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_BQ->CLBLL_LOGIC_OUTS5": { + "src_wire": "CLBLL_LL_BQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_A3->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A3", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_BYP7->CLBLL_L_DX": { + "src_wire": "CLBLL_BYP7", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_DX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX5->CLBLL_L_A6": { + "src_wire": "CLBLL_IMUX5", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_D->CLBLL_LOGIC_OUTS15": { + "src_wire": "CLBLL_LL_D", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS15", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_CLK0->CLBLL_L_CLK": { + "src_wire": "CLBLL_CLK0", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_C5->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C5", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX32->CLBLL_LL_C1": { + "src_wire": "CLBLL_IMUX32", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_C->>CLBLL_LL_CMUX": { + "src_wire": "CLBLL_LL_C", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_CMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_D5->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D5", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_DQ->CLBLL_LOGIC_OUTS3": { + "src_wire": "CLBLL_L_DQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_B4->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B4", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX10->CLBLL_L_A4": { + "src_wire": "CLBLL_IMUX10", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_B->>CLBLL_LL_BMUX": { + "src_wire": "CLBLL_LL_B", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_BMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_A1->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_D6->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D6", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_B4->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B4", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX46->CLBLL_L_D5": { + "src_wire": "CLBLL_IMUX46", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX38->CLBLL_LL_D3": { + "src_wire": "CLBLL_IMUX38", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX34->CLBLL_L_C6": { + "src_wire": "CLBLL_IMUX34", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_A5->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A5", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX22->CLBLL_LL_C3": { + "src_wire": "CLBLL_IMUX22", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_D->>CLBLL_L_DMUX": { + "src_wire": "CLBLL_L_D", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_COUT->CLBLL_LL_COUT_N": { + "src_wire": "CLBLL_LL_COUT", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_COUT_N", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_D->>CLBLL_LL_DMUX": { + "src_wire": "CLBLL_LL_D", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX25->CLBLL_L_B5": { + "src_wire": "CLBLL_IMUX25", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX40->CLBLL_LL_D1": { + "src_wire": "CLBLL_IMUX40", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_B5->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B5", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_COUT->>CLBLL_L_DMUX": { + "src_wire": "CLBLL_L_COUT", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_C3->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C3", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_CTRL1->CLBLL_LL_SR": { + "src_wire": "CLBLL_CTRL1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_SR", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_D4->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D4", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX9->CLBLL_L_A5": { + "src_wire": "CLBLL_IMUX9", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_C6->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C6", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX24->CLBLL_LL_B5": { + "src_wire": "CLBLL_IMUX24", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX43->CLBLL_LL_D6": { + "src_wire": "CLBLL_IMUX43", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX47->CLBLL_LL_D5": { + "src_wire": "CLBLL_IMUX47", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_BYP1->CLBLL_LL_AX": { + "src_wire": "CLBLL_BYP1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_AX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_C2->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C2", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX36->CLBLL_L_D2": { + "src_wire": "CLBLL_IMUX36", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX8->CLBLL_LL_A5": { + "src_wire": "CLBLL_IMUX8", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX14->CLBLL_L_B1": { + "src_wire": "CLBLL_IMUX14", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_C3->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C3", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_BYP2->CLBLL_L_CX": { + "src_wire": "CLBLL_BYP2", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_CX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX28->CLBLL_LL_C4": { + "src_wire": "CLBLL_IMUX28", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_B6->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B6", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX27->CLBLL_LL_B4": { + "src_wire": "CLBLL_IMUX27", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_A->>CLBLL_L_AMUX": { + "src_wire": "CLBLL_L_A", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_AMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_C4->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C4", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_CQ->CLBLL_LOGIC_OUTS6": { + "src_wire": "CLBLL_LL_CQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX17->CLBLL_LL_B3": { + "src_wire": "CLBLL_IMUX17", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX12->CLBLL_LL_B6": { + "src_wire": "CLBLL_IMUX12", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX35->CLBLL_LL_C6": { + "src_wire": "CLBLL_IMUX35", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_B3->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B3", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_A->CLBLL_LOGIC_OUTS8": { + "src_wire": "CLBLL_L_A", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS8", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_FAN7->CLBLL_LL_CE": { + "src_wire": "CLBLL_FAN7", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_CE", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_A3->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A3", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX31->CLBLL_LL_C5": { + "src_wire": "CLBLL_IMUX31", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_B2->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B2", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_B5->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B5", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_C1->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_D2->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D2", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_BQ->CLBLL_LOGIC_OUTS1": { + "src_wire": "CLBLL_L_BQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_CMUX->CLBLL_LOGIC_OUTS18": { + "src_wire": "CLBLL_L_CMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS18", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX0->CLBLL_L_A3": { + "src_wire": "CLBLL_IMUX0", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_B->>CLBLL_L_BMUX": { + "src_wire": "CLBLL_L_B", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_BMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_COUT->CLBLL_L_COUT_N": { + "src_wire": "CLBLL_L_COUT", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_COUT_N", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_IMUX19->CLBLL_L_B2": { + "src_wire": "CLBLL_IMUX19", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_D3->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D3", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_A->>CLBLL_LL_AMUX": { + "src_wire": "CLBLL_LL_A", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_AMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_BYP3->CLBLL_LL_CX": { + "src_wire": "CLBLL_BYP3", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_CX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_A1->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_DMUX->CLBLL_LOGIC_OUTS23": { + "src_wire": "CLBLL_LL_DMUX", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS23", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_LL_AQ->CLBLL_LOGIC_OUTS4": { + "src_wire": "CLBLL_LL_AQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLL_R.CLBLL_L_AQ->CLBLL_LOGIC_OUTS0": { + "src_wire": "CLBLL_L_AQ", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS0", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CLBLM_L.json b/kintex7/tile_type_CLBLM_L.json new file mode 100644 index 0000000..e145e9b --- /dev/null +++ b/kintex7/tile_type_CLBLM_L.json @@ -0,0 +1,1494 @@ +{ + "tile_type": "CLBLM_L", + "sites": [ + { + "y_coord": 0, + "name": "X1Y0", + "prefix": "SLICE", + "type": "SLICEL", + "site_pins": { + "BX": "CLBLM_L_BX", + "A3": "CLBLM_L_A3", + "D": "CLBLM_L_D", + "C": "CLBLM_L_C", + "DQ": "CLBLM_L_DQ", + "B2": "CLBLM_L_B2", + "C6": "CLBLM_L_C6", + "A2": "CLBLM_L_A2", + "SR": "CLBLM_L_SR", + "B6": "CLBLM_L_B6", + "D6": "CLBLM_L_D6", + "A5": "CLBLM_L_A5", + "B": "CLBLM_L_B", + "A4": "CLBLM_L_A4", + "B4": "CLBLM_L_B4", + "A6": "CLBLM_L_A6", + "C2": "CLBLM_L_C2", + "AQ": "CLBLM_L_AQ", + "A": "CLBLM_L_A", + "BQ": "CLBLM_L_BQ", + "D3": "CLBLM_L_D3", + "B1": "CLBLM_L_B1", + "COUT": "CLBLM_L_COUT", + "D4": "CLBLM_L_D4", + "AMUX": "CLBLM_L_AMUX", + "DMUX": "CLBLM_L_DMUX", + "AX": "CLBLM_L_AX", + "C1": "CLBLM_L_C1", + "C5": "CLBLM_L_C5", + "DX": "CLBLM_L_DX", + "CX": "CLBLM_L_CX", + "C3": "CLBLM_L_C3", + "CMUX": "CLBLM_L_CMUX", + "A1": "CLBLM_L_A1", + "D2": "CLBLM_L_D2", + "CQ": "CLBLM_L_CQ", + "CLK": "CLBLM_L_CLK", + "CIN": "CLBLM_L_CIN", + "BMUX": "CLBLM_L_BMUX", + "B3": "CLBLM_L_B3", + "D5": "CLBLM_L_D5", + "D1": "CLBLM_L_D1", + "CE": "CLBLM_L_CE", + "B5": "CLBLM_L_B5", + "C4": "CLBLM_L_C4" + }, + "x_coord": 1 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "SLICE", + "type": "SLICEM", + "site_pins": { + "BX": "CLBLM_M_BX", + "A3": "CLBLM_M_A3", + "D": "CLBLM_M_D", + "C": "CLBLM_M_C", + "DQ": "CLBLM_M_DQ", + "B2": "CLBLM_M_B2", + "C6": "CLBLM_M_C6", + "COUT": "CLBLM_M_COUT", + "A2": "CLBLM_M_A2", + "SR": "CLBLM_M_SR", + "AI": "CLBLM_M_AI", + "B6": "CLBLM_M_B6", + "BI": "CLBLM_M_BI", + "D6": "CLBLM_M_D6", + "A5": "CLBLM_M_A5", + "B": "CLBLM_M_B", + "A4": "CLBLM_M_A4", + "B4": "CLBLM_M_B4", + "A6": "CLBLM_M_A6", + "C2": "CLBLM_M_C2", + "BMUX": "CLBLM_M_BMUX", + "A": "CLBLM_M_A", + "BQ": "CLBLM_M_BQ", + "D3": "CLBLM_M_D3", + "B1": "CLBLM_M_B1", + "CI": "CLBLM_M_CI", + "WE": "CLBLM_M_WE", + "D4": "CLBLM_M_D4", + "AMUX": "CLBLM_M_AMUX", + "DMUX": "CLBLM_M_DMUX", + "DI": "CLBLM_M_DI", + "AX": "CLBLM_M_AX", + "C1": "CLBLM_M_C1", + "C5": "CLBLM_M_C5", + "DX": "CLBLM_M_DX", + "CX": "CLBLM_M_CX", + "C3": "CLBLM_M_C3", + "CMUX": "CLBLM_M_CMUX", + "A1": "CLBLM_M_A1", + "D2": "CLBLM_M_D2", + "CQ": "CLBLM_M_CQ", + "CLK": "CLBLM_M_CLK", + "CIN": "CLBLM_M_CIN", + "AQ": "CLBLM_M_AQ", + "B3": "CLBLM_M_B3", + "D5": "CLBLM_M_D5", + "D1": "CLBLM_M_D1", + "CE": "CLBLM_M_CE", + "B5": "CLBLM_M_B5", + "C4": "CLBLM_M_C4" + }, + "x_coord": 0 + } + ], + "wires": [ + "CLBLM_SE2A0", + "CLBLM_LOGIC_OUTS7", + "CLBLM_L_CIN", + "CLBLM_L_AQ", + "CLBLM_IMUX42", + "CLBLM_L_D6", + "CLBLM_L_A4", + "CLBLM_LH1", + "CLBLM_EE2A3", + "CLBLM_L_B", + "CLBLM_IMUX32", + "CLBLM_L_D2", + "CLBLM_M_BI", + "CLBLM_IMUX23", + "CLBLM_NW4END0", + "CLBLM_NW4END3", + "CLBLM_M_BMUX", + "CLBLM_ER1BEG2", + "CLBLM_WW4C1", + "CLBLM_M_AI", + "CLBLM_WL1END2", + "CLBLM_NW2A2", + "CLBLM_IMUX45", + "CLBLM_NW4A3", + "CLBLM_IMUX16", + "CLBLM_IMUX11", + "CLBLM_WW2END3", + "CLBLM_ER1BEG1", + "CLBLM_M_CIN", + "CLBLM_WW4B2", + "CLBLM_IMUX6", + "CLBLM_M_B2", + "CLBLM_M_C3", + "CLBLM_M_B4", + "CLBLM_SW2A0", + "CLBLM_NW4A0", + "CLBLM_BYP2", + "CLBLM_EE4A0", + "CLBLM_M_C", + "CLBLM_IMUX43", + "CLBLM_WW4B1", + "CLBLM_IMUX26", + "CLBLM_M_AX", + "CLBLM_IMUX9", + "CLBLM_EE2BEG3", + "CLBLM_M_DQ", + "CLBLM_NE2A0", + "CLBLM_WW2A0", + "CLBLM_EE2A0", + "CLBLM_L_D3", + "CLBLM_FAN5", + "CLBLM_SW4A0", + "CLBLM_M_B5", + "CLBLM_M_CE", + "CLBLM_LOGIC_OUTS9", + "CLBLM_L_BX", + "CLBLM_M_D6", + "CLBLM_IMUX7", + "CLBLM_WW4A1", + "CLBLM_EE2BEG2", + "CLBLM_IMUX13", + "CLBLM_M_DMUX", + "CLBLM_M_A2", + "CLBLM_M_DI", + "CLBLM_SW2A2", + "CLBLM_IMUX12", + "CLBLM_L_C2", + "CLBLM_SE4BEG1", + "CLBLM_ER1BEG0", + "CLBLM_L_CMUX", + "CLBLM_IMUX37", + "CLBLM_NE2A3", + "CLBLM_EE2BEG1", + "CLBLM_WW2END1", + "CLBLM_IMUX29", + "CLBLM_LOGIC_OUTS2", + "CLBLM_M_A1", + "CLBLM_IMUX30", + "CLBLM_EE4A2", + "CLBLM_IMUX36", + "CLBLM_SE4C2", + "CLBLM_EE2A1", + "CLBLM_FAN2", + "CLBLM_L_DMUX", + "CLBLM_WW2END0", + "CLBLM_IMUX15", + "CLBLM_NW4A2", + "CLBLM_IMUX38", + "CLBLM_NW4END2", + "CLBLM_SW4END3", + "CLBLM_FAN6", + "CLBLM_WR1END2", + "CLBLM_EE4C2", + "CLBLM_NE4C0", + "CLBLM_SW2A1", + "CLBLM_SW4END0", + "CLBLM_M_D5", + "CLBLM_EE2BEG0", + "CLBLM_IMUX25", + "CLBLM_L_B5", + "CLBLM_IMUX4", + "CLBLM_SE4BEG0", + "CLBLM_EE4C1", + "CLBLM_SE4BEG3", + "CLBLM_M_A", + "CLBLM_M_D", + "CLBLM_IMUX28", + "CLBLM_WL1END0", + "CLBLM_EL1BEG3", + "CLBLM_SW4END1", + "CLBLM_FAN1", + "CLBLM_LOGIC_OUTS6", + "CLBLM_CTRL0", + "CLBLM_WW4END0", + "CLBLM_LOGIC_OUTS23", + "CLBLM_IMUX41", + "CLBLM_LH4", + "CLBLM_M_CLK", + "CLBLM_L_A6", + "CLBLM_L_AMUX", + "CLBLM_L_C", + "CLBLM_IMUX3", + "CLBLM_FAN3", + "CLBLM_EL1BEG0", + "CLBLM_M_A4", + "CLBLM_LOGIC_OUTS18", + "CLBLM_NE4BEG3", + "CLBLM_L_A5", + "CLBLM_M_C6", + "CLBLM_L_BQ", + "CLBLM_WL1END1", + "CLBLM_NW2A3", + "CLBLM_M_B1", + "CLBLM_L_BMUX", + "CLBLM_M_CX", + "CLBLM_IMUX0", + "CLBLM_M_C2", + "CLBLM_LH10", + "CLBLM_WW4END3", + "CLBLM_NW2A1", + "CLBLM_FAN7", + "CLBLM_IMUX39", + "CLBLM_IMUX8", + "CLBLM_M_COUT_N", + "CLBLM_IMUX21", + "CLBLM_BYP1", + "CLBLM_L_CE", + "CLBLM_CLK0", + "CLBLM_LH12", + "CLBLM_EL1BEG2", + "CLBLM_LOGIC_OUTS1", + "CLBLM_IMUX27", + "CLBLM_LOGIC_OUTS22", + "CLBLM_M_C4", + "CLBLM_L_CQ", + "CLBLM_L_A1", + "CLBLM_CTRL1", + "CLBLM_L_B2", + "CLBLM_SW4A1", + "CLBLM_LOGIC_OUTS15", + "CLBLM_IMUX1", + "CLBLM_SW4END2", + "CLBLM_M_AQ", + "CLBLM_WW4B3", + "CLBLM_L_DX", + "CLBLM_SE2A3", + "CLBLM_FAN0", + "CLBLM_LOGIC_OUTS0", + "CLBLM_LOGIC_OUTS14", + "CLBLM_L_A3", + "CLBLM_BYP4", + "CLBLM_NE2A2", + "CLBLM_NE2A1", + "CLBLM_SE4C3", + "CLBLM_NE4BEG2", + "CLBLM_L_B6", + "CLBLM_WL1END3", + "CLBLM_NW4END1", + "CLBLM_IMUX10", + "CLBLM_M_C1", + "CLBLM_SW4A3", + "CLBLM_LOGIC_OUTS3", + "CLBLM_EE4C3", + "CLBLM_M_C5", + "CLBLM_M_A6", + "CLBLM_MONITOR_N", + "CLBLM_BYP7", + "CLBLM_WW4B0", + "CLBLM_CLK1", + "CLBLM_LOGIC_OUTS20", + "CLBLM_LH3", + "CLBLM_L_COUT", + "CLBLM_IMUX44", + "CLBLM_ER1BEG3", + "CLBLM_L_A2", + "CLBLM_L_D5", + "CLBLM_L_C6", + "CLBLM_LOGIC_OUTS4", + "CLBLM_WW2A1", + "CLBLM_EE4BEG0", + "CLBLM_SE4C1", + "CLBLM_EL1BEG1", + "CLBLM_L_C1", + "CLBLM_M_D1", + "CLBLM_WR1END0", + "CLBLM_WR1END1", + "CLBLM_EE4B1", + "CLBLM_WW4C2", + "CLBLM_L_DQ", + "CLBLM_M_A5", + "CLBLM_EE2A2", + "CLBLM_WW2END2", + "CLBLM_NE4C1", + "CLBLM_LH11", + "CLBLM_IMUX18", + "CLBLM_L_B1", + "CLBLM_M_CI", + "CLBLM_MONITOR_P", + "CLBLM_LH5", + "CLBLM_L_COUT_N", + "CLBLM_IMUX35", + "CLBLM_EE4BEG3", + "CLBLM_L_CX", + "CLBLM_NE4BEG0", + "CLBLM_LOGIC_OUTS21", + "CLBLM_IMUX2", + "CLBLM_BYP5", + "CLBLM_IMUX20", + "CLBLM_EE4B2", + "CLBLM_EE4B0", + "CLBLM_IMUX40", + "CLBLM_M_D2", + "CLBLM_WR1END3", + "CLBLM_LOGIC_OUTS16", + "CLBLM_WW4A3", + "CLBLM_LOGIC_OUTS5", + "CLBLM_M_AMUX", + "CLBLM_NE4C2", + "CLBLM_WW4END2", + "CLBLM_L_B4", + "CLBLM_WW2A2", + "CLBLM_NE4BEG1", + "CLBLM_M_CMUX", + "CLBLM_IMUX5", + "CLBLM_M_D3", + "CLBLM_WW2A3", + "CLBLM_LH6", + "CLBLM_L_A", + "CLBLM_M_WE", + "CLBLM_WW4END1", + "CLBLM_LOGIC_OUTS13", + "CLBLM_M_COUT", + "CLBLM_L_B3", + "CLBLM_L_D", + "CLBLM_LOGIC_OUTS10", + "CLBLM_SW2A3", + "CLBLM_LH8", + "CLBLM_FAN4", + "CLBLM_L_SR", + "CLBLM_M_B3", + "CLBLM_SE2A2", + "CLBLM_WW4C3", + "CLBLM_L_D1", + "CLBLM_L_C3", + "CLBLM_M_D4", + "CLBLM_L_C4", + "CLBLM_EE4B3", + "CLBLM_LOGIC_OUTS19", + "CLBLM_LOGIC_OUTS8", + "CLBLM_IMUX17", + "CLBLM_NW4A1", + "CLBLM_IMUX22", + "CLBLM_M_CQ", + "CLBLM_M_B", + "CLBLM_SW4A2", + "CLBLM_EE4C0", + "CLBLM_WW4A2", + "CLBLM_EE4BEG2", + "CLBLM_NW2A0", + "CLBLM_EE4BEG1", + "CLBLM_IMUX19", + "CLBLM_IMUX47", + "CLBLM_IMUX46", + "CLBLM_WW4C0", + "CLBLM_LH7", + "CLBLM_L_CLK", + "CLBLM_M_DX", + "CLBLM_M_A3", + "CLBLM_L_D4", + "CLBLM_LOGIC_OUTS12", + "CLBLM_M_BQ", + "CLBLM_IMUX14", + "CLBLM_BYP6", + "CLBLM_SE2A1", + "CLBLM_EE4A1", + "CLBLM_LH9", + "CLBLM_EE4A3", + "CLBLM_IMUX24", + "CLBLM_LOGIC_OUTS17", + "CLBLM_IMUX31", + "CLBLM_LH2", + "CLBLM_LOGIC_OUTS11", + "CLBLM_IMUX33", + "CLBLM_SE4BEG2", + "CLBLM_M_BX", + "CLBLM_M_SR", + "CLBLM_NE4C3", + "CLBLM_WW4A0", + "CLBLM_M_B6", + "CLBLM_BYP3", + "CLBLM_IMUX34", + "CLBLM_SE4C0", + "CLBLM_L_AX", + "CLBLM_L_C5", + "CLBLM_BYP0" + ], + "pips": { + "CLBLM_L.CLBLM_IMUX27->CLBLM_M_B4": { + "src_wire": "CLBLM_IMUX27", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_A2->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A2", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX22->CLBLM_M_C3": { + "src_wire": "CLBLM_IMUX22", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX45->CLBLM_M_D2": { + "src_wire": "CLBLM_IMUX45", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_C5->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C5", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_FAN7->CLBLM_M_CE": { + "src_wire": "CLBLM_FAN7", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CE", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX2->CLBLM_M_A2": { + "src_wire": "CLBLM_IMUX2", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX47->CLBLM_M_D5": { + "src_wire": "CLBLM_IMUX47", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX14->CLBLM_L_B1": { + "src_wire": "CLBLM_IMUX14", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_AMUX->CLBLM_LOGIC_OUTS16": { + "src_wire": "CLBLM_L_AMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS16", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_BQ->CLBLM_LOGIC_OUTS5": { + "src_wire": "CLBLM_M_BQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX31->CLBLM_M_C5": { + "src_wire": "CLBLM_IMUX31", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_A3->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A3", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX1->CLBLM_M_A3": { + "src_wire": "CLBLM_IMUX1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_D4->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D4", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_A6->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A6", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_BMUX->CLBLM_LOGIC_OUTS17": { + "src_wire": "CLBLM_L_BMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS17", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_CTRL0->CLBLM_L_SR": { + "src_wire": "CLBLM_CTRL0", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_SR", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX21->CLBLM_L_C4": { + "src_wire": "CLBLM_IMUX21", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_BYP6->CLBLM_M_DX": { + "src_wire": "CLBLM_BYP6", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_DX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX40->CLBLM_M_D1": { + "src_wire": "CLBLM_IMUX40", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_D2->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D2", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX16->CLBLM_L_B3": { + "src_wire": "CLBLM_IMUX16", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_D1->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_COUT->CLBLM_M_COUT_N": { + "src_wire": "CLBLM_M_COUT", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_COUT_N", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_B->CLBLM_LOGIC_OUTS9": { + "src_wire": "CLBLM_L_B", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS9", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_B5->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B5", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_C->CLBLM_LOGIC_OUTS14": { + "src_wire": "CLBLM_M_C", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS14", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX3->CLBLM_L_A2": { + "src_wire": "CLBLM_IMUX3", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_D6->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D6", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_FAN5->CLBLM_M_CI": { + "src_wire": "CLBLM_FAN5", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CI", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_FAN6->CLBLM_L_CE": { + "src_wire": "CLBLM_FAN6", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_CE", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX26->CLBLM_L_B4": { + "src_wire": "CLBLM_IMUX26", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_A6->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A6", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_BYP3->CLBLM_M_CX": { + "src_wire": "CLBLM_BYP3", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX35->CLBLM_M_C6": { + "src_wire": "CLBLM_IMUX35", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_C->>CLBLM_M_CMUX": { + "src_wire": "CLBLM_M_C", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_CMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_D2->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D2", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_CMUX->CLBLM_LOGIC_OUTS22": { + "src_wire": "CLBLM_M_CMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS22", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX30->CLBLM_L_C5": { + "src_wire": "CLBLM_IMUX30", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_AQ->CLBLM_LOGIC_OUTS0": { + "src_wire": "CLBLM_L_AQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS0", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_B5->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B5", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_A1->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_CLK0->CLBLM_L_CLK": { + "src_wire": "CLBLM_CLK0", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX7->CLBLM_M_A1": { + "src_wire": "CLBLM_IMUX7", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_A4->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A4", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX8->CLBLM_M_A5": { + "src_wire": "CLBLM_IMUX8", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX0->CLBLM_L_A3": { + "src_wire": "CLBLM_IMUX0", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX20->CLBLM_L_C2": { + "src_wire": "CLBLM_IMUX20", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_AQ->CLBLM_LOGIC_OUTS4": { + "src_wire": "CLBLM_M_AQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_B3->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B3", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_FAN2->CLBLM_M_BI": { + "src_wire": "CLBLM_FAN2", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_BI", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_B4->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B4", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_C1->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX44->CLBLM_M_D4": { + "src_wire": "CLBLM_IMUX44", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX46->CLBLM_L_D5": { + "src_wire": "CLBLM_IMUX46", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_D5->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D5", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX28->CLBLM_M_C4": { + "src_wire": "CLBLM_IMUX28", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX43->CLBLM_M_D6": { + "src_wire": "CLBLM_IMUX43", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_BYP0->CLBLM_L_AX": { + "src_wire": "CLBLM_BYP0", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_AX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_C6->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C6", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_FAN3->CLBLM_M_DI": { + "src_wire": "CLBLM_FAN3", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_DI", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_A4->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A4", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX29->CLBLM_M_C2": { + "src_wire": "CLBLM_IMUX29", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_A->>CLBLM_L_AMUX": { + "src_wire": "CLBLM_L_A", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_AMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX38->CLBLM_M_D3": { + "src_wire": "CLBLM_IMUX38", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX25->CLBLM_L_B5": { + "src_wire": "CLBLM_IMUX25", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_BYP4->CLBLM_M_BX": { + "src_wire": "CLBLM_BYP4", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_BX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX33->CLBLM_L_C1": { + "src_wire": "CLBLM_IMUX33", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_CMUX->CLBLM_LOGIC_OUTS18": { + "src_wire": "CLBLM_L_CMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS18", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX41->CLBLM_L_D1": { + "src_wire": "CLBLM_IMUX41", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX18->CLBLM_M_B2": { + "src_wire": "CLBLM_IMUX18", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX11->CLBLM_M_A4": { + "src_wire": "CLBLM_IMUX11", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX5->CLBLM_L_A6": { + "src_wire": "CLBLM_IMUX5", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_D->>CLBLM_M_DMUX": { + "src_wire": "CLBLM_M_D", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_C->>CLBLM_L_CMUX": { + "src_wire": "CLBLM_L_C", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_CMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_FAN4->CLBLM_M_WE": { + "src_wire": "CLBLM_FAN4", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_WE", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_B3->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B3", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX42->CLBLM_L_D6": { + "src_wire": "CLBLM_IMUX42", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX24->CLBLM_M_B5": { + "src_wire": "CLBLM_IMUX24", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_C->CLBLM_LOGIC_OUTS10": { + "src_wire": "CLBLM_L_C", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS10", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_D->CLBLM_LOGIC_OUTS15": { + "src_wire": "CLBLM_M_D", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS15", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_C5->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C5", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX39->CLBLM_L_D3": { + "src_wire": "CLBLM_IMUX39", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX13->CLBLM_L_B6": { + "src_wire": "CLBLM_IMUX13", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_CQ->CLBLM_LOGIC_OUTS2": { + "src_wire": "CLBLM_L_CQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_DQ->CLBLM_LOGIC_OUTS3": { + "src_wire": "CLBLM_L_DQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_BMUX->CLBLM_LOGIC_OUTS21": { + "src_wire": "CLBLM_M_BMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS21", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX36->CLBLM_L_D2": { + "src_wire": "CLBLM_IMUX36", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_B2->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B2", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX34->CLBLM_L_C6": { + "src_wire": "CLBLM_IMUX34", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX4->CLBLM_M_A6": { + "src_wire": "CLBLM_IMUX4", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_DMUX->CLBLM_LOGIC_OUTS23": { + "src_wire": "CLBLM_M_DMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS23", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX32->CLBLM_M_C1": { + "src_wire": "CLBLM_IMUX32", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_C3->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C3", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_BYP7->CLBLM_L_DX": { + "src_wire": "CLBLM_BYP7", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_DX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_BQ->CLBLM_LOGIC_OUTS1": { + "src_wire": "CLBLM_L_BQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_D->CLBLM_LOGIC_OUTS11": { + "src_wire": "CLBLM_L_D", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS11", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_A5->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A5", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_C2->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C2", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_D6->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D6", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_FAN0->CLBLM_M_AI": { + "src_wire": "CLBLM_FAN0", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_AI", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_BYP1->CLBLM_M_AX": { + "src_wire": "CLBLM_BYP1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_AX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_A->CLBLM_LOGIC_OUTS8": { + "src_wire": "CLBLM_L_A", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS8", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_C2->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C2", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_B6->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B6", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX10->CLBLM_L_A4": { + "src_wire": "CLBLM_IMUX10", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_C4->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C4", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX23->CLBLM_L_C3": { + "src_wire": "CLBLM_IMUX23", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_D3->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D3", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX17->CLBLM_M_B3": { + "src_wire": "CLBLM_IMUX17", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_BYP5->CLBLM_L_BX": { + "src_wire": "CLBLM_BYP5", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_BX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_A5->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A5", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_COUT->CLBLM_L_COUT_N": { + "src_wire": "CLBLM_L_COUT", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_COUT_N", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_C6->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C6", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_B1->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_BYP2->CLBLM_L_CX": { + "src_wire": "CLBLM_BYP2", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_CX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX37->CLBLM_L_D4": { + "src_wire": "CLBLM_IMUX37", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_B6->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B6", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_C1->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_D5->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D5", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_B->CLBLM_LOGIC_OUTS13": { + "src_wire": "CLBLM_M_B", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS13", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_B2->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B2", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_A3->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A3", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_A1->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_D1->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX12->CLBLM_M_B6": { + "src_wire": "CLBLM_IMUX12", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_CTRL1->CLBLM_M_SR": { + "src_wire": "CLBLM_CTRL1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_SR", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_CLK1->CLBLM_M_CLK": { + "src_wire": "CLBLM_CLK1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_DQ->CLBLM_LOGIC_OUTS7": { + "src_wire": "CLBLM_M_DQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS7", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX19->CLBLM_L_B2": { + "src_wire": "CLBLM_IMUX19", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_D3->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D3", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_D4->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D4", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_C3->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C3", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_B4->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B4", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_B1->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_COUT->>CLBLM_L_DMUX": { + "src_wire": "CLBLM_L_COUT", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_B->>CLBLM_L_BMUX": { + "src_wire": "CLBLM_L_B", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_BMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_A->CLBLM_LOGIC_OUTS12": { + "src_wire": "CLBLM_M_A", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS12", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_C4->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C4", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX6->CLBLM_L_A1": { + "src_wire": "CLBLM_IMUX6", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_B->>CLBLM_M_BMUX": { + "src_wire": "CLBLM_M_B", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_BMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_DMUX->CLBLM_LOGIC_OUTS19": { + "src_wire": "CLBLM_L_DMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS19", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_COUT->>CLBLM_M_DMUX": { + "src_wire": "CLBLM_M_COUT", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_L_D->>CLBLM_L_DMUX": { + "src_wire": "CLBLM_L_D", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX15->CLBLM_M_B1": { + "src_wire": "CLBLM_IMUX15", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_IMUX9->CLBLM_L_A5": { + "src_wire": "CLBLM_IMUX9", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_A->>CLBLM_M_AMUX": { + "src_wire": "CLBLM_M_A", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_AMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_A2->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A2", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_AMUX->CLBLM_LOGIC_OUTS20": { + "src_wire": "CLBLM_M_AMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS20", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_L.CLBLM_M_CQ->CLBLM_LOGIC_OUTS6": { + "src_wire": "CLBLM_M_CQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS6", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CLBLM_R.json b/kintex7/tile_type_CLBLM_R.json new file mode 100644 index 0000000..379777d --- /dev/null +++ b/kintex7/tile_type_CLBLM_R.json @@ -0,0 +1,1494 @@ +{ + "tile_type": "CLBLM_R", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "SLICE", + "type": "SLICEM", + "site_pins": { + "BX": "CLBLM_M_BX", + "A3": "CLBLM_M_A3", + "D": "CLBLM_M_D", + "C": "CLBLM_M_C", + "DQ": "CLBLM_M_DQ", + "B2": "CLBLM_M_B2", + "C6": "CLBLM_M_C6", + "COUT": "CLBLM_M_COUT", + "A2": "CLBLM_M_A2", + "SR": "CLBLM_M_SR", + "AI": "CLBLM_M_AI", + "B6": "CLBLM_M_B6", + "BI": "CLBLM_M_BI", + "D6": "CLBLM_M_D6", + "A5": "CLBLM_M_A5", + "B": "CLBLM_M_B", + "A4": "CLBLM_M_A4", + "B4": "CLBLM_M_B4", + "A6": "CLBLM_M_A6", + "C2": "CLBLM_M_C2", + "BMUX": "CLBLM_M_BMUX", + "A": "CLBLM_M_A", + "BQ": "CLBLM_M_BQ", + "D3": "CLBLM_M_D3", + "B1": "CLBLM_M_B1", + "CI": "CLBLM_M_CI", + "WE": "CLBLM_M_WE", + "D4": "CLBLM_M_D4", + "AMUX": "CLBLM_M_AMUX", + "DMUX": "CLBLM_M_DMUX", + "DI": "CLBLM_M_DI", + "AX": "CLBLM_M_AX", + "C1": "CLBLM_M_C1", + "C5": "CLBLM_M_C5", + "DX": "CLBLM_M_DX", + "CX": "CLBLM_M_CX", + "C3": "CLBLM_M_C3", + "CMUX": "CLBLM_M_CMUX", + "A1": "CLBLM_M_A1", + "D2": "CLBLM_M_D2", + "CQ": "CLBLM_M_CQ", + "CLK": "CLBLM_M_CLK", + "CIN": "CLBLM_M_CIN", + "AQ": "CLBLM_M_AQ", + "B3": "CLBLM_M_B3", + "D5": "CLBLM_M_D5", + "D1": "CLBLM_M_D1", + "CE": "CLBLM_M_CE", + "B5": "CLBLM_M_B5", + "C4": "CLBLM_M_C4" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X1Y0", + "prefix": "SLICE", + "type": "SLICEL", + "site_pins": { + "BX": "CLBLM_L_BX", + "A3": "CLBLM_L_A3", + "D": "CLBLM_L_D", + "C": "CLBLM_L_C", + "DQ": "CLBLM_L_DQ", + "B2": "CLBLM_L_B2", + "C6": "CLBLM_L_C6", + "A2": "CLBLM_L_A2", + "SR": "CLBLM_L_SR", + "B6": "CLBLM_L_B6", + "D6": "CLBLM_L_D6", + "A5": "CLBLM_L_A5", + "B": "CLBLM_L_B", + "A4": "CLBLM_L_A4", + "B4": "CLBLM_L_B4", + "A6": "CLBLM_L_A6", + "C2": "CLBLM_L_C2", + "AQ": "CLBLM_L_AQ", + "A": "CLBLM_L_A", + "BQ": "CLBLM_L_BQ", + "D3": "CLBLM_L_D3", + "B1": "CLBLM_L_B1", + "COUT": "CLBLM_L_COUT", + "D4": "CLBLM_L_D4", + "AMUX": "CLBLM_L_AMUX", + "DMUX": "CLBLM_L_DMUX", + "AX": "CLBLM_L_AX", + "C1": "CLBLM_L_C1", + "C5": "CLBLM_L_C5", + "DX": "CLBLM_L_DX", + "CX": "CLBLM_L_CX", + "C3": "CLBLM_L_C3", + "CMUX": "CLBLM_L_CMUX", + "A1": "CLBLM_L_A1", + "D2": "CLBLM_L_D2", + "CQ": "CLBLM_L_CQ", + "CLK": "CLBLM_L_CLK", + "CIN": "CLBLM_L_CIN", + "BMUX": "CLBLM_L_BMUX", + "B3": "CLBLM_L_B3", + "D5": "CLBLM_L_D5", + "D1": "CLBLM_L_D1", + "CE": "CLBLM_L_CE", + "B5": "CLBLM_L_B5", + "C4": "CLBLM_L_C4" + }, + "x_coord": 1 + } + ], + "wires": [ + "CLBLM_SE2A0", + "CLBLM_LOGIC_OUTS7", + "CLBLM_L_CIN", + "CLBLM_L_AQ", + "CLBLM_IMUX42", + "CLBLM_L_D6", + "CLBLM_L_A4", + "CLBLM_LH1", + "CLBLM_EE2A3", + "CLBLM_L_B", + "CLBLM_IMUX32", + "CLBLM_L_D2", + "CLBLM_M_BI", + "CLBLM_IMUX23", + "CLBLM_NW4END0", + "CLBLM_NW4END3", + "CLBLM_M_BMUX", + "CLBLM_ER1BEG2", + "CLBLM_WW4C1", + "CLBLM_M_AI", + "CLBLM_WL1END2", + "CLBLM_NW2A2", + "CLBLM_IMUX45", + "CLBLM_NW4A3", + "CLBLM_IMUX16", + "CLBLM_IMUX11", + "CLBLM_WW2END3", + "CLBLM_ER1BEG1", + "CLBLM_M_CIN", + "CLBLM_WW4B2", + "CLBLM_IMUX6", + "CLBLM_M_B2", + "CLBLM_M_C3", + "CLBLM_M_B4", + "CLBLM_SW2A0", + "CLBLM_NW4A0", + "CLBLM_BYP2", + "CLBLM_EE4A0", + "CLBLM_M_C", + "CLBLM_IMUX43", + "CLBLM_WW4B1", + "CLBLM_IMUX26", + "CLBLM_M_AX", + "CLBLM_IMUX9", + "CLBLM_EE2BEG3", + "CLBLM_M_DQ", + "CLBLM_NE2A0", + "CLBLM_WW2A0", + "CLBLM_EE2A0", + "CLBLM_L_D3", + "CLBLM_FAN5", + "CLBLM_SW4A0", + "CLBLM_M_B5", + "CLBLM_M_CE", + "CLBLM_LOGIC_OUTS9", + "CLBLM_L_BX", + "CLBLM_M_D6", + "CLBLM_IMUX7", + "CLBLM_WW4A1", + "CLBLM_EE2BEG2", + "CLBLM_IMUX13", + "CLBLM_M_DMUX", + "CLBLM_M_A2", + "CLBLM_M_DI", + "CLBLM_SW2A2", + "CLBLM_IMUX12", + "CLBLM_L_C2", + "CLBLM_SE4BEG1", + "CLBLM_ER1BEG0", + "CLBLM_L_CMUX", + "CLBLM_IMUX37", + "CLBLM_NE2A3", + "CLBLM_EE2BEG1", + "CLBLM_WW2END1", + "CLBLM_IMUX29", + "CLBLM_LOGIC_OUTS2", + "CLBLM_M_A1", + "CLBLM_IMUX30", + "CLBLM_EE4A2", + "CLBLM_IMUX36", + "CLBLM_SE4C2", + "CLBLM_EE2A1", + "CLBLM_FAN2", + "CLBLM_L_DMUX", + "CLBLM_WW2END0", + "CLBLM_IMUX15", + "CLBLM_NW4A2", + "CLBLM_IMUX38", + "CLBLM_NW4END2", + "CLBLM_SW4END3", + "CLBLM_FAN6", + "CLBLM_WR1END2", + "CLBLM_EE4C2", + "CLBLM_NE4C0", + "CLBLM_SW2A1", + "CLBLM_SW4END0", + "CLBLM_M_D5", + "CLBLM_EE2BEG0", + "CLBLM_IMUX25", + "CLBLM_L_B5", + "CLBLM_IMUX4", + "CLBLM_SE4BEG0", + "CLBLM_EE4C1", + "CLBLM_SE4BEG3", + "CLBLM_M_A", + "CLBLM_M_D", + "CLBLM_IMUX28", + "CLBLM_WL1END0", + "CLBLM_EL1BEG3", + "CLBLM_SW4END1", + "CLBLM_FAN1", + "CLBLM_LOGIC_OUTS6", + "CLBLM_CTRL0", + "CLBLM_WW4END0", + "CLBLM_LOGIC_OUTS23", + "CLBLM_IMUX41", + "CLBLM_LH4", + "CLBLM_M_CLK", + "CLBLM_L_A6", + "CLBLM_L_AMUX", + "CLBLM_L_C", + "CLBLM_IMUX3", + "CLBLM_FAN3", + "CLBLM_EL1BEG0", + "CLBLM_M_A4", + "CLBLM_LOGIC_OUTS18", + "CLBLM_NE4BEG3", + "CLBLM_L_A5", + "CLBLM_M_C6", + "CLBLM_L_BQ", + "CLBLM_WL1END1", + "CLBLM_NW2A3", + "CLBLM_M_B1", + "CLBLM_L_BMUX", + "CLBLM_M_CX", + "CLBLM_IMUX0", + "CLBLM_M_C2", + "CLBLM_LH10", + "CLBLM_WW4END3", + "CLBLM_NW2A1", + "CLBLM_FAN7", + "CLBLM_IMUX39", + "CLBLM_IMUX8", + "CLBLM_M_COUT_N", + "CLBLM_IMUX21", + "CLBLM_BYP1", + "CLBLM_L_CE", + "CLBLM_CLK0", + "CLBLM_LH12", + "CLBLM_EL1BEG2", + "CLBLM_LOGIC_OUTS1", + "CLBLM_IMUX27", + "CLBLM_LOGIC_OUTS22", + "CLBLM_M_C4", + "CLBLM_L_CQ", + "CLBLM_L_A1", + "CLBLM_CTRL1", + "CLBLM_L_B2", + "CLBLM_SW4A1", + "CLBLM_LOGIC_OUTS15", + "CLBLM_IMUX1", + "CLBLM_SW4END2", + "CLBLM_M_AQ", + "CLBLM_WW4B3", + "CLBLM_L_DX", + "CLBLM_SE2A3", + "CLBLM_FAN0", + "CLBLM_LOGIC_OUTS0", + "CLBLM_LOGIC_OUTS14", + "CLBLM_L_A3", + "CLBLM_BYP4", + "CLBLM_NE2A2", + "CLBLM_NE2A1", + "CLBLM_SE4C3", + "CLBLM_NE4BEG2", + "CLBLM_L_B6", + "CLBLM_WL1END3", + "CLBLM_NW4END1", + "CLBLM_IMUX10", + "CLBLM_M_C1", + "CLBLM_SW4A3", + "CLBLM_LOGIC_OUTS3", + "CLBLM_EE4C3", + "CLBLM_M_C5", + "CLBLM_M_A6", + "CLBLM_MONITOR_N", + "CLBLM_BYP7", + "CLBLM_WW4B0", + "CLBLM_CLK1", + "CLBLM_LOGIC_OUTS20", + "CLBLM_LH3", + "CLBLM_L_COUT", + "CLBLM_IMUX44", + "CLBLM_ER1BEG3", + "CLBLM_L_A2", + "CLBLM_L_D5", + "CLBLM_L_C6", + "CLBLM_LOGIC_OUTS4", + "CLBLM_WW2A1", + "CLBLM_EE4BEG0", + "CLBLM_SE4C1", + "CLBLM_EL1BEG1", + "CLBLM_L_C1", + "CLBLM_M_D1", + "CLBLM_WR1END0", + "CLBLM_WR1END1", + "CLBLM_EE4B1", + "CLBLM_WW4C2", + "CLBLM_L_DQ", + "CLBLM_M_A5", + "CLBLM_EE2A2", + "CLBLM_WW2END2", + "CLBLM_NE4C1", + "CLBLM_LH11", + "CLBLM_IMUX18", + "CLBLM_L_B1", + "CLBLM_M_CI", + "CLBLM_MONITOR_P", + "CLBLM_LH5", + "CLBLM_L_COUT_N", + "CLBLM_IMUX35", + "CLBLM_EE4BEG3", + "CLBLM_L_CX", + "CLBLM_NE4BEG0", + "CLBLM_LOGIC_OUTS21", + "CLBLM_IMUX2", + "CLBLM_BYP5", + "CLBLM_IMUX20", + "CLBLM_EE4B2", + "CLBLM_EE4B0", + "CLBLM_IMUX40", + "CLBLM_M_D2", + "CLBLM_WR1END3", + "CLBLM_LOGIC_OUTS16", + "CLBLM_WW4A3", + "CLBLM_LOGIC_OUTS5", + "CLBLM_M_AMUX", + "CLBLM_NE4C2", + "CLBLM_WW4END2", + "CLBLM_L_B4", + "CLBLM_WW2A2", + "CLBLM_NE4BEG1", + "CLBLM_M_CMUX", + "CLBLM_IMUX5", + "CLBLM_M_D3", + "CLBLM_WW2A3", + "CLBLM_LH6", + "CLBLM_L_A", + "CLBLM_M_WE", + "CLBLM_WW4END1", + "CLBLM_LOGIC_OUTS13", + "CLBLM_M_COUT", + "CLBLM_L_B3", + "CLBLM_L_D", + "CLBLM_LOGIC_OUTS10", + "CLBLM_SW2A3", + "CLBLM_LH8", + "CLBLM_FAN4", + "CLBLM_L_SR", + "CLBLM_M_B3", + "CLBLM_SE2A2", + "CLBLM_WW4C3", + "CLBLM_L_D1", + "CLBLM_L_C3", + "CLBLM_M_D4", + "CLBLM_L_C4", + "CLBLM_EE4B3", + "CLBLM_LOGIC_OUTS19", + "CLBLM_LOGIC_OUTS8", + "CLBLM_IMUX17", + "CLBLM_NW4A1", + "CLBLM_IMUX22", + "CLBLM_M_CQ", + "CLBLM_M_B", + "CLBLM_SW4A2", + "CLBLM_EE4C0", + "CLBLM_WW4A2", + "CLBLM_EE4BEG2", + "CLBLM_NW2A0", + "CLBLM_EE4BEG1", + "CLBLM_IMUX19", + "CLBLM_IMUX47", + "CLBLM_IMUX46", + "CLBLM_WW4C0", + "CLBLM_LH7", + "CLBLM_L_CLK", + "CLBLM_M_DX", + "CLBLM_M_A3", + "CLBLM_L_D4", + "CLBLM_LOGIC_OUTS12", + "CLBLM_M_BQ", + "CLBLM_IMUX14", + "CLBLM_BYP6", + "CLBLM_SE2A1", + "CLBLM_EE4A1", + "CLBLM_LH9", + "CLBLM_EE4A3", + "CLBLM_IMUX24", + "CLBLM_LOGIC_OUTS17", + "CLBLM_IMUX31", + "CLBLM_LH2", + "CLBLM_LOGIC_OUTS11", + "CLBLM_IMUX33", + "CLBLM_SE4BEG2", + "CLBLM_M_BX", + "CLBLM_M_SR", + "CLBLM_NE4C3", + "CLBLM_WW4A0", + "CLBLM_M_B6", + "CLBLM_BYP3", + "CLBLM_IMUX34", + "CLBLM_SE4C0", + "CLBLM_L_AX", + "CLBLM_L_C5", + "CLBLM_BYP0" + ], + "pips": { + "CLBLM_R.CLBLM_IMUX45->CLBLM_M_D2": { + "src_wire": "CLBLM_IMUX45", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_DQ->CLBLM_LOGIC_OUTS7": { + "src_wire": "CLBLM_M_DQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS7", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_BYP4->CLBLM_M_BX": { + "src_wire": "CLBLM_BYP4", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_BX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX9->CLBLM_L_A5": { + "src_wire": "CLBLM_IMUX9", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_DMUX->CLBLM_LOGIC_OUTS19": { + "src_wire": "CLBLM_L_DMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS19", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX34->CLBLM_L_C6": { + "src_wire": "CLBLM_IMUX34", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX15->CLBLM_M_B1": { + "src_wire": "CLBLM_IMUX15", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_B4->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B4", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_B5->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B5", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_D6->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D6", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_CTRL1->CLBLM_M_SR": { + "src_wire": "CLBLM_CTRL1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_SR", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX14->CLBLM_L_B1": { + "src_wire": "CLBLM_IMUX14", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_C2->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C2", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_C->CLBLM_LOGIC_OUTS10": { + "src_wire": "CLBLM_L_C", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS10", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX29->CLBLM_M_C2": { + "src_wire": "CLBLM_IMUX29", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX46->CLBLM_L_D5": { + "src_wire": "CLBLM_IMUX46", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_A1->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_C->>CLBLM_L_CMUX": { + "src_wire": "CLBLM_L_C", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_CMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_D5->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D5", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX23->CLBLM_L_C3": { + "src_wire": "CLBLM_IMUX23", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_BQ->CLBLM_LOGIC_OUTS5": { + "src_wire": "CLBLM_M_BQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_D3->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D3", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX31->CLBLM_M_C5": { + "src_wire": "CLBLM_IMUX31", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_FAN7->CLBLM_M_CE": { + "src_wire": "CLBLM_FAN7", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CE", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX36->CLBLM_L_D2": { + "src_wire": "CLBLM_IMUX36", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_FAN5->CLBLM_M_CI": { + "src_wire": "CLBLM_FAN5", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CI", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_A4->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A4", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_BYP6->CLBLM_M_DX": { + "src_wire": "CLBLM_BYP6", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_DX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_CQ->CLBLM_LOGIC_OUTS6": { + "src_wire": "CLBLM_M_CQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX3->CLBLM_L_A2": { + "src_wire": "CLBLM_IMUX3", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX19->CLBLM_L_B2": { + "src_wire": "CLBLM_IMUX19", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_B6->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B6", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_DMUX->CLBLM_LOGIC_OUTS23": { + "src_wire": "CLBLM_M_DMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS23", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX33->CLBLM_L_C1": { + "src_wire": "CLBLM_IMUX33", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_AMUX->CLBLM_LOGIC_OUTS20": { + "src_wire": "CLBLM_M_AMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS20", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX13->CLBLM_L_B6": { + "src_wire": "CLBLM_IMUX13", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX2->CLBLM_M_A2": { + "src_wire": "CLBLM_IMUX2", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_D->>CLBLM_L_DMUX": { + "src_wire": "CLBLM_L_D", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_B6->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B6", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_A1->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX5->CLBLM_L_A6": { + "src_wire": "CLBLM_IMUX5", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX47->CLBLM_M_D5": { + "src_wire": "CLBLM_IMUX47", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX20->CLBLM_L_C2": { + "src_wire": "CLBLM_IMUX20", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_D5->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D5", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX16->CLBLM_L_B3": { + "src_wire": "CLBLM_IMUX16", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_A6->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A6", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_C6->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C6", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_BYP0->CLBLM_L_AX": { + "src_wire": "CLBLM_BYP0", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_AX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX11->CLBLM_M_A4": { + "src_wire": "CLBLM_IMUX11", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_A2->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A2", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_CTRL0->CLBLM_L_SR": { + "src_wire": "CLBLM_CTRL0", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_SR", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_B->CLBLM_LOGIC_OUTS13": { + "src_wire": "CLBLM_M_B", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS13", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX1->CLBLM_M_A3": { + "src_wire": "CLBLM_IMUX1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_CQ->CLBLM_LOGIC_OUTS2": { + "src_wire": "CLBLM_L_CQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_A->CLBLM_LOGIC_OUTS8": { + "src_wire": "CLBLM_L_A", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS8", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_B5->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B5", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX37->CLBLM_L_D4": { + "src_wire": "CLBLM_IMUX37", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_BYP7->CLBLM_L_DX": { + "src_wire": "CLBLM_BYP7", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_DX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX27->CLBLM_M_B4": { + "src_wire": "CLBLM_IMUX27", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_AMUX->CLBLM_LOGIC_OUTS16": { + "src_wire": "CLBLM_L_AMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS16", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX28->CLBLM_M_C4": { + "src_wire": "CLBLM_IMUX28", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX32->CLBLM_M_C1": { + "src_wire": "CLBLM_IMUX32", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_B2->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B2", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_B2->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B2", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_BMUX->CLBLM_LOGIC_OUTS17": { + "src_wire": "CLBLM_L_BMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS17", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX39->CLBLM_L_D3": { + "src_wire": "CLBLM_IMUX39", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_D4->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D4", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_D->CLBLM_LOGIC_OUTS11": { + "src_wire": "CLBLM_L_D", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS11", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_FAN0->CLBLM_M_AI": { + "src_wire": "CLBLM_FAN0", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_AI", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_C3->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C3", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX8->CLBLM_M_A5": { + "src_wire": "CLBLM_IMUX8", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX38->CLBLM_M_D3": { + "src_wire": "CLBLM_IMUX38", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_A->>CLBLM_L_AMUX": { + "src_wire": "CLBLM_L_A", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_AMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX6->CLBLM_L_A1": { + "src_wire": "CLBLM_IMUX6", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_BQ->CLBLM_LOGIC_OUTS1": { + "src_wire": "CLBLM_L_BQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_C3->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C3", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX26->CLBLM_L_B4": { + "src_wire": "CLBLM_IMUX26", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_CLK0->CLBLM_L_CLK": { + "src_wire": "CLBLM_CLK0", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX21->CLBLM_L_C4": { + "src_wire": "CLBLM_IMUX21", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_A3->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A3", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_D->CLBLM_LOGIC_OUTS15": { + "src_wire": "CLBLM_M_D", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS15", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_C1->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_COUT->>CLBLM_L_DMUX": { + "src_wire": "CLBLM_L_COUT", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_BYP2->CLBLM_L_CX": { + "src_wire": "CLBLM_BYP2", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_CX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_C1->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_AQ->CLBLM_LOGIC_OUTS4": { + "src_wire": "CLBLM_M_AQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_D3->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D3", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_BYP3->CLBLM_M_CX": { + "src_wire": "CLBLM_BYP3", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_B3->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B3", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX22->CLBLM_M_C3": { + "src_wire": "CLBLM_IMUX22", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_A->CLBLM_LOGIC_OUTS12": { + "src_wire": "CLBLM_M_A", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS12", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_CLK1->CLBLM_M_CLK": { + "src_wire": "CLBLM_CLK1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_A3->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A3", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_C5->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C5", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_FAN2->CLBLM_M_BI": { + "src_wire": "CLBLM_FAN2", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_BI", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX40->CLBLM_M_D1": { + "src_wire": "CLBLM_IMUX40", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_C->CLBLM_LOGIC_OUTS14": { + "src_wire": "CLBLM_M_C", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS14", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX10->CLBLM_L_A4": { + "src_wire": "CLBLM_IMUX10", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX25->CLBLM_L_B5": { + "src_wire": "CLBLM_IMUX25", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_AQ->CLBLM_LOGIC_OUTS0": { + "src_wire": "CLBLM_L_AQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS0", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_B->>CLBLM_L_BMUX": { + "src_wire": "CLBLM_L_B", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_BMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX30->CLBLM_L_C5": { + "src_wire": "CLBLM_IMUX30", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_C4->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C4", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_D4->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D4", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_COUT->CLBLM_M_COUT_N": { + "src_wire": "CLBLM_M_COUT", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_COUT_N", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_FAN4->CLBLM_M_WE": { + "src_wire": "CLBLM_FAN4", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_WE", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_B1->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_A->>CLBLM_M_AMUX": { + "src_wire": "CLBLM_M_A", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_AMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_D2->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D2", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_COUT->CLBLM_L_COUT_N": { + "src_wire": "CLBLM_L_COUT", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_COUT_N", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_A2->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A2", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_A6->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A6", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX4->CLBLM_M_A6": { + "src_wire": "CLBLM_IMUX4", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_BYP1->CLBLM_M_AX": { + "src_wire": "CLBLM_BYP1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_AX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_B4->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B4", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_D->>CLBLM_M_DMUX": { + "src_wire": "CLBLM_M_D", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_FAN6->CLBLM_L_CE": { + "src_wire": "CLBLM_FAN6", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_CE", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_BMUX->CLBLM_LOGIC_OUTS21": { + "src_wire": "CLBLM_M_BMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS21", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX35->CLBLM_M_C6": { + "src_wire": "CLBLM_IMUX35", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_A5->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A5", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_A5->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A5", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_B->>CLBLM_M_BMUX": { + "src_wire": "CLBLM_M_B", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_BMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_D1->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_DQ->CLBLM_LOGIC_OUTS3": { + "src_wire": "CLBLM_L_DQ", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX41->CLBLM_L_D1": { + "src_wire": "CLBLM_IMUX41", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_FAN3->CLBLM_M_DI": { + "src_wire": "CLBLM_FAN3", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_DI", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_D6->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D6", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX18->CLBLM_M_B2": { + "src_wire": "CLBLM_IMUX18", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B2", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX44->CLBLM_M_D4": { + "src_wire": "CLBLM_IMUX44", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D4", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_BYP5->CLBLM_L_BX": { + "src_wire": "CLBLM_BYP5", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_BX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_C->>CLBLM_M_CMUX": { + "src_wire": "CLBLM_M_C", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_CMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX12->CLBLM_M_B6": { + "src_wire": "CLBLM_IMUX12", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX0->CLBLM_L_A3": { + "src_wire": "CLBLM_IMUX0", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_D2->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D2", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX24->CLBLM_M_B5": { + "src_wire": "CLBLM_IMUX24", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B5", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX42->CLBLM_L_D6": { + "src_wire": "CLBLM_IMUX42", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_CMUX->CLBLM_LOGIC_OUTS18": { + "src_wire": "CLBLM_L_CMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS18", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_B1->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_CMUX->CLBLM_LOGIC_OUTS22": { + "src_wire": "CLBLM_M_CMUX", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS22", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX43->CLBLM_M_D6": { + "src_wire": "CLBLM_IMUX43", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D6", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_C5->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C5", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_COUT->>CLBLM_M_DMUX": { + "src_wire": "CLBLM_M_COUT", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_C4->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C4", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX7->CLBLM_M_A1": { + "src_wire": "CLBLM_IMUX7", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A1", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_B3->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B3", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_A4->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A4", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_C2->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C2", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_IMUX17->CLBLM_M_B3": { + "src_wire": "CLBLM_IMUX17", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B3", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_C6->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C6", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_M_D1->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D", + "is_directional": "1", + "can_invert": "0" + }, + "CLBLM_R.CLBLM_L_B->CLBLM_LOGIC_OUTS9": { + "src_wire": "CLBLM_L_B", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS9", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CLK_BUFG_BOT_R.json b/kintex7/tile_type_CLK_BUFG_BOT_R.json new file mode 100644 index 0000000..7104490 --- /dev/null +++ b/kintex7/tile_type_CLK_BUFG_BOT_R.json @@ -0,0 +1,3569 @@ +{ + "tile_type": "CLK_BUFG_BOT_R", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL0_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL0_CE0", + "I1": "CLK_BUFG_BUFGCTRL0_I1", + "O": "CLK_BUFG_BUFGCTRL0_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL0_I0", + "S1": "CLK_BUFG_R_BUFGCTRL0_S1", + "S0": "CLK_BUFG_R_BUFGCTRL0_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL1_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL1_CE0", + "I1": "CLK_BUFG_BUFGCTRL1_I1", + "O": "CLK_BUFG_BUFGCTRL1_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL1_I0", + "S1": "CLK_BUFG_R_BUFGCTRL1_S1", + "S0": "CLK_BUFG_R_BUFGCTRL1_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 2, + "name": "X0Y2", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL2_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL2_CE0", + "I1": "CLK_BUFG_BUFGCTRL2_I1", + "O": "CLK_BUFG_BUFGCTRL2_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL2_I0", + "S1": "CLK_BUFG_R_BUFGCTRL2_S1", + "S0": "CLK_BUFG_R_BUFGCTRL2_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 3, + "name": "X0Y3", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL3_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL3_CE0", + "I1": "CLK_BUFG_BUFGCTRL3_I1", + "O": "CLK_BUFG_BUFGCTRL3_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL3_I0", + "S1": "CLK_BUFG_R_BUFGCTRL3_S1", + "S0": "CLK_BUFG_R_BUFGCTRL3_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 4, + "name": "X0Y4", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL4_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL4_CE0", + "I1": "CLK_BUFG_BUFGCTRL4_I1", + "O": "CLK_BUFG_BUFGCTRL4_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL4_I0", + "S1": "CLK_BUFG_R_BUFGCTRL4_S1", + "S0": "CLK_BUFG_R_BUFGCTRL4_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 5, + "name": "X0Y5", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL5_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL5_CE0", + "I1": "CLK_BUFG_BUFGCTRL5_I1", + "O": "CLK_BUFG_BUFGCTRL5_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL5_I0", + "S1": "CLK_BUFG_R_BUFGCTRL5_S1", + "S0": "CLK_BUFG_R_BUFGCTRL5_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 6, + "name": "X0Y6", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL6_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL6_CE0", + "I1": "CLK_BUFG_BUFGCTRL6_I1", + "O": "CLK_BUFG_BUFGCTRL6_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL6_I0", + "S1": "CLK_BUFG_R_BUFGCTRL6_S1", + "S0": "CLK_BUFG_R_BUFGCTRL6_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 7, + "name": "X0Y7", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL7_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL7_CE0", + "I1": "CLK_BUFG_BUFGCTRL7_I1", + "O": "CLK_BUFG_BUFGCTRL7_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL7_I0", + "S1": "CLK_BUFG_R_BUFGCTRL7_S1", + "S0": "CLK_BUFG_R_BUFGCTRL7_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 8, + "name": "X0Y8", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL8_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL8_CE0", + "I1": "CLK_BUFG_BUFGCTRL8_I1", + "O": "CLK_BUFG_BUFGCTRL8_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL8_I0", + "S1": "CLK_BUFG_R_BUFGCTRL8_S1", + "S0": "CLK_BUFG_R_BUFGCTRL8_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 9, + "name": "X0Y9", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL9_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL9_CE0", + "I1": "CLK_BUFG_BUFGCTRL9_I1", + "O": "CLK_BUFG_BUFGCTRL9_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL9_I0", + "S1": "CLK_BUFG_R_BUFGCTRL9_S1", + "S0": "CLK_BUFG_R_BUFGCTRL9_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 10, + "name": "X0Y10", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL10_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL10_CE0", + "I1": "CLK_BUFG_BUFGCTRL10_I1", + "O": "CLK_BUFG_BUFGCTRL10_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL10_I0", + "S1": "CLK_BUFG_R_BUFGCTRL10_S1", + "S0": "CLK_BUFG_R_BUFGCTRL10_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 11, + "name": "X0Y11", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL11_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL11_CE0", + "I1": "CLK_BUFG_BUFGCTRL11_I1", + "O": "CLK_BUFG_BUFGCTRL11_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL11_I0", + "S1": "CLK_BUFG_R_BUFGCTRL11_S1", + "S0": "CLK_BUFG_R_BUFGCTRL11_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 12, + "name": "X0Y12", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL12_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL12_CE0", + "I1": "CLK_BUFG_BUFGCTRL12_I1", + "O": "CLK_BUFG_BUFGCTRL12_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL12_I0", + "S1": "CLK_BUFG_R_BUFGCTRL12_S1", + "S0": "CLK_BUFG_R_BUFGCTRL12_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 13, + "name": "X0Y13", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL13_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL13_CE0", + "I1": "CLK_BUFG_BUFGCTRL13_I1", + "O": "CLK_BUFG_BUFGCTRL13_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL13_I0", + "S1": "CLK_BUFG_R_BUFGCTRL13_S1", + "S0": "CLK_BUFG_R_BUFGCTRL13_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 14, + "name": "X0Y14", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL14_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL14_CE0", + "I1": "CLK_BUFG_BUFGCTRL14_I1", + "O": "CLK_BUFG_BUFGCTRL14_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL14_I0", + "S1": "CLK_BUFG_R_BUFGCTRL14_S1", + "S0": "CLK_BUFG_R_BUFGCTRL14_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 15, + "name": "X0Y15", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL15_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL15_CE0", + "I1": "CLK_BUFG_BUFGCTRL15_I1", + "O": "CLK_BUFG_BUFGCTRL15_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL15_I0", + "S1": "CLK_BUFG_R_BUFGCTRL15_S1", + "S0": "CLK_BUFG_R_BUFGCTRL15_S0" + }, + "x_coord": 0 + } + ], + "wires": [ + "CLK_BUFG_R_BUFGCTRL14_S1", + "CLK_HROW_NW4A3_3", + "CLK_BUFG_R_BUFGCTRL11_IGNORE0", + "CLK_HROW_SE4C3_2", + "CLK_HROW_FAN0_3", + "CLK_BUFG_IMUX0_3", + "CLK_BUFG_CK_GCLK2", + "CLK_BUFG_R_FBG_OUT4", + "CLK_BUFG_R_BUFGCTRL11_S1", + "CLK_HROW_WW4B2_1", + "CLK_HROW_BYP4_2", + "CLK_HROW_WW4B0_0", + "CLK_BUFG_IMUX19_0", + "CLK_HROW_MONITOR_N_2", + "CLK_HROW_WW4B1_3", + "CLK_BUFG_IMUX13_0", + "CLK_BUFG_IMUX19_3", + "CLK_BUFG_LOGIC_OUTS_B23_1", + "CLK_BUFG_R_BUFGCTRL7_IGNORE0", + "CLK_HROW_LH9_1", + "CLK_HROW_NW2A1_0", + "CLK_HROW_WW2A3_1", + "CLK_HROW_SW2A1_0", + "CLK_BUFG_R_CK_FB_TEST1_10", + "CLK_HROW_NW4END1_1", + "CLK_HROW_WR1END3_1", + "CLK_BUFG_IMUX29_1", + "CLK_HROW_BYP0_2", + "CLK_HROW_SE4BEG2_0", + "CLK_BUFG_LOGIC_OUTS_B18_0", + "CLK_BUFG_LOGIC_OUTS_B6_0", + "CLK_BUFG_LOGIC_OUTS_B11_2", + "CLK_HROW_WW2A1_0", + "CLK_BUFG_R_BUFGCTRL1_CE1", + "CLK_HROW_LH11_0", + "CLK_HROW_SE4BEG1_1", + "CLK_BUFG_CK_GCLK3", + "CLK_HROW_WW4C3_3", + "CLK_BUFG_LOGIC_OUTS_B17_2", + "CLK_BUFG_LOGIC_OUTS_B16_3", + "CLK_HROW_NW4A0_2", + "CLK_BUFG_IMUX26_2", + "CLK_HROW_NE4C2_2", + "CLK_BUFG_LOGIC_OUTS_B8_2", + "CLK_HROW_EE2A2_0", + "CLK_HROW_BLOCK_OUTS_B0_2", + "CLK_HROW_LH9_0", + "CLK_HROW_NE2A2_2", + "CLK_BUFG_R_FBG_OUT11", + "CLK_HROW_WL1END2_1", + "CLK_BUFG_R_BUFGCTRL14_CE0", + "CLK_HROW_NE4C2_0", + "CLK_HROW_ER1BEG2_1", + "CLK_HROW_LH5_3", + "CLK_HROW_NE2A1_0", + "CLK_HROW_SW4END1_3", + "CLK_HROW_NW4A1_0", + "CLK_HROW_BLOCK_OUTS_B3_1", + "CLK_HROW_SW2A3_3", + "CLK_HROW_ER1BEG1_2", + "CLK_BUFG_BOT_R_CK_MUXED7", + "CLK_BUFG_LOGIC_OUTS_B23_2", + "CLK_BUFG_IMUX23_0", + "CLK_BUFG_BUFGCTRL0_I1", + "CLK_HROW_LH7_3", + "CLK_BUFG_LOGIC_OUTS_B8_3", + "CLK_HROW_SW4END0_0", + "CLK_BUFG_IMUX7_0", + "CLK_HROW_LH5_0", + "CLK_BUFG_R_BUFGCTRL10_S1", + "CLK_BUFG_BUFGCTRL1_I0", + "CLK_BUFG_BUFGCTRL7_I1", + "CLK_BUFG_IMUX43_0", + "CLK_BUFG_LOGIC_OUTS_B2_3", + "CLK_BUFG_BUFGCTRL3_I0", + "CLK_HROW_SE4C2_1", + "CLK_HROW_NW2A1_1", + "CLK_HROW_EE4BEG3_1", + "CLK_BUFG_R_BUFGCTRL9_IGNORE0", + "CLK_BUFG_LOGIC_OUTS_B19_0", + "CLK_BUFG_R_BUFGCTRL12_S1", + "CLK_HROW_NE4C1_3", + "CLK_BUFG_IMUX5_2", + "CLK_BUFG_IMUX17_1", + "CLK_HROW_SW2A1_2", + "CLK_HROW_EE2BEG2_3", + "CLK_BUFG_R_FBG_OUT6", + "CLK_HROW_EE2BEG3_0", + "CLK_HROW_WW2A3_2", + "CLK_HROW_NE4BEG1_1", + "CLK_BUFG_R_BUFGCTRL13_CE1", + "CLK_BUFG_BUFGCTRL8_O", + "CLK_BUFG_BOT_R_CK_MUXED11", + "CLK_HROW_LH10_3", + "CLK_HROW_BLOCK_OUTS_B3_0", + "CLK_HROW_EE4A3_0", + "CLK_BUFG_IMUX27_1", + "CLK_HROW_MONITOR_P_0", + "CLK_BUFG_IMUX14_2", + "CLK_HROW_NW4END1_2", + "CLK_BUFG_BOT_R_CK_MUXED21", + "CLK_BUFG_IMUX29_0", + "CLK_HROW_WW2END0_0", + "CLK_HROW_EE2A0_0", + "CLK_HROW_SE4C2_2", + "CLK_BUFG_R_BUFGCTRL3_IGNORE0", + "CLK_BUFG_R_BUFGCTRL3_CE1", + "CLK_BUFG_IMUX18_3", + "CLK_HROW_ER1BEG2_2", + "CLK_HROW_NW4A1_3", + "CLK_HROW_FAN4_2", + "CLK_HROW_WR1END3_2", + "CLK_BUFG_IMUX38_1", + "CLK_BUFG_CK_GCLK28", + "CLK_BUFG_R_BUFGCTRL14_CE1", + "CLK_HROW_SE4C1_1", + "CLK_HROW_EE2A3_2", + "CLK_BUFG_CK_GCLK1", + "CLK_HROW_FAN2_1", + "CLK_BUFG_IMUX15_1", + "CLK_HROW_ER1BEG2_3", + "CLK_HROW_EL1BEG3_2", + "CLK_HROW_NE4BEG1_0", + "CLK_HROW_NW2A3_0", + "CLK_HROW_CLK1_1", + "CLK_BUFG_R_CK_FB_TEST0_11", + "CLK_BUFG_R_BUFGCTRL10_IGNORE0", + "CLK_HROW_SE4C3_3", + "CLK_BUFG_IMUX6_1", + "CLK_HROW_SE4C0_0", + "CLK_BUFG_IMUX11_1", + "CLK_BUFG_IMUX4_2", + "CLK_HROW_SE4BEG2_1", + "CLK_BUFG_LOGIC_OUTS_B0_1", + "CLK_HROW_SE2A3_2", + "CLK_HROW_EE2A3_3", + "CLK_HROW_EE2BEG1_3", + "CLK_HROW_EL1BEG3_3", + "CLK_HROW_SE2A2_0", + "CLK_HROW_WW4END3_0", + "CLK_BUFG_LOGIC_OUTS_B7_0", + "CLK_HROW_NE4BEG1_3", + "CLK_BUFG_IMUX45_3", + "CLK_HROW_LH9_2", + "CLK_HROW_BYP6_2", + "CLK_BUFG_R_FBG_OUT15", + "CLK_HROW_SW2A1_3", + "CLK_BUFG_LOGIC_OUTS_B3_0", + "CLK_BUFG_LOGIC_OUTS_B3_1", + "CLK_HROW_BYP1_3", + "CLK_BUFG_IMUX44_3", + "CLK_BUFG_IMUX20_1", + "CLK_BUFG_BUFGCTRL10_O", + "CLK_HROW_SW4END3_0", + "CLK_BUFG_IMUX3_1", + "CLK_HROW_NE2A0_3", + "CLK_BUFG_R_CK_FB_TEST1_6", + "CLK_HROW_WW4C2_0", + "CLK_BUFG_IMUX40_0", + "CLK_BUFG_IMUX41_3", + "CLK_BUFG_LOGIC_OUTS_B5_0", + "CLK_HROW_NE4C0_2", + "CLK_HROW_SW4END0_1", + "CLK_HROW_LH1_3", + "CLK_BUFG_IMUX42_3", + "CLK_BUFG_LOGIC_OUTS_B13_0", + "CLK_BUFG_LOGIC_OUTS_B15_2", + "CLK_HROW_NW4END0_2", + "CLK_BUFG_R_BUFGCTRL9_S0", + "CLK_BUFG_IMUX34_3", + "CLK_BUFG_R_BUFGCTRL14_IGNORE0", + "CLK_BUFG_LOGIC_OUTS_B19_1", + "CLK_HROW_NE2A2_3", + "CLK_HROW_EL1BEG0_2", + "CLK_HROW_NW4END2_3", + "CLK_BUFG_IMUX43_3", + "CLK_BUFG_R_CK_FB_TEST1_8", + "CLK_BUFG_IMUX36_3", + "CLK_BUFG_LOGIC_OUTS_B11_1", + "CLK_HROW_EE4BEG2_0", + "CLK_HROW_FAN7_1", + "CLK_BUFG_LOGIC_OUTS_B7_1", + "CLK_HROW_EE2A3_1", + "CLK_BUFG_CK_GCLK25", + "CLK_HROW_WW4END0_0", + "CLK_BUFG_R_BUFGCTRL1_IGNORE0", + "CLK_HROW_SW4A2_2", + "CLK_HROW_SW2A1_1", + "CLK_BUFG_IMUX36_2", + "CLK_HROW_EE4A2_2", + "CLK_HROW_SE4C2_0", + "CLK_BUFG_IMUX37_2", + "CLK_BUFG_R_BUFGCTRL9_CE1", + "CLK_HROW_BYP1_1", + "CLK_HROW_WW4C1_2", + "CLK_BUFG_CK_GCLK17", + "CLK_BUFG_LOGIC_OUTS_B1_0", + "CLK_BUFG_BUFGCTRL14_O", + "CLK_BUFG_R_BUFGCTRL0_S1", + "CLK_HROW_BYP0_3", + "CLK_HROW_EL1BEG3_1", + "CLK_BUFG_IMUX19_2", + "CLK_BUFG_IMUX24_2", + "CLK_HROW_WW4A2_2", + "CLK_BUFG_IMUX34_0", + "CLK_HROW_SW4END1_2", + "CLK_BUFG_LOGIC_OUTS_B19_3", + "CLK_BUFG_R_BUFGCTRL11_CE1", + "CLK_BUFG_CK_GCLK26", + "CLK_BUFG_IMUX39_0", + "CLK_BUFG_LOGIC_OUTS_B5_2", + "CLK_HROW_EE2BEG3_2", + "CLK_BUFG_R_CK_FB_TEST0_7", + "CLK_BUFG_BUFGCTRL3_O", + "CLK_HROW_SE4C0_3", + "CLK_HROW_WW2A0_2", + "CLK_BUFG_LOGIC_OUTS_B1_3", + "CLK_BUFG_R_FBG_OUT9", + "CLK_BUFG_R_BUFGCTRL5_S0", + "CLK_HROW_SW4END1_1", + "CLK_HROW_SW4A0_0", + "CLK_BUFG_IMUX12_0", + "CLK_BUFG_R_BUFGCTRL0_CE0", + "CLK_HROW_WW4C1_1", + "CLK_HROW_FAN6_2", + "CLK_BUFG_IMUX21_0", + "CLK_HROW_BYP6_3", + "CLK_BUFG_IMUX2_3", + "CLK_HROW_SW4END3_2", + "CLK_HROW_EE2BEG1_2", + "CLK_HROW_SE2A1_2", + "CLK_HROW_LH9_3", + "CLK_HROW_SW4END2_2", + "CLK_HROW_EE4BEG0_3", + "CLK_BUFG_R_CK_FB_TEST1_0", + "CLK_BUFG_R_BUFGCTRL5_S1", + "CLK_BUFG_BUFGCTRL13_I0", + "CLK_BUFG_R_BUFGCTRL8_IGNORE0", + "CLK_HROW_NW4A3_0", + "CLK_HROW_WW2END1_1", + "CLK_BUFG_BOT_R_CK_MUXED23", + "CLK_HROW_WW4C0_1", + "CLK_HROW_EE4BEG2_3", + "CLK_HROW_EE4B2_1", + "CLK_HROW_EE4B2_2", + "CLK_BUFG_BOT_R_CK_MUXED6", + "CLK_BUFG_CK_GCLK0", + "CLK_BUFG_LOGIC_OUTS_B23_3", + "CLK_BUFG_CK_GCLK8", + "CLK_HROW_NE4BEG2_0", + "CLK_HROW_WW2END2_1", + "CLK_BUFG_IMUX5_1", + "CLK_HROW_FAN6_3", + "CLK_HROW_WR1END1_3", + "CLK_BUFG_BUFGCTRL3_I1", + "CLK_BUFG_IMUX24_3", + "CLK_BUFG_R_BUFGCTRL15_IGNORE0", + "CLK_HROW_WW4A1_1", + "CLK_HROW_WW4B1_1", + "CLK_HROW_FAN6_1", + "CLK_BUFG_R_CK_FB_TEST0_5", + "CLK_HROW_NW4END1_0", + "CLK_BUFG_IMUX38_3", + "CLK_HROW_LH2_3", + "CLK_BUFG_IMUX37_3", + "CLK_HROW_EL1BEG1_1", + "CLK_BUFG_IMUX9_2", + "CLK_BUFG_BUFGCTRL9_O", + "CLK_HROW_WW4B3_0", + "CLK_BUFG_CK_GCLK22", + "CLK_BUFG_IMUX31_1", + "CLK_HROW_WW4END3_2", + "CLK_BUFG_LOGIC_OUTS_B0_3", + "CLK_BUFG_CK_GCLK7", + "CLK_BUFG_R_CK_FB_TEST1_11", + "CLK_HROW_NE2A3_2", + "CLK_BUFG_R_CK_FB_TEST0_6", + "CLK_HROW_WW4END1_3", + "CLK_HROW_EE2BEG1_0", + "CLK_BUFG_BOT_R_CK_MUXED4", + "CLK_BUFG_R_FBG_OUT14", + "CLK_HROW_NW4END0_0", + "CLK_HROW_SE2A2_1", + "CLK_BUFG_BUFGCTRL1_I1", + "CLK_HROW_FAN5_0", + "CLK_BUFG_IMUX41_2", + "CLK_BUFG_IMUX26_3", + "CLK_BUFG_R_BUFGCTRL2_IGNORE1", + "CLK_HROW_SE2A0_1", + "CLK_BUFG_BUFGCTRL2_O", + "CLK_HROW_FAN2_2", + "CLK_HROW_WL1END2_0", + "CLK_HROW_LH8_1", + "CLK_BUFG_LOGIC_OUTS_B14_3", + "CLK_BUFG_IMUX16_1", + "CLK_HROW_NW4A2_1", + "CLK_HROW_NW4END0_3", + "CLK_BUFG_BOT_R_CK_MUXED18", + "CLK_HROW_ER1BEG0_1", + "CLK_BUFG_R_CK_FB_TEST0_8", + "CLK_BUFG_R_BUFGCTRL14_S0", + "CLK_HROW_BLOCK_OUTS_B0_0", + "CLK_BUFG_CK_GCLK19", + "CLK_HROW_EE2BEG3_3", + "CLK_BUFG_BOT_R_CK_MUXED29", + "CLK_HROW_EE2A0_2", + "CLK_HROW_WW2A1_3", + "CLK_HROW_BYP2_0", + "CLK_BUFG_LOGIC_OUTS_B2_1", + "CLK_HROW_LH2_0", + "CLK_BUFG_IMUX36_1", + "CLK_BUFG_LOGIC_OUTS_B0_2", + "CLK_BUFG_R_BUFGCTRL0_CE1", + "CLK_BUFG_LOGIC_OUTS_B18_3", + "CLK_BUFG_IMUX16_0", + "CLK_HROW_EE4C1_0", + "CLK_HROW_NW4END3_3", + "CLK_HROW_MONITOR_N_0", + "CLK_BUFG_LOGIC_OUTS_B3_2", + "CLK_BUFG_BOT_R_CK_MUXED20", + "CLK_HROW_WW2END3_0", + "CLK_HROW_BYP1_2", + "CLK_HROW_SW4END2_0", + "CLK_HROW_EE4B0_0", + "CLK_BUFG_IMUX43_2", + "CLK_HROW_FAN5_2", + "CLK_HROW_NW4A2_2", + "CLK_BUFG_LOGIC_OUTS_B19_2", + "CLK_BUFG_R_CK_FB_TEST0_15", + "CLK_BUFG_R_CK_FB_TEST0_0", + "CLK_HROW_EE4BEG1_2", + "CLK_BUFG_LOGIC_OUTS_B17_1", + "CLK_BUFG_R_FBG_OUT5", + "CLK_BUFG_R_CK_FB_TEST0_14", + "CLK_HROW_BLOCK_OUTS_B1_0", + "CLK_HROW_LH7_2", + "CLK_HROW_MONITOR_P_2", + "CLK_BUFG_R_BUFGCTRL3_S1", + "CLK_HROW_ER1BEG1_0", + "CLK_HROW_EE4C3_0", + "CLK_HROW_SW4A3_1", + "CLK_HROW_SE4C1_0", + "CLK_HROW_SW2A2_2", + "CLK_BUFG_IMUX23_2", + "CLK_BUFG_R_BUFGCTRL15_CE0", + "CLK_BUFG_BOT_R_CK_MUXED15", + "CLK_HROW_SW4A1_0", + "CLK_HROW_WR1END0_2", + "CLK_BUFG_IMUX38_0", + "CLK_HROW_SE4BEG3_1", + "CLK_BUFG_LOGIC_OUTS_B22_0", + "CLK_BUFG_R_CK_FB_TEST1_7", + "CLK_HROW_SW2A0_2", + "CLK_HROW_NE4C3_1", + "CLK_HROW_NW2A2_1", + "CLK_BUFG_BUFGCTRL10_I0", + "CLK_HROW_EE4C0_2", + "CLK_HROW_WR1END0_0", + "CLK_BUFG_R_BUFGCTRL9_CE0", + "CLK_HROW_WW4A1_0", + "CLK_BUFG_CK_GCLK29", + "CLK_HROW_NW2A1_2", + "CLK_HROW_LH11_3", + "CLK_BUFG_R_BUFGCTRL15_CE1", + "CLK_BUFG_BUFGCTRL7_O", + "CLK_BUFG_LOGIC_OUTS_B20_0", + "CLK_BUFG_IMUX32_3", + "CLK_BUFG_IMUX37_1", + "CLK_HROW_EE4A3_1", + "CLK_HROW_SE4BEG2_2", + "CLK_HROW_EL1BEG1_3", + "CLK_HROW_EE4B1_3", + "CLK_BUFG_IMUX2_2", + "CLK_BUFG_IMUX13_2", + "CLK_HROW_SW2A0_1", + "CLK_BUFG_BOT_R_CK_MUXED28", + "CLK_HROW_MONITOR_N_1", + "CLK_HROW_WW4A3_2", + "CLK_BUFG_R_BUFGCTRL1_IGNORE1", + "CLK_HROW_EE4B2_0", + "CLK_BUFG_R_FBG_OUT3", + "CLK_HROW_WW2END2_2", + "CLK_BUFG_R_BUFGCTRL7_CE1", + "CLK_BUFG_LOGIC_OUTS_B4_2", + "CLK_BUFG_R_BUFGCTRL6_IGNORE1", + "CLK_BUFG_R_CK_FB_TEST1_3", + "CLK_HROW_EE4C1_2", + "CLK_BUFG_R_BUFGCTRL9_S1", + "CLK_HROW_NW4END2_1", + "CLK_HROW_WL1END0_0", + "CLK_BUFG_IMUX44_2", + "CLK_HROW_FAN7_2", + "CLK_HROW_WW4C0_2", + "CLK_BUFG_LOGIC_OUTS_B21_2", + "CLK_BUFG_BUFGCTRL4_I1", + "CLK_BUFG_LOGIC_OUTS_B17_3", + "CLK_BUFG_R_BUFGCTRL15_S1", + "CLK_HROW_WW4B3_3", + "CLK_HROW_NE4BEG2_3", + "CLK_HROW_EE2BEG0_2", + "CLK_HROW_EE4C0_0", + "CLK_HROW_NE4C3_2", + "CLK_BUFG_IMUX15_3", + "CLK_HROW_FAN1_3", + "CLK_BUFG_BUFGCTRL14_I1", + "CLK_BUFG_R_BUFGCTRL3_CE0", + "CLK_HROW_LH1_2", + "CLK_BUFG_CK_GCLK23", + "CLK_HROW_SE2A3_3", + "CLK_HROW_SE4BEG3_0", + "CLK_BUFG_IMUX35_3", + "CLK_HROW_WL1END0_3", + "CLK_HROW_BYP6_1", + "CLK_HROW_ER1BEG3_0", + "CLK_HROW_WW4END1_0", + "CLK_BUFG_BOT_R_CK_MUXED16", + "CLK_HROW_FAN3_0", + "CLK_BUFG_BUFGCTRL5_O", + "CLK_BUFG_BUFGCTRL15_I1", + "CLK_BUFG_IMUX14_1", + "CLK_HROW_WR1END0_1", + "CLK_BUFG_BOT_R_CK_MUXED12", + "CLK_HROW_NE4BEG3_3", + "CLK_BUFG_BUFGCTRL13_I1", + "CLK_HROW_CLK1_3", + "CLK_BUFG_LOGIC_OUTS_B1_1", + "CLK_BUFG_LOGIC_OUTS_B6_1", + "CLK_HROW_SW2A3_2", + "CLK_HROW_EE4A1_0", + "CLK_HROW_EL1BEG2_2", + "CLK_BUFG_R_BUFGCTRL4_IGNORE1", + "CLK_BUFG_R_BUFGCTRL1_S0", + "CLK_HROW_WW4A0_3", + "CLK_HROW_WW2A3_0", + "CLK_BUFG_IMUX46_2", + "CLK_HROW_EE2BEG0_0", + "CLK_HROW_WW4B2_0", + "CLK_HROW_EE4BEG0_1", + "CLK_HROW_WW2END0_1", + "CLK_HROW_ER1BEG0_0", + "CLK_HROW_SE4BEG1_3", + "CLK_BUFG_R_BUFGCTRL2_S1", + "CLK_BUFG_IMUX14_0", + "CLK_HROW_WW4A3_0", + "CLK_BUFG_IMUX16_3", + "CLK_BUFG_LOGIC_OUTS_B21_1", + "CLK_HROW_EE4C1_1", + "CLK_HROW_BYP7_3", + "CLK_HROW_WW4C3_1", + "CLK_HROW_NE4BEG3_2", + "CLK_HROW_WW2A0_3", + "CLK_BUFG_IMUX44_1", + "CLK_BUFG_R_BUFGCTRL2_IGNORE0", + "CLK_HROW_WW2A2_3", + "CLK_BUFG_LOGIC_OUTS_B10_1", + "CLK_HROW_FAN3_2", + "CLK_BUFG_LOGIC_OUTS_B23_0", + "CLK_HROW_EE2A1_1", + "CLK_HROW_EE4B0_2", + "CLK_HROW_WL1END3_1", + "CLK_HROW_EE2A0_3", + "CLK_BUFG_R_BUFGCTRL11_S0", + "CLK_BUFG_CK_GCLK18", + "CLK_BUFG_BOT_R_CK_MUXED26", + "CLK_HROW_EE4A0_0", + "CLK_HROW_WW4END2_2", + "CLK_BUFG_IMUX11_0", + "CLK_BUFG_R_BUFGCTRL10_CE1", + "CLK_HROW_SE2A1_3", + "CLK_BUFG_IMUX31_2", + "CLK_HROW_BLOCK_OUTS_B1_3", + "CLK_HROW_WW4C2_1", + "CLK_HROW_SW2A2_0", + "CLK_HROW_EE2BEG2_1", + "CLK_BUFG_CK_GCLK12", + "CLK_BUFG_IMUX11_2", + "CLK_BUFG_BOT_R_CK_MUXED19", + "CLK_BUFG_R_BUFGCTRL13_CE0", + "CLK_BUFG_BUFGCTRL10_I1", + "CLK_BUFG_BUFGCTRL5_I1", + "CLK_HROW_WW4B2_3", + "CLK_HROW_SW4A1_2", + "CLK_BUFG_R_BUFGCTRL3_S0", + "CLK_HROW_CLK0_1", + "CLK_BUFG_LOGIC_OUTS_B5_3", + "CLK_HROW_NW4A2_0", + "CLK_BUFG_R_BUFGCTRL12_IGNORE1", + "CLK_BUFG_R_BUFGCTRL4_S0", + "CLK_BUFG_IMUX5_3", + "CLK_HROW_WL1END1_0", + "CLK_HROW_SE2A2_3", + "CLK_BUFG_R_BUFGCTRL15_S0", + "CLK_BUFG_IMUX27_2", + "CLK_HROW_WW4C3_0", + "CLK_BUFG_R_CK_FB_TEST0_12", + "CLK_BUFG_IMUX0_0", + "CLK_HROW_BLOCK_OUTS_B0_1", + "CLK_BUFG_R_BUFGCTRL8_CE1", + "CLK_HROW_WW4END3_1", + "CLK_HROW_EE4BEG2_2", + "CLK_BUFG_R_FBG_OUT7", + "CLK_HROW_NW4A0_3", + "CLK_HROW_FAN4_0", + "CLK_HROW_NW4A1_1", + "CLK_BUFG_IMUX12_1", + "CLK_BUFG_IMUX40_3", + "CLK_HROW_WW4A2_1", + "CLK_BUFG_BOT_R_CK_MUXED13", + "CLK_BUFG_IMUX8_3", + "CLK_HROW_NW2A0_0", + "CLK_HROW_NE4BEG1_2", + "CLK_HROW_BYP4_3", + "CLK_BUFG_IMUX7_3", + "CLK_BUFG_BUFGCTRL5_I0", + "CLK_BUFG_R_BUFGCTRL14_IGNORE1", + "CLK_HROW_FAN5_1", + "CLK_HROW_WW4B3_1", + "CLK_BUFG_LOGIC_OUTS_B11_3", + "CLK_BUFG_IMUX40_1", + "CLK_HROW_WW4END0_1", + "CLK_HROW_NE2A3_3", + "CLK_BUFG_R_BUFGCTRL5_IGNORE0", + "CLK_BUFG_BOT_R_CK_MUXED25", + "CLK_BUFG_R_BUFGCTRL6_IGNORE0", + "CLK_BUFG_LOGIC_OUTS_B12_2", + "CLK_BUFG_BUFGCTRL15_I0", + "CLK_HROW_EE4BEG1_3", + "CLK_HROW_WR1END3_3", + "CLK_HROW_SW4END1_0", + "CLK_BUFG_IMUX28_3", + "CLK_HROW_MONITOR_P_1", + "CLK_HROW_BYP2_3", + "CLK_BUFG_BUFGCTRL0_I0", + "CLK_BUFG_R_FBG_OUT13", + "CLK_BUFG_R_BUFGCTRL9_IGNORE1", + "CLK_HROW_WW4END2_0", + "CLK_BUFG_BUFGCTRL0_O", + "CLK_BUFG_IMUX33_3", + "CLK_BUFG_IMUX25_1", + "CLK_HROW_WW4END3_3", + "CLK_BUFG_R_BUFGCTRL4_CE1", + "CLK_BUFG_R_FBG_OUT10", + "CLK_BUFG_IMUX1_0", + "CLK_HROW_EE4A0_1", + "CLK_HROW_LH3_3", + "CLK_HROW_BYP0_0", + "CLK_BUFG_IMUX32_2", + "CLK_BUFG_R_BUFGCTRL11_CE0", + "CLK_BUFG_LOGIC_OUTS_B18_2", + "CLK_HROW_NW2A0_1", + "CLK_BUFG_BUFGCTRL2_I0", + "CLK_BUFG_BUFGCTRL2_I1", + "CLK_HROW_EE4A2_3", + "CLK_HROW_FAN6_0", + "CLK_BUFG_LOGIC_OUTS_B21_3", + "CLK_HROW_WW4C0_0", + "CLK_BUFG_CK_GCLK9", + "CLK_HROW_WL1END0_2", + "CLK_HROW_EE2BEG3_1", + "CLK_HROW_EE4A2_0", + "CLK_HROW_EE4B3_0", + "CLK_BUFG_BUFGCTRL8_I1", + "CLK_BUFG_IMUX30_1", + "CLK_BUFG_IMUX2_1", + "CLK_HROW_LH4_0", + "CLK_BUFG_LOGIC_OUTS_B21_0", + "CLK_BUFG_IMUX45_1", + "CLK_BUFG_LOGIC_OUTS_B16_2", + "CLK_BUFG_R_BUFGCTRL10_IGNORE1", + "CLK_HROW_CTRL0_1", + "CLK_BUFG_IMUX46_3", + "CLK_BUFG_IMUX42_2", + "CLK_BUFG_IMUX3_2", + "CLK_BUFG_BUFGCTRL6_I1", + "CLK_HROW_NE2A1_3", + "CLK_HROW_SE4C0_1", + "CLK_BUFG_IMUX27_3", + "CLK_HROW_SE2A0_3", + "CLK_HROW_LH8_0", + "CLK_HROW_LH12_1", + "CLK_HROW_WW2END3_3", + "CLK_HROW_NE4C0_0", + "CLK_BUFG_IMUX41_1", + "CLK_HROW_LH11_2", + "CLK_HROW_NE2A1_2", + "CLK_BUFG_R_BUFGCTRL3_IGNORE1", + "CLK_HROW_NE2A0_0", + "CLK_HROW_WW4END0_3", + "CLK_HROW_EE4C0_1", + "CLK_BUFG_IMUX17_0", + "CLK_BUFG_BOT_R_CK_MUXED17", + "CLK_BUFG_LOGIC_OUTS_B7_2", + "CLK_HROW_NE4BEG0_1", + "CLK_BUFG_IMUX35_1", + "CLK_HROW_WL1END3_0", + "CLK_BUFG_IMUX36_0", + "CLK_HROW_SE4BEG2_3", + "CLK_HROW_WW2A0_0", + "CLK_BUFG_IMUX47_3", + "CLK_HROW_EE2A1_2", + "CLK_BUFG_R_BUFGCTRL4_CE0", + "CLK_HROW_SW2A0_0", + "CLK_HROW_EE2A0_1", + "CLK_HROW_SW4A2_1", + "CLK_HROW_FAN0_1", + "CLK_HROW_EE2BEG2_2", + "CLK_HROW_WL1END0_1", + "CLK_HROW_WL1END2_3", + "CLK_BUFG_LOGIC_OUTS_B15_3", + "CLK_HROW_WL1END1_1", + "CLK_HROW_BYP6_0", + "CLK_BUFG_R_CK_FB_TEST1_14", + "CLK_HROW_NW4END2_2", + "CLK_BUFG_LOGIC_OUTS_B6_2", + "CLK_BUFG_R_CK_FB_TEST0_2", + "CLK_HROW_NE4C1_1", + "CLK_BUFG_IMUX33_1", + "CLK_HROW_EE4C2_2", + "CLK_BUFG_IMUX10_2", + "CLK_BUFG_IMUX30_3", + "CLK_HROW_LH3_2", + "CLK_HROW_BLOCK_OUTS_B2_1", + "CLK_BUFG_IMUX21_3", + "CLK_HROW_SW4END0_2", + "CLK_HROW_SW4A0_2", + "CLK_BUFG_CK_GCLK11", + "CLK_BUFG_R_BUFGCTRL8_IGNORE1", + "CLK_HROW_CTRL0_0", + "CLK_BUFG_IMUX8_1", + "CLK_BUFG_LOGIC_OUTS_B5_1", + "CLK_BUFG_R_BUFGCTRL2_S0", + "CLK_HROW_LH2_1", + "CLK_BUFG_IMUX2_0", + "CLK_BUFG_IMUX8_0", + "CLK_BUFG_IMUX20_2", + "CLK_BUFG_R_BUFGCTRL2_CE0", + "CLK_BUFG_IMUX4_3", + "CLK_HROW_NW4A0_0", + "CLK_HROW_WW4C1_3", + "CLK_BUFG_LOGIC_OUTS_B1_2", + "CLK_HROW_SE2A3_0", + "CLK_BUFG_LOGIC_OUTS_B11_0", + "CLK_HROW_EE4BEG0_2", + "CLK_HROW_EE4C2_3", + "CLK_HROW_EL1BEG0_3", + "CLK_HROW_WW4A0_0", + "CLK_HROW_WW2A3_3", + "CLK_BUFG_LOGIC_OUTS_B4_3", + "CLK_BUFG_BUFGCTRL14_I0", + "CLK_HROW_WR1END2_0", + "CLK_HROW_LH10_0", + "CLK_BUFG_R_BUFGCTRL12_IGNORE0", + "CLK_HROW_WW4B0_3", + "CLK_BUFG_IMUX9_1", + "CLK_BUFG_R_FBG_OUT2", + "CLK_HROW_NW2A3_1", + "CLK_HROW_EE4C1_3", + "CLK_HROW_FAN7_0", + "CLK_HROW_WW2A1_2", + "CLK_BUFG_R_CK_FB_TEST1_13", + "CLK_HROW_EE4C0_3", + "CLK_HROW_FAN5_3", + "CLK_HROW_NE2A3_0", + "CLK_HROW_SW4A2_0", + "CLK_BUFG_R_BUFGCTRL13_IGNORE1", + "CLK_HROW_WW2END2_3", + "CLK_HROW_CLK0_3", + "CLK_BUFG_R_BUFGCTRL4_S1", + "CLK_BUFG_CK_GCLK14", + "CLK_BUFG_IMUX34_1", + "CLK_BUFG_R_BUFGCTRL5_CE1", + "CLK_BUFG_LOGIC_OUTS_B0_0", + "CLK_HROW_WL1END3_3", + "CLK_HROW_LH2_2", + "CLK_HROW_WW2END0_3", + "CLK_BUFG_IMUX11_3", + "CLK_HROW_EE4BEG0_0", + "CLK_HROW_CTRL1_0", + "CLK_BUFG_IMUX15_0", + "CLK_HROW_SE4BEG0_3", + "CLK_HROW_BLOCK_OUTS_B1_1", + "CLK_HROW_EE4BEG2_1", + "CLK_BUFG_R_BUFGCTRL7_CE0", + "CLK_BUFG_IMUX28_0", + "CLK_BUFG_IMUX18_0", + "CLK_BUFG_LOGIC_OUTS_B16_0", + "CLK_HROW_NW2A0_3", + "CLK_BUFG_IMUX25_3", + "CLK_BUFG_IMUX20_0", + "CLK_HROW_BYP7_0", + "CLK_HROW_EE4B3_3", + "CLK_HROW_LH7_1", + "CLK_BUFG_IMUX7_1", + "CLK_HROW_SE4BEG3_3", + "CLK_BUFG_BOT_R_CK_MUXED10", + "CLK_BUFG_R_BUFGCTRL2_CE1", + "CLK_HROW_SW4A0_1", + "CLK_HROW_EE2BEG1_1", + "CLK_HROW_SW4END2_3", + "CLK_BUFG_CK_GCLK20", + "CLK_HROW_LH8_3", + "CLK_HROW_SE4C2_3", + "CLK_BUFG_R_BUFGCTRL13_S1", + "CLK_HROW_EE4BEG1_1", + "CLK_HROW_BYP5_1", + "CLK_BUFG_IMUX0_2", + "CLK_HROW_BLOCK_OUTS_B2_3", + "CLK_BUFG_LOGIC_OUTS_B22_1", + "CLK_BUFG_BOT_R_CK_MUXED14", + "CLK_BUFG_IMUX29_2", + "CLK_HROW_NW2A3_2", + "CLK_BUFG_R_CK_FB_TEST1_5", + "CLK_BUFG_LOGIC_OUTS_B8_1", + "CLK_HROW_EE4C3_3", + "CLK_BUFG_IMUX32_1", + "CLK_BUFG_BUFGCTRL4_O", + "CLK_HROW_SW4A2_3", + "CLK_BUFG_R_BUFGCTRL11_IGNORE1", + "CLK_BUFG_IMUX6_0", + "CLK_HROW_EL1BEG0_1", + "CLK_BUFG_BUFGCTRL6_I0", + "CLK_BUFG_IMUX31_0", + "CLK_HROW_FAN2_3", + "CLK_HROW_FAN4_1", + "CLK_BUFG_IMUX16_2", + "CLK_BUFG_LOGIC_OUTS_B20_2", + "CLK_BUFG_IMUX45_0", + "CLK_BUFG_IMUX24_0", + "CLK_BUFG_CK_GCLK16", + "CLK_HROW_BLOCK_OUTS_B3_2", + "CLK_BUFG_R_BUFGCTRL10_S0", + "CLK_BUFG_R_BUFGCTRL10_CE0", + "CLK_BUFG_BOT_R_CK_MUXED31", + "CLK_HROW_WW4A3_3", + "CLK_BUFG_IMUX47_0", + "CLK_HROW_WW4C2_3", + "CLK_BUFG_IMUX19_1", + "CLK_HROW_WW4B0_2", + "CLK_HROW_LH8_2", + "CLK_HROW_EL1BEG3_0", + "CLK_HROW_EL1BEG1_0", + "CLK_HROW_EE4B0_1", + "CLK_BUFG_LOGIC_OUTS_B7_3", + "CLK_HROW_LH1_0", + "CLK_HROW_LH12_2", + "CLK_BUFG_IMUX42_0", + "CLK_HROW_WW2A0_1", + "CLK_HROW_WW2END3_2", + "CLK_BUFG_IMUX25_0", + "CLK_BUFG_IMUX15_2", + "CLK_HROW_LH6_2", + "CLK_BUFG_BUFGCTRL6_O", + "CLK_BUFG_IMUX14_3", + "CLK_HROW_FAN2_0", + "CLK_HROW_SE4BEG0_2", + "CLK_BUFG_BOT_R_CK_MUXED5", + "CLK_HROW_BYP3_0", + "CLK_HROW_EE4B0_3", + "CLK_BUFG_IMUX34_2", + "CLK_BUFG_LOGIC_OUTS_B22_3", + "CLK_BUFG_LOGIC_OUTS_B9_1", + "CLK_HROW_MONITOR_N_3", + "CLK_HROW_FAN1_2", + "CLK_BUFG_R_BUFGCTRL1_S1", + "CLK_BUFG_IMUX5_0", + "CLK_BUFG_IMUX3_0", + "CLK_HROW_NW2A3_3", + "CLK_BUFG_CK_GCLK4", + "CLK_HROW_BYP4_1", + "CLK_BUFG_IMUX43_1", + "CLK_HROW_LH6_1", + "CLK_BUFG_R_BUFGCTRL8_S1", + "CLK_HROW_EE4B3_1", + "CLK_BUFG_CK_GCLK24", + "CLK_BUFG_BUFGCTRL12_I0", + "CLK_HROW_LH3_1", + "CLK_HROW_NE4C2_1", + "CLK_BUFG_IMUX30_2", + "CLK_HROW_MONITOR_P_3", + "CLK_HROW_WW4C3_2", + "CLK_BUFG_R_BUFGCTRL7_IGNORE1", + "CLK_BUFG_BUFGCTRL4_I0", + "CLK_HROW_EE4BEG3_2", + "CLK_HROW_SE4C3_0", + "CLK_HROW_NE4BEG0_3", + "CLK_BUFG_IMUX47_1", + "CLK_BUFG_LOGIC_OUTS_B9_2", + "CLK_BUFG_CK_GCLK5", + "CLK_BUFG_IMUX33_0", + "CLK_BUFG_IMUX9_3", + "CLK_BUFG_BOT_R_CK_MUXED2", + "CLK_BUFG_R_CK_FB_TEST1_12", + "CLK_HROW_WW2END3_1", + "CLK_HROW_WW4B2_2", + "CLK_BUFG_BUFGCTRL11_I0", + "CLK_HROW_WW2END1_3", + "CLK_HROW_EE4A1_1", + "CLK_HROW_NW2A0_2", + "CLK_BUFG_IMUX4_1", + "CLK_BUFG_IMUX10_1", + "CLK_HROW_CLK0_0", + "CLK_HROW_NE2A2_1", + "CLK_HROW_BYP0_1", + "CLK_HROW_EE4A3_3", + "CLK_HROW_CLK1_0", + "CLK_HROW_NE4C0_1", + "CLK_BUFG_LOGIC_OUTS_B12_0", + "CLK_BUFG_LOGIC_OUTS_B20_3", + "CLK_HROW_FAN0_0", + "CLK_HROW_SE4BEG1_2", + "CLK_BUFG_IMUX22_2", + "CLK_BUFG_IMUX40_2", + "CLK_HROW_CTRL0_3", + "CLK_BUFG_LOGIC_OUTS_B10_2", + "CLK_HROW_WW4B1_2", + "CLK_BUFG_LOGIC_OUTS_B17_0", + "CLK_BUFG_LOGIC_OUTS_B14_0", + "CLK_BUFG_IMUX23_3", + "CLK_BUFG_R_BUFGCTRL0_S0", + "CLK_BUFG_LOGIC_OUTS_B14_1", + "CLK_BUFG_IMUX46_0", + "CLK_HROW_LH7_0", + "CLK_BUFG_R_BUFGCTRL12_CE1", + "CLK_HROW_WW4A3_1", + "CLK_BUFG_R_BUFGCTRL1_CE0", + "CLK_BUFG_IMUX30_0", + "CLK_HROW_LH6_3", + "CLK_BUFG_IMUX1_1", + "CLK_BUFG_BOT_R_CK_MUXED1", + "CLK_BUFG_BOT_R_CK_MUXED30", + "CLK_BUFG_R_BUFGCTRL0_IGNORE1", + "CLK_HROW_ER1BEG0_3", + "CLK_HROW_SW4END0_3", + "CLK_BUFG_IMUX32_0", + "CLK_BUFG_R_CK_FB_TEST1_1", + "CLK_HROW_EL1BEG2_1", + "CLK_HROW_EE2A2_2", + "CLK_BUFG_R_CK_FB_TEST0_4", + "CLK_HROW_SE4BEG1_0", + "CLK_HROW_BYP2_1", + "CLK_BUFG_CK_GCLK6", + "CLK_BUFG_R_CK_FB_TEST0_10", + "CLK_HROW_NE4C2_3", + "CLK_HROW_SW4END3_3", + "CLK_HROW_SE4C1_2", + "CLK_HROW_SE4C1_3", + "CLK_BUFG_CK_GCLK13", + "CLK_BUFG_IMUX1_2", + "CLK_BUFG_IMUX45_2", + "CLK_BUFG_IMUX18_2", + "CLK_HROW_EL1BEG0_0", + "CLK_HROW_EE4A1_2", + "CLK_HROW_CLK0_2", + "CLK_BUFG_IMUX10_3", + "CLK_HROW_WW4END1_2", + "CLK_BUFG_LOGIC_OUTS_B15_1", + "CLK_BUFG_IMUX18_1", + "CLK_HROW_BYP1_0", + "CLK_HROW_EE4C3_2", + "CLK_HROW_WW2END0_2", + "CLK_BUFG_BOT_R_CK_MUXED9", + "CLK_HROW_NE4BEG3_1", + "CLK_HROW_BYP3_1", + "CLK_BUFG_BUFGCTRL8_I0", + "CLK_BUFG_R_BUFGCTRL8_CE0", + "CLK_BUFG_IMUX17_2", + "CLK_HROW_WW4B3_2", + "CLK_BUFG_IMUX39_1", + "CLK_HROW_WW4B0_1", + "CLK_HROW_BYP3_3", + "CLK_BUFG_IMUX39_3", + "CLK_BUFG_IMUX21_2", + "CLK_BUFG_BOT_R_CK_MUXED3", + "CLK_HROW_EL1BEG2_3", + "CLK_HROW_WW2A2_2", + "CLK_BUFG_IMUX9_0", + "CLK_HROW_SW4A3_3", + "CLK_HROW_BYP5_2", + "CLK_HROW_NW2A1_3", + "CLK_BUFG_LOGIC_OUTS_B12_3", + "CLK_HROW_WR1END1_1", + "CLK_BUFG_R_BUFGCTRL6_S1", + "CLK_HROW_SE2A1_1", + "CLK_HROW_WW4END0_2", + "CLK_HROW_NW2A2_0", + "CLK_HROW_SE2A3_1", + "CLK_BUFG_LOGIC_OUTS_B13_3", + "CLK_BUFG_BUFGCTRL11_I1", + "CLK_HROW_NW4A1_2", + "CLK_BUFG_IMUX46_1", + "CLK_HROW_EE4BEG3_0", + "CLK_HROW_LH11_1", + "CLK_HROW_NW2A2_3", + "CLK_HROW_BLOCK_OUTS_B2_0", + "CLK_HROW_WR1END2_3", + "CLK_HROW_EE2A1_0", + "CLK_HROW_NW4A0_1", + "CLK_HROW_NE4C0_3", + "CLK_HROW_WW4END1_1", + "CLK_HROW_FAN3_1", + "CLK_HROW_BYP5_0", + "CLK_HROW_NE4BEG2_2", + "CLK_BUFG_R_CK_FB_TEST1_15", + "CLK_HROW_SE4BEG3_2", + "CLK_BUFG_R_BUFGCTRL13_IGNORE0", + "CLK_BUFG_BOT_R_CK_MUXED27", + "CLK_HROW_WL1END3_2", + "CLK_HROW_EE4A2_1", + "CLK_HROW_SE4BEG0_0", + "CLK_BUFG_IMUX35_2", + "CLK_BUFG_IMUX10_0", + "CLK_HROW_SW2A2_3", + "CLK_HROW_WW4C1_0", + "CLK_BUFG_R_BUFGCTRL13_S0", + "CLK_HROW_WR1END2_1", + "CLK_HROW_WW4A1_2", + "CLK_BUFG_IMUX6_3", + "CLK_HROW_NW4END1_3", + "CLK_BUFG_LOGIC_OUTS_B4_1", + "CLK_HROW_EE4B3_2", + "CLK_BUFG_R_BUFGCTRL7_S0", + "CLK_BUFG_R_FBG_OUT0", + "CLK_HROW_EE4B1_1", + "CLK_HROW_NE2A0_1", + "CLK_BUFG_IMUX22_3", + "CLK_HROW_NW4A2_3", + "CLK_HROW_SE2A0_0", + "CLK_BUFG_IMUX26_1", + "CLK_BUFG_R_CK_FB_TEST0_9", + "CLK_BUFG_IMUX47_2", + "CLK_BUFG_R_FBG_OUT8", + "CLK_BUFG_IMUX22_1", + "CLK_HROW_SW4END2_1", + "CLK_HROW_SW4A1_3", + "CLK_HROW_SW4A0_3", + "CLK_HROW_LH10_2", + "CLK_BUFG_IMUX27_0", + "CLK_HROW_CTRL1_2", + "CLK_HROW_NE4C1_0", + "CLK_BUFG_IMUX7_2", + "CLK_HROW_EE4B1_2", + "CLK_BUFG_LOGIC_OUTS_B2_0", + "CLK_HROW_SE4C0_2", + "CLK_HROW_EE4A0_3", + "CLK_HROW_NE4BEG2_1", + "CLK_BUFG_BUFGCTRL12_O", + "CLK_BUFG_LOGIC_OUTS_B4_0", + "CLK_HROW_WW2A2_0", + "CLK_BUFG_BUFGCTRL7_I0", + "CLK_BUFG_IMUX24_1", + "CLK_HROW_ER1BEG1_1", + "CLK_BUFG_R_BUFGCTRL12_S0", + "CLK_BUFG_LOGIC_OUTS_B10_0", + "CLK_HROW_NW4A3_2", + "CLK_BUFG_R_BUFGCTRL8_S0", + "CLK_BUFG_LOGIC_OUTS_B6_3", + "CLK_HROW_FAN1_1", + "CLK_HROW_NW4A3_1", + "CLK_BUFG_CK_GCLK21", + "CLK_HROW_NW4END2_0", + "CLK_BUFG_IMUX13_1", + "CLK_HROW_BYP2_2", + "CLK_HROW_EE2A2_1", + "CLK_BUFG_LOGIC_OUTS_B14_2", + "CLK_HROW_CTRL1_1", + "CLK_HROW_WW2A1_1", + "CLK_HROW_EE2A3_0", + "CLK_HROW_SW4A3_2", + "CLK_BUFG_IMUX39_2", + "CLK_HROW_EE4BEG3_3", + "CLK_BUFG_LOGIC_OUTS_B22_2", + "CLK_BUFG_R_BUFGCTRL6_S0", + "CLK_HROW_WW4C2_2", + "CLK_BUFG_R_BUFGCTRL6_CE0", + "CLK_BUFG_LOGIC_OUTS_B13_1", + "CLK_HROW_CTRL1_3", + "CLK_BUFG_R_BUFGCTRL12_CE0", + "CLK_BUFG_BUFGCTRL9_I0", + "CLK_BUFG_LOGIC_OUTS_B16_1", + "CLK_BUFG_IMUX23_1", + "CLK_BUFG_IMUX38_2", + "CLK_BUFG_IMUX3_3", + "CLK_HROW_NW4END0_1", + "CLK_HROW_SW2A3_1", + "CLK_BUFG_IMUX33_2", + "CLK_BUFG_IMUX31_3", + "CLK_HROW_SW2A2_1", + "CLK_HROW_WR1END3_0", + "CLK_HROW_SW2A3_0", + "CLK_BUFG_R_CK_FB_TEST0_1", + "CLK_BUFG_BOT_R_CK_MUXED8", + "CLK_BUFG_CK_GCLK30", + "CLK_HROW_EL1BEG2_0", + "CLK_BUFG_CK_GCLK10", + "CLK_HROW_LH12_0", + "CLK_HROW_WR1END1_0", + "CLK_HROW_NW4END3_1", + "CLK_HROW_EE2A2_3", + "CLK_HROW_LH4_3", + "CLK_BUFG_IMUX35_0", + "CLK_HROW_SW4A1_1", + "CLK_BUFG_BUFGCTRL13_O", + "CLK_BUFG_R_FBG_OUT12", + "CLK_HROW_ER1BEG1_3", + "CLK_HROW_EE4A1_3", + "CLK_BUFG_IMUX21_1", + "CLK_HROW_EE2BEG0_3", + "CLK_HROW_SW2A0_3", + "CLK_BUFG_IMUX0_1", + "CLK_BUFG_BOT_R_CK_MUXED0", + "CLK_HROW_NE4BEG0_2", + "CLK_BUFG_LOGIC_OUTS_B20_1", + "CLK_HROW_NE2A3_1", + "CLK_HROW_EE4C2_0", + "CLK_BUFG_IMUX28_2", + "CLK_HROW_WW4A0_1", + "CLK_HROW_WW2END2_0", + "CLK_BUFG_BUFGCTRL1_O", + "CLK_HROW_NW4END3_2", + "CLK_HROW_LH3_0", + "CLK_HROW_WW4A2_3", + "CLK_HROW_EE2A1_3", + "CLK_HROW_BYP7_2", + "CLK_BUFG_LOGIC_OUTS_B8_0", + "CLK_BUFG_IMUX12_3", + "CLK_BUFG_BOT_R_CK_MUXED24", + "CLK_HROW_WL1END1_2", + "CLK_BUFG_R_FBG_OUT1", + "CLK_BUFG_LOGIC_OUTS_B3_3", + "CLK_BUFG_R_BUFGCTRL0_IGNORE0", + "CLK_HROW_EL1BEG1_2", + "CLK_HROW_LH12_3", + "CLK_HROW_SE2A2_2", + "CLK_BUFG_IMUX29_3", + "CLK_HROW_FAN7_3", + "CLK_HROW_ER1BEG0_2", + "CLK_HROW_EE4A0_2", + "CLK_BUFG_LOGIC_OUTS_B9_3", + "CLK_BUFG_CK_GCLK27", + "CLK_BUFG_R_BUFGCTRL5_CE0", + "CLK_BUFG_IMUX44_0", + "CLK_HROW_NE2A0_2", + "CLK_HROW_WW4END2_3", + "CLK_HROW_SW4END3_1", + "CLK_BUFG_IMUX25_2", + "CLK_HROW_LH6_0", + "CLK_HROW_ER1BEG3_3", + "CLK_HROW_NE4C1_2", + "CLK_HROW_WW2END1_0", + "CLK_HROW_BLOCK_OUTS_B3_3", + "CLK_BUFG_R_CK_FB_TEST1_4", + "CLK_HROW_WL1END2_2", + "CLK_BUFG_IMUX42_1", + "CLK_HROW_WW4A1_3", + "CLK_HROW_WW4C0_3", + "CLK_BUFG_IMUX4_0", + "CLK_HROW_LH4_1", + "CLK_BUFG_IMUX37_0", + "CLK_HROW_SE2A0_2", + "CLK_BUFG_BOT_R_CK_MUXED22", + "CLK_HROW_BLOCK_OUTS_B1_2", + "CLK_BUFG_R_BUFGCTRL6_CE1", + "CLK_HROW_LH5_2", + "CLK_HROW_NW2A2_2", + "CLK_HROW_SE2A1_0", + "CLK_HROW_WW4B1_0", + "CLK_HROW_ER1BEG3_2", + "CLK_HROW_BLOCK_OUTS_B0_3", + "CLK_BUFG_CK_GCLK15", + "CLK_HROW_LH4_2", + "CLK_HROW_BYP4_0", + "CLK_BUFG_R_CK_FB_TEST0_3", + "CLK_HROW_WR1END0_3", + "CLK_HROW_WL1END1_3", + "CLK_HROW_EE4BEG1_0", + "CLK_BUFG_IMUX1_3", + "CLK_HROW_NW4END3_0", + "CLK_BUFG_LOGIC_OUTS_B12_1", + "CLK_BUFG_IMUX12_2", + "CLK_HROW_FAN1_0", + "CLK_HROW_FAN3_3", + "CLK_BUFG_LOGIC_OUTS_B10_3", + "CLK_HROW_LH1_1", + "CLK_HROW_WW4END2_1", + "CLK_BUFG_R_BUFGCTRL7_S1", + "CLK_BUFG_IMUX26_0", + "CLK_BUFG_LOGIC_OUTS_B9_0", + "CLK_HROW_EE4C3_1", + "CLK_BUFG_R_BUFGCTRL15_IGNORE1", + "CLK_BUFG_R_BUFGCTRL5_IGNORE1", + "CLK_HROW_CTRL0_2", + "CLK_BUFG_LOGIC_OUTS_B13_2", + "CLK_HROW_SE4C3_1", + "CLK_HROW_FAN4_3", + "CLK_HROW_WW2A2_1", + "CLK_HROW_FAN0_2", + "CLK_HROW_WW4A2_0", + "CLK_BUFG_IMUX22_0", + "CLK_HROW_LH5_1", + "CLK_HROW_EE4B2_3", + "CLK_HROW_BYP3_2", + "CLK_BUFG_LOGIC_OUTS_B2_2", + "CLK_HROW_BLOCK_OUTS_B2_2", + "CLK_HROW_NE2A2_0", + "CLK_HROW_EE2BEG2_0", + "CLK_BUFG_IMUX41_0", + "CLK_BUFG_IMUX20_3", + "CLK_BUFG_LOGIC_OUTS_B18_1", + "CLK_BUFG_IMUX8_2", + "CLK_HROW_LH10_1", + "CLK_HROW_BYP7_1", + "CLK_HROW_NE4C3_3", + "CLK_HROW_SW4A3_0", + "CLK_BUFG_R_CK_FB_TEST1_9", + "CLK_BUFG_IMUX13_3", + "CLK_BUFG_R_BUFGCTRL4_IGNORE0", + "CLK_BUFG_IMUX28_1", + "CLK_BUFG_BUFGCTRL11_O", + "CLK_HROW_NE4BEG3_0", + "CLK_HROW_BYP5_3", + "CLK_BUFG_BUFGCTRL12_I1", + "CLK_HROW_SE4BEG0_1", + "CLK_HROW_WR1END2_2", + "CLK_HROW_EE4A3_2", + "CLK_BUFG_CK_GCLK31", + "CLK_HROW_ER1BEG3_1", + "CLK_BUFG_IMUX6_2", + "CLK_BUFG_LOGIC_OUTS_B15_0", + "CLK_BUFG_R_CK_FB_TEST0_13", + "CLK_HROW_WR1END1_2", + "CLK_BUFG_IMUX17_3", + "CLK_HROW_EE2BEG0_1", + "CLK_HROW_ER1BEG2_0", + "CLK_HROW_WW2END1_2", + "CLK_BUFG_R_CK_FB_TEST1_2", + "CLK_HROW_NE4BEG0_0", + "CLK_HROW_EE4B1_0", + "CLK_HROW_NE2A1_1", + "CLK_HROW_EE4C2_1", + "CLK_HROW_NE4C3_0", + "CLK_HROW_CLK1_2", + "CLK_BUFG_BUFGCTRL15_O", + "CLK_HROW_WW4A0_2", + "CLK_BUFG_BUFGCTRL9_I1" + ], + "pips": { + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_2->>CLK_BUFG_R_BUFGCTRL10_CE1": { + "src_wire": "CLK_BUFG_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I1": { + "src_wire": "CLK_BUFG_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_2->>CLK_BUFG_R_BUFGCTRL10_S0": { + "src_wire": "CLK_BUFG_IMUX6_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_0->>CLK_BUFG_R_BUFGCTRL1_S0": { + "src_wire": "CLK_BUFG_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED17->>CLK_BUFG_BUFGCTRL8_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED17", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_3->>CLK_BUFG_R_BUFGCTRL14_CE1": { + "src_wire": "CLK_BUFG_IMUX18_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0->>CLK_BUFG_BUFGCTRL11_O": { + "src_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL11_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I0": { + "src_wire": "CLK_BUFG_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_3->>CLK_BUFG_R_BUFGCTRL15_S1": { + "src_wire": "CLK_BUFG_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_CK_GCLK11": { + "src_wire": "CLK_BUFG_BUFGCTRL11_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_0->>CLK_BUFG_R_BUFGCTRL2_CE1": { + "src_wire": "CLK_BUFG_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_CK_GCLK15": { + "src_wire": "CLK_BUFG_BUFGCTRL15_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED7->>CLK_BUFG_BUFGCTRL3_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED7", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_R_FBG_OUT9": { + "src_wire": "CLK_BUFG_BUFGCTRL9_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX10_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_0->>CLK_BUFG_R_BUFGCTRL1_S1": { + "src_wire": "CLK_BUFG_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0->>CLK_BUFG_BUFGCTRL7_O": { + "src_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL7_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I0": { + "src_wire": "CLK_BUFG_IMUX24_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I1": { + "src_wire": "CLK_BUFG_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED24->>CLK_BUFG_BUFGCTRL12_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED24", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I1": { + "src_wire": "CLK_BUFG_IMUX31_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_R_FBG_OUT6": { + "src_wire": "CLK_BUFG_BUFGCTRL6_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_R_FBG_OUT2": { + "src_wire": "CLK_BUFG_BUFGCTRL2_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I1": { + "src_wire": "CLK_BUFG_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_CK_GCLK5": { + "src_wire": "CLK_BUFG_BUFGCTRL5_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0->>CLK_BUFG_BUFGCTRL10_O": { + "src_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL10_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_0->>CLK_BUFG_R_BUFGCTRL3_S0": { + "src_wire": "CLK_BUFG_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0->>CLK_BUFG_BUFGCTRL13_O": { + "src_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL13_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED1->>CLK_BUFG_BUFGCTRL0_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_0->>CLK_BUFG_R_BUFGCTRL1_CE0": { + "src_wire": "CLK_BUFG_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I1": { + "src_wire": "CLK_BUFG_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_1->>CLK_BUFG_R_BUFGCTRL6_S1": { + "src_wire": "CLK_BUFG_IMUX2_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I1": { + "src_wire": "CLK_BUFG_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I1": { + "src_wire": "CLK_BUFG_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I0": { + "src_wire": "CLK_BUFG_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_1->>CLK_BUFG_R_BUFGCTRL5_S0": { + "src_wire": "CLK_BUFG_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I0": { + "src_wire": "CLK_BUFG_IMUX24_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I0": { + "src_wire": "CLK_BUFG_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_2->>CLK_BUFG_R_BUFGCTRL11_CE1": { + "src_wire": "CLK_BUFG_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED6->>CLK_BUFG_BUFGCTRL3_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED6", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I1": { + "src_wire": "CLK_BUFG_IMUX24_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_R_FBG_OUT3": { + "src_wire": "CLK_BUFG_BUFGCTRL3_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0->>CLK_BUFG_BUFGCTRL1_O": { + "src_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL1_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_1->>CLK_BUFG_R_BUFGCTRL6_S0": { + "src_wire": "CLK_BUFG_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_R_FBG_OUT11": { + "src_wire": "CLK_BUFG_BUFGCTRL11_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED19->>CLK_BUFG_BUFGCTRL9_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED19", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_R_FBG_OUT10": { + "src_wire": "CLK_BUFG_BUFGCTRL10_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I1": { + "src_wire": "CLK_BUFG_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I0": { + "src_wire": "CLK_BUFG_IMUX31_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX14_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I0": { + "src_wire": "CLK_BUFG_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_1->>CLK_BUFG_R_BUFGCTRL5_S1": { + "src_wire": "CLK_BUFG_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX12_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED5->>CLK_BUFG_BUFGCTRL2_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED5", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_2->>CLK_BUFG_R_BUFGCTRL11_CE0": { + "src_wire": "CLK_BUFG_IMUX23_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_0->>CLK_BUFG_R_BUFGCTRL2_S1": { + "src_wire": "CLK_BUFG_IMUX2_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_3->>CLK_BUFG_R_BUFGCTRL13_CE1": { + "src_wire": "CLK_BUFG_IMUX17_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_2->>CLK_BUFG_R_BUFGCTRL8_S0": { + "src_wire": "CLK_BUFG_IMUX4_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED31->>CLK_BUFG_BUFGCTRL15_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED31", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I0": { + "src_wire": "CLK_BUFG_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_2->>CLK_BUFG_R_BUFGCTRL9_S1": { + "src_wire": "CLK_BUFG_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I1": { + "src_wire": "CLK_BUFG_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_3->>CLK_BUFG_R_BUFGCTRL13_S0": { + "src_wire": "CLK_BUFG_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I0": { + "src_wire": "CLK_BUFG_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_3->>CLK_BUFG_R_BUFGCTRL14_S0": { + "src_wire": "CLK_BUFG_IMUX6_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0->>CLK_BUFG_BUFGCTRL2_O": { + "src_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL2_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I1": { + "src_wire": "CLK_BUFG_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_3->>CLK_BUFG_R_BUFGCTRL15_S0": { + "src_wire": "CLK_BUFG_IMUX7_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_2->>CLK_BUFG_R_BUFGCTRL10_CE0": { + "src_wire": "CLK_BUFG_IMUX22_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0->>CLK_BUFG_BUFGCTRL6_O": { + "src_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL6_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_1->>CLK_BUFG_R_BUFGCTRL4_S1": { + "src_wire": "CLK_BUFG_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX12_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED10->>CLK_BUFG_BUFGCTRL5_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED10", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED23->>CLK_BUFG_BUFGCTRL11_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED23", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_1->>CLK_BUFG_R_BUFGCTRL4_S0": { + "src_wire": "CLK_BUFG_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_2->>CLK_BUFG_R_BUFGCTRL9_CE0": { + "src_wire": "CLK_BUFG_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I0": { + "src_wire": "CLK_BUFG_IMUX27_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_0->>CLK_BUFG_R_BUFGCTRL0_CE0": { + "src_wire": "CLK_BUFG_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I1": { + "src_wire": "CLK_BUFG_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I0": { + "src_wire": "CLK_BUFG_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I0": { + "src_wire": "CLK_BUFG_IMUX26_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX13_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED8->>CLK_BUFG_BUFGCTRL4_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED8", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED25->>CLK_BUFG_BUFGCTRL12_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED25", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_1->>CLK_BUFG_R_BUFGCTRL6_CE0": { + "src_wire": "CLK_BUFG_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I1": { + "src_wire": "CLK_BUFG_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I0": { + "src_wire": "CLK_BUFG_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I1": { + "src_wire": "CLK_BUFG_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0->>CLK_BUFG_BUFGCTRL9_O": { + "src_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL9_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_0->>CLK_BUFG_R_BUFGCTRL0_S0": { + "src_wire": "CLK_BUFG_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX11_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED3->>CLK_BUFG_BUFGCTRL1_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I0": { + "src_wire": "CLK_BUFG_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_CK_GCLK1": { + "src_wire": "CLK_BUFG_BUFGCTRL1_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED13->>CLK_BUFG_BUFGCTRL6_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED13", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX15_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_3->>CLK_BUFG_R_BUFGCTRL15_CE1": { + "src_wire": "CLK_BUFG_IMUX19_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED4->>CLK_BUFG_BUFGCTRL2_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED4", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED28->>CLK_BUFG_BUFGCTRL14_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED28", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I1": { + "src_wire": "CLK_BUFG_IMUX30_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED22->>CLK_BUFG_BUFGCTRL11_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED22", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I1": { + "src_wire": "CLK_BUFG_IMUX24_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_CK_GCLK6": { + "src_wire": "CLK_BUFG_BUFGCTRL6_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX13_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_CK_GCLK12": { + "src_wire": "CLK_BUFG_BUFGCTRL12_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0->>CLK_BUFG_BUFGCTRL14_O": { + "src_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL14_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_1->>CLK_BUFG_R_BUFGCTRL5_CE1": { + "src_wire": "CLK_BUFG_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX9_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED12->>CLK_BUFG_BUFGCTRL6_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED12", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_1->>CLK_BUFG_R_BUFGCTRL7_S0": { + "src_wire": "CLK_BUFG_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I0": { + "src_wire": "CLK_BUFG_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_3->>CLK_BUFG_R_BUFGCTRL13_S1": { + "src_wire": "CLK_BUFG_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_R_FBG_OUT13": { + "src_wire": "CLK_BUFG_BUFGCTRL13_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I0": { + "src_wire": "CLK_BUFG_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I0": { + "src_wire": "CLK_BUFG_IMUX27_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_CK_GCLK2": { + "src_wire": "CLK_BUFG_BUFGCTRL2_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I1": { + "src_wire": "CLK_BUFG_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_CK_GCLK0": { + "src_wire": "CLK_BUFG_BUFGCTRL0_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0->>CLK_BUFG_BUFGCTRL12_O": { + "src_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL12_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I1": { + "src_wire": "CLK_BUFG_IMUX25_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I1": { + "src_wire": "CLK_BUFG_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX9_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I1": { + "src_wire": "CLK_BUFG_IMUX27_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I0": { + "src_wire": "CLK_BUFG_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0->>CLK_BUFG_BUFGCTRL8_O": { + "src_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL8_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I0": { + "src_wire": "CLK_BUFG_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_2->>CLK_BUFG_R_BUFGCTRL8_CE0": { + "src_wire": "CLK_BUFG_IMUX20_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_1->>CLK_BUFG_R_BUFGCTRL4_CE1": { + "src_wire": "CLK_BUFG_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_0->>CLK_BUFG_R_BUFGCTRL3_CE0": { + "src_wire": "CLK_BUFG_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I1": { + "src_wire": "CLK_BUFG_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_R_FBG_OUT4": { + "src_wire": "CLK_BUFG_BUFGCTRL4_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_CK_GCLK10": { + "src_wire": "CLK_BUFG_BUFGCTRL10_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_CK_GCLK3": { + "src_wire": "CLK_BUFG_BUFGCTRL3_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_3->>CLK_BUFG_R_BUFGCTRL14_CE0": { + "src_wire": "CLK_BUFG_IMUX22_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_3->>CLK_BUFG_R_BUFGCTRL12_CE0": { + "src_wire": "CLK_BUFG_IMUX20_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I1": { + "src_wire": "CLK_BUFG_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_1->>CLK_BUFG_R_BUFGCTRL7_CE1": { + "src_wire": "CLK_BUFG_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_0->>CLK_BUFG_R_BUFGCTRL1_CE1": { + "src_wire": "CLK_BUFG_IMUX17_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_3->>CLK_BUFG_R_BUFGCTRL13_CE0": { + "src_wire": "CLK_BUFG_IMUX21_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0->>CLK_BUFG_BUFGCTRL5_O": { + "src_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL5_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I1": { + "src_wire": "CLK_BUFG_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I0": { + "src_wire": "CLK_BUFG_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX11_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED20->>CLK_BUFG_BUFGCTRL10_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED20", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED15->>CLK_BUFG_BUFGCTRL7_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED15", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED29->>CLK_BUFG_BUFGCTRL14_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED29", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_R_FBG_OUT15": { + "src_wire": "CLK_BUFG_BUFGCTRL15_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX11_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0->>CLK_BUFG_BUFGCTRL3_O": { + "src_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL3_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_R_FBG_OUT8": { + "src_wire": "CLK_BUFG_BUFGCTRL8_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX11_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I0": { + "src_wire": "CLK_BUFG_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX14_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0->>CLK_BUFG_BUFGCTRL0_O": { + "src_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL0_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_2->>CLK_BUFG_R_BUFGCTRL11_S0": { + "src_wire": "CLK_BUFG_IMUX7_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_R_FBG_OUT1": { + "src_wire": "CLK_BUFG_BUFGCTRL1_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_1->>CLK_BUFG_R_BUFGCTRL6_CE1": { + "src_wire": "CLK_BUFG_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_0->>CLK_BUFG_R_BUFGCTRL0_S1": { + "src_wire": "CLK_BUFG_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I0": { + "src_wire": "CLK_BUFG_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED30->>CLK_BUFG_BUFGCTRL15_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED30", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I0": { + "src_wire": "CLK_BUFG_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0->>CLK_BUFG_BUFGCTRL15_O": { + "src_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL15_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I1": { + "src_wire": "CLK_BUFG_IMUX27_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I0": { + "src_wire": "CLK_BUFG_IMUX25_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_0->>CLK_BUFG_R_BUFGCTRL0_CE1": { + "src_wire": "CLK_BUFG_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX8_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I0": { + "src_wire": "CLK_BUFG_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED18->>CLK_BUFG_BUFGCTRL9_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED18", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_1->>CLK_BUFG_R_BUFGCTRL7_S1": { + "src_wire": "CLK_BUFG_IMUX3_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_0->>CLK_BUFG_R_BUFGCTRL3_S1": { + "src_wire": "CLK_BUFG_IMUX3_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I0": { + "src_wire": "CLK_BUFG_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_0->>CLK_BUFG_R_BUFGCTRL3_CE1": { + "src_wire": "CLK_BUFG_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_R_FBG_OUT5": { + "src_wire": "CLK_BUFG_BUFGCTRL5_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_1->>CLK_BUFG_R_BUFGCTRL4_CE0": { + "src_wire": "CLK_BUFG_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I0": { + "src_wire": "CLK_BUFG_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_CK_GCLK4": { + "src_wire": "CLK_BUFG_BUFGCTRL4_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX10_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_R_FBG_OUT12": { + "src_wire": "CLK_BUFG_BUFGCTRL12_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_1->>CLK_BUFG_R_BUFGCTRL5_CE0": { + "src_wire": "CLK_BUFG_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX15_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I1": { + "src_wire": "CLK_BUFG_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I1": { + "src_wire": "CLK_BUFG_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED16->>CLK_BUFG_BUFGCTRL8_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED16", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I1": { + "src_wire": "CLK_BUFG_IMUX26_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_0->>CLK_BUFG_R_BUFGCTRL2_CE0": { + "src_wire": "CLK_BUFG_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I0": { + "src_wire": "CLK_BUFG_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I1": { + "src_wire": "CLK_BUFG_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_CK_GCLK8": { + "src_wire": "CLK_BUFG_BUFGCTRL8_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I1": { + "src_wire": "CLK_BUFG_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_3->>CLK_BUFG_R_BUFGCTRL12_CE1": { + "src_wire": "CLK_BUFG_IMUX16_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED0->>CLK_BUFG_BUFGCTRL0_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_CK_GCLK13": { + "src_wire": "CLK_BUFG_BUFGCTRL13_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_2->>CLK_BUFG_R_BUFGCTRL8_CE1": { + "src_wire": "CLK_BUFG_IMUX16_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_2->>CLK_BUFG_R_BUFGCTRL9_CE1": { + "src_wire": "CLK_BUFG_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_R_FBG_OUT14": { + "src_wire": "CLK_BUFG_BUFGCTRL14_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I1": { + "src_wire": "CLK_BUFG_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_2->>CLK_BUFG_R_BUFGCTRL9_S0": { + "src_wire": "CLK_BUFG_IMUX5_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_1->>CLK_BUFG_R_BUFGCTRL7_CE0": { + "src_wire": "CLK_BUFG_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_3->>CLK_BUFG_R_BUFGCTRL12_S1": { + "src_wire": "CLK_BUFG_IMUX0_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I1": { + "src_wire": "CLK_BUFG_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED11->>CLK_BUFG_BUFGCTRL5_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED11", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_3->>CLK_BUFG_R_BUFGCTRL14_S1": { + "src_wire": "CLK_BUFG_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_CK_GCLK7": { + "src_wire": "CLK_BUFG_BUFGCTRL7_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_2->>CLK_BUFG_R_BUFGCTRL10_S1": { + "src_wire": "CLK_BUFG_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_2->>CLK_BUFG_R_BUFGCTRL8_S1": { + "src_wire": "CLK_BUFG_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I1": { + "src_wire": "CLK_BUFG_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I0": { + "src_wire": "CLK_BUFG_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED9->>CLK_BUFG_BUFGCTRL4_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED9", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I0": { + "src_wire": "CLK_BUFG_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_3->>CLK_BUFG_R_BUFGCTRL15_CE0": { + "src_wire": "CLK_BUFG_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_R_FBG_OUT0": { + "src_wire": "CLK_BUFG_BUFGCTRL0_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_0->>CLK_BUFG_R_BUFGCTRL2_S0": { + "src_wire": "CLK_BUFG_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED26->>CLK_BUFG_BUFGCTRL13_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED26", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_CK_GCLK14": { + "src_wire": "CLK_BUFG_BUFGCTRL14_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_3->>CLK_BUFG_R_BUFGCTRL12_S0": { + "src_wire": "CLK_BUFG_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I0": { + "src_wire": "CLK_BUFG_IMUX30_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_R_FBG_OUT7": { + "src_wire": "CLK_BUFG_BUFGCTRL7_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED21->>CLK_BUFG_BUFGCTRL10_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED21", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_2->>CLK_BUFG_R_BUFGCTRL11_S1": { + "src_wire": "CLK_BUFG_IMUX3_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED14->>CLK_BUFG_BUFGCTRL7_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED14", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED2->>CLK_BUFG_BUFGCTRL1_I0": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I0": { + "src_wire": "CLK_BUFG_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_CK_GCLK9": { + "src_wire": "CLK_BUFG_BUFGCTRL9_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED27->>CLK_BUFG_BUFGCTRL13_I1": { + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED27", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0->>CLK_BUFG_BUFGCTRL4_O": { + "src_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL4_O", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CLK_BUFG_REBUF.json b/kintex7/tile_type_CLK_BUFG_REBUF.json new file mode 100644 index 0000000..43844cb --- /dev/null +++ b/kintex7/tile_type_CLK_BUFG_REBUF.json @@ -0,0 +1,1188 @@ +{ + "tile_type": "CLK_BUFG_REBUF", + "sites": [], + "wires": [ + "GCLK20_21_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_NW4END2_0", + "GCLK14_15_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_WW2A2_0", + "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", + "CLK_BUFG_REBUF_NW4END1_1", + "CLK_BUFG_REBUF_NE2A0_1", + "CLK_BUFG_REBUF_SW4A0_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", + "CLK_BUFG_REBUF_CK_GCLK22_TOP", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", + "CLK_BUFG_REBUF_WW2END3_1", + "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", + "GCLK1_0_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_EE4C0_1", + "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", + "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", + "CLK_BUFG_REBUF_CK_GCLK25_BOT", + "CLK_BUFG_REBUF_NW2A1_1", + "CLK_BUFG_REBUF_WW4END2_1", + "GCLK2_3_DN_TEST_RING_OUT", + "GCLK31_30_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_WL1END3_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", + "CLK_BUFG_REBUF_CK_GCLK9_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", + "CLK_BUFG_REBUF_ER1BEG0_1", + "GCLK28_29_DN_TEST_RING_OUT", + "GCLK1_0_UP_TEST_RING_IN", + "GCLK12_13_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", + "CLK_BUFG_REBUF_LH5_1", + "CLK_BUFG_REBUF_WW2END2_1", + "CLK_BUFG_REBUF_NW2A2_0", + "CLK_BUFG_REBUF_EE4C2_0", + "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", + "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", + "GCLK13_12_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_WR1END0_1", + "CLK_BUFG_REBUF_CK_GCLK29_TOP", + "CLK_BUFG_REBUF_EE4BEG3_0", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", + "CLK_BUFG_REBUF_CK_GCLK22_BOT", + "CLK_BUFG_REBUF_MONITOR_P_0", + "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", + "CLK_BUFG_REBUF_SW4END2_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC26", + "CLK_BUFG_REBUF_MONITOR_N_1", + "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", + "CLK_BUFG_REBUF_SW4END3_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC6", + "CLK_BUFG_REBUF_CK_BUFG_CASC28", + "CLK_BUFG_REBUF_EE4A0_1", + "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", + "CLK_BUFG_REBUF_NW4A0_0", + "GCLK7_6_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_BUFG_CASC12", + "CLK_BUFG_REBUF_EE4C3_0", + "CLK_BUFG_REBUF_NW4A1_0", + "CLK_BUFG_REBUF_EE4BEG0_0", + "CLK_BUFG_REBUF_NW4END0_0", + "CLK_BUFG_REBUF_NW4END3_1", + "CLK_BUFG_REBUF_LH1_1", + "CLK_BUFG_REBUF_WW2END1_0", + "CLK_BUFG_REBUF_NW4END0_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC30", + "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", + "CLK_BUFG_REBUF_SW2A2_0", + "CLK_BUFG_REBUF_WR1END1_1", + "CLK_BUFG_REBUF_NE4BEG0_0", + "GCLK25_24_UP_TEST_RING_IN", + "GCLK19_18_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_GCLK27_TOP", + "CLK_BUFG_REBUF_WW4END3_1", + "CLK_BUFG_REBUF_NE4BEG2_0", + "CLK_BUFG_REBUF_CK_BUFG_CASC19", + "CLK_BUFG_REBUF_CK_BUFG_CASC31", + "CLK_BUFG_REBUF_CK_GCLK1_BOT", + "CLK_BUFG_REBUF_WW4C2_1", + "GCLK26_27_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_WW4A3_0", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", + "CLK_BUFG_REBUF_WW4END0_0", + "CLK_BUFG_REBUF_NW4END3_0", + "CLK_BUFG_REBUF_MONITOR_N_0", + "GCLK17_16_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_SW4A2_0", + "CLK_BUFG_REBUF_WL1END2_1", + "CLK_BUFG_REBUF_LH12_1", + "CLK_BUFG_REBUF_WR1END0_0", + "CLK_BUFG_REBUF_LH9_1", + "CLK_BUFG_REBUF_WR1END1_0", + "CLK_BUFG_REBUF_CK_BUFG_CASC21", + "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", + "CLK_BUFG_REBUF_ER1BEG2_0", + "CLK_BUFG_REBUF_EL1BEG1_0", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", + "GCLK18_19_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_GCLK12_BOT", + "GCLK9_8_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_EE4A0_0", + "CLK_BUFG_REBUF_ER1BEG3_1", + "CLK_BUFG_REBUF_WR1END3_1", + "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", + "CLK_BUFG_REBUF_WW4C0_0", + "CLK_BUFG_REBUF_WW4B1_0", + "CLK_BUFG_REBUF_CK_GCLK24_TOP", + "CLK_BUFG_REBUF_EE4BEG3_1", + "CLK_BUFG_REBUF_NW4A3_0", + "GCLK3_2_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", + "CLK_BUFG_REBUF_WW4END1_0", + "CLK_BUFG_REBUF_EE4B0_1", + "GCLK0_1_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_SE4BEG2_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC29", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", + "CLK_BUFG_REBUF_CK_GCLK15_TOP", + "CLK_BUFG_REBUF_SE4C1_0", + "GCLK17_16_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", + "CLK_BUFG_REBUF_CK_BUFG_CASC18", + "CLK_BUFG_REBUF_EE4B2_1", + "GCLK23_22_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_GCLK21_TOP", + "CLK_BUFG_REBUF_EE2A3_1", + "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", + "CLK_BUFG_REBUF_CK_GCLK12_BOT", + "CLK_BUFG_REBUF_NE4BEG3_0", + "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", + "CLK_BUFG_REBUF_LH6_1", + "CLK_BUFG_REBUF_WW4A2_1", + "CLK_BUFG_REBUF_CK_GCLK8_BOT", + "CLK_BUFG_REBUF_EE2BEG3_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC8", + "CLK_BUFG_REBUF_EE4B3_0", + "CLK_BUFG_REBUF_SE2A2_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC14", + "CLK_BUFG_REBUF_EE4B2_0", + "CLK_BUFG_REBUF_SW4A3_0", + "CLK_BUFG_REBUF_EE2BEG0_0", + "CLK_BUFG_REBUF_WW4A2_0", + "CLK_BUFG_REBUF_CK_GCLK11_BOT", + "GCLK10_11_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_WW4B0_0", + "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", + "CLK_BUFG_REBUF_SE4BEG0_0", + "CLK_BUFG_REBUF_SE4C3_0", + "CLK_BUFG_REBUF_NE4C1_0", + "CLK_BUFG_REBUF_NE4C2_1", + "CLK_BUFG_REBUF_WW4END3_0", + "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", + "CLK_BUFG_REBUF_CK_GCLK2_BOT", + "CLK_BUFG_REBUF_CK_GCLK10_TOP", + "GCLK24_25_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_CK_BUFG_CASC3", + "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", + "CLK_BUFG_REBUF_CK_BUFG_CASC4", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", + "CLK_BUFG_REBUF_SW2A1_1", + "CLK_BUFG_REBUF_WR1END3_0", + "CLK_BUFG_REBUF_WL1END1_1", + "CLK_BUFG_REBUF_CK_GCLK6_TOP", + "CLK_BUFG_REBUF_CK_GCLK16_BOT", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", + "CLK_BUFG_REBUF_CK_GCLK3_BOT", + "CLK_BUFG_REBUF_WW2A0_1", + "CLK_BUFG_REBUF_NE2A1_1", + "CLK_BUFG_REBUF_EE2BEG3_0", + "GCLK15_14_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_EE2A0_0", + "CLK_BUFG_REBUF_LH12_0", + "CLK_BUFG_REBUF_WW4A0_1", + "CLK_BUFG_REBUF_WW4B2_0", + "CLK_BUFG_REBUF_NW4A2_0", + "CLK_BUFG_REBUF_LH1_0", + "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", + "CLK_BUFG_REBUF_WW2END0_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", + "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", + "CLK_BUFG_REBUF_NE2A0_0", + "CLK_BUFG_REBUF_NE4BEG1_1", + "CLK_BUFG_REBUF_NE4C3_0", + "CLK_BUFG_REBUF_CK_GCLK19_BOT", + "CLK_BUFG_REBUF_LH4_0", + "CLK_BUFG_REBUF_LH8_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC5", + "CLK_BUFG_REBUF_EE4A3_0", + "CLK_BUFG_REBUF_CK_GCLK13_TOP", + "CLK_BUFG_REBUF_WW2A1_1", + "CLK_BUFG_REBUF_NW4END1_0", + "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", + "GCLK8_9_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_WW4END2_0", + "CLK_BUFG_REBUF_LH3_0", + "CLK_BUFG_REBUF_EE4C1_0", + "CLK_BUFG_REBUF_SE4BEG1_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC23", + "CLK_BUFG_REBUF_SW4A3_1", + "GCLK6_7_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_WW4A1_0", + "CLK_BUFG_REBUF_CK_GCLK31_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", + "GCLK6_7_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", + "CLK_BUFG_REBUF_NE4BEG0_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", + "GCLK5_4_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_EL1BEG2_1", + "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", + "CLK_BUFG_REBUF_CK_GCLK6_BOT", + "CLK_BUFG_REBUF_EE4B1_0", + "CLK_BUFG_REBUF_CK_GCLK2_TOP", + "CLK_BUFG_REBUF_CK_GCLK20_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", + "CLK_BUFG_REBUF_SW4END3_0", + "CLK_BUFG_REBUF_CK_GCLK10_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", + "CLK_BUFG_REBUF_NW2A0_1", + "CLK_BUFG_REBUF_NE4BEG2_1", + "CLK_BUFG_REBUF_ER1BEG1_1", + "CLK_BUFG_REBUF_EE4A1_0", + "CLK_BUFG_REBUF_SW2A1_0", + "GCLK5_4_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", + "CLK_BUFG_REBUF_SW4END0_0", + "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", + "CLK_BUFG_REBUF_WW4C1_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", + "CLK_BUFG_REBUF_NE2A3_0", + "CLK_BUFG_REBUF_NE4C0_0", + "CLK_BUFG_REBUF_NW2A3_0", + "CLK_BUFG_REBUF_WL1END0_1", + "GCLK30_31_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", + "CLK_BUFG_REBUF_SE4C2_1", + "CLK_BUFG_REBUF_CK_GCLK16_TOP", + "GCLK22_23_DN_TEST_RING_OUT", + "GCLK26_27_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", + "CLK_BUFG_REBUF_SE2A3_1", + "GCLK29_28_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_LH8_0", + "CLK_BUFG_REBUF_SW4A0_0", + "GCLK11_10_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", + "GCLK16_17_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", + "CLK_BUFG_REBUF_WL1END1_0", + "CLK_BUFG_REBUF_ER1BEG1_0", + "CLK_BUFG_REBUF_NW4A2_1", + "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", + "CLK_BUFG_REBUF_EL1BEG2_0", + "CLK_BUFG_REBUF_EE2A0_1", + "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", + "CLK_BUFG_REBUF_EL1BEG0_0", + "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", + "CLK_BUFG_REBUF_NE2A2_0", + "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", + "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", + "CLK_BUFG_REBUF_EE4A3_1", + "CLK_BUFG_REBUF_EE2BEG1_1", + "CLK_BUFG_REBUF_NW4A0_1", + "CLK_BUFG_REBUF_WW4B3_0", + "CLK_BUFG_REBUF_EE4B0_0", + "CLK_BUFG_REBUF_NW4A1_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC25", + "GCLK13_12_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_SW4END1_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", + "CLK_BUFG_REBUF_CK_GCLK28_TOP", + "CLK_BUFG_REBUF_EL1BEG3_1", + "GCLK10_11_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", + "CLK_BUFG_REBUF_SE2A1_0", + "CLK_BUFG_REBUF_CK_BUFG_CASC24", + "CLK_BUFG_REBUF_SW4END0_1", + "CLK_BUFG_REBUF_EE2A2_1", + "CLK_BUFG_REBUF_EE2A1_0", + "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", + "CLK_BUFG_REBUF_WL1END3_0", + "CLK_BUFG_REBUF_ER1BEG3_0", + "GCLK4_5_DN_TEST_RING_OUT", + "GCLK30_31_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", + "CLK_BUFG_REBUF_CK_GCLK17_TOP", + "CLK_BUFG_REBUF_SE2A3_0", + "CLK_BUFG_REBUF_WW4B2_1", + "CLK_BUFG_REBUF_WW2END2_0", + "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", + "CLK_BUFG_REBUF_CK_GCLK28_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", + "CLK_BUFG_REBUF_WL1END2_0", + "CLK_BUFG_REBUF_WW4B3_1", + "CLK_BUFG_REBUF_EE2BEG2_0", + "CLK_BUFG_REBUF_WW4A0_0", + "GCLK19_18_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", + "CLK_BUFG_REBUF_CK_GCLK9_TOP", + "CLK_BUFG_REBUF_NE4BEG3_1", + "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", + "CLK_BUFG_REBUF_NW2A2_1", + "CLK_BUFG_REBUF_WW2A3_0", + "GCLK16_17_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_SE2A0_1", + "GCLK4_5_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_CK_BUFG_CASC22", + "GCLK23_22_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_LH10_0", + "GCLK24_25_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_EE4C3_1", + "CLK_BUFG_REBUF_WW4C1_0", + "CLK_BUFG_REBUF_SE4C1_1", + "GCLK21_20_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_EE2A1_1", + "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", + "CLK_BUFG_REBUF_CK_GCLK25_TOP", + "CLK_BUFG_REBUF_CK_GCLK5_TOP", + "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", + "CLK_BUFG_REBUF_EE2BEG0_1", + "CLK_BUFG_REBUF_WR1END2_0", + "CLK_BUFG_REBUF_SW4END2_0", + "CLK_BUFG_REBUF_EE4BEG1_1", + "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", + "CLK_BUFG_REBUF_SE2A1_1", + "CLK_BUFG_REBUF_CK_GCLK7_BOT", + "CLK_BUFG_REBUF_CK_GCLK23_TOP", + "CLK_BUFG_REBUF_EE4A2_0", + "CLK_BUFG_REBUF_SE4BEG2_0", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", + "GCLK7_6_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_WW2END3_0", + "CLK_BUFG_REBUF_CK_GCLK4_TOP", + "CLK_BUFG_REBUF_CK_GCLK1_TOP", + "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", + "CLK_BUFG_REBUF_NW4A3_1", + "CLK_BUFG_REBUF_EL1BEG3_0", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", + "CLK_BUFG_REBUF_CK_BUFG_CASC15", + "GCLK11_10_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_EE4A2_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC20", + "CLK_BUFG_REBUF_NE2A3_1", + "CLK_BUFG_REBUF_NE2A2_1", + "CLK_BUFG_REBUF_WW2A3_1", + "CLK_BUFG_REBUF_WW4C2_0", + "GCLK28_29_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC1", + "CLK_BUFG_REBUF_LH11_1", + "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", + "CLK_BUFG_REBUF_LH7_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC16", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", + "CLK_BUFG_REBUF_WR1END2_1", + "CLK_BUFG_REBUF_LH9_0", + "CLK_BUFG_REBUF_CK_GCLK19_TOP", + "CLK_BUFG_REBUF_WW4B1_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC10", + "CLK_BUFG_REBUF_WW4C0_1", + "CLK_BUFG_REBUF_EE4C0_0", + "GCLK18_19_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_LH3_1", + "CLK_BUFG_REBUF_NE4C1_1", + "CLK_BUFG_REBUF_CK_GCLK14_BOT", + "CLK_BUFG_REBUF_ER1BEG2_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", + "CLK_BUFG_REBUF_CK_GCLK3_TOP", + "CLK_BUFG_REBUF_WW4C3_1", + "CLK_BUFG_REBUF_MONITOR_P_1", + "CLK_BUFG_REBUF_NE4BEG1_0", + "CLK_BUFG_REBUF_CK_GCLK7_TOP", + "CLK_BUFG_REBUF_WW2END1_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", + "CLK_BUFG_REBUF_NE4C2_0", + "CLK_BUFG_REBUF_NW2A1_0", + "CLK_BUFG_REBUF_SW2A0_0", + "CLK_BUFG_REBUF_CK_GCLK0_BOT", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", + "CLK_BUFG_REBUF_EE2A3_0", + "CLK_BUFG_REBUF_WW4A3_1", + "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", + "CLK_BUFG_REBUF_WW4END1_1", + "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", + "CLK_BUFG_REBUF_LH6_0", + "GCLK31_30_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_EE4BEG1_0", + "CLK_BUFG_REBUF_CK_GCLK21_BOT", + "GCLK0_1_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_BUFG_CASC1", + "CLK_BUFG_REBUF_SE4BEG3_0", + "CLK_BUFG_REBUF_CK_GCLK24_BOT", + "CLK_BUFG_REBUF_NE4C0_1", + "GCLK2_3_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_EE4BEG2_1", + "CLK_BUFG_REBUF_SW2A2_1", + "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", + "CLK_BUFG_REBUF_CK_GCLK30_BOT", + "CLK_BUFG_REBUF_EE4C2_1", + "CLK_BUFG_REBUF_LH10_1", + "CLK_BUFG_REBUF_SE4BEG1_0", + "CLK_BUFG_REBUF_EE4B3_1", + "GCLK3_2_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_EL1BEG0_1", + "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", + "CLK_BUFG_REBUF_LH2_0", + "CLK_BUFG_REBUF_CK_GCLK4_BOT", + "CLK_BUFG_REBUF_SE4C0_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC0", + "CLK_BUFG_REBUF_CK_GCLK26_TOP", + "CLK_BUFG_REBUF_WW4C3_0", + "CLK_BUFG_REBUF_SE4BEG3_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", + "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", + "CLK_BUFG_REBUF_NE4C3_1", + "GCLK29_28_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC31", + "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", + "CLK_BUFG_REBUF_CK_GCLK8_TOP", + "CLK_BUFG_REBUF_SW2A3_1", + "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", + "GCLK20_21_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_GCLK17_BOT", + "CLK_BUFG_REBUF_EE2A2_0", + "CLK_BUFG_REBUF_WW2END0_0", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC9", + "CLK_BUFG_REBUF_CK_GCLK31_TOP", + "CLK_BUFG_REBUF_LH2_1", + "CLK_BUFG_REBUF_EE4B1_1", + "CLK_BUFG_REBUF_CK_GCLK0_TOP", + "CLK_BUFG_REBUF_EE4BEG0_1", + "CLK_BUFG_REBUF_SE4BEG0_1", + "CLK_BUFG_REBUF_CK_GCLK26_BOT", + "CLK_BUFG_REBUF_CK_BUFG_CASC11", + "CLK_BUFG_REBUF_SW2A3_0", + "CLK_BUFG_REBUF_CK_GCLK18_TOP", + "CLK_BUFG_REBUF_EE2BEG1_0", + "CLK_BUFG_REBUF_SW4A1_0", + "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", + "CLK_BUFG_REBUF_SE4C3_1", + "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", + "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", + "CLK_BUFG_REBUF_LH5_0", + "CLK_BUFG_REBUF_CK_BUFG_CASC9", + "CLK_BUFG_REBUF_NW2A3_1", + "CLK_BUFG_REBUF_EE4BEG2_0", + "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", + "CLK_BUFG_REBUF_SW4END1_0", + "CLK_BUFG_REBUF_CK_BUFG_CASC2", + "GCLK15_14_UP_TEST_RING_OUT", + "GCLK27_26_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_ER1BEG0_0", + "CLK_BUFG_REBUF_WW2A0_0", + "CLK_BUFG_REBUF_CK_BUFG_CASC13", + "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", + "CLK_BUFG_REBUF_CK_GCLK29_BOT", + "CLK_BUFG_REBUF_WW4A1_1", + "CLK_BUFG_REBUF_CK_GCLK30_TOP", + "GCLK25_24_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_GCLK18_BOT", + "CLK_BUFG_REBUF_CK_GCLK11_TOP", + "CLK_BUFG_REBUF_EE4A1_1", + "GCLK14_15_DN_TEST_RING_IN", + "GCLK9_8_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_GCLK20_TOP", + "CLK_BUFG_REBUF_SE4C2_0", + "GCLK21_20_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_BUFG_CASC17", + "CLK_BUFG_REBUF_CK_GCLK27_BOT", + "CLK_BUFG_REBUF_WW4END0_1", + "GCLK27_26_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_WL1END0_0", + "CLK_BUFG_REBUF_SW4A2_1", + "CLK_BUFG_REBUF_NE2A1_0", + "CLK_BUFG_REBUF_CK_GCLK23_BOT", + "CLK_BUFG_REBUF_SE2A0_0", + "CLK_BUFG_REBUF_CK_GCLK5_BOT", + "CLK_BUFG_REBUF_CK_BUFG_CASC27", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", + "CLK_BUFG_REBUF_SW2A0_1", + "CLK_BUFG_REBUF_NW4END2_1", + "GCLK12_13_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_SE2A2_0", + "GCLK22_23_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_EL1BEG1_1", + "CLK_BUFG_REBUF_EE4C1_1", + "CLK_BUFG_REBUF_WW2A1_0", + "CLK_BUFG_REBUF_LH4_1", + "CLK_BUFG_REBUF_CK_GCLK15_BOT", + "CLK_BUFG_REBUF_WW2A2_1", + "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", + "CLK_BUFG_REBUF_CK_GCLK13_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", + "CLK_BUFG_REBUF_CK_GCLK12_TOP", + "GCLK8_9_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_WW4B0_1", + "CLK_BUFG_REBUF_CK_GCLK14_TOP", + "CLK_BUFG_REBUF_LH7_0", + "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", + "CLK_BUFG_REBUF_CK_BUFG_CASC7", + "CLK_BUFG_REBUF_SE4C0_0", + "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", + "CLK_BUFG_REBUF_NW2A0_0", + "CLK_BUFG_REBUF_SW4A1_1", + "CLK_BUFG_REBUF_EE2BEG2_1", + "CLK_BUFG_REBUF_LH11_0" + ], + "pips": { + "CLK_BUFG_REBUF.GCLK15_14_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK14_TOP": { + "src_wire": "GCLK15_14_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK24_25_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK25_BOT": { + "src_wire": "GCLK24_25_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK18_19_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK19_BOT": { + "src_wire": "GCLK18_19_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_TOP->>GCLK23_22_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK23_22_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK21_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK13_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_BOT->>GCLK24_25_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK24_25_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK2_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK12_13_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK13_BOT": { + "src_wire": "GCLK12_13_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK4_5_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK5_BOT": { + "src_wire": "GCLK4_5_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_TOP->>GCLK5_4_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK5_4_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK20_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_BOT->>GCLK14_15_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK14_15_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK30_31_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK31_BOT": { + "src_wire": "GCLK30_31_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK6_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK16_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK1_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK19_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK23_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK28_29_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK29_BOT": { + "src_wire": "GCLK28_29_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK5_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT->>GCLK2_3_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK2_3_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK4_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_TOP->>GCLK21_20_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK21_20_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_TOP->>GCLK11_10_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK11_10_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_BOT->>GCLK12_13_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK12_13_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK11_10_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK10_TOP": { + "src_wire": "GCLK11_10_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK17_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK26_27_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK27_BOT": { + "src_wire": "GCLK26_27_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_BOT->>GCLK22_23_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK22_23_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK18_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK25_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT->>GCLK20_21_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK20_21_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_TOP->>GCLK9_8_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK9_8_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK3_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_TOP->>GCLK1_0_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK1_0_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK1_0_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK0_TOP": { + "src_wire": "GCLK1_0_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK31_30_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK30_TOP": { + "src_wire": "GCLK31_30_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_TOP->>GCLK7_6_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK7_6_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK29_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK6_7_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK7_BOT": { + "src_wire": "GCLK6_7_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK27_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK14_15_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK15_BOT": { + "src_wire": "GCLK14_15_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK28_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK23_22_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK22_TOP": { + "src_wire": "GCLK23_22_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK22_23_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK23_BOT": { + "src_wire": "GCLK22_23_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK30_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT->>GCLK4_5_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK4_5_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT->>GCLK30_31_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK30_31_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK10_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK22_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK14_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK7_6_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK6_TOP": { + "src_wire": "GCLK7_6_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT->>GCLK0_1_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK0_1_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT->>GCLK18_19_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK18_19_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK9_8_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK8_TOP": { + "src_wire": "GCLK9_8_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK12_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK8_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK29_28_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK28_TOP": { + "src_wire": "GCLK29_28_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK9_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK13_12_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK12_TOP": { + "src_wire": "GCLK13_12_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_TOP->>GCLK31_30_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK31_30_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT->>GCLK28_29_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK28_29_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_TOP->>GCLK19_18_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK19_18_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK0_1_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK1_BOT": { + "src_wire": "GCLK0_1_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_BOT->>GCLK16_17_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK16_17_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK5_4_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK4_TOP": { + "src_wire": "GCLK5_4_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_TOP->>GCLK27_26_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK27_26_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK25_24_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK24_TOP": { + "src_wire": "GCLK25_24_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK20_21_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK21_BOT": { + "src_wire": "GCLK20_21_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK19_18_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK18_TOP": { + "src_wire": "GCLK19_18_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT->>GCLK8_9_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK8_9_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK0_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK8_9_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK9_BOT": { + "src_wire": "GCLK8_9_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT->>GCLK10_11_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK10_11_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_TOP->>GCLK25_24_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK25_24_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK17_16_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK16_TOP": { + "src_wire": "GCLK17_16_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK10_11_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK11_BOT": { + "src_wire": "GCLK10_11_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT->>GCLK6_7_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK6_7_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK2_3_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK3_BOT": { + "src_wire": "GCLK2_3_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK31_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK7_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_TOP->>GCLK29_28_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK29_28_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_BOT->>GCLK26_27_DN_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", + "is_pseudo": "0", + "dst_wire": "GCLK26_27_DN_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_TOP->>GCLK15_14_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK15_14_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK24_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK26_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK27_26_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK26_TOP": { + "src_wire": "GCLK27_26_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK21_20_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK20_TOP": { + "src_wire": "GCLK21_20_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_TOP->>GCLK13_12_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK13_12_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_TOP->>GCLK3_2_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK3_2_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK16_17_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK17_BOT": { + "src_wire": "GCLK16_17_DN_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.GCLK3_2_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK2_TOP": { + "src_wire": "GCLK3_2_UP_TEST_RING_OUT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK11_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK15_TOP": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", + "is_directional": "0", + "can_invert": "0" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_TOP->>GCLK17_16_UP_TEST_RING_IN": { + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", + "is_pseudo": "0", + "dst_wire": "GCLK17_16_UP_TEST_RING_IN", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CLK_BUFG_TOP_R.json b/kintex7/tile_type_CLK_BUFG_TOP_R.json new file mode 100644 index 0000000..de13ebf --- /dev/null +++ b/kintex7/tile_type_CLK_BUFG_TOP_R.json @@ -0,0 +1,3569 @@ +{ + "tile_type": "CLK_BUFG_TOP_R", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL0_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL0_CE0", + "I1": "CLK_BUFG_BUFGCTRL0_I1", + "O": "CLK_BUFG_BUFGCTRL0_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL0_I0", + "S1": "CLK_BUFG_R_BUFGCTRL0_S1", + "S0": "CLK_BUFG_R_BUFGCTRL0_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL1_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL1_CE0", + "I1": "CLK_BUFG_BUFGCTRL1_I1", + "O": "CLK_BUFG_BUFGCTRL1_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL1_I0", + "S1": "CLK_BUFG_R_BUFGCTRL1_S1", + "S0": "CLK_BUFG_R_BUFGCTRL1_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 2, + "name": "X0Y2", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL2_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL2_CE0", + "I1": "CLK_BUFG_BUFGCTRL2_I1", + "O": "CLK_BUFG_BUFGCTRL2_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL2_I0", + "S1": "CLK_BUFG_R_BUFGCTRL2_S1", + "S0": "CLK_BUFG_R_BUFGCTRL2_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 3, + "name": "X0Y3", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL3_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL3_CE0", + "I1": "CLK_BUFG_BUFGCTRL3_I1", + "O": "CLK_BUFG_BUFGCTRL3_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL3_I0", + "S1": "CLK_BUFG_R_BUFGCTRL3_S1", + "S0": "CLK_BUFG_R_BUFGCTRL3_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 4, + "name": "X0Y4", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL4_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL4_CE0", + "I1": "CLK_BUFG_BUFGCTRL4_I1", + "O": "CLK_BUFG_BUFGCTRL4_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL4_I0", + "S1": "CLK_BUFG_R_BUFGCTRL4_S1", + "S0": "CLK_BUFG_R_BUFGCTRL4_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 5, + "name": "X0Y5", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL5_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL5_CE0", + "I1": "CLK_BUFG_BUFGCTRL5_I1", + "O": "CLK_BUFG_BUFGCTRL5_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL5_I0", + "S1": "CLK_BUFG_R_BUFGCTRL5_S1", + "S0": "CLK_BUFG_R_BUFGCTRL5_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 6, + "name": "X0Y6", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL6_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL6_CE0", + "I1": "CLK_BUFG_BUFGCTRL6_I1", + "O": "CLK_BUFG_BUFGCTRL6_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL6_I0", + "S1": "CLK_BUFG_R_BUFGCTRL6_S1", + "S0": "CLK_BUFG_R_BUFGCTRL6_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 7, + "name": "X0Y7", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL7_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL7_CE0", + "I1": "CLK_BUFG_BUFGCTRL7_I1", + "O": "CLK_BUFG_BUFGCTRL7_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL7_I0", + "S1": "CLK_BUFG_R_BUFGCTRL7_S1", + "S0": "CLK_BUFG_R_BUFGCTRL7_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 8, + "name": "X0Y8", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL8_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL8_CE0", + "I1": "CLK_BUFG_BUFGCTRL8_I1", + "O": "CLK_BUFG_BUFGCTRL8_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL8_I0", + "S1": "CLK_BUFG_R_BUFGCTRL8_S1", + "S0": "CLK_BUFG_R_BUFGCTRL8_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 9, + "name": "X0Y9", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL9_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL9_CE0", + "I1": "CLK_BUFG_BUFGCTRL9_I1", + "O": "CLK_BUFG_BUFGCTRL9_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL9_I0", + "S1": "CLK_BUFG_R_BUFGCTRL9_S1", + "S0": "CLK_BUFG_R_BUFGCTRL9_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 10, + "name": "X0Y10", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL10_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL10_CE0", + "I1": "CLK_BUFG_BUFGCTRL10_I1", + "O": "CLK_BUFG_BUFGCTRL10_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL10_I0", + "S1": "CLK_BUFG_R_BUFGCTRL10_S1", + "S0": "CLK_BUFG_R_BUFGCTRL10_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 11, + "name": "X0Y11", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL11_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL11_CE0", + "I1": "CLK_BUFG_BUFGCTRL11_I1", + "O": "CLK_BUFG_BUFGCTRL11_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL11_I0", + "S1": "CLK_BUFG_R_BUFGCTRL11_S1", + "S0": "CLK_BUFG_R_BUFGCTRL11_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 12, + "name": "X0Y12", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL12_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL12_CE0", + "I1": "CLK_BUFG_BUFGCTRL12_I1", + "O": "CLK_BUFG_BUFGCTRL12_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL12_I0", + "S1": "CLK_BUFG_R_BUFGCTRL12_S1", + "S0": "CLK_BUFG_R_BUFGCTRL12_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 13, + "name": "X0Y13", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL13_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL13_CE0", + "I1": "CLK_BUFG_BUFGCTRL13_I1", + "O": "CLK_BUFG_BUFGCTRL13_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL13_I0", + "S1": "CLK_BUFG_R_BUFGCTRL13_S1", + "S0": "CLK_BUFG_R_BUFGCTRL13_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 14, + "name": "X0Y14", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL14_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL14_CE0", + "I1": "CLK_BUFG_BUFGCTRL14_I1", + "O": "CLK_BUFG_BUFGCTRL14_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL14_I0", + "S1": "CLK_BUFG_R_BUFGCTRL14_S1", + "S0": "CLK_BUFG_R_BUFGCTRL14_S0" + }, + "x_coord": 0 + }, + { + "y_coord": 15, + "name": "X0Y15", + "prefix": "BUFGCTRL", + "type": "BUFGCTRL", + "site_pins": { + "CE1": "CLK_BUFG_R_BUFGCTRL15_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL15_CE0", + "I1": "CLK_BUFG_BUFGCTRL15_I1", + "O": "CLK_BUFG_BUFGCTRL15_O", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", + "IGNORE0": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", + "I0": "CLK_BUFG_BUFGCTRL15_I0", + "S1": "CLK_BUFG_R_BUFGCTRL15_S1", + "S0": "CLK_BUFG_R_BUFGCTRL15_S0" + }, + "x_coord": 0 + } + ], + "wires": [ + "CLK_BUFG_R_BUFGCTRL14_S1", + "CLK_HROW_NW4A3_3", + "CLK_BUFG_R_BUFGCTRL11_IGNORE0", + "CLK_HROW_SE4C3_2", + "CLK_HROW_FAN0_3", + "CLK_BUFG_IMUX0_3", + "CLK_BUFG_CK_GCLK2", + "CLK_BUFG_R_FBG_OUT4", + "CLK_BUFG_R_BUFGCTRL11_S1", + "CLK_HROW_WW4B2_1", + "CLK_HROW_BYP4_2", + "CLK_HROW_WW4B0_0", + "CLK_BUFG_IMUX19_0", + "CLK_HROW_MONITOR_N_2", + "CLK_HROW_WW4B1_3", + "CLK_BUFG_IMUX13_0", + "CLK_BUFG_IMUX19_3", + "CLK_BUFG_LOGIC_OUTS_B23_1", + "CLK_BUFG_R_BUFGCTRL7_IGNORE0", + "CLK_HROW_LH9_1", + "CLK_HROW_NW2A1_0", + "CLK_HROW_WW2A3_1", + "CLK_HROW_SW2A1_0", + "CLK_BUFG_TOP_R_CK_MUXED0", + "CLK_BUFG_R_CK_FB_TEST1_10", + "CLK_HROW_NW4END1_1", + "CLK_HROW_WR1END3_1", + "CLK_BUFG_IMUX29_1", + "CLK_HROW_BYP0_2", + "CLK_HROW_SE4BEG2_0", + "CLK_BUFG_LOGIC_OUTS_B18_0", + "CLK_BUFG_LOGIC_OUTS_B6_0", + "CLK_BUFG_LOGIC_OUTS_B11_2", + "CLK_HROW_WW2A1_0", + "CLK_BUFG_R_BUFGCTRL1_CE1", + "CLK_HROW_LH11_0", + "CLK_HROW_SE4BEG1_1", + "CLK_HROW_WW4C3_3", + "CLK_BUFG_CK_GCLK3", + "CLK_BUFG_LOGIC_OUTS_B17_2", + "CLK_BUFG_LOGIC_OUTS_B16_3", + "CLK_HROW_NW4A0_2", + "CLK_BUFG_IMUX26_2", + "CLK_HROW_NE4C2_2", + "CLK_BUFG_LOGIC_OUTS_B8_2", + "CLK_HROW_EE2A2_0", + "CLK_HROW_BLOCK_OUTS_B0_2", + "CLK_HROW_LH9_0", + "CLK_HROW_NE2A2_2", + "CLK_BUFG_R_FBG_OUT11", + "CLK_HROW_WL1END2_1", + "CLK_BUFG_R_BUFGCTRL14_CE0", + "CLK_HROW_NE4C2_0", + "CLK_HROW_ER1BEG2_1", + "CLK_HROW_LH5_3", + "CLK_HROW_NE2A1_0", + "CLK_HROW_SW4END1_3", + "CLK_HROW_NW4A1_0", + "CLK_HROW_BLOCK_OUTS_B3_1", + "CLK_HROW_SW2A3_3", + "CLK_BUFG_TOP_R_CK_MUXED10", + "CLK_HROW_ER1BEG1_2", + "CLK_BUFG_LOGIC_OUTS_B23_2", + "CLK_BUFG_IMUX23_0", + "CLK_BUFG_BUFGCTRL0_I1", + "CLK_HROW_LH7_3", + "CLK_BUFG_LOGIC_OUTS_B8_3", + "CLK_HROW_SW4END0_0", + "CLK_BUFG_IMUX7_0", + "CLK_HROW_LH5_0", + "CLK_BUFG_R_BUFGCTRL10_S1", + "CLK_BUFG_BUFGCTRL7_I1", + "CLK_BUFG_BUFGCTRL1_I0", + "CLK_BUFG_IMUX43_0", + "CLK_BUFG_LOGIC_OUTS_B2_3", + "CLK_BUFG_BUFGCTRL3_I0", + "CLK_HROW_SE4C2_1", + "CLK_HROW_NW2A1_1", + "CLK_HROW_EE4BEG3_1", + "CLK_BUFG_R_BUFGCTRL9_IGNORE0", + "CLK_BUFG_LOGIC_OUTS_B19_0", + "CLK_BUFG_R_BUFGCTRL12_S1", + "CLK_HROW_NE4C1_3", + "CLK_BUFG_IMUX5_2", + "CLK_BUFG_IMUX17_1", + "CLK_HROW_SW2A1_2", + "CLK_HROW_EE2BEG2_3", + "CLK_BUFG_R_FBG_OUT6", + "CLK_HROW_EE2BEG3_0", + "CLK_HROW_WW2A3_2", + "CLK_HROW_NE4BEG1_1", + "CLK_BUFG_R_BUFGCTRL13_CE1", + "CLK_BUFG_BUFGCTRL8_O", + "CLK_HROW_LH10_3", + "CLK_HROW_EE4A3_0", + "CLK_HROW_BLOCK_OUTS_B3_0", + "CLK_BUFG_IMUX27_1", + "CLK_HROW_MONITOR_P_0", + "CLK_BUFG_IMUX14_2", + "CLK_HROW_NW4END1_2", + "CLK_BUFG_IMUX29_0", + "CLK_HROW_WW2END0_0", + "CLK_HROW_EE2A0_0", + "CLK_HROW_SE4C2_2", + "CLK_BUFG_R_BUFGCTRL3_IGNORE0", + "CLK_BUFG_R_BUFGCTRL3_CE1", + "CLK_BUFG_IMUX18_3", + "CLK_HROW_ER1BEG2_2", + "CLK_HROW_NW4A1_3", + "CLK_HROW_FAN4_2", + "CLK_HROW_WR1END3_2", + "CLK_BUFG_IMUX38_1", + "CLK_BUFG_CK_GCLK28", + "CLK_BUFG_R_BUFGCTRL14_CE1", + "CLK_HROW_SE4C1_1", + "CLK_HROW_EE2A3_2", + "CLK_BUFG_CK_GCLK1", + "CLK_HROW_FAN2_1", + "CLK_BUFG_IMUX15_1", + "CLK_HROW_ER1BEG2_3", + "CLK_HROW_EL1BEG3_2", + "CLK_BUFG_TOP_R_CK_MUXED19", + "CLK_HROW_NE4BEG1_0", + "CLK_HROW_NW2A3_0", + "CLK_HROW_CLK1_1", + "CLK_BUFG_R_CK_FB_TEST0_11", + "CLK_BUFG_R_BUFGCTRL10_IGNORE0", + "CLK_HROW_SE4C3_3", + "CLK_BUFG_IMUX6_1", + "CLK_HROW_SE4C0_0", + "CLK_BUFG_IMUX11_1", + "CLK_BUFG_IMUX4_2", + "CLK_HROW_SE4BEG2_1", + "CLK_BUFG_LOGIC_OUTS_B0_1", + "CLK_HROW_SE2A3_2", + "CLK_HROW_EE2A3_3", + "CLK_HROW_EE2BEG1_3", + "CLK_HROW_EL1BEG3_3", + "CLK_BUFG_TOP_R_CK_MUXED20", + "CLK_HROW_SE2A2_0", + "CLK_HROW_WW4END3_0", + "CLK_BUFG_LOGIC_OUTS_B7_0", + "CLK_HROW_NE4BEG1_3", + "CLK_BUFG_IMUX45_3", + "CLK_HROW_LH9_2", + "CLK_HROW_BYP6_2", + "CLK_BUFG_R_FBG_OUT15", + "CLK_HROW_SW2A1_3", + "CLK_BUFG_LOGIC_OUTS_B3_0", + "CLK_BUFG_LOGIC_OUTS_B3_1", + "CLK_HROW_BYP1_3", + "CLK_BUFG_IMUX44_3", + "CLK_BUFG_IMUX20_1", + "CLK_BUFG_BUFGCTRL10_O", + "CLK_HROW_SW4END3_0", + "CLK_BUFG_IMUX3_1", + "CLK_HROW_NE2A0_3", + "CLK_BUFG_R_CK_FB_TEST1_6", + "CLK_HROW_WW4C2_0", + "CLK_BUFG_IMUX40_0", + "CLK_BUFG_IMUX41_3", + "CLK_BUFG_LOGIC_OUTS_B5_0", + "CLK_HROW_NE4C0_2", + "CLK_HROW_SW4END0_1", + "CLK_HROW_LH1_3", + "CLK_BUFG_IMUX42_3", + "CLK_BUFG_LOGIC_OUTS_B13_0", + "CLK_BUFG_LOGIC_OUTS_B15_2", + "CLK_HROW_NW4END0_2", + "CLK_BUFG_R_BUFGCTRL9_S0", + "CLK_BUFG_IMUX34_3", + "CLK_BUFG_TOP_R_CK_MUXED18", + "CLK_BUFG_R_BUFGCTRL14_IGNORE0", + "CLK_BUFG_LOGIC_OUTS_B19_1", + "CLK_HROW_NE2A2_3", + "CLK_HROW_EL1BEG0_2", + "CLK_HROW_NW4END2_3", + "CLK_BUFG_IMUX43_3", + "CLK_BUFG_R_CK_FB_TEST1_8", + "CLK_BUFG_TOP_R_CK_MUXED29", + "CLK_BUFG_IMUX36_3", + "CLK_BUFG_LOGIC_OUTS_B11_1", + "CLK_HROW_EE4BEG2_0", + "CLK_HROW_FAN7_1", + "CLK_BUFG_LOGIC_OUTS_B7_1", + "CLK_HROW_EE2A3_1", + "CLK_BUFG_CK_GCLK25", + "CLK_HROW_WW4END0_0", + "CLK_BUFG_R_BUFGCTRL1_IGNORE0", + "CLK_HROW_SW4A2_2", + "CLK_HROW_SW2A1_1", + "CLK_BUFG_IMUX36_2", + "CLK_HROW_EE4A2_2", + "CLK_HROW_SE4C2_0", + "CLK_BUFG_IMUX37_2", + "CLK_BUFG_R_BUFGCTRL9_CE1", + "CLK_HROW_BYP1_1", + "CLK_HROW_WW4C1_2", + "CLK_BUFG_CK_GCLK17", + "CLK_BUFG_LOGIC_OUTS_B1_0", + "CLK_BUFG_BUFGCTRL14_O", + "CLK_BUFG_R_BUFGCTRL0_S1", + "CLK_HROW_BYP0_3", + "CLK_HROW_EL1BEG3_1", + "CLK_BUFG_IMUX19_2", + "CLK_BUFG_IMUX24_2", + "CLK_HROW_WW4A2_2", + "CLK_BUFG_IMUX34_0", + "CLK_HROW_SW4END1_2", + "CLK_BUFG_LOGIC_OUTS_B19_3", + "CLK_BUFG_CK_GCLK26", + "CLK_BUFG_R_BUFGCTRL11_CE1", + "CLK_BUFG_IMUX39_0", + "CLK_BUFG_LOGIC_OUTS_B5_2", + "CLK_HROW_EE2BEG3_2", + "CLK_BUFG_R_CK_FB_TEST0_7", + "CLK_BUFG_BUFGCTRL3_O", + "CLK_HROW_SE4C0_3", + "CLK_HROW_WW2A0_2", + "CLK_BUFG_LOGIC_OUTS_B1_3", + "CLK_BUFG_R_FBG_OUT9", + "CLK_BUFG_R_BUFGCTRL5_S0", + "CLK_HROW_SW4END1_1", + "CLK_HROW_SW4A0_0", + "CLK_BUFG_IMUX12_0", + "CLK_BUFG_R_BUFGCTRL0_CE0", + "CLK_HROW_WW4C1_1", + "CLK_HROW_FAN6_2", + "CLK_BUFG_IMUX21_0", + "CLK_HROW_BYP6_3", + "CLK_BUFG_IMUX2_3", + "CLK_HROW_SW4END3_2", + "CLK_HROW_EE2BEG1_2", + "CLK_HROW_SE2A1_2", + "CLK_HROW_LH9_3", + "CLK_HROW_SW4END2_2", + "CLK_HROW_EE4BEG0_3", + "CLK_BUFG_R_CK_FB_TEST1_0", + "CLK_BUFG_R_BUFGCTRL5_S1", + "CLK_BUFG_R_BUFGCTRL8_IGNORE0", + "CLK_BUFG_BUFGCTRL13_I0", + "CLK_HROW_NW4A3_0", + "CLK_HROW_WW2END1_1", + "CLK_HROW_EE4BEG2_3", + "CLK_HROW_WW4C0_1", + "CLK_HROW_EE4B2_1", + "CLK_HROW_EE4B2_2", + "CLK_BUFG_CK_GCLK0", + "CLK_BUFG_LOGIC_OUTS_B23_3", + "CLK_BUFG_CK_GCLK8", + "CLK_HROW_NE4BEG2_0", + "CLK_HROW_WW2END2_1", + "CLK_BUFG_IMUX5_1", + "CLK_HROW_FAN6_3", + "CLK_HROW_WR1END1_3", + "CLK_BUFG_BUFGCTRL3_I1", + "CLK_BUFG_IMUX24_3", + "CLK_BUFG_R_BUFGCTRL15_IGNORE0", + "CLK_HROW_WW4A1_1", + "CLK_HROW_WW4B1_1", + "CLK_HROW_FAN6_1", + "CLK_BUFG_R_CK_FB_TEST0_5", + "CLK_HROW_NW4END1_0", + "CLK_BUFG_IMUX38_3", + "CLK_HROW_LH2_3", + "CLK_BUFG_IMUX37_3", + "CLK_HROW_EL1BEG1_1", + "CLK_BUFG_IMUX9_2", + "CLK_BUFG_BUFGCTRL9_O", + "CLK_HROW_WW4B3_0", + "CLK_BUFG_CK_GCLK22", + "CLK_BUFG_IMUX31_1", + "CLK_HROW_WW4END3_2", + "CLK_BUFG_LOGIC_OUTS_B0_3", + "CLK_BUFG_CK_GCLK7", + "CLK_BUFG_R_CK_FB_TEST1_11", + "CLK_HROW_NE2A3_2", + "CLK_BUFG_R_CK_FB_TEST0_6", + "CLK_HROW_WW4END1_3", + "CLK_HROW_EE2BEG1_0", + "CLK_BUFG_R_FBG_OUT14", + "CLK_HROW_NW4END0_0", + "CLK_HROW_SE2A2_1", + "CLK_BUFG_BUFGCTRL1_I1", + "CLK_HROW_FAN5_0", + "CLK_BUFG_IMUX41_2", + "CLK_BUFG_IMUX26_3", + "CLK_BUFG_R_BUFGCTRL2_IGNORE1", + "CLK_HROW_SE2A0_1", + "CLK_BUFG_BUFGCTRL2_O", + "CLK_HROW_FAN2_2", + "CLK_HROW_WL1END2_0", + "CLK_HROW_LH8_1", + "CLK_BUFG_LOGIC_OUTS_B14_3", + "CLK_BUFG_IMUX16_1", + "CLK_HROW_NW4A2_1", + "CLK_HROW_NW4END0_3", + "CLK_HROW_ER1BEG0_1", + "CLK_BUFG_R_CK_FB_TEST0_8", + "CLK_BUFG_R_BUFGCTRL14_S0", + "CLK_HROW_BLOCK_OUTS_B0_0", + "CLK_BUFG_CK_GCLK19", + "CLK_HROW_EE2BEG3_3", + "CLK_HROW_EE2A0_2", + "CLK_HROW_WW2A1_3", + "CLK_HROW_BYP2_0", + "CLK_BUFG_LOGIC_OUTS_B2_1", + "CLK_HROW_LH2_0", + "CLK_BUFG_IMUX36_1", + "CLK_BUFG_LOGIC_OUTS_B0_2", + "CLK_BUFG_R_BUFGCTRL0_CE1", + "CLK_BUFG_LOGIC_OUTS_B18_3", + "CLK_BUFG_IMUX16_0", + "CLK_BUFG_TOP_R_CK_MUXED9", + "CLK_HROW_EE4C1_0", + "CLK_HROW_NW4END3_3", + "CLK_HROW_MONITOR_N_0", + "CLK_BUFG_LOGIC_OUTS_B3_2", + "CLK_HROW_BYP1_2", + "CLK_HROW_WW2END3_0", + "CLK_HROW_SW4END2_0", + "CLK_HROW_EE4B0_0", + "CLK_BUFG_IMUX43_2", + "CLK_HROW_FAN5_2", + "CLK_HROW_NW4A2_2", + "CLK_BUFG_LOGIC_OUTS_B19_2", + "CLK_BUFG_R_CK_FB_TEST0_15", + "CLK_BUFG_R_CK_FB_TEST0_0", + "CLK_HROW_EE4BEG1_2", + "CLK_BUFG_LOGIC_OUTS_B17_1", + "CLK_BUFG_R_FBG_OUT5", + "CLK_BUFG_R_CK_FB_TEST0_14", + "CLK_HROW_BLOCK_OUTS_B1_0", + "CLK_HROW_LH7_2", + "CLK_HROW_MONITOR_P_2", + "CLK_BUFG_R_BUFGCTRL3_S1", + "CLK_HROW_ER1BEG1_0", + "CLK_HROW_EE4C3_0", + "CLK_HROW_SW4A3_1", + "CLK_HROW_SE4C1_0", + "CLK_HROW_SW2A2_2", + "CLK_BUFG_IMUX23_2", + "CLK_BUFG_R_BUFGCTRL15_CE0", + "CLK_HROW_SW4A1_0", + "CLK_HROW_WR1END0_2", + "CLK_BUFG_IMUX38_0", + "CLK_HROW_SE4BEG3_1", + "CLK_BUFG_LOGIC_OUTS_B22_0", + "CLK_BUFG_R_CK_FB_TEST1_7", + "CLK_HROW_SW2A0_2", + "CLK_HROW_NE4C3_1", + "CLK_HROW_NW2A2_1", + "CLK_BUFG_BUFGCTRL10_I0", + "CLK_HROW_EE4C0_2", + "CLK_HROW_WR1END0_0", + "CLK_BUFG_R_BUFGCTRL9_CE0", + "CLK_HROW_WW4A1_0", + "CLK_BUFG_TOP_R_CK_MUXED17", + "CLK_BUFG_CK_GCLK29", + "CLK_HROW_NW2A1_2", + "CLK_HROW_LH11_3", + "CLK_BUFG_R_BUFGCTRL15_CE1", + "CLK_BUFG_BUFGCTRL7_O", + "CLK_BUFG_LOGIC_OUTS_B20_0", + "CLK_BUFG_IMUX32_3", + "CLK_BUFG_IMUX37_1", + "CLK_HROW_EE4A3_1", + "CLK_HROW_SE4BEG2_2", + "CLK_HROW_EL1BEG1_3", + "CLK_HROW_EE4B1_3", + "CLK_BUFG_IMUX2_2", + "CLK_BUFG_TOP_R_CK_MUXED8", + "CLK_BUFG_IMUX13_2", + "CLK_HROW_SW2A0_1", + "CLK_HROW_MONITOR_N_1", + "CLK_HROW_WW4A3_2", + "CLK_BUFG_TOP_R_CK_MUXED21", + "CLK_BUFG_R_BUFGCTRL1_IGNORE1", + "CLK_HROW_EE4B2_0", + "CLK_BUFG_R_FBG_OUT3", + "CLK_HROW_WW2END2_2", + "CLK_BUFG_R_BUFGCTRL7_CE1", + "CLK_BUFG_LOGIC_OUTS_B4_2", + "CLK_BUFG_R_BUFGCTRL6_IGNORE1", + "CLK_BUFG_R_CK_FB_TEST1_3", + "CLK_HROW_EE4C1_2", + "CLK_BUFG_R_BUFGCTRL9_S1", + "CLK_HROW_NW4END2_1", + "CLK_HROW_WL1END0_0", + "CLK_BUFG_IMUX44_2", + "CLK_BUFG_TOP_R_CK_MUXED6", + "CLK_HROW_FAN7_2", + "CLK_HROW_WW4C0_2", + "CLK_BUFG_LOGIC_OUTS_B21_2", + "CLK_BUFG_BUFGCTRL4_I1", + "CLK_BUFG_LOGIC_OUTS_B17_3", + "CLK_BUFG_R_BUFGCTRL15_S1", + "CLK_HROW_WW4B3_3", + "CLK_HROW_NE4BEG2_3", + "CLK_HROW_EE4C0_0", + "CLK_HROW_EE2BEG0_2", + "CLK_HROW_NE4C3_2", + "CLK_BUFG_IMUX15_3", + "CLK_HROW_FAN1_3", + "CLK_BUFG_BUFGCTRL14_I1", + "CLK_BUFG_CK_GCLK23", + "CLK_BUFG_R_BUFGCTRL3_CE0", + "CLK_HROW_LH1_2", + "CLK_HROW_SE2A3_3", + "CLK_HROW_SE4BEG3_0", + "CLK_BUFG_IMUX35_3", + "CLK_HROW_WL1END0_3", + "CLK_HROW_BYP6_1", + "CLK_HROW_ER1BEG3_0", + "CLK_HROW_WW4END1_0", + "CLK_HROW_FAN3_0", + "CLK_BUFG_BUFGCTRL5_O", + "CLK_BUFG_BUFGCTRL15_I1", + "CLK_BUFG_TOP_R_CK_MUXED14", + "CLK_BUFG_IMUX14_1", + "CLK_HROW_WR1END0_1", + "CLK_HROW_NE4BEG3_3", + "CLK_BUFG_BUFGCTRL13_I1", + "CLK_HROW_CLK1_3", + "CLK_BUFG_LOGIC_OUTS_B1_1", + "CLK_BUFG_LOGIC_OUTS_B6_1", + "CLK_HROW_SW2A3_2", + "CLK_HROW_EE4A1_0", + "CLK_HROW_EL1BEG2_2", + "CLK_BUFG_R_BUFGCTRL4_IGNORE1", + "CLK_BUFG_R_BUFGCTRL1_S0", + "CLK_BUFG_TOP_R_CK_MUXED28", + "CLK_HROW_WW4A0_3", + "CLK_HROW_WW2A3_0", + "CLK_BUFG_TOP_R_CK_MUXED11", + "CLK_BUFG_IMUX46_2", + "CLK_HROW_EE2BEG0_0", + "CLK_HROW_WW4B2_0", + "CLK_HROW_EE4BEG0_1", + "CLK_HROW_WW2END0_1", + "CLK_HROW_ER1BEG0_0", + "CLK_HROW_SE4BEG1_3", + "CLK_BUFG_R_BUFGCTRL2_S1", + "CLK_BUFG_IMUX14_0", + "CLK_HROW_WW4A3_0", + "CLK_BUFG_IMUX16_3", + "CLK_BUFG_LOGIC_OUTS_B21_1", + "CLK_HROW_EE4C1_1", + "CLK_HROW_BYP7_3", + "CLK_HROW_WW4C3_1", + "CLK_HROW_NE4BEG3_2", + "CLK_HROW_WW2A0_3", + "CLK_BUFG_IMUX44_1", + "CLK_BUFG_R_BUFGCTRL2_IGNORE0", + "CLK_HROW_WW2A2_3", + "CLK_BUFG_LOGIC_OUTS_B10_1", + "CLK_HROW_FAN3_2", + "CLK_BUFG_LOGIC_OUTS_B23_0", + "CLK_HROW_EE2A1_1", + "CLK_HROW_EE4B0_2", + "CLK_HROW_WL1END3_1", + "CLK_HROW_EE2A0_3", + "CLK_BUFG_CK_GCLK18", + "CLK_BUFG_R_BUFGCTRL11_S0", + "CLK_HROW_EE4A0_0", + "CLK_HROW_WW4END2_2", + "CLK_BUFG_IMUX11_0", + "CLK_BUFG_R_BUFGCTRL10_CE1", + "CLK_HROW_SE2A1_3", + "CLK_BUFG_IMUX31_2", + "CLK_HROW_BLOCK_OUTS_B1_3", + "CLK_HROW_SW2A2_0", + "CLK_HROW_WW4C2_1", + "CLK_HROW_EE2BEG2_1", + "CLK_BUFG_CK_GCLK12", + "CLK_BUFG_IMUX11_2", + "CLK_BUFG_R_BUFGCTRL13_CE0", + "CLK_BUFG_BUFGCTRL5_I1", + "CLK_BUFG_BUFGCTRL10_I1", + "CLK_HROW_WW4B2_3", + "CLK_HROW_SW4A1_2", + "CLK_BUFG_R_BUFGCTRL3_S0", + "CLK_HROW_CLK0_1", + "CLK_BUFG_LOGIC_OUTS_B5_3", + "CLK_HROW_NW4A2_0", + "CLK_BUFG_R_BUFGCTRL12_IGNORE1", + "CLK_BUFG_R_BUFGCTRL4_S0", + "CLK_BUFG_IMUX5_3", + "CLK_HROW_WL1END1_0", + "CLK_HROW_SE2A2_3", + "CLK_BUFG_R_BUFGCTRL15_S0", + "CLK_BUFG_IMUX27_2", + "CLK_HROW_WW4C3_0", + "CLK_BUFG_R_CK_FB_TEST0_12", + "CLK_BUFG_IMUX0_0", + "CLK_HROW_BLOCK_OUTS_B0_1", + "CLK_BUFG_R_BUFGCTRL8_CE1", + "CLK_HROW_WW4END3_1", + "CLK_HROW_EE4BEG2_2", + "CLK_BUFG_R_FBG_OUT7", + "CLK_HROW_NW4A0_3", + "CLK_HROW_FAN4_0", + "CLK_HROW_NW4A1_1", + "CLK_BUFG_IMUX12_1", + "CLK_BUFG_IMUX40_3", + "CLK_HROW_WW4A2_1", + "CLK_BUFG_IMUX8_3", + "CLK_HROW_NW2A0_0", + "CLK_HROW_NE4BEG1_2", + "CLK_HROW_BYP4_3", + "CLK_BUFG_BUFGCTRL5_I0", + "CLK_BUFG_R_BUFGCTRL14_IGNORE1", + "CLK_BUFG_IMUX7_3", + "CLK_HROW_FAN5_1", + "CLK_HROW_WW4B3_1", + "CLK_BUFG_LOGIC_OUTS_B11_3", + "CLK_BUFG_IMUX40_1", + "CLK_HROW_WW4END0_1", + "CLK_HROW_NE2A3_3", + "CLK_BUFG_R_BUFGCTRL5_IGNORE0", + "CLK_BUFG_TOP_R_CK_MUXED7", + "CLK_BUFG_R_BUFGCTRL6_IGNORE0", + "CLK_BUFG_LOGIC_OUTS_B12_2", + "CLK_BUFG_BUFGCTRL15_I0", + "CLK_HROW_EE4BEG1_3", + "CLK_HROW_WR1END3_3", + "CLK_HROW_SW4END1_0", + "CLK_BUFG_IMUX28_3", + "CLK_HROW_MONITOR_P_1", + "CLK_HROW_BYP2_3", + "CLK_BUFG_TOP_R_CK_MUXED31", + "CLK_BUFG_BUFGCTRL0_I0", + "CLK_BUFG_R_FBG_OUT13", + "CLK_BUFG_R_BUFGCTRL9_IGNORE1", + "CLK_HROW_WW4END2_0", + "CLK_BUFG_BUFGCTRL0_O", + "CLK_BUFG_IMUX33_3", + "CLK_BUFG_IMUX25_1", + "CLK_HROW_WW4END3_3", + "CLK_BUFG_R_BUFGCTRL4_CE1", + "CLK_BUFG_R_FBG_OUT10", + "CLK_BUFG_IMUX1_0", + "CLK_HROW_EE4A0_1", + "CLK_HROW_LH3_3", + "CLK_HROW_BYP0_0", + "CLK_BUFG_IMUX32_2", + "CLK_BUFG_R_BUFGCTRL11_CE0", + "CLK_BUFG_LOGIC_OUTS_B18_2", + "CLK_HROW_NW2A0_1", + "CLK_BUFG_BUFGCTRL2_I0", + "CLK_BUFG_BUFGCTRL2_I1", + "CLK_HROW_EE4A2_3", + "CLK_HROW_FAN6_0", + "CLK_BUFG_LOGIC_OUTS_B21_3", + "CLK_HROW_WW4C0_0", + "CLK_BUFG_CK_GCLK9", + "CLK_HROW_WL1END0_2", + "CLK_HROW_EE2BEG3_1", + "CLK_HROW_EE4A2_0", + "CLK_HROW_EE4B3_0", + "CLK_BUFG_BUFGCTRL8_I1", + "CLK_BUFG_IMUX30_1", + "CLK_BUFG_IMUX2_1", + "CLK_HROW_LH4_0", + "CLK_BUFG_LOGIC_OUTS_B21_0", + "CLK_BUFG_IMUX45_1", + "CLK_BUFG_LOGIC_OUTS_B16_2", + "CLK_BUFG_R_BUFGCTRL10_IGNORE1", + "CLK_HROW_CTRL0_1", + "CLK_BUFG_TOP_R_CK_MUXED5", + "CLK_BUFG_IMUX46_3", + "CLK_BUFG_IMUX42_2", + "CLK_BUFG_IMUX3_2", + "CLK_BUFG_BUFGCTRL6_I1", + "CLK_HROW_NE2A1_3", + "CLK_HROW_SE4C0_1", + "CLK_BUFG_IMUX27_3", + "CLK_HROW_SE2A0_3", + "CLK_HROW_LH8_0", + "CLK_HROW_LH12_1", + "CLK_HROW_WW2END3_3", + "CLK_HROW_NE4C0_0", + "CLK_BUFG_IMUX41_1", + "CLK_HROW_LH11_2", + "CLK_HROW_NE2A1_2", + "CLK_BUFG_R_BUFGCTRL3_IGNORE1", + "CLK_HROW_NE2A0_0", + "CLK_HROW_WW4END0_3", + "CLK_HROW_EE4C0_1", + "CLK_BUFG_IMUX17_0", + "CLK_BUFG_LOGIC_OUTS_B7_2", + "CLK_HROW_NE4BEG0_1", + "CLK_BUFG_IMUX35_1", + "CLK_HROW_WL1END3_0", + "CLK_BUFG_IMUX36_0", + "CLK_HROW_SE4BEG2_3", + "CLK_HROW_WW2A0_0", + "CLK_BUFG_IMUX47_3", + "CLK_HROW_EE2A1_2", + "CLK_BUFG_R_BUFGCTRL4_CE0", + "CLK_HROW_SW2A0_0", + "CLK_HROW_EE2A0_1", + "CLK_HROW_SW4A2_1", + "CLK_HROW_FAN0_1", + "CLK_HROW_EE2BEG2_2", + "CLK_HROW_WL1END0_1", + "CLK_HROW_WL1END2_3", + "CLK_BUFG_LOGIC_OUTS_B15_3", + "CLK_HROW_WL1END1_1", + "CLK_HROW_BYP6_0", + "CLK_BUFG_R_CK_FB_TEST1_14", + "CLK_HROW_NW4END2_2", + "CLK_BUFG_LOGIC_OUTS_B6_2", + "CLK_BUFG_R_CK_FB_TEST0_2", + "CLK_HROW_NE4C1_1", + "CLK_BUFG_IMUX33_1", + "CLK_HROW_EE4C2_2", + "CLK_BUFG_IMUX10_2", + "CLK_BUFG_IMUX30_3", + "CLK_HROW_LH3_2", + "CLK_HROW_BLOCK_OUTS_B2_1", + "CLK_BUFG_IMUX21_3", + "CLK_HROW_SW4END0_2", + "CLK_HROW_SW4A0_2", + "CLK_BUFG_CK_GCLK11", + "CLK_BUFG_TOP_R_CK_MUXED27", + "CLK_BUFG_R_BUFGCTRL8_IGNORE1", + "CLK_HROW_CTRL0_0", + "CLK_BUFG_IMUX8_1", + "CLK_BUFG_LOGIC_OUTS_B5_1", + "CLK_BUFG_R_BUFGCTRL2_S0", + "CLK_HROW_LH2_1", + "CLK_BUFG_IMUX2_0", + "CLK_BUFG_IMUX20_2", + "CLK_BUFG_IMUX8_0", + "CLK_BUFG_R_BUFGCTRL2_CE0", + "CLK_BUFG_IMUX4_3", + "CLK_HROW_NW4A0_0", + "CLK_HROW_WW4C1_3", + "CLK_BUFG_LOGIC_OUTS_B1_2", + "CLK_HROW_SE2A3_0", + "CLK_BUFG_LOGIC_OUTS_B11_0", + "CLK_HROW_EE4BEG0_2", + "CLK_HROW_EE4C2_3", + "CLK_HROW_EL1BEG0_3", + "CLK_HROW_WW4A0_0", + "CLK_HROW_WW2A3_3", + "CLK_BUFG_LOGIC_OUTS_B4_3", + "CLK_BUFG_BUFGCTRL14_I0", + "CLK_HROW_WR1END2_0", + "CLK_HROW_LH10_0", + "CLK_BUFG_R_BUFGCTRL12_IGNORE0", + "CLK_HROW_WW4B0_3", + "CLK_BUFG_IMUX9_1", + "CLK_BUFG_R_FBG_OUT2", + "CLK_HROW_NW2A3_1", + "CLK_HROW_EE4C1_3", + "CLK_HROW_FAN7_0", + "CLK_HROW_WW2A1_2", + "CLK_BUFG_R_CK_FB_TEST1_13", + "CLK_HROW_EE4C0_3", + "CLK_HROW_FAN5_3", + "CLK_HROW_NE2A3_0", + "CLK_HROW_SW4A2_0", + "CLK_BUFG_R_BUFGCTRL13_IGNORE1", + "CLK_HROW_WW2END2_3", + "CLK_HROW_CLK0_3", + "CLK_BUFG_R_BUFGCTRL4_S1", + "CLK_BUFG_CK_GCLK14", + "CLK_BUFG_IMUX34_1", + "CLK_BUFG_R_BUFGCTRL5_CE1", + "CLK_BUFG_LOGIC_OUTS_B0_0", + "CLK_HROW_WL1END3_3", + "CLK_HROW_LH2_2", + "CLK_BUFG_TOP_R_CK_MUXED30", + "CLK_HROW_WW2END0_3", + "CLK_BUFG_IMUX11_3", + "CLK_HROW_EE4BEG0_0", + "CLK_HROW_CTRL1_0", + "CLK_BUFG_IMUX15_0", + "CLK_HROW_SE4BEG0_3", + "CLK_HROW_BLOCK_OUTS_B1_1", + "CLK_HROW_EE4BEG2_1", + "CLK_BUFG_R_BUFGCTRL7_CE0", + "CLK_BUFG_IMUX28_0", + "CLK_BUFG_IMUX18_0", + "CLK_BUFG_LOGIC_OUTS_B16_0", + "CLK_HROW_NW2A0_3", + "CLK_BUFG_IMUX25_3", + "CLK_BUFG_IMUX20_0", + "CLK_HROW_BYP7_0", + "CLK_HROW_EE4B3_3", + "CLK_BUFG_TOP_R_CK_MUXED26", + "CLK_HROW_LH7_1", + "CLK_BUFG_IMUX7_1", + "CLK_HROW_SE4BEG3_3", + "CLK_BUFG_R_BUFGCTRL2_CE1", + "CLK_HROW_SW4A0_1", + "CLK_HROW_EE2BEG1_1", + "CLK_HROW_SW4END2_3", + "CLK_BUFG_CK_GCLK20", + "CLK_HROW_LH8_3", + "CLK_HROW_SE4C2_3", + "CLK_BUFG_R_BUFGCTRL13_S1", + "CLK_HROW_EE4BEG1_1", + "CLK_HROW_BYP5_1", + "CLK_BUFG_IMUX0_2", + "CLK_HROW_BLOCK_OUTS_B2_3", + "CLK_BUFG_LOGIC_OUTS_B22_1", + "CLK_BUFG_IMUX29_2", + "CLK_HROW_NW2A3_2", + "CLK_BUFG_R_CK_FB_TEST1_5", + "CLK_BUFG_LOGIC_OUTS_B8_1", + "CLK_HROW_EE4C3_3", + "CLK_BUFG_IMUX32_1", + "CLK_BUFG_BUFGCTRL4_O", + "CLK_HROW_SW4A2_3", + "CLK_BUFG_R_BUFGCTRL11_IGNORE1", + "CLK_BUFG_IMUX6_0", + "CLK_HROW_EL1BEG0_1", + "CLK_BUFG_BUFGCTRL6_I0", + "CLK_BUFG_IMUX31_0", + "CLK_HROW_FAN2_3", + "CLK_HROW_FAN4_1", + "CLK_BUFG_IMUX16_2", + "CLK_BUFG_LOGIC_OUTS_B20_2", + "CLK_BUFG_IMUX45_0", + "CLK_BUFG_IMUX24_0", + "CLK_BUFG_CK_GCLK16", + "CLK_HROW_BLOCK_OUTS_B3_2", + "CLK_BUFG_R_BUFGCTRL10_S0", + "CLK_BUFG_TOP_R_CK_MUXED15", + "CLK_BUFG_R_BUFGCTRL10_CE0", + "CLK_HROW_WW4A3_3", + "CLK_BUFG_IMUX47_0", + "CLK_HROW_WW4C2_3", + "CLK_BUFG_IMUX19_1", + "CLK_HROW_WW4B0_2", + "CLK_HROW_LH8_2", + "CLK_HROW_EL1BEG3_0", + "CLK_HROW_EL1BEG1_0", + "CLK_HROW_EE4B0_1", + "CLK_BUFG_LOGIC_OUTS_B7_3", + "CLK_HROW_LH1_0", + "CLK_HROW_LH12_2", + "CLK_BUFG_IMUX42_0", + "CLK_HROW_WW2A0_1", + "CLK_HROW_WW2END3_2", + "CLK_BUFG_IMUX25_0", + "CLK_BUFG_IMUX15_2", + "CLK_HROW_LH6_2", + "CLK_BUFG_BUFGCTRL6_O", + "CLK_BUFG_IMUX14_3", + "CLK_HROW_FAN2_0", + "CLK_HROW_SE4BEG0_2", + "CLK_HROW_BYP3_0", + "CLK_HROW_EE4B0_3", + "CLK_BUFG_IMUX34_2", + "CLK_BUFG_LOGIC_OUTS_B22_3", + "CLK_BUFG_LOGIC_OUTS_B9_1", + "CLK_HROW_MONITOR_N_3", + "CLK_HROW_FAN1_2", + "CLK_BUFG_R_BUFGCTRL1_S1", + "CLK_BUFG_IMUX3_0", + "CLK_BUFG_IMUX5_0", + "CLK_HROW_NW2A3_3", + "CLK_HROW_BYP4_1", + "CLK_BUFG_CK_GCLK4", + "CLK_BUFG_IMUX43_1", + "CLK_HROW_LH6_1", + "CLK_BUFG_R_BUFGCTRL8_S1", + "CLK_HROW_EE4B3_1", + "CLK_BUFG_CK_GCLK24", + "CLK_BUFG_BUFGCTRL12_I0", + "CLK_HROW_LH3_1", + "CLK_HROW_NE4C2_1", + "CLK_BUFG_TOP_R_CK_MUXED23", + "CLK_BUFG_IMUX30_2", + "CLK_HROW_MONITOR_P_3", + "CLK_HROW_WW4C3_2", + "CLK_BUFG_R_BUFGCTRL7_IGNORE1", + "CLK_BUFG_BUFGCTRL4_I0", + "CLK_HROW_EE4BEG3_2", + "CLK_HROW_SE4C3_0", + "CLK_HROW_NE4BEG0_3", + "CLK_BUFG_IMUX47_1", + "CLK_BUFG_LOGIC_OUTS_B9_2", + "CLK_BUFG_CK_GCLK5", + "CLK_BUFG_IMUX33_0", + "CLK_BUFG_IMUX9_3", + "CLK_BUFG_R_CK_FB_TEST1_12", + "CLK_HROW_WW2END3_1", + "CLK_HROW_WW4B2_2", + "CLK_BUFG_BUFGCTRL11_I0", + "CLK_HROW_WW2END1_3", + "CLK_HROW_EE4A1_1", + "CLK_HROW_NW2A0_2", + "CLK_BUFG_IMUX4_1", + "CLK_BUFG_IMUX10_1", + "CLK_HROW_CLK0_0", + "CLK_HROW_NE2A2_1", + "CLK_HROW_BYP0_1", + "CLK_HROW_EE4A3_3", + "CLK_HROW_CLK1_0", + "CLK_HROW_NE4C0_1", + "CLK_BUFG_LOGIC_OUTS_B12_0", + "CLK_BUFG_LOGIC_OUTS_B20_3", + "CLK_HROW_FAN0_0", + "CLK_HROW_SE4BEG1_2", + "CLK_BUFG_IMUX22_2", + "CLK_BUFG_IMUX40_2", + "CLK_HROW_CTRL0_3", + "CLK_BUFG_LOGIC_OUTS_B10_2", + "CLK_HROW_WW4B1_2", + "CLK_BUFG_LOGIC_OUTS_B17_0", + "CLK_BUFG_LOGIC_OUTS_B14_0", + "CLK_BUFG_IMUX23_3", + "CLK_BUFG_R_BUFGCTRL0_S0", + "CLK_BUFG_LOGIC_OUTS_B14_1", + "CLK_BUFG_TOP_R_CK_MUXED13", + "CLK_BUFG_IMUX46_0", + "CLK_HROW_LH7_0", + "CLK_BUFG_R_BUFGCTRL12_CE1", + "CLK_HROW_WW4A3_1", + "CLK_BUFG_R_BUFGCTRL1_CE0", + "CLK_BUFG_TOP_R_CK_MUXED4", + "CLK_BUFG_IMUX30_0", + "CLK_HROW_LH6_3", + "CLK_BUFG_IMUX1_1", + "CLK_BUFG_R_BUFGCTRL0_IGNORE1", + "CLK_HROW_ER1BEG0_3", + "CLK_HROW_SW4END0_3", + "CLK_BUFG_IMUX32_0", + "CLK_BUFG_R_CK_FB_TEST1_1", + "CLK_HROW_EL1BEG2_1", + "CLK_HROW_EE2A2_2", + "CLK_BUFG_R_CK_FB_TEST0_4", + "CLK_HROW_SE4BEG1_0", + "CLK_HROW_BYP2_1", + "CLK_BUFG_CK_GCLK6", + "CLK_BUFG_R_CK_FB_TEST0_10", + "CLK_HROW_NE4C2_3", + "CLK_HROW_SW4END3_3", + "CLK_HROW_SE4C1_2", + "CLK_HROW_SE4C1_3", + "CLK_BUFG_CK_GCLK13", + "CLK_BUFG_IMUX1_2", + "CLK_BUFG_IMUX45_2", + "CLK_BUFG_IMUX18_2", + "CLK_HROW_EL1BEG0_0", + "CLK_HROW_EE4A1_2", + "CLK_HROW_CLK0_2", + "CLK_BUFG_IMUX10_3", + "CLK_HROW_WW4END1_2", + "CLK_BUFG_LOGIC_OUTS_B15_1", + "CLK_BUFG_IMUX18_1", + "CLK_HROW_BYP1_0", + "CLK_HROW_WW2END0_2", + "CLK_HROW_EE4C3_2", + "CLK_HROW_NE4BEG3_1", + "CLK_HROW_BYP3_1", + "CLK_BUFG_R_BUFGCTRL8_CE0", + "CLK_BUFG_BUFGCTRL8_I0", + "CLK_BUFG_IMUX17_2", + "CLK_HROW_WW4B3_2", + "CLK_BUFG_IMUX39_1", + "CLK_HROW_WW4B0_1", + "CLK_HROW_BYP3_3", + "CLK_BUFG_IMUX39_3", + "CLK_BUFG_IMUX21_2", + "CLK_HROW_EL1BEG2_3", + "CLK_HROW_WW2A2_2", + "CLK_BUFG_IMUX9_0", + "CLK_HROW_SW4A3_3", + "CLK_HROW_BYP5_2", + "CLK_HROW_NW2A1_3", + "CLK_BUFG_LOGIC_OUTS_B12_3", + "CLK_HROW_WR1END1_1", + "CLK_BUFG_R_BUFGCTRL6_S1", + "CLK_HROW_SE2A1_1", + "CLK_HROW_WW4END0_2", + "CLK_HROW_NW2A2_0", + "CLK_HROW_SE2A3_1", + "CLK_BUFG_LOGIC_OUTS_B13_3", + "CLK_BUFG_BUFGCTRL11_I1", + "CLK_HROW_NW4A1_2", + "CLK_BUFG_IMUX46_1", + "CLK_HROW_EE4BEG3_0", + "CLK_HROW_LH11_1", + "CLK_BUFG_TOP_R_CK_MUXED16", + "CLK_HROW_NW2A2_3", + "CLK_HROW_BLOCK_OUTS_B2_0", + "CLK_HROW_WR1END2_3", + "CLK_HROW_EE2A1_0", + "CLK_HROW_NW4A0_1", + "CLK_HROW_NE4C0_3", + "CLK_HROW_WW4END1_1", + "CLK_HROW_FAN3_1", + "CLK_HROW_BYP5_0", + "CLK_HROW_NE4BEG2_2", + "CLK_BUFG_R_CK_FB_TEST1_15", + "CLK_HROW_SE4BEG3_2", + "CLK_BUFG_R_BUFGCTRL13_IGNORE0", + "CLK_HROW_WL1END3_2", + "CLK_HROW_EE4A2_1", + "CLK_HROW_SE4BEG0_0", + "CLK_BUFG_IMUX35_2", + "CLK_BUFG_IMUX10_0", + "CLK_HROW_SW2A2_3", + "CLK_HROW_WW4C1_0", + "CLK_BUFG_R_BUFGCTRL13_S0", + "CLK_HROW_WR1END2_1", + "CLK_HROW_WW4A1_2", + "CLK_BUFG_IMUX6_3", + "CLK_HROW_NW4END1_3", + "CLK_BUFG_LOGIC_OUTS_B4_1", + "CLK_HROW_EE4B3_2", + "CLK_BUFG_R_BUFGCTRL7_S0", + "CLK_BUFG_R_FBG_OUT0", + "CLK_HROW_EE4B1_1", + "CLK_HROW_NE2A0_1", + "CLK_BUFG_IMUX22_3", + "CLK_HROW_NW4A2_3", + "CLK_HROW_SE2A0_0", + "CLK_BUFG_IMUX26_1", + "CLK_BUFG_R_CK_FB_TEST0_9", + "CLK_BUFG_IMUX47_2", + "CLK_BUFG_R_FBG_OUT8", + "CLK_BUFG_IMUX22_1", + "CLK_HROW_SW4END2_1", + "CLK_HROW_SW4A1_3", + "CLK_HROW_SW4A0_3", + "CLK_HROW_LH10_2", + "CLK_BUFG_IMUX27_0", + "CLK_HROW_CTRL1_2", + "CLK_HROW_NE4C1_0", + "CLK_BUFG_IMUX7_2", + "CLK_HROW_EE4B1_2", + "CLK_BUFG_LOGIC_OUTS_B2_0", + "CLK_HROW_SE4C0_2", + "CLK_HROW_EE4A0_3", + "CLK_HROW_NE4BEG2_1", + "CLK_BUFG_BUFGCTRL12_O", + "CLK_BUFG_LOGIC_OUTS_B4_0", + "CLK_HROW_WW2A2_0", + "CLK_BUFG_BUFGCTRL7_I0", + "CLK_BUFG_IMUX24_1", + "CLK_HROW_ER1BEG1_1", + "CLK_BUFG_R_BUFGCTRL12_S0", + "CLK_BUFG_LOGIC_OUTS_B10_0", + "CLK_HROW_NW4A3_2", + "CLK_BUFG_R_BUFGCTRL8_S0", + "CLK_BUFG_LOGIC_OUTS_B6_3", + "CLK_HROW_FAN1_1", + "CLK_BUFG_CK_GCLK21", + "CLK_HROW_NW4A3_1", + "CLK_HROW_NW4END2_0", + "CLK_BUFG_TOP_R_CK_MUXED2", + "CLK_BUFG_IMUX13_1", + "CLK_HROW_BYP2_2", + "CLK_HROW_EE2A2_1", + "CLK_BUFG_LOGIC_OUTS_B14_2", + "CLK_HROW_CTRL1_1", + "CLK_HROW_WW2A1_1", + "CLK_HROW_EE2A3_0", + "CLK_HROW_SW4A3_2", + "CLK_BUFG_IMUX39_2", + "CLK_HROW_EE4BEG3_3", + "CLK_BUFG_LOGIC_OUTS_B22_2", + "CLK_BUFG_R_BUFGCTRL6_S0", + "CLK_HROW_WW4C2_2", + "CLK_BUFG_R_BUFGCTRL6_CE0", + "CLK_BUFG_LOGIC_OUTS_B13_1", + "CLK_HROW_CTRL1_3", + "CLK_BUFG_R_BUFGCTRL12_CE0", + "CLK_BUFG_BUFGCTRL9_I0", + "CLK_BUFG_LOGIC_OUTS_B16_1", + "CLK_BUFG_IMUX23_1", + "CLK_BUFG_IMUX38_2", + "CLK_BUFG_IMUX3_3", + "CLK_HROW_NW4END0_1", + "CLK_HROW_SW2A3_1", + "CLK_BUFG_IMUX33_2", + "CLK_BUFG_IMUX31_3", + "CLK_HROW_SW2A2_1", + "CLK_HROW_WR1END3_0", + "CLK_HROW_SW2A3_0", + "CLK_BUFG_R_CK_FB_TEST0_1", + "CLK_BUFG_CK_GCLK30", + "CLK_HROW_EL1BEG2_0", + "CLK_BUFG_CK_GCLK10", + "CLK_HROW_LH12_0", + "CLK_HROW_WR1END1_0", + "CLK_HROW_NW4END3_1", + "CLK_HROW_EE2A2_3", + "CLK_HROW_LH4_3", + "CLK_BUFG_IMUX35_0", + "CLK_HROW_SW4A1_1", + "CLK_BUFG_TOP_R_CK_MUXED1", + "CLK_BUFG_BUFGCTRL13_O", + "CLK_BUFG_R_FBG_OUT12", + "CLK_HROW_ER1BEG1_3", + "CLK_HROW_EE4A1_3", + "CLK_BUFG_IMUX21_1", + "CLK_HROW_EE2BEG0_3", + "CLK_HROW_SW2A0_3", + "CLK_BUFG_IMUX0_1", + "CLK_HROW_NE4BEG0_2", + "CLK_BUFG_LOGIC_OUTS_B20_1", + "CLK_HROW_NE2A3_1", + "CLK_HROW_EE4C2_0", + "CLK_BUFG_IMUX28_2", + "CLK_HROW_WW4A0_1", + "CLK_HROW_WW2END2_0", + "CLK_BUFG_BUFGCTRL1_O", + "CLK_HROW_NW4END3_2", + "CLK_HROW_LH3_0", + "CLK_HROW_WW4A2_3", + "CLK_HROW_EE2A1_3", + "CLK_HROW_BYP7_2", + "CLK_BUFG_LOGIC_OUTS_B8_0", + "CLK_BUFG_IMUX12_3", + "CLK_BUFG_TOP_R_CK_MUXED25", + "CLK_HROW_WL1END1_2", + "CLK_BUFG_R_FBG_OUT1", + "CLK_BUFG_LOGIC_OUTS_B3_3", + "CLK_BUFG_R_BUFGCTRL0_IGNORE0", + "CLK_HROW_EL1BEG1_2", + "CLK_HROW_LH12_3", + "CLK_HROW_SE2A2_2", + "CLK_BUFG_IMUX29_3", + "CLK_HROW_FAN7_3", + "CLK_HROW_ER1BEG0_2", + "CLK_HROW_EE4A0_2", + "CLK_BUFG_LOGIC_OUTS_B9_3", + "CLK_BUFG_CK_GCLK27", + "CLK_BUFG_R_BUFGCTRL5_CE0", + "CLK_BUFG_IMUX44_0", + "CLK_HROW_NE2A0_2", + "CLK_HROW_WW4END2_3", + "CLK_HROW_SW4END3_1", + "CLK_BUFG_IMUX25_2", + "CLK_HROW_LH6_0", + "CLK_HROW_ER1BEG3_3", + "CLK_HROW_NE4C1_2", + "CLK_HROW_WW2END1_0", + "CLK_HROW_BLOCK_OUTS_B3_3", + "CLK_BUFG_R_CK_FB_TEST1_4", + "CLK_HROW_WL1END2_2", + "CLK_BUFG_IMUX42_1", + "CLK_HROW_WW4A1_3", + "CLK_HROW_WW4C0_3", + "CLK_BUFG_IMUX4_0", + "CLK_HROW_LH4_1", + "CLK_BUFG_IMUX37_0", + "CLK_HROW_SE2A0_2", + "CLK_HROW_BLOCK_OUTS_B1_2", + "CLK_BUFG_TOP_R_CK_MUXED22", + "CLK_BUFG_R_BUFGCTRL6_CE1", + "CLK_HROW_LH5_2", + "CLK_HROW_NW2A2_2", + "CLK_HROW_SE2A1_0", + "CLK_HROW_WW4B1_0", + "CLK_HROW_ER1BEG3_2", + "CLK_HROW_BLOCK_OUTS_B0_3", + "CLK_HROW_BYP4_0", + "CLK_HROW_LH4_2", + "CLK_BUFG_CK_GCLK15", + "CLK_BUFG_R_CK_FB_TEST0_3", + "CLK_HROW_WR1END0_3", + "CLK_HROW_WL1END1_3", + "CLK_HROW_EE4BEG1_0", + "CLK_BUFG_IMUX1_3", + "CLK_HROW_NW4END3_0", + "CLK_BUFG_LOGIC_OUTS_B12_1", + "CLK_BUFG_IMUX12_2", + "CLK_BUFG_TOP_R_CK_MUXED24", + "CLK_HROW_FAN1_0", + "CLK_HROW_FAN3_3", + "CLK_BUFG_LOGIC_OUTS_B10_3", + "CLK_HROW_LH1_1", + "CLK_HROW_WW4END2_1", + "CLK_BUFG_R_BUFGCTRL7_S1", + "CLK_BUFG_IMUX26_0", + "CLK_BUFG_LOGIC_OUTS_B9_0", + "CLK_HROW_EE4C3_1", + "CLK_BUFG_R_BUFGCTRL15_IGNORE1", + "CLK_BUFG_R_BUFGCTRL5_IGNORE1", + "CLK_BUFG_TOP_R_CK_MUXED3", + "CLK_HROW_CTRL0_2", + "CLK_BUFG_LOGIC_OUTS_B13_2", + "CLK_HROW_SE4C3_1", + "CLK_HROW_FAN4_3", + "CLK_HROW_WW2A2_1", + "CLK_HROW_FAN0_2", + "CLK_HROW_WW4A2_0", + "CLK_BUFG_IMUX22_0", + "CLK_HROW_LH5_1", + "CLK_HROW_EE4B2_3", + "CLK_HROW_BYP3_2", + "CLK_BUFG_LOGIC_OUTS_B2_2", + "CLK_HROW_BLOCK_OUTS_B2_2", + "CLK_HROW_NE2A2_0", + "CLK_HROW_EE2BEG2_0", + "CLK_BUFG_IMUX41_0", + "CLK_BUFG_IMUX20_3", + "CLK_BUFG_LOGIC_OUTS_B18_1", + "CLK_BUFG_IMUX8_2", + "CLK_HROW_LH10_1", + "CLK_HROW_BYP7_1", + "CLK_HROW_NE4C3_3", + "CLK_HROW_SW4A3_0", + "CLK_BUFG_R_CK_FB_TEST1_9", + "CLK_BUFG_IMUX13_3", + "CLK_BUFG_R_BUFGCTRL4_IGNORE0", + "CLK_BUFG_IMUX28_1", + "CLK_BUFG_BUFGCTRL11_O", + "CLK_HROW_NE4BEG3_0", + "CLK_HROW_BYP5_3", + "CLK_BUFG_BUFGCTRL12_I1", + "CLK_HROW_SE4BEG0_1", + "CLK_HROW_WR1END2_2", + "CLK_HROW_EE4A3_2", + "CLK_BUFG_CK_GCLK31", + "CLK_HROW_ER1BEG3_1", + "CLK_BUFG_IMUX6_2", + "CLK_BUFG_LOGIC_OUTS_B15_0", + "CLK_BUFG_R_CK_FB_TEST0_13", + "CLK_HROW_WR1END1_2", + "CLK_BUFG_IMUX17_3", + "CLK_HROW_EE2BEG0_1", + "CLK_HROW_ER1BEG2_0", + "CLK_HROW_WW2END1_2", + "CLK_BUFG_R_CK_FB_TEST1_2", + "CLK_HROW_NE4BEG0_0", + "CLK_HROW_EE4B1_0", + "CLK_HROW_NE2A1_1", + "CLK_HROW_EE4C2_1", + "CLK_HROW_NE4C3_0", + "CLK_HROW_CLK1_2", + "CLK_BUFG_BUFGCTRL15_O", + "CLK_BUFG_TOP_R_CK_MUXED12", + "CLK_HROW_WW4A0_2", + "CLK_BUFG_BUFGCTRL9_I1" + ], + "pips": { + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I0": { + "src_wire": "CLK_BUFG_IMUX27_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED15->>CLK_BUFG_BUFGCTRL7_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED15", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I0": { + "src_wire": "CLK_BUFG_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I0": { + "src_wire": "CLK_BUFG_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_2->>CLK_BUFG_R_BUFGCTRL10_S1": { + "src_wire": "CLK_BUFG_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I0": { + "src_wire": "CLK_BUFG_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_2->>CLK_BUFG_R_BUFGCTRL8_S1": { + "src_wire": "CLK_BUFG_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I1": { + "src_wire": "CLK_BUFG_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_CK_GCLK20": { + "src_wire": "CLK_BUFG_BUFGCTRL4_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I0": { + "src_wire": "CLK_BUFG_IMUX27_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_R_FBG_OUT2": { + "src_wire": "CLK_BUFG_BUFGCTRL2_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX12_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_0->>CLK_BUFG_R_BUFGCTRL3_S0": { + "src_wire": "CLK_BUFG_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I1": { + "src_wire": "CLK_BUFG_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_CK_GCLK22": { + "src_wire": "CLK_BUFG_BUFGCTRL6_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0->>CLK_BUFG_BUFGCTRL0_O": { + "src_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL0_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED17->>CLK_BUFG_BUFGCTRL8_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED17", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED12->>CLK_BUFG_BUFGCTRL6_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED12", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_0->>CLK_BUFG_R_BUFGCTRL3_CE1": { + "src_wire": "CLK_BUFG_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I1": { + "src_wire": "CLK_BUFG_IMUX26_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX10_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_CK_GCLK25": { + "src_wire": "CLK_BUFG_BUFGCTRL9_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I0": { + "src_wire": "CLK_BUFG_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_CK_GCLK24": { + "src_wire": "CLK_BUFG_BUFGCTRL8_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I1": { + "src_wire": "CLK_BUFG_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0->>CLK_BUFG_BUFGCTRL2_O": { + "src_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL2_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_0->>CLK_BUFG_R_BUFGCTRL3_S1": { + "src_wire": "CLK_BUFG_IMUX3_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I0": { + "src_wire": "CLK_BUFG_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I0": { + "src_wire": "CLK_BUFG_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_CK_GCLK21": { + "src_wire": "CLK_BUFG_BUFGCTRL5_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I0": { + "src_wire": "CLK_BUFG_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_CK_GCLK17": { + "src_wire": "CLK_BUFG_BUFGCTRL1_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_CK_GCLK30": { + "src_wire": "CLK_BUFG_BUFGCTRL14_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I0": { + "src_wire": "CLK_BUFG_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I1": { + "src_wire": "CLK_BUFG_IMUX31_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0->>CLK_BUFG_BUFGCTRL11_O": { + "src_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL11_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_R_FBG_OUT0": { + "src_wire": "CLK_BUFG_BUFGCTRL0_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED4->>CLK_BUFG_BUFGCTRL2_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED4", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX13_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_2->>CLK_BUFG_R_BUFGCTRL9_CE0": { + "src_wire": "CLK_BUFG_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_3->>CLK_BUFG_R_BUFGCTRL12_S1": { + "src_wire": "CLK_BUFG_IMUX0_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0->>CLK_BUFG_BUFGCTRL8_O": { + "src_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL8_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_2->>CLK_BUFG_R_BUFGCTRL8_CE0": { + "src_wire": "CLK_BUFG_IMUX20_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I0": { + "src_wire": "CLK_BUFG_IMUX31_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I1": { + "src_wire": "CLK_BUFG_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0->>CLK_BUFG_BUFGCTRL7_O": { + "src_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL7_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_1->>CLK_BUFG_R_BUFGCTRL5_CE1": { + "src_wire": "CLK_BUFG_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_3->>CLK_BUFG_R_BUFGCTRL13_S1": { + "src_wire": "CLK_BUFG_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_CK_GCLK16": { + "src_wire": "CLK_BUFG_BUFGCTRL0_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED30->>CLK_BUFG_BUFGCTRL15_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED30", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_0->>CLK_BUFG_R_BUFGCTRL0_S0": { + "src_wire": "CLK_BUFG_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I0": { + "src_wire": "CLK_BUFG_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0->>CLK_BUFG_BUFGCTRL4_O": { + "src_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL4_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX12_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX15_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_3->>CLK_BUFG_R_BUFGCTRL13_CE1": { + "src_wire": "CLK_BUFG_IMUX17_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED6->>CLK_BUFG_BUFGCTRL3_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED6", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0->>CLK_BUFG_BUFGCTRL3_O": { + "src_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL3_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED1->>CLK_BUFG_BUFGCTRL0_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX14_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I0": { + "src_wire": "CLK_BUFG_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_R_FBG_OUT14": { + "src_wire": "CLK_BUFG_BUFGCTRL14_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I1": { + "src_wire": "CLK_BUFG_IMUX24_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I0": { + "src_wire": "CLK_BUFG_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I0": { + "src_wire": "CLK_BUFG_IMUX25_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_0->>CLK_BUFG_R_BUFGCTRL0_S1": { + "src_wire": "CLK_BUFG_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED9->>CLK_BUFG_BUFGCTRL4_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED9", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED26->>CLK_BUFG_BUFGCTRL13_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED26", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_3->>CLK_BUFG_R_BUFGCTRL14_S1": { + "src_wire": "CLK_BUFG_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I0": { + "src_wire": "CLK_BUFG_IMUX30_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_1->>CLK_BUFG_R_BUFGCTRL7_S1": { + "src_wire": "CLK_BUFG_IMUX3_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_3->>CLK_BUFG_R_BUFGCTRL14_S0": { + "src_wire": "CLK_BUFG_IMUX6_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_1->>CLK_BUFG_R_BUFGCTRL6_S0": { + "src_wire": "CLK_BUFG_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_2->>CLK_BUFG_R_BUFGCTRL11_S0": { + "src_wire": "CLK_BUFG_IMUX7_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_1->>CLK_BUFG_R_BUFGCTRL7_S0": { + "src_wire": "CLK_BUFG_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_2->>CLK_BUFG_R_BUFGCTRL10_S0": { + "src_wire": "CLK_BUFG_IMUX6_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I0": { + "src_wire": "CLK_BUFG_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0->>CLK_BUFG_BUFGCTRL6_O": { + "src_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL6_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_2->>CLK_BUFG_R_BUFGCTRL8_CE1": { + "src_wire": "CLK_BUFG_IMUX16_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX11_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_3->>CLK_BUFG_R_BUFGCTRL14_CE0": { + "src_wire": "CLK_BUFG_IMUX22_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0->>CLK_BUFG_BUFGCTRL5_O": { + "src_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL5_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_1->>CLK_BUFG_R_BUFGCTRL4_CE1": { + "src_wire": "CLK_BUFG_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I1": { + "src_wire": "CLK_BUFG_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED24->>CLK_BUFG_BUFGCTRL12_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED24", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX8_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_R_FBG_OUT9": { + "src_wire": "CLK_BUFG_BUFGCTRL9_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_1->>CLK_BUFG_R_BUFGCTRL6_CE0": { + "src_wire": "CLK_BUFG_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_CK_GCLK18": { + "src_wire": "CLK_BUFG_BUFGCTRL2_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_0->>CLK_BUFG_R_BUFGCTRL0_CE0": { + "src_wire": "CLK_BUFG_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX9_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_3->>CLK_BUFG_R_BUFGCTRL12_S0": { + "src_wire": "CLK_BUFG_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_1->>CLK_BUFG_R_BUFGCTRL4_S1": { + "src_wire": "CLK_BUFG_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED5->>CLK_BUFG_BUFGCTRL2_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED5", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I0": { + "src_wire": "CLK_BUFG_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED16->>CLK_BUFG_BUFGCTRL8_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED16", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I0": { + "src_wire": "CLK_BUFG_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_R_FBG_OUT1": { + "src_wire": "CLK_BUFG_BUFGCTRL1_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I0": { + "src_wire": "CLK_BUFG_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I1": { + "src_wire": "CLK_BUFG_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I1": { + "src_wire": "CLK_BUFG_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED7->>CLK_BUFG_BUFGCTRL3_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED7", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I0": { + "src_wire": "CLK_BUFG_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_R_FBG_OUT6": { + "src_wire": "CLK_BUFG_BUFGCTRL6_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_3->>CLK_BUFG_R_BUFGCTRL12_CE0": { + "src_wire": "CLK_BUFG_IMUX20_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I1": { + "src_wire": "CLK_BUFG_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_0->>CLK_BUFG_R_BUFGCTRL2_CE0": { + "src_wire": "CLK_BUFG_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED3->>CLK_BUFG_BUFGCTRL1_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I1": { + "src_wire": "CLK_BUFG_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_CK_GCLK23": { + "src_wire": "CLK_BUFG_BUFGCTRL7_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_2->>CLK_BUFG_R_BUFGCTRL9_S1": { + "src_wire": "CLK_BUFG_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0->>CLK_BUFG_BUFGCTRL14_O": { + "src_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL14_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_1->>CLK_BUFG_R_BUFGCTRL5_S1": { + "src_wire": "CLK_BUFG_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I1": { + "src_wire": "CLK_BUFG_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX14_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED21->>CLK_BUFG_BUFGCTRL10_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED21", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED13->>CLK_BUFG_BUFGCTRL6_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED13", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I0": { + "src_wire": "CLK_BUFG_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED2->>CLK_BUFG_BUFGCTRL1_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_2->>CLK_BUFG_R_BUFGCTRL11_CE1": { + "src_wire": "CLK_BUFG_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I0": { + "src_wire": "CLK_BUFG_IMUX24_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I1": { + "src_wire": "CLK_BUFG_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_R_FBG_OUT8": { + "src_wire": "CLK_BUFG_BUFGCTRL8_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_3->>CLK_BUFG_R_BUFGCTRL15_CE1": { + "src_wire": "CLK_BUFG_IMUX19_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_CK_GCLK27": { + "src_wire": "CLK_BUFG_BUFGCTRL11_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_R_FBG_OUT3": { + "src_wire": "CLK_BUFG_BUFGCTRL3_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I0": { + "src_wire": "CLK_BUFG_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_1->>CLK_BUFG_R_BUFGCTRL4_CE0": { + "src_wire": "CLK_BUFG_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0->>CLK_BUFG_BUFGCTRL9_O": { + "src_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL9_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I1": { + "src_wire": "CLK_BUFG_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED27->>CLK_BUFG_BUFGCTRL13_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED27", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I0": { + "src_wire": "CLK_BUFG_IMUX26_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED19->>CLK_BUFG_BUFGCTRL9_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED19", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_2->>CLK_BUFG_R_BUFGCTRL8_S0": { + "src_wire": "CLK_BUFG_IMUX4_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_R_FBG_OUT12": { + "src_wire": "CLK_BUFG_BUFGCTRL12_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_3->>CLK_BUFG_R_BUFGCTRL15_S0": { + "src_wire": "CLK_BUFG_IMUX7_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED23->>CLK_BUFG_BUFGCTRL11_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED23", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I1": { + "src_wire": "CLK_BUFG_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_R_FBG_OUT11": { + "src_wire": "CLK_BUFG_BUFGCTRL11_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_1->>CLK_BUFG_R_BUFGCTRL5_S0": { + "src_wire": "CLK_BUFG_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX13_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX15_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_1->>CLK_BUFG_R_BUFGCTRL6_CE1": { + "src_wire": "CLK_BUFG_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_2->>CLK_BUFG_R_BUFGCTRL11_CE0": { + "src_wire": "CLK_BUFG_IMUX23_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I1": { + "src_wire": "CLK_BUFG_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I0": { + "src_wire": "CLK_BUFG_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_0->>CLK_BUFG_R_BUFGCTRL1_CE1": { + "src_wire": "CLK_BUFG_IMUX17_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I1": { + "src_wire": "CLK_BUFG_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I0": { + "src_wire": "CLK_BUFG_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED25->>CLK_BUFG_BUFGCTRL12_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED25", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0->>CLK_BUFG_BUFGCTRL1_O": { + "src_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL1_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I1": { + "src_wire": "CLK_BUFG_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I1": { + "src_wire": "CLK_BUFG_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I1": { + "src_wire": "CLK_BUFG_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_2->>CLK_BUFG_R_BUFGCTRL10_CE0": { + "src_wire": "CLK_BUFG_IMUX22_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I0": { + "src_wire": "CLK_BUFG_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED31->>CLK_BUFG_BUFGCTRL15_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED31", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_CK_GCLK26": { + "src_wire": "CLK_BUFG_BUFGCTRL10_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED14->>CLK_BUFG_BUFGCTRL7_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED14", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_R_FBG_OUT10": { + "src_wire": "CLK_BUFG_BUFGCTRL10_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0->>CLK_BUFG_BUFGCTRL15_O": { + "src_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL15_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_0->>CLK_BUFG_R_BUFGCTRL1_S1": { + "src_wire": "CLK_BUFG_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED20->>CLK_BUFG_BUFGCTRL10_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED20", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_2->>CLK_BUFG_R_BUFGCTRL10_CE1": { + "src_wire": "CLK_BUFG_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_1->>CLK_BUFG_R_BUFGCTRL7_CE0": { + "src_wire": "CLK_BUFG_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I1": { + "src_wire": "CLK_BUFG_IMUX25_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_3->>CLK_BUFG_R_BUFGCTRL13_S0": { + "src_wire": "CLK_BUFG_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED10->>CLK_BUFG_BUFGCTRL5_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED10", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX11_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0->>CLK_BUFG_BUFGCTRL13_O": { + "src_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL13_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_3->>CLK_BUFG_R_BUFGCTRL14_CE1": { + "src_wire": "CLK_BUFG_IMUX18_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_CK_GCLK28": { + "src_wire": "CLK_BUFG_BUFGCTRL12_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I1": { + "src_wire": "CLK_BUFG_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_3->>CLK_BUFG_R_BUFGCTRL15_CE0": { + "src_wire": "CLK_BUFG_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I1": { + "src_wire": "CLK_BUFG_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_CK_GCLK19": { + "src_wire": "CLK_BUFG_BUFGCTRL3_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_2->>CLK_BUFG_R_BUFGCTRL9_S0": { + "src_wire": "CLK_BUFG_IMUX5_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I1": { + "src_wire": "CLK_BUFG_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX11_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I1": { + "src_wire": "CLK_BUFG_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I1": { + "src_wire": "CLK_BUFG_IMUX30_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_0->>CLK_BUFG_R_BUFGCTRL2_CE1": { + "src_wire": "CLK_BUFG_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_R_FBG_OUT13": { + "src_wire": "CLK_BUFG_BUFGCTRL13_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE0": { + "src_wire": "CLK_BUFG_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_1->>CLK_BUFG_R_BUFGCTRL6_S1": { + "src_wire": "CLK_BUFG_IMUX2_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I1": { + "src_wire": "CLK_BUFG_IMUX27_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_0->>CLK_BUFG_R_BUFGCTRL1_CE0": { + "src_wire": "CLK_BUFG_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX9_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I1": { + "src_wire": "CLK_BUFG_IMUX24_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I0": { + "src_wire": "CLK_BUFG_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_R_FBG_OUT5": { + "src_wire": "CLK_BUFG_BUFGCTRL5_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED18->>CLK_BUFG_BUFGCTRL9_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED18", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_1->>CLK_BUFG_R_BUFGCTRL7_CE1": { + "src_wire": "CLK_BUFG_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_R_FBG_OUT4": { + "src_wire": "CLK_BUFG_BUFGCTRL4_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_0->>CLK_BUFG_R_BUFGCTRL1_S0": { + "src_wire": "CLK_BUFG_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED29->>CLK_BUFG_BUFGCTRL14_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED29", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_2->>CLK_BUFG_R_BUFGCTRL11_S1": { + "src_wire": "CLK_BUFG_IMUX3_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0->>CLK_BUFG_BUFGCTRL10_O": { + "src_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL10_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_CK_GCLK29": { + "src_wire": "CLK_BUFG_BUFGCTRL13_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_1->>CLK_BUFG_R_BUFGCTRL4_S0": { + "src_wire": "CLK_BUFG_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX11_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I1": { + "src_wire": "CLK_BUFG_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I1": { + "src_wire": "CLK_BUFG_IMUX27_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I0": { + "src_wire": "CLK_BUFG_IMUX24_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_0->>CLK_BUFG_R_BUFGCTRL2_S0": { + "src_wire": "CLK_BUFG_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_R_FBG_OUT7": { + "src_wire": "CLK_BUFG_BUFGCTRL7_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_3->>CLK_BUFG_R_BUFGCTRL15_S1": { + "src_wire": "CLK_BUFG_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0->>CLK_BUFG_BUFGCTRL12_O": { + "src_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL12_O", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED11->>CLK_BUFG_BUFGCTRL5_I1": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED11", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_0->>CLK_BUFG_R_BUFGCTRL3_CE0": { + "src_wire": "CLK_BUFG_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_3->>CLK_BUFG_R_BUFGCTRL12_CE1": { + "src_wire": "CLK_BUFG_IMUX16_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_CK_GCLK31": { + "src_wire": "CLK_BUFG_BUFGCTRL15_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_1->>CLK_BUFG_R_BUFGCTRL5_CE0": { + "src_wire": "CLK_BUFG_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I0": { + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_2->>CLK_BUFG_R_BUFGCTRL9_CE1": { + "src_wire": "CLK_BUFG_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_R_FBG_OUT15": { + "src_wire": "CLK_BUFG_BUFGCTRL15_O", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I0": { + "src_wire": "CLK_BUFG_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I1": { + "src_wire": "CLK_BUFG_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_3->>CLK_BUFG_R_BUFGCTRL13_CE0": { + "src_wire": "CLK_BUFG_IMUX21_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE1": { + "src_wire": "CLK_BUFG_IMUX10_3", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED22->>CLK_BUFG_BUFGCTRL11_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED22", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED28->>CLK_BUFG_BUFGCTRL14_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED28", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED8->>CLK_BUFG_BUFGCTRL4_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED8", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_0->>CLK_BUFG_R_BUFGCTRL2_S1": { + "src_wire": "CLK_BUFG_IMUX2_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_0->>CLK_BUFG_R_BUFGCTRL0_CE1": { + "src_wire": "CLK_BUFG_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I1": { + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED0->>CLK_BUFG_BUFGCTRL0_I0": { + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I0": { + "src_wire": "CLK_BUFG_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CLK_FEED.json b/kintex7/tile_type_CLK_FEED.json new file mode 100644 index 0000000..1e6d53f --- /dev/null +++ b/kintex7/tile_type_CLK_FEED.json @@ -0,0 +1,261 @@ +{ + "tile_type": "CLK_FEED", + "sites": [], + "wires": [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_SW4A1", + "CLK_FEED_CK_GCLK31", + "CLK_FEED_CK_BUFG_CASC9", + "CLK_FEED_EL1BEG1", + "CLK_FEED_WW2END2", + "CLK_FEED_EE2BEG3", + "CLK_FEED_CK_BUFG_CASC16", + "CLK_FEED_CK_GCLK16", + "CLK_FEED_SE4BEG3", + "CLK_FEED_LH1", + "CLK_FEED_EE4C2", + "CLK_FEED_NW4END2", + "CLK_FEED_CK_GCLK17", + "CLK_FEED_CK_GCLK5", + "CLK_FEED_NE4BEG3", + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_EE4A2", + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_CK_GCLK21", + "CLK_FEED_EE2A2", + "CLK_FEED_EE4B3", + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_EE4B0", + "CLK_FEED_EE4A3", + "CLK_FEED_CK_GCLK8", + "CLK_FEED_NW4END0", + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_CK_BUFG_CASC21", + "CLK_FEED_WW4B0", + "CLK_FEED_CK_BUFG_CASC2", + "CLK_FEED_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_ER1BEG1", + "CLK_FEED_SE4BEG0", + "CLK_FEED_CK_BUFG_CASC26", + "CLK_FEED_WW4A0", + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_WW4B2", + "CLK_FEED_SW2A1", + "CLK_FEED_LH3", + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_WW4END2", + "CLK_FEED_SE2A2", + "CLK_FEED_CK_BUFG_CASC1", + "CLK_FEED_EL1BEG3", + "CLK_FEED_NW4END1", + "CLK_FEED_LH8", + "CLK_FEED_LH4", + "CLK_FEED_CK_GCLK29", + "CLK_FEED_CK_GCLK14", + "CLK_FEED_SE4C0", + "CLK_FEED_LH9", + "CLK_FEED_WR1END3", + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_EE4BEG2", + "CLK_FEED_CK_GCLK19", + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_CK_GCLK25", + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_WW4END1", + "CLK_FEED_CK_GCLK23", + "CLK_FEED_EE4B1", + "CLK_FEED_CK_BUFG_CASC10", + "CLK_FEED_EE2BEG1", + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_SW4A3", + "CLK_FEED_SE4C1", + "CLK_FEED_NW4A2", + "CLK_FEED_CK_GCLK15", + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_CK_GCLK20", + "CLK_FEED_CK_BUFG_CASC5", + "CLK_FEED_LH11", + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_NE2A1", + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_CK_GCLK2", + "CLK_FEED_CK_GCLK11", + "CLK_FEED_CK_BUFG_CASC13", + "CLK_FEED_CK_BUFG_CASC18", + "CLK_FEED_CK_BUFG_CASC11", + "CLK_FEED_CK_GCLK3", + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_CK_BUFG_CASC23", + "CLK_FEED_CK_BUFG_CASC28", + "CLK_FEED_MONITOR_P", + "CLK_FEED_WW4A3", + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_CK_GCLK27", + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_NE4C1", + "CLK_FEED_CK_BUFG_CASC25", + "CLK_FEED_CK_BUFG_CASC6", + "CLK_FEED_CK_GCLK1", + "CLK_FEED_NE2A3", + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_ER1BEG3", + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_CK_BUFG_CASC8", + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_CK_GCLK22", + "CLK_FEED_WL1END1", + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_EE2BEG2", + "CLK_FEED_EE4C3", + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_CK_BUFG_CASC3", + "CLK_FEED_SE4C2", + "CLK_FEED_WL1END0", + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_CK_BUFG_CASC17", + "CLK_FEED_EE4BEG0", + "CLK_FEED_CK_BUFG_CASC22", + "CLK_FEED_WW4C2", + "CLK_FEED_EE2A1", + "CLK_FEED_EE4A0", + "CLK_FEED_WR1END0", + "CLK_FEED_CK_GCLK6", + "CLK_FEED_WR1END1", + "CLK_FEED_NE4BEG1", + "CLK_FEED_CK_BUFG_CASC0", + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_WL1END3", + "CLK_FEED_CK_GCLK10", + "CLK_FEED_CK_GCLK0", + "CLK_FEED_CK_GCLK30", + "CLK_FEED_EE4C0", + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_SE4BEG2", + "CLK_FEED_EE2A3", + "CLK_FEED_WW4B3", + "CLK_FEED_CK_BUFG_CASC7", + "CLK_FEED_EE4BEG1", + "CLK_FEED_EE4A1", + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_NE4C3", + "CLK_FEED_NW2A2", + "CLK_FEED_ER1BEG2", + "CLK_FEED_SW4END2", + "CLK_FEED_WW2A3", + "CLK_FEED_LH12", + "CLK_FEED_SW2A3", + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_SW4A2", + "CLK_FEED_SW4END3", + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_NE4BEG2", + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_EL1BEG2", + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_WW4C3", + "CLK_FEED_WL1END2", + "CLK_FEED_CK_GCLK26", + "CLK_FEED_WW2END1", + "CLK_FEED_SW2A2", + "CLK_FEED_ER1BEG0", + "CLK_FEED_WR1END2", + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_SE2A0", + "CLK_FEED_SW4A0", + "CLK_FEED_CK_BUFG_CASC31", + "CLK_FEED_NW4A3", + "CLK_FEED_WW2A1", + "CLK_FEED_CK_BUFG_CASC19", + "CLK_FEED_CK_BUFG_CASC27", + "CLK_FEED_CK_GCLK18", + "CLK_FEED_CK_GCLK4", + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_NE4C0", + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_SW2A0", + "CLK_FEED_CK_GCLK7", + "CLK_FEED_NE2A0", + "CLK_FEED_CK_BUFG_CASC24", + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_EE2A0", + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_SE4BEG1", + "CLK_FEED_WW2A2", + "CLK_FEED_CK_GCLK12", + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_CK_BUFG_CASC14", + "CLK_FEED_MONITOR_N", + "CLK_FEED_NE2A2", + "CLK_FEED_CK_GCLK9", + "CLK_FEED_SW4END1", + "CLK_FEED_EE4B2", + "CLK_FEED_EE4BEG3", + "CLK_FEED_WW2END3", + "CLK_FEED_NE4BEG0", + "CLK_FEED_WW4END0", + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_CK_BUFG_CASC12", + "CLK_FEED_LH7", + "CLK_FEED_CK_GCLK28", + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_NW4END3", + "CLK_FEED_NW2A3", + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_EE4C1", + "CLK_FEED_WW4END3", + "CLK_FEED_CK_GCLK13", + "CLK_FEED_NW2A1", + "CLK_FEED_CK_GCLK24", + "CLK_FEED_EL1BEG0", + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_WW4A2", + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_NW4A0", + "CLK_FEED_LH10", + "CLK_FEED_NW4A1", + "CLK_FEED_LH5", + "CLK_FEED_SE4C3", + "CLK_FEED_CK_BUFG_CASC4", + "CLK_FEED_NW2A0", + "CLK_FEED_WW4C0", + "CLK_FEED_LH6", + "CLK_FEED_SW4END0", + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_WW4B1", + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_WW2A0", + "CLK_FEED_CK_BUFG_CASC29", + "CLK_FEED_WW4A1", + "CLK_FEED_LH2", + "CLK_FEED_WW4C1", + "CLK_FEED_WW2END0", + "CLK_FEED_SE2A3", + "CLK_FEED_SE2A1", + "CLK_FEED_NE4C2", + "CLK_FEED_EE2BEG0" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_CLK_HROW_BOT_R.json b/kintex7/tile_type_CLK_HROW_BOT_R.json new file mode 100644 index 0000000..24e6f6a --- /dev/null +++ b/kintex7/tile_type_CLK_HROW_BOT_R.json @@ -0,0 +1,22381 @@ +{ + "tile_type": "CLK_HROW_BOT_R", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L0", + "O": "CLK_HROW_CK_HCLK_OUT_L0", + "I": "CLK_HROW_CK_MUX_OUT_L0" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L1", + "O": "CLK_HROW_CK_HCLK_OUT_L1", + "I": "CLK_HROW_CK_MUX_OUT_L1" + }, + "x_coord": 0 + }, + { + "y_coord": 2, + "name": "X0Y2", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L2", + "O": "CLK_HROW_CK_HCLK_OUT_L2", + "I": "CLK_HROW_CK_MUX_OUT_L2" + }, + "x_coord": 0 + }, + { + "y_coord": 3, + "name": "X0Y3", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L3", + "O": "CLK_HROW_CK_HCLK_OUT_L3", + "I": "CLK_HROW_CK_MUX_OUT_L3" + }, + "x_coord": 0 + }, + { + "y_coord": 4, + "name": "X0Y4", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L4", + "O": "CLK_HROW_CK_HCLK_OUT_L4", + "I": "CLK_HROW_CK_MUX_OUT_L4" + }, + "x_coord": 0 + }, + { + "y_coord": 5, + "name": "X0Y5", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L5", + "O": "CLK_HROW_CK_HCLK_OUT_L5", + "I": "CLK_HROW_CK_MUX_OUT_L5" + }, + "x_coord": 0 + }, + { + "y_coord": 6, + "name": "X0Y6", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L6", + "O": "CLK_HROW_CK_HCLK_OUT_L6", + "I": "CLK_HROW_CK_MUX_OUT_L6" + }, + "x_coord": 0 + }, + { + "y_coord": 7, + "name": "X0Y7", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L7", + "O": "CLK_HROW_CK_HCLK_OUT_L7", + "I": "CLK_HROW_CK_MUX_OUT_L7" + }, + "x_coord": 0 + }, + { + "y_coord": 8, + "name": "X0Y8", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L8", + "O": "CLK_HROW_CK_HCLK_OUT_L8", + "I": "CLK_HROW_CK_MUX_OUT_L8" + }, + "x_coord": 0 + }, + { + "y_coord": 9, + "name": "X0Y9", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L9", + "O": "CLK_HROW_CK_HCLK_OUT_L9", + "I": "CLK_HROW_CK_MUX_OUT_L9" + }, + "x_coord": 0 + }, + { + "y_coord": 10, + "name": "X0Y10", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L10", + "O": "CLK_HROW_CK_HCLK_OUT_L10", + "I": "CLK_HROW_CK_MUX_OUT_L10" + }, + "x_coord": 0 + }, + { + "y_coord": 11, + "name": "X0Y11", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L11", + "O": "CLK_HROW_CK_HCLK_OUT_L11", + "I": "CLK_HROW_CK_MUX_OUT_L11" + }, + "x_coord": 0 + }, + { + "y_coord": 11, + "name": "X1Y11", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R11", + "O": "CLK_HROW_CK_HCLK_OUT_R11", + "I": "CLK_HROW_CK_MUX_OUT_R11" + }, + "x_coord": 1 + }, + { + "y_coord": 10, + "name": "X1Y10", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R10", + "O": "CLK_HROW_CK_HCLK_OUT_R10", + "I": "CLK_HROW_CK_MUX_OUT_R10" + }, + "x_coord": 1 + }, + { + "y_coord": 9, + "name": "X1Y9", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R9", + "O": "CLK_HROW_CK_HCLK_OUT_R9", + "I": "CLK_HROW_CK_MUX_OUT_R9" + }, + "x_coord": 1 + }, + { + "y_coord": 8, + "name": "X1Y8", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R8", + "O": "CLK_HROW_CK_HCLK_OUT_R8", + "I": "CLK_HROW_CK_MUX_OUT_R8" + }, + "x_coord": 1 + }, + { + "y_coord": 7, + "name": "X1Y7", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R7", + "O": "CLK_HROW_CK_HCLK_OUT_R7", + "I": "CLK_HROW_CK_MUX_OUT_R7" + }, + "x_coord": 1 + }, + { + "y_coord": 6, + "name": "X1Y6", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R6", + "O": "CLK_HROW_CK_HCLK_OUT_R6", + "I": "CLK_HROW_CK_MUX_OUT_R6" + }, + "x_coord": 1 + }, + { + "y_coord": 5, + "name": "X1Y5", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R5", + "O": "CLK_HROW_CK_HCLK_OUT_R5", + "I": "CLK_HROW_CK_MUX_OUT_R5" + }, + "x_coord": 1 + }, + { + "y_coord": 4, + "name": "X1Y4", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R4", + "O": "CLK_HROW_CK_HCLK_OUT_R4", + "I": "CLK_HROW_CK_MUX_OUT_R4" + }, + "x_coord": 1 + }, + { + "y_coord": 3, + "name": "X1Y3", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R3", + "O": "CLK_HROW_CK_HCLK_OUT_R3", + "I": "CLK_HROW_CK_MUX_OUT_R3" + }, + "x_coord": 1 + }, + { + "y_coord": 2, + "name": "X1Y2", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R2", + "O": "CLK_HROW_CK_HCLK_OUT_R2", + "I": "CLK_HROW_CK_MUX_OUT_R2" + }, + "x_coord": 1 + }, + { + "y_coord": 1, + "name": "X1Y1", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R1", + "O": "CLK_HROW_CK_HCLK_OUT_R1", + "I": "CLK_HROW_CK_MUX_OUT_R1" + }, + "x_coord": 1 + }, + { + "y_coord": 0, + "name": "X1Y0", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R0", + "O": "CLK_HROW_CK_HCLK_OUT_R0", + "I": "CLK_HROW_CK_MUX_OUT_R0" + }, + "x_coord": 1 + } + ], + "wires": [ + "CLK_HROW_SE4C3_2", + "CLK_HROW_CK_MUX_OUT_R3", + "CLK_HROW_LOGIC_OUTS_B20_5", + "CLK_HROW_CK_IN_R5", + "CLK_HROW_FAN0_3", + "CLK_HROW_NW4END1_7", + "CLK_HROW_EL1BEG3_6", + "CLK_HROW_CK_GCLK_TEST_IN29", + "CLK_HROW_LH4_4", + "CLK_HROW_CK_GCLK_TEST_OUT0", + "CLK_HROW_WW2A3_6", + "CLK_HROW_WW4END3_5", + "CLK_HROW_BYP4_2", + "CLK_HROW_EE4A0_4", + "CLK_HROW_MONITOR_N_2", + "CLK_HROW_LH3_4", + "CLK_HROW_CK_IN_R_TEST_OUT", + "CLK_HROW_CK_GCLK_TEST_IN11", + "CLK_HROW_CK_GCLK_TEST10", + "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "CLK_HROW_LH9_1", + "CLK_HROW_NW2A1_0", + "CLK_HROW_WW2A3_1", + "CLK_HROW_CK_IN_L_TEST_IN", + "CLK_HROW_NW4END1_1", + "CLK_HROW_WR1END3_1", + "CLK_HROW_R_CK_GCLK16", + "CLK_HROW_CK_IN_R_IN_TEST", + "CLK_HROW_CK_GCLK_IN_TEST14", + "CLK_HROW_CE_INT_TOP5", + "CLK_HROW_CK_GCLK_TEST_OUT18", + "CLK_HROW_SE4BEG2_0", + "CLK_HROW_CK_GCLK_TEST_OUT7", + "CLK_HROW_CK_GCLK_OUT_TEST26", + "CLK_HROW_WW2A1_0", + "CLK_HROW_BLOCK_OUTS_B2_7", + "CLK_HROW_SE4BEG1_1", + "CLK_HROW_WW4C3_3", + "CLK_HROW_EE4BEG0_7", + "CLK_HROW_WW2A2_7", + "CLK_HROW_LOGIC_OUTS_B2_3", + "CLK_HROW_WW4END2_7", + "CLK_HROW_IMUX25_3", + "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "CLK_HROW_ER1BEG0_7", + "CLK_HROW_NE4C2_2", + "CLK_HROW_IMUX42_0", + "CLK_HROW_BLOCK_OUTS_B0_2", + "CLK_HROW_IMUX43_5", + "CLK_HROW_IMUX46_2", + "CLK_HROW_WL1END2_1", + "CLK_HROW_NE4C2_0", + "CLK_HROW_LH5_3", + "CLK_HROW_NE2A1_0", + "CLK_HROW_SW4END1_3", + "CLK_HROW_NW4A1_0", + "CLK_HROW_EE4B0_5", + "CLK_HROW_LH6_7", + "CLK_HROW_IMUX30_6", + "CLK_HROW_LH2_4", + "CLK_HROW_SW2A3_3", + "CLK_HROW_IMUX36_6", + "CLK_HROW_CK_INT_1_0", + "CLK_HROW_LOGIC_OUTS_B3_5", + "CLK_HROW_LOGIC_OUTS_B11_4", + "CLK_HROW_CK_GCLK_TEST_IN5", + "CLK_HROW_CK_GCLK_OUT_TEST8", + "CLK_HROW_SW4END1_4", + "CLK_HROW_LH5_0", + "CLK_HROW_LOGIC_OUTS_B22_7", + "CLK_HROW_CK_IN_R11", + "CLK_HROW_NE4BEG2_7", + "CLK_HROW_CK_BUFRCLK_R3", + "CLK_HROW_IMUX37_1", + "CLK_HROW_WL1END0_5", + "CLK_HROW_SE4C2_1", + "CLK_HROW_CE_INT_TOP11", + "CLK_HROW_CK_GCLK_IN_TEST29", + "CLK_HROW_BLOCK_OUTS_B1_4", + "CLK_HROW_IMUX21_7", + "CLK_HROW_MONITOR_N_7", + "CLK_HROW_LOGIC_OUTS_B2_6", + "CLK_HROW_CK_GCLK_IN_TEST9", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN15", + "CLK_HROW_WW2A3_2", + "CLK_HROW_NE4BEG1_1", + "CLK_HROW_LH10_3", + "CLK_HROW_IMUX32_1", + "CLK_HROW_LOGIC_OUTS_B17_6", + "CLK_HROW_IMUX18_4", + "CLK_HROW_CE_INT_BOT8", + "CLK_HROW_SW4END1_7", + "CLK_HROW_NW4END1_2", + "CLK_HROW_WW2END0_0", + "CLK_HROW_WW2END1_6", + "CLK_HROW_LOGIC_OUTS_B4_1", + "CLK_HROW_CK_IN_L_OUT_TEST", + "CLK_HROW_CK_GCLK_TEST_IN7", + "CLK_HROW_SE4C0_5", + "CLK_HROW_ER1BEG2_2", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN8", + "CLK_HROW_WR1END1_4", + "CLK_HROW_NW4A1_3", + "CLK_HROW_FAN5_6", + "CLK_HROW_CK_BUFHCLK_R8", + "CLK_HROW_IMUX16_5", + "CLK_HROW_CK_GCLK_OUT_TEST5", + "CLK_HROW_WR1END2_4", + "CLK_HROW_CK_GCLK_TEST_OUT3", + "CLK_HROW_CK_MUX_OUT_L1", + "CLK_HROW_FAN2_1", + "CLK_HROW_IMUX31_4", + "CLK_HROW_LOGIC_OUTS_B12_4", + "CLK_HROW_WW4C0_6", + "CLK_HROW_NW2A3_0", + "CLK_HROW_LOGIC_OUTS_B12_7", + "CLK_HROW_LOGIC_OUTS_B10_6", + "CLK_HROW_ER1BEG2_5", + "CLK_HROW_SE4C3_3", + "CLK_HROW_SE4C2_6", + "CLK_HROW_CK_GCLK_TEST_OUT14", + "CLK_HROW_SE4C0_0", + "CLK_HROW_LOGIC_OUTS_B12_3", + "CLK_HROW_IMUX8_3", + "CLK_HROW_SW2A1_7", + "CLK_HROW_WR1END3_6", + "CLK_HROW_SE4BEG2_1", + "CLK_HROW_EE2A3_3", + "CLK_HROW_SE2A3_2", + "CLK_HROW_IMUX22_1", + "CLK_HROW_CE_INT_BOT0", + "CLK_HROW_IMUX38_2", + "CLK_HROW_NW4A0_6", + "CLK_HROW_EL1BEG3_3", + "CLK_HROW_LH8_7", + "CLK_HROW_LH10_5", + "CLK_HROW_LOGIC_OUTS_B5_1", + "CLK_HROW_SE2A2_0", + "CLK_HROW_WW4END3_0", + "CLK_HROW_CK_IN_R1", + "CLK_HROW_SE2A0_4", + "CLK_HROW_CK_GCLK_TEST9", + "CLK_HROW_LH9_2", + "CLK_HROW_CK_GCLK_TEST_OUT21", + "CLK_HROW_CK_MUX_OUT_L11", + "CLK_HROW_CE_INT_BOT1", + "CLK_HROW_LOGIC_OUTS_B21_3", + "CLK_HROW_CK_HCLK_OUT_L9", + "CLK_HROW_BYP1_3", + "CLK_HROW_SW2A1_6", + "CLK_HROW_LOGIC_OUTS_B6_0", + "CLK_HROW_CK_GCLK_OUT_TEST0", + "CLK_HROW_SW4END3_0", + "CLK_HROW_NE2A0_3", + "CLK_HROW_CE_INT_BOT7", + "CLK_HROW_NE4C1_4", + "CLK_HROW_LOGIC_OUTS_B9_2", + "CLK_HROW_WW4C2_0", + "CLK_HROW_CK_HCLK_OUT_L2", + "CLK_HROW_LOGIC_OUTS_B7_7", + "CLK_HROW_SW2A2_7", + "CLK_HROW_CK_GCLK_TEST24", + "CLK_HROW_CK_IN_L_IN_TEST", + "CLK_HROW_IMUX37_3", + "CLK_HROW_CE_INT_TOP3", + "CLK_HROW_LOGIC_OUTS_B17_0", + "CLK_HROW_CK_GCLK_TEST_IN12", + "CLK_HROW_IMUX2_0", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN7", + "CLK_HROW_EE4A0_5", + "CLK_HROW_NW4END0_2", + "CLK_HROW_IMUX15_0", + "CLK_HROW_CK_GCLK_TEST_IN4", + "CLK_HROW_EE2BEG1_7", + "CLK_HROW_BUFHCE_CE_L3", + "CLK_HROW_WW4C0_7", + "CLK_HROW_NE2A2_3", + "CLK_HROW_SW4A3_4", + "CLK_HROW_EL1BEG0_2", + "CLK_HROW_SE4C2_4", + "CLK_HROW_ER1BEG0_4", + "CLK_HROW_IMUX15_4", + "CLK_HROW_EE4B2_6", + "CLK_HROW_SW4A2_6", + "CLK_HROW_SW4A1_4", + "CLK_HROW_WL1END0_4", + "CLK_HROW_IMUX46_1", + "CLK_HROW_FAN7_1", + "CLK_HROW_SW4A3_5", + "CLK_HROW_EE4BEG2_0", + "CLK_HROW_EE2A3_1", + "CLK_HROW_LOGIC_OUTS_B13_2", + "CLK_HROW_BUFHCE_CE_L0", + "CLK_HROW_IMUX16_3", + "CLK_HROW_IMUX27_0", + "CLK_HROW_IMUX20_6", + "CLK_HROW_SW2A1_1", + "CLK_HROW_IMUX23_0", + "CLK_HROW_R_CK_GCLK20", + "CLK_HROW_BYP1_1", + "CLK_HROW_WW4C1_2", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN27", + "CLK_HROW_SW2A2_5", + "CLK_HROW_BYP0_3", + "CLK_HROW_CK_GCLK_TEST_IN6", + "CLK_HROW_CK_GCLK_TEST11", + "CLK_HROW_CK_GCLK_OUT_TEST2", + "CLK_HROW_R_CK_GCLK24", + "CLK_HROW_IMUX3_0", + "CLK_HROW_CK_IN_L11", + "CLK_HROW_IMUX28_3", + "CLK_HROW_IMUX27_4", + "CLK_HROW_IMUX15_5", + "CLK_HROW_SW4END1_2", + "CLK_HROW_BUFHCE_CE_L9", + "CLK_HROW_CE_INT_BOT10", + "CLK_HROW_EE4B3_7", + "CLK_HROW_EE2BEG3_2", + "CLK_HROW_IMUX4_7", + "CLK_HROW_IMUX38_3", + "CLK_HROW_WW2END2_5", + "CLK_HROW_WW2A0_2", + "CLK_HROW_CK_GCLK_TEST_OUT4", + "CLK_HROW_SW4END1_1", + "CLK_HROW_CK_IN_R2", + "CLK_HROW_FAN1_7", + "CLK_HROW_WW4C1_1", + "CLK_HROW_CK_GCLK_OUT_TEST15", + "CLK_HROW_IMUX43_3", + "CLK_HROW_EE4BEG3_6", + "CLK_HROW_CK_GCLK_IN_TEST16", + "CLK_HROW_LOGIC_OUTS_B18_4", + "CLK_HROW_SW4END3_2", + "CLK_HROW_EE4A2_7", + "CLK_HROW_CK_GCLK_TEST_IN25", + "CLK_HROW_LOGIC_OUTS_B18_3", + "CLK_HROW_SE2A1_2", + "CLK_HROW_LH9_3", + "CLK_HROW_EE2BEG1_2", + "CLK_HROW_IMUX8_7", + "CLK_HROW_NW2A3_4", + "CLK_HROW_LOGIC_OUTS_B11_6", + "CLK_HROW_CK_GCLK_TEST0", + "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "CLK_HROW_EE4BEG0_3", + "CLK_HROW_EE4B1_7", + "CLK_HROW_WW4B1_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "CLK_HROW_WW2A0_7", + "CLK_HROW_WW4C0_1", + "CLK_HROW_EE4B2_1", + "CLK_HROW_CK_BUFHCLK_L5", + "CLK_HROW_NE4BEG2_0", + "CLK_HROW_LOGIC_OUTS_B2_1", + "CLK_HROW_CE_INT_BOT4", + "CLK_HROW_EE4BEG0_4", + "CLK_HROW_FAN6_3", + "CLK_HROW_R_CK_GCLK23", + "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "CLK_HROW_LOGIC_OUTS_B1_7", + "CLK_HROW_EE4A2_4", + "CLK_HROW_NE4BEG2_5", + "CLK_HROW_LOGIC_OUTS_B3_6", + "CLK_HROW_LOGIC_OUTS_B15_2", + "CLK_HROW_IMUX10_2", + "CLK_HROW_CK_HCLK_OUT_R11", + "CLK_HROW_FAN6_1", + "CLK_HROW_LOGIC_OUTS_B15_4", + "CLK_HROW_IMUX4_0", + "CLK_HROW_R_CK_GCLK26", + "CLK_HROW_WW4C3_7", + "CLK_HROW_LOGIC_OUTS_B17_1", + "CLK_HROW_IMUX10_3", + "CLK_HROW_CK_GCLK_TEST30", + "CLK_HROW_SW4A1_6", + "CLK_HROW_IMUX6_0", + "CLK_HROW_EL1BEG1_1", + "CLK_HROW_LH2_3", + "CLK_HROW_WW4B3_0", + "CLK_HROW_LOGIC_OUTS_B8_2", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN6", + "CLK_HROW_IMUX27_3", + "CLK_HROW_EE2BEG2_7", + "CLK_HROW_IMUX12_5", + "CLK_HROW_BLOCK_OUTS_B1_7", + "CLK_HROW_CE_INT_BOT6", + "CLK_HROW_WW4END1_3", + "CLK_HROW_IMUX7_4", + "CLK_HROW_EE2BEG1_0", + "CLK_HROW_LOGIC_OUTS_B9_3", + "CLK_HROW_WL1END3_7", + "CLK_HROW_NW4END0_0", + "CLK_HROW_SE2A2_1", + "CLK_HROW_EE2BEG3_7", + "CLK_HROW_LH6_5", + "CLK_HROW_EE4BEG2_5", + "CLK_HROW_IMUX13_1", + "CLK_HROW_SE4BEG3_4", + "CLK_HROW_ER1BEG1_5", + "CLK_HROW_LH8_1", + "CLK_HROW_SE4C3_6", + "CLK_HROW_IMUX34_2", + "CLK_HROW_IMUX21_3", + "CLK_HROW_LOGIC_OUTS_B15_1", + "CLK_HROW_LOGIC_OUTS_B8_1", + "CLK_HROW_NW4A2_1", + "CLK_HROW_ER1BEG0_1", + "CLK_HROW_SE2A3_5", + "CLK_HROW_EE2BEG3_3", + "CLK_HROW_NW4END3_6", + "CLK_HROW_WW2A1_6", + "CLK_HROW_IMUX37_7", + "CLK_HROW_EE2A0_2", + "CLK_HROW_WW2A1_3", + "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "CLK_HROW_CK_IN_R10", + "CLK_HROW_NE4BEG3_6", + "CLK_HROW_SW4A2_7", + "CLK_HROW_CK_IN_R6", + "CLK_HROW_IMUX18_3", + "CLK_HROW_IMUX38_7", + "CLK_HROW_BUFHCE_CE_R8", + "CLK_HROW_LH2_0", + "CLK_HROW_IMUX47_4", + "CLK_HROW_WR1END2_6", + "CLK_HROW_SW4A0_4", + "CLK_HROW_NW2A1_4", + "CLK_HROW_LOGIC_OUTS_B7_5", + "CLK_HROW_LOGIC_OUTS_B0_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "CLK_HROW_WL1END1_5", + "CLK_HROW_IMUX7_0", + "CLK_HROW_NE4C3_7", + "CLK_HROW_EE2A0_5", + "CLK_HROW_NW4END3_3", + "CLK_HROW_CK_BUFHCLK_R11", + "CLK_HROW_LOGIC_OUTS_B14_3", + "CLK_HROW_ER1BEG0_6", + "CLK_HROW_WW4B1_6", + "CLK_HROW_IMUX36_1", + "CLK_HROW_NE2A2_4", + "CLK_HROW_BYP6_5", + "CLK_HROW_CK_GCLK_TEST_OUT27", + "CLK_HROW_WW2END3_0", + "CLK_HROW_SW2A1_5", + "CLK_HROW_SW4END2_0", + "CLK_HROW_LOGIC_OUTS_B9_7", + "CLK_HROW_IMUX43_7", + "CLK_HROW_EE4B0_0", + "CLK_HROW_NW4A2_4", + "CLK_HROW_FAN5_2", + "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "CLK_HROW_NE2A1_7", + "CLK_HROW_CE_INT_BOT11", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN23", + "CLK_HROW_SE2A0_5", + "CLK_HROW_WR1END1_6", + "CLK_HROW_EE4C3_0", + "CLK_HROW_ER1BEG1_0", + "CLK_HROW_LH5_5", + "CLK_HROW_IMUX11_7", + "CLK_HROW_NW2A2_6", + "CLK_HROW_SE4C1_0", + "CLK_HROW_NW4A2_5", + "CLK_HROW_WR1END0_4", + "CLK_HROW_CK_GCLK_TEST_IN0", + "CLK_HROW_CK_IN_L8", + "CLK_HROW_SW4A1_0", + "CLK_HROW_WW4END1_7", + "CLK_HROW_IMUX14_5", + "CLK_HROW_CK_GCLK_TEST4", + "CLK_HROW_CK_BUFHCLK_L3", + "CLK_HROW_MONITOR_N_5", + "CLK_HROW_IMUX40_1", + "CLK_HROW_LOGIC_OUTS_B10_4", + "CLK_HROW_LOGIC_OUTS_B15_5", + "CLK_HROW_SW2A0_2", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN30", + "CLK_HROW_CE_INT_TOP7", + "CLK_HROW_NE4C3_1", + "CLK_HROW_EE2A3_6", + "CLK_HROW_NW2A2_1", + "CLK_HROW_IMUX27_2", + "CLK_HROW_CLK0_6", + "CLK_HROW_IMUX13_4", + "CLK_HROW_LOGIC_OUTS_B3_4", + "CLK_HROW_WW4A1_0", + "CLK_HROW_WW2END3_4", + "CLK_HROW_NW2A1_2", + "CLK_HROW_LH11_3", + "CLK_HROW_IMUX34_5", + "CLK_HROW_LOGIC_OUTS_B22_2", + "CLK_HROW_EE4A3_1", + "CLK_HROW_EL1BEG1_3", + "CLK_HROW_CK_GCLK_IN_TEST13", + "CLK_HROW_CK_GCLK_OUT_TEST7", + "CLK_HROW_BYP7_7", + "CLK_HROW_FAN3_4", + "CLK_HROW_IMUX18_0", + "CLK_HROW_SW2A0_1", + "CLK_HROW_CK_GCLK_TEST_OUT23", + "CLK_HROW_WW4A3_2", + "CLK_HROW_IMUX20_1", + "CLK_HROW_CLK0_4", + "CLK_HROW_WW2A1_5", + "CLK_HROW_EE4B2_0", + "CLK_HROW_IMUX13_2", + "CLK_HROW_CK_IN_R3", + "CLK_HROW_WW2END2_2", + "CLK_HROW_NE4C1_7", + "CLK_HROW_EE4B2_4", + "CLK_HROW_IMUX4_1", + "CLK_HROW_WW4END0_6", + "CLK_HROW_BLOCK_OUTS_B0_7", + "CLK_HROW_NW4END2_1", + "CLK_HROW_BYP6_7", + "CLK_HROW_NW2A1_6", + "CLK_HROW_NW4END0_7", + "CLK_HROW_IMUX32_6", + "CLK_HROW_BYP7_4", + "CLK_HROW_WW4B3_3", + "CLK_HROW_NE4BEG2_3", + "CLK_HROW_EE4C0_0", + "CLK_HROW_EE2BEG0_2", + "CLK_HROW_FAN1_3", + "CLK_HROW_LH1_2", + "CLK_HROW_CK_BUFHCLK_R5", + "CLK_HROW_CK_BUFRCLK_R2", + "CLK_HROW_SE4BEG3_0", + "CLK_HROW_SE2A3_3", + "CLK_HROW_SW4END3_4", + "CLK_HROW_WW4END1_0", + "CLK_HROW_CK_HCLK_OUT_R4", + "CLK_HROW_FAN3_0", + "CLK_HROW_ER1BEG2_7", + "CLK_HROW_IMUX5_1", + "CLK_HROW_IMUX38_1", + "CLK_HROW_IMUX33_3", + "CLK_HROW_CLK1_3", + "CLK_HROW_EE4C2_4", + "CLK_HROW_IMUX45_3", + "CLK_HROW_IMUX44_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "CLK_HROW_EE2BEG0_0", + "CLK_HROW_R_CK_GCLK13", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN0", + "CLK_HROW_WW4A3_0", + "CLK_HROW_BYP7_3", + "CLK_HROW_WW4C3_1", + "CLK_HROW_NE4BEG3_2", + "CLK_HROW_WW4END0_5", + "CLK_HROW_IMUX31_2", + "CLK_HROW_CK_HCLK_OUT_R7", + "CLK_HROW_WW2A2_3", + "CLK_HROW_FAN3_2", + "CLK_HROW_EE4B0_2", + "CLK_HROW_IMUX6_5", + "CLK_HROW_EE2A0_3", + "CLK_HROW_CK_GCLK_IN_TEST25", + "CLK_HROW_IMUX30_2", + "CLK_HROW_LOGIC_OUTS_B22_1", + "CLK_HROW_IMUX26_2", + "CLK_HROW_EE4A0_0", + "CLK_HROW_WW4END2_2", + "CLK_HROW_LH2_5", + "CLK_HROW_SE2A1_3", + "CLK_HROW_WW4C2_1", + "CLK_HROW_SE4C3_7", + "CLK_HROW_SW2A2_0", + "CLK_HROW_EE2BEG2_1", + "CLK_HROW_IMUX30_7", + "CLK_HROW_NW4A3_7", + "CLK_HROW_WW4B3_6", + "CLK_HROW_WW4B2_3", + "CLK_HROW_IMUX20_7", + "CLK_HROW_NW4A2_0", + "CLK_HROW_SE4BEG1_6", + "CLK_HROW_WL1END1_0", + "CLK_HROW_SE2A2_3", + "CLK_HROW_CK_GCLK_IN_TEST17", + "CLK_HROW_IMUX7_1", + "CLK_HROW_WW2A2_4", + "CLK_HROW_CK_HCLK_OUT_L1", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN22", + "CLK_HROW_WW4C3_0", + "CLK_HROW_IMUX10_5", + "CLK_HROW_CK_MUX_OUT_L5", + "CLK_HROW_BLOCK_OUTS_B0_1", + "CLK_HROW_EE4BEG2_2", + "CLK_HROW_FAN4_0", + "CLK_HROW_EE4A1_4", + "CLK_HROW_LOGIC_OUTS_B15_3", + "CLK_HROW_NW2A2_5", + "CLK_HROW_LH7_5", + "CLK_HROW_WW4A2_1", + "CLK_HROW_NW2A0_0", + "CLK_HROW_CK_GCLK_TEST_IN1", + "CLK_HROW_WW4B2_7", + "CLK_HROW_FAN5_7", + "CLK_HROW_NE4BEG1_2", + "CLK_HROW_BYP4_3", + "CLK_HROW_EL1BEG0_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "CLK_HROW_IMUX26_0", + "CLK_HROW_SE4BEG2_7", + "CLK_HROW_WW4END0_1", + "CLK_HROW_FAN4_4", + "CLK_HROW_EE2A2_6", + "CLK_HROW_WW2A2_6", + "CLK_HROW_IMUX16_7", + "CLK_HROW_IMUX44_2", + "CLK_HROW_EE4BEG1_3", + "CLK_HROW_WR1END3_3", + "CLK_HROW_SW4END1_0", + "CLK_HROW_BYP2_3", + "CLK_HROW_EE4A1_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "CLK_HROW_WW4END3_3", + "CLK_HROW_ER1BEG2_4", + "CLK_HROW_IMUX36_5", + "CLK_HROW_CK_GCLK_TEST_OUT9", + "CLK_HROW_BUFHCE_CE_L1", + "CLK_HROW_BYP0_0", + "CLK_HROW_IMUX39_7", + "CLK_HROW_LH3_3", + "CLK_HROW_IMUX3_7", + "CLK_HROW_EE2A1_6", + "CLK_HROW_NW2A0_1", + "CLK_HROW_NW4END3_7", + "CLK_HROW_BYP5_5", + "CLK_HROW_BYP0_4", + "CLK_HROW_CK_GCLK_TEST15", + "CLK_HROW_CK_GCLK_TEST_OUT25", + "CLK_HROW_CK_MUX_OUT_R1", + "CLK_HROW_WW4B3_7", + "CLK_HROW_LOGIC_OUTS_B9_0", + "CLK_HROW_WW4C0_0", + "CLK_HROW_WL1END0_2", + "CLK_HROW_WL1END2_7", + "CLK_HROW_NW4END3_5", + "CLK_HROW_SE4BEG1_5", + "CLK_HROW_SE4C0_1", + "CLK_HROW_WW4C0_4", + "CLK_HROW_IMUX32_2", + "CLK_HROW_LH8_0", + "CLK_HROW_WW4END0_4", + "CLK_HROW_SW4A2_4", + "CLK_HROW_IMUX46_4", + "CLK_HROW_NE2A1_2", + "CLK_HROW_NE4C3_4", + "CLK_HROW_WW4END0_3", + "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "CLK_HROW_BLOCK_OUTS_B0_5", + "CLK_HROW_IMUX9_7", + "CLK_HROW_WW2END2_4", + "CLK_HROW_IMUX35_6", + "CLK_HROW_SW2A0_5", + "CLK_HROW_LH12_7", + "CLK_HROW_R_CK_GCLK4", + "CLK_HROW_SE4BEG2_6", + "CLK_HROW_CK_GCLK_IN_TEST28", + "CLK_HROW_LH6_6", + "CLK_HROW_LOGIC_OUTS_B18_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN29", + "CLK_HROW_FAN3_7", + "CLK_HROW_WW2A0_0", + "CLK_HROW_SW2A0_0", + "CLK_HROW_WW2END2_6", + "CLK_HROW_IMUX30_0", + "CLK_HROW_SW4A2_1", + "CLK_HROW_R_CK_GCLK17", + "CLK_HROW_FAN0_1", + "CLK_HROW_CK_MUX_OUT_L0", + "CLK_HROW_WL1END2_3", + "CLK_HROW_WL1END1_1", + "CLK_HROW_IMUX2_5", + "CLK_HROW_CK_GCLK_OUT_TEST24", + "CLK_HROW_NW4END2_2", + "CLK_HROW_WW2A0_6", + "CLK_HROW_EE4A1_6", + "CLK_HROW_NE4C1_1", + "CLK_HROW_NE4BEG0_6", + "CLK_HROW_IMUX27_6", + "CLK_HROW_BUFHCE_CE_R4", + "CLK_HROW_CK_GCLK_TEST20", + "CLK_HROW_CK_GCLK_TEST_IN14", + "CLK_HROW_SW4END0_2", + "CLK_HROW_IMUX26_5", + "CLK_HROW_CK_GCLK_IN_TEST2", + "CLK_HROW_IMUX10_6", + "CLK_HROW_CK_MUX_OUT_L9", + "CLK_HROW_EL1BEG3_4", + "CLK_HROW_IMUX14_2", + "CLK_HROW_CTRL0_0", + "CLK_HROW_LOGIC_OUTS_B6_6", + "CLK_HROW_BUFHCE_CE_R11", + "CLK_HROW_NE4BEG2_6", + "CLK_HROW_LOGIC_OUTS_B0_2", + "CLK_HROW_CK_IN_L5", + "CLK_HROW_CK_IN_R13", + "CLK_HROW_NW4A0_0", + "CLK_HROW_WR1END0_5", + "CLK_HROW_IMUX41_2", + "CLK_HROW_BYP7_5", + "CLK_HROW_MONITOR_P_4", + "CLK_HROW_SE2A3_0", + "CLK_HROW_IMUX12_7", + "CLK_HROW_EE4BEG0_2", + "CLK_HROW_CK_HCLK_OUT_R0", + "CLK_HROW_EL1BEG2_5", + "CLK_HROW_NW4A1_5", + "CLK_HROW_IMUX41_3", + "CLK_HROW_IMUX25_4", + "CLK_HROW_IMUX12_3", + "CLK_HROW_IMUX29_0", + "CLK_HROW_WR1END2_0", + "CLK_HROW_WW4C1_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "CLK_HROW_LH10_0", + "CLK_HROW_IMUX1_2", + "CLK_HROW_WW4B0_3", + "CLK_HROW_BYP2_6", + "CLK_HROW_FAN7_0", + "CLK_HROW_IMUX44_5", + "CLK_HROW_IMUX40_4", + "CLK_HROW_R_CK_GCLK18", + "CLK_HROW_WW2END1_5", + "CLK_HROW_WW2END2_3", + "CLK_HROW_LOGIC_OUTS_B5_3", + "CLK_HROW_WW4A1_6", + "CLK_HROW_CLK0_3", + "CLK_HROW_IMUX42_4", + "CLK_HROW_WW4A0_4", + "CLK_HROW_IMUX43_1", + "CLK_HROW_WW2END2_7", + "CLK_HROW_EE4A3_5", + "CLK_HROW_WL1END3_3", + "CLK_HROW_WW2END0_3", + "CLK_HROW_CK_GCLK_TEST26", + "CLK_HROW_IMUX40_0", + "CLK_HROW_SE4BEG0_3", + "CLK_HROW_BLOCK_OUTS_B1_1", + "CLK_HROW_IMUX31_3", + "CLK_HROW_IMUX32_5", + "CLK_HROW_CK_HCLK_OUT_R10", + "CLK_HROW_LOGIC_OUTS_B11_1", + "CLK_HROW_BYP7_0", + "CLK_HROW_CK_BUFHCLK_R2", + "CLK_HROW_IMUX23_5", + "CLK_HROW_LOGIC_OUTS_B16_6", + "CLK_HROW_NE2A2_5", + "CLK_HROW_IMUX10_1", + "CLK_HROW_IMUX25_6", + "CLK_HROW_IMUX16_1", + "CLK_HROW_EE2BEG1_1", + "CLK_HROW_SE4C2_3", + "CLK_HROW_LOGIC_OUTS_B1_4", + "CLK_HROW_EE4BEG1_1", + "CLK_HROW_IMUX37_6", + "CLK_HROW_BYP5_1", + "CLK_HROW_BLOCK_OUTS_B2_3", + "CLK_HROW_WL1END1_4", + "CLK_HROW_CK_GCLK_TEST_IN16", + "CLK_HROW_NW2A3_2", + "CLK_HROW_IMUX19_2", + "CLK_HROW_LOGIC_OUTS_B22_5", + "CLK_HROW_EE4BEG3_5", + "CLK_HROW_SW4A2_3", + "CLK_HROW_BYP2_4", + "CLK_HROW_SW4END0_6", + "CLK_HROW_IMUX47_0", + "CLK_HROW_IMUX23_4", + "CLK_HROW_LH9_4", + "CLK_HROW_EL1BEG0_1", + "CLK_HROW_FAN2_3", + "CLK_HROW_FAN4_1", + "CLK_HROW_IMUX18_1", + "CLK_HROW_LH2_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN16", + "CLK_HROW_WW4C1_5", + "CLK_HROW_IMUX10_7", + "CLK_HROW_CK_IN_R_TEST_IN", + "CLK_HROW_NW4A0_7", + "CLK_HROW_IMUX41_4", + "CLK_HROW_LH1_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "CLK_HROW_IMUX1_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN28", + "CLK_HROW_LH8_2", + "CLK_HROW_EL1BEG1_0", + "CLK_HROW_CK_GCLK_IN_TEST22", + "CLK_HROW_LH1_0", + "CLK_HROW_LOGIC_OUTS_B11_2", + "CLK_HROW_REFCK_WESTCLK0", + "CLK_HROW_WW2A1_7", + "CLK_HROW_IMUX46_3", + "CLK_HROW_WW4END2_6", + "CLK_HROW_IMUX3_5", + "CLK_HROW_IMUX7_3", + "CLK_HROW_EL1BEG2_4", + "CLK_HROW_SW4A0_6", + "CLK_HROW_BUFHCE_CE_L7", + "CLK_HROW_NE4BEG1_5", + "CLK_HROW_BUFHCE_CE_L11", + "CLK_HROW_LH6_2", + "CLK_HROW_EE4B0_3", + "CLK_HROW_BYP3_0", + "CLK_HROW_LOGIC_OUTS_B14_0", + "CLK_HROW_EE4BEG1_7", + "CLK_HROW_IMUX27_1", + "CLK_HROW_CK_GCLK_IN_TEST10", + "CLK_HROW_LOGIC_OUTS_B5_0", + "CLK_HROW_CK_GCLK_TEST16", + "CLK_HROW_EE2A2_5", + "CLK_HROW_CK_IN_R_OUT_TEST", + "CLK_HROW_NW2A3_3", + "CLK_HROW_CK_BUFHCLK_L11", + "CLK_HROW_FAN6_6", + "CLK_HROW_CK_GCLK_TEST_OUT11", + "CLK_HROW_EE4B3_1", + "CLK_HROW_LH3_1", + "CLK_HROW_NE4C2_1", + "CLK_HROW_MONITOR_P_3", + "CLK_HROW_WW4C3_2", + "CLK_HROW_CK_GCLK_TEST_IN20", + "CLK_HROW_NW2A1_7", + "CLK_HROW_EE4A3_7", + "CLK_HROW_IMUX9_0", + "CLK_HROW_NW4A2_6", + "CLK_HROW_IMUX0_0", + "CLK_HROW_SE4C3_0", + "CLK_HROW_NE4BEG0_3", + "CLK_HROW_IMUX41_1", + "CLK_HROW_CK_GCLK_OUT_TEST10", + "CLK_HROW_LOGIC_OUTS_B0_5", + "CLK_HROW_IMUX17_7", + "CLK_HROW_WW2END3_6", + "CLK_HROW_WW2END3_1", + "CLK_HROW_WW4B2_2", + "CLK_HROW_WW2END1_3", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN25", + "CLK_HROW_LOGIC_OUTS_B1_1", + "CLK_HROW_EE4A1_1", + "CLK_HROW_IMUX29_4", + "CLK_HROW_LOGIC_OUTS_B12_5", + "CLK_HROW_BLOCK_OUTS_B0_6", + "CLK_HROW_EE4A3_3", + "CLK_HROW_WW2A3_5", + "CLK_HROW_NW2A2_7", + "CLK_HROW_CLK1_0", + "CLK_HROW_LOGIC_OUTS_B7_3", + "CLK_HROW_LOGIC_OUTS_B2_4", + "CLK_HROW_FAN0_0", + "CLK_HROW_CTRL0_3", + "CLK_HROW_IMUX47_1", + "CLK_HROW_WW4B3_5", + "CLK_HROW_CTRL1_6", + "CLK_HROW_WW4B1_2", + "CLK_HROW_WW2END3_5", + "CLK_HROW_IMUX42_3", + "CLK_HROW_SE4C0_6", + "CLK_HROW_IMUX17_4", + "CLK_HROW_CK_HCLK_OUT_L3", + "CLK_HROW_LH12_4", + "CLK_HROW_WW4C2_7", + "CLK_HROW_SW4END1_6", + "CLK_HROW_EL1BEG1_4", + "CLK_HROW_LH7_0", + "CLK_HROW_WW4A3_1", + "CLK_HROW_LH6_3", + "CLK_HROW_WW4B3_4", + "CLK_HROW_CK_IN_L10", + "CLK_HROW_IMUX45_0", + "CLK_HROW_LOGIC_OUTS_B13_0", + "CLK_HROW_SW4END0_3", + "CLK_HROW_ER1BEG0_3", + "CLK_HROW_LH11_4", + "CLK_HROW_LOGIC_OUTS_B19_3", + "CLK_HROW_NE2A3_5", + "CLK_HROW_WW4C3_4", + "CLK_HROW_EL1BEG2_1", + "CLK_HROW_EE2BEG2_4", + "CLK_HROW_WW4A3_4", + "CLK_HROW_IMUX38_0", + "CLK_HROW_EE2A2_2", + "CLK_HROW_BYP2_1", + "CLK_HROW_SW4END3_3", + "CLK_HROW_IMUX46_5", + "CLK_HROW_SE4C1_2", + "CLK_HROW_SE4C1_3", + "CLK_HROW_WL1END3_4", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN31", + "CLK_HROW_EL1BEG1_7", + "CLK_HROW_IMUX42_1", + "CLK_HROW_LOGIC_OUTS_B6_7", + "CLK_HROW_LOGIC_OUTS_B17_2", + "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "CLK_HROW_EL1BEG0_0", + "CLK_HROW_FAN1_6", + "CLK_HROW_CLK0_2", + "CLK_HROW_CK_BUFHCLK_L0", + "CLK_HROW_NE2A0_6", + "CLK_HROW_EE4C3_2", + "CLK_HROW_WW2END0_2", + "CLK_HROW_LOGIC_OUTS_B10_2", + "CLK_HROW_NE4BEG3_1", + "CLK_HROW_BYP3_1", + "CLK_HROW_IMUX43_4", + "CLK_HROW_LOGIC_OUTS_B8_6", + "CLK_HROW_EE2A0_7", + "CLK_HROW_WW4B0_1", + "CLK_HROW_FAN3_5", + "CLK_HROW_LOGIC_OUTS_B20_1", + "CLK_HROW_CK_GCLK_OUT_TEST13", + "CLK_HROW_EL1BEG2_3", + "CLK_HROW_IMUX38_6", + "CLK_HROW_WW2A2_2", + "CLK_HROW_NE4BEG3_7", + "CLK_HROW_CLK1_6", + "CLK_HROW_LOGIC_OUTS_B6_4", + "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "CLK_HROW_IMUX30_5", + "CLK_HROW_IMUX35_5", + "CLK_HROW_LH4_6", + "CLK_HROW_EE4C0_4", + "CLK_HROW_CK_GCLK_TEST_IN17", + "CLK_HROW_MONITOR_P_6", + "CLK_HROW_NW4A3_4", + "CLK_HROW_WW4END0_2", + "CLK_HROW_SW4END2_5", + "CLK_HROW_LH4_7", + "CLK_HROW_IMUX17_0", + "CLK_HROW_LOGIC_OUTS_B18_2", + "CLK_HROW_LOGIC_OUTS_B16_0", + "CLK_HROW_SE2A3_1", + "CLK_HROW_NW4A1_2", + "CLK_HROW_EE4BEG3_0", + "CLK_HROW_CK_GCLK_TEST_OUT22", + "CLK_HROW_CK_HCLK_OUT_L0", + "CLK_HROW_EE4C2_5", + "CLK_HROW_IMUX18_2", + "CLK_HROW_BLOCK_OUTS_B2_0", + "CLK_HROW_WR1END2_3", + "CLK_HROW_NW4A0_1", + "CLK_HROW_NE4C0_3", + "CLK_HROW_WW4END1_1", + "CLK_HROW_SE4C0_7", + "CLK_HROW_BYP5_0", + "CLK_HROW_SE4BEG3_2", + "CLK_HROW_IMUX1_6", + "CLK_HROW_BLOCK_OUTS_B3_6", + "CLK_HROW_WL1END3_2", + "CLK_HROW_EE4A2_1", + "CLK_HROW_EE2BEG3_5", + "CLK_HROW_EE2BEG3_4", + "CLK_HROW_NE4BEG1_7", + "CLK_HROW_IMUX47_7", + "CLK_HROW_CK_GCLK_TEST_OUT19", + "CLK_HROW_IMUX6_4", + "CLK_HROW_BYP1_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN13", + "CLK_HROW_LOGIC_OUTS_B16_7", + "CLK_HROW_SW2A2_3", + "CLK_HROW_CK_IN_R4", + "CLK_HROW_WW4C1_0", + "CLK_HROW_IMUX24_6", + "CLK_HROW_NW4END1_3", + "CLK_HROW_IMUX0_3", + "CLK_HROW_EE4B3_2", + "CLK_HROW_SE4BEG0_4", + "CLK_HROW_NE2A0_1", + "CLK_HROW_NW4A2_3", + "CLK_HROW_IMUX44_4", + "CLK_HROW_CK_GCLK_TEST_OUT31", + "CLK_HROW_SW4END2_1", + "CLK_HROW_SW4A1_3", + "CLK_HROW_EE2A3_5", + "CLK_HROW_LH10_2", + "CLK_HROW_LH9_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN4", + "CLK_HROW_NE4C1_0", + "CLK_HROW_CK_GCLK_TEST_OUT30", + "CLK_HROW_CK_GCLK_TEST_IN30", + "CLK_HROW_EE4B1_2", + "CLK_HROW_IMUX4_5", + "CLK_HROW_NE4BEG2_1", + "CLK_HROW_BUFHCE_CE_R7", + "CLK_HROW_ER1BEG1_7", + "CLK_HROW_LOGIC_OUTS_B23_6", + "CLK_HROW_LOGIC_OUTS_B2_0", + "CLK_HROW_EE4BEG1_6", + "CLK_HROW_EE4C2_7", + "CLK_HROW_NW2A3_6", + "CLK_HROW_NW4A2_7", + "CLK_HROW_SE4C1_7", + "CLK_HROW_IMUX6_1", + "CLK_HROW_SE2A2_4", + "CLK_HROW_IMUX3_2", + "CLK_HROW_IMUX19_4", + "CLK_HROW_IMUX31_1", + "CLK_HROW_NE4C3_5", + "CLK_HROW_LOGIC_OUTS_B19_2", + "CLK_HROW_ER1BEG3_4", + "CLK_HROW_WW2END3_7", + "CLK_HROW_NE4BEG0_5", + "CLK_HROW_FAN1_1", + "CLK_HROW_CK_GCLK_TEST_OUT16", + "CLK_HROW_BYP0_5", + "CLK_HROW_BYP4_6", + "CLK_HROW_LOGIC_OUTS_B12_0", + "CLK_HROW_LOGIC_OUTS_B17_7", + "CLK_HROW_EE2A2_1", + "CLK_HROW_LH8_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN12", + "CLK_HROW_CTRL1_1", + "CLK_HROW_EE2A1_7", + "CLK_HROW_WW2A1_1", + "CLK_HROW_LOGIC_OUTS_B9_5", + "CLK_HROW_SW4A3_2", + "CLK_HROW_SE2A2_7", + "CLK_HROW_CE_INT_TOP0", + "CLK_HROW_CK_HCLK_OUT_L6", + "CLK_HROW_IMUX29_3", + "CLK_HROW_IMUX28_1", + "CLK_HROW_IMUX37_2", + "CLK_HROW_WW4A3_7", + "CLK_HROW_CK_GCLK_IN_TEST24", + "CLK_HROW_WL1END0_7", + "CLK_HROW_LOGIC_OUTS_B21_6", + "CLK_HROW_NW4END0_1", + "CLK_HROW_SW2A3_1", + "CLK_HROW_IMUX21_6", + "CLK_HROW_CK_GCLK_IN_TEST12", + "CLK_HROW_WR1END3_0", + "CLK_HROW_SW2A2_1", + "CLK_HROW_SW2A3_0", + "CLK_HROW_CK_IN_L_TEST_OUT", + "CLK_HROW_IMUX25_2", + "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "CLK_HROW_WR1END0_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN17", + "CLK_HROW_SW4END2_4", + "CLK_HROW_EL1BEG2_0", + "CLK_HROW_LH12_0", + "CLK_HROW_WR1END1_0", + "CLK_HROW_CK_IN_R0", + "CLK_HROW_LH4_3", + "CLK_HROW_LOGIC_OUTS_B23_4", + "CLK_HROW_IMUX13_3", + "CLK_HROW_IMUX40_6", + "CLK_HROW_SW4A0_7", + "CLK_HROW_EE4B3_4", + "CLK_HROW_IMUX42_5", + "CLK_HROW_IMUX21_5", + "CLK_HROW_CK_BUFHCLK_R4", + "CLK_HROW_FAN5_4", + "CLK_HROW_LOGIC_OUTS_B11_0", + "CLK_HROW_EE2BEG0_3", + "CLK_HROW_BUFHCE_CE_R2", + "CLK_HROW_NE4BEG0_2", + "CLK_HROW_SW2A0_3", + "CLK_HROW_EL1BEG3_7", + "CLK_HROW_WW4B0_6", + "CLK_HROW_EE4C2_0", + "CLK_HROW_IMUX45_7", + "CLK_HROW_WW4A0_1", + "CLK_HROW_SE4BEG3_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "CLK_HROW_IMUX21_4", + "CLK_HROW_IMUX26_6", + "CLK_HROW_FAN7_7", + "CLK_HROW_IMUX9_1", + "CLK_HROW_EE4C1_7", + "CLK_HROW_EE4B1_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN24", + "CLK_HROW_WL1END1_2", + "CLK_HROW_LOGIC_OUTS_B0_6", + "CLK_HROW_LH7_7", + "CLK_HROW_CK_GCLK_OUT_TEST22", + "CLK_HROW_IMUX41_0", + "CLK_HROW_LH12_3", + "CLK_HROW_SE2A2_2", + "CLK_HROW_IMUX39_5", + "CLK_HROW_LOGIC_OUTS_B11_7", + "CLK_HROW_SE2A2_6", + "CLK_HROW_FAN7_3", + "CLK_HROW_LH5_4", + "CLK_HROW_ER1BEG0_2", + "CLK_HROW_LOGIC_OUTS_B3_3", + "CLK_HROW_EE4A0_2", + "CLK_HROW_CK_HCLK_OUT_L7", + "CLK_HROW_LOGIC_OUTS_B21_1", + "CLK_HROW_CK_GCLK_TEST12", + "CLK_HROW_CK_HCLK_OUT_R2", + "CLK_HROW_IMUX0_2", + "CLK_HROW_IMUX36_4", + "CLK_HROW_IMUX30_1", + "CLK_HROW_IMUX8_5", + "CLK_HROW_LOGIC_OUTS_B22_0", + "CLK_HROW_WW4END2_3", + "CLK_HROW_SW4END3_1", + "CLK_HROW_CK_GCLK_TEST13", + "CLK_HROW_LH6_0", + "CLK_HROW_WW2END1_0", + "CLK_HROW_CK_GCLK_TEST19", + "CLK_HROW_WW4A1_3", + "CLK_HROW_R_CK_GCLK29", + "CLK_HROW_LOGIC_OUTS_B18_1", + "CLK_HROW_IMUX41_6", + "CLK_HROW_NE4C0_4", + "CLK_HROW_LH4_1", + "CLK_HROW_LOGIC_OUTS_B1_5", + "CLK_HROW_BLOCK_OUTS_B1_2", + "CLK_HROW_LH5_2", + "CLK_HROW_CK_GCLK_TEST_OUT15", + "CLK_HROW_FAN5_5", + "CLK_HROW_R_CK_GCLK22", + "CLK_HROW_IMUX32_0", + "CLK_HROW_WL1END3_6", + "CLK_HROW_CK_HCLK_OUT_R1", + "CLK_HROW_WW4B1_0", + "CLK_HROW_SE2A1_0", + "CLK_HROW_ER1BEG3_2", + "CLK_HROW_SE2A3_4", + "CLK_HROW_BLOCK_OUTS_B0_3", + "CLK_HROW_CK_GCLK_TEST_IN2", + "CLK_HROW_LH4_2", + "CLK_HROW_CK_MUX_OUT_R5", + "CLK_HROW_WR1END0_3", + "CLK_HROW_CK_GCLK_TEST_IN27", + "CLK_HROW_WL1END1_3", + "CLK_HROW_IMUX4_2", + "CLK_HROW_LOGIC_OUTS_B20_4", + "CLK_HROW_CK_GCLK_TEST_OUT2", + "CLK_HROW_EE4B0_6", + "CLK_HROW_IMUX22_0", + "CLK_HROW_LOGIC_OUTS_B21_2", + "CLK_HROW_LOGIC_OUTS_B3_7", + "CLK_HROW_LOGIC_OUTS_B9_6", + "CLK_HROW_FAN1_0", + "CLK_HROW_WL1END3_5", + "CLK_HROW_LH1_1", + "CLK_HROW_WW4END2_1", + "CLK_HROW_CTRL0_2", + "CLK_HROW_IMUX12_1", + "CLK_HROW_IMUX33_4", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN21", + "CLK_HROW_CK_GCLK_OUT_TEST21", + "CLK_HROW_CK_MUX_OUT_L8", + "CLK_HROW_CK_GCLK_OUT_TEST16", + "CLK_HROW_WW2A2_1", + "CLK_HROW_IMUX5_4", + "CLK_HROW_SE2A0_7", + "CLK_HROW_EE4BEG0_6", + "CLK_HROW_IMUX13_6", + "CLK_HROW_LH5_1", + "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "CLK_HROW_IMUX32_3", + "CLK_HROW_EE4B2_3", + "CLK_HROW_CK_GCLK_TEST31", + "CLK_HROW_IMUX42_6", + "CLK_HROW_R_CK_GCLK0", + "CLK_HROW_WW2A2_5", + "CLK_HROW_R_CK_GCLK2", + "CLK_HROW_BYP3_2", + "CLK_HROW_CK_GCLK_TEST6", + "CLK_HROW_BUFHCE_CE_R5", + "CLK_HROW_BLOCK_OUTS_B2_2", + "CLK_HROW_EE2BEG2_0", + "CLK_HROW_LH10_1", + "CLK_HROW_NW4A1_4", + "CLK_HROW_BYP7_1", + "CLK_HROW_NW2A3_7", + "CLK_HROW_EE2BEG0_7", + "CLK_HROW_IMUX12_0", + "CLK_HROW_LOGIC_OUTS_B4_4", + "CLK_HROW_WR1END1_7", + "CLK_HROW_CK_GCLK_TEST_OUT17", + "CLK_HROW_MONITOR_N_6", + "CLK_HROW_BYP5_3", + "CLK_HROW_IMUX0_5", + "CLK_HROW_BYP1_6", + "CLK_HROW_LOGIC_OUTS_B10_0", + "CLK_HROW_CK_MUX_OUT_L3", + "CLK_HROW_IMUX46_0", + "CLK_HROW_ER1BEG3_1", + "CLK_HROW_IMUX47_5", + "CLK_HROW_SE4C2_7", + "CLK_HROW_EE4C0_5", + "CLK_HROW_CLK1_7", + "CLK_HROW_IMUX24_2", + "CLK_HROW_CK_GCLK_TEST_OUT26", + "CLK_HROW_WR1END1_2", + "CLK_HROW_WW4B0_4", + "CLK_HROW_ER1BEG2_0", + "CLK_HROW_EE4B1_0", + "CLK_HROW_BYP3_4", + "CLK_HROW_EE2BEG0_4", + "CLK_HROW_ER1BEG1_6", + "CLK_HROW_CLK1_2", + "CLK_HROW_CE_INT_TOP10", + "CLK_HROW_CK_GCLK_TEST_IN23", + "CLK_HROW_WR1END3_5", + "CLK_HROW_WW4A0_2", + "CLK_HROW_NW4A3_3", + "CLK_HROW_CK_GCLK_TEST18", + "CLK_HROW_FAN7_4", + "CLK_HROW_NE4BEG1_6", + "CLK_HROW_WR1END2_7", + "CLK_HROW_NW2A0_7", + "CLK_HROW_WW4B2_1", + "CLK_HROW_CK_GCLK_TEST_OUT10", + "CLK_HROW_NW4END2_7", + "CLK_HROW_WW4B0_0", + "CLK_HROW_IMUX10_0", + "CLK_HROW_IMUX44_7", + "CLK_HROW_CK_GCLK_TEST3", + "CLK_HROW_NE4C0_6", + "CLK_HROW_IMUX33_5", + "CLK_HROW_WW4B1_3", + "CLK_HROW_IMUX14_1", + "CLK_HROW_CK_GCLK_TEST_IN19", + "CLK_HROW_IMUX11_2", + "CLK_HROW_BUFHCE_CE_L10", + "CLK_HROW_CK_GCLK_IN_TEST3", + "CLK_HROW_CK_GCLK_IN_TEST27", + "CLK_HROW_FAN4_6", + "CLK_HROW_R_CK_GCLK15", + "CLK_HROW_SW2A1_0", + "CLK_HROW_CK_GCLK_OUT_TEST3", + "CLK_HROW_WW2END0_5", + "CLK_HROW_IMUX33_2", + "CLK_HROW_IMUX12_4", + "CLK_HROW_BYP0_2", + "CLK_HROW_CK_GCLK_IN_TEST4", + "CLK_HROW_SE4BEG3_5", + "CLK_HROW_CK_BUFHCLK_L10", + "CLK_HROW_NE4C1_6", + "CLK_HROW_EE2BEG1_5", + "CLK_HROW_SE4C0_4", + "CLK_HROW_LH11_0", + "CLK_HROW_CK_HCLK_OUT_R6", + "CLK_HROW_IMUX39_3", + "CLK_HROW_CK_GCLK_TEST1", + "CLK_HROW_NW4A0_2", + "CLK_HROW_IMUX45_6", + "CLK_HROW_IMUX9_6", + "CLK_HROW_NW4A0_4", + "CLK_HROW_SW2A3_6", + "CLK_HROW_FAN2_6", + "CLK_HROW_EE2A2_0", + "CLK_HROW_LH9_0", + "CLK_HROW_NE2A2_2", + "CLK_HROW_WW4A0_5", + "CLK_HROW_ER1BEG2_1", + "CLK_HROW_IMUX20_2", + "CLK_HROW_CK_IN_L9", + "CLK_HROW_BLOCK_OUTS_B3_1", + "CLK_HROW_LOGIC_OUTS_B8_4", + "CLK_HROW_LOGIC_OUTS_B23_7", + "CLK_HROW_ER1BEG1_2", + "CLK_HROW_LH8_4", + "CLK_HROW_FAN4_7", + "CLK_HROW_FAN0_6", + "CLK_HROW_EE2A3_7", + "CLK_HROW_CK_BUFHCLK_L6", + "CLK_HROW_LH7_3", + "CLK_HROW_CK_GCLK_OUT_TEST14", + "CLK_HROW_SW4END0_0", + "CLK_HROW_CK_GCLK_IN_TEST0", + "CLK_HROW_WW4A2_6", + "CLK_HROW_IMUX34_4", + "CLK_HROW_NW2A1_1", + "CLK_HROW_SW2A3_4", + "CLK_HROW_EE4BEG3_1", + "CLK_HROW_CK_MUX_OUT_R6", + "CLK_HROW_CE_INT_TOP4", + "CLK_HROW_LH9_5", + "CLK_HROW_IMUX19_5", + "CLK_HROW_IMUX31_5", + "CLK_HROW_NE4C1_3", + "CLK_HROW_IMUX2_4", + "CLK_HROW_CE_INT_BOT2", + "CLK_HROW_SW2A1_2", + "CLK_HROW_SW2A3_5", + "CLK_HROW_FAN2_7", + "CLK_HROW_EE2BEG2_3", + "CLK_HROW_IMUX29_6", + "CLK_HROW_EE2BEG3_0", + "CLK_HROW_EE4A3_0", + "CLK_HROW_BLOCK_OUTS_B3_0", + "CLK_HROW_EE4BEG2_4", + "CLK_HROW_NE4C0_7", + "CLK_HROW_CK_BUFRCLK_R1", + "CLK_HROW_MONITOR_P_0", + "CLK_HROW_BLOCK_OUTS_B2_6", + "CLK_HROW_WR1END3_7", + "CLK_HROW_CK_GCLK_TEST_OUT13", + "CLK_HROW_R_CK_GCLK28", + "CLK_HROW_EE2A0_0", + "CLK_HROW_LOGIC_OUTS_B23_5", + "CLK_HROW_CK_GCLK_TEST21", + "CLK_HROW_SE4C2_2", + "CLK_HROW_BUFHCE_CE_L2", + "CLK_HROW_BLOCK_OUTS_B2_5", + "CLK_HROW_SE2A2_5", + "CLK_HROW_FAN4_2", + "CLK_HROW_LOGIC_OUTS_B5_4", + "CLK_HROW_WR1END3_2", + "CLK_HROW_IMUX17_1", + "CLK_HROW_FAN7_5", + "CLK_HROW_WW4B0_7", + "CLK_HROW_SE4C1_1", + "CLK_HROW_EL1BEG0_6", + "CLK_HROW_EE2A3_2", + "CLK_HROW_FAN6_7", + "CLK_HROW_EE2BEG2_5", + "CLK_HROW_LOGIC_OUTS_B21_0", + "CLK_HROW_SE4BEG0_5", + "CLK_HROW_CE_INT_TOP9", + "CLK_HROW_ER1BEG2_3", + "CLK_HROW_EL1BEG3_2", + "CLK_HROW_NE4BEG1_0", + "CLK_HROW_IMUX5_7", + "CLK_HROW_EE2A2_7", + "CLK_HROW_CLK1_1", + "CLK_HROW_LH11_5", + "CLK_HROW_SE4C2_5", + "CLK_HROW_IMUX30_3", + "CLK_HROW_CK_BUFHCLK_R1", + "CLK_HROW_LOGIC_OUTS_B1_2", + "CLK_HROW_LOGIC_OUTS_B20_3", + "CLK_HROW_IMUX33_0", + "CLK_HROW_EE2BEG1_3", + "CLK_HROW_EL1BEG1_6", + "CLK_HROW_EE4C0_6", + "CLK_HROW_LOGIC_OUTS_B19_5", + "CLK_HROW_NE4BEG1_3", + "CLK_HROW_BYP6_2", + "CLK_HROW_LOGIC_OUTS_B19_6", + "CLK_HROW_SW2A1_3", + "CLK_HROW_IMUX37_0", + "CLK_HROW_WW4B1_4", + "CLK_HROW_IMUX0_6", + "CLK_HROW_CK_MUX_OUT_R0", + "CLK_HROW_IMUX32_7", + "CLK_HROW_LOGIC_OUTS_B17_4", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN18", + "CLK_HROW_NW4END0_5", + "CLK_HROW_NE4C0_2", + "CLK_HROW_SW4END0_1", + "CLK_HROW_WL1END1_7", + "CLK_HROW_LH1_3", + "CLK_HROW_BLOCK_OUTS_B0_4", + "CLK_HROW_IMUX39_0", + "CLK_HROW_WR1END3_4", + "CLK_HROW_LOGIC_OUTS_B15_7", + "CLK_HROW_NW4END2_3", + "CLK_HROW_LOGIC_OUTS_B10_7", + "CLK_HROW_CTRL1_5", + "CLK_HROW_NW2A2_4", + "CLK_HROW_IMUX34_0", + "CLK_HROW_IMUX24_3", + "CLK_HROW_WW2A0_5", + "CLK_HROW_LOGIC_OUTS_B16_5", + "CLK_HROW_CK_BUFHCLK_R9", + "CLK_HROW_IMUX22_6", + "CLK_HROW_EE4BEG1_5", + "CLK_HROW_IMUX25_7", + "CLK_HROW_IMUX23_3", + "CLK_HROW_EE4B2_7", + "CLK_HROW_LOGIC_OUTS_B5_2", + "CLK_HROW_LOGIC_OUTS_B5_7", + "CLK_HROW_WW4A2_7", + "CLK_HROW_CK_GCLK_TEST_IN21", + "CLK_HROW_WW4END0_0", + "CLK_HROW_IMUX33_1", + "CLK_HROW_SW4A2_2", + "CLK_HROW_CK_GCLK_TEST23", + "CLK_HROW_EE4A2_2", + "CLK_HROW_LH10_6", + "CLK_HROW_BYP3_7", + "CLK_HROW_SE4C2_0", + "CLK_HROW_SE4C3_5", + "CLK_HROW_IMUX39_6", + "CLK_HROW_R_CK_GCLK31", + "CLK_HROW_FAN2_4", + "CLK_HROW_EL1BEG3_1", + "CLK_HROW_WW4A2_2", + "CLK_HROW_LH7_6", + "CLK_HROW_LOGIC_OUTS_B7_1", + "CLK_HROW_LOGIC_OUTS_B13_1", + "CLK_HROW_CK_GCLK_TEST5", + "CLK_HROW_ER1BEG3_7", + "CLK_HROW_BYP5_4", + "CLK_HROW_SE4C0_3", + "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN9", + "CLK_HROW_IMUX2_1", + "CLK_HROW_IMUX39_4", + "CLK_HROW_SW4A0_0", + "CLK_HROW_CK_GCLK_TEST29", + "CLK_HROW_LOGIC_OUTS_B21_4", + "CLK_HROW_IMUX35_1", + "CLK_HROW_CK_GCLK_TEST_IN22", + "CLK_HROW_FAN6_2", + "CLK_HROW_FAN4_5", + "CLK_HROW_CK_GCLK_IN_TEST26", + "CLK_HROW_BYP6_3", + "CLK_HROW_BUFHCE_CE_L5", + "CLK_HROW_IMUX43_6", + "CLK_HROW_WW4END3_4", + "CLK_HROW_SW2A2_4", + "CLK_HROW_MONITOR_P_7", + "CLK_HROW_SW4END2_2", + "CLK_HROW_CK_GCLK_TEST_IN9", + "CLK_HROW_LOGIC_OUTS_B19_0", + "CLK_HROW_LOGIC_OUTS_B10_5", + "CLK_HROW_NW4A3_0", + "CLK_HROW_CK_GCLK_TEST_IN13", + "CLK_HROW_WW2END1_1", + "CLK_HROW_IMUX34_7", + "CLK_HROW_EE4BEG2_3", + "CLK_HROW_EE4B2_2", + "CLK_HROW_CTRL0_4", + "CLK_HROW_IMUX3_3", + "CLK_HROW_EE4B1_4", + "CLK_HROW_CK_IN_R9", + "CLK_HROW_IMUX19_0", + "CLK_HROW_WW2END2_1", + "CLK_HROW_CK_GCLK_TEST_OUT5", + "CLK_HROW_WR1END1_3", + "CLK_HROW_IMUX9_3", + "CLK_HROW_LOGIC_OUTS_B20_2", + "CLK_HROW_WW4A1_1", + "CLK_HROW_WW4B1_1", + "CLK_HROW_CK_BUFHCLK_R0", + "CLK_HROW_NW4A3_5", + "CLK_HROW_IMUX2_3", + "CLK_HROW_IMUX26_3", + "CLK_HROW_CK_GCLK_TEST17", + "CLK_HROW_EE4BEG0_5", + "CLK_HROW_IMUX8_6", + "CLK_HROW_NW4END1_0", + "CLK_HROW_LOGIC_OUTS_B23_2", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN2", + "CLK_HROW_IMUX11_4", + "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "CLK_HROW_WW4END3_2", + "CLK_HROW_IMUX12_2", + "CLK_HROW_LOGIC_OUTS_B10_3", + "CLK_HROW_CK_BUFHCLK_L1", + "CLK_HROW_NE2A3_2", + "CLK_HROW_SW2A3_7", + "CLK_HROW_LOGIC_OUTS_B8_5", + "CLK_HROW_SE4C1_5", + "CLK_HROW_NE4C2_4", + "CLK_HROW_FAN5_0", + "CLK_HROW_CK_HCLK_OUT_L10", + "CLK_HROW_SE2A0_1", + "CLK_HROW_FAN2_2", + "CLK_HROW_WL1END2_0", + "CLK_HROW_CK_IN_L4", + "CLK_HROW_LOGIC_OUTS_B4_0", + "CLK_HROW_WW2END1_4", + "CLK_HROW_NW4END3_4", + "CLK_HROW_EE4A1_7", + "CLK_HROW_NW4END0_3", + "CLK_HROW_IMUX8_1", + "CLK_HROW_BYP2_7", + "CLK_HROW_LOGIC_OUTS_B6_3", + "CLK_HROW_CK_MUX_OUT_R7", + "CLK_HROW_CK_GCLK_TEST25", + "CLK_HROW_BLOCK_OUTS_B0_0", + "CLK_HROW_IMUX42_7", + "CLK_HROW_BYP2_0", + "CLK_HROW_NW2A0_5", + "CLK_HROW_BYP5_7", + "CLK_HROW_CK_GCLK_IN_TEST23", + "CLK_HROW_CK_GCLK_IN_TEST1", + "CLK_HROW_CK_BUFHCLK_L7", + "CLK_HROW_IMUX8_4", + "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "CLK_HROW_EE4C1_0", + "CLK_HROW_REFCK_WESTCLK1", + "CLK_HROW_CK_GCLK_IN_TEST6", + "CLK_HROW_SW4END3_6", + "CLK_HROW_MONITOR_N_0", + "CLK_HROW_IMUX22_2", + "CLK_HROW_R_CK_GCLK19", + "CLK_HROW_EE4A0_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "CLK_HROW_CK_GCLK_OUT_TEST18", + "CLK_HROW_IMUX40_2", + "CLK_HROW_BYP1_2", + "CLK_HROW_CLK0_5", + "CLK_HROW_CK_GCLK_TEST_IN28", + "CLK_HROW_LH7_4", + "CLK_HROW_EE4A2_6", + "CLK_HROW_NW4A2_2", + "CLK_HROW_R_CK_GCLK6", + "CLK_HROW_IMUX37_5", + "CLK_HROW_EE2A0_6", + "CLK_HROW_IMUX18_6", + "CLK_HROW_LOGIC_OUTS_B4_7", + "CLK_HROW_EE4BEG1_2", + "CLK_HROW_IMUX28_4", + "CLK_HROW_BLOCK_OUTS_B1_0", + "CLK_HROW_LH7_2", + "CLK_HROW_IMUX15_1", + "CLK_HROW_MONITOR_P_2", + "CLK_HROW_IMUX10_4", + "CLK_HROW_SW4A3_1", + "CLK_HROW_IMUX2_6", + "CLK_HROW_LH5_6", + "CLK_HROW_CK_GCLK_IN_TEST8", + "CLK_HROW_SW2A2_2", + "CLK_HROW_EE2BEG3_6", + "CLK_HROW_LOGIC_OUTS_B14_1", + "CLK_HROW_LOGIC_OUTS_B7_6", + "CLK_HROW_IMUX30_4", + "CLK_HROW_EE4C0_7", + "CLK_HROW_IMUX24_0", + "CLK_HROW_IMUX41_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "CLK_HROW_WR1END0_2", + "CLK_HROW_SE4BEG3_1", + "CLK_HROW_LOGIC_OUTS_B16_2", + "CLK_HROW_CK_BUFRCLK_L1", + "CLK_HROW_CTRL1_4", + "CLK_HROW_IMUX5_3", + "CLK_HROW_WW4END1_5", + "CLK_HROW_EE4C0_2", + "CLK_HROW_WR1END0_0", + "CLK_HROW_IMUX20_0", + "CLK_HROW_IMUX11_0", + "CLK_HROW_IMUX8_2", + "CLK_HROW_LH10_4", + "CLK_HROW_CK_GCLK_TEST_IN24", + "CLK_HROW_IMUX38_4", + "CLK_HROW_ER1BEG2_6", + "CLK_HROW_WW4C2_4", + "CLK_HROW_WW2END0_4", + "CLK_HROW_SE4BEG2_2", + "CLK_HROW_EE4B1_3", + "CLK_HROW_LOGIC_OUTS_B23_0", + "CLK_HROW_IMUX4_4", + "CLK_HROW_LOGIC_OUTS_B13_4", + "CLK_HROW_WW4C2_5", + "CLK_HROW_MONITOR_N_1", + "CLK_HROW_IMUX39_1", + "CLK_HROW_IMUX29_1", + "CLK_HROW_IMUX23_7", + "CLK_HROW_LH3_6", + "CLK_HROW_IMUX31_0", + "CLK_HROW_EE4C1_2", + "CLK_HROW_LH11_7", + "CLK_HROW_SW2A0_4", + "CLK_HROW_WL1END0_0", + "CLK_HROW_FAN7_2", + "CLK_HROW_IMUX28_2", + "CLK_HROW_WW4C0_2", + "CLK_HROW_CE_INT_TOP6", + "CLK_HROW_BYP1_4", + "CLK_HROW_IMUX35_4", + "CLK_HROW_REFCK_EASTCLK1", + "CLK_HROW_SE2A3_6", + "CLK_HROW_LOGIC_OUTS_B23_3", + "CLK_HROW_CK_BUFHCLK_L8", + "CLK_HROW_NE4C3_2", + "CLK_HROW_IMUX8_0", + "CLK_HROW_WL1END0_3", + "CLK_HROW_BYP6_1", + "CLK_HROW_ER1BEG3_0", + "CLK_HROW_CK_GCLK_TEST_OUT6", + "CLK_HROW_CK_GCLK_OUT_TEST31", + "CLK_HROW_IMUX39_2", + "CLK_HROW_CK_GCLK_TEST2", + "CLK_HROW_WR1END0_1", + "CLK_HROW_NE4BEG3_3", + "CLK_HROW_IMUX35_7", + "CLK_HROW_LOGIC_OUTS_B7_0", + "CLK_HROW_SW4END0_5", + "CLK_HROW_CK_BUFHCLK_R6", + "CLK_HROW_IMUX15_2", + "CLK_HROW_CK_HCLK_OUT_L4", + "CLK_HROW_SW2A3_2", + "CLK_HROW_SW4END3_5", + "CLK_HROW_FAN1_4", + "CLK_HROW_EE4A1_0", + "CLK_HROW_WW4END1_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "CLK_HROW_EL1BEG2_2", + "CLK_HROW_BYP3_6", + "CLK_HROW_EE4B3_6", + "CLK_HROW_WW2A3_0", + "CLK_HROW_WW4A0_3", + "CLK_HROW_WW4B2_0", + "CLK_HROW_EE4BEG0_1", + "CLK_HROW_WW2END0_1", + "CLK_HROW_ER1BEG0_0", + "CLK_HROW_SE4BEG1_3", + "CLK_HROW_EE4B0_7", + "CLK_HROW_CK_MUX_OUT_R2", + "CLK_HROW_EE4C1_1", + "CLK_HROW_CE_INT_TOP2", + "CLK_HROW_BUFHCE_CE_R6", + "CLK_HROW_EE2A3_4", + "CLK_HROW_WW2A0_3", + "CLK_HROW_CK_HCLK_OUT_R5", + "CLK_HROW_IMUX1_3", + "CLK_HROW_LH1_7", + "CLK_HROW_EE2A1_1", + "CLK_HROW_LOGIC_OUTS_B0_1", + "CLK_HROW_R_CK_GCLK10", + "CLK_HROW_IMUX6_2", + "CLK_HROW_CK_GCLK_TEST14", + "CLK_HROW_IMUX14_3", + "CLK_HROW_CK_GCLK_TEST_OUT28", + "CLK_HROW_LOGIC_OUTS_B19_7", + "CLK_HROW_WL1END3_1", + "CLK_HROW_NW4END0_6", + "CLK_HROW_WW4END1_4", + "CLK_HROW_IMUX21_1", + "CLK_HROW_IMUX15_7", + "CLK_HROW_CK_GCLK_IN_TEST19", + "CLK_HROW_IMUX45_5", + "CLK_HROW_WW4A3_6", + "CLK_HROW_ER1BEG1_4", + "CLK_HROW_BLOCK_OUTS_B1_3", + "CLK_HROW_IMUX5_5", + "CLK_HROW_IMUX17_3", + "CLK_HROW_IMUX44_0", + "CLK_HROW_IMUX36_2", + "CLK_HROW_BUFHCE_CE_R9", + "CLK_HROW_LH12_5", + "CLK_HROW_R_CK_GCLK21", + "CLK_HROW_IMUX35_2", + "CLK_HROW_CK_BUFHCLK_L9", + "CLK_HROW_SW4A1_2", + "CLK_HROW_WW2A3_7", + "CLK_HROW_CLK0_1", + "CLK_HROW_CK_IN_R7", + "CLK_HROW_CLK1_5", + "CLK_HROW_IMUX0_7", + "CLK_HROW_LH6_4", + "CLK_HROW_WW4C3_6", + "CLK_HROW_BUFHCE_CE_R0", + "CLK_HROW_CK_GCLK_TEST_IN10", + "CLK_HROW_IMUX17_2", + "CLK_HROW_CK_GCLK_TEST_IN8", + "CLK_HROW_NW4END2_5", + "CLK_HROW_LOGIC_OUTS_B16_1", + "CLK_HROW_CK_IN_L0", + "CLK_HROW_WW4END3_1", + "CLK_HROW_IMUX15_3", + "CLK_HROW_NW4A0_3", + "CLK_HROW_IMUX9_4", + "CLK_HROW_NW4A1_1", + "CLK_HROW_LOGIC_OUTS_B12_2", + "CLK_HROW_IMUX44_3", + "CLK_HROW_BLOCK_OUTS_B3_7", + "CLK_HROW_EL1BEG0_4", + "CLK_HROW_FAN5_1", + "CLK_HROW_WW4B3_1", + "CLK_HROW_CK_GCLK_TEST_OUT12", + "CLK_HROW_CK_GCLK_TEST_IN3", + "CLK_HROW_SW2A0_6", + "CLK_HROW_CK_GCLK_TEST22", + "CLK_HROW_EE4B3_5", + "CLK_HROW_EE2A2_4", + "CLK_HROW_CK_GCLK_OUT_TEST1", + "CLK_HROW_IMUX6_6", + "CLK_HROW_EE4BEG1_4", + "CLK_HROW_NE2A3_3", + "CLK_HROW_IMUX27_5", + "CLK_HROW_CK_GCLK_IN_TEST20", + "CLK_HROW_NE2A3_4", + "CLK_HROW_EL1BEG3_5", + "CLK_HROW_CK_BUFHCLK_L4", + "CLK_HROW_BUFHCE_CE_L8", + "CLK_HROW_CLK1_4", + "CLK_HROW_LOGIC_OUTS_B2_7", + "CLK_HROW_BYP0_7", + "CLK_HROW_IMUX25_0", + "CLK_HROW_WW4A1_5", + "CLK_HROW_MONITOR_P_1", + "CLK_HROW_LH1_6", + "CLK_HROW_WW4END2_0", + "CLK_HROW_CK_MUX_OUT_L6", + "CLK_HROW_CK_GCLK_TEST_OUT24", + "CLK_HROW_NW2A1_5", + "CLK_HROW_CK_GCLK_TEST8", + "CLK_HROW_NW4END1_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN10", + "CLK_HROW_WW4C1_6", + "CLK_HROW_LOGIC_OUTS_B6_2", + "CLK_HROW_IMUX18_7", + "CLK_HROW_EE4A0_1", + "CLK_HROW_SE2A1_6", + "CLK_HROW_IMUX46_7", + "CLK_HROW_IMUX9_2", + "CLK_HROW_IMUX26_7", + "CLK_HROW_LOGIC_OUTS_B21_5", + "CLK_HROW_EE4A2_3", + "CLK_HROW_FAN6_0", + "CLK_HROW_CK_IN_R12", + "CLK_HROW_EE4B0_4", + "CLK_HROW_SW4END0_4", + "CLK_HROW_IMUX16_2", + "CLK_HROW_IMUX26_1", + "CLK_HROW_EE2BEG3_1", + "CLK_HROW_EE4A2_0", + "CLK_HROW_EE4B3_0", + "CLK_HROW_LH4_0", + "CLK_HROW_ER1BEG0_5", + "CLK_HROW_CK_BUFHCLK_L2", + "CLK_HROW_CTRL0_1", + "CLK_HROW_EE4BEG3_4", + "CLK_HROW_NE2A1_3", + "CLK_HROW_SE2A0_3", + "CLK_HROW_IMUX7_6", + "CLK_HROW_LH12_1", + "CLK_HROW_WW2END3_3", + "CLK_HROW_NW2A0_6", + "CLK_HROW_NE4C0_0", + "CLK_HROW_IMUX28_5", + "CLK_HROW_SW4A1_7", + "CLK_HROW_LH11_2", + "CLK_HROW_CK_MUX_OUT_R8", + "CLK_HROW_LOGIC_OUTS_B9_1", + "CLK_HROW_NE2A0_0", + "CLK_HROW_EE4A0_6", + "CLK_HROW_NE2A0_7", + "CLK_HROW_EE4C0_1", + "CLK_HROW_IMUX0_4", + "CLK_HROW_EE4C3_7", + "CLK_HROW_IMUX24_4", + "CLK_HROW_CLK0_7", + "CLK_HROW_NE4BEG0_1", + "CLK_HROW_BYP2_5", + "CLK_HROW_WW2A0_4", + "CLK_HROW_R_CK_GCLK5", + "CLK_HROW_IMUX34_3", + "CLK_HROW_LOGIC_OUTS_B1_3", + "CLK_HROW_WL1END3_0", + "CLK_HROW_BLOCK_OUTS_B2_4", + "CLK_HROW_SE4BEG2_3", + "CLK_HROW_EE4A3_4", + "CLK_HROW_EE2A1_2", + "CLK_HROW_LH2_7", + "CLK_HROW_EE2A0_1", + "CLK_HROW_EE2BEG2_2", + "CLK_HROW_WL1END0_1", + "CLK_HROW_BYP6_0", + "CLK_HROW_NE4BEG3_4", + "CLK_HROW_LOGIC_OUTS_B13_7", + "CLK_HROW_CK_GCLK_TEST27", + "CLK_HROW_EE4C2_2", + "CLK_HROW_IMUX38_5", + "CLK_HROW_LOGIC_OUTS_B14_5", + "CLK_HROW_LH3_2", + "CLK_HROW_BLOCK_OUTS_B2_1", + "CLK_HROW_CE_INT_BOT5", + "CLK_HROW_SW4A0_2", + "CLK_HROW_R_CK_GCLK11", + "CLK_HROW_CK_BUFHCLK_R3", + "CLK_HROW_CK_GCLK_OUT_TEST17", + "CLK_HROW_CK_GCLK_OUT_TEST28", + "CLK_HROW_CK_GCLK_TEST_IN26", + "CLK_HROW_SE4C1_4", + "CLK_HROW_WW4B2_6", + "CLK_HROW_LOGIC_OUTS_B7_2", + "CLK_HROW_LH2_1", + "CLK_HROW_SW4A1_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN1", + "CLK_HROW_R_CK_GCLK25", + "CLK_HROW_FAN2_5", + "CLK_HROW_WW2A1_4", + "CLK_HROW_CK_GCLK_OUT_TEST29", + "CLK_HROW_WW4C1_3", + "CLK_HROW_LOGIC_OUTS_B13_5", + "CLK_HROW_IMUX14_7", + "CLK_HROW_NW4A3_6", + "CLK_HROW_EE4C2_3", + "CLK_HROW_CK_GCLK_IN_TEST31", + "CLK_HROW_NE2A3_7", + "CLK_HROW_EL1BEG0_3", + "CLK_HROW_CK_MUX_OUT_R4", + "CLK_HROW_CK_GCLK_IN_TEST18", + "CLK_HROW_LOGIC_OUTS_B22_4", + "CLK_HROW_WW4A0_0", + "CLK_HROW_WW2A3_3", + "CLK_HROW_CTRL1_7", + "CLK_HROW_IMUX18_5", + "CLK_HROW_IMUX31_7", + "CLK_HROW_NW2A3_1", + "CLK_HROW_R_CK_GCLK30", + "CLK_HROW_EE4C1_3", + "CLK_HROW_FAN6_4", + "CLK_HROW_WW2A1_2", + "CLK_HROW_IMUX47_2", + "CLK_HROW_IMUX16_0", + "CLK_HROW_CK_GCLK_OUT_TEST9", + "CLK_HROW_CK_GCLK_OUT_TEST6", + "CLK_HROW_IMUX21_0", + "CLK_HROW_EE4C0_3", + "CLK_HROW_FAN5_3", + "CLK_HROW_NE2A3_0", + "CLK_HROW_SE4BEG0_7", + "CLK_HROW_SW4A2_0", + "CLK_HROW_BUFHCE_CE_R10", + "CLK_HROW_LOGIC_OUTS_B14_6", + "CLK_HROW_CK_IN_L3", + "CLK_HROW_WW2END1_7", + "CLK_HROW_SW4END3_7", + "CLK_HROW_IMUX33_7", + "CLK_HROW_CK_HCLK_OUT_R3", + "CLK_HROW_WW4C0_5", + "CLK_HROW_SE4C1_6", + "CLK_HROW_SW4END2_7", + "CLK_HROW_CK_BUFRCLK_L3", + "CLK_HROW_LOGIC_OUTS_B14_4", + "CLK_HROW_LH2_2", + "CLK_HROW_NE4BEG0_4", + "CLK_HROW_WW4B1_7", + "CLK_HROW_WW4END3_6", + "CLK_HROW_EE4BEG0_0", + "CLK_HROW_CTRL1_0", + "CLK_HROW_CK_HCLK_OUT_R9", + "CLK_HROW_WW4A2_5", + "CLK_HROW_EE4BEG2_1", + "CLK_HROW_BLOCK_OUTS_B1_6", + "CLK_HROW_IMUX24_7", + "CLK_HROW_WL1END2_6", + "CLK_HROW_LOGIC_OUTS_B18_6", + "CLK_HROW_IMUX43_0", + "CLK_HROW_NW2A0_3", + "CLK_HROW_IMUX22_5", + "CLK_HROW_EE4B3_3", + "CLK_HROW_NE2A0_5", + "CLK_HROW_LH7_1", + "CLK_HROW_LOGIC_OUTS_B8_3", + "CLK_HROW_SE4BEG3_3", + "CLK_HROW_LOGIC_OUTS_B11_3", + "CLK_HROW_SW4A0_1", + "CLK_HROW_SW4END2_3", + "CLK_HROW_EE4BEG2_6", + "CLK_HROW_LH8_3", + "CLK_HROW_NE4C0_5", + "CLK_HROW_LOGIC_OUTS_B17_3", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN14", + "CLK_HROW_EE4C3_3", + "CLK_HROW_EE2BEG0_5", + "CLK_HROW_IMUX42_2", + "CLK_HROW_SE2A0_6", + "CLK_HROW_CK_GCLK_OUT_TEST30", + "CLK_HROW_LOGIC_OUTS_B15_0", + "CLK_HROW_WW4C1_4", + "CLK_HROW_CK_MUX_OUT_L4", + "CLK_HROW_CK_MUX_OUT_L2", + "CLK_HROW_NW4END0_4", + "CLK_HROW_EE4A2_5", + "CLK_HROW_BLOCK_OUTS_B3_2", + "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "CLK_HROW_EE2BEG2_6", + "CLK_HROW_IMUX5_6", + "CLK_HROW_WW4A3_3", + "CLK_HROW_WW4C2_3", + "CLK_HROW_WW4B0_2", + "CLK_HROW_EL1BEG3_0", + "CLK_HROW_CTRL0_6", + "CLK_HROW_EE4B0_1", + "CLK_HROW_WW4A0_6", + "CLK_HROW_LH12_2", + "CLK_HROW_LOGIC_OUTS_B16_3", + "CLK_HROW_WW2A0_1", + "CLK_HROW_IMUX1_4", + "CLK_HROW_NE4BEG3_5", + "CLK_HROW_REFCK_EASTCLK0", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN19", + "CLK_HROW_WW2END3_2", + "CLK_HROW_LOGIC_OUTS_B21_7", + "CLK_HROW_IMUX1_5", + "CLK_HROW_NE2A0_4", + "CLK_HROW_IMUX40_3", + "CLK_HROW_IMUX16_4", + "CLK_HROW_EL1BEG2_7", + "CLK_HROW_IMUX45_2", + "CLK_HROW_LH9_7", + "CLK_HROW_NW4END2_4", + "CLK_HROW_WW2END0_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "CLK_HROW_NW4END1_6", + "CLK_HROW_FAN2_0", + "CLK_HROW_SE4BEG0_2", + "CLK_HROW_LOGIC_OUTS_B20_6", + "CLK_HROW_LOGIC_OUTS_B19_1", + "CLK_HROW_IMUX12_6", + "CLK_HROW_IMUX35_3", + "CLK_HROW_CK_GCLK_TEST_IN31", + "CLK_HROW_WW4B2_4", + "CLK_HROW_MONITOR_N_3", + "CLK_HROW_NE2A2_7", + "CLK_HROW_FAN7_6", + "CLK_HROW_FAN1_2", + "CLK_HROW_CK_BUFRCLK_L0", + "CLK_HROW_BYP4_1", + "CLK_HROW_BYP5_6", + "CLK_HROW_LH6_1", + "CLK_HROW_LOGIC_OUTS_B4_5", + "CLK_HROW_NE2A1_6", + "CLK_HROW_SE2A1_7", + "CLK_HROW_CK_BUFRCLK_R0", + "CLK_HROW_IMUX7_7", + "CLK_HROW_SW4A2_5", + "CLK_HROW_NW4A1_6", + "CLK_HROW_EE4BEG3_2", + "CLK_HROW_IMUX0_1", + "CLK_HROW_CK_MUX_OUT_R11", + "CLK_HROW_IMUX41_7", + "CLK_HROW_WW4A1_7", + "CLK_HROW_IMUX46_6", + "CLK_HROW_LH12_6", + "CLK_HROW_IMUX26_4", + "CLK_HROW_EE2BEG1_4", + "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "CLK_HROW_NW2A0_2", + "CLK_HROW_IMUX29_7", + "CLK_HROW_CE_INT_BOT9", + "CLK_HROW_CLK0_0", + "CLK_HROW_NE2A2_1", + "CLK_HROW_BYP0_1", + "CLK_HROW_NE4C0_1", + "CLK_HROW_BYP4_7", + "CLK_HROW_SE4BEG1_2", + "CLK_HROW_IMUX27_7", + "CLK_HROW_WW4END0_7", + "CLK_HROW_LOGIC_OUTS_B20_0", + "CLK_HROW_LOGIC_OUTS_B1_0", + "CLK_HROW_CTRL0_7", + "CLK_HROW_WW4A0_7", + "CLK_HROW_EE4C2_6", + "CLK_HROW_CK_GCLK_OUT_TEST12", + "CLK_HROW_WW4A2_4", + "CLK_HROW_CK_GCLK_TEST_OUT20", + "CLK_HROW_IMUX21_2", + "CLK_HROW_BYP7_6", + "CLK_HROW_CK_IN_L12", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN20", + "CLK_HROW_IMUX3_1", + "CLK_HROW_EE4A3_6", + "CLK_HROW_IMUX20_3", + "CLK_HROW_CK_GCLK_TEST_IN18", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN3", + "CLK_HROW_LOGIC_OUTS_B7_4", + "CLK_HROW_IMUX24_5", + "CLK_HROW_BUFHCE_CE_L6", + "CLK_HROW_IMUX47_6", + "CLK_HROW_LOGIC_OUTS_B6_5", + "CLK_HROW_CK_GCLK_OUT_TEST20", + "CLK_HROW_IMUX20_5", + "CLK_HROW_LH8_5", + "CLK_HROW_SE4BEG1_0", + "CLK_HROW_CK_GCLK_OUT_TEST4", + "CLK_HROW_IMUX14_0", + "CLK_HROW_NE4C2_3", + "CLK_HROW_WW2END0_7", + "CLK_HROW_WW2A3_4", + "CLK_HROW_WR1END2_5", + "CLK_HROW_LOGIC_OUTS_B20_7", + "CLK_HROW_SE4BEG3_7", + "CLK_HROW_SW4A0_5", + "CLK_HROW_FAN0_4", + "CLK_HROW_CTRL0_5", + "CLK_HROW_NE4C2_7", + "CLK_HROW_LOGIC_OUTS_B0_4", + "CLK_HROW_EE4A1_2", + "CLK_HROW_LOGIC_OUTS_B6_1", + "CLK_HROW_IMUX37_4", + "CLK_HROW_CK_MUX_OUT_L7", + "CLK_HROW_IMUX22_7", + "CLK_HROW_WW4END1_2", + "CLK_HROW_CK_GCLK_TEST_IN15", + "CLK_HROW_BYP1_0", + "CLK_HROW_WW4B3_2", + "CLK_HROW_CK_GCLK_OUT_TEST19", + "CLK_HROW_LH5_7", + "CLK_HROW_WL1END2_4", + "CLK_HROW_BYP3_3", + "CLK_HROW_SE4BEG2_5", + "CLK_HROW_LOGIC_OUTS_B19_4", + "CLK_HROW_R_CK_GCLK8", + "CLK_HROW_CK_GCLK_TEST7", + "CLK_HROW_IMUX5_2", + "CLK_HROW_BLOCK_OUTS_B3_4", + "CLK_HROW_EE4BEG3_7", + "CLK_HROW_CK_GCLK_OUT_TEST11", + "CLK_HROW_LOGIC_OUTS_B0_0", + "CLK_HROW_SW4A3_3", + "CLK_HROW_BYP5_2", + "CLK_HROW_NW2A1_3", + "CLK_HROW_WW4B0_5", + "CLK_HROW_WR1END1_1", + "CLK_HROW_SE4BEG0_6", + "CLK_HROW_NE4C3_6", + "CLK_HROW_SE2A1_1", + "CLK_HROW_IMUX29_2", + "CLK_HROW_CK_GCLK_TEST_OUT1", + "CLK_HROW_CK_GCLK_TEST_OUT29", + "CLK_HROW_NW2A2_0", + "CLK_HROW_LOGIC_OUTS_B13_3", + "CLK_HROW_IMUX36_0", + "CLK_HROW_WW4C3_5", + "CLK_HROW_IMUX1_0", + "CLK_HROW_LH11_1", + "CLK_HROW_NW2A2_3", + "CLK_HROW_LH11_6", + "CLK_HROW_CK_HCLK_OUT_R8", + "CLK_HROW_IMUX3_4", + "CLK_HROW_IMUX3_6", + "CLK_HROW_EE2A1_0", + "CLK_HROW_CK_GCLK_IN_TEST5", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN11", + "CLK_HROW_LOGIC_OUTS_B5_6", + "CLK_HROW_FAN3_1", + "CLK_HROW_WL1END0_6", + "CLK_HROW_NE4BEG2_2", + "CLK_HROW_LOGIC_OUTS_B14_7", + "CLK_HROW_IMUX11_6", + "CLK_HROW_SE4BEG0_0", + "CLK_HROW_SW4END1_5", + "CLK_HROW_FAN6_5", + "CLK_HROW_IMUX23_1", + "CLK_HROW_IMUX29_5", + "CLK_HROW_EE2A0_4", + "CLK_HROW_SW4A3_7", + "CLK_HROW_WW4C2_6", + "CLK_HROW_WR1END2_1", + "CLK_HROW_WW4A1_2", + "CLK_HROW_CK_INT_0_1", + "CLK_HROW_IMUX4_3", + "CLK_HROW_IMUX45_4", + "CLK_HROW_SE4BEG1_4", + "CLK_HROW_WW4END2_5", + "CLK_HROW_WW4B2_5", + "CLK_HROW_EE4B1_1", + "CLK_HROW_SE2A0_0", + "CLK_HROW_LOGIC_OUTS_B9_4", + "CLK_HROW_SW4END0_7", + "CLK_HROW_WW4END3_7", + "CLK_HROW_LOGIC_OUTS_B17_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "CLK_HROW_SW4A0_3", + "CLK_HROW_BYP4_5", + "CLK_HROW_CTRL1_2", + "CLK_HROW_SE4C0_2", + "CLK_HROW_SE2A1_5", + "CLK_HROW_SE4BEG2_4", + "CLK_HROW_LOGIC_OUTS_B4_3", + "CLK_HROW_EE2BEG0_6", + "CLK_HROW_EE4A0_3", + "CLK_HROW_IMUX40_5", + "CLK_HROW_NE4BEG2_4", + "CLK_HROW_WW2A2_0", + "CLK_HROW_EE4C3_5", + "CLK_HROW_LOGIC_OUTS_B22_3", + "CLK_HROW_CK_INT_0_0", + "CLK_HROW_ER1BEG1_1", + "CLK_HROW_IMUX7_2", + "CLK_HROW_R_CK_GCLK27", + "CLK_HROW_CK_BUFRCLK_L2", + "CLK_HROW_NE4C2_5", + "CLK_HROW_NW4A3_2", + "CLK_HROW_LOGIC_OUTS_B2_5", + "CLK_HROW_CK_IN_L2", + "CLK_HROW_FAN0_5", + "CLK_HROW_IMUX23_2", + "CLK_HROW_IMUX34_6", + "CLK_HROW_NW4A3_1", + "CLK_HROW_NW4END2_6", + "CLK_HROW_EL1BEG2_6", + "CLK_HROW_IMUX13_0", + "CLK_HROW_IMUX11_1", + "CLK_HROW_NE4C1_5", + "CLK_HROW_IMUX25_1", + "CLK_HROW_NW4END2_0", + "CLK_HROW_BYP0_6", + "CLK_HROW_BYP2_2", + "CLK_HROW_IMUX14_6", + "CLK_HROW_LH3_5", + "CLK_HROW_FAN1_5", + "CLK_HROW_LOGIC_OUTS_B4_6", + "CLK_HROW_IMUX9_5", + "CLK_HROW_EE2A3_0", + "CLK_HROW_MONITOR_P_5", + "CLK_HROW_LOGIC_OUTS_B8_7", + "CLK_HROW_BYP4_4", + "CLK_HROW_EE4BEG3_3", + "CLK_HROW_IMUX40_7", + "CLK_HROW_LOGIC_OUTS_B1_6", + "CLK_HROW_IMUX22_3", + "CLK_HROW_WW4C2_2", + "CLK_HROW_CTRL1_3", + "CLK_HROW_CK_GCLK_IN_TEST11", + "CLK_HROW_CK_GCLK_OUT_TEST25", + "CLK_HROW_ER1BEG3_6", + "CLK_HROW_LOGIC_OUTS_B12_1", + "CLK_HROW_R_CK_GCLK14", + "CLK_HROW_NE2A1_4", + "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "CLK_HROW_EE4C1_5", + "CLK_HROW_IMUX19_6", + "CLK_HROW_IMUX15_6", + "CLK_HROW_NE2A2_6", + "CLK_HROW_EE4BEG2_7", + "CLK_HROW_NW4END3_1", + "CLK_HROW_EE2A2_3", + "CLK_HROW_CK_GCLK_IN_TEST15", + "CLK_HROW_CK_IN_L1", + "CLK_HROW_IMUX28_0", + "CLK_HROW_SE4C3_4", + "CLK_HROW_SW4A1_1", + "CLK_HROW_R_CK_GCLK3", + "CLK_HROW_EL1BEG0_7", + "CLK_HROW_NE2A1_5", + "CLK_HROW_EE2A1_4", + "CLK_HROW_EE4C3_4", + "CLK_HROW_ER1BEG1_3", + "CLK_HROW_EE4A1_3", + "CLK_HROW_LOGIC_OUTS_B4_2", + "CLK_HROW_IMUX45_1", + "CLK_HROW_SW4A3_6", + "CLK_HROW_ER1BEG3_5", + "CLK_HROW_CK_MUX_OUT_L10", + "CLK_HROW_NE2A3_1", + "CLK_HROW_IMUX17_5", + "CLK_HROW_BUFHCE_CE_L4", + "CLK_HROW_IMUX11_3", + "CLK_HROW_WW2END2_0", + "CLK_HROW_LH1_4", + "CLK_HROW_NW2A3_5", + "CLK_HROW_IMUX13_7", + "CLK_HROW_NW4END3_2", + "CLK_HROW_LH3_0", + "CLK_HROW_BLOCK_OUTS_B3_5", + "CLK_HROW_WW4A2_3", + "CLK_HROW_IMUX25_5", + "CLK_HROW_BYP7_2", + "CLK_HROW_EE2A1_3", + "CLK_HROW_LOGIC_OUTS_B13_6", + "CLK_HROW_LOGIC_OUTS_B12_6", + "CLK_HROW_WW4END2_4", + "CLK_HROW_CK_IN_L7", + "CLK_HROW_MONITOR_N_4", + "CLK_HROW_WL1END2_5", + "CLK_HROW_FAN0_7", + "CLK_HROW_SW2A2_6", + "CLK_HROW_WW4A3_5", + "CLK_HROW_IMUX44_1", + "CLK_HROW_SW4END2_6", + "CLK_HROW_EL1BEG1_2", + "CLK_HROW_IMUX5_0", + "CLK_HROW_IMUX19_7", + "CLK_HROW_SW2A0_7", + "CLK_HROW_LOGIC_OUTS_B18_5", + "CLK_HROW_NW4A0_5", + "CLK_HROW_IMUX28_6", + "CLK_HROW_BUFHCE_CE_R1", + "CLK_HROW_IMUX19_3", + "CLK_HROW_CK_GCLK_OUT_TEST23", + "CLK_HROW_IMUX34_1", + "CLK_HROW_CK_IN_R8", + "CLK_HROW_BYP1_7", + "CLK_HROW_IMUX31_6", + "CLK_HROW_IMUX14_4", + "CLK_HROW_NE2A0_2", + "CLK_HROW_ER1BEG3_3", + "CLK_HROW_NE4C1_2", + "CLK_HROW_BYP6_4", + "CLK_HROW_LOGIC_OUTS_B5_5", + "CLK_HROW_IMUX28_7", + "CLK_HROW_WR1END1_5", + "CLK_HROW_BLOCK_OUTS_B3_3", + "CLK_HROW_WL1END2_2", + "CLK_HROW_IMUX6_3", + "CLK_HROW_IMUX24_1", + "CLK_HROW_IMUX22_4", + "CLK_HROW_WW4C0_3", + "CLK_HROW_CK_GCLK_IN_TEST21", + "CLK_HROW_WW4A1_4", + "CLK_HROW_NE2A3_6", + "CLK_HROW_IMUX6_7", + "CLK_HROW_SE2A0_2", + "CLK_HROW_IMUX2_7", + "CLK_HROW_CK_GCLK_TEST28", + "CLK_HROW_IMUX23_6", + "CLK_HROW_NW2A2_2", + "CLK_HROW_NE4BEG0_7", + "CLK_HROW_CE_INT_BOT3", + "CLK_HROW_CK_BUFHCLK_R7", + "CLK_HROW_EE4C3_6", + "CLK_HROW_EE2A1_5", + "CLK_HROW_LH10_7", + "CLK_HROW_LOGIC_OUTS_B23_1", + "CLK_HROW_EE2BEG1_6", + "CLK_HROW_BYP4_0", + "CLK_HROW_IMUX43_2", + "CLK_HROW_CE_INT_TOP8", + "CLK_HROW_IMUX11_5", + "CLK_HROW_EE4BEG1_0", + "CLK_HROW_NW4END3_0", + "CLK_HROW_LOGIC_OUTS_B10_1", + "CLK_HROW_IMUX19_1", + "CLK_HROW_IMUX13_5", + "CLK_HROW_CK_BUFHCLK_R10", + "CLK_HROW_R_CK_GCLK9", + "CLK_HROW_WR1END0_7", + "CLK_HROW_IMUX2_2", + "CLK_HROW_FAN3_3", + "CLK_HROW_IMUX4_6", + "CLK_HROW_LOGIC_OUTS_B16_4", + "CLK_HROW_CK_GCLK_IN_TEST7", + "CLK_HROW_LOGIC_OUTS_B3_2", + "CLK_HROW_EL1BEG1_5", + "CLK_HROW_IMUX32_4", + "CLK_HROW_EE4C3_1", + "CLK_HROW_IMUX17_6", + "CLK_HROW_IMUX36_3", + "CLK_HROW_LH4_5", + "CLK_HROW_IMUX7_5", + "CLK_HROW_LOGIC_OUTS_B2_2", + "CLK_HROW_IMUX20_4", + "CLK_HROW_SE4C3_1", + "CLK_HROW_BUFHCE_CE_R3", + "CLK_HROW_FAN4_3", + "CLK_HROW_LOGIC_OUTS_B14_2", + "CLK_HROW_FAN0_2", + "CLK_HROW_WW4A2_0", + "CLK_HROW_CK_INT_1_1", + "CLK_HROW_CK_IN_L6", + "CLK_HROW_LOGIC_OUTS_B11_5", + "CLK_HROW_NE4C2_6", + "CLK_HROW_SE2A1_4", + "CLK_HROW_CK_HCLK_OUT_L11", + "CLK_HROW_IMUX16_6", + "CLK_HROW_BYP6_6", + "CLK_HROW_NE4BEG1_4", + "CLK_HROW_NE2A2_0", + "CLK_HROW_SE2A3_7", + "CLK_HROW_IMUX33_6", + "CLK_HROW_CK_IN_L13", + "CLK_HROW_EE4C1_6", + "CLK_HROW_WL1END1_6", + "CLK_HROW_R_CK_GCLK12", + "CLK_HROW_NW4A1_7", + "CLK_HROW_LOGIC_OUTS_B3_1", + "CLK_HROW_LOGIC_OUTS_B3_0", + "CLK_HROW_NE4C3_3", + "CLK_HROW_SW4A3_0", + "CLK_HROW_CK_MUX_OUT_R10", + "CLK_HROW_BLOCK_OUTS_B1_5", + "CLK_HROW_LOGIC_OUTS_B18_0", + "CLK_HROW_LH3_7", + "CLK_HROW_IMUX35_0", + "CLK_HROW_LOGIC_OUTS_B15_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN5", + "CLK_HROW_IMUX36_7", + "CLK_HROW_NE4BEG3_0", + "CLK_HROW_R_CK_GCLK1", + "CLK_HROW_IMUX47_3", + "CLK_HROW_CK_GCLK_OUT_TEST27", + "CLK_HROW_SE4BEG0_1", + "CLK_HROW_SW2A1_4", + "CLK_HROW_EE4C1_4", + "CLK_HROW_BYP3_5", + "CLK_HROW_WR1END2_2", + "CLK_HROW_CK_HCLK_OUT_L5", + "CLK_HROW_EE4A3_2", + "CLK_HROW_NW4END1_4", + "CLK_HROW_FAN3_6", + "CLK_HROW_LOGIC_OUTS_B22_6", + "CLK_HROW_EE2BEG0_1", + "CLK_HROW_WW2END1_2", + "CLK_HROW_NE4BEG0_0", + "CLK_HROW_EE4B2_5", + "CLK_HROW_CK_MUX_OUT_R9", + "CLK_HROW_CK_GCLK_TEST_OUT8", + "CLK_HROW_EE4B1_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "CLK_HROW_NE2A1_1", + "CLK_HROW_CK_GCLK_IN_TEST30", + "CLK_HROW_NE4C3_0", + "CLK_HROW_EE4C2_1", + "CLK_HROW_CK_HCLK_OUT_L8", + "CLK_HROW_LOGIC_OUTS_B0_3", + "CLK_HROW_NW2A0_4", + "CLK_HROW_R_CK_GCLK7", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN26", + "CLK_HROW_LOGIC_OUTS_B8_0", + "CLK_HROW_SE4BEG1_7", + "CLK_HROW_CE_INT_TOP1", + "CLK_HROW_IMUX1_1" + ], + "pips": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX11_3->CLK_HROW_CE_INT_BOT11": { + "src_wire": "CLK_HROW_IMUX11_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX9_3->CLK_HROW_CE_INT_BOT9": { + "src_wire": "CLK_HROW_IMUX9_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R9->>CLK_HROW_CK_BUFHCLK_R9": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST15->CLK_HROW_CK_GCLK_TEST_IN15": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT26->CLK_HROW_CK_GCLK_OUT_TEST26": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST14->CLK_HROW_CK_GCLK_TEST_IN14": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L9->>CLK_HROW_CK_BUFHCLK_L9": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST10->CLK_HROW_CK_GCLK_TEST_IN10": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R3->>CLK_HROW_CK_HCLK_OUT_R3": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT11->>CLK_HROW_BUFHCE_CE_L5": { + "src_wire": "CLK_HROW_CE_INT_BOT11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP2->>CLK_HROW_BUFHCE_CE_L8": { + "src_wire": "CLK_HROW_CE_INT_TOP2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT12->CLK_HROW_CK_GCLK_OUT_TEST12": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R10->>CLK_HROW_CK_HCLK_OUT_R10": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L5->>CLK_HROW_CK_BUFHCLK_L5": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST13->CLK_HROW_CK_GCLK_TEST_IN13": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST19->CLK_HROW_CK_GCLK_TEST_IN19": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT11->CLK_HROW_CK_GCLK_OUT_TEST11": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX5_3->CLK_HROW_CE_INT_BOT5": { + "src_wire": "CLK_HROW_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST24->CLK_HROW_CK_GCLK_TEST_IN24": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT31->CLK_HROW_CK_GCLK_OUT_TEST31": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP6->>CLK_HROW_BUFHCE_CE_R6": { + "src_wire": "CLK_HROW_CE_INT_TOP6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN20->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST7->CLK_HROW_CK_GCLK_TEST_IN7": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP8->>CLK_HROW_BUFHCE_CE_R8": { + "src_wire": "CLK_HROW_CE_INT_TOP8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L6->>CLK_HROW_CK_BUFHCLK_L6": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R7->>CLK_HROW_CK_BUFHCLK_R7": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_OUT_TEST->CLK_HROW_CK_IN_R_TEST_OUT": { + "src_wire": "CLK_HROW_CK_IN_R_OUT_TEST", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_R_TEST_OUT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX2_4->CLK_HROW_CE_INT_TOP2": { + "src_wire": "CLK_HROW_IMUX2_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R5->>CLK_HROW_CK_BUFHCLK_R5": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L5->>CLK_HROW_CK_HCLK_OUT_L5": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX11_4->CLK_HROW_CE_INT_TOP11": { + "src_wire": "CLK_HROW_IMUX11_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX8_4->CLK_HROW_CE_INT_TOP8": { + "src_wire": "CLK_HROW_IMUX8_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT24->CLK_HROW_CK_GCLK_OUT_TEST24": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L11->>CLK_HROW_CK_HCLK_OUT_L11": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT4->CLK_HROW_CK_GCLK_OUT_TEST4": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN29->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN23->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L1->>CLK_HROW_CK_BUFHCLK_L1": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP1->>CLK_HROW_BUFHCE_CE_L7": { + "src_wire": "CLK_HROW_CE_INT_TOP1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX4_4->CLK_HROW_CE_INT_TOP4": { + "src_wire": "CLK_HROW_IMUX4_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R10->>CLK_HROW_CK_BUFHCLK_R10": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L10->>CLK_HROW_CK_HCLK_OUT_L10": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT10->>CLK_HROW_BUFHCE_CE_L4": { + "src_wire": "CLK_HROW_CE_INT_BOT10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN19->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN28->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST28->CLK_HROW_CK_GCLK_TEST_IN28": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT9->CLK_HROW_CK_GCLK_OUT_TEST9": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN17->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX5_4->CLK_HROW_CE_INT_TOP5": { + "src_wire": "CLK_HROW_IMUX5_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT6->CLK_HROW_CK_GCLK_OUT_TEST6": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT7->CLK_HROW_CK_GCLK_OUT_TEST7": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L0->>CLK_HROW_CK_HCLK_OUT_L0": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN14->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L8->>CLK_HROW_CK_HCLK_OUT_L8": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST6->CLK_HROW_CK_GCLK_TEST_IN6": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT19->CLK_HROW_CK_GCLK_OUT_TEST19": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN26->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT4->>CLK_HROW_BUFHCE_CE_R4": { + "src_wire": "CLK_HROW_CE_INT_BOT4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT9->>CLK_HROW_BUFHCE_CE_L3": { + "src_wire": "CLK_HROW_CE_INT_BOT9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP4->>CLK_HROW_BUFHCE_CE_L10": { + "src_wire": "CLK_HROW_CE_INT_TOP4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP11->>CLK_HROW_BUFHCE_CE_R11": { + "src_wire": "CLK_HROW_CE_INT_TOP11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT10->CLK_HROW_CK_GCLK_OUT_TEST10": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT18->CLK_HROW_CK_GCLK_OUT_TEST18": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP3->>CLK_HROW_BUFHCE_CE_L9": { + "src_wire": "CLK_HROW_CE_INT_TOP3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R0->>CLK_HROW_CK_HCLK_OUT_R0": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L8->>CLK_HROW_CK_BUFHCLK_L8": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT27->CLK_HROW_CK_GCLK_OUT_TEST27": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN24->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT21->CLK_HROW_CK_GCLK_OUT_TEST21": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST26->CLK_HROW_CK_GCLK_TEST_IN26": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L7->>CLK_HROW_CK_HCLK_OUT_L7": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST20->CLK_HROW_CK_GCLK_TEST_IN20": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CLK1_3->CLK_HROW_CK_INT_0_1": { + "src_wire": "CLK_HROW_CLK1_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP0->>CLK_HROW_BUFHCE_CE_L6": { + "src_wire": "CLK_HROW_CE_INT_TOP0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L11->>CLK_HROW_CK_BUFHCLK_L11": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R6->>CLK_HROW_CK_HCLK_OUT_R6": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT16->CLK_HROW_CK_GCLK_OUT_TEST16": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT3->CLK_HROW_CK_GCLK_OUT_TEST3": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R8->>CLK_HROW_CK_HCLK_OUT_R8": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R11->>CLK_HROW_CK_BUFHCLK_R11": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT17->CLK_HROW_CK_GCLK_OUT_TEST17": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST31->CLK_HROW_CK_GCLK_TEST_IN31": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT30->CLK_HROW_CK_GCLK_OUT_TEST30": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_TEST_IN->CLK_HROW_CK_IN_R_IN_TEST": { + "src_wire": "CLK_HROW_CK_IN_R_TEST_IN", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_R_IN_TEST", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L3->>CLK_HROW_CK_HCLK_OUT_L3": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L4->>CLK_HROW_CK_BUFHCLK_L4": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX7_3->CLK_HROW_CE_INT_BOT7": { + "src_wire": "CLK_HROW_IMUX7_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT20->CLK_HROW_CK_GCLK_OUT_TEST20": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L2->>CLK_HROW_CK_HCLK_OUT_L2": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX2_3->CLK_HROW_CE_INT_BOT2": { + "src_wire": "CLK_HROW_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST5->CLK_HROW_CK_GCLK_TEST_IN5": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX7_4->CLK_HROW_CE_INT_TOP7": { + "src_wire": "CLK_HROW_IMUX7_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT5->CLK_HROW_CK_GCLK_OUT_TEST5": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN15->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT25->CLK_HROW_CK_GCLK_OUT_TEST25": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP10->>CLK_HROW_BUFHCE_CE_R10": { + "src_wire": "CLK_HROW_CE_INT_TOP10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST29->CLK_HROW_CK_GCLK_TEST_IN29": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L2->>CLK_HROW_CK_BUFHCLK_L2": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT6->>CLK_HROW_BUFHCE_CE_L0": { + "src_wire": "CLK_HROW_CE_INT_BOT6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN16->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST17->CLK_HROW_CK_GCLK_TEST_IN17": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT28->CLK_HROW_CK_GCLK_OUT_TEST28": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN27->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX0_3->CLK_HROW_CE_INT_BOT0": { + "src_wire": "CLK_HROW_IMUX0_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT23->CLK_HROW_CK_GCLK_OUT_TEST23": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R3->>CLK_HROW_CK_BUFHCLK_R3": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST18->CLK_HROW_CK_GCLK_TEST_IN18": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX0_4->CLK_HROW_CE_INT_TOP0": { + "src_wire": "CLK_HROW_IMUX0_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT14->CLK_HROW_CK_GCLK_OUT_TEST14": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT8->>CLK_HROW_BUFHCE_CE_L2": { + "src_wire": "CLK_HROW_CE_INT_BOT8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX1_4->CLK_HROW_CE_INT_TOP1": { + "src_wire": "CLK_HROW_IMUX1_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT0->>CLK_HROW_BUFHCE_CE_R0": { + "src_wire": "CLK_HROW_CE_INT_BOT0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L6->>CLK_HROW_CK_HCLK_OUT_L6": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP9->>CLK_HROW_BUFHCE_CE_R9": { + "src_wire": "CLK_HROW_CE_INT_TOP9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT22->CLK_HROW_CK_GCLK_OUT_TEST22": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN18->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT3->>CLK_HROW_BUFHCE_CE_R3": { + "src_wire": "CLK_HROW_CE_INT_BOT3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R4->>CLK_HROW_CK_HCLK_OUT_R4": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST9->CLK_HROW_CK_GCLK_TEST_IN9": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST27->CLK_HROW_CK_GCLK_TEST_IN27": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP7->>CLK_HROW_BUFHCE_CE_R7": { + "src_wire": "CLK_HROW_CE_INT_TOP7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST2->CLK_HROW_CK_GCLK_TEST_IN2": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT7->>CLK_HROW_BUFHCE_CE_L1": { + "src_wire": "CLK_HROW_CE_INT_BOT7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX8_3->CLK_HROW_CE_INT_BOT8": { + "src_wire": "CLK_HROW_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX9_4->CLK_HROW_CE_INT_TOP9": { + "src_wire": "CLK_HROW_IMUX9_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN30->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN25->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L3->>CLK_HROW_CK_BUFHCLK_L3": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST23->CLK_HROW_CK_GCLK_TEST_IN23": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R8->>CLK_HROW_CK_BUFHCLK_R8": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST16->CLK_HROW_CK_GCLK_TEST_IN16": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT2->CLK_HROW_CK_GCLK_OUT_TEST2": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT1->CLK_HROW_CK_GCLK_OUT_TEST1": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST4->CLK_HROW_CK_GCLK_TEST_IN4": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX1_3->CLK_HROW_CE_INT_BOT1": { + "src_wire": "CLK_HROW_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CLK0_3->CLK_HROW_CK_INT_0_0": { + "src_wire": "CLK_HROW_CLK0_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L0->>CLK_HROW_CK_BUFHCLK_L0": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX3_4->CLK_HROW_CE_INT_TOP3": { + "src_wire": "CLK_HROW_IMUX3_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R2->>CLK_HROW_CK_BUFHCLK_R2": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT0->CLK_HROW_CK_GCLK_OUT_TEST0": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L9->>CLK_HROW_CK_HCLK_OUT_L9": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST25->CLK_HROW_CK_GCLK_TEST_IN25": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R7->>CLK_HROW_CK_HCLK_OUT_R7": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST11->CLK_HROW_CK_GCLK_TEST_IN11": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L1->>CLK_HROW_CK_HCLK_OUT_L1": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_TEST_IN->CLK_HROW_CK_IN_L_IN_TEST": { + "src_wire": "CLK_HROW_CK_IN_L_TEST_IN", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_L_IN_TEST", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L10->>CLK_HROW_CK_BUFHCLK_L10": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R11->>CLK_HROW_CK_HCLK_OUT_R11": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX10_3->CLK_HROW_CE_INT_BOT10": { + "src_wire": "CLK_HROW_IMUX10_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX6_4->CLK_HROW_CE_INT_TOP6": { + "src_wire": "CLK_HROW_IMUX6_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R9->>CLK_HROW_CK_HCLK_OUT_R9": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN31->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT29->CLK_HROW_CK_GCLK_OUT_TEST29": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R2->>CLK_HROW_CK_HCLK_OUT_R2": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST8->CLK_HROW_CK_GCLK_TEST_IN8": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R4->>CLK_HROW_CK_BUFHCLK_R4": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT2->>CLK_HROW_BUFHCE_CE_R2": { + "src_wire": "CLK_HROW_CE_INT_BOT2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX6_3->CLK_HROW_CE_INT_BOT6": { + "src_wire": "CLK_HROW_IMUX6_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN22->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST30->CLK_HROW_CK_GCLK_TEST_IN30": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST3->CLK_HROW_CK_GCLK_TEST_IN3": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT8->CLK_HROW_CK_GCLK_OUT_TEST8": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT15->CLK_HROW_CK_GCLK_OUT_TEST15": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L4->>CLK_HROW_CK_HCLK_OUT_L4": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX4_3->CLK_HROW_CE_INT_BOT4": { + "src_wire": "CLK_HROW_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT5->>CLK_HROW_BUFHCE_CE_R5": { + "src_wire": "CLK_HROW_CE_INT_BOT5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT13->CLK_HROW_CK_GCLK_OUT_TEST13": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R0->>CLK_HROW_CK_BUFHCLK_R0": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX3_3->CLK_HROW_CE_INT_BOT3": { + "src_wire": "CLK_HROW_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R1->>CLK_HROW_CK_HCLK_OUT_R1": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L7->>CLK_HROW_CK_BUFHCLK_L7": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN21->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST1->CLK_HROW_CK_GCLK_TEST_IN1": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R6->>CLK_HROW_CK_BUFHCLK_R6": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CLK0_4->CLK_HROW_CK_INT_1_0": { + "src_wire": "CLK_HROW_CLK0_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R5->>CLK_HROW_CK_HCLK_OUT_R5": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST0->CLK_HROW_CK_GCLK_TEST_IN0": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT1->>CLK_HROW_BUFHCE_CE_R1": { + "src_wire": "CLK_HROW_CE_INT_BOT1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_OUT_TEST->CLK_HROW_CK_IN_L_TEST_OUT": { + "src_wire": "CLK_HROW_CK_IN_L_OUT_TEST", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_L_TEST_OUT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R1->>CLK_HROW_CK_BUFHCLK_R1": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST21->CLK_HROW_CK_GCLK_TEST_IN21": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST12->CLK_HROW_CK_GCLK_TEST_IN12": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST22->CLK_HROW_CK_GCLK_TEST_IN22": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX10_4->CLK_HROW_CE_INT_TOP10": { + "src_wire": "CLK_HROW_IMUX10_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP5->>CLK_HROW_BUFHCE_CE_L11": { + "src_wire": "CLK_HROW_CE_INT_TOP5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CLK1_4->CLK_HROW_CK_INT_1_1": { + "src_wire": "CLK_HROW_CLK1_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CLK_HROW_TOP_R.json b/kintex7/tile_type_CLK_HROW_TOP_R.json new file mode 100644 index 0000000..d1eab20 --- /dev/null +++ b/kintex7/tile_type_CLK_HROW_TOP_R.json @@ -0,0 +1,22381 @@ +{ + "tile_type": "CLK_HROW_TOP_R", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L0", + "O": "CLK_HROW_CK_HCLK_OUT_L0", + "I": "CLK_HROW_CK_MUX_OUT_L0" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L1", + "O": "CLK_HROW_CK_HCLK_OUT_L1", + "I": "CLK_HROW_CK_MUX_OUT_L1" + }, + "x_coord": 0 + }, + { + "y_coord": 2, + "name": "X0Y2", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L2", + "O": "CLK_HROW_CK_HCLK_OUT_L2", + "I": "CLK_HROW_CK_MUX_OUT_L2" + }, + "x_coord": 0 + }, + { + "y_coord": 3, + "name": "X0Y3", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L3", + "O": "CLK_HROW_CK_HCLK_OUT_L3", + "I": "CLK_HROW_CK_MUX_OUT_L3" + }, + "x_coord": 0 + }, + { + "y_coord": 4, + "name": "X0Y4", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L4", + "O": "CLK_HROW_CK_HCLK_OUT_L4", + "I": "CLK_HROW_CK_MUX_OUT_L4" + }, + "x_coord": 0 + }, + { + "y_coord": 5, + "name": "X0Y5", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L5", + "O": "CLK_HROW_CK_HCLK_OUT_L5", + "I": "CLK_HROW_CK_MUX_OUT_L5" + }, + "x_coord": 0 + }, + { + "y_coord": 6, + "name": "X0Y6", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L6", + "O": "CLK_HROW_CK_HCLK_OUT_L6", + "I": "CLK_HROW_CK_MUX_OUT_L6" + }, + "x_coord": 0 + }, + { + "y_coord": 7, + "name": "X0Y7", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L7", + "O": "CLK_HROW_CK_HCLK_OUT_L7", + "I": "CLK_HROW_CK_MUX_OUT_L7" + }, + "x_coord": 0 + }, + { + "y_coord": 8, + "name": "X0Y8", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L8", + "O": "CLK_HROW_CK_HCLK_OUT_L8", + "I": "CLK_HROW_CK_MUX_OUT_L8" + }, + "x_coord": 0 + }, + { + "y_coord": 9, + "name": "X0Y9", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L9", + "O": "CLK_HROW_CK_HCLK_OUT_L9", + "I": "CLK_HROW_CK_MUX_OUT_L9" + }, + "x_coord": 0 + }, + { + "y_coord": 10, + "name": "X0Y10", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L10", + "O": "CLK_HROW_CK_HCLK_OUT_L10", + "I": "CLK_HROW_CK_MUX_OUT_L10" + }, + "x_coord": 0 + }, + { + "y_coord": 11, + "name": "X0Y11", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_L11", + "O": "CLK_HROW_CK_HCLK_OUT_L11", + "I": "CLK_HROW_CK_MUX_OUT_L11" + }, + "x_coord": 0 + }, + { + "y_coord": 11, + "name": "X1Y11", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R11", + "O": "CLK_HROW_CK_HCLK_OUT_R11", + "I": "CLK_HROW_CK_MUX_OUT_R11" + }, + "x_coord": 1 + }, + { + "y_coord": 10, + "name": "X1Y10", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R10", + "O": "CLK_HROW_CK_HCLK_OUT_R10", + "I": "CLK_HROW_CK_MUX_OUT_R10" + }, + "x_coord": 1 + }, + { + "y_coord": 9, + "name": "X1Y9", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R9", + "O": "CLK_HROW_CK_HCLK_OUT_R9", + "I": "CLK_HROW_CK_MUX_OUT_R9" + }, + "x_coord": 1 + }, + { + "y_coord": 8, + "name": "X1Y8", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R8", + "O": "CLK_HROW_CK_HCLK_OUT_R8", + "I": "CLK_HROW_CK_MUX_OUT_R8" + }, + "x_coord": 1 + }, + { + "y_coord": 7, + "name": "X1Y7", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R7", + "O": "CLK_HROW_CK_HCLK_OUT_R7", + "I": "CLK_HROW_CK_MUX_OUT_R7" + }, + "x_coord": 1 + }, + { + "y_coord": 6, + "name": "X1Y6", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R6", + "O": "CLK_HROW_CK_HCLK_OUT_R6", + "I": "CLK_HROW_CK_MUX_OUT_R6" + }, + "x_coord": 1 + }, + { + "y_coord": 5, + "name": "X1Y5", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R5", + "O": "CLK_HROW_CK_HCLK_OUT_R5", + "I": "CLK_HROW_CK_MUX_OUT_R5" + }, + "x_coord": 1 + }, + { + "y_coord": 4, + "name": "X1Y4", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R4", + "O": "CLK_HROW_CK_HCLK_OUT_R4", + "I": "CLK_HROW_CK_MUX_OUT_R4" + }, + "x_coord": 1 + }, + { + "y_coord": 3, + "name": "X1Y3", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R3", + "O": "CLK_HROW_CK_HCLK_OUT_R3", + "I": "CLK_HROW_CK_MUX_OUT_R3" + }, + "x_coord": 1 + }, + { + "y_coord": 2, + "name": "X1Y2", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R2", + "O": "CLK_HROW_CK_HCLK_OUT_R2", + "I": "CLK_HROW_CK_MUX_OUT_R2" + }, + "x_coord": 1 + }, + { + "y_coord": 1, + "name": "X1Y1", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R1", + "O": "CLK_HROW_CK_HCLK_OUT_R1", + "I": "CLK_HROW_CK_MUX_OUT_R1" + }, + "x_coord": 1 + }, + { + "y_coord": 0, + "name": "X1Y0", + "prefix": "BUFHCE", + "type": "BUFHCE", + "site_pins": { + "CE": "CLK_HROW_BUFHCE_CE_R0", + "O": "CLK_HROW_CK_HCLK_OUT_R0", + "I": "CLK_HROW_CK_MUX_OUT_R0" + }, + "x_coord": 1 + } + ], + "wires": [ + "CLK_HROW_SE4C3_2", + "CLK_HROW_CK_MUX_OUT_R3", + "CLK_HROW_LOGIC_OUTS_B20_5", + "CLK_HROW_CK_IN_R5", + "CLK_HROW_FAN0_3", + "CLK_HROW_NW4END1_7", + "CLK_HROW_EL1BEG3_6", + "CLK_HROW_CK_GCLK_TEST_IN29", + "CLK_HROW_LH4_4", + "CLK_HROW_CK_GCLK_TEST_OUT0", + "CLK_HROW_WW2A3_6", + "CLK_HROW_WW4END3_5", + "CLK_HROW_BYP4_2", + "CLK_HROW_EE4A0_4", + "CLK_HROW_MONITOR_N_2", + "CLK_HROW_LH3_4", + "CLK_HROW_CK_IN_R_TEST_OUT", + "CLK_HROW_CK_GCLK_TEST_IN11", + "CLK_HROW_CK_GCLK_TEST10", + "CLK_HROW_LH9_1", + "CLK_HROW_NW2A1_0", + "CLK_HROW_WW2A3_1", + "CLK_HROW_CK_IN_L_TEST_IN", + "CLK_HROW_NW4END1_1", + "CLK_HROW_WR1END3_1", + "CLK_HROW_R_CK_GCLK16", + "CLK_HROW_CK_IN_R_IN_TEST", + "CLK_HROW_CK_GCLK_IN_TEST14", + "CLK_HROW_CE_INT_TOP5", + "CLK_HROW_CK_GCLK_TEST_OUT18", + "CLK_HROW_SE4BEG2_0", + "CLK_HROW_CK_GCLK_TEST_OUT7", + "CLK_HROW_CK_GCLK_OUT_TEST26", + "CLK_HROW_WW2A1_0", + "CLK_HROW_BLOCK_OUTS_B2_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "CLK_HROW_SE4BEG1_1", + "CLK_HROW_WW4C3_3", + "CLK_HROW_EE4BEG0_7", + "CLK_HROW_WW2A2_7", + "CLK_HROW_LOGIC_OUTS_B2_3", + "CLK_HROW_WW4END2_7", + "CLK_HROW_IMUX25_3", + "CLK_HROW_ER1BEG0_7", + "CLK_HROW_NE4C2_2", + "CLK_HROW_IMUX42_0", + "CLK_HROW_BLOCK_OUTS_B0_2", + "CLK_HROW_IMUX46_2", + "CLK_HROW_IMUX43_5", + "CLK_HROW_WL1END2_1", + "CLK_HROW_NE4C2_0", + "CLK_HROW_LH5_3", + "CLK_HROW_NE2A1_0", + "CLK_HROW_SW4END1_3", + "CLK_HROW_NW4A1_0", + "CLK_HROW_EE4B0_5", + "CLK_HROW_LH6_7", + "CLK_HROW_IMUX30_6", + "CLK_HROW_LH2_4", + "CLK_HROW_SW2A3_3", + "CLK_HROW_IMUX36_6", + "CLK_HROW_CK_INT_1_0", + "CLK_HROW_LOGIC_OUTS_B3_5", + "CLK_HROW_LOGIC_OUTS_B11_4", + "CLK_HROW_CK_GCLK_TEST_IN5", + "CLK_HROW_CK_GCLK_OUT_TEST8", + "CLK_HROW_SW4END1_4", + "CLK_HROW_LH5_0", + "CLK_HROW_LOGIC_OUTS_B22_7", + "CLK_HROW_CK_IN_R11", + "CLK_HROW_NE4BEG2_7", + "CLK_HROW_CK_BUFRCLK_R3", + "CLK_HROW_IMUX37_1", + "CLK_HROW_WL1END0_5", + "CLK_HROW_SE4C2_1", + "CLK_HROW_CE_INT_TOP11", + "CLK_HROW_CK_GCLK_IN_TEST29", + "CLK_HROW_BLOCK_OUTS_B1_4", + "CLK_HROW_IMUX21_7", + "CLK_HROW_MONITOR_N_7", + "CLK_HROW_LOGIC_OUTS_B2_6", + "CLK_HROW_CK_GCLK_IN_TEST9", + "CLK_HROW_WW2A3_2", + "CLK_HROW_NE4BEG1_1", + "CLK_HROW_LH10_3", + "CLK_HROW_IMUX32_1", + "CLK_HROW_LOGIC_OUTS_B17_6", + "CLK_HROW_IMUX18_4", + "CLK_HROW_CE_INT_BOT8", + "CLK_HROW_SW4END1_7", + "CLK_HROW_NW4END1_2", + "CLK_HROW_WW2END0_0", + "CLK_HROW_WW2END1_6", + "CLK_HROW_LOGIC_OUTS_B4_1", + "CLK_HROW_CK_IN_L_OUT_TEST", + "CLK_HROW_CK_GCLK_TEST_IN7", + "CLK_HROW_SE4C0_5", + "CLK_HROW_ER1BEG2_2", + "CLK_HROW_WR1END1_4", + "CLK_HROW_NW4A1_3", + "CLK_HROW_FAN5_6", + "CLK_HROW_CK_BUFHCLK_R8", + "CLK_HROW_IMUX16_5", + "CLK_HROW_CK_GCLK_OUT_TEST5", + "CLK_HROW_WR1END2_4", + "CLK_HROW_CK_GCLK_TEST_OUT3", + "CLK_HROW_CK_MUX_OUT_L1", + "CLK_HROW_FAN2_1", + "CLK_HROW_IMUX31_4", + "CLK_HROW_LOGIC_OUTS_B12_4", + "CLK_HROW_WW4C0_6", + "CLK_HROW_NW2A3_0", + "CLK_HROW_LOGIC_OUTS_B12_7", + "CLK_HROW_LOGIC_OUTS_B10_6", + "CLK_HROW_ER1BEG2_5", + "CLK_HROW_SE4C3_3", + "CLK_HROW_SE4C2_6", + "CLK_HROW_CK_GCLK_TEST_OUT14", + "CLK_HROW_SE4C0_0", + "CLK_HROW_LOGIC_OUTS_B12_3", + "CLK_HROW_IMUX8_3", + "CLK_HROW_SW2A1_7", + "CLK_HROW_WR1END3_6", + "CLK_HROW_SE4BEG2_1", + "CLK_HROW_EE2A3_3", + "CLK_HROW_SE2A3_2", + "CLK_HROW_IMUX22_1", + "CLK_HROW_CE_INT_BOT0", + "CLK_HROW_IMUX38_2", + "CLK_HROW_NW4A0_6", + "CLK_HROW_EL1BEG3_3", + "CLK_HROW_LH8_7", + "CLK_HROW_LH10_5", + "CLK_HROW_LOGIC_OUTS_B5_1", + "CLK_HROW_SE2A2_0", + "CLK_HROW_WW4END3_0", + "CLK_HROW_CK_IN_R1", + "CLK_HROW_SE2A0_4", + "CLK_HROW_CK_GCLK_TEST9", + "CLK_HROW_LH9_2", + "CLK_HROW_CK_GCLK_TEST_OUT21", + "CLK_HROW_CK_MUX_OUT_L11", + "CLK_HROW_CE_INT_BOT1", + "CLK_HROW_LOGIC_OUTS_B21_3", + "CLK_HROW_CK_HCLK_OUT_L9", + "CLK_HROW_BYP1_3", + "CLK_HROW_SW2A1_6", + "CLK_HROW_LOGIC_OUTS_B6_0", + "CLK_HROW_CK_GCLK_OUT_TEST0", + "CLK_HROW_SW4END3_0", + "CLK_HROW_NE2A0_3", + "CLK_HROW_CE_INT_BOT7", + "CLK_HROW_NE4C1_4", + "CLK_HROW_LOGIC_OUTS_B9_2", + "CLK_HROW_WW4C2_0", + "CLK_HROW_CK_HCLK_OUT_L2", + "CLK_HROW_LOGIC_OUTS_B7_7", + "CLK_HROW_SW2A2_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "CLK_HROW_CK_GCLK_TEST24", + "CLK_HROW_CK_IN_L_IN_TEST", + "CLK_HROW_IMUX37_3", + "CLK_HROW_CE_INT_TOP3", + "CLK_HROW_LOGIC_OUTS_B17_0", + "CLK_HROW_CK_GCLK_TEST_IN12", + "CLK_HROW_IMUX2_0", + "CLK_HROW_EE4A0_5", + "CLK_HROW_NW4END0_2", + "CLK_HROW_IMUX15_0", + "CLK_HROW_CK_GCLK_TEST_IN4", + "CLK_HROW_EE2BEG1_7", + "CLK_HROW_BUFHCE_CE_L3", + "CLK_HROW_WW4C0_7", + "CLK_HROW_NE2A2_3", + "CLK_HROW_SW4A3_4", + "CLK_HROW_EL1BEG0_2", + "CLK_HROW_SE4C2_4", + "CLK_HROW_ER1BEG0_4", + "CLK_HROW_IMUX15_4", + "CLK_HROW_EE4B2_6", + "CLK_HROW_SW4A2_6", + "CLK_HROW_SW4A1_4", + "CLK_HROW_WL1END0_4", + "CLK_HROW_IMUX46_1", + "CLK_HROW_FAN7_1", + "CLK_HROW_SW4A3_5", + "CLK_HROW_EE4BEG2_0", + "CLK_HROW_EE2A3_1", + "CLK_HROW_LOGIC_OUTS_B13_2", + "CLK_HROW_BUFHCE_CE_L0", + "CLK_HROW_IMUX16_3", + "CLK_HROW_IMUX27_0", + "CLK_HROW_IMUX20_6", + "CLK_HROW_SW2A1_1", + "CLK_HROW_IMUX23_0", + "CLK_HROW_R_CK_GCLK20", + "CLK_HROW_BYP1_1", + "CLK_HROW_WW4C1_2", + "CLK_HROW_SW2A2_5", + "CLK_HROW_BYP0_3", + "CLK_HROW_CK_GCLK_TEST_IN6", + "CLK_HROW_CK_GCLK_TEST11", + "CLK_HROW_CK_GCLK_OUT_TEST2", + "CLK_HROW_R_CK_GCLK24", + "CLK_HROW_IMUX3_0", + "CLK_HROW_CK_IN_L11", + "CLK_HROW_IMUX28_3", + "CLK_HROW_IMUX27_4", + "CLK_HROW_IMUX15_5", + "CLK_HROW_SW4END1_2", + "CLK_HROW_BUFHCE_CE_L9", + "CLK_HROW_CE_INT_BOT10", + "CLK_HROW_EE4B3_7", + "CLK_HROW_EE2BEG3_2", + "CLK_HROW_IMUX4_7", + "CLK_HROW_IMUX38_3", + "CLK_HROW_WW2END2_5", + "CLK_HROW_WW2A0_2", + "CLK_HROW_CK_GCLK_TEST_OUT4", + "CLK_HROW_SW4END1_1", + "CLK_HROW_CK_IN_R2", + "CLK_HROW_FAN1_7", + "CLK_HROW_WW4C1_1", + "CLK_HROW_CK_GCLK_OUT_TEST15", + "CLK_HROW_IMUX43_3", + "CLK_HROW_EE4BEG3_6", + "CLK_HROW_CK_GCLK_IN_TEST16", + "CLK_HROW_LOGIC_OUTS_B18_4", + "CLK_HROW_SW4END3_2", + "CLK_HROW_EE4A2_7", + "CLK_HROW_CK_GCLK_TEST_IN25", + "CLK_HROW_LOGIC_OUTS_B18_3", + "CLK_HROW_SE2A1_2", + "CLK_HROW_EE2BEG1_2", + "CLK_HROW_IMUX8_7", + "CLK_HROW_LH9_3", + "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "CLK_HROW_NW2A3_4", + "CLK_HROW_LOGIC_OUTS_B11_6", + "CLK_HROW_CK_GCLK_TEST0", + "CLK_HROW_EE4BEG0_3", + "CLK_HROW_EE4B1_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN9", + "CLK_HROW_WW4B1_5", + "CLK_HROW_WW2A0_7", + "CLK_HROW_WW4C0_1", + "CLK_HROW_EE4B2_1", + "CLK_HROW_CK_BUFHCLK_L5", + "CLK_HROW_NE4BEG2_0", + "CLK_HROW_LOGIC_OUTS_B2_1", + "CLK_HROW_CE_INT_BOT4", + "CLK_HROW_EE4BEG0_4", + "CLK_HROW_FAN6_3", + "CLK_HROW_R_CK_GCLK23", + "CLK_HROW_LOGIC_OUTS_B1_7", + "CLK_HROW_EE4A2_4", + "CLK_HROW_NE4BEG2_5", + "CLK_HROW_LOGIC_OUTS_B3_6", + "CLK_HROW_LOGIC_OUTS_B15_2", + "CLK_HROW_IMUX10_2", + "CLK_HROW_CK_HCLK_OUT_R11", + "CLK_HROW_FAN6_1", + "CLK_HROW_LOGIC_OUTS_B15_4", + "CLK_HROW_IMUX4_0", + "CLK_HROW_R_CK_GCLK26", + "CLK_HROW_WW4C3_7", + "CLK_HROW_LOGIC_OUTS_B17_1", + "CLK_HROW_IMUX10_3", + "CLK_HROW_CK_GCLK_TEST30", + "CLK_HROW_SW4A1_6", + "CLK_HROW_IMUX6_0", + "CLK_HROW_EL1BEG1_1", + "CLK_HROW_LH2_3", + "CLK_HROW_WW4B3_0", + "CLK_HROW_LOGIC_OUTS_B8_2", + "CLK_HROW_IMUX27_3", + "CLK_HROW_EE2BEG2_7", + "CLK_HROW_IMUX12_5", + "CLK_HROW_BLOCK_OUTS_B1_7", + "CLK_HROW_CE_INT_BOT6", + "CLK_HROW_WW4END1_3", + "CLK_HROW_IMUX7_4", + "CLK_HROW_EE2BEG1_0", + "CLK_HROW_LOGIC_OUTS_B9_3", + "CLK_HROW_WL1END3_7", + "CLK_HROW_NW4END0_0", + "CLK_HROW_SE2A2_1", + "CLK_HROW_EE2BEG3_7", + "CLK_HROW_LH6_5", + "CLK_HROW_EE4BEG2_5", + "CLK_HROW_IMUX13_1", + "CLK_HROW_SE4BEG3_4", + "CLK_HROW_ER1BEG1_5", + "CLK_HROW_LH8_1", + "CLK_HROW_SE4C3_6", + "CLK_HROW_IMUX34_2", + "CLK_HROW_IMUX21_3", + "CLK_HROW_LOGIC_OUTS_B15_1", + "CLK_HROW_LOGIC_OUTS_B8_1", + "CLK_HROW_NW4A2_1", + "CLK_HROW_ER1BEG0_1", + "CLK_HROW_SE2A3_5", + "CLK_HROW_EE2BEG3_3", + "CLK_HROW_NW4END3_6", + "CLK_HROW_WW2A1_6", + "CLK_HROW_IMUX37_7", + "CLK_HROW_EE2A0_2", + "CLK_HROW_WW2A1_3", + "CLK_HROW_CK_IN_R10", + "CLK_HROW_NE4BEG3_6", + "CLK_HROW_SW4A2_7", + "CLK_HROW_CK_IN_R6", + "CLK_HROW_IMUX18_3", + "CLK_HROW_IMUX38_7", + "CLK_HROW_BUFHCE_CE_R8", + "CLK_HROW_LH2_0", + "CLK_HROW_IMUX47_4", + "CLK_HROW_WR1END2_6", + "CLK_HROW_SW4A0_4", + "CLK_HROW_NW2A1_4", + "CLK_HROW_LOGIC_OUTS_B7_5", + "CLK_HROW_LOGIC_OUTS_B0_7", + "CLK_HROW_WL1END1_5", + "CLK_HROW_IMUX7_0", + "CLK_HROW_NE4C3_7", + "CLK_HROW_EE2A0_5", + "CLK_HROW_NW4END3_3", + "CLK_HROW_CK_BUFHCLK_R11", + "CLK_HROW_LOGIC_OUTS_B14_3", + "CLK_HROW_ER1BEG0_6", + "CLK_HROW_WW4B1_6", + "CLK_HROW_IMUX36_1", + "CLK_HROW_NE2A2_4", + "CLK_HROW_BYP6_5", + "CLK_HROW_CK_GCLK_TEST_OUT27", + "CLK_HROW_WW2END3_0", + "CLK_HROW_SW2A1_5", + "CLK_HROW_SW4END2_0", + "CLK_HROW_LOGIC_OUTS_B9_7", + "CLK_HROW_IMUX43_7", + "CLK_HROW_EE4B0_0", + "CLK_HROW_NW4A2_4", + "CLK_HROW_FAN5_2", + "CLK_HROW_NE2A1_7", + "CLK_HROW_CE_INT_BOT11", + "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "CLK_HROW_SE2A0_5", + "CLK_HROW_WR1END1_6", + "CLK_HROW_EE4C3_0", + "CLK_HROW_IMUX11_7", + "CLK_HROW_ER1BEG1_0", + "CLK_HROW_LH5_5", + "CLK_HROW_NW2A2_6", + "CLK_HROW_SE4C1_0", + "CLK_HROW_NW4A2_5", + "CLK_HROW_WR1END0_4", + "CLK_HROW_CK_GCLK_TEST_IN0", + "CLK_HROW_CK_IN_L8", + "CLK_HROW_SW4A1_0", + "CLK_HROW_WW4END1_7", + "CLK_HROW_IMUX14_5", + "CLK_HROW_CK_GCLK_TEST4", + "CLK_HROW_CK_BUFHCLK_L3", + "CLK_HROW_MONITOR_N_5", + "CLK_HROW_IMUX40_1", + "CLK_HROW_LOGIC_OUTS_B10_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN12", + "CLK_HROW_LOGIC_OUTS_B15_5", + "CLK_HROW_SW2A0_2", + "CLK_HROW_CE_INT_TOP7", + "CLK_HROW_NE4C3_1", + "CLK_HROW_EE2A3_6", + "CLK_HROW_NW2A2_1", + "CLK_HROW_IMUX27_2", + "CLK_HROW_CLK0_6", + "CLK_HROW_IMUX13_4", + "CLK_HROW_LOGIC_OUTS_B3_4", + "CLK_HROW_WW4A1_0", + "CLK_HROW_WW2END3_4", + "CLK_HROW_NW2A1_2", + "CLK_HROW_LH11_3", + "CLK_HROW_IMUX34_5", + "CLK_HROW_LOGIC_OUTS_B22_2", + "CLK_HROW_EE4A3_1", + "CLK_HROW_EL1BEG1_3", + "CLK_HROW_CK_GCLK_IN_TEST13", + "CLK_HROW_CK_GCLK_OUT_TEST7", + "CLK_HROW_BYP7_7", + "CLK_HROW_FAN3_4", + "CLK_HROW_IMUX18_0", + "CLK_HROW_SW2A0_1", + "CLK_HROW_CK_GCLK_TEST_OUT23", + "CLK_HROW_WW4A3_2", + "CLK_HROW_IMUX20_1", + "CLK_HROW_CLK0_4", + "CLK_HROW_WW2A1_5", + "CLK_HROW_EE4B2_0", + "CLK_HROW_IMUX13_2", + "CLK_HROW_CK_IN_R3", + "CLK_HROW_WW2END2_2", + "CLK_HROW_NE4C1_7", + "CLK_HROW_EE4B2_4", + "CLK_HROW_IMUX4_1", + "CLK_HROW_WW4END0_6", + "CLK_HROW_BLOCK_OUTS_B0_7", + "CLK_HROW_NW4END2_1", + "CLK_HROW_BYP6_7", + "CLK_HROW_NW2A1_6", + "CLK_HROW_NW4END0_7", + "CLK_HROW_IMUX32_6", + "CLK_HROW_BYP7_4", + "CLK_HROW_WW4B3_3", + "CLK_HROW_NE4BEG2_3", + "CLK_HROW_EE4C0_0", + "CLK_HROW_EE2BEG0_2", + "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "CLK_HROW_FAN1_3", + "CLK_HROW_LH1_2", + "CLK_HROW_CK_BUFHCLK_R5", + "CLK_HROW_CK_BUFRCLK_R2", + "CLK_HROW_SE2A3_3", + "CLK_HROW_SE4BEG3_0", + "CLK_HROW_SW4END3_4", + "CLK_HROW_WW4END1_0", + "CLK_HROW_CK_HCLK_OUT_R4", + "CLK_HROW_FAN3_0", + "CLK_HROW_ER1BEG2_7", + "CLK_HROW_IMUX5_1", + "CLK_HROW_IMUX38_1", + "CLK_HROW_IMUX33_3", + "CLK_HROW_CLK1_3", + "CLK_HROW_EE4C2_4", + "CLK_HROW_IMUX45_3", + "CLK_HROW_IMUX44_6", + "CLK_HROW_EE2BEG0_0", + "CLK_HROW_R_CK_GCLK13", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN4", + "CLK_HROW_WW4A3_0", + "CLK_HROW_BYP7_3", + "CLK_HROW_WW4C3_1", + "CLK_HROW_NE4BEG3_2", + "CLK_HROW_WW4END0_5", + "CLK_HROW_IMUX31_2", + "CLK_HROW_CK_HCLK_OUT_R7", + "CLK_HROW_WW2A2_3", + "CLK_HROW_FAN3_2", + "CLK_HROW_EE4B0_2", + "CLK_HROW_IMUX6_5", + "CLK_HROW_EE2A0_3", + "CLK_HROW_CK_GCLK_IN_TEST25", + "CLK_HROW_IMUX30_2", + "CLK_HROW_LOGIC_OUTS_B22_1", + "CLK_HROW_IMUX26_2", + "CLK_HROW_EE4A0_0", + "CLK_HROW_WW4END2_2", + "CLK_HROW_LH2_5", + "CLK_HROW_SE2A1_3", + "CLK_HROW_WW4C2_1", + "CLK_HROW_SW2A2_0", + "CLK_HROW_SE4C3_7", + "CLK_HROW_EE2BEG2_1", + "CLK_HROW_IMUX30_7", + "CLK_HROW_NW4A3_7", + "CLK_HROW_WW4B3_6", + "CLK_HROW_WW4B2_3", + "CLK_HROW_IMUX20_7", + "CLK_HROW_NW4A2_0", + "CLK_HROW_SE4BEG1_6", + "CLK_HROW_WL1END1_0", + "CLK_HROW_SE2A2_3", + "CLK_HROW_CK_GCLK_IN_TEST17", + "CLK_HROW_IMUX7_1", + "CLK_HROW_WW2A2_4", + "CLK_HROW_CK_HCLK_OUT_L1", + "CLK_HROW_WW4C3_0", + "CLK_HROW_IMUX10_5", + "CLK_HROW_CK_MUX_OUT_L5", + "CLK_HROW_BLOCK_OUTS_B0_1", + "CLK_HROW_EE4BEG2_2", + "CLK_HROW_FAN4_0", + "CLK_HROW_EE4A1_4", + "CLK_HROW_LOGIC_OUTS_B15_3", + "CLK_HROW_NW2A2_5", + "CLK_HROW_LH7_5", + "CLK_HROW_WW4A2_1", + "CLK_HROW_NW2A0_0", + "CLK_HROW_CK_GCLK_TEST_IN1", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN29", + "CLK_HROW_WW4B2_7", + "CLK_HROW_FAN5_7", + "CLK_HROW_NE4BEG1_2", + "CLK_HROW_BYP4_3", + "CLK_HROW_EL1BEG0_5", + "CLK_HROW_IMUX26_0", + "CLK_HROW_SE4BEG2_7", + "CLK_HROW_WW4END0_1", + "CLK_HROW_FAN4_4", + "CLK_HROW_EE2A2_6", + "CLK_HROW_WW2A2_6", + "CLK_HROW_IMUX16_7", + "CLK_HROW_IMUX44_2", + "CLK_HROW_EE4BEG1_3", + "CLK_HROW_WR1END3_3", + "CLK_HROW_SW4END1_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN8", + "CLK_HROW_BYP2_3", + "CLK_HROW_EE4A1_5", + "CLK_HROW_ER1BEG2_4", + "CLK_HROW_WW4END3_3", + "CLK_HROW_IMUX36_5", + "CLK_HROW_CK_GCLK_TEST_OUT9", + "CLK_HROW_BUFHCE_CE_L1", + "CLK_HROW_BYP0_0", + "CLK_HROW_IMUX39_7", + "CLK_HROW_LH3_3", + "CLK_HROW_IMUX3_7", + "CLK_HROW_EE2A1_6", + "CLK_HROW_NW2A0_1", + "CLK_HROW_NW4END3_7", + "CLK_HROW_BYP5_5", + "CLK_HROW_BYP0_4", + "CLK_HROW_CK_GCLK_TEST15", + "CLK_HROW_CK_GCLK_TEST_OUT25", + "CLK_HROW_CK_MUX_OUT_R1", + "CLK_HROW_WW4B3_7", + "CLK_HROW_LOGIC_OUTS_B9_0", + "CLK_HROW_WW4C0_0", + "CLK_HROW_WL1END0_2", + "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "CLK_HROW_WL1END2_7", + "CLK_HROW_NW4END3_5", + "CLK_HROW_SE4BEG1_5", + "CLK_HROW_SE4C0_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN13", + "CLK_HROW_WW4C0_4", + "CLK_HROW_IMUX32_2", + "CLK_HROW_LH8_0", + "CLK_HROW_WW4END0_4", + "CLK_HROW_SW4A2_4", + "CLK_HROW_IMUX46_4", + "CLK_HROW_NE2A1_2", + "CLK_HROW_NE4C3_4", + "CLK_HROW_WW4END0_3", + "CLK_HROW_BLOCK_OUTS_B0_5", + "CLK_HROW_IMUX9_7", + "CLK_HROW_WW2END2_4", + "CLK_HROW_IMUX35_6", + "CLK_HROW_SW2A0_5", + "CLK_HROW_LH12_7", + "CLK_HROW_R_CK_GCLK4", + "CLK_HROW_SE4BEG2_6", + "CLK_HROW_CK_GCLK_IN_TEST28", + "CLK_HROW_LH6_6", + "CLK_HROW_LOGIC_OUTS_B18_7", + "CLK_HROW_FAN3_7", + "CLK_HROW_WW2A0_0", + "CLK_HROW_SW2A0_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN2", + "CLK_HROW_WW2END2_6", + "CLK_HROW_IMUX30_0", + "CLK_HROW_SW4A2_1", + "CLK_HROW_R_CK_GCLK17", + "CLK_HROW_FAN0_1", + "CLK_HROW_CK_MUX_OUT_L0", + "CLK_HROW_WL1END2_3", + "CLK_HROW_WL1END1_1", + "CLK_HROW_IMUX2_5", + "CLK_HROW_CK_GCLK_OUT_TEST24", + "CLK_HROW_NW4END2_2", + "CLK_HROW_WW2A0_6", + "CLK_HROW_EE4A1_6", + "CLK_HROW_NE4C1_1", + "CLK_HROW_NE4BEG0_6", + "CLK_HROW_IMUX27_6", + "CLK_HROW_BUFHCE_CE_R4", + "CLK_HROW_CK_GCLK_TEST20", + "CLK_HROW_CK_GCLK_TEST_IN14", + "CLK_HROW_SW4END0_2", + "CLK_HROW_IMUX26_5", + "CLK_HROW_CK_GCLK_IN_TEST2", + "CLK_HROW_IMUX10_6", + "CLK_HROW_CK_MUX_OUT_L9", + "CLK_HROW_EL1BEG3_4", + "CLK_HROW_IMUX14_2", + "CLK_HROW_CTRL0_0", + "CLK_HROW_LOGIC_OUTS_B6_6", + "CLK_HROW_BUFHCE_CE_R11", + "CLK_HROW_NE4BEG2_6", + "CLK_HROW_LOGIC_OUTS_B0_2", + "CLK_HROW_CK_IN_L5", + "CLK_HROW_CK_IN_R13", + "CLK_HROW_NW4A0_0", + "CLK_HROW_WR1END0_5", + "CLK_HROW_IMUX41_2", + "CLK_HROW_BYP7_5", + "CLK_HROW_MONITOR_P_4", + "CLK_HROW_SE2A3_0", + "CLK_HROW_IMUX12_7", + "CLK_HROW_EE4BEG0_2", + "CLK_HROW_CK_HCLK_OUT_R0", + "CLK_HROW_EL1BEG2_5", + "CLK_HROW_NW4A1_5", + "CLK_HROW_IMUX41_3", + "CLK_HROW_IMUX25_4", + "CLK_HROW_IMUX12_3", + "CLK_HROW_IMUX29_0", + "CLK_HROW_WR1END2_0", + "CLK_HROW_WW4C1_7", + "CLK_HROW_LH10_0", + "CLK_HROW_IMUX1_2", + "CLK_HROW_WW4B0_3", + "CLK_HROW_BYP2_6", + "CLK_HROW_FAN7_0", + "CLK_HROW_IMUX40_4", + "CLK_HROW_IMUX44_5", + "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "CLK_HROW_R_CK_GCLK18", + "CLK_HROW_WW2END1_5", + "CLK_HROW_WW2END2_3", + "CLK_HROW_LOGIC_OUTS_B5_3", + "CLK_HROW_WW4A1_6", + "CLK_HROW_CLK0_3", + "CLK_HROW_IMUX42_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN14", + "CLK_HROW_WW4A0_4", + "CLK_HROW_IMUX43_1", + "CLK_HROW_WW2END2_7", + "CLK_HROW_EE4A3_5", + "CLK_HROW_WL1END3_3", + "CLK_HROW_WW2END0_3", + "CLK_HROW_CK_GCLK_TEST26", + "CLK_HROW_IMUX40_0", + "CLK_HROW_SE4BEG0_3", + "CLK_HROW_BLOCK_OUTS_B1_1", + "CLK_HROW_IMUX31_3", + "CLK_HROW_IMUX32_5", + "CLK_HROW_CK_HCLK_OUT_R10", + "CLK_HROW_LOGIC_OUTS_B11_1", + "CLK_HROW_BYP7_0", + "CLK_HROW_CK_BUFHCLK_R2", + "CLK_HROW_IMUX23_5", + "CLK_HROW_LOGIC_OUTS_B16_6", + "CLK_HROW_NE2A2_5", + "CLK_HROW_IMUX10_1", + "CLK_HROW_IMUX25_6", + "CLK_HROW_IMUX16_1", + "CLK_HROW_EE2BEG1_1", + "CLK_HROW_SE4C2_3", + "CLK_HROW_LOGIC_OUTS_B1_4", + "CLK_HROW_EE4BEG1_1", + "CLK_HROW_IMUX37_6", + "CLK_HROW_BYP5_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN27", + "CLK_HROW_BLOCK_OUTS_B2_3", + "CLK_HROW_WL1END1_4", + "CLK_HROW_CK_GCLK_TEST_IN16", + "CLK_HROW_NW2A3_2", + "CLK_HROW_IMUX19_2", + "CLK_HROW_LOGIC_OUTS_B22_5", + "CLK_HROW_EE4BEG3_5", + "CLK_HROW_SW4A2_3", + "CLK_HROW_BYP2_4", + "CLK_HROW_SW4END0_6", + "CLK_HROW_IMUX47_0", + "CLK_HROW_IMUX23_4", + "CLK_HROW_LH9_4", + "CLK_HROW_EL1BEG0_1", + "CLK_HROW_FAN2_3", + "CLK_HROW_FAN4_1", + "CLK_HROW_IMUX18_1", + "CLK_HROW_LH2_6", + "CLK_HROW_WW4C1_5", + "CLK_HROW_IMUX10_7", + "CLK_HROW_CK_IN_R_TEST_IN", + "CLK_HROW_NW4A0_7", + "CLK_HROW_IMUX41_4", + "CLK_HROW_LH1_5", + "CLK_HROW_IMUX1_7", + "CLK_HROW_LH8_2", + "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "CLK_HROW_EL1BEG1_0", + "CLK_HROW_CK_GCLK_IN_TEST22", + "CLK_HROW_LH1_0", + "CLK_HROW_REFCK_WESTCLK0", + "CLK_HROW_WW2A1_7", + "CLK_HROW_IMUX46_3", + "CLK_HROW_LOGIC_OUTS_B11_2", + "CLK_HROW_WW4END2_6", + "CLK_HROW_IMUX3_5", + "CLK_HROW_IMUX7_3", + "CLK_HROW_EL1BEG2_4", + "CLK_HROW_SW4A0_6", + "CLK_HROW_BUFHCE_CE_L7", + "CLK_HROW_NE4BEG1_5", + "CLK_HROW_BUFHCE_CE_L11", + "CLK_HROW_LH6_2", + "CLK_HROW_BYP3_0", + "CLK_HROW_EE4B0_3", + "CLK_HROW_LOGIC_OUTS_B14_0", + "CLK_HROW_EE4BEG1_7", + "CLK_HROW_IMUX27_1", + "CLK_HROW_CK_GCLK_IN_TEST10", + "CLK_HROW_LOGIC_OUTS_B5_0", + "CLK_HROW_CK_GCLK_TEST16", + "CLK_HROW_EE2A2_5", + "CLK_HROW_CK_IN_R_OUT_TEST", + "CLK_HROW_NW2A3_3", + "CLK_HROW_CK_BUFHCLK_L11", + "CLK_HROW_FAN6_6", + "CLK_HROW_CK_GCLK_TEST_OUT11", + "CLK_HROW_EE4B3_1", + "CLK_HROW_LH3_1", + "CLK_HROW_NE4C2_1", + "CLK_HROW_MONITOR_P_3", + "CLK_HROW_WW4C3_2", + "CLK_HROW_CK_GCLK_TEST_IN20", + "CLK_HROW_NW2A1_7", + "CLK_HROW_EE4A3_7", + "CLK_HROW_IMUX9_0", + "CLK_HROW_NW4A2_6", + "CLK_HROW_IMUX0_0", + "CLK_HROW_SE4C3_0", + "CLK_HROW_NE4BEG0_3", + "CLK_HROW_IMUX41_1", + "CLK_HROW_CK_GCLK_OUT_TEST10", + "CLK_HROW_LOGIC_OUTS_B0_5", + "CLK_HROW_IMUX17_7", + "CLK_HROW_WW2END3_6", + "CLK_HROW_WW2END3_1", + "CLK_HROW_WW4B2_2", + "CLK_HROW_WW2END1_3", + "CLK_HROW_LOGIC_OUTS_B1_1", + "CLK_HROW_EE4A1_1", + "CLK_HROW_IMUX29_4", + "CLK_HROW_LOGIC_OUTS_B12_5", + "CLK_HROW_BLOCK_OUTS_B0_6", + "CLK_HROW_EE4A3_3", + "CLK_HROW_WW2A3_5", + "CLK_HROW_NW2A2_7", + "CLK_HROW_CLK1_0", + "CLK_HROW_LOGIC_OUTS_B7_3", + "CLK_HROW_LOGIC_OUTS_B2_4", + "CLK_HROW_FAN0_0", + "CLK_HROW_CTRL0_3", + "CLK_HROW_IMUX47_1", + "CLK_HROW_WW4B3_5", + "CLK_HROW_CTRL1_6", + "CLK_HROW_WW4B1_2", + "CLK_HROW_WW2END3_5", + "CLK_HROW_IMUX42_3", + "CLK_HROW_SE4C0_6", + "CLK_HROW_IMUX17_4", + "CLK_HROW_CK_HCLK_OUT_L3", + "CLK_HROW_LH12_4", + "CLK_HROW_WW4C2_7", + "CLK_HROW_SW4END1_6", + "CLK_HROW_EL1BEG1_4", + "CLK_HROW_LH7_0", + "CLK_HROW_WW4A3_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN26", + "CLK_HROW_LH6_3", + "CLK_HROW_WW4B3_4", + "CLK_HROW_CK_IN_L10", + "CLK_HROW_IMUX45_0", + "CLK_HROW_LOGIC_OUTS_B13_0", + "CLK_HROW_SW4END0_3", + "CLK_HROW_ER1BEG0_3", + "CLK_HROW_LH11_4", + "CLK_HROW_LOGIC_OUTS_B19_3", + "CLK_HROW_NE2A3_5", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN19", + "CLK_HROW_WW4C3_4", + "CLK_HROW_EL1BEG2_1", + "CLK_HROW_EE2BEG2_4", + "CLK_HROW_WW4A3_4", + "CLK_HROW_IMUX38_0", + "CLK_HROW_EE2A2_2", + "CLK_HROW_BYP2_1", + "CLK_HROW_SW4END3_3", + "CLK_HROW_IMUX46_5", + "CLK_HROW_SE4C1_2", + "CLK_HROW_SE4C1_3", + "CLK_HROW_WL1END3_4", + "CLK_HROW_EL1BEG1_7", + "CLK_HROW_IMUX42_1", + "CLK_HROW_LOGIC_OUTS_B6_7", + "CLK_HROW_LOGIC_OUTS_B17_2", + "CLK_HROW_EL1BEG0_0", + "CLK_HROW_FAN1_6", + "CLK_HROW_CLK0_2", + "CLK_HROW_CK_BUFHCLK_L0", + "CLK_HROW_NE2A0_6", + "CLK_HROW_WW2END0_2", + "CLK_HROW_EE4C3_2", + "CLK_HROW_LOGIC_OUTS_B10_2", + "CLK_HROW_NE4BEG3_1", + "CLK_HROW_BYP3_1", + "CLK_HROW_IMUX43_4", + "CLK_HROW_LOGIC_OUTS_B8_6", + "CLK_HROW_EE2A0_7", + "CLK_HROW_WW4B0_1", + "CLK_HROW_FAN3_5", + "CLK_HROW_LOGIC_OUTS_B20_1", + "CLK_HROW_CK_GCLK_OUT_TEST13", + "CLK_HROW_EL1BEG2_3", + "CLK_HROW_IMUX38_6", + "CLK_HROW_WW2A2_2", + "CLK_HROW_NE4BEG3_7", + "CLK_HROW_CLK1_6", + "CLK_HROW_LOGIC_OUTS_B6_4", + "CLK_HROW_IMUX30_5", + "CLK_HROW_IMUX35_5", + "CLK_HROW_LH4_6", + "CLK_HROW_EE4C0_4", + "CLK_HROW_CK_GCLK_TEST_IN17", + "CLK_HROW_MONITOR_P_6", + "CLK_HROW_NW4A3_4", + "CLK_HROW_WW4END0_2", + "CLK_HROW_SW4END2_5", + "CLK_HROW_LH4_7", + "CLK_HROW_IMUX17_0", + "CLK_HROW_LOGIC_OUTS_B18_2", + "CLK_HROW_LOGIC_OUTS_B16_0", + "CLK_HROW_SE2A3_1", + "CLK_HROW_NW4A1_2", + "CLK_HROW_EE4BEG3_0", + "CLK_HROW_CK_GCLK_TEST_OUT22", + "CLK_HROW_CK_HCLK_OUT_L0", + "CLK_HROW_EE4C2_5", + "CLK_HROW_IMUX18_2", + "CLK_HROW_BLOCK_OUTS_B2_0", + "CLK_HROW_WR1END2_3", + "CLK_HROW_NW4A0_1", + "CLK_HROW_NE4C0_3", + "CLK_HROW_WW4END1_1", + "CLK_HROW_SE4C0_7", + "CLK_HROW_BYP5_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN10", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN1", + "CLK_HROW_SE4BEG3_2", + "CLK_HROW_IMUX1_6", + "CLK_HROW_BLOCK_OUTS_B3_6", + "CLK_HROW_WL1END3_2", + "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "CLK_HROW_EE2BEG3_5", + "CLK_HROW_EE4A2_1", + "CLK_HROW_EE2BEG3_4", + "CLK_HROW_NE4BEG1_7", + "CLK_HROW_IMUX47_7", + "CLK_HROW_CK_GCLK_TEST_OUT19", + "CLK_HROW_IMUX6_4", + "CLK_HROW_BYP1_5", + "CLK_HROW_LOGIC_OUTS_B16_7", + "CLK_HROW_SW2A2_3", + "CLK_HROW_CK_IN_R4", + "CLK_HROW_WW4C1_0", + "CLK_HROW_IMUX24_6", + "CLK_HROW_NW4END1_3", + "CLK_HROW_IMUX0_3", + "CLK_HROW_EE4B3_2", + "CLK_HROW_SE4BEG0_4", + "CLK_HROW_NE2A0_1", + "CLK_HROW_NW4A2_3", + "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "CLK_HROW_IMUX44_4", + "CLK_HROW_CK_GCLK_TEST_OUT31", + "CLK_HROW_SW4END2_1", + "CLK_HROW_SW4A1_3", + "CLK_HROW_EE2A3_5", + "CLK_HROW_LH10_2", + "CLK_HROW_LH9_6", + "CLK_HROW_NE4C1_0", + "CLK_HROW_CK_GCLK_TEST_OUT30", + "CLK_HROW_CK_GCLK_TEST_IN30", + "CLK_HROW_EE4B1_2", + "CLK_HROW_IMUX4_5", + "CLK_HROW_NE4BEG2_1", + "CLK_HROW_BUFHCE_CE_R7", + "CLK_HROW_ER1BEG1_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "CLK_HROW_LOGIC_OUTS_B23_6", + "CLK_HROW_LOGIC_OUTS_B2_0", + "CLK_HROW_EE4BEG1_6", + "CLK_HROW_EE4C2_7", + "CLK_HROW_NW2A3_6", + "CLK_HROW_NW4A2_7", + "CLK_HROW_SE4C1_7", + "CLK_HROW_IMUX6_1", + "CLK_HROW_SE2A2_4", + "CLK_HROW_IMUX3_2", + "CLK_HROW_IMUX19_4", + "CLK_HROW_IMUX31_1", + "CLK_HROW_NE4C3_5", + "CLK_HROW_LOGIC_OUTS_B19_2", + "CLK_HROW_ER1BEG3_4", + "CLK_HROW_WW2END3_7", + "CLK_HROW_NE4BEG0_5", + "CLK_HROW_FAN1_1", + "CLK_HROW_CK_GCLK_TEST_OUT16", + "CLK_HROW_BYP0_5", + "CLK_HROW_BYP4_6", + "CLK_HROW_LOGIC_OUTS_B12_0", + "CLK_HROW_LOGIC_OUTS_B17_7", + "CLK_HROW_EE2A2_1", + "CLK_HROW_LH8_6", + "CLK_HROW_EE2A1_7", + "CLK_HROW_CTRL1_1", + "CLK_HROW_WW2A1_1", + "CLK_HROW_LOGIC_OUTS_B9_5", + "CLK_HROW_SW4A3_2", + "CLK_HROW_SE2A2_7", + "CLK_HROW_CE_INT_TOP0", + "CLK_HROW_CK_HCLK_OUT_L6", + "CLK_HROW_IMUX29_3", + "CLK_HROW_IMUX28_1", + "CLK_HROW_IMUX37_2", + "CLK_HROW_WW4A3_7", + "CLK_HROW_CK_GCLK_IN_TEST24", + "CLK_HROW_WL1END0_7", + "CLK_HROW_LOGIC_OUTS_B21_6", + "CLK_HROW_NW4END0_1", + "CLK_HROW_SW2A3_1", + "CLK_HROW_IMUX21_6", + "CLK_HROW_CK_GCLK_IN_TEST12", + "CLK_HROW_WR1END3_0", + "CLK_HROW_SW2A2_1", + "CLK_HROW_SW2A3_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "CLK_HROW_CK_IN_L_TEST_OUT", + "CLK_HROW_IMUX25_2", + "CLK_HROW_WR1END0_6", + "CLK_HROW_EL1BEG2_0", + "CLK_HROW_SW4END2_4", + "CLK_HROW_LH12_0", + "CLK_HROW_WR1END1_0", + "CLK_HROW_CK_IN_R0", + "CLK_HROW_LH4_3", + "CLK_HROW_LOGIC_OUTS_B23_4", + "CLK_HROW_IMUX13_3", + "CLK_HROW_IMUX40_6", + "CLK_HROW_SW4A0_7", + "CLK_HROW_EE4B3_4", + "CLK_HROW_IMUX42_5", + "CLK_HROW_IMUX21_5", + "CLK_HROW_CK_BUFHCLK_R4", + "CLK_HROW_FAN5_4", + "CLK_HROW_LOGIC_OUTS_B11_0", + "CLK_HROW_EE2BEG0_3", + "CLK_HROW_BUFHCE_CE_R2", + "CLK_HROW_NE4BEG0_2", + "CLK_HROW_SW2A0_3", + "CLK_HROW_EL1BEG3_7", + "CLK_HROW_WW4B0_6", + "CLK_HROW_EE4C2_0", + "CLK_HROW_IMUX45_7", + "CLK_HROW_WW4A0_1", + "CLK_HROW_SE4BEG3_6", + "CLK_HROW_IMUX21_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN22", + "CLK_HROW_IMUX26_6", + "CLK_HROW_FAN7_7", + "CLK_HROW_IMUX9_1", + "CLK_HROW_EE4C1_7", + "CLK_HROW_EE4B1_5", + "CLK_HROW_WL1END1_2", + "CLK_HROW_LOGIC_OUTS_B0_6", + "CLK_HROW_LH7_7", + "CLK_HROW_CK_GCLK_OUT_TEST22", + "CLK_HROW_IMUX41_0", + "CLK_HROW_LH12_3", + "CLK_HROW_SE2A2_2", + "CLK_HROW_IMUX39_5", + "CLK_HROW_SE2A2_6", + "CLK_HROW_FAN7_3", + "CLK_HROW_LOGIC_OUTS_B11_7", + "CLK_HROW_LH5_4", + "CLK_HROW_ER1BEG0_2", + "CLK_HROW_LOGIC_OUTS_B3_3", + "CLK_HROW_EE4A0_2", + "CLK_HROW_CK_HCLK_OUT_L7", + "CLK_HROW_LOGIC_OUTS_B21_1", + "CLK_HROW_CK_GCLK_TEST12", + "CLK_HROW_CK_HCLK_OUT_R2", + "CLK_HROW_IMUX0_2", + "CLK_HROW_IMUX36_4", + "CLK_HROW_IMUX30_1", + "CLK_HROW_IMUX8_5", + "CLK_HROW_LOGIC_OUTS_B22_0", + "CLK_HROW_WW4END2_3", + "CLK_HROW_SW4END3_1", + "CLK_HROW_CK_GCLK_TEST13", + "CLK_HROW_LH6_0", + "CLK_HROW_WW2END1_0", + "CLK_HROW_CK_GCLK_TEST19", + "CLK_HROW_WW4A1_3", + "CLK_HROW_R_CK_GCLK29", + "CLK_HROW_LOGIC_OUTS_B18_1", + "CLK_HROW_IMUX41_6", + "CLK_HROW_NE4C0_4", + "CLK_HROW_LH4_1", + "CLK_HROW_LOGIC_OUTS_B1_5", + "CLK_HROW_BLOCK_OUTS_B1_2", + "CLK_HROW_LH5_2", + "CLK_HROW_CK_GCLK_TEST_OUT15", + "CLK_HROW_FAN5_5", + "CLK_HROW_R_CK_GCLK22", + "CLK_HROW_IMUX32_0", + "CLK_HROW_WL1END3_6", + "CLK_HROW_CK_HCLK_OUT_R1", + "CLK_HROW_SE2A1_0", + "CLK_HROW_WW4B1_0", + "CLK_HROW_ER1BEG3_2", + "CLK_HROW_SE2A3_4", + "CLK_HROW_BLOCK_OUTS_B0_3", + "CLK_HROW_CK_GCLK_TEST_IN2", + "CLK_HROW_LH4_2", + "CLK_HROW_CK_MUX_OUT_R5", + "CLK_HROW_WR1END0_3", + "CLK_HROW_CK_GCLK_TEST_IN27", + "CLK_HROW_WL1END1_3", + "CLK_HROW_IMUX4_2", + "CLK_HROW_LOGIC_OUTS_B20_4", + "CLK_HROW_CK_GCLK_TEST_OUT2", + "CLK_HROW_EE4B0_6", + "CLK_HROW_IMUX22_0", + "CLK_HROW_LOGIC_OUTS_B21_2", + "CLK_HROW_LOGIC_OUTS_B3_7", + "CLK_HROW_LOGIC_OUTS_B9_6", + "CLK_HROW_FAN1_0", + "CLK_HROW_WL1END3_5", + "CLK_HROW_LH1_1", + "CLK_HROW_WW4END2_1", + "CLK_HROW_CTRL0_2", + "CLK_HROW_IMUX12_1", + "CLK_HROW_IMUX33_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "CLK_HROW_CK_GCLK_OUT_TEST21", + "CLK_HROW_CK_MUX_OUT_L8", + "CLK_HROW_CK_GCLK_OUT_TEST16", + "CLK_HROW_WW2A2_1", + "CLK_HROW_IMUX5_4", + "CLK_HROW_SE2A0_7", + "CLK_HROW_EE4BEG0_6", + "CLK_HROW_IMUX13_6", + "CLK_HROW_LH5_1", + "CLK_HROW_IMUX32_3", + "CLK_HROW_EE4B2_3", + "CLK_HROW_CK_GCLK_TEST31", + "CLK_HROW_IMUX42_6", + "CLK_HROW_R_CK_GCLK0", + "CLK_HROW_WW2A2_5", + "CLK_HROW_R_CK_GCLK2", + "CLK_HROW_BYP3_2", + "CLK_HROW_CK_GCLK_TEST6", + "CLK_HROW_BUFHCE_CE_R5", + "CLK_HROW_BLOCK_OUTS_B2_2", + "CLK_HROW_EE2BEG2_0", + "CLK_HROW_LH10_1", + "CLK_HROW_NW4A1_4", + "CLK_HROW_BYP7_1", + "CLK_HROW_NW2A3_7", + "CLK_HROW_EE2BEG0_7", + "CLK_HROW_IMUX12_0", + "CLK_HROW_LOGIC_OUTS_B4_4", + "CLK_HROW_WR1END1_7", + "CLK_HROW_CK_GCLK_TEST_OUT17", + "CLK_HROW_MONITOR_N_6", + "CLK_HROW_BYP5_3", + "CLK_HROW_IMUX0_5", + "CLK_HROW_BYP1_6", + "CLK_HROW_LOGIC_OUTS_B10_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "CLK_HROW_CK_MUX_OUT_L3", + "CLK_HROW_IMUX46_0", + "CLK_HROW_ER1BEG3_1", + "CLK_HROW_IMUX47_5", + "CLK_HROW_SE4C2_7", + "CLK_HROW_EE4C0_5", + "CLK_HROW_CLK1_7", + "CLK_HROW_IMUX24_2", + "CLK_HROW_CK_GCLK_TEST_OUT26", + "CLK_HROW_WR1END1_2", + "CLK_HROW_WW4B0_4", + "CLK_HROW_ER1BEG2_0", + "CLK_HROW_EE4B1_0", + "CLK_HROW_BYP3_4", + "CLK_HROW_EE2BEG0_4", + "CLK_HROW_ER1BEG1_6", + "CLK_HROW_CLK1_2", + "CLK_HROW_CE_INT_TOP10", + "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "CLK_HROW_CK_GCLK_TEST_IN23", + "CLK_HROW_WR1END3_5", + "CLK_HROW_WW4A0_2", + "CLK_HROW_NW4A3_3", + "CLK_HROW_CK_GCLK_TEST18", + "CLK_HROW_FAN7_4", + "CLK_HROW_NE4BEG1_6", + "CLK_HROW_WR1END2_7", + "CLK_HROW_NW2A0_7", + "CLK_HROW_WW4B2_1", + "CLK_HROW_CK_GCLK_TEST_OUT10", + "CLK_HROW_NW4END2_7", + "CLK_HROW_WW4B0_0", + "CLK_HROW_IMUX10_0", + "CLK_HROW_IMUX44_7", + "CLK_HROW_CK_GCLK_TEST3", + "CLK_HROW_NE4C0_6", + "CLK_HROW_IMUX33_5", + "CLK_HROW_WW4B1_3", + "CLK_HROW_IMUX14_1", + "CLK_HROW_CK_GCLK_TEST_IN19", + "CLK_HROW_IMUX11_2", + "CLK_HROW_BUFHCE_CE_L10", + "CLK_HROW_CK_GCLK_IN_TEST3", + "CLK_HROW_CK_GCLK_IN_TEST27", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN23", + "CLK_HROW_FAN4_6", + "CLK_HROW_R_CK_GCLK15", + "CLK_HROW_SW2A1_0", + "CLK_HROW_CK_GCLK_OUT_TEST3", + "CLK_HROW_WW2END0_5", + "CLK_HROW_IMUX33_2", + "CLK_HROW_IMUX12_4", + "CLK_HROW_BYP0_2", + "CLK_HROW_CK_GCLK_IN_TEST4", + "CLK_HROW_SE4BEG3_5", + "CLK_HROW_CK_BUFHCLK_L10", + "CLK_HROW_NE4C1_6", + "CLK_HROW_EE2BEG1_5", + "CLK_HROW_SE4C0_4", + "CLK_HROW_LH11_0", + "CLK_HROW_CK_HCLK_OUT_R6", + "CLK_HROW_IMUX39_3", + "CLK_HROW_CK_GCLK_TEST1", + "CLK_HROW_NW4A0_2", + "CLK_HROW_IMUX45_6", + "CLK_HROW_IMUX9_6", + "CLK_HROW_NW4A0_4", + "CLK_HROW_SW2A3_6", + "CLK_HROW_FAN2_6", + "CLK_HROW_EE2A2_0", + "CLK_HROW_LH9_0", + "CLK_HROW_NE2A2_2", + "CLK_HROW_WW4A0_5", + "CLK_HROW_ER1BEG2_1", + "CLK_HROW_IMUX20_2", + "CLK_HROW_CK_IN_L9", + "CLK_HROW_BLOCK_OUTS_B3_1", + "CLK_HROW_LOGIC_OUTS_B8_4", + "CLK_HROW_LOGIC_OUTS_B23_7", + "CLK_HROW_ER1BEG1_2", + "CLK_HROW_LH8_4", + "CLK_HROW_FAN4_7", + "CLK_HROW_FAN0_6", + "CLK_HROW_EE2A3_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "CLK_HROW_CK_BUFHCLK_L6", + "CLK_HROW_LH7_3", + "CLK_HROW_CK_GCLK_OUT_TEST14", + "CLK_HROW_SW4END0_0", + "CLK_HROW_CK_GCLK_IN_TEST0", + "CLK_HROW_WW4A2_6", + "CLK_HROW_IMUX34_4", + "CLK_HROW_NW2A1_1", + "CLK_HROW_SW2A3_4", + "CLK_HROW_EE4BEG3_1", + "CLK_HROW_CK_MUX_OUT_R6", + "CLK_HROW_CE_INT_TOP4", + "CLK_HROW_LH9_5", + "CLK_HROW_IMUX19_5", + "CLK_HROW_IMUX31_5", + "CLK_HROW_NE4C1_3", + "CLK_HROW_IMUX2_4", + "CLK_HROW_CE_INT_BOT2", + "CLK_HROW_SW2A1_2", + "CLK_HROW_SW2A3_5", + "CLK_HROW_FAN2_7", + "CLK_HROW_EE2BEG2_3", + "CLK_HROW_IMUX29_6", + "CLK_HROW_EE2BEG3_0", + "CLK_HROW_EE4A3_0", + "CLK_HROW_BLOCK_OUTS_B3_0", + "CLK_HROW_EE4BEG2_4", + "CLK_HROW_NE4C0_7", + "CLK_HROW_CK_BUFRCLK_R1", + "CLK_HROW_MONITOR_P_0", + "CLK_HROW_BLOCK_OUTS_B2_6", + "CLK_HROW_WR1END3_7", + "CLK_HROW_CK_GCLK_TEST_OUT13", + "CLK_HROW_R_CK_GCLK28", + "CLK_HROW_EE2A0_0", + "CLK_HROW_LOGIC_OUTS_B23_5", + "CLK_HROW_CK_GCLK_TEST21", + "CLK_HROW_SE4C2_2", + "CLK_HROW_BUFHCE_CE_L2", + "CLK_HROW_BLOCK_OUTS_B2_5", + "CLK_HROW_SE2A2_5", + "CLK_HROW_FAN4_2", + "CLK_HROW_LOGIC_OUTS_B5_4", + "CLK_HROW_WR1END3_2", + "CLK_HROW_IMUX17_1", + "CLK_HROW_FAN7_5", + "CLK_HROW_WW4B0_7", + "CLK_HROW_SE4C1_1", + "CLK_HROW_EL1BEG0_6", + "CLK_HROW_EE2A3_2", + "CLK_HROW_FAN6_7", + "CLK_HROW_EE2BEG2_5", + "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "CLK_HROW_LOGIC_OUTS_B21_0", + "CLK_HROW_SE4BEG0_5", + "CLK_HROW_CE_INT_TOP9", + "CLK_HROW_ER1BEG2_3", + "CLK_HROW_EL1BEG3_2", + "CLK_HROW_NE4BEG1_0", + "CLK_HROW_IMUX5_7", + "CLK_HROW_EE2A2_7", + "CLK_HROW_CLK1_1", + "CLK_HROW_LH11_5", + "CLK_HROW_SE4C2_5", + "CLK_HROW_IMUX30_3", + "CLK_HROW_CK_BUFHCLK_R1", + "CLK_HROW_LOGIC_OUTS_B1_2", + "CLK_HROW_LOGIC_OUTS_B20_3", + "CLK_HROW_IMUX33_0", + "CLK_HROW_EE2BEG1_3", + "CLK_HROW_EL1BEG1_6", + "CLK_HROW_EE4C0_6", + "CLK_HROW_LOGIC_OUTS_B19_5", + "CLK_HROW_NE4BEG1_3", + "CLK_HROW_BYP6_2", + "CLK_HROW_LOGIC_OUTS_B19_6", + "CLK_HROW_SW2A1_3", + "CLK_HROW_IMUX37_0", + "CLK_HROW_WW4B1_4", + "CLK_HROW_IMUX0_6", + "CLK_HROW_CK_MUX_OUT_R0", + "CLK_HROW_IMUX32_7", + "CLK_HROW_LOGIC_OUTS_B17_4", + "CLK_HROW_NW4END0_5", + "CLK_HROW_NE4C0_2", + "CLK_HROW_SW4END0_1", + "CLK_HROW_WL1END1_7", + "CLK_HROW_LH1_3", + "CLK_HROW_BLOCK_OUTS_B0_4", + "CLK_HROW_IMUX39_0", + "CLK_HROW_WR1END3_4", + "CLK_HROW_LOGIC_OUTS_B15_7", + "CLK_HROW_NW4END2_3", + "CLK_HROW_LOGIC_OUTS_B10_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "CLK_HROW_CTRL1_5", + "CLK_HROW_NW2A2_4", + "CLK_HROW_IMUX34_0", + "CLK_HROW_IMUX24_3", + "CLK_HROW_WW2A0_5", + "CLK_HROW_LOGIC_OUTS_B16_5", + "CLK_HROW_CK_BUFHCLK_R9", + "CLK_HROW_IMUX22_6", + "CLK_HROW_EE4BEG1_5", + "CLK_HROW_IMUX25_7", + "CLK_HROW_IMUX23_3", + "CLK_HROW_EE4B2_7", + "CLK_HROW_LOGIC_OUTS_B5_2", + "CLK_HROW_LOGIC_OUTS_B5_7", + "CLK_HROW_WW4A2_7", + "CLK_HROW_CK_GCLK_TEST_IN21", + "CLK_HROW_WW4END0_0", + "CLK_HROW_IMUX33_1", + "CLK_HROW_SW4A2_2", + "CLK_HROW_CK_GCLK_TEST23", + "CLK_HROW_EE4A2_2", + "CLK_HROW_LH10_6", + "CLK_HROW_BYP3_7", + "CLK_HROW_SE4C2_0", + "CLK_HROW_SE4C3_5", + "CLK_HROW_IMUX39_6", + "CLK_HROW_R_CK_GCLK31", + "CLK_HROW_FAN2_4", + "CLK_HROW_EL1BEG3_1", + "CLK_HROW_WW4A2_2", + "CLK_HROW_LH7_6", + "CLK_HROW_LOGIC_OUTS_B7_1", + "CLK_HROW_LOGIC_OUTS_B13_1", + "CLK_HROW_CK_GCLK_TEST5", + "CLK_HROW_ER1BEG3_7", + "CLK_HROW_BYP5_4", + "CLK_HROW_SE4C0_3", + "CLK_HROW_IMUX2_1", + "CLK_HROW_IMUX39_4", + "CLK_HROW_SW4A0_0", + "CLK_HROW_CK_GCLK_TEST29", + "CLK_HROW_LOGIC_OUTS_B21_4", + "CLK_HROW_IMUX35_1", + "CLK_HROW_CK_GCLK_TEST_IN22", + "CLK_HROW_FAN6_2", + "CLK_HROW_FAN4_5", + "CLK_HROW_CK_GCLK_IN_TEST26", + "CLK_HROW_BYP6_3", + "CLK_HROW_BUFHCE_CE_L5", + "CLK_HROW_IMUX43_6", + "CLK_HROW_WW4END3_4", + "CLK_HROW_SW2A2_4", + "CLK_HROW_MONITOR_P_7", + "CLK_HROW_SW4END2_2", + "CLK_HROW_CK_GCLK_TEST_IN9", + "CLK_HROW_LOGIC_OUTS_B19_0", + "CLK_HROW_NW4A3_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "CLK_HROW_CK_GCLK_TEST_IN13", + "CLK_HROW_WW2END1_1", + "CLK_HROW_LOGIC_OUTS_B10_5", + "CLK_HROW_IMUX34_7", + "CLK_HROW_EE4BEG2_3", + "CLK_HROW_EE4B2_2", + "CLK_HROW_CTRL0_4", + "CLK_HROW_IMUX3_3", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN24", + "CLK_HROW_EE4B1_4", + "CLK_HROW_CK_IN_R9", + "CLK_HROW_IMUX19_0", + "CLK_HROW_WW2END2_1", + "CLK_HROW_CK_GCLK_TEST_OUT5", + "CLK_HROW_WR1END1_3", + "CLK_HROW_IMUX9_3", + "CLK_HROW_LOGIC_OUTS_B20_2", + "CLK_HROW_WW4A1_1", + "CLK_HROW_WW4B1_1", + "CLK_HROW_CK_BUFHCLK_R0", + "CLK_HROW_NW4A3_5", + "CLK_HROW_IMUX2_3", + "CLK_HROW_IMUX26_3", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN21", + "CLK_HROW_CK_GCLK_TEST17", + "CLK_HROW_EE4BEG0_5", + "CLK_HROW_IMUX8_6", + "CLK_HROW_NW4END1_0", + "CLK_HROW_LOGIC_OUTS_B23_2", + "CLK_HROW_IMUX11_4", + "CLK_HROW_WW4END3_2", + "CLK_HROW_IMUX12_2", + "CLK_HROW_LOGIC_OUTS_B10_3", + "CLK_HROW_CK_BUFHCLK_L1", + "CLK_HROW_NE2A3_2", + "CLK_HROW_SW2A3_7", + "CLK_HROW_LOGIC_OUTS_B8_5", + "CLK_HROW_SE4C1_5", + "CLK_HROW_NE4C2_4", + "CLK_HROW_FAN5_0", + "CLK_HROW_CK_HCLK_OUT_L10", + "CLK_HROW_SE2A0_1", + "CLK_HROW_FAN2_2", + "CLK_HROW_WL1END2_0", + "CLK_HROW_CK_IN_L4", + "CLK_HROW_LOGIC_OUTS_B4_0", + "CLK_HROW_WW2END1_4", + "CLK_HROW_NW4END3_4", + "CLK_HROW_EE4A1_7", + "CLK_HROW_NW4END0_3", + "CLK_HROW_IMUX8_1", + "CLK_HROW_BYP2_7", + "CLK_HROW_LOGIC_OUTS_B6_3", + "CLK_HROW_CK_MUX_OUT_R7", + "CLK_HROW_CK_GCLK_TEST25", + "CLK_HROW_BLOCK_OUTS_B0_0", + "CLK_HROW_IMUX42_7", + "CLK_HROW_BYP2_0", + "CLK_HROW_NW2A0_5", + "CLK_HROW_BYP5_7", + "CLK_HROW_CK_GCLK_IN_TEST23", + "CLK_HROW_CK_GCLK_IN_TEST1", + "CLK_HROW_CK_BUFHCLK_L7", + "CLK_HROW_IMUX8_4", + "CLK_HROW_EE4C1_0", + "CLK_HROW_REFCK_WESTCLK1", + "CLK_HROW_CK_GCLK_IN_TEST6", + "CLK_HROW_SW4END3_6", + "CLK_HROW_MONITOR_N_0", + "CLK_HROW_IMUX22_2", + "CLK_HROW_R_CK_GCLK19", + "CLK_HROW_EE4A0_7", + "CLK_HROW_CK_GCLK_OUT_TEST18", + "CLK_HROW_IMUX40_2", + "CLK_HROW_BYP1_2", + "CLK_HROW_CLK0_5", + "CLK_HROW_CK_GCLK_TEST_IN28", + "CLK_HROW_LH7_4", + "CLK_HROW_EE4A2_6", + "CLK_HROW_NW4A2_2", + "CLK_HROW_R_CK_GCLK6", + "CLK_HROW_IMUX37_5", + "CLK_HROW_EE2A0_6", + "CLK_HROW_IMUX18_6", + "CLK_HROW_LOGIC_OUTS_B4_7", + "CLK_HROW_EE4BEG1_2", + "CLK_HROW_IMUX28_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN3", + "CLK_HROW_BLOCK_OUTS_B1_0", + "CLK_HROW_LH7_2", + "CLK_HROW_IMUX15_1", + "CLK_HROW_MONITOR_P_2", + "CLK_HROW_IMUX10_4", + "CLK_HROW_SW4A3_1", + "CLK_HROW_IMUX2_6", + "CLK_HROW_LH5_6", + "CLK_HROW_CK_GCLK_IN_TEST8", + "CLK_HROW_SW2A2_2", + "CLK_HROW_EE2BEG3_6", + "CLK_HROW_LOGIC_OUTS_B14_1", + "CLK_HROW_LOGIC_OUTS_B7_6", + "CLK_HROW_IMUX30_4", + "CLK_HROW_EE4C0_7", + "CLK_HROW_IMUX24_0", + "CLK_HROW_IMUX41_5", + "CLK_HROW_WR1END0_2", + "CLK_HROW_SE4BEG3_1", + "CLK_HROW_LOGIC_OUTS_B16_2", + "CLK_HROW_CK_BUFRCLK_L1", + "CLK_HROW_CTRL1_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN7", + "CLK_HROW_IMUX5_3", + "CLK_HROW_WW4END1_5", + "CLK_HROW_EE4C0_2", + "CLK_HROW_WR1END0_0", + "CLK_HROW_IMUX11_0", + "CLK_HROW_IMUX20_0", + "CLK_HROW_IMUX8_2", + "CLK_HROW_LH10_4", + "CLK_HROW_CK_GCLK_TEST_IN24", + "CLK_HROW_IMUX38_4", + "CLK_HROW_ER1BEG2_6", + "CLK_HROW_WW4C2_4", + "CLK_HROW_WW2END0_4", + "CLK_HROW_SE4BEG2_2", + "CLK_HROW_EE4B1_3", + "CLK_HROW_LOGIC_OUTS_B23_0", + "CLK_HROW_IMUX4_4", + "CLK_HROW_LOGIC_OUTS_B13_4", + "CLK_HROW_WW4C2_5", + "CLK_HROW_MONITOR_N_1", + "CLK_HROW_IMUX39_1", + "CLK_HROW_IMUX29_1", + "CLK_HROW_IMUX23_7", + "CLK_HROW_LH3_6", + "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "CLK_HROW_IMUX31_0", + "CLK_HROW_EE4C1_2", + "CLK_HROW_LH11_7", + "CLK_HROW_SW2A0_4", + "CLK_HROW_WL1END0_0", + "CLK_HROW_FAN7_2", + "CLK_HROW_IMUX28_2", + "CLK_HROW_WW4C0_2", + "CLK_HROW_CE_INT_TOP6", + "CLK_HROW_BYP1_4", + "CLK_HROW_IMUX35_4", + "CLK_HROW_REFCK_EASTCLK1", + "CLK_HROW_SE2A3_6", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN17", + "CLK_HROW_LOGIC_OUTS_B23_3", + "CLK_HROW_CK_BUFHCLK_L8", + "CLK_HROW_NE4C3_2", + "CLK_HROW_IMUX8_0", + "CLK_HROW_WL1END0_3", + "CLK_HROW_BYP6_1", + "CLK_HROW_ER1BEG3_0", + "CLK_HROW_CK_GCLK_TEST_OUT6", + "CLK_HROW_CK_GCLK_OUT_TEST31", + "CLK_HROW_IMUX39_2", + "CLK_HROW_CK_GCLK_TEST2", + "CLK_HROW_WR1END0_1", + "CLK_HROW_NE4BEG3_3", + "CLK_HROW_IMUX35_7", + "CLK_HROW_LOGIC_OUTS_B7_0", + "CLK_HROW_SW4END0_5", + "CLK_HROW_CK_BUFHCLK_R6", + "CLK_HROW_IMUX15_2", + "CLK_HROW_CK_HCLK_OUT_L4", + "CLK_HROW_SW2A3_2", + "CLK_HROW_SW4END3_5", + "CLK_HROW_FAN1_4", + "CLK_HROW_EE4A1_0", + "CLK_HROW_WW4END1_6", + "CLK_HROW_EL1BEG2_2", + "CLK_HROW_BYP3_6", + "CLK_HROW_EE4B3_6", + "CLK_HROW_WW4A0_3", + "CLK_HROW_WW2A3_0", + "CLK_HROW_WW4B2_0", + "CLK_HROW_EE4BEG0_1", + "CLK_HROW_WW2END0_1", + "CLK_HROW_ER1BEG0_0", + "CLK_HROW_SE4BEG1_3", + "CLK_HROW_EE4B0_7", + "CLK_HROW_CK_MUX_OUT_R2", + "CLK_HROW_EE4C1_1", + "CLK_HROW_CE_INT_TOP2", + "CLK_HROW_BUFHCE_CE_R6", + "CLK_HROW_EE2A3_4", + "CLK_HROW_WW2A0_3", + "CLK_HROW_CK_HCLK_OUT_R5", + "CLK_HROW_IMUX1_3", + "CLK_HROW_LH1_7", + "CLK_HROW_EE2A1_1", + "CLK_HROW_LOGIC_OUTS_B0_1", + "CLK_HROW_R_CK_GCLK10", + "CLK_HROW_IMUX6_2", + "CLK_HROW_CK_GCLK_TEST14", + "CLK_HROW_IMUX14_3", + "CLK_HROW_CK_GCLK_TEST_OUT28", + "CLK_HROW_LOGIC_OUTS_B19_7", + "CLK_HROW_WL1END3_1", + "CLK_HROW_NW4END0_6", + "CLK_HROW_WW4END1_4", + "CLK_HROW_IMUX21_1", + "CLK_HROW_IMUX15_7", + "CLK_HROW_CK_GCLK_IN_TEST19", + "CLK_HROW_IMUX45_5", + "CLK_HROW_WW4A3_6", + "CLK_HROW_ER1BEG1_4", + "CLK_HROW_BLOCK_OUTS_B1_3", + "CLK_HROW_IMUX5_5", + "CLK_HROW_IMUX17_3", + "CLK_HROW_IMUX44_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN25", + "CLK_HROW_IMUX36_2", + "CLK_HROW_BUFHCE_CE_R9", + "CLK_HROW_LH12_5", + "CLK_HROW_R_CK_GCLK21", + "CLK_HROW_IMUX35_2", + "CLK_HROW_CK_BUFHCLK_L9", + "CLK_HROW_SW4A1_2", + "CLK_HROW_WW2A3_7", + "CLK_HROW_CLK0_1", + "CLK_HROW_CK_IN_R7", + "CLK_HROW_IMUX0_7", + "CLK_HROW_CLK1_5", + "CLK_HROW_LH6_4", + "CLK_HROW_WW4C3_6", + "CLK_HROW_BUFHCE_CE_R0", + "CLK_HROW_CK_GCLK_TEST_IN10", + "CLK_HROW_IMUX17_2", + "CLK_HROW_CK_GCLK_TEST_IN8", + "CLK_HROW_NW4END2_5", + "CLK_HROW_LOGIC_OUTS_B16_1", + "CLK_HROW_CK_IN_L0", + "CLK_HROW_WW4END3_1", + "CLK_HROW_IMUX15_3", + "CLK_HROW_NW4A0_3", + "CLK_HROW_IMUX9_4", + "CLK_HROW_NW4A1_1", + "CLK_HROW_LOGIC_OUTS_B12_2", + "CLK_HROW_IMUX44_3", + "CLK_HROW_BLOCK_OUTS_B3_7", + "CLK_HROW_EL1BEG0_4", + "CLK_HROW_FAN5_1", + "CLK_HROW_WW4B3_1", + "CLK_HROW_CK_GCLK_TEST_OUT12", + "CLK_HROW_CK_GCLK_TEST_IN3", + "CLK_HROW_SW2A0_6", + "CLK_HROW_CK_GCLK_TEST22", + "CLK_HROW_EE4B3_5", + "CLK_HROW_EE2A2_4", + "CLK_HROW_CK_GCLK_OUT_TEST1", + "CLK_HROW_IMUX6_6", + "CLK_HROW_EE4BEG1_4", + "CLK_HROW_NE2A3_3", + "CLK_HROW_IMUX27_5", + "CLK_HROW_CK_GCLK_IN_TEST20", + "CLK_HROW_NE2A3_4", + "CLK_HROW_EL1BEG3_5", + "CLK_HROW_CK_BUFHCLK_L4", + "CLK_HROW_BUFHCE_CE_L8", + "CLK_HROW_CLK1_4", + "CLK_HROW_LOGIC_OUTS_B2_7", + "CLK_HROW_BYP0_7", + "CLK_HROW_IMUX25_0", + "CLK_HROW_WW4A1_5", + "CLK_HROW_MONITOR_P_1", + "CLK_HROW_LH1_6", + "CLK_HROW_WW4END2_0", + "CLK_HROW_CK_MUX_OUT_L6", + "CLK_HROW_CK_GCLK_TEST_OUT24", + "CLK_HROW_NW2A1_5", + "CLK_HROW_CK_GCLK_TEST8", + "CLK_HROW_NW4END1_5", + "CLK_HROW_WW4C1_6", + "CLK_HROW_LOGIC_OUTS_B6_2", + "CLK_HROW_IMUX18_7", + "CLK_HROW_EE4A0_1", + "CLK_HROW_SE2A1_6", + "CLK_HROW_IMUX46_7", + "CLK_HROW_IMUX9_2", + "CLK_HROW_IMUX26_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "CLK_HROW_LOGIC_OUTS_B21_5", + "CLK_HROW_EE4A2_3", + "CLK_HROW_FAN6_0", + "CLK_HROW_CK_IN_R12", + "CLK_HROW_EE4B0_4", + "CLK_HROW_SW4END0_4", + "CLK_HROW_IMUX16_2", + "CLK_HROW_IMUX26_1", + "CLK_HROW_EE2BEG3_1", + "CLK_HROW_EE4A2_0", + "CLK_HROW_EE4B3_0", + "CLK_HROW_LH4_0", + "CLK_HROW_ER1BEG0_5", + "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "CLK_HROW_CK_BUFHCLK_L2", + "CLK_HROW_CTRL0_1", + "CLK_HROW_EE4BEG3_4", + "CLK_HROW_NE2A1_3", + "CLK_HROW_SE2A0_3", + "CLK_HROW_IMUX7_6", + "CLK_HROW_LH12_1", + "CLK_HROW_WW2END3_3", + "CLK_HROW_NW2A0_6", + "CLK_HROW_NE4C0_0", + "CLK_HROW_IMUX28_5", + "CLK_HROW_SW4A1_7", + "CLK_HROW_LH11_2", + "CLK_HROW_CK_MUX_OUT_R8", + "CLK_HROW_LOGIC_OUTS_B9_1", + "CLK_HROW_NE2A0_0", + "CLK_HROW_EE4A0_6", + "CLK_HROW_NE2A0_7", + "CLK_HROW_EE4C0_1", + "CLK_HROW_IMUX0_4", + "CLK_HROW_EE4C3_7", + "CLK_HROW_IMUX24_4", + "CLK_HROW_CLK0_7", + "CLK_HROW_NE4BEG0_1", + "CLK_HROW_BYP2_5", + "CLK_HROW_WW2A0_4", + "CLK_HROW_R_CK_GCLK5", + "CLK_HROW_IMUX34_3", + "CLK_HROW_LOGIC_OUTS_B1_3", + "CLK_HROW_WL1END3_0", + "CLK_HROW_BLOCK_OUTS_B2_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "CLK_HROW_SE4BEG2_3", + "CLK_HROW_EE4A3_4", + "CLK_HROW_EE2A1_2", + "CLK_HROW_LH2_7", + "CLK_HROW_EE2A0_1", + "CLK_HROW_EE2BEG2_2", + "CLK_HROW_WL1END0_1", + "CLK_HROW_BYP6_0", + "CLK_HROW_NE4BEG3_4", + "CLK_HROW_LOGIC_OUTS_B13_7", + "CLK_HROW_CK_GCLK_TEST27", + "CLK_HROW_EE4C2_2", + "CLK_HROW_IMUX38_5", + "CLK_HROW_LOGIC_OUTS_B14_5", + "CLK_HROW_LH3_2", + "CLK_HROW_BLOCK_OUTS_B2_1", + "CLK_HROW_CE_INT_BOT5", + "CLK_HROW_SW4A0_2", + "CLK_HROW_R_CK_GCLK11", + "CLK_HROW_CK_BUFHCLK_R3", + "CLK_HROW_CK_GCLK_OUT_TEST17", + "CLK_HROW_CK_GCLK_OUT_TEST28", + "CLK_HROW_CK_GCLK_TEST_IN26", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN30", + "CLK_HROW_SE4C1_4", + "CLK_HROW_WW4B2_6", + "CLK_HROW_LOGIC_OUTS_B7_2", + "CLK_HROW_LH2_1", + "CLK_HROW_SW4A1_5", + "CLK_HROW_R_CK_GCLK25", + "CLK_HROW_FAN2_5", + "CLK_HROW_WW2A1_4", + "CLK_HROW_CK_GCLK_OUT_TEST29", + "CLK_HROW_WW4C1_3", + "CLK_HROW_LOGIC_OUTS_B13_5", + "CLK_HROW_IMUX14_7", + "CLK_HROW_NW4A3_6", + "CLK_HROW_EE4C2_3", + "CLK_HROW_CK_GCLK_IN_TEST31", + "CLK_HROW_NE2A3_7", + "CLK_HROW_EL1BEG0_3", + "CLK_HROW_CK_MUX_OUT_R4", + "CLK_HROW_CK_GCLK_IN_TEST18", + "CLK_HROW_LOGIC_OUTS_B22_4", + "CLK_HROW_WW4A0_0", + "CLK_HROW_WW2A3_3", + "CLK_HROW_CTRL1_7", + "CLK_HROW_IMUX18_5", + "CLK_HROW_IMUX31_7", + "CLK_HROW_NW2A3_1", + "CLK_HROW_R_CK_GCLK30", + "CLK_HROW_EE4C1_3", + "CLK_HROW_FAN6_4", + "CLK_HROW_WW2A1_2", + "CLK_HROW_IMUX47_2", + "CLK_HROW_IMUX16_0", + "CLK_HROW_CK_GCLK_OUT_TEST9", + "CLK_HROW_CK_GCLK_OUT_TEST6", + "CLK_HROW_IMUX21_0", + "CLK_HROW_EE4C0_3", + "CLK_HROW_FAN5_3", + "CLK_HROW_NE2A3_0", + "CLK_HROW_SE4BEG0_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "CLK_HROW_SW4A2_0", + "CLK_HROW_BUFHCE_CE_R10", + "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "CLK_HROW_LOGIC_OUTS_B14_6", + "CLK_HROW_CK_IN_L3", + "CLK_HROW_WW2END1_7", + "CLK_HROW_SW4END3_7", + "CLK_HROW_IMUX33_7", + "CLK_HROW_CK_HCLK_OUT_R3", + "CLK_HROW_WW4C0_5", + "CLK_HROW_SE4C1_6", + "CLK_HROW_SW4END2_7", + "CLK_HROW_CK_BUFRCLK_L3", + "CLK_HROW_LOGIC_OUTS_B14_4", + "CLK_HROW_LH2_2", + "CLK_HROW_NE4BEG0_4", + "CLK_HROW_WW4B1_7", + "CLK_HROW_WW4END3_6", + "CLK_HROW_EE4BEG0_0", + "CLK_HROW_CTRL1_0", + "CLK_HROW_CK_HCLK_OUT_R9", + "CLK_HROW_WW4A2_5", + "CLK_HROW_EE4BEG2_1", + "CLK_HROW_BLOCK_OUTS_B1_6", + "CLK_HROW_IMUX24_7", + "CLK_HROW_WL1END2_6", + "CLK_HROW_LOGIC_OUTS_B18_6", + "CLK_HROW_IMUX43_0", + "CLK_HROW_NW2A0_3", + "CLK_HROW_IMUX22_5", + "CLK_HROW_EE4B3_3", + "CLK_HROW_NE2A0_5", + "CLK_HROW_LH7_1", + "CLK_HROW_LOGIC_OUTS_B8_3", + "CLK_HROW_SE4BEG3_3", + "CLK_HROW_LOGIC_OUTS_B11_3", + "CLK_HROW_SW4A0_1", + "CLK_HROW_SW4END2_3", + "CLK_HROW_EE4BEG2_6", + "CLK_HROW_LH8_3", + "CLK_HROW_NE4C0_5", + "CLK_HROW_LOGIC_OUTS_B17_3", + "CLK_HROW_EE4C3_3", + "CLK_HROW_EE2BEG0_5", + "CLK_HROW_IMUX42_2", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN18", + "CLK_HROW_SE2A0_6", + "CLK_HROW_CK_GCLK_OUT_TEST30", + "CLK_HROW_LOGIC_OUTS_B15_0", + "CLK_HROW_WW4C1_4", + "CLK_HROW_CK_MUX_OUT_L4", + "CLK_HROW_CK_MUX_OUT_L2", + "CLK_HROW_NW4END0_4", + "CLK_HROW_EE4A2_5", + "CLK_HROW_BLOCK_OUTS_B3_2", + "CLK_HROW_IMUX5_6", + "CLK_HROW_EE2BEG2_6", + "CLK_HROW_WW4A3_3", + "CLK_HROW_WW4C2_3", + "CLK_HROW_WW4B0_2", + "CLK_HROW_EL1BEG3_0", + "CLK_HROW_CTRL0_6", + "CLK_HROW_EE4B0_1", + "CLK_HROW_WW4A0_6", + "CLK_HROW_LH12_2", + "CLK_HROW_LOGIC_OUTS_B16_3", + "CLK_HROW_WW2A0_1", + "CLK_HROW_IMUX1_4", + "CLK_HROW_NE4BEG3_5", + "CLK_HROW_REFCK_EASTCLK0", + "CLK_HROW_WW2END3_2", + "CLK_HROW_LOGIC_OUTS_B21_7", + "CLK_HROW_IMUX1_5", + "CLK_HROW_NE2A0_4", + "CLK_HROW_IMUX40_3", + "CLK_HROW_IMUX16_4", + "CLK_HROW_EL1BEG2_7", + "CLK_HROW_IMUX45_2", + "CLK_HROW_LH9_7", + "CLK_HROW_NW4END2_4", + "CLK_HROW_WW2END0_6", + "CLK_HROW_NW4END1_6", + "CLK_HROW_FAN2_0", + "CLK_HROW_SE4BEG0_2", + "CLK_HROW_LOGIC_OUTS_B20_6", + "CLK_HROW_LOGIC_OUTS_B19_1", + "CLK_HROW_IMUX12_6", + "CLK_HROW_IMUX35_3", + "CLK_HROW_CK_GCLK_TEST_IN31", + "CLK_HROW_WW4B2_4", + "CLK_HROW_NE2A2_7", + "CLK_HROW_MONITOR_N_3", + "CLK_HROW_FAN7_6", + "CLK_HROW_FAN1_2", + "CLK_HROW_CK_BUFRCLK_L0", + "CLK_HROW_BYP4_1", + "CLK_HROW_BYP5_6", + "CLK_HROW_LH6_1", + "CLK_HROW_LOGIC_OUTS_B4_5", + "CLK_HROW_NE2A1_6", + "CLK_HROW_SE2A1_7", + "CLK_HROW_CK_BUFRCLK_R0", + "CLK_HROW_IMUX7_7", + "CLK_HROW_SW4A2_5", + "CLK_HROW_NW4A1_6", + "CLK_HROW_EE4BEG3_2", + "CLK_HROW_IMUX0_1", + "CLK_HROW_CK_MUX_OUT_R11", + "CLK_HROW_IMUX41_7", + "CLK_HROW_WW4A1_7", + "CLK_HROW_IMUX46_6", + "CLK_HROW_LH12_6", + "CLK_HROW_IMUX26_4", + "CLK_HROW_EE2BEG1_4", + "CLK_HROW_NW2A0_2", + "CLK_HROW_IMUX29_7", + "CLK_HROW_CE_INT_BOT9", + "CLK_HROW_CLK0_0", + "CLK_HROW_NE2A2_1", + "CLK_HROW_BYP0_1", + "CLK_HROW_NE4C0_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN28", + "CLK_HROW_BYP4_7", + "CLK_HROW_SE4BEG1_2", + "CLK_HROW_IMUX27_7", + "CLK_HROW_WW4END0_7", + "CLK_HROW_LOGIC_OUTS_B20_0", + "CLK_HROW_LOGIC_OUTS_B1_0", + "CLK_HROW_CTRL0_7", + "CLK_HROW_WW4A0_7", + "CLK_HROW_EE4C2_6", + "CLK_HROW_CK_GCLK_OUT_TEST12", + "CLK_HROW_WW4A2_4", + "CLK_HROW_CK_GCLK_TEST_OUT20", + "CLK_HROW_IMUX21_2", + "CLK_HROW_BYP7_6", + "CLK_HROW_CK_IN_L12", + "CLK_HROW_IMUX3_1", + "CLK_HROW_EE4A3_6", + "CLK_HROW_IMUX20_3", + "CLK_HROW_CK_GCLK_TEST_IN18", + "CLK_HROW_LOGIC_OUTS_B7_4", + "CLK_HROW_IMUX24_5", + "CLK_HROW_BUFHCE_CE_L6", + "CLK_HROW_IMUX47_6", + "CLK_HROW_LOGIC_OUTS_B6_5", + "CLK_HROW_CK_GCLK_OUT_TEST20", + "CLK_HROW_IMUX20_5", + "CLK_HROW_LH8_5", + "CLK_HROW_SE4BEG1_0", + "CLK_HROW_CK_GCLK_OUT_TEST4", + "CLK_HROW_IMUX14_0", + "CLK_HROW_NE4C2_3", + "CLK_HROW_WW2END0_7", + "CLK_HROW_WW2A3_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "CLK_HROW_LOGIC_OUTS_B20_7", + "CLK_HROW_WR1END2_5", + "CLK_HROW_SE4BEG3_7", + "CLK_HROW_SW4A0_5", + "CLK_HROW_FAN0_4", + "CLK_HROW_CTRL0_5", + "CLK_HROW_NE4C2_7", + "CLK_HROW_EE4A1_2", + "CLK_HROW_LOGIC_OUTS_B0_4", + "CLK_HROW_LOGIC_OUTS_B6_1", + "CLK_HROW_IMUX37_4", + "CLK_HROW_CK_MUX_OUT_L7", + "CLK_HROW_IMUX22_7", + "CLK_HROW_WW4END1_2", + "CLK_HROW_CK_GCLK_TEST_IN15", + "CLK_HROW_BYP1_0", + "CLK_HROW_WW4B3_2", + "CLK_HROW_CK_GCLK_OUT_TEST19", + "CLK_HROW_LH5_7", + "CLK_HROW_WL1END2_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "CLK_HROW_BYP3_3", + "CLK_HROW_SE4BEG2_5", + "CLK_HROW_LOGIC_OUTS_B19_4", + "CLK_HROW_R_CK_GCLK8", + "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "CLK_HROW_CK_GCLK_TEST7", + "CLK_HROW_IMUX5_2", + "CLK_HROW_BLOCK_OUTS_B3_4", + "CLK_HROW_EE4BEG3_7", + "CLK_HROW_CK_GCLK_OUT_TEST11", + "CLK_HROW_LOGIC_OUTS_B0_0", + "CLK_HROW_SW4A3_3", + "CLK_HROW_BYP5_2", + "CLK_HROW_NW2A1_3", + "CLK_HROW_WW4B0_5", + "CLK_HROW_WR1END1_1", + "CLK_HROW_SE4BEG0_6", + "CLK_HROW_NE4C3_6", + "CLK_HROW_SE2A1_1", + "CLK_HROW_IMUX29_2", + "CLK_HROW_CK_GCLK_TEST_OUT1", + "CLK_HROW_CK_GCLK_TEST_OUT29", + "CLK_HROW_NW2A2_0", + "CLK_HROW_LOGIC_OUTS_B13_3", + "CLK_HROW_IMUX36_0", + "CLK_HROW_WW4C3_5", + "CLK_HROW_IMUX1_0", + "CLK_HROW_LH11_1", + "CLK_HROW_NW2A2_3", + "CLK_HROW_LH11_6", + "CLK_HROW_CK_HCLK_OUT_R8", + "CLK_HROW_IMUX3_4", + "CLK_HROW_IMUX3_6", + "CLK_HROW_EE2A1_0", + "CLK_HROW_CK_GCLK_IN_TEST5", + "CLK_HROW_LOGIC_OUTS_B5_6", + "CLK_HROW_FAN3_1", + "CLK_HROW_WL1END0_6", + "CLK_HROW_NE4BEG2_2", + "CLK_HROW_LOGIC_OUTS_B14_7", + "CLK_HROW_IMUX11_6", + "CLK_HROW_SE4BEG0_0", + "CLK_HROW_SW4END1_5", + "CLK_HROW_FAN6_5", + "CLK_HROW_IMUX23_1", + "CLK_HROW_IMUX29_5", + "CLK_HROW_EE2A0_4", + "CLK_HROW_SW4A3_7", + "CLK_HROW_WW4C2_6", + "CLK_HROW_WR1END2_1", + "CLK_HROW_WW4A1_2", + "CLK_HROW_CK_INT_0_1", + "CLK_HROW_IMUX4_3", + "CLK_HROW_IMUX45_4", + "CLK_HROW_SE4BEG1_4", + "CLK_HROW_WW4END2_5", + "CLK_HROW_WW4B2_5", + "CLK_HROW_EE4B1_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN6", + "CLK_HROW_SE2A0_0", + "CLK_HROW_LOGIC_OUTS_B9_4", + "CLK_HROW_SW4END0_7", + "CLK_HROW_WW4END3_7", + "CLK_HROW_LOGIC_OUTS_B17_5", + "CLK_HROW_SW4A0_3", + "CLK_HROW_BYP4_5", + "CLK_HROW_CTRL1_2", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN31", + "CLK_HROW_SE4C0_2", + "CLK_HROW_SE2A1_5", + "CLK_HROW_SE4BEG2_4", + "CLK_HROW_LOGIC_OUTS_B4_3", + "CLK_HROW_EE2BEG0_6", + "CLK_HROW_EE4A0_3", + "CLK_HROW_IMUX40_5", + "CLK_HROW_NE4BEG2_4", + "CLK_HROW_WW2A2_0", + "CLK_HROW_EE4C3_5", + "CLK_HROW_LOGIC_OUTS_B22_3", + "CLK_HROW_CK_INT_0_0", + "CLK_HROW_ER1BEG1_1", + "CLK_HROW_IMUX7_2", + "CLK_HROW_R_CK_GCLK27", + "CLK_HROW_CK_BUFRCLK_L2", + "CLK_HROW_NE4C2_5", + "CLK_HROW_NW4A3_2", + "CLK_HROW_LOGIC_OUTS_B2_5", + "CLK_HROW_CK_IN_L2", + "CLK_HROW_FAN0_5", + "CLK_HROW_IMUX23_2", + "CLK_HROW_IMUX34_6", + "CLK_HROW_NW4A3_1", + "CLK_HROW_NW4END2_6", + "CLK_HROW_EL1BEG2_6", + "CLK_HROW_IMUX11_1", + "CLK_HROW_IMUX13_0", + "CLK_HROW_NE4C1_5", + "CLK_HROW_IMUX25_1", + "CLK_HROW_NW4END2_0", + "CLK_HROW_BYP0_6", + "CLK_HROW_BYP2_2", + "CLK_HROW_IMUX14_6", + "CLK_HROW_LH3_5", + "CLK_HROW_FAN1_5", + "CLK_HROW_LOGIC_OUTS_B4_6", + "CLK_HROW_IMUX9_5", + "CLK_HROW_EE2A3_0", + "CLK_HROW_MONITOR_P_5", + "CLK_HROW_LOGIC_OUTS_B8_7", + "CLK_HROW_BYP4_4", + "CLK_HROW_EE4BEG3_3", + "CLK_HROW_IMUX40_7", + "CLK_HROW_LOGIC_OUTS_B1_6", + "CLK_HROW_IMUX22_3", + "CLK_HROW_WW4C2_2", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN16", + "CLK_HROW_CTRL1_3", + "CLK_HROW_CK_GCLK_IN_TEST11", + "CLK_HROW_CK_GCLK_OUT_TEST25", + "CLK_HROW_ER1BEG3_6", + "CLK_HROW_LOGIC_OUTS_B12_1", + "CLK_HROW_R_CK_GCLK14", + "CLK_HROW_NE2A1_4", + "CLK_HROW_EE4C1_5", + "CLK_HROW_IMUX19_6", + "CLK_HROW_IMUX15_6", + "CLK_HROW_NE2A2_6", + "CLK_HROW_EE4BEG2_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN5", + "CLK_HROW_NW4END3_1", + "CLK_HROW_EE2A2_3", + "CLK_HROW_CK_GCLK_IN_TEST15", + "CLK_HROW_CK_IN_L1", + "CLK_HROW_IMUX28_0", + "CLK_HROW_SE4C3_4", + "CLK_HROW_SW4A1_1", + "CLK_HROW_R_CK_GCLK3", + "CLK_HROW_EL1BEG0_7", + "CLK_HROW_NE2A1_5", + "CLK_HROW_EE2A1_4", + "CLK_HROW_EE4C3_4", + "CLK_HROW_ER1BEG1_3", + "CLK_HROW_EE4A1_3", + "CLK_HROW_LOGIC_OUTS_B4_2", + "CLK_HROW_IMUX45_1", + "CLK_HROW_SW4A3_6", + "CLK_HROW_ER1BEG3_5", + "CLK_HROW_CK_MUX_OUT_L10", + "CLK_HROW_NE2A3_1", + "CLK_HROW_IMUX17_5", + "CLK_HROW_BUFHCE_CE_L4", + "CLK_HROW_IMUX11_3", + "CLK_HROW_WW2END2_0", + "CLK_HROW_LH1_4", + "CLK_HROW_NW2A3_5", + "CLK_HROW_IMUX13_7", + "CLK_HROW_NW4END3_2", + "CLK_HROW_LH3_0", + "CLK_HROW_BLOCK_OUTS_B3_5", + "CLK_HROW_WW4A2_3", + "CLK_HROW_IMUX25_5", + "CLK_HROW_BYP7_2", + "CLK_HROW_EE2A1_3", + "CLK_HROW_LOGIC_OUTS_B13_6", + "CLK_HROW_LOGIC_OUTS_B12_6", + "CLK_HROW_WW4END2_4", + "CLK_HROW_CK_IN_L7", + "CLK_HROW_MONITOR_N_4", + "CLK_HROW_WL1END2_5", + "CLK_HROW_FAN0_7", + "CLK_HROW_SW2A2_6", + "CLK_HROW_WW4A3_5", + "CLK_HROW_IMUX44_1", + "CLK_HROW_SW4END2_6", + "CLK_HROW_EL1BEG1_2", + "CLK_HROW_IMUX5_0", + "CLK_HROW_IMUX19_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN20", + "CLK_HROW_SW2A0_7", + "CLK_HROW_LOGIC_OUTS_B18_5", + "CLK_HROW_NW4A0_5", + "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "CLK_HROW_IMUX28_6", + "CLK_HROW_BUFHCE_CE_R1", + "CLK_HROW_IMUX19_3", + "CLK_HROW_CK_GCLK_OUT_TEST23", + "CLK_HROW_IMUX34_1", + "CLK_HROW_CK_IN_R8", + "CLK_HROW_BYP1_7", + "CLK_HROW_IMUX31_6", + "CLK_HROW_IMUX14_4", + "CLK_HROW_NE2A0_2", + "CLK_HROW_ER1BEG3_3", + "CLK_HROW_NE4C1_2", + "CLK_HROW_BYP6_4", + "CLK_HROW_LOGIC_OUTS_B5_5", + "CLK_HROW_IMUX28_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "CLK_HROW_WR1END1_5", + "CLK_HROW_BLOCK_OUTS_B3_3", + "CLK_HROW_WL1END2_2", + "CLK_HROW_IMUX6_3", + "CLK_HROW_IMUX24_1", + "CLK_HROW_IMUX22_4", + "CLK_HROW_WW4C0_3", + "CLK_HROW_CK_GCLK_IN_TEST21", + "CLK_HROW_WW4A1_4", + "CLK_HROW_NE2A3_6", + "CLK_HROW_IMUX6_7", + "CLK_HROW_SE2A0_2", + "CLK_HROW_IMUX2_7", + "CLK_HROW_CK_GCLK_TEST28", + "CLK_HROW_IMUX23_6", + "CLK_HROW_NW2A2_2", + "CLK_HROW_NE4BEG0_7", + "CLK_HROW_CE_INT_BOT3", + "CLK_HROW_CK_BUFHCLK_R7", + "CLK_HROW_EE4C3_6", + "CLK_HROW_EE2A1_5", + "CLK_HROW_LH10_7", + "CLK_HROW_LOGIC_OUTS_B23_1", + "CLK_HROW_EE2BEG1_6", + "CLK_HROW_BYP4_0", + "CLK_HROW_IMUX43_2", + "CLK_HROW_CE_INT_TOP8", + "CLK_HROW_IMUX11_5", + "CLK_HROW_EE4BEG1_0", + "CLK_HROW_NW4END3_0", + "CLK_HROW_LOGIC_OUTS_B10_1", + "CLK_HROW_IMUX13_5", + "CLK_HROW_IMUX19_1", + "CLK_HROW_CK_BUFHCLK_R10", + "CLK_HROW_R_CK_GCLK9", + "CLK_HROW_WR1END0_7", + "CLK_HROW_IMUX2_2", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN15", + "CLK_HROW_FAN3_3", + "CLK_HROW_IMUX4_6", + "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN0", + "CLK_HROW_LOGIC_OUTS_B16_4", + "CLK_HROW_CK_GCLK_IN_TEST7", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN11", + "CLK_HROW_LOGIC_OUTS_B3_2", + "CLK_HROW_EL1BEG1_5", + "CLK_HROW_IMUX32_4", + "CLK_HROW_EE4C3_1", + "CLK_HROW_IMUX17_6", + "CLK_HROW_IMUX36_3", + "CLK_HROW_LH4_5", + "CLK_HROW_IMUX7_5", + "CLK_HROW_LOGIC_OUTS_B2_2", + "CLK_HROW_IMUX20_4", + "CLK_HROW_SE4C3_1", + "CLK_HROW_BUFHCE_CE_R3", + "CLK_HROW_FAN4_3", + "CLK_HROW_LOGIC_OUTS_B14_2", + "CLK_HROW_FAN0_2", + "CLK_HROW_WW4A2_0", + "CLK_HROW_CK_INT_1_1", + "CLK_HROW_CK_IN_L6", + "CLK_HROW_LOGIC_OUTS_B11_5", + "CLK_HROW_NE4C2_6", + "CLK_HROW_SE2A1_4", + "CLK_HROW_CK_HCLK_OUT_L11", + "CLK_HROW_IMUX16_6", + "CLK_HROW_BYP6_6", + "CLK_HROW_NE4BEG1_4", + "CLK_HROW_NE2A2_0", + "CLK_HROW_SE2A3_7", + "CLK_HROW_IMUX33_6", + "CLK_HROW_CK_IN_L13", + "CLK_HROW_EE4C1_6", + "CLK_HROW_WL1END1_6", + "CLK_HROW_R_CK_GCLK12", + "CLK_HROW_NW4A1_7", + "CLK_HROW_LOGIC_OUTS_B3_1", + "CLK_HROW_LOGIC_OUTS_B3_0", + "CLK_HROW_NE4C3_3", + "CLK_HROW_SW4A3_0", + "CLK_HROW_CK_MUX_OUT_R10", + "CLK_HROW_BLOCK_OUTS_B1_5", + "CLK_HROW_LOGIC_OUTS_B18_0", + "CLK_HROW_LH3_7", + "CLK_HROW_IMUX35_0", + "CLK_HROW_LOGIC_OUTS_B15_6", + "CLK_HROW_IMUX36_7", + "CLK_HROW_NE4BEG3_0", + "CLK_HROW_R_CK_GCLK1", + "CLK_HROW_IMUX47_3", + "CLK_HROW_CK_GCLK_OUT_TEST27", + "CLK_HROW_SE4BEG0_1", + "CLK_HROW_SW2A1_4", + "CLK_HROW_EE4C1_4", + "CLK_HROW_BYP3_5", + "CLK_HROW_WR1END2_2", + "CLK_HROW_CK_HCLK_OUT_L5", + "CLK_HROW_EE4A3_2", + "CLK_HROW_NW4END1_4", + "CLK_HROW_FAN3_6", + "CLK_HROW_LOGIC_OUTS_B22_6", + "CLK_HROW_EE2BEG0_1", + "CLK_HROW_WW2END1_2", + "CLK_HROW_NE4BEG0_0", + "CLK_HROW_EE4B2_5", + "CLK_HROW_CK_MUX_OUT_R9", + "CLK_HROW_CK_GCLK_TEST_OUT8", + "CLK_HROW_EE4B1_6", + "CLK_HROW_NE2A1_1", + "CLK_HROW_CK_GCLK_IN_TEST30", + "CLK_HROW_NE4C3_0", + "CLK_HROW_EE4C2_1", + "CLK_HROW_CK_HCLK_OUT_L8", + "CLK_HROW_LOGIC_OUTS_B0_3", + "CLK_HROW_NW2A0_4", + "CLK_HROW_R_CK_GCLK7", + "CLK_HROW_LOGIC_OUTS_B8_0", + "CLK_HROW_SE4BEG1_7", + "CLK_HROW_CE_INT_TOP1", + "CLK_HROW_IMUX1_1" + ], + "pips": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST18->CLK_HROW_CK_GCLK_TEST_IN18": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX3_4->CLK_HROW_CE_INT_TOP3": { + "src_wire": "CLK_HROW_IMUX3_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT3->CLK_HROW_CK_GCLK_OUT_TEST3": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX2_3->CLK_HROW_CE_INT_BOT2": { + "src_wire": "CLK_HROW_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX6_3->CLK_HROW_CE_INT_BOT6": { + "src_wire": "CLK_HROW_IMUX6_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT28->CLK_HROW_CK_GCLK_OUT_TEST28": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN28->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT11->CLK_HROW_CK_GCLK_OUT_TEST11": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT27->CLK_HROW_CK_GCLK_OUT_TEST27": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L7->>CLK_HROW_CK_HCLK_OUT_L7": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST22->CLK_HROW_CK_GCLK_TEST_IN22": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST9->CLK_HROW_CK_GCLK_TEST_IN9": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L3->>CLK_HROW_CK_HCLK_OUT_L3": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT8->>CLK_HROW_BUFHCE_CE_L2": { + "src_wire": "CLK_HROW_CE_INT_BOT8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST16->CLK_HROW_CK_GCLK_TEST_IN16": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT21->CLK_HROW_CK_GCLK_OUT_TEST21": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R9->>CLK_HROW_CK_HCLK_OUT_R9": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R1->>CLK_HROW_CK_BUFHCLK_R1": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT5->>CLK_HROW_BUFHCE_CE_R5": { + "src_wire": "CLK_HROW_CE_INT_BOT5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN26->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_TEST_IN->CLK_HROW_CK_IN_L_IN_TEST": { + "src_wire": "CLK_HROW_CK_IN_L_TEST_IN", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_L_IN_TEST", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN17->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R7->>CLK_HROW_CK_BUFHCLK_R7": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L1->>CLK_HROW_CK_BUFHCLK_L1": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT14->CLK_HROW_CK_GCLK_OUT_TEST14": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L10->>CLK_HROW_CK_BUFHCLK_L10": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST15->CLK_HROW_CK_GCLK_TEST_IN15": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN22->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT17->CLK_HROW_CK_GCLK_OUT_TEST17": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP11->>CLK_HROW_BUFHCE_CE_R11": { + "src_wire": "CLK_HROW_CE_INT_TOP11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX8_3->CLK_HROW_CE_INT_BOT8": { + "src_wire": "CLK_HROW_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT0->>CLK_HROW_BUFHCE_CE_R0": { + "src_wire": "CLK_HROW_CE_INT_BOT0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L4->>CLK_HROW_CK_HCLK_OUT_L4": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST3->CLK_HROW_CK_GCLK_TEST_IN3": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST31->CLK_HROW_CK_GCLK_TEST_IN31": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN14->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST21->CLK_HROW_CK_GCLK_TEST_IN21": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST28->CLK_HROW_CK_GCLK_TEST_IN28": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST27->CLK_HROW_CK_GCLK_TEST_IN27": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX3_3->CLK_HROW_CE_INT_BOT3": { + "src_wire": "CLK_HROW_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L6->>CLK_HROW_CK_BUFHCLK_L6": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST19->CLK_HROW_CK_GCLK_TEST_IN19": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP0->>CLK_HROW_BUFHCE_CE_L6": { + "src_wire": "CLK_HROW_CE_INT_TOP0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R10->>CLK_HROW_CK_BUFHCLK_R10": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_OUT_TEST->CLK_HROW_CK_IN_L_TEST_OUT": { + "src_wire": "CLK_HROW_CK_IN_L_OUT_TEST", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_L_TEST_OUT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST13->CLK_HROW_CK_GCLK_TEST_IN13": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT1->>CLK_HROW_BUFHCE_CE_R1": { + "src_wire": "CLK_HROW_CE_INT_BOT1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX11_4->CLK_HROW_CE_INT_TOP11": { + "src_wire": "CLK_HROW_IMUX11_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST5->CLK_HROW_CK_GCLK_TEST_IN5": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST29->CLK_HROW_CK_GCLK_TEST_IN29": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP6->>CLK_HROW_BUFHCE_CE_R6": { + "src_wire": "CLK_HROW_CE_INT_TOP6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT31->CLK_HROW_CK_GCLK_OUT_TEST31": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX5_4->CLK_HROW_CE_INT_TOP5": { + "src_wire": "CLK_HROW_IMUX5_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R2->>CLK_HROW_CK_HCLK_OUT_R2": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST24->CLK_HROW_CK_GCLK_TEST_IN24": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP5->>CLK_HROW_BUFHCE_CE_L11": { + "src_wire": "CLK_HROW_CE_INT_TOP5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX7_3->CLK_HROW_CE_INT_BOT7": { + "src_wire": "CLK_HROW_IMUX7_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L11->>CLK_HROW_CK_HCLK_OUT_L11": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L6->>CLK_HROW_CK_HCLK_OUT_L6": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT16->CLK_HROW_CK_GCLK_OUT_TEST16": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT20->CLK_HROW_CK_GCLK_OUT_TEST20": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST12->CLK_HROW_CK_GCLK_TEST_IN12": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX4_4->CLK_HROW_CE_INT_TOP4": { + "src_wire": "CLK_HROW_IMUX4_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L8->>CLK_HROW_CK_HCLK_OUT_L8": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT24->CLK_HROW_CK_GCLK_OUT_TEST24": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX10_3->CLK_HROW_CE_INT_BOT10": { + "src_wire": "CLK_HROW_IMUX10_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX2_4->CLK_HROW_CE_INT_TOP2": { + "src_wire": "CLK_HROW_IMUX2_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX5_3->CLK_HROW_CE_INT_BOT5": { + "src_wire": "CLK_HROW_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L5->>CLK_HROW_CK_BUFHCLK_L5": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX9_3->CLK_HROW_CE_INT_BOT9": { + "src_wire": "CLK_HROW_IMUX9_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST8->CLK_HROW_CK_GCLK_TEST_IN8": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT0->CLK_HROW_CK_GCLK_OUT_TEST0": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L2->>CLK_HROW_CK_BUFHCLK_L2": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT7->>CLK_HROW_BUFHCE_CE_L1": { + "src_wire": "CLK_HROW_CE_INT_BOT7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST26->CLK_HROW_CK_GCLK_TEST_IN26": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CLK1_3->CLK_HROW_CK_INT_0_1": { + "src_wire": "CLK_HROW_CLK1_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP7->>CLK_HROW_BUFHCE_CE_R7": { + "src_wire": "CLK_HROW_CE_INT_TOP7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT9->>CLK_HROW_BUFHCE_CE_L3": { + "src_wire": "CLK_HROW_CE_INT_BOT9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L2->>CLK_HROW_CK_HCLK_OUT_L2": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX4_3->CLK_HROW_CE_INT_BOT4": { + "src_wire": "CLK_HROW_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN20->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT22->CLK_HROW_CK_GCLK_OUT_TEST22": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L5->>CLK_HROW_CK_HCLK_OUT_L5": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT4->>CLK_HROW_BUFHCE_CE_R4": { + "src_wire": "CLK_HROW_CE_INT_BOT4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT2->CLK_HROW_CK_GCLK_OUT_TEST2": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT11->>CLK_HROW_BUFHCE_CE_L5": { + "src_wire": "CLK_HROW_CE_INT_BOT11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX10_4->CLK_HROW_CE_INT_TOP10": { + "src_wire": "CLK_HROW_IMUX10_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP3->>CLK_HROW_BUFHCE_CE_L9": { + "src_wire": "CLK_HROW_CE_INT_TOP3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT25->CLK_HROW_CK_GCLK_OUT_TEST25": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN31->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L9->>CLK_HROW_CK_HCLK_OUT_L9": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R11->>CLK_HROW_CK_BUFHCLK_R11": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_TEST_IN->CLK_HROW_CK_IN_R_IN_TEST": { + "src_wire": "CLK_HROW_CK_IN_R_TEST_IN", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_R_IN_TEST", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST6->CLK_HROW_CK_GCLK_TEST_IN6": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST30->CLK_HROW_CK_GCLK_TEST_IN30": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX8_4->CLK_HROW_CE_INT_TOP8": { + "src_wire": "CLK_HROW_IMUX8_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN25->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R0->>CLK_HROW_CK_BUFHCLK_R0": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R2->>CLK_HROW_CK_BUFHCLK_R2": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L0->>CLK_HROW_CK_BUFHCLK_L0": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT4->CLK_HROW_CK_GCLK_OUT_TEST4": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R8->>CLK_HROW_CK_BUFHCLK_R8": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L3->>CLK_HROW_CK_BUFHCLK_L3": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT3->>CLK_HROW_BUFHCE_CE_R3": { + "src_wire": "CLK_HROW_CE_INT_BOT3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN21->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT2->>CLK_HROW_BUFHCE_CE_R2": { + "src_wire": "CLK_HROW_CE_INT_BOT2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R9->>CLK_HROW_CK_BUFHCLK_R9": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R6->>CLK_HROW_CK_HCLK_OUT_R6": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CLK0_4->CLK_HROW_CK_INT_1_0": { + "src_wire": "CLK_HROW_CLK0_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN27->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R5->>CLK_HROW_CK_BUFHCLK_R5": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT8->CLK_HROW_CK_GCLK_OUT_TEST8": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP8->>CLK_HROW_BUFHCE_CE_R8": { + "src_wire": "CLK_HROW_CE_INT_TOP8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST14->CLK_HROW_CK_GCLK_TEST_IN14": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT18->CLK_HROW_CK_GCLK_OUT_TEST18": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L7->>CLK_HROW_CK_BUFHCLK_L7": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX6_4->CLK_HROW_CE_INT_TOP6": { + "src_wire": "CLK_HROW_IMUX6_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R3->>CLK_HROW_CK_BUFHCLK_R3": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT26->CLK_HROW_CK_GCLK_OUT_TEST26": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT6->CLK_HROW_CK_GCLK_OUT_TEST6": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT10->CLK_HROW_CK_GCLK_OUT_TEST10": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT13->CLK_HROW_CK_GCLK_OUT_TEST13": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST23->CLK_HROW_CK_GCLK_TEST_IN23": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT30->CLK_HROW_CK_GCLK_OUT_TEST30": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT12->CLK_HROW_CK_GCLK_OUT_TEST12": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX7_4->CLK_HROW_CE_INT_TOP7": { + "src_wire": "CLK_HROW_IMUX7_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX0_4->CLK_HROW_CE_INT_TOP0": { + "src_wire": "CLK_HROW_IMUX0_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP4->>CLK_HROW_BUFHCE_CE_L10": { + "src_wire": "CLK_HROW_CE_INT_TOP4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT15->CLK_HROW_CK_GCLK_OUT_TEST15": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT23->CLK_HROW_CK_GCLK_OUT_TEST23": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST11->CLK_HROW_CK_GCLK_TEST_IN11": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L4->>CLK_HROW_CK_BUFHCLK_L4": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN23->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST7->CLK_HROW_CK_GCLK_TEST_IN7": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT10->>CLK_HROW_BUFHCE_CE_L4": { + "src_wire": "CLK_HROW_CE_INT_BOT10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT1->CLK_HROW_CK_GCLK_OUT_TEST1": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT19->CLK_HROW_CK_GCLK_OUT_TEST19": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX9_4->CLK_HROW_CE_INT_TOP9": { + "src_wire": "CLK_HROW_IMUX9_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN16->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R5->>CLK_HROW_CK_HCLK_OUT_R5": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L10->>CLK_HROW_CK_HCLK_OUT_L10": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST25->CLK_HROW_CK_GCLK_TEST_IN25": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN15->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX1_4->CLK_HROW_CE_INT_TOP1": { + "src_wire": "CLK_HROW_IMUX1_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT7->CLK_HROW_CK_GCLK_OUT_TEST7": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX1_3->CLK_HROW_CE_INT_BOT1": { + "src_wire": "CLK_HROW_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST20->CLK_HROW_CK_GCLK_TEST_IN20": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT9->CLK_HROW_CK_GCLK_OUT_TEST9": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN18->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R4->>CLK_HROW_CK_BUFHCLK_R4": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN29->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R11->>CLK_HROW_CK_HCLK_OUT_R11": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP1->>CLK_HROW_BUFHCE_CE_L7": { + "src_wire": "CLK_HROW_CE_INT_TOP1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT6->>CLK_HROW_BUFHCE_CE_L0": { + "src_wire": "CLK_HROW_CE_INT_BOT6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP2->>CLK_HROW_BUFHCE_CE_L8": { + "src_wire": "CLK_HROW_CE_INT_TOP2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R4->>CLK_HROW_CK_HCLK_OUT_R4": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST2->CLK_HROW_CK_GCLK_TEST_IN2": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CLK1_4->CLK_HROW_CK_INT_1_1": { + "src_wire": "CLK_HROW_CLK1_4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L9->>CLK_HROW_CK_BUFHCLK_L9": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L8->>CLK_HROW_CK_BUFHCLK_L8": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST1->CLK_HROW_CK_GCLK_TEST_IN1": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CLK0_3->CLK_HROW_CK_INT_0_0": { + "src_wire": "CLK_HROW_CLK0_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L0->>CLK_HROW_CK_HCLK_OUT_L0": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L1->>CLK_HROW_CK_HCLK_OUT_L1": { + "src_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST17->CLK_HROW_CK_GCLK_TEST_IN17": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN30->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP10->>CLK_HROW_BUFHCE_CE_R10": { + "src_wire": "CLK_HROW_CE_INT_TOP10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN19->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R7": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R10->>CLK_HROW_CK_HCLK_OUT_R10": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R8->>CLK_HROW_CK_HCLK_OUT_R8": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST0->CLK_HROW_CK_GCLK_TEST_IN0": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_OUT_TEST->CLK_HROW_CK_IN_R_TEST_OUT": { + "src_wire": "CLK_HROW_CK_IN_R_OUT_TEST", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_R_TEST_OUT", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP9->>CLK_HROW_BUFHCE_CE_R9": { + "src_wire": "CLK_HROW_CE_INT_TOP9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R7->>CLK_HROW_CK_HCLK_OUT_R7": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R6->>CLK_HROW_CK_BUFHCLK_R6": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT29->CLK_HROW_CK_GCLK_OUT_TEST29": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R0->>CLK_HROW_CK_HCLK_OUT_R0": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST10->CLK_HROW_CK_GCLK_TEST_IN10": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX11_3->CLK_HROW_CE_INT_BOT11": { + "src_wire": "CLK_HROW_IMUX11_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN24->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L6": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST4->CLK_HROW_CK_GCLK_TEST_IN4": { + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L11": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_R0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX0_3->CLK_HROW_CE_INT_BOT0": { + "src_wire": "CLK_HROW_IMUX0_3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R11": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_CK_IN_L3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_L5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_IN_R2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L11->>CLK_HROW_CK_BUFHCLK_L11": { + "src_wire": "CLK_HROW_CK_HCLK_OUT_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L11", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R10": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R1->>CLK_HROW_CK_HCLK_OUT_R1": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_IN_R11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_L7", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L9": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R3": { + "src_wire": "CLK_HROW_CK_IN_R13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R2": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R3->>CLK_HROW_CK_HCLK_OUT_R3": { + "src_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT5->CLK_HROW_CK_GCLK_OUT_TEST5": { + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L8": { + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "src_wire": "CLK_HROW_CK_IN_R8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_R6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R5": { + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "src_wire": "CLK_HROW_CK_IN_L4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "src_wire": "CLK_HROW_CK_IN_L6", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L1": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_R9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L0": { + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L10": { + "src_wire": "CLK_HROW_CK_IN_R4", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R6": { + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L4": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "src_wire": "CLK_HROW_CK_IN_L12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L7": { + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_CK_IN_L10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R4": { + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R0": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "src_wire": "CLK_HROW_CK_IN_L8", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L5": { + "src_wire": "CLK_HROW_CK_IN_L13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "src_wire": "CLK_HROW_CK_IN_R1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R1": { + "src_wire": "CLK_HROW_CK_IN_L9", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "src_wire": "CLK_HROW_CK_IN_L11", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L3": { + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R9": { + "src_wire": "CLK_HROW_CK_IN_R12", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R8": { + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "src_wire": "CLK_HROW_CK_IN_L0", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "is_directional": "1", + "can_invert": "0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L2": { + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CLK_MTBF2.json b/kintex7/tile_type_CLK_MTBF2.json new file mode 100644 index 0000000..c452632 --- /dev/null +++ b/kintex7/tile_type_CLK_MTBF2.json @@ -0,0 +1,365 @@ +{ + "tile_type": "CLK_MTBF2", + "sites": [], + "wires": [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_SW4A1", + "CLK_PMV_BYP2_0", + "CLK_FEED_CK_GCLK31", + "CLK_FEED_CK_BUFG_CASC9", + "CLK_FEED_EL1BEG1", + "CLK_MTBF2_RESET", + "CLK_FEED_WW2END2", + "CLK_PMV_IMUX5_0", + "CLK_PMV_LOGIC_OUTS19_0", + "CLK_PMV_IMUX36_0", + "CLK_PMV_IMUX16_0", + "CLK_FEED_EE2BEG3", + "CLK_PMV_IMUX22_0", + "CLK_PMV_IMUX26_0", + "CLK_FEED_CK_BUFG_CASC16", + "CLK_FEED_CK_GCLK16", + "CLK_FEED_SE4BEG3", + "CLK_FEED_LH1", + "CLK_MTBF2_Q3B", + "CLK_FEED_EE4C2", + "CLK_PMV_IMUX0_0", + "CLK_FEED_CK_GCLK17", + "CLK_FEED_NW4END2", + "CLK_FEED_CK_GCLK5", + "CLK_FEED_NE4BEG3", + "CLK_PMV_IMUX19_0", + "CLK_MTBF2_Q6B", + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_GCLK14", + "CLK_PMV_IMUX2_0", + "CLK_FEED_EE4A2", + "CLK_PMV_IMUX27_0", + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_CK_GCLK21", + "CLK_FEED_EE2A2", + "CLK_FEED_EE4B3", + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_PMV_CTRL1_0", + "CLK_FEED_EE4B0", + "CLK_FEED_EE4A3", + "CLK_PMV_LOGIC_OUTS11_0", + "CLK_FEED_CK_GCLK8", + "CLK_PMV_IMUX33_0", + "CLK_FEED_NW4END0", + "CLK_PMV_IMUX15_0", + "CLK_FEED_R_CK_GCLK20", + "CLK_PMV_LOGIC_OUTS22_0", + "CLK_FEED_CK_BUFG_CASC21", + "CLK_FEED_WW4B0", + "CLK_FEED_CK_BUFG_CASC2", + "CLK_PMV_IMUX40_0", + "CLK_PMV_LOGIC_OUTS17_0", + "CLK_FEED_CK_BUFG_CASC20", + "CLK_PMV_LOGIC_OUTS9_0", + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_ER1BEG1", + "CLK_MTBF2_Q4B", + "CLK_FEED_SE4BEG0", + "CLK_FEED_CK_BUFG_CASC26", + "CLK_FEED_WW4A0", + "CLK_FEED_R_CK_GCLK15", + "CLK_MTBF2_CLK", + "CLK_FEED_WW4B2", + "CLK_FEED_SW2A1", + "CLK_FEED_LH3", + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_PMV_IMUX38_0", + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_GCLK30", + "CLK_PMV_LOGIC_OUTS12_0", + "CLK_PMV_FAN3_0", + "CLK_FEED_WW4END2", + "CLK_FEED_CK_BUFG_CASC1", + "CLK_FEED_EL1BEG3", + "CLK_FEED_SE2A2", + "CLK_PMV_FAN5_0", + "CLK_PMV_LOGIC_OUTS3_0", + "CLK_FEED_NW4END1", + "CLK_FEED_LH8", + "CLK_FEED_LH4", + "CLK_FEED_CK_GCLK29", + "CLK_FEED_CK_GCLK14", + "CLK_FEED_SE4C0", + "CLK_FEED_LH9", + "CLK_FEED_WR1END3", + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_EE4BEG2", + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_CK_GCLK19", + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_CK_GCLK25", + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_WW4END1", + "CLK_PMV_IMUX8_0", + "CLK_FEED_CK_GCLK23", + "CLK_FEED_EE4B1", + "CLK_FEED_CK_BUFG_CASC10", + "CLK_FEED_EE2BEG1", + "CLK_PMV_LOGIC_OUTS20_0", + "CLK_PMV_FAN4_0", + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_SW4A3", + "CLK_PMV_LOGIC_OUTS18_0", + "CLK_FEED_SE4C1", + "CLK_MTBF2_DIN", + "CLK_FEED_NW4A2", + "CLK_FEED_CK_GCLK15", + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_PMV_BYP7_0", + "CLK_FEED_CK_GCLK20", + "CLK_FEED_CK_BUFG_CASC5", + "CLK_PMV_IMUX18_0", + "CLK_FEED_LH11", + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_PMV_BYP5_0", + "CLK_PMV_IMUX25_0", + "CLK_FEED_NE2A1", + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_CK_BUFG_CASC13", + "CLK_FEED_CK_BUFG_CASC18", + "CLK_FEED_CK_GCLK11", + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_CK_GCLK2", + "CLK_PMV_LOGIC_OUTS16_0", + "CLK_PMV_IMUX24_0", + "CLK_FEED_CK_BUFG_CASC11", + "CLK_FEED_CK_GCLK3", + "CLK_FEED_R_CK_GCLK1", + "CLK_MTBF2_Q5B", + "CLK_FEED_CK_BUFG_CASC15", + "CLK_PMV_FAN0_0", + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_CK_BUFG_CASC23", + "CLK_PMV_IMUX44_0", + "CLK_FEED_CK_BUFG_CASC28", + "CLK_PMV_BYP4_0", + "CLK_FEED_MONITOR_P", + "CLK_FEED_WW4A3", + "CLK_FEED_R_CK_GCLK26", + "CLK_PMV_LOGIC_OUTS5_0", + "CLK_FEED_CK_GCLK27", + "CLK_PMV_IMUX23_0", + "CLK_FEED_R_CK_GCLK23", + "CLK_PMV_LOGIC_OUTS1_0", + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_NE4C1", + "CLK_FEED_CK_BUFG_CASC25", + "CLK_FEED_CK_BUFG_CASC6", + "CLK_PMV_IMUX1_0", + "CLK_PMV_IMUX7_0", + "CLK_FEED_CK_GCLK1", + "CLK_FEED_NE2A3", + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_ER1BEG3", + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_CK_BUFG_CASC8", + "CLK_PMV_FAN7_0", + "CLK_PMV_BYP0_0", + "CLK_FEED_CK_BUFG_CASC30", + "CLK_FEED_CK_GCLK22", + "CLK_PMV_CLK0_0", + "CLK_PMV_LOGIC_OUTS7_0", + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_WL1END1", + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_PMV_BYP1_0", + "CLK_FEED_EE2BEG2", + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_PMV_CTRL0_0", + "CLK_FEED_EE4C3", + "CLK_MTBF2_Q1B", + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_PMV_LOGIC_OUTS8_0", + "CLK_PMV_IMUX47_0", + "CLK_FEED_CK_BUFG_CASC3", + "CLK_FEED_SE4C2", + "CLK_FEED_WL1END0", + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_CK_BUFG_CASC17", + "CLK_FEED_EE4BEG0", + "CLK_FEED_CK_BUFG_CASC22", + "CLK_FEED_WW4C2", + "CLK_FEED_EE2A1", + "CLK_PMV_IMUX31_0", + "CLK_FEED_EE4A0", + "CLK_PMV_IMUX37_0", + "CLK_FEED_WR1END0", + "CLK_PMV_IMUX20_0", + "CLK_FEED_CK_GCLK6", + "CLK_FEED_WR1END1", + "CLK_FEED_NE4BEG1", + "CLK_FEED_CK_BUFG_CASC0", + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_WL1END3", + "CLK_FEED_CK_GCLK10", + "CLK_FEED_CK_GCLK0", + "CLK_FEED_CK_GCLK30", + "CLK_FEED_EE4C0", + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_PMV_IMUX46_0", + "CLK_PMV_IMUX30_0", + "CLK_FEED_SE4BEG2", + "CLK_PMV_BYP3_0", + "CLK_PMV_LOGIC_OUTS14_0", + "CLK_PMV_IMUX17_0", + "CLK_PMV_LOGIC_OUTS4_0", + "CLK_FEED_EE2A3", + "CLK_FEED_WW4B3", + "CLK_FEED_EE4BEG1", + "CLK_FEED_CK_BUFG_CASC7", + "CLK_PMV_IMUX9_0", + "CLK_PMV_LOGIC_OUTS23_0", + "CLK_FEED_EE4A1", + "CLK_FEED_R_CK_GCLK12", + "CLK_PMV_IMUX28_0", + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_GCLK4", + "CLK_PMV_IMUX12_0", + "CLK_FEED_NE4C3", + "CLK_FEED_NW2A2", + "CLK_FEED_ER1BEG2", + "CLK_PMV_IMUX41_0", + "CLK_FEED_SW4END2", + "CLK_FEED_WW2A3", + "CLK_FEED_LH12", + "CLK_FEED_SW2A3", + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_PMV_IMUX35_0", + "CLK_FEED_SW4A2", + "CLK_MTBF2_EN", + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_SW4END3", + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_NE4BEG2", + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_EL1BEG2", + "CLK_PMV_CLK1_0", + "CLK_FEED_WW4C3", + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_WL1END2", + "CLK_FEED_CK_GCLK26", + "CLK_FEED_ER1BEG0", + "CLK_FEED_SW2A2", + "CLK_FEED_WW2END1", + "CLK_PMV_IMUX11_0", + "CLK_FEED_WR1END2", + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_SW4A0", + "CLK_FEED_SE2A0", + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_GCLK10", + "CLK_PMV_IMUX34_0", + "CLK_PMV_IMUX21_0", + "CLK_FEED_CK_BUFG_CASC31", + "CLK_FEED_NW4A3", + "CLK_FEED_WW2A1", + "CLK_PMV_LOGIC_OUTS10_0", + "CLK_PMV_IMUX6_0", + "CLK_FEED_CK_BUFG_CASC19", + "CLK_FEED_CK_BUFG_CASC27", + "CLK_FEED_CK_GCLK18", + "CLK_PMV_FAN6_0", + "CLK_PMV_IMUX32_0", + "CLK_FEED_CK_GCLK4", + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_NE4C0", + "CLK_FEED_R_CK_GCLK25", + "CLK_PMV_LOGIC_OUTS21_0", + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_SW2A0", + "CLK_MTBF2_Q7B", + "CLK_FEED_NE2A0", + "CLK_FEED_CK_GCLK7", + "CLK_FEED_CK_BUFG_CASC24", + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_EE2A0", + "CLK_FEED_SE4BEG1", + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_WW2A2", + "CLK_FEED_CK_GCLK12", + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_PMV_IMUX4_0", + "CLK_FEED_CK_BUFG_CASC14", + "CLK_FEED_MONITOR_N", + "CLK_FEED_NE2A2", + "CLK_FEED_CK_GCLK9", + "CLK_FEED_SW4END1", + "CLK_PMV_IMUX42_0", + "CLK_FEED_EE4B2", + "CLK_FEED_EE4BEG3", + "CLK_PMV_BYP6_0", + "CLK_FEED_WW2END3", + "CLK_PMV_LOGIC_OUTS2_0", + "CLK_FEED_NE4BEG0", + "CLK_FEED_WW4END0", + "CLK_FEED_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_LH7", + "CLK_PMV_IMUX43_0", + "CLK_FEED_CK_GCLK28", + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_NW4END3", + "CLK_FEED_NW2A3", + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_EE4C1", + "CLK_FEED_WW4END3", + "CLK_PMV_FAN1_0", + "CLK_PMV_IMUX29_0", + "CLK_FEED_CK_GCLK13", + "CLK_FEED_NW2A1", + "CLK_FEED_CK_GCLK24", + "CLK_PMV_IMUX10_0", + "CLK_PMV_IMUX39_0", + "CLK_MTBF2_Q0B", + "CLK_FEED_EL1BEG0", + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_NW4A0", + "CLK_FEED_WW4A2", + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_LH10", + "CLK_FEED_NW4A1", + "CLK_FEED_LH5", + "CLK_FEED_SE4C3", + "CLK_FEED_CK_BUFG_CASC4", + "CLK_FEED_NW2A0", + "CLK_FEED_WW4C0", + "CLK_FEED_LH6", + "CLK_PMV_LOGIC_OUTS6_0", + "CLK_PMV_IMUX13_0", + "CLK_FEED_SW4END0", + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_PMV_IMUX45_0", + "CLK_PMV_LOGIC_OUTS13_0", + "CLK_FEED_WW4B1", + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_WW2A0", + "CLK_FEED_CK_BUFG_CASC29", + "CLK_MTBF2_Q2B", + "CLK_PMV_IMUX14_0", + "CLK_FEED_WW4A1", + "CLK_FEED_LH2", + "CLK_FEED_WW4C1", + "CLK_FEED_WW2END0", + "CLK_FEED_SE2A3", + "CLK_PMV_LOGIC_OUTS0_0", + "CLK_PMV_LOGIC_OUTS15_0", + "CLK_PMV_FAN2_0", + "CLK_FEED_SE2A1", + "CLK_FEED_NE4C2", + "CLK_FEED_EE2BEG0", + "CLK_PMV_IMUX3_0" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_CLK_PMV.json b/kintex7/tile_type_CLK_PMV.json new file mode 100644 index 0000000..d59f811 --- /dev/null +++ b/kintex7/tile_type_CLK_PMV.json @@ -0,0 +1,1671 @@ +{ + "tile_type": "CLK_PMV", + "sites": [], + "wires": [ + "CLK_PMV_EE4B0_6", + "CLK_PMV_WR1END1_6", + "CLK_PMV_EE4C1_2", + "CLK_PMV_IMUX9_1", + "CLK_PMV_LH4_4", + "CLK_PMV_LH2_6", + "CLK_PMV_EE2BEG2_0", + "CLK_PMV_IMUX39_6", + "CLK_PMV_WL1END0_2", + "CLK_PMV_CTRL0_6", + "CLK_PMV_FAN4_3", + "CLK_PMV_WW4A1_1", + "CLK_PMV_IMUX36_0", + "CLK_PMV_ER1BEG3_0", + "CLK_PMV_IMUX1_4", + "CLK_PMV_LOGIC_OUTS15_3", + "CLK_PMV_WR1END3_3", + "CLK_PMV_IMUX22_0", + "CLK_PMV_R_CK_GCLK24", + "CLK_PMV_WR1END1_1", + "CLK_PMV_LOGIC_OUTS13_6", + "CLK_PMV_LOGIC_OUTS14_3", + "CLK_PMV_EE4C1_6", + "CLK_PMV_LH6_0", + "CLK_PMV_NE4BEG2_4", + "CLK_PMV_CK_GCLK2", + "CLK_PMV_NW4END1_0", + "CLK_PMV_SW2A3_0", + "CLK_PMV_ER1BEG3_1", + "CLK_PMV_EE4BEG2_5", + "CLK_PMV_IMUX4_5", + "CLK_PMV_NW4END2_2", + "CLK_PMV_ER1BEG1_4", + "CLK_PMV_WR1END2_4", + "CLK_PMV_EL1BEG3_3", + "CLK_PMV_EE4A1_6", + "CLK_PMV_CTRL0_2", + "CLK_PMV_LOGIC_OUTS7_2", + "CLK_PMV_LOGIC_OUTS18_5", + "CLK_PMV_EL1BEG0_4", + "CLK_PMV_IMUX22_5", + "CLK_PMV_IMUX32_1", + "CLK_PMV_NW2A1_1", + "CLK_PMV_WR1END1_2", + "CLK_PMV_IMUX27_0", + "CLK_PMV_SE2A3_6", + "CLK_PMV_BYP3_1", + "CLK_PMV_LOGIC_OUTS3_2", + "CLK_PMV_WW2END1_5", + "CLK_PMV_WL1END0_3", + "CLK_PMV_BYP3_6", + "CLK_PMV_IMUX25_2", + "CLK_PMV_WW4B3_5", + "CLK_PMV_IMUX24_6", + "CLK_PMV_MONITOR_P_3", + "CLK_PMV_SE4BEG1_3", + "CLK_PMV_WW4B1_6", + "CLK_PMV_SE4C1_3", + "CLK_PMV_WW2END2_4", + "CLK_PMV_EE4BEG0_2", + "CLK_PMV_LOGIC_OUTS11_0", + "CLK_PMV_LOGIC_OUTS19_4", + "CLK_PMV_LOGIC_OUTS1_1", + "CLK_PMV_LOGIC_OUTS23_3", + "CLK_PMV_IMUX21_4", + "CLK_PMV_IMUX33_0", + "CLK_PMV_WW4END2_2", + "CLK_PMV_CK_BUFG_CASC13", + "CLK_PMV_IMUX15_0", + "CLK_PMV_IMUX32_6", + "CLK_PMV_LOGIC_OUTS7_5", + "CLK_PMV_WW4B2_6", + "CLK_PMV_SW4END0_4", + "CLK_PMV_SE2A1_1", + "CLK_PMV_IMUX7_3", + "CLK_PMV_IMUX30_5", + "CLK_PMV_LOGIC_OUTS2_5", + "CLK_PMV_WW4END3_2", + "CLK_PMV_LH6_5", + "CLK_PMV_EE4BEG1_2", + "CLK_PMV_R_CK_BUFG_CASC15", + "CLK_PMV_LH2_3", + "CLK_PMV_WW4A2_4", + "CLK_PMV_SW4A0_2", + "CLK_PMV_NE4C0_4", + "CLK_PMV_LOGIC_OUTS15_5", + "CLK_PMV_WW4B3_0", + "CLK_PMV_WL1END0_4", + "CLK_PMV_LOGIC_OUTS7_6", + "CLK_PMV_R_CK_GCLK23", + "CLK_PMV_SW4A3_5", + "CLK_PMV_R_CK_BUFG_CASC5", + "CLK_PMV_LOGIC_OUTS11_4", + "CLK_PMV_LOGIC_OUTS6_3", + "CLK_PMV_IMUX16_3", + "CLK_PMV_SW4END3_4", + "CLK_PMV_IMUX34_4", + "CLK_PMV_FAN5_5", + "CLK_PMV_FAN3_0", + "CLK_PMV_IMUX15_2", + "CLK_PMV_LOGIC_OUTS3_0", + "CLK_PMV_WW4END3_1", + "CLK_PMV_WW4B0_0", + "CLK_PMV_EE4A3_5", + "CLK_PMV_FAN4_2", + "CLK_PMV_IMUX6_4", + "CLK_PMV_LOGIC_OUTS18_3", + "CLK_PMV_EE2BEG2_5", + "CLK_PMV_IMUX9_3", + "CLK_PMV_LOGIC_OUTS5_2", + "CLK_PMV_SE2A2_1", + "CLK_PMV_WW2A3_2", + "CLK_PMV_IMUX46_5", + "CLK_PMV_NE2A0_3", + "CLK_PMV_IMUX8_4", + "CLK_PMV_IMUX17_5", + "CLK_PMV_WW4END2_5", + "CLK_PMV_WW4C2_3", + "CLK_PMV_NE4C2_2", + "CLK_PMV_IMUX42_2", + "CLK_PMV_NW2A0_3", + "CLK_PMV_WL1END1_3", + "CLK_PMV_EE2A1_4", + "CLK_PMV_LOGIC_OUTS0_6", + "CLK_PMV_R_CK_BUFG_CASC24", + "CLK_PMV_SE4C3_3", + "CLK_PMV_BYP6_3", + "CLK_PMV_BYP4_6", + "CLK_PMV_FAN4_1", + "CLK_PMV_LOGIC_OUTS12_6", + "CLK_PMV_MONITOR_N_2", + "CLK_PMV_IMUX45_1", + "CLK_PMV_NW4A3_1", + "CLK_PMV_LOGIC_OUTS6_4", + "CLK_PMV_CK_BUFG_CASC28", + "CLK_PMV_IMUX44_5", + "CLK_PMV_WW2A3_4", + "CLK_PMV_IMUX46_3", + "CLK_PMV_SW4A3_6", + "CLK_PMV_R_CK_GCLK31", + "CLK_PMV_LOGIC_OUTS8_5", + "CLK_PMV_EL1BEG2_0", + "CLK_PMV_CK_BUFG_CASC24", + "CLK_PMV_LOGIC_OUTS20_0", + "CLK_PMV_NW2A0_5", + "CLK_PMV_IMUX36_3", + "CLK_PMV_BYP2_3", + "CLK_PMV_WW4B0_6", + "CLK_PMV_NW4A3_3", + "CLK_PMV_R_CK_GCLK19", + "CLK_PMV_IMUX12_2", + "CLK_PMV_NW4A2_2", + "CLK_PMV_EE4A2_6", + "CLK_PMV_BYP7_1", + "CLK_PMV_ER1BEG2_6", + "CLK_PMV_EE4A2_5", + "CLK_PMV_EE4A1_5", + "CLK_PMV_BYP7_0", + "CLK_PMV_LOGIC_OUTS0_1", + "CLK_PMV_LOGIC_OUTS15_6", + "CLK_PMV_BYP5_0", + "CLK_PMV_IMUX27_6", + "CLK_PMV_CK_GCLK30", + "CLK_PMV_IMUX25_0", + "CLK_PMV_EE4A0_2", + "CLK_PMV_R_CK_GCLK27", + "CLK_PMV_CK_GCLK17", + "CLK_PMV_LOGIC_OUTS16_5", + "CLK_PMV_SE2A1_3", + "CLK_PMV_IMUX3_4", + "CLK_PMV_WW4B1_4", + "CLK_PMV_SW4A2_5", + "CLK_PMV_LOGIC_OUTS16_0", + "CLK_PMV_LOGIC_OUTS0_5", + "CLK_PMV_NW4A0_3", + "CLK_PMV_FAN3_2", + "CLK_PMV_EE4B0_5", + "CLK_PMV_IMUX10_4", + "CLK_PMV_CK_BUFG_CASC29", + "CLK_PMV_BYP1_4", + "CLK_PMV_IMUX19_3", + "CLK_PMV_NE2A3_0", + "CLK_PMV_SW4END2_4", + "CLK_PMV_WW2END1_2", + "CLK_PMV_IMUX22_3", + "CLK_PMV_LH11_0", + "CLK_PMV_SE4BEG2_5", + "CLK_PMV_WW4C2_5", + "CLK_PMV_IMUX40_2", + "CLK_PMV_WW4C0_1", + "CLK_PMV_WW4B3_1", + "CLK_PMV_NE2A0_5", + "CLK_PMV_CLK1_5", + "CLK_PMV_ER1BEG0_5", + "CLK_PMV_EE4B3_3", + "CLK_PMV_CK_GCLK25", + "CLK_PMV_WR1END0_4", + "CLK_PMV_IMUX23_6", + "CLK_PMV_WR1END3_2", + "CLK_PMV_SW2A1_3", + "CLK_PMV_NW2A2_6", + "CLK_PMV_MONITOR_N_0", + "CLK_PMV_NE4BEG2_5", + "CLK_PMV_SE2A1_4", + "CLK_PMV_IMUX37_2", + "CLK_PMV_CLK0_2", + "CLK_PMV_SW4END3_1", + "CLK_PMV_ER1BEG3_5", + "CLK_PMV_CLK0_0", + "CLK_PMV_BYP1_3", + "CLK_PMV_BYP0_0", + "CLK_PMV_WW4A0_1", + "CLK_PMV_NW4END1_5", + "CLK_PMV_IMUX45_3", + "CLK_PMV_WW2A1_1", + "CLK_PMV_CTRL0_0", + "CLK_PMV_CK_BUFG_CASC22", + "CLK_PMV_IMUX7_1", + "CLK_PMV_IMUX24_5", + "CLK_PMV_LOGIC_OUTS8_0", + "CLK_PMV_NW2A2_4", + "CLK_PMV_R_CK_GCLK21", + "CLK_PMV_LOGIC_OUTS17_1", + "CLK_PMV_SE4BEG1_0", + "CLK_PMV_LOGIC_OUTS1_6", + "CLK_PMV_EE4B3_4", + "CLK_PMV_NE4C1_1", + "CLK_PMV_EL1BEG0_5", + "CLK_PMV_EE2BEG2_6", + "CLK_PMV_LH8_2", + "CLK_PMV_BYP3_4", + "CLK_PMV_IMUX33_5", + "CLK_PMV_WR1END2_1", + "CLK_PMV_LOGIC_OUTS21_4", + "CLK_PMV_CTRL1_4", + "CLK_PMV_IMUX36_2", + "CLK_PMV_NE4BEG3_1", + "CLK_PMV_NW4A1_0", + "CLK_PMV_CK_BUFG_CASC18", + "CLK_PMV_IMUX15_3", + "CLK_PMV_IMUX15_5", + "CLK_PMV_WW2END0_5", + "CLK_PMV_SW2A2_6", + "CLK_PMV_NE4BEG3_3", + "CLK_PMV_BYP0_6", + "CLK_PMV_NE2A2_0", + "CLK_PMV_LOGIC_OUTS18_2", + "CLK_PMV_NE2A1_1", + "CLK_PMV_NE4BEG1_3", + "CLK_PMV_NW4END0_2", + "CLK_PMV_SE4C3_2", + "CLK_PMV_EE4A2_0", + "CLK_PMV_FAN7_2", + "CLK_PMV_LOGIC_OUTS1_4", + "CLK_PMV_WW2A1_3", + "CLK_PMV_IMUX20_0", + "CLK_PMV_R_CK_GCLK9", + "CLK_PMV_SW4A1_6", + "CLK_PMV_WW2END2_6", + "CLK_PMV_WW2A1_5", + "CLK_PMV_NW2A3_5", + "CLK_PMV_FAN0_1", + "CLK_PMV_LOGIC_OUTS2_1", + "CLK_PMV_EE4A0_1", + "CLK_PMV_IMUX29_5", + "CLK_PMV_LOGIC_OUTS2_2", + "CLK_PMV_WL1END3_4", + "CLK_PMV_LOGIC_OUTS20_3", + "CLK_PMV_IMUX2_2", + "CLK_PMV_IMUX17_0", + "CLK_PMV_WL1END2_5", + "CLK_PMV_IMUX14_4", + "CLK_PMV_SW4A1_4", + "CLK_PMV_IMUX41_4", + "CLK_PMV_IMUX26_4", + "CLK_PMV_CTRL1_5", + "CLK_PMV_LH2_0", + "CLK_PMV_NE4C1_4", + "CLK_PMV_EE4C2_6", + "CLK_PMV_LOGIC_OUTS22_3", + "CLK_PMV_WW4C3_3", + "CLK_PMV_WW4END0_0", + "CLK_PMV_WW4A3_6", + "CLK_PMV_FAN5_6", + "CLK_PMV_LOGIC_OUTS23_0", + "CLK_PMV_NE4C0_6", + "CLK_PMV_IMUX33_3", + "CLK_PMV_IMUX16_6", + "CLK_PMV_FAN4_4", + "CLK_PMV_EE2A2_0", + "CLK_PMV_SE4C1_1", + "CLK_PMV_LOGIC_OUTS10_1", + "CLK_PMV_WW4B0_5", + "CLK_PMV_IMUX13_4", + "CLK_PMV_LOGIC_OUTS23_2", + "CLK_PMV_CK_BUFG_CASC9", + "CLK_PMV_LOGIC_OUTS4_4", + "CLK_PMV_R_CK_GCLK29", + "CLK_PMV_WW2END1_3", + "CLK_PMV_IMUX38_1", + "CLK_PMV_NW4END1_1", + "CLK_PMV_SW4A0_3", + "CLK_PMV_IMUX4_3", + "CLK_PMV_IMUX14_2", + "CLK_PMV_R_CK_GCLK26", + "CLK_PMV_CK_GCLK6", + "CLK_PMV_FAN3_3", + "CLK_PMV_NW2A1_3", + "CLK_PMV_ER1BEG1_2", + "CLK_PMV_NW4END2_0", + "CLK_PMV_WW4A2_1", + "CLK_PMV_LOGIC_OUTS10_6", + "CLK_PMV_NW4END0_0", + "CLK_PMV_EE4B1_6", + "CLK_PMV_WL1END0_1", + "CLK_PMV_WW2A1_6", + "CLK_PMV_EL1BEG3_1", + "CLK_PMV_IMUX28_2", + "CLK_PMV_WL1END0_5", + "CLK_PMV_EL1BEG3_6", + "CLK_PMV_IMUX4_2", + "CLK_PMV_LOGIC_OUTS16_3", + "CLK_PMV_LH8_3", + "CLK_PMV_LOGIC_OUTS15_1", + "CLK_PMV_WW4C2_1", + "CLK_PMV_IMUX37_1", + "CLK_PMV_NW4END2_4", + "CLK_PMV_SW2A3_3", + "CLK_PMV_LOGIC_OUTS20_1", + "CLK_PMV_NE4BEG0_4", + "CLK_PMV_CK_BUFG_CASC7", + "CLK_PMV_SW2A1_2", + "CLK_PMV_IMUX40_6", + "CLK_PMV_BYP6_6", + "CLK_PMV_CTRL0_1", + "CLK_PMV_SE2A2_2", + "CLK_PMV_SW2A1_6", + "CLK_PMV_LOGIC_OUTS15_4", + "CLK_PMV_R_CK_BUFG_CASC29", + "CLK_PMV_WW4END0_3", + "CLK_PMV_WW2A1_2", + "CLK_PMV_LH7_3", + "CLK_PMV_R_CK_GCLK10", + "CLK_PMV_WW4A2_5", + "CLK_PMV_SE4C2_6", + "CLK_PMV_SE2A0_1", + "CLK_PMV_CLK1_3", + "CLK_PMV_IMUX39_5", + "CLK_PMV_WW4END2_4", + "CLK_PMV_EE4B0_4", + "CLK_PMV_R_CK_BUFG_CASC23", + "CLK_PMV_NW4END0_6", + "CLK_PMV_LOGIC_OUTS18_1", + "CLK_PMV_IMUX45_5", + "CLK_PMV_CK_GCLK19", + "CLK_PMV_LOGIC_OUTS1_3", + "CLK_PMV_IMUX13_6", + "CLK_PMV_NE2A3_1", + "CLK_PMV_WW2END0_2", + "CLK_PMV_BYP6_2", + "CLK_PMV_EE2BEG0_0", + "CLK_PMV_WW2END3_3", + "CLK_PMV_BYP2_6", + "CLK_PMV_SE4BEG1_1", + "CLK_PMV_IMUX30_2", + "CLK_PMV_EE4C1_0", + "CLK_PMV_R_CK_BUFG_CASC3", + "CLK_PMV_IMUX37_6", + "CLK_PMV_NE4C0_5", + "CLK_PMV_ER1BEG3_6", + "CLK_PMV_EL1BEG3_5", + "CLK_PMV_IMUX25_5", + "CLK_PMV_FAN0_5", + "CLK_PMV_IMUX30_4", + "CLK_PMV_LOGIC_OUTS23_4", + "CLK_PMV_WW2END0_4", + "CLK_PMV_SW4END1_6", + "CLK_PMV_WW2END0_6", + "CLK_PMV_SW2A2_0", + "CLK_PMV_IMUX17_1", + "CLK_PMV_EE2BEG0_6", + "CLK_PMV_SE2A3_5", + "CLK_PMV_LH12_6", + "CLK_PMV_LOGIC_OUTS6_0", + "CLK_PMV_WW2A2_0", + "CLK_PMV_O", + "CLK_PMV_IMUX41_5", + "CLK_PMV_LH12_1", + "CLK_PMV_LOGIC_OUTS18_6", + "CLK_PMV_LOGIC_OUTS13_0", + "CLK_PMV_IMUX45_0", + "CLK_PMV_IMUX38_5", + "CLK_PMV_CK_BUFG_CASC25", + "CLK_PMV_IMUX44_3", + "CLK_PMV_WW4C0_3", + "CLK_PMV_SE4BEG0_6", + "CLK_PMV_FAN1_6", + "CLK_PMV_IMUX14_0", + "CLK_PMV_ER1BEG2_4", + "CLK_PMV_IMUX22_6", + "CLK_PMV_IMUX4_6", + "CLK_PMV_LH10_1", + "CLK_PMV_LH7_4", + "CLK_PMV_SE4BEG3_2", + "CLK_PMV_LH3_5", + "CLK_PMV_NW2A2_3", + "CLK_PMV_IMUX28_3", + "CLK_PMV_LOGIC_OUTS15_0", + "CLK_PMV_FAN3_1", + "CLK_PMV_SW2A2_2", + "CLK_PMV_NW4A0_4", + "CLK_PMV_CK_BUFG_CASC4", + "CLK_PMV_NE2A1_4", + "CLK_PMV_WW2END2_2", + "CLK_PMV_SE2A2_0", + "CLK_PMV_EE2BEG3_6", + "CLK_PMV_IMUX44_1", + "CLK_PMV_R_CK_GCLK20", + "CLK_PMV_IMUX33_1", + "CLK_PMV_EL1BEG2_1", + "CLK_PMV_WW4B1_0", + "CLK_PMV_NW2A3_0", + "CLK_PMV_SE2A0_0", + "CLK_PMV_SE4C2_0", + "CLK_PMV_NW4END0_5", + "CLK_PMV_WW2END2_3", + "CLK_PMV_IMUX5_0", + "CLK_PMV_IMUX26_6", + "CLK_PMV_LOGIC_OUTS19_0", + "CLK_PMV_SE4BEG0_1", + "CLK_PMV_LOGIC_OUTS4_2", + "CLK_PMV_LOGIC_OUTS14_1", + "CLK_PMV_WR1END1_4", + "CLK_PMV_NE4BEG1_1", + "CLK_PMV_R_CK_GCLK7", + "CLK_PMV_CK_BUFG_CASC16", + "CLK_PMV_LOGIC_OUTS12_3", + "CLK_PMV_NW4A3_5", + "CLK_PMV_NE4C0_1", + "CLK_PMV_IMUX16_2", + "CLK_PMV_R_CK_GCLK1", + "CLK_PMV_LOGIC_OUTS17_5", + "CLK_PMV_IMUX0_0", + "CLK_PMV_EE2BEG2_3", + "CLK_PMV_LH1_2", + "CLK_PMV_BYP3_3", + "CLK_PMV_WL1END2_4", + "CLK_PMV_EE4C3_5", + "CLK_PMV_CK_GCLK23", + "CLK_PMV_FAN5_3", + "CLK_PMV_WW4A1_4", + "CLK_PMV_WW4END1_4", + "CLK_PMV_SE2A2_6", + "CLK_PMV_WW4C1_2", + "CLK_PMV_SE4BEG0_2", + "CLK_PMV_EE4BEG0_5", + "CLK_PMV_IMUX45_4", + "CLK_PMV_IMUX2_0", + "CLK_PMV_IMUX30_6", + "CLK_PMV_NW4END3_0", + "CLK_PMV_LOGIC_OUTS10_2", + "CLK_PMV_IMUX38_3", + "CLK_PMV_NW4A2_3", + "CLK_PMV_WW2A1_0", + "CLK_PMV_LOGIC_OUTS22_6", + "CLK_PMV_WL1END3_3", + "CLK_PMV_SW4END0_6", + "CLK_PMV_NW4A1_6", + "CLK_PMV_BYP3_5", + "CLK_PMV_CTRL1_0", + "CLK_PMV_IMUX16_1", + "CLK_PMV_CK_BUFG_CASC0", + "CLK_PMV_LH6_6", + "CLK_PMV_EE4A2_2", + "CLK_PMV_NW2A0_0", + "CLK_PMV_NW4A0_6", + "CLK_PMV_EE4C2_5", + "CLK_PMV_SW4END1_2", + "CLK_PMV_SW2A2_3", + "CLK_PMV_NE2A0_6", + "CLK_PMV_IMUX47_5", + "CLK_PMV_SW4A2_3", + "CLK_PMV_EE4C0_1", + "CLK_PMV_LH9_1", + "CLK_PMV_SW2A0_0", + "CLK_PMV_WL1END0_0", + "CLK_PMV_LOGIC_OUTS23_1", + "CLK_PMV_LH3_3", + "CLK_PMV_LOGIC_OUTS6_1", + "CLK_PMV_WW4C2_2", + "CLK_PMV_EE4C3_6", + "CLK_PMV_SW4A1_0", + "CLK_PMV_EE2BEG0_2", + "CLK_PMV_LOGIC_OUTS17_3", + "CLK_PMV_EE2BEG1_5", + "CLK_PMV_SW2A1_0", + "CLK_PMV_LOGIC_OUTS4_1", + "CLK_PMV_CK_GCLK18", + "CLK_PMV_IMUX43_2", + "CLK_PMV_IMUX32_4", + "CLK_PMV_MONITOR_P_6", + "CLK_PMV_EE4C2_4", + "CLK_PMV_IMUX3_5", + "CLK_PMV_WW4C1_3", + "CLK_PMV_EE2A1_0", + "CLK_PMV_MONITOR_N_1", + "CLK_PMV_WR1END2_6", + "CLK_PMV_IMUX46_6", + "CLK_PMV_LOGIC_OUTS4_5", + "CLK_PMV_EE4C0_2", + "CLK_PMV_CLK1_2", + "CLK_PMV_SE4BEG2_2", + "CLK_PMV_EL1BEG0_2", + "CLK_PMV_SW4A3_3", + "CLK_PMV_WW4C2_0", + "CLK_PMV_NW2A2_2", + "CLK_PMV_IMUX8_5", + "CLK_PMV_SW4END0_3", + "CLK_PMV_NE4BEG1_5", + "CLK_PMV_SW2A0_4", + "CLK_PMV_LOGIC_OUTS11_1", + "CLK_PMV_LH11_5", + "CLK_PMV_WW4A0_0", + "CLK_PMV_LOGIC_OUTS11_5", + "CLK_PMV_R_CK_BUFG_CASC11", + "CLK_PMV_IMUX0_2", + "CLK_PMV_NW2A0_4", + "CLK_PMV_CK_GCLK4", + "CLK_PMV_FAN1_5", + "CLK_PMV_CK_BUFG_CASC30", + "CLK_PMV_IMUX14_6", + "CLK_PMV_EE4BEG2_6", + "CLK_PMV_NE4BEG2_6", + "CLK_PMV_LH4_2", + "CLK_PMV_LOGIC_OUTS3_3", + "CLK_PMV_LH2_4", + "CLK_PMV_LOGIC_OUTS12_1", + "CLK_PMV_FAN3_5", + "CLK_PMV_EE4C3_1", + "CLK_PMV_EE2A0_1", + "CLK_PMV_IMUX45_6", + "CLK_PMV_NW4A0_1", + "CLK_PMV_WR1END1_3", + "CLK_PMV_EL1BEG1_1", + "CLK_PMV_LOGIC_OUTS7_1", + "CLK_PMV_LOGIC_OUTS9_2", + "CLK_PMV_EE4BEG3_0", + "CLK_PMV_WW4A3_0", + "CLK_PMV_LH6_3", + "CLK_PMV_R_CK_BUFG_CASC19", + "CLK_PMV_NE4BEG3_0", + "CLK_PMV_BYP2_1", + "CLK_PMV_SW4END1_4", + "CLK_PMV_NW4END2_1", + "CLK_PMV_MONITOR_P_1", + "CLK_PMV_IMUX31_5", + "CLK_PMV_IMUX21_6", + "CLK_PMV_EL1BEG1_0", + "CLK_PMV_FAN3_4", + "CLK_PMV_EE4C0_6", + "CLK_PMV_IMUX11_3", + "CLK_PMV_IMUX46_2", + "CLK_PMV_EE2A1_5", + "CLK_PMV_BYP5_6", + "CLK_PMV_LOGIC_OUTS9_3", + "CLK_PMV_NE4BEG1_6", + "CLK_PMV_FAN6_2", + "CLK_PMV_LOGIC_OUTS6_2", + "CLK_PMV_R_CK_GCLK0", + "CLK_PMV_WW4C3_6", + "CLK_PMV_IMUX24_0", + "CLK_PMV_NW4END2_3", + "CLK_PMV_IMUX5_5", + "CLK_PMV_WR1END3_6", + "CLK_PMV_FAN0_0", + "CLK_PMV_EE4A2_4", + "CLK_PMV_IMUX12_3", + "CLK_PMV_EE4C1_4", + "CLK_PMV_IMUX44_0", + "CLK_PMV_LH5_6", + "CLK_PMV_IMUX7_5", + "CLK_PMV_SW2A0_3", + "CLK_PMV_CK_BUFG_CASC1", + "CLK_PMV_NW4A2_0", + "CLK_PMV_EE4BEG3_2", + "CLK_PMV_IMUX23_2", + "CLK_PMV_WL1END1_0", + "CLK_PMV_NE4C1_5", + "CLK_PMV_WW4END2_0", + "CLK_PMV_SW4END1_5", + "CLK_PMV_NE4C0_3", + "CLK_PMV_NW2A2_0", + "CLK_PMV_WW4C3_1", + "CLK_PMV_LH8_0", + "CLK_PMV_IMUX7_0", + "CLK_PMV_IMUX19_5", + "CLK_PMV_WW4A0_2", + "CLK_PMV_WL1END3_0", + "CLK_PMV_IMUX35_6", + "CLK_PMV_CK_GCLK7", + "CLK_PMV_EE4C3_4", + "CLK_PMV_ER1BEG2_2", + "CLK_PMV_R_CK_BUFG_CASC6", + "CLK_PMV_NE2A1_0", + "CLK_PMV_WR1END2_3", + "CLK_PMV_NE4C3_2", + "CLK_PMV_NE4BEG0_1", + "CLK_PMV_CK_GCLK9", + "CLK_PMV_CK_GCLK0", + "CLK_PMV_EE4B0_3", + "CLK_PMV_IMUX34_5", + "CLK_PMV_CTRL1_1", + "CLK_PMV_IMUX29_4", + "CLK_PMV_FAN7_0", + "CLK_PMV_SE4BEG3_5", + "CLK_PMV_SE2A1_2", + "CLK_PMV_CK_BUFG_CASC14", + "CLK_PMV_IMUX37_5", + "CLK_PMV_LH3_0", + "CLK_PMV_SE2A0_2", + "CLK_PMV_BYP1_0", + "CLK_PMV_FAN2_5", + "CLK_PMV_FAN1_3", + "CLK_PMV_EE2BEG1_1", + "CLK_PMV_WW4C3_4", + "CLK_PMV_IMUX43_6", + "CLK_PMV_NE4C2_6", + "CLK_PMV_LH10_3", + "CLK_PMV_IMUX11_2", + "CLK_PMV_IMUX27_4", + "CLK_PMV_SW4END2_2", + "CLK_PMV_WW4B2_2", + "CLK_PMV_NW4A3_0", + "CLK_PMV_NW4A2_4", + "CLK_PMV_NE2A1_6", + "CLK_PMV_R_CK_BUFG_CASC28", + "CLK_PMV_FAN2_1", + "CLK_PMV_SE4BEG1_6", + "CLK_PMV_LH9_5", + "CLK_PMV_WW2A0_5", + "CLK_PMV_CK_BUFG_CASC27", + "CLK_PMV_LOGIC_OUTS10_4", + "CLK_PMV_R_CK_BUFG_CASC22", + "CLK_PMV_EE4B2_3", + "CLK_PMV_IMUX40_1", + "CLK_PMV_IMUX18_1", + "CLK_PMV_WW2A3_6", + "CLK_PMV_IMUX29_6", + "CLK_PMV_EE2A3_4", + "CLK_PMV_NW4END1_4", + "CLK_PMV_NE4BEG1_2", + "CLK_PMV_IMUX34_2", + "CLK_PMV_WW4C1_4", + "CLK_PMV_EL1BEG3_0", + "CLK_PMV_IMUX5_4", + "CLK_PMV_WW4C0_4", + "CLK_PMV_IMUX35_2", + "CLK_PMV_IMUX6_2", + "CLK_PMV_IMUX46_0", + "CLK_PMV_IMUX23_3", + "CLK_PMV_LOGIC_OUTS16_1", + "CLK_PMV_NW2A3_4", + "CLK_PMV_IMUX10_5", + "CLK_PMV_ER1BEG2_3", + "CLK_PMV_LH9_2", + "CLK_PMV_WW4END1_3", + "CLK_PMV_LOGIC_OUTS2_6", + "CLK_PMV_SW2A3_4", + "CLK_PMV_R_CK_BUFG_CASC25", + "CLK_PMV_NW4END0_3", + "CLK_PMV_IMUX9_0", + "CLK_PMV_WW4A0_6", + "CLK_PMV_NE4BEG3_4", + "CLK_PMV_EE4B1_0", + "CLK_PMV_IMUX28_5", + "CLK_PMV_WW4A1_5", + "CLK_PMV_IMUX39_1", + "CLK_PMV_NE2A0_0", + "CLK_PMV_LOGIC_OUTS16_2", + "CLK_PMV_NW2A1_2", + "CLK_PMV_IMUX47_1", + "CLK_PMV_NW2A3_1", + "CLK_PMV_R_CK_GCLK25", + "CLK_PMV_IMUX26_1", + "CLK_PMV_NE2A2_6", + "CLK_PMV_IMUX44_2", + "CLK_PMV_SE4C2_4", + "CLK_PMV_R_CK_GCLK18", + "CLK_PMV_WW4A2_0", + "CLK_PMV_IMUX18_6", + "CLK_PMV_LOGIC_OUTS14_4", + "CLK_PMV_FAN1_2", + "CLK_PMV_LOGIC_OUTS19_3", + "CLK_PMV_BYP1_5", + "CLK_PMV_SW4END0_0", + "CLK_PMV_CLK1_0", + "CLK_PMV_CLK1_6", + "CLK_PMV_IMUX13_5", + "CLK_PMV_SE4C2_5", + "CLK_PMV_CLK0_6", + "CLK_PMV_NW2A1_5", + "CLK_PMV_LOGIC_OUTS13_3", + "CLK_PMV_CK_BUFG_CASC5", + "CLK_PMV_LOGIC_OUTS2_3", + "CLK_PMV_IMUX2_4", + "CLK_PMV_IMUX12_1", + "CLK_PMV_IMUX34_0", + "CLK_PMV_SW4END0_2", + "CLK_PMV_LOGIC_OUTS7_3", + "CLK_PMV_WW4A3_4", + "CLK_PMV_SE2A3_0", + "CLK_PMV_IMUX1_6", + "CLK_PMV_NE2A1_2", + "CLK_PMV_LOGIC_OUTS19_1", + "CLK_PMV_CK_GCLK22", + "CLK_PMV_ER1BEG2_1", + "CLK_PMV_IMUX34_6", + "CLK_PMV_IMUX42_4", + "CLK_PMV_LH4_0", + "CLK_PMV_IMUX0_1", + "CLK_PMV_SE4C3_0", + "CLK_PMV_IMUX36_1", + "CLK_PMV_FAN6_6", + "CLK_PMV_CK_GCLK12", + "CLK_PMV_LOGIC_OUTS3_4", + "CLK_PMV_SW4END2_1", + "CLK_PMV_WW4A0_4", + "CLK_PMV_SE4BEG2_3", + "CLK_PMV_R_CK_GCLK8", + "CLK_PMV_BYP7_2", + "CLK_PMV_IMUX37_3", + "CLK_PMV_IMUX31_2", + "CLK_PMV_ER1BEG1_1", + "CLK_PMV_EE4C3_3", + "CLK_PMV_LH4_3", + "CLK_PMV_WW2END1_0", + "CLK_PMV_FAN5_2", + "CLK_PMV_IMUX4_0", + "CLK_PMV_SE2A3_2", + "CLK_PMV_CK_BUFG_CASC8", + "CLK_PMV_WR1END2_0", + "CLK_PMV_SE4BEG3_0", + "CLK_PMV_IMUX24_4", + "CLK_PMV_EE2A3_2", + "CLK_PMV_LH8_1", + "CLK_PMV_LH5_0", + "CLK_PMV_EE2BEG1_4", + "CLK_PMV_NW2A0_6", + "CLK_PMV_IMUX27_1", + "CLK_PMV_BYP5_5", + "CLK_PMV_NE2A2_2", + "CLK_PMV_WW4B3_4", + "CLK_PMV_LH9_4", + "CLK_PMV_R_CK_GCLK30", + "CLK_PMV_SW2A0_2", + "CLK_PMV_EE2A0_6", + "CLK_PMV_IMUX13_2", + "CLK_PMV_IMUX0_3", + "CLK_PMV_CK_GCLK26", + "CLK_PMV_R_CK_BUFG_CASC7", + "CLK_PMV_ER1BEG0_4", + "CLK_PMV_WL1END1_5", + "CLK_PMV_NE4BEG3_6", + "CLK_PMV_BYP7_6", + "CLK_PMV_R_CK_GCLK14", + "CLK_PMV_WW4B1_2", + "CLK_PMV_IMUX43_0", + "CLK_PMV_IMUX15_6", + "CLK_PMV_R_CK_GCLK16", + "CLK_PMV_SW2A2_4", + "CLK_PMV_EE4BEG2_2", + "CLK_PMV_CTRL1_3", + "CLK_PMV_NW4END2_5", + "CLK_PMV_LOGIC_OUTS20_5", + "CLK_PMV_LOGIC_OUTS1_5", + "CLK_PMV_BYP4_1", + "CLK_PMV_IMUX35_1", + "CLK_PMV_NW2A3_6", + "CLK_PMV_IMUX29_0", + "CLK_PMV_IMUX7_6", + "CLK_PMV_LH10_6", + "CLK_PMV_EL1BEG1_2", + "CLK_PMV_CK_GCLK29", + "CLK_PMV_LOGIC_OUTS0_4", + "CLK_PMV_IMUX34_3", + "CLK_PMV_SW4END3_3", + "CLK_PMV_IMUX10_0", + "CLK_PMV_MONITOR_N_3", + "CLK_PMV_ER1BEG0_6", + "CLK_PMV_CK_BUFG_CASC2", + "CLK_PMV_R_CK_GCLK17", + "CLK_PMV_EE4BEG0_6", + "CLK_PMV_IMUX9_2", + "CLK_PMV_EE4BEG0_4", + "CLK_PMV_FAN2_4", + "CLK_PMV_EE4A3_4", + "CLK_PMV_NW4A0_5", + "CLK_PMV_CK_BUFG_CASC11", + "CLK_PMV_SW2A3_5", + "CLK_PMV_IMUX22_1", + "CLK_PMV_SW4A0_5", + "CLK_PMV_EL1BEG2_3", + "CLK_PMV_IMUX20_4", + "CLK_PMV_MONITOR_N_5", + "CLK_PMV_WW4B1_5", + "CLK_PMV_IMUX10_3", + "CLK_PMV_LOGIC_OUTS3_1", + "CLK_PMV_EE4A3_0", + "CLK_PMV_IMUX13_1", + "CLK_PMV_IMUX35_5", + "CLK_PMV_CK_BUFG_CASC3", + "CLK_PMV_IMUX8_3", + "CLK_PMV_SW4A1_5", + "CLK_PMV_IMUX41_1", + "CLK_PMV_IMUX29_3", + "CLK_PMV_LOGIC_OUTS13_2", + "CLK_PMV_LOGIC_OUTS3_6", + "CLK_PMV_WW2END3_5", + "CLK_PMV_SW4END0_5", + "CLK_PMV_SW4END1_1", + "CLK_PMV_WW2A2_5", + "CLK_PMV_SW4END3_2", + "CLK_PMV_FAN2_2", + "CLK_PMV_IMUX47_2", + "CLK_PMV_CK_BUFG_CASC21", + "CLK_PMV_EE4C3_0", + "CLK_PMV_IMUX6_5", + "CLK_PMV_IMUX24_1", + "CLK_PMV_EE2A2_4", + "CLK_PMV_IMUX3_0", + "CLK_PMV_WW4B3_3", + "CLK_PMV_LOGIC_OUTS14_2", + "CLK_PMV_WW4C0_0", + "CLK_PMV_BYP2_0", + "CLK_PMV_NW2A3_3", + "CLK_PMV_CLK1_1", + "CLK_PMV_SW4END2_5", + "CLK_PMV_IMUX16_0", + "CLK_PMV_IMUX7_2", + "CLK_PMV_WW4A3_5", + "CLK_PMV_WR1END3_5", + "CLK_PMV_IMUX17_3", + "CLK_PMV_EL1BEG2_4", + "CLK_PMV_EE2BEG0_5", + "CLK_PMV_LOGIC_OUTS7_4", + "CLK_PMV_CLK0_3", + "CLK_PMV_SW4END3_6", + "CLK_PMV_SW2A3_1", + "CLK_PMV_IMUX19_2", + "CLK_PMV_R_CK_BUFG_CASC12", + "CLK_PMV_NE4BEG0_6", + "CLK_PMV_FAN0_4", + "CLK_PMV_WW2END3_4", + "CLK_PMV_LH1_1", + "CLK_PMV_EE2A0_4", + "CLK_PMV_BYP5_3", + "CLK_PMV_NW4A1_2", + "CLK_PMV_WW4END2_3", + "CLK_PMV_IMUX19_0", + "CLK_PMV_CK_BUFG_CASC20", + "CLK_PMV_BYP5_1", + "CLK_PMV_LOGIC_OUTS0_3", + "CLK_PMV_CLK0_5", + "CLK_PMV_IMUX20_3", + "CLK_PMV_LOGIC_OUTS18_4", + "CLK_PMV_NE4C3_0", + "CLK_PMV_CK_BUFG_CASC31", + "CLK_PMV_SW2A2_5", + "CLK_PMV_NE4BEG2_3", + "CLK_PMV_MONITOR_P_4", + "CLK_PMV_WW4END2_1", + "CLK_PMV_CK_GCLK11", + "CLK_PMV_EE2BEG1_0", + "CLK_PMV_EE4BEG3_3", + "CLK_PMV_CK_BUFG_CASC12", + "CLK_PMV_NE4C3_6", + "CLK_PMV_BYP4_4", + "CLK_PMV_IMUX8_2", + "CLK_PMV_WW4A1_3", + "CLK_PMV_LH10_0", + "CLK_PMV_WW4B2_4", + "CLK_PMV_EE4B2_2", + "CLK_PMV_WW4A1_0", + "CLK_PMV_IMUX34_1", + "CLK_PMV_LH3_6", + "CLK_PMV_EE4BEG1_0", + "CLK_PMV_EL1BEG0_3", + "CLK_PMV_EL1BEG2_5", + "CLK_PMV_LOGIC_OUTS22_0", + "CLK_PMV_LH2_5", + "CLK_PMV_WW2A0_1", + "CLK_PMV_WW4C1_1", + "CLK_PMV_MONITOR_N_6", + "CLK_PMV_IMUX20_1", + "CLK_PMV_LH6_1", + "CLK_PMV_IMUX23_4", + "CLK_PMV_EE2BEG3_2", + "CLK_PMV_IMUX43_1", + "CLK_PMV_WW4B3_6", + "CLK_PMV_LOGIC_OUTS14_6", + "CLK_PMV_LOGIC_OUTS19_6", + "CLK_PMV_EE2A1_3", + "CLK_PMV_BYP0_1", + "CLK_PMV_NW2A3_2", + "CLK_PMV_NE4BEG2_2", + "CLK_PMV_NE4C3_3", + "CLK_PMV_BYP4_2", + "CLK_PMV_CK_BUFG_CASC17", + "CLK_PMV_IMUX12_6", + "CLK_PMV_EE4C2_0", + "CLK_PMV_SE2A3_4", + "CLK_PMV_IMUX31_3", + "CLK_PMV_IMUX42_3", + "CLK_PMV_WL1END3_1", + "CLK_PMV_NW4A3_2", + "CLK_PMV_LOGIC_OUTS12_0", + "CLK_PMV_EE2BEG2_4", + "CLK_PMV_IMUX2_1", + "CLK_PMV_LOGIC_OUTS0_2", + "CLK_PMV_WW4END3_3", + "CLK_PMV_IMUX40_3", + "CLK_PMV_NE4C2_0", + "CLK_PMV_EE4A1_2", + "CLK_PMV_IMUX27_5", + "CLK_PMV_BYP2_2", + "CLK_PMV_SE4C2_3", + "CLK_PMV_FAN5_4", + "CLK_PMV_ER1BEG0_0", + "CLK_PMV_EE4BEG3_1", + "CLK_PMV_WW4B2_1", + "CLK_PMV_IMUX36_6", + "CLK_PMV_NE4C1_3", + "CLK_PMV_WW4B0_3", + "CLK_PMV_NE4C0_2", + "CLK_PMV_WL1END3_6", + "CLK_PMV_WL1END3_5", + "CLK_PMV_LH4_5", + "CLK_PMV_NW4A1_3", + "CLK_PMV_SE2A0_3", + "CLK_PMV_IMUX21_3", + "CLK_PMV_WW4END1_5", + "CLK_PMV_IMUX28_4", + "CLK_PMV_IMUX8_1", + "CLK_PMV_SW2A2_1", + "CLK_PMV_IMUX22_2", + "CLK_PMV_R_CK_BUFG_CASC20", + "CLK_PMV_CK_GCLK24", + "CLK_PMV_LOGIC_OUTS11_3", + "CLK_PMV_EE4A3_2", + "CLK_PMV_NW4END1_3", + "CLK_PMV_SW4A3_2", + "CLK_PMV_IMUX6_6", + "CLK_PMV_IMUX33_6", + "CLK_PMV_EE4B1_2", + "CLK_PMV_IMUX38_6", + "CLK_PMV_LOGIC_OUTS8_1", + "CLK_PMV_SW4A1_3", + "CLK_PMV_EL1BEG3_4", + "CLK_PMV_CK_BUFG_CASC15", + "CLK_PMV_WW2END3_6", + "CLK_PMV_LH7_2", + "CLK_PMV_NW4A1_5", + "CLK_PMV_EE2A0_0", + "CLK_PMV_WR1END3_0", + "CLK_PMV_IMUX31_4", + "CLK_PMV_NE4BEG1_4", + "CLK_PMV_WW4C1_5", + "CLK_PMV_IMUX18_0", + "CLK_PMV_A4", + "CLK_PMV_WW2END0_3", + "CLK_PMV_WW2END2_0", + "CLK_PMV_NW2A0_2", + "CLK_PMV_R_CK_BUFG_CASC4", + "CLK_PMV_WW4A0_3", + "CLK_PMV_NE2A3_6", + "CLK_PMV_NE2A0_2", + "CLK_PMV_NW4END3_3", + "CLK_PMV_IMUX38_2", + "CLK_PMV_EE4C1_3", + "CLK_PMV_IMUX2_3", + "CLK_PMV_SE4C3_1", + "CLK_PMV_R_CK_BUFG_CASC16", + "CLK_PMV_NE2A3_4", + "CLK_PMV_WW2A3_0", + "CLK_PMV_EE2A2_3", + "CLK_PMV_SE4BEG2_0", + "CLK_PMV_LH6_2", + "CLK_PMV_SE4C0_1", + "CLK_PMV_IMUX1_2", + "CLK_PMV_NW2A0_1", + "CLK_PMV_ER1BEG2_0", + "CLK_PMV_SE4BEG1_5", + "CLK_PMV_EE4B2_6", + "CLK_PMV_NW2A2_5", + "CLK_PMV_EL1BEG1_6", + "CLK_PMV_IMUX36_5", + "CLK_PMV_EE2BEG3_3", + "CLK_PMV_SE4C1_4", + "CLK_PMV_WW2A0_3", + "CLK_PMV_SE2A1_0", + "CLK_PMV_IMUX16_5", + "CLK_PMV_WR1END0_0", + "CLK_PMV_EE2A1_2", + "CLK_PMV_IMUX23_0", + "CLK_PMV_IMUX46_1", + "CLK_PMV_LH3_1", + "CLK_PMV_LH2_2", + "CLK_PMV_FAN7_3", + "CLK_PMV_SW2A0_5", + "CLK_PMV_LOGIC_OUTS17_2", + "CLK_PMV_IMUX21_5", + "CLK_PMV_R_CK_BUFG_CASC27", + "CLK_PMV_EE2BEG0_3", + "CLK_PMV_R_CK_GCLK28", + "CLK_PMV_NE4C1_6", + "CLK_PMV_NW4A1_4", + "CLK_PMV_LOGIC_OUTS13_1", + "CLK_PMV_EE2BEG1_3", + "CLK_PMV_IMUX16_4", + "CLK_PMV_R_CK_BUFG_CASC10", + "CLK_PMV_WW4END3_6", + "CLK_PMV_IMUX15_1", + "CLK_PMV_WW4B2_5", + "CLK_PMV_FAN2_6", + "CLK_PMV_R_CK_GCLK2", + "CLK_PMV_LH7_6", + "CLK_PMV_WR1END1_5", + "CLK_PMV_WW4B2_0", + "CLK_PMV_EE2BEG0_1", + "CLK_PMV_LH1_4", + "CLK_PMV_LOGIC_OUTS7_0", + "CLK_PMV_WR1END0_1", + "CLK_PMV_NW4END3_2", + "CLK_PMV_EL1BEG2_2", + "CLK_PMV_WL1END1_4", + "CLK_PMV_LH6_4", + "CLK_PMV_NE4C2_4", + "CLK_PMV_BYP2_5", + "CLK_PMV_IMUX47_0", + "CLK_PMV_IMUX1_5", + "CLK_PMV_EE2A0_3", + "CLK_PMV_IMUX31_1", + "CLK_PMV_WW4B1_3", + "CLK_PMV_IMUX10_2", + "CLK_PMV_LOGIC_OUTS19_2", + "CLK_PMV_SW4A0_1", + "CLK_PMV_EE4C2_2", + "CLK_PMV_A0", + "CLK_PMV_SW2A0_6", + "CLK_PMV_WL1END1_6", + "CLK_PMV_LH11_6", + "CLK_PMV_IMUX31_0", + "CLK_PMV_SW4END0_1", + "CLK_PMV_ER1BEG3_2", + "CLK_PMV_BYP6_1", + "CLK_PMV_WW4END0_1", + "CLK_PMV_LOGIC_OUTS21_1", + "CLK_PMV_NW4END1_6", + "CLK_PMV_WW2A0_4", + "CLK_PMV_SW4A3_4", + "CLK_PMV_CK_GCLK16", + "CLK_PMV_SE4C1_2", + "CLK_PMV_R_CK_GCLK4", + "CLK_PMV_SW4A0_6", + "CLK_PMV_LOGIC_OUTS22_4", + "CLK_PMV_LOGIC_OUTS8_3", + "CLK_PMV_BYP4_3", + "CLK_PMV_EE4B2_1", + "CLK_PMV_NE4BEG3_5", + "CLK_PMV_LOGIC_OUTS5_6", + "CLK_PMV_WW2END2_5", + "CLK_PMV_R_CK_BUFG_CASC17", + "CLK_PMV_IMUX30_0", + "CLK_PMV_BYP1_2", + "CLK_PMV_IMUX30_3", + "CLK_PMV_BYP3_0", + "CLK_PMV_LOGIC_OUTS14_0", + "CLK_PMV_WL1END1_1", + "CLK_PMV_CTRL0_5", + "CLK_PMV_WW2A2_1", + "CLK_PMV_NE4BEG0_3", + "CLK_PMV_SE2A0_6", + "CLK_PMV_MONITOR_P_5", + "CLK_PMV_A3", + "CLK_PMV_SE4BEG3_1", + "CLK_PMV_IMUX26_5", + "CLK_PMV_IMUX36_4", + "CLK_PMV_EE2A2_5", + "CLK_PMV_CK_GCLK14", + "CLK_PMV_NW2A1_4", + "CLK_PMV_NE4C1_2", + "CLK_PMV_WW4A3_3", + "CLK_PMV_IMUX43_4", + "CLK_PMV_IMUX28_0", + "CLK_PMV_SW4END1_0", + "CLK_PMV_LOGIC_OUTS19_5", + "CLK_PMV_WW4A2_2", + "CLK_PMV_EE2BEG2_2", + "CLK_PMV_WR1END3_4", + "CLK_PMV_EE4BEG0_3", + "CLK_PMV_LH3_2", + "CLK_PMV_NW4END0_1", + "CLK_PMV_EE4B1_5", + "CLK_PMV_IMUX41_0", + "CLK_PMV_SW4A3_0", + "CLK_PMV_LOGIC_OUTS1_2", + "CLK_PMV_IMUX35_0", + "CLK_PMV_IMUX23_5", + "CLK_PMV_IMUX28_6", + "CLK_PMV_WR1END0_3", + "CLK_PMV_WW4A0_5", + "CLK_PMV_WW4B3_2", + "CLK_PMV_ER1BEG1_3", + "CLK_PMV_R_CK_GCLK12", + "CLK_PMV_WW2END2_1", + "CLK_PMV_SE4C0_2", + "CLK_PMV_SW4A2_0", + "CLK_PMV_CK_GCLK10", + "CLK_PMV_IMUX11_0", + "CLK_PMV_SW4A0_0", + "CLK_PMV_EE2BEG3_5", + "CLK_PMV_NE4C2_5", + "CLK_PMV_WW2A0_0", + "CLK_PMV_EL1BEG0_0", + "CLK_PMV_IMUX21_0", + "CLK_PMV_IMUX26_3", + "CLK_PMV_IMUX41_2", + "CLK_PMV_BYP7_5", + "CLK_PMV_IMUX46_4", + "CLK_PMV_CK_BUFG_CASC23", + "CLK_PMV_MONITOR_P_2", + "CLK_PMV_LOGIC_OUTS4_3", + "CLK_PMV_EE4C1_5", + "CLK_PMV_WW2END3_2", + "CLK_PMV_LOGIC_OUTS21_3", + "CLK_PMV_SE4BEG2_4", + "CLK_PMV_WW4END0_4", + "CLK_PMV_FAN6_0", + "CLK_PMV_SE4C1_0", + "CLK_PMV_WR1END0_6", + "CLK_PMV_EE4A1_1", + "CLK_PMV_IMUX32_0", + "CLK_PMV_CTRL0_3", + "CLK_PMV_WR1END3_1", + "CLK_PMV_IMUX42_6", + "CLK_PMV_LOGIC_OUTS16_6", + "CLK_PMV_WW2A3_3", + "CLK_PMV_SE4BEG1_4", + "CLK_PMV_IMUX5_1", + "CLK_PMV_WW4C3_5", + "CLK_PMV_LOGIC_OUTS21_0", + "CLK_PMV_IMUX1_1", + "CLK_PMV_IMUX24_3", + "CLK_PMV_FAN4_6", + "CLK_PMV_IMUX24_2", + "CLK_PMV_EE2BEG3_0", + "CLK_PMV_IMUX43_5", + "CLK_PMV_MONITOR_P_0", + "CLK_PMV_EN", + "CLK_PMV_LH12_4", + "CLK_PMV_EE4BEG1_1", + "CLK_PMV_LOGIC_OUTS22_5", + "CLK_PMV_EE4BEG0_1", + "CLK_PMV_IMUX29_1", + "CLK_PMV_IMUX5_6", + "CLK_PMV_SW4END2_6", + "CLK_PMV_EL1BEG2_6", + "CLK_PMV_NW4A1_1", + "CLK_PMV_NE4BEG3_2", + "CLK_PMV_LH1_0", + "CLK_PMV_LOGIC_OUTS21_6", + "CLK_PMV_SE4C0_4", + "CLK_PMV_NE2A0_4", + "CLK_PMV_NW2A2_1", + "CLK_PMV_SE4BEG3_3", + "CLK_PMV_EE4C0_0", + "CLK_PMV_IMUX13_3", + "CLK_PMV_FAN1_4", + "CLK_PMV_NE4C1_0", + "CLK_PMV_NE4BEG2_1", + "CLK_PMV_EE4A1_3", + "CLK_PMV_EE2A3_5", + "CLK_PMV_R_CK_BUFG_CASC31", + "CLK_PMV_SW4A2_4", + "CLK_PMV_IMUX9_5", + "CLK_PMV_EE4B0_2", + "CLK_PMV_BYP4_5", + "CLK_PMV_NW4END3_4", + "CLK_PMV_IMUX41_6", + "CLK_PMV_WW2END3_1", + "CLK_PMV_IMUX22_4", + "CLK_PMV_EE2BEG0_4", + "CLK_PMV_BYP0_5", + "CLK_PMV_BYP7_3", + "CLK_PMV_IMUX10_6", + "CLK_PMV_FAN1_0", + "CLK_PMV_CK_GCLK21", + "CLK_PMV_EE4B0_1", + "CLK_PMV_LH10_4", + "CLK_PMV_IMUX12_4", + "CLK_PMV_FAN6_1", + "CLK_PMV_NW4END2_6", + "CLK_PMV_IMUX39_0", + "CLK_PMV_IMUX14_5", + "CLK_PMV_SE4BEG2_6", + "CLK_PMV_IMUX27_3", + "CLK_PMV_IMUX32_3", + "CLK_PMV_ER1BEG0_2", + "CLK_PMV_EE4C3_2", + "CLK_PMV_R_CK_GCLK22", + "CLK_PMV_EE2A1_6", + "CLK_PMV_NW4END3_5", + "CLK_PMV_NE2A1_3", + "CLK_PMV_LH11_2", + "CLK_PMV_SE4C1_5", + "CLK_PMV_SW2A1_1", + "CLK_PMV_R_CK_BUFG_CASC0", + "CLK_PMV_EL1BEG1_5", + "CLK_PMV_WW4C3_0", + "CLK_PMV_WW4B0_1", + "CLK_PMV_IMUX25_6", + "CLK_PMV_SE4BEG0_4", + "CLK_PMV_SE2A1_6", + "CLK_PMV_LH5_1", + "CLK_PMV_FAN4_5", + "CLK_PMV_R_CK_BUFG_CASC14", + "CLK_PMV_SW2A3_2", + "CLK_PMV_EE4C2_3", + "CLK_PMV_WW4C0_5", + "CLK_PMV_IMUX25_1", + "CLK_PMV_SE2A0_4", + "CLK_PMV_IMUX47_6", + "CLK_PMV_LOGIC_OUTS23_5", + "CLK_PMV_IMUX5_2", + "CLK_PMV_ER1BEG0_3", + "CLK_PMV_SE2A3_3", + "CLK_PMV_BYP5_2", + "CLK_PMV_IMUX3_2", + "CLK_PMV_IMUX35_4", + "CLK_PMV_EE4A0_4", + "CLK_PMV_IMUX0_6", + "CLK_PMV_IMUX0_4", + "CLK_PMV_SE2A0_5", + "CLK_PMV_NW4END1_2", + "CLK_PMV_ODIV4", + "CLK_PMV_LOGIC_OUTS11_2", + "CLK_PMV_WW4A3_2", + "CLK_PMV_EE4B1_4", + "CLK_PMV_EE4C0_3", + "CLK_PMV_SW4END3_5", + "CLK_PMV_FAN1_1", + "CLK_PMV_LH5_5", + "CLK_PMV_SE4BEG0_3", + "CLK_PMV_LH1_3", + "CLK_PMV_IMUX30_1", + "CLK_PMV_LOGIC_OUTS13_5", + "CLK_PMV_NE2A2_1", + "CLK_PMV_IMUX26_0", + "CLK_PMV_IMUX15_4", + "CLK_PMV_CTRL1_6", + "CLK_PMV_IMUX18_4", + "CLK_PMV_IMUX3_3", + "CLK_PMV_EE4B2_0", + "CLK_PMV_IMUX42_1", + "CLK_PMV_LOGIC_OUTS12_4", + "CLK_PMV_WW2A1_4", + "CLK_PMV_ER1BEG1_0", + "CLK_PMV_SW4END2_3", + "CLK_PMV_LOGIC_OUTS5_3", + "CLK_PMV_CLK1_4", + "CLK_PMV_A2", + "CLK_PMV_WW4B1_1", + "CLK_PMV_NW4A3_6", + "CLK_PMV_LH4_1", + "CLK_PMV_IMUX25_4", + "CLK_PMV_EE4B2_5", + "CLK_PMV_NE2A2_5", + "CLK_PMV_EE2A3_1", + "CLK_PMV_LOGIC_OUTS9_1", + "CLK_PMV_NE2A3_3", + "CLK_PMV_WW4END1_2", + "CLK_PMV_SE4BEG1_2", + "CLK_PMV_WL1END1_2", + "CLK_PMV_CTRL0_4", + "CLK_PMV_LOGIC_OUTS8_2", + "CLK_PMV_LOGIC_OUTS14_5", + "CLK_PMV_SW2A0_1", + "CLK_PMV_LH11_1", + "CLK_PMV_EE2BEG3_4", + "CLK_PMV_IMUX31_6", + "CLK_PMV_LH5_3", + "CLK_PMV_LH11_3", + "CLK_PMV_SE4C0_5", + "CLK_PMV_LH12_0", + "CLK_PMV_EE2A3_3", + "CLK_PMV_EL1BEG1_4", + "CLK_PMV_WW4END0_5", + "CLK_PMV_CLK0_1", + "CLK_PMV_LOGIC_OUTS12_2", + "CLK_PMV_WW4B0_4", + "CLK_PMV_IMUX42_5", + "CLK_PMV_EE2BEG1_2", + "CLK_PMV_IMUX2_6", + "CLK_PMV_FAN7_4", + "CLK_PMV_CK_GCLK15", + "CLK_PMV_SW4A2_1", + "CLK_PMV_LOGIC_OUTS21_5", + "CLK_PMV_NE2A0_1", + "CLK_PMV_NE4C3_5", + "CLK_PMV_SW2A1_4", + "CLK_PMV_EE4B1_1", + "CLK_PMV_IMUX47_3", + "CLK_PMV_WW2END3_0", + "CLK_PMV_IMUX40_4", + "CLK_PMV_IMUX35_3", + "CLK_PMV_EE4BEG3_6", + "CLK_PMV_LH2_1", + "CLK_PMV_EE4A0_0", + "CLK_PMV_LOGIC_OUTS17_0", + "CLK_PMV_SE4C0_3", + "CLK_PMV_IMUX40_0", + "CLK_PMV_CK_GCLK31", + "CLK_PMV_SW4END3_0", + "CLK_PMV_FAN7_5", + "CLK_PMV_CK_BUFG_CASC6", + "CLK_PMV_LOGIC_OUTS9_0", + "CLK_PMV_FAN7_1", + "CLK_PMV_NE4BEG0_2", + "CLK_PMV_LH10_5", + "CLK_PMV_LOGIC_OUTS23_6", + "CLK_PMV_IMUX19_4", + "CLK_PMV_FAN6_3", + "CLK_PMV_IMUX1_3", + "CLK_PMV_IMUX4_1", + "CLK_PMV_CK_GCLK27", + "CLK_PMV_EE2BEG1_6", + "CLK_PMV_IMUX43_3", + "CLK_PMV_LH5_2", + "CLK_PMV_EE4B2_4", + "CLK_PMV_WW2END0_0", + "CLK_PMV_NE4BEG0_0", + "CLK_PMV_IMUX11_4", + "CLK_PMV_IMUX38_0", + "CLK_PMV_IMUX6_1", + "CLK_PMV_NE4BEG2_0", + "CLK_PMV_IMUX37_4", + "CLK_PMV_EL1BEG1_3", + "CLK_PMV_EE4BEG3_4", + "CLK_PMV_FAN5_0", + "CLK_PMV_IMUX33_2", + "CLK_PMV_NE4BEG1_0", + "CLK_PMV_FAN3_6", + "CLK_PMV_EE2A0_5", + "CLK_PMV_LOGIC_OUTS9_4", + "CLK_PMV_LOGIC_OUTS20_2", + "CLK_PMV_EE4BEG2_3", + "CLK_PMV_FAN0_6", + "CLK_PMV_WW2END0_1", + "CLK_PMV_WL1END2_0", + "CLK_PMV_IMUX40_5", + "CLK_PMV_BYP1_1", + "CLK_PMV_WW4C2_6", + "CLK_PMV_WR1END0_2", + "CLK_PMV_NW4A2_6", + "CLK_PMV_LH11_4", + "CLK_PMV_NE2A1_5", + "CLK_PMV_LOGIC_OUTS16_4", + "CLK_PMV_LOGIC_OUTS2_4", + "CLK_PMV_IMUX8_0", + "CLK_PMV_CK_GCLK5", + "CLK_PMV_WW2A2_3", + "CLK_PMV_IMUX12_5", + "CLK_PMV_FAN0_2", + "CLK_PMV_EE4A3_3", + "CLK_PMV_R_CK_GCLK15", + "CLK_PMV_EE4A3_1", + "CLK_PMV_EE4A1_0", + "CLK_PMV_LOGIC_OUTS15_2", + "CLK_PMV_LOGIC_OUTS10_5", + "CLK_PMV_EE4A0_6", + "CLK_PMV_BYP0_2", + "CLK_PMV_SE4C2_1", + "CLK_PMV_FAN4_0", + "CLK_PMV_WW2A3_5", + "CLK_PMV_LOGIC_OUTS18_0", + "CLK_PMV_LOGIC_OUTS10_3", + "CLK_PMV_EE2A2_1", + "CLK_PMV_LH1_5", + "CLK_PMV_IMUX29_2", + "CLK_PMV_SE2A2_4", + "CLK_PMV_IMUX32_5", + "CLK_PMV_SW4END2_0", + "CLK_PMV_SE4C1_6", + "CLK_PMV_SE4C3_6", + "CLK_PMV_EE4BEG3_5", + "CLK_PMV_SW4END1_3", + "CLK_PMV_EE4B3_2", + "CLK_PMV_WR1END2_2", + "CLK_PMV_IMUX19_6", + "CLK_PMV_WW4END3_5", + "CLK_PMV_NW4A3_4", + "CLK_PMV_LH9_0", + "CLK_PMV_LH8_4", + "CLK_PMV_NE4C3_4", + "CLK_PMV_IMUX18_5", + "CLK_PMV_IMUX23_1", + "CLK_PMV_R_CK_GCLK5", + "CLK_PMV_WL1END0_6", + "CLK_PMV_IMUX17_4", + "CLK_PMV_LOGIC_OUTS5_4", + "CLK_PMV_WW4A3_1", + "CLK_PMV_NW2A1_6", + "CLK_PMV_WW4END1_1", + "CLK_PMV_WW4END1_6", + "CLK_PMV_IMUX18_2", + "CLK_PMV_EE4B1_3", + "CLK_PMV_BYP4_0", + "CLK_PMV_IMUX8_6", + "CLK_PMV_NE2A3_5", + "CLK_PMV_WW4A2_6", + "CLK_PMV_LH4_6", + "CLK_PMV_WL1END2_1", + "CLK_PMV_WL1END2_2", + "CLK_PMV_LOGIC_OUTS5_0", + "CLK_PMV_IMUX28_1", + "CLK_PMV_LOGIC_OUTS3_5", + "CLK_PMV_FAN6_5", + "CLK_PMV_LOGIC_OUTS1_0", + "CLK_PMV_IMUX0_5", + "CLK_PMV_LOGIC_OUTS6_5", + "CLK_PMV_IMUX11_1", + "CLK_PMV_EE4A3_6", + "CLK_PMV_WR1END0_5", + "CLK_PMV_EE4BEG2_4", + "CLK_PMV_EL1BEG0_6", + "CLK_PMV_LOGIC_OUTS9_5", + "CLK_PMV_SW2A3_6", + "CLK_PMV_IMUX4_4", + "CLK_PMV_IMUX1_0", + "CLK_PMV_WW4B2_3", + "CLK_PMV_BYP0_4", + "CLK_PMV_LH5_4", + "CLK_PMV_WW2END1_4", + "CLK_PMV_SE2A3_1", + "CLK_PMV_A5", + "CLK_PMV_R_CK_BUFG_CASC2", + "CLK_PMV_LOGIC_OUTS20_6", + "CLK_PMV_BYP6_5", + "CLK_PMV_WW4C0_2", + "CLK_PMV_LOGIC_OUTS11_6", + "CLK_PMV_LOGIC_OUTS8_4", + "CLK_PMV_R_CK_BUFG_CASC30", + "CLK_PMV_LH9_3", + "CLK_PMV_WW4A2_3", + "CLK_PMV_EE4BEG1_3", + "CLK_PMV_EE4B3_1", + "CLK_PMV_EE2A2_6", + "CLK_PMV_IMUX3_1", + "CLK_PMV_IMUX6_3", + "CLK_PMV_IMUX11_6", + "CLK_PMV_IMUX3_6", + "CLK_PMV_FAN0_3", + "CLK_PMV_LOGIC_OUTS20_4", + "CLK_PMV_WW2A0_2", + "CLK_PMV_IMUX11_5", + "CLK_PMV_IMUX17_2", + "CLK_PMV_EL1BEG0_1", + "CLK_PMV_NE4C2_3", + "CLK_PMV_IMUX39_3", + "CLK_PMV_EE4A1_4", + "CLK_PMV_BYP3_2", + "CLK_PMV_CK_BUFG_CASC26", + "CLK_PMV_IMUX14_3", + "CLK_PMV_IMUX21_1", + "CLK_PMV_LOGIC_OUTS13_4", + "CLK_PMV_WW4C2_4", + "CLK_PMV_R_CK_BUFG_CASC9", + "CLK_PMV_LOGIC_OUTS22_2", + "CLK_PMV_EE4A0_5", + "CLK_PMV_R_CK_GCLK3", + "CLK_PMV_IMUX37_0", + "CLK_PMV_IMUX44_4", + "CLK_PMV_IMUX44_6", + "CLK_PMV_SW4A0_4", + "CLK_PMV_EE4B3_0", + "CLK_PMV_WW4END2_6", + "CLK_PMV_NE2A2_4", + "CLK_PMV_LOGIC_OUTS5_1", + "CLK_PMV_LOGIC_OUTS17_4", + "CLK_PMV_EE4C0_4", + "CLK_PMV_EE4A2_1", + "CLK_PMV_SE4BEG3_6", + "CLK_PMV_LH3_4", + "CLK_PMV_SE4BEG2_1", + "CLK_PMV_CK_GCLK8", + "CLK_PMV_WW4END0_6", + "CLK_PMV_R_CK_GCLK13", + "CLK_PMV_NW4A2_1", + "CLK_PMV_CK_GCLK13", + "CLK_PMV_IMUX26_2", + "CLK_PMV_R_CK_GCLK11", + "CLK_PMV_CK_GCLK1", + "CLK_PMV_WW4END1_0", + "CLK_PMV_WL1END2_3", + "CLK_PMV_IMUX32_2", + "CLK_PMV_LOGIC_OUTS6_6", + "CLK_PMV_IMUX21_2", + "CLK_PMV_EE4BEG0_0", + "CLK_PMV_LOGIC_OUTS4_0", + "CLK_PMV_ER1BEG0_1", + "CLK_PMV_ER1BEG3_4", + "CLK_PMV_NW4END3_1", + "CLK_PMV_SE4BEG3_4", + "CLK_PMV_EE4C1_1", + "CLK_PMV_WR1END1_0", + "CLK_PMV_WW4B0_2", + "CLK_PMV_IMUX20_5", + "CLK_PMV_IMUX39_2", + "CLK_PMV_R_CK_BUFG_CASC26", + "CLK_PMV_LOGIC_OUTS4_6", + "CLK_PMV_BYP1_6", + "CLK_PMV_IMUX20_6", + "CLK_PMV_WW2A2_2", + "CLK_PMV_WW4A1_6", + "CLK_PMV_IMUX12_0", + "CLK_PMV_LH12_2", + "CLK_PMV_LH7_1", + "CLK_PMV_SW4A1_2", + "CLK_PMV_IMUX39_4", + "CLK_PMV_CK_GCLK28", + "CLK_PMV_R_CK_BUFG_CASC1", + "CLK_PMV_R_CK_BUFG_CASC18", + "CLK_PMV_NE2A3_2", + "CLK_PMV_WW4A1_2", + "CLK_PMV_ER1BEG3_3", + "CLK_PMV_SE4C3_4", + "CLK_PMV_CK_BUFG_CASC10", + "CLK_PMV_LOGIC_OUTS12_5", + "CLK_PMV_WL1END2_6", + "CLK_PMV_EE2A3_6", + "CLK_PMV_BYP6_4", + "CLK_PMV_NW4END0_4", + "CLK_PMV_WW4END0_2", + "CLK_PMV_EE4B0_0", + "CLK_PMV_SW4A2_6", + "CLK_PMV_BYP5_4", + "CLK_PMV_LH12_3", + "CLK_PMV_CLK0_4", + "CLK_PMV_BYP7_4", + "CLK_PMV_WW2A3_1", + "CLK_PMV_LH7_0", + "CLK_PMV_LOGIC_OUTS5_5", + "CLK_PMV_LOGIC_OUTS10_0", + "CLK_PMV_IMUX6_0", + "CLK_PMV_NE4C0_0", + "CLK_PMV_CTRL1_2", + "CLK_PMV_R_CK_BUFG_CASC21", + "CLK_PMV_WW4C1_0", + "CLK_PMV_IMUX9_6", + "CLK_PMV_NE2A2_3", + "CLK_PMV_NE4BEG0_5", + "CLK_PMV_CK_BUFG_CASC19", + "CLK_PMV_IMUX18_3", + "CLK_PMV_SE2A2_5", + "CLK_PMV_NW4A0_2", + "CLK_PMV_LH7_5", + "CLK_PMV_NW4A0_0", + "CLK_PMV_A1", + "CLK_PMV_IMUX45_2", + "CLK_PMV_WW2END1_6", + "CLK_PMV_R_CK_GCLK6", + "CLK_PMV_R_CK_BUFG_CASC13", + "CLK_PMV_WW4C0_6", + "CLK_PMV_LH8_6", + "CLK_PMV_EE4BEG2_0", + "CLK_PMV_EE4BEG1_4", + "CLK_PMV_ER1BEG1_5", + "CLK_PMV_SE4C0_6", + "CLK_PMV_NE4C2_1", + "CLK_PMV_EE4C0_5", + "CLK_PMV_SE4C0_0", + "CLK_PMV_ER1BEG1_6", + "CLK_PMV_IMUX7_4", + "CLK_PMV_MONITOR_N_4", + "CLK_PMV_IMUX19_1", + "CLK_PMV_EE4A2_3", + "CLK_PMV_WW4END3_0", + "CLK_PMV_IMUX42_0", + "CLK_PMV_IMUX20_2", + "CLK_PMV_BYP6_0", + "CLK_PMV_LOGIC_OUTS2_0", + "CLK_PMV_IMUX10_1", + "CLK_PMV_EE2A3_0", + "CLK_PMV_IMUX25_3", + "CLK_PMV_WW2A0_6", + "CLK_PMV_LH8_5", + "CLK_PMV_LOGIC_OUTS17_6", + "CLK_PMV_IMUX2_5", + "CLK_PMV_EE4C2_1", + "CLK_PMV_ODIV2", + "CLK_PMV_SW2A1_5", + "CLK_PMV_LH1_6", + "CLK_PMV_IMUX33_4", + "CLK_PMV_IMUX17_6", + "CLK_PMV_SE2A2_3", + "CLK_PMV_LOGIC_OUTS8_6", + "CLK_PMV_EE4B3_5", + "CLK_PMV_EE4BEG1_5", + "CLK_PMV_WW4END3_4", + "CLK_PMV_WW4C3_2", + "CLK_PMV_CK_GCLK3", + "CLK_PMV_NW4A2_5", + "CLK_PMV_BYP0_3", + "CLK_PMV_EE2A1_1", + "CLK_PMV_IMUX38_4", + "CLK_PMV_EE4BEG2_1", + "CLK_PMV_EE2A2_2", + "CLK_PMV_R_CK_BUFG_CASC8", + "CLK_PMV_SW4A3_1", + "CLK_PMV_FAN6_4", + "CLK_PMV_EE2A0_2", + "CLK_PMV_NW4END3_6", + "CLK_PMV_FAN2_3", + "CLK_PMV_IMUX14_1", + "CLK_PMV_CK_GCLK20", + "CLK_PMV_WW4C1_6", + "CLK_PMV_WW2END1_1", + "CLK_PMV_NE4C3_1", + "CLK_PMV_WL1END3_2", + "CLK_PMV_EE2BEG3_1", + "CLK_PMV_LH9_6", + "CLK_PMV_LOGIC_OUTS9_6", + "CLK_PMV_SE4BEG0_0", + "CLK_PMV_ER1BEG2_5", + "CLK_PMV_IMUX41_3", + "CLK_PMV_BYP2_4", + "CLK_PMV_LOGIC_OUTS22_1", + "CLK_PMV_IMUX5_3", + "CLK_PMV_IMUX13_0", + "CLK_PMV_FAN5_1", + "CLK_PMV_EE4BEG1_6", + "CLK_PMV_SW4A2_2", + "CLK_PMV_SE2A1_5", + "CLK_PMV_EE2BEG2_1", + "CLK_PMV_EE4A0_3", + "CLK_PMV_IMUX47_4", + "CLK_PMV_WW2A2_6", + "CLK_PMV_SW4A1_1", + "CLK_PMV_IMUX9_4", + "CLK_PMV_FAN7_6", + "CLK_PMV_LOGIC_OUTS0_0", + "CLK_PMV_EE4B3_6", + "CLK_PMV_IMUX27_2", + "CLK_PMV_EL1BEG3_2", + "CLK_PMV_SE4BEG0_5", + "CLK_PMV_SE4C2_2", + "CLK_PMV_NW2A1_0", + "CLK_PMV_LH10_2", + "CLK_PMV_FAN2_0", + "CLK_PMV_SE4C3_5", + "CLK_PMV_LH12_5", + "CLK_PMV_WW2A2_4", + "CLK_PMV_WR1END2_5", + "CLK_PMV_LOGIC_OUTS21_2" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_CLK_PMV2.json b/kintex7/tile_type_CLK_PMV2.json new file mode 100644 index 0000000..f3ae66c --- /dev/null +++ b/kintex7/tile_type_CLK_PMV2.json @@ -0,0 +1,377 @@ +{ + "tile_type": "CLK_PMV2", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "PMV", + "type": "PMV2", + "site_pins": { + "A2": "CLK_PMV2_A2", + "A0": "CLK_PMV2_A0", + "A1": "CLK_PMV2_A1", + "EN": "CLK_PMV2_EN", + "O": "CLK_PMV2_O", + "ODIV4": "CLK_PMV2_ODIV4", + "ODIV2": "CLK_PMV2_ODIV2" + }, + "x_coord": 0 + } + ], + "wires": [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_SW4A1", + "CLK_PMV_BYP2_0", + "CLK_FEED_CK_GCLK31", + "CLK_FEED_CK_BUFG_CASC9", + "CLK_FEED_EL1BEG1", + "CLK_FEED_WW2END2", + "CLK_PMV_IMUX5_0", + "CLK_PMV_LOGIC_OUTS19_0", + "CLK_PMV_IMUX36_0", + "CLK_PMV_IMUX16_0", + "CLK_FEED_EE2BEG3", + "CLK_PMV_IMUX22_0", + "CLK_PMV_IMUX26_0", + "CLK_FEED_CK_BUFG_CASC16", + "CLK_FEED_CK_GCLK16", + "CLK_FEED_SE4BEG3", + "CLK_FEED_LH1", + "CLK_FEED_EE4C2", + "CLK_PMV_IMUX0_0", + "CLK_FEED_CK_GCLK17", + "CLK_FEED_NW4END2", + "CLK_FEED_CK_GCLK5", + "CLK_FEED_NE4BEG3", + "CLK_PMV_IMUX19_0", + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_GCLK14", + "CLK_PMV_IMUX2_0", + "CLK_FEED_EE4A2", + "CLK_PMV_IMUX27_0", + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_CK_GCLK21", + "CLK_FEED_EE2A2", + "CLK_FEED_EE4B3", + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_PMV_CTRL1_0", + "CLK_FEED_EE4B0", + "CLK_FEED_EE4A3", + "CLK_PMV_LOGIC_OUTS11_0", + "CLK_FEED_CK_GCLK8", + "CLK_PMV_IMUX33_0", + "CLK_FEED_NW4END0", + "CLK_PMV_IMUX15_0", + "CLK_FEED_R_CK_GCLK20", + "CLK_PMV_LOGIC_OUTS22_0", + "CLK_FEED_CK_BUFG_CASC21", + "CLK_FEED_WW4B0", + "CLK_FEED_CK_BUFG_CASC2", + "CLK_PMV_IMUX40_0", + "CLK_PMV_LOGIC_OUTS17_0", + "CLK_FEED_CK_BUFG_CASC20", + "CLK_PMV_LOGIC_OUTS9_0", + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_ER1BEG1", + "CLK_FEED_SE4BEG0", + "CLK_FEED_CK_BUFG_CASC26", + "CLK_FEED_WW4A0", + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_WW4B2", + "CLK_FEED_SW2A1", + "CLK_FEED_LH3", + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_PMV_IMUX38_0", + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_GCLK30", + "CLK_PMV_LOGIC_OUTS12_0", + "CLK_PMV_FAN3_0", + "CLK_FEED_WW4END2", + "CLK_FEED_CK_BUFG_CASC1", + "CLK_FEED_EL1BEG3", + "CLK_FEED_SE2A2", + "CLK_PMV_FAN5_0", + "CLK_PMV_LOGIC_OUTS3_0", + "CLK_FEED_NW4END1", + "CLK_FEED_LH8", + "CLK_FEED_LH4", + "CLK_FEED_CK_GCLK29", + "CLK_FEED_CK_GCLK14", + "CLK_FEED_SE4C0", + "CLK_FEED_LH9", + "CLK_FEED_WR1END3", + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_EE4BEG2", + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_CK_GCLK19", + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_CK_GCLK25", + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_WW4END1", + "CLK_PMV_IMUX8_0", + "CLK_FEED_CK_GCLK23", + "CLK_FEED_EE4B1", + "CLK_PMV2_O", + "CLK_FEED_CK_BUFG_CASC10", + "CLK_FEED_EE2BEG1", + "CLK_PMV_LOGIC_OUTS20_0", + "CLK_PMV_FAN4_0", + "CLK_FEED_R_CK_GCLK9", + "CLK_PMV2_A1", + "CLK_FEED_SW4A3", + "CLK_PMV_LOGIC_OUTS18_0", + "CLK_FEED_SE4C1", + "CLK_FEED_NW4A2", + "CLK_FEED_CK_GCLK15", + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_PMV_BYP7_0", + "CLK_FEED_CK_GCLK20", + "CLK_FEED_CK_BUFG_CASC5", + "CLK_PMV_IMUX18_0", + "CLK_FEED_LH11", + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_PMV_BYP5_0", + "CLK_PMV_IMUX25_0", + "CLK_FEED_NE2A1", + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_CK_BUFG_CASC13", + "CLK_FEED_CK_BUFG_CASC18", + "CLK_FEED_CK_GCLK11", + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_CK_GCLK2", + "CLK_PMV_LOGIC_OUTS16_0", + "CLK_PMV_IMUX24_0", + "CLK_FEED_CK_BUFG_CASC11", + "CLK_FEED_CK_GCLK3", + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_CK_BUFG_CASC15", + "CLK_PMV_FAN0_0", + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_PMV2_ODIV4", + "CLK_FEED_CK_BUFG_CASC23", + "CLK_PMV_IMUX44_0", + "CLK_FEED_CK_BUFG_CASC28", + "CLK_PMV_BYP4_0", + "CLK_FEED_MONITOR_P", + "CLK_FEED_WW4A3", + "CLK_FEED_R_CK_GCLK26", + "CLK_PMV_LOGIC_OUTS5_0", + "CLK_FEED_CK_GCLK27", + "CLK_PMV_IMUX23_0", + "CLK_FEED_R_CK_GCLK23", + "CLK_PMV_LOGIC_OUTS1_0", + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_NE4C1", + "CLK_FEED_CK_BUFG_CASC25", + "CLK_FEED_CK_BUFG_CASC6", + "CLK_PMV_IMUX1_0", + "CLK_PMV_IMUX7_0", + "CLK_FEED_CK_GCLK1", + "CLK_FEED_NE2A3", + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_ER1BEG3", + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_CK_BUFG_CASC8", + "CLK_PMV_FAN7_0", + "CLK_PMV_BYP0_0", + "CLK_FEED_CK_BUFG_CASC30", + "CLK_FEED_CK_GCLK22", + "CLK_PMV_CLK0_0", + "CLK_PMV2_EN", + "CLK_PMV_LOGIC_OUTS7_0", + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_WL1END1", + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_PMV_BYP1_0", + "CLK_FEED_EE2BEG2", + "CLK_PMV_CTRL0_0", + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_EE4C3", + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_PMV_LOGIC_OUTS8_0", + "CLK_PMV_IMUX47_0", + "CLK_FEED_CK_BUFG_CASC3", + "CLK_FEED_SE4C2", + "CLK_FEED_WL1END0", + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_CK_BUFG_CASC17", + "CLK_FEED_EE4BEG0", + "CLK_FEED_CK_BUFG_CASC22", + "CLK_FEED_WW4C2", + "CLK_FEED_EE2A1", + "CLK_PMV_IMUX31_0", + "CLK_FEED_EE4A0", + "CLK_PMV_IMUX37_0", + "CLK_FEED_WR1END0", + "CLK_PMV_IMUX20_0", + "CLK_FEED_CK_GCLK6", + "CLK_FEED_WR1END1", + "CLK_FEED_NE4BEG1", + "CLK_PMV2_ODIV2", + "CLK_FEED_CK_BUFG_CASC0", + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_WL1END3", + "CLK_FEED_CK_GCLK10", + "CLK_FEED_CK_GCLK0", + "CLK_FEED_CK_GCLK30", + "CLK_FEED_EE4C0", + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_PMV_IMUX46_0", + "CLK_PMV_IMUX30_0", + "CLK_FEED_SE4BEG2", + "CLK_PMV_BYP3_0", + "CLK_PMV_LOGIC_OUTS14_0", + "CLK_PMV_IMUX17_0", + "CLK_PMV_LOGIC_OUTS4_0", + "CLK_FEED_EE2A3", + "CLK_FEED_WW4B3", + "CLK_FEED_EE4BEG1", + "CLK_FEED_CK_BUFG_CASC7", + "CLK_PMV_IMUX9_0", + "CLK_PMV_LOGIC_OUTS23_0", + "CLK_PMV2_A0", + "CLK_FEED_EE4A1", + "CLK_FEED_R_CK_GCLK12", + "CLK_PMV_IMUX28_0", + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_GCLK4", + "CLK_PMV_IMUX12_0", + "CLK_FEED_NE4C3", + "CLK_FEED_NW2A2", + "CLK_FEED_ER1BEG2", + "CLK_PMV_IMUX41_0", + "CLK_FEED_SW4END2", + "CLK_FEED_WW2A3", + "CLK_FEED_LH12", + "CLK_FEED_SW2A3", + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_PMV_IMUX35_0", + "CLK_FEED_SW4A2", + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_SW4END3", + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_NE4BEG2", + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_EL1BEG2", + "CLK_PMV_CLK1_0", + "CLK_FEED_WW4C3", + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_WL1END2", + "CLK_FEED_CK_GCLK26", + "CLK_FEED_ER1BEG0", + "CLK_FEED_SW2A2", + "CLK_FEED_WW2END1", + "CLK_PMV_IMUX11_0", + "CLK_FEED_WR1END2", + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_SW4A0", + "CLK_FEED_SE2A0", + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_GCLK10", + "CLK_PMV_IMUX34_0", + "CLK_PMV_IMUX21_0", + "CLK_FEED_CK_BUFG_CASC31", + "CLK_FEED_NW4A3", + "CLK_FEED_WW2A1", + "CLK_PMV_LOGIC_OUTS10_0", + "CLK_PMV_IMUX6_0", + "CLK_FEED_CK_BUFG_CASC19", + "CLK_FEED_CK_BUFG_CASC27", + "CLK_FEED_CK_GCLK18", + "CLK_PMV_FAN6_0", + "CLK_PMV_IMUX32_0", + "CLK_FEED_CK_GCLK4", + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_NE4C0", + "CLK_FEED_R_CK_GCLK25", + "CLK_PMV_LOGIC_OUTS21_0", + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_SW2A0", + "CLK_FEED_NE2A0", + "CLK_FEED_CK_GCLK7", + "CLK_FEED_CK_BUFG_CASC24", + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_EE2A0", + "CLK_FEED_SE4BEG1", + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_WW2A2", + "CLK_FEED_CK_GCLK12", + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_PMV_IMUX4_0", + "CLK_FEED_CK_BUFG_CASC14", + "CLK_FEED_MONITOR_N", + "CLK_FEED_NE2A2", + "CLK_FEED_CK_GCLK9", + "CLK_FEED_SW4END1", + "CLK_PMV_IMUX42_0", + "CLK_FEED_EE4B2", + "CLK_FEED_EE4BEG3", + "CLK_PMV_BYP6_0", + "CLK_FEED_WW2END3", + "CLK_PMV_LOGIC_OUTS2_0", + "CLK_FEED_NE4BEG0", + "CLK_FEED_WW4END0", + "CLK_FEED_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_LH7", + "CLK_PMV_IMUX43_0", + "CLK_FEED_CK_GCLK28", + "CLK_FEED_NW4END3", + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_NW2A3", + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_EE4C1", + "CLK_FEED_WW4END3", + "CLK_PMV_FAN1_0", + "CLK_PMV_IMUX29_0", + "CLK_FEED_CK_GCLK13", + "CLK_FEED_NW2A1", + "CLK_FEED_CK_GCLK24", + "CLK_PMV_IMUX10_0", + "CLK_PMV_IMUX39_0", + "CLK_FEED_EL1BEG0", + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_NW4A0", + "CLK_FEED_WW4A2", + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_LH10", + "CLK_FEED_NW4A1", + "CLK_FEED_LH5", + "CLK_FEED_SE4C3", + "CLK_FEED_CK_BUFG_CASC4", + "CLK_FEED_NW2A0", + "CLK_FEED_WW4C0", + "CLK_FEED_LH6", + "CLK_PMV_LOGIC_OUTS6_0", + "CLK_PMV_IMUX13_0", + "CLK_FEED_SW4END0", + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_PMV_IMUX45_0", + "CLK_PMV_LOGIC_OUTS13_0", + "CLK_FEED_WW4B1", + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_WW2A0", + "CLK_FEED_CK_BUFG_CASC29", + "CLK_PMV_IMUX14_0", + "CLK_FEED_WW4A1", + "CLK_FEED_LH2", + "CLK_FEED_WW4C1", + "CLK_FEED_WW2END0", + "CLK_PMV2_A2", + "CLK_FEED_SE2A3", + "CLK_PMV_LOGIC_OUTS0_0", + "CLK_PMV_LOGIC_OUTS15_0", + "CLK_PMV_FAN2_0", + "CLK_FEED_SE2A1", + "CLK_FEED_NE4C2", + "CLK_FEED_EE2BEG0", + "CLK_PMV_IMUX3_0" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_CLK_PMV2_SVT.json b/kintex7/tile_type_CLK_PMV2_SVT.json new file mode 100644 index 0000000..eb8fa5a --- /dev/null +++ b/kintex7/tile_type_CLK_PMV2_SVT.json @@ -0,0 +1,360 @@ +{ + "tile_type": "CLK_PMV2_SVT", + "sites": [], + "wires": [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_SW4A1", + "CLK_PMV_BYP2_0", + "CLK_FEED_CK_GCLK31", + "CLK_FEED_CK_BUFG_CASC9", + "CLK_FEED_EL1BEG1", + "CLK_FEED_WW2END2", + "CLK_PMV_IMUX5_0", + "CLK_PMV_LOGIC_OUTS19_0", + "CLK_PMV_IMUX36_0", + "CLK_PMV_IMUX16_0", + "CLK_FEED_EE2BEG3", + "CLK_PMV_IMUX22_0", + "CLK_PMV_IMUX26_0", + "CLK_FEED_CK_BUFG_CASC16", + "CLK_FEED_CK_GCLK16", + "CLK_FEED_SE4BEG3", + "CLK_FEED_LH1", + "CLK_FEED_EE4C2", + "CLK_PMV_IMUX0_0", + "CLK_FEED_CK_GCLK17", + "CLK_FEED_NW4END2", + "CLK_FEED_CK_GCLK5", + "CLK_FEED_NE4BEG3", + "CLK_PMV_IMUX19_0", + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_GCLK14", + "CLK_PMV_IMUX2_0", + "CLK_FEED_EE4A2", + "CLK_PMV_IMUX27_0", + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_CK_GCLK21", + "CLK_FEED_EE2A2", + "CLK_FEED_EE4B3", + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_PMV_CTRL1_0", + "CLK_FEED_EE4B0", + "CLK_FEED_EE4A3", + "CLK_PMV_LOGIC_OUTS11_0", + "CLK_FEED_CK_GCLK8", + "CLK_PMV_IMUX33_0", + "CLK_FEED_NW4END0", + "CLK_PMV_IMUX15_0", + "CLK_FEED_R_CK_GCLK20", + "CLK_PMV_LOGIC_OUTS22_0", + "CLK_FEED_CK_BUFG_CASC21", + "CLK_FEED_WW4B0", + "CLK_FEED_CK_BUFG_CASC2", + "CLK_PMV_IMUX40_0", + "CLK_PMV_LOGIC_OUTS17_0", + "CLK_FEED_CK_BUFG_CASC20", + "CLK_PMV_LOGIC_OUTS9_0", + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_ER1BEG1", + "CLK_FEED_SE4BEG0", + "CLK_FEED_CK_BUFG_CASC26", + "CLK_FEED_WW4A0", + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_WW4B2", + "CLK_FEED_SW2A1", + "CLK_FEED_LH3", + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_PMV_IMUX38_0", + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_GCLK30", + "CLK_PMV_LOGIC_OUTS12_0", + "CLK_PMV_FAN3_0", + "CLK_FEED_WW4END2", + "CLK_FEED_CK_BUFG_CASC1", + "CLK_FEED_EL1BEG3", + "CLK_FEED_SE2A2", + "CLK_PMV_FAN5_0", + "CLK_PMV_LOGIC_OUTS3_0", + "CLK_FEED_NW4END1", + "CLK_FEED_LH8", + "CLK_FEED_LH4", + "CLK_FEED_CK_GCLK29", + "CLK_FEED_CK_GCLK14", + "CLK_FEED_SE4C0", + "CLK_FEED_LH9", + "CLK_FEED_WR1END3", + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_EE4BEG2", + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_CK_GCLK19", + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_CK_GCLK25", + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_WW4END1", + "CLK_PMV_IMUX8_0", + "CLK_FEED_CK_GCLK23", + "CLK_FEED_EE4B1", + "CLK_PMV2_O", + "CLK_FEED_CK_BUFG_CASC10", + "CLK_FEED_EE2BEG1", + "CLK_PMV_LOGIC_OUTS20_0", + "CLK_PMV_FAN4_0", + "CLK_FEED_R_CK_GCLK9", + "CLK_PMV2_A1", + "CLK_FEED_SW4A3", + "CLK_PMV_LOGIC_OUTS18_0", + "CLK_FEED_SE4C1", + "CLK_FEED_NW4A2", + "CLK_FEED_CK_GCLK15", + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_PMV_BYP7_0", + "CLK_FEED_CK_GCLK20", + "CLK_FEED_CK_BUFG_CASC5", + "CLK_PMV_IMUX18_0", + "CLK_FEED_LH11", + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_PMV_BYP5_0", + "CLK_PMV_IMUX25_0", + "CLK_FEED_NE2A1", + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_CK_BUFG_CASC13", + "CLK_FEED_CK_BUFG_CASC18", + "CLK_FEED_CK_GCLK11", + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_CK_GCLK2", + "CLK_PMV_LOGIC_OUTS16_0", + "CLK_PMV_IMUX24_0", + "CLK_FEED_CK_BUFG_CASC11", + "CLK_FEED_CK_GCLK3", + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_CK_BUFG_CASC15", + "CLK_PMV_FAN0_0", + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_PMV2_ODIV4", + "CLK_FEED_CK_BUFG_CASC23", + "CLK_PMV_IMUX44_0", + "CLK_FEED_CK_BUFG_CASC28", + "CLK_PMV_BYP4_0", + "CLK_FEED_MONITOR_P", + "CLK_FEED_WW4A3", + "CLK_FEED_R_CK_GCLK26", + "CLK_PMV_LOGIC_OUTS5_0", + "CLK_FEED_CK_GCLK27", + "CLK_PMV_IMUX23_0", + "CLK_FEED_R_CK_GCLK23", + "CLK_PMV_LOGIC_OUTS1_0", + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_NE4C1", + "CLK_FEED_CK_BUFG_CASC25", + "CLK_FEED_CK_BUFG_CASC6", + "CLK_PMV_IMUX1_0", + "CLK_PMV_IMUX7_0", + "CLK_FEED_CK_GCLK1", + "CLK_FEED_NE2A3", + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_ER1BEG3", + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_CK_BUFG_CASC8", + "CLK_PMV_FAN7_0", + "CLK_PMV_BYP0_0", + "CLK_FEED_CK_BUFG_CASC30", + "CLK_FEED_CK_GCLK22", + "CLK_PMV_CLK0_0", + "CLK_PMV2_EN", + "CLK_PMV_LOGIC_OUTS7_0", + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_WL1END1", + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_PMV_BYP1_0", + "CLK_FEED_EE2BEG2", + "CLK_PMV_CTRL0_0", + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_EE4C3", + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_PMV_LOGIC_OUTS8_0", + "CLK_PMV_IMUX47_0", + "CLK_FEED_CK_BUFG_CASC3", + "CLK_FEED_SE4C2", + "CLK_FEED_WL1END0", + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_CK_BUFG_CASC17", + "CLK_FEED_EE4BEG0", + "CLK_FEED_CK_BUFG_CASC22", + "CLK_FEED_WW4C2", + "CLK_FEED_EE2A1", + "CLK_PMV_IMUX31_0", + "CLK_FEED_EE4A0", + "CLK_PMV_IMUX37_0", + "CLK_FEED_WR1END0", + "CLK_PMV_IMUX20_0", + "CLK_FEED_CK_GCLK6", + "CLK_FEED_WR1END1", + "CLK_FEED_NE4BEG1", + "CLK_PMV2_ODIV2", + "CLK_FEED_CK_BUFG_CASC0", + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_WL1END3", + "CLK_FEED_CK_GCLK10", + "CLK_FEED_CK_GCLK0", + "CLK_FEED_CK_GCLK30", + "CLK_FEED_EE4C0", + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_PMV_IMUX46_0", + "CLK_PMV_IMUX30_0", + "CLK_FEED_SE4BEG2", + "CLK_PMV_BYP3_0", + "CLK_PMV_LOGIC_OUTS14_0", + "CLK_PMV_IMUX17_0", + "CLK_PMV_LOGIC_OUTS4_0", + "CLK_FEED_EE2A3", + "CLK_FEED_WW4B3", + "CLK_FEED_EE4BEG1", + "CLK_FEED_CK_BUFG_CASC7", + "CLK_PMV_IMUX9_0", + "CLK_PMV_LOGIC_OUTS23_0", + "CLK_PMV2_A0", + "CLK_FEED_EE4A1", + "CLK_FEED_R_CK_GCLK12", + "CLK_PMV_IMUX28_0", + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_GCLK4", + "CLK_PMV_IMUX12_0", + "CLK_FEED_NE4C3", + "CLK_FEED_NW2A2", + "CLK_FEED_ER1BEG2", + "CLK_PMV_IMUX41_0", + "CLK_FEED_SW4END2", + "CLK_FEED_WW2A3", + "CLK_FEED_LH12", + "CLK_FEED_SW2A3", + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_PMV_IMUX35_0", + "CLK_FEED_SW4A2", + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_SW4END3", + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_NE4BEG2", + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_EL1BEG2", + "CLK_PMV_CLK1_0", + "CLK_FEED_WW4C3", + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_WL1END2", + "CLK_FEED_CK_GCLK26", + "CLK_FEED_ER1BEG0", + "CLK_FEED_SW2A2", + "CLK_FEED_WW2END1", + "CLK_PMV_IMUX11_0", + "CLK_FEED_WR1END2", + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_SW4A0", + "CLK_FEED_SE2A0", + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_GCLK10", + "CLK_PMV_IMUX34_0", + "CLK_PMV_IMUX21_0", + "CLK_FEED_CK_BUFG_CASC31", + "CLK_FEED_NW4A3", + "CLK_FEED_WW2A1", + "CLK_PMV_LOGIC_OUTS10_0", + "CLK_PMV_IMUX6_0", + "CLK_FEED_CK_BUFG_CASC19", + "CLK_FEED_CK_BUFG_CASC27", + "CLK_FEED_CK_GCLK18", + "CLK_PMV_FAN6_0", + "CLK_PMV_IMUX32_0", + "CLK_FEED_CK_GCLK4", + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_NE4C0", + "CLK_FEED_R_CK_GCLK25", + "CLK_PMV_LOGIC_OUTS21_0", + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_SW2A0", + "CLK_FEED_NE2A0", + "CLK_FEED_CK_GCLK7", + "CLK_FEED_CK_BUFG_CASC24", + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_EE2A0", + "CLK_FEED_SE4BEG1", + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_WW2A2", + "CLK_FEED_CK_GCLK12", + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_PMV_IMUX4_0", + "CLK_FEED_CK_BUFG_CASC14", + "CLK_FEED_MONITOR_N", + "CLK_FEED_NE2A2", + "CLK_FEED_CK_GCLK9", + "CLK_FEED_SW4END1", + "CLK_PMV_IMUX42_0", + "CLK_FEED_EE4B2", + "CLK_FEED_EE4BEG3", + "CLK_PMV_BYP6_0", + "CLK_FEED_WW2END3", + "CLK_PMV_LOGIC_OUTS2_0", + "CLK_FEED_NE4BEG0", + "CLK_FEED_WW4END0", + "CLK_FEED_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_LH7", + "CLK_PMV_IMUX43_0", + "CLK_FEED_CK_GCLK28", + "CLK_FEED_NW4END3", + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_NW2A3", + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_EE4C1", + "CLK_FEED_WW4END3", + "CLK_PMV_FAN1_0", + "CLK_PMV_IMUX29_0", + "CLK_FEED_CK_GCLK13", + "CLK_FEED_NW2A1", + "CLK_FEED_CK_GCLK24", + "CLK_PMV_IMUX10_0", + "CLK_PMV_IMUX39_0", + "CLK_FEED_EL1BEG0", + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_NW4A0", + "CLK_FEED_WW4A2", + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_LH10", + "CLK_FEED_NW4A1", + "CLK_FEED_LH5", + "CLK_FEED_SE4C3", + "CLK_FEED_CK_BUFG_CASC4", + "CLK_FEED_NW2A0", + "CLK_FEED_WW4C0", + "CLK_FEED_LH6", + "CLK_PMV_LOGIC_OUTS6_0", + "CLK_PMV_IMUX13_0", + "CLK_FEED_SW4END0", + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_PMV_IMUX45_0", + "CLK_PMV_LOGIC_OUTS13_0", + "CLK_FEED_WW4B1", + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_WW2A0", + "CLK_FEED_CK_BUFG_CASC29", + "CLK_PMV_IMUX14_0", + "CLK_FEED_WW4A1", + "CLK_FEED_LH2", + "CLK_FEED_WW4C1", + "CLK_FEED_WW2END0", + "CLK_PMV2_A2", + "CLK_FEED_SE2A3", + "CLK_PMV_LOGIC_OUTS0_0", + "CLK_PMV_LOGIC_OUTS15_0", + "CLK_PMV_FAN2_0", + "CLK_FEED_SE2A1", + "CLK_FEED_NE4C2", + "CLK_FEED_EE2BEG0", + "CLK_PMV_IMUX3_0" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_CLK_PMVIOB.json b/kintex7/tile_type_CLK_PMVIOB.json new file mode 100644 index 0000000..2db033a --- /dev/null +++ b/kintex7/tile_type_CLK_PMVIOB.json @@ -0,0 +1,359 @@ +{ + "tile_type": "CLK_PMVIOB", + "sites": [], + "wires": [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_SW4A1", + "CLK_PMV_BYP2_0", + "CLK_FEED_CK_GCLK31", + "CLK_FEED_CK_BUFG_CASC9", + "CLK_FEED_EL1BEG1", + "CLK_FEED_WW2END2", + "CLK_PMV_IMUX5_0", + "CLK_PMV_LOGIC_OUTS19_0", + "CLK_PMV_IMUX36_0", + "CLK_PMV_IMUX16_0", + "CLK_FEED_EE2BEG3", + "CLK_PMV_IMUX22_0", + "CLK_PMV_IMUX26_0", + "CLK_FEED_CK_BUFG_CASC16", + "CLK_FEED_CK_GCLK16", + "CLK_FEED_SE4BEG3", + "CLK_FEED_LH1", + "CLK_FEED_EE4C2", + "CLK_PMV_IMUX0_0", + "CLK_FEED_CK_GCLK17", + "CLK_FEED_NW4END2", + "CLK_FEED_CK_GCLK5", + "CLK_FEED_NE4BEG3", + "CLK_PMV_IMUX19_0", + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_GCLK14", + "CLK_PMV_IMUX2_0", + "CLK_FEED_EE4A2", + "CLK_PMV_IMUX27_0", + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_CK_GCLK21", + "CLK_FEED_EE2A2", + "CLK_FEED_EE4B3", + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_PMV_CTRL1_0", + "CLK_FEED_EE4B0", + "CLK_FEED_EE4A3", + "CLK_PMV_LOGIC_OUTS11_0", + "CLK_FEED_CK_GCLK8", + "CLK_PMV_IMUX33_0", + "CLK_FEED_NW4END0", + "CLK_PMV_IMUX15_0", + "CLK_FEED_R_CK_GCLK20", + "CLK_PMV_LOGIC_OUTS22_0", + "CLK_FEED_CK_BUFG_CASC21", + "CLK_FEED_WW4B0", + "CLK_FEED_CK_BUFG_CASC2", + "CLK_PMV_IMUX40_0", + "CLK_PMV_LOGIC_OUTS17_0", + "CLK_FEED_CK_BUFG_CASC20", + "CLK_PMV_LOGIC_OUTS9_0", + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_ER1BEG1", + "CLK_FEED_SE4BEG0", + "CLK_FEED_CK_BUFG_CASC26", + "CLK_FEED_WW4A0", + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_WW4B2", + "CLK_FEED_SW2A1", + "CLK_FEED_LH3", + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_PMV_IMUX38_0", + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_GCLK30", + "CLK_PMV_LOGIC_OUTS12_0", + "CLK_PMV_FAN3_0", + "CLK_FEED_WW4END2", + "CLK_FEED_CK_BUFG_CASC1", + "CLK_FEED_EL1BEG3", + "CLK_FEED_SE2A2", + "CLK_PMV_FAN5_0", + "CLK_PMV_LOGIC_OUTS3_0", + "CLK_FEED_NW4END1", + "CLK_FEED_LH8", + "CLK_FEED_LH4", + "CLK_FEED_CK_GCLK29", + "CLK_FEED_CK_GCLK14", + "CLK_FEED_SE4C0", + "CLK_FEED_LH9", + "CLK_FEED_WR1END3", + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_EE4BEG2", + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_CK_GCLK19", + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_CK_GCLK25", + "CLK_PMVIOB_ODIV2", + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_WW4END1", + "CLK_PMV_IMUX8_0", + "CLK_FEED_CK_GCLK23", + "CLK_FEED_EE4B1", + "CLK_FEED_CK_BUFG_CASC10", + "CLK_FEED_EE2BEG1", + "CLK_PMV_LOGIC_OUTS20_0", + "CLK_PMV_FAN4_0", + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_SW4A3", + "CLK_PMV_LOGIC_OUTS18_0", + "CLK_FEED_SE4C1", + "CLK_FEED_NW4A2", + "CLK_FEED_CK_GCLK15", + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_PMV_BYP7_0", + "CLK_FEED_CK_GCLK20", + "CLK_FEED_CK_BUFG_CASC5", + "CLK_PMV_IMUX18_0", + "CLK_FEED_LH11", + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_PMV_BYP5_0", + "CLK_PMV_IMUX25_0", + "CLK_FEED_NE2A1", + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_CK_BUFG_CASC13", + "CLK_FEED_CK_BUFG_CASC18", + "CLK_FEED_CK_GCLK11", + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_CK_GCLK2", + "CLK_PMV_LOGIC_OUTS16_0", + "CLK_PMV_IMUX24_0", + "CLK_FEED_CK_BUFG_CASC11", + "CLK_FEED_CK_GCLK3", + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_CK_BUFG_CASC15", + "CLK_PMV_FAN0_0", + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_CK_BUFG_CASC23", + "CLK_PMV_IMUX44_0", + "CLK_FEED_CK_BUFG_CASC28", + "CLK_PMV_BYP4_0", + "CLK_FEED_MONITOR_P", + "CLK_FEED_WW4A3", + "CLK_FEED_R_CK_GCLK26", + "CLK_PMV_LOGIC_OUTS5_0", + "CLK_FEED_CK_GCLK27", + "CLK_PMV_IMUX23_0", + "CLK_FEED_R_CK_GCLK23", + "CLK_PMV_LOGIC_OUTS1_0", + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_NE4C1", + "CLK_FEED_CK_BUFG_CASC25", + "CLK_FEED_CK_BUFG_CASC6", + "CLK_PMV_IMUX1_0", + "CLK_PMV_IMUX7_0", + "CLK_PMVIOB_A0", + "CLK_FEED_CK_GCLK1", + "CLK_FEED_NE2A3", + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_ER1BEG3", + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_CK_BUFG_CASC8", + "CLK_PMV_FAN7_0", + "CLK_PMV_CLK0_0", + "CLK_FEED_CK_BUFG_CASC30", + "CLK_FEED_CK_GCLK22", + "CLK_PMV_BYP0_0", + "CLK_PMV_LOGIC_OUTS7_0", + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_WL1END1", + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_PMV_BYP1_0", + "CLK_FEED_EE2BEG2", + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_PMV_CTRL0_0", + "CLK_FEED_EE4C3", + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_PMV_LOGIC_OUTS8_0", + "CLK_PMV_IMUX47_0", + "CLK_FEED_CK_BUFG_CASC3", + "CLK_FEED_SE4C2", + "CLK_FEED_WL1END0", + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_CK_BUFG_CASC17", + "CLK_FEED_EE4BEG0", + "CLK_FEED_CK_BUFG_CASC22", + "CLK_FEED_WW4C2", + "CLK_FEED_EE2A1", + "CLK_PMV_IMUX31_0", + "CLK_FEED_EE4A0", + "CLK_PMV_IMUX37_0", + "CLK_FEED_WR1END0", + "CLK_PMV_IMUX20_0", + "CLK_FEED_CK_GCLK6", + "CLK_FEED_WR1END1", + "CLK_FEED_NE4BEG1", + "CLK_FEED_CK_BUFG_CASC0", + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_WL1END3", + "CLK_FEED_CK_GCLK10", + "CLK_FEED_CK_GCLK0", + "CLK_FEED_CK_GCLK30", + "CLK_FEED_EE4C0", + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_PMV_IMUX46_0", + "CLK_PMV_IMUX30_0", + "CLK_FEED_SE4BEG2", + "CLK_PMV_BYP3_0", + "CLK_PMV_LOGIC_OUTS14_0", + "CLK_PMV_IMUX17_0", + "CLK_PMV_LOGIC_OUTS4_0", + "CLK_FEED_EE2A3", + "CLK_FEED_WW4B3", + "CLK_FEED_EE4BEG1", + "CLK_FEED_CK_BUFG_CASC7", + "CLK_PMV_IMUX9_0", + "CLK_PMV_LOGIC_OUTS23_0", + "CLK_FEED_EE4A1", + "CLK_FEED_R_CK_GCLK12", + "CLK_PMV_IMUX28_0", + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_GCLK4", + "CLK_PMV_IMUX12_0", + "CLK_FEED_NE4C3", + "CLK_FEED_NW2A2", + "CLK_FEED_ER1BEG2", + "CLK_PMV_IMUX41_0", + "CLK_FEED_SW4END2", + "CLK_FEED_WW2A3", + "CLK_FEED_LH12", + "CLK_FEED_SW2A3", + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_PMV_IMUX35_0", + "CLK_FEED_SW4A2", + "CLK_PMVIOB_A1", + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_SW4END3", + "CLK_PMVIOB_O", + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_NE4BEG2", + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_EL1BEG2", + "CLK_PMV_CLK1_0", + "CLK_FEED_WW4C3", + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_WL1END2", + "CLK_FEED_CK_GCLK26", + "CLK_FEED_ER1BEG0", + "CLK_FEED_SW2A2", + "CLK_FEED_WW2END1", + "CLK_PMV_IMUX11_0", + "CLK_FEED_WR1END2", + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_SW4A0", + "CLK_FEED_SE2A0", + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_GCLK10", + "CLK_PMV_IMUX34_0", + "CLK_PMV_IMUX21_0", + "CLK_FEED_CK_BUFG_CASC31", + "CLK_FEED_NW4A3", + "CLK_FEED_WW2A1", + "CLK_PMV_LOGIC_OUTS10_0", + "CLK_PMV_IMUX6_0", + "CLK_FEED_CK_BUFG_CASC19", + "CLK_FEED_CK_BUFG_CASC27", + "CLK_FEED_CK_GCLK18", + "CLK_PMV_FAN6_0", + "CLK_PMV_IMUX32_0", + "CLK_FEED_CK_GCLK4", + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_NE4C0", + "CLK_FEED_R_CK_GCLK25", + "CLK_PMV_LOGIC_OUTS21_0", + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_SW2A0", + "CLK_FEED_NE2A0", + "CLK_FEED_CK_GCLK7", + "CLK_FEED_CK_BUFG_CASC24", + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_EE2A0", + "CLK_FEED_SE4BEG1", + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_WW2A2", + "CLK_FEED_CK_GCLK12", + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_PMV_IMUX4_0", + "CLK_FEED_CK_BUFG_CASC14", + "CLK_FEED_MONITOR_N", + "CLK_FEED_NE2A2", + "CLK_FEED_CK_GCLK9", + "CLK_FEED_SW4END1", + "CLK_PMV_IMUX42_0", + "CLK_FEED_EE4B2", + "CLK_FEED_EE4BEG3", + "CLK_PMV_BYP6_0", + "CLK_FEED_WW2END3", + "CLK_PMV_LOGIC_OUTS2_0", + "CLK_FEED_NE4BEG0", + "CLK_FEED_WW4END0", + "CLK_FEED_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_LH7", + "CLK_PMV_IMUX43_0", + "CLK_FEED_CK_GCLK28", + "CLK_FEED_NW4END3", + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_NW2A3", + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_EE4C1", + "CLK_FEED_WW4END3", + "CLK_PMV_FAN1_0", + "CLK_PMV_IMUX29_0", + "CLK_FEED_CK_GCLK13", + "CLK_FEED_NW2A1", + "CLK_FEED_CK_GCLK24", + "CLK_PMVIOB_ODIV4", + "CLK_PMV_IMUX10_0", + "CLK_PMV_IMUX39_0", + "CLK_FEED_EL1BEG0", + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_NW4A0", + "CLK_FEED_WW4A2", + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_LH10", + "CLK_FEED_NW4A1", + "CLK_FEED_LH5", + "CLK_FEED_SE4C3", + "CLK_FEED_CK_BUFG_CASC4", + "CLK_FEED_NW2A0", + "CLK_FEED_WW4C0", + "CLK_FEED_LH6", + "CLK_PMV_LOGIC_OUTS6_0", + "CLK_PMV_IMUX13_0", + "CLK_FEED_SW4END0", + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_PMV_IMUX45_0", + "CLK_PMV_LOGIC_OUTS13_0", + "CLK_FEED_WW4B1", + "CLK_PMVIOB_EN", + "CLK_FEED_WW2A0", + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_CK_BUFG_CASC29", + "CLK_PMV_IMUX14_0", + "CLK_FEED_WW4A1", + "CLK_FEED_LH2", + "CLK_FEED_WW4C1", + "CLK_FEED_WW2END0", + "CLK_FEED_SE2A3", + "CLK_PMV_LOGIC_OUTS0_0", + "CLK_PMV_LOGIC_OUTS15_0", + "CLK_PMV_FAN2_0", + "CLK_FEED_SE2A1", + "CLK_FEED_NE4C2", + "CLK_FEED_EE2BEG0", + "CLK_PMV_IMUX3_0" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_CLK_TERM.json b/kintex7/tile_type_CLK_TERM.json new file mode 100644 index 0000000..236abac --- /dev/null +++ b/kintex7/tile_type_CLK_TERM.json @@ -0,0 +1,71 @@ +{ + "tile_type": "CLK_TERM", + "sites": [], + "wires": [ + "CLK_TERM_R_GCLK6", + "CLK_TERM_R_GCLK27", + "CLK_TERM_R_GCLK19", + "CLK_TERM_R_GCLK16", + "CLK_TERM_R_GCLK24", + "CLK_TERM_GCLK4", + "CLK_TERM_R_GCLK10", + "CLK_TERM_GCLK28", + "CLK_TERM_R_GCLK9", + "CLK_TERM_GCLK1", + "CLK_TERM_GCLK24", + "CLK_TERM_R_GCLK7", + "CLK_TERM_GCLK5", + "CLK_TERM_R_GCLK5", + "CLK_TERM_GCLK2", + "CLK_TERM_GCLK9", + "CLK_TERM_GCLK6", + "CLK_TERM_GCLK0", + "CLK_TERM_GCLK3", + "CLK_TERM_GCLK17", + "CLK_TERM_R_GCLK11", + "CLK_TERM_R_GCLK12", + "CLK_TERM_GCLK16", + "CLK_TERM_GCLK23", + "CLK_TERM_GCLK25", + "CLK_TERM_GCLK19", + "CLK_TERM_R_GCLK15", + "CLK_TERM_R_GCLK25", + "CLK_TERM_GCLK26", + "CLK_TERM_R_GCLK23", + "CLK_TERM_GCLK18", + "CLK_TERM_R_GCLK8", + "CLK_TERM_GCLK15", + "CLK_TERM_R_GCLK2", + "CLK_TERM_R_GCLK14", + "CLK_TERM_R_GCLK0", + "CLK_TERM_R_GCLK29", + "CLK_TERM_R_GCLK17", + "CLK_TERM_R_GCLK4", + "CLK_TERM_R_GCLK30", + "CLK_TERM_R_GCLK18", + "CLK_TERM_GCLK7", + "CLK_TERM_GCLK29", + "CLK_TERM_R_GCLK31", + "CLK_TERM_GCLK14", + "CLK_TERM_GCLK11", + "CLK_TERM_GCLK31", + "CLK_TERM_R_GCLK21", + "CLK_TERM_GCLK21", + "CLK_TERM_R_GCLK1", + "CLK_TERM_R_GCLK3", + "CLK_TERM_R_GCLK20", + "CLK_TERM_GCLK8", + "CLK_TERM_R_GCLK26", + "CLK_TERM_GCLK12", + "CLK_TERM_GCLK22", + "CLK_TERM_GCLK30", + "CLK_TERM_R_GCLK13", + "CLK_TERM_GCLK20", + "CLK_TERM_R_GCLK22", + "CLK_TERM_R_GCLK28", + "CLK_TERM_GCLK10", + "CLK_TERM_GCLK27", + "CLK_TERM_GCLK13" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_CMT_FIFO_L.json b/kintex7/tile_type_CMT_FIFO_L.json new file mode 100644 index 0000000..81bec92 --- /dev/null +++ b/kintex7/tile_type_CMT_FIFO_L.json @@ -0,0 +1,5261 @@ +{ + "tile_type": "CMT_FIFO_L", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "OUT_FIFO", + "type": "OUT_FIFO", + "site_pins": { + "WREN": "CMT_OUT_FIFO_WREN", + "SCANOUT0": "CMT_OUT_FIFO_SCANOUT0", + "D67": "CMT_OUT_FIFO_D67", + "D15": "CMT_OUT_FIFO_D15", + "WRCLK": "CMT_OUT_FIFO_WRCLK", + "Q00": "CMT_OUT_FIFO_Q00", + "D11": "CMT_OUT_FIFO_D11", + "ALMOSTFULL": "CMT_OUT_FIFO_ALMOSTFULL", + "Q33": "CMT_OUT_FIFO_Q33", + "D72": "CMT_OUT_FIFO_D72", + "Q01": "CMT_OUT_FIFO_Q01", + "Q83": "CMT_OUT_FIFO_Q83", + "D33": "CMT_OUT_FIFO_D33", + "Q12": "CMT_OUT_FIFO_Q12", + "D74": "CMT_OUT_FIFO_D74", + "Q56": "CMT_OUT_FIFO_Q56", + "D37": "CMT_OUT_FIFO_D37", + "D35": "CMT_OUT_FIFO_D35", + "Q92": "CMT_OUT_FIFO_Q92", + "Q91": "CMT_OUT_FIFO_Q91", + "Q52": "CMT_OUT_FIFO_Q52", + "Q20": "CMT_OUT_FIFO_Q20", + "D52": "CMT_OUT_FIFO_D52", + "Q81": "CMT_OUT_FIFO_Q81", + "RDEN": "CMT_OUT_FIFO_RDEN", + "Q64": "CMT_OUT_FIFO_Q64", + "Q61": "CMT_OUT_FIFO_Q61", + "D87": "CMT_OUT_FIFO_D87", + "D86": "CMT_OUT_FIFO_D86", + "D94": "CMT_OUT_FIFO_D94", + "D04": "CMT_OUT_FIFO_D04", + "D62": "CMT_OUT_FIFO_D62", + "D36": "CMT_OUT_FIFO_D36", + "D25": "CMT_OUT_FIFO_D25", + "Q41": "CMT_OUT_FIFO_Q41", + "D60": "CMT_OUT_FIFO_D60", + "Q43": "CMT_OUT_FIFO_Q43", + "SCANENB": "CMT_OUT_FIFO_SCANENB", + "D45": "CMT_OUT_FIFO_D45", + "Q54": "CMT_OUT_FIFO_Q54", + "FULL": "CMT_OUT_FIFO_FULL", + "D43": "CMT_OUT_FIFO_D43", + "Q67": "CMT_OUT_FIFO_Q67", + "D51": "CMT_OUT_FIFO_D51", + "D23": "CMT_OUT_FIFO_D23", + "SCANIN0": "CMT_OUT_FIFO_SCANIN0", + "D92": "CMT_OUT_FIFO_D92", + "D02": "CMT_OUT_FIFO_D02", + "D83": "CMT_OUT_FIFO_D83", + "Q57": "CMT_OUT_FIFO_Q57", + "D80": "CMT_OUT_FIFO_D80", + "TESTREADDISB": "CMT_OUT_FIFO_TESTREADDISB", + "Q51": "CMT_OUT_FIFO_Q51", + "D85": "CMT_OUT_FIFO_D85", + "D82": "CMT_OUT_FIFO_D82", + "Q21": "CMT_OUT_FIFO_Q21", + "SCANOUT1": "CMT_OUT_FIFO_SCANOUT1", + "D06": "CMT_OUT_FIFO_D06", + "Q90": "CMT_OUT_FIFO_Q90", + "D31": "CMT_OUT_FIFO_D31", + "D47": "CMT_OUT_FIFO_D47", + "Q66": "CMT_OUT_FIFO_Q66", + "D41": "CMT_OUT_FIFO_D41", + "D95": "CMT_OUT_FIFO_D95", + "D70": "CMT_OUT_FIFO_D70", + "D21": "CMT_OUT_FIFO_D21", + "TESTMODEB": "CMT_OUT_FIFO_TESTMODEB", + "D66": "CMT_OUT_FIFO_D66", + "Q71": "CMT_OUT_FIFO_Q71", + "Q50": "CMT_OUT_FIFO_Q50", + "Q42": "CMT_OUT_FIFO_Q42", + "SCANOUT2": "CMT_OUT_FIFO_SCANOUT2", + "Q80": "CMT_OUT_FIFO_Q80", + "Q10": "CMT_OUT_FIFO_Q10", + "Q62": "CMT_OUT_FIFO_Q62", + "D32": "CMT_OUT_FIFO_D32", + "Q32": "CMT_OUT_FIFO_Q32", + "D97": "CMT_OUT_FIFO_D97", + "Q23": "CMT_OUT_FIFO_Q23", + "D40": "CMT_OUT_FIFO_D40", + "D96": "CMT_OUT_FIFO_D96", + "D16": "CMT_OUT_FIFO_D16", + "Q11": "CMT_OUT_FIFO_Q11", + "D20": "CMT_OUT_FIFO_D20", + "D13": "CMT_OUT_FIFO_D13", + "Q40": "CMT_OUT_FIFO_Q40", + "D10": "CMT_OUT_FIFO_D10", + "Q31": "CMT_OUT_FIFO_Q31", + "D76": "CMT_OUT_FIFO_D76", + "Q93": "CMT_OUT_FIFO_Q93", + "Q65": "CMT_OUT_FIFO_Q65", + "SCANIN3": "CMT_OUT_FIFO_SCANIN3", + "D90": "CMT_OUT_FIFO_D90", + "Q63": "CMT_OUT_FIFO_Q63", + "D93": "CMT_OUT_FIFO_D93", + "D26": "CMT_OUT_FIFO_D26", + "D44": "CMT_OUT_FIFO_D44", + "Q72": "CMT_OUT_FIFO_Q72", + "Q60": "CMT_OUT_FIFO_Q60", + "D73": "CMT_OUT_FIFO_D73", + "D14": "CMT_OUT_FIFO_D14", + "D65": "CMT_OUT_FIFO_D65", + "D64": "CMT_OUT_FIFO_D64", + "D61": "CMT_OUT_FIFO_D61", + "D57": "CMT_OUT_FIFO_D57", + "D75": "CMT_OUT_FIFO_D75", + "Q30": "CMT_OUT_FIFO_Q30", + "Q13": "CMT_OUT_FIFO_Q13", + "RESET": "CMT_OUT_FIFO_RESET", + "D84": "CMT_OUT_FIFO_D84", + "D05": "CMT_OUT_FIFO_D05", + "D03": "CMT_OUT_FIFO_D03", + "D91": "CMT_OUT_FIFO_D91", + "Q02": "CMT_OUT_FIFO_Q02", + "D30": "CMT_OUT_FIFO_D30", + "Q82": "CMT_OUT_FIFO_Q82", + "SCANIN1": "CMT_OUT_FIFO_SCANIN1", + "SCANOUT3": "CMT_OUT_FIFO_SCANOUT3", + "D17": "CMT_OUT_FIFO_D17", + "D12": "CMT_OUT_FIFO_D12", + "Q70": "CMT_OUT_FIFO_Q70", + "D55": "CMT_OUT_FIFO_D55", + "D24": "CMT_OUT_FIFO_D24", + "D54": "CMT_OUT_FIFO_D54", + "Q73": "CMT_OUT_FIFO_Q73", + "D07": "CMT_OUT_FIFO_D07", + "D34": "CMT_OUT_FIFO_D34", + "Q55": "CMT_OUT_FIFO_Q55", + "D63": "CMT_OUT_FIFO_D63", + "TESTWRITEDISB": "CMT_OUT_FIFO_TESTWRITEDISB", + "RDCLK": "CMT_OUT_FIFO_RDCLK", + "Q53": "CMT_OUT_FIFO_Q53", + "D81": "CMT_OUT_FIFO_D81", + "D42": "CMT_OUT_FIFO_D42", + "D22": "CMT_OUT_FIFO_D22", + "D53": "CMT_OUT_FIFO_D53", + "D71": "CMT_OUT_FIFO_D71", + "D56": "CMT_OUT_FIFO_D56", + "ALMOSTEMPTY": "CMT_OUT_FIFO_ALMOSTEMPTY", + "Q03": "CMT_OUT_FIFO_Q03", + "D46": "CMT_OUT_FIFO_D46", + "D50": "CMT_OUT_FIFO_D50", + "Q22": "CMT_OUT_FIFO_Q22", + "D01": "CMT_OUT_FIFO_D01", + "D00": "CMT_OUT_FIFO_D00", + "EMPTY": "CMT_OUT_FIFO_EMPTY", + "D77": "CMT_OUT_FIFO_D77", + "SCANIN2": "CMT_OUT_FIFO_SCANIN2", + "D27": "CMT_OUT_FIFO_D27" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IN_FIFO", + "type": "IN_FIFO", + "site_pins": { + "WREN": "CMT_IN_FIFO_WREN", + "SCANOUT0": "CMT_IN_FIFO_SCANOUT0", + "D67": "CMT_IN_FIFO_D67", + "Q34": "CMT_IN_FIFO_Q34", + "Q86": "CMT_IN_FIFO_Q86", + "Q00": "CMT_IN_FIFO_Q00", + "Q84": "CMT_IN_FIFO_Q84", + "Q77": "CMT_IN_FIFO_Q77", + "D11": "CMT_IN_FIFO_D11", + "ALMOSTFULL": "CMT_IN_FIFO_ALMOSTFULL", + "Q33": "CMT_IN_FIFO_Q33", + "D72": "CMT_IN_FIFO_D72", + "Q01": "CMT_IN_FIFO_Q01", + "Q95": "CMT_IN_FIFO_Q95", + "Q07": "CMT_IN_FIFO_Q07", + "Q06": "CMT_IN_FIFO_Q06", + "D33": "CMT_IN_FIFO_D33", + "Q12": "CMT_IN_FIFO_Q12", + "Q56": "CMT_IN_FIFO_Q56", + "Q92": "CMT_IN_FIFO_Q92", + "Q91": "CMT_IN_FIFO_Q91", + "Q52": "CMT_IN_FIFO_Q52", + "Q20": "CMT_IN_FIFO_Q20", + "WRCLK": "CMT_IN_FIFO_WRCLK", + "Q81": "CMT_IN_FIFO_Q81", + "RDEN": "CMT_IN_FIFO_RDEN", + "Q64": "CMT_IN_FIFO_Q64", + "Q61": "CMT_IN_FIFO_Q61", + "SCANIN1": "CMT_IN_FIFO_SCANIN1", + "D02": "CMT_IN_FIFO_D02", + "D53": "CMT_IN_FIFO_D53", + "D62": "CMT_IN_FIFO_D62", + "Q94": "CMT_IN_FIFO_Q94", + "Q46": "CMT_IN_FIFO_Q46", + "Q41": "CMT_IN_FIFO_Q41", + "D60": "CMT_IN_FIFO_D60", + "Q43": "CMT_IN_FIFO_Q43", + "Q75": "CMT_IN_FIFO_Q75", + "SCANENB": "CMT_IN_FIFO_SCANENB", + "Q54": "CMT_IN_FIFO_Q54", + "FULL": "CMT_IN_FIFO_FULL", + "D43": "CMT_IN_FIFO_D43", + "Q67": "CMT_IN_FIFO_Q67", + "D51": "CMT_IN_FIFO_D51", + "D23": "CMT_IN_FIFO_D23", + "SCANIN0": "CMT_IN_FIFO_SCANIN0", + "D92": "CMT_IN_FIFO_D92", + "Q45": "CMT_IN_FIFO_Q45", + "D01": "CMT_IN_FIFO_D01", + "D83": "CMT_IN_FIFO_D83", + "Q25": "CMT_IN_FIFO_Q25", + "Q05": "CMT_IN_FIFO_Q05", + "Q57": "CMT_IN_FIFO_Q57", + "Q24": "CMT_IN_FIFO_Q24", + "D80": "CMT_IN_FIFO_D80", + "Q51": "CMT_IN_FIFO_Q51", + "D82": "CMT_IN_FIFO_D82", + "Q21": "CMT_IN_FIFO_Q21", + "SCANOUT1": "CMT_IN_FIFO_SCANOUT1", + "Q27": "CMT_IN_FIFO_Q27", + "Q17": "CMT_IN_FIFO_Q17", + "Q47": "CMT_IN_FIFO_Q47", + "Q90": "CMT_IN_FIFO_Q90", + "D31": "CMT_IN_FIFO_D31", + "Q66": "CMT_IN_FIFO_Q66", + "D41": "CMT_IN_FIFO_D41", + "D70": "CMT_IN_FIFO_D70", + "D21": "CMT_IN_FIFO_D21", + "TESTMODEB": "CMT_IN_FIFO_TESTMODEB", + "D66": "CMT_IN_FIFO_D66", + "Q15": "CMT_IN_FIFO_Q15", + "Q71": "CMT_IN_FIFO_Q71", + "Q50": "CMT_IN_FIFO_Q50", + "Q42": "CMT_IN_FIFO_Q42", + "SCANOUT2": "CMT_IN_FIFO_SCANOUT2", + "Q26": "CMT_IN_FIFO_Q26", + "Q80": "CMT_IN_FIFO_Q80", + "Q10": "CMT_IN_FIFO_Q10", + "Q85": "CMT_IN_FIFO_Q85", + "D32": "CMT_IN_FIFO_D32", + "Q32": "CMT_IN_FIFO_Q32", + "Q16": "CMT_IN_FIFO_Q16", + "Q23": "CMT_IN_FIFO_Q23", + "D40": "CMT_IN_FIFO_D40", + "Q83": "CMT_IN_FIFO_Q83", + "Q11": "CMT_IN_FIFO_Q11", + "D20": "CMT_IN_FIFO_D20", + "D13": "CMT_IN_FIFO_D13", + "Q40": "CMT_IN_FIFO_Q40", + "D10": "CMT_IN_FIFO_D10", + "Q31": "CMT_IN_FIFO_Q31", + "Q93": "CMT_IN_FIFO_Q93", + "Q65": "CMT_IN_FIFO_Q65", + "SCANIN3": "CMT_IN_FIFO_SCANIN3", + "Q96": "CMT_IN_FIFO_Q96", + "D90": "CMT_IN_FIFO_D90", + "Q63": "CMT_IN_FIFO_Q63", + "D93": "CMT_IN_FIFO_D93", + "Q04": "CMT_IN_FIFO_Q04", + "Q72": "CMT_IN_FIFO_Q72", + "Q37": "CMT_IN_FIFO_Q37", + "D73": "CMT_IN_FIFO_D73", + "D65": "CMT_IN_FIFO_D65", + "D64": "CMT_IN_FIFO_D64", + "D61": "CMT_IN_FIFO_D61", + "D57": "CMT_IN_FIFO_D57", + "Q36": "CMT_IN_FIFO_Q36", + "Q97": "CMT_IN_FIFO_Q97", + "Q13": "CMT_IN_FIFO_Q13", + "RESET": "CMT_IN_FIFO_RESET", + "D12": "CMT_IN_FIFO_D12", + "TESTREADDISB": "CMT_IN_FIFO_TESTREADDISB", + "D03": "CMT_IN_FIFO_D03", + "D91": "CMT_IN_FIFO_D91", + "Q02": "CMT_IN_FIFO_Q02", + "D30": "CMT_IN_FIFO_D30", + "Q82": "CMT_IN_FIFO_Q82", + "Q62": "CMT_IN_FIFO_Q62", + "SCANOUT3": "CMT_IN_FIFO_SCANOUT3", + "Q74": "CMT_IN_FIFO_Q74", + "Q30": "CMT_IN_FIFO_Q30", + "Q60": "CMT_IN_FIFO_Q60", + "Q70": "CMT_IN_FIFO_Q70", + "D55": "CMT_IN_FIFO_D55", + "D63": "CMT_IN_FIFO_D63", + "D54": "CMT_IN_FIFO_D54", + "Q73": "CMT_IN_FIFO_Q73", + "Q55": "CMT_IN_FIFO_Q55", + "TESTWRITEDISB": "CMT_IN_FIFO_TESTWRITEDISB", + "RDCLK": "CMT_IN_FIFO_RDCLK", + "Q53": "CMT_IN_FIFO_Q53", + "D81": "CMT_IN_FIFO_D81", + "D42": "CMT_IN_FIFO_D42", + "D22": "CMT_IN_FIFO_D22", + "Q35": "CMT_IN_FIFO_Q35", + "D71": "CMT_IN_FIFO_D71", + "D56": "CMT_IN_FIFO_D56", + "ALMOSTEMPTY": "CMT_IN_FIFO_ALMOSTEMPTY", + "Q03": "CMT_IN_FIFO_Q03", + "D50": "CMT_IN_FIFO_D50", + "Q87": "CMT_IN_FIFO_Q87", + "Q22": "CMT_IN_FIFO_Q22", + "D52": "CMT_IN_FIFO_D52", + "D00": "CMT_IN_FIFO_D00", + "Q76": "CMT_IN_FIFO_Q76", + "EMPTY": "CMT_IN_FIFO_EMPTY", + "Q14": "CMT_IN_FIFO_Q14", + "Q44": "CMT_IN_FIFO_Q44", + "SCANIN2": "CMT_IN_FIFO_SCANIN2" + }, + "x_coord": 0 + } + ], + "wires": [ + "CMT_FIFO_NW4END0_8", + "CMT_OUT_FIFO_D87", + "CMT_IN_FIFO_D65", + "CMT_FIFO_L_IMUX35_3", + "CMT_FIFO_L_LOGIC_OUTS0_8", + "CMT_OUT_FIFO_SCANOUT3", + "CMT_FIFO_L_FAN2_2", + "CMT_FIFO_SE4C3_4", + "CMT_FIFO_L_IMUX3_6", + "CMT_OUT_FIFO_D00", + "CMT_FIFO_L_FAN4_9", + "CMT_IN_FIFO_Q14", + "CMT_FIFO_NW4END3_5", + "CMT_FIFO_WL1END1_10", + "CMT_FIFO_SW2A1_11", + "CMT_FIFO_L_LOGIC_OUTS23_6", + "CMT_FIFO_EE2A0_9", + "CMT_FIFO_L_IMUX19_9", + "CMT_FIFO_SW2A1_4", + "CMT_FIFO_EL1BEG3_5", + "CMT_FIFO_SE4BEG3_1", + "CMT_FIFO_L_FAN6_8", + "CMT_FIFO_NW4A2_0", + "CMT_FIFO_L_IMUX0_6", + "CMT_FIFO_L_FAN0_7", + "CMT_FIFO_NW2A2_9", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "CMT_FIFO_SE2A3_2", + "CMT_FIFO_SE4C1_9", + "CMT_OUT_FIFO_D81", + "CMT_FIFO_WW2A3_3", + "CMT_FIFO_SE2A3_4", + "CMT_FIFO_LH2_1", + "CMT_OUT_FIFO_Q61", + "CMT_FIFO_LH4_0", + "CMT_FIFO_L_LOGIC_OUTS15_5", + "CMT_FIFO_EL1BEG0_8", + "CMT_FIFO_WL1END2_4", + "CMT_FIFO_WW4END2_7", + "CMT_FIFO_EE2BEG2_3", + "CMT_FIFO_L_FAN1_7", + "CMT_FIFO_WL1END0_10", + "CMT_FIFO_L_IMUX0_5", + "CMT_FIFO_MONITOR_N_10", + "CMT_FIFO_WW4C2_7", + "CMT_FIFO_SW4END2_9", + "CMT_FIFO_SE4C0_10", + "CMT_FIFO_L_IMUX32_1", + "CMT_FIFO_L_IMUX26_0", + "CMT_FIFO_EE4C3_5", + "CMT_FIFO_WW4A1_8", + "CMT_FIFO_EL1BEG2_3", + "CMT_FIFO_LH10_4", + "CMT_FIFO_EE4A1_8", + "CMT_FIFO_L_IMUX45_3", + "CMT_FIFO_L_IMUX0_7", + "CMT_FIFO_WW4C3_9", + "CMT_FIFO_WW4END1_7", + "CMT_FIFO_EE4A2_10", + "CMT_FIFO_L_IMUX45_4", + "CMT_FIFO_NW2A0_2", + "CMT_FIFO_WL1END1_7", + "CMT_FIFO_NW4END0_11", + "CMT_FIFO_L_CTRL0_4", + "CMT_FIFO_L_IMUX10_7", + "CMT_FIFO_WW4B1_7", + "CMT_FIFO_SW4END3_4", + "CMT_FIFO_L_IMUX29_8", + "CMT_FIFO_L_IMUX30_4", + "CMT_IN_FIFO_Q22", + "CMT_FIFO_L_IMUX37_9", + "CMT_FIFO_SE4C0_8", + "CMT_FIFO_WW2A2_4", + "CMT_FIFO_SE2A1_8", + "CMT_FIFO_SW4A0_4", + "CMT_FIFO_WW4A1_4", + "CMT_FIFO_L_LOGIC_OUTS21_10", + "CMT_FIFO_L_IMUX40_9", + "CMT_FIFO_L_BYP1_2", + "CMT_OUT_FIFO_D85", + "CMT_FIFO_L_LOGIC_OUTS10_6", + "CMT_FIFO_EE2BEG0_0", + "CMT_FIFO_L_LOGIC_OUTS7_1", + "CMT_FIFO_NE4C1_10", + "CMT_IN_FIFO_Q41", + "CMT_FIFO_L_IMUX42_9", + "CMT_FIFO_L_IMUX45_7", + "CMT_FIFO_L_IMUX31_10", + "CMT_FIFO_LH8_0", + "CMT_FIFO_LH3_3", + "CMT_FIFO_L_BYP0_10", + "CMT_FIFO_L_LOGIC_OUTS17_11", + "CMT_FIFO_SW2A2_5", + "CMT_FIFO_LH11_4", + "CMT_FIFO_L_LOGIC_OUTS6_1", + "CMT_FIFO_WW4A3_4", + "CMT_FIFO_EE4A1_9", + "CMT_FIFO_EE2BEG0_4", + "CMT_FIFO_L_IMUX10_0", + "CMT_FIFO_NW4A0_2", + "CMT_FIFO_ER1BEG3_8", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "CMT_FIFO_L_CLK1_8", + "CMT_FIFO_L_IMUX39_2", + "CMT_FIFO_LH8_5", + "CMT_FIFO_SW4A0_11", + "CMT_FIFO_WW4B3_1", + "CMT_FIFO_EE2BEG2_9", + "CMT_FIFO_L_IMUX21_1", + "CMT_FIFO_EE4A0_6", + "CMT_FIFO_L_IMUX19_1", + "CMT_FIFO_LH10_2", + "CMT_FIFO_L_LOGIC_OUTS22_10", + "CMT_FIFO_SE4C0_5", + "FIFO_DQS_IOTOPHASER_1", + "CMT_FIFO_L_IMUX27_9", + "CMT_FIFO_LH1_6", + "CMT_FIFO_NE4BEG1_0", + "CMT_FIFO_L_IMUX31_6", + "CMT_FIFO_L_LOGIC_OUTS19_2", + "CMT_FIFO_L_IMUX33_8", + "CMT_FIFO_EE4BEG2_3", + "CMT_FIFO_L_LOGIC_OUTS15_8", + "CMT_FIFO_NE2A0_6", + "CMT_FIFO_WW2A1_2", + "CMT_OUT_FIFO_Q12", + "CMT_FIFO_L_BYP4_4", + "CMT_FIFO_WW4C3_5", + "CMT_FIFO_EE4B0_8", + "CMT_FIFO_L_IMUX33_1", + "CMT_FIFO_NE4BEG0_9", + "CMT_FIFO_SW4END3_5", + "CMT_FIFO_L_IMUX21_2", + "CMT_FIFO_WW4END2_6", + "CMT_FIFO_SE2A0_5", + "CMT_FIFO_L_IMUX35_2", + "CMT_FIFO_NW2A1_2", + "CMT_OUT_FIFO_ALMOSTEMPTY", + "CMT_FIFO_NE4BEG1_6", + "CMT_FIFO_EE4C3_10", + "CMT_FIFO_L_LOGIC_OUTS12_0", + "CMT_FIFO_L_BYP6_8", + "CMT_OUT_FIFO_Q30", + "CMT_FIFO_LH11_6", + "CMT_FIFO_WW2END1_2", + "CMT_FIFO_SW4END3_2", + "CMT_FIFO_EE4A1_0", + "CMT_FIFO_LH9_2", + "CMT_FIFO_L_LOGIC_OUTS23_8", + "CMT_FIFO_L_IMUX37_10", + "CMT_OUT_FIFO_D27", + "CMT_FIFO_WW2END1_1", + "CMT_FIFO_L_LOGIC_OUTS14_8", + "CMT_FIFO_SW2A1_8", + "FIFO_DQS_IOTOPHASER_22", + "CMT_FIFO_LH12_6", + "CMT_FIFO_NE4BEG3_4", + "CMT_FIFO_SW4END1_1", + "CMT_FIFO_L_IMUX31_9", + "CMT_OUT_FIFO_Q93", + "FIFO_DQS_IOTOPHASER_3", + "CMT_FIFO_L_IMUX0_11", + "CMT_FIFO_L_FAN5_9", + "CMT_FIFO_NE4BEG1_1", + "FIFO_DQS_IOTOPHASER_4", + "CMT_FIFO_WW4A1_2", + "CMT_FIFO_L_LOGIC_OUTS0_10", + "CMT_FIFO_L_IMUX29_10", + "CMT_OUT_FIFO_D10", + "CMT_FIFO_L_BYP1_11", + "CMT_FIFO_SE4BEG1_7", + "CMT_FIFO_SE2A3_6", + "CMT_FIFO_L_IMUX31_0", + "CMT_FIFO_MONITOR_P_2", + "CMT_FIFO_L_IMUX9_10", + "CMT_FIFO_L_BYP1_6", + "CMT_FIFO_L_LOGIC_OUTS2_2", + "CMT_IN_FIFO_SCANOUT0", + "CMT_IN_FIFO_Q03", + "CMT_FIFO_LH2_9", + "CMT_OUT_FIFO_RESET", + "CMT_FIFO_SW4A3_5", + "CMT_FIFO_L_LOGIC_OUTS1_3", + "CMT_FIFO_L_FAN7_8", + "CMT_FIFO_WW4C3_2", + "CMT_FIFO_L_IMUX45_8", + "CMT_FIFO_L_FAN5_5", + "CMT_FIFO_L_IMUX9_0", + "CMT_FIFO_WW4END1_8", + "CMT_FIFO_WR1END0_8", + "CMT_FIFO_L_IMUX44_8", + "CMT_FIFO_L_IMUX27_4", + "CMT_FIFO_L_FAN1_10", + "CMT_FIFO_EE2BEG3_8", + "CMT_FIFO_EE4B3_1", + "CMT_FIFO_L_LOGIC_OUTS16_8", + "CMT_FIFO_WL1END2_5", + "CMT_FIFO_WW4B0_2", + "CMT_FIFO_LH7_0", + "CMT_OUT_FIFO_RDCLK", + "CMT_FIFO_EE4C1_10", + "CMT_FIFO_WW2A3_6", + "CMT_FIFO_WW4A2_1", + "CMT_FIFO_WW4END3_9", + "CMT_FIFO_NE2A3_8", + "CMT_FIFO_L_FAN0_5", + "CMT_FIFO_EL1BEG0_2", + "CMT_FIFO_L_LOGIC_OUTS12_4", + "CMT_IN_FIFO_Q02", + "CMT_FIFO_EE4BEG2_7", + "CMT_FIFO_L_IMUX32_7", + "CMT_OUT_FIFO_Q92", + "CMT_FIFO_L_BYP1_9", + "CMT_OUT_FIFO_EMPTY", + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "CMT_FIFO_NE4C0_0", + "CMT_FIFO_L_IMUX14_11", + "CMT_FIFO_WW2A1_0", + "CMT_FIFO_WW4C0_9", + "CMT_IN_FIFO_EMPTY", + "CMT_FIFO_WW4END1_4", + "CMT_FIFO_SW2A1_7", + "CMT_FIFO_L_CLK0_0", + "CMT_FIFO_NE4BEG2_11", + "CMT_IN_FIFO_D52", + "CMT_FIFO_EE4BEG3_9", + "CMT_FIFO_L_IMUX40_2", + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "CMT_FIFO_L_BYP4_0", + "CMT_FIFO_EE4B1_2", + "CMT_FIFO_L_IMUX36_3", + "CMT_FIFO_WW4A0_3", + "CMT_FIFO_ER1BEG0_5", + "CMT_FIFO_SW4A0_8", + "CMT_FIFO_EE2BEG0_8", + "CMT_FIFO_EE2BEG3_3", + "CMT_FIFO_EL1BEG0_10", + "CMT_FIFO_L_IMUX42_11", + "CMT_FIFO_NE4C3_4", + "CMT_FIFO_EE2BEG1_2", + "CMT_FIFO_L_BYP6_10", + "CMT_FIFO_NE2A1_3", + "CMT_FIFO_L_IMUX3_7", + "CMT_FIFO_WR1END0_7", + "CMT_IN_FIFO_Q72", + "CMT_FIFO_L_IMUX6_3", + "CMT_FIFO_SE4C1_1", + "CMT_FIFO_L_FAN1_3", + "CMT_FIFO_SW2A1_2", + "CMT_FIFO_L_LOGIC_OUTS3_8", + "CMT_FIFO_L_IMUX32_11", + "CMT_FIFO_L_LOGIC_OUTS12_8", + "CMT_FIFO_WW4B1_5", + "CMT_FIFO_WW4B2_3", + "CMT_FIFO_L_IMUX5_0", + "CMT_FIFO_EL1BEG3_11", + "CMT_FIFO_L_IMUX31_2", + "CMT_FIFO_L_LOGIC_OUTS5_6", + "CMT_FIFO_L_LOGIC_OUTS23_3", + "CMT_OUT_FIFO_Q81", + "CMT_FIFO_L_LOGIC_OUTS7_6", + "CMT_FIFO_EE2BEG2_4", + "CMT_IN_FIFO_Q74", + "CMT_FIFO_LH6_6", + "CMT_FIFO_EE4C1_11", + "CMT_FIFO_EL1BEG2_10", + "CMT_FIFO_L_LOGIC_OUTS23_0", + "CMT_FIFO_NE4C3_7", + "CMT_FIFO_LH6_11", + "CMT_FIFO_SW4END1_3", + "CMT_FIFO_L_LOGIC_OUTS14_1", + "CMT_FIFO_EE4BEG0_2", + "CMT_FIFO_L_LOGIC_OUTS21_8", + "CMT_FIFO_L_CTRL1_11", + "CMT_FIFO_SE4C1_7", + "CMT_FIFO_L_BYP7_11", + "CMT_IN_FIFO_Q64", + "CMT_IN_FIFO_Q67", + "CMT_FIFO_NE2A0_8", + "CMT_FIFO_LH5_11", + "CMT_IN_FIFO_D01", + "CMT_FIFO_NE4C0_5", + "CMT_FIFO_WW4C2_0", + "CMT_FIFO_ER1BEG1_1", + "CMT_FIFO_EE4A1_3", + "CMT_FIFO_L_IMUX38_4", + "CMT_FIFO_SW2A3_7", + "CMT_FIFO_WL1END3_2", + "CMT_FIFO_EE4B2_9", + "CMT_OUT_FIFO_D32", + "CMT_FIFO_SE4BEG0_0", + "CMT_FIFO_L_IMUX21_6", + "CMT_FIFO_WW4A2_8", + "CMT_FIFO_WW4END0_9", + "CMT_OUT_FIFO_D62", + "CMT_FIFO_L_IMUX36_7", + "CMT_FIFO_WL1END1_4", + "CMT_FIFO_EE4B0_4", + "CMT_IN_FIFO_Q55", + "CMT_FIFO_NE2A3_10", + "CMT_FIFO_L_IMUX1_7", + "CMT_OUT_FIFO_D24", + "CMT_FIFO_L_CLK0_6", + "CMT_FIFO_L_IMUX42_4", + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "CMT_FIFO_LH9_3", + "CMT_FIFO_L_IMUX28_0", + "CMT_FIFO_LH4_4", + "CMT_FIFO_NE4BEG1_7", + "CMT_FIFO_LH6_4", + "CMT_FIFO_L_LOGIC_OUTS19_8", + "CMT_FIFO_L_IMUX24_2", + "CMT_FIFO_L_CTRL0_2", + "CMT_FIFO_NW4END3_2", + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "CMT_FIFO_L_IMUX12_5", + "CMT_FIFO_L_LOGIC_OUTS5_9", + "CMT_FIFO_L_IMUX12_6", + "CMT_FIFO_L_LOGIC_OUTS9_0", + "CMT_FIFO_L_BYP2_5", + "CMT_FIFO_L_IMUX30_10", + "CMT_FIFO_SW2A0_11", + "CMT_FIFO_WW4B2_7", + "CMT_FIFO_L_IMUX29_1", + "CMT_FIFO_L_IMUX34_4", + "CMT_FIFO_L_IMUX31_7", + "CMT_FIFO_L_IMUX29_9", + "CMT_FIFO_L_IMUX44_10", + "CMT_IN_FIFO_Q75", + "CMT_FIFO_L_FAN5_1", + "CMT_FIFO_L_IMUX18_6", + "CMT_FIFO_L_BYP1_3", + "CMT_FIFO_NW2A2_10", + "CMT_FIFO_L_LOGIC_OUTS15_7", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "CMT_FIFO_WW4A3_6", + "CMT_OUT_FIFO_Q32", + "CMT_FIFO_L_IMUX2_10", + "CMT_OUT_FIFO_Q31", + "CMT_FIFO_L_LOGIC_OUTS8_3", + "CMT_OUT_FIFO_D31", + "CMT_FIFO_SE4BEG0_4", + "CMT_FIFO_LH1_0", + "CMT_IN_FIFO_Q76", + "CMT_FIFO_SW4A3_0", + "CMT_FIFO_SE4BEG3_9", + "CMT_IN_FIFO_Q97", + "CMT_OUT_FIFO_SCANOUT0", + "CMT_FIFO_ER1BEG2_9", + "CMT_FIFO_SW4A0_6", + "CMT_FIFO_LH9_0", + "CMT_FIFO_L_FAN4_1", + "CMT_FIFO_WW2END0_11", + "CMT_FIFO_WL1END2_3", + "CMT_FIFO_L_LOGIC_OUTS10_9", + "CMT_FIFO_EE4B2_8", + "CMT_FIFO_L_CLK1_10", + "CMT_FIFO_EE4BEG2_6", + "CMT_FIFO_LH10_6", + "CMT_IN_FIFO_D54", + "CMT_FIFO_L_CLK0_2", + "CMT_FIFO_ER1BEG2_3", + "CMT_FIFO_WW4C2_1", + "CMT_FIFO_L_IMUX34_11", + "CMT_FIFO_L_FAN3_10", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "CMT_FIFO_EE4B2_5", + "CMT_FIFO_L_BYP3_0", + "CMT_FIFO_L_IMUX29_4", + "CMT_FIFO_L_FAN1_0", + "CMT_FIFO_LH4_10", + "CMT_FIFO_WW2END3_6", + "CMT_FIFO_NE4BEG2_10", + "CMT_FIFO_EE4A3_3", + "CMT_FIFO_L_IMUX10_3", + "CMT_FIFO_NW4END2_1", + "CMT_FIFO_ER1BEG0_6", + "CMT_FIFO_L_LOGIC_OUTS19_6", + "CMT_FIFO_L_LOGIC_OUTS18_4", + "CMT_FIFO_L_IMUX21_11", + "CMT_FIFO_WR1END2_11", + "CMT_FIFO_L_BYP0_0", + "CMT_FIFO_SE4C1_2", + "CMT_FIFO_L_IMUX45_9", + "CMT_FIFO_L_IMUX8_7", + "CMT_FIFO_EE4B0_3", + "CMT_FIFO_L_FAN3_0", + "CMT_IN_FIFO_D67", + "CMT_FIFO_L_CLK0_4", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "CMT_FIFO_EE2BEG3_6", + "CMT_FIFO_SE2A2_10", + "CMT_FIFO_ER1BEG2_10", + "CMT_FIFO_L_IMUX38_10", + "CMT_FIFO_L_FAN4_8", + "CMT_FIFO_NW2A2_1", + "CMT_FIFO_EE2A1_6", + "CMT_FIFO_WW4C0_6", + "CMT_FIFO_L_LOGIC_OUTS16_5", + "CMT_FIFO_L_IMUX23_10", + "CMT_FIFO_EE4B3_2", + "CMT_FIFO_L_IMUX13_6", + "CMT_FIFO_L_FAN2_0", + "CMT_FIFO_NE2A0_2", + "CMT_FIFO_L_IMUX41_0", + "CMT_FIFO_EE2BEG3_7", + "CMT_FIFO_L_LOGIC_OUTS18_7", + "CMT_FIFO_L_IMUX42_5", + "CMT_FIFO_L_IMUX40_5", + "CMT_FIFO_L_IMUX18_8", + "CMT_FIFO_WW2END0_7", + "CMT_FIFO_WW4B3_5", + "CMT_FIFO_L_IMUX4_2", + "CMT_FIFO_L_LOGIC_OUTS23_5", + "CMT_FIFO_LH9_6", + "CMT_FIFO_LH1_5", + "CMT_FIFO_SE4C1_11", + "CMT_FIFO_ER1BEG0_7", + "CMT_FIFO_WW2A3_11", + "CMT_FIFO_EE4BEG1_4", + "CMT_FIFO_NW4END1_3", + "CMT_FIFO_L_LOGIC_OUTS7_4", + "CMT_FIFO_EL1BEG3_8", + "CMT_FIFO_NW2A0_1", + "CMT_OUT_FIFO_D11", + "CMT_FIFO_L_IMUX4_1", + "CMT_FIFO_L_LOGIC_OUTS5_5", + "CMT_OUT_FIFO_Q73", + "CMT_FIFO_WW4B2_9", + "CMT_FIFO_L_LOGIC_OUTS0_0", + "CMT_FIFO_EE4BEG2_5", + "CMT_FIFO_L_BYP0_3", + "CMT_FIFO_EE4BEG3_5", + "CMT_FIFO_L_IMUX23_0", + "CMT_FIFO_L_LOGIC_OUTS19_7", + "CMT_FIFO_WW4A0_7", + "CMT_OUT_FIFO_D95", + "CMT_FIFO_L_LOGIC_OUTS17_9", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "CMT_FIFO_L_IMUX40_6", + "CMT_FIFO_EE4C0_1", + "CMT_FIFO_L_IMUX0_9", + "CMT_FIFO_WR1END1_4", + "CMT_FIFO_L_IMUX26_4", + "CMT_FIFO_NW4A0_11", + "CMT_FIFO_L_IMUX18_0", + "CMT_FIFO_L_IMUX13_9", + "CMT_FIFO_SE4C2_10", + "CMT_FIFO_EE4A0_11", + "CMT_FIFO_EE2BEG0_6", + "CMT_FIFO_EE2BEG1_11", + "CMT_FIFO_WW2A1_9", + "CMT_FIFO_ER1BEG3_5", + "CMT_FIFO_L_FAN1_4", + "CMT_FIFO_NW4A1_6", + "CMT_FIFO_L_LOGIC_OUTS16_6", + "CMT_FIFO_L_LOGIC_OUTS11_11", + "CMT_FIFO_WW2END0_2", + "CMT_FIFO_EE4BEG2_10", + "CMT_FIFO_WW2A0_9", + "CMT_FIFO_L_IMUX30_7", + "CMT_FIFO_L_IMUX7_0", + "CMT_FIFO_EL1BEG1_9", + "CMT_FIFO_L_IMUX26_7", + "CMT_FIFO_L_IMUX22_9", + "CMT_FIFO_L_IMUX43_5", + "CMT_FIFO_SW4END2_8", + "CMT_FIFO_L_BYP5_8", + "CMT_OUT_FIFO_Q02", + "CMT_FIFO_NE4C0_8", + "CMT_OUT_FIFO_D22", + "CMT_FIFO_L_IMUX23_5", + "CMT_FIFO_NE4C1_8", + "CMT_FIFO_WW4A3_2", + "CMT_FIFO_WR1END1_5", + "CMT_FIFO_NW4END2_6", + "CMT_FIFO_L_LOGIC_OUTS13_5", + "CMT_FIFO_L_IMUX26_1", + "CMT_FIFO_WL1END0_4", + "CMT_FIFO_SE4BEG2_2", + "CMT_FIFO_LH2_10", + "CMT_FIFO_L_LOGIC_OUTS0_4", + "CMT_FIFO_EE4C3_0", + "CMT_FIFO_L_BYP0_4", + "CMT_FIFO_NE2A1_1", + "CMT_FIFO_SW2A1_9", + "CMT_FIFO_LH9_8", + "CMT_FIFO_L_IMUX10_10", + "CMT_OUT_FIFO_D57", + "CMT_FIFO_L_IMUX21_7", + "CMT_FIFO_L_LOGIC_OUTS4_6", + "CMT_FIFO_SW2A0_1", + "CMT_FIFO_NE2A2_11", + "CMT_FIFO_LH11_3", + "CMT_FIFO_L_IMUX46_5", + "CMT_FIFO_L_IMUX32_8", + "CMT_FIFO_SW4END1_9", + "CMT_IN_FIFO_SCANOUT2", + "CMT_FIFO_NW4A1_0", + "CMT_FIFO_L_BYP4_2", + "FIFO_DQS_IOTOPHASER_66", + "CMT_FIFO_WR1END2_9", + "CMT_FIFO_NW2A0_11", + "CMT_FIFO_NW2A3_5", + "CMT_OUT_FIFO_D44", + "CMT_FIFO_NW4END1_0", + "CMT_FIFO_WW2END2_1", + "CMT_FIFO_L_IMUX17_8", + "CMT_FIFO_NW4END0_0", + "CMT_FIFO_SW2A3_5", + "CMT_FIFO_EL1BEG3_9", + "CMT_FIFO_LH12_0", + "CMT_FIFO_WW4A0_9", + "CMT_FIFO_L_IMUX34_0", + "CMT_IN_FIFO_D10", + "CMT_FIFO_EE2BEG1_1", + "CMT_IN_FIFO_Q91", + "CMT_FIFO_NE4C3_8", + "CMT_FIFO_EE2BEG1_0", + "CMT_FIFO_L_LOGIC_OUTS10_0", + "CMT_FIFO_NE4BEG0_5", + "CMT_FIFO_MONITOR_P_11", + "CMT_FIFO_SE2A3_0", + "CMT_FIFO_NE4BEG2_5", + "CMT_FIFO_NW4END3_8", + "CMT_FIFO_LH8_7", + "CMT_FIFO_L_LOGIC_OUTS19_9", + "CMT_FIFO_L_IMUX5_1", + "CMT_IN_FIFO_D64", + "CMT_FIFO_L_CTRL1_3", + "CMT_FIFO_WW4END3_6", + "CMT_FIFO_L_FAN7_9", + "CMT_FIFO_EE4BEG1_8", + "CMT_IN_FIFO_SCANIN3", + "CMT_FIFO_NW2A1_0", + "CMT_OUT_FIFO_Q90", + "CMT_FIFO_L_LOGIC_OUTS19_10", + "CMT_FIFO_L_IMUX41_4", + "CMT_FIFO_NW4END2_7", + "CMT_FIFO_L_FAN3_5", + "CMT_FIFO_L_LOGIC_OUTS23_9", + "CMT_FIFO_L_IMUX0_1", + "CMT_FIFO_SE4BEG2_3", + "CMT_OUT_FIFO_Q13", + "CMT_FIFO_L_FAN4_10", + "CMT_FIFO_SW2A0_10", + "CMT_FIFO_L_IMUX1_8", + "CMT_FIFO_L_CTRL1_9", + "CMT_FIFO_EE4BEG1_2", + "CMT_FIFO_L_LOGIC_OUTS11_7", + "CMT_FIFO_SW4A1_8", + "CMT_FIFO_SW2A1_0", + "CMT_OUT_FIFO_Q21", + "CMT_FIFO_NW4END0_5", + "CMT_FIFO_L_IMUX40_1", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_11", + "CMT_FIFO_EE2A2_2", + "CMT_FIFO_L_IMUX28_7", + "CMT_FIFO_ER1BEG1_8", + "CMT_FIFO_WW4C0_3", + "CMT_FIFO_L_LOGIC_OUTS0_1", + "CMT_FIFO_WW2A3_2", + "CMT_FIFO_L_IMUX20_8", + "CMT_FIFO_L_IMUX8_6", + "CMT_FIFO_WW2END2_2", + "CMT_FIFO_WW2END1_5", + "CMT_FIFO_L_IMUX0_3", + "CMT_FIFO_ER1BEG3_4", + "CMT_FIFO_NW4A2_11", + "CMT_FIFO_ER1BEG0_10", + "CMT_FIFO_EE4A0_2", + "CMT_FIFO_L_BYP2_8", + "CMT_FIFO_L_IMUX12_3", + "CMT_FIFO_SW4A2_9", + "CMT_FIFO_L_LOGIC_OUTS0_9", + "CMT_FIFO_NE2A1_4", + "CMT_OUT_FIFO_D50", + "CMT_FIFO_WW2A2_7", + "CMT_FIFO_L_BYP6_3", + "CMT_FIFO_EE4A0_8", + "CMT_FIFO_L_IMUX25_10", + "CMT_FIFO_L_IMUX14_4", + "CMT_IN_FIFO_WREN", + "CMT_FIFO_WR1END3_6", + "CMT_FIFO_SE2A2_5", + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "CMT_FIFO_L_LOGIC_OUTS14_3", + "CMT_FIFO_EE4A3_4", + "CMT_FIFO_NW4A1_2", + "CMT_FIFO_WW2A2_10", + "CMT_OUT_FIFO_Q65", + "CMT_FIFO_LH5_4", + "CMT_FIFO_L_IMUX37_2", + "CMT_FIFO_EE2BEG3_10", + "CMT_FIFO_L_IMUX23_4", + "CMT_FIFO_EE2A3_4", + "CMT_FIFO_EE4A2_5", + "CMT_FIFO_WW2A3_9", + "CMT_FIFO_L_IMUX26_2", + "CMT_FIFO_L_CTRL0_1", + "CMT_FIFO_EE4C1_4", + "CMT_FIFO_SE4BEG0_9", + "CMT_FIFO_WW2END3_9", + "CMT_FIFO_LH8_8", + "CMT_FIFO_L_IMUX28_4", + "CMT_FIFO_L_IMUX3_0", + "CMT_FIFO_MONITOR_N_11", + "CMT_FIFO_EE4A3_1", + "CMT_FIFO_L_LOGIC_OUTS14_7", + "CMT_FIFO_L_IMUX11_9", + "CMT_FIFO_L_IMUX27_11", + "CMT_IN_FIFO_D73", + "CMT_FIFO_SE4C0_11", + "CMT_IN_FIFO_Q43", + "CMT_FIFO_L_BYP6_2", + "CMT_FIFO_L_IMUX34_10", + "CMT_FIFO_EE4B0_1", + "CMT_FIFO_LH4_2", + "CMT_FIFO_WW4B0_9", + "CMT_FIFO_L_FAN0_0", + "CMT_FIFO_NE4BEG2_4", + "CMT_FIFO_L_IMUX15_2", + "CMT_FIFO_WW2A0_4", + "CMT_FIFO_L_IMUX44_4", + "CMT_FIFO_EE4BEG0_4", + "CMT_FIFO_L_FAN5_7", + "CMT_FIFO_EL1BEG0_11", + "CMT_FIFO_L_IMUX37_0", + "CMT_FIFO_L_BYP7_7", + "CMT_FIFO_L_IMUX5_7", + "CMT_FIFO_L_LOGIC_OUTS9_10", + "CMT_FIFO_SE4BEG0_2", + "CMT_FIFO_L_BYP7_9", + "CMT_FIFO_EE4A3_6", + "CMT_OUT_FIFO_Q10", + "CMT_FIFO_L_LOGIC_OUTS10_4", + "CMT_FIFO_L_IMUX14_5", + "CMT_FIFO_L_LOGIC_OUTS16_9", + "CMT_FIFO_NW4END1_8", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_8", + "CMT_FIFO_L_IMUX27_6", + "CMT_IN_FIFO_Q73", + "CMT_FIFO_L_LOGIC_OUTS17_0", + "CMT_FIFO_L_IMUX10_4", + "CMT_FIFO_SE4BEG1_3", + "CMT_FIFO_SW2A0_3", + "CMT_FIFO_SW4A2_2", + "CMT_FIFO_L_FAN4_2", + "CMT_FIFO_L_IMUX16_11", + "CMT_FIFO_ER1BEG1_11", + "CMT_FIFO_SE2A3_3", + "CMT_FIFO_ER1BEG3_10", + "CMT_FIFO_WW4A0_1", + "CMT_FIFO_L_IMUX22_7", + "CMT_FIFO_WW4END2_2", + "CMT_FIFO_EE4C2_1", + "CMT_FIFO_L_LOGIC_OUTS20_7", + "CMT_FIFO_LH8_6", + "CMT_FIFO_MONITOR_N_3", + "CMT_IN_FIFO_Q70", + "CMT_FIFO_SW2A2_7", + "CMT_FIFO_WW4A1_9", + "CMT_FIFO_L_BYP0_11", + "CMT_FIFO_L_LOGIC_OUTS18_11", + "CMT_IN_FIFO_D51", + "CMT_FIFO_LH5_9", + "CMT_FIFO_EE4C3_8", + "CMT_FIFO_L_IMUX35_9", + "CMT_OUT_FIFO_D01", + "CMT_FIFO_WR1END0_6", + "CMT_FIFO_L_IMUX28_10", + "CMT_FIFO_WW4C2_8", + "CMT_OUT_FIFO_Q62", + "CMT_FIFO_L_IMUX30_9", + "CMT_FIFO_NE2A0_4", + "CMT_FIFO_L_IMUX34_2", + "CMT_FIFO_EE2A0_4", + "CMT_FIFO_SE2A0_3", + "CMT_FIFO_LH12_8", + "CMT_FIFO_NE2A1_7", + "CMT_FIFO_L_LOGIC_OUTS16_11", + "CMT_FIFO_NW4A3_6", + "CMT_FIFO_NE4BEG0_0", + "CMT_FIFO_L_IMUX40_4", + "CMT_FIFO_EE4B1_6", + "CMT_FIFO_WW2END3_5", + "CMT_FIFO_NE4BEG3_11", + "CMT_FIFO_EE2A0_7", + "CMT_FIFO_L_IMUX2_0", + "CMT_FIFO_EE4C2_5", + "CMT_FIFO_L_IMUX31_4", + "CMT_FIFO_L_IMUX30_6", + "CMT_FIFO_L_LOGIC_OUTS15_0", + "CMT_FIFO_WR1END2_0", + "CMT_FIFO_ER1BEG1_5", + "CMT_FIFO_L_LOGIC_OUTS11_4", + "CMT_FIFO_L_LOGIC_OUTS20_2", + "CMT_FIFO_EE4BEG3_8", + "CMT_FIFO_L_IMUX41_1", + "CMT_FIFO_L_BYP2_11", + "CMT_FIFO_NE2A3_11", + "CMT_FIFO_L_FAN6_0", + "CMT_FIFO_L_IMUX44_0", + "CMT_FIFO_NW4END0_9", + "CMT_FIFO_EL1BEG2_11", + "CMT_OUT_FIFO_D76", + "CMT_FIFO_L_IMUX2_9", + "CMT_FIFO_WW4C3_6", + "CMT_FIFO_EE2A0_5", + "CMT_FIFO_NW4A0_4", + "CMT_FIFO_EL1BEG3_10", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_1", + "CMT_IN_FIFO_Q57", + "CMT_FIFO_WW4END0_8", + "CMT_FIFO_EE4BEG1_11", + "CMT_FIFO_L_IMUX9_11", + "CMT_FIFO_L_BYP3_9", + "CMT_FIFO_EE4C0_3", + "CMT_OUT_FIFO_Q82", + "CMT_FIFO_L_IMUX30_3", + "CMT_FIFO_L_CTRL1_7", + "CMT_FIFO_L_BYP3_7", + "CMT_FIFO_SE2A1_4", + "CMT_FIFO_L_LOGIC_OUTS21_3", + "CMT_FIFO_L_IMUX10_2", + "CMT_FIFO_SW4A1_7", + "CMT_FIFO_NW2A0_3", + "CMT_FIFO_NW4A0_0", + "CMT_FIFO_WL1END3_9", + "CMT_FIFO_L_IMUX24_9", + "CMT_FIFO_EE2BEG0_5", + "CMT_FIFO_L_BYP6_5", + "CMT_FIFO_L_FAN5_4", + "CMT_FIFO_L_IMUX24_7", + "CMT_FIFO_EE4C1_6", + "CMT_FIFO_L_IMUX4_6", + "CMT_FIFO_NE4C2_0", + "CMT_FIFO_L_BYP5_0", + "CMT_FIFO_L_IMUX21_8", + "CMT_FIFO_L_IMUX19_11", + "CMT_FIFO_L_IMUX20_11", + "CMT_FIFO_SE4C1_6", + "CMT_FIFO_L_CTRL0_5", + "CMT_FIFO_L_IMUX20_0", + "CMT_FIFO_L_LOGIC_OUTS22_5", + "CMT_FIFO_WW4C1_5", + "CMT_FIFO_LH4_3", + "CMT_FIFO_NW4A3_3", + "CMT_FIFO_SE2A0_9", + "CMT_FIFO_SE2A1_3", + "CMT_FIFO_SE4C1_8", + "CMT_FIFO_L_IMUX14_1", + "CMT_FIFO_L_IMUX17_10", + "CMT_FIFO_L_IMUX46_1", + "CMT_FIFO_EE4C2_3", + "CMT_FIFO_NE2A2_0", + "CMT_FIFO_L_IMUX38_7", + "CMT_FIFO_ER1BEG3_6", + "CMT_FIFO_LH3_10", + "CMT_FIFO_EE4C1_0", + "CMT_IN_FIFO_SCANENB", + "CMT_FIFO_SW4END0_4", + "CMT_FIFO_WL1END0_9", + "CMT_FIFO_NW2A1_9", + "CMT_FIFO_SE2A3_5", + "CMT_FIFO_L_IMUX38_3", + "CMT_FIFO_WW4B1_0", + "CMT_FIFO_LH6_0", + "CMT_FIFO_EE4B1_10", + "CMT_IN_FIFO_Q36", + "CMT_FIFO_L_IMUX9_6", + "CMT_IN_FIFO_Q13", + "CMT_OUT_FIFO_SCANIN1", + "CMT_FIFO_L_LOGIC_OUTS6_11", + "CMT_FIFO_ER1BEG1_0", + "CMT_FIFO_L_BYP6_11", + "CMT_FIFO_SW4END3_9", + "CMT_FIFO_L_LOGIC_OUTS9_3", + "CMT_FIFO_L_BYP4_11", + "CMT_FIFO_EE4B1_1", + "CMT_FIFO_EE4BEG2_2", + "CMT_FIFO_L_LOGIC_OUTS12_2", + "CMT_FIFO_L_IMUX2_7", + "CMT_FIFO_EE2A3_8", + "CMT_IN_FIFO_Q45", + "CMT_FIFO_NE2A1_10", + "CMT_FIFO_SW2A2_0", + "CMT_FIFO_EE2BEG2_7", + "CMT_FIFO_SW4A3_10", + "CMT_FIFO_NW2A1_6", + "CMT_FIFO_NE4C2_6", + "CMT_FIFO_L_LOGIC_OUTS8_2", + "CMT_FIFO_L_IMUX14_10", + "CMT_FIFO_SW2A3_9", + "CMT_FIFO_EE4B2_7", + "CMT_FIFO_L_BYP3_2", + "CMT_FIFO_SW2A2_6", + "CMT_FIFO_NW4END1_9", + "CMT_OUT_FIFO_Q63", + "CMT_IN_FIFO_D57", + "CMT_FIFO_L_LOGIC_OUTS2_11", + "CMT_FIFO_EE4A1_5", + "CMT_FIFO_L_CLK1_11", + "CMT_OUT_FIFO_D92", + "CMT_FIFO_NW4END2_9", + "CMT_FIFO_L_FAN6_11", + "CMT_FIFO_WL1END3_0", + "CMT_FIFO_NE4BEG0_6", + "CMT_FIFO_NE2A2_2", + "CMT_FIFO_WR1END3_0", + "CMT_FIFO_NE4C1_3", + "CMT_FIFO_SE2A2_9", + "CMT_FIFO_L_LOGIC_OUTS15_6", + "CMT_FIFO_L_BYP1_4", + "CMT_FIFO_L_LOGIC_OUTS1_1", + "CMT_FIFO_SE4C0_2", + "CMT_FIFO_NW4A2_2", + "CMT_FIFO_MONITOR_N_1", + "CMT_IN_FIFO_Q95", + "CMT_FIFO_WW4B2_10", + "CMT_FIFO_L_IMUX5_5", + "CMT_IN_FIFO_Q05", + "CMT_FIFO_L_IMUX2_2", + "CMT_FIFO_L_BYP0_1", + "CMT_FIFO_L_BYP4_10", + "CMT_OUT_FIFO_Q51", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "CMT_FIFO_L_CTRL0_3", + "CMT_FIFO_L_IMUX4_8", + "CMT_FIFO_WW2END3_11", + "CMT_FIFO_WW4A3_0", + "CMT_FIFO_L_IMUX45_5", + "CMT_FIFO_EE4B0_0", + "CMT_FIFO_L_IMUX22_10", + "CMT_FIFO_EE4A2_2", + "CMT_FIFO_L_CTRL1_6", + "CMT_FIFO_SW4A0_7", + "CMT_FIFO_WW4C2_4", + "CMT_FIFO_WW4A0_2", + "CMT_FIFO_EE4BEG1_10", + "CMT_FIFO_L_LOGIC_OUTS18_0", + "CMT_FIFO_L_IMUX23_2", + "CMT_FIFO_EE2A1_11", + "CMT_FIFO_L_BYP3_6", + "CMT_FIFO_NW2A3_10", + "CMT_FIFO_L_LOGIC_OUTS23_7", + "CMT_FIFO_L_FAN3_7", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "CMT_FIFO_WW2A1_7", + "CMT_FIFO_L_IMUX3_5", + "CMT_FIFO_NW2A2_4", + "CMT_FIFO_L_LOGIC_OUTS17_1", + "CMT_FIFO_SE4BEG1_10", + "CMT_FIFO_L_IMUX5_9", + "CMT_FIFO_LH5_2", + "CMT_FIFO_NW4A0_10", + "CMT_FIFO_L_LOGIC_OUTS4_10", + "CMT_FIFO_EE4BEG3_7", + "CMT_FIFO_NE2A3_3", + "CMT_FIFO_L_FAN5_11", + "CMT_FIFO_LH9_5", + "CMT_FIFO_WW4C0_4", + "CMT_FIFO_EE2BEG1_3", + "CMT_FIFO_SE4BEG0_7", + "CMT_OUT_FIFO_D20", + "CMT_FIFO_WW4C3_7", + "CMT_FIFO_L_IMUX11_6", + "CMT_FIFO_WW4B3_3", + "CMT_FIFO_L_IMUX8_3", + "CMT_FIFO_ER1BEG1_9", + "CMT_FIFO_L_IMUX29_3", + "CMT_FIFO_SE2A3_11", + "CMT_OUT_FIFO_Q42", + "CMT_FIFO_SW4A1_6", + "CMT_FIFO_L_PHASER_WRCLK", + "CMT_FIFO_L_IMUX19_7", + "CMT_FIFO_L_LOGIC_OUTS1_10", + "CMT_FIFO_L_LOGIC_OUTS9_4", + "CMT_FIFO_L_LOGIC_OUTS22_4", + "CMT_OUT_FIFO_Q11", + "CMT_FIFO_L_IMUX22_4", + "CMT_OUT_FIFO_Q52", + "CMT_FIFO_L_LOGIC_OUTS3_1", + "CMT_OUT_FIFO_D13", + "CMT_OUT_FIFO_TESTREADDISB", + "CMT_FIFO_WW4B1_9", + "CMT_FIFO_L_IMUX7_8", + "CMT_FIFO_NW4A0_3", + "CMT_FIFO_SW4END1_4", + "CMT_FIFO_WR1END1_1", + "CMT_FIFO_EE4B0_7", + "CMT_FIFO_L_LOGIC_OUTS6_0", + "CMT_FIFO_LH3_11", + "CMT_FIFO_EE2BEG0_2", + "CMT_FIFO_L_IMUX6_5", + "CMT_FIFO_LH7_4", + "CMT_FIFO_EE4A2_9", + "CMT_FIFO_EE4C1_2", + "CMT_FIFO_L_IMUX28_11", + "CMT_FIFO_EE2A3_6", + "CMT_FIFO_SE2A3_8", + "CMT_FIFO_SE2A1_5", + "CMT_FIFO_EE2BEG2_8", + "CMT_FIFO_SW4A3_11", + "CMT_FIFO_SE2A2_0", + "CMT_FIFO_L_FAN0_10", + "CMT_FIFO_SE2A2_3", + "CMT_FIFO_L_IMUX42_1", + "CMT_FIFO_WL1END0_11", + "CMT_FIFO_L_IMUX11_4", + "CMT_FIFO_EE4A0_4", + "CMT_FIFO_SW4END2_3", + "CMT_IN_FIFO_Q63", + "CMT_FIFO_EL1BEG3_4", + "CMT_FIFO_WW2END3_0", + "CMT_FIFO_L_LOGIC_OUTS23_4", + "CMT_FIFO_WW2END3_2", + "CMT_FIFO_L_IMUX18_5", + "CMT_FIFO_L_LOGIC_OUTS6_3", + "CMT_FIFO_EE4C2_8", + "CMT_FIFO_NW4A2_1", + "CMT_FIFO_LH11_11", + "CMT_FIFO_L_IMUX18_9", + "CMT_FIFO_WW4C1_6", + "CMT_FIFO_LH6_2", + "CMT_FIFO_L_IMUX33_6", + "CMT_FIFO_NE2A2_4", + "CMT_FIFO_LH6_1", + "CMT_OUT_FIFO_D82", + "CMT_FIFO_L_LOGIC_OUTS17_5", + "CMT_FIFO_L_FAN4_11", + "CMT_FIFO_NW4A0_7", + "CMT_FIFO_L_LOGIC_OUTS14_11", + "CMT_FIFO_WW4C1_0", + "CMT_FIFO_WL1END2_6", + "CMT_FIFO_EE4C0_0", + "CMT_FIFO_L_IMUX17_0", + "CMT_FIFO_EE4B3_9", + "CMT_FIFO_SW4A1_4", + "CMT_OUT_FIFO_D30", + "CMT_FIFO_L_IMUX30_5", + "CMT_FIFO_LH7_9", + "CMT_FIFO_L_BYP5_9", + "CMT_FIFO_LH7_11", + "CMT_FIFO_NE4C3_6", + "CMT_FIFO_L_BYP1_8", + "CMT_FIFO_L_IMUX12_10", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "CMT_FIFO_WW4B2_6", + "CMT_FIFO_NW4END0_10", + "CMT_FIFO_L_LOGIC_OUTS2_6", + "CMT_FIFO_WW4C2_2", + "CMT_FIFO_WW4C2_10", + "CMT_FIFO_WW4C1_7", + "CMT_FIFO_L_BYP1_0", + "CMT_FIFO_L_IMUX39_5", + "CMT_FIFO_SW2A2_3", + "CMT_FIFO_L_BYP7_1", + "CMT_FIFO_NE2A2_9", + "CMT_FIFO_L_BYP7_3", + "CMT_FIFO_NE4C3_1", + "CMT_FIFO_L_IMUX46_6", + "CMT_FIFO_EE4C2_7", + "CMT_FIFO_WW2END0_3", + "CMT_FIFO_EE4BEG3_4", + "CMT_FIFO_EE4A3_11", + "CMT_FIFO_WL1END1_1", + "CMT_FIFO_L_IMUX22_8", + "CMT_IN_FIFO_Q42", + "CMT_FIFO_NW2A1_4", + "CMT_FIFO_EE2BEG3_0", + "CMT_FIFO_SW4A1_0", + "CMT_FIFO_L_IMUX22_5", + "CMT_FIFO_EL1BEG1_5", + "CMT_FIFO_L_IMUX18_3", + "CMT_FIFO_L_IMUX41_6", + "CMT_FIFO_L_LOGIC_OUTS23_2", + "CMT_FIFO_LH11_5", + "CMT_FIFO_L_IMUX41_5", + "CMT_OUT_FIFO_Q83", + "CMT_FIFO_NW4END0_7", + "CMT_FIFO_L_IMUX32_5", + "CMT_IN_FIFO_Q07", + "CMT_FIFO_L_IMUX34_3", + "CMT_FIFO_NE2A1_8", + "CMT_FIFO_L_IMUX30_8", + "CMT_FIFO_L_IMUX12_11", + "CMT_FIFO_WW4C1_9", + "CMT_FIFO_SE2A2_7", + "CMT_FIFO_EE4A1_11", + "CMT_FIFO_SE2A3_7", + "CMT_FIFO_WR1END3_9", + "CMT_FIFO_EE4A1_6", + "CMT_FIFO_WR1END3_4", + "CMT_FIFO_WW4B0_8", + "CMT_FIFO_WW4END3_8", + "CMT_FIFO_L_IMUX35_7", + "CMT_FIFO_L_IMUX12_4", + "CMT_FIFO_EE4B2_1", + "CMT_FIFO_NW4A0_5", + "CMT_FIFO_L_LOGIC_OUTS3_0", + "CMT_OUT_FIFO_D05", + "CMT_FIFO_L_BYP7_2", + "CMT_FIFO_L_IMUX13_11", + "CMT_FIFO_NE4C0_2", + "CMT_FIFO_L_LOGIC_OUTS6_8", + "CMT_FIFO_WW4B2_8", + "CMT_FIFO_WW4END1_6", + "CMT_FIFO_WW4A1_6", + "CMT_FIFO_L_IMUX26_5", + "CMT_FIFO_WW2A2_3", + "CMT_FIFO_EL1BEG2_2", + "CMT_FIFO_L_IMUX25_9", + "CMT_FIFO_SE4C0_6", + "CMT_FIFO_L_IMUX36_8", + "CMT_FIFO_SE4C3_2", + "CMT_IN_FIFO_Q46", + "CMT_FIFO_NW4END2_5", + "CMT_OUT_FIFO_D97", + "CMT_FIFO_LH11_9", + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "CMT_FIFO_SE4C3_1", + "CMT_FIFO_SE2A3_1", + "CMT_FIFO_LH1_11", + "CMT_FIFO_L_IMUX24_11", + "CMT_FIFO_L_IMUX20_5", + "CMT_FIFO_NE4C0_7", + "CMT_FIFO_EE2A1_3", + "FIFO_DQS_IOTOPHASER_44", + "CMT_FIFO_L_LOGIC_OUTS8_9", + "CMT_FIFO_SE4C3_7", + "CMT_FIFO_LH4_11", + "CMT_FIFO_L_IMUX16_6", + "CMT_FIFO_SW4A2_3", + "CMT_FIFO_NE4BEG2_7", + "CMT_FIFO_L_IMUX19_3", + "CMT_FIFO_WW4B2_0", + "CMT_FIFO_EE2A1_0", + "CMT_FIFO_L_IMUX39_0", + "CMT_FIFO_L_IMUX8_2", + "CMT_FIFO_L_LOGIC_OUTS21_4", + "CMT_FIFO_L_FAN5_10", + "CMT_FIFO_NW4END0_3", + "CMT_FIFO_WR1END2_2", + "CMT_FIFO_L_IMUX10_5", + "CMT_FIFO_EE4A1_1", + "CMT_FIFO_WW2A1_5", + "CMT_FIFO_SW4A0_9", + "CMT_FIFO_L_LOGIC_OUTS2_7", + "CMT_FIFO_NW4A3_10", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "CMT_FIFO_ER1BEG3_9", + "CMT_FIFO_LH9_4", + "CMT_FIFO_SE4C0_3", + "CMT_FIFO_LH8_2", + "CMT_FIFO_LH6_9", + "CMT_FIFO_L_LOGIC_OUTS4_11", + "CMT_IN_FIFO_Q10", + "CMT_FIFO_WL1END3_7", + "CMT_FIFO_SE4C2_9", + "CMT_IN_FIFO_D30", + "CMT_IN_FIFO_D33", + "CMT_FIFO_L_IMUX19_4", + "CMT_FIFO_NE4C0_1", + "CMT_FIFO_WW2A0_2", + "CMT_FIFO_L_IMUX15_8", + "CMT_FIFO_L_IMUX9_5", + "CMT_FIFO_NE4C1_2", + "CMT_FIFO_EL1BEG3_2", + "CMT_FIFO_L_CTRL1_10", + "CMT_FIFO_LH3_0", + "CMT_FIFO_EE4BEG1_1", + "CMT_FIFO_EE4BEG1_5", + "CMT_FIFO_MONITOR_N_0", + "CMT_FIFO_L_IMUX17_6", + "CMT_FIFO_EL1BEG2_5", + "CMT_FIFO_L_IMUX18_11", + "CMT_FIFO_NE4C3_0", + "CMT_OUT_FIFO_D23", + "CMT_FIFO_NW4A3_5", + "CMT_FIFO_L_FAN3_8", + "CMT_FIFO_WW4B2_2", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_4", + "CMT_FIFO_L_IMUX7_10", + "CMT_FIFO_SW4END1_5", + "CMT_FIFO_WR1END0_10", + "CMT_FIFO_L_FAN2_4", + "CMT_FIFO_L_IMUX17_9", + "CMT_FIFO_EE4BEG1_9", + "CMT_IN_FIFO_D11", + "CMT_FIFO_L_IMUX26_9", + "CMT_FIFO_L_LOGIC_OUTS9_1", + "CMT_FIFO_L_BYP0_6", + "CMT_FIFO_SW4END0_1", + "CMT_FIFO_NW4END1_1", + "CMT_FIFO_L_IMUX44_2", + "CMT_FIFO_WL1END1_11", + "CMT_FIFO_MONITOR_N_8", + "CMT_FIFO_SW4A3_4", + "CMT_FIFO_SE4BEG3_6", + "CMT_FIFO_WW2A1_4", + "CMT_FIFO_LH6_7", + "CMT_FIFO_L_IMUX2_8", + "CMT_FIFO_L_BYP0_7", + "CMT_FIFO_EE4B3_7", + "CMT_FIFO_L_IMUX18_4", + "CMT_OUT_FIFO_Q56", + "CMT_FIFO_ER1BEG3_1", + "CMT_FIFO_SW4A2_11", + "CMT_FIFO_WW4B2_1", + "CMT_FIFO_WL1END2_9", + "CMT_FIFO_NW4END1_7", + "CMT_FIFO_L_IMUX46_10", + "CMT_FIFO_L_IMUX37_5", + "CMT_FIFO_NE4BEG1_5", + "CMT_FIFO_NE4C2_8", + "CMT_FIFO_WW2END1_11", + "CMT_FIFO_EE4C2_0", + "CMT_FIFO_EE2A3_9", + "CMT_FIFO_SW4END2_11", + "CMT_FIFO_L_LOGIC_OUTS14_5", + "CMT_FIFO_L_IMUX9_2", + "CMT_OUT_FIFO_D64", + "CMT_FIFO_L_FAN7_6", + "CMT_FIFO_L_LOGIC_OUTS4_8", + "CMT_FIFO_WW4A0_5", + "CMT_OUT_FIFO_D04", + "CMT_FIFO_L_IMUX25_2", + "CMT_FIFO_LH5_0", + "CMT_FIFO_L_IMUX15_3", + "CMT_FIFO_NW4END1_5", + "CMT_FIFO_EE2BEG1_9", + "CMT_FIFO_NW2A1_1", + "CMT_FIFO_SW2A3_10", + "CMT_FIFO_EE2BEG3_4", + "CMT_FIFO_EE2A2_5", + "CMT_IN_FIFO_SCANIN0", + "CMT_FIFO_L_LOGIC_OUTS2_9", + "CMT_FIFO_WR1END2_7", + "CMT_FIFO_ER1BEG1_2", + "CMT_FIFO_EL1BEG3_6", + "CMT_FIFO_NE4BEG3_5", + "CMT_FIFO_L_LOGIC_OUTS17_6", + "CMT_FIFO_L_IMUX5_2", + "CMT_FIFO_WR1END0_1", + "CMT_FIFO_WW2END3_3", + "CMT_FIFO_L_IMUX39_4", + "CMT_FIFO_L_LOGIC_OUTS7_9", + "CMT_FIFO_EE4BEG3_1", + "CMT_FIFO_WR1END3_7", + "CMT_FIFO_SE4C2_11", + "CMT_FIFO_SW2A3_2", + "CMT_FIFO_L_LOGIC_OUTS11_10", + "CMT_FIFO_L_IMUX34_7", + "CMT_FIFO_EL1BEG1_10", + "CMT_FIFO_L_BYP1_5", + "CMT_IN_FIFO_Q85", + "CMT_FIFO_WW4C0_10", + "CMT_FIFO_WW4B3_0", + "CMT_OUT_FIFO_D60", + "CMT_FIFO_L_IMUX6_4", + "CMT_FIFO_L_LOGIC_OUTS6_10", + "CMT_FIFO_L_LOGIC_OUTS2_4", + "CMT_OUT_FIFO_Q01", + "CMT_FIFO_NW2A1_3", + "CMT_OUT_FIFO_D54", + "CMT_FIFO_L_IMUX6_7", + "CMT_FIFO_L_IMUX0_8", + "CMT_FIFO_L_LOGIC_OUTS22_0", + "CMT_FIFO_NW4A0_8", + "CMT_FIFO_L_IMUX13_8", + "CMT_FIFO_WW4B0_10", + "CMT_FIFO_L_FAN1_8", + "CMT_OUT_FIFO_D03", + "CMT_FIFO_L_BYP7_5", + "CMT_FIFO_L_IMUX39_3", + "CMT_OUT_FIFO_D36", + "CMT_FIFO_WR1END1_0", + "CMT_FIFO_L_IMUX25_3", + "CMT_OUT_FIFO_D96", + "CMT_FIFO_WW4B0_7", + "CMT_FIFO_L_IMUX33_7", + "CMT_FIFO_ER1BEG2_1", + "CMT_FIFO_WR1END3_2", + "CMT_OUT_FIFO_D80", + "CMT_FIFO_WW2A0_1", + "CMT_FIFO_L_LOGIC_OUTS16_1", + "CMT_FIFO_L_IMUX33_11", + "CMT_FIFO_L_LOGIC_OUTS20_3", + "CMT_IN_FIFO_Q52", + "CMT_FIFO_SW4END1_6", + "CMT_FIFO_EE4B2_11", + "CMT_FIFO_L_IMUX3_4", + "CMT_FIFO_SW4END0_7", + "CMT_FIFO_WW4B3_8", + "CMT_IN_FIFO_Q27", + "CMT_IN_FIFO_ALMOSTEMPTY", + "CMT_FIFO_MONITOR_P_4", + "CMT_FIFO_L_LOGIC_OUTS4_1", + "CMT_FIFO_L_CLK0_5", + "CMT_FIFO_L_BYP3_5", + "CMT_FIFO_L_FAN2_7", + "CMT_FIFO_EE4BEG3_10", + "CMT_FIFO_NE2A3_2", + "CMT_FIFO_LH6_5", + "CMT_FIFO_WW2END1_3", + "CMT_FIFO_EE4A2_11", + "CMT_FIFO_EE4B3_8", + "CMT_FIFO_WL1END3_11", + "CMT_FIFO_EE2A2_0", + "CMT_FIFO_L_IMUX22_0", + "CMT_FIFO_NW4A2_7", + "CMT_FIFO_WW2A1_8", + "CMT_FIFO_NW4A0_1", + "CMT_FIFO_L_LOGIC_OUTS10_5", + "CMT_FIFO_L_IMUX25_11", + "CMT_FIFO_L_IMUX24_0", + "CMT_FIFO_NW4END0_2", + "CMT_FIFO_L_CTRL1_8", + "CMT_FIFO_LH12_4", + "CMT_FIFO_EL1BEG1_3", + "CMT_FIFO_SE4C2_0", + "CMT_FIFO_L_IMUX43_11", + "CMT_FIFO_L_LOGIC_OUTS10_11", + "CMT_FIFO_WW2END0_0", + "CMT_FIFO_L_IMUX6_8", + "CMT_FIFO_L_IMUX2_1", + "CMT_IN_FIFO_FULL", + "CMT_FIFO_L_IMUX13_2", + "CMT_FIFO_L_PHASER_RDENABLE", + "CMT_FIFO_EE4A0_3", + "CMT_FIFO_L_FAN7_3", + "CMT_FIFO_L_IMUX7_9", + "CMT_FIFO_L_IMUX18_1", + "CMT_FIFO_L_IMUX33_10", + "CMT_FIFO_L_IMUX9_7", + "CMT_OUT_FIFO_Q55", + "CMT_FIFO_EE4BEG1_6", + "CMT_FIFO_L_IMUX15_6", + "CMT_FIFO_EE4A3_7", + "CMT_FIFO_L_IMUX39_11", + "CMT_FIFO_L_IMUX20_2", + "CMT_FIFO_ER1BEG0_11", + "CMT_FIFO_ER1BEG0_1", + "CMT_FIFO_ER1BEG3_2", + "CMT_FIFO_L_FAN4_3", + "CMT_FIFO_L_FAN2_5", + "CMT_FIFO_NW4END3_7", + "CMT_FIFO_EE4C3_6", + "CMT_FIFO_L_IMUX35_1", + "CMT_FIFO_L_IMUX40_3", + "CMT_FIFO_WR1END2_8", + "CMT_FIFO_L_LOGIC_OUTS13_3", + "CMT_FIFO_L_IMUX20_7", + "CMT_FIFO_L_BYP6_1", + "CMT_FIFO_L_IMUX16_8", + "CMT_OUT_FIFO_D34", + "CMT_FIFO_L_FAN0_2", + "CMT_FIFO_L_LOGIC_OUTS16_7", + "CMT_FIFO_EE4BEG2_0", + "CMT_FIFO_L_BYP2_10", + "CMT_FIFO_NE2A1_11", + "CMT_FIFO_L_LOGIC_OUTS21_0", + "CMT_FIFO_SW2A2_2", + "CMT_FIFO_L_IMUX9_3", + "CMT_FIFO_L_IMUX40_7", + "CMT_FIFO_L_LOGIC_OUTS14_6", + "CMT_FIFO_NW4A3_9", + "CMT_FIFO_EE4B0_11", + "CMT_FIFO_WW2A2_8", + "CMT_FIFO_L_IMUX37_7", + "CMT_FIFO_WW4END1_1", + "CMT_FIFO_LH4_6", + "CMT_FIFO_EE4B1_3", + "CMT_FIFO_SE4C1_0", + "CMT_FIFO_L_IMUX35_5", + "CMT_FIFO_LH12_9", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "CMT_FIFO_WW4B0_6", + "CMT_FIFO_L_BYP2_1", + "CMT_FIFO_NW2A3_4", + "CMT_FIFO_WW4END2_11", + "CMT_FIFO_L_BYP4_7", + "CMT_FIFO_SE2A0_0", + "CMT_FIFO_WL1END3_6", + "CMT_FIFO_WW4C1_11", + "CMT_FIFO_SE4C1_4", + "CMT_OUT_FIFO_D90", + "CMT_IN_FIFO_Q60", + "CMT_FIFO_L_FAN3_3", + "CMT_FIFO_L_LOGIC_OUTS0_3", + "CMT_FIFO_L_IMUX28_8", + "CMT_FIFO_SE2A1_0", + "CMT_FIFO_L_LOGIC_OUTS7_11", + "CMT_FIFO_L_IMUX2_4", + "CMT_FIFO_LH1_1", + "CMT_FIFO_L_FAN0_9", + "CMT_FIFO_L_IMUX36_9", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "CMT_FIFO_L_LOGIC_OUTS16_10", + "CMT_FIFO_L_LOGIC_OUTS13_9", + "CMT_OUT_FIFO_Q71", + "CMT_IN_FIFO_Q86", + "CMT_IN_FIFO_D60", + "CMT_FIFO_EE2A3_0", + "CMT_FIFO_WW2END0_4", + "CMT_FIFO_WW4C2_5", + "CMT_FIFO_L_FAN6_7", + "CMT_IN_FIFO_Q47", + "CMT_FIFO_EE4A2_0", + "CMT_FIFO_WW4C3_11", + "CMT_FIFO_SE4C2_4", + "CMT_FIFO_L_LOGIC_OUTS19_1", + "CMT_FIFO_L_IMUX21_5", + "CMT_FIFO_L_IMUX33_9", + "CMT_FIFO_SE4BEG1_0", + "CMT_FIFO_L_BYP4_6", + "CMT_FIFO_SE4C3_10", + "CMT_FIFO_L_IMUX35_10", + "CMT_OUT_FIFO_Q41", + "CMT_FIFO_L_LOGIC_OUTS17_7", + "CMT_FIFO_WW4C2_6", + "CMT_FIFO_EE4C1_7", + "CMT_OUT_FIFO_D67", + "CMT_FIFO_ER1BEG0_2", + "CMT_FIFO_SW4END2_5", + "CMT_FIFO_LH2_0", + "CMT_FIFO_WL1END2_11", + "CMT_OUT_FIFO_D52", + "CMT_FIFO_L_IMUX39_9", + "CMT_FIFO_WW4A2_5", + "CMT_FIFO_WW4A0_4", + "CMT_FIFO_L_BYP6_6", + "CMT_FIFO_SW2A3_0", + "CMT_IN_FIFO_Q15", + "CMT_FIFO_L_IMUX46_11", + "CMT_IN_FIFO_Q34", + "CMT_OUT_FIFO_D56", + "CMT_FIFO_WW4A0_10", + "CMT_FIFO_L_IMUX11_11", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "CMT_FIFO_WW4C1_4", + "CMT_FIFO_WW4B0_11", + "CMT_FIFO_ER1BEG1_3", + "CMT_FIFO_WW2A1_11", + "CMT_FIFO_WW4END2_5", + "CMT_FIFO_L_LOGIC_OUTS22_9", + "CMT_FIFO_EE4C1_3", + "CMT_FIFO_NW4END1_4", + "CMT_FIFO_L_IMUX30_2", + "CMT_FIFO_L_IMUX47_7", + "CMT_FIFO_L_IMUX7_2", + "CMT_FIFO_NW4A2_5", + "CMT_FIFO_MONITOR_P_1", + "CMT_FIFO_L_IMUX8_5", + "CMT_FIFO_SE4BEG0_5", + "CMT_FIFO_L_IMUX36_2", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "CMT_FIFO_EE2A2_10", + "CMT_FIFO_WW4END0_3", + "CMT_FIFO_WR1END2_6", + "CMT_FIFO_L_IMUX47_6", + "CMT_FIFO_L_LOGIC_OUTS10_7", + "CMT_FIFO_LH12_3", + "CMT_OUT_FIFO_D06", + "CMT_FIFO_LH2_2", + "CMT_FIFO_L_FAN2_9", + "CMT_FIFO_L_LOGIC_OUTS19_5", + "CMT_FIFO_L_FAN5_2", + "CMT_FIFO_L_LOGIC_OUTS13_1", + "CMT_FIFO_L_IMUX0_2", + "CMT_FIFO_L_IMUX31_8", + "CMT_FIFO_NW4A1_11", + "CMT_FIFO_EE4B0_5", + "CMT_FIFO_SE4BEG2_6", + "CMT_FIFO_NW2A2_8", + "CMT_OUT_FIFO_Q20", + "CMT_IN_FIFO_Q30", + "CMT_FIFO_ER1BEG1_4", + "CMT_FIFO_WW4B3_11", + "CMT_FIFO_L_IMUX47_5", + "CMT_FIFO_SE4C2_1", + "CMT_FIFO_L_IMUX43_3", + "CMT_FIFO_L_CTRL1_4", + "CMT_FIFO_MONITOR_N_4", + "CMT_FIFO_NW2A0_9", + "CMT_FIFO_L_IMUX24_8", + "CMT_FIFO_L_LOGIC_OUTS16_2", + "CMT_FIFO_WW4A3_7", + "CMT_FIFO_SE4BEG0_8", + "CMT_FIFO_L_BYP0_9", + "CMT_FIFO_L_IMUX47_2", + "CMT_FIFO_LH2_3", + "CMT_FIFO_EE4A2_8", + "CMT_FIFO_WW4A2_9", + "CMT_FIFO_LH6_3", + "CMT_FIFO_L_PHASER_WRENABLE", + "CMT_FIFO_L_FAN1_6", + "CMT_OUT_FIFO_D07", + "CMT_FIFO_WW4A3_1", + "CMT_FIFO_L_IMUX38_0", + "CMT_IN_FIFO_D82", + "CMT_IN_FIFO_RDEN", + "CMT_FIFO_NE2A2_6", + "CMT_FIFO_L_BYP2_0", + "CMT_FIFO_L_LOGIC_OUTS18_3", + "CMT_FIFO_LH7_3", + "CMT_FIFO_NW2A3_6", + "CMT_OUT_FIFO_Q23", + "CMT_FIFO_L_CTRL1_2", + "CMT_FIFO_L_IMUX20_1", + "CMT_FIFO_L_IMUX5_8", + "CMT_FIFO_WW2END0_1", + "CMT_FIFO_WW4END1_2", + "CMT_FIFO_L_IMUX24_5", + "CMT_FIFO_L_IMUX12_7", + "CMT_FIFO_SE4BEG1_4", + "CMT_FIFO_SW4END2_10", + "CMT_FIFO_L_LOGIC_OUTS14_2", + "CMT_FIFO_L_LOGIC_OUTS9_11", + "CMT_FIFO_L_IMUX14_8", + "CMT_FIFO_WW4B2_4", + "CMT_FIFO_EE4C3_9", + "CMT_FIFO_EE4B2_2", + "CMT_FIFO_L_IMUX3_10", + "CMT_FIFO_L_CLK1_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_10", + "CMT_FIFO_L_IMUX5_4", + "CMT_FIFO_L_LOGIC_OUTS8_5", + "CMT_OUT_FIFO_Q22", + "CMT_FIFO_MONITOR_P_9", + "CMT_FIFO_L_IMUX40_11", + "CMT_FIFO_LH2_6", + "CMT_FIFO_L_IMUX3_1", + "CMT_FIFO_SE4BEG3_0", + "CMT_FIFO_L_LOGIC_OUTS11_8", + "CMT_FIFO_L_IMUX6_11", + "CMT_FIFO_L_IMUX44_7", + "CMT_FIFO_WW2END3_8", + "CMT_FIFO_NE2A0_1", + "CMT_FIFO_SE2A2_11", + "CMT_FIFO_L_IMUX18_2", + "CMT_FIFO_NW2A3_9", + "CMT_FIFO_SE4BEG2_9", + "CMT_FIFO_SW4END1_0", + "CMT_FIFO_L_LOGIC_OUTS15_9", + "CMT_FIFO_L_IMUX27_5", + "CMT_OUT_FIFO_Q60", + "CMT_FIFO_L_LOGIC_OUTS21_5", + "CMT_FIFO_L_LOGIC_OUTS1_7", + "CMT_FIFO_L_IMUX13_0", + "CMT_FIFO_EE2A0_0", + "CMT_FIFO_NW2A0_5", + "CMT_FIFO_NW4END1_10", + "CMT_FIFO_WW4A2_7", + "CMT_FIFO_SW4END2_4", + "CMT_FIFO_ER1BEG2_0", + "CMT_FIFO_L_IMUX21_9", + "CMT_IN_FIFO_SCANIN2", + "CMT_FIFO_L_LOGIC_OUTS3_7", + "CMT_FIFO_LH2_7", + "CMT_FIFO_SE4C3_9", + "CMT_FIFO_L_IMUX15_4", + "CMT_FIFO_NW4END2_3", + "CMT_FIFO_L_FAN3_1", + "CMT_FIFO_NE4C3_5", + "CMT_FIFO_L_IMUX10_9", + "CMT_FIFO_NE4C1_9", + "CMT_FIFO_L_IMUX14_9", + "CMT_FIFO_NW2A3_3", + "CMT_FIFO_L_LOGIC_OUTS10_2", + "CMT_FIFO_LH3_8", + "CMT_FIFO_WW2END2_10", + "CMT_FIFO_NW4END2_4", + "CMT_FIFO_EE4B1_8", + "CMT_FIFO_L_IMUX11_3", + "CMT_FIFO_L_FAN1_5", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_5", + "CMT_FIFO_NE4BEG0_2", + "CMT_FIFO_EE2A2_9", + "CMT_FIFO_SE2A2_4", + "CMT_FIFO_WW4END0_11", + "CMT_FIFO_EE4C0_5", + "CMT_FIFO_SW2A3_6", + "CMT_FIFO_NE4C1_5", + "CMT_FIFO_L_BYP4_9", + "CMT_IN_FIFO_Q82", + "CMT_IN_FIFO_Q94", + "CMT_FIFO_L_LOGIC_OUTS5_7", + "CMT_FIFO_WW2A3_5", + "CMT_FIFO_NE2A2_7", + "CMT_FIFO_L_LOGIC_OUTS15_3", + "CMT_FIFO_SE4C3_6", + "CMT_FIFO_EE2BEG2_1", + "CMT_FIFO_WW2A2_0", + "CMT_FIFO_WW2END3_10", + "CMT_FIFO_L_BYP7_8", + "CMT_FIFO_WW4A1_5", + "CMT_FIFO_NW2A2_6", + "CMT_OUT_FIFO_D42", + "CMT_FIFO_SW4A2_10", + "CMT_IN_FIFO_Q11", + "CMT_FIFO_L_FAN6_6", + "CMT_FIFO_L_IMUX1_6", + "CMT_FIFO_SW4A0_10", + "CMT_FIFO_L_BYP7_4", + "CMT_FIFO_EE4C2_11", + "CMT_OUT_FIFO_Q54", + "CMT_FIFO_L_IMUX44_1", + "CMT_FIFO_EE2A3_2", + "CMT_FIFO_SE4BEG3_4", + "CMT_FIFO_L_IMUX15_0", + "CMT_FIFO_L_IMUX27_3", + "CMT_FIFO_L_IMUX16_3", + "CMT_FIFO_NW2A2_3", + "CMT_FIFO_L_LOGIC_OUTS10_10", + "CMT_IN_FIFO_D02", + "CMT_FIFO_L_IMUX24_3", + "CMT_FIFO_L_BYP7_0", + "CMT_FIFO_L_IMUX35_4", + "CMT_FIFO_L_CLK1_5", + "CMT_FIFO_WW4A3_5", + "CMT_FIFO_L_FAN4_4", + "CMT_OUT_FIFO_D14", + "CMT_OUT_FIFO_D61", + "CMT_FIFO_L_LOGIC_OUTS11_5", + "CMT_FIFO_NE2A2_10", + "CMT_FIFO_L_BYP3_8", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_6", + "CMT_FIFO_WW4C3_0", + "CMT_FIFO_L_IMUX35_11", + "CMT_FIFO_NE4BEG3_6", + "CMT_FIFO_L_IMUX16_4", + "CMT_FIFO_L_IMUX40_0", + "CMT_FIFO_L_IMUX11_10", + "CMT_FIFO_L_IMUX35_6", + "CMT_FIFO_L_IMUX45_10", + "CMT_FIFO_WL1END2_7", + "CMT_FIFO_WW4B3_6", + "CMT_FIFO_L_IMUX42_2", + "CMT_FIFO_L_IMUX46_4", + "CMT_IN_FIFO_RESET", + "CMT_IN_FIFO_Q50", + "CMT_IN_FIFO_Q84", + "CMT_FIFO_L_BYP3_4", + "CMT_FIFO_NE4BEG0_8", + "CMT_FIFO_SE4BEG3_10", + "CMT_FIFO_L_IMUX28_5", + "CMT_FIFO_L_FAN1_2", + "CMT_FIFO_WW4C1_10", + "CMT_FIFO_NW4A1_7", + "CMT_OUT_FIFO_Q80", + "CMT_FIFO_SW4END3_7", + "CMT_FIFO_L_LOGIC_OUTS18_9", + "CMT_FIFO_NE4BEG3_10", + "CMT_FIFO_SW2A1_10", + "CMT_FIFO_L_CLK0_3", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "CMT_FIFO_L_LOGIC_OUTS0_7", + "CMT_FIFO_SE4BEG2_0", + "CMT_FIFO_L_LOGIC_OUTS18_10", + "CMT_FIFO_SW4END1_10", + "CMT_FIFO_L_IMUX23_3", + "CMT_FIFO_EE4A1_2", + "CMT_FIFO_L_IMUX25_6", + "CMT_IN_FIFO_D31", + "CMT_FIFO_SE4BEG2_11", + "CMT_FIFO_L_IMUX32_0", + "CMT_FIFO_WW4A1_11", + "CMT_FIFO_WW2END2_7", + "CMT_FIFO_L_BYP5_4", + "CMT_FIFO_L_LOGIC_OUTS3_9", + "CMT_FIFO_L_IMUX9_8", + "CMT_IN_FIFO_D42", + "CMT_IN_FIFO_D80", + "CMT_FIFO_L_IMUX15_10", + "CMT_FIFO_NE2A0_9", + "CMT_FIFO_WW4B0_1", + "CMT_OUT_FIFO_D21", + "CMT_FIFO_L_IMUX42_10", + "CMT_IN_FIFO_Q17", + "CMT_IN_FIFO_Q96", + "CMT_FIFO_SE4BEG1_5", + "CMT_FIFO_EE4C0_7", + "CMT_FIFO_L_IMUX8_0", + "CMT_FIFO_EE4B2_4", + "CMT_FIFO_NE2A3_9", + "CMT_FIFO_LH7_1", + "CMT_FIFO_L_IMUX45_0", + "CMT_IN_FIFO_SCANOUT3", + "CMT_FIFO_L_IMUX28_1", + "CMT_IN_FIFO_Q93", + "CMT_FIFO_L_IMUX34_5", + "CMT_FIFO_WL1END3_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_3", + "CMT_FIFO_LH7_6", + "CMT_FIFO_WW2END3_4", + "CMT_FIFO_L_IMUX5_6", + "CMT_FIFO_WW4A2_10", + "CMT_FIFO_L_IMUX41_10", + "CMT_FIFO_L_IMUX32_4", + "CMT_FIFO_L_CTRL1_5", + "FIFO_DQS_IOTOPHASER_6", + "CMT_FIFO_L_IMUX3_8", + "CMT_OUT_FIFO_D73", + "CMT_FIFO_ER1BEG2_6", + "CMT_FIFO_L_IMUX20_6", + "CMT_FIFO_SE4C1_5", + "CMT_FIFO_L_IMUX46_2", + "CMT_FIFO_L_IMUX34_1", + "CMT_OUT_FIFO_D12", + "FIFO_DQS_IOTOPHASER_55", + "CMT_FIFO_SW4A3_3", + "CMT_FIFO_WW4B0_3", + "CMT_FIFO_EE4B1_5", + "CMT_FIFO_EL1BEG1_7", + "CMT_FIFO_L_IMUX13_1", + "CMT_FIFO_NE4C3_2", + "CMT_IN_FIFO_WRCLK", + "CMT_FIFO_WW4A3_8", + "CMT_FIFO_WW4A0_0", + "CMT_FIFO_L_IMUX15_11", + "CMT_FIFO_EE4B0_6", + "CMT_FIFO_L_FAN2_1", + "CMT_FIFO_WR1END1_11", + "CMT_FIFO_LH1_4", + "CMT_FIFO_L_LOGIC_OUTS3_3", + "CMT_FIFO_L_FAN2_3", + "CMT_IN_FIFO_D70", + "CMT_FIFO_EE4B1_9", + "CMT_OUT_FIFO_Q66", + "CMT_FIFO_SE4BEG2_5", + "CMT_FIFO_EE4BEG1_0", + "CMT_FIFO_LH10_11", + "CMT_FIFO_MONITOR_P_5", + "CMT_FIFO_L_IMUX1_10", + "CMT_FIFO_NW4END3_0", + "CMT_FIFO_SE4BEG3_8", + "CMT_FIFO_L_IMUX43_6", + "CMT_FIFO_EE4A1_4", + "CMT_FIFO_EL1BEG1_8", + "CMT_FIFO_EE2A3_11", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "CMT_FIFO_L_LOGIC_OUTS3_10", + "CMT_FIFO_EE2A3_10", + "CMT_FIFO_L_IMUX35_8", + "CMT_FIFO_L_LOGIC_OUTS0_2", + "CMT_FIFO_L_CTRL1_0", + "CMT_FIFO_L_FAN4_7", + "CMT_FIFO_L_BYP5_6", + "CMT_FIFO_WW2A0_8", + "CMT_FIFO_LH3_4", + "CMT_FIFO_WW4A1_1", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "CMT_FIFO_ER1BEG3_0", + "CMT_FIFO_EE4B3_5", + "CMT_FIFO_L_LOGIC_OUTS20_9", + "CMT_FIFO_SW4A3_8", + "CMT_FIFO_L_LOGIC_OUTS13_10", + "CMT_FIFO_WW4C0_0", + "CMT_FIFO_L_BYP6_7", + "CMT_FIFO_EE2BEG2_6", + "CMT_FIFO_SW4A0_0", + "CMT_FIFO_WR1END1_9", + "CMT_FIFO_NE4C1_11", + "CMT_FIFO_WW4C0_11", + "CMT_OUT_FIFO_D75", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "CMT_FIFO_EL1BEG3_0", + "CMT_FIFO_L_IMUX41_9", + "CMT_OUT_FIFO_D47", + "CMT_FIFO_EL1BEG0_5", + "CMT_FIFO_EE2BEG1_6", + "CMT_FIFO_L_LOGIC_OUTS6_2", + "CMT_FIFO_L_FAN6_3", + "CMT_FIFO_SW4A1_2", + "CMT_FIFO_NE4C1_0", + "CMT_FIFO_NE2A2_8", + "CMT_FIFO_L_LOGIC_OUTS17_4", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "CMT_FIFO_SE4BEG0_1", + "CMT_FIFO_MONITOR_P_10", + "CMT_FIFO_LH3_5", + "CMT_FIFO_L_IMUX2_11", + "CMT_OUT_FIFO_Q33", + "CMT_FIFO_L_IMUX33_3", + "CMT_FIFO_WW4C2_3", + "CMT_FIFO_EE4A0_0", + "CMT_FIFO_EE4B3_6", + "CMT_FIFO_NW4END3_3", + "CMT_FIFO_L_CTRL0_11", + "CMT_FIFO_L_IMUX47_8", + "CMT_FIFO_LH1_3", + "CMT_FIFO_WW2A3_8", + "CMT_FIFO_L_BYP7_10", + "CMT_FIFO_EE2A2_7", + "CMT_IN_FIFO_D93", + "CMT_FIFO_LH11_2", + "CMT_FIFO_L_IMUX18_10", + "CMT_FIFO_WW4C0_2", + "CMT_FIFO_L_IMUX23_1", + "CMT_FIFO_NW4END1_2", + "CMT_FIFO_WL1END1_9", + "CMT_FIFO_LH10_5", + "CMT_FIFO_NE4C2_1", + "CMT_FIFO_L_LOGIC_OUTS8_6", + "CMT_FIFO_WW4C1_2", + "CMT_FIFO_L_IMUX11_5", + "CMT_FIFO_LH10_3", + "CMT_FIFO_WW2END1_8", + "CMT_FIFO_L_FAN6_10", + "CMT_FIFO_L_IMUX27_1", + "CMT_FIFO_EE4A0_9", + "CMT_FIFO_SE4C3_5", + "CMT_FIFO_NE4BEG2_0", + "CMT_FIFO_L_CTRL0_7", + "CMT_FIFO_L_LOGIC_OUTS16_0", + "CMT_FIFO_WW4END0_4", + "CMT_FIFO_L_IMUX19_0", + "CMT_FIFO_WR1END0_9", + "CMT_IN_FIFO_D12", + "CMT_FIFO_L_FAN0_4", + "CMT_FIFO_EE4BEG0_6", + "CMT_FIFO_L_LOGIC_OUTS21_9", + "CMT_FIFO_L_LOGIC_OUTS21_2", + "CMT_FIFO_SW4END0_9", + "CMT_FIFO_SW4A0_3", + "CMT_FIFO_WR1END2_1", + "CMT_FIFO_L_IMUX3_3", + "CMT_FIFO_SE4C1_10", + "CMT_FIFO_L_FAN0_3", + "CMT_FIFO_SW2A3_3", + "CMT_FIFO_L_IMUX4_9", + "CMT_FIFO_L_LOGIC_OUTS23_10", + "CMT_FIFO_L_IMUX26_3", + "CMT_FIFO_ER1BEG2_7", + "CMT_FIFO_SE2A2_1", + "CMT_FIFO_MONITOR_N_5", + "CMT_FIFO_NW4A2_10", + "CMT_FIFO_L_IMUX43_7", + "CMT_FIFO_SE2A0_2", + "CMT_FIFO_NE4C0_10", + "CMT_FIFO_L_IMUX28_3", + "CMT_FIFO_EE4C3_11", + "CMT_FIFO_SW4END1_7", + "CMT_FIFO_EE2A2_1", + "CMT_FIFO_MONITOR_P_3", + "CMT_FIFO_L_IMUX27_10", + "CMT_FIFO_L_BYP1_10", + "CMT_FIFO_SE4BEG2_7", + "CMT_IN_FIFO_D23", + "CMT_FIFO_L_BYP6_4", + "CMT_IN_FIFO_D72", + "CMT_FIFO_SE4C3_8", + "CMT_FIFO_L_IMUX29_2", + "CMT_OUT_FIFO_D94", + "CMT_OUT_FIFO_D26", + "CMT_FIFO_L_BYP7_6", + "CMT_FIFO_LH8_10", + "CMT_FIFO_NW4END3_10", + "CMT_FIFO_EE2BEG1_4", + "CMT_OUT_FIFO_Q00", + "CMT_FIFO_WW4A1_10", + "CMT_FIFO_L_LOGIC_OUTS10_3", + "CMT_FIFO_EE2BEG1_5", + "CMT_FIFO_EE2A1_7", + "CMT_FIFO_WW4END3_0", + "CMT_FIFO_WL1END3_10", + "CMT_IN_FIFO_Q40", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "CMT_FIFO_WW4END3_10", + "CMT_FIFO_L_LOGIC_OUTS12_11", + "FIFO_DQS_IOTOPHASER_2", + "CMT_FIFO_SW2A2_10", + "CMT_FIFO_WW4A1_3", + "CMT_FIFO_SW2A3_8", + "CMT_FIFO_EE4C0_9", + "CMT_FIFO_EE4B3_10", + "CMT_OUT_FIFO_SCANOUT2", + "CMT_FIFO_L_CTRL0_10", + "CMT_FIFO_LH3_9", + "CMT_FIFO_NE4BEG2_8", + "CMT_FIFO_WW2END2_11", + "CMT_FIFO_L_IMUX16_0", + "CMT_FIFO_NW2A2_2", + "CMT_FIFO_L_LOGIC_OUTS7_3", + "CMT_IN_FIFO_D83", + "CMT_FIFO_SE4C3_0", + "CMT_FIFO_SW4END1_11", + "CMT_FIFO_NE4BEG0_10", + "CMT_FIFO_L_IMUX46_7", + "CMT_FIFO_WW2A1_6", + "CMT_IN_FIFO_Q90", + "CMT_FIFO_NE4BEG1_11", + "CMT_FIFO_L_IMUX15_5", + "CMT_FIFO_L_LOGIC_OUTS21_11", + "CMT_FIFO_WR1END0_4", + "CMT_FIFO_WW4C1_3", + "CMT_FIFO_L_LOGIC_OUTS0_6", + "CMT_FIFO_WW4A0_11", + "CMT_FIFO_NW2A0_4", + "CMT_FIFO_L_IMUX20_3", + "CMT_FIFO_L_BYP3_11", + "CMT_FIFO_L_LOGIC_OUTS6_6", + "CMT_FIFO_L_IMUX23_8", + "CMT_FIFO_NE4BEG3_1", + "CMT_FIFO_NW2A2_11", + "CMT_FIFO_L_LOGIC_OUTS11_9", + "CMT_FIFO_EL1BEG0_1", + "CMT_FIFO_L_LOGIC_OUTS17_10", + "CMT_FIFO_L_LOGIC_OUTS20_8", + "CMT_FIFO_WR1END0_5", + "CMT_FIFO_WW4B1_4", + "CMT_FIFO_LH12_7", + "CMT_IN_FIFO_D21", + "CMT_FIFO_WW2A1_1", + "CMT_FIFO_WW4C3_1", + "CMT_FIFO_EE4A3_9", + "CMT_FIFO_SE2A3_10", + "CMT_FIFO_NW4END3_4", + "CMT_FIFO_L_IMUX38_11", + "CMT_FIFO_ER1BEG0_9", + "CMT_FIFO_SW4END3_6", + "CMT_FIFO_L_FAN7_2", + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "CMT_FIFO_NW4A2_3", + "CMT_FIFO_L_LOGIC_OUTS2_1", + "CMT_FIFO_L_BYP2_4", + "CMT_FIFO_SW4A2_6", + "CMT_FIFO_LH8_1", + "CMT_IN_FIFO_D32", + "CMT_FIFO_ER1BEG1_10", + "CMT_FIFO_WW2A0_3", + "CMT_FIFO_EE2BEG2_2", + "CMT_FIFO_NE4BEG2_2", + "CMT_FIFO_WW2A2_2", + "CMT_FIFO_L_FAN5_0", + "CMT_FIFO_EE2BEG0_10", + "CMT_FIFO_EE4C0_11", + "CMT_FIFO_EE4BEG2_9", + "FIFO_DQS_IOTOPHASER_5", + "CMT_FIFO_L_LOGIC_OUTS20_0", + "CMT_FIFO_EL1BEG3_1", + "CMT_FIFO_EE4C3_4", + "CMT_FIFO_L_LOGIC_OUTS22_11", + "CMT_FIFO_WW4END2_1", + "CMT_FIFO_NE4BEG0_3", + "CMT_FIFO_L_BYP4_3", + "CMT_FIFO_EE4A1_7", + "CMT_FIFO_WW4A0_8", + "CMT_FIFO_NW4END2_0", + "CMT_FIFO_SW4END1_2", + "CMT_FIFO_L_LOGIC_OUTS19_4", + "CMT_FIFO_NW4A2_4", + "CMT_FIFO_L_BYP0_8", + "CMT_FIFO_EE4BEG2_1", + "CMT_FIFO_L_LOGIC_OUTS4_9", + "CMT_FIFO_EE4BEG2_8", + "CMT_FIFO_NW4A3_7", + "CMT_FIFO_L_IMUX17_1", + "CMT_FIFO_L_IMUX9_1", + "CMT_FIFO_NW4A1_5", + "CMT_FIFO_WL1END0_0", + "CMT_IN_FIFO_D20", + "CMT_FIFO_L_LOGIC_OUTS11_2", + "CMT_FIFO_L_LOGIC_OUTS2_10", + "CMT_FIFO_L_IMUX30_0", + "CMT_FIFO_EE4A2_7", + "CMT_IN_FIFO_TESTWRITEDISB", + "CMT_FIFO_NE4C2_11", + "CMT_FIFO_L_IMUX34_6", + "CMT_FIFO_NW4A3_8", + "CMT_FIFO_L_IMUX17_2", + "CMT_FIFO_LH4_5", + "CMT_FIFO_L_LOGIC_OUTS0_11", + "CMT_FIFO_NE4BEG0_1", + "CMT_FIFO_EE2BEG1_7", + "CMT_FIFO_L_LOGIC_OUTS13_4", + "CMT_FIFO_LH5_1", + "CMT_FIFO_WW2END2_5", + "CMT_FIFO_LH1_8", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_0", + "CMT_FIFO_L_BYP1_1", + "CMT_FIFO_L_BYP5_11", + "CMT_FIFO_NW2A2_7", + "CMT_FIFO_L_LOGIC_OUTS1_2", + "CMT_FIFO_L_LOGIC_OUTS10_8", + "CMT_OUT_FIFO_D25", + "CMT_FIFO_WW2A0_7", + "CMT_OUT_FIFO_SCANIN3", + "CMT_FIFO_L_FAN4_6", + "CMT_FIFO_WW4A2_4", + "CMT_FIFO_LH8_3", + "CMT_FIFO_SW4A1_9", + "CMT_FIFO_L_FAN0_1", + "CMT_FIFO_WW4END2_4", + "CMT_IN_FIFO_Q16", + "CMT_FIFO_LH12_11", + "CMT_FIFO_L_LOGIC_OUTS1_9", + "CMT_FIFO_WW4B1_2", + "CMT_IN_FIFO_SCANIN1", + "CMT_FIFO_L_IMUX2_3", + "CMT_FIFO_L_LOGIC_OUTS9_7", + "CMT_FIFO_WW2A3_7", + "CMT_FIFO_SE4BEG1_1", + "CMT_FIFO_NE2A0_7", + "CMT_FIFO_NE4C2_4", + "CMT_FIFO_L_LOGIC_OUTS12_6", + "CMT_IN_FIFO_Q65", + "CMT_FIFO_NW4END2_10", + "CMT_FIFO_L_IMUX8_4", + "CMT_FIFO_EE4B3_0", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "CMT_FIFO_L_IMUX31_11", + "CMT_FIFO_L_LOGIC_OUTS15_11", + "CMT_FIFO_LH7_7", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "CMT_FIFO_EE4BEG0_0", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "CMT_FIFO_L_IMUX8_9", + "CMT_FIFO_L_IMUX29_6", + "CMT_FIFO_SW4END0_8", + "CMT_FIFO_L_IMUX37_1", + "CMT_OUT_FIFO_SCANIN2", + "CMT_FIFO_EE2BEG0_11", + "CMT_OUT_FIFO_D91", + "CMT_FIFO_SW4A0_1", + "CMT_FIFO_WW4A3_10", + "CMT_FIFO_L_LOGIC_OUTS6_4", + "CMT_FIFO_WW4END3_7", + "CMT_FIFO_NW4A3_0", + "CMT_FIFO_LH3_1", + "CMT_FIFO_LH5_3", + "CMT_FIFO_L_LOGIC_OUTS6_9", + "CMT_FIFO_L_IMUX7_5", + "CMT_FIFO_WW4END1_9", + "CMT_OUT_FIFO_Q50", + "CMT_FIFO_L_LOGIC_OUTS20_1", + "CMT_FIFO_LH7_2", + "CMT_FIFO_SE4BEG2_8", + "CMT_OUT_FIFO_ALMOSTFULL", + "CMT_FIFO_L_IMUX41_3", + "CMT_FIFO_SE4C0_1", + "CMT_FIFO_L_LOGIC_OUTS5_8", + "CMT_FIFO_SW2A2_1", + "CMT_FIFO_L_IMUX42_6", + "CMT_FIFO_EE4BEG0_1", + "CMT_FIFO_EE4BEG3_3", + "CMT_FIFO_L_IMUX17_7", + "CMT_FIFO_L_CTRL0_8", + "CMT_OUT_FIFO_D17", + "CMT_FIFO_L_LOGIC_OUTS22_1", + "CMT_FIFO_L_IMUX36_4", + "CMT_FIFO_NE2A0_11", + "CMT_FIFO_WW4END3_4", + "CMT_FIFO_SE2A1_11", + "CMT_FIFO_SE2A0_7", + "CMT_FIFO_WW4END1_11", + "CMT_FIFO_L_BYP5_10", + "CMT_FIFO_SW4END0_6", + "CMT_FIFO_SE4BEG1_8", + "CMT_FIFO_MONITOR_P_7", + "CMT_FIFO_L_LOGIC_OUTS19_0", + "CMT_OUT_FIFO_Q43", + "CMT_FIFO_NE4BEG3_0", + "CMT_FIFO_L_FAN1_11", + "CMT_OUT_FIFO_D43", + "CMT_FIFO_L_CLK0_1", + "CMT_FIFO_L_IMUX7_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "CMT_FIFO_SE4BEG2_4", + "CMT_FIFO_LH9_9", + "CMT_FIFO_L_IMUX30_1", + "CMT_FIFO_WW4A3_3", + "CMT_FIFO_WW2A2_1", + "CMT_FIFO_WW2A2_6", + "CMT_IN_FIFO_TESTMODEB", + "CMT_FIFO_WW4A2_3", + "CMT_FIFO_L_LOGIC_OUTS1_11", + "CMT_OUT_FIFO_D15", + "CMT_FIFO_WW4END2_10", + "CMT_FIFO_L_IMUX21_4", + "CMT_FIFO_SE2A0_4", + "CMT_FIFO_SW2A0_6", + "CMT_FIFO_WW4END0_7", + "CMT_FIFO_L_IMUX42_7", + "CMT_FIFO_EE4C3_2", + "CMT_FIFO_WR1END1_7", + "CMT_FIFO_NE4BEG1_2", + "CMT_FIFO_NE4BEG1_4", + "CMT_FIFO_L_IMUX12_8", + "CMT_FIFO_NE2A0_3", + "CMT_IN_FIFO_Q51", + "CMT_FIFO_L_IMUX22_3", + "CMT_FIFO_SW4END3_10", + "CMT_FIFO_NW2A1_11", + "CMT_FIFO_NE4BEG2_6", + "CMT_FIFO_WW2END2_8", + "CMT_FIFO_L_IMUX37_3", + "CMT_FIFO_EL1BEG1_11", + "CMT_FIFO_EE2BEG3_11", + "CMT_FIFO_L_LOGIC_OUTS17_8", + "CMT_FIFO_L_FAN2_8", + "CMT_IN_FIFO_D03", + "CMT_FIFO_SE4C2_6", + "CMT_FIFO_L_IMUX19_6", + "CMT_FIFO_SW2A1_6", + "CMT_FIFO_NE4C3_11", + "CMT_FIFO_L_IMUX32_9", + "CMT_FIFO_L_LOGIC_OUTS21_6", + "CMT_FIFO_NW4END3_1", + "CMT_FIFO_L_IMUX39_8", + "CMT_FIFO_SE2A2_6", + "CMT_FIFO_NW2A0_0", + "CMT_FIFO_L_IMUX36_0", + "CMT_FIFO_SE4BEG0_11", + "CMT_FIFO_L_IMUX13_3", + "CMT_FIFO_LH3_7", + "CMT_FIFO_EE2A0_11", + "CMT_FIFO_L_LOGIC_OUTS22_6", + "CMT_FIFO_L_LOGIC_OUTS11_6", + "CMT_FIFO_SE4BEG1_2", + "CMT_FIFO_WR1END2_5", + "CMT_FIFO_WL1END0_2", + "CMT_FIFO_EE4A3_0", + "CMT_FIFO_EE4BEG0_10", + "CMT_FIFO_NE4C2_3", + "CMT_FIFO_ER1BEG2_8", + "CMT_FIFO_L_LOGIC_OUTS13_8", + "CMT_FIFO_NE4C2_7", + "CMT_FIFO_EE4A0_5", + "CMT_FIFO_EL1BEG0_3", + "CMT_FIFO_WW4END0_1", + "CMT_FIFO_L_LOGIC_OUTS0_5", + "CMT_FIFO_L_CTRL0_6", + "CMT_FIFO_NE2A1_5", + "CMT_FIFO_L_IMUX12_1", + "CMT_FIFO_NE4C2_5", + "CMT_FIFO_WR1END2_3", + "CMT_FIFO_LH7_8", + "CMT_FIFO_WW4END3_2", + "CMT_FIFO_WW2END3_7", + "CMT_FIFO_SW4END3_0", + "CMT_FIFO_WR1END1_10", + "CMT_FIFO_WR1END3_11", + "CMT_FIFO_L_FAN6_4", + "CMT_FIFO_WW4C2_11", + "CMT_FIFO_L_BYP3_3", + "CMT_FIFO_EE2BEG1_8", + "CMT_IN_FIFO_Q00", + "CMT_OUT_FIFO_D74", + "CMT_FIFO_WW4END2_0", + "CMT_FIFO_L_IMUX15_7", + "CMT_FIFO_L_IMUX35_0", + "CMT_FIFO_L_LOGIC_OUTS4_0", + "CMT_FIFO_WW4A1_7", + "CMT_FIFO_SW4END0_11", + "CMT_FIFO_WW4B1_10", + "CMT_FIFO_L_IMUX46_3", + "CMT_IN_FIFO_Q44", + "CMT_FIFO_SW4A2_7", + "CMT_FIFO_L_IMUX26_8", + "CMT_FIFO_L_IMUX13_4", + "CMT_FIFO_SE4BEG2_1", + "CMT_FIFO_WW4END1_0", + "CMT_FIFO_L_FAN6_2", + "CMT_FIFO_LH12_2", + "CMT_FIFO_L_IMUX13_7", + "CMT_FIFO_L_LOGIC_OUTS16_4", + "CMT_FIFO_L_IMUX22_11", + "CMT_OUT_FIFO_SCANIN0", + "CMT_FIFO_L_IMUX27_7", + "CMT_FIFO_L_IMUX5_10", + "CMT_FIFO_WW4B3_7", + "CMT_FIFO_EE4C3_3", + "CMT_FIFO_LH2_11", + "CMT_FIFO_L_IMUX10_8", + "CMT_FIFO_WW2A2_9", + "CMT_FIFO_L_IMUX38_2", + "CMT_FIFO_WW4A1_0", + "CMT_FIFO_NE4C1_1", + "CMT_FIFO_L_FAN4_0", + "CMT_FIFO_L_FAN5_8", + "CMT_FIFO_L_IMUX47_0", + "CMT_FIFO_L_LOGIC_OUTS22_2", + "CMT_FIFO_L_IMUX6_6", + "CMT_FIFO_L_LOGIC_OUTS8_11", + "CMT_FIFO_L_LOGIC_OUTS13_0", + "CMT_FIFO_WW2END2_0", + "CMT_FIFO_LH5_8", + "CMT_FIFO_SE4BEG3_5", + "CMT_FIFO_L_IMUX18_7", + "CMT_FIFO_LH5_6", + "CMT_FIFO_L_LOGIC_OUTS3_4", + "CMT_OUT_FIFO_RDEN", + "CMT_FIFO_L_FAN5_3", + "CMT_FIFO_L_CLK1_9", + "CMT_FIFO_WW4A3_11", + "CMT_FIFO_L_IMUX16_10", + "CMT_FIFO_WW2A0_0", + "CMT_FIFO_EE4A2_4", + "CMT_FIFO_L_LOGIC_OUTS7_7", + "CMT_FIFO_WW2A3_0", + "CMT_FIFO_L_LOGIC_OUTS23_11", + "CMT_FIFO_L_IMUX6_9", + "CMT_FIFO_L_LOGIC_OUTS18_5", + "CMT_FIFO_L_IMUX36_1", + "CMT_FIFO_SW4A3_1", + "CMT_FIFO_SW4END3_11", + "CMT_FIFO_LH5_10", + "CMT_FIFO_L_IMUX17_5", + "CMT_OUT_FIFO_Q57", + "CMT_FIFO_L_IMUX4_3", + "CMT_IN_FIFO_Q33", + "CMT_FIFO_SW4A3_6", + "CMT_FIFO_WW4C1_8", + "CMT_OUT_FIFO_Q03", + "CMT_FIFO_WW2A3_1", + "CMT_FIFO_SW4END2_0", + "CMT_FIFO_L_LOGIC_OUTS4_7", + "CMT_FIFO_NW2A1_7", + "CMT_FIFO_L_FAN1_9", + "CMT_FIFO_L_IMUX13_10", + "CMT_FIFO_WL1END3_5", + "CMT_FIFO_L_LOGIC_OUTS7_8", + "CMT_FIFO_L_IMUX13_5", + "CMT_FIFO_EE2A0_8", + "CMT_FIFO_WW4C3_3", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "CMT_FIFO_NE2A1_6", + "CMT_FIFO_NE2A1_2", + "CMT_FIFO_L_IMUX12_9", + "CMT_FIFO_L_IMUX46_9", + "CMT_FIFO_WW4A2_11", + "CMT_FIFO_NE4C1_7", + "CMT_FIFO_L_LOGIC_OUTS14_10", + "CMT_FIFO_SW4A2_5", + "CMT_FIFO_L_IMUX31_5", + "CMT_FIFO_L_LOGIC_OUTS12_7", + "CMT_FIFO_ER1BEG1_7", + "CMT_FIFO_L_FAN2_6", + "CMT_FIFO_WW4END3_5", + "CMT_FIFO_NE4C0_3", + "CMT_FIFO_EL1BEG2_7", + "CMT_FIFO_L_FAN3_6", + "CMT_FIFO_SW2A2_9", + "CMT_FIFO_L_IMUX42_8", + "CMT_FIFO_EE4BEG3_0", + "CMT_FIFO_NE4C0_4", + "CMT_IN_FIFO_D62", + "CMT_FIFO_WW2END1_10", + "CMT_FIFO_L_IMUX32_2", + "CMT_FIFO_EE4C2_4", + "CMT_FIFO_SW4END0_2", + "CMT_FIFO_L_IMUX21_10", + "CMT_FIFO_NE4C2_9", + "CMT_FIFO_WL1END0_5", + "CMT_FIFO_NW4A2_8", + "CMT_FIFO_L_IMUX34_8", + "CMT_FIFO_SW4END0_5", + "CMT_FIFO_WW4END2_9", + "CMT_OUT_FIFO_WREN", + "CMT_FIFO_L_LOGIC_OUTS12_10", + "CMT_FIFO_WL1END2_2", + "CMT_FIFO_WW2A0_6", + "CMT_FIFO_L_IMUX0_0", + "CMT_FIFO_NW4A1_1", + "CMT_OUT_FIFO_D55", + "CMT_FIFO_EE2A3_5", + "CMT_FIFO_SW2A2_4", + "CMT_FIFO_L_IMUX46_8", + "CMT_FIFO_SE4BEG1_11", + "CMT_FIFO_NE4C3_9", + "CMT_FIFO_SE4BEG3_3", + "CMT_FIFO_EE4BEG0_5", + "CMT_FIFO_EE4BEG2_11", + "CMT_OUT_FIFO_D37", + "CMT_FIFO_LH8_9", + "CMT_FIFO_L_LOGIC_OUTS5_11", + "CMT_FIFO_NE4BEG1_9", + "CMT_FIFO_L_BYP2_2", + "CMT_FIFO_L_LOGIC_OUTS8_0", + "CMT_FIFO_WW4END0_10", + "CMT_FIFO_WW4A3_9", + "CMT_FIFO_ER1BEG2_4", + "CMT_FIFO_EL1BEG0_4", + "CMT_FIFO_L_LOGIC_OUTS19_11", + "CMT_FIFO_L_FAN3_2", + "CMT_FIFO_L_IMUX47_3", + "CMT_FIFO_EE2A3_7", + "CMT_FIFO_WR1END0_0", + "CMT_FIFO_L_LOGIC_OUTS11_1", + "CMT_FIFO_NE4C1_4", + "CMT_FIFO_L_LOGIC_OUTS12_5", + "CMT_FIFO_NE4BEG2_9", + "CMT_FIFO_EE2BEG3_1", + "CMT_FIFO_NE4BEG2_3", + "CMT_FIFO_SE2A1_9", + "CMT_FIFO_EE2A3_3", + "CMT_FIFO_L_BYP3_10", + "CMT_FIFO_NW4END1_6", + "CMT_FIFO_L_IMUX24_6", + "CMT_FIFO_L_IMUX38_1", + "CMT_FIFO_L_LOGIC_OUTS4_5", + "CMT_FIFO_EE2A1_1", + "CMT_FIFO_SW4A2_0", + "CMT_FIFO_EE4C0_4", + "CMT_FIFO_L_FAN7_1", + "CMT_FIFO_L_IMUX25_7", + "CMT_FIFO_WW2END1_9", + "CMT_FIFO_EL1BEG2_8", + "CMT_FIFO_EE4B0_2", + "CMT_FIFO_L_IMUX36_11", + "CMT_FIFO_L_IMUX6_1", + "CMT_IN_FIFO_Q77", + "CMT_FIFO_L_IMUX43_9", + "CMT_OUT_FIFO_D84", + "CMT_FIFO_EE4C0_8", + "CMT_IN_FIFO_Q23", + "CMT_FIFO_WL1END0_8", + "CMT_FIFO_L_LOGIC_OUTS9_5", + "CMT_IN_FIFO_Q31", + "CMT_FIFO_L_CLK0_7", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "CMT_FIFO_EE4C0_2", + "CMT_FIFO_L_LOGIC_OUTS6_7", + "CMT_FIFO_WW2A2_5", + "CMT_FIFO_L_IMUX25_4", + "CMT_FIFO_L_BYP6_9", + "CMT_FIFO_EE4A0_7", + "CMT_FIFO_EE2BEG2_10", + "CMT_FIFO_L_LOGIC_OUTS5_10", + "CMT_FIFO_EE2A3_1", + "CMT_FIFO_EL1BEG2_4", + "CMT_FIFO_WW4B1_8", + "CMT_FIFO_SE4C1_3", + "CMT_IN_FIFO_D71", + "CMT_FIFO_WW2END2_9", + "CMT_FIFO_SE4BEG0_6", + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "CMT_FIFO_L_IMUX42_0", + "CMT_IN_FIFO_Q62", + "CMT_FIFO_L_IMUX44_6", + "CMT_FIFO_WW4END1_5", + "CMT_FIFO_L_IMUX6_0", + "CMT_FIFO_L_IMUX32_6", + "CMT_FIFO_L_IMUX14_6", + "CMT_FIFO_NW4A0_9", + "CMT_FIFO_L_IMUX11_2", + "CMT_FIFO_EL1BEG3_7", + "CMT_FIFO_L_IMUX33_5", + "CMT_FIFO_L_IMUX32_3", + "CMT_FIFO_EE2A1_5", + "CMT_FIFO_NW2A0_8", + "CMT_OUT_FIFO_D45", + "CMT_FIFO_L_IMUX21_0", + "CMT_FIFO_WW4END2_8", + "CMT_FIFO_L_LOGIC_OUTS14_0", + "CMT_FIFO_L_IMUX19_10", + "CMT_FIFO_L_FAN7_4", + "CMT_FIFO_L_IMUX39_7", + "CMT_FIFO_L_LOGIC_OUTS22_8", + "CMT_OUT_FIFO_D71", + "CMT_FIFO_NE2A0_5", + "CMT_OUT_FIFO_Q70", + "CMT_FIFO_L_LOGIC_OUTS8_1", + "CMT_FIFO_WL1END3_3", + "CMT_FIFO_WW4C0_7", + "CMT_FIFO_L_FAN3_9", + "CMT_IN_FIFO_Q12", + "CMT_FIFO_L_IMUX43_4", + "CMT_FIFO_L_IMUX47_4", + "CMT_FIFO_WR1END3_8", + "CMT_FIFO_L_LOGIC_OUTS7_2", + "CMT_FIFO_L_BYP5_7", + "CMT_FIFO_L_IMUX38_9", + "CMT_FIFO_L_IMUX4_7", + "CMT_FIFO_EE2BEG2_0", + "CMT_FIFO_NE2A0_0", + "CMT_FIFO_L_LOGIC_OUTS18_6", + "CMT_FIFO_EE2BEG0_1", + "CMT_FIFO_EE4BEG1_3", + "CMT_FIFO_WW4A2_0", + "CMT_IN_FIFO_D00", + "CMT_FIFO_L_LOGIC_OUTS8_7", + "CMT_FIFO_SE4C0_4", + "CMT_FIFO_L_CLK1_0", + "CMT_FIFO_L_IMUX1_0", + "CMT_FIFO_SE2A1_2", + "CMT_FIFO_WW4A2_2", + "CMT_FIFO_SW2A0_2", + "CMT_FIFO_L_LOGIC_OUTS9_6", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "CMT_FIFO_L_IMUX16_2", + "CMT_FIFO_EE4BEG0_9", + "CMT_FIFO_EL1BEG1_2", + "CMT_FIFO_SE4BEG2_10", + "CMT_FIFO_EE4BEG0_11", + "CMT_FIFO_SE2A0_1", + "CMT_FIFO_L_IMUX43_0", + "CMT_FIFO_SW4END2_2", + "CMT_FIFO_NE4C1_6", + "CMT_FIFO_EL1BEG2_0", + "CMT_FIFO_LH1_10", + "CMT_IN_FIFO_D50", + "CMT_FIFO_WW4C0_8", + "CMT_FIFO_L_IMUX39_1", + "CMT_FIFO_NE2A3_1", + "CMT_FIFO_EE2BEG2_5", + "CMT_IN_FIFO_D13", + "CMT_FIFO_L_IMUX4_5", + "CMT_FIFO_NW4A3_11", + "CMT_FIFO_L_FAN7_5", + "CMT_FIFO_L_LOGIC_OUTS20_4", + "CMT_IN_FIFO_D81", + "CMT_FIFO_NW2A1_5", + "CMT_FIFO_L_IMUX31_3", + "CMT_FIFO_L_IMUX25_1", + "CMT_FIFO_SE2A2_2", + "CMT_FIFO_NW2A3_0", + "CMT_FIFO_WW2END0_10", + "CMT_FIFO_WW4END1_10", + "CMT_FIFO_SE4C3_3", + "CMT_FIFO_WL1END1_2", + "CMT_FIFO_EE4B2_0", + "CMT_FIFO_NE4BEG3_9", + "CMT_FIFO_L_LOGIC_OUTS10_1", + "CMT_FIFO_WL1END0_7", + "CMT_FIFO_L_IMUX23_7", + "CMT_FIFO_L_LOGIC_OUTS1_6", + "CMT_FIFO_L_IMUX15_1", + "CMT_FIFO_WW2A3_4", + "CMT_FIFO_L_BYP2_9", + "CMT_FIFO_L_LOGIC_OUTS1_4", + "CMT_FIFO_L_IMUX23_11", + "CMT_FIFO_NW4END1_11", + "CMT_FIFO_SW4END1_8", + "CMT_FIFO_NW4END2_11", + "CMT_IN_FIFO_Q21", + "CMT_FIFO_L_IMUX15_9", + "CMT_FIFO_L_IMUX41_2", + "CMT_FIFO_SE4C2_2", + "CMT_FIFO_EE4A0_1", + "CMT_FIFO_L_LOGIC_OUTS5_1", + "CMT_FIFO_EE2A1_8", + "CMT_FIFO_ER1BEG3_3", + "CMT_FIFO_L_IMUX7_3", + "CMT_IN_FIFO_Q54", + "CMT_FIFO_LH10_0", + "CMT_FIFO_L_FAN6_9", + "CMT_IN_FIFO_Q83", + "CMT_FIFO_EE4C0_10", + "CMT_OUT_FIFO_D70", + "CMT_FIFO_WL1END1_5", + "CMT_OUT_FIFO_D35", + "CMT_FIFO_L_IMUX6_10", + "CMT_FIFO_WW2A0_10", + "CMT_FIFO_ER1BEG0_8", + "CMT_FIFO_L_IMUX38_5", + "CMT_FIFO_SW2A0_9", + "CMT_FIFO_SE2A2_8", + "CMT_FIFO_WW4B1_11", + "CMT_FIFO_SW4END2_1", + "CMT_OUT_FIFO_Q53", + "CMT_FIFO_LH12_10", + "CMT_FIFO_WW4B3_4", + "CMT_IN_FIFO_D92", + "CMT_FIFO_L_IMUX42_3", + "CMT_FIFO_SW4A2_1", + "CMT_IN_FIFO_Q06", + "CMT_FIFO_NE4C0_11", + "CMT_FIFO_L_IMUX10_11", + "CMT_FIFO_NW2A1_10", + "CMT_FIFO_L_BYP4_1", + "CMT_FIFO_L_IMUX4_4", + "CMT_FIFO_LH10_9", + "CMT_FIFO_L_LOGIC_OUTS15_4", + "CMT_FIFO_L_IMUX9_9", + "CMT_FIFO_L_IMUX5_11", + "CMT_FIFO_WR1END2_10", + "CMT_OUT_FIFO_FULL", + "CMT_FIFO_L_IMUX45_6", + "CMT_FIFO_MONITOR_N_7", + "CMT_FIFO_EE4C1_8", + "CMT_FIFO_WW4B0_4", + "CMT_FIFO_L_CLK0_8", + "CMT_FIFO_WR1END1_6", + "CMT_FIFO_SW4END3_8", + "CMT_FIFO_WW2END0_6", + "CMT_FIFO_SW2A2_8", + "CMT_FIFO_LH9_11", + "CMT_FIFO_SW4A3_2", + "CMT_FIFO_WW4C0_1", + "CMT_FIFO_L_IMUX16_9", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "CMT_FIFO_ER1BEG0_4", + "CMT_FIFO_L_IMUX4_10", + "CMT_FIFO_WW4C3_8", + "CMT_FIFO_L_IMUX46_0", + "CMT_FIFO_L_LOGIC_OUTS2_3", + "CMT_FIFO_WL1END3_1", + "CMT_FIFO_L_FAN0_6", + "CMT_FIFO_WR1END3_10", + "CMT_FIFO_SE2A1_6", + "CMT_FIFO_SE2A0_11", + "CMT_FIFO_EE2A2_6", + "CMT_FIFO_L_BYP2_6", + "CMT_FIFO_ER1BEG2_5", + "CMT_FIFO_EE4B1_7", + "CMT_FIFO_NW4END0_4", + "CMT_FIFO_EE2A0_10", + "CMT_FIFO_L_IMUX1_1", + "CMT_FIFO_SW4A1_3", + "CMT_FIFO_SW2A2_11", + "CMT_FIFO_EE4BEG3_11", + "CMT_FIFO_NE2A3_6", + "CMT_FIFO_EE4B1_0", + "CMT_FIFO_L_IMUX34_9", + "CMT_FIFO_NW4A3_4", + "CMT_FIFO_L_IMUX19_2", + "CMT_FIFO_L_IMUX43_10", + "CMT_FIFO_WW2END1_6", + "CMT_FIFO_L_FAN0_11", + "CMT_OUT_FIFO_D53", + "CMT_FIFO_SW4END3_1", + "CMT_FIFO_L_IMUX21_3", + "CMT_FIFO_WW4B3_2", + "CMT_FIFO_NW2A0_6", + "CMT_FIFO_L_IMUX5_3", + "CMT_FIFO_SW4A0_5", + "CMT_FIFO_EE4A3_8", + "CMT_OUT_FIFO_D93", + "CMT_FIFO_L_LOGIC_OUTS5_4", + "CMT_FIFO_WW4A0_6", + "CMT_FIFO_L_IMUX7_6", + "CMT_FIFO_WW4C3_4", + "CMT_FIFO_L_BYP1_7", + "CMT_FIFO_EE2A0_1", + "CMT_FIFO_L_IMUX2_6", + "CMT_FIFO_L_IMUX28_9", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "CMT_FIFO_WW4A2_6", + "CMT_FIFO_L_IMUX36_6", + "CMT_FIFO_NW2A3_1", + "CMT_FIFO_WW4END0_6", + "CMT_FIFO_L_IMUX25_0", + "CMT_FIFO_L_IMUX47_11", + "CMT_FIFO_L_IMUX16_5", + "CMT_FIFO_L_IMUX25_8", + "CMT_FIFO_EL1BEG1_6", + "CMT_FIFO_NE4C0_6", + "CMT_FIFO_NE4BEG3_2", + "CMT_FIFO_SW2A3_11", + "CMT_FIFO_LH4_8", + "CMT_FIFO_LH5_5", + "CMT_FIFO_EE4C1_9", + "CMT_FIFO_L_IMUX6_2", + "CMT_FIFO_SE4C2_3", + "CMT_FIFO_L_LOGIC_OUTS15_1", + "CMT_FIFO_WW2A1_3", + "CMT_FIFO_NW4END2_2", + "CMT_FIFO_WR1END0_3", + "CMT_FIFO_L_LOGIC_OUTS8_10", + "CMT_IN_FIFO_Q80", + "CMT_FIFO_L_IMUX1_5", + "CMT_FIFO_NE2A3_7", + "CMT_FIFO_WR1END2_4", + "CMT_FIFO_SW4A2_4", + "CMT_FIFO_EE4A2_3", + "CMT_FIFO_NE4BEG3_7", + "CMT_FIFO_EE4BEG2_4", + "CMT_FIFO_LH9_1", + "CMT_FIFO_NW4A1_3", + "CMT_FIFO_MONITOR_N_9", + "CMT_FIFO_L_LOGIC_OUTS12_9", + "CMT_IN_FIFO_D66", + "CMT_FIFO_L_LOGIC_OUTS5_0", + "CMT_OUT_FIFO_D02", + "CMT_FIFO_LH11_0", + "CMT_FIFO_NE4C0_9", + "CMT_FIFO_NE2A3_0", + "CMT_FIFO_NE2A1_0", + "CMT_OUT_FIFO_D66", + "CMT_OUT_FIFO_Q64", + "CMT_FIFO_SE4C2_5", + "CMT_FIFO_L_IMUX12_0", + "CMT_FIFO_WW2END1_0", + "CMT_FIFO_NE2A2_1", + "CMT_FIFO_L_IMUX23_9", + "CMT_FIFO_L_LOGIC_OUTS13_2", + "CMT_IN_FIFO_D53", + "CMT_FIFO_EE4A0_10", + "CMT_FIFO_L_IMUX36_5", + "CMT_FIFO_L_IMUX17_11", + "CMT_FIFO_SW4END0_3", + "CMT_OUT_FIFO_Q40", + "CMT_FIFO_NW4A0_6", + "CMT_FIFO_ER1BEG2_11", + "CMT_FIFO_NW4A1_9", + "CMT_FIFO_EE2A2_4", + "CMT_OUT_FIFO_SCANOUT1", + "CMT_FIFO_L_IMUX45_11", + "CMT_IN_FIFO_Q32", + "CMT_IN_FIFO_D41", + "CMT_FIFO_WR1END0_11", + "CMT_FIFO_WW4END3_1", + "CMT_FIFO_SW2A1_5", + "CMT_FIFO_EL1BEG1_1", + "CMT_FIFO_L_IMUX29_5", + "CMT_FIFO_NW4END2_8", + "CMT_FIFO_EE4A3_5", + "CMT_OUT_FIFO_D77", + "CMT_FIFO_L_IMUX29_7", + "CMT_FIFO_L_LOGIC_OUTS12_3", + "CMT_FIFO_EE2A2_3", + "CMT_FIFO_LH7_10", + "CMT_FIFO_SW4A0_2", + "CMT_FIFO_EE4BEG3_6", + "CMT_FIFO_SW4A1_5", + "CMT_FIFO_L_IMUX29_11", + "CMT_FIFO_EE4B1_11", + "CMT_FIFO_WL1END2_8", + "CMT_FIFO_WW4END2_3", + "CMT_FIFO_L_CLK0_9", + "CMT_FIFO_L_LOGIC_OUTS11_3", + "CMT_FIFO_WL1END1_6", + "CMT_FIFO_EE4C3_7", + "CMT_FIFO_EL1BEG1_0", + "CMT_FIFO_LH1_7", + "CMT_FIFO_WW2END0_5", + "CMT_FIFO_WW2A0_11", + "CMT_FIFO_EE2BEG0_3", + "CMT_IN_FIFO_Q56", + "CMT_FIFO_SW4A3_9", + "CMT_IN_FIFO_Q37", + "CMT_FIFO_LH10_10", + "CMT_FIFO_L_LOGIC_OUTS8_8", + "CMT_FIFO_L_IMUX41_7", + "CMT_FIFO_L_IMUX1_11", + "CMT_FIFO_L_CTRL0_0", + "CMT_FIFO_WL1END2_10", + "CMT_FIFO_EE2A0_2", + "CMT_FIFO_NE4BEG0_7", + "CMT_FIFO_EL1BEG0_7", + "CMT_FIFO_EE2BEG1_10", + "CMT_OUT_FIFO_D63", + "CMT_FIFO_SE4C0_7", + "CMT_FIFO_L_IMUX30_11", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "CMT_FIFO_EE4BEG0_7", + "CMT_FIFO_L_FAN1_1", + "CMT_FIFO_EE4B2_10", + "CMT_FIFO_SW2A0_7", + "CMT_FIFO_WW2END1_7", + "CMT_FIFO_WL1END3_8", + "CMT_FIFO_SE2A0_6", + "CMT_FIFO_SW2A0_5", + "CMT_FIFO_EE4A3_10", + "CMT_OUT_FIFO_D41", + "CMT_FIFO_NE2A3_4", + "CMT_IN_FIFO_Q25", + "CMT_FIFO_LH6_8", + "CMT_FIFO_EE4A3_2", + "CMT_FIFO_L_CTRL0_9", + "CMT_FIFO_L_IMUX3_2", + "CMT_FIFO_LH4_9", + "CMT_FIFO_L_IMUX19_5", + "CMT_FIFO_SE4BEG3_2", + "CMT_FIFO_L_IMUX16_1", + "CMT_FIFO_NW2A2_5", + "CMT_FIFO_WW4B1_1", + "CMT_FIFO_WW2A3_10", + "CMT_FIFO_L_IMUX9_4", + "CMT_FIFO_WW2END0_8", + "CMT_FIFO_L_FAN7_7", + "CMT_FIFO_L_LOGIC_OUTS3_11", + "CMT_FIFO_NW4END0_1", + "CMT_FIFO_NE4C3_10", + "CMT_FIFO_LH12_5", + "CMT_FIFO_LH2_4", + "CMT_FIFO_NE4BEG3_8", + "CMT_FIFO_EE2A1_10", + "CMT_FIFO_WW4END0_0", + "CMT_OUT_FIFO_D83", + "CMT_FIFO_SE4BEG0_3", + "CMT_FIFO_SW4A1_1", + "CMT_FIFO_LH2_8", + "CMT_FIFO_EE4B2_3", + "CMT_FIFO_L_IMUX7_1", + "CMT_FIFO_L_LOGIC_OUTS14_9", + "CMT_FIFO_WW4C0_5", + "CMT_FIFO_L_LOGIC_OUTS13_11", + "CMT_FIFO_EL1BEG2_1", + "CMT_OUT_FIFO_TESTWRITEDISB", + "CMT_FIFO_WW2A1_10", + "CMT_FIFO_ER1BEG3_11", + "CMT_IN_FIFO_Q01", + "CMT_FIFO_SE2A3_9", + "CMT_OUT_FIFO_D16", + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "CMT_FIFO_L_BYP3_1", + "CMT_FIFO_L_CTRL1_1", + "CMT_FIFO_EL1BEG2_9", + "CMT_IN_FIFO_D40", + "CMT_FIFO_L_LOGIC_OUTS21_7", + "CMT_FIFO_L_IMUX37_8", + "CMT_FIFO_SW2A1_1", + "CMT_FIFO_L_IMUX47_10", + "CMT_FIFO_NE2A0_10", + "CMT_IN_FIFO_D63", + "CMT_FIFO_SW2A0_4", + "CMT_FIFO_ER1BEG2_2", + "CMT_FIFO_NW4A1_4", + "CMT_FIFO_MONITOR_P_0", + "CMT_FIFO_NE4BEG0_11", + "CMT_FIFO_NW2A1_8", + "CMT_FIFO_EL1BEG3_3", + "CMT_FIFO_EE4B2_6", + "CMT_FIFO_WW4END1_3", + "CMT_FIFO_NE4BEG1_8", + "CMT_FIFO_LH3_6", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "CMT_FIFO_L_IMUX22_1", + "CMT_FIFO_L_IMUX43_2", + "CMT_FIFO_L_IMUX45_1", + "CMT_IN_FIFO_D90", + "CMT_FIFO_SE4C2_7", + "CMT_FIFO_SW4A1_10", + "CMT_FIFO_EE4C2_9", + "CMT_FIFO_WW4B2_11", + "CMT_FIFO_NE4BEG3_3", + "CMT_FIFO_L_LOGIC_OUTS4_2", + "CMT_FIFO_LH11_10", + "CMT_FIFO_L_IMUX22_6", + "CMT_FIFO_L_LOGIC_OUTS3_6", + "CMT_FIFO_EE2A1_2", + "CMT_FIFO_L_LOGIC_OUTS23_1", + "CMT_FIFO_NW4END3_11", + "CMT_OUT_FIFO_Q67", + "CMT_IN_FIFO_Q81", + "CMT_FIFO_L_IMUX0_4", + "CMT_FIFO_EE4B3_4", + "CMT_FIFO_ER1BEG0_0", + "CMT_FIFO_L_LOGIC_OUTS9_2", + "CMT_FIFO_EE2A0_3", + "CMT_FIFO_EE2BEG0_9", + "CMT_FIFO_L_IMUX14_0", + "CMT_FIFO_L_FAN3_11", + "CMT_FIFO_EE4C3_1", + "CMT_FIFO_L_IMUX26_6", + "CMT_FIFO_WR1END1_3", + "CMT_FIFO_SW2A3_4", + "CMT_FIFO_EE4B0_10", + "CMT_FIFO_L_LOGIC_OUTS17_2", + "CMT_FIFO_EE4B3_3", + "CMT_OUT_FIFO_SCANENB", + "CMT_FIFO_SE4C2_8", + "CMT_FIFO_NW4END0_6", + "CMT_FIFO_SW2A0_0", + "CMT_FIFO_L_IMUX22_2", + "CMT_FIFO_L_LOGIC_OUTS16_3", + "CMT_FIFO_L_BYP5_3", + "CMT_FIFO_WW4END3_3", + "CMT_FIFO_SE4BEG3_11", + "CMT_FIFO_SE4C3_11", + "CMT_FIFO_WL1END2_0", + "CMT_FIFO_L_LOGIC_OUTS15_2", + "CMT_FIFO_L_BYP2_7", + "CMT_FIFO_L_IMUX10_1", + "CMT_FIFO_L_LOGIC_OUTS5_3", + "CMT_FIFO_L_FAN7_11", + "CMT_FIFO_EE4B1_4", + "CMT_FIFO_WW4B0_0", + "CMT_FIFO_L_LOGIC_OUTS7_5", + "CMT_FIFO_NW2A0_10", + "CMT_FIFO_WW2END3_1", + "CMT_FIFO_SW2A3_1", + "CMT_FIFO_ER1BEG1_6", + "CMT_FIFO_L_CLK0_10", + "CMT_FIFO_EE4BEG0_8", + "CMT_FIFO_L_LOGIC_OUTS6_5", + "CMT_FIFO_L_FAN4_5", + "CMT_FIFO_L_IMUX1_3", + "CMT_FIFO_WW4END3_11", + "CMT_FIFO_WL1END0_3", + "CMT_FIFO_EE2A2_8", + "CMT_FIFO_L_IMUX8_10", + "CMT_FIFO_SE2A0_10", + "CMT_FIFO_L_IMUX19_8", + "CMT_IN_FIFO_D43", + "CMT_FIFO_L_LOGIC_OUTS2_0", + "CMT_FIFO_L_LOGIC_OUTS20_5", + "CMT_FIFO_L_IMUX26_11", + "CMT_FIFO_SE4BEG1_9", + "CMT_FIFO_L_IMUX39_10", + "CMT_FIFO_WW2END2_3", + "CMT_FIFO_L_IMUX7_11", + "CMT_FIFO_LH1_2", + "CMT_FIFO_NW2A0_7", + "CMT_FIFO_EE4B3_11", + "CMT_FIFO_SW4END2_6", + "CMT_FIFO_EE4BEG3_2", + "CMT_FIFO_L_LOGIC_OUTS18_1", + "CMT_FIFO_WR1END3_1", + "CMT_FIFO_WW2A2_11", + "CMT_FIFO_L_LOGIC_OUTS5_2", + "CMT_OUT_FIFO_Q91", + "CMT_FIFO_L_IMUX28_6", + "CMT_FIFO_L_PHASER_RDCLK", + "CMT_FIFO_L_LOGIC_OUTS9_9", + "CMT_FIFO_ER1BEG3_7", + "CMT_FIFO_L_CLK1_7", + "CMT_FIFO_NW2A3_7", + "CMT_FIFO_L_LOGIC_OUTS13_6", + "CMT_FIFO_L_BYP5_5", + "CMT_IN_FIFO_Q35", + "CMT_FIFO_L_LOGIC_OUTS22_7", + "CMT_FIFO_L_LOGIC_OUTS1_0", + "CMT_FIFO_SE4BEG1_6", + "CMT_FIFO_WW4END0_5", + "CMT_FIFO_L_IMUX10_6", + "CMT_FIFO_L_LOGIC_OUTS7_10", + "CMT_FIFO_L_FAN6_1", + "CMT_FIFO_LH8_4", + "CMT_FIFO_L_IMUX33_4", + "CMT_FIFO_L_IMUX2_5", + "CMT_FIFO_L_LOGIC_OUTS20_11", + "CMT_FIFO_NE4C3_3", + "CMT_FIFO_L_LOGIC_OUTS4_3", + "CMT_FIFO_ER1BEG0_3", + "CMT_FIFO_NE4BEG2_1", + "CMT_FIFO_EE2A0_6", + "CMT_FIFO_WW4B1_6", + "CMT_FIFO_WL1END1_3", + "CMT_FIFO_EE4A2_6", + "CMT_FIFO_SW4END3_3", + "CMT_FIFO_NE4BEG0_4", + "CMT_OUT_FIFO_D65", + "CMT_FIFO_L_IMUX31_1", + "CMT_FIFO_WL1END0_1", + "CMT_FIFO_L_IMUX43_8", + "CMT_FIFO_NW4END3_9", + "CMT_FIFO_NE2A2_5", + "CMT_FIFO_WW4B3_10", + "CMT_FIFO_L_IMUX37_6", + "CMT_FIFO_L_FAN7_10", + "CMT_FIFO_L_IMUX27_2", + "CMT_FIFO_L_FAN6_5", + "CMT_FIFO_L_IMUX32_10", + "CMT_FIFO_L_IMUX28_2", + "CMT_FIFO_WW4C3_10", + "CMT_FIFO_NE2A1_9", + "CMT_FIFO_NW4A3_1", + "FIFO_DQS_IOTOPHASER_33", + "CMT_FIFO_L_IMUX24_1", + "CMT_FIFO_L_IMUX20_10", + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "CMT_FIFO_LH6_10", + "CMT_FIFO_WW2A0_5", + "CMT_IN_FIFO_D56", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_2", + "CMT_FIFO_L_BYP5_1", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "CMT_FIFO_EE4C2_10", + "CMT_FIFO_L_IMUX44_3", + "CMT_FIFO_L_IMUX12_2", + "CMT_FIFO_L_IMUX36_10", + "CMT_FIFO_EE2A1_9", + "CMT_OUT_FIFO_D40", + "CMT_FIFO_L_IMUX14_7", + "CMT_FIFO_NE4C2_10", + "CMT_FIFO_WW2END2_6", + "CMT_FIFO_L_IMUX47_9", + "CMT_FIFO_L_LOGIC_OUTS2_8", + "CMT_FIFO_L_BYP4_8", + "CMT_FIFO_EE2BEG2_11", + "CMT_FIFO_EE4B0_9", + "CMT_FIFO_EE2BEG0_7", + "CMT_FIFO_LH2_5", + "CMT_FIFO_L_LOGIC_OUTS14_4", + "CMT_FIFO_L_IMUX23_6", + "CMT_FIFO_L_IMUX14_3", + "CMT_FIFO_NE2A2_3", + "CMT_FIFO_L_IMUX26_10", + "CMT_FIFO_L_LOGIC_OUTS3_2", + "CMT_FIFO_EE2BEG3_2", + "CMT_IN_FIFO_Q61", + "CMT_FIFO_L_IMUX11_0", + "CMT_OUT_FIFO_WRCLK", + "CMT_FIFO_LH8_11", + "CMT_FIFO_L_IMUX0_10", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "CMT_FIFO_L_IMUX3_11", + "CMT_FIFO_EL1BEG0_9", + "CMT_FIFO_NE4BEG1_3", + "CMT_OUT_FIFO_D51", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "CMT_FIFO_L_IMUX47_1", + "CMT_FIFO_WW4END0_2", + "CMT_IN_FIFO_Q53", + "CMT_IN_FIFO_Q24", + "CMT_FIFO_WL1END2_1", + "CMT_FIFO_NE4C2_2", + "CMT_FIFO_LH9_7", + "CMT_FIFO_SE2A1_10", + "CMT_FIFO_L_IMUX44_5", + "CMT_IN_FIFO_Q71", + "CMT_FIFO_L_FAN7_0", + "CMT_FIFO_L_IMUX24_10", + "CMT_FIFO_L_LOGIC_OUTS22_3", + "CMT_OUT_FIFO_D46", + "CMT_FIFO_SE2A1_1", + "CMT_FIFO_L_IMUX11_7", + "CMT_FIFO_NW2A3_8", + "CMT_FIFO_WW2END2_4", + "CMT_IN_FIFO_RDCLK", + "CMT_FIFO_L_IMUX8_11", + "CMT_FIFO_SW4END0_10", + "CMT_FIFO_NW4END3_6", + "CMT_FIFO_NW2A2_0", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "CMT_FIFO_L_IMUX27_8", + "CMT_FIFO_EE4C1_5", + "CMT_FIFO_L_IMUX11_1", + "CMT_FIFO_SE2A1_7", + "CMT_FIFO_L_LOGIC_OUTS11_0", + "CMT_FIFO_L_FAN0_8", + "CMT_FIFO_NW4A1_8", + "CMT_FIFO_L_IMUX40_8", + "CMT_IN_FIFO_ALMOSTFULL", + "CMT_FIFO_EE2BEG3_9", + "CMT_FIFO_LH10_8", + "CMT_FIFO_EE4C0_6", + "CMT_FIFO_EL1BEG2_6", + "CMT_FIFO_L_IMUX1_9", + "CMT_OUT_FIFO_TESTMODEB", + "CMT_FIFO_LH4_1", + "CMT_FIFO_SE4C0_9", + "CMT_FIFO_L_LOGIC_OUTS18_2", + "CMT_IN_FIFO_Q92", + "CMT_IN_FIFO_TESTREADDISB", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "CMT_FIFO_L_CLK1_1", + "CMT_FIFO_LH11_7", + "CMT_FIFO_WR1END0_2", + "CMT_FIFO_EE4C2_6", + "CMT_FIFO_L_LOGIC_OUTS13_7", + "CMT_FIFO_L_BYP6_0", + "CMT_FIFO_L_CLK1_6", + "CMT_FIFO_L_LOGIC_OUTS12_1", + "CMT_FIFO_LH7_5", + "CMT_FIFO_L_IMUX38_8", + "CMT_FIFO_EE4C1_1", + "CMT_FIFO_L_CLK1_3", + "CMT_FIFO_L_IMUX7_7", + "CMT_FIFO_SW4A2_8", + "CMT_FIFO_EE2A2_11", + "CMT_FIFO_WW4C1_1", + "CMT_FIFO_L_FAN2_10", + "CMT_IN_FIFO_Q04", + "CMT_FIFO_L_FAN5_6", + "CMT_FIFO_L_IMUX8_8", + "CMT_FIFO_NE2A3_5", + "CMT_FIFO_SW2A0_8", + "CMT_FIFO_L_IMUX40_10", + "CMT_FIFO_SW2A1_3", + "CMT_FIFO_L_IMUX20_4", + "CMT_FIFO_L_IMUX33_2", + "CMT_FIFO_LH10_1", + "CMT_OUT_FIFO_D86", + "CMT_FIFO_L_IMUX16_7", + "CMT_FIFO_EL1BEG1_4", + "CMT_FIFO_L_LOGIC_OUTS20_6", + "CMT_FIFO_LH10_7", + "CMT_FIFO_L_CLK1_2", + "CMT_FIFO_L_LOGIC_OUTS1_8", + "CMT_IN_FIFO_Q87", + "CMT_FIFO_LH4_7", + "CMT_FIFO_L_IMUX29_0", + "CMT_FIFO_WL1END1_8", + "CMT_OUT_FIFO_D33", + "CMT_FIFO_EE4C2_2", + "CMT_IN_FIFO_D91", + "CMT_FIFO_L_IMUX14_2", + "CMT_FIFO_WL1END0_6", + "CMT_FIFO_SW4A1_11", + "CMT_FIFO_L_BYP5_2", + "CMT_FIFO_L_LOGIC_OUTS7_0", + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "CMT_FIFO_LH5_7", + "CMT_FIFO_L_IMUX24_4", + "CMT_FIFO_L_LOGIC_OUTS21_1", + "CMT_FIFO_L_IMUX27_0", + "CMT_FIFO_L_IMUX38_6", + "CMT_FIFO_L_IMUX17_3", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "CMT_FIFO_LH11_8", + "CMT_IN_FIFO_SCANOUT1", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_9", + "CMT_FIFO_L_IMUX43_1", + "CMT_FIFO_WW2END0_9", + "CMT_FIFO_EL1BEG0_0", + "CMT_FIFO_L_IMUX45_2", + "CMT_IN_FIFO_D22", + "CMT_FIFO_WR1END3_3", + "CMT_FIFO_EL1BEG0_6", + "CMT_FIFO_EE4A1_10", + "CMT_FIFO_L_IMUX20_9", + "CMT_FIFO_NW4A2_6", + "CMT_FIFO_L_LOGIC_OUTS2_5", + "CMT_FIFO_NW4A3_2", + "CMT_FIFO_L_IMUX39_6", + "CMT_FIFO_L_BYP4_5", + "CMT_FIFO_SE4BEG3_7", + "CMT_FIFO_MONITOR_P_6", + "CMT_FIFO_MONITOR_P_8", + "CMT_FIFO_EE4A2_1", + "CMT_FIFO_L_LOGIC_OUTS3_5", + "CMT_FIFO_LH11_1", + "CMT_FIFO_MONITOR_N_6", + "CMT_FIFO_LH12_1", + "CMT_FIFO_WW4B3_9", + "CMT_FIFO_WR1END1_2", + "CMT_FIFO_L_IMUX11_8", + "CMT_FIFO_EE2A1_4", + "CMT_FIFO_SE2A0_8", + "CMT_FIFO_SW4END0_0", + "CMT_FIFO_SE4BEG0_10", + "CMT_FIFO_L_BYP2_3", + "CMT_IN_FIFO_D55", + "CMT_FIFO_NW2A3_2", + "CMT_FIFO_SW4A3_7", + "CMT_FIFO_LH9_10", + "CMT_FIFO_L_IMUX44_9", + "CMT_FIFO_L_IMUX1_2", + "CMT_FIFO_L_IMUX4_0", + "CMT_FIFO_MONITOR_N_2", + "CMT_FIFO_L_LOGIC_OUTS20_10", + "CMT_FIFO_L_IMUX37_11", + "CMT_FIFO_L_IMUX25_5", + "CMT_FIFO_NE4BEG1_10", + "CMT_IN_FIFO_Q26", + "CMT_FIFO_L_LOGIC_OUTS8_4", + "CMT_FIFO_EE4BEG1_7", + "CMT_FIFO_L_IMUX17_4", + "CMT_FIFO_L_LOGIC_OUTS9_8", + "CMT_FIFO_L_BYP0_5", + "CMT_FIFO_SE4C0_0", + "CMT_IN_FIFO_Q20", + "CMT_FIFO_LH3_2", + "CMT_FIFO_EE2BEG3_5", + "CMT_IN_FIFO_Q66", + "CMT_FIFO_WL1END1_0", + "CMT_FIFO_EE4BEG0_3", + "CMT_FIFO_L_LOGIC_OUTS18_8", + "CMT_FIFO_WW4B2_5", + "CMT_FIFO_SW4END2_7", + "CMT_FIFO_NW4A1_10", + "CMT_FIFO_L_LOGIC_OUTS4_4", + "CMT_FIFO_L_FAN2_11", + "CMT_FIFO_L_FAN3_4", + "CMT_FIFO_WW4C2_9", + "CMT_FIFO_WR1END3_5", + "CMT_OUT_FIFO_Q72", + "CMT_FIFO_WW4B0_5", + "CMT_FIFO_L_IMUX37_4", + "CMT_FIFO_L_IMUX1_4", + "CMT_FIFO_L_LOGIC_OUTS15_10", + "CMT_FIFO_L_BYP0_2", + "CMT_FIFO_L_IMUX4_11", + "CMT_FIFO_WW2END1_4", + "CMT_IN_FIFO_D61", + "CMT_FIFO_L_IMUX41_8", + "CMT_FIFO_L_IMUX3_9", + "CMT_FIFO_WW4B1_3", + "FIFO_DQS_IOTOPHASER_11", + "CMT_FIFO_NW4A2_9", + "CMT_FIFO_L_LOGIC_OUTS1_5", + "CMT_FIFO_WR1END1_8", + "CMT_FIFO_L_LOGIC_OUTS17_3", + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "CMT_FIFO_L_CLK0_11", + "CMT_FIFO_LH1_9", + "CMT_FIFO_L_IMUX41_11", + "CMT_FIFO_L_IMUX8_1", + "CMT_FIFO_L_IMUX44_11", + "CMT_FIFO_NW2A3_11", + "CMT_OUT_FIFO_D72", + "CMT_FIFO_L_LOGIC_OUTS19_3", + "CMT_FIFO_L_IMUX33_0" + ], + "pips": { + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_8->CMT_OUT_FIFO_D65": { + "src_wire": "CMT_FIFO_L_IMUX5_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D65", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_6->CMT_OUT_FIFO_RESET": { + "src_wire": "CMT_FIFO_L_IMUX5_6", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RESET", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_9->CMT_OUT_FIFO_D72": { + "src_wire": "CMT_FIFO_L_IMUX39_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D72", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q95->CMT_FIFO_L_LOGIC_OUTS8_11": { + "src_wire": "CMT_IN_FIFO_Q95", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_5->CMT_OUT_FIFO_D51": { + "src_wire": "CMT_FIFO_L_IMUX21_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D51", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q36->CMT_FIFO_L_LOGIC_OUTS9_3": { + "src_wire": "CMT_IN_FIFO_Q36", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_11->CMT_OUT_FIFO_D97": { + "src_wire": "CMT_FIFO_L_IMUX6_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D97", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_2->CMT_OUT_FIFO_D22": { + "src_wire": "CMT_FIFO_L_IMUX39_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D22", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q47->CMT_FIFO_L_LOGIC_OUTS13_4": { + "src_wire": "CMT_IN_FIFO_Q47", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS20_8": { + "src_wire": "CMT_OUT_FIFO_Q63", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS20_3": { + "src_wire": "CMT_OUT_FIFO_Q33", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_2->CMT_OUT_FIFO_D27": { + "src_wire": "CMT_FIFO_L_IMUX6_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D27", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_6": { + "src_wire": "CMT_OUT_FIFO_EMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_8->CMT_OUT_FIFO_D64": { + "src_wire": "CMT_FIFO_L_IMUX12_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D64", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_9->CMT_IN_FIFO_D70": { + "src_wire": "CMT_FIFO_L_IMUX26_9", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D70", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS4_2": { + "src_wire": "CMT_IN_FIFO_Q21", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_9->CMT_IN_FIFO_D73": { + "src_wire": "CMT_FIFO_L_IMUX42_9", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D73", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_5->CMT_OUT_FIFO_D56": { + "src_wire": "CMT_FIFO_L_IMUX7_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D56", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS1_1": { + "src_wire": "CMT_IN_FIFO_Q13", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q04->CMT_FIFO_L_LOGIC_OUTS12_0": { + "src_wire": "CMT_IN_FIFO_Q04", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS11_3": { + "src_wire": "CMT_OUT_FIFO_Q32", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_2->CMT_OUT_FIFO_D20": { + "src_wire": "CMT_FIFO_L_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D20", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_1->CMT_OUT_FIFO_D11": { + "src_wire": "CMT_FIFO_L_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS22_11": { + "src_wire": "CMT_OUT_FIFO_Q90", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q25->CMT_FIFO_L_LOGIC_OUTS8_2": { + "src_wire": "CMT_IN_FIFO_Q25", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_8->CMT_OUT_FIFO_D67": { + "src_wire": "CMT_FIFO_L_IMUX6_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D67", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_11->CMT_OUT_FIFO_D90": { + "src_wire": "CMT_FIFO_L_IMUX28_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D90", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q97->CMT_FIFO_L_LOGIC_OUTS13_11": { + "src_wire": "CMT_IN_FIFO_Q97", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q07->CMT_FIFO_L_LOGIC_OUTS13_0": { + "src_wire": "CMT_IN_FIFO_Q07", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_PHASER_RDENABLE->CMT_OUT_FIFO_RDEN": { + "src_wire": "CMT_FIFO_L_PHASER_RDENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_2->CMT_IN_FIFO_D22": { + "src_wire": "CMT_FIFO_L_IMUX36_2", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D22", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS1_0": { + "src_wire": "CMT_IN_FIFO_Q03", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_3->CMT_OUT_FIFO_D33": { + "src_wire": "CMT_FIFO_L_IMUX38_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D33", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS1_2": { + "src_wire": "CMT_IN_FIFO_Q23", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_11->CMT_OUT_FIFO_D95": { + "src_wire": "CMT_FIFO_L_IMUX5_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D95", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS1_4": { + "src_wire": "CMT_IN_FIFO_Q43", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS19_0": { + "src_wire": "CMT_OUT_FIFO_Q01", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS19_2": { + "src_wire": "CMT_OUT_FIFO_Q21", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS0_10": { + "src_wire": "CMT_IN_FIFO_Q80", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_4->CMT_OUT_FIFO_D42": { + "src_wire": "CMT_FIFO_L_IMUX39_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D42", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS19_1": { + "src_wire": "CMT_OUT_FIFO_Q11", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS1_11": { + "src_wire": "CMT_IN_FIFO_Q93", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_2->CMT_OUT_FIFO_D25": { + "src_wire": "CMT_FIFO_L_IMUX5_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D25", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS1_8": { + "src_wire": "CMT_IN_FIFO_Q63", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_3->CMT_OUT_FIFO_D35": { + "src_wire": "CMT_FIFO_L_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D35", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_0->CMT_IN_FIFO_D00": { + "src_wire": "CMT_FIFO_L_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D00", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_1->CMT_OUT_FIFO_D13": { + "src_wire": "CMT_FIFO_L_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS5_5": { + "src_wire": "CMT_IN_FIFO_Q52", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS20_6": { + "src_wire": "CMT_OUT_FIFO_Q57", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q46->CMT_FIFO_L_LOGIC_OUTS9_4": { + "src_wire": "CMT_IN_FIFO_Q46", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q14->CMT_FIFO_L_LOGIC_OUTS12_1": { + "src_wire": "CMT_IN_FIFO_Q14", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q15->CMT_FIFO_L_LOGIC_OUTS8_1": { + "src_wire": "CMT_IN_FIFO_Q15", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_1->CMT_OUT_FIFO_D16": { + "src_wire": "CMT_FIFO_L_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D16", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_0->CMT_OUT_FIFO_D04": { + "src_wire": "CMT_FIFO_L_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D04", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_4->CMT_OUT_FIFO_D41": { + "src_wire": "CMT_FIFO_L_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D41", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS5_0": { + "src_wire": "CMT_IN_FIFO_Q02", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_11->CMT_IN_FIFO_D93": { + "src_wire": "CMT_FIFO_L_IMUX42_11", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D93", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q96->CMT_FIFO_L_LOGIC_OUTS9_11": { + "src_wire": "CMT_IN_FIFO_Q96", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_4->CMT_IN_FIFO_D42": { + "src_wire": "CMT_FIFO_L_IMUX36_4", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D42", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS4_10": { + "src_wire": "CMT_IN_FIFO_Q81", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_11->CMT_IN_FIFO_D92": { + "src_wire": "CMT_FIFO_L_IMUX36_11", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D92", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS19_4": { + "src_wire": "CMT_OUT_FIFO_Q41", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_2->CMT_OUT_FIFO_D24": { + "src_wire": "CMT_FIFO_L_IMUX12_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D24", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_3->CMT_IN_FIFO_D33": { + "src_wire": "CMT_FIFO_L_IMUX42_3", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D33", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS4_4": { + "src_wire": "CMT_IN_FIFO_Q41", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_3->CMT_OUT_FIFO_D32": { + "src_wire": "CMT_FIFO_L_IMUX39_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D32", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_7": { + "src_wire": "CMT_IN_FIFO_FULL", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_7": { + "src_wire": "CMT_IN_FIFO_ALMOSTEMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_CLK1_6->CMT_IN_FIFO_WRCLK": { + "src_wire": "CMT_FIFO_L_CLK1_6", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_4->CMT_OUT_FIFO_D45": { + "src_wire": "CMT_FIFO_L_IMUX5_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D45", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_8->CMT_OUT_FIFO_D61": { + "src_wire": "CMT_FIFO_L_IMUX21_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D61", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS19_3": { + "src_wire": "CMT_OUT_FIFO_Q31", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_8->CMT_IN_FIFO_D63": { + "src_wire": "CMT_FIFO_L_IMUX42_8", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D63", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_11->CMT_IN_FIFO_D90": { + "src_wire": "CMT_FIFO_L_IMUX26_11", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D90", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS8_8": { + "src_wire": "CMT_IN_FIFO_Q65", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_8->CMT_OUT_FIFO_D63": { + "src_wire": "CMT_FIFO_L_IMUX38_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D63", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_7->CMT_IN_FIFO_D64": { + "src_wire": "CMT_FIFO_L_IMUX26_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D64", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS4_0": { + "src_wire": "CMT_IN_FIFO_Q01", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_PHASER_WRENABLE->CMT_IN_FIFO_WREN": { + "src_wire": "CMT_FIFO_L_PHASER_WRENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WREN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_5->CMT_OUT_FIFO_D57": { + "src_wire": "CMT_FIFO_L_IMUX6_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D57", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS0_3": { + "src_wire": "CMT_IN_FIFO_Q30", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS22_0": { + "src_wire": "CMT_OUT_FIFO_Q00", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_9->CMT_IN_FIFO_D72": { + "src_wire": "CMT_FIFO_L_IMUX36_9", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D72", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_10->CMT_OUT_FIFO_D83": { + "src_wire": "CMT_FIFO_L_IMUX38_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D83", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS11_7": { + "src_wire": "CMT_OUT_FIFO_Q66", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS4_9": { + "src_wire": "CMT_IN_FIFO_Q71", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS13_8": { + "src_wire": "CMT_IN_FIFO_Q67", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS11_10": { + "src_wire": "CMT_OUT_FIFO_Q82", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS8_5": { + "src_wire": "CMT_IN_FIFO_Q55", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_5->CMT_IN_FIFO_D51": { + "src_wire": "CMT_FIFO_L_IMUX40_5", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D51", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_0->CMT_IN_FIFO_D03": { + "src_wire": "CMT_FIFO_L_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D03", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_9->CMT_OUT_FIFO_D77": { + "src_wire": "CMT_FIFO_L_IMUX6_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D77", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_6->CMT_IN_FIFO_D54": { + "src_wire": "CMT_FIFO_L_IMUX26_6", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D54", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_5->CMT_OUT_FIFO_D50": { + "src_wire": "CMT_FIFO_L_IMUX28_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D50", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS20_11": { + "src_wire": "CMT_OUT_FIFO_Q93", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q44->CMT_FIFO_L_LOGIC_OUTS12_4": { + "src_wire": "CMT_IN_FIFO_Q44", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS19_10": { + "src_wire": "CMT_OUT_FIFO_Q81", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_9->CMT_OUT_FIFO_D73": { + "src_wire": "CMT_FIFO_L_IMUX38_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D73", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_4->CMT_IN_FIFO_D41": { + "src_wire": "CMT_FIFO_L_IMUX40_4", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D41", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q06->CMT_FIFO_L_LOGIC_OUTS9_0": { + "src_wire": "CMT_IN_FIFO_Q06", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS20_10": { + "src_wire": "CMT_OUT_FIFO_Q83", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_10->CMT_OUT_FIFO_D87": { + "src_wire": "CMT_FIFO_L_IMUX6_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D87", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS22_3": { + "src_wire": "CMT_OUT_FIFO_Q30", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS5_2": { + "src_wire": "CMT_IN_FIFO_Q22", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q34->CMT_FIFO_L_LOGIC_OUTS12_3": { + "src_wire": "CMT_IN_FIFO_Q34", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_5->CMT_OUT_FIFO_D53": { + "src_wire": "CMT_FIFO_L_IMUX38_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D53", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS0_8": { + "src_wire": "CMT_IN_FIFO_Q60", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_4->CMT_IN_FIFO_D40": { + "src_wire": "CMT_FIFO_L_IMUX26_4", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D40", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_0->CMT_OUT_FIFO_D07": { + "src_wire": "CMT_FIFO_L_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D07", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_11->CMT_OUT_FIFO_D96": { + "src_wire": "CMT_FIFO_L_IMUX7_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D96", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS9_5": { + "src_wire": "CMT_IN_FIFO_Q56", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS11_2": { + "src_wire": "CMT_OUT_FIFO_Q22", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS22_4": { + "src_wire": "CMT_OUT_FIFO_Q40", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_3->CMT_OUT_FIFO_D30": { + "src_wire": "CMT_FIFO_L_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D30", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_4->CMT_OUT_FIFO_D43": { + "src_wire": "CMT_FIFO_L_IMUX38_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D43", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_4->CMT_OUT_FIFO_D44": { + "src_wire": "CMT_FIFO_L_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D44", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS11_6": { + "src_wire": "CMT_OUT_FIFO_Q56", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS20_7": { + "src_wire": "CMT_OUT_FIFO_Q67", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_5->CMT_OUT_FIFO_D54": { + "src_wire": "CMT_FIFO_L_IMUX12_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D54", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS20_4": { + "src_wire": "CMT_OUT_FIFO_Q43", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_7": { + "src_wire": "CMT_IN_FIFO_ALMOSTFULL", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_0->CMT_OUT_FIFO_D00": { + "src_wire": "CMT_FIFO_L_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D00", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q45->CMT_FIFO_L_LOGIC_OUTS8_4": { + "src_wire": "CMT_IN_FIFO_Q45", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS0_2": { + "src_wire": "CMT_IN_FIFO_Q20", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_PHASER_RDCLK->CMT_OUT_FIFO_RDCLK": { + "src_wire": "CMT_FIFO_L_PHASER_RDCLK", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS4_5": { + "src_wire": "CMT_IN_FIFO_Q51", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS5_4": { + "src_wire": "CMT_IN_FIFO_Q42", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS22_6": { + "src_wire": "CMT_OUT_FIFO_Q54", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_7->CMT_IN_FIFO_D67": { + "src_wire": "CMT_FIFO_L_IMUX42_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D67", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS11_5": { + "src_wire": "CMT_OUT_FIFO_Q52", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_0->CMT_IN_FIFO_D02": { + "src_wire": "CMT_FIFO_L_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D02", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q87->CMT_FIFO_L_LOGIC_OUTS13_10": { + "src_wire": "CMT_IN_FIFO_Q87", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_10->CMT_IN_FIFO_D82": { + "src_wire": "CMT_FIFO_L_IMUX36_10", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D82", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_5->CMT_OUT_FIFO_D55": { + "src_wire": "CMT_FIFO_L_IMUX5_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D55", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_1->CMT_IN_FIFO_D11": { + "src_wire": "CMT_FIFO_L_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q85->CMT_FIFO_L_LOGIC_OUTS8_10": { + "src_wire": "CMT_IN_FIFO_Q85", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_2->CMT_IN_FIFO_D20": { + "src_wire": "CMT_FIFO_L_IMUX26_2", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D20", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_8->CMT_IN_FIFO_D62": { + "src_wire": "CMT_FIFO_L_IMUX36_8", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D62", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_4->CMT_OUT_FIFO_D46": { + "src_wire": "CMT_FIFO_L_IMUX7_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D46", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_1->CMT_OUT_FIFO_D17": { + "src_wire": "CMT_FIFO_L_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D17", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_9->CMT_OUT_FIFO_D75": { + "src_wire": "CMT_FIFO_L_IMUX5_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D75", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_3->CMT_IN_FIFO_D30": { + "src_wire": "CMT_FIFO_L_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D30", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_1->CMT_IN_FIFO_D10": { + "src_wire": "CMT_FIFO_L_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_0->CMT_IN_FIFO_D01": { + "src_wire": "CMT_FIFO_L_IMUX40_0", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D01", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS22_10": { + "src_wire": "CMT_OUT_FIFO_Q80", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS5_11": { + "src_wire": "CMT_IN_FIFO_Q92", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_1->CMT_IN_FIFO_D13": { + "src_wire": "CMT_FIFO_L_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS12_5": { + "src_wire": "CMT_IN_FIFO_Q54", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q84->CMT_FIFO_L_LOGIC_OUTS12_10": { + "src_wire": "CMT_IN_FIFO_Q84", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS22_7": { + "src_wire": "CMT_OUT_FIFO_Q64", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q75->CMT_FIFO_L_LOGIC_OUTS8_9": { + "src_wire": "CMT_IN_FIFO_Q75", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q24->CMT_FIFO_L_LOGIC_OUTS12_2": { + "src_wire": "CMT_IN_FIFO_Q24", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS0_4": { + "src_wire": "CMT_IN_FIFO_Q40", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS20_5": { + "src_wire": "CMT_OUT_FIFO_Q53", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_CLK0_7->CMT_OUT_FIFO_RDCLK": { + "src_wire": "CMT_FIFO_L_CLK0_7", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_10->CMT_OUT_FIFO_D85": { + "src_wire": "CMT_FIFO_L_IMUX5_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D85", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_8->CMT_IN_FIFO_D60": { + "src_wire": "CMT_FIFO_L_IMUX26_8", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D60", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_7": { + "src_wire": "CMT_IN_FIFO_EMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_10->CMT_IN_FIFO_D80": { + "src_wire": "CMT_FIFO_L_IMUX26_10", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D80", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS1_3": { + "src_wire": "CMT_IN_FIFO_Q33", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_9->CMT_OUT_FIFO_D70": { + "src_wire": "CMT_FIFO_L_IMUX28_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D70", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS19_8": { + "src_wire": "CMT_OUT_FIFO_Q61", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS0_0": { + "src_wire": "CMT_IN_FIFO_Q00", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_6": { + "src_wire": "CMT_OUT_FIFO_ALMOSTFULL", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS11_8": { + "src_wire": "CMT_OUT_FIFO_Q62", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_1->CMT_IN_FIFO_D12": { + "src_wire": "CMT_FIFO_L_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_6": { + "src_wire": "CMT_OUT_FIFO_ALMOSTEMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS22_5": { + "src_wire": "CMT_OUT_FIFO_Q50", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_3->CMT_IN_FIFO_D32": { + "src_wire": "CMT_FIFO_L_IMUX36_3", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D32", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_11->CMT_OUT_FIFO_D94": { + "src_wire": "CMT_FIFO_L_IMUX12_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D94", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_5->CMT_IN_FIFO_D52": { + "src_wire": "CMT_FIFO_L_IMUX36_5", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D52", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_8->CMT_IN_FIFO_D61": { + "src_wire": "CMT_FIFO_L_IMUX40_8", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D61", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q37->CMT_FIFO_L_LOGIC_OUTS13_3": { + "src_wire": "CMT_IN_FIFO_Q37", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS5_3": { + "src_wire": "CMT_IN_FIFO_Q32", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_10->CMT_OUT_FIFO_D86": { + "src_wire": "CMT_FIFO_L_IMUX7_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D86", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_5->CMT_IN_FIFO_D50": { + "src_wire": "CMT_FIFO_L_IMUX26_5", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D50", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_7->CMT_IN_FIFO_RDEN": { + "src_wire": "CMT_FIFO_L_IMUX7_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_RDEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_8->CMT_OUT_FIFO_D62": { + "src_wire": "CMT_FIFO_L_IMUX39_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D62", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_3->CMT_OUT_FIFO_D37": { + "src_wire": "CMT_FIFO_L_IMUX6_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D37", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_3->CMT_OUT_FIFO_D34": { + "src_wire": "CMT_FIFO_L_IMUX12_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D34", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS19_11": { + "src_wire": "CMT_OUT_FIFO_Q91", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_2->CMT_OUT_FIFO_D23": { + "src_wire": "CMT_FIFO_L_IMUX38_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D23", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS11_0": { + "src_wire": "CMT_OUT_FIFO_Q02", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS20_1": { + "src_wire": "CMT_OUT_FIFO_Q13", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_1->CMT_OUT_FIFO_D14": { + "src_wire": "CMT_FIFO_L_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS0_9": { + "src_wire": "CMT_IN_FIFO_Q70", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_6": { + "src_wire": "CMT_OUT_FIFO_FULL", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS4_3": { + "src_wire": "CMT_IN_FIFO_Q31", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS0_11": { + "src_wire": "CMT_IN_FIFO_Q90", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS0_5": { + "src_wire": "CMT_IN_FIFO_Q50", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_2->CMT_OUT_FIFO_D26": { + "src_wire": "CMT_FIFO_L_IMUX7_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D26", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q27->CMT_FIFO_L_LOGIC_OUTS13_2": { + "src_wire": "CMT_IN_FIFO_Q27", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_10->CMT_IN_FIFO_D83": { + "src_wire": "CMT_FIFO_L_IMUX42_10", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D83", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_10->CMT_OUT_FIFO_D82": { + "src_wire": "CMT_FIFO_L_IMUX39_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D82", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q16->CMT_FIFO_L_LOGIC_OUTS9_1": { + "src_wire": "CMT_IN_FIFO_Q16", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q17->CMT_FIFO_L_LOGIC_OUTS13_1": { + "src_wire": "CMT_IN_FIFO_Q17", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_11->CMT_OUT_FIFO_D93": { + "src_wire": "CMT_FIFO_L_IMUX38_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D93", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_PHASER_WRCLK->CMT_IN_FIFO_WRCLK": { + "src_wire": "CMT_FIFO_L_PHASER_WRCLK", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_1->CMT_OUT_FIFO_D15": { + "src_wire": "CMT_FIFO_L_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS5_10": { + "src_wire": "CMT_IN_FIFO_Q82", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS1_9": { + "src_wire": "CMT_IN_FIFO_Q73", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS9_8": { + "src_wire": "CMT_IN_FIFO_Q66", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q77->CMT_FIFO_L_LOGIC_OUTS13_9": { + "src_wire": "CMT_IN_FIFO_Q77", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_2->CMT_IN_FIFO_D23": { + "src_wire": "CMT_FIFO_L_IMUX42_2", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D23", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS22_2": { + "src_wire": "CMT_OUT_FIFO_Q20", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_3->CMT_IN_FIFO_D31": { + "src_wire": "CMT_FIFO_L_IMUX40_3", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D31", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q26->CMT_FIFO_L_LOGIC_OUTS9_2": { + "src_wire": "CMT_IN_FIFO_Q26", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_0->CMT_OUT_FIFO_D02": { + "src_wire": "CMT_FIFO_L_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D02", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q05->CMT_FIFO_L_LOGIC_OUTS8_0": { + "src_wire": "CMT_IN_FIFO_Q05", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_1->CMT_OUT_FIFO_D12": { + "src_wire": "CMT_FIFO_L_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS5_1": { + "src_wire": "CMT_IN_FIFO_Q12", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS1_5": { + "src_wire": "CMT_IN_FIFO_Q53", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS5_8": { + "src_wire": "CMT_IN_FIFO_Q62", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_10->CMT_OUT_FIFO_D84": { + "src_wire": "CMT_FIFO_L_IMUX12_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D84", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS12_8": { + "src_wire": "CMT_IN_FIFO_Q64", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS13_5": { + "src_wire": "CMT_IN_FIFO_Q57", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_6->CMT_OUT_FIFO_WREN": { + "src_wire": "CMT_FIFO_L_IMUX6_6", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_WREN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_0->CMT_OUT_FIFO_D06": { + "src_wire": "CMT_FIFO_L_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D06", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_7->CMT_IN_FIFO_D66": { + "src_wire": "CMT_FIFO_L_IMUX36_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D66", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_5->CMT_IN_FIFO_D53": { + "src_wire": "CMT_FIFO_L_IMUX42_5", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D53", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS11_1": { + "src_wire": "CMT_OUT_FIFO_Q12", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS0_1": { + "src_wire": "CMT_IN_FIFO_Q10", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_9->CMT_OUT_FIFO_D71": { + "src_wire": "CMT_FIFO_L_IMUX21_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D71", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_0->CMT_OUT_FIFO_D05": { + "src_wire": "CMT_FIFO_L_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D05", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_6->CMT_IN_FIFO_D55": { + "src_wire": "CMT_FIFO_L_IMUX40_6", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D55", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_10->CMT_OUT_FIFO_D81": { + "src_wire": "CMT_FIFO_L_IMUX21_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D81", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_9->CMT_OUT_FIFO_D76": { + "src_wire": "CMT_FIFO_L_IMUX7_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D76", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_11->CMT_OUT_FIFO_D92": { + "src_wire": "CMT_FIFO_L_IMUX39_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D92", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_4->CMT_OUT_FIFO_D47": { + "src_wire": "CMT_FIFO_L_IMUX6_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D47", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS20_2": { + "src_wire": "CMT_OUT_FIFO_Q23", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_3->CMT_OUT_FIFO_D36": { + "src_wire": "CMT_FIFO_L_IMUX7_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D36", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS22_1": { + "src_wire": "CMT_OUT_FIFO_Q10", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS19_9": { + "src_wire": "CMT_OUT_FIFO_Q71", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS11_9": { + "src_wire": "CMT_OUT_FIFO_Q72", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS4_1": { + "src_wire": "CMT_IN_FIFO_Q11", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_4->CMT_IN_FIFO_D43": { + "src_wire": "CMT_FIFO_L_IMUX42_4", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D43", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q86->CMT_FIFO_L_LOGIC_OUTS9_10": { + "src_wire": "CMT_IN_FIFO_Q86", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_7->CMT_IN_FIFO_RESET": { + "src_wire": "CMT_FIFO_L_IMUX5_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_RESET", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_10->CMT_OUT_FIFO_D80": { + "src_wire": "CMT_FIFO_L_IMUX28_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D80", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_1->CMT_OUT_FIFO_D10": { + "src_wire": "CMT_FIFO_L_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_6->CMT_IN_FIFO_D56": { + "src_wire": "CMT_FIFO_L_IMUX36_6", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D56", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS22_9": { + "src_wire": "CMT_OUT_FIFO_Q70", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_10->CMT_IN_FIFO_D81": { + "src_wire": "CMT_FIFO_L_IMUX40_10", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D81", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS19_7": { + "src_wire": "CMT_OUT_FIFO_Q65", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_5->CMT_OUT_FIFO_D52": { + "src_wire": "CMT_FIFO_L_IMUX39_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D52", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q76->CMT_FIFO_L_LOGIC_OUTS9_9": { + "src_wire": "CMT_IN_FIFO_Q76", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_CLK0_6->CMT_OUT_FIFO_WRCLK": { + "src_wire": "CMT_FIFO_L_CLK0_6", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_WRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_11->CMT_IN_FIFO_D91": { + "src_wire": "CMT_FIFO_L_IMUX40_11", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D91", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_7->CMT_OUT_FIFO_RDEN": { + "src_wire": "CMT_FIFO_L_IMUX6_7", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_0->CMT_OUT_FIFO_D03": { + "src_wire": "CMT_FIFO_L_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D03", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS11_4": { + "src_wire": "CMT_OUT_FIFO_Q42", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS20_0": { + "src_wire": "CMT_OUT_FIFO_Q03", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_8->CMT_OUT_FIFO_D66": { + "src_wire": "CMT_FIFO_L_IMUX7_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D66", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_7->CMT_IN_FIFO_D65": { + "src_wire": "CMT_FIFO_L_IMUX40_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D65", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS5_9": { + "src_wire": "CMT_IN_FIFO_Q72", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_2->CMT_OUT_FIFO_D21": { + "src_wire": "CMT_FIFO_L_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D21", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS19_6": { + "src_wire": "CMT_OUT_FIFO_Q55", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS19_5": { + "src_wire": "CMT_OUT_FIFO_Q51", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_6->CMT_IN_FIFO_D57": { + "src_wire": "CMT_FIFO_L_IMUX42_6", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D57", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q74->CMT_FIFO_L_LOGIC_OUTS12_9": { + "src_wire": "CMT_IN_FIFO_Q74", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS11_11": { + "src_wire": "CMT_OUT_FIFO_Q92", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q35->CMT_FIFO_L_LOGIC_OUTS8_3": { + "src_wire": "CMT_IN_FIFO_Q35", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS1_10": { + "src_wire": "CMT_IN_FIFO_Q83", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_CLK1_7->CMT_IN_FIFO_RDCLK": { + "src_wire": "CMT_FIFO_L_CLK1_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_RDCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_9->CMT_OUT_FIFO_D74": { + "src_wire": "CMT_FIFO_L_IMUX12_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D74", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q94->CMT_FIFO_L_LOGIC_OUTS12_11": { + "src_wire": "CMT_IN_FIFO_Q94", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_6->CMT_IN_FIFO_WREN": { + "src_wire": "CMT_FIFO_L_IMUX7_6", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WREN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS22_8": { + "src_wire": "CMT_OUT_FIFO_Q60", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_9->CMT_IN_FIFO_D71": { + "src_wire": "CMT_FIFO_L_IMUX40_9", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D71", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS20_9": { + "src_wire": "CMT_OUT_FIFO_Q73", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_11->CMT_OUT_FIFO_D91": { + "src_wire": "CMT_FIFO_L_IMUX21_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D91", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS4_8": { + "src_wire": "CMT_IN_FIFO_Q61", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_0->CMT_OUT_FIFO_D01": { + "src_wire": "CMT_FIFO_L_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D01", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS4_11": { + "src_wire": "CMT_IN_FIFO_Q91", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_2->CMT_IN_FIFO_D21": { + "src_wire": "CMT_FIFO_L_IMUX40_2", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D21", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_4->CMT_OUT_FIFO_D40": { + "src_wire": "CMT_FIFO_L_IMUX28_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D40", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_3->CMT_OUT_FIFO_D31": { + "src_wire": "CMT_FIFO_L_IMUX21_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D31", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_8->CMT_OUT_FIFO_D60": { + "src_wire": "CMT_FIFO_L_IMUX28_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D60", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CMT_FIFO_R.json b/kintex7/tile_type_CMT_FIFO_R.json new file mode 100644 index 0000000..738b7eb --- /dev/null +++ b/kintex7/tile_type_CMT_FIFO_R.json @@ -0,0 +1,5261 @@ +{ + "tile_type": "CMT_FIFO_R", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "OUT_FIFO", + "type": "OUT_FIFO", + "site_pins": { + "WREN": "CMT_OUT_FIFO_WREN", + "SCANOUT0": "CMT_OUT_FIFO_SCANOUT0", + "D67": "CMT_OUT_FIFO_D67", + "D15": "CMT_OUT_FIFO_D15", + "WRCLK": "CMT_OUT_FIFO_WRCLK", + "Q00": "CMT_OUT_FIFO_Q00", + "D11": "CMT_OUT_FIFO_D11", + "ALMOSTFULL": "CMT_OUT_FIFO_ALMOSTFULL", + "Q33": "CMT_OUT_FIFO_Q33", + "D72": "CMT_OUT_FIFO_D72", + "Q01": "CMT_OUT_FIFO_Q01", + "Q83": "CMT_OUT_FIFO_Q83", + "D33": "CMT_OUT_FIFO_D33", + "Q12": "CMT_OUT_FIFO_Q12", + "D74": "CMT_OUT_FIFO_D74", + "Q56": "CMT_OUT_FIFO_Q56", + "D37": "CMT_OUT_FIFO_D37", + "D35": "CMT_OUT_FIFO_D35", + "Q92": "CMT_OUT_FIFO_Q92", + "Q91": "CMT_OUT_FIFO_Q91", + "Q52": "CMT_OUT_FIFO_Q52", + "Q20": "CMT_OUT_FIFO_Q20", + "D52": "CMT_OUT_FIFO_D52", + "Q81": "CMT_OUT_FIFO_Q81", + "RDEN": "CMT_OUT_FIFO_RDEN", + "Q64": "CMT_OUT_FIFO_Q64", + "Q61": "CMT_OUT_FIFO_Q61", + "D87": "CMT_OUT_FIFO_D87", + "D86": "CMT_OUT_FIFO_D86", + "D94": "CMT_OUT_FIFO_D94", + "D04": "CMT_OUT_FIFO_D04", + "D62": "CMT_OUT_FIFO_D62", + "D36": "CMT_OUT_FIFO_D36", + "D25": "CMT_OUT_FIFO_D25", + "Q41": "CMT_OUT_FIFO_Q41", + "D60": "CMT_OUT_FIFO_D60", + "Q43": "CMT_OUT_FIFO_Q43", + "SCANENB": "CMT_OUT_FIFO_SCANENB", + "D45": "CMT_OUT_FIFO_D45", + "Q54": "CMT_OUT_FIFO_Q54", + "FULL": "CMT_OUT_FIFO_FULL", + "D43": "CMT_OUT_FIFO_D43", + "Q67": "CMT_OUT_FIFO_Q67", + "D51": "CMT_OUT_FIFO_D51", + "D23": "CMT_OUT_FIFO_D23", + "SCANIN0": "CMT_OUT_FIFO_SCANIN0", + "D92": "CMT_OUT_FIFO_D92", + "D02": "CMT_OUT_FIFO_D02", + "D83": "CMT_OUT_FIFO_D83", + "Q57": "CMT_OUT_FIFO_Q57", + "D80": "CMT_OUT_FIFO_D80", + "TESTREADDISB": "CMT_OUT_FIFO_TESTREADDISB", + "Q51": "CMT_OUT_FIFO_Q51", + "D85": "CMT_OUT_FIFO_D85", + "D82": "CMT_OUT_FIFO_D82", + "Q21": "CMT_OUT_FIFO_Q21", + "SCANOUT1": "CMT_OUT_FIFO_SCANOUT1", + "D06": "CMT_OUT_FIFO_D06", + "Q90": "CMT_OUT_FIFO_Q90", + "D31": "CMT_OUT_FIFO_D31", + "D47": "CMT_OUT_FIFO_D47", + "Q66": "CMT_OUT_FIFO_Q66", + "D41": "CMT_OUT_FIFO_D41", + "D95": "CMT_OUT_FIFO_D95", + "D70": "CMT_OUT_FIFO_D70", + "D21": "CMT_OUT_FIFO_D21", + "TESTMODEB": "CMT_OUT_FIFO_TESTMODEB", + "D66": "CMT_OUT_FIFO_D66", + "Q71": "CMT_OUT_FIFO_Q71", + "Q50": "CMT_OUT_FIFO_Q50", + "Q42": "CMT_OUT_FIFO_Q42", + "SCANOUT2": "CMT_OUT_FIFO_SCANOUT2", + "Q80": "CMT_OUT_FIFO_Q80", + "Q10": "CMT_OUT_FIFO_Q10", + "Q62": "CMT_OUT_FIFO_Q62", + "D32": "CMT_OUT_FIFO_D32", + "Q32": "CMT_OUT_FIFO_Q32", + "D97": "CMT_OUT_FIFO_D97", + "Q23": "CMT_OUT_FIFO_Q23", + "D40": "CMT_OUT_FIFO_D40", + "D96": "CMT_OUT_FIFO_D96", + "D16": "CMT_OUT_FIFO_D16", + "Q11": "CMT_OUT_FIFO_Q11", + "D20": "CMT_OUT_FIFO_D20", + "D13": "CMT_OUT_FIFO_D13", + "Q40": "CMT_OUT_FIFO_Q40", + "D10": "CMT_OUT_FIFO_D10", + "Q31": "CMT_OUT_FIFO_Q31", + "D76": "CMT_OUT_FIFO_D76", + "Q93": "CMT_OUT_FIFO_Q93", + "Q65": "CMT_OUT_FIFO_Q65", + "SCANIN3": "CMT_OUT_FIFO_SCANIN3", + "D90": "CMT_OUT_FIFO_D90", + "Q63": "CMT_OUT_FIFO_Q63", + "D93": "CMT_OUT_FIFO_D93", + "D26": "CMT_OUT_FIFO_D26", + "D44": "CMT_OUT_FIFO_D44", + "Q72": "CMT_OUT_FIFO_Q72", + "Q60": "CMT_OUT_FIFO_Q60", + "D73": "CMT_OUT_FIFO_D73", + "D14": "CMT_OUT_FIFO_D14", + "D65": "CMT_OUT_FIFO_D65", + "D64": "CMT_OUT_FIFO_D64", + "D61": "CMT_OUT_FIFO_D61", + "D57": "CMT_OUT_FIFO_D57", + "D75": "CMT_OUT_FIFO_D75", + "Q30": "CMT_OUT_FIFO_Q30", + "Q13": "CMT_OUT_FIFO_Q13", + "RESET": "CMT_OUT_FIFO_RESET", + "D84": "CMT_OUT_FIFO_D84", + "D05": "CMT_OUT_FIFO_D05", + "D03": "CMT_OUT_FIFO_D03", + "D91": "CMT_OUT_FIFO_D91", + "Q02": "CMT_OUT_FIFO_Q02", + "D30": "CMT_OUT_FIFO_D30", + "Q82": "CMT_OUT_FIFO_Q82", + "SCANIN1": "CMT_OUT_FIFO_SCANIN1", + "SCANOUT3": "CMT_OUT_FIFO_SCANOUT3", + "D17": "CMT_OUT_FIFO_D17", + "D12": "CMT_OUT_FIFO_D12", + "Q70": "CMT_OUT_FIFO_Q70", + "D55": "CMT_OUT_FIFO_D55", + "D24": "CMT_OUT_FIFO_D24", + "D54": "CMT_OUT_FIFO_D54", + "Q73": "CMT_OUT_FIFO_Q73", + "D07": "CMT_OUT_FIFO_D07", + "D34": "CMT_OUT_FIFO_D34", + "Q55": "CMT_OUT_FIFO_Q55", + "D63": "CMT_OUT_FIFO_D63", + "TESTWRITEDISB": "CMT_OUT_FIFO_TESTWRITEDISB", + "RDCLK": "CMT_OUT_FIFO_RDCLK", + "Q53": "CMT_OUT_FIFO_Q53", + "D81": "CMT_OUT_FIFO_D81", + "D42": "CMT_OUT_FIFO_D42", + "D22": "CMT_OUT_FIFO_D22", + "D53": "CMT_OUT_FIFO_D53", + "D71": "CMT_OUT_FIFO_D71", + "D56": "CMT_OUT_FIFO_D56", + "ALMOSTEMPTY": "CMT_OUT_FIFO_ALMOSTEMPTY", + "Q03": "CMT_OUT_FIFO_Q03", + "D46": "CMT_OUT_FIFO_D46", + "D50": "CMT_OUT_FIFO_D50", + "Q22": "CMT_OUT_FIFO_Q22", + "D01": "CMT_OUT_FIFO_D01", + "D00": "CMT_OUT_FIFO_D00", + "EMPTY": "CMT_OUT_FIFO_EMPTY", + "D77": "CMT_OUT_FIFO_D77", + "SCANIN2": "CMT_OUT_FIFO_SCANIN2", + "D27": "CMT_OUT_FIFO_D27" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IN_FIFO", + "type": "IN_FIFO", + "site_pins": { + "WREN": "CMT_IN_FIFO_WREN", + "SCANOUT0": "CMT_IN_FIFO_SCANOUT0", + "D67": "CMT_IN_FIFO_D67", + "Q34": "CMT_IN_FIFO_Q34", + "Q86": "CMT_IN_FIFO_Q86", + "Q00": "CMT_IN_FIFO_Q00", + "Q84": "CMT_IN_FIFO_Q84", + "Q77": "CMT_IN_FIFO_Q77", + "D11": "CMT_IN_FIFO_D11", + "ALMOSTFULL": "CMT_IN_FIFO_ALMOSTFULL", + "Q33": "CMT_IN_FIFO_Q33", + "D72": "CMT_IN_FIFO_D72", + "Q01": "CMT_IN_FIFO_Q01", + "Q95": "CMT_IN_FIFO_Q95", + "Q07": "CMT_IN_FIFO_Q07", + "Q06": "CMT_IN_FIFO_Q06", + "D33": "CMT_IN_FIFO_D33", + "Q12": "CMT_IN_FIFO_Q12", + "Q56": "CMT_IN_FIFO_Q56", + "Q92": "CMT_IN_FIFO_Q92", + "Q91": "CMT_IN_FIFO_Q91", + "Q52": "CMT_IN_FIFO_Q52", + "Q20": "CMT_IN_FIFO_Q20", + "WRCLK": "CMT_IN_FIFO_WRCLK", + "Q81": "CMT_IN_FIFO_Q81", + "RDEN": "CMT_IN_FIFO_RDEN", + "Q64": "CMT_IN_FIFO_Q64", + "Q61": "CMT_IN_FIFO_Q61", + "SCANIN1": "CMT_IN_FIFO_SCANIN1", + "D02": "CMT_IN_FIFO_D02", + "D53": "CMT_IN_FIFO_D53", + "D62": "CMT_IN_FIFO_D62", + "Q94": "CMT_IN_FIFO_Q94", + "Q46": "CMT_IN_FIFO_Q46", + "Q41": "CMT_IN_FIFO_Q41", + "D60": "CMT_IN_FIFO_D60", + "Q43": "CMT_IN_FIFO_Q43", + "Q75": "CMT_IN_FIFO_Q75", + "SCANENB": "CMT_IN_FIFO_SCANENB", + "Q54": "CMT_IN_FIFO_Q54", + "FULL": "CMT_IN_FIFO_FULL", + "D43": "CMT_IN_FIFO_D43", + "Q67": "CMT_IN_FIFO_Q67", + "D51": "CMT_IN_FIFO_D51", + "D23": "CMT_IN_FIFO_D23", + "SCANIN0": "CMT_IN_FIFO_SCANIN0", + "D92": "CMT_IN_FIFO_D92", + "Q45": "CMT_IN_FIFO_Q45", + "D01": "CMT_IN_FIFO_D01", + "D83": "CMT_IN_FIFO_D83", + "Q25": "CMT_IN_FIFO_Q25", + "Q05": "CMT_IN_FIFO_Q05", + "Q57": "CMT_IN_FIFO_Q57", + "Q24": "CMT_IN_FIFO_Q24", + "D80": "CMT_IN_FIFO_D80", + "Q51": "CMT_IN_FIFO_Q51", + "D82": "CMT_IN_FIFO_D82", + "Q21": "CMT_IN_FIFO_Q21", + "SCANOUT1": "CMT_IN_FIFO_SCANOUT1", + "Q27": "CMT_IN_FIFO_Q27", + "Q17": "CMT_IN_FIFO_Q17", + "Q47": "CMT_IN_FIFO_Q47", + "Q90": "CMT_IN_FIFO_Q90", + "D31": "CMT_IN_FIFO_D31", + "Q66": "CMT_IN_FIFO_Q66", + "D41": "CMT_IN_FIFO_D41", + "D70": "CMT_IN_FIFO_D70", + "D21": "CMT_IN_FIFO_D21", + "TESTMODEB": "CMT_IN_FIFO_TESTMODEB", + "D66": "CMT_IN_FIFO_D66", + "Q15": "CMT_IN_FIFO_Q15", + "Q71": "CMT_IN_FIFO_Q71", + "Q50": "CMT_IN_FIFO_Q50", + "Q42": "CMT_IN_FIFO_Q42", + "SCANOUT2": "CMT_IN_FIFO_SCANOUT2", + "Q26": "CMT_IN_FIFO_Q26", + "Q80": "CMT_IN_FIFO_Q80", + "Q10": "CMT_IN_FIFO_Q10", + "Q85": "CMT_IN_FIFO_Q85", + "D32": "CMT_IN_FIFO_D32", + "Q32": "CMT_IN_FIFO_Q32", + "Q16": "CMT_IN_FIFO_Q16", + "Q23": "CMT_IN_FIFO_Q23", + "D40": "CMT_IN_FIFO_D40", + "Q83": "CMT_IN_FIFO_Q83", + "Q11": "CMT_IN_FIFO_Q11", + "D20": "CMT_IN_FIFO_D20", + "D13": "CMT_IN_FIFO_D13", + "Q40": "CMT_IN_FIFO_Q40", + "D10": "CMT_IN_FIFO_D10", + "Q31": "CMT_IN_FIFO_Q31", + "Q93": "CMT_IN_FIFO_Q93", + "Q65": "CMT_IN_FIFO_Q65", + "SCANIN3": "CMT_IN_FIFO_SCANIN3", + "Q96": "CMT_IN_FIFO_Q96", + "D90": "CMT_IN_FIFO_D90", + "Q63": "CMT_IN_FIFO_Q63", + "D93": "CMT_IN_FIFO_D93", + "Q04": "CMT_IN_FIFO_Q04", + "Q72": "CMT_IN_FIFO_Q72", + "Q37": "CMT_IN_FIFO_Q37", + "D73": "CMT_IN_FIFO_D73", + "D65": "CMT_IN_FIFO_D65", + "D64": "CMT_IN_FIFO_D64", + "D61": "CMT_IN_FIFO_D61", + "D57": "CMT_IN_FIFO_D57", + "Q36": "CMT_IN_FIFO_Q36", + "Q97": "CMT_IN_FIFO_Q97", + "Q13": "CMT_IN_FIFO_Q13", + "RESET": "CMT_IN_FIFO_RESET", + "D12": "CMT_IN_FIFO_D12", + "TESTREADDISB": "CMT_IN_FIFO_TESTREADDISB", + "D03": "CMT_IN_FIFO_D03", + "D91": "CMT_IN_FIFO_D91", + "Q02": "CMT_IN_FIFO_Q02", + "D30": "CMT_IN_FIFO_D30", + "Q82": "CMT_IN_FIFO_Q82", + "Q62": "CMT_IN_FIFO_Q62", + "SCANOUT3": "CMT_IN_FIFO_SCANOUT3", + "Q74": "CMT_IN_FIFO_Q74", + "Q30": "CMT_IN_FIFO_Q30", + "Q60": "CMT_IN_FIFO_Q60", + "Q70": "CMT_IN_FIFO_Q70", + "D55": "CMT_IN_FIFO_D55", + "D63": "CMT_IN_FIFO_D63", + "D54": "CMT_IN_FIFO_D54", + "Q73": "CMT_IN_FIFO_Q73", + "Q55": "CMT_IN_FIFO_Q55", + "TESTWRITEDISB": "CMT_IN_FIFO_TESTWRITEDISB", + "RDCLK": "CMT_IN_FIFO_RDCLK", + "Q53": "CMT_IN_FIFO_Q53", + "D81": "CMT_IN_FIFO_D81", + "D42": "CMT_IN_FIFO_D42", + "D22": "CMT_IN_FIFO_D22", + "Q35": "CMT_IN_FIFO_Q35", + "D71": "CMT_IN_FIFO_D71", + "D56": "CMT_IN_FIFO_D56", + "ALMOSTEMPTY": "CMT_IN_FIFO_ALMOSTEMPTY", + "Q03": "CMT_IN_FIFO_Q03", + "D50": "CMT_IN_FIFO_D50", + "Q87": "CMT_IN_FIFO_Q87", + "Q22": "CMT_IN_FIFO_Q22", + "D52": "CMT_IN_FIFO_D52", + "D00": "CMT_IN_FIFO_D00", + "Q76": "CMT_IN_FIFO_Q76", + "EMPTY": "CMT_IN_FIFO_EMPTY", + "Q14": "CMT_IN_FIFO_Q14", + "Q44": "CMT_IN_FIFO_Q44", + "SCANIN2": "CMT_IN_FIFO_SCANIN2" + }, + "x_coord": 0 + } + ], + "wires": [ + "CMT_FIFO_NW4END0_8", + "CMT_OUT_FIFO_D87", + "CMT_IN_FIFO_D65", + "CMT_FIFO_L_IMUX35_3", + "CMT_FIFO_L_LOGIC_OUTS0_8", + "CMT_OUT_FIFO_SCANOUT3", + "CMT_FIFO_L_FAN2_2", + "CMT_FIFO_SE4C3_4", + "CMT_FIFO_L_IMUX3_6", + "CMT_OUT_FIFO_D00", + "CMT_FIFO_L_FAN4_9", + "CMT_IN_FIFO_Q14", + "CMT_FIFO_NW4END3_5", + "CMT_FIFO_WL1END1_10", + "CMT_FIFO_SW2A1_11", + "CMT_FIFO_L_LOGIC_OUTS23_6", + "CMT_FIFO_EE2A0_9", + "CMT_FIFO_L_IMUX19_9", + "CMT_FIFO_SW2A1_4", + "CMT_FIFO_EL1BEG3_5", + "CMT_FIFO_SE4BEG3_1", + "CMT_FIFO_L_FAN6_8", + "CMT_FIFO_NW4A2_0", + "CMT_FIFO_L_IMUX0_6", + "CMT_FIFO_L_FAN0_7", + "CMT_FIFO_NW2A2_9", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "CMT_FIFO_SE2A3_2", + "CMT_FIFO_SE4C1_9", + "CMT_OUT_FIFO_D81", + "CMT_FIFO_WW2A3_3", + "CMT_FIFO_SE2A3_4", + "CMT_FIFO_LH2_1", + "CMT_OUT_FIFO_Q61", + "CMT_FIFO_LH4_0", + "CMT_FIFO_L_LOGIC_OUTS15_5", + "CMT_FIFO_EL1BEG0_8", + "CMT_FIFO_WL1END2_4", + "CMT_FIFO_WW4END2_7", + "CMT_FIFO_EE2BEG2_3", + "CMT_FIFO_L_FAN1_7", + "CMT_FIFO_WL1END0_10", + "CMT_FIFO_L_IMUX0_5", + "CMT_FIFO_MONITOR_N_10", + "CMT_FIFO_WW4C2_7", + "CMT_FIFO_SW4END2_9", + "CMT_FIFO_SE4C0_10", + "CMT_FIFO_L_IMUX32_1", + "CMT_FIFO_L_IMUX26_0", + "CMT_FIFO_EE4C3_5", + "CMT_FIFO_WW4A1_8", + "CMT_FIFO_EL1BEG2_3", + "CMT_FIFO_LH10_4", + "CMT_FIFO_EE4A1_8", + "CMT_FIFO_L_IMUX45_3", + "CMT_FIFO_L_IMUX0_7", + "CMT_FIFO_WW4C3_9", + "CMT_FIFO_WW4END1_7", + "CMT_FIFO_EE4A2_10", + "CMT_FIFO_L_IMUX45_4", + "CMT_FIFO_NW2A0_2", + "CMT_FIFO_WL1END1_7", + "CMT_FIFO_NW4END0_11", + "CMT_FIFO_L_CTRL0_4", + "CMT_FIFO_L_IMUX10_7", + "CMT_FIFO_WW4B1_7", + "CMT_FIFO_SW4END3_4", + "CMT_FIFO_L_IMUX29_8", + "CMT_FIFO_L_IMUX30_4", + "CMT_IN_FIFO_Q22", + "CMT_FIFO_L_IMUX37_9", + "CMT_FIFO_SE4C0_8", + "CMT_FIFO_WW2A2_4", + "CMT_FIFO_SE2A1_8", + "CMT_FIFO_SW4A0_4", + "CMT_FIFO_WW4A1_4", + "CMT_FIFO_L_LOGIC_OUTS21_10", + "CMT_FIFO_L_IMUX40_9", + "CMT_FIFO_L_BYP1_2", + "CMT_OUT_FIFO_D85", + "CMT_FIFO_L_LOGIC_OUTS10_6", + "CMT_FIFO_EE2BEG0_0", + "CMT_FIFO_L_LOGIC_OUTS7_1", + "CMT_FIFO_NE4C1_10", + "CMT_IN_FIFO_Q41", + "CMT_FIFO_L_IMUX42_9", + "CMT_FIFO_L_IMUX45_7", + "CMT_FIFO_L_IMUX31_10", + "CMT_FIFO_LH8_0", + "CMT_FIFO_LH3_3", + "CMT_FIFO_L_BYP0_10", + "CMT_FIFO_L_LOGIC_OUTS17_11", + "CMT_FIFO_SW2A2_5", + "CMT_FIFO_LH11_4", + "CMT_FIFO_L_LOGIC_OUTS6_1", + "CMT_FIFO_WW4A3_4", + "CMT_FIFO_EE4A1_9", + "CMT_FIFO_EE2BEG0_4", + "CMT_FIFO_L_IMUX10_0", + "CMT_FIFO_NW4A0_2", + "CMT_FIFO_ER1BEG3_8", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "CMT_FIFO_L_CLK1_8", + "CMT_FIFO_L_IMUX39_2", + "CMT_FIFO_LH8_5", + "CMT_FIFO_SW4A0_11", + "CMT_FIFO_WW4B3_1", + "CMT_FIFO_EE2BEG2_9", + "CMT_FIFO_L_IMUX21_1", + "CMT_FIFO_EE4A0_6", + "CMT_FIFO_L_IMUX19_1", + "CMT_FIFO_LH10_2", + "CMT_FIFO_L_LOGIC_OUTS22_10", + "CMT_FIFO_SE4C0_5", + "FIFO_DQS_IOTOPHASER_1", + "CMT_FIFO_L_IMUX27_9", + "CMT_FIFO_LH1_6", + "CMT_FIFO_NE4BEG1_0", + "CMT_FIFO_L_IMUX31_6", + "CMT_FIFO_L_LOGIC_OUTS19_2", + "CMT_FIFO_L_IMUX33_8", + "CMT_FIFO_EE4BEG2_3", + "CMT_FIFO_L_LOGIC_OUTS15_8", + "CMT_FIFO_NE2A0_6", + "CMT_FIFO_WW2A1_2", + "CMT_OUT_FIFO_Q12", + "CMT_FIFO_L_BYP4_4", + "CMT_FIFO_WW4C3_5", + "CMT_FIFO_EE4B0_8", + "CMT_FIFO_L_IMUX33_1", + "CMT_FIFO_NE4BEG0_9", + "CMT_FIFO_SW4END3_5", + "CMT_FIFO_L_IMUX21_2", + "CMT_FIFO_WW4END2_6", + "CMT_FIFO_SE2A0_5", + "CMT_FIFO_L_IMUX35_2", + "CMT_FIFO_NW2A1_2", + "CMT_OUT_FIFO_ALMOSTEMPTY", + "CMT_FIFO_NE4BEG1_6", + "CMT_FIFO_EE4C3_10", + "CMT_FIFO_L_LOGIC_OUTS12_0", + "CMT_FIFO_L_BYP6_8", + "CMT_OUT_FIFO_Q30", + "CMT_FIFO_LH11_6", + "CMT_FIFO_WW2END1_2", + "CMT_FIFO_SW4END3_2", + "CMT_FIFO_EE4A1_0", + "CMT_FIFO_LH9_2", + "CMT_FIFO_L_LOGIC_OUTS23_8", + "CMT_FIFO_L_IMUX37_10", + "CMT_OUT_FIFO_D27", + "CMT_FIFO_WW2END1_1", + "CMT_FIFO_L_LOGIC_OUTS14_8", + "CMT_FIFO_SW2A1_8", + "FIFO_DQS_IOTOPHASER_22", + "CMT_FIFO_LH12_6", + "CMT_FIFO_NE4BEG3_4", + "CMT_FIFO_SW4END1_1", + "CMT_FIFO_L_IMUX31_9", + "CMT_OUT_FIFO_Q93", + "FIFO_DQS_IOTOPHASER_3", + "CMT_FIFO_L_IMUX0_11", + "CMT_FIFO_L_FAN5_9", + "CMT_FIFO_NE4BEG1_1", + "FIFO_DQS_IOTOPHASER_4", + "CMT_FIFO_WW4A1_2", + "CMT_FIFO_L_LOGIC_OUTS0_10", + "CMT_FIFO_L_IMUX29_10", + "CMT_OUT_FIFO_D10", + "CMT_FIFO_L_BYP1_11", + "CMT_FIFO_SE4BEG1_7", + "CMT_FIFO_SE2A3_6", + "CMT_FIFO_L_IMUX31_0", + "CMT_FIFO_MONITOR_P_2", + "CMT_FIFO_L_IMUX9_10", + "CMT_FIFO_L_BYP1_6", + "CMT_FIFO_L_LOGIC_OUTS2_2", + "CMT_IN_FIFO_SCANOUT0", + "CMT_IN_FIFO_Q03", + "CMT_FIFO_LH2_9", + "CMT_OUT_FIFO_RESET", + "CMT_FIFO_SW4A3_5", + "CMT_FIFO_L_LOGIC_OUTS1_3", + "CMT_FIFO_L_FAN7_8", + "CMT_FIFO_WW4C3_2", + "CMT_FIFO_L_IMUX45_8", + "CMT_FIFO_L_FAN5_5", + "CMT_FIFO_L_IMUX9_0", + "CMT_FIFO_WW4END1_8", + "CMT_FIFO_WR1END0_8", + "CMT_FIFO_L_IMUX44_8", + "CMT_FIFO_L_IMUX27_4", + "CMT_FIFO_L_FAN1_10", + "CMT_FIFO_EE2BEG3_8", + "CMT_FIFO_EE4B3_1", + "CMT_FIFO_L_LOGIC_OUTS16_8", + "CMT_FIFO_WL1END2_5", + "CMT_FIFO_WW4B0_2", + "CMT_FIFO_LH7_0", + "CMT_OUT_FIFO_RDCLK", + "CMT_FIFO_EE4C1_10", + "CMT_FIFO_WW2A3_6", + "CMT_FIFO_WW4A2_1", + "CMT_FIFO_WW4END3_9", + "CMT_FIFO_NE2A3_8", + "CMT_FIFO_L_FAN0_5", + "CMT_FIFO_EL1BEG0_2", + "CMT_FIFO_L_LOGIC_OUTS12_4", + "CMT_IN_FIFO_Q02", + "CMT_FIFO_EE4BEG2_7", + "CMT_FIFO_L_IMUX32_7", + "CMT_OUT_FIFO_Q92", + "CMT_FIFO_L_BYP1_9", + "CMT_OUT_FIFO_EMPTY", + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "CMT_FIFO_NE4C0_0", + "CMT_FIFO_L_IMUX14_11", + "CMT_FIFO_WW2A1_0", + "CMT_FIFO_WW4C0_9", + "CMT_IN_FIFO_EMPTY", + "CMT_FIFO_WW4END1_4", + "CMT_FIFO_SW2A1_7", + "CMT_FIFO_L_CLK0_0", + "CMT_FIFO_NE4BEG2_11", + "CMT_IN_FIFO_D52", + "CMT_FIFO_EE4BEG3_9", + "CMT_FIFO_L_IMUX40_2", + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "CMT_FIFO_L_BYP4_0", + "CMT_FIFO_EE4B1_2", + "CMT_FIFO_L_IMUX36_3", + "CMT_FIFO_WW4A0_3", + "CMT_FIFO_ER1BEG0_5", + "CMT_FIFO_SW4A0_8", + "CMT_FIFO_EE2BEG0_8", + "CMT_FIFO_EE2BEG3_3", + "CMT_FIFO_EL1BEG0_10", + "CMT_FIFO_L_IMUX42_11", + "CMT_FIFO_NE4C3_4", + "CMT_FIFO_EE2BEG1_2", + "CMT_FIFO_L_BYP6_10", + "CMT_FIFO_NE2A1_3", + "CMT_FIFO_L_IMUX3_7", + "CMT_FIFO_WR1END0_7", + "CMT_IN_FIFO_Q72", + "CMT_FIFO_L_IMUX6_3", + "CMT_FIFO_SE4C1_1", + "CMT_FIFO_L_FAN1_3", + "CMT_FIFO_SW2A1_2", + "CMT_FIFO_L_LOGIC_OUTS3_8", + "CMT_FIFO_L_IMUX32_11", + "CMT_FIFO_L_LOGIC_OUTS12_8", + "CMT_FIFO_WW4B1_5", + "CMT_FIFO_WW4B2_3", + "CMT_FIFO_L_IMUX5_0", + "CMT_FIFO_EL1BEG3_11", + "CMT_FIFO_L_IMUX31_2", + "CMT_FIFO_L_LOGIC_OUTS5_6", + "CMT_FIFO_L_LOGIC_OUTS23_3", + "CMT_OUT_FIFO_Q81", + "CMT_FIFO_L_LOGIC_OUTS7_6", + "CMT_FIFO_EE2BEG2_4", + "CMT_IN_FIFO_Q74", + "CMT_FIFO_LH6_6", + "CMT_FIFO_EE4C1_11", + "CMT_FIFO_EL1BEG2_10", + "CMT_FIFO_L_LOGIC_OUTS23_0", + "CMT_FIFO_NE4C3_7", + "CMT_FIFO_LH6_11", + "CMT_FIFO_SW4END1_3", + "CMT_FIFO_L_LOGIC_OUTS14_1", + "CMT_FIFO_EE4BEG0_2", + "CMT_FIFO_L_LOGIC_OUTS21_8", + "CMT_FIFO_L_CTRL1_11", + "CMT_FIFO_SE4C1_7", + "CMT_FIFO_L_BYP7_11", + "CMT_IN_FIFO_Q64", + "CMT_IN_FIFO_Q67", + "CMT_FIFO_NE2A0_8", + "CMT_FIFO_LH5_11", + "CMT_IN_FIFO_D01", + "CMT_FIFO_NE4C0_5", + "CMT_FIFO_WW4C2_0", + "CMT_FIFO_ER1BEG1_1", + "CMT_FIFO_EE4A1_3", + "CMT_FIFO_L_IMUX38_4", + "CMT_FIFO_SW2A3_7", + "CMT_FIFO_WL1END3_2", + "CMT_FIFO_EE4B2_9", + "CMT_OUT_FIFO_D32", + "CMT_FIFO_SE4BEG0_0", + "CMT_FIFO_L_IMUX21_6", + "CMT_FIFO_WW4A2_8", + "CMT_FIFO_WW4END0_9", + "CMT_OUT_FIFO_D62", + "CMT_FIFO_L_IMUX36_7", + "CMT_FIFO_WL1END1_4", + "CMT_FIFO_EE4B0_4", + "CMT_IN_FIFO_Q55", + "CMT_FIFO_NE2A3_10", + "CMT_FIFO_L_IMUX1_7", + "CMT_OUT_FIFO_D24", + "CMT_FIFO_L_CLK0_6", + "CMT_FIFO_L_IMUX42_4", + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "CMT_FIFO_LH9_3", + "CMT_FIFO_L_IMUX28_0", + "CMT_FIFO_LH4_4", + "CMT_FIFO_NE4BEG1_7", + "CMT_FIFO_LH6_4", + "CMT_FIFO_L_LOGIC_OUTS19_8", + "CMT_FIFO_L_IMUX24_2", + "CMT_FIFO_L_CTRL0_2", + "CMT_FIFO_NW4END3_2", + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "CMT_FIFO_L_IMUX12_5", + "CMT_FIFO_L_LOGIC_OUTS5_9", + "CMT_FIFO_L_IMUX12_6", + "CMT_FIFO_L_LOGIC_OUTS9_0", + "CMT_FIFO_L_BYP2_5", + "CMT_FIFO_L_IMUX30_10", + "CMT_FIFO_SW2A0_11", + "CMT_FIFO_WW4B2_7", + "CMT_FIFO_L_IMUX29_1", + "CMT_FIFO_L_IMUX34_4", + "CMT_FIFO_L_IMUX31_7", + "CMT_FIFO_L_IMUX29_9", + "CMT_FIFO_L_IMUX44_10", + "CMT_IN_FIFO_Q75", + "CMT_FIFO_L_FAN5_1", + "CMT_FIFO_L_IMUX18_6", + "CMT_FIFO_L_BYP1_3", + "CMT_FIFO_NW2A2_10", + "CMT_FIFO_L_LOGIC_OUTS15_7", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "CMT_FIFO_WW4A3_6", + "CMT_OUT_FIFO_Q32", + "CMT_FIFO_L_IMUX2_10", + "CMT_OUT_FIFO_Q31", + "CMT_FIFO_L_LOGIC_OUTS8_3", + "CMT_OUT_FIFO_D31", + "CMT_FIFO_SE4BEG0_4", + "CMT_FIFO_LH1_0", + "CMT_IN_FIFO_Q76", + "CMT_FIFO_SW4A3_0", + "CMT_FIFO_SE4BEG3_9", + "CMT_IN_FIFO_Q97", + "CMT_OUT_FIFO_SCANOUT0", + "CMT_FIFO_ER1BEG2_9", + "CMT_FIFO_SW4A0_6", + "CMT_FIFO_LH9_0", + "CMT_FIFO_L_FAN4_1", + "CMT_FIFO_WW2END0_11", + "CMT_FIFO_WL1END2_3", + "CMT_FIFO_L_LOGIC_OUTS10_9", + "CMT_FIFO_EE4B2_8", + "CMT_FIFO_L_CLK1_10", + "CMT_FIFO_EE4BEG2_6", + "CMT_FIFO_LH10_6", + "CMT_IN_FIFO_D54", + "CMT_FIFO_L_CLK0_2", + "CMT_FIFO_ER1BEG2_3", + "CMT_FIFO_WW4C2_1", + "CMT_FIFO_L_IMUX34_11", + "CMT_FIFO_L_FAN3_10", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "CMT_FIFO_EE4B2_5", + "CMT_FIFO_L_BYP3_0", + "CMT_FIFO_L_IMUX29_4", + "CMT_FIFO_L_FAN1_0", + "CMT_FIFO_LH4_10", + "CMT_FIFO_WW2END3_6", + "CMT_FIFO_NE4BEG2_10", + "CMT_FIFO_EE4A3_3", + "CMT_FIFO_L_IMUX10_3", + "CMT_FIFO_NW4END2_1", + "CMT_FIFO_ER1BEG0_6", + "CMT_FIFO_L_LOGIC_OUTS19_6", + "CMT_FIFO_L_LOGIC_OUTS18_4", + "CMT_FIFO_L_IMUX21_11", + "CMT_FIFO_WR1END2_11", + "CMT_FIFO_L_BYP0_0", + "CMT_FIFO_SE4C1_2", + "CMT_FIFO_L_IMUX45_9", + "CMT_FIFO_L_IMUX8_7", + "CMT_FIFO_EE4B0_3", + "CMT_FIFO_L_FAN3_0", + "CMT_IN_FIFO_D67", + "CMT_FIFO_L_CLK0_4", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "CMT_FIFO_EE2BEG3_6", + "CMT_FIFO_SE2A2_10", + "CMT_FIFO_ER1BEG2_10", + "CMT_FIFO_L_IMUX38_10", + "CMT_FIFO_L_FAN4_8", + "CMT_FIFO_NW2A2_1", + "CMT_FIFO_EE2A1_6", + "CMT_FIFO_WW4C0_6", + "CMT_FIFO_L_LOGIC_OUTS16_5", + "CMT_FIFO_L_IMUX23_10", + "CMT_FIFO_EE4B3_2", + "CMT_FIFO_L_IMUX13_6", + "CMT_FIFO_L_FAN2_0", + "CMT_FIFO_NE2A0_2", + "CMT_FIFO_L_IMUX41_0", + "CMT_FIFO_EE2BEG3_7", + "CMT_FIFO_L_LOGIC_OUTS18_7", + "CMT_FIFO_L_IMUX42_5", + "CMT_FIFO_L_IMUX40_5", + "CMT_FIFO_L_IMUX18_8", + "CMT_FIFO_WW2END0_7", + "CMT_FIFO_WW4B3_5", + "CMT_FIFO_L_IMUX4_2", + "CMT_FIFO_L_LOGIC_OUTS23_5", + "CMT_FIFO_LH9_6", + "CMT_FIFO_LH1_5", + "CMT_FIFO_SE4C1_11", + "CMT_FIFO_ER1BEG0_7", + "CMT_FIFO_WW2A3_11", + "CMT_FIFO_EE4BEG1_4", + "CMT_FIFO_NW4END1_3", + "CMT_FIFO_L_LOGIC_OUTS7_4", + "CMT_FIFO_EL1BEG3_8", + "CMT_FIFO_NW2A0_1", + "CMT_OUT_FIFO_D11", + "CMT_FIFO_L_IMUX4_1", + "CMT_FIFO_L_LOGIC_OUTS5_5", + "CMT_OUT_FIFO_Q73", + "CMT_FIFO_WW4B2_9", + "CMT_FIFO_L_LOGIC_OUTS0_0", + "CMT_FIFO_EE4BEG2_5", + "CMT_FIFO_L_BYP0_3", + "CMT_FIFO_EE4BEG3_5", + "CMT_FIFO_L_IMUX23_0", + "CMT_FIFO_L_LOGIC_OUTS19_7", + "CMT_FIFO_WW4A0_7", + "CMT_OUT_FIFO_D95", + "CMT_FIFO_L_LOGIC_OUTS17_9", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "CMT_FIFO_L_IMUX40_6", + "CMT_FIFO_EE4C0_1", + "CMT_FIFO_L_IMUX0_9", + "CMT_FIFO_WR1END1_4", + "CMT_FIFO_L_IMUX26_4", + "CMT_FIFO_NW4A0_11", + "CMT_FIFO_L_IMUX18_0", + "CMT_FIFO_L_IMUX13_9", + "CMT_FIFO_SE4C2_10", + "CMT_FIFO_EE4A0_11", + "CMT_FIFO_EE2BEG0_6", + "CMT_FIFO_EE2BEG1_11", + "CMT_FIFO_WW2A1_9", + "CMT_FIFO_ER1BEG3_5", + "CMT_FIFO_L_FAN1_4", + "CMT_FIFO_NW4A1_6", + "CMT_FIFO_L_LOGIC_OUTS16_6", + "CMT_FIFO_L_LOGIC_OUTS11_11", + "CMT_FIFO_WW2END0_2", + "CMT_FIFO_EE4BEG2_10", + "CMT_FIFO_WW2A0_9", + "CMT_FIFO_L_IMUX30_7", + "CMT_FIFO_L_IMUX7_0", + "CMT_FIFO_EL1BEG1_9", + "CMT_FIFO_L_IMUX26_7", + "CMT_FIFO_L_IMUX22_9", + "CMT_FIFO_L_IMUX43_5", + "CMT_FIFO_SW4END2_8", + "CMT_FIFO_L_BYP5_8", + "CMT_OUT_FIFO_Q02", + "CMT_FIFO_NE4C0_8", + "CMT_OUT_FIFO_D22", + "CMT_FIFO_L_IMUX23_5", + "CMT_FIFO_NE4C1_8", + "CMT_FIFO_WW4A3_2", + "CMT_FIFO_WR1END1_5", + "CMT_FIFO_NW4END2_6", + "CMT_FIFO_L_LOGIC_OUTS13_5", + "CMT_FIFO_L_IMUX26_1", + "CMT_FIFO_WL1END0_4", + "CMT_FIFO_SE4BEG2_2", + "CMT_FIFO_LH2_10", + "CMT_FIFO_L_LOGIC_OUTS0_4", + "CMT_FIFO_EE4C3_0", + "CMT_FIFO_L_BYP0_4", + "CMT_FIFO_NE2A1_1", + "CMT_FIFO_SW2A1_9", + "CMT_FIFO_LH9_8", + "CMT_FIFO_L_IMUX10_10", + "CMT_OUT_FIFO_D57", + "CMT_FIFO_L_IMUX21_7", + "CMT_FIFO_L_LOGIC_OUTS4_6", + "CMT_FIFO_SW2A0_1", + "CMT_FIFO_NE2A2_11", + "CMT_FIFO_LH11_3", + "CMT_FIFO_L_IMUX46_5", + "CMT_FIFO_L_IMUX32_8", + "CMT_FIFO_SW4END1_9", + "CMT_IN_FIFO_SCANOUT2", + "CMT_FIFO_NW4A1_0", + "CMT_FIFO_L_BYP4_2", + "FIFO_DQS_IOTOPHASER_66", + "CMT_FIFO_WR1END2_9", + "CMT_FIFO_NW2A0_11", + "CMT_FIFO_NW2A3_5", + "CMT_OUT_FIFO_D44", + "CMT_FIFO_NW4END1_0", + "CMT_FIFO_WW2END2_1", + "CMT_FIFO_L_IMUX17_8", + "CMT_FIFO_NW4END0_0", + "CMT_FIFO_SW2A3_5", + "CMT_FIFO_EL1BEG3_9", + "CMT_FIFO_LH12_0", + "CMT_FIFO_WW4A0_9", + "CMT_FIFO_L_IMUX34_0", + "CMT_IN_FIFO_D10", + "CMT_FIFO_EE2BEG1_1", + "CMT_IN_FIFO_Q91", + "CMT_FIFO_NE4C3_8", + "CMT_FIFO_EE2BEG1_0", + "CMT_FIFO_L_LOGIC_OUTS10_0", + "CMT_FIFO_NE4BEG0_5", + "CMT_FIFO_MONITOR_P_11", + "CMT_FIFO_SE2A3_0", + "CMT_FIFO_NE4BEG2_5", + "CMT_FIFO_NW4END3_8", + "CMT_FIFO_LH8_7", + "CMT_FIFO_L_LOGIC_OUTS19_9", + "CMT_FIFO_L_IMUX5_1", + "CMT_IN_FIFO_D64", + "CMT_FIFO_L_CTRL1_3", + "CMT_FIFO_WW4END3_6", + "CMT_FIFO_L_FAN7_9", + "CMT_FIFO_EE4BEG1_8", + "CMT_IN_FIFO_SCANIN3", + "CMT_FIFO_NW2A1_0", + "CMT_OUT_FIFO_Q90", + "CMT_FIFO_L_LOGIC_OUTS19_10", + "CMT_FIFO_L_IMUX41_4", + "CMT_FIFO_NW4END2_7", + "CMT_FIFO_L_FAN3_5", + "CMT_FIFO_L_LOGIC_OUTS23_9", + "CMT_FIFO_L_IMUX0_1", + "CMT_FIFO_SE4BEG2_3", + "CMT_OUT_FIFO_Q13", + "CMT_FIFO_L_FAN4_10", + "CMT_FIFO_SW2A0_10", + "CMT_FIFO_L_IMUX1_8", + "CMT_FIFO_L_CTRL1_9", + "CMT_FIFO_EE4BEG1_2", + "CMT_FIFO_L_LOGIC_OUTS11_7", + "CMT_FIFO_SW4A1_8", + "CMT_FIFO_SW2A1_0", + "CMT_OUT_FIFO_Q21", + "CMT_FIFO_NW4END0_5", + "CMT_FIFO_L_IMUX40_1", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_11", + "CMT_FIFO_EE2A2_2", + "CMT_FIFO_L_IMUX28_7", + "CMT_FIFO_ER1BEG1_8", + "CMT_FIFO_WW4C0_3", + "CMT_FIFO_L_LOGIC_OUTS0_1", + "CMT_FIFO_WW2A3_2", + "CMT_FIFO_L_IMUX20_8", + "CMT_FIFO_L_IMUX8_6", + "CMT_FIFO_WW2END2_2", + "CMT_FIFO_WW2END1_5", + "CMT_FIFO_L_IMUX0_3", + "CMT_FIFO_ER1BEG3_4", + "CMT_FIFO_NW4A2_11", + "CMT_FIFO_ER1BEG0_10", + "CMT_FIFO_EE4A0_2", + "CMT_FIFO_L_BYP2_8", + "CMT_FIFO_L_IMUX12_3", + "CMT_FIFO_SW4A2_9", + "CMT_FIFO_L_LOGIC_OUTS0_9", + "CMT_FIFO_NE2A1_4", + "CMT_OUT_FIFO_D50", + "CMT_FIFO_WW2A2_7", + "CMT_FIFO_L_BYP6_3", + "CMT_FIFO_EE4A0_8", + "CMT_FIFO_L_IMUX25_10", + "CMT_FIFO_L_IMUX14_4", + "CMT_IN_FIFO_WREN", + "CMT_FIFO_WR1END3_6", + "CMT_FIFO_SE2A2_5", + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "CMT_FIFO_L_LOGIC_OUTS14_3", + "CMT_FIFO_EE4A3_4", + "CMT_FIFO_NW4A1_2", + "CMT_FIFO_WW2A2_10", + "CMT_OUT_FIFO_Q65", + "CMT_FIFO_LH5_4", + "CMT_FIFO_L_IMUX37_2", + "CMT_FIFO_EE2BEG3_10", + "CMT_FIFO_L_IMUX23_4", + "CMT_FIFO_EE2A3_4", + "CMT_FIFO_EE4A2_5", + "CMT_FIFO_WW2A3_9", + "CMT_FIFO_L_IMUX26_2", + "CMT_FIFO_L_CTRL0_1", + "CMT_FIFO_EE4C1_4", + "CMT_FIFO_SE4BEG0_9", + "CMT_FIFO_WW2END3_9", + "CMT_FIFO_LH8_8", + "CMT_FIFO_L_IMUX28_4", + "CMT_FIFO_L_IMUX3_0", + "CMT_FIFO_MONITOR_N_11", + "CMT_FIFO_EE4A3_1", + "CMT_FIFO_L_LOGIC_OUTS14_7", + "CMT_FIFO_L_IMUX11_9", + "CMT_FIFO_L_IMUX27_11", + "CMT_IN_FIFO_D73", + "CMT_FIFO_SE4C0_11", + "CMT_IN_FIFO_Q43", + "CMT_FIFO_L_BYP6_2", + "CMT_FIFO_L_IMUX34_10", + "CMT_FIFO_EE4B0_1", + "CMT_FIFO_LH4_2", + "CMT_FIFO_WW4B0_9", + "CMT_FIFO_L_FAN0_0", + "CMT_FIFO_NE4BEG2_4", + "CMT_FIFO_L_IMUX15_2", + "CMT_FIFO_WW2A0_4", + "CMT_FIFO_L_IMUX44_4", + "CMT_FIFO_EE4BEG0_4", + "CMT_FIFO_L_FAN5_7", + "CMT_FIFO_EL1BEG0_11", + "CMT_FIFO_L_IMUX37_0", + "CMT_FIFO_L_BYP7_7", + "CMT_FIFO_L_IMUX5_7", + "CMT_FIFO_L_LOGIC_OUTS9_10", + "CMT_FIFO_SE4BEG0_2", + "CMT_FIFO_L_BYP7_9", + "CMT_FIFO_EE4A3_6", + "CMT_OUT_FIFO_Q10", + "CMT_FIFO_L_LOGIC_OUTS10_4", + "CMT_FIFO_L_IMUX14_5", + "CMT_FIFO_L_LOGIC_OUTS16_9", + "CMT_FIFO_NW4END1_8", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_8", + "CMT_FIFO_L_IMUX27_6", + "CMT_IN_FIFO_Q73", + "CMT_FIFO_L_LOGIC_OUTS17_0", + "CMT_FIFO_L_IMUX10_4", + "CMT_FIFO_SE4BEG1_3", + "CMT_FIFO_SW2A0_3", + "CMT_FIFO_SW4A2_2", + "CMT_FIFO_L_FAN4_2", + "CMT_FIFO_L_IMUX16_11", + "CMT_FIFO_ER1BEG1_11", + "CMT_FIFO_SE2A3_3", + "CMT_FIFO_ER1BEG3_10", + "CMT_FIFO_WW4A0_1", + "CMT_FIFO_L_IMUX22_7", + "CMT_FIFO_WW4END2_2", + "CMT_FIFO_EE4C2_1", + "CMT_FIFO_L_LOGIC_OUTS20_7", + "CMT_FIFO_LH8_6", + "CMT_FIFO_MONITOR_N_3", + "CMT_IN_FIFO_Q70", + "CMT_FIFO_SW2A2_7", + "CMT_FIFO_WW4A1_9", + "CMT_FIFO_L_BYP0_11", + "CMT_FIFO_L_LOGIC_OUTS18_11", + "CMT_IN_FIFO_D51", + "CMT_FIFO_LH5_9", + "CMT_FIFO_EE4C3_8", + "CMT_FIFO_L_IMUX35_9", + "CMT_OUT_FIFO_D01", + "CMT_FIFO_WR1END0_6", + "CMT_FIFO_L_IMUX28_10", + "CMT_FIFO_WW4C2_8", + "CMT_OUT_FIFO_Q62", + "CMT_FIFO_L_IMUX30_9", + "CMT_FIFO_NE2A0_4", + "CMT_FIFO_L_IMUX34_2", + "CMT_FIFO_EE2A0_4", + "CMT_FIFO_SE2A0_3", + "CMT_FIFO_LH12_8", + "CMT_FIFO_NE2A1_7", + "CMT_FIFO_L_LOGIC_OUTS16_11", + "CMT_FIFO_NW4A3_6", + "CMT_FIFO_NE4BEG0_0", + "CMT_FIFO_L_IMUX40_4", + "CMT_FIFO_EE4B1_6", + "CMT_FIFO_WW2END3_5", + "CMT_FIFO_NE4BEG3_11", + "CMT_FIFO_EE2A0_7", + "CMT_FIFO_L_IMUX2_0", + "CMT_FIFO_EE4C2_5", + "CMT_FIFO_L_IMUX31_4", + "CMT_FIFO_L_IMUX30_6", + "CMT_FIFO_L_LOGIC_OUTS15_0", + "CMT_FIFO_WR1END2_0", + "CMT_FIFO_ER1BEG1_5", + "CMT_FIFO_L_LOGIC_OUTS11_4", + "CMT_FIFO_L_LOGIC_OUTS20_2", + "CMT_FIFO_EE4BEG3_8", + "CMT_FIFO_L_IMUX41_1", + "CMT_FIFO_L_BYP2_11", + "CMT_FIFO_NE2A3_11", + "CMT_FIFO_L_FAN6_0", + "CMT_FIFO_L_IMUX44_0", + "CMT_FIFO_NW4END0_9", + "CMT_FIFO_EL1BEG2_11", + "CMT_OUT_FIFO_D76", + "CMT_FIFO_L_IMUX2_9", + "CMT_FIFO_WW4C3_6", + "CMT_FIFO_EE2A0_5", + "CMT_FIFO_NW4A0_4", + "CMT_FIFO_EL1BEG3_10", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_1", + "CMT_IN_FIFO_Q57", + "CMT_FIFO_WW4END0_8", + "CMT_FIFO_EE4BEG1_11", + "CMT_FIFO_L_IMUX9_11", + "CMT_FIFO_L_BYP3_9", + "CMT_FIFO_EE4C0_3", + "CMT_OUT_FIFO_Q82", + "CMT_FIFO_L_IMUX30_3", + "CMT_FIFO_L_CTRL1_7", + "CMT_FIFO_L_BYP3_7", + "CMT_FIFO_SE2A1_4", + "CMT_FIFO_L_LOGIC_OUTS21_3", + "CMT_FIFO_L_IMUX10_2", + "CMT_FIFO_SW4A1_7", + "CMT_FIFO_NW2A0_3", + "CMT_FIFO_NW4A0_0", + "CMT_FIFO_WL1END3_9", + "CMT_FIFO_L_IMUX24_9", + "CMT_FIFO_EE2BEG0_5", + "CMT_FIFO_L_BYP6_5", + "CMT_FIFO_L_FAN5_4", + "CMT_FIFO_L_IMUX24_7", + "CMT_FIFO_EE4C1_6", + "CMT_FIFO_L_IMUX4_6", + "CMT_FIFO_NE4C2_0", + "CMT_FIFO_L_BYP5_0", + "CMT_FIFO_L_IMUX21_8", + "CMT_FIFO_L_IMUX19_11", + "CMT_FIFO_L_IMUX20_11", + "CMT_FIFO_SE4C1_6", + "CMT_FIFO_L_CTRL0_5", + "CMT_FIFO_L_IMUX20_0", + "CMT_FIFO_L_LOGIC_OUTS22_5", + "CMT_FIFO_WW4C1_5", + "CMT_FIFO_LH4_3", + "CMT_FIFO_NW4A3_3", + "CMT_FIFO_SE2A0_9", + "CMT_FIFO_SE2A1_3", + "CMT_FIFO_SE4C1_8", + "CMT_FIFO_L_IMUX14_1", + "CMT_FIFO_L_IMUX17_10", + "CMT_FIFO_L_IMUX46_1", + "CMT_FIFO_EE4C2_3", + "CMT_FIFO_NE2A2_0", + "CMT_FIFO_L_IMUX38_7", + "CMT_FIFO_ER1BEG3_6", + "CMT_FIFO_LH3_10", + "CMT_FIFO_EE4C1_0", + "CMT_IN_FIFO_SCANENB", + "CMT_FIFO_SW4END0_4", + "CMT_FIFO_WL1END0_9", + "CMT_FIFO_NW2A1_9", + "CMT_FIFO_SE2A3_5", + "CMT_FIFO_L_IMUX38_3", + "CMT_FIFO_WW4B1_0", + "CMT_FIFO_LH6_0", + "CMT_FIFO_EE4B1_10", + "CMT_IN_FIFO_Q36", + "CMT_FIFO_L_IMUX9_6", + "CMT_IN_FIFO_Q13", + "CMT_OUT_FIFO_SCANIN1", + "CMT_FIFO_L_LOGIC_OUTS6_11", + "CMT_FIFO_ER1BEG1_0", + "CMT_FIFO_L_BYP6_11", + "CMT_FIFO_SW4END3_9", + "CMT_FIFO_L_LOGIC_OUTS9_3", + "CMT_FIFO_L_BYP4_11", + "CMT_FIFO_EE4B1_1", + "CMT_FIFO_EE4BEG2_2", + "CMT_FIFO_L_LOGIC_OUTS12_2", + "CMT_FIFO_L_IMUX2_7", + "CMT_FIFO_EE2A3_8", + "CMT_IN_FIFO_Q45", + "CMT_FIFO_NE2A1_10", + "CMT_FIFO_SW2A2_0", + "CMT_FIFO_EE2BEG2_7", + "CMT_FIFO_SW4A3_10", + "CMT_FIFO_NW2A1_6", + "CMT_FIFO_NE4C2_6", + "CMT_FIFO_L_LOGIC_OUTS8_2", + "CMT_FIFO_L_IMUX14_10", + "CMT_FIFO_SW2A3_9", + "CMT_FIFO_EE4B2_7", + "CMT_FIFO_L_BYP3_2", + "CMT_FIFO_SW2A2_6", + "CMT_FIFO_NW4END1_9", + "CMT_OUT_FIFO_Q63", + "CMT_IN_FIFO_D57", + "CMT_FIFO_L_LOGIC_OUTS2_11", + "CMT_FIFO_EE4A1_5", + "CMT_FIFO_L_CLK1_11", + "CMT_OUT_FIFO_D92", + "CMT_FIFO_NW4END2_9", + "CMT_FIFO_L_FAN6_11", + "CMT_FIFO_WL1END3_0", + "CMT_FIFO_NE4BEG0_6", + "CMT_FIFO_NE2A2_2", + "CMT_FIFO_WR1END3_0", + "CMT_FIFO_NE4C1_3", + "CMT_FIFO_SE2A2_9", + "CMT_FIFO_L_LOGIC_OUTS15_6", + "CMT_FIFO_L_BYP1_4", + "CMT_FIFO_L_LOGIC_OUTS1_1", + "CMT_FIFO_SE4C0_2", + "CMT_FIFO_NW4A2_2", + "CMT_FIFO_MONITOR_N_1", + "CMT_IN_FIFO_Q95", + "CMT_FIFO_WW4B2_10", + "CMT_FIFO_L_IMUX5_5", + "CMT_IN_FIFO_Q05", + "CMT_FIFO_L_IMUX2_2", + "CMT_FIFO_L_BYP0_1", + "CMT_FIFO_L_BYP4_10", + "CMT_OUT_FIFO_Q51", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "CMT_FIFO_L_CTRL0_3", + "CMT_FIFO_L_IMUX4_8", + "CMT_FIFO_WW2END3_11", + "CMT_FIFO_WW4A3_0", + "CMT_FIFO_L_IMUX45_5", + "CMT_FIFO_EE4B0_0", + "CMT_FIFO_L_IMUX22_10", + "CMT_FIFO_EE4A2_2", + "CMT_FIFO_L_CTRL1_6", + "CMT_FIFO_SW4A0_7", + "CMT_FIFO_WW4C2_4", + "CMT_FIFO_WW4A0_2", + "CMT_FIFO_EE4BEG1_10", + "CMT_FIFO_L_LOGIC_OUTS18_0", + "CMT_FIFO_L_IMUX23_2", + "CMT_FIFO_EE2A1_11", + "CMT_FIFO_L_BYP3_6", + "CMT_FIFO_NW2A3_10", + "CMT_FIFO_L_LOGIC_OUTS23_7", + "CMT_FIFO_L_FAN3_7", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "CMT_FIFO_WW2A1_7", + "CMT_FIFO_L_IMUX3_5", + "CMT_FIFO_NW2A2_4", + "CMT_FIFO_L_LOGIC_OUTS17_1", + "CMT_FIFO_SE4BEG1_10", + "CMT_FIFO_L_IMUX5_9", + "CMT_FIFO_LH5_2", + "CMT_FIFO_NW4A0_10", + "CMT_FIFO_L_LOGIC_OUTS4_10", + "CMT_FIFO_EE4BEG3_7", + "CMT_FIFO_NE2A3_3", + "CMT_FIFO_L_FAN5_11", + "CMT_FIFO_LH9_5", + "CMT_FIFO_WW4C0_4", + "CMT_FIFO_EE2BEG1_3", + "CMT_FIFO_SE4BEG0_7", + "CMT_OUT_FIFO_D20", + "CMT_FIFO_WW4C3_7", + "CMT_FIFO_L_IMUX11_6", + "CMT_FIFO_WW4B3_3", + "CMT_FIFO_L_IMUX8_3", + "CMT_FIFO_ER1BEG1_9", + "CMT_FIFO_L_IMUX29_3", + "CMT_FIFO_SE2A3_11", + "CMT_OUT_FIFO_Q42", + "CMT_FIFO_SW4A1_6", + "CMT_FIFO_L_PHASER_WRCLK", + "CMT_FIFO_L_IMUX19_7", + "CMT_FIFO_L_LOGIC_OUTS1_10", + "CMT_FIFO_L_LOGIC_OUTS9_4", + "CMT_FIFO_L_LOGIC_OUTS22_4", + "CMT_OUT_FIFO_Q11", + "CMT_FIFO_L_IMUX22_4", + "CMT_OUT_FIFO_Q52", + "CMT_FIFO_L_LOGIC_OUTS3_1", + "CMT_OUT_FIFO_D13", + "CMT_OUT_FIFO_TESTREADDISB", + "CMT_FIFO_WW4B1_9", + "CMT_FIFO_L_IMUX7_8", + "CMT_FIFO_NW4A0_3", + "CMT_FIFO_SW4END1_4", + "CMT_FIFO_WR1END1_1", + "CMT_FIFO_EE4B0_7", + "CMT_FIFO_L_LOGIC_OUTS6_0", + "CMT_FIFO_LH3_11", + "CMT_FIFO_EE2BEG0_2", + "CMT_FIFO_L_IMUX6_5", + "CMT_FIFO_LH7_4", + "CMT_FIFO_EE4A2_9", + "CMT_FIFO_EE4C1_2", + "CMT_FIFO_L_IMUX28_11", + "CMT_FIFO_EE2A3_6", + "CMT_FIFO_SE2A3_8", + "CMT_FIFO_SE2A1_5", + "CMT_FIFO_EE2BEG2_8", + "CMT_FIFO_SW4A3_11", + "CMT_FIFO_SE2A2_0", + "CMT_FIFO_L_FAN0_10", + "CMT_FIFO_SE2A2_3", + "CMT_FIFO_L_IMUX42_1", + "CMT_FIFO_WL1END0_11", + "CMT_FIFO_L_IMUX11_4", + "CMT_FIFO_EE4A0_4", + "CMT_FIFO_SW4END2_3", + "CMT_IN_FIFO_Q63", + "CMT_FIFO_EL1BEG3_4", + "CMT_FIFO_WW2END3_0", + "CMT_FIFO_L_LOGIC_OUTS23_4", + "CMT_FIFO_WW2END3_2", + "CMT_FIFO_L_IMUX18_5", + "CMT_FIFO_L_LOGIC_OUTS6_3", + "CMT_FIFO_EE4C2_8", + "CMT_FIFO_NW4A2_1", + "CMT_FIFO_LH11_11", + "CMT_FIFO_L_IMUX18_9", + "CMT_FIFO_WW4C1_6", + "CMT_FIFO_LH6_2", + "CMT_FIFO_L_IMUX33_6", + "CMT_FIFO_NE2A2_4", + "CMT_FIFO_LH6_1", + "CMT_OUT_FIFO_D82", + "CMT_FIFO_L_LOGIC_OUTS17_5", + "CMT_FIFO_L_FAN4_11", + "CMT_FIFO_NW4A0_7", + "CMT_FIFO_L_LOGIC_OUTS14_11", + "CMT_FIFO_WW4C1_0", + "CMT_FIFO_WL1END2_6", + "CMT_FIFO_EE4C0_0", + "CMT_FIFO_L_IMUX17_0", + "CMT_FIFO_EE4B3_9", + "CMT_FIFO_SW4A1_4", + "CMT_OUT_FIFO_D30", + "CMT_FIFO_L_IMUX30_5", + "CMT_FIFO_LH7_9", + "CMT_FIFO_L_BYP5_9", + "CMT_FIFO_LH7_11", + "CMT_FIFO_NE4C3_6", + "CMT_FIFO_L_BYP1_8", + "CMT_FIFO_L_IMUX12_10", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "CMT_FIFO_WW4B2_6", + "CMT_FIFO_NW4END0_10", + "CMT_FIFO_L_LOGIC_OUTS2_6", + "CMT_FIFO_WW4C2_2", + "CMT_FIFO_WW4C2_10", + "CMT_FIFO_WW4C1_7", + "CMT_FIFO_L_BYP1_0", + "CMT_FIFO_L_IMUX39_5", + "CMT_FIFO_SW2A2_3", + "CMT_FIFO_L_BYP7_1", + "CMT_FIFO_NE2A2_9", + "CMT_FIFO_L_BYP7_3", + "CMT_FIFO_NE4C3_1", + "CMT_FIFO_L_IMUX46_6", + "CMT_FIFO_EE4C2_7", + "CMT_FIFO_WW2END0_3", + "CMT_FIFO_EE4BEG3_4", + "CMT_FIFO_EE4A3_11", + "CMT_FIFO_WL1END1_1", + "CMT_FIFO_L_IMUX22_8", + "CMT_IN_FIFO_Q42", + "CMT_FIFO_NW2A1_4", + "CMT_FIFO_EE2BEG3_0", + "CMT_FIFO_SW4A1_0", + "CMT_FIFO_L_IMUX22_5", + "CMT_FIFO_EL1BEG1_5", + "CMT_FIFO_L_IMUX18_3", + "CMT_FIFO_L_IMUX41_6", + "CMT_FIFO_L_LOGIC_OUTS23_2", + "CMT_FIFO_LH11_5", + "CMT_FIFO_L_IMUX41_5", + "CMT_OUT_FIFO_Q83", + "CMT_FIFO_NW4END0_7", + "CMT_FIFO_L_IMUX32_5", + "CMT_IN_FIFO_Q07", + "CMT_FIFO_L_IMUX34_3", + "CMT_FIFO_NE2A1_8", + "CMT_FIFO_L_IMUX30_8", + "CMT_FIFO_L_IMUX12_11", + "CMT_FIFO_WW4C1_9", + "CMT_FIFO_SE2A2_7", + "CMT_FIFO_EE4A1_11", + "CMT_FIFO_SE2A3_7", + "CMT_FIFO_WR1END3_9", + "CMT_FIFO_EE4A1_6", + "CMT_FIFO_WR1END3_4", + "CMT_FIFO_WW4B0_8", + "CMT_FIFO_WW4END3_8", + "CMT_FIFO_L_IMUX35_7", + "CMT_FIFO_L_IMUX12_4", + "CMT_FIFO_EE4B2_1", + "CMT_FIFO_NW4A0_5", + "CMT_FIFO_L_LOGIC_OUTS3_0", + "CMT_OUT_FIFO_D05", + "CMT_FIFO_L_BYP7_2", + "CMT_FIFO_L_IMUX13_11", + "CMT_FIFO_NE4C0_2", + "CMT_FIFO_L_LOGIC_OUTS6_8", + "CMT_FIFO_WW4B2_8", + "CMT_FIFO_WW4END1_6", + "CMT_FIFO_WW4A1_6", + "CMT_FIFO_L_IMUX26_5", + "CMT_FIFO_WW2A2_3", + "CMT_FIFO_EL1BEG2_2", + "CMT_FIFO_L_IMUX25_9", + "CMT_FIFO_SE4C0_6", + "CMT_FIFO_L_IMUX36_8", + "CMT_FIFO_SE4C3_2", + "CMT_IN_FIFO_Q46", + "CMT_FIFO_NW4END2_5", + "CMT_OUT_FIFO_D97", + "CMT_FIFO_LH11_9", + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "CMT_FIFO_SE4C3_1", + "CMT_FIFO_SE2A3_1", + "CMT_FIFO_LH1_11", + "CMT_FIFO_L_IMUX24_11", + "CMT_FIFO_L_IMUX20_5", + "CMT_FIFO_NE4C0_7", + "CMT_FIFO_EE2A1_3", + "FIFO_DQS_IOTOPHASER_44", + "CMT_FIFO_L_LOGIC_OUTS8_9", + "CMT_FIFO_SE4C3_7", + "CMT_FIFO_LH4_11", + "CMT_FIFO_L_IMUX16_6", + "CMT_FIFO_SW4A2_3", + "CMT_FIFO_NE4BEG2_7", + "CMT_FIFO_L_IMUX19_3", + "CMT_FIFO_WW4B2_0", + "CMT_FIFO_EE2A1_0", + "CMT_FIFO_L_IMUX39_0", + "CMT_FIFO_L_IMUX8_2", + "CMT_FIFO_L_LOGIC_OUTS21_4", + "CMT_FIFO_L_FAN5_10", + "CMT_FIFO_NW4END0_3", + "CMT_FIFO_WR1END2_2", + "CMT_FIFO_L_IMUX10_5", + "CMT_FIFO_EE4A1_1", + "CMT_FIFO_WW2A1_5", + "CMT_FIFO_SW4A0_9", + "CMT_FIFO_L_LOGIC_OUTS2_7", + "CMT_FIFO_NW4A3_10", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "CMT_FIFO_ER1BEG3_9", + "CMT_FIFO_LH9_4", + "CMT_FIFO_SE4C0_3", + "CMT_FIFO_LH8_2", + "CMT_FIFO_LH6_9", + "CMT_FIFO_L_LOGIC_OUTS4_11", + "CMT_IN_FIFO_Q10", + "CMT_FIFO_WL1END3_7", + "CMT_FIFO_SE4C2_9", + "CMT_IN_FIFO_D30", + "CMT_IN_FIFO_D33", + "CMT_FIFO_L_IMUX19_4", + "CMT_FIFO_NE4C0_1", + "CMT_FIFO_WW2A0_2", + "CMT_FIFO_L_IMUX15_8", + "CMT_FIFO_L_IMUX9_5", + "CMT_FIFO_NE4C1_2", + "CMT_FIFO_EL1BEG3_2", + "CMT_FIFO_L_CTRL1_10", + "CMT_FIFO_LH3_0", + "CMT_FIFO_EE4BEG1_1", + "CMT_FIFO_EE4BEG1_5", + "CMT_FIFO_MONITOR_N_0", + "CMT_FIFO_L_IMUX17_6", + "CMT_FIFO_EL1BEG2_5", + "CMT_FIFO_L_IMUX18_11", + "CMT_FIFO_NE4C3_0", + "CMT_OUT_FIFO_D23", + "CMT_FIFO_NW4A3_5", + "CMT_FIFO_L_FAN3_8", + "CMT_FIFO_WW4B2_2", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_4", + "CMT_FIFO_L_IMUX7_10", + "CMT_FIFO_SW4END1_5", + "CMT_FIFO_WR1END0_10", + "CMT_FIFO_L_FAN2_4", + "CMT_FIFO_L_IMUX17_9", + "CMT_FIFO_EE4BEG1_9", + "CMT_IN_FIFO_D11", + "CMT_FIFO_L_IMUX26_9", + "CMT_FIFO_L_LOGIC_OUTS9_1", + "CMT_FIFO_L_BYP0_6", + "CMT_FIFO_SW4END0_1", + "CMT_FIFO_NW4END1_1", + "CMT_FIFO_L_IMUX44_2", + "CMT_FIFO_WL1END1_11", + "CMT_FIFO_MONITOR_N_8", + "CMT_FIFO_SW4A3_4", + "CMT_FIFO_SE4BEG3_6", + "CMT_FIFO_WW2A1_4", + "CMT_FIFO_LH6_7", + "CMT_FIFO_L_IMUX2_8", + "CMT_FIFO_L_BYP0_7", + "CMT_FIFO_EE4B3_7", + "CMT_FIFO_L_IMUX18_4", + "CMT_OUT_FIFO_Q56", + "CMT_FIFO_ER1BEG3_1", + "CMT_FIFO_SW4A2_11", + "CMT_FIFO_WW4B2_1", + "CMT_FIFO_WL1END2_9", + "CMT_FIFO_NW4END1_7", + "CMT_FIFO_L_IMUX46_10", + "CMT_FIFO_L_IMUX37_5", + "CMT_FIFO_NE4BEG1_5", + "CMT_FIFO_NE4C2_8", + "CMT_FIFO_WW2END1_11", + "CMT_FIFO_EE4C2_0", + "CMT_FIFO_EE2A3_9", + "CMT_FIFO_SW4END2_11", + "CMT_FIFO_L_LOGIC_OUTS14_5", + "CMT_FIFO_L_IMUX9_2", + "CMT_OUT_FIFO_D64", + "CMT_FIFO_L_FAN7_6", + "CMT_FIFO_L_LOGIC_OUTS4_8", + "CMT_FIFO_WW4A0_5", + "CMT_OUT_FIFO_D04", + "CMT_FIFO_L_IMUX25_2", + "CMT_FIFO_LH5_0", + "CMT_FIFO_L_IMUX15_3", + "CMT_FIFO_NW4END1_5", + "CMT_FIFO_EE2BEG1_9", + "CMT_FIFO_NW2A1_1", + "CMT_FIFO_SW2A3_10", + "CMT_FIFO_EE2BEG3_4", + "CMT_FIFO_EE2A2_5", + "CMT_IN_FIFO_SCANIN0", + "CMT_FIFO_L_LOGIC_OUTS2_9", + "CMT_FIFO_WR1END2_7", + "CMT_FIFO_ER1BEG1_2", + "CMT_FIFO_EL1BEG3_6", + "CMT_FIFO_NE4BEG3_5", + "CMT_FIFO_L_LOGIC_OUTS17_6", + "CMT_FIFO_L_IMUX5_2", + "CMT_FIFO_WR1END0_1", + "CMT_FIFO_WW2END3_3", + "CMT_FIFO_L_IMUX39_4", + "CMT_FIFO_L_LOGIC_OUTS7_9", + "CMT_FIFO_EE4BEG3_1", + "CMT_FIFO_WR1END3_7", + "CMT_FIFO_SE4C2_11", + "CMT_FIFO_SW2A3_2", + "CMT_FIFO_L_LOGIC_OUTS11_10", + "CMT_FIFO_L_IMUX34_7", + "CMT_FIFO_EL1BEG1_10", + "CMT_FIFO_L_BYP1_5", + "CMT_IN_FIFO_Q85", + "CMT_FIFO_WW4C0_10", + "CMT_FIFO_WW4B3_0", + "CMT_OUT_FIFO_D60", + "CMT_FIFO_L_IMUX6_4", + "CMT_FIFO_L_LOGIC_OUTS6_10", + "CMT_FIFO_L_LOGIC_OUTS2_4", + "CMT_OUT_FIFO_Q01", + "CMT_FIFO_NW2A1_3", + "CMT_OUT_FIFO_D54", + "CMT_FIFO_L_IMUX6_7", + "CMT_FIFO_L_IMUX0_8", + "CMT_FIFO_L_LOGIC_OUTS22_0", + "CMT_FIFO_NW4A0_8", + "CMT_FIFO_L_IMUX13_8", + "CMT_FIFO_WW4B0_10", + "CMT_FIFO_L_FAN1_8", + "CMT_OUT_FIFO_D03", + "CMT_FIFO_L_BYP7_5", + "CMT_FIFO_L_IMUX39_3", + "CMT_OUT_FIFO_D36", + "CMT_FIFO_WR1END1_0", + "CMT_FIFO_L_IMUX25_3", + "CMT_OUT_FIFO_D96", + "CMT_FIFO_WW4B0_7", + "CMT_FIFO_L_IMUX33_7", + "CMT_FIFO_ER1BEG2_1", + "CMT_FIFO_WR1END3_2", + "CMT_OUT_FIFO_D80", + "CMT_FIFO_WW2A0_1", + "CMT_FIFO_L_LOGIC_OUTS16_1", + "CMT_FIFO_L_IMUX33_11", + "CMT_FIFO_L_LOGIC_OUTS20_3", + "CMT_IN_FIFO_Q52", + "CMT_FIFO_SW4END1_6", + "CMT_FIFO_EE4B2_11", + "CMT_FIFO_L_IMUX3_4", + "CMT_FIFO_SW4END0_7", + "CMT_FIFO_WW4B3_8", + "CMT_IN_FIFO_Q27", + "CMT_IN_FIFO_ALMOSTEMPTY", + "CMT_FIFO_MONITOR_P_4", + "CMT_FIFO_L_LOGIC_OUTS4_1", + "CMT_FIFO_L_CLK0_5", + "CMT_FIFO_L_BYP3_5", + "CMT_FIFO_L_FAN2_7", + "CMT_FIFO_EE4BEG3_10", + "CMT_FIFO_NE2A3_2", + "CMT_FIFO_LH6_5", + "CMT_FIFO_WW2END1_3", + "CMT_FIFO_EE4A2_11", + "CMT_FIFO_EE4B3_8", + "CMT_FIFO_WL1END3_11", + "CMT_FIFO_EE2A2_0", + "CMT_FIFO_L_IMUX22_0", + "CMT_FIFO_NW4A2_7", + "CMT_FIFO_WW2A1_8", + "CMT_FIFO_NW4A0_1", + "CMT_FIFO_L_LOGIC_OUTS10_5", + "CMT_FIFO_L_IMUX25_11", + "CMT_FIFO_L_IMUX24_0", + "CMT_FIFO_NW4END0_2", + "CMT_FIFO_L_CTRL1_8", + "CMT_FIFO_LH12_4", + "CMT_FIFO_EL1BEG1_3", + "CMT_FIFO_SE4C2_0", + "CMT_FIFO_L_IMUX43_11", + "CMT_FIFO_L_LOGIC_OUTS10_11", + "CMT_FIFO_WW2END0_0", + "CMT_FIFO_L_IMUX6_8", + "CMT_FIFO_L_IMUX2_1", + "CMT_IN_FIFO_FULL", + "CMT_FIFO_L_IMUX13_2", + "CMT_FIFO_L_PHASER_RDENABLE", + "CMT_FIFO_EE4A0_3", + "CMT_FIFO_L_FAN7_3", + "CMT_FIFO_L_IMUX7_9", + "CMT_FIFO_L_IMUX18_1", + "CMT_FIFO_L_IMUX33_10", + "CMT_FIFO_L_IMUX9_7", + "CMT_OUT_FIFO_Q55", + "CMT_FIFO_EE4BEG1_6", + "CMT_FIFO_L_IMUX15_6", + "CMT_FIFO_EE4A3_7", + "CMT_FIFO_L_IMUX39_11", + "CMT_FIFO_L_IMUX20_2", + "CMT_FIFO_ER1BEG0_11", + "CMT_FIFO_ER1BEG0_1", + "CMT_FIFO_ER1BEG3_2", + "CMT_FIFO_L_FAN4_3", + "CMT_FIFO_L_FAN2_5", + "CMT_FIFO_NW4END3_7", + "CMT_FIFO_EE4C3_6", + "CMT_FIFO_L_IMUX35_1", + "CMT_FIFO_L_IMUX40_3", + "CMT_FIFO_WR1END2_8", + "CMT_FIFO_L_LOGIC_OUTS13_3", + "CMT_FIFO_L_IMUX20_7", + "CMT_FIFO_L_BYP6_1", + "CMT_FIFO_L_IMUX16_8", + "CMT_OUT_FIFO_D34", + "CMT_FIFO_L_FAN0_2", + "CMT_FIFO_L_LOGIC_OUTS16_7", + "CMT_FIFO_EE4BEG2_0", + "CMT_FIFO_L_BYP2_10", + "CMT_FIFO_NE2A1_11", + "CMT_FIFO_L_LOGIC_OUTS21_0", + "CMT_FIFO_SW2A2_2", + "CMT_FIFO_L_IMUX9_3", + "CMT_FIFO_L_IMUX40_7", + "CMT_FIFO_L_LOGIC_OUTS14_6", + "CMT_FIFO_NW4A3_9", + "CMT_FIFO_EE4B0_11", + "CMT_FIFO_WW2A2_8", + "CMT_FIFO_L_IMUX37_7", + "CMT_FIFO_WW4END1_1", + "CMT_FIFO_LH4_6", + "CMT_FIFO_EE4B1_3", + "CMT_FIFO_SE4C1_0", + "CMT_FIFO_L_IMUX35_5", + "CMT_FIFO_LH12_9", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "CMT_FIFO_WW4B0_6", + "CMT_FIFO_L_BYP2_1", + "CMT_FIFO_NW2A3_4", + "CMT_FIFO_WW4END2_11", + "CMT_FIFO_L_BYP4_7", + "CMT_FIFO_SE2A0_0", + "CMT_FIFO_WL1END3_6", + "CMT_FIFO_WW4C1_11", + "CMT_FIFO_SE4C1_4", + "CMT_OUT_FIFO_D90", + "CMT_IN_FIFO_Q60", + "CMT_FIFO_L_FAN3_3", + "CMT_FIFO_L_LOGIC_OUTS0_3", + "CMT_FIFO_L_IMUX28_8", + "CMT_FIFO_SE2A1_0", + "CMT_FIFO_L_LOGIC_OUTS7_11", + "CMT_FIFO_L_IMUX2_4", + "CMT_FIFO_LH1_1", + "CMT_FIFO_L_FAN0_9", + "CMT_FIFO_L_IMUX36_9", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "CMT_FIFO_L_LOGIC_OUTS16_10", + "CMT_FIFO_L_LOGIC_OUTS13_9", + "CMT_OUT_FIFO_Q71", + "CMT_IN_FIFO_Q86", + "CMT_IN_FIFO_D60", + "CMT_FIFO_EE2A3_0", + "CMT_FIFO_WW2END0_4", + "CMT_FIFO_WW4C2_5", + "CMT_FIFO_L_FAN6_7", + "CMT_IN_FIFO_Q47", + "CMT_FIFO_EE4A2_0", + "CMT_FIFO_WW4C3_11", + "CMT_FIFO_SE4C2_4", + "CMT_FIFO_L_LOGIC_OUTS19_1", + "CMT_FIFO_L_IMUX21_5", + "CMT_FIFO_L_IMUX33_9", + "CMT_FIFO_SE4BEG1_0", + "CMT_FIFO_L_BYP4_6", + "CMT_FIFO_SE4C3_10", + "CMT_FIFO_L_IMUX35_10", + "CMT_OUT_FIFO_Q41", + "CMT_FIFO_L_LOGIC_OUTS17_7", + "CMT_FIFO_WW4C2_6", + "CMT_FIFO_EE4C1_7", + "CMT_OUT_FIFO_D67", + "CMT_FIFO_ER1BEG0_2", + "CMT_FIFO_SW4END2_5", + "CMT_FIFO_LH2_0", + "CMT_FIFO_WL1END2_11", + "CMT_OUT_FIFO_D52", + "CMT_FIFO_L_IMUX39_9", + "CMT_FIFO_WW4A2_5", + "CMT_FIFO_WW4A0_4", + "CMT_FIFO_L_BYP6_6", + "CMT_FIFO_SW2A3_0", + "CMT_IN_FIFO_Q15", + "CMT_FIFO_L_IMUX46_11", + "CMT_IN_FIFO_Q34", + "CMT_OUT_FIFO_D56", + "CMT_FIFO_WW4A0_10", + "CMT_FIFO_L_IMUX11_11", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "CMT_FIFO_WW4C1_4", + "CMT_FIFO_WW4B0_11", + "CMT_FIFO_ER1BEG1_3", + "CMT_FIFO_WW2A1_11", + "CMT_FIFO_WW4END2_5", + "CMT_FIFO_L_LOGIC_OUTS22_9", + "CMT_FIFO_EE4C1_3", + "CMT_FIFO_NW4END1_4", + "CMT_FIFO_L_IMUX30_2", + "CMT_FIFO_L_IMUX47_7", + "CMT_FIFO_L_IMUX7_2", + "CMT_FIFO_NW4A2_5", + "CMT_FIFO_MONITOR_P_1", + "CMT_FIFO_L_IMUX8_5", + "CMT_FIFO_SE4BEG0_5", + "CMT_FIFO_L_IMUX36_2", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "CMT_FIFO_EE2A2_10", + "CMT_FIFO_WW4END0_3", + "CMT_FIFO_WR1END2_6", + "CMT_FIFO_L_IMUX47_6", + "CMT_FIFO_L_LOGIC_OUTS10_7", + "CMT_FIFO_LH12_3", + "CMT_OUT_FIFO_D06", + "CMT_FIFO_LH2_2", + "CMT_FIFO_L_FAN2_9", + "CMT_FIFO_L_LOGIC_OUTS19_5", + "CMT_FIFO_L_FAN5_2", + "CMT_FIFO_L_LOGIC_OUTS13_1", + "CMT_FIFO_L_IMUX0_2", + "CMT_FIFO_L_IMUX31_8", + "CMT_FIFO_NW4A1_11", + "CMT_FIFO_EE4B0_5", + "CMT_FIFO_SE4BEG2_6", + "CMT_FIFO_NW2A2_8", + "CMT_OUT_FIFO_Q20", + "CMT_IN_FIFO_Q30", + "CMT_FIFO_ER1BEG1_4", + "CMT_FIFO_WW4B3_11", + "CMT_FIFO_L_IMUX47_5", + "CMT_FIFO_SE4C2_1", + "CMT_FIFO_L_IMUX43_3", + "CMT_FIFO_L_CTRL1_4", + "CMT_FIFO_MONITOR_N_4", + "CMT_FIFO_NW2A0_9", + "CMT_FIFO_L_IMUX24_8", + "CMT_FIFO_L_LOGIC_OUTS16_2", + "CMT_FIFO_WW4A3_7", + "CMT_FIFO_SE4BEG0_8", + "CMT_FIFO_L_BYP0_9", + "CMT_FIFO_L_IMUX47_2", + "CMT_FIFO_LH2_3", + "CMT_FIFO_EE4A2_8", + "CMT_FIFO_WW4A2_9", + "CMT_FIFO_LH6_3", + "CMT_FIFO_L_PHASER_WRENABLE", + "CMT_FIFO_L_FAN1_6", + "CMT_OUT_FIFO_D07", + "CMT_FIFO_WW4A3_1", + "CMT_FIFO_L_IMUX38_0", + "CMT_IN_FIFO_D82", + "CMT_IN_FIFO_RDEN", + "CMT_FIFO_NE2A2_6", + "CMT_FIFO_L_BYP2_0", + "CMT_FIFO_L_LOGIC_OUTS18_3", + "CMT_FIFO_LH7_3", + "CMT_FIFO_NW2A3_6", + "CMT_OUT_FIFO_Q23", + "CMT_FIFO_L_CTRL1_2", + "CMT_FIFO_L_IMUX20_1", + "CMT_FIFO_L_IMUX5_8", + "CMT_FIFO_WW2END0_1", + "CMT_FIFO_WW4END1_2", + "CMT_FIFO_L_IMUX24_5", + "CMT_FIFO_L_IMUX12_7", + "CMT_FIFO_SE4BEG1_4", + "CMT_FIFO_SW4END2_10", + "CMT_FIFO_L_LOGIC_OUTS14_2", + "CMT_FIFO_L_LOGIC_OUTS9_11", + "CMT_FIFO_L_IMUX14_8", + "CMT_FIFO_WW4B2_4", + "CMT_FIFO_EE4C3_9", + "CMT_FIFO_EE4B2_2", + "CMT_FIFO_L_IMUX3_10", + "CMT_FIFO_L_CLK1_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_10", + "CMT_FIFO_L_IMUX5_4", + "CMT_FIFO_L_LOGIC_OUTS8_5", + "CMT_OUT_FIFO_Q22", + "CMT_FIFO_MONITOR_P_9", + "CMT_FIFO_L_IMUX40_11", + "CMT_FIFO_LH2_6", + "CMT_FIFO_L_IMUX3_1", + "CMT_FIFO_SE4BEG3_0", + "CMT_FIFO_L_LOGIC_OUTS11_8", + "CMT_FIFO_L_IMUX6_11", + "CMT_FIFO_L_IMUX44_7", + "CMT_FIFO_WW2END3_8", + "CMT_FIFO_NE2A0_1", + "CMT_FIFO_SE2A2_11", + "CMT_FIFO_L_IMUX18_2", + "CMT_FIFO_NW2A3_9", + "CMT_FIFO_SE4BEG2_9", + "CMT_FIFO_SW4END1_0", + "CMT_FIFO_L_LOGIC_OUTS15_9", + "CMT_FIFO_L_IMUX27_5", + "CMT_OUT_FIFO_Q60", + "CMT_FIFO_L_LOGIC_OUTS21_5", + "CMT_FIFO_L_LOGIC_OUTS1_7", + "CMT_FIFO_L_IMUX13_0", + "CMT_FIFO_EE2A0_0", + "CMT_FIFO_NW2A0_5", + "CMT_FIFO_NW4END1_10", + "CMT_FIFO_WW4A2_7", + "CMT_FIFO_SW4END2_4", + "CMT_FIFO_ER1BEG2_0", + "CMT_FIFO_L_IMUX21_9", + "CMT_IN_FIFO_SCANIN2", + "CMT_FIFO_L_LOGIC_OUTS3_7", + "CMT_FIFO_LH2_7", + "CMT_FIFO_SE4C3_9", + "CMT_FIFO_L_IMUX15_4", + "CMT_FIFO_NW4END2_3", + "CMT_FIFO_L_FAN3_1", + "CMT_FIFO_NE4C3_5", + "CMT_FIFO_L_IMUX10_9", + "CMT_FIFO_NE4C1_9", + "CMT_FIFO_L_IMUX14_9", + "CMT_FIFO_NW2A3_3", + "CMT_FIFO_L_LOGIC_OUTS10_2", + "CMT_FIFO_LH3_8", + "CMT_FIFO_WW2END2_10", + "CMT_FIFO_NW4END2_4", + "CMT_FIFO_EE4B1_8", + "CMT_FIFO_L_IMUX11_3", + "CMT_FIFO_L_FAN1_5", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_5", + "CMT_FIFO_NE4BEG0_2", + "CMT_FIFO_EE2A2_9", + "CMT_FIFO_SE2A2_4", + "CMT_FIFO_WW4END0_11", + "CMT_FIFO_EE4C0_5", + "CMT_FIFO_SW2A3_6", + "CMT_FIFO_NE4C1_5", + "CMT_FIFO_L_BYP4_9", + "CMT_IN_FIFO_Q82", + "CMT_IN_FIFO_Q94", + "CMT_FIFO_L_LOGIC_OUTS5_7", + "CMT_FIFO_WW2A3_5", + "CMT_FIFO_NE2A2_7", + "CMT_FIFO_L_LOGIC_OUTS15_3", + "CMT_FIFO_SE4C3_6", + "CMT_FIFO_EE2BEG2_1", + "CMT_FIFO_WW2A2_0", + "CMT_FIFO_WW2END3_10", + "CMT_FIFO_L_BYP7_8", + "CMT_FIFO_WW4A1_5", + "CMT_FIFO_NW2A2_6", + "CMT_OUT_FIFO_D42", + "CMT_FIFO_SW4A2_10", + "CMT_IN_FIFO_Q11", + "CMT_FIFO_L_FAN6_6", + "CMT_FIFO_L_IMUX1_6", + "CMT_FIFO_SW4A0_10", + "CMT_FIFO_L_BYP7_4", + "CMT_FIFO_EE4C2_11", + "CMT_OUT_FIFO_Q54", + "CMT_FIFO_L_IMUX44_1", + "CMT_FIFO_EE2A3_2", + "CMT_FIFO_SE4BEG3_4", + "CMT_FIFO_L_IMUX15_0", + "CMT_FIFO_L_IMUX27_3", + "CMT_FIFO_L_IMUX16_3", + "CMT_FIFO_NW2A2_3", + "CMT_FIFO_L_LOGIC_OUTS10_10", + "CMT_IN_FIFO_D02", + "CMT_FIFO_L_IMUX24_3", + "CMT_FIFO_L_BYP7_0", + "CMT_FIFO_L_IMUX35_4", + "CMT_FIFO_L_CLK1_5", + "CMT_FIFO_WW4A3_5", + "CMT_FIFO_L_FAN4_4", + "CMT_OUT_FIFO_D14", + "CMT_OUT_FIFO_D61", + "CMT_FIFO_L_LOGIC_OUTS11_5", + "CMT_FIFO_NE2A2_10", + "CMT_FIFO_L_BYP3_8", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_6", + "CMT_FIFO_WW4C3_0", + "CMT_FIFO_L_IMUX35_11", + "CMT_FIFO_NE4BEG3_6", + "CMT_FIFO_L_IMUX16_4", + "CMT_FIFO_L_IMUX40_0", + "CMT_FIFO_L_IMUX11_10", + "CMT_FIFO_L_IMUX35_6", + "CMT_FIFO_L_IMUX45_10", + "CMT_FIFO_WL1END2_7", + "CMT_FIFO_WW4B3_6", + "CMT_FIFO_L_IMUX42_2", + "CMT_FIFO_L_IMUX46_4", + "CMT_IN_FIFO_RESET", + "CMT_IN_FIFO_Q50", + "CMT_IN_FIFO_Q84", + "CMT_FIFO_L_BYP3_4", + "CMT_FIFO_NE4BEG0_8", + "CMT_FIFO_SE4BEG3_10", + "CMT_FIFO_L_IMUX28_5", + "CMT_FIFO_L_FAN1_2", + "CMT_FIFO_WW4C1_10", + "CMT_FIFO_NW4A1_7", + "CMT_OUT_FIFO_Q80", + "CMT_FIFO_SW4END3_7", + "CMT_FIFO_L_LOGIC_OUTS18_9", + "CMT_FIFO_NE4BEG3_10", + "CMT_FIFO_SW2A1_10", + "CMT_FIFO_L_CLK0_3", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "CMT_FIFO_L_LOGIC_OUTS0_7", + "CMT_FIFO_SE4BEG2_0", + "CMT_FIFO_L_LOGIC_OUTS18_10", + "CMT_FIFO_SW4END1_10", + "CMT_FIFO_L_IMUX23_3", + "CMT_FIFO_EE4A1_2", + "CMT_FIFO_L_IMUX25_6", + "CMT_IN_FIFO_D31", + "CMT_FIFO_SE4BEG2_11", + "CMT_FIFO_L_IMUX32_0", + "CMT_FIFO_WW4A1_11", + "CMT_FIFO_WW2END2_7", + "CMT_FIFO_L_BYP5_4", + "CMT_FIFO_L_LOGIC_OUTS3_9", + "CMT_FIFO_L_IMUX9_8", + "CMT_IN_FIFO_D42", + "CMT_IN_FIFO_D80", + "CMT_FIFO_L_IMUX15_10", + "CMT_FIFO_NE2A0_9", + "CMT_FIFO_WW4B0_1", + "CMT_OUT_FIFO_D21", + "CMT_FIFO_L_IMUX42_10", + "CMT_IN_FIFO_Q17", + "CMT_IN_FIFO_Q96", + "CMT_FIFO_SE4BEG1_5", + "CMT_FIFO_EE4C0_7", + "CMT_FIFO_L_IMUX8_0", + "CMT_FIFO_EE4B2_4", + "CMT_FIFO_NE2A3_9", + "CMT_FIFO_LH7_1", + "CMT_FIFO_L_IMUX45_0", + "CMT_IN_FIFO_SCANOUT3", + "CMT_FIFO_L_IMUX28_1", + "CMT_IN_FIFO_Q93", + "CMT_FIFO_L_IMUX34_5", + "CMT_FIFO_WL1END3_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_3", + "CMT_FIFO_LH7_6", + "CMT_FIFO_WW2END3_4", + "CMT_FIFO_L_IMUX5_6", + "CMT_FIFO_WW4A2_10", + "CMT_FIFO_L_IMUX41_10", + "CMT_FIFO_L_IMUX32_4", + "CMT_FIFO_L_CTRL1_5", + "FIFO_DQS_IOTOPHASER_6", + "CMT_FIFO_L_IMUX3_8", + "CMT_OUT_FIFO_D73", + "CMT_FIFO_ER1BEG2_6", + "CMT_FIFO_L_IMUX20_6", + "CMT_FIFO_SE4C1_5", + "CMT_FIFO_L_IMUX46_2", + "CMT_FIFO_L_IMUX34_1", + "CMT_OUT_FIFO_D12", + "FIFO_DQS_IOTOPHASER_55", + "CMT_FIFO_SW4A3_3", + "CMT_FIFO_WW4B0_3", + "CMT_FIFO_EE4B1_5", + "CMT_FIFO_EL1BEG1_7", + "CMT_FIFO_L_IMUX13_1", + "CMT_FIFO_NE4C3_2", + "CMT_IN_FIFO_WRCLK", + "CMT_FIFO_WW4A3_8", + "CMT_FIFO_WW4A0_0", + "CMT_FIFO_L_IMUX15_11", + "CMT_FIFO_EE4B0_6", + "CMT_FIFO_L_FAN2_1", + "CMT_FIFO_WR1END1_11", + "CMT_FIFO_LH1_4", + "CMT_FIFO_L_LOGIC_OUTS3_3", + "CMT_FIFO_L_FAN2_3", + "CMT_IN_FIFO_D70", + "CMT_FIFO_EE4B1_9", + "CMT_OUT_FIFO_Q66", + "CMT_FIFO_SE4BEG2_5", + "CMT_FIFO_EE4BEG1_0", + "CMT_FIFO_LH10_11", + "CMT_FIFO_MONITOR_P_5", + "CMT_FIFO_L_IMUX1_10", + "CMT_FIFO_NW4END3_0", + "CMT_FIFO_SE4BEG3_8", + "CMT_FIFO_L_IMUX43_6", + "CMT_FIFO_EE4A1_4", + "CMT_FIFO_EL1BEG1_8", + "CMT_FIFO_EE2A3_11", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "CMT_FIFO_L_LOGIC_OUTS3_10", + "CMT_FIFO_EE2A3_10", + "CMT_FIFO_L_IMUX35_8", + "CMT_FIFO_L_LOGIC_OUTS0_2", + "CMT_FIFO_L_CTRL1_0", + "CMT_FIFO_L_FAN4_7", + "CMT_FIFO_L_BYP5_6", + "CMT_FIFO_WW2A0_8", + "CMT_FIFO_LH3_4", + "CMT_FIFO_WW4A1_1", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "CMT_FIFO_ER1BEG3_0", + "CMT_FIFO_EE4B3_5", + "CMT_FIFO_L_LOGIC_OUTS20_9", + "CMT_FIFO_SW4A3_8", + "CMT_FIFO_L_LOGIC_OUTS13_10", + "CMT_FIFO_WW4C0_0", + "CMT_FIFO_L_BYP6_7", + "CMT_FIFO_EE2BEG2_6", + "CMT_FIFO_SW4A0_0", + "CMT_FIFO_WR1END1_9", + "CMT_FIFO_NE4C1_11", + "CMT_FIFO_WW4C0_11", + "CMT_OUT_FIFO_D75", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "CMT_FIFO_EL1BEG3_0", + "CMT_FIFO_L_IMUX41_9", + "CMT_OUT_FIFO_D47", + "CMT_FIFO_EL1BEG0_5", + "CMT_FIFO_EE2BEG1_6", + "CMT_FIFO_L_LOGIC_OUTS6_2", + "CMT_FIFO_L_FAN6_3", + "CMT_FIFO_SW4A1_2", + "CMT_FIFO_NE4C1_0", + "CMT_FIFO_NE2A2_8", + "CMT_FIFO_L_LOGIC_OUTS17_4", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "CMT_FIFO_SE4BEG0_1", + "CMT_FIFO_MONITOR_P_10", + "CMT_FIFO_LH3_5", + "CMT_FIFO_L_IMUX2_11", + "CMT_OUT_FIFO_Q33", + "CMT_FIFO_L_IMUX33_3", + "CMT_FIFO_WW4C2_3", + "CMT_FIFO_EE4A0_0", + "CMT_FIFO_EE4B3_6", + "CMT_FIFO_NW4END3_3", + "CMT_FIFO_L_CTRL0_11", + "CMT_FIFO_L_IMUX47_8", + "CMT_FIFO_LH1_3", + "CMT_FIFO_WW2A3_8", + "CMT_FIFO_L_BYP7_10", + "CMT_FIFO_EE2A2_7", + "CMT_IN_FIFO_D93", + "CMT_FIFO_LH11_2", + "CMT_FIFO_L_IMUX18_10", + "CMT_FIFO_WW4C0_2", + "CMT_FIFO_L_IMUX23_1", + "CMT_FIFO_NW4END1_2", + "CMT_FIFO_WL1END1_9", + "CMT_FIFO_LH10_5", + "CMT_FIFO_NE4C2_1", + "CMT_FIFO_L_LOGIC_OUTS8_6", + "CMT_FIFO_WW4C1_2", + "CMT_FIFO_L_IMUX11_5", + "CMT_FIFO_LH10_3", + "CMT_FIFO_WW2END1_8", + "CMT_FIFO_L_FAN6_10", + "CMT_FIFO_L_IMUX27_1", + "CMT_FIFO_EE4A0_9", + "CMT_FIFO_SE4C3_5", + "CMT_FIFO_NE4BEG2_0", + "CMT_FIFO_L_CTRL0_7", + "CMT_FIFO_L_LOGIC_OUTS16_0", + "CMT_FIFO_WW4END0_4", + "CMT_FIFO_L_IMUX19_0", + "CMT_FIFO_WR1END0_9", + "CMT_IN_FIFO_D12", + "CMT_FIFO_L_FAN0_4", + "CMT_FIFO_EE4BEG0_6", + "CMT_FIFO_L_LOGIC_OUTS21_9", + "CMT_FIFO_L_LOGIC_OUTS21_2", + "CMT_FIFO_SW4END0_9", + "CMT_FIFO_SW4A0_3", + "CMT_FIFO_WR1END2_1", + "CMT_FIFO_L_IMUX3_3", + "CMT_FIFO_SE4C1_10", + "CMT_FIFO_L_FAN0_3", + "CMT_FIFO_SW2A3_3", + "CMT_FIFO_L_IMUX4_9", + "CMT_FIFO_L_LOGIC_OUTS23_10", + "CMT_FIFO_L_IMUX26_3", + "CMT_FIFO_ER1BEG2_7", + "CMT_FIFO_SE2A2_1", + "CMT_FIFO_MONITOR_N_5", + "CMT_FIFO_NW4A2_10", + "CMT_FIFO_L_IMUX43_7", + "CMT_FIFO_SE2A0_2", + "CMT_FIFO_NE4C0_10", + "CMT_FIFO_L_IMUX28_3", + "CMT_FIFO_EE4C3_11", + "CMT_FIFO_SW4END1_7", + "CMT_FIFO_EE2A2_1", + "CMT_FIFO_MONITOR_P_3", + "CMT_FIFO_L_IMUX27_10", + "CMT_FIFO_L_BYP1_10", + "CMT_FIFO_SE4BEG2_7", + "CMT_IN_FIFO_D23", + "CMT_FIFO_L_BYP6_4", + "CMT_IN_FIFO_D72", + "CMT_FIFO_SE4C3_8", + "CMT_FIFO_L_IMUX29_2", + "CMT_OUT_FIFO_D94", + "CMT_OUT_FIFO_D26", + "CMT_FIFO_L_BYP7_6", + "CMT_FIFO_LH8_10", + "CMT_FIFO_NW4END3_10", + "CMT_FIFO_EE2BEG1_4", + "CMT_OUT_FIFO_Q00", + "CMT_FIFO_WW4A1_10", + "CMT_FIFO_L_LOGIC_OUTS10_3", + "CMT_FIFO_EE2BEG1_5", + "CMT_FIFO_EE2A1_7", + "CMT_FIFO_WW4END3_0", + "CMT_FIFO_WL1END3_10", + "CMT_IN_FIFO_Q40", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "CMT_FIFO_WW4END3_10", + "CMT_FIFO_L_LOGIC_OUTS12_11", + "FIFO_DQS_IOTOPHASER_2", + "CMT_FIFO_SW2A2_10", + "CMT_FIFO_WW4A1_3", + "CMT_FIFO_SW2A3_8", + "CMT_FIFO_EE4C0_9", + "CMT_FIFO_EE4B3_10", + "CMT_OUT_FIFO_SCANOUT2", + "CMT_FIFO_L_CTRL0_10", + "CMT_FIFO_LH3_9", + "CMT_FIFO_NE4BEG2_8", + "CMT_FIFO_WW2END2_11", + "CMT_FIFO_L_IMUX16_0", + "CMT_FIFO_NW2A2_2", + "CMT_FIFO_L_LOGIC_OUTS7_3", + "CMT_IN_FIFO_D83", + "CMT_FIFO_SE4C3_0", + "CMT_FIFO_SW4END1_11", + "CMT_FIFO_NE4BEG0_10", + "CMT_FIFO_L_IMUX46_7", + "CMT_FIFO_WW2A1_6", + "CMT_IN_FIFO_Q90", + "CMT_FIFO_NE4BEG1_11", + "CMT_FIFO_L_IMUX15_5", + "CMT_FIFO_L_LOGIC_OUTS21_11", + "CMT_FIFO_WR1END0_4", + "CMT_FIFO_WW4C1_3", + "CMT_FIFO_L_LOGIC_OUTS0_6", + "CMT_FIFO_WW4A0_11", + "CMT_FIFO_NW2A0_4", + "CMT_FIFO_L_IMUX20_3", + "CMT_FIFO_L_BYP3_11", + "CMT_FIFO_L_LOGIC_OUTS6_6", + "CMT_FIFO_L_IMUX23_8", + "CMT_FIFO_NE4BEG3_1", + "CMT_FIFO_NW2A2_11", + "CMT_FIFO_L_LOGIC_OUTS11_9", + "CMT_FIFO_EL1BEG0_1", + "CMT_FIFO_L_LOGIC_OUTS17_10", + "CMT_FIFO_L_LOGIC_OUTS20_8", + "CMT_FIFO_WR1END0_5", + "CMT_FIFO_WW4B1_4", + "CMT_FIFO_LH12_7", + "CMT_IN_FIFO_D21", + "CMT_FIFO_WW2A1_1", + "CMT_FIFO_WW4C3_1", + "CMT_FIFO_EE4A3_9", + "CMT_FIFO_SE2A3_10", + "CMT_FIFO_NW4END3_4", + "CMT_FIFO_L_IMUX38_11", + "CMT_FIFO_ER1BEG0_9", + "CMT_FIFO_SW4END3_6", + "CMT_FIFO_L_FAN7_2", + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "CMT_FIFO_NW4A2_3", + "CMT_FIFO_L_LOGIC_OUTS2_1", + "CMT_FIFO_L_BYP2_4", + "CMT_FIFO_SW4A2_6", + "CMT_FIFO_LH8_1", + "CMT_IN_FIFO_D32", + "CMT_FIFO_ER1BEG1_10", + "CMT_FIFO_WW2A0_3", + "CMT_FIFO_EE2BEG2_2", + "CMT_FIFO_NE4BEG2_2", + "CMT_FIFO_WW2A2_2", + "CMT_FIFO_L_FAN5_0", + "CMT_FIFO_EE2BEG0_10", + "CMT_FIFO_EE4C0_11", + "CMT_FIFO_EE4BEG2_9", + "FIFO_DQS_IOTOPHASER_5", + "CMT_FIFO_L_LOGIC_OUTS20_0", + "CMT_FIFO_EL1BEG3_1", + "CMT_FIFO_EE4C3_4", + "CMT_FIFO_L_LOGIC_OUTS22_11", + "CMT_FIFO_WW4END2_1", + "CMT_FIFO_NE4BEG0_3", + "CMT_FIFO_L_BYP4_3", + "CMT_FIFO_EE4A1_7", + "CMT_FIFO_WW4A0_8", + "CMT_FIFO_NW4END2_0", + "CMT_FIFO_SW4END1_2", + "CMT_FIFO_L_LOGIC_OUTS19_4", + "CMT_FIFO_NW4A2_4", + "CMT_FIFO_L_BYP0_8", + "CMT_FIFO_EE4BEG2_1", + "CMT_FIFO_L_LOGIC_OUTS4_9", + "CMT_FIFO_EE4BEG2_8", + "CMT_FIFO_NW4A3_7", + "CMT_FIFO_L_IMUX17_1", + "CMT_FIFO_L_IMUX9_1", + "CMT_FIFO_NW4A1_5", + "CMT_FIFO_WL1END0_0", + "CMT_IN_FIFO_D20", + "CMT_FIFO_L_LOGIC_OUTS11_2", + "CMT_FIFO_L_LOGIC_OUTS2_10", + "CMT_FIFO_L_IMUX30_0", + "CMT_FIFO_EE4A2_7", + "CMT_IN_FIFO_TESTWRITEDISB", + "CMT_FIFO_NE4C2_11", + "CMT_FIFO_L_IMUX34_6", + "CMT_FIFO_NW4A3_8", + "CMT_FIFO_L_IMUX17_2", + "CMT_FIFO_LH4_5", + "CMT_FIFO_L_LOGIC_OUTS0_11", + "CMT_FIFO_NE4BEG0_1", + "CMT_FIFO_EE2BEG1_7", + "CMT_FIFO_L_LOGIC_OUTS13_4", + "CMT_FIFO_LH5_1", + "CMT_FIFO_WW2END2_5", + "CMT_FIFO_LH1_8", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_0", + "CMT_FIFO_L_BYP1_1", + "CMT_FIFO_L_BYP5_11", + "CMT_FIFO_NW2A2_7", + "CMT_FIFO_L_LOGIC_OUTS1_2", + "CMT_FIFO_L_LOGIC_OUTS10_8", + "CMT_OUT_FIFO_D25", + "CMT_FIFO_WW2A0_7", + "CMT_OUT_FIFO_SCANIN3", + "CMT_FIFO_L_FAN4_6", + "CMT_FIFO_WW4A2_4", + "CMT_FIFO_LH8_3", + "CMT_FIFO_SW4A1_9", + "CMT_FIFO_L_FAN0_1", + "CMT_FIFO_WW4END2_4", + "CMT_IN_FIFO_Q16", + "CMT_FIFO_LH12_11", + "CMT_FIFO_L_LOGIC_OUTS1_9", + "CMT_FIFO_WW4B1_2", + "CMT_IN_FIFO_SCANIN1", + "CMT_FIFO_L_IMUX2_3", + "CMT_FIFO_L_LOGIC_OUTS9_7", + "CMT_FIFO_WW2A3_7", + "CMT_FIFO_SE4BEG1_1", + "CMT_FIFO_NE2A0_7", + "CMT_FIFO_NE4C2_4", + "CMT_FIFO_L_LOGIC_OUTS12_6", + "CMT_IN_FIFO_Q65", + "CMT_FIFO_NW4END2_10", + "CMT_FIFO_L_IMUX8_4", + "CMT_FIFO_EE4B3_0", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "CMT_FIFO_L_IMUX31_11", + "CMT_FIFO_L_LOGIC_OUTS15_11", + "CMT_FIFO_LH7_7", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "CMT_FIFO_EE4BEG0_0", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "CMT_FIFO_L_IMUX8_9", + "CMT_FIFO_L_IMUX29_6", + "CMT_FIFO_SW4END0_8", + "CMT_FIFO_L_IMUX37_1", + "CMT_OUT_FIFO_SCANIN2", + "CMT_FIFO_EE2BEG0_11", + "CMT_OUT_FIFO_D91", + "CMT_FIFO_SW4A0_1", + "CMT_FIFO_WW4A3_10", + "CMT_FIFO_L_LOGIC_OUTS6_4", + "CMT_FIFO_WW4END3_7", + "CMT_FIFO_NW4A3_0", + "CMT_FIFO_LH3_1", + "CMT_FIFO_LH5_3", + "CMT_FIFO_L_LOGIC_OUTS6_9", + "CMT_FIFO_L_IMUX7_5", + "CMT_FIFO_WW4END1_9", + "CMT_OUT_FIFO_Q50", + "CMT_FIFO_L_LOGIC_OUTS20_1", + "CMT_FIFO_LH7_2", + "CMT_FIFO_SE4BEG2_8", + "CMT_OUT_FIFO_ALMOSTFULL", + "CMT_FIFO_L_IMUX41_3", + "CMT_FIFO_SE4C0_1", + "CMT_FIFO_L_LOGIC_OUTS5_8", + "CMT_FIFO_SW2A2_1", + "CMT_FIFO_L_IMUX42_6", + "CMT_FIFO_EE4BEG0_1", + "CMT_FIFO_EE4BEG3_3", + "CMT_FIFO_L_IMUX17_7", + "CMT_FIFO_L_CTRL0_8", + "CMT_OUT_FIFO_D17", + "CMT_FIFO_L_LOGIC_OUTS22_1", + "CMT_FIFO_L_IMUX36_4", + "CMT_FIFO_NE2A0_11", + "CMT_FIFO_WW4END3_4", + "CMT_FIFO_SE2A1_11", + "CMT_FIFO_SE2A0_7", + "CMT_FIFO_WW4END1_11", + "CMT_FIFO_L_BYP5_10", + "CMT_FIFO_SW4END0_6", + "CMT_FIFO_SE4BEG1_8", + "CMT_FIFO_MONITOR_P_7", + "CMT_FIFO_L_LOGIC_OUTS19_0", + "CMT_OUT_FIFO_Q43", + "CMT_FIFO_NE4BEG3_0", + "CMT_FIFO_L_FAN1_11", + "CMT_OUT_FIFO_D43", + "CMT_FIFO_L_CLK0_1", + "CMT_FIFO_L_IMUX7_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "CMT_FIFO_SE4BEG2_4", + "CMT_FIFO_LH9_9", + "CMT_FIFO_L_IMUX30_1", + "CMT_FIFO_WW4A3_3", + "CMT_FIFO_WW2A2_1", + "CMT_FIFO_WW2A2_6", + "CMT_IN_FIFO_TESTMODEB", + "CMT_FIFO_WW4A2_3", + "CMT_FIFO_L_LOGIC_OUTS1_11", + "CMT_OUT_FIFO_D15", + "CMT_FIFO_WW4END2_10", + "CMT_FIFO_L_IMUX21_4", + "CMT_FIFO_SE2A0_4", + "CMT_FIFO_SW2A0_6", + "CMT_FIFO_WW4END0_7", + "CMT_FIFO_L_IMUX42_7", + "CMT_FIFO_EE4C3_2", + "CMT_FIFO_WR1END1_7", + "CMT_FIFO_NE4BEG1_2", + "CMT_FIFO_NE4BEG1_4", + "CMT_FIFO_L_IMUX12_8", + "CMT_FIFO_NE2A0_3", + "CMT_IN_FIFO_Q51", + "CMT_FIFO_L_IMUX22_3", + "CMT_FIFO_SW4END3_10", + "CMT_FIFO_NW2A1_11", + "CMT_FIFO_NE4BEG2_6", + "CMT_FIFO_WW2END2_8", + "CMT_FIFO_L_IMUX37_3", + "CMT_FIFO_EL1BEG1_11", + "CMT_FIFO_EE2BEG3_11", + "CMT_FIFO_L_LOGIC_OUTS17_8", + "CMT_FIFO_L_FAN2_8", + "CMT_IN_FIFO_D03", + "CMT_FIFO_SE4C2_6", + "CMT_FIFO_L_IMUX19_6", + "CMT_FIFO_SW2A1_6", + "CMT_FIFO_NE4C3_11", + "CMT_FIFO_L_IMUX32_9", + "CMT_FIFO_L_LOGIC_OUTS21_6", + "CMT_FIFO_NW4END3_1", + "CMT_FIFO_L_IMUX39_8", + "CMT_FIFO_SE2A2_6", + "CMT_FIFO_NW2A0_0", + "CMT_FIFO_L_IMUX36_0", + "CMT_FIFO_SE4BEG0_11", + "CMT_FIFO_L_IMUX13_3", + "CMT_FIFO_LH3_7", + "CMT_FIFO_EE2A0_11", + "CMT_FIFO_L_LOGIC_OUTS22_6", + "CMT_FIFO_L_LOGIC_OUTS11_6", + "CMT_FIFO_SE4BEG1_2", + "CMT_FIFO_WR1END2_5", + "CMT_FIFO_WL1END0_2", + "CMT_FIFO_EE4A3_0", + "CMT_FIFO_EE4BEG0_10", + "CMT_FIFO_NE4C2_3", + "CMT_FIFO_ER1BEG2_8", + "CMT_FIFO_L_LOGIC_OUTS13_8", + "CMT_FIFO_NE4C2_7", + "CMT_FIFO_EE4A0_5", + "CMT_FIFO_EL1BEG0_3", + "CMT_FIFO_WW4END0_1", + "CMT_FIFO_L_LOGIC_OUTS0_5", + "CMT_FIFO_L_CTRL0_6", + "CMT_FIFO_NE2A1_5", + "CMT_FIFO_L_IMUX12_1", + "CMT_FIFO_NE4C2_5", + "CMT_FIFO_WR1END2_3", + "CMT_FIFO_LH7_8", + "CMT_FIFO_WW4END3_2", + "CMT_FIFO_WW2END3_7", + "CMT_FIFO_SW4END3_0", + "CMT_FIFO_WR1END1_10", + "CMT_FIFO_WR1END3_11", + "CMT_FIFO_L_FAN6_4", + "CMT_FIFO_WW4C2_11", + "CMT_FIFO_L_BYP3_3", + "CMT_FIFO_EE2BEG1_8", + "CMT_IN_FIFO_Q00", + "CMT_OUT_FIFO_D74", + "CMT_FIFO_WW4END2_0", + "CMT_FIFO_L_IMUX15_7", + "CMT_FIFO_L_IMUX35_0", + "CMT_FIFO_L_LOGIC_OUTS4_0", + "CMT_FIFO_WW4A1_7", + "CMT_FIFO_SW4END0_11", + "CMT_FIFO_WW4B1_10", + "CMT_FIFO_L_IMUX46_3", + "CMT_IN_FIFO_Q44", + "CMT_FIFO_SW4A2_7", + "CMT_FIFO_L_IMUX26_8", + "CMT_FIFO_L_IMUX13_4", + "CMT_FIFO_SE4BEG2_1", + "CMT_FIFO_WW4END1_0", + "CMT_FIFO_L_FAN6_2", + "CMT_FIFO_LH12_2", + "CMT_FIFO_L_IMUX13_7", + "CMT_FIFO_L_LOGIC_OUTS16_4", + "CMT_FIFO_L_IMUX22_11", + "CMT_OUT_FIFO_SCANIN0", + "CMT_FIFO_L_IMUX27_7", + "CMT_FIFO_L_IMUX5_10", + "CMT_FIFO_WW4B3_7", + "CMT_FIFO_EE4C3_3", + "CMT_FIFO_LH2_11", + "CMT_FIFO_L_IMUX10_8", + "CMT_FIFO_WW2A2_9", + "CMT_FIFO_L_IMUX38_2", + "CMT_FIFO_WW4A1_0", + "CMT_FIFO_NE4C1_1", + "CMT_FIFO_L_FAN4_0", + "CMT_FIFO_L_FAN5_8", + "CMT_FIFO_L_IMUX47_0", + "CMT_FIFO_L_LOGIC_OUTS22_2", + "CMT_FIFO_L_IMUX6_6", + "CMT_FIFO_L_LOGIC_OUTS8_11", + "CMT_FIFO_L_LOGIC_OUTS13_0", + "CMT_FIFO_WW2END2_0", + "CMT_FIFO_LH5_8", + "CMT_FIFO_SE4BEG3_5", + "CMT_FIFO_L_IMUX18_7", + "CMT_FIFO_LH5_6", + "CMT_FIFO_L_LOGIC_OUTS3_4", + "CMT_OUT_FIFO_RDEN", + "CMT_FIFO_L_FAN5_3", + "CMT_FIFO_L_CLK1_9", + "CMT_FIFO_WW4A3_11", + "CMT_FIFO_L_IMUX16_10", + "CMT_FIFO_WW2A0_0", + "CMT_FIFO_EE4A2_4", + "CMT_FIFO_L_LOGIC_OUTS7_7", + "CMT_FIFO_WW2A3_0", + "CMT_FIFO_L_LOGIC_OUTS23_11", + "CMT_FIFO_L_IMUX6_9", + "CMT_FIFO_L_LOGIC_OUTS18_5", + "CMT_FIFO_L_IMUX36_1", + "CMT_FIFO_SW4A3_1", + "CMT_FIFO_SW4END3_11", + "CMT_FIFO_LH5_10", + "CMT_FIFO_L_IMUX17_5", + "CMT_OUT_FIFO_Q57", + "CMT_FIFO_L_IMUX4_3", + "CMT_IN_FIFO_Q33", + "CMT_FIFO_SW4A3_6", + "CMT_FIFO_WW4C1_8", + "CMT_OUT_FIFO_Q03", + "CMT_FIFO_WW2A3_1", + "CMT_FIFO_SW4END2_0", + "CMT_FIFO_L_LOGIC_OUTS4_7", + "CMT_FIFO_NW2A1_7", + "CMT_FIFO_L_FAN1_9", + "CMT_FIFO_L_IMUX13_10", + "CMT_FIFO_WL1END3_5", + "CMT_FIFO_L_LOGIC_OUTS7_8", + "CMT_FIFO_L_IMUX13_5", + "CMT_FIFO_EE2A0_8", + "CMT_FIFO_WW4C3_3", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "CMT_FIFO_NE2A1_6", + "CMT_FIFO_NE2A1_2", + "CMT_FIFO_L_IMUX12_9", + "CMT_FIFO_L_IMUX46_9", + "CMT_FIFO_WW4A2_11", + "CMT_FIFO_NE4C1_7", + "CMT_FIFO_L_LOGIC_OUTS14_10", + "CMT_FIFO_SW4A2_5", + "CMT_FIFO_L_IMUX31_5", + "CMT_FIFO_L_LOGIC_OUTS12_7", + "CMT_FIFO_ER1BEG1_7", + "CMT_FIFO_L_FAN2_6", + "CMT_FIFO_WW4END3_5", + "CMT_FIFO_NE4C0_3", + "CMT_FIFO_EL1BEG2_7", + "CMT_FIFO_L_FAN3_6", + "CMT_FIFO_SW2A2_9", + "CMT_FIFO_L_IMUX42_8", + "CMT_FIFO_EE4BEG3_0", + "CMT_FIFO_NE4C0_4", + "CMT_IN_FIFO_D62", + "CMT_FIFO_WW2END1_10", + "CMT_FIFO_L_IMUX32_2", + "CMT_FIFO_EE4C2_4", + "CMT_FIFO_SW4END0_2", + "CMT_FIFO_L_IMUX21_10", + "CMT_FIFO_NE4C2_9", + "CMT_FIFO_WL1END0_5", + "CMT_FIFO_NW4A2_8", + "CMT_FIFO_L_IMUX34_8", + "CMT_FIFO_SW4END0_5", + "CMT_FIFO_WW4END2_9", + "CMT_OUT_FIFO_WREN", + "CMT_FIFO_L_LOGIC_OUTS12_10", + "CMT_FIFO_WL1END2_2", + "CMT_FIFO_WW2A0_6", + "CMT_FIFO_L_IMUX0_0", + "CMT_FIFO_NW4A1_1", + "CMT_OUT_FIFO_D55", + "CMT_FIFO_EE2A3_5", + "CMT_FIFO_SW2A2_4", + "CMT_FIFO_L_IMUX46_8", + "CMT_FIFO_SE4BEG1_11", + "CMT_FIFO_NE4C3_9", + "CMT_FIFO_SE4BEG3_3", + "CMT_FIFO_EE4BEG0_5", + "CMT_FIFO_EE4BEG2_11", + "CMT_OUT_FIFO_D37", + "CMT_FIFO_LH8_9", + "CMT_FIFO_L_LOGIC_OUTS5_11", + "CMT_FIFO_NE4BEG1_9", + "CMT_FIFO_L_BYP2_2", + "CMT_FIFO_L_LOGIC_OUTS8_0", + "CMT_FIFO_WW4END0_10", + "CMT_FIFO_WW4A3_9", + "CMT_FIFO_ER1BEG2_4", + "CMT_FIFO_EL1BEG0_4", + "CMT_FIFO_L_LOGIC_OUTS19_11", + "CMT_FIFO_L_FAN3_2", + "CMT_FIFO_L_IMUX47_3", + "CMT_FIFO_EE2A3_7", + "CMT_FIFO_WR1END0_0", + "CMT_FIFO_L_LOGIC_OUTS11_1", + "CMT_FIFO_NE4C1_4", + "CMT_FIFO_L_LOGIC_OUTS12_5", + "CMT_FIFO_NE4BEG2_9", + "CMT_FIFO_EE2BEG3_1", + "CMT_FIFO_NE4BEG2_3", + "CMT_FIFO_SE2A1_9", + "CMT_FIFO_EE2A3_3", + "CMT_FIFO_L_BYP3_10", + "CMT_FIFO_NW4END1_6", + "CMT_FIFO_L_IMUX24_6", + "CMT_FIFO_L_IMUX38_1", + "CMT_FIFO_L_LOGIC_OUTS4_5", + "CMT_FIFO_EE2A1_1", + "CMT_FIFO_SW4A2_0", + "CMT_FIFO_EE4C0_4", + "CMT_FIFO_L_FAN7_1", + "CMT_FIFO_L_IMUX25_7", + "CMT_FIFO_WW2END1_9", + "CMT_FIFO_EL1BEG2_8", + "CMT_FIFO_EE4B0_2", + "CMT_FIFO_L_IMUX36_11", + "CMT_FIFO_L_IMUX6_1", + "CMT_IN_FIFO_Q77", + "CMT_FIFO_L_IMUX43_9", + "CMT_OUT_FIFO_D84", + "CMT_FIFO_EE4C0_8", + "CMT_IN_FIFO_Q23", + "CMT_FIFO_WL1END0_8", + "CMT_FIFO_L_LOGIC_OUTS9_5", + "CMT_IN_FIFO_Q31", + "CMT_FIFO_L_CLK0_7", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "CMT_FIFO_EE4C0_2", + "CMT_FIFO_L_LOGIC_OUTS6_7", + "CMT_FIFO_WW2A2_5", + "CMT_FIFO_L_IMUX25_4", + "CMT_FIFO_L_BYP6_9", + "CMT_FIFO_EE4A0_7", + "CMT_FIFO_EE2BEG2_10", + "CMT_FIFO_L_LOGIC_OUTS5_10", + "CMT_FIFO_EE2A3_1", + "CMT_FIFO_EL1BEG2_4", + "CMT_FIFO_WW4B1_8", + "CMT_FIFO_SE4C1_3", + "CMT_IN_FIFO_D71", + "CMT_FIFO_WW2END2_9", + "CMT_FIFO_SE4BEG0_6", + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "CMT_FIFO_L_IMUX42_0", + "CMT_IN_FIFO_Q62", + "CMT_FIFO_L_IMUX44_6", + "CMT_FIFO_WW4END1_5", + "CMT_FIFO_L_IMUX6_0", + "CMT_FIFO_L_IMUX32_6", + "CMT_FIFO_L_IMUX14_6", + "CMT_FIFO_NW4A0_9", + "CMT_FIFO_L_IMUX11_2", + "CMT_FIFO_EL1BEG3_7", + "CMT_FIFO_L_IMUX33_5", + "CMT_FIFO_L_IMUX32_3", + "CMT_FIFO_EE2A1_5", + "CMT_FIFO_NW2A0_8", + "CMT_OUT_FIFO_D45", + "CMT_FIFO_L_IMUX21_0", + "CMT_FIFO_WW4END2_8", + "CMT_FIFO_L_LOGIC_OUTS14_0", + "CMT_FIFO_L_IMUX19_10", + "CMT_FIFO_L_FAN7_4", + "CMT_FIFO_L_IMUX39_7", + "CMT_FIFO_L_LOGIC_OUTS22_8", + "CMT_OUT_FIFO_D71", + "CMT_FIFO_NE2A0_5", + "CMT_OUT_FIFO_Q70", + "CMT_FIFO_L_LOGIC_OUTS8_1", + "CMT_FIFO_WL1END3_3", + "CMT_FIFO_WW4C0_7", + "CMT_FIFO_L_FAN3_9", + "CMT_IN_FIFO_Q12", + "CMT_FIFO_L_IMUX43_4", + "CMT_FIFO_L_IMUX47_4", + "CMT_FIFO_WR1END3_8", + "CMT_FIFO_L_LOGIC_OUTS7_2", + "CMT_FIFO_L_BYP5_7", + "CMT_FIFO_L_IMUX38_9", + "CMT_FIFO_L_IMUX4_7", + "CMT_FIFO_EE2BEG2_0", + "CMT_FIFO_NE2A0_0", + "CMT_FIFO_L_LOGIC_OUTS18_6", + "CMT_FIFO_EE2BEG0_1", + "CMT_FIFO_EE4BEG1_3", + "CMT_FIFO_WW4A2_0", + "CMT_IN_FIFO_D00", + "CMT_FIFO_L_LOGIC_OUTS8_7", + "CMT_FIFO_SE4C0_4", + "CMT_FIFO_L_CLK1_0", + "CMT_FIFO_L_IMUX1_0", + "CMT_FIFO_SE2A1_2", + "CMT_FIFO_WW4A2_2", + "CMT_FIFO_SW2A0_2", + "CMT_FIFO_L_LOGIC_OUTS9_6", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "CMT_FIFO_L_IMUX16_2", + "CMT_FIFO_EE4BEG0_9", + "CMT_FIFO_EL1BEG1_2", + "CMT_FIFO_SE4BEG2_10", + "CMT_FIFO_EE4BEG0_11", + "CMT_FIFO_SE2A0_1", + "CMT_FIFO_L_IMUX43_0", + "CMT_FIFO_SW4END2_2", + "CMT_FIFO_NE4C1_6", + "CMT_FIFO_EL1BEG2_0", + "CMT_FIFO_LH1_10", + "CMT_IN_FIFO_D50", + "CMT_FIFO_WW4C0_8", + "CMT_FIFO_L_IMUX39_1", + "CMT_FIFO_NE2A3_1", + "CMT_FIFO_EE2BEG2_5", + "CMT_IN_FIFO_D13", + "CMT_FIFO_L_IMUX4_5", + "CMT_FIFO_NW4A3_11", + "CMT_FIFO_L_FAN7_5", + "CMT_FIFO_L_LOGIC_OUTS20_4", + "CMT_IN_FIFO_D81", + "CMT_FIFO_NW2A1_5", + "CMT_FIFO_L_IMUX31_3", + "CMT_FIFO_L_IMUX25_1", + "CMT_FIFO_SE2A2_2", + "CMT_FIFO_NW2A3_0", + "CMT_FIFO_WW2END0_10", + "CMT_FIFO_WW4END1_10", + "CMT_FIFO_SE4C3_3", + "CMT_FIFO_WL1END1_2", + "CMT_FIFO_EE4B2_0", + "CMT_FIFO_NE4BEG3_9", + "CMT_FIFO_L_LOGIC_OUTS10_1", + "CMT_FIFO_WL1END0_7", + "CMT_FIFO_L_IMUX23_7", + "CMT_FIFO_L_LOGIC_OUTS1_6", + "CMT_FIFO_L_IMUX15_1", + "CMT_FIFO_WW2A3_4", + "CMT_FIFO_L_BYP2_9", + "CMT_FIFO_L_LOGIC_OUTS1_4", + "CMT_FIFO_L_IMUX23_11", + "CMT_FIFO_NW4END1_11", + "CMT_FIFO_SW4END1_8", + "CMT_FIFO_NW4END2_11", + "CMT_IN_FIFO_Q21", + "CMT_FIFO_L_IMUX15_9", + "CMT_FIFO_L_IMUX41_2", + "CMT_FIFO_SE4C2_2", + "CMT_FIFO_EE4A0_1", + "CMT_FIFO_L_LOGIC_OUTS5_1", + "CMT_FIFO_EE2A1_8", + "CMT_FIFO_ER1BEG3_3", + "CMT_FIFO_L_IMUX7_3", + "CMT_IN_FIFO_Q54", + "CMT_FIFO_LH10_0", + "CMT_FIFO_L_FAN6_9", + "CMT_IN_FIFO_Q83", + "CMT_FIFO_EE4C0_10", + "CMT_OUT_FIFO_D70", + "CMT_FIFO_WL1END1_5", + "CMT_OUT_FIFO_D35", + "CMT_FIFO_L_IMUX6_10", + "CMT_FIFO_WW2A0_10", + "CMT_FIFO_ER1BEG0_8", + "CMT_FIFO_L_IMUX38_5", + "CMT_FIFO_SW2A0_9", + "CMT_FIFO_SE2A2_8", + "CMT_FIFO_WW4B1_11", + "CMT_FIFO_SW4END2_1", + "CMT_OUT_FIFO_Q53", + "CMT_FIFO_LH12_10", + "CMT_FIFO_WW4B3_4", + "CMT_IN_FIFO_D92", + "CMT_FIFO_L_IMUX42_3", + "CMT_FIFO_SW4A2_1", + "CMT_IN_FIFO_Q06", + "CMT_FIFO_NE4C0_11", + "CMT_FIFO_L_IMUX10_11", + "CMT_FIFO_NW2A1_10", + "CMT_FIFO_L_BYP4_1", + "CMT_FIFO_L_IMUX4_4", + "CMT_FIFO_LH10_9", + "CMT_FIFO_L_LOGIC_OUTS15_4", + "CMT_FIFO_L_IMUX9_9", + "CMT_FIFO_L_IMUX5_11", + "CMT_FIFO_WR1END2_10", + "CMT_OUT_FIFO_FULL", + "CMT_FIFO_L_IMUX45_6", + "CMT_FIFO_MONITOR_N_7", + "CMT_FIFO_EE4C1_8", + "CMT_FIFO_WW4B0_4", + "CMT_FIFO_L_CLK0_8", + "CMT_FIFO_WR1END1_6", + "CMT_FIFO_SW4END3_8", + "CMT_FIFO_WW2END0_6", + "CMT_FIFO_SW2A2_8", + "CMT_FIFO_LH9_11", + "CMT_FIFO_SW4A3_2", + "CMT_FIFO_WW4C0_1", + "CMT_FIFO_L_IMUX16_9", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "CMT_FIFO_ER1BEG0_4", + "CMT_FIFO_L_IMUX4_10", + "CMT_FIFO_WW4C3_8", + "CMT_FIFO_L_IMUX46_0", + "CMT_FIFO_L_LOGIC_OUTS2_3", + "CMT_FIFO_WL1END3_1", + "CMT_FIFO_L_FAN0_6", + "CMT_FIFO_WR1END3_10", + "CMT_FIFO_SE2A1_6", + "CMT_FIFO_SE2A0_11", + "CMT_FIFO_EE2A2_6", + "CMT_FIFO_L_BYP2_6", + "CMT_FIFO_ER1BEG2_5", + "CMT_FIFO_EE4B1_7", + "CMT_FIFO_NW4END0_4", + "CMT_FIFO_EE2A0_10", + "CMT_FIFO_L_IMUX1_1", + "CMT_FIFO_SW4A1_3", + "CMT_FIFO_SW2A2_11", + "CMT_FIFO_EE4BEG3_11", + "CMT_FIFO_NE2A3_6", + "CMT_FIFO_EE4B1_0", + "CMT_FIFO_L_IMUX34_9", + "CMT_FIFO_NW4A3_4", + "CMT_FIFO_L_IMUX19_2", + "CMT_FIFO_L_IMUX43_10", + "CMT_FIFO_WW2END1_6", + "CMT_FIFO_L_FAN0_11", + "CMT_OUT_FIFO_D53", + "CMT_FIFO_SW4END3_1", + "CMT_FIFO_L_IMUX21_3", + "CMT_FIFO_WW4B3_2", + "CMT_FIFO_NW2A0_6", + "CMT_FIFO_L_IMUX5_3", + "CMT_FIFO_SW4A0_5", + "CMT_FIFO_EE4A3_8", + "CMT_OUT_FIFO_D93", + "CMT_FIFO_L_LOGIC_OUTS5_4", + "CMT_FIFO_WW4A0_6", + "CMT_FIFO_L_IMUX7_6", + "CMT_FIFO_WW4C3_4", + "CMT_FIFO_L_BYP1_7", + "CMT_FIFO_EE2A0_1", + "CMT_FIFO_L_IMUX2_6", + "CMT_FIFO_L_IMUX28_9", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "CMT_FIFO_WW4A2_6", + "CMT_FIFO_L_IMUX36_6", + "CMT_FIFO_NW2A3_1", + "CMT_FIFO_WW4END0_6", + "CMT_FIFO_L_IMUX25_0", + "CMT_FIFO_L_IMUX47_11", + "CMT_FIFO_L_IMUX16_5", + "CMT_FIFO_L_IMUX25_8", + "CMT_FIFO_EL1BEG1_6", + "CMT_FIFO_NE4C0_6", + "CMT_FIFO_NE4BEG3_2", + "CMT_FIFO_SW2A3_11", + "CMT_FIFO_LH4_8", + "CMT_FIFO_LH5_5", + "CMT_FIFO_EE4C1_9", + "CMT_FIFO_L_IMUX6_2", + "CMT_FIFO_SE4C2_3", + "CMT_FIFO_L_LOGIC_OUTS15_1", + "CMT_FIFO_WW2A1_3", + "CMT_FIFO_NW4END2_2", + "CMT_FIFO_WR1END0_3", + "CMT_FIFO_L_LOGIC_OUTS8_10", + "CMT_IN_FIFO_Q80", + "CMT_FIFO_L_IMUX1_5", + "CMT_FIFO_NE2A3_7", + "CMT_FIFO_WR1END2_4", + "CMT_FIFO_SW4A2_4", + "CMT_FIFO_EE4A2_3", + "CMT_FIFO_NE4BEG3_7", + "CMT_FIFO_EE4BEG2_4", + "CMT_FIFO_LH9_1", + "CMT_FIFO_NW4A1_3", + "CMT_FIFO_MONITOR_N_9", + "CMT_FIFO_L_LOGIC_OUTS12_9", + "CMT_IN_FIFO_D66", + "CMT_FIFO_L_LOGIC_OUTS5_0", + "CMT_OUT_FIFO_D02", + "CMT_FIFO_LH11_0", + "CMT_FIFO_NE4C0_9", + "CMT_FIFO_NE2A3_0", + "CMT_FIFO_NE2A1_0", + "CMT_OUT_FIFO_D66", + "CMT_OUT_FIFO_Q64", + "CMT_FIFO_SE4C2_5", + "CMT_FIFO_L_IMUX12_0", + "CMT_FIFO_WW2END1_0", + "CMT_FIFO_NE2A2_1", + "CMT_FIFO_L_IMUX23_9", + "CMT_FIFO_L_LOGIC_OUTS13_2", + "CMT_IN_FIFO_D53", + "CMT_FIFO_EE4A0_10", + "CMT_FIFO_L_IMUX36_5", + "CMT_FIFO_L_IMUX17_11", + "CMT_FIFO_SW4END0_3", + "CMT_OUT_FIFO_Q40", + "CMT_FIFO_NW4A0_6", + "CMT_FIFO_ER1BEG2_11", + "CMT_FIFO_NW4A1_9", + "CMT_FIFO_EE2A2_4", + "CMT_OUT_FIFO_SCANOUT1", + "CMT_FIFO_L_IMUX45_11", + "CMT_IN_FIFO_Q32", + "CMT_IN_FIFO_D41", + "CMT_FIFO_WR1END0_11", + "CMT_FIFO_WW4END3_1", + "CMT_FIFO_SW2A1_5", + "CMT_FIFO_EL1BEG1_1", + "CMT_FIFO_L_IMUX29_5", + "CMT_FIFO_NW4END2_8", + "CMT_FIFO_EE4A3_5", + "CMT_OUT_FIFO_D77", + "CMT_FIFO_L_IMUX29_7", + "CMT_FIFO_L_LOGIC_OUTS12_3", + "CMT_FIFO_EE2A2_3", + "CMT_FIFO_LH7_10", + "CMT_FIFO_SW4A0_2", + "CMT_FIFO_EE4BEG3_6", + "CMT_FIFO_SW4A1_5", + "CMT_FIFO_L_IMUX29_11", + "CMT_FIFO_EE4B1_11", + "CMT_FIFO_WL1END2_8", + "CMT_FIFO_WW4END2_3", + "CMT_FIFO_L_CLK0_9", + "CMT_FIFO_L_LOGIC_OUTS11_3", + "CMT_FIFO_WL1END1_6", + "CMT_FIFO_EE4C3_7", + "CMT_FIFO_EL1BEG1_0", + "CMT_FIFO_LH1_7", + "CMT_FIFO_WW2END0_5", + "CMT_FIFO_WW2A0_11", + "CMT_FIFO_EE2BEG0_3", + "CMT_IN_FIFO_Q56", + "CMT_FIFO_SW4A3_9", + "CMT_IN_FIFO_Q37", + "CMT_FIFO_LH10_10", + "CMT_FIFO_L_LOGIC_OUTS8_8", + "CMT_FIFO_L_IMUX41_7", + "CMT_FIFO_L_IMUX1_11", + "CMT_FIFO_L_CTRL0_0", + "CMT_FIFO_WL1END2_10", + "CMT_FIFO_EE2A0_2", + "CMT_FIFO_NE4BEG0_7", + "CMT_FIFO_EL1BEG0_7", + "CMT_FIFO_EE2BEG1_10", + "CMT_OUT_FIFO_D63", + "CMT_FIFO_SE4C0_7", + "CMT_FIFO_L_IMUX30_11", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "CMT_FIFO_EE4BEG0_7", + "CMT_FIFO_L_FAN1_1", + "CMT_FIFO_EE4B2_10", + "CMT_FIFO_SW2A0_7", + "CMT_FIFO_WW2END1_7", + "CMT_FIFO_WL1END3_8", + "CMT_FIFO_SE2A0_6", + "CMT_FIFO_SW2A0_5", + "CMT_FIFO_EE4A3_10", + "CMT_OUT_FIFO_D41", + "CMT_FIFO_NE2A3_4", + "CMT_IN_FIFO_Q25", + "CMT_FIFO_LH6_8", + "CMT_FIFO_EE4A3_2", + "CMT_FIFO_L_CTRL0_9", + "CMT_FIFO_L_IMUX3_2", + "CMT_FIFO_LH4_9", + "CMT_FIFO_L_IMUX19_5", + "CMT_FIFO_SE4BEG3_2", + "CMT_FIFO_L_IMUX16_1", + "CMT_FIFO_NW2A2_5", + "CMT_FIFO_WW4B1_1", + "CMT_FIFO_WW2A3_10", + "CMT_FIFO_L_IMUX9_4", + "CMT_FIFO_WW2END0_8", + "CMT_FIFO_L_FAN7_7", + "CMT_FIFO_L_LOGIC_OUTS3_11", + "CMT_FIFO_NW4END0_1", + "CMT_FIFO_NE4C3_10", + "CMT_FIFO_LH12_5", + "CMT_FIFO_LH2_4", + "CMT_FIFO_NE4BEG3_8", + "CMT_FIFO_EE2A1_10", + "CMT_FIFO_WW4END0_0", + "CMT_OUT_FIFO_D83", + "CMT_FIFO_SE4BEG0_3", + "CMT_FIFO_SW4A1_1", + "CMT_FIFO_LH2_8", + "CMT_FIFO_EE4B2_3", + "CMT_FIFO_L_IMUX7_1", + "CMT_FIFO_L_LOGIC_OUTS14_9", + "CMT_FIFO_WW4C0_5", + "CMT_FIFO_L_LOGIC_OUTS13_11", + "CMT_FIFO_EL1BEG2_1", + "CMT_OUT_FIFO_TESTWRITEDISB", + "CMT_FIFO_WW2A1_10", + "CMT_FIFO_ER1BEG3_11", + "CMT_IN_FIFO_Q01", + "CMT_FIFO_SE2A3_9", + "CMT_OUT_FIFO_D16", + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "CMT_FIFO_L_BYP3_1", + "CMT_FIFO_L_CTRL1_1", + "CMT_FIFO_EL1BEG2_9", + "CMT_IN_FIFO_D40", + "CMT_FIFO_L_LOGIC_OUTS21_7", + "CMT_FIFO_L_IMUX37_8", + "CMT_FIFO_SW2A1_1", + "CMT_FIFO_L_IMUX47_10", + "CMT_FIFO_NE2A0_10", + "CMT_IN_FIFO_D63", + "CMT_FIFO_SW2A0_4", + "CMT_FIFO_ER1BEG2_2", + "CMT_FIFO_NW4A1_4", + "CMT_FIFO_MONITOR_P_0", + "CMT_FIFO_NE4BEG0_11", + "CMT_FIFO_NW2A1_8", + "CMT_FIFO_EL1BEG3_3", + "CMT_FIFO_EE4B2_6", + "CMT_FIFO_WW4END1_3", + "CMT_FIFO_NE4BEG1_8", + "CMT_FIFO_LH3_6", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "CMT_FIFO_L_IMUX22_1", + "CMT_FIFO_L_IMUX43_2", + "CMT_FIFO_L_IMUX45_1", + "CMT_IN_FIFO_D90", + "CMT_FIFO_SE4C2_7", + "CMT_FIFO_SW4A1_10", + "CMT_FIFO_EE4C2_9", + "CMT_FIFO_WW4B2_11", + "CMT_FIFO_NE4BEG3_3", + "CMT_FIFO_L_LOGIC_OUTS4_2", + "CMT_FIFO_LH11_10", + "CMT_FIFO_L_IMUX22_6", + "CMT_FIFO_L_LOGIC_OUTS3_6", + "CMT_FIFO_EE2A1_2", + "CMT_FIFO_L_LOGIC_OUTS23_1", + "CMT_FIFO_NW4END3_11", + "CMT_OUT_FIFO_Q67", + "CMT_IN_FIFO_Q81", + "CMT_FIFO_L_IMUX0_4", + "CMT_FIFO_EE4B3_4", + "CMT_FIFO_ER1BEG0_0", + "CMT_FIFO_L_LOGIC_OUTS9_2", + "CMT_FIFO_EE2A0_3", + "CMT_FIFO_EE2BEG0_9", + "CMT_FIFO_L_IMUX14_0", + "CMT_FIFO_L_FAN3_11", + "CMT_FIFO_EE4C3_1", + "CMT_FIFO_L_IMUX26_6", + "CMT_FIFO_WR1END1_3", + "CMT_FIFO_SW2A3_4", + "CMT_FIFO_EE4B0_10", + "CMT_FIFO_L_LOGIC_OUTS17_2", + "CMT_FIFO_EE4B3_3", + "CMT_OUT_FIFO_SCANENB", + "CMT_FIFO_SE4C2_8", + "CMT_FIFO_NW4END0_6", + "CMT_FIFO_SW2A0_0", + "CMT_FIFO_L_IMUX22_2", + "CMT_FIFO_L_LOGIC_OUTS16_3", + "CMT_FIFO_L_BYP5_3", + "CMT_FIFO_WW4END3_3", + "CMT_FIFO_SE4BEG3_11", + "CMT_FIFO_SE4C3_11", + "CMT_FIFO_WL1END2_0", + "CMT_FIFO_L_LOGIC_OUTS15_2", + "CMT_FIFO_L_BYP2_7", + "CMT_FIFO_L_IMUX10_1", + "CMT_FIFO_L_LOGIC_OUTS5_3", + "CMT_FIFO_L_FAN7_11", + "CMT_FIFO_EE4B1_4", + "CMT_FIFO_WW4B0_0", + "CMT_FIFO_L_LOGIC_OUTS7_5", + "CMT_FIFO_NW2A0_10", + "CMT_FIFO_WW2END3_1", + "CMT_FIFO_SW2A3_1", + "CMT_FIFO_ER1BEG1_6", + "CMT_FIFO_L_CLK0_10", + "CMT_FIFO_EE4BEG0_8", + "CMT_FIFO_L_LOGIC_OUTS6_5", + "CMT_FIFO_L_FAN4_5", + "CMT_FIFO_L_IMUX1_3", + "CMT_FIFO_WW4END3_11", + "CMT_FIFO_WL1END0_3", + "CMT_FIFO_EE2A2_8", + "CMT_FIFO_L_IMUX8_10", + "CMT_FIFO_SE2A0_10", + "CMT_FIFO_L_IMUX19_8", + "CMT_IN_FIFO_D43", + "CMT_FIFO_L_LOGIC_OUTS2_0", + "CMT_FIFO_L_LOGIC_OUTS20_5", + "CMT_FIFO_L_IMUX26_11", + "CMT_FIFO_SE4BEG1_9", + "CMT_FIFO_L_IMUX39_10", + "CMT_FIFO_WW2END2_3", + "CMT_FIFO_L_IMUX7_11", + "CMT_FIFO_LH1_2", + "CMT_FIFO_NW2A0_7", + "CMT_FIFO_EE4B3_11", + "CMT_FIFO_SW4END2_6", + "CMT_FIFO_EE4BEG3_2", + "CMT_FIFO_L_LOGIC_OUTS18_1", + "CMT_FIFO_WR1END3_1", + "CMT_FIFO_WW2A2_11", + "CMT_FIFO_L_LOGIC_OUTS5_2", + "CMT_OUT_FIFO_Q91", + "CMT_FIFO_L_IMUX28_6", + "CMT_FIFO_L_PHASER_RDCLK", + "CMT_FIFO_L_LOGIC_OUTS9_9", + "CMT_FIFO_ER1BEG3_7", + "CMT_FIFO_L_CLK1_7", + "CMT_FIFO_NW2A3_7", + "CMT_FIFO_L_LOGIC_OUTS13_6", + "CMT_FIFO_L_BYP5_5", + "CMT_IN_FIFO_Q35", + "CMT_FIFO_L_LOGIC_OUTS22_7", + "CMT_FIFO_L_LOGIC_OUTS1_0", + "CMT_FIFO_SE4BEG1_6", + "CMT_FIFO_WW4END0_5", + "CMT_FIFO_L_IMUX10_6", + "CMT_FIFO_L_LOGIC_OUTS7_10", + "CMT_FIFO_L_FAN6_1", + "CMT_FIFO_LH8_4", + "CMT_FIFO_L_IMUX33_4", + "CMT_FIFO_L_IMUX2_5", + "CMT_FIFO_L_LOGIC_OUTS20_11", + "CMT_FIFO_NE4C3_3", + "CMT_FIFO_L_LOGIC_OUTS4_3", + "CMT_FIFO_ER1BEG0_3", + "CMT_FIFO_NE4BEG2_1", + "CMT_FIFO_EE2A0_6", + "CMT_FIFO_WW4B1_6", + "CMT_FIFO_WL1END1_3", + "CMT_FIFO_EE4A2_6", + "CMT_FIFO_SW4END3_3", + "CMT_FIFO_NE4BEG0_4", + "CMT_OUT_FIFO_D65", + "CMT_FIFO_L_IMUX31_1", + "CMT_FIFO_WL1END0_1", + "CMT_FIFO_L_IMUX43_8", + "CMT_FIFO_NW4END3_9", + "CMT_FIFO_NE2A2_5", + "CMT_FIFO_WW4B3_10", + "CMT_FIFO_L_IMUX37_6", + "CMT_FIFO_L_FAN7_10", + "CMT_FIFO_L_IMUX27_2", + "CMT_FIFO_L_FAN6_5", + "CMT_FIFO_L_IMUX32_10", + "CMT_FIFO_L_IMUX28_2", + "CMT_FIFO_WW4C3_10", + "CMT_FIFO_NE2A1_9", + "CMT_FIFO_NW4A3_1", + "FIFO_DQS_IOTOPHASER_33", + "CMT_FIFO_L_IMUX24_1", + "CMT_FIFO_L_IMUX20_10", + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "CMT_FIFO_LH6_10", + "CMT_FIFO_WW2A0_5", + "CMT_IN_FIFO_D56", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_2", + "CMT_FIFO_L_BYP5_1", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "CMT_FIFO_EE4C2_10", + "CMT_FIFO_L_IMUX44_3", + "CMT_FIFO_L_IMUX12_2", + "CMT_FIFO_L_IMUX36_10", + "CMT_FIFO_EE2A1_9", + "CMT_OUT_FIFO_D40", + "CMT_FIFO_L_IMUX14_7", + "CMT_FIFO_NE4C2_10", + "CMT_FIFO_WW2END2_6", + "CMT_FIFO_L_IMUX47_9", + "CMT_FIFO_L_LOGIC_OUTS2_8", + "CMT_FIFO_L_BYP4_8", + "CMT_FIFO_EE2BEG2_11", + "CMT_FIFO_EE4B0_9", + "CMT_FIFO_EE2BEG0_7", + "CMT_FIFO_LH2_5", + "CMT_FIFO_L_LOGIC_OUTS14_4", + "CMT_FIFO_L_IMUX23_6", + "CMT_FIFO_L_IMUX14_3", + "CMT_FIFO_NE2A2_3", + "CMT_FIFO_L_IMUX26_10", + "CMT_FIFO_L_LOGIC_OUTS3_2", + "CMT_FIFO_EE2BEG3_2", + "CMT_IN_FIFO_Q61", + "CMT_FIFO_L_IMUX11_0", + "CMT_OUT_FIFO_WRCLK", + "CMT_FIFO_LH8_11", + "CMT_FIFO_L_IMUX0_10", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "CMT_FIFO_L_IMUX3_11", + "CMT_FIFO_EL1BEG0_9", + "CMT_FIFO_NE4BEG1_3", + "CMT_OUT_FIFO_D51", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "CMT_FIFO_L_IMUX47_1", + "CMT_FIFO_WW4END0_2", + "CMT_IN_FIFO_Q53", + "CMT_IN_FIFO_Q24", + "CMT_FIFO_WL1END2_1", + "CMT_FIFO_NE4C2_2", + "CMT_FIFO_LH9_7", + "CMT_FIFO_SE2A1_10", + "CMT_FIFO_L_IMUX44_5", + "CMT_IN_FIFO_Q71", + "CMT_FIFO_L_FAN7_0", + "CMT_FIFO_L_IMUX24_10", + "CMT_FIFO_L_LOGIC_OUTS22_3", + "CMT_OUT_FIFO_D46", + "CMT_FIFO_SE2A1_1", + "CMT_FIFO_L_IMUX11_7", + "CMT_FIFO_NW2A3_8", + "CMT_FIFO_WW2END2_4", + "CMT_IN_FIFO_RDCLK", + "CMT_FIFO_L_IMUX8_11", + "CMT_FIFO_SW4END0_10", + "CMT_FIFO_NW4END3_6", + "CMT_FIFO_NW2A2_0", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "CMT_FIFO_L_IMUX27_8", + "CMT_FIFO_EE4C1_5", + "CMT_FIFO_L_IMUX11_1", + "CMT_FIFO_SE2A1_7", + "CMT_FIFO_L_LOGIC_OUTS11_0", + "CMT_FIFO_L_FAN0_8", + "CMT_FIFO_NW4A1_8", + "CMT_FIFO_L_IMUX40_8", + "CMT_IN_FIFO_ALMOSTFULL", + "CMT_FIFO_EE2BEG3_9", + "CMT_FIFO_LH10_8", + "CMT_FIFO_EE4C0_6", + "CMT_FIFO_EL1BEG2_6", + "CMT_FIFO_L_IMUX1_9", + "CMT_OUT_FIFO_TESTMODEB", + "CMT_FIFO_LH4_1", + "CMT_FIFO_SE4C0_9", + "CMT_FIFO_L_LOGIC_OUTS18_2", + "CMT_IN_FIFO_Q92", + "CMT_IN_FIFO_TESTREADDISB", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "CMT_FIFO_L_CLK1_1", + "CMT_FIFO_LH11_7", + "CMT_FIFO_WR1END0_2", + "CMT_FIFO_EE4C2_6", + "CMT_FIFO_L_LOGIC_OUTS13_7", + "CMT_FIFO_L_BYP6_0", + "CMT_FIFO_L_CLK1_6", + "CMT_FIFO_L_LOGIC_OUTS12_1", + "CMT_FIFO_LH7_5", + "CMT_FIFO_L_IMUX38_8", + "CMT_FIFO_EE4C1_1", + "CMT_FIFO_L_CLK1_3", + "CMT_FIFO_L_IMUX7_7", + "CMT_FIFO_SW4A2_8", + "CMT_FIFO_EE2A2_11", + "CMT_FIFO_WW4C1_1", + "CMT_FIFO_L_FAN2_10", + "CMT_IN_FIFO_Q04", + "CMT_FIFO_L_FAN5_6", + "CMT_FIFO_L_IMUX8_8", + "CMT_FIFO_NE2A3_5", + "CMT_FIFO_SW2A0_8", + "CMT_FIFO_L_IMUX40_10", + "CMT_FIFO_SW2A1_3", + "CMT_FIFO_L_IMUX20_4", + "CMT_FIFO_L_IMUX33_2", + "CMT_FIFO_LH10_1", + "CMT_OUT_FIFO_D86", + "CMT_FIFO_L_IMUX16_7", + "CMT_FIFO_EL1BEG1_4", + "CMT_FIFO_L_LOGIC_OUTS20_6", + "CMT_FIFO_LH10_7", + "CMT_FIFO_L_CLK1_2", + "CMT_FIFO_L_LOGIC_OUTS1_8", + "CMT_IN_FIFO_Q87", + "CMT_FIFO_LH4_7", + "CMT_FIFO_L_IMUX29_0", + "CMT_FIFO_WL1END1_8", + "CMT_OUT_FIFO_D33", + "CMT_FIFO_EE4C2_2", + "CMT_IN_FIFO_D91", + "CMT_FIFO_L_IMUX14_2", + "CMT_FIFO_WL1END0_6", + "CMT_FIFO_SW4A1_11", + "CMT_FIFO_L_BYP5_2", + "CMT_FIFO_L_LOGIC_OUTS7_0", + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "CMT_FIFO_LH5_7", + "CMT_FIFO_L_IMUX24_4", + "CMT_FIFO_L_LOGIC_OUTS21_1", + "CMT_FIFO_L_IMUX27_0", + "CMT_FIFO_L_IMUX38_6", + "CMT_FIFO_L_IMUX17_3", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "CMT_FIFO_LH11_8", + "CMT_IN_FIFO_SCANOUT1", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_9", + "CMT_FIFO_L_IMUX43_1", + "CMT_FIFO_WW2END0_9", + "CMT_FIFO_EL1BEG0_0", + "CMT_FIFO_L_IMUX45_2", + "CMT_IN_FIFO_D22", + "CMT_FIFO_WR1END3_3", + "CMT_FIFO_EL1BEG0_6", + "CMT_FIFO_EE4A1_10", + "CMT_FIFO_L_IMUX20_9", + "CMT_FIFO_NW4A2_6", + "CMT_FIFO_L_LOGIC_OUTS2_5", + "CMT_FIFO_NW4A3_2", + "CMT_FIFO_L_IMUX39_6", + "CMT_FIFO_L_BYP4_5", + "CMT_FIFO_SE4BEG3_7", + "CMT_FIFO_MONITOR_P_6", + "CMT_FIFO_MONITOR_P_8", + "CMT_FIFO_EE4A2_1", + "CMT_FIFO_L_LOGIC_OUTS3_5", + "CMT_FIFO_LH11_1", + "CMT_FIFO_MONITOR_N_6", + "CMT_FIFO_LH12_1", + "CMT_FIFO_WW4B3_9", + "CMT_FIFO_WR1END1_2", + "CMT_FIFO_L_IMUX11_8", + "CMT_FIFO_EE2A1_4", + "CMT_FIFO_SE2A0_8", + "CMT_FIFO_SW4END0_0", + "CMT_FIFO_SE4BEG0_10", + "CMT_FIFO_L_BYP2_3", + "CMT_IN_FIFO_D55", + "CMT_FIFO_NW2A3_2", + "CMT_FIFO_SW4A3_7", + "CMT_FIFO_LH9_10", + "CMT_FIFO_L_IMUX44_9", + "CMT_FIFO_L_IMUX1_2", + "CMT_FIFO_L_IMUX4_0", + "CMT_FIFO_MONITOR_N_2", + "CMT_FIFO_L_LOGIC_OUTS20_10", + "CMT_FIFO_L_IMUX37_11", + "CMT_FIFO_L_IMUX25_5", + "CMT_FIFO_NE4BEG1_10", + "CMT_IN_FIFO_Q26", + "CMT_FIFO_L_LOGIC_OUTS8_4", + "CMT_FIFO_EE4BEG1_7", + "CMT_FIFO_L_IMUX17_4", + "CMT_FIFO_L_LOGIC_OUTS9_8", + "CMT_FIFO_L_BYP0_5", + "CMT_FIFO_SE4C0_0", + "CMT_IN_FIFO_Q20", + "CMT_FIFO_LH3_2", + "CMT_FIFO_EE2BEG3_5", + "CMT_IN_FIFO_Q66", + "CMT_FIFO_WL1END1_0", + "CMT_FIFO_EE4BEG0_3", + "CMT_FIFO_L_LOGIC_OUTS18_8", + "CMT_FIFO_WW4B2_5", + "CMT_FIFO_SW4END2_7", + "CMT_FIFO_NW4A1_10", + "CMT_FIFO_L_LOGIC_OUTS4_4", + "CMT_FIFO_L_FAN2_11", + "CMT_FIFO_L_FAN3_4", + "CMT_FIFO_WW4C2_9", + "CMT_FIFO_WR1END3_5", + "CMT_OUT_FIFO_Q72", + "CMT_FIFO_WW4B0_5", + "CMT_FIFO_L_IMUX37_4", + "CMT_FIFO_L_IMUX1_4", + "CMT_FIFO_L_LOGIC_OUTS15_10", + "CMT_FIFO_L_BYP0_2", + "CMT_FIFO_L_IMUX4_11", + "CMT_FIFO_WW2END1_4", + "CMT_IN_FIFO_D61", + "CMT_FIFO_L_IMUX41_8", + "CMT_FIFO_L_IMUX3_9", + "CMT_FIFO_WW4B1_3", + "FIFO_DQS_IOTOPHASER_11", + "CMT_FIFO_NW4A2_9", + "CMT_FIFO_L_LOGIC_OUTS1_5", + "CMT_FIFO_WR1END1_8", + "CMT_FIFO_L_LOGIC_OUTS17_3", + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "CMT_FIFO_L_CLK0_11", + "CMT_FIFO_LH1_9", + "CMT_FIFO_L_IMUX41_11", + "CMT_FIFO_L_IMUX8_1", + "CMT_FIFO_L_IMUX44_11", + "CMT_FIFO_NW2A3_11", + "CMT_OUT_FIFO_D72", + "CMT_FIFO_L_LOGIC_OUTS19_3", + "CMT_FIFO_L_IMUX33_0" + ], + "pips": { + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_1->CMT_OUT_FIFO_D15": { + "src_wire": "CMT_FIFO_L_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q76->CMT_FIFO_L_LOGIC_OUTS9_9": { + "src_wire": "CMT_IN_FIFO_Q76", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS11_4": { + "src_wire": "CMT_OUT_FIFO_Q42", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_11->CMT_IN_FIFO_D90": { + "src_wire": "CMT_FIFO_L_IMUX26_11", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D90", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_4->CMT_IN_FIFO_D41": { + "src_wire": "CMT_FIFO_L_IMUX40_4", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D41", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS20_5": { + "src_wire": "CMT_OUT_FIFO_Q53", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS20_0": { + "src_wire": "CMT_OUT_FIFO_Q03", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_0->CMT_OUT_FIFO_D04": { + "src_wire": "CMT_FIFO_L_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D04", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_8->CMT_OUT_FIFO_D66": { + "src_wire": "CMT_FIFO_L_IMUX7_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D66", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS11_10": { + "src_wire": "CMT_OUT_FIFO_Q82", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS1_11": { + "src_wire": "CMT_IN_FIFO_Q93", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_3->CMT_IN_FIFO_D33": { + "src_wire": "CMT_FIFO_L_IMUX42_3", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D33", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_1->CMT_OUT_FIFO_D10": { + "src_wire": "CMT_FIFO_L_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS20_9": { + "src_wire": "CMT_OUT_FIFO_Q73", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_10->CMT_IN_FIFO_D81": { + "src_wire": "CMT_FIFO_L_IMUX40_10", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D81", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS19_11": { + "src_wire": "CMT_OUT_FIFO_Q91", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_0->CMT_OUT_FIFO_D00": { + "src_wire": "CMT_FIFO_L_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D00", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_0->CMT_IN_FIFO_D02": { + "src_wire": "CMT_FIFO_L_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D02", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_11->CMT_OUT_FIFO_D93": { + "src_wire": "CMT_FIFO_L_IMUX38_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D93", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q17->CMT_FIFO_L_LOGIC_OUTS13_1": { + "src_wire": "CMT_IN_FIFO_Q17", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_0->CMT_IN_FIFO_D01": { + "src_wire": "CMT_FIFO_L_IMUX40_0", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D01", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS12_5": { + "src_wire": "CMT_IN_FIFO_Q54", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_1->CMT_IN_FIFO_D12": { + "src_wire": "CMT_FIFO_L_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS19_10": { + "src_wire": "CMT_OUT_FIFO_Q81", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_9->CMT_OUT_FIFO_D70": { + "src_wire": "CMT_FIFO_L_IMUX28_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D70", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q15->CMT_FIFO_L_LOGIC_OUTS8_1": { + "src_wire": "CMT_IN_FIFO_Q15", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_1->CMT_IN_FIFO_D13": { + "src_wire": "CMT_FIFO_L_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_2->CMT_OUT_FIFO_D26": { + "src_wire": "CMT_FIFO_L_IMUX7_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D26", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS5_10": { + "src_wire": "CMT_IN_FIFO_Q82", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q37->CMT_FIFO_L_LOGIC_OUTS13_3": { + "src_wire": "CMT_IN_FIFO_Q37", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_10->CMT_OUT_FIFO_D82": { + "src_wire": "CMT_FIFO_L_IMUX39_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D82", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_3->CMT_OUT_FIFO_D34": { + "src_wire": "CMT_FIFO_L_IMUX12_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D34", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_11->CMT_OUT_FIFO_D97": { + "src_wire": "CMT_FIFO_L_IMUX6_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D97", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_2->CMT_OUT_FIFO_D23": { + "src_wire": "CMT_FIFO_L_IMUX38_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D23", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_8->CMT_OUT_FIFO_D61": { + "src_wire": "CMT_FIFO_L_IMUX21_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D61", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_0->CMT_OUT_FIFO_D05": { + "src_wire": "CMT_FIFO_L_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D05", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_11->CMT_IN_FIFO_D91": { + "src_wire": "CMT_FIFO_L_IMUX40_11", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D91", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_4->CMT_OUT_FIFO_D41": { + "src_wire": "CMT_FIFO_L_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D41", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_3->CMT_OUT_FIFO_D31": { + "src_wire": "CMT_FIFO_L_IMUX21_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D31", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS11_6": { + "src_wire": "CMT_OUT_FIFO_Q56", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_3->CMT_IN_FIFO_D32": { + "src_wire": "CMT_FIFO_L_IMUX36_3", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D32", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS13_5": { + "src_wire": "CMT_IN_FIFO_Q57", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS20_7": { + "src_wire": "CMT_OUT_FIFO_Q67", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_3->CMT_OUT_FIFO_D33": { + "src_wire": "CMT_FIFO_L_IMUX38_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D33", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_3->CMT_OUT_FIFO_D37": { + "src_wire": "CMT_FIFO_L_IMUX6_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D37", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_4->CMT_IN_FIFO_D42": { + "src_wire": "CMT_FIFO_L_IMUX36_4", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D42", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS11_7": { + "src_wire": "CMT_OUT_FIFO_Q66", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_11->CMT_OUT_FIFO_D91": { + "src_wire": "CMT_FIFO_L_IMUX21_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D91", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_7->CMT_OUT_FIFO_RDEN": { + "src_wire": "CMT_FIFO_L_IMUX6_7", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS5_11": { + "src_wire": "CMT_IN_FIFO_Q92", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_10->CMT_IN_FIFO_D80": { + "src_wire": "CMT_FIFO_L_IMUX26_10", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D80", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_2->CMT_OUT_FIFO_D21": { + "src_wire": "CMT_FIFO_L_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D21", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS1_3": { + "src_wire": "CMT_IN_FIFO_Q33", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS4_11": { + "src_wire": "CMT_IN_FIFO_Q91", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS22_2": { + "src_wire": "CMT_OUT_FIFO_Q20", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_11->CMT_OUT_FIFO_D95": { + "src_wire": "CMT_FIFO_L_IMUX5_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D95", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q27->CMT_FIFO_L_LOGIC_OUTS13_2": { + "src_wire": "CMT_IN_FIFO_Q27", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS20_10": { + "src_wire": "CMT_OUT_FIFO_Q83", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q06->CMT_FIFO_L_LOGIC_OUTS9_0": { + "src_wire": "CMT_IN_FIFO_Q06", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q87->CMT_FIFO_L_LOGIC_OUTS13_10": { + "src_wire": "CMT_IN_FIFO_Q87", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_4->CMT_OUT_FIFO_D40": { + "src_wire": "CMT_FIFO_L_IMUX28_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D40", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS20_2": { + "src_wire": "CMT_OUT_FIFO_Q23", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_4->CMT_OUT_FIFO_D45": { + "src_wire": "CMT_FIFO_L_IMUX5_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D45", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS19_4": { + "src_wire": "CMT_OUT_FIFO_Q41", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_3->CMT_OUT_FIFO_D36": { + "src_wire": "CMT_FIFO_L_IMUX7_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D36", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_8->CMT_IN_FIFO_D62": { + "src_wire": "CMT_FIFO_L_IMUX36_8", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D62", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_4->CMT_OUT_FIFO_D46": { + "src_wire": "CMT_FIFO_L_IMUX7_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D46", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_5->CMT_OUT_FIFO_D50": { + "src_wire": "CMT_FIFO_L_IMUX28_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D50", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_3->CMT_IN_FIFO_D30": { + "src_wire": "CMT_FIFO_L_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D30", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS19_5": { + "src_wire": "CMT_OUT_FIFO_Q51", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS20_8": { + "src_wire": "CMT_OUT_FIFO_Q63", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS11_5": { + "src_wire": "CMT_OUT_FIFO_Q52", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_6->CMT_IN_FIFO_D57": { + "src_wire": "CMT_FIFO_L_IMUX42_6", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D57", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_5->CMT_OUT_FIFO_D55": { + "src_wire": "CMT_FIFO_L_IMUX5_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D55", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS11_8": { + "src_wire": "CMT_OUT_FIFO_Q62", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_10->CMT_IN_FIFO_D83": { + "src_wire": "CMT_FIFO_L_IMUX42_10", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D83", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q05->CMT_FIFO_L_LOGIC_OUTS8_0": { + "src_wire": "CMT_IN_FIFO_Q05", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q14->CMT_FIFO_L_LOGIC_OUTS12_1": { + "src_wire": "CMT_IN_FIFO_Q14", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS19_2": { + "src_wire": "CMT_OUT_FIFO_Q21", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_10->CMT_OUT_FIFO_D83": { + "src_wire": "CMT_FIFO_L_IMUX38_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D83", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_8->CMT_IN_FIFO_D60": { + "src_wire": "CMT_FIFO_L_IMUX26_8", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D60", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS1_9": { + "src_wire": "CMT_IN_FIFO_Q73", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_0->CMT_IN_FIFO_D00": { + "src_wire": "CMT_FIFO_L_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D00", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS19_8": { + "src_wire": "CMT_OUT_FIFO_Q61", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS22_9": { + "src_wire": "CMT_OUT_FIFO_Q70", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS8_8": { + "src_wire": "CMT_IN_FIFO_Q65", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q24->CMT_FIFO_L_LOGIC_OUTS12_2": { + "src_wire": "CMT_IN_FIFO_Q24", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_PHASER_RDENABLE->CMT_OUT_FIFO_RDEN": { + "src_wire": "CMT_FIFO_L_PHASER_RDENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_10->CMT_IN_FIFO_D82": { + "src_wire": "CMT_FIFO_L_IMUX36_10", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D82", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_8->CMT_OUT_FIFO_D60": { + "src_wire": "CMT_FIFO_L_IMUX28_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D60", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_PHASER_RDCLK->CMT_OUT_FIFO_RDCLK": { + "src_wire": "CMT_FIFO_L_PHASER_RDCLK", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_5->CMT_IN_FIFO_D52": { + "src_wire": "CMT_FIFO_L_IMUX36_5", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D52", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_11->CMT_IN_FIFO_D92": { + "src_wire": "CMT_FIFO_L_IMUX36_11", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D92", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS19_0": { + "src_wire": "CMT_OUT_FIFO_Q01", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_10->CMT_OUT_FIFO_D80": { + "src_wire": "CMT_FIFO_L_IMUX28_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D80", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_9->CMT_OUT_FIFO_D77": { + "src_wire": "CMT_FIFO_L_IMUX6_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D77", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS4_10": { + "src_wire": "CMT_IN_FIFO_Q81", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_4->CMT_OUT_FIFO_D44": { + "src_wire": "CMT_FIFO_L_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D44", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q94->CMT_FIFO_L_LOGIC_OUTS12_11": { + "src_wire": "CMT_IN_FIFO_Q94", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_3->CMT_IN_FIFO_D31": { + "src_wire": "CMT_FIFO_L_IMUX40_3", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D31", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q36->CMT_FIFO_L_LOGIC_OUTS9_3": { + "src_wire": "CMT_IN_FIFO_Q36", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_9->CMT_IN_FIFO_D73": { + "src_wire": "CMT_FIFO_L_IMUX42_9", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D73", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS19_1": { + "src_wire": "CMT_OUT_FIFO_Q11", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q95->CMT_FIFO_L_LOGIC_OUTS8_11": { + "src_wire": "CMT_IN_FIFO_Q95", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_6->CMT_IN_FIFO_D54": { + "src_wire": "CMT_FIFO_L_IMUX26_6", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D54", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_6->CMT_IN_FIFO_D56": { + "src_wire": "CMT_FIFO_L_IMUX36_6", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D56", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_4->CMT_OUT_FIFO_D43": { + "src_wire": "CMT_FIFO_L_IMUX38_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D43", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q26->CMT_FIFO_L_LOGIC_OUTS9_2": { + "src_wire": "CMT_IN_FIFO_Q26", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS0_9": { + "src_wire": "CMT_IN_FIFO_Q70", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_6": { + "src_wire": "CMT_OUT_FIFO_ALMOSTEMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_8->CMT_OUT_FIFO_D63": { + "src_wire": "CMT_FIFO_L_IMUX38_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D63", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_10->CMT_OUT_FIFO_D84": { + "src_wire": "CMT_FIFO_L_IMUX12_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D84", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q46->CMT_FIFO_L_LOGIC_OUTS9_4": { + "src_wire": "CMT_IN_FIFO_Q46", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_1->CMT_OUT_FIFO_D11": { + "src_wire": "CMT_FIFO_L_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_5->CMT_IN_FIFO_D50": { + "src_wire": "CMT_FIFO_L_IMUX26_5", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D50", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS11_1": { + "src_wire": "CMT_OUT_FIFO_Q12", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_CLK0_7->CMT_OUT_FIFO_RDCLK": { + "src_wire": "CMT_FIFO_L_CLK0_7", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS0_1": { + "src_wire": "CMT_IN_FIFO_Q10", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_9->CMT_IN_FIFO_D71": { + "src_wire": "CMT_FIFO_L_IMUX40_9", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D71", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS0_4": { + "src_wire": "CMT_IN_FIFO_Q40", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_11->CMT_OUT_FIFO_D90": { + "src_wire": "CMT_FIFO_L_IMUX28_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D90", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_5->CMT_OUT_FIFO_D53": { + "src_wire": "CMT_FIFO_L_IMUX38_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D53", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_8->CMT_OUT_FIFO_D62": { + "src_wire": "CMT_FIFO_L_IMUX39_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D62", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS22_1": { + "src_wire": "CMT_OUT_FIFO_Q10", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_7->CMT_IN_FIFO_D65": { + "src_wire": "CMT_FIFO_L_IMUX40_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D65", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_11->CMT_OUT_FIFO_D92": { + "src_wire": "CMT_FIFO_L_IMUX39_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D92", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS19_9": { + "src_wire": "CMT_OUT_FIFO_Q71", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_6->CMT_IN_FIFO_WREN": { + "src_wire": "CMT_FIFO_L_IMUX7_6", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WREN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_7": { + "src_wire": "CMT_IN_FIFO_FULL", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS5_8": { + "src_wire": "CMT_IN_FIFO_Q62", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS4_1": { + "src_wire": "CMT_IN_FIFO_Q11", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS1_2": { + "src_wire": "CMT_IN_FIFO_Q23", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_11->CMT_IN_FIFO_D93": { + "src_wire": "CMT_FIFO_L_IMUX42_11", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D93", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS11_9": { + "src_wire": "CMT_OUT_FIFO_Q72", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_2->CMT_IN_FIFO_D20": { + "src_wire": "CMT_FIFO_L_IMUX26_2", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D20", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_7->CMT_IN_FIFO_RESET": { + "src_wire": "CMT_FIFO_L_IMUX5_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_RESET", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS4_4": { + "src_wire": "CMT_IN_FIFO_Q41", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS0_0": { + "src_wire": "CMT_IN_FIFO_Q00", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q04->CMT_FIFO_L_LOGIC_OUTS12_0": { + "src_wire": "CMT_IN_FIFO_Q04", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_2->CMT_IN_FIFO_D22": { + "src_wire": "CMT_FIFO_L_IMUX36_2", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D22", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS11_3": { + "src_wire": "CMT_OUT_FIFO_Q32", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS0_10": { + "src_wire": "CMT_IN_FIFO_Q80", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_1->CMT_OUT_FIFO_D14": { + "src_wire": "CMT_FIFO_L_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_CLK0_6->CMT_OUT_FIFO_WRCLK": { + "src_wire": "CMT_FIFO_L_CLK0_6", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_WRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS22_3": { + "src_wire": "CMT_OUT_FIFO_Q30", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS5_4": { + "src_wire": "CMT_IN_FIFO_Q42", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS20_6": { + "src_wire": "CMT_OUT_FIFO_Q57", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_PHASER_WRENABLE->CMT_IN_FIFO_WREN": { + "src_wire": "CMT_FIFO_L_PHASER_WRENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WREN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_5->CMT_IN_FIFO_D51": { + "src_wire": "CMT_FIFO_L_IMUX40_5", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D51", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS9_8": { + "src_wire": "CMT_IN_FIFO_Q66", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_4->CMT_IN_FIFO_D43": { + "src_wire": "CMT_FIFO_L_IMUX42_4", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D43", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_7": { + "src_wire": "CMT_IN_FIFO_EMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_5->CMT_OUT_FIFO_D54": { + "src_wire": "CMT_FIFO_L_IMUX12_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D54", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS0_5": { + "src_wire": "CMT_IN_FIFO_Q50", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_5->CMT_OUT_FIFO_D57": { + "src_wire": "CMT_FIFO_L_IMUX6_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D57", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS5_5": { + "src_wire": "CMT_IN_FIFO_Q52", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_9->CMT_OUT_FIFO_D71": { + "src_wire": "CMT_FIFO_L_IMUX21_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D71", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS4_3": { + "src_wire": "CMT_IN_FIFO_Q31", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_0->CMT_OUT_FIFO_D03": { + "src_wire": "CMT_FIFO_L_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D03", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_9->CMT_OUT_FIFO_D73": { + "src_wire": "CMT_FIFO_L_IMUX38_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D73", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS1_0": { + "src_wire": "CMT_IN_FIFO_Q03", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS11_2": { + "src_wire": "CMT_OUT_FIFO_Q22", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_8->CMT_OUT_FIFO_D64": { + "src_wire": "CMT_FIFO_L_IMUX12_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D64", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_0->CMT_IN_FIFO_D03": { + "src_wire": "CMT_FIFO_L_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D03", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q45->CMT_FIFO_L_LOGIC_OUTS8_4": { + "src_wire": "CMT_IN_FIFO_Q45", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_6->CMT_OUT_FIFO_WREN": { + "src_wire": "CMT_FIFO_L_IMUX6_6", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_WREN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_10->CMT_OUT_FIFO_D81": { + "src_wire": "CMT_FIFO_L_IMUX21_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D81", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_4->CMT_OUT_FIFO_D42": { + "src_wire": "CMT_FIFO_L_IMUX39_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D42", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS1_8": { + "src_wire": "CMT_IN_FIFO_Q63", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_9->CMT_OUT_FIFO_D72": { + "src_wire": "CMT_FIFO_L_IMUX39_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D72", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS4_5": { + "src_wire": "CMT_IN_FIFO_Q51", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q96->CMT_FIFO_L_LOGIC_OUTS9_11": { + "src_wire": "CMT_IN_FIFO_Q96", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q74->CMT_FIFO_L_LOGIC_OUTS12_9": { + "src_wire": "CMT_IN_FIFO_Q74", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_10->CMT_OUT_FIFO_D87": { + "src_wire": "CMT_FIFO_L_IMUX6_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D87", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_8->CMT_IN_FIFO_D63": { + "src_wire": "CMT_FIFO_L_IMUX42_8", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D63", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_0->CMT_OUT_FIFO_D07": { + "src_wire": "CMT_FIFO_L_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D07", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q34->CMT_FIFO_L_LOGIC_OUTS12_3": { + "src_wire": "CMT_IN_FIFO_Q34", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS5_1": { + "src_wire": "CMT_IN_FIFO_Q12", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q07->CMT_FIFO_L_LOGIC_OUTS13_0": { + "src_wire": "CMT_IN_FIFO_Q07", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS13_8": { + "src_wire": "CMT_IN_FIFO_Q67", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_0->CMT_OUT_FIFO_D01": { + "src_wire": "CMT_FIFO_L_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D01", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS22_5": { + "src_wire": "CMT_OUT_FIFO_Q50", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_6": { + "src_wire": "CMT_OUT_FIFO_FULL", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS22_8": { + "src_wire": "CMT_OUT_FIFO_Q60", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_7->CMT_IN_FIFO_D64": { + "src_wire": "CMT_FIFO_L_IMUX26_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D64", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_7": { + "src_wire": "CMT_IN_FIFO_ALMOSTFULL", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q86->CMT_FIFO_L_LOGIC_OUTS9_10": { + "src_wire": "CMT_IN_FIFO_Q86", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS4_2": { + "src_wire": "CMT_IN_FIFO_Q21", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_9->CMT_IN_FIFO_D70": { + "src_wire": "CMT_FIFO_L_IMUX26_9", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D70", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS11_0": { + "src_wire": "CMT_OUT_FIFO_Q02", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_8->CMT_IN_FIFO_D61": { + "src_wire": "CMT_FIFO_L_IMUX40_8", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D61", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q75->CMT_FIFO_L_LOGIC_OUTS8_9": { + "src_wire": "CMT_IN_FIFO_Q75", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q85->CMT_FIFO_L_LOGIC_OUTS8_10": { + "src_wire": "CMT_IN_FIFO_Q85", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_CLK1_7->CMT_IN_FIFO_RDCLK": { + "src_wire": "CMT_FIFO_L_CLK1_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_RDCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS22_0": { + "src_wire": "CMT_OUT_FIFO_Q00", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS1_5": { + "src_wire": "CMT_IN_FIFO_Q53", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS0_8": { + "src_wire": "CMT_IN_FIFO_Q60", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS1_1": { + "src_wire": "CMT_IN_FIFO_Q13", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS8_5": { + "src_wire": "CMT_IN_FIFO_Q55", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_2->CMT_IN_FIFO_D21": { + "src_wire": "CMT_FIFO_L_IMUX40_2", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D21", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_9->CMT_OUT_FIFO_D75": { + "src_wire": "CMT_FIFO_L_IMUX5_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D75", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_7->CMT_IN_FIFO_D67": { + "src_wire": "CMT_FIFO_L_IMUX42_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D67", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q47->CMT_FIFO_L_LOGIC_OUTS13_4": { + "src_wire": "CMT_IN_FIFO_Q47", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q84->CMT_FIFO_L_LOGIC_OUTS12_10": { + "src_wire": "CMT_IN_FIFO_Q84", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS5_9": { + "src_wire": "CMT_IN_FIFO_Q72", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS19_7": { + "src_wire": "CMT_OUT_FIFO_Q65", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS9_5": { + "src_wire": "CMT_IN_FIFO_Q56", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_1->CMT_OUT_FIFO_D13": { + "src_wire": "CMT_FIFO_L_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_6->CMT_IN_FIFO_D55": { + "src_wire": "CMT_FIFO_L_IMUX40_6", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D55", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_11->CMT_OUT_FIFO_D96": { + "src_wire": "CMT_FIFO_L_IMUX7_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D96", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_2->CMT_OUT_FIFO_D20": { + "src_wire": "CMT_FIFO_L_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D20", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_8->CMT_OUT_FIFO_D65": { + "src_wire": "CMT_FIFO_L_IMUX5_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D65", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_9->CMT_OUT_FIFO_D74": { + "src_wire": "CMT_FIFO_L_IMUX12_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D74", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q35->CMT_FIFO_L_LOGIC_OUTS8_3": { + "src_wire": "CMT_IN_FIFO_Q35", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_5->CMT_OUT_FIFO_D51": { + "src_wire": "CMT_FIFO_L_IMUX21_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D51", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_6->CMT_OUT_FIFO_RESET": { + "src_wire": "CMT_FIFO_L_IMUX5_6", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RESET", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_5->CMT_OUT_FIFO_D56": { + "src_wire": "CMT_FIFO_L_IMUX7_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D56", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q25->CMT_FIFO_L_LOGIC_OUTS8_2": { + "src_wire": "CMT_IN_FIFO_Q25", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_4->CMT_OUT_FIFO_D47": { + "src_wire": "CMT_FIFO_L_IMUX6_4", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D47", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_5->CMT_IN_FIFO_D53": { + "src_wire": "CMT_FIFO_L_IMUX42_5", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D53", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS20_11": { + "src_wire": "CMT_OUT_FIFO_Q93", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS20_4": { + "src_wire": "CMT_OUT_FIFO_Q43", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_9->CMT_IN_FIFO_D72": { + "src_wire": "CMT_FIFO_L_IMUX36_9", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D72", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_1->CMT_IN_FIFO_D10": { + "src_wire": "CMT_FIFO_L_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS0_11": { + "src_wire": "CMT_IN_FIFO_Q90", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS22_4": { + "src_wire": "CMT_OUT_FIFO_Q40", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS5_3": { + "src_wire": "CMT_IN_FIFO_Q32", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS0_2": { + "src_wire": "CMT_IN_FIFO_Q20", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_2->CMT_OUT_FIFO_D24": { + "src_wire": "CMT_FIFO_L_IMUX12_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D24", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_7": { + "src_wire": "CMT_IN_FIFO_ALMOSTEMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_11->CMT_OUT_FIFO_D94": { + "src_wire": "CMT_FIFO_L_IMUX12_11", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D94", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS19_3": { + "src_wire": "CMT_OUT_FIFO_Q31", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS20_1": { + "src_wire": "CMT_OUT_FIFO_Q13", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_6": { + "src_wire": "CMT_OUT_FIFO_EMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_8->CMT_OUT_FIFO_D67": { + "src_wire": "CMT_FIFO_L_IMUX6_8", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D67", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_10->CMT_OUT_FIFO_D86": { + "src_wire": "CMT_FIFO_L_IMUX7_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D86", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS1_4": { + "src_wire": "CMT_IN_FIFO_Q43", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_2->CMT_OUT_FIFO_D22": { + "src_wire": "CMT_FIFO_L_IMUX39_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D22", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS20_3": { + "src_wire": "CMT_OUT_FIFO_Q33", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_1->CMT_IN_FIFO_D11": { + "src_wire": "CMT_FIFO_L_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q97->CMT_FIFO_L_LOGIC_OUTS13_11": { + "src_wire": "CMT_IN_FIFO_Q97", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS22_10": { + "src_wire": "CMT_OUT_FIFO_Q80", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS22_11": { + "src_wire": "CMT_OUT_FIFO_Q90", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_3->CMT_OUT_FIFO_D35": { + "src_wire": "CMT_FIFO_L_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D35", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS1_10": { + "src_wire": "CMT_IN_FIFO_Q83", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS12_8": { + "src_wire": "CMT_IN_FIFO_Q64", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_CLK1_6->CMT_IN_FIFO_WRCLK": { + "src_wire": "CMT_FIFO_L_CLK1_6", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_4->CMT_IN_FIFO_D40": { + "src_wire": "CMT_FIFO_L_IMUX26_4", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D40", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_3->CMT_OUT_FIFO_D30": { + "src_wire": "CMT_FIFO_L_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D30", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_9->CMT_OUT_FIFO_D76": { + "src_wire": "CMT_FIFO_L_IMUX7_9", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D76", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_PHASER_WRCLK->CMT_IN_FIFO_WRCLK": { + "src_wire": "CMT_FIFO_L_PHASER_WRCLK", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_0->CMT_OUT_FIFO_D06": { + "src_wire": "CMT_FIFO_L_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D06", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS11_11": { + "src_wire": "CMT_OUT_FIFO_Q92", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q77->CMT_FIFO_L_LOGIC_OUTS13_9": { + "src_wire": "CMT_IN_FIFO_Q77", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS4_0": { + "src_wire": "CMT_IN_FIFO_Q01", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_5->CMT_OUT_FIFO_D52": { + "src_wire": "CMT_FIFO_L_IMUX39_5", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D52", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_1->CMT_OUT_FIFO_D17": { + "src_wire": "CMT_FIFO_L_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D17", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS4_8": { + "src_wire": "CMT_IN_FIFO_Q61", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS0_3": { + "src_wire": "CMT_IN_FIFO_Q30", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_2->CMT_OUT_FIFO_D27": { + "src_wire": "CMT_FIFO_L_IMUX6_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D27", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS22_7": { + "src_wire": "CMT_OUT_FIFO_Q64", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_3->CMT_OUT_FIFO_D32": { + "src_wire": "CMT_FIFO_L_IMUX39_3", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D32", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_2->CMT_IN_FIFO_D23": { + "src_wire": "CMT_FIFO_L_IMUX42_2", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D23", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS19_6": { + "src_wire": "CMT_OUT_FIFO_Q55", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q16->CMT_FIFO_L_LOGIC_OUTS9_1": { + "src_wire": "CMT_IN_FIFO_Q16", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_7->CMT_IN_FIFO_D66": { + "src_wire": "CMT_FIFO_L_IMUX36_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D66", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_10->CMT_OUT_FIFO_D85": { + "src_wire": "CMT_FIFO_L_IMUX5_10", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D85", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_7->CMT_IN_FIFO_RDEN": { + "src_wire": "CMT_FIFO_L_IMUX7_7", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_RDEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS5_0": { + "src_wire": "CMT_IN_FIFO_Q02", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q44->CMT_FIFO_L_LOGIC_OUTS12_4": { + "src_wire": "CMT_IN_FIFO_Q44", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_1->CMT_OUT_FIFO_D12": { + "src_wire": "CMT_FIFO_L_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_6": { + "src_wire": "CMT_OUT_FIFO_ALMOSTFULL", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_2->CMT_OUT_FIFO_D25": { + "src_wire": "CMT_FIFO_L_IMUX5_2", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D25", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_0->CMT_OUT_FIFO_D02": { + "src_wire": "CMT_FIFO_L_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D02", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS4_9": { + "src_wire": "CMT_IN_FIFO_Q71", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS22_6": { + "src_wire": "CMT_OUT_FIFO_Q54", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_1->CMT_OUT_FIFO_D16": { + "src_wire": "CMT_FIFO_L_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D16", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS5_2": { + "src_wire": "CMT_IN_FIFO_Q22", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_2", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CMT_PMV.json b/kintex7/tile_type_CMT_PMV.json new file mode 100644 index 0000000..9a74eca --- /dev/null +++ b/kintex7/tile_type_CMT_PMV.json @@ -0,0 +1,230 @@ +{ + "tile_type": "CMT_PMV", + "sites": [], + "wires": [ + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "CMT_PMV_NW4END1", + "CMT_PMV_IMUX34", + "CMT_PMV_LOGIC_OUTS3", + "CMT_PMV_IMUX40", + "CMT_PMV_NW4END0", + "CMT_PMV_CTRL0", + "CMT_PMV_NW2A0", + "CMT_PMV_LH10", + "CMT_PMV_LOGIC_OUTS0", + "CMT_PMV_IMUX1", + "CMT_PMV_SW4A3", + "CMT_PMV_EE4A0", + "CMT_PMV_FAN1", + "CMT_PMV_IMUX20", + "CMT_PMV_NE4BEG0", + "CMT_PMV_LH2", + "CMT_PMV_FAN2", + "CMT_PMV_IMUX42", + "CMT_PMV_EE2BEG1", + "CMT_PMV_FAN4", + "CMT_PMV_LH12", + "CMT_PMV_WW2END1", + "CMT_PMV_IMUX31", + "CMT_PMV_NE4C0", + "CMT_PMV_LH4", + "CMT_PMV_SW2A3", + "CMT_PMV_WW4C0", + "CMT_PMV_MONITOR_P", + "CMT_PMV_WR1END0", + "CMT_PMV_WW4A1", + "CMT_PMV_EL1BEG0", + "CMT_PMV_EE2A1", + "CMT_PMV_IMUX39", + "CMT_PMV_LOGIC_OUTS1", + "CMT_PMV_IMUX9", + "CMT_PMV_IMUX8", + "CMT_PMV_EE4C3", + "CMT_PMV_LOGIC_OUTS5", + "CMT_PMV_LOGIC_OUTS21", + "CMT_PMV_IMUX25", + "CMT_PMV_NW2A3", + "CMT_PMV_NW2A2", + "CMT_PMV_EE4BEG2", + "CMT_PMV_LOGIC_OUTS19", + "CMT_PMV_IMUX12", + "CMT_PMV_EE4B0", + "CMT_PMV_LOGIC_OUTS18", + "CMT_PMV_SE4C2", + "CMT_PMV_SW4END0", + "CMT_PMV_LH11", + "CMT_PMV_EE4A1", + "CMT_PMV_WW4B0", + "CMT_PMV_IMUX32", + "CMT_PMV_LOGIC_OUTS13", + "CMT_PMV_EE2A2", + "CMT_PMV_MONITOR_N", + "CMT_PMV_IMUX2", + "CMT_PMV_EE2A3", + "CMT_PMV_IMUX21", + "CMT_PMV_LOGIC_OUTS11", + "CMT_PMV_IMUX11", + "CMT_PMV_SE2A1", + "CMT_PMV_WR1END3", + "CMT_PMV_SW2A0", + "CMT_PMV_SW4END2", + "CMT_PMV_CTRL1", + "CMT_PMV_IMUX35", + "CMT_PMV_EE4C1", + "CMT_PMV_ER1BEG2", + "CMT_PMV_NW2A1", + "CMT_PMV_LOGIC_OUTS16", + "CMT_PMV_SW4END3", + "CMT_PMV_IMUX26", + "CMT_PMV_LOGIC_OUTS12", + "CMT_PMV_IMUX7", + "CMT_PMV_IMUX16", + "CMT_PMV_SE4C3", + "CMT_PMV_LH5", + "CMT_PMV_SW2A2", + "CMT_PMV_ER1BEG1", + "CMT_PMV_IMUX45", + "CMT_PMV_NE2A0", + "CMT_PMV_NE4C3", + "CMT_PMV_WW4C3", + "CMT_PMV_WL1END0", + "CMT_PMV_NW4A0", + "CMT_PMV_LH9", + "CMT_PMV_FAN5", + "CMT_PMV_FAN3", + "CMT_PMV_EE4A3", + "CMT_PMV_IMUX17", + "CMT_PMV_SW4A0", + "CMT_PMV_SE2A2", + "CMT_PMV_WW2A0", + "CMT_PMV_WW2END2", + "CMT_PMV_EE4BEG1", + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", + "CMT_PMV_IMUX37", + "CMT_PMV_WR1END2", + "CMT_PMV_NE4BEG3", + "CMT_PMV_IMUX4", + "CMT_PMV_IMUX14", + "CMT_PMV_SE4BEG1", + "CMT_PMV_WW2END0", + "CMT_PMV_LH1", + "CMT_PMV_IMUX29", + "CMT_PMV_BYP5", + "CMT_PMV_LOGIC_OUTS23", + "CMT_PMV_NE2A2", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "CMT_PMV_IMUX23", + "CMT_PMV_LH8", + "CMT_PMV_EL1BEG3", + "CMT_PMV_BYP0", + "CMT_PMV_IMUX36", + "CMT_PMV_WW4END2", + "CMT_PMV_NW4A3", + "CMT_PMV_EL1BEG2", + "CMT_PMV_ER1BEG0", + "CMT_PMV_ER1BEG3", + "CMT_PMV_IMUX19", + "CMT_PMV_EE4BEG0", + "CMT_PMV_EE4C0", + "CMT_PMV_IMUX0", + "CMT_PMV_WW2A2", + "CMT_PMV_WW4END3", + "CMT_PMV_EL1BEG1", + "CMT_PMV_EE4B1", + "CMT_PMV_IMUX10", + "CMT_PMV_LOGIC_OUTS8", + "CMT_PMV_SE4BEG0", + "CMT_PMV_FAN6", + "CMT_PMV_WW2END3", + "CMT_PMV_BYP6", + "CMT_PMV_IMUX38", + "CMT_PMV_IMUX22", + "CMT_PMV_NE2A3", + "CMT_PMV_IMUX33", + "CMT_PMV_WW4END1", + "CMT_PMV_EE4A2", + "CMT_PMV_IMUX41", + "CMT_PMV_LOGIC_OUTS7", + "CMT_PMV_SE4C1", + "CMT_PMV_SE4BEG2", + "CMT_PMV_WR1END1", + "CMT_PMV_BYP3", + "CMT_PMV_WW4A3", + "CMT_PMV_LOGIC_OUTS14", + "CMT_PMV_LH3", + "CMT_PMV_SE2A3", + "CMT_PMV_IMUX47", + "CMT_PMV_SE4BEG3", + "CMT_PMV_EE2A0", + "CMT_PMV_LOGIC_OUTS4", + "CMT_PMV_SE2A0", + "CMT_PMV_LOGIC_OUTS17", + "CMT_PMV_IMUX43", + "CMT_PMV_LOGIC_OUTS22", + "CMT_PMV_BYP1", + "CMT_PMV_LOGIC_OUTS15", + "CMT_PMV_WL1END3", + "CMT_PMV_NE4C2", + "CMT_PMV_WW4B2", + "CMT_PMV_IMUX46", + "CMT_PMV_NE2A1", + "CMT_PMV_BYP7", + "CMT_PMV_IMUX24", + "CMT_PMV_FAN7", + "CMT_PMV_IMUX15", + "CMT_PMV_LOGIC_OUTS6", + "CMT_PMV_IMUX3", + "CMT_PMV_NE4BEG2", + "CMT_PMV_LH6", + "CMT_PMV_NW4END3", + "CMT_PMV_WW2A1", + "CMT_PMV_NW4A2", + "CMT_PMV_EE2BEG2", + "CMT_PMV_WW2A3", + "CMT_PMV_WW4C2", + "CMT_PMV_IMUX44", + "CMT_PMV_NE4BEG1", + "CMT_PMV_BYP4", + "CMT_PMV_EE2BEG0", + "CMT_PMV_WW4A2", + "CMT_PMV_EE2BEG3", + "CMT_PMV_SW2A1", + "CMT_PMV_IMUX18", + "CMT_PMV_SE4C0", + "CMT_PMV_LH7", + "CMT_PMV_SW4END1", + "CMT_PMV_IMUX6", + "CMT_PMV_LOGIC_OUTS2", + "CMT_PMV_SW4A2", + "CMT_PMV_IMUX27", + "CMT_PMV_WL1END1", + "CMT_PMV_LOGIC_OUTS9", + "L_TERM_INT_PHASER_TO_IO_OCLK", + "CMT_PMV_IMUX30", + "CMT_PMV_WW4C1", + "CMT_PMV_EE4B3", + "CMT_PMV_LOGIC_OUTS10", + "CMT_PMV_SW4A1", + "CMT_PMV_WW4A0", + "CMT_PMV_BYP2", + "CMT_PMV_WW4END0", + "CMT_PMV_CLK0", + "CMT_PMV_LOGIC_OUTS20", + "CMT_PMV_IMUX13", + "CMT_PMV_NW4A1", + "CMT_PMV_IMUX5", + "L_TERM_INT_PHASER_TO_IO_ICLK", + "CMT_PMV_IMUX28", + "CMT_PMV_FAN0", + "CMT_PMV_EE4B2", + "CMT_PMV_EE4BEG3", + "CMT_PMV_CLK1", + "CMT_PMV_NE4C1", + "CMT_PMV_NW4END2", + "CMT_PMV_EE4C2", + "CMT_PMV_WW4B3", + "CMT_PMV_WW4B1", + "CMT_PMV_WL1END2" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_CMT_PMV_L.json b/kintex7/tile_type_CMT_PMV_L.json new file mode 100644 index 0000000..458f81e --- /dev/null +++ b/kintex7/tile_type_CMT_PMV_L.json @@ -0,0 +1,230 @@ +{ + "tile_type": "CMT_PMV_L", + "sites": [], + "wires": [ + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "CMT_PMV_NW4END1", + "CMT_PMV_IMUX34", + "CMT_PMV_LOGIC_OUTS3", + "CMT_PMV_IMUX40", + "CMT_PMV_NW4END0", + "CMT_PMV_CTRL0", + "CMT_PMV_NW2A0", + "CMT_PMV_LH10", + "CMT_PMV_LOGIC_OUTS0", + "CMT_PMV_IMUX1", + "CMT_PMV_SW4A3", + "CMT_PMV_EE4A0", + "CMT_PMV_FAN1", + "CMT_PMV_IMUX20", + "CMT_PMV_NE4BEG0", + "CMT_PMV_LH2", + "CMT_PMV_FAN2", + "CMT_PMV_IMUX42", + "CMT_PMV_EE2BEG1", + "CMT_PMV_FAN4", + "CMT_PMV_LH12", + "CMT_PMV_WW2END1", + "CMT_PMV_IMUX31", + "CMT_PMV_NE4C0", + "CMT_PMV_LH4", + "CMT_PMV_SW2A3", + "CMT_PMV_WW4C0", + "CMT_PMV_MONITOR_P", + "CMT_PMV_WR1END0", + "CMT_PMV_WW4A1", + "CMT_PMV_EL1BEG0", + "CMT_PMV_EE2A1", + "CMT_PMV_IMUX39", + "CMT_PMV_LOGIC_OUTS1", + "CMT_PMV_IMUX9", + "CMT_PMV_IMUX8", + "CMT_PMV_EE4C3", + "CMT_PMV_LOGIC_OUTS5", + "CMT_PMV_LOGIC_OUTS21", + "CMT_PMV_IMUX25", + "CMT_PMV_NW2A3", + "CMT_PMV_NW2A2", + "CMT_PMV_EE4BEG2", + "CMT_PMV_LOGIC_OUTS19", + "CMT_PMV_IMUX12", + "CMT_PMV_EE4B0", + "CMT_PMV_LOGIC_OUTS18", + "CMT_PMV_SE4C2", + "CMT_PMV_SW4END0", + "CMT_PMV_LH11", + "CMT_PMV_EE4A1", + "CMT_PMV_WW4B0", + "CMT_PMV_IMUX32", + "CMT_PMV_LOGIC_OUTS13", + "CMT_PMV_EE2A2", + "CMT_PMV_MONITOR_N", + "CMT_PMV_IMUX2", + "CMT_PMV_EE2A3", + "CMT_PMV_IMUX21", + "CMT_PMV_LOGIC_OUTS11", + "CMT_PMV_IMUX11", + "CMT_PMV_SE2A1", + "CMT_PMV_WR1END3", + "CMT_PMV_SW2A0", + "CMT_PMV_SW4END2", + "CMT_PMV_CTRL1", + "CMT_PMV_IMUX35", + "CMT_PMV_EE4C1", + "CMT_PMV_ER1BEG2", + "CMT_PMV_NW2A1", + "CMT_PMV_LOGIC_OUTS16", + "CMT_PMV_SW4END3", + "CMT_PMV_IMUX26", + "CMT_PMV_LOGIC_OUTS12", + "CMT_PMV_IMUX7", + "CMT_PMV_IMUX16", + "CMT_PMV_SE4C3", + "CMT_PMV_LH5", + "CMT_PMV_SW2A2", + "CMT_PMV_ER1BEG1", + "CMT_PMV_IMUX45", + "CMT_PMV_NE2A0", + "CMT_PMV_NE4C3", + "CMT_PMV_WW4C3", + "CMT_PMV_WL1END0", + "CMT_PMV_NW4A0", + "CMT_PMV_LH9", + "CMT_PMV_FAN5", + "CMT_PMV_FAN3", + "CMT_PMV_EE4A3", + "CMT_PMV_IMUX17", + "CMT_PMV_SW4A0", + "CMT_PMV_SE2A2", + "CMT_PMV_WW2A0", + "CMT_PMV_WW2END2", + "CMT_PMV_EE4BEG1", + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", + "CMT_PMV_IMUX37", + "CMT_PMV_WR1END2", + "CMT_PMV_NE4BEG3", + "CMT_PMV_IMUX4", + "CMT_PMV_IMUX14", + "CMT_PMV_SE4BEG1", + "CMT_PMV_WW2END0", + "CMT_PMV_LH1", + "CMT_PMV_IMUX29", + "CMT_PMV_BYP5", + "CMT_PMV_LOGIC_OUTS23", + "CMT_PMV_NE2A2", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "CMT_PMV_IMUX23", + "CMT_PMV_LH8", + "CMT_PMV_EL1BEG3", + "CMT_PMV_BYP0", + "CMT_PMV_IMUX36", + "CMT_PMV_WW4END2", + "CMT_PMV_NW4A3", + "CMT_PMV_EL1BEG2", + "CMT_PMV_ER1BEG0", + "CMT_PMV_ER1BEG3", + "CMT_PMV_IMUX19", + "CMT_PMV_EE4BEG0", + "CMT_PMV_EE4C0", + "CMT_PMV_IMUX0", + "CMT_PMV_WW2A2", + "CMT_PMV_WW4END3", + "CMT_PMV_EL1BEG1", + "CMT_PMV_EE4B1", + "CMT_PMV_IMUX10", + "CMT_PMV_LOGIC_OUTS8", + "CMT_PMV_SE4BEG0", + "CMT_PMV_FAN6", + "CMT_PMV_WW2END3", + "CMT_PMV_BYP6", + "CMT_PMV_IMUX38", + "CMT_PMV_IMUX22", + "CMT_PMV_NE2A3", + "CMT_PMV_IMUX33", + "CMT_PMV_WW4END1", + "CMT_PMV_EE4A2", + "CMT_PMV_IMUX41", + "CMT_PMV_LOGIC_OUTS7", + "CMT_PMV_SE4C1", + "CMT_PMV_SE4BEG2", + "CMT_PMV_WR1END1", + "CMT_PMV_BYP3", + "CMT_PMV_WW4A3", + "CMT_PMV_LOGIC_OUTS14", + "CMT_PMV_LH3", + "CMT_PMV_SE2A3", + "CMT_PMV_IMUX47", + "CMT_PMV_SE4BEG3", + "CMT_PMV_EE2A0", + "CMT_PMV_LOGIC_OUTS4", + "CMT_PMV_SE2A0", + "CMT_PMV_LOGIC_OUTS17", + "CMT_PMV_IMUX43", + "CMT_PMV_LOGIC_OUTS22", + "CMT_PMV_BYP1", + "CMT_PMV_LOGIC_OUTS15", + "CMT_PMV_WL1END3", + "CMT_PMV_NE4C2", + "CMT_PMV_WW4B2", + "CMT_PMV_IMUX46", + "CMT_PMV_NE2A1", + "CMT_PMV_BYP7", + "CMT_PMV_IMUX24", + "CMT_PMV_FAN7", + "CMT_PMV_IMUX15", + "CMT_PMV_LOGIC_OUTS6", + "CMT_PMV_IMUX3", + "CMT_PMV_NE4BEG2", + "CMT_PMV_LH6", + "CMT_PMV_NW4END3", + "CMT_PMV_WW2A1", + "CMT_PMV_NW4A2", + "CMT_PMV_EE2BEG2", + "CMT_PMV_WW2A3", + "CMT_PMV_WW4C2", + "CMT_PMV_IMUX44", + "CMT_PMV_NE4BEG1", + "CMT_PMV_BYP4", + "CMT_PMV_EE2BEG0", + "CMT_PMV_WW4A2", + "CMT_PMV_EE2BEG3", + "CMT_PMV_SW2A1", + "CMT_PMV_IMUX18", + "CMT_PMV_SE4C0", + "CMT_PMV_LH7", + "CMT_PMV_SW4END1", + "CMT_PMV_IMUX6", + "CMT_PMV_LOGIC_OUTS2", + "CMT_PMV_SW4A2", + "CMT_PMV_IMUX27", + "CMT_PMV_WL1END1", + "CMT_PMV_LOGIC_OUTS9", + "L_TERM_INT_PHASER_TO_IO_OCLK", + "CMT_PMV_IMUX30", + "CMT_PMV_WW4C1", + "CMT_PMV_EE4B3", + "CMT_PMV_LOGIC_OUTS10", + "CMT_PMV_SW4A1", + "CMT_PMV_WW4A0", + "CMT_PMV_BYP2", + "CMT_PMV_WW4END0", + "CMT_PMV_CLK0", + "CMT_PMV_LOGIC_OUTS20", + "CMT_PMV_IMUX13", + "CMT_PMV_NW4A1", + "CMT_PMV_IMUX5", + "L_TERM_INT_PHASER_TO_IO_ICLK", + "CMT_PMV_IMUX28", + "CMT_PMV_FAN0", + "CMT_PMV_EE4B2", + "CMT_PMV_EE4BEG3", + "CMT_PMV_CLK1", + "CMT_PMV_NE4C1", + "CMT_PMV_NW4END2", + "CMT_PMV_EE4C2", + "CMT_PMV_WW4B3", + "CMT_PMV_WW4B1", + "CMT_PMV_WL1END2" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_CMT_TOP_L_LOWER_B.json b/kintex7/tile_type_CMT_TOP_L_LOWER_B.json new file mode 100644 index 0000000..d4010bd --- /dev/null +++ b/kintex7/tile_type_CMT_TOP_L_LOWER_B.json @@ -0,0 +1,5450 @@ +{ + "tile_type": "CMT_TOP_L_LOWER_B", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "MMCME2_ADV", + "type": "MMCME2_ADV", + "site_pins": { + "TESTIN23": "CMT_LR_LOWER_B_MMCM_TESTIN23", + "TESTIN25": "CMT_LR_LOWER_B_MMCM_TESTIN25", + "LOCKED": "CMT_LR_LOWER_B_MMCM_LOCKED", + "DEN": "CMT_LR_LOWER_B_MMCM_DEN", + "TESTIN16": "CMT_LR_LOWER_B_MMCM_TESTIN16", + "TESTIN6": "CMT_LR_LOWER_B_MMCM_TESTIN6", + "TESTOUT0": "CMT_LR_LOWER_B_MMCM_TESTOUT0", + "TESTOUT9": "CMT_LR_LOWER_B_MMCM_TESTOUT9", + "TESTOUT28": "CMT_LR_LOWER_B_MMCM_TESTOUT28", + "TESTIN27": "CMT_LR_LOWER_B_MMCM_TESTIN27", + "TESTOUT24": "CMT_LR_LOWER_B_MMCM_TESTOUT24", + "CLKOUT0": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "TESTIN17": "CMT_LR_LOWER_B_MMCM_TESTIN17", + "TESTOUT12": "CMT_LR_LOWER_B_MMCM_TESTOUT12", + "DI15": "CMT_LR_LOWER_B_MMCM_DI15", + "TESTOUT2": "CMT_LR_LOWER_B_MMCM_TESTOUT2", + "TESTIN13": "CMT_LR_LOWER_B_MMCM_TESTIN13", + "DI12": "CMT_LR_LOWER_B_MMCM_DI12", + "DO15": "CMT_LR_LOWER_B_MMCM_DO15", + "TESTOUT59": "CMT_LR_LOWER_B_MMCM_TESTOUT59", + "PSDONE": "CMT_LR_LOWER_B_MMCM_PSDONE", + "DI2": "CMT_LR_LOWER_B_MMCM_DI2", + "TESTOUT38": "CMT_LR_LOWER_B_MMCM_TESTOUT38", + "TESTIN29": "CMT_LR_LOWER_B_MMCM_TESTIN29", + "CLKFBOUT": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "TESTOUT8": "CMT_LR_LOWER_B_MMCM_TESTOUT8", + "DI11": "CMT_LR_LOWER_B_MMCM_DI11", + "TESTIN14": "CMT_LR_LOWER_B_MMCM_TESTIN14", + "TESTOUT11": "CMT_LR_LOWER_B_MMCM_TESTOUT11", + "TESTOUT25": "CMT_LR_LOWER_B_MMCM_TESTOUT25", + "TESTOUT56": "CMT_LR_LOWER_B_MMCM_TESTOUT56", + "CLKIN2": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "PSEN": "CMT_LR_LOWER_B_MMCM_PSEN", + "CLKOUT3B": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", + "DO10": "CMT_LR_LOWER_B_MMCM_DO10", + "TESTOUT6": "CMT_LR_LOWER_B_MMCM_TESTOUT6", + "DO11": "CMT_LR_LOWER_B_MMCM_DO11", + "DO0": "CMT_LR_LOWER_B_MMCM_DO0", + "TESTOUT27": "CMT_LR_LOWER_B_MMCM_TESTOUT27", + "DI6": "CMT_LR_LOWER_B_MMCM_DI6", + "CLKOUT5": "CMT_LR_LOWER_B_MMCM_CLKOUT5", + "DI8": "CMT_LR_LOWER_B_MMCM_DI8", + "DADDR0": "CMT_LR_LOWER_B_MMCM_DADDR0", + "TESTOUT5": "CMT_LR_LOWER_B_MMCM_TESTOUT5", + "TMUXOUT": "CMT_LR_LOWER_B_MMCM_TMUXOUT", + "DI3": "CMT_LR_LOWER_B_MMCM_DI3", + "TESTOUT30": "CMT_LR_LOWER_B_MMCM_TESTOUT30", + "TESTOUT4": "CMT_LR_LOWER_B_MMCM_TESTOUT4", + "TESTIN31": "CMT_LR_LOWER_B_MMCM_TESTIN31", + "TESTOUT34": "CMT_LR_LOWER_B_MMCM_TESTOUT34", + "DADDR3": "CMT_LR_LOWER_B_MMCM_DADDR3", + "PWRDWN": "CMT_LR_LOWER_B_MMCM_PWRDWN", + "TESTOUT14": "CMT_LR_LOWER_B_MMCM_TESTOUT14", + "TESTIN9": "CMT_LR_LOWER_B_MMCM_TESTIN9", + "TESTOUT63": "CMT_LR_LOWER_B_MMCM_TESTOUT63", + "DO1": "CMT_LR_LOWER_B_MMCM_DO1", + "TESTOUT15": "CMT_LR_LOWER_B_MMCM_TESTOUT15", + "TESTOUT23": "CMT_LR_LOWER_B_MMCM_TESTOUT23", + "TESTOUT61": "CMT_LR_LOWER_B_MMCM_TESTOUT61", + "DI0": "CMT_LR_LOWER_B_MMCM_DI0", + "CLKOUT4": "CMT_LR_LOWER_B_MMCM_CLKOUT4", + "DI9": "CMT_LR_LOWER_B_MMCM_DI9", + "TESTOUT43": "CMT_LR_LOWER_B_MMCM_TESTOUT43", + "CLKOUT2": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "TESTOUT60": "CMT_LR_LOWER_B_MMCM_TESTOUT60", + "DO5": "CMT_LR_LOWER_B_MMCM_DO5", + "DO4": "CMT_LR_LOWER_B_MMCM_DO4", + "TESTOUT18": "CMT_LR_LOWER_B_MMCM_TESTOUT18", + "TESTOUT29": "CMT_LR_LOWER_B_MMCM_TESTOUT29", + "TESTOUT26": "CMT_LR_LOWER_B_MMCM_TESTOUT26", + "CLKOUT0B": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", + "DO8": "CMT_LR_LOWER_B_MMCM_DO8", + "DADDR6": "CMT_LR_LOWER_B_MMCM_DADDR6", + "TESTIN30": "CMT_LR_LOWER_B_MMCM_TESTIN30", + "TESTOUT32": "CMT_LR_LOWER_B_MMCM_TESTOUT32", + "TESTIN18": "CMT_LR_LOWER_B_MMCM_TESTIN18", + "TESTOUT54": "CMT_LR_LOWER_B_MMCM_TESTOUT54", + "DADDR1": "CMT_LR_LOWER_B_MMCM_DADDR1", + "TESTOUT46": "CMT_LR_LOWER_B_MMCM_TESTOUT46", + "DADDR2": "CMT_LR_LOWER_B_MMCM_DADDR2", + "CLKINSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", + "TESTIN7": "CMT_LR_LOWER_B_MMCM_TESTIN7", + "RST": "CMT_LR_LOWER_B_MMCM_RST", + "TESTIN8": "CMT_LR_LOWER_B_MMCM_TESTIN8", + "TESTOUT48": "CMT_LR_LOWER_B_MMCM_TESTOUT48", + "DRDY": "CMT_LR_LOWER_B_MMCM_DRDY", + "DWE": "CMT_LR_LOWER_B_MMCM_DWE", + "CLKOUT1": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "TESTIN3": "CMT_LR_LOWER_B_MMCM_TESTIN3", + "DI14": "CMT_LR_LOWER_B_MMCM_DI14", + "TESTOUT49": "CMT_LR_LOWER_B_MMCM_TESTOUT49", + "TESTIN26": "CMT_LR_LOWER_B_MMCM_TESTIN26", + "TESTOUT52": "CMT_LR_LOWER_B_MMCM_TESTOUT52", + "TESTOUT50": "CMT_LR_LOWER_B_MMCM_TESTOUT50", + "TESTOUT20": "CMT_LR_LOWER_B_MMCM_TESTOUT20", + "TESTIN15": "CMT_LR_LOWER_B_MMCM_TESTIN15", + "TESTIN19": "CMT_LR_LOWER_B_MMCM_TESTIN19", + "TESTIN4": "CMT_LR_LOWER_B_MMCM_TESTIN4", + "DADDR5": "CMT_LR_LOWER_B_MMCM_DADDR5", + "TESTIN11": "CMT_LR_LOWER_B_MMCM_TESTIN11", + "TESTIN1": "CMT_LR_LOWER_B_MMCM_TESTIN1", + "TESTIN20": "CMT_LR_LOWER_B_MMCM_TESTIN20", + "DI4": "CMT_LR_LOWER_B_MMCM_DI4", + "DO9": "CMT_LR_LOWER_B_MMCM_DO9", + "TESTOUT17": "CMT_LR_LOWER_B_MMCM_TESTOUT17", + "TESTOUT21": "CMT_LR_LOWER_B_MMCM_TESTOUT21", + "TESTOUT10": "CMT_LR_LOWER_B_MMCM_TESTOUT10", + "TESTIN28": "CMT_LR_LOWER_B_MMCM_TESTIN28", + "CLKOUT1B": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", + "CLKOUT2B": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", + "TESTOUT53": "CMT_LR_LOWER_B_MMCM_TESTOUT53", + "TESTOUT55": "CMT_LR_LOWER_B_MMCM_TESTOUT55", + "TESTOUT19": "CMT_LR_LOWER_B_MMCM_TESTOUT19", + "CLKIN1": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "TESTIN10": "CMT_LR_LOWER_B_MMCM_TESTIN10", + "TESTOUT22": "CMT_LR_LOWER_B_MMCM_TESTOUT22", + "DCLK": "CMT_LR_LOWER_B_MMCM_DCLK", + "DI7": "CMT_LR_LOWER_B_MMCM_DI7", + "TESTOUT57": "CMT_LR_LOWER_B_MMCM_TESTOUT57", + "PSCLK": "CMT_LR_LOWER_B_MMCM_PSCLK", + "TESTOUT44": "CMT_LR_LOWER_B_MMCM_TESTOUT44", + "CLKINSEL": "CMT_LR_LOWER_B_MMCM_CLKINSEL", + "CLKFBIN": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "DO6": "CMT_LR_LOWER_B_MMCM_DO6", + "TESTOUT45": "CMT_LR_LOWER_B_MMCM_TESTOUT45", + "TESTIN2": "CMT_LR_LOWER_B_MMCM_TESTIN2", + "TESTOUT51": "CMT_LR_LOWER_B_MMCM_TESTOUT51", + "TESTOUT40": "CMT_LR_LOWER_B_MMCM_TESTOUT40", + "TESTIN24": "CMT_LR_LOWER_B_MMCM_TESTIN24", + "TESTOUT58": "CMT_LR_LOWER_B_MMCM_TESTOUT58", + "TESTOUT16": "CMT_LR_LOWER_B_MMCM_TESTOUT16", + "DO14": "CMT_LR_LOWER_B_MMCM_DO14", + "DO12": "CMT_LR_LOWER_B_MMCM_DO12", + "DI13": "CMT_LR_LOWER_B_MMCM_DI13", + "TESTOUT41": "CMT_LR_LOWER_B_MMCM_TESTOUT41", + "DO13": "CMT_LR_LOWER_B_MMCM_DO13", + "CLKOUT6": "CMT_LR_LOWER_B_MMCM_CLKOUT6", + "CLKOUT3": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "PSINCDEC": "CMT_LR_LOWER_B_MMCM_PSINCDEC", + "DO3": "CMT_LR_LOWER_B_MMCM_DO3", + "CLKFBSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", + "DI1": "CMT_LR_LOWER_B_MMCM_DI1", + "TESTOUT42": "CMT_LR_LOWER_B_MMCM_TESTOUT42", + "TESTOUT47": "CMT_LR_LOWER_B_MMCM_TESTOUT47", + "CLKFBOUTB": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", + "TESTIN5": "CMT_LR_LOWER_B_MMCM_TESTIN5", + "TESTIN22": "CMT_LR_LOWER_B_MMCM_TESTIN22", + "TESTOUT3": "CMT_LR_LOWER_B_MMCM_TESTOUT3", + "TESTOUT36": "CMT_LR_LOWER_B_MMCM_TESTOUT36", + "TESTIN0": "CMT_LR_LOWER_B_MMCM_TESTIN0", + "TESTOUT7": "CMT_LR_LOWER_B_MMCM_TESTOUT7", + "TESTOUT33": "CMT_LR_LOWER_B_MMCM_TESTOUT33", + "DADDR4": "CMT_LR_LOWER_B_MMCM_DADDR4", + "DO2": "CMT_LR_LOWER_B_MMCM_DO2", + "TESTOUT13": "CMT_LR_LOWER_B_MMCM_TESTOUT13", + "DO7": "CMT_LR_LOWER_B_MMCM_DO7", + "DI10": "CMT_LR_LOWER_B_MMCM_DI10", + "TESTOUT1": "CMT_LR_LOWER_B_MMCM_TESTOUT1", + "TESTIN12": "CMT_LR_LOWER_B_MMCM_TESTIN12", + "TESTOUT37": "CMT_LR_LOWER_B_MMCM_TESTOUT37", + "DI5": "CMT_LR_LOWER_B_MMCM_DI5", + "TESTOUT62": "CMT_LR_LOWER_B_MMCM_TESTOUT62", + "TESTIN21": "CMT_LR_LOWER_B_MMCM_TESTIN21", + "TESTOUT31": "CMT_LR_LOWER_B_MMCM_TESTOUT31", + "TESTOUT39": "CMT_LR_LOWER_B_MMCM_TESTOUT39", + "TESTOUT35": "CMT_LR_LOWER_B_MMCM_TESTOUT35" + }, + "x_coord": 0 + } + ], + "wires": [ + "CMT_TOP_WR1END2_7", + "CMT_TOP_WW4A1_15", + "CMT_TOP_WW4C3_6", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_IMUX18_1", + "CMT_TOP_WL1END3_8", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX8_5", + "CMT_TOP_WW2END3_7", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_EE4B0_9", + "CMT_TOP_IMUX15_8", + "CMT_TOP_LH5_7", + "CMT_TOP_LOGIC_OUTS_L_B12_11", + "CMT_TOP_EE2A0_15", + "CMT_TOP_SE4C2_0", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_FAN2_3", + "CMT_TOP_IMUX40_8", + "CMT_TOP_EE4C2_7", + "CMT_TOP_SE4BEG0_10", + "CMT_TOP_NW2A1_4", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_EE2A1_6", + "CMT_TOP_EE4A2_4", + "CMT_TOP_BYP1_4", + "CMT_TOP_EE4C0_3", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_SE4BEG1_14", + "CMT_TOP_SE4C1_4", + "CMT_TOP_IMUX28_14", + "CMT_TOP_IMUX23_5", + "CMT_TOP_BYP6_12", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_IMUX34_7", + "CMT_TOP_ER1BEG2_13", + "CMT_L_LOWER_B_CLK_IN2_INT", + "CMT_TOP_SW2A3_14", + "CMT_TOP_IMUX25_10", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN5_3", + "CMT_TOP_NE4C2_2", + "CMT_TOP_EE4A2_5", + "CMT_TOP_IMUX35_5", + "CMT_TOP_EE2A0_1", + "CMT_TOP_SE4BEG3_10", + "CMT_TOP_IMUX40_12", + "CMT_TOP_FAN3_2", + "CMT_TOP_BYP2_11", + "CMT_TOP_EE2A2_1", + "CMT_TOP_SW4END2_10", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE2A2_5", + "CMT_TOP_WW2END0_3", + "CMT_TOP_SW4END3_9", + "CMT_TOP_ER1BEG3_15", + "CMT_TOP_IMUX16_11", + "CMT_TOP_IMUX28_13", + "CMT_TOP_ER1BEG1_0", + "CMT_TOP_SE2A2_10", + "CMT_TOP_WW4C2_14", + "CMT_TOP_SE4C0_2", + "CMT_TOP_EE4BEG3_14", + "CMT_TOP_EE4B3_8", + "CMT_TOP_NW4A3_9", + "CMT_TOP_EE4A1_2", + "CMT_TOP_IMUX31_4", + "CMT_TOP_NW4A3_12", + "CMT_TOP_EL1BEG3_5", + "CMT_TOP_IMUX12_15", + "CMT_TOP_SE4C3_11", + "CMT_TOP_NW4A3_4", + "CMT_TOP_WW4END1_2", + "CMT_TOP_WW4B1_5", + "CMT_TOP_LOGIC_OUTS_L_B2_9", + "CMT_TOP_IMUX12_5", + "CMT_LR_LOWER_B_MMCM_TESTIN14", + "CMT_TOP_EE2BEG1_14", + "CMT_TOP_IMUX8_10", + "CMT_TOP_NW4A1_12", + "CMT_L_LOWER_B_CLK_MMCM3", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_EE4A0_6", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_WW4B3_14", + "CMT_TOP_NE4C3_9", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_SE4BEG2_15", + "CMT_TOP_SW2A0_11", + "CMT_TOP_WR1END0_2", + "CMT_TOP_SW4A0_12", + "CMT_TOP_NW4END1_8", + "CMT_TOP_SE2A0_8", + "CMT_TOP_LH11_2", + "CMT_TOP_WR1END3_15", + "CMT_TOP_IMUX26_14", + "CMT_MMCM_PHASERA_CTSBUS0", + "CMT_TOP_EE4C3_2", + "CMT_TOP_IMUX2_7", + "CMT_TOP_LOGIC_OUTS_L_B7_11", + "CMT_TOP_EE2A1_7", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_ER1BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX16_6", + "CMT_TOP_LH6_2", + "CMT_TOP_NE4BEG1_9", + "CMT_LR_LOWER_B_MMCM_TESTOUT16", + "CMT_TOP_WW4END2_14", + "CMT_TOP_IMUX9_2", + "CMT_TOP_BYP5_1", + "CMT_TOP_OCLKDIV_12", + "CMT_TOP_WR1END1_7", + "CMT_TOP_WL1END1_1", + "CMT_TOP_EE2A3_11", + "CMT_TOP_IMUX11_15", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_EE4A0_11", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX23_8", + "CMT_TOP_IMUX11_12", + "CMT_LR_LOWER_B_MMCM_DADDR3", + "CMT_TOP_LOGIC_OUTS_L_B19_9", + "CMT_TOP_EE4C3_11", + "CMT_TOP_SW4END2_11", + "CMT_TOP_EE4C3_15", + "CMT_TOP_LOGIC_OUTS_L_B19_13", + "CMT_LR_LOWER_B_MMCM_CLKINSEL", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_WW4B1_11", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_IMUX1_14", + "CMT_TOP_WW4A2_11", + "CMT_TOP_NW4END3_0", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_SE4BEG0_6", + "CMT_TOP_IMUX7_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_SE4C2_12", + "CMT_TOP_SW2A3_2", + "CMT_TOP_WW4C1_4", + "CMT_TOP_NE2A2_5", + "CMT_TOP_SE4C3_9", + "CMT_TOP_IMUX9_12", + "CMT_TOP_IMUX3_7", + "CMT_TOP_WW4A0_8", + "CMT_TOP_NW4END0_5", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_TOP_FAN5_1", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_LH4_15", + "CMT_TOP_SE4BEG2_10", + "CMT_TOP_IMUX9_9", + "CMT_TOP_EE2A2_12", + "CMT_TOP_SE4BEG3_13", + "CMT_LR_LOWER_B_MMCM_TESTOUT51", + "CMT_TOP_IMUX31_9", + "CMT_TOP_FAN1_6", + "CMT_TOP_IMUX26_4", + "CMT_TOP_LH2_13", + "CMT_TOP_IMUX31_12", + "CMT_TOP_IMUX3_2", + "CMT_TOP_LH9_11", + "CMT_TOP_IMUX12_14", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_LH4_2", + "CMT_TOP_EE4BEG2_14", + "CMT_TOP_EE4A1_8", + "MMCM_CLK_FREQ_BB_NS0", + "CMT_TOP_WW4END1_7", + "CMT_TOP_SW4A3_15", + "CMT_TOP_IMUX35_10", + "CMT_TOP_NE4C3_15", + "CMT_TOP_IMUX44_5", + "CMT_TOP_NW2A3_15", + "CMT_TOP_IMUX37_4", + "CMT_TOP_WW4C2_8", + "CMT_TOP_NW4A0_12", + "CMT_TOP_EE4A0_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT39", + "CMT_TOP_FAN1_12", + "CMT_TOP_WW4B3_1", + "CMT_TOP_IMUX29_14", + "CMT_TOP_NW2A0_14", + "CMT_TOP_LOGIC_OUTS_L_B12_15", + "CMT_TOP_EE4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_TOP_IMUX26_13", + "CMT_TOP_SW4END1_15", + "CMT_TOP_IMUX23_12", + "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "CMT_TOP_LOGIC_OUTS_L_B15_9", + "CMT_TOP_NE4BEG2_11", + "CMT_TOP_EE2BEG1_12", + "CMT_TOP_IMUX6_12", + "CMT_TOP_WW2END1_0", + "CMT_TOP_IMUX22_9", + "CMT_TOP_FAN3_11", + "CMT_TOP_SE2A1_14", + "CMT_TOP_IMUX13_3", + "CMT_TOP_WW4END1_4", + "CMT_TOP_IMUX14_11", + "CMT_TOP_EE4BEG0_9", + "CMT_TOP_WR1END0_10", + "CMT_TOP_IMUX16_13", + "CMT_TOP_LOGIC_OUTS_L_B0_12", + "CMT_TOP_EE4C1_5", + "CMT_TOP_LH9_1", + "CMT_TOP_WL1END0_13", + "CMT_TOP_SE4BEG0_14", + "CMT_TOP_LOGIC_OUTS_L_B0_14", + "CMT_TOP_LH11_10", + "CMT_TOP_FAN6_12", + "CMT_TOP_SE2A1_3", + "CMT_TOP_BYP1_13", + "CMT_LR_LOWER_B_MMCM_TESTOUT49", + "CMT_TOP_SE2A0_1", + "CMT_TOP_SE4C0_10", + "CMT_TOP_LH12_3", + "CMT_TOP_CLK1_12", + "CMT_TOP_ER1BEG3_11", + "CMT_TOP_FAN7_4", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END2_5", + "CMT_TOP_EE4B2_12", + "CMT_TOP_LOGIC_OUTS_L_B6_15", + "CMT_TOP_WR1END2_9", + "CMT_TOP_FAN1_0", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_IMUX40_7", + "CMT_TOP_BYP7_8", + "CMT_TOP_NW4A3_0", + "CMT_TOP_WL1END2_4", + "CMT_TOP_IMUX0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_SW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_EE2A3_3", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW2A0_2", + "CMT_TOP_SW4END1_2", + "CMT_TOP_EE2A3_5", + "CMT_TOP_WR1END0_1", + "CMT_TOP_LOGIC_OUTS_L_B4_15", + "CMT_TOP_WW4C1_3", + "CMT_TOP_LH4_3", + "CMT_TOP_EE4B2_8", + "CMT_TOP_IMUX7_15", + "CMT_TOP_CLK0_13", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_WL1END3_15", + "CMT_TOP_IMUX5_2", + "CMT_TOP_EE2BEG1_6", + "CMT_TOP_EE4BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_NE2A2_2", + "CMT_LR_LOWER_B_MMCM_DO4", + "CMT_TOP_IMUX2_12", + "CMT_TOP_NW4A0_6", + "CMT_TOP_WL1END3_12", + "CMT_TOP_FAN4_14", + "CMT_TOP_EE2A1_10", + "CMT_TOP_EE4A3_5", + "CMT_TOP_LOGIC_OUTS_L_B8_10", + "CMT_TOP_IMUX14_0", + "CMT_TOP_LH7_5", + "CMT_PHASER_A_ICLK_TOIOI", + "CMT_TOP_WW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_TOP_WW2END2_3", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WW2END3_8", + "CMT_TOP_NW4END1_0", + "CMT_TOP_IMUX30_13", + "CMT_LR_LOWER_B_MMCM_DWE", + "CMT_TOP_NE4C2_5", + "CMT_TOP_SE2A2_11", + "CMT_TOP_IMUX14_4", + "CMT_TOP_IMUX12_4", + "CMT_TOP_SW4END3_2", + "CMT_TOP_IMUX32_0", + "CMT_TOP_SW4END3_12", + "CMT_TOP_SE4BEG0_1", + "CMT_TOP_OCLKDIV_15", + "CMT_TOP_NW2A2_15", + "CMT_TOP_LH8_14", + "CMT_TOP_NE4C1_13", + "CMT_TOP_IMUX44_6", + "CMT_TOP_LH9_13", + "CMT_TOP_IMUX40_9", + "CMT_TOP_SE2A3_3", + "CMT_TOP_LOGIC_OUTS_L_B1_15", + "CMT_TOP_SE4BEG3_12", + "CMT_TOP_ER1BEG0_11", + "CMT_TOP_FAN0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_NE2A3_10", + "CMT_TOP_WW4B3_2", + "CMT_TOP_LOGIC_OUTS_L_B3_10", + "CMT_TOP_FAN0_7", + "CMT_TOP_WW4B0_3", + "CMT_TOP_LH11_8", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_TOP_IMUX47_4", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_EE4A0_10", + "CMT_TOP_WW4C1_6", + "CMT_TOP_IMUX35_11", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_NW2A1_11", + "CMT_LR_LOWER_B_MMCM_TESTIN23", + "CMT_TOP_IMUX46_9", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_SW4END3_7", + "CMT_TOP_EE4C0_15", + "CMT_TOP_NE2A3_15", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_NW4END3_6", + "CMT_TOP_EE2BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_EE4B0_12", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_FAN1_15", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_TOP_ER1BEG1_11", + "CMT_TOP_IMUX45_6", + "CMT_TOP_WW4END2_8", + "CMT_TOP_LOGIC_OUTS_L_B23_15", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_WW4END1_0", + "CMT_TOP_LH3_2", + "CMT_TOP_IMUX1_9", + "CMT_TOP_IMUX8_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_IMUX2_8", + "CMT_TOP_WW2A1_12", + "CMT_L_LOWER_B_CLK_MMCM8", + "CMT_LR_LOWER_B_MMCM_TESTOUT26", + "CMT_L_LOWER_B_CLK_MMCM11", + "CMT_TOP_OCLK_5", + "CMT_TOP_BYP0_3", + "CMT_TOP_NE4C0_10", + "CMT_TOP_WW2A2_2", + "CMT_TOP_IMUX25_4", + "CMT_TOP_WL1END1_15", + "CMT_TOP_IMUX20_7", + "CMT_MMCM_DQS_TO_PHASERA", + "CMT_TOP_NW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_LR_LOWER_B_MMCM_DO1", + "CMT_TOP_WW4C0_3", + "CMT_TOP_IMUX28_5", + "CMT_TOP_NE2A0_2", + "CMT_TOP_WL1END2_12", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_WW4END2_15", + "CMT_TOP_EE4A3_12", + "CMT_TOP_BYP1_1", + "CMT_TOP_SE2A3_6", + "CMT_TOP_SW4A1_11", + "CMT_TOP_IMUX2_2", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX21_0", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_WW4END2_9", + "CMT_TOP_SE2A0_2", + "CMT_TOP_IMUX43_1", + "CMT_TOP_EE2BEG2_12", + "CMT_TOP_SE2A3_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT62", + "CMT_TOP_BYP4_12", + "CMT_LR_LOWER_B_MMCM_DO5", + "CMT_TOP_EE4BEG1_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_IMUX28_8", + "CMT_TOP_WW4C3_4", + "CMT_TOP_SW4END0_9", + "CMT_TOP_LH8_1", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_EE4C2_13", + "CMT_TOP_NE2A0_11", + "CMT_TOP_WW2A3_2", + "CMT_TOP_NW4A0_7", + "CMT_TOP_LH9_5", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT1", + "CMT_TOP_EE4C2_15", + "CMT_TOP_IMUX6_7", + "CMT_TOP_IMUX45_10", + "CMT_TOP_EL1BEG0_13", + "CMT_TOP_WR1END3_4", + "CMT_LR_LOWER_B_MMCM_TESTOUT32", + "CMT_TOP_LOGIC_OUTS_L_B13_14", + "CMT_TOP_EE2A0_6", + "CMT_TOP_EE2BEG0_9", + "CMT_LR_LOWER_B_MMCM_TESTOUT9", + "CMT_TOP_ER1BEG1_14", + "CMT_TOP_EE2A2_6", + "CMT_TOP_BYP2_2", + "CMT_TOP_LOGIC_OUTS_L_B14_14", + "CMT_TOP_LOGIC_OUTS_L_B0_11", + "CMT_TOP_IMUX21_6", + "CMT_TOP_SE4C3_1", + "CMT_TOP_SW2A2_3", + "CMT_TOP_EE2A0_14", + "CMT_TOP_IMUX19_7", + "CMT_TOP_IMUX0_4", + "CMT_TOP_ICLK_9", + "CMT_TOP_SW4END2_7", + "CMT_TOP_WW4B3_9", + "CMT_TOP_IMUX15_0", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_WW2A0_15", + "CMT_LR_LOWER_B_MMCM_TESTIN20", + "CMT_TOP_EL1BEG2_9", + "CMT_TOP_IMUX33_12", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_WW4END2_5", + "CMT_TOP_WW2A1_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_IMUX9_8", + "CMT_TOP_WW2A1_9", + "CMT_TOP_OCLK1X_90_13", + "CMT_TOP_SW4A0_4", + "CMT_TOP_LOGIC_OUTS_L_B13_13", + "CMT_TOP_BYP5_15", + "CMT_TOP_BYP0_11", + "CMT_TOP_FAN1_8", + "CMT_TOP_IMUX12_13", + "CMT_TOP_IMUX34_4", + "CMT_TOP_IMUX12_9", + "CMT_TOP_SW4A1_10", + "CMT_TOP_SW4END1_12", + "CMT_TOP_WW4A2_12", + "CMT_TOP_NW4A0_11", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4B0_2", + "CMT_TOP_LH2_2", + "CMT_TOP_IMUX10_7", + "CMT_TOP_IMUX39_0", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_WW4END0_10", + "CMT_TOP_FAN3_13", + "CMT_TOP_IMUX30_10", + "CMT_TOP_NW2A0_9", + "CMT_TOP_IMUX2_15", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_TOP_SW4A3_5", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_IMUX14_1", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_WL1END0_10", + "CMT_TOP_WW2A2_15", + "CMT_TOP_IMUX26_1", + "CMT_TOP_BLOCK_OUTS_L_B2_15", + "CMT_TOP_WL1END0_1", + "CMT_TOP_CTRL0_9", + "CMT_TOP_LH11_6", + "CMT_TOP_NE4C3_8", + "CMT_TOP_IMUX46_12", + "CMT_TOP_NE4BEG1_13", + "CMT_TOP_WL1END0_7", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_TOP_LH12_4", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_NE4C3_4", + "CMT_TOP_ER1BEG0_7", + "CMT_TOP_WL1END2_13", + "CMT_TOP_WW2END2_4", + "CMT_TOP_SE4C2_6", + "CMT_TOP_SW4END1_8", + "CMT_TOP_SE4BEG2_13", + "CMT_TOP_IMUX26_12", + "CMT_TOP_BYP3_14", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_BYP2_13", + "CMT_TOP_SW2A1_1", + "MMCMOUT_CLK_FREQ_BB_3", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_WW4END3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_9", + "CMT_TOP_FAN7_15", + "CMT_TOP_NW2A2_14", + "CMT_TOP_WL1END2_6", + "CMT_TOP_IMUX43_6", + "CMT_TOP_NW4A1_1", + "CMT_TOP_SE4C1_8", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_SE4BEG0_3", + "CMT_TOP_IMUX40_5", + "CMT_TOP_EE2A2_14", + "CMT_TOP_EE4BEG3_2", + "CMT_TOP_BLOCK_OUTS_L_B1_10", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_IMUX34_1", + "CMT_TOP_WL1END2_0", + "CMT_TOP_EE4A1_3", + "CMT_TOP_OCLKDIV_10", + "CMT_TOP_LH7_0", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_IMUX8_11", + "CMT_TOP_WW2END0_2", + "CMT_TOP_IMUX0_3", + "CMT_TOP_EE4A0_1", + "CMT_TOP_WW4A1_4", + "CMT_TOP_IMUX23_3", + "CMT_TOP_IMUX20_0", + "CMT_TOP_WR1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_LH11_9", + "CMT_TOP_IMUX25_1", + "CMT_TOP_ER1BEG1_1", + "CMT_TOP_IMUX44_7", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_TOP_EE2A3_15", + "CMT_TOP_FAN0_12", + "CMT_TOP_WW4A3_10", + "CMT_TOP_IMUX31_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT47", + "CMT_TOP_EL1BEG3_15", + "CMT_TOP_WW2A0_4", + "CMT_TOP_SW2A0_10", + "CMT_TOP_IMUX11_13", + "CMT_TOP_EE4C3_13", + "CMT_TOP_LH6_15", + "CMT_TOP_WW4A3_3", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_LH1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_NW4A0_4", + "CMT_TOP_CLK1_5", + "CMT_TOP_IMUX37_12", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_NE2A0_10", + "CMT_TOP_WW4B2_14", + "CMT_TOP_IMUX21_15", + "CMT_TOP_IMUX18_5", + "CMT_MMCM_PHASERREF0", + "CMT_TOP_LOGIC_OUTS_L_B21_14", + "CMT_TOP_IMUX24_8", + "CMT_TOP_IMUX24_7", + "CMT_TOP_LH12_11", + "CMT_TOP_NW2A2_13", + "CMT_TOP_EE4B0_2", + "CMT_LR_LOWER_B_MMCM_TESTOUT2", + "CMT_TOP_IMUX29_12", + "CMT_TOP_SW2A0_2", + "CMT_TOP_SW4A3_1", + "CMT_TOP_NE4BEG0_13", + "CMT_TOP_EE2A3_10", + "CMT_TOP_IMUX42_12", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_WL1END3_2", + "CMT_TOP_SE4BEG0_11", + "CMT_TOP_FAN4_5", + "CMT_TOP_EE4A1_10", + "CMT_TOP_NE2A1_2", + "CMT_TOP_SE4BEG1_7", + "CMT_TOP_NE2A1_10", + "CMT_TOP_WW2END2_11", + "CMT_TOP_SW4END3_15", + "CMT_TOP_IMUX36_3", + "CMT_TOP_IMUX10_11", + "CMT_TOP_IMUX45_14", + "CMT_TOP_IMUX14_9", + "CMT_TOP_ER1BEG2_11", + "CMT_TOP_IMUX21_7", + "CMT_TOP_EE4B3_11", + "CMT_TOP_IMUX25_7", + "CMT_TOP_SW4A2_5", + "CMT_MMCM_PHASERA_CTSBUS1", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_EE4BEG2_12", + "CMT_TOP_NE2A2_12", + "CMT_TOP_WW4C0_9", + "CMT_TOP_IMUX9_15", + "CMT_TOP_NE4C2_3", + "CMT_TOP_EE4A2_15", + "CMT_TOP_WW4A1_8", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_BYP7_5", + "CMT_TOP_NE2A0_5", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_EE4A0_2", + "CMT_TOP_SW4END3_8", + "CMT_TOP_IMUX20_6", + "CMT_TOP_LH9_3", + "CMT_TOP_EE4B3_0", + "CMT_TOP_EL1BEG1_9", + "CMT_TOP_SW2A2_10", + "CMT_TOP_WW4END3_0", + "CMT_TOP_OCLK_14", + "CMT_TOP_WW2A0_1", + "CMT_TOP_SW4A0_9", + "CMT_TOP_IMUX45_7", + "CMT_TOP_IMUX19_2", + "CMT_TOP_IMUX42_5", + "CMT_TOP_NW4A3_15", + "CMT_TOP_IMUX18_11", + "CMT_TOP_IMUX27_13", + "CMT_TOP_EE4B1_12", + "CMT_TOP_LOGIC_OUTS_L_B10_12", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_BLOCK_OUTS_L_B0_9", + "CMT_TOP_WL1END2_7", + "CMT_L_LOWER_B_CLK_IN2_HCLK", + "CMT_TOP_SW4END3_6", + "CMT_TOP_SW4A0_3", + "CMT_TOP_SE4BEG2_14", + "CMT_LR_LOWER_B_MMCM_DO7", + "CMT_TOP_BYP1_10", + "CMT_TOP_EE4BEG0_15", + "CMT_TOP_IMUX27_7", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_EE4BEG3_12", + "MMCMOUT_CLK_FREQ_BB_2", + "CMT_TOP_SW4A2_10", + "CMT_TOP_IMUX28_12", + "CMT_L_LOWER_B_CLK_PERF0", + "CMT_TOP_LOGIC_OUTS_L_B6_10", + "CMT_TOP_IMUX27_8", + "CMT_TOP_BYP5_6", + "CMT_TOP_SW4END3_14", + "CMT_TOP_IMUX34_3", + "CMT_TOP_EL1BEG2_13", + "CMT_TOP_FAN0_0", + "CMT_TOP_WW2A3_14", + "CMT_TOP_IMUX23_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT12", + "CMT_TOP_WR1END1_1", + "CMT_TOP_WW4END3_6", + "CMT_TOP_WW4B3_7", + "CMT_TOP_SW4A0_7", + "CMT_TOP_NE4BEG1_11", + "CMT_TOP_SW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B15_10", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_LOGIC_OUTS_L_B15_15", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_IMUX6_2", + "CMT_TOP_IMUX10_14", + "MMCM_CLK_FREQ_BB_NS3", + "CMT_TOP_IMUX23_14", + "CMT_TOP_WW4A1_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT14", + "CMT_TOP_NE4BEG2_15", + "CMT_TOP_WW4C2_5", + "CMT_TOP_IMUX40_0", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_EE2A2_8", + "CMT_TOP_NE2A3_7", + "CMT_TOP_ER1BEG1_2", + "MMCM_CLK_FREQ_BB_REBUF1_NS", + "CMT_TOP_SW4END0_12", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_LOGIC_OUTS_L_B14_11", + "CMT_TOP_SE2A3_14", + "CMT_TOP_IMUX3_5", + "CMT_TOP_LH4_5", + "CMT_TOP_BYP7_4", + "CMT_TOP_CLK1_0", + "CMT_TOP_IMUX26_11", + "CMT_TOP_IMUX1_5", + "CMT_TOP_LH9_4", + "CMT_L_LOWER_B_CLK_IN3_INT", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_SE4C2_1", + "CMT_TOP_IMUX38_14", + "CMT_TOP_EE2A3_1", + "CMT_TOP_SW2A2_9", + "CMT_TOP_EL1BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_11", + "CMT_TOP_IMUX28_0", + "CMT_TOP_BYP3_11", + "CMT_TOP_NE4BEG3_15", + "CMT_TOP_IMUX18_2", + "CMT_TOP_WW2END0_1", + "CMT_TOP_LOGIC_OUTS_L_B7_9", + "CMT_TOP_SW2A1_15", + "CMT_TOP_IMUX11_14", + "CMT_TOP_BYP3_0", + "CMT_TOP_BYP4_3", + "CMT_TOP_IMUX17_14", + "CMT_TOP_CLK1_10", + "CMT_TOP_EE4BEG0_11", + "CMT_TOP_NE2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B8_14", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_BLOCK_OUTS_L_B0_11", + "CMT_TOP_EE2A3_8", + "CMT_TOP_EE4A2_8", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_WW4C0_6", + "CMT_TOP_ER1BEG2_14", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_CTRL0_4", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SW4END0_6", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_NW4A3_7", + "CMT_TOP_WW4B1_10", + "CMT_TOP_SE2A3_5", + "CMT_TOP_LH5_10", + "CMT_TOP_WW4END0_11", + "CMT_TOP_BYP7_7", + "CMT_LR_LOWER_B_MMCM_LOCKED", + "CMT_TOP_IMUX29_5", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_IMUX25_5", + "CMT_TOP_WW4A3_4", + "CMT_TOP_NE4BEG0_14", + "CMT_LR_LOWER_B_MMCM_DADDR0", + "CMT_TOP_FAN5_9", + "CMT_TOP_MONITOR_P_15", + "CMT_TOP_IMUX46_8", + "CMT_TOP_IMUX31_11", + "CMT_TOP_BYP4_0", + "CMT_TOP_SE2A0_13", + "CMT_TOP_IMUX18_4", + "CMT_TOP_BLOCK_OUTS_L_B1_14", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_TOP_LOGIC_OUTS_L_B16_9", + "CMT_TOP_WW2A2_3", + "CMT_TOP_IMUX44_12", + "CMT_TOP_IMUX28_3", + "CMT_TOP_SE2A1_12", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WW2A1_11", + "CMT_TOP_LH7_3", + "CMT_TOP_LH6_1", + "CMT_LR_LOWER_B_MMCM_TESTOUT55", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_TOP_NE4BEG1_15", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_NE2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH6_0", + "CMT_TOP_WW4C0_7", + "CMT_TOP_SE4BEG2_2", + "CMT_TOP_WW4END1_10", + "CMT_TOP_IMUX3_13", + "CMT_TOP_LH3_5", + "CMT_TOP_NE4C0_4", + "CMT_TOP_BYP0_10", + "CMT_TOP_SW2A1_7", + "CMT_TOP_NE4C0_2", + "CMT_TOP_IMUX45_13", + "CMT_LR_LOWER_B_MMCM_RST", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "MMCMOUT_CLK_FREQ_BB_0", + "CMT_TOP_SE4C0_7", + "CMT_TOP_EL1BEG3_4", + "CMT_LR_LOWER_B_MMCM_DO0", + "CMT_TOP_SE4C0_12", + "CMT_TOP_LOGIC_OUTS_L_B11_10", + "CMT_TOP_SW4A1_8", + "CMT_MMCM_PHASER_OUT_B_OCLK1X_90", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_LH11_11", + "CMT_TOP_WR1END3_3", + "CMT_TOP_MONITOR_P_1", + "CMT_TOP_OCLK_15", + "CMT_TOP_LH8_8", + "CMT_TOP_EE4A0_14", + "CMT_TOP_SW4A3_6", + "CMT_TOP_SW4END1_11", + "CMT_TOP_WW4END3_15", + "CMT_TOP_IMUX31_8", + "CMT_TOP_IMUX18_13", + "CMT_TOP_EE2A3_0", + "CMT_TOP_IMUX21_11", + "CMT_TOP_IMUX13_2", + "CMT_TOP_IMUX39_4", + "CMT_TOP_NW4END2_11", + "CMT_LR_LOWER_B_MMCM_CLKOUT3B", + "CMT_TOP_MONITOR_P_3", + "CMT_LR_LOWER_B_MMCM_TESTOUT7", + "CMT_TOP_EE4B1_7", + "CMT_TOP_WW4A0_7", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_FAN1_13", + "CMT_TOP_IMUX21_13", + "CMT_TOP_WW4B0_11", + "CMT_TOP_SE2A1_2", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_BYP5_11", + "CMT_TOP_NE2A0_4", + "CMT_TOP_LH9_0", + "CMT_TOP_IMUX22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_10", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_IMUX25_6", + "CMT_TOP_NE2A1_4", + "CMT_TOP_EE4BEG3_0", + "CMT_TOP_WW2END1_7", + "CMT_TOP_EE4B0_7", + "CMT_TOP_LH11_15", + "CMT_TOP_WW4B2_10", + "CMT_TOP_BYP1_0", + "CMT_TOP_IMUX22_4", + "CMT_TOP_SE4C1_0", + "CMT_TOP_IMUX24_14", + "CMT_TOP_FAN7_3", + "CMT_TOP_WW4A0_6", + "CMT_TOP_WW2END2_1", + "CMT_TOP_IMUX45_5", + "CMT_TOP_BYP6_4", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_TOP_BYP3_5", + "CMT_TOP_EE2A0_3", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_EE4C2_2", + "CMT_TOP_FAN2_10", + "CMT_TOP_CTRL1_5", + "CMT_TOP_CTRL0_5", + "CMT_TOP_WW2END0_6", + "CMT_TOP_IMUX1_3", + "CMT_TOP_NW4A1_15", + "CMT_TOP_WW2END0_7", + "CMT_TOP_NW4END0_11", + "CMT_TOP_EL1BEG0_12", + "CMT_TOP_IMUX41_13", + "CMT_TOP_LOGIC_OUTS_L_B20_11", + "CMT_TOP_WW4END1_12", + "CMT_TOP_WL1END2_3", + "CMT_TOP_EL1BEG3_14", + "CMT_TOP_IMUX36_11", + "CMT_MMCM_PHASERREF_ABOVE1", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_IMUX10_3", + "CMT_TOP_SW4A2_13", + "CMT_LR_LOWER_B_MMCM_DO6", + "CMT_TOP_IMUX37_10", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_SW4A3_12", + "CMT_TOP_NW2A0_13", + "CMT_TOP_BYP6_13", + "CMT_TOP_SW4END2_15", + "CMT_TOP_WR1END3_8", + "CMT_TOP_SW4A3_14", + "CMT_TOP_IMUX17_15", + "CMT_TOP_IMUX47_1", + "CMT_TOP_IMUX10_6", + "CMT_TOP_IMUX44_10", + "CMT_TOP_BYP6_11", + "CMT_TOP_NE4C1_0", + "CMT_TOP_WW4A3_1", + "CMT_TOP_BYP6_6", + "CMT_TOP_BYP4_10", + "CMT_TOP_LOGIC_OUTS_L_B23_11", + "CMT_LR_LOWER_B_MMCM_TESTIN24", + "CMT_TOP_NE4C0_3", + "CMT_TOP_SW4A3_9", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_OCLKDIV_8", + "CMT_TOP_LH2_1", + "CMT_TOP_EE4A3_13", + "CMT_TOP_IMUX42_1", + "CMT_TOP_SW4A1_6", + "CMT_TOP_LH12_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT10", + "CMT_TOP_LOGIC_OUTS_L_B22_13", + "CMT_TOP_NW4A2_13", + "CMT_TOP_IMUX7_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT23", + "CMT_TOP_NW4A1_9", + "CMT_TOP_BYP1_8", + "CMT_TOP_WW4C2_1", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_IMUX42_0", + "CMT_TOP_NW4A1_14", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_FAN7_1", + "CMT_TOP_IMUX13_13", + "CMT_TOP_SE4C2_9", + "CMT_TOP_LOGIC_OUTS_L_B16_14", + "CMT_TOP_IMUX38_12", + "CMT_TOP_WW2A3_0", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_WW4A2_9", + "CMT_TOP_NW4END3_13", + "CMT_TOP_NE4C2_12", + "CMT_TOP_ICLK_14", + "CMT_TOP_WW2A3_15", + "MMCMOUT_CLK_FREQ_BB_1", + "CMT_TOP_LH1_7", + "CMT_TOP_EE2BEG2_11", + "CMT_TOP_NW4A1_6", + "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "CMT_TOP_BYP2_1", + "CMT_TOP_WL1END2_10", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_IMUX13_0", + "CMT_TOP_EE2A3_14", + "CMT_TOP_LOGIC_OUTS_L_B22_12", + "CMT_TOP_LH9_15", + "CMT_TOP_IMUX30_7", + "CMT_TOP_IMUX32_15", + "CMT_TOP_WW4A0_3", + "CMT_TOP_FAN2_0", + "CMT_TOP_BLOCK_OUTS_L_B1_9", + "CMT_TOP_MONITOR_N_13", + "CMT_TOP_IMUX18_9", + "CMT_TOP_CTRL1_0", + "CMT_TOP_EE2A0_5", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_TOP_IMUX30_12", + "CMT_TOP_WW4A0_1", + "CMT_TOP_SE4BEG0_13", + "CMT_TOP_FAN3_0", + "CMT_TOP_LH2_7", + "CMT_TOP_OCLKDIV_13", + "CMT_TOP_IMUX30_2", + "CMT_TOP_FAN3_3", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_IMUX2_5", + "CMT_TOP_IMUX28_4", + "CMT_TOP_IMUX10_9", + "CMT_TOP_MONITOR_N_14", + "CMT_TOP_EL1BEG3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_9", + "CMT_TOP_LH11_0", + "CMT_TOP_EE4C1_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT29", + "CMT_TOP_IMUX15_5", + "CMT_TOP_IMUX13_8", + "CMT_TOP_SE4C1_9", + "CMT_TOP_EE4C0_5", + "CMT_TOP_IMUX2_0", + "CMT_TOP_NE4BEG3_1", + "CMT_LR_LOWER_B_MMCM_CLKOUT4", + "CMT_TOP_SW4END1_1", + "CMT_TOP_WW4B0_13", + "CMT_TOP_LH12_7", + "CMT_TOP_WW4C3_13", + "CMT_TOP_WR1END3_7", + "CMT_TOP_WL1END1_7", + "CMT_TOP_OCLK_4", + "CMT_L_LOWER_B_CLK_IN1_HCLK", + "CMT_TOP_EE4C1_2", + "CMT_TOP_BYP0_4", + "CMT_TOP_FAN4_0", + "CMT_TOP_BYP7_10", + "CMT_TOP_SW2A0_9", + "CMT_TOP_IMUX2_13", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_MONITOR_N_9", + "CMT_TOP_WW4A1_3", + "CMT_TOP_WW4END0_9", + "CMT_TOP_FAN4_4", + "CMT_TOP_SW2A0_15", + "CMT_TOP_ICLKDIV_9", + "CMT_TOP_IMUX25_12", + "CMT_TOP_NW4END1_13", + "CMT_TOP_IMUX39_15", + "CMT_TOP_IMUX7_8", + "CMT_TOP_LOGIC_OUTS_L_B5_11", + "CMT_TOP_WW4B2_11", + "CMT_TOP_BYP7_0", + "CMT_TOP_ICLKDIV_13", + "CMT_TOP_FAN7_11", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_BYP6_2", + "CMT_TOP_EL1BEG3_1", + "CMT_MMCM_PHASER_OUT_A_OCLKDIV", + "CMT_LR_LOWER_B_MMCM_TESTOUT22", + "CMT_TOP_EE4C2_8", + "CMT_TOP_IMUX14_6", + "CMT_TOP_LOGIC_OUTS_L_B19_11", + "CMT_TOP_SW4A2_11", + "CMT_LR_LOWER_B_MMCM_DO8", + "CMT_TOP_IMUX10_1", + "CMT_TOP_WW4END1_14", + "CMT_TOP_NE4C3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_LOGIC_OUTS_L_B8_9", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_IMUX37_11", + "CMT_TOP_IMUX40_14", + "CMT_TOP_IMUX6_4", + "CMT_TOP_BLOCK_OUTS_L_B0_10", + "CMT_TOP_BLOCK_OUTS_L_B1_11", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_TOP_CTRL0_11", + "CMT_TOP_IMUX43_7", + "CMT_TOP_LOGIC_OUTS_L_B23_9", + "CMT_TOP_EE2BEG0_4", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LOGIC_OUTS_L_B7_10", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_WW4B0_14", + "CMT_TOP_IMUX38_7", + "CMT_TOP_IMUX21_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT50", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_SW4A2_7", + "CMT_TOP_OCLK1X_90_10", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_LH1_2", + "CMT_TOP_BYP0_9", + "CMT_TOP_LOGIC_OUTS_L_B4_10", + "CMT_TOP_LOGIC_OUTS_L_B11_15", + "CMT_TOP_LOGIC_OUTS_L_B23_14", + "CMT_TOP_IMUX44_13", + "CMT_TOP_FAN4_10", + "CMT_TOP_IMUX30_3", + "CMT_TOP_WR1END3_10", + "CMT_TOP_EE2BEG3_9", + "CMT_TOP_WR1END1_6", + "CMT_TOP_SW2A2_5", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_NW2A1_8", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_IMUX15_11", + "CMT_TOP_IMUX36_9", + "CMT_TOP_EE4B2_1", + "CMT_TOP_IMUX38_15", + "CMT_TOP_SW2A2_0", + "CMT_TOP_NW4END2_3", + "CMT_TOP_WW4A0_15", + "CMT_TOP_FAN4_2", + "CMT_TOP_IMUX10_13", + "CMT_TOP_IMUX43_0", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_WW4END0_8", + "CMT_TOP_SW4A1_4", + "CMT_TOP_WW2A2_12", + "CMT_TOP_CLK0_12", + "CMT_TOP_IMUX29_0", + "CMT_TOP_FAN6_0", + "CMT_TOP_NW2A2_12", + "CMT_TOP_IMUX43_2", + "CMT_TOP_EE4B1_1", + "CMT_TOP_NW2A2_8", + "CMT_TOP_CTRL1_10", + "CMT_TOP_IMUX23_13", + "CMT_TOP_WL1END1_14", + "CMT_TOP_WW2A0_3", + "CMT_TOP_WW2A2_5", + "CMT_TOP_FAN4_9", + "CMT_TOP_SW4END1_6", + "CMT_TOP_NE4BEG0_9", + "CMT_TOP_EE4B2_5", + "MMCM_CLK_FREQ_BB_NS2", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_WW2A2_0", + "CMT_TOP_ER1BEG1_13", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_NE4C3_2", + "CMT_LR_LOWER_B_MMCM_TESTOUT25", + "CMT_TOP_WW2END3_3", + "CMT_TOP_SE4BEG3_4", + "CMT_TOP_IMUX5_4", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_TOP_WW2END3_2", + "CMT_TOP_NE4C2_1", + "CMT_TOP_WR1END0_15", + "CMT_TOP_SW4END2_2", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_NE2A3_8", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_EE2A2_15", + "CMT_TOP_EE2BEG2_15", + "CMT_TOP_LOGIC_OUTS_L_B2_11", + "CMT_TOP_SW4A1_3", + "CMT_TOP_OCLK1X_90_15", + "CMT_TOP_NW4A2_8", + "CMT_TOP_WR1END1_5", + "CMT_TOP_SE4C2_5", + "CMT_LR_LOWER_B_MMCM_TESTOUT31", + "CMT_TOP_LOGIC_OUTS_L_B22_11", + "CMT_TOP_WW4C2_15", + "CMT_TOP_ER1BEG3_3", + "CMT_TOP_WW2A3_9", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_FAN2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_IMUX23_15", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_IMUX41_2", + "CMT_TOP_EE4B2_15", + "CMT_TOP_NE4C0_15", + "CMT_TOP_IMUX20_2", + "CMT_TOP_SW4END2_6", + "CMT_TOP_NW4END0_9", + "CMT_TOP_IMUX45_1", + "CMT_TOP_LOGIC_OUTS_L_B18_12", + "CMT_TOP_IMUX24_9", + "CMT_TOP_WW4B3_3", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_WW4C1_12", + "CMT_TOP_NE4C3_3", + "CMT_TOP_BYP2_0", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_WL1END3_13", + "CMT_TOP_LH8_12", + "CMT_TOP_LH12_6", + "CMT_TOP_SW4END2_9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_EE4A1_1", + "CMT_TOP_IMUX27_9", + "CMT_TOP_SW4A0_10", + "CMT_TOP_IMUX26_3", + "CMT_TOP_SW4A2_0", + "CMT_TOP_EL1BEG3_9", + "CMT_TOP_ER1BEG1_15", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_FAN6_14", + "CMT_TOP_LOGIC_OUTS_L_B2_10", + "CMT_MMCM_A_WREN_TOFIFO", + "CMT_TOP_IMUX47_0", + "CMT_TOP_IMUX7_10", + "CMT_TOP_FAN5_5", + "CMT_TOP_NW4END2_10", + "CMT_TOP_SE4C0_3", + "CMT_TOP_IMUX45_4", + "CMT_TOP_EL1BEG1_11", + "CMT_TOP_EE2A3_7", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_EE4A3_9", + "CMT_TOP_IMUX19_0", + "CMT_TOP_WR1END0_0", + "CMT_TOP_BYP4_15", + "CMT_TOP_WW4B1_12", + "CMT_TOP_SW4A1_13", + "CMT_TOP_EE4BEG1_9", + "CMT_TOP_NE2A3_3", + "CMT_TOP_WW4C1_8", + "CMT_TOP_SW4A3_10", + "CMT_TOP_FAN5_11", + "CMT_TOP_NE4C0_5", + "CMT_LR_LOWER_B_MMCM_TESTIN4", + "CMT_TOP_IMUX8_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT36", + "CMT_LR_LOWER_B_MMCM_TESTOUT46", + "CMT_TOP_WL1END2_2", + "CMT_TOP_SE2A0_9", + "CMT_TOP_EE4A3_4", + "CMT_TOP_WW4END0_12", + "CMT_TOP_BYP1_2", + "CMT_TOP_WW4END2_3", + "CMT_TOP_IMUX24_2", + "CMT_TOP_IMUX6_0", + "CMT_TOP_NW4END1_10", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_WW2END2_10", + "CMT_TOP_EE4B2_0", + "CMT_TOP_IMUX45_12", + "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", + "CMT_TOP_SW2A0_7", + "CMT_TOP_CLK0_8", + "CMT_TOP_IMUX44_0", + "CMT_TOP_EE4C3_10", + "CMT_TOP_BYP4_6", + "CMT_TOP_LH2_12", + "CMT_TOP_WW2END1_11", + "CMT_TOP_IMUX7_0", + "CMT_TOP_IMUX9_4", + "CMT_TOP_EE4A0_4", + "CMT_TOP_LH9_6", + "CMT_TOP_SW2A3_7", + "CMT_TOP_WW4END2_13", + "CMT_TOP_WW4A3_9", + "CMT_MMCM_PHYCTRL_SYNC_BB_UP", + "CMT_TOP_NW4END3_8", + "CMT_TOP_NW4A1_2", + "CMT_TOP_SE2A0_7", + "CMT_TOP_WW4B1_3", + "CMT_TOP_BYP4_11", + "CMT_TOP_IMUX16_15", + "CMT_TOP_WR1END2_8", + "CMT_TOP_LH4_12", + "CMT_TOP_NW2A0_2", + "CMT_TOP_EE4B0_3", + "CMT_TOP_FAN1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_10", + "CMT_TOP_SE2A1_4", + "CMT_TOP_SE4C0_6", + "CMT_TOP_LH6_14", + "MMCM_CLK_FREQ_BB_NS1", + "CMT_TOP_IMUX17_4", + "CMT_LR_LOWER_B_MMCM_DI15", + "CMT_TOP_LH2_10", + "CMT_TOP_EL1BEG1_13", + "CMT_TOP_WR1END1_15", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_EL1BEG1_12", + "CMT_TOP_WW4END0_15", + "CMT_TOP_SW4END2_4", + "CMT_TOP_WL1END0_6", + "CMT_TOP_LOGIC_OUTS_L_B13_12", + "CMT_TOP_IMUX35_14", + "CMT_MMCM_A_RDEN_TOFIFO", + "CMT_LR_LOWER_B_MMCM_TESTOUT44", + "CMT_TOP_IMUX22_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT63", + "CMT_TOP_IMUX37_2", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_BYP1_14", + "CMT_TOP_FAN3_15", + "CMT_TOP_EE4B3_6", + "CMT_TOP_NW4END2_5", + "CMT_TOP_EE4A1_7", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_IMUX15_3", + "CMT_TOP_EE2A3_12", + "CMT_TOP_LH7_10", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_WR1END3_9", + "CMT_TOP_WW2END3_10", + "CMT_TOP_SW4A0_13", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_LH6_7", + "CMT_TOP_WW4END3_12", + "CMT_TOP_EE4C2_10", + "CMT_TOP_IMUX11_3", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_MONITOR_P_12", + "CMT_TOP_EE4B2_4", + "CMT_TOP_WW2A3_5", + "CMT_TOP_WW2END2_6", + "CMT_TOP_SW4END0_7", + "CMT_TOP_OCLK_9", + "CMT_TOP_LH1_9", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_BYP7_11", + "CMT_TOP_WL1END1_2", + "CMT_TOP_SE4C3_13", + "CMT_TOP_FAN5_15", + "CMT_TOP_WW2A3_8", + "CMT_TOP_WW2END3_0", + "CMT_TOP_LH6_13", + "CMT_TOP_IMUX30_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT3", + "CMT_TOP_EL1BEG0_1", + "CMT_TOP_IMUX22_5", + "CMT_TOP_FAN2_11", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_IMUX12_0", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_NE2A1_1", + "CMT_TOP_IMUX19_3", + "CMT_TOP_WW4B0_5", + "CMT_TOP_ICLK_8", + "CMT_TOP_EE4A2_14", + "CMT_TOP_IMUX45_15", + "CMT_TOP_IMUX7_9", + "CMT_TOP_WW2END3_13", + "CMT_TOP_IMUX7_6", + "CMT_TOP_SW2A1_2", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_IMUX36_2", + "CMT_TOP_WW2END3_1", + "CMT_TOP_NE4C0_1", + "CMT_TOP_IMUX11_11", + "CMT_TOP_BYP3_10", + "CMT_TOP_IMUX11_5", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_TOP_NE4BEG2_2", + "CMT_LR_LOWER_B_MMCM_TESTIN2", + "CMT_TOP_IMUX30_1", + "CMT_TOP_WR1END1_12", + "CMT_TOP_WW2END0_11", + "CMT_TOP_WW4C1_9", + "CMT_TOP_SE4C3_2", + "CMT_TOP_NE4C0_7", + "CMT_TOP_EE4A2_1", + "CMT_TOP_WW2END2_9", + "CMT_TOP_SW2A0_14", + "CMT_TOP_IMUX43_3", + "CMT_TOP_IMUX33_3", + "CMT_TOP_IMUX21_4", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_LH5_8", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_NW4A2_10", + "CMT_TOP_WW4END3_1", + "CMT_TOP_LOGIC_OUTS_L_B14_10", + "CMT_TOP_IMUX35_4", + "CMT_TOP_WW4A3_13", + "CMT_TOP_SW4A0_14", + "CMT_TOP_NE4C1_10", + "CMT_TOP_LOGIC_OUTS_L_B3_9", + "CMT_TOP_IMUX42_8", + "CMT_TOP_EE2A3_4", + "CMT_TOP_EE4BEG2_6", + "CMT_TOP_LH3_14", + "CMT_TOP_NW4END3_14", + "CMT_TOP_IMUX38_8", + "CMT_TOP_CLK0_0", + "CMT_TOP_SE2A1_6", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_LH8_11", + "CMT_TOP_FAN7_2", + "CMT_TOP_EE2A0_7", + "CMT_TOP_IMUX19_13", + "CMT_TOP_NE4BEG3_13", + "CMT_TOP_WW4A0_13", + "CMT_TOP_NE4BEG2_10", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_WW4C3_9", + "CMT_TOP_EE2BEG0_10", + "CMT_TOP_IMUX37_1", + "CMT_TOP_EE4C3_5", + "CMT_TOP_NE4C3_5", + "CMT_TOP_LOGIC_OUTS_L_B6_13", + "CMT_TOP_IMUX10_15", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_IMUX35_13", + "CMT_TOP_SE2A0_15", + "CMT_TOP_ER1BEG2_12", + "CMT_TOP_BYP5_2", + "CMT_TOP_NE2A0_12", + "CMT_TOP_EE4B1_15", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_IMUX6_1", + "CMT_TOP_NE2A0_9", + "CMT_TOP_IMUX36_4", + "CMT_TOP_IMUX47_14", + "CMT_TOP_BYP4_1", + "CMT_TOP_IMUX9_3", + "CMT_TOP_IMUX15_6", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_SE2A2_13", + "CMT_TOP_IMUX7_3", + "CMT_TOP_NW4END1_1", + "CMT_TOP_FAN3_8", + "CMT_TOP_LH4_1", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX45_0", + "CMT_TOP_ER1BEG3_13", + "CMT_TOP_EE4B1_9", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_FAN6_9", + "CMT_TOP_LH8_15", + "CMT_TOP_EE4C2_3", + "CMT_TOP_SW4A1_15", + "CMT_TOP_WR1END1_8", + "CMT_TOP_IMUX19_9", + "CMT_TOP_IMUX5_10", + "CMT_TOP_NE2A0_15", + "CMT_TOP_WR1END3_13", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_EL1BEG0_11", + "CMT_TOP_EE4A0_5", + "CMT_TOP_IMUX24_13", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NW2A0_5", + "CMT_TOP_CTRL1_15", + "CMT_TOP_IMUX24_10", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_IMUX16_10", + "CMT_TOP_EE4BEG1_13", + "CMT_TOP_LOGIC_OUTS_L_B8_12", + "CMT_TOP_SW4END1_4", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX5_11", + "CMT_TOP_LOGIC_OUTS_L_B17_11", + "CMT_TOP_EE4C0_9", + "CMT_TOP_EE4B0_1", + "CMT_TOP_IMUX18_6", + "CMT_TOP_SW2A3_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_WW4A3_7", + "CMT_TOP_LH10_15", + "CMT_TOP_WW4A1_7", + "CMT_TOP_IMUX41_6", + "CMT_TOP_WW4C3_15", + "CMT_TOP_EL1BEG2_15", + "CMT_TOP_LH4_0", + "CMT_TOP_SW2A2_8", + "CMT_TOP_WW2A0_9", + "CMT_TOP_BYP2_7", + "CMT_TOP_LOGIC_OUTS_L_B12_12", + "CMT_LR_LOWER_B_MMCM_TESTOUT61", + "CMT_TOP_SW4A1_2", + "CMT_TOP_FAN3_4", + "CMT_TOP_IMUX4_10", + "CMT_TOP_SW4END3_3", + "CMT_TOP_LOGIC_OUTS_L_B17_12", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH11_7", + "CMT_TOP_NW2A3_1", + "CMT_TOP_WW4A1_5", + "CMT_TOP_WW2A2_11", + "CMT_TOP_FAN3_5", + "CMT_TOP_EE4C1_3", + "CMT_TOP_WW2A2_7", + "CMT_TOP_BYP5_10", + "CMT_TOP_OCLK_1", + "CMT_TOP_EE4C1_9", + "CMT_TOP_WL1END3_4", + "CMT_TOP_EE2A0_10", + "CMT_TOP_BYP7_15", + "CMT_LR_LOWER_B_MMCM_CLKIN2", + "CMT_TOP_BYP0_14", + "CMT_TOP_FAN2_14", + "CMT_TOP_WW4END2_12", + "CMT_TOP_IMUX41_12", + "CMT_TOP_EE4B3_2", + "CMT_TOP_SW2A1_11", + "CMT_TOP_BYP1_12", + "CMT_TOP_NW4END2_2", + "CMT_TOP_IMUX15_15", + "CMT_TOP_SE4C0_4", + "CMT_TOP_LOGIC_OUTS_L_B2_12", + "CMT_TOP_ICLK_15", + "CMT_TOP_FAN6_1", + "CMT_TOP_EE4C1_7", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_IMUX28_11", + "CMT_TOP_SE4C1_6", + "CMT_TOP_SW4END0_15", + "CMT_TOP_IMUX39_6", + "MMCM_CLK_FREQ_BB_REBUF3_NS", + "CMT_TOP_IMUX35_2", + "CMT_TOP_LOGIC_OUTS_L_B5_14", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_NE2A1_9", + "CMT_TOP_WL1END0_2", + "CMT_TOP_IMUX33_10", + "CMT_TOP_IMUX44_1", + "CMT_TOP_LOGIC_OUTS_L_B22_9", + "CMT_TOP_IMUX41_10", + "CMT_LR_LOWER_B_MMCM_TESTIN27", + "CMT_LR_LOWER_B_MMCM_TESTOUT4", + "CMT_MMCM_PHASERA_DTSBUS1", + "CMT_TOP_WW2A1_2", + "CMT_TOP_IMUX16_5", + "CMT_TOP_NW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_TOP_IMUX39_7", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_TOP_SW4END3_10", + "CMT_TOP_IMUX26_0", + "CMT_TOP_EL1BEG0_4", + "CMT_TOP_IMUX18_15", + "CMT_TOP_IMUX4_6", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_IMUX4_14", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_EE4B3_3", + "CMT_TOP_LOGIC_OUTS_L_B21_13", + "CMT_TOP_WW4B0_6", + "CMT_TOP_NW2A0_1", + "CMT_TOP_EE4C2_14", + "CMT_TOP_IMUX27_4", + "CMT_TOP_LOGIC_OUTS_L_B0_10", + "CMT_TOP_NE4BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_EE4C1_8", + "CMT_TOP_EE4C1_4", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_SW2A3_9", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_WW4END0_14", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_BYP2_4", + "CMT_TOP_WL1END0_15", + "CMT_TOP_IMUX0_9", + "CMT_TOP_NW2A3_6", + "CMT_TOP_LH3_15", + "CMT_TOP_IMUX42_14", + "CMT_TOP_WW4A0_14", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_CLK0_7", + "CMT_TOP_WL1END3_0", + "CMT_TOP_FAN5_13", + "CMT_LR_LOWER_B_MMCM_TESTOUT52", + "CMT_TOP_IMUX13_7", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_EE2A2_0", + "CMT_LR_LOWER_B_MMCM_DCLK", + "CMT_TOP_ICLK_4", + "CMT_TOP_LOGIC_OUTS_L_B21_9", + "CMT_TOP_IMUX4_0", + "CMT_TOP_EE4BEG0_13", + "CMT_TOP_MONITOR_P_9", + "CMT_TOP_IMUX3_6", + "CMT_TOP_EE4B0_11", + "CMT_TOP_BYP7_1", + "CMT_TOP_OCLKDIV_9", + "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "CMT_TOP_WW2END0_8", + "CMT_L_LOWER_B_CLK_PERF1", + "CMT_TOP_FAN1_14", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_WW2END1_3", + "CMT_TOP_NE4C2_14", + "CMT_TOP_SE2A3_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_NE4BEG3_9", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_BYP3_4", + "CMT_TOP_SE4C3_0", + "CMT_TOP_IMUX25_8", + "CMT_TOP_NE4BEG1_12", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_SW4END3_0", + "CMT_LR_LOWER_B_MMCM_CLKOUT5", + "CMT_TOP_WW4C0_12", + "CMT_TOP_IMUX3_3", + "CMT_TOP_WW2END1_2", + "CMT_TOP_SE4C1_3", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_LH9_10", + "CMT_TOP_WW2A0_11", + "CMT_TOP_IMUX25_11", + "CMT_TOP_IMUX46_13", + "CMT_TOP_NW2A1_1", + "CMT_TOP_IMUX6_15", + "CMT_TOP_IMUX36_15", + "CMT_TOP_IMUX14_12", + "CMT_TOP_CTRL1_14", + "CMT_TOP_SE2A2_15", + "CMT_TOP_NW2A2_5", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX19_6", + "CMT_TOP_IMUX25_15", + "CMT_TOP_WW4A1_2", + "CMT_TOP_EE2BEG0_14", + "CMT_TOP_NW4A2_9", + "CMT_TOP_IMUX19_11", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_SE4BEG2_5", + "CMT_LR_LOWER_B_MMCM_DO14", + "CMT_TOP_BLOCK_OUTS_L_B3_11", + "CMT_TOP_CLK1_13", + "CMT_LR_LOWER_B_MMCM_DO3", + "CMT_TOP_NE4C3_11", + "CMT_TOP_FAN2_13", + "CMT_TOP_NW4END2_9", + "CMT_TOP_WW2A1_7", + "CMT_TOP_SW4END0_8", + "CMT_TOP_WW4A2_15", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WL1END0_4", + "CMT_TOP_IMUX35_1", + "CMT_TOP_IMUX18_12", + "CMT_TOP_NE4C1_1", + "CMT_TOP_WL1END0_5", + "CMT_LR_LOWER_B_MMCM_DO15", + "CMT_TOP_IMUX6_9", + "CMT_TOP_NE2A0_13", + "CMT_TOP_WL1END2_15", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_IMUX20_1", + "CMT_TOP_LH1_13", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_WL1END2_14", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B3_15", + "CMT_TOP_WW4C1_15", + "CMT_TOP_WW4C3_0", + "CMT_TOP_EL1BEG2_14", + "CMT_TOP_EE4A3_15", + "CMT_TOP_FAN4_3", + "CMT_TOP_NW4END1_12", + "CMT_TOP_WR1END3_2", + "CMT_TOP_WW4B3_11", + "CMT_TOP_SE2A2_9", + "CMT_TOP_IMUX5_7", + "CMT_TOP_OCLKDIV_14", + "CMT_TOP_LH7_11", + "CMT_TOP_FAN7_10", + "CMT_TOP_IMUX22_11", + "CMT_TOP_LH12_13", + "CMT_TOP_IMUX40_10", + "CMT_TOP_SE4C3_14", + "CMT_TOP_WW2A2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_WR1END0_14", + "CMT_TOP_WW2END0_4", + "CMT_TOP_NW2A2_1", + "CMT_TOP_EE4A1_9", + "CMT_TOP_NE4C3_6", + "CMT_TOP_OCLK_7", + "CMT_TOP_LOGIC_OUTS_L_B4_14", + "CMT_TOP_IMUX20_14", + "CMT_TOP_ER1BEG2_0", + "CMT_TOP_NW4A2_3", + "CMT_TOP_EE2BEG1_10", + "CMT_MMCM_PHASERREF_BELOW1", + "CMT_TOP_EE2BEG0_12", + "CMT_TOP_WW4C3_3", + "CMT_TOP_NW4END1_4", + "CMT_TOP_NW2A1_2", + "CMT_TOP_EE4BEG0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_TOP_WW4END0_7", + "CMT_TOP_SW2A3_13", + "CMT_TOP_SW4A3_2", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_IMUX5_8", + "CMT_LR_LOWER_B_MMCM_TESTIN13", + "CMT_TOP_WW4A1_11", + "CMT_TOP_SW4A1_5", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_MONITOR_N_11", + "CMT_TOP_IMUX32_6", + "CMT_TOP_SE2A2_12", + "CMT_TOP_NW4A2_14", + "CMT_TOP_NW2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_WW4B2_13", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_WW4B0_10", + "CMT_TOP_WW4A1_0", + "CMT_TOP_SW4END2_14", + "CMT_TOP_LH1_14", + "CMT_TOP_EE2A3_6", + "CMT_TOP_WR1END2_10", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_BYP0_6", + "CMT_LR_LOWER_B_MMCM_TESTIN0", + "CMT_TOP_WL1END1_5", + "CMT_TOP_IMUX30_0", + "CMT_TOP_LOGIC_OUTS_L_B5_9", + "CMT_LR_LOWER_B_MMCM_TESTIN7", + "CMT_TOP_NE4C2_13", + "CMT_TOP_NW2A0_8", + "CMT_TOP_WW4C1_5", + "CMT_TOP_SE4BEG2_11", + "CMT_TOP_NW4A3_11", + "CMT_TOP_WW4C3_12", + "CMT_TOP_IMUX34_6", + "CMT_TOP_SW4A2_4", + "CMT_TOP_NE4C3_1", + "CMT_TOP_NW4A1_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT59", + "CMT_TOP_IMUX22_6", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX1_4", + "CMT_MMCM_A_WRCLK_TOFIFO", + "CMT_TOP_SW4A1_0", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_IMUX41_9", + "CMT_TOP_FAN2_2", + "CMT_TOP_IMUX33_4", + "CMT_TOP_SE4C0_8", + "CMT_TOP_EE2BEG0_11", + "CMT_TOP_NE4BEG3_12", + "CMT_TOP_IMUX32_8", + "CMT_TOP_FAN0_15", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_EE2BEG1_3", + "CMT_TOP_EE2A2_4", + "CMT_TOP_WW4B2_7", + "CMT_TOP_EE4B1_3", + "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "CMT_TOP_SW4END0_0", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH10_2", + "CMT_TOP_IMUX4_8", + "CMT_TOP_NE4C1_11", + "CMT_TOP_WW2A1_1", + "CMT_TOP_WW4END0_13", + "CMT_TOP_EE4A1_0", + "CMT_LR_LOWER_B_MMCM_DI10", + "CMT_LR_LOWER_B_MMCM_DI1", + "CMT_TOP_IMUX9_6", + "CMT_TOP_IMUX42_3", + "CMT_TOP_IMUX13_10", + "CMT_TOP_IMUX20_15", + "CMT_TOP_WR1END0_6", + "CMT_TOP_OCLK1X_90_11", + "CMT_TOP_BYP6_15", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_TOP_IMUX0_13", + "CMT_TOP_IMUX22_2", + "CMT_LR_LOWER_B_MMCM_DI6", + "CMT_TOP_IMUX15_13", + "CMT_TOP_SE4C3_6", + "CMT_TOP_IMUX44_4", + "CMT_L_LOWER_B_CLK_MMCM6", + "CMT_TOP_SE2A0_14", + "CMT_TOP_LH8_13", + "CMT_TOP_CTRL0_1", + "CMT_TOP_IMUX29_10", + "CMT_TOP_IMUX12_11", + "CMT_TOP_WW4B2_0", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_BLOCK_OUTS_L_B3_14", + "CMT_TOP_LH12_5", + "CMT_TOP_NE4BEG3_11", + "CMT_TOP_IMUX12_6", + "CMT_TOP_IMUX23_4", + "CMT_TOP_NE4BEG1_5", + "CMT_TOP_IMUX43_13", + "CMT_TOP_NE2A3_6", + "CMT_TOP_ICLK_3", + "CMT_TOP_IMUX7_4", + "CMT_TOP_CLK0_4", + "CMT_TOP_SE2A3_4", + "CMT_TOP_NE2A3_11", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_IMUX28_6", + "CMT_TOP_WW4A3_8", + "CMT_TOP_EE2A0_0", + "CMT_TOP_SE2A1_0", + "CMT_TOP_LH12_10", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_L_LOWER_B_CLK_MMCM4", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_WW4B1_2", + "CMT_TOP_CTRL1_3", + "CMT_TOP_IMUX30_14", + "CMT_TOP_OCLK1X_90_12", + "CMT_TOP_EE4A3_8", + "CMT_TOP_NW4A0_2", + "CMT_TOP_IMUX26_5", + "CMT_TOP_OCLK1X_90_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT19", + "CMT_TOP_IMUX27_10", + "CMT_TOP_EE4BEG3_10", + "CMT_TOP_LH6_3", + "CMT_TOP_IMUX40_6", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_WR1END2_4", + "CMT_TOP_WW4C1_11", + "CMT_TOP_IMUX20_4", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_TOP_LOGIC_OUTS_L_B11_14", + "CMT_TOP_WW4END2_7", + "CMT_TOP_BYP4_7", + "CMT_TOP_FAN4_11", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_TOP_LOGIC_OUTS_L_B20_15", + "CMT_TOP_NE2A2_8", + "CMT_TOP_NW4A2_15", + "CMT_TOP_LOGIC_OUTS_L_B20_13", + "CMT_TOP_IMUX34_0", + "CMT_TOP_SE4C0_9", + "CMT_TOP_NE2A1_6", + "CMT_TOP_NE4BEG3_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT42", + "CMT_TOP_LOGIC_OUTS_L_B7_12", + "CMT_TOP_IMUX2_9", + "CMT_TOP_IMUX0_8", + "CMT_TOP_IMUX31_6", + "CMT_TOP_IMUX36_10", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_TOP_WW4END3_7", + "CMT_TOP_WL1END0_9", + "CMT_TOP_LOGIC_OUTS_L_B2_13", + "CMT_LR_LOWER_B_MMCM_TESTOUT37", + "CMT_TOP_EE4A0_15", + "CMT_TOP_SW4A0_1", + "CMT_TOP_WW2END1_13", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE2A2_1", + "CMT_TOP_SW2A3_11", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_IMUX43_15", + "CMT_TOP_WW2END0_13", + "CMT_TOP_SW2A1_5", + "CMT_TOP_BLOCK_OUTS_L_B2_10", + "CMT_TOP_CTRL1_8", + "CMT_TOP_OCLK1X_90_9", + "CMT_TOP_NW4A2_5", + "CMT_TOP_NW4A0_0", + "CMT_TOP_WW2A1_10", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_IMUX41_1", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX11_7", + "CMT_TOP_IMUX1_12", + "CMT_TOP_NE4C3_14", + "CMT_TOP_NE4C2_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT38", + "CMT_TOP_IMUX14_3", + "CMT_TOP_IMUX17_1", + "CMT_TOP_WW4A2_4", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_ICLKDIV_10", + "CMT_TOP_IMUX4_1", + "CMT_TOP_IMUX23_1", + "CMT_TOP_NW4A0_3", + "CMT_TOP_NW2A1_13", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_TOP_EE2A0_2", + "CMT_TOP_IMUX19_14", + "CMT_TOP_IMUX17_9", + "CMT_TOP_LOGIC_OUTS_L_B21_11", + "CMT_TOP_WW4A3_12", + "CMT_TOP_LH11_13", + "CMT_TOP_WW4END3_3", + "CMT_TOP_SE4C2_14", + "CMT_TOP_LH2_6", + "CMT_TOP_WW4B1_9", + "CMT_TOP_WR1END2_11", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_LR_LOWER_B_MMCM_PSEN", + "CMT_TOP_IMUX32_11", + "CMT_TOP_BYP2_8", + "CMT_TOP_WW4A0_0", + "CMT_TOP_WR1END3_5", + "CMT_TOP_SE4BEG1_3", + "CMT_TOP_IMUX5_13", + "CMT_TOP_WW4A1_13", + "CMT_TOP_WW4A2_13", + "CMT_MMCM_PHASERA_DQSBUS1", + "CMT_TOP_WW4END3_2", + "CMT_TOP_EE2BEG3_13", + "CMT_TOP_WL1END3_3", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_IMUX34_8", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_CTRL0_7", + "CMT_TOP_IMUX43_9", + "CMT_TOP_WW2END1_12", + "CMT_TOP_IMUX13_1", + "CMT_TOP_IMUX11_1", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_SE2A2_3", + "CMT_TOP_NE2A3_4", + "CMT_TOP_OCLKDIV_11", + "CMT_TOP_EE4C2_6", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_SW2A0_5", + "CMT_TOP_SW2A3_10", + "CMT_TOP_LH7_9", + "CMT_TOP_CTRL1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_TOP_IMUX24_12", + "CMT_TOP_LH8_5", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_EE4BEG3_13", + "CMT_TOP_WR1END0_13", + "CMT_TOP_EE2BEG0_13", + "CMT_TOP_WL1END3_6", + "CMT_TOP_LH1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_14", + "CMT_TOP_IMUX4_7", + "CMT_TOP_WW4END2_10", + "CMT_TOP_IMUX24_4", + "CMT_TOP_BYP7_9", + "CMT_TOP_LOGIC_OUTS_L_B8_13", + "CMT_TOP_SE4BEG2_12", + "CMT_TOP_FAN2_9", + "CMT_TOP_IMUX6_14", + "CMT_TOP_LOGIC_OUTS_L_B15_11", + "CMT_TOP_WW4A1_9", + "CMT_TOP_IMUX29_13", + "CMT_TOP_EE2BEG0_15", + "CMT_TOP_EE4C2_11", + "CMT_TOP_IMUX19_1", + "CMT_TOP_LOGIC_OUTS_L_B23_10", + "CMT_TOP_FAN2_8", + "CMT_TOP_NW2A1_9", + "CMT_TOP_EE4A3_14", + "CMT_TOP_LOGIC_OUTS_L_B8_11", + "CMT_TOP_EL1BEG0_15", + "CMT_TOP_IMUX3_15", + "CMT_TOP_SE4C2_7", + "CMT_TOP_LH5_9", + "CMT_TOP_LOGIC_OUTS_L_B14_15", + "CMT_TOP_IMUX0_14", + "CMT_TOP_BYP6_14", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH7_2", + "CMT_TOP_IMUX41_14", + "CMT_TOP_IMUX13_6", + "CMT_TOP_NW2A1_15", + "CMT_TOP_IMUX32_13", + "CMT_TOP_IMUX1_1", + "CMT_TOP_IMUX4_11", + "CMT_TOP_LH3_8", + "CMT_TOP_LOGIC_OUTS_L_B5_12", + "CMT_TOP_EE4C3_3", + "CMT_TOP_SW4A0_0", + "CMT_TOP_SW2A1_8", + "CMT_TOP_IMUX5_9", + "CMT_TOP_IMUX46_0", + "CMT_TOP_IMUX6_13", + "CMT_TOP_IMUX3_0", + "CMT_TOP_IMUX17_12", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_TOP_SE4C2_15", + "CMT_TOP_EE4C2_0", + "CMT_TOP_IMUX16_1", + "CMT_TOP_SW4END2_5", + "CMT_TOP_IMUX16_0", + "CMT_TOP_SE4C0_13", + "CMT_TOP_EE2A1_0", + "CMT_TOP_NW4END0_4", + "CMT_TOP_IMUX12_7", + "CMT_TOP_FAN3_14", + "CMT_TOP_NW4A0_9", + "CMT_TOP_ER1BEG0_14", + "CMT_TOP_WR1END1_3", + "CMT_TOP_IMUX42_9", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_IMUX47_5", + "CMT_LR_LOWER_B_MMCM_TESTOUT40", + "CMT_TOP_IMUX31_2", + "CMT_TOP_LOGIC_OUTS_L_B10_13", + "CMT_TOP_WR1END0_9", + "CMT_TOP_IMUX17_5", + "CMT_TOP_WW4END3_11", + "CMT_TOP_CLK1_3", + "CMT_TOP_WR1END1_14", + "CMT_TOP_ICLKDIV_11", + "CMT_TOP_SE2A1_9", + "CMT_TOP_EE2A3_2", + "CMT_TOP_LH12_9", + "CMT_LR_LOWER_B_MMCM_CLKOUT6", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_SE4C0_11", + "CMT_TOP_SE4C1_10", + "CMT_TOP_SE4C3_8", + "CMT_TOP_EE4BEG0_12", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_IMUX8_15", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_TOP_WW4B1_14", + "CMT_TOP_FAN6_13", + "CMT_TOP_IMUX43_11", + "CMT_TOP_IMUX39_1", + "CMT_TOP_LH1_3", + "CMT_TOP_BYP5_7", + "CMT_TOP_IMUX6_11", + "CMT_TOP_IMUX47_8", + "CMT_TOP_IMUX36_0", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_NW4A2_2", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_IMUX26_9", + "CMT_TOP_IMUX46_10", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END1_6", + "CMT_TOP_SW4A2_15", + "CMT_TOP_WL1END1_8", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_LOGIC_OUTS_L_B18_15", + "CMT_TOP_WW2END1_6", + "CMT_TOP_WW4END0_6", + "CMT_TOP_SE2A2_6", + "CMT_TOP_EE2BEG2_13", + "CMT_TOP_WW4A3_11", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_FAN5_0", + "CMT_L_LOWER_B_CLK_IN3_HCLK", + "CMT_TOP_WW2END0_14", + "CMT_TOP_LOGIC_OUTS_L_B3_11", + "CMT_TOP_WW4END3_13", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_IMUX7_2", + "CMT_TOP_SW4A3_11", + "CMT_TOP_SE2A3_10", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_FAN4_12", + "CMT_TOP_LH2_0", + "CMT_TOP_SE2A0_6", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LH9_2", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_EE4A2_13", + "CMT_TOP_EL1BEG0_14", + "CMT_TOP_WW4END1_13", + "CMT_LR_LOWER_B_MMCM_DO12", + "CMT_TOP_LOGIC_OUTS_L_B4_9", + "CMT_TOP_WW2A3_1", + "CMT_TOP_LH5_3", + "CMT_TOP_NE2A0_6", + "CMT_TOP_FAN4_1", + "CMT_TOP_WR1END2_15", + "CMT_TOP_IMUX24_15", + "CMT_TOP_LH12_1", + "CMT_TOP_LH8_6", + "CMT_TOP_IMUX36_5", + "CMT_TOP_OCLK_6", + "CMT_TOP_SW4END1_5", + "CMT_TOP_IMUX47_15", + "CMT_TOP_LOGIC_OUTS_L_B1_9", + "CMT_TOP_NW4END0_12", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_LR_LOWER_B_MMCM_DADDR4", + "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", + "CMT_TOP_FAN6_6", + "CMT_TOP_NE2A2_7", + "CMT_TOP_SW4A3_13", + "CMT_TOP_LH7_6", + "CMT_TOP_WW4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX45_3", + "CMT_TOP_IMUX16_12", + "CMT_TOP_NE4BEG1_10", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_WR1END1_10", + "CMT_TOP_LOGIC_OUTS_L_B16_10", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_SW2A0_3", + "CMT_TOP_NE4C1_12", + "CMT_TOP_EE4C0_7", + "CMT_TOP_NW2A0_11", + "CMT_TOP_IMUX12_12", + "CMT_TOP_NW4END1_6", + "CMT_TOP_BYP7_13", + "CMT_TOP_IMUX34_11", + "CMT_TOP_IMUX38_4", + "CMT_TOP_FAN6_7", + "CMT_TOP_EE4BEG1_11", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_IMUX41_5", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_SW4END2_3", + "CMT_TOP_NW2A3_13", + "CMT_TOP_LH5_13", + "CMT_TOP_EE2BEG3_8", + "CMT_TOP_LH9_7", + "CMT_TOP_IMUX4_12", + "CMT_TOP_WW4A1_1", + "CMT_TOP_WR1END0_3", + "CMT_TOP_WL1END3_14", + "CMT_TOP_FAN2_7", + "CMT_TOP_LH1_6", + "CMT_TOP_BYP7_6", + "CMT_TOP_LOGIC_OUTS_L_B2_14", + "CMT_TOP_IMUX40_11", + "CMT_TOP_NW4A1_5", + "CMT_TOP_IMUX18_14", + "CMT_TOP_CTRL0_13", + "CMT_TOP_IMUX8_13", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_1", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_IMUX2_10", + "CMT_TOP_IMUX32_10", + "CMT_MMCM_PHASERREF1", + "CMT_TOP_FAN6_8", + "CMT_TOP_EE4BEG1_10", + "CMT_TOP_IMUX39_12", + "CMT_TOP_NE2A1_13", + "CMT_TOP_NW4A2_4", + "CMT_TOP_WW4C2_4", + "CMT_TOP_LOGIC_OUTS_L_B11_9", + "CMT_TOP_LH6_5", + "CMT_TOP_FAN5_7", + "CMT_TOP_BYP2_12", + "CMT_TOP_OCLK_2", + "CMT_LR_LOWER_B_MMCM_TESTOUT20", + "CMT_TOP_WL1END1_6", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_BYP6_0", + "CMT_LR_LOWER_B_MMCM_CLKOUT1B", + "CMT_TOP_WL1END3_9", + "CMT_TOP_EE2BEG2_6", + "CMT_TOP_WW4B3_15", + "CMT_TOP_WW2END3_9", + "CMT_TOP_IMUX25_9", + "CMT_TOP_NW4END1_7", + "CMT_TOP_EE2A1_4", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_IMUX33_6", + "CMT_TOP_LH2_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT34", + "CMT_TOP_NW4A2_6", + "CMT_TOP_EE2BEG3_15", + "CMT_TOP_NE4C1_6", + "CMT_TOP_IMUX8_9", + "CMT_TOP_SW2A1_12", + "CMT_TOP_NE2A0_3", + "CMT_TOP_SE4C3_7", + "CMT_TOP_IMUX34_10", + "CMT_TOP_LOGIC_OUTS_L_B5_13", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_IMUX31_1", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_WW4C3_7", + "CMT_TOP_ICLKDIV_15", + "CMT_TOP_IMUX32_9", + "CMT_TOP_IMUX8_4", + "CMT_TOP_WW2END2_13", + "CMT_TOP_WR1END1_13", + "CMT_TOP_NW2A2_10", + "CMT_LR_LOWER_B_MMCM_DI9", + "CMT_TOP_IMUX33_1", + "CMT_TOP_IMUX32_12", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_BYP0_12", + "CMT_TOP_WW4END1_3", + "CMT_TOP_FAN1_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT41", + "CMT_TOP_SW2A0_1", + "CMT_TOP_FAN5_14", + "CMT_TOP_IMUX37_14", + "CMT_TOP_IMUX33_8", + "CMT_TOP_NW4A1_3", + "CMT_TOP_LH10_0", + "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "CMT_TOP_LH5_6", + "CMT_TOP_WW4B2_1", + "CMT_TOP_EE4C1_15", + "CMT_TOP_IMUX7_5", + "CMT_TOP_EE4C2_1", + "CMT_TOP_NE2A3_9", + "CMT_TOP_ER1BEG2_5", + "CMT_TOP_NW2A3_11", + "CMT_TOP_SW4A2_12", + "CMT_TOP_EE4BEG1_5", + "CMT_TOP_EE4BEG2_15", + "CMT_TOP_EE2A1_3", + "CMT_TOP_EE4C2_4", + "CMT_TOP_WW4C1_14", + "CMT_LR_LOWER_B_MMCM_CLKOUT0B", + "CMT_TOP_SW4A2_3", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_NE4C3_7", + "CMT_TOP_IMUX12_2", + "CMT_TOP_WW4B1_8", + "CMT_TOP_SE2A1_11", + "CMT_TOP_NW4A2_12", + "CMT_TOP_LH6_12", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_IMUX3_9", + "CMT_L_LOWER_B_CLK_MMCM0", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_LR_LOWER_B_MMCM_TMUXOUT", + "CMT_TOP_IMUX21_3", + "CMT_TOP_LH4_11", + "CMT_TOP_EE4A2_3", + "CMT_TOP_LH1_11", + "CMT_TOP_SW4A2_6", + "CMT_TOP_IMUX35_8", + "CMT_TOP_IMUX9_0", + "CMT_TOP_SW4END0_11", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_WW2A3_12", + "CMT_TOP_NW4END2_15", + "CMT_TOP_IMUX16_4", + "CMT_TOP_IMUX39_11", + "CMT_TOP_LH2_4", + "CMT_TOP_LOGIC_OUTS_L_B14_9", + "CMT_TOP_WW4C0_2", + "CMT_TOP_LOGIC_OUTS_L_B3_13", + "CMT_TOP_CTRL1_11", + "CMT_TOP_EE4B2_11", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_EE2A0_12", + "CMT_TOP_LH3_6", + "CMT_TOP_LH7_15", + "CMT_TOP_WW4A0_12", + "CMT_TOP_EE4C3_0", + "CMT_LR_LOWER_B_MMCM_TESTIN22", + "CMT_TOP_IMUX40_1", + "CMT_TOP_CLK0_10", + "CMT_TOP_EE4B0_10", + "CMT_TOP_WW4C2_13", + "CMT_TOP_MONITOR_P_13", + "CMT_MMCM_PHYCTRL_SYNC_BB_DN", + "CMT_TOP_WW4C3_11", + "CMT_TOP_IMUX20_11", + "CMT_TOP_FAN7_9", + "CMT_TOP_IMUX29_15", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_ER1BEG0_12", + "CMT_TOP_IMUX32_2", + "CMT_TOP_LH1_4", + "CMT_TOP_IMUX14_14", + "CMT_TOP_BYP1_11", + "CMT_TOP_BYP0_1", + "CMT_TOP_FAN3_10", + "CMT_TOP_NE4C0_6", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_IMUX24_1", + "CMT_TOP_IMUX12_1", + "CMT_LR_LOWER_B_MMCM_TESTOUT13", + "CMT_TOP_IMUX29_3", + "CMT_TOP_IMUX18_0", + "CMT_TOP_SW2A0_6", + "CMT_TOP_FAN7_6", + "CMT_TOP_LOGIC_OUTS_L_B21_10", + "CMT_TOP_IMUX24_11", + "CMT_TOP_LH1_15", + "CMT_TOP_EE4A0_3", + "CMT_TOP_NE4C3_12", + "CMT_TOP_SW2A3_6", + "CMT_TOP_IMUX10_10", + "CMT_TOP_WW4B1_15", + "CMT_TOP_BLOCK_OUTS_L_B2_11", + "CMT_TOP_NE4C1_15", + "CMT_TOP_IMUX44_11", + "CMT_LR_LOWER_B_MMCM_TESTIN1", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_BLOCK_OUTS_L_B0_13", + "CMT_TOP_NW2A0_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT28", + "CMT_TOP_WR1END2_5", + "CMT_TOP_ER1BEG3_12", + "CMT_TOP_BYP5_3", + "CMT_TOP_NW4END2_14", + "CMT_TOP_NW4A2_1", + "CMT_TOP_FAN5_6", + "CMT_TOP_IMUX32_4", + "CMT_TOP_LH6_11", + "CMT_TOP_LOGIC_OUTS_L_B16_12", + "CMT_TOP_LOGIC_OUTS_L_B3_12", + "CMT_TOP_SE4BEG3_9", + "CMT_TOP_LOGIC_OUTS_L_B17_13", + "CMT_TOP_EE4C3_1", + "CMT_TOP_CTRL0_3", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_TOP_LH5_11", + "CMT_TOP_SE4BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_SW4END1_7", + "CMT_TOP_NW4A3_10", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_LR_LOWER_B_MMCM_DI14", + "CMT_TOP_WW2END3_14", + "CMT_TOP_ER1BEG2_7", + "CMT_L_LOWER_B_CLK_MMCM12", + "CMT_TOP_IMUX6_5", + "CMT_TOP_WW4A3_5", + "CMT_TOP_NE2A2_13", + "CMT_TOP_IMUX42_15", + "CMT_TOP_NE4BEG2_7", + "CMT_MMCM_PHASERREF_ABOVE0", + "CMT_TOP_LOGIC_OUTS_L_B18_13", + "CMT_TOP_EE4A1_12", + "CMT_TOP_BYP3_9", + "CMT_TOP_IMUX26_2", + "CMT_TOP_SW2A1_13", + "CMT_TOP_IMUX20_10", + "CMT_TOP_IMUX13_4", + "CMT_LR_LOWER_B_MMCM_PSINCDEC", + "CMT_TOP_IMUX4_15", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_NW4END2_12", + "CMT_TOP_WW4C3_8", + "CMT_TOP_NE2A0_8", + "CMT_TOP_LH6_4", + "CMT_TOP_NW2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B10_15", + "CMT_TOP_IMUX20_9", + "CMT_TOP_WW2END3_6", + "CMT_TOP_FAN6_10", + "CMT_TOP_EE4B2_9", + "CMT_TOP_WW4B1_1", + "CMT_TOP_WW4B1_7", + "CMT_L_LOWER_B_CLK_MMCM9", + "CMT_TOP_WW2A3_4", + "CMT_TOP_NW4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_IMUX9_11", + "CMT_TOP_BYP7_3", + "CMT_TOP_SW4A2_14", + "CMT_TOP_IMUX25_0", + "CMT_TOP_NE4C2_8", + "CMT_TOP_IMUX41_0", + "CMT_TOP_WL1END2_9", + "CMT_TOP_FAN0_14", + "CMT_TOP_LH4_4", + "CMT_TOP_WW4B3_12", + "CMT_TOP_IMUX24_3", + "CMT_LR_LOWER_B_MMCM_DO10", + "CMT_TOP_IMUX14_13", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_LOGIC_OUTS_L_B14_12", + "CMT_TOP_BLOCK_OUTS_L_B1_13", + "CMT_TOP_EE4C3_12", + "CMT_TOP_LOGIC_OUTS_L_B17_14", + "CMT_TOP_NE4BEG2_14", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_NW2A0_4", + "CMT_TOP_EE2A1_2", + "CMT_TOP_WW4C3_14", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX46_3", + "CMT_TOP_WW2END3_11", + "CMT_TOP_CLK1_11", + "CMT_TOP_LOGIC_OUTS_L_B13_15", + "CMT_TOP_EE4A2_0", + "CMT_TOP_SE2A2_4", + "CMT_TOP_IMUX29_11", + "CMT_TOP_EE4A0_7", + "CMT_TOP_WW4C2_3", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_IMUX32_3", + "CMT_TOP_BLOCK_OUTS_L_B2_14", + "CMT_TOP_EE2A0_11", + "CMT_LR_LOWER_B_MMCM_TESTIN31", + "CMT_TOP_IMUX11_8", + "CMT_TOP_ER1BEG2_10", + "CMT_TOP_IMUX27_5", + "CMT_TOP_IMUX36_8", + "CMT_TOP_NW2A1_10", + "CMT_TOP_WL1END1_0", + "CMT_TOP_NW4A1_13", + "CMT_TOP_LH10_12", + "CMT_TOP_IMUX47_3", + "CMT_TOP_IMUX0_2", + "CMT_TOP_SE4BEG1_15", + "CMT_TOP_NW4END3_11", + "CMT_TOP_WW2A1_6", + "CMT_TOP_SW4A2_1", + "CMT_TOP_NW2A2_2", + "CMT_TOP_NW2A0_10", + "CMT_TOP_IMUX5_5", + "CMT_TOP_LOGIC_OUTS_L_B0_13", + "CMT_TOP_BLOCK_OUTS_L_B0_15", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4BEG1_4", + "CMT_TOP_WW4END3_9", + "CMT_TOP_SW4A1_12", + "CMT_LR_LOWER_B_MMCM_DI13", + "CMT_TOP_SE2A1_13", + "CMT_TOP_MONITOR_P_2", + "CMT_TOP_IMUX30_11", + "CMT_TOP_WW2A2_14", + "CMT_LR_LOWER_B_MMCM_PSDONE", + "CMT_TOP_LOGIC_OUTS_L_B15_14", + "CMT_TOP_WW4C3_1", + "CMT_TOP_IMUX33_5", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SE4C2_3", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_EE4A0_9", + "CMT_TOP_LH7_7", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_BYP6_10", + "CMT_TOP_NW4END3_1", + "CMT_L_LOWER_B_CLK_PERF2", + "CMT_TOP_IMUX13_15", + "CMT_TOP_EE4C0_14", + "CMT_TOP_EE2BEG3_10", + "CMT_TOP_WW2END0_5", + "CMT_TOP_LH5_1", + "CMT_TOP_FAN3_12", + "CMT_TOP_LH8_7", + "CMT_TOP_OCLK_11", + "CMT_TOP_FAN6_5", + "CMT_TOP_IMUX22_15", + "CMT_TOP_IMUX27_1", + "CMT_TOP_NE4BEG2_1", + "CMT_TOP_WW2END1_15", + "CMT_TOP_SW4END0_13", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_SE2A2_8", + "CMT_TOP_SE4C3_10", + "CMT_TOP_WL1END2_5", + "CMT_TOP_IMUX15_12", + "CMT_TOP_WW2A2_9", + "CMT_TOP_SE2A3_9", + "CMT_TOP_SE2A2_14", + "CMT_TOP_IMUX14_8", + "CMT_TOP_FAN2_15", + "CMT_TOP_NW4END3_4", + "CMT_TOP_SW4END0_14", + "CMT_TOP_NE2A2_3", + "CMT_TOP_LH8_2", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_EE4A2_10", + "CMT_TOP_IMUX19_10", + "CMT_LR_LOWER_B_MMCM_PSCLK", + "CMT_TOP_LOGIC_OUTS_L_B16_13", + "CMT_TOP_FAN4_13", + "CMT_TOP_LOGIC_OUTS_L_B19_12", + "CMT_TOP_WR1END3_12", + "CMT_TOP_EE4BEG2_11", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_WW2END0_10", + "CMT_PHASER_A_ICLKDIV_TOIOI", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_SE2A3_2", + "CMT_TOP_ER1BEG3_10", + "CMT_TOP_CLK1_8", + "CMT_TOP_IMUX47_12", + "CMT_TOP_LOGIC_OUTS_L_B15_12", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_EL1BEG2_11", + "CMT_TOP_LH2_14", + "CMT_TOP_NW4A0_1", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_NW4END2_1", + "CMT_TOP_EE4B0_8", + "CMT_TOP_IMUX0_15", + "CMT_TOP_NW4END2_8", + "CMT_TOP_CLK0_6", + "CMT_TOP_WR1END2_6", + "CMT_TOP_WW4END0_1", + "CMT_TOP_FAN4_15", + "CMT_TOP_NW2A1_7", + "CMT_TOP_WW4A2_6", + "CMT_TOP_IMUX27_3", + "CMT_TOP_SW2A3_0", + "CMT_TOP_EE2A2_9", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_EE4A1_13", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_WR1END2_2", + "CMT_TOP_EE4BEG2_9", + "CMT_TOP_WW4END1_15", + "CMT_TOP_EE2A2_7", + "CMT_TOP_EE4B2_13", + "CMT_TOP_IMUX26_10", + "CMT_TOP_IMUX8_0", + "CMT_TOP_IMUX21_9", + "CMT_TOP_WW4C1_1", + "CMT_TOP_EE4A0_12", + "CMT_TOP_IMUX2_14", + "CMT_TOP_LOGIC_OUTS_L_B11_13", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_LH5_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4C2_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT8", + "CMT_TOP_BLOCK_OUTS_L_B2_12", + "CMT_TOP_SW4END1_14", + "CMT_TOP_EE2A2_11", + "CMT_TOP_WR1END0_8", + "CMT_TOP_WW4C0_10", + "CMT_TOP_WL1END1_4", + "CMT_L_LOWER_B_CLK_IN1_INT", + "CMT_TOP_WW4B1_6", + "CMT_TOP_EE4B3_14", + "CMT_LR_LOWER_B_MMCM_DO9", + "CMT_TOP_NW4A0_14", + "CMT_MMCM_PHASER_IN_A_ICLK", + "CMT_LR_LOWER_B_MMCM_CLKOUT2B", + "CMT_TOP_WW2A3_7", + "CMT_TOP_CTRL1_13", + "CMT_TOP_IMUX31_13", + "CMT_TOP_BYP3_6", + "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", + "CMT_TOP_EE4B1_8", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_IMUX9_1", + "CMT_LR_LOWER_B_MMCM_TESTOUT53", + "CMT_LR_LOWER_B_MMCM_TESTIN3", + "CMT_TOP_SE4C1_5", + "CMT_TOP_LH4_7", + "CMT_TOP_LOGIC_OUTS_L_B5_10", + "CMT_TOP_IMUX20_5", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_NE4C2_4", + "CMT_TOP_NE4BEG2_12", + "CMT_TOP_EE2A1_15", + "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "CMT_TOP_WW4B1_0", + "CMT_TOP_IMUX0_10", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_IMUX23_7", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_LR_LOWER_B_MMCM_TESTOUT0", + "CMT_TOP_SE4C1_12", + "CMT_TOP_EE4A2_7", + "CMT_TOP_FAN3_9", + "CMT_TOP_EE2A0_8", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_WW2A2_13", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_NW4END0_8", + "CMT_TOP_WW4B2_3", + "CMT_TOP_IMUX23_0", + "CMT_TOP_EE2BEG3_1", + "CMT_TOP_LH6_8", + "CMT_TOP_SW4END0_10", + "CMT_TOP_WW4A3_14", + "CMT_TOP_LH6_10", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_WL1END0_0", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_FAN0_2", + "CMT_TOP_EE2A1_14", + "CMT_TOP_LOGIC_OUTS_L_B10_10", + "CMT_TOP_LH2_11", + "CMT_TOP_WW2END2_0", + "CMT_TOP_IMUX18_3", + "CMT_TOP_IMUX6_10", + "CMT_L_LOWER_B_CLK_FREQ_BB1", + "CMT_TOP_BLOCK_OUTS_L_B0_12", + "CMT_TOP_FAN1_1", + "CMT_TOP_BLOCK_OUTS_L_B3_13", + "CMT_TOP_NW2A3_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT24", + "CMT_TOP_LH7_1", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_IMUX43_5", + "CMT_TOP_SE4BEG1_10", + "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", + "CMT_TOP_EE4B1_10", + "CMT_TOP_IMUX7_13", + "CMT_TOP_IMUX41_4", + "CMT_TOP_ER1BEG0_13", + "CMT_LR_LOWER_B_MMCM_TESTIN11", + "CMT_TOP_SE4C0_15", + "CMT_TOP_IMUX33_0", + "CMT_TOP_LOGIC_OUTS_L_B14_13", + "CMT_TOP_IMUX35_15", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_EE4B3_15", + "CMT_TOP_SE2A3_8", + "CMT_TOP_WW4C0_13", + "CMT_TOP_LOGIC_OUTS_L_B4_13", + "CMT_TOP_NE2A1_15", + "CMT_TOP_SE4C0_0", + "CMT_PHASER_A_OCLKDIV_TOIOI", + "CMT_TOP_BYP2_15", + "CMT_TOP_NE2A2_9", + "CMT_TOP_OCLKDIV_2", + "CMT_TOP_WW4C2_12", + "CMT_TOP_WW4B3_4", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX5_3", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_WW2A1_15", + "CMT_TOP_BYP2_9", + "CMT_TOP_IMUX23_10", + "CMT_TOP_LH5_0", + "CMT_TOP_WW2END2_15", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_IMUX42_10", + "CMT_TOP_LH10_10", + "CMT_TOP_WW4END2_11", + "CMT_TOP_EE4A1_4", + "CMT_TOP_NW4A1_10", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX11_0", + "CMT_TOP_CTRL0_15", + "CMT_TOP_WW2END3_5", + "CMT_TOP_LH7_8", + "CMT_TOP_LOGIC_OUTS_L_B9_14", + "CMT_LR_LOWER_B_MMCM_TESTIN10", + "CMT_TOP_NE4C1_3", + "CMT_TOP_CTRL1_6", + "CMT_TOP_WW4C2_11", + "CMT_TOP_CLK1_9", + "CMT_TOP_BYP3_13", + "CMT_TOP_IMUX31_3", + "CMT_TOP_IMUX37_3", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_LOGIC_OUTS_L_B18_11", + "CMT_TOP_LH7_13", + "CMT_TOP_WW4C0_0", + "CMT_TOP_WW4A0_5", + "CMT_TOP_LH9_12", + "CMT_TOP_EE4C3_9", + "CMT_TOP_IMUX3_8", + "CMT_TOP_NW4END1_11", + "CMT_TOP_WW2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B9_10", + "CMT_TOP_SE2A0_4", + "CMT_TOP_IMUX15_1", + "CMT_TOP_IMUX6_3", + "CMT_TOP_IMUX45_9", + "CMT_TOP_EE4B2_7", + "CMT_TOP_NW2A2_9", + "CMT_TOP_LH3_11", + "CMT_TOP_WR1END0_7", + "CMT_TOP_IMUX24_5", + "CMT_TOP_IMUX14_15", + "CMT_TOP_FAN2_1", + "CMT_TOP_LOGIC_OUTS_L_B2_15", + "CMT_TOP_IMUX5_6", + "CMT_TOP_NW4END0_10", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_NW4END1_9", + "CMT_TOP_SE4BEG0_9", + "CMT_TOP_SE4C0_14", + "CMT_TOP_WW4B2_15", + "CMT_TOP_BYP6_5", + "CMT_TOP_ER1BEG3_5", + "CMT_TOP_IMUX37_5", + "CMT_TOP_IMUX37_8", + "CMT_TOP_EE4C0_0", + "CMT_TOP_WW4END2_1", + "CMT_TOP_ICLK_13", + "CMT_TOP_IMUX9_14", + "CMT_TOP_EE4A1_6", + "CMT_TOP_LOGIC_OUTS_L_B12_10", + "CMT_TOP_SW4END1_0", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_IMUX35_3", + "CMT_TOP_SE4BEG0_12", + "CMT_TOP_WW4A2_3", + "CMT_TOP_IMUX10_4", + "CMT_TOP_LOGIC_OUTS_L_B13_9", + "CMT_TOP_BYP6_9", + "CMT_TOP_WW4END2_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT56", + "CMT_TOP_IMUX26_6", + "CMT_TOP_EE4A3_0", + "CMT_TOP_IMUX18_10", + "CMT_TOP_LOGIC_OUTS_L_B17_15", + "CMT_TOP_IMUX22_10", + "CMT_TOP_EE2A1_5", + "CMT_TOP_SW4END3_1", + "CMT_TOP_EL1BEG1_6", + "CMT_TOP_IMUX4_4", + "CMT_TOP_LOGIC_OUTS_L_B11_12", + "CMT_TOP_IMUX3_14", + "CMT_TOP_NW4END3_3", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_WW4C1_2", + "CMT_TOP_EE2A1_12", + "CMT_TOP_SW4A2_9", + "CMT_TOP_EL1BEG2_12", + "CMT_TOP_IMUX22_0", + "CMT_TOP_LOGIC_OUTS_L_B16_11", + "CMT_TOP_SE2A1_1", + "CMT_TOP_WL1END1_12", + "CMT_TOP_NW2A3_9", + "CMT_TOP_WR1END0_4", + "CMT_TOP_EE2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B18_14", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_WW4A1_10", + "CMT_TOP_EE4C0_6", + "CMT_TOP_IMUX24_0", + "CMT_TOP_EL1BEG1_4", + "CMT_TOP_ER1BEG3_14", + "CMT_TOP_LOGIC_OUTS_L_B6_12", + "CMT_TOP_WW4B3_10", + "CMT_LR_LOWER_B_MMCM_DEN", + "CMT_TOP_LOGIC_OUTS_L_B3_14", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_SW2A3_3", + "CMT_TOP_SW4END0_1", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_EE4B1_0", + "CMT_TOP_NE2A3_2", + "CMT_TOP_ER1BEG1_9", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_TOP_WW4C0_15", + "CMT_TOP_ICLK_12", + "CMT_TOP_EE4B1_6", + "CMT_TOP_LH3_9", + "CMT_TOP_BYP3_2", + "CMT_LR_LOWER_B_CLKFBOUT2IN", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_LH5_12", + "CMT_TOP_LOGIC_OUTS_L_B10_14", + "CMT_LR_LOWER_B_MMCM_DI7", + "CMT_TOP_SE4BEG1_9", + "CMT_TOP_IMUX34_9", + "CMT_TOP_CLK0_2", + "CMT_TOP_SE4C1_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT58", + "CMT_TOP_LH10_1", + "CMT_TOP_IMUX22_12", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_SE4BEG3_11", + "CMT_TOP_LOGIC_OUTS_L_B21_15", + "CMT_TOP_LOGIC_OUTS_L_B10_11", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_FAN3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_TOP_WW4A0_9", + "CMT_TOP_SW2A1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_EE4BEG1_15", + "CMT_LR_LOWER_B_MMCM_DI5", + "CMT_TOP_IMUX3_4", + "CMT_TOP_ICLK_5", + "CMT_TOP_IMUX47_9", + "CMT_TOP_IMUX15_9", + "CMT_TOP_LH12_12", + "CMT_TOP_IMUX31_0", + "CMT_TOP_LH4_14", + "CMT_TOP_IMUX29_8", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_LH2_3", + "CMT_TOP_WR1END1_9", + "CMT_TOP_IMUX28_10", + "CMT_TOP_NE4C1_4", + "CMT_TOP_WW2END3_15", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_IMUX2_4", + "CMT_TOP_IMUX38_11", + "CMT_TOP_EE4C1_1", + "CMT_TOP_SW2A0_4", + "CMT_LR_LOWER_B_MMCM_TESTIN26", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_LH8_4", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_WW4END2_0", + "CMT_TOP_EE4C0_1", + "CMT_TOP_IMUX33_11", + "CMT_TOP_FAN5_8", + "CMT_TOP_WW4C1_0", + "CMT_TOP_LOGIC_OUTS_L_B11_11", + "CMT_TOP_EE2A3_9", + "CMT_TOP_WW4B0_15", + "CMT_TOP_LH10_7", + "CMT_TOP_IMUX37_13", + "CMT_TOP_SE4C0_1", + "CMT_TOP_NW4END3_9", + "CMT_TOP_WW4C1_7", + "CMT_TOP_SE2A0_5", + "CMT_TOP_EE2BEG1_9", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_WW2A3_13", + "CMT_LR_LOWER_B_MMCM_CLKIN1", + "CMT_TOP_ER1BEG3_9", + "CMT_TOP_CLK1_15", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_IMUX47_11", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LH10_14", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_NW4END0_15", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_WR1END2_14", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BYP0_0", + "CMT_TOP_EE4B2_2", + "CMT_TOP_FAN7_7", + "CMT_TOP_NW4END2_13", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_WW4A0_4", + "CMT_TOP_EE4B3_13", + "CMT_TOP_WW4B0_12", + "CMT_TOP_IMUX4_13", + "CMT_TOP_WW4A3_0", + "CMT_TOP_SE4C1_1", + "CMT_TOP_ER1BEG0_6", + "CMT_TOP_IMUX46_1", + "CMT_TOP_FAN6_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT35", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_IMUX30_8", + "CMT_TOP_SW2A1_0", + "CMT_TOP_CLK0_1", + "CMT_TOP_BYP5_4", + "CMT_TOP_IMUX45_2", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_WW4C2_6", + "CMT_TOP_IMUX19_5", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_SE2A1_15", + "CMT_TOP_NW4END0_1", + "CMT_TOP_IMUX35_12", + "CMT_TOP_LH3_10", + "CMT_TOP_LH9_8", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_TOP_LH12_14", + "CMT_TOP_NW2A2_7", + "CMT_TOP_MONITOR_N_15", + "CMT_TOP_LH11_12", + "CMT_TOP_SW4END0_5", + "CMT_TOP_IMUX29_1", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_IMUX9_5", + "CMT_TOP_SW4A0_2", + "CMT_TOP_WW2END1_5", + "CMT_TOP_WW2A2_8", + "CMT_TOP_WW4A1_12", + "CMT_TOP_OCLK_8", + "CMT_TOP_CLK1_14", + "CMT_TOP_IMUX46_7", + "CMT_TOP_EE4C1_12", + "CMT_TOP_IMUX44_15", + "CMT_LR_LOWER_B_MMCM_DI3", + "CMT_TOP_IMUX8_3", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_IMUX14_7", + "CMT_TOP_NE4BEG2_13", + "CMT_TOP_NW2A2_0", + "CMT_TOP_SE4C0_5", + "CMT_TOP_SW4END3_4", + "CMT_TOP_SE2A2_7", + "CMT_TOP_SW2A1_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_IMUX22_8", + "CMT_TOP_IMUX9_13", + "CMT_TOP_LH3_7", + "CMT_TOP_IMUX30_15", + "CMT_TOP_IMUX1_11", + "CMT_TOP_EE4BEG2_13", + "CMT_TOP_SE2A1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_9", + "CMT_TOP_IMUX43_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT57", + "CMT_TOP_LH10_5", + "CMT_TOP_EE4C0_13", + "CMT_TOP_NE4BEG2_5", + "CMT_TOP_BYP3_15", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_BLOCK_OUTS_L_B3_10", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_NE2A0_0", + "CMT_TOP_NE2A2_6", + "CMT_TOP_SW2A3_12", + "CMT_TOP_NE2A1_12", + "CMT_TOP_NE4C1_14", + "CMT_TOP_WW4C2_9", + "CMT_TOP_SW2A2_2", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_LH11_1", + "CMT_TOP_EE2A1_11", + "CMT_TOP_BLOCK_OUTS_L_B2_13", + "CMT_TOP_IMUX40_13", + "CMT_MMCM_A_RDCLK_TOFIFO", + "CMT_TOP_EE4C3_14", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_LOGIC_OUTS_L_B20_10", + "CMT_TOP_WW2A2_4", + "CMT_TOP_EE4C1_10", + "CMT_TOP_LH5_2", + "CMT_TOP_IMUX17_8", + "CMT_TOP_IMUX41_15", + "CMT_TOP_EE4BEG1_12", + "CMT_TOP_EE2BEG1_13", + "CMT_TOP_IMUX46_15", + "CMT_TOP_IMUX36_7", + "CMT_TOP_FAN0_13", + "CMT_TOP_SW4END3_13", + "CMT_TOP_BYP1_7", + "CMT_TOP_IMUX4_5", + "CMT_TOP_IMUX36_12", + "CMT_LR_LOWER_B_MMCM_DI11", + "CMT_TOP_EE4C0_4", + "CMT_TOP_IMUX26_15", + "CMT_TOP_EE2BEG2_14", + "CMT_TOP_EL1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B13_10", + "CMT_TOP_LOGIC_OUTS_L_B19_10", + "CMT_TOP_ICLK_7", + "CMT_TOP_SE4C3_15", + "CMT_TOP_NE4BEG0_10", + "CMT_TOP_LH11_3", + "CMT_TOP_SE4BEG0_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT45", + "CMT_TOP_IMUX32_1", + "CMT_TOP_SW2A2_4", + "CMT_TOP_IMUX11_4", + "CMT_TOP_IMUX9_10", + "CMT_TOP_EE4C3_7", + "CMT_L_LOWER_B_CLK_FREQ_BB3", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_WW4B3_0", + "CMT_TOP_ER1BEG2_15", + "CMT_TOP_IMUX10_5", + "CMT_TOP_EE4A1_14", + "CMT_TOP_WW2END1_1", + "CMT_TOP_FAN0_9", + "CMT_TOP_FAN1_7", + "CMT_TOP_IMUX23_2", + "CMT_TOP_IMUX5_0", + "CMT_TOP_ICLK_6", + "CMT_TOP_NW4A3_14", + "CMT_TOP_EE4A2_9", + "CMT_TOP_IMUX22_1", + "CMT_TOP_WW4B0_8", + "CMT_TOP_SW4A0_15", + "CMT_TOP_IMUX42_11", + "CMT_TOP_EE4B1_13", + "CMT_TOP_BYP2_14", + "CMT_TOP_OCLKDIV_6", + "CMT_TOP_SE4BEG3_14", + "CMT_TOP_LH2_9", + "CMT_TOP_NW4A3_1", + "CMT_TOP_IMUX27_0", + "CMT_TOP_SW2A2_14", + "CMT_TOP_SE4C2_8", + "CMT_LR_LOWER_B_MMCM_TESTIN25", + "CMT_TOP_WW2END0_9", + "CMT_TOP_SE4C2_4", + "CMT_TOP_SW2A2_15", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_EE2BEG3_12", + "CMT_TOP_SE2A2_1", + "CMT_TOP_NW4END1_5", + "CMT_TOP_EE2BEG0_7", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_NW4END0_14", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_WW2A0_12", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX14_10", + "CMT_TOP_WR1END0_12", + "CMT_TOP_IMUX42_7", + "CMT_TOP_IMUX32_14", + "CMT_TOP_EL1BEG0_9", + "CMT_TOP_LOGIC_OUTS_L_B22_15", + "CMT_TOP_IMUX41_11", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_IMUX33_15", + "CMT_TOP_IMUX34_12", + "CMT_TOP_WR1END1_11", + "CMT_TOP_IMUX35_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT60", + "CMT_TOP_SW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_WW4C1_13", + "CMT_TOP_FAN3_7", + "CMT_TOP_LH9_9", + "CMT_TOP_SW4A1_1", + "CMT_LR_LOWER_B_MMCM_TESTIN19", + "CMT_TOP_IMUX13_14", + "CMT_MMCM_PHASER_OUT_B_OCLK", + "CMT_TOP_SW2A0_8", + "CMT_TOP_IMUX28_9", + "CMT_TOP_EE4B3_7", + "CMT_TOP_WW2A3_11", + "CMT_TOP_IMUX44_3", + "CMT_TOP_IMUX31_10", + "CMT_LR_LOWER_B_MMCM_TESTIN15", + "CMT_TOP_EE4B3_10", + "CMT_TOP_WW2END2_12", + "CMT_TOP_NE4C1_9", + "CMT_TOP_SE2A0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_BYP2_3", + "CMT_TOP_IMUX12_10", + "CMT_TOP_IMUX40_3", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_LOGIC_OUTS_L_B22_14", + "CMT_TOP_IMUX11_6", + "CMT_L_LOWER_B_CLK_MMCM1", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_IMUX39_10", + "CMT_TOP_LH3_13", + "CMT_TOP_BYP4_2", + "MMCM_CLK_FREQ_BB_REBUF0_NS", + "CMT_TOP_NW2A1_14", + "CMT_TOP_NE4BEG0_12", + "CMT_TOP_NE4BEG3_8", + "CMT_TOP_IMUX1_10", + "CMT_TOP_SE4BEG3_15", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_SW2A1_9", + "CMT_TOP_FAN6_15", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_IMUX26_7", + "CMT_TOP_IMUX1_7", + "CMT_TOP_IMUX23_6", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_FAN5_10", + "CMT_TOP_IMUX6_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT15", + "CMT_TOP_IMUX4_3", + "CMT_TOP_EE2A3_13", + "CMT_TOP_EE4C1_6", + "CMT_TOP_NW4END3_7", + "CMT_TOP_WW2END3_12", + "CMT_TOP_IMUX13_5", + "CMT_TOP_LOGIC_OUTS_L_B7_13", + "CMT_TOP_IMUX46_6", + "CMT_TOP_WW4END0_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LH12_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_CLK1_2", + "CMT_TOP_WW4C2_10", + "CMT_TOP_LOGIC_OUTS_L_B18_10", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_IMUX15_7", + "CMT_TOP_SW4END2_0", + "CMT_TOP_WW4B0_9", + "CMT_TOP_WW4END1_5", + "CMT_TOP_NW4A0_5", + "CMT_TOP_SW2A3_15", + "CMT_TOP_EE2A2_2", + "CMT_TOP_WW4A0_2", + "CMT_TOP_IMUX37_6", + "CMT_TOP_WL1END1_11", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_LH10_11", + "CMT_L_LOWER_B_CLK_FREQ_BB0", + "CMT_TOP_BYP5_13", + "CMT_TOP_IMUX0_0", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_NW2A3_4", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_EE2BEG1_15", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_IMUX42_6", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_BLOCK_OUTS_L_B3_15", + "CMT_TOP_LH3_1", + "CMT_TOP_EE2BEG3_11", + "CMT_TOP_WL1END3_11", + "CMT_TOP_ICLKDIV_14", + "CMT_LR_LOWER_B_MMCM_DADDR2", + "CMT_TOP_EE4C0_2", + "CMT_TOP_IMUX23_9", + "CMT_TOP_IMUX35_6", + "CMT_TOP_EL1BEG3_13", + "CMT_LR_LOWER_B_MMCM_TESTIN6", + "CMT_TOP_SE2A3_11", + "CMT_TOP_FAN3_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT48", + "CMT_TOP_SW4END2_1", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_EE4A2_11", + "CMT_TOP_LOGIC_OUTS_L_B17_9", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_TOP_IMUX36_13", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_WW2A1_3", + "CMT_TOP_FAN2_5", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_LH4_13", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_TOP_WW2END1_8", + "CMT_TOP_WR1END2_0", + "CMT_TOP_NE2A1_0", + "CMT_TOP_BLOCK_OUTS_L_B3_12", + "CMT_TOP_LH1_8", + "CMT_TOP_LH11_14", + "CMT_TOP_WW2A0_7", + "CMT_TOP_FAN7_12", + "CMT_TOP_LOGIC_OUTS_L_B17_10", + "CMT_TOP_EE4BEG1_4", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_EE2BEG2_8", + "CMT_TOP_LOGIC_OUTS_L_B16_15", + "CMT_LR_LOWER_B_MMCM_DRDY", + "CMT_TOP_SW4END0_2", + "CMT_TOP_SW4A0_6", + "CMT_TOP_BYP5_8", + "CMT_TOP_FAN5_4", + "CMT_TOP_IMUX41_7", + "CMT_TOP_IMUX25_2", + "CMT_TOP_EE4A3_1", + "CMT_TOP_WR1END3_14", + "CMT_TOP_IMUX12_8", + "CMT_TOP_WW2A3_3", + "CMT_TOP_IMUX27_14", + "CMT_TOP_IMUX1_6", + "CMT_TOP_IMUX21_2", + "CMT_TOP_IMUX25_14", + "CMT_TOP_WW2A1_14", + "CMT_TOP_CLK1_1", + "CMT_TOP_IMUX27_12", + "CMT_TOP_WW4A2_0", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_TOP_WW4END3_10", + "CMT_TOP_IMUX16_9", + "CMT_TOP_FAN1_10", + "CMT_TOP_NE2A2_0", + "CMT_TOP_IMUX17_11", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_WW2END2_7", + "CMT_TOP_CTRL1_9", + "CMT_TOP_SE4BEG1_1", + "CMT_TOP_CTRL0_12", + "CMT_TOP_NW4END3_5", + "CMT_TOP_IMUX21_5", + "CMT_TOP_WW4END3_4", + "CMT_LR_LOWER_B_MMCM_TESTIN30", + "CMT_TOP_LH10_13", + "CMT_TOP_EE2A1_13", + "CMT_TOP_WL1END0_8", + "CMT_TOP_SE2A3_0", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_WW2END1_9", + "CMT_TOP_NW4A3_6", + "CMT_TOP_IMUX34_15", + "CMT_TOP_SE4C1_7", + "CMT_TOP_WL1END3_10", + "CMT_PHASER_A_OCLK90_TOIOI", + "CMT_TOP_LOGIC_OUTS_L_B9_11", + "CMT_TOP_NW2A3_12", + "CMT_TOP_BYP0_8", + "CMT_TOP_IMUX1_15", + "CMT_TOP_SW4END2_13", + "CMT_TOP_IMUX2_11", + "CMT_TOP_EE4A3_3", + "CMT_TOP_WR1END2_12", + "CMT_TOP_LH10_6", + "CMT_TOP_NW4A3_2", + "CMT_L_LOWER_B_CLK_FREQ_BB2", + "CMT_LR_LOWER_B_MMCM_TESTOUT54", + "CMT_TOP_WW4A2_14", + "CMT_TOP_MONITOR_P_14", + "CMT_TOP_NE4C0_11", + "CMT_TOP_SW2A0_13", + "CMT_TOP_LH3_4", + "CMT_TOP_LOGIC_OUTS_L_B12_13", + "CMT_TOP_LH8_0", + "CMT_TOP_IMUX24_6", + "CMT_MMCM_PHASER_OUT_A_OCLK", + "CMT_TOP_IMUX27_15", + "CMT_TOP_IMUX45_8", + "CMT_TOP_IMUX33_7", + "CMT_LR_LOWER_B_MMCM_TESTIN17", + "CMT_TOP_ER1BEG0_10", + "CMT_TOP_FAN0_10", + "CMT_TOP_IMUX28_7", + "CMT_TOP_LH8_9", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_TOP_WL1END1_9", + "CMT_TOP_EE4B0_5", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX15_10", + "CMT_TOP_CLK0_11", + "CMT_TOP_BYP4_13", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_IMUX3_10", + "CMT_TOP_IMUX17_0", + "CMT_TOP_BYP3_8", + "CMT_TOP_NE2A3_1", + "CMT_TOP_EE4C2_12", + "CMT_TOP_WL1END1_13", + "CMT_MMCM_PHASERA_DTSBUS0", + "CMT_TOP_NW2A3_2", + "CMT_TOP_EE4B3_1", + "CMT_TOP_WW4B3_5", + "CMT_TOP_BYP1_9", + "CMT_TOP_SE4C2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_SE2A1_7", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_SE4C3_12", + "CMT_TOP_CTRL1_12", + "CMT_TOP_WL1END3_5", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_IMUX3_1", + "CMT_TOP_WR1END2_1", + "CMT_TOP_NW4A1_4", + "CMT_TOP_WL1END2_11", + "CMT_TOP_IMUX19_15", + "CMT_TOP_WL1END1_10", + "CMT_TOP_IMUX20_3", + "CMT_TOP_BYP6_8", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX14_2", + "CMT_L_LOWER_B_CLK_MMCM10", + "CMT_TOP_BYP4_4", + "CMT_MMCM_PHASER_IN_A_ICLKDIV", + "CMT_TOP_CLK1_7", + "CMT_TOP_IMUX2_3", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_IMUX46_5", + "CMT_TOP_NW4END1_3", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_IMUX45_11", + "CMT_TOP_NW2A3_5", + "CMT_TOP_EL1BEG3_12", + "CMT_TOP_WR1END2_3", + "CMT_TOP_BYP2_6", + "CMT_TOP_BYP3_3", + "CMT_TOP_FAN6_2", + "CMT_TOP_NW2A2_3", + "CMT_TOP_SW4END2_12", + "CMT_TOP_IMUX40_4", + "CMT_TOP_MONITOR_P_11", + "CMT_TOP_WW4A0_10", + "CMT_TOP_IMUX47_6", + "CMT_TOP_SW4A3_4", + "CMT_TOP_FAN7_0", + "CMT_TOP_WW4A0_11", + "CMT_TOP_LH11_5", + "CMT_TOP_IMUX30_5", + "CMT_TOP_SE2A3_1", + "CMT_TOP_EE4A3_6", + "CMT_TOP_IMUX5_1", + "CMT_TOP_EE4BEG3_6", + "CMT_TOP_SE2A2_0", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_BYP1_15", + "CMT_TOP_LOGIC_OUTS_L_B1_14", + "CMT_TOP_EE4B3_4", + "CMT_TOP_EE4C3_6", + "CMT_TOP_EE4C0_11", + "CMT_TOP_CLK0_14", + "CMT_TOP_WW4B0_0", + "CMT_TOP_IMUX27_2", + "CMT_TOP_FAN0_8", + "CMT_MMCM_PHASERREF_BELOW0", + "CMT_TOP_EE4A2_6", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_FAN2_6", + "CMT_TOP_SE4BEG0_8", + "CMT_TOP_LH5_15", + "CMT_TOP_WW2A1_13", + "CMT_TOP_CLK0_9", + "CMT_TOP_LH1_10", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_FAN7_14", + "CMT_TOP_SW2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_9", + "CMT_TOP_LOGIC_OUTS_L_B23_12", + "CMT_TOP_OCLK_12", + "CMT_TOP_IMUX46_11", + "CMT_TOP_SW2A1_14", + "CMT_TOP_IMUX3_11", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_NW4END0_6", + "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "CMT_TOP_IMUX16_14", + "CMT_TOP_IMUX10_0", + "CMT_TOP_IMUX43_4", + "CMT_TOP_EE4A0_0", + "CMT_TOP_IMUX36_1", + "CMT_TOP_LH1_0", + "CMT_TOP_WW4A3_6", + "CMT_TOP_LOGIC_OUTS_L_B15_13", + "CMT_TOP_EE2A1_9", + "CMT_TOP_LOGIC_OUTS_L_B20_14", + "CMT_TOP_IMUX0_12", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_LOGIC_OUTS_L_B4_11", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_TOP_WW4A3_2", + "CMT_TOP_WW4B2_9", + "CMT_TOP_EE4C0_12", + "CMT_TOP_BYP0_5", + "CMT_TOP_IMUX10_12", + "CMT_TOP_ICLK_2", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_FAN0_11", + "CMT_TOP_NE2A3_5", + "CMT_TOP_EL1BEG3_10", + "CMT_LR_LOWER_B_MMCM_DI12", + "CMT_TOP_NE2A1_8", + "CMT_TOP_NW4END3_15", + "CMT_TOP_LH12_2", + "CMT_TOP_WW2A0_10", + "CMT_TOP_EE4C2_5", + "CMT_TOP_IMUX44_14", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_IMUX47_10", + "CMT_TOP_IMUX30_9", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_LOGIC_OUTS_L_B19_15", + "CMT_TOP_IMUX19_8", + "CMT_LR_LOWER_B_MMCM_DADDR5", + "CMT_TOP_WW2A2_6", + "CMT_TOP_IMUX17_6", + "CMT_TOP_IMUX14_5", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_TOP_IMUX34_2", + "CMT_TOP_BYP1_6", + "CMT_TOP_LOGIC_OUTS_L_B6_14", + "CMT_TOP_SW4A2_2", + "CMT_TOP_SE4C1_15", + "CMT_TOP_EE2BEG2_10", + "CMT_TOP_LOGIC_OUTS_L_B0_15", + "CMT_TOP_WW4A2_8", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_IMUX39_5", + "CMT_TOP_NW4A2_7", + "CMT_TOP_IMUX38_1", + "CMT_TOP_WW2A0_8", + "CMT_TOP_ER1BEG1_12", + "CMT_TOP_CTRL1_4", + "CMT_TOP_NW2A1_12", + "CMT_TOP_SE2A0_11", + "CMT_TOP_IMUX15_14", + "CMT_TOP_CTRL0_10", + "CMT_TOP_NE4C2_0", + "CMT_TOP_FAN2_12", + "CMT_TOP_IMUX8_1", + "CMT_TOP_OCLK_0", + "CMT_TOP_NE4C2_7", + "CMT_TOP_SW4END1_13", + "CMT_TOP_IMUX20_8", + "CMT_TOP_LOGIC_OUTS_L_B23_13", + "CMT_LR_LOWER_B_MMCM_TESTOUT33", + "CMT_TOP_IMUX46_14", + "CMT_TOP_SE2A3_12", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SE4C3_4", + "CMT_TOP_SE4C3_3", + "CMT_TOP_IMUX12_3", + "CMT_TOP_IMUX19_12", + "CMT_TOP_CLK0_5", + "CMT_TOP_WW2END1_4", + "CMT_L_LOWER_B_CLK_MMCM7", + "CMT_TOP_NW2A1_5", + "CMT_TOP_IMUX16_2", + "CMT_TOP_MONITOR_N_10", + "CMT_TOP_BYP2_5", + "CMT_LR_LOWER_B_MMCM_TESTOUT30", + "CMT_TOP_WR1END3_11", + "CMT_TOP_IMUX40_2", + "CMT_TOP_WW4B2_8", + "CMT_TOP_EE4B1_2", + "CMT_TOP_SE4C1_2", + "CMT_TOP_SE4BEG1_13", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_WW4B3_13", + "CMT_TOP_SW4A1_9", + "CMT_TOP_FAN0_6", + "CMT_TOP_SW4END2_8", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_EE4A1_15", + "CMT_TOP_SE4BEG3_2", + "CMT_TOP_WL1END0_14", + "CMT_TOP_NW4A1_11", + "CMT_TOP_IMUX18_7", + "CMT_TOP_LH7_14", + "CMT_TOP_EL1BEG1_14", + "CMT_TOP_EE2BEG1_8", + "CMT_TOP_SW4A1_14", + "CMT_TOP_NE2A2_10", + "CMT_TOP_EE2BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B21_12", + "CMT_TOP_BYP0_15", + "CMT_LR_LOWER_B_MMCM_TESTIN29", + "CMT_TOP_BYP4_14", + "CMT_TOP_WW4A2_5", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX44_2", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_CTRL0_0", + "CMT_TOP_IMUX1_8", + "CMT_TOP_IMUX38_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_IMUX5_12", + "CMT_TOP_NW2A1_0", + "CMT_TOP_LOGIC_OUTS_L_B19_14", + "CMT_TOP_WW4B3_8", + "CMT_TOP_EE4BEG2_10", + "CMT_TOP_LH2_15", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_NW4A0_15", + "CMT_TOP_LOGIC_OUTS_L_B4_12", + "CMT_TOP_WW4B1_13", + "CMT_TOP_FAN7_13", + "CMT_LR_LOWER_B_MMCM_TESTIN16", + "CMT_TOP_WW4C0_14", + "CMT_TOP_IMUX38_0", + "CMT_TOP_EE4BEG3_15", + "CMT_TOP_IMUX36_14", + "CMT_TOP_SW2A2_1", + "CMT_TOP_EE4C1_13", + "CMT_TOP_NE4C2_9", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_TOP_SE4BEG1_11", + "CMT_TOP_NW2A3_14", + "CMT_TOP_BYP1_3", + "CMT_TOP_CTRL0_6", + "CMT_TOP_EE4A3_10", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_IMUX17_3", + "CMT_TOP_NW2A3_10", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX28_2", + "CMT_TOP_IMUX43_12", + "CMT_TOP_EE2A0_9", + "CMT_TOP_IMUX21_8", + "CMT_TOP_BLOCK_OUTS_L_B1_15", + "CMT_TOP_IMUX31_15", + "CMT_TOP_EE4B0_15", + "CMT_TOP_EL1BEG3_11", + "CMT_TOP_BYP7_14", + "CMT_TOP_IMUX42_2", + "CMT_TOP_WW2A3_6", + "CMT_TOP_WW4B0_4", + "CMT_TOP_WW2END1_14", + "CMT_TOP_SE2A2_5", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_TOP_IMUX38_9", + "CMT_TOP_BYP2_10", + "CMT_TOP_LOGIC_OUTS_L_B12_14", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EL1BEG0_10", + "CMT_TOP_EE4B1_11", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_EE2BEG2_7", + "CMT_TOP_ICLK_0", + "CMT_TOP_NW4END1_2", + "CMT_TOP_WW2A2_10", + "CMT_TOP_WW4END1_9", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX31_7", + "CMT_LR_LOWER_B_MMCM_TESTIN21", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_NW2A1_3", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX47_2", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_NE2A3_0", + "CMT_TOP_IMUX13_9", + "CMT_TOP_LH10_4", + "CMT_TOP_BYP0_2", + "CMT_TOP_CLK0_3", + "CMT_TOP_EE4B3_12", + "CMT_TOP_NE4C0_14", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_SW4A0_11", + "CMT_TOP_LOGIC_OUTS_L_B13_11", + "CMT_TOP_SW2A2_7", + "CMT_TOP_EL1BEG2_10", + "CMT_TOP_NE2A1_14", + "CMT_TOP_IMUX29_9", + "CMT_L_LOWER_B_CLK_MMCM5", + "CMT_LR_LOWER_B_MMCM_TESTIN9", + "CMT_TOP_EE4B3_9", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_NE4C3_13", + "CMT_TOP_IMUX25_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_SE4BEG1_12", + "CMT_TOP_EE2A2_13", + "CMT_TOP_IMUX8_14", + "CMT_TOP_ICLK_10", + "CMT_TOP_NE4C1_7", + "CMT_TOP_NW2A2_11", + "CMT_TOP_EE4C3_8", + "CMT_TOP_ICLKDIV_12", + "CMT_TOP_IMUX4_2", + "CMT_TOP_NW4END0_0", + "CMT_TOP_IMUX47_13", + "CMT_TOP_IMUX11_9", + "CMT_TOP_EE4B2_10", + "CMT_TOP_IMUX0_6", + "CMT_TOP_WW4B0_1", + "CMT_TOP_FAN1_5", + "CMT_TOP_WL1END0_11", + "CMT_TOP_EE2A1_8", + "CMT_TOP_NE4C3_10", + "CMT_TOP_NE4C0_13", + "CMT_TOP_IMUX38_13", + "CMT_TOP_OCLK_10", + "CMT_TOP_IMUX7_14", + "CMT_TOP_WW2END2_2", + "CMT_TOP_SE2A3_13", + "CMT_TOP_EE2BEG3_14", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_IMUX17_13", + "CMT_TOP_FAN4_7", + "CMT_TOP_IMUX27_11", + "CMT_TOP_IMUX36_6", + "CMT_TOP_WW2END0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_EE4BEG3_11", + "CMT_TOP_NW4END1_15", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_EE4B3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_IMUX42_13", + "CMT_TOP_NW4A0_10", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_LH8_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_WW2END0_15", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_NE4C0_12", + "CMT_TOP_MONITOR_P_10", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_NE4C0_9", + "CMT_TOP_SW4A3_8", + "CMT_TOP_IMUX39_14", + "CMT_TOP_SW2A1_10", + "CMT_TOP_WW2A0_6", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_LH7_12", + "CMT_TOP_WL1END2_1", + "CMT_TOP_LH8_10", + "CMT_TOP_NE4C0_0", + "CMT_TOP_IMUX29_7", + "CMT_TOP_EE4B0_4", + "CMT_TOP_WR1END3_6", + "CMT_TOP_LOGIC_OUTS_L_B6_11", + "CMT_TOP_LH9_14", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_TOP_IMUX1_13", + "CMT_TOP_BLOCK_OUTS_L_B3_9", + "CMT_TOP_WW4B2_2", + "CMT_PHASER_A_OCLK_TOIOI", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_LH11_4", + "CMT_TOP_LH6_6", + "CMT_TOP_LOGIC_OUTS_L_B1_12", + "MMCM_CLK_FREQ_BB_REBUF2_NS", + "CMT_TOP_NE2A1_11", + "CMT_TOP_EE4BEG1_14", + "CMT_TOP_NW2A3_7", + "CMT_TOP_WW4END0_5", + "CMT_TOP_FAN4_8", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_EE4BEG0_14", + "CMT_TOP_IMUX22_7", + "CMT_TOP_IMUX8_12", + "CMT_TOP_WR1END1_2", + "CMT_TOP_IMUX2_6", + "CMT_TOP_LOGIC_OUTS_L_B12_9", + "CMT_TOP_BYP4_8", + "CMT_TOP_IMUX25_13", + "CMT_TOP_IMUX33_13", + "CMT_TOP_SE4C3_5", + "CMT_TOP_BLOCK_OUTS_L_B2_9", + "CMT_TOP_SE4C1_13", + "CMT_TOP_FAN5_12", + "CMT_L_LOWER_B_CLK_MMCM2", + "CMT_TOP_IMUX15_4", + "CMT_TOP_IMUX39_9", + "CMT_TOP_IMUX4_9", + "CMT_LR_LOWER_B_MMCM_DADDR6", + "CMT_LR_LOWER_B_MMCM_TESTIN12", + "CMT_TOP_IMUX22_13", + "CMT_TOP_BYP5_5", + "CMT_TOP_ICLK_1", + "CMT_TOP_BYP3_12", + "CMT_TOP_WW2END1_10", + "CMT_TOP_EE2A0_13", + "CMT_TOP_IMUX0_1", + "CMT_TOP_BYP6_7", + "CMT_TOP_CLK0_15", + "CMT_TOP_WW4B2_6", + "CMT_TOP_IMUX32_7", + "CMT_TOP_LH3_3", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_SW4A2_8", + "CMT_TOP_SE2A0_12", + "CMT_TOP_WL1END3_7", + "CMT_TOP_SW2A2_13", + "CMT_TOP_SW4A1_7", + "CMT_TOP_NE2A3_13", + "CMT_TOP_LH12_15", + "CMT_TOP_SW2A3_5", + "CMT_TOP_EE4C2_9", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_WW4END1_8", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_LH5_14", + "CMT_TOP_SW4A3_3", + "CMT_TOP_FAN1_9", + "CMT_LR_LOWER_B_MMCM_DI8", + "CMT_TOP_WW4A2_2", + "CMT_TOP_IMUX28_1", + "CMT_TOP_IMUX46_4", + "CMT_TOP_WW2END3_4", + "CMT_TOP_NW4END0_13", + "CMT_TOP_EE4B1_5", + "CMT_TOP_NE4C2_15", + "CMT_TOP_NW4A0_13", + "CMT_TOP_WR1END0_11", + "CMT_TOP_EE4B0_6", + "CMT_TOP_SW2A0_0", + "CMT_TOP_LH3_12", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_NW4A1_0", + "CMT_L_LOWER_B_CLK_MMCM13", + "CMT_TOP_WR1END2_13", + "CMT_TOP_WW2END0_12", + "CMT_TOP_WW4B0_7", + "CMT_TOP_IMUX33_9", + "CMT_TOP_NW4END2_6", + "CMT_TOP_CLK1_4", + "CMT_TOP_IMUX13_12", + "CMT_TOP_IMUX17_10", + "CMT_LR_LOWER_B_MMCM_TESTIN18", + "CMT_TOP_IMUX37_15", + "CMT_TOP_BYP5_0", + "CMT_TOP_MONITOR_N_12", + "CMT_TOP_BYP5_14", + "CMT_TOP_NE4C1_8", + "CMT_TOP_WW4END1_1", + "CMT_TOP_NW4A2_11", + "CMT_TOP_IMUX37_0", + "CMT_TOP_SW2A0_12", + "CMT_TOP_WL1END3_1", + "CMT_TOP_IMUX16_8", + "CMT_TOP_IMUX39_2", + "CMT_TOP_IMUX37_7", + "CMT_TOP_IMUX16_3", + "CMT_MMCM_PHASERA_DQSBUS0", + "CMT_TOP_IMUX1_2", + "CMT_TOP_SE4C2_13", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_TOP_IMUX6_6", + "CMT_TOP_LH1_12", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_WW4B2_4", + "CMT_TOP_ER1BEG2_2", + "CMT_TOP_IMUX20_13", + "CMT_LR_LOWER_B_MMCM_DADDR1", + "CMT_TOP_IMUX11_10", + "CMT_TOP_IMUX17_7", + "CMT_TOP_OCLK_13", + "CMT_TOP_NW2A0_15", + "CMT_TOP_CTRL0_8", + "CMT_TOP_IMUX35_9", + "CMT_LR_LOWER_B_MMCM_PWRDWN", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_IMUX29_2", + "CMT_TOP_BYP6_1", + "CMT_TOP_ER1BEG0_9", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_FAN1_4", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW2A0_5", + "CMT_TOP_NE2A1_3", + "CMT_TOP_IMUX28_15", + "CMT_LR_LOWER_B_MMCM_DI0", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_LR_LOWER_B_MMCM_TESTOUT27", + "CMT_TOP_NW2A0_3", + "CMT_TOP_IMUX5_15", + "CMT_L_LOWER_B_CLK_PERF3", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_SE2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_LH4_9", + "CMT_TOP_NW4A1_8", + "CMT_TOP_NE4BEG0_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT5", + "CMT_TOP_NW4END3_2", + "CMT_TOP_IMUX39_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_IMUX7_12", + "CMT_TOP_SW4END1_10", + "CMT_TOP_NW4END0_7", + "CMT_TOP_WW2A0_14", + "CMT_TOP_IMUX44_9", + "CMT_TOP_EE4A0_13", + "CMT_TOP_SW4END0_4", + "CMT_TOP_CTRL1_2", + "CMT_TOP_WW4END2_2", + "CMT_TOP_EE4B1_14", + "CMT_TOP_IMUX38_10", + "CMT_TOP_EE4B2_14", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4C2_10", + "CMT_TOP_EE4B0_14", + "CMT_TOP_BYP3_7", + "CMT_TOP_IMUX38_2", + "CMT_TOP_LH3_0", + "CMT_TOP_EE4BEG3_9", + "CMT_TOP_EE4C1_14", + "CMT_TOP_EE4A2_12", + "CMT_TOP_NE4BEG2_6", + "CMT_MMCM_PHASER_IN_B_ICLK", + "CMT_TOP_WW4A3_15", + "CMT_TOP_ICLK_11", + "CMT_TOP_OCLK_3", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX13_11", + "CMT_TOP_NE2A2_15", + "CMT_TOP_LOGIC_OUTS_L_B7_15", + "CMT_TOP_ER1BEG0_15", + "CMT_TOP_WW2A0_13", + "CMT_TOP_IMUX11_2", + "CMT_TOP_WW4A2_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT18", + "CMT_TOP_SW4A0_5", + "CMT_TOP_EE4B2_3", + "CMT_TOP_IMUX9_7", + "CMT_TOP_EE2A2_3", + "CMT_TOP_WR1END3_1", + "CMT_TOP_WW2A0_0", + "CMT_TOP_WR1END0_5", + "CMT_TOP_ER1BEG2_8", + "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "CMT_TOP_NE4BEG1_14", + "CMT_TOP_WW4C3_10", + "CMT_TOP_IMUX21_14", + "CMT_TOP_NW4A0_8", + "CMT_TOP_BYP7_12", + "CMT_TOP_LOGIC_OUTS_L_B6_9", + "CMT_TOP_EE4C0_10", + "CMT_TOP_WW4B2_5", + "CMT_TOP_SW2A2_12", + "CMT_TOP_IMUX41_8", + "CMT_TOP_SW2A3_8", + "CMT_TOP_WW4END3_14", + "CMT_TOP_SW4END1_9", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_IMUX5_14", + "CMT_TOP_LH4_10", + "CMT_TOP_NE4BEG0_11", + "CMT_TOP_WW4B3_6", + "CMT_TOP_NW4END3_10", + "CMT_TOP_WW4END3_8", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_LOGIC_OUTS_L_B8_15", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX33_2", + "CMT_TOP_LOGIC_OUTS_L_B9_15", + "CMT_TOP_WW2END2_8", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_NE4BEG0_15", + "CMT_TOP_WW4C0_11", + "CMT_TOP_NE2A0_7", + "CMT_TOP_LOGIC_OUTS_L_B7_14", + "CMT_TOP_SE2A0_10", + "CMT_LR_LOWER_B_MMCM_DO13", + "CMT_LR_LOWER_B_MMCM_DO11", + "CMT_TOP_NW2A0_12", + "CMT_TOP_BYP0_7", + "CMT_TOP_NE2A2_14", + "CMT_TOP_IMUX0_11", + "CMT_TOP_EE4B0_13", + "CMT_TOP_IMUX21_12", + "CMT_TOP_NE2A1_7", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_TOP_IMUX3_12", + "CMT_LR_LOWER_B_MMCM_TESTOUT11", + "CMT_TOP_WW2A3_10", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_NW4A3_8", + "CMT_TOP_NW4A3_13", + "CMT_TOP_EE4A1_11", + "CMT_TOP_WW4C0_5", + "CMT_TOP_BYP4_9", + "CMT_TOP_IMUX8_7", + "CMT_TOP_IMUX33_14", + "CMT_TOP_NE2A0_1", + "CMT_TOP_IMUX40_15", + "CMT_TOP_WW4END0_0", + "CMT_TOP_FAN5_2", + "CMT_TOP_CTRL0_14", + "CMT_TOP_BYP0_13", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_WW4C1_10", + "CMT_TOP_IMUX39_8", + "CMT_TOP_NE4C1_2", + "CMT_TOP_IMUX30_4", + "CMT_TOP_WL1END0_12", + "CMT_TOP_NE2A3_12", + "CMT_LR_LOWER_B_MMCM_TESTIN8", + "CMT_TOP_BYP1_5", + "CMT_TOP_EE4C3_4", + "CMT_TOP_IMUX20_12", + "CMT_TOP_IMUX10_8", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_TOP_IMUX34_13", + "CMT_TOP_WW4B2_12", + "CMT_TOP_NE4BEG3_14", + "CMT_TOP_NE2A2_11", + "CMT_TOP_EE4A3_11", + "CMT_TOP_IMUX43_10", + "CMT_TOP_EE2A2_10", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_EL1BEG1_15", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_IMUX43_14", + "CMT_TOP_IMUX44_8", + "CMT_TOP_WL1END0_3", + "CMT_TOP_IMUX19_4", + "CMT_TOP_IMUX18_8", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_NE4C2_10", + "CMT_TOP_WW2END2_14", + "CMT_TOP_NW4END3_12", + "CMT_TOP_LH10_9", + "CMT_LR_LOWER_B_MMCM_TESTOUT43", + "CMT_TOP_LOGIC_OUTS_L_B10_9", + "CMT_LR_LOWER_B_MMCM_TESTIN28", + "CMT_LR_LOWER_B_MMCM_TESTOUT6", + "CMT_TOP_LH7_4", + "CMT_LR_LOWER_B_MMCM_TESTIN5", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_LOGIC_OUTS_L_B9_13", + "CMT_TOP_NW4A3_5", + "CMT_LR_LOWER_B_MMCM_TESTOUT17", + "CMT_LR_LOWER_B_MMCM_DO2", + "CMT_TOP_LOGIC_OUTS_L_B9_12", + "CMT_TOP_NW4END0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_12", + "CMT_TOP_LOGIC_OUTS_L_B5_15", + "CMT_TOP_IMUX29_4", + "CMT_TOP_NW2A0_6", + "CMT_TOP_BLOCK_OUTS_L_B1_12", + "CMT_TOP_SE2A2_2", + "CMT_LR_LOWER_B_MMCM_DI4", + "CMT_TOP_WW4C2_7", + "CMT_LR_LOWER_B_MMCM_DI2", + "CMT_TOP_IMUX37_9", + "CMT_TOP_WW4C0_4", + "CMT_TOP_IMUX34_14", + "CMT_TOP_BYP5_9", + "CMT_TOP_EE4BEG3_4", + "CMT_TOP_WW4A2_1", + "CMT_TOP_LH6_9", + "CMT_TOP_BYP5_12", + "CMT_TOP_SE4C2_11", + "CMT_TOP_IMUX39_13", + "CMT_TOP_LH10_3", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_WW4C3_2", + "CMT_TOP_IMUX38_5", + "CMT_TOP_IMUX8_8", + "CMT_TOP_NE2A0_14", + "CMT_TOP_NW4END1_14", + "CMT_TOP_FAN4_6", + "CMT_TOP_IMUX47_7", + "CMT_TOP_EE2A1_1", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_ER1BEG1_10", + "CMT_TOP_FAN7_8", + "CMT_TOP_FAN6_3", + "CMT_TOP_EE4B0_0", + "CMT_TOP_WW4A1_14", + "CMT_TOP_SE4C1_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT21", + "CMT_TOP_IMUX34_5", + "CMT_TOP_IMUX31_5", + "CMT_TOP_NE2A3_14", + "CMT_TOP_WW4END1_11", + "CMT_TOP_LOGIC_OUTS_L_B1_13", + "CMT_TOP_IMUX0_7", + "CMT_TOP_IMUX2_1", + "CMT_TOP_ER1BEG3_8" + ], + "pips": { + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_12": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0B->>CMT_L_LOWER_B_CLK_MMCM1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS1->>CMT_L_LOWER_B_CLK_FREQ_BB2": { + "src_wire": "MMCM_CLK_FREQ_BB_NS1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2B->>CMT_L_LOWER_B_CLK_MMCM5": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_12": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DRDY", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_12": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX1_2->>CMT_LR_LOWER_B_MMCM_PSEN": { + "src_wire": "CMT_TOP_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PSEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX22_1->>CMT_LR_LOWER_B_MMCM_DWE": { + "src_wire": "CMT_TOP_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DWE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX1_1->>CMT_LR_LOWER_B_MMCM_DADDR1": { + "src_wire": "CMT_TOP_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO14->>CMT_TOP_LOGIC_OUTS_L_B7_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO14", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX3_0->>CMT_LR_LOWER_B_MMCM_DI6": { + "src_wire": "CMT_TOP_IMUX3_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_11": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_8": { + "src_wire": "CMT_MMCM_PHASERA_CTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO2->>CMT_TOP_LOGIC_OUTS_L_B0_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN2_INT->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "src_wire": "CMT_L_LOWER_B_CLK_IN2_INT", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF2_NS<<->>MMCM_CLK_FREQ_BB_NS2": { + "src_wire": "MMCM_CLK_FREQ_BB_REBUF2_NS", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS2", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_MMCM2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX4_0->>CMT_LR_LOWER_B_MMCM_DI8": { + "src_wire": "CMT_TOP_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLK->>CMT_PHASER_A_OCLK_TOIOI": { + "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF3_NS<<->>MMCM_CLK_FREQ_BB_NS3": { + "src_wire": "MMCM_CLK_FREQ_BB_REBUF3_NS", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS3", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3B->>CMT_L_LOWER_B_CLK_MMCM7": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO11->>CMT_TOP_LOGIC_OUTS_L_B20_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO15->>CMT_TOP_LOGIC_OUTS_L_B17_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO15", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_MMCM4": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO13->>CMT_TOP_LOGIC_OUTS_L_B21_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO13", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_MMCM6": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_12": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX34_2->>CMT_LR_LOWER_B_MMCM_RST": { + "src_wire": "CMT_TOP_IMUX34_2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_14": { + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX44_1->>CMT_LR_LOWER_B_MMCM_DADDR6": { + "src_wire": "CMT_TOP_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB3", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_PERF3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B18_1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_LOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLKDIV->>CMT_PHASER_A_OCLKDIV_TOIOI": { + "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>MMCMOUT_CLK_FREQ_BB_1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX35_0->>CMT_LR_LOWER_B_MMCM_DI7": { + "src_wire": "CMT_TOP_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_15": { + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_PERF2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_PERF2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX6_0->>CMT_LR_LOWER_B_MMCM_DI12": { + "src_wire": "CMT_TOP_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_8": { + "src_wire": "CMT_MMCM_PHASERA_DQSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3->>CMT_L_LOWER_B_CLK_FREQ_BB0": { + "src_wire": "MMCM_CLK_FREQ_BB_NS3", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_PERF1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUTB->>CMT_L_LOWER_B_CLK_MMCM12": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO0->>CMT_TOP_LOGIC_OUTS_L_B8_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B8_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX2_2->>CMT_LR_LOWER_B_MMCM_PSINCDEC": { + "src_wire": "CMT_TOP_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PSINCDEC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_PERF0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_CLK0_14->>CMT_L_LOWER_B_CLK_IN3_INT": { + "src_wire": "CMT_TOP_CLK0_14", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_IN3_INT", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_14": { + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_14": { + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_15": { + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX32_0->>CMT_LR_LOWER_B_MMCM_DI1": { + "src_wire": "CMT_TOP_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF1_NS<<->>MMCM_CLK_FREQ_BB_NS1": { + "src_wire": "MMCM_CLK_FREQ_BB_REBUF1_NS", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS1", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLK1X_90->>CMT_PHASER_A_OCLK90_TOIOI": { + "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_OCLK90_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2->>CMT_L_LOWER_B_CLK_FREQ_BB1": { + "src_wire": "MMCM_CLK_FREQ_BB_NS2", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX37_0->>CMT_LR_LOWER_B_MMCM_DI11": { + "src_wire": "CMT_TOP_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_PERF0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_15": { + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_9": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX0_2->>CMT_LR_LOWER_B_MMCM_CLKINSEL": { + "src_wire": "CMT_TOP_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKINSEL", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN1_HCLK->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "src_wire": "CMT_L_LOWER_B_CLK_IN1_HCLK", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1B->>CMT_L_LOWER_B_CLK_MMCM3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT6->>CMT_L_LOWER_B_CLK_MMCM10": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT6", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_8": { + "src_wire": "CMT_PHASER_A_OCLK90_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN2_HCLK->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "src_wire": "CMT_L_LOWER_B_CLK_IN2_HCLK", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>MMCMOUT_CLK_FREQ_BB_3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_PERF3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT5->>CMT_L_LOWER_B_CLK_MMCM9": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT5", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX34_1->>CMT_LR_LOWER_B_MMCM_DADDR3": { + "src_wire": "CMT_TOP_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_13": { + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_13": { + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS0->>CMT_L_LOWER_B_CLK_FREQ_BB3": { + "src_wire": "MMCM_CLK_FREQ_BB_NS0", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED->>CMT_TOP_LOGIC_OUTS_L_B18_2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_PERF1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO7->>CMT_TOP_LOGIC_OUTS_L_B19_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO7", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED->>CMT_TOP_LOGIC_OUTS_L_B16_2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO8->>CMT_TOP_LOGIC_OUTS_L_B10_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO8", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_CLK0_0->>CMT_LR_LOWER_B_MMCM_DCLK": { + "src_wire": "CMT_TOP_CLK0_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX47_1->>CMT_LR_LOWER_B_MMCM_PWRDWN": { + "src_wire": "CMT_TOP_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PWRDWN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO1->>CMT_TOP_LOGIC_OUTS_L_B18_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB3", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_15": { + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN1_INT->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "src_wire": "CMT_L_LOWER_B_CLK_IN1_INT", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_8": { + "src_wire": "CMT_MMCM_PHASERA_DQSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX35_1->>CMT_LR_LOWER_B_MMCM_DADDR5": { + "src_wire": "CMT_TOP_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { + "src_wire": "CMT_MMCM_PHASERA_DTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_LR_LOWER_B_CLKFBOUT2IN": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX5_0->>CMT_LR_LOWER_B_MMCM_DI10": { + "src_wire": "CMT_TOP_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSDONE->>CMT_TOP_LOGIC_OUTS_L_B21_1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_PSDONE", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_14": { + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "src_wire": "CMT_MMCM_PHASERA_DTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO12->>CMT_TOP_LOGIC_OUTS_L_B15_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_11": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_10": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN3_INT->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_L_LOWER_B_CLK_IN3_INT", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_8": { + "src_wire": "CMT_MMCM_PHASERA_CTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO3->>CMT_TOP_LOGIC_OUTS_L_B22_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B22_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_13": { + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_A_ICLK->>CMT_PHASER_A_ICLK_TOIOI": { + "src_wire": "CMT_MMCM_PHASER_IN_A_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT4->>CMT_L_LOWER_B_CLK_MMCM8": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT4", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX7_0->>CMT_LR_LOWER_B_MMCM_DI14": { + "src_wire": "CMT_TOP_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO5->>CMT_TOP_LOGIC_OUTS_L_B23_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF0_NS<<->>MMCM_CLK_FREQ_BB_NS0": { + "src_wire": "MMCM_CLK_FREQ_BB_REBUF0_NS", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS0", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX36_0->>CMT_LR_LOWER_B_MMCM_DI9": { + "src_wire": "CMT_TOP_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO6->>CMT_TOP_LOGIC_OUTS_L_B5_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO6", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX0_1->>CMT_LR_LOWER_B_MMCM_DADDR0": { + "src_wire": "CMT_TOP_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_9": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX33_0->>CMT_LR_LOWER_B_MMCM_DI3": { + "src_wire": "CMT_TOP_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX34_0->>CMT_LR_LOWER_B_MMCM_DI5": { + "src_wire": "CMT_TOP_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO10->>CMT_TOP_LOGIC_OUTS_L_B2_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO10", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX3_1->>CMT_LR_LOWER_B_MMCM_DADDR4": { + "src_wire": "CMT_TOP_IMUX3_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO9->>CMT_TOP_LOGIC_OUTS_L_B16_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO9", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX38_0->>CMT_LR_LOWER_B_MMCM_DI13": { + "src_wire": "CMT_TOP_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB3", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN3_HCLK->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_L_LOWER_B_CLK_IN3_HCLK", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>MMCMOUT_CLK_FREQ_BB_2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_A_ICLKDIV->>CMT_PHASER_A_ICLKDIV_TOIOI": { + "src_wire": "CMT_MMCM_PHASER_IN_A_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>MMCMOUT_CLK_FREQ_BB_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_TMUXOUT->>CMT_L_LOWER_B_CLK_MMCM13": { + "src_wire": "CMT_LR_LOWER_B_MMCM_TMUXOUT", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHYCTRL_SYNC_BB_DN<<->>CMT_MMCM_PHYCTRL_SYNC_BB_UP": { + "src_wire": "CMT_MMCM_PHYCTRL_SYNC_BB_DN", + "is_pseudo": "0", + "dst_wire": "CMT_MMCM_PHYCTRL_SYNC_BB_UP", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX2_1->>CMT_LR_LOWER_B_MMCM_DADDR2": { + "src_wire": "CMT_TOP_IMUX2_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_CLK1_15->>CMT_L_LOWER_B_CLK_IN2_INT": { + "src_wire": "CMT_TOP_CLK1_15", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_IN2_INT", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_CLK0_15->>CMT_L_LOWER_B_CLK_IN1_INT": { + "src_wire": "CMT_TOP_CLK0_15", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_IN1_INT", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX39_0->>CMT_LR_LOWER_B_MMCM_DI15": { + "src_wire": "CMT_TOP_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_CLK0_1->>CMT_LR_LOWER_B_MMCM_PSCLK": { + "src_wire": "CMT_TOP_CLK0_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX1_0->>CMT_LR_LOWER_B_MMCM_DI2": { + "src_wire": "CMT_TOP_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX15_1->>CMT_LR_LOWER_B_MMCM_DEN": { + "src_wire": "CMT_TOP_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO4->>CMT_TOP_LOGIC_OUTS_L_B13_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX0_0->>CMT_LR_LOWER_B_MMCM_DI0": { + "src_wire": "CMT_TOP_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_10": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_MMCM11": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX2_0->>CMT_LR_LOWER_B_MMCM_DI4": { + "src_wire": "CMT_TOP_IMUX2_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_13": { + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_MMCM0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CMT_TOP_L_LOWER_T.json b/kintex7/tile_type_CMT_TOP_L_LOWER_T.json new file mode 100644 index 0000000..e86ebab --- /dev/null +++ b/kintex7/tile_type_CMT_TOP_L_LOWER_T.json @@ -0,0 +1,4823 @@ +{ + "tile_type": "CMT_TOP_L_LOWER_T", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "PHASER_OUT_PHY", + "type": "PHASER_OUT_PHY", + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", + "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", + "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", + "RST": "CMT_PHASER_OUT_CA_RST", + "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", + "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", + "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", + "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", + "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", + "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", + "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", + "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", + "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", + "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", + "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", + "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", + "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", + "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", + "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", + "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", + "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", + "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", + "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", + "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", + "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", + "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", + "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", + "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", + "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", + "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", + "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", + "OCLK": "CMT_PHASER_OUT_CA_OCLK", + "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", + "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", + "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3", + "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", + "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", + "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", + "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "PHASER_IN_PHY", + "type": "PHASER_IN_PHY", + "site_pins": { + "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", + "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE", + "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", + "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", + "RST": "CMT_PHASER_IN_CA_RST", + "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", + "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", + "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", + "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_IN_CA_FINEINC", + "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", + "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", + "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", + "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", + "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", + "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", + "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", + "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", + "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", + "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", + "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", + "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", + "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", + "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", + "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", + "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", + "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", + "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", + "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", + "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", + "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "STG1READ": "CMT_PHASER_IN_CA_STG1READ", + "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", + "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", + "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", + "SCANENB": "CMT_PHASER_IN_CA_SCANENB", + "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", + "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", + "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", + "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", + "SCANIN": "CMT_PHASER_IN_CA_SCANIN", + "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", + "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", + "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", + "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", + "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", + "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", + "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST", + "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", + "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", + "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", + "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", + "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", + "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", + "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", + "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", + "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", + "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", + "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", + "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", + "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1", + "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", + "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", + "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", + "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", + "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", + "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", + "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", + "ICLK": "CMT_PHASER_IN_CA_ICLK", + "RCLK": "CMT_PHASER_IN_CA_RCLK" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "PHASER_OUT_PHY", + "type": "PHASER_OUT_PHY", + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_DB_COARSEINC", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", + "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", + "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", + "RST": "CMT_PHASER_OUT_DB_RST", + "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", + "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", + "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", + "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", + "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", + "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", + "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", + "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", + "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE", + "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", + "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", + "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", + "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", + "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "COARSEENABLE": "CMT_PHASER_OUT_DB_COARSEENABLE", + "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", + "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", + "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", + "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", + "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", + "COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", + "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", + "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", + "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", + "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", + "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", + "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", + "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", + "OCLK": "CMT_PHASER_OUT_DB_OCLK", + "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", + "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", + "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3", + "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING", + "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", + "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", + "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "PHASER_IN_PHY", + "type": "PHASER_IN_PHY", + "site_pins": { + "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", + "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE", + "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", + "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", + "RST": "CMT_PHASER_IN_DB_RST", + "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", + "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", + "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", + "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_IN_DB_FINEINC", + "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", + "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", + "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", + "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", + "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", + "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", + "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", + "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", + "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", + "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", + "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", + "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", + "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", + "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", + "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", + "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", + "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", + "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", + "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", + "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", + "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "STG1READ": "CMT_PHASER_IN_DB_STG1READ", + "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", + "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", + "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", + "SCANENB": "CMT_PHASER_IN_DB_SCANENB", + "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", + "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", + "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", + "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", + "SCANIN": "CMT_PHASER_IN_DB_SCANIN", + "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", + "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", + "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", + "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", + "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", + "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", + "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST", + "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", + "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", + "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", + "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", + "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", + "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", + "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", + "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", + "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", + "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", + "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", + "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", + "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1", + "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", + "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", + "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", + "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", + "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", + "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", + "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", + "ICLK": "CMT_PHASER_IN_DB_ICLK", + "RCLK": "CMT_PHASER_IN_DB_RCLK" + }, + "x_coord": 0 + } + ], + "wires": [ + "CMT_TOP_WR1END2_7", + "CMT_TOP_IMUX17_5", + "CMT_TOP_WW4C3_6", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_IMUX18_1", + "CMT_TOP_WL1END3_8", + "CMT_TOP_WW2A1_0", + "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "CMT_TOP_IMUX8_5", + "CMT_TOP_WW2END3_7", + "CMT_PHASER_IN_DB_EDGEADV", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_CLK1_3", + "CMT_TOP_IMUX15_8", + "CMT_TOP_LH5_7", + "CMT_PHASER_IN_CA_TESTOUT0", + "CMT_TOP_SE4C2_0", + "CMT_TOP_EE2A3_2", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_FAN2_3", + "CMT_TOP_IMUX40_8", + "CMT_PHASER_OUT_A_OCLK", + "CMT_TOP_EE4C2_7", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_SE4C3_8", + "CMT_TOP_NW2A1_4", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_EE2A1_6", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_TOP_EE4A2_4", + "CMT_TOP_BYP1_4", + "CMT_TOP_EE4C0_3", + "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_IMUX39_1", + "CMT_TOP_LH1_3", + "CMT_TOP_SE4C1_4", + "CMT_TOP_BYP5_7", + "CMT_TOP_IMUX47_8", + "CMT_PHASER_IN_DB_TESTIN6", + "CMT_TOP_IMUX23_5", + "CMT_TOP_IMUX36_0", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "CMT_TOP_IMUX34_7", + "CMT_PHASER_BOT_OBURSTPENDING1", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN5_3", + "CMT_TOP_NE4C2_2", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_NW4A2_2", + "CMT_TOP_EE4A2_5", + "CMT_PHASER_IN_CA_RANKSEL1", + "CMT_TOP_IMUX35_5", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_EE2A0_1", + "CMT_TOP_EE4C1_0", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_WW4END1_6", + "CMT_PHASER_IN_CA_ENCALIBPHY0", + "CMT_PHASER_OUT_DB_TESTIN1", + "CMT_TOP_WL1END1_8", + "CMT_TOP_FAN3_2", + "CMT_PHASER_IN_DB_WRENABLE", + "CMT_PHASER_OUT_DB_COUNTERREADEN", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_WW2END1_6", + "CMT_TOP_WW4END0_6", + "CMT_TOP_SE2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE2A2_1", + "CMT_LR_LOWER_T_CLK_MMCM2", + "CMT_TOP_EE2A2_5", + "CMT_PHASER_IN_CA_FREQREFCLK", + "CMT_TOP_WW2END0_3", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_FAN5_0", + "CMT_TOP_ER1BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_IMUX7_2", + "CMT_TOP_SE4C0_2", + "CMT_TOP_EE4B3_8", + "CMT_PHASER_OUT_DB_TESTIN12", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_EE4A1_2", + "CMT_PHASER_OUT_DB_TESTIN2", + "CMT_TOP_IMUX31_4", + "CMT_TOP_LH2_0", + "CMT_TOP_EL1BEG3_5", + "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "CMT_TOP_SE2A0_6", + "CMT_PHASER_IN_CA_RCLK", + "CMT_LR_LOWER_T_CLK_MMCM13", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_NW4A3_4", + "CMT_TOP_LH9_2", + "CMT_TOP_WW4END1_2", + "CMT_PHASER_IN_DB_STG1REGR7", + "CMT_TOP_WW4B1_5", + "CMT_TOP_EE2BEG2_1", + "CMT_PHASER_OUT_CA_TESTIN0", + "CMT_TOP_IMUX12_5", + "CMT_PHASER_OUT_DB_COARSEINC", + "CMT_PHASER_IN_DB_STG1REGR8", + "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "CMT_TOP_WW2A3_1", + "CMT_TOP_LH5_3", + "CMT_TOP_NE2A0_6", + "CMT_TOP_FAN4_1", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_EE4A0_6", + "CMT_PHASER_OUT_CA_COARSEENABLE", + "CMT_TOP_LH12_1", + "CMT_TOP_LH8_6", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_IMUX36_5", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_OCLK_6", + "CMT_TOP_SW4END1_5", + "CMT_TOP_WR1END0_2", + "CMT_TOP_NW4END1_8", + "CMT_TOP_SE2A0_8", + "CMT_TOP_LH11_2", + "CMT_TOP_EE4C3_2", + "CMT_TOP_IMUX2_7", + "CMT_TOP_EE2A1_7", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX16_6", + "CMT_TOP_LH6_2", + "CMT_PHASER_IN_DB_STG1REGL6", + "CMT_TOP_FAN6_6", + "CMT_TOP_NE2A2_7", + "CMT_TOP_LH7_6", + "CMT_PHASER_OUT_CA_TESTOUT3", + "CMT_TOP_IMUX9_2", + "CMT_TOP_WW4C0_1", + "CMT_TOP_BYP5_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_PHASER_IN_CA_ENCALIB0", + "CMT_LR_LOWER_T_CLK_MMCM7", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX45_3", + "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "CMT_TOP_WR1END1_7", + "CMT_TOP_WL1END1_1", + "CMT_PHASER_BOT_IRANKA1", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_SW2A0_3", + "CMT_PHASER_IN_DB_FINEINC", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_EE4C0_7", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX23_8", + "CMT_TOP_NW4END1_6", + "CMT_TOP_IMUX38_4", + "CMT_TOP_FAN6_7", + "CMT_PHASER_OUT_DB_SCANOUT", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_IMUX41_5", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_SW4END2_3", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_EE2BEG3_8", + "CMT_TOP_LH9_7", + "CMT_PHASER_OUT_CA_DQSBUS0", + "CMT_PHASER_IN_DB_TESTIN1", + "CMT_TOP_WW4A1_1", + "CMT_TOP_WR1END0_3", + "CMT_TOP_LH1_6", + "CMT_TOP_FAN2_7", + "CMT_PHASER_IN_DB_RANKSEL0", + "CMT_TOP_BYP7_6", + "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "CMT_PHASER_OUT_DB_DTSBUS0", + "CMT_TOP_NW4END3_0", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_NW4A1_5", + "CMT_PHASER_OUT_CA_TESTIN7", + "CMT_TOP_SE4BEG0_6", + "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "CMT_TOP_IMUX7_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_1", + "CMT_TOP_EE2BEG1_7", + "CMT_PHASER_OUT_CA_TESTIN14", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_FAN6_8", + "CMT_PHASER_IN_DB_STG1REGL4", + "CMT_TOP_WW4C1_4", + "CMT_TOP_NE2A2_5", + "CMT_TOP_SW2A3_2", + "CMT_TOP_IMUX3_7", + "CMT_TOP_NW4A2_4", + "CMT_TOP_WW4A0_8", + "CMT_TOP_WW4C2_4", + "CMT_TOP_NW4END0_5", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_TOP_LH6_5", + "CMT_PHASER_IN_CA_STG1READ", + "CMT_TOP_FAN5_7", + "CMT_TOP_OCLK_2", + "CMT_TOP_WL1END1_6", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_BYP6_0", + "CMT_TOP_FAN5_1", + "CMT_TOP_ER1BEG0_8", + "CMT_LR_LOWER_T_CLK_MMCM10", + "CMT_TOP_EE2BEG2_6", + "CMT_PHASER_IN_CA_DQSFOUND", + "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "CMT_TOP_NW4END1_7", + "CMT_TOP_EE2A1_4", + "CMT_TOP_FAN1_6", + "CMT_TOP_IMUX26_4", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_IMUX33_6", + "CMT_TOP_LH2_8", + "CMT_TOP_IMUX3_2", + "CMT_TOP_NW4A2_6", + "CMT_PHASER_IN_B_WRCLK_TOFIFO", + "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_LH4_2", + "CMT_TOP_NE4C1_6", + "CMT_TOP_EE4A1_8", + "CMT_PHASER_IN_DB_FINEENABLE", + "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "CMT_TOP_WW4END1_7", + "CMT_TOP_IMUX44_5", + "CMT_TOP_NE2A0_3", + "CMT_PHASER_IN_CA_TESTIN6", + "CMT_TOP_SE4C3_7", + "CMT_TOP_IMUX37_4", + "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "CMT_TOP_WW4C2_8", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_IMUX31_1", + "CMT_TOP_EE4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_WW4C3_7", + "CMT_TOP_WW4B3_1", + "CMT_TOP_IMUX8_4", + "CMT_TOP_EE4C0_8", + "CMT_TOP_IMUX33_1", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_PHASER_IN_DB_TESTIN3", + "CMT_TOP_EL1BEG0_7", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "CMT_TOP_WW4END1_3", + "CMT_TOP_SW2A0_1", + "CMT_TOP_IMUX33_8", + "CMT_TOP_NW4A1_3", + "CMT_TOP_LH10_0", + "CMT_TOP_LH5_6", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX7_5", + "CMT_TOP_WW2END1_0", + "CMT_TOP_EE4C2_1", + "CMT_TOP_IMUX13_3", + "CMT_TOP_ER1BEG2_5", + "CMT_TOP_WW4END1_4", + "CMT_PHASER_IN_DB_STG1REGR6", + "CMT_TOP_EE4BEG1_5", + "CMT_PHASER_IN_CA_SCANENB", + "CMT_TOP_EE4C2_4", + "CMT_TOP_EE2A1_3", + "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "CMT_TOP_EE4C1_5", + "CMT_TOP_LH9_1", + "CMT_TOP_SW4A2_3", + "CMT_TOP_SE2A1_3", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_NE4C3_7", + "CMT_TOP_IMUX12_2", + "CMT_TOP_SE2A0_1", + "CMT_TOP_WW4B1_8", + "CMT_TOP_LH12_3", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_FAN7_4", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END2_5", + "CMT_PHASER_OUT_DB_ENCALIB0", + "CMT_TOP_FAN1_0", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_IMUX40_7", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_PHASER_OUT_B_OCLKDIV", + "CMT_TOP_BYP7_8", + "CMT_PHASER_IN_DB_RANKSELPHY0", + "CMT_TOP_IMUX21_3", + "CMT_PHASER_OUT_DB_CTSBUS0", + "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "CMT_TOP_NW4A3_0", + "CMT_TOP_EE4A2_3", + "CMT_TOP_WL1END2_4", + "CMT_TOP_SW4A2_6", + "CMT_TOP_IMUX9_0", + "CMT_TOP_IMUX0_5", + "CMT_TOP_IMUX35_8", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_EE2A3_3", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW2A0_2", + "CMT_TOP_SW4END1_2", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_EE2A3_5", + "CMT_TOP_WR1END0_1", + "CMT_TOP_IMUX16_4", + "CMT_TOP_WW4C1_3", + "CMT_TOP_LH4_3", + "CMT_TOP_EE4B2_8", + "CMT_TOP_LH2_4", + "CMT_TOP_WW4C0_2", + "CMT_PHASER_OUT_CA_RDENABLE", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_IMUX5_2", + "CMT_TOP_EE2BEG1_6", + "CMT_PHASER_IN_CA_TESTIN13", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_EE4BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NW4A0_6", + "CMT_TOP_LH3_6", + "CMT_TOP_EE4A3_5", + "CMT_TOP_IMUX14_0", + "CMT_TOP_EE4C3_0", + "CMT_TOP_IMUX40_1", + "CMT_TOP_LH7_5", + "CMT_TOP_WW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_PHASERA_DQSBUS0", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_LR_LOWER_T_CLK_MMCM1", + "CMT_TOP_WW2END2_3", + "CMT_TOP_IMUX42_4", + "CMT_TOP_IMUX32_2", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_WW2END3_8", + "CMT_TOP_NW4END1_0", + "CMT_TOP_LH1_4", + "CMT_PHASER_IN_CA_RANKSELPHY0", + "CMT_TOP_BYP0_1", + "CMT_PHASER_OUT_DB_SYNCIN", + "CMT_TOP_NE4C2_5", + "CMT_TOP_NE4C0_6", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "CMT_TOP_IMUX24_1", + "CMT_TOP_IMUX14_4", + "CMT_TOP_IMUX12_4", + "CMT_TOP_IMUX12_1", + "CMT_TOP_SW4END3_2", + "CMT_TOP_IMUX32_0", + "CMT_TOP_SE4BEG0_1", + "CMT_TOP_IMUX29_3", + "CMT_TOP_IMUX18_0", + "CMT_PHASER_IN_CA_STG1REGR6", + "CMT_TOP_SW2A0_6", + "CMT_TOP_IMUX44_6", + "CMT_PHASER_DOWN_PHASERREF1", + "CMT_TOP_SE2A3_3", + "CMT_TOP_FAN7_6", + "CMT_PHASER_OUT_DB_MEMREFCLK", + "CMT_TOP_EE4A0_3", + "CMT_TOP_FAN0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_SW2A3_6", + "CMT_TOP_WW4B3_2", + "CMT_PHASER_IN_CA_TESTIN2", + "CMT_TOP_FAN0_7", + "CMT_TOP_WW4B0_3", + "CMT_TOP_LH11_8", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_PHASER_IN_CA_STG1REGR8", + "CMT_TOP_IMUX47_4", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_WW4C1_6", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_NW2A0_7", + "CMT_PHASER_DOWN_DQS_TO_PHASER_A", + "CMT_TOP_WR1END2_5", + "CMT_TOP_BYP5_3", + "CMT_TOP_NW4A2_1", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_SW4END3_7", + "CMT_TOP_FAN5_6", + "CMT_TOP_IMUX32_4", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_NW4END3_6", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "CMT_PHASER_IN_DB_PHASEREFCLK", + "CMT_TOP_IMUX45_6", + "CMT_TOP_EE4C3_1", + "CMT_TOP_WW4END2_8", + "CMT_TOP_CTRL0_3", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_WW4END1_0", + "CMT_TOP_LH3_2", + "CMT_TOP_SW4END1_7", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "CMT_TOP_IMUX8_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_IMUX2_8", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_IMUX6_5", + "CMT_TOP_WW4A3_5", + "CMT_TOP_OCLK_5", + "CMT_TOP_BYP0_3", + "CMT_PHASER_OUT_DB_TESTIN14", + "CMT_TOP_WW2A2_2", + "CMT_TOP_IMUX20_7", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_IMUX25_4", + "CMT_TOP_IMUX26_2", + "CMT_TOP_NW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_IMUX13_4", + "CMT_TOP_WW4C0_3", + "CMT_PHASER_IN_DB_RANKSEL1", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_NE2A0_2", + "CMT_TOP_IMUX28_5", + "CMT_TOP_WW4C3_8", + "CMT_PHASER_IN_DB_TESTIN13", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_NE2A0_8", + "CMT_TOP_LH6_4", + "CMT_TOP_NW2A2_4", + "CMT_TOP_BYP1_1", + "CMT_TOP_SE2A3_6", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX2_2", + "CMT_TOP_WW2END3_6", + "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "CMT_TOP_IMUX21_0", + "CMT_PHASER_IN_CA_SCANCLK", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "CMT_PHASER_IN_CA_RANKSEL0", + "CMT_PHASER_OUT_DB_TESTIN9", + "CMT_TOP_IMUX43_1", + "CMT_TOP_SE2A0_2", + "CMT_TOP_WW4B1_1", + "CMT_TOP_WW4B1_7", + "CMT_TOP_EE4BEG1_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_TOP_WW2A3_4", + "CMT_TOP_IMUX28_8", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_WW4C3_4", + "CMT_TOP_LH8_1", + "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "CMT_TOP_NW4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_WW2A3_2", + "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "CMT_TOP_NW4A0_7", + "CMT_TOP_BYP7_3", + "CMT_TOP_IMUX25_0", + "CMT_PHASER_IN_CA_TESTIN3", + "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "CMT_TOP_LH9_5", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_NE4C2_8", + "CMT_PHASER_OUT_DB_SCANENB", + "CMT_TOP_IMUX6_7", + "CMT_PHASER_OUT_DB_COARSEENABLE", + "CMT_PHASER_OUT_DB_FREQREFCLK", + "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "CMT_PHASER_IN_A_WRCLK_TOFIFO", + "CMT_PHASER_IN_DB_STG1REGR2", + "CMT_TOP_IMUX41_0", + "CMT_TOP_LH4_4", + "CMT_TOP_WR1END3_4", + "CMT_TOP_IMUX24_3", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_EE2A0_6", + "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "CMT_TOP_EE2A2_6", + "CMT_TOP_BYP2_2", + "CMT_PHASER_OUT_DB_EDGEADV", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_NW2A0_4", + "CMT_TOP_EE2A1_2", + "CMT_TOP_IMUX21_6", + "CMT_TOP_SE4C3_1", + "CMT_TOP_SW2A2_3", + "CMT_TOP_IMUX19_7", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX0_4", + "CMT_TOP_IMUX46_3", + "CMT_TOP_EE4A2_0", + "CMT_TOP_SW4END2_7", + "CMT_TOP_SE2A2_4", + "CMT_TOP_IMUX15_0", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_EE4A0_7", + "CMT_TOP_WW4C2_3", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_IMUX32_3", + "CMT_PHASER_IN_DB_COUNTERLOADEN", + "CMT_TOP_IMUX11_8", + "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_WW4END2_5", + "CMT_TOP_IMUX27_5", + "CMT_TOP_WW2A1_8", + "CMT_TOP_IMUX36_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_IMUX9_8", + "CMT_TOP_WL1END1_0", + "CMT_TOP_IMUX47_3", + "CMT_PHASER_IN_DB_ICLK", + "CMT_TOP_SW4A0_4", + "CMT_TOP_IMUX0_2", + "CMT_PHASER_IN_DB_ENCALIBPHY0", + "CMT_TOP_FAN1_8", + "CMT_PHASER_OUT_DB_TESTIN13", + "CMT_TOP_IMUX34_4", + "CMT_TOP_WW2A1_6", + "CMT_TOP_SW4A2_1", + "CMT_TOP_NW2A2_2", + "CMT_PHASER_IN_DB_STG1REGR5", + "CMT_TOP_FAN0_3", + "CMT_TOP_IMUX5_5", + "CMT_TOP_WW4B0_2", + "CMT_TOP_LH2_2", + "CMT_PHASER_OUT_CA_OCLKDIV", + "CMT_TOP_NW2A0_0", + "CMT_TOP_IMUX10_7", + "CMT_TOP_SE4BEG1_4", + "CMT_TOP_IMUX39_0", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_MONITOR_P_2", + "CMT_PHASER_B_TOMMCM_ICLKDIV", + "CMT_TOP_WW4C3_1", + "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "CMT_PHASER_OUT_CA_TESTIN13", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SE4C2_3", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_IMUX33_5", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "CMT_TOP_SW4A3_5", + "CMT_PHASER_OUT_CA_EDGEADV", + "CMT_PHASER_BOT_REFMUX_0", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_LH7_7", + "CMT_TOP_IMUX14_1", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_NW4END3_1", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_IMUX26_1", + "CMT_TOP_WW2END0_5", + "CMT_TOP_WL1END0_1", + "CMT_TOP_LH11_6", + "CMT_TOP_NE4C3_8", + "CMT_TOP_LH5_1", + "CMT_TOP_LH8_7", + "CMT_TOP_WL1END0_7", + "CMT_TOP_LH12_4", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_PHASER_OUT_CA_CTSBUS0", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_NE4C3_4", + "CMT_TOP_ER1BEG0_7", + "CMT_TOP_FAN6_5", + "CMT_TOP_WW2END2_4", + "CMT_TOP_SE4C2_6", + "CMT_TOP_SW4END1_8", + "CMT_TOP_IMUX27_1", + "CMT_TOP_NE4BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_SE2A2_8", + "CMT_TOP_SW2A1_1", + "CMT_TOP_WL1END2_5", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_WW4END3_5", + "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "CMT_TOP_WL1END2_6", + "CMT_TOP_IMUX43_6", + "CMT_TOP_IMUX14_8", + "CMT_PHASER_OUT_DB_TESTIN4", + "CMT_TOP_NW4A1_1", + "CMT_TOP_SE4C1_8", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_NW4END3_4", + "CMT_TOP_SE4BEG0_3", + "CMT_PHASER_IN_CA_TESTIN7", + "CMT_TOP_IMUX40_5", + "CMT_TOP_NE2A2_3", + "CMT_PHASER_IN_DB_STG1OVERFLOW", + "CMT_TOP_LH8_2", + "CMT_TOP_OCLK1X_90_5", + "CMT_PHASER_IN_DB_DQSFOUND", + "CMT_TOP_EE4BEG3_2", + "CMT_PHASER_IN_CA_ENCALIB1", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_IMUX34_1", + "CMT_TOP_WL1END2_0", + "CMT_TOP_EE4A1_3", + "CMT_TOP_LH7_0", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_WW2END0_2", + "CMT_TOP_IMUX0_3", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_EE4A0_1", + "CMT_TOP_WW4A1_4", + "CMT_TOP_IMUX23_3", + "CMT_TOP_IMUX20_0", + "CMT_TOP_WR1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_IMUX25_1", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_SE2A3_2", + "CMT_TOP_ER1BEG1_1", + "CMT_TOP_CLK1_8", + "CMT_TOP_IMUX44_7", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_PHASER_IN_DB_TESTIN7", + "CMT_PHASER_IN_DB_STG1REGR0", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_NW4A0_1", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_WW2A0_4", + "CMT_TOP_NW4END2_1", + "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "CMT_PHASER_B_TOMMCM_OCLK", + "CMT_TOP_EE4B0_8", + "CMT_TOP_NW4END2_8", + "CMT_TOP_CLK0_6", + "CMT_TOP_WR1END2_6", + "CMT_TOP_WW4A3_3", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_WW4END0_1", + "CMT_TOP_LH1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_NW4A0_4", + "CMT_TOP_CLK1_5", + "CMT_TOP_NW2A1_7", + "CMT_TOP_WW4A2_6", + "CMT_TOP_IMUX27_3", + "CMT_TOP_SW2A3_0", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_WR1END2_2", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_EE2A2_7", + "CMT_PHASER_IN_CA_STG1REGL7", + "CMT_TOP_IMUX18_5", + "CMT_TOP_IMUX8_0", + "CMT_TOP_IMUX24_8", + "CMT_TOP_IMUX24_7", + "CMT_PHASER_OUT_B_OCLK1X_90", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "CMT_PHASER_IN_CA_STG1REGL8", + "CMT_TOP_WW4C1_1", + "CMT_TOP_EE4B0_2", + "CMT_TOP_SW2A0_2", + "CMT_TOP_SW4A3_1", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_LH5_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4C2_0", + "CMT_PHASERA_DTSBUS1", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_WL1END3_2", + "CMT_LR_LOWER_T_CLK_MMCM11", + "CMT_TOP_FAN4_5", + "CMT_TOP_NE2A1_2", + "CMT_TOP_SE4BEG1_7", + "CMT_PHASER_OUT_A_OCLKDIV", + "CMT_TOP_WR1END0_8", + "CMT_TOP_IMUX36_3", + "CMT_TOP_WL1END1_4", + "CMT_TOP_WW4B1_6", + "CMT_PHASER_IN_DB_FINEOVERFLOW", + "CMT_TOP_WW2A3_7", + "CMT_TOP_BYP3_6", + "CMT_TOP_EE4B1_8", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_IMUX9_1", + "CMT_TOP_IMUX21_7", + "CMT_PHASER_B_TOMMCM_OCLKDIV", + "CMT_TOP_IMUX25_7", + "CMT_TOP_SW4A2_5", + "CMT_TOP_SE4C1_5", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_LH4_7", + "CMT_TOP_IMUX20_5", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_PHASER_OUT_DB_TESTOUT3", + "CMT_TOP_NE4C2_4", + "CMT_TOP_NE4C2_3", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_WW4A1_8", + "CMT_TOP_WW4B1_0", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_BYP7_5", + "CMT_TOP_NE2A0_5", + "CMT_TOP_IMUX23_7", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_TOP_EE4A0_2", + "CMT_PHASER_IN_DB_COUNTERREADEN", + "CMT_TOP_SW4END3_8", + "CMT_TOP_EE4A2_7", + "CMT_TOP_IMUX20_6", + "CMT_TOP_LH9_3", + "CMT_TOP_EE4B3_0", + "CMT_TOP_WW4END3_0", + "CMT_TOP_EE2A0_8", + "CMT_TOP_WW2A0_1", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_IMUX45_7", + "CMT_TOP_IMUX19_2", + "CMT_TOP_NW4END0_8", + "CMT_TOP_MONITOR_N_0", + "CMT_PHASER_OUT_B_RDEN_TOFIFO", + "CMT_TOP_WW4B2_3", + "CMT_TOP_IMUX23_0", + "CMT_TOP_IMUX42_5", + "CMT_TOP_EE2BEG3_1", + "CMT_LR_LOWER_T_CLK_IN2_HCLK", + "CMT_TOP_LH6_8", + "CMT_TOP_EE2BEG3_6", + "CMT_PHASER_IN_DB_SYNCIN", + "CMT_TOP_WL1END2_7", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_WL1END0_0", + "CMT_TOP_SW4END3_6", + "CMT_PHASER_IN_CA_RSTDQSFIND", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_SW4A0_3", + "CMT_TOP_FAN0_2", + "CMT_TOP_WW2END2_0", + "CMT_TOP_IMUX18_3", + "CMT_TOP_IMUX27_7", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_FAN1_1", + "CMT_TOP_NW2A3_8", + "CMT_TOP_BYP5_6", + "CMT_TOP_IMUX27_8", + "CMT_PHASER_OUT_CA_DTSBUS0", + "CMT_TOP_IMUX34_3", + "CMT_TOP_LH7_1", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_IMUX43_5", + "CMT_TOP_FAN0_0", + "CMT_PHASER_IN_DB_STG1INCDEC", + "CMT_TOP_IMUX41_4", + "CMT_PHASER_IN_DB_TESTIN2", + "CMT_TOP_IMUX33_0", + "CMT_PHASER_IN_DB_ICLKDIV", + "CMT_TOP_WR1END1_1", + "CMT_TOP_WW4END3_6", + "CMT_TOP_WW4B3_7", + "CMT_PHASER_OUT_A_OCLK1X_90", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_SW4A0_7", + "CMT_TOP_SE2A3_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "CMT_TOP_SW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_SE4C0_0", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_IMUX6_2", + "CMT_PHASER_BOT_REFMUX_2", + "CMT_PHASER_OUT_CA_SCANCLK", + "CMT_PHASER_OUT_DB_OCLKDIV", + "CMT_TOP_OCLKDIV_2", + "CMT_TOP_WW4A1_6", + "CMT_PHASER_IN_DB_TESTOUT1", + "CMT_TOP_WW4B3_4", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX5_3", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_WW4C2_5", + "CMT_TOP_IMUX40_0", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_EE2A2_8", + "CMT_TOP_LH5_0", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_NE2A3_7", + "CMT_PHASER_OUT_DB_TESTIN3", + "CMT_TOP_ER1BEG1_2", + "CMT_TOP_EE4A1_4", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX11_0", + "CMT_TOP_WW2END3_5", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_LH7_8", + "CMT_TOP_NE4C1_3", + "CMT_TOP_CTRL1_6", + "CMT_TOP_IMUX31_3", + "CMT_TOP_IMUX3_5", + "CMT_TOP_LH4_5", + "CMT_TOP_BYP7_4", + "CMT_TOP_IMUX37_3", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_PHASER_IN_CA_TESTIN9", + "CMT_TOP_CLK1_0", + "CMT_TOP_IMUX1_5", + "CMT_TOP_LH9_4", + "CMT_TOP_WW4C0_0", + "CMT_TOP_WW4A0_5", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_SE4C2_1", + "CMT_PHASER_IN_DB_TESTIN8", + "CMT_TOP_IMUX3_8", + "CMT_TOP_WW2A1_5", + "CMT_TOP_EE2A3_1", + "CMT_TOP_SE2A0_4", + "CMT_TOP_IMUX28_0", + "CMT_TOP_IMUX15_1", + "CMT_PHASER_IN_DB_ISERDESRST", + "CMT_TOP_IMUX6_3", + "CMT_TOP_EE4B2_7", + "CMT_PHASER_BOT_OBURSTPENDING0", + "CMT_TOP_IMUX18_2", + "CMT_PHASER_IN_CA_STG1REGR1", + "CMT_TOP_WW2END0_1", + "CMT_PHASER_OUT_DB_RST", + "CMT_PHASER_IN_CA_FINEENABLE", + "CMT_TOP_BYP3_0", + "CMT_TOP_BYP4_3", + "CMT_TOP_NE2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_PHASER_IN_B_ICLKDIV", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_WR1END0_7", + "CMT_TOP_IMUX24_5", + "CMT_TOP_FAN2_1", + "CMT_TOP_EE2A3_8", + "CMT_TOP_EE4A2_8", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_IMUX5_6", + "CMT_PHASER_IN_DB_TESTIN10", + "CMT_TOP_WW4C0_6", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_CTRL0_4", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SW4END0_6", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_BYP6_5", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "CMT_TOP_ER1BEG3_5", + "CMT_PHASER_OUT_CA_TESTIN10", + "CMT_TOP_IMUX37_5", + "CMT_TOP_IMUX37_8", + "CMT_PHASER_IN_DB_STG1REGL2", + "CMT_TOP_NW4A3_7", + "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "CMT_TOP_EE4C0_0", + "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "CMT_TOP_WW4END2_1", + "CMT_PHASER_IN_CA_STG1INCDEC", + "CMT_TOP_SE2A3_5", + "CMT_TOP_EE4A1_6", + "CMT_TOP_BYP7_7", + "CMT_TOP_SW4END1_0", + "CMT_TOP_IMUX29_5", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_IMUX35_3", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_IMUX25_5", + "CMT_PHASER_IN_A_RCLK0", + "CMT_TOP_WW4A2_3", + "CMT_PHASER_IN_DB_PHASELOCKED", + "CMT_TOP_WW4A3_4", + "CMT_TOP_IMUX10_4", + "CMT_TOP_WW4END2_6", + "CMT_PHASER_IN_DB_TESTIN11", + "CMT_PHASER_OUT_CA_BURSTPENDING", + "CMT_TOP_IMUX26_6", + "CMT_TOP_EE4A3_0", + "CMT_PHASER_IN_CA_DIVIDERST", + "CMT_TOP_IMUX46_8", + "CMT_TOP_BYP4_0", + "CMT_TOP_EE2A1_5", + "CMT_TOP_SW4END3_1", + "CMT_TOP_IMUX18_4", + "CMT_TOP_EL1BEG1_6", + "CMT_TOP_IMUX4_4", + "CMT_TOP_NW4END3_3", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_WW4C1_2", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_PHASER_OUT_DB_ENCALIB1", + "CMT_TOP_WW2A2_3", + "CMT_TOP_IMUX22_0", + "CMT_PHASER_B_OCLKDIV_TOIOI", + "CMT_TOP_IMUX28_3", + "CMT_TOP_SE2A1_1", + "CMT_TOP_IMUX29_6", + "CMT_TOP_LH6_1", + "CMT_TOP_LH7_3", + "CMT_PHASER_IN_DB_RCLK", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_TOP_WR1END0_4", + "CMT_TOP_EE2A0_4", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_EE4C0_6", + "CMT_TOP_NE2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH6_0", + "CMT_PHASER_IN_CA_TESTOUT3", + "CMT_TOP_IMUX24_0", + "CMT_TOP_WW4C0_7", + "CMT_TOP_SE4BEG2_2", + "CMT_PHASER_OUT_CA_SYNCIN", + "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "CMT_TOP_EL1BEG1_4", + "CMT_PHASER_IN_CA_STG1REGR4", + "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "CMT_TOP_LH3_5", + "CMT_TOP_NE4C0_4", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_SW2A3_3", + "CMT_TOP_SW4END0_1", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_SW2A1_7", + "CMT_PHASER_IN_DB_SCANENB", + "CMT_TOP_EE4B1_0", + "CMT_TOP_NE4C0_2", + "CMT_TOP_NE2A3_2", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "CMT_TOP_EE4B1_6", + "CMT_TOP_SE4C0_7", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_BYP3_2", + "CMT_TOP_SW4A1_8", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_WR1END3_3", + "CMT_TOP_MONITOR_P_1", + "CMT_TOP_CLK0_2", + "CMT_TOP_LH8_8", + "CMT_TOP_SW4A3_6", + "CMT_TOP_LH10_1", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_IMUX31_8", + "CMT_TOP_EE2A3_0", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_IMUX13_2", + "CMT_TOP_FAN3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_TOP_IMUX39_4", + "CMT_PHASER_IN_DB_SCANMODEB", + "CMT_TOP_SW2A1_4", + "CMT_TOP_MONITOR_P_3", + "CMT_TOP_EE4B1_7", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_WW4A0_7", + "CMT_TOP_IMUX3_4", + "CMT_TOP_ICLK_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "CMT_TOP_SE2A1_2", + "CMT_PHASER_OUT_CA_FINEENABLE", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_NE2A0_4", + "CMT_PHASER_OUT_DB_SCANMODEB", + "CMT_TOP_LH9_0", + "CMT_PHASER_IN_DB_DIVIDERST", + "CMT_TOP_IMUX22_3", + "CMT_TOP_IMUX27_6", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_IMUX31_0", + "CMT_TOP_IMUX25_6", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "CMT_TOP_LH2_3", + "CMT_TOP_IMUX29_8", + "CMT_TOP_NE2A1_4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "CMT_TOP_EE4BEG3_0", + "CMT_TOP_WW2END1_7", + "CMT_TOP_NE4C1_4", + "CMT_TOP_EE4B0_7", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_IMUX2_4", + "CMT_PHASER_OUT_CA_TESTIN8", + "CMT_TOP_BYP1_0", + "CMT_TOP_EE4C1_1", + "CMT_TOP_IMUX22_4", + "CMT_TOP_SE4C1_0", + "CMT_TOP_SW2A0_4", + "CMT_PHASER_OUT_CA_FREQREFCLK", + "CMT_TOP_FAN7_3", + "CMT_PHASER_IN_A_ICLKDIV", + "CMT_TOP_WW4A0_6", + "CMT_PHASER_IN_DB_SYSCLK", + "CMT_TOP_WW2END2_1", + "CMT_TOP_IMUX45_5", + "CMT_TOP_BYP6_4", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_TOP_BYP3_5", + "CMT_TOP_EE2A0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_LH8_4", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_EE4C2_2", + "CMT_TOP_WW4END2_0", + "CMT_TOP_EE4C0_1", + "CMT_PHASER_OUT_CA_CTSBUS1", + "CMT_TOP_CTRL1_5", + "CMT_TOP_CTRL0_5", + "CMT_TOP_WW2END0_6", + "CMT_PHASERREF_DOWN_PHASERIN_A", + "CMT_TOP_IMUX1_3", + "CMT_TOP_WW2END0_7", + "CMT_TOP_FAN5_8", + "CMT_TOP_WW4C1_0", + "CMT_PHASER_OUT_DB_TESTOUT2", + "CMT_TOP_WL1END2_3", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_LH10_7", + "CMT_TOP_SE4C0_1", + "CMT_TOP_WW4C1_7", + "CMT_TOP_IMUX10_3", + "CMT_TOP_SE2A0_5", + "CMT_PHASER_OUT_CA_TESTIN6", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_WR1END3_8", + "CMT_TOP_EE4A2_2", + "CMT_TOP_IMUX47_1", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_IMUX10_6", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_NE4C1_0", + "CMT_PHASER_IN_DB_STG1READ", + "CMT_TOP_WW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BYP6_6", + "CMT_TOP_BYP0_0", + "CMT_TOP_EE4B2_2", + "CMT_TOP_FAN7_7", + "CMT_PHASER_OUT_DB_TESTIN6", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_WW4A0_4", + "CMT_TOP_NE4C0_3", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_WW4A3_0", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_OCLKDIV_8", + "CMT_TOP_SE4C1_1", + "CMT_TOP_LH2_1", + "CMT_TOP_ER1BEG0_6", + "CMT_TOP_IMUX46_1", + "CMT_TOP_IMUX42_1", + "CMT_TOP_SW4A1_6", + "CMT_PHASER_IN_DB_STG1REGL8", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_IMUX30_8", + "CMT_TOP_SW2A1_0", + "CMT_TOP_LH12_0", + "CMT_PHASER_B_OCLK_TOIOI", + "CMT_TOP_CLK0_1", + "CMT_TOP_BYP5_4", + "CMT_TOP_IMUX45_2", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_BYP1_8", + "CMT_TOP_WW4C2_6", + "CMT_TOP_IMUX19_5", + "CMT_TOP_WW4C2_1", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_IMUX42_0", + "CMT_TOP_NW4END0_1", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_FAN7_1", + "CMT_TOP_LH9_8", + "CMT_PHASER_IN_DB_TESTOUT2", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_PHASER_IN_CA_STG1REGL4", + "CMT_TOP_NW2A2_7", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_WW2A3_0", + "CMT_TOP_SW4END0_5", + "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "CMT_TOP_IMUX29_1", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_IMUX9_5", + "CMT_TOP_SW4A0_2", + "CMT_TOP_WW2END1_5", + "CMT_TOP_WW2A2_8", + "CMT_TOP_LH1_7", + "CMT_TOP_OCLK_8", + "CMT_TOP_NW4A1_6", + "CMT_TOP_BYP2_1", + "CMT_TOP_IMUX46_7", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_PHASER_IN_B_RCLK1", + "CMT_TOP_IMUX13_0", + "CMT_TOP_IMUX30_7", + "MMCM_CLK_FREQBB_REBUFOUT0", + "CMT_TOP_IMUX8_3", + "CMT_TOP_WW4A0_3", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_FAN2_0", + "CMT_TOP_IMUX14_7", + "CMT_TOP_NW2A2_0", + "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "CMT_TOP_SE4C0_5", + "CMT_PHASER_IN_CA_PHASELOCKED", + "CMT_TOP_EE2A0_5", + "CMT_TOP_CTRL1_0", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_TOP_WW4A0_1", + "CMT_PHASER_IN_DB_STG1REGL0", + "CMT_TOP_SW4END3_4", + "CMT_TOP_FAN3_0", + "CMT_TOP_LH2_7", + "CMT_TOP_SE2A2_7", + "CMT_TOP_IMUX30_2", + "CMT_TOP_SW2A1_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_FAN3_3", + "CMT_TOP_IMUX2_5", + "CMT_TOP_IMUX22_8", + "CMT_TOP_IMUX28_4", + "CMT_TOP_LH3_7", + "CMT_PHASER_IN_CA_STG1REGL3", + "CMT_TOP_EL1BEG3_7", + "CMT_TOP_LH11_0", + "CMT_TOP_IMUX43_8", + "CMT_TOP_LH10_5", + "CMT_TOP_IMUX15_5", + "CMT_PHASER_OUT_DB_DQSBUS0", + "CMT_TOP_NE4BEG2_5", + "CMT_TOP_IMUX13_8", + "CMT_PHASER_IN_CA_STG1REGL1", + "CMT_TOP_EE4C0_5", + "CMT_TOP_IMUX2_0", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_PHASER_OUT_CA_OCLKDELAYED", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_NE2A0_0", + "CMT_TOP_SW4END1_1", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_NE2A2_6", + "CMT_TOP_LH12_7", + "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "CMT_TOP_SW2A2_2", + "CMT_TOP_WR1END3_7", + "CMT_TOP_WL1END1_7", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_OCLK_4", + "CMT_TOP_LH11_1", + "CMT_TOP_EE4C1_2", + "CMT_TOP_BYP0_4", + "CMT_TOP_FAN4_0", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_PHASER_OUT_CA_FINEINC", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_WW2A2_4", + "CMT_TOP_FAN4_4", + "CMT_TOP_WW4A1_3", + "CMT_TOP_LH5_2", + "CMT_TOP_IMUX17_8", + "CMT_TOP_IMUX36_7", + "CMT_TOP_BYP1_7", + "CMT_TOP_IMUX4_5", + "CMT_TOP_IMUX7_8", + "CMT_TOP_EE4C0_4", + "CMT_TOP_EL1BEG2_1", + "CMT_TOP_BYP7_0", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_BYP6_2", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_ICLK_7", + "CMT_TOP_EE4C2_8", + "CMT_TOP_LH11_3", + "CMT_PHASER_OUT_CA_OSERDESRST", + "CMT_PHASER_IN_CA_ENSTG1", + "CMT_TOP_IMUX14_6", + "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "CMT_TOP_IMUX32_1", + "CMT_TOP_IMUX11_4", + "CMT_TOP_SW2A2_4", + "CMT_LR_LOWER_T_CLK_MMCM12", + "CMT_PHASER_BOT_SYNC_BB", + "CMT_TOP_EE4C3_7", + "CMT_PHASER_OUT_DB_TESTOUT0", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_WW4B3_0", + "CMT_TOP_IMUX10_1", + "CMT_TOP_NE4C3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "CMT_LR_LOWER_T_CLK_MMCM3", + "CMT_TOP_IMUX10_5", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_WW2END1_1", + "CMT_TOP_FAN1_7", + "CMT_TOP_IMUX23_2", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_IMUX6_4", + "CMT_TOP_IMUX5_0", + "CMT_TOP_ICLK_6", + "CMT_TOP_IMUX22_1", + "CMT_TOP_WW4B0_8", + "CMT_TOP_OCLKDIV_6", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_TOP_NW4A3_1", + "CMT_TOP_IMUX27_0", + "CMT_TOP_IMUX43_7", + "CMT_TOP_SE4C2_8", + "CMT_TOP_EE2BEG0_4", + "CMT_PHASER_OUT_CA_TESTIN9", + "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "CMT_TOP_SE4C2_4", + "CMT_PHASER_IN_A_ICLK", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_WR1END3_0", + "CMT_TOP_SE2A2_1", + "CMT_TOP_NW4END1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_EE2BEG0_7", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_IMUX38_7", + "CMT_PHASER_OUT_CA_COARSEINC", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX42_7", + "CMT_TOP_SW4A2_7", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_EE2BEG2_4", + "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "CMT_TOP_LH1_2", + "CMT_TOP_IMUX35_7", + "CMT_LR_LOWER_T_CLK_MMCM0", + "CMT_PHASER_OUT_DB_TESTIN8", + "CMT_TOP_IMUX30_3", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_WR1END1_6", + "CMT_TOP_FAN3_7", + "CMT_TOP_SW2A2_5", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_NW2A1_8", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_EE4B2_1", + "CMT_PHASERREF_DOWN_PHASERIN_B", + "CMT_TOP_SW2A2_0", + "CMT_TOP_SW4A1_1", + "CMT_TOP_NW4END2_3", + "CMT_TOP_FAN4_2", + "CMT_PHASERA_DQSBUS1", + "CMT_TOP_SW2A0_8", + "CMT_TOP_IMUX43_0", + "CMT_TOP_EE4B3_7", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_IMUX44_3", + "CMT_TOP_WW4END0_8", + "CMT_TOP_SW4A1_4", + "CMT_PHASER_OUT_CA_SCANMODEB", + "CMT_TOP_SE2A0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_BYP2_3", + "CMT_PHASER_BOT_IRANKB1", + "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "CMT_TOP_IMUX40_3", + "CMT_TOP_IMUX29_0", + "CMT_TOP_FAN6_0", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_IMUX43_2", + "CMT_TOP_IMUX11_6", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_EE4B1_1", + "CMT_PHASER_IN_CA_ISERDESRST", + "CMT_PHASER_IN_DB_STG1REGL5", + "CMT_TOP_NW2A2_8", + "CMT_TOP_BYP4_2", + "CMT_TOP_NE4BEG3_8", + "CMT_PHASER_IN_CA_STG1REGL2", + "CMT_TOP_WW2A0_3", + "CMT_TOP_WW2A2_5", + "CMT_TOP_SW4END1_6", + "CMT_PHASER_BOT_REFMUX_1", + "CMT_TOP_EE4B2_5", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_WW2A2_0", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_IMUX26_7", + "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "CMT_TOP_IMUX1_7", + "CMT_TOP_IMUX23_6", + "CMT_TOP_NE4C3_2", + "CMT_TOP_WW2END3_3", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_SE4BEG3_4", + "CMT_TOP_IMUX5_4", + "CMT_TOP_IMUX6_8", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_PHASER_OUT_CA_OCLK", + "CMT_TOP_WW2END3_2", + "CMT_TOP_IMUX4_3", + "CMT_TOP_NE4C2_1", + "CMT_TOP_EE4C1_6", + "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "CMT_TOP_NW4END3_7", + "CMT_PHASER_OUT_CA_TESTIN15", + "CMT_TOP_IMUX13_5", + "CMT_TOP_IMUX46_6", + "CMT_TOP_WW4END0_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_SW4END2_2", + "CMT_TOP_LH12_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_CLK1_2", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_NE2A3_8", + "CMT_PHASER_IN_DB_RANKSELPHY1", + "CMT_TOP_EL1BEG0_3", + "CMT_PHASER_OUT_CA_MEMREFCLK", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_LR_LOWER_T_CLK_MMCM5", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_SW4A1_3", + "CMT_TOP_IMUX15_7", + "CMT_TOP_NW4A2_8", + "CMT_TOP_WR1END1_5", + "CMT_TOP_SE4C2_5", + "CMT_TOP_SW4END2_0", + "CMT_TOP_WW4END1_5", + "CMT_TOP_NW4A0_5", + "CMT_TOP_EE2A2_2", + "CMT_TOP_ER1BEG3_3", + "CMT_TOP_WW4A0_2", + "CMT_TOP_IMUX37_6", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_FAN2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_IMUX41_2", + "CMT_TOP_IMUX20_2", + "CMT_TOP_IMUX0_0", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_SW4END2_6", + "CMT_TOP_IMUX45_1", + "CMT_PHASER_OUT_CA_TESTIN4", + "CMT_TOP_NW2A3_4", + "CMT_TOP_WW4B3_3", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_IMUX42_6", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_LH3_1", + "CMT_PHASER_OUT_B_OCLK", + "CMT_TOP_NE4C3_3", + "CMT_TOP_BYP2_0", + "CMT_TOP_EE4C0_2", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "MMCM_CLK_FREQBB_REBUFOUT1", + "CMT_TOP_LH12_6", + "CMT_PHASER_IN_DB_TESTIN9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_IMUX35_6", + "CMT_TOP_EE4A1_1", + "CMT_TOP_IMUX26_3", + "CMT_TOP_SW4A2_0", + "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "CMT_PHASER_IN_DB_ENCALIB0", + "CMT_TOP_FAN3_6", + "CMT_TOP_SW4END2_1", + "CMT_PHASER_OUT_DB_DQSBUS1", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_IMUX47_0", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_PHASER_IN_CA_SELCALORSTG1", + "CMT_TOP_FAN5_5", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_WW2A1_3", + "CMT_TOP_FAN2_5", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_SE4C0_3", + "CMT_TOP_IMUX45_4", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_PHASER_OUT_DB_SCANIN", + "CMT_TOP_WW2END1_8", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_WR1END2_0", + "CMT_TOP_NE2A1_0", + "CMT_PHASER_OUT_CA_TESTIN1", + "CMT_TOP_EE2A3_7", + "CMT_TOP_IMUX19_0", + "CMT_TOP_WR1END0_0", + "CMT_TOP_LH1_8", + "CMT_TOP_NE2A3_3", + "CMT_TOP_WW2A0_7", + "CMT_TOP_WW4C1_8", + "CMT_TOP_NE4C0_5", + "CMT_TOP_IMUX8_6", + "CMT_TOP_WL1END2_2", + "CMT_PHASER_OUT_DB_TESTIN5", + "CMT_TOP_EE4BEG1_4", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_EE2BEG2_8", + "CMT_TOP_EE4A3_4", + "CMT_PHASER_IN_DB_TESTIN12", + "CMT_TOP_SW4END0_2", + "CMT_TOP_BYP1_2", + "CMT_TOP_SW4A0_6", + "CMT_TOP_BYP5_8", + "CMT_TOP_FAN5_4", + "CMT_PHASER_BOT_IRANKB0", + "CMT_TOP_WW4END2_3", + "CMT_TOP_IMUX41_7", + "CMT_TOP_IMUX25_2", + "CMT_TOP_EE4A3_1", + "CMT_TOP_IMUX12_8", + "CMT_TOP_IMUX24_2", + "CMT_TOP_WW2A3_3", + "CMT_TOP_IMUX1_6", + "CMT_TOP_IMUX6_0", + "CMT_TOP_IMUX21_2", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_CLK1_1", + "CMT_TOP_EE4B2_0", + "CMT_TOP_WW4A2_0", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_PHASER_IN_CA_TESTIN4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "CMT_TOP_SW2A0_7", + "CMT_TOP_CLK0_8", + "CMT_TOP_IMUX44_0", + "CMT_TOP_BYP4_6", + "CMT_TOP_IMUX7_0", + "CMT_PHASER_OUT_DB_TESTIN11", + "CMT_TOP_IMUX9_4", + "CMT_TOP_EE4A0_4", + "CMT_TOP_NE2A2_0", + "CMT_TOP_LH9_6", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_WW2END2_7", + "CMT_PHASER_IN_DB_STG1REGL7", + "CMT_TOP_SW2A3_7", + "CMT_TOP_SE4BEG1_1", + "CMT_TOP_NW4END3_8", + "CMT_TOP_NW4A1_2", + "CMT_TOP_SE2A0_7", + "CMT_TOP_NW4END3_5", + "CMT_TOP_IMUX21_5", + "CMT_TOP_WW4B1_3", + "CMT_TOP_WW4END3_4", + "CMT_PHASER_OUT_CA_ENCALIB0", + "CMT_TOP_WR1END2_8", + "CMT_PHASER_OUT_DB_OCLK", + "CMT_TOP_WL1END0_8", + "CMT_TOP_NW2A0_2", + "CMT_TOP_SE2A3_0", + "CMT_TOP_EE4B0_3", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_FAN1_3", + "CMT_TOP_NW4A3_6", + "CMT_TOP_SE2A1_4", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "CMT_TOP_SE4C0_6", + "CMT_TOP_SE4C1_7", + "CMT_TOP_IMUX17_4", + "CMT_PHASER_OUT_DB_RDENABLE", + "CMT_TOP_BYP0_8", + "CMT_PHASER_OUT_A_RDCLK_TOFIFO", + "CMT_TOP_EE4A3_3", + "CMT_TOP_LH10_6", + "CMT_TOP_NW4A3_2", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_R_TOP_LOWER_B_CLKINT_1", + "CMT_TOP_LH3_4", + "CMT_TOP_SW4END2_4", + "CMT_TOP_WL1END0_6", + "CMT_TOP_LH8_0", + "CMT_TOP_IMUX24_6", + "CMT_TOP_IMUX45_8", + "CMT_TOP_IMUX33_7", + "CMT_TOP_IMUX28_7", + "CMT_TOP_IMUX37_2", + "CMT_TOP_NE4BEG3_4", + "CMT_PHASER_OUT_CA_PHASEREFCLK", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_TOP_EE4B3_6", + "CMT_TOP_NW4END2_5", + "CMT_TOP_EE4A1_7", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_IMUX15_3", + "CMT_PHASER_OUT_B_RDCLK_TOFIFO", + "CMT_TOP_EE4B0_5", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_SW4END0_3", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "CMT_LR_LOWER_T_CLK_PERF0", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_LH6_7", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_BYP3_8", + "CMT_TOP_IMUX17_0", + "CMT_BOT_HCLKMUX_CLKINT_0", + "CMT_TOP_NE2A3_1", + "CMT_PHASER_IN_CA_STG1REGR3", + "CMT_TOP_IMUX11_3", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_EE4B2_4", + "CMT_TOP_NW2A3_2", + "CMT_TOP_EE4B3_1", + "CMT_TOP_WW4B3_5", + "CMT_TOP_WW2A3_5", + "CMT_TOP_WW2END2_6", + "CMT_LR_LOWER_T_CLK_PERF2", + "CMT_TOP_SW4END0_7", + "CMT_PHASER_OUT_CA_TESTIN2", + "CMT_PHASER_OUT_DB_TESTIN0", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_SE4C2_2", + "CMT_TOP_WL1END1_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_SE2A1_7", + "CMT_TOP_NE4BEG2_4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "CMT_TOP_WL1END3_5", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_IMUX3_1", + "CMT_PHASER_IN_CA_STG1REGR7", + "CMT_TOP_WW2A3_8", + "CMT_TOP_WW2END3_0", + "CMT_TOP_WR1END2_1", + "CMT_TOP_NW4A1_4", + "CMT_TOP_IMUX30_6", + "CMT_TOP_EL1BEG0_1", + "CMT_TOP_IMUX22_5", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_IMUX20_3", + "CMT_TOP_BYP6_8", + "CMT_TOP_IMUX12_0", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX14_2", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "CMT_TOP_BYP4_4", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_CLK1_7", + "CMT_TOP_NE2A1_1", + "CMT_TOP_IMUX2_3", + "CMT_LR_LOWER_T_CLK_MMCM6", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_IMUX19_3", + "CMT_TOP_IMUX46_5", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_NW4END1_3", + "CMT_TOP_WW4B0_5", + "CMT_TOP_ICLK_8", + "CMT_TOP_NW2A3_5", + "CMT_TOP_WR1END2_3", + "CMT_TOP_IMUX7_6", + "CMT_TOP_SW2A1_2", + "CMT_TOP_BYP2_6", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_IMUX36_2", + "CMT_TOP_WW2END3_1", + "CMT_TOP_BYP3_3", + "CMT_TOP_FAN6_2", + "CMT_TOP_NE4C0_1", + "CMT_TOP_NW2A2_3", + "CMT_PHASER_B_OCLK90_TOIOI", + "CMT_TOP_IMUX40_4", + "CMT_TOP_IMUX11_5", + "CMT_TOP_IMUX47_6", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_TOP_NE4BEG2_2", + "CMT_TOP_SW4A3_4", + "CMT_TOP_FAN7_0", + "CMT_TOP_LH11_5", + "CMT_TOP_IMUX30_5", + "CMT_TOP_SE2A3_1", + "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "CMT_TOP_IMUX30_1", + "CMT_TOP_EE4A3_6", + "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "CMT_PHASER_IN_CA_WRENABLE", + "CMT_TOP_IMUX5_1", + "CMT_TOP_EE4BEG3_6", + "CMT_TOP_SE4C3_2", + "CMT_TOP_SE2A2_0", + "CMT_TOP_NE4C0_7", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_EE4A2_1", + "CMT_TOP_EE4B3_4", + "CMT_TOP_EE4C3_6", + "CMT_TOP_WW4B0_0", + "CMT_TOP_IMUX43_3", + "CMT_PHASER_OUT_CA_TESTOUT0", + "CMT_PHASER_OUT_DB_PHASEREFCLK", + "CMT_TOP_IMUX27_2", + "CMT_TOP_IMUX33_3", + "CMT_TOP_IMUX21_4", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_FAN0_8", + "CMT_TOP_EE4A2_6", + "CMT_TOP_LH5_8", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_FAN2_6", + "CMT_PHASER_IN_CA_TESTIN8", + "CMT_TOP_SE4BEG0_8", + "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "CMT_TOP_WW4END3_1", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_IMUX35_4", + "CMT_TOP_SW2A2_6", + "CMT_TOP_IMUX42_8", + "CMT_TOP_EE2A3_4", + "CMT_TOP_EE4BEG2_6", + "CMT_R_TOP_LOWER_B_CLKINT_0", + "CMT_TOP_IMUX38_8", + "CMT_PHASER_OUT_CA_TESTOUT2", + "CMT_TOP_CLK0_0", + "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_SE2A1_6", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_NW4END0_6", + "CMT_TOP_FAN7_2", + "CMT_TOP_EE2A0_7", + "CMT_TOP_IMUX10_0", + "CMT_PHASER_OUT_DB_TESTIN7", + "CMT_TOP_IMUX43_4", + "CMT_TOP_EE4A0_0", + "CMT_TOP_IMUX36_1", + "CMT_TOP_LH1_0", + "CMT_TOP_WW4A3_6", + "CMT_PHASER_OUT_DB_CTSBUS1", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_IMUX37_1", + "CMT_TOP_EE4C3_5", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_TOP_NE4C3_5", + "CMT_TOP_WW4A3_2", + "CMT_PHASER_IN_DB_ENSTG1", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_BYP5_2", + "CMT_TOP_BYP0_5", + "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_IMUX6_1", + "CMT_TOP_ICLK_2", + "CMT_TOP_IMUX36_4", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LH4_8", + "CMT_TOP_BYP4_1", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_IMUX9_3", + "CMT_TOP_IMUX15_6", + "CMT_PHASER_OUT_DB_BURSTPENDING", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_NE2A3_5", + "CMT_TOP_IMUX7_3", + "CMT_TOP_NE2A1_8", + "CMT_TOP_NW4END1_1", + "CMT_TOP_FAN3_8", + "CMT_PHASER_IN_CA_RST", + "CMT_TOP_LH4_1", + "CMT_PHASER_OUT_DB_FINEENABLE", + "CMT_TOP_LH12_2", + "CMT_PHASER_IN_CA_FINEINC", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX45_0", + "CMT_TOP_EE4C2_5", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_ICLKDIV_6", + "CMT_PHASER_IN_CA_TESTIN10", + "CMT_TOP_EE4C2_3", + "CMT_PHASER_IN_DB_TESTIN5", + "CMT_TOP_WR1END1_8", + "CMT_TOP_IMUX19_8", + "CMT_TOP_IMUX17_6", + "CMT_TOP_WW2A2_6", + "CMT_PHASER_IN_CA_STG1REGR2", + "CMT_TOP_IMUX14_5", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_IMUX34_2", + "CMT_TOP_BYP1_6", + "CMT_TOP_SW4A2_2", + "CMT_TOP_EE4A0_5", + "CMT_TOP_BYP4_5", + "CMT_TOP_WW4A2_8", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NW2A0_5", + "CMT_TOP_NE4BEG3_6", + "CMT_PHASER_IN_CA_SCANIN", + "CMT_TOP_IMUX39_5", + "CMT_TOP_NW4A2_7", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_IMUX38_1", + "CMT_TOP_WW2A0_8", + "CMT_TOP_SW4END1_4", + "CMT_TOP_FAN7_5", + "CMT_TOP_CTRL1_4", + "CMT_TOP_EE4B0_1", + "CMT_TOP_IMUX18_6", + "CMT_TOP_NE4C2_0", + "CMT_TOP_SW2A3_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_IMUX8_1", + "CMT_TOP_WW4A3_7", + "CMT_TOP_OCLK_0", + "CMT_PHASERA_CTSBUS1", + "CMT_TOP_WW4A1_7", + "CMT_TOP_IMUX41_6", + "CMT_TOP_NE4C2_7", + "CMT_TOP_LH4_0", + "CMT_TOP_SW2A2_8", + "CMT_TOP_IMUX20_8", + "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "CMT_TOP_BYP2_7", + "CMT_TOP_SW4A1_2", + "CMT_TOP_FAN3_4", + "CMT_TOP_SW4END3_3", + "CMT_TOP_IMUX16_7", + "CMT_TOP_IMUX15_2", + "CMT_TOP_SE4C3_4", + "CMT_TOP_LH11_7", + "CMT_TOP_SE4C3_3", + "CMT_LR_LOWER_T_CLK_MMCM9", + "CMT_TOP_IMUX12_3", + "CMT_TOP_NW2A3_1", + "CMT_TOP_WW4A1_5", + "CMT_TOP_EE4C1_3", + "CMT_TOP_FAN3_5", + "CMT_TOP_CLK0_5", + "CMT_TOP_WW2END1_4", + "CMT_PHASER_IN_CA_SYNCIN", + "CMT_TOP_WW2A2_7", + "CMT_PHASER_IN_CA_TESTIN11", + "CMT_TOP_OCLK_1", + "CMT_TOP_WL1END3_4", + "CMT_TOP_NW2A1_5", + "CMT_PHASER_OUT_CA_ENCALIB1", + "CMT_TOP_IMUX16_2", + "CMT_TOP_BYP2_5", + "CMT_TOP_IMUX40_2", + "CMT_TOP_WW4B2_8", + "CMT_PHASER_IN_CA_STG1REGL6", + "CMT_TOP_EE4B3_2", + "CMT_TOP_EE4B1_2", + "CMT_TOP_SE4C1_2", + "CMT_BOT_HCLKMUX_CLKINT_1", + "CMT_TOP_NW4END2_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_FAN6_1", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_EE4C1_7", + "CMT_TOP_FAN0_6", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_SW4END2_8", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_SE4C1_6", + "CMT_TOP_IMUX39_6", + "CMT_TOP_IMUX35_2", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_WL1END0_2", + "CMT_PHASER_OUT_CA_TESTIN3", + "CMT_TOP_IMUX18_7", + "CMT_TOP_IMUX44_1", + "CMT_TOP_SE4BEG3_2", + "CMT_PHASER_IN_CA_TESTIN12", + "CMT_TOP_EE2BEG1_8", + "CMT_PHASER_IN_CA_STG1REGL5", + "CMT_TOP_WW2A1_2", + "CMT_TOP_IMUX16_5", + "CMT_PHASER_IN_DB_STG1REGR3", + "CMT_PHASER_OUT_CA_COUNTERREADEN", + "CMT_PHASER_OUT_DB_OCLKDELAYED", + "CMT_TOP_WW4A2_5", + "CMT_TOP_NW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_PHASER_IN_DB_ENCALIBPHY1", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX44_2", + "CMT_TOP_IMUX39_7", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_CTRL0_0", + "CMT_TOP_EL1BEG0_4", + "CMT_TOP_IMUX26_0", + "CMT_TOP_IMUX4_6", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_IMUX1_8", + "CMT_TOP_IMUX38_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_NW2A1_0", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_WW4B3_8", + "CMT_PHASER_IN_CA_SCANOUT", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_EE4B3_3", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_WW4B0_6", + "CMT_PHASER_IN_DB_STG1REGR1", + "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "CMT_TOP_IMUX38_0", + "CMT_TOP_NW2A0_1", + "CMT_TOP_IMUX27_4", + "CMT_TOP_SW2A2_1", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_EE4C1_8", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_EE4C1_4", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_PHASER_IN_DB_TESTOUT3", + "CMT_TOP_BYP1_3", + "CMT_TOP_CTRL0_6", + "CMT_LR_LOWER_T_CLK_MMCM8", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_EL1BEG2_2", + "CMT_PHASER_OUT_DB_TESTIN10", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_BYP2_4", + "CMT_TOP_IMUX17_3", + "CMT_TOP_FAN0_1", + "CMT_PHASER_OUT_DB_TESTOUT1", + "CMT_TOP_NW2A3_6", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_WW4END0_4", + "CMT_TOP_CLK0_7", + "CMT_TOP_WL1END3_0", + "CMT_TOP_IMUX28_2", + "CMT_TOP_IMUX21_8", + "CMT_TOP_IMUX13_7", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_EE2A2_0", + "CMT_TOP_ICLK_4", + "CMT_TOP_IMUX4_0", + "CMT_TOP_IMUX3_6", + "CMT_TOP_BYP7_1", + "CMT_TOP_WW2END0_8", + "CMT_TOP_IMUX42_2", + "CMT_TOP_WW2A3_6", + "CMT_TOP_WW4B0_4", + "CMT_PHASER_OUT_CA_SCANENB", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_SE2A2_5", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_TOP_WW2END1_3", + "CMT_TOP_SE2A3_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_SW4END3_5", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_EE2BEG2_7", + "CMT_PHASER_IN_DB_TESTIN0", + "CMT_TOP_ICLK_0", + "CMT_TOP_EE4BEG2_0", + "CMT_PHASER_OUT_A_RDEN_TOFIFO", + "CMT_TOP_NW4END1_2", + "CMT_TOP_BYP3_4", + "CMT_TOP_SE4C3_0", + "CMT_TOP_IMUX25_8", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX31_7", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_NW2A1_3", + "CMT_TOP_FAN6_4", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_IMUX47_2", + "CMT_TOP_EE2BEG0_1", + "CMT_PHASER_IN_DB_TESTOUT0", + "CMT_TOP_SW4END3_0", + "CMT_TOP_IMUX3_3", + "CMT_TOP_NE2A3_0", + "CMT_PHASER_IN_CA_STG1REGL0", + "CMT_TOP_WW2END1_2", + "CMT_PHASER_IN_CA_RANKSELPHY1", + "CMT_TOP_SE4C1_3", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_CLK0_3", + "CMT_TOP_LH10_4", + "CMT_TOP_BYP0_2", + "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NE4C0_8", + "CMT_PHASER_IN_CA_STG1OVERFLOW", + "CMT_PHASER_IN_DB_SELCALORSTG1", + "CMT_TOP_SW2A2_7", + "CMT_TOP_NW2A1_1", + "CMT_TOP_NW2A2_5", + "CMT_PHASER_IN_B_WREN_TOFIFO", + "CMT_PHASER_IN_DB_SCANIN", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX19_6", + "CMT_TOP_WW4A1_2", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_IMUX25_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_SE4BEG2_5", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_PHASER_BOT_IRANKA0", + "CMT_TOP_NE4C1_7", + "CMT_TOP_EE4C3_8", + "MMCM_CLK_FREQBB_REBUFOUT3", + "CMT_TOP_IMUX4_2", + "CMT_TOP_WW2A1_7", + "CMT_PHASER_IN_CA_TESTIN0", + "CMT_PHASER_IN_CA_SYSCLK", + "CMT_TOP_NW4END0_0", + "CMT_TOP_SW4END0_8", + "CMT_TOP_IMUX0_6", + "CMT_PHASER_OUT_DB_DTSBUS1", + "CMT_TOP_WW4B0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WL1END0_4", + "CMT_TOP_FAN1_5", + "CMT_PHASER_OUT_CA_DIVIDERST", + "CMT_TOP_IMUX35_1", + "CMT_TOP_NE4C1_1", + "CMT_TOP_EE2A1_8", + "CMT_PHASER_IN_CA_TESTIN5", + "CMT_PHASER_IN_DB_STG1REGL3", + "CMT_TOP_WL1END0_5", + "CMT_PHASER_IN_DB_SCANCLK", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "CMT_PHASER_OUT_DB_DIVIDERST", + "CMT_TOP_WW2END2_2", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_IMUX20_1", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_FAN4_7", + "CMT_PHASER_OUT_DB_SCANCLK", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_IMUX36_6", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_WW2END0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_PHASER_OUT_CA_TESTIN5", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_WW4C3_0", + "CMT_TOP_EE4B3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_FAN4_3", + "CMT_TOP_WR1END3_2", + "CMT_PHASER_IN_CA_STG1REGR5", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_LH8_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_IMUX5_7", + "CMT_PHASER_OUT_CA_SCANOUT", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_SW4A3_8", + "CMT_PHASER_OUT_CA_RST", + "CMT_TOP_WW2A0_6", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_WW2A2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_WL1END2_1", + "CMT_PHASERA_DTSBUS0", + "CMT_TOP_IMUX29_7", + "CMT_TOP_NE4C0_0", + "CMT_TOP_NW2A2_1", + "CMT_TOP_WW2END0_4", + "CMT_TOP_EE4B0_4", + "CMT_PHASER_IN_CA_STG1LOAD", + "CMT_TOP_WR1END3_6", + "CMT_TOP_NE4C3_6", + "CMT_PHASERREF_DOWN_PHASEROUT_A", + "CMT_PHASER_B_TOMMCM_ICLK", + "CMT_TOP_OCLK_7", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_PHASER_IN_DB_BURSTPENDING", + "CMT_PHASER_IN_DB_SCANOUT", + "CMT_TOP_WW4B2_2", + "CMT_TOP_ER1BEG2_0", + "CMT_PHASER_IN_CA_SCANMODEB", + "CMT_TOP_NW4A2_3", + "CMT_PHASER_IN_CA_TESTOUT1", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_LH11_4", + "CMT_TOP_LH6_6", + "CMT_TOP_WW4C3_3", + "CMT_TOP_NW4END1_4", + "CMT_PHASER_IN_DB_TESTIN4", + "CMT_TOP_NW2A1_2", + "CMT_TOP_NW2A3_7", + "CMT_TOP_WW4END0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_TOP_FAN4_8", + "CMT_TOP_WW4END0_7", + "CMT_TOP_SW4A3_2", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_IMUX5_8", + "CMT_TOP_IMUX22_7", + "CMT_TOP_WR1END1_2", + "CMT_TOP_SW4A1_5", + "CMT_TOP_IMUX2_6", + "CMT_TOP_BYP4_8", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_IMUX32_6", + "CMT_TOP_SE4C3_5", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_NW2A2_6", + "CMT_TOP_IMUX15_4", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_EE4BEG0_5", + "CMT_PHASER_IN_CA_BURSTPENDING", + "CMT_TOP_WW4A1_0", + "CMT_TOP_BYP5_5", + "CMT_TOP_ICLK_1", + "CMT_TOP_EE2A3_6", + "CMT_TOP_IMUX0_1", + "CMT_TOP_BYP6_7", + "CMT_TOP_BYP0_6", + "CMT_PHASER_OUT_CA_TESTIN11", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_WW4B2_6", + "CMT_TOP_WL1END1_5", + "CMT_TOP_IMUX32_7", + "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "CMT_TOP_LH3_3", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_SW4A2_8", + "CMT_TOP_IMUX30_0", + "CMT_TOP_WL1END3_7", + "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "CMT_TOP_SW4A1_7", + "CMT_TOP_NW2A0_8", + "CMT_TOP_WW4C1_5", + "CMT_TOP_SW2A3_5", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_WW4END1_8", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_SW4A3_3", + "CMT_TOP_IMUX34_6", + "CMT_TOP_SW4A2_4", + "CMT_TOP_WW4A2_2", + "CMT_TOP_NE4C3_1", + "CMT_TOP_IMUX28_1", + "CMT_TOP_IMUX46_4", + "CMT_TOP_NW4A1_7", + "CMT_TOP_WW2END3_4", + "CMT_TOP_IMUX22_6", + "CMT_PHASER_IN_DB_RST", + "CMT_TOP_EE4B1_5", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_EE4B0_6", + "CMT_TOP_IMUX1_4", + "CMT_TOP_SW2A0_0", + "CMT_TOP_SW4A1_0", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_FAN2_2", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_IMUX33_4", + "CMT_PHASER_IN_CA_ICLKDIV", + "CMT_PHASER_OUT_CA_SCANIN", + "CMT_TOP_NW4A1_0", + "CMT_TOP_WW4B0_7", + "CMT_TOP_SE4C0_8", + "CMT_PHASER_BOT_ENCALIB1", + "CMT_TOP_IMUX32_8", + "CMT_TOP_NW4END2_6", + "CMT_TOP_CLK1_4", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_EE2A2_4", + "CMT_TOP_EE2BEG1_3", + "CMT_LR_LOWER_T_CLK_IN1_HCLK", + "CMT_TOP_WW4B2_7", + "CMT_TOP_EE4B1_3", + "CMT_TOP_BYP5_0", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "CMT_PHASER_IN_B_ICLK", + "CMT_TOP_SW4END0_0", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH10_2", + "CMT_TOP_IMUX4_8", + "CMT_TOP_NE4C1_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "CMT_TOP_WW2A1_1", + "CMT_TOP_WW4END1_1", + "CMT_TOP_EE4A1_0", + "CMT_TOP_IMUX37_0", + "CMT_TOP_WL1END3_1", + "CMT_PHASER_IN_DB_MEMREFCLK", + "CMT_TOP_IMUX16_8", + "CMT_TOP_IMUX9_6", + "CMT_TOP_IMUX42_3", + "CMT_PHASER_OUT_DB_TESTIN15", + "CMT_PHASER_OUT_DB_OSERDESRST", + "CMT_TOP_IMUX39_2", + "CMT_TOP_WR1END0_6", + "CMT_TOP_IMUX37_7", + "CMT_TOP_IMUX16_3", + "CMT_PHASER_IN_DB_STG1LOAD", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_PHASER_IN_CA_ENCALIBPHY1", + "CMT_TOP_IMUX1_2", + "CMT_PHASER_IN_CA_EDGEADV", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_TOP_IMUX6_6", + "CMT_TOP_IMUX22_2", + "CMT_PHASER_OUT_CA_DTSBUS1", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_WW4B2_4", + "CMT_TOP_ER1BEG2_2", + "MMCM_CLK_FREQBB_REBUFOUT2", + "CMT_TOP_SE4C3_6", + "CMT_TOP_IMUX44_4", + "CMT_PHASER_IN_DB_STG1REGR4", + "CMT_LR_LOWER_T_CLK_MMCM4", + "CMT_TOP_IMUX17_7", + "CMT_TOP_CTRL0_1", + "CMT_TOP_CTRL0_8", + "CMT_TOP_WW4B2_0", + "CMT_TOP_MONITOR_P_6", + "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "CMT_PHASER_IN_CA_TESTOUT2", + "CMT_TOP_LH12_5", + "CMT_PHASER_IN_DB_RSTDQSFIND", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "CMT_TOP_IMUX12_6", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_IMUX23_4", + "CMT_TOP_IMUX29_2", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_BYP6_1", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_NE4BEG1_5", + "CMT_PHASER_IN_CA_PHASEREFCLK", + "CMT_TOP_FAN1_4", + "CMT_TOP_NE2A3_6", + "CMT_TOP_IMUX38_3", + "CMT_TOP_ICLK_3", + "CMT_TOP_WW2A0_5", + "CMT_TOP_NE2A1_3", + "CMT_TOP_IMUX7_4", + "CMT_TOP_CLK0_4", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_SE2A3_4", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_IMUX28_6", + "CMT_PHASER_B_ICLKDIV_TOIOI", + "CMT_TOP_WW4A3_8", + "CMT_TOP_EE2A0_0", + "CMT_TOP_SE2A1_0", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_TOP_NW2A0_3", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_SE2A1_5", + "CMT_TOP_WW4B1_2", + "CMT_TOP_CTRL1_3", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "CMT_TOP_EE4A3_8", + "CMT_TOP_NW4A0_2", + "CMT_TOP_NW4A1_8", + "CMT_TOP_IMUX26_5", + "CMT_TOP_IMUX40_6", + "CMT_TOP_LH6_3", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_WR1END2_4", + "CMT_TOP_NW4END3_2", + "CMT_TOP_IMUX39_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_IMUX20_4", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_LR_LOWER_T_CLK_PERF3", + "CMT_TOP_NW4END0_7", + "CMT_TOP_WW4END2_7", + "CMT_TOP_BYP4_7", + "CMT_PHASER_DOWN_PHASERREF0", + "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_PHASER_OUT_DB_FINEINC", + "CMT_TOP_NE2A2_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "CMT_TOP_SW4END0_4", + "CMT_TOP_CTRL1_2", + "CMT_TOP_WW4END2_2", + "CMT_TOP_IMUX34_0", + "CMT_TOP_NE2A1_6", + "CMT_TOP_SW2A3_1", + "CMT_TOP_IMUX38_2", + "CMT_TOP_BYP3_7", + "CMT_TOP_LH3_0", + "CMT_TOP_IMUX0_8", + "CMT_TOP_IMUX31_6", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_TOP_WW4END3_7", + "CMT_TOP_NE4BEG2_6", + "CMT_PHASER_IN_CA_FINEOVERFLOW", + "CMT_TOP_OCLK_3", + "CMT_PHASER_BOT_IBURSTPENDING1", + "CMT_TOP_FAN1_2", + "CMT_PHASER_OUT_CA_TESTOUT1", + "CMT_TOP_IMUX11_2", + "CMT_TOP_SW4A0_1", + "CMT_TOP_SW4A0_5", + "CMT_TOP_EE4B2_3", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "CMT_TOP_IMUX9_7", + "CMT_TOP_NE2A2_1", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_EE2A2_3", + "CMT_TOP_WR1END3_1", + "CMT_TOP_SW2A1_5", + "CMT_TOP_WW2A0_0", + "CMT_TOP_WR1END0_5", + "CMT_TOP_CTRL1_8", + "CMT_TOP_ER1BEG2_8", + "CMT_TOP_NW4A2_5", + "CMT_TOP_NW4A0_0", + "CMT_PHASER_OUT_CA_SYSCLK", + "CMT_PHASER_IN_DB_STG1REGL1", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_IMUX41_1", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX11_7", + "CMT_TOP_NW4A0_8", + "CMT_TOP_WW4B2_5", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "CMT_TOP_IMUX41_8", + "CMT_TOP_SW2A3_8", + "CMT_TOP_IMUX14_3", + "CMT_TOP_IMUX17_1", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_WW4A2_4", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_WW4B3_6", + "CMT_TOP_WW4END3_8", + "CMT_TOP_IMUX4_1", + "CMT_TOP_NE4BEG0_6", + "CMT_PHASER_BOT_ENCALIB0", + "CMT_TOP_IMUX23_1", + "CMT_TOP_BYP7_2", + "CMT_TOP_NW4A0_3", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_TOP_IMUX33_2", + "CMT_TOP_EE2A0_2", + "CMT_PHASER_IN_A_WREN_TOFIFO", + "CMT_PHASER_IN_DB_FREQREFCLK", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_PHASER_IN_CA_STG1REGR0", + "CMT_TOP_WW2END2_8", + "CMT_TOP_NE2A0_7", + "CMT_TOP_WW4END3_3", + "CMT_TOP_LH2_6", + "CMT_PHASER_OUT_DB_SYSCLK", + "CMT_TOP_BYP0_7", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_BYP2_8", + "CMT_PHASER_BOT_IBURSTPENDING0", + "CMT_TOP_WW4A0_0", + "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "CMT_TOP_NE2A1_7", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_PHASER_IN_CA_TESTIN1", + "CMT_TOP_WR1END3_5", + "CMT_TOP_SE4BEG1_3", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_WW4END3_2", + "CMT_TOP_WL1END3_3", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_IMUX34_8", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_NW4A3_8", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_CTRL0_7", + "CMT_TOP_WW4C0_5", + "CMT_TOP_IMUX13_1", + "CMT_TOP_IMUX11_1", + "CMT_TOP_IMUX8_7", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_NE2A0_1", + "CMT_TOP_WW4END0_0", + "CMT_TOP_SE2A2_3", + "CMT_TOP_FAN5_2", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_IMUX39_8", + "CMT_TOP_NE2A3_4", + "CMT_TOP_NE4C1_2", + "CMT_TOP_EE4C2_6", + "CMT_TOP_SW2A0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_IMUX30_4", + "CMT_PHASER_DOWN_DQS_TO_PHASER_B", + "CMT_TOP_CTRL1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_PHASER_IN_CA_MEMREFCLK", + "CMT_TOP_LH8_5", + "CMT_TOP_EE4C3_4", + "CMT_TOP_BYP1_5", + "CMT_TOP_IMUX10_8", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_PHASER_B_TOMMCM_OCLK1X_90", + "CMT_TOP_MONITOR_N_3", + "CMT_PHASER_OUT_CA_TESTIN12", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_IMUX44_8", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_WL1END3_6", + "CMT_TOP_WL1END0_3", + "CMT_LR_LOWER_T_CLK_IN3_HCLK", + "CMT_TOP_LH1_1", + "CMT_TOP_IMUX19_4", + "CMT_TOP_IMUX18_8", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_IMUX4_7", + "CMT_PHASER_IN_CA_COUNTERREADEN", + "CMT_PHASERA_CTSBUS0", + "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "CMT_PHASER_B_ICLK_TOIOI", + "CMT_TOP_IMUX24_4", + "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "CMT_LR_LOWER_T_CLK_PERF1", + "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "CMT_TOP_LH7_4", + "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_IMUX19_1", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_NW4A3_5", + "CMT_TOP_FAN2_8", + "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "CMT_PHASER_IN_CA_ICLK", + "CMT_TOP_NW4END0_3", + "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "CMT_TOP_IMUX29_4", + "CMT_TOP_SE4C2_7", + "CMT_TOP_NW2A0_6", + "CMT_TOP_SE2A2_2", + "CMT_TOP_WW4C2_7", + "CMT_TOP_WW4C0_4", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH7_2", + "CMT_TOP_EE4BEG3_4", + "CMT_TOP_IMUX13_6", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "CMT_TOP_WW4A2_1", + "CMT_TOP_IMUX1_1", + "CMT_TOP_LH10_3", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_WW4C3_2", + "CMT_TOP_LH3_8", + "CMT_PHASERREF_DOWN_PHASEROUT_B", + "CMT_TOP_IMUX38_5", + "CMT_TOP_IMUX8_8", + "CMT_TOP_EE4C3_3", + "CMT_TOP_SW4A0_0", + "CMT_TOP_IMUX47_7", + "CMT_TOP_SW2A1_8", + "CMT_TOP_FAN4_6", + "CMT_TOP_EE2A1_1", + "CMT_TOP_IMUX46_0", + "CMT_TOP_IMUX3_0", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_EE4C2_0", + "CMT_TOP_IMUX16_1", + "CMT_TOP_SW4END2_5", + "CMT_TOP_FAN6_3", + "CMT_TOP_FAN7_8", + "CMT_TOP_IMUX16_0", + "CMT_TOP_EE2A1_0", + "CMT_TOP_EE4B0_0", + "CMT_TOP_NW4END0_4", + "CMT_TOP_IMUX12_7", + "CMT_PHASER_IN_DB_ENCALIB1", + "CMT_PHASER_IN_CA_COUNTERLOADEN", + "CMT_TOP_IMUX47_5", + "CMT_TOP_WR1END1_3", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_IMUX34_5", + "CMT_TOP_IMUX31_5", + "CMT_PHASER_OUT_CA_DQSBUS1", + "CMT_TOP_IMUX0_7", + "CMT_TOP_IMUX2_1", + "CMT_TOP_IMUX31_2", + "CMT_TOP_ER1BEG3_8" + ], + "pips": { + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B6_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { + "src_wire": "CMT_TOP_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_4->CMT_PHASER_OUT_DB_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX23_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B16_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS0->CMT_PHASERA_CTSBUS0": { + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_CTSBUS0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX45_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLK->>CMT_PHASER_B_ICLK_TOIOI": { + "src_wire": "CMT_PHASER_IN_B_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT0->>MMCM_CLK_FREQBB_REBUFOUT0": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX31_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_8": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { + "src_wire": "CMT_TOP_IMUX14_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING1->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { + "src_wire": "CMT_PHASER_BOT_IBURSTPENDING1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX44_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { + "src_wire": "CMT_TOP_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_4->CMT_PHASER_IN_CA_RANKSEL0": { + "src_wire": "CMT_TOP_IMUX27_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { + "src_wire": "CMT_TOP_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX20_4->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { + "src_wire": "CMT_TOP_IMUX20_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX46_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { + "src_wire": "CMT_TOP_IMUX46_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV->>CMT_PHASER_B_OCLKDIV_TOIOI": { + "src_wire": "CMT_PHASER_OUT_B_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS0->CMT_PHASERA_DQSBUS0": { + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DQSBUS0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B14_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT3->>MMCM_CLK_FREQBB_REBUFOUT3": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { + "src_wire": "CMT_TOP_IMUX15_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B16_6": { + "src_wire": "CMT_PHASER_IN_DB_DQSFOUND", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_5->CMT_PHASER_OUT_DB_FINEINC": { + "src_wire": "CMT_TOP_IMUX13_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_IN_CA_SYNCIN": { + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_A->CMT_PHASER_OUT_CA_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_B_OCLK": { + "src_wire": "CMT_PHASER_OUT_DB_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { + "src_wire": "CMT_TOP_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX29_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_5": { + "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS1->CMT_PHASERA_DQSBUS1": { + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DQSBUS1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_B_ICLK": { + "src_wire": "CMT_PHASER_IN_DB_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_ICLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B16_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_EDGEADV": { + "src_wire": "CMT_TOP_IMUX34_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX14_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_DQS_TO_PHASER_B->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_DQS_TO_PHASER_B", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX8_3->CMT_PHASER_IN_CA_RSTDQSFIND": { + "src_wire": "CMT_TOP_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_6->CMT_PHASER_IN_DB_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_5->CMT_PHASER_OUT_DB_COARSEINC": { + "src_wire": "CMT_TOP_IMUX45_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { + "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_A_WREN_TOFIFO": { + "src_wire": "CMT_PHASER_IN_CA_WRENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_WREN_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_6->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX29_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B15_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_A_ICLK": { + "src_wire": "CMT_PHASER_IN_CA_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_ICLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKA1->CMT_PHASER_IN_CA_RANKSELPHY1": { + "src_wire": "CMT_PHASER_BOT_IRANKA1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_8->>CMT_BOT_HCLKMUX_CLKINT_0": { + "src_wire": "CMT_TOP_CLK0_8", + "is_pseudo": "0", + "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_DQS_TO_PHASER_A->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_DQS_TO_PHASER_A", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_IN_DB_SYNCIN": { + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_OUT_CA_SYNCIN": { + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_1->CMT_PHASER_OUT_CA_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO->CMT_PHASER_IN_A_ICLKDIV": { + "src_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_ICLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_B_WREN_TOFIFO": { + "src_wire": "CMT_PHASER_IN_DB_WRENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_WREN_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_B->CMT_PHASER_IN_DB_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_A->CMT_PHASER_IN_CA_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ICLKDIV->CMT_PHASER_IN_A_WRCLK_TOFIFO": { + "src_wire": "CMT_PHASER_IN_CA_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_B->CMT_PHASER_OUT_DB_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_0": { + "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX19_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_5->CMT_PHASER_OUT_DB_RST": { + "src_wire": "CMT_TOP_IMUX47_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX39_4->CMT_PHASER_OUT_DB_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX39_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX27_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->CMT_PHASER_B_TOMMCM_OCLK": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK->>CMT_PHASER_B_OCLK_TOIOI": { + "src_wire": "CMT_PHASER_OUT_B_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_4": { + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_4": { + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_7->CMT_PHASER_IN_DB_RST": { + "src_wire": "CMT_TOP_IMUX47_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLKDIV->>CMT_PHASER_B_ICLKDIV_TOIOI": { + "src_wire": "CMT_PHASER_IN_B_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX43_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX43_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX30_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_4": { + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B3_6": { + "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B16_3": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLKDIV->CMT_PHASER_OUT_B_RDCLK_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { + "src_wire": "CMT_TOP_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_2": { + "src_wire": "CMT_PHASER_IN_CA_DQSFOUND", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_OUT_DB_SYNCIN": { + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B18_4": { + "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO->CMT_PHASER_IN_B_ICLKDIV": { + "src_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_ICLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B21_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { + "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_A_OCLK1X_90": { + "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_OCLK1X_90", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_4": { + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_5->CMT_PHASER_OUT_DB_COARSEENABLE": { + "src_wire": "CMT_TOP_IMUX14_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_7->CMT_PHASER_IN_DB_RANKSEL1": { + "src_wire": "CMT_TOP_IMUX31_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_A_RDCLK_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_B_OCLK1X_90": { + "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_OCLK1X_90", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_2->CMT_PHASER_IN_CA_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B14_0": { + "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX28_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX32_2->CMT_PHASER_OUT_CA_FINEINC": { + "src_wire": "CMT_TOP_IMUX32_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B2_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_5->CMT_PHASER_OUT_DB_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX29_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_6->CMT_PHASER_IN_DB_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX23_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_7->CMT_PHASER_IN_DB_RSTDQSFIND": { + "src_wire": "CMT_TOP_IMUX0_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX25_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { + "src_wire": "CMT_TOP_IMUX25_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->CMT_PHASER_B_TOMMCM_ICLKDIV": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_ICLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX30_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_6->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX13_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_B_RCLK1": { + "src_wire": "CMT_PHASER_IN_DB_RCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_RCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B6_3": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_2": { + "src_wire": "CMT_PHASER_IN_CA_ISERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_3": { + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_4": { + "src_wire": "CMT_PHASER_B_OCLK90_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->CMT_PHASER_B_TOMMCM_OCLKDIV": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_OCLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX12_4->CMT_PHASER_IN_CA_RST": { + "src_wire": "CMT_TOP_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX21_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_6->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX44_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX12_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX12_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO->CMT_PHASER_OUT_B_OCLKDIV": { + "src_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_OCLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B3_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_5->CMT_PHASER_OUT_DB_EDGEADV": { + "src_wire": "CMT_TOP_IMUX30_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B23_1": { + "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B15_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90->>CMT_PHASER_B_OCLK90_TOIOI": { + "src_wire": "CMT_PHASER_OUT_B_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_OCLK90_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_6": { + "src_wire": "CMT_PHASER_IN_DB_ISERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { + "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX19_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX45_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT1->>MMCM_CLK_FREQBB_REBUFOUT1": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_A_OCLK": { + "src_wire": "CMT_PHASER_OUT_CA_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX25_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { + "src_wire": "CMT_TOP_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS0->CMT_PHASERA_DTSBUS0": { + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DTSBUS0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_A_RCLK0": { + "src_wire": "CMT_PHASER_IN_CA_RCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_RCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { + "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_CA_RCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX11_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX11_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_FINEINC": { + "src_wire": "CMT_TOP_IMUX14_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING1->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { + "src_wire": "CMT_PHASER_BOT_OBURSTPENDING1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_CLK1_8->>CMT_BOT_HCLKMUX_CLKINT_1": { + "src_wire": "CMT_TOP_CLK1_8", + "is_pseudo": "0", + "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_6->CMT_PHASER_IN_DB_FINEINC": { + "src_wire": "CMT_TOP_IMUX47_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { + "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B1_3": { + "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKA0->CMT_PHASER_IN_CA_RANKSELPHY0": { + "src_wire": "CMT_PHASER_BOT_IRANKA0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_3": { + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { + "src_wire": "CMT_TOP_IMUX15_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { + "src_wire": "CMT_TOP_IMUX41_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { + "src_wire": "CMT_TOP_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_B_WRCLK_TOFIFO": { + "src_wire": "CMT_PHASER_IN_DB_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_8": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS1->CMT_PHASERA_CTSBUS1": { + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_CTSBUS1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKB0->CMT_PHASER_IN_DB_RANKSELPHY0": { + "src_wire": "CMT_PHASER_BOT_IRANKB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX43_4->CMT_PHASER_IN_CA_RANKSEL1": { + "src_wire": "CMT_TOP_IMUX43_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING0->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { + "src_wire": "CMT_PHASER_BOT_OBURSTPENDING0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKB1->CMT_PHASER_IN_DB_RANKSELPHY1": { + "src_wire": "CMT_PHASER_BOT_IRANKB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING0->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { + "src_wire": "CMT_PHASER_BOT_IBURSTPENDING0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->CMT_PHASER_B_TOMMCM_ICLK": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_ICLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { + "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_DB_RCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX0_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO->CMT_PHASER_OUT_A_OCLKDIV": { + "src_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_OCLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS1->CMT_PHASERA_DTSBUS1": { + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DTSBUS1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX14_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_A_RDEN_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_CA_RDENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_RDEN_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B10_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B16_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT2->>MMCM_CLK_FREQBB_REBUFOUT2": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX44_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_RDENABLE->CMT_PHASER_OUT_B_RDEN_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_DB_RDENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_RDEN_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CMT_TOP_L_UPPER_B.json b/kintex7/tile_type_CMT_TOP_L_UPPER_B.json new file mode 100644 index 0000000..8ee51a9 --- /dev/null +++ b/kintex7/tile_type_CMT_TOP_L_UPPER_B.json @@ -0,0 +1,6524 @@ +{ + "tile_type": "CMT_TOP_L_UPPER_B", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "PHASER_REF", + "type": "PHASER_REF", + "site_pins": { + "TESTIN1": "CMT_PHASER_REF_TESTIN1", + "TESTOUT3": "CMT_PHASER_REF_TESTOUT3", + "TESTOUT7": "CMT_PHASER_REF_TESTOUT7", + "TESTOUT5": "CMT_PHASER_REF_TESTOUT5", + "TESTIN4": "CMT_PHASER_REF_TESTIN4", + "TESTIN7": "CMT_PHASER_REF_TESTIN7", + "RST": "CMT_PHASER_REF_RST", + "TESTIN2": "CMT_PHASER_REF_TESTIN2", + "TMUXOUT": "CMT_PHASER_REF_TMUXOUT", + "TESTIN6": "CMT_PHASER_REF_TESTIN6", + "TESTOUT4": "CMT_PHASER_REF_TESTOUT4", + "TESTOUT0": "CMT_PHASER_REF_TESTOUT0", + "TESTOUT1": "CMT_PHASER_REF_TESTOUT1", + "LOCKED": "CMT_PHASER_REF_LOCKED", + "PWRDWN": "CMT_PHASER_REF_PWRDWN", + "CLKIN": "CMT_PHASER_REF_CLKIN", + "TESTIN0": "CMT_PHASER_REF_TESTIN0", + "TESTOUT6": "CMT_PHASER_REF_TESTOUT6", + "TESTIN3": "CMT_PHASER_REF_TESTIN3", + "TESTOUT2": "CMT_PHASER_REF_TESTOUT2", + "TESTIN5": "CMT_PHASER_REF_TESTIN5", + "CLKOUT": "CMT_PHASER_REF_CLKOUT" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "PHY_CONTROL", + "type": "PHY_CONTROL", + "site_pins": { + "PHYCTLWD20": "CMT_PHY_CONTROL_PHYCTLWD20", + "PHYCTLWD11": "CMT_PHY_CONTROL_PHYCTLWD11", + "PHYCTLWRENABLE": "CMT_PHY_CONTROL_PHYCTLWRENABLE", + "OUTBURSTPENDING0": "CMT_PHY_CONTROL_OUTBURSTPENDING0", + "PHYCTLWD8": "CMT_PHY_CONTROL_PHYCTLWD8", + "TESTOUTPUT1": "CMT_PHY_CONTROL_TESTOUTPUT1", + "PHYCTLWD22": "CMT_PHY_CONTROL_PHYCTLWD22", + "TESTINPUT13": "CMT_PHY_CONTROL_TESTINPUT13", + "PHYCTLEMPTY": "CMT_PHY_CONTROL_PHYCTLEMPTY", + "TESTSELECT2": "CMT_PHY_CONTROL_TESTSELECT2", + "PHYCTLMSTREMPTY": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", + "PHYCTLWD13": "CMT_PHY_CONTROL_PHYCTLWD13", + "TESTINPUT7": "CMT_PHY_CONTROL_TESTINPUT7", + "AUXOUTPUT2": "CMT_PHY_CONTROL_AUXOUTPUT2", + "PHYCTLWD0": "CMT_PHY_CONTROL_PHYCTLWD0", + "TESTINPUT15": "CMT_PHY_CONTROL_TESTINPUT15", + "TESTINPUT8": "CMT_PHY_CONTROL_TESTINPUT8", + "PHYCTLWD4": "CMT_PHY_CONTROL_PHYCTLWD4", + "PLLLOCK": "CMT_PHY_CONTROL_PLLLOCK", + "PHYCTLALMOSTFULL": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", + "PHYCTLREADY": "CMT_PHY_CONTROL_PHYCTLREADY", + "TESTINPUT3": "CMT_PHY_CONTROL_TESTINPUT3", + "PHYCTLWD29": "CMT_PHY_CONTROL_PHYCTLWD29", + "PHYCTLWD21": "CMT_PHY_CONTROL_PHYCTLWD21", + "INRANKA1": "CMT_PHY_CONTROL_INRANKA1", + "TESTOUTPUT8": "CMT_PHY_CONTROL_TESTOUTPUT8", + "TESTOUTPUT11": "CMT_PHY_CONTROL_TESTOUTPUT11", + "TESTOUTPUT14": "CMT_PHY_CONTROL_TESTOUTPUT14", + "TESTSELECT0": "CMT_PHY_CONTROL_TESTSELECT0", + "PCENABLECALIB1": "CMT_PHY_CONTROL_PCENABLECALIB1", + "PHYCTLWD5": "CMT_PHY_CONTROL_PHYCTLWD5", + "TESTOUTPUT3": "CMT_PHY_CONTROL_TESTOUTPUT3", + "PHYCTLWD17": "CMT_PHY_CONTROL_PHYCTLWD17", + "TESTOUTPUT5": "CMT_PHY_CONTROL_TESTOUTPUT5", + "INBURSTPENDING2": "CMT_PHY_CONTROL_INBURSTPENDING2", + "TESTINPUT12": "CMT_PHY_CONTROL_TESTINPUT12", + "WRITECALIBENABLE": "CMT_PHY_CONTROL_WRITECALIBENABLE", + "INRANKD1": "CMT_PHY_CONTROL_INRANKD1", + "TESTOUTPUT6": "CMT_PHY_CONTROL_TESTOUTPUT6", + "PHYCTLWD15": "CMT_PHY_CONTROL_PHYCTLWD15", + "PHYCTLWD26": "CMT_PHY_CONTROL_PHYCTLWD26", + "MEMREFCLK": "CMT_PHY_CONTROL_MEMREFCLK", + "PHYCTLWD7": "CMT_PHY_CONTROL_PHYCTLWD7", + "TESTINPUT0": "CMT_PHY_CONTROL_TESTINPUT0", + "TESTINPUT11": "CMT_PHY_CONTROL_TESTINPUT11", + "PHYCTLWD28": "CMT_PHY_CONTROL_PHYCTLWD28", + "INBURSTPENDING1": "CMT_PHY_CONTROL_INBURSTPENDING1", + "REFDLLLOCK": "CMT_PHY_CONTROL_REFDLLLOCK", + "PHYCTLWD19": "CMT_PHY_CONTROL_PHYCTLWD19", + "TESTOUTPUT4": "CMT_PHY_CONTROL_TESTOUTPUT4", + "AUXOUTPUT1": "CMT_PHY_CONTROL_AUXOUTPUT1", + "TESTOUTPUT13": "CMT_PHY_CONTROL_TESTOUTPUT13", + "PHYCTLWD6": "CMT_PHY_CONTROL_PHYCTLWD6", + "PCENABLECALIB0": "CMT_PHY_CONTROL_PCENABLECALIB0", + "TESTINPUT2": "CMT_PHY_CONTROL_TESTINPUT2", + "TESTINPUT6": "CMT_PHY_CONTROL_TESTINPUT6", + "PHYCTLWD9": "CMT_PHY_CONTROL_PHYCTLWD9", + "PHYCTLWD23": "CMT_PHY_CONTROL_PHYCTLWD23", + "TESTOUTPUT12": "CMT_PHY_CONTROL_TESTOUTPUT12", + "TESTOUTPUT10": "CMT_PHY_CONTROL_TESTOUTPUT10", + "TESTINPUT4": "CMT_PHY_CONTROL_TESTINPUT4", + "TESTINPUT10": "CMT_PHY_CONTROL_TESTINPUT10", + "TESTOUTPUT2": "CMT_PHY_CONTROL_TESTOUTPUT2", + "RESET": "CMT_PHY_CONTROL_RESET", + "TESTINPUT9": "CMT_PHY_CONTROL_TESTINPUT9", + "TESTINPUT14": "CMT_PHY_CONTROL_TESTINPUT14", + "AUXOUTPUT0": "CMT_PHY_CONTROL_AUXOUTPUT0", + "INRANKB0": "CMT_PHY_CONTROL_INRANKB0", + "PHYCTLWD30": "CMT_PHY_CONTROL_PHYCTLWD30", + "SYNCIN": "CMT_PHY_CONTROL_SYNCIN", + "PHYCTLFULL": "CMT_PHY_CONTROL_PHYCTLFULL", + "TESTOUTPUT0": "CMT_PHY_CONTROL_TESTOUTPUT0", + "TESTINPUT1": "CMT_PHY_CONTROL_TESTINPUT1", + "PHYCTLWD14": "CMT_PHY_CONTROL_PHYCTLWD14", + "INBURSTPENDING3": "CMT_PHY_CONTROL_INBURSTPENDING3", + "PHYCLK": "CMT_PHY_CONTROL_PHYCLK", + "TESTOUTPUT9": "CMT_PHY_CONTROL_TESTOUTPUT9", + "PHYCTLWD31": "CMT_PHY_CONTROL_PHYCTLWD31", + "PHYCTLWD25": "CMT_PHY_CONTROL_PHYCTLWD25", + "PHYCTLWD24": "CMT_PHY_CONTROL_PHYCTLWD24", + "SCANENABLEN": "CMT_PHY_CONTROL_SCANENABLEN", + "PHYCTLWD2": "CMT_PHY_CONTROL_PHYCTLWD2", + "TESTINPUT5": "CMT_PHY_CONTROL_TESTINPUT5", + "OUTBURSTPENDING2": "CMT_PHY_CONTROL_OUTBURSTPENDING2", + "PHYCTLWD16": "CMT_PHY_CONTROL_PHYCTLWD16", + "TESTOUTPUT15": "CMT_PHY_CONTROL_TESTOUTPUT15", + "INRANKC0": "CMT_PHY_CONTROL_INRANKC0", + "INRANKD0": "CMT_PHY_CONTROL_INRANKD0", + "READCALIBENABLE": "CMT_PHY_CONTROL_READCALIBENABLE", + "INRANKA0": "CMT_PHY_CONTROL_INRANKA0", + "PHYCTLWD1": "CMT_PHY_CONTROL_PHYCTLWD1", + "OUTBURSTPENDING3": "CMT_PHY_CONTROL_OUTBURSTPENDING3", + "TESTOUTPUT7": "CMT_PHY_CONTROL_TESTOUTPUT7", + "PHYCTLWD3": "CMT_PHY_CONTROL_PHYCTLWD3", + "PHYCTLWD27": "CMT_PHY_CONTROL_PHYCTLWD27", + "PHYCTLWD12": "CMT_PHY_CONTROL_PHYCTLWD12", + "PHYCTLWD10": "CMT_PHY_CONTROL_PHYCTLWD10", + "INRANKC1": "CMT_PHY_CONTROL_INRANKC1", + "OUTBURSTPENDING1": "CMT_PHY_CONTROL_OUTBURSTPENDING1", + "INRANKB1": "CMT_PHY_CONTROL_INRANKB1", + "PHYCTLWD18": "CMT_PHY_CONTROL_PHYCTLWD18", + "AUXOUTPUT3": "CMT_PHY_CONTROL_AUXOUTPUT3", + "TESTSELECT1": "CMT_PHY_CONTROL_TESTSELECT1", + "INBURSTPENDING0": "CMT_PHY_CONTROL_INBURSTPENDING0" + }, + "x_coord": 0 + }, + { + "y_coord": 5, + "name": "X0Y5", + "prefix": "PHASER_OUT_PHY", + "type": "PHASER_OUT_PHY", + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", + "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", + "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", + "RST": "CMT_PHASER_OUT_CA_RST", + "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", + "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", + "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", + "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", + "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", + "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", + "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", + "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", + "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", + "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", + "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", + "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", + "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", + "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", + "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", + "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", + "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", + "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", + "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", + "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", + "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", + "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", + "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", + "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", + "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", + "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", + "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", + "OCLK": "CMT_PHASER_OUT_CA_OCLK", + "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", + "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", + "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3", + "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", + "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", + "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", + "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3" + }, + "x_coord": 0 + }, + { + "y_coord": 5, + "name": "X0Y5", + "prefix": "PHASER_IN_PHY", + "type": "PHASER_IN_PHY", + "site_pins": { + "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", + "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE", + "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", + "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", + "RST": "CMT_PHASER_IN_CA_RST", + "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", + "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", + "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", + "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_IN_CA_FINEINC", + "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", + "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", + "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", + "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", + "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", + "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", + "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", + "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", + "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", + "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", + "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", + "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", + "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", + "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", + "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", + "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", + "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", + "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", + "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", + "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", + "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "STG1READ": "CMT_PHASER_IN_CA_STG1READ", + "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", + "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", + "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", + "SCANENB": "CMT_PHASER_IN_CA_SCANENB", + "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", + "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", + "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", + "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", + "SCANIN": "CMT_PHASER_IN_CA_SCANIN", + "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", + "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", + "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", + "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", + "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", + "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", + "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST", + "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", + "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", + "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", + "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", + "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", + "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", + "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", + "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", + "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", + "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", + "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", + "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", + "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1", + "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", + "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", + "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", + "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", + "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", + "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", + "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", + "ICLK": "CMT_PHASER_IN_CA_ICLK", + "RCLK": "CMT_PHASER_IN_CA_RCLK" + }, + "x_coord": 0 + }, + { + "y_coord": 6, + "name": "X0Y6", + "prefix": "PHASER_OUT_PHY", + "type": "PHASER_OUT_PHY", + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_DB_COARSEINC", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", + "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", + "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", + "RST": "CMT_PHASER_OUT_DB_RST", + "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", + "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", + "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", + "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", + "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", + "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", + "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", + "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", + "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE", + "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", + "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", + "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", + "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", + "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "COARSEENABLE": "CMT_PHASER_OUT_DB_COARSEENABLE", + "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", + "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", + "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", + "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", + "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", + "COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", + "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", + "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", + "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", + "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", + "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", + "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", + "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", + "OCLK": "CMT_PHASER_OUT_DB_OCLK", + "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", + "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", + "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3", + "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING", + "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", + "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", + "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3" + }, + "x_coord": 0 + }, + { + "y_coord": 6, + "name": "X0Y6", + "prefix": "PHASER_IN_PHY", + "type": "PHASER_IN_PHY", + "site_pins": { + "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", + "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE", + "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", + "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", + "RST": "CMT_PHASER_IN_DB_RST", + "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", + "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", + "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", + "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_IN_DB_FINEINC", + "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", + "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", + "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", + "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", + "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", + "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", + "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", + "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", + "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", + "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", + "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", + "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", + "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", + "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", + "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", + "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", + "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", + "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", + "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", + "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", + "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "STG1READ": "CMT_PHASER_IN_DB_STG1READ", + "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", + "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", + "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", + "SCANENB": "CMT_PHASER_IN_DB_SCANENB", + "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", + "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", + "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", + "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", + "SCANIN": "CMT_PHASER_IN_DB_SCANIN", + "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", + "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", + "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", + "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", + "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", + "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", + "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST", + "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", + "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", + "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", + "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", + "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", + "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", + "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", + "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", + "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", + "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", + "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", + "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", + "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1", + "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", + "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", + "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", + "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", + "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", + "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", + "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", + "ICLK": "CMT_PHASER_IN_DB_ICLK", + "RCLK": "CMT_PHASER_IN_DB_RCLK" + }, + "x_coord": 0 + } + ], + "wires": [ + "CMT_TOP_WR1END2_7", + "CMT_TOP_WW4C3_6", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_IMUX18_1", + "CMT_TOP_WL1END3_8", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX8_5", + "CMT_TOP_WW2END3_7", + "CMT_PHASER_IN_DB_EDGEADV", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_IMUX15_8", + "CMT_TOP_EE4B0_9", + "CMT_TOP_LH5_7", + "CMT_TOP_LOGIC_OUTS_L_B12_11", + "CMT_PHASER_IN_CA_TESTOUT0", + "CMT_TOP_SE4C2_0", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_FAN2_3", + "CMT_TOP_IMUX40_8", + "CMT_TOP_EE4C2_7", + "CMT_TOP_SE4BEG0_10", + "CMT_PHY_CONTROL_OUTBURSTPENDING0", + "CMT_TOP_NW2A1_4", + "CMT_TOP_ER1BEG2_3", + "CMT_PHY_CONTROL_IRANKC1", + "CMT_TOP_EE2A1_6", + "CMT_TOP_EE4A2_4", + "CMT_TOP_BYP1_4", + "CMT_PHASER_OUT_C_OCLK1X_90", + "CMT_TOP_EE4C0_3", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_SE4C1_4", + "CMT_TOP_IMUX23_5", + "CMT_PHASER_UP_PHASERREF0", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_IMUX34_7", + "CMT_TOP_IMUX25_10", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN5_3", + "CMT_TOP_NE4C2_2", + "CMT_TOP_EE4A2_5", + "CMT_TOP_IMUX35_5", + "CMT_TOP_EE2A0_1", + "CMT_TOP_SE4BEG3_10", + "CMT_PHASER_IN_CA_ENCALIBPHY0", + "CMT_TOP_FAN3_2", + "CMT_TOP_BYP2_11", + "CMT_TOP_EE2A2_1", + "CMT_TOP_SW4END2_10", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE2A2_5", + "CMT_PHASER_IN_CA_FREQREFCLK", + "CMT_TOP_WW2END0_3", + "CMT_TOP_SW4END3_9", + "CMT_PHY_CONTROL_PHYCTLWD2", + "CMT_TOP_IMUX16_11", + "CMT_TOP_ER1BEG1_0", + "CMT_R_PHASER_IN_C_WRCLK_FIFO", + "CMT_TOP_SE4C0_2", + "CMT_TOP_SE2A2_10", + "CMT_TOP_EE4B3_8", + "CMT_TOP_NW4A3_9", + "CMT_TOP_EE4A1_2", + "CMT_PHASER_OUT_DB_TESTIN2", + "CMT_TOP_IMUX31_4", + "CMT_TOP_EL1BEG3_5", + "CMT_PHY_CONTROL_WRITECALIBENABLE", + "CMT_PHASER_IN_CA_RCLK", + "CMT_TOP_SE4C3_11", + "CMT_PHASER_UP_PHASERREF1", + "CMT_TOP_NW4A3_4", + "CMT_TOP_WW4END1_2", + "CMT_PHASER_IN_DB_STG1REGR7", + "CMT_TOP_WW4B1_5", + "CMT_TOP_LOGIC_OUTS_L_B2_9", + "CMT_PHASER_OUT_CA_TESTIN0", + "CMT_TOP_IMUX12_5", + "CMT_PHASER_OUT_DB_COARSEINC", + "CMT_TOP_IMUX8_10", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_EE4A0_6", + "CMT_PHASER_OUT_CA_COARSEENABLE", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_NE4C3_9", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_SW2A0_11", + "CMT_TOP_WR1END0_2", + "CMT_TOP_NW4END1_8", + "CMT_TOP_SE2A0_8", + "CMT_TOP_LH11_2", + "CMT_TOP_EE4C3_2", + "CMT_TOP_IMUX2_7", + "CMT_TOP_LOGIC_OUTS_L_B7_11", + "CMT_TOP_EE2A1_7", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_ER1BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX16_6", + "CMT_TOP_LH6_2", + "CMT_PHASER_IN_DB_STG1REGL6", + "CMT_TOP_NE4BEG1_9", + "CMT_TOP_IMUX9_2", + "CMT_TOP_BYP5_1", + "CMT_PHASER_UP_BUFMRCE_CE0", + "CMT_TOP_WR1END1_7", + "CMT_TOP_WL1END1_1", + "CMT_TOP_EE2A3_11", + "CMT_PHASER_IN_DB_FINEINC", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_EE4A0_11", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX23_8", + "CMT_TOP_EE4C3_11", + "CMT_TOP_LOGIC_OUTS_L_B19_9", + "CMT_TOP_SW4END2_11", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_WW4B1_11", + "CMT_TOP_EL1BEG1_2", + "CMT_PHASER_OUT_CA_DQSBUS0", + "CMT_PHASER_IN_DB_RANKSEL0", + "CMT_TOP_WW4A2_11", + "CMT_PHASER_OUT_DB_DTSBUS0", + "CMT_TOP_NW4END3_0", + "CMT_TOP_ER1BEG1_8", + "CMT_PHASER_OUT_CA_TESTIN7", + "CMT_TOP_SE4BEG0_6", + "CMT_TOP_IMUX7_7", + "CMT_TOP_WL1END2_8", + "CMT_PHASER_OUT_CA_TESTIN14", + "CMT_TOP_NE4BEG1_8", + "CMT_PHASER_IN_DB_STG1REGL4", + "CMT_TOP_WW4C1_4", + "CMT_TOP_NE2A2_5", + "CMT_TOP_SE4C3_9", + "CMT_TOP_SW2A3_2", + "CMT_TOP_IMUX3_7", + "CMT_TOP_WW4A0_8", + "CMT_TOP_NW4END0_5", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_PHASER_IN_CA_STG1READ", + "CMT_PHY_CONTROL_TESTOUTPUT8", + "CMT_TOP_FAN5_1", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_SE4BEG2_10", + "CMT_TOP_IMUX9_9", + "CMT_PHY_CONTROL_PHYCTLWD30", + "CMT_TOP_IMUX31_9", + "CMT_TOP_FAN1_6", + "CMT_TOP_IMUX26_4", + "CMT_PHASER_UP_PHASERREF_BELOW0", + "CMT_TOP_IMUX3_2", + "CMT_TOP_LH9_11", + "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_LH4_2", + "CMT_TOP_EE4A1_8", + "CMT_PHASER_IN_DB_FINEENABLE", + "CMT_TOP_WW4END1_7", + "CMT_TOP_IMUX35_10", + "CMT_TOP_IMUX44_5", + "CMT_TOP_IMUX37_4", + "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "CMT_TOP_WW4C2_8", + "CMT_TOP_EE4A0_8", + "CMT_PHY_CONTROL_INBURSTPENDING3", + "CMT_TOP_WW4B3_1", + "CMT_TOP_EE4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_PHASER_IN_DB_TESTIN3", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "CMT_TOP_LOGIC_OUTS_L_B15_9", + "CMT_TOP_NE4BEG2_11", + "CMT_TOP_WW2END1_0", + "CMT_TOP_IMUX22_9", + "CMT_TOP_FAN3_11", + "CMT_TOP_IMUX13_3", + "CMT_TOP_WW4END1_4", + "CMT_TOP_IMUX14_11", + "CMT_TOP_EE4BEG0_9", + "CMT_PHASER_IN_CA_SCANENB", + "CMT_TOP_WR1END0_10", + "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "CMT_TOP_EE4C1_5", + "CMT_TOP_LH9_1", + "CMT_TOP_LH11_10", + "CMT_TOP_SE2A1_3", + "CMT_TOP_SE2A0_1", + "CMT_TOP_SE4C0_10", + "CMT_TOP_LH12_3", + "CMT_TOP_ER1BEG3_11", + "CMT_TOP_FAN7_4", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END2_5", + "CMT_TOP_WR1END2_9", + "CMT_TOP_FAN1_0", + "CMT_PHASER_REF_TESTOUT6", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_IMUX40_7", + "CMT_TOP_BYP7_8", + "CMT_PHASER_OUT_DB_CTSBUS0", + "CMT_TOP_NW4A3_0", + "CMT_TOP_WL1END2_4", + "CMT_TOP_IMUX0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_SW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_EE2A3_3", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW2A0_2", + "CMT_TOP_SW4END1_2", + "CMT_TOP_EE2A3_5", + "CMT_TOP_WR1END0_1", + "CMT_TOP_WW4C1_3", + "CMT_TOP_LH4_3", + "CMT_TOP_EE4B2_8", + "CMT_PHASER_OUT_CA_RDENABLE", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_IMUX5_2", + "CMT_TOP_EE2BEG1_6", + "CMT_PHASER_IN_CA_TESTIN13", + "CMT_TOP_EE4BEG3_3", + "CMT_R_TOP_UPPER_B_CLKPLL7", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NW4A0_6", + "CMT_TOP_EE2A1_10", + "CMT_TOP_EE4A3_5", + "CMT_TOP_LOGIC_OUTS_L_B8_10", + "CMT_TOP_IMUX14_0", + "CMT_TOP_LH7_5", + "CMT_PHY_CONTROL_MEMREFCLK", + "CMT_TOP_WW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_TOP_WW2END2_3", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WW2END3_8", + "CMT_TOP_NW4END1_0", + "CMT_PHASER_OUT_DB_SYNCIN", + "CMT_TOP_NE4C2_5", + "CMT_TOP_SE2A2_11", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "CMT_TOP_IMUX14_4", + "CMT_TOP_IMUX12_4", + "CMT_TOP_SW4END3_2", + "CMT_TOP_IMUX32_0", + "CMT_TOP_SE4BEG0_1", + "CMT_PHASER_REF_TESTIN5", + "CMT_TOP_IMUX44_6", + "CMT_PHY_CONTROL_PHYCTLWD29", + "CMT_TOP_IMUX40_9", + "CMT_TOP_SE2A3_3", + "CMT_TOP_ER1BEG0_11", + "CMT_TOP_FAN0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_NE2A3_10", + "CMT_PHASER_IN_CA_TESTIN2", + "CMT_TOP_WW4B3_2", + "CMT_TOP_LOGIC_OUTS_L_B3_10", + "CMT_TOP_FAN0_7", + "CMT_R_TOP_UPPER_B_CLKPLL6", + "CMT_TOP_WW4B0_3", + "CMT_TOP_LH11_8", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_PHASER_IN_CA_STG1REGR8", + "CMT_TOP_IMUX47_4", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_EE4A0_10", + "CMT_TOP_WW4C1_6", + "CMT_TOP_IMUX35_11", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_NW2A1_11", + "CMT_TOP_IMUX46_9", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_SW4END3_7", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_PHASER_IN_D_ICLK", + "CMT_TOP_NW4END3_6", + "CMT_TOP_EE2BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_PHY_CONTROL_TESTINPUT15", + "CMT_PHASER_IN_DB_PHASEREFCLK", + "CMT_TOP_ER1BEG1_11", + "CMT_TOP_IMUX45_6", + "CMT_TOP_WW4END2_8", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_WW4END1_0", + "CMT_TOP_LH3_2", + "CMT_TOP_IMUX1_9", + "CMT_TOP_IMUX8_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_IMUX2_8", + "CMT_TOP_BYP0_3", + "CMT_TOP_OCLK_5", + "CMT_TOP_NE4C0_10", + "CMT_TOP_WW2A2_2", + "CMT_TOP_IMUX20_7", + "CMT_TOP_IMUX25_4", + "CMT_TOP_NW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_WW4C0_3", + "CMT_TOP_IMUX28_5", + "CMT_TOP_NE2A0_2", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_BYP1_1", + "CMT_TOP_SE2A3_6", + "CMT_TOP_SW4A1_11", + "CMT_TOP_IMUX2_2", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX21_0", + "CMT_PHASER_IN_CA_SCANCLK", + "CMT_TOP_WW4END2_9", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_SE2A0_2", + "CMT_PHASER_OUT_DB_TESTIN9", + "CMT_TOP_IMUX43_1", + "CMT_TOP_EE4BEG1_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_IMUX28_8", + "CMT_TOP_WW4C3_4", + "CMT_TOP_SW4END0_9", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_LH8_1", + "CMT_TOP_NE2A0_11", + "CMT_TOP_WW2A3_2", + "CMT_TOP_NW4A0_7", + "CMT_TOP_LH9_5", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_IMUX6_7", + "CMT_PHASER_OUT_DB_COARSEENABLE", + "CMT_TOP_IMUX45_10", + "CMT_TOP_WR1END3_4", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "CMT_TOP_EE2A0_6", + "CMT_TOP_EE2BEG0_9", + "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "CMT_TOP_EE2A2_6", + "CMT_TOP_BYP2_2", + "CMT_PHASER_OUT_DB_EDGEADV", + "CMT_TOP_IMUX21_6", + "CMT_TOP_LOGIC_OUTS_L_B0_11", + "CMT_TOP_SE4C3_1", + "CMT_TOP_SW2A2_3", + "CMT_TOP_IMUX19_7", + "CMT_TOP_IMUX0_4", + "CMT_TOP_ICLK_9", + "CMT_TOP_SW4END2_7", + "CMT_TOP_WW4B3_9", + "CMT_TOP_IMUX15_0", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_PHASER_REF_TESTOUT4", + "CMT_TOP_EL1BEG2_9", + "CMT_PHASER_IN_DB_COUNTERLOADEN", + "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_WW4END2_5", + "CMT_TOP_WW2A1_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_IMUX9_8", + "CMT_TOP_WW2A1_9", + "PLL_CLK_FREQBB_REBUFOUT0", + "CMT_PHASER_IN_DB_ICLK", + "CMT_TOP_SW4A0_4", + "CMT_TOP_BYP0_11", + "CMT_TOP_FAN1_8", + "CMT_TOP_IMUX34_4", + "CMT_TOP_IMUX12_9", + "CMT_TOP_SW4A1_10", + "CMT_TOP_NW4A0_11", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4B0_2", + "CMT_L_TOP_UPPER_B_CLKINT_2", + "CMT_TOP_LH2_2", + "CMT_PHASER_OUT_CA_OCLKDIV", + "CMT_TOP_IMUX10_7", + "CMT_TOP_IMUX39_0", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_WW4END0_10", + "CMT_TOP_IMUX30_10", + "CMT_PHASER_OUT_CA_TESTIN13", + "CMT_TOP_NW2A0_9", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "CMT_TOP_SW4A3_5", + "CMT_TOP_IMUX14_1", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_WL1END0_10", + "CMT_TOP_IMUX26_1", + "CMT_TOP_CTRL0_9", + "CMT_TOP_WL1END0_1", + "CMT_TOP_LH11_6", + "CMT_TOP_NE4C3_8", + "CMT_TOP_WL1END0_7", + "CMT_TOP_LH12_4", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_NE4C3_4", + "CMT_TOP_ER1BEG0_7", + "CMT_TOP_WW2END2_4", + "CMT_TOP_SE4C2_6", + "CMT_TOP_SW4END1_8", + "CMT_PHY_CONTROL_TESTINPUT6", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_SW2A1_1", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_WW4END3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_9", + "CMT_TOP_WL1END2_6", + "CMT_TOP_IMUX43_6", + "CMT_PHASER_OUT_DB_TESTIN4", + "CMT_TOP_NW4A1_1", + "CMT_TOP_SE4C1_8", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_SE4BEG0_3", + "CMT_PHASER_IN_CA_TESTIN7", + "CMT_TOP_IMUX40_5", + "CMT_PHASER_IN_DB_STG1OVERFLOW", + "CMT_PHASER_IN_DB_DQSFOUND", + "CMT_TOP_EE4BEG3_2", + "CMT_TOP_BLOCK_OUTS_L_B1_10", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_IMUX34_1", + "CMT_TOP_WL1END2_0", + "CMT_TOP_EE4A1_3", + "CMT_TOP_OCLKDIV_10", + "CMT_TOP_LH7_0", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_IMUX8_11", + "CMT_TOP_WW2END0_2", + "CMT_TOP_IMUX0_3", + "CMT_TOP_EE4A0_1", + "CMT_TOP_WW4A1_4", + "CMT_TOP_IMUX23_3", + "CMT_TOP_IMUX20_0", + "CMT_TOP_WR1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_LH11_9", + "CMT_TOP_IMUX25_1", + "CMT_TOP_ER1BEG1_1", + "CMT_TOP_IMUX44_7", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_PHASER_IN_DB_TESTIN7", + "CMT_PHASER_IN_DB_STG1REGR0", + "CMT_TOP_WW4A3_10", + "CMT_TOP_WW2A0_4", + "CMT_TOP_SW2A0_10", + "CMT_TOP_WW4A3_3", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_LH1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_NW4A0_4", + "CMT_TOP_CLK1_5", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_NE2A0_10", + "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "CMT_TOP_IMUX18_5", + "CMT_TOP_IMUX24_8", + "CMT_R_TOP_UPPER_B_CLKPLL3", + "CMT_TOP_IMUX24_7", + "CMT_TOP_LH12_11", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "CMT_TOP_EE4B0_2", + "CMT_TOP_SW2A0_2", + "CMT_TOP_SW4A3_1", + "CMT_TOP_EE2A3_10", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_WL1END3_2", + "CMT_TOP_SE4BEG0_11", + "CMT_TOP_FAN4_5", + "CMT_TOP_EE4A1_10", + "CMT_TOP_NE2A1_2", + "CMT_TOP_SE4BEG1_7", + "CMT_TOP_NE2A1_10", + "CMT_TOP_WW2END2_11", + "CMT_TOP_IMUX36_3", + "CMT_TOP_IMUX10_11", + "CMT_TOP_IMUX14_9", + "CMT_TOP_ER1BEG2_11", + "CMT_TOP_IMUX21_7", + "CMT_TOP_EE4B3_11", + "CMT_TOP_IMUX25_7", + "CMT_TOP_SW4A2_5", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_WW4C0_9", + "CMT_PHASER_OUT_DB_TESTOUT3", + "CMT_TOP_NE4C2_3", + "CMT_TOP_WW4A1_8", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_BYP7_5", + "CMT_PHY_CONTROL_PHYCTLWD22", + "CMT_TOP_NE2A0_5", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_EE4A0_2", + "CMT_PHASER_IN_DB_COUNTERREADEN", + "CMT_TOP_SW4END3_8", + "CMT_TOP_IMUX20_6", + "CMT_TOP_LH9_3", + "CMT_TOP_EE4B3_0", + "CMT_TOP_EL1BEG1_9", + "CMT_TOP_SW2A2_10", + "CMT_TOP_WW4END3_0", + "CMT_PHY_CONTROL_PHYCTLWD7", + "CMT_TOP_WW2A0_1", + "CMT_TOP_SW4A0_9", + "CMT_TOP_IMUX45_7", + "CMT_TOP_IMUX19_2", + "CMT_TOP_IMUX42_5", + "CMT_TOP_IMUX18_11", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_BLOCK_OUTS_L_B0_9", + "CMT_TOP_WL1END2_7", + "CMT_TOP_SW4END3_6", + "CMT_TOP_SW4A0_3", + "PLL_CLK_FREQBB_REBUFOUT2", + "CMT_TOP_BYP1_10", + "CMT_TOP_IMUX27_7", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_PHY_CONTROL_TESTOUTPUT4", + "CMT_PHY_CONTROL_PHYCTLWD14", + "CMT_TOP_SW4A2_10", + "CMT_TOP_LOGIC_OUTS_L_B6_10", + "CMT_TOP_BYP5_6", + "CMT_TOP_IMUX27_8", + "CMT_TOP_IMUX34_3", + "CMT_TOP_FAN0_0", + "CMT_PHASER_IN_DB_STG1INCDEC", + "CMT_TOP_IMUX23_11", + "CMT_PHASER_IN_DB_ICLKDIV", + "CMT_TOP_WR1END1_1", + "CMT_TOP_WW4END3_6", + "CMT_TOP_WW4B3_7", + "CMT_TOP_SW4A0_7", + "CMT_TOP_NE4BEG1_11", + "CMT_TOP_SW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_LOGIC_OUTS_L_B15_10", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_IMUX6_2", + "CMT_PHASER_OUT_CA_SCANCLK", + "CMT_TOP_WW4A1_6", + "CMT_PHY_CONTROL_TESTOUTPUT12", + "CMT_TOP_WW4C2_5", + "CMT_TOP_IMUX40_0", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_EE2A2_8", + "CMT_TOP_NE2A3_7", + "CMT_PHASER_OUT_DB_TESTIN3", + "CMT_TOP_ER1BEG1_2", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_LOGIC_OUTS_L_B14_11", + "CMT_TOP_IMUX3_5", + "CMT_TOP_LH4_5", + "CMT_TOP_BYP7_4", + "CMT_PHASER_IN_CA_TESTIN9", + "CMT_TOP_CLK1_0", + "CMT_TOP_IMUX26_11", + "CMT_TOP_IMUX1_5", + "CMT_TOP_LH9_4", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_SE4C2_1", + "CMT_R_TOP_UPPER_B_CLKPLL1", + "CMT_TOP_EE2A3_1", + "CMT_TOP_SW2A2_9", + "CMT_TOP_EL1BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_11", + "CMT_TOP_IMUX28_0", + "CMT_PHASER_IN_DB_ISERDESRST", + "CMT_TOP_BYP3_11", + "CMT_TOP_IMUX18_2", + "CMT_TOP_WW2END0_1", + "CMT_TOP_LOGIC_OUTS_L_B7_9", + "CMT_PHASER_IN_CA_FINEENABLE", + "CMT_PHASER_OUT_DB_RST", + "CMT_TOP_BYP3_0", + "CMT_TOP_BYP4_3", + "CMT_TOP_CLK1_10", + "CMT_TOP_EE4BEG0_11", + "CMT_TOP_NE2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_BLOCK_OUTS_L_B0_11", + "CMT_TOP_EE2A3_8", + "CMT_TOP_EE4A2_8", + "CMT_TOP_OCLKDIV_4", + "CMT_PHASER_IN_DB_TESTIN10", + "CMT_TOP_WW4C0_6", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_CTRL0_4", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SW4END0_6", + "CMT_TOP_NE4BEG1_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "CMT_PHASER_OUT_CA_TESTIN10", + "CMT_PHASER_IN_DB_STG1REGL2", + "CMT_TOP_NW4A3_7", + "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "CMT_TOP_WW4B1_10", + "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "CMT_TOP_SE2A3_5", + "CMT_TOP_LH5_10", + "CMT_TOP_WW4END0_11", + "CMT_TOP_BYP7_7", + "CMT_TOP_IMUX29_5", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_IMUX25_5", + "CMT_TOP_WW4A3_4", + "CMT_TOP_FAN5_9", + "CMT_TOP_IMUX46_8", + "CMT_TOP_IMUX31_11", + "CMT_PHASERREF_PHASEROUT_C", + "CMT_TOP_BYP4_0", + "CMT_PHY_CONTROL_INRANKD1", + "CMT_TOP_IMUX18_4", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_TOP_LOGIC_OUTS_L_B16_9", + "CMT_TOP_WW2A2_3", + "CMT_TOP_IMUX28_3", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WW2A1_11", + "CMT_TOP_LH7_3", + "CMT_TOP_LH6_1", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_NE2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH6_0", + "CMT_TOP_WW4C0_7", + "CMT_TOP_SE4BEG2_2", + "CMT_TOP_WW4END1_10", + "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "CMT_PHASER_IN_CA_STG1REGR4", + "CMT_TOP_LH3_5", + "CMT_TOP_BYP0_10", + "CMT_TOP_NE4C0_4", + "CMT_TOP_SW2A1_7", + "CMT_PHASER_IN_DB_SCANENB", + "CMT_TOP_NE4C0_2", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "CMT_PHASER_OUT_C_OCLK", + "CMT_TOP_SE4C0_7", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_LOGIC_OUTS_L_B11_10", + "CMT_TOP_SW4A1_8", + "CMT_PHY_CONTROL_TESTOUTPUT2", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_LH11_11", + "CMT_TOP_WR1END3_3", + "CMT_TOP_MONITOR_P_1", + "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO", + "CMT_TOP_LH8_8", + "CMT_TOP_SW4A3_6", + "CMT_TOP_SW4END1_11", + "CMT_TOP_IMUX31_8", + "CMT_TOP_EE2A3_0", + "CMT_TOP_IMUX21_11", + "CMT_TOP_IMUX13_2", + "CMT_TOP_IMUX39_4", + "CMT_PHASER_IN_DB_SCANMODEB", + "CMT_TOP_NW4END2_11", + "CMT_TOP_MONITOR_P_3", + "CMT_TOP_EE4B1_7", + "CMT_TOP_WW4A0_7", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_PHY_CONTROL_IRANKD0", + "CMT_PHY_CONTROL_INBURSTPENDING1", + "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "CMT_TOP_WW4B0_11", + "CMT_TOP_SE2A1_2", + "CMT_L_TOP_UPPER_B_CLKINT_3", + "CMT_PHASER_OUT_CA_FINEENABLE", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_BYP5_11", + "CMT_TOP_NE2A0_4", + "CMT_TOP_LH9_0", + "CMT_TOP_IMUX22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_10", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_IMUX25_6", + "CMT_TOP_NE2A1_4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "CMT_TOP_EE4BEG3_0", + "CMT_TOP_WW2END1_7", + "CMT_TOP_EE4B0_7", + "CMT_TOP_WW4B2_10", + "CMT_TOP_BYP1_0", + "CMT_TOP_IMUX22_4", + "CMT_TOP_SE4C1_0", + "CMT_PHASER_OUT_CA_FREQREFCLK", + "CMT_TOP_FAN7_3", + "CMT_TOP_WW4A0_6", + "CMT_PHASER_IN_DB_SYSCLK", + "CMT_TOP_WW2END2_1", + "CMT_TOP_IMUX45_5", + "CMT_TOP_BYP6_4", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_TOP_BYP3_5", + "CMT_TOP_EE2A0_3", + "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_EE4C2_2", + "CMT_TOP_FAN2_10", + "CMT_TOP_CTRL1_5", + "CMT_TOP_CTRL0_5", + "CMT_TOP_WW2END0_6", + "CMT_TOP_IMUX1_3", + "CMT_TOP_WW2END0_7", + "CMT_TOP_NW4END0_11", + "CMT_PHASER_OUT_DB_TESTOUT2", + "CMT_TOP_WL1END2_3", + "CMT_TOP_LOGIC_OUTS_L_B20_11", + "CMT_TOP_IMUX36_11", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_IMUX10_3", + "CMT_TOP_IMUX37_10", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_WR1END3_8", + "CMT_TOP_IMUX47_1", + "CMT_TOP_IMUX10_6", + "CMT_TOP_IMUX44_10", + "CMT_TOP_BYP6_11", + "CMT_TOP_NE4C1_0", + "CMT_PHASER_IN_DB_STG1READ", + "CMT_TOP_WW4A3_1", + "CMT_TOP_BYP6_6", + "CMT_TOP_BYP4_10", + "CMT_PHY_CONTROL_TESTINPUT13", + "CMT_TOP_LOGIC_OUTS_L_B23_11", + "CMT_TOP_NE4C0_3", + "CMT_TOP_SW4A3_9", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_OCLKDIV_8", + "CMT_PHY_CONTROL_IRANKD1", + "CMT_TOP_LH2_1", + "CMT_TOP_IMUX42_1", + "CMT_TOP_SW4A1_6", + "CMT_PHASER_IN_DB_STG1REGL8", + "CMT_TOP_LH12_0", + "CMT_TOP_IMUX7_11", + "CMT_TOP_NW4A1_9", + "CMT_TOP_BYP1_8", + "CMT_TOP_WW4C2_1", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_IMUX42_0", + "CMT_PHASERREF_PHASERIN_C", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_FAN7_1", + "CMT_PHASER_IN_DB_TESTOUT2", + "CMT_TOP_SE4C2_9", + "CMT_TOP_WW2A3_0", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_WW4A2_9", + "CMT_TOP_LH1_7", + "CMT_TOP_EE2BEG2_11", + "CMT_PHY_CONTROL_SYNCIN", + "CMT_TOP_NW4A1_6", + "CMT_TOP_BYP2_1", + "CMT_TOP_WL1END2_10", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_IMUX13_0", + "CMT_TOP_IMUX30_7", + "CMT_TOP_WW4A0_3", + "CMT_TOP_FAN2_0", + "CMT_TOP_BLOCK_OUTS_L_B1_9", + "CMT_TOP_IMUX18_9", + "CMT_PHASER_IN_CA_PHASELOCKED", + "CMT_TOP_CTRL1_0", + "CMT_TOP_EE2A0_5", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_TOP_WW4A0_1", + "CMT_PHASER_IN_DB_STG1REGL0", + "CMT_TOP_FAN3_0", + "CMT_TOP_LH2_7", + "CMT_TOP_IMUX30_2", + "CMT_TOP_FAN3_3", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_IMUX2_5", + "CMT_TOP_IMUX28_4", + "CMT_TOP_IMUX10_9", + "CMT_PHASER_IN_CA_STG1REGL3", + "CMT_TOP_EL1BEG3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_9", + "CMT_PHY_CONTROL_TESTINPUT4", + "CMT_TOP_LH11_0", + "CMT_TOP_EE4C1_11", + "CMT_TOP_IMUX15_5", + "CMT_TOP_IMUX13_8", + "CMT_TOP_SE4C1_9", + "CMT_TOP_EE4C0_5", + "CMT_TOP_IMUX2_0", + "CMT_PHASER_OUT_CA_OCLKDELAYED", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_SW4END1_1", + "CMT_TOP_LH12_7", + "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "CMT_TOP_WR1END3_7", + "CMT_TOP_WL1END1_7", + "CMT_TOP_OCLK_4", + "CMT_PHY_CONTROL_TESTSELECT1", + "CMT_TOP_EE4C1_2", + "CMT_TOP_BYP0_4", + "CMT_TOP_FAN4_0", + "CMT_TOP_BYP7_10", + "CMT_TOP_SW2A0_9", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_MONITOR_N_9", + "CMT_TOP_WW4A1_3", + "CMT_TOP_WW4END0_9", + "CMT_TOP_FAN4_4", + "CMT_TOP_ICLKDIV_9", + "CMT_PHY_CONTROL_TESTOUTPUT3", + "CMT_TOP_IMUX7_8", + "CMT_TOP_LOGIC_OUTS_L_B5_11", + "CMT_TOP_WW4B2_11", + "CMT_TOP_BYP7_0", + "CMT_TOP_FAN7_11", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_BYP6_2", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_EE4C2_8", + "CMT_PHASER_OUT_CA_OSERDESRST", + "CMT_TOP_IMUX14_6", + "CMT_TOP_LOGIC_OUTS_L_B19_11", + "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "CMT_TOP_SW4A2_11", + "CMT_TOP_IMUX10_1", + "CMT_TOP_NE4C3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_LOGIC_OUTS_L_B8_9", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_IMUX37_11", + "CMT_TOP_IMUX6_4", + "CMT_TOP_BLOCK_OUTS_L_B0_10", + "CMT_TOP_BLOCK_OUTS_L_B1_11", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_TOP_CTRL0_11", + "CMT_TOP_IMUX43_7", + "CMT_TOP_LOGIC_OUTS_L_B23_9", + "CMT_TOP_EE2BEG0_4", + "CMT_PHASER_REF_TESTIN3", + "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "CMT_PHY_CONTROL_IBURSTPENDING0", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LOGIC_OUTS_L_B7_10", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_IMUX38_7", + "CMT_TOP_IMUX21_10", + "CMT_PHASER_OUT_CA_COARSEINC", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_SW4A2_7", + "CMT_TOP_OCLK1X_90_10", + "CMT_PHASER_REF_TESTOUT5", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_LH1_2", + "CMT_TOP_BYP0_9", + "CMT_TOP_LOGIC_OUTS_L_B4_10", + "CMT_TOP_FAN4_10", + "CMT_TOP_IMUX30_3", + "CMT_TOP_WR1END3_10", + "CMT_TOP_EE2BEG3_9", + "CMT_TOP_WR1END1_6", + "CMT_TOP_SW2A2_5", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_NW2A1_8", + "CMT_TOP_IMUX15_11", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_IMUX36_9", + "CMT_TOP_EE4B2_1", + "CMT_TOP_SW2A2_0", + "CMT_TOP_NW4END2_3", + "CMT_TOP_FAN4_2", + "CMT_PHASER_IN_C_ICLKDIV", + "CMT_TOP_IMUX43_0", + "CMT_TOP_ER1BEG1_7", + "CMT_PHASER_IN_D_ICLKDIV", + "CMT_TOP_WW4END0_8", + "CMT_TOP_SW4A1_4", + "CMT_PHY_CONTROL_AUXOUTPUT3", + "CMT_PHASER_OUT_CA_SCANMODEB", + "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "CMT_TOP_IMUX29_0", + "CMT_TOP_FAN6_0", + "CMT_TOP_IMUX43_2", + "CMT_TOP_EE4B1_1", + "CMT_TOP_NW2A2_8", + "CMT_PHASER_IN_DB_STG1REGL5", + "CMT_TOP_CTRL1_10", + "CMT_TOP_WW2A0_3", + "CMT_PHY_CONTROL_TESTINPUT0", + "CMT_PHY_CONTROL_INBURSTPENDING2", + "CMT_TOP_WW2A2_5", + "CMT_TOP_SW4END1_6", + "CMT_TOP_FAN4_9", + "CMT_TOP_NE4BEG0_9", + "CMT_TOP_EE4B2_5", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_WW2A2_0", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", + "CMT_TOP_NE4C3_2", + "CMT_TOP_SE4BEG3_4", + "CMT_TOP_WW2END3_3", + "CMT_TOP_IMUX5_4", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_TOP_WW2END3_2", + "CMT_TOP_NE4C2_1", + "CMT_PHY_CONTROL_PHYCTLWD10", + "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "CMT_PHASER_OUT_CA_TESTIN15", + "CMT_TOP_SW4END2_2", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_NE2A3_8", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B2_11", + "CMT_TOP_SW4A1_3", + "CMT_TOP_NW4A2_8", + "CMT_TOP_WR1END1_5", + "CMT_TOP_SE4C2_5", + "CMT_TOP_LOGIC_OUTS_L_B22_11", + "CMT_TOP_ER1BEG3_3", + "CMT_PHY_CONTROL_AUXOUTPUT1", + "CMT_TOP_WW2A3_9", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_FAN2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_IMUX41_2", + "CMT_TOP_IMUX20_2", + "CMT_TOP_SW4END2_6", + "CMT_TOP_IMUX45_1", + "CMT_TOP_NW4END0_9", + "CMT_PHASER_OUT_CA_TESTIN4", + "CMT_TOP_IMUX24_9", + "CMT_TOP_WW4B3_3", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_NE4C3_3", + "CMT_TOP_BYP2_0", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_LH12_6", + "CMT_PHASER_IN_DB_TESTIN9", + "CMT_TOP_SW4END2_9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_EE4A1_1", + "CMT_TOP_IMUX27_9", + "CMT_TOP_SW4A0_10", + "CMT_TOP_IMUX26_3", + "CMT_TOP_SW4A2_0", + "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "CMT_TOP_EL1BEG3_9", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_LOGIC_OUTS_L_B2_10", + "CMT_TOP_IMUX47_0", + "CMT_TOP_IMUX7_10", + "CMT_TOP_FAN5_5", + "CMT_PHASER_IN_CA_SELCALORSTG1", + "CMT_TOP_NW4END2_10", + "CMT_TOP_SE4C0_3", + "CMT_TOP_IMUX45_4", + "CMT_TOP_EL1BEG1_11", + "CMT_PHASER_OUT_DB_SCANIN", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_EE2A3_7", + "CMT_TOP_EE4A3_9", + "CMT_TOP_IMUX19_0", + "CMT_TOP_WR1END0_0", + "CMT_TOP_EE4BEG1_9", + "CMT_TOP_NE2A3_3", + "CMT_TOP_WW4C1_8", + "CMT_TOP_SW4A3_10", + "CMT_TOP_FAN5_11", + "CMT_TOP_NE4C0_5", + "CMT_TOP_IMUX8_6", + "CMT_TOP_WL1END2_2", + "CMT_TOP_SE2A0_9", + "CMT_TOP_EE4A3_4", + "CMT_PHASER_IN_C_RCLK2", + "CMT_PHY_CONTROL_TESTOUTPUT5", + "CMT_PHASER_IN_DB_TESTIN12", + "CMT_TOP_BYP1_2", + "CMT_TOP_WW4END2_3", + "CMT_PHASER_UP_DQS_TO_PHASER_C", + "CMT_TOP_IMUX24_2", + "CMT_TOP_IMUX6_0", + "CMT_TOP_NW4END1_10", + "CMT_TOP_EE4BEG3_8", + "CMT_PHY_CONTROL_TESTINPUT2", + "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "CMT_TOP_WW2END2_10", + "CMT_TOP_EE4B2_0", + "CMT_TOP_SW2A0_7", + "CMT_TOP_CLK0_8", + "CMT_TOP_IMUX44_0", + "CMT_TOP_EE4C3_10", + "CMT_TOP_BYP4_6", + "CMT_TOP_WW2END1_11", + "CMT_PHY_CONTROL_READCALIBENABLE", + "CMT_TOP_IMUX9_4", + "CMT_TOP_IMUX7_0", + "CMT_TOP_EE4A0_4", + "CMT_TOP_LH9_6", + "CMT_TOP_SW2A3_7", + "CMT_TOP_WW4A3_9", + "CMT_TOP_NW4END3_8", + "CMT_TOP_NW4A1_2", + "CMT_TOP_SE2A0_7", + "CMT_TOP_WW4B1_3", + "CMT_TOP_BYP4_11", + "CMT_PHASER_OUT_CA_ENCALIB0", + "CMT_TOP_WR1END2_8", + "CMT_PHASER_OUT_DB_OCLK", + "CMT_TOP_NW2A0_2", + "CMT_TOP_EE4B0_3", + "CMT_TOP_FAN1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_10", + "CMT_TOP_SE2A1_4", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "CMT_TOP_SE4C0_6", + "CMT_TOP_IMUX17_4", + "CMT_TOP_LH2_10", + "CMT_PHASER_IN_C_WRENABLE_FIFO", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_SW4END2_4", + "CMT_TOP_WL1END0_6", + "CMT_TOP_IMUX37_2", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_EE4B3_6", + "CMT_TOP_NW4END2_5", + "CMT_TOP_EE4A1_7", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_IMUX15_3", + "CMT_TOP_LH7_10", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_WR1END3_9", + "CMT_TOP_WW2END3_10", + "CMT_TOP_ICLKDIV_2", + "CMT_PHY_CONTROL_TESTINPUT8", + "CMT_TOP_LH6_7", + "CMT_TOP_EE4C2_10", + "CMT_TOP_IMUX11_3", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_EE4B2_4", + "CMT_TOP_WW2A3_5", + "CMT_TOP_WW2END2_6", + "CMT_TOP_SW4END0_7", + "CMT_TOP_OCLK_9", + "CMT_TOP_LH1_9", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_BYP7_11", + "CMT_TOP_WL1END1_2", + "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "CMT_TOP_WW2A3_8", + "CMT_TOP_WW2END3_0", + "CMT_TOP_IMUX30_6", + "CMT_FREQ_BB_PREF_IN2", + "CMT_TOP_EL1BEG0_1", + "CMT_TOP_IMUX22_5", + "CMT_TOP_FAN2_11", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_IMUX12_0", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_NE2A1_1", + "CMT_TOP_IMUX19_3", + "CMT_TOP_WW4B0_5", + "CMT_TOP_ICLK_8", + "CMT_TOP_IMUX7_9", + "CMT_TOP_IMUX7_6", + "CMT_PHY_CONTROL_SCANENABLEN", + "CMT_TOP_SW2A1_2", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_IMUX36_2", + "CMT_TOP_WW2END3_1", + "CMT_TOP_NE4C0_1", + "CMT_TOP_IMUX11_11", + "CMT_TOP_BYP3_10", + "CMT_TOP_IMUX11_5", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_TOP_NE4BEG2_2", + "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "CMT_TOP_IMUX30_1", + "CMT_PHASER_IN_CA_WRENABLE", + "CMT_FREQ_BB_PREF_IN0", + "CMT_TOP_WW2END0_11", + "CMT_TOP_WW4C1_9", + "CMT_TOP_SE4C3_2", + "CMT_TOP_NE4C0_7", + "CMT_TOP_EE4A2_1", + "CMT_TOP_WW2END2_9", + "CMT_TOP_IMUX43_3", + "CMT_PHASER_OUT_CA_TESTOUT0", + "CMT_PHASER_OUT_DB_PHASEREFCLK", + "CMT_TOP_IMUX33_3", + "CMT_TOP_IMUX21_4", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_LH5_8", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_NW4A2_10", + "CMT_PHASER_IN_CA_TESTIN8", + "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "CMT_TOP_WW4END3_1", + "CMT_TOP_LOGIC_OUTS_L_B14_10", + "CMT_TOP_IMUX35_4", + "CMT_TOP_NE4C1_10", + "CMT_TOP_LOGIC_OUTS_L_B3_9", + "CMT_TOP_IMUX42_8", + "CMT_TOP_EE2A3_4", + "CMT_TOP_EE4BEG2_6", + "CMT_PHY_CONTROL_PHYCTLWD15", + "CMT_TOP_IMUX38_8", + "CMT_PHY_CONTROL_TESTOUTPUT7", + "CMT_PHASER_OUT_CA_TESTOUT2", + "CMT_TOP_CLK0_0", + "CMT_TOP_SE2A1_6", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_LH8_11", + "CMT_TOP_FAN7_2", + "CMT_TOP_EE2A0_7", + "CMT_PHASER_OUT_DB_CTSBUS1", + "CMT_TOP_NE4BEG2_10", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_WW4C3_9", + "CMT_TOP_EE2BEG0_10", + "CMT_TOP_IMUX37_1", + "CMT_TOP_EE4C3_5", + "CMT_TOP_NE4C3_5", + "CMT_PHASER_IN_DB_ENSTG1", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_BYP5_2", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_IMUX6_1", + "CMT_TOP_NE2A0_9", + "CMT_TOP_IMUX36_4", + "CMT_TOP_BYP4_1", + "CMT_TOP_IMUX9_3", + "CMT_TOP_IMUX15_6", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_IMUX7_3", + "CMT_TOP_NW4END1_1", + "CMT_TOP_FAN3_8", + "CMT_TOP_LH4_1", + "CMT_PHASER_OUT_DB_FINEENABLE", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX45_0", + "CMT_PHASER_C_OCLKDIV_TOIOI", + "CMT_TOP_EE4B1_9", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_FAN6_9", + "CMT_PHASER_IN_CA_TESTIN10", + "CMT_TOP_EE4C2_3", + "CMT_PHASER_IN_DB_TESTIN5", + "CMT_PHY_CONTROL_TESTOUTPUT11", + "CMT_R_PHASER_OUT_C_RDCLK_FIFO", + "CMT_TOP_WR1END1_8", + "CMT_TOP_IMUX19_9", + "CMT_TOP_IMUX5_10", + "CMT_PHASER_IN_CA_STG1REGR2", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_EL1BEG0_11", + "CMT_TOP_EE4A0_5", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NW2A0_5", + "CMT_TOP_IMUX24_10", + "CMT_PHASER_IN_CA_SCANIN", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_IMUX16_10", + "CMT_TOP_SW4END1_4", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX5_11", + "CMT_TOP_LOGIC_OUTS_L_B17_11", + "CMT_TOP_EE4C0_9", + "CMT_TOP_EE4B0_1", + "CMT_TOP_IMUX18_6", + "CMT_TOP_SW2A3_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_WW4A3_7", + "CMT_TOP_WW4A1_7", + "CMT_TOP_IMUX41_6", + "CMT_PHY_CONTROL_PHYCTLWD21", + "CMT_TOP_LH4_0", + "CMT_TOP_SW2A2_8", + "CMT_TOP_WW2A0_9", + "CMT_TOP_BYP2_7", + "CMT_PHASER_REF_TESTOUT1", + "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "CMT_TOP_SW4A1_2", + "CMT_TOP_IMUX4_10", + "CMT_TOP_FAN3_4", + "CMT_TOP_SW4END3_3", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH11_7", + "CMT_TOP_NW2A3_1", + "CMT_TOP_WW4A1_5", + "CMT_TOP_WW2A2_11", + "CMT_TOP_EE4C1_3", + "CMT_TOP_FAN3_5", + "CMT_PHASER_IN_CA_SYNCIN", + "CMT_TOP_WW2A2_7", + "CMT_TOP_BYP5_10", + "CMT_TOP_OCLK_1", + "CMT_TOP_EE4C1_9", + "CMT_TOP_WL1END3_4", + "CMT_TOP_EE2A0_10", + "CMT_PHASER_OUT_CA_ENCALIB1", + "PLL_CLK_FREQBB_REBUFOUT1", + "CMT_TOP_SW2A1_11", + "CMT_TOP_EE4B3_2", + "CMT_PHY_CONTROL_OUTBURSTPENDING3", + "CMT_TOP_NW4END2_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_FAN6_1", + "CMT_TOP_EE4C1_7", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_IMUX28_11", + "CMT_TOP_SE4C1_6", + "CMT_TOP_IMUX39_6", + "CMT_TOP_IMUX35_2", + "CMT_R_TOP_UPPER_B_CLKPLL2", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_NE2A1_9", + "CMT_TOP_WL1END0_2", + "CMT_TOP_IMUX33_10", + "CMT_TOP_LOGIC_OUTS_L_B22_9", + "CMT_TOP_IMUX44_1", + "CMT_TOP_IMUX41_10", + "CMT_PHASER_IN_CA_TESTIN12", + "CMT_PHASER_IN_CA_STG1REGL5", + "CMT_TOP_WW2A1_2", + "CMT_TOP_IMUX16_5", + "CMT_PHASER_IN_DB_STG1REGR3", + "CMT_PHASER_OUT_DB_OCLKDELAYED", + "CMT_TOP_NW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_PHASER_IN_DB_ENCALIBPHY1", + "CMT_TOP_IMUX39_7", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_TOP_SW4END3_10", + "CMT_TOP_IMUX26_0", + "CMT_TOP_EL1BEG0_4", + "CMT_TOP_IMUX4_6", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_PHY_CONTROL_IRANKA0", + "CMT_TOP_EE4B3_3", + "CMT_TOP_WW4B0_6", + "CMT_TOP_NW2A0_1", + "CMT_PHASER_REF_LOCKED", + "CMT_TOP_IMUX27_4", + "CMT_TOP_LOGIC_OUTS_L_B0_10", + "CMT_TOP_NE4BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_EE4C1_8", + "CMT_TOP_EE4C1_4", + "CMT_PHASER_IN_DB_TESTOUT3", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_SW2A3_9", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_ER1BEG0_0", + "CMT_PHASER_OUT_DB_TESTIN10", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_BYP2_4", + "CMT_PHASER_OUT_DB_TESTOUT1", + "CMT_TOP_IMUX0_9", + "CMT_TOP_NW2A3_6", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_CLK0_7", + "CMT_TOP_WL1END3_0", + "CMT_TOP_IMUX13_7", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_EE2A2_0", + "CMT_TOP_ICLK_4", + "CMT_TOP_LOGIC_OUTS_L_B21_9", + "CMT_TOP_IMUX4_0", + "CMT_TOP_MONITOR_P_9", + "CMT_TOP_IMUX3_6", + "CMT_TOP_EE4B0_11", + "CMT_TOP_BYP7_1", + "CMT_TOP_OCLKDIV_9", + "CMT_TOP_WW2END0_8", + "CMT_PHASER_OUT_CA_SCANENB", + "CMT_PHASERD_CTSBUS0", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_WW2END1_3", + "CMT_TOP_SE2A3_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_NE4BEG3_9", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_BYP3_4", + "CMT_TOP_SE4C3_0", + "CMT_TOP_IMUX25_8", + "CMT_TOP_ICLKDIV_1", + "CMT_PHASER_IN_DB_TESTOUT0", + "CMT_TOP_SW4END3_0", + "CMT_TOP_IMUX3_3", + "CMT_PHASER_IN_CA_STG1REGL0", + "CMT_TOP_WW2END1_2", + "CMT_PHASER_IN_CA_RANKSELPHY1", + "CMT_TOP_SE4C1_3", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_LH9_10", + "CMT_TOP_WW2A0_11", + "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "CMT_PHASER_OUT_D_OCLK1X_90", + "CMT_TOP_IMUX25_11", + "CMT_PHASER_IN_CA_STG1OVERFLOW", + "CMT_TOP_NW2A1_1", + "CMT_TOP_NW2A2_5", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX19_6", + "CMT_TOP_WW4A1_2", + "CMT_TOP_NW4A2_9", + "CMT_PHASER_OUT_D_OCLKDIV", + "CMT_TOP_IMUX19_11", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_SE4BEG2_5", + "CMT_PHY_CONTROL_OBURSTPENDING2", + "CMT_TOP_BLOCK_OUTS_L_B3_11", + "CMT_TOP_NE4C3_11", + "CMT_TOP_NW4END2_9", + "CMT_TOP_WW2A1_7", + "CMT_PHASER_IN_CA_TESTIN0", + "CMT_TOP_SW4END0_8", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WL1END0_4", + "CMT_PHASER_OUT_CA_DIVIDERST", + "CMT_TOP_IMUX35_1", + "CMT_TOP_NE4C1_1", + "CMT_TOP_WL1END0_5", + "CMT_TOP_IMUX6_9", + "CMT_PHASER_IN_DB_SCANCLK", + "CMT_PHY_CONTROL_IBURSTPENDING3", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_IMUX20_1", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_NE4BEG1_0", + "CMT_PHY_CONTROL_OUTBURSTPENDING2", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_WW4C3_0", + "CMT_TOP_FAN4_3", + "CMT_TOP_WR1END3_2", + "CMT_TOP_WW4B3_11", + "CMT_TOP_SE2A2_9", + "CMT_TOP_IMUX5_7", + "CMT_TOP_LH7_11", + "CMT_TOP_FAN7_10", + "CMT_TOP_IMUX22_11", + "CMT_TOP_IMUX40_10", + "CMT_TOP_WW2A2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_WW2END0_4", + "CMT_TOP_NW2A2_1", + "CMT_TOP_EE4A1_9", + "CMT_TOP_NE4C3_6", + "CMT_PHY_CONTROL_PHYCTLWD17", + "CMT_TOP_OCLK_7", + "CMT_PHASER_IN_DB_BURSTPENDING", + "CMT_TOP_ER1BEG2_0", + "CMT_PHASER_IN_CA_SCANMODEB", + "CMT_TOP_NW4A2_3", + "CMT_TOP_EE2BEG1_10", + "CMT_TOP_WW4C3_3", + "CMT_TOP_NW4END1_4", + "CMT_TOP_NW2A1_2", + "CMT_TOP_EE4BEG0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_TOP_WW4END0_7", + "CMT_TOP_SW4A3_2", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_IMUX5_8", + "CMT_TOP_WW4A1_11", + "CMT_TOP_SW4A1_5", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_IMUX32_6", + "CMT_TOP_MONITOR_N_11", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_NW2A2_6", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_WW4B0_10", + "CMT_TOP_WW4A1_0", + "CMT_PHY_CONTROL_PHYCTLWD8", + "CMT_TOP_EE2A3_6", + "CMT_TOP_WR1END2_10", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_BYP0_6", + "CMT_TOP_WL1END1_5", + "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "CMT_TOP_IMUX30_0", + "CMT_TOP_LOGIC_OUTS_L_B5_9", + "CMT_TOP_NW2A0_8", + "CMT_TOP_WW4C1_5", + "CMT_TOP_SE4BEG2_11", + "CMT_TOP_NW4A3_11", + "CMT_TOP_IMUX34_6", + "CMT_TOP_SW4A2_4", + "CMT_TOP_NE4C3_1", + "CMT_TOP_NW4A1_7", + "CMT_TOP_IMUX22_6", + "CMT_PHASER_IN_DB_RST", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX1_4", + "CMT_TOP_SW4A1_0", + "CMT_TOP_IMUX41_9", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_FAN2_2", + "CMT_TOP_IMUX33_4", + "CMT_PHASER_OUT_CA_SCANIN", + "CMT_TOP_SE4C0_8", + "CMT_TOP_EE2BEG0_11", + "CMT_TOP_IMUX32_8", + "CMT_PHY_CONTROL_TESTINPUT1", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_EE2BEG1_3", + "CMT_TOP_EE2A2_4", + "CMT_TOP_WW4B2_7", + "CMT_TOP_EE4B1_3", + "CMT_TOP_SW4END0_0", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH10_2", + "CMT_TOP_IMUX4_8", + "CMT_TOP_NE4C1_11", + "CMT_TOP_WW2A1_1", + "CMT_TOP_EE4A1_0", + "CMT_PHASER_IN_DB_MEMREFCLK", + "CMT_TOP_IMUX9_6", + "CMT_TOP_IMUX42_3", + "CMT_TOP_IMUX13_10", + "CMT_TOP_WR1END0_6", + "CMT_TOP_OCLK1X_90_11", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_PHASER_IN_CA_ENCALIBPHY1", + "CMT_PHY_CONTROL_INRANKB0", + "CMT_TOP_IMUX22_2", + "CMT_TOP_SE4C3_6", + "CMT_TOP_IMUX44_4", + "CMT_TOP_CTRL0_1", + "CMT_TOP_IMUX29_10", + "CMT_TOP_IMUX12_11", + "CMT_TOP_WW4B2_0", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_LH12_5", + "CMT_TOP_NE4BEG3_11", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "CMT_TOP_IMUX12_6", + "CMT_TOP_IMUX23_4", + "CMT_TOP_NE4BEG1_5", + "CMT_TOP_NE2A3_6", + "CMT_TOP_ICLK_3", + "CMT_TOP_IMUX7_4", + "CMT_TOP_CLK0_4", + "CMT_TOP_SE2A3_4", + "CMT_TOP_NE2A3_11", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_IMUX28_6", + "CMT_TOP_WW4A3_8", + "CMT_TOP_EE2A0_0", + "CMT_TOP_SE2A1_0", + "CMT_TOP_LH12_10", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_PHY_CONTROL_PHYCTLREADY", + "CMT_TOP_WW4B1_2", + "CMT_TOP_CTRL1_3", + "CMT_TOP_EE4A3_8", + "CMT_TOP_NW4A0_2", + "CMT_TOP_IMUX26_5", + "CMT_TOP_IMUX27_10", + "CMT_TOP_EE4BEG3_10", + "CMT_TOP_LH6_3", + "CMT_TOP_IMUX40_6", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_WR1END2_4", + "CMT_TOP_WW4C1_11", + "CMT_TOP_IMUX20_4", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_TOP_WW4END2_7", + "CMT_TOP_BYP4_7", + "CMT_TOP_FAN4_11", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "CMT_PHASER_OUT_DB_FINEINC", + "CMT_TOP_NE2A2_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "CMT_R_PHASER_IN_D_WRCLK_TOFIFO", + "CMT_TOP_SE4C0_9", + "CMT_TOP_IMUX34_0", + "CMT_TOP_NE2A1_6", + "CMT_TOP_NE4BEG3_10", + "CMT_TOP_IMUX2_9", + "CMT_PHY_CONTROL_PHYCTLWD23", + "CMT_TOP_IMUX0_8", + "CMT_TOP_IMUX31_6", + "CMT_TOP_IMUX36_10", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_TOP_WW4END3_7", + "CMT_TOP_WL1END0_9", + "CMT_PHASER_IN_CA_FINEOVERFLOW", + "CMT_PHASER_OUT_CA_TESTOUT1", + "CMT_PHY_CONTROL_PHYCTLWD24", + "CMT_TOP_SW4A0_1", + "CMT_PHY_CONTROL_INRANKC0", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE2A2_1", + "CMT_TOP_SW2A3_11", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_SW2A1_5", + "CMT_TOP_BLOCK_OUTS_L_B2_10", + "CMT_TOP_CTRL1_8", + "CMT_TOP_OCLK1X_90_9", + "CMT_TOP_NW4A2_5", + "CMT_TOP_NW4A0_0", + "CMT_PHASER_OUT_CA_SYSCLK", + "CMT_PHASER_IN_DB_STG1REGL1", + "CMT_TOP_WW2A1_10", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_IMUX41_1", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX11_7", + "CMT_TOP_NE4C2_11", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "CMT_PHY_CONTROL_TESTSELECT0", + "CMT_TOP_IMUX14_3", + "CMT_TOP_IMUX17_1", + "CMT_TOP_WW4A2_4", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_ICLKDIV_10", + "CMT_TOP_IMUX4_1", + "CMT_TOP_IMUX23_1", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_TOP_NW4A0_3", + "CMT_TOP_EE2A0_2", + "CMT_TOP_IMUX17_9", + "CMT_PHY_CONTROL_PHYCTLWRENABLE", + "CMT_PHASER_IN_DB_FREQREFCLK", + "CMT_TOP_LOGIC_OUTS_L_B21_11", + "CMT_PHASER_IN_CA_STG1REGR0", + "CMT_TOP_WW4END3_3", + "CMT_PHY_CONTROL_PHYCTLWD27", + "CMT_TOP_LH2_6", + "CMT_TOP_WW4B1_9", + "CMT_TOP_WR1END2_11", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_IMUX32_11", + "CMT_TOP_BYP2_8", + "CMT_TOP_WW4A0_0", + "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "CMT_PHASER_IN_CA_TESTIN1", + "CMT_TOP_WR1END3_5", + "CMT_TOP_SE4BEG1_3", + "CMT_PHY_CONTROL_PCENABLECALIB1", + "CMT_PHY_CONTROL_TESTOUTPUT6", + "CMT_TOP_WW4END3_2", + "CMT_TOP_WL1END3_3", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_IMUX34_8", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_CTRL0_7", + "CMT_TOP_IMUX43_9", + "CMT_TOP_IMUX11_1", + "CMT_TOP_IMUX13_1", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_SE2A2_3", + "CMT_TOP_NE2A3_4", + "CMT_TOP_OCLKDIV_11", + "CMT_TOP_EE4C2_6", + "CMT_TOP_SW2A0_5", + "CMT_TOP_SW2A3_10", + "CMT_TOP_LH7_9", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_CTRL1_1", + "CMT_PHY_CONTROL_TESTINPUT9", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_TOP_LH8_5", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_WL1END3_6", + "CMT_TOP_LH1_1", + "CMT_TOP_IMUX4_7", + "CMT_PHASER_IN_CA_COUNTERREADEN", + "CMT_TOP_WW4END2_10", + "CMT_TOP_IMUX24_4", + "CMT_PHY_CONTROL_IBURSTPENDING1", + "CMT_TOP_BYP7_9", + "CMT_TOP_FAN2_9", + "CMT_TOP_LOGIC_OUTS_L_B15_11", + "CMT_TOP_WW4A1_9", + "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "CMT_TOP_EE4C2_11", + "CMT_TOP_IMUX19_1", + "CMT_TOP_LOGIC_OUTS_L_B23_10", + "CMT_TOP_FAN2_8", + "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "CMT_TOP_NW2A1_9", + "CMT_TOP_LOGIC_OUTS_L_B8_11", + "CMT_PHY_CONTROL_PHYCTLFULL", + "CMT_TOP_SE4C2_7", + "CMT_TOP_LH5_9", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH7_2", + "CMT_TOP_IMUX13_6", + "CMT_TOP_IMUX1_1", + "CMT_PHASERD_DQSBUS0", + "CMT_TOP_IMUX4_11", + "CMT_TOP_LH3_8", + "CMT_TOP_EE4C3_3", + "CMT_TOP_SW4A0_0", + "CMT_TOP_SW2A1_8", + "CMT_TOP_IMUX5_9", + "CMT_TOP_IMUX46_0", + "CMT_TOP_IMUX3_0", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_TOP_EE4C2_0", + "CMT_TOP_IMUX16_1", + "CMT_TOP_IMUX16_0", + "CMT_TOP_SW4END2_5", + "CMT_TOP_EE2A1_0", + "CMT_TOP_IMUX12_7", + "CMT_TOP_NW4END0_4", + "CMT_PHASER_IN_CA_COUNTERLOADEN", + "CMT_TOP_NW4A0_9", + "CMT_TOP_IMUX47_5", + "CMT_TOP_WR1END1_3", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_IMUX42_9", + "CMT_PHASER_OUT_CA_DQSBUS1", + "CMT_TOP_IMUX31_2", + "CMT_TOP_WR1END0_9", + "CMT_TOP_IMUX17_5", + "CMT_TOP_WW4END3_11", + "CMT_PHY_CONTROL_OUTBURSTPENDING1", + "CMT_TOP_CLK1_3", + "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "CMT_TOP_ICLKDIV_11", + "CMT_TOP_SE2A1_9", + "CMT_TOP_EE2A3_2", + "CMT_TOP_LH12_9", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_SE4C0_11", + "CMT_TOP_SE4C1_10", + "CMT_TOP_SE4C3_8", + "CMT_PHY_CONTROL_OBURSTPENDING1", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "CMT_TOP_IMUX43_11", + "CMT_TOP_IMUX39_1", + "CMT_TOP_LH1_3", + "CMT_TOP_BYP5_7", + "CMT_TOP_IMUX6_11", + "CMT_TOP_IMUX47_8", + "CMT_PHASER_IN_DB_TESTIN6", + "CMT_TOP_IMUX36_0", + "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "CMT_PHASER_IN_D_RCLK3", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_NW4A2_2", + "CMT_PHASER_IN_CA_RANKSEL1", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_IMUX26_9", + "CMT_TOP_IMUX46_10", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END1_6", + "CMT_PHASER_OUT_DB_TESTIN1", + "CMT_TOP_WL1END1_8", + "CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO", + "CMT_PHASER_IN_DB_WRENABLE", + "CMT_PHASER_OUT_DB_COUNTERREADEN", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_WW2END1_6", + "CMT_TOP_WW4END0_6", + "CMT_TOP_SE2A2_6", + "CMT_TOP_WW4A3_11", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_FAN5_0", + "CMT_PHASERTOP_PHYCTLEMPTY", + "CMT_TOP_LOGIC_OUTS_L_B3_11", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_IMUX7_2", + "CMT_TOP_SW4A3_11", + "CMT_PHASER_OUT_DB_TESTIN12", + "CMT_TOP_SE2A3_10", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_LH2_0", + "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "CMT_TOP_SE2A0_6", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LH9_2", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B4_9", + "CMT_PHASER_IN_DB_STG1REGR8", + "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "CMT_TOP_WW2A3_1", + "CMT_TOP_LH5_3", + "CMT_TOP_NE2A0_6", + "CMT_TOP_FAN4_1", + "CMT_TOP_LH12_1", + "CMT_TOP_LH8_6", + "CMT_TOP_IMUX36_5", + "CMT_TOP_OCLK_6", + "CMT_TOP_SW4END1_5", + "CMT_TOP_LOGIC_OUTS_L_B1_9", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_FAN6_6", + "CMT_TOP_NE2A2_7", + "CMT_TOP_LH7_6", + "CMT_PHASER_OUT_CA_TESTOUT3", + "CMT_TOP_WW4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_PHASER_IN_CA_ENCALIB0", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX45_3", + "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "CMT_TOP_NE4BEG1_10", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_WR1END1_10", + "CMT_TOP_LOGIC_OUTS_L_B16_10", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_SW2A0_3", + "CMT_TOP_EE4C0_7", + "CMT_TOP_NW2A0_11", + "CMT_TOP_NW4END1_6", + "CMT_TOP_IMUX34_11", + "CMT_TOP_IMUX38_4", + "CMT_TOP_FAN6_7", + "CMT_PHASER_OUT_DB_SCANOUT", + "CMT_TOP_EE4BEG1_11", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_IMUX41_5", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_SW4END2_3", + "CMT_TOP_EE2BEG3_8", + "CMT_TOP_LH9_7", + "CMT_PHASER_IN_DB_TESTIN1", + "CMT_PHASER_REF_TMUXOUT", + "CMT_TOP_WW4A1_1", + "CMT_TOP_WR1END0_3", + "CMT_TOP_LH1_6", + "CMT_TOP_FAN2_7", + "CMT_TOP_BYP7_6", + "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "CMT_TOP_IMUX40_11", + "CMT_TOP_NW4A1_5", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_1", + "CMT_TOP_IMUX2_10", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_IMUX32_10", + "CMT_TOP_FAN6_8", + "CMT_TOP_EE4BEG1_10", + "CMT_TOP_NW4A2_4", + "CMT_TOP_WW4C2_4", + "CMT_TOP_LH6_5", + "CMT_TOP_LOGIC_OUTS_L_B11_9", + "CMT_TOP_FAN5_7", + "CMT_TOP_OCLK_2", + "CMT_TOP_WL1END1_6", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_BYP6_0", + "CMT_TOP_WL1END3_9", + "CMT_PHY_CONTROL_TESTSELECT2", + "CMT_TOP_EE2BEG2_6", + "CMT_PHASER_IN_CA_DQSFOUND", + "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "CMT_TOP_WW2END3_9", + "CMT_TOP_IMUX25_9", + "CMT_TOP_NW4END1_7", + "CMT_TOP_EE2A1_4", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_IMUX33_6", + "CMT_TOP_LH2_8", + "CMT_PHY_CONTROL_TESTINPUT14", + "CMT_TOP_NW4A2_6", + "CMT_TOP_NE4C1_6", + "CMT_TOP_IMUX8_9", + "CMT_TOP_NE2A0_3", + "CMT_PHASER_IN_CA_TESTIN6", + "CMT_TOP_SE4C3_7", + "CMT_TOP_IMUX34_10", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_IMUX31_1", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_WW4C3_7", + "CMT_TOP_IMUX32_9", + "CMT_TOP_IMUX8_4", + "CMT_TOP_NW2A2_10", + "CMT_TOP_IMUX33_1", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_WW4END1_3", + "CMT_TOP_FAN1_11", + "CMT_TOP_SW2A0_1", + "CMT_TOP_IMUX33_8", + "CMT_TOP_NW4A1_3", + "CMT_TOP_LH10_0", + "CMT_TOP_LH5_6", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX7_5", + "CMT_TOP_EE4C2_1", + "CMT_TOP_NE2A3_9", + "CMT_TOP_ER1BEG2_5", + "CMT_TOP_NW2A3_11", + "CMT_PHASER_IN_DB_STG1REGR6", + "CMT_TOP_EE4BEG1_5", + "CMT_TOP_EE4C2_4", + "CMT_TOP_EE2A1_3", + "CMT_TOP_SW4A2_3", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_NE4C3_7", + "CMT_TOP_IMUX12_2", + "CMT_TOP_WW4B1_8", + "CMT_TOP_SE2A1_11", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_IMUX3_9", + "CMT_PHASER_OUT_DB_ENCALIB0", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_PHASER_IN_DB_RANKSELPHY0", + "CMT_TOP_IMUX21_3", + "CMT_TOP_LH4_11", + "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "CMT_TOP_EE4A2_3", + "CMT_TOP_LH1_11", + "CMT_TOP_SW4A2_6", + "CMT_TOP_IMUX35_8", + "CMT_TOP_IMUX9_0", + "CMT_TOP_SW4END0_11", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_PHY_CONTROL_TESTINPUT5", + "CMT_TOP_IMUX16_4", + "CMT_TOP_IMUX39_11", + "CMT_TOP_LH2_4", + "CMT_FREQ_BB_PREF_IN3", + "CMT_TOP_LOGIC_OUTS_L_B14_9", + "CMT_TOP_WW4C0_2", + "CMT_TOP_CTRL1_11", + "CMT_TOP_EE4B2_11", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_LH3_6", + "CMT_PHASER_OUT_D_OCLK", + "CMT_TOP_EE4C3_0", + "CMT_TOP_IMUX40_1", + "CMT_TOP_CLK0_10", + "CMT_TOP_EE4B0_10", + "CMT_TOP_IMUX20_11", + "CMT_TOP_WW4C3_11", + "CMT_TOP_FAN7_9", + "CMT_TOP_IMUX32_2", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_R_TOP_UPPER_B_CLKPLL5", + "CMT_TOP_LH1_4", + "CMT_TOP_BYP1_11", + "CMT_PHASER_IN_CA_RANKSELPHY0", + "CMT_TOP_BYP0_1", + "CMT_TOP_FAN3_10", + "CMT_TOP_NE4C0_6", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_IMUX24_1", + "CMT_PHASER_OUT_C_OCLKDIV", + "CMT_TOP_IMUX12_1", + "CMT_TOP_IMUX29_3", + "CMT_PHASER_C_ICLK_TOIOI", + "CMT_TOP_IMUX18_0", + "CMT_PHASER_IN_CA_STG1REGR6", + "CMT_TOP_SW2A0_6", + "CMT_TOP_FAN7_6", + "CMT_TOP_LOGIC_OUTS_L_B21_10", + "CMT_TOP_IMUX24_11", + "CMT_PHASER_OUT_DB_MEMREFCLK", + "CMT_TOP_EE4A0_3", + "CMT_TOP_SW2A3_6", + "CMT_TOP_IMUX10_10", + "CMT_TOP_BLOCK_OUTS_L_B2_11", + "CMT_TOP_IMUX44_11", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_NW2A0_7", + "CMT_TOP_WR1END2_5", + "CMT_TOP_BYP5_3", + "CMT_TOP_NW4A2_1", + "CMT_TOP_FAN5_6", + "CMT_TOP_IMUX32_4", + "CMT_TOP_LH6_11", + "CMT_TOP_SE4BEG3_9", + "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "CMT_R_TOP_UPPER_B_CLKFBIN", + "CMT_TOP_EE4C3_1", + "CMT_TOP_CTRL0_3", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_PHASER_UP_BUFMRCE_CE1", + "CMT_TOP_LH5_11", + "CMT_TOP_SE4BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_SW4END1_7", + "CMT_TOP_NW4A3_10", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_IMUX6_5", + "CMT_TOP_WW4A3_5", + "CMT_PHASER_OUT_DB_TESTIN14", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_BYP3_9", + "CMT_TOP_IMUX26_2", + "CMT_TOP_IMUX20_10", + "CMT_TOP_IMUX13_4", + "CMT_PHASER_IN_DB_RANKSEL1", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_WW4C3_8", + "CMT_PHASER_IN_DB_TESTIN13", + "CMT_TOP_NE2A0_8", + "CMT_TOP_LH6_4", + "CMT_TOP_NW2A2_4", + "CMT_TOP_IMUX20_9", + "CMT_TOP_WW2END3_6", + "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "CMT_PHASER_IN_CA_RANKSEL0", + "CMT_TOP_FAN6_10", + "CMT_TOP_EE4B2_9", + "CMT_TOP_WW4B1_1", + "CMT_PHASER_C_ICLKDIV_TOIOI", + "CMT_TOP_WW4B1_7", + "CMT_TOP_WW2A3_4", + "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "CMT_TOP_NW4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_IMUX9_11", + "CMT_TOP_BYP7_3", + "CMT_TOP_IMUX25_0", + "CMT_PHASER_IN_CA_TESTIN3", + "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "CMT_TOP_NE4C2_8", + "CMT_PHASER_OUT_DB_SCANENB", + "CMT_PHASER_OUT_DB_FREQREFCLK", + "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "CMT_TOP_IMUX41_0", + "CMT_PHASER_IN_DB_STG1REGR2", + "CMT_TOP_WL1END2_9", + "CMT_TOP_LH4_4", + "CMT_TOP_IMUX24_3", + "CMT_PHY_CONTROL_IRANKB0", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_R_TOP_UPPER_B_CLKPLL0", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_NW2A0_4", + "CMT_TOP_EE2A1_2", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX46_3", + "CMT_TOP_WW2END3_11", + "CMT_TOP_CLK1_11", + "CMT_TOP_EE4A2_0", + "CMT_TOP_SE2A2_4", + "CMT_TOP_IMUX29_11", + "CMT_TOP_EE4A0_7", + "CMT_TOP_WW4C2_3", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_IMUX32_3", + "CMT_TOP_EE2A0_11", + "CMT_TOP_IMUX11_8", + "CMT_TOP_ER1BEG2_10", + "CMT_PHASERD_DTSBUS0", + "CMT_TOP_IMUX27_5", + "CMT_TOP_IMUX36_8", + "CMT_TOP_NW2A1_10", + "CMT_PHASER_UP_PHASERREF_ABOVE1", + "CMT_TOP_WL1END1_0", + "CMT_TOP_IMUX47_3", + "CMT_TOP_IMUX0_2", + "CMT_PHASER_IN_DB_ENCALIBPHY0", + "CMT_PHASER_OUT_DB_TESTIN13", + "CMT_PHASER_REF_TESTIN4", + "CMT_TOP_NW4END3_11", + "CMT_PHY_CONTROL_TESTINPUT10", + "CMT_TOP_WW2A1_6", + "CMT_TOP_SW4A2_1", + "CMT_TOP_NW2A2_2", + "CMT_PHASER_IN_DB_STG1REGR5", + "CMT_TOP_NW2A0_10", + "CMT_TOP_IMUX5_5", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4BEG1_4", + "CMT_TOP_WW4END3_9", + "CMT_TOP_MONITOR_P_2", + "CMT_FREQ_PHASER_REFMUX_0", + "CMT_TOP_IMUX30_11", + "CMT_TOP_WW4C3_1", + "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "CMT_TOP_IMUX33_5", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SE4C2_3", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_EE4A0_9", + "CMT_PHASER_OUT_CA_EDGEADV", + "CMT_TOP_LH7_7", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_BYP6_10", + "CMT_TOP_NW4END3_1", + "CMT_TOP_EE2BEG3_10", + "CMT_TOP_WW2END0_5", + "CMT_TOP_LH5_1", + "CMT_TOP_LH8_7", + "CMT_TOP_OCLK_11", + "CMT_PHASER_OUT_CA_CTSBUS0", + "CMT_TOP_FAN6_5", + "CMT_TOP_IMUX27_1", + "CMT_TOP_NE4BEG2_1", + "CMT_PHY_CONTROL_TESTOUTPUT9", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_SE2A2_8", + "CMT_TOP_SE4C3_10", + "CMT_TOP_WL1END2_5", + "CMT_TOP_WW2A2_9", + "CMT_TOP_SE2A3_9", + "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "CMT_TOP_IMUX14_8", + "CMT_PHY_CONTROL_INRANKA0", + "CMT_TOP_NW4END3_4", + "CMT_TOP_NE2A2_3", + "CMT_TOP_LH8_2", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_EE4A2_10", + "CMT_TOP_IMUX19_10", + "CMT_PHASER_IN_CA_ENCALIB1", + "CMT_TOP_EE4BEG2_11", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_WW2END0_10", + "CMT_TOP_NE4BEG3_0", + "CMT_PHY_CONTROL_INRANKC1", + "CMT_TOP_SE2A3_2", + "CMT_TOP_ER1BEG3_10", + "CMT_TOP_CLK1_8", + "CMT_TOP_EL1BEG2_11", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_NW4A0_1", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_NW4END2_1", + "CMT_TOP_EE4B0_8", + "CMT_TOP_NW4END2_8", + "CMT_TOP_CLK0_6", + "CMT_TOP_WR1END2_6", + "CMT_TOP_WW4END0_1", + "CMT_TOP_NW2A1_7", + "CMT_TOP_WW4A2_6", + "CMT_TOP_IMUX27_3", + "CMT_TOP_SW2A3_0", + "CMT_TOP_EE2A2_9", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_WR1END2_2", + "CMT_TOP_EE4BEG2_9", + "CMT_TOP_EE2A2_7", + "CMT_PHASER_IN_CA_STG1REGL7", + "CMT_TOP_IMUX26_10", + "CMT_TOP_IMUX8_0", + "CMT_TOP_IMUX21_9", + "CMT_PHASER_IN_CA_STG1REGL8", + "CMT_TOP_WW4C1_1", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_LH5_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4C2_0", + "CMT_TOP_EE2A2_11", + "CMT_TOP_WR1END0_8", + "CMT_TOP_WW4C0_10", + "CMT_TOP_WL1END1_4", + "CMT_TOP_WW4B1_6", + "CMT_PHASER_IN_DB_FINEOVERFLOW", + "CMT_TOP_WW2A3_7", + "CMT_TOP_BYP3_6", + "CMT_TOP_EE4B1_8", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_IMUX9_1", + "CMT_TOP_SE4C1_5", + "CMT_TOP_LH4_7", + "CMT_TOP_LOGIC_OUTS_L_B5_10", + "CMT_TOP_IMUX20_5", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_NE4C2_4", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_WW4B1_0", + "CMT_TOP_IMUX0_10", + "CMT_PHASER_REF_RST", + "CMT_TOP_IMUX23_7", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_TOP_EE4A2_7", + "CMT_TOP_FAN3_9", + "CMT_TOP_EE2A0_8", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_NW4END0_8", + "CMT_TOP_WW4B2_3", + "CMT_TOP_IMUX23_0", + "CMT_TOP_EE2BEG3_1", + "CMT_TOP_LH6_8", + "CMT_TOP_SW4END0_10", + "CMT_PHASER_IN_DB_SYNCIN", + "CMT_TOP_LH6_10", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_PHASER_REF_TMUXOUT_TOHCLK", + "CMT_TOP_WL1END0_0", + "CMT_PHASER_IN_CA_RSTDQSFIND", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_FAN0_2", + "CMT_TOP_LOGIC_OUTS_L_B10_10", + "CMT_TOP_LH2_11", + "CMT_TOP_WW2END2_0", + "CMT_TOP_IMUX18_3", + "CMT_PHY_CONTROL_TESTOUTPUT14", + "CMT_TOP_IMUX6_10", + "CMT_TOP_FAN1_1", + "CMT_TOP_NW2A3_8", + "CMT_PHASER_OUT_CA_DTSBUS0", + "CMT_TOP_LH7_1", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_IMUX43_5", + "CMT_TOP_SE4BEG1_10", + "CMT_TOP_EE4B1_10", + "CMT_TOP_IMUX41_4", + "CMT_PHASER_IN_DB_TESTIN2", + "CMT_TOP_IMUX33_0", + "CMT_PHY_CONTROL_PHYCTLEMPTY", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_SE2A3_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "CMT_TOP_SE4C0_0", + "CMT_PHY_CONTROL_IBURSTPENDING2", + "CMT_TOP_NE2A2_9", + "CMT_PHASER_OUT_DB_OCLKDIV", + "CMT_TOP_OCLKDIV_2", + "CMT_PHASER_IN_DB_TESTOUT1", + "CMT_TOP_WW4B3_4", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX5_3", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_BYP2_9", + "CMT_TOP_IMUX23_10", + "CMT_TOP_LH5_0", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_IMUX42_10", + "CMT_TOP_LH10_10", + "CMT_TOP_WW4END2_11", + "CMT_TOP_EE4A1_4", + "CMT_TOP_NW4A1_10", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX11_0", + "CMT_TOP_WW2END3_5", + "CMT_TOP_LH7_8", + "CMT_TOP_NE4C1_3", + "CMT_TOP_CTRL1_6", + "CMT_TOP_WW4C2_11", + "CMT_TOP_CLK1_9", + "CMT_TOP_IMUX31_3", + "CMT_TOP_IMUX37_3", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_LOGIC_OUTS_L_B18_11", + "CMT_TOP_WW4C0_0", + "CMT_TOP_WW4A0_5", + "CMT_TOP_EE4C3_9", + "CMT_PHASER_IN_DB_TESTIN8", + "CMT_TOP_IMUX3_8", + "CMT_TOP_NW4END1_11", + "CMT_PHY_CONTROL_AUXOUTPUT0", + "CMT_TOP_WW2A1_5", + "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", + "CMT_TOP_LOGIC_OUTS_L_B9_10", + "CMT_TOP_SE2A0_4", + "CMT_TOP_IMUX15_1", + "CMT_TOP_IMUX6_3", + "CMT_TOP_IMUX45_9", + "CMT_TOP_EE4B2_7", + "CMT_PHASER_IN_CA_STG1REGR1", + "CMT_TOP_NW2A2_9", + "CMT_PHY_CONTROL_INBURSTPENDING0", + "CMT_TOP_LH3_11", + "CMT_TOP_WR1END0_7", + "CMT_TOP_IMUX24_5", + "CMT_TOP_FAN2_1", + "CMT_TOP_IMUX5_6", + "CMT_TOP_NW4END0_10", + "CMT_TOP_SE4BEG0_9", + "CMT_TOP_NW4END1_9", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_BYP6_5", + "CMT_TOP_ER1BEG3_5", + "CMT_FREQ_PHASER_REFMUX_2", + "CMT_TOP_IMUX37_5", + "CMT_PHY_CONTROL_PHYCTLWD1", + "CMT_TOP_IMUX37_8", + "CMT_TOP_EE4C0_0", + "CMT_TOP_WW4END2_1", + "CMT_PHASER_IN_CA_STG1INCDEC", + "CMT_TOP_EE4A1_6", + "CMT_TOP_LOGIC_OUTS_L_B12_10", + "CMT_TOP_SW4END1_0", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_IMUX35_3", + "CMT_TOP_WW4A2_3", + "CMT_PHASER_IN_DB_PHASELOCKED", + "CMT_TOP_BYP6_9", + "CMT_TOP_IMUX10_4", + "CMT_TOP_LOGIC_OUTS_L_B13_9", + "CMT_TOP_WW4END2_6", + "CMT_PHASER_IN_DB_TESTIN11", + "CMT_PHASER_OUT_CA_BURSTPENDING", + "CMT_TOP_IMUX26_6", + "CMT_TOP_EE4A3_0", + "CMT_PHASER_IN_CA_DIVIDERST", + "CMT_TOP_IMUX18_10", + "CMT_TOP_IMUX22_10", + "CMT_TOP_EE2A1_5", + "CMT_TOP_SW4END3_1", + "CMT_TOP_EL1BEG1_6", + "CMT_PHASER_REF_TESTIN1", + "CMT_TOP_IMUX4_4", + "CMT_TOP_NW4END3_3", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_WW4C1_2", + "CMT_PHASER_OUT_DB_ENCALIB1", + "CMT_TOP_SW4A2_9", + "CMT_TOP_IMUX22_0", + "CMT_TOP_LOGIC_OUTS_L_B16_11", + "CMT_TOP_SE2A1_1", + "CMT_PHASER_IN_DB_RCLK", + "CMT_TOP_NW2A3_9", + "CMT_TOP_WR1END0_4", + "CMT_TOP_EE2A0_4", + "CMT_TOP_WW4A1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_EE4C0_6", + "CMT_TOP_IMUX24_0", + "CMT_PHASER_IN_CA_TESTOUT3", + "CMT_PHASER_OUT_CA_SYNCIN", + "CMT_TOP_EL1BEG1_4", + "CMT_TOP_WW4B3_10", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_SW2A3_3", + "CMT_TOP_SW4END0_1", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_EE4B1_0", + "CMT_TOP_NE2A3_2", + "CMT_TOP_ER1BEG1_9", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_PHASERREF_PHASEROUT_D", + "CMT_PHY_CONTROL_PHYCTLWD3", + "CMT_TOP_EE4B1_6", + "CMT_TOP_LH3_9", + "CMT_TOP_BYP3_2", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_SE4BEG1_9", + "CMT_TOP_IMUX34_9", + "CMT_TOP_CLK0_2", + "CMT_TOP_SE4C1_11", + "CMT_TOP_LH10_1", + "CMT_TOP_EE2BEG2_3", + "CMT_PHY_CONTROL_TESTINPUT11", + "CMT_TOP_SE4BEG3_11", + "CMT_TOP_LOGIC_OUTS_L_B10_11", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_FAN3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_TOP_WW4A0_9", + "CMT_TOP_SW2A1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_IMUX3_4", + "CMT_TOP_ICLK_5", + "CMT_TOP_IMUX47_9", + "CMT_PHASER_REF_CLKOUT_TOHCLK", + "CMT_PHASER_REF_TESTOUT3", + "CMT_TOP_IMUX15_9", + "CMT_PHY_CONTROL_PHYCTLWD13", + "CMT_PHASER_OUT_DB_SCANMODEB", + "CMT_TOP_IMUX31_0", + "CMT_PHASER_IN_DB_DIVIDERST", + "CMT_TOP_IMUX29_8", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_LH2_3", + "CMT_TOP_WR1END1_9", + "CMT_TOP_IMUX28_10", + "CMT_TOP_NE4C1_4", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_IMUX2_4", + "CMT_PHASER_IN_D_WRENABLE_FIFO", + "CMT_PHASER_OUT_CA_TESTIN8", + "CMT_TOP_IMUX38_11", + "CMT_TOP_EE4C1_1", + "CMT_TOP_SW2A0_4", + "CMT_PHY_CONTROL_PHYCTLWD6", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_LH8_4", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_WW4END2_0", + "CMT_TOP_EE4C0_1", + "CMT_PHASER_OUT_CA_CTSBUS1", + "CMT_TOP_IMUX33_11", + "CMT_TOP_FAN5_8", + "CMT_TOP_WW4C1_0", + "CMT_TOP_LOGIC_OUTS_L_B11_11", + "CMT_TOP_EE2A3_9", + "CMT_TOP_LH10_7", + "CMT_TOP_SE4C0_1", + "CMT_TOP_NW4END3_9", + "CMT_TOP_WW4C1_7", + "CMT_TOP_SE2A0_5", + "CMT_TOP_EE2BEG1_9", + "CMT_PHASER_OUT_CA_TESTIN6", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_ER1BEG3_9", + "CMT_TOP_IMUX47_11", + "CMT_TOP_SE4BEG0_7", + "CMT_PHASER_UP_DQS_TO_PHASER_D", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BYP0_0", + "CMT_TOP_EE4B2_2", + "CMT_TOP_FAN7_7", + "CMT_PHASER_OUT_DB_TESTIN6", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_WW4A0_4", + "CMT_TOP_WW4A3_0", + "CMT_TOP_SE4C1_1", + "CMT_TOP_ER1BEG0_6", + "CMT_TOP_IMUX46_1", + "CMT_TOP_FAN6_11", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_IMUX30_8", + "CMT_TOP_SW2A1_0", + "CMT_TOP_CLK0_1", + "CMT_TOP_BYP5_4", + "CMT_PHY_CONTROL_TESTINPUT3", + "CMT_TOP_IMUX45_2", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_WW4C2_6", + "CMT_TOP_IMUX19_5", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_NW4END0_1", + "CMT_TOP_LH3_10", + "CMT_PHASERD_DTSBUS1", + "CMT_TOP_LH9_8", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_PHASER_IN_CA_STG1REGL4", + "CMT_TOP_NW2A2_7", + "CMT_TOP_SW4END0_5", + "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "CMT_TOP_IMUX29_1", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_IMUX9_5", + "CMT_PHY_CONTROL_PHYCTLWD26", + "CMT_TOP_SW4A0_2", + "CMT_TOP_WW2END1_5", + "CMT_TOP_WW2A2_8", + "CMT_TOP_OCLK_8", + "CMT_TOP_IMUX46_7", + "CMT_TOP_IMUX8_3", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_IMUX14_7", + "CMT_TOP_NW2A2_0", + "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "CMT_TOP_SE4C0_5", + "CMT_TOP_SW4END3_4", + "CMT_TOP_SE2A2_7", + "CMT_TOP_SW2A1_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_IMUX22_8", + "CMT_PHASERD_DQSBUS1", + "CMT_TOP_LH3_7", + "CMT_TOP_IMUX1_11", + "CMT_TOP_SE2A1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_9", + "CMT_TOP_IMUX43_8", + "CMT_TOP_LH10_5", + "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "CMT_PHASER_OUT_DB_DQSBUS0", + "CMT_TOP_NE4BEG2_5", + "CMT_PHASER_IN_CA_STG1REGL1", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_BLOCK_OUTS_L_B3_10", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_NE2A0_0", + "CMT_TOP_NE2A2_6", + "CMT_TOP_WW4C2_9", + "CMT_TOP_SW2A2_2", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_LH11_1", + "CMT_TOP_EE2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_LOGIC_OUTS_L_B20_10", + "CMT_PHASER_OUT_CA_FINEINC", + "CMT_TOP_WW2A2_4", + "CMT_TOP_EE4C1_10", + "CMT_TOP_LH5_2", + "CMT_TOP_IMUX17_8", + "CMT_TOP_IMUX36_7", + "CMT_TOP_BYP1_7", + "CMT_PHY_CONTROL_ECALIB1", + "CMT_TOP_IMUX4_5", + "CMT_TOP_EE4C0_4", + "CMT_TOP_EL1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B13_10", + "CMT_TOP_LOGIC_OUTS_L_B19_10", + "CMT_TOP_ICLK_7", + "CMT_TOP_NE4BEG0_10", + "CMT_TOP_LH11_3", + "CMT_PHASER_IN_CA_ENSTG1", + "CMT_TOP_IMUX32_1", + "CMT_TOP_IMUX11_4", + "CMT_TOP_IMUX9_10", + "CMT_TOP_SW2A2_4", + "CMT_TOP_EE4C3_7", + "CMT_PHASER_OUT_DB_TESTOUT0", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_WW4B3_0", + "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "CMT_TOP_IMUX10_5", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "CMT_TOP_WW2END1_1", + "CMT_TOP_FAN0_9", + "CMT_TOP_FAN1_7", + "CMT_TOP_IMUX23_2", + "CMT_PHASER_REF_TESTIN6", + "CMT_TOP_ICLK_6", + "CMT_TOP_IMUX5_0", + "CMT_TOP_EE4A2_9", + "CMT_TOP_IMUX22_1", + "CMT_TOP_WW4B0_8", + "CMT_TOP_IMUX42_11", + "CMT_TOP_OCLKDIV_6", + "CMT_PHASER_C_OCLK_TOIOI", + "CMT_TOP_LH2_9", + "CMT_TOP_NW4A3_1", + "CMT_TOP_IMUX27_0", + "CMT_PHY_CONTROL_TESTOUTPUT13", + "CMT_TOP_SE4C2_8", + "CMT_TOP_WW2END0_9", + "CMT_PHASER_OUT_CA_TESTIN9", + "CMT_TOP_SE4C2_4", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_SE2A2_1", + "CMT_TOP_NW4END1_5", + "CMT_TOP_EE2BEG0_7", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_PHASER_UP_PHASERREF_BELOW1", + "CMT_TOP_IMUX14_10", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX42_7", + "CMT_TOP_EL1BEG0_9", + "CMT_TOP_IMUX41_11", + "CMT_TOP_EE2BEG0_2", + "CMT_PHASERTOP_PHYCTLMSTREMPTY", + "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "CMT_TOP_WR1END1_11", + "CMT_TOP_IMUX35_7", + "CMT_PHY_CONTROL_TESTOUTPUT1", + "CMT_PHASER_OUT_DB_TESTIN8", + "CMT_PHY_CONTROL_IRANKB1", + "CMT_TOP_SW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_FAN3_7", + "CMT_TOP_LH9_9", + "CMT_TOP_SW4A1_1", + "CMT_TOP_SW2A0_8", + "CMT_TOP_IMUX28_9", + "CMT_TOP_EE4B3_7", + "CMT_TOP_WW2A3_11", + "CMT_TOP_IMUX44_3", + "CMT_TOP_IMUX31_10", + "CMT_TOP_EE4B3_10", + "CMT_TOP_NE4C1_9", + "CMT_TOP_SE2A0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_BYP2_3", + "CMT_TOP_IMUX12_10", + "CMT_TOP_IMUX40_3", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_IMUX11_6", + "CMT_TOP_EE4BEG0_1", + "CMT_R_TOP_UPPER_B_CLKIN2", + "CMT_TOP_IMUX39_10", + "CMT_PHASER_IN_CA_ISERDESRST", + "CMT_TOP_BYP4_2", + "CMT_TOP_NE4BEG3_8", + "CMT_TOP_IMUX1_10", + "CMT_PHASER_IN_CA_STG1REGL2", + "CMT_PHASERREF_PHASERIN_D", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_SW2A1_9", + "CMT_TOP_IMUX26_7", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "CMT_TOP_IMUX1_7", + "CMT_TOP_IMUX23_6", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_FAN5_10", + "CMT_TOP_IMUX6_8", + "CMT_PHASER_OUT_CA_OCLK", + "CMT_TOP_IMUX4_3", + "CMT_TOP_EE4C1_6", + "CMT_TOP_NW4END3_7", + "CMT_TOP_IMUX13_5", + "CMT_TOP_IMUX46_6", + "CMT_TOP_WW4END0_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LH12_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_CLK1_2", + "CMT_PHASER_IN_DB_RANKSELPHY1", + "CMT_TOP_WW4C2_10", + "CMT_PHASER_OUT_CA_MEMREFCLK", + "CMT_TOP_LOGIC_OUTS_L_B18_10", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_IMUX15_7", + "CMT_TOP_SW4END2_0", + "CMT_TOP_WW4B0_9", + "CMT_TOP_WW4END1_5", + "CMT_TOP_NW4A0_5", + "CMT_TOP_EE2A2_2", + "CMT_TOP_WW4A0_2", + "CMT_TOP_IMUX37_6", + "CMT_TOP_WL1END1_11", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_LH10_11", + "CMT_PHY_CONTROL_PHYCTLWD5", + "CMT_TOP_IMUX0_0", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_NW2A3_4", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_IMUX42_6", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_LH3_1", + "CMT_TOP_EE2BEG3_11", + "CMT_TOP_WL1END3_11", + "CMT_TOP_EE4C0_2", + "CMT_TOP_IMUX23_9", + "CMT_PHY_CONTROL_OBURSTPENDING0", + "CMT_TOP_IMUX35_6", + "CMT_TOP_SE2A3_11", + "CMT_PHASER_IN_DB_ENCALIB0", + "CMT_TOP_FAN3_6", + "CMT_TOP_SW4END2_1", + "CMT_PHASER_OUT_DB_DQSBUS1", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_EE4A2_11", + "CMT_TOP_LOGIC_OUTS_L_B17_9", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_WW2A1_3", + "CMT_TOP_FAN2_5", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_TOP_WW2END1_8", + "CMT_TOP_WR1END2_0", + "CMT_TOP_NE2A1_0", + "CMT_PHASER_OUT_CA_TESTIN1", + "CMT_TOP_LH1_8", + "CMT_TOP_WW2A0_7", + "CMT_TOP_LOGIC_OUTS_L_B17_10", + "CMT_PHASER_OUT_DB_TESTIN5", + "CMT_TOP_EE4BEG1_4", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_EE2BEG2_8", + "CMT_PHY_CONTROL_TESTOUTPUT0", + "CMT_TOP_SW4END0_2", + "CMT_TOP_SW4A0_6", + "CMT_TOP_BYP5_8", + "CMT_TOP_FAN5_4", + "CMT_TOP_IMUX41_7", + "CMT_TOP_IMUX25_2", + "CMT_TOP_EE4A3_1", + "CMT_TOP_IMUX12_8", + "CMT_TOP_WW2A3_3", + "CMT_TOP_IMUX1_6", + "CMT_TOP_IMUX21_2", + "CMT_TOP_CLK1_1", + "CMT_PHASERD_CTSBUS1", + "CMT_TOP_WW4A2_0", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_PHASER_IN_CA_TESTIN4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "CMT_TOP_WW4END3_10", + "CMT_TOP_IMUX16_9", + "CMT_TOP_FAN1_10", + "CMT_PHASER_OUT_DB_TESTIN11", + "CMT_TOP_NE2A2_0", + "CMT_TOP_IMUX17_11", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_WW2END2_7", + "CMT_PHASER_IN_DB_STG1REGL7", + "CMT_TOP_CTRL1_9", + "CMT_PHY_CONTROL_OBURSTPENDING3", + "CMT_TOP_SE4BEG1_1", + "CMT_TOP_NW4END3_5", + "CMT_TOP_IMUX21_5", + "CMT_TOP_WW4END3_4", + "CMT_TOP_WL1END0_8", + "CMT_FREQ_PHASER_REFMUX_1", + "CMT_TOP_SE2A3_0", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_WW2END1_9", + "CMT_TOP_NW4A3_6", + "CMT_PHY_CONTROL_PHYCTLWD18", + "CMT_TOP_SE4C1_7", + "CMT_TOP_WL1END3_10", + "CMT_PHASER_OUT_DB_RDENABLE", + "CMT_TOP_LOGIC_OUTS_L_B9_11", + "CMT_TOP_BYP0_8", + "CMT_TOP_IMUX2_11", + "CMT_TOP_EE4A3_3", + "CMT_TOP_LH10_6", + "CMT_TOP_NW4A3_2", + "CMT_TOP_NE4C0_11", + "CMT_TOP_LH3_4", + "CMT_TOP_LH8_0", + "CMT_TOP_IMUX24_6", + "CMT_TOP_IMUX45_8", + "CMT_TOP_IMUX33_7", + "CMT_TOP_IMUX28_7", + "CMT_TOP_ER1BEG0_10", + "CMT_TOP_FAN0_10", + "CMT_TOP_LH8_9", + "CMT_PHASER_OUT_CA_PHASEREFCLK", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_R_TOP_UPPER_B_CLKPLL4", + "CMT_TOP_WL1END1_9", + "CMT_TOP_EE4B0_5", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX15_10", + "CMT_TOP_CLK0_11", + "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_IMUX3_10", + "CMT_TOP_BYP3_8", + "CMT_TOP_IMUX17_0", + "CMT_TOP_NE2A3_1", + "CMT_PHASER_IN_CA_STG1REGR3", + "CMT_TOP_NW2A3_2", + "CMT_TOP_EE4B3_1", + "CMT_TOP_WW4B3_5", + "CMT_PHASER_OUT_CA_TESTIN2", + "CMT_PHASER_OUT_DB_TESTIN0", + "CMT_TOP_BYP1_9", + "CMT_TOP_SE4C2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_SE2A1_7", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_WL1END3_5", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_IMUX3_1", + "CMT_PHASER_IN_CA_STG1REGR7", + "CMT_TOP_WR1END2_1", + "CMT_TOP_NW4A1_4", + "CMT_TOP_WL1END2_11", + "CMT_TOP_WL1END1_10", + "CMT_TOP_IMUX20_3", + "CMT_TOP_BYP6_8", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX14_2", + "CMT_TOP_BYP4_4", + "CMT_TOP_IMUX2_3", + "CMT_TOP_CLK1_7", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_IMUX46_5", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_IMUX45_11", + "CMT_TOP_NW4END1_3", + "CMT_TOP_NW2A3_5", + "CMT_TOP_WR1END2_3", + "CMT_R_TOP_UPPER_B_CLKIN1", + "CMT_TOP_BYP2_6", + "CMT_TOP_BYP3_3", + "CMT_TOP_FAN6_2", + "CMT_TOP_NW2A2_3", + "CMT_TOP_IMUX40_4", + "CMT_TOP_MONITOR_P_11", + "CMT_TOP_WW4A0_10", + "CMT_TOP_IMUX47_6", + "CMT_TOP_SW4A3_4", + "CMT_TOP_FAN7_0", + "CMT_TOP_WW4A0_11", + "CMT_TOP_LH11_5", + "CMT_TOP_IMUX30_5", + "CMT_TOP_SE2A3_1", + "CMT_TOP_EE4A3_6", + "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "CMT_TOP_IMUX5_1", + "CMT_TOP_EE4BEG3_6", + "CMT_TOP_SE2A2_0", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_EE4B3_4", + "CMT_TOP_EE4C3_6", + "CMT_TOP_EE4C0_11", + "CMT_TOP_WW4B0_0", + "CMT_TOP_IMUX27_2", + "CMT_TOP_FAN0_8", + "CMT_TOP_EE4A2_6", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_FAN2_6", + "CMT_TOP_SE4BEG0_8", + "CMT_TOP_CLK0_9", + "PLL_CLK_FREQBB_REBUFOUT3", + "CMT_TOP_LH1_10", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_PHY_CONTROL_TESTINPUT12", + "CMT_TOP_SW2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_9", + "CMT_TOP_IMUX46_11", + "CMT_TOP_IMUX3_11", + "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_NW4END0_6", + "CMT_TOP_IMUX10_0", + "CMT_PHASER_OUT_DB_TESTIN7", + "CMT_PHY_CONTROL_PHYCTLWD12", + "CMT_TOP_IMUX43_4", + "CMT_PHASER_REF_TESTIN2", + "CMT_TOP_EE4A0_0", + "CMT_TOP_IMUX36_1", + "CMT_TOP_LH1_0", + "CMT_TOP_WW4A3_6", + "CMT_TOP_EE2A1_9", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_LOGIC_OUTS_L_B4_11", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_TOP_WW4A3_2", + "CMT_TOP_WW4B2_9", + "CMT_TOP_BYP0_5", + "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "CMT_TOP_ICLK_2", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_PHY_CONTROL_PHYCTLWD20", + "CMT_PHASER_OUT_DB_BURSTPENDING", + "CMT_TOP_FAN0_11", + "CMT_TOP_NE2A3_5", + "CMT_TOP_EL1BEG3_10", + "CMT_TOP_NE2A1_8", + "CMT_PHASER_IN_CA_RST", + "CMT_TOP_LH12_2", + "CMT_PHY_CONTROL_INRANKA1", + "CMT_PHASER_IN_CA_FINEINC", + "CMT_TOP_WW2A0_10", + "CMT_TOP_EE4C2_5", + "CMT_TOP_IMUX47_10", + "CMT_TOP_IMUX30_9", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_IMUX19_8", + "CMT_TOP_IMUX17_6", + "CMT_TOP_WW2A2_6", + "CMT_TOP_IMUX14_5", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_TOP_IMUX34_2", + "CMT_TOP_BYP1_6", + "CMT_TOP_SW4A2_2", + "CMT_TOP_EE2BEG2_10", + "CMT_TOP_WW4A2_8", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_IMUX39_5", + "CMT_TOP_NW4A2_7", + "CMT_TOP_IMUX38_1", + "CMT_TOP_WW2A0_8", + "CMT_TOP_CTRL1_4", + "CMT_TOP_SE2A0_11", + "CMT_TOP_CTRL0_10", + "CMT_TOP_NE4C2_0", + "CMT_TOP_IMUX8_1", + "CMT_TOP_OCLK_0", + "CMT_TOP_NE4C2_7", + "CMT_TOP_IMUX20_8", + "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "CMT_PHY_CONTROL_IRANKA1", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SE4C3_4", + "CMT_PHY_CONTROL_PHYCTLWD25", + "CMT_TOP_SE4C3_3", + "CMT_TOP_IMUX12_3", + "CMT_TOP_CLK0_5", + "CMT_TOP_WW2END1_4", + "CMT_PHASER_IN_CA_TESTIN11", + "CMT_TOP_NW2A1_5", + "CMT_TOP_IMUX16_2", + "CMT_TOP_MONITOR_N_10", + "CMT_TOP_BYP2_5", + "CMT_TOP_WR1END3_11", + "CMT_TOP_IMUX40_2", + "CMT_TOP_WW4B2_8", + "CMT_PHASER_IN_CA_STG1REGL6", + "CMT_TOP_EE4B1_2", + "CMT_TOP_SE4C1_2", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_SW4A1_9", + "CMT_TOP_FAN0_6", + "CMT_TOP_SW4END2_8", + "CMT_PHY_CONTROL_IRANKC0", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_PHASER_OUT_CA_TESTIN3", + "CMT_TOP_IMUX18_7", + "CMT_TOP_NW4A1_11", + "CMT_TOP_SE4BEG3_2", + "CMT_TOP_EE2BEG1_8", + "CMT_TOP_NE2A2_10", + "CMT_TOP_EE2BEG1_11", + "CMT_PHASER_OUT_CA_COUNTERREADEN", + "CMT_TOP_WW4A2_5", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX44_2", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_CTRL0_0", + "CMT_PHASER_REF_TESTIN7", + "CMT_TOP_IMUX1_8", + "CMT_TOP_IMUX38_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_NW2A1_0", + "CMT_TOP_WW4B3_8", + "CMT_TOP_EE4BEG2_10", + "CMT_PHASER_IN_CA_SCANOUT", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4BEG3_6", + "CMT_PHASER_IN_DB_STG1REGR1", + "CMT_TOP_IMUX38_0", + "CMT_TOP_SW2A2_1", + "CMT_TOP_NE4C2_9", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "CMT_TOP_SE4BEG1_11", + "CMT_TOP_BYP1_3", + "CMT_TOP_CTRL0_6", + "CMT_TOP_EE4A3_10", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_IMUX17_3", + "CMT_TOP_NW2A3_10", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX28_2", + "CMT_TOP_EE2A0_9", + "CMT_TOP_IMUX21_8", + "CMT_PHY_CONTROL_RESET", + "CMT_PHASER_REF_TESTIN0", + "CMT_TOP_EL1BEG3_11", + "CMT_TOP_IMUX42_2", + "CMT_TOP_WW2A3_6", + "CMT_TOP_WW4B0_4", + "CMT_TOP_SE2A2_5", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_TOP_IMUX38_9", + "CMT_TOP_BYP2_10", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EL1BEG0_10", + "CMT_TOP_EE4B1_11", + "CMT_TOP_OCLKDIV_0", + "CMT_PHASER_REF_TESTOUT0", + "CMT_TOP_EE2BEG2_7", + "CMT_PHASER_IN_DB_TESTIN0", + "CMT_TOP_ICLK_0", + "CMT_PHY_CONTROL_PHYCTLWD31", + "CMT_TOP_NW4END1_2", + "CMT_TOP_WW2A2_10", + "CMT_TOP_WW4END1_9", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX31_7", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_NW2A1_3", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX47_2", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_NE2A3_0", + "CMT_TOP_IMUX13_9", + "CMT_TOP_LH10_4", + "CMT_TOP_BYP0_2", + "CMT_TOP_CLK0_3", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_SW4A0_11", + "CMT_TOP_LOGIC_OUTS_L_B13_11", + "CMT_PHASER_IN_DB_SELCALORSTG1", + "CMT_TOP_SW2A2_7", + "CMT_TOP_EL1BEG2_10", + "CMT_TOP_IMUX29_9", + "CMT_PHY_CONTROL_TESTOUTPUT15", + "CMT_PHASER_IN_DB_SCANIN", + "CMT_TOP_EE4B3_9", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_IMUX25_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_ICLK_10", + "CMT_TOP_NE4C1_7", + "CMT_TOP_NW2A2_11", + "CMT_TOP_EE4C3_8", + "CMT_PHY_CONTROL_INRANKB1", + "CMT_TOP_IMUX4_2", + "CMT_TOP_NW4END0_0", + "CMT_PHASER_IN_CA_SYSCLK", + "CMT_TOP_IMUX11_9", + "CMT_TOP_EE4B2_10", + "CMT_TOP_IMUX0_6", + "CMT_PHASER_OUT_DB_DTSBUS1", + "CMT_TOP_WW4B0_1", + "CMT_PHY_CONTROL_REFDLLLOCK", + "CMT_TOP_FAN1_5", + "CMT_TOP_WL1END0_11", + "CMT_TOP_EE2A1_8", + "CMT_PHASER_IN_CA_TESTIN5", + "CMT_TOP_NE4C3_10", + "CMT_PHASER_IN_DB_STG1REGL3", + "CMT_PHY_CONTROL_PHYCTLWD11", + "CMT_PHASER_OUT_DB_DIVIDERST", + "CMT_TOP_OCLK_10", + "CMT_TOP_WW2END2_2", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_FAN4_7", + "CMT_PHASER_OUT_DB_SCANCLK", + "CMT_TOP_IMUX27_11", + "CMT_TOP_IMUX36_6", + "CMT_TOP_WW2END0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_EE4BEG3_11", + "CMT_PHY_CONTROL_ECALIB0", + "CMT_PHASER_OUT_CA_TESTIN5", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_EE4B3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_NW4A0_10", + "CMT_PHASER_IN_CA_STG1REGR5", + "CMT_PHY_CONTROL_TESTOUTPUT10", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_LH8_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_EL1BEG0_8", + "CMT_PHASER_OUT_CA_SCANOUT", + "CMT_TOP_MONITOR_P_10", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_NE4C0_9", + "CMT_PHASER_OUT_CA_RST", + "CMT_TOP_SW4A3_8", + "CMT_TOP_SW2A1_10", + "CMT_TOP_WW2A0_6", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_WL1END2_1", + "CMT_TOP_LH8_10", + "CMT_TOP_NE4C0_0", + "CMT_TOP_IMUX29_7", + "CMT_TOP_EE4B0_4", + "CMT_PHASER_IN_CA_STG1LOAD", + "CMT_TOP_WR1END3_6", + "CMT_TOP_LOGIC_OUTS_L_B6_11", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_PHASER_IN_DB_SCANOUT", + "CMT_TOP_BLOCK_OUTS_L_B3_9", + "CMT_PHY_CONTROL_PHYCTLWD9", + "CMT_TOP_WW4B2_2", + "CMT_PHASER_IN_CA_TESTOUT1", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_LH11_4", + "CMT_TOP_LH6_6", + "CMT_PHASER_IN_DB_TESTIN4", + "CMT_TOP_NE2A1_11", + "CMT_TOP_NW2A3_7", + "CMT_TOP_WW4END0_5", + "CMT_TOP_FAN4_8", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_PHASER_TOP_SYNC_BB", + "CMT_TOP_IMUX22_7", + "CMT_PHY_CONTROL_PHYCTLWD19", + "CMT_PHASER_C_OCLK90_TOIOI", + "CMT_TOP_WR1END1_2", + "CMT_TOP_IMUX2_6", + "CMT_TOP_LOGIC_OUTS_L_B12_9", + "CMT_TOP_BYP4_8", + "CMT_PHASER_UP_PHASERREF_ABOVE0", + "CMT_TOP_SE4C3_5", + "CMT_TOP_BLOCK_OUTS_L_B2_9", + "CMT_TOP_IMUX15_4", + "CMT_TOP_IMUX39_9", + "CMT_PHASER_IN_CA_BURSTPENDING", + "CMT_TOP_IMUX4_9", + "CMT_TOP_BYP5_5", + "CMT_TOP_ICLK_1", + "CMT_TOP_WW2END1_10", + "CMT_TOP_IMUX0_1", + "CMT_TOP_BYP6_7", + "CMT_PHASER_OUT_CA_TESTIN11", + "CMT_TOP_WW4B2_6", + "CMT_TOP_IMUX32_7", + "CMT_TOP_LH3_3", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_SW4A2_8", + "CMT_TOP_WL1END3_7", + "CMT_FREQ_BB_PREF_IN1", + "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "CMT_TOP_SW4A1_7", + "CMT_TOP_SW2A3_5", + "CMT_TOP_EE4C2_9", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_WW4END1_8", + "CMT_TOP_OCLK1X_90_1", + "CMT_PHY_CONTROL_PHYCTLWD4", + "CMT_TOP_SW4A3_3", + "CMT_TOP_FAN1_9", + "CMT_TOP_WW4A2_2", + "CMT_TOP_IMUX28_1", + "CMT_TOP_IMUX46_4", + "CMT_TOP_WW2END3_4", + "CMT_TOP_EE4B1_5", + "CMT_TOP_EE4B0_6", + "CMT_TOP_WR1END0_11", + "CMT_TOP_SW2A0_0", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_PHASER_IN_CA_ICLKDIV", + "CMT_TOP_NW4A1_0", + "CMT_PHY_CONTROL_AUXOUTPUT2", + "CMT_TOP_WW4B0_7", + "CMT_TOP_IMUX33_9", + "CMT_TOP_CLK1_4", + "CMT_TOP_NW4END2_6", + "CMT_TOP_IMUX17_10", + "CMT_R_PHASER_OUT_C_RDENABLE_FIFO", + "CMT_TOP_BYP5_0", + "CMT_PHASER_REF_TESTOUT7", + "CMT_TOP_NE4C1_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "CMT_TOP_WW4END1_1", + "CMT_TOP_NW4A2_11", + "CMT_TOP_IMUX37_0", + "CMT_TOP_WL1END3_1", + "CMT_TOP_IMUX16_8", + "CMT_PHASER_OUT_DB_TESTIN15", + "CMT_PHASER_OUT_DB_OSERDESRST", + "CMT_TOP_IMUX39_2", + "CMT_TOP_IMUX37_7", + "CMT_TOP_IMUX16_3", + "CMT_PHY_CONTROL_PLLLOCK", + "CMT_PHASER_IN_DB_STG1LOAD", + "CMT_TOP_IMUX1_2", + "CMT_PHASER_IN_CA_EDGEADV", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_TOP_IMUX6_6", + "CMT_PHASER_OUT_CA_DTSBUS1", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_WW4B2_4", + "CMT_TOP_ER1BEG2_2", + "CMT_PHASER_IN_DB_STG1REGR4", + "CMT_TOP_IMUX11_10", + "CMT_TOP_IMUX17_7", + "CMT_TOP_CTRL0_8", + "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "CMT_PHASER_REF_CLKIN", + "CMT_PHASER_IN_CA_TESTOUT2", + "CMT_TOP_IMUX35_9", + "CMT_PHASER_IN_DB_RSTDQSFIND", + "CMT_TOP_OCLK1X_90_8", + "CMT_PHASER_REF_TESTOUT2", + "CMT_TOP_IMUX29_2", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_ER1BEG0_9", + "CMT_TOP_BYP6_1", + "CMT_TOP_EE4BEG2_2", + "CMT_PHASER_IN_CA_PHASEREFCLK", + "CMT_TOP_FAN1_4", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW2A0_5", + "CMT_TOP_NE2A1_3", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_TOP_NW2A0_3", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_SE2A1_5", + "CMT_TOP_LH4_9", + "CMT_TOP_NW4A1_8", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_NW4END3_2", + "CMT_TOP_IMUX39_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_SW4END1_10", + "CMT_TOP_NW4END0_7", + "CMT_TOP_IMUX44_9", + "CMT_TOP_SW4END0_4", + "CMT_TOP_CTRL1_2", + "CMT_TOP_WW4END2_2", + "CMT_TOP_IMUX38_10", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4C2_10", + "CMT_TOP_IMUX38_2", + "CMT_TOP_BYP3_7", + "CMT_TOP_LH3_0", + "CMT_PHY_CONTROL_INRANKD0", + "CMT_PHASER_REF_CLKOUT", + "CMT_TOP_EE4BEG3_9", + "CMT_TOP_NE4BEG2_6", + "CMT_TOP_ICLK_11", + "CMT_TOP_OCLK_3", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX13_11", + "CMT_TOP_IMUX11_2", + "CMT_TOP_WW4A2_10", + "CMT_TOP_SW4A0_5", + "CMT_TOP_EE4B2_3", + "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "CMT_TOP_IMUX9_7", + "CMT_TOP_EE2A2_3", + "CMT_TOP_WR1END3_1", + "CMT_TOP_WW2A0_0", + "CMT_TOP_WR1END0_5", + "CMT_TOP_ER1BEG2_8", + "CMT_PHASER_REF_PWRDWN", + "CMT_TOP_WW4C3_10", + "CMT_TOP_NW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B6_9", + "CMT_TOP_EE4C0_10", + "CMT_TOP_WW4B2_5", + "CMT_PHY_CONTROL_PHYCTLWD0", + "CMT_TOP_IMUX41_8", + "CMT_TOP_SW2A3_8", + "CMT_TOP_SW4END1_9", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_LH4_10", + "CMT_TOP_NE4BEG0_11", + "CMT_TOP_WW4B3_6", + "CMT_TOP_NW4END3_10", + "CMT_TOP_WW4END3_8", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX33_2", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_WW2END2_8", + "CMT_TOP_WW4C0_11", + "CMT_TOP_NE2A0_7", + "CMT_TOP_SE2A0_10", + "CMT_PHASER_OUT_DB_SYSCLK", + "CMT_TOP_BYP0_7", + "CMT_TOP_IMUX0_11", + "CMT_TOP_NE2A1_7", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_PHY_CONTROL_PHYCLK", + "CMT_TOP_WW2A3_10", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_NW4A3_8", + "CMT_TOP_EE4A1_11", + "CMT_TOP_WW4C0_5", + "CMT_TOP_BYP4_9", + "CMT_TOP_IMUX8_7", + "CMT_TOP_NE2A0_1", + "CMT_TOP_WW4END0_0", + "CMT_TOP_FAN5_2", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_WW4C1_10", + "CMT_TOP_IMUX39_8", + "CMT_TOP_NE4C1_2", + "CMT_TOP_IMUX30_4", + "CMT_PHASER_IN_CA_MEMREFCLK", + "CMT_TOP_BYP1_5", + "CMT_TOP_EE4C3_4", + "CMT_TOP_IMUX10_8", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_TOP_NE2A2_11", + "CMT_TOP_IMUX43_10", + "CMT_TOP_EE4A3_11", + "CMT_PHASER_OUT_CA_TESTIN12", + "CMT_TOP_EE2A2_10", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_IMUX44_8", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_WL1END0_3", + "CMT_TOP_IMUX19_4", + "CMT_TOP_IMUX18_8", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_NE4C2_10", + "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "CMT_TOP_LH10_9", + "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "CMT_TOP_LOGIC_OUTS_L_B10_9", + "CMT_PHASER_IN_C_ICLK", + "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "CMT_TOP_LH7_4", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_NW4A3_5", + "CMT_PHY_CONTROL_PHYCTLWD16", + "CMT_PHASER_IN_CA_ICLK", + "CMT_TOP_NW4END0_3", + "CMT_TOP_IMUX29_4", + "CMT_PHY_CONTROL_PCENABLECALIB0", + "CMT_TOP_NW2A0_6", + "CMT_TOP_SE2A2_2", + "CMT_TOP_WW4C2_7", + "CMT_TOP_IMUX37_9", + "CMT_TOP_WW4C0_4", + "CMT_TOP_BYP5_9", + "CMT_TOP_EE4BEG3_4", + "CMT_PHY_CONTROL_PHYCTLWD28", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "CMT_TOP_WW4A2_1", + "CMT_TOP_LH6_9", + "CMT_TOP_SE4C2_11", + "CMT_TOP_LH10_3", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_WW4C3_2", + "CMT_TOP_IMUX38_5", + "CMT_TOP_IMUX8_8", + "CMT_TOP_FAN4_6", + "CMT_TOP_IMUX47_7", + "CMT_TOP_EE2A1_1", + "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "CMT_PHY_CONTROL_TESTINPUT7", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_ER1BEG1_10", + "CMT_TOP_FAN7_8", + "CMT_TOP_FAN6_3", + "CMT_TOP_EE4B0_0", + "CMT_PHASER_IN_DB_ENCALIB1", + "CMT_TOP_IMUX34_5", + "CMT_TOP_IMUX31_5", + "CMT_TOP_WW4END1_11", + "CMT_TOP_IMUX0_7", + "CMT_TOP_IMUX2_1", + "CMT_TOP_ER1BEG3_8" + ], + "pips": { + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLKDIV->>CMT_PHASER_C_ICLKDIV_TOIOI": { + "src_wire": "CMT_PHASER_IN_C_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_CA_SYNCIN": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B16_5": { + "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX41_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_FINEINC": { + "src_wire": "CMT_TOP_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_6": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_9->CMT_PHY_CONTROL_PHYCTLWD7": { + "src_wire": "CMT_TOP_IMUX46_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_9->CMT_PHY_CONTROL_PHYCTLWD2": { + "src_wire": "CMT_TOP_IMUX44_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_D_WRENABLE_FIFO": { + "src_wire": "CMT_PHASER_IN_DB_WRENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_WRENABLE_FIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { + "src_wire": "CMT_TOP_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_7": { + "src_wire": "CMT_PHASER_C_OCLK90_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS0->CMT_PHASERD_CTSBUS0": { + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_CTSBUS0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B15_0": { + "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_10->CMT_PHY_CONTROL_PHYCTLWD18": { + "src_wire": "CMT_TOP_IMUX15_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD18", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS0->CMT_PHASERD_DTSBUS0": { + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DTSBUS0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_RDENABLE->CMT_R_PHASER_OUT_C_RDENABLE_FIFO": { + "src_wire": "CMT_PHASER_OUT_CA_RDENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_R_PHASER_OUT_C_RDENABLE_FIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX1_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX1_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX3_4->CMT_PHASER_IN_CA_RANKSEL1": { + "src_wire": "CMT_TOP_IMUX3_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKA1->CMT_PHY_CONTROL_IRANKA1": { + "src_wire": "CMT_PHY_CONTROL_INRANKA1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKA1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX14_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_D_RCLK3": { + "src_wire": "CMT_PHASER_IN_DB_RCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_RCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_0": { + "src_wire": "CMT_FREQ_BB_PREF_IN0", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { + "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_2": { + "src_wire": "CMT_FREQ_BB_PREF_IN2", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKD1->CMT_PHY_CONTROL_IRANKD1": { + "src_wire": "CMT_PHY_CONTROL_INRANKD1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKD1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT1->CMT_TOP_LOGIC_OUTS_L_B21_9": { + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLEMPTY->CMT_PHASERTOP_PHYCTLEMPTY": { + "src_wire": "CMT_PHY_CONTROL_PHYCTLEMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERTOP_PHYCTLEMPTY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX9_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_10": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASERIN_D->CMT_PHASER_IN_DB_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_PHASERIN_D", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX3_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { + "src_wire": "CMT_TOP_IMUX3_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { + "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_10->CMT_PHY_CONTROL_PHYCTLWD19": { + "src_wire": "CMT_TOP_IMUX31_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD19", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B6_3": { + "src_wire": "CMT_PHASER_IN_CA_DQSFOUND", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ICLKDIV->CMT_R_PHASER_IN_D_WRCLK_TOFIFO": { + "src_wire": "CMT_PHASER_IN_DB_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_R_PHASER_IN_D_WRCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B9_6": { + "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_5->CMT_PHASER_OUT_DB_FINEINC": { + "src_wire": "CMT_TOP_IMUX43_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_0": { + "src_wire": "CMT_FREQ_BB_PREF_IN1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { + "src_wire": "CMT_TOP_IMUX34_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLKDIV->CMT_R_PHASER_OUT_C_RDCLK_FIFO": { + "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_R_PHASER_OUT_C_RDCLK_FIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_10": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B15_3": { + "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX19_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_10->CMT_PHY_CONTROL_REFDLLLOCK": { + "src_wire": "CMT_TOP_IMUX4_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_REFDLLLOCK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT2->CMT_TOP_LOGIC_OUTS_L_B17_10": { + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_3->CMT_PHASER_IN_CA_RSTDQSFIND": { + "src_wire": "CMT_TOP_IMUX0_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC0->CMT_PHASER_IN_CA_RANKSELPHY0": { + "src_wire": "CMT_PHY_CONTROL_IRANKC0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_11->CMT_PHY_CONTROL_PHYCTLWD23": { + "src_wire": "CMT_TOP_IMUX20_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD23", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING3->CMT_PHY_CONTROL_IBURSTPENDING3": { + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING3", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX18_2->CMT_PHASER_OUT_CA_ENCALIB0": { + "src_wire": "CMT_TOP_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIB0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_TMUXOUT->CMT_PHASER_REF_TMUXOUT_TOHCLK": { + "src_wire": "CMT_PHASER_REF_TMUXOUT", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_TMUXOUT_TOHCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_0->CMT_PHASER_UP_BUFMRCE_CE0": { + "src_wire": "CMT_TOP_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_1": { + "src_wire": "CMT_FREQ_BB_PREF_IN1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING2->CMT_PHY_CONTROL_IBURSTPENDING2": { + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING2", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY->CMT_PHY_CONTROL_PHYCTLMSTREMPTY": { + "src_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHY_CONTROL_SYNCIN": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX16_6->CMT_PHASER_OUT_DB_COARSEINC": { + "src_wire": "CMT_TOP_IMUX16_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKOUT->CMT_PHASER_REF_CLKOUT_TOHCLK": { + "src_wire": "CMT_PHASER_REF_CLKOUT", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_CLKOUT_TOHCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { + "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_CA_RCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90->>CMT_PHASER_C_OCLK90_TOIOI": { + "src_wire": "CMT_PHASER_OUT_C_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_OCLK90_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B6_6": { + "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_11->CMT_PHY_CONTROL_PHYCTLWD30": { + "src_wire": "CMT_TOP_IMUX15_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD30", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_11->CMT_PHY_CONTROL_PHYCTLWD28": { + "src_wire": "CMT_TOP_IMUX30_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD28", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_6->CMT_PHASER_IN_DB_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX19_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_11->CMT_PHY_CONTROL_PHYCTLWD22": { + "src_wire": "CMT_TOP_IMUX4_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD22", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_9->CMT_PHY_CONTROL_PHYCTLWD3": { + "src_wire": "CMT_TOP_IMUX13_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV->>CMT_PHASER_C_OCLKDIV_TOIOI": { + "src_wire": "CMT_PHASER_OUT_C_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX12_7->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX12_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B3_3": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_8": { + "src_wire": "CMT_PHASER_IN_DB_ISERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX8_7->CMT_PHASER_IN_DB_RSTDQSFIND": { + "src_wire": "CMT_TOP_IMUX8_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX13_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_6->CMT_PHASER_IN_DB_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX46_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_10->CMT_PHY_CONTROL_PHYCTLWD13": { + "src_wire": "CMT_TOP_IMUX13_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_9->CMT_PHY_CONTROL_PLLLOCK": { + "src_wire": "CMT_TOP_IMUX43_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PLLLOCK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT3->>CMT_FREQ_BB_PREF_IN3": { + "src_wire": "PLL_CLK_FREQBB_REBUFOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_10->CMT_PHY_CONTROL_PHYCLK": { + "src_wire": "CMT_TOP_CLK0_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_9->CMT_PHY_CONTROL_PHYCTLWD9": { + "src_wire": "CMT_TOP_IMUX31_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX17_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B23_2": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_D_OCLK": { + "src_wire": "CMT_PHASER_OUT_DB_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT3->CMT_TOP_LOGIC_OUTS_L_B17_11": { + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { + "src_wire": "CMT_TOP_IMUX0_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_CA_SYNCIN": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>CMT_FREQ_PHASER_REFMUX_2": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B6_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX32_4->CMT_PHASER_IN_CA_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX32_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASEROUT_D->CMT_PHASER_OUT_DB_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { + "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { + "src_wire": "CMT_TOP_IMUX14_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLKDIV->CMT_R_PHASER_OUT_D_RDCLK_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_11->CMT_PHY_CONTROL_PHYCTLWD26": { + "src_wire": "CMT_TOP_IMUX45_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD26", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB0->CMT_PHY_CONTROL_ECALIB0": { + "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASERIN_C->CMT_PHASER_IN_CA_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_PHASERIN_C", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_2->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { + "src_wire": "CMT_TOP_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_7->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX27_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B3_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_TOP_SYNC_BB->>CMT_PHASERTOP_PHYCTLMSTREMPTY": { + "src_wire": "CMT_PHASER_TOP_SYNC_BB", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { + "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_8": { + "src_wire": "CMT_PHASER_IN_DB_DQSFOUND", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_1": { + "src_wire": "CMT_FREQ_BB_PREF_IN0", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_D->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_D", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX14_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_REF_CLKIN": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_CLKIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_11->CMT_PHY_CONTROL_PHYCTLWD29": { + "src_wire": "CMT_TOP_IMUX46_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD29", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_5->CMT_PHASER_OUT_DB_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX11_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { + "src_wire": "CMT_TOP_IMUX41_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_4->CMT_PHASER_OUT_DB_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX19_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_9->CMT_PHY_CONTROL_PHYCTLWD4": { + "src_wire": "CMT_TOP_IMUX45_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_9->CMT_PHY_CONTROL_PHYCTLWD5": { + "src_wire": "CMT_TOP_IMUX14_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKA0->CMT_PHY_CONTROL_IRANKA0": { + "src_wire": "CMT_PHY_CONTROL_INRANKA0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKA0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ICLKDIV->CMT_R_PHASER_IN_C_WRCLK_FIFO": { + "src_wire": "CMT_PHASER_IN_CA_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_R_PHASER_IN_C_WRCLK_FIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_2": { + "src_wire": "CMT_FREQ_BB_PREF_IN0", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_C_WRENABLE_FIFO": { + "src_wire": "CMT_PHASER_IN_CA_WRENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_WRENABLE_FIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_6->CMT_PHASER_OUT_DB_ENCALIB0": { + "src_wire": "CMT_TOP_IMUX17_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIB0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B15_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT2->>CMT_FREQ_BB_PREF_IN2": { + "src_wire": "PLL_CLK_FREQBB_REBUFOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT0->>PLL_CLK_FREQBB_REBUFOUT0": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_5->CMT_PHASER_OUT_DB_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX27_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { + "src_wire": "CMT_TOP_IMUX15_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_8->CMT_PHASER_IN_DB_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_8", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B9_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_10->CMT_PHY_CONTROL_PHYCTLWD11": { + "src_wire": "CMT_TOP_IMUX20_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT0->>CMT_FREQ_BB_PREF_IN0": { + "src_wire": "PLL_CLK_FREQBB_REBUFOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLREADY->CMT_TOP_LOGIC_OUTS_L_B17_8": { + "src_wire": "CMT_PHY_CONTROL_PHYCTLREADY", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING0->CMT_PHY_CONTROL_IBURSTPENDING0": { + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { + "src_wire": "CMT_TOP_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX44_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_7->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX43_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_9->CMT_PHY_CONTROL_PHYCTLWD1": { + "src_wire": "CMT_TOP_IMUX20_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_2": { + "src_wire": "CMT_FREQ_BB_PREF_IN1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_2": { + "src_wire": "CMT_FREQ_BB_PREF_IN3", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB1->CMT_PHY_CONTROL_ECALIB1": { + "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLK->>CMT_PHASER_C_ICLK_TOIOI": { + "src_wire": "CMT_PHASER_IN_C_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKC0->CMT_PHY_CONTROL_IRANKC0": { + "src_wire": "CMT_PHY_CONTROL_INRANKC0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKC0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD1->CMT_PHASER_IN_DB_RANKSELPHY1": { + "src_wire": "CMT_PHY_CONTROL_IRANKD1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_11->CMT_PHY_CONTROL_PHYCTLWRENABLE": { + "src_wire": "CMT_TOP_IMUX47_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWRENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_11->CMT_PHY_CONTROL_PHYCTLWD24": { + "src_wire": "CMT_TOP_IMUX44_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD24", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_FINEINC": { + "src_wire": "CMT_TOP_IMUX30_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT3->>PLL_CLK_FREQBB_REBUFOUT3": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLFULL->CMT_TOP_LOGIC_OUTS_L_B17_9": { + "src_wire": "CMT_PHY_CONTROL_PHYCTLFULL", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B18_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B7_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_10->CMT_PHY_CONTROL_PHYCTLWD15": { + "src_wire": "CMT_TOP_IMUX14_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING1->CMT_PHY_CONTROL_OBURSTPENDING1": { + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_1": { + "src_wire": "CMT_FREQ_BB_PREF_IN3", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { + "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_9->CMT_PHY_CONTROL_PHYCTLWD0": { + "src_wire": "CMT_TOP_IMUX4_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_CLK1_0->>CMT_L_TOP_UPPER_B_CLKINT_3": { + "src_wire": "CMT_TOP_CLK1_0", + "is_pseudo": "0", + "dst_wire": "CMT_L_TOP_UPPER_B_CLKINT_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_9->CMT_PHY_CONTROL_PHYCTLWD10": { + "src_wire": "CMT_TOP_IMUX47_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B21_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING0->CMT_PHY_CONTROL_OBURSTPENDING0": { + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_C_RCLK2": { + "src_wire": "CMT_PHASER_IN_CA_RCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_RCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING1->CMT_PHY_CONTROL_IBURSTPENDING1": { + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_3": { + "src_wire": "CMT_PHASER_IN_CA_ISERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDCLK_FIFO->CMT_PHASER_OUT_C_OCLKDIV": { + "src_wire": "CMT_R_PHASER_OUT_C_RDCLK_FIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_OCLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_C_ICLK": { + "src_wire": "CMT_PHASER_IN_CA_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_ICLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKC1->CMT_PHY_CONTROL_IRANKC1": { + "src_wire": "CMT_PHY_CONTROL_INRANKC1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKC1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_6": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_10->CMT_PHY_CONTROL_PHYCTLWD20": { + "src_wire": "CMT_TOP_IMUX47_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD20", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_D_WRCLK_TOFIFO->CMT_PHASER_IN_D_ICLKDIV": { + "src_wire": "CMT_R_PHASER_IN_D_WRCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_ICLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKB1->CMT_PHY_CONTROL_IRANKB1": { + "src_wire": "CMT_PHY_CONTROL_INRANKB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKB1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_11": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX2_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX2_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_4->CMT_PHASER_IN_CA_RST": { + "src_wire": "CMT_TOP_IMUX11_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { + "src_wire": "CMT_TOP_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD0->CMT_PHASER_IN_DB_RANKSELPHY0": { + "src_wire": "CMT_PHY_CONTROL_IRANKD0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B1_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_9": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B21_3": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKB0->CMT_PHY_CONTROL_IRANKB0": { + "src_wire": "CMT_PHY_CONTROL_INRANKB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKB0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC1->CMT_PHASER_IN_CA_RANKSELPHY1": { + "src_wire": "CMT_PHY_CONTROL_IRANKC1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_10->CMT_PHY_CONTROL_PHYCTLWD14": { + "src_wire": "CMT_TOP_IMUX45_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_9->CMT_PHY_CONTROL_PHYCTLWD8": { + "src_wire": "CMT_TOP_IMUX15_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_2": { + "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_11->CMT_PHY_CONTROL_RESET": { + "src_wire": "CMT_TOP_IMUX11_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_RESET", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT1->>CMT_FREQ_BB_PREF_IN1": { + "src_wire": "PLL_CLK_FREQBB_REBUFOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_DB_SYNCIN": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_11->CMT_PHY_CONTROL_PHYCTLWD25": { + "src_wire": "CMT_TOP_IMUX13_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD25", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASEROUT_C->CMT_PHASER_OUT_CA_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT0->CMT_TOP_LOGIC_OUTS_L_B3_9": { + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_C_OCLK": { + "src_wire": "CMT_PHASER_OUT_CA_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_10->CMT_PHY_CONTROL_PHYCTLWD17": { + "src_wire": "CMT_TOP_IMUX46_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD17", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_RANKSEL0": { + "src_wire": "CMT_TOP_IMUX34_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_2->CMT_PHASER_OUT_CA_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_C_OCLK1X_90": { + "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_OCLK1X_90", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_11->CMT_PHY_CONTROL_PHYCTLWD21": { + "src_wire": "CMT_TOP_IMUX43_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD21", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_3->CMT_PHASER_IN_CA_FINEINC": { + "src_wire": "CMT_TOP_IMUX47_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT2->>PLL_CLK_FREQBB_REBUFOUT2": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY->>CMT_PHASER_TOP_SYNC_BB": { + "src_wire": "CMT_PHASERTOP_PHYCTLEMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_TOP_SYNC_BB", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX32_6->CMT_PHASER_OUT_DB_COARSEENABLE": { + "src_wire": "CMT_TOP_IMUX32_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { + "src_wire": "CMT_TOP_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX44_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_1": { + "src_wire": "CMT_FREQ_BB_PREF_IN2", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { + "src_wire": "CMT_TOP_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>CMT_FREQ_PHASER_REFMUX_0": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_10->CMT_PHY_CONTROL_PHYCTLWD16": { + "src_wire": "CMT_TOP_IMUX30_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD16", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS1->CMT_PHASERD_DTSBUS1": { + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DTSBUS1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { + "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX39_7->CMT_PHASER_IN_DB_RST": { + "src_wire": "CMT_TOP_IMUX39_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_6->CMT_PHASER_OUT_DB_RST": { + "src_wire": "CMT_TOP_IMUX34_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX22_10->CMT_PHY_CONTROL_WRITECALIBENABLE": { + "src_wire": "CMT_TOP_IMUX22_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_WRITECALIBENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS0->CMT_PHASERD_DQSBUS0": { + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DQSBUS0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { + "src_wire": "CMT_TOP_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX23_3->CMT_PHASER_IN_CA_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS1->CMT_PHASERD_DQSBUS1": { + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DQSBUS1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_6->CMT_PHASER_OUT_DB_EDGEADV": { + "src_wire": "CMT_TOP_IMUX9_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_4->CMT_PHASER_IN_CA_EDGEADV": { + "src_wire": "CMT_TOP_IMUX41_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_11->CMT_PHY_CONTROL_PHYCTLWD31": { + "src_wire": "CMT_TOP_IMUX31_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD31", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_0": { + "src_wire": "CMT_FREQ_BB_PREF_IN2", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_C->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_C", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_D_ICLK": { + "src_wire": "CMT_PHASER_IN_DB_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_ICLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>CMT_FREQ_PHASER_REFMUX_1": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX16_0->CMT_PHASER_UP_BUFMRCE_CE1": { + "src_wire": "CMT_TOP_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_10->CMT_PHY_CONTROL_READCALIBENABLE": { + "src_wire": "CMT_TOP_IMUX29_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_READCALIBENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_9->CMT_PHY_CONTROL_PHYCTLWD6": { + "src_wire": "CMT_TOP_IMUX30_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX8_6->CMT_PHASER_OUT_DB_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX8_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_D_OCLK1X_90": { + "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_OCLK1X_90", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_9": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_0->CMT_PHASER_REF_RST": { + "src_wire": "CMT_TOP_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_DB_SYNCIN": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_0->CMT_PHASER_REF_PWRDWN": { + "src_wire": "CMT_TOP_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_PWRDWN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO->CMT_PHASER_OUT_D_OCLKDIV": { + "src_wire": "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_OCLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX45_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_4->CMT_PHASER_IN_CA_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_1": { + "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_RDENABLE->CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_DB_RDENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_11->CMT_PHY_CONTROL_PHYCTLWD27": { + "src_wire": "CMT_TOP_IMUX14_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD27", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX23_7->CMT_PHASER_IN_DB_RANKSEL1": { + "src_wire": "CMT_TOP_IMUX23_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX18_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX18_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX28_7->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX28_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKD0->CMT_PHY_CONTROL_IRANKD0": { + "src_wire": "CMT_PHY_CONTROL_INRANKD0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKD0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHY_CONTROL_MEMREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { + "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_DB_RCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { + "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_0->>CMT_L_TOP_UPPER_B_CLKINT_2": { + "src_wire": "CMT_TOP_CLK0_0", + "is_pseudo": "0", + "dst_wire": "CMT_L_TOP_UPPER_B_CLKINT_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT1->>PLL_CLK_FREQBB_REBUFOUT1": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_LOCKED->CMT_TOP_LOGIC_OUTS_L_B14_0": { + "src_wire": "CMT_PHASER_REF_LOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING2->CMT_PHY_CONTROL_OBURSTPENDING2": { + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING2", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_2": { + "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_0": { + "src_wire": "CMT_FREQ_BB_PREF_IN3", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_11": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX37_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { + "src_wire": "CMT_TOP_IMUX37_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { + "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_C_WRCLK_FIFO->CMT_PHASER_IN_C_ICLKDIV": { + "src_wire": "CMT_R_PHASER_IN_C_WRCLK_FIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_ICLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK->>CMT_PHASER_C_OCLK_TOIOI": { + "src_wire": "CMT_PHASER_OUT_C_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS1->CMT_PHASERD_CTSBUS1": { + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_CTSBUS1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING3->CMT_PHY_CONTROL_OBURSTPENDING3": { + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING3", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_10->CMT_PHY_CONTROL_PHYCTLWD12": { + "src_wire": "CMT_TOP_IMUX44_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLALMOSTFULL->CMT_TOP_LOGIC_OUTS_L_B7_9": { + "src_wire": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_9", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CMT_TOP_L_UPPER_T.json b/kintex7/tile_type_CMT_TOP_L_UPPER_T.json new file mode 100644 index 0000000..3d5d1a2 --- /dev/null +++ b/kintex7/tile_type_CMT_TOP_L_UPPER_T.json @@ -0,0 +1,4422 @@ +{ + "tile_type": "CMT_TOP_L_UPPER_T", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "PLLE2_ADV", + "type": "PLLE2_ADV", + "site_pins": { + "TESTIN23": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", + "TESTIN25": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", + "DO4": "CMT_TOP_R_UPPER_T_PLLE2_DO4", + "LOCKED": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", + "DEN": "CMT_TOP_R_UPPER_T_PLLE2_DEN", + "TESTIN16": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", + "TESTOUT0": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", + "TESTOUT9": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", + "TESTOUT28": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", + "TESTIN27": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", + "TESTOUT24": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", + "CLKOUT0": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "TESTIN17": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", + "TESTOUT12": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", + "DI15": "CMT_TOP_R_UPPER_T_PLLE2_DI15", + "TESTOUT2": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", + "TESTIN13": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", + "DI12": "CMT_TOP_R_UPPER_T_PLLE2_DI12", + "DO15": "CMT_TOP_R_UPPER_T_PLLE2_DO15", + "TESTOUT59": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", + "DI2": "CMT_TOP_R_UPPER_T_PLLE2_DI2", + "DO3": "CMT_TOP_R_UPPER_T_PLLE2_DO3", + "TESTIN29": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", + "CLKFBOUT": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "TESTOUT8": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", + "DI11": "CMT_TOP_R_UPPER_T_PLLE2_DI11", + "TESTIN14": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", + "TESTOUT11": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", + "TESTOUT25": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", + "TESTOUT56": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", + "CLKIN2": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "DO10": "CMT_TOP_R_UPPER_T_PLLE2_DO10", + "TESTOUT6": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", + "DO11": "CMT_TOP_R_UPPER_T_PLLE2_DO11", + "DO0": "CMT_TOP_R_UPPER_T_PLLE2_DO0", + "TESTOUT27": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", + "DI6": "CMT_TOP_R_UPPER_T_PLLE2_DI6", + "CLKOUT5": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", + "DI8": "CMT_TOP_R_UPPER_T_PLLE2_DI8", + "DADDR0": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", + "TESTOUT5": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", + "TMUXOUT": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", + "DI3": "CMT_TOP_R_UPPER_T_PLLE2_DI3", + "TESTOUT30": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", + "TESTOUT4": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", + "TESTIN31": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", + "TESTOUT34": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", + "DADDR3": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", + "PWRDWN": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", + "TESTOUT14": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", + "TESTIN9": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", + "TESTOUT63": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", + "TESTOUT43": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", + "TESTOUT15": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", + "TESTOUT23": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", + "TESTOUT61": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", + "DI0": "CMT_TOP_R_UPPER_T_PLLE2_DI0", + "CLKOUT4": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", + "DI9": "CMT_TOP_R_UPPER_T_PLLE2_DI9", + "CLKOUT2": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "TESTOUT60": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", + "DO5": "CMT_TOP_R_UPPER_T_PLLE2_DO5", + "DADDR6": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", + "TESTOUT18": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", + "TESTOUT29": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", + "TESTOUT26": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", + "DO8": "CMT_TOP_R_UPPER_T_PLLE2_DO8", + "TESTIN30": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", + "TESTOUT32": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", + "TESTIN18": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", + "TESTOUT54": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", + "DADDR1": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", + "TESTOUT46": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", + "DADDR2": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", + "TESTIN7": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", + "RST": "CMT_TOP_R_UPPER_T_PLLE2_RST", + "TESTIN8": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", + "TESTOUT48": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", + "DRDY": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", + "DWE": "CMT_TOP_R_UPPER_T_PLLE2_DWE", + "CLKOUT1": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "TESTIN3": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", + "DI14": "CMT_TOP_R_UPPER_T_PLLE2_DI14", + "TESTOUT49": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", + "TESTIN26": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", + "TESTOUT52": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", + "TESTOUT50": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", + "DO6": "CMT_TOP_R_UPPER_T_PLLE2_DO6", + "TESTIN15": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", + "TESTIN19": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", + "TESTIN4": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", + "TESTIN11": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", + "DADDR5": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", + "TESTIN20": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", + "DI4": "CMT_TOP_R_UPPER_T_PLLE2_DI4", + "DO9": "CMT_TOP_R_UPPER_T_PLLE2_DO9", + "TESTOUT17": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", + "TESTOUT21": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", + "TESTOUT10": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", + "TESTIN28": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", + "TESTIN6": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", + "TESTOUT53": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", + "TESTOUT55": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", + "TESTOUT19": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", + "CLKIN1": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "TESTIN10": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", + "TESTOUT22": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", + "DCLK": "CMT_TOP_R_UPPER_T_PLLE2_DCLK", + "DI7": "CMT_TOP_R_UPPER_T_PLLE2_DI7", + "TESTOUT57": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", + "TESTOUT44": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", + "CLKINSEL": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", + "CLKFBIN": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "TESTOUT20": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", + "TESTOUT45": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", + "TESTIN2": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", + "TESTOUT51": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", + "TESTOUT40": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", + "TESTIN24": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", + "TESTOUT58": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", + "TESTOUT16": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", + "DO14": "CMT_TOP_R_UPPER_T_PLLE2_DO14", + "DO12": "CMT_TOP_R_UPPER_T_PLLE2_DO12", + "DI13": "CMT_TOP_R_UPPER_T_PLLE2_DI13", + "TESTOUT41": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", + "DO13": "CMT_TOP_R_UPPER_T_PLLE2_DO13", + "DO1": "CMT_TOP_R_UPPER_T_PLLE2_DO1", + "CLKOUT3": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "TESTOUT38": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", + "DI1": "CMT_TOP_R_UPPER_T_PLLE2_DI1", + "TESTOUT42": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", + "TESTOUT47": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", + "TESTIN5": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", + "TESTIN22": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", + "TESTOUT3": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", + "TESTOUT36": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", + "TESTIN0": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", + "TESTOUT7": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", + "TESTIN1": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", + "TESTOUT33": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", + "DADDR4": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", + "DO2": "CMT_TOP_R_UPPER_T_PLLE2_DO2", + "TESTOUT13": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", + "DO7": "CMT_TOP_R_UPPER_T_PLLE2_DO7", + "DI10": "CMT_TOP_R_UPPER_T_PLLE2_DI10", + "TESTOUT1": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", + "TESTIN12": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", + "TESTOUT37": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", + "DI5": "CMT_TOP_R_UPPER_T_PLLE2_DI5", + "TESTOUT62": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", + "TESTIN21": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", + "TESTOUT31": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", + "TESTOUT39": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", + "TESTOUT35": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35" + }, + "x_coord": 0 + } + ], + "wires": [ + "CMT_TOP_WR1END2_7", + "CMT_TOP_WW4C3_6", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_IMUX18_1", + "CMT_TOP_WL1END3_8", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX8_5", + "CMT_TOP_WW2END3_7", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_EE4B0_9", + "CMT_TOP_IMUX15_8", + "CMT_TOP_LH5_7", + "CMT_TOP_LOGIC_OUTS_L_B12_11", + "CMT_TOP_SE4C2_0", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_FAN2_3", + "CMT_TOP_IMUX40_8", + "CMT_TOP_EE4C2_7", + "CMT_TOP_SE4BEG0_10", + "CMT_TOP_NW2A1_4", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_EE2A1_6", + "CMT_TOP_EE4A2_4", + "CMT_TOP_BYP1_4", + "CMT_TOP_EE4C0_3", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_SE4C1_4", + "CMT_TOP_IMUX23_5", + "CMT_TOP_BYP6_12", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_IMUX34_7", + "CMT_TOP_IMUX25_10", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN5_3", + "CMT_TOP_NE4C2_2", + "CMT_TOP_EE4A2_5", + "CMT_TOP_IMUX35_5", + "CMT_TOP_EE2A0_1", + "CMT_TOP_SE4BEG3_10", + "CMT_TOP_IMUX40_12", + "CMT_TOP_FAN3_2", + "CMT_TOP_BYP2_11", + "CMT_TOP_EE2A2_1", + "CMT_TOP_SW4END2_10", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE2A2_5", + "CMT_TOP_WW2END0_3", + "CMT_TOP_SW4END3_9", + "CMT_TOP_IMUX16_11", + "CMT_TOP_ER1BEG1_0", + "CMT_TOP_SE2A2_10", + "CMT_TOP_SE4C0_2", + "CMT_TOP_R_UPPER_T_PLLE2_DO1", + "CMT_TOP_EE4B3_8", + "CMT_TOP_NW4A3_9", + "CMT_TOP_EE4A1_2", + "CMT_TOP_IMUX31_4", + "CMT_TOP_NW4A3_12", + "CMT_TOP_EL1BEG3_5", + "CMT_TOP_SE4C3_11", + "CMT_TOP_NW4A3_4", + "CMT_TOP_WW4END1_2", + "CMT_TOP_WW4B1_5", + "CMT_TOP_LOGIC_OUTS_L_B2_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", + "CMT_TOP_IMUX12_5", + "CMT_TOP_IMUX8_10", + "CMT_TOP_NW4A1_12", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_EE4A0_6", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_NE4C3_9", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_WR1END0_2", + "CMT_TOP_SW4A0_12", + "CMT_TOP_SW2A0_11", + "CMT_TOP_NW4END1_8", + "CMT_TOP_SE2A0_8", + "CMT_TOP_LH11_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", + "CMT_TOP_EE4C3_2", + "CMT_TOP_IMUX2_7", + "CMT_TOP_LOGIC_OUTS_L_B7_11", + "CMT_TOP_EE2A1_7", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_ER1BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX16_6", + "CMT_TOP_LH6_2", + "CMT_TOP_NE4BEG1_9", + "CMT_PHASER_D_ICLKDIV_TOIOI", + "CMT_TOP_IMUX9_2", + "CMT_TOP_BYP5_1", + "CMT_TOP_OCLKDIV_12", + "CMT_TOP_WR1END1_7", + "CMT_TOP_WL1END1_1", + "CMT_TOP_EE2A3_11", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_EE4A0_11", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX23_8", + "CMT_TOP_IMUX11_12", + "CMT_TOP_LOGIC_OUTS_L_B19_9", + "CMT_TOP_EE4C3_11", + "CMT_TOP_SW4END2_11", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_WW4B1_11", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_WW4A2_11", + "CMT_TOP_NW4END3_0", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", + "CMT_TOP_SE4BEG0_6", + "CMT_TOP_IMUX7_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_SE4C2_12", + "CMT_TOP_SW2A3_2", + "CMT_TOP_WW4C1_4", + "CMT_TOP_NE2A2_5", + "CMT_TOP_SE4C3_9", + "CMT_TOP_IMUX9_12", + "CMT_TOP_IMUX3_7", + "CMT_TOP_WW4A0_8", + "CMT_TOP_NW4END0_5", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_TOP_FAN5_1", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_SE4BEG2_10", + "CMT_TOP_IMUX9_9", + "CMT_TOP_EE2A2_12", + "CMT_TOP_IMUX31_9", + "CMT_TOP_FAN1_6", + "CMT_TOP_IMUX26_4", + "CMT_TOP_IMUX31_12", + "CMT_PLL_PHASER_WRENABLE_TOFIFO", + "CMT_TOP_IMUX3_2", + "CMT_TOP_LH9_11", + "CMT_PLL_PHASERD_CTSBUS0", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_LH4_2", + "CMT_TOP_EE4A1_8", + "CMT_TOP_WW4END1_7", + "CMT_TOP_IMUX35_10", + "CMT_TOP_IMUX44_5", + "CMT_TOP_IMUX37_4", + "CMT_TOP_WW4C2_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", + "CMT_TOP_NW4A0_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", + "CMT_TOP_R_UPPER_T_PLLE2_DI6", + "CMT_TOP_EE4A0_8", + "CMT_TOP_FAN1_12", + "CMT_TOP_WW4B3_1", + "CMT_TOP_EE4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_PHASER_D_OCLK90_TOIOI", + "CMT_TOP_L_UPPER_T_CLKPLL5", + "CMT_TOP_IMUX23_12", + "CMT_TOP_LOGIC_OUTS_L_B15_9", + "CMT_TOP_NE4BEG2_11", + "CMT_TOP_EE2BEG1_12", + "CMT_TOP_IMUX6_12", + "CMT_TOP_WW2END1_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", + "CMT_TOP_IMUX22_9", + "CMT_TOP_FAN3_11", + "CMT_TOP_IMUX13_3", + "CMT_PLL_PHASERD_DQSBUS0", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", + "CMT_TOP_WW4END1_4", + "CMT_TOP_IMUX14_11", + "CMT_TOP_EE4BEG0_9", + "CMT_TOP_WR1END0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_12", + "CMT_TOP_EE4C1_5", + "CMT_TOP_LH9_1", + "CMT_TOP_LH11_10", + "CMT_TOP_FAN6_12", + "CMT_TOP_SE2A1_3", + "CMT_TOP_SE2A0_1", + "PLL_CLK_FREQ_BB_BUFOUT_NS3", + "CMT_TOP_SE4C0_10", + "CMT_TOP_LH12_3", + "CMT_TOP_CLK1_12", + "CMT_TOP_ER1BEG3_11", + "CMT_TOP_FAN7_4", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END2_5", + "CMT_TOP_EE4B2_12", + "CMT_TOP_WR1END2_9", + "CMT_TOP_FAN1_0", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_IMUX40_7", + "CMT_TOP_BYP7_8", + "CMT_TOP_NW4A3_0", + "CMT_TOP_WL1END2_4", + "CMT_TOP_IMUX0_5", + "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_SW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_EE2A3_3", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW2A0_2", + "CMT_TOP_SW4END1_2", + "CMT_TOP_EE2A3_5", + "CMT_TOP_WR1END0_1", + "CMT_TOP_WW4C1_3", + "CMT_TOP_LH4_3", + "CMT_TOP_EE4B2_8", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_IMUX5_2", + "CMT_TOP_EE2BEG1_6", + "CMT_TOP_EE4BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NW4A0_6", + "CMT_TOP_IMUX2_12", + "CMT_TOP_WL1END3_12", + "CMT_TOP_EE2A1_10", + "CMT_TOP_EE4A3_5", + "CMT_TOP_LOGIC_OUTS_L_B8_10", + "CMT_TOP_IMUX14_0", + "CMT_TOP_LH7_5", + "CMT_TOP_WW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_TOP_WW2END2_3", + "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WW2END3_8", + "CMT_TOP_NW4END1_0", + "CMT_TOP_NE4C2_5", + "CMT_TOP_SE2A2_11", + "CMT_TOP_IMUX14_4", + "CMT_TOP_IMUX12_4", + "CMT_TOP_SW4END3_2", + "CMT_TOP_IMUX32_0", + "CMT_TOP_SW4END3_12", + "CMT_TOP_SE4BEG0_1", + "CMT_TOP_IMUX44_6", + "CMT_TOP_IMUX40_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", + "CMT_TOP_SE2A3_3", + "CMT_TOP_SE4BEG3_12", + "CMT_TOP_ER1BEG0_11", + "CMT_TOP_FAN0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_R_UPPER_T_PLLE2_DEN", + "CMT_TOP_NE2A3_10", + "CMT_TOP_WW4B3_2", + "CMT_TOP_LOGIC_OUTS_L_B3_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", + "CMT_TOP_FAN0_7", + "CMT_TOP_WW4B0_3", + "CMT_TOP_R_UPPER_T_PLLE2_DO13", + "CMT_TOP_LH11_8", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_TOP_IMUX47_4", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_EE4A0_10", + "CMT_TOP_WW4C1_6", + "CMT_TOP_IMUX35_11", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_NW2A1_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", + "CMT_TOP_IMUX46_9", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_SW4END3_7", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_NW4END3_6", + "CMT_TOP_EE2BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_EE4B0_12", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_TOP_ER1BEG1_11", + "CMT_TOP_IMUX45_6", + "CMT_TOP_WW4END2_8", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_WW4END1_0", + "CMT_TOP_LH3_2", + "CMT_TOP_IMUX1_9", + "CMT_TOP_IMUX8_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_IMUX2_8", + "CMT_TOP_WW2A1_12", + "CMT_TOP_OCLK_5", + "CMT_TOP_BYP0_3", + "CMT_TOP_NE4C0_10", + "CMT_TOP_WW2A2_2", + "CMT_TOP_IMUX20_7", + "CMT_TOP_IMUX25_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", + "CMT_TOP_NW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_WW4C0_3", + "CMT_TOP_IMUX28_5", + "CMT_TOP_NE2A0_2", + "CMT_TOP_WL1END2_12", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_EE4A3_12", + "CMT_TOP_BYP1_1", + "CMT_TOP_SE2A3_6", + "CMT_TOP_SW4A1_11", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX2_2", + "CMT_TOP_R_UPPER_T_PLLE2_DO11", + "CMT_TOP_IMUX21_0", + "CMT_TOP_WW4END2_9", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_SE2A0_2", + "CMT_TOP_IMUX43_1", + "CMT_TOP_EE2BEG2_12", + "CMT_TOP_BYP4_12", + "CMT_PLL_PHASERREF1", + "CMT_TOP_EE4BEG1_6", + "PLL_CLK_FREQ_BB0_NS", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_TOP_IMUX28_8", + "CMT_TOP_WW4C3_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", + "CMT_TOP_SW4END0_9", + "CMT_TOP_LH8_1", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_NE2A0_11", + "CMT_TOP_WW2A3_2", + "CMT_TOP_NW4A0_7", + "CMT_TOP_LH9_5", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_IMUX6_7", + "CMT_TOP_IMUX45_10", + "CMT_TOP_WR1END3_4", + "CMT_TOP_EE2A0_6", + "CMT_TOP_EE2BEG0_9", + "CMT_TOP_EE2A2_6", + "CMT_TOP_BYP2_2", + "CMT_TOP_LOGIC_OUTS_L_B0_11", + "CMT_TOP_IMUX21_6", + "CMT_TOP_SE4C3_1", + "CMT_TOP_SW2A2_3", + "CMT_TOP_IMUX19_7", + "CMT_TOP_IMUX0_4", + "CMT_TOP_ICLK_9", + "CMT_TOP_SW4END2_7", + "CMT_TOP_WW4B3_9", + "CMT_TOP_IMUX15_0", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_IMUX33_12", + "CMT_TOP_EL1BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_WW4END2_5", + "CMT_TOP_WW2A1_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_IMUX9_8", + "CMT_TOP_WW2A1_9", + "CMT_TOP_SW4A0_4", + "CMT_TOP_BYP0_11", + "CMT_TOP_FAN1_8", + "CMT_TOP_IMUX34_4", + "CMT_TOP_IMUX12_9", + "CMT_TOP_SW4A1_10", + "CMT_TOP_SW4END1_12", + "CMT_TOP_WW4A2_12", + "CMT_TOP_NW4A0_11", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4B0_2", + "CMT_TOP_LH2_2", + "CMT_TOP_IMUX10_7", + "CMT_TOP_IMUX39_0", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_WW4END0_10", + "CMT_TOP_IMUX30_10", + "CMT_TOP_NW2A0_9", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_TOP_SW4A3_5", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_IMUX14_1", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_WL1END0_10", + "CMT_TOP_IMUX26_1", + "CMT_TOP_CTRL0_9", + "CMT_TOP_WL1END0_1", + "CMT_TOP_LH11_6", + "CMT_TOP_NE4C3_8", + "CMT_TOP_IMUX46_12", + "CMT_TOP_WL1END0_7", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_TOP_LH12_4", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_NE4C3_4", + "CMT_TOP_ER1BEG0_7", + "CMT_TOP_WW2END2_4", + "CMT_TOP_SW4END1_8", + "CMT_TOP_SE4C2_6", + "CMT_TOP_IMUX26_12", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_SW2A1_1", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_WW4END3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_9", + "CMT_TOP_WL1END2_6", + "CMT_TOP_IMUX43_6", + "CMT_TOP_NW4A1_1", + "CMT_TOP_SE4C1_8", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_SE4BEG0_3", + "CMT_TOP_IMUX40_5", + "CMT_TOP_EE4BEG3_2", + "PLL_CLK_FREQ_BB_BUFOUT_NS2", + "CMT_TOP_BLOCK_OUTS_L_B1_10", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_IMUX34_1", + "CMT_TOP_WL1END2_0", + "CMT_TOP_EE4A1_3", + "CMT_TOP_OCLKDIV_10", + "CMT_TOP_LH7_0", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_IMUX8_11", + "CMT_PHASER_D_OCLKDIV_TOIOI", + "CMT_TOP_WW2END0_2", + "CMT_TOP_IMUX0_3", + "CMT_TOP_EE4A0_1", + "CMT_TOP_WW4A1_4", + "CMT_TOP_IMUX23_3", + "CMT_TOP_IMUX20_0", + "CMT_TOP_WR1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_LH11_9", + "CMT_TOP_IMUX25_1", + "CMT_TOP_ER1BEG1_1", + "CMT_TOP_IMUX44_7", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_TOP_FAN0_12", + "CMT_TOP_WW4A3_10", + "CMT_TOP_WW2A0_4", + "CMT_TOP_SW2A0_10", + "CMT_TOP_WW4A3_3", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_LH1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_NW4A0_4", + "CMT_TOP_CLK1_5", + "CMT_TOP_IMUX37_12", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_NE2A0_10", + "CMT_TOP_IMUX18_5", + "CMT_TOP_IMUX24_8", + "CMT_TOP_IMUX24_7", + "CMT_TOP_LH12_11", + "CMT_TOP_EE4B0_2", + "CMT_TOP_IMUX29_12", + "CMT_TOP_SW2A0_2", + "CMT_TOP_SW4A3_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", + "CMT_TOP_EE2A3_10", + "CMT_TOP_IMUX42_12", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_WL1END3_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", + "CMT_TOP_SE4BEG0_11", + "CMT_TOP_FAN4_5", + "CMT_TOP_EE4A1_10", + "CMT_TOP_NE2A1_2", + "CMT_TOP_SE4BEG1_7", + "CMT_TOP_NE2A1_10", + "CMT_TOP_WW2END2_11", + "CMT_TOP_IMUX36_3", + "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", + "CMT_TOP_IMUX10_11", + "CMT_TOP_IMUX14_9", + "CMT_TOP_ER1BEG2_11", + "CMT_TOP_IMUX21_7", + "CMT_TOP_EE4B3_11", + "CMT_TOP_IMUX25_7", + "CMT_TOP_SW4A2_5", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_EE4BEG2_12", + "CMT_TOP_NE2A2_12", + "CMT_TOP_WW4C0_9", + "CMT_TOP_NE4C2_3", + "CMT_TOP_WW4A1_8", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_BYP7_5", + "CMT_TOP_NE2A0_5", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_EE4A0_2", + "CMT_TOP_SW4END3_8", + "CMT_TOP_IMUX20_6", + "CMT_TOP_LH9_3", + "CMT_TOP_EE4B3_0", + "CMT_TOP_EL1BEG1_9", + "CMT_TOP_SW2A2_10", + "CMT_TOP_WW4END3_0", + "CMT_TOP_WW2A0_1", + "CMT_TOP_SW4A0_9", + "CMT_TOP_IMUX45_7", + "CMT_TOP_IMUX19_2", + "CMT_TOP_IMUX42_5", + "CMT_TOP_IMUX18_11", + "CMT_TOP_EE4B1_12", + "CMT_TOP_LOGIC_OUTS_L_B10_12", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_BLOCK_OUTS_L_B0_9", + "CMT_TOP_WL1END2_7", + "CMT_TOP_SW4END3_6", + "CMT_TOP_SW4A0_3", + "CMT_TOP_BYP1_10", + "CMT_TOP_IMUX27_7", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_EE4BEG3_12", + "CMT_TOP_SW4A2_10", + "CMT_TOP_IMUX28_12", + "CMT_TOP_LOGIC_OUTS_L_B6_10", + "CMT_TOP_BYP5_6", + "CMT_TOP_IMUX27_8", + "CMT_TOP_IMUX34_3", + "CMT_TOP_FAN0_0", + "CMT_TOP_IMUX23_11", + "CMT_TOP_WR1END1_1", + "CMT_TOP_WW4END3_6", + "CMT_TOP_WW4B3_7", + "CMT_TOP_SW4A0_7", + "CMT_TOP_NE4BEG1_11", + "CMT_TOP_SW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B15_10", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_IMUX6_2", + "CMT_TOP_WW4A1_6", + "CMT_PLL_PHASERREF_BELOW1", + "CMT_TOP_WW4C2_5", + "CMT_TOP_IMUX40_0", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_EE2A2_8", + "CMT_TOP_NE2A3_7", + "CMT_TOP_ER1BEG1_2", + "CMT_TOP_SW4END0_12", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_LOGIC_OUTS_L_B14_11", + "CMT_TOP_LH4_5", + "CMT_TOP_IMUX3_5", + "CMT_TOP_BYP7_4", + "CMT_TOP_CLK1_0", + "CMT_TOP_IMUX26_11", + "CMT_TOP_IMUX1_5", + "CMT_TOP_LH9_4", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_SE4C2_1", + "CMT_TOP_EE2A3_1", + "CMT_TOP_SW2A2_9", + "CMT_TOP_EL1BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_11", + "CMT_TOP_IMUX28_0", + "CMT_TOP_BYP3_11", + "CMT_TOP_IMUX18_2", + "CMT_TOP_WW2END0_1", + "CMT_TOP_LOGIC_OUTS_L_B7_9", + "CMT_TOP_BYP4_3", + "CMT_TOP_BYP3_0", + "CMT_TOP_CLK1_10", + "CMT_TOP_EE4BEG0_11", + "CMT_TOP_NE2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_BLOCK_OUTS_L_B0_11", + "CMT_TOP_EE2A3_8", + "CMT_TOP_EE4A2_8", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", + "CMT_TOP_WW4C0_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_WW4B1_4", + "CMT_TOP_CTRL0_4", + "CMT_TOP_SW4END0_6", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_NW4A3_7", + "CMT_TOP_WW4B1_10", + "CMT_TOP_SE2A3_5", + "CMT_TOP_LH5_10", + "CMT_TOP_WW4END0_11", + "CMT_TOP_BYP7_7", + "CMT_TOP_IMUX29_5", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_IMUX25_5", + "CMT_TOP_WW4A3_4", + "CMT_PLL_PHASER_RDCLK_TOFIFO", + "CMT_TOP_FAN5_9", + "CMT_TOP_IMUX46_8", + "CMT_TOP_IMUX31_11", + "CMT_TOP_BYP4_0", + "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "CMT_TOP_IMUX18_4", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_TOP_LOGIC_OUTS_L_B16_9", + "CMT_TOP_WW2A2_3", + "CMT_TOP_IMUX44_12", + "CMT_TOP_IMUX28_3", + "CMT_TOP_SE2A1_12", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WW2A1_11", + "CMT_TOP_LH6_1", + "CMT_TOP_LH7_3", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_NE2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH6_0", + "CMT_TOP_WW4C0_7", + "CMT_TOP_SE4BEG2_2", + "CMT_TOP_WW4END1_10", + "CMT_TOP_LH3_5", + "CMT_TOP_BYP0_10", + "CMT_TOP_NE4C0_4", + "CMT_TOP_SW2A1_7", + "CMT_TOP_NE4C0_2", + "CMT_TOP_R_UPPER_T_PLLE2_DO5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "CMT_TOP_SE4C0_7", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_SE4C0_12", + "CMT_TOP_LOGIC_OUTS_L_B11_10", + "CMT_TOP_SW4A1_8", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_LH11_11", + "CMT_TOP_WR1END3_3", + "CMT_TOP_MONITOR_P_1", + "CMT_TOP_LH8_8", + "CMT_TOP_SW4A3_6", + "CMT_TOP_SW4END1_11", + "CMT_TOP_IMUX31_8", + "CMT_TOP_EE2A3_0", + "CMT_TOP_IMUX21_11", + "CMT_TOP_IMUX13_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", + "CMT_TOP_IMUX39_4", + "CMT_TOP_NW4END2_11", + "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "CMT_TOP_MONITOR_P_3", + "CMT_TOP_EE4B1_7", + "CMT_TOP_WW4A0_7", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_WW4B0_11", + "CMT_TOP_SE2A1_2", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_BYP5_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", + "CMT_TOP_NE2A0_4", + "CMT_TOP_LH9_0", + "CMT_TOP_IMUX22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_10", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_IMUX25_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", + "CMT_TOP_NE2A1_4", + "CMT_TOP_EE4BEG3_0", + "CMT_TOP_WW2END1_7", + "CMT_TOP_EE4B0_7", + "CMT_TOP_WW4B2_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", + "CMT_TOP_BYP1_0", + "CMT_TOP_IMUX22_4", + "CMT_TOP_SE4C1_0", + "CMT_TOP_FAN7_3", + "CMT_TOP_WW4A0_6", + "CMT_TOP_WW2END2_1", + "CMT_TOP_IMUX45_5", + "CMT_TOP_BYP6_4", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_TOP_BYP3_5", + "CMT_TOP_EE2A0_3", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_EE4C2_2", + "CMT_TOP_FAN2_10", + "CMT_TOP_CTRL1_5", + "CMT_TOP_CTRL0_5", + "CMT_TOP_WW2END0_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", + "CMT_TOP_IMUX1_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", + "CMT_TOP_WW2END0_7", + "CMT_TOP_NW4END0_11", + "CMT_TOP_EL1BEG0_12", + "CMT_TOP_LOGIC_OUTS_L_B20_11", + "CMT_TOP_WL1END2_3", + "CMT_TOP_WW4END1_12", + "CMT_TOP_IMUX36_11", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_IMUX10_3", + "CMT_TOP_IMUX37_10", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_SW4A3_12", + "CMT_TOP_WR1END3_8", + "CMT_TOP_IMUX47_1", + "CMT_TOP_IMUX10_6", + "CMT_TOP_IMUX44_10", + "CMT_TOP_BYP6_11", + "CMT_TOP_NE4C1_0", + "CMT_TOP_WW4A3_1", + "CMT_TOP_BYP6_6", + "CMT_TOP_BYP4_10", + "CMT_TOP_LOGIC_OUTS_L_B23_11", + "CMT_TOP_NE4C0_3", + "CMT_TOP_SW4A3_9", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_OCLKDIV_8", + "CMT_TOP_LH2_1", + "CMT_TOP_IMUX42_1", + "CMT_TOP_SW4A1_6", + "CMT_TOP_LH12_0", + "CMT_TOP_IMUX7_11", + "CMT_TOP_NW4A1_9", + "CMT_TOP_BYP1_8", + "CMT_TOP_WW4C2_1", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_IMUX42_0", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", + "CMT_TOP_FAN7_1", + "CMT_TOP_SE4C2_9", + "CMT_TOP_IMUX38_12", + "CMT_TOP_WW2A3_0", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_WW4A2_9", + "CMT_TOP_NE4C2_12", + "CMT_TOP_LH1_7", + "CMT_TOP_EE2BEG2_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", + "CMT_TOP_NW4A1_6", + "CMT_TOP_BYP2_1", + "CMT_TOP_WL1END2_10", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_IMUX13_0", + "CMT_TOP_LOGIC_OUTS_L_B22_12", + "CMT_TOP_IMUX30_7", + "CMT_TOP_WW4A0_3", + "CMT_TOP_FAN2_0", + "CMT_TOP_BLOCK_OUTS_L_B1_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", + "CMT_TOP_IMUX18_9", + "CMT_TOP_EE2A0_5", + "CMT_TOP_CTRL1_0", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_TOP_IMUX30_12", + "CMT_TOP_WW4A0_1", + "CMT_TOP_FAN3_0", + "CMT_TOP_LH2_7", + "CMT_TOP_IMUX30_2", + "CMT_TOP_FAN3_3", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_IMUX2_5", + "CMT_TOP_IMUX28_4", + "CMT_TOP_IMUX10_9", + "CMT_TOP_EL1BEG3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_9", + "CMT_TOP_LH11_0", + "CMT_TOP_EE4C1_11", + "CMT_TOP_IMUX15_5", + "CMT_TOP_IMUX13_8", + "CMT_TOP_SE4C1_9", + "CMT_TOP_EE4C0_5", + "CMT_TOP_IMUX2_0", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_SW4END1_1", + "CMT_TOP_LH12_7", + "CMT_TOP_WR1END3_7", + "CMT_TOP_WL1END1_7", + "CMT_TOP_OCLK_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", + "CMT_TOP_EE4C1_2", + "CMT_TOP_R_UPPER_T_PLLE2_DI5", + "CMT_TOP_BYP0_4", + "CMT_TOP_FAN4_0", + "CMT_TOP_BYP7_10", + "CMT_TOP_SW2A0_9", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_MONITOR_N_9", + "CMT_TOP_WW4A1_3", + "CMT_TOP_WW4END0_9", + "CMT_TOP_FAN4_4", + "CMT_TOP_ICLKDIV_9", + "CMT_TOP_IMUX25_12", + "CMT_TOP_IMUX7_8", + "CMT_TOP_LOGIC_OUTS_L_B5_11", + "CMT_TOP_WW4B2_11", + "CMT_TOP_BYP7_0", + "CMT_TOP_FAN7_11", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_BYP6_2", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_EE4C2_8", + "CMT_TOP_IMUX14_6", + "CMT_TOP_LOGIC_OUTS_L_B19_11", + "CMT_TOP_SW4A2_11", + "CMT_TOP_IMUX10_1", + "CMT_TOP_NE4C3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_LOGIC_OUTS_L_B8_9", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_IMUX37_11", + "CMT_TOP_IMUX6_4", + "CMT_TOP_BLOCK_OUTS_L_B0_10", + "CMT_TOP_BLOCK_OUTS_L_B1_11", + "CMT_TOP_R_UPPER_T_PLLE2_DO4", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_TOP_CTRL0_11", + "CMT_TOP_R_UPPER_T_PLLE2_DI10", + "CMT_TOP_IMUX43_7", + "CMT_TOP_LOGIC_OUTS_L_B23_9", + "CMT_TOP_R_UPPER_T_PLLE2_DRDY", + "CMT_TOP_EE2BEG0_4", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LOGIC_OUTS_L_B7_10", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_IMUX38_7", + "CMT_TOP_IMUX21_10", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_SW4A2_7", + "CMT_TOP_OCLK1X_90_10", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", + "CMT_TOP_LH1_2", + "CMT_TOP_BYP0_9", + "CMT_TOP_LOGIC_OUTS_L_B4_10", + "CMT_TOP_FAN4_10", + "CMT_TOP_IMUX30_3", + "CMT_TOP_R_UPPER_T_PLLE2_DI9", + "CMT_TOP_WR1END3_10", + "CMT_TOP_EE2BEG3_9", + "CMT_TOP_WR1END1_6", + "CMT_TOP_SW2A2_5", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_NW2A1_8", + "CMT_TOP_IMUX15_11", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_IMUX36_9", + "CMT_TOP_EE4B2_1", + "CMT_TOP_SW2A2_0", + "CMT_TOP_NW4END2_3", + "CMT_TOP_FAN4_2", + "CMT_TOP_IMUX43_0", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_WW4END0_8", + "CMT_TOP_SW4A1_4", + "CMT_TOP_WW2A2_12", + "CMT_TOP_CLK0_12", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", + "CMT_TOP_IMUX29_0", + "CMT_TOP_FAN6_0", + "CMT_TOP_NW2A2_12", + "CMT_TOP_IMUX43_2", + "CMT_TOP_EE4B1_1", + "CMT_TOP_NW2A2_8", + "CMT_TOP_CTRL1_10", + "CMT_TOP_WW2A0_3", + "CMT_TOP_WW2A2_5", + "CMT_TOP_FAN4_9", + "CMT_TOP_SW4END1_6", + "CMT_TOP_NE4BEG0_9", + "CMT_TOP_EE4B2_5", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_WW2A2_0", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_NE4C3_2", + "CMT_TOP_SE4BEG3_4", + "CMT_TOP_WW2END3_3", + "CMT_TOP_IMUX5_4", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_TOP_WW2END3_2", + "CMT_TOP_NE4C2_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", + "CMT_TOP_SW4END2_2", + "CMT_PLL_PHASER_OUT_D_OCLK", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_NE2A3_8", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B2_11", + "CMT_TOP_SW4A1_3", + "CMT_TOP_NW4A2_8", + "CMT_TOP_WR1END1_5", + "CMT_TOP_SE4C2_5", + "CMT_TOP_R_UPPER_T_PLLE2_DWE", + "CMT_TOP_LOGIC_OUTS_L_B22_11", + "CMT_TOP_ER1BEG3_3", + "CMT_TOP_WW2A3_9", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_FAN2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_IMUX41_2", + "CMT_TOP_IMUX20_2", + "CMT_TOP_SW4END2_6", + "CMT_TOP_NW4END0_9", + "CMT_TOP_IMUX45_1", + "CMT_TOP_LOGIC_OUTS_L_B18_12", + "CMT_TOP_IMUX24_9", + "CMT_TOP_WW4B3_3", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_WW4C1_12", + "CMT_TOP_NE4C3_3", + "CMT_TOP_BYP2_0", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_LH8_12", + "CMT_TOP_LH12_6", + "CMT_TOP_SW4END2_9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_EE4A1_1", + "CMT_TOP_IMUX27_9", + "CMT_TOP_SW4A0_10", + "CMT_TOP_IMUX26_3", + "CMT_TOP_SW4A2_0", + "CMT_TOP_EL1BEG3_9", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_LOGIC_OUTS_L_B2_10", + "CMT_TOP_IMUX47_0", + "CMT_TOP_IMUX7_10", + "CMT_TOP_FAN5_5", + "CMT_TOP_NW4END2_10", + "CMT_TOP_SE4C0_3", + "CMT_TOP_IMUX45_4", + "CMT_TOP_EL1BEG1_11", + "CMT_TOP_EE2A3_7", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_EE4A3_9", + "CMT_TOP_IMUX19_0", + "CMT_TOP_WR1END0_0", + "CMT_TOP_WW4B1_12", + "CMT_TOP_EE4BEG1_9", + "CMT_TOP_NE2A3_3", + "CMT_TOP_WW4C1_8", + "CMT_TOP_SW4A3_10", + "CMT_TOP_FAN5_11", + "CMT_TOP_NE4C0_5", + "CMT_TOP_IMUX8_6", + "CMT_TOP_WL1END2_2", + "CMT_TOP_SE2A0_9", + "CMT_TOP_R_UPPER_T_PLLE2_DO8", + "CMT_TOP_EE4A3_4", + "CMT_TOP_WW4END0_12", + "CMT_TOP_BYP1_2", + "CMT_TOP_WW4END2_3", + "CMT_TOP_IMUX24_2", + "CMT_TOP_IMUX6_0", + "CMT_TOP_NW4END1_10", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_WW2END2_10", + "CMT_TOP_EE4B2_0", + "CMT_TOP_IMUX45_12", + "CMT_TOP_SW2A0_7", + "CMT_TOP_CLK0_8", + "CMT_TOP_IMUX44_0", + "CMT_TOP_EE4C3_10", + "CMT_TOP_BYP4_6", + "CMT_TOP_LH2_12", + "CMT_TOP_WW2END1_11", + "CMT_TOP_IMUX7_0", + "CMT_TOP_IMUX9_4", + "CMT_TOP_EE4A0_4", + "CMT_TOP_LH9_6", + "CMT_TOP_SW2A3_7", + "CMT_TOP_WW4A3_9", + "CMT_TOP_NW4END3_8", + "CMT_TOP_NW4A1_2", + "CMT_TOP_SE2A0_7", + "CMT_TOP_WW4B1_3", + "CMT_TOP_BYP4_11", + "CMT_TOP_WR1END2_8", + "CMT_TOP_LH4_12", + "CMT_TOP_NW2A0_2", + "CMT_TOP_EE4B0_3", + "CMT_TOP_FAN1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_10", + "CMT_TOP_SE2A1_4", + "CMT_TOP_SE4C0_6", + "CMT_TOP_IMUX17_4", + "CMT_TOP_LH2_10", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", + "CMT_TOP_EL1BEG1_12", + "CMT_TOP_SW4END2_4", + "CMT_TOP_WL1END0_6", + "CMT_TOP_LOGIC_OUTS_L_B13_12", + "CMT_TOP_IMUX37_2", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_EE4B3_6", + "CMT_TOP_NW4END2_5", + "CMT_TOP_EE4A1_7", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_IMUX15_3", + "CMT_TOP_EE2A3_12", + "CMT_TOP_LH7_10", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_WR1END3_9", + "CMT_TOP_WW2END3_10", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_LH6_7", + "CMT_TOP_WW4END3_12", + "CMT_TOP_EE4C2_10", + "CMT_TOP_IMUX11_3", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_MONITOR_P_12", + "CMT_TOP_EE4B2_4", + "CMT_TOP_WW2A3_5", + "CMT_TOP_WW2END2_6", + "CMT_TOP_SW4END0_7", + "CMT_TOP_OCLK_9", + "CMT_TOP_LH1_9", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_BYP7_11", + "CMT_TOP_WL1END1_2", + "CMT_TOP_WW2A3_8", + "CMT_TOP_WW2END3_0", + "CMT_TOP_IMUX30_6", + "CMT_TOP_EL1BEG0_1", + "CMT_TOP_IMUX22_5", + "CMT_TOP_FAN2_11", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_IMUX12_0", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_NE2A1_1", + "CMT_TOP_IMUX19_3", + "CMT_TOP_WW4B0_5", + "CMT_TOP_R_UPPER_T_PLLE2_DO14", + "CMT_TOP_ICLK_8", + "CMT_TOP_IMUX7_9", + "CMT_TOP_IMUX7_6", + "CMT_TOP_SW2A1_2", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_IMUX36_2", + "CMT_TOP_WW2END3_1", + "CMT_TOP_NE4C0_1", + "CMT_TOP_IMUX11_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", + "CMT_TOP_BYP3_10", + "CMT_TOP_IMUX11_5", + "CMT_TOP_L_UPPER_T_CLKFBIN", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_TOP_NE4BEG2_2", + "CMT_TOP_IMUX30_1", + "CMT_TOP_WR1END1_12", + "CMT_TOP_WW2END0_11", + "CMT_TOP_WW4C1_9", + "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", + "CMT_TOP_SE4C3_2", + "CMT_TOP_L_UPPER_T_CLKPLL4", + "CMT_TOP_NE4C0_7", + "CMT_TOP_EE4A2_1", + "CMT_TOP_WW2END2_9", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "CMT_TOP_IMUX43_3", + "CMT_TOP_IMUX21_4", + "CMT_TOP_IMUX33_3", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_LH5_8", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_NW4A2_10", + "CMT_TOP_WW4END3_1", + "CMT_TOP_LOGIC_OUTS_L_B14_10", + "CMT_TOP_IMUX35_4", + "CMT_TOP_NE4C1_10", + "CMT_TOP_LOGIC_OUTS_L_B3_9", + "CMT_TOP_IMUX42_8", + "CMT_TOP_EE2A3_4", + "CMT_TOP_EE4BEG2_6", + "CMT_TOP_IMUX38_8", + "CMT_TOP_CLK0_0", + "CMT_TOP_SE2A1_6", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_LH8_11", + "CMT_TOP_FAN7_2", + "CMT_TOP_EE2A0_7", + "CMT_TOP_NE4BEG2_10", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_WW4C3_9", + "CMT_TOP_EE2BEG0_10", + "CMT_TOP_IMUX37_1", + "CMT_TOP_EE4C3_5", + "CMT_TOP_NE4C3_5", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_ER1BEG2_12", + "CMT_TOP_BYP5_2", + "CMT_TOP_NE2A0_12", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_IMUX6_1", + "CMT_TOP_NE2A0_9", + "CMT_TOP_IMUX36_4", + "CMT_TOP_BYP4_1", + "CMT_TOP_IMUX9_3", + "CMT_TOP_IMUX15_6", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_IMUX7_3", + "CMT_TOP_NW4END1_1", + "CMT_TOP_FAN3_8", + "CMT_TOP_LH4_1", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX45_0", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", + "CMT_TOP_EE4B1_9", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_FAN6_9", + "CMT_TOP_EE4C2_3", + "CMT_TOP_WR1END1_8", + "CMT_TOP_IMUX19_9", + "CMT_TOP_IMUX5_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", + "CMT_TOP_EL1BEG0_11", + "CMT_TOP_EE4A0_5", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NW2A0_5", + "CMT_TOP_IMUX24_10", + "CMT_PHASER_D_ICLK_TOIOI", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_IMUX16_10", + "CMT_TOP_LOGIC_OUTS_L_B8_12", + "CMT_TOP_SW4END1_4", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX5_11", + "CMT_TOP_EE4C0_9", + "CMT_TOP_IMUX18_6", + "CMT_TOP_EE4B0_1", + "CMT_TOP_LOGIC_OUTS_L_B17_11", + "CMT_TOP_SW2A3_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_WW4A3_7", + "CMT_TOP_WW4A1_7", + "CMT_TOP_IMUX41_6", + "CMT_TOP_LH4_0", + "CMT_TOP_SW2A2_8", + "CMT_TOP_WW2A0_9", + "CMT_TOP_BYP2_7", + "CMT_TOP_LOGIC_OUTS_L_B12_12", + "CMT_TOP_SW4A1_2", + "CMT_TOP_FAN3_4", + "CMT_TOP_IMUX4_10", + "CMT_TOP_SW4END3_3", + "CMT_TOP_LOGIC_OUTS_L_B17_12", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH11_7", + "CMT_TOP_NW2A3_1", + "CMT_TOP_WW4A1_5", + "CMT_TOP_WW2A2_11", + "CMT_TOP_FAN3_5", + "CMT_TOP_EE4C1_3", + "CMT_TOP_WW2A2_7", + "CMT_TOP_BYP5_10", + "CMT_TOP_OCLK_1", + "CMT_TOP_EE4C1_9", + "CMT_TOP_WL1END3_4", + "CMT_TOP_EE2A0_10", + "CMT_TOP_WW4END2_12", + "CMT_TOP_IMUX41_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", + "CMT_TOP_EE4B3_2", + "CMT_TOP_SW2A1_11", + "CMT_TOP_BYP1_12", + "CMT_TOP_NW4END2_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_LOGIC_OUTS_L_B2_12", + "CMT_TOP_FAN6_1", + "CMT_TOP_EE4C1_7", + "CMT_TOP_R_UPPER_T_PLLE2_DI4", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_IMUX28_11", + "CMT_TOP_SE4C1_6", + "CMT_TOP_IMUX39_6", + "CMT_TOP_IMUX35_2", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_NE2A1_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", + "CMT_TOP_WL1END0_2", + "CMT_TOP_LOGIC_OUTS_L_B22_9", + "CMT_TOP_IMUX41_10", + "CMT_TOP_IMUX44_1", + "CMT_TOP_IMUX33_10", + "CMT_TOP_WW2A1_2", + "CMT_TOP_IMUX16_5", + "CMT_TOP_NW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_TOP_IMUX39_7", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_TOP_SW4END3_10", + "CMT_TOP_IMUX26_0", + "CMT_TOP_EL1BEG0_4", + "CMT_TOP_IMUX4_6", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_EE4B3_3", + "CMT_TOP_R_UPPER_T_PLLE2_DO12", + "CMT_TOP_WW4B0_6", + "CMT_TOP_NW2A0_1", + "CMT_TOP_IMUX27_4", + "CMT_TOP_LOGIC_OUTS_L_B0_10", + "CMT_TOP_NE4BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_EE4C1_8", + "CMT_TOP_EE4C1_4", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_SW2A3_9", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_BYP2_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", + "CMT_TOP_IMUX0_9", + "CMT_TOP_NW2A3_6", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_CLK0_7", + "CMT_TOP_WL1END3_0", + "CMT_TOP_L_UPPER_T_CLKPLL6", + "CMT_TOP_IMUX13_7", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_EE2A2_0", + "CMT_TOP_ICLK_4", + "CMT_TOP_LOGIC_OUTS_L_B21_9", + "CMT_TOP_IMUX4_0", + "PLL_CLK_FREQ_BB_BUFOUT_NS0", + "CMT_TOP_MONITOR_P_9", + "CMT_TOP_IMUX3_6", + "CMT_TOP_EE4B0_11", + "CMT_TOP_BYP7_1", + "CMT_TOP_OCLKDIV_9", + "CMT_TOP_WW2END0_8", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_WW2END1_3", + "CMT_TOP_SE2A3_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_L_UPPER_T_CLKIN2", + "CMT_TOP_NE4BEG3_9", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_BYP3_4", + "CMT_TOP_SE4C3_0", + "CMT_TOP_IMUX25_8", + "CMT_TOP_NE4BEG1_12", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_SW4END3_0", + "CMT_TOP_WW4C0_12", + "CMT_TOP_IMUX3_3", + "CMT_TOP_WW2END1_2", + "CMT_TOP_SE4C1_3", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_LH9_10", + "CMT_TOP_WW2A0_11", + "CMT_TOP_IMUX25_11", + "CMT_TOP_NW2A1_1", + "CMT_TOP_IMUX14_12", + "CMT_TOP_NW2A2_5", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX19_6", + "CMT_TOP_WW4A1_2", + "CMT_TOP_NW4A2_9", + "CMT_TOP_IMUX19_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_SE4BEG2_5", + "CMT_TOP_BLOCK_OUTS_L_B3_11", + "CMT_TOP_NE4C3_11", + "CMT_TOP_NW4END2_9", + "CMT_TOP_WW2A1_7", + "CMT_TOP_SW4END0_8", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WL1END0_4", + "CMT_TOP_IMUX18_12", + "CMT_TOP_IMUX35_1", + "CMT_TOP_NE4C1_1", + "CMT_TOP_WL1END0_5", + "CMT_TOP_IMUX6_9", + "CMT_TOP_R_UPPER_T_PLLE2_DO3", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_IMUX20_1", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_WW4C3_0", + "CMT_TOP_FAN4_3", + "CMT_TOP_NW4END1_12", + "CMT_TOP_WR1END3_2", + "CMT_TOP_WW4B3_11", + "CMT_TOP_SE2A2_9", + "CMT_TOP_IMUX5_7", + "CMT_TOP_LH7_11", + "CMT_TOP_FAN7_10", + "CMT_TOP_IMUX22_11", + "CMT_TOP_IMUX40_10", + "CMT_TOP_R_UPPER_T_PLLE2_DO2", + "CMT_TOP_WW2A2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_WW2END0_4", + "CMT_TOP_NW2A2_1", + "CMT_TOP_EE4A1_9", + "CMT_TOP_NE4C3_6", + "CMT_TOP_OCLK_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", + "CMT_PLL_DQS_TO_PHASER_D", + "CMT_TOP_ER1BEG2_0", + "CMT_TOP_NW4A2_3", + "CMT_TOP_EE2BEG1_10", + "CMT_TOP_EE2BEG0_12", + "CMT_TOP_WW4C3_3", + "CMT_TOP_NW4END1_4", + "CMT_TOP_NW2A1_2", + "CMT_TOP_EE4BEG0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_TOP_WW4END0_7", + "CMT_TOP_SW4A3_2", + "CMT_TOP_R_UPPER_T_PLLE2_DI11", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_IMUX5_8", + "CMT_TOP_WW4A1_11", + "CMT_TOP_SW4A1_5", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_MONITOR_N_11", + "CMT_TOP_IMUX32_6", + "CMT_TOP_SE2A2_12", + "CMT_TOP_NW2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_WW4B0_10", + "CMT_TOP_WW4A1_0", + "CMT_TOP_EE2A3_6", + "CMT_TOP_WR1END2_10", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_BYP0_6", + "CMT_TOP_WL1END1_5", + "CMT_TOP_IMUX30_0", + "CMT_TOP_LOGIC_OUTS_L_B5_9", + "CMT_TOP_NW2A0_8", + "CMT_TOP_WW4C1_5", + "CMT_TOP_SE4BEG2_11", + "CMT_TOP_NW4A3_11", + "CMT_TOP_WW4C3_12", + "CMT_TOP_IMUX34_6", + "CMT_TOP_SW4A2_4", + "CMT_TOP_NE4C3_1", + "CMT_TOP_NW4A1_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", + "CMT_TOP_IMUX22_6", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX1_4", + "CMT_TOP_SW4A1_0", + "CMT_TOP_IMUX41_9", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_FAN2_2", + "CMT_TOP_IMUX33_4", + "CMT_TOP_SE4C0_8", + "CMT_TOP_EE2BEG0_11", + "CMT_TOP_NE4BEG3_12", + "CMT_TOP_IMUX32_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", + "CMT_TOP_L_CLKFBOUT2IN", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_EE2A2_4", + "CMT_TOP_EE2BEG1_3", + "CMT_TOP_WW4B2_7", + "CMT_TOP_EE4B1_3", + "CMT_TOP_SW4END0_0", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH10_2", + "CMT_TOP_IMUX4_8", + "CMT_TOP_NE4C1_11", + "CMT_TOP_WW2A1_1", + "CMT_TOP_EE4A1_0", + "CMT_TOP_IMUX9_6", + "CMT_TOP_IMUX42_3", + "CMT_TOP_IMUX13_10", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", + "CMT_TOP_WR1END0_6", + "CMT_TOP_OCLK1X_90_11", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_TOP_IMUX22_2", + "CMT_TOP_R_UPPER_T_PLLE2_DI1", + "CMT_TOP_SE4C3_6", + "CMT_TOP_IMUX44_4", + "CMT_TOP_CTRL0_1", + "CMT_TOP_IMUX29_10", + "CMT_TOP_IMUX12_11", + "CMT_TOP_WW4B2_0", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_LH12_5", + "CMT_TOP_NE4BEG3_11", + "CMT_TOP_IMUX12_6", + "PLL_CLK_FREQ_BB2_NS", + "CMT_TOP_IMUX23_4", + "CMT_TOP_NE4BEG1_5", + "CMT_TOP_NE2A3_6", + "CMT_TOP_ICLK_3", + "CMT_TOP_IMUX7_4", + "CMT_TOP_CLK0_4", + "CMT_TOP_SE2A3_4", + "CMT_TOP_NE2A3_11", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_IMUX28_6", + "CMT_TOP_WW4A3_8", + "CMT_TOP_EE2A0_0", + "CMT_TOP_SE2A1_0", + "CMT_TOP_LH12_10", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_WW4B1_2", + "CMT_TOP_CTRL1_3", + "CMT_TOP_OCLK1X_90_12", + "CMT_TOP_EE4A3_8", + "CMT_TOP_NW4A0_2", + "CMT_TOP_IMUX26_5", + "CMT_TOP_IMUX27_10", + "CMT_TOP_EE4BEG3_10", + "CMT_TOP_LH6_3", + "CMT_TOP_IMUX40_6", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_WR1END2_4", + "CMT_TOP_WW4C1_11", + "CMT_TOP_IMUX20_4", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_TOP_WW4END2_7", + "CMT_TOP_BYP4_7", + "CMT_TOP_FAN4_11", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_TOP_NE2A2_8", + "CMT_TOP_SE4C0_9", + "CMT_TOP_IMUX34_0", + "CMT_TOP_NE2A1_6", + "CMT_TOP_NE4BEG3_10", + "CMT_TOP_LOGIC_OUTS_L_B7_12", + "CMT_TOP_IMUX2_9", + "CMT_TOP_IMUX0_8", + "CMT_PLL_PHASERREF_BELOW0", + "CMT_TOP_IMUX31_6", + "CMT_TOP_IMUX36_10", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_TOP_WW4END3_7", + "CMT_TOP_WL1END0_9", + "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "CMT_TOP_SW4A0_1", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE2A2_1", + "CMT_TOP_SW2A3_11", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_SW2A1_5", + "CMT_TOP_BLOCK_OUTS_L_B2_10", + "CMT_TOP_CTRL1_8", + "CMT_TOP_OCLK1X_90_9", + "CMT_TOP_NW4A2_5", + "CMT_TOP_NW4A0_0", + "CMT_TOP_WW2A1_10", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_PLL_PHASER_IN_D_ICLK", + "CMT_TOP_IMUX41_1", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX11_7", + "CMT_TOP_IMUX1_12", + "CMT_TOP_NE4C2_11", + "CMT_TOP_R_UPPER_T_PLLE2_DI0", + "PLLOUT_CLK_FREQ_BB_0", + "CMT_TOP_IMUX14_3", + "CMT_TOP_IMUX17_1", + "CMT_TOP_WW4A2_4", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_ICLKDIV_10", + "CMT_TOP_IMUX4_1", + "CMT_TOP_IMUX23_1", + "CMT_TOP_NW4A0_3", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_TOP_IMUX17_9", + "CMT_TOP_EE2A0_2", + "CMT_TOP_LOGIC_OUTS_L_B21_11", + "CMT_TOP_WW4A3_12", + "CMT_TOP_WW4END3_3", + "CMT_TOP_LH2_6", + "CMT_TOP_WW4B1_9", + "CMT_TOP_WR1END2_11", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_IMUX32_11", + "CMT_TOP_BYP2_8", + "CMT_TOP_WW4A0_0", + "CMT_TOP_WR1END3_5", + "CMT_TOP_SE4BEG1_3", + "CMT_TOP_WW4END3_2", + "CMT_TOP_WL1END3_3", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_IMUX34_8", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_CTRL0_7", + "CMT_TOP_IMUX43_9", + "CMT_TOP_WW2END1_12", + "CMT_TOP_IMUX13_1", + "CMT_TOP_IMUX11_1", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_SE2A2_3", + "CMT_TOP_NE2A3_4", + "CMT_TOP_OCLKDIV_11", + "CMT_TOP_EE4C2_6", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_SW2A3_10", + "CMT_TOP_SW2A0_5", + "CMT_TOP_LH7_9", + "CMT_TOP_CTRL1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_TOP_IMUX24_12", + "CMT_TOP_LH8_5", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_WL1END3_6", + "CMT_PLL_PHASER_RDENABLE_TOFIFO", + "CMT_TOP_LH1_1", + "CMT_TOP_IMUX4_7", + "CMT_TOP_WW4END2_10", + "CMT_TOP_IMUX24_4", + "CMT_TOP_BYP7_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", + "CMT_TOP_SE4BEG2_12", + "CMT_TOP_FAN2_9", + "CMT_TOP_LOGIC_OUTS_L_B15_11", + "CMT_TOP_WW4A1_9", + "CMT_TOP_EE4C2_11", + "CMT_TOP_IMUX19_1", + "CMT_TOP_LOGIC_OUTS_L_B23_10", + "CMT_TOP_FAN2_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", + "CMT_TOP_NW2A1_9", + "CMT_TOP_LOGIC_OUTS_L_B8_11", + "CMT_TOP_SE4C2_7", + "CMT_TOP_LH5_9", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH7_2", + "CMT_TOP_IMUX13_6", + "CMT_TOP_IMUX1_1", + "CMT_TOP_R_UPPER_T_PLLE2_DI15", + "CMT_TOP_IMUX4_11", + "CMT_TOP_LH3_8", + "CMT_TOP_LOGIC_OUTS_L_B5_12", + "CMT_TOP_EE4C3_3", + "CMT_TOP_SW4A0_0", + "CMT_TOP_SW2A1_8", + "CMT_TOP_IMUX5_9", + "CMT_TOP_IMUX46_0", + "CMT_TOP_IMUX3_0", + "CMT_TOP_IMUX17_12", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_TOP_EE4C2_0", + "CMT_TOP_IMUX16_1", + "CMT_TOP_SW4END2_5", + "CMT_TOP_IMUX16_0", + "CMT_TOP_EE2A1_0", + "CMT_TOP_NW4END0_4", + "CMT_TOP_IMUX12_7", + "CMT_TOP_NW4A0_9", + "CMT_TOP_WR1END1_3", + "CMT_TOP_R_UPPER_T_PLLE2_DI14", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_IMUX42_9", + "CMT_TOP_IMUX47_5", + "CMT_TOP_IMUX31_2", + "CMT_TOP_WR1END0_9", + "CMT_TOP_IMUX17_5", + "CMT_TOP_WW4END3_11", + "CMT_TOP_CLK1_3", + "CMT_TOP_ICLKDIV_11", + "CMT_TOP_R_UPPER_T_PLLE2_DO7", + "CMT_TOP_SE2A1_9", + "CMT_TOP_EE2A3_2", + "CMT_TOP_LH12_9", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_SE4C0_11", + "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT", + "CMT_TOP_SE4C1_10", + "CMT_TOP_SE4C3_8", + "CMT_TOP_EE4BEG0_12", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT", + "CMT_TOP_IMUX43_11", + "CMT_TOP_IMUX39_1", + "CMT_TOP_LH1_3", + "CMT_TOP_BYP5_7", + "CMT_TOP_IMUX6_11", + "CMT_TOP_IMUX47_8", + "CMT_TOP_IMUX36_0", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_NW4A2_2", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_IMUX26_9", + "CMT_TOP_IMUX46_10", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END1_6", + "CMT_TOP_WL1END1_8", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_WW2END1_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", + "PLLOUT_CLK_FREQ_BB_2", + "CMT_TOP_WW4END0_6", + "CMT_TOP_SE2A2_6", + "CMT_TOP_L_UPPER_T_CLKPLL2", + "CMT_TOP_WW4A3_11", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_FAN5_0", + "CMT_TOP_LOGIC_OUTS_L_B3_11", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_IMUX7_2", + "CMT_TOP_SW4A3_11", + "CMT_TOP_SE2A3_10", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_FAN4_12", + "CMT_TOP_LH2_0", + "CMT_TOP_SE2A0_6", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LH9_2", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B4_9", + "CMT_TOP_WW2A3_1", + "CMT_TOP_LH5_3", + "CMT_TOP_NE2A0_6", + "CMT_TOP_FAN4_1", + "CMT_TOP_LH12_1", + "CMT_TOP_LH8_6", + "CMT_TOP_IMUX36_5", + "CMT_TOP_OCLK_6", + "CMT_TOP_SW4END1_5", + "CMT_TOP_LOGIC_OUTS_L_B1_9", + "CMT_TOP_NW4END0_12", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_FAN6_6", + "CMT_TOP_NE2A2_7", + "CMT_TOP_LH7_6", + "CMT_TOP_WW4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX45_3", + "CMT_TOP_IMUX16_12", + "CMT_TOP_NE4BEG1_10", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_WR1END1_10", + "CMT_TOP_LOGIC_OUTS_L_B16_10", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_SW2A0_3", + "CMT_TOP_NE4C1_12", + "CMT_TOP_EE4C0_7", + "CMT_TOP_NW2A0_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", + "CMT_TOP_IMUX12_12", + "CMT_TOP_NW4END1_6", + "CMT_TOP_IMUX34_11", + "CMT_TOP_IMUX38_4", + "CMT_TOP_FAN6_7", + "CMT_TOP_EE4BEG1_11", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_IMUX41_5", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_SW4END2_3", + "CMT_TOP_EE2BEG3_8", + "CMT_TOP_LH9_7", + "CMT_TOP_IMUX4_12", + "CMT_TOP_WW4A1_1", + "CMT_TOP_WR1END0_3", + "CMT_TOP_LH1_6", + "CMT_TOP_FAN2_7", + "CMT_TOP_BYP7_6", + "CMT_TOP_IMUX40_11", + "CMT_TOP_NW4A1_5", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_1", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_IMUX2_10", + "CMT_TOP_IMUX32_10", + "CMT_TOP_FAN6_8", + "CMT_TOP_EE4BEG1_10", + "CMT_TOP_IMUX39_12", + "CMT_TOP_NW4A2_4", + "CMT_TOP_WW4C2_4", + "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", + "CMT_TOP_LH6_5", + "CMT_TOP_LOGIC_OUTS_L_B11_9", + "CMT_TOP_FAN5_7", + "CMT_TOP_BYP2_12", + "CMT_TOP_OCLK_2", + "CMT_TOP_WL1END1_6", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_BYP6_0", + "CMT_TOP_WL1END3_9", + "CMT_TOP_EE2BEG2_6", + "CMT_TOP_WW2END3_9", + "CMT_TOP_IMUX25_9", + "CMT_TOP_NW4END1_7", + "CMT_TOP_EE2A1_4", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_IMUX33_6", + "CMT_TOP_LH2_8", + "CMT_TOP_NW4A2_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", + "CMT_TOP_NE4C1_6", + "CMT_TOP_IMUX8_9", + "CMT_TOP_SW2A1_12", + "CMT_TOP_NE2A0_3", + "CMT_TOP_SE4C3_7", + "CMT_TOP_IMUX34_10", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_IMUX31_1", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_WW4C3_7", + "CMT_TOP_IMUX32_9", + "CMT_TOP_IMUX8_4", + "CMT_TOP_NW2A2_10", + "CMT_TOP_IMUX33_1", + "CMT_TOP_IMUX32_12", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_BYP0_12", + "CMT_TOP_WW4END1_3", + "CMT_TOP_FAN1_11", + "CMT_TOP_SW2A0_1", + "CMT_TOP_IMUX33_8", + "CMT_TOP_NW4A1_3", + "CMT_TOP_LH10_0", + "CMT_TOP_LH5_6", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX7_5", + "CMT_TOP_EE4C2_1", + "CMT_TOP_NE2A3_9", + "CMT_TOP_ER1BEG2_5", + "CMT_TOP_NW2A3_11", + "CMT_TOP_SW4A2_12", + "CMT_TOP_EE4BEG1_5", + "CMT_PLL_PHASERD_DTSBUS0", + "CMT_TOP_EE2A1_3", + "CMT_TOP_EE4C2_4", + "CMT_TOP_SW4A2_3", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_NE4C3_7", + "CMT_TOP_IMUX12_2", + "CMT_TOP_WW4B1_8", + "CMT_TOP_SE2A1_11", + "CMT_TOP_NW4A2_12", + "CMT_TOP_LH6_12", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_IMUX3_9", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_TOP_IMUX21_3", + "CMT_TOP_LH4_11", + "CMT_TOP_EE4A2_3", + "CMT_TOP_LH1_11", + "CMT_TOP_SW4A2_6", + "CMT_TOP_IMUX35_8", + "CMT_TOP_IMUX9_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", + "CMT_TOP_SW4END0_11", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_WW2A3_12", + "CMT_TOP_IMUX16_4", + "CMT_TOP_IMUX39_11", + "CMT_TOP_LH2_4", + "CMT_TOP_LOGIC_OUTS_L_B14_9", + "CMT_TOP_WW4C0_2", + "CMT_TOP_CTRL1_11", + "CMT_TOP_EE4B2_11", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_EE2A0_12", + "CMT_TOP_LH3_6", + "CMT_TOP_WW4A0_12", + "CMT_TOP_EE4C3_0", + "CMT_TOP_IMUX40_1", + "CMT_TOP_CLK0_10", + "CMT_TOP_EE4B0_10", + "CMT_TOP_R_UPPER_T_PLLE2_DI7", + "CMT_TOP_WW4C3_11", + "CMT_TOP_IMUX20_11", + "CMT_TOP_FAN7_9", + "CMT_TOP_IMUX32_2", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_ER1BEG0_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", + "CMT_TOP_LH1_4", + "CMT_TOP_BYP1_11", + "CMT_TOP_BYP0_1", + "CMT_TOP_FAN3_10", + "CMT_TOP_NE4C0_6", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_IMUX24_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", + "CMT_TOP_IMUX12_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", + "CMT_TOP_IMUX29_3", + "CMT_TOP_IMUX18_0", + "CMT_TOP_SW2A0_6", + "CMT_TOP_FAN7_6", + "CMT_TOP_LOGIC_OUTS_L_B21_10", + "CMT_TOP_IMUX24_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", + "CMT_TOP_EE4A0_3", + "CMT_TOP_NE4C3_12", + "CMT_TOP_SW2A3_6", + "CMT_TOP_IMUX10_10", + "CMT_TOP_BLOCK_OUTS_L_B2_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", + "CMT_TOP_IMUX44_11", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_NW2A0_7", + "CMT_TOP_L_UPPER_T_FREQ_BB1", + "CMT_TOP_WR1END2_5", + "CMT_TOP_ER1BEG3_12", + "CMT_TOP_BYP5_3", + "CMT_TOP_NW4A2_1", + "CMT_TOP_FAN5_6", + "CMT_TOP_IMUX32_4", + "CMT_TOP_R_UPPER_T_PLLE2_DI13", + "CMT_TOP_LH6_11", + "CMT_TOP_LOGIC_OUTS_L_B16_12", + "CMT_TOP_LOGIC_OUTS_L_B3_12", + "CMT_TOP_SE4BEG3_9", + "CMT_TOP_EE4C3_1", + "CMT_TOP_CTRL0_3", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_TOP_LH5_11", + "CMT_TOP_SE4BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_SW4END1_7", + "CMT_TOP_NW4A3_10", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_IMUX6_5", + "CMT_TOP_WW4A3_5", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_BYP3_9", + "CMT_TOP_EE4A1_12", + "CMT_TOP_IMUX26_2", + "CMT_TOP_IMUX20_10", + "CMT_TOP_IMUX13_4", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_NW4END2_12", + "CMT_TOP_WW4C3_8", + "CMT_TOP_NE2A0_8", + "CMT_TOP_LH6_4", + "CMT_TOP_NW2A2_4", + "CMT_TOP_IMUX20_9", + "CMT_TOP_WW2END3_6", + "CMT_TOP_FAN6_10", + "CMT_TOP_EE4B2_9", + "CMT_TOP_L_UPPER_T_CLKPLL7", + "CMT_TOP_WW4B1_1", + "CMT_TOP_WW4B1_7", + "CMT_TOP_WW2A3_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", + "CMT_TOP_NW4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_IMUX9_11", + "CMT_TOP_BYP7_3", + "CMT_TOP_IMUX25_0", + "CMT_TOP_NE4C2_8", + "CMT_TOP_IMUX41_0", + "CMT_TOP_WL1END2_9", + "CMT_TOP_LH4_4", + "CMT_TOP_WW4B3_12", + "CMT_TOP_IMUX24_3", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_LOGIC_OUTS_L_B14_12", + "CMT_TOP_EE4C3_12", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_NW2A0_4", + "CMT_TOP_EE2A1_2", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX46_3", + "CMT_TOP_WW2END3_11", + "CMT_TOP_CLK1_11", + "CMT_TOP_EE4A2_0", + "CMT_TOP_SE2A2_4", + "CMT_TOP_IMUX29_11", + "CMT_TOP_EE4A0_7", + "CMT_TOP_WW4C2_3", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_IMUX32_3", + "CMT_TOP_EE2A0_11", + "CMT_TOP_IMUX11_8", + "CMT_TOP_ER1BEG2_10", + "CMT_TOP_IMUX27_5", + "CMT_TOP_IMUX36_8", + "CMT_TOP_NW2A1_10", + "CMT_TOP_WL1END1_0", + "CMT_TOP_LH10_12", + "CMT_TOP_IMUX47_3", + "CMT_TOP_IMUX0_2", + "CMT_TOP_NW4END3_11", + "CMT_TOP_WW2A1_6", + "CMT_TOP_SW4A2_1", + "CMT_PLL_PHASER_OUT_D_OCLKDIV", + "CMT_TOP_NW2A0_10", + "CMT_TOP_NW2A2_2", + "CMT_TOP_IMUX5_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4BEG1_4", + "CMT_TOP_WW4END3_9", + "CMT_TOP_SW4A1_12", + "CMT_TOP_MONITOR_P_2", + "CMT_TOP_IMUX30_11", + "CMT_TOP_WW4C3_1", + "CMT_TOP_IMUX33_5", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SE4C2_3", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_EE4A0_9", + "CMT_TOP_LH7_7", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_BYP6_10", + "CMT_TOP_NW4END3_1", + "CMT_TOP_EE2BEG3_10", + "CMT_TOP_WW2END0_5", + "CMT_TOP_LH5_1", + "CMT_TOP_FAN3_12", + "CMT_TOP_LH8_7", + "CMT_TOP_OCLK_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", + "CMT_TOP_FAN6_5", + "CMT_TOP_IMUX27_1", + "CMT_TOP_NE4BEG2_1", + "CMT_PLL_PHYCTRL_SYNC_BB_DN", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_SE2A2_8", + "CMT_TOP_SE4C3_10", + "CMT_TOP_WL1END2_5", + "CMT_TOP_IMUX15_12", + "CMT_TOP_WW2A2_9", + "CMT_TOP_SE2A3_9", + "CMT_TOP_IMUX14_8", + "CMT_TOP_NW4END3_4", + "CMT_TOP_NE2A2_3", + "CMT_TOP_LH8_2", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_EE4A2_10", + "CMT_TOP_IMUX19_10", + "CMT_TOP_LOGIC_OUTS_L_B19_12", + "CMT_TOP_WR1END3_12", + "CMT_TOP_EE4BEG2_11", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_WW2END0_10", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_SE2A3_2", + "CMT_TOP_ER1BEG3_10", + "CMT_TOP_CLK1_8", + "CMT_TOP_IMUX47_12", + "CMT_TOP_LOGIC_OUTS_L_B15_12", + "CMT_TOP_EL1BEG2_11", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_NW4A0_1", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_NW4END2_1", + "CMT_TOP_EE4B0_8", + "CMT_TOP_NW4END2_8", + "CMT_TOP_CLK0_6", + "CMT_TOP_R_UPPER_T_PLLE2_DO10", + "CMT_TOP_WR1END2_6", + "CMT_TOP_WW4END0_1", + "CMT_PLL_PHASER_WRCLK_TOFIFO", + "CMT_TOP_NW2A1_7", + "CMT_TOP_WW4A2_6", + "CMT_TOP_IMUX27_3", + "CMT_TOP_SW2A3_0", + "CMT_TOP_EE2A2_9", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_WR1END2_2", + "CMT_TOP_EE4BEG2_9", + "CMT_TOP_EE2A2_7", + "CMT_TOP_IMUX26_10", + "CMT_TOP_IMUX8_0", + "CMT_TOP_IMUX21_9", + "CMT_TOP_WW4C1_1", + "CMT_TOP_EE4A0_12", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_LH5_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4C2_0", + "PLLOUT_CLK_FREQ_BB_3", + "CMT_TOP_BLOCK_OUTS_L_B2_12", + "CMT_TOP_EE2A2_11", + "CMT_TOP_WR1END0_8", + "CMT_TOP_WL1END1_4", + "CMT_TOP_WW4C0_10", + "CMT_TOP_WW4B1_6", + "CMT_TOP_WW2A3_7", + "CMT_TOP_BYP3_6", + "CMT_TOP_EE4B1_8", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_IMUX9_1", + "CMT_TOP_SE4C1_5", + "CMT_TOP_LH4_7", + "CMT_TOP_LOGIC_OUTS_L_B5_10", + "CMT_TOP_IMUX20_5", + "CMT_TOP_NE4BEG2_12", + "CMT_TOP_NE4C2_4", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_WW4B1_0", + "CMT_TOP_IMUX0_10", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_IMUX23_7", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_TOP_SE4C1_12", + "CMT_TOP_EE4A2_7", + "CMT_TOP_FAN3_9", + "CMT_TOP_EE2A0_8", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_NW4END0_8", + "CMT_TOP_WW4B2_3", + "CMT_TOP_IMUX23_0", + "CMT_TOP_EE2BEG3_1", + "CMT_TOP_LH6_8", + "CMT_TOP_SW4END0_10", + "CMT_TOP_LH6_10", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_WL1END0_0", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_FAN0_2", + "CMT_TOP_LOGIC_OUTS_L_B10_10", + "CMT_TOP_LH2_11", + "CMT_TOP_WW2END2_0", + "CMT_TOP_IMUX18_3", + "CMT_TOP_IMUX6_10", + "CMT_TOP_BLOCK_OUTS_L_B0_12", + "CMT_TOP_FAN1_1", + "CMT_TOP_NW2A3_8", + "CMT_TOP_LH7_1", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_IMUX43_5", + "CMT_TOP_SE4BEG1_10", + "CMT_TOP_EE4B1_10", + "CMT_TOP_IMUX41_4", + "CMT_TOP_IMUX33_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_SE2A3_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", + "CMT_TOP_SE4C0_0", + "CMT_TOP_NE2A2_9", + "CMT_TOP_OCLKDIV_2", + "CMT_TOP_WW4C2_12", + "CMT_TOP_WW4B3_4", + "CMT_TOP_R_UPPER_T_PLLE2_DI8", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX5_3", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_PLL_PHASERREF0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", + "CMT_TOP_BYP2_9", + "CMT_TOP_IMUX23_10", + "PLLOUT_CLK_FREQ_BB_1", + "CMT_TOP_LH5_0", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_IMUX42_10", + "CMT_TOP_LH10_10", + "CMT_TOP_WW4END2_11", + "CMT_TOP_EE4A1_4", + "CMT_TOP_NW4A1_10", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX11_0", + "CMT_TOP_WW2END3_5", + "CMT_TOP_LH7_8", + "CMT_TOP_NE4C1_3", + "CMT_TOP_CTRL1_6", + "CMT_TOP_WW4C2_11", + "CMT_TOP_CLK1_9", + "CMT_TOP_IMUX31_3", + "CMT_TOP_R_UPPER_T_PLLE2_DO15", + "CMT_TOP_IMUX37_3", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_LOGIC_OUTS_L_B18_11", + "CMT_TOP_WW4C0_0", + "CMT_TOP_R_UPPER_T_PLLE2_DCLK", + "CMT_TOP_WW4A0_5", + "CMT_TOP_LH9_12", + "CMT_TOP_EE4C3_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", + "CMT_TOP_IMUX3_8", + "CMT_TOP_NW4END1_11", + "CMT_TOP_WW2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B9_10", + "CMT_TOP_SE2A0_4", + "CMT_TOP_IMUX15_1", + "CMT_TOP_IMUX6_3", + "CMT_TOP_IMUX45_9", + "CMT_TOP_EE4B2_7", + "CMT_TOP_NW2A2_9", + "CMT_TOP_LH3_11", + "CMT_TOP_WR1END0_7", + "CMT_TOP_IMUX24_5", + "CMT_TOP_FAN2_1", + "CMT_TOP_IMUX5_6", + "CMT_TOP_NW4END0_10", + "CMT_TOP_SE4BEG0_9", + "CMT_TOP_NW4END1_9", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_BYP6_5", + "CMT_TOP_ER1BEG3_5", + "CMT_TOP_IMUX37_5", + "CMT_TOP_IMUX37_8", + "CMT_TOP_EE4C0_0", + "CMT_TOP_WW4END2_1", + "CMT_TOP_EE4A1_6", + "CMT_TOP_LOGIC_OUTS_L_B12_10", + "CMT_TOP_SW4END1_0", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_IMUX35_3", + "CMT_TOP_SE4BEG0_12", + "CMT_TOP_WW4A2_3", + "CMT_TOP_IMUX10_4", + "CMT_TOP_BYP6_9", + "CMT_TOP_LOGIC_OUTS_L_B13_9", + "CMT_TOP_WW4END2_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", + "CMT_TOP_IMUX26_6", + "CMT_TOP_EE4A3_0", + "CMT_TOP_IMUX18_10", + "CMT_TOP_IMUX22_10", + "CMT_TOP_EE2A1_5", + "CMT_TOP_SW4END3_1", + "CMT_TOP_EL1BEG1_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", + "CMT_TOP_IMUX4_4", + "CMT_TOP_LOGIC_OUTS_L_B11_12", + "CMT_TOP_NW4END3_3", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_WW4C1_2", + "CMT_TOP_EE2A1_12", + "CMT_TOP_SW4A2_9", + "CMT_TOP_EL1BEG2_12", + "CMT_TOP_IMUX22_0", + "CMT_TOP_LOGIC_OUTS_L_B16_11", + "CMT_TOP_SE2A1_1", + "CMT_TOP_WL1END1_12", + "CMT_TOP_NW2A3_9", + "CMT_TOP_WR1END0_4", + "CMT_TOP_EE2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_WW4A1_10", + "CMT_TOP_EE4C0_6", + "CMT_TOP_IMUX24_0", + "CMT_TOP_EL1BEG1_4", + "CMT_TOP_LOGIC_OUTS_L_B6_12", + "CMT_TOP_WW4B3_10", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_SW2A3_3", + "CMT_TOP_SW4END0_1", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_EE4B1_0", + "CMT_TOP_NE2A3_2", + "CMT_TOP_ER1BEG1_9", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_TOP_ICLK_12", + "CMT_TOP_EE4B1_6", + "CMT_TOP_LH3_9", + "CMT_TOP_BYP3_2", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_LH5_12", + "CMT_TOP_R_UPPER_T_PLLE2_DO6", + "CMT_TOP_SE4BEG1_9", + "CMT_TOP_IMUX34_9", + "CMT_TOP_CLK0_2", + "CMT_TOP_SE4C1_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", + "CMT_TOP_LH10_1", + "CMT_TOP_IMUX22_12", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_SE4BEG3_11", + "CMT_TOP_LOGIC_OUTS_L_B10_11", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_FAN3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_TOP_R_UPPER_T_PLLE2_DI3", + "CMT_TOP_WW4A0_9", + "CMT_TOP_SW2A1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_IMUX3_4", + "CMT_TOP_ICLK_5", + "CMT_TOP_IMUX47_9", + "CMT_TOP_L_UPPER_T_FREQ_BB2", + "CMT_TOP_IMUX15_9", + "CMT_TOP_LH12_12", + "CMT_TOP_IMUX31_0", + "CMT_TOP_IMUX29_8", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_LH2_3", + "CMT_TOP_WR1END1_9", + "CMT_TOP_IMUX28_10", + "CMT_TOP_NE4C1_4", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_IMUX2_4", + "CMT_TOP_IMUX38_11", + "CMT_TOP_EE4C1_1", + "CMT_TOP_SW2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_LH8_4", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_WW4END2_0", + "CMT_TOP_EE4C0_1", + "CMT_TOP_IMUX33_11", + "CMT_TOP_FAN5_8", + "CMT_TOP_WW4C1_0", + "CMT_TOP_LOGIC_OUTS_L_B11_11", + "CMT_TOP_EE2A3_9", + "CMT_TOP_LH10_7", + "CMT_TOP_SE4C0_1", + "CMT_TOP_NW4END3_9", + "CMT_TOP_WW4C1_7", + "CMT_TOP_SE2A0_5", + "CMT_TOP_EE2BEG1_9", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_ER1BEG3_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", + "CMT_TOP_IMUX47_11", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BYP0_0", + "CMT_TOP_EE4B2_2", + "CMT_TOP_FAN7_7", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_WW4A0_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", + "CMT_TOP_WW4B0_12", + "CMT_TOP_WW4A3_0", + "CMT_TOP_SE4C1_1", + "CMT_TOP_ER1BEG0_6", + "CMT_TOP_IMUX46_1", + "CMT_TOP_FAN6_11", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_IMUX30_8", + "CMT_TOP_SW2A1_0", + "CMT_TOP_CLK0_1", + "CMT_TOP_BYP5_4", + "CMT_TOP_IMUX45_2", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_WW4C2_6", + "CMT_TOP_IMUX19_5", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_IMUX35_12", + "CMT_TOP_NW4END0_1", + "CMT_TOP_LH3_10", + "CMT_TOP_LH9_8", + "CMT_TOP_R_UPPER_T_PLLE2_DO9", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_TOP_L_UPPER_T_CLKPLL3", + "CMT_TOP_NW2A2_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", + "CMT_TOP_LH11_12", + "CMT_TOP_SW4END0_5", + "CMT_TOP_IMUX29_1", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_IMUX9_5", + "CMT_TOP_SW4A0_2", + "CMT_TOP_WW2END1_5", + "CMT_TOP_WW2A2_8", + "CMT_TOP_WW4A1_12", + "CMT_TOP_OCLK_8", + "CMT_TOP_IMUX46_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", + "CMT_TOP_EE4C1_12", + "CMT_TOP_IMUX8_3", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_IMUX14_7", + "CMT_TOP_NW2A2_0", + "CMT_TOP_SE4C0_5", + "CMT_TOP_SW4END3_4", + "CMT_TOP_SE2A2_7", + "CMT_TOP_SW2A1_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_IMUX22_8", + "CMT_TOP_LH3_7", + "CMT_TOP_IMUX1_11", + "CMT_TOP_SE2A1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_9", + "CMT_TOP_IMUX43_8", + "CMT_TOP_LH10_5", + "CMT_TOP_NE4BEG2_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_BLOCK_OUTS_L_B3_10", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_NE2A0_0", + "CMT_TOP_NE2A2_6", + "CMT_TOP_SW2A3_12", + "CMT_TOP_NE2A1_12", + "CMT_TOP_WW4C2_9", + "CMT_TOP_SW2A2_2", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_LH11_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", + "CMT_TOP_EE2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_LOGIC_OUTS_L_B20_10", + "CMT_TOP_WW2A2_4", + "CMT_TOP_EE4C1_10", + "CMT_TOP_LH5_2", + "CMT_TOP_IMUX17_8", + "CMT_TOP_EE4BEG1_12", + "CMT_TOP_IMUX36_7", + "CMT_TOP_BYP1_7", + "CMT_TOP_IMUX4_5", + "CMT_TOP_IMUX36_12", + "CMT_TOP_EE4C0_4", + "CMT_TOP_EL1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B13_10", + "CMT_TOP_LOGIC_OUTS_L_B19_10", + "CMT_TOP_ICLK_7", + "CMT_TOP_NE4BEG0_10", + "CMT_TOP_LH11_3", + "CMT_TOP_IMUX32_1", + "CMT_TOP_SW2A2_4", + "CMT_TOP_IMUX11_4", + "CMT_TOP_IMUX9_10", + "CMT_TOP_EE4C3_7", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_WW4B3_0", + "CMT_TOP_IMUX10_5", + "CMT_TOP_WW2END1_1", + "CMT_TOP_FAN0_9", + "CMT_TOP_FAN1_7", + "CMT_TOP_IMUX23_2", + "CMT_TOP_IMUX5_0", + "CMT_TOP_ICLK_6", + "CMT_TOP_EE4A2_9", + "CMT_TOP_IMUX22_1", + "CMT_TOP_WW4B0_8", + "CMT_TOP_IMUX42_11", + "CMT_TOP_OCLKDIV_6", + "CMT_TOP_LH2_9", + "CMT_TOP_NW4A3_1", + "CMT_TOP_IMUX27_0", + "CMT_TOP_SE4C2_8", + "CMT_TOP_WW2END0_9", + "CMT_TOP_SE4C2_4", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_EE2BEG3_12", + "CMT_TOP_SE2A2_1", + "CMT_TOP_NW4END1_5", + "CMT_TOP_EE2BEG0_7", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_WW2A0_12", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX14_10", + "CMT_TOP_WR1END0_12", + "CMT_TOP_IMUX42_7", + "CMT_TOP_EL1BEG0_9", + "CMT_TOP_IMUX41_11", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_IMUX34_12", + "CMT_TOP_WR1END1_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", + "CMT_TOP_IMUX35_7", + "CMT_PLL_PHASERREF_ABOVE0", + "CMT_TOP_SW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_FAN3_7", + "CMT_TOP_LH9_9", + "CMT_TOP_SW4A1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", + "CMT_TOP_SW2A0_8", + "CMT_TOP_IMUX28_9", + "CMT_TOP_EE4B3_7", + "CMT_TOP_WW2A3_11", + "CMT_TOP_IMUX44_3", + "CMT_TOP_IMUX31_10", + "CMT_PLL_PHASERD_DTSBUS1", + "CMT_TOP_EE4B3_10", + "CMT_TOP_WW2END2_12", + "CMT_TOP_NE4C1_9", + "CMT_TOP_SE2A0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_BYP2_3", + "CMT_TOP_IMUX12_10", + "CMT_TOP_IMUX40_3", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_IMUX11_6", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_IMUX39_10", + "CMT_TOP_BYP4_2", + "CMT_PLL_PHASERREF_ABOVE1", + "CMT_TOP_NE4BEG0_12", + "CMT_TOP_NE4BEG3_8", + "CMT_TOP_IMUX1_10", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_L_UPPER_T_CLKPLL1", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_SW2A1_9", + "CMT_TOP_IMUX26_7", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_IMUX1_7", + "CMT_TOP_IMUX23_6", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_FAN5_10", + "CMT_TOP_IMUX6_8", + "CMT_TOP_IMUX4_3", + "CMT_TOP_EE4C1_6", + "CMT_TOP_NW4END3_7", + "CMT_TOP_WW2END3_12", + "CMT_TOP_IMUX13_5", + "CMT_TOP_IMUX46_6", + "CMT_TOP_WW4END0_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LH12_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_CLK1_2", + "CMT_TOP_WW4C2_10", + "CMT_TOP_LOGIC_OUTS_L_B18_10", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_IMUX15_7", + "CMT_TOP_SW4END2_0", + "CMT_TOP_WW4B0_9", + "CMT_TOP_WW4END1_5", + "CMT_TOP_NW4A0_5", + "CMT_TOP_EE2A2_2", + "CMT_TOP_WW4A0_2", + "CMT_TOP_IMUX37_6", + "CMT_TOP_WL1END1_11", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_LH10_11", + "CMT_TOP_IMUX0_0", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_NW2A3_4", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_IMUX42_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_LH3_1", + "CMT_TOP_EE2BEG3_11", + "CMT_TOP_WL1END3_11", + "CMT_TOP_EE4C0_2", + "CMT_TOP_IMUX23_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", + "CMT_TOP_IMUX35_6", + "CMT_TOP_SE2A3_11", + "CMT_TOP_FAN3_6", + "CMT_TOP_SW4END2_1", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_EE4A2_11", + "CMT_TOP_LOGIC_OUTS_L_B17_9", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_WW2A1_3", + "CMT_TOP_FAN2_5", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_TOP_WW2END1_8", + "CMT_TOP_WR1END2_0", + "CMT_TOP_NE2A1_0", + "CMT_TOP_BLOCK_OUTS_L_B3_12", + "CMT_TOP_LH1_8", + "CMT_TOP_WW2A0_7", + "CMT_TOP_FAN7_12", + "CMT_TOP_LOGIC_OUTS_L_B17_10", + "CMT_PLL_PHASERD_DQSBUS1", + "CMT_TOP_EE4BEG1_4", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_EE2BEG2_8", + "CMT_TOP_SW4END0_2", + "CMT_TOP_SW4A0_6", + "CMT_TOP_BYP5_8", + "CMT_TOP_FAN5_4", + "CMT_TOP_IMUX41_7", + "CMT_TOP_IMUX25_2", + "CMT_TOP_EE4A3_1", + "CMT_TOP_IMUX12_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", + "CMT_TOP_WW2A3_3", + "CMT_TOP_IMUX1_6", + "CMT_TOP_IMUX21_2", + "CMT_TOP_CLK1_1", + "CMT_TOP_IMUX27_12", + "CMT_TOP_WW4A2_0", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_TOP_IMUX16_9", + "CMT_TOP_WW4END3_10", + "CMT_TOP_FAN1_10", + "CMT_TOP_L_UPPER_T_CLKIN1", + "CMT_TOP_NE2A2_0", + "CMT_TOP_IMUX17_11", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_WW2END2_7", + "CMT_TOP_CTRL1_9", + "CMT_TOP_SE4BEG1_1", + "CMT_TOP_CTRL0_12", + "CMT_TOP_NW4END3_5", + "CMT_TOP_IMUX21_5", + "CMT_TOP_WW4END3_4", + "PLL_CLK_FREQ_BB3_NS", + "CMT_TOP_WL1END0_8", + "CMT_TOP_SE2A3_0", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", + "CMT_TOP_WW2END1_9", + "CMT_TOP_NW4A3_6", + "CMT_TOP_WL1END3_10", + "CMT_TOP_SE4C1_7", + "CMT_TOP_LOGIC_OUTS_L_B9_11", + "CMT_TOP_NW2A3_12", + "CMT_TOP_BYP0_8", + "CMT_TOP_IMUX2_11", + "CMT_TOP_EE4A3_3", + "CMT_TOP_WR1END2_12", + "CMT_TOP_LH10_6", + "CMT_TOP_NW4A3_2", + "CMT_TOP_NE4C0_11", + "CMT_TOP_LH3_4", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", + "CMT_TOP_LH8_0", + "CMT_TOP_IMUX24_6", + "CMT_TOP_IMUX45_8", + "CMT_TOP_IMUX33_7", + "CMT_TOP_ER1BEG0_10", + "CMT_TOP_IMUX28_7", + "CMT_TOP_FAN0_10", + "CMT_TOP_LH8_9", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_TOP_R_UPPER_T_PLLE2_DO0", + "CMT_TOP_WL1END1_9", + "CMT_TOP_EE4B0_5", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX15_10", + "CMT_TOP_CLK0_11", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_IMUX3_10", + "CMT_TOP_IMUX17_0", + "CMT_TOP_BYP3_8", + "CMT_TOP_NE2A3_1", + "CMT_TOP_EE4C2_12", + "CMT_TOP_NW2A3_2", + "CMT_TOP_EE4B3_1", + "CMT_TOP_WW4B3_5", + "CMT_TOP_BYP1_9", + "CMT_TOP_SE4C2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_SE2A1_7", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_SE4C3_12", + "CMT_TOP_CTRL1_12", + "CMT_TOP_WL1END3_5", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", + "CMT_TOP_IMUX3_1", + "CMT_TOP_WR1END2_1", + "CMT_TOP_NW4A1_4", + "CMT_TOP_WL1END2_11", + "CMT_TOP_WL1END1_10", + "CMT_TOP_IMUX20_3", + "CMT_TOP_BYP6_8", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX14_2", + "CMT_TOP_BYP4_4", + "CMT_TOP_CLK1_7", + "CMT_TOP_IMUX2_3", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_IMUX46_5", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_NW4END1_3", + "CMT_TOP_IMUX45_11", + "CMT_TOP_NW2A3_5", + "CMT_TOP_EL1BEG3_12", + "CMT_TOP_WR1END2_3", + "CMT_TOP_BYP2_6", + "CMT_TOP_BYP3_3", + "CMT_TOP_FAN6_2", + "CMT_TOP_NW2A2_3", + "CMT_TOP_SW4END2_12", + "CMT_TOP_IMUX40_4", + "CMT_TOP_MONITOR_P_11", + "CMT_TOP_WW4A0_10", + "CMT_TOP_IMUX47_6", + "CMT_TOP_SW4A3_4", + "CMT_TOP_FAN7_0", + "CMT_TOP_WW4A0_11", + "CMT_TOP_LH11_5", + "CMT_TOP_IMUX30_5", + "CMT_TOP_SE2A3_1", + "CMT_TOP_EE4A3_6", + "CMT_TOP_IMUX5_1", + "CMT_TOP_EE4BEG3_6", + "CMT_TOP_SE2A2_0", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_EE4B3_4", + "CMT_TOP_EE4C3_6", + "CMT_TOP_EE4C0_11", + "CMT_TOP_WW4B0_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", + "CMT_PHASER_D_OCLK_TOIOI", + "CMT_TOP_IMUX27_2", + "CMT_TOP_FAN0_8", + "CMT_TOP_EE4A2_6", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_FAN2_6", + "CMT_TOP_SE4BEG0_8", + "CMT_TOP_CLK0_9", + "CMT_TOP_LH1_10", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_SW2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_9", + "CMT_TOP_LOGIC_OUTS_L_B23_12", + "CMT_TOP_OCLK_12", + "CMT_TOP_IMUX46_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", + "CMT_TOP_IMUX3_11", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_NW4END0_6", + "CMT_TOP_IMUX10_0", + "CMT_TOP_IMUX43_4", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "CMT_TOP_EE4A0_0", + "CMT_TOP_IMUX36_1", + "CMT_TOP_LH1_0", + "CMT_TOP_WW4A3_6", + "CMT_TOP_EE2A1_9", + "CMT_TOP_IMUX0_12", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_LOGIC_OUTS_L_B4_11", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_TOP_WW4A3_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", + "CMT_TOP_WW4B2_9", + "CMT_TOP_EE4C0_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", + "CMT_TOP_BYP0_5", + "CMT_TOP_IMUX10_12", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", + "CMT_TOP_ICLK_2", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_FAN0_11", + "CMT_TOP_NE2A3_5", + "CMT_TOP_EL1BEG3_10", + "CMT_TOP_NE2A1_8", + "CMT_TOP_R_UPPER_T_PLLE2_DI2", + "CMT_PLL_PHASERD_CTSBUS1", + "CMT_TOP_LH12_2", + "CMT_TOP_WW2A0_10", + "CMT_TOP_EE4C2_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", + "CMT_TOP_IMUX47_10", + "CMT_TOP_IMUX30_9", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_IMUX19_8", + "CMT_TOP_IMUX17_6", + "CMT_TOP_WW2A2_6", + "CMT_TOP_IMUX14_5", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_TOP_BYP1_6", + "CMT_TOP_IMUX34_2", + "CMT_TOP_SW4A2_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", + "CMT_TOP_EE2BEG2_10", + "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT", + "CMT_TOP_WW4A2_8", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_IMUX39_5", + "CMT_TOP_NW4A2_7", + "CMT_TOP_IMUX38_1", + "CMT_TOP_WW2A0_8", + "CMT_TOP_ER1BEG1_12", + "CMT_TOP_CTRL1_4", + "CMT_TOP_NW2A1_12", + "CMT_TOP_SE2A0_11", + "CMT_TOP_CTRL0_10", + "CMT_TOP_NE4C2_0", + "CMT_TOP_FAN2_12", + "CMT_TOP_IMUX8_1", + "CMT_TOP_OCLK_0", + "CMT_TOP_NE4C2_7", + "CMT_TOP_IMUX20_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "CMT_TOP_SE2A3_12", + "CMT_TOP_R_UPPER_T_PLLE2_RST", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SE4C3_4", + "CMT_TOP_SE4C3_3", + "CMT_TOP_IMUX12_3", + "PLL_CLK_FREQ_BB_BUFOUT_NS1", + "CMT_PLL_PHASER_IN_D_ICLKDIV", + "CMT_TOP_IMUX19_12", + "CMT_TOP_CLK0_5", + "CMT_TOP_WW2END1_4", + "CMT_TOP_NW2A1_5", + "CMT_TOP_L_UPPER_T_CLKPLL0", + "CMT_TOP_IMUX16_2", + "CMT_TOP_MONITOR_N_10", + "CMT_TOP_BYP2_5", + "CMT_TOP_WR1END3_11", + "CMT_TOP_IMUX40_2", + "CMT_TOP_WW4B2_8", + "CMT_TOP_EE4B1_2", + "CMT_TOP_SE4C1_2", + "CMT_TOP_R_UPPER_T_PLLE2_DI12", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_SW4A1_9", + "CMT_TOP_FAN0_6", + "CMT_TOP_SW4END2_8", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_SE4BEG3_2", + "CMT_TOP_IMUX18_7", + "CMT_TOP_NW4A1_11", + "CMT_TOP_EE2BEG1_8", + "CMT_TOP_NE2A2_10", + "CMT_TOP_EE2BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B21_12", + "CMT_TOP_WW4A2_5", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX44_2", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_CTRL0_0", + "CMT_TOP_IMUX1_8", + "CMT_TOP_IMUX38_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_IMUX5_12", + "CMT_TOP_NW2A1_0", + "CMT_TOP_WW4B3_8", + "CMT_TOP_EE4BEG2_10", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_LOGIC_OUTS_L_B4_12", + "CMT_TOP_IMUX38_0", + "CMT_TOP_SW2A2_1", + "CMT_TOP_NE4C2_9", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_TOP_SE4BEG1_11", + "CMT_TOP_BYP1_3", + "CMT_TOP_CTRL0_6", + "CMT_TOP_EE4A3_10", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_IMUX17_3", + "CMT_TOP_NW2A3_10", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX28_2", + "CMT_TOP_IMUX43_12", + "CMT_TOP_EE2A0_9", + "CMT_TOP_IMUX21_8", + "CMT_TOP_EL1BEG3_11", + "CMT_TOP_IMUX42_2", + "CMT_TOP_WW2A3_6", + "CMT_TOP_WW4B0_4", + "CMT_TOP_SE2A2_5", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_TOP_IMUX38_9", + "CMT_TOP_BYP2_10", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EL1BEG0_10", + "CMT_TOP_EE4B1_11", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_EE2BEG2_7", + "CMT_TOP_ICLK_0", + "CMT_TOP_NW4END1_2", + "CMT_TOP_WW2A2_10", + "CMT_TOP_WW4END1_9", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX31_7", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_NW2A1_3", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX47_2", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_NE2A3_0", + "CMT_TOP_IMUX13_9", + "CMT_TOP_LH10_4", + "CMT_TOP_BYP0_2", + "CMT_TOP_CLK0_3", + "CMT_TOP_EE4B3_12", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_SW4A0_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", + "CMT_TOP_LOGIC_OUTS_L_B13_11", + "CMT_TOP_SW2A2_7", + "CMT_TOP_EL1BEG2_10", + "CMT_TOP_IMUX29_9", + "CMT_TOP_EE4B3_9", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_IMUX25_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_SE4BEG1_12", + "CMT_TOP_ICLK_10", + "CMT_TOP_NE4C1_7", + "CMT_TOP_NW2A2_11", + "CMT_TOP_EE4C3_8", + "CMT_TOP_ICLKDIV_12", + "CMT_TOP_IMUX4_2", + "CMT_TOP_NW4END0_0", + "CMT_TOP_IMUX11_9", + "CMT_TOP_EE4B2_10", + "CMT_TOP_IMUX0_6", + "CMT_TOP_WW4B0_1", + "CMT_TOP_FAN1_5", + "CMT_TOP_WL1END0_11", + "CMT_TOP_EE2A1_8", + "CMT_TOP_NE4C3_10", + "CMT_TOP_OCLK_10", + "CMT_TOP_WW2END2_2", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_FAN4_7", + "CMT_TOP_IMUX27_11", + "CMT_TOP_IMUX36_6", + "CMT_TOP_WW2END0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_EE4BEG3_11", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_EE4B3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_NW4A0_10", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_LH8_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_NE4C0_12", + "CMT_TOP_MONITOR_P_10", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_NE4C0_9", + "CMT_TOP_SW4A3_8", + "CMT_TOP_SW2A1_10", + "CMT_TOP_WW2A0_6", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_LH7_12", + "CMT_TOP_WL1END2_1", + "CMT_TOP_LH8_10", + "CMT_TOP_NE4C0_0", + "CMT_TOP_IMUX29_7", + "CMT_TOP_EE4B0_4", + "CMT_TOP_WR1END3_6", + "CMT_TOP_LOGIC_OUTS_L_B6_11", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_TOP_BLOCK_OUTS_L_B3_9", + "CMT_TOP_WW4B2_2", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_LH11_4", + "CMT_TOP_LH6_6", + "CMT_TOP_LOGIC_OUTS_L_B1_12", + "CMT_TOP_NE2A1_11", + "CMT_TOP_NW2A3_7", + "CMT_TOP_WW4END0_5", + "CMT_TOP_FAN4_8", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_IMUX22_7", + "CMT_TOP_IMUX8_12", + "CMT_TOP_WR1END1_2", + "CMT_TOP_IMUX2_6", + "CMT_TOP_BYP4_8", + "CMT_TOP_LOGIC_OUTS_L_B12_9", + "CMT_TOP_SE4C3_5", + "CMT_TOP_BLOCK_OUTS_L_B2_9", + "CMT_TOP_FAN5_12", + "CMT_TOP_IMUX15_4", + "CMT_TOP_IMUX39_9", + "CMT_TOP_IMUX4_9", + "CMT_TOP_BYP5_5", + "CMT_TOP_ICLK_1", + "CMT_TOP_BYP3_12", + "CMT_TOP_L_UPPER_T_FREQ_BB0", + "CMT_TOP_WW2END1_10", + "CMT_TOP_IMUX0_1", + "CMT_TOP_BYP6_7", + "CMT_TOP_WW4B2_6", + "CMT_TOP_IMUX32_7", + "CMT_TOP_LH3_3", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_SW4A2_8", + "CMT_TOP_SE2A0_12", + "CMT_TOP_WL1END3_7", + "CMT_TOP_SW4A1_7", + "CMT_TOP_SW2A3_5", + "CMT_TOP_EE4C2_9", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_WW4END1_8", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_SW4A3_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", + "CMT_TOP_FAN1_9", + "CMT_TOP_WW4A2_2", + "CMT_TOP_IMUX28_1", + "CMT_TOP_IMUX46_4", + "CMT_TOP_WW2END3_4", + "CMT_TOP_EE4B1_5", + "CMT_TOP_EE4B0_6", + "CMT_TOP_WR1END0_11", + "CMT_TOP_SW2A0_0", + "CMT_TOP_LH3_12", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_NW4A1_0", + "CMT_TOP_WW2END0_12", + "CMT_TOP_WW4B0_7", + "CMT_TOP_IMUX33_9", + "CMT_TOP_NW4END2_6", + "CMT_TOP_CLK1_4", + "CMT_TOP_IMUX13_12", + "CMT_TOP_IMUX17_10", + "CMT_TOP_BYP5_0", + "CMT_TOP_MONITOR_N_12", + "CMT_TOP_NE4C1_8", + "CMT_TOP_WW4END1_1", + "CMT_TOP_NW4A2_11", + "CMT_TOP_IMUX37_0", + "CMT_TOP_SW2A0_12", + "CMT_TOP_WL1END3_1", + "CMT_TOP_IMUX16_8", + "CMT_TOP_IMUX39_2", + "CMT_TOP_IMUX37_7", + "CMT_TOP_IMUX16_3", + "CMT_TOP_IMUX1_2", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_TOP_IMUX6_6", + "CMT_TOP_LH1_12", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_WW4B2_4", + "CMT_TOP_ER1BEG2_2", + "CMT_TOP_IMUX11_10", + "CMT_TOP_IMUX17_7", + "CMT_TOP_CTRL0_8", + "CMT_TOP_IMUX35_9", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_IMUX29_2", + "CMT_TOP_BYP6_1", + "CMT_TOP_ER1BEG0_9", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_FAN1_4", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW2A0_5", + "CMT_TOP_NE2A1_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_TOP_NW2A0_3", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_SE2A1_5", + "CMT_TOP_LH4_9", + "CMT_TOP_NW4A1_8", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_NW4END3_2", + "CMT_TOP_IMUX39_3", + "CMT_TOP_IMUX7_12", + "CMT_TOP_CTRL0_2", + "CMT_TOP_SW4END1_10", + "CMT_TOP_NW4END0_7", + "CMT_TOP_IMUX44_9", + "CMT_TOP_SW4END0_4", + "CMT_TOP_CTRL1_2", + "CMT_TOP_WW4END2_2", + "CMT_TOP_IMUX38_10", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4C2_10", + "CMT_TOP_IMUX38_2", + "CMT_TOP_BYP3_7", + "CMT_TOP_LH3_0", + "CMT_TOP_EE4BEG3_9", + "CMT_TOP_EE4A2_12", + "CMT_TOP_NE4BEG2_6", + "CMT_TOP_ICLK_11", + "CMT_TOP_OCLK_3", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX13_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", + "CMT_TOP_IMUX11_2", + "CMT_TOP_WW4A2_10", + "CMT_TOP_SW4A0_5", + "CMT_TOP_EE4B2_3", + "CMT_TOP_IMUX9_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", + "CMT_TOP_EE2A2_3", + "CMT_TOP_WR1END3_1", + "CMT_TOP_WW2A0_0", + "CMT_TOP_WR1END0_5", + "CMT_TOP_ER1BEG2_8", + "CMT_TOP_WW4C3_10", + "CMT_TOP_NW4A0_8", + "CMT_TOP_BYP7_12", + "CMT_TOP_LOGIC_OUTS_L_B6_9", + "CMT_TOP_EE4C0_10", + "CMT_TOP_WW4B2_5", + "CMT_TOP_SW2A2_12", + "CMT_TOP_IMUX41_8", + "CMT_TOP_SW2A3_8", + "CMT_TOP_SW4END1_9", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_LH4_10", + "CMT_TOP_NE4BEG0_11", + "CMT_TOP_WW4B3_6", + "CMT_TOP_NW4END3_10", + "CMT_TOP_WW4END3_8", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX33_2", + "CMT_TOP_WW2END2_8", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_WW4C0_11", + "CMT_TOP_NE2A0_7", + "CMT_TOP_SE2A0_10", + "CMT_TOP_NW2A0_12", + "CMT_TOP_BYP0_7", + "CMT_TOP_IMUX0_11", + "CMT_TOP_IMUX21_12", + "CMT_TOP_NE2A1_7", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_TOP_IMUX3_12", + "CMT_TOP_WW2A3_10", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_NW4A3_8", + "CMT_TOP_EE4A1_11", + "CMT_TOP_WW4C0_5", + "CMT_TOP_BYP4_9", + "CMT_TOP_IMUX8_7", + "CMT_TOP_NE2A0_1", + "CMT_TOP_WW4END0_0", + "CMT_TOP_FAN5_2", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_WW4C1_10", + "CMT_TOP_IMUX39_8", + "CMT_TOP_NE4C1_2", + "CMT_TOP_IMUX30_4", + "CMT_TOP_WL1END0_12", + "CMT_TOP_NE2A3_12", + "PLL_CLK_FREQ_BB1_NS", + "CMT_TOP_EE4C3_4", + "CMT_TOP_BYP1_5", + "CMT_TOP_IMUX20_12", + "CMT_TOP_IMUX10_8", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_TOP_WW4B2_12", + "CMT_TOP_NE2A2_11", + "CMT_TOP_EE4A3_11", + "CMT_TOP_IMUX43_10", + "CMT_TOP_EE2A2_10", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_IMUX44_8", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_WL1END0_3", + "CMT_PLL_PHASER_OUT_D_OCLK1X_90", + "CMT_TOP_IMUX18_8", + "CMT_TOP_IMUX19_4", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_NE4C2_10", + "CMT_TOP_NW4END3_12", + "CMT_TOP_LH10_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", + "CMT_TOP_LOGIC_OUTS_L_B10_9", + "CMT_TOP_LH7_4", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_NW4A3_5", + "CMT_TOP_L_UPPER_T_FREQ_BB3", + "CMT_PLL_PHYCTRL_SYNC_BB_UP", + "CMT_TOP_LOGIC_OUTS_L_B9_12", + "CMT_TOP_NW4END0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_12", + "CMT_TOP_IMUX29_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", + "CMT_TOP_NW2A0_6", + "CMT_TOP_BLOCK_OUTS_L_B1_12", + "CMT_TOP_SE2A2_2", + "CMT_TOP_WW4C2_7", + "CMT_TOP_IMUX37_9", + "CMT_TOP_WW4C0_4", + "CMT_TOP_BYP5_9", + "CMT_TOP_EE4BEG3_4", + "CMT_TOP_WW4A2_1", + "CMT_TOP_LH6_9", + "CMT_TOP_BYP5_12", + "CMT_TOP_SE4C2_11", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", + "CMT_TOP_LH10_3", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_WW4C3_2", + "CMT_TOP_IMUX38_5", + "CMT_TOP_IMUX8_8", + "CMT_TOP_FAN4_6", + "CMT_TOP_IMUX47_7", + "CMT_TOP_EE2A1_1", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_ER1BEG1_10", + "CMT_TOP_FAN7_8", + "CMT_TOP_FAN6_3", + "CMT_TOP_EE4B0_0", + "CMT_TOP_IMUX34_5", + "CMT_TOP_IMUX31_5", + "CMT_TOP_WW4END1_11", + "CMT_TOP_IMUX0_7", + "CMT_TOP_IMUX2_1", + "CMT_TOP_ER1BEG3_8" + ], + "pips": { + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX0_11->>CMT_TOP_R_UPPER_T_PLLE2_PWRDWN": { + "src_wire": "CMT_TOP_IMUX0_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX7_12->>CMT_TOP_R_UPPER_T_PLLE2_DI1": { + "src_wire": "CMT_TOP_IMUX7_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX35_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR5": { + "src_wire": "CMT_TOP_IMUX35_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO0->>CMT_TOP_LOGIC_OUTS_L_B17_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS->>CMT_TOP_L_UPPER_T_FREQ_BB2": { + "src_wire": "PLL_CLK_FREQ_BB2_NS", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_9": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_12": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX37_12->>CMT_TOP_R_UPPER_T_PLLE2_DI4": { + "src_wire": "CMT_TOP_IMUX37_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_12": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX34_12->>CMT_TOP_R_UPPER_T_PLLE2_DI10": { + "src_wire": "CMT_TOP_IMUX34_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO6->>CMT_TOP_LOGIC_OUTS_L_B16_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO6", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_IN_D_ICLKDIV->>CMT_PHASER_D_ICLKDIV_TOIOI": { + "src_wire": "CMT_PLL_PHASER_IN_D_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3->>CMT_TOP_L_UPPER_T_CLKPLL3": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "src_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_9": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0->>PLLOUT_CLK_FREQ_BB_0": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0->>CMT_TOP_L_UPPER_T_CLKPLL0": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX1_12->>CMT_TOP_R_UPPER_T_PLLE2_DI13": { + "src_wire": "CMT_TOP_IMUX1_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_11": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS->>CMT_TOP_L_UPPER_T_FREQ_BB3": { + "src_wire": "PLL_CLK_FREQ_BB3_NS", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX0_12->>CMT_TOP_R_UPPER_T_PLLE2_DI15": { + "src_wire": "CMT_TOP_IMUX0_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO11->>CMT_TOP_LOGIC_OUTS_L_B13_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B13_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { + "src_wire": "CMT_PLL_PHASERD_DQSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_11": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLK1X_90->>CMT_PHASER_D_OCLK90_TOIOI": { + "src_wire": "CMT_PLL_PHASER_OUT_D_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_OCLK90_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1->>PLLOUT_CLK_FREQ_BB_1": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT->>CMT_TOP_L_UPPER_T_CLKPLL6": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS->>CMT_TOP_L_UPPER_T_FREQ_BB1": { + "src_wire": "PLL_CLK_FREQ_BB1_NS", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4->>CMT_TOP_L_UPPER_T_CLKPLL4": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO8->>CMT_TOP_LOGIC_OUTS_L_B19_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO8", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX22_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR2": { + "src_wire": "CMT_TOP_IMUX22_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { + "src_wire": "CMT_PLL_PHASERD_DTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B21_11": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO10->>CMT_TOP_LOGIC_OUTS_L_B23_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO10", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { + "src_wire": "CMT_PLL_PHASERD_DQSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKFBIN->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_L_UPPER_T_CLKFBIN", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { + "src_wire": "CMT_PLL_PHASERD_DTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS0": { + "src_wire": "PLL_CLK_FREQ_BB0_NS", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS0", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX4_12->>CMT_TOP_R_UPPER_T_PLLE2_DI7": { + "src_wire": "CMT_TOP_IMUX4_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX39_12->>CMT_TOP_R_UPPER_T_PLLE2_DI0": { + "src_wire": "CMT_TOP_IMUX39_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX47_10->>CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL": { + "src_wire": "CMT_TOP_IMUX47_10", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_10": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO2->>CMT_TOP_LOGIC_OUTS_L_B21_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO7->>CMT_TOP_LOGIC_OUTS_L_B10_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO7", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX5_12->>CMT_TOP_R_UPPER_T_PLLE2_DI5": { + "src_wire": "CMT_TOP_IMUX5_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS2": { + "src_wire": "PLL_CLK_FREQ_BB2_NS", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS2", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_12": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX2_11->>CMT_TOP_R_UPPER_T_PLLE2_DWE": { + "src_wire": "CMT_TOP_IMUX2_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DWE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX38_12->>CMT_TOP_R_UPPER_T_PLLE2_DI2": { + "src_wire": "CMT_TOP_IMUX38_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO1->>CMT_TOP_LOGIC_OUTS_L_B7_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1->>CMT_TOP_L_UPPER_T_CLKPLL1": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5->>CMT_TOP_L_UPPER_T_CLKPLL5": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3->>PLLOUT_CLK_FREQ_BB_3": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX2_12->>CMT_TOP_R_UPPER_T_PLLE2_DI11": { + "src_wire": "CMT_TOP_IMUX2_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO12->>CMT_TOP_LOGIC_OUTS_L_B22_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B22_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLKDIV->>CMT_PHASER_D_OCLKDIV_TOIOI": { + "src_wire": "CMT_PLL_PHASER_OUT_D_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_CLK0_12->>CMT_TOP_R_UPPER_T_PLLE2_DCLK": { + "src_wire": "CMT_TOP_CLK0_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_12": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX1_11->>CMT_TOP_R_UPPER_T_PLLE2_DEN": { + "src_wire": "CMT_TOP_IMUX1_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO15->>CMT_TOP_LOGIC_OUTS_L_B8_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO15", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B8_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX13_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR3": { + "src_wire": "CMT_TOP_IMUX13_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_DN<<->>CMT_PLL_PHYCTRL_SYNC_BB_UP": { + "src_wire": "CMT_PLL_PHYCTRL_SYNC_BB_DN", + "is_pseudo": "0", + "dst_wire": "CMT_PLL_PHYCTRL_SYNC_BB_UP", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX32_12->>CMT_TOP_R_UPPER_T_PLLE2_DI14": { + "src_wire": "CMT_TOP_IMUX32_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO14->>CMT_TOP_LOGIC_OUTS_L_B18_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO14", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX6_12->>CMT_TOP_R_UPPER_T_PLLE2_DI3": { + "src_wire": "CMT_TOP_IMUX6_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS1": { + "src_wire": "PLL_CLK_FREQ_BB1_NS", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS1", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "src_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO5->>CMT_TOP_LOGIC_OUTS_L_B2_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX13_10->>CMT_TOP_R_UPPER_T_PLLE2_RST": { + "src_wire": "CMT_TOP_IMUX13_10", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_10": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS->>CMT_TOP_L_UPPER_T_FREQ_BB0": { + "src_wire": "PLL_CLK_FREQ_BB0_NS", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX15_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR1": { + "src_wire": "CMT_TOP_IMUX15_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX36_12->>CMT_TOP_R_UPPER_T_PLLE2_DI6": { + "src_wire": "CMT_TOP_IMUX36_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO4->>CMT_TOP_LOGIC_OUTS_L_B20_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS3": { + "src_wire": "PLL_CLK_FREQ_BB3_NS", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS3", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_IN_D_ICLK->>CMT_PHASER_D_ICLK_TOIOI": { + "src_wire": "CMT_PLL_PHASER_IN_D_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX47_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR0": { + "src_wire": "CMT_TOP_IMUX47_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2->>CMT_TOP_L_UPPER_T_CLKPLL2": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT->CMT_TOP_L_CLKFBOUT2IN": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_CLKFBOUT2IN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO13->>CMT_TOP_LOGIC_OUTS_L_B0_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO13", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_CLK1_0->>CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT": { + "src_wire": "CMT_TOP_CLK1_0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_CLKFBOUT2IN->CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_L_CLKFBOUT2IN", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT->>CMT_TOP_L_UPPER_T_CLKPLL7": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX35_12->>CMT_TOP_R_UPPER_T_PLLE2_DI8": { + "src_wire": "CMT_TOP_IMUX35_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX44_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR4": { + "src_wire": "CMT_TOP_IMUX44_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_7": { + "src_wire": "CMT_PHASER_D_OCLK90_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX33_12->>CMT_TOP_R_UPPER_T_PLLE2_DI12": { + "src_wire": "CMT_TOP_IMUX33_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX3_12->>CMT_TOP_R_UPPER_T_PLLE2_DI9": { + "src_wire": "CMT_TOP_IMUX3_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKIN1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "src_wire": "CMT_TOP_L_UPPER_T_CLKIN1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO9->>CMT_TOP_LOGIC_OUTS_L_B5_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO9", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLK->>CMT_PHASER_D_OCLK_TOIOI": { + "src_wire": "CMT_PLL_PHASER_OUT_D_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX3_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR6": { + "src_wire": "CMT_TOP_IMUX3_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_CLK0_1->>CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT": { + "src_wire": "CMT_TOP_CLK0_1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { + "src_wire": "CMT_PLL_PHASERD_CTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_11": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "src_wire": "CMT_PLL_PHASERD_CTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO3->>CMT_TOP_LOGIC_OUTS_L_B15_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2->>PLLOUT_CLK_FREQ_BB_2": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_CLK0_0->>CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT": { + "src_wire": "CMT_TOP_CLK0_0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKIN2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "src_wire": "CMT_TOP_L_UPPER_T_CLKIN2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CMT_TOP_R_LOWER_B.json b/kintex7/tile_type_CMT_TOP_R_LOWER_B.json new file mode 100644 index 0000000..a3e2990 --- /dev/null +++ b/kintex7/tile_type_CMT_TOP_R_LOWER_B.json @@ -0,0 +1,5450 @@ +{ + "tile_type": "CMT_TOP_R_LOWER_B", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "MMCME2_ADV", + "type": "MMCME2_ADV", + "site_pins": { + "TESTIN23": "CMT_LR_LOWER_B_MMCM_TESTIN23", + "TESTIN25": "CMT_LR_LOWER_B_MMCM_TESTIN25", + "LOCKED": "CMT_LR_LOWER_B_MMCM_LOCKED", + "DEN": "CMT_LR_LOWER_B_MMCM_DEN", + "TESTIN16": "CMT_LR_LOWER_B_MMCM_TESTIN16", + "TESTIN6": "CMT_LR_LOWER_B_MMCM_TESTIN6", + "TESTOUT0": "CMT_LR_LOWER_B_MMCM_TESTOUT0", + "TESTOUT9": "CMT_LR_LOWER_B_MMCM_TESTOUT9", + "TESTOUT28": "CMT_LR_LOWER_B_MMCM_TESTOUT28", + "TESTIN27": "CMT_LR_LOWER_B_MMCM_TESTIN27", + "TESTOUT24": "CMT_LR_LOWER_B_MMCM_TESTOUT24", + "CLKOUT0": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "TESTIN17": "CMT_LR_LOWER_B_MMCM_TESTIN17", + "TESTOUT12": "CMT_LR_LOWER_B_MMCM_TESTOUT12", + "DI15": "CMT_LR_LOWER_B_MMCM_DI15", + "TESTOUT2": "CMT_LR_LOWER_B_MMCM_TESTOUT2", + "TESTIN13": "CMT_LR_LOWER_B_MMCM_TESTIN13", + "DI12": "CMT_LR_LOWER_B_MMCM_DI12", + "DO15": "CMT_LR_LOWER_B_MMCM_DO15", + "TESTOUT59": "CMT_LR_LOWER_B_MMCM_TESTOUT59", + "PSDONE": "CMT_LR_LOWER_B_MMCM_PSDONE", + "DI2": "CMT_LR_LOWER_B_MMCM_DI2", + "TESTOUT38": "CMT_LR_LOWER_B_MMCM_TESTOUT38", + "TESTIN29": "CMT_LR_LOWER_B_MMCM_TESTIN29", + "CLKFBOUT": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "TESTOUT8": "CMT_LR_LOWER_B_MMCM_TESTOUT8", + "DI11": "CMT_LR_LOWER_B_MMCM_DI11", + "TESTIN14": "CMT_LR_LOWER_B_MMCM_TESTIN14", + "TESTOUT11": "CMT_LR_LOWER_B_MMCM_TESTOUT11", + "TESTOUT25": "CMT_LR_LOWER_B_MMCM_TESTOUT25", + "TESTOUT56": "CMT_LR_LOWER_B_MMCM_TESTOUT56", + "CLKIN2": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "PSEN": "CMT_LR_LOWER_B_MMCM_PSEN", + "CLKOUT3B": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", + "DO10": "CMT_LR_LOWER_B_MMCM_DO10", + "TESTOUT6": "CMT_LR_LOWER_B_MMCM_TESTOUT6", + "DO11": "CMT_LR_LOWER_B_MMCM_DO11", + "DO0": "CMT_LR_LOWER_B_MMCM_DO0", + "TESTOUT27": "CMT_LR_LOWER_B_MMCM_TESTOUT27", + "DI6": "CMT_LR_LOWER_B_MMCM_DI6", + "CLKOUT5": "CMT_LR_LOWER_B_MMCM_CLKOUT5", + "DI8": "CMT_LR_LOWER_B_MMCM_DI8", + "DADDR0": "CMT_LR_LOWER_B_MMCM_DADDR0", + "TESTOUT5": "CMT_LR_LOWER_B_MMCM_TESTOUT5", + "TMUXOUT": "CMT_LR_LOWER_B_MMCM_TMUXOUT", + "DI3": "CMT_LR_LOWER_B_MMCM_DI3", + "TESTOUT30": "CMT_LR_LOWER_B_MMCM_TESTOUT30", + "TESTOUT4": "CMT_LR_LOWER_B_MMCM_TESTOUT4", + "TESTIN31": "CMT_LR_LOWER_B_MMCM_TESTIN31", + "TESTOUT34": "CMT_LR_LOWER_B_MMCM_TESTOUT34", + "DADDR3": "CMT_LR_LOWER_B_MMCM_DADDR3", + "PWRDWN": "CMT_LR_LOWER_B_MMCM_PWRDWN", + "TESTOUT14": "CMT_LR_LOWER_B_MMCM_TESTOUT14", + "TESTIN9": "CMT_LR_LOWER_B_MMCM_TESTIN9", + "TESTOUT63": "CMT_LR_LOWER_B_MMCM_TESTOUT63", + "DO1": "CMT_LR_LOWER_B_MMCM_DO1", + "TESTOUT15": "CMT_LR_LOWER_B_MMCM_TESTOUT15", + "TESTOUT23": "CMT_LR_LOWER_B_MMCM_TESTOUT23", + "TESTOUT61": "CMT_LR_LOWER_B_MMCM_TESTOUT61", + "DI0": "CMT_LR_LOWER_B_MMCM_DI0", + "CLKOUT4": "CMT_LR_LOWER_B_MMCM_CLKOUT4", + "DI9": "CMT_LR_LOWER_B_MMCM_DI9", + "TESTOUT43": "CMT_LR_LOWER_B_MMCM_TESTOUT43", + "CLKOUT2": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "TESTOUT60": "CMT_LR_LOWER_B_MMCM_TESTOUT60", + "DO5": "CMT_LR_LOWER_B_MMCM_DO5", + "DO4": "CMT_LR_LOWER_B_MMCM_DO4", + "TESTOUT18": "CMT_LR_LOWER_B_MMCM_TESTOUT18", + "TESTOUT29": "CMT_LR_LOWER_B_MMCM_TESTOUT29", + "TESTOUT26": "CMT_LR_LOWER_B_MMCM_TESTOUT26", + "CLKOUT0B": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", + "DO8": "CMT_LR_LOWER_B_MMCM_DO8", + "DADDR6": "CMT_LR_LOWER_B_MMCM_DADDR6", + "TESTIN30": "CMT_LR_LOWER_B_MMCM_TESTIN30", + "TESTOUT32": "CMT_LR_LOWER_B_MMCM_TESTOUT32", + "TESTIN18": "CMT_LR_LOWER_B_MMCM_TESTIN18", + "TESTOUT54": "CMT_LR_LOWER_B_MMCM_TESTOUT54", + "DADDR1": "CMT_LR_LOWER_B_MMCM_DADDR1", + "TESTOUT46": "CMT_LR_LOWER_B_MMCM_TESTOUT46", + "DADDR2": "CMT_LR_LOWER_B_MMCM_DADDR2", + "CLKINSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", + "TESTIN7": "CMT_LR_LOWER_B_MMCM_TESTIN7", + "RST": "CMT_LR_LOWER_B_MMCM_RST", + "TESTIN8": "CMT_LR_LOWER_B_MMCM_TESTIN8", + "TESTOUT48": "CMT_LR_LOWER_B_MMCM_TESTOUT48", + "DRDY": "CMT_LR_LOWER_B_MMCM_DRDY", + "DWE": "CMT_LR_LOWER_B_MMCM_DWE", + "CLKOUT1": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "TESTIN3": "CMT_LR_LOWER_B_MMCM_TESTIN3", + "DI14": "CMT_LR_LOWER_B_MMCM_DI14", + "TESTOUT49": "CMT_LR_LOWER_B_MMCM_TESTOUT49", + "TESTIN26": "CMT_LR_LOWER_B_MMCM_TESTIN26", + "TESTOUT52": "CMT_LR_LOWER_B_MMCM_TESTOUT52", + "TESTOUT50": "CMT_LR_LOWER_B_MMCM_TESTOUT50", + "TESTOUT20": "CMT_LR_LOWER_B_MMCM_TESTOUT20", + "TESTIN15": "CMT_LR_LOWER_B_MMCM_TESTIN15", + "TESTIN19": "CMT_LR_LOWER_B_MMCM_TESTIN19", + "TESTIN4": "CMT_LR_LOWER_B_MMCM_TESTIN4", + "DADDR5": "CMT_LR_LOWER_B_MMCM_DADDR5", + "TESTIN11": "CMT_LR_LOWER_B_MMCM_TESTIN11", + "TESTIN1": "CMT_LR_LOWER_B_MMCM_TESTIN1", + "TESTIN20": "CMT_LR_LOWER_B_MMCM_TESTIN20", + "DI4": "CMT_LR_LOWER_B_MMCM_DI4", + "DO9": "CMT_LR_LOWER_B_MMCM_DO9", + "TESTOUT17": "CMT_LR_LOWER_B_MMCM_TESTOUT17", + "TESTOUT21": "CMT_LR_LOWER_B_MMCM_TESTOUT21", + "TESTOUT10": "CMT_LR_LOWER_B_MMCM_TESTOUT10", + "TESTIN28": "CMT_LR_LOWER_B_MMCM_TESTIN28", + "CLKOUT1B": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", + "CLKOUT2B": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", + "TESTOUT53": "CMT_LR_LOWER_B_MMCM_TESTOUT53", + "TESTOUT55": "CMT_LR_LOWER_B_MMCM_TESTOUT55", + "TESTOUT19": "CMT_LR_LOWER_B_MMCM_TESTOUT19", + "CLKIN1": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "TESTIN10": "CMT_LR_LOWER_B_MMCM_TESTIN10", + "TESTOUT22": "CMT_LR_LOWER_B_MMCM_TESTOUT22", + "DCLK": "CMT_LR_LOWER_B_MMCM_DCLK", + "DI7": "CMT_LR_LOWER_B_MMCM_DI7", + "TESTOUT57": "CMT_LR_LOWER_B_MMCM_TESTOUT57", + "PSCLK": "CMT_LR_LOWER_B_MMCM_PSCLK", + "TESTOUT44": "CMT_LR_LOWER_B_MMCM_TESTOUT44", + "CLKINSEL": "CMT_LR_LOWER_B_MMCM_CLKINSEL", + "CLKFBIN": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "DO6": "CMT_LR_LOWER_B_MMCM_DO6", + "TESTOUT45": "CMT_LR_LOWER_B_MMCM_TESTOUT45", + "TESTIN2": "CMT_LR_LOWER_B_MMCM_TESTIN2", + "TESTOUT51": "CMT_LR_LOWER_B_MMCM_TESTOUT51", + "TESTOUT40": "CMT_LR_LOWER_B_MMCM_TESTOUT40", + "TESTIN24": "CMT_LR_LOWER_B_MMCM_TESTIN24", + "TESTOUT58": "CMT_LR_LOWER_B_MMCM_TESTOUT58", + "TESTOUT16": "CMT_LR_LOWER_B_MMCM_TESTOUT16", + "DO14": "CMT_LR_LOWER_B_MMCM_DO14", + "DO12": "CMT_LR_LOWER_B_MMCM_DO12", + "DI13": "CMT_LR_LOWER_B_MMCM_DI13", + "TESTOUT41": "CMT_LR_LOWER_B_MMCM_TESTOUT41", + "DO13": "CMT_LR_LOWER_B_MMCM_DO13", + "CLKOUT6": "CMT_LR_LOWER_B_MMCM_CLKOUT6", + "CLKOUT3": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "PSINCDEC": "CMT_LR_LOWER_B_MMCM_PSINCDEC", + "DO3": "CMT_LR_LOWER_B_MMCM_DO3", + "CLKFBSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", + "DI1": "CMT_LR_LOWER_B_MMCM_DI1", + "TESTOUT42": "CMT_LR_LOWER_B_MMCM_TESTOUT42", + "TESTOUT47": "CMT_LR_LOWER_B_MMCM_TESTOUT47", + "CLKFBOUTB": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", + "TESTIN5": "CMT_LR_LOWER_B_MMCM_TESTIN5", + "TESTIN22": "CMT_LR_LOWER_B_MMCM_TESTIN22", + "TESTOUT3": "CMT_LR_LOWER_B_MMCM_TESTOUT3", + "TESTOUT36": "CMT_LR_LOWER_B_MMCM_TESTOUT36", + "TESTIN0": "CMT_LR_LOWER_B_MMCM_TESTIN0", + "TESTOUT7": "CMT_LR_LOWER_B_MMCM_TESTOUT7", + "TESTOUT33": "CMT_LR_LOWER_B_MMCM_TESTOUT33", + "DADDR4": "CMT_LR_LOWER_B_MMCM_DADDR4", + "DO2": "CMT_LR_LOWER_B_MMCM_DO2", + "TESTOUT13": "CMT_LR_LOWER_B_MMCM_TESTOUT13", + "DO7": "CMT_LR_LOWER_B_MMCM_DO7", + "DI10": "CMT_LR_LOWER_B_MMCM_DI10", + "TESTOUT1": "CMT_LR_LOWER_B_MMCM_TESTOUT1", + "TESTIN12": "CMT_LR_LOWER_B_MMCM_TESTIN12", + "TESTOUT37": "CMT_LR_LOWER_B_MMCM_TESTOUT37", + "DI5": "CMT_LR_LOWER_B_MMCM_DI5", + "TESTOUT62": "CMT_LR_LOWER_B_MMCM_TESTOUT62", + "TESTIN21": "CMT_LR_LOWER_B_MMCM_TESTIN21", + "TESTOUT31": "CMT_LR_LOWER_B_MMCM_TESTOUT31", + "TESTOUT39": "CMT_LR_LOWER_B_MMCM_TESTOUT39", + "TESTOUT35": "CMT_LR_LOWER_B_MMCM_TESTOUT35" + }, + "x_coord": 0 + } + ], + "wires": [ + "CMT_TOP_WR1END2_7", + "CMT_TOP_WW4A1_15", + "CMT_TOP_WW4C3_6", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_IMUX18_1", + "CMT_TOP_WL1END3_8", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX8_5", + "CMT_TOP_WW2END3_7", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_EE4B0_9", + "CMT_TOP_IMUX15_8", + "CMT_TOP_LH5_7", + "CMT_TOP_LOGIC_OUTS_L_B12_11", + "CMT_TOP_EE2A0_15", + "CMT_TOP_SE4C2_0", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_FAN2_3", + "CMT_TOP_IMUX40_8", + "CMT_TOP_EE4C2_7", + "CMT_TOP_SE4BEG0_10", + "CMT_TOP_NW2A1_4", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_EE2A1_6", + "CMT_TOP_EE4A2_4", + "CMT_TOP_BYP1_4", + "CMT_TOP_EE4C0_3", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_SE4BEG1_14", + "CMT_TOP_SE4C1_4", + "CMT_TOP_IMUX28_14", + "CMT_TOP_IMUX23_5", + "CMT_TOP_BYP6_12", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_IMUX34_7", + "CMT_TOP_ER1BEG2_13", + "CMT_TOP_SW2A3_14", + "CMT_TOP_IMUX25_10", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN5_3", + "CMT_TOP_NE4C2_2", + "CMT_TOP_EE4A2_5", + "CMT_TOP_IMUX35_5", + "CMT_TOP_EE2A0_1", + "CMT_TOP_SE4BEG3_10", + "CMT_TOP_IMUX40_12", + "CMT_TOP_FAN3_2", + "CMT_TOP_BYP2_11", + "CMT_TOP_EE2A2_1", + "CMT_TOP_SW4END2_10", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE2A2_5", + "CMT_TOP_WW2END0_3", + "CMT_TOP_SW4END3_9", + "CMT_TOP_ER1BEG3_15", + "CMT_TOP_IMUX16_11", + "CMT_TOP_IMUX28_13", + "CMT_TOP_ER1BEG1_0", + "CMT_TOP_SE2A2_10", + "CMT_TOP_WW4C2_14", + "CMT_TOP_SE4C0_2", + "CMT_TOP_EE4BEG3_14", + "CMT_TOP_EE4B3_8", + "CMT_TOP_NW4A3_9", + "CMT_TOP_EE4A1_2", + "CMT_TOP_IMUX31_4", + "CMT_TOP_NW4A3_12", + "CMT_TOP_EL1BEG3_5", + "CMT_TOP_IMUX12_15", + "CMT_TOP_SE4C3_11", + "CMT_TOP_NW4A3_4", + "CMT_TOP_WW4END1_2", + "CMT_TOP_WW4B1_5", + "CMT_TOP_LOGIC_OUTS_L_B2_9", + "CMT_TOP_IMUX12_5", + "CMT_LR_LOWER_B_MMCM_TESTIN14", + "CMT_TOP_EE2BEG1_14", + "CMT_TOP_IMUX8_10", + "CMT_TOP_NW4A1_12", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_EE4A0_6", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_WW4B3_14", + "CMT_TOP_NE4C3_9", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_SE4BEG2_15", + "CMT_TOP_SW2A0_11", + "CMT_TOP_WR1END0_2", + "CMT_TOP_SW4A0_12", + "CMT_TOP_NW4END1_8", + "CMT_TOP_SE2A0_8", + "CMT_TOP_LH11_2", + "CMT_TOP_WR1END3_15", + "CMT_TOP_IMUX26_14", + "CMT_MMCM_PHASERA_CTSBUS0", + "CMT_TOP_EE4C3_2", + "CMT_TOP_IMUX2_7", + "CMT_TOP_LOGIC_OUTS_L_B7_11", + "CMT_TOP_EE2A1_7", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_ER1BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX16_6", + "CMT_TOP_LH6_2", + "CMT_TOP_NE4BEG1_9", + "CMT_LR_LOWER_B_MMCM_TESTOUT16", + "CMT_TOP_WW4END2_14", + "CMT_TOP_IMUX9_2", + "CMT_TOP_BYP5_1", + "CMT_TOP_OCLKDIV_12", + "CMT_TOP_WR1END1_7", + "CMT_TOP_WL1END1_1", + "CMT_TOP_EE2A3_11", + "CMT_TOP_IMUX11_15", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_EE4A0_11", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX23_8", + "CMT_TOP_IMUX11_12", + "CMT_LR_LOWER_B_MMCM_DADDR3", + "CMT_TOP_LOGIC_OUTS_L_B19_9", + "CMT_TOP_EE4C3_11", + "CMT_TOP_SW4END2_11", + "CMT_TOP_EE4C3_15", + "CMT_TOP_LOGIC_OUTS_L_B19_13", + "CMT_LR_LOWER_B_MMCM_CLKINSEL", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_WW4B1_11", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_IMUX1_14", + "CMT_TOP_WW4A2_11", + "CMT_TOP_NW4END3_0", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_SE4BEG0_6", + "CMT_TOP_IMUX7_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_SE4C2_12", + "CMT_TOP_SW2A3_2", + "CMT_TOP_WW4C1_4", + "CMT_TOP_NE2A2_5", + "CMT_TOP_SE4C3_9", + "CMT_TOP_IMUX9_12", + "CMT_TOP_IMUX3_7", + "CMT_TOP_WW4A0_8", + "CMT_TOP_NW4END0_5", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_TOP_FAN5_1", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_LH4_15", + "CMT_TOP_SE4BEG2_10", + "CMT_TOP_IMUX9_9", + "CMT_TOP_EE2A2_12", + "CMT_TOP_SE4BEG3_13", + "CMT_LR_LOWER_B_MMCM_TESTOUT51", + "CMT_TOP_IMUX31_9", + "CMT_TOP_FAN1_6", + "CMT_TOP_IMUX26_4", + "CMT_TOP_LH2_13", + "CMT_TOP_IMUX31_12", + "CMT_TOP_IMUX3_2", + "CMT_TOP_LH9_11", + "CMT_TOP_IMUX12_14", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_LH4_2", + "CMT_TOP_EE4BEG2_14", + "CMT_TOP_EE4A1_8", + "MMCM_CLK_FREQ_BB_NS0", + "CMT_TOP_WW4END1_7", + "CMT_TOP_SW4A3_15", + "CMT_TOP_IMUX35_10", + "CMT_TOP_NE4C3_15", + "CMT_TOP_IMUX44_5", + "CMT_R_LOWER_B_CLK_MMCM7", + "CMT_TOP_NW2A3_15", + "CMT_TOP_IMUX37_4", + "CMT_TOP_WW4C2_8", + "CMT_TOP_NW4A0_12", + "CMT_TOP_EE4A0_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT39", + "CMT_TOP_FAN1_12", + "CMT_TOP_WW4B3_1", + "CMT_TOP_IMUX29_14", + "CMT_TOP_NW2A0_14", + "CMT_TOP_LOGIC_OUTS_L_B12_15", + "CMT_TOP_EE4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_TOP_IMUX26_13", + "CMT_TOP_SW4END1_15", + "CMT_TOP_IMUX23_12", + "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "CMT_TOP_LOGIC_OUTS_L_B15_9", + "CMT_TOP_NE4BEG2_11", + "CMT_TOP_EE2BEG1_12", + "CMT_TOP_IMUX6_12", + "CMT_TOP_WW2END1_0", + "CMT_TOP_IMUX22_9", + "CMT_TOP_FAN3_11", + "CMT_TOP_SE2A1_14", + "CMT_TOP_IMUX13_3", + "CMT_TOP_WW4END1_4", + "CMT_TOP_IMUX14_11", + "CMT_TOP_EE4BEG0_9", + "CMT_TOP_WR1END0_10", + "CMT_TOP_IMUX16_13", + "CMT_TOP_LOGIC_OUTS_L_B0_12", + "CMT_TOP_EE4C1_5", + "CMT_TOP_LH9_1", + "CMT_TOP_WL1END0_13", + "CMT_TOP_SE4BEG0_14", + "CMT_TOP_LOGIC_OUTS_L_B0_14", + "CMT_TOP_LH11_10", + "CMT_TOP_FAN6_12", + "CMT_TOP_SE2A1_3", + "CMT_TOP_BYP1_13", + "CMT_LR_LOWER_B_MMCM_TESTOUT49", + "CMT_TOP_SE2A0_1", + "CMT_TOP_SE4C0_10", + "CMT_TOP_LH12_3", + "CMT_TOP_CLK1_12", + "CMT_TOP_ER1BEG3_11", + "CMT_TOP_FAN7_4", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END2_5", + "CMT_TOP_EE4B2_12", + "CMT_TOP_LOGIC_OUTS_L_B6_15", + "CMT_TOP_WR1END2_9", + "CMT_TOP_FAN1_0", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_IMUX40_7", + "CMT_TOP_BYP7_8", + "CMT_TOP_NW4A3_0", + "CMT_TOP_WL1END2_4", + "CMT_TOP_IMUX0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_SW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_EE2A3_3", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW2A0_2", + "CMT_TOP_SW4END1_2", + "CMT_TOP_EE2A3_5", + "CMT_TOP_WR1END0_1", + "CMT_TOP_LOGIC_OUTS_L_B4_15", + "CMT_TOP_WW4C1_3", + "CMT_TOP_LH4_3", + "CMT_TOP_EE4B2_8", + "CMT_TOP_IMUX7_15", + "CMT_TOP_CLK0_13", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_WL1END3_15", + "CMT_TOP_IMUX5_2", + "CMT_TOP_EE2BEG1_6", + "CMT_TOP_EE4BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_NE2A2_2", + "CMT_LR_LOWER_B_MMCM_DO4", + "CMT_TOP_IMUX2_12", + "CMT_TOP_NW4A0_6", + "CMT_TOP_WL1END3_12", + "CMT_TOP_FAN4_14", + "CMT_TOP_EE2A1_10", + "CMT_TOP_EE4A3_5", + "CMT_TOP_LOGIC_OUTS_L_B8_10", + "CMT_TOP_IMUX14_0", + "CMT_TOP_LH7_5", + "CMT_PHASER_A_ICLK_TOIOI", + "CMT_TOP_WW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_TOP_WW2END2_3", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WW2END3_8", + "CMT_TOP_NW4END1_0", + "CMT_TOP_IMUX30_13", + "CMT_LR_LOWER_B_MMCM_DWE", + "CMT_TOP_NE4C2_5", + "CMT_TOP_SE2A2_11", + "CMT_TOP_IMUX14_4", + "CMT_TOP_IMUX12_4", + "CMT_TOP_SW4END3_2", + "CMT_TOP_IMUX32_0", + "CMT_TOP_SW4END3_12", + "CMT_TOP_SE4BEG0_1", + "CMT_TOP_OCLKDIV_15", + "CMT_TOP_NW2A2_15", + "CMT_TOP_LH8_14", + "CMT_TOP_NE4C1_13", + "CMT_TOP_IMUX44_6", + "CMT_TOP_LH9_13", + "CMT_TOP_IMUX40_9", + "CMT_TOP_SE2A3_3", + "CMT_TOP_LOGIC_OUTS_L_B1_15", + "CMT_TOP_SE4BEG3_12", + "CMT_TOP_ER1BEG0_11", + "CMT_TOP_FAN0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_NE2A3_10", + "CMT_TOP_WW4B3_2", + "CMT_TOP_LOGIC_OUTS_L_B3_10", + "CMT_TOP_FAN0_7", + "CMT_TOP_WW4B0_3", + "CMT_TOP_LH11_8", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_TOP_IMUX47_4", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_EE4A0_10", + "CMT_TOP_WW4C1_6", + "CMT_TOP_IMUX35_11", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_NW2A1_11", + "CMT_LR_LOWER_B_MMCM_TESTIN23", + "CMT_TOP_IMUX46_9", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_SW4END3_7", + "CMT_TOP_EE4C0_15", + "CMT_TOP_NE2A3_15", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_NW4END3_6", + "CMT_TOP_EE2BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_EE4B0_12", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_FAN1_15", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_TOP_ER1BEG1_11", + "CMT_TOP_IMUX45_6", + "CMT_TOP_WW4END2_8", + "CMT_TOP_LOGIC_OUTS_L_B23_15", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_WW4END1_0", + "CMT_TOP_LH3_2", + "CMT_TOP_IMUX1_9", + "CMT_TOP_IMUX8_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_IMUX2_8", + "CMT_TOP_WW2A1_12", + "CMT_LR_LOWER_B_MMCM_TESTOUT26", + "CMT_TOP_OCLK_5", + "CMT_TOP_BYP0_3", + "CMT_TOP_NE4C0_10", + "CMT_TOP_WW2A2_2", + "CMT_TOP_IMUX25_4", + "CMT_TOP_WL1END1_15", + "CMT_TOP_IMUX20_7", + "CMT_MMCM_DQS_TO_PHASERA", + "CMT_TOP_NW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_LR_LOWER_B_MMCM_DO1", + "CMT_TOP_WW4C0_3", + "CMT_TOP_IMUX28_5", + "CMT_R_LOWER_B_CLK_PERF0", + "CMT_TOP_NE2A0_2", + "CMT_TOP_WL1END2_12", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_WW4END2_15", + "CMT_TOP_EE4A3_12", + "CMT_TOP_BYP1_1", + "CMT_TOP_SE2A3_6", + "CMT_TOP_SW4A1_11", + "CMT_TOP_IMUX2_2", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX21_0", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_WW4END2_9", + "CMT_TOP_SE2A0_2", + "CMT_TOP_IMUX43_1", + "CMT_TOP_EE2BEG2_12", + "CMT_TOP_SE2A3_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT62", + "CMT_TOP_BYP4_12", + "CMT_LR_LOWER_B_MMCM_DO5", + "CMT_TOP_EE4BEG1_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_IMUX28_8", + "CMT_TOP_WW4C3_4", + "CMT_TOP_SW4END0_9", + "CMT_TOP_LH8_1", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_EE4C2_13", + "CMT_TOP_NE2A0_11", + "CMT_TOP_WW2A3_2", + "CMT_TOP_NW4A0_7", + "CMT_TOP_LH9_5", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT1", + "CMT_TOP_EE4C2_15", + "CMT_TOP_IMUX6_7", + "CMT_TOP_IMUX45_10", + "CMT_TOP_EL1BEG0_13", + "CMT_TOP_WR1END3_4", + "CMT_LR_LOWER_B_MMCM_TESTOUT32", + "CMT_TOP_LOGIC_OUTS_L_B13_14", + "CMT_TOP_EE2A0_6", + "CMT_TOP_EE2BEG0_9", + "CMT_LR_LOWER_B_MMCM_TESTOUT9", + "CMT_TOP_ER1BEG1_14", + "CMT_TOP_EE2A2_6", + "CMT_TOP_BYP2_2", + "CMT_TOP_LOGIC_OUTS_L_B14_14", + "CMT_TOP_LOGIC_OUTS_L_B0_11", + "CMT_TOP_IMUX21_6", + "CMT_TOP_SE4C3_1", + "CMT_TOP_SW2A2_3", + "CMT_TOP_EE2A0_14", + "CMT_TOP_IMUX19_7", + "CMT_TOP_IMUX0_4", + "CMT_TOP_ICLK_9", + "CMT_TOP_SW4END2_7", + "CMT_TOP_WW4B3_9", + "CMT_TOP_IMUX15_0", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_WW2A0_15", + "CMT_LR_LOWER_B_MMCM_TESTIN20", + "CMT_TOP_EL1BEG2_9", + "CMT_TOP_IMUX33_12", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_WW4END2_5", + "CMT_TOP_WW2A1_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_IMUX9_8", + "CMT_TOP_WW2A1_9", + "CMT_TOP_OCLK1X_90_13", + "CMT_TOP_SW4A0_4", + "CMT_TOP_LOGIC_OUTS_L_B13_13", + "CMT_TOP_BYP5_15", + "CMT_TOP_BYP0_11", + "CMT_TOP_FAN1_8", + "CMT_TOP_IMUX12_13", + "CMT_TOP_IMUX34_4", + "CMT_TOP_IMUX12_9", + "CMT_TOP_SW4A1_10", + "CMT_TOP_SW4END1_12", + "CMT_TOP_WW4A2_12", + "CMT_TOP_NW4A0_11", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4B0_2", + "CMT_TOP_LH2_2", + "CMT_TOP_IMUX10_7", + "CMT_TOP_IMUX39_0", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_WW4END0_10", + "CMT_TOP_FAN3_13", + "CMT_TOP_IMUX30_10", + "CMT_TOP_NW2A0_9", + "CMT_TOP_IMUX2_15", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_TOP_SW4A3_5", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_IMUX14_1", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_WL1END0_10", + "CMT_TOP_WW2A2_15", + "CMT_TOP_IMUX26_1", + "CMT_TOP_BLOCK_OUTS_L_B2_15", + "CMT_TOP_WL1END0_1", + "CMT_TOP_CTRL0_9", + "CMT_TOP_LH11_6", + "CMT_TOP_NE4C3_8", + "CMT_TOP_IMUX46_12", + "CMT_TOP_NE4BEG1_13", + "CMT_TOP_WL1END0_7", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_TOP_LH12_4", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_NE4C3_4", + "CMT_TOP_ER1BEG0_7", + "CMT_TOP_WL1END2_13", + "CMT_TOP_WW2END2_4", + "CMT_TOP_SE4C2_6", + "CMT_TOP_SW4END1_8", + "CMT_TOP_SE4BEG2_13", + "CMT_TOP_IMUX26_12", + "CMT_TOP_BYP2_13", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_BYP3_14", + "CMT_TOP_SW2A1_1", + "MMCMOUT_CLK_FREQ_BB_3", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_WW4END3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_9", + "CMT_TOP_FAN7_15", + "CMT_TOP_NW2A2_14", + "CMT_TOP_WL1END2_6", + "CMT_TOP_IMUX43_6", + "CMT_TOP_NW4A1_1", + "CMT_TOP_SE4C1_8", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_SE4BEG0_3", + "CMT_TOP_IMUX40_5", + "CMT_TOP_EE2A2_14", + "CMT_TOP_EE4BEG3_2", + "CMT_TOP_BLOCK_OUTS_L_B1_10", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_IMUX34_1", + "CMT_TOP_WL1END2_0", + "CMT_TOP_EE4A1_3", + "CMT_TOP_OCLKDIV_10", + "CMT_TOP_LH7_0", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_IMUX8_11", + "CMT_TOP_WW2END0_2", + "CMT_TOP_IMUX0_3", + "CMT_TOP_EE4A0_1", + "CMT_TOP_WW4A1_4", + "CMT_TOP_IMUX23_3", + "CMT_TOP_IMUX20_0", + "CMT_TOP_WR1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_LH11_9", + "CMT_TOP_IMUX25_1", + "CMT_TOP_ER1BEG1_1", + "CMT_TOP_IMUX44_7", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_TOP_EE2A3_15", + "CMT_TOP_FAN0_12", + "CMT_TOP_WW4A3_10", + "CMT_TOP_IMUX31_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT47", + "CMT_TOP_EL1BEG3_15", + "CMT_TOP_WW2A0_4", + "CMT_TOP_SW2A0_10", + "CMT_TOP_EE4C3_13", + "CMT_TOP_IMUX11_13", + "CMT_TOP_LH6_15", + "CMT_TOP_WW4A3_3", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_LH1_5", + "CMT_R_LOWER_B_CLK_MMCM10", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_NW4A0_4", + "CMT_TOP_CLK1_5", + "CMT_TOP_IMUX37_12", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_NE2A0_10", + "CMT_TOP_WW4B2_14", + "CMT_TOP_IMUX21_15", + "CMT_TOP_IMUX18_5", + "CMT_TOP_LOGIC_OUTS_L_B21_14", + "CMT_MMCM_PHASERREF0", + "CMT_TOP_IMUX24_8", + "CMT_TOP_IMUX24_7", + "CMT_TOP_LH12_11", + "CMT_TOP_NW2A2_13", + "CMT_TOP_EE4B0_2", + "CMT_LR_LOWER_B_MMCM_TESTOUT2", + "CMT_TOP_IMUX29_12", + "CMT_TOP_SW2A0_2", + "CMT_TOP_SW4A3_1", + "CMT_TOP_NE4BEG0_13", + "CMT_TOP_EE2A3_10", + "CMT_TOP_IMUX42_12", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_WL1END3_2", + "CMT_TOP_SE4BEG0_11", + "CMT_TOP_FAN4_5", + "CMT_TOP_EE4A1_10", + "CMT_TOP_NE2A1_2", + "CMT_TOP_SE4BEG1_7", + "CMT_TOP_NE2A1_10", + "CMT_TOP_WW2END2_11", + "CMT_TOP_SW4END3_15", + "CMT_TOP_IMUX36_3", + "CMT_TOP_IMUX10_11", + "CMT_TOP_IMUX45_14", + "CMT_TOP_IMUX14_9", + "CMT_TOP_ER1BEG2_11", + "CMT_TOP_IMUX21_7", + "CMT_TOP_EE4B3_11", + "CMT_TOP_IMUX25_7", + "CMT_TOP_SW4A2_5", + "CMT_MMCM_PHASERA_CTSBUS1", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_EE4BEG2_12", + "CMT_TOP_NE2A2_12", + "CMT_TOP_WW4C0_9", + "CMT_TOP_IMUX9_15", + "CMT_TOP_NE4C2_3", + "CMT_TOP_EE4A2_15", + "CMT_TOP_WW4A1_8", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_BYP7_5", + "CMT_TOP_NE2A0_5", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_EE4A0_2", + "CMT_TOP_SW4END3_8", + "CMT_TOP_IMUX20_6", + "CMT_TOP_LH9_3", + "CMT_TOP_EE4B3_0", + "CMT_TOP_EL1BEG1_9", + "CMT_TOP_SW2A2_10", + "CMT_TOP_WW4END3_0", + "CMT_TOP_OCLK_14", + "CMT_TOP_WW2A0_1", + "CMT_TOP_SW4A0_9", + "CMT_TOP_IMUX45_7", + "CMT_TOP_IMUX19_2", + "CMT_TOP_IMUX42_5", + "CMT_TOP_NW4A3_15", + "CMT_TOP_IMUX18_11", + "CMT_TOP_IMUX27_13", + "CMT_TOP_EE4B1_12", + "CMT_TOP_LOGIC_OUTS_L_B10_12", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_BLOCK_OUTS_L_B0_9", + "CMT_TOP_WL1END2_7", + "CMT_TOP_SW4END3_6", + "CMT_TOP_SW4A0_3", + "CMT_TOP_SE4BEG2_14", + "CMT_LR_LOWER_B_MMCM_DO7", + "CMT_TOP_BYP1_10", + "CMT_TOP_EE4BEG0_15", + "CMT_TOP_IMUX27_7", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_EE4BEG3_12", + "MMCMOUT_CLK_FREQ_BB_2", + "CMT_TOP_SW4A2_10", + "CMT_TOP_IMUX28_12", + "CMT_TOP_LOGIC_OUTS_L_B6_10", + "CMT_TOP_IMUX27_8", + "CMT_TOP_BYP5_6", + "CMT_TOP_SW4END3_14", + "CMT_TOP_IMUX34_3", + "CMT_TOP_EL1BEG2_13", + "CMT_TOP_FAN0_0", + "CMT_TOP_WW2A3_14", + "CMT_TOP_IMUX23_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT12", + "CMT_TOP_WR1END1_1", + "CMT_TOP_WW4END3_6", + "CMT_TOP_WW4B3_7", + "CMT_TOP_SW4A0_7", + "CMT_TOP_NE4BEG1_11", + "CMT_TOP_SW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B15_10", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_LOGIC_OUTS_L_B15_15", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_IMUX6_2", + "CMT_TOP_IMUX10_14", + "CMT_R_LOWER_B_CLK_MMCM8", + "MMCM_CLK_FREQ_BB_NS3", + "CMT_TOP_IMUX23_14", + "CMT_TOP_WW4A1_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT14", + "CMT_TOP_NE4BEG2_15", + "CMT_TOP_WW4C2_5", + "CMT_TOP_IMUX40_0", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_EE2A2_8", + "CMT_TOP_NE2A3_7", + "CMT_TOP_ER1BEG1_2", + "MMCM_CLK_FREQ_BB_REBUF1_NS", + "CMT_TOP_SW4END0_12", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_LOGIC_OUTS_L_B14_11", + "CMT_TOP_SE2A3_14", + "CMT_TOP_IMUX3_5", + "CMT_TOP_LH4_5", + "CMT_TOP_BYP7_4", + "CMT_TOP_CLK1_0", + "CMT_TOP_IMUX26_11", + "CMT_TOP_IMUX1_5", + "CMT_TOP_LH9_4", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_SE4C2_1", + "CMT_TOP_IMUX38_14", + "CMT_TOP_EE2A3_1", + "CMT_TOP_SW2A2_9", + "CMT_TOP_EL1BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_11", + "CMT_TOP_IMUX28_0", + "CMT_TOP_BYP3_11", + "CMT_TOP_NE4BEG3_15", + "CMT_TOP_IMUX18_2", + "CMT_TOP_WW2END0_1", + "CMT_TOP_LOGIC_OUTS_L_B7_9", + "CMT_TOP_SW2A1_15", + "CMT_TOP_IMUX11_14", + "CMT_TOP_BYP3_0", + "CMT_TOP_BYP4_3", + "CMT_TOP_IMUX17_14", + "CMT_TOP_CLK1_10", + "CMT_TOP_EE4BEG0_11", + "CMT_TOP_NE2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B8_14", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_BLOCK_OUTS_L_B0_11", + "CMT_TOP_EE2A3_8", + "CMT_TOP_EE4A2_8", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_WW4C0_6", + "CMT_TOP_ER1BEG2_14", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_CTRL0_4", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SW4END0_6", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_NW4A3_7", + "CMT_TOP_WW4B1_10", + "CMT_TOP_SE2A3_5", + "CMT_TOP_LH5_10", + "CMT_TOP_WW4END0_11", + "CMT_TOP_BYP7_7", + "CMT_LR_LOWER_B_MMCM_LOCKED", + "CMT_TOP_IMUX29_5", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_IMUX25_5", + "CMT_TOP_WW4A3_4", + "CMT_TOP_NE4BEG0_14", + "CMT_LR_LOWER_B_MMCM_DADDR0", + "CMT_TOP_FAN5_9", + "CMT_TOP_MONITOR_P_15", + "CMT_TOP_IMUX46_8", + "CMT_TOP_IMUX31_11", + "CMT_TOP_BYP4_0", + "CMT_TOP_SE2A0_13", + "CMT_TOP_IMUX18_4", + "CMT_TOP_BLOCK_OUTS_L_B1_14", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_TOP_LOGIC_OUTS_L_B16_9", + "CMT_TOP_WW2A2_3", + "CMT_TOP_IMUX44_12", + "CMT_TOP_IMUX28_3", + "CMT_TOP_SE2A1_12", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WW2A1_11", + "CMT_TOP_LH6_1", + "CMT_TOP_LH7_3", + "CMT_LR_LOWER_B_MMCM_TESTOUT55", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_TOP_NE4BEG1_15", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_NE2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH6_0", + "CMT_TOP_WW4C0_7", + "CMT_TOP_SE4BEG2_2", + "CMT_TOP_WW4END1_10", + "CMT_TOP_IMUX3_13", + "CMT_TOP_LH3_5", + "CMT_TOP_NE4C0_4", + "CMT_TOP_BYP0_10", + "CMT_TOP_SW2A1_7", + "CMT_TOP_NE4C0_2", + "CMT_TOP_IMUX45_13", + "CMT_LR_LOWER_B_MMCM_RST", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "MMCMOUT_CLK_FREQ_BB_0", + "CMT_TOP_SE4C0_7", + "CMT_TOP_EL1BEG3_4", + "CMT_LR_LOWER_B_MMCM_DO0", + "CMT_TOP_LOGIC_OUTS_L_B11_10", + "CMT_TOP_SE4C0_12", + "CMT_TOP_SW4A1_8", + "CMT_MMCM_PHASER_OUT_B_OCLK1X_90", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_LH11_11", + "CMT_TOP_WR1END3_3", + "CMT_TOP_MONITOR_P_1", + "CMT_TOP_OCLK_15", + "CMT_TOP_LH8_8", + "CMT_TOP_EE4A0_14", + "CMT_TOP_SW4A3_6", + "CMT_TOP_SW4END1_11", + "CMT_TOP_WW4END3_15", + "CMT_TOP_IMUX31_8", + "CMT_TOP_IMUX18_13", + "CMT_TOP_EE2A3_0", + "CMT_TOP_IMUX21_11", + "CMT_TOP_IMUX13_2", + "CMT_TOP_IMUX39_4", + "CMT_TOP_NW4END2_11", + "CMT_LR_LOWER_B_MMCM_CLKOUT3B", + "CMT_TOP_MONITOR_P_3", + "CMT_LR_LOWER_B_MMCM_TESTOUT7", + "CMT_TOP_EE4B1_7", + "CMT_TOP_WW4A0_7", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_FAN1_13", + "CMT_TOP_IMUX21_13", + "CMT_TOP_WW4B0_11", + "CMT_TOP_SE2A1_2", + "CMT_R_LOWER_B_CLK_MMCM6", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_BYP5_11", + "CMT_TOP_NE2A0_4", + "CMT_TOP_LH9_0", + "CMT_TOP_IMUX22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_10", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_IMUX25_6", + "CMT_TOP_NE2A1_4", + "CMT_TOP_EE4BEG3_0", + "CMT_TOP_WW2END1_7", + "CMT_TOP_EE4B0_7", + "CMT_TOP_LH11_15", + "CMT_TOP_WW4B2_10", + "CMT_TOP_BYP1_0", + "CMT_TOP_IMUX22_4", + "CMT_TOP_SE4C1_0", + "CMT_TOP_IMUX24_14", + "CMT_TOP_FAN7_3", + "CMT_TOP_WW4A0_6", + "CMT_TOP_WW2END2_1", + "CMT_TOP_IMUX45_5", + "CMT_TOP_BYP6_4", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_TOP_BYP3_5", + "CMT_TOP_EE2A0_3", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_EE4C2_2", + "CMT_TOP_FAN2_10", + "CMT_TOP_CTRL1_5", + "CMT_TOP_CTRL0_5", + "CMT_TOP_WW2END0_6", + "CMT_TOP_IMUX1_3", + "CMT_TOP_NW4A1_15", + "CMT_TOP_WW2END0_7", + "CMT_TOP_NW4END0_11", + "CMT_TOP_EL1BEG0_12", + "CMT_TOP_IMUX41_13", + "CMT_TOP_LOGIC_OUTS_L_B20_11", + "CMT_TOP_WW4END1_12", + "CMT_TOP_WL1END2_3", + "CMT_TOP_EL1BEG3_14", + "CMT_TOP_IMUX36_11", + "CMT_MMCM_PHASERREF_ABOVE1", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_IMUX10_3", + "CMT_TOP_SW4A2_13", + "CMT_LR_LOWER_B_MMCM_DO6", + "CMT_TOP_IMUX37_10", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_SW4A3_12", + "CMT_TOP_NW2A0_13", + "CMT_TOP_BYP6_13", + "CMT_TOP_SW4END2_15", + "CMT_TOP_WR1END3_8", + "CMT_TOP_SW4A3_14", + "CMT_TOP_IMUX17_15", + "CMT_TOP_IMUX47_1", + "CMT_TOP_IMUX10_6", + "CMT_TOP_IMUX44_10", + "CMT_TOP_BYP6_11", + "CMT_TOP_NE4C1_0", + "CMT_TOP_WW4A3_1", + "CMT_TOP_BYP6_6", + "CMT_TOP_BYP4_10", + "CMT_TOP_LOGIC_OUTS_L_B23_11", + "CMT_LR_LOWER_B_MMCM_TESTIN24", + "CMT_TOP_NE4C0_3", + "CMT_TOP_SW4A3_9", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_OCLKDIV_8", + "CMT_TOP_LH2_1", + "CMT_TOP_EE4A3_13", + "CMT_TOP_IMUX42_1", + "CMT_TOP_SW4A1_6", + "CMT_TOP_LH12_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT10", + "CMT_TOP_LOGIC_OUTS_L_B22_13", + "CMT_TOP_NW4A2_13", + "CMT_TOP_IMUX7_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT23", + "CMT_TOP_NW4A1_9", + "CMT_TOP_BYP1_8", + "CMT_TOP_WW4C2_1", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_IMUX42_0", + "CMT_TOP_NW4A1_14", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_FAN7_1", + "CMT_TOP_IMUX13_13", + "CMT_TOP_SE4C2_9", + "CMT_TOP_LOGIC_OUTS_L_B16_14", + "CMT_TOP_IMUX38_12", + "CMT_TOP_WW2A3_0", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_WW4A2_9", + "CMT_TOP_NW4END3_13", + "CMT_TOP_NE4C2_12", + "CMT_TOP_ICLK_14", + "CMT_TOP_WW2A3_15", + "MMCMOUT_CLK_FREQ_BB_1", + "CMT_TOP_LH1_7", + "CMT_TOP_EE2BEG2_11", + "CMT_TOP_NW4A1_6", + "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "CMT_TOP_BYP2_1", + "CMT_TOP_WL1END2_10", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_IMUX13_0", + "CMT_TOP_EE2A3_14", + "CMT_TOP_LOGIC_OUTS_L_B22_12", + "CMT_TOP_LH9_15", + "CMT_TOP_IMUX30_7", + "CMT_TOP_IMUX32_15", + "CMT_TOP_WW4A0_3", + "CMT_TOP_FAN2_0", + "CMT_TOP_BLOCK_OUTS_L_B1_9", + "CMT_TOP_MONITOR_N_13", + "CMT_TOP_IMUX18_9", + "CMT_TOP_CTRL1_0", + "CMT_TOP_EE2A0_5", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_TOP_IMUX30_12", + "CMT_TOP_WW4A0_1", + "CMT_TOP_SE4BEG0_13", + "CMT_TOP_FAN3_0", + "CMT_TOP_LH2_7", + "CMT_TOP_OCLKDIV_13", + "CMT_TOP_IMUX30_2", + "CMT_TOP_FAN3_3", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_IMUX2_5", + "CMT_TOP_IMUX28_4", + "CMT_TOP_IMUX10_9", + "CMT_TOP_MONITOR_N_14", + "CMT_TOP_EL1BEG3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_9", + "CMT_TOP_LH11_0", + "CMT_TOP_EE4C1_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT29", + "CMT_TOP_IMUX15_5", + "CMT_TOP_IMUX13_8", + "CMT_TOP_SE4C1_9", + "CMT_TOP_EE4C0_5", + "CMT_TOP_IMUX2_0", + "CMT_TOP_NE4BEG3_1", + "CMT_LR_LOWER_B_MMCM_CLKOUT4", + "CMT_TOP_SW4END1_1", + "CMT_TOP_WW4B0_13", + "CMT_TOP_LH12_7", + "CMT_TOP_WW4C3_13", + "CMT_TOP_WR1END3_7", + "CMT_TOP_WL1END1_7", + "CMT_TOP_OCLK_4", + "CMT_TOP_EE4C1_2", + "CMT_TOP_BYP0_4", + "CMT_TOP_FAN4_0", + "CMT_TOP_BYP7_10", + "CMT_TOP_SW2A0_9", + "CMT_TOP_IMUX2_13", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_MONITOR_N_9", + "CMT_TOP_WW4A1_3", + "CMT_TOP_WW4END0_9", + "CMT_TOP_FAN4_4", + "CMT_TOP_SW2A0_15", + "CMT_TOP_ICLKDIV_9", + "CMT_TOP_IMUX25_12", + "CMT_TOP_NW4END1_13", + "CMT_TOP_IMUX39_15", + "CMT_TOP_IMUX7_8", + "CMT_TOP_LOGIC_OUTS_L_B5_11", + "CMT_TOP_WW4B2_11", + "CMT_TOP_BYP7_0", + "CMT_TOP_ICLKDIV_13", + "CMT_TOP_FAN7_11", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_BYP6_2", + "CMT_TOP_EL1BEG3_1", + "CMT_MMCM_PHASER_OUT_A_OCLKDIV", + "CMT_LR_LOWER_B_MMCM_TESTOUT22", + "CMT_TOP_EE4C2_8", + "CMT_TOP_IMUX14_6", + "CMT_TOP_LOGIC_OUTS_L_B19_11", + "CMT_TOP_SW4A2_11", + "CMT_LR_LOWER_B_MMCM_DO8", + "CMT_TOP_IMUX10_1", + "CMT_TOP_WW4END1_14", + "CMT_TOP_NE4C3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_LOGIC_OUTS_L_B8_9", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_IMUX37_11", + "CMT_TOP_IMUX40_14", + "CMT_TOP_IMUX6_4", + "CMT_TOP_BLOCK_OUTS_L_B0_10", + "CMT_TOP_BLOCK_OUTS_L_B1_11", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_TOP_CTRL0_11", + "CMT_TOP_IMUX43_7", + "CMT_TOP_LOGIC_OUTS_L_B23_9", + "CMT_TOP_EE2BEG0_4", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LOGIC_OUTS_L_B7_10", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_WW4B0_14", + "CMT_TOP_IMUX38_7", + "CMT_TOP_IMUX21_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT50", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_SW4A2_7", + "CMT_TOP_OCLK1X_90_10", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_LH1_2", + "CMT_TOP_BYP0_9", + "CMT_TOP_LOGIC_OUTS_L_B4_10", + "CMT_TOP_LOGIC_OUTS_L_B11_15", + "CMT_TOP_LOGIC_OUTS_L_B23_14", + "CMT_TOP_IMUX44_13", + "CMT_R_LOWER_B_CLK_MMCM13", + "CMT_TOP_FAN4_10", + "CMT_TOP_IMUX30_3", + "CMT_TOP_WR1END3_10", + "CMT_TOP_EE2BEG3_9", + "CMT_TOP_WR1END1_6", + "CMT_TOP_SW2A2_5", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_NW2A1_8", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_IMUX15_11", + "CMT_TOP_IMUX36_9", + "CMT_TOP_EE4B2_1", + "CMT_TOP_IMUX38_15", + "CMT_TOP_SW2A2_0", + "CMT_TOP_NW4END2_3", + "CMT_TOP_WW4A0_15", + "CMT_TOP_FAN4_2", + "CMT_TOP_IMUX10_13", + "CMT_TOP_IMUX43_0", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_WW4END0_8", + "CMT_TOP_SW4A1_4", + "CMT_TOP_WW2A2_12", + "CMT_TOP_CLK0_12", + "CMT_TOP_IMUX29_0", + "CMT_TOP_FAN6_0", + "CMT_TOP_NW2A2_12", + "CMT_TOP_IMUX43_2", + "CMT_TOP_EE4B1_1", + "CMT_TOP_NW2A2_8", + "CMT_TOP_CTRL1_10", + "CMT_TOP_IMUX23_13", + "CMT_TOP_WL1END1_14", + "CMT_TOP_WW2A0_3", + "CMT_TOP_WW2A2_5", + "CMT_TOP_FAN4_9", + "CMT_TOP_SW4END1_6", + "CMT_TOP_NE4BEG0_9", + "CMT_TOP_EE4B2_5", + "MMCM_CLK_FREQ_BB_NS2", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_WW2A2_0", + "CMT_TOP_ER1BEG1_13", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_NE4C3_2", + "CMT_LR_LOWER_B_MMCM_TESTOUT25", + "CMT_TOP_WW2END3_3", + "CMT_TOP_SE4BEG3_4", + "CMT_TOP_IMUX5_4", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_TOP_WW2END3_2", + "CMT_TOP_NE4C2_1", + "CMT_TOP_WR1END0_15", + "CMT_TOP_SW4END2_2", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_NE2A3_8", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_EE2A2_15", + "CMT_TOP_EE2BEG2_15", + "CMT_TOP_LOGIC_OUTS_L_B2_11", + "CMT_TOP_SW4A1_3", + "CMT_TOP_OCLK1X_90_15", + "CMT_TOP_NW4A2_8", + "CMT_TOP_SE4C2_5", + "CMT_TOP_WR1END1_5", + "CMT_LR_LOWER_B_MMCM_TESTOUT31", + "CMT_TOP_LOGIC_OUTS_L_B22_11", + "CMT_TOP_WW4C2_15", + "CMT_TOP_ER1BEG3_3", + "CMT_TOP_WW2A3_9", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_FAN2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_IMUX23_15", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_IMUX41_2", + "CMT_TOP_EE4B2_15", + "CMT_TOP_NE4C0_15", + "CMT_TOP_IMUX20_2", + "CMT_TOP_SW4END2_6", + "CMT_TOP_NW4END0_9", + "CMT_TOP_IMUX45_1", + "CMT_TOP_LOGIC_OUTS_L_B18_12", + "CMT_TOP_IMUX24_9", + "CMT_TOP_WW4B3_3", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_WW4C1_12", + "CMT_TOP_NE4C3_3", + "CMT_TOP_BYP2_0", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_WL1END3_13", + "CMT_TOP_LH8_12", + "CMT_TOP_LH12_6", + "CMT_TOP_SW4END2_9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_EE4A1_1", + "CMT_TOP_IMUX27_9", + "CMT_TOP_SW4A0_10", + "CMT_TOP_IMUX26_3", + "CMT_TOP_SW4A2_0", + "CMT_TOP_EL1BEG3_9", + "CMT_TOP_ER1BEG1_15", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_FAN6_14", + "CMT_TOP_LOGIC_OUTS_L_B2_10", + "CMT_MMCM_A_WREN_TOFIFO", + "CMT_TOP_IMUX47_0", + "CMT_TOP_IMUX7_10", + "CMT_TOP_FAN5_5", + "CMT_TOP_NW4END2_10", + "CMT_TOP_SE4C0_3", + "CMT_TOP_IMUX45_4", + "CMT_TOP_EL1BEG1_11", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_EE2A3_7", + "CMT_TOP_EE4A3_9", + "CMT_TOP_IMUX19_0", + "CMT_TOP_WR1END0_0", + "CMT_TOP_BYP4_15", + "CMT_TOP_WW4B1_12", + "CMT_TOP_SW4A1_13", + "CMT_TOP_EE4BEG1_9", + "CMT_TOP_NE2A3_3", + "CMT_TOP_WW4C1_8", + "CMT_TOP_SW4A3_10", + "CMT_TOP_FAN5_11", + "CMT_TOP_NE4C0_5", + "CMT_LR_LOWER_B_MMCM_TESTIN4", + "CMT_TOP_IMUX8_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT36", + "CMT_LR_LOWER_B_MMCM_TESTOUT46", + "CMT_TOP_WL1END2_2", + "CMT_TOP_SE2A0_9", + "CMT_TOP_EE4A3_4", + "CMT_TOP_WW4END0_12", + "CMT_TOP_BYP1_2", + "CMT_TOP_WW4END2_3", + "CMT_TOP_IMUX24_2", + "CMT_TOP_IMUX6_0", + "CMT_TOP_NW4END1_10", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_WW2END2_10", + "CMT_TOP_EE4B2_0", + "CMT_TOP_IMUX45_12", + "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", + "CMT_TOP_SW2A0_7", + "CMT_TOP_CLK0_8", + "CMT_TOP_IMUX44_0", + "CMT_TOP_EE4C3_10", + "CMT_TOP_BYP4_6", + "CMT_TOP_LH2_12", + "CMT_TOP_WW2END1_11", + "CMT_TOP_IMUX7_0", + "CMT_TOP_IMUX9_4", + "CMT_TOP_EE4A0_4", + "CMT_TOP_LH9_6", + "CMT_TOP_SW2A3_7", + "CMT_TOP_WW4END2_13", + "CMT_TOP_WW4A3_9", + "CMT_MMCM_PHYCTRL_SYNC_BB_UP", + "CMT_TOP_NW4END3_8", + "CMT_TOP_NW4A1_2", + "CMT_TOP_SE2A0_7", + "CMT_TOP_WW4B1_3", + "CMT_TOP_BYP4_11", + "CMT_TOP_IMUX16_15", + "CMT_TOP_WR1END2_8", + "CMT_TOP_LH4_12", + "CMT_TOP_NW2A0_2", + "CMT_TOP_EE4B0_3", + "CMT_TOP_FAN1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_10", + "CMT_TOP_SE2A1_4", + "CMT_TOP_SE4C0_6", + "CMT_TOP_LH6_14", + "MMCM_CLK_FREQ_BB_NS1", + "CMT_TOP_IMUX17_4", + "CMT_LR_LOWER_B_MMCM_DI15", + "CMT_TOP_LH2_10", + "CMT_TOP_EL1BEG1_13", + "CMT_TOP_WR1END1_15", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_EL1BEG1_12", + "CMT_TOP_WW4END0_15", + "CMT_TOP_SW4END2_4", + "CMT_TOP_WL1END0_6", + "CMT_TOP_LOGIC_OUTS_L_B13_12", + "CMT_TOP_IMUX35_14", + "CMT_MMCM_A_RDEN_TOFIFO", + "CMT_LR_LOWER_B_MMCM_TESTOUT44", + "CMT_TOP_IMUX22_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT63", + "CMT_TOP_IMUX37_2", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_BYP1_14", + "CMT_TOP_FAN3_15", + "CMT_TOP_EE4B3_6", + "CMT_TOP_NW4END2_5", + "CMT_TOP_EE4A1_7", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_IMUX15_3", + "CMT_TOP_EE2A3_12", + "CMT_TOP_LH7_10", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_WR1END3_9", + "CMT_TOP_WW2END3_10", + "CMT_TOP_SW4A0_13", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_LH6_7", + "CMT_TOP_WW4END3_12", + "CMT_TOP_EE4C2_10", + "CMT_TOP_IMUX11_3", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_MONITOR_P_12", + "CMT_TOP_EE4B2_4", + "CMT_TOP_WW2A3_5", + "CMT_TOP_WW2END2_6", + "CMT_TOP_SW4END0_7", + "CMT_TOP_OCLK_9", + "CMT_TOP_LH1_9", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_BYP7_11", + "CMT_TOP_WL1END1_2", + "CMT_TOP_SE4C3_13", + "CMT_TOP_FAN5_15", + "CMT_TOP_WW2A3_8", + "CMT_TOP_WW2END3_0", + "CMT_TOP_LH6_13", + "CMT_TOP_IMUX30_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT3", + "CMT_TOP_EL1BEG0_1", + "CMT_TOP_IMUX22_5", + "CMT_TOP_FAN2_11", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_IMUX12_0", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_NE2A1_1", + "CMT_TOP_IMUX19_3", + "CMT_TOP_WW4B0_5", + "CMT_TOP_ICLK_8", + "CMT_TOP_EE4A2_14", + "CMT_TOP_IMUX45_15", + "CMT_TOP_IMUX7_9", + "CMT_TOP_WW2END3_13", + "CMT_TOP_IMUX7_6", + "CMT_TOP_SW2A1_2", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_IMUX36_2", + "CMT_TOP_WW2END3_1", + "CMT_TOP_NE4C0_1", + "CMT_TOP_IMUX11_11", + "CMT_TOP_BYP3_10", + "CMT_TOP_IMUX11_5", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_TOP_NE4BEG2_2", + "CMT_LR_LOWER_B_MMCM_TESTIN2", + "CMT_TOP_IMUX30_1", + "CMT_TOP_WR1END1_12", + "CMT_TOP_WW2END0_11", + "CMT_TOP_WW4C1_9", + "CMT_TOP_SE4C3_2", + "CMT_TOP_NE4C0_7", + "CMT_TOP_EE4A2_1", + "CMT_TOP_WW2END2_9", + "CMT_TOP_SW2A0_14", + "CMT_TOP_IMUX43_3", + "CMT_TOP_IMUX33_3", + "CMT_TOP_IMUX21_4", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_LH5_8", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_NW4A2_10", + "CMT_TOP_WW4END3_1", + "CMT_TOP_LOGIC_OUTS_L_B14_10", + "CMT_TOP_IMUX35_4", + "CMT_TOP_WW4A3_13", + "CMT_TOP_SW4A0_14", + "CMT_TOP_NE4C1_10", + "CMT_TOP_LOGIC_OUTS_L_B3_9", + "CMT_TOP_IMUX42_8", + "CMT_TOP_EE2A3_4", + "CMT_TOP_EE4BEG2_6", + "CMT_TOP_LH3_14", + "CMT_TOP_NW4END3_14", + "CMT_TOP_IMUX38_8", + "CMT_TOP_CLK0_0", + "CMT_TOP_SE2A1_6", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_LH8_11", + "CMT_TOP_FAN7_2", + "CMT_TOP_EE2A0_7", + "CMT_TOP_IMUX19_13", + "CMT_TOP_NE4BEG3_13", + "CMT_TOP_WW4A0_13", + "CMT_TOP_NE4BEG2_10", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_WW4C3_9", + "CMT_TOP_EE2BEG0_10", + "CMT_TOP_IMUX37_1", + "CMT_TOP_EE4C3_5", + "CMT_TOP_NE4C3_5", + "CMT_TOP_LOGIC_OUTS_L_B6_13", + "CMT_TOP_IMUX10_15", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_IMUX35_13", + "CMT_TOP_SE2A0_15", + "CMT_TOP_ER1BEG2_12", + "CMT_TOP_BYP5_2", + "CMT_TOP_NE2A0_12", + "CMT_TOP_EE4B1_15", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_IMUX6_1", + "CMT_TOP_NE2A0_9", + "CMT_TOP_IMUX36_4", + "CMT_TOP_IMUX47_14", + "CMT_TOP_BYP4_1", + "CMT_TOP_IMUX9_3", + "CMT_TOP_IMUX15_6", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_SE2A2_13", + "CMT_TOP_IMUX7_3", + "CMT_TOP_NW4END1_1", + "CMT_TOP_FAN3_8", + "CMT_TOP_LH4_1", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX45_0", + "CMT_TOP_ER1BEG3_13", + "CMT_TOP_EE4B1_9", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_FAN6_9", + "CMT_TOP_LH8_15", + "CMT_TOP_EE4C2_3", + "CMT_TOP_SW4A1_15", + "CMT_TOP_WR1END1_8", + "CMT_TOP_IMUX19_9", + "CMT_TOP_IMUX5_10", + "CMT_TOP_NE2A0_15", + "CMT_TOP_WR1END3_13", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_EL1BEG0_11", + "CMT_TOP_EE4A0_5", + "CMT_TOP_IMUX24_13", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NW2A0_5", + "CMT_TOP_CTRL1_15", + "CMT_TOP_IMUX24_10", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_IMUX16_10", + "CMT_TOP_EE4BEG1_13", + "CMT_TOP_LOGIC_OUTS_L_B8_12", + "CMT_TOP_SW4END1_4", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX5_11", + "CMT_TOP_LOGIC_OUTS_L_B17_11", + "CMT_TOP_EE4C0_9", + "CMT_TOP_EE4B0_1", + "CMT_TOP_IMUX18_6", + "CMT_TOP_SW2A3_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_WW4A3_7", + "CMT_TOP_LH10_15", + "CMT_TOP_WW4A1_7", + "CMT_TOP_IMUX41_6", + "CMT_TOP_WW4C3_15", + "CMT_TOP_EL1BEG2_15", + "CMT_TOP_LH4_0", + "CMT_TOP_SW2A2_8", + "CMT_TOP_WW2A0_9", + "CMT_TOP_BYP2_7", + "CMT_TOP_LOGIC_OUTS_L_B12_12", + "CMT_LR_LOWER_B_MMCM_TESTOUT61", + "CMT_TOP_SW4A1_2", + "CMT_TOP_FAN3_4", + "CMT_TOP_IMUX4_10", + "CMT_TOP_SW4END3_3", + "CMT_TOP_LOGIC_OUTS_L_B17_12", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH11_7", + "CMT_TOP_NW2A3_1", + "CMT_TOP_WW4A1_5", + "CMT_TOP_WW2A2_11", + "CMT_TOP_FAN3_5", + "CMT_TOP_EE4C1_3", + "CMT_TOP_WW2A2_7", + "CMT_TOP_BYP5_10", + "CMT_TOP_OCLK_1", + "CMT_TOP_EE4C1_9", + "CMT_TOP_WL1END3_4", + "CMT_TOP_EE2A0_10", + "CMT_TOP_BYP7_15", + "CMT_LR_LOWER_B_MMCM_CLKIN2", + "CMT_TOP_BYP0_14", + "CMT_TOP_FAN2_14", + "CMT_TOP_WW4END2_12", + "CMT_TOP_IMUX41_12", + "CMT_TOP_EE4B3_2", + "CMT_TOP_SW2A1_11", + "CMT_TOP_BYP1_12", + "CMT_TOP_NW4END2_2", + "CMT_TOP_IMUX15_15", + "CMT_TOP_SE4C0_4", + "CMT_TOP_LOGIC_OUTS_L_B2_12", + "CMT_TOP_ICLK_15", + "CMT_TOP_FAN6_1", + "CMT_TOP_EE4C1_7", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_IMUX28_11", + "CMT_TOP_SE4C1_6", + "CMT_TOP_SW4END0_15", + "CMT_TOP_IMUX39_6", + "MMCM_CLK_FREQ_BB_REBUF3_NS", + "CMT_TOP_IMUX35_2", + "CMT_TOP_LOGIC_OUTS_L_B5_14", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_NE2A1_9", + "CMT_TOP_WL1END0_2", + "CMT_TOP_IMUX33_10", + "CMT_R_LOWER_B_CLK_MMCM9", + "CMT_TOP_IMUX44_1", + "CMT_TOP_LOGIC_OUTS_L_B22_9", + "CMT_LR_LOWER_B_MMCM_TESTIN27", + "CMT_TOP_IMUX41_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT4", + "CMT_MMCM_PHASERA_DTSBUS1", + "CMT_TOP_WW2A1_2", + "CMT_TOP_IMUX16_5", + "CMT_TOP_NW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_TOP_IMUX39_7", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_TOP_SW4END3_10", + "CMT_TOP_IMUX26_0", + "CMT_TOP_EL1BEG0_4", + "CMT_TOP_IMUX18_15", + "CMT_TOP_IMUX4_6", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_IMUX4_14", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_EE4B3_3", + "CMT_TOP_LOGIC_OUTS_L_B21_13", + "CMT_TOP_WW4B0_6", + "CMT_TOP_NW2A0_1", + "CMT_TOP_EE4C2_14", + "CMT_TOP_IMUX27_4", + "CMT_TOP_LOGIC_OUTS_L_B0_10", + "CMT_TOP_NE4BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_EE4C1_8", + "CMT_TOP_EE4C1_4", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_SW2A3_9", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_WW4END0_14", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_BYP2_4", + "CMT_TOP_WL1END0_15", + "CMT_TOP_IMUX0_9", + "CMT_TOP_NW2A3_6", + "CMT_TOP_LH3_15", + "CMT_TOP_IMUX42_14", + "CMT_TOP_WW4A0_14", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_CLK0_7", + "CMT_TOP_WL1END3_0", + "CMT_TOP_FAN5_13", + "CMT_LR_LOWER_B_MMCM_TESTOUT52", + "CMT_TOP_IMUX13_7", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_EE2A2_0", + "CMT_LR_LOWER_B_MMCM_DCLK", + "CMT_TOP_ICLK_4", + "CMT_TOP_LOGIC_OUTS_L_B21_9", + "CMT_TOP_IMUX4_0", + "CMT_TOP_EE4BEG0_13", + "CMT_TOP_MONITOR_P_9", + "CMT_R_LOWER_B_CLK_IN1_INT", + "CMT_TOP_IMUX3_6", + "CMT_TOP_EE4B0_11", + "CMT_TOP_BYP7_1", + "CMT_TOP_OCLKDIV_9", + "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "CMT_TOP_WW2END0_8", + "CMT_TOP_FAN1_14", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_WW2END1_3", + "CMT_TOP_NE4C2_14", + "CMT_TOP_SE2A3_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_NE4BEG3_9", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_BYP3_4", + "CMT_TOP_SE4C3_0", + "CMT_TOP_IMUX25_8", + "CMT_TOP_NE4BEG1_12", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_SW4END3_0", + "CMT_LR_LOWER_B_MMCM_CLKOUT5", + "CMT_TOP_WW4C0_12", + "CMT_TOP_IMUX3_3", + "CMT_TOP_WW2END1_2", + "CMT_TOP_SE4C1_3", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_LH9_10", + "CMT_TOP_WW2A0_11", + "CMT_TOP_IMUX25_11", + "CMT_TOP_IMUX46_13", + "CMT_TOP_NW2A1_1", + "CMT_TOP_IMUX6_15", + "CMT_TOP_IMUX36_15", + "CMT_TOP_IMUX14_12", + "CMT_TOP_CTRL1_14", + "CMT_TOP_SE2A2_15", + "CMT_TOP_NW2A2_5", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX19_6", + "CMT_TOP_IMUX25_15", + "CMT_TOP_WW4A1_2", + "CMT_TOP_EE2BEG0_14", + "CMT_TOP_NW4A2_9", + "CMT_TOP_IMUX19_11", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_SE4BEG2_5", + "CMT_LR_LOWER_B_MMCM_DO14", + "CMT_TOP_BLOCK_OUTS_L_B3_11", + "CMT_TOP_CLK1_13", + "CMT_LR_LOWER_B_MMCM_DO3", + "CMT_TOP_NE4C3_11", + "CMT_TOP_FAN2_13", + "CMT_TOP_NW4END2_9", + "CMT_TOP_WW2A1_7", + "CMT_TOP_SW4END0_8", + "CMT_TOP_WW4A2_15", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WL1END0_4", + "CMT_TOP_IMUX35_1", + "CMT_TOP_IMUX18_12", + "CMT_TOP_NE4C1_1", + "CMT_TOP_WL1END0_5", + "CMT_LR_LOWER_B_MMCM_DO15", + "CMT_TOP_IMUX6_9", + "CMT_TOP_NE2A0_13", + "CMT_TOP_WL1END2_15", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_IMUX20_1", + "CMT_TOP_LH1_13", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_WL1END2_14", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B3_15", + "CMT_TOP_WW4C1_15", + "CMT_TOP_WW4C3_0", + "CMT_TOP_EL1BEG2_14", + "CMT_TOP_EE4A3_15", + "CMT_TOP_FAN4_3", + "CMT_TOP_NW4END1_12", + "CMT_TOP_WR1END3_2", + "CMT_TOP_SE2A2_9", + "CMT_TOP_WW4B3_11", + "CMT_TOP_IMUX5_7", + "CMT_TOP_OCLKDIV_14", + "CMT_TOP_LH7_11", + "CMT_TOP_FAN7_10", + "CMT_TOP_IMUX22_11", + "CMT_TOP_LH12_13", + "CMT_TOP_IMUX40_10", + "CMT_TOP_SE4C3_14", + "CMT_TOP_WW2A2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_WR1END0_14", + "CMT_TOP_WW2END0_4", + "CMT_TOP_NW2A2_1", + "CMT_TOP_EE4A1_9", + "CMT_TOP_NE4C3_6", + "CMT_TOP_OCLK_7", + "CMT_TOP_LOGIC_OUTS_L_B4_14", + "CMT_TOP_IMUX20_14", + "CMT_TOP_ER1BEG2_0", + "CMT_TOP_NW4A2_3", + "CMT_TOP_EE2BEG1_10", + "CMT_MMCM_PHASERREF_BELOW1", + "CMT_TOP_EE2BEG0_12", + "CMT_TOP_WW4C3_3", + "CMT_TOP_NW4END1_4", + "CMT_TOP_NW2A1_2", + "CMT_TOP_EE4BEG0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_TOP_WW4END0_7", + "CMT_TOP_SW2A3_13", + "CMT_TOP_SW4A3_2", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_IMUX5_8", + "CMT_LR_LOWER_B_MMCM_TESTIN13", + "CMT_TOP_WW4A1_11", + "CMT_TOP_SW4A1_5", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_MONITOR_N_11", + "CMT_TOP_IMUX32_6", + "CMT_TOP_SE2A2_12", + "CMT_TOP_NW4A2_14", + "CMT_TOP_NW2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_WW4B2_13", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_WW4B0_10", + "CMT_TOP_WW4A1_0", + "CMT_TOP_SW4END2_14", + "CMT_TOP_LH1_14", + "CMT_TOP_EE2A3_6", + "CMT_TOP_WR1END2_10", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_BYP0_6", + "CMT_LR_LOWER_B_MMCM_TESTIN0", + "CMT_TOP_WL1END1_5", + "CMT_TOP_IMUX30_0", + "CMT_TOP_LOGIC_OUTS_L_B5_9", + "CMT_LR_LOWER_B_MMCM_TESTIN7", + "CMT_TOP_NE4C2_13", + "CMT_TOP_NW2A0_8", + "CMT_TOP_WW4C1_5", + "CMT_TOP_SE4BEG2_11", + "CMT_TOP_NW4A3_11", + "CMT_TOP_WW4C3_12", + "CMT_TOP_IMUX34_6", + "CMT_TOP_SW4A2_4", + "CMT_TOP_NE4C3_1", + "CMT_TOP_NW4A1_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT59", + "CMT_TOP_IMUX22_6", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX1_4", + "CMT_MMCM_A_WRCLK_TOFIFO", + "CMT_TOP_SW4A1_0", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_IMUX41_9", + "CMT_TOP_FAN2_2", + "CMT_TOP_IMUX33_4", + "CMT_TOP_SE4C0_8", + "CMT_TOP_EE2BEG0_11", + "CMT_TOP_NE4BEG3_12", + "CMT_TOP_IMUX32_8", + "CMT_TOP_FAN0_15", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_EE2BEG1_3", + "CMT_TOP_EE2A2_4", + "CMT_TOP_WW4B2_7", + "CMT_TOP_EE4B1_3", + "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "CMT_TOP_SW4END0_0", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH10_2", + "CMT_TOP_IMUX4_8", + "CMT_TOP_NE4C1_11", + "CMT_TOP_WW2A1_1", + "CMT_TOP_WW4END0_13", + "CMT_TOP_EE4A1_0", + "CMT_LR_LOWER_B_MMCM_DI10", + "CMT_LR_LOWER_B_MMCM_DI1", + "CMT_TOP_IMUX9_6", + "CMT_TOP_IMUX42_3", + "CMT_TOP_IMUX13_10", + "CMT_TOP_IMUX20_15", + "CMT_TOP_WR1END0_6", + "CMT_TOP_OCLK1X_90_11", + "CMT_TOP_BYP6_15", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_TOP_IMUX0_13", + "CMT_TOP_IMUX22_2", + "CMT_LR_LOWER_B_MMCM_DI6", + "CMT_TOP_IMUX15_13", + "CMT_TOP_SE4C3_6", + "CMT_TOP_IMUX44_4", + "CMT_TOP_SE2A0_14", + "CMT_TOP_LH8_13", + "CMT_TOP_CTRL0_1", + "CMT_TOP_IMUX29_10", + "CMT_TOP_IMUX12_11", + "CMT_TOP_WW4B2_0", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_BLOCK_OUTS_L_B3_14", + "CMT_TOP_LH12_5", + "CMT_TOP_NE4BEG3_11", + "CMT_R_LOWER_B_CLK_FREQ_BB0", + "CMT_TOP_IMUX12_6", + "CMT_TOP_IMUX23_4", + "CMT_TOP_NE4BEG1_5", + "CMT_TOP_IMUX43_13", + "CMT_TOP_NE2A3_6", + "CMT_TOP_ICLK_3", + "CMT_TOP_IMUX7_4", + "CMT_TOP_CLK0_4", + "CMT_TOP_SE2A3_4", + "CMT_TOP_NE2A3_11", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_IMUX28_6", + "CMT_TOP_WW4A3_8", + "CMT_TOP_EE2A0_0", + "CMT_TOP_SE2A1_0", + "CMT_TOP_LH12_10", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_WW4B1_2", + "CMT_TOP_CTRL1_3", + "CMT_TOP_IMUX30_14", + "CMT_TOP_OCLK1X_90_12", + "CMT_TOP_EE4A3_8", + "CMT_TOP_NW4A0_2", + "CMT_TOP_IMUX26_5", + "CMT_TOP_OCLK1X_90_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT19", + "CMT_TOP_IMUX27_10", + "CMT_TOP_EE4BEG3_10", + "CMT_TOP_LH6_3", + "CMT_TOP_IMUX40_6", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_WR1END2_4", + "CMT_TOP_WW4C1_11", + "CMT_TOP_IMUX20_4", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_TOP_LOGIC_OUTS_L_B11_14", + "CMT_TOP_WW4END2_7", + "CMT_TOP_BYP4_7", + "CMT_TOP_FAN4_11", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_TOP_LOGIC_OUTS_L_B20_15", + "CMT_TOP_NE2A2_8", + "CMT_TOP_NW4A2_15", + "CMT_TOP_LOGIC_OUTS_L_B20_13", + "CMT_TOP_IMUX34_0", + "CMT_TOP_SE4C0_9", + "CMT_TOP_NE2A1_6", + "CMT_TOP_NE4BEG3_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT42", + "CMT_TOP_LOGIC_OUTS_L_B7_12", + "CMT_TOP_IMUX2_9", + "CMT_TOP_IMUX0_8", + "CMT_TOP_IMUX31_6", + "CMT_TOP_IMUX36_10", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_TOP_WW4END3_7", + "CMT_TOP_WL1END0_9", + "CMT_TOP_LOGIC_OUTS_L_B2_13", + "CMT_LR_LOWER_B_MMCM_TESTOUT37", + "CMT_TOP_EE4A0_15", + "CMT_TOP_SW4A0_1", + "CMT_TOP_WW2END1_13", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE2A2_1", + "CMT_TOP_SW2A3_11", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_IMUX43_15", + "CMT_TOP_WW2END0_13", + "CMT_TOP_SW2A1_5", + "CMT_TOP_BLOCK_OUTS_L_B2_10", + "CMT_TOP_CTRL1_8", + "CMT_TOP_OCLK1X_90_9", + "CMT_TOP_NW4A2_5", + "CMT_TOP_NW4A0_0", + "CMT_TOP_WW2A1_10", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_IMUX41_1", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX11_7", + "CMT_TOP_IMUX1_12", + "CMT_TOP_NE4C3_14", + "CMT_TOP_NE4C2_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT38", + "CMT_TOP_IMUX14_3", + "CMT_TOP_IMUX17_1", + "CMT_TOP_WW4A2_4", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_ICLKDIV_10", + "CMT_TOP_IMUX4_1", + "CMT_TOP_IMUX23_1", + "CMT_TOP_NW4A0_3", + "CMT_TOP_NW2A1_13", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_TOP_IMUX17_9", + "CMT_TOP_EE2A0_2", + "CMT_TOP_IMUX19_14", + "CMT_TOP_LOGIC_OUTS_L_B21_11", + "CMT_TOP_WW4A3_12", + "CMT_TOP_LH11_13", + "CMT_TOP_WW4END3_3", + "CMT_TOP_SE4C2_14", + "CMT_TOP_LH2_6", + "CMT_TOP_WW4B1_9", + "CMT_TOP_WR1END2_11", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_LR_LOWER_B_MMCM_PSEN", + "CMT_TOP_IMUX32_11", + "CMT_TOP_BYP2_8", + "CMT_TOP_WW4A0_0", + "CMT_TOP_WR1END3_5", + "CMT_TOP_SE4BEG1_3", + "CMT_TOP_IMUX5_13", + "CMT_TOP_WW4A1_13", + "CMT_TOP_WW4A2_13", + "CMT_MMCM_PHASERA_DQSBUS1", + "CMT_TOP_WW4END3_2", + "CMT_TOP_EE2BEG3_13", + "CMT_TOP_WL1END3_3", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_IMUX34_8", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_CTRL0_7", + "CMT_TOP_IMUX43_9", + "CMT_TOP_WW2END1_12", + "CMT_TOP_IMUX13_1", + "CMT_TOP_IMUX11_1", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_SE2A2_3", + "CMT_TOP_NE2A3_4", + "CMT_TOP_OCLKDIV_11", + "CMT_TOP_EE4C2_6", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_SW2A0_5", + "CMT_TOP_SW2A3_10", + "CMT_TOP_LH7_9", + "CMT_TOP_CTRL1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_TOP_IMUX24_12", + "CMT_TOP_LH8_5", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_EE4BEG3_13", + "CMT_TOP_WR1END0_13", + "CMT_TOP_EE2BEG0_13", + "CMT_TOP_WL1END3_6", + "CMT_TOP_LH1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_14", + "CMT_TOP_IMUX4_7", + "CMT_TOP_WW4END2_10", + "CMT_TOP_IMUX24_4", + "CMT_TOP_BYP7_9", + "CMT_TOP_LOGIC_OUTS_L_B8_13", + "CMT_TOP_SE4BEG2_12", + "CMT_TOP_FAN2_9", + "CMT_TOP_IMUX6_14", + "CMT_TOP_LOGIC_OUTS_L_B15_11", + "CMT_TOP_WW4A1_9", + "CMT_TOP_IMUX29_13", + "CMT_TOP_EE2BEG0_15", + "CMT_TOP_EE4C2_11", + "CMT_TOP_IMUX19_1", + "CMT_TOP_LOGIC_OUTS_L_B23_10", + "CMT_TOP_FAN2_8", + "CMT_TOP_NW2A1_9", + "CMT_TOP_EE4A3_14", + "CMT_TOP_LOGIC_OUTS_L_B8_11", + "CMT_TOP_EL1BEG0_15", + "CMT_TOP_IMUX3_15", + "CMT_TOP_SE4C2_7", + "CMT_TOP_LH5_9", + "CMT_TOP_LOGIC_OUTS_L_B14_15", + "CMT_TOP_IMUX0_14", + "CMT_TOP_BYP6_14", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH7_2", + "CMT_TOP_IMUX41_14", + "CMT_TOP_IMUX13_6", + "CMT_TOP_NW2A1_15", + "CMT_TOP_IMUX32_13", + "CMT_TOP_IMUX1_1", + "CMT_TOP_IMUX4_11", + "CMT_TOP_LH3_8", + "CMT_TOP_LOGIC_OUTS_L_B5_12", + "CMT_TOP_EE4C3_3", + "CMT_TOP_SW4A0_0", + "CMT_TOP_SW2A1_8", + "CMT_TOP_IMUX5_9", + "CMT_TOP_IMUX46_0", + "CMT_TOP_IMUX6_13", + "CMT_TOP_IMUX3_0", + "CMT_TOP_IMUX17_12", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_TOP_SE4C2_15", + "CMT_TOP_EE4C2_0", + "CMT_TOP_IMUX16_1", + "CMT_TOP_SW4END2_5", + "CMT_TOP_IMUX16_0", + "CMT_TOP_SE4C0_13", + "CMT_TOP_EE2A1_0", + "CMT_TOP_NW4END0_4", + "CMT_TOP_IMUX12_7", + "CMT_TOP_FAN3_14", + "CMT_TOP_NW4A0_9", + "CMT_TOP_ER1BEG0_14", + "CMT_TOP_WR1END1_3", + "CMT_TOP_IMUX42_9", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_IMUX47_5", + "CMT_LR_LOWER_B_MMCM_TESTOUT40", + "CMT_TOP_IMUX31_2", + "CMT_TOP_LOGIC_OUTS_L_B10_13", + "CMT_TOP_WR1END0_9", + "CMT_TOP_IMUX17_5", + "CMT_TOP_WW4END3_11", + "CMT_TOP_CLK1_3", + "CMT_TOP_WR1END1_14", + "CMT_TOP_ICLKDIV_11", + "CMT_R_LOWER_B_CLK_IN2_HCLK", + "CMT_TOP_SE2A1_9", + "CMT_TOP_EE2A3_2", + "CMT_TOP_LH12_9", + "CMT_LR_LOWER_B_MMCM_CLKOUT6", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_SE4C0_11", + "CMT_TOP_SE4C1_10", + "CMT_TOP_SE4C3_8", + "CMT_TOP_EE4BEG0_12", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_IMUX8_15", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_TOP_WW4B1_14", + "CMT_TOP_FAN6_13", + "CMT_TOP_IMUX43_11", + "CMT_TOP_IMUX39_1", + "CMT_TOP_LH1_3", + "CMT_TOP_BYP5_7", + "CMT_TOP_IMUX6_11", + "CMT_TOP_IMUX47_8", + "CMT_TOP_IMUX36_0", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_NW4A2_2", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_IMUX26_9", + "CMT_TOP_IMUX46_10", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END1_6", + "CMT_TOP_SW4A2_15", + "CMT_TOP_WL1END1_8", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_LOGIC_OUTS_L_B18_15", + "CMT_TOP_WW2END1_6", + "CMT_TOP_WW4END0_6", + "CMT_TOP_SE2A2_6", + "CMT_TOP_EE2BEG2_13", + "CMT_TOP_WW4A3_11", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_FAN5_0", + "CMT_TOP_WW2END0_14", + "CMT_TOP_LOGIC_OUTS_L_B3_11", + "CMT_TOP_WW4END3_13", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_IMUX7_2", + "CMT_TOP_SW4A3_11", + "CMT_TOP_SE2A3_10", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_FAN4_12", + "CMT_TOP_LH2_0", + "CMT_TOP_SE2A0_6", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LH9_2", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_EE4A2_13", + "CMT_TOP_EL1BEG0_14", + "CMT_TOP_WW4END1_13", + "CMT_LR_LOWER_B_MMCM_DO12", + "CMT_TOP_LOGIC_OUTS_L_B4_9", + "CMT_TOP_WW2A3_1", + "CMT_TOP_LH5_3", + "CMT_TOP_NE2A0_6", + "CMT_TOP_FAN4_1", + "CMT_TOP_WR1END2_15", + "CMT_TOP_IMUX24_15", + "CMT_TOP_LH12_1", + "CMT_TOP_LH8_6", + "CMT_TOP_IMUX36_5", + "CMT_TOP_OCLK_6", + "CMT_TOP_SW4END1_5", + "CMT_TOP_IMUX47_15", + "CMT_TOP_LOGIC_OUTS_L_B1_9", + "CMT_TOP_NW4END0_12", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_LR_LOWER_B_MMCM_DADDR4", + "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", + "CMT_TOP_FAN6_6", + "CMT_TOP_NE2A2_7", + "CMT_TOP_SW4A3_13", + "CMT_TOP_LH7_6", + "CMT_TOP_WW4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX45_3", + "CMT_TOP_IMUX16_12", + "CMT_TOP_NE4BEG1_10", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_WR1END1_10", + "CMT_TOP_LOGIC_OUTS_L_B16_10", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_SW2A0_3", + "CMT_TOP_NE4C1_12", + "CMT_TOP_EE4C0_7", + "CMT_TOP_NW2A0_11", + "CMT_TOP_IMUX12_12", + "CMT_TOP_NW4END1_6", + "CMT_TOP_BYP7_13", + "CMT_TOP_IMUX34_11", + "CMT_TOP_IMUX38_4", + "CMT_TOP_FAN6_7", + "CMT_TOP_EE4BEG1_11", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_IMUX41_5", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_SW4END2_3", + "CMT_TOP_NW2A3_13", + "CMT_TOP_LH5_13", + "CMT_TOP_EE2BEG3_8", + "CMT_TOP_LH9_7", + "CMT_TOP_IMUX4_12", + "CMT_TOP_WW4A1_1", + "CMT_TOP_WR1END0_3", + "CMT_TOP_WL1END3_14", + "CMT_TOP_FAN2_7", + "CMT_TOP_LH1_6", + "CMT_TOP_BYP7_6", + "CMT_TOP_LOGIC_OUTS_L_B2_14", + "CMT_TOP_IMUX40_11", + "CMT_TOP_NW4A1_5", + "CMT_TOP_IMUX18_14", + "CMT_TOP_CTRL0_13", + "CMT_TOP_IMUX8_13", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_1", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_IMUX2_10", + "CMT_TOP_IMUX32_10", + "CMT_MMCM_PHASERREF1", + "CMT_TOP_FAN6_8", + "CMT_TOP_EE4BEG1_10", + "CMT_TOP_IMUX39_12", + "CMT_TOP_NE2A1_13", + "CMT_TOP_NW4A2_4", + "CMT_TOP_WW4C2_4", + "CMT_TOP_LOGIC_OUTS_L_B11_9", + "CMT_TOP_LH6_5", + "CMT_TOP_FAN5_7", + "CMT_TOP_BYP2_12", + "CMT_TOP_OCLK_2", + "CMT_LR_LOWER_B_MMCM_TESTOUT20", + "CMT_TOP_WL1END1_6", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_BYP6_0", + "CMT_LR_LOWER_B_MMCM_CLKOUT1B", + "CMT_TOP_WL1END3_9", + "CMT_TOP_EE2BEG2_6", + "CMT_TOP_WW4B3_15", + "CMT_TOP_WW2END3_9", + "CMT_TOP_IMUX25_9", + "CMT_TOP_NW4END1_7", + "CMT_TOP_EE2A1_4", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_IMUX33_6", + "CMT_TOP_LH2_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT34", + "CMT_TOP_NW4A2_6", + "CMT_TOP_EE2BEG3_15", + "CMT_TOP_NE4C1_6", + "CMT_TOP_IMUX8_9", + "CMT_TOP_SW2A1_12", + "CMT_TOP_NE2A0_3", + "CMT_TOP_SE4C3_7", + "CMT_TOP_IMUX34_10", + "CMT_TOP_LOGIC_OUTS_L_B5_13", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_IMUX31_1", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_WW4C3_7", + "CMT_TOP_ICLKDIV_15", + "CMT_TOP_IMUX32_9", + "CMT_TOP_IMUX8_4", + "CMT_TOP_WW2END2_13", + "CMT_TOP_WR1END1_13", + "CMT_TOP_NW2A2_10", + "CMT_LR_LOWER_B_MMCM_DI9", + "CMT_TOP_IMUX33_1", + "CMT_TOP_IMUX32_12", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_BYP0_12", + "CMT_TOP_WW4END1_3", + "CMT_TOP_FAN1_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT41", + "CMT_TOP_SW2A0_1", + "CMT_TOP_FAN5_14", + "CMT_TOP_IMUX37_14", + "CMT_TOP_IMUX33_8", + "CMT_TOP_NW4A1_3", + "CMT_TOP_LH10_0", + "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "CMT_TOP_LH5_6", + "CMT_TOP_WW4B2_1", + "CMT_TOP_EE4C1_15", + "CMT_TOP_IMUX7_5", + "CMT_TOP_EE4C2_1", + "CMT_TOP_NE2A3_9", + "CMT_TOP_ER1BEG2_5", + "CMT_TOP_NW2A3_11", + "CMT_TOP_SW4A2_12", + "CMT_TOP_EE4BEG1_5", + "CMT_TOP_EE4BEG2_15", + "CMT_TOP_EE2A1_3", + "CMT_TOP_EE4C2_4", + "CMT_TOP_WW4C1_14", + "CMT_LR_LOWER_B_MMCM_CLKOUT0B", + "CMT_TOP_SW4A2_3", + "CMT_R_LOWER_B_CLK_IN3_HCLK", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_NE4C3_7", + "CMT_TOP_IMUX12_2", + "CMT_TOP_WW4B1_8", + "CMT_TOP_SE2A1_11", + "CMT_TOP_NW4A2_12", + "CMT_TOP_LH6_12", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_IMUX3_9", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_LR_LOWER_B_MMCM_TMUXOUT", + "CMT_TOP_IMUX21_3", + "CMT_TOP_LH4_11", + "CMT_TOP_EE4A2_3", + "CMT_TOP_LH1_11", + "CMT_TOP_SW4A2_6", + "CMT_TOP_IMUX35_8", + "CMT_TOP_IMUX9_0", + "CMT_TOP_SW4END0_11", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_WW2A3_12", + "CMT_TOP_NW4END2_15", + "CMT_TOP_IMUX16_4", + "CMT_TOP_IMUX39_11", + "CMT_TOP_LH2_4", + "CMT_TOP_LOGIC_OUTS_L_B14_9", + "CMT_TOP_WW4C0_2", + "CMT_TOP_LOGIC_OUTS_L_B3_13", + "CMT_TOP_CTRL1_11", + "CMT_TOP_EE4B2_11", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_EE2A0_12", + "CMT_TOP_LH3_6", + "CMT_TOP_LH7_15", + "CMT_TOP_WW4A0_12", + "CMT_TOP_EE4C3_0", + "CMT_LR_LOWER_B_MMCM_TESTIN22", + "CMT_TOP_IMUX40_1", + "CMT_TOP_CLK0_10", + "CMT_TOP_EE4B0_10", + "CMT_TOP_WW4C2_13", + "CMT_TOP_MONITOR_P_13", + "CMT_MMCM_PHYCTRL_SYNC_BB_DN", + "CMT_TOP_WW4C3_11", + "CMT_TOP_IMUX20_11", + "CMT_TOP_FAN7_9", + "CMT_TOP_IMUX29_15", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_ER1BEG0_12", + "CMT_TOP_IMUX32_2", + "CMT_TOP_LH1_4", + "CMT_TOP_IMUX14_14", + "CMT_TOP_BYP1_11", + "CMT_TOP_BYP0_1", + "CMT_TOP_FAN3_10", + "CMT_TOP_NE4C0_6", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_IMUX24_1", + "CMT_TOP_IMUX12_1", + "CMT_LR_LOWER_B_MMCM_TESTOUT13", + "CMT_TOP_IMUX29_3", + "CMT_TOP_IMUX18_0", + "CMT_TOP_SW2A0_6", + "CMT_TOP_FAN7_6", + "CMT_TOP_LOGIC_OUTS_L_B21_10", + "CMT_TOP_IMUX24_11", + "CMT_TOP_LH1_15", + "CMT_TOP_EE4A0_3", + "CMT_TOP_NE4C3_12", + "CMT_TOP_SW2A3_6", + "CMT_TOP_IMUX10_10", + "CMT_TOP_WW4B1_15", + "CMT_TOP_BLOCK_OUTS_L_B2_11", + "CMT_TOP_NE4C1_15", + "CMT_TOP_IMUX44_11", + "CMT_LR_LOWER_B_MMCM_TESTIN1", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_BLOCK_OUTS_L_B0_13", + "CMT_TOP_NW2A0_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT28", + "CMT_TOP_WR1END2_5", + "CMT_TOP_ER1BEG3_12", + "CMT_TOP_BYP5_3", + "CMT_TOP_NW4END2_14", + "CMT_TOP_NW4A2_1", + "CMT_TOP_FAN5_6", + "CMT_TOP_IMUX32_4", + "CMT_TOP_LH6_11", + "CMT_TOP_LOGIC_OUTS_L_B16_12", + "CMT_TOP_LOGIC_OUTS_L_B3_12", + "CMT_TOP_SE4BEG3_9", + "CMT_TOP_LOGIC_OUTS_L_B17_13", + "CMT_TOP_EE4C3_1", + "CMT_TOP_CTRL0_3", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_TOP_LH5_11", + "CMT_TOP_SE4BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_SW4END1_7", + "CMT_TOP_NW4A3_10", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_LR_LOWER_B_MMCM_DI14", + "CMT_TOP_WW2END3_14", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_IMUX6_5", + "CMT_TOP_WW4A3_5", + "CMT_TOP_NE2A2_13", + "CMT_TOP_IMUX42_15", + "CMT_TOP_NE4BEG2_7", + "CMT_MMCM_PHASERREF_ABOVE0", + "CMT_TOP_LOGIC_OUTS_L_B18_13", + "CMT_TOP_EE4A1_12", + "CMT_TOP_BYP3_9", + "CMT_TOP_IMUX26_2", + "CMT_TOP_SW2A1_13", + "CMT_TOP_IMUX20_10", + "CMT_TOP_IMUX13_4", + "CMT_LR_LOWER_B_MMCM_PSINCDEC", + "CMT_TOP_IMUX4_15", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_NW4END2_12", + "CMT_TOP_WW4C3_8", + "CMT_TOP_NE2A0_8", + "CMT_TOP_LH6_4", + "CMT_TOP_NW2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B10_15", + "CMT_TOP_IMUX20_9", + "CMT_TOP_WW2END3_6", + "CMT_TOP_FAN6_10", + "CMT_TOP_EE4B2_9", + "CMT_TOP_WW4B1_1", + "CMT_TOP_WW4B1_7", + "CMT_TOP_WW2A3_4", + "CMT_TOP_NW4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_IMUX9_11", + "CMT_TOP_BYP7_3", + "CMT_TOP_SW4A2_14", + "CMT_TOP_IMUX25_0", + "CMT_TOP_NE4C2_8", + "CMT_TOP_IMUX41_0", + "CMT_TOP_WL1END2_9", + "CMT_TOP_FAN0_14", + "CMT_TOP_LH4_4", + "CMT_TOP_WW4B3_12", + "CMT_TOP_IMUX24_3", + "CMT_LR_LOWER_B_MMCM_DO10", + "CMT_TOP_IMUX14_13", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_LOGIC_OUTS_L_B14_12", + "CMT_TOP_BLOCK_OUTS_L_B1_13", + "CMT_TOP_EE4C3_12", + "CMT_TOP_LOGIC_OUTS_L_B17_14", + "CMT_TOP_NE4BEG2_14", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_NW2A0_4", + "CMT_TOP_EE2A1_2", + "CMT_TOP_WW4C3_14", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX46_3", + "CMT_TOP_WW2END3_11", + "CMT_TOP_CLK1_11", + "CMT_TOP_LOGIC_OUTS_L_B13_15", + "CMT_TOP_EE4A2_0", + "CMT_TOP_SE2A2_4", + "CMT_TOP_IMUX29_11", + "CMT_TOP_EE4A0_7", + "CMT_TOP_WW4C2_3", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_IMUX32_3", + "CMT_TOP_BLOCK_OUTS_L_B2_14", + "CMT_TOP_EE2A0_11", + "CMT_LR_LOWER_B_MMCM_TESTIN31", + "CMT_TOP_IMUX11_8", + "CMT_TOP_ER1BEG2_10", + "CMT_TOP_IMUX27_5", + "CMT_TOP_IMUX36_8", + "CMT_TOP_NW2A1_10", + "CMT_TOP_WL1END1_0", + "CMT_TOP_NW4A1_13", + "CMT_TOP_LH10_12", + "CMT_TOP_IMUX47_3", + "CMT_TOP_IMUX0_2", + "CMT_TOP_SE4BEG1_15", + "CMT_TOP_NW4END3_11", + "CMT_TOP_WW2A1_6", + "CMT_TOP_SW4A2_1", + "CMT_TOP_NW2A2_2", + "CMT_TOP_NW2A0_10", + "CMT_TOP_IMUX5_5", + "CMT_TOP_LOGIC_OUTS_L_B0_13", + "CMT_TOP_BLOCK_OUTS_L_B0_15", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4BEG1_4", + "CMT_TOP_WW4END3_9", + "CMT_TOP_SW4A1_12", + "CMT_LR_LOWER_B_MMCM_DI13", + "CMT_TOP_SE2A1_13", + "CMT_TOP_MONITOR_P_2", + "CMT_TOP_IMUX30_11", + "CMT_TOP_WW2A2_14", + "CMT_LR_LOWER_B_MMCM_PSDONE", + "CMT_TOP_LOGIC_OUTS_L_B15_14", + "CMT_TOP_WW4C3_1", + "CMT_TOP_IMUX33_5", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SE4C2_3", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_EE4A0_9", + "CMT_TOP_LH7_7", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_BYP6_10", + "CMT_TOP_NW4END3_1", + "CMT_R_LOWER_B_CLK_FREQ_BB2", + "CMT_TOP_IMUX13_15", + "CMT_TOP_EE4C0_14", + "CMT_TOP_EE2BEG3_10", + "CMT_TOP_WW2END0_5", + "CMT_TOP_LH5_1", + "CMT_TOP_FAN3_12", + "CMT_TOP_LH8_7", + "CMT_TOP_OCLK_11", + "CMT_TOP_FAN6_5", + "CMT_TOP_IMUX22_15", + "CMT_TOP_IMUX27_1", + "CMT_TOP_NE4BEG2_1", + "CMT_TOP_WW2END1_15", + "CMT_TOP_SW4END0_13", + "CMT_TOP_SE2A2_8", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_SE4C3_10", + "CMT_TOP_WL1END2_5", + "CMT_TOP_IMUX15_12", + "CMT_TOP_WW2A2_9", + "CMT_TOP_SE2A3_9", + "CMT_TOP_SE2A2_14", + "CMT_TOP_IMUX14_8", + "CMT_TOP_FAN2_15", + "CMT_TOP_NW4END3_4", + "CMT_TOP_SW4END0_14", + "CMT_TOP_NE2A2_3", + "CMT_TOP_LH8_2", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_EE4A2_10", + "CMT_TOP_IMUX19_10", + "CMT_LR_LOWER_B_MMCM_PSCLK", + "CMT_TOP_LOGIC_OUTS_L_B16_13", + "CMT_TOP_FAN4_13", + "CMT_TOP_LOGIC_OUTS_L_B19_12", + "CMT_TOP_WR1END3_12", + "CMT_TOP_EE4BEG2_11", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_WW2END0_10", + "CMT_PHASER_A_ICLKDIV_TOIOI", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_SE2A3_2", + "CMT_TOP_ER1BEG3_10", + "CMT_TOP_CLK1_8", + "CMT_TOP_IMUX47_12", + "CMT_TOP_LOGIC_OUTS_L_B15_12", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_EL1BEG2_11", + "CMT_TOP_LH2_14", + "CMT_TOP_NW4A0_1", + "CMT_TOP_MONITOR_N_1", + "CMT_R_LOWER_B_CLK_FREQ_BB1", + "CMT_TOP_NW4END2_1", + "CMT_TOP_EE4B0_8", + "CMT_TOP_IMUX0_15", + "CMT_TOP_NW4END2_8", + "CMT_TOP_CLK0_6", + "CMT_TOP_WR1END2_6", + "CMT_TOP_WW4END0_1", + "CMT_TOP_FAN4_15", + "CMT_TOP_NW2A1_7", + "CMT_TOP_WW4A2_6", + "CMT_TOP_IMUX27_3", + "CMT_TOP_SW2A3_0", + "CMT_TOP_EE2A2_9", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_EE4A1_13", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_WR1END2_2", + "CMT_TOP_EE4BEG2_9", + "CMT_TOP_WW4END1_15", + "CMT_TOP_EE2A2_7", + "CMT_TOP_EE4B2_13", + "CMT_TOP_IMUX26_10", + "CMT_TOP_IMUX8_0", + "CMT_TOP_IMUX21_9", + "CMT_TOP_WW4C1_1", + "CMT_TOP_EE4A0_12", + "CMT_TOP_IMUX2_14", + "CMT_TOP_LOGIC_OUTS_L_B11_13", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_LH5_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4C2_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT8", + "CMT_TOP_BLOCK_OUTS_L_B2_12", + "CMT_TOP_SW4END1_14", + "CMT_TOP_EE2A2_11", + "CMT_TOP_WR1END0_8", + "CMT_TOP_WW4C0_10", + "CMT_TOP_WL1END1_4", + "CMT_TOP_WW4B1_6", + "CMT_TOP_EE4B3_14", + "CMT_LR_LOWER_B_MMCM_DO9", + "CMT_TOP_NW4A0_14", + "CMT_MMCM_PHASER_IN_A_ICLK", + "CMT_LR_LOWER_B_MMCM_CLKOUT2B", + "CMT_TOP_WW2A3_7", + "CMT_TOP_CTRL1_13", + "CMT_TOP_IMUX31_13", + "CMT_TOP_BYP3_6", + "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", + "CMT_TOP_EE4B1_8", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_IMUX9_1", + "CMT_LR_LOWER_B_MMCM_TESTOUT53", + "CMT_LR_LOWER_B_MMCM_TESTIN3", + "CMT_TOP_SE4C1_5", + "CMT_TOP_LH4_7", + "CMT_TOP_LOGIC_OUTS_L_B5_10", + "CMT_TOP_IMUX20_5", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_NE4C2_4", + "CMT_TOP_NE4BEG2_12", + "CMT_TOP_EE2A1_15", + "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "CMT_TOP_WW4B1_0", + "CMT_TOP_IMUX0_10", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_IMUX23_7", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_LR_LOWER_B_MMCM_TESTOUT0", + "CMT_TOP_SE4C1_12", + "CMT_TOP_EE4A2_7", + "CMT_TOP_FAN3_9", + "CMT_TOP_EE2A0_8", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_WW2A2_13", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_NW4END0_8", + "CMT_TOP_WW4B2_3", + "CMT_TOP_IMUX23_0", + "CMT_TOP_EE2BEG3_1", + "CMT_TOP_LH6_8", + "CMT_TOP_SW4END0_10", + "CMT_TOP_WW4A3_14", + "CMT_TOP_LH6_10", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_WL1END0_0", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_FAN0_2", + "CMT_TOP_EE2A1_14", + "CMT_TOP_LOGIC_OUTS_L_B10_10", + "CMT_TOP_LH2_11", + "CMT_TOP_WW2END2_0", + "CMT_TOP_IMUX18_3", + "CMT_TOP_IMUX6_10", + "CMT_TOP_BLOCK_OUTS_L_B0_12", + "CMT_TOP_FAN1_1", + "CMT_TOP_BLOCK_OUTS_L_B3_13", + "CMT_TOP_NW2A3_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT24", + "CMT_TOP_LH7_1", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_IMUX43_5", + "CMT_TOP_SE4BEG1_10", + "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", + "CMT_TOP_EE4B1_10", + "CMT_TOP_IMUX7_13", + "CMT_TOP_IMUX41_4", + "CMT_TOP_ER1BEG0_13", + "CMT_LR_LOWER_B_MMCM_TESTIN11", + "CMT_TOP_SE4C0_15", + "CMT_TOP_IMUX33_0", + "CMT_TOP_LOGIC_OUTS_L_B14_13", + "CMT_TOP_IMUX35_15", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_EE4B3_15", + "CMT_TOP_SE2A3_8", + "CMT_R_LOWER_B_CLK_PERF1", + "CMT_TOP_WW4C0_13", + "CMT_TOP_LOGIC_OUTS_L_B4_13", + "CMT_TOP_NE2A1_15", + "CMT_TOP_SE4C0_0", + "CMT_PHASER_A_OCLKDIV_TOIOI", + "CMT_TOP_BYP2_15", + "CMT_TOP_NE2A2_9", + "CMT_TOP_OCLKDIV_2", + "CMT_TOP_WW4C2_12", + "CMT_TOP_WW4B3_4", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX5_3", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_WW2A1_15", + "CMT_TOP_BYP2_9", + "CMT_TOP_IMUX23_10", + "CMT_TOP_LH5_0", + "CMT_TOP_WW2END2_15", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_IMUX42_10", + "CMT_TOP_LH10_10", + "CMT_TOP_WW4END2_11", + "CMT_TOP_EE4A1_4", + "CMT_TOP_NW4A1_10", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX11_0", + "CMT_TOP_CTRL0_15", + "CMT_TOP_WW2END3_5", + "CMT_TOP_LH7_8", + "CMT_TOP_LOGIC_OUTS_L_B9_14", + "CMT_LR_LOWER_B_MMCM_TESTIN10", + "CMT_TOP_NE4C1_3", + "CMT_TOP_CTRL1_6", + "CMT_TOP_WW4C2_11", + "CMT_TOP_CLK1_9", + "CMT_TOP_BYP3_13", + "CMT_TOP_IMUX31_3", + "CMT_TOP_IMUX37_3", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_LOGIC_OUTS_L_B18_11", + "CMT_TOP_LH7_13", + "CMT_TOP_WW4C0_0", + "CMT_TOP_WW4A0_5", + "CMT_TOP_LH9_12", + "CMT_TOP_EE4C3_9", + "CMT_TOP_IMUX3_8", + "CMT_TOP_NW4END1_11", + "CMT_TOP_WW2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B9_10", + "CMT_TOP_SE2A0_4", + "CMT_TOP_IMUX15_1", + "CMT_TOP_IMUX6_3", + "CMT_TOP_IMUX45_9", + "CMT_TOP_EE4B2_7", + "CMT_TOP_NW2A2_9", + "CMT_TOP_LH3_11", + "CMT_TOP_WR1END0_7", + "CMT_TOP_IMUX24_5", + "CMT_TOP_IMUX14_15", + "CMT_TOP_FAN2_1", + "CMT_TOP_LOGIC_OUTS_L_B2_15", + "CMT_TOP_IMUX5_6", + "CMT_TOP_NW4END0_10", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_NW4END1_9", + "CMT_TOP_SE4BEG0_9", + "CMT_TOP_SE4C0_14", + "CMT_TOP_WW4B2_15", + "CMT_TOP_BYP6_5", + "CMT_TOP_ER1BEG3_5", + "CMT_TOP_IMUX37_5", + "CMT_TOP_IMUX37_8", + "CMT_TOP_EE4C0_0", + "CMT_TOP_WW4END2_1", + "CMT_TOP_ICLK_13", + "CMT_TOP_IMUX9_14", + "CMT_TOP_EE4A1_6", + "CMT_TOP_LOGIC_OUTS_L_B12_10", + "CMT_TOP_SW4END1_0", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_IMUX35_3", + "CMT_TOP_SE4BEG0_12", + "CMT_TOP_WW4A2_3", + "CMT_TOP_IMUX10_4", + "CMT_TOP_LOGIC_OUTS_L_B13_9", + "CMT_TOP_BYP6_9", + "CMT_TOP_WW4END2_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT56", + "CMT_TOP_IMUX26_6", + "CMT_TOP_EE4A3_0", + "CMT_TOP_IMUX18_10", + "CMT_TOP_LOGIC_OUTS_L_B17_15", + "CMT_TOP_IMUX22_10", + "CMT_TOP_EE2A1_5", + "CMT_TOP_SW4END3_1", + "CMT_TOP_EL1BEG1_6", + "CMT_TOP_IMUX4_4", + "CMT_TOP_LOGIC_OUTS_L_B11_12", + "CMT_TOP_IMUX3_14", + "CMT_TOP_NW4END3_3", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_WW4C1_2", + "CMT_TOP_EE2A1_12", + "CMT_TOP_SW4A2_9", + "CMT_TOP_EL1BEG2_12", + "CMT_TOP_IMUX22_0", + "CMT_TOP_LOGIC_OUTS_L_B16_11", + "CMT_TOP_SE2A1_1", + "CMT_TOP_WL1END1_12", + "CMT_TOP_NW2A3_9", + "CMT_TOP_WR1END0_4", + "CMT_TOP_EE2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B18_14", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_WW4A1_10", + "CMT_TOP_EE4C0_6", + "CMT_TOP_IMUX24_0", + "CMT_TOP_EL1BEG1_4", + "CMT_TOP_ER1BEG3_14", + "CMT_TOP_LOGIC_OUTS_L_B6_12", + "CMT_TOP_WW4B3_10", + "CMT_LR_LOWER_B_MMCM_DEN", + "CMT_TOP_LOGIC_OUTS_L_B3_14", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_SW2A3_3", + "CMT_TOP_SW4END0_1", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_EE4B1_0", + "CMT_TOP_NE2A3_2", + "CMT_TOP_ER1BEG1_9", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_TOP_WW4C0_15", + "CMT_TOP_ICLK_12", + "CMT_TOP_EE4B1_6", + "CMT_TOP_LH3_9", + "CMT_TOP_BYP3_2", + "CMT_LR_LOWER_B_CLKFBOUT2IN", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_LH5_12", + "CMT_TOP_LOGIC_OUTS_L_B10_14", + "CMT_LR_LOWER_B_MMCM_DI7", + "CMT_TOP_SE4BEG1_9", + "CMT_TOP_IMUX34_9", + "CMT_TOP_CLK0_2", + "CMT_TOP_SE4C1_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT58", + "CMT_TOP_LH10_1", + "CMT_TOP_IMUX22_12", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_SE4BEG3_11", + "CMT_TOP_LOGIC_OUTS_L_B21_15", + "CMT_TOP_LOGIC_OUTS_L_B10_11", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_FAN3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_TOP_WW4A0_9", + "CMT_TOP_SW2A1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_EE4BEG1_15", + "CMT_LR_LOWER_B_MMCM_DI5", + "CMT_TOP_IMUX3_4", + "CMT_TOP_ICLK_5", + "CMT_TOP_IMUX47_9", + "CMT_TOP_IMUX15_9", + "CMT_TOP_LH12_12", + "CMT_TOP_IMUX31_0", + "CMT_TOP_LH4_14", + "CMT_TOP_IMUX29_8", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_LH2_3", + "CMT_TOP_WR1END1_9", + "CMT_TOP_IMUX28_10", + "CMT_TOP_NE4C1_4", + "CMT_TOP_WW2END3_15", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_IMUX2_4", + "CMT_TOP_IMUX38_11", + "CMT_TOP_EE4C1_1", + "CMT_TOP_SW2A0_4", + "CMT_LR_LOWER_B_MMCM_TESTIN26", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_LH8_4", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_WW4END2_0", + "CMT_TOP_EE4C0_1", + "CMT_TOP_IMUX33_11", + "CMT_TOP_FAN5_8", + "CMT_TOP_WW4C1_0", + "CMT_TOP_LOGIC_OUTS_L_B11_11", + "CMT_TOP_EE2A3_9", + "CMT_TOP_WW4B0_15", + "CMT_TOP_LH10_7", + "CMT_TOP_IMUX37_13", + "CMT_TOP_SE4C0_1", + "CMT_TOP_NW4END3_9", + "CMT_TOP_WW4C1_7", + "CMT_TOP_SE2A0_5", + "CMT_TOP_EE2BEG1_9", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_WW2A3_13", + "CMT_LR_LOWER_B_MMCM_CLKIN1", + "CMT_TOP_ER1BEG3_9", + "CMT_TOP_CLK1_15", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_IMUX47_11", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LH10_14", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_NW4END0_15", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_WR1END2_14", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BYP0_0", + "CMT_TOP_EE4B2_2", + "CMT_TOP_FAN7_7", + "CMT_TOP_NW4END2_13", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_WW4A0_4", + "CMT_TOP_EE4B3_13", + "CMT_TOP_WW4B0_12", + "CMT_TOP_IMUX4_13", + "CMT_TOP_WW4A3_0", + "CMT_TOP_SE4C1_1", + "CMT_TOP_ER1BEG0_6", + "CMT_TOP_IMUX46_1", + "CMT_TOP_FAN6_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT35", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_IMUX30_8", + "CMT_TOP_SW2A1_0", + "CMT_TOP_CLK0_1", + "CMT_TOP_BYP5_4", + "CMT_TOP_IMUX45_2", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_WW4C2_6", + "CMT_TOP_IMUX19_5", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_SE2A1_15", + "CMT_R_LOWER_B_CLK_MMCM4", + "CMT_TOP_NW4END0_1", + "CMT_TOP_IMUX35_12", + "CMT_TOP_LH3_10", + "CMT_TOP_LH9_8", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_TOP_LH12_14", + "CMT_TOP_NW2A2_7", + "CMT_TOP_MONITOR_N_15", + "CMT_TOP_LH11_12", + "CMT_TOP_SW4END0_5", + "CMT_TOP_IMUX29_1", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_IMUX9_5", + "CMT_TOP_SW4A0_2", + "CMT_TOP_WW2END1_5", + "CMT_TOP_WW2A2_8", + "CMT_TOP_WW4A1_12", + "CMT_TOP_OCLK_8", + "CMT_TOP_CLK1_14", + "CMT_TOP_IMUX46_7", + "CMT_TOP_EE4C1_12", + "CMT_TOP_IMUX44_15", + "CMT_LR_LOWER_B_MMCM_DI3", + "CMT_TOP_IMUX8_3", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_IMUX14_7", + "CMT_TOP_NE4BEG2_13", + "CMT_TOP_NW2A2_0", + "CMT_TOP_SE4C0_5", + "CMT_TOP_SW4END3_4", + "CMT_TOP_SE2A2_7", + "CMT_TOP_SW2A1_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_IMUX22_8", + "CMT_TOP_IMUX9_13", + "CMT_TOP_LH3_7", + "CMT_TOP_IMUX30_15", + "CMT_TOP_IMUX1_11", + "CMT_TOP_EE4BEG2_13", + "CMT_TOP_SE2A1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_9", + "CMT_TOP_IMUX43_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT57", + "CMT_TOP_LH10_5", + "CMT_TOP_EE4C0_13", + "CMT_TOP_NE4BEG2_5", + "CMT_TOP_BYP3_15", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_BLOCK_OUTS_L_B3_10", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_NE2A0_0", + "CMT_TOP_NE2A2_6", + "CMT_TOP_SW2A3_12", + "CMT_TOP_NE2A1_12", + "CMT_TOP_NE4C1_14", + "CMT_TOP_WW4C2_9", + "CMT_TOP_SW2A2_2", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_LH11_1", + "CMT_TOP_EE2A1_11", + "CMT_R_LOWER_B_CLK_IN1_HCLK", + "CMT_TOP_BLOCK_OUTS_L_B2_13", + "CMT_TOP_IMUX40_13", + "CMT_MMCM_A_RDCLK_TOFIFO", + "CMT_TOP_EE4C3_14", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_LOGIC_OUTS_L_B20_10", + "CMT_TOP_WW2A2_4", + "CMT_TOP_EE4C1_10", + "CMT_TOP_LH5_2", + "CMT_TOP_IMUX17_8", + "CMT_TOP_IMUX41_15", + "CMT_TOP_EE4BEG1_12", + "CMT_TOP_EE2BEG1_13", + "CMT_TOP_IMUX46_15", + "CMT_TOP_IMUX36_7", + "CMT_TOP_FAN0_13", + "CMT_TOP_SW4END3_13", + "CMT_TOP_BYP1_7", + "CMT_TOP_IMUX4_5", + "CMT_TOP_IMUX36_12", + "CMT_LR_LOWER_B_MMCM_DI11", + "CMT_TOP_EE4C0_4", + "CMT_TOP_IMUX26_15", + "CMT_TOP_EE2BEG2_14", + "CMT_TOP_EL1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B13_10", + "CMT_TOP_LOGIC_OUTS_L_B19_10", + "CMT_TOP_ICLK_7", + "CMT_TOP_SE4C3_15", + "CMT_TOP_NE4BEG0_10", + "CMT_TOP_LH11_3", + "CMT_TOP_SE4BEG0_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT45", + "CMT_TOP_IMUX32_1", + "CMT_TOP_SW2A2_4", + "CMT_TOP_IMUX11_4", + "CMT_TOP_IMUX9_10", + "CMT_TOP_EE4C3_7", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_WW4B3_0", + "CMT_TOP_ER1BEG2_15", + "CMT_TOP_IMUX10_5", + "CMT_TOP_EE4A1_14", + "CMT_TOP_WW2END1_1", + "CMT_TOP_FAN0_9", + "CMT_TOP_FAN1_7", + "CMT_TOP_IMUX23_2", + "CMT_TOP_IMUX5_0", + "CMT_TOP_ICLK_6", + "CMT_TOP_NW4A3_14", + "CMT_TOP_EE4A2_9", + "CMT_TOP_IMUX22_1", + "CMT_TOP_WW4B0_8", + "CMT_TOP_SW4A0_15", + "CMT_TOP_IMUX42_11", + "CMT_TOP_EE4B1_13", + "CMT_TOP_BYP2_14", + "CMT_TOP_OCLKDIV_6", + "CMT_TOP_SE4BEG3_14", + "CMT_TOP_LH2_9", + "CMT_TOP_NW4A3_1", + "CMT_TOP_IMUX27_0", + "CMT_TOP_SW2A2_14", + "CMT_TOP_SE4C2_8", + "CMT_LR_LOWER_B_MMCM_TESTIN25", + "CMT_TOP_WW2END0_9", + "CMT_TOP_SE4C2_4", + "CMT_TOP_SW2A2_15", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_EE2BEG3_12", + "CMT_TOP_SE2A2_1", + "CMT_TOP_NW4END1_5", + "CMT_TOP_EE2BEG0_7", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_NW4END0_14", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_WW2A0_12", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX14_10", + "CMT_TOP_WR1END0_12", + "CMT_TOP_IMUX42_7", + "CMT_TOP_IMUX32_14", + "CMT_TOP_EL1BEG0_9", + "CMT_TOP_LOGIC_OUTS_L_B22_15", + "CMT_TOP_IMUX41_11", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_IMUX33_15", + "CMT_TOP_IMUX34_12", + "CMT_TOP_WR1END1_11", + "CMT_TOP_IMUX35_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT60", + "CMT_TOP_SW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_WW4C1_13", + "CMT_TOP_FAN3_7", + "CMT_TOP_LH9_9", + "CMT_TOP_SW4A1_1", + "CMT_LR_LOWER_B_MMCM_TESTIN19", + "CMT_TOP_IMUX13_14", + "CMT_MMCM_PHASER_OUT_B_OCLK", + "CMT_TOP_SW2A0_8", + "CMT_TOP_IMUX28_9", + "CMT_TOP_EE4B3_7", + "CMT_TOP_WW2A3_11", + "CMT_TOP_IMUX44_3", + "CMT_TOP_IMUX31_10", + "CMT_LR_LOWER_B_MMCM_TESTIN15", + "CMT_TOP_EE4B3_10", + "CMT_TOP_WW2END2_12", + "CMT_TOP_NE4C1_9", + "CMT_TOP_SE2A0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_BYP2_3", + "CMT_TOP_IMUX12_10", + "CMT_TOP_IMUX40_3", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_LOGIC_OUTS_L_B22_14", + "CMT_TOP_IMUX11_6", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_IMUX39_10", + "CMT_TOP_LH3_13", + "CMT_TOP_BYP4_2", + "MMCM_CLK_FREQ_BB_REBUF0_NS", + "CMT_TOP_NW2A1_14", + "CMT_TOP_NE4BEG0_12", + "CMT_TOP_NE4BEG3_8", + "CMT_TOP_IMUX1_10", + "CMT_TOP_SE4BEG3_15", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_SW2A1_9", + "CMT_TOP_FAN6_15", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_IMUX26_7", + "CMT_TOP_IMUX1_7", + "CMT_TOP_IMUX23_6", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_FAN5_10", + "CMT_TOP_IMUX6_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT15", + "CMT_TOP_IMUX4_3", + "CMT_TOP_EE2A3_13", + "CMT_TOP_EE4C1_6", + "CMT_TOP_NW4END3_7", + "CMT_TOP_WW2END3_12", + "CMT_TOP_IMUX13_5", + "CMT_TOP_LOGIC_OUTS_L_B7_13", + "CMT_TOP_IMUX46_6", + "CMT_TOP_WW4END0_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LH12_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_CLK1_2", + "CMT_TOP_WW4C2_10", + "CMT_TOP_LOGIC_OUTS_L_B18_10", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_IMUX15_7", + "CMT_TOP_SW4END2_0", + "CMT_TOP_WW4B0_9", + "CMT_TOP_WW4END1_5", + "CMT_TOP_NW4A0_5", + "CMT_TOP_SW2A3_15", + "CMT_TOP_EE2A2_2", + "CMT_TOP_WW4A0_2", + "CMT_TOP_IMUX37_6", + "CMT_TOP_WL1END1_11", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_LH10_11", + "CMT_TOP_BYP5_13", + "CMT_TOP_IMUX0_0", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_NW2A3_4", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_EE2BEG1_15", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_IMUX42_6", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_BLOCK_OUTS_L_B3_15", + "CMT_TOP_LH3_1", + "CMT_TOP_EE2BEG3_11", + "CMT_TOP_WL1END3_11", + "CMT_TOP_ICLKDIV_14", + "CMT_LR_LOWER_B_MMCM_DADDR2", + "CMT_TOP_EE4C0_2", + "CMT_TOP_IMUX23_9", + "CMT_R_LOWER_B_CLK_PERF3", + "CMT_TOP_IMUX35_6", + "CMT_TOP_EL1BEG3_13", + "CMT_LR_LOWER_B_MMCM_TESTIN6", + "CMT_TOP_SE2A3_11", + "CMT_TOP_FAN3_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT48", + "CMT_TOP_SW4END2_1", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_EE4A2_11", + "CMT_TOP_LOGIC_OUTS_L_B17_9", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_TOP_IMUX36_13", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_WW2A1_3", + "CMT_TOP_FAN2_5", + "CMT_TOP_EE4BEG3_5", + "CMT_R_LOWER_B_CLK_MMCM5", + "CMT_TOP_LH4_13", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_TOP_WW2END1_8", + "CMT_TOP_WR1END2_0", + "CMT_TOP_NE2A1_0", + "CMT_TOP_BLOCK_OUTS_L_B3_12", + "CMT_TOP_LH1_8", + "CMT_TOP_LH11_14", + "CMT_TOP_WW2A0_7", + "CMT_TOP_FAN7_12", + "CMT_TOP_LOGIC_OUTS_L_B17_10", + "CMT_TOP_EE4BEG1_4", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_EE2BEG2_8", + "CMT_TOP_LOGIC_OUTS_L_B16_15", + "CMT_LR_LOWER_B_MMCM_DRDY", + "CMT_TOP_SW4END0_2", + "CMT_TOP_SW4A0_6", + "CMT_TOP_BYP5_8", + "CMT_TOP_FAN5_4", + "CMT_TOP_IMUX41_7", + "CMT_TOP_IMUX25_2", + "CMT_TOP_EE4A3_1", + "CMT_TOP_WR1END3_14", + "CMT_TOP_IMUX12_8", + "CMT_TOP_WW2A3_3", + "CMT_TOP_IMUX27_14", + "CMT_TOP_IMUX1_6", + "CMT_TOP_IMUX21_2", + "CMT_TOP_IMUX25_14", + "CMT_TOP_WW2A1_14", + "CMT_TOP_CLK1_1", + "CMT_TOP_IMUX27_12", + "CMT_TOP_WW4A2_0", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_TOP_WW4END3_10", + "CMT_TOP_IMUX16_9", + "CMT_TOP_FAN1_10", + "CMT_TOP_NE2A2_0", + "CMT_TOP_IMUX17_11", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_WW2END2_7", + "CMT_TOP_CTRL1_9", + "CMT_TOP_SE4BEG1_1", + "CMT_TOP_CTRL0_12", + "CMT_TOP_NW4END3_5", + "CMT_TOP_IMUX21_5", + "CMT_TOP_WW4END3_4", + "CMT_LR_LOWER_B_MMCM_TESTIN30", + "CMT_TOP_LH10_13", + "CMT_TOP_EE2A1_13", + "CMT_TOP_WL1END0_8", + "CMT_TOP_SE2A3_0", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_WW2END1_9", + "CMT_TOP_NW4A3_6", + "CMT_TOP_IMUX34_15", + "CMT_TOP_SE4C1_7", + "CMT_TOP_WL1END3_10", + "CMT_PHASER_A_OCLK90_TOIOI", + "CMT_TOP_LOGIC_OUTS_L_B9_11", + "CMT_TOP_NW2A3_12", + "CMT_TOP_BYP0_8", + "CMT_TOP_IMUX1_15", + "CMT_TOP_SW4END2_13", + "CMT_TOP_IMUX2_11", + "CMT_TOP_EE4A3_3", + "CMT_TOP_WR1END2_12", + "CMT_TOP_LH10_6", + "CMT_TOP_NW4A3_2", + "CMT_LR_LOWER_B_MMCM_TESTOUT54", + "CMT_TOP_WW4A2_14", + "CMT_TOP_MONITOR_P_14", + "CMT_TOP_NE4C0_11", + "CMT_TOP_SW2A0_13", + "CMT_TOP_LH3_4", + "CMT_TOP_LOGIC_OUTS_L_B12_13", + "CMT_TOP_LH8_0", + "CMT_TOP_IMUX24_6", + "CMT_MMCM_PHASER_OUT_A_OCLK", + "CMT_TOP_IMUX27_15", + "CMT_TOP_IMUX45_8", + "CMT_TOP_IMUX33_7", + "CMT_LR_LOWER_B_MMCM_TESTIN17", + "CMT_TOP_ER1BEG0_10", + "CMT_TOP_FAN0_10", + "CMT_TOP_IMUX28_7", + "CMT_TOP_LH8_9", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_TOP_WL1END1_9", + "CMT_TOP_EE4B0_5", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX15_10", + "CMT_TOP_CLK0_11", + "CMT_TOP_BYP4_13", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_IMUX3_10", + "CMT_TOP_IMUX17_0", + "CMT_TOP_BYP3_8", + "CMT_TOP_NE2A3_1", + "CMT_TOP_EE4C2_12", + "CMT_TOP_WL1END1_13", + "CMT_MMCM_PHASERA_DTSBUS0", + "CMT_TOP_NW2A3_2", + "CMT_TOP_EE4B3_1", + "CMT_TOP_WW4B3_5", + "CMT_TOP_BYP1_9", + "CMT_TOP_SE4C2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_SE2A1_7", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_SE4C3_12", + "CMT_TOP_CTRL1_12", + "CMT_TOP_WL1END3_5", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_IMUX3_1", + "CMT_TOP_WR1END2_1", + "CMT_TOP_NW4A1_4", + "CMT_TOP_WL1END2_11", + "CMT_TOP_IMUX19_15", + "CMT_TOP_WL1END1_10", + "CMT_TOP_IMUX20_3", + "CMT_TOP_BYP6_8", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX14_2", + "CMT_TOP_BYP4_4", + "CMT_MMCM_PHASER_IN_A_ICLKDIV", + "CMT_TOP_CLK1_7", + "CMT_TOP_IMUX2_3", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_IMUX46_5", + "CMT_TOP_NW4END1_3", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_IMUX45_11", + "CMT_TOP_NW2A3_5", + "CMT_TOP_EL1BEG3_12", + "CMT_TOP_WR1END2_3", + "CMT_TOP_BYP2_6", + "CMT_TOP_BYP3_3", + "CMT_TOP_FAN6_2", + "CMT_TOP_NW2A2_3", + "CMT_TOP_SW4END2_12", + "CMT_TOP_IMUX40_4", + "CMT_TOP_MONITOR_P_11", + "CMT_TOP_WW4A0_10", + "CMT_TOP_IMUX47_6", + "CMT_TOP_SW4A3_4", + "CMT_TOP_FAN7_0", + "CMT_TOP_WW4A0_11", + "CMT_TOP_LH11_5", + "CMT_TOP_IMUX30_5", + "CMT_TOP_SE2A3_1", + "CMT_TOP_EE4A3_6", + "CMT_TOP_IMUX5_1", + "CMT_TOP_EE4BEG3_6", + "CMT_TOP_SE2A2_0", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_BYP1_15", + "CMT_TOP_LOGIC_OUTS_L_B1_14", + "CMT_TOP_EE4B3_4", + "CMT_R_LOWER_B_CLK_MMCM0", + "CMT_TOP_EE4C3_6", + "CMT_TOP_CLK0_14", + "CMT_TOP_EE4C0_11", + "CMT_TOP_WW4B0_0", + "CMT_TOP_IMUX27_2", + "CMT_TOP_FAN0_8", + "CMT_MMCM_PHASERREF_BELOW0", + "CMT_TOP_EE4A2_6", + "CMT_R_LOWER_B_CLK_MMCM12", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_FAN2_6", + "CMT_TOP_SE4BEG0_8", + "CMT_TOP_LH5_15", + "CMT_TOP_WW2A1_13", + "CMT_TOP_CLK0_9", + "CMT_TOP_LH1_10", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_FAN7_14", + "CMT_TOP_SW2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_9", + "CMT_TOP_LOGIC_OUTS_L_B23_12", + "CMT_TOP_OCLK_12", + "CMT_TOP_IMUX46_11", + "CMT_TOP_SW2A1_14", + "CMT_TOP_IMUX3_11", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_NW4END0_6", + "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "CMT_TOP_IMUX16_14", + "CMT_TOP_IMUX10_0", + "CMT_TOP_IMUX43_4", + "CMT_TOP_EE4A0_0", + "CMT_TOP_IMUX36_1", + "CMT_R_LOWER_B_CLK_MMCM1", + "CMT_TOP_LH1_0", + "CMT_TOP_WW4A3_6", + "CMT_TOP_LOGIC_OUTS_L_B15_13", + "CMT_TOP_EE2A1_9", + "CMT_TOP_LOGIC_OUTS_L_B20_14", + "CMT_TOP_IMUX0_12", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_LOGIC_OUTS_L_B4_11", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_TOP_WW4A3_2", + "CMT_TOP_WW4B2_9", + "CMT_TOP_EE4C0_12", + "CMT_TOP_BYP0_5", + "CMT_TOP_IMUX10_12", + "CMT_TOP_ICLK_2", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_FAN0_11", + "CMT_TOP_NE2A3_5", + "CMT_TOP_EL1BEG3_10", + "CMT_LR_LOWER_B_MMCM_DI12", + "CMT_TOP_NE2A1_8", + "CMT_TOP_NW4END3_15", + "CMT_TOP_LH12_2", + "CMT_TOP_WW2A0_10", + "CMT_TOP_EE4C2_5", + "CMT_TOP_IMUX44_14", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_IMUX47_10", + "CMT_TOP_IMUX30_9", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_LOGIC_OUTS_L_B19_15", + "CMT_TOP_IMUX19_8", + "CMT_LR_LOWER_B_MMCM_DADDR5", + "CMT_TOP_WW2A2_6", + "CMT_TOP_IMUX17_6", + "CMT_TOP_IMUX14_5", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_TOP_IMUX34_2", + "CMT_TOP_BYP1_6", + "CMT_TOP_LOGIC_OUTS_L_B6_14", + "CMT_TOP_SW4A2_2", + "CMT_TOP_SE4C1_15", + "CMT_TOP_EE2BEG2_10", + "CMT_TOP_LOGIC_OUTS_L_B0_15", + "CMT_TOP_WW4A2_8", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_IMUX39_5", + "CMT_TOP_NW4A2_7", + "CMT_R_LOWER_B_CLK_IN2_INT", + "CMT_TOP_IMUX38_1", + "CMT_TOP_WW2A0_8", + "CMT_TOP_ER1BEG1_12", + "CMT_TOP_CTRL1_4", + "CMT_TOP_NW2A1_12", + "CMT_TOP_SE2A0_11", + "CMT_TOP_IMUX15_14", + "CMT_TOP_CTRL0_10", + "CMT_TOP_NE4C2_0", + "CMT_TOP_FAN2_12", + "CMT_TOP_IMUX8_1", + "CMT_TOP_OCLK_0", + "CMT_TOP_NE4C2_7", + "CMT_TOP_SW4END1_13", + "CMT_TOP_IMUX20_8", + "CMT_TOP_LOGIC_OUTS_L_B23_13", + "CMT_LR_LOWER_B_MMCM_TESTOUT33", + "CMT_TOP_IMUX46_14", + "CMT_TOP_SE2A3_12", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SE4C3_4", + "CMT_TOP_SE4C3_3", + "CMT_TOP_IMUX12_3", + "CMT_TOP_IMUX19_12", + "CMT_TOP_CLK0_5", + "CMT_TOP_WW2END1_4", + "CMT_TOP_NW2A1_5", + "CMT_TOP_IMUX16_2", + "CMT_TOP_MONITOR_N_10", + "CMT_TOP_BYP2_5", + "CMT_LR_LOWER_B_MMCM_TESTOUT30", + "CMT_TOP_WR1END3_11", + "CMT_TOP_IMUX40_2", + "CMT_TOP_WW4B2_8", + "CMT_TOP_EE4B1_2", + "CMT_TOP_SE4C1_2", + "CMT_TOP_SE4BEG1_13", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_WW4B3_13", + "CMT_TOP_SW4A1_9", + "CMT_TOP_FAN0_6", + "CMT_TOP_SW4END2_8", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_EE4A1_15", + "CMT_TOP_SE4BEG3_2", + "CMT_TOP_WL1END0_14", + "CMT_TOP_NW4A1_11", + "CMT_TOP_IMUX18_7", + "CMT_TOP_LH7_14", + "CMT_TOP_EL1BEG1_14", + "CMT_TOP_EE2BEG1_8", + "CMT_TOP_SW4A1_14", + "CMT_TOP_NE2A2_10", + "CMT_TOP_EE2BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B21_12", + "CMT_TOP_BYP0_15", + "CMT_LR_LOWER_B_MMCM_TESTIN29", + "CMT_TOP_BYP4_14", + "CMT_TOP_WW4A2_5", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX44_2", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_CTRL0_0", + "CMT_TOP_IMUX1_8", + "CMT_TOP_IMUX38_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_IMUX5_12", + "CMT_TOP_NW2A1_0", + "CMT_TOP_LOGIC_OUTS_L_B19_14", + "CMT_TOP_WW4B3_8", + "CMT_TOP_EE4BEG2_10", + "CMT_TOP_LH2_15", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_NW4A0_15", + "CMT_TOP_LOGIC_OUTS_L_B4_12", + "CMT_TOP_WW4B1_13", + "CMT_TOP_FAN7_13", + "CMT_LR_LOWER_B_MMCM_TESTIN16", + "CMT_TOP_WW4C0_14", + "CMT_TOP_IMUX38_0", + "CMT_TOP_EE4BEG3_15", + "CMT_TOP_IMUX36_14", + "CMT_TOP_SW2A2_1", + "CMT_TOP_EE4C1_13", + "CMT_TOP_NE4C2_9", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_TOP_SE4BEG1_11", + "CMT_TOP_NW2A3_14", + "CMT_TOP_BYP1_3", + "CMT_TOP_CTRL0_6", + "CMT_TOP_EE4A3_10", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_IMUX17_3", + "CMT_TOP_NW2A3_10", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX28_2", + "CMT_TOP_IMUX43_12", + "CMT_TOP_EE2A0_9", + "CMT_TOP_IMUX21_8", + "CMT_TOP_BLOCK_OUTS_L_B1_15", + "CMT_TOP_IMUX31_15", + "CMT_TOP_EE4B0_15", + "CMT_TOP_EL1BEG3_11", + "CMT_TOP_BYP7_14", + "CMT_TOP_IMUX42_2", + "CMT_TOP_WW2A3_6", + "CMT_TOP_WW4B0_4", + "CMT_TOP_WW2END1_14", + "CMT_TOP_SE2A2_5", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_TOP_IMUX38_9", + "CMT_TOP_BYP2_10", + "CMT_TOP_LOGIC_OUTS_L_B12_14", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EL1BEG0_10", + "CMT_TOP_EE4B1_11", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_EE2BEG2_7", + "CMT_TOP_ICLK_0", + "CMT_TOP_NW4END1_2", + "CMT_TOP_WW2A2_10", + "CMT_TOP_WW4END1_9", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX31_7", + "CMT_LR_LOWER_B_MMCM_TESTIN21", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_NW2A1_3", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX47_2", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_NE2A3_0", + "CMT_TOP_IMUX13_9", + "CMT_TOP_LH10_4", + "CMT_TOP_BYP0_2", + "CMT_TOP_CLK0_3", + "CMT_TOP_EE4B3_12", + "CMT_TOP_NE4C0_14", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_SW4A0_11", + "CMT_TOP_LOGIC_OUTS_L_B13_11", + "CMT_TOP_SW2A2_7", + "CMT_TOP_EL1BEG2_10", + "CMT_TOP_NE2A1_14", + "CMT_TOP_IMUX29_9", + "CMT_LR_LOWER_B_MMCM_TESTIN9", + "CMT_TOP_EE4B3_9", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_NE4C3_13", + "CMT_TOP_IMUX25_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_SE4BEG1_12", + "CMT_TOP_EE2A2_13", + "CMT_TOP_IMUX8_14", + "CMT_TOP_ICLK_10", + "CMT_TOP_NE4C1_7", + "CMT_TOP_NW2A2_11", + "CMT_TOP_EE4C3_8", + "CMT_TOP_ICLKDIV_12", + "CMT_TOP_IMUX4_2", + "CMT_TOP_NW4END0_0", + "CMT_TOP_IMUX47_13", + "CMT_TOP_IMUX11_9", + "CMT_TOP_EE4B2_10", + "CMT_TOP_IMUX0_6", + "CMT_TOP_WW4B0_1", + "CMT_TOP_FAN1_5", + "CMT_TOP_WL1END0_11", + "CMT_TOP_EE2A1_8", + "CMT_TOP_NE4C3_10", + "CMT_TOP_NE4C0_13", + "CMT_TOP_IMUX38_13", + "CMT_TOP_OCLK_10", + "CMT_TOP_IMUX7_14", + "CMT_TOP_WW2END2_2", + "CMT_TOP_SE2A3_13", + "CMT_TOP_EE2BEG3_14", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_IMUX17_13", + "CMT_TOP_FAN4_7", + "CMT_TOP_IMUX27_11", + "CMT_TOP_IMUX36_6", + "CMT_TOP_WW2END0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_EE4BEG3_11", + "CMT_TOP_NW4END1_15", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_EE4B3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_IMUX42_13", + "CMT_TOP_NW4A0_10", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_LH8_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_WW2END0_15", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_NE4C0_12", + "CMT_TOP_MONITOR_P_10", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_NE4C0_9", + "CMT_TOP_SW4A3_8", + "CMT_TOP_IMUX39_14", + "CMT_TOP_SW2A1_10", + "CMT_TOP_WW2A0_6", + "CMT_R_LOWER_B_CLK_MMCM11", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_LH7_12", + "CMT_TOP_WL1END2_1", + "CMT_TOP_LH8_10", + "CMT_TOP_NE4C0_0", + "CMT_TOP_IMUX29_7", + "CMT_TOP_EE4B0_4", + "CMT_TOP_WR1END3_6", + "CMT_TOP_LOGIC_OUTS_L_B6_11", + "CMT_TOP_LH9_14", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_TOP_IMUX1_13", + "CMT_TOP_BLOCK_OUTS_L_B3_9", + "CMT_TOP_WW4B2_2", + "CMT_PHASER_A_OCLK_TOIOI", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_LH11_4", + "CMT_TOP_LH6_6", + "CMT_TOP_LOGIC_OUTS_L_B1_12", + "MMCM_CLK_FREQ_BB_REBUF2_NS", + "CMT_TOP_NE2A1_11", + "CMT_TOP_EE4BEG1_14", + "CMT_TOP_NW2A3_7", + "CMT_TOP_WW4END0_5", + "CMT_TOP_FAN4_8", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_EE4BEG0_14", + "CMT_TOP_IMUX22_7", + "CMT_TOP_IMUX8_12", + "CMT_TOP_WR1END1_2", + "CMT_TOP_IMUX2_6", + "CMT_TOP_LOGIC_OUTS_L_B12_9", + "CMT_TOP_BYP4_8", + "CMT_TOP_IMUX25_13", + "CMT_TOP_IMUX33_13", + "CMT_TOP_SE4C3_5", + "CMT_TOP_BLOCK_OUTS_L_B2_9", + "CMT_TOP_SE4C1_13", + "CMT_TOP_FAN5_12", + "CMT_TOP_IMUX15_4", + "CMT_TOP_IMUX39_9", + "CMT_TOP_IMUX4_9", + "CMT_LR_LOWER_B_MMCM_DADDR6", + "CMT_LR_LOWER_B_MMCM_TESTIN12", + "CMT_TOP_IMUX22_13", + "CMT_TOP_BYP5_5", + "CMT_TOP_ICLK_1", + "CMT_TOP_BYP3_12", + "CMT_TOP_WW2END1_10", + "CMT_TOP_EE2A0_13", + "CMT_TOP_IMUX0_1", + "CMT_TOP_BYP6_7", + "CMT_TOP_CLK0_15", + "CMT_TOP_WW4B2_6", + "CMT_TOP_IMUX32_7", + "CMT_TOP_LH3_3", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_SW4A2_8", + "CMT_TOP_SE2A0_12", + "CMT_TOP_WL1END3_7", + "CMT_TOP_SW2A2_13", + "CMT_TOP_SW4A1_7", + "CMT_TOP_NE2A3_13", + "CMT_TOP_LH12_15", + "CMT_TOP_SW2A3_5", + "CMT_TOP_EE4C2_9", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_WW4END1_8", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_LH5_14", + "CMT_TOP_SW4A3_3", + "CMT_TOP_FAN1_9", + "CMT_LR_LOWER_B_MMCM_DI8", + "CMT_TOP_WW4A2_2", + "CMT_TOP_IMUX28_1", + "CMT_TOP_IMUX46_4", + "CMT_TOP_WW2END3_4", + "CMT_TOP_NW4END0_13", + "CMT_TOP_EE4B1_5", + "CMT_TOP_NE4C2_15", + "CMT_TOP_NW4A0_13", + "CMT_TOP_WR1END0_11", + "CMT_TOP_EE4B0_6", + "CMT_R_LOWER_B_CLK_IN3_INT", + "CMT_TOP_SW2A0_0", + "CMT_TOP_LH3_12", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_NW4A1_0", + "CMT_TOP_WR1END2_13", + "CMT_TOP_WW2END0_12", + "CMT_TOP_WW4B0_7", + "CMT_TOP_IMUX33_9", + "CMT_TOP_NW4END2_6", + "CMT_TOP_CLK1_4", + "CMT_TOP_IMUX13_12", + "CMT_TOP_IMUX17_10", + "CMT_LR_LOWER_B_MMCM_TESTIN18", + "CMT_TOP_IMUX37_15", + "CMT_TOP_BYP5_0", + "CMT_TOP_MONITOR_N_12", + "CMT_TOP_BYP5_14", + "CMT_TOP_NE4C1_8", + "CMT_TOP_WW4END1_1", + "CMT_TOP_NW4A2_11", + "CMT_TOP_IMUX37_0", + "CMT_TOP_SW2A0_12", + "CMT_TOP_WL1END3_1", + "CMT_TOP_IMUX16_8", + "CMT_TOP_IMUX39_2", + "CMT_TOP_IMUX37_7", + "CMT_TOP_IMUX16_3", + "CMT_MMCM_PHASERA_DQSBUS0", + "CMT_TOP_IMUX1_2", + "CMT_TOP_SE4C2_13", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_TOP_IMUX6_6", + "CMT_TOP_LH1_12", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_WW4B2_4", + "CMT_TOP_ER1BEG2_2", + "CMT_TOP_IMUX20_13", + "CMT_LR_LOWER_B_MMCM_DADDR1", + "CMT_TOP_IMUX11_10", + "CMT_TOP_IMUX17_7", + "CMT_TOP_OCLK_13", + "CMT_TOP_NW2A0_15", + "CMT_TOP_CTRL0_8", + "CMT_TOP_IMUX35_9", + "CMT_LR_LOWER_B_MMCM_PWRDWN", + "CMT_R_LOWER_B_CLK_PERF2", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_IMUX29_2", + "CMT_TOP_BYP6_1", + "CMT_TOP_ER1BEG0_9", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_FAN1_4", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW2A0_5", + "CMT_TOP_NE2A1_3", + "CMT_TOP_IMUX28_15", + "CMT_LR_LOWER_B_MMCM_DI0", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_LR_LOWER_B_MMCM_TESTOUT27", + "CMT_TOP_NW2A0_3", + "CMT_TOP_IMUX5_15", + "CMT_R_LOWER_B_CLK_MMCM2", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_SE2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_LH4_9", + "CMT_TOP_NW4A1_8", + "CMT_TOP_NE4BEG0_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT5", + "CMT_TOP_NW4END3_2", + "CMT_TOP_IMUX39_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_IMUX7_12", + "CMT_TOP_SW4END1_10", + "CMT_TOP_NW4END0_7", + "CMT_TOP_WW2A0_14", + "CMT_TOP_IMUX44_9", + "CMT_TOP_EE4A0_13", + "CMT_TOP_SW4END0_4", + "CMT_TOP_CTRL1_2", + "CMT_TOP_WW4END2_2", + "CMT_TOP_EE4B1_14", + "CMT_TOP_IMUX38_10", + "CMT_TOP_EE4B2_14", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4C2_10", + "CMT_TOP_EE4B0_14", + "CMT_TOP_BYP3_7", + "CMT_TOP_IMUX38_2", + "CMT_TOP_LH3_0", + "CMT_TOP_EE4BEG3_9", + "CMT_TOP_EE4C1_14", + "CMT_TOP_EE4A2_12", + "CMT_TOP_NE4BEG2_6", + "CMT_MMCM_PHASER_IN_B_ICLK", + "CMT_TOP_WW4A3_15", + "CMT_TOP_ICLK_11", + "CMT_R_LOWER_B_CLK_MMCM3", + "CMT_TOP_OCLK_3", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX13_11", + "CMT_TOP_NE2A2_15", + "CMT_TOP_LOGIC_OUTS_L_B7_15", + "CMT_TOP_ER1BEG0_15", + "CMT_TOP_WW2A0_13", + "CMT_TOP_IMUX11_2", + "CMT_TOP_WW4A2_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT18", + "CMT_TOP_SW4A0_5", + "CMT_TOP_EE4B2_3", + "CMT_TOP_IMUX9_7", + "CMT_TOP_EE2A2_3", + "CMT_TOP_WR1END3_1", + "CMT_TOP_WW2A0_0", + "CMT_TOP_WR1END0_5", + "CMT_TOP_ER1BEG2_8", + "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "CMT_TOP_NE4BEG1_14", + "CMT_TOP_WW4C3_10", + "CMT_TOP_IMUX21_14", + "CMT_TOP_NW4A0_8", + "CMT_TOP_BYP7_12", + "CMT_TOP_LOGIC_OUTS_L_B6_9", + "CMT_TOP_EE4C0_10", + "CMT_TOP_WW4B2_5", + "CMT_TOP_SW2A2_12", + "CMT_TOP_IMUX41_8", + "CMT_TOP_SW2A3_8", + "CMT_TOP_WW4END3_14", + "CMT_TOP_SW4END1_9", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_IMUX5_14", + "CMT_TOP_LH4_10", + "CMT_TOP_NE4BEG0_11", + "CMT_TOP_WW4B3_6", + "CMT_TOP_NW4END3_10", + "CMT_TOP_WW4END3_8", + "CMT_R_LOWER_B_CLK_FREQ_BB3", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_LOGIC_OUTS_L_B8_15", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX33_2", + "CMT_TOP_LOGIC_OUTS_L_B9_15", + "CMT_TOP_WW2END2_8", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_NE4BEG0_15", + "CMT_TOP_WW4C0_11", + "CMT_TOP_NE2A0_7", + "CMT_TOP_LOGIC_OUTS_L_B7_14", + "CMT_TOP_SE2A0_10", + "CMT_LR_LOWER_B_MMCM_DO13", + "CMT_LR_LOWER_B_MMCM_DO11", + "CMT_TOP_NW2A0_12", + "CMT_TOP_BYP0_7", + "CMT_TOP_NE2A2_14", + "CMT_TOP_IMUX0_11", + "CMT_TOP_EE4B0_13", + "CMT_TOP_IMUX21_12", + "CMT_TOP_NE2A1_7", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_TOP_IMUX3_12", + "CMT_LR_LOWER_B_MMCM_TESTOUT11", + "CMT_TOP_WW2A3_10", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_NW4A3_8", + "CMT_TOP_NW4A3_13", + "CMT_TOP_EE4A1_11", + "CMT_TOP_WW4C0_5", + "CMT_TOP_BYP4_9", + "CMT_TOP_IMUX8_7", + "CMT_TOP_IMUX33_14", + "CMT_TOP_NE2A0_1", + "CMT_TOP_IMUX40_15", + "CMT_TOP_WW4END0_0", + "CMT_TOP_FAN5_2", + "CMT_TOP_CTRL0_14", + "CMT_TOP_BYP0_13", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_WW4C1_10", + "CMT_TOP_IMUX39_8", + "CMT_TOP_NE4C1_2", + "CMT_TOP_IMUX30_4", + "CMT_TOP_WL1END0_12", + "CMT_TOP_NE2A3_12", + "CMT_LR_LOWER_B_MMCM_TESTIN8", + "CMT_TOP_BYP1_5", + "CMT_TOP_EE4C3_4", + "CMT_TOP_IMUX20_12", + "CMT_TOP_IMUX10_8", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_TOP_IMUX34_13", + "CMT_TOP_WW4B2_12", + "CMT_TOP_NE4BEG3_14", + "CMT_TOP_NE2A2_11", + "CMT_TOP_EE4A3_11", + "CMT_TOP_IMUX43_10", + "CMT_TOP_EE2A2_10", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_EL1BEG1_15", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_IMUX43_14", + "CMT_TOP_IMUX44_8", + "CMT_TOP_WL1END0_3", + "CMT_TOP_IMUX18_8", + "CMT_TOP_IMUX19_4", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_NE4C2_10", + "CMT_TOP_WW2END2_14", + "CMT_TOP_NW4END3_12", + "CMT_TOP_LH10_9", + "CMT_LR_LOWER_B_MMCM_TESTOUT43", + "CMT_TOP_LOGIC_OUTS_L_B10_9", + "CMT_LR_LOWER_B_MMCM_TESTIN28", + "CMT_LR_LOWER_B_MMCM_TESTOUT6", + "CMT_TOP_LH7_4", + "CMT_LR_LOWER_B_MMCM_TESTIN5", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_LOGIC_OUTS_L_B9_13", + "CMT_TOP_NW4A3_5", + "CMT_LR_LOWER_B_MMCM_TESTOUT17", + "CMT_LR_LOWER_B_MMCM_DO2", + "CMT_TOP_LOGIC_OUTS_L_B9_12", + "CMT_TOP_NW4END0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_12", + "CMT_TOP_LOGIC_OUTS_L_B5_15", + "CMT_TOP_IMUX29_4", + "CMT_TOP_NW2A0_6", + "CMT_TOP_BLOCK_OUTS_L_B1_12", + "CMT_TOP_SE2A2_2", + "CMT_LR_LOWER_B_MMCM_DI4", + "CMT_TOP_WW4C2_7", + "CMT_LR_LOWER_B_MMCM_DI2", + "CMT_TOP_IMUX37_9", + "CMT_TOP_WW4C0_4", + "CMT_TOP_IMUX34_14", + "CMT_TOP_BYP5_9", + "CMT_TOP_EE4BEG3_4", + "CMT_TOP_WW4A2_1", + "CMT_TOP_LH6_9", + "CMT_TOP_BYP5_12", + "CMT_TOP_SE4C2_11", + "CMT_TOP_IMUX39_13", + "CMT_TOP_LH10_3", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_WW4C3_2", + "CMT_TOP_IMUX38_5", + "CMT_TOP_IMUX8_8", + "CMT_TOP_NE2A0_14", + "CMT_TOP_NW4END1_14", + "CMT_TOP_FAN4_6", + "CMT_TOP_IMUX47_7", + "CMT_TOP_EE2A1_1", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_ER1BEG1_10", + "CMT_TOP_FAN7_8", + "CMT_TOP_FAN6_3", + "CMT_TOP_EE4B0_0", + "CMT_TOP_WW4A1_14", + "CMT_TOP_SE4C1_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT21", + "CMT_TOP_IMUX34_5", + "CMT_TOP_IMUX31_5", + "CMT_TOP_NE2A3_14", + "CMT_TOP_WW4END1_11", + "CMT_TOP_LOGIC_OUTS_L_B1_13", + "CMT_TOP_IMUX0_7", + "CMT_TOP_IMUX2_1", + "CMT_TOP_ER1BEG3_8" + ], + "pips": { + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX3_0->>CMT_LR_LOWER_B_MMCM_DI6": { + "src_wire": "CMT_TOP_IMUX3_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO4->>CMT_TOP_LOGIC_OUTS_L_B13_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_PERF0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX0_2->>CMT_LR_LOWER_B_MMCM_CLKINSEL": { + "src_wire": "CMT_TOP_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKINSEL", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_14": { + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO3->>CMT_TOP_LOGIC_OUTS_L_B22_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B22_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED->>CMT_TOP_LOGIC_OUTS_L_B18_2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN2_HCLK->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "src_wire": "CMT_R_LOWER_B_CLK_IN2_HCLK", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLK->>CMT_PHASER_A_OCLK_TOIOI": { + "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX47_1->>CMT_LR_LOWER_B_MMCM_PWRDWN": { + "src_wire": "CMT_TOP_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PWRDWN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN2_INT->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "src_wire": "CMT_R_LOWER_B_CLK_IN2_INT", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_13": { + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_9": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX34_2->>CMT_LR_LOWER_B_MMCM_RST": { + "src_wire": "CMT_TOP_IMUX34_2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_A_ICLKDIV->>CMT_PHASER_A_ICLKDIV_TOIOI": { + "src_wire": "CMT_MMCM_PHASER_IN_A_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_PERF2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO1->>CMT_TOP_LOGIC_OUTS_L_B18_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_CLK0_0->>CMT_LR_LOWER_B_MMCM_DCLK": { + "src_wire": "CMT_TOP_CLK0_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLKDIV->>CMT_PHASER_A_OCLKDIV_TOIOI": { + "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX44_1->>CMT_LR_LOWER_B_MMCM_DADDR6": { + "src_wire": "CMT_TOP_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX34_1->>CMT_LR_LOWER_B_MMCM_DADDR3": { + "src_wire": "CMT_TOP_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF0_NS<<->>MMCM_CLK_FREQ_BB_NS0": { + "src_wire": "MMCM_CLK_FREQ_BB_REBUF0_NS", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS0", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX39_0->>CMT_LR_LOWER_B_MMCM_DI15": { + "src_wire": "CMT_TOP_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1B->>CMT_R_LOWER_B_CLK_MMCM3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_13": { + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_PERF3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_12": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_15": { + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_PERF2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLK1X_90->>CMT_PHASER_A_OCLK90_TOIOI": { + "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_OCLK90_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX15_1->>CMT_LR_LOWER_B_MMCM_DEN": { + "src_wire": "CMT_TOP_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_8": { + "src_wire": "CMT_MMCM_PHASERA_CTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_PERF1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB3", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO7->>CMT_TOP_LOGIC_OUTS_L_B19_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO7", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX35_0->>CMT_LR_LOWER_B_MMCM_DI7": { + "src_wire": "CMT_TOP_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO6->>CMT_TOP_LOGIC_OUTS_L_B5_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO6", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3B->>CMT_R_LOWER_B_CLK_MMCM7": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_12": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO0->>CMT_TOP_LOGIC_OUTS_L_B8_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B8_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_10": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO2->>CMT_TOP_LOGIC_OUTS_L_B0_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_PERF0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_PERF3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX2_2->>CMT_LR_LOWER_B_MMCM_PSINCDEC": { + "src_wire": "CMT_TOP_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PSINCDEC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX1_0->>CMT_LR_LOWER_B_MMCM_DI2": { + "src_wire": "CMT_TOP_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN3_HCLK->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_R_LOWER_B_CLK_IN3_HCLK", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_CLK0_15->>CMT_R_LOWER_B_CLK_IN1_INT": { + "src_wire": "CMT_TOP_CLK0_15", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_IN1_INT", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_14": { + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_10": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_LR_LOWER_B_CLKFBOUT2IN": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0B->>CMT_R_LOWER_B_CLK_MMCM1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN1_HCLK->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "src_wire": "CMT_R_LOWER_B_CLK_IN1_HCLK", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO15->>CMT_TOP_LOGIC_OUTS_L_B17_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO15", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO12->>CMT_TOP_LOGIC_OUTS_L_B15_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX38_0->>CMT_LR_LOWER_B_MMCM_DI13": { + "src_wire": "CMT_TOP_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT5->>CMT_R_LOWER_B_CLK_MMCM9": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT5", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_PERF3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO14->>CMT_TOP_LOGIC_OUTS_L_B7_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO14", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_12": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2B->>CMT_R_LOWER_B_CLK_MMCM5": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2->>CMT_R_LOWER_B_CLK_FREQ_BB1": { + "src_wire": "MMCM_CLK_FREQ_BB_NS2", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO8->>CMT_TOP_LOGIC_OUTS_L_B10_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO8", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUTB->>CMT_R_LOWER_B_CLK_MMCM12": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>MMCMOUT_CLK_FREQ_BB_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB3", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX35_1->>CMT_LR_LOWER_B_MMCM_DADDR5": { + "src_wire": "CMT_TOP_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_MMCM4": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_MMCM0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_PERF0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_14": { + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX2_1->>CMT_LR_LOWER_B_MMCM_DADDR2": { + "src_wire": "CMT_TOP_IMUX2_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_PERF1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX32_0->>CMT_LR_LOWER_B_MMCM_DI1": { + "src_wire": "CMT_TOP_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "src_wire": "CMT_MMCM_PHASERA_DTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>MMCMOUT_CLK_FREQ_BB_1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX0_0->>CMT_LR_LOWER_B_MMCM_DI0": { + "src_wire": "CMT_TOP_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO9->>CMT_TOP_LOGIC_OUTS_L_B16_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO9", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_PERF1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO5->>CMT_TOP_LOGIC_OUTS_L_B23_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_14": { + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_PERF3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX22_1->>CMT_LR_LOWER_B_MMCM_DWE": { + "src_wire": "CMT_TOP_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DWE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_8": { + "src_wire": "CMT_MMCM_PHASERA_CTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_TMUXOUT->>CMT_R_LOWER_B_CLK_MMCM13": { + "src_wire": "CMT_LR_LOWER_B_MMCM_TMUXOUT", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX4_0->>CMT_LR_LOWER_B_MMCM_DI8": { + "src_wire": "CMT_TOP_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_PERF2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS1->>CMT_R_LOWER_B_CLK_FREQ_BB2": { + "src_wire": "MMCM_CLK_FREQ_BB_NS1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_CLK1_15->>CMT_R_LOWER_B_CLK_IN2_INT": { + "src_wire": "CMT_TOP_CLK1_15", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_IN2_INT", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>MMCMOUT_CLK_FREQ_BB_3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX3_1->>CMT_LR_LOWER_B_MMCM_DADDR4": { + "src_wire": "CMT_TOP_IMUX3_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB3", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_8": { + "src_wire": "CMT_MMCM_PHASERA_DQSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHYCTRL_SYNC_BB_DN<<->>CMT_MMCM_PHYCTRL_SYNC_BB_UP": { + "src_wire": "CMT_MMCM_PHYCTRL_SYNC_BB_DN", + "is_pseudo": "0", + "dst_wire": "CMT_MMCM_PHYCTRL_SYNC_BB_UP", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT6->>CMT_R_LOWER_B_CLK_MMCM10": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT6", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_13": { + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO10->>CMT_TOP_LOGIC_OUTS_L_B2_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO10", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN3_INT->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_R_LOWER_B_CLK_IN3_INT", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>MMCMOUT_CLK_FREQ_BB_2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_11": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX7_0->>CMT_LR_LOWER_B_MMCM_DI14": { + "src_wire": "CMT_TOP_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS0->>CMT_R_LOWER_B_CLK_FREQ_BB3": { + "src_wire": "MMCM_CLK_FREQ_BB_NS0", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX2_0->>CMT_LR_LOWER_B_MMCM_DI4": { + "src_wire": "CMT_TOP_IMUX2_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_15": { + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_MMCM2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX34_0->>CMT_LR_LOWER_B_MMCM_DI5": { + "src_wire": "CMT_TOP_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3->>CMT_R_LOWER_B_CLK_FREQ_BB0": { + "src_wire": "MMCM_CLK_FREQ_BB_NS3", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF1_NS<<->>MMCM_CLK_FREQ_BB_NS1": { + "src_wire": "MMCM_CLK_FREQ_BB_REBUF1_NS", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS1", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED->>CMT_TOP_LOGIC_OUTS_L_B16_2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_CLK0_14->>CMT_R_LOWER_B_CLK_IN3_INT": { + "src_wire": "CMT_TOP_CLK0_14", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_IN3_INT", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX37_0->>CMT_LR_LOWER_B_MMCM_DI11": { + "src_wire": "CMT_TOP_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX6_0->>CMT_LR_LOWER_B_MMCM_DI12": { + "src_wire": "CMT_TOP_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_A_ICLK->>CMT_PHASER_A_ICLK_TOIOI": { + "src_wire": "CMT_MMCM_PHASER_IN_A_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX0_1->>CMT_LR_LOWER_B_MMCM_DADDR0": { + "src_wire": "CMT_TOP_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO13->>CMT_TOP_LOGIC_OUTS_L_B21_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO13", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF3_NS<<->>MMCM_CLK_FREQ_BB_NS3": { + "src_wire": "MMCM_CLK_FREQ_BB_REBUF3_NS", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS3", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF2_NS<<->>MMCM_CLK_FREQ_BB_NS2": { + "src_wire": "MMCM_CLK_FREQ_BB_REBUF2_NS", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS2", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_PERF0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO11->>CMT_TOP_LOGIC_OUTS_L_B20_0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DO11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_11": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT4->>CMT_R_LOWER_B_CLK_MMCM8": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT4", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_PERF3": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSDONE->>CMT_TOP_LOGIC_OUTS_L_B21_1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_PSDONE", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_PERF1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_PERF2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_MMCM6": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_DRDY", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX1_1->>CMT_LR_LOWER_B_MMCM_DADDR1": { + "src_wire": "CMT_TOP_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_PERF1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_CLK0_1->>CMT_LR_LOWER_B_MMCM_PSCLK": { + "src_wire": "CMT_TOP_CLK0_1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN1_INT->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "src_wire": "CMT_R_LOWER_B_CLK_IN1_INT", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_9": { + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_12": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_PERF2": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_PERF0": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_MMCM11": { + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX33_0->>CMT_LR_LOWER_B_MMCM_DI3": { + "src_wire": "CMT_TOP_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX5_0->>CMT_LR_LOWER_B_MMCM_DI10": { + "src_wire": "CMT_TOP_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX1_2->>CMT_LR_LOWER_B_MMCM_PSEN": { + "src_wire": "CMT_TOP_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PSEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX36_0->>CMT_LR_LOWER_B_MMCM_DI9": { + "src_wire": "CMT_TOP_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_8": { + "src_wire": "CMT_MMCM_PHASERA_DQSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_13": { + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_8": { + "src_wire": "CMT_PHASER_A_OCLK90_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B18_1": { + "src_wire": "CMT_LR_LOWER_B_MMCM_LOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { + "src_wire": "CMT_MMCM_PHASERA_DTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_15": { + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_15": { + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_15", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CMT_TOP_R_LOWER_T.json b/kintex7/tile_type_CMT_TOP_R_LOWER_T.json new file mode 100644 index 0000000..6e40b8b --- /dev/null +++ b/kintex7/tile_type_CMT_TOP_R_LOWER_T.json @@ -0,0 +1,4823 @@ +{ + "tile_type": "CMT_TOP_R_LOWER_T", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "PHASER_OUT_PHY", + "type": "PHASER_OUT_PHY", + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", + "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", + "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", + "RST": "CMT_PHASER_OUT_CA_RST", + "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", + "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", + "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", + "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", + "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", + "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", + "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", + "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", + "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", + "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", + "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", + "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", + "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", + "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", + "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", + "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", + "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", + "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", + "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", + "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", + "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", + "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", + "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", + "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", + "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", + "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", + "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", + "OCLK": "CMT_PHASER_OUT_CA_OCLK", + "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", + "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", + "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3", + "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", + "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", + "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", + "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "PHASER_IN_PHY", + "type": "PHASER_IN_PHY", + "site_pins": { + "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", + "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE", + "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", + "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", + "RST": "CMT_PHASER_IN_CA_RST", + "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", + "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", + "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", + "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_IN_CA_FINEINC", + "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", + "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", + "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", + "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", + "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", + "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", + "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", + "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", + "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", + "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", + "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", + "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", + "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", + "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", + "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", + "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", + "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", + "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", + "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", + "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", + "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "STG1READ": "CMT_PHASER_IN_CA_STG1READ", + "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", + "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", + "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", + "SCANENB": "CMT_PHASER_IN_CA_SCANENB", + "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", + "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", + "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", + "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", + "SCANIN": "CMT_PHASER_IN_CA_SCANIN", + "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", + "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", + "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", + "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", + "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", + "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", + "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST", + "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", + "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", + "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", + "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", + "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", + "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", + "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", + "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", + "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", + "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", + "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", + "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", + "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1", + "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", + "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", + "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", + "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", + "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", + "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", + "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", + "ICLK": "CMT_PHASER_IN_CA_ICLK", + "RCLK": "CMT_PHASER_IN_CA_RCLK" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "PHASER_OUT_PHY", + "type": "PHASER_OUT_PHY", + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_DB_COARSEINC", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", + "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", + "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", + "RST": "CMT_PHASER_OUT_DB_RST", + "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", + "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", + "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", + "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", + "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", + "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", + "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", + "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", + "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE", + "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", + "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", + "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", + "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", + "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "COARSEENABLE": "CMT_PHASER_OUT_DB_COARSEENABLE", + "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", + "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", + "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", + "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", + "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", + "COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", + "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", + "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", + "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", + "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", + "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", + "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", + "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", + "OCLK": "CMT_PHASER_OUT_DB_OCLK", + "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", + "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", + "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3", + "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING", + "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", + "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", + "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "PHASER_IN_PHY", + "type": "PHASER_IN_PHY", + "site_pins": { + "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", + "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE", + "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", + "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", + "RST": "CMT_PHASER_IN_DB_RST", + "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", + "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", + "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", + "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_IN_DB_FINEINC", + "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", + "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", + "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", + "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", + "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", + "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", + "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", + "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", + "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", + "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", + "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", + "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", + "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", + "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", + "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", + "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", + "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", + "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", + "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", + "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", + "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "STG1READ": "CMT_PHASER_IN_DB_STG1READ", + "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", + "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", + "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", + "SCANENB": "CMT_PHASER_IN_DB_SCANENB", + "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", + "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", + "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", + "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", + "SCANIN": "CMT_PHASER_IN_DB_SCANIN", + "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", + "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", + "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", + "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", + "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", + "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", + "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST", + "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", + "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", + "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", + "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", + "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", + "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", + "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", + "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", + "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", + "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", + "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", + "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", + "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1", + "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", + "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", + "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", + "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", + "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", + "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", + "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", + "ICLK": "CMT_PHASER_IN_DB_ICLK", + "RCLK": "CMT_PHASER_IN_DB_RCLK" + }, + "x_coord": 0 + } + ], + "wires": [ + "CMT_TOP_WR1END2_7", + "CMT_TOP_IMUX17_5", + "CMT_TOP_WW4C3_6", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_IMUX18_1", + "CMT_TOP_WL1END3_8", + "CMT_TOP_WW2A1_0", + "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "CMT_TOP_IMUX8_5", + "CMT_TOP_WW2END3_7", + "CMT_PHASER_IN_DB_EDGEADV", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_CLK1_3", + "CMT_TOP_IMUX15_8", + "CMT_TOP_LH5_7", + "CMT_PHASER_IN_CA_TESTOUT0", + "CMT_TOP_SE4C2_0", + "CMT_TOP_EE2A3_2", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_FAN2_3", + "CMT_TOP_IMUX40_8", + "CMT_PHASER_OUT_A_OCLK", + "CMT_TOP_EE4C2_7", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_SE4C3_8", + "CMT_TOP_NW2A1_4", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_EE2A1_6", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_TOP_EE4A2_4", + "CMT_TOP_BYP1_4", + "CMT_TOP_EE4C0_3", + "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_IMUX39_1", + "CMT_TOP_LH1_3", + "CMT_TOP_SE4C1_4", + "CMT_TOP_BYP5_7", + "CMT_TOP_IMUX47_8", + "CMT_PHASER_IN_DB_TESTIN6", + "CMT_TOP_IMUX23_5", + "CMT_TOP_IMUX36_0", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "CMT_TOP_IMUX34_7", + "CMT_PHASER_BOT_OBURSTPENDING1", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN5_3", + "CMT_TOP_NE4C2_2", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_NW4A2_2", + "CMT_TOP_EE4A2_5", + "CMT_PHASER_IN_CA_RANKSEL1", + "CMT_TOP_IMUX35_5", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_EE2A0_1", + "CMT_TOP_EE4C1_0", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_WW4END1_6", + "CMT_PHASER_IN_CA_ENCALIBPHY0", + "CMT_PHASER_OUT_DB_TESTIN1", + "CMT_TOP_WL1END1_8", + "CMT_TOP_FAN3_2", + "CMT_PHASER_IN_DB_WRENABLE", + "CMT_PHASER_OUT_DB_COUNTERREADEN", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_WW2END1_6", + "CMT_TOP_WW4END0_6", + "CMT_TOP_SE2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE2A2_1", + "CMT_LR_LOWER_T_CLK_MMCM2", + "CMT_TOP_EE2A2_5", + "CMT_PHASER_IN_CA_FREQREFCLK", + "CMT_TOP_WW2END0_3", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_FAN5_0", + "CMT_TOP_ER1BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_IMUX7_2", + "CMT_TOP_SE4C0_2", + "CMT_TOP_EE4B3_8", + "CMT_PHASER_OUT_DB_TESTIN12", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_EE4A1_2", + "CMT_PHASER_OUT_DB_TESTIN2", + "CMT_TOP_IMUX31_4", + "CMT_TOP_LH2_0", + "CMT_TOP_EL1BEG3_5", + "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "CMT_TOP_SE2A0_6", + "CMT_PHASER_IN_CA_RCLK", + "CMT_LR_LOWER_T_CLK_MMCM13", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_NW4A3_4", + "CMT_TOP_LH9_2", + "CMT_TOP_WW4END1_2", + "CMT_PHASER_IN_DB_STG1REGR7", + "CMT_TOP_WW4B1_5", + "CMT_TOP_EE2BEG2_1", + "CMT_PHASER_OUT_CA_TESTIN0", + "CMT_TOP_IMUX12_5", + "CMT_PHASER_OUT_DB_COARSEINC", + "CMT_PHASER_IN_DB_STG1REGR8", + "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "CMT_TOP_WW2A3_1", + "CMT_TOP_LH5_3", + "CMT_TOP_NE2A0_6", + "CMT_TOP_FAN4_1", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_EE4A0_6", + "CMT_PHASER_OUT_CA_COARSEENABLE", + "CMT_TOP_LH12_1", + "CMT_TOP_LH8_6", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_IMUX36_5", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_OCLK_6", + "CMT_TOP_SW4END1_5", + "CMT_TOP_WR1END0_2", + "CMT_TOP_NW4END1_8", + "CMT_TOP_SE2A0_8", + "CMT_TOP_LH11_2", + "CMT_TOP_EE4C3_2", + "CMT_TOP_IMUX2_7", + "CMT_TOP_EE2A1_7", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX16_6", + "CMT_TOP_LH6_2", + "CMT_PHASER_IN_DB_STG1REGL6", + "CMT_TOP_FAN6_6", + "CMT_TOP_NE2A2_7", + "CMT_TOP_LH7_6", + "CMT_PHASER_OUT_CA_TESTOUT3", + "CMT_TOP_IMUX9_2", + "CMT_TOP_WW4C0_1", + "CMT_TOP_BYP5_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_PHASER_IN_CA_ENCALIB0", + "CMT_LR_LOWER_T_CLK_MMCM7", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX45_3", + "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "CMT_TOP_WR1END1_7", + "CMT_TOP_WL1END1_1", + "CMT_PHASER_BOT_IRANKA1", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_SW2A0_3", + "CMT_PHASER_IN_DB_FINEINC", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_EE4C0_7", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX23_8", + "CMT_TOP_NW4END1_6", + "CMT_TOP_IMUX38_4", + "CMT_TOP_FAN6_7", + "CMT_PHASER_OUT_DB_SCANOUT", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_IMUX41_5", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_SW4END2_3", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_EE2BEG3_8", + "CMT_TOP_LH9_7", + "CMT_PHASER_OUT_CA_DQSBUS0", + "CMT_PHASER_IN_DB_TESTIN1", + "CMT_TOP_WW4A1_1", + "CMT_TOP_WR1END0_3", + "CMT_TOP_LH1_6", + "CMT_TOP_FAN2_7", + "CMT_PHASER_IN_DB_RANKSEL0", + "CMT_TOP_BYP7_6", + "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "CMT_PHASER_OUT_DB_DTSBUS0", + "CMT_TOP_NW4END3_0", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_NW4A1_5", + "CMT_PHASER_OUT_CA_TESTIN7", + "CMT_TOP_SE4BEG0_6", + "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "CMT_TOP_IMUX7_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_1", + "CMT_TOP_EE2BEG1_7", + "CMT_PHASER_OUT_CA_TESTIN14", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_FAN6_8", + "CMT_PHASER_IN_DB_STG1REGL4", + "CMT_TOP_WW4C1_4", + "CMT_TOP_NE2A2_5", + "CMT_TOP_SW2A3_2", + "CMT_TOP_IMUX3_7", + "CMT_TOP_NW4A2_4", + "CMT_TOP_WW4A0_8", + "CMT_TOP_WW4C2_4", + "CMT_TOP_NW4END0_5", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_TOP_LH6_5", + "CMT_PHASER_IN_CA_STG1READ", + "CMT_TOP_FAN5_7", + "CMT_TOP_OCLK_2", + "CMT_TOP_WL1END1_6", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_BYP6_0", + "CMT_TOP_FAN5_1", + "CMT_TOP_ER1BEG0_8", + "CMT_LR_LOWER_T_CLK_MMCM10", + "CMT_TOP_EE2BEG2_6", + "CMT_PHASER_IN_CA_DQSFOUND", + "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "CMT_TOP_NW4END1_7", + "CMT_TOP_EE2A1_4", + "CMT_TOP_FAN1_6", + "CMT_TOP_IMUX26_4", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_IMUX33_6", + "CMT_TOP_LH2_8", + "CMT_TOP_IMUX3_2", + "CMT_TOP_NW4A2_6", + "CMT_PHASER_IN_B_WRCLK_TOFIFO", + "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_LH4_2", + "CMT_TOP_NE4C1_6", + "CMT_TOP_EE4A1_8", + "CMT_PHASER_IN_DB_FINEENABLE", + "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "CMT_TOP_WW4END1_7", + "CMT_TOP_IMUX44_5", + "CMT_TOP_NE2A0_3", + "CMT_PHASER_IN_CA_TESTIN6", + "CMT_TOP_SE4C3_7", + "CMT_TOP_IMUX37_4", + "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "CMT_TOP_WW4C2_8", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_IMUX31_1", + "CMT_TOP_EE4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_WW4C3_7", + "CMT_TOP_WW4B3_1", + "CMT_TOP_IMUX8_4", + "CMT_TOP_EE4C0_8", + "CMT_TOP_IMUX33_1", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_PHASER_IN_DB_TESTIN3", + "CMT_TOP_EL1BEG0_7", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "CMT_TOP_WW4END1_3", + "CMT_TOP_SW2A0_1", + "CMT_TOP_IMUX33_8", + "CMT_TOP_NW4A1_3", + "CMT_TOP_LH10_0", + "CMT_TOP_LH5_6", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX7_5", + "CMT_TOP_WW2END1_0", + "CMT_TOP_EE4C2_1", + "CMT_TOP_IMUX13_3", + "CMT_TOP_ER1BEG2_5", + "CMT_TOP_WW4END1_4", + "CMT_PHASER_IN_DB_STG1REGR6", + "CMT_TOP_EE4BEG1_5", + "CMT_PHASER_IN_CA_SCANENB", + "CMT_TOP_EE4C2_4", + "CMT_TOP_EE2A1_3", + "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "CMT_TOP_EE4C1_5", + "CMT_TOP_LH9_1", + "CMT_TOP_SW4A2_3", + "CMT_TOP_SE2A1_3", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_NE4C3_7", + "CMT_TOP_IMUX12_2", + "CMT_TOP_SE2A0_1", + "CMT_TOP_WW4B1_8", + "CMT_TOP_LH12_3", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_FAN7_4", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END2_5", + "CMT_PHASER_OUT_DB_ENCALIB0", + "CMT_TOP_FAN1_0", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_IMUX40_7", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_PHASER_OUT_B_OCLKDIV", + "CMT_TOP_BYP7_8", + "CMT_PHASER_IN_DB_RANKSELPHY0", + "CMT_TOP_IMUX21_3", + "CMT_PHASER_OUT_DB_CTSBUS0", + "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "CMT_TOP_NW4A3_0", + "CMT_TOP_EE4A2_3", + "CMT_TOP_WL1END2_4", + "CMT_TOP_SW4A2_6", + "CMT_TOP_IMUX9_0", + "CMT_TOP_IMUX0_5", + "CMT_TOP_IMUX35_8", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_EE2A3_3", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW2A0_2", + "CMT_TOP_SW4END1_2", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_EE2A3_5", + "CMT_TOP_WR1END0_1", + "CMT_TOP_IMUX16_4", + "CMT_TOP_WW4C1_3", + "CMT_TOP_LH4_3", + "CMT_TOP_EE4B2_8", + "CMT_TOP_LH2_4", + "CMT_TOP_WW4C0_2", + "CMT_PHASER_OUT_CA_RDENABLE", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_IMUX5_2", + "CMT_TOP_EE2BEG1_6", + "CMT_PHASER_IN_CA_TESTIN13", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_EE4BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NW4A0_6", + "CMT_TOP_LH3_6", + "CMT_TOP_EE4A3_5", + "CMT_TOP_IMUX14_0", + "CMT_TOP_EE4C3_0", + "CMT_TOP_IMUX40_1", + "CMT_TOP_LH7_5", + "CMT_TOP_WW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_PHASERA_DQSBUS0", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_LR_LOWER_T_CLK_MMCM1", + "CMT_TOP_WW2END2_3", + "CMT_TOP_IMUX42_4", + "CMT_TOP_IMUX32_2", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_WW2END3_8", + "CMT_TOP_NW4END1_0", + "CMT_TOP_LH1_4", + "CMT_PHASER_IN_CA_RANKSELPHY0", + "CMT_TOP_BYP0_1", + "CMT_PHASER_OUT_DB_SYNCIN", + "CMT_TOP_NE4C2_5", + "CMT_TOP_NE4C0_6", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "CMT_TOP_IMUX24_1", + "CMT_TOP_IMUX14_4", + "CMT_TOP_IMUX12_4", + "CMT_TOP_IMUX12_1", + "CMT_TOP_SW4END3_2", + "CMT_TOP_IMUX32_0", + "CMT_TOP_SE4BEG0_1", + "CMT_TOP_IMUX29_3", + "CMT_TOP_IMUX18_0", + "CMT_PHASER_IN_CA_STG1REGR6", + "CMT_TOP_SW2A0_6", + "CMT_TOP_IMUX44_6", + "CMT_PHASER_DOWN_PHASERREF1", + "CMT_TOP_SE2A3_3", + "CMT_TOP_FAN7_6", + "CMT_PHASER_OUT_DB_MEMREFCLK", + "CMT_TOP_EE4A0_3", + "CMT_TOP_FAN0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_SW2A3_6", + "CMT_TOP_WW4B3_2", + "CMT_PHASER_IN_CA_TESTIN2", + "CMT_TOP_FAN0_7", + "CMT_TOP_WW4B0_3", + "CMT_TOP_LH11_8", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_PHASER_IN_CA_STG1REGR8", + "CMT_TOP_IMUX47_4", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_WW4C1_6", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_NW2A0_7", + "CMT_PHASER_DOWN_DQS_TO_PHASER_A", + "CMT_TOP_WR1END2_5", + "CMT_TOP_BYP5_3", + "CMT_TOP_NW4A2_1", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_SW4END3_7", + "CMT_TOP_FAN5_6", + "CMT_TOP_IMUX32_4", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_NW4END3_6", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "CMT_PHASER_IN_DB_PHASEREFCLK", + "CMT_TOP_IMUX45_6", + "CMT_TOP_EE4C3_1", + "CMT_TOP_WW4END2_8", + "CMT_TOP_CTRL0_3", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_WW4END1_0", + "CMT_TOP_LH3_2", + "CMT_TOP_SW4END1_7", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "CMT_TOP_IMUX8_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_IMUX2_8", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_IMUX6_5", + "CMT_TOP_WW4A3_5", + "CMT_TOP_OCLK_5", + "CMT_TOP_BYP0_3", + "CMT_PHASER_OUT_DB_TESTIN14", + "CMT_TOP_WW2A2_2", + "CMT_TOP_IMUX20_7", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_IMUX25_4", + "CMT_TOP_IMUX26_2", + "CMT_TOP_NW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_IMUX13_4", + "CMT_TOP_WW4C0_3", + "CMT_PHASER_IN_DB_RANKSEL1", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_NE2A0_2", + "CMT_TOP_IMUX28_5", + "CMT_TOP_WW4C3_8", + "CMT_PHASER_IN_DB_TESTIN13", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_NE2A0_8", + "CMT_TOP_LH6_4", + "CMT_TOP_NW2A2_4", + "CMT_TOP_BYP1_1", + "CMT_TOP_SE2A3_6", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX2_2", + "CMT_TOP_WW2END3_6", + "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "CMT_TOP_IMUX21_0", + "CMT_PHASER_IN_CA_SCANCLK", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "CMT_PHASER_IN_CA_RANKSEL0", + "CMT_PHASER_OUT_DB_TESTIN9", + "CMT_TOP_IMUX43_1", + "CMT_TOP_SE2A0_2", + "CMT_TOP_WW4B1_1", + "CMT_TOP_WW4B1_7", + "CMT_TOP_EE4BEG1_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_TOP_WW2A3_4", + "CMT_TOP_IMUX28_8", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_WW4C3_4", + "CMT_TOP_LH8_1", + "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "CMT_TOP_NW4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_WW2A3_2", + "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "CMT_TOP_NW4A0_7", + "CMT_TOP_BYP7_3", + "CMT_TOP_IMUX25_0", + "CMT_PHASER_IN_CA_TESTIN3", + "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "CMT_TOP_LH9_5", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_NE4C2_8", + "CMT_PHASER_OUT_DB_SCANENB", + "CMT_TOP_IMUX6_7", + "CMT_PHASER_OUT_DB_COARSEENABLE", + "CMT_PHASER_OUT_DB_FREQREFCLK", + "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "CMT_PHASER_IN_A_WRCLK_TOFIFO", + "CMT_PHASER_IN_DB_STG1REGR2", + "CMT_TOP_IMUX41_0", + "CMT_TOP_LH4_4", + "CMT_TOP_WR1END3_4", + "CMT_TOP_IMUX24_3", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_EE2A0_6", + "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "CMT_TOP_EE2A2_6", + "CMT_TOP_BYP2_2", + "CMT_PHASER_OUT_DB_EDGEADV", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_NW2A0_4", + "CMT_TOP_EE2A1_2", + "CMT_TOP_IMUX21_6", + "CMT_TOP_SE4C3_1", + "CMT_TOP_SW2A2_3", + "CMT_TOP_IMUX19_7", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX0_4", + "CMT_TOP_IMUX46_3", + "CMT_TOP_EE4A2_0", + "CMT_TOP_SW4END2_7", + "CMT_TOP_SE2A2_4", + "CMT_TOP_IMUX15_0", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_EE4A0_7", + "CMT_TOP_WW4C2_3", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_IMUX32_3", + "CMT_PHASER_IN_DB_COUNTERLOADEN", + "CMT_TOP_IMUX11_8", + "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_WW4END2_5", + "CMT_TOP_IMUX27_5", + "CMT_TOP_WW2A1_8", + "CMT_TOP_IMUX36_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_IMUX9_8", + "CMT_TOP_WL1END1_0", + "CMT_TOP_IMUX47_3", + "CMT_PHASER_IN_DB_ICLK", + "CMT_TOP_SW4A0_4", + "CMT_TOP_IMUX0_2", + "CMT_PHASER_IN_DB_ENCALIBPHY0", + "CMT_TOP_FAN1_8", + "CMT_PHASER_OUT_DB_TESTIN13", + "CMT_TOP_IMUX34_4", + "CMT_TOP_WW2A1_6", + "CMT_TOP_SW4A2_1", + "CMT_TOP_NW2A2_2", + "CMT_PHASER_IN_DB_STG1REGR5", + "CMT_TOP_FAN0_3", + "CMT_TOP_IMUX5_5", + "CMT_TOP_WW4B0_2", + "CMT_TOP_LH2_2", + "CMT_PHASER_OUT_CA_OCLKDIV", + "CMT_TOP_NW2A0_0", + "CMT_TOP_IMUX10_7", + "CMT_TOP_SE4BEG1_4", + "CMT_TOP_IMUX39_0", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_MONITOR_P_2", + "CMT_PHASER_B_TOMMCM_ICLKDIV", + "CMT_TOP_WW4C3_1", + "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "CMT_PHASER_OUT_CA_TESTIN13", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SE4C2_3", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_IMUX33_5", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "CMT_TOP_SW4A3_5", + "CMT_PHASER_OUT_CA_EDGEADV", + "CMT_PHASER_BOT_REFMUX_0", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_LH7_7", + "CMT_TOP_IMUX14_1", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_NW4END3_1", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_IMUX26_1", + "CMT_TOP_WW2END0_5", + "CMT_TOP_WL1END0_1", + "CMT_TOP_LH11_6", + "CMT_TOP_NE4C3_8", + "CMT_TOP_LH5_1", + "CMT_TOP_LH8_7", + "CMT_TOP_WL1END0_7", + "CMT_TOP_LH12_4", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_PHASER_OUT_CA_CTSBUS0", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_NE4C3_4", + "CMT_TOP_ER1BEG0_7", + "CMT_TOP_FAN6_5", + "CMT_TOP_WW2END2_4", + "CMT_TOP_SE4C2_6", + "CMT_TOP_SW4END1_8", + "CMT_TOP_IMUX27_1", + "CMT_TOP_NE4BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_SE2A2_8", + "CMT_TOP_SW2A1_1", + "CMT_TOP_WL1END2_5", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_WW4END3_5", + "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "CMT_TOP_WL1END2_6", + "CMT_TOP_IMUX43_6", + "CMT_TOP_IMUX14_8", + "CMT_PHASER_OUT_DB_TESTIN4", + "CMT_TOP_NW4A1_1", + "CMT_TOP_SE4C1_8", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_NW4END3_4", + "CMT_TOP_SE4BEG0_3", + "CMT_PHASER_IN_CA_TESTIN7", + "CMT_TOP_IMUX40_5", + "CMT_TOP_NE2A2_3", + "CMT_PHASER_IN_DB_STG1OVERFLOW", + "CMT_TOP_LH8_2", + "CMT_TOP_OCLK1X_90_5", + "CMT_PHASER_IN_DB_DQSFOUND", + "CMT_TOP_EE4BEG3_2", + "CMT_PHASER_IN_CA_ENCALIB1", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_IMUX34_1", + "CMT_TOP_WL1END2_0", + "CMT_TOP_EE4A1_3", + "CMT_TOP_LH7_0", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_WW2END0_2", + "CMT_TOP_IMUX0_3", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_EE4A0_1", + "CMT_TOP_WW4A1_4", + "CMT_TOP_IMUX23_3", + "CMT_TOP_IMUX20_0", + "CMT_TOP_WR1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_IMUX25_1", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_SE2A3_2", + "CMT_TOP_ER1BEG1_1", + "CMT_TOP_CLK1_8", + "CMT_TOP_IMUX44_7", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_PHASER_IN_DB_TESTIN7", + "CMT_PHASER_IN_DB_STG1REGR0", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_NW4A0_1", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_WW2A0_4", + "CMT_TOP_NW4END2_1", + "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "CMT_PHASER_B_TOMMCM_OCLK", + "CMT_TOP_EE4B0_8", + "CMT_TOP_NW4END2_8", + "CMT_TOP_CLK0_6", + "CMT_TOP_WR1END2_6", + "CMT_TOP_WW4A3_3", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_WW4END0_1", + "CMT_TOP_LH1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_NW4A0_4", + "CMT_TOP_CLK1_5", + "CMT_TOP_NW2A1_7", + "CMT_TOP_WW4A2_6", + "CMT_TOP_IMUX27_3", + "CMT_TOP_SW2A3_0", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_WR1END2_2", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_EE2A2_7", + "CMT_PHASER_IN_CA_STG1REGL7", + "CMT_TOP_IMUX18_5", + "CMT_TOP_IMUX8_0", + "CMT_TOP_IMUX24_8", + "CMT_TOP_IMUX24_7", + "CMT_PHASER_OUT_B_OCLK1X_90", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "CMT_PHASER_IN_CA_STG1REGL8", + "CMT_TOP_WW4C1_1", + "CMT_TOP_EE4B0_2", + "CMT_TOP_SW2A0_2", + "CMT_TOP_SW4A3_1", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_LH5_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4C2_0", + "CMT_PHASERA_DTSBUS1", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_WL1END3_2", + "CMT_LR_LOWER_T_CLK_MMCM11", + "CMT_TOP_FAN4_5", + "CMT_TOP_NE2A1_2", + "CMT_TOP_SE4BEG1_7", + "CMT_PHASER_OUT_A_OCLKDIV", + "CMT_TOP_WR1END0_8", + "CMT_TOP_IMUX36_3", + "CMT_TOP_WL1END1_4", + "CMT_TOP_WW4B1_6", + "CMT_PHASER_IN_DB_FINEOVERFLOW", + "CMT_TOP_WW2A3_7", + "CMT_TOP_BYP3_6", + "CMT_TOP_EE4B1_8", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_IMUX9_1", + "CMT_TOP_IMUX21_7", + "CMT_PHASER_B_TOMMCM_OCLKDIV", + "CMT_TOP_IMUX25_7", + "CMT_TOP_SW4A2_5", + "CMT_TOP_SE4C1_5", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_LH4_7", + "CMT_TOP_IMUX20_5", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_PHASER_OUT_DB_TESTOUT3", + "CMT_TOP_NE4C2_4", + "CMT_TOP_NE4C2_3", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_WW4A1_8", + "CMT_TOP_WW4B1_0", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_BYP7_5", + "CMT_TOP_NE2A0_5", + "CMT_TOP_IMUX23_7", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_TOP_EE4A0_2", + "CMT_PHASER_IN_DB_COUNTERREADEN", + "CMT_TOP_SW4END3_8", + "CMT_TOP_EE4A2_7", + "CMT_TOP_IMUX20_6", + "CMT_TOP_LH9_3", + "CMT_TOP_EE4B3_0", + "CMT_TOP_WW4END3_0", + "CMT_TOP_EE2A0_8", + "CMT_TOP_WW2A0_1", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_IMUX45_7", + "CMT_TOP_IMUX19_2", + "CMT_TOP_NW4END0_8", + "CMT_TOP_MONITOR_N_0", + "CMT_PHASER_OUT_B_RDEN_TOFIFO", + "CMT_TOP_WW4B2_3", + "CMT_TOP_IMUX23_0", + "CMT_TOP_IMUX42_5", + "CMT_TOP_EE2BEG3_1", + "CMT_LR_LOWER_T_CLK_IN2_HCLK", + "CMT_TOP_LH6_8", + "CMT_TOP_EE2BEG3_6", + "CMT_PHASER_IN_DB_SYNCIN", + "CMT_TOP_WL1END2_7", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_WL1END0_0", + "CMT_TOP_SW4END3_6", + "CMT_PHASER_IN_CA_RSTDQSFIND", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_SW4A0_3", + "CMT_TOP_FAN0_2", + "CMT_TOP_WW2END2_0", + "CMT_TOP_IMUX18_3", + "CMT_TOP_IMUX27_7", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_FAN1_1", + "CMT_TOP_NW2A3_8", + "CMT_TOP_BYP5_6", + "CMT_TOP_IMUX27_8", + "CMT_PHASER_OUT_CA_DTSBUS0", + "CMT_TOP_IMUX34_3", + "CMT_TOP_LH7_1", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_IMUX43_5", + "CMT_TOP_FAN0_0", + "CMT_PHASER_IN_DB_STG1INCDEC", + "CMT_TOP_IMUX41_4", + "CMT_PHASER_IN_DB_TESTIN2", + "CMT_TOP_IMUX33_0", + "CMT_PHASER_IN_DB_ICLKDIV", + "CMT_TOP_WR1END1_1", + "CMT_TOP_WW4END3_6", + "CMT_TOP_WW4B3_7", + "CMT_PHASER_OUT_A_OCLK1X_90", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_SW4A0_7", + "CMT_TOP_SE2A3_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "CMT_TOP_SW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_SE4C0_0", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_IMUX6_2", + "CMT_PHASER_BOT_REFMUX_2", + "CMT_PHASER_OUT_CA_SCANCLK", + "CMT_PHASER_OUT_DB_OCLKDIV", + "CMT_TOP_OCLKDIV_2", + "CMT_TOP_WW4A1_6", + "CMT_PHASER_IN_DB_TESTOUT1", + "CMT_TOP_WW4B3_4", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX5_3", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_WW4C2_5", + "CMT_TOP_IMUX40_0", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_EE2A2_8", + "CMT_TOP_LH5_0", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_NE2A3_7", + "CMT_PHASER_OUT_DB_TESTIN3", + "CMT_TOP_ER1BEG1_2", + "CMT_TOP_EE4A1_4", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX11_0", + "CMT_TOP_WW2END3_5", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_LH7_8", + "CMT_TOP_NE4C1_3", + "CMT_TOP_CTRL1_6", + "CMT_TOP_IMUX31_3", + "CMT_TOP_IMUX3_5", + "CMT_TOP_LH4_5", + "CMT_TOP_BYP7_4", + "CMT_TOP_IMUX37_3", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_PHASER_IN_CA_TESTIN9", + "CMT_TOP_CLK1_0", + "CMT_TOP_IMUX1_5", + "CMT_TOP_LH9_4", + "CMT_TOP_WW4C0_0", + "CMT_TOP_WW4A0_5", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_SE4C2_1", + "CMT_PHASER_IN_DB_TESTIN8", + "CMT_TOP_IMUX3_8", + "CMT_TOP_WW2A1_5", + "CMT_TOP_EE2A3_1", + "CMT_TOP_SE2A0_4", + "CMT_TOP_IMUX28_0", + "CMT_TOP_IMUX15_1", + "CMT_PHASER_IN_DB_ISERDESRST", + "CMT_TOP_IMUX6_3", + "CMT_TOP_EE4B2_7", + "CMT_PHASER_BOT_OBURSTPENDING0", + "CMT_TOP_IMUX18_2", + "CMT_PHASER_IN_CA_STG1REGR1", + "CMT_TOP_WW2END0_1", + "CMT_PHASER_OUT_DB_RST", + "CMT_PHASER_IN_CA_FINEENABLE", + "CMT_TOP_BYP3_0", + "CMT_TOP_BYP4_3", + "CMT_TOP_NE2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_PHASER_IN_B_ICLKDIV", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_WR1END0_7", + "CMT_TOP_IMUX24_5", + "CMT_TOP_FAN2_1", + "CMT_TOP_EE2A3_8", + "CMT_TOP_EE4A2_8", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_IMUX5_6", + "CMT_PHASER_IN_DB_TESTIN10", + "CMT_TOP_WW4C0_6", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_CTRL0_4", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SW4END0_6", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_BYP6_5", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "CMT_TOP_ER1BEG3_5", + "CMT_PHASER_OUT_CA_TESTIN10", + "CMT_TOP_IMUX37_5", + "CMT_TOP_IMUX37_8", + "CMT_PHASER_IN_DB_STG1REGL2", + "CMT_TOP_NW4A3_7", + "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "CMT_TOP_EE4C0_0", + "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "CMT_TOP_WW4END2_1", + "CMT_PHASER_IN_CA_STG1INCDEC", + "CMT_TOP_SE2A3_5", + "CMT_TOP_EE4A1_6", + "CMT_TOP_BYP7_7", + "CMT_TOP_SW4END1_0", + "CMT_TOP_IMUX29_5", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_IMUX35_3", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_IMUX25_5", + "CMT_PHASER_IN_A_RCLK0", + "CMT_TOP_WW4A2_3", + "CMT_PHASER_IN_DB_PHASELOCKED", + "CMT_TOP_WW4A3_4", + "CMT_TOP_IMUX10_4", + "CMT_TOP_WW4END2_6", + "CMT_PHASER_IN_DB_TESTIN11", + "CMT_PHASER_OUT_CA_BURSTPENDING", + "CMT_TOP_IMUX26_6", + "CMT_TOP_EE4A3_0", + "CMT_PHASER_IN_CA_DIVIDERST", + "CMT_TOP_IMUX46_8", + "CMT_TOP_BYP4_0", + "CMT_TOP_EE2A1_5", + "CMT_TOP_SW4END3_1", + "CMT_TOP_IMUX18_4", + "CMT_TOP_EL1BEG1_6", + "CMT_TOP_IMUX4_4", + "CMT_TOP_NW4END3_3", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_WW4C1_2", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_PHASER_OUT_DB_ENCALIB1", + "CMT_TOP_WW2A2_3", + "CMT_TOP_IMUX22_0", + "CMT_PHASER_B_OCLKDIV_TOIOI", + "CMT_TOP_IMUX28_3", + "CMT_TOP_SE2A1_1", + "CMT_TOP_IMUX29_6", + "CMT_TOP_LH6_1", + "CMT_TOP_LH7_3", + "CMT_PHASER_IN_DB_RCLK", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_TOP_WR1END0_4", + "CMT_TOP_EE2A0_4", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_EE4C0_6", + "CMT_TOP_NE2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH6_0", + "CMT_PHASER_IN_CA_TESTOUT3", + "CMT_TOP_IMUX24_0", + "CMT_TOP_WW4C0_7", + "CMT_TOP_SE4BEG2_2", + "CMT_PHASER_OUT_CA_SYNCIN", + "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "CMT_TOP_EL1BEG1_4", + "CMT_PHASER_IN_CA_STG1REGR4", + "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "CMT_TOP_LH3_5", + "CMT_TOP_NE4C0_4", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_SW2A3_3", + "CMT_TOP_SW4END0_1", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_SW2A1_7", + "CMT_PHASER_IN_DB_SCANENB", + "CMT_TOP_EE4B1_0", + "CMT_TOP_NE4C0_2", + "CMT_TOP_NE2A3_2", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "CMT_TOP_EE4B1_6", + "CMT_TOP_SE4C0_7", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_BYP3_2", + "CMT_TOP_SW4A1_8", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_WR1END3_3", + "CMT_TOP_MONITOR_P_1", + "CMT_TOP_CLK0_2", + "CMT_TOP_LH8_8", + "CMT_TOP_SW4A3_6", + "CMT_TOP_LH10_1", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_IMUX31_8", + "CMT_TOP_EE2A3_0", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_IMUX13_2", + "CMT_TOP_FAN3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_TOP_IMUX39_4", + "CMT_PHASER_IN_DB_SCANMODEB", + "CMT_TOP_SW2A1_4", + "CMT_TOP_MONITOR_P_3", + "CMT_TOP_EE4B1_7", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_WW4A0_7", + "CMT_TOP_IMUX3_4", + "CMT_TOP_ICLK_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "CMT_TOP_SE2A1_2", + "CMT_PHASER_OUT_CA_FINEENABLE", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_NE2A0_4", + "CMT_PHASER_OUT_DB_SCANMODEB", + "CMT_TOP_LH9_0", + "CMT_PHASER_IN_DB_DIVIDERST", + "CMT_TOP_IMUX22_3", + "CMT_TOP_IMUX27_6", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_IMUX31_0", + "CMT_TOP_IMUX25_6", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "CMT_TOP_LH2_3", + "CMT_TOP_IMUX29_8", + "CMT_TOP_NE2A1_4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "CMT_TOP_EE4BEG3_0", + "CMT_TOP_WW2END1_7", + "CMT_TOP_NE4C1_4", + "CMT_TOP_EE4B0_7", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_IMUX2_4", + "CMT_PHASER_OUT_CA_TESTIN8", + "CMT_TOP_BYP1_0", + "CMT_TOP_EE4C1_1", + "CMT_TOP_IMUX22_4", + "CMT_TOP_SE4C1_0", + "CMT_TOP_SW2A0_4", + "CMT_PHASER_OUT_CA_FREQREFCLK", + "CMT_TOP_FAN7_3", + "CMT_PHASER_IN_A_ICLKDIV", + "CMT_TOP_WW4A0_6", + "CMT_PHASER_IN_DB_SYSCLK", + "CMT_TOP_WW2END2_1", + "CMT_TOP_IMUX45_5", + "CMT_TOP_BYP6_4", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_TOP_BYP3_5", + "CMT_TOP_EE2A0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_LH8_4", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_EE4C2_2", + "CMT_TOP_WW4END2_0", + "CMT_TOP_EE4C0_1", + "CMT_PHASER_OUT_CA_CTSBUS1", + "CMT_TOP_CTRL1_5", + "CMT_TOP_CTRL0_5", + "CMT_TOP_WW2END0_6", + "CMT_PHASERREF_DOWN_PHASERIN_A", + "CMT_TOP_IMUX1_3", + "CMT_TOP_WW2END0_7", + "CMT_TOP_FAN5_8", + "CMT_TOP_WW4C1_0", + "CMT_PHASER_OUT_DB_TESTOUT2", + "CMT_TOP_WL1END2_3", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_LH10_7", + "CMT_TOP_SE4C0_1", + "CMT_TOP_WW4C1_7", + "CMT_TOP_IMUX10_3", + "CMT_TOP_SE2A0_5", + "CMT_PHASER_OUT_CA_TESTIN6", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_WR1END3_8", + "CMT_TOP_EE4A2_2", + "CMT_TOP_IMUX47_1", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_IMUX10_6", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_NE4C1_0", + "CMT_PHASER_IN_DB_STG1READ", + "CMT_TOP_WW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BYP6_6", + "CMT_TOP_BYP0_0", + "CMT_TOP_EE4B2_2", + "CMT_TOP_FAN7_7", + "CMT_PHASER_OUT_DB_TESTIN6", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_WW4A0_4", + "CMT_TOP_NE4C0_3", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_WW4A3_0", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_OCLKDIV_8", + "CMT_TOP_SE4C1_1", + "CMT_TOP_LH2_1", + "CMT_TOP_ER1BEG0_6", + "CMT_TOP_IMUX46_1", + "CMT_TOP_IMUX42_1", + "CMT_TOP_SW4A1_6", + "CMT_PHASER_IN_DB_STG1REGL8", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_IMUX30_8", + "CMT_TOP_SW2A1_0", + "CMT_TOP_LH12_0", + "CMT_PHASER_B_OCLK_TOIOI", + "CMT_TOP_CLK0_1", + "CMT_TOP_BYP5_4", + "CMT_TOP_IMUX45_2", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_BYP1_8", + "CMT_TOP_WW4C2_6", + "CMT_TOP_IMUX19_5", + "CMT_TOP_WW4C2_1", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_IMUX42_0", + "CMT_TOP_NW4END0_1", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_FAN7_1", + "CMT_TOP_LH9_8", + "CMT_PHASER_IN_DB_TESTOUT2", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_PHASER_IN_CA_STG1REGL4", + "CMT_TOP_NW2A2_7", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_WW2A3_0", + "CMT_TOP_SW4END0_5", + "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "CMT_TOP_IMUX29_1", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_IMUX9_5", + "CMT_TOP_SW4A0_2", + "CMT_TOP_WW2END1_5", + "CMT_TOP_WW2A2_8", + "CMT_TOP_LH1_7", + "CMT_TOP_OCLK_8", + "CMT_TOP_NW4A1_6", + "CMT_TOP_BYP2_1", + "CMT_TOP_IMUX46_7", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_PHASER_IN_B_RCLK1", + "CMT_TOP_IMUX13_0", + "CMT_TOP_IMUX30_7", + "MMCM_CLK_FREQBB_REBUFOUT0", + "CMT_TOP_IMUX8_3", + "CMT_TOP_WW4A0_3", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_FAN2_0", + "CMT_TOP_IMUX14_7", + "CMT_TOP_NW2A2_0", + "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "CMT_TOP_SE4C0_5", + "CMT_PHASER_IN_CA_PHASELOCKED", + "CMT_TOP_EE2A0_5", + "CMT_TOP_CTRL1_0", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_TOP_WW4A0_1", + "CMT_PHASER_IN_DB_STG1REGL0", + "CMT_TOP_SW4END3_4", + "CMT_TOP_FAN3_0", + "CMT_TOP_LH2_7", + "CMT_TOP_SE2A2_7", + "CMT_TOP_IMUX30_2", + "CMT_TOP_SW2A1_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_FAN3_3", + "CMT_TOP_IMUX2_5", + "CMT_TOP_IMUX22_8", + "CMT_TOP_IMUX28_4", + "CMT_TOP_LH3_7", + "CMT_PHASER_IN_CA_STG1REGL3", + "CMT_TOP_EL1BEG3_7", + "CMT_TOP_LH11_0", + "CMT_TOP_IMUX43_8", + "CMT_TOP_LH10_5", + "CMT_TOP_IMUX15_5", + "CMT_PHASER_OUT_DB_DQSBUS0", + "CMT_TOP_NE4BEG2_5", + "CMT_TOP_IMUX13_8", + "CMT_PHASER_IN_CA_STG1REGL1", + "CMT_TOP_EE4C0_5", + "CMT_TOP_IMUX2_0", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_PHASER_OUT_CA_OCLKDELAYED", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_NE2A0_0", + "CMT_TOP_SW4END1_1", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_NE2A2_6", + "CMT_TOP_LH12_7", + "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "CMT_TOP_SW2A2_2", + "CMT_TOP_WR1END3_7", + "CMT_TOP_WL1END1_7", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_OCLK_4", + "CMT_TOP_LH11_1", + "CMT_TOP_EE4C1_2", + "CMT_TOP_BYP0_4", + "CMT_TOP_FAN4_0", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_PHASER_OUT_CA_FINEINC", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_WW2A2_4", + "CMT_TOP_FAN4_4", + "CMT_TOP_WW4A1_3", + "CMT_TOP_LH5_2", + "CMT_TOP_IMUX17_8", + "CMT_TOP_IMUX36_7", + "CMT_TOP_BYP1_7", + "CMT_TOP_IMUX4_5", + "CMT_TOP_IMUX7_8", + "CMT_TOP_EE4C0_4", + "CMT_TOP_EL1BEG2_1", + "CMT_TOP_BYP7_0", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_BYP6_2", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_ICLK_7", + "CMT_TOP_EE4C2_8", + "CMT_TOP_LH11_3", + "CMT_PHASER_OUT_CA_OSERDESRST", + "CMT_PHASER_IN_CA_ENSTG1", + "CMT_TOP_IMUX14_6", + "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "CMT_TOP_IMUX32_1", + "CMT_TOP_IMUX11_4", + "CMT_TOP_SW2A2_4", + "CMT_LR_LOWER_T_CLK_MMCM12", + "CMT_PHASER_BOT_SYNC_BB", + "CMT_TOP_EE4C3_7", + "CMT_PHASER_OUT_DB_TESTOUT0", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_WW4B3_0", + "CMT_TOP_IMUX10_1", + "CMT_TOP_NE4C3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "CMT_LR_LOWER_T_CLK_MMCM3", + "CMT_TOP_IMUX10_5", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_WW2END1_1", + "CMT_TOP_FAN1_7", + "CMT_TOP_IMUX23_2", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_IMUX6_4", + "CMT_TOP_IMUX5_0", + "CMT_TOP_ICLK_6", + "CMT_TOP_IMUX22_1", + "CMT_TOP_WW4B0_8", + "CMT_TOP_OCLKDIV_6", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_TOP_NW4A3_1", + "CMT_TOP_IMUX27_0", + "CMT_TOP_IMUX43_7", + "CMT_TOP_SE4C2_8", + "CMT_TOP_EE2BEG0_4", + "CMT_PHASER_OUT_CA_TESTIN9", + "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "CMT_TOP_SE4C2_4", + "CMT_PHASER_IN_A_ICLK", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_WR1END3_0", + "CMT_TOP_SE2A2_1", + "CMT_TOP_NW4END1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_EE2BEG0_7", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_IMUX38_7", + "CMT_PHASER_OUT_CA_COARSEINC", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX42_7", + "CMT_TOP_SW4A2_7", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_EE2BEG2_4", + "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "CMT_TOP_LH1_2", + "CMT_TOP_IMUX35_7", + "CMT_LR_LOWER_T_CLK_MMCM0", + "CMT_PHASER_OUT_DB_TESTIN8", + "CMT_TOP_IMUX30_3", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_WR1END1_6", + "CMT_TOP_FAN3_7", + "CMT_TOP_SW2A2_5", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_NW2A1_8", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_EE4B2_1", + "CMT_PHASERREF_DOWN_PHASERIN_B", + "CMT_TOP_SW2A2_0", + "CMT_TOP_SW4A1_1", + "CMT_TOP_NW4END2_3", + "CMT_TOP_FAN4_2", + "CMT_PHASERA_DQSBUS1", + "CMT_TOP_SW2A0_8", + "CMT_TOP_IMUX43_0", + "CMT_TOP_EE4B3_7", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_IMUX44_3", + "CMT_TOP_WW4END0_8", + "CMT_TOP_SW4A1_4", + "CMT_PHASER_OUT_CA_SCANMODEB", + "CMT_TOP_SE2A0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_BYP2_3", + "CMT_PHASER_BOT_IRANKB1", + "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "CMT_TOP_IMUX40_3", + "CMT_TOP_IMUX29_0", + "CMT_TOP_FAN6_0", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_IMUX43_2", + "CMT_TOP_IMUX11_6", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_EE4B1_1", + "CMT_PHASER_IN_CA_ISERDESRST", + "CMT_PHASER_IN_DB_STG1REGL5", + "CMT_TOP_NW2A2_8", + "CMT_TOP_BYP4_2", + "CMT_TOP_NE4BEG3_8", + "CMT_PHASER_IN_CA_STG1REGL2", + "CMT_TOP_WW2A0_3", + "CMT_TOP_WW2A2_5", + "CMT_TOP_SW4END1_6", + "CMT_PHASER_BOT_REFMUX_1", + "CMT_TOP_EE4B2_5", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_WW2A2_0", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_IMUX26_7", + "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "CMT_TOP_IMUX1_7", + "CMT_TOP_IMUX23_6", + "CMT_TOP_NE4C3_2", + "CMT_TOP_WW2END3_3", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_SE4BEG3_4", + "CMT_TOP_IMUX5_4", + "CMT_TOP_IMUX6_8", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_PHASER_OUT_CA_OCLK", + "CMT_TOP_WW2END3_2", + "CMT_TOP_IMUX4_3", + "CMT_TOP_NE4C2_1", + "CMT_TOP_EE4C1_6", + "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "CMT_TOP_NW4END3_7", + "CMT_PHASER_OUT_CA_TESTIN15", + "CMT_TOP_IMUX13_5", + "CMT_TOP_IMUX46_6", + "CMT_TOP_WW4END0_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_SW4END2_2", + "CMT_TOP_LH12_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_CLK1_2", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_NE2A3_8", + "CMT_PHASER_IN_DB_RANKSELPHY1", + "CMT_TOP_EL1BEG0_3", + "CMT_PHASER_OUT_CA_MEMREFCLK", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_LR_LOWER_T_CLK_MMCM5", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_SW4A1_3", + "CMT_TOP_IMUX15_7", + "CMT_TOP_NW4A2_8", + "CMT_TOP_WR1END1_5", + "CMT_TOP_SE4C2_5", + "CMT_TOP_SW4END2_0", + "CMT_TOP_WW4END1_5", + "CMT_TOP_NW4A0_5", + "CMT_TOP_EE2A2_2", + "CMT_TOP_ER1BEG3_3", + "CMT_TOP_WW4A0_2", + "CMT_TOP_IMUX37_6", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_FAN2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_IMUX41_2", + "CMT_TOP_IMUX20_2", + "CMT_TOP_IMUX0_0", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_SW4END2_6", + "CMT_TOP_IMUX45_1", + "CMT_PHASER_OUT_CA_TESTIN4", + "CMT_TOP_NW2A3_4", + "CMT_TOP_WW4B3_3", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_IMUX42_6", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_LH3_1", + "CMT_PHASER_OUT_B_OCLK", + "CMT_TOP_NE4C3_3", + "CMT_TOP_BYP2_0", + "CMT_TOP_EE4C0_2", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "MMCM_CLK_FREQBB_REBUFOUT1", + "CMT_TOP_LH12_6", + "CMT_PHASER_IN_DB_TESTIN9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_IMUX35_6", + "CMT_TOP_EE4A1_1", + "CMT_TOP_IMUX26_3", + "CMT_TOP_SW4A2_0", + "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "CMT_PHASER_IN_DB_ENCALIB0", + "CMT_TOP_FAN3_6", + "CMT_TOP_SW4END2_1", + "CMT_PHASER_OUT_DB_DQSBUS1", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_IMUX47_0", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_PHASER_IN_CA_SELCALORSTG1", + "CMT_TOP_FAN5_5", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_WW2A1_3", + "CMT_TOP_FAN2_5", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_SE4C0_3", + "CMT_TOP_IMUX45_4", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_PHASER_OUT_DB_SCANIN", + "CMT_TOP_WW2END1_8", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_WR1END2_0", + "CMT_TOP_NE2A1_0", + "CMT_PHASER_OUT_CA_TESTIN1", + "CMT_TOP_EE2A3_7", + "CMT_TOP_IMUX19_0", + "CMT_TOP_WR1END0_0", + "CMT_TOP_LH1_8", + "CMT_TOP_NE2A3_3", + "CMT_TOP_WW2A0_7", + "CMT_TOP_WW4C1_8", + "CMT_TOP_NE4C0_5", + "CMT_TOP_IMUX8_6", + "CMT_TOP_WL1END2_2", + "CMT_PHASER_OUT_DB_TESTIN5", + "CMT_TOP_EE4BEG1_4", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_EE2BEG2_8", + "CMT_TOP_EE4A3_4", + "CMT_PHASER_IN_DB_TESTIN12", + "CMT_TOP_SW4END0_2", + "CMT_TOP_BYP1_2", + "CMT_TOP_SW4A0_6", + "CMT_TOP_BYP5_8", + "CMT_TOP_FAN5_4", + "CMT_PHASER_BOT_IRANKB0", + "CMT_TOP_WW4END2_3", + "CMT_TOP_IMUX41_7", + "CMT_TOP_IMUX25_2", + "CMT_TOP_EE4A3_1", + "CMT_TOP_IMUX12_8", + "CMT_TOP_IMUX24_2", + "CMT_TOP_WW2A3_3", + "CMT_TOP_IMUX1_6", + "CMT_TOP_IMUX6_0", + "CMT_TOP_IMUX21_2", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_CLK1_1", + "CMT_TOP_EE4B2_0", + "CMT_TOP_WW4A2_0", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_PHASER_IN_CA_TESTIN4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "CMT_TOP_SW2A0_7", + "CMT_TOP_CLK0_8", + "CMT_TOP_IMUX44_0", + "CMT_TOP_BYP4_6", + "CMT_TOP_IMUX7_0", + "CMT_PHASER_OUT_DB_TESTIN11", + "CMT_TOP_IMUX9_4", + "CMT_TOP_EE4A0_4", + "CMT_TOP_NE2A2_0", + "CMT_TOP_LH9_6", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_WW2END2_7", + "CMT_PHASER_IN_DB_STG1REGL7", + "CMT_TOP_SW2A3_7", + "CMT_TOP_SE4BEG1_1", + "CMT_TOP_NW4END3_8", + "CMT_TOP_NW4A1_2", + "CMT_TOP_SE2A0_7", + "CMT_TOP_NW4END3_5", + "CMT_TOP_IMUX21_5", + "CMT_TOP_WW4B1_3", + "CMT_TOP_WW4END3_4", + "CMT_PHASER_OUT_CA_ENCALIB0", + "CMT_TOP_WR1END2_8", + "CMT_PHASER_OUT_DB_OCLK", + "CMT_TOP_WL1END0_8", + "CMT_TOP_NW2A0_2", + "CMT_TOP_SE2A3_0", + "CMT_TOP_EE4B0_3", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_FAN1_3", + "CMT_TOP_NW4A3_6", + "CMT_TOP_SE2A1_4", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "CMT_TOP_SE4C0_6", + "CMT_TOP_SE4C1_7", + "CMT_TOP_IMUX17_4", + "CMT_PHASER_OUT_DB_RDENABLE", + "CMT_TOP_BYP0_8", + "CMT_PHASER_OUT_A_RDCLK_TOFIFO", + "CMT_TOP_EE4A3_3", + "CMT_TOP_LH10_6", + "CMT_TOP_NW4A3_2", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_R_TOP_LOWER_B_CLKINT_1", + "CMT_TOP_LH3_4", + "CMT_TOP_SW4END2_4", + "CMT_TOP_WL1END0_6", + "CMT_TOP_LH8_0", + "CMT_TOP_IMUX24_6", + "CMT_TOP_IMUX45_8", + "CMT_TOP_IMUX33_7", + "CMT_TOP_IMUX28_7", + "CMT_TOP_IMUX37_2", + "CMT_TOP_NE4BEG3_4", + "CMT_PHASER_OUT_CA_PHASEREFCLK", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_TOP_EE4B3_6", + "CMT_TOP_NW4END2_5", + "CMT_TOP_EE4A1_7", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_IMUX15_3", + "CMT_PHASER_OUT_B_RDCLK_TOFIFO", + "CMT_TOP_EE4B0_5", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_SW4END0_3", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "CMT_LR_LOWER_T_CLK_PERF0", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_LH6_7", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_BYP3_8", + "CMT_TOP_IMUX17_0", + "CMT_BOT_HCLKMUX_CLKINT_0", + "CMT_TOP_NE2A3_1", + "CMT_PHASER_IN_CA_STG1REGR3", + "CMT_TOP_IMUX11_3", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_EE4B2_4", + "CMT_TOP_NW2A3_2", + "CMT_TOP_EE4B3_1", + "CMT_TOP_WW4B3_5", + "CMT_TOP_WW2A3_5", + "CMT_TOP_WW2END2_6", + "CMT_LR_LOWER_T_CLK_PERF2", + "CMT_TOP_SW4END0_7", + "CMT_PHASER_OUT_CA_TESTIN2", + "CMT_PHASER_OUT_DB_TESTIN0", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_SE4C2_2", + "CMT_TOP_WL1END1_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_SE2A1_7", + "CMT_TOP_NE4BEG2_4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "CMT_TOP_WL1END3_5", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_IMUX3_1", + "CMT_PHASER_IN_CA_STG1REGR7", + "CMT_TOP_WW2A3_8", + "CMT_TOP_WW2END3_0", + "CMT_TOP_WR1END2_1", + "CMT_TOP_NW4A1_4", + "CMT_TOP_IMUX30_6", + "CMT_TOP_EL1BEG0_1", + "CMT_TOP_IMUX22_5", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_IMUX20_3", + "CMT_TOP_BYP6_8", + "CMT_TOP_IMUX12_0", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX14_2", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "CMT_TOP_BYP4_4", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_CLK1_7", + "CMT_TOP_NE2A1_1", + "CMT_TOP_IMUX2_3", + "CMT_LR_LOWER_T_CLK_MMCM6", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_IMUX19_3", + "CMT_TOP_IMUX46_5", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_NW4END1_3", + "CMT_TOP_WW4B0_5", + "CMT_TOP_ICLK_8", + "CMT_TOP_NW2A3_5", + "CMT_TOP_WR1END2_3", + "CMT_TOP_IMUX7_6", + "CMT_TOP_SW2A1_2", + "CMT_TOP_BYP2_6", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_IMUX36_2", + "CMT_TOP_WW2END3_1", + "CMT_TOP_BYP3_3", + "CMT_TOP_FAN6_2", + "CMT_TOP_NE4C0_1", + "CMT_TOP_NW2A2_3", + "CMT_PHASER_B_OCLK90_TOIOI", + "CMT_TOP_IMUX40_4", + "CMT_TOP_IMUX11_5", + "CMT_TOP_IMUX47_6", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_TOP_NE4BEG2_2", + "CMT_TOP_SW4A3_4", + "CMT_TOP_FAN7_0", + "CMT_TOP_LH11_5", + "CMT_TOP_IMUX30_5", + "CMT_TOP_SE2A3_1", + "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "CMT_TOP_IMUX30_1", + "CMT_TOP_EE4A3_6", + "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "CMT_PHASER_IN_CA_WRENABLE", + "CMT_TOP_IMUX5_1", + "CMT_TOP_EE4BEG3_6", + "CMT_TOP_SE4C3_2", + "CMT_TOP_SE2A2_0", + "CMT_TOP_NE4C0_7", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_EE4A2_1", + "CMT_TOP_EE4B3_4", + "CMT_TOP_EE4C3_6", + "CMT_TOP_WW4B0_0", + "CMT_TOP_IMUX43_3", + "CMT_PHASER_OUT_CA_TESTOUT0", + "CMT_PHASER_OUT_DB_PHASEREFCLK", + "CMT_TOP_IMUX27_2", + "CMT_TOP_IMUX33_3", + "CMT_TOP_IMUX21_4", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_FAN0_8", + "CMT_TOP_EE4A2_6", + "CMT_TOP_LH5_8", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_FAN2_6", + "CMT_PHASER_IN_CA_TESTIN8", + "CMT_TOP_SE4BEG0_8", + "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "CMT_TOP_WW4END3_1", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_IMUX35_4", + "CMT_TOP_SW2A2_6", + "CMT_TOP_IMUX42_8", + "CMT_TOP_EE2A3_4", + "CMT_TOP_EE4BEG2_6", + "CMT_R_TOP_LOWER_B_CLKINT_0", + "CMT_TOP_IMUX38_8", + "CMT_PHASER_OUT_CA_TESTOUT2", + "CMT_TOP_CLK0_0", + "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_SE2A1_6", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_NW4END0_6", + "CMT_TOP_FAN7_2", + "CMT_TOP_EE2A0_7", + "CMT_TOP_IMUX10_0", + "CMT_PHASER_OUT_DB_TESTIN7", + "CMT_TOP_IMUX43_4", + "CMT_TOP_EE4A0_0", + "CMT_TOP_IMUX36_1", + "CMT_TOP_LH1_0", + "CMT_TOP_WW4A3_6", + "CMT_PHASER_OUT_DB_CTSBUS1", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_IMUX37_1", + "CMT_TOP_EE4C3_5", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_TOP_NE4C3_5", + "CMT_TOP_WW4A3_2", + "CMT_PHASER_IN_DB_ENSTG1", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_BYP5_2", + "CMT_TOP_BYP0_5", + "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_IMUX6_1", + "CMT_TOP_ICLK_2", + "CMT_TOP_IMUX36_4", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LH4_8", + "CMT_TOP_BYP4_1", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_IMUX9_3", + "CMT_TOP_IMUX15_6", + "CMT_PHASER_OUT_DB_BURSTPENDING", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_NE2A3_5", + "CMT_TOP_IMUX7_3", + "CMT_TOP_NE2A1_8", + "CMT_TOP_NW4END1_1", + "CMT_TOP_FAN3_8", + "CMT_PHASER_IN_CA_RST", + "CMT_TOP_LH4_1", + "CMT_PHASER_OUT_DB_FINEENABLE", + "CMT_TOP_LH12_2", + "CMT_PHASER_IN_CA_FINEINC", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX45_0", + "CMT_TOP_EE4C2_5", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_ICLKDIV_6", + "CMT_PHASER_IN_CA_TESTIN10", + "CMT_TOP_EE4C2_3", + "CMT_PHASER_IN_DB_TESTIN5", + "CMT_TOP_WR1END1_8", + "CMT_TOP_IMUX19_8", + "CMT_TOP_IMUX17_6", + "CMT_TOP_WW2A2_6", + "CMT_PHASER_IN_CA_STG1REGR2", + "CMT_TOP_IMUX14_5", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_IMUX34_2", + "CMT_TOP_BYP1_6", + "CMT_TOP_SW4A2_2", + "CMT_TOP_EE4A0_5", + "CMT_TOP_BYP4_5", + "CMT_TOP_WW4A2_8", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NW2A0_5", + "CMT_TOP_NE4BEG3_6", + "CMT_PHASER_IN_CA_SCANIN", + "CMT_TOP_IMUX39_5", + "CMT_TOP_NW4A2_7", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_IMUX38_1", + "CMT_TOP_WW2A0_8", + "CMT_TOP_SW4END1_4", + "CMT_TOP_FAN7_5", + "CMT_TOP_CTRL1_4", + "CMT_TOP_EE4B0_1", + "CMT_TOP_IMUX18_6", + "CMT_TOP_NE4C2_0", + "CMT_TOP_SW2A3_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_IMUX8_1", + "CMT_TOP_WW4A3_7", + "CMT_TOP_OCLK_0", + "CMT_PHASERA_CTSBUS1", + "CMT_TOP_WW4A1_7", + "CMT_TOP_IMUX41_6", + "CMT_TOP_NE4C2_7", + "CMT_TOP_LH4_0", + "CMT_TOP_SW2A2_8", + "CMT_TOP_IMUX20_8", + "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "CMT_TOP_BYP2_7", + "CMT_TOP_SW4A1_2", + "CMT_TOP_FAN3_4", + "CMT_TOP_SW4END3_3", + "CMT_TOP_IMUX16_7", + "CMT_TOP_IMUX15_2", + "CMT_TOP_SE4C3_4", + "CMT_TOP_LH11_7", + "CMT_TOP_SE4C3_3", + "CMT_LR_LOWER_T_CLK_MMCM9", + "CMT_TOP_IMUX12_3", + "CMT_TOP_NW2A3_1", + "CMT_TOP_WW4A1_5", + "CMT_TOP_EE4C1_3", + "CMT_TOP_FAN3_5", + "CMT_TOP_CLK0_5", + "CMT_TOP_WW2END1_4", + "CMT_PHASER_IN_CA_SYNCIN", + "CMT_TOP_WW2A2_7", + "CMT_PHASER_IN_CA_TESTIN11", + "CMT_TOP_OCLK_1", + "CMT_TOP_WL1END3_4", + "CMT_TOP_NW2A1_5", + "CMT_PHASER_OUT_CA_ENCALIB1", + "CMT_TOP_IMUX16_2", + "CMT_TOP_BYP2_5", + "CMT_TOP_IMUX40_2", + "CMT_TOP_WW4B2_8", + "CMT_PHASER_IN_CA_STG1REGL6", + "CMT_TOP_EE4B3_2", + "CMT_TOP_EE4B1_2", + "CMT_TOP_SE4C1_2", + "CMT_BOT_HCLKMUX_CLKINT_1", + "CMT_TOP_NW4END2_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_FAN6_1", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_EE4C1_7", + "CMT_TOP_FAN0_6", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_SW4END2_8", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_SE4C1_6", + "CMT_TOP_IMUX39_6", + "CMT_TOP_IMUX35_2", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_WL1END0_2", + "CMT_PHASER_OUT_CA_TESTIN3", + "CMT_TOP_IMUX18_7", + "CMT_TOP_IMUX44_1", + "CMT_TOP_SE4BEG3_2", + "CMT_PHASER_IN_CA_TESTIN12", + "CMT_TOP_EE2BEG1_8", + "CMT_PHASER_IN_CA_STG1REGL5", + "CMT_TOP_WW2A1_2", + "CMT_TOP_IMUX16_5", + "CMT_PHASER_IN_DB_STG1REGR3", + "CMT_PHASER_OUT_CA_COUNTERREADEN", + "CMT_PHASER_OUT_DB_OCLKDELAYED", + "CMT_TOP_WW4A2_5", + "CMT_TOP_NW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_PHASER_IN_DB_ENCALIBPHY1", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX44_2", + "CMT_TOP_IMUX39_7", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_CTRL0_0", + "CMT_TOP_EL1BEG0_4", + "CMT_TOP_IMUX26_0", + "CMT_TOP_IMUX4_6", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_IMUX1_8", + "CMT_TOP_IMUX38_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_NW2A1_0", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_WW4B3_8", + "CMT_PHASER_IN_CA_SCANOUT", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_EE4B3_3", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_WW4B0_6", + "CMT_PHASER_IN_DB_STG1REGR1", + "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "CMT_TOP_IMUX38_0", + "CMT_TOP_NW2A0_1", + "CMT_TOP_IMUX27_4", + "CMT_TOP_SW2A2_1", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_EE4C1_8", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_EE4C1_4", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_PHASER_IN_DB_TESTOUT3", + "CMT_TOP_BYP1_3", + "CMT_TOP_CTRL0_6", + "CMT_LR_LOWER_T_CLK_MMCM8", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_EL1BEG2_2", + "CMT_PHASER_OUT_DB_TESTIN10", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_BYP2_4", + "CMT_TOP_IMUX17_3", + "CMT_TOP_FAN0_1", + "CMT_PHASER_OUT_DB_TESTOUT1", + "CMT_TOP_NW2A3_6", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_WW4END0_4", + "CMT_TOP_CLK0_7", + "CMT_TOP_WL1END3_0", + "CMT_TOP_IMUX28_2", + "CMT_TOP_IMUX21_8", + "CMT_TOP_IMUX13_7", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_EE2A2_0", + "CMT_TOP_ICLK_4", + "CMT_TOP_IMUX4_0", + "CMT_TOP_IMUX3_6", + "CMT_TOP_BYP7_1", + "CMT_TOP_WW2END0_8", + "CMT_TOP_IMUX42_2", + "CMT_TOP_WW2A3_6", + "CMT_TOP_WW4B0_4", + "CMT_PHASER_OUT_CA_SCANENB", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_SE2A2_5", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_TOP_WW2END1_3", + "CMT_TOP_SE2A3_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_SW4END3_5", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_EE2BEG2_7", + "CMT_PHASER_IN_DB_TESTIN0", + "CMT_TOP_ICLK_0", + "CMT_TOP_EE4BEG2_0", + "CMT_PHASER_OUT_A_RDEN_TOFIFO", + "CMT_TOP_NW4END1_2", + "CMT_TOP_BYP3_4", + "CMT_TOP_SE4C3_0", + "CMT_TOP_IMUX25_8", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX31_7", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_NW2A1_3", + "CMT_TOP_FAN6_4", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_IMUX47_2", + "CMT_TOP_EE2BEG0_1", + "CMT_PHASER_IN_DB_TESTOUT0", + "CMT_TOP_SW4END3_0", + "CMT_TOP_IMUX3_3", + "CMT_TOP_NE2A3_0", + "CMT_PHASER_IN_CA_STG1REGL0", + "CMT_TOP_WW2END1_2", + "CMT_PHASER_IN_CA_RANKSELPHY1", + "CMT_TOP_SE4C1_3", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_CLK0_3", + "CMT_TOP_LH10_4", + "CMT_TOP_BYP0_2", + "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NE4C0_8", + "CMT_PHASER_IN_CA_STG1OVERFLOW", + "CMT_PHASER_IN_DB_SELCALORSTG1", + "CMT_TOP_SW2A2_7", + "CMT_TOP_NW2A1_1", + "CMT_TOP_NW2A2_5", + "CMT_PHASER_IN_B_WREN_TOFIFO", + "CMT_PHASER_IN_DB_SCANIN", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX19_6", + "CMT_TOP_WW4A1_2", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_IMUX25_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_SE4BEG2_5", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_PHASER_BOT_IRANKA0", + "CMT_TOP_NE4C1_7", + "CMT_TOP_EE4C3_8", + "MMCM_CLK_FREQBB_REBUFOUT3", + "CMT_TOP_IMUX4_2", + "CMT_TOP_WW2A1_7", + "CMT_PHASER_IN_CA_TESTIN0", + "CMT_PHASER_IN_CA_SYSCLK", + "CMT_TOP_NW4END0_0", + "CMT_TOP_SW4END0_8", + "CMT_TOP_IMUX0_6", + "CMT_PHASER_OUT_DB_DTSBUS1", + "CMT_TOP_WW4B0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WL1END0_4", + "CMT_TOP_FAN1_5", + "CMT_PHASER_OUT_CA_DIVIDERST", + "CMT_TOP_IMUX35_1", + "CMT_TOP_NE4C1_1", + "CMT_TOP_EE2A1_8", + "CMT_PHASER_IN_CA_TESTIN5", + "CMT_PHASER_IN_DB_STG1REGL3", + "CMT_TOP_WL1END0_5", + "CMT_PHASER_IN_DB_SCANCLK", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "CMT_PHASER_OUT_DB_DIVIDERST", + "CMT_TOP_WW2END2_2", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_IMUX20_1", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_FAN4_7", + "CMT_PHASER_OUT_DB_SCANCLK", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_IMUX36_6", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_WW2END0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_PHASER_OUT_CA_TESTIN5", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_WW4C3_0", + "CMT_TOP_EE4B3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_FAN4_3", + "CMT_TOP_WR1END3_2", + "CMT_PHASER_IN_CA_STG1REGR5", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_LH8_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_IMUX5_7", + "CMT_PHASER_OUT_CA_SCANOUT", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_SW4A3_8", + "CMT_PHASER_OUT_CA_RST", + "CMT_TOP_WW2A0_6", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_WW2A2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_WL1END2_1", + "CMT_PHASERA_DTSBUS0", + "CMT_TOP_IMUX29_7", + "CMT_TOP_NE4C0_0", + "CMT_TOP_NW2A2_1", + "CMT_TOP_WW2END0_4", + "CMT_TOP_EE4B0_4", + "CMT_PHASER_IN_CA_STG1LOAD", + "CMT_TOP_WR1END3_6", + "CMT_TOP_NE4C3_6", + "CMT_PHASERREF_DOWN_PHASEROUT_A", + "CMT_PHASER_B_TOMMCM_ICLK", + "CMT_TOP_OCLK_7", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_PHASER_IN_DB_BURSTPENDING", + "CMT_PHASER_IN_DB_SCANOUT", + "CMT_TOP_WW4B2_2", + "CMT_TOP_ER1BEG2_0", + "CMT_PHASER_IN_CA_SCANMODEB", + "CMT_TOP_NW4A2_3", + "CMT_PHASER_IN_CA_TESTOUT1", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_LH11_4", + "CMT_TOP_LH6_6", + "CMT_TOP_WW4C3_3", + "CMT_TOP_NW4END1_4", + "CMT_PHASER_IN_DB_TESTIN4", + "CMT_TOP_NW2A1_2", + "CMT_TOP_NW2A3_7", + "CMT_TOP_WW4END0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_TOP_FAN4_8", + "CMT_TOP_WW4END0_7", + "CMT_TOP_SW4A3_2", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_IMUX5_8", + "CMT_TOP_IMUX22_7", + "CMT_TOP_WR1END1_2", + "CMT_TOP_SW4A1_5", + "CMT_TOP_IMUX2_6", + "CMT_TOP_BYP4_8", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_IMUX32_6", + "CMT_TOP_SE4C3_5", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_NW2A2_6", + "CMT_TOP_IMUX15_4", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_EE4BEG0_5", + "CMT_PHASER_IN_CA_BURSTPENDING", + "CMT_TOP_WW4A1_0", + "CMT_TOP_BYP5_5", + "CMT_TOP_ICLK_1", + "CMT_TOP_EE2A3_6", + "CMT_TOP_IMUX0_1", + "CMT_TOP_BYP6_7", + "CMT_TOP_BYP0_6", + "CMT_PHASER_OUT_CA_TESTIN11", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_WW4B2_6", + "CMT_TOP_WL1END1_5", + "CMT_TOP_IMUX32_7", + "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "CMT_TOP_LH3_3", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_SW4A2_8", + "CMT_TOP_IMUX30_0", + "CMT_TOP_WL1END3_7", + "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "CMT_TOP_SW4A1_7", + "CMT_TOP_NW2A0_8", + "CMT_TOP_WW4C1_5", + "CMT_TOP_SW2A3_5", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_WW4END1_8", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_SW4A3_3", + "CMT_TOP_IMUX34_6", + "CMT_TOP_SW4A2_4", + "CMT_TOP_WW4A2_2", + "CMT_TOP_NE4C3_1", + "CMT_TOP_IMUX28_1", + "CMT_TOP_IMUX46_4", + "CMT_TOP_NW4A1_7", + "CMT_TOP_WW2END3_4", + "CMT_TOP_IMUX22_6", + "CMT_PHASER_IN_DB_RST", + "CMT_TOP_EE4B1_5", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_EE4B0_6", + "CMT_TOP_IMUX1_4", + "CMT_TOP_SW2A0_0", + "CMT_TOP_SW4A1_0", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_FAN2_2", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_IMUX33_4", + "CMT_PHASER_IN_CA_ICLKDIV", + "CMT_PHASER_OUT_CA_SCANIN", + "CMT_TOP_NW4A1_0", + "CMT_TOP_WW4B0_7", + "CMT_TOP_SE4C0_8", + "CMT_PHASER_BOT_ENCALIB1", + "CMT_TOP_IMUX32_8", + "CMT_TOP_NW4END2_6", + "CMT_TOP_CLK1_4", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_EE2A2_4", + "CMT_TOP_EE2BEG1_3", + "CMT_LR_LOWER_T_CLK_IN1_HCLK", + "CMT_TOP_WW4B2_7", + "CMT_TOP_EE4B1_3", + "CMT_TOP_BYP5_0", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "CMT_PHASER_IN_B_ICLK", + "CMT_TOP_SW4END0_0", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH10_2", + "CMT_TOP_IMUX4_8", + "CMT_TOP_NE4C1_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "CMT_TOP_WW2A1_1", + "CMT_TOP_WW4END1_1", + "CMT_TOP_EE4A1_0", + "CMT_TOP_IMUX37_0", + "CMT_TOP_WL1END3_1", + "CMT_PHASER_IN_DB_MEMREFCLK", + "CMT_TOP_IMUX16_8", + "CMT_TOP_IMUX9_6", + "CMT_TOP_IMUX42_3", + "CMT_PHASER_OUT_DB_TESTIN15", + "CMT_PHASER_OUT_DB_OSERDESRST", + "CMT_TOP_IMUX39_2", + "CMT_TOP_WR1END0_6", + "CMT_TOP_IMUX37_7", + "CMT_TOP_IMUX16_3", + "CMT_PHASER_IN_DB_STG1LOAD", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_PHASER_IN_CA_ENCALIBPHY1", + "CMT_TOP_IMUX1_2", + "CMT_PHASER_IN_CA_EDGEADV", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_TOP_IMUX6_6", + "CMT_TOP_IMUX22_2", + "CMT_PHASER_OUT_CA_DTSBUS1", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_WW4B2_4", + "CMT_TOP_ER1BEG2_2", + "MMCM_CLK_FREQBB_REBUFOUT2", + "CMT_TOP_SE4C3_6", + "CMT_TOP_IMUX44_4", + "CMT_PHASER_IN_DB_STG1REGR4", + "CMT_LR_LOWER_T_CLK_MMCM4", + "CMT_TOP_IMUX17_7", + "CMT_TOP_CTRL0_1", + "CMT_TOP_CTRL0_8", + "CMT_TOP_WW4B2_0", + "CMT_TOP_MONITOR_P_6", + "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "CMT_PHASER_IN_CA_TESTOUT2", + "CMT_TOP_LH12_5", + "CMT_PHASER_IN_DB_RSTDQSFIND", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "CMT_TOP_IMUX12_6", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_IMUX23_4", + "CMT_TOP_IMUX29_2", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_BYP6_1", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_NE4BEG1_5", + "CMT_PHASER_IN_CA_PHASEREFCLK", + "CMT_TOP_FAN1_4", + "CMT_TOP_NE2A3_6", + "CMT_TOP_IMUX38_3", + "CMT_TOP_ICLK_3", + "CMT_TOP_WW2A0_5", + "CMT_TOP_NE2A1_3", + "CMT_TOP_IMUX7_4", + "CMT_TOP_CLK0_4", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_SE2A3_4", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_IMUX28_6", + "CMT_PHASER_B_ICLKDIV_TOIOI", + "CMT_TOP_WW4A3_8", + "CMT_TOP_EE2A0_0", + "CMT_TOP_SE2A1_0", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_TOP_NW2A0_3", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_SE2A1_5", + "CMT_TOP_WW4B1_2", + "CMT_TOP_CTRL1_3", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "CMT_TOP_EE4A3_8", + "CMT_TOP_NW4A0_2", + "CMT_TOP_NW4A1_8", + "CMT_TOP_IMUX26_5", + "CMT_TOP_IMUX40_6", + "CMT_TOP_LH6_3", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_WR1END2_4", + "CMT_TOP_NW4END3_2", + "CMT_TOP_IMUX39_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_IMUX20_4", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_LR_LOWER_T_CLK_PERF3", + "CMT_TOP_NW4END0_7", + "CMT_TOP_WW4END2_7", + "CMT_TOP_BYP4_7", + "CMT_PHASER_DOWN_PHASERREF0", + "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_PHASER_OUT_DB_FINEINC", + "CMT_TOP_NE2A2_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "CMT_TOP_SW4END0_4", + "CMT_TOP_CTRL1_2", + "CMT_TOP_WW4END2_2", + "CMT_TOP_IMUX34_0", + "CMT_TOP_NE2A1_6", + "CMT_TOP_SW2A3_1", + "CMT_TOP_IMUX38_2", + "CMT_TOP_BYP3_7", + "CMT_TOP_LH3_0", + "CMT_TOP_IMUX0_8", + "CMT_TOP_IMUX31_6", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_TOP_WW4END3_7", + "CMT_TOP_NE4BEG2_6", + "CMT_PHASER_IN_CA_FINEOVERFLOW", + "CMT_TOP_OCLK_3", + "CMT_PHASER_BOT_IBURSTPENDING1", + "CMT_TOP_FAN1_2", + "CMT_PHASER_OUT_CA_TESTOUT1", + "CMT_TOP_IMUX11_2", + "CMT_TOP_SW4A0_1", + "CMT_TOP_SW4A0_5", + "CMT_TOP_EE4B2_3", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "CMT_TOP_IMUX9_7", + "CMT_TOP_NE2A2_1", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_EE2A2_3", + "CMT_TOP_WR1END3_1", + "CMT_TOP_SW2A1_5", + "CMT_TOP_WW2A0_0", + "CMT_TOP_WR1END0_5", + "CMT_TOP_CTRL1_8", + "CMT_TOP_ER1BEG2_8", + "CMT_TOP_NW4A2_5", + "CMT_TOP_NW4A0_0", + "CMT_PHASER_OUT_CA_SYSCLK", + "CMT_PHASER_IN_DB_STG1REGL1", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_IMUX41_1", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX11_7", + "CMT_TOP_NW4A0_8", + "CMT_TOP_WW4B2_5", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "CMT_TOP_IMUX41_8", + "CMT_TOP_SW2A3_8", + "CMT_TOP_IMUX14_3", + "CMT_TOP_IMUX17_1", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_WW4A2_4", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_WW4B3_6", + "CMT_TOP_WW4END3_8", + "CMT_TOP_IMUX4_1", + "CMT_TOP_NE4BEG0_6", + "CMT_PHASER_BOT_ENCALIB0", + "CMT_TOP_IMUX23_1", + "CMT_TOP_BYP7_2", + "CMT_TOP_NW4A0_3", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_TOP_IMUX33_2", + "CMT_TOP_EE2A0_2", + "CMT_PHASER_IN_A_WREN_TOFIFO", + "CMT_PHASER_IN_DB_FREQREFCLK", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_PHASER_IN_CA_STG1REGR0", + "CMT_TOP_WW2END2_8", + "CMT_TOP_NE2A0_7", + "CMT_TOP_WW4END3_3", + "CMT_TOP_LH2_6", + "CMT_PHASER_OUT_DB_SYSCLK", + "CMT_TOP_BYP0_7", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_BYP2_8", + "CMT_PHASER_BOT_IBURSTPENDING0", + "CMT_TOP_WW4A0_0", + "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "CMT_TOP_NE2A1_7", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_PHASER_IN_CA_TESTIN1", + "CMT_TOP_WR1END3_5", + "CMT_TOP_SE4BEG1_3", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_WW4END3_2", + "CMT_TOP_WL1END3_3", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_IMUX34_8", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_NW4A3_8", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_CTRL0_7", + "CMT_TOP_WW4C0_5", + "CMT_TOP_IMUX13_1", + "CMT_TOP_IMUX11_1", + "CMT_TOP_IMUX8_7", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_NE2A0_1", + "CMT_TOP_WW4END0_0", + "CMT_TOP_SE2A2_3", + "CMT_TOP_FAN5_2", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_IMUX39_8", + "CMT_TOP_NE2A3_4", + "CMT_TOP_NE4C1_2", + "CMT_TOP_EE4C2_6", + "CMT_TOP_SW2A0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_IMUX30_4", + "CMT_PHASER_DOWN_DQS_TO_PHASER_B", + "CMT_TOP_CTRL1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_PHASER_IN_CA_MEMREFCLK", + "CMT_TOP_LH8_5", + "CMT_TOP_EE4C3_4", + "CMT_TOP_BYP1_5", + "CMT_TOP_IMUX10_8", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_PHASER_B_TOMMCM_OCLK1X_90", + "CMT_TOP_MONITOR_N_3", + "CMT_PHASER_OUT_CA_TESTIN12", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_IMUX44_8", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_WL1END3_6", + "CMT_TOP_WL1END0_3", + "CMT_LR_LOWER_T_CLK_IN3_HCLK", + "CMT_TOP_LH1_1", + "CMT_TOP_IMUX19_4", + "CMT_TOP_IMUX18_8", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_IMUX4_7", + "CMT_PHASER_IN_CA_COUNTERREADEN", + "CMT_PHASERA_CTSBUS0", + "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "CMT_PHASER_B_ICLK_TOIOI", + "CMT_TOP_IMUX24_4", + "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "CMT_LR_LOWER_T_CLK_PERF1", + "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "CMT_TOP_LH7_4", + "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_IMUX19_1", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_NW4A3_5", + "CMT_TOP_FAN2_8", + "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "CMT_PHASER_IN_CA_ICLK", + "CMT_TOP_NW4END0_3", + "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "CMT_TOP_IMUX29_4", + "CMT_TOP_SE4C2_7", + "CMT_TOP_NW2A0_6", + "CMT_TOP_SE2A2_2", + "CMT_TOP_WW4C2_7", + "CMT_TOP_WW4C0_4", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH7_2", + "CMT_TOP_EE4BEG3_4", + "CMT_TOP_IMUX13_6", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "CMT_TOP_WW4A2_1", + "CMT_TOP_IMUX1_1", + "CMT_TOP_LH10_3", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_WW4C3_2", + "CMT_TOP_LH3_8", + "CMT_PHASERREF_DOWN_PHASEROUT_B", + "CMT_TOP_IMUX38_5", + "CMT_TOP_IMUX8_8", + "CMT_TOP_EE4C3_3", + "CMT_TOP_SW4A0_0", + "CMT_TOP_IMUX47_7", + "CMT_TOP_SW2A1_8", + "CMT_TOP_FAN4_6", + "CMT_TOP_EE2A1_1", + "CMT_TOP_IMUX46_0", + "CMT_TOP_IMUX3_0", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_EE4C2_0", + "CMT_TOP_IMUX16_1", + "CMT_TOP_SW4END2_5", + "CMT_TOP_FAN6_3", + "CMT_TOP_FAN7_8", + "CMT_TOP_IMUX16_0", + "CMT_TOP_EE2A1_0", + "CMT_TOP_EE4B0_0", + "CMT_TOP_NW4END0_4", + "CMT_TOP_IMUX12_7", + "CMT_PHASER_IN_DB_ENCALIB1", + "CMT_PHASER_IN_CA_COUNTERLOADEN", + "CMT_TOP_IMUX47_5", + "CMT_TOP_WR1END1_3", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_IMUX34_5", + "CMT_TOP_IMUX31_5", + "CMT_PHASER_OUT_CA_DQSBUS1", + "CMT_TOP_IMUX0_7", + "CMT_TOP_IMUX2_1", + "CMT_TOP_IMUX31_2", + "CMT_TOP_ER1BEG3_8" + ], + "pips": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_DQS_TO_PHASER_A->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_DQS_TO_PHASER_A", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT2->>MMCM_CLK_FREQBB_REBUFOUT2": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_5->CMT_PHASER_OUT_DB_COARSEENABLE": { + "src_wire": "CMT_TOP_IMUX14_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKB0->CMT_PHASER_IN_DB_RANKSELPHY0": { + "src_wire": "CMT_PHASER_BOT_IRANKB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX29_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX30_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX19_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_2": { + "src_wire": "CMT_PHASER_IN_CA_DQSFOUND", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_A->CMT_PHASER_OUT_CA_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B16_6": { + "src_wire": "CMT_PHASER_IN_DB_DQSFOUND", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX21_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_7->CMT_PHASER_IN_DB_RSTDQSFIND": { + "src_wire": "CMT_TOP_IMUX0_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_DQS_TO_PHASER_B->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_DQS_TO_PHASER_B", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_5->CMT_PHASER_OUT_DB_RST": { + "src_wire": "CMT_TOP_IMUX47_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_5->CMT_PHASER_OUT_DB_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX29_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX25_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { + "src_wire": "CMT_TOP_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX46_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { + "src_wire": "CMT_TOP_IMUX46_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_3": { + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX23_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { + "src_wire": "CMT_TOP_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX45_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B2_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKB1->CMT_PHASER_IN_DB_RANKSELPHY1": { + "src_wire": "CMT_PHASER_BOT_IRANKB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT0->>MMCM_CLK_FREQBB_REBUFOUT0": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX8_3->CMT_PHASER_IN_CA_RSTDQSFIND": { + "src_wire": "CMT_TOP_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B15_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX31_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX31_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { + "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B21_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B6_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX23_4->CMT_PHASER_OUT_DB_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX23_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_2->CMT_PHASER_IN_CA_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_A_RDCLK_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_IN_DB_SYNCIN": { + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_4": { + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { + "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_DB_RCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING0->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { + "src_wire": "CMT_PHASER_BOT_OBURSTPENDING0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B18_4": { + "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLKDIV->>CMT_PHASER_B_ICLKDIV_TOIOI": { + "src_wire": "CMT_PHASER_IN_B_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->CMT_PHASER_B_TOMMCM_OCLK": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX23_6->CMT_PHASER_IN_DB_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX23_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_A_OCLK": { + "src_wire": "CMT_PHASER_OUT_CA_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_IN_CA_SYNCIN": { + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_A_ICLK": { + "src_wire": "CMT_PHASER_IN_CA_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_ICLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX20_4->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { + "src_wire": "CMT_TOP_IMUX20_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_A->CMT_PHASER_IN_CA_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_FINEINC": { + "src_wire": "CMT_TOP_IMUX14_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B3_6": { + "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_4": { + "src_wire": "CMT_PHASER_B_OCLK90_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX43_4->CMT_PHASER_IN_CA_RANKSEL1": { + "src_wire": "CMT_TOP_IMUX43_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { + "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { + "src_wire": "CMT_TOP_IMUX14_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_6": { + "src_wire": "CMT_PHASER_IN_DB_ISERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_CLK1_8->>CMT_BOT_HCLKMUX_CLKINT_1": { + "src_wire": "CMT_TOP_CLK1_8", + "is_pseudo": "0", + "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B16_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING0->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { + "src_wire": "CMT_PHASER_BOT_IBURSTPENDING0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX14_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX11_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX11_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX45_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_B_OCLK": { + "src_wire": "CMT_PHASER_OUT_DB_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX44_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_8": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->CMT_PHASER_B_TOMMCM_OCLKDIV": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_OCLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_B->CMT_PHASER_IN_DB_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_EDGEADV": { + "src_wire": "CMT_TOP_IMUX34_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX13_5->CMT_PHASER_OUT_DB_FINEINC": { + "src_wire": "CMT_TOP_IMUX13_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX27_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX27_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { + "src_wire": "CMT_TOP_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B10_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_4": { + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B14_0": { + "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_6->CMT_PHASER_IN_DB_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_3": { + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_B->CMT_PHASER_OUT_DB_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX25_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { + "src_wire": "CMT_TOP_IMUX25_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_4": { + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_RDENABLE->CMT_PHASER_OUT_B_RDEN_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_DB_RDENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_RDEN_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX0_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->CMT_PHASER_B_TOMMCM_ICLK": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_ICLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->CMT_PHASER_B_TOMMCM_ICLKDIV": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_ICLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX13_6->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX13_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS1->CMT_PHASERA_DTSBUS1": { + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DTSBUS1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_6->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX29_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKA0->CMT_PHASER_IN_CA_RANKSELPHY0": { + "src_wire": "CMT_PHASER_BOT_IRANKA0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS1->CMT_PHASERA_DQSBUS1": { + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DQSBUS1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_5": { + "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_1->CMT_PHASER_OUT_CA_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { + "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B14_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { + "src_wire": "CMT_TOP_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX39_4->CMT_PHASER_OUT_DB_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX39_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS0->CMT_PHASERA_DQSBUS0": { + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DQSBUS0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK->>CMT_PHASER_B_OCLK_TOIOI": { + "src_wire": "CMT_PHASER_OUT_B_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT1->>MMCM_CLK_FREQBB_REBUFOUT1": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { + "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OCLKDIV->CMT_PHASER_OUT_B_RDCLK_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX28_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_OUT_CA_SYNCIN": { + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX14_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_6->CMT_PHASER_IN_DB_FINEINC": { + "src_wire": "CMT_TOP_IMUX47_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_B_WREN_TOFIFO": { + "src_wire": "CMT_PHASER_IN_DB_WRENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_WREN_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B1_3": { + "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX27_4->CMT_PHASER_IN_CA_RANKSEL0": { + "src_wire": "CMT_TOP_IMUX27_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_8": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING1->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { + "src_wire": "CMT_PHASER_BOT_OBURSTPENDING1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B3_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_5->CMT_PHASER_OUT_DB_COARSEINC": { + "src_wire": "CMT_TOP_IMUX45_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { + "src_wire": "CMT_TOP_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS0->CMT_PHASERA_CTSBUS0": { + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_CTSBUS0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B16_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO->CMT_PHASER_IN_B_ICLKDIV": { + "src_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_ICLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_7->CMT_PHASER_IN_DB_RST": { + "src_wire": "CMT_TOP_IMUX47_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_OUT_DB_SYNCIN": { + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO->CMT_PHASER_OUT_B_OCLKDIV": { + "src_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_OCLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { + "src_wire": "CMT_TOP_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90->>CMT_PHASER_B_OCLK90_TOIOI": { + "src_wire": "CMT_PHASER_OUT_B_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_OCLK90_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { + "src_wire": "CMT_TOP_IMUX41_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_B_WRCLK_TOFIFO": { + "src_wire": "CMT_PHASER_IN_DB_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B6_3": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX44_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX44_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B15_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLK->>CMT_PHASER_B_ICLK_TOIOI": { + "src_wire": "CMT_PHASER_IN_B_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX12_4->CMT_PHASER_IN_CA_RST": { + "src_wire": "CMT_TOP_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B23_1": { + "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX44_6->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX44_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B16_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_4": { + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { + "src_wire": "CMT_TOP_IMUX15_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_2": { + "src_wire": "CMT_PHASER_IN_CA_ISERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT3->>MMCM_CLK_FREQBB_REBUFOUT3": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX19_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX19_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX31_7->CMT_PHASER_IN_DB_RANKSEL1": { + "src_wire": "CMT_TOP_IMUX31_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV->>CMT_PHASER_B_OCLKDIV_TOIOI": { + "src_wire": "CMT_PHASER_OUT_B_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_A_RCLK0": { + "src_wire": "CMT_PHASER_IN_CA_RCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_RCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX12_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX12_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_A_RDEN_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_CA_RDENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_RDEN_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_A_OCLK1X_90": { + "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_OCLK1X_90", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS0->CMT_PHASERA_DTSBUS0": { + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DTSBUS0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { + "src_wire": "CMT_TOP_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_B_OCLK1X_90": { + "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_OCLK1X_90", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS1->CMT_PHASERA_CTSBUS1": { + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_CTSBUS1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_0": { + "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_5->CMT_PHASER_OUT_DB_EDGEADV": { + "src_wire": "CMT_TOP_IMUX30_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_B_RCLK1": { + "src_wire": "CMT_PHASER_IN_DB_RCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_RCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { + "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_CA_RCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_B_ICLK": { + "src_wire": "CMT_PHASER_IN_DB_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_ICLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ICLKDIV->CMT_PHASER_IN_A_WRCLK_TOFIFO": { + "src_wire": "CMT_PHASER_IN_CA_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX43_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX43_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX32_2->CMT_PHASER_OUT_CA_FINEINC": { + "src_wire": "CMT_TOP_IMUX32_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO->CMT_PHASER_OUT_A_OCLKDIV": { + "src_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_OCLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX15_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { + "src_wire": "CMT_TOP_IMUX15_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO->CMT_PHASER_IN_A_ICLKDIV": { + "src_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_ICLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING1->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { + "src_wire": "CMT_PHASER_BOT_IBURSTPENDING1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B16_3": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_A_WREN_TOFIFO": { + "src_wire": "CMT_PHASER_IN_CA_WRENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_WREN_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": { + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX30_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_8->>CMT_BOT_HCLKMUX_CLKINT_0": { + "src_wire": "CMT_TOP_CLK0_8", + "is_pseudo": "0", + "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKA1->CMT_PHASER_IN_CA_RANKSELPHY1": { + "src_wire": "CMT_PHASER_BOT_IRANKA1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CMT_TOP_R_UPPER_B.json b/kintex7/tile_type_CMT_TOP_R_UPPER_B.json new file mode 100644 index 0000000..26a6e6a --- /dev/null +++ b/kintex7/tile_type_CMT_TOP_R_UPPER_B.json @@ -0,0 +1,6524 @@ +{ + "tile_type": "CMT_TOP_R_UPPER_B", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "PHASER_REF", + "type": "PHASER_REF", + "site_pins": { + "TESTIN1": "CMT_PHASER_REF_TESTIN1", + "TESTOUT3": "CMT_PHASER_REF_TESTOUT3", + "TESTOUT7": "CMT_PHASER_REF_TESTOUT7", + "TESTOUT5": "CMT_PHASER_REF_TESTOUT5", + "TESTIN4": "CMT_PHASER_REF_TESTIN4", + "TESTIN7": "CMT_PHASER_REF_TESTIN7", + "RST": "CMT_PHASER_REF_RST", + "TESTIN2": "CMT_PHASER_REF_TESTIN2", + "TMUXOUT": "CMT_PHASER_REF_TMUXOUT", + "TESTIN6": "CMT_PHASER_REF_TESTIN6", + "TESTOUT4": "CMT_PHASER_REF_TESTOUT4", + "TESTOUT0": "CMT_PHASER_REF_TESTOUT0", + "TESTOUT1": "CMT_PHASER_REF_TESTOUT1", + "LOCKED": "CMT_PHASER_REF_LOCKED", + "PWRDWN": "CMT_PHASER_REF_PWRDWN", + "CLKIN": "CMT_PHASER_REF_CLKIN", + "TESTIN0": "CMT_PHASER_REF_TESTIN0", + "TESTOUT6": "CMT_PHASER_REF_TESTOUT6", + "TESTIN3": "CMT_PHASER_REF_TESTIN3", + "TESTOUT2": "CMT_PHASER_REF_TESTOUT2", + "TESTIN5": "CMT_PHASER_REF_TESTIN5", + "CLKOUT": "CMT_PHASER_REF_CLKOUT" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "PHY_CONTROL", + "type": "PHY_CONTROL", + "site_pins": { + "PHYCTLWD20": "CMT_PHY_CONTROL_PHYCTLWD20", + "PHYCTLWD11": "CMT_PHY_CONTROL_PHYCTLWD11", + "PHYCTLWRENABLE": "CMT_PHY_CONTROL_PHYCTLWRENABLE", + "OUTBURSTPENDING0": "CMT_PHY_CONTROL_OUTBURSTPENDING0", + "PHYCTLWD8": "CMT_PHY_CONTROL_PHYCTLWD8", + "TESTOUTPUT1": "CMT_PHY_CONTROL_TESTOUTPUT1", + "PHYCTLWD22": "CMT_PHY_CONTROL_PHYCTLWD22", + "TESTINPUT13": "CMT_PHY_CONTROL_TESTINPUT13", + "PHYCTLEMPTY": "CMT_PHY_CONTROL_PHYCTLEMPTY", + "TESTSELECT2": "CMT_PHY_CONTROL_TESTSELECT2", + "PHYCTLMSTREMPTY": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", + "PHYCTLWD13": "CMT_PHY_CONTROL_PHYCTLWD13", + "TESTINPUT7": "CMT_PHY_CONTROL_TESTINPUT7", + "AUXOUTPUT2": "CMT_PHY_CONTROL_AUXOUTPUT2", + "PHYCTLWD0": "CMT_PHY_CONTROL_PHYCTLWD0", + "TESTINPUT15": "CMT_PHY_CONTROL_TESTINPUT15", + "TESTINPUT8": "CMT_PHY_CONTROL_TESTINPUT8", + "PHYCTLWD4": "CMT_PHY_CONTROL_PHYCTLWD4", + "PLLLOCK": "CMT_PHY_CONTROL_PLLLOCK", + "PHYCTLALMOSTFULL": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", + "PHYCTLREADY": "CMT_PHY_CONTROL_PHYCTLREADY", + "TESTINPUT3": "CMT_PHY_CONTROL_TESTINPUT3", + "PHYCTLWD29": "CMT_PHY_CONTROL_PHYCTLWD29", + "PHYCTLWD21": "CMT_PHY_CONTROL_PHYCTLWD21", + "INRANKA1": "CMT_PHY_CONTROL_INRANKA1", + "TESTOUTPUT8": "CMT_PHY_CONTROL_TESTOUTPUT8", + "TESTOUTPUT11": "CMT_PHY_CONTROL_TESTOUTPUT11", + "TESTOUTPUT14": "CMT_PHY_CONTROL_TESTOUTPUT14", + "TESTSELECT0": "CMT_PHY_CONTROL_TESTSELECT0", + "PCENABLECALIB1": "CMT_PHY_CONTROL_PCENABLECALIB1", + "PHYCTLWD5": "CMT_PHY_CONTROL_PHYCTLWD5", + "TESTOUTPUT3": "CMT_PHY_CONTROL_TESTOUTPUT3", + "PHYCTLWD17": "CMT_PHY_CONTROL_PHYCTLWD17", + "TESTOUTPUT5": "CMT_PHY_CONTROL_TESTOUTPUT5", + "INBURSTPENDING2": "CMT_PHY_CONTROL_INBURSTPENDING2", + "TESTINPUT12": "CMT_PHY_CONTROL_TESTINPUT12", + "WRITECALIBENABLE": "CMT_PHY_CONTROL_WRITECALIBENABLE", + "INRANKD1": "CMT_PHY_CONTROL_INRANKD1", + "TESTOUTPUT6": "CMT_PHY_CONTROL_TESTOUTPUT6", + "PHYCTLWD15": "CMT_PHY_CONTROL_PHYCTLWD15", + "PHYCTLWD26": "CMT_PHY_CONTROL_PHYCTLWD26", + "MEMREFCLK": "CMT_PHY_CONTROL_MEMREFCLK", + "PHYCTLWD7": "CMT_PHY_CONTROL_PHYCTLWD7", + "TESTINPUT0": "CMT_PHY_CONTROL_TESTINPUT0", + "TESTINPUT11": "CMT_PHY_CONTROL_TESTINPUT11", + "PHYCTLWD28": "CMT_PHY_CONTROL_PHYCTLWD28", + "INBURSTPENDING1": "CMT_PHY_CONTROL_INBURSTPENDING1", + "REFDLLLOCK": "CMT_PHY_CONTROL_REFDLLLOCK", + "PHYCTLWD19": "CMT_PHY_CONTROL_PHYCTLWD19", + "TESTOUTPUT4": "CMT_PHY_CONTROL_TESTOUTPUT4", + "AUXOUTPUT1": "CMT_PHY_CONTROL_AUXOUTPUT1", + "TESTOUTPUT13": "CMT_PHY_CONTROL_TESTOUTPUT13", + "PHYCTLWD6": "CMT_PHY_CONTROL_PHYCTLWD6", + "PCENABLECALIB0": "CMT_PHY_CONTROL_PCENABLECALIB0", + "TESTINPUT2": "CMT_PHY_CONTROL_TESTINPUT2", + "TESTINPUT6": "CMT_PHY_CONTROL_TESTINPUT6", + "PHYCTLWD9": "CMT_PHY_CONTROL_PHYCTLWD9", + "PHYCTLWD23": "CMT_PHY_CONTROL_PHYCTLWD23", + "TESTOUTPUT12": "CMT_PHY_CONTROL_TESTOUTPUT12", + "TESTOUTPUT10": "CMT_PHY_CONTROL_TESTOUTPUT10", + "TESTINPUT4": "CMT_PHY_CONTROL_TESTINPUT4", + "TESTINPUT10": "CMT_PHY_CONTROL_TESTINPUT10", + "TESTOUTPUT2": "CMT_PHY_CONTROL_TESTOUTPUT2", + "RESET": "CMT_PHY_CONTROL_RESET", + "TESTINPUT9": "CMT_PHY_CONTROL_TESTINPUT9", + "TESTINPUT14": "CMT_PHY_CONTROL_TESTINPUT14", + "AUXOUTPUT0": "CMT_PHY_CONTROL_AUXOUTPUT0", + "INRANKB0": "CMT_PHY_CONTROL_INRANKB0", + "PHYCTLWD30": "CMT_PHY_CONTROL_PHYCTLWD30", + "SYNCIN": "CMT_PHY_CONTROL_SYNCIN", + "PHYCTLFULL": "CMT_PHY_CONTROL_PHYCTLFULL", + "TESTOUTPUT0": "CMT_PHY_CONTROL_TESTOUTPUT0", + "TESTINPUT1": "CMT_PHY_CONTROL_TESTINPUT1", + "PHYCTLWD14": "CMT_PHY_CONTROL_PHYCTLWD14", + "INBURSTPENDING3": "CMT_PHY_CONTROL_INBURSTPENDING3", + "PHYCLK": "CMT_PHY_CONTROL_PHYCLK", + "TESTOUTPUT9": "CMT_PHY_CONTROL_TESTOUTPUT9", + "PHYCTLWD31": "CMT_PHY_CONTROL_PHYCTLWD31", + "PHYCTLWD25": "CMT_PHY_CONTROL_PHYCTLWD25", + "PHYCTLWD24": "CMT_PHY_CONTROL_PHYCTLWD24", + "SCANENABLEN": "CMT_PHY_CONTROL_SCANENABLEN", + "PHYCTLWD2": "CMT_PHY_CONTROL_PHYCTLWD2", + "TESTINPUT5": "CMT_PHY_CONTROL_TESTINPUT5", + "OUTBURSTPENDING2": "CMT_PHY_CONTROL_OUTBURSTPENDING2", + "PHYCTLWD16": "CMT_PHY_CONTROL_PHYCTLWD16", + "TESTOUTPUT15": "CMT_PHY_CONTROL_TESTOUTPUT15", + "INRANKC0": "CMT_PHY_CONTROL_INRANKC0", + "INRANKD0": "CMT_PHY_CONTROL_INRANKD0", + "READCALIBENABLE": "CMT_PHY_CONTROL_READCALIBENABLE", + "INRANKA0": "CMT_PHY_CONTROL_INRANKA0", + "PHYCTLWD1": "CMT_PHY_CONTROL_PHYCTLWD1", + "OUTBURSTPENDING3": "CMT_PHY_CONTROL_OUTBURSTPENDING3", + "TESTOUTPUT7": "CMT_PHY_CONTROL_TESTOUTPUT7", + "PHYCTLWD3": "CMT_PHY_CONTROL_PHYCTLWD3", + "PHYCTLWD27": "CMT_PHY_CONTROL_PHYCTLWD27", + "PHYCTLWD12": "CMT_PHY_CONTROL_PHYCTLWD12", + "PHYCTLWD10": "CMT_PHY_CONTROL_PHYCTLWD10", + "INRANKC1": "CMT_PHY_CONTROL_INRANKC1", + "OUTBURSTPENDING1": "CMT_PHY_CONTROL_OUTBURSTPENDING1", + "INRANKB1": "CMT_PHY_CONTROL_INRANKB1", + "PHYCTLWD18": "CMT_PHY_CONTROL_PHYCTLWD18", + "AUXOUTPUT3": "CMT_PHY_CONTROL_AUXOUTPUT3", + "TESTSELECT1": "CMT_PHY_CONTROL_TESTSELECT1", + "INBURSTPENDING0": "CMT_PHY_CONTROL_INBURSTPENDING0" + }, + "x_coord": 0 + }, + { + "y_coord": 11, + "name": "X0Y11", + "prefix": "PHASER_OUT_PHY", + "type": "PHASER_OUT_PHY", + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", + "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", + "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", + "RST": "CMT_PHASER_OUT_CA_RST", + "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", + "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", + "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", + "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", + "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", + "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", + "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", + "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", + "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", + "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", + "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", + "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", + "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", + "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", + "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", + "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", + "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", + "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", + "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", + "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", + "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", + "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", + "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", + "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", + "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", + "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", + "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", + "OCLK": "CMT_PHASER_OUT_CA_OCLK", + "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", + "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", + "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3", + "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", + "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", + "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", + "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3" + }, + "x_coord": 0 + }, + { + "y_coord": 11, + "name": "X0Y11", + "prefix": "PHASER_IN_PHY", + "type": "PHASER_IN_PHY", + "site_pins": { + "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", + "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE", + "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", + "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", + "RST": "CMT_PHASER_IN_CA_RST", + "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", + "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", + "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", + "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_IN_CA_FINEINC", + "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", + "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", + "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", + "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", + "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", + "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", + "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", + "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", + "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", + "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", + "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", + "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", + "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", + "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", + "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", + "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", + "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", + "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", + "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", + "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", + "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "STG1READ": "CMT_PHASER_IN_CA_STG1READ", + "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", + "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", + "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", + "SCANENB": "CMT_PHASER_IN_CA_SCANENB", + "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", + "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", + "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", + "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", + "SCANIN": "CMT_PHASER_IN_CA_SCANIN", + "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", + "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", + "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", + "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", + "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", + "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", + "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST", + "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", + "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", + "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", + "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", + "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", + "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", + "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", + "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", + "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", + "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", + "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", + "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", + "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1", + "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", + "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", + "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", + "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", + "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", + "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", + "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", + "ICLK": "CMT_PHASER_IN_CA_ICLK", + "RCLK": "CMT_PHASER_IN_CA_RCLK" + }, + "x_coord": 0 + }, + { + "y_coord": 12, + "name": "X0Y12", + "prefix": "PHASER_OUT_PHY", + "type": "PHASER_OUT_PHY", + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_DB_COARSEINC", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", + "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", + "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", + "RST": "CMT_PHASER_OUT_DB_RST", + "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", + "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", + "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", + "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", + "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", + "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", + "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", + "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", + "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE", + "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", + "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", + "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", + "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", + "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "COARSEENABLE": "CMT_PHASER_OUT_DB_COARSEENABLE", + "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", + "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", + "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", + "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", + "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", + "COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", + "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", + "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", + "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", + "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", + "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", + "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", + "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", + "OCLK": "CMT_PHASER_OUT_DB_OCLK", + "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", + "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", + "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3", + "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING", + "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", + "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", + "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3" + }, + "x_coord": 0 + }, + { + "y_coord": 12, + "name": "X0Y12", + "prefix": "PHASER_IN_PHY", + "type": "PHASER_IN_PHY", + "site_pins": { + "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", + "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE", + "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", + "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", + "RST": "CMT_PHASER_IN_DB_RST", + "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", + "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", + "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", + "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", + "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "FINEINC": "CMT_PHASER_IN_DB_FINEINC", + "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", + "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", + "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", + "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", + "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", + "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", + "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", + "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", + "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", + "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", + "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", + "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", + "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", + "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", + "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", + "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", + "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", + "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", + "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", + "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", + "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "STG1READ": "CMT_PHASER_IN_DB_STG1READ", + "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", + "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", + "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", + "SCANENB": "CMT_PHASER_IN_DB_SCANENB", + "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", + "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", + "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", + "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", + "SCANIN": "CMT_PHASER_IN_DB_SCANIN", + "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", + "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", + "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", + "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", + "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", + "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", + "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", + "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST", + "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", + "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", + "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", + "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", + "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", + "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", + "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", + "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", + "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", + "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", + "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", + "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", + "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", + "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", + "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", + "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1", + "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", + "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", + "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", + "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", + "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", + "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", + "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", + "ICLK": "CMT_PHASER_IN_DB_ICLK", + "RCLK": "CMT_PHASER_IN_DB_RCLK" + }, + "x_coord": 0 + } + ], + "wires": [ + "CMT_TOP_WR1END2_7", + "CMT_TOP_WW4C3_6", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_IMUX18_1", + "CMT_TOP_WL1END3_8", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX8_5", + "CMT_TOP_WW2END3_7", + "CMT_PHASER_IN_DB_EDGEADV", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_IMUX15_8", + "CMT_TOP_EE4B0_9", + "CMT_TOP_LH5_7", + "CMT_TOP_LOGIC_OUTS_L_B12_11", + "CMT_PHASER_IN_CA_TESTOUT0", + "CMT_TOP_SE4C2_0", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_FAN2_3", + "CMT_TOP_IMUX40_8", + "CMT_TOP_EE4C2_7", + "CMT_TOP_SE4BEG0_10", + "CMT_PHY_CONTROL_OUTBURSTPENDING0", + "CMT_TOP_NW2A1_4", + "CMT_TOP_ER1BEG2_3", + "CMT_PHY_CONTROL_IRANKC1", + "CMT_TOP_EE2A1_6", + "CMT_TOP_EE4A2_4", + "CMT_TOP_BYP1_4", + "CMT_PHASER_OUT_C_OCLK1X_90", + "CMT_TOP_EE4C0_3", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_SE4C1_4", + "CMT_TOP_IMUX23_5", + "CMT_PHASER_UP_PHASERREF0", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_IMUX34_7", + "CMT_TOP_IMUX25_10", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN5_3", + "CMT_TOP_NE4C2_2", + "CMT_TOP_EE4A2_5", + "CMT_TOP_IMUX35_5", + "CMT_TOP_EE2A0_1", + "CMT_TOP_SE4BEG3_10", + "CMT_PHASER_IN_CA_ENCALIBPHY0", + "CMT_TOP_FAN3_2", + "CMT_TOP_BYP2_11", + "CMT_TOP_EE2A2_1", + "CMT_TOP_SW4END2_10", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE2A2_5", + "CMT_PHASER_IN_CA_FREQREFCLK", + "CMT_TOP_WW2END0_3", + "CMT_TOP_SW4END3_9", + "CMT_PHY_CONTROL_PHYCTLWD2", + "CMT_TOP_IMUX16_11", + "CMT_TOP_ER1BEG1_0", + "CMT_TOP_SE4C0_2", + "CMT_TOP_SE2A2_10", + "CMT_TOP_EE4B3_8", + "CMT_TOP_NW4A3_9", + "CMT_TOP_EE4A1_2", + "CMT_PHASER_OUT_DB_TESTIN2", + "CMT_TOP_IMUX31_4", + "CMT_TOP_EL1BEG3_5", + "CMT_PHY_CONTROL_WRITECALIBENABLE", + "CMT_PHASER_IN_CA_RCLK", + "CMT_TOP_SE4C3_11", + "CMT_PHASER_UP_PHASERREF1", + "CMT_TOP_NW4A3_4", + "CMT_TOP_WW4END1_2", + "CMT_PHASER_IN_DB_STG1REGR7", + "CMT_TOP_WW4B1_5", + "CMT_TOP_LOGIC_OUTS_L_B2_9", + "CMT_PHASER_OUT_CA_TESTIN0", + "CMT_TOP_IMUX12_5", + "CMT_PHASER_OUT_DB_COARSEINC", + "CMT_TOP_IMUX8_10", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_EE4A0_6", + "CMT_PHASER_OUT_CA_COARSEENABLE", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_NE4C3_9", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_SW2A0_11", + "CMT_TOP_WR1END0_2", + "CMT_TOP_NW4END1_8", + "CMT_TOP_SE2A0_8", + "CMT_TOP_LH11_2", + "CMT_TOP_EE4C3_2", + "CMT_TOP_IMUX2_7", + "CMT_TOP_LOGIC_OUTS_L_B7_11", + "CMT_TOP_EE2A1_7", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_ER1BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX16_6", + "CMT_TOP_LH6_2", + "CMT_PHASER_IN_DB_STG1REGL6", + "CMT_TOP_NE4BEG1_9", + "CMT_TOP_IMUX9_2", + "CMT_TOP_BYP5_1", + "CMT_PHASER_UP_BUFMRCE_CE0", + "CMT_TOP_WR1END1_7", + "CMT_TOP_WL1END1_1", + "CMT_TOP_EE2A3_11", + "CMT_PHASER_IN_DB_FINEINC", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_EE4A0_11", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX23_8", + "CMT_TOP_EE4C3_11", + "CMT_TOP_LOGIC_OUTS_L_B19_9", + "CMT_TOP_SW4END2_11", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_WW4B1_11", + "CMT_TOP_EL1BEG1_2", + "CMT_PHASER_OUT_CA_DQSBUS0", + "CMT_PHASER_IN_DB_RANKSEL0", + "CMT_TOP_WW4A2_11", + "CMT_PHASER_OUT_DB_DTSBUS0", + "CMT_TOP_NW4END3_0", + "CMT_TOP_ER1BEG1_8", + "CMT_PHASER_OUT_CA_TESTIN7", + "CMT_TOP_SE4BEG0_6", + "CMT_TOP_IMUX7_7", + "CMT_TOP_WL1END2_8", + "CMT_PHASER_OUT_CA_TESTIN14", + "CMT_TOP_NE4BEG1_8", + "CMT_PHASER_IN_DB_STG1REGL4", + "CMT_TOP_WW4C1_4", + "CMT_TOP_NE2A2_5", + "CMT_TOP_SE4C3_9", + "CMT_TOP_SW2A3_2", + "CMT_TOP_IMUX3_7", + "CMT_TOP_WW4A0_8", + "CMT_TOP_NW4END0_5", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_PHASER_IN_CA_STG1READ", + "CMT_PHY_CONTROL_TESTOUTPUT8", + "CMT_TOP_FAN5_1", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_SE4BEG2_10", + "CMT_TOP_IMUX9_9", + "CMT_PHY_CONTROL_PHYCTLWD30", + "CMT_TOP_IMUX31_9", + "CMT_TOP_FAN1_6", + "CMT_TOP_IMUX26_4", + "CMT_PHASER_UP_PHASERREF_BELOW0", + "CMT_TOP_IMUX3_2", + "CMT_TOP_LH9_11", + "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_LH4_2", + "CMT_TOP_EE4A1_8", + "CMT_PHASER_IN_DB_FINEENABLE", + "CMT_TOP_WW4END1_7", + "CMT_TOP_IMUX35_10", + "CMT_TOP_IMUX44_5", + "CMT_TOP_IMUX37_4", + "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "CMT_TOP_WW4C2_8", + "CMT_TOP_EE4A0_8", + "CMT_PHY_CONTROL_INBURSTPENDING3", + "CMT_TOP_WW4B3_1", + "CMT_TOP_EE4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_PHASER_IN_DB_TESTIN3", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "CMT_TOP_LOGIC_OUTS_L_B15_9", + "CMT_TOP_NE4BEG2_11", + "CMT_TOP_WW2END1_0", + "CMT_TOP_IMUX22_9", + "CMT_TOP_FAN3_11", + "CMT_TOP_IMUX13_3", + "CMT_TOP_WW4END1_4", + "CMT_TOP_IMUX14_11", + "CMT_TOP_EE4BEG0_9", + "CMT_PHASER_IN_CA_SCANENB", + "CMT_TOP_WR1END0_10", + "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "CMT_TOP_EE4C1_5", + "CMT_TOP_LH9_1", + "CMT_TOP_LH11_10", + "CMT_TOP_SE2A1_3", + "CMT_TOP_SE2A0_1", + "CMT_TOP_SE4C0_10", + "CMT_TOP_LH12_3", + "CMT_TOP_ER1BEG3_11", + "CMT_TOP_FAN7_4", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END2_5", + "CMT_TOP_WR1END2_9", + "CMT_TOP_FAN1_0", + "CMT_PHASER_REF_TESTOUT6", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_IMUX40_7", + "CMT_TOP_BYP7_8", + "CMT_PHASER_OUT_DB_CTSBUS0", + "CMT_TOP_NW4A3_0", + "CMT_TOP_WL1END2_4", + "CMT_TOP_IMUX0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_SW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_EE2A3_3", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW2A0_2", + "CMT_TOP_SW4END1_2", + "CMT_TOP_EE2A3_5", + "CMT_TOP_WR1END0_1", + "CMT_TOP_WW4C1_3", + "CMT_TOP_LH4_3", + "CMT_TOP_EE4B2_8", + "CMT_PHASER_OUT_CA_RDENABLE", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_IMUX5_2", + "CMT_TOP_EE2BEG1_6", + "CMT_PHASER_IN_CA_TESTIN13", + "CMT_TOP_EE4BEG3_3", + "CMT_R_TOP_UPPER_B_CLKPLL7", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NW4A0_6", + "CMT_TOP_EE2A1_10", + "CMT_TOP_EE4A3_5", + "CMT_TOP_LOGIC_OUTS_L_B8_10", + "CMT_TOP_IMUX14_0", + "CMT_TOP_LH7_5", + "CMT_PHY_CONTROL_MEMREFCLK", + "CMT_TOP_WW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_TOP_WW2END2_3", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WW2END3_8", + "CMT_TOP_NW4END1_0", + "CMT_PHASER_OUT_DB_SYNCIN", + "CMT_TOP_NE4C2_5", + "CMT_TOP_SE2A2_11", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "CMT_TOP_IMUX14_4", + "CMT_TOP_IMUX12_4", + "CMT_TOP_SW4END3_2", + "CMT_TOP_IMUX32_0", + "CMT_TOP_SE4BEG0_1", + "CMT_PHASER_REF_TESTIN5", + "CMT_TOP_IMUX44_6", + "CMT_PHY_CONTROL_PHYCTLWD29", + "CMT_TOP_IMUX40_9", + "CMT_TOP_SE2A3_3", + "CMT_TOP_ER1BEG0_11", + "CMT_TOP_FAN0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_NE2A3_10", + "CMT_PHASER_IN_CA_TESTIN2", + "CMT_TOP_WW4B3_2", + "CMT_TOP_LOGIC_OUTS_L_B3_10", + "CMT_TOP_FAN0_7", + "CMT_R_TOP_UPPER_B_CLKPLL6", + "CMT_TOP_WW4B0_3", + "CMT_TOP_LH11_8", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_PHASER_IN_CA_STG1REGR8", + "CMT_TOP_IMUX47_4", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_EE4A0_10", + "CMT_TOP_WW4C1_6", + "CMT_TOP_IMUX35_11", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_NW2A1_11", + "CMT_PHASER_OUT_D_RDENABLE_TOFIFO", + "CMT_TOP_IMUX46_9", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_SW4END3_7", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_PHASER_IN_D_ICLK", + "CMT_TOP_NW4END3_6", + "CMT_TOP_EE2BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_PHY_CONTROL_TESTINPUT15", + "CMT_PHASER_IN_DB_PHASEREFCLK", + "CMT_TOP_ER1BEG1_11", + "CMT_TOP_IMUX45_6", + "CMT_TOP_WW4END2_8", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_WW4END1_0", + "CMT_TOP_LH3_2", + "CMT_TOP_IMUX1_9", + "CMT_TOP_IMUX8_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_IMUX2_8", + "CMT_TOP_BYP0_3", + "CMT_TOP_OCLK_5", + "CMT_TOP_NE4C0_10", + "CMT_TOP_WW2A2_2", + "CMT_TOP_IMUX20_7", + "CMT_TOP_IMUX25_4", + "CMT_TOP_NW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_WW4C0_3", + "CMT_TOP_IMUX28_5", + "CMT_TOP_NE2A0_2", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_BYP1_1", + "CMT_TOP_SE2A3_6", + "CMT_TOP_SW4A1_11", + "CMT_TOP_IMUX2_2", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX21_0", + "CMT_PHASER_IN_CA_SCANCLK", + "CMT_TOP_WW4END2_9", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_SE2A0_2", + "CMT_PHASER_OUT_DB_TESTIN9", + "CMT_TOP_IMUX43_1", + "CMT_TOP_EE4BEG1_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_IMUX28_8", + "CMT_TOP_WW4C3_4", + "CMT_TOP_SW4END0_9", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_LH8_1", + "CMT_TOP_NE2A0_11", + "CMT_TOP_WW2A3_2", + "CMT_TOP_NW4A0_7", + "CMT_TOP_LH9_5", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_IMUX6_7", + "CMT_PHASER_OUT_DB_COARSEENABLE", + "CMT_TOP_IMUX45_10", + "CMT_TOP_WR1END3_4", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "CMT_TOP_EE2A0_6", + "CMT_TOP_EE2BEG0_9", + "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "CMT_TOP_EE2A2_6", + "CMT_TOP_BYP2_2", + "CMT_PHASER_OUT_DB_EDGEADV", + "CMT_TOP_IMUX21_6", + "CMT_TOP_LOGIC_OUTS_L_B0_11", + "CMT_TOP_SE4C3_1", + "CMT_TOP_SW2A2_3", + "CMT_TOP_IMUX19_7", + "CMT_TOP_IMUX0_4", + "CMT_TOP_ICLK_9", + "CMT_TOP_SW4END2_7", + "CMT_TOP_WW4B3_9", + "CMT_TOP_IMUX15_0", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_PHASER_REF_TESTOUT4", + "CMT_TOP_EL1BEG2_9", + "CMT_PHASER_IN_DB_COUNTERLOADEN", + "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_WW4END2_5", + "CMT_TOP_WW2A1_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_IMUX9_8", + "CMT_TOP_WW2A1_9", + "PLL_CLK_FREQBB_REBUFOUT0", + "CMT_PHASER_IN_DB_ICLK", + "CMT_TOP_SW4A0_4", + "CMT_TOP_BYP0_11", + "CMT_TOP_FAN1_8", + "CMT_TOP_IMUX34_4", + "CMT_TOP_IMUX12_9", + "CMT_TOP_SW4A1_10", + "CMT_TOP_NW4A0_11", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4B0_2", + "CMT_TOP_LH2_2", + "CMT_PHASER_OUT_CA_OCLKDIV", + "CMT_TOP_IMUX10_7", + "CMT_TOP_IMUX39_0", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_WW4END0_10", + "CMT_TOP_IMUX30_10", + "CMT_PHASER_OUT_CA_TESTIN13", + "CMT_TOP_NW2A0_9", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "CMT_TOP_SW4A3_5", + "CMT_TOP_IMUX14_1", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_WL1END0_10", + "CMT_TOP_IMUX26_1", + "CMT_TOP_CTRL0_9", + "CMT_TOP_WL1END0_1", + "CMT_TOP_LH11_6", + "CMT_TOP_NE4C3_8", + "CMT_TOP_WL1END0_7", + "CMT_TOP_LH12_4", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_NE4C3_4", + "CMT_TOP_ER1BEG0_7", + "CMT_TOP_WW2END2_4", + "CMT_TOP_SE4C2_6", + "CMT_TOP_SW4END1_8", + "CMT_PHY_CONTROL_TESTINPUT6", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_SW2A1_1", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_WW4END3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_9", + "CMT_TOP_WL1END2_6", + "CMT_TOP_IMUX43_6", + "CMT_PHASER_OUT_DB_TESTIN4", + "CMT_TOP_NW4A1_1", + "CMT_TOP_SE4C1_8", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_SE4BEG0_3", + "CMT_PHASER_IN_CA_TESTIN7", + "CMT_TOP_IMUX40_5", + "CMT_PHASER_IN_DB_STG1OVERFLOW", + "CMT_PHASER_IN_DB_DQSFOUND", + "CMT_TOP_EE4BEG3_2", + "CMT_TOP_BLOCK_OUTS_L_B1_10", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_IMUX34_1", + "CMT_TOP_WL1END2_0", + "CMT_TOP_EE4A1_3", + "CMT_TOP_OCLKDIV_10", + "CMT_TOP_LH7_0", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_IMUX8_11", + "CMT_TOP_WW2END0_2", + "CMT_TOP_IMUX0_3", + "CMT_TOP_EE4A0_1", + "CMT_TOP_WW4A1_4", + "CMT_TOP_IMUX23_3", + "CMT_TOP_IMUX20_0", + "CMT_TOP_WR1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_LH11_9", + "CMT_TOP_IMUX25_1", + "CMT_TOP_ER1BEG1_1", + "CMT_TOP_IMUX44_7", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_PHASER_IN_DB_TESTIN7", + "CMT_PHASER_IN_DB_STG1REGR0", + "CMT_TOP_WW4A3_10", + "CMT_TOP_WW2A0_4", + "CMT_TOP_SW2A0_10", + "CMT_TOP_WW4A3_3", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_LH1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_NW4A0_4", + "CMT_TOP_CLK1_5", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_NE2A0_10", + "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "CMT_TOP_IMUX18_5", + "CMT_TOP_IMUX24_8", + "CMT_R_TOP_UPPER_B_CLKPLL3", + "CMT_TOP_IMUX24_7", + "CMT_TOP_LH12_11", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "CMT_TOP_EE4B0_2", + "CMT_TOP_SW2A0_2", + "CMT_TOP_SW4A3_1", + "CMT_TOP_EE2A3_10", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_WL1END3_2", + "CMT_TOP_SE4BEG0_11", + "CMT_TOP_FAN4_5", + "CMT_TOP_EE4A1_10", + "CMT_TOP_NE2A1_2", + "CMT_TOP_SE4BEG1_7", + "CMT_TOP_NE2A1_10", + "CMT_TOP_WW2END2_11", + "CMT_TOP_IMUX36_3", + "CMT_TOP_IMUX10_11", + "CMT_TOP_IMUX14_9", + "CMT_TOP_ER1BEG2_11", + "CMT_TOP_IMUX21_7", + "CMT_TOP_EE4B3_11", + "CMT_TOP_IMUX25_7", + "CMT_TOP_SW4A2_5", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_WW4C0_9", + "CMT_PHASER_OUT_DB_TESTOUT3", + "CMT_TOP_NE4C2_3", + "CMT_TOP_WW4A1_8", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_BYP7_5", + "CMT_PHY_CONTROL_PHYCTLWD22", + "CMT_TOP_NE2A0_5", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_EE4A0_2", + "CMT_PHASER_IN_DB_COUNTERREADEN", + "CMT_TOP_SW4END3_8", + "CMT_TOP_IMUX20_6", + "CMT_TOP_LH9_3", + "CMT_TOP_EE4B3_0", + "CMT_TOP_EL1BEG1_9", + "CMT_TOP_SW2A2_10", + "CMT_TOP_WW4END3_0", + "CMT_PHY_CONTROL_PHYCTLWD7", + "CMT_TOP_WW2A0_1", + "CMT_TOP_SW4A0_9", + "CMT_TOP_IMUX45_7", + "CMT_TOP_IMUX19_2", + "CMT_TOP_IMUX42_5", + "CMT_TOP_IMUX18_11", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_BLOCK_OUTS_L_B0_9", + "CMT_TOP_WL1END2_7", + "CMT_TOP_SW4END3_6", + "CMT_TOP_SW4A0_3", + "PLL_CLK_FREQBB_REBUFOUT2", + "CMT_TOP_BYP1_10", + "CMT_TOP_IMUX27_7", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_PHY_CONTROL_TESTOUTPUT4", + "CMT_PHY_CONTROL_PHYCTLWD14", + "CMT_TOP_SW4A2_10", + "CMT_TOP_LOGIC_OUTS_L_B6_10", + "CMT_TOP_BYP5_6", + "CMT_TOP_IMUX27_8", + "CMT_TOP_IMUX34_3", + "CMT_TOP_FAN0_0", + "CMT_PHASER_IN_DB_STG1INCDEC", + "CMT_TOP_IMUX23_11", + "CMT_PHASER_IN_DB_ICLKDIV", + "CMT_TOP_WR1END1_1", + "CMT_TOP_WW4END3_6", + "CMT_TOP_WW4B3_7", + "CMT_TOP_SW4A0_7", + "CMT_TOP_NE4BEG1_11", + "CMT_TOP_SW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_LOGIC_OUTS_L_B15_10", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_IMUX6_2", + "CMT_PHASER_OUT_CA_SCANCLK", + "CMT_TOP_WW4A1_6", + "CMT_PHY_CONTROL_TESTOUTPUT12", + "CMT_TOP_WW4C2_5", + "CMT_TOP_IMUX40_0", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_EE2A2_8", + "CMT_TOP_NE2A3_7", + "CMT_PHASER_OUT_DB_TESTIN3", + "CMT_TOP_ER1BEG1_2", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_LOGIC_OUTS_L_B14_11", + "CMT_TOP_IMUX3_5", + "CMT_TOP_LH4_5", + "CMT_TOP_BYP7_4", + "CMT_PHASER_IN_CA_TESTIN9", + "CMT_TOP_CLK1_0", + "CMT_TOP_IMUX26_11", + "CMT_TOP_IMUX1_5", + "CMT_TOP_LH9_4", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_SE4C2_1", + "CMT_R_TOP_UPPER_B_CLKPLL1", + "CMT_TOP_EE2A3_1", + "CMT_TOP_SW2A2_9", + "CMT_TOP_EL1BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_11", + "CMT_TOP_IMUX28_0", + "CMT_PHASER_IN_DB_ISERDESRST", + "CMT_TOP_BYP3_11", + "CMT_TOP_IMUX18_2", + "CMT_TOP_WW2END0_1", + "CMT_TOP_LOGIC_OUTS_L_B7_9", + "CMT_PHASER_IN_CA_FINEENABLE", + "CMT_PHASER_OUT_DB_RST", + "CMT_TOP_BYP3_0", + "CMT_TOP_BYP4_3", + "CMT_TOP_CLK1_10", + "CMT_TOP_EE4BEG0_11", + "CMT_TOP_NE2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_BLOCK_OUTS_L_B0_11", + "CMT_TOP_EE2A3_8", + "CMT_TOP_EE4A2_8", + "CMT_TOP_OCLKDIV_4", + "CMT_PHASER_IN_DB_TESTIN10", + "CMT_TOP_WW4C0_6", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_CTRL0_4", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SW4END0_6", + "CMT_TOP_NE4BEG1_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "CMT_PHASER_OUT_CA_TESTIN10", + "CMT_PHASER_IN_DB_STG1REGL2", + "CMT_TOP_NW4A3_7", + "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "CMT_TOP_WW4B1_10", + "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "CMT_TOP_SE2A3_5", + "CMT_TOP_LH5_10", + "CMT_TOP_WW4END0_11", + "CMT_TOP_BYP7_7", + "CMT_TOP_IMUX29_5", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_IMUX25_5", + "CMT_TOP_WW4A3_4", + "CMT_TOP_FAN5_9", + "CMT_TOP_IMUX46_8", + "CMT_TOP_IMUX31_11", + "CMT_PHASERREF_PHASEROUT_C", + "CMT_TOP_BYP4_0", + "CMT_PHY_CONTROL_INRANKD1", + "CMT_TOP_IMUX18_4", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_TOP_LOGIC_OUTS_L_B16_9", + "CMT_TOP_WW2A2_3", + "CMT_TOP_IMUX28_3", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WW2A1_11", + "CMT_TOP_LH7_3", + "CMT_TOP_LH6_1", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_NE2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH6_0", + "CMT_TOP_WW4C0_7", + "CMT_TOP_SE4BEG2_2", + "CMT_TOP_WW4END1_10", + "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "CMT_PHASER_IN_CA_STG1REGR4", + "CMT_TOP_LH3_5", + "CMT_TOP_BYP0_10", + "CMT_TOP_NE4C0_4", + "CMT_TOP_SW2A1_7", + "CMT_PHASER_IN_DB_SCANENB", + "CMT_TOP_NE4C0_2", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "CMT_PHASER_OUT_C_OCLK", + "CMT_TOP_SE4C0_7", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_LOGIC_OUTS_L_B11_10", + "CMT_TOP_SW4A1_8", + "CMT_PHY_CONTROL_TESTOUTPUT2", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_LH11_11", + "CMT_TOP_WR1END3_3", + "CMT_TOP_MONITOR_P_1", + "CMT_TOP_LH8_8", + "CMT_TOP_SW4A3_6", + "CMT_TOP_SW4END1_11", + "CMT_TOP_IMUX31_8", + "CMT_TOP_EE2A3_0", + "CMT_TOP_IMUX21_11", + "CMT_TOP_IMUX13_2", + "CMT_TOP_IMUX39_4", + "CMT_PHASER_IN_DB_SCANMODEB", + "CMT_TOP_NW4END2_11", + "CMT_TOP_MONITOR_P_3", + "CMT_TOP_EE4B1_7", + "CMT_TOP_WW4A0_7", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_PHY_CONTROL_IRANKD0", + "CMT_PHY_CONTROL_INBURSTPENDING1", + "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "CMT_TOP_WW4B0_11", + "CMT_TOP_SE2A1_2", + "CMT_PHASER_OUT_CA_FINEENABLE", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_BYP5_11", + "CMT_TOP_NE2A0_4", + "CMT_TOP_LH9_0", + "CMT_TOP_IMUX22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_10", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_IMUX25_6", + "CMT_TOP_NE2A1_4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "CMT_TOP_EE4BEG3_0", + "CMT_TOP_WW2END1_7", + "CMT_TOP_EE4B0_7", + "CMT_TOP_WW4B2_10", + "CMT_TOP_BYP1_0", + "CMT_TOP_IMUX22_4", + "CMT_TOP_SE4C1_0", + "CMT_PHASER_OUT_CA_FREQREFCLK", + "CMT_TOP_FAN7_3", + "CMT_TOP_WW4A0_6", + "CMT_PHASER_IN_DB_SYSCLK", + "CMT_TOP_WW2END2_1", + "CMT_TOP_IMUX45_5", + "CMT_TOP_BYP6_4", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_TOP_BYP3_5", + "CMT_TOP_EE2A0_3", + "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_EE4C2_2", + "CMT_TOP_FAN2_10", + "CMT_TOP_CTRL1_5", + "CMT_TOP_CTRL0_5", + "CMT_TOP_WW2END0_6", + "CMT_TOP_IMUX1_3", + "CMT_TOP_WW2END0_7", + "CMT_TOP_NW4END0_11", + "CMT_PHASER_OUT_DB_TESTOUT2", + "CMT_TOP_WL1END2_3", + "CMT_TOP_LOGIC_OUTS_L_B20_11", + "CMT_TOP_IMUX36_11", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_IMUX10_3", + "CMT_TOP_IMUX37_10", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_WR1END3_8", + "CMT_TOP_IMUX47_1", + "CMT_TOP_IMUX10_6", + "CMT_TOP_IMUX44_10", + "CMT_TOP_BYP6_11", + "CMT_TOP_NE4C1_0", + "CMT_PHASER_IN_DB_STG1READ", + "CMT_TOP_WW4A3_1", + "CMT_TOP_BYP6_6", + "CMT_TOP_BYP4_10", + "CMT_PHY_CONTROL_TESTINPUT13", + "CMT_TOP_LOGIC_OUTS_L_B23_11", + "CMT_TOP_NE4C0_3", + "CMT_TOP_SW4A3_9", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_OCLKDIV_8", + "CMT_PHY_CONTROL_IRANKD1", + "CMT_TOP_LH2_1", + "CMT_TOP_IMUX42_1", + "CMT_TOP_SW4A1_6", + "CMT_PHASER_IN_DB_STG1REGL8", + "CMT_TOP_LH12_0", + "CMT_TOP_IMUX7_11", + "CMT_TOP_NW4A1_9", + "CMT_TOP_BYP1_8", + "CMT_TOP_WW4C2_1", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_IMUX42_0", + "CMT_PHASERREF_PHASERIN_C", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_FAN7_1", + "CMT_PHASER_IN_DB_TESTOUT2", + "CMT_TOP_SE4C2_9", + "CMT_TOP_WW2A3_0", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_WW4A2_9", + "CMT_TOP_LH1_7", + "CMT_TOP_EE2BEG2_11", + "CMT_PHY_CONTROL_SYNCIN", + "CMT_TOP_NW4A1_6", + "CMT_TOP_BYP2_1", + "CMT_TOP_WL1END2_10", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_IMUX13_0", + "CMT_TOP_IMUX30_7", + "CMT_TOP_WW4A0_3", + "CMT_TOP_FAN2_0", + "CMT_TOP_BLOCK_OUTS_L_B1_9", + "CMT_TOP_IMUX18_9", + "CMT_PHASER_IN_CA_PHASELOCKED", + "CMT_TOP_CTRL1_0", + "CMT_TOP_EE2A0_5", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_TOP_WW4A0_1", + "CMT_PHASER_IN_DB_STG1REGL0", + "CMT_TOP_FAN3_0", + "CMT_TOP_LH2_7", + "CMT_TOP_IMUX30_2", + "CMT_TOP_FAN3_3", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_IMUX2_5", + "CMT_TOP_IMUX28_4", + "CMT_TOP_IMUX10_9", + "CMT_PHASER_IN_CA_STG1REGL3", + "CMT_TOP_EL1BEG3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_9", + "CMT_PHY_CONTROL_TESTINPUT4", + "CMT_TOP_LH11_0", + "CMT_TOP_EE4C1_11", + "CMT_TOP_IMUX15_5", + "CMT_TOP_IMUX13_8", + "CMT_TOP_SE4C1_9", + "CMT_TOP_EE4C0_5", + "CMT_TOP_IMUX2_0", + "CMT_PHASER_OUT_CA_OCLKDELAYED", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_SW4END1_1", + "CMT_TOP_LH12_7", + "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "CMT_TOP_WR1END3_7", + "CMT_TOP_WL1END1_7", + "CMT_TOP_OCLK_4", + "CMT_PHY_CONTROL_TESTSELECT1", + "CMT_TOP_EE4C1_2", + "CMT_TOP_BYP0_4", + "CMT_TOP_FAN4_0", + "CMT_TOP_BYP7_10", + "CMT_TOP_SW2A0_9", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_MONITOR_N_9", + "CMT_TOP_WW4A1_3", + "CMT_TOP_WW4END0_9", + "CMT_TOP_FAN4_4", + "CMT_TOP_ICLKDIV_9", + "CMT_PHY_CONTROL_TESTOUTPUT3", + "CMT_TOP_IMUX7_8", + "CMT_TOP_LOGIC_OUTS_L_B5_11", + "CMT_TOP_WW4B2_11", + "CMT_TOP_BYP7_0", + "CMT_TOP_FAN7_11", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_BYP6_2", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_EE4C2_8", + "CMT_PHASER_OUT_CA_OSERDESRST", + "CMT_TOP_IMUX14_6", + "CMT_TOP_LOGIC_OUTS_L_B19_11", + "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "CMT_TOP_SW4A2_11", + "CMT_TOP_IMUX10_1", + "CMT_TOP_NE4C3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_LOGIC_OUTS_L_B8_9", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_IMUX37_11", + "CMT_TOP_IMUX6_4", + "CMT_TOP_BLOCK_OUTS_L_B0_10", + "CMT_TOP_BLOCK_OUTS_L_B1_11", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_TOP_CTRL0_11", + "CMT_TOP_IMUX43_7", + "CMT_TOP_LOGIC_OUTS_L_B23_9", + "CMT_TOP_EE2BEG0_4", + "CMT_PHASER_REF_TESTIN3", + "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "CMT_PHY_CONTROL_IBURSTPENDING0", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LOGIC_OUTS_L_B7_10", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_IMUX38_7", + "CMT_TOP_IMUX21_10", + "CMT_PHASER_OUT_CA_COARSEINC", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_SW4A2_7", + "CMT_TOP_OCLK1X_90_10", + "CMT_PHASER_REF_TESTOUT5", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_LH1_2", + "CMT_TOP_BYP0_9", + "CMT_TOP_LOGIC_OUTS_L_B4_10", + "CMT_TOP_FAN4_10", + "CMT_TOP_IMUX30_3", + "CMT_TOP_WR1END3_10", + "CMT_TOP_EE2BEG3_9", + "CMT_TOP_WR1END1_6", + "CMT_TOP_SW2A2_5", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_NW2A1_8", + "CMT_TOP_IMUX15_11", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_IMUX36_9", + "CMT_TOP_EE4B2_1", + "CMT_TOP_SW2A2_0", + "CMT_TOP_NW4END2_3", + "CMT_TOP_FAN4_2", + "CMT_PHASER_IN_C_ICLKDIV", + "CMT_TOP_IMUX43_0", + "CMT_TOP_ER1BEG1_7", + "CMT_PHASER_IN_D_ICLKDIV", + "CMT_TOP_WW4END0_8", + "CMT_TOP_SW4A1_4", + "CMT_PHY_CONTROL_AUXOUTPUT3", + "CMT_PHASER_OUT_CA_SCANMODEB", + "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "CMT_TOP_IMUX29_0", + "CMT_TOP_FAN6_0", + "CMT_TOP_IMUX43_2", + "CMT_TOP_EE4B1_1", + "CMT_TOP_NW2A2_8", + "CMT_PHASER_IN_DB_STG1REGL5", + "CMT_TOP_CTRL1_10", + "CMT_TOP_WW2A0_3", + "CMT_PHY_CONTROL_TESTINPUT0", + "CMT_PHY_CONTROL_INBURSTPENDING2", + "CMT_TOP_WW2A2_5", + "CMT_TOP_SW4END1_6", + "CMT_TOP_FAN4_9", + "CMT_TOP_NE4BEG0_9", + "CMT_TOP_EE4B2_5", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_WW2A2_0", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", + "CMT_TOP_NE4C3_2", + "CMT_TOP_SE4BEG3_4", + "CMT_TOP_WW2END3_3", + "CMT_TOP_IMUX5_4", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_TOP_WW2END3_2", + "CMT_TOP_NE4C2_1", + "CMT_PHY_CONTROL_PHYCTLWD10", + "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "CMT_PHASER_OUT_CA_TESTIN15", + "CMT_TOP_SW4END2_2", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_NE2A3_8", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B2_11", + "CMT_TOP_SW4A1_3", + "CMT_TOP_NW4A2_8", + "CMT_TOP_WR1END1_5", + "CMT_TOP_SE4C2_5", + "CMT_TOP_LOGIC_OUTS_L_B22_11", + "CMT_TOP_ER1BEG3_3", + "CMT_PHY_CONTROL_AUXOUTPUT1", + "CMT_TOP_WW2A3_9", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_FAN2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_IMUX41_2", + "CMT_TOP_IMUX20_2", + "CMT_TOP_SW4END2_6", + "CMT_TOP_IMUX45_1", + "CMT_TOP_NW4END0_9", + "CMT_PHASER_OUT_CA_TESTIN4", + "CMT_TOP_IMUX24_9", + "CMT_TOP_WW4B3_3", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_NE4C3_3", + "CMT_TOP_BYP2_0", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_LH12_6", + "CMT_PHASER_IN_DB_TESTIN9", + "CMT_TOP_SW4END2_9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_EE4A1_1", + "CMT_TOP_IMUX27_9", + "CMT_TOP_SW4A0_10", + "CMT_TOP_IMUX26_3", + "CMT_TOP_SW4A2_0", + "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "CMT_TOP_EL1BEG3_9", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_LOGIC_OUTS_L_B2_10", + "CMT_TOP_IMUX47_0", + "CMT_TOP_IMUX7_10", + "CMT_TOP_FAN5_5", + "CMT_PHASER_IN_CA_SELCALORSTG1", + "CMT_TOP_NW4END2_10", + "CMT_TOP_SE4C0_3", + "CMT_TOP_IMUX45_4", + "CMT_TOP_EL1BEG1_11", + "CMT_PHASER_OUT_DB_SCANIN", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_EE2A3_7", + "CMT_TOP_EE4A3_9", + "CMT_TOP_IMUX19_0", + "CMT_TOP_WR1END0_0", + "CMT_TOP_EE4BEG1_9", + "CMT_TOP_NE2A3_3", + "CMT_TOP_WW4C1_8", + "CMT_TOP_SW4A3_10", + "CMT_TOP_FAN5_11", + "CMT_TOP_NE4C0_5", + "CMT_TOP_IMUX8_6", + "CMT_TOP_WL1END2_2", + "CMT_TOP_SE2A0_9", + "CMT_TOP_EE4A3_4", + "CMT_PHASER_IN_C_RCLK2", + "CMT_PHY_CONTROL_TESTOUTPUT5", + "CMT_PHASER_IN_DB_TESTIN12", + "CMT_TOP_BYP1_2", + "CMT_TOP_WW4END2_3", + "CMT_PHASER_UP_DQS_TO_PHASER_C", + "CMT_TOP_IMUX24_2", + "CMT_TOP_IMUX6_0", + "CMT_TOP_NW4END1_10", + "CMT_TOP_EE4BEG3_8", + "CMT_PHY_CONTROL_TESTINPUT2", + "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "CMT_TOP_WW2END2_10", + "CMT_TOP_EE4B2_0", + "CMT_TOP_SW2A0_7", + "CMT_TOP_CLK0_8", + "CMT_TOP_IMUX44_0", + "CMT_TOP_EE4C3_10", + "CMT_TOP_BYP4_6", + "CMT_TOP_WW2END1_11", + "CMT_PHY_CONTROL_READCALIBENABLE", + "CMT_TOP_IMUX9_4", + "CMT_TOP_IMUX7_0", + "CMT_TOP_EE4A0_4", + "CMT_TOP_LH9_6", + "CMT_TOP_SW2A3_7", + "CMT_TOP_WW4A3_9", + "CMT_TOP_NW4END3_8", + "CMT_TOP_NW4A1_2", + "CMT_TOP_SE2A0_7", + "CMT_TOP_WW4B1_3", + "CMT_TOP_BYP4_11", + "CMT_PHASER_OUT_CA_ENCALIB0", + "CMT_TOP_WR1END2_8", + "CMT_PHASER_OUT_DB_OCLK", + "CMT_TOP_NW2A0_2", + "CMT_TOP_EE4B0_3", + "CMT_TOP_FAN1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_10", + "CMT_TOP_SE2A1_4", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "CMT_TOP_SE4C0_6", + "CMT_TOP_IMUX17_4", + "CMT_TOP_LH2_10", + "CMT_PHASER_IN_C_WRENABLE_FIFO", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_SW4END2_4", + "CMT_TOP_WL1END0_6", + "CMT_TOP_IMUX37_2", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_EE4B3_6", + "CMT_TOP_NW4END2_5", + "CMT_TOP_EE4A1_7", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_IMUX15_3", + "CMT_TOP_LH7_10", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_WR1END3_9", + "CMT_TOP_WW2END3_10", + "CMT_TOP_ICLKDIV_2", + "CMT_PHY_CONTROL_TESTINPUT8", + "CMT_TOP_LH6_7", + "CMT_TOP_EE4C2_10", + "CMT_TOP_IMUX11_3", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_EE4B2_4", + "CMT_TOP_WW2A3_5", + "CMT_TOP_WW2END2_6", + "CMT_TOP_SW4END0_7", + "CMT_TOP_OCLK_9", + "CMT_TOP_LH1_9", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_BYP7_11", + "CMT_TOP_WL1END1_2", + "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "CMT_TOP_WW2A3_8", + "CMT_TOP_WW2END3_0", + "CMT_TOP_IMUX30_6", + "CMT_FREQ_BB_PREF_IN2", + "CMT_TOP_EL1BEG0_1", + "CMT_TOP_IMUX22_5", + "CMT_TOP_FAN2_11", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_IMUX12_0", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_NE2A1_1", + "CMT_TOP_IMUX19_3", + "CMT_TOP_WW4B0_5", + "CMT_TOP_ICLK_8", + "CMT_TOP_IMUX7_9", + "CMT_TOP_IMUX7_6", + "CMT_PHY_CONTROL_SCANENABLEN", + "CMT_TOP_SW2A1_2", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_IMUX36_2", + "CMT_TOP_WW2END3_1", + "CMT_TOP_NE4C0_1", + "CMT_TOP_IMUX11_11", + "CMT_TOP_BYP3_10", + "CMT_TOP_IMUX11_5", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_TOP_NE4BEG2_2", + "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "CMT_TOP_IMUX30_1", + "CMT_PHASER_IN_CA_WRENABLE", + "CMT_FREQ_BB_PREF_IN0", + "CMT_TOP_WW2END0_11", + "CMT_TOP_WW4C1_9", + "CMT_TOP_SE4C3_2", + "CMT_TOP_NE4C0_7", + "CMT_TOP_EE4A2_1", + "CMT_TOP_WW2END2_9", + "CMT_TOP_IMUX43_3", + "CMT_PHASER_OUT_CA_TESTOUT0", + "CMT_PHASER_OUT_DB_PHASEREFCLK", + "CMT_TOP_IMUX33_3", + "CMT_TOP_IMUX21_4", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_LH5_8", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_NW4A2_10", + "CMT_PHASER_IN_CA_TESTIN8", + "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "CMT_TOP_WW4END3_1", + "CMT_TOP_LOGIC_OUTS_L_B14_10", + "CMT_TOP_IMUX35_4", + "CMT_TOP_NE4C1_10", + "CMT_TOP_LOGIC_OUTS_L_B3_9", + "CMT_TOP_IMUX42_8", + "CMT_TOP_EE2A3_4", + "CMT_TOP_EE4BEG2_6", + "CMT_PHY_CONTROL_PHYCTLWD15", + "CMT_TOP_IMUX38_8", + "CMT_PHY_CONTROL_TESTOUTPUT7", + "CMT_PHASER_OUT_CA_TESTOUT2", + "CMT_TOP_CLK0_0", + "CMT_TOP_SE2A1_6", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_LH8_11", + "CMT_TOP_FAN7_2", + "CMT_TOP_EE2A0_7", + "CMT_PHASER_OUT_DB_CTSBUS1", + "CMT_TOP_NE4BEG2_10", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_WW4C3_9", + "CMT_TOP_EE2BEG0_10", + "CMT_TOP_IMUX37_1", + "CMT_TOP_EE4C3_5", + "CMT_TOP_NE4C3_5", + "CMT_PHASER_IN_DB_ENSTG1", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_BYP5_2", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_IMUX6_1", + "CMT_TOP_NE2A0_9", + "CMT_TOP_IMUX36_4", + "CMT_TOP_BYP4_1", + "CMT_TOP_IMUX9_3", + "CMT_TOP_IMUX15_6", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_IMUX7_3", + "CMT_TOP_NW4END1_1", + "CMT_TOP_FAN3_8", + "CMT_TOP_LH4_1", + "CMT_PHASER_OUT_DB_FINEENABLE", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX45_0", + "CMT_PHASER_C_OCLKDIV_TOIOI", + "CMT_TOP_EE4B1_9", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_FAN6_9", + "CMT_PHASER_IN_CA_TESTIN10", + "CMT_TOP_EE4C2_3", + "CMT_PHASER_IN_DB_TESTIN5", + "CMT_PHY_CONTROL_TESTOUTPUT11", + "CMT_TOP_WR1END1_8", + "CMT_TOP_IMUX19_9", + "CMT_TOP_IMUX5_10", + "CMT_PHASER_IN_CA_STG1REGR2", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_EL1BEG0_11", + "CMT_TOP_EE4A0_5", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NW2A0_5", + "CMT_TOP_IMUX24_10", + "CMT_PHASER_IN_CA_SCANIN", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_IMUX16_10", + "CMT_TOP_SW4END1_4", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX5_11", + "CMT_TOP_LOGIC_OUTS_L_B17_11", + "CMT_TOP_EE4C0_9", + "CMT_TOP_EE4B0_1", + "CMT_TOP_IMUX18_6", + "CMT_TOP_SW2A3_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_WW4A3_7", + "CMT_TOP_WW4A1_7", + "CMT_TOP_IMUX41_6", + "CMT_PHY_CONTROL_PHYCTLWD21", + "CMT_TOP_LH4_0", + "CMT_TOP_SW2A2_8", + "CMT_TOP_WW2A0_9", + "CMT_TOP_BYP2_7", + "CMT_PHASER_REF_TESTOUT1", + "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "CMT_TOP_SW4A1_2", + "CMT_TOP_IMUX4_10", + "CMT_TOP_FAN3_4", + "CMT_TOP_SW4END3_3", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH11_7", + "CMT_TOP_NW2A3_1", + "CMT_TOP_WW4A1_5", + "CMT_TOP_WW2A2_11", + "CMT_TOP_EE4C1_3", + "CMT_TOP_FAN3_5", + "CMT_PHASER_IN_CA_SYNCIN", + "CMT_TOP_WW2A2_7", + "CMT_TOP_BYP5_10", + "CMT_TOP_OCLK_1", + "CMT_TOP_EE4C1_9", + "CMT_TOP_WL1END3_4", + "CMT_TOP_EE2A0_10", + "CMT_PHASER_OUT_CA_ENCALIB1", + "PLL_CLK_FREQBB_REBUFOUT1", + "CMT_TOP_SW2A1_11", + "CMT_TOP_EE4B3_2", + "CMT_PHY_CONTROL_OUTBURSTPENDING3", + "CMT_TOP_NW4END2_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_FAN6_1", + "CMT_TOP_EE4C1_7", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_IMUX28_11", + "CMT_TOP_SE4C1_6", + "CMT_TOP_IMUX39_6", + "CMT_TOP_IMUX35_2", + "CMT_R_TOP_UPPER_B_CLKPLL2", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_NE2A1_9", + "CMT_TOP_WL1END0_2", + "CMT_TOP_IMUX33_10", + "CMT_TOP_LOGIC_OUTS_L_B22_9", + "CMT_TOP_IMUX44_1", + "CMT_TOP_IMUX41_10", + "CMT_PHASER_IN_CA_TESTIN12", + "CMT_PHASER_IN_CA_STG1REGL5", + "CMT_TOP_WW2A1_2", + "CMT_TOP_IMUX16_5", + "CMT_PHASER_IN_DB_STG1REGR3", + "CMT_PHASER_OUT_DB_OCLKDELAYED", + "CMT_TOP_NW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_PHASER_IN_DB_ENCALIBPHY1", + "CMT_TOP_IMUX39_7", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_TOP_SW4END3_10", + "CMT_TOP_IMUX26_0", + "CMT_TOP_EL1BEG0_4", + "CMT_TOP_IMUX4_6", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_PHY_CONTROL_IRANKA0", + "CMT_TOP_EE4B3_3", + "CMT_TOP_WW4B0_6", + "CMT_TOP_NW2A0_1", + "CMT_PHASER_REF_LOCKED", + "CMT_TOP_IMUX27_4", + "CMT_TOP_LOGIC_OUTS_L_B0_10", + "CMT_TOP_NE4BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_EE4C1_8", + "CMT_TOP_EE4C1_4", + "CMT_PHASER_IN_DB_TESTOUT3", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_SW2A3_9", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_ER1BEG0_0", + "CMT_PHASER_OUT_DB_TESTIN10", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_BYP2_4", + "CMT_PHASER_OUT_DB_TESTOUT1", + "CMT_TOP_IMUX0_9", + "CMT_TOP_NW2A3_6", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_CLK0_7", + "CMT_TOP_WL1END3_0", + "CMT_TOP_IMUX13_7", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_EE2A2_0", + "CMT_TOP_ICLK_4", + "CMT_TOP_LOGIC_OUTS_L_B21_9", + "CMT_TOP_IMUX4_0", + "CMT_TOP_MONITOR_P_9", + "CMT_TOP_IMUX3_6", + "CMT_TOP_EE4B0_11", + "CMT_TOP_BYP7_1", + "CMT_TOP_OCLKDIV_9", + "CMT_TOP_WW2END0_8", + "CMT_PHASER_OUT_CA_SCANENB", + "CMT_PHASERD_CTSBUS0", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_WW2END1_3", + "CMT_TOP_SE2A3_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_NE4BEG3_9", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_BYP3_4", + "CMT_TOP_SE4C3_0", + "CMT_TOP_IMUX25_8", + "CMT_TOP_ICLKDIV_1", + "CMT_PHASER_IN_DB_TESTOUT0", + "CMT_TOP_SW4END3_0", + "CMT_TOP_IMUX3_3", + "CMT_PHASER_IN_CA_STG1REGL0", + "CMT_TOP_WW2END1_2", + "CMT_PHASER_IN_CA_RANKSELPHY1", + "CMT_TOP_SE4C1_3", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_LH9_10", + "CMT_TOP_WW2A0_11", + "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "CMT_PHASER_OUT_D_OCLK1X_90", + "CMT_TOP_IMUX25_11", + "CMT_PHASER_IN_CA_STG1OVERFLOW", + "CMT_TOP_NW2A1_1", + "CMT_TOP_NW2A2_5", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX19_6", + "CMT_TOP_WW4A1_2", + "CMT_TOP_NW4A2_9", + "CMT_PHASER_OUT_D_OCLKDIV", + "CMT_TOP_IMUX19_11", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_SE4BEG2_5", + "CMT_PHY_CONTROL_OBURSTPENDING2", + "CMT_TOP_BLOCK_OUTS_L_B3_11", + "CMT_TOP_NE4C3_11", + "CMT_TOP_NW4END2_9", + "CMT_TOP_WW2A1_7", + "CMT_PHASER_IN_CA_TESTIN0", + "CMT_TOP_SW4END0_8", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WL1END0_4", + "CMT_PHASER_OUT_CA_DIVIDERST", + "CMT_TOP_IMUX35_1", + "CMT_TOP_NE4C1_1", + "CMT_TOP_WL1END0_5", + "CMT_TOP_IMUX6_9", + "CMT_PHASER_IN_DB_SCANCLK", + "CMT_PHY_CONTROL_IBURSTPENDING3", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_IMUX20_1", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_NE4BEG1_0", + "CMT_PHY_CONTROL_OUTBURSTPENDING2", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_WW4C3_0", + "CMT_TOP_FAN4_3", + "CMT_TOP_WR1END3_2", + "CMT_TOP_WW4B3_11", + "CMT_TOP_SE2A2_9", + "CMT_TOP_IMUX5_7", + "CMT_TOP_LH7_11", + "CMT_TOP_FAN7_10", + "CMT_TOP_IMUX22_11", + "CMT_TOP_IMUX40_10", + "CMT_TOP_WW2A2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_WW2END0_4", + "CMT_TOP_NW2A2_1", + "CMT_TOP_EE4A1_9", + "CMT_TOP_NE4C3_6", + "CMT_PHY_CONTROL_PHYCTLWD17", + "CMT_TOP_OCLK_7", + "CMT_PHASER_IN_DB_BURSTPENDING", + "CMT_TOP_ER1BEG2_0", + "CMT_PHASER_IN_CA_SCANMODEB", + "CMT_TOP_NW4A2_3", + "CMT_TOP_EE2BEG1_10", + "CMT_TOP_WW4C3_3", + "CMT_TOP_NW4END1_4", + "CMT_TOP_NW2A1_2", + "CMT_TOP_EE4BEG0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_TOP_WW4END0_7", + "CMT_TOP_SW4A3_2", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_IMUX5_8", + "CMT_TOP_WW4A1_11", + "CMT_TOP_SW4A1_5", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_IMUX32_6", + "CMT_TOP_MONITOR_N_11", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_NW2A2_6", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_WW4B0_10", + "CMT_TOP_WW4A1_0", + "CMT_PHY_CONTROL_PHYCTLWD8", + "CMT_TOP_EE2A3_6", + "CMT_TOP_WR1END2_10", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_BYP0_6", + "CMT_TOP_WL1END1_5", + "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "CMT_TOP_IMUX30_0", + "CMT_TOP_LOGIC_OUTS_L_B5_9", + "CMT_TOP_NW2A0_8", + "CMT_TOP_WW4C1_5", + "CMT_TOP_SE4BEG2_11", + "CMT_TOP_NW4A3_11", + "CMT_TOP_IMUX34_6", + "CMT_TOP_SW4A2_4", + "CMT_TOP_NE4C3_1", + "CMT_TOP_NW4A1_7", + "CMT_TOP_IMUX22_6", + "CMT_PHASER_IN_DB_RST", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX1_4", + "CMT_TOP_SW4A1_0", + "CMT_TOP_IMUX41_9", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_FAN2_2", + "CMT_TOP_IMUX33_4", + "CMT_PHASER_OUT_CA_SCANIN", + "CMT_TOP_SE4C0_8", + "CMT_TOP_EE2BEG0_11", + "CMT_TOP_IMUX32_8", + "CMT_PHY_CONTROL_TESTINPUT1", + "CMT_R_TOP_UPPER_B_CLKINT_2", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_EE2BEG1_3", + "CMT_TOP_EE2A2_4", + "CMT_TOP_WW4B2_7", + "CMT_TOP_EE4B1_3", + "CMT_TOP_SW4END0_0", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH10_2", + "CMT_TOP_IMUX4_8", + "CMT_TOP_NE4C1_11", + "CMT_TOP_WW2A1_1", + "CMT_TOP_EE4A1_0", + "CMT_PHASER_IN_DB_MEMREFCLK", + "CMT_TOP_IMUX9_6", + "CMT_TOP_IMUX42_3", + "CMT_TOP_IMUX13_10", + "CMT_TOP_WR1END0_6", + "CMT_TOP_OCLK1X_90_11", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_PHASER_IN_CA_ENCALIBPHY1", + "CMT_PHY_CONTROL_INRANKB0", + "CMT_TOP_IMUX22_2", + "CMT_TOP_SE4C3_6", + "CMT_TOP_IMUX44_4", + "CMT_TOP_CTRL0_1", + "CMT_TOP_IMUX29_10", + "CMT_TOP_IMUX12_11", + "CMT_TOP_WW4B2_0", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_LH12_5", + "CMT_TOP_NE4BEG3_11", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "CMT_TOP_IMUX12_6", + "CMT_TOP_IMUX23_4", + "CMT_TOP_NE4BEG1_5", + "CMT_TOP_NE2A3_6", + "CMT_TOP_ICLK_3", + "CMT_TOP_IMUX7_4", + "CMT_TOP_CLK0_4", + "CMT_TOP_SE2A3_4", + "CMT_TOP_NE2A3_11", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_IMUX28_6", + "CMT_TOP_WW4A3_8", + "CMT_TOP_EE2A0_0", + "CMT_TOP_SE2A1_0", + "CMT_TOP_LH12_10", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_PHY_CONTROL_PHYCTLREADY", + "CMT_TOP_WW4B1_2", + "CMT_TOP_CTRL1_3", + "CMT_TOP_EE4A3_8", + "CMT_TOP_NW4A0_2", + "CMT_TOP_IMUX26_5", + "CMT_TOP_IMUX27_10", + "CMT_TOP_EE4BEG3_10", + "CMT_TOP_LH6_3", + "CMT_TOP_IMUX40_6", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_WR1END2_4", + "CMT_TOP_WW4C1_11", + "CMT_TOP_IMUX20_4", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_TOP_WW4END2_7", + "CMT_TOP_BYP4_7", + "CMT_TOP_FAN4_11", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "CMT_PHASER_OUT_DB_FINEINC", + "CMT_TOP_NE2A2_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "CMT_TOP_SE4C0_9", + "CMT_TOP_IMUX34_0", + "CMT_TOP_NE2A1_6", + "CMT_TOP_NE4BEG3_10", + "CMT_TOP_IMUX2_9", + "CMT_PHY_CONTROL_PHYCTLWD23", + "CMT_TOP_IMUX0_8", + "CMT_TOP_IMUX31_6", + "CMT_TOP_IMUX36_10", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_TOP_WW4END3_7", + "CMT_TOP_WL1END0_9", + "CMT_PHASER_IN_CA_FINEOVERFLOW", + "CMT_PHASER_OUT_CA_TESTOUT1", + "CMT_PHY_CONTROL_PHYCTLWD24", + "CMT_TOP_SW4A0_1", + "CMT_PHY_CONTROL_INRANKC0", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE2A2_1", + "CMT_TOP_SW2A3_11", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_SW2A1_5", + "CMT_TOP_BLOCK_OUTS_L_B2_10", + "CMT_TOP_CTRL1_8", + "CMT_TOP_OCLK1X_90_9", + "CMT_TOP_NW4A2_5", + "CMT_TOP_NW4A0_0", + "CMT_PHASER_OUT_CA_SYSCLK", + "CMT_PHASER_IN_DB_STG1REGL1", + "CMT_TOP_WW2A1_10", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_IMUX41_1", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX11_7", + "CMT_TOP_NE4C2_11", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "CMT_PHY_CONTROL_TESTSELECT0", + "CMT_TOP_IMUX17_1", + "CMT_TOP_IMUX14_3", + "CMT_TOP_WW4A2_4", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_ICLKDIV_10", + "CMT_TOP_IMUX4_1", + "CMT_TOP_IMUX23_1", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_TOP_NW4A0_3", + "CMT_TOP_EE2A0_2", + "CMT_TOP_IMUX17_9", + "CMT_PHY_CONTROL_PHYCTLWRENABLE", + "CMT_PHASER_IN_DB_FREQREFCLK", + "CMT_TOP_LOGIC_OUTS_L_B21_11", + "CMT_PHASER_IN_CA_STG1REGR0", + "CMT_TOP_WW4END3_3", + "CMT_PHY_CONTROL_PHYCTLWD27", + "CMT_TOP_LH2_6", + "CMT_TOP_WW4B1_9", + "CMT_TOP_WR1END2_11", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_IMUX32_11", + "CMT_TOP_BYP2_8", + "CMT_TOP_WW4A0_0", + "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "CMT_PHASER_IN_CA_TESTIN1", + "CMT_TOP_WR1END3_5", + "CMT_TOP_SE4BEG1_3", + "CMT_PHY_CONTROL_PCENABLECALIB1", + "CMT_PHY_CONTROL_TESTOUTPUT6", + "CMT_TOP_WW4END3_2", + "CMT_TOP_WL1END3_3", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_IMUX34_8", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_CTRL0_7", + "CMT_TOP_IMUX43_9", + "CMT_TOP_IMUX11_1", + "CMT_TOP_IMUX13_1", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_SE2A2_3", + "CMT_TOP_NE2A3_4", + "CMT_TOP_OCLKDIV_11", + "CMT_TOP_EE4C2_6", + "CMT_TOP_SW2A0_5", + "CMT_TOP_SW2A3_10", + "CMT_TOP_LH7_9", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_CTRL1_1", + "CMT_PHY_CONTROL_TESTINPUT9", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_TOP_LH8_5", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_WL1END3_6", + "CMT_TOP_LH1_1", + "CMT_TOP_IMUX4_7", + "CMT_PHASER_IN_CA_COUNTERREADEN", + "CMT_TOP_WW4END2_10", + "CMT_TOP_IMUX24_4", + "CMT_PHY_CONTROL_IBURSTPENDING1", + "CMT_TOP_BYP7_9", + "CMT_TOP_FAN2_9", + "CMT_TOP_LOGIC_OUTS_L_B15_11", + "CMT_TOP_WW4A1_9", + "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "CMT_TOP_EE4C2_11", + "CMT_TOP_IMUX19_1", + "CMT_TOP_LOGIC_OUTS_L_B23_10", + "CMT_TOP_FAN2_8", + "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "CMT_TOP_NW2A1_9", + "CMT_TOP_LOGIC_OUTS_L_B8_11", + "CMT_PHY_CONTROL_PHYCTLFULL", + "CMT_TOP_SE4C2_7", + "CMT_TOP_LH5_9", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH7_2", + "CMT_TOP_IMUX13_6", + "CMT_TOP_IMUX1_1", + "CMT_PHASERD_DQSBUS0", + "CMT_TOP_IMUX4_11", + "CMT_TOP_LH3_8", + "CMT_TOP_EE4C3_3", + "CMT_TOP_SW4A0_0", + "CMT_TOP_SW2A1_8", + "CMT_TOP_IMUX5_9", + "CMT_TOP_IMUX46_0", + "CMT_TOP_IMUX3_0", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_TOP_EE4C2_0", + "CMT_TOP_IMUX16_1", + "CMT_TOP_IMUX16_0", + "CMT_TOP_SW4END2_5", + "CMT_TOP_EE2A1_0", + "CMT_TOP_IMUX12_7", + "CMT_TOP_NW4END0_4", + "CMT_PHASER_IN_CA_COUNTERLOADEN", + "CMT_TOP_NW4A0_9", + "CMT_TOP_IMUX47_5", + "CMT_TOP_WR1END1_3", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_IMUX42_9", + "CMT_PHASER_OUT_CA_DQSBUS1", + "CMT_TOP_IMUX31_2", + "CMT_PHASER_OUT_C_RDENABLE_TOFIFO", + "CMT_TOP_WR1END0_9", + "CMT_TOP_IMUX17_5", + "CMT_TOP_WW4END3_11", + "CMT_PHY_CONTROL_OUTBURSTPENDING1", + "CMT_TOP_CLK1_3", + "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "CMT_TOP_ICLKDIV_11", + "CMT_TOP_SE2A1_9", + "CMT_TOP_EE2A3_2", + "CMT_TOP_LH12_9", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_SE4C0_11", + "CMT_TOP_SE4C1_10", + "CMT_TOP_SE4C3_8", + "CMT_PHY_CONTROL_OBURSTPENDING1", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "CMT_TOP_IMUX43_11", + "CMT_TOP_IMUX39_1", + "CMT_TOP_LH1_3", + "CMT_TOP_BYP5_7", + "CMT_TOP_IMUX6_11", + "CMT_TOP_IMUX47_8", + "CMT_PHASER_IN_DB_TESTIN6", + "CMT_TOP_IMUX36_0", + "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "CMT_PHASER_IN_D_RCLK3", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_NW4A2_2", + "CMT_PHASER_IN_CA_RANKSEL1", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_IMUX26_9", + "CMT_TOP_IMUX46_10", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END1_6", + "CMT_PHASER_OUT_DB_TESTIN1", + "CMT_TOP_WL1END1_8", + "CMT_PHASER_IN_DB_WRENABLE", + "CMT_PHASER_OUT_DB_COUNTERREADEN", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_WW2END1_6", + "CMT_TOP_WW4END0_6", + "CMT_TOP_SE2A2_6", + "CMT_TOP_WW4A3_11", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_FAN5_0", + "CMT_PHASERTOP_PHYCTLEMPTY", + "CMT_TOP_LOGIC_OUTS_L_B3_11", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_IMUX7_2", + "CMT_TOP_SW4A3_11", + "CMT_PHASER_OUT_DB_TESTIN12", + "CMT_TOP_SE2A3_10", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_LH2_0", + "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "CMT_TOP_SE2A0_6", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LH9_2", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B4_9", + "CMT_PHASER_IN_DB_STG1REGR8", + "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "CMT_TOP_WW2A3_1", + "CMT_TOP_LH5_3", + "CMT_TOP_NE2A0_6", + "CMT_TOP_FAN4_1", + "CMT_TOP_LH12_1", + "CMT_TOP_LH8_6", + "CMT_TOP_IMUX36_5", + "CMT_TOP_OCLK_6", + "CMT_TOP_SW4END1_5", + "CMT_TOP_LOGIC_OUTS_L_B1_9", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_FAN6_6", + "CMT_TOP_NE2A2_7", + "CMT_TOP_LH7_6", + "CMT_PHASER_OUT_CA_TESTOUT3", + "CMT_TOP_WW4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_PHASER_IN_CA_ENCALIB0", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX45_3", + "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "CMT_TOP_NE4BEG1_10", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_WR1END1_10", + "CMT_TOP_LOGIC_OUTS_L_B16_10", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_SW2A0_3", + "CMT_TOP_EE4C0_7", + "CMT_TOP_NW2A0_11", + "CMT_TOP_NW4END1_6", + "CMT_TOP_IMUX34_11", + "CMT_TOP_IMUX38_4", + "CMT_TOP_FAN6_7", + "CMT_PHASER_OUT_DB_SCANOUT", + "CMT_TOP_EE4BEG1_11", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_IMUX41_5", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_SW4END2_3", + "CMT_TOP_EE2BEG3_8", + "CMT_TOP_LH9_7", + "CMT_PHASER_IN_DB_TESTIN1", + "CMT_PHASER_REF_TMUXOUT", + "CMT_TOP_WW4A1_1", + "CMT_TOP_WR1END0_3", + "CMT_TOP_LH1_6", + "CMT_TOP_FAN2_7", + "CMT_TOP_BYP7_6", + "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "CMT_TOP_IMUX40_11", + "CMT_TOP_NW4A1_5", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_1", + "CMT_TOP_IMUX2_10", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_IMUX32_10", + "CMT_TOP_FAN6_8", + "CMT_TOP_EE4BEG1_10", + "CMT_TOP_NW4A2_4", + "CMT_TOP_WW4C2_4", + "CMT_TOP_LH6_5", + "CMT_TOP_LOGIC_OUTS_L_B11_9", + "CMT_TOP_FAN5_7", + "CMT_TOP_OCLK_2", + "CMT_TOP_WL1END1_6", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_BYP6_0", + "CMT_TOP_WL1END3_9", + "CMT_PHY_CONTROL_TESTSELECT2", + "CMT_TOP_EE2BEG2_6", + "CMT_PHASER_IN_CA_DQSFOUND", + "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "CMT_TOP_WW2END3_9", + "CMT_TOP_IMUX25_9", + "CMT_TOP_NW4END1_7", + "CMT_TOP_EE2A1_4", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_IMUX33_6", + "CMT_TOP_LH2_8", + "CMT_PHY_CONTROL_TESTINPUT14", + "CMT_TOP_NW4A2_6", + "CMT_TOP_NE4C1_6", + "CMT_TOP_IMUX8_9", + "CMT_TOP_NE2A0_3", + "CMT_PHASER_IN_CA_TESTIN6", + "CMT_TOP_SE4C3_7", + "CMT_TOP_IMUX34_10", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_IMUX31_1", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_WW4C3_7", + "CMT_TOP_IMUX32_9", + "CMT_TOP_IMUX8_4", + "CMT_TOP_NW2A2_10", + "CMT_TOP_IMUX33_1", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_WW4END1_3", + "CMT_TOP_FAN1_11", + "CMT_TOP_SW2A0_1", + "CMT_TOP_IMUX33_8", + "CMT_TOP_NW4A1_3", + "CMT_TOP_LH10_0", + "CMT_TOP_LH5_6", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX7_5", + "CMT_TOP_EE4C2_1", + "CMT_TOP_NE2A3_9", + "CMT_TOP_ER1BEG2_5", + "CMT_TOP_NW2A3_11", + "CMT_PHASER_IN_DB_STG1REGR6", + "CMT_TOP_EE4BEG1_5", + "CMT_TOP_EE4C2_4", + "CMT_TOP_EE2A1_3", + "CMT_TOP_SW4A2_3", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_NE4C3_7", + "CMT_TOP_IMUX12_2", + "CMT_TOP_WW4B1_8", + "CMT_TOP_SE2A1_11", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_IMUX3_9", + "CMT_PHASER_OUT_DB_ENCALIB0", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_PHASER_IN_DB_RANKSELPHY0", + "CMT_TOP_IMUX21_3", + "CMT_TOP_LH4_11", + "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "CMT_TOP_EE4A2_3", + "CMT_TOP_LH1_11", + "CMT_TOP_SW4A2_6", + "CMT_TOP_IMUX35_8", + "CMT_TOP_IMUX9_0", + "CMT_TOP_SW4END0_11", + "CMT_PHASER_IN_D_WRCLK_TOFIFO", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_PHY_CONTROL_TESTINPUT5", + "CMT_TOP_IMUX16_4", + "CMT_TOP_IMUX39_11", + "CMT_TOP_LH2_4", + "CMT_FREQ_BB_PREF_IN3", + "CMT_TOP_LOGIC_OUTS_L_B14_9", + "CMT_TOP_WW4C0_2", + "CMT_TOP_CTRL1_11", + "CMT_TOP_EE4B2_11", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_LH3_6", + "CMT_PHASER_OUT_D_OCLK", + "CMT_TOP_EE4C3_0", + "CMT_TOP_IMUX40_1", + "CMT_TOP_CLK0_10", + "CMT_TOP_EE4B0_10", + "CMT_TOP_IMUX20_11", + "CMT_TOP_WW4C3_11", + "CMT_TOP_FAN7_9", + "CMT_TOP_IMUX32_2", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_R_TOP_UPPER_B_CLKPLL5", + "CMT_TOP_LH1_4", + "CMT_TOP_BYP1_11", + "CMT_PHASER_IN_CA_RANKSELPHY0", + "CMT_TOP_BYP0_1", + "CMT_TOP_FAN3_10", + "CMT_TOP_NE4C0_6", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_IMUX24_1", + "CMT_PHASER_OUT_C_OCLKDIV", + "CMT_TOP_IMUX12_1", + "CMT_TOP_IMUX29_3", + "CMT_PHASER_C_ICLK_TOIOI", + "CMT_TOP_IMUX18_0", + "CMT_PHASER_IN_CA_STG1REGR6", + "CMT_TOP_SW2A0_6", + "CMT_TOP_FAN7_6", + "CMT_TOP_LOGIC_OUTS_L_B21_10", + "CMT_TOP_IMUX24_11", + "CMT_PHASER_OUT_DB_MEMREFCLK", + "CMT_TOP_EE4A0_3", + "CMT_TOP_SW2A3_6", + "CMT_TOP_IMUX10_10", + "CMT_TOP_BLOCK_OUTS_L_B2_11", + "CMT_TOP_IMUX44_11", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_NW2A0_7", + "CMT_TOP_WR1END2_5", + "CMT_TOP_BYP5_3", + "CMT_TOP_NW4A2_1", + "CMT_TOP_FAN5_6", + "CMT_TOP_IMUX32_4", + "CMT_TOP_LH6_11", + "CMT_TOP_SE4BEG3_9", + "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "CMT_R_TOP_UPPER_B_CLKFBIN", + "CMT_TOP_EE4C3_1", + "CMT_TOP_CTRL0_3", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_PHASER_UP_BUFMRCE_CE1", + "CMT_TOP_LH5_11", + "CMT_TOP_SE4BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_SW4END1_7", + "CMT_TOP_NW4A3_10", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_IMUX6_5", + "CMT_TOP_WW4A3_5", + "CMT_PHASER_OUT_DB_TESTIN14", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_BYP3_9", + "CMT_TOP_IMUX26_2", + "CMT_TOP_IMUX20_10", + "CMT_TOP_IMUX13_4", + "CMT_PHASER_IN_DB_RANKSEL1", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_WW4C3_8", + "CMT_PHASER_IN_DB_TESTIN13", + "CMT_TOP_NE2A0_8", + "CMT_TOP_LH6_4", + "CMT_TOP_NW2A2_4", + "CMT_TOP_IMUX20_9", + "CMT_TOP_WW2END3_6", + "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "CMT_PHASER_IN_CA_RANKSEL0", + "CMT_TOP_FAN6_10", + "CMT_TOP_EE4B2_9", + "CMT_TOP_WW4B1_1", + "CMT_PHASER_C_ICLKDIV_TOIOI", + "CMT_TOP_WW4B1_7", + "CMT_TOP_WW2A3_4", + "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "CMT_TOP_NW4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_IMUX9_11", + "CMT_TOP_BYP7_3", + "CMT_TOP_IMUX25_0", + "CMT_PHASER_IN_CA_TESTIN3", + "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "CMT_TOP_NE4C2_8", + "CMT_PHASER_OUT_DB_SCANENB", + "CMT_PHASER_OUT_DB_FREQREFCLK", + "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "CMT_TOP_IMUX41_0", + "CMT_PHASER_IN_DB_STG1REGR2", + "CMT_TOP_WL1END2_9", + "CMT_TOP_LH4_4", + "CMT_TOP_IMUX24_3", + "CMT_PHY_CONTROL_IRANKB0", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_R_TOP_UPPER_B_CLKPLL0", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_NW2A0_4", + "CMT_TOP_EE2A1_2", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX46_3", + "CMT_TOP_WW2END3_11", + "CMT_TOP_CLK1_11", + "CMT_TOP_EE4A2_0", + "CMT_TOP_SE2A2_4", + "CMT_TOP_IMUX29_11", + "CMT_TOP_EE4A0_7", + "CMT_TOP_WW4C2_3", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_IMUX32_3", + "CMT_TOP_EE2A0_11", + "CMT_TOP_IMUX11_8", + "CMT_TOP_ER1BEG2_10", + "CMT_PHASERD_DTSBUS0", + "CMT_TOP_IMUX27_5", + "CMT_TOP_IMUX36_8", + "CMT_TOP_NW2A1_10", + "CMT_PHASER_UP_PHASERREF_ABOVE1", + "CMT_TOP_WL1END1_0", + "CMT_TOP_IMUX47_3", + "CMT_TOP_IMUX0_2", + "CMT_PHASER_IN_DB_ENCALIBPHY0", + "CMT_PHASER_OUT_DB_TESTIN13", + "CMT_PHASER_REF_TESTIN4", + "CMT_TOP_NW4END3_11", + "CMT_PHY_CONTROL_TESTINPUT10", + "CMT_TOP_WW2A1_6", + "CMT_TOP_SW4A2_1", + "CMT_TOP_NW2A2_2", + "CMT_PHASER_IN_DB_STG1REGR5", + "CMT_TOP_NW2A0_10", + "CMT_TOP_IMUX5_5", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4BEG1_4", + "CMT_TOP_WW4END3_9", + "CMT_TOP_MONITOR_P_2", + "CMT_FREQ_PHASER_REFMUX_0", + "CMT_TOP_IMUX30_11", + "CMT_TOP_WW4C3_1", + "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "CMT_TOP_IMUX33_5", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SE4C2_3", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_EE4A0_9", + "CMT_PHASER_OUT_CA_EDGEADV", + "CMT_TOP_LH7_7", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_BYP6_10", + "CMT_TOP_NW4END3_1", + "CMT_TOP_EE2BEG3_10", + "CMT_TOP_WW2END0_5", + "CMT_TOP_LH5_1", + "CMT_TOP_LH8_7", + "CMT_TOP_OCLK_11", + "CMT_PHASER_OUT_CA_CTSBUS0", + "CMT_TOP_FAN6_5", + "CMT_TOP_IMUX27_1", + "CMT_TOP_NE4BEG2_1", + "CMT_PHY_CONTROL_TESTOUTPUT9", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_SE2A2_8", + "CMT_TOP_SE4C3_10", + "CMT_TOP_WL1END2_5", + "CMT_TOP_WW2A2_9", + "CMT_TOP_SE2A3_9", + "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "CMT_TOP_IMUX14_8", + "CMT_PHY_CONTROL_INRANKA0", + "CMT_TOP_NW4END3_4", + "CMT_TOP_NE2A2_3", + "CMT_TOP_LH8_2", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_EE4A2_10", + "CMT_TOP_IMUX19_10", + "CMT_PHASER_IN_CA_ENCALIB1", + "CMT_TOP_EE4BEG2_11", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_WW2END0_10", + "CMT_TOP_NE4BEG3_0", + "CMT_PHY_CONTROL_INRANKC1", + "CMT_TOP_SE2A3_2", + "CMT_TOP_ER1BEG3_10", + "CMT_TOP_CLK1_8", + "CMT_TOP_EL1BEG2_11", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_NW4A0_1", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_NW4END2_1", + "CMT_TOP_EE4B0_8", + "CMT_TOP_NW4END2_8", + "CMT_TOP_CLK0_6", + "CMT_TOP_WR1END2_6", + "CMT_TOP_WW4END0_1", + "CMT_TOP_NW2A1_7", + "CMT_TOP_WW4A2_6", + "CMT_TOP_IMUX27_3", + "CMT_TOP_SW2A3_0", + "CMT_TOP_EE2A2_9", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_WR1END2_2", + "CMT_TOP_EE4BEG2_9", + "CMT_TOP_EE2A2_7", + "CMT_PHASER_IN_CA_STG1REGL7", + "CMT_TOP_IMUX26_10", + "CMT_TOP_IMUX8_0", + "CMT_TOP_IMUX21_9", + "CMT_PHASER_IN_CA_STG1REGL8", + "CMT_TOP_WW4C1_1", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_LH5_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4C2_0", + "CMT_TOP_EE2A2_11", + "CMT_TOP_WR1END0_8", + "CMT_TOP_WW4C0_10", + "CMT_TOP_WL1END1_4", + "CMT_TOP_WW4B1_6", + "CMT_PHASER_IN_DB_FINEOVERFLOW", + "CMT_TOP_WW2A3_7", + "CMT_TOP_BYP3_6", + "CMT_TOP_EE4B1_8", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_IMUX9_1", + "CMT_TOP_SE4C1_5", + "CMT_TOP_LH4_7", + "CMT_TOP_LOGIC_OUTS_L_B5_10", + "CMT_TOP_IMUX20_5", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_NE4C2_4", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_WW4B1_0", + "CMT_TOP_IMUX0_10", + "CMT_PHASER_REF_RST", + "CMT_TOP_IMUX23_7", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_TOP_EE4A2_7", + "CMT_TOP_FAN3_9", + "CMT_TOP_EE2A0_8", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_NW4END0_8", + "CMT_TOP_WW4B2_3", + "CMT_TOP_IMUX23_0", + "CMT_TOP_EE2BEG3_1", + "CMT_TOP_LH6_8", + "CMT_TOP_SW4END0_10", + "CMT_PHASER_IN_DB_SYNCIN", + "CMT_TOP_LH6_10", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_PHASER_REF_TMUXOUT_TOHCLK", + "CMT_TOP_WL1END0_0", + "CMT_PHASER_IN_CA_RSTDQSFIND", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_FAN0_2", + "CMT_TOP_LOGIC_OUTS_L_B10_10", + "CMT_TOP_LH2_11", + "CMT_TOP_WW2END2_0", + "CMT_TOP_IMUX18_3", + "CMT_PHY_CONTROL_TESTOUTPUT14", + "CMT_TOP_IMUX6_10", + "CMT_TOP_FAN1_1", + "CMT_TOP_NW2A3_8", + "CMT_PHASER_OUT_CA_DTSBUS0", + "CMT_TOP_LH7_1", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_IMUX43_5", + "CMT_TOP_SE4BEG1_10", + "CMT_TOP_EE4B1_10", + "CMT_TOP_IMUX41_4", + "CMT_PHASER_IN_DB_TESTIN2", + "CMT_TOP_IMUX33_0", + "CMT_PHY_CONTROL_PHYCTLEMPTY", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_SE2A3_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "CMT_TOP_SE4C0_0", + "CMT_PHY_CONTROL_IBURSTPENDING2", + "CMT_TOP_NE2A2_9", + "CMT_PHASER_OUT_DB_OCLKDIV", + "CMT_TOP_OCLKDIV_2", + "CMT_PHASER_IN_DB_TESTOUT1", + "CMT_TOP_WW4B3_4", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX5_3", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_BYP2_9", + "CMT_TOP_IMUX23_10", + "CMT_TOP_LH5_0", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_IMUX42_10", + "CMT_TOP_LH10_10", + "CMT_TOP_WW4END2_11", + "CMT_TOP_EE4A1_4", + "CMT_TOP_NW4A1_10", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX11_0", + "CMT_TOP_WW2END3_5", + "CMT_TOP_LH7_8", + "CMT_TOP_NE4C1_3", + "CMT_TOP_CTRL1_6", + "CMT_TOP_WW4C2_11", + "CMT_TOP_CLK1_9", + "CMT_TOP_IMUX31_3", + "CMT_TOP_IMUX37_3", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_LOGIC_OUTS_L_B18_11", + "CMT_TOP_WW4C0_0", + "CMT_TOP_WW4A0_5", + "CMT_TOP_EE4C3_9", + "CMT_PHASER_IN_DB_TESTIN8", + "CMT_TOP_IMUX3_8", + "CMT_TOP_NW4END1_11", + "CMT_PHY_CONTROL_AUXOUTPUT0", + "CMT_TOP_WW2A1_5", + "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", + "CMT_TOP_LOGIC_OUTS_L_B9_10", + "CMT_TOP_SE2A0_4", + "CMT_TOP_IMUX15_1", + "CMT_TOP_IMUX6_3", + "CMT_TOP_IMUX45_9", + "CMT_TOP_EE4B2_7", + "CMT_PHASER_IN_CA_STG1REGR1", + "CMT_TOP_NW2A2_9", + "CMT_PHY_CONTROL_INBURSTPENDING0", + "CMT_TOP_LH3_11", + "CMT_TOP_WR1END0_7", + "CMT_TOP_IMUX24_5", + "CMT_TOP_FAN2_1", + "CMT_TOP_IMUX5_6", + "CMT_TOP_NW4END0_10", + "CMT_TOP_SE4BEG0_9", + "CMT_TOP_NW4END1_9", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_BYP6_5", + "CMT_TOP_ER1BEG3_5", + "CMT_FREQ_PHASER_REFMUX_2", + "CMT_TOP_IMUX37_5", + "CMT_PHY_CONTROL_PHYCTLWD1", + "CMT_TOP_IMUX37_8", + "CMT_TOP_EE4C0_0", + "CMT_TOP_WW4END2_1", + "CMT_PHASER_IN_CA_STG1INCDEC", + "CMT_TOP_EE4A1_6", + "CMT_TOP_LOGIC_OUTS_L_B12_10", + "CMT_TOP_SW4END1_0", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_IMUX35_3", + "CMT_TOP_WW4A2_3", + "CMT_PHASER_IN_DB_PHASELOCKED", + "CMT_TOP_BYP6_9", + "CMT_TOP_IMUX10_4", + "CMT_TOP_LOGIC_OUTS_L_B13_9", + "CMT_TOP_WW4END2_6", + "CMT_PHASER_IN_DB_TESTIN11", + "CMT_PHASER_OUT_CA_BURSTPENDING", + "CMT_TOP_IMUX26_6", + "CMT_TOP_EE4A3_0", + "CMT_PHASER_IN_CA_DIVIDERST", + "CMT_TOP_IMUX18_10", + "CMT_TOP_IMUX22_10", + "CMT_TOP_EE2A1_5", + "CMT_TOP_SW4END3_1", + "CMT_TOP_EL1BEG1_6", + "CMT_PHASER_REF_TESTIN1", + "CMT_TOP_IMUX4_4", + "CMT_TOP_NW4END3_3", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_WW4C1_2", + "CMT_PHASER_OUT_DB_ENCALIB1", + "CMT_TOP_SW4A2_9", + "CMT_TOP_IMUX22_0", + "CMT_TOP_LOGIC_OUTS_L_B16_11", + "CMT_TOP_SE2A1_1", + "CMT_PHASER_IN_DB_RCLK", + "CMT_TOP_NW2A3_9", + "CMT_TOP_WR1END0_4", + "CMT_TOP_EE2A0_4", + "CMT_TOP_WW4A1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_EE4C0_6", + "CMT_TOP_IMUX24_0", + "CMT_PHASER_IN_CA_TESTOUT3", + "CMT_PHASER_OUT_CA_SYNCIN", + "CMT_TOP_EL1BEG1_4", + "CMT_TOP_WW4B3_10", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_SW2A3_3", + "CMT_TOP_SW4END0_1", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_EE4B1_0", + "CMT_TOP_NE2A3_2", + "CMT_TOP_ER1BEG1_9", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_PHASERREF_PHASEROUT_D", + "CMT_PHY_CONTROL_PHYCTLWD3", + "CMT_TOP_EE4B1_6", + "CMT_TOP_LH3_9", + "CMT_TOP_BYP3_2", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_SE4BEG1_9", + "CMT_TOP_IMUX34_9", + "CMT_TOP_CLK0_2", + "CMT_TOP_SE4C1_11", + "CMT_TOP_LH10_1", + "CMT_TOP_EE2BEG2_3", + "CMT_PHY_CONTROL_TESTINPUT11", + "CMT_TOP_SE4BEG3_11", + "CMT_TOP_LOGIC_OUTS_L_B10_11", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_FAN3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_TOP_WW4A0_9", + "CMT_TOP_SW2A1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_IMUX3_4", + "CMT_TOP_ICLK_5", + "CMT_TOP_IMUX47_9", + "CMT_PHASER_REF_CLKOUT_TOHCLK", + "CMT_PHASER_REF_TESTOUT3", + "CMT_TOP_IMUX15_9", + "CMT_PHY_CONTROL_PHYCTLWD13", + "CMT_PHASER_OUT_DB_SCANMODEB", + "CMT_TOP_IMUX31_0", + "CMT_PHASER_IN_DB_DIVIDERST", + "CMT_TOP_IMUX29_8", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_LH2_3", + "CMT_TOP_WR1END1_9", + "CMT_TOP_IMUX28_10", + "CMT_R_TOP_UPPER_B_CLKINT_3", + "CMT_TOP_NE4C1_4", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_IMUX2_4", + "CMT_PHASER_IN_D_WRENABLE_FIFO", + "CMT_PHASER_OUT_CA_TESTIN8", + "CMT_TOP_IMUX38_11", + "CMT_TOP_EE4C1_1", + "CMT_TOP_SW2A0_4", + "CMT_PHASER_OUT_D_RDCLK_TOFIFO", + "CMT_PHY_CONTROL_PHYCTLWD6", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_LH8_4", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_WW4END2_0", + "CMT_TOP_EE4C0_1", + "CMT_PHASER_OUT_CA_CTSBUS1", + "CMT_TOP_IMUX33_11", + "CMT_TOP_FAN5_8", + "CMT_TOP_WW4C1_0", + "CMT_TOP_LOGIC_OUTS_L_B11_11", + "CMT_TOP_EE2A3_9", + "CMT_TOP_LH10_7", + "CMT_TOP_SE4C0_1", + "CMT_TOP_NW4END3_9", + "CMT_TOP_WW4C1_7", + "CMT_TOP_SE2A0_5", + "CMT_TOP_EE2BEG1_9", + "CMT_PHASER_OUT_CA_TESTIN6", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_ER1BEG3_9", + "CMT_TOP_IMUX47_11", + "CMT_TOP_SE4BEG0_7", + "CMT_PHASER_IN_C_WRCLK_TOFIFO", + "CMT_PHASER_UP_DQS_TO_PHASER_D", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BYP0_0", + "CMT_TOP_EE4B2_2", + "CMT_TOP_FAN7_7", + "CMT_PHASER_OUT_DB_TESTIN6", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_WW4A0_4", + "CMT_TOP_WW4A3_0", + "CMT_TOP_SE4C1_1", + "CMT_TOP_ER1BEG0_6", + "CMT_TOP_IMUX46_1", + "CMT_TOP_FAN6_11", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_IMUX30_8", + "CMT_TOP_SW2A1_0", + "CMT_TOP_CLK0_1", + "CMT_TOP_BYP5_4", + "CMT_PHY_CONTROL_TESTINPUT3", + "CMT_TOP_IMUX45_2", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_WW4C2_6", + "CMT_TOP_IMUX19_5", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_NW4END0_1", + "CMT_TOP_LH3_10", + "CMT_PHASERD_DTSBUS1", + "CMT_TOP_LH9_8", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_PHASER_IN_CA_STG1REGL4", + "CMT_TOP_NW2A2_7", + "CMT_TOP_SW4END0_5", + "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "CMT_TOP_IMUX29_1", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_IMUX9_5", + "CMT_PHY_CONTROL_PHYCTLWD26", + "CMT_TOP_SW4A0_2", + "CMT_TOP_WW2END1_5", + "CMT_TOP_WW2A2_8", + "CMT_TOP_OCLK_8", + "CMT_TOP_IMUX46_7", + "CMT_TOP_IMUX8_3", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_IMUX14_7", + "CMT_TOP_NW2A2_0", + "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "CMT_TOP_SE4C0_5", + "CMT_TOP_SW4END3_4", + "CMT_TOP_SE2A2_7", + "CMT_TOP_SW2A1_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_IMUX22_8", + "CMT_PHASERD_DQSBUS1", + "CMT_TOP_LH3_7", + "CMT_TOP_IMUX1_11", + "CMT_TOP_SE2A1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_9", + "CMT_TOP_IMUX43_8", + "CMT_TOP_LH10_5", + "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "CMT_PHASER_OUT_DB_DQSBUS0", + "CMT_TOP_NE4BEG2_5", + "CMT_PHASER_IN_CA_STG1REGL1", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_BLOCK_OUTS_L_B3_10", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_NE2A0_0", + "CMT_TOP_NE2A2_6", + "CMT_TOP_WW4C2_9", + "CMT_TOP_SW2A2_2", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_LH11_1", + "CMT_TOP_EE2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_LOGIC_OUTS_L_B20_10", + "CMT_PHASER_OUT_CA_FINEINC", + "CMT_TOP_WW2A2_4", + "CMT_TOP_EE4C1_10", + "CMT_TOP_LH5_2", + "CMT_TOP_IMUX17_8", + "CMT_TOP_IMUX36_7", + "CMT_TOP_BYP1_7", + "CMT_PHY_CONTROL_ECALIB1", + "CMT_TOP_IMUX4_5", + "CMT_TOP_EE4C0_4", + "CMT_TOP_EL1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B13_10", + "CMT_TOP_LOGIC_OUTS_L_B19_10", + "CMT_TOP_ICLK_7", + "CMT_TOP_NE4BEG0_10", + "CMT_TOP_LH11_3", + "CMT_PHASER_IN_CA_ENSTG1", + "CMT_TOP_IMUX32_1", + "CMT_TOP_IMUX11_4", + "CMT_TOP_IMUX9_10", + "CMT_TOP_SW2A2_4", + "CMT_TOP_EE4C3_7", + "CMT_PHASER_OUT_DB_TESTOUT0", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_WW4B3_0", + "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "CMT_TOP_IMUX10_5", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "CMT_TOP_WW2END1_1", + "CMT_TOP_FAN0_9", + "CMT_TOP_FAN1_7", + "CMT_TOP_IMUX23_2", + "CMT_PHASER_REF_TESTIN6", + "CMT_TOP_ICLK_6", + "CMT_TOP_IMUX5_0", + "CMT_TOP_EE4A2_9", + "CMT_TOP_IMUX22_1", + "CMT_TOP_WW4B0_8", + "CMT_TOP_IMUX42_11", + "CMT_TOP_OCLKDIV_6", + "CMT_PHASER_C_OCLK_TOIOI", + "CMT_TOP_LH2_9", + "CMT_TOP_NW4A3_1", + "CMT_TOP_IMUX27_0", + "CMT_PHY_CONTROL_TESTOUTPUT13", + "CMT_TOP_SE4C2_8", + "CMT_TOP_WW2END0_9", + "CMT_PHASER_OUT_CA_TESTIN9", + "CMT_TOP_SE4C2_4", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_SE2A2_1", + "CMT_TOP_NW4END1_5", + "CMT_TOP_EE2BEG0_7", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_PHASER_UP_PHASERREF_BELOW1", + "CMT_TOP_IMUX14_10", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX42_7", + "CMT_TOP_EL1BEG0_9", + "CMT_TOP_IMUX41_11", + "CMT_TOP_EE2BEG0_2", + "CMT_PHASERTOP_PHYCTLMSTREMPTY", + "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "CMT_TOP_WR1END1_11", + "CMT_TOP_IMUX35_7", + "CMT_PHY_CONTROL_TESTOUTPUT1", + "CMT_PHASER_OUT_DB_TESTIN8", + "CMT_PHY_CONTROL_IRANKB1", + "CMT_TOP_SW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_FAN3_7", + "CMT_TOP_LH9_9", + "CMT_TOP_SW4A1_1", + "CMT_TOP_SW2A0_8", + "CMT_TOP_IMUX28_9", + "CMT_TOP_EE4B3_7", + "CMT_TOP_WW2A3_11", + "CMT_TOP_IMUX44_3", + "CMT_TOP_IMUX31_10", + "CMT_TOP_EE4B3_10", + "CMT_TOP_NE4C1_9", + "CMT_TOP_SE2A0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_BYP2_3", + "CMT_TOP_IMUX12_10", + "CMT_TOP_IMUX40_3", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_IMUX11_6", + "CMT_TOP_EE4BEG0_1", + "CMT_R_TOP_UPPER_B_CLKIN2", + "CMT_TOP_IMUX39_10", + "CMT_PHASER_IN_CA_ISERDESRST", + "CMT_TOP_BYP4_2", + "CMT_TOP_NE4BEG3_8", + "CMT_TOP_IMUX1_10", + "CMT_PHASER_IN_CA_STG1REGL2", + "CMT_PHASERREF_PHASERIN_D", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_SW2A1_9", + "CMT_TOP_IMUX26_7", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "CMT_TOP_IMUX1_7", + "CMT_TOP_IMUX23_6", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_FAN5_10", + "CMT_TOP_IMUX6_8", + "CMT_PHASER_OUT_CA_OCLK", + "CMT_TOP_IMUX4_3", + "CMT_TOP_EE4C1_6", + "CMT_TOP_NW4END3_7", + "CMT_TOP_IMUX13_5", + "CMT_TOP_IMUX46_6", + "CMT_TOP_WW4END0_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LH12_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_CLK1_2", + "CMT_PHASER_IN_DB_RANKSELPHY1", + "CMT_TOP_WW4C2_10", + "CMT_PHASER_OUT_CA_MEMREFCLK", + "CMT_TOP_LOGIC_OUTS_L_B18_10", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_IMUX15_7", + "CMT_TOP_SW4END2_0", + "CMT_TOP_WW4B0_9", + "CMT_TOP_WW4END1_5", + "CMT_TOP_NW4A0_5", + "CMT_TOP_EE2A2_2", + "CMT_TOP_WW4A0_2", + "CMT_TOP_IMUX37_6", + "CMT_TOP_WL1END1_11", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_LH10_11", + "CMT_PHY_CONTROL_PHYCTLWD5", + "CMT_TOP_IMUX0_0", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_NW2A3_4", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_IMUX42_6", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_LH3_1", + "CMT_TOP_EE2BEG3_11", + "CMT_TOP_WL1END3_11", + "CMT_TOP_EE4C0_2", + "CMT_TOP_IMUX23_9", + "CMT_PHY_CONTROL_OBURSTPENDING0", + "CMT_TOP_IMUX35_6", + "CMT_TOP_SE2A3_11", + "CMT_PHASER_IN_DB_ENCALIB0", + "CMT_TOP_FAN3_6", + "CMT_TOP_SW4END2_1", + "CMT_PHASER_OUT_DB_DQSBUS1", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_EE4A2_11", + "CMT_TOP_LOGIC_OUTS_L_B17_9", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_WW2A1_3", + "CMT_TOP_FAN2_5", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_TOP_WW2END1_8", + "CMT_TOP_WR1END2_0", + "CMT_TOP_NE2A1_0", + "CMT_PHASER_OUT_CA_TESTIN1", + "CMT_TOP_LH1_8", + "CMT_TOP_WW2A0_7", + "CMT_TOP_LOGIC_OUTS_L_B17_10", + "CMT_PHASER_OUT_DB_TESTIN5", + "CMT_TOP_EE4BEG1_4", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_EE2BEG2_8", + "CMT_PHY_CONTROL_TESTOUTPUT0", + "CMT_TOP_SW4END0_2", + "CMT_TOP_SW4A0_6", + "CMT_TOP_BYP5_8", + "CMT_TOP_FAN5_4", + "CMT_TOP_IMUX41_7", + "CMT_TOP_IMUX25_2", + "CMT_TOP_EE4A3_1", + "CMT_TOP_IMUX12_8", + "CMT_TOP_WW2A3_3", + "CMT_TOP_IMUX1_6", + "CMT_TOP_IMUX21_2", + "CMT_TOP_CLK1_1", + "CMT_PHASERD_CTSBUS1", + "CMT_TOP_WW4A2_0", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_PHASER_IN_CA_TESTIN4", + "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "CMT_TOP_WW4END3_10", + "CMT_TOP_IMUX16_9", + "CMT_TOP_FAN1_10", + "CMT_PHASER_OUT_DB_TESTIN11", + "CMT_TOP_NE2A2_0", + "CMT_TOP_IMUX17_11", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_WW2END2_7", + "CMT_PHASER_IN_DB_STG1REGL7", + "CMT_TOP_CTRL1_9", + "CMT_PHY_CONTROL_OBURSTPENDING3", + "CMT_TOP_SE4BEG1_1", + "CMT_TOP_NW4END3_5", + "CMT_TOP_IMUX21_5", + "CMT_TOP_WW4END3_4", + "CMT_TOP_WL1END0_8", + "CMT_FREQ_PHASER_REFMUX_1", + "CMT_TOP_SE2A3_0", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_WW2END1_9", + "CMT_TOP_NW4A3_6", + "CMT_PHY_CONTROL_PHYCTLWD18", + "CMT_TOP_SE4C1_7", + "CMT_TOP_WL1END3_10", + "CMT_PHASER_OUT_DB_RDENABLE", + "CMT_TOP_LOGIC_OUTS_L_B9_11", + "CMT_TOP_BYP0_8", + "CMT_TOP_IMUX2_11", + "CMT_TOP_EE4A3_3", + "CMT_TOP_LH10_6", + "CMT_TOP_NW4A3_2", + "CMT_TOP_NE4C0_11", + "CMT_TOP_LH3_4", + "CMT_TOP_LH8_0", + "CMT_TOP_IMUX24_6", + "CMT_TOP_IMUX45_8", + "CMT_TOP_IMUX33_7", + "CMT_TOP_IMUX28_7", + "CMT_TOP_ER1BEG0_10", + "CMT_TOP_FAN0_10", + "CMT_TOP_LH8_9", + "CMT_PHASER_OUT_CA_PHASEREFCLK", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_R_TOP_UPPER_B_CLKPLL4", + "CMT_TOP_WL1END1_9", + "CMT_TOP_EE4B0_5", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX15_10", + "CMT_TOP_CLK0_11", + "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_IMUX3_10", + "CMT_TOP_BYP3_8", + "CMT_TOP_IMUX17_0", + "CMT_TOP_NE2A3_1", + "CMT_PHASER_IN_CA_STG1REGR3", + "CMT_TOP_NW2A3_2", + "CMT_TOP_EE4B3_1", + "CMT_TOP_WW4B3_5", + "CMT_PHASER_OUT_CA_TESTIN2", + "CMT_PHASER_OUT_DB_TESTIN0", + "CMT_TOP_BYP1_9", + "CMT_TOP_SE4C2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_SE2A1_7", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_WL1END3_5", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_IMUX3_1", + "CMT_PHASER_IN_CA_STG1REGR7", + "CMT_TOP_WR1END2_1", + "CMT_TOP_NW4A1_4", + "CMT_TOP_WL1END2_11", + "CMT_TOP_WL1END1_10", + "CMT_TOP_IMUX20_3", + "CMT_TOP_BYP6_8", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX14_2", + "CMT_TOP_BYP4_4", + "CMT_TOP_IMUX2_3", + "CMT_TOP_CLK1_7", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_IMUX46_5", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_IMUX45_11", + "CMT_TOP_NW4END1_3", + "CMT_TOP_NW2A3_5", + "CMT_TOP_WR1END2_3", + "CMT_R_TOP_UPPER_B_CLKIN1", + "CMT_TOP_BYP2_6", + "CMT_TOP_BYP3_3", + "CMT_TOP_FAN6_2", + "CMT_TOP_NW2A2_3", + "CMT_TOP_IMUX40_4", + "CMT_TOP_MONITOR_P_11", + "CMT_TOP_WW4A0_10", + "CMT_TOP_IMUX47_6", + "CMT_TOP_SW4A3_4", + "CMT_TOP_FAN7_0", + "CMT_TOP_WW4A0_11", + "CMT_TOP_LH11_5", + "CMT_TOP_IMUX30_5", + "CMT_TOP_SE2A3_1", + "CMT_TOP_EE4A3_6", + "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "CMT_TOP_IMUX5_1", + "CMT_TOP_EE4BEG3_6", + "CMT_TOP_SE2A2_0", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_EE4B3_4", + "CMT_TOP_EE4C3_6", + "CMT_TOP_EE4C0_11", + "CMT_TOP_WW4B0_0", + "CMT_TOP_IMUX27_2", + "CMT_TOP_FAN0_8", + "CMT_TOP_EE4A2_6", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_FAN2_6", + "CMT_TOP_SE4BEG0_8", + "CMT_TOP_CLK0_9", + "PLL_CLK_FREQBB_REBUFOUT3", + "CMT_TOP_LH1_10", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_PHY_CONTROL_TESTINPUT12", + "CMT_TOP_SW2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_9", + "CMT_TOP_IMUX46_11", + "CMT_TOP_IMUX3_11", + "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_NW4END0_6", + "CMT_TOP_IMUX10_0", + "CMT_PHASER_OUT_DB_TESTIN7", + "CMT_PHY_CONTROL_PHYCTLWD12", + "CMT_TOP_IMUX43_4", + "CMT_PHASER_REF_TESTIN2", + "CMT_TOP_EE4A0_0", + "CMT_TOP_IMUX36_1", + "CMT_TOP_LH1_0", + "CMT_TOP_WW4A3_6", + "CMT_TOP_EE2A1_9", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_LOGIC_OUTS_L_B4_11", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_TOP_WW4A3_2", + "CMT_TOP_WW4B2_9", + "CMT_TOP_BYP0_5", + "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "CMT_TOP_ICLK_2", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_PHY_CONTROL_PHYCTLWD20", + "CMT_PHASER_OUT_DB_BURSTPENDING", + "CMT_TOP_FAN0_11", + "CMT_TOP_NE2A3_5", + "CMT_TOP_EL1BEG3_10", + "CMT_TOP_NE2A1_8", + "CMT_PHASER_IN_CA_RST", + "CMT_TOP_LH12_2", + "CMT_PHY_CONTROL_INRANKA1", + "CMT_PHASER_IN_CA_FINEINC", + "CMT_TOP_WW2A0_10", + "CMT_TOP_EE4C2_5", + "CMT_TOP_IMUX47_10", + "CMT_TOP_IMUX30_9", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_IMUX19_8", + "CMT_TOP_IMUX17_6", + "CMT_TOP_WW2A2_6", + "CMT_TOP_IMUX14_5", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_TOP_IMUX34_2", + "CMT_TOP_BYP1_6", + "CMT_TOP_SW4A2_2", + "CMT_TOP_EE2BEG2_10", + "CMT_TOP_WW4A2_8", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_IMUX39_5", + "CMT_TOP_NW4A2_7", + "CMT_TOP_IMUX38_1", + "CMT_TOP_WW2A0_8", + "CMT_TOP_CTRL1_4", + "CMT_TOP_SE2A0_11", + "CMT_TOP_CTRL0_10", + "CMT_TOP_NE4C2_0", + "CMT_TOP_IMUX8_1", + "CMT_TOP_OCLK_0", + "CMT_TOP_NE4C2_7", + "CMT_TOP_IMUX20_8", + "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "CMT_PHY_CONTROL_IRANKA1", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SE4C3_4", + "CMT_PHY_CONTROL_PHYCTLWD25", + "CMT_TOP_SE4C3_3", + "CMT_TOP_IMUX12_3", + "CMT_TOP_CLK0_5", + "CMT_TOP_WW2END1_4", + "CMT_PHASER_IN_CA_TESTIN11", + "CMT_TOP_NW2A1_5", + "CMT_TOP_IMUX16_2", + "CMT_TOP_MONITOR_N_10", + "CMT_TOP_BYP2_5", + "CMT_TOP_WR1END3_11", + "CMT_TOP_IMUX40_2", + "CMT_TOP_WW4B2_8", + "CMT_PHASER_IN_CA_STG1REGL6", + "CMT_TOP_EE4B1_2", + "CMT_TOP_SE4C1_2", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_SW4A1_9", + "CMT_TOP_FAN0_6", + "CMT_TOP_SW4END2_8", + "CMT_PHY_CONTROL_IRANKC0", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_PHASER_OUT_CA_TESTIN3", + "CMT_TOP_IMUX18_7", + "CMT_TOP_NW4A1_11", + "CMT_TOP_SE4BEG3_2", + "CMT_TOP_EE2BEG1_8", + "CMT_TOP_NE2A2_10", + "CMT_TOP_EE2BEG1_11", + "CMT_PHASER_OUT_CA_COUNTERREADEN", + "CMT_TOP_WW4A2_5", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX44_2", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_CTRL0_0", + "CMT_PHASER_REF_TESTIN7", + "CMT_TOP_IMUX1_8", + "CMT_TOP_IMUX38_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_NW2A1_0", + "CMT_TOP_WW4B3_8", + "CMT_TOP_EE4BEG2_10", + "CMT_PHASER_IN_CA_SCANOUT", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4BEG3_6", + "CMT_PHASER_IN_DB_STG1REGR1", + "CMT_TOP_IMUX38_0", + "CMT_TOP_SW2A2_1", + "CMT_TOP_NE4C2_9", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "CMT_TOP_SE4BEG1_11", + "CMT_TOP_BYP1_3", + "CMT_TOP_CTRL0_6", + "CMT_TOP_EE4A3_10", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_IMUX17_3", + "CMT_TOP_NW2A3_10", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX28_2", + "CMT_TOP_EE2A0_9", + "CMT_TOP_IMUX21_8", + "CMT_PHY_CONTROL_RESET", + "CMT_PHASER_REF_TESTIN0", + "CMT_TOP_EL1BEG3_11", + "CMT_TOP_IMUX42_2", + "CMT_TOP_WW2A3_6", + "CMT_TOP_WW4B0_4", + "CMT_TOP_SE2A2_5", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_TOP_IMUX38_9", + "CMT_TOP_BYP2_10", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EL1BEG0_10", + "CMT_TOP_EE4B1_11", + "CMT_TOP_OCLKDIV_0", + "CMT_PHASER_REF_TESTOUT0", + "CMT_TOP_EE2BEG2_7", + "CMT_PHASER_IN_DB_TESTIN0", + "CMT_TOP_ICLK_0", + "CMT_PHY_CONTROL_PHYCTLWD31", + "CMT_TOP_NW4END1_2", + "CMT_TOP_WW2A2_10", + "CMT_TOP_WW4END1_9", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX31_7", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_NW2A1_3", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX47_2", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_NE2A3_0", + "CMT_TOP_IMUX13_9", + "CMT_TOP_LH10_4", + "CMT_TOP_BYP0_2", + "CMT_TOP_CLK0_3", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_SW4A0_11", + "CMT_TOP_LOGIC_OUTS_L_B13_11", + "CMT_PHASER_IN_DB_SELCALORSTG1", + "CMT_TOP_SW2A2_7", + "CMT_TOP_EL1BEG2_10", + "CMT_TOP_IMUX29_9", + "CMT_PHY_CONTROL_TESTOUTPUT15", + "CMT_PHASER_IN_DB_SCANIN", + "CMT_TOP_EE4B3_9", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_IMUX25_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_ICLK_10", + "CMT_TOP_NE4C1_7", + "CMT_TOP_NW2A2_11", + "CMT_TOP_EE4C3_8", + "CMT_PHY_CONTROL_INRANKB1", + "CMT_TOP_IMUX4_2", + "CMT_TOP_NW4END0_0", + "CMT_PHASER_IN_CA_SYSCLK", + "CMT_TOP_IMUX11_9", + "CMT_TOP_EE4B2_10", + "CMT_TOP_IMUX0_6", + "CMT_PHASER_OUT_DB_DTSBUS1", + "CMT_TOP_WW4B0_1", + "CMT_PHY_CONTROL_REFDLLLOCK", + "CMT_TOP_FAN1_5", + "CMT_TOP_WL1END0_11", + "CMT_TOP_EE2A1_8", + "CMT_PHASER_IN_CA_TESTIN5", + "CMT_TOP_NE4C3_10", + "CMT_PHASER_IN_DB_STG1REGL3", + "CMT_PHY_CONTROL_PHYCTLWD11", + "CMT_PHASER_OUT_DB_DIVIDERST", + "CMT_TOP_OCLK_10", + "CMT_TOP_WW2END2_2", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_FAN4_7", + "CMT_PHASER_OUT_DB_SCANCLK", + "CMT_TOP_IMUX27_11", + "CMT_TOP_IMUX36_6", + "CMT_TOP_WW2END0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_EE4BEG3_11", + "CMT_PHY_CONTROL_ECALIB0", + "CMT_PHASER_OUT_CA_TESTIN5", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_EE4B3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_NW4A0_10", + "CMT_PHASER_IN_CA_STG1REGR5", + "CMT_PHY_CONTROL_TESTOUTPUT10", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_LH8_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_EL1BEG0_8", + "CMT_PHASER_OUT_CA_SCANOUT", + "CMT_TOP_MONITOR_P_10", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_NE4C0_9", + "CMT_PHASER_OUT_CA_RST", + "CMT_TOP_SW4A3_8", + "CMT_TOP_SW2A1_10", + "CMT_TOP_WW2A0_6", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_WL1END2_1", + "CMT_TOP_LH8_10", + "CMT_TOP_NE4C0_0", + "CMT_TOP_IMUX29_7", + "CMT_TOP_EE4B0_4", + "CMT_PHASER_IN_CA_STG1LOAD", + "CMT_TOP_WR1END3_6", + "CMT_TOP_LOGIC_OUTS_L_B6_11", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_PHASER_IN_DB_SCANOUT", + "CMT_TOP_BLOCK_OUTS_L_B3_9", + "CMT_PHY_CONTROL_PHYCTLWD9", + "CMT_TOP_WW4B2_2", + "CMT_PHASER_IN_CA_TESTOUT1", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_LH11_4", + "CMT_TOP_LH6_6", + "CMT_PHASER_IN_DB_TESTIN4", + "CMT_TOP_NE2A1_11", + "CMT_TOP_NW2A3_7", + "CMT_TOP_WW4END0_5", + "CMT_TOP_FAN4_8", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_PHASER_TOP_SYNC_BB", + "CMT_TOP_IMUX22_7", + "CMT_PHY_CONTROL_PHYCTLWD19", + "CMT_PHASER_C_OCLK90_TOIOI", + "CMT_TOP_WR1END1_2", + "CMT_TOP_IMUX2_6", + "CMT_TOP_LOGIC_OUTS_L_B12_9", + "CMT_TOP_BYP4_8", + "CMT_PHASER_UP_PHASERREF_ABOVE0", + "CMT_TOP_SE4C3_5", + "CMT_TOP_BLOCK_OUTS_L_B2_9", + "CMT_TOP_IMUX15_4", + "CMT_TOP_IMUX39_9", + "CMT_PHASER_IN_CA_BURSTPENDING", + "CMT_TOP_IMUX4_9", + "CMT_TOP_BYP5_5", + "CMT_TOP_ICLK_1", + "CMT_TOP_WW2END1_10", + "CMT_TOP_IMUX0_1", + "CMT_TOP_BYP6_7", + "CMT_PHASER_OUT_CA_TESTIN11", + "CMT_TOP_WW4B2_6", + "CMT_TOP_IMUX32_7", + "CMT_TOP_LH3_3", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_SW4A2_8", + "CMT_TOP_WL1END3_7", + "CMT_FREQ_BB_PREF_IN1", + "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "CMT_TOP_SW4A1_7", + "CMT_TOP_SW2A3_5", + "CMT_TOP_EE4C2_9", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_WW4END1_8", + "CMT_TOP_OCLK1X_90_1", + "CMT_PHY_CONTROL_PHYCTLWD4", + "CMT_TOP_SW4A3_3", + "CMT_TOP_FAN1_9", + "CMT_TOP_WW4A2_2", + "CMT_TOP_IMUX28_1", + "CMT_TOP_IMUX46_4", + "CMT_TOP_WW2END3_4", + "CMT_TOP_EE4B1_5", + "CMT_TOP_EE4B0_6", + "CMT_TOP_WR1END0_11", + "CMT_TOP_SW2A0_0", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_PHASER_IN_CA_ICLKDIV", + "CMT_TOP_NW4A1_0", + "CMT_PHY_CONTROL_AUXOUTPUT2", + "CMT_TOP_WW4B0_7", + "CMT_TOP_IMUX33_9", + "CMT_TOP_CLK1_4", + "CMT_TOP_NW4END2_6", + "CMT_TOP_IMUX17_10", + "CMT_TOP_BYP5_0", + "CMT_PHASER_REF_TESTOUT7", + "CMT_TOP_NE4C1_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "CMT_TOP_WW4END1_1", + "CMT_TOP_NW4A2_11", + "CMT_TOP_IMUX37_0", + "CMT_TOP_WL1END3_1", + "CMT_TOP_IMUX16_8", + "CMT_PHASER_OUT_DB_TESTIN15", + "CMT_PHASER_OUT_DB_OSERDESRST", + "CMT_TOP_IMUX39_2", + "CMT_TOP_IMUX37_7", + "CMT_TOP_IMUX16_3", + "CMT_PHY_CONTROL_PLLLOCK", + "CMT_PHASER_IN_DB_STG1LOAD", + "CMT_TOP_IMUX1_2", + "CMT_PHASER_IN_CA_EDGEADV", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_TOP_IMUX6_6", + "CMT_PHASER_OUT_CA_DTSBUS1", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_WW4B2_4", + "CMT_TOP_ER1BEG2_2", + "CMT_PHASER_IN_DB_STG1REGR4", + "CMT_TOP_IMUX11_10", + "CMT_TOP_IMUX17_7", + "CMT_TOP_CTRL0_8", + "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "CMT_PHASER_REF_CLKIN", + "CMT_PHASER_IN_CA_TESTOUT2", + "CMT_TOP_IMUX35_9", + "CMT_PHASER_IN_DB_RSTDQSFIND", + "CMT_TOP_OCLK1X_90_8", + "CMT_PHASER_REF_TESTOUT2", + "CMT_TOP_IMUX29_2", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_ER1BEG0_9", + "CMT_TOP_BYP6_1", + "CMT_TOP_EE4BEG2_2", + "CMT_PHASER_IN_CA_PHASEREFCLK", + "CMT_TOP_FAN1_4", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW2A0_5", + "CMT_TOP_NE2A1_3", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_TOP_NW2A0_3", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_SE2A1_5", + "CMT_TOP_LH4_9", + "CMT_TOP_NW4A1_8", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_NW4END3_2", + "CMT_TOP_IMUX39_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_SW4END1_10", + "CMT_TOP_NW4END0_7", + "CMT_TOP_IMUX44_9", + "CMT_TOP_SW4END0_4", + "CMT_TOP_CTRL1_2", + "CMT_TOP_WW4END2_2", + "CMT_TOP_IMUX38_10", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4C2_10", + "CMT_TOP_IMUX38_2", + "CMT_TOP_BYP3_7", + "CMT_TOP_LH3_0", + "CMT_PHY_CONTROL_INRANKD0", + "CMT_PHASER_REF_CLKOUT", + "CMT_TOP_EE4BEG3_9", + "CMT_TOP_NE4BEG2_6", + "CMT_TOP_ICLK_11", + "CMT_TOP_OCLK_3", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX13_11", + "CMT_TOP_IMUX11_2", + "CMT_TOP_WW4A2_10", + "CMT_TOP_SW4A0_5", + "CMT_TOP_EE4B2_3", + "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "CMT_TOP_IMUX9_7", + "CMT_TOP_EE2A2_3", + "CMT_TOP_WR1END3_1", + "CMT_TOP_WW2A0_0", + "CMT_TOP_WR1END0_5", + "CMT_TOP_ER1BEG2_8", + "CMT_PHASER_REF_PWRDWN", + "CMT_TOP_WW4C3_10", + "CMT_TOP_NW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B6_9", + "CMT_TOP_EE4C0_10", + "CMT_TOP_WW4B2_5", + "CMT_PHY_CONTROL_PHYCTLWD0", + "CMT_TOP_IMUX41_8", + "CMT_TOP_SW2A3_8", + "CMT_TOP_SW4END1_9", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_LH4_10", + "CMT_TOP_NE4BEG0_11", + "CMT_TOP_WW4B3_6", + "CMT_TOP_NW4END3_10", + "CMT_TOP_WW4END3_8", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX33_2", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_WW2END2_8", + "CMT_TOP_WW4C0_11", + "CMT_TOP_NE2A0_7", + "CMT_TOP_SE2A0_10", + "CMT_PHASER_OUT_DB_SYSCLK", + "CMT_TOP_BYP0_7", + "CMT_TOP_IMUX0_11", + "CMT_TOP_NE2A1_7", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_PHY_CONTROL_PHYCLK", + "CMT_TOP_WW2A3_10", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_NW4A3_8", + "CMT_TOP_EE4A1_11", + "CMT_TOP_WW4C0_5", + "CMT_TOP_BYP4_9", + "CMT_TOP_IMUX8_7", + "CMT_TOP_NE2A0_1", + "CMT_TOP_WW4END0_0", + "CMT_TOP_FAN5_2", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_WW4C1_10", + "CMT_TOP_IMUX39_8", + "CMT_TOP_NE4C1_2", + "CMT_TOP_IMUX30_4", + "CMT_PHASER_OUT_C_RDCLK_TOFIFO", + "CMT_PHASER_IN_CA_MEMREFCLK", + "CMT_TOP_EE4C3_4", + "CMT_TOP_BYP1_5", + "CMT_TOP_IMUX10_8", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_TOP_NE2A2_11", + "CMT_TOP_IMUX43_10", + "CMT_TOP_EE4A3_11", + "CMT_PHASER_OUT_CA_TESTIN12", + "CMT_TOP_EE2A2_10", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_IMUX44_8", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_WL1END0_3", + "CMT_TOP_IMUX19_4", + "CMT_TOP_IMUX18_8", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_NE4C2_10", + "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "CMT_TOP_LH10_9", + "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "CMT_TOP_LOGIC_OUTS_L_B10_9", + "CMT_PHASER_IN_C_ICLK", + "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "CMT_TOP_LH7_4", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_NW4A3_5", + "CMT_PHY_CONTROL_PHYCTLWD16", + "CMT_PHASER_IN_CA_ICLK", + "CMT_TOP_NW4END0_3", + "CMT_TOP_IMUX29_4", + "CMT_PHY_CONTROL_PCENABLECALIB0", + "CMT_TOP_NW2A0_6", + "CMT_TOP_SE2A2_2", + "CMT_TOP_WW4C2_7", + "CMT_TOP_IMUX37_9", + "CMT_TOP_WW4C0_4", + "CMT_TOP_BYP5_9", + "CMT_TOP_EE4BEG3_4", + "CMT_PHY_CONTROL_PHYCTLWD28", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "CMT_TOP_WW4A2_1", + "CMT_TOP_LH6_9", + "CMT_TOP_SE4C2_11", + "CMT_TOP_LH10_3", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_WW4C3_2", + "CMT_TOP_IMUX38_5", + "CMT_TOP_IMUX8_8", + "CMT_TOP_FAN4_6", + "CMT_TOP_IMUX47_7", + "CMT_TOP_EE2A1_1", + "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "CMT_PHY_CONTROL_TESTINPUT7", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_ER1BEG1_10", + "CMT_TOP_FAN7_8", + "CMT_TOP_FAN6_3", + "CMT_TOP_EE4B0_0", + "CMT_PHASER_IN_DB_ENCALIB1", + "CMT_TOP_IMUX34_5", + "CMT_TOP_IMUX31_5", + "CMT_TOP_WW4END1_11", + "CMT_TOP_IMUX0_7", + "CMT_TOP_IMUX2_1", + "CMT_TOP_ER1BEG3_8" + ], + "pips": { + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD1->CMT_PHASER_IN_DB_RANKSELPHY1": { + "src_wire": "CMT_PHY_CONTROL_IRANKD1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX11_11->CMT_PHY_CONTROL_RESET": { + "src_wire": "CMT_TOP_IMUX11_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_RESET", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_9->CMT_PHY_CONTROL_PHYCTLWD6": { + "src_wire": "CMT_TOP_IMUX30_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { + "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_3->CMT_PHASER_IN_CA_FINEINC": { + "src_wire": "CMT_TOP_IMUX47_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX3_4->CMT_PHASER_IN_CA_RANKSEL1": { + "src_wire": "CMT_TOP_IMUX3_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_11->CMT_PHY_CONTROL_PHYCTLWD26": { + "src_wire": "CMT_TOP_IMUX45_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD26", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLALMOSTFULL->CMT_TOP_LOGIC_OUTS_L_B7_9": { + "src_wire": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD0->CMT_PHASER_IN_DB_RANKSELPHY0": { + "src_wire": "CMT_PHY_CONTROL_IRANKD0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_1": { + "src_wire": "CMT_FREQ_BB_PREF_IN0", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B3_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B6_6": { + "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_9": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING1->CMT_PHY_CONTROL_OBURSTPENDING1": { + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX8_7->CMT_PHASER_IN_DB_RSTDQSFIND": { + "src_wire": "CMT_TOP_IMUX8_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX32_6->CMT_PHASER_OUT_DB_COARSEENABLE": { + "src_wire": "CMT_TOP_IMUX32_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT2->>CMT_FREQ_BB_PREF_IN2": { + "src_wire": "PLL_CLK_FREQBB_REBUFOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B9_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING0->CMT_PHY_CONTROL_OBURSTPENDING0": { + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_4->CMT_PHASER_IN_CA_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_9->CMT_PHY_CONTROL_PHYCTLWD10": { + "src_wire": "CMT_TOP_IMUX47_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKC0->CMT_PHY_CONTROL_IRANKC0": { + "src_wire": "CMT_PHY_CONTROL_INRANKC0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKC0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_C_OCLK": { + "src_wire": "CMT_PHASER_OUT_CA_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT2->>PLL_CLK_FREQBB_REBUFOUT2": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { + "src_wire": "CMT_TOP_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_11->CMT_PHY_CONTROL_PHYCTLWD30": { + "src_wire": "CMT_TOP_IMUX15_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD30", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKB1->CMT_PHY_CONTROL_IRANKB1": { + "src_wire": "CMT_PHY_CONTROL_INRANKB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKB1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_CA_SYNCIN": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_11->CMT_PHY_CONTROL_PHYCTLWD23": { + "src_wire": "CMT_TOP_IMUX20_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD23", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_0": { + "src_wire": "CMT_FREQ_BB_PREF_IN2", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_2": { + "src_wire": "CMT_FREQ_BB_PREF_IN0", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS0->CMT_PHASERD_DQSBUS0": { + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DQSBUS0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_7": { + "src_wire": "CMT_PHASER_C_OCLK90_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_11": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRCLK_TOFIFO->CMT_PHASER_IN_D_ICLKDIV": { + "src_wire": "CMT_PHASER_IN_D_WRCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_ICLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS0->CMT_PHASERD_CTSBUS0": { + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_CTSBUS0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_11->CMT_PHY_CONTROL_PHYCTLWRENABLE": { + "src_wire": "CMT_TOP_IMUX47_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWRENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX2_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX2_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_0->CMT_PHASER_REF_PWRDWN": { + "src_wire": "CMT_TOP_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_PWRDWN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B15_0": { + "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX13_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_9->CMT_PHY_CONTROL_PHYCTLWD8": { + "src_wire": "CMT_TOP_IMUX15_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { + "src_wire": "CMT_TOP_IMUX15_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_9->CMT_PHY_CONTROL_PHYCTLWD7": { + "src_wire": "CMT_TOP_IMUX46_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { + "src_wire": "CMT_TOP_IMUX0_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASERREF_PHASERIN_D->CMT_PHASER_IN_DB_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_PHASERIN_D", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING0->CMT_PHY_CONTROL_IBURSTPENDING0": { + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_8": { + "src_wire": "CMT_PHASER_IN_DB_DQSFOUND", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_9->CMT_PHY_CONTROL_PLLLOCK": { + "src_wire": "CMT_TOP_IMUX43_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PLLLOCK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX41_4->CMT_PHASER_IN_CA_EDGEADV": { + "src_wire": "CMT_TOP_IMUX41_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX32_4->CMT_PHASER_IN_CA_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX32_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B9_6": { + "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B18_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_9->CMT_PHY_CONTROL_PHYCTLWD2": { + "src_wire": "CMT_TOP_IMUX44_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B7_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKC1->CMT_PHY_CONTROL_IRANKC1": { + "src_wire": "CMT_PHY_CONTROL_INRANKC1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKC1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_C_RCLK2": { + "src_wire": "CMT_PHASER_IN_CA_RCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_RCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX9_6->CMT_PHASER_OUT_DB_EDGEADV": { + "src_wire": "CMT_TOP_IMUX9_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX16_0->CMT_PHASER_UP_BUFMRCE_CE1": { + "src_wire": "CMT_TOP_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX17_6->CMT_PHASER_OUT_DB_ENCALIB0": { + "src_wire": "CMT_TOP_IMUX17_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIB0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX4_9->CMT_PHY_CONTROL_PHYCTLWD0": { + "src_wire": "CMT_TOP_IMUX4_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_TOP_SYNC_BB->>CMT_PHASERTOP_PHYCTLMSTREMPTY": { + "src_wire": "CMT_PHASER_TOP_SYNC_BB", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_1": { + "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS1->CMT_PHASERD_CTSBUS1": { + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_CTSBUS1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { + "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_CA_RCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX34_6->CMT_PHASER_OUT_DB_RST": { + "src_wire": "CMT_TOP_IMUX34_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_REF_CLKIN": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_CLKIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK->>CMT_PHASER_C_OCLK_TOIOI": { + "src_wire": "CMT_PHASER_OUT_C_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT1->>PLL_CLK_FREQBB_REBUFOUT1": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX27_5->CMT_PHASER_OUT_DB_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX27_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_2": { + "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASERREF_PHASEROUT_D->CMT_PHASER_OUT_DB_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_0": { + "src_wire": "CMT_FREQ_BB_PREF_IN1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_10->CMT_PHY_CONTROL_PHYCTLWD13": { + "src_wire": "CMT_TOP_IMUX13_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLKDIV->>CMT_PHASER_C_ICLKDIV_TOIOI": { + "src_wire": "CMT_PHASER_IN_C_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLREADY->CMT_TOP_LOGIC_OUTS_L_B17_8": { + "src_wire": "CMT_PHY_CONTROL_PHYCTLREADY", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX14_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX8_6->CMT_PHASER_OUT_DB_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX8_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC0->CMT_PHASER_IN_CA_RANKSELPHY0": { + "src_wire": "CMT_PHY_CONTROL_IRANKC0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX45_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_1": { + "src_wire": "CMT_FREQ_BB_PREF_IN2", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKD0->CMT_PHY_CONTROL_IRANKD0": { + "src_wire": "CMT_PHY_CONTROL_INRANKD0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKD0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING2->CMT_PHY_CONTROL_IBURSTPENDING2": { + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING2", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_3": { + "src_wire": "CMT_PHASER_IN_CA_ISERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_10->CMT_PHY_CONTROL_PHYCLK": { + "src_wire": "CMT_TOP_CLK0_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90->>CMT_PHASER_C_OCLK90_TOIOI": { + "src_wire": "CMT_PHASER_OUT_C_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_OCLK90_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_11->CMT_PHY_CONTROL_PHYCTLWD21": { + "src_wire": "CMT_TOP_IMUX43_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD21", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_10->CMT_PHY_CONTROL_PHYCTLWD18": { + "src_wire": "CMT_TOP_IMUX15_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD18", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_FINEINC": { + "src_wire": "CMT_TOP_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB0->CMT_PHY_CONTROL_ECALIB0": { + "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX1_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX1_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX44_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_0": { + "src_wire": "CMT_FREQ_BB_PREF_IN0", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKB0->CMT_PHY_CONTROL_IRANKB0": { + "src_wire": "CMT_PHY_CONTROL_INRANKB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKB0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_9->CMT_PHY_CONTROL_PHYCTLWD3": { + "src_wire": "CMT_TOP_IMUX13_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLFULL->CMT_TOP_LOGIC_OUTS_L_B17_9": { + "src_wire": "CMT_PHY_CONTROL_PHYCTLFULL", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_10->CMT_PHY_CONTROL_PHYCTLWD20": { + "src_wire": "CMT_TOP_IMUX47_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD20", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX44_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_9->CMT_PHY_CONTROL_PHYCTLWD4": { + "src_wire": "CMT_TOP_IMUX45_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_10->CMT_PHY_CONTROL_PHYCTLWD16": { + "src_wire": "CMT_TOP_IMUX30_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD16", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX9_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX9_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { + "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_DB_RCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX27_7->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX27_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_C_WRENABLE_FIFO": { + "src_wire": "CMT_PHASER_IN_CA_WRENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_WRENABLE_FIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B21_3": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_7->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX43_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING3->CMT_PHY_CONTROL_IBURSTPENDING3": { + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING3", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS1->CMT_PHASERD_DTSBUS1": { + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DTSBUS1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX3_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { + "src_wire": "CMT_TOP_IMUX3_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_D_RCLK3": { + "src_wire": "CMT_PHASER_IN_DB_RCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_RCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_0": { + "src_wire": "CMT_FREQ_BB_PREF_IN3", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_10->CMT_PHY_CONTROL_PHYCTLWD12": { + "src_wire": "CMT_TOP_IMUX44_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV->>CMT_PHASER_C_OCLKDIV_TOIOI": { + "src_wire": "CMT_PHASER_OUT_C_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { + "src_wire": "CMT_TOP_IMUX41_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_9": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB1->CMT_PHY_CONTROL_ECALIB1": { + "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY->CMT_PHY_CONTROL_PHYCTLMSTREMPTY": { + "src_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLK->>CMT_PHASER_C_ICLK_TOIOI": { + "src_wire": "CMT_PHASER_IN_C_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLEMPTY->CMT_PHASERTOP_PHYCTLEMPTY": { + "src_wire": "CMT_PHY_CONTROL_PHYCTLEMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERTOP_PHYCTLEMPTY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { + "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B16_5": { + "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX41_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX41_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_2->CMT_PHASER_OUT_CA_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX34_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { + "src_wire": "CMT_TOP_IMUX34_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_11->CMT_PHY_CONTROL_PHYCTLWD29": { + "src_wire": "CMT_TOP_IMUX46_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD29", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_6->CMT_PHASER_IN_DB_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX19_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>CMT_FREQ_PHASER_REFMUX_0": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_8": { + "src_wire": "CMT_PHASER_IN_DB_ISERDESRST", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B15_3": { + "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKA1->CMT_PHY_CONTROL_IRANKA1": { + "src_wire": "CMT_PHY_CONTROL_INRANKA1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKA1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX4_10->CMT_PHY_CONTROL_REFDLLLOCK": { + "src_wire": "CMT_TOP_IMUX4_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_REFDLLLOCK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT0->>CMT_FREQ_BB_PREF_IN0": { + "src_wire": "PLL_CLK_FREQBB_REBUFOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_REF_TMUXOUT->CMT_PHASER_REF_TMUXOUT_TOHCLK": { + "src_wire": "CMT_PHASER_REF_TMUXOUT", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_TMUXOUT_TOHCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B1_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_D_OCLK": { + "src_wire": "CMT_PHASER_OUT_DB_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_1": { + "src_wire": "CMT_FREQ_BB_PREF_IN3", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_C_RDCLK_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_RDCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { + "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT3->CMT_TOP_LOGIC_OUTS_L_B17_11": { + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT3->>CMT_FREQ_BB_PREF_IN3": { + "src_wire": "PLL_CLK_FREQBB_REBUFOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX37_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { + "src_wire": "CMT_TOP_IMUX37_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHY_CONTROL_SYNCIN": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>CMT_FREQ_PHASER_REFMUX_2": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX18_2->CMT_PHASER_OUT_CA_ENCALIB0": { + "src_wire": "CMT_TOP_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIB0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_2": { + "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>CMT_FREQ_PHASER_REFMUX_1": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_10->CMT_PHY_CONTROL_PHYCTLWD14": { + "src_wire": "CMT_TOP_IMUX45_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { + "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_11->CMT_PHY_CONTROL_PHYCTLWD27": { + "src_wire": "CMT_TOP_IMUX14_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD27", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_D->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_D", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_C_ICLK": { + "src_wire": "CMT_PHASER_IN_CA_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_ICLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_11->CMT_PHY_CONTROL_PHYCTLWD24": { + "src_wire": "CMT_TOP_IMUX44_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD24", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_10->CMT_PHY_CONTROL_PHYCTLWD11": { + "src_wire": "CMT_TOP_IMUX20_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDCLK_TOFIFO->CMT_PHASER_OUT_D_OCLKDIV": { + "src_wire": "CMT_PHASER_OUT_D_RDCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_OCLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT0->>PLL_CLK_FREQBB_REBUFOUT0": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX12_7->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX12_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC1->CMT_PHASER_IN_CA_RANKSELPHY1": { + "src_wire": "CMT_PHY_CONTROL_IRANKC1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX17_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX17_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_RANKSEL0": { + "src_wire": "CMT_TOP_IMUX34_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_C->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_C", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX18_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX18_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_REF_CLKOUT->CMT_PHASER_REF_CLKOUT_TOHCLK": { + "src_wire": "CMT_PHASER_REF_CLKOUT", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_CLKOUT_TOHCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX14_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKD1->CMT_PHY_CONTROL_IRANKD1": { + "src_wire": "CMT_PHY_CONTROL_INRANKD1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKD1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { + "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX23_7->CMT_PHASER_IN_DB_RANKSEL1": { + "src_wire": "CMT_TOP_IMUX23_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_D_WRENABLE_FIFO": { + "src_wire": "CMT_PHASER_IN_DB_WRENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_WRENABLE_FIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_0->>CMT_R_TOP_UPPER_B_CLKINT_2": { + "src_wire": "CMT_TOP_CLK0_0", + "is_pseudo": "0", + "dst_wire": "CMT_R_TOP_UPPER_B_CLKINT_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { + "src_wire": "CMT_TOP_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B3_3": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { + "src_wire": "CMT_TOP_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { + "src_wire": "CMT_TOP_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_9->CMT_PHY_CONTROL_PHYCTLWD1": { + "src_wire": "CMT_TOP_IMUX20_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_DB_SYNCIN": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_10->CMT_PHY_CONTROL_PHYCTLWD15": { + "src_wire": "CMT_TOP_IMUX14_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS0->CMT_PHASERD_DTSBUS0": { + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DTSBUS0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY->>CMT_PHASER_TOP_SYNC_BB": { + "src_wire": "CMT_PHASERTOP_PHYCTLEMPTY", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_TOP_SYNC_BB", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_10->CMT_PHY_CONTROL_PHYCTLWD17": { + "src_wire": "CMT_TOP_IMUX46_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD17", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_OCLKDIV->CMT_PHASER_OUT_D_RDCLK_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_RDCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING3->CMT_PHY_CONTROL_OBURSTPENDING3": { + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING3", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING2->CMT_PHY_CONTROL_OBURSTPENDING2": { + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING2", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_10": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_DB_SYNCIN": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_11": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_2": { + "src_wire": "CMT_FREQ_BB_PREF_IN2", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX28_7->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { + "src_wire": "CMT_TOP_IMUX28_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT0->CMT_TOP_LOGIC_OUTS_L_B3_9": { + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_D_ICLK": { + "src_wire": "CMT_PHASER_IN_DB_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_ICLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_6": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B6_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT2->CMT_TOP_LOGIC_OUTS_L_B17_10": { + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT3->>PLL_CLK_FREQBB_REBUFOUT3": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { + "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B23_2": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_11->CMT_PHY_CONTROL_PHYCTLWD25": { + "src_wire": "CMT_TOP_IMUX13_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD25", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASERREF_PHASERIN_C->CMT_PHASER_IN_CA_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_PHASERIN_C", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B15_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_4->CMT_PHASER_OUT_DB_DIVIDERST": { + "src_wire": "CMT_TOP_IMUX19_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_CA_SYNCIN": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYNCIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_C_OCLK1X_90": { + "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_OCLK1X_90", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT1->>CMT_FREQ_BB_PREF_IN1": { + "src_wire": "PLL_CLK_FREQBB_REBUFOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_9->CMT_PHY_CONTROL_PHYCTLWD9": { + "src_wire": "CMT_TOP_IMUX31_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_2": { + "src_wire": "CMT_FREQ_BB_PREF_IN3", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_FINEINC": { + "src_wire": "CMT_TOP_IMUX30_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_11->CMT_PHY_CONTROL_PHYCTLWD31": { + "src_wire": "CMT_TOP_IMUX31_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD31", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX4_11->CMT_PHY_CONTROL_PHYCTLWD22": { + "src_wire": "CMT_TOP_IMUX4_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD22", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_10": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX11_5->CMT_PHASER_OUT_DB_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX11_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX22_10->CMT_PHY_CONTROL_WRITECALIBENABLE": { + "src_wire": "CMT_TOP_IMUX22_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_WRITECALIBENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS1->CMT_PHASERD_DQSBUS1": { + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DQSBUS1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_1": { + "src_wire": "CMT_FREQ_BB_PREF_IN1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { + "src_wire": "CMT_TOP_IMUX19_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { + "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B21_1": { + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_4": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_RDENABLE->CMT_PHASER_OUT_D_RDENABLE_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_DB_RDENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_RDENABLE_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKA0->CMT_PHY_CONTROL_IRANKA0": { + "src_wire": "CMT_PHY_CONTROL_INRANKA0", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKA0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHY_CONTROL_MEMREFCLK": { + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_MEMREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_0->CMT_PHASER_UP_BUFMRCE_CE0": { + "src_wire": "CMT_TOP_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { + "src_wire": "CMT_TOP_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASERREF_PHASEROUT_C->CMT_PHASER_OUT_CA_PHASEREFCLK": { + "src_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_3->CMT_PHASER_IN_CA_RSTDQSFIND": { + "src_wire": "CMT_TOP_IMUX0_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_0->CMT_PHASER_REF_RST": { + "src_wire": "CMT_TOP_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": { + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_REF_LOCKED->CMT_TOP_LOGIC_OUTS_L_B14_0": { + "src_wire": "CMT_PHASER_REF_LOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDCLK_TOFIFO->CMT_PHASER_OUT_C_OCLKDIV": { + "src_wire": "CMT_PHASER_OUT_C_RDCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_OCLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_7": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { + "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX29_10->CMT_PHY_CONTROL_READCALIBENABLE": { + "src_wire": "CMT_TOP_IMUX29_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_READCALIBENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B6_3": { + "src_wire": "CMT_PHASER_IN_CA_DQSFOUND", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT1->CMT_TOP_LOGIC_OUTS_L_B21_9": { + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX17_2->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { + "src_wire": "CMT_TOP_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_6": { + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRCLK_TOFIFO->CMT_PHASER_IN_C_ICLKDIV": { + "src_wire": "CMT_PHASER_IN_C_WRCLK_TOFIFO", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_ICLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX11_4->CMT_PHASER_IN_CA_RST": { + "src_wire": "CMT_TOP_IMUX11_4", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ICLKDIV->CMT_PHASER_IN_C_WRCLK_TOFIFO": { + "src_wire": "CMT_PHASER_IN_CA_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_WRCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_D_OCLK1X_90": { + "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_OCLK1X_90", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK1_0->>CMT_R_TOP_UPPER_B_CLKINT_3": { + "src_wire": "CMT_TOP_CLK1_0", + "is_pseudo": "0", + "dst_wire": "CMT_R_TOP_UPPER_B_CLKINT_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING1->CMT_PHY_CONTROL_IBURSTPENDING1": { + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_C": { + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX16_6->CMT_PHASER_OUT_DB_COARSEINC": { + "src_wire": "CMT_TOP_IMUX16_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_10->CMT_PHY_CONTROL_PHYCTLWD19": { + "src_wire": "CMT_TOP_IMUX31_10", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD19", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_2": { + "src_wire": "CMT_FREQ_BB_PREF_IN1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_C_RDENABLE_TOFIFO": { + "src_wire": "CMT_PHASER_OUT_CA_RDENABLE", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_RDENABLE_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_9->CMT_PHY_CONTROL_PHYCTLWD5": { + "src_wire": "CMT_TOP_IMUX14_9", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { + "src_wire": "CMT_TOP_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { + "src_wire": "CMT_TOP_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { + "src_wire": "CMT_TOP_IMUX14_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { + "src_wire": "CMT_TOP_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX23_3->CMT_PHASER_IN_CA_COUNTERREADEN": { + "src_wire": "CMT_TOP_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_8->CMT_PHASER_IN_DB_SYSCLK": { + "src_wire": "CMT_TOP_CLK0_8", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { + "src_wire": "CMT_TOP_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { + "src_wire": "CMT_TOP_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_6->CMT_PHASER_IN_DB_FINEENABLE": { + "src_wire": "CMT_TOP_IMUX46_6", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { + "src_wire": "CMT_TOP_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_D": { + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_11->CMT_PHY_CONTROL_PHYCTLWD28": { + "src_wire": "CMT_TOP_IMUX30_11", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD28", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_5->CMT_PHASER_OUT_DB_FINEINC": { + "src_wire": "CMT_TOP_IMUX43_5", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX39_7->CMT_PHASER_IN_DB_RST": { + "src_wire": "CMT_TOP_IMUX39_7", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_D_WRCLK_TOFIFO": { + "src_wire": "CMT_PHASER_IN_DB_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_WRCLK_TOFIFO", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_CMT_TOP_R_UPPER_T.json b/kintex7/tile_type_CMT_TOP_R_UPPER_T.json new file mode 100644 index 0000000..ceb3ea1 --- /dev/null +++ b/kintex7/tile_type_CMT_TOP_R_UPPER_T.json @@ -0,0 +1,4422 @@ +{ + "tile_type": "CMT_TOP_R_UPPER_T", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "PLLE2_ADV", + "type": "PLLE2_ADV", + "site_pins": { + "TESTIN23": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", + "TESTIN25": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", + "DO4": "CMT_TOP_R_UPPER_T_PLLE2_DO4", + "LOCKED": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", + "DEN": "CMT_TOP_R_UPPER_T_PLLE2_DEN", + "TESTIN16": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", + "TESTOUT0": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", + "TESTOUT9": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", + "TESTOUT28": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", + "TESTIN27": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", + "TESTOUT24": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", + "CLKOUT0": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "TESTIN17": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", + "TESTOUT12": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", + "DI15": "CMT_TOP_R_UPPER_T_PLLE2_DI15", + "TESTOUT2": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", + "TESTIN13": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", + "DI12": "CMT_TOP_R_UPPER_T_PLLE2_DI12", + "DO15": "CMT_TOP_R_UPPER_T_PLLE2_DO15", + "TESTOUT59": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", + "DI2": "CMT_TOP_R_UPPER_T_PLLE2_DI2", + "DO3": "CMT_TOP_R_UPPER_T_PLLE2_DO3", + "TESTIN29": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", + "CLKFBOUT": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "TESTOUT8": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", + "DI11": "CMT_TOP_R_UPPER_T_PLLE2_DI11", + "TESTIN14": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", + "TESTOUT11": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", + "TESTOUT25": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", + "TESTOUT56": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", + "CLKIN2": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "DO10": "CMT_TOP_R_UPPER_T_PLLE2_DO10", + "TESTOUT6": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", + "DO11": "CMT_TOP_R_UPPER_T_PLLE2_DO11", + "DO0": "CMT_TOP_R_UPPER_T_PLLE2_DO0", + "TESTOUT27": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", + "DI6": "CMT_TOP_R_UPPER_T_PLLE2_DI6", + "CLKOUT5": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", + "DI8": "CMT_TOP_R_UPPER_T_PLLE2_DI8", + "DADDR0": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", + "TESTOUT5": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", + "TMUXOUT": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", + "DI3": "CMT_TOP_R_UPPER_T_PLLE2_DI3", + "TESTOUT30": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", + "TESTOUT4": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", + "TESTIN31": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", + "TESTOUT34": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", + "DADDR3": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", + "PWRDWN": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", + "TESTOUT14": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", + "TESTIN9": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", + "TESTOUT63": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", + "TESTOUT43": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", + "TESTOUT15": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", + "TESTOUT23": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", + "TESTOUT61": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", + "DI0": "CMT_TOP_R_UPPER_T_PLLE2_DI0", + "CLKOUT4": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", + "DI9": "CMT_TOP_R_UPPER_T_PLLE2_DI9", + "CLKOUT2": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "TESTOUT60": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", + "DO5": "CMT_TOP_R_UPPER_T_PLLE2_DO5", + "DADDR6": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", + "TESTOUT18": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", + "TESTOUT29": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", + "TESTOUT26": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", + "DO8": "CMT_TOP_R_UPPER_T_PLLE2_DO8", + "TESTIN30": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", + "TESTOUT32": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", + "TESTIN18": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", + "TESTOUT54": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", + "DADDR1": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", + "TESTOUT46": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", + "DADDR2": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", + "TESTIN7": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", + "RST": "CMT_TOP_R_UPPER_T_PLLE2_RST", + "TESTIN8": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", + "TESTOUT48": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", + "DRDY": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", + "DWE": "CMT_TOP_R_UPPER_T_PLLE2_DWE", + "CLKOUT1": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "TESTIN3": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", + "DI14": "CMT_TOP_R_UPPER_T_PLLE2_DI14", + "TESTOUT49": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", + "TESTIN26": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", + "TESTOUT52": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", + "TESTOUT50": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", + "DO6": "CMT_TOP_R_UPPER_T_PLLE2_DO6", + "TESTIN15": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", + "TESTIN19": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", + "TESTIN4": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", + "TESTIN11": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", + "DADDR5": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", + "TESTIN20": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", + "DI4": "CMT_TOP_R_UPPER_T_PLLE2_DI4", + "DO9": "CMT_TOP_R_UPPER_T_PLLE2_DO9", + "TESTOUT17": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", + "TESTOUT21": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", + "TESTOUT10": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", + "TESTIN28": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", + "TESTIN6": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", + "TESTOUT53": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", + "TESTOUT55": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", + "TESTOUT19": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", + "CLKIN1": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "TESTIN10": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", + "TESTOUT22": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", + "DCLK": "CMT_TOP_R_UPPER_T_PLLE2_DCLK", + "DI7": "CMT_TOP_R_UPPER_T_PLLE2_DI7", + "TESTOUT57": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", + "TESTOUT44": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", + "CLKINSEL": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", + "CLKFBIN": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "TESTOUT20": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", + "TESTOUT45": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", + "TESTIN2": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", + "TESTOUT51": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", + "TESTOUT40": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", + "TESTIN24": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", + "TESTOUT58": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", + "TESTOUT16": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", + "DO14": "CMT_TOP_R_UPPER_T_PLLE2_DO14", + "DO12": "CMT_TOP_R_UPPER_T_PLLE2_DO12", + "DI13": "CMT_TOP_R_UPPER_T_PLLE2_DI13", + "TESTOUT41": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", + "DO13": "CMT_TOP_R_UPPER_T_PLLE2_DO13", + "DO1": "CMT_TOP_R_UPPER_T_PLLE2_DO1", + "CLKOUT3": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "TESTOUT38": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", + "DI1": "CMT_TOP_R_UPPER_T_PLLE2_DI1", + "TESTOUT42": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", + "TESTOUT47": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", + "TESTIN5": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", + "TESTIN22": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", + "TESTOUT3": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", + "TESTOUT36": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", + "TESTIN0": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", + "TESTOUT7": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", + "TESTIN1": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", + "TESTOUT33": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", + "DADDR4": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", + "DO2": "CMT_TOP_R_UPPER_T_PLLE2_DO2", + "TESTOUT13": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", + "DO7": "CMT_TOP_R_UPPER_T_PLLE2_DO7", + "DI10": "CMT_TOP_R_UPPER_T_PLLE2_DI10", + "TESTOUT1": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", + "TESTIN12": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", + "TESTOUT37": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", + "DI5": "CMT_TOP_R_UPPER_T_PLLE2_DI5", + "TESTOUT62": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", + "TESTIN21": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", + "TESTOUT31": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", + "TESTOUT39": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", + "TESTOUT35": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35" + }, + "x_coord": 0 + } + ], + "wires": [ + "CMT_TOP_WR1END2_7", + "CMT_TOP_WW4C3_6", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_IMUX18_1", + "CMT_TOP_WL1END3_8", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX8_5", + "CMT_TOP_WW2END3_7", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_EE4B0_9", + "CMT_TOP_IMUX15_8", + "CMT_TOP_LH5_7", + "CMT_TOP_LOGIC_OUTS_L_B12_11", + "CMT_TOP_SE4C2_0", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_FAN2_3", + "CMT_TOP_IMUX40_8", + "CMT_TOP_EE4C2_7", + "CMT_TOP_SE4BEG0_10", + "CMT_TOP_NW2A1_4", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_EE2A1_6", + "CMT_TOP_EE4A2_4", + "CMT_TOP_BYP1_4", + "CMT_TOP_EE4C0_3", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_SE4C1_4", + "CMT_TOP_IMUX23_5", + "CMT_TOP_BYP6_12", + "CMT_TOP_R_UPPER_T_FREQ_BB3", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_IMUX34_7", + "CMT_TOP_IMUX25_10", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN5_3", + "CMT_TOP_NE4C2_2", + "CMT_TOP_EE4A2_5", + "CMT_TOP_IMUX35_5", + "CMT_TOP_EE2A0_1", + "CMT_TOP_SE4BEG3_10", + "CMT_TOP_IMUX40_12", + "CMT_TOP_FAN3_2", + "CMT_TOP_BYP2_11", + "CMT_TOP_EE2A2_1", + "CMT_TOP_SW4END2_10", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE2A2_5", + "CMT_TOP_WW2END0_3", + "CMT_TOP_SW4END3_9", + "CMT_TOP_IMUX16_11", + "CMT_TOP_ER1BEG1_0", + "CMT_TOP_SE2A2_10", + "CMT_TOP_SE4C0_2", + "CMT_TOP_R_UPPER_T_PLLE2_DO1", + "CMT_TOP_EE4B3_8", + "CMT_TOP_NW4A3_9", + "CMT_TOP_EE4A1_2", + "CMT_TOP_IMUX31_4", + "CMT_TOP_NW4A3_12", + "CMT_TOP_EL1BEG3_5", + "CMT_TOP_SE4C3_11", + "CMT_TOP_NW4A3_4", + "CMT_TOP_WW4END1_2", + "CMT_TOP_WW4B1_5", + "CMT_TOP_LOGIC_OUTS_L_B2_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", + "CMT_TOP_IMUX12_5", + "CMT_TOP_IMUX8_10", + "CMT_TOP_NW4A1_12", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_EE4A0_6", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_NE4C3_9", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_WR1END0_2", + "CMT_TOP_SW4A0_12", + "CMT_TOP_SW2A0_11", + "CMT_TOP_NW4END1_8", + "CMT_TOP_SE2A0_8", + "CMT_TOP_LH11_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", + "CMT_TOP_EE4C3_2", + "CMT_TOP_IMUX2_7", + "CMT_TOP_LOGIC_OUTS_L_B7_11", + "CMT_TOP_EE2A1_7", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_R_UPPER_T_CLKPLL1", + "CMT_TOP_ER1BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX16_6", + "CMT_TOP_LH6_2", + "CMT_TOP_NE4BEG1_9", + "CMT_PHASER_D_ICLKDIV_TOIOI", + "CMT_TOP_IMUX9_2", + "CMT_TOP_BYP5_1", + "CMT_TOP_OCLKDIV_12", + "CMT_TOP_WR1END1_7", + "CMT_TOP_WL1END1_1", + "CMT_TOP_EE2A3_11", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_EE4A0_11", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX23_8", + "CMT_TOP_IMUX11_12", + "CMT_TOP_LOGIC_OUTS_L_B19_9", + "CMT_TOP_EE4C3_11", + "CMT_TOP_SW4END2_11", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_WW4B1_11", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_WW4A2_11", + "CMT_TOP_NW4END3_0", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", + "CMT_TOP_SE4BEG0_6", + "CMT_TOP_IMUX7_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_SE4C2_12", + "CMT_TOP_SW2A3_2", + "CMT_TOP_WW4C1_4", + "CMT_TOP_NE2A2_5", + "CMT_TOP_SE4C3_9", + "CMT_TOP_IMUX9_12", + "CMT_TOP_IMUX3_7", + "CMT_TOP_WW4A0_8", + "CMT_TOP_NW4END0_5", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_TOP_FAN5_1", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_SE4BEG2_10", + "CMT_TOP_IMUX9_9", + "CMT_TOP_EE2A2_12", + "CMT_TOP_IMUX31_9", + "CMT_TOP_FAN1_6", + "CMT_TOP_IMUX26_4", + "CMT_TOP_IMUX31_12", + "CMT_PLL_PHASER_WRENABLE_TOFIFO", + "CMT_TOP_IMUX3_2", + "CMT_TOP_LH9_11", + "CMT_PLL_PHASERD_CTSBUS0", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_LH4_2", + "CMT_TOP_EE4A1_8", + "CMT_TOP_WW4END1_7", + "CMT_TOP_IMUX35_10", + "CMT_TOP_IMUX44_5", + "CMT_TOP_IMUX37_4", + "CMT_TOP_WW4C2_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", + "CMT_TOP_NW4A0_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", + "CMT_TOP_R_UPPER_T_PLLE2_DI6", + "CMT_TOP_EE4A0_8", + "CMT_TOP_FAN1_12", + "CMT_TOP_WW4B3_1", + "CMT_TOP_EE4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_PHASER_D_OCLK90_TOIOI", + "CMT_TOP_IMUX23_12", + "CMT_TOP_LOGIC_OUTS_L_B15_9", + "CMT_TOP_NE4BEG2_11", + "CMT_TOP_EE2BEG1_12", + "CMT_TOP_IMUX6_12", + "CMT_TOP_WW2END1_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", + "CMT_TOP_IMUX22_9", + "CMT_TOP_FAN3_11", + "CMT_TOP_IMUX13_3", + "CMT_PLL_PHASERD_DQSBUS0", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", + "CMT_TOP_WW4END1_4", + "CMT_TOP_IMUX14_11", + "CMT_TOP_EE4BEG0_9", + "CMT_TOP_WR1END0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_12", + "CMT_TOP_EE4C1_5", + "CMT_TOP_LH9_1", + "CMT_TOP_LH11_10", + "CMT_TOP_FAN6_12", + "CMT_TOP_SE2A1_3", + "CMT_TOP_SE2A0_1", + "PLL_CLK_FREQ_BB_BUFOUT_NS3", + "CMT_TOP_SE4C0_10", + "CMT_TOP_LH12_3", + "CMT_TOP_CLK1_12", + "CMT_TOP_ER1BEG3_11", + "CMT_TOP_FAN7_4", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END2_5", + "CMT_TOP_EE4B2_12", + "CMT_TOP_WR1END2_9", + "CMT_TOP_FAN1_0", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_IMUX40_7", + "CMT_TOP_BYP7_8", + "CMT_TOP_NW4A3_0", + "CMT_TOP_WL1END2_4", + "CMT_TOP_IMUX0_5", + "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_SW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_EE2A3_3", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW2A0_2", + "CMT_TOP_SW4END1_2", + "CMT_TOP_EE2A3_5", + "CMT_TOP_WR1END0_1", + "CMT_TOP_WW4C1_3", + "CMT_TOP_LH4_3", + "CMT_TOP_EE4B2_8", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_IMUX5_2", + "CMT_TOP_EE2BEG1_6", + "CMT_TOP_EE4BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NW4A0_6", + "CMT_TOP_IMUX2_12", + "CMT_TOP_WL1END3_12", + "CMT_TOP_EE2A1_10", + "CMT_TOP_EE4A3_5", + "CMT_TOP_LOGIC_OUTS_L_B8_10", + "CMT_TOP_IMUX14_0", + "CMT_TOP_LH7_5", + "CMT_TOP_WW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_TOP_WW2END2_3", + "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WW2END3_8", + "CMT_TOP_NW4END1_0", + "CMT_TOP_NE4C2_5", + "CMT_TOP_SE2A2_11", + "CMT_TOP_IMUX14_4", + "CMT_TOP_IMUX12_4", + "CMT_TOP_SW4END3_2", + "CMT_TOP_IMUX32_0", + "CMT_TOP_SW4END3_12", + "CMT_TOP_SE4BEG0_1", + "CMT_TOP_IMUX44_6", + "CMT_TOP_IMUX40_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", + "CMT_TOP_SE2A3_3", + "CMT_TOP_SE4BEG3_12", + "CMT_TOP_ER1BEG0_11", + "CMT_TOP_FAN0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_R_UPPER_T_PLLE2_DEN", + "CMT_TOP_NE2A3_10", + "CMT_TOP_WW4B3_2", + "CMT_TOP_LOGIC_OUTS_L_B3_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", + "CMT_TOP_FAN0_7", + "CMT_TOP_WW4B0_3", + "CMT_TOP_R_UPPER_T_PLLE2_DO13", + "CMT_TOP_LH11_8", + "CMT_TOP_R_UPPER_T_CLKIN1", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_TOP_IMUX47_4", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_EE4A0_10", + "CMT_TOP_WW4C1_6", + "CMT_TOP_IMUX35_11", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_NW2A1_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", + "CMT_TOP_IMUX46_9", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_SW4END3_7", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_NW4END3_6", + "CMT_TOP_EE2BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_EE4B0_12", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_TOP_ER1BEG1_11", + "CMT_TOP_IMUX45_6", + "CMT_TOP_WW4END2_8", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_WW4END1_0", + "CMT_TOP_LH3_2", + "CMT_TOP_IMUX1_9", + "CMT_TOP_IMUX8_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_IMUX2_8", + "CMT_TOP_WW2A1_12", + "CMT_TOP_OCLK_5", + "CMT_TOP_BYP0_3", + "CMT_TOP_NE4C0_10", + "CMT_TOP_WW2A2_2", + "CMT_TOP_IMUX20_7", + "CMT_TOP_IMUX25_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", + "CMT_TOP_NW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_WW4C0_3", + "CMT_TOP_IMUX28_5", + "CMT_TOP_NE2A0_2", + "CMT_TOP_WL1END2_12", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_EE4A3_12", + "CMT_TOP_BYP1_1", + "CMT_TOP_SE2A3_6", + "CMT_TOP_SW4A1_11", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX2_2", + "CMT_TOP_R_UPPER_T_PLLE2_DO11", + "CMT_TOP_IMUX21_0", + "CMT_TOP_WW4END2_9", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_SE2A0_2", + "CMT_TOP_IMUX43_1", + "CMT_TOP_EE2BEG2_12", + "CMT_TOP_BYP4_12", + "CMT_PLL_PHASERREF1", + "CMT_TOP_EE4BEG1_6", + "PLL_CLK_FREQ_BB0_NS", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_TOP_IMUX28_8", + "CMT_TOP_WW4C3_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", + "CMT_TOP_SW4END0_9", + "CMT_TOP_LH8_1", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_NE2A0_11", + "CMT_TOP_WW2A3_2", + "CMT_TOP_NW4A0_7", + "CMT_TOP_LH9_5", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_IMUX6_7", + "CMT_TOP_IMUX45_10", + "CMT_TOP_WR1END3_4", + "CMT_TOP_EE2A0_6", + "CMT_TOP_EE2BEG0_9", + "CMT_TOP_EE2A2_6", + "CMT_TOP_BYP2_2", + "CMT_TOP_LOGIC_OUTS_L_B0_11", + "CMT_TOP_IMUX21_6", + "CMT_TOP_SE4C3_1", + "CMT_TOP_SW2A2_3", + "CMT_TOP_IMUX19_7", + "CMT_TOP_IMUX0_4", + "CMT_TOP_ICLK_9", + "CMT_TOP_SW4END2_7", + "CMT_TOP_WW4B3_9", + "CMT_TOP_IMUX15_0", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_R_UPPER_T_CLKFBIN", + "CMT_TOP_IMUX33_12", + "CMT_TOP_EL1BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_WW4END2_5", + "CMT_TOP_WW2A1_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_IMUX9_8", + "CMT_TOP_WW2A1_9", + "CMT_TOP_SW4A0_4", + "CMT_TOP_BYP0_11", + "CMT_TOP_FAN1_8", + "CMT_TOP_IMUX34_4", + "CMT_TOP_IMUX12_9", + "CMT_TOP_SW4A1_10", + "CMT_TOP_SW4END1_12", + "CMT_TOP_WW4A2_12", + "CMT_TOP_NW4A0_11", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4B0_2", + "CMT_TOP_LH2_2", + "CMT_TOP_IMUX10_7", + "CMT_TOP_IMUX39_0", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_WW4END0_10", + "CMT_TOP_IMUX30_10", + "CMT_TOP_NW2A0_9", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_TOP_SW4A3_5", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_IMUX14_1", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_WL1END0_10", + "CMT_TOP_IMUX26_1", + "CMT_TOP_CTRL0_9", + "CMT_TOP_WL1END0_1", + "CMT_TOP_LH11_6", + "CMT_TOP_NE4C3_8", + "CMT_TOP_IMUX46_12", + "CMT_TOP_WL1END0_7", + "CMT_TOP_LH12_4", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_NE4C3_4", + "CMT_TOP_ER1BEG0_7", + "CMT_TOP_WW2END2_4", + "CMT_TOP_SW4END1_8", + "CMT_TOP_SE4C2_6", + "CMT_TOP_IMUX26_12", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_SW2A1_1", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_WW4END3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_9", + "CMT_TOP_WL1END2_6", + "CMT_TOP_IMUX43_6", + "CMT_TOP_NW4A1_1", + "CMT_TOP_SE4C1_8", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_SE4BEG0_3", + "CMT_TOP_IMUX40_5", + "CMT_TOP_EE4BEG3_2", + "PLL_CLK_FREQ_BB_BUFOUT_NS2", + "CMT_TOP_BLOCK_OUTS_L_B1_10", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_IMUX34_1", + "CMT_TOP_WL1END2_0", + "CMT_TOP_EE4A1_3", + "CMT_TOP_OCLKDIV_10", + "CMT_TOP_LH7_0", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_IMUX8_11", + "CMT_PHASER_D_OCLKDIV_TOIOI", + "CMT_TOP_WW2END0_2", + "CMT_TOP_IMUX0_3", + "CMT_TOP_EE4A0_1", + "CMT_TOP_WW4A1_4", + "CMT_TOP_IMUX23_3", + "CMT_TOP_IMUX20_0", + "CMT_TOP_WR1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_LH11_9", + "CMT_TOP_IMUX25_1", + "CMT_TOP_ER1BEG1_1", + "CMT_TOP_IMUX44_7", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_TOP_FAN0_12", + "CMT_TOP_WW4A3_10", + "CMT_TOP_WW2A0_4", + "CMT_TOP_SW2A0_10", + "CMT_TOP_WW4A3_3", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_LH1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_NW4A0_4", + "CMT_TOP_CLK1_5", + "CMT_TOP_IMUX37_12", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_NE2A0_10", + "CMT_TOP_IMUX18_5", + "CMT_TOP_IMUX24_8", + "CMT_TOP_IMUX24_7", + "CMT_TOP_LH12_11", + "CMT_TOP_EE4B0_2", + "CMT_TOP_IMUX29_12", + "CMT_TOP_SW2A0_2", + "CMT_TOP_SW4A3_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", + "CMT_TOP_EE2A3_10", + "CMT_TOP_IMUX42_12", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_WL1END3_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", + "CMT_TOP_SE4BEG0_11", + "CMT_TOP_FAN4_5", + "CMT_TOP_EE4A1_10", + "CMT_TOP_NE2A1_2", + "CMT_TOP_SE4BEG1_7", + "CMT_TOP_NE2A1_10", + "CMT_TOP_WW2END2_11", + "CMT_TOP_IMUX36_3", + "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", + "CMT_TOP_IMUX10_11", + "CMT_TOP_IMUX14_9", + "CMT_TOP_ER1BEG2_11", + "CMT_TOP_IMUX21_7", + "CMT_TOP_EE4B3_11", + "CMT_TOP_IMUX25_7", + "CMT_TOP_SW4A2_5", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_EE4BEG2_12", + "CMT_TOP_NE2A2_12", + "CMT_TOP_WW4C0_9", + "CMT_TOP_NE4C2_3", + "CMT_TOP_WW4A1_8", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_BYP7_5", + "CMT_TOP_NE2A0_5", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_EE4A0_2", + "CMT_TOP_SW4END3_8", + "CMT_TOP_IMUX20_6", + "CMT_TOP_LH9_3", + "CMT_TOP_EE4B3_0", + "CMT_TOP_EL1BEG1_9", + "CMT_TOP_SW2A2_10", + "CMT_TOP_WW4END3_0", + "CMT_TOP_WW2A0_1", + "CMT_TOP_SW4A0_9", + "CMT_TOP_IMUX45_7", + "CMT_TOP_IMUX19_2", + "CMT_TOP_IMUX42_5", + "CMT_TOP_IMUX18_11", + "CMT_TOP_EE4B1_12", + "CMT_TOP_LOGIC_OUTS_L_B10_12", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_BLOCK_OUTS_L_B0_9", + "CMT_TOP_WL1END2_7", + "CMT_TOP_SW4END3_6", + "CMT_TOP_SW4A0_3", + "CMT_TOP_BYP1_10", + "CMT_TOP_IMUX27_7", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_EE4BEG3_12", + "CMT_TOP_SW4A2_10", + "CMT_TOP_IMUX28_12", + "CMT_TOP_LOGIC_OUTS_L_B6_10", + "CMT_TOP_BYP5_6", + "CMT_TOP_IMUX27_8", + "CMT_TOP_IMUX34_3", + "CMT_TOP_FAN0_0", + "CMT_TOP_IMUX23_11", + "CMT_TOP_WR1END1_1", + "CMT_TOP_WW4END3_6", + "CMT_TOP_WW4B3_7", + "CMT_TOP_SW4A0_7", + "CMT_TOP_NE4BEG1_11", + "CMT_TOP_SW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B15_10", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_IMUX6_2", + "CMT_TOP_WW4A1_6", + "CMT_PLL_PHASERREF_BELOW1", + "CMT_TOP_WW4C2_5", + "CMT_TOP_IMUX40_0", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_EE2A2_8", + "CMT_TOP_NE2A3_7", + "CMT_TOP_ER1BEG1_2", + "CMT_TOP_SW4END0_12", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_LOGIC_OUTS_L_B14_11", + "CMT_TOP_LH4_5", + "CMT_TOP_IMUX3_5", + "CMT_TOP_BYP7_4", + "CMT_TOP_CLK1_0", + "CMT_TOP_IMUX26_11", + "CMT_TOP_IMUX1_5", + "CMT_TOP_LH9_4", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_SE4C2_1", + "CMT_TOP_EE2A3_1", + "CMT_TOP_SW2A2_9", + "CMT_TOP_EL1BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_11", + "CMT_TOP_IMUX28_0", + "CMT_TOP_BYP3_11", + "CMT_TOP_IMUX18_2", + "CMT_TOP_WW2END0_1", + "CMT_TOP_LOGIC_OUTS_L_B7_9", + "CMT_TOP_BYP3_0", + "CMT_TOP_BYP4_3", + "CMT_TOP_CLK1_10", + "CMT_TOP_EE4BEG0_11", + "CMT_TOP_NE2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_BLOCK_OUTS_L_B0_11", + "CMT_TOP_EE2A3_8", + "CMT_TOP_EE4A2_8", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", + "CMT_TOP_WW4C0_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_WW4B1_4", + "CMT_TOP_CTRL0_4", + "CMT_TOP_SW4END0_6", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_NW4A3_7", + "CMT_TOP_WW4B1_10", + "CMT_TOP_SE2A3_5", + "CMT_TOP_LH5_10", + "CMT_TOP_WW4END0_11", + "CMT_TOP_BYP7_7", + "CMT_TOP_IMUX29_5", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_IMUX25_5", + "CMT_TOP_WW4A3_4", + "CMT_PLL_PHASER_RDCLK_TOFIFO", + "CMT_TOP_FAN5_9", + "CMT_TOP_IMUX46_8", + "CMT_TOP_IMUX31_11", + "CMT_TOP_BYP4_0", + "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "CMT_TOP_IMUX18_4", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_TOP_LOGIC_OUTS_L_B16_9", + "CMT_TOP_WW2A2_3", + "CMT_TOP_IMUX44_12", + "CMT_TOP_IMUX28_3", + "CMT_TOP_SE2A1_12", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WW2A1_11", + "CMT_TOP_LH6_1", + "CMT_TOP_LH7_3", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_NE2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH6_0", + "CMT_TOP_WW4C0_7", + "CMT_TOP_SE4BEG2_2", + "CMT_TOP_WW4END1_10", + "CMT_TOP_LH3_5", + "CMT_TOP_BYP0_10", + "CMT_TOP_NE4C0_4", + "CMT_TOP_SW2A1_7", + "CMT_TOP_NE4C0_2", + "CMT_TOP_R_UPPER_T_PLLE2_DO5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "CMT_TOP_SE4C0_7", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_SE4C0_12", + "CMT_TOP_LOGIC_OUTS_L_B11_10", + "CMT_TOP_SW4A1_8", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_LH11_11", + "CMT_TOP_WR1END3_3", + "CMT_TOP_MONITOR_P_1", + "CMT_TOP_LH8_8", + "CMT_TOP_SW4A3_6", + "CMT_TOP_SW4END1_11", + "CMT_TOP_IMUX31_8", + "CMT_TOP_EE2A3_0", + "CMT_TOP_IMUX21_11", + "CMT_TOP_IMUX13_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", + "CMT_TOP_IMUX39_4", + "CMT_TOP_NW4END2_11", + "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "CMT_TOP_MONITOR_P_3", + "CMT_TOP_EE4B1_7", + "CMT_TOP_WW4A0_7", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_WW4B0_11", + "CMT_TOP_SE2A1_2", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_BYP5_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", + "CMT_TOP_NE2A0_4", + "CMT_TOP_LH9_0", + "CMT_TOP_IMUX22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_10", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_IMUX25_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", + "CMT_TOP_NE2A1_4", + "CMT_TOP_EE4BEG3_0", + "CMT_TOP_WW2END1_7", + "CMT_TOP_EE4B0_7", + "CMT_TOP_WW4B2_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", + "CMT_TOP_BYP1_0", + "CMT_TOP_IMUX22_4", + "CMT_TOP_SE4C1_0", + "CMT_TOP_FAN7_3", + "CMT_TOP_WW4A0_6", + "CMT_TOP_WW2END2_1", + "CMT_TOP_IMUX45_5", + "CMT_TOP_BYP6_4", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_TOP_BYP3_5", + "CMT_TOP_EE2A0_3", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_EE4C2_2", + "CMT_TOP_FAN2_10", + "CMT_TOP_CTRL1_5", + "CMT_TOP_CTRL0_5", + "CMT_TOP_WW2END0_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", + "CMT_TOP_IMUX1_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", + "CMT_TOP_WW2END0_7", + "CMT_TOP_NW4END0_11", + "CMT_TOP_EL1BEG0_12", + "CMT_TOP_LOGIC_OUTS_L_B20_11", + "CMT_TOP_WL1END2_3", + "CMT_TOP_WW4END1_12", + "CMT_TOP_IMUX36_11", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_IMUX10_3", + "CMT_TOP_IMUX37_10", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_SW4A3_12", + "CMT_TOP_WR1END3_8", + "CMT_TOP_IMUX47_1", + "CMT_TOP_IMUX10_6", + "CMT_TOP_IMUX44_10", + "CMT_TOP_BYP6_11", + "CMT_TOP_NE4C1_0", + "CMT_TOP_WW4A3_1", + "CMT_TOP_BYP6_6", + "CMT_TOP_BYP4_10", + "CMT_TOP_LOGIC_OUTS_L_B23_11", + "CMT_TOP_NE4C0_3", + "CMT_TOP_SW4A3_9", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_OCLKDIV_8", + "CMT_TOP_LH2_1", + "CMT_TOP_IMUX42_1", + "CMT_TOP_SW4A1_6", + "CMT_TOP_LH12_0", + "CMT_TOP_IMUX7_11", + "CMT_TOP_NW4A1_9", + "CMT_TOP_BYP1_8", + "CMT_TOP_WW4C2_1", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_IMUX42_0", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", + "CMT_TOP_FAN7_1", + "CMT_TOP_SE4C2_9", + "CMT_TOP_IMUX38_12", + "CMT_TOP_WW2A3_0", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_WW4A2_9", + "CMT_TOP_NE4C2_12", + "CMT_TOP_LH1_7", + "CMT_TOP_EE2BEG2_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", + "CMT_TOP_NW4A1_6", + "CMT_TOP_BYP2_1", + "CMT_TOP_WL1END2_10", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_IMUX13_0", + "CMT_TOP_LOGIC_OUTS_L_B22_12", + "CMT_TOP_IMUX30_7", + "CMT_TOP_WW4A0_3", + "CMT_TOP_FAN2_0", + "CMT_TOP_BLOCK_OUTS_L_B1_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", + "CMT_TOP_IMUX18_9", + "CMT_TOP_EE2A0_5", + "CMT_TOP_CTRL1_0", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_TOP_IMUX30_12", + "CMT_TOP_WW4A0_1", + "CMT_TOP_FAN3_0", + "CMT_TOP_LH2_7", + "CMT_TOP_IMUX30_2", + "CMT_TOP_FAN3_3", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_IMUX2_5", + "CMT_TOP_IMUX28_4", + "CMT_TOP_IMUX10_9", + "CMT_TOP_EL1BEG3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_9", + "CMT_TOP_LH11_0", + "CMT_TOP_EE4C1_11", + "CMT_TOP_IMUX15_5", + "CMT_TOP_IMUX13_8", + "CMT_TOP_SE4C1_9", + "CMT_TOP_EE4C0_5", + "CMT_TOP_IMUX2_0", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_SW4END1_1", + "CMT_TOP_LH12_7", + "CMT_TOP_WR1END3_7", + "CMT_TOP_WL1END1_7", + "CMT_TOP_OCLK_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", + "CMT_TOP_EE4C1_2", + "CMT_TOP_R_UPPER_T_PLLE2_DI5", + "CMT_TOP_BYP0_4", + "CMT_TOP_FAN4_0", + "CMT_TOP_BYP7_10", + "CMT_TOP_SW2A0_9", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_MONITOR_N_9", + "CMT_TOP_WW4A1_3", + "CMT_TOP_WW4END0_9", + "CMT_TOP_FAN4_4", + "CMT_TOP_ICLKDIV_9", + "CMT_TOP_IMUX25_12", + "CMT_TOP_IMUX7_8", + "CMT_TOP_LOGIC_OUTS_L_B5_11", + "CMT_TOP_WW4B2_11", + "CMT_TOP_BYP7_0", + "CMT_TOP_FAN7_11", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_BYP6_2", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_EE4C2_8", + "CMT_TOP_IMUX14_6", + "CMT_TOP_LOGIC_OUTS_L_B19_11", + "CMT_TOP_SW4A2_11", + "CMT_TOP_IMUX10_1", + "CMT_TOP_NE4C3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_LOGIC_OUTS_L_B8_9", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_IMUX37_11", + "CMT_TOP_IMUX6_4", + "CMT_TOP_BLOCK_OUTS_L_B0_10", + "CMT_TOP_BLOCK_OUTS_L_B1_11", + "CMT_TOP_R_UPPER_T_PLLE2_DO4", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_TOP_CTRL0_11", + "CMT_TOP_R_UPPER_T_PLLE2_DI10", + "CMT_TOP_IMUX43_7", + "CMT_TOP_LOGIC_OUTS_L_B23_9", + "CMT_TOP_R_UPPER_T_PLLE2_DRDY", + "CMT_TOP_EE2BEG0_4", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LOGIC_OUTS_L_B7_10", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_IMUX38_7", + "CMT_TOP_IMUX21_10", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_SW4A2_7", + "CMT_TOP_OCLK1X_90_10", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", + "CMT_TOP_LH1_2", + "CMT_TOP_BYP0_9", + "CMT_TOP_LOGIC_OUTS_L_B4_10", + "CMT_TOP_FAN4_10", + "CMT_TOP_IMUX30_3", + "CMT_TOP_R_UPPER_T_PLLE2_DI9", + "CMT_TOP_WR1END3_10", + "CMT_TOP_EE2BEG3_9", + "CMT_TOP_WR1END1_6", + "CMT_TOP_SW2A2_5", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_NW2A1_8", + "CMT_TOP_IMUX15_11", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_IMUX36_9", + "CMT_TOP_EE4B2_1", + "CMT_TOP_SW2A2_0", + "CMT_TOP_NW4END2_3", + "CMT_TOP_FAN4_2", + "CMT_TOP_IMUX43_0", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_WW4END0_8", + "CMT_TOP_SW4A1_4", + "CMT_TOP_WW2A2_12", + "CMT_TOP_CLK0_12", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", + "CMT_TOP_IMUX29_0", + "CMT_TOP_FAN6_0", + "CMT_TOP_NW2A2_12", + "CMT_TOP_IMUX43_2", + "CMT_TOP_EE4B1_1", + "CMT_TOP_NW2A2_8", + "CMT_TOP_CTRL1_10", + "CMT_TOP_WW2A0_3", + "CMT_TOP_WW2A2_5", + "CMT_TOP_FAN4_9", + "CMT_TOP_SW4END1_6", + "CMT_TOP_NE4BEG0_9", + "CMT_TOP_EE4B2_5", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_WW2A2_0", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_NE4C3_2", + "CMT_TOP_SE4BEG3_4", + "CMT_TOP_WW2END3_3", + "CMT_TOP_IMUX5_4", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_TOP_WW2END3_2", + "CMT_TOP_NE4C2_1", + "CMT_TOP_R_UPPER_T_CLKPLL3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", + "CMT_TOP_SW4END2_2", + "CMT_PLL_PHASER_OUT_D_OCLK", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_NE2A3_8", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B2_11", + "CMT_TOP_SW4A1_3", + "CMT_TOP_NW4A2_8", + "CMT_TOP_WR1END1_5", + "CMT_TOP_SE4C2_5", + "CMT_TOP_R_UPPER_T_PLLE2_DWE", + "CMT_TOP_LOGIC_OUTS_L_B22_11", + "CMT_TOP_ER1BEG3_3", + "CMT_TOP_WW2A3_9", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_FAN2_4", + "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_IMUX41_2", + "CMT_TOP_IMUX20_2", + "CMT_TOP_SW4END2_6", + "CMT_TOP_NW4END0_9", + "CMT_TOP_IMUX45_1", + "CMT_TOP_LOGIC_OUTS_L_B18_12", + "CMT_TOP_IMUX24_9", + "CMT_TOP_WW4B3_3", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_WW4C1_12", + "CMT_TOP_NE4C3_3", + "CMT_TOP_BYP2_0", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_LH8_12", + "CMT_TOP_LH12_6", + "CMT_TOP_SW4END2_9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_EE4A1_1", + "CMT_TOP_IMUX27_9", + "CMT_TOP_SW4A0_10", + "CMT_TOP_IMUX26_3", + "CMT_TOP_SW4A2_0", + "CMT_TOP_EL1BEG3_9", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_LOGIC_OUTS_L_B2_10", + "CMT_TOP_IMUX47_0", + "CMT_TOP_IMUX7_10", + "CMT_TOP_FAN5_5", + "CMT_TOP_NW4END2_10", + "CMT_TOP_SE4C0_3", + "CMT_TOP_IMUX45_4", + "CMT_TOP_EL1BEG1_11", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_EE2A3_7", + "CMT_TOP_EE4A3_9", + "CMT_TOP_IMUX19_0", + "CMT_TOP_WR1END0_0", + "CMT_TOP_WW4B1_12", + "CMT_TOP_EE4BEG1_9", + "CMT_TOP_NE2A3_3", + "CMT_TOP_WW4C1_8", + "CMT_TOP_SW4A3_10", + "CMT_TOP_FAN5_11", + "CMT_TOP_NE4C0_5", + "CMT_TOP_IMUX8_6", + "CMT_TOP_WL1END2_2", + "CMT_TOP_SE2A0_9", + "CMT_TOP_R_UPPER_T_PLLE2_DO8", + "CMT_TOP_EE4A3_4", + "CMT_TOP_WW4END0_12", + "CMT_TOP_BYP1_2", + "CMT_TOP_WW4END2_3", + "CMT_TOP_IMUX24_2", + "CMT_TOP_IMUX6_0", + "CMT_TOP_NW4END1_10", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_WW2END2_10", + "CMT_TOP_EE4B2_0", + "CMT_TOP_IMUX45_12", + "CMT_TOP_SW2A0_7", + "CMT_TOP_CLK0_8", + "CMT_TOP_IMUX44_0", + "CMT_TOP_EE4C3_10", + "CMT_TOP_BYP4_6", + "CMT_TOP_LH2_12", + "CMT_TOP_WW2END1_11", + "CMT_TOP_IMUX7_0", + "CMT_TOP_IMUX9_4", + "CMT_TOP_EE4A0_4", + "CMT_TOP_LH9_6", + "CMT_TOP_SW2A3_7", + "CMT_TOP_WW4A3_9", + "CMT_TOP_NW4END3_8", + "CMT_TOP_NW4A1_2", + "CMT_TOP_SE2A0_7", + "CMT_TOP_WW4B1_3", + "CMT_TOP_BYP4_11", + "CMT_TOP_WR1END2_8", + "CMT_TOP_LH4_12", + "CMT_TOP_NW2A0_2", + "CMT_TOP_EE4B0_3", + "CMT_TOP_FAN1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_10", + "CMT_TOP_SE2A1_4", + "CMT_TOP_SE4C0_6", + "CMT_TOP_IMUX17_4", + "CMT_TOP_LH2_10", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", + "CMT_TOP_EL1BEG1_12", + "CMT_TOP_SW4END2_4", + "CMT_TOP_WL1END0_6", + "CMT_TOP_LOGIC_OUTS_L_B13_12", + "CMT_TOP_IMUX37_2", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_EE4B3_6", + "CMT_TOP_NW4END2_5", + "CMT_TOP_EE4A1_7", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_IMUX15_3", + "CMT_TOP_EE2A3_12", + "CMT_TOP_LH7_10", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_WR1END3_9", + "CMT_TOP_WW2END3_10", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_LH6_7", + "CMT_TOP_WW4END3_12", + "CMT_TOP_EE4C2_10", + "CMT_TOP_IMUX11_3", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_MONITOR_P_12", + "CMT_TOP_EE4B2_4", + "CMT_TOP_WW2A3_5", + "CMT_TOP_WW2END2_6", + "CMT_TOP_SW4END0_7", + "CMT_TOP_OCLK_9", + "CMT_TOP_LH1_9", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_BYP7_11", + "CMT_TOP_WL1END1_2", + "CMT_TOP_WW2A3_8", + "CMT_TOP_WW2END3_0", + "CMT_TOP_IMUX30_6", + "CMT_TOP_EL1BEG0_1", + "CMT_TOP_IMUX22_5", + "CMT_TOP_FAN2_11", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_IMUX12_0", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_NE2A1_1", + "CMT_TOP_IMUX19_3", + "CMT_TOP_WW4B0_5", + "CMT_TOP_R_UPPER_T_PLLE2_DO14", + "CMT_TOP_ICLK_8", + "CMT_TOP_IMUX7_9", + "CMT_TOP_IMUX7_6", + "CMT_TOP_SW2A1_2", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_IMUX36_2", + "CMT_TOP_WW2END3_1", + "CMT_TOP_NE4C0_1", + "CMT_TOP_IMUX11_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", + "CMT_TOP_BYP3_10", + "CMT_TOP_IMUX11_5", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_TOP_NE4BEG2_2", + "CMT_TOP_IMUX30_1", + "CMT_TOP_WR1END1_12", + "CMT_TOP_WW2END0_11", + "CMT_TOP_WW4C1_9", + "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", + "CMT_TOP_SE4C3_2", + "CMT_TOP_NE4C0_7", + "CMT_TOP_EE4A2_1", + "CMT_TOP_WW2END2_9", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "CMT_TOP_IMUX43_3", + "CMT_TOP_IMUX21_4", + "CMT_TOP_IMUX33_3", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_LH5_8", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_NW4A2_10", + "CMT_TOP_WW4END3_1", + "CMT_TOP_LOGIC_OUTS_L_B14_10", + "CMT_TOP_IMUX35_4", + "CMT_TOP_NE4C1_10", + "CMT_TOP_LOGIC_OUTS_L_B3_9", + "CMT_TOP_IMUX42_8", + "CMT_TOP_EE2A3_4", + "CMT_TOP_EE4BEG2_6", + "CMT_TOP_IMUX38_8", + "CMT_TOP_CLK0_0", + "CMT_TOP_SE2A1_6", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_LH8_11", + "CMT_TOP_FAN7_2", + "CMT_TOP_EE2A0_7", + "CMT_TOP_NE4BEG2_10", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_WW4C3_9", + "CMT_TOP_EE2BEG0_10", + "CMT_TOP_IMUX37_1", + "CMT_TOP_EE4C3_5", + "CMT_TOP_NE4C3_5", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_ER1BEG2_12", + "CMT_TOP_BYP5_2", + "CMT_TOP_NE2A0_12", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_IMUX6_1", + "CMT_TOP_NE2A0_9", + "CMT_TOP_IMUX36_4", + "CMT_TOP_BYP4_1", + "CMT_TOP_IMUX9_3", + "CMT_TOP_IMUX15_6", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_IMUX7_3", + "CMT_TOP_NW4END1_1", + "CMT_TOP_FAN3_8", + "CMT_TOP_LH4_1", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX45_0", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", + "CMT_TOP_EE4B1_9", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_FAN6_9", + "CMT_TOP_EE4C2_3", + "CMT_TOP_WR1END1_8", + "CMT_TOP_IMUX19_9", + "CMT_TOP_IMUX5_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", + "CMT_TOP_EL1BEG0_11", + "CMT_TOP_EE4A0_5", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NW2A0_5", + "CMT_TOP_IMUX24_10", + "CMT_PHASER_D_ICLK_TOIOI", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_IMUX16_10", + "CMT_TOP_LOGIC_OUTS_L_B8_12", + "CMT_TOP_SW4END1_4", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX5_11", + "CMT_TOP_EE4C0_9", + "CMT_TOP_IMUX18_6", + "CMT_TOP_EE4B0_1", + "CMT_TOP_LOGIC_OUTS_L_B17_11", + "CMT_TOP_SW2A3_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_WW4A3_7", + "CMT_TOP_WW4A1_7", + "CMT_TOP_IMUX41_6", + "CMT_TOP_LH4_0", + "CMT_TOP_SW2A2_8", + "CMT_TOP_WW2A0_9", + "CMT_TOP_BYP2_7", + "CMT_TOP_LOGIC_OUTS_L_B12_12", + "CMT_TOP_SW4A1_2", + "CMT_TOP_FAN3_4", + "CMT_TOP_IMUX4_10", + "CMT_TOP_SW4END3_3", + "CMT_TOP_LOGIC_OUTS_L_B17_12", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH11_7", + "CMT_TOP_NW2A3_1", + "CMT_TOP_WW4A1_5", + "CMT_TOP_WW2A2_11", + "CMT_TOP_FAN3_5", + "CMT_TOP_EE4C1_3", + "CMT_TOP_WW2A2_7", + "CMT_TOP_BYP5_10", + "CMT_TOP_OCLK_1", + "CMT_TOP_EE4C1_9", + "CMT_TOP_WL1END3_4", + "CMT_TOP_EE2A0_10", + "CMT_TOP_WW4END2_12", + "CMT_TOP_IMUX41_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", + "CMT_TOP_EE4B3_2", + "CMT_TOP_SW2A1_11", + "CMT_TOP_BYP1_12", + "CMT_TOP_NW4END2_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_LOGIC_OUTS_L_B2_12", + "CMT_TOP_FAN6_1", + "CMT_TOP_EE4C1_7", + "CMT_TOP_R_UPPER_T_PLLE2_DI4", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_IMUX28_11", + "CMT_TOP_SE4C1_6", + "CMT_TOP_IMUX39_6", + "CMT_TOP_IMUX35_2", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_NE2A1_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", + "CMT_TOP_WL1END0_2", + "CMT_TOP_LOGIC_OUTS_L_B22_9", + "CMT_TOP_IMUX41_10", + "CMT_TOP_IMUX44_1", + "CMT_TOP_IMUX33_10", + "CMT_TOP_WW2A1_2", + "CMT_TOP_IMUX16_5", + "CMT_TOP_R_UPPER_T_CLKPLL0", + "CMT_TOP_NW4END2_4", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_TOP_IMUX39_7", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_TOP_SW4END3_10", + "CMT_TOP_IMUX26_0", + "CMT_TOP_EL1BEG0_4", + "CMT_TOP_IMUX4_6", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_EE4B3_3", + "CMT_TOP_R_UPPER_T_PLLE2_DO12", + "CMT_TOP_WW4B0_6", + "CMT_TOP_NW2A0_1", + "CMT_TOP_IMUX27_4", + "CMT_TOP_LOGIC_OUTS_L_B0_10", + "CMT_TOP_NE4BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_EE4C1_8", + "CMT_TOP_EE4C1_4", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_SW2A3_9", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_BYP2_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", + "CMT_TOP_IMUX0_9", + "CMT_TOP_NW2A3_6", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_CLK0_7", + "CMT_TOP_WL1END3_0", + "CMT_TOP_IMUX13_7", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_EE2A2_0", + "CMT_TOP_ICLK_4", + "CMT_TOP_LOGIC_OUTS_L_B21_9", + "CMT_TOP_IMUX4_0", + "PLL_CLK_FREQ_BB_BUFOUT_NS0", + "CMT_TOP_MONITOR_P_9", + "CMT_TOP_IMUX3_6", + "CMT_TOP_EE4B0_11", + "CMT_TOP_BYP7_1", + "CMT_TOP_OCLKDIV_9", + "CMT_TOP_WW2END0_8", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_WW2END1_3", + "CMT_TOP_SE2A3_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_NE4BEG3_9", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_BYP3_4", + "CMT_TOP_SE4C3_0", + "CMT_TOP_IMUX25_8", + "CMT_TOP_NE4BEG1_12", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_SW4END3_0", + "CMT_TOP_WW4C0_12", + "CMT_TOP_IMUX3_3", + "CMT_TOP_WW2END1_2", + "CMT_TOP_SE4C1_3", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_LH9_10", + "CMT_TOP_WW2A0_11", + "CMT_TOP_IMUX25_11", + "CMT_TOP_NW2A1_1", + "CMT_TOP_IMUX14_12", + "CMT_TOP_NW2A2_5", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX19_6", + "CMT_TOP_WW4A1_2", + "CMT_TOP_NW4A2_9", + "CMT_TOP_IMUX19_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_SE4BEG2_5", + "CMT_TOP_BLOCK_OUTS_L_B3_11", + "CMT_TOP_NE4C3_11", + "CMT_TOP_NW4END2_9", + "CMT_TOP_WW2A1_7", + "CMT_TOP_SW4END0_8", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WL1END0_4", + "CMT_TOP_IMUX18_12", + "CMT_TOP_IMUX35_1", + "CMT_TOP_NE4C1_1", + "CMT_TOP_WL1END0_5", + "CMT_TOP_IMUX6_9", + "CMT_TOP_R_UPPER_T_PLLE2_DO3", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_IMUX20_1", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_WW4C3_0", + "CMT_TOP_FAN4_3", + "CMT_TOP_NW4END1_12", + "CMT_TOP_WR1END3_2", + "CMT_TOP_WW4B3_11", + "CMT_TOP_SE2A2_9", + "CMT_TOP_IMUX5_7", + "CMT_TOP_LH7_11", + "CMT_TOP_FAN7_10", + "CMT_TOP_IMUX22_11", + "CMT_TOP_IMUX40_10", + "CMT_TOP_R_UPPER_T_PLLE2_DO2", + "CMT_TOP_WW2A2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_WW2END0_4", + "CMT_TOP_NW2A2_1", + "CMT_TOP_EE4A1_9", + "CMT_TOP_NE4C3_6", + "CMT_TOP_OCLK_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", + "CMT_PLL_DQS_TO_PHASER_D", + "CMT_TOP_ER1BEG2_0", + "CMT_TOP_R_UPPER_T_CLKPLL2", + "CMT_TOP_NW4A2_3", + "CMT_TOP_EE2BEG1_10", + "CMT_TOP_EE2BEG0_12", + "CMT_TOP_WW4C3_3", + "CMT_TOP_NW4END1_4", + "CMT_TOP_NW2A1_2", + "CMT_TOP_EE4BEG0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_TOP_WW4END0_7", + "CMT_TOP_SW4A3_2", + "CMT_TOP_R_UPPER_T_PLLE2_DI11", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_IMUX5_8", + "CMT_TOP_WW4A1_11", + "CMT_TOP_SW4A1_5", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_MONITOR_N_11", + "CMT_TOP_IMUX32_6", + "CMT_TOP_SE2A2_12", + "CMT_TOP_NW2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_WW4B0_10", + "CMT_TOP_WW4A1_0", + "CMT_TOP_EE2A3_6", + "CMT_TOP_WR1END2_10", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_BYP0_6", + "CMT_TOP_WL1END1_5", + "CMT_TOP_IMUX30_0", + "CMT_TOP_LOGIC_OUTS_L_B5_9", + "CMT_TOP_NW2A0_8", + "CMT_TOP_WW4C1_5", + "CMT_TOP_SE4BEG2_11", + "CMT_TOP_NW4A3_11", + "CMT_TOP_WW4C3_12", + "CMT_TOP_IMUX34_6", + "CMT_TOP_SW4A2_4", + "CMT_TOP_NE4C3_1", + "CMT_TOP_NW4A1_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", + "CMT_TOP_IMUX22_6", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX1_4", + "CMT_TOP_SW4A1_0", + "CMT_TOP_IMUX41_9", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_FAN2_2", + "CMT_TOP_IMUX33_4", + "CMT_TOP_SE4C0_8", + "CMT_TOP_EE2BEG0_11", + "CMT_TOP_NE4BEG3_12", + "CMT_TOP_IMUX32_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_EE2BEG1_3", + "CMT_TOP_EE2A2_4", + "CMT_TOP_WW4B2_7", + "CMT_TOP_EE4B1_3", + "CMT_TOP_SW4END0_0", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH10_2", + "CMT_TOP_IMUX4_8", + "CMT_TOP_NE4C1_11", + "CMT_TOP_WW2A1_1", + "CMT_TOP_EE4A1_0", + "CMT_TOP_IMUX9_6", + "CMT_TOP_IMUX42_3", + "CMT_TOP_IMUX13_10", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", + "CMT_TOP_WR1END0_6", + "CMT_TOP_OCLK1X_90_11", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_TOP_IMUX22_2", + "CMT_TOP_R_UPPER_T_PLLE2_DI1", + "CMT_TOP_SE4C3_6", + "CMT_TOP_IMUX44_4", + "CMT_TOP_CTRL0_1", + "CMT_TOP_IMUX29_10", + "CMT_TOP_IMUX12_11", + "CMT_TOP_WW4B2_0", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_LH12_5", + "CMT_TOP_NE4BEG3_11", + "CMT_TOP_IMUX12_6", + "PLL_CLK_FREQ_BB2_NS", + "CMT_TOP_IMUX23_4", + "CMT_TOP_NE4BEG1_5", + "CMT_TOP_NE2A3_6", + "CMT_TOP_ICLK_3", + "CMT_TOP_IMUX7_4", + "CMT_TOP_CLK0_4", + "CMT_TOP_SE2A3_4", + "CMT_TOP_NE2A3_11", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_IMUX28_6", + "CMT_TOP_WW4A3_8", + "CMT_TOP_EE2A0_0", + "CMT_TOP_SE2A1_0", + "CMT_TOP_LH12_10", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_WW4B1_2", + "CMT_TOP_CTRL1_3", + "CMT_TOP_OCLK1X_90_12", + "CMT_TOP_EE4A3_8", + "CMT_TOP_NW4A0_2", + "CMT_TOP_IMUX26_5", + "CMT_TOP_IMUX27_10", + "CMT_TOP_EE4BEG3_10", + "CMT_TOP_LH6_3", + "CMT_TOP_IMUX40_6", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_WR1END2_4", + "CMT_TOP_WW4C1_11", + "CMT_TOP_IMUX20_4", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_TOP_WW4END2_7", + "CMT_TOP_BYP4_7", + "CMT_TOP_FAN4_11", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_TOP_NE2A2_8", + "CMT_TOP_SE4C0_9", + "CMT_TOP_IMUX34_0", + "CMT_TOP_NE2A1_6", + "CMT_TOP_NE4BEG3_10", + "CMT_TOP_LOGIC_OUTS_L_B7_12", + "CMT_TOP_IMUX2_9", + "CMT_TOP_IMUX0_8", + "CMT_PLL_PHASERREF_BELOW0", + "CMT_TOP_IMUX31_6", + "CMT_TOP_IMUX36_10", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_TOP_WW4END3_7", + "CMT_TOP_WL1END0_9", + "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "CMT_TOP_SW4A0_1", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE2A2_1", + "CMT_TOP_SW2A3_11", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_SW2A1_5", + "CMT_TOP_BLOCK_OUTS_L_B2_10", + "CMT_TOP_CTRL1_8", + "CMT_TOP_OCLK1X_90_9", + "CMT_TOP_NW4A2_5", + "CMT_TOP_NW4A0_0", + "CMT_TOP_WW2A1_10", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_PLL_PHASER_IN_D_ICLK", + "CMT_TOP_IMUX41_1", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX11_7", + "CMT_TOP_IMUX1_12", + "CMT_TOP_NE4C2_11", + "CMT_TOP_R_UPPER_T_PLLE2_DI0", + "PLLOUT_CLK_FREQ_BB_0", + "CMT_TOP_IMUX14_3", + "CMT_TOP_IMUX17_1", + "CMT_TOP_WW4A2_4", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_ICLKDIV_10", + "CMT_TOP_IMUX4_1", + "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT", + "CMT_TOP_IMUX23_1", + "CMT_TOP_NW4A0_3", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_TOP_IMUX17_9", + "CMT_TOP_EE2A0_2", + "CMT_TOP_LOGIC_OUTS_L_B21_11", + "CMT_TOP_WW4A3_12", + "CMT_TOP_WW4END3_3", + "CMT_TOP_LH2_6", + "CMT_TOP_WW4B1_9", + "CMT_TOP_WR1END2_11", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_IMUX32_11", + "CMT_TOP_BYP2_8", + "CMT_TOP_WW4A0_0", + "CMT_TOP_WR1END3_5", + "CMT_TOP_SE4BEG1_3", + "CMT_TOP_WW4END3_2", + "CMT_TOP_WL1END3_3", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_IMUX34_8", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_CTRL0_7", + "CMT_TOP_IMUX43_9", + "CMT_TOP_WW2END1_12", + "CMT_TOP_IMUX13_1", + "CMT_TOP_IMUX11_1", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_SE2A2_3", + "CMT_TOP_NE2A3_4", + "CMT_TOP_OCLKDIV_11", + "CMT_TOP_EE4C2_6", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_SW2A3_10", + "CMT_TOP_SW2A0_5", + "CMT_TOP_LH7_9", + "CMT_TOP_CTRL1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_TOP_IMUX24_12", + "CMT_TOP_LH8_5", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_WL1END3_6", + "CMT_PLL_PHASER_RDENABLE_TOFIFO", + "CMT_TOP_LH1_1", + "CMT_TOP_IMUX4_7", + "CMT_TOP_WW4END2_10", + "CMT_TOP_IMUX24_4", + "CMT_TOP_BYP7_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", + "CMT_TOP_SE4BEG2_12", + "CMT_TOP_FAN2_9", + "CMT_TOP_LOGIC_OUTS_L_B15_11", + "CMT_TOP_WW4A1_9", + "CMT_TOP_EE4C2_11", + "CMT_TOP_IMUX19_1", + "CMT_TOP_LOGIC_OUTS_L_B23_10", + "CMT_TOP_FAN2_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", + "CMT_TOP_NW2A1_9", + "CMT_TOP_LOGIC_OUTS_L_B8_11", + "CMT_TOP_SE4C2_7", + "CMT_TOP_LH5_9", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH7_2", + "CMT_TOP_IMUX13_6", + "CMT_TOP_IMUX1_1", + "CMT_TOP_R_UPPER_T_PLLE2_DI15", + "CMT_TOP_IMUX4_11", + "CMT_TOP_LH3_8", + "CMT_TOP_LOGIC_OUTS_L_B5_12", + "CMT_TOP_EE4C3_3", + "CMT_TOP_SW4A0_0", + "CMT_TOP_SW2A1_8", + "CMT_TOP_IMUX5_9", + "CMT_TOP_IMUX46_0", + "CMT_TOP_IMUX3_0", + "CMT_TOP_IMUX17_12", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_TOP_R_UPPER_T_CLKPLL4", + "CMT_TOP_EE4C2_0", + "CMT_TOP_IMUX16_1", + "CMT_TOP_SW4END2_5", + "CMT_TOP_IMUX16_0", + "CMT_TOP_EE2A1_0", + "CMT_TOP_NW4END0_4", + "CMT_TOP_IMUX12_7", + "CMT_TOP_NW4A0_9", + "CMT_TOP_WR1END1_3", + "CMT_TOP_R_UPPER_T_PLLE2_DI14", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_IMUX42_9", + "CMT_TOP_IMUX47_5", + "CMT_TOP_IMUX31_2", + "CMT_TOP_WR1END0_9", + "CMT_TOP_IMUX17_5", + "CMT_TOP_WW4END3_11", + "CMT_TOP_CLK1_3", + "CMT_TOP_ICLKDIV_11", + "CMT_TOP_R_UPPER_T_PLLE2_DO7", + "CMT_TOP_SE2A1_9", + "CMT_TOP_EE2A3_2", + "CMT_TOP_LH12_9", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_SE4C0_11", + "CMT_TOP_SE4C1_10", + "CMT_TOP_SE4C3_8", + "CMT_TOP_EE4BEG0_12", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_TOP_IMUX43_11", + "CMT_TOP_IMUX39_1", + "CMT_TOP_LH1_3", + "CMT_TOP_BYP5_7", + "CMT_TOP_IMUX6_11", + "CMT_TOP_IMUX47_8", + "CMT_TOP_IMUX36_0", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_NW4A2_2", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_IMUX26_9", + "CMT_TOP_IMUX46_10", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END1_6", + "CMT_TOP_WL1END1_8", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_WW2END1_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", + "PLLOUT_CLK_FREQ_BB_2", + "CMT_TOP_WW4END0_6", + "CMT_TOP_SE2A2_6", + "CMT_TOP_WW4A3_11", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_FAN5_0", + "CMT_TOP_LOGIC_OUTS_L_B3_11", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_IMUX7_2", + "CMT_TOP_SW4A3_11", + "CMT_TOP_SE2A3_10", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_FAN4_12", + "CMT_TOP_LH2_0", + "CMT_TOP_SE2A0_6", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LH9_2", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B4_9", + "CMT_TOP_WW2A3_1", + "CMT_TOP_LH5_3", + "CMT_TOP_R_UPPER_T_CLKPLL6", + "CMT_TOP_NE2A0_6", + "CMT_TOP_FAN4_1", + "CMT_TOP_LH12_1", + "CMT_TOP_LH8_6", + "CMT_TOP_IMUX36_5", + "CMT_TOP_OCLK_6", + "CMT_TOP_SW4END1_5", + "CMT_TOP_LOGIC_OUTS_L_B1_9", + "CMT_TOP_NW4END0_12", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_FAN6_6", + "CMT_TOP_NE2A2_7", + "CMT_TOP_LH7_6", + "CMT_TOP_WW4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX45_3", + "CMT_TOP_IMUX16_12", + "CMT_TOP_NE4BEG1_10", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_WR1END1_10", + "CMT_TOP_LOGIC_OUTS_L_B16_10", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_SW2A0_3", + "CMT_TOP_NE4C1_12", + "CMT_TOP_EE4C0_7", + "CMT_TOP_NW2A0_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", + "CMT_TOP_IMUX12_12", + "CMT_TOP_NW4END1_6", + "CMT_TOP_IMUX34_11", + "CMT_TOP_IMUX38_4", + "CMT_TOP_FAN6_7", + "CMT_TOP_EE4BEG1_11", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_IMUX41_5", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_SW4END2_3", + "CMT_TOP_EE2BEG3_8", + "CMT_TOP_LH9_7", + "CMT_TOP_IMUX4_12", + "CMT_TOP_WW4A1_1", + "CMT_TOP_WR1END0_3", + "CMT_TOP_LH1_6", + "CMT_TOP_FAN2_7", + "CMT_TOP_BYP7_6", + "CMT_TOP_IMUX40_11", + "CMT_TOP_NW4A1_5", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_1", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_IMUX2_10", + "CMT_TOP_IMUX32_10", + "CMT_TOP_FAN6_8", + "CMT_TOP_EE4BEG1_10", + "CMT_TOP_IMUX39_12", + "CMT_TOP_NW4A2_4", + "CMT_TOP_WW4C2_4", + "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", + "CMT_TOP_LH6_5", + "CMT_TOP_LOGIC_OUTS_L_B11_9", + "CMT_TOP_FAN5_7", + "CMT_TOP_BYP2_12", + "CMT_TOP_OCLK_2", + "CMT_TOP_WL1END1_6", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_BYP6_0", + "CMT_TOP_WL1END3_9", + "CMT_TOP_EE2BEG2_6", + "CMT_TOP_WW2END3_9", + "CMT_TOP_IMUX25_9", + "CMT_TOP_NW4END1_7", + "CMT_TOP_EE2A1_4", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_IMUX33_6", + "CMT_TOP_LH2_8", + "CMT_TOP_NW4A2_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", + "CMT_TOP_NE4C1_6", + "CMT_TOP_IMUX8_9", + "CMT_TOP_SW2A1_12", + "CMT_TOP_NE2A0_3", + "CMT_TOP_SE4C3_7", + "CMT_TOP_IMUX34_10", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_IMUX31_1", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_WW4C3_7", + "CMT_TOP_IMUX32_9", + "CMT_TOP_IMUX8_4", + "CMT_TOP_NW2A2_10", + "CMT_TOP_IMUX33_1", + "CMT_TOP_IMUX32_12", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_BYP0_12", + "CMT_TOP_WW4END1_3", + "CMT_TOP_FAN1_11", + "CMT_TOP_SW2A0_1", + "CMT_TOP_IMUX33_8", + "CMT_TOP_NW4A1_3", + "CMT_TOP_LH10_0", + "CMT_TOP_LH5_6", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX7_5", + "CMT_TOP_EE4C2_1", + "CMT_TOP_NE2A3_9", + "CMT_TOP_ER1BEG2_5", + "CMT_TOP_NW2A3_11", + "CMT_TOP_SW4A2_12", + "CMT_TOP_EE4BEG1_5", + "CMT_PLL_PHASERD_DTSBUS0", + "CMT_TOP_EE2A1_3", + "CMT_TOP_EE4C2_4", + "CMT_TOP_SW4A2_3", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_NE4C3_7", + "CMT_TOP_IMUX12_2", + "CMT_TOP_WW4B1_8", + "CMT_TOP_SE2A1_11", + "CMT_TOP_NW4A2_12", + "CMT_TOP_LH6_12", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_IMUX3_9", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_TOP_IMUX21_3", + "CMT_TOP_LH4_11", + "CMT_TOP_EE4A2_3", + "CMT_TOP_LH1_11", + "CMT_TOP_SW4A2_6", + "CMT_TOP_IMUX35_8", + "CMT_TOP_IMUX9_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", + "CMT_TOP_SW4END0_11", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_WW2A3_12", + "CMT_TOP_IMUX16_4", + "CMT_TOP_IMUX39_11", + "CMT_TOP_LH2_4", + "CMT_TOP_LOGIC_OUTS_L_B14_9", + "CMT_TOP_WW4C0_2", + "CMT_TOP_CTRL1_11", + "CMT_TOP_EE4B2_11", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_EE2A0_12", + "CMT_TOP_LH3_6", + "CMT_TOP_WW4A0_12", + "CMT_TOP_EE4C3_0", + "CMT_TOP_IMUX40_1", + "CMT_TOP_CLK0_10", + "CMT_TOP_EE4B0_10", + "CMT_TOP_R_UPPER_T_PLLE2_DI7", + "CMT_TOP_WW4C3_11", + "CMT_TOP_IMUX20_11", + "CMT_TOP_FAN7_9", + "CMT_TOP_IMUX32_2", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_ER1BEG0_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", + "CMT_TOP_LH1_4", + "CMT_TOP_BYP1_11", + "CMT_TOP_BYP0_1", + "CMT_TOP_FAN3_10", + "CMT_TOP_NE4C0_6", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_IMUX24_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", + "CMT_TOP_IMUX12_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", + "CMT_TOP_IMUX29_3", + "CMT_TOP_IMUX18_0", + "CMT_TOP_SW2A0_6", + "CMT_TOP_FAN7_6", + "CMT_TOP_LOGIC_OUTS_L_B21_10", + "CMT_TOP_IMUX24_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", + "CMT_TOP_EE4A0_3", + "CMT_TOP_NE4C3_12", + "CMT_TOP_SW2A3_6", + "CMT_TOP_R_UPPER_T_CLKPLL7", + "CMT_TOP_IMUX10_10", + "CMT_TOP_BLOCK_OUTS_L_B2_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", + "CMT_TOP_IMUX44_11", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_NW2A0_7", + "CMT_TOP_WR1END2_5", + "CMT_TOP_ER1BEG3_12", + "CMT_TOP_BYP5_3", + "CMT_TOP_NW4A2_1", + "CMT_TOP_FAN5_6", + "CMT_TOP_IMUX32_4", + "CMT_TOP_R_UPPER_T_PLLE2_DI13", + "CMT_TOP_LH6_11", + "CMT_TOP_LOGIC_OUTS_L_B16_12", + "CMT_TOP_LOGIC_OUTS_L_B3_12", + "CMT_TOP_SE4BEG3_9", + "CMT_TOP_EE4C3_1", + "CMT_TOP_CTRL0_3", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_TOP_LH5_11", + "CMT_TOP_SE4BEG2_9", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_SW4END1_7", + "CMT_TOP_NW4A3_10", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_IMUX6_5", + "CMT_TOP_WW4A3_5", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_BYP3_9", + "CMT_TOP_EE4A1_12", + "CMT_TOP_IMUX26_2", + "CMT_TOP_IMUX20_10", + "CMT_TOP_IMUX13_4", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_NW4END2_12", + "CMT_TOP_WW4C3_8", + "CMT_TOP_NE2A0_8", + "CMT_TOP_LH6_4", + "CMT_TOP_NW2A2_4", + "CMT_TOP_IMUX20_9", + "CMT_TOP_WW2END3_6", + "CMT_TOP_FAN6_10", + "CMT_TOP_EE4B2_9", + "CMT_TOP_WW4B1_1", + "CMT_TOP_WW4B1_7", + "CMT_TOP_WW2A3_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", + "CMT_TOP_NW4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_IMUX9_11", + "CMT_TOP_BYP7_3", + "CMT_TOP_IMUX25_0", + "CMT_TOP_NE4C2_8", + "CMT_TOP_IMUX41_0", + "CMT_TOP_WL1END2_9", + "CMT_TOP_LH4_4", + "CMT_TOP_WW4B3_12", + "CMT_TOP_IMUX24_3", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_LOGIC_OUTS_L_B14_12", + "CMT_TOP_EE4C3_12", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_NW2A0_4", + "CMT_TOP_EE2A1_2", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX46_3", + "CMT_TOP_WW2END3_11", + "CMT_TOP_CLK1_11", + "CMT_TOP_EE4A2_0", + "CMT_TOP_SE2A2_4", + "CMT_TOP_IMUX29_11", + "CMT_TOP_EE4A0_7", + "CMT_TOP_WW4C2_3", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_IMUX32_3", + "CMT_TOP_EE2A0_11", + "CMT_TOP_IMUX11_8", + "CMT_TOP_ER1BEG2_10", + "CMT_TOP_IMUX27_5", + "CMT_TOP_IMUX36_8", + "CMT_TOP_NW2A1_10", + "CMT_TOP_WL1END1_0", + "CMT_TOP_LH10_12", + "CMT_TOP_IMUX47_3", + "CMT_TOP_IMUX0_2", + "CMT_TOP_NW4END3_11", + "CMT_TOP_WW2A1_6", + "CMT_TOP_SW4A2_1", + "CMT_PLL_PHASER_OUT_D_OCLKDIV", + "CMT_TOP_NW2A2_2", + "CMT_TOP_NW2A0_10", + "CMT_TOP_IMUX5_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4BEG1_4", + "CMT_TOP_WW4END3_9", + "CMT_TOP_SW4A1_12", + "CMT_TOP_MONITOR_P_2", + "CMT_TOP_IMUX30_11", + "CMT_TOP_WW4C3_1", + "CMT_TOP_IMUX33_5", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SE4C2_3", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_EE4A0_9", + "CMT_TOP_LH7_7", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_BYP6_10", + "CMT_TOP_NW4END3_1", + "CMT_TOP_EE2BEG3_10", + "CMT_TOP_WW2END0_5", + "CMT_TOP_LH5_1", + "CMT_TOP_FAN3_12", + "CMT_TOP_LH8_7", + "CMT_TOP_OCLK_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", + "CMT_TOP_FAN6_5", + "CMT_TOP_IMUX27_1", + "CMT_TOP_NE4BEG2_1", + "CMT_PLL_PHYCTRL_SYNC_BB_DN", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_SE2A2_8", + "CMT_TOP_SE4C3_10", + "CMT_TOP_WL1END2_5", + "CMT_TOP_IMUX15_12", + "CMT_TOP_WW2A2_9", + "CMT_TOP_SE2A3_9", + "CMT_TOP_IMUX14_8", + "CMT_TOP_NW4END3_4", + "CMT_TOP_NE2A2_3", + "CMT_TOP_LH8_2", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_EE4A2_10", + "CMT_TOP_IMUX19_10", + "CMT_TOP_LOGIC_OUTS_L_B19_12", + "CMT_TOP_WR1END3_12", + "CMT_TOP_EE4BEG2_11", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_WW2END0_10", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_SE2A3_2", + "CMT_TOP_ER1BEG3_10", + "CMT_TOP_CLK1_8", + "CMT_TOP_IMUX47_12", + "CMT_TOP_LOGIC_OUTS_L_B15_12", + "CMT_TOP_EL1BEG2_11", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_NW4A0_1", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_NW4END2_1", + "CMT_TOP_EE4B0_8", + "CMT_TOP_NW4END2_8", + "CMT_TOP_CLK0_6", + "CMT_TOP_R_UPPER_T_PLLE2_DO10", + "CMT_TOP_WR1END2_6", + "CMT_TOP_WW4END0_1", + "CMT_PLL_PHASER_WRCLK_TOFIFO", + "CMT_TOP_NW2A1_7", + "CMT_TOP_WW4A2_6", + "CMT_TOP_IMUX27_3", + "CMT_TOP_SW2A3_0", + "CMT_TOP_EE2A2_9", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_WR1END2_2", + "CMT_TOP_EE4BEG2_9", + "CMT_TOP_EE2A2_7", + "CMT_TOP_IMUX26_10", + "CMT_TOP_IMUX8_0", + "CMT_TOP_IMUX21_9", + "CMT_TOP_WW4C1_1", + "CMT_TOP_R_UPPER_T_FREQ_BB2", + "CMT_TOP_EE4A0_12", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_LH5_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4C2_0", + "PLLOUT_CLK_FREQ_BB_3", + "CMT_TOP_BLOCK_OUTS_L_B2_12", + "CMT_TOP_EE2A2_11", + "CMT_TOP_WR1END0_8", + "CMT_TOP_WL1END1_4", + "CMT_TOP_WW4C0_10", + "CMT_TOP_WW4B1_6", + "CMT_TOP_WW2A3_7", + "CMT_TOP_BYP3_6", + "CMT_TOP_EE4B1_8", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_IMUX9_1", + "CMT_TOP_SE4C1_5", + "CMT_TOP_LH4_7", + "CMT_TOP_LOGIC_OUTS_L_B5_10", + "CMT_TOP_IMUX20_5", + "CMT_TOP_NE4BEG2_12", + "CMT_TOP_NE4C2_4", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_WW4B1_0", + "CMT_TOP_IMUX0_10", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_IMUX23_7", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_TOP_SE4C1_12", + "CMT_TOP_EE4A2_7", + "CMT_TOP_FAN3_9", + "CMT_TOP_EE2A0_8", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_NW4END0_8", + "CMT_TOP_WW4B2_3", + "CMT_TOP_IMUX23_0", + "CMT_TOP_EE2BEG3_1", + "CMT_TOP_LH6_8", + "CMT_TOP_SW4END0_10", + "CMT_TOP_LH6_10", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_WL1END0_0", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_FAN0_2", + "CMT_TOP_LOGIC_OUTS_L_B10_10", + "CMT_TOP_LH2_11", + "CMT_TOP_WW2END2_0", + "CMT_TOP_IMUX18_3", + "CMT_TOP_IMUX6_10", + "CMT_TOP_BLOCK_OUTS_L_B0_12", + "CMT_TOP_FAN1_1", + "CMT_TOP_NW2A3_8", + "CMT_TOP_LH7_1", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_IMUX43_5", + "CMT_TOP_SE4BEG1_10", + "CMT_TOP_EE4B1_10", + "CMT_TOP_IMUX41_4", + "CMT_TOP_IMUX33_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_SE2A3_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", + "CMT_TOP_SE4C0_0", + "CMT_TOP_NE2A2_9", + "CMT_TOP_OCLKDIV_2", + "CMT_TOP_WW4C2_12", + "CMT_TOP_WW4B3_4", + "CMT_TOP_R_UPPER_T_PLLE2_DI8", + "CMT_TOP_EE4A1_5", + "CMT_TOP_R_UPPER_T_CLKIN2", + "CMT_TOP_IMUX5_3", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_PLL_PHASERREF0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", + "CMT_TOP_BYP2_9", + "CMT_TOP_IMUX23_10", + "PLLOUT_CLK_FREQ_BB_1", + "CMT_TOP_LH5_0", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_IMUX42_10", + "CMT_TOP_LH10_10", + "CMT_TOP_WW4END2_11", + "CMT_TOP_EE4A1_4", + "CMT_TOP_NW4A1_10", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX11_0", + "CMT_TOP_WW2END3_5", + "CMT_TOP_LH7_8", + "CMT_TOP_NE4C1_3", + "CMT_TOP_CTRL1_6", + "CMT_TOP_WW4C2_11", + "CMT_TOP_CLK1_9", + "CMT_TOP_IMUX31_3", + "CMT_TOP_R_UPPER_T_PLLE2_DO15", + "CMT_TOP_IMUX37_3", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_LOGIC_OUTS_L_B18_11", + "CMT_TOP_WW4C0_0", + "CMT_TOP_R_UPPER_T_PLLE2_DCLK", + "CMT_TOP_WW4A0_5", + "CMT_TOP_LH9_12", + "CMT_TOP_EE4C3_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", + "CMT_TOP_IMUX3_8", + "CMT_TOP_NW4END1_11", + "CMT_TOP_WW2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B9_10", + "CMT_TOP_SE2A0_4", + "CMT_TOP_IMUX15_1", + "CMT_TOP_IMUX6_3", + "CMT_TOP_IMUX45_9", + "CMT_TOP_EE4B2_7", + "CMT_TOP_NW2A2_9", + "CMT_TOP_LH3_11", + "CMT_TOP_WR1END0_7", + "CMT_TOP_IMUX24_5", + "CMT_TOP_FAN2_1", + "CMT_TOP_IMUX5_6", + "CMT_TOP_NW4END0_10", + "CMT_TOP_SE4BEG0_9", + "CMT_TOP_NW4END1_9", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_BYP6_5", + "CMT_TOP_ER1BEG3_5", + "CMT_TOP_IMUX37_5", + "CMT_TOP_IMUX37_8", + "CMT_TOP_EE4C0_0", + "CMT_TOP_WW4END2_1", + "CMT_TOP_EE4A1_6", + "CMT_TOP_LOGIC_OUTS_L_B12_10", + "CMT_TOP_SW4END1_0", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_IMUX35_3", + "CMT_TOP_SE4BEG0_12", + "CMT_TOP_WW4A2_3", + "CMT_TOP_IMUX10_4", + "CMT_TOP_BYP6_9", + "CMT_TOP_LOGIC_OUTS_L_B13_9", + "CMT_TOP_WW4END2_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", + "CMT_TOP_IMUX26_6", + "CMT_TOP_EE4A3_0", + "CMT_TOP_IMUX18_10", + "CMT_TOP_IMUX22_10", + "CMT_TOP_EE2A1_5", + "CMT_TOP_SW4END3_1", + "CMT_TOP_EL1BEG1_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", + "CMT_TOP_IMUX4_4", + "CMT_TOP_LOGIC_OUTS_L_B11_12", + "CMT_TOP_NW4END3_3", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_WW4C1_2", + "CMT_TOP_EE2A1_12", + "CMT_TOP_SW4A2_9", + "CMT_TOP_EL1BEG2_12", + "CMT_TOP_IMUX22_0", + "CMT_TOP_LOGIC_OUTS_L_B16_11", + "CMT_TOP_SE2A1_1", + "CMT_TOP_WL1END1_12", + "CMT_TOP_NW2A3_9", + "CMT_TOP_WR1END0_4", + "CMT_TOP_EE2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_WW4A1_10", + "CMT_TOP_EE4C0_6", + "CMT_TOP_IMUX24_0", + "CMT_TOP_EL1BEG1_4", + "CMT_TOP_LOGIC_OUTS_L_B6_12", + "CMT_TOP_WW4B3_10", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_SW2A3_3", + "CMT_TOP_SW4END0_1", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_EE4B1_0", + "CMT_TOP_NE2A3_2", + "CMT_TOP_ER1BEG1_9", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_TOP_ICLK_12", + "CMT_TOP_EE4B1_6", + "CMT_TOP_LH3_9", + "CMT_TOP_BYP3_2", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_LH5_12", + "CMT_TOP_R_UPPER_T_PLLE2_DO6", + "CMT_TOP_SE4BEG1_9", + "CMT_TOP_IMUX34_9", + "CMT_TOP_CLK0_2", + "CMT_TOP_SE4C1_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", + "CMT_TOP_LH10_1", + "CMT_TOP_IMUX22_12", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_SE4BEG3_11", + "CMT_TOP_LOGIC_OUTS_L_B10_11", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_FAN3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_TOP_R_UPPER_T_PLLE2_DI3", + "CMT_TOP_WW4A0_9", + "CMT_TOP_SW2A1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_IMUX3_4", + "CMT_TOP_ICLK_5", + "CMT_TOP_IMUX47_9", + "CMT_TOP_IMUX15_9", + "CMT_TOP_LH12_12", + "CMT_TOP_IMUX31_0", + "CMT_TOP_IMUX29_8", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_LH2_3", + "CMT_TOP_WR1END1_9", + "CMT_TOP_IMUX28_10", + "CMT_TOP_NE4C1_4", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_IMUX2_4", + "CMT_TOP_IMUX38_11", + "CMT_TOP_EE4C1_1", + "CMT_TOP_SW2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_LH8_4", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_WW4END2_0", + "CMT_TOP_EE4C0_1", + "CMT_TOP_IMUX33_11", + "CMT_TOP_FAN5_8", + "CMT_TOP_WW4C1_0", + "CMT_TOP_LOGIC_OUTS_L_B11_11", + "CMT_TOP_EE2A3_9", + "CMT_TOP_LH10_7", + "CMT_TOP_SE4C0_1", + "CMT_TOP_NW4END3_9", + "CMT_TOP_WW4C1_7", + "CMT_TOP_SE2A0_5", + "CMT_TOP_EE2BEG1_9", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_ER1BEG3_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", + "CMT_TOP_IMUX47_11", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BYP0_0", + "CMT_TOP_EE4B2_2", + "CMT_TOP_FAN7_7", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_WW4A0_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", + "CMT_TOP_WW4B0_12", + "CMT_TOP_WW4A3_0", + "CMT_TOP_SE4C1_1", + "CMT_TOP_ER1BEG0_6", + "CMT_TOP_IMUX46_1", + "CMT_TOP_FAN6_11", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_IMUX30_8", + "CMT_TOP_SW2A1_0", + "CMT_TOP_CLK0_1", + "CMT_TOP_BYP5_4", + "CMT_TOP_IMUX45_2", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_WW4C2_6", + "CMT_TOP_IMUX19_5", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_IMUX35_12", + "CMT_TOP_NW4END0_1", + "CMT_TOP_LH3_10", + "CMT_TOP_LH9_8", + "CMT_TOP_R_UPPER_T_PLLE2_DO9", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_TOP_NW2A2_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", + "CMT_TOP_LH11_12", + "CMT_TOP_SW4END0_5", + "CMT_TOP_IMUX29_1", + "CMT_TOP_R_UPPER_T_FREQ_BB1", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_IMUX9_5", + "CMT_TOP_SW4A0_2", + "CMT_TOP_WW2END1_5", + "CMT_TOP_WW2A2_8", + "CMT_TOP_WW4A1_12", + "CMT_TOP_OCLK_8", + "CMT_TOP_IMUX46_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", + "CMT_TOP_EE4C1_12", + "CMT_TOP_IMUX8_3", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_IMUX14_7", + "CMT_TOP_NW2A2_0", + "CMT_TOP_SE4C0_5", + "CMT_TOP_SW4END3_4", + "CMT_TOP_SE2A2_7", + "CMT_TOP_SW2A1_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_IMUX22_8", + "CMT_TOP_LH3_7", + "CMT_TOP_IMUX1_11", + "CMT_TOP_SE2A1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_9", + "CMT_TOP_IMUX43_8", + "CMT_TOP_LH10_5", + "CMT_TOP_NE4BEG2_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_BLOCK_OUTS_L_B3_10", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_NE2A0_0", + "CMT_TOP_NE2A2_6", + "CMT_TOP_SW2A3_12", + "CMT_TOP_NE2A1_12", + "CMT_TOP_WW4C2_9", + "CMT_TOP_SW2A2_2", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_LH11_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", + "CMT_TOP_EE2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_LOGIC_OUTS_L_B20_10", + "CMT_TOP_WW2A2_4", + "CMT_TOP_EE4C1_10", + "CMT_TOP_LH5_2", + "CMT_TOP_IMUX17_8", + "CMT_TOP_EE4BEG1_12", + "CMT_TOP_IMUX36_7", + "CMT_TOP_BYP1_7", + "CMT_TOP_IMUX4_5", + "CMT_TOP_IMUX36_12", + "CMT_TOP_EE4C0_4", + "CMT_TOP_EL1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B13_10", + "CMT_TOP_LOGIC_OUTS_L_B19_10", + "CMT_TOP_ICLK_7", + "CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT", + "CMT_TOP_NE4BEG0_10", + "CMT_TOP_LH11_3", + "CMT_TOP_IMUX32_1", + "CMT_TOP_SW2A2_4", + "CMT_TOP_IMUX11_4", + "CMT_TOP_IMUX9_10", + "CMT_TOP_EE4C3_7", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_WW4B3_0", + "CMT_TOP_IMUX10_5", + "CMT_TOP_WW2END1_1", + "CMT_TOP_FAN0_9", + "CMT_TOP_FAN1_7", + "CMT_TOP_IMUX23_2", + "CMT_TOP_IMUX5_0", + "CMT_TOP_ICLK_6", + "CMT_TOP_EE4A2_9", + "CMT_TOP_IMUX22_1", + "CMT_TOP_WW4B0_8", + "CMT_TOP_IMUX42_11", + "CMT_TOP_OCLKDIV_6", + "CMT_TOP_LH2_9", + "CMT_TOP_NW4A3_1", + "CMT_TOP_IMUX27_0", + "CMT_TOP_SE4C2_8", + "CMT_TOP_WW2END0_9", + "CMT_TOP_SE4C2_4", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_EE2BEG3_12", + "CMT_TOP_SE2A2_1", + "CMT_TOP_NW4END1_5", + "CMT_TOP_EE2BEG0_7", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_WW2A0_12", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX14_10", + "CMT_TOP_WR1END0_12", + "CMT_TOP_IMUX42_7", + "CMT_TOP_EL1BEG0_9", + "CMT_TOP_IMUX41_11", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_IMUX34_12", + "CMT_TOP_WR1END1_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", + "CMT_TOP_IMUX35_7", + "CMT_PLL_PHASERREF_ABOVE0", + "CMT_TOP_SW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_FAN3_7", + "CMT_TOP_LH9_9", + "CMT_TOP_SW4A1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", + "CMT_TOP_SW2A0_8", + "CMT_TOP_IMUX28_9", + "CMT_TOP_EE4B3_7", + "CMT_TOP_WW2A3_11", + "CMT_TOP_IMUX44_3", + "CMT_TOP_IMUX31_10", + "CMT_PLL_PHASERD_DTSBUS1", + "CMT_TOP_EE4B3_10", + "CMT_TOP_WW2END2_12", + "CMT_TOP_NE4C1_9", + "CMT_TOP_SE2A0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_BYP2_3", + "CMT_TOP_IMUX12_10", + "CMT_TOP_IMUX40_3", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_IMUX11_6", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_IMUX39_10", + "CMT_TOP_BYP4_2", + "CMT_PLL_PHASERREF_ABOVE1", + "CMT_TOP_NE4BEG0_12", + "CMT_TOP_NE4BEG3_8", + "CMT_TOP_IMUX1_10", + "CMT_TOP_R_UPPER_T_FREQ_BB0", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_SW2A1_9", + "CMT_TOP_IMUX26_7", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_IMUX1_7", + "CMT_TOP_IMUX23_6", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_FAN5_10", + "CMT_TOP_IMUX6_8", + "CMT_TOP_IMUX4_3", + "CMT_TOP_EE4C1_6", + "CMT_TOP_NW4END3_7", + "CMT_TOP_WW2END3_12", + "CMT_TOP_IMUX13_5", + "CMT_TOP_IMUX46_6", + "CMT_TOP_WW4END0_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LH12_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_CLK1_2", + "CMT_TOP_WW4C2_10", + "CMT_TOP_LOGIC_OUTS_L_B18_10", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_IMUX15_7", + "CMT_TOP_SW4END2_0", + "CMT_TOP_WW4B0_9", + "CMT_TOP_WW4END1_5", + "CMT_TOP_NW4A0_5", + "CMT_TOP_EE2A2_2", + "CMT_TOP_WW4A0_2", + "CMT_TOP_IMUX37_6", + "CMT_TOP_WL1END1_11", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_LH10_11", + "CMT_TOP_IMUX0_0", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_NW2A3_4", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_IMUX42_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_LH3_1", + "CMT_TOP_EE2BEG3_11", + "CMT_TOP_WL1END3_11", + "CMT_TOP_EE4C0_2", + "CMT_TOP_IMUX23_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", + "CMT_TOP_IMUX35_6", + "CMT_TOP_SE2A3_11", + "CMT_TOP_FAN3_6", + "CMT_TOP_SW4END2_1", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_EE4A2_11", + "CMT_TOP_LOGIC_OUTS_L_B17_9", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_WW2A1_3", + "CMT_TOP_FAN2_5", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_TOP_WW2END1_8", + "CMT_TOP_WR1END2_0", + "CMT_TOP_NE2A1_0", + "CMT_TOP_BLOCK_OUTS_L_B3_12", + "CMT_TOP_LH1_8", + "CMT_TOP_WW2A0_7", + "CMT_TOP_FAN7_12", + "CMT_TOP_LOGIC_OUTS_L_B17_10", + "CMT_PLL_PHASERD_DQSBUS1", + "CMT_TOP_EE4BEG1_4", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_EE2BEG2_8", + "CMT_TOP_SW4END0_2", + "CMT_TOP_SW4A0_6", + "CMT_TOP_BYP5_8", + "CMT_TOP_FAN5_4", + "CMT_TOP_IMUX41_7", + "CMT_TOP_IMUX25_2", + "CMT_TOP_EE4A3_1", + "CMT_TOP_IMUX12_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", + "CMT_TOP_WW2A3_3", + "CMT_TOP_IMUX1_6", + "CMT_TOP_IMUX21_2", + "CMT_TOP_CLK1_1", + "CMT_TOP_IMUX27_12", + "CMT_TOP_WW4A2_0", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_TOP_IMUX16_9", + "CMT_TOP_WW4END3_10", + "CMT_TOP_FAN1_10", + "CMT_TOP_NE2A2_0", + "CMT_TOP_IMUX17_11", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_WW2END2_7", + "CMT_TOP_CTRL1_9", + "CMT_TOP_SE4BEG1_1", + "CMT_TOP_CTRL0_12", + "CMT_TOP_NW4END3_5", + "CMT_TOP_IMUX21_5", + "CMT_TOP_WW4END3_4", + "PLL_CLK_FREQ_BB3_NS", + "CMT_TOP_WL1END0_8", + "CMT_TOP_SE2A3_0", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", + "CMT_TOP_WW2END1_9", + "CMT_TOP_NW4A3_6", + "CMT_TOP_WL1END3_10", + "CMT_TOP_SE4C1_7", + "CMT_TOP_LOGIC_OUTS_L_B9_11", + "CMT_TOP_NW2A3_12", + "CMT_TOP_BYP0_8", + "CMT_TOP_IMUX2_11", + "CMT_TOP_EE4A3_3", + "CMT_TOP_WR1END2_12", + "CMT_TOP_LH10_6", + "CMT_TOP_NW4A3_2", + "CMT_TOP_NE4C0_11", + "CMT_TOP_LH3_4", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", + "CMT_TOP_LH8_0", + "CMT_TOP_IMUX24_6", + "CMT_TOP_IMUX45_8", + "CMT_TOP_IMUX33_7", + "CMT_TOP_ER1BEG0_10", + "CMT_TOP_IMUX28_7", + "CMT_TOP_FAN0_10", + "CMT_TOP_LH8_9", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_TOP_R_UPPER_T_PLLE2_DO0", + "CMT_TOP_WL1END1_9", + "CMT_TOP_EE4B0_5", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX15_10", + "CMT_TOP_CLK0_11", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_IMUX3_10", + "CMT_TOP_IMUX17_0", + "CMT_TOP_BYP3_8", + "CMT_TOP_NE2A3_1", + "CMT_TOP_EE4C2_12", + "CMT_TOP_NW2A3_2", + "CMT_TOP_EE4B3_1", + "CMT_TOP_WW4B3_5", + "CMT_TOP_BYP1_9", + "CMT_TOP_SE4C2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_SE2A1_7", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_SE4C3_12", + "CMT_TOP_CTRL1_12", + "CMT_TOP_WL1END3_5", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", + "CMT_TOP_IMUX3_1", + "CMT_TOP_WR1END2_1", + "CMT_TOP_NW4A1_4", + "CMT_TOP_WL1END2_11", + "CMT_TOP_WL1END1_10", + "CMT_TOP_IMUX20_3", + "CMT_TOP_BYP6_8", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX14_2", + "CMT_TOP_BYP4_4", + "CMT_TOP_CLK1_7", + "CMT_TOP_IMUX2_3", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_IMUX46_5", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_NW4END1_3", + "CMT_TOP_IMUX45_11", + "CMT_TOP_NW2A3_5", + "CMT_TOP_EL1BEG3_12", + "CMT_TOP_WR1END2_3", + "CMT_TOP_BYP2_6", + "CMT_TOP_BYP3_3", + "CMT_TOP_FAN6_2", + "CMT_TOP_NW2A2_3", + "CMT_TOP_SW4END2_12", + "CMT_TOP_IMUX40_4", + "CMT_TOP_MONITOR_P_11", + "CMT_TOP_WW4A0_10", + "CMT_TOP_IMUX47_6", + "CMT_TOP_SW4A3_4", + "CMT_TOP_FAN7_0", + "CMT_TOP_WW4A0_11", + "CMT_TOP_LH11_5", + "CMT_TOP_IMUX30_5", + "CMT_TOP_SE2A3_1", + "CMT_TOP_EE4A3_6", + "CMT_TOP_IMUX5_1", + "CMT_TOP_EE4BEG3_6", + "CMT_TOP_SE2A2_0", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_EE4B3_4", + "CMT_TOP_EE4C3_6", + "CMT_TOP_EE4C0_11", + "CMT_TOP_WW4B0_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", + "CMT_PHASER_D_OCLK_TOIOI", + "CMT_TOP_IMUX27_2", + "CMT_TOP_FAN0_8", + "CMT_TOP_EE4A2_6", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_FAN2_6", + "CMT_TOP_SE4BEG0_8", + "CMT_TOP_CLK0_9", + "CMT_TOP_LH1_10", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_SW2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_9", + "CMT_TOP_LOGIC_OUTS_L_B23_12", + "CMT_TOP_OCLK_12", + "CMT_TOP_IMUX46_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", + "CMT_TOP_IMUX3_11", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_NW4END0_6", + "CMT_TOP_IMUX10_0", + "CMT_TOP_IMUX43_4", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "CMT_TOP_EE4A0_0", + "CMT_TOP_IMUX36_1", + "CMT_TOP_LH1_0", + "CMT_TOP_WW4A3_6", + "CMT_TOP_EE2A1_9", + "CMT_TOP_IMUX0_12", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_LOGIC_OUTS_L_B4_11", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_TOP_WW4A3_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", + "CMT_TOP_WW4B2_9", + "CMT_TOP_EE4C0_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", + "CMT_TOP_BYP0_5", + "CMT_TOP_IMUX10_12", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", + "CMT_TOP_ICLK_2", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_FAN0_11", + "CMT_TOP_NE2A3_5", + "CMT_TOP_EL1BEG3_10", + "CMT_TOP_NE2A1_8", + "CMT_TOP_R_UPPER_T_PLLE2_DI2", + "CMT_PLL_PHASERD_CTSBUS1", + "CMT_TOP_LH12_2", + "CMT_TOP_WW2A0_10", + "CMT_TOP_EE4C2_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", + "CMT_TOP_IMUX47_10", + "CMT_TOP_IMUX30_9", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_IMUX19_8", + "CMT_TOP_IMUX17_6", + "CMT_TOP_WW2A2_6", + "CMT_TOP_IMUX14_5", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_TOP_BYP1_6", + "CMT_TOP_IMUX34_2", + "CMT_TOP_SW4A2_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", + "CMT_TOP_EE2BEG2_10", + "CMT_TOP_WW4A2_8", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_IMUX39_5", + "CMT_TOP_NW4A2_7", + "CMT_TOP_IMUX38_1", + "CMT_TOP_WW2A0_8", + "CMT_TOP_ER1BEG1_12", + "CMT_TOP_CTRL1_4", + "CMT_TOP_NW2A1_12", + "CMT_TOP_SE2A0_11", + "CMT_TOP_CTRL0_10", + "CMT_TOP_NE4C2_0", + "CMT_TOP_FAN2_12", + "CMT_TOP_IMUX8_1", + "CMT_TOP_OCLK_0", + "CMT_TOP_NE4C2_7", + "CMT_TOP_IMUX20_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "CMT_TOP_SE2A3_12", + "CMT_TOP_R_UPPER_T_PLLE2_RST", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SE4C3_4", + "CMT_TOP_SE4C3_3", + "CMT_TOP_IMUX12_3", + "PLL_CLK_FREQ_BB_BUFOUT_NS1", + "CMT_PLL_PHASER_IN_D_ICLKDIV", + "CMT_TOP_IMUX19_12", + "CMT_TOP_CLK0_5", + "CMT_TOP_WW2END1_4", + "CMT_TOP_NW2A1_5", + "CMT_TOP_IMUX16_2", + "CMT_TOP_MONITOR_N_10", + "CMT_TOP_BYP2_5", + "CMT_TOP_WR1END3_11", + "CMT_TOP_IMUX40_2", + "CMT_TOP_WW4B2_8", + "CMT_TOP_EE4B1_2", + "CMT_TOP_SE4C1_2", + "CMT_TOP_R_UPPER_T_PLLE2_DI12", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_SW4A1_9", + "CMT_TOP_FAN0_6", + "CMT_TOP_SW4END2_8", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_SE4BEG3_2", + "CMT_TOP_IMUX18_7", + "CMT_TOP_NW4A1_11", + "CMT_TOP_EE2BEG1_8", + "CMT_TOP_NE2A2_10", + "CMT_TOP_EE2BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B21_12", + "CMT_TOP_WW4A2_5", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX44_2", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_CTRL0_0", + "CMT_TOP_IMUX1_8", + "CMT_TOP_IMUX38_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_IMUX5_12", + "CMT_TOP_NW2A1_0", + "CMT_TOP_WW4B3_8", + "CMT_TOP_EE4BEG2_10", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_LOGIC_OUTS_L_B4_12", + "CMT_TOP_IMUX38_0", + "CMT_TOP_SW2A2_1", + "CMT_TOP_NE4C2_9", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_TOP_SE4BEG1_11", + "CMT_TOP_BYP1_3", + "CMT_TOP_CTRL0_6", + "CMT_TOP_EE4A3_10", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_IMUX17_3", + "CMT_TOP_NW2A3_10", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX28_2", + "CMT_TOP_IMUX43_12", + "CMT_TOP_EE2A0_9", + "CMT_TOP_IMUX21_8", + "CMT_TOP_EL1BEG3_11", + "CMT_TOP_IMUX42_2", + "CMT_TOP_WW2A3_6", + "CMT_TOP_WW4B0_4", + "CMT_TOP_SE2A2_5", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_TOP_IMUX38_9", + "CMT_TOP_BYP2_10", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EL1BEG0_10", + "CMT_TOP_EE4B1_11", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_EE2BEG2_7", + "CMT_TOP_ICLK_0", + "CMT_TOP_NW4END1_2", + "CMT_TOP_WW2A2_10", + "CMT_TOP_WW4END1_9", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX31_7", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_NW2A1_3", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX47_2", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_NE2A3_0", + "CMT_TOP_IMUX13_9", + "CMT_TOP_LH10_4", + "CMT_TOP_BYP0_2", + "CMT_TOP_CLK0_3", + "CMT_TOP_EE4B3_12", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_SW4A0_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", + "CMT_TOP_LOGIC_OUTS_L_B13_11", + "CMT_TOP_SW2A2_7", + "CMT_TOP_EL1BEG2_10", + "CMT_TOP_IMUX29_9", + "CMT_TOP_EE4B3_9", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_IMUX25_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_SE4BEG1_12", + "CMT_TOP_ICLK_10", + "CMT_TOP_NE4C1_7", + "CMT_TOP_NW2A2_11", + "CMT_TOP_EE4C3_8", + "CMT_TOP_ICLKDIV_12", + "CMT_TOP_IMUX4_2", + "CMT_TOP_NW4END0_0", + "CMT_TOP_IMUX11_9", + "CMT_TOP_EE4B2_10", + "CMT_TOP_IMUX0_6", + "CMT_TOP_WW4B0_1", + "CMT_TOP_FAN1_5", + "CMT_TOP_WL1END0_11", + "CMT_TOP_EE2A1_8", + "CMT_TOP_NE4C3_10", + "CMT_TOP_OCLK_10", + "CMT_TOP_WW2END2_2", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_FAN4_7", + "CMT_TOP_IMUX27_11", + "CMT_TOP_IMUX36_6", + "CMT_TOP_WW2END0_0", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_EE4BEG3_11", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_EE4B3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_NW4A0_10", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_LH8_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_NE4C0_12", + "CMT_TOP_MONITOR_P_10", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_NE4C0_9", + "CMT_TOP_SW4A3_8", + "CMT_TOP_SW2A1_10", + "CMT_TOP_WW2A0_6", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_LH7_12", + "CMT_TOP_WL1END2_1", + "CMT_TOP_LH8_10", + "CMT_TOP_NE4C0_0", + "CMT_TOP_IMUX29_7", + "CMT_TOP_EE4B0_4", + "CMT_TOP_WR1END3_6", + "CMT_TOP_LOGIC_OUTS_L_B6_11", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_TOP_BLOCK_OUTS_L_B3_9", + "CMT_TOP_WW4B2_2", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_LH11_4", + "CMT_TOP_LH6_6", + "CMT_TOP_LOGIC_OUTS_L_B1_12", + "CMT_TOP_NE2A1_11", + "CMT_TOP_NW2A3_7", + "CMT_TOP_WW4END0_5", + "CMT_TOP_FAN4_8", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_IMUX22_7", + "CMT_TOP_IMUX8_12", + "CMT_TOP_WR1END1_2", + "CMT_TOP_IMUX2_6", + "CMT_TOP_BYP4_8", + "CMT_TOP_LOGIC_OUTS_L_B12_9", + "CMT_TOP_SE4C3_5", + "CMT_TOP_BLOCK_OUTS_L_B2_9", + "CMT_TOP_FAN5_12", + "CMT_TOP_IMUX15_4", + "CMT_TOP_IMUX39_9", + "CMT_TOP_IMUX4_9", + "CMT_TOP_BYP5_5", + "CMT_TOP_ICLK_1", + "CMT_TOP_BYP3_12", + "CMT_TOP_WW2END1_10", + "CMT_TOP_IMUX0_1", + "CMT_TOP_BYP6_7", + "CMT_TOP_WW4B2_6", + "CMT_TOP_IMUX32_7", + "CMT_TOP_LH3_3", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_SW4A2_8", + "CMT_TOP_SE2A0_12", + "CMT_TOP_WL1END3_7", + "CMT_TOP_SW4A1_7", + "CMT_TOP_SW2A3_5", + "CMT_TOP_EE4C2_9", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_WW4END1_8", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_SW4A3_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", + "CMT_TOP_FAN1_9", + "CMT_TOP_WW4A2_2", + "CMT_TOP_IMUX28_1", + "CMT_TOP_IMUX46_4", + "CMT_TOP_WW2END3_4", + "CMT_TOP_EE4B1_5", + "CMT_TOP_EE4B0_6", + "CMT_TOP_WR1END0_11", + "CMT_TOP_SW2A0_0", + "CMT_TOP_LH3_12", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_NW4A1_0", + "CMT_TOP_WW2END0_12", + "CMT_TOP_WW4B0_7", + "CMT_TOP_IMUX33_9", + "CMT_TOP_NW4END2_6", + "CMT_TOP_CLK1_4", + "CMT_TOP_IMUX13_12", + "CMT_TOP_IMUX17_10", + "CMT_TOP_BYP5_0", + "CMT_TOP_MONITOR_N_12", + "CMT_TOP_NE4C1_8", + "CMT_TOP_WW4END1_1", + "CMT_TOP_NW4A2_11", + "CMT_TOP_IMUX37_0", + "CMT_TOP_SW2A0_12", + "CMT_TOP_WL1END3_1", + "CMT_TOP_IMUX16_8", + "CMT_TOP_IMUX39_2", + "CMT_TOP_IMUX37_7", + "CMT_TOP_IMUX16_3", + "CMT_TOP_IMUX1_2", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_TOP_IMUX6_6", + "CMT_TOP_LH1_12", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_WW4B2_4", + "CMT_TOP_ER1BEG2_2", + "CMT_TOP_IMUX11_10", + "CMT_TOP_IMUX17_7", + "CMT_TOP_CTRL0_8", + "CMT_TOP_IMUX35_9", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_IMUX29_2", + "CMT_TOP_BYP6_1", + "CMT_TOP_ER1BEG0_9", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_FAN1_4", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW2A0_5", + "CMT_TOP_NE2A1_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_TOP_NW2A0_3", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_SE2A1_5", + "CMT_TOP_LH4_9", + "CMT_TOP_NW4A1_8", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_NW4END3_2", + "CMT_TOP_IMUX39_3", + "CMT_TOP_IMUX7_12", + "CMT_TOP_CTRL0_2", + "CMT_TOP_SW4END1_10", + "CMT_TOP_NW4END0_7", + "CMT_TOP_IMUX44_9", + "CMT_TOP_SW4END0_4", + "CMT_TOP_CTRL1_2", + "CMT_TOP_WW4END2_2", + "CMT_TOP_IMUX38_10", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4C2_10", + "CMT_TOP_IMUX38_2", + "CMT_TOP_BYP3_7", + "CMT_TOP_LH3_0", + "CMT_TOP_EE4BEG3_9", + "CMT_TOP_EE4A2_12", + "CMT_TOP_NE4BEG2_6", + "CMT_TOP_ICLK_11", + "CMT_TOP_OCLK_3", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX13_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", + "CMT_TOP_IMUX11_2", + "CMT_TOP_WW4A2_10", + "CMT_TOP_SW4A0_5", + "CMT_TOP_EE4B2_3", + "CMT_TOP_IMUX9_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", + "CMT_TOP_EE2A2_3", + "CMT_TOP_WR1END3_1", + "CMT_TOP_WW2A0_0", + "CMT_TOP_WR1END0_5", + "CMT_TOP_ER1BEG2_8", + "CMT_TOP_WW4C3_10", + "CMT_TOP_NW4A0_8", + "CMT_TOP_BYP7_12", + "CMT_TOP_LOGIC_OUTS_L_B6_9", + "CMT_TOP_EE4C0_10", + "CMT_TOP_R_UPPER_T_CLKPLL5", + "CMT_TOP_WW4B2_5", + "CMT_TOP_SW2A2_12", + "CMT_TOP_IMUX41_8", + "CMT_TOP_SW2A3_8", + "CMT_TOP_SW4END1_9", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_LH4_10", + "CMT_TOP_NE4BEG0_11", + "CMT_TOP_WW4B3_6", + "CMT_TOP_NW4END3_10", + "CMT_TOP_WW4END3_8", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX33_2", + "CMT_TOP_R_CLKFBOUT2IN", + "CMT_TOP_WW2END2_8", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_WW4C0_11", + "CMT_TOP_NE2A0_7", + "CMT_TOP_SE2A0_10", + "CMT_TOP_NW2A0_12", + "CMT_TOP_BYP0_7", + "CMT_TOP_IMUX0_11", + "CMT_TOP_IMUX21_12", + "CMT_TOP_NE2A1_7", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_TOP_IMUX3_12", + "CMT_TOP_WW2A3_10", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_NW4A3_8", + "CMT_TOP_EE4A1_11", + "CMT_TOP_WW4C0_5", + "CMT_TOP_BYP4_9", + "CMT_TOP_IMUX8_7", + "CMT_TOP_NE2A0_1", + "CMT_TOP_WW4END0_0", + "CMT_TOP_FAN5_2", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_WW4C1_10", + "CMT_TOP_IMUX39_8", + "CMT_TOP_NE4C1_2", + "CMT_TOP_IMUX30_4", + "CMT_TOP_WL1END0_12", + "CMT_TOP_NE2A3_12", + "PLL_CLK_FREQ_BB1_NS", + "CMT_TOP_EE4C3_4", + "CMT_TOP_BYP1_5", + "CMT_TOP_IMUX20_12", + "CMT_TOP_IMUX10_8", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_TOP_WW4B2_12", + "CMT_TOP_NE2A2_11", + "CMT_TOP_EE4A3_11", + "CMT_TOP_IMUX43_10", + "CMT_TOP_EE2A2_10", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_IMUX44_8", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_WL1END0_3", + "CMT_PLL_PHASER_OUT_D_OCLK1X_90", + "CMT_TOP_IMUX18_8", + "CMT_TOP_IMUX19_4", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_NE4C2_10", + "CMT_TOP_NW4END3_12", + "CMT_TOP_LH10_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", + "CMT_TOP_LOGIC_OUTS_L_B10_9", + "CMT_TOP_LH7_4", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_NW4A3_5", + "CMT_PLL_PHYCTRL_SYNC_BB_UP", + "CMT_TOP_LOGIC_OUTS_L_B9_12", + "CMT_TOP_NW4END0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_12", + "CMT_TOP_IMUX29_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", + "CMT_TOP_NW2A0_6", + "CMT_TOP_BLOCK_OUTS_L_B1_12", + "CMT_TOP_SE2A2_2", + "CMT_TOP_WW4C2_7", + "CMT_TOP_IMUX37_9", + "CMT_TOP_WW4C0_4", + "CMT_TOP_BYP5_9", + "CMT_TOP_EE4BEG3_4", + "CMT_TOP_WW4A2_1", + "CMT_TOP_LH6_9", + "CMT_TOP_BYP5_12", + "CMT_TOP_SE4C2_11", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", + "CMT_TOP_LH10_3", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_WW4C3_2", + "CMT_TOP_IMUX38_5", + "CMT_TOP_IMUX8_8", + "CMT_TOP_FAN4_6", + "CMT_TOP_IMUX47_7", + "CMT_TOP_EE2A1_1", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_ER1BEG1_10", + "CMT_TOP_FAN7_8", + "CMT_TOP_FAN6_3", + "CMT_TOP_EE4B0_0", + "CMT_TOP_IMUX34_5", + "CMT_TOP_IMUX31_5", + "CMT_TOP_WW4END1_11", + "CMT_TOP_IMUX0_7", + "CMT_TOP_IMUX2_1", + "CMT_TOP_ER1BEG3_8" + ], + "pips": { + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { + "src_wire": "CMT_PLL_PHASERD_DTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO9->>CMT_TOP_LOGIC_OUTS_L_B5_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO9", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT->>CMT_TOP_R_UPPER_T_CLKPLL6": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX15_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR1": { + "src_wire": "CMT_TOP_IMUX15_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX47_10->>CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL": { + "src_wire": "CMT_TOP_IMUX47_10", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_12": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX34_12->>CMT_TOP_R_UPPER_T_PLLE2_DI10": { + "src_wire": "CMT_TOP_IMUX34_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_IN_D_ICLK->>CMT_PHASER_D_ICLK_TOIOI": { + "src_wire": "CMT_PLL_PHASER_IN_D_ICLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKIN1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "src_wire": "CMT_TOP_R_UPPER_T_CLKIN1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_12": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO1->>CMT_TOP_LOGIC_OUTS_L_B7_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX3_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR6": { + "src_wire": "CMT_TOP_IMUX3_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO10->>CMT_TOP_LOGIC_OUTS_L_B23_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO10", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX2_12->>CMT_TOP_R_UPPER_T_PLLE2_DI11": { + "src_wire": "CMT_TOP_IMUX2_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2->>CMT_TOP_R_UPPER_T_CLKPLL2": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_CLK0_1->>CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT": { + "src_wire": "CMT_TOP_CLK0_1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS->>CMT_TOP_R_UPPER_T_FREQ_BB3": { + "src_wire": "PLL_CLK_FREQ_BB3_NS", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4->>CMT_TOP_R_UPPER_T_CLKPLL4": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX44_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR4": { + "src_wire": "CMT_TOP_IMUX44_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_IN_D_ICLKDIV->>CMT_PHASER_D_ICLKDIV_TOIOI": { + "src_wire": "CMT_PLL_PHASER_IN_D_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX36_12->>CMT_TOP_R_UPPER_T_PLLE2_DI6": { + "src_wire": "CMT_TOP_IMUX36_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3->>PLLOUT_CLK_FREQ_BB_3": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX7_12->>CMT_TOP_R_UPPER_T_PLLE2_DI1": { + "src_wire": "CMT_TOP_IMUX7_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX35_12->>CMT_TOP_R_UPPER_T_PLLE2_DI8": { + "src_wire": "CMT_TOP_IMUX35_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B21_11": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5->>CMT_TOP_R_UPPER_T_CLKPLL5": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX5_12->>CMT_TOP_R_UPPER_T_PLLE2_DI5": { + "src_wire": "CMT_TOP_IMUX5_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS->>CMT_TOP_R_UPPER_T_FREQ_BB2": { + "src_wire": "PLL_CLK_FREQ_BB2_NS", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_10": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO8->>CMT_TOP_LOGIC_OUTS_L_B19_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO8", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { + "src_wire": "CMT_PLL_PHASERD_DQSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_9": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO13->>CMT_TOP_LOGIC_OUTS_L_B0_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO13", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1->>PLLOUT_CLK_FREQ_BB_1": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_12": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX47_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR0": { + "src_wire": "CMT_TOP_IMUX47_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO5->>CMT_TOP_LOGIC_OUTS_L_B2_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO5", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_CLKFBOUT2IN->CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_R_CLKFBOUT2IN", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX22_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR2": { + "src_wire": "CMT_TOP_IMUX22_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX3_12->>CMT_TOP_R_UPPER_T_PLLE2_DI9": { + "src_wire": "CMT_TOP_IMUX3_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLKDIV->>CMT_PHASER_D_OCLKDIV_TOIOI": { + "src_wire": "CMT_PLL_PHASER_OUT_D_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0->>CMT_TOP_R_UPPER_T_CLKPLL0": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO6->>CMT_TOP_LOGIC_OUTS_L_B16_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO6", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX39_12->>CMT_TOP_R_UPPER_T_PLLE2_DI0": { + "src_wire": "CMT_TOP_IMUX39_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX6_12->>CMT_TOP_R_UPPER_T_PLLE2_DI3": { + "src_wire": "CMT_TOP_IMUX6_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO15->>CMT_TOP_LOGIC_OUTS_L_B8_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO15", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B8_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3->>CMT_TOP_R_UPPER_T_CLKPLL3": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX33_12->>CMT_TOP_R_UPPER_T_PLLE2_DI12": { + "src_wire": "CMT_TOP_IMUX33_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { + "src_wire": "CMT_PLL_PHASERD_CTSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO2->>CMT_TOP_LOGIC_OUTS_L_B21_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX32_12->>CMT_TOP_R_UPPER_T_PLLE2_DI14": { + "src_wire": "CMT_TOP_IMUX32_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI14", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS->>CMT_TOP_R_UPPER_T_FREQ_BB1": { + "src_wire": "PLL_CLK_FREQ_BB1_NS", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX1_11->>CMT_TOP_R_UPPER_T_PLLE2_DEN": { + "src_wire": "CMT_TOP_IMUX1_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DEN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS0": { + "src_wire": "PLL_CLK_FREQ_BB0_NS", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS0", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO7->>CMT_TOP_LOGIC_OUTS_L_B10_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO7", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0->>PLLOUT_CLK_FREQ_BB_0": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO3->>CMT_TOP_LOGIC_OUTS_L_B15_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT->>CMT_TOP_R_UPPER_T_CLKPLL7": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO0->>CMT_TOP_LOGIC_OUTS_L_B17_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX37_12->>CMT_TOP_R_UPPER_T_PLLE2_DI4": { + "src_wire": "CMT_TOP_IMUX37_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX4_12->>CMT_TOP_R_UPPER_T_PLLE2_DI7": { + "src_wire": "CMT_TOP_IMUX4_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_11": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX35_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR5": { + "src_wire": "CMT_TOP_IMUX35_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_11": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO12->>CMT_TOP_LOGIC_OUTS_L_B22_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B22_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_9": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_12": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKIN2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "src_wire": "CMT_TOP_R_UPPER_T_CLKIN2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX1_12->>CMT_TOP_R_UPPER_T_PLLE2_DI13": { + "src_wire": "CMT_TOP_IMUX1_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI13", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO4->>CMT_TOP_LOGIC_OUTS_L_B20_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO4", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLK->>CMT_PHASER_D_OCLK_TOIOI": { + "src_wire": "CMT_PLL_PHASER_OUT_D_OCLK", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKFBIN->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_R_UPPER_T_CLKFBIN", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { + "src_wire": "CMT_PLL_PHASERD_DTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_DN<<->>CMT_PLL_PHYCTRL_SYNC_BB_UP": { + "src_wire": "CMT_PLL_PHYCTRL_SYNC_BB_DN", + "is_pseudo": "0", + "dst_wire": "CMT_PLL_PHYCTRL_SYNC_BB_UP", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_10": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX0_11->>CMT_TOP_R_UPPER_T_PLLE2_PWRDWN": { + "src_wire": "CMT_TOP_IMUX0_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "src_wire": "CMT_PLL_PHASERD_CTSBUS0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX0_12->>CMT_TOP_R_UPPER_T_PLLE2_DI15": { + "src_wire": "CMT_TOP_IMUX0_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI15", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS2": { + "src_wire": "PLL_CLK_FREQ_BB2_NS", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS2", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS1": { + "src_wire": "PLL_CLK_FREQ_BB1_NS", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS1", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1->>CMT_TOP_R_UPPER_T_CLKPLL1": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS3": { + "src_wire": "PLL_CLK_FREQ_BB3_NS", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS3", + "is_directional": "0", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX2_11->>CMT_TOP_R_UPPER_T_PLLE2_DWE": { + "src_wire": "CMT_TOP_IMUX2_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DWE", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX13_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR3": { + "src_wire": "CMT_TOP_IMUX13_11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLK1X_90->>CMT_PHASER_D_OCLK90_TOIOI": { + "src_wire": "CMT_PLL_PHASER_OUT_D_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_OCLK90_TOIOI", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_CLK1_0->>CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT": { + "src_wire": "CMT_TOP_CLK1_0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2->>PLLOUT_CLK_FREQ_BB_2": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_CLK0_0->>CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT": { + "src_wire": "CMT_TOP_CLK0_0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX38_12->>CMT_TOP_R_UPPER_T_PLLE2_DI2": { + "src_wire": "CMT_TOP_IMUX38_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS->>CMT_TOP_R_UPPER_T_FREQ_BB0": { + "src_wire": "PLL_CLK_FREQ_BB0_NS", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB0", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB3", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_11": { + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_CLK0_12->>CMT_TOP_R_UPPER_T_PLLE2_DCLK": { + "src_wire": "CMT_TOP_CLK0_12", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DCLK", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_7": { + "src_wire": "CMT_PHASER_D_OCLK90_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB2", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_9", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT->CMT_TOP_R_CLKFBOUT2IN": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_CLKFBOUT2IN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX13_10->>CMT_TOP_R_UPPER_T_PLLE2_RST": { + "src_wire": "CMT_TOP_IMUX13_10", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_RST", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { + "src_wire": "CMT_PLL_PHASERD_DQSBUS1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO14->>CMT_TOP_LOGIC_OUTS_L_B18_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO14", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_12", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB0", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO11->>CMT_TOP_LOGIC_OUTS_L_B13_12": { + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO11", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B13_12", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_DSP_L.json b/kintex7/tile_type_DSP_L.json new file mode 100644 index 0000000..568620b --- /dev/null +++ b/kintex7/tile_type_DSP_L.json @@ -0,0 +1,8474 @@ +{ + "tile_type": "DSP_L", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "DSP48", + "type": "DSP48E1", + "site_pins": { + "A17": "DSP_0_A17", + "ACIN11": "DSP_0_ACIN11", + "A22": "DSP_0_A22", + "PCIN31": "DSP_0_PCIN31", + "ACIN19": "DSP_0_ACIN19", + "INMODE0": "DSP_0_INMODE0", + "D15": "DSP_0_D15", + "P24": "DSP_0_P24", + "C38": "DSP_0_C38", + "D11": "DSP_0_D11", + "CARRYINSEL2": "DSP_0_CARRYINSEL2", + "BCIN17": "DSP_0_BCIN17", + "BCOUT2": "DSP_0_BCOUT2", + "PCOUT12": "DSP_0_PCOUT12", + "BCIN1": "DSP_0_BCIN1", + "PCIN41": "DSP_0_PCIN41", + "ACOUT29": "DSP_0_ACOUT29", + "ACIN25": "DSP_0_ACIN25", + "PCOUT6": "DSP_0_PCOUT6", + "PCIN1": "DSP_0_PCIN1", + "RSTCTRL": "DSP_0_RSTCTRL", + "C36": "DSP_0_C36", + "ACIN0": "DSP_0_ACIN0", + "PCIN26": "DSP_0_PCIN26", + "D0": "DSP_0_D0", + "PCOUT31": "DSP_0_PCOUT31", + "ACOUT3": "DSP_0_ACOUT3", + "B1": "DSP_0_B1", + "PCIN35": "DSP_0_PCIN35", + "PCOUT47": "DSP_0_PCOUT47", + "P23": "DSP_0_P23", + "ACIN21": "DSP_0_ACIN21", + "ACIN29": "DSP_0_ACIN29", + "PCOUT19": "DSP_0_PCOUT19", + "P31": "DSP_0_P31", + "P17": "DSP_0_P17", + "PCIN22": "DSP_0_PCIN22", + "PCOUT4": "DSP_0_PCOUT4", + "ACIN26": "DSP_0_ACIN26", + "C27": "DSP_0_C27", + "PCIN40": "DSP_0_PCIN40", + "C16": "DSP_0_C16", + "BCIN8": "DSP_0_BCIN8", + "PCIN27": "DSP_0_PCIN27", + "PCOUT42": "DSP_0_PCOUT42", + "C21": "DSP_0_C21", + "ACOUT28": "DSP_0_ACOUT28", + "INMODE4": "DSP_0_INMODE4", + "C24": "DSP_0_C24", + "C31": "DSP_0_C31", + "BCIN14": "DSP_0_BCIN14", + "ACIN15": "DSP_0_ACIN15", + "C35": "DSP_0_C35", + "PCOUT38": "DSP_0_PCOUT38", + "C29": "DSP_0_C29", + "P9": "DSP_0_P9", + "PCOUT37": "DSP_0_PCOUT37", + "CEB1": "DSP_0_CEB1", + "BCIN2": "DSP_0_BCIN2", + "D23": "DSP_0_D23", + "C13": "DSP_0_C13", + "P39": "DSP_0_P39", + "D19": "DSP_0_D19", + "P10": "DSP_0_P10", + "C17": "DSP_0_C17", + "C15": "DSP_0_C15", + "MULTSIGNIN": "DSP_0_MULTSIGNIN", + "P19": "DSP_0_P19", + "ACOUT22": "DSP_0_ACOUT22", + "ACIN5": "DSP_0_ACIN5", + "PCOUT3": "DSP_0_PCOUT3", + "B16": "DSP_0_B16", + "ALUMODE3": "DSP_0_ALUMODE3", + "ACIN6": "DSP_0_ACIN6", + "CEP": "DSP_0_CEP", + "ACOUT21": "DSP_0_ACOUT21", + "PCIN39": "DSP_0_PCIN39", + "BCOUT0": "DSP_0_BCOUT0", + "PCIN16": "DSP_0_PCIN16", + "PCIN46": "DSP_0_PCIN46", + "BCOUT4": "DSP_0_BCOUT4", + "C14": "DSP_0_C14", + "ACOUT15": "DSP_0_ACOUT15", + "BCOUT9": "DSP_0_BCOUT9", + "ACOUT16": "DSP_0_ACOUT16", + "PCOUT23": "DSP_0_PCOUT23", + "PCIN15": "DSP_0_PCIN15", + "PCOUT14": "DSP_0_PCOUT14", + "OPMODE0": "DSP_0_OPMODE0", + "UNDERFLOW": "DSP_0_UNDERFLOW", + "D2": "DSP_0_D2", + "ACOUT10": "DSP_0_ACOUT10", + "ACIN27": "DSP_0_ACIN27", + "PCOUT28": "DSP_0_PCOUT28", + "A21": "DSP_0_A21", + "B10": "DSP_0_B10", + "C28": "DSP_0_C28", + "PCOUT46": "DSP_0_PCOUT46", + "D1": "DSP_0_D1", + "D5": "DSP_0_D5", + "ACOUT26": "DSP_0_ACOUT26", + "P43": "DSP_0_P43", + "RSTD": "DSP_0_RSTD", + "C45": "DSP_0_C45", + "CEINMODE": "DSP_0_CEINMODE", + "RSTM": "DSP_0_RSTM", + "P26": "DSP_0_P26", + "PCIN20": "DSP_0_PCIN20", + "ACIN3": "DSP_0_ACIN3", + "PCOUT32": "DSP_0_PCOUT32", + "P1": "DSP_0_P1", + "P15": "DSP_0_P15", + "CARRYCASCOUT": "DSP_0_CARRYCASCOUT", + "B2": "DSP_0_B2", + "BCOUT12": "DSP_0_BCOUT12", + "P6": "DSP_0_P6", + "PCOUT11": "DSP_0_PCOUT11", + "PCIN7": "DSP_0_PCIN7", + "CARRYOUT3": "DSP_0_CARRYOUT3", + "PCOUT26": "DSP_0_PCOUT26", + "D6": "DSP_0_D6", + "D12": "DSP_0_D12", + "BCOUT5": "DSP_0_BCOUT5", + "RSTB": "DSP_0_RSTB", + "ALUMODE0": "DSP_0_ALUMODE0", + "PCIN30": "DSP_0_PCIN30", + "A28": "DSP_0_A28", + "P8": "DSP_0_P8", + "CEA1": "DSP_0_CEA1", + "C0": "DSP_0_C0", + "P40": "DSP_0_P40", + "CEM": "DSP_0_CEM", + "PCIN18": "DSP_0_PCIN18", + "PCOUT43": "DSP_0_PCOUT43", + "PCOUT33": "DSP_0_PCOUT33", + "A1": "DSP_0_A1", + "RSTC": "DSP_0_RSTC", + "PCIN3": "DSP_0_PCIN3", + "PCOUT25": "DSP_0_PCOUT25", + "D9": "DSP_0_D9", + "PCIN14": "DSP_0_PCIN14", + "CED": "DSP_0_CED", + "C8": "DSP_0_C8", + "RSTALLCARRYIN": "DSP_0_RSTALLCARRYIN", + "C3": "DSP_0_C3", + "ACOUT13": "DSP_0_ACOUT13", + "CEAD": "DSP_0_CEAD", + "A16": "DSP_0_A16", + "C10": "DSP_0_C10", + "ACIN10": "DSP_0_ACIN10", + "PCOUT20": "DSP_0_PCOUT20", + "PCIN34": "DSP_0_PCIN34", + "C32": "DSP_0_C32", + "D16": "DSP_0_D16", + "OVERFLOW": "DSP_0_OVERFLOW", + "ACIN18": "DSP_0_ACIN18", + "ACIN8": "DSP_0_ACIN8", + "D18": "DSP_0_D18", + "PCIN25": "DSP_0_PCIN25", + "P42": "DSP_0_P42", + "CARRYINSEL0": "DSP_0_CARRYINSEL0", + "ACIN20": "DSP_0_ACIN20", + "A3": "DSP_0_A3", + "BCIN0": "DSP_0_BCIN0", + "CARRYINSEL1": "DSP_0_CARRYINSEL1", + "PCIN8": "DSP_0_PCIN8", + "BCIN9": "DSP_0_BCIN9", + "P16": "DSP_0_P16", + "ACOUT18": "DSP_0_ACOUT18", + "PCIN38": "DSP_0_PCIN38", + "CARRYOUT0": "DSP_0_CARRYOUT0", + "PCOUT17": "DSP_0_PCOUT17", + "B17": "DSP_0_B17", + "PCIN42": "DSP_0_PCIN42", + "PCIN5": "DSP_0_PCIN5", + "D24": "DSP_0_D24", + "P36": "DSP_0_P36", + "C9": "DSP_0_C9", + "ACOUT1": "DSP_0_ACOUT1", + "B7": "DSP_0_B7", + "MULTSIGNOUT": "DSP_0_MULTSIGNOUT", + "PCOUT0": "DSP_0_PCOUT0", + "C41": "DSP_0_C41", + "A25": "DSP_0_A25", + "PCIN24": "DSP_0_PCIN24", + "C37": "DSP_0_C37", + "C39": "DSP_0_C39", + "ACIN16": "DSP_0_ACIN16", + "P3": "DSP_0_P3", + "B0": "DSP_0_B0", + "PCOUT2": "DSP_0_PCOUT2", + "C33": "DSP_0_C33", + "OPMODE4": "DSP_0_OPMODE4", + "PCIN37": "DSP_0_PCIN37", + "CEALUMODE": "DSP_0_CEALUMODE", + "C20": "DSP_0_C20", + "ACOUT11": "DSP_0_ACOUT11", + "B12": "DSP_0_B12", + "PCIN11": "DSP_0_PCIN11", + "ACOUT14": "DSP_0_ACOUT14", + "ACOUT23": "DSP_0_ACOUT23", + "PCOUT1": "DSP_0_PCOUT1", + "P47": "DSP_0_P47", + "P30": "DSP_0_P30", + "PCIN29": "DSP_0_PCIN29", + "ACOUT25": "DSP_0_ACOUT25", + "PCOUT39": "DSP_0_PCOUT39", + "B5": "DSP_0_B5", + "A27": "DSP_0_A27", + "CEB2": "DSP_0_CEB2", + "PCIN45": "DSP_0_PCIN45", + "P25": "DSP_0_P25", + "RSTALUMODE": "DSP_0_RSTALUMODE", + "PCIN36": "DSP_0_PCIN36", + "OPMODE2": "DSP_0_OPMODE2", + "BCOUT1": "DSP_0_BCOUT1", + "D22": "DSP_0_D22", + "PCOUT8": "DSP_0_PCOUT8", + "ACIN1": "DSP_0_ACIN1", + "C43": "DSP_0_C43", + "INMODE2": "DSP_0_INMODE2", + "A2": "DSP_0_A2", + "PCOUT45": "DSP_0_PCOUT45", + "PATTERNDETECT": "DSP_0_PATTERNDETECT", + "A29": "DSP_0_A29", + "RSTA": "DSP_0_RSTA", + "ACOUT17": "DSP_0_ACOUT17", + "A14": "DSP_0_A14", + "CARRYOUT2": "DSP_0_CARRYOUT2", + "A12": "DSP_0_A12", + "BCIN4": "DSP_0_BCIN4", + "PCOUT40": "DSP_0_PCOUT40", + "CEA2": "DSP_0_CEA2", + "C30": "DSP_0_C30", + "P2": "DSP_0_P2", + "B14": "DSP_0_B14", + "P5": "DSP_0_P5", + "P18": "DSP_0_P18", + "ACOUT4": "DSP_0_ACOUT4", + "A0": "DSP_0_A0", + "ACOUT0": "DSP_0_ACOUT0", + "BCIN6": "DSP_0_BCIN6", + "BCIN13": "DSP_0_BCIN13", + "C40": "DSP_0_C40", + "P29": "DSP_0_P29", + "A4": "DSP_0_A4", + "PCOUT21": "DSP_0_PCOUT21", + "ALUMODE1": "DSP_0_ALUMODE1", + "C22": "DSP_0_C22", + "BCOUT8": "DSP_0_BCOUT8", + "P14": "DSP_0_P14", + "OPMODE6": "DSP_0_OPMODE6", + "PCOUT22": "DSP_0_PCOUT22", + "BCIN16": "DSP_0_BCIN16", + "ACOUT5": "DSP_0_ACOUT5", + "ACIN14": "DSP_0_ACIN14", + "D8": "DSP_0_D8", + "RSTINMODE": "DSP_0_RSTINMODE", + "PCOUT13": "DSP_0_PCOUT13", + "ALUMODE2": "DSP_0_ALUMODE2", + "P45": "DSP_0_P45", + "BCIN7": "DSP_0_BCIN7", + "ACOUT9": "DSP_0_ACOUT9", + "P38": "DSP_0_P38", + "PCIN28": "DSP_0_PCIN28", + "C26": "DSP_0_C26", + "P21": "DSP_0_P21", + "ACIN12": "DSP_0_ACIN12", + "ACOUT20": "DSP_0_ACOUT20", + "BCOUT16": "DSP_0_BCOUT16", + "A8": "DSP_0_A8", + "C47": "DSP_0_C47", + "PCIN44": "DSP_0_PCIN44", + "A23": "DSP_0_A23", + "C34": "DSP_0_C34", + "C12": "DSP_0_C12", + "P4": "DSP_0_P4", + "OPMODE1": "DSP_0_OPMODE1", + "B13": "DSP_0_B13", + "CEC": "DSP_0_CEC", + "A26": "DSP_0_A26", + "PCIN9": "DSP_0_PCIN9", + "PCIN32": "DSP_0_PCIN32", + "D7": "DSP_0_D7", + "PCOUT27": "DSP_0_PCOUT27", + "P34": "DSP_0_P34", + "BCOUT6": "DSP_0_BCOUT6", + "BCIN15": "DSP_0_BCIN15", + "PCIN10": "DSP_0_PCIN10", + "PCIN0": "DSP_0_PCIN0", + "BCOUT14": "DSP_0_BCOUT14", + "CARRYIN": "DSP_0_CARRYIN", + "PCIN43": "DSP_0_PCIN43", + "D21": "DSP_0_D21", + "BCOUT17": "DSP_0_BCOUT17", + "PCIN13": "DSP_0_PCIN13", + "A9": "DSP_0_A9", + "PCIN6": "DSP_0_PCIN6", + "CLK": "DSP_0_CLK", + "PCIN4": "DSP_0_PCIN4", + "C25": "DSP_0_C25", + "CECARRYIN": "DSP_0_CECARRYIN", + "BCIN5": "DSP_0_BCIN5", + "C19": "DSP_0_C19", + "P13": "DSP_0_P13", + "INMODE1": "DSP_0_INMODE1", + "PCIN23": "DSP_0_PCIN23", + "P44": "DSP_0_P44", + "B15": "DSP_0_B15", + "A15": "DSP_0_A15", + "BCOUT11": "DSP_0_BCOUT11", + "A18": "DSP_0_A18", + "P0": "DSP_0_P0", + "C7": "DSP_0_C7", + "ACOUT2": "DSP_0_ACOUT2", + "ACIN7": "DSP_0_ACIN7", + "D20": "DSP_0_D20", + "D13": "DSP_0_D13", + "A19": "DSP_0_A19", + "PCOUT44": "DSP_0_PCOUT44", + "BCOUT10": "DSP_0_BCOUT10", + "CECTRL": "DSP_0_CECTRL", + "PCIN33": "DSP_0_PCIN33", + "D10": "DSP_0_D10", + "BCOUT13": "DSP_0_BCOUT13", + "B11": "DSP_0_B11", + "ACOUT8": "DSP_0_ACOUT8", + "INMODE3": "DSP_0_INMODE3", + "B6": "DSP_0_B6", + "OPMODE3": "DSP_0_OPMODE3", + "ACIN17": "DSP_0_ACIN17", + "P28": "DSP_0_P28", + "P20": "DSP_0_P20", + "C4": "DSP_0_C4", + "B8": "DSP_0_B8", + "B4": "DSP_0_B4", + "A6": "DSP_0_A6", + "P41": "DSP_0_P41", + "ACIN4": "DSP_0_ACIN4", + "PCOUT41": "DSP_0_PCOUT41", + "D4": "DSP_0_D4", + "D14": "DSP_0_D14", + "ACOUT27": "DSP_0_ACOUT27", + "PCOUT5": "DSP_0_PCOUT5", + "ACOUT24": "DSP_0_ACOUT24", + "C11": "DSP_0_C11", + "PCOUT34": "DSP_0_PCOUT34", + "C5": "DSP_0_C5", + "A7": "DSP_0_A7", + "ACIN13": "DSP_0_ACIN13", + "ACIN28": "DSP_0_ACIN28", + "P11": "DSP_0_P11", + "A11": "DSP_0_A11", + "PCOUT30": "DSP_0_PCOUT30", + "C23": "DSP_0_C23", + "P32": "DSP_0_P32", + "D3": "DSP_0_D3", + "ACOUT6": "DSP_0_ACOUT6", + "P22": "DSP_0_P22", + "C46": "DSP_0_C46", + "CARRYCASCIN": "DSP_0_CARRYCASCIN", + "P35": "DSP_0_P35", + "PCIN17": "DSP_0_PCIN17", + "PCIN21": "DSP_0_PCIN21", + "BCOUT7": "DSP_0_BCOUT7", + "PCOUT15": "DSP_0_PCOUT15", + "A20": "DSP_0_A20", + "C42": "DSP_0_C42", + "PCOUT18": "DSP_0_PCOUT18", + "PCOUT10": "DSP_0_PCOUT10", + "BCIN10": "DSP_0_BCIN10", + "ACIN22": "DSP_0_ACIN22", + "B9": "DSP_0_B9", + "A10": "DSP_0_A10", + "D17": "DSP_0_D17", + "ACIN2": "DSP_0_ACIN2", + "A13": "DSP_0_A13", + "PCOUT29": "DSP_0_PCOUT29", + "C6": "DSP_0_C6", + "PCIN2": "DSP_0_PCIN2", + "PCOUT35": "DSP_0_PCOUT35", + "ACOUT19": "DSP_0_ACOUT19", + "PCOUT7": "DSP_0_PCOUT7", + "C18": "DSP_0_C18", + "P7": "DSP_0_P7", + "BCIN3": "DSP_0_BCIN3", + "PCOUT16": "DSP_0_PCOUT16", + "C2": "DSP_0_C2", + "P46": "DSP_0_P46", + "ACOUT7": "DSP_0_ACOUT7", + "PCOUT36": "DSP_0_PCOUT36", + "A5": "DSP_0_A5", + "ACIN9": "DSP_0_ACIN9", + "A24": "DSP_0_A24", + "P27": "DSP_0_P27", + "ACIN24": "DSP_0_ACIN24", + "CARRYOUT1": "DSP_0_CARRYOUT1", + "ACOUT12": "DSP_0_ACOUT12", + "BCOUT15": "DSP_0_BCOUT15", + "B3": "DSP_0_B3", + "P33": "DSP_0_P33", + "PCIN47": "DSP_0_PCIN47", + "PATTERNBDETECT": "DSP_0_PATTERNBDETECT", + "P37": "DSP_0_P37", + "P12": "DSP_0_P12", + "BCIN12": "DSP_0_BCIN12", + "RSTP": "DSP_0_RSTP", + "BCOUT3": "DSP_0_BCOUT3", + "OPMODE5": "DSP_0_OPMODE5", + "C44": "DSP_0_C44", + "BCIN11": "DSP_0_BCIN11", + "PCIN12": "DSP_0_PCIN12", + "C1": "DSP_0_C1", + "PCOUT24": "DSP_0_PCOUT24", + "PCIN19": "DSP_0_PCIN19", + "PCOUT9": "DSP_0_PCOUT9", + "ACIN23": "DSP_0_ACIN23" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "DSP48", + "type": "DSP48E1", + "site_pins": { + "A17": "DSP_1_A17", + "ACIN11": "DSP_1_ACIN11", + "A22": "DSP_1_A22", + "PCIN31": "DSP_1_PCIN31", + "ACIN19": "DSP_1_ACIN19", + "INMODE0": "DSP_1_INMODE0", + "D15": "DSP_1_D15", + "P24": "DSP_1_P24", + "C38": "DSP_1_C38", + "D11": "DSP_1_D11", + "CARRYINSEL2": "DSP_1_CARRYINSEL2", + "BCIN17": "DSP_1_BCIN17", + "BCOUT2": "DSP_1_BCOUT2", + "PCOUT12": "DSP_1_PCOUT12", + "BCIN1": "DSP_1_BCIN1", + "PCIN41": "DSP_1_PCIN41", + "ACOUT29": "DSP_1_ACOUT29", + "ACIN25": "DSP_1_ACIN25", + "PCOUT6": "DSP_1_PCOUT6", + "PCIN1": "DSP_1_PCIN1", + "RSTCTRL": "DSP_1_RSTCTRL", + "C36": "DSP_1_C36", + "ACIN0": "DSP_1_ACIN0", + "PCIN26": "DSP_1_PCIN26", + "D0": "DSP_1_D0", + "PCOUT31": "DSP_1_PCOUT31", + "ACOUT3": "DSP_1_ACOUT3", + "B1": "DSP_1_B1", + "PCIN35": "DSP_1_PCIN35", + "PCOUT47": "DSP_1_PCOUT47", + "P23": "DSP_1_P23", + "ACIN21": "DSP_1_ACIN21", + "ACIN29": "DSP_1_ACIN29", + "PCOUT19": "DSP_1_PCOUT19", + "P31": "DSP_1_P31", + "P17": "DSP_1_P17", + "PCIN22": "DSP_1_PCIN22", + "PCOUT4": "DSP_1_PCOUT4", + "ACIN26": "DSP_1_ACIN26", + "C27": "DSP_1_C27", + "PCIN40": "DSP_1_PCIN40", + "C16": "DSP_1_C16", + "BCIN8": "DSP_1_BCIN8", + "PCIN27": "DSP_1_PCIN27", + "PCOUT42": "DSP_1_PCOUT42", + "C21": "DSP_1_C21", + "ACOUT28": "DSP_1_ACOUT28", + "INMODE4": "DSP_1_INMODE4", + "C24": "DSP_1_C24", + "C31": "DSP_1_C31", + "BCIN14": "DSP_1_BCIN14", + "ACIN15": "DSP_1_ACIN15", + "C35": "DSP_1_C35", + "PCOUT38": "DSP_1_PCOUT38", + "C29": "DSP_1_C29", + "P9": "DSP_1_P9", + "PCOUT37": "DSP_1_PCOUT37", + "CEB1": "DSP_1_CEB1", + "BCIN2": "DSP_1_BCIN2", + "D23": "DSP_1_D23", + "C13": "DSP_1_C13", + "P39": "DSP_1_P39", + "D19": "DSP_1_D19", + "P10": "DSP_1_P10", + "C17": "DSP_1_C17", + "C15": "DSP_1_C15", + "MULTSIGNIN": "DSP_1_MULTSIGNIN", + "P19": "DSP_1_P19", + "ACOUT22": "DSP_1_ACOUT22", + "ACIN5": "DSP_1_ACIN5", + "PCOUT3": "DSP_1_PCOUT3", + "B16": "DSP_1_B16", + "ALUMODE3": "DSP_1_ALUMODE3", + "ACIN6": "DSP_1_ACIN6", + "CEP": "DSP_1_CEP", + "ACOUT21": "DSP_1_ACOUT21", + "PCIN39": "DSP_1_PCIN39", + "BCOUT0": "DSP_1_BCOUT0", + "PCIN16": "DSP_1_PCIN16", + "PCIN46": "DSP_1_PCIN46", + "BCOUT4": "DSP_1_BCOUT4", + "C14": "DSP_1_C14", + "ACOUT15": "DSP_1_ACOUT15", + "BCOUT9": "DSP_1_BCOUT9", + "ACOUT16": "DSP_1_ACOUT16", + "PCOUT23": "DSP_1_PCOUT23", + "PCIN15": "DSP_1_PCIN15", + "PCOUT14": "DSP_1_PCOUT14", + "OPMODE0": "DSP_1_OPMODE0", + "UNDERFLOW": "DSP_1_UNDERFLOW", + "D2": "DSP_1_D2", + "ACOUT10": "DSP_1_ACOUT10", + "ACIN27": "DSP_1_ACIN27", + "PCOUT28": "DSP_1_PCOUT28", + "A21": "DSP_1_A21", + "B10": "DSP_1_B10", + "C28": "DSP_1_C28", + "PCOUT46": "DSP_1_PCOUT46", + "D1": "DSP_1_D1", + "D5": "DSP_1_D5", + "ACOUT26": "DSP_1_ACOUT26", + "P43": "DSP_1_P43", + "RSTD": "DSP_1_RSTD", + "C45": "DSP_1_C45", + "CEINMODE": "DSP_1_CEINMODE", + "RSTM": "DSP_1_RSTM", + "P26": "DSP_1_P26", + "PCIN20": "DSP_1_PCIN20", + "ACIN3": "DSP_1_ACIN3", + "PCOUT32": "DSP_1_PCOUT32", + "P1": "DSP_1_P1", + "P15": "DSP_1_P15", + "CARRYCASCOUT": "DSP_1_CARRYCASCOUT", + "B2": "DSP_1_B2", + "BCOUT12": "DSP_1_BCOUT12", + "P6": "DSP_1_P6", + "PCOUT11": "DSP_1_PCOUT11", + "PCIN7": "DSP_1_PCIN7", + "CARRYOUT3": "DSP_1_CARRYOUT3", + "PCOUT26": "DSP_1_PCOUT26", + "D6": "DSP_1_D6", + "D12": "DSP_1_D12", + "BCOUT5": "DSP_1_BCOUT5", + "RSTB": "DSP_1_RSTB", + "ALUMODE0": "DSP_1_ALUMODE0", + "PCIN30": "DSP_1_PCIN30", + "A28": "DSP_1_A28", + "P8": "DSP_1_P8", + "CEA1": "DSP_1_CEA1", + "C0": "DSP_1_C0", + "P40": "DSP_1_P40", + "CEM": "DSP_1_CEM", + "PCIN18": "DSP_1_PCIN18", + "PCOUT43": "DSP_1_PCOUT43", + "PCOUT33": "DSP_1_PCOUT33", + "A1": "DSP_1_A1", + "RSTC": "DSP_1_RSTC", + "PCIN3": "DSP_1_PCIN3", + "PCOUT25": "DSP_1_PCOUT25", + "D9": "DSP_1_D9", + "PCIN14": "DSP_1_PCIN14", + "CED": "DSP_1_CED", + "C8": "DSP_1_C8", + "RSTALLCARRYIN": "DSP_1_RSTALLCARRYIN", + "C3": "DSP_1_C3", + "ACOUT13": "DSP_1_ACOUT13", + "CEAD": "DSP_1_CEAD", + "A16": "DSP_1_A16", + "C10": "DSP_1_C10", + "ACIN10": "DSP_1_ACIN10", + "PCOUT20": "DSP_1_PCOUT20", + "PCIN34": "DSP_1_PCIN34", + "C32": "DSP_1_C32", + "D16": "DSP_1_D16", + "OVERFLOW": "DSP_1_OVERFLOW", + "ACIN18": "DSP_1_ACIN18", + "ACIN8": "DSP_1_ACIN8", + "D18": "DSP_1_D18", + "PCIN25": "DSP_1_PCIN25", + "P42": "DSP_1_P42", + "CARRYINSEL0": "DSP_1_CARRYINSEL0", + "ACIN20": "DSP_1_ACIN20", + "A3": "DSP_1_A3", + "BCIN0": "DSP_1_BCIN0", + "CARRYINSEL1": "DSP_1_CARRYINSEL1", + "PCIN8": "DSP_1_PCIN8", + "BCIN9": "DSP_1_BCIN9", + "P16": "DSP_1_P16", + "ACOUT18": "DSP_1_ACOUT18", + "PCIN38": "DSP_1_PCIN38", + "CARRYOUT0": "DSP_1_CARRYOUT0", + "PCOUT17": "DSP_1_PCOUT17", + "B17": "DSP_1_B17", + "PCIN42": "DSP_1_PCIN42", + "PCIN5": "DSP_1_PCIN5", + "D24": "DSP_1_D24", + "P36": "DSP_1_P36", + "C9": "DSP_1_C9", + "ACOUT1": "DSP_1_ACOUT1", + "B7": "DSP_1_B7", + "MULTSIGNOUT": "DSP_1_MULTSIGNOUT", + "PCOUT0": "DSP_1_PCOUT0", + "C41": "DSP_1_C41", + "A25": "DSP_1_A25", + "PCIN24": "DSP_1_PCIN24", + "C37": "DSP_1_C37", + "C39": "DSP_1_C39", + "ACIN16": "DSP_1_ACIN16", + "P3": "DSP_1_P3", + "B0": "DSP_1_B0", + "PCOUT2": "DSP_1_PCOUT2", + "C33": "DSP_1_C33", + "OPMODE4": "DSP_1_OPMODE4", + "PCIN37": "DSP_1_PCIN37", + "CEALUMODE": "DSP_1_CEALUMODE", + "C20": "DSP_1_C20", + "ACOUT11": "DSP_1_ACOUT11", + "B12": "DSP_1_B12", + "PCIN11": "DSP_1_PCIN11", + "ACOUT14": "DSP_1_ACOUT14", + "ACOUT23": "DSP_1_ACOUT23", + "PCOUT1": "DSP_1_PCOUT1", + "P47": "DSP_1_P47", + "P30": "DSP_1_P30", + "PCIN29": "DSP_1_PCIN29", + "ACOUT25": "DSP_1_ACOUT25", + "PCOUT39": "DSP_1_PCOUT39", + "B5": "DSP_1_B5", + "A27": "DSP_1_A27", + "CEB2": "DSP_1_CEB2", + "PCIN45": "DSP_1_PCIN45", + "P25": "DSP_1_P25", + "RSTALUMODE": "DSP_1_RSTALUMODE", + "PCIN36": "DSP_1_PCIN36", + "OPMODE2": "DSP_1_OPMODE2", + "BCOUT1": "DSP_1_BCOUT1", + "D22": "DSP_1_D22", + "PCOUT8": "DSP_1_PCOUT8", + "ACIN1": "DSP_1_ACIN1", + "C43": "DSP_1_C43", + "INMODE2": "DSP_1_INMODE2", + "A2": "DSP_1_A2", + "PCOUT45": "DSP_1_PCOUT45", + "PATTERNDETECT": "DSP_1_PATTERNDETECT", + "A29": "DSP_1_A29", + "RSTA": "DSP_1_RSTA", + "ACOUT17": "DSP_1_ACOUT17", + "A14": "DSP_1_A14", + "CARRYOUT2": "DSP_1_CARRYOUT2", + "A12": "DSP_1_A12", + "BCIN4": "DSP_1_BCIN4", + "PCOUT40": "DSP_1_PCOUT40", + "CEA2": "DSP_1_CEA2", + "C30": "DSP_1_C30", + "P2": "DSP_1_P2", + "B14": "DSP_1_B14", + "P5": "DSP_1_P5", + "P18": "DSP_1_P18", + "ACOUT4": "DSP_1_ACOUT4", + "A0": "DSP_1_A0", + "ACOUT0": "DSP_1_ACOUT0", + "BCIN6": "DSP_1_BCIN6", + "BCIN13": "DSP_1_BCIN13", + "C40": "DSP_1_C40", + "P29": "DSP_1_P29", + "A4": "DSP_1_A4", + "PCOUT21": "DSP_1_PCOUT21", + "ALUMODE1": "DSP_1_ALUMODE1", + "C22": "DSP_1_C22", + "BCOUT8": "DSP_1_BCOUT8", + "P14": "DSP_1_P14", + "OPMODE6": "DSP_1_OPMODE6", + "PCOUT22": "DSP_1_PCOUT22", + "BCIN16": "DSP_1_BCIN16", + "ACOUT5": "DSP_1_ACOUT5", + "ACIN14": "DSP_1_ACIN14", + "D8": "DSP_1_D8", + "RSTINMODE": "DSP_1_RSTINMODE", + "PCOUT13": "DSP_1_PCOUT13", + "ALUMODE2": "DSP_1_ALUMODE2", + "P45": "DSP_1_P45", + "BCIN7": "DSP_1_BCIN7", + "ACOUT9": "DSP_1_ACOUT9", + "P38": "DSP_1_P38", + "PCIN28": "DSP_1_PCIN28", + "C26": "DSP_1_C26", + "P21": "DSP_1_P21", + "ACIN12": "DSP_1_ACIN12", + "ACOUT20": "DSP_1_ACOUT20", + "BCOUT16": "DSP_1_BCOUT16", + "A8": "DSP_1_A8", + "C47": "DSP_1_C47", + "PCIN44": "DSP_1_PCIN44", + "A23": "DSP_1_A23", + "C34": "DSP_1_C34", + "C12": "DSP_1_C12", + "P4": "DSP_1_P4", + "OPMODE1": "DSP_1_OPMODE1", + "B13": "DSP_1_B13", + "CEC": "DSP_1_CEC", + "A26": "DSP_1_A26", + "PCIN9": "DSP_1_PCIN9", + "PCIN32": "DSP_1_PCIN32", + "D7": "DSP_1_D7", + "PCOUT27": "DSP_1_PCOUT27", + "P34": "DSP_1_P34", + "BCOUT6": "DSP_1_BCOUT6", + "BCIN15": "DSP_1_BCIN15", + "PCIN10": "DSP_1_PCIN10", + "PCIN0": "DSP_1_PCIN0", + "BCOUT14": "DSP_1_BCOUT14", + "CARRYIN": "DSP_1_CARRYIN", + "PCIN43": "DSP_1_PCIN43", + "D21": "DSP_1_D21", + "BCOUT17": "DSP_1_BCOUT17", + "PCIN13": "DSP_1_PCIN13", + "A9": "DSP_1_A9", + "PCIN6": "DSP_1_PCIN6", + "CLK": "DSP_1_CLK", + "PCIN4": "DSP_1_PCIN4", + "C25": "DSP_1_C25", + "CECARRYIN": "DSP_1_CECARRYIN", + "BCIN5": "DSP_1_BCIN5", + "C19": "DSP_1_C19", + "P13": "DSP_1_P13", + "INMODE1": "DSP_1_INMODE1", + "PCIN23": "DSP_1_PCIN23", + "P44": "DSP_1_P44", + "B15": "DSP_1_B15", + "A15": "DSP_1_A15", + "BCOUT11": "DSP_1_BCOUT11", + "A18": "DSP_1_A18", + "P0": "DSP_1_P0", + "C7": "DSP_1_C7", + "ACOUT2": "DSP_1_ACOUT2", + "ACIN7": "DSP_1_ACIN7", + "D20": "DSP_1_D20", + "D13": "DSP_1_D13", + "A19": "DSP_1_A19", + "PCOUT44": "DSP_1_PCOUT44", + "BCOUT10": "DSP_1_BCOUT10", + "CECTRL": "DSP_1_CECTRL", + "PCIN33": "DSP_1_PCIN33", + "D10": "DSP_1_D10", + "BCOUT13": "DSP_1_BCOUT13", + "B11": "DSP_1_B11", + "ACOUT8": "DSP_1_ACOUT8", + "INMODE3": "DSP_1_INMODE3", + "B6": "DSP_1_B6", + "OPMODE3": "DSP_1_OPMODE3", + "ACIN17": "DSP_1_ACIN17", + "P28": "DSP_1_P28", + "P20": "DSP_1_P20", + "C4": "DSP_1_C4", + "B8": "DSP_1_B8", + "B4": "DSP_1_B4", + "A6": "DSP_1_A6", + "P41": "DSP_1_P41", + "ACIN4": "DSP_1_ACIN4", + "PCOUT41": "DSP_1_PCOUT41", + "D4": "DSP_1_D4", + "D14": "DSP_1_D14", + "ACOUT27": "DSP_1_ACOUT27", + "PCOUT5": "DSP_1_PCOUT5", + "ACOUT24": "DSP_1_ACOUT24", + "C11": "DSP_1_C11", + "PCOUT34": "DSP_1_PCOUT34", + "C5": "DSP_1_C5", + "A7": "DSP_1_A7", + "ACIN13": "DSP_1_ACIN13", + "ACIN28": "DSP_1_ACIN28", + "P11": "DSP_1_P11", + "A11": "DSP_1_A11", + "PCOUT30": "DSP_1_PCOUT30", + "C23": "DSP_1_C23", + "P32": "DSP_1_P32", + "D3": "DSP_1_D3", + "ACOUT6": "DSP_1_ACOUT6", + "P22": "DSP_1_P22", + "C46": "DSP_1_C46", + "CARRYCASCIN": "DSP_1_CARRYCASCIN", + "P35": "DSP_1_P35", + "PCIN17": "DSP_1_PCIN17", + "PCIN21": "DSP_1_PCIN21", + "BCOUT7": "DSP_1_BCOUT7", + "PCOUT15": "DSP_1_PCOUT15", + "A20": "DSP_1_A20", + "C42": "DSP_1_C42", + "PCOUT18": "DSP_1_PCOUT18", + "PCOUT10": "DSP_1_PCOUT10", + "BCIN10": "DSP_1_BCIN10", + "ACIN22": "DSP_1_ACIN22", + "B9": "DSP_1_B9", + "A10": "DSP_1_A10", + "D17": "DSP_1_D17", + "ACIN2": "DSP_1_ACIN2", + "A13": "DSP_1_A13", + "PCOUT29": "DSP_1_PCOUT29", + "C6": "DSP_1_C6", + "PCIN2": "DSP_1_PCIN2", + "PCOUT35": "DSP_1_PCOUT35", + "ACOUT19": "DSP_1_ACOUT19", + "PCOUT7": "DSP_1_PCOUT7", + "C18": "DSP_1_C18", + "P7": "DSP_1_P7", + "BCIN3": "DSP_1_BCIN3", + "PCOUT16": "DSP_1_PCOUT16", + "C2": "DSP_1_C2", + "P46": "DSP_1_P46", + "ACOUT7": "DSP_1_ACOUT7", + "PCOUT36": "DSP_1_PCOUT36", + "A5": "DSP_1_A5", + "ACIN9": "DSP_1_ACIN9", + "A24": "DSP_1_A24", + "P27": "DSP_1_P27", + "ACIN24": "DSP_1_ACIN24", + "CARRYOUT1": "DSP_1_CARRYOUT1", + "ACOUT12": "DSP_1_ACOUT12", + "BCOUT15": "DSP_1_BCOUT15", + "B3": "DSP_1_B3", + "P33": "DSP_1_P33", + "PCIN47": "DSP_1_PCIN47", + "PATTERNBDETECT": "DSP_1_PATTERNBDETECT", + "P37": "DSP_1_P37", + "P12": "DSP_1_P12", + "BCIN12": "DSP_1_BCIN12", + "RSTP": "DSP_1_RSTP", + "BCOUT3": "DSP_1_BCOUT3", + "OPMODE5": "DSP_1_OPMODE5", + "C44": "DSP_1_C44", + "BCIN11": "DSP_1_BCIN11", + "PCIN12": "DSP_1_PCIN12", + "C1": "DSP_1_C1", + "PCOUT24": "DSP_1_PCOUT24", + "PCIN19": "DSP_1_PCIN19", + "PCOUT9": "DSP_1_PCOUT9", + "ACIN23": "DSP_1_ACIN23" + }, + "x_coord": 0 + }, + { + "y_coord": 117, + "name": "X14Y117", + "prefix": "TIEOFF", + "type": "TIEOFF", + "site_pins": { + "HARD0": "DSP_GND_L", + "HARD1": "DSP_VCC_L" + }, + "x_coord": 14 + } + ], + "wires": [ + "DSP_1_P44", + "DSP_BYP6_4", + "DSP_PCOUT37", + "DSP_BYP7_4", + "DSP_MONITOR_N_3", + "DSP_BCOUT13", + "DSP_0_D7", + "DSP_1_BCIN6", + "DSP_0_PCIN5", + "DSP_0_PCOUT45", + "DSP_0_C16", + "DSP_MONITOR_P_1", + "DSP_1_MULTSIGNOUT", + "DSP_SE4BEG0_4", + "DSP_1_PCOUT3", + "DSP_0_BCIN14", + "DSP_LOGIC_OUTS_B5_0", + "DSP_0_PCOUT41", + "DSP_WW2END0_3", + "DSP_0_P42", + "DSP_LOGIC_OUTS_B11_2", + "DSP_IMUX41_0", + "DSP_0_UNDERFLOW", + "DSP_SW4END2_4", + "DSP_LOGIC_OUTS_B16_1", + "DSP_1_C47", + "DSP_LOGIC_OUTS_B7_0", + "DSP_0_ACIN1", + "DSP_EE4BEG0_2", + "DSP_0_ACIN15", + "DSP_1_C45", + "DSP_1_P41", + "DSP_CLK0_4", + "DSP_1_C16", + "DSP_1_BCIN1", + "DSP_1_ACIN10", + "DSP_NW4A3_2", + "DSP_1_P18", + "DSP_PCOUT39", + "DSP_0_PCOUT3", + "DSP_EE2BEG3_4", + "DSP_IMUX26_0", + "DSP_EE4B3_0", + "DSP_1_P10", + "DSP_0_OPMODE4", + "DSP_1_PCOUT43", + "DSP_0_PCIN7", + "DSP_0_PCOUT24", + "DSP_BCOUT11", + "DSP_0_C7", + "DSP_IMUX5_0", + "DSP_0_P1", + "DSP_EE4C0_3", + "DSP_IMUX14_1", + "DSP_1_PCOUT28", + "DSP_EE4BEG1_4", + "DSP_LOGIC_OUTS_B12_1", + "DSP_1_BCOUT8", + "DSP_EE4B3_3", + "DSP_ER1BEG0_4", + "DSP_0_PCIN46", + "DSP_0_PCIN1", + "DSP_0_C1", + "DSP_FAN3_0", + "DSP_WW2A2_2", + "DSP_0_P38", + "DSP_LOGIC_OUTS_B6_1", + "DSP_1_PCOUT19", + "DSP_IMUX23_2", + "DSP_0_D11", + "DSP_LOGIC_OUTS_B21_2", + "DSP_PCOUT24", + "DSP_NW2A2_4", + "DSP_SE2A1_4", + "DSP_IMUX1_3", + "DSP_0_PCOUT43", + "DSP_WR1END1_2", + "DSP_IMUX24_1", + "DSP_IMUX47_4", + "DSP_1_PCOUT10", + "DSP_0_ACIN20", + "DSP_WW4B2_4", + "DSP_IMUX37_2", + "DSP_ER1BEG1_0", + "DSP_1_D20", + "DSP_1_INMODE0", + "DSP_IMUX12_4", + "DSP_IMUX19_4", + "DSP_1_D10", + "DSP_NE4C2_3", + "DSP_1_ACIN18", + "DSP_1_ACIN5", + "DSP_EE4C2_3", + "DSP_EE2A1_0", + "DSP_0_PCOUT6", + "DSP_0_D17", + "DSP_SW2A0_4", + "DSP_0_A11", + "DSP_LOGIC_OUTS_B18_4", + "DSP_CLK1_3", + "DSP_1_D5", + "DSP_SE2A1_1", + "DSP_1_ALUMODE1", + "DSP_NE2A0_3", + "DSP_MONITOR_P_2", + "DSP_0_A15", + "DSP_LOGIC_OUTS_B23_1", + "DSP_SE4BEG2_1", + "DSP_1_A2", + "DSP_BYP7_1", + "DSP_0_BCIN10", + "DSP_0_BCIN5", + "DSP_LH6_0", + "DSP_LOGIC_OUTS_B15_3", + "DSP_BYP5_3", + "DSP_PCOUT5", + "DSP_1_ACOUT3", + "DSP_NW4A1_0", + "DSP_NW2A1_0", + "DSP_WW4C0_4", + "DSP_SE2A2_1", + "DSP_0_P5", + "DSP_0_C27", + "DSP_FAN6_2", + "DSP_EE4A1_4", + "DSP_IMUX41_2", + "DSP_LOGIC_OUTS_B23_3", + "DSP_LOGIC_OUTS_B13_4", + "DSP_0_CEB1", + "DSP_EL1BEG0_2", + "DSP_0_ACOUT19", + "DSP_1_ACOUT28", + "DSP_EE4C3_3", + "DSP_0_PCIN3", + "DSP_IMUX21_2", + "DSP_1_PCIN44", + "DSP_0_B4", + "DSP_IMUX45_4", + "DSP_1_PATTERNDETECT", + "DSP_LOGIC_OUTS_B4_3", + "DSP_SW4A2_1", + "DSP_0_P20", + "DSP_SE4C1_1", + "DSP_BLOCK_OUTS_B0_4", + "DSP_BYP7_0", + "DSP_FAN5_3", + "DSP_IMUX30_3", + "DSP_NW4END2_3", + "DSP_0_D9", + "DSP_1_D7", + "DSP_LOGIC_OUTS_B3_1", + "DSP_IMUX1_1", + "DSP_1_PCOUT8", + "DSP_BYP2_1", + "DSP_1_BCIN15", + "DSP_EE4B2_0", + "DSP_LH11_4", + "DSP_NW2A0_0", + "DSP_0_BCOUT10", + "DSP_NE4C0_3", + "DSP_LOGIC_OUTS_B13_3", + "DSP_WL1END1_2", + "DSP_1_B13", + "DSP_1_C24", + "DSP_IMUX38_0", + "DSP_WW4C3_2", + "DSP_NE4C0_1", + "DSP_IMUX42_2", + "DSP_0_P8", + "DSP_0_C43", + "DSP_IMUX0_4", + "DSP_NW4END1_0", + "DSP_BCOUT3", + "DSP_NW4A2_4", + "DSP_CLK1_1", + "DSP_LOGIC_OUTS_B18_1", + "DSP_PCOUT14", + "DSP_NW4END2_1", + "DSP_EE4BEG0_3", + "DSP_1_PCIN15", + "DSP_WL1END2_3", + "DSP_PCOUT31", + "DSP_IMUX34_1", + "DSP_ACOUT21", + "DSP_EE4BEG1_2", + "DSP_0_P44", + "DSP_1_PCIN20", + "DSP_0_C18", + "DSP_IMUX18_1", + "DSP_EE2BEG0_1", + "DSP_NE4BEG1_4", + "DSP_PCOUT6", + "DSP_1_BCIN16", + "DSP_LH2_2", + "DSP_1_CEINMODE", + "DSP_0_C12", + "DSP_1_PCIN27", + "DSP_SW4A1_2", + "DSP_0_ACOUT21", + "DSP_1_PCOUT44", + "DSP_WL1END0_1", + "DSP_0_OVERFLOW", + "DSP_1_RSTP", + "DSP_WR1END1_3", + "DSP_0_BCOUT6", + "DSP_1_ACIN21", + "DSP_FAN7_4", + "DSP_1_C3", + "DSP_EE2BEG3_0", + "DSP_LH8_2", + "DSP_1_ACOUT20", + "DSP_1_C38", + "DSP_0_PCIN44", + "DSP_0_ALUMODE2", + "DSP_IMUX10_2", + "DSP_LOGIC_OUTS_B16_4", + "DSP_WW2END0_2", + "DSP_1_BCOUT10", + "DSP_ACOUT29", + "DSP_LOGIC_OUTS_B23_4", + "DSP_1_PCIN8", + "DSP_1_C14", + "DSP_0_BCIN9", + "DSP_1_PCOUT31", + "DSP_1_OPMODE4", + "DSP_0_C9", + "DSP_SW4END3_1", + "DSP_1_C20", + "DSP_PCOUT1", + "DSP_IMUX16_1", + "DSP_IMUX13_1", + "DSP_ER1BEG3_3", + "DSP_MONITOR_P_3", + "DSP_NW2A3_4", + "DSP_1_P36", + "DSP_LOGIC_OUTS_B2_0", + "DSP_1_C13", + "DSP_IMUX21_1", + "DSP_PCOUT9", + "DSP_PCOUT25", + "DSP_0_C36", + "DSP_LH9_0", + "DSP_SW4A1_3", + "DSP_IMUX20_0", + "DSP_0_RSTM", + "DSP_1_PCOUT2", + "DSP_BYP0_0", + "DSP_1_C41", + "DSP_IMUX8_2", + "DSP_WR1END3_4", + "DSP_EL1BEG2_4", + "DSP_0_PCIN24", + "DSP_WW4A2_2", + "DSP_ACOUT25", + "DSP_1_P3", + "DSP_IMUX46_4", + "DSP_CARRYCASCOUT", + "DSP_LH10_4", + "DSP_1_PCOUT29", + "DSP_LOGIC_OUTS_B5_1", + "DSP_0_PCOUT25", + "DSP_SE2A0_2", + "DSP_NW2A3_1", + "DSP_1_PCOUT25", + "DSP_0_BCOUT16", + "DSP_0_C38", + "DSP_BYP6_1", + "DSP_WW4A0_4", + "DSP_IMUX46_3", + "DSP_0_PCOUT7", + "DSP_0_B9", + "DSP_WW4A0_3", + "DSP_1_BCIN10", + "DSP_0_B5", + "DSP_IMUX36_4", + "DSP_0_A4", + "DSP_PCOUT22", + "DSP_IMUX27_2", + "DSP_0_P10", + "DSP_0_D1", + "DSP_1_ACOUT29", + "DSP_1_PCIN41", + "DSP_EE4BEG1_0", + "DSP_NE2A0_0", + "DSP_MULTSIGNOUT", + "DSP_0_ALUMODE0", + "DSP_1_OPMODE3", + "DSP_EE4B0_4", + "DSP_IMUX34_4", + "DSP_EE4BEG0_0", + "DSP_EE2A0_2", + "DSP_IMUX3_4", + "DSP_0_PCOUT14", + "DSP_FAN3_1", + "DSP_0_C33", + "DSP_0_PCOUT21", + "DSP_IMUX30_4", + "DSP_WW4B3_1", + "DSP_CTRL1_1", + "DSP_1_OVERFLOW", + "DSP_FAN2_4", + "DSP_BYP5_2", + "DSP_NE4BEG0_1", + "DSP_0_PCOUT30", + "DSP_WW4B1_3", + "DSP_0_BCIN3", + "DSP_NE2A0_1", + "DSP_0_P6", + "DSP_NE4C2_0", + "DSP_IMUX16_2", + "DSP_NW4A1_1", + "DSP_0_ALUMODE1", + "DSP_0_PCOUT15", + "DSP_1_PCIN21", + "DSP_1_BCIN13", + "DSP_0_C4", + "DSP_IMUX13_3", + "DSP_0_PCIN4", + "DSP_LOGIC_OUTS_B8_2", + "DSP_LH2_0", + "DSP_0_D22", + "DSP_1_P40", + "DSP_1_CECARRYIN", + "DSP_1_A28", + "DSP_SE4BEG1_1", + "DSP_SE2A2_0", + "DSP_1_CEB1", + "DSP_0_BCIN2", + "DSP_NE4C3_3", + "DSP_1_P0", + "DSP_1_BCIN12", + "DSP_SE4C3_4", + "DSP_SE4BEG2_2", + "DSP_1_BCIN17", + "DSP_WL1END2_0", + "DSP_LOGIC_OUTS_B0_3", + "DSP_1_PCIN1", + "DSP_WR1END0_4", + "DSP_WL1END1_3", + "DSP_1_PCIN40", + "DSP_0_PCIN16", + "DSP_LH11_0", + "DSP_FAN2_3", + "DSP_0_ACOUT0", + "DSP_WW4END3_1", + "DSP_WW4C1_1", + "DSP_SE2A0_0", + "DSP_EE4A1_3", + "DSP_NE2A2_2", + "DSP_IMUX18_2", + "DSP_IMUX28_0", + "DSP_LH4_4", + "DSP_FAN6_4", + "DSP_IMUX13_2", + "DSP_0_CARRYOUT0", + "DSP_1_P25", + "DSP_0_C24", + "DSP_IMUX7_2", + "DSP_WW4C1_2", + "DSP_0_PCOUT44", + "DSP_1_PCOUT15", + "DSP_NE2A3_2", + "DSP_WW4B2_3", + "DSP_IMUX36_0", + "DSP_NE4BEG1_0", + "DSP_0_PCIN18", + "DSP_IMUX46_0", + "DSP_0_CARRYINSEL2", + "DSP_EE2A1_4", + "DSP_ACOUT14", + "DSP_1_A10", + "DSP_BYP3_2", + "DSP_0_A18", + "DSP_WW4C3_0", + "DSP_WW4C2_3", + "DSP_SE4C1_0", + "DSP_BCOUT5", + "DSP_LOGIC_OUTS_B1_0", + "DSP_1_PCIN0", + "DSP_WR1END1_1", + "DSP_LH1_0", + "DSP_SW2A2_3", + "DSP_1_ACOUT10", + "DSP_IMUX15_0", + "DSP_IMUX12_0", + "DSP_BYP7_2", + "DSP_1_ACOUT9", + "DSP_1_CARRYINSEL2", + "DSP_1_A24", + "DSP_EE2A0_4", + "DSP_EE4B0_3", + "DSP_1_PCOUT45", + "DSP_ACOUT19", + "DSP_0_PATTERNDETECT", + "DSP_1_B3", + "DSP_WW2A2_4", + "DSP_LOGIC_OUTS_B4_1", + "DSP_IMUX39_4", + "DSP_0_P3", + "DSP_SW2A2_0", + "DSP_IMUX13_0", + "DSP_GND_L", + "DSP_NE2A2_3", + "DSP_SE4BEG0_0", + "DSP_LOGIC_OUTS_B16_3", + "DSP_NW4END3_4", + "DSP_NW4END3_1", + "DSP_WW4B2_1", + "DSP_0_BCOUT14", + "DSP_WW2END2_1", + "DSP_BLOCK_OUTS_B2_3", + "DSP_PCOUT43", + "DSP_0_PCOUT46", + "DSP_WW2END1_3", + "DSP_0_INMODE3", + "DSP_SW4END0_3", + "DSP_0_PCOUT39", + "DSP_SE2A0_4", + "DSP_0_RSTA", + "DSP_NW4END0_2", + "DSP_EE2A1_3", + "DSP_0_CARRYCASCIN", + "DSP_SW2A3_4", + "DSP_IMUX43_1", + "DSP_IMUX15_3", + "DSP_LH10_1", + "DSP_0_ACIN2", + "DSP_0_OPMODE2", + "DSP_NE2A2_0", + "DSP_EE2A1_2", + "DSP_EE4BEG3_2", + "DSP_EE2BEG1_3", + "DSP_SW2A0_1", + "DSP_IMUX22_1", + "DSP_EE4A1_1", + "DSP_SW4A1_4", + "DSP_PCOUT41", + "DSP_IMUX19_3", + "DSP_SE4BEG3_2", + "DSP_1_P23", + "DSP_0_A26", + "DSP_FAN1_3", + "DSP_EE4C1_3", + "DSP_BCOUT17", + "DSP_1_A29", + "DSP_EE2A2_2", + "DSP_BLOCK_OUTS_B1_0", + "DSP_LH10_3", + "DSP_0_CLK", + "DSP_1_ACOUT15", + "DSP_1_PCOUT27", + "DSP_IMUX2_1", + "DSP_0_ACIN26", + "DSP_WW4B0_4", + "DSP_0_A10", + "DSP_LOGIC_OUTS_B10_3", + "DSP_0_D14", + "DSP_NW4END3_2", + "DSP_0_BCIN17", + "DSP_1_PCIN43", + "DSP_0_P11", + "DSP_1_B15", + "DSP_LOGIC_OUTS_B18_2", + "DSP_0_A14", + "DSP_IMUX47_3", + "DSP_1_PCOUT13", + "DSP_1_ACIN29", + "DSP_LOGIC_OUTS_B9_3", + "DSP_1_ACOUT1", + "DSP_EE4BEG2_3", + "DSP_0_P46", + "DSP_1_PCIN36", + "DSP_IMUX19_2", + "DSP_1_ACIN22", + "DSP_1_PCIN7", + "DSP_CTRL1_4", + "DSP_IMUX11_1", + "DSP_EL1BEG1_2", + "DSP_ER1BEG3_4", + "DSP_LOGIC_OUTS_B4_2", + "DSP_EE4A3_2", + "DSP_0_PCOUT18", + "DSP_0_A29", + "DSP_1_ACIN2", + "DSP_1_CED", + "DSP_PCOUT0", + "DSP_NW2A1_1", + "DSP_ER1BEG2_3", + "DSP_1_RSTD", + "DSP_SW4A2_0", + "DSP_LOGIC_OUTS_B22_1", + "DSP_1_A18", + "DSP_IMUX32_1", + "DSP_IMUX44_4", + "DSP_FAN4_2", + "DSP_EE2BEG2_0", + "DSP_NW2A3_3", + "DSP_0_ACOUT5", + "DSP_1_BCOUT7", + "DSP_1_PCIN12", + "DSP_IMUX43_3", + "DSP_1_ACOUT8", + "DSP_IMUX41_4", + "DSP_1_D16", + "DSP_0_A8", + "DSP_VCC_L", + "DSP_EE2BEG3_3", + "DSP_LOGIC_OUTS_B7_3", + "DSP_1_C42", + "DSP_WW2END2_0", + "DSP_LH3_0", + "DSP_EE4C3_0", + "DSP_SW4A3_3", + "DSP_EE2BEG1_0", + "DSP_BCOUT9", + "DSP_0_PCIN30", + "DSP_1_P17", + "DSP_1_PCIN4", + "DSP_1_ACOUT26", + "DSP_IMUX34_2", + "DSP_0_D16", + "DSP_WW2END3_4", + "DSP_1_BCOUT12", + "DSP_1_B1", + "DSP_0_PCIN47", + "DSP_WW4A3_0", + "DSP_0_A12", + "DSP_WW2END1_2", + "DSP_NE2A2_1", + "DSP_EL1BEG1_1", + "DSP_WL1END1_0", + "DSP_LH12_0", + "DSP_0_BCIN7", + "DSP_NW4A1_4", + "DSP_1_PCOUT14", + "DSP_0_BCOUT12", + "DSP_IMUX4_4", + "DSP_1_PCOUT38", + "DSP_EE4B1_2", + "DSP_IMUX28_3", + "DSP_PCOUT4", + "DSP_WW2END3_1", + "DSP_SW4END2_1", + "DSP_IMUX22_2", + "DSP_1_C6", + "DSP_IMUX33_0", + "DSP_LOGIC_OUTS_B6_4", + "DSP_FAN0_1", + "DSP_1_OPMODE5", + "DSP_0_C14", + "DSP_1_P8", + "DSP_EE4BEG3_1", + "DSP_1_A25", + "DSP_EL1BEG0_4", + "DSP_IMUX4_1", + "DSP_SE4C3_1", + "DSP_0_BCIN8", + "DSP_LH9_3", + "DSP_BYP5_4", + "DSP_EL1BEG3_3", + "DSP_WW4A3_2", + "DSP_1_PCIN31", + "DSP_WW4A1_2", + "DSP_LOGIC_OUTS_B15_2", + "DSP_0_BCOUT15", + "DSP_1_A21", + "DSP_IMUX40_4", + "DSP_SW2A1_3", + "DSP_BYP0_4", + "DSP_WW2A0_4", + "DSP_1_C7", + "DSP_BLOCK_OUTS_B2_0", + "DSP_ACOUT4", + "DSP_BLOCK_OUTS_B0_0", + "DSP_IMUX20_4", + "DSP_NW2A2_1", + "DSP_1_PCIN32", + "DSP_0_ACIN22", + "DSP_0_INMODE0", + "DSP_IMUX9_3", + "DSP_WW4END2_1", + "DSP_1_B12", + "DSP_SW4END3_0", + "DSP_LOGIC_OUTS_B3_2", + "DSP_PCOUT17", + "DSP_1_BCOUT13", + "DSP_WW4A0_1", + "DSP_EE2BEG0_2", + "DSP_WW2A1_3", + "DSP_0_B8", + "DSP_CTRL0_3", + "DSP_1_CARRYINSEL1", + "DSP_ACOUT12", + "DSP_0_D12", + "DSP_NE4BEG3_3", + "DSP_IMUX1_2", + "DSP_IMUX6_3", + "DSP_WW2A1_1", + "DSP_1_P30", + "DSP_1_ACOUT24", + "DSP_0_ACIN25", + "DSP_NW4END2_2", + "DSP_SE4C2_3", + "DSP_EE4B3_1", + "DSP_0_PCIN38", + "DSP_1_C43", + "DSP_FAN0_0", + "DSP_NW4END0_1", + "DSP_WR1END3_2", + "DSP_1_INMODE2", + "DSP_WW4A1_0", + "DSP_NE2A1_4", + "DSP_IMUX32_0", + "DSP_1_ACOUT12", + "DSP_LOGIC_OUTS_B18_0", + "DSP_IMUX5_3", + "DSP_IMUX36_2", + "DSP_1_BCIN14", + "DSP_EE2BEG1_2", + "DSP_0_P41", + "DSP_EE4A2_1", + "DSP_NW2A0_3", + "DSP_EL1BEG2_3", + "DSP_1_ACIN27", + "DSP_EE2BEG3_2", + "DSP_0_RSTB", + "DSP_0_P29", + "DSP_WW2END0_0", + "DSP_0_INMODE1", + "DSP_0_ACOUT18", + "DSP_LOGIC_OUTS_B9_1", + "DSP_BYP4_4", + "DSP_SE4BEG3_4", + "DSP_1_BCOUT2", + "DSP_1_ACIN26", + "DSP_NW4A0_2", + "DSP_1_ACOUT6", + "DSP_CTRL0_1", + "DSP_BLOCK_OUTS_B2_2", + "DSP_SE4BEG2_0", + "DSP_NE4BEG1_1", + "DSP_IMUX17_4", + "DSP_IMUX15_4", + "DSP_PCOUT42", + "DSP_0_C26", + "DSP_NE4BEG0_2", + "DSP_WW4END3_2", + "DSP_LH7_4", + "DSP_0_BCIN16", + "DSP_SE4C1_2", + "DSP_FAN0_2", + "DSP_1_PCIN28", + "DSP_IMUX3_0", + "DSP_IMUX25_2", + "DSP_EE4A3_4", + "DSP_WW2A3_3", + "DSP_0_PCOUT28", + "DSP_NW4A3_0", + "DSP_SE2A2_2", + "DSP_IMUX32_2", + "DSP_LOGIC_OUTS_B11_3", + "DSP_0_D15", + "DSP_0_ACIN4", + "DSP_NW2A2_0", + "DSP_1_PCIN42", + "DSP_0_CEC", + "DSP_SW4END2_3", + "DSP_1_ACIN12", + "DSP_0_PCOUT12", + "DSP_CLK1_4", + "DSP_0_PCOUT5", + "DSP_LOGIC_OUTS_B20_3", + "DSP_BCOUT12", + "DSP_SW4END3_3", + "DSP_1_D18", + "DSP_1_P2", + "DSP_ACOUT24", + "DSP_WR1END2_3", + "DSP_FAN3_3", + "DSP_LH12_4", + "DSP_NW4END0_3", + "DSP_EE4C2_0", + "DSP_0_P16", + "DSP_IMUX39_0", + "DSP_0_PCIN32", + "DSP_PCOUT7", + "DSP_LH11_1", + "DSP_IMUX12_2", + "DSP_LOGIC_OUTS_B1_4", + "DSP_LOGIC_OUTS_B5_3", + "DSP_LH5_3", + "DSP_ACOUT9", + "DSP_EE4BEG2_4", + "DSP_0_CARRYINSEL1", + "DSP_IMUX28_4", + "DSP_IMUX8_1", + "DSP_1_P5", + "DSP_1_PCIN17", + "DSP_1_D17", + "DSP_IMUX31_2", + "DSP_SW4END1_0", + "DSP_0_A19", + "DSP_1_PCIN35", + "DSP_ER1BEG0_1", + "DSP_IMUX1_0", + "DSP_0_PCIN11", + "DSP_CLK0_0", + "DSP_IMUX12_3", + "DSP_NW2A1_3", + "DSP_LOGIC_OUTS_B8_0", + "DSP_WR1END1_0", + "DSP_WW4A3_1", + "DSP_WW4A1_1", + "DSP_WW4B1_1", + "DSP_1_PCOUT40", + "DSP_0_P28", + "DSP_SW2A2_2", + "DSP_0_PCOUT16", + "DSP_1_D19", + "DSP_PCOUT23", + "DSP_BLOCK_OUTS_B1_4", + "DSP_0_D20", + "DSP_FAN7_0", + "DSP_SE4C1_3", + "DSP_SW2A0_2", + "DSP_WL1END0_2", + "DSP_1_PCIN3", + "DSP_1_D1", + "DSP_1_B4", + "DSP_FAN4_1", + "DSP_NW4A0_3", + "DSP_0_OPMODE5", + "DSP_1_B17", + "DSP_1_CARRYOUT1", + "DSP_0_C35", + "DSP_NE4C3_4", + "DSP_LH8_1", + "DSP_LH5_4", + "DSP_0_A0", + "DSP_1_P31", + "DSP_BCOUT4", + "DSP_0_D0", + "DSP_IMUX35_0", + "DSP_1_D0", + "DSP_ACOUT23", + "DSP_IMUX29_3", + "DSP_SE4C3_3", + "DSP_SW4A1_1", + "DSP_WL1END1_4", + "DSP_PCOUT16", + "DSP_IMUX10_3", + "DSP_WW4END2_4", + "DSP_LH3_1", + "DSP_LH9_1", + "DSP_LH1_1", + "DSP_0_P45", + "DSP_1_A23", + "DSP_LOGIC_OUTS_B20_0", + "DSP_1_ACIN19", + "DSP_1_BCIN11", + "DSP_FAN0_3", + "DSP_EE2A1_1", + "DSP_1_PCOUT20", + "DSP_WW4B1_2", + "DSP_EE4BEG1_1", + "DSP_WW4A0_0", + "DSP_LOGIC_OUTS_B7_4", + "DSP_WW4C0_3", + "DSP_FAN2_2", + "DSP_0_B17", + "DSP_0_P31", + "DSP_0_BCOUT9", + "DSP_1_BCIN5", + "DSP_0_B12", + "DSP_IMUX11_0", + "DSP_1_C0", + "DSP_0_ACOUT22", + "DSP_0_P17", + "DSP_NE4BEG3_4", + "DSP_0_PCIN39", + "DSP_BYP3_3", + "DSP_1_C12", + "DSP_1_D8", + "DSP_BLOCK_OUTS_B0_1", + "DSP_1_ACIN1", + "DSP_IMUX9_0", + "DSP_WW4B2_0", + "DSP_0_CEM", + "DSP_1_A26", + "DSP_0_BCOUT3", + "DSP_LOGIC_OUTS_B9_2", + "DSP_IMUX15_2", + "DSP_NE4BEG1_2", + "DSP_LH8_4", + "DSP_IMUX3_2", + "DSP_0_P36", + "DSP_BLOCK_OUTS_B3_0", + "DSP_NE2A3_4", + "DSP_1_C11", + "DSP_0_PCOUT23", + "DSP_ACOUT3", + "DSP_BLOCK_OUTS_B1_1", + "DSP_IMUX38_1", + "DSP_0_P15", + "DSP_1_PCOUT22", + "DSP_0_C34", + "DSP_WW4B3_2", + "DSP_1_RSTINMODE", + "DSP_1_P37", + "DSP_0_P30", + "DSP_CTRL0_0", + "DSP_1_PCOUT46", + "DSP_LOGIC_OUTS_B22_4", + "DSP_0_PCOUT34", + "DSP_1_P22", + "DSP_IMUX47_0", + "DSP_EL1BEG3_1", + "DSP_WW2END0_1", + "DSP_NW4A2_1", + "DSP_SE4C2_0", + "DSP_1_D9", + "DSP_BYP0_1", + "DSP_NE4BEG3_0", + "DSP_LOGIC_OUTS_B1_2", + "DSP_IMUX8_0", + "DSP_1_P33", + "DSP_0_CEP", + "DSP_1_PCIN26", + "DSP_1_PCOUT42", + "DSP_LOGIC_OUTS_B12_2", + "DSP_SW2A2_4", + "DSP_BCOUT8", + "DSP_IMUX45_3", + "DSP_WW4C3_3", + "DSP_0_P9", + "DSP_SW2A0_3", + "DSP_IMUX11_4", + "DSP_IMUX29_0", + "DSP_0_BCIN4", + "DSP_0_BCOUT4", + "DSP_0_PCIN27", + "DSP_SE4C3_0", + "DSP_IMUX25_4", + "DSP_1_BCIN4", + "DSP_ACOUT8", + "DSP_0_P24", + "DSP_EE2BEG0_3", + "DSP_CLK0_1", + "DSP_IMUX12_1", + "DSP_CTRL1_0", + "DSP_LOGIC_OUTS_B11_0", + "DSP_0_BCOUT5", + "DSP_ACOUT26", + "DSP_WR1END2_1", + "DSP_0_C19", + "DSP_WW4END1_3", + "DSP_LOGIC_OUTS_B1_1", + "DSP_0_PCIN29", + "DSP_1_A6", + "DSP_0_D19", + "DSP_NE4BEG0_3", + "DSP_LOGIC_OUTS_B10_2", + "DSP_1_C29", + "DSP_EE4A3_1", + "DSP_PCOUT21", + "DSP_1_P35", + "DSP_CTRL1_3", + "DSP_1_P32", + "DSP_1_C33", + "DSP_EE4C1_0", + "DSP_EE4B1_1", + "DSP_1_ACIN17", + "DSP_IMUX2_0", + "DSP_IMUX18_0", + "DSP_NW2A1_2", + "DSP_EE2A0_0", + "DSP_NE2A0_2", + "DSP_1_RSTC", + "DSP_IMUX45_1", + "DSP_1_B16", + "DSP_LOGIC_OUTS_B17_0", + "DSP_1_CECTRL", + "DSP_0_C11", + "DSP_EE2BEG2_3", + "DSP_LH10_2", + "DSP_0_A13", + "DSP_0_C44", + "DSP_WW4A3_3", + "DSP_WW4END1_4", + "DSP_SE2A0_1", + "DSP_LH9_2", + "DSP_CLK0_3", + "DSP_BYP5_0", + "DSP_1_B14", + "DSP_0_CARRYOUT2", + "DSP_EL1BEG3_4", + "DSP_1_CLK", + "DSP_1_ACIN14", + "DSP_PCOUT44", + "DSP_1_P38", + "DSP_SW4END0_2", + "DSP_IMUX6_0", + "DSP_NE4C0_0", + "DSP_IMUX21_3", + "DSP_NW4END1_2", + "DSP_LOGIC_OUTS_B15_1", + "DSP_1_ACOUT25", + "DSP_IMUX0_2", + "DSP_WW2END1_4", + "DSP_NE4C2_1", + "DSP_IMUX40_0", + "DSP_IMUX17_3", + "DSP_IMUX6_4", + "DSP_1_C21", + "DSP_1_A14", + "DSP_1_CEA1", + "DSP_WW2A1_2", + "DSP_0_A1", + "DSP_LOGIC_OUTS_B21_3", + "DSP_0_PCOUT35", + "DSP_WW2END0_4", + "DSP_1_A11", + "DSP_MONITOR_P_0", + "DSP_1_PCOUT18", + "DSP_0_C25", + "DSP_1_RSTM", + "DSP_0_C2", + "DSP_LOGIC_OUTS_B4_4", + "DSP_PCOUT8", + "DSP_WW2END3_0", + "DSP_LH4_1", + "DSP_ER1BEG2_1", + "DSP_IMUX16_0", + "DSP_IMUX46_1", + "DSP_1_PCIN25", + "DSP_1_A20", + "DSP_LH5_0", + "DSP_IMUX35_3", + "DSP_0_B14", + "DSP_0_CEA2", + "DSP_NE2A3_1", + "DSP_1_P7", + "DSP_NE4BEG3_2", + "DSP_0_A16", + "DSP_EE4B0_0", + "DSP_IMUX40_1", + "DSP_EL1BEG2_2", + "DSP_LOGIC_OUTS_B21_4", + "DSP_EE4A1_0", + "DSP_FAN3_2", + "DSP_EE4A0_3", + "DSP_NE4C1_1", + "DSP_IMUX6_1", + "DSP_SW2A0_0", + "DSP_ER1BEG3_0", + "DSP_NW2A0_1", + "DSP_0_ACIN27", + "DSP_IMUX33_1", + "DSP_0_PCOUT11", + "DSP_EL1BEG2_0", + "DSP_WR1END1_4", + "DSP_IMUX42_3", + "DSP_IMUX39_2", + "DSP_FAN2_0", + "DSP_1_A5", + "DSP_EE4C0_2", + "DSP_IMUX25_0", + "DSP_WW4C1_4", + "DSP_0_P22", + "DSP_BYP1_4", + "DSP_BYP4_1", + "DSP_0_ACIN9", + "DSP_BYP0_2", + "DSP_0_PCIN35", + "DSP_0_A6", + "DSP_LH3_3", + "DSP_IMUX9_1", + "DSP_IMUX5_2", + "DSP_FAN7_3", + "DSP_1_BCOUT6", + "DSP_SE4C0_0", + "DSP_0_BCOUT1", + "DSP_0_C22", + "DSP_0_B0", + "DSP_WW2END3_2", + "DSP_1_P24", + "DSP_0_ACOUT28", + "DSP_1_PCOUT21", + "DSP_0_C41", + "DSP_WR1END0_1", + "DSP_WW4B3_3", + "DSP_NE4C2_4", + "DSP_1_D4", + "DSP_0_D18", + "DSP_LOGIC_OUTS_B10_4", + "DSP_FAN7_1", + "DSP_1_ALUMODE2", + "DSP_NE4BEG2_0", + "DSP_EE4BEG2_1", + "DSP_EL1BEG3_2", + "DSP_1_P45", + "DSP_LOGIC_OUTS_B13_1", + "DSP_1_PCIN29", + "DSP_SE4BEG0_1", + "DSP_1_P6", + "DSP_1_ACIN24", + "DSP_0_P4", + "DSP_LH1_4", + "DSP_WW4B3_4", + "DSP_SW4END1_4", + "DSP_1_P46", + "DSP_NE2A3_3", + "DSP_0_ACIN29", + "DSP_IMUX8_4", + "DSP_EL1BEG0_0", + "DSP_0_ACIN18", + "DSP_0_D21", + "DSP_1_ACOUT22", + "DSP_0_C47", + "DSP_IMUX4_0", + "DSP_EE4C2_1", + "DSP_BCOUT6", + "DSP_1_P4", + "DSP_1_C31", + "DSP_1_BCOUT3", + "DSP_EE2A3_4", + "DSP_WW2END2_3", + "DSP_EE4A2_3", + "DSP_EE2A3_3", + "DSP_1_ACIN9", + "DSP_0_PCOUT40", + "DSP_0_ACOUT25", + "DSP_WR1END2_0", + "DSP_0_ACOUT24", + "DSP_FAN5_0", + "DSP_LH10_0", + "DSP_LOGIC_OUTS_B14_2", + "DSP_EE2A2_1", + "DSP_0_ACOUT2", + "DSP_1_C35", + "DSP_1_ACOUT4", + "DSP_1_D21", + "DSP_0_PCOUT17", + "DSP_WW4A2_3", + "DSP_1_D3", + "DSP_EE2BEG2_4", + "DSP_EE4C0_4", + "DSP_IMUX4_3", + "DSP_1_BCOUT15", + "DSP_1_A8", + "DSP_ACOUT7", + "DSP_SE2A3_4", + "DSP_IMUX29_1", + "DSP_1_PCIN10", + "DSP_0_P2", + "DSP_IMUX46_2", + "DSP_0_ACIN19", + "DSP_IMUX17_2", + "DSP_0_C13", + "DSP_BYP4_3", + "DSP_NW4A0_0", + "DSP_SW4A3_2", + "DSP_1_CEA2", + "DSP_LH4_3", + "DSP_IMUX14_4", + "DSP_LH6_2", + "DSP_LOGIC_OUTS_B5_4", + "DSP_1_PCOUT47", + "DSP_FAN4_4", + "DSP_0_BCOUT7", + "DSP_BYP3_4", + "DSP_LOGIC_OUTS_B20_1", + "DSP_WW2END3_3", + "DSP_IMUX17_1", + "DSP_BLOCK_OUTS_B3_4", + "DSP_WR1END0_2", + "DSP_WW4END3_3", + "DSP_NW4A3_3", + "DSP_CTRL0_4", + "DSP_FAN6_1", + "DSP_1_ACOUT21", + "DSP_LOGIC_OUTS_B5_2", + "DSP_0_ACOUT10", + "DSP_LH7_0", + "DSP_1_P14", + "DSP_FAN1_1", + "DSP_SW4A0_3", + "DSP_1_OPMODE2", + "DSP_BYP4_0", + "DSP_1_P20", + "DSP_IMUX10_0", + "DSP_WW4END3_4", + "DSP_IMUX43_2", + "DSP_0_C10", + "DSP_EL1BEG1_0", + "DSP_FAN3_4", + "DSP_1_PCOUT23", + "DSP_1_PCOUT4", + "DSP_WL1END0_0", + "DSP_1_PCIN30", + "DSP_0_BCOUT0", + "DSP_IMUX22_4", + "DSP_NE4C3_1", + "DSP_0_A5", + "DSP_WR1END0_3", + "DSP_1_BCIN9", + "DSP_PCOUT3", + "DSP_0_PCIN25", + "DSP_SW2A1_2", + "DSP_WW4END2_2", + "DSP_PCOUT47", + "DSP_0_P47", + "DSP_1_BCOUT17", + "DSP_EL1BEG0_3", + "DSP_WW2A2_0", + "DSP_1_BCOUT4", + "DSP_SE4BEG3_3", + "DSP_IMUX44_0", + "DSP_WW4A2_1", + "DSP_EE4BEG2_0", + "DSP_WR1END2_2", + "DSP_BYP6_0", + "DSP_1_A4", + "DSP_1_P27", + "DSP_0_P26", + "DSP_LOGIC_OUTS_B6_3", + "DSP_IMUX42_4", + "DSP_NW2A1_4", + "DSP_IMUX29_4", + "DSP_1_B10", + "DSP_EE4B3_2", + "DSP_NE4C3_0", + "DSP_WW2END2_4", + "DSP_0_PCIN36", + "DSP_1_PCIN9", + "DSP_1_C26", + "DSP_EE4BEG3_4", + "DSP_EL1BEG0_1", + "DSP_LOGIC_OUTS_B11_4", + "DSP_BYP6_2", + "DSP_PCOUT12", + "DSP_0_PCOUT9", + "DSP_0_A25", + "DSP_EE4C1_4", + "DSP_1_BCOUT0", + "DSP_0_PCOUT2", + "DSP_0_ACIN13", + "DSP_LOGIC_OUTS_B19_4", + "DSP_PCOUT40", + "DSP_SW4A2_3", + "DSP_1_CARRYOUT3", + "DSP_1_ALUMODE0", + "DSP_0_PCIN26", + "DSP_1_ACIN0", + "DSP_SE2A1_3", + "DSP_1_OPMODE0", + "DSP_ER1BEG2_4", + "DSP_1_PCIN14", + "DSP_IMUX42_1", + "DSP_IMUX3_1", + "DSP_LOGIC_OUTS_B12_3", + "DSP_SW4END2_2", + "DSP_IMUX45_0", + "DSP_BLOCK_OUTS_B1_2", + "DSP_1_PCOUT7", + "DSP_1_PCOUT34", + "DSP_0_ACIN28", + "DSP_WW4END0_1", + "DSP_0_PCIN28", + "DSP_BLOCK_OUTS_B3_1", + "DSP_ACOUT6", + "DSP_SE4C0_2", + "DSP_0_A23", + "DSP_1_C36", + "DSP_1_P16", + "DSP_1_CEB2", + "DSP_EE4A2_4", + "DSP_EE4A1_2", + "DSP_WW4C0_0", + "DSP_0_ACIN21", + "DSP_WW4END1_2", + "DSP_1_PCIN47", + "DSP_0_D24", + "DSP_CLK1_0", + "DSP_EE4BEG3_0", + "DSP_1_C19", + "DSP_IMUX14_3", + "DSP_1_CEC", + "DSP_SE4BEG3_0", + "DSP_1_C8", + "DSP_1_ACIN16", + "DSP_1_ACOUT23", + "DSP_WW2A2_1", + "DSP_0_PCOUT38", + "DSP_IMUX35_1", + "DSP_LH6_3", + "DSP_0_P40", + "DSP_0_ACIN6", + "DSP_1_ACOUT0", + "DSP_SW4END1_1", + "DSP_LH12_2", + "DSP_0_PCOUT13", + "DSP_0_PCOUT8", + "DSP_1_C40", + "DSP_FAN5_4", + "DSP_WW4B1_4", + "DSP_IMUX22_0", + "DSP_IMUX3_3", + "DSP_1_BCOUT1", + "DSP_1_PCOUT32", + "DSP_BYP3_1", + "DSP_NW4A1_3", + "DSP_IMUX22_3", + "DSP_SW4A2_2", + "DSP_ACOUT22", + "DSP_IMUX33_3", + "DSP_SE2A1_2", + "DSP_LOGIC_OUTS_B3_3", + "DSP_0_B3", + "DSP_0_CARRYINSEL0", + "DSP_1_PCIN5", + "DSP_IMUX18_3", + "DSP_1_PCOUT12", + "DSP_1_INMODE1", + "DSP_1_D6", + "DSP_IMUX2_4", + "DSP_0_B7", + "DSP_NW2A3_0", + "DSP_1_PCIN39", + "DSP_1_P29", + "DSP_SW4END3_2", + "DSP_BLOCK_OUTS_B3_3", + "DSP_SW4END3_4", + "DSP_PCOUT11", + "DSP_1_PCIN11", + "DSP_LH8_3", + "DSP_IMUX34_3", + "DSP_0_PCIN10", + "DSP_NE4BEG2_3", + "DSP_0_ACIN16", + "DSP_1_B9", + "DSP_1_C5", + "DSP_PCOUT18", + "DSP_1_C15", + "DSP_LOGIC_OUTS_B7_1", + "DSP_1_ACIN6", + "DSP_1_PCOUT30", + "DSP_IMUX26_4", + "DSP_NW4END1_4", + "DSP_1_ACIN7", + "DSP_EE2A3_1", + "DSP_1_PCIN2", + "DSP_ER1BEG1_1", + "DSP_1_A22", + "DSP_1_A0", + "DSP_1_PCIN45", + "DSP_IMUX37_1", + "DSP_EE4A3_0", + "DSP_WW4A3_4", + "DSP_IMUX30_2", + "DSP_NW2A0_4", + "DSP_PCOUT13", + "DSP_NW4A2_0", + "DSP_0_ACOUT3", + "DSP_IMUX10_1", + "DSP_NW4END2_4", + "DSP_0_PCOUT26", + "DSP_WL1END2_4", + "DSP_EE4C1_1", + "DSP_1_PCOUT36", + "DSP_LOGIC_OUTS_B0_0", + "DSP_SE4BEG2_3", + "DSP_1_PCOUT16", + "DSP_WW4C3_4", + "DSP_WW4END0_2", + "DSP_IMUX34_0", + "DSP_0_ACIN0", + "DSP_ACOUT13", + "DSP_WW4B0_0", + "DSP_WW2A0_0", + "DSP_EL1BEG1_3", + "DSP_0_CARRYOUT3", + "DSP_EE4BEG0_4", + "DSP_IMUX17_0", + "DSP_LOGIC_OUTS_B10_0", + "DSP_SW4END0_4", + "DSP_1_PCIN16", + "DSP_1_P21", + "DSP_WW4END1_0", + "DSP_1_D22", + "DSP_BYP1_0", + "DSP_SW4A0_2", + "DSP_BLOCK_OUTS_B3_2", + "DSP_0_BCIN15", + "DSP_1_C18", + "DSP_SW2A2_1", + "DSP_LOGIC_OUTS_B23_0", + "DSP_EE4B3_4", + "DSP_NW4END2_0", + "DSP_LOGIC_OUTS_B15_0", + "DSP_1_A15", + "DSP_1_ACOUT14", + "DSP_IMUX39_3", + "DSP_IMUX36_1", + "DSP_NW2A2_3", + "DSP_0_A28", + "DSP_BYP7_3", + "DSP_LOGIC_OUTS_B22_3", + "DSP_0_A17", + "DSP_IMUX38_4", + "DSP_LOGIC_OUTS_B14_3", + "DSP_0_ALUMODE3", + "DSP_IMUX20_1", + "DSP_1_CARRYCASCIN", + "DSP_WR1END3_0", + "DSP_NW4END0_4", + "DSP_PCOUT19", + "DSP_1_D11", + "DSP_SE4C0_1", + "DSP_SW2A3_2", + "DSP_1_P13", + "DSP_BYP6_3", + "DSP_SW4A0_1", + "DSP_LOGIC_OUTS_B3_0", + "DSP_BCOUT7", + "DSP_IMUX9_2", + "DSP_LOGIC_OUTS_B19_0", + "DSP_SE2A3_1", + "DSP_WW4C2_1", + "DSP_ER1BEG0_3", + "DSP_BLOCK_OUTS_B2_4", + "DSP_LOGIC_OUTS_B20_2", + "DSP_IMUX47_1", + "DSP_NW4END3_0", + "DSP_1_ACIN28", + "DSP_SW4A3_0", + "DSP_IMUX47_2", + "DSP_SE4BEG1_2", + "DSP_NE4BEG3_1", + "DSP_1_PCIN13", + "DSP_0_PCOUT37", + "DSP_0_ACIN23", + "DSP_0_C17", + "DSP_LOGIC_OUTS_B14_0", + "DSP_SE2A0_3", + "DSP_IMUX4_2", + "DSP_NW4A2_3", + "DSP_NE2A2_4", + "DSP_0_C31", + "DSP_0_BCIN0", + "DSP_SW2A1_4", + "DSP_WL1END2_2", + "DSP_1_B11", + "DSP_1_C28", + "DSP_0_OPMODE3", + "DSP_1_ACIN13", + "DSP_LH1_2", + "DSP_LH6_1", + "DSP_0_RSTALUMODE", + "DSP_1_A13", + "DSP_1_PCOUT0", + "DSP_SE2A3_2", + "DSP_BLOCK_OUTS_B1_3", + "DSP_1_OPMODE1", + "DSP_0_INMODE4", + "DSP_NW4A0_1", + "DSP_EL1BEG2_1", + "DSP_0_D8", + "DSP_LOGIC_OUTS_B15_4", + "DSP_0_A21", + "DSP_LH11_2", + "DSP_WW4A1_3", + "DSP_NE4C1_3", + "DSP_0_A2", + "DSP_IMUX42_0", + "DSP_IMUX5_1", + "DSP_IMUX0_1", + "DSP_NE4BEG2_1", + "DSP_0_P43", + "DSP_1_BCIN0", + "DSP_NW2A2_2", + "DSP_LOGIC_OUTS_B9_4", + "DSP_0_PCOUT4", + "DSP_NE4C0_2", + "DSP_SE4C2_4", + "DSP_0_CED", + "DSP_NE2A1_2", + "DSP_0_PCIN17", + "DSP_0_PCIN19", + "DSP_IMUX31_1", + "DSP_0_ACIN8", + "DSP_1_PCIN37", + "DSP_1_ACOUT16", + "DSP_0_PCIN8", + "DSP_1_A1", + "DSP_1_PCIN34", + "DSP_EE4A3_3", + "DSP_LOGIC_OUTS_B23_2", + "DSP_IMUX1_4", + "DSP_0_BCIN1", + "DSP_NE2A1_0", + "DSP_WW4C1_0", + "DSP_0_CECTRL", + "DSP_CLK1_2", + "DSP_FAN5_1", + "DSP_1_PCOUT33", + "DSP_LOGIC_OUTS_B8_3", + "DSP_0_P14", + "DSP_1_PCOUT24", + "DSP_SE4BEG1_0", + "DSP_SW2A3_0", + "DSP_LOGIC_OUTS_B0_2", + "DSP_NW4A0_4", + "DSP_BYP4_2", + "DSP_1_A19", + "DSP_1_PCIN33", + "DSP_LOGIC_OUTS_B17_4", + "DSP_SE4C2_2", + "DSP_1_A16", + "DSP_IMUX24_4", + "DSP_PCOUT2", + "DSP_LOGIC_OUTS_B12_4", + "DSP_PCOUT46", + "DSP_LH5_1", + "DSP_WW2END2_2", + "DSP_SE2A3_0", + "DSP_IMUX25_1", + "DSP_0_D6", + "DSP_1_PCOUT11", + "DSP_BCOUT14", + "DSP_LOGIC_OUTS_B10_1", + "DSP_1_ACOUT18", + "DSP_FAN1_2", + "DSP_SW2A1_0", + "DSP_SE4C3_2", + "DSP_0_A22", + "DSP_1_P47", + "DSP_EE2BEG2_2", + "DSP_0_C40", + "DSP_WW4B2_2", + "DSP_IMUX7_4", + "DSP_1_CARRYIN", + "DSP_1_C22", + "DSP_SW4END2_0", + "DSP_IMUX37_4", + "DSP_WW2A3_0", + "DSP_0_C30", + "DSP_LOGIC_OUTS_B2_1", + "DSP_LOGIC_OUTS_B19_1", + "DSP_0_PCOUT32", + "DSP_1_C46", + "DSP_LOGIC_OUTS_B6_2", + "DSP_1_PATTERNBDETECT", + "DSP_WW4B0_1", + "DSP_0_OPMODE6", + "DSP_WW2A0_3", + "DSP_1_PCOUT5", + "DSP_IMUX31_4", + "DSP_1_PCOUT41", + "DSP_0_RSTINMODE", + "DSP_ACOUT27", + "DSP_PCOUT36", + "DSP_LOGIC_OUTS_B4_0", + "DSP_0_ACOUT23", + "DSP_NW4END1_3", + "DSP_LOGIC_OUTS_B19_3", + "DSP_WW4END2_3", + "DSP_0_P18", + "DSP_1_PCOUT17", + "DSP_0_BCIN11", + "DSP_MONITOR_N_0", + "DSP_0_BCOUT13", + "DSP_LOGIC_OUTS_B17_1", + "DSP_0_ACIN17", + "DSP_IMUX30_1", + "DSP_0_ACIN12", + "DSP_0_PCIN21", + "DSP_SW4A0_0", + "DSP_LH11_3", + "DSP_1_PCOUT37", + "DSP_LOGIC_OUTS_B16_0", + "DSP_1_B6", + "DSP_IMUX14_0", + "DSP_EE4B2_1", + "DSP_IMUX24_2", + "DSP_1_CARRYCASCOUT", + "DSP_LH5_2", + "DSP_IMUX39_1", + "DSP_SW4A3_4", + "DSP_BYP2_2", + "DSP_LH9_4", + "DSP_1_P11", + "DSP_0_C15", + "DSP_LH6_4", + "DSP_1_CEAD", + "DSP_IMUX11_2", + "DSP_0_P12", + "DSP_1_B2", + "DSP_FAN1_0", + "DSP_0_PCIN42", + "DSP_EE4B2_4", + "DSP_0_INMODE2", + "DSP_1_ACIN8", + "DSP_IMUX43_0", + "DSP_1_C27", + "DSP_LOGIC_OUTS_B3_4", + "DSP_FAN5_2", + "DSP_0_PCIN41", + "DSP_IMUX18_4", + "DSP_WW4C3_1", + "DSP_0_C45", + "DSP_WW4C2_0", + "DSP_LOGIC_OUTS_B9_0", + "DSP_1_C32", + "DSP_SE2A2_3", + "DSP_NE4C3_2", + "DSP_0_P25", + "DSP_WR1END3_1", + "DSP_IMUX19_1", + "DSP_WW4END3_0", + "DSP_EE4B2_3", + "DSP_WL1END3_3", + "DSP_1_P15", + "DSP_0_ACOUT20", + "DSP_EE4A0_0", + "DSP_LOGIC_OUTS_B6_0", + "DSP_ER1BEG1_3", + "DSP_1_PCIN23", + "DSP_0_ACOUT17", + "DSP_EE4B0_1", + "DSP_BYP2_0", + "DSP_1_P42", + "DSP_SE4C0_4", + "DSP_MONITOR_N_4", + "DSP_ACOUT0", + "DSP_1_D14", + "DSP_1_CARRYINSEL0", + "DSP_0_ACIN11", + "DSP_PCOUT38", + "DSP_0_ACOUT13", + "DSP_IMUX19_0", + "DSP_FAN6_0", + "DSP_0_D3", + "DSP_1_ACIN11", + "DSP_1_P34", + "DSP_SE2A3_3", + "DSP_FAN6_3", + "DSP_NE4C1_2", + "DSP_EE2A0_3", + "DSP_1_ACIN3", + "DSP_ACOUT5", + "DSP_LOGIC_OUTS_B21_1", + "DSP_SE4BEG0_2", + "DSP_SW4A3_1", + "DSP_LOGIC_OUTS_B18_3", + "DSP_0_PCIN9", + "DSP_EE2A2_3", + "DSP_1_ACIN23", + "DSP_0_B10", + "DSP_0_PCIN14", + "DSP_IMUX35_4", + "DSP_0_ACOUT29", + "DSP_PCOUT45", + "DSP_1_OPMODE6", + "DSP_WL1END3_2", + "DSP_SE2A2_4", + "DSP_0_ACOUT8", + "DSP_0_ACOUT9", + "DSP_PCOUT28", + "DSP_0_RSTP", + "DSP_WW2END1_1", + "DSP_BCOUT15", + "DSP_0_ACIN10", + "DSP_1_ACIN4", + "DSP_SW4END0_1", + "DSP_EE4A0_4", + "DSP_PCOUT30", + "DSP_0_B1", + "DSP_0_PCIN2", + "DSP_WL1END3_4", + "DSP_SE4BEG1_3", + "DSP_ER1BEG2_2", + "DSP_LOGIC_OUTS_B20_4", + "DSP_IMUX15_1", + "DSP_IMUX29_2", + "DSP_1_C4", + "DSP_0_RSTD", + "DSP_LOGIC_OUTS_B17_2", + "DSP_WW2A1_4", + "DSP_0_C32", + "DSP_EE2A3_0", + "DSP_0_A24", + "DSP_1_P28", + "DSP_PCOUT15", + "DSP_1_ACIN20", + "DSP_0_P27", + "DSP_0_PCOUT19", + "DSP_NE4C0_4", + "DSP_0_PCIN40", + "DSP_WL1END1_1", + "DSP_1_A12", + "DSP_0_C0", + "DSP_0_D23", + "DSP_NE4BEG0_0", + "DSP_0_PCIN15", + "DSP_LOGIC_OUTS_B0_1", + "DSP_1_PCIN38", + "DSP_IMUX32_3", + "DSP_ACOUT16", + "DSP_IMUX33_4", + "DSP_0_PCIN33", + "DSP_IMUX23_3", + "DSP_0_C20", + "DSP_1_C39", + "DSP_EE4B1_3", + "DSP_EE4C3_1", + "DSP_PCOUT20", + "DSP_IMUX2_3", + "DSP_LOGIC_OUTS_B16_2", + "DSP_LOGIC_OUTS_B8_1", + "DSP_0_A7", + "DSP_1_RSTA", + "DSP_0_P39", + "DSP_1_ACOUT17", + "DSP_PCOUT29", + "DSP_PCOUT34", + "DSP_FAN1_4", + "DSP_0_P21", + "DSP_0_C23", + "DSP_1_ALUMODE3", + "DSP_0_RSTC", + "DSP_IMUX38_2", + "DSP_IMUX27_1", + "DSP_EE2A2_0", + "DSP_BCOUT16", + "DSP_0_C8", + "DSP_0_PCOUT36", + "DSP_BYP1_3", + "DSP_LOGIC_OUTS_B22_2", + "DSP_NW4A3_1", + "DSP_1_ACOUT7", + "DSP_WR1END3_3", + "DSP_0_PCIN12", + "DSP_LOGIC_OUTS_B12_0", + "DSP_0_ACOUT26", + "DSP_0_OPMODE0", + "DSP_MONITOR_N_1", + "DSP_WW4END0_0", + "DSP_WW4C2_4", + "DSP_MONITOR_P_4", + "DSP_0_C29", + "DSP_1_ACIN15", + "DSP_IMUX44_3", + "DSP_WW4C0_2", + "DSP_1_PCIN19", + "DSP_IMUX25_3", + "DSP_BYP1_1", + "DSP_0_A9", + "DSP_0_ACIN24", + "DSP_IMUX10_4", + "DSP_LH4_0", + "DSP_0_D13", + "DSP_0_PCIN6", + "DSP_IMUX23_4", + "DSP_WW2A1_0", + "DSP_NE4BEG2_4", + "DSP_NE2A0_4", + "DSP_1_D23", + "DSP_SW4A2_4", + "DSP_1_ACOUT27", + "DSP_0_ACIN7", + "DSP_EL1BEG3_0", + "DSP_BYP2_3", + "DSP_CTRL1_2", + "DSP_EE4B0_2", + "DSP_ER1BEG3_1", + "DSP_0_CEAD", + "DSP_IMUX20_3", + "DSP_IMUX28_1", + "DSP_0_CEALUMODE", + "DSP_WW4A2_0", + "DSP_IMUX20_2", + "DSP_1_PCIN6", + "DSP_ACOUT1", + "DSP_SW2A3_1", + "DSP_0_P32", + "DSP_0_BCIN13", + "DSP_0_D2", + "DSP_NW2A0_2", + "DSP_EE2BEG2_1", + "DSP_0_ACOUT12", + "DSP_IMUX14_2", + "DSP_1_CARRYOUT0", + "DSP_WW4B0_3", + "DSP_IMUX23_1", + "DSP_IMUX5_4", + "DSP_1_P12", + "DSP_IMUX6_2", + "DSP_WL1END0_4", + "DSP_FAN2_1", + "DSP_WR1END0_0", + "DSP_IMUX43_4", + "DSP_LOGIC_OUTS_B21_0", + "DSP_IMUX27_4", + "DSP_IMUX13_4", + "DSP_EE4B1_0", + "DSP_0_PCIN22", + "DSP_NE4BEG2_2", + "DSP_IMUX38_3", + "DSP_NE2A1_3", + "DSP_0_ACOUT14", + "DSP_1_PCOUT39", + "DSP_0_A27", + "DSP_BYP3_0", + "DSP_NW4A3_4", + "DSP_EE4BEG2_2", + "DSP_1_CEALUMODE", + "DSP_0_PCIN13", + "DSP_0_PCOUT10", + "DSP_1_P26", + "DSP_ACOUT28", + "DSP_1_C37", + "DSP_IMUX41_1", + "DSP_PCOUT27", + "DSP_1_PCOUT6", + "DSP_0_ACOUT1", + "DSP_0_PCIN43", + "DSP_EE4BEG3_3", + "DSP_0_C46", + "DSP_1_C30", + "DSP_EE2BEG3_1", + "DSP_ACOUT10", + "DSP_LOGIC_OUTS_B13_2", + "DSP_0_RSTALLCARRYIN", + "DSP_WW4END2_0", + "DSP_0_PCOUT22", + "DSP_ER1BEG1_2", + "DSP_1_INMODE4", + "DSP_1_PCIN22", + "DSP_IMUX24_0", + "DSP_IMUX37_3", + "DSP_0_P33", + "DSP_1_D13", + "DSP_LOGIC_OUTS_B2_2", + "DSP_SE4BEG0_3", + "DSP_1_A27", + "DSP_WW2A3_2", + "DSP_NW4END3_3", + "DSP_0_PCOUT33", + "DSP_NE4BEG1_3", + "DSP_1_D15", + "DSP_IMUX11_3", + "DSP_1_P1", + "DSP_0_P34", + "DSP_1_A3", + "DSP_EE2A2_4", + "DSP_LH2_3", + "DSP_1_PCIN18", + "DSP_BCOUT1", + "DSP_PCOUT26", + "DSP_0_C37", + "DSP_0_PCOUT20", + "DSP_NE2A1_1", + "DSP_1_D12", + "DSP_EE4C1_2", + "DSP_1_B5", + "DSP_SW2A3_3", + "DSP_1_PCIN46", + "DSP_BCOUT0", + "DSP_1_BCOUT11", + "DSP_IMUX33_2", + "DSP_SE4BEG3_1", + "DSP_NE4BEG0_4", + "DSP_EE4C2_2", + "DSP_LOGIC_OUTS_B14_1", + "DSP_LOGIC_OUTS_B17_3", + "DSP_WW4END0_3", + "DSP_NE4C2_2", + "DSP_0_D4", + "DSP_ACOUT2", + "DSP_LH12_3", + "DSP_0_OPMODE1", + "DSP_EE2A0_1", + "DSP_WW2A0_1", + "DSP_NW4A2_2", + "DSP_0_PCIN0", + "DSP_NW4END0_0", + "DSP_1_C23", + "DSP_IMUX7_3", + "DSP_IMUX0_0", + "DSP_SW4END1_2", + "DSP_SW4END0_0", + "DSP_0_PCIN45", + "DSP_WW2A2_3", + "DSP_LH1_3", + "DSP_0_MULTSIGNIN", + "DSP_EE4B1_4", + "DSP_WW2A3_1", + "DSP_1_C34", + "DSP_0_BCIN6", + "DSP_LH7_3", + "DSP_LH3_2", + "DSP_BYP2_4", + "DSP_EE4A0_2", + "DSP_IMUX26_3", + "DSP_IMUX26_1", + "DSP_EE2BEG1_4", + "DSP_1_A9", + "DSP_IMUX28_2", + "DSP_0_D5", + "DSP_LOGIC_OUTS_B14_4", + "DSP_1_BCOUT16", + "DSP_LH2_4", + "DSP_0_PCOUT42", + "DSP_0_B13", + "DSP_CTRL0_2", + "DSP_1_ACOUT13", + "DSP_0_C5", + "DSP_WW4A0_2", + "DSP_LH3_4", + "DSP_0_BCOUT17", + "DSP_0_ACIN14", + "DSP_0_P13", + "DSP_0_A3", + "DSP_ER1BEG0_0", + "DSP_WW2A0_2", + "DSP_LH12_1", + "DSP_0_ACIN3", + "DSP_LOGIC_OUTS_B19_2", + "DSP_BYP5_1", + "DSP_SE4C1_4", + "DSP_PCOUT33", + "DSP_0_C42", + "DSP_IMUX35_2", + "DSP_IMUX27_3", + "DSP_0_B6", + "DSP_0_C3", + "DSP_NE4C1_4", + "DSP_IMUX40_3", + "DSP_SE2A1_0", + "DSP_BCOUT2", + "DSP_0_A20", + "DSP_IMUX41_3", + "DSP_EE4BEG0_1", + "DSP_IMUX37_0", + "DSP_EE4B2_2", + "DSP_1_BCOUT9", + "DSP_0_P35", + "DSP_1_BCIN2", + "DSP_1_BCOUT14", + "DSP_1_A17", + "DSP_PCOUT32", + "DSP_WW4A1_4", + "DSP_0_ACIN5", + "DSP_IMUX24_3", + "DSP_0_BCOUT11", + "DSP_1_P9", + "DSP_LOGIC_OUTS_B13_0", + "DSP_0_P7", + "DSP_1_RSTCTRL", + "DSP_IMUX2_2", + "DSP_1_ACOUT19", + "DSP_1_P43", + "DSP_EE4BEG1_3", + "DSP_WW4END1_1", + "DSP_NW4END1_1", + "DSP_WL1END3_0", + "DSP_WW2A3_4", + "DSP_ER1BEG0_2", + "DSP_1_PCOUT35", + "DSP_EE2BEG0_0", + "DSP_EE4C3_4", + "DSP_0_ACOUT27", + "DSP_LOGIC_OUTS_B2_4", + "DSP_0_CARRYIN", + "DSP_NE2A3_0", + "DSP_IMUX23_0", + "DSP_BLOCK_OUTS_B0_2", + "DSP_1_C2", + "DSP_WR1END2_4", + "DSP_ACOUT11", + "DSP_ACOUT15", + "DSP_ACOUT18", + "DSP_0_C6", + "DSP_WW4B0_2", + "DSP_NE4C1_0", + "DSP_LH7_2", + "DSP_1_D2", + "DSP_0_PCOUT31", + "DSP_0_ACOUT16", + "DSP_IMUX7_0", + "DSP_0_MULTSIGNOUT", + "DSP_1_D24", + "DSP_IMUX44_2", + "DSP_0_ACOUT4", + "DSP_SW4A0_4", + "DSP_BLOCK_OUTS_B0_3", + "DSP_0_ACOUT6", + "DSP_1_RSTB", + "DSP_1_C17", + "DSP_0_BCOUT2", + "DSP_LOGIC_OUTS_B1_3", + "DSP_0_P0", + "DSP_0_C39", + "DSP_0_P19", + "DSP_0_B11", + "DSP_MONITOR_N_2", + "DSP_1_PCIN24", + "DSP_WW4END0_4", + "DSP_IMUX8_3", + "DSP_EL1BEG1_4", + "DSP_FAN4_0", + "DSP_0_C21", + "DSP_SE4BEG2_4", + "DSP_1_PCOUT26", + "DSP_0_PCOUT1", + "DSP_IMUX30_0", + "DSP_0_CARRYCASCOUT", + "DSP_FAN4_3", + "DSP_0_PCIN37", + "DSP_1_P39", + "DSP_FAN0_4", + "DSP_IMUX44_1", + "DSP_BLOCK_OUTS_B2_1", + "DSP_LOGIC_OUTS_B2_3", + "DSP_CLK0_2", + "DSP_IMUX27_0", + "DSP_EE4C0_1", + "DSP_WL1END2_1", + "DSP_1_BCOUT5", + "DSP_WW2END1_0", + "DSP_EE2BEG0_4", + "DSP_1_ACOUT5", + "DSP_LH2_1", + "DSP_0_ACOUT7", + "DSP_0_CARRYOUT1", + "DSP_1_CARRYOUT2", + "DSP_SW4END1_3", + "DSP_WW4C1_3", + "DSP_IMUX7_1", + "DSP_PCOUT35", + "DSP_1_A7", + "DSP_EE4C2_4", + "DSP_0_BCOUT8", + "DSP_1_C25", + "DSP_LH4_2", + "DSP_0_PCOUT0", + "DSP_1_CEM", + "DSP_ER1BEG2_0", + "DSP_0_P23", + "DSP_0_CEA1", + "DSP_0_D10", + "DSP_EE4C3_2", + "DSP_1_P19", + "DSP_0_PCOUT47", + "DSP_LOGIC_OUTS_B11_1", + "DSP_0_ACOUT15", + "DSP_IMUX36_3", + "DSP_EE2A3_2", + "DSP_0_CEINMODE", + "DSP_1_BCIN8", + "DSP_0_BCIN12", + "DSP_IMUX0_3", + "DSP_0_CECARRYIN", + "DSP_1_C44", + "DSP_PCOUT10", + "DSP_LOGIC_OUTS_B0_4", + "DSP_NW2A3_2", + "DSP_0_RSTCTRL", + "DSP_1_CEP", + "DSP_SW4A1_0", + "DSP_1_PCOUT9", + "DSP_BYP0_3", + "DSP_EE2BEG1_1", + "DSP_NW4A1_2", + "DSP_0_PCIN23", + "DSP_IMUX31_3", + "DSP_0_PCIN20", + "DSP_1_ACIN25", + "DSP_WW4B3_0", + "DSP_EE4A2_0", + "DSP_LOGIC_OUTS_B8_4", + "DSP_0_PATTERNBDETECT", + "DSP_WW4C2_2", + "DSP_1_INMODE3", + "DSP_IMUX26_2", + "DSP_0_P37", + "DSP_IMUX21_0", + "DSP_LH8_0", + "DSP_IMUX45_2", + "DSP_SW2A1_1", + "DSP_LH7_1", + "DSP_WL1END3_1", + "DSP_0_PCIN34", + "DSP_SE4C0_3", + "DSP_0_B16", + "DSP_EE4A2_2", + "DSP_0_PCIN31", + "DSP_FAN7_2", + "DSP_0_B2", + "DSP_1_RSTALUMODE", + "DSP_1_B0", + "DSP_1_C1", + "DSP_1_BCIN3", + "DSP_1_C10", + "DSP_0_C28", + "DSP_1_RSTALLCARRYIN", + "DSP_IMUX31_0", + "DSP_1_UNDERFLOW", + "DSP_BYP1_2", + "DSP_WW4C0_1", + "DSP_0_CEB2", + "DSP_SE4C2_1", + "DSP_0_PCOUT27", + "DSP_1_ACOUT2", + "DSP_ACOUT17", + "DSP_1_MULTSIGNIN", + "DSP_1_C9", + "DSP_1_B7", + "DSP_1_BCIN7", + "DSP_1_PCOUT1", + "DSP_EE4C0_0", + "DSP_ER1BEG3_2", + "DSP_IMUX21_4", + "DSP_IMUX16_3", + "DSP_1_ACOUT11", + "DSP_SE4BEG1_4", + "DSP_LOGIC_OUTS_B22_0", + "DSP_ACOUT20", + "DSP_ER1BEG1_4", + "DSP_EE4A0_1", + "DSP_1_B8", + "DSP_LOGIC_OUTS_B7_2", + "DSP_0_ACOUT11", + "DSP_0_B15", + "DSP_IMUX16_4", + "DSP_BCOUT10", + "DSP_WW4B1_0", + "DSP_IMUX9_4", + "DSP_WW4A2_4", + "DSP_IMUX40_2", + "DSP_IMUX32_4", + "DSP_WL1END0_3", + "DSP_0_PCOUT29" + ], + "pips": { + "DSP_L.DSP_IMUX10_0->DSP_1_C21": { + "src_wire": "DSP_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT7->DSP_1_PCIN7": { + "src_wire": "DSP_0_PCOUT7", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_CTRL0_4->DSP_1_RSTP": { + "src_wire": "DSP_CTRL0_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTP", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT0->DSP_1_ACIN0": { + "src_wire": "DSP_0_ACOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN6_0->DSP_1_D1": { + "src_wire": "DSP_FAN6_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_D1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN4_4->DSP_1_D19": { + "src_wire": "DSP_FAN4_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_D19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT14->DSP_1_BCIN14": { + "src_wire": "DSP_0_BCOUT14", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_ALUMODE2": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT9->DSP_1_ACIN9": { + "src_wire": "DSP_0_ACOUT9", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX4_0->DSP_1_A23": { + "src_wire": "DSP_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX3_0->DSP_0_C1": { + "src_wire": "DSP_IMUX3_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT24->DSP_1_PCIN24": { + "src_wire": "DSP_0_PCOUT24", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP1_4->DSP_0_D19": { + "src_wire": "DSP_BYP1_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_D19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PATTERNDETECT->DSP_LOGIC_OUTS_B13_2": { + "src_wire": "DSP_1_PATTERNDETECT", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D7": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_CARRYOUT0->DSP_LOGIC_OUTS_B8_3": { + "src_wire": "DSP_1_CARRYOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX1_1->DSP_0_CEB2": { + "src_wire": "DSP_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEB2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D8": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN0_3->DSP_1_CED": { + "src_wire": "DSP_FAN0_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CED", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D3": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX24_2->DSP_1_C31": { + "src_wire": "DSP_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C31", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX19_4->DSP_0_C46": { + "src_wire": "DSP_IMUX19_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C46", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP6_0->DSP_0_D20": { + "src_wire": "DSP_BYP6_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_D20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT15->DSP_BCOUT15": { + "src_wire": "DSP_1_BCOUT15", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX16_0->DSP_0_C41": { + "src_wire": "DSP_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C41", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX47_2->DSP_0_A28": { + "src_wire": "DSP_IMUX47_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_A28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D23": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_INMODE4": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P37->DSP_LOGIC_OUTS_B22_4": { + "src_wire": "DSP_0_P37", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX19_0->DSP_0_A1": { + "src_wire": "DSP_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX32_3->DSP_0_C35": { + "src_wire": "DSP_IMUX32_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C35", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_UNDERFLOW->DSP_LOGIC_OUTS_B14_3": { + "src_wire": "DSP_1_UNDERFLOW", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_CARRYOUT3->DSP_LOGIC_OUTS_B10_1": { + "src_wire": "DSP_0_CARRYOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN4_3->DSP_1_D15": { + "src_wire": "DSP_FAN4_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_D15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT27->DSP_1_PCIN27": { + "src_wire": "DSP_0_PCOUT27", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX3_4->DSP_0_B17": { + "src_wire": "DSP_IMUX3_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_B17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P10->DSP_LOGIC_OUTS_B16_2": { + "src_wire": "DSP_0_P10", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P41->DSP_LOGIC_OUTS_B12_0": { + "src_wire": "DSP_0_P41", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B12_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP7_3->DSP_0_D12": { + "src_wire": "DSP_BYP7_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_D12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX25_0->DSP_1_C43": { + "src_wire": "DSP_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C43", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX11_1->DSP_1_A5": { + "src_wire": "DSP_IMUX11_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P7->DSP_LOGIC_OUTS_B18_1": { + "src_wire": "DSP_0_P7", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT13->DSP_BCOUT13": { + "src_wire": "DSP_1_BCOUT13", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D13": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX46_1->DSP_0_A26": { + "src_wire": "DSP_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX15_1->DSP_1_A4": { + "src_wire": "DSP_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_CEALUMODE": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P6->DSP_LOGIC_OUTS_B16_1": { + "src_wire": "DSP_0_P6", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT14->DSP_1_ACIN14": { + "src_wire": "DSP_0_ACOUT14", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX10_1->DSP_1_B5": { + "src_wire": "DSP_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_RSTD": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D13": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D10": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN7_4->DSP_1_INMODE2": { + "src_wire": "DSP_FAN7_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN1_0->DSP_1_D20": { + "src_wire": "DSP_FAN1_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_D20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT6->DSP_1_BCIN6": { + "src_wire": "DSP_0_BCOUT6", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN2_3->DSP_1_CEINMODE": { + "src_wire": "DSP_FAN2_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX44_2->DSP_1_B10": { + "src_wire": "DSP_IMUX44_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_B10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P16->DSP_LOGIC_OUTS_B3_4": { + "src_wire": "DSP_1_P16", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX1_2->DSP_0_CEM": { + "src_wire": "DSP_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEM", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN6_4->DSP_1_D17": { + "src_wire": "DSP_FAN6_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_D17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX28_1->DSP_1_B6": { + "src_wire": "DSP_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP4_1->DSP_0_RSTD": { + "src_wire": "DSP_BYP4_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_CARRYOUT1->DSP_LOGIC_OUTS_B11_1": { + "src_wire": "DSP_0_CARRYOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT10->DSP_ACOUT10": { + "src_wire": "DSP_1_ACOUT10", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PATTERNBDETECT->DSP_LOGIC_OUTS_B14_2": { + "src_wire": "DSP_0_PATTERNBDETECT", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX45_2->DSP_1_A28": { + "src_wire": "DSP_IMUX45_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_A28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN4_2->DSP_1_D11": { + "src_wire": "DSP_FAN4_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_D11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX18_2->DSP_0_B9": { + "src_wire": "DSP_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_B9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT12->DSP_1_PCIN12": { + "src_wire": "DSP_0_PCOUT12", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX29_2->DSP_1_C10": { + "src_wire": "DSP_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT16->DSP_1_BCIN16": { + "src_wire": "DSP_0_BCOUT16", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX2_0->DSP_1_C42": { + "src_wire": "DSP_IMUX2_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C42", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_OPMODE6": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT11->DSP_1_BCIN11": { + "src_wire": "DSP_0_BCOUT11", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D19": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D16": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX23_0->DSP_0_A0": { + "src_wire": "DSP_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX11_3->DSP_1_CECTRL": { + "src_wire": "DSP_IMUX11_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CECTRL", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT9->DSP_1_BCIN9": { + "src_wire": "DSP_0_BCOUT9", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX39_0->DSP_0_C0": { + "src_wire": "DSP_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX12_4->DSP_1_C38": { + "src_wire": "DSP_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C38", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P43->DSP_LOGIC_OUTS_B8_0": { + "src_wire": "DSP_0_P43", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX16_3->DSP_1_CEB2": { + "src_wire": "DSP_IMUX16_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEB2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX12_0->DSP_1_C22": { + "src_wire": "DSP_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX26_3->DSP_1_CECARRYIN": { + "src_wire": "DSP_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CECARRYIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX43_1->DSP_0_RSTCTRL": { + "src_wire": "DSP_IMUX43_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D5": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_CEAD": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEAD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_CED": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_CED", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT39->DSP_1_PCIN39": { + "src_wire": "DSP_0_PCOUT39", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN39", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT24->DSP_ACOUT24": { + "src_wire": "DSP_1_ACOUT24", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX20_4->DSP_0_C38": { + "src_wire": "DSP_IMUX20_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C38", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX5_1->DSP_1_A25": { + "src_wire": "DSP_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP1_2->DSP_0_D11": { + "src_wire": "DSP_BYP1_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_D11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D22": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D12": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX33_0->DSP_0_C43": { + "src_wire": "DSP_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C43", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D21": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P0->DSP_LOGIC_OUTS_B3_0": { + "src_wire": "DSP_1_P0", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P41->DSP_LOGIC_OUTS_B11_0": { + "src_wire": "DSP_1_P41", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT43->DSP_PCOUT43": { + "src_wire": "DSP_1_PCOUT43", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT43", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT33->DSP_PCOUT33": { + "src_wire": "DSP_1_PCOUT33", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT33", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX32_1->DSP_0_C27": { + "src_wire": "DSP_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT7->DSP_1_BCIN7": { + "src_wire": "DSP_0_BCOUT7", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT11->DSP_1_ACIN11": { + "src_wire": "DSP_0_ACOUT11", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN7_3->DSP_1_D23": { + "src_wire": "DSP_FAN7_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_D23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX6_4->DSP_0_A19": { + "src_wire": "DSP_IMUX6_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_A19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT1->DSP_1_PCIN1": { + "src_wire": "DSP_0_PCOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX20_0->DSP_0_C22": { + "src_wire": "DSP_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_OPMODE6": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D14": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX22_1->DSP_0_C24": { + "src_wire": "DSP_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P40->DSP_LOGIC_OUTS_B13_0": { + "src_wire": "DSP_0_P40", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_INMODE2": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP0_2->DSP_0_D22": { + "src_wire": "DSP_BYP0_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_D22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_CED": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_CED", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT22->DSP_ACOUT22": { + "src_wire": "DSP_1_ACOUT22", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P18->DSP_LOGIC_OUTS_B6_4": { + "src_wire": "DSP_1_P18", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT15->DSP_ACOUT15": { + "src_wire": "DSP_1_ACOUT15", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX4_1->DSP_1_A27": { + "src_wire": "DSP_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT4->DSP_1_BCIN4": { + "src_wire": "DSP_0_BCOUT4", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT23->DSP_1_PCIN23": { + "src_wire": "DSP_0_PCOUT23", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX35_2->DSP_0_OPMODE0": { + "src_wire": "DSP_IMUX35_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX45_3->DSP_1_A12": { + "src_wire": "DSP_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_A12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX34_1->DSP_0_C25": { + "src_wire": "DSP_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_CEALUMODE": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT22->DSP_1_PCIN22": { + "src_wire": "DSP_0_PCOUT22", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT21->DSP_ACOUT21": { + "src_wire": "DSP_1_ACOUT21", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX0_0->DSP_1_B3": { + "src_wire": "DSP_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_B3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT10->DSP_1_PCIN10": { + "src_wire": "DSP_0_PCOUT10", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX42_1->DSP_0_RSTINMODE": { + "src_wire": "DSP_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT13->DSP_1_ACIN13": { + "src_wire": "DSP_0_ACOUT13", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX21_1->DSP_0_A6": { + "src_wire": "DSP_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT8->DSP_1_BCIN8": { + "src_wire": "DSP_0_BCOUT8", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_CEINMODE": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT11->DSP_BCOUT11": { + "src_wire": "DSP_1_BCOUT11", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT0->DSP_PCOUT0": { + "src_wire": "DSP_1_PCOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P16->DSP_LOGIC_OUTS_B21_4": { + "src_wire": "DSP_0_P16", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D24": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT18->DSP_ACOUT18": { + "src_wire": "DSP_1_ACOUT18", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_INMODE1": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D10": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX36_2->DSP_0_B10": { + "src_wire": "DSP_IMUX36_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_B10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX7_4->DSP_0_A17": { + "src_wire": "DSP_IMUX7_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_A17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D9": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P17->DSP_LOGIC_OUTS_B1_4": { + "src_wire": "DSP_1_P17", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_CTRL0_2->DSP_0_RSTB": { + "src_wire": "DSP_CTRL0_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTB", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT13->DSP_PCOUT13": { + "src_wire": "DSP_1_PCOUT13", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P44->DSP_LOGIC_OUTS_B9_4": { + "src_wire": "DSP_0_P44", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B9_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P47->DSP_LOGIC_OUTS_B15_4": { + "src_wire": "DSP_1_P47", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D16": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_CEINMODE": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D6": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX43_4->DSP_0_B16": { + "src_wire": "DSP_IMUX43_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_B16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX13_1->DSP_1_A6": { + "src_wire": "DSP_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT1->DSP_1_ACIN1": { + "src_wire": "DSP_0_ACOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX7_3->DSP_0_A13": { + "src_wire": "DSP_IMUX7_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_A13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX27_2->DSP_0_OPMODE2": { + "src_wire": "DSP_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P25->DSP_LOGIC_OUTS_B5_1": { + "src_wire": "DSP_1_P25", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT29->DSP_ACOUT29": { + "src_wire": "DSP_1_ACOUT29", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN6_1->DSP_1_D5": { + "src_wire": "DSP_FAN6_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX17_2->DSP_0_A11": { + "src_wire": "DSP_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_A11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX7_2->DSP_0_A29": { + "src_wire": "DSP_IMUX7_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_A29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT20->DSP_1_ACIN20": { + "src_wire": "DSP_0_ACOUT20", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT44->DSP_PCOUT44": { + "src_wire": "DSP_1_PCOUT44", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT44", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP7_4->DSP_0_D16": { + "src_wire": "DSP_BYP7_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_D16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT5->DSP_ACOUT5": { + "src_wire": "DSP_1_ACOUT5", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX34_4->DSP_0_C44": { + "src_wire": "DSP_IMUX34_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C44", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P34->DSP_LOGIC_OUTS_B20_3": { + "src_wire": "DSP_0_P34", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D9": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT5->DSP_1_PCIN5": { + "src_wire": "DSP_0_PCOUT5", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP2_4->DSP_1_CARRYINSEL2": { + "src_wire": "DSP_BYP2_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D0": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT10->DSP_1_ACIN10": { + "src_wire": "DSP_0_ACOUT10", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX3_3->DSP_0_B13": { + "src_wire": "DSP_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_B13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P1->DSP_LOGIC_OUTS_B23_0": { + "src_wire": "DSP_0_P1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT41->DSP_1_PCIN41": { + "src_wire": "DSP_0_PCOUT41", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN41", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT47->DSP_PCOUT47": { + "src_wire": "DSP_1_PCOUT47", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT47", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_CTRL0_0->DSP_0_RSTP": { + "src_wire": "DSP_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTP", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P33->DSP_LOGIC_OUTS_B19_3": { + "src_wire": "DSP_0_P33", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT4->DSP_1_PCIN4": { + "src_wire": "DSP_0_PCOUT4", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P31->DSP_LOGIC_OUTS_B22_2": { + "src_wire": "DSP_0_P31", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT11->DSP_PCOUT11": { + "src_wire": "DSP_1_PCOUT11", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT2->DSP_PCOUT2": { + "src_wire": "DSP_1_PCOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D22": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX7_1->DSP_0_A25": { + "src_wire": "DSP_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX25_1->DSP_1_C7": { + "src_wire": "DSP_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT26->DSP_1_ACIN26": { + "src_wire": "DSP_0_ACOUT26", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D20": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX8_1->DSP_1_B7": { + "src_wire": "DSP_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX21_3->DSP_0_ALUMODE0": { + "src_wire": "DSP_IMUX21_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX29_1->DSP_1_C6": { + "src_wire": "DSP_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_CEAD": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEAD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P47->DSP_LOGIC_OUTS_B8_4": { + "src_wire": "DSP_0_P47", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX38_0->DSP_0_C20": { + "src_wire": "DSP_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT0->DSP_1_BCIN0": { + "src_wire": "DSP_0_BCOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT22->DSP_1_ACIN22": { + "src_wire": "DSP_0_ACOUT22", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX26_1->DSP_1_C25": { + "src_wire": "DSP_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_RSTD": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_ALUMODE3": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT25->DSP_1_ACIN25": { + "src_wire": "DSP_0_ACOUT25", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_ALUMODE2": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_CARRYOUT3->DSP_LOGIC_OUTS_B15_3": { + "src_wire": "DSP_1_CARRYOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_MULTSIGNOUT->DSP_MULTSIGNOUT": { + "src_wire": "DSP_1_MULTSIGNOUT", + "is_pseudo": "0", + "dst_wire": "DSP_MULTSIGNOUT", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX2_1->DSP_0_RSTALLCARRYIN": { + "src_wire": "DSP_IMUX2_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTALLCARRYIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D11": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX16_2->DSP_0_B11": { + "src_wire": "DSP_IMUX16_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_B11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT34->DSP_PCOUT34": { + "src_wire": "DSP_1_PCOUT34", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT34", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P39->DSP_LOGIC_OUTS_B5_4": { + "src_wire": "DSP_1_P39", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT13->DSP_1_PCIN13": { + "src_wire": "DSP_0_PCOUT13", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX30_0->DSP_1_C20": { + "src_wire": "DSP_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D12": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX42_4->DSP_1_B16": { + "src_wire": "DSP_IMUX42_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_B16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT17->DSP_1_ACIN17": { + "src_wire": "DSP_0_ACOUT17", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D2": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX44_4->DSP_1_A18": { + "src_wire": "DSP_IMUX44_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_A18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT26->DSP_PCOUT26": { + "src_wire": "DSP_1_PCOUT26", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP3_4->DSP_0_D18": { + "src_wire": "DSP_BYP3_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_D18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT21->DSP_1_ACIN21": { + "src_wire": "DSP_0_ACOUT21", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P18->DSP_LOGIC_OUTS_B16_4": { + "src_wire": "DSP_0_P18", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT5->DSP_1_ACIN5": { + "src_wire": "DSP_0_ACOUT5", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX4_2->DSP_0_C30": { + "src_wire": "DSP_IMUX4_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C30", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX14_1->DSP_1_C24": { + "src_wire": "DSP_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D3": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P42->DSP_LOGIC_OUTS_B10_0": { + "src_wire": "DSP_1_P42", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX6_1->DSP_0_A27": { + "src_wire": "DSP_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D19": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX9_2->DSP_1_A11": { + "src_wire": "DSP_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_A11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_CARRYINSEL2": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT33->DSP_1_PCIN33": { + "src_wire": "DSP_0_PCOUT33", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN33", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX6_2->DSP_0_C28": { + "src_wire": "DSP_IMUX6_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT0->DSP_ACOUT0": { + "src_wire": "DSP_1_ACOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_INMODE2": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT44->DSP_1_PCIN44": { + "src_wire": "DSP_0_PCOUT44", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN44", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P35->DSP_LOGIC_OUTS_B22_3": { + "src_wire": "DSP_0_P35", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT19->DSP_1_ACIN19": { + "src_wire": "DSP_0_ACOUT19", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT24->DSP_1_ACIN24": { + "src_wire": "DSP_0_ACOUT24", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_CEALUMODE": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT38->DSP_PCOUT38": { + "src_wire": "DSP_1_PCOUT38", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT38", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN6_2->DSP_1_D9": { + "src_wire": "DSP_FAN6_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_D9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT10->DSP_PCOUT10": { + "src_wire": "DSP_1_PCOUT10", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_CEAD": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEAD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P5->DSP_LOGIC_OUTS_B1_1": { + "src_wire": "DSP_1_P5", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT24->DSP_PCOUT24": { + "src_wire": "DSP_1_PCOUT24", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX38_2->DSP_0_OPMODE3": { + "src_wire": "DSP_IMUX38_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX31_2->DSP_1_C8": { + "src_wire": "DSP_IMUX31_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX0_1->DSP_0_CEA2": { + "src_wire": "DSP_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEA2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT6->DSP_1_ACIN6": { + "src_wire": "DSP_0_ACOUT6", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT42->DSP_1_PCIN42": { + "src_wire": "DSP_0_PCOUT42", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN42", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX35_3->DSP_0_C13": { + "src_wire": "DSP_IMUX35_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT3->DSP_ACOUT3": { + "src_wire": "DSP_1_ACOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX16_1->DSP_0_B7": { + "src_wire": "DSP_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT45->DSP_1_PCIN45": { + "src_wire": "DSP_0_PCOUT45", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN45", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT27->DSP_ACOUT27": { + "src_wire": "DSP_1_ACOUT27", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P10->DSP_LOGIC_OUTS_B6_2": { + "src_wire": "DSP_1_P10", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT26->DSP_ACOUT26": { + "src_wire": "DSP_1_ACOUT26", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_RSTD": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D14": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX22_0->DSP_0_B0": { + "src_wire": "DSP_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_B0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX29_4->DSP_1_C45": { + "src_wire": "DSP_IMUX29_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C45", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX26_0->DSP_1_B1": { + "src_wire": "DSP_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_B1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_INMODE0": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_INMODE3": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT16->DSP_ACOUT16": { + "src_wire": "DSP_1_ACOUT16", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D13": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX20_1->DSP_0_C26": { + "src_wire": "DSP_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_CTRL0_3->DSP_1_RSTC": { + "src_wire": "DSP_CTRL0_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTC", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX11_0->DSP_1_A1": { + "src_wire": "DSP_IMUX11_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT6->DSP_1_PCIN6": { + "src_wire": "DSP_0_PCOUT6", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX37_2->DSP_0_C10": { + "src_wire": "DSP_IMUX37_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT26->DSP_1_PCIN26": { + "src_wire": "DSP_0_PCOUT26", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT29->DSP_1_PCIN29": { + "src_wire": "DSP_0_PCOUT29", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D11": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D22": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P7->DSP_LOGIC_OUTS_B4_1": { + "src_wire": "DSP_1_P7", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT12->DSP_1_ACIN12": { + "src_wire": "DSP_0_ACOUT12", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_ALUMODE2": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX31_3->DSP_1_C12": { + "src_wire": "DSP_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX47_0->DSP_0_A20": { + "src_wire": "DSP_IMUX47_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX39_4->DSP_0_C16": { + "src_wire": "DSP_IMUX39_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX12_1->DSP_1_C26": { + "src_wire": "DSP_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P14->DSP_LOGIC_OUTS_B6_3": { + "src_wire": "DSP_1_P14", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P11->DSP_LOGIC_OUTS_B18_2": { + "src_wire": "DSP_0_P11", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX42_2->DSP_1_B9": { + "src_wire": "DSP_IMUX42_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_B9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D0": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX23_4->DSP_1_RSTINMODE": { + "src_wire": "DSP_IMUX23_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_CARRYINSEL2": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P34->DSP_LOGIC_OUTS_B2_3": { + "src_wire": "DSP_1_P34", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT4->DSP_BCOUT4": { + "src_wire": "DSP_1_BCOUT4", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D17": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P23->DSP_LOGIC_OUTS_B22_0": { + "src_wire": "DSP_0_P23", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX18_1->DSP_0_B5": { + "src_wire": "DSP_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX28_3->DSP_1_OPMODE0": { + "src_wire": "DSP_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX41_3->DSP_1_B12": { + "src_wire": "DSP_IMUX41_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_B12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D3": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX37_0->DSP_0_C2": { + "src_wire": "DSP_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D9": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT19->DSP_1_PCIN19": { + "src_wire": "DSP_0_PCOUT19", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX29_0->DSP_1_C2": { + "src_wire": "DSP_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP2_3->DSP_0_D23": { + "src_wire": "DSP_BYP2_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_D23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P14->DSP_LOGIC_OUTS_B16_3": { + "src_wire": "DSP_0_P14", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN0_1->DSP_0_CED": { + "src_wire": "DSP_FAN0_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CED", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT12->DSP_BCOUT12": { + "src_wire": "DSP_1_BCOUT12", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT3->DSP_1_BCIN3": { + "src_wire": "DSP_0_BCOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT13->DSP_1_BCIN13": { + "src_wire": "DSP_0_BCOUT13", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT15->DSP_PCOUT15": { + "src_wire": "DSP_1_PCOUT15", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P3->DSP_LOGIC_OUTS_B18_0": { + "src_wire": "DSP_0_P3", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT9->DSP_BCOUT9": { + "src_wire": "DSP_1_BCOUT9", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN7_2->DSP_0_OPMODE6": { + "src_wire": "DSP_FAN7_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN1_2->DSP_0_INMODE2": { + "src_wire": "DSP_FAN1_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX44_1->DSP_1_A26": { + "src_wire": "DSP_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT21->DSP_PCOUT21": { + "src_wire": "DSP_1_PCOUT21", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX1_3->DSP_1_B13": { + "src_wire": "DSP_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_B13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_OPMODE6": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D13": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D24": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT25->DSP_ACOUT25": { + "src_wire": "DSP_1_ACOUT25", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN3_0->DSP_1_D0": { + "src_wire": "DSP_FAN3_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_D0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX11_2->DSP_1_A9": { + "src_wire": "DSP_IMUX11_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_A9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX41_4->DSP_1_C19": { + "src_wire": "DSP_IMUX41_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P23->DSP_LOGIC_OUTS_B0_0": { + "src_wire": "DSP_1_P23", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP6_4->DSP_1_RSTD": { + "src_wire": "DSP_BYP6_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX37_3->DSP_0_C14": { + "src_wire": "DSP_IMUX37_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P4->DSP_LOGIC_OUTS_B21_1": { + "src_wire": "DSP_0_P4", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_CTRL1_1->DSP_0_RSTM": { + "src_wire": "DSP_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTM", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT14->DSP_BCOUT14": { + "src_wire": "DSP_1_BCOUT14", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P19->DSP_LOGIC_OUTS_B18_4": { + "src_wire": "DSP_0_P19", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P21->DSP_LOGIC_OUTS_B19_0": { + "src_wire": "DSP_0_P21", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D6": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX35_0->DSP_0_C40": { + "src_wire": "DSP_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C40", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX28_4->DSP_1_CARRYINSEL1": { + "src_wire": "DSP_IMUX28_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX30_3->DSP_0_CARRYINSEL0": { + "src_wire": "DSP_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT9->DSP_1_PCIN9": { + "src_wire": "DSP_0_PCOUT9", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_OPMODE6": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_CARRYOUT0->DSP_LOGIC_OUTS_B12_1": { + "src_wire": "DSP_0_CARRYOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B12_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN5_2->DSP_1_D10": { + "src_wire": "DSP_FAN5_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_D10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN2_2->DSP_1_INMODE4": { + "src_wire": "DSP_FAN2_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT10->DSP_BCOUT10": { + "src_wire": "DSP_1_BCOUT10", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX8_0->DSP_1_C41": { + "src_wire": "DSP_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C41", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT31->DSP_PCOUT31": { + "src_wire": "DSP_1_PCOUT31", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT31", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT20->DSP_ACOUT20": { + "src_wire": "DSP_1_ACOUT20", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX8_2->DSP_1_B11": { + "src_wire": "DSP_IMUX8_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_B11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX14_2->DSP_1_B8": { + "src_wire": "DSP_IMUX14_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_B8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P32->DSP_LOGIC_OUTS_B7_3": { + "src_wire": "DSP_1_P32", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT8->DSP_1_ACIN8": { + "src_wire": "DSP_0_ACOUT8", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP5_2->DSP_0_D9": { + "src_wire": "DSP_BYP5_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_D9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PATTERNDETECT->DSP_LOGIC_OUTS_B11_2": { + "src_wire": "DSP_0_PATTERNDETECT", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT2->DSP_1_BCIN2": { + "src_wire": "DSP_0_BCOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_INMODE4": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX20_2->DSP_0_OPMODE4": { + "src_wire": "DSP_IMUX20_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX15_4->DSP_1_RSTALLCARRYIN": { + "src_wire": "DSP_IMUX15_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTALLCARRYIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_CEINMODE": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT43->DSP_1_PCIN43": { + "src_wire": "DSP_0_PCOUT43", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN43", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT12->DSP_PCOUT12": { + "src_wire": "DSP_1_PCOUT12", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT29->DSP_PCOUT29": { + "src_wire": "DSP_1_PCOUT29", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_INMODE1": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT18->DSP_PCOUT18": { + "src_wire": "DSP_1_PCOUT18", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_INMODE1": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P22->DSP_LOGIC_OUTS_B2_0": { + "src_wire": "DSP_1_P22", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX26_2->DSP_1_CEP": { + "src_wire": "DSP_IMUX26_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEP", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D8": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX27_4->DSP_1_C17": { + "src_wire": "DSP_IMUX27_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P46->DSP_LOGIC_OUTS_B13_4": { + "src_wire": "DSP_0_P46", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D7": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN2_4->DSP_1_OPMODE6": { + "src_wire": "DSP_FAN2_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT9->DSP_PCOUT9": { + "src_wire": "DSP_1_PCOUT9", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX11_4->DSP_1_C46": { + "src_wire": "DSP_IMUX11_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C46", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX40_3->DSP_1_B14": { + "src_wire": "DSP_IMUX40_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_B14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX30_1->DSP_1_B4": { + "src_wire": "DSP_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_UNDERFLOW->DSP_LOGIC_OUTS_B9_2": { + "src_wire": "DSP_0_UNDERFLOW", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B9_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_CLK0_1->DSP_0_CLK": { + "src_wire": "DSP_CLK0_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P46->DSP_LOGIC_OUTS_B14_4": { + "src_wire": "DSP_1_P46", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT17->DSP_ACOUT17": { + "src_wire": "DSP_1_ACOUT17", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX5_2->DSP_1_A29": { + "src_wire": "DSP_IMUX5_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_A29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX17_0->DSP_0_A3": { + "src_wire": "DSP_IMUX17_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP5_4->DSP_0_D17": { + "src_wire": "DSP_BYP5_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_D17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D4": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT11->DSP_ACOUT11": { + "src_wire": "DSP_1_ACOUT11", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P24->DSP_LOGIC_OUTS_B7_1": { + "src_wire": "DSP_1_P24", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX21_4->DSP_0_C18": { + "src_wire": "DSP_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX8_3->DSP_1_CEB1": { + "src_wire": "DSP_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEB1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P32->DSP_LOGIC_OUTS_B17_3": { + "src_wire": "DSP_0_P32", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX30_4->DSP_1_C36": { + "src_wire": "DSP_IMUX30_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C36", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX16_4->DSP_1_OPMODE3": { + "src_wire": "DSP_IMUX16_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT2->DSP_1_ACIN2": { + "src_wire": "DSP_0_ACOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX33_3->DSP_0_C15": { + "src_wire": "DSP_IMUX33_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P45->DSP_LOGIC_OUTS_B10_4": { + "src_wire": "DSP_0_P45", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_CARRYOUT2->DSP_LOGIC_OUTS_B10_3": { + "src_wire": "DSP_1_CARRYOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX2_2->DSP_0_C29": { + "src_wire": "DSP_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D17": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX32_2->DSP_0_C31": { + "src_wire": "DSP_IMUX32_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C31", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D21": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D0": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT37->DSP_PCOUT37": { + "src_wire": "DSP_1_PCOUT37", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT37", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT1->DSP_ACOUT1": { + "src_wire": "DSP_1_ACOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_CED": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_CED", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX47_1->DSP_0_A24": { + "src_wire": "DSP_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P26->DSP_LOGIC_OUTS_B2_1": { + "src_wire": "DSP_1_P26", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT19->DSP_ACOUT19": { + "src_wire": "DSP_1_ACOUT19", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_RSTD": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX47_3->DSP_0_A12": { + "src_wire": "DSP_IMUX47_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_A12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_ALUMODE2": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_INMODE2": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX46_4->DSP_0_A18": { + "src_wire": "DSP_IMUX46_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_A18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P42->DSP_LOGIC_OUTS_B9_0": { + "src_wire": "DSP_0_P42", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B9_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX4_3->DSP_1_A15": { + "src_wire": "DSP_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_A15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX15_0->DSP_1_A0": { + "src_wire": "DSP_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D21": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX41_2->DSP_0_CECTRL": { + "src_wire": "DSP_IMUX41_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_CECTRL", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT5->DSP_PCOUT5": { + "src_wire": "DSP_1_PCOUT5", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P30->DSP_LOGIC_OUTS_B2_2": { + "src_wire": "DSP_1_P30", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D5": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT18->DSP_1_ACIN18": { + "src_wire": "DSP_0_ACOUT18", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P17->DSP_LOGIC_OUTS_B23_4": { + "src_wire": "DSP_0_P17", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT23->DSP_ACOUT23": { + "src_wire": "DSP_1_ACOUT23", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN5_1->DSP_1_D6": { + "src_wire": "DSP_FAN5_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT16->DSP_BCOUT16": { + "src_wire": "DSP_1_BCOUT16", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT28->DSP_1_ACIN28": { + "src_wire": "DSP_0_ACOUT28", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT3->DSP_PCOUT3": { + "src_wire": "DSP_1_PCOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D18": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_CTRL1_4->DSP_1_RSTB": { + "src_wire": "DSP_CTRL1_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTB", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX34_0->DSP_0_B1": { + "src_wire": "DSP_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_B1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX22_2->DSP_0_B8": { + "src_wire": "DSP_IMUX22_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_B8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT32->DSP_1_PCIN32": { + "src_wire": "DSP_0_PCOUT32", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN32", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN2_0->DSP_0_CEINMODE": { + "src_wire": "DSP_FAN2_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P22->DSP_LOGIC_OUTS_B20_0": { + "src_wire": "DSP_0_P22", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT45->DSP_PCOUT45": { + "src_wire": "DSP_1_PCOUT45", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT45", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P9->DSP_LOGIC_OUTS_B1_2": { + "src_wire": "DSP_1_P9", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P36->DSP_LOGIC_OUTS_B17_4": { + "src_wire": "DSP_0_P36", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT15->DSP_1_BCIN15": { + "src_wire": "DSP_0_BCOUT15", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX13_3->DSP_0_ALUMODE1": { + "src_wire": "DSP_IMUX13_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D10": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX18_4->DSP_0_C39": { + "src_wire": "DSP_IMUX18_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C39", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT8->DSP_1_PCIN8": { + "src_wire": "DSP_0_PCOUT8", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D20": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN3_4->DSP_1_D16": { + "src_wire": "DSP_FAN3_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_D16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX27_3->DSP_1_C13": { + "src_wire": "DSP_IMUX27_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D4": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P33->DSP_LOGIC_OUTS_B5_3": { + "src_wire": "DSP_1_P33", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT0->DSP_1_PCIN0": { + "src_wire": "DSP_0_PCOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P8->DSP_LOGIC_OUTS_B3_2": { + "src_wire": "DSP_1_P8", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX10_4->DSP_1_C39": { + "src_wire": "DSP_IMUX10_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C39", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT1->DSP_BCOUT1": { + "src_wire": "DSP_1_BCOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P0->DSP_LOGIC_OUTS_B21_0": { + "src_wire": "DSP_0_P0", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX36_3->DSP_1_OPMODE2": { + "src_wire": "DSP_IMUX36_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX19_1->DSP_0_A5": { + "src_wire": "DSP_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_INMODE3": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT14->DSP_ACOUT14": { + "src_wire": "DSP_1_ACOUT14", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX38_1->DSP_0_B4": { + "src_wire": "DSP_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P25->DSP_LOGIC_OUTS_B19_1": { + "src_wire": "DSP_0_P25", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX46_0->DSP_0_A22": { + "src_wire": "DSP_IMUX46_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D6": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P13->DSP_LOGIC_OUTS_B1_3": { + "src_wire": "DSP_1_P13", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX32_4->DSP_0_C37": { + "src_wire": "DSP_IMUX32_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C37", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX46_3->DSP_0_A14": { + "src_wire": "DSP_IMUX46_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_A14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D7": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT7->DSP_ACOUT7": { + "src_wire": "DSP_1_ACOUT7", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX14_0->DSP_1_B0": { + "src_wire": "DSP_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_B0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP4_2->DSP_1_INMODE0": { + "src_wire": "DSP_BYP4_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT20->DSP_1_PCIN20": { + "src_wire": "DSP_0_PCOUT20", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D14": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D23": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P43->DSP_LOGIC_OUTS_B14_0": { + "src_wire": "DSP_1_P43", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_CTRL0_1->DSP_0_RSTC": { + "src_wire": "DSP_CTRL0_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTC", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX47_4->DSP_0_A16": { + "src_wire": "DSP_IMUX47_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_A16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P15->DSP_LOGIC_OUTS_B4_3": { + "src_wire": "DSP_1_P15", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P24->DSP_LOGIC_OUTS_B17_1": { + "src_wire": "DSP_0_P24", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT36->DSP_1_PCIN36": { + "src_wire": "DSP_0_PCOUT36", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN36", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX5_4->DSP_1_A17": { + "src_wire": "DSP_IMUX5_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_A17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX19_2->DSP_0_A9": { + "src_wire": "DSP_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_A9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P28->DSP_LOGIC_OUTS_B17_2": { + "src_wire": "DSP_0_P28", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_INMODE2": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT17->DSP_PCOUT17": { + "src_wire": "DSP_1_PCOUT17", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX3_2->DSP_0_C9": { + "src_wire": "DSP_IMUX3_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT1->DSP_1_BCIN1": { + "src_wire": "DSP_0_BCOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT6->DSP_PCOUT6": { + "src_wire": "DSP_1_PCOUT6", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN4_0->DSP_1_D3": { + "src_wire": "DSP_FAN4_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_D3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_CEAD": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEAD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P21->DSP_LOGIC_OUTS_B5_0": { + "src_wire": "DSP_1_P21", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT5->DSP_1_BCIN5": { + "src_wire": "DSP_0_BCOUT5", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX45_1->DSP_1_A24": { + "src_wire": "DSP_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D20": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN0_4->DSP_1_ALUMODE2": { + "src_wire": "DSP_FAN0_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_INMODE4": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_CTRL1_0->DSP_0_RSTA": { + "src_wire": "DSP_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTA", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PATTERNBDETECT->DSP_LOGIC_OUTS_B15_2": { + "src_wire": "DSP_1_PATTERNBDETECT", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT8->DSP_ACOUT8": { + "src_wire": "DSP_1_ACOUT8", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D11": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D15": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P6->DSP_LOGIC_OUTS_B6_1": { + "src_wire": "DSP_1_P6", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D1": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT3->DSP_1_PCIN3": { + "src_wire": "DSP_0_PCOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX13_0->DSP_1_A2": { + "src_wire": "DSP_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX9_4->DSP_1_OPMODE5": { + "src_wire": "DSP_IMUX9_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P29->DSP_LOGIC_OUTS_B5_2": { + "src_wire": "DSP_1_P29", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT8->DSP_PCOUT8": { + "src_wire": "DSP_1_PCOUT8", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT32->DSP_PCOUT32": { + "src_wire": "DSP_1_PCOUT32", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT32", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX40_1->DSP_0_CEA1": { + "src_wire": "DSP_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEA1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT40->DSP_1_PCIN40": { + "src_wire": "DSP_0_PCOUT40", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN40", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX33_1->DSP_0_C7": { + "src_wire": "DSP_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX41_1->DSP_0_CEB1": { + "src_wire": "DSP_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEB1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT15->DSP_1_ACIN15": { + "src_wire": "DSP_0_ACOUT15", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX23_3->DSP_0_CARRYIN": { + "src_wire": "DSP_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT46->DSP_1_PCIN46": { + "src_wire": "DSP_0_PCOUT46", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN46", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D5": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT6->DSP_BCOUT6": { + "src_wire": "DSP_1_BCOUT6", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN0_2->DSP_1_D22": { + "src_wire": "DSP_FAN0_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_D22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP3_3->DSP_0_D14": { + "src_wire": "DSP_BYP3_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_D14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P3->DSP_LOGIC_OUTS_B4_0": { + "src_wire": "DSP_1_P3", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT42->DSP_PCOUT42": { + "src_wire": "DSP_1_PCOUT42", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT42", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX39_3->DSP_0_C12": { + "src_wire": "DSP_IMUX39_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN3_3->DSP_1_D12": { + "src_wire": "DSP_FAN3_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_D12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP6_3->DSP_0_INMODE0": { + "src_wire": "DSP_BYP6_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX39_2->DSP_0_C8": { + "src_wire": "DSP_IMUX39_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX22_4->DSP_1_RSTALUMODE": { + "src_wire": "DSP_IMUX22_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX17_3->DSP_1_CEA2": { + "src_wire": "DSP_IMUX17_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEA2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX23_2->DSP_0_A8": { + "src_wire": "DSP_IMUX23_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_A8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX18_0->DSP_0_C21": { + "src_wire": "DSP_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX4_4->DSP_1_A19": { + "src_wire": "DSP_IMUX4_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_A19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT41->DSP_PCOUT41": { + "src_wire": "DSP_1_PCOUT41", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT41", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D1": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT25->DSP_1_PCIN25": { + "src_wire": "DSP_0_PCOUT25", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT28->DSP_ACOUT28": { + "src_wire": "DSP_1_ACOUT28", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D15": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT13->DSP_ACOUT13": { + "src_wire": "DSP_1_ACOUT13", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D18": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP0_4->DSP_1_ALUMODE3": { + "src_wire": "DSP_BYP0_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX45_4->DSP_1_A16": { + "src_wire": "DSP_IMUX45_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_A16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP5_3->DSP_0_D13": { + "src_wire": "DSP_BYP5_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_D13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P38->DSP_LOGIC_OUTS_B2_4": { + "src_wire": "DSP_1_P38", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX25_2->DSP_1_C11": { + "src_wire": "DSP_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_CEALUMODE": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX20_3->DSP_0_C34": { + "src_wire": "DSP_IMUX20_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C34", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_INMODE3": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX28_2->DSP_1_C30": { + "src_wire": "DSP_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C30", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_CARRYCASCOUT->DSP_CARRYCASCOUT": { + "src_wire": "DSP_1_CARRYCASCOUT", + "is_pseudo": "0", + "dst_wire": "DSP_CARRYCASCOUT", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX46_2->DSP_1_C28": { + "src_wire": "DSP_IMUX46_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P29->DSP_LOGIC_OUTS_B19_2": { + "src_wire": "DSP_0_P29", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P38->DSP_LOGIC_OUTS_B20_4": { + "src_wire": "DSP_0_P38", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D17": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_CTRL1_2->DSP_1_RSTA": { + "src_wire": "DSP_CTRL1_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTA", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P36->DSP_LOGIC_OUTS_B7_4": { + "src_wire": "DSP_1_P36", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P12->DSP_LOGIC_OUTS_B3_3": { + "src_wire": "DSP_1_P12", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D11": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D23": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX18_3->DSP_0_C33": { + "src_wire": "DSP_IMUX18_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C33", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT4->DSP_ACOUT4": { + "src_wire": "DSP_1_ACOUT4", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_CARRYOUT2->DSP_LOGIC_OUTS_B13_1": { + "src_wire": "DSP_0_CARRYOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT3->DSP_BCOUT3": { + "src_wire": "DSP_1_BCOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN5_3->DSP_1_D14": { + "src_wire": "DSP_FAN5_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_D14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_MULTSIGNOUT->DSP_1_MULTSIGNIN": { + "src_wire": "DSP_0_MULTSIGNOUT", + "is_pseudo": "0", + "dst_wire": "DSP_1_MULTSIGNIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT38->DSP_1_PCIN38": { + "src_wire": "DSP_0_PCOUT38", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN38", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX0_2->DSP_0_CECARRYIN": { + "src_wire": "DSP_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_CECARRYIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT14->DSP_PCOUT14": { + "src_wire": "DSP_1_PCOUT14", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX24_0->DSP_1_C23": { + "src_wire": "DSP_IMUX24_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D4": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN6_3->DSP_1_D13": { + "src_wire": "DSP_FAN6_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_D13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX43_3->DSP_0_B12": { + "src_wire": "DSP_IMUX43_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_B12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P5->DSP_LOGIC_OUTS_B23_1": { + "src_wire": "DSP_0_P5", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT23->DSP_PCOUT23": { + "src_wire": "DSP_1_PCOUT23", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN5_0->DSP_1_D2": { + "src_wire": "DSP_FAN5_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_D2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT27->DSP_PCOUT27": { + "src_wire": "DSP_1_PCOUT27", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_CARRYINSEL2": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX9_1->DSP_1_A7": { + "src_wire": "DSP_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP5_1->DSP_0_D5": { + "src_wire": "DSP_BYP5_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P26->DSP_LOGIC_OUTS_B20_1": { + "src_wire": "DSP_0_P26", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP6_1->DSP_0_D21": { + "src_wire": "DSP_BYP6_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX39_1->DSP_0_C4": { + "src_wire": "DSP_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT4->DSP_1_ACIN4": { + "src_wire": "DSP_0_ACOUT4", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX37_1->DSP_0_C6": { + "src_wire": "DSP_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P2->DSP_LOGIC_OUTS_B16_0": { + "src_wire": "DSP_0_P2", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP0_0->DSP_0_ALUMODE3": { + "src_wire": "DSP_BYP0_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT19->DSP_PCOUT19": { + "src_wire": "DSP_1_PCOUT19", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX24_1->DSP_1_C27": { + "src_wire": "DSP_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT7->DSP_PCOUT7": { + "src_wire": "DSP_1_PCOUT7", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_INMODE1": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP0_3->DSP_1_CEAD": { + "src_wire": "DSP_BYP0_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEAD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX43_2->DSP_1_C9": { + "src_wire": "DSP_IMUX43_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX42_3->DSP_0_B14": { + "src_wire": "DSP_IMUX42_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_B14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P15->DSP_LOGIC_OUTS_B18_3": { + "src_wire": "DSP_0_P15", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX24_4->DSP_1_C37": { + "src_wire": "DSP_IMUX24_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C37", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX44_3->DSP_1_A14": { + "src_wire": "DSP_IMUX44_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_A14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN5_4->DSP_1_D18": { + "src_wire": "DSP_FAN5_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_D18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX1_0->DSP_0_C3": { + "src_wire": "DSP_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX41_0->DSP_1_C3": { + "src_wire": "DSP_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT30->DSP_1_PCIN30": { + "src_wire": "DSP_0_PCOUT30", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN30", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX32_0->DSP_0_C23": { + "src_wire": "DSP_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX2_4->DSP_1_B17": { + "src_wire": "DSP_IMUX2_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_B17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT12->DSP_ACOUT12": { + "src_wire": "DSP_1_ACOUT12", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX30_2->DSP_0_OPMODE1": { + "src_wire": "DSP_IMUX30_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX10_3->DSP_1_C33": { + "src_wire": "DSP_IMUX10_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C33", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_CARRYOUT1->DSP_LOGIC_OUTS_B11_3": { + "src_wire": "DSP_1_CARRYOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT18->DSP_1_PCIN18": { + "src_wire": "DSP_0_PCOUT18", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX12_2->DSP_0_OPMODE5": { + "src_wire": "DSP_IMUX12_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT46->DSP_PCOUT46": { + "src_wire": "DSP_1_PCOUT46", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT46", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX34_2->DSP_0_CEP": { + "src_wire": "DSP_IMUX34_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEP", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT39->DSP_PCOUT39": { + "src_wire": "DSP_1_PCOUT39", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT39", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX7_0->DSP_0_A21": { + "src_wire": "DSP_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX31_4->DSP_1_C16": { + "src_wire": "DSP_IMUX31_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX0_4->DSP_1_ALUMODE0": { + "src_wire": "DSP_IMUX0_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX29_3->DSP_1_C14": { + "src_wire": "DSP_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT31->DSP_1_PCIN31": { + "src_wire": "DSP_0_PCOUT31", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN31", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX36_1->DSP_0_B6": { + "src_wire": "DSP_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN3_1->DSP_1_D4": { + "src_wire": "DSP_FAN3_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX13_2->DSP_1_A10": { + "src_wire": "DSP_IMUX13_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_A10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT17->DSP_1_PCIN17": { + "src_wire": "DSP_0_PCOUT17", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D2": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT8->DSP_BCOUT8": { + "src_wire": "DSP_1_BCOUT8", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D18": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX24_3->DSP_1_C35": { + "src_wire": "DSP_IMUX24_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C35", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D8": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX44_0->DSP_1_A22": { + "src_wire": "DSP_IMUX44_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT28->DSP_1_PCIN28": { + "src_wire": "DSP_0_PCOUT28", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP2_1->DSP_1_INMODE1": { + "src_wire": "DSP_BYP2_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_INMODE3": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_ALUMODE3": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT5->DSP_BCOUT5": { + "src_wire": "DSP_1_BCOUT5", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D14": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D5": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX14_4->DSP_1_RSTCTRL": { + "src_wire": "DSP_IMUX14_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D12": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P27->DSP_LOGIC_OUTS_B0_1": { + "src_wire": "DSP_1_P27", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT2->DSP_1_PCIN2": { + "src_wire": "DSP_0_PCOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX22_3->DSP_1_C32": { + "src_wire": "DSP_IMUX22_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C32", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT2->DSP_BCOUT2": { + "src_wire": "DSP_1_BCOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX45_0->DSP_1_A20": { + "src_wire": "DSP_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P20->DSP_LOGIC_OUTS_B17_0": { + "src_wire": "DSP_0_P20", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D16": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P4->DSP_LOGIC_OUTS_B3_1": { + "src_wire": "DSP_1_P4", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP1_0->DSP_0_D3": { + "src_wire": "DSP_BYP1_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP3_0->DSP_0_D2": { + "src_wire": "DSP_BYP3_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D23": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX42_0->DSP_0_C42": { + "src_wire": "DSP_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C42", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX28_0->DSP_1_B2": { + "src_wire": "DSP_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_B2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX38_3->DSP_0_C32": { + "src_wire": "DSP_IMUX38_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C32", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP4_4->DSP_1_INMODE3": { + "src_wire": "DSP_BYP4_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP7_1->DSP_0_D4": { + "src_wire": "DSP_BYP7_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D15": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT3->DSP_1_ACIN3": { + "src_wire": "DSP_0_ACOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P12->DSP_LOGIC_OUTS_B21_3": { + "src_wire": "DSP_0_P12", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_CLK0_3->DSP_1_CLK": { + "src_wire": "DSP_CLK0_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D21": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D4": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D17": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP1_3->DSP_0_D15": { + "src_wire": "DSP_BYP1_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_D15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT15->DSP_1_PCIN15": { + "src_wire": "DSP_0_PCOUT15", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP6_2->DSP_0_INMODE3": { + "src_wire": "DSP_BYP6_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN0_0->DSP_0_ALUMODE2": { + "src_wire": "DSP_FAN0_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P28->DSP_LOGIC_OUTS_B7_2": { + "src_wire": "DSP_1_P28", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX21_2->DSP_0_A10": { + "src_wire": "DSP_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_A10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX34_3->DSP_1_CEC": { + "src_wire": "DSP_IMUX34_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEC", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT17->DSP_1_BCIN17": { + "src_wire": "DSP_0_BCOUT17", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P45->DSP_LOGIC_OUTS_B11_4": { + "src_wire": "DSP_1_P45", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP3_1->DSP_0_D6": { + "src_wire": "DSP_BYP3_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT7->DSP_BCOUT7": { + "src_wire": "DSP_1_BCOUT7", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX0_3->DSP_1_B15": { + "src_wire": "DSP_IMUX0_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_B15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P19->DSP_LOGIC_OUTS_B4_4": { + "src_wire": "DSP_1_P19", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT12->DSP_1_BCIN12": { + "src_wire": "DSP_0_BCOUT12", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D1": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P31->DSP_LOGIC_OUTS_B0_2": { + "src_wire": "DSP_1_P31", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P39->DSP_LOGIC_OUTS_B19_4": { + "src_wire": "DSP_0_P39", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX25_4->DSP_1_C47": { + "src_wire": "DSP_IMUX25_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C47", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX26_4->DSP_1_C44": { + "src_wire": "DSP_IMUX26_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C44", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT2->DSP_ACOUT2": { + "src_wire": "DSP_1_ACOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT23->DSP_1_ACIN23": { + "src_wire": "DSP_0_ACOUT23", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT36->DSP_PCOUT36": { + "src_wire": "DSP_1_PCOUT36", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT36", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_CTRL1_3->DSP_1_RSTM": { + "src_wire": "DSP_CTRL1_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTM", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX6_3->DSP_0_A15": { + "src_wire": "DSP_IMUX6_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_A15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT34->DSP_1_PCIN34": { + "src_wire": "DSP_0_PCOUT34", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN34", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX31_0->DSP_1_C0": { + "src_wire": "DSP_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P35->DSP_LOGIC_OUTS_B0_3": { + "src_wire": "DSP_1_P35", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_OVERFLOW->DSP_LOGIC_OUTS_B8_2": { + "src_wire": "DSP_1_OVERFLOW", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX2_3->DSP_0_B15": { + "src_wire": "DSP_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_B15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN7_1->DSP_0_INMODE1": { + "src_wire": "DSP_FAN7_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX13_4->DSP_1_C18": { + "src_wire": "DSP_IMUX13_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT35->DSP_1_PCIN35": { + "src_wire": "DSP_0_PCOUT35", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN35", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN1_3->DSP_0_INMODE4": { + "src_wire": "DSP_FAN1_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX35_4->DSP_0_C17": { + "src_wire": "DSP_IMUX35_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT40->DSP_PCOUT40": { + "src_wire": "DSP_1_PCOUT40", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT40", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX40_2->DSP_0_CEC": { + "src_wire": "DSP_IMUX40_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEC", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D3": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D12": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P20->DSP_LOGIC_OUTS_B7_0": { + "src_wire": "DSP_1_P20", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT25->DSP_PCOUT25": { + "src_wire": "DSP_1_PCOUT25", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_ALUMODE3": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX5_3->DSP_1_A13": { + "src_wire": "DSP_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_A13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT28->DSP_PCOUT28": { + "src_wire": "DSP_1_PCOUT28", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P2->DSP_LOGIC_OUTS_B6_0": { + "src_wire": "DSP_1_P2", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D10": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX17_4->DSP_1_OPMODE4": { + "src_wire": "DSP_IMUX17_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX6_0->DSP_0_A23": { + "src_wire": "DSP_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P37->DSP_LOGIC_OUTS_B0_4": { + "src_wire": "DSP_1_P37", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX35_1->DSP_0_C5": { + "src_wire": "DSP_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT14->DSP_1_PCIN14": { + "src_wire": "DSP_0_PCOUT14", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX19_3->DSP_1_CEM": { + "src_wire": "DSP_IMUX19_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEM", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX37_4->DSP_0_C45": { + "src_wire": "DSP_IMUX37_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C45", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT47->DSP_1_PCIN47": { + "src_wire": "DSP_0_PCOUT47", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN47", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D24": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P30->DSP_LOGIC_OUTS_B20_2": { + "src_wire": "DSP_0_P30", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX1_4->DSP_0_C19": { + "src_wire": "DSP_IMUX1_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_CED": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_CED", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX36_4->DSP_1_CARRYINSEL0": { + "src_wire": "DSP_IMUX36_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_INMODE4": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP1_1->DSP_0_D7": { + "src_wire": "DSP_BYP1_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D15": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX5_0->DSP_1_A21": { + "src_wire": "DSP_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX40_4->DSP_1_ALUMODE1": { + "src_wire": "DSP_IMUX40_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D0": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP0_1->DSP_0_CEAD": { + "src_wire": "DSP_BYP0_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEAD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT17->DSP_BCOUT17": { + "src_wire": "DSP_1_BCOUT17", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX10_2->DSP_1_C29": { + "src_wire": "DSP_IMUX10_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP4_0->DSP_0_CEALUMODE": { + "src_wire": "DSP_BYP4_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX36_0->DSP_0_B2": { + "src_wire": "DSP_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_B2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT29->DSP_1_ACIN29": { + "src_wire": "DSP_0_ACOUT29", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN1_1->DSP_1_D21": { + "src_wire": "DSP_FAN1_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX9_0->DSP_1_A3": { + "src_wire": "DSP_IMUX9_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX3_1->DSP_0_RSTALUMODE": { + "src_wire": "DSP_IMUX3_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP7_2->DSP_0_D8": { + "src_wire": "DSP_BYP7_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_ALUMODE3": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX9_3->DSP_1_CEA1": { + "src_wire": "DSP_IMUX9_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEA1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP5_0->DSP_0_D1": { + "src_wire": "DSP_BYP5_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX33_4->DSP_0_C47": { + "src_wire": "DSP_IMUX33_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C47", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT9->DSP_ACOUT9": { + "src_wire": "DSP_1_ACOUT9", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D19": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D7": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX15_2->DSP_1_A8": { + "src_wire": "DSP_IMUX15_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_A8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_BCOUT10->DSP_1_BCIN10": { + "src_wire": "DSP_0_BCOUT10", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT37->DSP_1_PCIN37": { + "src_wire": "DSP_0_PCOUT37", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN37", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX38_4->DSP_0_C36": { + "src_wire": "DSP_IMUX38_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C36", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT4->DSP_PCOUT4": { + "src_wire": "DSP_1_PCOUT4", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_CARRYINSEL2": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D24": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX21_0->DSP_0_A2": { + "src_wire": "DSP_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_BCOUT0->DSP_BCOUT0": { + "src_wire": "DSP_1_BCOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN7_0->DSP_1_D24": { + "src_wire": "DSP_FAN7_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_D24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX27_1->DSP_1_C5": { + "src_wire": "DSP_IMUX27_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D16": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP7_0->DSP_0_D0": { + "src_wire": "DSP_BYP7_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_D0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT30->DSP_PCOUT30": { + "src_wire": "DSP_1_PCOUT30", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT30", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT11->DSP_1_PCIN11": { + "src_wire": "DSP_0_PCOUT11", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP2_2->DSP_0_CARRYINSEL2": { + "src_wire": "DSP_BYP2_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D8": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX25_3->DSP_1_C15": { + "src_wire": "DSP_IMUX25_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D2": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX14_3->DSP_0_CARRYINSEL1": { + "src_wire": "DSP_IMUX14_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT22->DSP_PCOUT22": { + "src_wire": "DSP_1_PCOUT22", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX17_1->DSP_0_A7": { + "src_wire": "DSP_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX8_4->DSP_1_OPMODE1": { + "src_wire": "DSP_IMUX8_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX23_1->DSP_0_A4": { + "src_wire": "DSP_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX40_0->DSP_0_B3": { + "src_wire": "DSP_IMUX40_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_B3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P40->DSP_LOGIC_OUTS_B15_0": { + "src_wire": "DSP_1_P40", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D18": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT27->DSP_1_ACIN27": { + "src_wire": "DSP_0_ACOUT27", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_INMODE0": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT16->DSP_1_ACIN16": { + "src_wire": "DSP_0_ACOUT16", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX27_0->DSP_1_C40": { + "src_wire": "DSP_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C40", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P44->DSP_LOGIC_OUTS_B12_4": { + "src_wire": "DSP_1_P44", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B12_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_INMODE0": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P1->DSP_LOGIC_OUTS_B1_0": { + "src_wire": "DSP_1_P1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P9->DSP_LOGIC_OUTS_B23_2": { + "src_wire": "DSP_0_P9", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_CARRYCASCOUT->DSP_1_CARRYCASCIN": { + "src_wire": "DSP_0_CARRYCASCOUT", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYCASCIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT20->DSP_PCOUT20": { + "src_wire": "DSP_1_PCOUT20", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_CEINMODE": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP2_0->DSP_0_D24": { + "src_wire": "DSP_BYP2_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_D24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D22": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P8->DSP_LOGIC_OUTS_B21_2": { + "src_wire": "DSP_0_P8", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN4_1->DSP_1_D7": { + "src_wire": "DSP_FAN4_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT35->DSP_PCOUT35": { + "src_wire": "DSP_1_PCOUT35", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT35", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_FAN3_2->DSP_1_D8": { + "src_wire": "DSP_FAN3_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_D8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT21->DSP_1_PCIN21": { + "src_wire": "DSP_0_PCOUT21", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_D6": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX12_3->DSP_1_C34": { + "src_wire": "DSP_IMUX12_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C34", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX31_1->DSP_1_C4": { + "src_wire": "DSP_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT1->DSP_PCOUT1": { + "src_wire": "DSP_1_PCOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX43_0->DSP_1_C1": { + "src_wire": "DSP_IMUX43_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D20": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D9": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX15_3->DSP_1_CARRYIN": { + "src_wire": "DSP_IMUX15_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_OVERFLOW->DSP_LOGIC_OUTS_B10_2": { + "src_wire": "DSP_0_OVERFLOW", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_ACOUT6->DSP_ACOUT6": { + "src_wire": "DSP_1_ACOUT6", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P27->DSP_LOGIC_OUTS_B22_1": { + "src_wire": "DSP_0_P27", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_PCOUT16->DSP_PCOUT16": { + "src_wire": "DSP_1_PCOUT16", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_P13->DSP_LOGIC_OUTS_B23_3": { + "src_wire": "DSP_0_P13", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D1": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_IMUX33_2->DSP_0_C11": { + "src_wire": "DSP_IMUX33_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP3_2->DSP_0_D10": { + "src_wire": "DSP_BYP3_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_D10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_0_D2": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_GND_L->DSP_1_INMODE0": { + "src_wire": "DSP_GND_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D19": { + "src_wire": "DSP_VCC_L", + "is_pseudo": "0", + "dst_wire": "DSP_1_D19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_BYP4_3->DSP_1_CEALUMODE": { + "src_wire": "DSP_BYP4_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_1_P11->DSP_LOGIC_OUTS_B4_2": { + "src_wire": "DSP_1_P11", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_ACOUT7->DSP_1_ACIN7": { + "src_wire": "DSP_0_ACOUT7", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_L.DSP_0_PCOUT16->DSP_1_PCIN16": { + "src_wire": "DSP_0_PCOUT16", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN16", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_DSP_R.json b/kintex7/tile_type_DSP_R.json new file mode 100644 index 0000000..586ac9e --- /dev/null +++ b/kintex7/tile_type_DSP_R.json @@ -0,0 +1,8474 @@ +{ + "tile_type": "DSP_R", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "DSP48", + "type": "DSP48E1", + "site_pins": { + "A17": "DSP_0_A17", + "ACIN11": "DSP_0_ACIN11", + "A22": "DSP_0_A22", + "PCIN31": "DSP_0_PCIN31", + "ACIN19": "DSP_0_ACIN19", + "INMODE0": "DSP_0_INMODE0", + "D15": "DSP_0_D15", + "P24": "DSP_0_P24", + "C38": "DSP_0_C38", + "D11": "DSP_0_D11", + "CARRYINSEL2": "DSP_0_CARRYINSEL2", + "BCIN17": "DSP_0_BCIN17", + "BCOUT2": "DSP_0_BCOUT2", + "PCOUT12": "DSP_0_PCOUT12", + "BCIN1": "DSP_0_BCIN1", + "PCIN41": "DSP_0_PCIN41", + "ACOUT29": "DSP_0_ACOUT29", + "ACIN25": "DSP_0_ACIN25", + "PCOUT6": "DSP_0_PCOUT6", + "PCIN1": "DSP_0_PCIN1", + "RSTCTRL": "DSP_0_RSTCTRL", + "C36": "DSP_0_C36", + "ACIN0": "DSP_0_ACIN0", + "PCIN26": "DSP_0_PCIN26", + "D0": "DSP_0_D0", + "PCOUT31": "DSP_0_PCOUT31", + "ACOUT3": "DSP_0_ACOUT3", + "B1": "DSP_0_B1", + "PCIN35": "DSP_0_PCIN35", + "PCOUT47": "DSP_0_PCOUT47", + "P23": "DSP_0_P23", + "ACIN21": "DSP_0_ACIN21", + "ACIN29": "DSP_0_ACIN29", + "PCOUT19": "DSP_0_PCOUT19", + "P31": "DSP_0_P31", + "P17": "DSP_0_P17", + "PCIN22": "DSP_0_PCIN22", + "PCOUT4": "DSP_0_PCOUT4", + "ACIN26": "DSP_0_ACIN26", + "C27": "DSP_0_C27", + "PCIN40": "DSP_0_PCIN40", + "C16": "DSP_0_C16", + "BCIN8": "DSP_0_BCIN8", + "PCIN27": "DSP_0_PCIN27", + "PCOUT42": "DSP_0_PCOUT42", + "C21": "DSP_0_C21", + "ACOUT28": "DSP_0_ACOUT28", + "INMODE4": "DSP_0_INMODE4", + "C24": "DSP_0_C24", + "C31": "DSP_0_C31", + "BCIN14": "DSP_0_BCIN14", + "ACIN15": "DSP_0_ACIN15", + "C35": "DSP_0_C35", + "PCOUT38": "DSP_0_PCOUT38", + "C29": "DSP_0_C29", + "P9": "DSP_0_P9", + "PCOUT37": "DSP_0_PCOUT37", + "CEB1": "DSP_0_CEB1", + "BCIN2": "DSP_0_BCIN2", + "D23": "DSP_0_D23", + "C13": "DSP_0_C13", + "P39": "DSP_0_P39", + "D19": "DSP_0_D19", + "P10": "DSP_0_P10", + "C17": "DSP_0_C17", + "C15": "DSP_0_C15", + "MULTSIGNIN": "DSP_0_MULTSIGNIN", + "P19": "DSP_0_P19", + "ACOUT22": "DSP_0_ACOUT22", + "ACIN5": "DSP_0_ACIN5", + "PCOUT3": "DSP_0_PCOUT3", + "B16": "DSP_0_B16", + "ALUMODE3": "DSP_0_ALUMODE3", + "ACIN6": "DSP_0_ACIN6", + "CEP": "DSP_0_CEP", + "ACOUT21": "DSP_0_ACOUT21", + "PCIN39": "DSP_0_PCIN39", + "BCOUT0": "DSP_0_BCOUT0", + "PCIN16": "DSP_0_PCIN16", + "PCIN46": "DSP_0_PCIN46", + "BCOUT4": "DSP_0_BCOUT4", + "C14": "DSP_0_C14", + "ACOUT15": "DSP_0_ACOUT15", + "BCOUT9": "DSP_0_BCOUT9", + "ACOUT16": "DSP_0_ACOUT16", + "PCOUT23": "DSP_0_PCOUT23", + "PCIN15": "DSP_0_PCIN15", + "PCOUT14": "DSP_0_PCOUT14", + "OPMODE0": "DSP_0_OPMODE0", + "UNDERFLOW": "DSP_0_UNDERFLOW", + "D2": "DSP_0_D2", + "ACOUT10": "DSP_0_ACOUT10", + "ACIN27": "DSP_0_ACIN27", + "PCOUT28": "DSP_0_PCOUT28", + "A21": "DSP_0_A21", + "B10": "DSP_0_B10", + "C28": "DSP_0_C28", + "PCOUT46": "DSP_0_PCOUT46", + "D1": "DSP_0_D1", + "D5": "DSP_0_D5", + "ACOUT26": "DSP_0_ACOUT26", + "P43": "DSP_0_P43", + "RSTD": "DSP_0_RSTD", + "C45": "DSP_0_C45", + "CEINMODE": "DSP_0_CEINMODE", + "RSTM": "DSP_0_RSTM", + "P26": "DSP_0_P26", + "PCIN20": "DSP_0_PCIN20", + "ACIN3": "DSP_0_ACIN3", + "PCOUT32": "DSP_0_PCOUT32", + "P1": "DSP_0_P1", + "P15": "DSP_0_P15", + "CARRYCASCOUT": "DSP_0_CARRYCASCOUT", + "B2": "DSP_0_B2", + "BCOUT12": "DSP_0_BCOUT12", + "P6": "DSP_0_P6", + "PCOUT11": "DSP_0_PCOUT11", + "PCIN7": "DSP_0_PCIN7", + "CARRYOUT3": "DSP_0_CARRYOUT3", + "PCOUT26": "DSP_0_PCOUT26", + "D6": "DSP_0_D6", + "D12": "DSP_0_D12", + "BCOUT5": "DSP_0_BCOUT5", + "RSTB": "DSP_0_RSTB", + "ALUMODE0": "DSP_0_ALUMODE0", + "PCIN30": "DSP_0_PCIN30", + "A28": "DSP_0_A28", + "P8": "DSP_0_P8", + "CEA1": "DSP_0_CEA1", + "C0": "DSP_0_C0", + "P40": "DSP_0_P40", + "CEM": "DSP_0_CEM", + "PCIN18": "DSP_0_PCIN18", + "PCOUT43": "DSP_0_PCOUT43", + "PCOUT33": "DSP_0_PCOUT33", + "A1": "DSP_0_A1", + "RSTC": "DSP_0_RSTC", + "PCIN3": "DSP_0_PCIN3", + "PCOUT25": "DSP_0_PCOUT25", + "D9": "DSP_0_D9", + "PCIN14": "DSP_0_PCIN14", + "CED": "DSP_0_CED", + "C8": "DSP_0_C8", + "RSTALLCARRYIN": "DSP_0_RSTALLCARRYIN", + "C3": "DSP_0_C3", + "ACOUT13": "DSP_0_ACOUT13", + "CEAD": "DSP_0_CEAD", + "A16": "DSP_0_A16", + "C10": "DSP_0_C10", + "ACIN10": "DSP_0_ACIN10", + "PCOUT20": "DSP_0_PCOUT20", + "PCIN34": "DSP_0_PCIN34", + "C32": "DSP_0_C32", + "D16": "DSP_0_D16", + "OVERFLOW": "DSP_0_OVERFLOW", + "ACIN18": "DSP_0_ACIN18", + "ACIN8": "DSP_0_ACIN8", + "D18": "DSP_0_D18", + "PCIN25": "DSP_0_PCIN25", + "P42": "DSP_0_P42", + "CARRYINSEL0": "DSP_0_CARRYINSEL0", + "ACIN20": "DSP_0_ACIN20", + "A3": "DSP_0_A3", + "BCIN0": "DSP_0_BCIN0", + "CARRYINSEL1": "DSP_0_CARRYINSEL1", + "PCIN8": "DSP_0_PCIN8", + "BCIN9": "DSP_0_BCIN9", + "P16": "DSP_0_P16", + "ACOUT18": "DSP_0_ACOUT18", + "PCIN38": "DSP_0_PCIN38", + "CARRYOUT0": "DSP_0_CARRYOUT0", + "PCOUT17": "DSP_0_PCOUT17", + "B17": "DSP_0_B17", + "PCIN42": "DSP_0_PCIN42", + "PCIN5": "DSP_0_PCIN5", + "D24": "DSP_0_D24", + "P36": "DSP_0_P36", + "C9": "DSP_0_C9", + "ACOUT1": "DSP_0_ACOUT1", + "B7": "DSP_0_B7", + "MULTSIGNOUT": "DSP_0_MULTSIGNOUT", + "PCOUT0": "DSP_0_PCOUT0", + "C41": "DSP_0_C41", + "A25": "DSP_0_A25", + "PCIN24": "DSP_0_PCIN24", + "C37": "DSP_0_C37", + "C39": "DSP_0_C39", + "ACIN16": "DSP_0_ACIN16", + "P3": "DSP_0_P3", + "B0": "DSP_0_B0", + "PCOUT2": "DSP_0_PCOUT2", + "C33": "DSP_0_C33", + "OPMODE4": "DSP_0_OPMODE4", + "PCIN37": "DSP_0_PCIN37", + "CEALUMODE": "DSP_0_CEALUMODE", + "C20": "DSP_0_C20", + "ACOUT11": "DSP_0_ACOUT11", + "B12": "DSP_0_B12", + "PCIN11": "DSP_0_PCIN11", + "ACOUT14": "DSP_0_ACOUT14", + "ACOUT23": "DSP_0_ACOUT23", + "PCOUT1": "DSP_0_PCOUT1", + "P47": "DSP_0_P47", + "P30": "DSP_0_P30", + "PCIN29": "DSP_0_PCIN29", + "ACOUT25": "DSP_0_ACOUT25", + "PCOUT39": "DSP_0_PCOUT39", + "B5": "DSP_0_B5", + "A27": "DSP_0_A27", + "CEB2": "DSP_0_CEB2", + "PCIN45": "DSP_0_PCIN45", + "P25": "DSP_0_P25", + "RSTALUMODE": "DSP_0_RSTALUMODE", + "PCIN36": "DSP_0_PCIN36", + "OPMODE2": "DSP_0_OPMODE2", + "BCOUT1": "DSP_0_BCOUT1", + "D22": "DSP_0_D22", + "PCOUT8": "DSP_0_PCOUT8", + "ACIN1": "DSP_0_ACIN1", + "C43": "DSP_0_C43", + "INMODE2": "DSP_0_INMODE2", + "A2": "DSP_0_A2", + "PCOUT45": "DSP_0_PCOUT45", + "PATTERNDETECT": "DSP_0_PATTERNDETECT", + "A29": "DSP_0_A29", + "RSTA": "DSP_0_RSTA", + "ACOUT17": "DSP_0_ACOUT17", + "A14": "DSP_0_A14", + "CARRYOUT2": "DSP_0_CARRYOUT2", + "A12": "DSP_0_A12", + "BCIN4": "DSP_0_BCIN4", + "PCOUT40": "DSP_0_PCOUT40", + "CEA2": "DSP_0_CEA2", + "C30": "DSP_0_C30", + "P2": "DSP_0_P2", + "B14": "DSP_0_B14", + "P5": "DSP_0_P5", + "P18": "DSP_0_P18", + "ACOUT4": "DSP_0_ACOUT4", + "A0": "DSP_0_A0", + "ACOUT0": "DSP_0_ACOUT0", + "BCIN6": "DSP_0_BCIN6", + "BCIN13": "DSP_0_BCIN13", + "C40": "DSP_0_C40", + "P29": "DSP_0_P29", + "A4": "DSP_0_A4", + "PCOUT21": "DSP_0_PCOUT21", + "ALUMODE1": "DSP_0_ALUMODE1", + "C22": "DSP_0_C22", + "BCOUT8": "DSP_0_BCOUT8", + "P14": "DSP_0_P14", + "OPMODE6": "DSP_0_OPMODE6", + "PCOUT22": "DSP_0_PCOUT22", + "BCIN16": "DSP_0_BCIN16", + "ACOUT5": "DSP_0_ACOUT5", + "ACIN14": "DSP_0_ACIN14", + "D8": "DSP_0_D8", + "RSTINMODE": "DSP_0_RSTINMODE", + "PCOUT13": "DSP_0_PCOUT13", + "ALUMODE2": "DSP_0_ALUMODE2", + "P45": "DSP_0_P45", + "BCIN7": "DSP_0_BCIN7", + "ACOUT9": "DSP_0_ACOUT9", + "P38": "DSP_0_P38", + "PCIN28": "DSP_0_PCIN28", + "C26": "DSP_0_C26", + "P21": "DSP_0_P21", + "ACIN12": "DSP_0_ACIN12", + "ACOUT20": "DSP_0_ACOUT20", + "BCOUT16": "DSP_0_BCOUT16", + "A8": "DSP_0_A8", + "C47": "DSP_0_C47", + "PCIN44": "DSP_0_PCIN44", + "A23": "DSP_0_A23", + "C34": "DSP_0_C34", + "C12": "DSP_0_C12", + "P4": "DSP_0_P4", + "OPMODE1": "DSP_0_OPMODE1", + "B13": "DSP_0_B13", + "CEC": "DSP_0_CEC", + "A26": "DSP_0_A26", + "PCIN9": "DSP_0_PCIN9", + "PCIN32": "DSP_0_PCIN32", + "D7": "DSP_0_D7", + "PCOUT27": "DSP_0_PCOUT27", + "P34": "DSP_0_P34", + "BCOUT6": "DSP_0_BCOUT6", + "BCIN15": "DSP_0_BCIN15", + "PCIN10": "DSP_0_PCIN10", + "PCIN0": "DSP_0_PCIN0", + "BCOUT14": "DSP_0_BCOUT14", + "CARRYIN": "DSP_0_CARRYIN", + "PCIN43": "DSP_0_PCIN43", + "D21": "DSP_0_D21", + "BCOUT17": "DSP_0_BCOUT17", + "PCIN13": "DSP_0_PCIN13", + "A9": "DSP_0_A9", + "PCIN6": "DSP_0_PCIN6", + "CLK": "DSP_0_CLK", + "PCIN4": "DSP_0_PCIN4", + "C25": "DSP_0_C25", + "CECARRYIN": "DSP_0_CECARRYIN", + "BCIN5": "DSP_0_BCIN5", + "C19": "DSP_0_C19", + "P13": "DSP_0_P13", + "INMODE1": "DSP_0_INMODE1", + "PCIN23": "DSP_0_PCIN23", + "P44": "DSP_0_P44", + "B15": "DSP_0_B15", + "A15": "DSP_0_A15", + "BCOUT11": "DSP_0_BCOUT11", + "A18": "DSP_0_A18", + "P0": "DSP_0_P0", + "C7": "DSP_0_C7", + "ACOUT2": "DSP_0_ACOUT2", + "ACIN7": "DSP_0_ACIN7", + "D20": "DSP_0_D20", + "D13": "DSP_0_D13", + "A19": "DSP_0_A19", + "PCOUT44": "DSP_0_PCOUT44", + "BCOUT10": "DSP_0_BCOUT10", + "CECTRL": "DSP_0_CECTRL", + "PCIN33": "DSP_0_PCIN33", + "D10": "DSP_0_D10", + "BCOUT13": "DSP_0_BCOUT13", + "B11": "DSP_0_B11", + "ACOUT8": "DSP_0_ACOUT8", + "INMODE3": "DSP_0_INMODE3", + "B6": "DSP_0_B6", + "OPMODE3": "DSP_0_OPMODE3", + "ACIN17": "DSP_0_ACIN17", + "P28": "DSP_0_P28", + "P20": "DSP_0_P20", + "C4": "DSP_0_C4", + "B8": "DSP_0_B8", + "B4": "DSP_0_B4", + "A6": "DSP_0_A6", + "P41": "DSP_0_P41", + "ACIN4": "DSP_0_ACIN4", + "PCOUT41": "DSP_0_PCOUT41", + "D4": "DSP_0_D4", + "D14": "DSP_0_D14", + "ACOUT27": "DSP_0_ACOUT27", + "PCOUT5": "DSP_0_PCOUT5", + "ACOUT24": "DSP_0_ACOUT24", + "C11": "DSP_0_C11", + "PCOUT34": "DSP_0_PCOUT34", + "C5": "DSP_0_C5", + "A7": "DSP_0_A7", + "ACIN13": "DSP_0_ACIN13", + "ACIN28": "DSP_0_ACIN28", + "P11": "DSP_0_P11", + "A11": "DSP_0_A11", + "PCOUT30": "DSP_0_PCOUT30", + "C23": "DSP_0_C23", + "P32": "DSP_0_P32", + "D3": "DSP_0_D3", + "ACOUT6": "DSP_0_ACOUT6", + "P22": "DSP_0_P22", + "C46": "DSP_0_C46", + "CARRYCASCIN": "DSP_0_CARRYCASCIN", + "P35": "DSP_0_P35", + "PCIN17": "DSP_0_PCIN17", + "PCIN21": "DSP_0_PCIN21", + "BCOUT7": "DSP_0_BCOUT7", + "PCOUT15": "DSP_0_PCOUT15", + "A20": "DSP_0_A20", + "C42": "DSP_0_C42", + "PCOUT18": "DSP_0_PCOUT18", + "PCOUT10": "DSP_0_PCOUT10", + "BCIN10": "DSP_0_BCIN10", + "ACIN22": "DSP_0_ACIN22", + "B9": "DSP_0_B9", + "A10": "DSP_0_A10", + "D17": "DSP_0_D17", + "ACIN2": "DSP_0_ACIN2", + "A13": "DSP_0_A13", + "PCOUT29": "DSP_0_PCOUT29", + "C6": "DSP_0_C6", + "PCIN2": "DSP_0_PCIN2", + "PCOUT35": "DSP_0_PCOUT35", + "ACOUT19": "DSP_0_ACOUT19", + "PCOUT7": "DSP_0_PCOUT7", + "C18": "DSP_0_C18", + "P7": "DSP_0_P7", + "BCIN3": "DSP_0_BCIN3", + "PCOUT16": "DSP_0_PCOUT16", + "C2": "DSP_0_C2", + "P46": "DSP_0_P46", + "ACOUT7": "DSP_0_ACOUT7", + "PCOUT36": "DSP_0_PCOUT36", + "A5": "DSP_0_A5", + "ACIN9": "DSP_0_ACIN9", + "A24": "DSP_0_A24", + "P27": "DSP_0_P27", + "ACIN24": "DSP_0_ACIN24", + "CARRYOUT1": "DSP_0_CARRYOUT1", + "ACOUT12": "DSP_0_ACOUT12", + "BCOUT15": "DSP_0_BCOUT15", + "B3": "DSP_0_B3", + "P33": "DSP_0_P33", + "PCIN47": "DSP_0_PCIN47", + "PATTERNBDETECT": "DSP_0_PATTERNBDETECT", + "P37": "DSP_0_P37", + "P12": "DSP_0_P12", + "BCIN12": "DSP_0_BCIN12", + "RSTP": "DSP_0_RSTP", + "BCOUT3": "DSP_0_BCOUT3", + "OPMODE5": "DSP_0_OPMODE5", + "C44": "DSP_0_C44", + "BCIN11": "DSP_0_BCIN11", + "PCIN12": "DSP_0_PCIN12", + "C1": "DSP_0_C1", + "PCOUT24": "DSP_0_PCOUT24", + "PCIN19": "DSP_0_PCIN19", + "PCOUT9": "DSP_0_PCOUT9", + "ACIN23": "DSP_0_ACIN23" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "DSP48", + "type": "DSP48E1", + "site_pins": { + "A17": "DSP_1_A17", + "ACIN11": "DSP_1_ACIN11", + "A22": "DSP_1_A22", + "PCIN31": "DSP_1_PCIN31", + "ACIN19": "DSP_1_ACIN19", + "INMODE0": "DSP_1_INMODE0", + "D15": "DSP_1_D15", + "P24": "DSP_1_P24", + "C38": "DSP_1_C38", + "D11": "DSP_1_D11", + "CARRYINSEL2": "DSP_1_CARRYINSEL2", + "BCIN17": "DSP_1_BCIN17", + "BCOUT2": "DSP_1_BCOUT2", + "PCOUT12": "DSP_1_PCOUT12", + "BCIN1": "DSP_1_BCIN1", + "PCIN41": "DSP_1_PCIN41", + "ACOUT29": "DSP_1_ACOUT29", + "ACIN25": "DSP_1_ACIN25", + "PCOUT6": "DSP_1_PCOUT6", + "PCIN1": "DSP_1_PCIN1", + "RSTCTRL": "DSP_1_RSTCTRL", + "C36": "DSP_1_C36", + "ACIN0": "DSP_1_ACIN0", + "PCIN26": "DSP_1_PCIN26", + "D0": "DSP_1_D0", + "PCOUT31": "DSP_1_PCOUT31", + "ACOUT3": "DSP_1_ACOUT3", + "B1": "DSP_1_B1", + "PCIN35": "DSP_1_PCIN35", + "PCOUT47": "DSP_1_PCOUT47", + "P23": "DSP_1_P23", + "ACIN21": "DSP_1_ACIN21", + "ACIN29": "DSP_1_ACIN29", + "PCOUT19": "DSP_1_PCOUT19", + "P31": "DSP_1_P31", + "P17": "DSP_1_P17", + "PCIN22": "DSP_1_PCIN22", + "PCOUT4": "DSP_1_PCOUT4", + "ACIN26": "DSP_1_ACIN26", + "C27": "DSP_1_C27", + "PCIN40": "DSP_1_PCIN40", + "C16": "DSP_1_C16", + "BCIN8": "DSP_1_BCIN8", + "PCIN27": "DSP_1_PCIN27", + "PCOUT42": "DSP_1_PCOUT42", + "C21": "DSP_1_C21", + "ACOUT28": "DSP_1_ACOUT28", + "INMODE4": "DSP_1_INMODE4", + "C24": "DSP_1_C24", + "C31": "DSP_1_C31", + "BCIN14": "DSP_1_BCIN14", + "ACIN15": "DSP_1_ACIN15", + "C35": "DSP_1_C35", + "PCOUT38": "DSP_1_PCOUT38", + "C29": "DSP_1_C29", + "P9": "DSP_1_P9", + "PCOUT37": "DSP_1_PCOUT37", + "CEB1": "DSP_1_CEB1", + "BCIN2": "DSP_1_BCIN2", + "D23": "DSP_1_D23", + "C13": "DSP_1_C13", + "P39": "DSP_1_P39", + "D19": "DSP_1_D19", + "P10": "DSP_1_P10", + "C17": "DSP_1_C17", + "C15": "DSP_1_C15", + "MULTSIGNIN": "DSP_1_MULTSIGNIN", + "P19": "DSP_1_P19", + "ACOUT22": "DSP_1_ACOUT22", + "ACIN5": "DSP_1_ACIN5", + "PCOUT3": "DSP_1_PCOUT3", + "B16": "DSP_1_B16", + "ALUMODE3": "DSP_1_ALUMODE3", + "ACIN6": "DSP_1_ACIN6", + "CEP": "DSP_1_CEP", + "ACOUT21": "DSP_1_ACOUT21", + "PCIN39": "DSP_1_PCIN39", + "BCOUT0": "DSP_1_BCOUT0", + "PCIN16": "DSP_1_PCIN16", + "PCIN46": "DSP_1_PCIN46", + "BCOUT4": "DSP_1_BCOUT4", + "C14": "DSP_1_C14", + "ACOUT15": "DSP_1_ACOUT15", + "BCOUT9": "DSP_1_BCOUT9", + "ACOUT16": "DSP_1_ACOUT16", + "PCOUT23": "DSP_1_PCOUT23", + "PCIN15": "DSP_1_PCIN15", + "PCOUT14": "DSP_1_PCOUT14", + "OPMODE0": "DSP_1_OPMODE0", + "UNDERFLOW": "DSP_1_UNDERFLOW", + "D2": "DSP_1_D2", + "ACOUT10": "DSP_1_ACOUT10", + "ACIN27": "DSP_1_ACIN27", + "PCOUT28": "DSP_1_PCOUT28", + "A21": "DSP_1_A21", + "B10": "DSP_1_B10", + "C28": "DSP_1_C28", + "PCOUT46": "DSP_1_PCOUT46", + "D1": "DSP_1_D1", + "D5": "DSP_1_D5", + "ACOUT26": "DSP_1_ACOUT26", + "P43": "DSP_1_P43", + "RSTD": "DSP_1_RSTD", + "C45": "DSP_1_C45", + "CEINMODE": "DSP_1_CEINMODE", + "RSTM": "DSP_1_RSTM", + "P26": "DSP_1_P26", + "PCIN20": "DSP_1_PCIN20", + "ACIN3": "DSP_1_ACIN3", + "PCOUT32": "DSP_1_PCOUT32", + "P1": "DSP_1_P1", + "P15": "DSP_1_P15", + "CARRYCASCOUT": "DSP_1_CARRYCASCOUT", + "B2": "DSP_1_B2", + "BCOUT12": "DSP_1_BCOUT12", + "P6": "DSP_1_P6", + "PCOUT11": "DSP_1_PCOUT11", + "PCIN7": "DSP_1_PCIN7", + "CARRYOUT3": "DSP_1_CARRYOUT3", + "PCOUT26": "DSP_1_PCOUT26", + "D6": "DSP_1_D6", + "D12": "DSP_1_D12", + "BCOUT5": "DSP_1_BCOUT5", + "RSTB": "DSP_1_RSTB", + "ALUMODE0": "DSP_1_ALUMODE0", + "PCIN30": "DSP_1_PCIN30", + "A28": "DSP_1_A28", + "P8": "DSP_1_P8", + "CEA1": "DSP_1_CEA1", + "C0": "DSP_1_C0", + "P40": "DSP_1_P40", + "CEM": "DSP_1_CEM", + "PCIN18": "DSP_1_PCIN18", + "PCOUT43": "DSP_1_PCOUT43", + "PCOUT33": "DSP_1_PCOUT33", + "A1": "DSP_1_A1", + "RSTC": "DSP_1_RSTC", + "PCIN3": "DSP_1_PCIN3", + "PCOUT25": "DSP_1_PCOUT25", + "D9": "DSP_1_D9", + "PCIN14": "DSP_1_PCIN14", + "CED": "DSP_1_CED", + "C8": "DSP_1_C8", + "RSTALLCARRYIN": "DSP_1_RSTALLCARRYIN", + "C3": "DSP_1_C3", + "ACOUT13": "DSP_1_ACOUT13", + "CEAD": "DSP_1_CEAD", + "A16": "DSP_1_A16", + "C10": "DSP_1_C10", + "ACIN10": "DSP_1_ACIN10", + "PCOUT20": "DSP_1_PCOUT20", + "PCIN34": "DSP_1_PCIN34", + "C32": "DSP_1_C32", + "D16": "DSP_1_D16", + "OVERFLOW": "DSP_1_OVERFLOW", + "ACIN18": "DSP_1_ACIN18", + "ACIN8": "DSP_1_ACIN8", + "D18": "DSP_1_D18", + "PCIN25": "DSP_1_PCIN25", + "P42": "DSP_1_P42", + "CARRYINSEL0": "DSP_1_CARRYINSEL0", + "ACIN20": "DSP_1_ACIN20", + "A3": "DSP_1_A3", + "BCIN0": "DSP_1_BCIN0", + "CARRYINSEL1": "DSP_1_CARRYINSEL1", + "PCIN8": "DSP_1_PCIN8", + "BCIN9": "DSP_1_BCIN9", + "P16": "DSP_1_P16", + "ACOUT18": "DSP_1_ACOUT18", + "PCIN38": "DSP_1_PCIN38", + "CARRYOUT0": "DSP_1_CARRYOUT0", + "PCOUT17": "DSP_1_PCOUT17", + "B17": "DSP_1_B17", + "PCIN42": "DSP_1_PCIN42", + "PCIN5": "DSP_1_PCIN5", + "D24": "DSP_1_D24", + "P36": "DSP_1_P36", + "C9": "DSP_1_C9", + "ACOUT1": "DSP_1_ACOUT1", + "B7": "DSP_1_B7", + "MULTSIGNOUT": "DSP_1_MULTSIGNOUT", + "PCOUT0": "DSP_1_PCOUT0", + "C41": "DSP_1_C41", + "A25": "DSP_1_A25", + "PCIN24": "DSP_1_PCIN24", + "C37": "DSP_1_C37", + "C39": "DSP_1_C39", + "ACIN16": "DSP_1_ACIN16", + "P3": "DSP_1_P3", + "B0": "DSP_1_B0", + "PCOUT2": "DSP_1_PCOUT2", + "C33": "DSP_1_C33", + "OPMODE4": "DSP_1_OPMODE4", + "PCIN37": "DSP_1_PCIN37", + "CEALUMODE": "DSP_1_CEALUMODE", + "C20": "DSP_1_C20", + "ACOUT11": "DSP_1_ACOUT11", + "B12": "DSP_1_B12", + "PCIN11": "DSP_1_PCIN11", + "ACOUT14": "DSP_1_ACOUT14", + "ACOUT23": "DSP_1_ACOUT23", + "PCOUT1": "DSP_1_PCOUT1", + "P47": "DSP_1_P47", + "P30": "DSP_1_P30", + "PCIN29": "DSP_1_PCIN29", + "ACOUT25": "DSP_1_ACOUT25", + "PCOUT39": "DSP_1_PCOUT39", + "B5": "DSP_1_B5", + "A27": "DSP_1_A27", + "CEB2": "DSP_1_CEB2", + "PCIN45": "DSP_1_PCIN45", + "P25": "DSP_1_P25", + "RSTALUMODE": "DSP_1_RSTALUMODE", + "PCIN36": "DSP_1_PCIN36", + "OPMODE2": "DSP_1_OPMODE2", + "BCOUT1": "DSP_1_BCOUT1", + "D22": "DSP_1_D22", + "PCOUT8": "DSP_1_PCOUT8", + "ACIN1": "DSP_1_ACIN1", + "C43": "DSP_1_C43", + "INMODE2": "DSP_1_INMODE2", + "A2": "DSP_1_A2", + "PCOUT45": "DSP_1_PCOUT45", + "PATTERNDETECT": "DSP_1_PATTERNDETECT", + "A29": "DSP_1_A29", + "RSTA": "DSP_1_RSTA", + "ACOUT17": "DSP_1_ACOUT17", + "A14": "DSP_1_A14", + "CARRYOUT2": "DSP_1_CARRYOUT2", + "A12": "DSP_1_A12", + "BCIN4": "DSP_1_BCIN4", + "PCOUT40": "DSP_1_PCOUT40", + "CEA2": "DSP_1_CEA2", + "C30": "DSP_1_C30", + "P2": "DSP_1_P2", + "B14": "DSP_1_B14", + "P5": "DSP_1_P5", + "P18": "DSP_1_P18", + "ACOUT4": "DSP_1_ACOUT4", + "A0": "DSP_1_A0", + "ACOUT0": "DSP_1_ACOUT0", + "BCIN6": "DSP_1_BCIN6", + "BCIN13": "DSP_1_BCIN13", + "C40": "DSP_1_C40", + "P29": "DSP_1_P29", + "A4": "DSP_1_A4", + "PCOUT21": "DSP_1_PCOUT21", + "ALUMODE1": "DSP_1_ALUMODE1", + "C22": "DSP_1_C22", + "BCOUT8": "DSP_1_BCOUT8", + "P14": "DSP_1_P14", + "OPMODE6": "DSP_1_OPMODE6", + "PCOUT22": "DSP_1_PCOUT22", + "BCIN16": "DSP_1_BCIN16", + "ACOUT5": "DSP_1_ACOUT5", + "ACIN14": "DSP_1_ACIN14", + "D8": "DSP_1_D8", + "RSTINMODE": "DSP_1_RSTINMODE", + "PCOUT13": "DSP_1_PCOUT13", + "ALUMODE2": "DSP_1_ALUMODE2", + "P45": "DSP_1_P45", + "BCIN7": "DSP_1_BCIN7", + "ACOUT9": "DSP_1_ACOUT9", + "P38": "DSP_1_P38", + "PCIN28": "DSP_1_PCIN28", + "C26": "DSP_1_C26", + "P21": "DSP_1_P21", + "ACIN12": "DSP_1_ACIN12", + "ACOUT20": "DSP_1_ACOUT20", + "BCOUT16": "DSP_1_BCOUT16", + "A8": "DSP_1_A8", + "C47": "DSP_1_C47", + "PCIN44": "DSP_1_PCIN44", + "A23": "DSP_1_A23", + "C34": "DSP_1_C34", + "C12": "DSP_1_C12", + "P4": "DSP_1_P4", + "OPMODE1": "DSP_1_OPMODE1", + "B13": "DSP_1_B13", + "CEC": "DSP_1_CEC", + "A26": "DSP_1_A26", + "PCIN9": "DSP_1_PCIN9", + "PCIN32": "DSP_1_PCIN32", + "D7": "DSP_1_D7", + "PCOUT27": "DSP_1_PCOUT27", + "P34": "DSP_1_P34", + "BCOUT6": "DSP_1_BCOUT6", + "BCIN15": "DSP_1_BCIN15", + "PCIN10": "DSP_1_PCIN10", + "PCIN0": "DSP_1_PCIN0", + "BCOUT14": "DSP_1_BCOUT14", + "CARRYIN": "DSP_1_CARRYIN", + "PCIN43": "DSP_1_PCIN43", + "D21": "DSP_1_D21", + "BCOUT17": "DSP_1_BCOUT17", + "PCIN13": "DSP_1_PCIN13", + "A9": "DSP_1_A9", + "PCIN6": "DSP_1_PCIN6", + "CLK": "DSP_1_CLK", + "PCIN4": "DSP_1_PCIN4", + "C25": "DSP_1_C25", + "CECARRYIN": "DSP_1_CECARRYIN", + "BCIN5": "DSP_1_BCIN5", + "C19": "DSP_1_C19", + "P13": "DSP_1_P13", + "INMODE1": "DSP_1_INMODE1", + "PCIN23": "DSP_1_PCIN23", + "P44": "DSP_1_P44", + "B15": "DSP_1_B15", + "A15": "DSP_1_A15", + "BCOUT11": "DSP_1_BCOUT11", + "A18": "DSP_1_A18", + "P0": "DSP_1_P0", + "C7": "DSP_1_C7", + "ACOUT2": "DSP_1_ACOUT2", + "ACIN7": "DSP_1_ACIN7", + "D20": "DSP_1_D20", + "D13": "DSP_1_D13", + "A19": "DSP_1_A19", + "PCOUT44": "DSP_1_PCOUT44", + "BCOUT10": "DSP_1_BCOUT10", + "CECTRL": "DSP_1_CECTRL", + "PCIN33": "DSP_1_PCIN33", + "D10": "DSP_1_D10", + "BCOUT13": "DSP_1_BCOUT13", + "B11": "DSP_1_B11", + "ACOUT8": "DSP_1_ACOUT8", + "INMODE3": "DSP_1_INMODE3", + "B6": "DSP_1_B6", + "OPMODE3": "DSP_1_OPMODE3", + "ACIN17": "DSP_1_ACIN17", + "P28": "DSP_1_P28", + "P20": "DSP_1_P20", + "C4": "DSP_1_C4", + "B8": "DSP_1_B8", + "B4": "DSP_1_B4", + "A6": "DSP_1_A6", + "P41": "DSP_1_P41", + "ACIN4": "DSP_1_ACIN4", + "PCOUT41": "DSP_1_PCOUT41", + "D4": "DSP_1_D4", + "D14": "DSP_1_D14", + "ACOUT27": "DSP_1_ACOUT27", + "PCOUT5": "DSP_1_PCOUT5", + "ACOUT24": "DSP_1_ACOUT24", + "C11": "DSP_1_C11", + "PCOUT34": "DSP_1_PCOUT34", + "C5": "DSP_1_C5", + "A7": "DSP_1_A7", + "ACIN13": "DSP_1_ACIN13", + "ACIN28": "DSP_1_ACIN28", + "P11": "DSP_1_P11", + "A11": "DSP_1_A11", + "PCOUT30": "DSP_1_PCOUT30", + "C23": "DSP_1_C23", + "P32": "DSP_1_P32", + "D3": "DSP_1_D3", + "ACOUT6": "DSP_1_ACOUT6", + "P22": "DSP_1_P22", + "C46": "DSP_1_C46", + "CARRYCASCIN": "DSP_1_CARRYCASCIN", + "P35": "DSP_1_P35", + "PCIN17": "DSP_1_PCIN17", + "PCIN21": "DSP_1_PCIN21", + "BCOUT7": "DSP_1_BCOUT7", + "PCOUT15": "DSP_1_PCOUT15", + "A20": "DSP_1_A20", + "C42": "DSP_1_C42", + "PCOUT18": "DSP_1_PCOUT18", + "PCOUT10": "DSP_1_PCOUT10", + "BCIN10": "DSP_1_BCIN10", + "ACIN22": "DSP_1_ACIN22", + "B9": "DSP_1_B9", + "A10": "DSP_1_A10", + "D17": "DSP_1_D17", + "ACIN2": "DSP_1_ACIN2", + "A13": "DSP_1_A13", + "PCOUT29": "DSP_1_PCOUT29", + "C6": "DSP_1_C6", + "PCIN2": "DSP_1_PCIN2", + "PCOUT35": "DSP_1_PCOUT35", + "ACOUT19": "DSP_1_ACOUT19", + "PCOUT7": "DSP_1_PCOUT7", + "C18": "DSP_1_C18", + "P7": "DSP_1_P7", + "BCIN3": "DSP_1_BCIN3", + "PCOUT16": "DSP_1_PCOUT16", + "C2": "DSP_1_C2", + "P46": "DSP_1_P46", + "ACOUT7": "DSP_1_ACOUT7", + "PCOUT36": "DSP_1_PCOUT36", + "A5": "DSP_1_A5", + "ACIN9": "DSP_1_ACIN9", + "A24": "DSP_1_A24", + "P27": "DSP_1_P27", + "ACIN24": "DSP_1_ACIN24", + "CARRYOUT1": "DSP_1_CARRYOUT1", + "ACOUT12": "DSP_1_ACOUT12", + "BCOUT15": "DSP_1_BCOUT15", + "B3": "DSP_1_B3", + "P33": "DSP_1_P33", + "PCIN47": "DSP_1_PCIN47", + "PATTERNBDETECT": "DSP_1_PATTERNBDETECT", + "P37": "DSP_1_P37", + "P12": "DSP_1_P12", + "BCIN12": "DSP_1_BCIN12", + "RSTP": "DSP_1_RSTP", + "BCOUT3": "DSP_1_BCOUT3", + "OPMODE5": "DSP_1_OPMODE5", + "C44": "DSP_1_C44", + "BCIN11": "DSP_1_BCIN11", + "PCIN12": "DSP_1_PCIN12", + "C1": "DSP_1_C1", + "PCOUT24": "DSP_1_PCOUT24", + "PCIN19": "DSP_1_PCIN19", + "PCOUT9": "DSP_1_PCOUT9", + "ACIN23": "DSP_1_ACIN23" + }, + "x_coord": 0 + }, + { + "y_coord": 117, + "name": "X10Y117", + "prefix": "TIEOFF", + "type": "TIEOFF", + "site_pins": { + "HARD0": "DSP_GND_R", + "HARD1": "DSP_VCC_R" + }, + "x_coord": 10 + } + ], + "wires": [ + "DSP_1_P44", + "DSP_BYP6_4", + "DSP_PCOUT37", + "DSP_BYP7_4", + "DSP_MONITOR_N_3", + "DSP_BCOUT13", + "DSP_0_D7", + "DSP_1_BCIN6", + "DSP_0_PCIN5", + "DSP_0_PCOUT45", + "DSP_0_C16", + "DSP_MONITOR_P_1", + "DSP_1_MULTSIGNOUT", + "DSP_SE4BEG0_4", + "DSP_1_PCOUT3", + "DSP_0_BCIN14", + "DSP_LOGIC_OUTS_B5_0", + "DSP_0_PCOUT41", + "DSP_WW2END0_3", + "DSP_0_P42", + "DSP_LOGIC_OUTS_B11_2", + "DSP_IMUX41_0", + "DSP_0_UNDERFLOW", + "DSP_SW4END2_4", + "DSP_LOGIC_OUTS_B16_1", + "DSP_1_C47", + "DSP_LOGIC_OUTS_B7_0", + "DSP_0_ACIN1", + "DSP_EE4BEG0_2", + "DSP_0_ACIN15", + "DSP_1_C45", + "DSP_1_P41", + "DSP_CLK0_4", + "DSP_1_C16", + "DSP_1_BCIN1", + "DSP_1_ACIN10", + "DSP_NW4A3_2", + "DSP_1_P18", + "DSP_PCOUT39", + "DSP_0_PCOUT3", + "DSP_EE2BEG3_4", + "DSP_IMUX26_0", + "DSP_EE4B3_0", + "DSP_1_P10", + "DSP_0_OPMODE4", + "DSP_1_PCOUT43", + "DSP_0_PCIN7", + "DSP_0_PCOUT24", + "DSP_BCOUT11", + "DSP_0_C7", + "DSP_IMUX5_0", + "DSP_0_P1", + "DSP_EE4C0_3", + "DSP_IMUX14_1", + "DSP_1_PCOUT28", + "DSP_EE4BEG1_4", + "DSP_LOGIC_OUTS_B12_1", + "DSP_1_BCOUT8", + "DSP_EE4B3_3", + "DSP_ER1BEG0_4", + "DSP_0_PCIN46", + "DSP_0_PCIN1", + "DSP_0_C1", + "DSP_FAN3_0", + "DSP_WW2A2_2", + "DSP_0_P38", + "DSP_LOGIC_OUTS_B6_1", + "DSP_1_PCOUT19", + "DSP_IMUX23_2", + "DSP_0_D11", + "DSP_LOGIC_OUTS_B21_2", + "DSP_PCOUT24", + "DSP_NW2A2_4", + "DSP_SE2A1_4", + "DSP_IMUX1_3", + "DSP_0_PCOUT43", + "DSP_WR1END1_2", + "DSP_IMUX24_1", + "DSP_IMUX47_4", + "DSP_1_PCOUT10", + "DSP_0_ACIN20", + "DSP_WW4B2_4", + "DSP_IMUX37_2", + "DSP_ER1BEG1_0", + "DSP_1_D20", + "DSP_1_INMODE0", + "DSP_IMUX12_4", + "DSP_IMUX19_4", + "DSP_1_D10", + "DSP_NE4C2_3", + "DSP_1_ACIN18", + "DSP_1_ACIN5", + "DSP_EE4C2_3", + "DSP_EE2A1_0", + "DSP_0_PCOUT6", + "DSP_0_D17", + "DSP_SW2A0_4", + "DSP_0_A11", + "DSP_LOGIC_OUTS_B18_4", + "DSP_CLK1_3", + "DSP_1_D5", + "DSP_SE2A1_1", + "DSP_1_ALUMODE1", + "DSP_NE2A0_3", + "DSP_MONITOR_P_2", + "DSP_0_A15", + "DSP_LOGIC_OUTS_B23_1", + "DSP_SE4BEG2_1", + "DSP_1_A2", + "DSP_BYP7_1", + "DSP_0_BCIN10", + "DSP_0_BCIN5", + "DSP_LH6_0", + "DSP_LOGIC_OUTS_B15_3", + "DSP_BYP5_3", + "DSP_PCOUT5", + "DSP_1_ACOUT3", + "DSP_NW4A1_0", + "DSP_NW2A1_0", + "DSP_WW4C0_4", + "DSP_SE2A2_1", + "DSP_0_P5", + "DSP_0_C27", + "DSP_FAN6_2", + "DSP_EE4A1_4", + "DSP_IMUX41_2", + "DSP_LOGIC_OUTS_B23_3", + "DSP_LOGIC_OUTS_B13_4", + "DSP_0_CEB1", + "DSP_EL1BEG0_2", + "DSP_0_ACOUT19", + "DSP_1_ACOUT28", + "DSP_EE4C3_3", + "DSP_0_PCIN3", + "DSP_IMUX21_2", + "DSP_1_PCIN44", + "DSP_0_B4", + "DSP_IMUX45_4", + "DSP_1_PATTERNDETECT", + "DSP_LOGIC_OUTS_B4_3", + "DSP_SW4A2_1", + "DSP_0_P20", + "DSP_SE4C1_1", + "DSP_BLOCK_OUTS_B0_4", + "DSP_BYP7_0", + "DSP_FAN5_3", + "DSP_IMUX30_3", + "DSP_NW4END2_3", + "DSP_0_D9", + "DSP_1_D7", + "DSP_LOGIC_OUTS_B3_1", + "DSP_IMUX1_1", + "DSP_1_PCOUT8", + "DSP_BYP2_1", + "DSP_1_BCIN15", + "DSP_EE4B2_0", + "DSP_LH11_4", + "DSP_NW2A0_0", + "DSP_0_BCOUT10", + "DSP_NE4C0_3", + "DSP_LOGIC_OUTS_B13_3", + "DSP_WL1END1_2", + "DSP_1_B13", + "DSP_1_C24", + "DSP_IMUX38_0", + "DSP_WW4C3_2", + "DSP_NE4C0_1", + "DSP_IMUX42_2", + "DSP_0_P8", + "DSP_0_C43", + "DSP_IMUX0_4", + "DSP_NW4END1_0", + "DSP_BCOUT3", + "DSP_NW4A2_4", + "DSP_CLK1_1", + "DSP_LOGIC_OUTS_B18_1", + "DSP_PCOUT14", + "DSP_NW4END2_1", + "DSP_EE4BEG0_3", + "DSP_1_PCIN15", + "DSP_WL1END2_3", + "DSP_PCOUT31", + "DSP_IMUX34_1", + "DSP_ACOUT21", + "DSP_EE4BEG1_2", + "DSP_0_P44", + "DSP_1_PCIN20", + "DSP_0_C18", + "DSP_IMUX18_1", + "DSP_EE2BEG0_1", + "DSP_NE4BEG1_4", + "DSP_PCOUT6", + "DSP_1_BCIN16", + "DSP_LH2_2", + "DSP_1_CEINMODE", + "DSP_0_C12", + "DSP_1_PCIN27", + "DSP_SW4A1_2", + "DSP_0_ACOUT21", + "DSP_1_PCOUT44", + "DSP_WL1END0_1", + "DSP_0_OVERFLOW", + "DSP_1_RSTP", + "DSP_WR1END1_3", + "DSP_0_BCOUT6", + "DSP_1_ACIN21", + "DSP_FAN7_4", + "DSP_1_C3", + "DSP_EE2BEG3_0", + "DSP_LH8_2", + "DSP_1_ACOUT20", + "DSP_1_C38", + "DSP_0_PCIN44", + "DSP_0_ALUMODE2", + "DSP_IMUX10_2", + "DSP_LOGIC_OUTS_B16_4", + "DSP_WW2END0_2", + "DSP_1_BCOUT10", + "DSP_ACOUT29", + "DSP_LOGIC_OUTS_B23_4", + "DSP_1_PCIN8", + "DSP_1_C14", + "DSP_0_BCIN9", + "DSP_1_PCOUT31", + "DSP_1_OPMODE4", + "DSP_0_C9", + "DSP_SW4END3_1", + "DSP_1_C20", + "DSP_PCOUT1", + "DSP_IMUX16_1", + "DSP_IMUX13_1", + "DSP_ER1BEG3_3", + "DSP_MONITOR_P_3", + "DSP_NW2A3_4", + "DSP_1_P36", + "DSP_LOGIC_OUTS_B2_0", + "DSP_1_C13", + "DSP_IMUX21_1", + "DSP_PCOUT9", + "DSP_PCOUT25", + "DSP_0_C36", + "DSP_LH9_0", + "DSP_SW4A1_3", + "DSP_IMUX20_0", + "DSP_0_RSTM", + "DSP_1_PCOUT2", + "DSP_BYP0_0", + "DSP_1_C41", + "DSP_IMUX8_2", + "DSP_WR1END3_4", + "DSP_EL1BEG2_4", + "DSP_0_PCIN24", + "DSP_WW4A2_2", + "DSP_ACOUT25", + "DSP_1_P3", + "DSP_IMUX46_4", + "DSP_CARRYCASCOUT", + "DSP_LH10_4", + "DSP_1_PCOUT29", + "DSP_LOGIC_OUTS_B5_1", + "DSP_0_PCOUT25", + "DSP_SE2A0_2", + "DSP_NW2A3_1", + "DSP_1_PCOUT25", + "DSP_0_BCOUT16", + "DSP_0_C38", + "DSP_BYP6_1", + "DSP_WW4A0_4", + "DSP_IMUX46_3", + "DSP_0_PCOUT7", + "DSP_0_B9", + "DSP_WW4A0_3", + "DSP_1_BCIN10", + "DSP_0_B5", + "DSP_IMUX36_4", + "DSP_0_A4", + "DSP_PCOUT22", + "DSP_IMUX27_2", + "DSP_0_P10", + "DSP_0_D1", + "DSP_1_ACOUT29", + "DSP_1_PCIN41", + "DSP_EE4BEG1_0", + "DSP_NE2A0_0", + "DSP_MULTSIGNOUT", + "DSP_0_ALUMODE0", + "DSP_1_OPMODE3", + "DSP_EE4B0_4", + "DSP_IMUX34_4", + "DSP_EE4BEG0_0", + "DSP_EE2A0_2", + "DSP_IMUX3_4", + "DSP_0_PCOUT14", + "DSP_FAN3_1", + "DSP_0_C33", + "DSP_0_PCOUT21", + "DSP_IMUX30_4", + "DSP_WW4B3_1", + "DSP_CTRL1_1", + "DSP_1_OVERFLOW", + "DSP_FAN2_4", + "DSP_BYP5_2", + "DSP_NE4BEG0_1", + "DSP_0_PCOUT30", + "DSP_WW4B1_3", + "DSP_0_BCIN3", + "DSP_NE2A0_1", + "DSP_0_P6", + "DSP_NE4C2_0", + "DSP_IMUX16_2", + "DSP_NW4A1_1", + "DSP_0_ALUMODE1", + "DSP_0_PCOUT15", + "DSP_1_PCIN21", + "DSP_1_BCIN13", + "DSP_0_C4", + "DSP_IMUX13_3", + "DSP_0_PCIN4", + "DSP_LOGIC_OUTS_B8_2", + "DSP_LH2_0", + "DSP_0_D22", + "DSP_1_P40", + "DSP_1_CECARRYIN", + "DSP_1_A28", + "DSP_SE4BEG1_1", + "DSP_SE2A2_0", + "DSP_1_CEB1", + "DSP_0_BCIN2", + "DSP_NE4C3_3", + "DSP_1_P0", + "DSP_1_BCIN12", + "DSP_SE4C3_4", + "DSP_SE4BEG2_2", + "DSP_1_BCIN17", + "DSP_WL1END2_0", + "DSP_LOGIC_OUTS_B0_3", + "DSP_1_PCIN1", + "DSP_WR1END0_4", + "DSP_WL1END1_3", + "DSP_1_PCIN40", + "DSP_0_PCIN16", + "DSP_LH11_0", + "DSP_FAN2_3", + "DSP_0_ACOUT0", + "DSP_WW4END3_1", + "DSP_WW4C1_1", + "DSP_SE2A0_0", + "DSP_EE4A1_3", + "DSP_NE2A2_2", + "DSP_IMUX18_2", + "DSP_IMUX28_0", + "DSP_LH4_4", + "DSP_FAN6_4", + "DSP_IMUX13_2", + "DSP_0_CARRYOUT0", + "DSP_1_P25", + "DSP_0_C24", + "DSP_IMUX7_2", + "DSP_WW4C1_2", + "DSP_0_PCOUT44", + "DSP_1_PCOUT15", + "DSP_NE2A3_2", + "DSP_WW4B2_3", + "DSP_IMUX36_0", + "DSP_NE4BEG1_0", + "DSP_0_PCIN18", + "DSP_IMUX46_0", + "DSP_0_CARRYINSEL2", + "DSP_EE2A1_4", + "DSP_ACOUT14", + "DSP_1_A10", + "DSP_BYP3_2", + "DSP_0_A18", + "DSP_WW4C3_0", + "DSP_WW4C2_3", + "DSP_SE4C1_0", + "DSP_BCOUT5", + "DSP_LOGIC_OUTS_B1_0", + "DSP_1_PCIN0", + "DSP_WR1END1_1", + "DSP_LH1_0", + "DSP_SW2A2_3", + "DSP_1_ACOUT10", + "DSP_IMUX15_0", + "DSP_IMUX12_0", + "DSP_BYP7_2", + "DSP_1_ACOUT9", + "DSP_1_CARRYINSEL2", + "DSP_1_A24", + "DSP_EE2A0_4", + "DSP_EE4B0_3", + "DSP_1_PCOUT45", + "DSP_ACOUT19", + "DSP_0_PATTERNDETECT", + "DSP_1_B3", + "DSP_WW2A2_4", + "DSP_LOGIC_OUTS_B4_1", + "DSP_IMUX39_4", + "DSP_0_P3", + "DSP_SW2A2_0", + "DSP_IMUX13_0", + "DSP_NE2A2_3", + "DSP_SE4BEG0_0", + "DSP_LOGIC_OUTS_B16_3", + "DSP_NW4END3_4", + "DSP_NW4END3_1", + "DSP_WW4B2_1", + "DSP_0_BCOUT14", + "DSP_WW2END2_1", + "DSP_BLOCK_OUTS_B2_3", + "DSP_PCOUT43", + "DSP_0_PCOUT46", + "DSP_WW2END1_3", + "DSP_0_INMODE3", + "DSP_SW4END0_3", + "DSP_0_PCOUT39", + "DSP_SE2A0_4", + "DSP_0_RSTA", + "DSP_NW4END0_2", + "DSP_EE2A1_3", + "DSP_0_CARRYCASCIN", + "DSP_SW2A3_4", + "DSP_IMUX43_1", + "DSP_IMUX15_3", + "DSP_LH10_1", + "DSP_0_ACIN2", + "DSP_0_OPMODE2", + "DSP_NE2A2_0", + "DSP_EE2A1_2", + "DSP_EE4BEG3_2", + "DSP_EE2BEG1_3", + "DSP_SW2A0_1", + "DSP_IMUX22_1", + "DSP_EE4A1_1", + "DSP_SW4A1_4", + "DSP_PCOUT41", + "DSP_IMUX19_3", + "DSP_SE4BEG3_2", + "DSP_1_P23", + "DSP_0_A26", + "DSP_FAN1_3", + "DSP_EE4C1_3", + "DSP_BCOUT17", + "DSP_1_A29", + "DSP_EE2A2_2", + "DSP_BLOCK_OUTS_B1_0", + "DSP_LH10_3", + "DSP_0_CLK", + "DSP_1_ACOUT15", + "DSP_1_PCOUT27", + "DSP_IMUX2_1", + "DSP_0_ACIN26", + "DSP_WW4B0_4", + "DSP_0_A10", + "DSP_LOGIC_OUTS_B10_3", + "DSP_0_D14", + "DSP_NW4END3_2", + "DSP_0_BCIN17", + "DSP_1_PCIN43", + "DSP_0_P11", + "DSP_1_B15", + "DSP_LOGIC_OUTS_B18_2", + "DSP_0_A14", + "DSP_IMUX47_3", + "DSP_1_PCOUT13", + "DSP_1_ACIN29", + "DSP_LOGIC_OUTS_B9_3", + "DSP_1_ACOUT1", + "DSP_EE4BEG2_3", + "DSP_0_P46", + "DSP_1_PCIN36", + "DSP_IMUX19_2", + "DSP_1_ACIN22", + "DSP_1_PCIN7", + "DSP_CTRL1_4", + "DSP_IMUX11_1", + "DSP_EL1BEG1_2", + "DSP_ER1BEG3_4", + "DSP_LOGIC_OUTS_B4_2", + "DSP_EE4A3_2", + "DSP_0_PCOUT18", + "DSP_0_A29", + "DSP_1_ACIN2", + "DSP_1_CED", + "DSP_PCOUT0", + "DSP_NW2A1_1", + "DSP_ER1BEG2_3", + "DSP_1_RSTD", + "DSP_SW4A2_0", + "DSP_LOGIC_OUTS_B22_1", + "DSP_1_A18", + "DSP_IMUX32_1", + "DSP_IMUX44_4", + "DSP_FAN4_2", + "DSP_EE2BEG2_0", + "DSP_NW2A3_3", + "DSP_0_ACOUT5", + "DSP_1_BCOUT7", + "DSP_1_PCIN12", + "DSP_IMUX43_3", + "DSP_1_ACOUT8", + "DSP_IMUX41_4", + "DSP_1_D16", + "DSP_0_A8", + "DSP_EE2BEG3_3", + "DSP_LOGIC_OUTS_B7_3", + "DSP_1_C42", + "DSP_WW2END2_0", + "DSP_LH3_0", + "DSP_EE4C3_0", + "DSP_SW4A3_3", + "DSP_EE2BEG1_0", + "DSP_BCOUT9", + "DSP_0_PCIN30", + "DSP_1_P17", + "DSP_1_PCIN4", + "DSP_1_ACOUT26", + "DSP_IMUX34_2", + "DSP_0_D16", + "DSP_WW2END3_4", + "DSP_1_BCOUT12", + "DSP_1_B1", + "DSP_0_PCIN47", + "DSP_WW4A3_0", + "DSP_0_A12", + "DSP_WW2END1_2", + "DSP_NE2A2_1", + "DSP_EL1BEG1_1", + "DSP_WL1END1_0", + "DSP_LH12_0", + "DSP_0_BCIN7", + "DSP_NW4A1_4", + "DSP_1_PCOUT14", + "DSP_0_BCOUT12", + "DSP_IMUX4_4", + "DSP_1_PCOUT38", + "DSP_EE4B1_2", + "DSP_IMUX28_3", + "DSP_PCOUT4", + "DSP_WW2END3_1", + "DSP_SW4END2_1", + "DSP_IMUX22_2", + "DSP_1_C6", + "DSP_IMUX33_0", + "DSP_LOGIC_OUTS_B6_4", + "DSP_FAN0_1", + "DSP_1_OPMODE5", + "DSP_0_C14", + "DSP_1_P8", + "DSP_EE4BEG3_1", + "DSP_1_A25", + "DSP_EL1BEG0_4", + "DSP_IMUX4_1", + "DSP_SE4C3_1", + "DSP_0_BCIN8", + "DSP_LH9_3", + "DSP_BYP5_4", + "DSP_EL1BEG3_3", + "DSP_WW4A3_2", + "DSP_1_PCIN31", + "DSP_WW4A1_2", + "DSP_LOGIC_OUTS_B15_2", + "DSP_0_BCOUT15", + "DSP_1_A21", + "DSP_IMUX40_4", + "DSP_SW2A1_3", + "DSP_BYP0_4", + "DSP_WW2A0_4", + "DSP_1_C7", + "DSP_BLOCK_OUTS_B2_0", + "DSP_ACOUT4", + "DSP_BLOCK_OUTS_B0_0", + "DSP_IMUX20_4", + "DSP_NW2A2_1", + "DSP_1_PCIN32", + "DSP_0_ACIN22", + "DSP_0_INMODE0", + "DSP_IMUX9_3", + "DSP_WW4END2_1", + "DSP_1_B12", + "DSP_SW4END3_0", + "DSP_LOGIC_OUTS_B3_2", + "DSP_PCOUT17", + "DSP_1_BCOUT13", + "DSP_WW4A0_1", + "DSP_EE2BEG0_2", + "DSP_WW2A1_3", + "DSP_0_B8", + "DSP_CTRL0_3", + "DSP_1_CARRYINSEL1", + "DSP_ACOUT12", + "DSP_0_D12", + "DSP_NE4BEG3_3", + "DSP_IMUX1_2", + "DSP_IMUX6_3", + "DSP_WW2A1_1", + "DSP_1_P30", + "DSP_1_ACOUT24", + "DSP_0_ACIN25", + "DSP_NW4END2_2", + "DSP_SE4C2_3", + "DSP_EE4B3_1", + "DSP_0_PCIN38", + "DSP_1_C43", + "DSP_FAN0_0", + "DSP_NW4END0_1", + "DSP_WR1END3_2", + "DSP_1_INMODE2", + "DSP_WW4A1_0", + "DSP_NE2A1_4", + "DSP_IMUX32_0", + "DSP_1_ACOUT12", + "DSP_LOGIC_OUTS_B18_0", + "DSP_IMUX5_3", + "DSP_IMUX36_2", + "DSP_1_BCIN14", + "DSP_EE2BEG1_2", + "DSP_0_P41", + "DSP_EE4A2_1", + "DSP_NW2A0_3", + "DSP_EL1BEG2_3", + "DSP_1_ACIN27", + "DSP_EE2BEG3_2", + "DSP_0_RSTB", + "DSP_0_P29", + "DSP_WW2END0_0", + "DSP_0_INMODE1", + "DSP_0_ACOUT18", + "DSP_LOGIC_OUTS_B9_1", + "DSP_BYP4_4", + "DSP_SE4BEG3_4", + "DSP_1_BCOUT2", + "DSP_1_ACIN26", + "DSP_NW4A0_2", + "DSP_1_ACOUT6", + "DSP_CTRL0_1", + "DSP_BLOCK_OUTS_B2_2", + "DSP_SE4BEG2_0", + "DSP_NE4BEG1_1", + "DSP_IMUX17_4", + "DSP_IMUX15_4", + "DSP_PCOUT42", + "DSP_0_C26", + "DSP_NE4BEG0_2", + "DSP_WW4END3_2", + "DSP_LH7_4", + "DSP_0_BCIN16", + "DSP_SE4C1_2", + "DSP_FAN0_2", + "DSP_1_PCIN28", + "DSP_IMUX3_0", + "DSP_IMUX25_2", + "DSP_EE4A3_4", + "DSP_WW2A3_3", + "DSP_0_PCOUT28", + "DSP_NW4A3_0", + "DSP_SE2A2_2", + "DSP_IMUX32_2", + "DSP_LOGIC_OUTS_B11_3", + "DSP_0_D15", + "DSP_0_ACIN4", + "DSP_NW2A2_0", + "DSP_1_PCIN42", + "DSP_0_CEC", + "DSP_SW4END2_3", + "DSP_1_ACIN12", + "DSP_0_PCOUT12", + "DSP_CLK1_4", + "DSP_0_PCOUT5", + "DSP_LOGIC_OUTS_B20_3", + "DSP_BCOUT12", + "DSP_SW4END3_3", + "DSP_1_D18", + "DSP_1_P2", + "DSP_ACOUT24", + "DSP_WR1END2_3", + "DSP_FAN3_3", + "DSP_LH12_4", + "DSP_NW4END0_3", + "DSP_EE4C2_0", + "DSP_0_P16", + "DSP_IMUX39_0", + "DSP_0_PCIN32", + "DSP_PCOUT7", + "DSP_LH11_1", + "DSP_IMUX12_2", + "DSP_LOGIC_OUTS_B1_4", + "DSP_LOGIC_OUTS_B5_3", + "DSP_LH5_3", + "DSP_ACOUT9", + "DSP_EE4BEG2_4", + "DSP_0_CARRYINSEL1", + "DSP_IMUX28_4", + "DSP_IMUX8_1", + "DSP_1_P5", + "DSP_1_PCIN17", + "DSP_1_D17", + "DSP_IMUX31_2", + "DSP_SW4END1_0", + "DSP_0_A19", + "DSP_1_PCIN35", + "DSP_ER1BEG0_1", + "DSP_IMUX1_0", + "DSP_0_PCIN11", + "DSP_CLK0_0", + "DSP_IMUX12_3", + "DSP_NW2A1_3", + "DSP_LOGIC_OUTS_B8_0", + "DSP_WR1END1_0", + "DSP_WW4A3_1", + "DSP_WW4A1_1", + "DSP_WW4B1_1", + "DSP_1_PCOUT40", + "DSP_0_P28", + "DSP_SW2A2_2", + "DSP_0_PCOUT16", + "DSP_1_D19", + "DSP_PCOUT23", + "DSP_BLOCK_OUTS_B1_4", + "DSP_0_D20", + "DSP_FAN7_0", + "DSP_SE4C1_3", + "DSP_SW2A0_2", + "DSP_WL1END0_2", + "DSP_1_PCIN3", + "DSP_1_D1", + "DSP_1_B4", + "DSP_FAN4_1", + "DSP_NW4A0_3", + "DSP_0_OPMODE5", + "DSP_1_B17", + "DSP_1_CARRYOUT1", + "DSP_0_C35", + "DSP_NE4C3_4", + "DSP_LH8_1", + "DSP_LH5_4", + "DSP_0_A0", + "DSP_1_P31", + "DSP_BCOUT4", + "DSP_0_D0", + "DSP_IMUX35_0", + "DSP_1_D0", + "DSP_ACOUT23", + "DSP_IMUX29_3", + "DSP_SE4C3_3", + "DSP_SW4A1_1", + "DSP_WL1END1_4", + "DSP_PCOUT16", + "DSP_IMUX10_3", + "DSP_WW4END2_4", + "DSP_LH3_1", + "DSP_LH9_1", + "DSP_LH1_1", + "DSP_0_P45", + "DSP_1_A23", + "DSP_LOGIC_OUTS_B20_0", + "DSP_1_ACIN19", + "DSP_1_BCIN11", + "DSP_FAN0_3", + "DSP_EE2A1_1", + "DSP_1_PCOUT20", + "DSP_WW4B1_2", + "DSP_EE4BEG1_1", + "DSP_WW4A0_0", + "DSP_LOGIC_OUTS_B7_4", + "DSP_WW4C0_3", + "DSP_FAN2_2", + "DSP_0_B17", + "DSP_0_P31", + "DSP_0_BCOUT9", + "DSP_1_BCIN5", + "DSP_0_B12", + "DSP_IMUX11_0", + "DSP_1_C0", + "DSP_0_ACOUT22", + "DSP_0_P17", + "DSP_NE4BEG3_4", + "DSP_0_PCIN39", + "DSP_BYP3_3", + "DSP_1_C12", + "DSP_1_D8", + "DSP_BLOCK_OUTS_B0_1", + "DSP_1_ACIN1", + "DSP_IMUX9_0", + "DSP_WW4B2_0", + "DSP_0_CEM", + "DSP_1_A26", + "DSP_0_BCOUT3", + "DSP_LOGIC_OUTS_B9_2", + "DSP_IMUX15_2", + "DSP_NE4BEG1_2", + "DSP_LH8_4", + "DSP_IMUX3_2", + "DSP_0_P36", + "DSP_BLOCK_OUTS_B3_0", + "DSP_NE2A3_4", + "DSP_1_C11", + "DSP_0_PCOUT23", + "DSP_ACOUT3", + "DSP_BLOCK_OUTS_B1_1", + "DSP_IMUX38_1", + "DSP_0_P15", + "DSP_1_PCOUT22", + "DSP_0_C34", + "DSP_WW4B3_2", + "DSP_1_RSTINMODE", + "DSP_1_P37", + "DSP_0_P30", + "DSP_CTRL0_0", + "DSP_1_PCOUT46", + "DSP_LOGIC_OUTS_B22_4", + "DSP_0_PCOUT34", + "DSP_1_P22", + "DSP_IMUX47_0", + "DSP_EL1BEG3_1", + "DSP_WW2END0_1", + "DSP_NW4A2_1", + "DSP_SE4C2_0", + "DSP_1_D9", + "DSP_BYP0_1", + "DSP_NE4BEG3_0", + "DSP_LOGIC_OUTS_B1_2", + "DSP_IMUX8_0", + "DSP_1_P33", + "DSP_0_CEP", + "DSP_1_PCIN26", + "DSP_1_PCOUT42", + "DSP_LOGIC_OUTS_B12_2", + "DSP_SW2A2_4", + "DSP_BCOUT8", + "DSP_IMUX45_3", + "DSP_WW4C3_3", + "DSP_0_P9", + "DSP_SW2A0_3", + "DSP_IMUX11_4", + "DSP_IMUX29_0", + "DSP_0_BCIN4", + "DSP_0_BCOUT4", + "DSP_0_PCIN27", + "DSP_SE4C3_0", + "DSP_IMUX25_4", + "DSP_1_BCIN4", + "DSP_ACOUT8", + "DSP_0_P24", + "DSP_EE2BEG0_3", + "DSP_CLK0_1", + "DSP_IMUX12_1", + "DSP_CTRL1_0", + "DSP_LOGIC_OUTS_B11_0", + "DSP_0_BCOUT5", + "DSP_ACOUT26", + "DSP_WR1END2_1", + "DSP_0_C19", + "DSP_WW4END1_3", + "DSP_LOGIC_OUTS_B1_1", + "DSP_0_PCIN29", + "DSP_1_A6", + "DSP_0_D19", + "DSP_NE4BEG0_3", + "DSP_LOGIC_OUTS_B10_2", + "DSP_1_C29", + "DSP_EE4A3_1", + "DSP_PCOUT21", + "DSP_1_P35", + "DSP_CTRL1_3", + "DSP_1_P32", + "DSP_1_C33", + "DSP_EE4C1_0", + "DSP_EE4B1_1", + "DSP_1_ACIN17", + "DSP_IMUX2_0", + "DSP_IMUX18_0", + "DSP_NW2A1_2", + "DSP_EE2A0_0", + "DSP_NE2A0_2", + "DSP_1_RSTC", + "DSP_IMUX45_1", + "DSP_1_B16", + "DSP_LOGIC_OUTS_B17_0", + "DSP_1_CECTRL", + "DSP_0_C11", + "DSP_EE2BEG2_3", + "DSP_LH10_2", + "DSP_0_A13", + "DSP_0_C44", + "DSP_WW4A3_3", + "DSP_WW4END1_4", + "DSP_SE2A0_1", + "DSP_LH9_2", + "DSP_CLK0_3", + "DSP_BYP5_0", + "DSP_1_B14", + "DSP_0_CARRYOUT2", + "DSP_EL1BEG3_4", + "DSP_1_CLK", + "DSP_1_ACIN14", + "DSP_PCOUT44", + "DSP_1_P38", + "DSP_SW4END0_2", + "DSP_IMUX6_0", + "DSP_NE4C0_0", + "DSP_IMUX21_3", + "DSP_NW4END1_2", + "DSP_LOGIC_OUTS_B15_1", + "DSP_1_ACOUT25", + "DSP_IMUX0_2", + "DSP_WW2END1_4", + "DSP_NE4C2_1", + "DSP_IMUX40_0", + "DSP_IMUX17_3", + "DSP_IMUX6_4", + "DSP_1_C21", + "DSP_1_A14", + "DSP_1_CEA1", + "DSP_WW2A1_2", + "DSP_0_A1", + "DSP_LOGIC_OUTS_B21_3", + "DSP_0_PCOUT35", + "DSP_WW2END0_4", + "DSP_1_A11", + "DSP_MONITOR_P_0", + "DSP_1_PCOUT18", + "DSP_0_C25", + "DSP_1_RSTM", + "DSP_0_C2", + "DSP_LOGIC_OUTS_B4_4", + "DSP_PCOUT8", + "DSP_WW2END3_0", + "DSP_LH4_1", + "DSP_ER1BEG2_1", + "DSP_IMUX16_0", + "DSP_IMUX46_1", + "DSP_1_PCIN25", + "DSP_1_A20", + "DSP_LH5_0", + "DSP_IMUX35_3", + "DSP_0_B14", + "DSP_0_CEA2", + "DSP_NE2A3_1", + "DSP_1_P7", + "DSP_NE4BEG3_2", + "DSP_0_A16", + "DSP_EE4B0_0", + "DSP_IMUX40_1", + "DSP_EL1BEG2_2", + "DSP_LOGIC_OUTS_B21_4", + "DSP_EE4A1_0", + "DSP_FAN3_2", + "DSP_EE4A0_3", + "DSP_NE4C1_1", + "DSP_IMUX6_1", + "DSP_SW2A0_0", + "DSP_ER1BEG3_0", + "DSP_NW2A0_1", + "DSP_0_ACIN27", + "DSP_IMUX33_1", + "DSP_0_PCOUT11", + "DSP_EL1BEG2_0", + "DSP_WR1END1_4", + "DSP_VCC_R", + "DSP_IMUX42_3", + "DSP_IMUX39_2", + "DSP_FAN2_0", + "DSP_1_A5", + "DSP_EE4C0_2", + "DSP_IMUX25_0", + "DSP_WW4C1_4", + "DSP_0_P22", + "DSP_BYP1_4", + "DSP_BYP4_1", + "DSP_0_ACIN9", + "DSP_BYP0_2", + "DSP_0_PCIN35", + "DSP_0_A6", + "DSP_LH3_3", + "DSP_IMUX9_1", + "DSP_IMUX5_2", + "DSP_FAN7_3", + "DSP_1_BCOUT6", + "DSP_SE4C0_0", + "DSP_0_BCOUT1", + "DSP_0_C22", + "DSP_0_B0", + "DSP_WW2END3_2", + "DSP_1_P24", + "DSP_0_ACOUT28", + "DSP_1_PCOUT21", + "DSP_0_C41", + "DSP_WR1END0_1", + "DSP_WW4B3_3", + "DSP_NE4C2_4", + "DSP_1_D4", + "DSP_0_D18", + "DSP_LOGIC_OUTS_B10_4", + "DSP_FAN7_1", + "DSP_1_ALUMODE2", + "DSP_NE4BEG2_0", + "DSP_EE4BEG2_1", + "DSP_EL1BEG3_2", + "DSP_1_P45", + "DSP_LOGIC_OUTS_B13_1", + "DSP_1_PCIN29", + "DSP_SE4BEG0_1", + "DSP_1_P6", + "DSP_1_ACIN24", + "DSP_0_P4", + "DSP_LH1_4", + "DSP_WW4B3_4", + "DSP_SW4END1_4", + "DSP_1_P46", + "DSP_NE2A3_3", + "DSP_0_ACIN29", + "DSP_IMUX8_4", + "DSP_EL1BEG0_0", + "DSP_0_ACIN18", + "DSP_0_D21", + "DSP_1_ACOUT22", + "DSP_0_C47", + "DSP_IMUX4_0", + "DSP_EE4C2_1", + "DSP_BCOUT6", + "DSP_1_P4", + "DSP_1_C31", + "DSP_1_BCOUT3", + "DSP_EE2A3_4", + "DSP_WW2END2_3", + "DSP_EE4A2_3", + "DSP_EE2A3_3", + "DSP_1_ACIN9", + "DSP_0_PCOUT40", + "DSP_0_ACOUT25", + "DSP_WR1END2_0", + "DSP_0_ACOUT24", + "DSP_FAN5_0", + "DSP_LH10_0", + "DSP_LOGIC_OUTS_B14_2", + "DSP_EE2A2_1", + "DSP_0_ACOUT2", + "DSP_1_C35", + "DSP_1_ACOUT4", + "DSP_1_D21", + "DSP_0_PCOUT17", + "DSP_WW4A2_3", + "DSP_1_D3", + "DSP_EE2BEG2_4", + "DSP_EE4C0_4", + "DSP_IMUX4_3", + "DSP_1_BCOUT15", + "DSP_1_A8", + "DSP_ACOUT7", + "DSP_SE2A3_4", + "DSP_IMUX29_1", + "DSP_1_PCIN10", + "DSP_0_P2", + "DSP_IMUX46_2", + "DSP_0_ACIN19", + "DSP_IMUX17_2", + "DSP_0_C13", + "DSP_BYP4_3", + "DSP_NW4A0_0", + "DSP_SW4A3_2", + "DSP_1_CEA2", + "DSP_LH4_3", + "DSP_IMUX14_4", + "DSP_LH6_2", + "DSP_LOGIC_OUTS_B5_4", + "DSP_1_PCOUT47", + "DSP_FAN4_4", + "DSP_0_BCOUT7", + "DSP_BYP3_4", + "DSP_LOGIC_OUTS_B20_1", + "DSP_WW2END3_3", + "DSP_IMUX17_1", + "DSP_BLOCK_OUTS_B3_4", + "DSP_WR1END0_2", + "DSP_WW4END3_3", + "DSP_NW4A3_3", + "DSP_CTRL0_4", + "DSP_FAN6_1", + "DSP_1_ACOUT21", + "DSP_LOGIC_OUTS_B5_2", + "DSP_0_ACOUT10", + "DSP_LH7_0", + "DSP_1_P14", + "DSP_FAN1_1", + "DSP_SW4A0_3", + "DSP_1_OPMODE2", + "DSP_BYP4_0", + "DSP_1_P20", + "DSP_IMUX10_0", + "DSP_WW4END3_4", + "DSP_IMUX43_2", + "DSP_0_C10", + "DSP_EL1BEG1_0", + "DSP_FAN3_4", + "DSP_1_PCOUT23", + "DSP_1_PCOUT4", + "DSP_WL1END0_0", + "DSP_1_PCIN30", + "DSP_0_BCOUT0", + "DSP_IMUX22_4", + "DSP_NE4C3_1", + "DSP_0_A5", + "DSP_WR1END0_3", + "DSP_1_BCIN9", + "DSP_PCOUT3", + "DSP_0_PCIN25", + "DSP_SW2A1_2", + "DSP_WW4END2_2", + "DSP_PCOUT47", + "DSP_0_P47", + "DSP_1_BCOUT17", + "DSP_EL1BEG0_3", + "DSP_WW2A2_0", + "DSP_1_BCOUT4", + "DSP_SE4BEG3_3", + "DSP_IMUX44_0", + "DSP_WW4A2_1", + "DSP_EE4BEG2_0", + "DSP_WR1END2_2", + "DSP_BYP6_0", + "DSP_1_A4", + "DSP_1_P27", + "DSP_0_P26", + "DSP_LOGIC_OUTS_B6_3", + "DSP_IMUX42_4", + "DSP_NW2A1_4", + "DSP_IMUX29_4", + "DSP_1_B10", + "DSP_EE4B3_2", + "DSP_NE4C3_0", + "DSP_WW2END2_4", + "DSP_0_PCIN36", + "DSP_1_PCIN9", + "DSP_1_C26", + "DSP_EE4BEG3_4", + "DSP_EL1BEG0_1", + "DSP_LOGIC_OUTS_B11_4", + "DSP_BYP6_2", + "DSP_PCOUT12", + "DSP_0_PCOUT9", + "DSP_0_A25", + "DSP_EE4C1_4", + "DSP_1_BCOUT0", + "DSP_0_PCOUT2", + "DSP_0_ACIN13", + "DSP_LOGIC_OUTS_B19_4", + "DSP_PCOUT40", + "DSP_SW4A2_3", + "DSP_1_CARRYOUT3", + "DSP_1_ALUMODE0", + "DSP_0_PCIN26", + "DSP_1_ACIN0", + "DSP_SE2A1_3", + "DSP_1_OPMODE0", + "DSP_ER1BEG2_4", + "DSP_1_PCIN14", + "DSP_IMUX42_1", + "DSP_IMUX3_1", + "DSP_LOGIC_OUTS_B12_3", + "DSP_SW4END2_2", + "DSP_IMUX45_0", + "DSP_BLOCK_OUTS_B1_2", + "DSP_1_PCOUT7", + "DSP_1_PCOUT34", + "DSP_0_ACIN28", + "DSP_WW4END0_1", + "DSP_0_PCIN28", + "DSP_BLOCK_OUTS_B3_1", + "DSP_ACOUT6", + "DSP_SE4C0_2", + "DSP_0_A23", + "DSP_1_C36", + "DSP_1_P16", + "DSP_1_CEB2", + "DSP_EE4A2_4", + "DSP_EE4A1_2", + "DSP_WW4C0_0", + "DSP_0_ACIN21", + "DSP_WW4END1_2", + "DSP_1_PCIN47", + "DSP_0_D24", + "DSP_CLK1_0", + "DSP_EE4BEG3_0", + "DSP_1_C19", + "DSP_IMUX14_3", + "DSP_1_CEC", + "DSP_SE4BEG3_0", + "DSP_1_C8", + "DSP_1_ACIN16", + "DSP_1_ACOUT23", + "DSP_WW2A2_1", + "DSP_0_PCOUT38", + "DSP_IMUX35_1", + "DSP_LH6_3", + "DSP_0_P40", + "DSP_0_ACIN6", + "DSP_1_ACOUT0", + "DSP_SW4END1_1", + "DSP_LH12_2", + "DSP_0_PCOUT13", + "DSP_0_PCOUT8", + "DSP_1_C40", + "DSP_FAN5_4", + "DSP_WW4B1_4", + "DSP_IMUX22_0", + "DSP_IMUX3_3", + "DSP_1_BCOUT1", + "DSP_1_PCOUT32", + "DSP_BYP3_1", + "DSP_NW4A1_3", + "DSP_IMUX22_3", + "DSP_SW4A2_2", + "DSP_ACOUT22", + "DSP_IMUX33_3", + "DSP_SE2A1_2", + "DSP_LOGIC_OUTS_B3_3", + "DSP_0_B3", + "DSP_0_CARRYINSEL0", + "DSP_1_PCIN5", + "DSP_IMUX18_3", + "DSP_1_PCOUT12", + "DSP_1_INMODE1", + "DSP_1_D6", + "DSP_IMUX2_4", + "DSP_0_B7", + "DSP_NW2A3_0", + "DSP_1_PCIN39", + "DSP_1_P29", + "DSP_SW4END3_2", + "DSP_BLOCK_OUTS_B3_3", + "DSP_SW4END3_4", + "DSP_PCOUT11", + "DSP_1_PCIN11", + "DSP_LH8_3", + "DSP_IMUX34_3", + "DSP_0_PCIN10", + "DSP_NE4BEG2_3", + "DSP_0_ACIN16", + "DSP_1_B9", + "DSP_1_C5", + "DSP_PCOUT18", + "DSP_1_C15", + "DSP_LOGIC_OUTS_B7_1", + "DSP_1_ACIN6", + "DSP_1_PCOUT30", + "DSP_IMUX26_4", + "DSP_NW4END1_4", + "DSP_1_ACIN7", + "DSP_EE2A3_1", + "DSP_1_PCIN2", + "DSP_ER1BEG1_1", + "DSP_1_A22", + "DSP_1_A0", + "DSP_1_PCIN45", + "DSP_IMUX37_1", + "DSP_EE4A3_0", + "DSP_WW4A3_4", + "DSP_IMUX30_2", + "DSP_NW2A0_4", + "DSP_PCOUT13", + "DSP_NW4A2_0", + "DSP_0_ACOUT3", + "DSP_IMUX10_1", + "DSP_NW4END2_4", + "DSP_0_PCOUT26", + "DSP_WL1END2_4", + "DSP_EE4C1_1", + "DSP_1_PCOUT36", + "DSP_LOGIC_OUTS_B0_0", + "DSP_SE4BEG2_3", + "DSP_1_PCOUT16", + "DSP_WW4C3_4", + "DSP_WW4END0_2", + "DSP_IMUX34_0", + "DSP_0_ACIN0", + "DSP_ACOUT13", + "DSP_WW4B0_0", + "DSP_WW2A0_0", + "DSP_EL1BEG1_3", + "DSP_0_CARRYOUT3", + "DSP_EE4BEG0_4", + "DSP_IMUX17_0", + "DSP_LOGIC_OUTS_B10_0", + "DSP_SW4END0_4", + "DSP_1_PCIN16", + "DSP_1_P21", + "DSP_WW4END1_0", + "DSP_1_D22", + "DSP_BYP1_0", + "DSP_SW4A0_2", + "DSP_BLOCK_OUTS_B3_2", + "DSP_0_BCIN15", + "DSP_1_C18", + "DSP_SW2A2_1", + "DSP_LOGIC_OUTS_B23_0", + "DSP_EE4B3_4", + "DSP_NW4END2_0", + "DSP_LOGIC_OUTS_B15_0", + "DSP_1_A15", + "DSP_1_ACOUT14", + "DSP_IMUX39_3", + "DSP_IMUX36_1", + "DSP_NW2A2_3", + "DSP_0_A28", + "DSP_BYP7_3", + "DSP_LOGIC_OUTS_B22_3", + "DSP_0_A17", + "DSP_IMUX38_4", + "DSP_LOGIC_OUTS_B14_3", + "DSP_0_ALUMODE3", + "DSP_IMUX20_1", + "DSP_1_CARRYCASCIN", + "DSP_WR1END3_0", + "DSP_NW4END0_4", + "DSP_PCOUT19", + "DSP_1_D11", + "DSP_SE4C0_1", + "DSP_SW2A3_2", + "DSP_1_P13", + "DSP_BYP6_3", + "DSP_SW4A0_1", + "DSP_LOGIC_OUTS_B3_0", + "DSP_BCOUT7", + "DSP_IMUX9_2", + "DSP_LOGIC_OUTS_B19_0", + "DSP_SE2A3_1", + "DSP_WW4C2_1", + "DSP_ER1BEG0_3", + "DSP_BLOCK_OUTS_B2_4", + "DSP_LOGIC_OUTS_B20_2", + "DSP_IMUX47_1", + "DSP_NW4END3_0", + "DSP_1_ACIN28", + "DSP_SW4A3_0", + "DSP_IMUX47_2", + "DSP_SE4BEG1_2", + "DSP_NE4BEG3_1", + "DSP_1_PCIN13", + "DSP_0_PCOUT37", + "DSP_0_ACIN23", + "DSP_0_C17", + "DSP_LOGIC_OUTS_B14_0", + "DSP_SE2A0_3", + "DSP_IMUX4_2", + "DSP_NW4A2_3", + "DSP_NE2A2_4", + "DSP_0_C31", + "DSP_0_BCIN0", + "DSP_SW2A1_4", + "DSP_WL1END2_2", + "DSP_1_B11", + "DSP_1_C28", + "DSP_0_OPMODE3", + "DSP_1_ACIN13", + "DSP_LH1_2", + "DSP_LH6_1", + "DSP_0_RSTALUMODE", + "DSP_1_A13", + "DSP_1_PCOUT0", + "DSP_SE2A3_2", + "DSP_BLOCK_OUTS_B1_3", + "DSP_1_OPMODE1", + "DSP_0_INMODE4", + "DSP_NW4A0_1", + "DSP_EL1BEG2_1", + "DSP_0_D8", + "DSP_LOGIC_OUTS_B15_4", + "DSP_0_A21", + "DSP_LH11_2", + "DSP_WW4A1_3", + "DSP_NE4C1_3", + "DSP_0_A2", + "DSP_IMUX42_0", + "DSP_IMUX5_1", + "DSP_IMUX0_1", + "DSP_NE4BEG2_1", + "DSP_0_P43", + "DSP_1_BCIN0", + "DSP_NW2A2_2", + "DSP_LOGIC_OUTS_B9_4", + "DSP_0_PCOUT4", + "DSP_NE4C0_2", + "DSP_SE4C2_4", + "DSP_0_CED", + "DSP_NE2A1_2", + "DSP_0_PCIN17", + "DSP_0_PCIN19", + "DSP_IMUX31_1", + "DSP_0_ACIN8", + "DSP_1_PCIN37", + "DSP_1_ACOUT16", + "DSP_0_PCIN8", + "DSP_1_A1", + "DSP_1_PCIN34", + "DSP_EE4A3_3", + "DSP_LOGIC_OUTS_B23_2", + "DSP_IMUX1_4", + "DSP_0_BCIN1", + "DSP_NE2A1_0", + "DSP_WW4C1_0", + "DSP_0_CECTRL", + "DSP_CLK1_2", + "DSP_FAN5_1", + "DSP_1_PCOUT33", + "DSP_LOGIC_OUTS_B8_3", + "DSP_0_P14", + "DSP_1_PCOUT24", + "DSP_SE4BEG1_0", + "DSP_SW2A3_0", + "DSP_LOGIC_OUTS_B0_2", + "DSP_NW4A0_4", + "DSP_BYP4_2", + "DSP_1_A19", + "DSP_1_PCIN33", + "DSP_LOGIC_OUTS_B17_4", + "DSP_SE4C2_2", + "DSP_1_A16", + "DSP_IMUX24_4", + "DSP_PCOUT2", + "DSP_LOGIC_OUTS_B12_4", + "DSP_PCOUT46", + "DSP_LH5_1", + "DSP_WW2END2_2", + "DSP_SE2A3_0", + "DSP_IMUX25_1", + "DSP_0_D6", + "DSP_1_PCOUT11", + "DSP_BCOUT14", + "DSP_LOGIC_OUTS_B10_1", + "DSP_1_ACOUT18", + "DSP_FAN1_2", + "DSP_SW2A1_0", + "DSP_SE4C3_2", + "DSP_0_A22", + "DSP_1_P47", + "DSP_EE2BEG2_2", + "DSP_0_C40", + "DSP_WW4B2_2", + "DSP_IMUX7_4", + "DSP_1_CARRYIN", + "DSP_1_C22", + "DSP_SW4END2_0", + "DSP_IMUX37_4", + "DSP_WW2A3_0", + "DSP_0_C30", + "DSP_LOGIC_OUTS_B2_1", + "DSP_LOGIC_OUTS_B19_1", + "DSP_0_PCOUT32", + "DSP_1_C46", + "DSP_LOGIC_OUTS_B6_2", + "DSP_1_PATTERNBDETECT", + "DSP_WW4B0_1", + "DSP_0_OPMODE6", + "DSP_WW2A0_3", + "DSP_1_PCOUT5", + "DSP_IMUX31_4", + "DSP_1_PCOUT41", + "DSP_0_RSTINMODE", + "DSP_ACOUT27", + "DSP_PCOUT36", + "DSP_LOGIC_OUTS_B4_0", + "DSP_0_ACOUT23", + "DSP_NW4END1_3", + "DSP_LOGIC_OUTS_B19_3", + "DSP_WW4END2_3", + "DSP_0_P18", + "DSP_1_PCOUT17", + "DSP_0_BCIN11", + "DSP_MONITOR_N_0", + "DSP_0_BCOUT13", + "DSP_LOGIC_OUTS_B17_1", + "DSP_0_ACIN17", + "DSP_IMUX30_1", + "DSP_0_ACIN12", + "DSP_0_PCIN21", + "DSP_SW4A0_0", + "DSP_LH11_3", + "DSP_1_PCOUT37", + "DSP_LOGIC_OUTS_B16_0", + "DSP_1_B6", + "DSP_IMUX14_0", + "DSP_EE4B2_1", + "DSP_IMUX24_2", + "DSP_1_CARRYCASCOUT", + "DSP_LH5_2", + "DSP_IMUX39_1", + "DSP_SW4A3_4", + "DSP_BYP2_2", + "DSP_LH9_4", + "DSP_1_P11", + "DSP_0_C15", + "DSP_LH6_4", + "DSP_1_CEAD", + "DSP_IMUX11_2", + "DSP_0_P12", + "DSP_1_B2", + "DSP_FAN1_0", + "DSP_0_PCIN42", + "DSP_EE4B2_4", + "DSP_0_INMODE2", + "DSP_1_ACIN8", + "DSP_IMUX43_0", + "DSP_1_C27", + "DSP_LOGIC_OUTS_B3_4", + "DSP_FAN5_2", + "DSP_0_PCIN41", + "DSP_IMUX18_4", + "DSP_WW4C3_1", + "DSP_0_C45", + "DSP_WW4C2_0", + "DSP_LOGIC_OUTS_B9_0", + "DSP_1_C32", + "DSP_SE2A2_3", + "DSP_NE4C3_2", + "DSP_0_P25", + "DSP_WR1END3_1", + "DSP_IMUX19_1", + "DSP_WW4END3_0", + "DSP_EE4B2_3", + "DSP_WL1END3_3", + "DSP_1_P15", + "DSP_0_ACOUT20", + "DSP_EE4A0_0", + "DSP_LOGIC_OUTS_B6_0", + "DSP_ER1BEG1_3", + "DSP_1_PCIN23", + "DSP_0_ACOUT17", + "DSP_EE4B0_1", + "DSP_BYP2_0", + "DSP_1_P42", + "DSP_SE4C0_4", + "DSP_MONITOR_N_4", + "DSP_ACOUT0", + "DSP_1_D14", + "DSP_1_CARRYINSEL0", + "DSP_0_ACIN11", + "DSP_PCOUT38", + "DSP_0_ACOUT13", + "DSP_IMUX19_0", + "DSP_FAN6_0", + "DSP_0_D3", + "DSP_1_ACIN11", + "DSP_1_P34", + "DSP_SE2A3_3", + "DSP_FAN6_3", + "DSP_NE4C1_2", + "DSP_EE2A0_3", + "DSP_1_ACIN3", + "DSP_ACOUT5", + "DSP_LOGIC_OUTS_B21_1", + "DSP_SE4BEG0_2", + "DSP_SW4A3_1", + "DSP_LOGIC_OUTS_B18_3", + "DSP_0_PCIN9", + "DSP_EE2A2_3", + "DSP_1_ACIN23", + "DSP_0_B10", + "DSP_0_PCIN14", + "DSP_IMUX35_4", + "DSP_0_ACOUT29", + "DSP_PCOUT45", + "DSP_1_OPMODE6", + "DSP_WL1END3_2", + "DSP_SE2A2_4", + "DSP_0_ACOUT8", + "DSP_0_ACOUT9", + "DSP_PCOUT28", + "DSP_0_RSTP", + "DSP_WW2END1_1", + "DSP_BCOUT15", + "DSP_0_ACIN10", + "DSP_1_ACIN4", + "DSP_SW4END0_1", + "DSP_EE4A0_4", + "DSP_PCOUT30", + "DSP_0_B1", + "DSP_0_PCIN2", + "DSP_WL1END3_4", + "DSP_SE4BEG1_3", + "DSP_ER1BEG2_2", + "DSP_LOGIC_OUTS_B20_4", + "DSP_IMUX15_1", + "DSP_IMUX29_2", + "DSP_1_C4", + "DSP_0_RSTD", + "DSP_LOGIC_OUTS_B17_2", + "DSP_WW2A1_4", + "DSP_0_C32", + "DSP_EE2A3_0", + "DSP_0_A24", + "DSP_1_P28", + "DSP_PCOUT15", + "DSP_1_ACIN20", + "DSP_0_P27", + "DSP_0_PCOUT19", + "DSP_NE4C0_4", + "DSP_0_PCIN40", + "DSP_WL1END1_1", + "DSP_1_A12", + "DSP_0_C0", + "DSP_0_D23", + "DSP_NE4BEG0_0", + "DSP_0_PCIN15", + "DSP_LOGIC_OUTS_B0_1", + "DSP_1_PCIN38", + "DSP_IMUX32_3", + "DSP_ACOUT16", + "DSP_IMUX33_4", + "DSP_0_PCIN33", + "DSP_IMUX23_3", + "DSP_0_C20", + "DSP_1_C39", + "DSP_EE4B1_3", + "DSP_EE4C3_1", + "DSP_PCOUT20", + "DSP_IMUX2_3", + "DSP_LOGIC_OUTS_B16_2", + "DSP_LOGIC_OUTS_B8_1", + "DSP_0_A7", + "DSP_1_RSTA", + "DSP_0_P39", + "DSP_1_ACOUT17", + "DSP_PCOUT29", + "DSP_PCOUT34", + "DSP_FAN1_4", + "DSP_0_P21", + "DSP_0_C23", + "DSP_1_ALUMODE3", + "DSP_0_RSTC", + "DSP_IMUX38_2", + "DSP_IMUX27_1", + "DSP_EE2A2_0", + "DSP_BCOUT16", + "DSP_0_C8", + "DSP_0_PCOUT36", + "DSP_BYP1_3", + "DSP_LOGIC_OUTS_B22_2", + "DSP_NW4A3_1", + "DSP_1_ACOUT7", + "DSP_WR1END3_3", + "DSP_0_PCIN12", + "DSP_LOGIC_OUTS_B12_0", + "DSP_0_ACOUT26", + "DSP_0_OPMODE0", + "DSP_MONITOR_N_1", + "DSP_WW4END0_0", + "DSP_WW4C2_4", + "DSP_MONITOR_P_4", + "DSP_0_C29", + "DSP_1_ACIN15", + "DSP_IMUX44_3", + "DSP_WW4C0_2", + "DSP_1_PCIN19", + "DSP_IMUX25_3", + "DSP_BYP1_1", + "DSP_0_A9", + "DSP_0_ACIN24", + "DSP_IMUX10_4", + "DSP_LH4_0", + "DSP_0_D13", + "DSP_0_PCIN6", + "DSP_IMUX23_4", + "DSP_WW2A1_0", + "DSP_NE4BEG2_4", + "DSP_NE2A0_4", + "DSP_1_D23", + "DSP_SW4A2_4", + "DSP_1_ACOUT27", + "DSP_0_ACIN7", + "DSP_EL1BEG3_0", + "DSP_BYP2_3", + "DSP_CTRL1_2", + "DSP_EE4B0_2", + "DSP_ER1BEG3_1", + "DSP_0_CEAD", + "DSP_IMUX20_3", + "DSP_IMUX28_1", + "DSP_0_CEALUMODE", + "DSP_WW4A2_0", + "DSP_IMUX20_2", + "DSP_1_PCIN6", + "DSP_ACOUT1", + "DSP_SW2A3_1", + "DSP_0_P32", + "DSP_0_BCIN13", + "DSP_0_D2", + "DSP_NW2A0_2", + "DSP_EE2BEG2_1", + "DSP_0_ACOUT12", + "DSP_IMUX14_2", + "DSP_1_CARRYOUT0", + "DSP_WW4B0_3", + "DSP_IMUX23_1", + "DSP_IMUX5_4", + "DSP_1_P12", + "DSP_IMUX6_2", + "DSP_WL1END0_4", + "DSP_FAN2_1", + "DSP_WR1END0_0", + "DSP_IMUX43_4", + "DSP_LOGIC_OUTS_B21_0", + "DSP_IMUX27_4", + "DSP_IMUX13_4", + "DSP_EE4B1_0", + "DSP_0_PCIN22", + "DSP_NE4BEG2_2", + "DSP_IMUX38_3", + "DSP_NE2A1_3", + "DSP_0_ACOUT14", + "DSP_1_PCOUT39", + "DSP_0_A27", + "DSP_BYP3_0", + "DSP_NW4A3_4", + "DSP_EE4BEG2_2", + "DSP_1_CEALUMODE", + "DSP_0_PCIN13", + "DSP_0_PCOUT10", + "DSP_1_P26", + "DSP_ACOUT28", + "DSP_1_C37", + "DSP_IMUX41_1", + "DSP_PCOUT27", + "DSP_1_PCOUT6", + "DSP_0_ACOUT1", + "DSP_0_PCIN43", + "DSP_EE4BEG3_3", + "DSP_0_C46", + "DSP_1_C30", + "DSP_EE2BEG3_1", + "DSP_ACOUT10", + "DSP_LOGIC_OUTS_B13_2", + "DSP_0_RSTALLCARRYIN", + "DSP_WW4END2_0", + "DSP_0_PCOUT22", + "DSP_ER1BEG1_2", + "DSP_1_INMODE4", + "DSP_1_PCIN22", + "DSP_IMUX24_0", + "DSP_IMUX37_3", + "DSP_0_P33", + "DSP_1_D13", + "DSP_LOGIC_OUTS_B2_2", + "DSP_SE4BEG0_3", + "DSP_1_A27", + "DSP_WW2A3_2", + "DSP_NW4END3_3", + "DSP_0_PCOUT33", + "DSP_NE4BEG1_3", + "DSP_1_D15", + "DSP_IMUX11_3", + "DSP_1_P1", + "DSP_0_P34", + "DSP_1_A3", + "DSP_EE2A2_4", + "DSP_LH2_3", + "DSP_1_PCIN18", + "DSP_BCOUT1", + "DSP_PCOUT26", + "DSP_0_C37", + "DSP_0_PCOUT20", + "DSP_NE2A1_1", + "DSP_1_D12", + "DSP_EE4C1_2", + "DSP_1_B5", + "DSP_SW2A3_3", + "DSP_1_PCIN46", + "DSP_BCOUT0", + "DSP_1_BCOUT11", + "DSP_IMUX33_2", + "DSP_SE4BEG3_1", + "DSP_NE4BEG0_4", + "DSP_EE4C2_2", + "DSP_LOGIC_OUTS_B14_1", + "DSP_LOGIC_OUTS_B17_3", + "DSP_WW4END0_3", + "DSP_NE4C2_2", + "DSP_0_D4", + "DSP_ACOUT2", + "DSP_LH12_3", + "DSP_0_OPMODE1", + "DSP_EE2A0_1", + "DSP_WW2A0_1", + "DSP_NW4A2_2", + "DSP_0_PCIN0", + "DSP_GND_R", + "DSP_NW4END0_0", + "DSP_1_C23", + "DSP_IMUX7_3", + "DSP_IMUX0_0", + "DSP_SW4END1_2", + "DSP_SW4END0_0", + "DSP_0_PCIN45", + "DSP_WW2A2_3", + "DSP_LH1_3", + "DSP_0_MULTSIGNIN", + "DSP_EE4B1_4", + "DSP_WW2A3_1", + "DSP_1_C34", + "DSP_0_BCIN6", + "DSP_LH7_3", + "DSP_LH3_2", + "DSP_BYP2_4", + "DSP_EE4A0_2", + "DSP_IMUX26_3", + "DSP_IMUX26_1", + "DSP_EE2BEG1_4", + "DSP_1_A9", + "DSP_IMUX28_2", + "DSP_0_D5", + "DSP_LOGIC_OUTS_B14_4", + "DSP_1_BCOUT16", + "DSP_LH2_4", + "DSP_0_PCOUT42", + "DSP_0_B13", + "DSP_CTRL0_2", + "DSP_1_ACOUT13", + "DSP_0_C5", + "DSP_WW4A0_2", + "DSP_LH3_4", + "DSP_0_BCOUT17", + "DSP_0_ACIN14", + "DSP_0_P13", + "DSP_0_A3", + "DSP_ER1BEG0_0", + "DSP_WW2A0_2", + "DSP_LH12_1", + "DSP_0_ACIN3", + "DSP_LOGIC_OUTS_B19_2", + "DSP_BYP5_1", + "DSP_SE4C1_4", + "DSP_PCOUT33", + "DSP_0_C42", + "DSP_IMUX35_2", + "DSP_IMUX27_3", + "DSP_0_B6", + "DSP_0_C3", + "DSP_NE4C1_4", + "DSP_IMUX40_3", + "DSP_SE2A1_0", + "DSP_BCOUT2", + "DSP_0_A20", + "DSP_IMUX41_3", + "DSP_EE4BEG0_1", + "DSP_IMUX37_0", + "DSP_EE4B2_2", + "DSP_1_BCOUT9", + "DSP_0_P35", + "DSP_1_BCIN2", + "DSP_1_BCOUT14", + "DSP_1_A17", + "DSP_PCOUT32", + "DSP_WW4A1_4", + "DSP_0_ACIN5", + "DSP_IMUX24_3", + "DSP_0_BCOUT11", + "DSP_1_P9", + "DSP_LOGIC_OUTS_B13_0", + "DSP_0_P7", + "DSP_1_RSTCTRL", + "DSP_IMUX2_2", + "DSP_1_ACOUT19", + "DSP_1_P43", + "DSP_EE4BEG1_3", + "DSP_WW4END1_1", + "DSP_NW4END1_1", + "DSP_WL1END3_0", + "DSP_WW2A3_4", + "DSP_ER1BEG0_2", + "DSP_1_PCOUT35", + "DSP_EE2BEG0_0", + "DSP_EE4C3_4", + "DSP_0_ACOUT27", + "DSP_LOGIC_OUTS_B2_4", + "DSP_0_CARRYIN", + "DSP_NE2A3_0", + "DSP_IMUX23_0", + "DSP_BLOCK_OUTS_B0_2", + "DSP_1_C2", + "DSP_WR1END2_4", + "DSP_ACOUT11", + "DSP_ACOUT15", + "DSP_ACOUT18", + "DSP_0_C6", + "DSP_WW4B0_2", + "DSP_NE4C1_0", + "DSP_LH7_2", + "DSP_1_D2", + "DSP_0_PCOUT31", + "DSP_0_ACOUT16", + "DSP_IMUX7_0", + "DSP_0_MULTSIGNOUT", + "DSP_1_D24", + "DSP_IMUX44_2", + "DSP_0_ACOUT4", + "DSP_SW4A0_4", + "DSP_BLOCK_OUTS_B0_3", + "DSP_0_ACOUT6", + "DSP_1_RSTB", + "DSP_1_C17", + "DSP_0_BCOUT2", + "DSP_LOGIC_OUTS_B1_3", + "DSP_0_P0", + "DSP_0_C39", + "DSP_0_P19", + "DSP_0_B11", + "DSP_MONITOR_N_2", + "DSP_1_PCIN24", + "DSP_WW4END0_4", + "DSP_IMUX8_3", + "DSP_EL1BEG1_4", + "DSP_FAN4_0", + "DSP_0_C21", + "DSP_SE4BEG2_4", + "DSP_1_PCOUT26", + "DSP_0_PCOUT1", + "DSP_IMUX30_0", + "DSP_0_CARRYCASCOUT", + "DSP_FAN4_3", + "DSP_0_PCIN37", + "DSP_1_P39", + "DSP_FAN0_4", + "DSP_IMUX44_1", + "DSP_BLOCK_OUTS_B2_1", + "DSP_LOGIC_OUTS_B2_3", + "DSP_CLK0_2", + "DSP_IMUX27_0", + "DSP_EE4C0_1", + "DSP_WL1END2_1", + "DSP_1_BCOUT5", + "DSP_WW2END1_0", + "DSP_EE2BEG0_4", + "DSP_1_ACOUT5", + "DSP_LH2_1", + "DSP_0_ACOUT7", + "DSP_0_CARRYOUT1", + "DSP_1_CARRYOUT2", + "DSP_SW4END1_3", + "DSP_WW4C1_3", + "DSP_IMUX7_1", + "DSP_PCOUT35", + "DSP_1_A7", + "DSP_EE4C2_4", + "DSP_0_BCOUT8", + "DSP_1_C25", + "DSP_LH4_2", + "DSP_0_PCOUT0", + "DSP_1_CEM", + "DSP_ER1BEG2_0", + "DSP_0_P23", + "DSP_0_CEA1", + "DSP_0_D10", + "DSP_EE4C3_2", + "DSP_1_P19", + "DSP_0_PCOUT47", + "DSP_LOGIC_OUTS_B11_1", + "DSP_0_ACOUT15", + "DSP_IMUX36_3", + "DSP_EE2A3_2", + "DSP_0_CEINMODE", + "DSP_1_BCIN8", + "DSP_0_BCIN12", + "DSP_IMUX0_3", + "DSP_0_CECARRYIN", + "DSP_1_C44", + "DSP_PCOUT10", + "DSP_LOGIC_OUTS_B0_4", + "DSP_NW2A3_2", + "DSP_0_RSTCTRL", + "DSP_1_CEP", + "DSP_SW4A1_0", + "DSP_1_PCOUT9", + "DSP_BYP0_3", + "DSP_EE2BEG1_1", + "DSP_NW4A1_2", + "DSP_0_PCIN23", + "DSP_IMUX31_3", + "DSP_0_PCIN20", + "DSP_1_ACIN25", + "DSP_WW4B3_0", + "DSP_EE4A2_0", + "DSP_LOGIC_OUTS_B8_4", + "DSP_0_PATTERNBDETECT", + "DSP_WW4C2_2", + "DSP_1_INMODE3", + "DSP_IMUX26_2", + "DSP_0_P37", + "DSP_IMUX21_0", + "DSP_LH8_0", + "DSP_IMUX45_2", + "DSP_SW2A1_1", + "DSP_LH7_1", + "DSP_WL1END3_1", + "DSP_0_PCIN34", + "DSP_SE4C0_3", + "DSP_0_B16", + "DSP_EE4A2_2", + "DSP_0_PCIN31", + "DSP_FAN7_2", + "DSP_0_B2", + "DSP_1_RSTALUMODE", + "DSP_1_B0", + "DSP_1_C1", + "DSP_1_BCIN3", + "DSP_1_C10", + "DSP_0_C28", + "DSP_1_RSTALLCARRYIN", + "DSP_IMUX31_0", + "DSP_1_UNDERFLOW", + "DSP_BYP1_2", + "DSP_WW4C0_1", + "DSP_0_CEB2", + "DSP_SE4C2_1", + "DSP_0_PCOUT27", + "DSP_1_ACOUT2", + "DSP_ACOUT17", + "DSP_1_MULTSIGNIN", + "DSP_1_C9", + "DSP_1_B7", + "DSP_1_BCIN7", + "DSP_1_PCOUT1", + "DSP_EE4C0_0", + "DSP_ER1BEG3_2", + "DSP_IMUX21_4", + "DSP_IMUX16_3", + "DSP_1_ACOUT11", + "DSP_SE4BEG1_4", + "DSP_LOGIC_OUTS_B22_0", + "DSP_ACOUT20", + "DSP_ER1BEG1_4", + "DSP_EE4A0_1", + "DSP_1_B8", + "DSP_LOGIC_OUTS_B7_2", + "DSP_0_ACOUT11", + "DSP_0_B15", + "DSP_IMUX16_4", + "DSP_BCOUT10", + "DSP_WW4B1_0", + "DSP_IMUX9_4", + "DSP_WW4A2_4", + "DSP_IMUX40_2", + "DSP_IMUX32_4", + "DSP_WL1END0_3", + "DSP_0_PCOUT29" + ], + "pips": { + "DSP_R.DSP_CTRL1_0->DSP_0_RSTA": { + "src_wire": "DSP_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTA", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT18->DSP_PCOUT18": { + "src_wire": "DSP_1_PCOUT18", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX12_3->DSP_1_C34": { + "src_wire": "DSP_IMUX12_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C34", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX18_1->DSP_0_B5": { + "src_wire": "DSP_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT23->DSP_PCOUT23": { + "src_wire": "DSP_1_PCOUT23", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP7_2->DSP_0_D8": { + "src_wire": "DSP_BYP7_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P26->DSP_LOGIC_OUTS_B2_1": { + "src_wire": "DSP_1_P26", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_CTRL0_2->DSP_0_RSTB": { + "src_wire": "DSP_CTRL0_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTB", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P36->DSP_LOGIC_OUTS_B17_4": { + "src_wire": "DSP_0_P36", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT18->DSP_1_PCIN18": { + "src_wire": "DSP_0_PCOUT18", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP5_4->DSP_0_D17": { + "src_wire": "DSP_BYP5_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_D17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_INMODE1": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX34_0->DSP_0_B1": { + "src_wire": "DSP_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_B1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT12->DSP_BCOUT12": { + "src_wire": "DSP_1_BCOUT12", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX25_4->DSP_1_C47": { + "src_wire": "DSP_IMUX25_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C47", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX8_4->DSP_1_OPMODE1": { + "src_wire": "DSP_IMUX8_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT13->DSP_1_BCIN13": { + "src_wire": "DSP_0_BCOUT13", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX28_4->DSP_1_CARRYINSEL1": { + "src_wire": "DSP_IMUX28_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX22_1->DSP_0_C24": { + "src_wire": "DSP_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX37_0->DSP_0_C2": { + "src_wire": "DSP_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT11->DSP_1_BCIN11": { + "src_wire": "DSP_0_BCOUT11", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX20_3->DSP_0_C34": { + "src_wire": "DSP_IMUX20_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C34", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX10_1->DSP_1_B5": { + "src_wire": "DSP_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX11_0->DSP_1_A1": { + "src_wire": "DSP_IMUX11_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_CEINMODE": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT23->DSP_ACOUT23": { + "src_wire": "DSP_1_ACOUT23", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT11->DSP_1_ACIN11": { + "src_wire": "DSP_0_ACOUT11", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P15->DSP_LOGIC_OUTS_B4_3": { + "src_wire": "DSP_1_P15", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT12->DSP_PCOUT12": { + "src_wire": "DSP_1_PCOUT12", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP5_2->DSP_0_D9": { + "src_wire": "DSP_BYP5_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_D9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX45_4->DSP_1_A16": { + "src_wire": "DSP_IMUX45_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_A16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_INMODE0": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT9->DSP_1_PCIN9": { + "src_wire": "DSP_0_PCOUT9", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_OPMODE6": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX11_4->DSP_1_C46": { + "src_wire": "DSP_IMUX11_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C46", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_OPMODE6": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX24_4->DSP_1_C37": { + "src_wire": "DSP_IMUX24_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C37", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_CARRYOUT0->DSP_LOGIC_OUTS_B12_1": { + "src_wire": "DSP_0_CARRYOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B12_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT44->DSP_1_PCIN44": { + "src_wire": "DSP_0_PCOUT44", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN44", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT15->DSP_1_BCIN15": { + "src_wire": "DSP_0_BCOUT15", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT46->DSP_PCOUT46": { + "src_wire": "DSP_1_PCOUT46", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT46", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN1_1->DSP_1_D21": { + "src_wire": "DSP_FAN1_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX23_1->DSP_0_A4": { + "src_wire": "DSP_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX0_1->DSP_0_CEA2": { + "src_wire": "DSP_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEA2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D18": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT42->DSP_1_PCIN42": { + "src_wire": "DSP_0_PCOUT42", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN42", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX16_2->DSP_0_B11": { + "src_wire": "DSP_IMUX16_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_B11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_CEINMODE": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX17_0->DSP_0_A3": { + "src_wire": "DSP_IMUX17_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT10->DSP_PCOUT10": { + "src_wire": "DSP_1_PCOUT10", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT9->DSP_ACOUT9": { + "src_wire": "DSP_1_ACOUT9", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN3_4->DSP_1_D16": { + "src_wire": "DSP_FAN3_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_D16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT15->DSP_1_ACIN15": { + "src_wire": "DSP_0_ACOUT15", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_INMODE4": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_INMODE2": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D18": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D4": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX0_0->DSP_1_B3": { + "src_wire": "DSP_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_B3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX22_0->DSP_0_B0": { + "src_wire": "DSP_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_B0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_CED": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_CED", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX38_1->DSP_0_B4": { + "src_wire": "DSP_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT34->DSP_1_PCIN34": { + "src_wire": "DSP_0_PCOUT34", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN34", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_INMODE3": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX14_0->DSP_1_B0": { + "src_wire": "DSP_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_B0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D0": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D12": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D22": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT28->DSP_1_ACIN28": { + "src_wire": "DSP_0_ACOUT28", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN6_4->DSP_1_D17": { + "src_wire": "DSP_FAN6_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_D17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX23_4->DSP_1_RSTINMODE": { + "src_wire": "DSP_IMUX23_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P18->DSP_LOGIC_OUTS_B16_4": { + "src_wire": "DSP_0_P18", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P40->DSP_LOGIC_OUTS_B15_0": { + "src_wire": "DSP_1_P40", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT11->DSP_BCOUT11": { + "src_wire": "DSP_1_BCOUT11", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT21->DSP_1_ACIN21": { + "src_wire": "DSP_0_ACOUT21", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D0": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT16->DSP_1_PCIN16": { + "src_wire": "DSP_0_PCOUT16", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX13_2->DSP_1_A10": { + "src_wire": "DSP_IMUX13_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_A10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT17->DSP_1_PCIN17": { + "src_wire": "DSP_0_PCOUT17", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P9->DSP_LOGIC_OUTS_B23_2": { + "src_wire": "DSP_0_P9", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX1_2->DSP_0_CEM": { + "src_wire": "DSP_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEM", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX35_0->DSP_0_C40": { + "src_wire": "DSP_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C40", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN3_1->DSP_1_D4": { + "src_wire": "DSP_FAN3_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT36->DSP_1_PCIN36": { + "src_wire": "DSP_0_PCOUT36", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN36", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT43->DSP_1_PCIN43": { + "src_wire": "DSP_0_PCOUT43", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN43", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX46_0->DSP_0_A22": { + "src_wire": "DSP_IMUX46_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX25_1->DSP_1_C7": { + "src_wire": "DSP_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT20->DSP_ACOUT20": { + "src_wire": "DSP_1_ACOUT20", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP7_1->DSP_0_D4": { + "src_wire": "DSP_BYP7_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D13": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT5->DSP_PCOUT5": { + "src_wire": "DSP_1_PCOUT5", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX21_3->DSP_0_ALUMODE0": { + "src_wire": "DSP_IMUX21_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX4_3->DSP_1_A15": { + "src_wire": "DSP_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_A15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_RSTD": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT38->DSP_PCOUT38": { + "src_wire": "DSP_1_PCOUT38", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT38", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX19_4->DSP_0_C46": { + "src_wire": "DSP_IMUX19_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C46", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP3_4->DSP_0_D18": { + "src_wire": "DSP_BYP3_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_D18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX8_1->DSP_1_B7": { + "src_wire": "DSP_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX36_1->DSP_0_B6": { + "src_wire": "DSP_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX16_1->DSP_0_B7": { + "src_wire": "DSP_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT8->DSP_PCOUT8": { + "src_wire": "DSP_1_PCOUT8", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX0_4->DSP_1_ALUMODE0": { + "src_wire": "DSP_IMUX0_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX40_2->DSP_0_CEC": { + "src_wire": "DSP_IMUX40_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEC", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PATTERNBDETECT->DSP_LOGIC_OUTS_B14_2": { + "src_wire": "DSP_0_PATTERNBDETECT", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX4_0->DSP_1_A23": { + "src_wire": "DSP_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP1_4->DSP_0_D19": { + "src_wire": "DSP_BYP1_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_D19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT2->DSP_1_BCIN2": { + "src_wire": "DSP_0_BCOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P20->DSP_LOGIC_OUTS_B17_0": { + "src_wire": "DSP_0_P20", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT7->DSP_1_ACIN7": { + "src_wire": "DSP_0_ACOUT7", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT10->DSP_1_BCIN10": { + "src_wire": "DSP_0_BCOUT10", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX40_4->DSP_1_ALUMODE1": { + "src_wire": "DSP_IMUX40_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX45_0->DSP_1_A20": { + "src_wire": "DSP_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_INMODE0": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX26_1->DSP_1_C25": { + "src_wire": "DSP_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_CTRL1_2->DSP_1_RSTA": { + "src_wire": "DSP_CTRL1_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTA", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT20->DSP_1_ACIN20": { + "src_wire": "DSP_0_ACOUT20", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P37->DSP_LOGIC_OUTS_B0_4": { + "src_wire": "DSP_1_P37", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT16->DSP_1_BCIN16": { + "src_wire": "DSP_0_BCOUT16", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT16->DSP_PCOUT16": { + "src_wire": "DSP_1_PCOUT16", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX46_3->DSP_0_A14": { + "src_wire": "DSP_IMUX46_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_A14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX35_1->DSP_0_C5": { + "src_wire": "DSP_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT8->DSP_1_ACIN8": { + "src_wire": "DSP_0_ACOUT8", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX16_0->DSP_0_C41": { + "src_wire": "DSP_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C41", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX3_2->DSP_0_C9": { + "src_wire": "DSP_IMUX3_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT3->DSP_ACOUT3": { + "src_wire": "DSP_1_ACOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN2_3->DSP_1_CEINMODE": { + "src_wire": "DSP_FAN2_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX18_3->DSP_0_C33": { + "src_wire": "DSP_IMUX18_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C33", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT12->DSP_1_ACIN12": { + "src_wire": "DSP_0_ACOUT12", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_UNDERFLOW->DSP_LOGIC_OUTS_B9_2": { + "src_wire": "DSP_0_UNDERFLOW", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B9_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT30->DSP_PCOUT30": { + "src_wire": "DSP_1_PCOUT30", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT30", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX2_0->DSP_1_C42": { + "src_wire": "DSP_IMUX2_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C42", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT26->DSP_ACOUT26": { + "src_wire": "DSP_1_ACOUT26", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT11->DSP_1_PCIN11": { + "src_wire": "DSP_0_PCOUT11", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D17": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX17_3->DSP_1_CEA2": { + "src_wire": "DSP_IMUX17_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEA2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX38_0->DSP_0_C20": { + "src_wire": "DSP_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP1_0->DSP_0_D3": { + "src_wire": "DSP_BYP1_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT39->DSP_PCOUT39": { + "src_wire": "DSP_1_PCOUT39", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT39", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P8->DSP_LOGIC_OUTS_B3_2": { + "src_wire": "DSP_1_P8", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_CARRYOUT3->DSP_LOGIC_OUTS_B10_1": { + "src_wire": "DSP_0_CARRYOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_INMODE4": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT2->DSP_PCOUT2": { + "src_wire": "DSP_1_PCOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT5->DSP_1_PCIN5": { + "src_wire": "DSP_0_PCOUT5", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_INMODE0": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_CEINMODE": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT1->DSP_1_PCIN1": { + "src_wire": "DSP_0_PCOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX6_0->DSP_0_A23": { + "src_wire": "DSP_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX5_3->DSP_1_A13": { + "src_wire": "DSP_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_A13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT7->DSP_1_PCIN7": { + "src_wire": "DSP_0_PCOUT7", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_INMODE1": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT8->DSP_BCOUT8": { + "src_wire": "DSP_1_BCOUT8", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D20": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D11": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP2_4->DSP_1_CARRYINSEL2": { + "src_wire": "DSP_BYP2_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_INMODE2": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX13_3->DSP_0_ALUMODE1": { + "src_wire": "DSP_IMUX13_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P42->DSP_LOGIC_OUTS_B9_0": { + "src_wire": "DSP_0_P42", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B9_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_CTRL0_0->DSP_0_RSTP": { + "src_wire": "DSP_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTP", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN4_0->DSP_1_D3": { + "src_wire": "DSP_FAN4_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_D3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT22->DSP_1_PCIN22": { + "src_wire": "DSP_0_PCOUT22", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P44->DSP_LOGIC_OUTS_B12_4": { + "src_wire": "DSP_1_P44", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B12_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX36_3->DSP_1_OPMODE2": { + "src_wire": "DSP_IMUX36_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT9->DSP_1_ACIN9": { + "src_wire": "DSP_0_ACOUT9", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX5_2->DSP_1_A29": { + "src_wire": "DSP_IMUX5_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_A29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX5_4->DSP_1_A17": { + "src_wire": "DSP_IMUX5_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_A17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX15_2->DSP_1_A8": { + "src_wire": "DSP_IMUX15_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_A8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT30->DSP_1_PCIN30": { + "src_wire": "DSP_0_PCOUT30", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN30", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX43_0->DSP_1_C1": { + "src_wire": "DSP_IMUX43_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT12->DSP_1_BCIN12": { + "src_wire": "DSP_0_BCOUT12", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN2_2->DSP_1_INMODE4": { + "src_wire": "DSP_FAN2_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX25_3->DSP_1_C15": { + "src_wire": "DSP_IMUX25_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT21->DSP_1_PCIN21": { + "src_wire": "DSP_0_PCOUT21", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX19_1->DSP_0_A5": { + "src_wire": "DSP_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX36_2->DSP_0_B10": { + "src_wire": "DSP_IMUX36_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_B10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT13->DSP_1_ACIN13": { + "src_wire": "DSP_0_ACOUT13", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D23": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT45->DSP_1_PCIN45": { + "src_wire": "DSP_0_PCOUT45", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN45", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D15": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_CARRYCASCOUT->DSP_CARRYCASCOUT": { + "src_wire": "DSP_1_CARRYCASCOUT", + "is_pseudo": "0", + "dst_wire": "DSP_CARRYCASCOUT", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_CED": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_CED", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT22->DSP_PCOUT22": { + "src_wire": "DSP_1_PCOUT22", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P34->DSP_LOGIC_OUTS_B20_3": { + "src_wire": "DSP_0_P34", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX13_0->DSP_1_A2": { + "src_wire": "DSP_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_OVERFLOW->DSP_LOGIC_OUTS_B10_2": { + "src_wire": "DSP_0_OVERFLOW", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP2_2->DSP_0_CARRYINSEL2": { + "src_wire": "DSP_BYP2_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX4_2->DSP_0_C30": { + "src_wire": "DSP_IMUX4_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C30", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D5": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX41_0->DSP_1_C3": { + "src_wire": "DSP_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P39->DSP_LOGIC_OUTS_B19_4": { + "src_wire": "DSP_0_P39", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT9->DSP_1_BCIN9": { + "src_wire": "DSP_0_BCOUT9", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT46->DSP_1_PCIN46": { + "src_wire": "DSP_0_PCOUT46", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN46", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D19": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX47_3->DSP_0_A12": { + "src_wire": "DSP_IMUX47_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_A12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX21_0->DSP_0_A2": { + "src_wire": "DSP_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX40_1->DSP_0_CEA1": { + "src_wire": "DSP_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEA1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_ALUMODE2": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT10->DSP_BCOUT10": { + "src_wire": "DSP_1_BCOUT10", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_OPMODE6": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D7": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX11_2->DSP_1_A9": { + "src_wire": "DSP_IMUX11_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_A9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_ALUMODE3": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P34->DSP_LOGIC_OUTS_B2_3": { + "src_wire": "DSP_1_P34", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_CEINMODE": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P13->DSP_LOGIC_OUTS_B23_3": { + "src_wire": "DSP_0_P13", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX3_1->DSP_0_RSTALUMODE": { + "src_wire": "DSP_IMUX3_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D9": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX11_1->DSP_1_A5": { + "src_wire": "DSP_IMUX11_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX41_1->DSP_0_CEB1": { + "src_wire": "DSP_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEB1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D16": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_CLK0_1->DSP_0_CLK": { + "src_wire": "DSP_CLK0_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN1_3->DSP_0_INMODE4": { + "src_wire": "DSP_FAN1_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_CEAD": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEAD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P14->DSP_LOGIC_OUTS_B6_3": { + "src_wire": "DSP_1_P14", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P4->DSP_LOGIC_OUTS_B21_1": { + "src_wire": "DSP_0_P4", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P24->DSP_LOGIC_OUTS_B17_1": { + "src_wire": "DSP_0_P24", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT1->DSP_1_BCIN1": { + "src_wire": "DSP_0_BCOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PATTERNBDETECT->DSP_LOGIC_OUTS_B15_2": { + "src_wire": "DSP_1_PATTERNBDETECT", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT18->DSP_1_ACIN18": { + "src_wire": "DSP_0_ACOUT18", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT5->DSP_1_BCIN5": { + "src_wire": "DSP_0_BCOUT5", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT25->DSP_1_ACIN25": { + "src_wire": "DSP_0_ACOUT25", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT15->DSP_ACOUT15": { + "src_wire": "DSP_1_ACOUT15", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT4->DSP_PCOUT4": { + "src_wire": "DSP_1_PCOUT4", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX47_0->DSP_0_A20": { + "src_wire": "DSP_IMUX47_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX42_3->DSP_0_B14": { + "src_wire": "DSP_IMUX42_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_B14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT14->DSP_PCOUT14": { + "src_wire": "DSP_1_PCOUT14", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P35->DSP_LOGIC_OUTS_B0_3": { + "src_wire": "DSP_1_P35", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP1_2->DSP_0_D11": { + "src_wire": "DSP_BYP1_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_D11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D6": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P11->DSP_LOGIC_OUTS_B18_2": { + "src_wire": "DSP_0_P11", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_CEAD": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEAD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT5->DSP_BCOUT5": { + "src_wire": "DSP_1_BCOUT5", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX20_1->DSP_0_C26": { + "src_wire": "DSP_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT2->DSP_ACOUT2": { + "src_wire": "DSP_1_ACOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P7->DSP_LOGIC_OUTS_B4_1": { + "src_wire": "DSP_1_P7", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P38->DSP_LOGIC_OUTS_B20_4": { + "src_wire": "DSP_0_P38", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT20->DSP_PCOUT20": { + "src_wire": "DSP_1_PCOUT20", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT17->DSP_ACOUT17": { + "src_wire": "DSP_1_ACOUT17", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN0_3->DSP_1_CED": { + "src_wire": "DSP_FAN0_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CED", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P32->DSP_LOGIC_OUTS_B17_3": { + "src_wire": "DSP_0_P32", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX32_0->DSP_0_C23": { + "src_wire": "DSP_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP5_3->DSP_0_D13": { + "src_wire": "DSP_BYP5_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_D13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX43_1->DSP_0_RSTCTRL": { + "src_wire": "DSP_IMUX43_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT27->DSP_ACOUT27": { + "src_wire": "DSP_1_ACOUT27", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P2->DSP_LOGIC_OUTS_B6_0": { + "src_wire": "DSP_1_P2", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_CARRYOUT1->DSP_LOGIC_OUTS_B11_3": { + "src_wire": "DSP_1_CARRYOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT39->DSP_1_PCIN39": { + "src_wire": "DSP_0_PCOUT39", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN39", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P40->DSP_LOGIC_OUTS_B13_0": { + "src_wire": "DSP_0_P40", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P16->DSP_LOGIC_OUTS_B21_4": { + "src_wire": "DSP_0_P16", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX7_3->DSP_0_A13": { + "src_wire": "DSP_IMUX7_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_A13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT34->DSP_PCOUT34": { + "src_wire": "DSP_1_PCOUT34", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT34", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_CLK0_3->DSP_1_CLK": { + "src_wire": "DSP_CLK0_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX36_4->DSP_1_CARRYINSEL0": { + "src_wire": "DSP_IMUX36_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P30->DSP_LOGIC_OUTS_B20_2": { + "src_wire": "DSP_0_P30", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D10": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX32_4->DSP_0_C37": { + "src_wire": "DSP_IMUX32_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C37", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX21_2->DSP_0_A10": { + "src_wire": "DSP_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_A10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_CTRL1_1->DSP_0_RSTM": { + "src_wire": "DSP_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTM", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT2->DSP_1_ACIN2": { + "src_wire": "DSP_0_ACOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT11->DSP_PCOUT11": { + "src_wire": "DSP_1_PCOUT11", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX21_1->DSP_0_A6": { + "src_wire": "DSP_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX28_2->DSP_1_C30": { + "src_wire": "DSP_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C30", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX16_4->DSP_1_OPMODE3": { + "src_wire": "DSP_IMUX16_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_CTRL0_4->DSP_1_RSTP": { + "src_wire": "DSP_CTRL0_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTP", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P37->DSP_LOGIC_OUTS_B22_4": { + "src_wire": "DSP_0_P37", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P2->DSP_LOGIC_OUTS_B16_0": { + "src_wire": "DSP_0_P2", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT44->DSP_PCOUT44": { + "src_wire": "DSP_1_PCOUT44", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT44", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_ALUMODE2": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P44->DSP_LOGIC_OUTS_B9_4": { + "src_wire": "DSP_0_P44", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B9_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P20->DSP_LOGIC_OUTS_B7_0": { + "src_wire": "DSP_1_P20", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP0_3->DSP_1_CEAD": { + "src_wire": "DSP_BYP0_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEAD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX20_2->DSP_0_OPMODE4": { + "src_wire": "DSP_IMUX20_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D3": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D4": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT1->DSP_BCOUT1": { + "src_wire": "DSP_1_BCOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN5_4->DSP_1_D18": { + "src_wire": "DSP_FAN5_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_D18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D24": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT32->DSP_1_PCIN32": { + "src_wire": "DSP_0_PCOUT32", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN32", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_CARRYOUT0->DSP_LOGIC_OUTS_B8_3": { + "src_wire": "DSP_1_CARRYOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN3_0->DSP_1_D0": { + "src_wire": "DSP_FAN3_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_D0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN3_2->DSP_1_D8": { + "src_wire": "DSP_FAN3_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_D8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P28->DSP_LOGIC_OUTS_B7_2": { + "src_wire": "DSP_1_P28", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP1_1->DSP_0_D7": { + "src_wire": "DSP_BYP1_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT24->DSP_ACOUT24": { + "src_wire": "DSP_1_ACOUT24", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P1->DSP_LOGIC_OUTS_B23_0": { + "src_wire": "DSP_0_P1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX41_3->DSP_1_B12": { + "src_wire": "DSP_IMUX41_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_B12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D22": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P38->DSP_LOGIC_OUTS_B2_4": { + "src_wire": "DSP_1_P38", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P7->DSP_LOGIC_OUTS_B18_1": { + "src_wire": "DSP_0_P7", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT7->DSP_PCOUT7": { + "src_wire": "DSP_1_PCOUT7", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT3->DSP_1_BCIN3": { + "src_wire": "DSP_0_BCOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX27_0->DSP_1_C40": { + "src_wire": "DSP_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C40", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT26->DSP_1_PCIN26": { + "src_wire": "DSP_0_PCOUT26", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN7_2->DSP_0_OPMODE6": { + "src_wire": "DSP_FAN7_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN7_4->DSP_1_INMODE2": { + "src_wire": "DSP_FAN7_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT13->DSP_1_PCIN13": { + "src_wire": "DSP_0_PCOUT13", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P13->DSP_LOGIC_OUTS_B1_3": { + "src_wire": "DSP_1_P13", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D21": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX19_2->DSP_0_A9": { + "src_wire": "DSP_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_A9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX1_4->DSP_0_C19": { + "src_wire": "DSP_IMUX1_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT5->DSP_1_ACIN5": { + "src_wire": "DSP_0_ACOUT5", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P3->DSP_LOGIC_OUTS_B4_0": { + "src_wire": "DSP_1_P3", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT13->DSP_ACOUT13": { + "src_wire": "DSP_1_ACOUT13", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT19->DSP_1_ACIN19": { + "src_wire": "DSP_0_ACOUT19", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D10": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P30->DSP_LOGIC_OUTS_B2_2": { + "src_wire": "DSP_1_P30", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX17_4->DSP_1_OPMODE4": { + "src_wire": "DSP_IMUX17_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D23": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX5_1->DSP_1_A25": { + "src_wire": "DSP_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT27->DSP_PCOUT27": { + "src_wire": "DSP_1_PCOUT27", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP4_2->DSP_1_INMODE0": { + "src_wire": "DSP_BYP4_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT13->DSP_PCOUT13": { + "src_wire": "DSP_1_PCOUT13", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P21->DSP_LOGIC_OUTS_B5_0": { + "src_wire": "DSP_1_P21", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D13": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP2_3->DSP_0_D23": { + "src_wire": "DSP_BYP2_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_D23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX25_2->DSP_1_C11": { + "src_wire": "DSP_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D21": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P24->DSP_LOGIC_OUTS_B7_1": { + "src_wire": "DSP_1_P24", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT19->DSP_PCOUT19": { + "src_wire": "DSP_1_PCOUT19", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX42_0->DSP_0_C42": { + "src_wire": "DSP_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C42", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX15_0->DSP_1_A0": { + "src_wire": "DSP_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D19": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT17->DSP_PCOUT17": { + "src_wire": "DSP_1_PCOUT17", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D7": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP4_3->DSP_1_CEALUMODE": { + "src_wire": "DSP_BYP4_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX15_3->DSP_1_CARRYIN": { + "src_wire": "DSP_IMUX15_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX9_1->DSP_1_A7": { + "src_wire": "DSP_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT6->DSP_ACOUT6": { + "src_wire": "DSP_1_ACOUT6", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX17_1->DSP_0_A7": { + "src_wire": "DSP_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D6": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX6_2->DSP_0_C28": { + "src_wire": "DSP_IMUX6_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT41->DSP_PCOUT41": { + "src_wire": "DSP_1_PCOUT41", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT41", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX10_3->DSP_1_C33": { + "src_wire": "DSP_IMUX10_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C33", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX39_3->DSP_0_C12": { + "src_wire": "DSP_IMUX39_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P18->DSP_LOGIC_OUTS_B6_4": { + "src_wire": "DSP_1_P18", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX0_3->DSP_1_B15": { + "src_wire": "DSP_IMUX0_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_B15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D3": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D10": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT0->DSP_1_BCIN0": { + "src_wire": "DSP_0_BCOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT10->DSP_ACOUT10": { + "src_wire": "DSP_1_ACOUT10", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT6->DSP_BCOUT6": { + "src_wire": "DSP_1_BCOUT6", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX0_2->DSP_0_CECARRYIN": { + "src_wire": "DSP_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_CECARRYIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX43_2->DSP_1_C9": { + "src_wire": "DSP_IMUX43_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_CEAD": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEAD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_CTRL1_4->DSP_1_RSTB": { + "src_wire": "DSP_CTRL1_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTB", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT8->DSP_ACOUT8": { + "src_wire": "DSP_1_ACOUT8", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P19->DSP_LOGIC_OUTS_B18_4": { + "src_wire": "DSP_0_P19", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D2": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PATTERNDETECT->DSP_LOGIC_OUTS_B11_2": { + "src_wire": "DSP_0_PATTERNDETECT", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT25->DSP_1_PCIN25": { + "src_wire": "DSP_0_PCOUT25", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN5_1->DSP_1_D6": { + "src_wire": "DSP_FAN5_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN5_0->DSP_1_D2": { + "src_wire": "DSP_FAN5_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_D2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT6->DSP_1_ACIN6": { + "src_wire": "DSP_0_ACOUT6", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT3->DSP_PCOUT3": { + "src_wire": "DSP_1_PCOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX43_4->DSP_0_B16": { + "src_wire": "DSP_IMUX43_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_B16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX7_4->DSP_0_A17": { + "src_wire": "DSP_IMUX7_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_A17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_MULTSIGNOUT->DSP_1_MULTSIGNIN": { + "src_wire": "DSP_0_MULTSIGNOUT", + "is_pseudo": "0", + "dst_wire": "DSP_1_MULTSIGNIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT17->DSP_1_ACIN17": { + "src_wire": "DSP_0_ACOUT17", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT3->DSP_1_ACIN3": { + "src_wire": "DSP_0_ACOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D15": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX41_4->DSP_1_C19": { + "src_wire": "DSP_IMUX41_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX44_1->DSP_1_A26": { + "src_wire": "DSP_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT3->DSP_1_PCIN3": { + "src_wire": "DSP_0_PCOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP0_4->DSP_1_ALUMODE3": { + "src_wire": "DSP_BYP0_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP3_1->DSP_0_D6": { + "src_wire": "DSP_BYP3_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX2_2->DSP_0_C29": { + "src_wire": "DSP_IMUX2_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX38_2->DSP_0_OPMODE3": { + "src_wire": "DSP_IMUX38_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX34_3->DSP_1_CEC": { + "src_wire": "DSP_IMUX34_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEC", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT11->DSP_ACOUT11": { + "src_wire": "DSP_1_ACOUT11", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT5->DSP_ACOUT5": { + "src_wire": "DSP_1_ACOUT5", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX41_2->DSP_0_CECTRL": { + "src_wire": "DSP_IMUX41_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_CECTRL", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_CARRYINSEL2": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_RSTD": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX12_4->DSP_1_C38": { + "src_wire": "DSP_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C38", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX22_3->DSP_1_C32": { + "src_wire": "DSP_IMUX22_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C32", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D21": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN1_2->DSP_0_INMODE2": { + "src_wire": "DSP_FAN1_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX34_2->DSP_0_CEP": { + "src_wire": "DSP_IMUX34_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEP", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX23_3->DSP_0_CARRYIN": { + "src_wire": "DSP_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX2_1->DSP_0_RSTALLCARRYIN": { + "src_wire": "DSP_IMUX2_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTALLCARRYIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT47->DSP_1_PCIN47": { + "src_wire": "DSP_0_PCOUT47", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN47", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP0_1->DSP_0_CEAD": { + "src_wire": "DSP_BYP0_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEAD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P23->DSP_LOGIC_OUTS_B0_0": { + "src_wire": "DSP_1_P23", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP6_4->DSP_1_RSTD": { + "src_wire": "DSP_BYP6_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D18": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX29_0->DSP_1_C2": { + "src_wire": "DSP_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX44_4->DSP_1_A18": { + "src_wire": "DSP_IMUX44_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_A18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_CEALUMODE": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX27_1->DSP_1_C5": { + "src_wire": "DSP_IMUX27_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX28_3->DSP_1_OPMODE0": { + "src_wire": "DSP_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT24->DSP_1_PCIN24": { + "src_wire": "DSP_0_PCOUT24", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP2_0->DSP_0_D24": { + "src_wire": "DSP_BYP2_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_D24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX33_2->DSP_0_C11": { + "src_wire": "DSP_IMUX33_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT28->DSP_PCOUT28": { + "src_wire": "DSP_1_PCOUT28", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT29->DSP_1_PCIN29": { + "src_wire": "DSP_0_PCOUT29", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN4_1->DSP_1_D7": { + "src_wire": "DSP_FAN4_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP0_0->DSP_0_ALUMODE3": { + "src_wire": "DSP_BYP0_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT21->DSP_PCOUT21": { + "src_wire": "DSP_1_PCOUT21", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D13": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX17_2->DSP_0_A11": { + "src_wire": "DSP_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_A11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P17->DSP_LOGIC_OUTS_B23_4": { + "src_wire": "DSP_0_P17", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX32_1->DSP_0_C27": { + "src_wire": "DSP_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT45->DSP_PCOUT45": { + "src_wire": "DSP_1_PCOUT45", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT45", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PATTERNDETECT->DSP_LOGIC_OUTS_B13_2": { + "src_wire": "DSP_1_PATTERNDETECT", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP7_4->DSP_0_D16": { + "src_wire": "DSP_BYP7_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_D16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D3": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX10_2->DSP_1_C29": { + "src_wire": "DSP_IMUX10_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D20": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX33_1->DSP_0_C7": { + "src_wire": "DSP_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT4->DSP_BCOUT4": { + "src_wire": "DSP_1_BCOUT4", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P33->DSP_LOGIC_OUTS_B19_3": { + "src_wire": "DSP_0_P33", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX30_4->DSP_1_C36": { + "src_wire": "DSP_IMUX30_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C36", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT33->DSP_1_PCIN33": { + "src_wire": "DSP_0_PCOUT33", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN33", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P12->DSP_LOGIC_OUTS_B21_3": { + "src_wire": "DSP_0_P12", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX12_1->DSP_1_C26": { + "src_wire": "DSP_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX14_4->DSP_1_RSTCTRL": { + "src_wire": "DSP_IMUX14_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT6->DSP_PCOUT6": { + "src_wire": "DSP_1_PCOUT6", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX3_3->DSP_0_B13": { + "src_wire": "DSP_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_B13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P29->DSP_LOGIC_OUTS_B19_2": { + "src_wire": "DSP_0_P29", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX40_3->DSP_1_B14": { + "src_wire": "DSP_IMUX40_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_B14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX16_3->DSP_1_CEB2": { + "src_wire": "DSP_IMUX16_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEB2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_OPMODE6": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX32_2->DSP_0_C31": { + "src_wire": "DSP_IMUX32_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C31", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX27_2->DSP_0_OPMODE2": { + "src_wire": "DSP_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_ALUMODE3": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D14": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P25->DSP_LOGIC_OUTS_B5_1": { + "src_wire": "DSP_1_P25", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX26_2->DSP_1_CEP": { + "src_wire": "DSP_IMUX26_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEP", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT3->DSP_BCOUT3": { + "src_wire": "DSP_1_BCOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P16->DSP_LOGIC_OUTS_B3_4": { + "src_wire": "DSP_1_P16", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P39->DSP_LOGIC_OUTS_B5_4": { + "src_wire": "DSP_1_P39", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT4->DSP_1_PCIN4": { + "src_wire": "DSP_0_PCOUT4", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT0->DSP_BCOUT0": { + "src_wire": "DSP_1_BCOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT23->DSP_1_ACIN23": { + "src_wire": "DSP_0_ACOUT23", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT31->DSP_PCOUT31": { + "src_wire": "DSP_1_PCOUT31", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT31", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D8": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP6_3->DSP_0_INMODE0": { + "src_wire": "DSP_BYP6_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX21_4->DSP_0_C18": { + "src_wire": "DSP_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX24_3->DSP_1_C35": { + "src_wire": "DSP_IMUX24_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C35", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX33_3->DSP_0_C15": { + "src_wire": "DSP_IMUX33_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX27_4->DSP_1_C17": { + "src_wire": "DSP_IMUX27_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX27_3->DSP_1_C13": { + "src_wire": "DSP_IMUX27_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX26_0->DSP_1_B1": { + "src_wire": "DSP_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_B1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P27->DSP_LOGIC_OUTS_B22_1": { + "src_wire": "DSP_0_P27", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_INMODE4": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX44_2->DSP_1_B10": { + "src_wire": "DSP_IMUX44_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_B10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN2_4->DSP_1_OPMODE6": { + "src_wire": "DSP_FAN2_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX15_4->DSP_1_RSTALLCARRYIN": { + "src_wire": "DSP_IMUX15_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTALLCARRYIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX2_3->DSP_0_B15": { + "src_wire": "DSP_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_B15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT43->DSP_PCOUT43": { + "src_wire": "DSP_1_PCOUT43", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT43", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D17": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT7->DSP_ACOUT7": { + "src_wire": "DSP_1_ACOUT7", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP3_2->DSP_0_D10": { + "src_wire": "DSP_BYP3_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_D10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT14->DSP_BCOUT14": { + "src_wire": "DSP_1_BCOUT14", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P35->DSP_LOGIC_OUTS_B22_3": { + "src_wire": "DSP_0_P35", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT10->DSP_1_ACIN10": { + "src_wire": "DSP_0_ACOUT10", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX10_4->DSP_1_C39": { + "src_wire": "DSP_IMUX10_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C39", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT37->DSP_PCOUT37": { + "src_wire": "DSP_1_PCOUT37", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT37", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D11": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT2->DSP_1_PCIN2": { + "src_wire": "DSP_0_PCOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP4_1->DSP_0_RSTD": { + "src_wire": "DSP_BYP4_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D20": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX11_3->DSP_1_CECTRL": { + "src_wire": "DSP_IMUX11_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CECTRL", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX28_1->DSP_1_B6": { + "src_wire": "DSP_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX44_0->DSP_1_A22": { + "src_wire": "DSP_IMUX44_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX3_4->DSP_0_B17": { + "src_wire": "DSP_IMUX3_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_B17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P15->DSP_LOGIC_OUTS_B18_3": { + "src_wire": "DSP_0_P15", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT27->DSP_1_ACIN27": { + "src_wire": "DSP_0_ACOUT27", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN6_3->DSP_1_D13": { + "src_wire": "DSP_FAN6_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_D13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX33_4->DSP_0_C47": { + "src_wire": "DSP_IMUX33_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C47", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P47->DSP_LOGIC_OUTS_B8_4": { + "src_wire": "DSP_0_P47", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP2_1->DSP_1_INMODE1": { + "src_wire": "DSP_BYP2_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT40->DSP_PCOUT40": { + "src_wire": "DSP_1_PCOUT40", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT40", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN6_1->DSP_1_D5": { + "src_wire": "DSP_FAN6_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_CARRYOUT3->DSP_LOGIC_OUTS_B15_3": { + "src_wire": "DSP_1_CARRYOUT3", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P26->DSP_LOGIC_OUTS_B20_1": { + "src_wire": "DSP_0_P26", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D10": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D8": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT15->DSP_PCOUT15": { + "src_wire": "DSP_1_PCOUT15", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX29_4->DSP_1_C45": { + "src_wire": "DSP_IMUX29_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C45", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D7": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX38_4->DSP_0_C36": { + "src_wire": "DSP_IMUX38_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C36", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT47->DSP_PCOUT47": { + "src_wire": "DSP_1_PCOUT47", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT47", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D23": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_CARRYOUT2->DSP_LOGIC_OUTS_B13_1": { + "src_wire": "DSP_0_CARRYOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN4_2->DSP_1_D11": { + "src_wire": "DSP_FAN4_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_D11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX37_2->DSP_0_C10": { + "src_wire": "DSP_IMUX37_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P33->DSP_LOGIC_OUTS_B5_3": { + "src_wire": "DSP_1_P33", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D21": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D20": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX14_2->DSP_1_B8": { + "src_wire": "DSP_IMUX14_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_B8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D5": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX13_1->DSP_1_A6": { + "src_wire": "DSP_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT12->DSP_ACOUT12": { + "src_wire": "DSP_1_ACOUT12", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D0": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_CEAD": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEAD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX18_4->DSP_0_C39": { + "src_wire": "DSP_IMUX18_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C39", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX31_4->DSP_1_C16": { + "src_wire": "DSP_IMUX31_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN6_0->DSP_1_D1": { + "src_wire": "DSP_FAN6_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_D1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D24": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D12": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D17": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P9->DSP_LOGIC_OUTS_B1_2": { + "src_wire": "DSP_1_P9", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D24": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN4_3->DSP_1_D15": { + "src_wire": "DSP_FAN4_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_D15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_MULTSIGNOUT->DSP_MULTSIGNOUT": { + "src_wire": "DSP_1_MULTSIGNOUT", + "is_pseudo": "0", + "dst_wire": "DSP_MULTSIGNOUT", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX29_3->DSP_1_C14": { + "src_wire": "DSP_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P6->DSP_LOGIC_OUTS_B6_1": { + "src_wire": "DSP_1_P6", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT32->DSP_PCOUT32": { + "src_wire": "DSP_1_PCOUT32", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT32", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P28->DSP_LOGIC_OUTS_B17_2": { + "src_wire": "DSP_0_P28", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX34_4->DSP_0_C44": { + "src_wire": "DSP_IMUX34_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C44", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX29_2->DSP_1_C10": { + "src_wire": "DSP_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D12": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT22->DSP_ACOUT22": { + "src_wire": "DSP_1_ACOUT22", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX2_4->DSP_1_B17": { + "src_wire": "DSP_IMUX2_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_B17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P5->DSP_LOGIC_OUTS_B23_1": { + "src_wire": "DSP_0_P5", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX14_1->DSP_1_C24": { + "src_wire": "DSP_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D18": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT1->DSP_PCOUT1": { + "src_wire": "DSP_1_PCOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_CTRL0_1->DSP_0_RSTC": { + "src_wire": "DSP_CTRL0_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTC", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN4_4->DSP_1_D19": { + "src_wire": "DSP_FAN4_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_D19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT33->DSP_PCOUT33": { + "src_wire": "DSP_1_PCOUT33", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT33", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P19->DSP_LOGIC_OUTS_B4_4": { + "src_wire": "DSP_1_P19", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX15_1->DSP_1_A4": { + "src_wire": "DSP_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D13": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN5_2->DSP_1_D10": { + "src_wire": "DSP_FAN5_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_D10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P45->DSP_LOGIC_OUTS_B11_4": { + "src_wire": "DSP_1_P45", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D11": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D3": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_INMODE1": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P23->DSP_LOGIC_OUTS_B22_0": { + "src_wire": "DSP_0_P23", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P29->DSP_LOGIC_OUTS_B5_2": { + "src_wire": "DSP_1_P29", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT0->DSP_1_PCIN0": { + "src_wire": "DSP_0_PCOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT31->DSP_1_PCIN31": { + "src_wire": "DSP_0_PCOUT31", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN31", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX8_0->DSP_1_C41": { + "src_wire": "DSP_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C41", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P47->DSP_LOGIC_OUTS_B15_4": { + "src_wire": "DSP_1_P47", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX12_0->DSP_1_C22": { + "src_wire": "DSP_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT29->DSP_PCOUT29": { + "src_wire": "DSP_1_PCOUT29", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P5->DSP_LOGIC_OUTS_B1_1": { + "src_wire": "DSP_1_P5", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT2->DSP_BCOUT2": { + "src_wire": "DSP_1_BCOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P10->DSP_LOGIC_OUTS_B16_2": { + "src_wire": "DSP_0_P10", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX8_2->DSP_1_B11": { + "src_wire": "DSP_IMUX8_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_B11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_INMODE2": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_CEALUMODE": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT9->DSP_PCOUT9": { + "src_wire": "DSP_1_PCOUT9", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX4_4->DSP_1_A19": { + "src_wire": "DSP_IMUX4_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_A19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_CTRL1_3->DSP_1_RSTM": { + "src_wire": "DSP_CTRL1_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTM", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX29_1->DSP_1_C6": { + "src_wire": "DSP_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT4->DSP_1_BCIN4": { + "src_wire": "DSP_0_BCOUT4", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN7_0->DSP_1_D24": { + "src_wire": "DSP_FAN7_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_D24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT28->DSP_ACOUT28": { + "src_wire": "DSP_1_ACOUT28", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_INMODE3": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D22": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT16->DSP_BCOUT16": { + "src_wire": "DSP_1_BCOUT16", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX1_3->DSP_1_B13": { + "src_wire": "DSP_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_B13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT19->DSP_ACOUT19": { + "src_wire": "DSP_1_ACOUT19", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX40_0->DSP_0_B3": { + "src_wire": "DSP_IMUX40_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_B3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P11->DSP_LOGIC_OUTS_B4_2": { + "src_wire": "DSP_1_P11", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX39_0->DSP_0_C0": { + "src_wire": "DSP_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX18_0->DSP_0_C21": { + "src_wire": "DSP_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P32->DSP_LOGIC_OUTS_B7_3": { + "src_wire": "DSP_1_P32", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX14_3->DSP_0_CARRYINSEL1": { + "src_wire": "DSP_IMUX14_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT13->DSP_BCOUT13": { + "src_wire": "DSP_1_BCOUT13", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P46->DSP_LOGIC_OUTS_B14_4": { + "src_wire": "DSP_1_P46", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX31_1->DSP_1_C4": { + "src_wire": "DSP_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX24_1->DSP_1_C27": { + "src_wire": "DSP_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_ALUMODE2": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX31_3->DSP_1_C12": { + "src_wire": "DSP_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_C12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D1": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P31->DSP_LOGIC_OUTS_B22_2": { + "src_wire": "DSP_0_P31", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_INMODE1": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_CED": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_CED", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P41->DSP_LOGIC_OUTS_B12_0": { + "src_wire": "DSP_0_P41", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B12_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX25_0->DSP_1_C43": { + "src_wire": "DSP_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C43", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX9_2->DSP_1_A11": { + "src_wire": "DSP_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_A11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX26_4->DSP_1_C44": { + "src_wire": "DSP_IMUX26_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C44", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT21->DSP_ACOUT21": { + "src_wire": "DSP_1_ACOUT21", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D14": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D2": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D16": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D1": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT26->DSP_1_ACIN26": { + "src_wire": "DSP_0_ACOUT26", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P6->DSP_LOGIC_OUTS_B16_1": { + "src_wire": "DSP_0_P6", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P42->DSP_LOGIC_OUTS_B10_0": { + "src_wire": "DSP_1_P42", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT17->DSP_BCOUT17": { + "src_wire": "DSP_1_BCOUT17", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX45_1->DSP_1_A24": { + "src_wire": "DSP_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_UNDERFLOW->DSP_LOGIC_OUTS_B14_3": { + "src_wire": "DSP_1_UNDERFLOW", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT14->DSP_1_PCIN14": { + "src_wire": "DSP_0_PCOUT14", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P0->DSP_LOGIC_OUTS_B21_0": { + "src_wire": "DSP_0_P0", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D0": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D16": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P17->DSP_LOGIC_OUTS_B1_4": { + "src_wire": "DSP_1_P17", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_CARRYOUT1->DSP_LOGIC_OUTS_B11_1": { + "src_wire": "DSP_0_CARRYOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P12->DSP_LOGIC_OUTS_B3_3": { + "src_wire": "DSP_1_P12", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D15": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P31->DSP_LOGIC_OUTS_B0_2": { + "src_wire": "DSP_1_P31", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX23_0->DSP_0_A0": { + "src_wire": "DSP_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_OVERFLOW->DSP_LOGIC_OUTS_B8_2": { + "src_wire": "DSP_1_OVERFLOW", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX43_3->DSP_0_B12": { + "src_wire": "DSP_IMUX43_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_B12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX47_4->DSP_0_A16": { + "src_wire": "DSP_IMUX47_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_A16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT35->DSP_PCOUT35": { + "src_wire": "DSP_1_PCOUT35", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT35", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D15": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT10->DSP_1_PCIN10": { + "src_wire": "DSP_0_PCOUT10", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN10", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP6_0->DSP_0_D20": { + "src_wire": "DSP_BYP6_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_D20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP7_3->DSP_0_D12": { + "src_wire": "DSP_BYP7_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_D12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D4": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D23": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX30_0->DSP_1_C20": { + "src_wire": "DSP_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX39_4->DSP_0_C16": { + "src_wire": "DSP_IMUX39_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_RSTD": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX33_0->DSP_0_C43": { + "src_wire": "DSP_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C43", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P43->DSP_LOGIC_OUTS_B14_0": { + "src_wire": "DSP_1_P43", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX46_4->DSP_0_A18": { + "src_wire": "DSP_IMUX46_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_A18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX35_4->DSP_0_C17": { + "src_wire": "DSP_IMUX35_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D19": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT23->DSP_1_PCIN23": { + "src_wire": "DSP_0_PCOUT23", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D4": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT36->DSP_PCOUT36": { + "src_wire": "DSP_1_PCOUT36", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT36", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN0_2->DSP_1_D22": { + "src_wire": "DSP_FAN0_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_D22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX12_2->DSP_0_OPMODE5": { + "src_wire": "DSP_IMUX12_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT25->DSP_ACOUT25": { + "src_wire": "DSP_1_ACOUT25", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX5_0->DSP_1_A21": { + "src_wire": "DSP_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D6": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX19_0->DSP_0_A1": { + "src_wire": "DSP_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX4_1->DSP_1_A27": { + "src_wire": "DSP_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX35_2->DSP_0_OPMODE0": { + "src_wire": "DSP_IMUX35_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT41->DSP_1_PCIN41": { + "src_wire": "DSP_0_PCOUT41", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN41", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP3_3->DSP_0_D14": { + "src_wire": "DSP_BYP3_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_D14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT19->DSP_1_PCIN19": { + "src_wire": "DSP_0_PCOUT19", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT35->DSP_1_PCIN35": { + "src_wire": "DSP_0_PCOUT35", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN35", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P3->DSP_LOGIC_OUTS_B18_0": { + "src_wire": "DSP_0_P3", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT29->DSP_ACOUT29": { + "src_wire": "DSP_1_ACOUT29", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P46->DSP_LOGIC_OUTS_B13_4": { + "src_wire": "DSP_0_P46", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT37->DSP_1_PCIN37": { + "src_wire": "DSP_0_PCOUT37", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN37", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT1->DSP_ACOUT1": { + "src_wire": "DSP_1_ACOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT12->DSP_1_PCIN12": { + "src_wire": "DSP_0_PCOUT12", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D17": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX45_2->DSP_1_A28": { + "src_wire": "DSP_IMUX45_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_A28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX38_3->DSP_0_C32": { + "src_wire": "DSP_IMUX38_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C32", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_ALUMODE2": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_ALUMODE3": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX39_2->DSP_0_C8": { + "src_wire": "DSP_IMUX39_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_C8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX8_3->DSP_1_CEB1": { + "src_wire": "DSP_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEB1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D5": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP0_2->DSP_0_D22": { + "src_wire": "DSP_BYP0_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_D22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX3_0->DSP_0_C1": { + "src_wire": "DSP_IMUX3_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P25->DSP_LOGIC_OUTS_B19_1": { + "src_wire": "DSP_0_P25", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP4_4->DSP_1_INMODE3": { + "src_wire": "DSP_BYP4_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D7": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX30_3->DSP_0_CARRYINSEL0": { + "src_wire": "DSP_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX22_4->DSP_1_RSTALUMODE": { + "src_wire": "DSP_IMUX22_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D12": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT6->DSP_1_BCIN6": { + "src_wire": "DSP_0_BCOUT6", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT17->DSP_1_BCIN17": { + "src_wire": "DSP_0_BCOUT17", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN17", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN5_3->DSP_1_D14": { + "src_wire": "DSP_FAN5_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_D14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX37_1->DSP_0_C6": { + "src_wire": "DSP_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT8->DSP_1_BCIN8": { + "src_wire": "DSP_0_BCOUT8", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P8->DSP_LOGIC_OUTS_B21_2": { + "src_wire": "DSP_0_P8", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT18->DSP_ACOUT18": { + "src_wire": "DSP_1_ACOUT18", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX32_3->DSP_0_C35": { + "src_wire": "DSP_IMUX32_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C35", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX47_2->DSP_0_A28": { + "src_wire": "DSP_IMUX47_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_A28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX42_4->DSP_1_B16": { + "src_wire": "DSP_IMUX42_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_B16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX18_2->DSP_0_B9": { + "src_wire": "DSP_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_B9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D6": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX23_2->DSP_0_A8": { + "src_wire": "DSP_IMUX23_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_A8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX46_2->DSP_1_C28": { + "src_wire": "DSP_IMUX46_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D8": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT0->DSP_ACOUT0": { + "src_wire": "DSP_1_ACOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX1_1->DSP_0_CEB2": { + "src_wire": "DSP_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEB2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_ALUMODE3": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P1->DSP_LOGIC_OUTS_B1_0": { + "src_wire": "DSP_1_P1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX7_2->DSP_0_A29": { + "src_wire": "DSP_IMUX7_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_A29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX30_1->DSP_1_B4": { + "src_wire": "DSP_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D16": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX31_2->DSP_1_C8": { + "src_wire": "DSP_IMUX31_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX37_4->DSP_0_C45": { + "src_wire": "DSP_IMUX37_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C45", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN2_0->DSP_0_CEINMODE": { + "src_wire": "DSP_FAN2_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT0->DSP_1_ACIN0": { + "src_wire": "DSP_0_ACOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P22->DSP_LOGIC_OUTS_B20_0": { + "src_wire": "DSP_0_P22", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX45_3->DSP_1_A12": { + "src_wire": "DSP_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_A12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D9": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX31_0->DSP_1_C0": { + "src_wire": "DSP_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D2": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_CEALUMODE": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX1_0->DSP_0_C3": { + "src_wire": "DSP_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX24_2->DSP_1_C31": { + "src_wire": "DSP_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_C31", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D22": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT40->DSP_1_PCIN40": { + "src_wire": "DSP_0_PCOUT40", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN40", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D5": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN1_0->DSP_1_D20": { + "src_wire": "DSP_FAN1_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_D20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_INMODE4": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX9_3->DSP_1_CEA1": { + "src_wire": "DSP_IMUX9_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEA1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D9": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX9_4->DSP_1_OPMODE5": { + "src_wire": "DSP_IMUX9_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP5_0->DSP_0_D1": { + "src_wire": "DSP_BYP5_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT15->DSP_BCOUT15": { + "src_wire": "DSP_1_BCOUT15", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D11": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D11", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN6_2->DSP_1_D9": { + "src_wire": "DSP_FAN6_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_D9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT14->DSP_1_BCIN14": { + "src_wire": "DSP_0_BCOUT14", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN3_3->DSP_1_D12": { + "src_wire": "DSP_FAN3_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_D12", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT8->DSP_1_PCIN8": { + "src_wire": "DSP_0_PCOUT8", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P22->DSP_LOGIC_OUTS_B2_0": { + "src_wire": "DSP_1_P22", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT7->DSP_BCOUT7": { + "src_wire": "DSP_1_BCOUT7", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P10->DSP_LOGIC_OUTS_B6_2": { + "src_wire": "DSP_1_P10", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D19": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D1": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_CARRYINSEL2": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_INMODE3": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX30_2->DSP_0_OPMODE1": { + "src_wire": "DSP_IMUX30_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP7_0->DSP_0_D0": { + "src_wire": "DSP_BYP7_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_D0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX19_3->DSP_1_CEM": { + "src_wire": "DSP_IMUX19_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEM", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX22_2->DSP_0_B8": { + "src_wire": "DSP_IMUX22_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_B8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX26_3->DSP_1_CECARRYIN": { + "src_wire": "DSP_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_CECARRYIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX6_4->DSP_0_A19": { + "src_wire": "DSP_IMUX6_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_A19", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT20->DSP_1_PCIN20": { + "src_wire": "DSP_0_PCOUT20", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN20", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_INMODE2": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_CED": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_CED", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT16->DSP_1_ACIN16": { + "src_wire": "DSP_0_ACOUT16", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P43->DSP_LOGIC_OUTS_B8_0": { + "src_wire": "DSP_0_P43", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D1": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX7_0->DSP_0_A21": { + "src_wire": "DSP_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_A21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX42_2->DSP_1_B9": { + "src_wire": "DSP_IMUX42_2", + "is_pseudo": "0", + "dst_wire": "DSP_1_B9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX24_0->DSP_1_C23": { + "src_wire": "DSP_IMUX24_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT4->DSP_ACOUT4": { + "src_wire": "DSP_1_ACOUT4", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN0_4->DSP_1_ALUMODE2": { + "src_wire": "DSP_FAN0_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX44_3->DSP_1_A14": { + "src_wire": "DSP_IMUX44_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_A14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P21->DSP_LOGIC_OUTS_B19_0": { + "src_wire": "DSP_0_P21", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX35_3->DSP_0_C13": { + "src_wire": "DSP_IMUX35_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C13", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP6_1->DSP_0_D21": { + "src_wire": "DSP_BYP6_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P45->DSP_LOGIC_OUTS_B10_4": { + "src_wire": "DSP_0_P45", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP6_2->DSP_0_INMODE3": { + "src_wire": "DSP_BYP6_2", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX34_1->DSP_0_C25": { + "src_wire": "DSP_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN7_3->DSP_1_D23": { + "src_wire": "DSP_FAN7_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_D23", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP4_0->DSP_0_CEALUMODE": { + "src_wire": "DSP_BYP4_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_CEALUMODE": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEALUMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_D9": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX47_1->DSP_0_A24": { + "src_wire": "DSP_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN0_1->DSP_0_CED": { + "src_wire": "DSP_FAN0_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CED", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P4->DSP_LOGIC_OUTS_B3_1": { + "src_wire": "DSP_1_P4", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_P14->DSP_LOGIC_OUTS_B16_3": { + "src_wire": "DSP_0_P14", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT14->DSP_ACOUT14": { + "src_wire": "DSP_1_ACOUT14", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D14": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN0_0->DSP_0_ALUMODE2": { + "src_wire": "DSP_FAN0_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT1->DSP_1_ACIN1": { + "src_wire": "DSP_0_ACOUT1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P36->DSP_LOGIC_OUTS_B7_4": { + "src_wire": "DSP_1_P36", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_0_D14": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX36_0->DSP_0_B2": { + "src_wire": "DSP_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_B2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX9_0->DSP_1_A3": { + "src_wire": "DSP_IMUX9_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_A3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX20_4->DSP_0_C38": { + "src_wire": "DSP_IMUX20_4", + "is_pseudo": "0", + "dst_wire": "DSP_0_C38", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_CARRYINSEL2": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_CARRYOUT2->DSP_LOGIC_OUTS_B10_3": { + "src_wire": "DSP_1_CARRYOUT2", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT6->DSP_1_PCIN6": { + "src_wire": "DSP_0_PCOUT6", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN6", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX42_1->DSP_0_RSTINMODE": { + "src_wire": "DSP_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTINMODE", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT4->DSP_1_ACIN4": { + "src_wire": "DSP_0_ACOUT4", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_ACOUT16->DSP_ACOUT16": { + "src_wire": "DSP_1_ACOUT16", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT16", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX28_0->DSP_1_B2": { + "src_wire": "DSP_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_B2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT29->DSP_1_ACIN29": { + "src_wire": "DSP_0_ACOUT29", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN29", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D2": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT38->DSP_1_PCIN38": { + "src_wire": "DSP_0_PCOUT38", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN38", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT0->DSP_PCOUT0": { + "src_wire": "DSP_1_PCOUT0", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT14->DSP_1_ACIN14": { + "src_wire": "DSP_0_ACOUT14", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT24->DSP_PCOUT24": { + "src_wire": "DSP_1_PCOUT24", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX6_3->DSP_0_A15": { + "src_wire": "DSP_IMUX6_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_A15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D24": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_D24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_GND_R->DSP_1_CARRYINSEL2": { + "src_wire": "DSP_GND_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P41->DSP_LOGIC_OUTS_B11_0": { + "src_wire": "DSP_1_P41", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT27->DSP_1_PCIN27": { + "src_wire": "DSP_0_PCOUT27", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP3_0->DSP_0_D2": { + "src_wire": "DSP_BYP3_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_INMODE3": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX39_1->DSP_0_C4": { + "src_wire": "DSP_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C4", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D8": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_D8", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT42->DSP_PCOUT42": { + "src_wire": "DSP_1_PCOUT42", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT42", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_BCOUT9->DSP_BCOUT9": { + "src_wire": "DSP_1_BCOUT9", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT9", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_FAN7_1->DSP_0_INMODE1": { + "src_wire": "DSP_FAN7_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX37_3->DSP_0_C14": { + "src_wire": "DSP_IMUX37_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_C14", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP5_1->DSP_0_D5": { + "src_wire": "DSP_BYP5_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_CTRL0_3->DSP_1_RSTC": { + "src_wire": "DSP_CTRL0_3", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTC", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_1_INMODE0": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_BCOUT7->DSP_1_BCIN7": { + "src_wire": "DSP_0_BCOUT7", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN7", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT26->DSP_PCOUT26": { + "src_wire": "DSP_1_PCOUT26", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_BYP1_3->DSP_0_D15": { + "src_wire": "DSP_BYP1_3", + "is_pseudo": "0", + "dst_wire": "DSP_0_D15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX6_1->DSP_0_A27": { + "src_wire": "DSP_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A27", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_CARRYCASCOUT->DSP_1_CARRYCASCIN": { + "src_wire": "DSP_0_CARRYCASCOUT", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYCASCIN", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX7_1->DSP_0_A25": { + "src_wire": "DSP_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT15->DSP_1_PCIN15": { + "src_wire": "DSP_0_PCOUT15", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN15", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT24->DSP_1_ACIN24": { + "src_wire": "DSP_0_ACOUT24", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN24", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX13_4->DSP_1_C18": { + "src_wire": "DSP_IMUX13_4", + "is_pseudo": "0", + "dst_wire": "DSP_1_C18", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_PCOUT28->DSP_1_PCIN28": { + "src_wire": "DSP_0_PCOUT28", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN28", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX20_0->DSP_0_C22": { + "src_wire": "DSP_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "DSP_0_C22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_PCOUT25->DSP_PCOUT25": { + "src_wire": "DSP_1_PCOUT25", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT25", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX10_0->DSP_1_C21": { + "src_wire": "DSP_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "DSP_1_C21", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P0->DSP_LOGIC_OUTS_B3_0": { + "src_wire": "DSP_1_P0", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_IMUX46_1->DSP_0_A26": { + "src_wire": "DSP_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A26", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_VCC_R->DSP_0_RSTD": { + "src_wire": "DSP_VCC_R", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTD", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_0_ACOUT22->DSP_1_ACIN22": { + "src_wire": "DSP_0_ACOUT22", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN22", + "is_directional": "1", + "can_invert": "0" + }, + "DSP_R.DSP_1_P27->DSP_LOGIC_OUTS_B0_1": { + "src_wire": "DSP_1_P27", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_1", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_GTX_CHANNEL_0.json b/kintex7/tile_type_GTX_CHANNEL_0.json new file mode 100644 index 0000000..74b31a3 --- /dev/null +++ b/kintex7/tile_type_GTX_CHANNEL_0.json @@ -0,0 +1,6854 @@ +{ + "tile_type": "GTX_CHANNEL_0", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "GTXE2_CHANNEL", + "type": "GTXE2_CHANNEL", + "site_pins": { + "RXQPIEN": "GTXE2_CHANNEL_RXQPIEN", + "TXDATA47": "GTXE2_CHANNEL_TXDATA47", + "RXDATA59": "GTXE2_CHANNEL_RXDATA59", + "TXDATA19": "GTXE2_CHANNEL_TXDATA19", + "RXDISPERR3": "GTXE2_CHANNEL_RXDISPERR3", + "RXBUFSTATUS1": "GTXE2_CHANNEL_RXBUFSTATUS1", + "TXCHARDISPMODE5": "GTXE2_CHANNEL_TXCHARDISPMODE5", + "TXCHARDISPMODE3": "GTXE2_CHANNEL_TXCHARDISPMODE3", + "RXDATA47": "GTXE2_CHANNEL_RXDATA47", + "TXDATA24": "GTXE2_CHANNEL_TXDATA24", + "TXHEADER1": "GTXE2_CHANNEL_TXHEADER1", + "TSTIN17": "GTXE2_CHANNEL_TSTIN17", + "TXPHALIGN": "GTXE2_CHANNEL_TXPHALIGN", + "CLKRSVD3": "GTXE2_CHANNEL_CLKRSVD3", + "PCSRSVDIN20": "GTXE2_CHANNEL_PCSRSVDIN20", + "RXDATA25": "GTXE2_CHANNEL_RXDATA25", + "DRPDO9": "GTXE2_CHANNEL_DRPDO9", + "RXDATA20": "GTXE2_CHANNEL_RXDATA20", + "GTRSVD4": "GTXE2_CHANNEL_GTRSVD4", + "TXCOMSAS": "GTXE2_CHANNEL_TXCOMSAS", + "PMASCANCLK2": "GTXE2_CHANNEL_PMASCANCLK2", + "RXBYTEISALIGNED": "GTXE2_CHANNEL_RXBYTEISALIGNED", + "RXPRBSSEL2": "GTXE2_CHANNEL_RXPRBSSEL2", + "TXDATA43": "GTXE2_CHANNEL_TXDATA43", + "RXDATA38": "GTXE2_CHANNEL_RXDATA38", + "RXOUTCLKFABRIC": "GTXE2_CHANNEL_RXOUTCLKFABRIC", + "TSTOUT8": "GTXE2_CHANNEL_TSTOUT8", + "RESETOVRD": "GTXE2_CHANNEL_RESETOVRD", + "GTREFCLK1": "GTXE2_CHANNEL_GTREFCLK1", + "TXSTARTSEQ": "GTXE2_CHANNEL_TXSTARTSEQ", + "RXDATA7": "GTXE2_CHANNEL_RXDATA7", + "RX8B10BEN": "GTXE2_CHANNEL_RX8B10BEN", + "PCSRSVDOUT8": "GTXE2_CHANNEL_PCSRSVDOUT8", + "TXDLYSRESETDONE": "GTXE2_CHANNEL_TXDLYSRESETDONE", + "RXMONITOROUT4": "GTXE2_CHANNEL_RXMONITOROUT4", + "RXOUTCLKSEL1": "GTXE2_CHANNEL_RXOUTCLKSEL1", + "TXPOSTCURSOR0": "GTXE2_CHANNEL_TXPOSTCURSOR0", + "RXCHARISK4": "GTXE2_CHANNEL_RXCHARISK4", + "PCSRSVDOUT11": "GTXE2_CHANNEL_PCSRSVDOUT11", + "SCANENB": "GTXE2_CHANNEL_SCANENB", + "TXCHARDISPMODE1": "GTXE2_CHANNEL_TXCHARDISPMODE1", + "RXDLYTESTENB": "GTXE2_CHANNEL_RXDLYTESTENB", + "RXPCOMMAALIGNEN": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", + "TXPRECURSOR1": "GTXE2_CHANNEL_TXPRECURSOR1", + "RXCHBONDLEVEL1": "GTXE2_CHANNEL_RXCHBONDLEVEL1", + "RXPD0": "GTXE2_CHANNEL_RXPD0", + "DRPDI15": "GTXE2_CHANNEL_DRPDI15", + "TXPOSTCURSORINV": "GTXE2_CHANNEL_TXPOSTCURSORINV", + "GTRSVD7": "GTXE2_CHANNEL_GTRSVD7", + "PMASCANMODEB": "GTXE2_CHANNEL_PMASCANMODEB", + "RXMONITOROUT0": "GTXE2_CHANNEL_RXMONITOROUT0", + "RXRATEDONE": "GTXE2_CHANNEL_RXRATEDONE", + "PMASCANOUT2": "GTXE2_CHANNEL_PMASCANOUT2", + "RXDFETAP4OVRDEN": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", + "RXDATA16": "GTXE2_CHANNEL_RXDATA16", + "TXCHARDISPMODE7": "GTXE2_CHANNEL_TXCHARDISPMODE7", + "RXDATA49": "GTXE2_CHANNEL_RXDATA49", + "SETERRSTATUS": "GTXE2_CHANNEL_SETERRSTATUS", + "TXDLYSRESET": "GTXE2_CHANNEL_TXDLYSRESET", + "TXDATA1": "GTXE2_CHANNEL_TXDATA1", + "TX8B10BBYPASS4": "GTXE2_CHANNEL_TX8B10BBYPASS4", + "PMARSVDIN20": "GTXE2_CHANNEL_PMARSVDIN20", + "TSTOUT0": "GTXE2_CHANNEL_TSTOUT0", + "RXPHDLYRESET": "GTXE2_CHANNEL_RXPHDLYRESET", + "TXDATA30": "GTXE2_CHANNEL_TXDATA30", + "DRPDI12": "GTXE2_CHANNEL_DRPDI12", + "TXRUNDISP4": "GTXE2_CHANNEL_TXRUNDISP4", + "CLKRSVD2": "GTXE2_CHANNEL_CLKRSVD2", + "PCSRSVDIN12": "GTXE2_CHANNEL_PCSRSVDIN12", + "TXCHARDISPMODE0": "GTXE2_CHANNEL_TXCHARDISPMODE0", + "TXDATA51": "GTXE2_CHANNEL_TXDATA51", + "RXMONITOROUT6": "GTXE2_CHANNEL_RXMONITOROUT6", + "CPLLREFCLKLOST": "GTXE2_CHANNEL_CPLLREFCLKLOST", + "SCANOUT2": "GTXE2_CHANNEL_SCANOUT2", + "RXDATA62": "GTXE2_CHANNEL_RXDATA62", + "DRPDI5": "GTXE2_CHANNEL_DRPDI5", + "RXRESETDONE": "GTXE2_CHANNEL_RXRESETDONE", + "TSTCLK0": "GTXE2_CHANNEL_TSTCLK0", + "DRPDO5": "GTXE2_CHANNEL_DRPDO5", + "PCSRSVDIN10": "GTXE2_CHANNEL_PCSRSVDIN10", + "RXCDRHOLD": "GTXE2_CHANNEL_RXCDRHOLD", + "PCSRSVDIN24": "GTXE2_CHANNEL_PCSRSVDIN24", + "TXDIFFCTRL0": "GTXE2_CHANNEL_TXDIFFCTRL0", + "RXMONITOROUT3": "GTXE2_CHANNEL_RXMONITOROUT3", + "TSTIN2": "GTXE2_CHANNEL_TSTIN2", + "RXRATE1": "GTXE2_CHANNEL_RXRATE1", + "PMARSVDIN0": "GTXE2_CHANNEL_PMARSVDIN0", + "RXDFELFHOLD": "GTXE2_CHANNEL_RXDFELFHOLD", + "RXDFEVPHOLD": "GTXE2_CHANNEL_RXDFEVPHOLD", + "RXDATA26": "GTXE2_CHANNEL_RXDATA26", + "TXPRBSSEL2": "GTXE2_CHANNEL_TXPRBSSEL2", + "TXDATA20": "GTXE2_CHANNEL_TXDATA20", + "TXDATA18": "GTXE2_CHANNEL_TXDATA18", + "TXCHARISK7": "GTXE2_CHANNEL_TXCHARISK7", + "LOOPBACK0": "GTXE2_CHANNEL_LOOPBACK0", + "TXPHDLYPD": "GTXE2_CHANNEL_TXPHDLYPD", + "TXPRECURSOR3": "GTXE2_CHANNEL_TXPRECURSOR3", + "DRPDO11": "GTXE2_CHANNEL_DRPDO11", + "GTXRXP": "GTXE2_CHANNEL_RXP", + "TXCHARDISPVAL7": "GTXE2_CHANNEL_TXCHARDISPVAL7", + "RXCHANBONDSEQ": "GTXE2_CHANNEL_RXCHANBONDSEQ", + "DRPDI6": "GTXE2_CHANNEL_DRPDI6", + "TXDATA48": "GTXE2_CHANNEL_TXDATA48", + "CPLLFBCLKLOST": "GTXE2_CHANNEL_CPLLFBCLKLOST", + "RXDATA55": "GTXE2_CHANNEL_RXDATA55", + "TSTIN10": "GTXE2_CHANNEL_TSTIN10", + "RXDATA60": "GTXE2_CHANNEL_RXDATA60", + "RXDATA11": "GTXE2_CHANNEL_RXDATA11", + "SCANIN1": "GTXE2_CHANNEL_SCANIN1", + "DRPDO3": "GTXE2_CHANNEL_DRPDO3", + "TXDATA8": "GTXE2_CHANNEL_TXDATA8", + "RXCHBONDEN": "GTXE2_CHANNEL_RXCHBONDEN", + "PMASCANOUT1": "GTXE2_CHANNEL_PMASCANOUT1", + "DMONITOROUT4": "GTXE2_CHANNEL_DMONITOROUT4", + "SCANOUT3": "GTXE2_CHANNEL_SCANOUT3", + "RXDATA57": "GTXE2_CHANNEL_RXDATA57", + "TXDATA25": "GTXE2_CHANNEL_TXDATA25", + "RXDFEUTOVRDEN": "GTXE2_CHANNEL_RXDFEUTOVRDEN", + "PMASCANIN3": "GTXE2_CHANNEL_PMASCANIN3", + "TXPISOPD": "GTXE2_CHANNEL_TXPISOPD", + "TXCHARDISPMODE6": "GTXE2_CHANNEL_TXCHARDISPMODE6", + "RXCDRFREQRESET": "GTXE2_CHANNEL_RXCDRFREQRESET", + "TXCHARDISPVAL4": "GTXE2_CHANNEL_TXCHARDISPVAL4", + "GTSOUTHREFCLK0": "GTXE2_CHANNEL_GTSOUTHREFCLK0", + "TXCHARDISPVAL5": "GTXE2_CHANNEL_TXCHARDISPVAL5", + "GTXRXN": "GTXE2_CHANNEL_RXN", + "TXDATA53": "GTXE2_CHANNEL_TXDATA53", + "RXPHDLYPD": "GTXE2_CHANNEL_RXPHDLYPD", + "TSTPD2": "GTXE2_CHANNEL_TSTPD2", + "RXCHBONDO1": "GTXE2_CHANNEL_RXCHBONDO1", + "RXBUFSTATUS0": "GTXE2_CHANNEL_RXBUFSTATUS0", + "TXDATA13": "GTXE2_CHANNEL_TXDATA13", + "PMASCANOUT0": "GTXE2_CHANNEL_PMASCANOUT0", + "RXCHARISCOMMA2": "GTXE2_CHANNEL_RXCHARISCOMMA2", + "TXOUTCLKPCS": "GTXE2_CHANNEL_TXOUTCLKPCS", + "PCSRSVDOUT14": "GTXE2_CHANNEL_PCSRSVDOUT14", + "RXDATA24": "GTXE2_CHANNEL_RXDATA24", + "RXDATA37": "GTXE2_CHANNEL_RXDATA37", + "TX8B10BBYPASS1": "GTXE2_CHANNEL_TX8B10BBYPASS1", + "DRPDI9": "GTXE2_CHANNEL_DRPDI9", + "TXCHARDISPMODE2": "GTXE2_CHANNEL_TXCHARDISPMODE2", + "TXOUTCLKSEL1": "GTXE2_CHANNEL_TXOUTCLKSEL1", + "RXCHBONDMASTER": "GTXE2_CHANNEL_RXCHBONDMASTER", + "TXDATA28": "GTXE2_CHANNEL_TXDATA28", + "RXDATA34": "GTXE2_CHANNEL_RXDATA34", + "CFGRESET": "GTXE2_CHANNEL_CFGRESET", + "RXDFEVPOVRDEN": "GTXE2_CHANNEL_RXDFEVPOVRDEN", + "TXDATA29": "GTXE2_CHANNEL_TXDATA29", + "GTRESETSEL": "GTXE2_CHANNEL_GTRESETSEL", + "EDTCONFIGURATION": "GTXE2_CHANNEL_EDTCONFIGURATION", + "TXCHARISK4": "GTXE2_CHANNEL_TXCHARISK4", + "TXQPISENP": "GTXE2_CHANNEL_TXQPISENP", + "RXCHBONDLEVEL0": "GTXE2_CHANNEL_RXCHBONDLEVEL0", + "PCSRSVDIN8": "GTXE2_CHANNEL_PCSRSVDIN8", + "PMASCANIN0": "GTXE2_CHANNEL_PMASCANIN0", + "DRPDO4": "GTXE2_CHANNEL_DRPDO4", + "RXDATA14": "GTXE2_CHANNEL_RXDATA14", + "TSTOUT5": "GTXE2_CHANNEL_TSTOUT5", + "EDTCLOCK": "GTXE2_CHANNEL_EDTCLOCK", + "QPLLREFCLK": "GTXE2_CHANNEL_GTQPLLREFCLK", + "RXDATA39": "GTXE2_CHANNEL_RXDATA39", + "RXLPMEN": "GTXE2_CHANNEL_RXLPMEN", + "EDTUPDATE": "GTXE2_CHANNEL_EDTUPDATE", + "TXSWING": "GTXE2_CHANNEL_TXSWING", + "TXRATE0": "GTXE2_CHANNEL_TXRATE0", + "RXDATA9": "GTXE2_CHANNEL_RXDATA9", + "TXRUNDISP5": "GTXE2_CHANNEL_TXRUNDISP5", + "RXMCOMMAALIGNEN": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", + "SCANIN2": "GTXE2_CHANNEL_SCANIN2", + "TXPOLARITY": "GTXE2_CHANNEL_TXPOLARITY", + "RXDATA32": "GTXE2_CHANNEL_RXDATA32", + "DRPDO2": "GTXE2_CHANNEL_DRPDO2", + "TXPOSTCURSOR3": "GTXE2_CHANNEL_TXPOSTCURSOR3", + "TXDLYTESTENB": "GTXE2_CHANNEL_TXDLYTESTENB", + "RXLPMLFKLOVRDEN": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", + "RXRATE2": "GTXE2_CHANNEL_RXRATE2", + "RXDFECM1EN": "GTXE2_CHANNEL_RXDFECM1EN", + "RXCDRRESETRSV": "GTXE2_CHANNEL_RXCDRRESETRSV", + "SCANCLK": "GTXE2_CHANNEL_SCANCLK", + "TSTIN6": "GTXE2_CHANNEL_TSTIN6", + "TXDLYHOLD": "GTXE2_CHANNEL_TXDLYHOLD", + "RXCHANREALIGN": "GTXE2_CHANNEL_RXCHANREALIGN", + "RXCHBONDO4": "GTXE2_CHANNEL_RXCHBONDO4", + "TXRUNDISP1": "GTXE2_CHANNEL_TXRUNDISP1", + "TXDATA23": "GTXE2_CHANNEL_TXDATA23", + "TXDATA21": "GTXE2_CHANNEL_TXDATA21", + "RXNOTINTABLE7": "GTXE2_CHANNEL_RXNOTINTABLE7", + "RXDATA29": "GTXE2_CHANNEL_RXDATA29", + "TXDATA37": "GTXE2_CHANNEL_TXDATA37", + "DMONITOROUT1": "GTXE2_CHANNEL_DMONITOROUT1", + "PMASCANCLK4": "GTXE2_CHANNEL_PMASCANCLK4", + "PCSRSVDOUT9": "GTXE2_CHANNEL_PCSRSVDOUT9", + "TXPHDLYTSTCLK": "GTXE2_CHANNEL_TXPHDLYTSTCLK", + "TXUSRCLK2": "GTXE2_CHANNEL_TXUSRCLK2", + "DRPDO15": "GTXE2_CHANNEL_DRPDO15", + "TXOUTCLKSEL2": "GTXE2_CHANNEL_TXOUTCLKSEL2", + "TX8B10BBYPASS2": "GTXE2_CHANNEL_TX8B10BBYPASS2", + "CPLLLOCKEN": "GTXE2_CHANNEL_CPLLLOCKEN", + "DRPDI4": "GTXE2_CHANNEL_DRPDI4", + "TXDATA42": "GTXE2_CHANNEL_TXDATA42", + "RXHEADERVALID": "GTXE2_CHANNEL_RXHEADERVALID", + "RXDISPERR2": "GTXE2_CHANNEL_RXDISPERR2", + "RXCHBONDI0": "GTXE2_CHANNEL_RXCHBONDI0", + "TXBUFSTATUS1": "GTXE2_CHANNEL_TXBUFSTATUS1", + "PCSRSVDOUT5": "GTXE2_CHANNEL_PCSRSVDOUT5", + "RXPRBSSEL1": "GTXE2_CHANNEL_RXPRBSSEL1", + "RXDATA2": "GTXE2_CHANNEL_RXDATA2", + "RXDATA18": "GTXE2_CHANNEL_RXDATA18", + "TXOUTCLKFABRIC": "GTXE2_CHANNEL_TXOUTCLKFABRIC", + "PMARSVDIN24": "GTXE2_CHANNEL_PMARSVDIN24", + "TXQPISENN": "GTXE2_CHANNEL_TXQPISENN", + "RXQPISENN": "GTXE2_CHANNEL_RXQPISENN", + "TSTOUT4": "GTXE2_CHANNEL_TSTOUT4", + "TXDATA22": "GTXE2_CHANNEL_TXDATA22", + "DRPWE": "GTXE2_CHANNEL_DRPWE", + "RXCHANISALIGNED": "GTXE2_CHANNEL_RXCHANISALIGNED", + "TXPHOVRDEN": "GTXE2_CHANNEL_TXPHOVRDEN", + "RXDATA54": "GTXE2_CHANNEL_RXDATA54", + "TX8B10BBYPASS6": "GTXE2_CHANNEL_TX8B10BBYPASS6", + "TXDIFFCTRL2": "GTXE2_CHANNEL_TXDIFFCTRL2", + "TXINHIBIT": "GTXE2_CHANNEL_TXINHIBIT", + "TSTIN8": "GTXE2_CHANNEL_TSTIN8", + "TSTIN3": "GTXE2_CHANNEL_TSTIN3", + "TXDATA35": "GTXE2_CHANNEL_TXDATA35", + "TXHEADER0": "GTXE2_CHANNEL_TXHEADER0", + "RXDATA8": "GTXE2_CHANNEL_RXDATA8", + "SCANIN0": "GTXE2_CHANNEL_SCANIN0", + "TXPCSRESET": "GTXE2_CHANNEL_TXPCSRESET", + "TXPOSTCURSOR4": "GTXE2_CHANNEL_TXPOSTCURSOR4", + "RXCHARISK2": "GTXE2_CHANNEL_RXCHARISK2", + "RXDLYBYPASS": "GTXE2_CHANNEL_RXDLYBYPASS", + "PCSRSVDIN14": "GTXE2_CHANNEL_PCSRSVDIN14", + "TXPRECURSORINV": "GTXE2_CHANNEL_TXPRECURSORINV", + "RXDATA40": "GTXE2_CHANNEL_RXDATA40", + "TXCHARDISPVAL2": "GTXE2_CHANNEL_TXCHARDISPVAL2", + "TX8B10BBYPASS3": "GTXE2_CHANNEL_TX8B10BBYPASS3", + "PCSRSVDOUT2": "GTXE2_CHANNEL_PCSRSVDOUT2", + "TXDATA45": "GTXE2_CHANNEL_TXDATA45", + "RXHEADER2": "GTXE2_CHANNEL_RXHEADER2", + "EYESCANTRIGGER": "GTXE2_CHANNEL_EYESCANTRIGGER", + "RXDATA53": "GTXE2_CHANNEL_RXDATA53", + "TXMAINCURSOR0": "GTXE2_CHANNEL_TXMAINCURSOR0", + "PMARSVDIN23": "GTXE2_CHANNEL_PMARSVDIN23", + "RXDATA10": "GTXE2_CHANNEL_RXDATA10", + "DRPDI10": "GTXE2_CHANNEL_DRPDI10", + "RXDATA58": "GTXE2_CHANNEL_RXDATA58", + "CPLLREFCLKSEL0": "GTXE2_CHANNEL_CPLLREFCLKSEL0", + "DMONITOROUT0": "GTXE2_CHANNEL_DMONITOROUT0", + "PCSRSVDIN2": "GTXE2_CHANNEL_PCSRSVDIN2", + "RXDLYEN": "GTXE2_CHANNEL_RXDLYEN", + "EYESCANMODE": "GTXE2_CHANNEL_EYESCANMODE", + "PMASCANOUT4": "GTXE2_CHANNEL_PMASCANOUT4", + "RXBYTEREALIGN": "GTXE2_CHANNEL_RXBYTEREALIGN", + "RXCOMWAKEDET": "GTXE2_CHANNEL_RXCOMWAKEDET", + "TSTOUT2": "GTXE2_CHANNEL_TSTOUT2", + "RXPRBSSEL0": "GTXE2_CHANNEL_RXPRBSSEL0", + "TXSEQUENCE6": "GTXE2_CHANNEL_TXSEQUENCE6", + "TSTIN14": "GTXE2_CHANNEL_TSTIN14", + "CPLLRESET": "GTXE2_CHANNEL_CPLLRESET", + "RXCHARISK1": "GTXE2_CHANNEL_RXCHARISK1", + "GTSOUTHREFCLK1": "GTXE2_CHANNEL_GTSOUTHREFCLK1", + "RXDATA3": "GTXE2_CHANNEL_RXDATA3", + "TXPRBSSEL0": "GTXE2_CHANNEL_TXPRBSSEL0", + "SCANIN4": "GTXE2_CHANNEL_SCANIN4", + "RXDATA36": "GTXE2_CHANNEL_RXDATA36", + "TXGEARBOXREADY": "GTXE2_CHANNEL_TXGEARBOXREADY", + "TXRESETDONE": "GTXE2_CHANNEL_TXRESETDONE", + "DRPDO12": "GTXE2_CHANNEL_DRPDO12", + "PCSRSVDOUT12": "GTXE2_CHANNEL_PCSRSVDOUT12", + "GTNORTHREFCLK0": "GTXE2_CHANNEL_GTNORTHREFCLK0", + "RXPMARESET": "GTXE2_CHANNEL_RXPMARESET", + "TXSYSCLKSEL0": "GTXE2_CHANNEL_TXSYSCLKSEL0", + "TSTIN7": "GTXE2_CHANNEL_TSTIN7", + "DMONITOROUT3": "GTXE2_CHANNEL_DMONITOROUT3", + "PCSRSVDIN9": "GTXE2_CHANNEL_PCSRSVDIN9", + "TXCOMINIT": "GTXE2_CHANNEL_TXCOMINIT", + "TXPD1": "GTXE2_CHANNEL_TXPD1", + "RXCHARISCOMMA7": "GTXE2_CHANNEL_RXCHARISCOMMA7", + "RXMONITORSEL0": "GTXE2_CHANNEL_RXMONITORSEL0", + "RXOUTCLKPCS": "GTXE2_CHANNEL_RXOUTCLKPCS", + "RXMONITOROUT2": "GTXE2_CHANNEL_RXMONITOROUT2", + "RXPHSLIPMONITOR1": "GTXE2_CHANNEL_RXPHSLIPMONITOR1", + "SCANIN3": "GTXE2_CHANNEL_SCANIN3", + "DRPADDR6": "GTXE2_CHANNEL_DRPADDR6", + "RXCHARISK6": "GTXE2_CHANNEL_RXCHARISK6", + "RXLPMHFOVRDEN": "GTXE2_CHANNEL_RXLPMHFOVRDEN", + "RXDLYOVRDEN": "GTXE2_CHANNEL_RXDLYOVRDEN", + "LOOPBACK2": "GTXE2_CHANNEL_LOOPBACK2", + "PCSRSVDIN11": "GTXE2_CHANNEL_PCSRSVDIN11", + "DRPCLK": "GTXE2_CHANNEL_DRPCLK", + "TXMAINCURSOR1": "GTXE2_CHANNEL_TXMAINCURSOR1", + "RXSLIDE": "GTXE2_CHANNEL_RXSLIDE", + "TXUSERRDY": "GTXE2_CHANNEL_TXUSERRDY", + "RXMONITOROUT5": "GTXE2_CHANNEL_RXMONITOROUT5", + "TX8B10BBYPASS5": "GTXE2_CHANNEL_TX8B10BBYPASS5", + "RXPCSRESET": "GTXE2_CHANNEL_RXPCSRESET", + "TXDATA26": "GTXE2_CHANNEL_TXDATA26", + "TXELECIDLE": "GTXE2_CHANNEL_TXELECIDLE", + "DRPADDR8": "GTXE2_CHANNEL_DRPADDR8", + "RXPOLARITY": "GTXE2_CHANNEL_RXPOLARITY", + "TXCHARDISPVAL6": "GTXE2_CHANNEL_TXCHARDISPVAL6", + "RXDATA35": "GTXE2_CHANNEL_RXDATA35", + "TSTPDOVRDB": "GTXE2_CHANNEL_TSTPDOVRDB", + "RXCHARISCOMMA4": "GTXE2_CHANNEL_RXCHARISCOMMA4", + "RXLPMLFHOLD": "GTXE2_CHANNEL_RXLPMLFHOLD", + "DRPDI3": "GTXE2_CHANNEL_DRPDI3", + "TXPOSTCURSOR1": "GTXE2_CHANNEL_TXPOSTCURSOR1", + "RXDATA50": "GTXE2_CHANNEL_RXDATA50", + "TXSEQUENCE5": "GTXE2_CHANNEL_TXSEQUENCE5", + "RXOUTCLK": "GTXE2_CHANNEL_GTRXOUTCLK_0", + "GTRSVD3": "GTXE2_CHANNEL_GTRSVD3", + "RXPHMONITOR3": "GTXE2_CHANNEL_RXPHMONITOR3", + "RXNOTINTABLE2": "GTXE2_CHANNEL_RXNOTINTABLE2", + "RXPHOVRDEN": "GTXE2_CHANNEL_RXPHOVRDEN", + "EYESCANRESET": "GTXE2_CHANNEL_EYESCANRESET", + "RXNOTINTABLE0": "GTXE2_CHANNEL_RXNOTINTABLE0", + "TXMARGIN2": "GTXE2_CHANNEL_TXMARGIN2", + "RXDFETAP3HOLD": "GTXE2_CHANNEL_RXDFETAP3HOLD", + "PCSRSVDIN15": "GTXE2_CHANNEL_PCSRSVDIN15", + "TXDATA38": "GTXE2_CHANNEL_TXDATA38", + "TXSEQUENCE2": "GTXE2_CHANNEL_TXSEQUENCE2", + "DRPADDR0": "GTXE2_CHANNEL_DRPADDR0", + "RXOSOVRDEN": "GTXE2_CHANNEL_RXOSOVRDEN", + "TXPHALIGNDONE": "GTXE2_CHANNEL_TXPHALIGNDONE", + "TXCHARISK3": "GTXE2_CHANNEL_TXCHARISK3", + "TSTPD0": "GTXE2_CHANNEL_TSTPD0", + "PCSRSVDOUT6": "GTXE2_CHANNEL_PCSRSVDOUT6", + "TXBUFDIFFCTRL2": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", + "TXMAINCURSOR4": "GTXE2_CHANNEL_TXMAINCURSOR4", + "RXCHARISCOMMA6": "GTXE2_CHANNEL_RXCHARISCOMMA6", + "RXDFETAP2HOLD": "GTXE2_CHANNEL_RXDFETAP2HOLD", + "RXSTATUS2": "GTXE2_CHANNEL_RXSTATUS2", + "TXRUNDISP3": "GTXE2_CHANNEL_TXRUNDISP3", + "RXDATA48": "GTXE2_CHANNEL_RXDATA48", + "TXDATA5": "GTXE2_CHANNEL_TXDATA5", + "DMONITOROUT5": "GTXE2_CHANNEL_DMONITOROUT5", + "RXCHARISCOMMA0": "GTXE2_CHANNEL_RXCHARISCOMMA0", + "TXDATA63": "GTXE2_CHANNEL_TXDATA63", + "DMONITOROUT6": "GTXE2_CHANNEL_DMONITOROUT6", + "RXELECIDLE": "GTXE2_CHANNEL_RXELECIDLE", + "RXGEARBOXSLIP": "GTXE2_CHANNEL_RXGEARBOXSLIP", + "GTRSVD13": "GTXE2_CHANNEL_GTRSVD13", + "RXMONITORSEL1": "GTXE2_CHANNEL_RXMONITORSEL1", + "RXPHMONITOR4": "GTXE2_CHANNEL_RXPHMONITOR4", + "RXDATA44": "GTXE2_CHANNEL_RXDATA44", + "SCANOUT0": "GTXE2_CHANNEL_SCANOUT0", + "PHYSTATUS": "GTXE2_CHANNEL_PHYSTATUS", + "TXRUNDISP6": "GTXE2_CHANNEL_TXRUNDISP6", + "GTRSVD14": "GTXE2_CHANNEL_GTRSVD14", + "RXDFETAP5OVRDEN": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", + "RXDATA56": "GTXE2_CHANNEL_RXDATA56", + "RXCOMSASDET": "GTXE2_CHANNEL_RXCOMSASDET", + "TXQPIBIASEN": "GTXE2_CHANNEL_TXQPIBIASEN", + "RXCHBONDLEVEL2": "GTXE2_CHANNEL_RXCHBONDLEVEL2", + "RXDATA41": "GTXE2_CHANNEL_RXDATA41", + "RXDATA33": "GTXE2_CHANNEL_RXDATA33", + "RXDATA61": "GTXE2_CHANNEL_RXDATA61", + "RXDATA1": "GTXE2_CHANNEL_RXDATA1", + "RXMONITOROUT1": "GTXE2_CHANNEL_RXMONITOROUT1", + "TXPHALIGNEN": "GTXE2_CHANNEL_TXPHALIGNEN", + "GTRSVD0": "GTXE2_CHANNEL_GTRSVD0", + "RXDISPERR1": "GTXE2_CHANNEL_RXDISPERR1", + "TXDATA56": "GTXE2_CHANNEL_TXDATA56", + "TXDIFFCTRL3": "GTXE2_CHANNEL_TXDIFFCTRL3", + "DRPADDR1": "GTXE2_CHANNEL_DRPADDR1", + "TXCHARISK0": "GTXE2_CHANNEL_TXCHARISK0", + "PCSRSVDOUT10": "GTXE2_CHANNEL_PCSRSVDOUT10", + "CPLLLOCK": "GTXE2_CHANNEL_CPLLLOCK", + "TXBUFSTATUS0": "GTXE2_CHANNEL_TXBUFSTATUS0", + "RXCHARISK7": "GTXE2_CHANNEL_RXCHARISK7", + "RXNOTINTABLE6": "GTXE2_CHANNEL_RXNOTINTABLE6", + "DRPEN": "GTXE2_CHANNEL_DRPEN", + "TXBUFDIFFCTRL0": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", + "TXDATA62": "GTXE2_CHANNEL_TXDATA62", + "TXBUFDIFFCTRL1": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", + "SCANOUT4": "GTXE2_CHANNEL_SCANOUT4", + "DRPDO6": "GTXE2_CHANNEL_DRPDO6", + "DRPADDR7": "GTXE2_CHANNEL_DRPADDR7", + "RXSTATUS1": "GTXE2_CHANNEL_RXSTATUS1", + "RXDISPERR5": "GTXE2_CHANNEL_RXDISPERR5", + "RXVALID": "GTXE2_CHANNEL_RXVALID", + "DRPDI2": "GTXE2_CHANNEL_DRPDI2", + "GTRSVD9": "GTXE2_CHANNEL_GTRSVD9", + "TXDATA60": "GTXE2_CHANNEL_TXDATA60", + "TXDLYUPDOWN": "GTXE2_CHANNEL_TXDLYUPDOWN", + "RXDFETAP3OVRDEN": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", + "RXCOMINITDET": "GTXE2_CHANNEL_RXCOMINITDET", + "RXOUTCLKSEL0": "GTXE2_CHANNEL_RXOUTCLKSEL0", + "TXDATA11": "GTXE2_CHANNEL_TXDATA11", + "RXSYSCLKSEL1": "GTXE2_CHANNEL_RXSYSCLKSEL1", + "RXSTATUS0": "GTXE2_CHANNEL_RXSTATUS0", + "TXDATA52": "GTXE2_CHANNEL_TXDATA52", + "RXDATA46": "GTXE2_CHANNEL_RXDATA46", + "RXOSHOLD": "GTXE2_CHANNEL_RXOSHOLD", + "RXCOMMADET": "GTXE2_CHANNEL_RXCOMMADET", + "RXCHBONDO3": "GTXE2_CHANNEL_RXCHBONDO3", + "RXDATA31": "GTXE2_CHANNEL_RXDATA31", + "RXUSERRDY": "GTXE2_CHANNEL_RXUSERRDY", + "RXCHBONDSLAVE": "GTXE2_CHANNEL_RXCHBONDSLAVE", + "RXCHBONDI2": "GTXE2_CHANNEL_RXCHBONDI2", + "PCSRSVDIN0": "GTXE2_CHANNEL_PCSRSVDIN0", + "TXDATA10": "GTXE2_CHANNEL_TXDATA10", + "TXCHARISK5": "GTXE2_CHANNEL_TXCHARISK5", + "RXPHMONITOR1": "GTXE2_CHANNEL_RXPHMONITOR1", + "TXDATA33": "GTXE2_CHANNEL_TXDATA33", + "TSTIN0": "GTXE2_CHANNEL_TSTIN0", + "TX8B10BEN": "GTXE2_CHANNEL_TX8B10BEN", + "PMASCANOUT3": "GTXE2_CHANNEL_PMASCANOUT3", + "RXDATA45": "GTXE2_CHANNEL_RXDATA45", + "GTREFCLKMONITOR": "GTXE2_CHANNEL_GTREFCLKMONITOR", + "PCSRSVDIN7": "GTXE2_CHANNEL_PCSRSVDIN7", + "TXCHARISK1": "GTXE2_CHANNEL_TXCHARISK1", + "TXRUNDISP0": "GTXE2_CHANNEL_TXRUNDISP0", + "RXDATA52": "GTXE2_CHANNEL_RXDATA52", + "RXPD1": "GTXE2_CHANNEL_RXPD1", + "TXDLYOVRDEN": "GTXE2_CHANNEL_TXDLYOVRDEN", + "TXDATA36": "GTXE2_CHANNEL_TXDATA36", + "RXPHSLIPMONITOR2": "GTXE2_CHANNEL_RXPHSLIPMONITOR2", + "TXMARGIN0": "GTXE2_CHANNEL_TXMARGIN0", + "TXDATA34": "GTXE2_CHANNEL_TXDATA34", + "TXSEQUENCE1": "GTXE2_CHANNEL_TXSEQUENCE1", + "RXCLKCORCNT0": "GTXE2_CHANNEL_RXCLKCORCNT0", + "RXCHBONDI1": "GTXE2_CHANNEL_RXCHBONDI1", + "GTRSVD8": "GTXE2_CHANNEL_GTRSVD8", + "CPLLPD": "GTXE2_CHANNEL_CPLLPD", + "RXDATA21": "GTXE2_CHANNEL_RXDATA21", + "RXCHARISCOMMA3": "GTXE2_CHANNEL_RXCHARISCOMMA3", + "TSTPD3": "GTXE2_CHANNEL_TSTPD3", + "GTRSVD12": "GTXE2_CHANNEL_GTRSVD12", + "RXDATA51": "GTXE2_CHANNEL_RXDATA51", + "PMASCANCLK0": "GTXE2_CHANNEL_PMASCANCLK0", + "TXDATA54": "GTXE2_CHANNEL_TXDATA54", + "TSTPD1": "GTXE2_CHANNEL_TSTPD1", + "GTXTXN": "GTXE2_CHANNEL_TXN", + "TXDATA32": "GTXE2_CHANNEL_TXDATA32", + "RXPHMONITOR2": "GTXE2_CHANNEL_RXPHMONITOR2", + "RXELECIDLEMODE1": "GTXE2_CHANNEL_RXELECIDLEMODE1", + "RXDATA28": "GTXE2_CHANNEL_RXDATA28", + "RXCHARISK5": "GTXE2_CHANNEL_RXCHARISK5", + "RXPHALIGNEN": "GTXE2_CHANNEL_RXPHALIGNEN", + "TSTIN19": "GTXE2_CHANNEL_TSTIN19", + "PMASCANIN2": "GTXE2_CHANNEL_PMASCANIN2", + "PMARSVDIN2": "GTXE2_CHANNEL_PMARSVDIN2", + "PCSRSVDIN5": "GTXE2_CHANNEL_PCSRSVDIN5", + "RXPHALIGNDONE": "GTXE2_CHANNEL_RXPHALIGNDONE", + "RXDATA0": "GTXE2_CHANNEL_RXDATA0", + "TXRATE2": "GTXE2_CHANNEL_TXRATE2", + "CPLLREFCLKSEL1": "GTXE2_CHANNEL_CPLLREFCLKSEL1", + "TSTOUT7": "GTXE2_CHANNEL_TSTOUT7", + "TXPHINITDONE": "GTXE2_CHANNEL_TXPHINITDONE", + "RXDATA15": "GTXE2_CHANNEL_RXDATA15", + "TXDATA16": "GTXE2_CHANNEL_TXDATA16", + "RXPRBSCNTRESET": "GTXE2_CHANNEL_RXPRBSCNTRESET", + "TXDATA14": "GTXE2_CHANNEL_TXDATA14", + "GTRSVD6": "GTXE2_CHANNEL_GTRSVD6", + "RXNOTINTABLE1": "GTXE2_CHANNEL_RXNOTINTABLE1", + "TXDATA2": "GTXE2_CHANNEL_TXDATA2", + "RXCHBONDO0": "GTXE2_CHANNEL_RXCHBONDO0", + "TXDEEMPH": "GTXE2_CHANNEL_TXDEEMPH", + "GTNORTHREFCLK1": "GTXE2_CHANNEL_GTNORTHREFCLK1", + "RXDFETAP4HOLD": "GTXE2_CHANNEL_RXDFETAP4HOLD", + "RXDFETAP5HOLD": "GTXE2_CHANNEL_RXDFETAP5HOLD", + "TXDATA7": "GTXE2_CHANNEL_TXDATA7", + "RXCHBONDO2": "GTXE2_CHANNEL_RXCHBONDO2", + "TXPRECURSOR2": "GTXE2_CHANNEL_TXPRECURSOR2", + "DRPDI11": "GTXE2_CHANNEL_DRPDI11", + "TXDETECTRX": "GTXE2_CHANNEL_TXDETECTRX", + "TXDATA0": "GTXE2_CHANNEL_TXDATA0", + "RXNOTINTABLE5": "GTXE2_CHANNEL_RXNOTINTABLE5", + "DRPADDR3": "GTXE2_CHANNEL_DRPADDR3", + "RXDATA42": "GTXE2_CHANNEL_RXDATA42", + "TXUSRCLK": "GTXE2_CHANNEL_TXUSRCLK", + "TXSYSCLKSEL1": "GTXE2_CHANNEL_TXSYSCLKSEL1", + "TX8B10BBYPASS0": "GTXE2_CHANNEL_TX8B10BBYPASS0", + "RXQPISENP": "GTXE2_CHANNEL_RXQPISENP", + "DRPDI13": "GTXE2_CHANNEL_DRPDI13", + "RXBUFSTATUS2": "GTXE2_CHANNEL_RXBUFSTATUS2", + "RXDISPERR0": "GTXE2_CHANNEL_RXDISPERR0", + "TXDATA46": "GTXE2_CHANNEL_TXDATA46", + "DRPDO1": "GTXE2_CHANNEL_DRPDO1", + "TXDATA15": "GTXE2_CHANNEL_TXDATA15", + "PCSRSVDIN3": "GTXE2_CHANNEL_PCSRSVDIN3", + "RXDLYSRESETDONE": "GTXE2_CHANNEL_RXDLYSRESETDONE", + "PCSRSVDIN1": "GTXE2_CHANNEL_PCSRSVDIN1", + "TXCHARDISPVAL3": "GTXE2_CHANNEL_TXCHARDISPVAL3", + "RXDFELFOVRDEN": "GTXE2_CHANNEL_RXDFELFOVRDEN", + "TXDATA41": "GTXE2_CHANNEL_TXDATA41", + "PCSRSVDOUT13": "GTXE2_CHANNEL_PCSRSVDOUT13", + "RXDATA27": "GTXE2_CHANNEL_RXDATA27", + "RXDATA30": "GTXE2_CHANNEL_RXDATA30", + "RXCHBONDI4": "GTXE2_CHANNEL_RXCHBONDI4", + "EDTSINGLEBYPASSCHAIN": "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", + "RXPRBSERR": "GTXE2_CHANNEL_RXPRBSERR", + "TXCOMWAKE": "GTXE2_CHANNEL_TXCOMWAKE", + "RXRATE0": "GTXE2_CHANNEL_RXRATE0", + "TSTIN4": "GTXE2_CHANNEL_TSTIN4", + "PMARSVDIN4": "GTXE2_CHANNEL_PMARSVDIN4", + "RXOUTCLKSEL2": "GTXE2_CHANNEL_RXOUTCLKSEL2", + "TSTOUT6": "GTXE2_CHANNEL_TSTOUT6", + "RXOOBRESET": "GTXE2_CHANNEL_RXOOBRESET", + "TSTPD4": "GTXE2_CHANNEL_TSTPD4", + "PMASCANRSTEN": "GTXE2_CHANNEL_PMASCANRSTEN", + "DRPDI8": "GTXE2_CHANNEL_DRPDI8", + "RXELECIDLEMODE0": "GTXE2_CHANNEL_RXELECIDLEMODE0", + "RXDATA6": "GTXE2_CHANNEL_RXDATA6", + "TXQPISTRONGPDOWN": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", + "TXHEADER2": "GTXE2_CHANNEL_TXHEADER2", + "PCSRSVDIN6": "GTXE2_CHANNEL_PCSRSVDIN6", + "DMONITOROUT2": "GTXE2_CHANNEL_DMONITOROUT2", + "TXDATA39": "GTXE2_CHANNEL_TXDATA39", + "TXRUNDISP7": "GTXE2_CHANNEL_TXRUNDISP7", + "TXPMARESET": "GTXE2_CHANNEL_TXPMARESET", + "RXDFETAP2OVRDEN": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", + "TX8B10BBYPASS7": "GTXE2_CHANNEL_TX8B10BBYPASS7", + "TSTIN1": "GTXE2_CHANNEL_TSTIN1", + "RXPHSLIPMONITOR0": "GTXE2_CHANNEL_RXPHSLIPMONITOR0", + "DRPDI1": "GTXE2_CHANNEL_DRPDI1", + "RXCDRRESET": "GTXE2_CHANNEL_RXCDRRESET", + "RXCHARISCOMMA1": "GTXE2_CHANNEL_RXCHARISCOMMA1", + "TXPOSTCURSOR2": "GTXE2_CHANNEL_TXPOSTCURSOR2", + "EYESCANDATAERROR": "GTXE2_CHANNEL_EYESCANDATAERROR", + "TXDATA6": "GTXE2_CHANNEL_TXDATA6", + "RXDLYSRESET": "GTXE2_CHANNEL_RXDLYSRESET", + "TXCHARDISPVAL0": "GTXE2_CHANNEL_TXCHARDISPVAL0", + "TXMAINCURSOR2": "GTXE2_CHANNEL_TXMAINCURSOR2", + "EDTBYPASS": "GTXE2_CHANNEL_EDTBYPASS", + "RXDISPERR6": "GTXE2_CHANNEL_RXDISPERR6", + "TXDATA44": "GTXE2_CHANNEL_TXDATA44", + "RXUSRCLK2": "GTXE2_CHANNEL_RXUSRCLK2", + "RXCHBONDI3": "GTXE2_CHANNEL_RXCHBONDI3", + "TSTCLK1": "GTXE2_CHANNEL_TSTCLK1", + "GTREFCLK0": "GTXE2_CHANNEL_GTREFCLK0", + "DRPDO8": "GTXE2_CHANNEL_DRPDO8", + "RXPHMONITOR0": "GTXE2_CHANNEL_RXPHMONITOR0", + "PMARSVDIN22": "GTXE2_CHANNEL_PMARSVDIN22", + "RXCHARISK3": "GTXE2_CHANNEL_RXCHARISK3", + "RXDFEAGCHOLD": "GTXE2_CHANNEL_RXDFEAGCHOLD", + "TXCHARISK2": "GTXE2_CHANNEL_TXCHARISK2", + "PCSRSVDIN23": "GTXE2_CHANNEL_PCSRSVDIN23", + "TSTOUT1": "GTXE2_CHANNEL_TSTOUT1", + "GTRSVD5": "GTXE2_CHANNEL_GTRSVD5", + "RXPHSLIPMONITOR3": "GTXE2_CHANNEL_RXPHSLIPMONITOR3", + "TXCHARDISPMODE4": "GTXE2_CHANNEL_TXCHARDISPMODE4", + "RXHEADER0": "GTXE2_CHANNEL_RXHEADER0", + "DRPDO0": "GTXE2_CHANNEL_DRPDO0", + "TXCHARISK6": "GTXE2_CHANNEL_TXCHARISK6", + "RXCLKCORCNT1": "GTXE2_CHANNEL_RXCLKCORCNT1", + "RXDFEAGCOVRDEN": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", + "TXDATA61": "GTXE2_CHANNEL_TXDATA61", + "RXDFEVSEN": "GTXE2_CHANNEL_RXDFEVSEN", + "DRPDO7": "GTXE2_CHANNEL_DRPDO7", + "PMARSVDIN21": "GTXE2_CHANNEL_PMARSVDIN21", + "PCSRSVDOUT1": "GTXE2_CHANNEL_PCSRSVDOUT1", + "PCSRSVDOUT4": "GTXE2_CHANNEL_PCSRSVDOUT4", + "RXNOTINTABLE4": "GTXE2_CHANNEL_RXNOTINTABLE4", + "RXNOTINTABLE3": "GTXE2_CHANNEL_RXNOTINTABLE3", + "GTRSVD15": "GTXE2_CHANNEL_GTRSVD15", + "TSTIN15": "GTXE2_CHANNEL_TSTIN15", + "DRPDO13": "GTXE2_CHANNEL_DRPDO13", + "RXDATAVALID": "GTXE2_CHANNEL_RXDATAVALID", + "RXDATA19": "GTXE2_CHANNEL_RXDATA19", + "RXBUFRESET": "GTXE2_CHANNEL_RXBUFRESET", + "TXPD0": "GTXE2_CHANNEL_TXPD0", + "PMARSVDIN1": "GTXE2_CHANNEL_PMARSVDIN1", + "RXDATA63": "GTXE2_CHANNEL_RXDATA63", + "TXMAINCURSOR3": "GTXE2_CHANNEL_TXMAINCURSOR3", + "RXDEBUGPULSE": "GTXE2_CHANNEL_RXDEBUGPULSE", + "RXDATA4": "GTXE2_CHANNEL_RXDATA4", + "PMASCANIN1": "GTXE2_CHANNEL_PMASCANIN1", + "TSTIN11": "GTXE2_CHANNEL_TSTIN11", + "CPLLREFCLKSEL2": "GTXE2_CHANNEL_CPLLREFCLKSEL2", + "SCANOUT1": "GTXE2_CHANNEL_SCANOUT1", + "TXRUNDISP2": "GTXE2_CHANNEL_TXRUNDISP2", + "PCSRSVDIN13": "GTXE2_CHANNEL_PCSRSVDIN13", + "SCANMODEB": "GTXE2_CHANNEL_SCANMODEB", + "GTRXRESET": "GTXE2_CHANNEL_GTRXRESET", + "PCSRSVDIN22": "GTXE2_CHANNEL_PCSRSVDIN22", + "TXDATA3": "GTXE2_CHANNEL_TXDATA3", + "TXMAINCURSOR5": "GTXE2_CHANNEL_TXMAINCURSOR5", + "GTRSVD2": "GTXE2_CHANNEL_GTRSVD2", + "CLKRSVD1": "GTXE2_CHANNEL_CLKRSVD1", + "TXOUTCLKSEL0": "GTXE2_CHANNEL_TXOUTCLKSEL0", + "TXDATA57": "GTXE2_CHANNEL_TXDATA57", + "TXPDELECIDLEMODE": "GTXE2_CHANNEL_TXPDELECIDLEMODE", + "PCSRSVDIN21": "GTXE2_CHANNEL_PCSRSVDIN21", + "TSTOUT3": "GTXE2_CHANNEL_TSTOUT3", + "PCSRSVDOUT15": "GTXE2_CHANNEL_PCSRSVDOUT15", + "TXSEQUENCE3": "GTXE2_CHANNEL_TXSEQUENCE3", + "TSTIN18": "GTXE2_CHANNEL_TSTIN18", + "TXRATE1": "GTXE2_CHANNEL_TXRATE1", + "TXSEQUENCE4": "GTXE2_CHANNEL_TXSEQUENCE4", + "RXSTARTOFSEQ": "GTXE2_CHANNEL_RXSTARTOFSEQ", + "RXPHALIGN": "GTXE2_CHANNEL_RXPHALIGN", + "RXDFEUTHOLD": "GTXE2_CHANNEL_RXDFEUTHOLD", + "DRPDI14": "GTXE2_CHANNEL_DRPDI14", + "TXRATEDONE": "GTXE2_CHANNEL_TXRATEDONE", + "TXDIFFPD": "GTXE2_CHANNEL_TXDIFFPD", + "TXCHARDISPVAL1": "GTXE2_CHANNEL_TXCHARDISPVAL1", + "RXDFELPMRESET": "GTXE2_CHANNEL_RXDFELPMRESET", + "RXCDRLOCK": "GTXE2_CHANNEL_RXCDRLOCK", + "TXDATA31": "GTXE2_CHANNEL_TXDATA31", + "RXCHARISK0": "GTXE2_CHANNEL_RXCHARISK0", + "RXDATA43": "GTXE2_CHANNEL_RXDATA43", + "TXDATA55": "GTXE2_CHANNEL_TXDATA55", + "TSTIN9": "GTXE2_CHANNEL_TSTIN9", + "TXQPIWEAKPUP": "GTXE2_CHANNEL_TXQPIWEAKPUP", + "TXDATA4": "GTXE2_CHANNEL_TXDATA4", + "RXSYSCLKSEL0": "GTXE2_CHANNEL_RXSYSCLKSEL0", + "DRPDO14": "GTXE2_CHANNEL_DRPDO14", + "TSTIN12": "GTXE2_CHANNEL_TSTIN12", + "DRPDI7": "GTXE2_CHANNEL_DRPDI7", + "TXSEQUENCE0": "GTXE2_CHANNEL_TXSEQUENCE0", + "RXDISPERR7": "GTXE2_CHANNEL_RXDISPERR7", + "CPLLLOCKDETCLK": "GTXE2_CHANNEL_CPLLLOCKDETCLK", + "DRPADDR4": "GTXE2_CHANNEL_DRPADDR4", + "RXCOMMADETEN": "GTXE2_CHANNEL_RXCOMMADETEN", + "DRPADDR2": "GTXE2_CHANNEL_DRPADDR2", + "TXPRECURSOR0": "GTXE2_CHANNEL_TXPRECURSOR0", + "PCSRSVDOUT7": "GTXE2_CHANNEL_PCSRSVDOUT7", + "RXPHSLIPMONITOR4": "GTXE2_CHANNEL_RXPHSLIPMONITOR4", + "TXPHINIT": "GTXE2_CHANNEL_TXPHINIT", + "DRPADDR5": "GTXE2_CHANNEL_DRPADDR5", + "TXDATA50": "GTXE2_CHANNEL_TXDATA50", + "PMASCANIN4": "GTXE2_CHANNEL_PMASCANIN4", + "TXPRECURSOR4": "GTXE2_CHANNEL_TXPRECURSOR4", + "PMASCANCLK1": "GTXE2_CHANNEL_PMASCANCLK1", + "TXPRBSSEL1": "GTXE2_CHANNEL_TXPRBSSEL1", + "GTRSVD11": "GTXE2_CHANNEL_GTRSVD11", + "DRPDO10": "GTXE2_CHANNEL_DRPDO10", + "TXDATA12": "GTXE2_CHANNEL_TXDATA12", + "RXDATA5": "GTXE2_CHANNEL_RXDATA5", + "TXCOMFINISH": "GTXE2_CHANNEL_TXCOMFINISH", + "TXDATA17": "GTXE2_CHANNEL_TXDATA17", + "GTTXRESET": "GTXE2_CHANNEL_GTTXRESET", + "PMASCANCLK3": "GTXE2_CHANNEL_PMASCANCLK3", + "TXDIFFCTRL1": "GTXE2_CHANNEL_TXDIFFCTRL1", + "TXPHDLYRESET": "GTXE2_CHANNEL_TXPHDLYRESET", + "RXDATA13": "GTXE2_CHANNEL_RXDATA13", + "TXDATA9": "GTXE2_CHANNEL_TXDATA9", + "PCSRSVDIN4": "GTXE2_CHANNEL_PCSRSVDIN4", + "DMONITOROUT7": "GTXE2_CHANNEL_DMONITOROUT7", + "TSTIN5": "GTXE2_CHANNEL_TSTIN5", + "RXDISPERR4": "GTXE2_CHANNEL_RXDISPERR4", + "TXDATA40": "GTXE2_CHANNEL_TXDATA40", + "TXDATA49": "GTXE2_CHANNEL_TXDATA49", + "PMARSVDIN3": "GTXE2_CHANNEL_PMARSVDIN3", + "RXDATA23": "GTXE2_CHANNEL_RXDATA23", + "TXMARGIN1": "GTXE2_CHANNEL_TXMARGIN1", + "TXDLYBYPASS": "GTXE2_CHANNEL_TXDLYBYPASS", + "PCSRSVDOUT0": "GTXE2_CHANNEL_PCSRSVDOUT0", + "TXOUTCLK": "GTXE2_CHANNEL_GTTXOUTCLK_0", + "RXLPMHFHOLD": "GTXE2_CHANNEL_RXLPMHFHOLD", + "RXDFEXYDEN": "GTXE2_CHANNEL_RXDFEXYDEN", + "TSTOUT9": "GTXE2_CHANNEL_TSTOUT9", + "TXDLYEN": "GTXE2_CHANNEL_TXDLYEN", + "RXUSRCLK": "GTXE2_CHANNEL_RXUSRCLK", + "RXDFEXYDHOLD": "GTXE2_CHANNEL_RXDFEXYDHOLD", + "TSTIN13": "GTXE2_CHANNEL_TSTIN13", + "TXPRBSFORCEERR": "GTXE2_CHANNEL_TXPRBSFORCEERR", + "CLKRSVD0": "GTXE2_CHANNEL_CLKRSVD0", + "RXPCD1DONE": "GTXE2_CHANNEL_RXPCD1DONE", + "DRPRDY": "GTXE2_CHANNEL_DRPRDY", + "RXDFEXYDOVRDEN": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", + "LOOPBACK1": "GTXE2_CHANNEL_LOOPBACK1", + "GTGREFCLK": "GTXE2_CHANNEL_GTGREFCLK", + "RXHEADER1": "GTXE2_CHANNEL_RXHEADER1", + "GTRSVD1": "GTXE2_CHANNEL_GTRSVD1", + "TXMAINCURSOR6": "GTXE2_CHANNEL_TXMAINCURSOR6", + "RXDATA17": "GTXE2_CHANNEL_RXDATA17", + "RXDATA22": "GTXE2_CHANNEL_RXDATA22", + "PCSRSVDOUT3": "GTXE2_CHANNEL_PCSRSVDOUT3", + "DRPDI0": "GTXE2_CHANNEL_DRPDI0", + "RXCHARISCOMMA5": "GTXE2_CHANNEL_RXCHARISCOMMA5", + "TXDATA58": "GTXE2_CHANNEL_TXDATA58", + "QPLLCLK": "GTXE2_CHANNEL_GTQPLLCLK", + "RXDDIEN": "GTXE2_CHANNEL_RXDDIEN", + "GTXTXP": "GTXE2_CHANNEL_TXP", + "PMASCANENB": "GTXE2_CHANNEL_PMASCANENB", + "TXDATA59": "GTXE2_CHANNEL_TXDATA59", + "GTRSVD10": "GTXE2_CHANNEL_GTRSVD10", + "RXDATA12": "GTXE2_CHANNEL_RXDATA12", + "RXCDROVRDEN": "GTXE2_CHANNEL_RXCDROVRDEN", + "TSTIN16": "GTXE2_CHANNEL_TSTIN16", + "TXDATA27": "GTXE2_CHANNEL_TXDATA27" + }, + "x_coord": 0 + }, + { + "y_coord": 26, + "name": "X0Y26", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "GTXE2_CHANNEL_RXN_PAD" + }, + "x_coord": 0 + }, + { + "y_coord": 27, + "name": "X0Y27", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "GTXE2_CHANNEL_RXP_PAD" + }, + "x_coord": 0 + }, + { + "y_coord": 4, + "name": "X0Y4", + "prefix": "OPAD", + "type": "OPAD", + "site_pins": { + "I": "GTXE2_CHANNEL_TXN_PAD" + }, + "x_coord": 0 + }, + { + "y_coord": 5, + "name": "X0Y5", + "prefix": "OPAD", + "type": "OPAD", + "site_pins": { + "I": "GTXE2_CHANNEL_TXP_PAD" + }, + "x_coord": 0 + } + ], + "wires": [ + "GTXE2_CHANNEL_PMASCANIN2", + "GTXE2_CHANNEL_RXDFETAP3HOLD", + "GTXE2_CHANNEL_GTTXOUTCLK_0", + "GTXE2_CHANNEL_RXHEADER0", + "GTXE2_IMUX29_3", + "GTXE2_LOGIC_OUTS_B21_5", + "GTXE2_CHANNEL_TXQPISENN", + "GTXE2_IMUX42_5", + "GTXE2_CHANNEL_TXDATA44", + "GTXE2_FAN2_6", + "GTXE2_IMUX23_5", + "GTXE2_LOGIC_OUTS_B19_1", + "GTXE2_CHANNEL_GTREFCLKMONITOR", + "GTXE2_CHANNEL_CPLLREFCLKSEL1", + "GTXE2_IMUX29_9", + "GTXE2_FAN5_4", + "GTXE2_LOGIC_OUTS_B23_10", + "GTXE2_CHANNEL_RXBUFSTATUS0", + "GTXE2_CHANNEL_PCSRSVDOUT13", + "GTXE2_CHANNEL_RXNOTINTABLE5", + "GTXE2_IMUX46_0", + "GTXE2_IMUX20_7", + "GTXE2_CHANNEL_DRPDI6", + "GTXE2_BYP2_3", + "GTXE2_CHANNEL_RXCHARISK4", + "GTXE2_CHANNEL_TXDIFFPD", + "GTXE2_IMUX4_4", + "GTXE2_IMUX6_0", + "GTXE2_IMUX25_4", + "GTXE2_IMUX3_2", + "GTXE2_CHANNEL_TSTIN11", + "GTXE2_CHANNEL_TSTIN8", + "GTXE2_IMUX31_7", + "GTXE2_CHANNEL_CPLLFBCLKLOST", + "GTXE2_IMUX41_9", + "GTXE2_CHANNEL_RXDLYEN", + "GTXE2_CHANNEL_RXCHARISK6", + "GTXE2_CHANNEL_GTQPLLREFCLK", + "GTXE2_CHANNEL_RXDISPERR7", + "GTXE2_CHANNEL_TXDLYBYPASS", + "GTXE2_CHANNEL_NORTHREFCLK1", + "GTXE2_IMUX26_0", + "GTXE2_CHANNEL_TXCHARDISPMODE0", + "GTXE2_LOGIC_OUTS_B23_6", + "GTXE2_CHANNEL_PCSRSVDIN24", + "GTXE2_IMUX9_2", + "GTXE2_LOGIC_OUTS_B19_2", + "GTXE2_LOGIC_OUTS_B22_8", + "GTXE2_LOGIC_OUTS_B4_1", + "GTXE2_FAN7_10", + "GTXE2_CHANNEL_RXDATA35", + "GTXE2_IMUX35_10", + "GTXE2_IMUX33_8", + "GTXE2_IMUX42_8", + "GTXE2_FAN3_8", + "GTXE2_BYP0_5", + "GTXE2_CHANNEL_PCSRSVDOUT5", + "GTXE2_CTRL0_4", + "GTXE2_CHANNEL_TXDATA24", + "GTXE2_BYP7_7", + "GTXE2_IMUX7_2", + "GTXE2_IMUX30_8", + "GTXE2_FAN5_10", + "GTXE2_IMUX15_9", + "GTXE2_CHANNEL_RXHEADERVALID", + "GTXE2_BYP1_10", + "GTXE2_CHANNEL_CPLLPD", + "GTXE2_CHANNEL_RXDFETAP2OVRDEN", + "GTXE2_CHANNEL_RXBYTEISALIGNED", + "GTXE2_LOGIC_OUTS_B2_1", + "GTXE2_CHANNEL_TXDATA48", + "GTXE2_CHANNEL_TXDATA32", + "GTXE2_CHANNEL_RXCHBONDO2", + "GTXE2_CHANNEL_PMASCANCLK1", + "GTXE2_CHANNEL_TXDLYSRESET", + "GTXE2_IMUX35_9", + "GTXE2_LOGIC_OUTS_B9_7", + "GTXE2_IMUX43_0", + "GTXE2_IMUX23_7", + "GTXE2_CHANNEL_PMASCANCLK3", + "GTXE2_FAN1_9", + "GTXE2_CHANNEL_CPLLREFCLKSEL0", + "GTXE2_IMUX26_9", + "GTXE2_LOGIC_OUTS_B1_4", + "GTXE2_CHANNEL_TXDATA29", + "GTXE2_LOGIC_OUTS_B20_8", + "GTXE2_FAN3_9", + "GTXE2_IMUX18_7", + "GTXE2_LOGIC_OUTS_B12_4", + "GTXE2_CHANNEL_TXCHARISK7", + "GTXE2_LOGIC_OUTS_B1_9", + "GTXE2_CHANNEL_RXDATA28", + "GTXE2_CHANNEL_RXMCOMMAALIGNEN", + "GTXE2_IMUX47_8", + "GTXE2_CHANNEL_RXCHBONDMASTER", + "GTXE2_CHANNEL_TXCHARDISPVAL5", + "GTXE2_IMUX19_6", + "GTXE2_IMUX10_4", + "GTXE2_FAN5_3", + "GTXE2_CHANNEL_RXPHSLIPMONITOR4", + "GTXE2_FAN1_8", + "GTXE2_CHANNEL_TXCHARISK3", + "GTXE2_BYP1_4", + "GTXE2_FAN0_6", + "GTXE2_CHANNEL_DRPADDR4", + "GTXE2_CHANNEL_RXPRBSSEL2", + "GTXE2_IMUX1_3", + "GTXE2_IMUX1_5", + "GTXE2_IMUX31_10", + "GTXE2_LOGIC_OUTS_B15_9", + "GTXE2_CHANNEL_RXN", + "GTXE2_CHANNEL_TXDEEMPH", + "GTXE2_CHANNEL_TSTIN6", + "GTXE2_CHANNEL_PMASCANRSTEN", + "GTXE2_CHANNEL_LOOPBACK1", + "GTXE2_CHANNEL_TXOUTCLK_0", + "GTXE2_BYP1_2", + "GTXE2_CHANNEL_TXDATA63", + "GTXE2_IMUX6_2", + "GTXE2_LOGIC_OUTS_B23_5", + "GTXE2_CHANNEL_RXDATA15", + "GTXE2_CHANNEL_TXCHARDISPMODE5", + "GTXE2_LOGIC_OUTS_B7_9", + "GTXE2_CHANNEL_RXCDRRESET", + "GTXE2_CHANNEL_TSTIN4", + "GTXE2_CHANNEL_RXOOBRESET", + "GTXE2_FAN7_6", + "GTXE2_CTRL0_7", + "GTXE2_IMUX37_2", + "GTXE2_CHANNEL_RXDATA50", + "GTXE2_CHANNEL_TXDATA36", + "GTXE2_IMUX45_0", + "GTXE2_BYP4_7", + "GTXE2_FAN7_0", + "GTXE2_LOGIC_OUTS_B19_6", + "GTXE2_CHANNEL_RXDATA54", + "GTXE2_CHANNEL_RXCOMMADET", + "GTXE2_CLK1_7", + "GTXE2_IMUX46_1", + "GTXE2_CHANNEL_RXQPIEN", + "GTXE2_CHANNEL_RXSTATUS2", + "GTXE2_IMUX30_2", + "GTXE2_CHANNEL_RXOUTCLKSEL2", + "GTXE2_BYP5_5", + "GTXE2_IMUX22_4", + "GTXE2_BYP2_0", + "GTXE2_IMUX35_1", + "GTXE2_CHANNEL_RXDATA17", + "GTXE2_IMUX15_0", + "GTXE2_BYP5_3", + "GTXE2_LOGIC_OUTS_B6_7", + "GTXE2_CHANNEL_RXCOMWAKEDET", + "GTXE2_LOGIC_OUTS_B3_0", + "GTXE2_BYP1_1", + "GTXE2_LOGIC_OUTS_B3_1", + "GTXE2_IMUX24_4", + "GTXE2_FAN1_5", + "GTXE2_IMUX44_0", + "GTXE2_LOGIC_OUTS_B5_3", + "GTXE2_CHANNEL_RXSTATUS1", + "GTXE2_CHANNEL_RXDATA62", + "GTXE2_BYP0_7", + "GTXE2_LOGIC_OUTS_B19_10", + "GTXE2_CLK1_9", + "GTXE2_CHANNEL_PCSRSVDIN7", + "GTXE2_LOGIC_OUTS_B7_7", + "GTXE2_CHANNEL_TXDATA28", + "GTXE2_IMUX22_10", + "GTXE2_LOGIC_OUTS_B21_3", + "GTXE2_FAN5_8", + "GTXE2_IMUX39_5", + "GTXE2_IMUX22_1", + "GTXE2_CHANNEL_PMARSVDIN24", + "GTXE2_CHANNEL_RXCHBONDI3", + "GTXE2_IMUX8_8", + "GTXE2_IMUX44_2", + "GTXE2_LOGIC_OUTS_B11_4", + "GTXE2_CHANNEL_TSTIN19", + "GTXE2_IMUX23_0", + "GTXE2_CHANNEL_TXDATA13", + "GTXE2_LOGIC_OUTS_B21_8", + "GTXE2_IMUX44_9", + "GTXE2_CHANNEL_GTRSVD0", + "GTXE2_CHANNEL_DRPCLK", + "GTXE2_CHANNEL_GTRSVD13", + "GTXE2_BYP5_8", + "GTXE2_IMUX11_9", + "GTXE2_LOGIC_OUTS_B8_6", + "GTXE2_CHANNEL_RXCHARISCOMMA4", + "GTXE2_IMUX42_2", + "GTXE2_IMUX41_10", + "GTXE2_CHANNEL_TSTPD2", + "GTXE2_CHANNEL_TXPRECURSOR2", + "GTXE2_LOGIC_OUTS_B11_9", + "GTXE2_IMUX2_7", + "GTXE2_CHANNEL_TXDATA19", + "GTXE2_IMUX1_4", + "GTXE2_CHANNEL_TXSEQUENCE6", + "GTXE2_IMUX31_3", + "GTXE2_LOGIC_OUTS_B23_9", + "GTXE2_LOGIC_OUTS_B10_8", + "GTXE2_CHANNEL_CLKRSVD2", + "GTXE2_CLK1_10", + "GTXE2_IMUX13_9", + "GTXE2_IMUX21_10", + "GTXE2_BYP7_10", + "GTXE2_CTRL0_8", + "GTXE2_CHANNEL_TXPHDLYRESET", + "GTXE2_BYP7_2", + "GTXE2_CHANNEL_PCSRSVDOUT15", + "GTXE2_BYP6_8", + "GTXE2_CHANNEL_TXDATA16", + "GTXE2_IMUX11_8", + "GTXE2_CHANNEL_TXMAINCURSOR1", + "GTXE2_CHANNEL_PCSRSVDOUT11", + "GTXE2_IMUX22_8", + "GTXE2_IMUX17_1", + "GTXE2_FAN3_10", + "GTXE2_CHANNEL_TXRUNDISP5", + "GTXE2_CHANNEL_TXPOSTCURSOR0", + "GTXE2_IMUX21_0", + "GTXE2_CTRL1_7", + "GTXE2_CHANNEL_RXOUTCLKFABRIC", + "GTXE2_IMUX45_8", + "GTXE2_CHANNEL_RXCHBONDO4", + "GTXE2_LOGIC_OUTS_B20_0", + "GTXE2_BYP6_5", + "GTXE2_IMUX33_10", + "GTXE2_IMUX46_3", + "GTXE2_IMUX8_7", + "GTXE2_CHANNEL_RXOSHOLD", + "GTXE2_BYP2_10", + "GTXE2_CHANNEL_TXDATA8", + "GTXE2_CHANNEL_RXCHARISK2", + "GTXE2_CHANNEL_DRPDO10", + "GTXE2_LOGIC_OUTS_B17_9", + "GTXE2_IMUX9_1", + "GTXE2_IMUX12_1", + "GTXE2_IMUX0_10", + "GTXE2_CHANNEL_RXELECIDLE", + "GTXE2_CHANNEL_DRPDI10", + "GTXE2_FAN7_1", + "GTXE2_CHANNEL_RXDATA42", + "GTXE2_CHANNEL_TXCHARDISPMODE6", + "GTXE2_IMUX5_8", + "GTXE2_LOGIC_OUTS_B5_8", + "GTXE2_CHANNEL_TXQPISENP", + "GTXE2_CHANNEL_RXDATA21", + "GTXE2_CHANNEL_TXPOSTCURSORINV", + "GTXE2_LOGIC_OUTS_B9_0", + "GTXE2_IMUX0_5", + "GTXE2_BYP1_7", + "GTXE2_FAN4_9", + "GTXE2_IMUX25_10", + "GTXE2_CHANNEL_RXELECIDLEMODE0", + "GTXE2_LOGIC_OUTS_B20_10", + "GTXE2_CHANNEL_RXDATA39", + "GTXE2_CHANNEL_TXPHOVRDEN", + "GTXE2_IMUX22_3", + "GTXE2_CHANNEL_PMARSVDIN22", + "GTXE2_IMUX36_2", + "GTXE2_FAN6_3", + "GTXE2_CHANNEL_GTRSVD5", + "GTXE2_LOGIC_OUTS_B3_2", + "GTXE2_IMUX2_5", + "GTXE2_IMUX33_4", + "GTXE2_CHANNEL_DMONITOROUT4", + "GTXE2_IMUX40_3", + "GTXE2_CHANNEL_DMONITOROUT5", + "GTXE2_CHANNEL_TXRUNDISP4", + "GTXE2_CHANNEL_DRPADDR8", + "GTXE2_IMUX27_4", + "GTXE2_IMUX36_3", + "GTXE2_LOGIC_OUTS_B8_10", + "GTXE2_IMUX31_9", + "GTXE2_LOGIC_OUTS_B16_0", + "GTXE2_IMUX11_0", + "GTXE2_CHANNEL_PCSRSVDOUT1", + "GTXE2_IMUX24_1", + "GTXE2_FAN3_0", + "GTXE2_CHANNEL_RXVALID", + "GTXE2_IMUX5_7", + "GTXE2_BYP6_10", + "GTXE2_CHANNEL_PCSRSVDIN6", + "GTXE2_IMUX23_6", + "GTXE2_CHANNEL_RXNOTINTABLE1", + "GTXE2_CHANNEL_DRPRDY", + "GTXE2_IMUX1_10", + "GTXE2_IMUX25_8", + "GTXE2_LOGIC_OUTS_B14_4", + "GTXE2_CHANNEL_TXSWING", + "GTXE2_IMUX28_8", + "GTXE2_IMUX28_7", + "GTXE2_CHANNEL_PCSRSVDOUT14", + "GTXE2_CHANNEL_TXCOMWAKE", + "GTXE2_IMUX3_3", + "GTXE2_IMUX10_6", + "GTXE2_CHANNEL_TXPHDLYPD", + "GTXE2_CHANNEL_TSTIN7", + "GTXE2_CHANNEL_RESETOVRD", + "GTXE2_IMUX10_0", + "GTXE2_IMUX3_1", + "GTXE2_LOGIC_OUTS_B19_7", + "GTXE2_CHANNEL_DRPDO6", + "GTXE2_CHANNEL_RXDFEVPOVRDEN", + "GTXE2_IMUX37_6", + "GTXE2_IMUX16_9", + "GTXE2_BYP3_6", + "GTXE2_BYP7_5", + "GTXE2_CHANNEL_RXPD0", + "GTXE2_LOGIC_OUTS_B12_5", + "GTXE2_LOGIC_OUTS_B3_3", + "GTXE2_IMUX12_10", + "GTXE2_CHANNEL_RXP_PAD", + "GTXE2_IMUX14_1", + "GTXE2_CHANNEL_TXDATA40", + "GTXE2_IMUX32_8", + "GTXE2_IMUX12_5", + "GTXE2_LOGIC_OUTS_B13_1", + "GTXE2_LOGIC_OUTS_B8_4", + "GTXE2_LOGIC_OUTS_B17_0", + "GTXE2_IMUX44_8", + "GTXE2_CTRL1_1", + "GTXE2_LOGIC_OUTS_B7_1", + "GTXE2_IMUX4_10", + "GTXE2_CHANNEL_DMONITOROUT6", + "GTXE2_CHANNEL_TXDATA3", + "GTXE2_CHANNEL_RXBUFSTATUS2", + "GTXE2_CHANNEL_RXDFEVPHOLD", + "GTXE2_LOGIC_OUTS_B5_4", + "GTXE2_IMUX14_10", + "GTXE2_IMUX27_2", + "GTXE2_IMUX13_8", + "GTXE2_LOGIC_OUTS_B16_6", + "GTXE2_IMUX15_5", + "GTXE2_LOGIC_OUTS_B2_10", + "GTXE2_IMUX41_2", + "GTXE2_CHANNEL_TXRUNDISP2", + "GTXE2_LOGIC_OUTS_B10_1", + "GTXE2_CHANNEL_SCANIN0", + "GTXE2_IMUX23_4", + "GTXE2_CLK1_5", + "GTXE2_IMUX6_9", + "GTXE2_IMUX21_3", + "GTXE2_IMUX11_4", + "GTXE2_IMUX25_9", + "GTXE2_CHANNEL_TXQPISTRONGPDOWN", + "GTXE2_BYP5_7", + "GTXE2_IMUX47_10", + "GTXE2_IMUX22_6", + "GTXE2_CHANNEL_SCANENB", + "GTXE2_CHANNEL_NORTHREFCLK0", + "GTXE2_CHANNEL_RXPHMONITOR0", + "GTXE2_LOGIC_OUTS_B15_1", + "GTXE2_CHANNEL_RXCHANREALIGN", + "GTXE2_CHANNEL_DMONITOROUT2", + "GTXE2_IMUX40_2", + "GTXE2_IMUX39_6", + "GTXE2_CHANNEL_RXCOMSASDET", + "GTXE2_CTRL1_10", + "GTXE2_CHANNEL_TXDATA59", + "GTXE2_IMUX21_6", + "GTXE2_IMUX22_9", + "GTXE2_LOGIC_OUTS_B11_10", + "GTXE2_IMUX1_0", + "GTXE2_LOGIC_OUTS_B0_5", + "GTXE2_FAN5_9", + "GTXE2_LOGIC_OUTS_B22_3", + "GTXE2_FAN5_5", + "GTXE2_FAN4_3", + "GTXE2_LOGIC_OUTS_B1_0", + "GTXE2_LOGIC_OUTS_B9_5", + "GTXE2_CHANNEL_RXCHBONDEN", + "GTXE2_LOGIC_OUTS_B6_6", + "GTXE2_CHANNEL_TXPRBSSEL0", + "GTXE2_BYP0_0", + "GTXE2_IMUX17_10", + "GTXE2_LOGIC_OUTS_B12_2", + "GTXE2_IMUX27_1", + "GTXE2_IMUX12_9", + "GTXE2_IMUX28_4", + "GTXE2_LOGIC_OUTS_B16_3", + "GTXE2_LOGIC_OUTS_B19_5", + "GTXE2_CHANNEL_TXHEADER1", + "GTXE2_IMUX11_7", + "GTXE2_LOGIC_OUTS_B15_4", + "GTXE2_IMUX19_4", + "GTXE2_IMUX32_2", + "GTXE2_LOGIC_OUTS_B12_1", + "GTXE2_CHANNEL_TXCHARDISPMODE2", + "GTXE2_IMUX30_3", + "GTXE2_CHANNEL_RXUSRCLK", + "GTXE2_CHANNEL_TSTCLK0", + "GTXE2_CHANNEL_DRPDI9", + "GTXE2_CHANNEL_TXDATA9", + "GTXE2_LOGIC_OUTS_B21_2", + "GTXE2_IMUX19_5", + "GTXE2_IMUX27_5", + "GTXE2_FAN0_8", + "GTXE2_CHANNEL_DRPDI13", + "GTXE2_FAN2_5", + "GTXE2_CHANNEL_RXDFEVSEN", + "GTXE2_IMUX37_7", + "GTXE2_LOGIC_OUTS_B23_2", + "GTXE2_IMUX2_2", + "GTXE2_CHANNEL_TX8B10BBYPASS6", + "GTXE2_CHANNEL_TXPOSTCURSOR1", + "GTXE2_CHANNEL_RXDATAVALID", + "GTXE2_CHANNEL_TXDATA31", + "GTXE2_CHANNEL_TXPHDLYTSTCLK", + "GTXE2_CHANNEL_TXCHARISK0", + "GTXE2_LOGIC_OUTS_B3_10", + "GTXE2_CHANNEL_PMARSVDIN3", + "GTXE2_IMUX34_5", + "GTXE2_CHANNEL_TXDATA6", + "GTXE2_CHANNEL_RXPRBSCNTRESET", + "GTXE2_IMUX3_7", + "GTXE2_CHANNEL_TXRUNDISP1", + "GTXE2_IMUX40_0", + "GTXE2_IMUX9_5", + "GTXE2_IMUX4_5", + "GTXE2_FAN6_9", + "GTXE2_CHANNEL_TSTIN0", + "GTXE2_FAN4_0", + "GTXE2_CHANNEL_TXDATA14", + "GTXE2_CHANNEL_TSTIN9", + "GTXE2_LOGIC_OUTS_B4_4", + "GTXE2_CHANNEL_GTRXOUTCLK_0", + "GTXE2_BYP0_3", + "GTXE2_FAN3_5", + "GTXE2_CHANNEL_TSTIN12", + "GTXE2_CHANNEL_TXCHARISK1", + "GTXE2_IMUX40_9", + "GTXE2_CHANNEL_TXDATA10", + "GTXE2_CHANNEL_RXNOTINTABLE6", + "GTXE2_IMUX39_3", + "GTXE2_LOGIC_OUTS_B4_7", + "GTXE2_IMUX43_7", + "GTXE2_CHANNEL_TXBUFDIFFCTRL2", + "GTXE2_IMUX5_4", + "GTXE2_CHANNEL_TXDATA30", + "GTXE2_IMUX39_1", + "GTXE2_CHANNEL_CPLLREFCLKLOST", + "GTXE2_CTRL0_9", + "GTXE2_LOGIC_OUTS_B21_7", + "GTXE2_CHANNEL_GTREFCLK1", + "GTXE2_BYP0_8", + "GTXE2_CHANNEL_DRPDI14", + "GTXE2_IMUX33_2", + "GTXE2_LOGIC_OUTS_B11_5", + "GTXE2_IMUX17_4", + "GTXE2_CHANNEL_TXDATA0", + "GTXE2_CHANNEL_EYESCANMODE", + "GTXE2_LOGIC_OUTS_B4_2", + "GTXE2_CHANNEL_SCANOUT3", + "GTXE2_IMUX13_2", + "GTXE2_IMUX19_9", + "GTXE2_LOGIC_OUTS_B9_1", + "GTXE2_CHANNEL_GTRSVD11", + "GTXE2_IMUX10_8", + "GTXE2_LOGIC_OUTS_B18_1", + "GTXE2_CHANNEL_RXDDIEN", + "GTXE2_IMUX5_1", + "GTXE2_IMUX35_5", + "GTXE2_IMUX32_6", + "GTXE2_IMUX40_8", + "GTXE2_CTRL1_2", + "GTXE2_LOGIC_OUTS_B6_2", + "GTXE2_LOGIC_OUTS_B16_8", + "GTXE2_IMUX40_10", + "GTXE2_CHANNEL_PMASCANCLK2", + "GTXE2_LOGIC_OUTS_B2_4", + "GTXE2_CHANNEL_PCSRSVDIN22", + "GTXE2_IMUX9_7", + "GTXE2_CHANNEL_DRPDI8", + "GTXE2_CHANNEL_TXPHINITDONE", + "GTXE2_FAN5_2", + "GTXE2_CHANNEL_LOOPBACK0", + "GTXE2_IMUX29_8", + "GTXE2_LOGIC_OUTS_B17_7", + "GTXE2_LOGIC_OUTS_B11_3", + "GTXE2_CHANNEL_CPLLLOCK", + "GTXE2_CHANNEL_RXDFETAP4OVRDEN", + "GTXE2_IMUX0_8", + "GTXE2_BYP4_4", + "GTXE2_LOGIC_OUTS_B10_9", + "GTXE2_CHANNEL_RXBUFRESET", + "GTXE2_IMUX12_2", + "GTXE2_CHANNEL_PCSRSVDOUT7", + "GTXE2_LOGIC_OUTS_B9_9", + "GTXE2_IMUX5_10", + "GTXE2_LOGIC_OUTS_B20_5", + "GTXE2_CHANNEL_PCSRSVDIN23", + "GTXE2_IMUX8_2", + "GTXE2_CHANNEL_TXDATA42", + "GTXE2_IMUX46_2", + "GTXE2_IMUX40_6", + "GTXE2_IMUX33_1", + "GTXE2_FAN6_0", + "GTXE2_LOGIC_OUTS_B11_7", + "GTXE2_BYP2_8", + "GTXE2_IMUX47_0", + "GTXE2_FAN0_3", + "GTXE2_CHANNEL_RXPHDLYRESET", + "GTXE2_LOGIC_OUTS_B11_6", + "GTXE2_LOGIC_OUTS_B8_3", + "GTXE2_IMUX36_4", + "GTXE2_CHANNEL_GTRESETSEL", + "GTXE2_CHANNEL_GTGREFCLK", + "GTXE2_LOGIC_OUTS_B11_0", + "GTXE2_LOGIC_OUTS_B5_9", + "GTXE2_IMUX34_2", + "GTXE2_IMUX8_3", + "GTXE2_LOGIC_OUTS_B14_1", + "GTXE2_LOGIC_OUTS_B18_6", + "GTXE2_CHANNEL_GTRSVD15", + "GTXE2_CHANNEL_RXDATA7", + "GTXE2_LOGIC_OUTS_B3_6", + "GTXE2_CHANNEL_RXCHARISK0", + "GTXE2_IMUX4_3", + "GTXE2_IMUX16_1", + "GTXE2_CHANNEL_RXDATA11", + "GTXE2_CHANNEL_TX8B10BBYPASS2", + "GTXE2_IMUX19_10", + "GTXE2_CHANNEL_TXDATA61", + "GTXE2_CHANNEL_RXDATA19", + "GTXE2_BYP5_10", + "GTXE2_IMUX20_1", + "GTXE2_IMUX16_6", + "GTXE2_IMUX26_7", + "GTXE2_CHANNEL_PMASCANOUT2", + "GTXE2_CHANNEL_TSTIN2", + "GTXE2_IMUX1_2", + "GTXE2_BYP4_3", + "GTXE2_LOGIC_OUTS_B18_7", + "GTXE2_CHANNEL_PCSRSVDIN21", + "GTXE2_CHANNEL_RXDISPERR3", + "GTXE2_IMUX40_5", + "GTXE2_FAN3_6", + "GTXE2_IMUX20_3", + "GTXE2_FAN7_2", + "GTXE2_CHANNEL_RXDLYTESTENB", + "GTXE2_FAN4_7", + "GTXE2_FAN2_0", + "GTXE2_IMUX32_9", + "GTXE2_IMUX30_9", + "GTXE2_IMUX32_4", + "GTXE2_CHANNEL_GTRSVD10", + "GTXE2_IMUX30_1", + "GTXE2_CHANNEL_DRPDO15", + "GTXE2_CHANNEL_TXDLYSRESETDONE", + "GTXE2_FAN2_3", + "GTXE2_IMUX30_5", + "GTXE2_LOGIC_OUTS_B6_4", + "GTXE2_CHANNEL_TXPOLARITY", + "GTXE2_CHANNEL_GTRSVD8", + "GTXE2_CHANNEL_TXDATA43", + "GTXE2_IMUX43_5", + "GTXE2_LOGIC_OUTS_B18_5", + "GTXE2_BYP3_0", + "GTXE2_BYP6_2", + "GTXE2_CHANNEL_TXDATA57", + "GTXE2_IMUX27_9", + "GTXE2_CHANNEL_DRPADDR0", + "GTXE2_CHANNEL_TXDATA15", + "GTXE2_IMUX10_1", + "GTXE2_CHANNEL_PCSRSVDOUT0", + "GTXE2_CHANNEL_PMARSVDIN1", + "GTXE2_IMUX4_1", + "GTXE2_IMUX39_2", + "GTXE2_CHANNEL_REFCLK1", + "GTXE2_IMUX9_8", + "GTXE2_LOGIC_OUTS_B21_1", + "GTXE2_IMUX4_0", + "GTXE2_BYP3_8", + "GTXE2_CHANNEL_DRPDO8", + "GTXE2_IMUX11_5", + "GTXE2_IMUX24_8", + "GTXE2_IMUX44_3", + "GTXE2_IMUX20_4", + "GTXE2_CHANNEL_RXDLYOVRDEN", + "GTXE2_CTRL1_5", + "GTXE2_CHANNEL_DRPWE", + "GTXE2_IMUX20_0", + "GTXE2_BYP3_10", + "GTXE2_LOGIC_OUTS_B5_1", + "GTXE2_CHANNEL_RXMONITORSEL0", + "GTXE2_CHANNEL_TXPRECURSOR0", + "GTXE2_CHANNEL_RXDATA10", + "GTXE2_CHANNEL_DMONITOROUT3", + "GTXE2_CHANNEL_TXDATA34", + "GTXE2_CHANNEL_TXDATA1", + "GTXE2_IMUX16_10", + "GTXE2_IMUX15_6", + "GTXE2_BYP0_10", + "GTXE2_CHANNEL_RXSTATUS0", + "GTXE2_FAN1_1", + "GTXE2_IMUX12_0", + "GTXE2_FAN0_2", + "GTXE2_LOGIC_OUTS_B0_6", + "GTXE2_IMUX37_8", + "GTXE2_CHANNEL_TXRUNDISP7", + "GTXE2_CHANNEL_DRPDI3", + "GTXE2_IMUX8_4", + "GTXE2_CHANNEL_RXDATA58", + "GTXE2_FAN3_1", + "GTXE2_CHANNEL_TXDATA41", + "GTXE2_BYP7_9", + "GTXE2_BYP4_1", + "GTXE2_LOGIC_OUTS_B18_2", + "GTXE2_CHANNEL_TXRATE1", + "GTXE2_CHANNEL_TXDLYOVRDEN", + "GTXE2_IMUX4_9", + "GTXE2_IMUX34_7", + "GTXE2_LOGIC_OUTS_B2_9", + "GTXE2_IMUX39_9", + "GTXE2_CHANNEL_RXDATA52", + "GTXE2_IMUX6_6", + "GTXE2_IMUX2_4", + "GTXE2_IMUX9_4", + "GTXE2_CHANNEL_PCSRSVDOUT12", + "GTXE2_IMUX3_4", + "GTXE2_CHANNEL_TSTPDOVRDB", + "GTXE2_CLK1_1", + "GTXE2_IMUX1_6", + "GTXE2_CHANNEL_TXDATA47", + "GTXE2_BYP4_2", + "GTXE2_CHANNEL_RXQPISENN", + "GTXE2_CHANNEL_RXPHMONITOR1", + "GTXE2_FAN6_2", + "GTXE2_CHANNEL_RXMONITOROUT4", + "GTXE2_CHANNEL_TXPRECURSOR3", + "GTXE2_CHANNEL_DRPDO7", + "GTXE2_LOGIC_OUTS_B6_0", + "GTXE2_IMUX17_5", + "GTXE2_LOGIC_OUTS_B10_2", + "GTXE2_CHANNEL_TXN_PAD", + "GTXE2_BYP3_3", + "GTXE2_IMUX2_3", + "GTXE2_CHANNEL_TXDATA62", + "GTXE2_FAN3_7", + "GTXE2_IMUX7_1", + "GTXE2_LOGIC_OUTS_B13_5", + "GTXE2_CHANNEL_RXRESETDONE", + "GTXE2_IMUX40_1", + "GTXE2_CHANNEL_TSTOUT6", + "GTXE2_IMUX36_10", + "GTXE2_CHANNEL_TXCOMINIT", + "GTXE2_LOGIC_OUTS_B0_9", + "GTXE2_IMUX4_8", + "GTXE2_IMUX29_4", + "GTXE2_IMUX45_9", + "GTXE2_FAN2_8", + "GTXE2_IMUX10_10", + "GTXE2_CHANNEL_RXDATA34", + "GTXE2_CHANNEL_PCSRSVDIN5", + "GTXE2_CHANNEL_GTRSVD9", + "GTXE2_IMUX6_1", + "GTXE2_IMUX43_2", + "GTXE2_LOGIC_OUTS_B0_10", + "GTXE2_IMUX30_6", + "GTXE2_LOGIC_OUTS_B14_5", + "GTXE2_IMUX42_7", + "GTXE2_IMUX21_8", + "GTXE2_IMUX35_7", + "GTXE2_CHANNEL_RXLPMHFOVRDEN", + "GTXE2_IMUX18_4", + "GTXE2_CHANNEL_RXPRBSSEL0", + "GTXE2_IMUX0_2", + "GTXE2_CHANNEL_PCSRSVDIN13", + "GTXE2_LOGIC_OUTS_B0_4", + "GTXE2_IMUX46_9", + "GTXE2_CHANNEL_PCSRSVDIN15", + "GTXE2_CHANNEL_TXP", + "GTXE2_CHANNEL_RXCHARISK5", + "GTXE2_CHANNEL_TXMAINCURSOR0", + "GTXE2_CHANNEL_TXDATA53", + "GTXE2_LOGIC_OUTS_B15_8", + "GTXE2_CHANNEL_DRPDO13", + "GTXE2_IMUX33_9", + "GTXE2_IMUX25_3", + "GTXE2_CHANNEL_TXMAINCURSOR3", + "GTXE2_CHANNEL_DRPDO4", + "GTXE2_IMUX42_4", + "GTXE2_IMUX31_5", + "GTXE2_CHANNEL_RXDATA32", + "GTXE2_LOGIC_OUTS_B20_6", + "GTXE2_LOGIC_OUTS_B13_9", + "GTXE2_CHANNEL_TXRATEDONE", + "GTXE2_CHANNEL_RXRATEDONE", + "GTXE2_FAN6_1", + "GTXE2_IMUX43_1", + "GTXE2_IMUX39_8", + "GTXE2_IMUX45_3", + "GTXE2_IMUX45_5", + "GTXE2_CTRL0_3", + "GTXE2_IMUX41_7", + "GTXE2_CHANNEL_RXCHBONDO3", + "GTXE2_CHANNEL_TXCHARDISPVAL3", + "GTXE2_CHANNEL_TXDATA45", + "GTXE2_CHANNEL_TXUSERRDY", + "GTXE2_FAN4_5", + "GTXE2_FAN5_1", + "GTXE2_LOGIC_OUTS_B8_7", + "GTXE2_CHANNEL_TSTPD4", + "GTXE2_CHANNEL_PMASCANCLK0", + "GTXE2_IMUX23_10", + "GTXE2_CHANNEL_TXBUFDIFFCTRL0", + "GTXE2_BYP0_9", + "GTXE2_FAN2_9", + "GTXE2_IMUX15_4", + "GTXE2_IMUX6_4", + "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", + "GTXE2_CHANNEL_TXDATA38", + "GTXE2_CHANNEL_RXDFEUTOVRDEN", + "GTXE2_FAN1_0", + "GTXE2_CHANNEL_RXDATA51", + "GTXE2_CLK0_9", + "GTXE2_CHANNEL_TXPD0", + "GTXE2_CHANNEL_GTRSVD4", + "GTXE2_IMUX2_10", + "GTXE2_IMUX47_6", + "GTXE2_CHANNEL_TXPD1", + "GTXE2_IMUX35_0", + "GTXE2_CHANNEL_TXDLYHOLD", + "GTXE2_CHANNEL_TXPMARESET", + "GTXE2_IMUX28_10", + "GTXE2_LOGIC_OUTS_B22_5", + "GTXE2_LOGIC_OUTS_B17_2", + "GTXE2_LOGIC_OUTS_B19_9", + "GTXE2_IMUX14_2", + "GTXE2_CHANNEL_TXDATA60", + "GTXE2_IMUX38_0", + "GTXE2_BYP6_9", + "GTXE2_CHANNEL_QPLLREFCLK", + "GTXE2_LOGIC_OUTS_B21_10", + "GTXE2_IMUX24_3", + "GTXE2_CHANNEL_DRPDI0", + "GTXE2_LOGIC_OUTS_B9_10", + "GTXE2_CHANNEL_TSTIN15", + "GTXE2_CHANNEL_RXPHSLIPMONITOR1", + "GTXE2_CHANNEL_RXDFETAP4HOLD", + "GTXE2_BYP3_7", + "GTXE2_CHANNEL_TXSEQUENCE3", + "GTXE2_BYP6_4", + "GTXE2_IMUX18_3", + "GTXE2_IMUX45_7", + "GTXE2_CHANNEL_TSTIN14", + "GTXE2_IMUX8_0", + "GTXE2_CHANNEL_RXHEADER1", + "GTXE2_CHANNEL_TXCHARISK5", + "GTXE2_IMUX37_1", + "GTXE2_CHANNEL_RXBYTEREALIGN", + "GTXE2_IMUX5_0", + "GTXE2_CHANNEL_DMONITOROUT0", + "GTXE2_CHANNEL_DRPEN", + "GTXE2_CHANNEL_TXUSRCLK", + "GTXE2_FAN3_4", + "GTXE2_IMUX19_8", + "GTXE2_CHANNEL_PCSRSVDIN10", + "GTXE2_IMUX1_9", + "GTXE2_LOGIC_OUTS_B17_8", + "GTXE2_CHANNEL_RXPHMONITOR4", + "GTXE2_FAN6_7", + "GTXE2_IMUX8_9", + "GTXE2_IMUX2_6", + "GTXE2_CHANNEL_PCSRSVDOUT6", + "GTXE2_IMUX7_9", + "GTXE2_IMUX19_1", + "GTXE2_CHANNEL_PCSRSVDIN4", + "GTXE2_IMUX21_7", + "GTXE2_LOGIC_OUTS_B18_8", + "GTXE2_IMUX7_5", + "GTXE2_IMUX41_1", + "GTXE2_CHANNEL_TXDATA5", + "GTXE2_IMUX9_9", + "GTXE2_CLK1_2", + "GTXE2_LOGIC_OUTS_B6_8", + "GTXE2_BYP6_7", + "GTXE2_CTRL1_8", + "GTXE2_IMUX17_7", + "GTXE2_IMUX46_7", + "GTXE2_CHANNEL_TSTIN3", + "GTXE2_CHANNEL_RXCHBONDLEVEL2", + "GTXE2_CTRL0_1", + "GTXE2_CHANNEL_TXMAINCURSOR4", + "GTXE2_CHANNEL_PCSRSVDIN2", + "GTXE2_IMUX26_4", + "GTXE2_CHANNEL_RXMONITOROUT1", + "GTXE2_CHANNEL_RXCHARISK3", + "GTXE2_IMUX15_8", + "GTXE2_CHANNEL_TSTIN13", + "GTXE2_CHANNEL_PCSRSVDIN1", + "GTXE2_CHANNEL_GTNORTHREFCLK1", + "GTXE2_BYP0_6", + "GTXE2_CHANNEL_RXDATA36", + "GTXE2_CHANNEL_RXQPISENP", + "GTXE2_CHANNEL_RXDATA31", + "GTXE2_LOGIC_OUTS_B0_8", + "GTXE2_LOGIC_OUTS_B0_7", + "GTXE2_IMUX24_6", + "GTXE2_LOGIC_OUTS_B22_9", + "GTXE2_CHANNEL_RXDATA46", + "GTXE2_IMUX33_6", + "GTXE2_LOGIC_OUTS_B21_0", + "GTXE2_IMUX19_0", + "GTXE2_CLK1_3", + "GTXE2_LOGIC_OUTS_B14_2", + "GTXE2_IMUX37_4", + "GTXE2_BYP5_1", + "GTXE2_IMUX6_8", + "GTXE2_IMUX16_2", + "GTXE2_CHANNEL_RXDATA2", + "GTXE2_IMUX31_2", + "GTXE2_FAN4_2", + "GTXE2_LOGIC_OUTS_B18_0", + "GTXE2_CHANNEL_SCANIN4", + "GTXE2_LOGIC_OUTS_B15_10", + "GTXE2_LOGIC_OUTS_B13_3", + "GTXE2_LOGIC_OUTS_B5_7", + "GTXE2_LOGIC_OUTS_B6_9", + "GTXE2_CHANNEL_TXCHARDISPMODE1", + "GTXE2_CHANNEL_RXPCD1DONE", + "GTXE2_IMUX21_2", + "GTXE2_LOGIC_OUTS_B23_3", + "GTXE2_IMUX39_10", + "GTXE2_CHANNEL_TXQPIBIASEN", + "GTXE2_LOGIC_OUTS_B9_2", + "GTXE2_LOGIC_OUTS_B0_2", + "GTXE2_CHANNEL_RXUSERRDY", + "GTXE2_CHANNEL_DRPDO3", + "GTXE2_CHANNEL_EYESCANRESET", + "GTXE2_BYP7_1", + "GTXE2_LOGIC_OUTS_B12_6", + "GTXE2_CLK0_7", + "GTXE2_FAN0_7", + "GTXE2_CHANNEL_RXPHALIGNEN", + "GTXE2_IMUX24_5", + "GTXE2_CHANNEL_TXMARGIN1", + "GTXE2_CHANNEL_TXCHARDISPVAL0", + "GTXE2_IMUX8_5", + "GTXE2_IMUX14_8", + "GTXE2_CHANNEL_RXDATA0", + "GTXE2_FAN1_7", + "GTXE2_CHANNEL_RXPOLARITY", + "GTXE2_IMUX0_1", + "GTXE2_IMUX16_7", + "GTXE2_CHANNEL_TXSEQUENCE2", + "GTXE2_IMUX47_7", + "GTXE2_CHANNEL_RXPCOMMAALIGNEN", + "GTXE2_IMUX42_1", + "GTXE2_LOGIC_OUTS_B18_10", + "GTXE2_CHANNEL_GTRSVD1", + "GTXE2_LOGIC_OUTS_B7_0", + "GTXE2_CLK0_4", + "GTXE2_CHANNEL_TX8B10BBYPASS0", + "GTXE2_LOGIC_OUTS_B18_4", + "GTXE2_LOGIC_OUTS_B23_4", + "GTXE2_CHANNEL_PCSRSVDIN8", + "GTXE2_IMUX0_9", + "GTXE2_LOGIC_OUTS_B1_8", + "GTXE2_BYP1_8", + "GTXE2_LOGIC_OUTS_B7_5", + "GTXE2_CHANNEL_TXPCSRESET", + "GTXE2_CHANNEL_TXOUTCLKSEL2", + "GTXE2_CHANNEL_TXCHARDISPVAL7", + "GTXE2_CHANNEL_RXDATA3", + "GTXE2_IMUX47_5", + "GTXE2_CHANNEL_TXMAINCURSOR6", + "GTXE2_CHANNEL_RXPHSLIPMONITOR3", + "GTXE2_LOGIC_OUTS_B9_4", + "GTXE2_IMUX7_3", + "GTXE2_CHANNEL_PMASCANIN1", + "GTXE2_IMUX36_9", + "GTXE2_CHANNEL_TSTOUT2", + "GTXE2_IMUX27_3", + "GTXE2_LOGIC_OUTS_B19_4", + "GTXE2_IMUX27_0", + "GTXE2_CHANNEL_RXCLKCORCNT1", + "GTXE2_CHANNEL_TXDATA46", + "GTXE2_CHANNEL_RXDFEXYDHOLD", + "GTXE2_LOGIC_OUTS_B22_0", + "GTXE2_BYP2_5", + "GTXE2_CHANNEL_EDTBYPASS", + "GTXE2_CHANNEL_RXDATA40", + "GTXE2_IMUX42_6", + "GTXE2_CHANNEL_TXCHARDISPVAL6", + "GTXE2_LOGIC_OUTS_B16_9", + "GTXE2_LOGIC_OUTS_B11_8", + "GTXE2_LOGIC_OUTS_B14_0", + "GTXE2_CTRL1_3", + "GTXE2_CHANNEL_RXDATA23", + "GTXE2_IMUX32_7", + "GTXE2_CHANNEL_PMASCANIN4", + "GTXE2_IMUX31_8", + "GTXE2_LOGIC_OUTS_B4_6", + "GTXE2_CHANNEL_RXN_PAD", + "GTXE2_BYP2_9", + "GTXE2_IMUX18_5", + "GTXE2_CHANNEL_TXELECIDLE", + "GTXE2_LOGIC_OUTS_B13_8", + "GTXE2_IMUX46_6", + "GTXE2_CHANNEL_RXCHANISALIGNED", + "GTXE2_IMUX32_5", + "GTXE2_IMUX38_6", + "GTXE2_IMUX30_4", + "GTXE2_LOGIC_OUTS_B17_5", + "GTXE2_CLK0_3", + "GTXE2_IMUX25_2", + "GTXE2_IMUX9_3", + "GTXE2_IMUX32_1", + "GTXE2_CHANNEL_TXDIFFCTRL3", + "GTXE2_IMUX31_0", + "GTXE2_CHANNEL_RXDISPERR4", + "GTXE2_IMUX17_9", + "GTXE2_CHANNEL_SCANOUT2", + "GTXE2_FAN0_9", + "GTXE2_CHANNEL_TXPOSTCURSOR3", + "GTXE2_CHANNEL_TXOUTCLKSEL1", + "GTXE2_LOGIC_OUTS_B1_10", + "GTXE2_IMUX28_1", + "GTXE2_CHANNEL_RXPCSRESET", + "GTXE2_CHANNEL_TXHEADER2", + "GTXE2_IMUX7_10", + "GTXE2_CHANNEL_TXPOSTCURSOR2", + "GTXE2_IMUX20_6", + "GTXE2_BYP7_8", + "GTXE2_FAN5_0", + "GTXE2_CHANNEL_SCANIN1", + "GTXE2_CHANNEL_PMASCANMODEB", + "GTXE2_IMUX40_4", + "GTXE2_LOGIC_OUTS_B10_5", + "GTXE2_CHANNEL_TXPISOPD", + "GTXE2_LOGIC_OUTS_B23_1", + "GTXE2_CHANNEL_QPLLCLK", + "GTXE2_IMUX8_10", + "GTXE2_CHANNEL_RXDLYSRESET", + "GTXE2_IMUX16_5", + "GTXE2_IMUX9_6", + "GTXE2_CHANNEL_TXN", + "GTXE2_LOGIC_OUTS_B1_5", + "GTXE2_BYP2_4", + "GTXE2_CHANNEL_PCSRSVDOUT3", + "GTXE2_BYP4_5", + "GTXE2_CLK1_0", + "GTXE2_IMUX44_6", + "GTXE2_IMUX43_8", + "GTXE2_IMUX14_0", + "GTXE2_BYP7_0", + "GTXE2_CHANNEL_REFCLK0", + "GTXE2_CHANNEL_RXPMARESET", + "GTXE2_CHANNEL_RXCHANBONDSEQ", + "GTXE2_CHANNEL_TXCOMFINISH", + "GTXE2_IMUX7_6", + "GTXE2_CHANNEL_TXBUFDIFFCTRL1", + "GTXE2_IMUX17_0", + "GTXE2_CHANNEL_EYESCANDATAERROR", + "GTXE2_IMUX11_1", + "GTXE2_CHANNEL_TXDATA11", + "GTXE2_LOGIC_OUTS_B1_3", + "GTXE2_CHANNEL_RXCHBONDI0", + "GTXE2_CHANNEL_RXCHBONDLEVEL0", + "GTXE2_CHANNEL_RXDATA1", + "GTXE2_LOGIC_OUTS_B4_10", + "GTXE2_IMUX34_3", + "GTXE2_IMUX14_9", + "GTXE2_CHANNEL_RXCHARISCOMMA0", + "GTXE2_FAN4_6", + "GTXE2_IMUX14_4", + "GTXE2_CHANNEL_TSTOUT5", + "GTXE2_LOGIC_OUTS_B15_7", + "GTXE2_CHANNEL_PCSRSVDOUT9", + "GTXE2_IMUX13_7", + "GTXE2_FAN4_4", + "GTXE2_LOGIC_OUTS_B2_8", + "GTXE2_CHANNEL_TXPHALIGNEN", + "GTXE2_IMUX37_0", + "GTXE2_CHANNEL_TXOUTCLK_3", + "GTXE2_CHANNEL_GTRSVD6", + "GTXE2_CHANNEL_RXMONITORSEL1", + "GTXE2_CHANNEL_TXCHARDISPVAL4", + "GTXE2_CHANNEL_RXDATA16", + "GTXE2_IMUX40_7", + "GTXE2_CHANNEL_PCSRSVDIN12", + "GTXE2_IMUX38_9", + "GTXE2_CHANNEL_PMARSVDIN4", + "GTXE2_IMUX28_0", + "GTXE2_BYP4_8", + "GTXE2_CHANNEL_TXBUFSTATUS0", + "GTXE2_CHANNEL_RXCHBONDLEVEL1", + "GTXE2_IMUX19_2", + "GTXE2_LOGIC_OUTS_B7_8", + "GTXE2_CHANNEL_TXMARGIN2", + "GTXE2_IMUX41_6", + "GTXE2_CHANNEL_DRPDO5", + "GTXE2_CHANNEL_RXDATA55", + "GTXE2_IMUX23_8", + "GTXE2_BYP1_5", + "GTXE2_CHANNEL_RXSYSCLKSEL1", + "GTXE2_LOGIC_OUTS_B16_7", + "GTXE2_CHANNEL_RXCHBONDI2", + "GTXE2_CHANNEL_TXSEQUENCE1", + "GTXE2_CHANNEL_SOUTHREFCLK0", + "GTXE2_IMUX16_3", + "GTXE2_IMUX28_6", + "GTXE2_IMUX35_4", + "GTXE2_LOGIC_OUTS_B16_1", + "GTXE2_CHANNEL_RXDATA57", + "GTXE2_CHANNEL_TXDATA18", + "GTXE2_LOGIC_OUTS_B14_3", + "GTXE2_IMUX27_7", + "GTXE2_CHANNEL_DMONITOROUT1", + "GTXE2_IMUX39_7", + "GTXE2_LOGIC_OUTS_B17_1", + "GTXE2_IMUX27_10", + "GTXE2_CHANNEL_RXCHARISCOMMA1", + "GTXE2_CHANNEL_RXLPMHFHOLD", + "GTXE2_IMUX27_6", + "GTXE2_IMUX6_5", + "GTXE2_BYP5_2", + "GTXE2_CHANNEL_SETERRSTATUS", + "GTXE2_CHANNEL_TXCHARDISPVAL1", + "GTXE2_LOGIC_OUTS_B12_9", + "GTXE2_CHANNEL_PCSRSVDIN9", + "GTXE2_IMUX46_4", + "GTXE2_CHANNEL_PMASCANIN3", + "GTXE2_IMUX20_8", + "GTXE2_CHANNEL_CPLLLOCKEN", + "GTXE2_CHANNEL_DRPADDR6", + "GTXE2_IMUX45_4", + "GTXE2_LOGIC_OUTS_B1_1", + "GTXE2_IMUX42_3", + "GTXE2_BYP1_3", + "GTXE2_CTRL1_0", + "GTXE2_CHANNEL_TXRUNDISP0", + "GTXE2_IMUX42_9", + "GTXE2_CHANNEL_RXDFETAP5OVRDEN", + "GTXE2_IMUX47_2", + "GTXE2_IMUX0_3", + "GTXE2_CTRL0_5", + "GTXE2_CHANNEL_PCSRSVDIN20", + "GTXE2_BYP3_9", + "GTXE2_CHANNEL_TSTCLK1", + "GTXE2_BYP2_1", + "GTXE2_CHANNEL_RXCHARISK1", + "GTXE2_IMUX33_7", + "GTXE2_IMUX12_8", + "GTXE2_IMUX35_2", + "GTXE2_IMUX10_5", + "GTXE2_IMUX34_8", + "GTXE2_CHANNEL_TSTPD1", + "GTXE2_IMUX2_9", + "GTXE2_CHANNEL_TXDATA2", + "GTXE2_IMUX21_1", + "GTXE2_LOGIC_OUTS_B22_7", + "GTXE2_CHANNEL_TXOUTCLK_1", + "GTXE2_FAN1_10", + "GTXE2_IMUX32_3", + "GTXE2_LOGIC_OUTS_B13_10", + "GTXE2_LOGIC_OUTS_B7_6", + "GTXE2_FAN7_3", + "GTXE2_CHANNEL_TXOUTCLKPCS", + "GTXE2_IMUX4_6", + "GTXE2_CHANNEL_TSTOUT3", + "GTXE2_CHANNEL_RXNOTINTABLE7", + "GTXE2_LOGIC_OUTS_B12_8", + "GTXE2_CHANNEL_RXDATA61", + "GTXE2_CHANNEL_RXDATA56", + "GTXE2_FAN3_2", + "GTXE2_LOGIC_OUTS_B8_5", + "GTXE2_CLK0_5", + "GTXE2_FAN2_10", + "GTXE2_IMUX41_8", + "GTXE2_BYP5_9", + "GTXE2_CHANNEL_DRPDI5", + "GTXE2_CHANNEL_TXSEQUENCE0", + "GTXE2_IMUX26_10", + "GTXE2_CHANNEL_RXSTARTOFSEQ", + "GTXE2_BYP1_0", + "GTXE2_IMUX47_1", + "GTXE2_CHANNEL_PMARSVDIN21", + "GTXE2_IMUX18_10", + "GTXE2_CHANNEL_TXPOSTCURSOR4", + "GTXE2_LOGIC_OUTS_B15_3", + "GTXE2_CHANNEL_RXCOMMADETEN", + "GTXE2_FAN0_1", + "GTXE2_CHANNEL_GTRSVD7", + "GTXE2_CLK1_8", + "GTXE2_CHANNEL_TXDIFFCTRL0", + "GTXE2_IMUX22_2", + "GTXE2_LOGIC_OUTS_B4_5", + "GTXE2_CHANNEL_TXBUFSTATUS1", + "GTXE2_IMUX6_10", + "GTXE2_CHANNEL_SCANIN3", + "GTXE2_FAN0_0", + "GTXE2_LOGIC_OUTS_B22_6", + "GTXE2_LOGIC_OUTS_B13_4", + "GTXE2_CHANNEL_RXDATA12", + "GTXE2_LOGIC_OUTS_B7_3", + "GTXE2_IMUX41_5", + "GTXE2_CHANNEL_RXOUTCLK_0", + "GTXE2_IMUX20_9", + "GTXE2_IMUX27_8", + "GTXE2_CHANNEL_RXDFELFHOLD", + "GTXE2_CHANNEL_PCSRSVDIN14", + "GTXE2_FAN1_6", + "GTXE2_IMUX34_4", + "GTXE2_CHANNEL_RXDISPERR2", + "GTXE2_CHANNEL_TXRUNDISP3", + "GTXE2_CHANNEL_CPLLRESET", + "GTXE2_BYP5_6", + "GTXE2_LOGIC_OUTS_B6_1", + "GTXE2_IMUX12_4", + "GTXE2_FAN2_2", + "GTXE2_CHANNEL_RXDATA47", + "GTXE2_CHANNEL_DRPDO9", + "GTXE2_LOGIC_OUTS_B14_6", + "GTXE2_CHANNEL_DRPDO1", + "GTXE2_CHANNEL_TXPRBSFORCEERR", + "GTXE2_LOGIC_OUTS_B16_4", + "GTXE2_IMUX16_8", + "GTXE2_LOGIC_OUTS_B14_7", + "GTXE2_LOGIC_OUTS_B23_8", + "GTXE2_FAN6_4", + "GTXE2_LOGIC_OUTS_B0_3", + "GTXE2_IMUX29_5", + "GTXE2_CHANNEL_RXCDRLOCK", + "GTXE2_CHANNEL_GTNORTHREFCLK0", + "GTXE2_IMUX31_1", + "GTXE2_IMUX20_5", + "GTXE2_CHANNEL_LOOPBACK2", + "GTXE2_CHANNEL_RXPRBSERR", + "GTXE2_IMUX7_0", + "GTXE2_BYP0_2", + "GTXE2_CHANNEL_RXGEARBOXSLIP", + "GTXE2_LOGIC_OUTS_B8_9", + "GTXE2_CHANNEL_PMASCANOUT3", + "GTXE2_CHANNEL_TSTIN1", + "GTXE2_LOGIC_OUTS_B21_9", + "GTXE2_FAN4_1", + "GTXE2_LOGIC_OUTS_B6_10", + "GTXE2_IMUX35_6", + "GTXE2_IMUX24_9", + "GTXE2_CHANNEL_TSTIN18", + "GTXE2_CHANNEL_RXDISPERR5", + "GTXE2_FAN6_10", + "GTXE2_IMUX32_0", + "GTXE2_CHANNEL_CLKRSVD1", + "GTXE2_CTRL1_6", + "GTXE2_CHANNEL_TSTOUT7", + "GTXE2_LOGIC_OUTS_B9_8", + "GTXE2_IMUX38_7", + "GTXE2_IMUX5_2", + "GTXE2_CLK0_2", + "GTXE2_CHANNEL_DRPDI11", + "GTXE2_CHANNEL_RXPHALIGN", + "GTXE2_LOGIC_OUTS_B0_0", + "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", + "GTXE2_CHANNEL_TXDATA58", + "GTXE2_LOGIC_OUTS_B3_4", + "GTXE2_CHANNEL_RXUSRCLK2", + "GTXE2_CHANNEL_TXDATA50", + "GTXE2_CHANNEL_RXDATA24", + "GTXE2_CHANNEL_PCSRSVDIN0", + "GTXE2_CHANNEL_RXCHBONDO0", + "GTXE2_LOGIC_OUTS_B22_4", + "GTXE2_IMUX13_1", + "GTXE2_CHANNEL_TXCHARDISPMODE3", + "GTXE2_CHANNEL_RXRATE0", + "GTXE2_CHANNEL_RXDATA27", + "GTXE2_IMUX28_2", + "GTXE2_IMUX14_7", + "GTXE2_LOGIC_OUTS_B20_2", + "GTXE2_IMUX44_5", + "GTXE2_BYP4_9", + "GTXE2_IMUX36_1", + "GTXE2_BYP2_7", + "GTXE2_CHANNEL_TXDATA12", + "GTXE2_CHANNEL_EDTUPDATE", + "GTXE2_IMUX26_3", + "GTXE2_CHANNEL_RXDISPERR6", + "GTXE2_FAN3_3", + "GTXE2_CHANNEL_TXPHALIGN", + "GTXE2_CHANNEL_TXDIFFCTRL1", + "GTXE2_LOGIC_OUTS_B4_0", + "GTXE2_IMUX9_10", + "GTXE2_CHANNEL_TXDATA26", + "GTXE2_CHANNEL_TXP_PAD", + "GTXE2_CHANNEL_RXOUTCLK_1", + "GTXE2_IMUX12_7", + "GTXE2_IMUX33_5", + "GTXE2_IMUX47_3", + "GTXE2_LOGIC_OUTS_B14_8", + "GTXE2_CHANNEL_RXDEBUGPULSE", + "GTXE2_CHANNEL_RXDATA4", + "GTXE2_LOGIC_OUTS_B12_7", + "GTXE2_IMUX20_2", + "GTXE2_CHANNEL_RXNOTINTABLE4", + "GTXE2_CHANNEL_RXDFEUTHOLD", + "GTXE2_CHANNEL_GTREFCLK0", + "GTXE2_IMUX37_9", + "GTXE2_CHANNEL_RXBUFSTATUS1", + "GTXE2_IMUX4_7", + "GTXE2_BYP1_9", + "GTXE2_CHANNEL_DRPDO12", + "GTXE2_IMUX31_6", + "GTXE2_CHANNEL_RXMONITOROUT5", + "GTXE2_FAN5_6", + "GTXE2_CHANNEL_TXDATA7", + "GTXE2_CHANNEL_TSTOUT9", + "GTXE2_CHANNEL_RXNOTINTABLE3", + "GTXE2_CHANNEL_EYESCANTRIGGER", + "GTXE2_IMUX10_7", + "GTXE2_CHANNEL_GTSOUTHREFCLK0", + "GTXE2_LOGIC_OUTS_B19_8", + "GTXE2_LOGIC_OUTS_B7_10", + "GTXE2_CHANNEL_RXCDRRESETRSV", + "GTXE2_CHANNEL_RXSLIDE", + "GTXE2_CHANNEL_TXPRBSSEL2", + "GTXE2_IMUX43_10", + "GTXE2_CHANNEL_RXCHBONDI1", + "GTXE2_BYP3_1", + "GTXE2_CHANNEL_RXP", + "GTXE2_IMUX13_6", + "GTXE2_LOGIC_OUTS_B5_2", + "GTXE2_LOGIC_OUTS_B9_6", + "GTXE2_IMUX35_8", + "GTXE2_CHANNEL_TXRATE2", + "GTXE2_CHANNEL_CPLLLOCKDETCLK", + "GTXE2_IMUX36_5", + "GTXE2_CHANNEL_RXLPMEN", + "GTXE2_CHANNEL_RXCDROVRDEN", + "GTXE2_BYP6_3", + "GTXE2_BYP3_4", + "GTXE2_LOGIC_OUTS_B21_6", + "GTXE2_LOGIC_OUTS_B12_10", + "GTXE2_IMUX43_3", + "GTXE2_FAN4_10", + "GTXE2_IMUX24_2", + "GTXE2_IMUX46_10", + "GTXE2_LOGIC_OUTS_B5_5", + "GTXE2_CHANNEL_TXOUTCLKFABRIC", + "GTXE2_CHANNEL_TSTIN10", + "GTXE2_IMUX36_6", + "GTXE2_BYP4_10", + "GTXE2_CHANNEL_RXDFEXYDOVRDEN", + "GTXE2_IMUX34_0", + "GTXE2_CLK0_1", + "GTXE2_IMUX11_10", + "GTXE2_LOGIC_OUTS_B10_4", + "GTXE2_LOGIC_OUTS_B20_1", + "GTXE2_CHANNEL_TXMAINCURSOR2", + "GTXE2_CHANNEL_RXPD1", + "GTXE2_IMUX32_10", + "GTXE2_LOGIC_OUTS_B7_2", + "GTXE2_LOGIC_OUTS_B0_1", + "GTXE2_CHANNEL_RXDATA18", + "GTXE2_IMUX21_9", + "GTXE2_IMUX3_0", + "GTXE2_CTRL0_6", + "GTXE2_CHANNEL_RXCDRFREQRESET", + "GTXE2_IMUX45_2", + "GTXE2_LOGIC_OUTS_B13_2", + "GTXE2_CHANNEL_RXDISPERR1", + "GTXE2_CTRL0_0", + "GTXE2_FAN6_8", + "GTXE2_IMUX30_0", + "GTXE2_IMUX43_6", + "GTXE2_BYP1_6", + "GTXE2_IMUX28_3", + "GTXE2_IMUX18_0", + "GTXE2_LOGIC_OUTS_B10_7", + "GTXE2_CHANNEL_PCSRSVDOUT8", + "GTXE2_FAN6_5", + "GTXE2_CLK0_0", + "GTXE2_LOGIC_OUTS_B9_3", + "GTXE2_CHANNEL_TXDATA55", + "GTXE2_LOGIC_OUTS_B20_3", + "GTXE2_CHANNEL_PMASCANIN0", + "GTXE2_IMUX29_10", + "GTXE2_CHANNEL_DRPDI2", + "GTXE2_LOGIC_OUTS_B20_4", + "GTXE2_CHANNEL_RXDFECM1EN", + "GTXE2_CHANNEL_RXCHARISCOMMA3", + "GTXE2_CHANNEL_RXCHARISCOMMA5", + "GTXE2_CHANNEL_PMASCANENB", + "GTXE2_IMUX11_6", + "GTXE2_BYP3_2", + "GTXE2_CHANNEL_RXCHARISCOMMA7", + "GTXE2_CHANNEL_TXPHINIT", + "GTXE2_IMUX25_1", + "GTXE2_BYP7_4", + "GTXE2_CHANNEL_RXOUTCLKSEL0", + "GTXE2_IMUX1_1", + "GTXE2_CHANNEL_TXDATA51", + "GTXE2_IMUX35_3", + "GTXE2_LOGIC_OUTS_B22_10", + "GTXE2_FAN5_7", + "GTXE2_CHANNEL_RXDFETAP3OVRDEN", + "GTXE2_CHANNEL_PMARSVDIN20", + "GTXE2_CHANNEL_RXPHMONITOR2", + "GTXE2_CHANNEL_RXDATA25", + "GTXE2_CHANNEL_RXDATA9", + "GTXE2_CHANNEL_TSTOUT0", + "GTXE2_CHANNEL_TXPRECURSOR4", + "GTXE2_IMUX5_5", + "GTXE2_IMUX22_5", + "GTXE2_IMUX30_10", + "GTXE2_LOGIC_OUTS_B19_3", + "GTXE2_FAN1_3", + "GTXE2_CHANNEL_RXCDRHOLD", + "GTXE2_LOGIC_OUTS_B10_6", + "GTXE2_LOGIC_OUTS_B16_5", + "GTXE2_FAN1_2", + "GTXE2_IMUX45_1", + "GTXE2_IMUX19_7", + "GTXE2_CHANNEL_RXDATA43", + "GTXE2_CHANNEL_TXUSRCLK2", + "GTXE2_IMUX26_6", + "GTXE2_IMUX3_6", + "GTXE2_CHANNEL_TXCHARISK4", + "GTXE2_LOGIC_OUTS_B11_2", + "GTXE2_CHANNEL_TSTPD3", + "GTXE2_IMUX38_3", + "GTXE2_LOGIC_OUTS_B12_3", + "GTXE2_IMUX45_10", + "GTXE2_FAN7_5", + "GTXE2_IMUX38_5", + "GTXE2_BYP5_4", + "GTXE2_CHANNEL_PCSRSVDIN3", + "GTXE2_LOGIC_OUTS_B4_9", + "GTXE2_LOGIC_OUTS_B2_5", + "GTXE2_IMUX26_2", + "GTXE2_CHANNEL_SCANOUT4", + "GTXE2_CHANNEL_CFGRESET", + "GTXE2_IMUX33_3", + "GTXE2_CHANNEL_RXDATA20", + "GTXE2_IMUX38_10", + "GTXE2_CHANNEL_TSTOUT1", + "GTXE2_IMUX1_8", + "GTXE2_CHANNEL_TXDATA20", + "GTXE2_CHANNEL_TSTPD0", + "GTXE2_CHANNEL_TXDATA37", + "GTXE2_IMUX23_1", + "GTXE2_IMUX36_0", + "GTXE2_LOGIC_OUTS_B16_10", + "GTXE2_IMUX4_2", + "GTXE2_IMUX18_1", + "GTXE2_LOGIC_OUTS_B12_0", + "GTXE2_CHANNEL_RXDATA30", + "GTXE2_IMUX44_10", + "GTXE2_IMUX25_6", + "GTXE2_CHANNEL_PMASCANOUT4", + "GTXE2_LOGIC_OUTS_B17_10", + "GTXE2_CHANNEL_TXINHIBIT", + "GTXE2_IMUX3_5", + "GTXE2_CHANNEL_TXDATA39", + "GTXE2_IMUX15_10", + "GTXE2_CHANNEL_TXPDELECIDLEMODE", + "GTXE2_IMUX26_8", + "GTXE2_CHANNEL_GTTXRESET", + "GTXE2_CHANNEL_TXCHARISK2", + "GTXE2_IMUX6_3", + "GTXE2_CHANNEL_RXPRBSSEL1", + "GTXE2_CHANNEL_RXPHSLIPMONITOR0", + "GTXE2_CLK0_10", + "GTXE2_CHANNEL_RXDFELPMRESET", + "GTXE2_IMUX42_10", + "GTXE2_IMUX2_1", + "GTXE2_LOGIC_OUTS_B16_2", + "GTXE2_CHANNEL_TXCOMSAS", + "GTXE2_IMUX6_7", + "GTXE2_IMUX29_6", + "GTXE2_IMUX31_4", + "GTXE2_CHANNEL_RXLPMLFHOLD", + "GTXE2_CHANNEL_PCSRSVDOUT4", + "GTXE2_CHANNEL_RXDATA59", + "GTXE2_CHANNEL_DRPADDR1", + "GTXE2_LOGIC_OUTS_B20_7", + "GTXE2_FAN2_1", + "GTXE2_FAN7_7", + "GTXE2_IMUX12_6", + "GTXE2_CHANNEL_TXDATA21", + "GTXE2_IMUX29_2", + "GTXE2_CHANNEL_RXDATA45", + "GTXE2_CHANNEL_TX8B10BBYPASS1", + "GTXE2_CHANNEL_SCANMODEB", + "GTXE2_IMUX36_7", + "GTXE2_IMUX17_3", + "GTXE2_CHANNEL_TXHEADER0", + "GTXE2_LOGIC_OUTS_B13_7", + "GTXE2_IMUX29_0", + "GTXE2_LOGIC_OUTS_B3_5", + "GTXE2_CHANNEL_TXCHARDISPMODE7", + "GTXE2_CHANNEL_GTRSVD12", + "GTXE2_LOGIC_OUTS_B1_7", + "GTXE2_CHANNEL_SCANOUT0", + "GTXE2_IMUX24_7", + "GTXE2_IMUX15_7", + "GTXE2_CHANNEL_RXDFEXYDEN", + "GTXE2_IMUX1_7", + "GTXE2_IMUX23_3", + "GTXE2_CHANNEL_TX8B10BBYPASS3", + "GTXE2_IMUX34_1", + "GTXE2_CHANNEL_RXCHARISCOMMA6", + "GTXE2_CHANNEL_TXOUTCLK_2", + "GTXE2_CHANNEL_TXDATA56", + "GTXE2_LOGIC_OUTS_B5_10", + "GTXE2_IMUX25_0", + "GTXE2_CHANNEL_PCSRSVDIN11", + "GTXE2_CHANNEL_TXRESETDONE", + "GTXE2_CHANNEL_TSTOUT4", + "GTXE2_IMUX43_9", + "GTXE2_CHANNEL_TSTOUT8", + "GTXE2_LOGIC_OUTS_B1_2", + "GTXE2_BYP7_6", + "GTXE2_FAN2_4", + "GTXE2_IMUX18_8", + "GTXE2_IMUX39_0", + "GTXE2_CHANNEL_RXDFETAP2HOLD", + "GTXE2_BYP6_6", + "GTXE2_CHANNEL_TXPHALIGNDONE", + "GTXE2_LOGIC_OUTS_B2_6", + "GTXE2_IMUX37_5", + "GTXE2_LOGIC_OUTS_B8_1", + "GTXE2_CHANNEL_TXDATA35", + "GTXE2_CHANNEL_TXPRECURSORINV", + "GTXE2_IMUX10_9", + "GTXE2_IMUX38_1", + "GTXE2_IMUX14_6", + "GTXE2_CHANNEL_PMARSVDIN2", + "GTXE2_IMUX18_6", + "GTXE2_FAN0_5", + "GTXE2_CHANNEL_RXCHBONDSLAVE", + "GTXE2_CHANNEL_DRPADDR2", + "GTXE2_CHANNEL_RXDATA29", + "GTXE2_CHANNEL_RXMONITOROUT6", + "GTXE2_CHANNEL_TXDATA54", + "GTXE2_BYP4_0", + "GTXE2_CHANNEL_PCSRSVDOUT10", + "GTXE2_LOGIC_OUTS_B14_10", + "GTXE2_CHANNEL_RXCHBONDI4", + "GTXE2_IMUX44_1", + "GTXE2_CHANNEL_TXDLYEN", + "GTXE2_LOGIC_OUTS_B17_4", + "GTXE2_LOGIC_OUTS_B10_0", + "GTXE2_FAN0_10", + "GTXE2_IMUX39_4", + "GTXE2_CHANNEL_TXMAINCURSOR5", + "GTXE2_IMUX7_7", + "GTXE2_CHANNEL_RXNOTINTABLE2", + "GTXE2_CHANNEL_DRPDI12", + "GTXE2_IMUX14_5", + "GTXE2_LOGIC_OUTS_B5_6", + "GTXE2_FAN2_7", + "GTXE2_CHANNEL_DRPDI7", + "GTXE2_CHANNEL_TXQPIWEAKPUP", + "GTXE2_CHANNEL_RXDISPERR0", + "GTXE2_BYP2_6", + "GTXE2_CHANNEL_RXPHOVRDEN", + "GTXE2_CHANNEL_TX8B10BBYPASS4", + "GTXE2_IMUX21_5", + "GTXE2_CHANNEL_EDTCONFIGURATION", + "GTXE2_CHANNEL_DRPDO0", + "GTXE2_IMUX24_10", + "GTXE2_IMUX43_4", + "GTXE2_LOGIC_OUTS_B13_6", + "GTXE2_FAN1_4", + "GTXE2_CHANNEL_RXOUTCLK_3", + "GTXE2_IMUX0_4", + "GTXE2_LOGIC_OUTS_B8_0", + "GTXE2_CHANNEL_TXDATA33", + "GTXE2_CHANNEL_SCANCLK", + "GTXE2_CHANNEL_TX8B10BBYPASS7", + "GTXE2_IMUX25_7", + "GTXE2_BYP5_0", + "GTXE2_IMUX46_5", + "GTXE2_IMUX13_4", + "GTXE2_LOGIC_OUTS_B8_2", + "GTXE2_CHANNEL_GTRSVD2", + "GTXE2_CHANNEL_GTSOUTHREFCLK1", + "GTXE2_CHANNEL_CLKRSVD3", + "GTXE2_CHANNEL_GTQPLLCLK", + "GTXE2_CHANNEL_RXDLYSRESETDONE", + "GTXE2_CHANNEL_RXDATA48", + "GTXE2_CHANNEL_RXHEADER2", + "GTXE2_FAN7_4", + "GTXE2_IMUX30_7", + "GTXE2_CLK0_6", + "GTXE2_CHANNEL_RXDATA22", + "GTXE2_IMUX3_9", + "GTXE2_CHANNEL_PCSRSVDOUT2", + "GTXE2_IMUX34_10", + "GTXE2_CHANNEL_RXPHSLIPMONITOR2", + "GTXE2_CHANNEL_TXDATA27", + "GTXE2_CHANNEL_PMASCANCLK4", + "GTXE2_CHANNEL_TXGEARBOXREADY", + "GTXE2_IMUX44_7", + "GTXE2_CHANNEL_RXDATA53", + "GTXE2_LOGIC_OUTS_B17_6", + "GTXE2_CHANNEL_TSTIN17", + "GTXE2_CHANNEL_RXCHBONDO1", + "GTXE2_LOGIC_OUTS_B21_4", + "GTXE2_IMUX44_4", + "GTXE2_IMUX13_3", + "GTXE2_FAN7_8", + "GTXE2_CLK0_8", + "GTXE2_IMUX36_8", + "GTXE2_CHANNEL_TXSTARTSEQ", + "GTXE2_IMUX10_2", + "GTXE2_IMUX41_0", + "GTXE2_IMUX3_10", + "GTXE2_CHANNEL_TXSEQUENCE5", + "GTXE2_LOGIC_OUTS_B7_4", + "GTXE2_CHANNEL_TXMARGIN0", + "GTXE2_IMUX15_3", + "GTXE2_BYP7_3", + "GTXE2_CHANNEL_RXDATA41", + "GTXE2_CHANNEL_DRPDI1", + "GTXE2_LOGIC_OUTS_B2_0", + "GTXE2_CHANNEL_RXDATA13", + "GTXE2_LOGIC_OUTS_B15_0", + "GTXE2_CHANNEL_RXDFELFOVRDEN", + "GTXE2_IMUX37_10", + "GTXE2_CHANNEL_PMARSVDIN23", + "GTXE2_CHANNEL_RXDATA63", + "GTXE2_CHANNEL_RXDATA60", + "GTXE2_CHANNEL_EDTCLOCK", + "GTXE2_CHANNEL_RXDATA44", + "GTXE2_CHANNEL_RXCLKCORCNT0", + "GTXE2_FAN4_8", + "GTXE2_CHANNEL_DMONITOROUT7", + "GTXE2_IMUX23_9", + "GTXE2_IMUX2_0", + "GTXE2_IMUX38_4", + "GTXE2_CHANNEL_RXOSOVRDEN", + "GTXE2_IMUX28_5", + "GTXE2_IMUX9_0", + "GTXE2_CHANNEL_RXMONITOROUT0", + "GTXE2_CHANNEL_TXRATE0", + "GTXE2_CHANNEL_TX8B10BEN", + "GTXE2_IMUX42_0", + "GTXE2_IMUX38_8", + "GTXE2_IMUX5_6", + "GTXE2_IMUX7_8", + "GTXE2_CHANNEL_TXDIFFCTRL2", + "GTXE2_CHANNEL_GTRSVD3", + "GTXE2_CHANNEL_DRPDI15", + "GTXE2_IMUX2_8", + "GTXE2_IMUX18_9", + "GTXE2_LOGIC_OUTS_B10_10", + "GTXE2_CHANNEL_RXRATE1", + "GTXE2_LOGIC_OUTS_B8_8", + "GTXE2_CLK1_6", + "GTXE2_CHANNEL_RXMONITOROUT3", + "GTXE2_CHANNEL_TXOUTCLKSEL0", + "GTXE2_CHANNEL_TXSEQUENCE4", + "GTXE2_CHANNEL_TX8B10BBYPASS5", + "GTXE2_CHANNEL_DRPDO11", + "GTXE2_CTRL0_2", + "GTXE2_LOGIC_OUTS_B10_3", + "GTXE2_IMUX46_8", + "GTXE2_LOGIC_OUTS_B19_0", + "GTXE2_BYP0_4", + "GTXE2_CHANNEL_TXCHARDISPMODE4", + "GTXE2_IMUX29_7", + "GTXE2_IMUX26_1", + "GTXE2_CHANNEL_PHYSTATUS", + "GTXE2_LOGIC_OUTS_B23_7", + "GTXE2_CHANNEL_TXPRBSSEL1", + "GTXE2_IMUX0_7", + "GTXE2_IMUX41_4", + "GTXE2_CHANNEL_TXDATA23", + "GTXE2_CHANNEL_RXDATA14", + "GTXE2_CHANNEL_RXDATA26", + "GTXE2_IMUX0_6", + "GTXE2_IMUX33_0", + "GTXE2_LOGIC_OUTS_B15_2", + "GTXE2_LOGIC_OUTS_B3_9", + "GTXE2_CHANNEL_DRPDO14", + "GTXE2_CHANNEL_TXDETECTRX", + "GTXE2_CHANNEL_RXDATA6", + "GTXE2_CHANNEL_TXDATA17", + "GTXE2_IMUX0_0", + "GTXE2_IMUX47_9", + "GTXE2_IMUX3_8", + "GTXE2_IMUX8_1", + "GTXE2_IMUX28_9", + "GTXE2_IMUX13_10", + "GTXE2_CHANNEL_TXSYSCLKSEL0", + "GTXE2_LOGIC_OUTS_B4_8", + "GTXE2_LOGIC_OUTS_B2_2", + "GTXE2_CHANNEL_GTRXRESET", + "GTXE2_IMUX21_4", + "GTXE2_CHANNEL_RXPHALIGNDONE", + "GTXE2_CHANNEL_RXDATA38", + "GTXE2_LOGIC_OUTS_B15_6", + "GTXE2_CHANNEL_GTRSVD14", + "GTXE2_CHANNEL_TXCHARISK6", + "GTXE2_FAN7_9", + "GTXE2_CHANNEL_RXDATA8", + "GTXE2_CHANNEL_DRPDO2", + "GTXE2_CHANNEL_RXDATA33", + "GTXE2_CHANNEL_PMASCANOUT1", + "GTXE2_LOGIC_OUTS_B18_3", + "GTXE2_LOGIC_OUTS_B11_1", + "GTXE2_CHANNEL_SOUTHREFCLK1", + "GTXE2_CHANNEL_TXDLYUPDOWN", + "GTXE2_IMUX38_2", + "GTXE2_LOGIC_OUTS_B20_9", + "GTXE2_LOGIC_OUTS_B17_3", + "GTXE2_LOGIC_OUTS_B15_5", + "GTXE2_IMUX11_3", + "GTXE2_CHANNEL_TXRUNDISP6", + "GTXE2_CHANNEL_TXPRECURSOR1", + "GTXE2_IMUX16_0", + "GTXE2_LOGIC_OUTS_B18_9", + "GTXE2_BYP2_2", + "GTXE2_CHANNEL_RXOUTCLKPCS", + "GTXE2_IMUX29_1", + "GTXE2_FAN6_6", + "GTXE2_FAN0_4", + "GTXE2_IMUX17_6", + "GTXE2_CHANNEL_RXCHARISCOMMA2", + "GTXE2_CHANNEL_RXPHMONITOR3", + "GTXE2_LOGIC_OUTS_B5_0", + "GTXE2_IMUX10_3", + "GTXE2_BYP4_6", + "GTXE2_CHANNEL_PMARSVDIN0", + "GTXE2_IMUX19_3", + "GTXE2_IMUX13_5", + "GTXE2_IMUX15_2", + "GTXE2_LOGIC_OUTS_B2_7", + "GTXE2_CHANNEL_DRPADDR3", + "GTXE2_CHANNEL_RXELECIDLEMODE1", + "GTXE2_LOGIC_OUTS_B6_3", + "GTXE2_LOGIC_OUTS_B3_8", + "GTXE2_LOGIC_OUTS_B1_6", + "GTXE2_CHANNEL_RXDFEAGCOVRDEN", + "GTXE2_CHANNEL_RXDLYBYPASS", + "GTXE2_CHANNEL_CPLLREFCLKSEL2", + "GTXE2_CHANNEL_RXDATA49", + "GTXE2_IMUX41_3", + "GTXE2_LOGIC_OUTS_B3_7", + "GTXE2_IMUX34_9", + "GTXE2_CHANNEL_RXMONITOROUT2", + "GTXE2_LOGIC_OUTS_B2_3", + "GTXE2_BYP6_0", + "GTXE2_CHANNEL_CLKRSVD0", + "GTXE2_IMUX16_4", + "GTXE2_CHANNEL_TSTIN5", + "GTXE2_CHANNEL_RXNOTINTABLE0", + "GTXE2_LOGIC_OUTS_B22_1", + "GTXE2_IMUX7_4", + "GTXE2_IMUX37_3", + "GTXE2_IMUX12_3", + "GTXE2_CHANNEL_TSTIN16", + "GTXE2_CHANNEL_TXDATA52", + "GTXE2_IMUX20_10", + "GTXE2_CHANNEL_DRPADDR5", + "GTXE2_BYP3_5", + "GTXE2_LOGIC_OUTS_B6_5", + "GTXE2_CHANNEL_TXDATA49", + "GTXE2_CHANNEL_SCANIN2", + "GTXE2_CHANNEL_RXDFEAGCHOLD", + "GTXE2_CHANNEL_TXCHARDISPVAL2", + "GTXE2_IMUX8_6", + "GTXE2_CHANNEL_TXDATA4", + "GTXE2_CTRL0_10", + "GTXE2_IMUX23_2", + "GTXE2_IMUX34_6", + "GTXE2_LOGIC_OUTS_B4_3", + "GTXE2_CHANNEL_RX8B10BEN", + "GTXE2_CHANNEL_RXOUTCLK_2", + "GTXE2_BYP6_1", + "GTXE2_CTRL1_4", + "GTXE2_LOGIC_OUTS_B13_0", + "GTXE2_IMUX26_5", + "GTXE2_IMUX13_0", + "GTXE2_LOGIC_OUTS_B22_2", + "GTXE2_CHANNEL_RXCOMINITDET", + "GTXE2_CHANNEL_TXDLYTESTENB", + "GTXE2_IMUX25_5", + "GTXE2_IMUX45_6", + "GTXE2_LOGIC_OUTS_B14_9", + "GTXE2_CHANNEL_SCANOUT1", + "GTXE2_IMUX22_0", + "GTXE2_IMUX5_3", + "GTXE2_CHANNEL_RXSYSCLKSEL0", + "GTXE2_IMUX22_7", + "GTXE2_LOGIC_OUTS_B23_0", + "GTXE2_IMUX14_3", + "GTXE2_CHANNEL_TXDATA22", + "GTXE2_CHANNEL_RXPHDLYPD", + "GTXE2_IMUX18_2", + "GTXE2_CHANNEL_DRPDI4", + "GTXE2_CHANNEL_RXCHARISK7", + "GTXE2_IMUX24_0", + "GTXE2_CHANNEL_RXDATA37", + "GTXE2_IMUX11_2", + "GTXE2_CHANNEL_TXSYSCLKSEL1", + "GTXE2_CHANNEL_RXRATE2", + "GTXE2_IMUX17_8", + "GTXE2_CHANNEL_RXDATA5", + "GTXE2_CHANNEL_TXDATA25", + "GTXE2_IMUX47_4", + "GTXE2_CHANNEL_PMASCANOUT0", + "GTXE2_IMUX17_2", + "GTXE2_BYP0_1", + "GTXE2_CHANNEL_RXDFETAP5HOLD", + "GTXE2_IMUX5_9", + "GTXE2_CTRL1_9", + "GTXE2_IMUX15_1", + "GTXE2_CHANNEL_RXOUTCLKSEL1", + "GTXE2_CHANNEL_DRPADDR7", + "GTXE2_CLK1_4" + ], + "pips": { + "GTX_CHANNEL_0.GTXE2_IMUX0_8->GTXE2_CHANNEL_PMARSVDIN4": { + "src_wire": "GTXE2_IMUX0_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX12_1->GTXE2_CHANNEL_TXCOMWAKE": { + "src_wire": "GTXE2_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCOMWAKE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO0->GTXE2_LOGIC_OUTS_B0_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX28_1->GTXE2_CHANNEL_TXCOMSAS": { + "src_wire": "GTXE2_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCOMSAS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX25_7->GTXE2_CHANNEL_PCSRSVDIN4": { + "src_wire": "GTXE2_IMUX25_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA18->GTXE2_LOGIC_OUTS_B4_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA18", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX23_8->GTXE2_CHANNEL_RXPRBSSEL2": { + "src_wire": "GTXE2_IMUX23_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA13->GTXE2_LOGIC_OUTS_B7_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA13", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX25_6->GTXE2_CHANNEL_PCSRSVDIN3": { + "src_wire": "GTXE2_IMUX25_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX1_2->GTXE2_CHANNEL_RXMONITORSEL1": { + "src_wire": "GTXE2_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX39_1->GTXE2_CHANNEL_DRPDI4": { + "src_wire": "GTXE2_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT6->GTXE2_LOGIC_OUTS_B13_6": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE1->GTXE2_LOGIC_OUTS_B14_8": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA48->GTXE2_LOGIC_OUTS_B3_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA48", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_3": { + "src_wire": "GTXE2_CHANNEL_TXPHALIGNDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX43_10->GTXE2_CHANNEL_RXLPMHFHOLD": { + "src_wire": "GTXE2_IMUX43_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMHFHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA21->GTXE2_LOGIC_OUTS_B7_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA21", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX13_10->GTXE2_CHANNEL_RXPRBSCNTRESET": { + "src_wire": "GTXE2_IMUX13_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSCNTRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA19->GTXE2_LOGIC_OUTS_B0_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA19", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX21_10->GTXE2_CHANNEL_RXDFEAGCOVRDEN": { + "src_wire": "GTXE2_IMUX21_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX31_2->GTXE2_CHANNEL_TXCHARDISPMODE6": { + "src_wire": "GTXE2_IMUX31_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL1_1->GTXE2_CHANNEL_RXPHDLYRESET": { + "src_wire": "GTXE2_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHDLYRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX26_5->GTXE2_CHANNEL_GTRSVD10": { + "src_wire": "GTXE2_IMUX26_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR4->GTXE2_LOGIC_OUTS_B21_3": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX18_3->GTXE2_CHANNEL_TXDATA16": { + "src_wire": "GTXE2_IMUX18_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA16", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX18_5->GTXE2_CHANNEL_TXDATA8": { + "src_wire": "GTXE2_IMUX18_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT12->GTXE2_LOGIC_OUTS_B9_1": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT12", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX29_3->GTXE2_CHANNEL_TXCHARISK6": { + "src_wire": "GTXE2_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT4->GTXE2_LOGIC_OUTS_B11_4": { + "src_wire": "GTXE2_CHANNEL_TSTOUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX38_1->GTXE2_CHANNEL_DRPDI5": { + "src_wire": "GTXE2_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX20_2->GTXE2_CHANNEL_TXDATA22": { + "src_wire": "GTXE2_IMUX20_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX36_1->GTXE2_CHANNEL_DRPDI13": { + "src_wire": "GTXE2_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA44->GTXE2_LOGIC_OUTS_B6_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA44", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO12->GTXE2_LOGIC_OUTS_B5_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO12", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX8_0->GTXE2_CHANNEL_TXCHARDISPVAL3": { + "src_wire": "GTXE2_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX12_9->GTXE2_CHANNEL_RX8B10BEN": { + "src_wire": "GTXE2_IMUX12_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RX8B10BEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_GTREFCLKMONITOR->GTXE2_LOGIC_OUTS_B23_2": { + "src_wire": "GTXE2_CHANNEL_GTREFCLKMONITOR", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX44_3->GTXE2_CHANNEL_DRPEN": { + "src_wire": "GTXE2_IMUX44_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX17_5->GTXE2_CHANNEL_TXDATA41": { + "src_wire": "GTXE2_IMUX17_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA41", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX25_8->GTXE2_CHANNEL_PCSRSVDIN5": { + "src_wire": "GTXE2_IMUX25_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT6->GTXE2_LOGIC_OUTS_B9_4": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX29_2->GTXE2_CHANNEL_TXCHARDISPMODE2": { + "src_wire": "GTXE2_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX39_10->GTXE2_CHANNEL_PCSRSVDIN23": { + "src_wire": "GTXE2_IMUX39_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT14->GTXE2_LOGIC_OUTS_B16_0": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT14", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX4_4->GTXE2_CHANNEL_TXMAINCURSOR5": { + "src_wire": "GTXE2_IMUX4_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX5_5->GTXE2_CHANNEL_TXSEQUENCE0": { + "src_wire": "GTXE2_IMUX5_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX22_6->GTXE2_CHANNEL_TXDATA38": { + "src_wire": "GTXE2_IMUX22_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA38", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO2->GTXE2_LOGIC_OUTS_B2_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX14_7->GTXE2_CHANNEL_RXPCSRESET": { + "src_wire": "GTXE2_IMUX14_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPCSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX27_8->GTXE2_CHANNEL_RXDFEVPOVRDEN": { + "src_wire": "GTXE2_IMUX27_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEVPOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA31->GTXE2_LOGIC_OUTS_B5_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA31", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR3->GTXE2_LOGIC_OUTS_B22_4": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX18_7->GTXE2_CHANNEL_TXDATA0": { + "src_wire": "GTXE2_IMUX18_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO10->GTXE2_LOGIC_OUTS_B2_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO10", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT8->GTXE2_LOGIC_OUTS_B11_8": { + "src_wire": "GTXE2_CHANNEL_TSTOUT8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX42_8->GTXE2_CHANNEL_GTRSVD5": { + "src_wire": "GTXE2_IMUX42_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX3_8->GTXE2_CHANNEL_TXPRBSSEL0": { + "src_wire": "GTXE2_IMUX3_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX14_8->GTXE2_CHANNEL_RXCDROVRDEN": { + "src_wire": "GTXE2_IMUX14_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDROVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_QPLLCLK->GTXE2_CHANNEL_GTQPLLCLK": { + "src_wire": "GTXE2_CHANNEL_QPLLCLK", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTQPLLCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX28_8->GTXE2_CHANNEL_RXPD1": { + "src_wire": "GTXE2_IMUX28_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX10_2->GTXE2_CHANNEL_TXCHARDISPVAL6": { + "src_wire": "GTXE2_IMUX10_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCLKCORCNT1->GTXE2_LOGIC_OUTS_B20_5": { + "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX31_8->GTXE2_CHANNEL_EYESCANTRIGGER": { + "src_wire": "GTXE2_IMUX31_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_EYESCANTRIGGER", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX30_9->GTXE2_CHANNEL_RXCHBONDMASTER": { + "src_wire": "GTXE2_IMUX30_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDMASTER", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA25->GTXE2_LOGIC_OUTS_B2_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA25", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX44_8->GTXE2_CHANNEL_RXUSERRDY": { + "src_wire": "GTXE2_IMUX44_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXUSERRDY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX19_8->GTXE2_CHANNEL_RXDFEVPHOLD": { + "src_wire": "GTXE2_IMUX19_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEVPHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX17_2->GTXE2_CHANNEL_TXDATA21": { + "src_wire": "GTXE2_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX19_10->GTXE2_CHANNEL_RXCHBONDLEVEL1": { + "src_wire": "GTXE2_IMUX19_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX26_10->GTXE2_CHANNEL_GTRSVD15": { + "src_wire": "GTXE2_IMUX26_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX16_1->GTXE2_CHANNEL_TXDATA56": { + "src_wire": "GTXE2_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA56", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE0->GTXE2_LOGIC_OUTS_B14_10": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXRESETDONE->GTXE2_LOGIC_OUTS_B16_4": { + "src_wire": "GTXE2_CHANNEL_TXRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX14_9->GTXE2_CHANNEL_RXPHALIGN": { + "src_wire": "GTXE2_IMUX14_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHALIGN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX0_10->GTXE2_CHANNEL_RXELECIDLEMODE0": { + "src_wire": "GTXE2_IMUX0_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX18_2->GTXE2_CHANNEL_TXDATA52": { + "src_wire": "GTXE2_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA52", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX20_6->GTXE2_CHANNEL_TXDATA6": { + "src_wire": "GTXE2_IMUX20_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX3_5->GTXE2_CHANNEL_TXDIFFCTRL2": { + "src_wire": "GTXE2_IMUX3_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX24_4->GTXE2_CHANNEL_TSTIN13": { + "src_wire": "GTXE2_IMUX24_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX17_7->GTXE2_CHANNEL_TXDATA34": { + "src_wire": "GTXE2_IMUX17_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA34", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX16_4->GTXE2_CHANNEL_TXDATA12": { + "src_wire": "GTXE2_IMUX16_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO8->GTXE2_LOGIC_OUTS_B0_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBYTEISALIGNED->GTXE2_LOGIC_OUTS_B18_10": { + "src_wire": "GTXE2_CHANNEL_RXBYTEISALIGNED", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK7->GTXE2_LOGIC_OUTS_B12_3": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX44_9->GTXE2_CHANNEL_RXCOMMADETEN": { + "src_wire": "GTXE2_IMUX44_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCOMMADETEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX38_2->GTXE2_CHANNEL_DRPADDR1": { + "src_wire": "GTXE2_IMUX38_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX2_10->GTXE2_CHANNEL_RXOUTCLKSEL2": { + "src_wire": "GTXE2_IMUX2_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX5_1->GTXE2_CHANNEL_TXQPIBIASEN": { + "src_wire": "GTXE2_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXQPIBIASEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX9_5->GTXE2_CHANNEL_PCSRSVDIN10": { + "src_wire": "GTXE2_IMUX9_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX42_9->GTXE2_CHANNEL_GTRSVD6": { + "src_wire": "GTXE2_IMUX42_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX37_8->GTXE2_CHANNEL_RXDFEXYDHOLD": { + "src_wire": "GTXE2_IMUX37_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEXYDHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B17_9": { + "src_wire": "GTXE2_CHANNEL_RXOUTCLKFABRIC", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX37_1->GTXE2_CHANNEL_DRPDI12": { + "src_wire": "GTXE2_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX39_3->GTXE2_CHANNEL_DRPADDR4": { + "src_wire": "GTXE2_IMUX39_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXRATEDONE->GTXE2_LOGIC_OUTS_B23_5": { + "src_wire": "GTXE2_CHANNEL_RXRATEDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR1->GTXE2_LOGIC_OUTS_B22_8": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA5->GTXE2_LOGIC_OUTS_B7_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL0_6->GTXE2_CHANNEL_RXDLYSRESET": { + "src_wire": "GTXE2_CTRL0_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_NORTHREFCLK0->GTXE2_CHANNEL_GTNORTHREFCLK0": { + "src_wire": "GTXE2_CHANNEL_NORTHREFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX5_7->GTXE2_CHANNEL_PMARSVDIN20": { + "src_wire": "GTXE2_IMUX5_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT2->GTXE2_LOGIC_OUTS_B11_2": { + "src_wire": "GTXE2_CHANNEL_TSTOUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA40->GTXE2_LOGIC_OUTS_B3_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA40", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX30_3->GTXE2_CHANNEL_TXPOLARITY": { + "src_wire": "GTXE2_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOLARITY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX24_10->GTXE2_CHANNEL_TSTIN19": { + "src_wire": "GTXE2_IMUX24_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN19", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX21_2->GTXE2_CHANNEL_TXDATA23": { + "src_wire": "GTXE2_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL0_8->GTXE2_CHANNEL_GTRXRESET": { + "src_wire": "GTXE2_CTRL0_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRXRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX41_5->GTXE2_CHANNEL_RESETOVRD": { + "src_wire": "GTXE2_IMUX41_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RESETOVRD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX11_6->GTXE2_CHANNEL_RXRATE2": { + "src_wire": "GTXE2_IMUX11_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXRATE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA51->GTXE2_LOGIC_OUTS_B5_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA51", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX30_10->GTXE2_CHANNEL_RXCHBONDSLAVE": { + "src_wire": "GTXE2_IMUX30_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDSLAVE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_QPLLREFCLK->GTXE2_CHANNEL_GTQPLLREFCLK": { + "src_wire": "GTXE2_CHANNEL_QPLLREFCLK", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTQPLLREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA22->GTXE2_LOGIC_OUTS_B1_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA22", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXELECIDLE->GTXE2_LOGIC_OUTS_B19_8": { + "src_wire": "GTXE2_CHANNEL_RXELECIDLE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT0->GTXE2_LOGIC_OUTS_B13_0": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX29_9->GTXE2_CHANNEL_RXDFETAP5HOLD": { + "src_wire": "GTXE2_IMUX29_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP5HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX26_6->GTXE2_CHANNEL_GTRSVD11": { + "src_wire": "GTXE2_IMUX26_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT5->GTXE2_LOGIC_OUTS_B8_5": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX29_7->GTXE2_CHANNEL_TXCHARISK4": { + "src_wire": "GTXE2_IMUX29_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK2->GTXE2_LOGIC_OUTS_B12_6": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX15_7->GTXE2_CHANNEL_TX8B10BBYPASS0": { + "src_wire": "GTXE2_IMUX15_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CLK0_2->GTXE2_CHANNEL_CPLLLOCKDETCLK": { + "src_wire": "GTXE2_CLK0_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLLOCKDETCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX11_5->GTXE2_CHANNEL_TXDLYHOLD": { + "src_wire": "GTXE2_IMUX11_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX39_6->GTXE2_CHANNEL_TXELECIDLE": { + "src_wire": "GTXE2_IMUX39_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXELECIDLE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX19_3->GTXE2_CHANNEL_TXDATA17": { + "src_wire": "GTXE2_IMUX19_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA17", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXN_PAD->GTXE2_CHANNEL_RXN": { + "src_wire": "GTXE2_CHANNEL_RXN_PAD", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXP->GTXE2_CHANNEL_TXP_PAD": { + "src_wire": "GTXE2_CHANNEL_TXP", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXP_PAD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX2_6->GTXE2_CHANNEL_TXPRECURSOR3": { + "src_wire": "GTXE2_IMUX2_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX24_9->GTXE2_CHANNEL_TSTIN18": { + "src_wire": "GTXE2_IMUX24_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN18", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT8->GTXE2_LOGIC_OUTS_B13_8": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK4->GTXE2_LOGIC_OUTS_B12_9": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX41_1->GTXE2_CHANNEL_TXPOSTCURSORINV": { + "src_wire": "GTXE2_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSORINV", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX13_9->GTXE2_CHANNEL_RXDFETAP5OVRDEN": { + "src_wire": "GTXE2_IMUX13_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX20_1->GTXE2_CHANNEL_TXDATA58": { + "src_wire": "GTXE2_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA58", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX28_3->GTXE2_CHANNEL_DRPWE": { + "src_wire": "GTXE2_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPWE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL1_9->GTXE2_CHANNEL_RXCDRRESET": { + "src_wire": "GTXE2_CTRL1_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA26->GTXE2_LOGIC_OUTS_B4_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA26", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX21_0->GTXE2_CHANNEL_TXDATA31": { + "src_wire": "GTXE2_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA31", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX43_5->GTXE2_CHANNEL_TXDLYUPDOWN": { + "src_wire": "GTXE2_IMUX43_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYUPDOWN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR0->GTXE2_LOGIC_OUTS_B5_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX10_1->GTXE2_CHANNEL_TXPDELECIDLEMODE": { + "src_wire": "GTXE2_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPDELECIDLEMODE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX36_10->GTXE2_CHANNEL_RXDFETAP3HOLD": { + "src_wire": "GTXE2_IMUX36_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP3HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX1_8->GTXE2_CHANNEL_TXOUTCLKSEL2": { + "src_wire": "GTXE2_IMUX1_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CLK1_7->GTXE2_CHANNEL_CLKRSVD2": { + "src_wire": "GTXE2_CLK1_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX13_1->GTXE2_CHANNEL_TXQPISTRONGPDOWN": { + "src_wire": "GTXE2_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX2_3->GTXE2_CHANNEL_DRPADDR8": { + "src_wire": "GTXE2_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR2->GTXE2_LOGIC_OUTS_B2_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX26_7->GTXE2_CHANNEL_GTRSVD12": { + "src_wire": "GTXE2_IMUX26_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL0_9->GTXE2_CHANNEL_RXDFELPMRESET": { + "src_wire": "GTXE2_CTRL0_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFELPMRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCOMINITDET->GTXE2_LOGIC_OUTS_B20_7": { + "src_wire": "GTXE2_CHANNEL_RXCOMINITDET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXSTATUS2->GTXE2_LOGIC_OUTS_B23_8": { + "src_wire": "GTXE2_CHANNEL_RXSTATUS2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX35_8->GTXE2_CHANNEL_RXDFEUTOVRDEN": { + "src_wire": "GTXE2_IMUX35_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEUTOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXSTARTOFSEQ->GTXE2_LOGIC_OUTS_B18_8": { + "src_wire": "GTXE2_CHANNEL_RXSTARTOFSEQ", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA20->GTXE2_LOGIC_OUTS_B3_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA20", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXGEARBOXREADY->GTXE2_LOGIC_OUTS_B23_4": { + "src_wire": "GTXE2_CHANNEL_TXGEARBOXREADY", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX16_0->GTXE2_CHANNEL_TXDATA28": { + "src_wire": "GTXE2_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA28", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA36->GTXE2_LOGIC_OUTS_B6_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA36", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK5->GTXE2_LOGIC_OUTS_B12_7": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL0_5->GTXE2_CHANNEL_GTTXRESET": { + "src_wire": "GTXE2_CTRL0_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTTXRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT9->GTXE2_LOGIC_OUTS_B11_9": { + "src_wire": "GTXE2_CHANNEL_TSTOUT9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX2_4->GTXE2_CHANNEL_TXPOSTCURSOR3": { + "src_wire": "GTXE2_IMUX2_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX37_4->GTXE2_CHANNEL_TXDIFFPD": { + "src_wire": "GTXE2_IMUX37_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX38_4->GTXE2_CHANNEL_TXMARGIN1": { + "src_wire": "GTXE2_IMUX38_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMARGIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CLK1_8->GTXE2_CHANNEL_CLKRSVD3": { + "src_wire": "GTXE2_CLK1_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX35_2->GTXE2_CHANNEL_DRPADDR2": { + "src_wire": "GTXE2_IMUX35_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA39->GTXE2_LOGIC_OUTS_B0_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA39", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX13_7->GTXE2_CHANNEL_TXBUFDIFFCTRL1": { + "src_wire": "GTXE2_IMUX13_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX19_4->GTXE2_CHANNEL_TXDATA45": { + "src_wire": "GTXE2_IMUX19_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA45", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX23_1->GTXE2_CHANNEL_TXDATA27": { + "src_wire": "GTXE2_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA27", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX47_6->GTXE2_CHANNEL_TXRATE0": { + "src_wire": "GTXE2_IMUX47_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXRATE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA32->GTXE2_LOGIC_OUTS_B3_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA32", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX30_7->GTXE2_CHANNEL_TXPCSRESET": { + "src_wire": "GTXE2_IMUX30_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPCSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX1_6->GTXE2_CHANNEL_TXSEQUENCE6": { + "src_wire": "GTXE2_IMUX1_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA52->GTXE2_LOGIC_OUTS_B6_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA52", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCOMWAKEDET->GTXE2_LOGIC_OUTS_B19_9": { + "src_wire": "GTXE2_CHANNEL_RXCOMWAKEDET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CLK1_4->GTXE2_CHANNEL_CLKRSVD0": { + "src_wire": "GTXE2_CLK1_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX40_3->GTXE2_CHANNEL_TSTIN2": { + "src_wire": "GTXE2_IMUX40_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX0_5->GTXE2_CHANNEL_TXSEQUENCE3": { + "src_wire": "GTXE2_IMUX0_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CLK0_6->GTXE2_CHANNEL_RXUSRCLK": { + "src_wire": "GTXE2_CLK0_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXUSRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX10_5->GTXE2_CHANNEL_TXUSERRDY": { + "src_wire": "GTXE2_IMUX10_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXUSERRDY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO1->GTXE2_LOGIC_OUTS_B4_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR1->GTXE2_LOGIC_OUTS_B4_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX31_0->GTXE2_CHANNEL_TXCHARDISPMODE7": { + "src_wire": "GTXE2_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX0_9->GTXE2_CHANNEL_PMARSVDIN3": { + "src_wire": "GTXE2_IMUX0_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX6_8->GTXE2_CHANNEL_TXPRBSSEL1": { + "src_wire": "GTXE2_IMUX6_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA49->GTXE2_LOGIC_OUTS_B7_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA49", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX31_6->GTXE2_CHANNEL_TXCHARDISPMODE4": { + "src_wire": "GTXE2_IMUX31_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX21_6->GTXE2_CHANNEL_TXDATA7": { + "src_wire": "GTXE2_IMUX21_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT2->GTXE2_LOGIC_OUTS_B8_8": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX21_7->GTXE2_CHANNEL_TXDATA32": { + "src_wire": "GTXE2_IMUX21_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA32", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA6->GTXE2_LOGIC_OUTS_B1_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO3->GTXE2_LOGIC_OUTS_B6_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX38_8->GTXE2_CHANNEL_RXPRBSSEL1": { + "src_wire": "GTXE2_IMUX38_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT6->GTXE2_LOGIC_OUTS_B11_6": { + "src_wire": "GTXE2_CHANNEL_TSTOUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA8->GTXE2_LOGIC_OUTS_B6_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX4_8->GTXE2_CHANNEL_TXOUTCLKSEL1": { + "src_wire": "GTXE2_IMUX4_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX45_10->GTXE2_CHANNEL_RXMONITORSEL0": { + "src_wire": "GTXE2_IMUX45_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXVALID->GTXE2_LOGIC_OUTS_B20_9": { + "src_wire": "GTXE2_CHANNEL_RXVALID", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX35_0->GTXE2_CHANNEL_DRPDI2": { + "src_wire": "GTXE2_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX19_1->GTXE2_CHANNEL_TXDATA25": { + "src_wire": "GTXE2_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA25", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX7_7->GTXE2_CHANNEL_TXPRECURSOR4": { + "src_wire": "GTXE2_IMUX7_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA1->GTXE2_LOGIC_OUTS_B15_7": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX19_0->GTXE2_CHANNEL_TXDATA61": { + "src_wire": "GTXE2_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA61", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXQPISENP->GTXE2_LOGIC_OUTS_B15_1": { + "src_wire": "GTXE2_CHANNEL_RXQPISENP", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX26_8->GTXE2_CHANNEL_GTRSVD13": { + "src_wire": "GTXE2_IMUX26_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX42_2->GTXE2_CHANNEL_RXSYSCLKSEL1": { + "src_wire": "GTXE2_IMUX42_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_SOUTHREFCLK1->GTXE2_CHANNEL_GTSOUTHREFCLK1": { + "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL1_10->GTXE2_CHANNEL_RXOOBRESET": { + "src_wire": "GTXE2_CTRL1_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOOBRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT1->GTXE2_LOGIC_OUTS_B9_9": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX11_10->GTXE2_CHANNEL_RXLPMLFHOLD": { + "src_wire": "GTXE2_IMUX11_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMLFHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX28_6->GTXE2_CHANNEL_RXDLYEN": { + "src_wire": "GTXE2_IMUX28_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO5->GTXE2_LOGIC_OUTS_B1_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX25_10->GTXE2_CHANNEL_PCSRSVDIN7": { + "src_wire": "GTXE2_IMUX25_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX6_5->GTXE2_CHANNEL_TXDIFFCTRL1": { + "src_wire": "GTXE2_IMUX6_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX16_2->GTXE2_CHANNEL_TXDATA20": { + "src_wire": "GTXE2_IMUX16_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK1->GTXE2_LOGIC_OUTS_B12_8": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX23_4->GTXE2_CHANNEL_TXDATA47": { + "src_wire": "GTXE2_IMUX23_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA47", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX35_5->GTXE2_CHANNEL_TXDEEMPH": { + "src_wire": "GTXE2_IMUX35_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDEEMPH", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX39_2->GTXE2_CHANNEL_DRPADDR0": { + "src_wire": "GTXE2_IMUX39_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_4": { + "src_wire": "GTXE2_CHANNEL_RXPHALIGNDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA47->GTXE2_LOGIC_OUTS_B0_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA47", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX13_8->GTXE2_CHANNEL_RXOSOVRDEN": { + "src_wire": "GTXE2_IMUX13_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOSOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CLK1_1->GTXE2_CHANNEL_DRPCLK": { + "src_wire": "GTXE2_CLK1_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX15_6->GTXE2_CHANNEL_RXRATE0": { + "src_wire": "GTXE2_IMUX15_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXRATE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT10->GTXE2_LOGIC_OUTS_B13_10": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT10", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA15->GTXE2_LOGIC_OUTS_B5_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA15", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX16_6->GTXE2_CHANNEL_TXDATA4": { + "src_wire": "GTXE2_IMUX16_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX22_0->GTXE2_CHANNEL_TXDATA62": { + "src_wire": "GTXE2_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA62", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX24_5->GTXE2_CHANNEL_TSTIN14": { + "src_wire": "GTXE2_IMUX24_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX30_8->GTXE2_CHANNEL_RXCDRHOLD": { + "src_wire": "GTXE2_IMUX30_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX38_6->GTXE2_CHANNEL_TXPD0": { + "src_wire": "GTXE2_IMUX38_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXOUTCLKPCS->GTXE2_LOGIC_OUTS_B17_4": { + "src_wire": "GTXE2_CHANNEL_TXOUTCLKPCS", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX9_1->GTXE2_CHANNEL_RXPHDLYPD": { + "src_wire": "GTXE2_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHDLYPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT0->GTXE2_LOGIC_OUTS_B9_10": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXSTATUS1->GTXE2_LOGIC_OUTS_B17_8": { + "src_wire": "GTXE2_CHANNEL_RXSTATUS1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA3->GTXE2_LOGIC_OUTS_B15_3": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA14->GTXE2_LOGIC_OUTS_B1_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA14", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX34_8->GTXE2_CHANNEL_RXLPMEN": { + "src_wire": "GTXE2_IMUX34_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX18_0->GTXE2_CHANNEL_TXDATA60": { + "src_wire": "GTXE2_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA60", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA54->GTXE2_LOGIC_OUTS_B4_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA54", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA61->GTXE2_LOGIC_OUTS_B2_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA61", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX39_4->GTXE2_CHANNEL_TXMARGIN0": { + "src_wire": "GTXE2_IMUX39_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMARGIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX23_2->GTXE2_CHANNEL_TXDATA55": { + "src_wire": "GTXE2_IMUX23_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA55", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA62->GTXE2_LOGIC_OUTS_B4_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA62", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXSTATUS0->GTXE2_LOGIC_OUTS_B21_8": { + "src_wire": "GTXE2_CHANNEL_RXSTATUS0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX7_3->GTXE2_CHANNEL_TXPOSTCURSOR4": { + "src_wire": "GTXE2_IMUX7_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX8_2->GTXE2_CHANNEL_TXCHARDISPVAL2": { + "src_wire": "GTXE2_IMUX8_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX7_0->GTXE2_CHANNEL_TXPISOPD": { + "src_wire": "GTXE2_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPISOPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX42_10->GTXE2_CHANNEL_GTRSVD7": { + "src_wire": "GTXE2_IMUX42_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX24_7->GTXE2_CHANNEL_TSTIN16": { + "src_wire": "GTXE2_IMUX24_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN16", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA6->GTXE2_LOGIC_OUTS_B15_6": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX4_10->GTXE2_CHANNEL_RXOUTCLKSEL0": { + "src_wire": "GTXE2_IMUX4_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPRDY->GTXE2_LOGIC_OUTS_B20_0": { + "src_wire": "GTXE2_CHANNEL_DRPRDY", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX12_5->GTXE2_CHANNEL_TXDLYOVRDEN": { + "src_wire": "GTXE2_IMUX12_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA7->GTXE2_LOGIC_OUTS_B5_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX1_9->GTXE2_CHANNEL_PMARSVDIN2": { + "src_wire": "GTXE2_IMUX1_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX0_6->GTXE2_CHANNEL_PMARSVDIN24": { + "src_wire": "GTXE2_IMUX0_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX28_10->GTXE2_CHANNEL_RXDFETAP2OVRDEN": { + "src_wire": "GTXE2_IMUX28_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT1->GTXE2_LOGIC_OUTS_B13_1": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX42_3->GTXE2_CHANNEL_GTRSVD0": { + "src_wire": "GTXE2_IMUX42_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX17_0->GTXE2_CHANNEL_TXDATA29": { + "src_wire": "GTXE2_IMUX17_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA29", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CLK1_6->GTXE2_CHANNEL_GTGREFCLK": { + "src_wire": "GTXE2_CLK1_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTGREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX9_6->GTXE2_CHANNEL_PCSRSVDIN11": { + "src_wire": "GTXE2_IMUX9_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE3->GTXE2_LOGIC_OUTS_B14_4": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE4->GTXE2_LOGIC_OUTS_B14_9": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX41_6->GTXE2_CHANNEL_RXPHALIGNEN": { + "src_wire": "GTXE2_IMUX41_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT3->GTXE2_LOGIC_OUTS_B9_7": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX44_1->GTXE2_CHANNEL_TXCOMINIT": { + "src_wire": "GTXE2_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCOMINIT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE6->GTXE2_LOGIC_OUTS_B14_5": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX22_2->GTXE2_CHANNEL_TXDATA54": { + "src_wire": "GTXE2_IMUX22_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA54", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT9->GTXE2_LOGIC_OUTS_B13_9": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX33_1->GTXE2_CHANNEL_DRPDI14": { + "src_wire": "GTXE2_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR7->GTXE2_LOGIC_OUTS_B22_3": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATAVALID->GTXE2_LOGIC_OUTS_B19_5": { + "src_wire": "GTXE2_CHANNEL_RXDATAVALID", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX29_5->GTXE2_CHANNEL_TXCHARISK5": { + "src_wire": "GTXE2_IMUX29_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL1_8->GTXE2_CHANNEL_RXCDRRESETRSV": { + "src_wire": "GTXE2_CTRL1_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRRESETRSV", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX20_7->GTXE2_CHANNEL_TXDATA33": { + "src_wire": "GTXE2_IMUX20_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA33", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX0_3->GTXE2_CHANNEL_TXMAINCURSOR3": { + "src_wire": "GTXE2_IMUX0_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX18_9->GTXE2_CHANNEL_RXCHBONDI0": { + "src_wire": "GTXE2_IMUX18_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX35_9->GTXE2_CHANNEL_RXDFELFHOLD": { + "src_wire": "GTXE2_IMUX35_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFELFHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX17_9->GTXE2_CHANNEL_RXCHBONDEN": { + "src_wire": "GTXE2_IMUX17_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO4->GTXE2_LOGIC_OUTS_B5_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX34_9->GTXE2_CHANNEL_RXPCOMMAALIGNEN": { + "src_wire": "GTXE2_IMUX34_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA1->GTXE2_LOGIC_OUTS_B2_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX9_8->GTXE2_CHANNEL_PCSRSVDIN13": { + "src_wire": "GTXE2_IMUX9_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX31_5->GTXE2_CHANNEL_TXCHARISK1": { + "src_wire": "GTXE2_IMUX31_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX34_3->GTXE2_CHANNEL_DRPADDR7": { + "src_wire": "GTXE2_IMUX34_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX32_2->GTXE2_CHANNEL_TXINHIBIT": { + "src_wire": "GTXE2_IMUX32_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXINHIBIT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXPHINITDONE->GTXE2_LOGIC_OUTS_B17_0": { + "src_wire": "GTXE2_CHANNEL_TXPHINITDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXQPISENP->GTXE2_LOGIC_OUTS_B8_3": { + "src_wire": "GTXE2_CHANNEL_TXQPISENP", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX22_7->GTXE2_CHANNEL_TXDATA2": { + "src_wire": "GTXE2_IMUX22_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX8_4->GTXE2_CHANNEL_TXCHARDISPVAL1": { + "src_wire": "GTXE2_IMUX8_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXRESETDONE->GTXE2_LOGIC_OUTS_B20_8": { + "src_wire": "GTXE2_CHANNEL_RXRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR4->GTXE2_LOGIC_OUTS_B16_3": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B17_3": { + "src_wire": "GTXE2_CHANNEL_TXDLYSRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR3->GTXE2_LOGIC_OUTS_B3_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA30->GTXE2_LOGIC_OUTS_B1_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA30", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE5->GTXE2_LOGIC_OUTS_B14_7": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX14_6->GTXE2_CHANNEL_RXRATE1": { + "src_wire": "GTXE2_IMUX14_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXRATE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX2_9->GTXE2_CHANNEL_RXMCOMMAALIGNEN": { + "src_wire": "GTXE2_IMUX2_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX25_4->GTXE2_CHANNEL_PCSRSVDIN1": { + "src_wire": "GTXE2_IMUX25_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX45_2->GTXE2_CHANNEL_RXSYSCLKSEL0": { + "src_wire": "GTXE2_IMUX45_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX3_4->GTXE2_CHANNEL_TXPOSTCURSOR2": { + "src_wire": "GTXE2_IMUX3_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX32_8->GTXE2_CHANNEL_RXDLYBYPASS": { + "src_wire": "GTXE2_IMUX32_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYBYPASS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA17->GTXE2_LOGIC_OUTS_B2_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA17", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX42_6->GTXE2_CHANNEL_GTRSVD3": { + "src_wire": "GTXE2_IMUX42_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CLK0_4->GTXE2_CHANNEL_TXUSRCLK": { + "src_wire": "GTXE2_CLK0_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXUSRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX18_1->GTXE2_CHANNEL_TXDATA24": { + "src_wire": "GTXE2_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX24_8->GTXE2_CHANNEL_TSTIN17": { + "src_wire": "GTXE2_IMUX24_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN17", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX16_7->GTXE2_CHANNEL_TXDATA35": { + "src_wire": "GTXE2_IMUX16_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA35", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX40_9->GTXE2_CHANNEL_TSTIN8": { + "src_wire": "GTXE2_IMUX40_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX8_7->GTXE2_CHANNEL_TX8B10BBYPASS4": { + "src_wire": "GTXE2_IMUX8_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX44_5->GTXE2_CHANNEL_TXDLYBYPASS": { + "src_wire": "GTXE2_IMUX44_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYBYPASS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CLK0_7->GTXE2_CHANNEL_RXUSRCLK2": { + "src_wire": "GTXE2_CLK0_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXUSRCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX2_5->GTXE2_CHANNEL_TXDIFFCTRL3": { + "src_wire": "GTXE2_IMUX2_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX18_10->GTXE2_CHANNEL_RXCHBONDLEVEL0": { + "src_wire": "GTXE2_IMUX18_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX12_2->GTXE2_CHANNEL_TXHEADER1": { + "src_wire": "GTXE2_IMUX12_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXHEADER1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT0->GTXE2_LOGIC_OUTS_B11_0": { + "src_wire": "GTXE2_CHANNEL_TSTOUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT1->GTXE2_LOGIC_OUTS_B8_9": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCOMMADET->GTXE2_LOGIC_OUTS_B19_7": { + "src_wire": "GTXE2_CHANNEL_RXCOMMADET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX1_4->GTXE2_CHANNEL_TXMAINCURSOR6": { + "src_wire": "GTXE2_IMUX1_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA24->GTXE2_LOGIC_OUTS_B6_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA24", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX19_2->GTXE2_CHANNEL_TXDATA53": { + "src_wire": "GTXE2_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA53", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX25_2->GTXE2_CHANNEL_TXPHALIGN": { + "src_wire": "GTXE2_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHALIGN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA37->GTXE2_LOGIC_OUTS_B2_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA37", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX20_4->GTXE2_CHANNEL_TXDATA14": { + "src_wire": "GTXE2_IMUX20_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX18_6->GTXE2_CHANNEL_TXDATA36": { + "src_wire": "GTXE2_IMUX18_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA36", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX9_10->GTXE2_CHANNEL_PCSRSVDIN15": { + "src_wire": "GTXE2_IMUX9_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX10_4->GTXE2_CHANNEL_TXCHARDISPVAL5": { + "src_wire": "GTXE2_IMUX10_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX33_0->GTXE2_CHANNEL_DRPDI10": { + "src_wire": "GTXE2_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX17_1->GTXE2_CHANNEL_TXDATA57": { + "src_wire": "GTXE2_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA57", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX12_8->GTXE2_CHANNEL_RXSLIDE": { + "src_wire": "GTXE2_IMUX12_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXSLIDE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX24_6->GTXE2_CHANNEL_TSTIN15": { + "src_wire": "GTXE2_IMUX24_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX40_4->GTXE2_CHANNEL_TSTIN3": { + "src_wire": "GTXE2_IMUX40_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX5_3->GTXE2_CHANNEL_TXMAINCURSOR0": { + "src_wire": "GTXE2_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT13->GTXE2_LOGIC_OUTS_B9_2": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT13", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA33->GTXE2_LOGIC_OUTS_B7_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA33", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX40_1->GTXE2_CHANNEL_TSTIN0": { + "src_wire": "GTXE2_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT6->GTXE2_LOGIC_OUTS_B8_4": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_EYESCANDATAERROR->GTXE2_LOGIC_OUTS_B20_10": { + "src_wire": "GTXE2_CHANNEL_EYESCANDATAERROR", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX18_4->GTXE2_CHANNEL_TXDATA44": { + "src_wire": "GTXE2_IMUX18_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA44", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX38_3->GTXE2_CHANNEL_DRPADDR5": { + "src_wire": "GTXE2_IMUX38_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX23_6->GTXE2_CHANNEL_TXDATA39": { + "src_wire": "GTXE2_IMUX23_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA39", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA2->GTXE2_LOGIC_OUTS_B15_5": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHANISALIGNED->GTXE2_LOGIC_OUTS_B18_9": { + "src_wire": "GTXE2_CHANNEL_RXCHANISALIGNED", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX40_6->GTXE2_CHANNEL_TSTIN5": { + "src_wire": "GTXE2_IMUX40_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX28_2->GTXE2_CHANNEL_CPLLLOCKEN": { + "src_wire": "GTXE2_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLLOCKEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX19_9->GTXE2_CHANNEL_RXCHBONDI1": { + "src_wire": "GTXE2_IMUX19_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT5->GTXE2_LOGIC_OUTS_B11_5": { + "src_wire": "GTXE2_CHANNEL_TSTOUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA12->GTXE2_LOGIC_OUTS_B3_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA12", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPRBSERR->GTXE2_LOGIC_OUTS_B20_6": { + "src_wire": "GTXE2_CHANNEL_RXPRBSERR", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX23_0->GTXE2_CHANNEL_TXDATA63": { + "src_wire": "GTXE2_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA63", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR4->GTXE2_LOGIC_OUTS_B22_9": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX7_5->GTXE2_CHANNEL_TXDIFFCTRL0": { + "src_wire": "GTXE2_IMUX7_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX45_8->GTXE2_CHANNEL_EYESCANRESET": { + "src_wire": "GTXE2_IMUX45_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_EYESCANRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX17_4->GTXE2_CHANNEL_TXDATA13": { + "src_wire": "GTXE2_IMUX17_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT11->GTXE2_LOGIC_OUTS_B9_0": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT11", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX39_0->GTXE2_CHANNEL_DRPDI0": { + "src_wire": "GTXE2_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXOUTCLKPCS->GTXE2_LOGIC_OUTS_B21_9": { + "src_wire": "GTXE2_CHANNEL_RXOUTCLKPCS", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA4->GTXE2_LOGIC_OUTS_B3_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX3_7->GTXE2_CHANNEL_RXPD0": { + "src_wire": "GTXE2_IMUX3_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL1_6->GTXE2_CHANNEL_RXBUFRESET": { + "src_wire": "GTXE2_CTRL1_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXBUFRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA58->GTXE2_LOGIC_OUTS_B1_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA58", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX21_8->GTXE2_CHANNEL_RXDFEXYDOVRDEN": { + "src_wire": "GTXE2_IMUX21_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX40_7->GTXE2_CHANNEL_TSTIN6": { + "src_wire": "GTXE2_IMUX40_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B22_1": { + "src_wire": "GTXE2_CHANNEL_RXDLYSRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX21_9->GTXE2_CHANNEL_RXDFETAP4OVRDEN": { + "src_wire": "GTXE2_IMUX21_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA53->GTXE2_LOGIC_OUTS_B2_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA53", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO13->GTXE2_LOGIC_OUTS_B1_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO13", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR0->GTXE2_LOGIC_OUTS_B0_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B23_3": { + "src_wire": "GTXE2_CHANNEL_TXOUTCLKFABRIC", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX34_2->GTXE2_CHANNEL_DRPADDR3": { + "src_wire": "GTXE2_IMUX34_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO14->GTXE2_LOGIC_OUTS_B7_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO14", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA10->GTXE2_LOGIC_OUTS_B4_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA10", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX35_6->GTXE2_CHANNEL_TXPD1": { + "src_wire": "GTXE2_IMUX35_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX5_4->GTXE2_CHANNEL_TXMAINCURSOR4": { + "src_wire": "GTXE2_IMUX5_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX43_6->GTXE2_CHANNEL_TXRATE2": { + "src_wire": "GTXE2_IMUX43_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXRATE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCLKCORCNT0->GTXE2_LOGIC_OUTS_B18_5": { + "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX5_6->GTXE2_CHANNEL_TXSEQUENCE4": { + "src_wire": "GTXE2_IMUX5_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLFBCLKLOST->GTXE2_LOGIC_OUTS_B8_1": { + "src_wire": "GTXE2_CHANNEL_CPLLFBCLKLOST", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX9_9->GTXE2_CHANNEL_PCSRSVDIN14": { + "src_wire": "GTXE2_IMUX9_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA56->GTXE2_LOGIC_OUTS_B3_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA56", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX22_10->GTXE2_CHANNEL_RXCHBONDLEVEL2": { + "src_wire": "GTXE2_IMUX22_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA50->GTXE2_LOGIC_OUTS_B1_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA50", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_SOUTHREFCLK0->GTXE2_CHANNEL_GTSOUTHREFCLK0": { + "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR6->GTXE2_LOGIC_OUTS_B22_5": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX45_3->GTXE2_CHANNEL_TXDLYSRESET": { + "src_wire": "GTXE2_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCDRLOCK->GTXE2_LOGIC_OUTS_B17_5": { + "src_wire": "GTXE2_CHANNEL_RXCDRLOCK", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX28_4->GTXE2_CHANNEL_TXSYSCLKSEL1": { + "src_wire": "GTXE2_IMUX28_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX22_9->GTXE2_CHANNEL_RXCHBONDI2": { + "src_wire": "GTXE2_IMUX22_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA5->GTXE2_LOGIC_OUTS_B15_8": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO2->GTXE2_LOGIC_OUTS_B16_8": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT3->GTXE2_LOGIC_OUTS_B11_3": { + "src_wire": "GTXE2_CHANNEL_TSTOUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXBUFSTATUS1->GTXE2_LOGIC_OUTS_B21_2": { + "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_REFCLK0->GTXE2_CHANNEL_GTREFCLK0": { + "src_wire": "GTXE2_CHANNEL_REFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX23_7->GTXE2_CHANNEL_TXDATA3": { + "src_wire": "GTXE2_IMUX23_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR5->GTXE2_LOGIC_OUTS_B22_7": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA42->GTXE2_LOGIC_OUTS_B1_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA42", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX2_8->GTXE2_CHANNEL_RXGEARBOXSLIP": { + "src_wire": "GTXE2_IMUX2_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXGEARBOXSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX31_4->GTXE2_CHANNEL_TXCHARDISPMODE5": { + "src_wire": "GTXE2_IMUX31_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA23->GTXE2_LOGIC_OUTS_B5_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA23", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX34_1->GTXE2_CHANNEL_DRPDI7": { + "src_wire": "GTXE2_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_REFCLK1->GTXE2_CHANNEL_GTREFCLK1": { + "src_wire": "GTXE2_CHANNEL_REFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX21_3->GTXE2_CHANNEL_TXDATA51": { + "src_wire": "GTXE2_IMUX21_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA51", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL0_7->GTXE2_CHANNEL_RXCDRFREQRESET": { + "src_wire": "GTXE2_CTRL0_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRFREQRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX4_5->GTXE2_CHANNEL_TXSEQUENCE1": { + "src_wire": "GTXE2_IMUX4_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX10_9->GTXE2_CHANNEL_RXQPIEN": { + "src_wire": "GTXE2_IMUX10_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXQPIEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX9_3->GTXE2_CHANNEL_PCSRSVDIN8": { + "src_wire": "GTXE2_IMUX9_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA63->GTXE2_LOGIC_OUTS_B0_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA63", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX17_3->GTXE2_CHANNEL_TXDATA49": { + "src_wire": "GTXE2_IMUX17_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA49", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXN->GTXE2_CHANNEL_TXN_PAD": { + "src_wire": "GTXE2_CHANNEL_TXN", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXN_PAD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX38_0->GTXE2_CHANNEL_DRPDI1": { + "src_wire": "GTXE2_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX14_5->GTXE2_CHANNEL_TXDLYEN": { + "src_wire": "GTXE2_IMUX14_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX25_3->GTXE2_CHANNEL_PCSRSVDIN0": { + "src_wire": "GTXE2_IMUX25_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX38_5->GTXE2_CHANNEL_TXSWING": { + "src_wire": "GTXE2_IMUX38_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSWING", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX31_7->GTXE2_CHANNEL_TXCHARISK0": { + "src_wire": "GTXE2_IMUX31_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX35_1->GTXE2_CHANNEL_DRPDI6": { + "src_wire": "GTXE2_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX22_5->GTXE2_CHANNEL_TXDATA10": { + "src_wire": "GTXE2_IMUX22_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO7->GTXE2_LOGIC_OUTS_B3_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX0_2->GTXE2_CHANNEL_TX8B10BEN": { + "src_wire": "GTXE2_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX8_6->GTXE2_CHANNEL_TXCHARDISPVAL0": { + "src_wire": "GTXE2_IMUX8_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX37_0->GTXE2_CHANNEL_DRPDI8": { + "src_wire": "GTXE2_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL1_5->GTXE2_CHANNEL_CFGRESET": { + "src_wire": "GTXE2_CTRL1_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CFGRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX26_9->GTXE2_CHANNEL_GTRSVD14": { + "src_wire": "GTXE2_IMUX26_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE7->GTXE2_LOGIC_OUTS_B14_3": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCOMSASDET->GTXE2_LOGIC_OUTS_B18_7": { + "src_wire": "GTXE2_CHANNEL_RXCOMSASDET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBYTEREALIGN->GTXE2_LOGIC_OUTS_B10_10": { + "src_wire": "GTXE2_CHANNEL_RXBYTEREALIGN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA46->GTXE2_LOGIC_OUTS_B4_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA46", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_GTTXOUTCLK_0->GTXE2_CHANNEL_TXOUTCLK_0": { + "src_wire": "GTXE2_CHANNEL_GTTXOUTCLK_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX26_3->GTXE2_CHANNEL_GTRSVD8": { + "src_wire": "GTXE2_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXCOMFINISH->GTXE2_LOGIC_OUTS_B16_5": { + "src_wire": "GTXE2_CHANNEL_TXCOMFINISH", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX8_8->GTXE2_CHANNEL_RXDDIEN": { + "src_wire": "GTXE2_IMUX8_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDDIEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX1_7->GTXE2_CHANNEL_PMARSVDIN22": { + "src_wire": "GTXE2_IMUX1_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX19_6->GTXE2_CHANNEL_TXDATA37": { + "src_wire": "GTXE2_IMUX19_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA37", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBUFSTATUS1->GTXE2_LOGIC_OUTS_B19_10": { + "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX5_10->GTXE2_CHANNEL_RXOUTCLKSEL1": { + "src_wire": "GTXE2_IMUX5_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CLK0_5->GTXE2_CHANNEL_TXUSRCLK2": { + "src_wire": "GTXE2_CLK0_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXUSRCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX12_10->GTXE2_CHANNEL_RXDFETAP3OVRDEN": { + "src_wire": "GTXE2_IMUX12_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX27_5->GTXE2_CHANNEL_TXPHINIT": { + "src_wire": "GTXE2_IMUX27_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHINIT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX5_8->GTXE2_CHANNEL_TXOUTCLKSEL0": { + "src_wire": "GTXE2_IMUX5_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX3_6->GTXE2_CHANNEL_TXPRECURSOR2": { + "src_wire": "GTXE2_IMUX3_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX40_5->GTXE2_CHANNEL_TSTIN4": { + "src_wire": "GTXE2_IMUX40_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX9_2->GTXE2_CHANNEL_TXHEADER2": { + "src_wire": "GTXE2_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXHEADER2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX22_3->GTXE2_CHANNEL_TXDATA18": { + "src_wire": "GTXE2_IMUX22_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA18", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO1->GTXE2_LOGIC_OUTS_B16_9": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR3->GTXE2_LOGIC_OUTS_B6_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX24_2->GTXE2_CHANNEL_TSTIN11": { + "src_wire": "GTXE2_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX27_9->GTXE2_CHANNEL_RXDFELFOVRDEN": { + "src_wire": "GTXE2_IMUX27_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFELFOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR2->GTXE2_LOGIC_OUTS_B7_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBUFSTATUS2->GTXE2_LOGIC_OUTS_B17_10": { + "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR2->GTXE2_LOGIC_OUTS_B22_6": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX14_10->GTXE2_CHANNEL_RXPHOVRDEN": { + "src_wire": "GTXE2_IMUX14_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX4_1->GTXE2_CHANNEL_TXPRECURSORINV": { + "src_wire": "GTXE2_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSORINV", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX9_4->GTXE2_CHANNEL_PCSRSVDIN9": { + "src_wire": "GTXE2_IMUX9_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX20_3->GTXE2_CHANNEL_TXDATA50": { + "src_wire": "GTXE2_IMUX20_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA50", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX29_4->GTXE2_CHANNEL_TXCHARDISPMODE1": { + "src_wire": "GTXE2_IMUX29_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT7->GTXE2_LOGIC_OUTS_B13_7": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX15_4->GTXE2_CHANNEL_TXPRBSFORCEERR": { + "src_wire": "GTXE2_IMUX15_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSFORCEERR", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX4_9->GTXE2_CHANNEL_PMARSVDIN1": { + "src_wire": "GTXE2_IMUX4_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX17_6->GTXE2_CHANNEL_TXDATA5": { + "src_wire": "GTXE2_IMUX17_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_GTRXOUTCLK_0->GTXE2_CHANNEL_RXOUTCLK_0": { + "src_wire": "GTXE2_CHANNEL_GTRXOUTCLK_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX10_0->GTXE2_CHANNEL_TXCHARDISPVAL7": { + "src_wire": "GTXE2_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT7->GTXE2_LOGIC_OUTS_B11_7": { + "src_wire": "GTXE2_CHANNEL_TSTOUT7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXQPISENN->GTXE2_LOGIC_OUTS_B20_3": { + "src_wire": "GTXE2_CHANNEL_TXQPISENN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX15_3->GTXE2_CHANNEL_TX8B10BBYPASS2": { + "src_wire": "GTXE2_IMUX15_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX5_9->GTXE2_CHANNEL_PMARSVDIN0": { + "src_wire": "GTXE2_IMUX5_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX1_3->GTXE2_CHANNEL_TXMAINCURSOR2": { + "src_wire": "GTXE2_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX33_2->GTXE2_CHANNEL_TXPHALIGNEN": { + "src_wire": "GTXE2_IMUX33_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX29_6->GTXE2_CHANNEL_TXCHARDISPMODE0": { + "src_wire": "GTXE2_IMUX29_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX16_3->GTXE2_CHANNEL_TXDATA48": { + "src_wire": "GTXE2_IMUX16_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA48", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX4_7->GTXE2_CHANNEL_PMARSVDIN21": { + "src_wire": "GTXE2_IMUX4_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX42_7->GTXE2_CHANNEL_GTRSVD4": { + "src_wire": "GTXE2_IMUX42_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK3->GTXE2_LOGIC_OUTS_B12_4": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT15->GTXE2_LOGIC_OUTS_B16_1": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT15", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX12_4->GTXE2_CHANNEL_TXPHOVRDEN": { + "src_wire": "GTXE2_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXHEADERVALID->GTXE2_LOGIC_OUTS_B23_7": { + "src_wire": "GTXE2_CHANNEL_RXHEADERVALID", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX15_2->GTXE2_CHANNEL_CPLLREFCLKSEL0": { + "src_wire": "GTXE2_IMUX15_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA3->GTXE2_LOGIC_OUTS_B0_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX42_5->GTXE2_CHANNEL_GTRSVD2": { + "src_wire": "GTXE2_IMUX42_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX6_4->GTXE2_CHANNEL_TXPOSTCURSOR1": { + "src_wire": "GTXE2_IMUX6_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX29_8->GTXE2_CHANNEL_RXOSHOLD": { + "src_wire": "GTXE2_IMUX29_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOSHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX39_5->GTXE2_CHANNEL_TXDETECTRX": { + "src_wire": "GTXE2_IMUX39_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDETECTRX", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX22_8->GTXE2_CHANNEL_RXPRBSSEL0": { + "src_wire": "GTXE2_IMUX22_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX1_10->GTXE2_CHANNEL_RXELECIDLEMODE1": { + "src_wire": "GTXE2_IMUX1_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX36_2->GTXE2_CHANNEL_CPLLPD": { + "src_wire": "GTXE2_IMUX36_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX24_3->GTXE2_CHANNEL_TSTIN12": { + "src_wire": "GTXE2_IMUX24_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA11->GTXE2_LOGIC_OUTS_B0_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA11", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX11_8->GTXE2_CHANNEL_RXDFEVSEN": { + "src_wire": "GTXE2_IMUX11_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEVSEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA38->GTXE2_LOGIC_OUTS_B4_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA38", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR1->GTXE2_LOGIC_OUTS_B1_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX20_5->GTXE2_CHANNEL_TXDATA42": { + "src_wire": "GTXE2_IMUX20_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA42", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX7_8->GTXE2_CHANNEL_TXPRBSSEL2": { + "src_wire": "GTXE2_IMUX7_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX46_9->GTXE2_CHANNEL_LOOPBACK1": { + "src_wire": "GTXE2_IMUX46_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_LOOPBACK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX7_6->GTXE2_CHANNEL_TXPRECURSOR0": { + "src_wire": "GTXE2_IMUX7_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX16_5->GTXE2_CHANNEL_TXDATA40": { + "src_wire": "GTXE2_IMUX16_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA40", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT1->GTXE2_LOGIC_OUTS_B11_1": { + "src_wire": "GTXE2_CHANNEL_TSTOUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX45_9->GTXE2_CHANNEL_RXDFEXYDEN": { + "src_wire": "GTXE2_IMUX45_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEXYDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHANREALIGN->GTXE2_LOGIC_OUTS_B23_9": { + "src_wire": "GTXE2_CHANNEL_RXCHANREALIGN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE2->GTXE2_LOGIC_OUTS_B14_6": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX21_5->GTXE2_CHANNEL_TXDATA43": { + "src_wire": "GTXE2_IMUX21_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA43", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX23_10->GTXE2_CHANNEL_RXCHBONDI4": { + "src_wire": "GTXE2_IMUX23_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX36_5->GTXE2_CHANNEL_TXPHDLYRESET": { + "src_wire": "GTXE2_IMUX36_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHDLYRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK0->GTXE2_LOGIC_OUTS_B12_10": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX47_9->GTXE2_CHANNEL_LOOPBACK2": { + "src_wire": "GTXE2_IMUX47_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_LOOPBACK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX40_8->GTXE2_CHANNEL_TSTIN7": { + "src_wire": "GTXE2_IMUX40_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX35_3->GTXE2_CHANNEL_DRPADDR6": { + "src_wire": "GTXE2_IMUX35_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL0_10->GTXE2_CHANNEL_GTRESETSEL": { + "src_wire": "GTXE2_CTRL0_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRESETSEL", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA60->GTXE2_LOGIC_OUTS_B6_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA60", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT2->GTXE2_LOGIC_OUTS_B13_2": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXBUFSTATUS0->GTXE2_LOGIC_OUTS_B17_2": { + "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX21_4->GTXE2_CHANNEL_TXDATA15": { + "src_wire": "GTXE2_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX19_5->GTXE2_CHANNEL_TXDATA9": { + "src_wire": "GTXE2_IMUX19_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX21_1->GTXE2_CHANNEL_TXDATA59": { + "src_wire": "GTXE2_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA59", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX32_0->GTXE2_CHANNEL_DRPDI11": { + "src_wire": "GTXE2_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX37_9->GTXE2_CHANNEL_RXDFETAP4HOLD": { + "src_wire": "GTXE2_IMUX37_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP4HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA55->GTXE2_LOGIC_OUTS_B0_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA55", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX23_9->GTXE2_CHANNEL_RXCHBONDI3": { + "src_wire": "GTXE2_IMUX23_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX6_6->GTXE2_CHANNEL_TXPRECURSOR1": { + "src_wire": "GTXE2_IMUX6_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX24_1->GTXE2_CHANNEL_TSTIN10": { + "src_wire": "GTXE2_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBUFSTATUS0->GTXE2_LOGIC_OUTS_B23_10": { + "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXHEADER2->GTXE2_LOGIC_OUTS_B17_6": { + "src_wire": "GTXE2_CHANNEL_RXHEADER2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CLK1_5->GTXE2_CHANNEL_CLKRSVD1": { + "src_wire": "GTXE2_CLK1_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXQPISENN->GTXE2_LOGIC_OUTS_B17_1": { + "src_wire": "GTXE2_CHANNEL_RXQPISENN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX29_0->GTXE2_CHANNEL_TXCHARDISPMODE3": { + "src_wire": "GTXE2_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX8_5->GTXE2_CHANNEL_TX8B10BBYPASS5": { + "src_wire": "GTXE2_IMUX8_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL1_7->GTXE2_CHANNEL_RXPMARESET": { + "src_wire": "GTXE2_CTRL1_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPMARESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT3->GTXE2_LOGIC_OUTS_B13_3": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX16_10->GTXE2_CHANNEL_RXDFECM1EN": { + "src_wire": "GTXE2_IMUX16_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFECM1EN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX4_6->GTXE2_CHANNEL_TXSEQUENCE5": { + "src_wire": "GTXE2_IMUX4_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX10_7->GTXE2_CHANNEL_TXBUFDIFFCTRL2": { + "src_wire": "GTXE2_IMUX10_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA16->GTXE2_LOGIC_OUTS_B6_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA16", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXHEADER0->GTXE2_LOGIC_OUTS_B19_6": { + "src_wire": "GTXE2_CHANNEL_RXHEADER0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX42_4->GTXE2_CHANNEL_GTRSVD1": { + "src_wire": "GTXE2_IMUX42_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX38_10->GTXE2_CHANNEL_PCSRSVDIN22": { + "src_wire": "GTXE2_IMUX38_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PHYSTATUS->GTXE2_LOGIC_OUTS_B10_9": { + "src_wire": "GTXE2_CHANNEL_PHYSTATUS", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA57->GTXE2_LOGIC_OUTS_B7_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA57", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX34_10->GTXE2_CHANNEL_PCSRSVDIN20": { + "src_wire": "GTXE2_IMUX34_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXP_PAD->GTXE2_CHANNEL_RXP": { + "src_wire": "GTXE2_CHANNEL_RXP_PAD", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXP", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX29_1->GTXE2_CHANNEL_TXCHARISK7": { + "src_wire": "GTXE2_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX8_3->GTXE2_CHANNEL_TX8B10BBYPASS6": { + "src_wire": "GTXE2_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX35_4->GTXE2_CHANNEL_TXMARGIN2": { + "src_wire": "GTXE2_IMUX35_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMARGIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA2->GTXE2_LOGIC_OUTS_B4_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX10_6->GTXE2_CHANNEL_TXCHARDISPVAL4": { + "src_wire": "GTXE2_IMUX10_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX19_7->GTXE2_CHANNEL_TXDATA1": { + "src_wire": "GTXE2_IMUX19_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO15->GTXE2_LOGIC_OUTS_B3_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO15", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT5->GTXE2_LOGIC_OUTS_B13_5": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX9_7->GTXE2_CHANNEL_PCSRSVDIN12": { + "src_wire": "GTXE2_IMUX9_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA35->GTXE2_LOGIC_OUTS_B5_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA35", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX46_6->GTXE2_CHANNEL_TXRATE1": { + "src_wire": "GTXE2_IMUX46_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXRATE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_TXRATEDONE->GTXE2_LOGIC_OUTS_B20_4": { + "src_wire": "GTXE2_CHANNEL_TXRATEDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHANBONDSEQ->GTXE2_LOGIC_OUTS_B10_8": { + "src_wire": "GTXE2_CHANNEL_RXCHANBONDSEQ", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX12_7->GTXE2_CHANNEL_TXBUFDIFFCTRL0": { + "src_wire": "GTXE2_IMUX12_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX27_10->GTXE2_CHANNEL_RXLPMHFOVRDEN": { + "src_wire": "GTXE2_IMUX27_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMHFOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX22_1->GTXE2_CHANNEL_TXDATA26": { + "src_wire": "GTXE2_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA26", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_NORTHREFCLK1->GTXE2_CHANNEL_GTNORTHREFCLK1": { + "src_wire": "GTXE2_CHANNEL_NORTHREFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX1_5->GTXE2_CHANNEL_TXSEQUENCE2": { + "src_wire": "GTXE2_IMUX1_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX31_1->GTXE2_CHANNEL_TXCHARISK3": { + "src_wire": "GTXE2_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX45_1->GTXE2_CHANNEL_TXQPIWEAKPUP": { + "src_wire": "GTXE2_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXQPIWEAKPUP", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX3_9->GTXE2_CHANNEL_RXDFEUTHOLD": { + "src_wire": "GTXE2_IMUX3_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEUTHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT3->GTXE2_LOGIC_OUTS_B8_7": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX38_7->GTXE2_CHANNEL_RXDLYOVRDEN": { + "src_wire": "GTXE2_IMUX38_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA9->GTXE2_LOGIC_OUTS_B2_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX29_10->GTXE2_CHANNEL_RXDFEAGCHOLD": { + "src_wire": "GTXE2_IMUX29_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEAGCHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX20_0->GTXE2_CHANNEL_TXDATA30": { + "src_wire": "GTXE2_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA30", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CLK1_2->GTXE2_CHANNEL_TXPHDLYTSTCLK": { + "src_wire": "GTXE2_CLK1_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHDLYTSTCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL1_3->GTXE2_CHANNEL_TXPMARESET": { + "src_wire": "GTXE2_CTRL1_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPMARESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX34_4->GTXE2_CHANNEL_SETERRSTATUS": { + "src_wire": "GTXE2_IMUX34_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_SETERRSTATUS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX35_10->GTXE2_CHANNEL_PCSRSVDIN21": { + "src_wire": "GTXE2_IMUX35_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK6->GTXE2_LOGIC_OUTS_B12_5": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA7->GTXE2_LOGIC_OUTS_B15_4": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT4->GTXE2_LOGIC_OUTS_B8_6": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO3->GTXE2_LOGIC_OUTS_B16_7": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA27->GTXE2_LOGIC_OUTS_B0_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA27", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX43_9->GTXE2_CHANNEL_LOOPBACK0": { + "src_wire": "GTXE2_IMUX43_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_LOOPBACK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXHEADER1->GTXE2_LOGIC_OUTS_B23_6": { + "src_wire": "GTXE2_CHANNEL_RXHEADER1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO0->GTXE2_LOGIC_OUTS_B16_10": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX7_4->GTXE2_CHANNEL_TXPOSTCURSOR0": { + "src_wire": "GTXE2_IMUX7_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX25_5->GTXE2_CHANNEL_PCSRSVDIN2": { + "src_wire": "GTXE2_IMUX25_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX22_4->GTXE2_CHANNEL_TXDATA46": { + "src_wire": "GTXE2_IMUX22_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA46", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX3_10->GTXE2_CHANNEL_RXLPMLFKLOVRDEN": { + "src_wire": "GTXE2_IMUX3_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX36_0->GTXE2_CHANNEL_DRPDI9": { + "src_wire": "GTXE2_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA28->GTXE2_LOGIC_OUTS_B3_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA28", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO11->GTXE2_LOGIC_OUTS_B6_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO11", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT0->GTXE2_LOGIC_OUTS_B8_10": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX0_7->GTXE2_CHANNEL_PMARSVDIN23": { + "src_wire": "GTXE2_IMUX0_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT2->GTXE2_LOGIC_OUTS_B9_8": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX23_5->GTXE2_CHANNEL_TXDATA11": { + "src_wire": "GTXE2_IMUX23_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLLOCK->GTXE2_LOGIC_OUTS_B14_1": { + "src_wire": "GTXE2_CHANNEL_CPLLLOCK", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT4->GTXE2_LOGIC_OUTS_B9_6": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX44_10->GTXE2_CHANNEL_RXDFETAP2HOLD": { + "src_wire": "GTXE2_IMUX44_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP2HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA59->GTXE2_LOGIC_OUTS_B5_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA59", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLREFCLKLOST->GTXE2_LOGIC_OUTS_B18_1": { + "src_wire": "GTXE2_CHANNEL_CPLLREFCLKLOST", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX3_3->GTXE2_CHANNEL_TXSTARTSEQ": { + "src_wire": "GTXE2_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSTARTSEQ", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA34->GTXE2_LOGIC_OUTS_B1_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA34", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO6->GTXE2_LOGIC_OUTS_B7_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX27_7->GTXE2_CHANNEL_RXPOLARITY": { + "src_wire": "GTXE2_IMUX27_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPOLARITY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX13_2->GTXE2_CHANNEL_TXHEADER0": { + "src_wire": "GTXE2_IMUX13_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXHEADER0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA43->GTXE2_LOGIC_OUTS_B5_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA43", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX26_4->GTXE2_CHANNEL_GTRSVD9": { + "src_wire": "GTXE2_IMUX26_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX41_0->GTXE2_CHANNEL_EYESCANMODE": { + "src_wire": "GTXE2_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_EYESCANMODE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA0->GTXE2_LOGIC_OUTS_B15_9": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX14_2->GTXE2_CHANNEL_CPLLREFCLKSEL1": { + "src_wire": "GTXE2_IMUX14_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA29->GTXE2_LOGIC_OUTS_B7_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA29", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA0->GTXE2_LOGIC_OUTS_B6_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT5->GTXE2_LOGIC_OUTS_B9_5": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CTRL0_3->GTXE2_CHANNEL_CPLLRESET": { + "src_wire": "GTXE2_CTRL0_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX34_0->GTXE2_CHANNEL_DRPDI3": { + "src_wire": "GTXE2_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX4_3->GTXE2_CHANNEL_TXMAINCURSOR1": { + "src_wire": "GTXE2_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX11_2->GTXE2_CHANNEL_CPLLREFCLKSEL2": { + "src_wire": "GTXE2_IMUX11_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO4->GTXE2_LOGIC_OUTS_B16_6": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA45->GTXE2_LOGIC_OUTS_B2_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA45", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX28_5->GTXE2_CHANNEL_TXSYSCLKSEL0": { + "src_wire": "GTXE2_IMUX28_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT7->GTXE2_LOGIC_OUTS_B9_3": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA41->GTXE2_LOGIC_OUTS_B7_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA41", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX37_3->GTXE2_CHANNEL_TXPHDLYPD": { + "src_wire": "GTXE2_IMUX37_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHDLYPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX8_1->GTXE2_CHANNEL_TX8B10BBYPASS7": { + "src_wire": "GTXE2_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX40_10->GTXE2_CHANNEL_TSTIN9": { + "src_wire": "GTXE2_IMUX40_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA4->GTXE2_LOGIC_OUTS_B15_10": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO9->GTXE2_LOGIC_OUTS_B4_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX15_1->GTXE2_CHANNEL_TX8B10BBYPASS3": { + "src_wire": "GTXE2_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR0->GTXE2_LOGIC_OUTS_B22_10": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX40_2->GTXE2_CHANNEL_TSTIN1": { + "src_wire": "GTXE2_IMUX40_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX15_5->GTXE2_CHANNEL_TX8B10BBYPASS1": { + "src_wire": "GTXE2_IMUX15_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT4->GTXE2_LOGIC_OUTS_B13_4": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX25_9->GTXE2_CHANNEL_PCSRSVDIN6": { + "src_wire": "GTXE2_IMUX25_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX23_3->GTXE2_CHANNEL_TXDATA19": { + "src_wire": "GTXE2_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA19", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX32_1->GTXE2_CHANNEL_DRPDI15": { + "src_wire": "GTXE2_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX39_9->GTXE2_CHANNEL_PCSRSVDIN24": { + "src_wire": "GTXE2_IMUX39_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_0.GTXE2_IMUX31_3->GTXE2_CHANNEL_TXCHARISK2": { + "src_wire": "GTXE2_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK2", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_GTX_CHANNEL_1.json b/kintex7/tile_type_GTX_CHANNEL_1.json new file mode 100644 index 0000000..6cd2aca --- /dev/null +++ b/kintex7/tile_type_GTX_CHANNEL_1.json @@ -0,0 +1,6854 @@ +{ + "tile_type": "GTX_CHANNEL_1", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "GTXE2_CHANNEL", + "type": "GTXE2_CHANNEL", + "site_pins": { + "RXQPIEN": "GTXE2_CHANNEL_RXQPIEN", + "TXDATA47": "GTXE2_CHANNEL_TXDATA47", + "RXDATA59": "GTXE2_CHANNEL_RXDATA59", + "TXDATA19": "GTXE2_CHANNEL_TXDATA19", + "RXDISPERR3": "GTXE2_CHANNEL_RXDISPERR3", + "RXBUFSTATUS1": "GTXE2_CHANNEL_RXBUFSTATUS1", + "TXCHARDISPMODE5": "GTXE2_CHANNEL_TXCHARDISPMODE5", + "TXCHARDISPMODE3": "GTXE2_CHANNEL_TXCHARDISPMODE3", + "RXDATA47": "GTXE2_CHANNEL_RXDATA47", + "TXDATA24": "GTXE2_CHANNEL_TXDATA24", + "TXHEADER1": "GTXE2_CHANNEL_TXHEADER1", + "TSTIN17": "GTXE2_CHANNEL_TSTIN17", + "TXPHALIGN": "GTXE2_CHANNEL_TXPHALIGN", + "CLKRSVD3": "GTXE2_CHANNEL_CLKRSVD3", + "PCSRSVDIN20": "GTXE2_CHANNEL_PCSRSVDIN20", + "RXDATA25": "GTXE2_CHANNEL_RXDATA25", + "DRPDO9": "GTXE2_CHANNEL_DRPDO9", + "RXDATA20": "GTXE2_CHANNEL_RXDATA20", + "GTRSVD4": "GTXE2_CHANNEL_GTRSVD4", + "TXCOMSAS": "GTXE2_CHANNEL_TXCOMSAS", + "PMASCANCLK2": "GTXE2_CHANNEL_PMASCANCLK2", + "RXBYTEISALIGNED": "GTXE2_CHANNEL_RXBYTEISALIGNED", + "RXPRBSSEL2": "GTXE2_CHANNEL_RXPRBSSEL2", + "TXDATA43": "GTXE2_CHANNEL_TXDATA43", + "RXDATA38": "GTXE2_CHANNEL_RXDATA38", + "RXOUTCLKFABRIC": "GTXE2_CHANNEL_RXOUTCLKFABRIC", + "TSTOUT8": "GTXE2_CHANNEL_TSTOUT8", + "RESETOVRD": "GTXE2_CHANNEL_RESETOVRD", + "GTREFCLK1": "GTXE2_CHANNEL_GTREFCLK1", + "TXSTARTSEQ": "GTXE2_CHANNEL_TXSTARTSEQ", + "RXDATA7": "GTXE2_CHANNEL_RXDATA7", + "RX8B10BEN": "GTXE2_CHANNEL_RX8B10BEN", + "PCSRSVDOUT8": "GTXE2_CHANNEL_PCSRSVDOUT8", + "TXDLYSRESETDONE": "GTXE2_CHANNEL_TXDLYSRESETDONE", + "RXMONITOROUT4": "GTXE2_CHANNEL_RXMONITOROUT4", + "RXOUTCLKSEL1": "GTXE2_CHANNEL_RXOUTCLKSEL1", + "TXPOSTCURSOR0": "GTXE2_CHANNEL_TXPOSTCURSOR0", + "RXCHARISK4": "GTXE2_CHANNEL_RXCHARISK4", + "PCSRSVDOUT11": "GTXE2_CHANNEL_PCSRSVDOUT11", + "SCANENB": "GTXE2_CHANNEL_SCANENB", + "TXCHARDISPMODE1": "GTXE2_CHANNEL_TXCHARDISPMODE1", + "RXDLYTESTENB": "GTXE2_CHANNEL_RXDLYTESTENB", + "RXPCOMMAALIGNEN": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", + "TXPRECURSOR1": "GTXE2_CHANNEL_TXPRECURSOR1", + "RXCHBONDLEVEL1": "GTXE2_CHANNEL_RXCHBONDLEVEL1", + "RXPD0": "GTXE2_CHANNEL_RXPD0", + "DRPDI15": "GTXE2_CHANNEL_DRPDI15", + "TXPOSTCURSORINV": "GTXE2_CHANNEL_TXPOSTCURSORINV", + "GTRSVD7": "GTXE2_CHANNEL_GTRSVD7", + "PMASCANMODEB": "GTXE2_CHANNEL_PMASCANMODEB", + "RXMONITOROUT0": "GTXE2_CHANNEL_RXMONITOROUT0", + "RXRATEDONE": "GTXE2_CHANNEL_RXRATEDONE", + "PMASCANOUT2": "GTXE2_CHANNEL_PMASCANOUT2", + "RXDFETAP4OVRDEN": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", + "RXDATA16": "GTXE2_CHANNEL_RXDATA16", + "TXCHARDISPMODE7": "GTXE2_CHANNEL_TXCHARDISPMODE7", + "RXDATA49": "GTXE2_CHANNEL_RXDATA49", + "SETERRSTATUS": "GTXE2_CHANNEL_SETERRSTATUS", + "TXDLYSRESET": "GTXE2_CHANNEL_TXDLYSRESET", + "TXDATA1": "GTXE2_CHANNEL_TXDATA1", + "TX8B10BBYPASS4": "GTXE2_CHANNEL_TX8B10BBYPASS4", + "PMARSVDIN20": "GTXE2_CHANNEL_PMARSVDIN20", + "TSTOUT0": "GTXE2_CHANNEL_TSTOUT0", + "RXPHDLYRESET": "GTXE2_CHANNEL_RXPHDLYRESET", + "TXDATA30": "GTXE2_CHANNEL_TXDATA30", + "DRPDI12": "GTXE2_CHANNEL_DRPDI12", + "TXRUNDISP4": "GTXE2_CHANNEL_TXRUNDISP4", + "CLKRSVD2": "GTXE2_CHANNEL_CLKRSVD2", + "PCSRSVDIN12": "GTXE2_CHANNEL_PCSRSVDIN12", + "TXCHARDISPMODE0": "GTXE2_CHANNEL_TXCHARDISPMODE0", + "TXDATA51": "GTXE2_CHANNEL_TXDATA51", + "RXMONITOROUT6": "GTXE2_CHANNEL_RXMONITOROUT6", + "CPLLREFCLKLOST": "GTXE2_CHANNEL_CPLLREFCLKLOST", + "SCANOUT2": "GTXE2_CHANNEL_SCANOUT2", + "RXDATA62": "GTXE2_CHANNEL_RXDATA62", + "DRPDI5": "GTXE2_CHANNEL_DRPDI5", + "RXRESETDONE": "GTXE2_CHANNEL_RXRESETDONE", + "TSTCLK0": "GTXE2_CHANNEL_TSTCLK0", + "DRPDO5": "GTXE2_CHANNEL_DRPDO5", + "PCSRSVDIN10": "GTXE2_CHANNEL_PCSRSVDIN10", + "RXCDRHOLD": "GTXE2_CHANNEL_RXCDRHOLD", + "PCSRSVDIN24": "GTXE2_CHANNEL_PCSRSVDIN24", + "TXDIFFCTRL0": "GTXE2_CHANNEL_TXDIFFCTRL0", + "RXMONITOROUT3": "GTXE2_CHANNEL_RXMONITOROUT3", + "TSTIN2": "GTXE2_CHANNEL_TSTIN2", + "RXRATE1": "GTXE2_CHANNEL_RXRATE1", + "PMARSVDIN0": "GTXE2_CHANNEL_PMARSVDIN0", + "RXDFELFHOLD": "GTXE2_CHANNEL_RXDFELFHOLD", + "RXDFEVPHOLD": "GTXE2_CHANNEL_RXDFEVPHOLD", + "RXDATA26": "GTXE2_CHANNEL_RXDATA26", + "TXPRBSSEL2": "GTXE2_CHANNEL_TXPRBSSEL2", + "TXDATA20": "GTXE2_CHANNEL_TXDATA20", + "TXDATA18": "GTXE2_CHANNEL_TXDATA18", + "TXCHARISK7": "GTXE2_CHANNEL_TXCHARISK7", + "LOOPBACK0": "GTXE2_CHANNEL_LOOPBACK0", + "TXPHDLYPD": "GTXE2_CHANNEL_TXPHDLYPD", + "TXPRECURSOR3": "GTXE2_CHANNEL_TXPRECURSOR3", + "DRPDO11": "GTXE2_CHANNEL_DRPDO11", + "GTXRXP": "GTXE2_CHANNEL_RXP", + "TXCHARDISPVAL7": "GTXE2_CHANNEL_TXCHARDISPVAL7", + "RXCHANBONDSEQ": "GTXE2_CHANNEL_RXCHANBONDSEQ", + "DRPDI6": "GTXE2_CHANNEL_DRPDI6", + "TXDATA48": "GTXE2_CHANNEL_TXDATA48", + "CPLLFBCLKLOST": "GTXE2_CHANNEL_CPLLFBCLKLOST", + "RXDATA55": "GTXE2_CHANNEL_RXDATA55", + "TSTIN10": "GTXE2_CHANNEL_TSTIN10", + "RXDATA60": "GTXE2_CHANNEL_RXDATA60", + "RXDATA11": "GTXE2_CHANNEL_RXDATA11", + "SCANIN1": "GTXE2_CHANNEL_SCANIN1", + "DRPDO3": "GTXE2_CHANNEL_DRPDO3", + "TXDATA8": "GTXE2_CHANNEL_TXDATA8", + "RXCHBONDEN": "GTXE2_CHANNEL_RXCHBONDEN", + "PMASCANOUT1": "GTXE2_CHANNEL_PMASCANOUT1", + "DMONITOROUT4": "GTXE2_CHANNEL_DMONITOROUT4", + "SCANOUT3": "GTXE2_CHANNEL_SCANOUT3", + "RXDATA57": "GTXE2_CHANNEL_RXDATA57", + "TXDATA25": "GTXE2_CHANNEL_TXDATA25", + "RXDFEUTOVRDEN": "GTXE2_CHANNEL_RXDFEUTOVRDEN", + "PMASCANIN3": "GTXE2_CHANNEL_PMASCANIN3", + "TXPISOPD": "GTXE2_CHANNEL_TXPISOPD", + "TXCHARDISPMODE6": "GTXE2_CHANNEL_TXCHARDISPMODE6", + "RXCDRFREQRESET": "GTXE2_CHANNEL_RXCDRFREQRESET", + "TXCHARDISPVAL4": "GTXE2_CHANNEL_TXCHARDISPVAL4", + "GTSOUTHREFCLK0": "GTXE2_CHANNEL_GTSOUTHREFCLK0", + "TXCHARDISPVAL5": "GTXE2_CHANNEL_TXCHARDISPVAL5", + "GTXRXN": "GTXE2_CHANNEL_RXN", + "TXDATA53": "GTXE2_CHANNEL_TXDATA53", + "RXPHDLYPD": "GTXE2_CHANNEL_RXPHDLYPD", + "TSTPD2": "GTXE2_CHANNEL_TSTPD2", + "RXCHBONDO1": "GTXE2_CHANNEL_RXCHBONDO1", + "RXBUFSTATUS0": "GTXE2_CHANNEL_RXBUFSTATUS0", + "TXDATA13": "GTXE2_CHANNEL_TXDATA13", + "PMASCANOUT0": "GTXE2_CHANNEL_PMASCANOUT0", + "RXCHARISCOMMA2": "GTXE2_CHANNEL_RXCHARISCOMMA2", + "TXOUTCLKPCS": "GTXE2_CHANNEL_TXOUTCLKPCS", + "PCSRSVDOUT14": "GTXE2_CHANNEL_PCSRSVDOUT14", + "RXDATA24": "GTXE2_CHANNEL_RXDATA24", + "RXDATA37": "GTXE2_CHANNEL_RXDATA37", + "TX8B10BBYPASS1": "GTXE2_CHANNEL_TX8B10BBYPASS1", + "DRPDI9": "GTXE2_CHANNEL_DRPDI9", + "TXCHARDISPMODE2": "GTXE2_CHANNEL_TXCHARDISPMODE2", + "TXOUTCLKSEL1": "GTXE2_CHANNEL_TXOUTCLKSEL1", + "RXCHBONDMASTER": "GTXE2_CHANNEL_RXCHBONDMASTER", + "TXDATA28": "GTXE2_CHANNEL_TXDATA28", + "RXDATA34": "GTXE2_CHANNEL_RXDATA34", + "CFGRESET": "GTXE2_CHANNEL_CFGRESET", + "RXDFEVPOVRDEN": "GTXE2_CHANNEL_RXDFEVPOVRDEN", + "TXDATA29": "GTXE2_CHANNEL_TXDATA29", + "GTRESETSEL": "GTXE2_CHANNEL_GTRESETSEL", + "EDTCONFIGURATION": "GTXE2_CHANNEL_EDTCONFIGURATION", + "TXCHARISK4": "GTXE2_CHANNEL_TXCHARISK4", + "TXQPISENP": "GTXE2_CHANNEL_TXQPISENP", + "RXCHBONDLEVEL0": "GTXE2_CHANNEL_RXCHBONDLEVEL0", + "PCSRSVDIN8": "GTXE2_CHANNEL_PCSRSVDIN8", + "PMASCANIN0": "GTXE2_CHANNEL_PMASCANIN0", + "DRPDO4": "GTXE2_CHANNEL_DRPDO4", + "RXDATA14": "GTXE2_CHANNEL_RXDATA14", + "TSTOUT5": "GTXE2_CHANNEL_TSTOUT5", + "EDTCLOCK": "GTXE2_CHANNEL_EDTCLOCK", + "QPLLREFCLK": "GTXE2_CHANNEL_GTQPLLREFCLK", + "RXDATA39": "GTXE2_CHANNEL_RXDATA39", + "RXLPMEN": "GTXE2_CHANNEL_RXLPMEN", + "EDTUPDATE": "GTXE2_CHANNEL_EDTUPDATE", + "TXSWING": "GTXE2_CHANNEL_TXSWING", + "TXRATE0": "GTXE2_CHANNEL_TXRATE0", + "RXDATA9": "GTXE2_CHANNEL_RXDATA9", + "TXRUNDISP5": "GTXE2_CHANNEL_TXRUNDISP5", + "RXMCOMMAALIGNEN": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", + "SCANIN2": "GTXE2_CHANNEL_SCANIN2", + "TXPOLARITY": "GTXE2_CHANNEL_TXPOLARITY", + "RXDATA32": "GTXE2_CHANNEL_RXDATA32", + "DRPDO2": "GTXE2_CHANNEL_DRPDO2", + "TXPOSTCURSOR3": "GTXE2_CHANNEL_TXPOSTCURSOR3", + "TXDLYTESTENB": "GTXE2_CHANNEL_TXDLYTESTENB", + "RXLPMLFKLOVRDEN": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", + "RXRATE2": "GTXE2_CHANNEL_RXRATE2", + "RXDFECM1EN": "GTXE2_CHANNEL_RXDFECM1EN", + "RXCDRRESETRSV": "GTXE2_CHANNEL_RXCDRRESETRSV", + "SCANCLK": "GTXE2_CHANNEL_SCANCLK", + "TSTIN6": "GTXE2_CHANNEL_TSTIN6", + "TXDLYHOLD": "GTXE2_CHANNEL_TXDLYHOLD", + "RXCHANREALIGN": "GTXE2_CHANNEL_RXCHANREALIGN", + "RXCHBONDO4": "GTXE2_CHANNEL_RXCHBONDO4", + "TXRUNDISP1": "GTXE2_CHANNEL_TXRUNDISP1", + "TXDATA23": "GTXE2_CHANNEL_TXDATA23", + "TXDATA21": "GTXE2_CHANNEL_TXDATA21", + "RXNOTINTABLE7": "GTXE2_CHANNEL_RXNOTINTABLE7", + "RXDATA29": "GTXE2_CHANNEL_RXDATA29", + "TXDATA37": "GTXE2_CHANNEL_TXDATA37", + "DMONITOROUT1": "GTXE2_CHANNEL_DMONITOROUT1", + "PMASCANCLK4": "GTXE2_CHANNEL_PMASCANCLK4", + "PCSRSVDOUT9": "GTXE2_CHANNEL_PCSRSVDOUT9", + "TXPHDLYTSTCLK": "GTXE2_CHANNEL_TXPHDLYTSTCLK", + "TXUSRCLK2": "GTXE2_CHANNEL_TXUSRCLK2", + "DRPDO15": "GTXE2_CHANNEL_DRPDO15", + "TXOUTCLKSEL2": "GTXE2_CHANNEL_TXOUTCLKSEL2", + "TX8B10BBYPASS2": "GTXE2_CHANNEL_TX8B10BBYPASS2", + "CPLLLOCKEN": "GTXE2_CHANNEL_CPLLLOCKEN", + "DRPDI4": "GTXE2_CHANNEL_DRPDI4", + "TXDATA42": "GTXE2_CHANNEL_TXDATA42", + "RXHEADERVALID": "GTXE2_CHANNEL_RXHEADERVALID", + "RXDISPERR2": "GTXE2_CHANNEL_RXDISPERR2", + "RXCHBONDI0": "GTXE2_CHANNEL_RXCHBONDI0", + "TXBUFSTATUS1": "GTXE2_CHANNEL_TXBUFSTATUS1", + "PCSRSVDOUT5": "GTXE2_CHANNEL_PCSRSVDOUT5", + "RXPRBSSEL1": "GTXE2_CHANNEL_RXPRBSSEL1", + "RXDATA2": "GTXE2_CHANNEL_RXDATA2", + "RXDATA18": "GTXE2_CHANNEL_RXDATA18", + "TXOUTCLKFABRIC": "GTXE2_CHANNEL_TXOUTCLKFABRIC", + "PMARSVDIN24": "GTXE2_CHANNEL_PMARSVDIN24", + "TXQPISENN": "GTXE2_CHANNEL_TXQPISENN", + "RXQPISENN": "GTXE2_CHANNEL_RXQPISENN", + "TSTOUT4": "GTXE2_CHANNEL_TSTOUT4", + "TXDATA22": "GTXE2_CHANNEL_TXDATA22", + "DRPWE": "GTXE2_CHANNEL_DRPWE", + "RXCHANISALIGNED": "GTXE2_CHANNEL_RXCHANISALIGNED", + "TXPHOVRDEN": "GTXE2_CHANNEL_TXPHOVRDEN", + "RXDATA54": "GTXE2_CHANNEL_RXDATA54", + "TX8B10BBYPASS6": "GTXE2_CHANNEL_TX8B10BBYPASS6", + "TXDIFFCTRL2": "GTXE2_CHANNEL_TXDIFFCTRL2", + "TXINHIBIT": "GTXE2_CHANNEL_TXINHIBIT", + "TSTIN8": "GTXE2_CHANNEL_TSTIN8", + "TSTIN3": "GTXE2_CHANNEL_TSTIN3", + "TXDATA35": "GTXE2_CHANNEL_TXDATA35", + "TXHEADER0": "GTXE2_CHANNEL_TXHEADER0", + "RXDATA8": "GTXE2_CHANNEL_RXDATA8", + "SCANIN0": "GTXE2_CHANNEL_SCANIN0", + "TXPCSRESET": "GTXE2_CHANNEL_TXPCSRESET", + "TXPOSTCURSOR4": "GTXE2_CHANNEL_TXPOSTCURSOR4", + "RXCHARISK2": "GTXE2_CHANNEL_RXCHARISK2", + "RXDLYBYPASS": "GTXE2_CHANNEL_RXDLYBYPASS", + "PCSRSVDIN14": "GTXE2_CHANNEL_PCSRSVDIN14", + "TXPRECURSORINV": "GTXE2_CHANNEL_TXPRECURSORINV", + "RXDATA40": "GTXE2_CHANNEL_RXDATA40", + "TXCHARDISPVAL2": "GTXE2_CHANNEL_TXCHARDISPVAL2", + "TX8B10BBYPASS3": "GTXE2_CHANNEL_TX8B10BBYPASS3", + "PCSRSVDOUT2": "GTXE2_CHANNEL_PCSRSVDOUT2", + "TXDATA45": "GTXE2_CHANNEL_TXDATA45", + "RXHEADER2": "GTXE2_CHANNEL_RXHEADER2", + "EYESCANTRIGGER": "GTXE2_CHANNEL_EYESCANTRIGGER", + "RXDATA53": "GTXE2_CHANNEL_RXDATA53", + "TXMAINCURSOR0": "GTXE2_CHANNEL_TXMAINCURSOR0", + "PMARSVDIN23": "GTXE2_CHANNEL_PMARSVDIN23", + "RXDATA10": "GTXE2_CHANNEL_RXDATA10", + "DRPDI10": "GTXE2_CHANNEL_DRPDI10", + "RXDATA58": "GTXE2_CHANNEL_RXDATA58", + "CPLLREFCLKSEL0": "GTXE2_CHANNEL_CPLLREFCLKSEL0", + "DMONITOROUT0": "GTXE2_CHANNEL_DMONITOROUT0", + "PCSRSVDIN2": "GTXE2_CHANNEL_PCSRSVDIN2", + "RXDLYEN": "GTXE2_CHANNEL_RXDLYEN", + "EYESCANMODE": "GTXE2_CHANNEL_EYESCANMODE", + "PMASCANOUT4": "GTXE2_CHANNEL_PMASCANOUT4", + "RXBYTEREALIGN": "GTXE2_CHANNEL_RXBYTEREALIGN", + "RXCOMWAKEDET": "GTXE2_CHANNEL_RXCOMWAKEDET", + "TSTOUT2": "GTXE2_CHANNEL_TSTOUT2", + "RXPRBSSEL0": "GTXE2_CHANNEL_RXPRBSSEL0", + "TXSEQUENCE6": "GTXE2_CHANNEL_TXSEQUENCE6", + "TSTIN14": "GTXE2_CHANNEL_TSTIN14", + "CPLLRESET": "GTXE2_CHANNEL_CPLLRESET", + "RXCHARISK1": "GTXE2_CHANNEL_RXCHARISK1", + "GTSOUTHREFCLK1": "GTXE2_CHANNEL_GTSOUTHREFCLK1", + "RXDATA3": "GTXE2_CHANNEL_RXDATA3", + "TXPRBSSEL0": "GTXE2_CHANNEL_TXPRBSSEL0", + "SCANIN4": "GTXE2_CHANNEL_SCANIN4", + "RXDATA36": "GTXE2_CHANNEL_RXDATA36", + "TXGEARBOXREADY": "GTXE2_CHANNEL_TXGEARBOXREADY", + "TXRESETDONE": "GTXE2_CHANNEL_TXRESETDONE", + "DRPDO12": "GTXE2_CHANNEL_DRPDO12", + "PCSRSVDOUT12": "GTXE2_CHANNEL_PCSRSVDOUT12", + "GTNORTHREFCLK0": "GTXE2_CHANNEL_GTNORTHREFCLK0", + "RXPMARESET": "GTXE2_CHANNEL_RXPMARESET", + "TXSYSCLKSEL0": "GTXE2_CHANNEL_TXSYSCLKSEL0", + "TSTIN7": "GTXE2_CHANNEL_TSTIN7", + "DMONITOROUT3": "GTXE2_CHANNEL_DMONITOROUT3", + "PCSRSVDIN9": "GTXE2_CHANNEL_PCSRSVDIN9", + "TXCOMINIT": "GTXE2_CHANNEL_TXCOMINIT", + "TXPD1": "GTXE2_CHANNEL_TXPD1", + "RXCHARISCOMMA7": "GTXE2_CHANNEL_RXCHARISCOMMA7", + "RXMONITORSEL0": "GTXE2_CHANNEL_RXMONITORSEL0", + "RXOUTCLKPCS": "GTXE2_CHANNEL_RXOUTCLKPCS", + "RXMONITOROUT2": "GTXE2_CHANNEL_RXMONITOROUT2", + "RXPHSLIPMONITOR1": "GTXE2_CHANNEL_RXPHSLIPMONITOR1", + "SCANIN3": "GTXE2_CHANNEL_SCANIN3", + "DRPADDR6": "GTXE2_CHANNEL_DRPADDR6", + "RXCHARISK6": "GTXE2_CHANNEL_RXCHARISK6", + "RXLPMHFOVRDEN": "GTXE2_CHANNEL_RXLPMHFOVRDEN", + "RXDLYOVRDEN": "GTXE2_CHANNEL_RXDLYOVRDEN", + "LOOPBACK2": "GTXE2_CHANNEL_LOOPBACK2", + "PCSRSVDIN11": "GTXE2_CHANNEL_PCSRSVDIN11", + "DRPCLK": "GTXE2_CHANNEL_DRPCLK", + "TXMAINCURSOR1": "GTXE2_CHANNEL_TXMAINCURSOR1", + "RXSLIDE": "GTXE2_CHANNEL_RXSLIDE", + "TXUSERRDY": "GTXE2_CHANNEL_TXUSERRDY", + "RXMONITOROUT5": "GTXE2_CHANNEL_RXMONITOROUT5", + "TX8B10BBYPASS5": "GTXE2_CHANNEL_TX8B10BBYPASS5", + "RXPCSRESET": "GTXE2_CHANNEL_RXPCSRESET", + "TXDATA26": "GTXE2_CHANNEL_TXDATA26", + "TXELECIDLE": "GTXE2_CHANNEL_TXELECIDLE", + "DRPADDR8": "GTXE2_CHANNEL_DRPADDR8", + "RXPOLARITY": "GTXE2_CHANNEL_RXPOLARITY", + "TXCHARDISPVAL6": "GTXE2_CHANNEL_TXCHARDISPVAL6", + "RXDATA35": "GTXE2_CHANNEL_RXDATA35", + "TSTPDOVRDB": "GTXE2_CHANNEL_TSTPDOVRDB", + "RXCHARISCOMMA4": "GTXE2_CHANNEL_RXCHARISCOMMA4", + "RXLPMLFHOLD": "GTXE2_CHANNEL_RXLPMLFHOLD", + "DRPDI3": "GTXE2_CHANNEL_DRPDI3", + "TXPOSTCURSOR1": "GTXE2_CHANNEL_TXPOSTCURSOR1", + "RXDATA50": "GTXE2_CHANNEL_RXDATA50", + "TXSEQUENCE5": "GTXE2_CHANNEL_TXSEQUENCE5", + "RXOUTCLK": "GTXE2_CHANNEL_GTRXOUTCLK_1", + "GTRSVD3": "GTXE2_CHANNEL_GTRSVD3", + "RXPHMONITOR3": "GTXE2_CHANNEL_RXPHMONITOR3", + "RXNOTINTABLE2": "GTXE2_CHANNEL_RXNOTINTABLE2", + "RXPHOVRDEN": "GTXE2_CHANNEL_RXPHOVRDEN", + "EYESCANRESET": "GTXE2_CHANNEL_EYESCANRESET", + "RXNOTINTABLE0": "GTXE2_CHANNEL_RXNOTINTABLE0", + "TXMARGIN2": "GTXE2_CHANNEL_TXMARGIN2", + "RXDFETAP3HOLD": "GTXE2_CHANNEL_RXDFETAP3HOLD", + "PCSRSVDIN15": "GTXE2_CHANNEL_PCSRSVDIN15", + "TXDATA38": "GTXE2_CHANNEL_TXDATA38", + "TXSEQUENCE2": "GTXE2_CHANNEL_TXSEQUENCE2", + "DRPADDR0": "GTXE2_CHANNEL_DRPADDR0", + "RXOSOVRDEN": "GTXE2_CHANNEL_RXOSOVRDEN", + "TXPHALIGNDONE": "GTXE2_CHANNEL_TXPHALIGNDONE", + "TXCHARISK3": "GTXE2_CHANNEL_TXCHARISK3", + "TSTPD0": "GTXE2_CHANNEL_TSTPD0", + "PCSRSVDOUT6": "GTXE2_CHANNEL_PCSRSVDOUT6", + "TXBUFDIFFCTRL2": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", + "TXMAINCURSOR4": "GTXE2_CHANNEL_TXMAINCURSOR4", + "RXCHARISCOMMA6": "GTXE2_CHANNEL_RXCHARISCOMMA6", + "RXDFETAP2HOLD": "GTXE2_CHANNEL_RXDFETAP2HOLD", + "RXSTATUS2": "GTXE2_CHANNEL_RXSTATUS2", + "TXRUNDISP3": "GTXE2_CHANNEL_TXRUNDISP3", + "RXDATA48": "GTXE2_CHANNEL_RXDATA48", + "TXDATA5": "GTXE2_CHANNEL_TXDATA5", + "DMONITOROUT5": "GTXE2_CHANNEL_DMONITOROUT5", + "RXCHARISCOMMA0": "GTXE2_CHANNEL_RXCHARISCOMMA0", + "TXDATA63": "GTXE2_CHANNEL_TXDATA63", + "DMONITOROUT6": "GTXE2_CHANNEL_DMONITOROUT6", + "RXELECIDLE": "GTXE2_CHANNEL_RXELECIDLE", + "RXGEARBOXSLIP": "GTXE2_CHANNEL_RXGEARBOXSLIP", + "GTRSVD13": "GTXE2_CHANNEL_GTRSVD13", + "RXMONITORSEL1": "GTXE2_CHANNEL_RXMONITORSEL1", + "RXPHMONITOR4": "GTXE2_CHANNEL_RXPHMONITOR4", + "RXDATA44": "GTXE2_CHANNEL_RXDATA44", + "SCANOUT0": "GTXE2_CHANNEL_SCANOUT0", + "PHYSTATUS": "GTXE2_CHANNEL_PHYSTATUS", + "TXRUNDISP6": "GTXE2_CHANNEL_TXRUNDISP6", + "GTRSVD14": "GTXE2_CHANNEL_GTRSVD14", + "RXDFETAP5OVRDEN": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", + "RXDATA56": "GTXE2_CHANNEL_RXDATA56", + "RXCOMSASDET": "GTXE2_CHANNEL_RXCOMSASDET", + "TXQPIBIASEN": "GTXE2_CHANNEL_TXQPIBIASEN", + "RXCHBONDLEVEL2": "GTXE2_CHANNEL_RXCHBONDLEVEL2", + "RXDATA41": "GTXE2_CHANNEL_RXDATA41", + "RXDATA33": "GTXE2_CHANNEL_RXDATA33", + "RXDATA61": "GTXE2_CHANNEL_RXDATA61", + "RXDATA1": "GTXE2_CHANNEL_RXDATA1", + "RXMONITOROUT1": "GTXE2_CHANNEL_RXMONITOROUT1", + "TXPHALIGNEN": "GTXE2_CHANNEL_TXPHALIGNEN", + "GTRSVD0": "GTXE2_CHANNEL_GTRSVD0", + "RXDISPERR1": "GTXE2_CHANNEL_RXDISPERR1", + "TXDATA56": "GTXE2_CHANNEL_TXDATA56", + "TXDIFFCTRL3": "GTXE2_CHANNEL_TXDIFFCTRL3", + "DRPADDR1": "GTXE2_CHANNEL_DRPADDR1", + "TXCHARISK0": "GTXE2_CHANNEL_TXCHARISK0", + "PCSRSVDOUT10": "GTXE2_CHANNEL_PCSRSVDOUT10", + "CPLLLOCK": "GTXE2_CHANNEL_CPLLLOCK", + "TXBUFSTATUS0": "GTXE2_CHANNEL_TXBUFSTATUS0", + "RXCHARISK7": "GTXE2_CHANNEL_RXCHARISK7", + "RXNOTINTABLE6": "GTXE2_CHANNEL_RXNOTINTABLE6", + "DRPEN": "GTXE2_CHANNEL_DRPEN", + "TXBUFDIFFCTRL0": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", + "TXDATA62": "GTXE2_CHANNEL_TXDATA62", + "TXBUFDIFFCTRL1": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", + "SCANOUT4": "GTXE2_CHANNEL_SCANOUT4", + "DRPDO6": "GTXE2_CHANNEL_DRPDO6", + "DRPADDR7": "GTXE2_CHANNEL_DRPADDR7", + "RXSTATUS1": "GTXE2_CHANNEL_RXSTATUS1", + "RXDISPERR5": "GTXE2_CHANNEL_RXDISPERR5", + "RXVALID": "GTXE2_CHANNEL_RXVALID", + "DRPDI2": "GTXE2_CHANNEL_DRPDI2", + "GTRSVD9": "GTXE2_CHANNEL_GTRSVD9", + "TXDATA60": "GTXE2_CHANNEL_TXDATA60", + "TXDLYUPDOWN": "GTXE2_CHANNEL_TXDLYUPDOWN", + "RXDFETAP3OVRDEN": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", + "RXCOMINITDET": "GTXE2_CHANNEL_RXCOMINITDET", + "RXOUTCLKSEL0": "GTXE2_CHANNEL_RXOUTCLKSEL0", + "TXDATA11": "GTXE2_CHANNEL_TXDATA11", + "RXSYSCLKSEL1": "GTXE2_CHANNEL_RXSYSCLKSEL1", + "RXSTATUS0": "GTXE2_CHANNEL_RXSTATUS0", + "TXDATA52": "GTXE2_CHANNEL_TXDATA52", + "RXDATA46": "GTXE2_CHANNEL_RXDATA46", + "RXOSHOLD": "GTXE2_CHANNEL_RXOSHOLD", + "RXCOMMADET": "GTXE2_CHANNEL_RXCOMMADET", + "RXCHBONDO3": "GTXE2_CHANNEL_RXCHBONDO3", + "RXDATA31": "GTXE2_CHANNEL_RXDATA31", + "RXUSERRDY": "GTXE2_CHANNEL_RXUSERRDY", + "RXCHBONDSLAVE": "GTXE2_CHANNEL_RXCHBONDSLAVE", + "RXCHBONDI2": "GTXE2_CHANNEL_RXCHBONDI2", + "PCSRSVDIN0": "GTXE2_CHANNEL_PCSRSVDIN0", + "TXDATA10": "GTXE2_CHANNEL_TXDATA10", + "TXCHARISK5": "GTXE2_CHANNEL_TXCHARISK5", + "RXPHMONITOR1": "GTXE2_CHANNEL_RXPHMONITOR1", + "TXDATA33": "GTXE2_CHANNEL_TXDATA33", + "TSTIN0": "GTXE2_CHANNEL_TSTIN0", + "TX8B10BEN": "GTXE2_CHANNEL_TX8B10BEN", + "PMASCANOUT3": "GTXE2_CHANNEL_PMASCANOUT3", + "RXDATA45": "GTXE2_CHANNEL_RXDATA45", + "GTREFCLKMONITOR": "GTXE2_CHANNEL_GTREFCLKMONITOR", + "PCSRSVDIN7": "GTXE2_CHANNEL_PCSRSVDIN7", + "TXCHARISK1": "GTXE2_CHANNEL_TXCHARISK1", + "TXRUNDISP0": "GTXE2_CHANNEL_TXRUNDISP0", + "RXDATA52": "GTXE2_CHANNEL_RXDATA52", + "RXPD1": "GTXE2_CHANNEL_RXPD1", + "TXDLYOVRDEN": "GTXE2_CHANNEL_TXDLYOVRDEN", + "TXDATA36": "GTXE2_CHANNEL_TXDATA36", + "RXPHSLIPMONITOR2": "GTXE2_CHANNEL_RXPHSLIPMONITOR2", + "TXMARGIN0": "GTXE2_CHANNEL_TXMARGIN0", + "TXDATA34": "GTXE2_CHANNEL_TXDATA34", + "TXSEQUENCE1": "GTXE2_CHANNEL_TXSEQUENCE1", + "RXCLKCORCNT0": "GTXE2_CHANNEL_RXCLKCORCNT0", + "RXCHBONDI1": "GTXE2_CHANNEL_RXCHBONDI1", + "GTRSVD8": "GTXE2_CHANNEL_GTRSVD8", + "CPLLPD": "GTXE2_CHANNEL_CPLLPD", + "RXDATA21": "GTXE2_CHANNEL_RXDATA21", + "RXCHARISCOMMA3": "GTXE2_CHANNEL_RXCHARISCOMMA3", + "TSTPD3": "GTXE2_CHANNEL_TSTPD3", + "GTRSVD12": "GTXE2_CHANNEL_GTRSVD12", + "RXDATA51": "GTXE2_CHANNEL_RXDATA51", + "PMASCANCLK0": "GTXE2_CHANNEL_PMASCANCLK0", + "TXDATA54": "GTXE2_CHANNEL_TXDATA54", + "TSTPD1": "GTXE2_CHANNEL_TSTPD1", + "GTXTXN": "GTXE2_CHANNEL_TXN", + "TXDATA32": "GTXE2_CHANNEL_TXDATA32", + "RXPHMONITOR2": "GTXE2_CHANNEL_RXPHMONITOR2", + "RXELECIDLEMODE1": "GTXE2_CHANNEL_RXELECIDLEMODE1", + "RXDATA28": "GTXE2_CHANNEL_RXDATA28", + "RXCHARISK5": "GTXE2_CHANNEL_RXCHARISK5", + "RXPHALIGNEN": "GTXE2_CHANNEL_RXPHALIGNEN", + "TSTIN19": "GTXE2_CHANNEL_TSTIN19", + "PMASCANIN2": "GTXE2_CHANNEL_PMASCANIN2", + "PMARSVDIN2": "GTXE2_CHANNEL_PMARSVDIN2", + "PCSRSVDIN5": "GTXE2_CHANNEL_PCSRSVDIN5", + "RXPHALIGNDONE": "GTXE2_CHANNEL_RXPHALIGNDONE", + "RXDATA0": "GTXE2_CHANNEL_RXDATA0", + "TXRATE2": "GTXE2_CHANNEL_TXRATE2", + "CPLLREFCLKSEL1": "GTXE2_CHANNEL_CPLLREFCLKSEL1", + "TSTOUT7": "GTXE2_CHANNEL_TSTOUT7", + "TXPHINITDONE": "GTXE2_CHANNEL_TXPHINITDONE", + "RXDATA15": "GTXE2_CHANNEL_RXDATA15", + "TXDATA16": "GTXE2_CHANNEL_TXDATA16", + "RXPRBSCNTRESET": "GTXE2_CHANNEL_RXPRBSCNTRESET", + "TXDATA14": "GTXE2_CHANNEL_TXDATA14", + "GTRSVD6": "GTXE2_CHANNEL_GTRSVD6", + "RXNOTINTABLE1": "GTXE2_CHANNEL_RXNOTINTABLE1", + "TXDATA2": "GTXE2_CHANNEL_TXDATA2", + "RXCHBONDO0": "GTXE2_CHANNEL_RXCHBONDO0", + "TXDEEMPH": "GTXE2_CHANNEL_TXDEEMPH", + "GTNORTHREFCLK1": "GTXE2_CHANNEL_GTNORTHREFCLK1", + "RXDFETAP4HOLD": "GTXE2_CHANNEL_RXDFETAP4HOLD", + "RXDFETAP5HOLD": "GTXE2_CHANNEL_RXDFETAP5HOLD", + "TXDATA7": "GTXE2_CHANNEL_TXDATA7", + "RXCHBONDO2": "GTXE2_CHANNEL_RXCHBONDO2", + "TXPRECURSOR2": "GTXE2_CHANNEL_TXPRECURSOR2", + "DRPDI11": "GTXE2_CHANNEL_DRPDI11", + "TXDETECTRX": "GTXE2_CHANNEL_TXDETECTRX", + "TXDATA0": "GTXE2_CHANNEL_TXDATA0", + "RXNOTINTABLE5": "GTXE2_CHANNEL_RXNOTINTABLE5", + "DRPADDR3": "GTXE2_CHANNEL_DRPADDR3", + "RXDATA42": "GTXE2_CHANNEL_RXDATA42", + "TXUSRCLK": "GTXE2_CHANNEL_TXUSRCLK", + "TXSYSCLKSEL1": "GTXE2_CHANNEL_TXSYSCLKSEL1", + "TX8B10BBYPASS0": "GTXE2_CHANNEL_TX8B10BBYPASS0", + "RXQPISENP": "GTXE2_CHANNEL_RXQPISENP", + "DRPDI13": "GTXE2_CHANNEL_DRPDI13", + "RXBUFSTATUS2": "GTXE2_CHANNEL_RXBUFSTATUS2", + "RXDISPERR0": "GTXE2_CHANNEL_RXDISPERR0", + "TXDATA46": "GTXE2_CHANNEL_TXDATA46", + "DRPDO1": "GTXE2_CHANNEL_DRPDO1", + "TXDATA15": "GTXE2_CHANNEL_TXDATA15", + "PCSRSVDIN3": "GTXE2_CHANNEL_PCSRSVDIN3", + "RXDLYSRESETDONE": "GTXE2_CHANNEL_RXDLYSRESETDONE", + "PCSRSVDIN1": "GTXE2_CHANNEL_PCSRSVDIN1", + "TXCHARDISPVAL3": "GTXE2_CHANNEL_TXCHARDISPVAL3", + "RXDFELFOVRDEN": "GTXE2_CHANNEL_RXDFELFOVRDEN", + "TXDATA41": "GTXE2_CHANNEL_TXDATA41", + "PCSRSVDOUT13": "GTXE2_CHANNEL_PCSRSVDOUT13", + "RXDATA27": "GTXE2_CHANNEL_RXDATA27", + "RXDATA30": "GTXE2_CHANNEL_RXDATA30", + "RXCHBONDI4": "GTXE2_CHANNEL_RXCHBONDI4", + "EDTSINGLEBYPASSCHAIN": "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", + "RXPRBSERR": "GTXE2_CHANNEL_RXPRBSERR", + "TXCOMWAKE": "GTXE2_CHANNEL_TXCOMWAKE", + "RXRATE0": "GTXE2_CHANNEL_RXRATE0", + "TSTIN4": "GTXE2_CHANNEL_TSTIN4", + "PMARSVDIN4": "GTXE2_CHANNEL_PMARSVDIN4", + "RXOUTCLKSEL2": "GTXE2_CHANNEL_RXOUTCLKSEL2", + "TSTOUT6": "GTXE2_CHANNEL_TSTOUT6", + "RXOOBRESET": "GTXE2_CHANNEL_RXOOBRESET", + "TSTPD4": "GTXE2_CHANNEL_TSTPD4", + "PMASCANRSTEN": "GTXE2_CHANNEL_PMASCANRSTEN", + "DRPDI8": "GTXE2_CHANNEL_DRPDI8", + "RXELECIDLEMODE0": "GTXE2_CHANNEL_RXELECIDLEMODE0", + "RXDATA6": "GTXE2_CHANNEL_RXDATA6", + "TXQPISTRONGPDOWN": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", + "TXHEADER2": "GTXE2_CHANNEL_TXHEADER2", + "PCSRSVDIN6": "GTXE2_CHANNEL_PCSRSVDIN6", + "DMONITOROUT2": "GTXE2_CHANNEL_DMONITOROUT2", + "TXDATA39": "GTXE2_CHANNEL_TXDATA39", + "TXRUNDISP7": "GTXE2_CHANNEL_TXRUNDISP7", + "TXPMARESET": "GTXE2_CHANNEL_TXPMARESET", + "RXDFETAP2OVRDEN": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", + "TX8B10BBYPASS7": "GTXE2_CHANNEL_TX8B10BBYPASS7", + "TSTIN1": "GTXE2_CHANNEL_TSTIN1", + "RXPHSLIPMONITOR0": "GTXE2_CHANNEL_RXPHSLIPMONITOR0", + "DRPDI1": "GTXE2_CHANNEL_DRPDI1", + "RXCDRRESET": "GTXE2_CHANNEL_RXCDRRESET", + "RXCHARISCOMMA1": "GTXE2_CHANNEL_RXCHARISCOMMA1", + "TXPOSTCURSOR2": "GTXE2_CHANNEL_TXPOSTCURSOR2", + "EYESCANDATAERROR": "GTXE2_CHANNEL_EYESCANDATAERROR", + "TXDATA6": "GTXE2_CHANNEL_TXDATA6", + "RXDLYSRESET": "GTXE2_CHANNEL_RXDLYSRESET", + "TXCHARDISPVAL0": "GTXE2_CHANNEL_TXCHARDISPVAL0", + "TXMAINCURSOR2": "GTXE2_CHANNEL_TXMAINCURSOR2", + "EDTBYPASS": "GTXE2_CHANNEL_EDTBYPASS", + "RXDISPERR6": "GTXE2_CHANNEL_RXDISPERR6", + "TXDATA44": "GTXE2_CHANNEL_TXDATA44", + "RXUSRCLK2": "GTXE2_CHANNEL_RXUSRCLK2", + "RXCHBONDI3": "GTXE2_CHANNEL_RXCHBONDI3", + "TSTCLK1": "GTXE2_CHANNEL_TSTCLK1", + "GTREFCLK0": "GTXE2_CHANNEL_GTREFCLK0", + "DRPDO8": "GTXE2_CHANNEL_DRPDO8", + "RXPHMONITOR0": "GTXE2_CHANNEL_RXPHMONITOR0", + "PMARSVDIN22": "GTXE2_CHANNEL_PMARSVDIN22", + "RXCHARISK3": "GTXE2_CHANNEL_RXCHARISK3", + "RXDFEAGCHOLD": "GTXE2_CHANNEL_RXDFEAGCHOLD", + "TXCHARISK2": "GTXE2_CHANNEL_TXCHARISK2", + "PCSRSVDIN23": "GTXE2_CHANNEL_PCSRSVDIN23", + "TSTOUT1": "GTXE2_CHANNEL_TSTOUT1", + "GTRSVD5": "GTXE2_CHANNEL_GTRSVD5", + "RXPHSLIPMONITOR3": "GTXE2_CHANNEL_RXPHSLIPMONITOR3", + "TXCHARDISPMODE4": "GTXE2_CHANNEL_TXCHARDISPMODE4", + "RXHEADER0": "GTXE2_CHANNEL_RXHEADER0", + "DRPDO0": "GTXE2_CHANNEL_DRPDO0", + "TXCHARISK6": "GTXE2_CHANNEL_TXCHARISK6", + "RXCLKCORCNT1": "GTXE2_CHANNEL_RXCLKCORCNT1", + "RXDFEAGCOVRDEN": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", + "TXDATA61": "GTXE2_CHANNEL_TXDATA61", + "RXDFEVSEN": "GTXE2_CHANNEL_RXDFEVSEN", + "DRPDO7": "GTXE2_CHANNEL_DRPDO7", + "PMARSVDIN21": "GTXE2_CHANNEL_PMARSVDIN21", + "PCSRSVDOUT1": "GTXE2_CHANNEL_PCSRSVDOUT1", + "PCSRSVDOUT4": "GTXE2_CHANNEL_PCSRSVDOUT4", + "RXNOTINTABLE4": "GTXE2_CHANNEL_RXNOTINTABLE4", + "RXNOTINTABLE3": "GTXE2_CHANNEL_RXNOTINTABLE3", + "GTRSVD15": "GTXE2_CHANNEL_GTRSVD15", + "TSTIN15": "GTXE2_CHANNEL_TSTIN15", + "DRPDO13": "GTXE2_CHANNEL_DRPDO13", + "RXDATAVALID": "GTXE2_CHANNEL_RXDATAVALID", + "RXDATA19": "GTXE2_CHANNEL_RXDATA19", + "RXBUFRESET": "GTXE2_CHANNEL_RXBUFRESET", + "TXPD0": "GTXE2_CHANNEL_TXPD0", + "PMARSVDIN1": "GTXE2_CHANNEL_PMARSVDIN1", + "RXDATA63": "GTXE2_CHANNEL_RXDATA63", + "TXMAINCURSOR3": "GTXE2_CHANNEL_TXMAINCURSOR3", + "RXDEBUGPULSE": "GTXE2_CHANNEL_RXDEBUGPULSE", + "RXDATA4": "GTXE2_CHANNEL_RXDATA4", + "PMASCANIN1": "GTXE2_CHANNEL_PMASCANIN1", + "TSTIN11": "GTXE2_CHANNEL_TSTIN11", + "CPLLREFCLKSEL2": "GTXE2_CHANNEL_CPLLREFCLKSEL2", + "SCANOUT1": "GTXE2_CHANNEL_SCANOUT1", + "TXRUNDISP2": "GTXE2_CHANNEL_TXRUNDISP2", + "PCSRSVDIN13": "GTXE2_CHANNEL_PCSRSVDIN13", + "SCANMODEB": "GTXE2_CHANNEL_SCANMODEB", + "GTRXRESET": "GTXE2_CHANNEL_GTRXRESET", + "PCSRSVDIN22": "GTXE2_CHANNEL_PCSRSVDIN22", + "TXDATA3": "GTXE2_CHANNEL_TXDATA3", + "TXMAINCURSOR5": "GTXE2_CHANNEL_TXMAINCURSOR5", + "GTRSVD2": "GTXE2_CHANNEL_GTRSVD2", + "CLKRSVD1": "GTXE2_CHANNEL_CLKRSVD1", + "TXOUTCLKSEL0": "GTXE2_CHANNEL_TXOUTCLKSEL0", + "TXDATA57": "GTXE2_CHANNEL_TXDATA57", + "TXPDELECIDLEMODE": "GTXE2_CHANNEL_TXPDELECIDLEMODE", + "PCSRSVDIN21": "GTXE2_CHANNEL_PCSRSVDIN21", + "TSTOUT3": "GTXE2_CHANNEL_TSTOUT3", + "PCSRSVDOUT15": "GTXE2_CHANNEL_PCSRSVDOUT15", + "TXSEQUENCE3": "GTXE2_CHANNEL_TXSEQUENCE3", + "TSTIN18": "GTXE2_CHANNEL_TSTIN18", + "TXRATE1": "GTXE2_CHANNEL_TXRATE1", + "TXSEQUENCE4": "GTXE2_CHANNEL_TXSEQUENCE4", + "RXSTARTOFSEQ": "GTXE2_CHANNEL_RXSTARTOFSEQ", + "RXPHALIGN": "GTXE2_CHANNEL_RXPHALIGN", + "RXDFEUTHOLD": "GTXE2_CHANNEL_RXDFEUTHOLD", + "DRPDI14": "GTXE2_CHANNEL_DRPDI14", + "TXRATEDONE": "GTXE2_CHANNEL_TXRATEDONE", + "TXDIFFPD": "GTXE2_CHANNEL_TXDIFFPD", + "TXCHARDISPVAL1": "GTXE2_CHANNEL_TXCHARDISPVAL1", + "RXDFELPMRESET": "GTXE2_CHANNEL_RXDFELPMRESET", + "RXCDRLOCK": "GTXE2_CHANNEL_RXCDRLOCK", + "TXDATA31": "GTXE2_CHANNEL_TXDATA31", + "RXCHARISK0": "GTXE2_CHANNEL_RXCHARISK0", + "RXDATA43": "GTXE2_CHANNEL_RXDATA43", + "TXDATA55": "GTXE2_CHANNEL_TXDATA55", + "TSTIN9": "GTXE2_CHANNEL_TSTIN9", + "TXQPIWEAKPUP": "GTXE2_CHANNEL_TXQPIWEAKPUP", + "TXDATA4": "GTXE2_CHANNEL_TXDATA4", + "RXSYSCLKSEL0": "GTXE2_CHANNEL_RXSYSCLKSEL0", + "DRPDO14": "GTXE2_CHANNEL_DRPDO14", + "TSTIN12": "GTXE2_CHANNEL_TSTIN12", + "DRPDI7": "GTXE2_CHANNEL_DRPDI7", + "TXSEQUENCE0": "GTXE2_CHANNEL_TXSEQUENCE0", + "RXDISPERR7": "GTXE2_CHANNEL_RXDISPERR7", + "CPLLLOCKDETCLK": "GTXE2_CHANNEL_CPLLLOCKDETCLK", + "DRPADDR4": "GTXE2_CHANNEL_DRPADDR4", + "RXCOMMADETEN": "GTXE2_CHANNEL_RXCOMMADETEN", + "DRPADDR2": "GTXE2_CHANNEL_DRPADDR2", + "TXPRECURSOR0": "GTXE2_CHANNEL_TXPRECURSOR0", + "PCSRSVDOUT7": "GTXE2_CHANNEL_PCSRSVDOUT7", + "RXPHSLIPMONITOR4": "GTXE2_CHANNEL_RXPHSLIPMONITOR4", + "TXPHINIT": "GTXE2_CHANNEL_TXPHINIT", + "DRPADDR5": "GTXE2_CHANNEL_DRPADDR5", + "TXDATA50": "GTXE2_CHANNEL_TXDATA50", + "PMASCANIN4": "GTXE2_CHANNEL_PMASCANIN4", + "TXPRECURSOR4": "GTXE2_CHANNEL_TXPRECURSOR4", + "PMASCANCLK1": "GTXE2_CHANNEL_PMASCANCLK1", + "TXPRBSSEL1": "GTXE2_CHANNEL_TXPRBSSEL1", + "GTRSVD11": "GTXE2_CHANNEL_GTRSVD11", + "DRPDO10": "GTXE2_CHANNEL_DRPDO10", + "TXDATA12": "GTXE2_CHANNEL_TXDATA12", + "RXDATA5": "GTXE2_CHANNEL_RXDATA5", + "TXCOMFINISH": "GTXE2_CHANNEL_TXCOMFINISH", + "TXDATA17": "GTXE2_CHANNEL_TXDATA17", + "GTTXRESET": "GTXE2_CHANNEL_GTTXRESET", + "PMASCANCLK3": "GTXE2_CHANNEL_PMASCANCLK3", + "TXDIFFCTRL1": "GTXE2_CHANNEL_TXDIFFCTRL1", + "TXPHDLYRESET": "GTXE2_CHANNEL_TXPHDLYRESET", + "RXDATA13": "GTXE2_CHANNEL_RXDATA13", + "TXDATA9": "GTXE2_CHANNEL_TXDATA9", + "PCSRSVDIN4": "GTXE2_CHANNEL_PCSRSVDIN4", + "DMONITOROUT7": "GTXE2_CHANNEL_DMONITOROUT7", + "TSTIN5": "GTXE2_CHANNEL_TSTIN5", + "RXDISPERR4": "GTXE2_CHANNEL_RXDISPERR4", + "TXDATA40": "GTXE2_CHANNEL_TXDATA40", + "TXDATA49": "GTXE2_CHANNEL_TXDATA49", + "PMARSVDIN3": "GTXE2_CHANNEL_PMARSVDIN3", + "RXDATA23": "GTXE2_CHANNEL_RXDATA23", + "TXMARGIN1": "GTXE2_CHANNEL_TXMARGIN1", + "TXDLYBYPASS": "GTXE2_CHANNEL_TXDLYBYPASS", + "PCSRSVDOUT0": "GTXE2_CHANNEL_PCSRSVDOUT0", + "TXOUTCLK": "GTXE2_CHANNEL_GTTXOUTCLK_1", + "RXLPMHFHOLD": "GTXE2_CHANNEL_RXLPMHFHOLD", + "RXDFEXYDEN": "GTXE2_CHANNEL_RXDFEXYDEN", + "TSTOUT9": "GTXE2_CHANNEL_TSTOUT9", + "TXDLYEN": "GTXE2_CHANNEL_TXDLYEN", + "RXUSRCLK": "GTXE2_CHANNEL_RXUSRCLK", + "RXDFEXYDHOLD": "GTXE2_CHANNEL_RXDFEXYDHOLD", + "TSTIN13": "GTXE2_CHANNEL_TSTIN13", + "TXPRBSFORCEERR": "GTXE2_CHANNEL_TXPRBSFORCEERR", + "CLKRSVD0": "GTXE2_CHANNEL_CLKRSVD0", + "RXPCD1DONE": "GTXE2_CHANNEL_RXPCD1DONE", + "DRPRDY": "GTXE2_CHANNEL_DRPRDY", + "RXDFEXYDOVRDEN": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", + "LOOPBACK1": "GTXE2_CHANNEL_LOOPBACK1", + "GTGREFCLK": "GTXE2_CHANNEL_GTGREFCLK", + "RXHEADER1": "GTXE2_CHANNEL_RXHEADER1", + "GTRSVD1": "GTXE2_CHANNEL_GTRSVD1", + "TXMAINCURSOR6": "GTXE2_CHANNEL_TXMAINCURSOR6", + "RXDATA17": "GTXE2_CHANNEL_RXDATA17", + "RXDATA22": "GTXE2_CHANNEL_RXDATA22", + "PCSRSVDOUT3": "GTXE2_CHANNEL_PCSRSVDOUT3", + "DRPDI0": "GTXE2_CHANNEL_DRPDI0", + "RXCHARISCOMMA5": "GTXE2_CHANNEL_RXCHARISCOMMA5", + "TXDATA58": "GTXE2_CHANNEL_TXDATA58", + "QPLLCLK": "GTXE2_CHANNEL_GTQPLLCLK", + "RXDDIEN": "GTXE2_CHANNEL_RXDDIEN", + "GTXTXP": "GTXE2_CHANNEL_TXP", + "PMASCANENB": "GTXE2_CHANNEL_PMASCANENB", + "TXDATA59": "GTXE2_CHANNEL_TXDATA59", + "GTRSVD10": "GTXE2_CHANNEL_GTRSVD10", + "RXDATA12": "GTXE2_CHANNEL_RXDATA12", + "RXCDROVRDEN": "GTXE2_CHANNEL_RXCDROVRDEN", + "TSTIN16": "GTXE2_CHANNEL_TSTIN16", + "TXDATA27": "GTXE2_CHANNEL_TXDATA27" + }, + "x_coord": 0 + }, + { + "y_coord": 31, + "name": "X0Y31", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "GTXE2_CHANNEL_RXN_PAD" + }, + "x_coord": 0 + }, + { + "y_coord": 32, + "name": "X0Y32", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "GTXE2_CHANNEL_RXP_PAD" + }, + "x_coord": 0 + }, + { + "y_coord": 5, + "name": "X0Y5", + "prefix": "OPAD", + "type": "OPAD", + "site_pins": { + "I": "GTXE2_CHANNEL_TXN_PAD" + }, + "x_coord": 0 + }, + { + "y_coord": 6, + "name": "X0Y6", + "prefix": "OPAD", + "type": "OPAD", + "site_pins": { + "I": "GTXE2_CHANNEL_TXP_PAD" + }, + "x_coord": 0 + } + ], + "wires": [ + "GTXE2_CHANNEL_PMASCANIN2", + "GTXE2_CHANNEL_RXDFETAP3HOLD", + "GTXE2_CHANNEL_RXHEADER0", + "GTXE2_IMUX29_3", + "GTXE2_LOGIC_OUTS_B21_5", + "GTXE2_CHANNEL_TXQPISENN", + "GTXE2_IMUX42_5", + "GTXE2_CHANNEL_TXDATA44", + "GTXE2_FAN2_6", + "GTXE2_IMUX23_5", + "GTXE2_LOGIC_OUTS_B19_1", + "GTXE2_CHANNEL_GTREFCLKMONITOR", + "GTXE2_CHANNEL_CPLLREFCLKSEL1", + "GTXE2_IMUX29_9", + "GTXE2_FAN5_4", + "GTXE2_LOGIC_OUTS_B23_10", + "GTXE2_CHANNEL_RXBUFSTATUS0", + "GTXE2_CHANNEL_PCSRSVDOUT13", + "GTXE2_CHANNEL_RXNOTINTABLE5", + "GTXE2_IMUX46_0", + "GTXE2_IMUX20_7", + "GTXE2_CHANNEL_DRPDI6", + "GTXE2_BYP2_3", + "GTXE2_CHANNEL_RXCHARISK4", + "GTXE2_CHANNEL_TXDIFFPD", + "GTXE2_IMUX4_4", + "GTXE2_IMUX6_0", + "GTXE2_IMUX25_4", + "GTXE2_IMUX3_2", + "GTXE2_CHANNEL_TSTIN11", + "GTXE2_CHANNEL_TSTIN8", + "GTXE2_IMUX31_7", + "GTXE2_CHANNEL_CPLLFBCLKLOST", + "GTXE2_IMUX41_9", + "GTXE2_CHANNEL_RXDLYEN", + "GTXE2_CHANNEL_RXCHARISK6", + "GTXE2_CHANNEL_GTQPLLREFCLK", + "GTXE2_CHANNEL_RXDISPERR7", + "GTXE2_CHANNEL_TXDLYBYPASS", + "GTXE2_CHANNEL_NORTHREFCLK1", + "GTXE2_IMUX26_0", + "GTXE2_CHANNEL_TXCHARDISPMODE0", + "GTXE2_LOGIC_OUTS_B23_6", + "GTXE2_CHANNEL_PCSRSVDIN24", + "GTXE2_IMUX9_2", + "GTXE2_LOGIC_OUTS_B19_2", + "GTXE2_LOGIC_OUTS_B22_8", + "GTXE2_LOGIC_OUTS_B4_1", + "GTXE2_FAN7_10", + "GTXE2_CHANNEL_RXDATA35", + "GTXE2_IMUX35_10", + "GTXE2_IMUX33_8", + "GTXE2_IMUX42_8", + "GTXE2_FAN3_8", + "GTXE2_BYP0_5", + "GTXE2_CHANNEL_PCSRSVDOUT5", + "GTXE2_CTRL0_4", + "GTXE2_CHANNEL_TXDATA24", + "GTXE2_BYP7_7", + "GTXE2_IMUX7_2", + "GTXE2_IMUX30_8", + "GTXE2_FAN5_10", + "GTXE2_IMUX15_9", + "GTXE2_CHANNEL_RXHEADERVALID", + "GTXE2_BYP1_10", + "GTXE2_CHANNEL_CPLLPD", + "GTXE2_CHANNEL_RXDFETAP2OVRDEN", + "GTXE2_CHANNEL_RXBYTEISALIGNED", + "GTXE2_LOGIC_OUTS_B2_1", + "GTXE2_CHANNEL_TXDATA48", + "GTXE2_CHANNEL_TXDATA32", + "GTXE2_CHANNEL_RXCHBONDO2", + "GTXE2_CHANNEL_PMASCANCLK1", + "GTXE2_CHANNEL_TXDLYSRESET", + "GTXE2_IMUX35_9", + "GTXE2_LOGIC_OUTS_B9_7", + "GTXE2_IMUX43_0", + "GTXE2_IMUX23_7", + "GTXE2_CHANNEL_PMASCANCLK3", + "GTXE2_FAN1_9", + "GTXE2_CHANNEL_CPLLREFCLKSEL0", + "GTXE2_IMUX26_9", + "GTXE2_LOGIC_OUTS_B1_4", + "GTXE2_CHANNEL_TXDATA29", + "GTXE2_LOGIC_OUTS_B20_8", + "GTXE2_FAN3_9", + "GTXE2_IMUX18_7", + "GTXE2_LOGIC_OUTS_B12_4", + "GTXE2_CHANNEL_TXCHARISK7", + "GTXE2_LOGIC_OUTS_B1_9", + "GTXE2_CHANNEL_RXDATA28", + "GTXE2_CHANNEL_RXMCOMMAALIGNEN", + "GTXE2_IMUX47_8", + "GTXE2_CHANNEL_RXCHBONDMASTER", + "GTXE2_CHANNEL_TXCHARDISPVAL5", + "GTXE2_IMUX19_6", + "GTXE2_IMUX10_4", + "GTXE2_FAN5_3", + "GTXE2_CHANNEL_RXPHSLIPMONITOR4", + "GTXE2_FAN1_8", + "GTXE2_CHANNEL_TXCHARISK3", + "GTXE2_BYP1_4", + "GTXE2_FAN0_6", + "GTXE2_CHANNEL_DRPADDR4", + "GTXE2_CHANNEL_RXPRBSSEL2", + "GTXE2_IMUX1_3", + "GTXE2_IMUX1_5", + "GTXE2_IMUX31_10", + "GTXE2_LOGIC_OUTS_B15_9", + "GTXE2_CHANNEL_RXN", + "GTXE2_CHANNEL_TXDEEMPH", + "GTXE2_CHANNEL_TSTIN6", + "GTXE2_CHANNEL_PMASCANRSTEN", + "GTXE2_CHANNEL_LOOPBACK1", + "GTXE2_CHANNEL_TXOUTCLK_0", + "GTXE2_BYP1_2", + "GTXE2_CHANNEL_TXDATA63", + "GTXE2_IMUX6_2", + "GTXE2_LOGIC_OUTS_B23_5", + "GTXE2_CHANNEL_RXDATA15", + "GTXE2_CHANNEL_TXCHARDISPMODE5", + "GTXE2_LOGIC_OUTS_B7_9", + "GTXE2_CHANNEL_RXCDRRESET", + "GTXE2_CHANNEL_TSTIN4", + "GTXE2_CHANNEL_RXOOBRESET", + "GTXE2_FAN7_6", + "GTXE2_CTRL0_7", + "GTXE2_IMUX37_2", + "GTXE2_CHANNEL_RXDATA50", + "GTXE2_CHANNEL_TXDATA36", + "GTXE2_IMUX45_0", + "GTXE2_BYP4_7", + "GTXE2_FAN7_0", + "GTXE2_LOGIC_OUTS_B19_6", + "GTXE2_CHANNEL_RXDATA54", + "GTXE2_CHANNEL_RXCOMMADET", + "GTXE2_CLK1_7", + "GTXE2_IMUX46_1", + "GTXE2_CHANNEL_RXQPIEN", + "GTXE2_CHANNEL_RXSTATUS2", + "GTXE2_IMUX30_2", + "GTXE2_CHANNEL_RXOUTCLKSEL2", + "GTXE2_BYP5_5", + "GTXE2_IMUX22_4", + "GTXE2_BYP2_0", + "GTXE2_IMUX35_1", + "GTXE2_CHANNEL_RXDATA17", + "GTXE2_IMUX15_0", + "GTXE2_BYP5_3", + "GTXE2_LOGIC_OUTS_B6_7", + "GTXE2_CHANNEL_RXCOMWAKEDET", + "GTXE2_LOGIC_OUTS_B3_0", + "GTXE2_BYP1_1", + "GTXE2_LOGIC_OUTS_B3_1", + "GTXE2_IMUX24_4", + "GTXE2_FAN1_5", + "GTXE2_IMUX44_0", + "GTXE2_LOGIC_OUTS_B5_3", + "GTXE2_CHANNEL_RXSTATUS1", + "GTXE2_CHANNEL_RXDATA62", + "GTXE2_BYP0_7", + "GTXE2_LOGIC_OUTS_B19_10", + "GTXE2_CLK1_9", + "GTXE2_CHANNEL_PCSRSVDIN7", + "GTXE2_LOGIC_OUTS_B7_7", + "GTXE2_CHANNEL_TXDATA28", + "GTXE2_IMUX22_10", + "GTXE2_LOGIC_OUTS_B21_3", + "GTXE2_FAN5_8", + "GTXE2_IMUX39_5", + "GTXE2_IMUX22_1", + "GTXE2_CHANNEL_PMARSVDIN24", + "GTXE2_CHANNEL_RXCHBONDI3", + "GTXE2_IMUX8_8", + "GTXE2_IMUX44_2", + "GTXE2_LOGIC_OUTS_B11_4", + "GTXE2_CHANNEL_TSTIN19", + "GTXE2_IMUX23_0", + "GTXE2_CHANNEL_TXDATA13", + "GTXE2_LOGIC_OUTS_B21_8", + "GTXE2_IMUX44_9", + "GTXE2_CHANNEL_GTRSVD0", + "GTXE2_CHANNEL_DRPCLK", + "GTXE2_CHANNEL_GTRSVD13", + "GTXE2_BYP5_8", + "GTXE2_IMUX11_9", + "GTXE2_LOGIC_OUTS_B8_6", + "GTXE2_CHANNEL_RXCHARISCOMMA4", + "GTXE2_IMUX42_2", + "GTXE2_IMUX41_10", + "GTXE2_CHANNEL_TSTPD2", + "GTXE2_CHANNEL_TXPRECURSOR2", + "GTXE2_LOGIC_OUTS_B11_9", + "GTXE2_IMUX2_7", + "GTXE2_CHANNEL_TXDATA19", + "GTXE2_IMUX1_4", + "GTXE2_CHANNEL_TXSEQUENCE6", + "GTXE2_IMUX31_3", + "GTXE2_LOGIC_OUTS_B23_9", + "GTXE2_LOGIC_OUTS_B10_8", + "GTXE2_CHANNEL_CLKRSVD2", + "GTXE2_CLK1_10", + "GTXE2_IMUX13_9", + "GTXE2_IMUX21_10", + "GTXE2_BYP7_10", + "GTXE2_CTRL0_8", + "GTXE2_CHANNEL_TXPHDLYRESET", + "GTXE2_BYP7_2", + "GTXE2_CHANNEL_PCSRSVDOUT15", + "GTXE2_BYP6_8", + "GTXE2_CHANNEL_TXDATA16", + "GTXE2_IMUX11_8", + "GTXE2_CHANNEL_TXMAINCURSOR1", + "GTXE2_CHANNEL_PCSRSVDOUT11", + "GTXE2_IMUX22_8", + "GTXE2_IMUX17_1", + "GTXE2_FAN3_10", + "GTXE2_CHANNEL_TXRUNDISP5", + "GTXE2_CHANNEL_TXPOSTCURSOR0", + "GTXE2_IMUX21_0", + "GTXE2_CTRL1_7", + "GTXE2_CHANNEL_RXOUTCLKFABRIC", + "GTXE2_IMUX45_8", + "GTXE2_CHANNEL_RXCHBONDO4", + "GTXE2_LOGIC_OUTS_B20_0", + "GTXE2_BYP6_5", + "GTXE2_IMUX33_10", + "GTXE2_IMUX46_3", + "GTXE2_IMUX8_7", + "GTXE2_CHANNEL_RXOSHOLD", + "GTXE2_BYP2_10", + "GTXE2_CHANNEL_TXDATA8", + "GTXE2_CHANNEL_RXCHARISK2", + "GTXE2_CHANNEL_DRPDO10", + "GTXE2_LOGIC_OUTS_B17_9", + "GTXE2_IMUX9_1", + "GTXE2_IMUX12_1", + "GTXE2_IMUX0_10", + "GTXE2_CHANNEL_RXELECIDLE", + "GTXE2_CHANNEL_DRPDI10", + "GTXE2_FAN7_1", + "GTXE2_CHANNEL_RXDATA42", + "GTXE2_CHANNEL_TXCHARDISPMODE6", + "GTXE2_IMUX5_8", + "GTXE2_LOGIC_OUTS_B5_8", + "GTXE2_CHANNEL_TXQPISENP", + "GTXE2_CHANNEL_RXDATA21", + "GTXE2_CHANNEL_TXPOSTCURSORINV", + "GTXE2_LOGIC_OUTS_B9_0", + "GTXE2_IMUX0_5", + "GTXE2_BYP1_7", + "GTXE2_FAN4_9", + "GTXE2_IMUX25_10", + "GTXE2_CHANNEL_RXELECIDLEMODE0", + "GTXE2_LOGIC_OUTS_B20_10", + "GTXE2_CHANNEL_RXDATA39", + "GTXE2_CHANNEL_TXPHOVRDEN", + "GTXE2_IMUX22_3", + "GTXE2_CHANNEL_PMARSVDIN22", + "GTXE2_IMUX36_2", + "GTXE2_FAN6_3", + "GTXE2_CHANNEL_GTRSVD5", + "GTXE2_LOGIC_OUTS_B3_2", + "GTXE2_IMUX2_5", + "GTXE2_IMUX33_4", + "GTXE2_CHANNEL_DMONITOROUT4", + "GTXE2_IMUX40_3", + "GTXE2_CHANNEL_DMONITOROUT5", + "GTXE2_CHANNEL_TXRUNDISP4", + "GTXE2_CHANNEL_DRPADDR8", + "GTXE2_IMUX27_4", + "GTXE2_IMUX36_3", + "GTXE2_LOGIC_OUTS_B8_10", + "GTXE2_IMUX31_9", + "GTXE2_LOGIC_OUTS_B16_0", + "GTXE2_IMUX11_0", + "GTXE2_CHANNEL_PCSRSVDOUT1", + "GTXE2_IMUX24_1", + "GTXE2_FAN3_0", + "GTXE2_CHANNEL_RXVALID", + "GTXE2_IMUX5_7", + "GTXE2_BYP6_10", + "GTXE2_CHANNEL_PCSRSVDIN6", + "GTXE2_IMUX23_6", + "GTXE2_CHANNEL_RXNOTINTABLE1", + "GTXE2_CHANNEL_DRPRDY", + "GTXE2_IMUX1_10", + "GTXE2_IMUX25_8", + "GTXE2_LOGIC_OUTS_B14_4", + "GTXE2_CHANNEL_TXSWING", + "GTXE2_IMUX28_8", + "GTXE2_IMUX28_7", + "GTXE2_CHANNEL_PCSRSVDOUT14", + "GTXE2_CHANNEL_TXCOMWAKE", + "GTXE2_IMUX3_3", + "GTXE2_IMUX10_6", + "GTXE2_CHANNEL_TXPHDLYPD", + "GTXE2_CHANNEL_TSTIN7", + "GTXE2_CHANNEL_RESETOVRD", + "GTXE2_IMUX10_0", + "GTXE2_IMUX3_1", + "GTXE2_LOGIC_OUTS_B19_7", + "GTXE2_CHANNEL_DRPDO6", + "GTXE2_CHANNEL_RXDFEVPOVRDEN", + "GTXE2_IMUX37_6", + "GTXE2_IMUX16_9", + "GTXE2_BYP3_6", + "GTXE2_BYP7_5", + "GTXE2_CHANNEL_RXPD0", + "GTXE2_LOGIC_OUTS_B12_5", + "GTXE2_LOGIC_OUTS_B3_3", + "GTXE2_IMUX12_10", + "GTXE2_CHANNEL_RXP_PAD", + "GTXE2_IMUX14_1", + "GTXE2_CHANNEL_TXDATA40", + "GTXE2_IMUX32_8", + "GTXE2_IMUX12_5", + "GTXE2_LOGIC_OUTS_B13_1", + "GTXE2_LOGIC_OUTS_B8_4", + "GTXE2_LOGIC_OUTS_B17_0", + "GTXE2_IMUX44_8", + "GTXE2_CTRL1_1", + "GTXE2_LOGIC_OUTS_B7_1", + "GTXE2_IMUX4_10", + "GTXE2_CHANNEL_DMONITOROUT6", + "GTXE2_CHANNEL_TXDATA3", + "GTXE2_CHANNEL_RXBUFSTATUS2", + "GTXE2_CHANNEL_RXDFEVPHOLD", + "GTXE2_LOGIC_OUTS_B5_4", + "GTXE2_IMUX14_10", + "GTXE2_IMUX27_2", + "GTXE2_IMUX13_8", + "GTXE2_LOGIC_OUTS_B16_6", + "GTXE2_IMUX15_5", + "GTXE2_LOGIC_OUTS_B2_10", + "GTXE2_IMUX41_2", + "GTXE2_CHANNEL_TXRUNDISP2", + "GTXE2_LOGIC_OUTS_B10_1", + "GTXE2_CHANNEL_SCANIN0", + "GTXE2_IMUX23_4", + "GTXE2_CLK1_5", + "GTXE2_IMUX6_9", + "GTXE2_IMUX21_3", + "GTXE2_IMUX11_4", + "GTXE2_IMUX25_9", + "GTXE2_CHANNEL_TXQPISTRONGPDOWN", + "GTXE2_BYP5_7", + "GTXE2_IMUX47_10", + "GTXE2_IMUX22_6", + "GTXE2_CHANNEL_SCANENB", + "GTXE2_CHANNEL_NORTHREFCLK0", + "GTXE2_CHANNEL_RXPHMONITOR0", + "GTXE2_LOGIC_OUTS_B15_1", + "GTXE2_CHANNEL_RXCHANREALIGN", + "GTXE2_CHANNEL_DMONITOROUT2", + "GTXE2_IMUX40_2", + "GTXE2_IMUX39_6", + "GTXE2_CHANNEL_RXCOMSASDET", + "GTXE2_CTRL1_10", + "GTXE2_CHANNEL_TXDATA59", + "GTXE2_IMUX21_6", + "GTXE2_IMUX22_9", + "GTXE2_LOGIC_OUTS_B11_10", + "GTXE2_IMUX1_0", + "GTXE2_LOGIC_OUTS_B0_5", + "GTXE2_FAN5_9", + "GTXE2_LOGIC_OUTS_B22_3", + "GTXE2_FAN5_5", + "GTXE2_FAN4_3", + "GTXE2_LOGIC_OUTS_B1_0", + "GTXE2_LOGIC_OUTS_B9_5", + "GTXE2_CHANNEL_RXCHBONDEN", + "GTXE2_LOGIC_OUTS_B6_6", + "GTXE2_CHANNEL_TXPRBSSEL0", + "GTXE2_BYP0_0", + "GTXE2_IMUX17_10", + "GTXE2_LOGIC_OUTS_B12_2", + "GTXE2_IMUX27_1", + "GTXE2_IMUX12_9", + "GTXE2_IMUX28_4", + "GTXE2_LOGIC_OUTS_B16_3", + "GTXE2_LOGIC_OUTS_B19_5", + "GTXE2_CHANNEL_TXHEADER1", + "GTXE2_IMUX11_7", + "GTXE2_LOGIC_OUTS_B15_4", + "GTXE2_IMUX19_4", + "GTXE2_IMUX32_2", + "GTXE2_LOGIC_OUTS_B12_1", + "GTXE2_CHANNEL_TXCHARDISPMODE2", + "GTXE2_IMUX30_3", + "GTXE2_CHANNEL_RXUSRCLK", + "GTXE2_CHANNEL_TSTCLK0", + "GTXE2_CHANNEL_DRPDI9", + "GTXE2_CHANNEL_TXDATA9", + "GTXE2_LOGIC_OUTS_B21_2", + "GTXE2_IMUX19_5", + "GTXE2_IMUX27_5", + "GTXE2_FAN0_8", + "GTXE2_CHANNEL_DRPDI13", + "GTXE2_FAN2_5", + "GTXE2_CHANNEL_RXDFEVSEN", + "GTXE2_IMUX37_7", + "GTXE2_LOGIC_OUTS_B23_2", + "GTXE2_IMUX2_2", + "GTXE2_CHANNEL_TX8B10BBYPASS6", + "GTXE2_CHANNEL_TXPOSTCURSOR1", + "GTXE2_CHANNEL_RXDATAVALID", + "GTXE2_CHANNEL_TXDATA31", + "GTXE2_CHANNEL_TXPHDLYTSTCLK", + "GTXE2_CHANNEL_TXCHARISK0", + "GTXE2_LOGIC_OUTS_B3_10", + "GTXE2_CHANNEL_PMARSVDIN3", + "GTXE2_IMUX34_5", + "GTXE2_CHANNEL_TXDATA6", + "GTXE2_CHANNEL_RXPRBSCNTRESET", + "GTXE2_IMUX3_7", + "GTXE2_CHANNEL_TXRUNDISP1", + "GTXE2_IMUX40_0", + "GTXE2_IMUX9_5", + "GTXE2_IMUX4_5", + "GTXE2_FAN6_9", + "GTXE2_CHANNEL_TSTIN0", + "GTXE2_FAN4_0", + "GTXE2_CHANNEL_TXDATA14", + "GTXE2_CHANNEL_TSTIN9", + "GTXE2_LOGIC_OUTS_B4_4", + "GTXE2_BYP0_3", + "GTXE2_FAN3_5", + "GTXE2_CHANNEL_TSTIN12", + "GTXE2_CHANNEL_TXCHARISK1", + "GTXE2_IMUX40_9", + "GTXE2_CHANNEL_TXDATA10", + "GTXE2_CHANNEL_RXNOTINTABLE6", + "GTXE2_IMUX39_3", + "GTXE2_LOGIC_OUTS_B4_7", + "GTXE2_IMUX43_7", + "GTXE2_CHANNEL_TXBUFDIFFCTRL2", + "GTXE2_IMUX5_4", + "GTXE2_CHANNEL_TXDATA30", + "GTXE2_IMUX39_1", + "GTXE2_CHANNEL_CPLLREFCLKLOST", + "GTXE2_CTRL0_9", + "GTXE2_LOGIC_OUTS_B21_7", + "GTXE2_CHANNEL_GTREFCLK1", + "GTXE2_BYP0_8", + "GTXE2_CHANNEL_DRPDI14", + "GTXE2_IMUX33_2", + "GTXE2_LOGIC_OUTS_B11_5", + "GTXE2_IMUX17_4", + "GTXE2_CHANNEL_TXDATA0", + "GTXE2_CHANNEL_EYESCANMODE", + "GTXE2_LOGIC_OUTS_B4_2", + "GTXE2_CHANNEL_SCANOUT3", + "GTXE2_IMUX13_2", + "GTXE2_IMUX19_9", + "GTXE2_LOGIC_OUTS_B9_1", + "GTXE2_CHANNEL_GTRSVD11", + "GTXE2_IMUX10_8", + "GTXE2_LOGIC_OUTS_B18_1", + "GTXE2_CHANNEL_RXDDIEN", + "GTXE2_IMUX5_1", + "GTXE2_IMUX35_5", + "GTXE2_IMUX32_6", + "GTXE2_IMUX40_8", + "GTXE2_CTRL1_2", + "GTXE2_LOGIC_OUTS_B6_2", + "GTXE2_LOGIC_OUTS_B16_8", + "GTXE2_IMUX40_10", + "GTXE2_CHANNEL_PMASCANCLK2", + "GTXE2_LOGIC_OUTS_B2_4", + "GTXE2_CHANNEL_PCSRSVDIN22", + "GTXE2_IMUX9_7", + "GTXE2_CHANNEL_DRPDI8", + "GTXE2_CHANNEL_TXPHINITDONE", + "GTXE2_FAN5_2", + "GTXE2_CHANNEL_LOOPBACK0", + "GTXE2_IMUX29_8", + "GTXE2_LOGIC_OUTS_B17_7", + "GTXE2_LOGIC_OUTS_B11_3", + "GTXE2_CHANNEL_CPLLLOCK", + "GTXE2_CHANNEL_RXDFETAP4OVRDEN", + "GTXE2_IMUX0_8", + "GTXE2_BYP4_4", + "GTXE2_LOGIC_OUTS_B10_9", + "GTXE2_CHANNEL_RXBUFRESET", + "GTXE2_IMUX12_2", + "GTXE2_CHANNEL_PCSRSVDOUT7", + "GTXE2_LOGIC_OUTS_B9_9", + "GTXE2_IMUX5_10", + "GTXE2_LOGIC_OUTS_B20_5", + "GTXE2_CHANNEL_PCSRSVDIN23", + "GTXE2_IMUX8_2", + "GTXE2_CHANNEL_TXDATA42", + "GTXE2_IMUX46_2", + "GTXE2_IMUX40_6", + "GTXE2_IMUX33_1", + "GTXE2_FAN6_0", + "GTXE2_LOGIC_OUTS_B11_7", + "GTXE2_BYP2_8", + "GTXE2_IMUX47_0", + "GTXE2_FAN0_3", + "GTXE2_CHANNEL_RXPHDLYRESET", + "GTXE2_LOGIC_OUTS_B11_6", + "GTXE2_LOGIC_OUTS_B8_3", + "GTXE2_IMUX36_4", + "GTXE2_CHANNEL_GTRESETSEL", + "GTXE2_CHANNEL_GTGREFCLK", + "GTXE2_LOGIC_OUTS_B11_0", + "GTXE2_LOGIC_OUTS_B5_9", + "GTXE2_IMUX34_2", + "GTXE2_IMUX8_3", + "GTXE2_LOGIC_OUTS_B14_1", + "GTXE2_LOGIC_OUTS_B18_6", + "GTXE2_CHANNEL_GTRSVD15", + "GTXE2_CHANNEL_RXDATA7", + "GTXE2_LOGIC_OUTS_B3_6", + "GTXE2_CHANNEL_RXCHARISK0", + "GTXE2_IMUX4_3", + "GTXE2_IMUX16_1", + "GTXE2_CHANNEL_RXDATA11", + "GTXE2_CHANNEL_TX8B10BBYPASS2", + "GTXE2_IMUX19_10", + "GTXE2_CHANNEL_TXDATA61", + "GTXE2_CHANNEL_RXDATA19", + "GTXE2_BYP5_10", + "GTXE2_IMUX20_1", + "GTXE2_IMUX16_6", + "GTXE2_IMUX26_7", + "GTXE2_CHANNEL_PMASCANOUT2", + "GTXE2_CHANNEL_TSTIN2", + "GTXE2_IMUX1_2", + "GTXE2_BYP4_3", + "GTXE2_LOGIC_OUTS_B18_7", + "GTXE2_CHANNEL_PCSRSVDIN21", + "GTXE2_CHANNEL_RXDISPERR3", + "GTXE2_IMUX40_5", + "GTXE2_FAN3_6", + "GTXE2_IMUX20_3", + "GTXE2_FAN7_2", + "GTXE2_CHANNEL_RXDLYTESTENB", + "GTXE2_FAN4_7", + "GTXE2_FAN2_0", + "GTXE2_IMUX32_9", + "GTXE2_IMUX30_9", + "GTXE2_IMUX32_4", + "GTXE2_CHANNEL_GTRSVD10", + "GTXE2_IMUX30_1", + "GTXE2_CHANNEL_DRPDO15", + "GTXE2_CHANNEL_TXDLYSRESETDONE", + "GTXE2_FAN2_3", + "GTXE2_IMUX30_5", + "GTXE2_LOGIC_OUTS_B6_4", + "GTXE2_CHANNEL_TXPOLARITY", + "GTXE2_CHANNEL_GTRSVD8", + "GTXE2_CHANNEL_TXDATA43", + "GTXE2_IMUX43_5", + "GTXE2_LOGIC_OUTS_B18_5", + "GTXE2_BYP3_0", + "GTXE2_BYP6_2", + "GTXE2_CHANNEL_TXDATA57", + "GTXE2_IMUX27_9", + "GTXE2_CHANNEL_DRPADDR0", + "GTXE2_CHANNEL_TXDATA15", + "GTXE2_IMUX10_1", + "GTXE2_CHANNEL_PCSRSVDOUT0", + "GTXE2_CHANNEL_PMARSVDIN1", + "GTXE2_IMUX4_1", + "GTXE2_IMUX39_2", + "GTXE2_CHANNEL_REFCLK1", + "GTXE2_IMUX9_8", + "GTXE2_LOGIC_OUTS_B21_1", + "GTXE2_IMUX4_0", + "GTXE2_BYP3_8", + "GTXE2_CHANNEL_DRPDO8", + "GTXE2_IMUX11_5", + "GTXE2_IMUX24_8", + "GTXE2_IMUX44_3", + "GTXE2_IMUX20_4", + "GTXE2_CHANNEL_RXDLYOVRDEN", + "GTXE2_CTRL1_5", + "GTXE2_CHANNEL_DRPWE", + "GTXE2_IMUX20_0", + "GTXE2_BYP3_10", + "GTXE2_LOGIC_OUTS_B5_1", + "GTXE2_CHANNEL_RXMONITORSEL0", + "GTXE2_CHANNEL_TXPRECURSOR0", + "GTXE2_CHANNEL_RXDATA10", + "GTXE2_CHANNEL_DMONITOROUT3", + "GTXE2_CHANNEL_TXDATA34", + "GTXE2_CHANNEL_TXDATA1", + "GTXE2_IMUX16_10", + "GTXE2_IMUX15_6", + "GTXE2_BYP0_10", + "GTXE2_CHANNEL_RXSTATUS0", + "GTXE2_FAN1_1", + "GTXE2_IMUX12_0", + "GTXE2_FAN0_2", + "GTXE2_LOGIC_OUTS_B0_6", + "GTXE2_IMUX37_8", + "GTXE2_CHANNEL_TXRUNDISP7", + "GTXE2_CHANNEL_DRPDI3", + "GTXE2_IMUX8_4", + "GTXE2_CHANNEL_RXDATA58", + "GTXE2_FAN3_1", + "GTXE2_CHANNEL_TXDATA41", + "GTXE2_BYP7_9", + "GTXE2_BYP4_1", + "GTXE2_LOGIC_OUTS_B18_2", + "GTXE2_CHANNEL_TXRATE1", + "GTXE2_CHANNEL_TXDLYOVRDEN", + "GTXE2_IMUX4_9", + "GTXE2_IMUX34_7", + "GTXE2_LOGIC_OUTS_B2_9", + "GTXE2_IMUX39_9", + "GTXE2_CHANNEL_RXDATA52", + "GTXE2_IMUX6_6", + "GTXE2_IMUX2_4", + "GTXE2_IMUX9_4", + "GTXE2_CHANNEL_PCSRSVDOUT12", + "GTXE2_IMUX3_4", + "GTXE2_CHANNEL_TSTPDOVRDB", + "GTXE2_CLK1_1", + "GTXE2_IMUX1_6", + "GTXE2_CHANNEL_TXDATA47", + "GTXE2_BYP4_2", + "GTXE2_CHANNEL_RXQPISENN", + "GTXE2_CHANNEL_RXPHMONITOR1", + "GTXE2_FAN6_2", + "GTXE2_CHANNEL_RXMONITOROUT4", + "GTXE2_CHANNEL_TXPRECURSOR3", + "GTXE2_CHANNEL_DRPDO7", + "GTXE2_LOGIC_OUTS_B6_0", + "GTXE2_IMUX17_5", + "GTXE2_LOGIC_OUTS_B10_2", + "GTXE2_CHANNEL_TXN_PAD", + "GTXE2_BYP3_3", + "GTXE2_IMUX2_3", + "GTXE2_CHANNEL_TXDATA62", + "GTXE2_FAN3_7", + "GTXE2_IMUX7_1", + "GTXE2_LOGIC_OUTS_B13_5", + "GTXE2_CHANNEL_RXRESETDONE", + "GTXE2_IMUX40_1", + "GTXE2_CHANNEL_TSTOUT6", + "GTXE2_IMUX36_10", + "GTXE2_CHANNEL_TXCOMINIT", + "GTXE2_LOGIC_OUTS_B0_9", + "GTXE2_IMUX4_8", + "GTXE2_IMUX29_4", + "GTXE2_IMUX45_9", + "GTXE2_FAN2_8", + "GTXE2_IMUX10_10", + "GTXE2_CHANNEL_RXDATA34", + "GTXE2_CHANNEL_PCSRSVDIN5", + "GTXE2_CHANNEL_GTRSVD9", + "GTXE2_IMUX6_1", + "GTXE2_IMUX43_2", + "GTXE2_LOGIC_OUTS_B0_10", + "GTXE2_IMUX30_6", + "GTXE2_LOGIC_OUTS_B14_5", + "GTXE2_IMUX42_7", + "GTXE2_IMUX21_8", + "GTXE2_IMUX35_7", + "GTXE2_CHANNEL_RXLPMHFOVRDEN", + "GTXE2_IMUX18_4", + "GTXE2_CHANNEL_RXPRBSSEL0", + "GTXE2_IMUX0_2", + "GTXE2_CHANNEL_PCSRSVDIN13", + "GTXE2_LOGIC_OUTS_B0_4", + "GTXE2_IMUX46_9", + "GTXE2_CHANNEL_PCSRSVDIN15", + "GTXE2_CHANNEL_TXP", + "GTXE2_CHANNEL_RXCHARISK5", + "GTXE2_CHANNEL_TXMAINCURSOR0", + "GTXE2_CHANNEL_TXDATA53", + "GTXE2_LOGIC_OUTS_B15_8", + "GTXE2_CHANNEL_DRPDO13", + "GTXE2_IMUX33_9", + "GTXE2_IMUX25_3", + "GTXE2_CHANNEL_TXMAINCURSOR3", + "GTXE2_CHANNEL_DRPDO4", + "GTXE2_IMUX42_4", + "GTXE2_IMUX31_5", + "GTXE2_CHANNEL_RXDATA32", + "GTXE2_LOGIC_OUTS_B20_6", + "GTXE2_LOGIC_OUTS_B13_9", + "GTXE2_CHANNEL_TXRATEDONE", + "GTXE2_CHANNEL_RXRATEDONE", + "GTXE2_FAN6_1", + "GTXE2_IMUX43_1", + "GTXE2_IMUX39_8", + "GTXE2_IMUX45_3", + "GTXE2_IMUX45_5", + "GTXE2_CTRL0_3", + "GTXE2_IMUX41_7", + "GTXE2_CHANNEL_RXCHBONDO3", + "GTXE2_CHANNEL_TXCHARDISPVAL3", + "GTXE2_CHANNEL_TXDATA45", + "GTXE2_CHANNEL_TXUSERRDY", + "GTXE2_FAN4_5", + "GTXE2_FAN5_1", + "GTXE2_LOGIC_OUTS_B8_7", + "GTXE2_CHANNEL_TSTPD4", + "GTXE2_CHANNEL_PMASCANCLK0", + "GTXE2_IMUX23_10", + "GTXE2_CHANNEL_TXBUFDIFFCTRL0", + "GTXE2_BYP0_9", + "GTXE2_FAN2_9", + "GTXE2_IMUX15_4", + "GTXE2_IMUX6_4", + "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", + "GTXE2_CHANNEL_TXDATA38", + "GTXE2_CHANNEL_RXDFEUTOVRDEN", + "GTXE2_FAN1_0", + "GTXE2_CHANNEL_RXDATA51", + "GTXE2_CLK0_9", + "GTXE2_CHANNEL_TXPD0", + "GTXE2_CHANNEL_GTRSVD4", + "GTXE2_IMUX2_10", + "GTXE2_IMUX47_6", + "GTXE2_CHANNEL_TXPD1", + "GTXE2_IMUX35_0", + "GTXE2_CHANNEL_TXDLYHOLD", + "GTXE2_CHANNEL_TXPMARESET", + "GTXE2_IMUX28_10", + "GTXE2_LOGIC_OUTS_B22_5", + "GTXE2_LOGIC_OUTS_B17_2", + "GTXE2_LOGIC_OUTS_B19_9", + "GTXE2_IMUX14_2", + "GTXE2_CHANNEL_TXDATA60", + "GTXE2_IMUX38_0", + "GTXE2_BYP6_9", + "GTXE2_CHANNEL_QPLLREFCLK", + "GTXE2_LOGIC_OUTS_B21_10", + "GTXE2_IMUX24_3", + "GTXE2_CHANNEL_DRPDI0", + "GTXE2_LOGIC_OUTS_B9_10", + "GTXE2_CHANNEL_TSTIN15", + "GTXE2_CHANNEL_RXPHSLIPMONITOR1", + "GTXE2_CHANNEL_RXDFETAP4HOLD", + "GTXE2_BYP3_7", + "GTXE2_CHANNEL_TXSEQUENCE3", + "GTXE2_BYP6_4", + "GTXE2_IMUX18_3", + "GTXE2_IMUX45_7", + "GTXE2_CHANNEL_TSTIN14", + "GTXE2_IMUX8_0", + "GTXE2_CHANNEL_RXHEADER1", + "GTXE2_CHANNEL_TXCHARISK5", + "GTXE2_IMUX37_1", + "GTXE2_CHANNEL_RXBYTEREALIGN", + "GTXE2_IMUX5_0", + "GTXE2_CHANNEL_DMONITOROUT0", + "GTXE2_CHANNEL_DRPEN", + "GTXE2_CHANNEL_TXUSRCLK", + "GTXE2_FAN3_4", + "GTXE2_IMUX19_8", + "GTXE2_CHANNEL_PCSRSVDIN10", + "GTXE2_IMUX1_9", + "GTXE2_LOGIC_OUTS_B17_8", + "GTXE2_CHANNEL_RXPHMONITOR4", + "GTXE2_FAN6_7", + "GTXE2_IMUX8_9", + "GTXE2_IMUX2_6", + "GTXE2_CHANNEL_PCSRSVDOUT6", + "GTXE2_IMUX7_9", + "GTXE2_IMUX19_1", + "GTXE2_CHANNEL_PCSRSVDIN4", + "GTXE2_IMUX21_7", + "GTXE2_LOGIC_OUTS_B18_8", + "GTXE2_IMUX7_5", + "GTXE2_IMUX41_1", + "GTXE2_CHANNEL_TXDATA5", + "GTXE2_IMUX9_9", + "GTXE2_CLK1_2", + "GTXE2_LOGIC_OUTS_B6_8", + "GTXE2_BYP6_7", + "GTXE2_CTRL1_8", + "GTXE2_IMUX17_7", + "GTXE2_IMUX46_7", + "GTXE2_CHANNEL_TSTIN3", + "GTXE2_CHANNEL_RXCHBONDLEVEL2", + "GTXE2_CTRL0_1", + "GTXE2_CHANNEL_TXMAINCURSOR4", + "GTXE2_CHANNEL_PCSRSVDIN2", + "GTXE2_IMUX26_4", + "GTXE2_CHANNEL_RXMONITOROUT1", + "GTXE2_CHANNEL_RXCHARISK3", + "GTXE2_IMUX15_8", + "GTXE2_CHANNEL_TSTIN13", + "GTXE2_CHANNEL_PCSRSVDIN1", + "GTXE2_CHANNEL_GTNORTHREFCLK1", + "GTXE2_BYP0_6", + "GTXE2_CHANNEL_RXDATA36", + "GTXE2_CHANNEL_RXQPISENP", + "GTXE2_CHANNEL_RXDATA31", + "GTXE2_LOGIC_OUTS_B0_8", + "GTXE2_LOGIC_OUTS_B0_7", + "GTXE2_IMUX24_6", + "GTXE2_LOGIC_OUTS_B22_9", + "GTXE2_CHANNEL_RXDATA46", + "GTXE2_IMUX33_6", + "GTXE2_LOGIC_OUTS_B21_0", + "GTXE2_IMUX19_0", + "GTXE2_CLK1_3", + "GTXE2_LOGIC_OUTS_B14_2", + "GTXE2_IMUX37_4", + "GTXE2_BYP5_1", + "GTXE2_IMUX6_8", + "GTXE2_IMUX16_2", + "GTXE2_CHANNEL_RXDATA2", + "GTXE2_IMUX31_2", + "GTXE2_FAN4_2", + "GTXE2_LOGIC_OUTS_B18_0", + "GTXE2_CHANNEL_SCANIN4", + "GTXE2_LOGIC_OUTS_B15_10", + "GTXE2_LOGIC_OUTS_B13_3", + "GTXE2_LOGIC_OUTS_B5_7", + "GTXE2_LOGIC_OUTS_B6_9", + "GTXE2_CHANNEL_TXCHARDISPMODE1", + "GTXE2_CHANNEL_RXPCD1DONE", + "GTXE2_IMUX21_2", + "GTXE2_LOGIC_OUTS_B23_3", + "GTXE2_IMUX39_10", + "GTXE2_CHANNEL_TXQPIBIASEN", + "GTXE2_LOGIC_OUTS_B9_2", + "GTXE2_LOGIC_OUTS_B0_2", + "GTXE2_CHANNEL_RXUSERRDY", + "GTXE2_CHANNEL_DRPDO3", + "GTXE2_CHANNEL_EYESCANRESET", + "GTXE2_BYP7_1", + "GTXE2_LOGIC_OUTS_B12_6", + "GTXE2_CLK0_7", + "GTXE2_FAN0_7", + "GTXE2_CHANNEL_RXPHALIGNEN", + "GTXE2_IMUX24_5", + "GTXE2_CHANNEL_TXMARGIN1", + "GTXE2_CHANNEL_TXCHARDISPVAL0", + "GTXE2_IMUX8_5", + "GTXE2_IMUX14_8", + "GTXE2_CHANNEL_RXDATA0", + "GTXE2_FAN1_7", + "GTXE2_CHANNEL_RXPOLARITY", + "GTXE2_IMUX0_1", + "GTXE2_IMUX16_7", + "GTXE2_CHANNEL_TXSEQUENCE2", + "GTXE2_IMUX47_7", + "GTXE2_CHANNEL_RXPCOMMAALIGNEN", + "GTXE2_IMUX42_1", + "GTXE2_LOGIC_OUTS_B18_10", + "GTXE2_CHANNEL_GTRSVD1", + "GTXE2_LOGIC_OUTS_B7_0", + "GTXE2_CLK0_4", + "GTXE2_CHANNEL_TX8B10BBYPASS0", + "GTXE2_LOGIC_OUTS_B18_4", + "GTXE2_LOGIC_OUTS_B23_4", + "GTXE2_CHANNEL_PCSRSVDIN8", + "GTXE2_IMUX0_9", + "GTXE2_LOGIC_OUTS_B1_8", + "GTXE2_BYP1_8", + "GTXE2_LOGIC_OUTS_B7_5", + "GTXE2_CHANNEL_TXPCSRESET", + "GTXE2_CHANNEL_TXOUTCLKSEL2", + "GTXE2_CHANNEL_TXCHARDISPVAL7", + "GTXE2_CHANNEL_RXDATA3", + "GTXE2_IMUX47_5", + "GTXE2_CHANNEL_TXMAINCURSOR6", + "GTXE2_CHANNEL_RXPHSLIPMONITOR3", + "GTXE2_LOGIC_OUTS_B9_4", + "GTXE2_IMUX7_3", + "GTXE2_CHANNEL_PMASCANIN1", + "GTXE2_IMUX36_9", + "GTXE2_CHANNEL_TSTOUT2", + "GTXE2_IMUX27_3", + "GTXE2_LOGIC_OUTS_B19_4", + "GTXE2_IMUX27_0", + "GTXE2_CHANNEL_RXCLKCORCNT1", + "GTXE2_CHANNEL_TXDATA46", + "GTXE2_CHANNEL_RXDFEXYDHOLD", + "GTXE2_LOGIC_OUTS_B22_0", + "GTXE2_BYP2_5", + "GTXE2_CHANNEL_EDTBYPASS", + "GTXE2_CHANNEL_RXDATA40", + "GTXE2_IMUX42_6", + "GTXE2_CHANNEL_TXCHARDISPVAL6", + "GTXE2_LOGIC_OUTS_B16_9", + "GTXE2_LOGIC_OUTS_B11_8", + "GTXE2_LOGIC_OUTS_B14_0", + "GTXE2_CTRL1_3", + "GTXE2_CHANNEL_RXDATA23", + "GTXE2_IMUX32_7", + "GTXE2_CHANNEL_PMASCANIN4", + "GTXE2_IMUX31_8", + "GTXE2_LOGIC_OUTS_B4_6", + "GTXE2_CHANNEL_RXN_PAD", + "GTXE2_BYP2_9", + "GTXE2_IMUX18_5", + "GTXE2_CHANNEL_TXELECIDLE", + "GTXE2_LOGIC_OUTS_B13_8", + "GTXE2_IMUX46_6", + "GTXE2_CHANNEL_RXCHANISALIGNED", + "GTXE2_IMUX32_5", + "GTXE2_IMUX38_6", + "GTXE2_IMUX30_4", + "GTXE2_LOGIC_OUTS_B17_5", + "GTXE2_CLK0_3", + "GTXE2_IMUX25_2", + "GTXE2_IMUX9_3", + "GTXE2_IMUX32_1", + "GTXE2_CHANNEL_TXDIFFCTRL3", + "GTXE2_IMUX31_0", + "GTXE2_CHANNEL_RXDISPERR4", + "GTXE2_IMUX17_9", + "GTXE2_CHANNEL_SCANOUT2", + "GTXE2_FAN0_9", + "GTXE2_CHANNEL_TXPOSTCURSOR3", + "GTXE2_CHANNEL_TXOUTCLKSEL1", + "GTXE2_LOGIC_OUTS_B1_10", + "GTXE2_IMUX28_1", + "GTXE2_CHANNEL_RXPCSRESET", + "GTXE2_CHANNEL_TXHEADER2", + "GTXE2_IMUX7_10", + "GTXE2_CHANNEL_TXPOSTCURSOR2", + "GTXE2_IMUX20_6", + "GTXE2_BYP7_8", + "GTXE2_FAN5_0", + "GTXE2_CHANNEL_SCANIN1", + "GTXE2_CHANNEL_PMASCANMODEB", + "GTXE2_CHANNEL_GTTXOUTCLK_1", + "GTXE2_IMUX40_4", + "GTXE2_LOGIC_OUTS_B10_5", + "GTXE2_CHANNEL_TXPISOPD", + "GTXE2_LOGIC_OUTS_B23_1", + "GTXE2_CHANNEL_QPLLCLK", + "GTXE2_IMUX8_10", + "GTXE2_CHANNEL_RXDLYSRESET", + "GTXE2_IMUX16_5", + "GTXE2_IMUX9_6", + "GTXE2_CHANNEL_TXN", + "GTXE2_LOGIC_OUTS_B1_5", + "GTXE2_BYP2_4", + "GTXE2_CHANNEL_PCSRSVDOUT3", + "GTXE2_BYP4_5", + "GTXE2_CLK1_0", + "GTXE2_IMUX44_6", + "GTXE2_IMUX43_8", + "GTXE2_IMUX14_0", + "GTXE2_BYP7_0", + "GTXE2_CHANNEL_REFCLK0", + "GTXE2_CHANNEL_RXPMARESET", + "GTXE2_CHANNEL_RXCHANBONDSEQ", + "GTXE2_CHANNEL_TXCOMFINISH", + "GTXE2_IMUX7_6", + "GTXE2_CHANNEL_TXBUFDIFFCTRL1", + "GTXE2_IMUX17_0", + "GTXE2_CHANNEL_EYESCANDATAERROR", + "GTXE2_IMUX11_1", + "GTXE2_CHANNEL_TXDATA11", + "GTXE2_LOGIC_OUTS_B1_3", + "GTXE2_CHANNEL_RXCHBONDI0", + "GTXE2_CHANNEL_RXCHBONDLEVEL0", + "GTXE2_CHANNEL_RXDATA1", + "GTXE2_LOGIC_OUTS_B4_10", + "GTXE2_IMUX34_3", + "GTXE2_IMUX14_9", + "GTXE2_CHANNEL_RXCHARISCOMMA0", + "GTXE2_FAN4_6", + "GTXE2_IMUX14_4", + "GTXE2_CHANNEL_TSTOUT5", + "GTXE2_LOGIC_OUTS_B15_7", + "GTXE2_CHANNEL_PCSRSVDOUT9", + "GTXE2_IMUX13_7", + "GTXE2_FAN4_4", + "GTXE2_LOGIC_OUTS_B2_8", + "GTXE2_CHANNEL_TXPHALIGNEN", + "GTXE2_IMUX37_0", + "GTXE2_CHANNEL_TXOUTCLK_3", + "GTXE2_CHANNEL_GTRSVD6", + "GTXE2_CHANNEL_RXMONITORSEL1", + "GTXE2_CHANNEL_TXCHARDISPVAL4", + "GTXE2_CHANNEL_RXDATA16", + "GTXE2_IMUX40_7", + "GTXE2_CHANNEL_PCSRSVDIN12", + "GTXE2_IMUX38_9", + "GTXE2_CHANNEL_PMARSVDIN4", + "GTXE2_IMUX28_0", + "GTXE2_BYP4_8", + "GTXE2_CHANNEL_TXBUFSTATUS0", + "GTXE2_CHANNEL_RXCHBONDLEVEL1", + "GTXE2_IMUX19_2", + "GTXE2_LOGIC_OUTS_B7_8", + "GTXE2_CHANNEL_TXMARGIN2", + "GTXE2_IMUX41_6", + "GTXE2_CHANNEL_DRPDO5", + "GTXE2_CHANNEL_RXDATA55", + "GTXE2_IMUX23_8", + "GTXE2_BYP1_5", + "GTXE2_CHANNEL_RXSYSCLKSEL1", + "GTXE2_LOGIC_OUTS_B16_7", + "GTXE2_CHANNEL_RXCHBONDI2", + "GTXE2_CHANNEL_TXSEQUENCE1", + "GTXE2_CHANNEL_SOUTHREFCLK0", + "GTXE2_IMUX16_3", + "GTXE2_IMUX28_6", + "GTXE2_IMUX35_4", + "GTXE2_LOGIC_OUTS_B16_1", + "GTXE2_CHANNEL_RXDATA57", + "GTXE2_CHANNEL_TXDATA18", + "GTXE2_LOGIC_OUTS_B14_3", + "GTXE2_IMUX27_7", + "GTXE2_CHANNEL_DMONITOROUT1", + "GTXE2_IMUX39_7", + "GTXE2_LOGIC_OUTS_B17_1", + "GTXE2_IMUX27_10", + "GTXE2_CHANNEL_RXCHARISCOMMA1", + "GTXE2_CHANNEL_RXLPMHFHOLD", + "GTXE2_IMUX27_6", + "GTXE2_IMUX6_5", + "GTXE2_BYP5_2", + "GTXE2_CHANNEL_SETERRSTATUS", + "GTXE2_CHANNEL_TXCHARDISPVAL1", + "GTXE2_LOGIC_OUTS_B12_9", + "GTXE2_CHANNEL_PCSRSVDIN9", + "GTXE2_IMUX46_4", + "GTXE2_CHANNEL_PMASCANIN3", + "GTXE2_IMUX20_8", + "GTXE2_CHANNEL_CPLLLOCKEN", + "GTXE2_CHANNEL_DRPADDR6", + "GTXE2_IMUX45_4", + "GTXE2_LOGIC_OUTS_B1_1", + "GTXE2_IMUX42_3", + "GTXE2_BYP1_3", + "GTXE2_CTRL1_0", + "GTXE2_CHANNEL_TXRUNDISP0", + "GTXE2_IMUX42_9", + "GTXE2_CHANNEL_RXDFETAP5OVRDEN", + "GTXE2_IMUX47_2", + "GTXE2_IMUX0_3", + "GTXE2_CTRL0_5", + "GTXE2_CHANNEL_PCSRSVDIN20", + "GTXE2_BYP3_9", + "GTXE2_CHANNEL_TSTCLK1", + "GTXE2_BYP2_1", + "GTXE2_CHANNEL_RXCHARISK1", + "GTXE2_IMUX33_7", + "GTXE2_IMUX12_8", + "GTXE2_IMUX35_2", + "GTXE2_IMUX10_5", + "GTXE2_IMUX34_8", + "GTXE2_CHANNEL_TSTPD1", + "GTXE2_IMUX2_9", + "GTXE2_CHANNEL_TXDATA2", + "GTXE2_IMUX21_1", + "GTXE2_LOGIC_OUTS_B22_7", + "GTXE2_CHANNEL_TXOUTCLK_1", + "GTXE2_FAN1_10", + "GTXE2_IMUX32_3", + "GTXE2_LOGIC_OUTS_B13_10", + "GTXE2_LOGIC_OUTS_B7_6", + "GTXE2_FAN7_3", + "GTXE2_CHANNEL_TXOUTCLKPCS", + "GTXE2_IMUX4_6", + "GTXE2_CHANNEL_TSTOUT3", + "GTXE2_CHANNEL_RXNOTINTABLE7", + "GTXE2_LOGIC_OUTS_B12_8", + "GTXE2_CHANNEL_RXDATA61", + "GTXE2_CHANNEL_RXDATA56", + "GTXE2_FAN3_2", + "GTXE2_LOGIC_OUTS_B8_5", + "GTXE2_CLK0_5", + "GTXE2_FAN2_10", + "GTXE2_IMUX41_8", + "GTXE2_BYP5_9", + "GTXE2_CHANNEL_DRPDI5", + "GTXE2_CHANNEL_TXSEQUENCE0", + "GTXE2_IMUX26_10", + "GTXE2_CHANNEL_RXSTARTOFSEQ", + "GTXE2_BYP1_0", + "GTXE2_IMUX47_1", + "GTXE2_CHANNEL_PMARSVDIN21", + "GTXE2_IMUX18_10", + "GTXE2_CHANNEL_TXPOSTCURSOR4", + "GTXE2_LOGIC_OUTS_B15_3", + "GTXE2_CHANNEL_RXCOMMADETEN", + "GTXE2_FAN0_1", + "GTXE2_CHANNEL_GTRSVD7", + "GTXE2_CLK1_8", + "GTXE2_CHANNEL_TXDIFFCTRL0", + "GTXE2_IMUX22_2", + "GTXE2_LOGIC_OUTS_B4_5", + "GTXE2_CHANNEL_TXBUFSTATUS1", + "GTXE2_IMUX6_10", + "GTXE2_CHANNEL_SCANIN3", + "GTXE2_FAN0_0", + "GTXE2_LOGIC_OUTS_B22_6", + "GTXE2_LOGIC_OUTS_B13_4", + "GTXE2_CHANNEL_RXDATA12", + "GTXE2_LOGIC_OUTS_B7_3", + "GTXE2_IMUX41_5", + "GTXE2_CHANNEL_RXOUTCLK_0", + "GTXE2_IMUX20_9", + "GTXE2_IMUX27_8", + "GTXE2_CHANNEL_RXDFELFHOLD", + "GTXE2_CHANNEL_PCSRSVDIN14", + "GTXE2_FAN1_6", + "GTXE2_IMUX34_4", + "GTXE2_CHANNEL_RXDISPERR2", + "GTXE2_CHANNEL_TXRUNDISP3", + "GTXE2_CHANNEL_CPLLRESET", + "GTXE2_BYP5_6", + "GTXE2_LOGIC_OUTS_B6_1", + "GTXE2_IMUX12_4", + "GTXE2_FAN2_2", + "GTXE2_CHANNEL_RXDATA47", + "GTXE2_CHANNEL_DRPDO9", + "GTXE2_LOGIC_OUTS_B14_6", + "GTXE2_CHANNEL_DRPDO1", + "GTXE2_CHANNEL_TXPRBSFORCEERR", + "GTXE2_LOGIC_OUTS_B16_4", + "GTXE2_IMUX16_8", + "GTXE2_LOGIC_OUTS_B14_7", + "GTXE2_LOGIC_OUTS_B23_8", + "GTXE2_FAN6_4", + "GTXE2_LOGIC_OUTS_B0_3", + "GTXE2_IMUX29_5", + "GTXE2_CHANNEL_RXCDRLOCK", + "GTXE2_CHANNEL_GTNORTHREFCLK0", + "GTXE2_IMUX31_1", + "GTXE2_IMUX20_5", + "GTXE2_CHANNEL_LOOPBACK2", + "GTXE2_CHANNEL_RXPRBSERR", + "GTXE2_IMUX7_0", + "GTXE2_BYP0_2", + "GTXE2_CHANNEL_RXGEARBOXSLIP", + "GTXE2_LOGIC_OUTS_B8_9", + "GTXE2_CHANNEL_PMASCANOUT3", + "GTXE2_CHANNEL_TSTIN1", + "GTXE2_LOGIC_OUTS_B21_9", + "GTXE2_FAN4_1", + "GTXE2_LOGIC_OUTS_B6_10", + "GTXE2_IMUX35_6", + "GTXE2_IMUX24_9", + "GTXE2_CHANNEL_TSTIN18", + "GTXE2_CHANNEL_RXDISPERR5", + "GTXE2_FAN6_10", + "GTXE2_IMUX32_0", + "GTXE2_CHANNEL_CLKRSVD1", + "GTXE2_CTRL1_6", + "GTXE2_CHANNEL_TSTOUT7", + "GTXE2_LOGIC_OUTS_B9_8", + "GTXE2_IMUX38_7", + "GTXE2_IMUX5_2", + "GTXE2_CLK0_2", + "GTXE2_CHANNEL_DRPDI11", + "GTXE2_CHANNEL_RXPHALIGN", + "GTXE2_LOGIC_OUTS_B0_0", + "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", + "GTXE2_CHANNEL_TXDATA58", + "GTXE2_LOGIC_OUTS_B3_4", + "GTXE2_CHANNEL_RXUSRCLK2", + "GTXE2_CHANNEL_TXDATA50", + "GTXE2_CHANNEL_RXDATA24", + "GTXE2_CHANNEL_PCSRSVDIN0", + "GTXE2_CHANNEL_RXCHBONDO0", + "GTXE2_LOGIC_OUTS_B22_4", + "GTXE2_IMUX13_1", + "GTXE2_CHANNEL_TXCHARDISPMODE3", + "GTXE2_CHANNEL_RXRATE0", + "GTXE2_CHANNEL_RXDATA27", + "GTXE2_IMUX28_2", + "GTXE2_IMUX14_7", + "GTXE2_LOGIC_OUTS_B20_2", + "GTXE2_IMUX44_5", + "GTXE2_BYP4_9", + "GTXE2_IMUX36_1", + "GTXE2_BYP2_7", + "GTXE2_CHANNEL_TXDATA12", + "GTXE2_CHANNEL_EDTUPDATE", + "GTXE2_IMUX26_3", + "GTXE2_CHANNEL_RXDISPERR6", + "GTXE2_FAN3_3", + "GTXE2_CHANNEL_TXPHALIGN", + "GTXE2_CHANNEL_TXDIFFCTRL1", + "GTXE2_LOGIC_OUTS_B4_0", + "GTXE2_IMUX9_10", + "GTXE2_CHANNEL_TXDATA26", + "GTXE2_CHANNEL_TXP_PAD", + "GTXE2_CHANNEL_RXOUTCLK_1", + "GTXE2_IMUX12_7", + "GTXE2_IMUX33_5", + "GTXE2_IMUX47_3", + "GTXE2_LOGIC_OUTS_B14_8", + "GTXE2_CHANNEL_RXDEBUGPULSE", + "GTXE2_CHANNEL_RXDATA4", + "GTXE2_LOGIC_OUTS_B12_7", + "GTXE2_IMUX20_2", + "GTXE2_CHANNEL_RXNOTINTABLE4", + "GTXE2_CHANNEL_RXDFEUTHOLD", + "GTXE2_CHANNEL_GTREFCLK0", + "GTXE2_IMUX37_9", + "GTXE2_CHANNEL_RXBUFSTATUS1", + "GTXE2_IMUX4_7", + "GTXE2_BYP1_9", + "GTXE2_CHANNEL_DRPDO12", + "GTXE2_IMUX31_6", + "GTXE2_CHANNEL_RXMONITOROUT5", + "GTXE2_FAN5_6", + "GTXE2_CHANNEL_TXDATA7", + "GTXE2_CHANNEL_TSTOUT9", + "GTXE2_CHANNEL_RXNOTINTABLE3", + "GTXE2_CHANNEL_EYESCANTRIGGER", + "GTXE2_IMUX10_7", + "GTXE2_CHANNEL_GTSOUTHREFCLK0", + "GTXE2_LOGIC_OUTS_B19_8", + "GTXE2_LOGIC_OUTS_B7_10", + "GTXE2_CHANNEL_RXCDRRESETRSV", + "GTXE2_CHANNEL_RXSLIDE", + "GTXE2_CHANNEL_TXPRBSSEL2", + "GTXE2_IMUX43_10", + "GTXE2_CHANNEL_RXCHBONDI1", + "GTXE2_BYP3_1", + "GTXE2_CHANNEL_RXP", + "GTXE2_IMUX13_6", + "GTXE2_LOGIC_OUTS_B5_2", + "GTXE2_LOGIC_OUTS_B9_6", + "GTXE2_IMUX35_8", + "GTXE2_CHANNEL_TXRATE2", + "GTXE2_CHANNEL_CPLLLOCKDETCLK", + "GTXE2_IMUX36_5", + "GTXE2_CHANNEL_RXLPMEN", + "GTXE2_CHANNEL_RXCDROVRDEN", + "GTXE2_BYP6_3", + "GTXE2_BYP3_4", + "GTXE2_LOGIC_OUTS_B21_6", + "GTXE2_LOGIC_OUTS_B12_10", + "GTXE2_IMUX43_3", + "GTXE2_FAN4_10", + "GTXE2_IMUX24_2", + "GTXE2_IMUX46_10", + "GTXE2_LOGIC_OUTS_B5_5", + "GTXE2_CHANNEL_TXOUTCLKFABRIC", + "GTXE2_CHANNEL_TSTIN10", + "GTXE2_IMUX36_6", + "GTXE2_BYP4_10", + "GTXE2_CHANNEL_RXDFEXYDOVRDEN", + "GTXE2_IMUX34_0", + "GTXE2_CLK0_1", + "GTXE2_IMUX11_10", + "GTXE2_LOGIC_OUTS_B10_4", + "GTXE2_LOGIC_OUTS_B20_1", + "GTXE2_CHANNEL_TXMAINCURSOR2", + "GTXE2_CHANNEL_RXPD1", + "GTXE2_IMUX32_10", + "GTXE2_LOGIC_OUTS_B7_2", + "GTXE2_LOGIC_OUTS_B0_1", + "GTXE2_CHANNEL_RXDATA18", + "GTXE2_IMUX21_9", + "GTXE2_IMUX3_0", + "GTXE2_CTRL0_6", + "GTXE2_CHANNEL_RXCDRFREQRESET", + "GTXE2_IMUX45_2", + "GTXE2_LOGIC_OUTS_B13_2", + "GTXE2_CHANNEL_RXDISPERR1", + "GTXE2_CTRL0_0", + "GTXE2_FAN6_8", + "GTXE2_IMUX30_0", + "GTXE2_IMUX43_6", + "GTXE2_BYP1_6", + "GTXE2_IMUX28_3", + "GTXE2_IMUX18_0", + "GTXE2_LOGIC_OUTS_B10_7", + "GTXE2_CHANNEL_PCSRSVDOUT8", + "GTXE2_FAN6_5", + "GTXE2_CLK0_0", + "GTXE2_LOGIC_OUTS_B9_3", + "GTXE2_CHANNEL_TXDATA55", + "GTXE2_LOGIC_OUTS_B20_3", + "GTXE2_CHANNEL_PMASCANIN0", + "GTXE2_IMUX29_10", + "GTXE2_CHANNEL_DRPDI2", + "GTXE2_LOGIC_OUTS_B20_4", + "GTXE2_CHANNEL_RXDFECM1EN", + "GTXE2_CHANNEL_RXCHARISCOMMA3", + "GTXE2_CHANNEL_RXCHARISCOMMA5", + "GTXE2_CHANNEL_PMASCANENB", + "GTXE2_IMUX11_6", + "GTXE2_BYP3_2", + "GTXE2_CHANNEL_RXCHARISCOMMA7", + "GTXE2_CHANNEL_TXPHINIT", + "GTXE2_IMUX25_1", + "GTXE2_BYP7_4", + "GTXE2_CHANNEL_RXOUTCLKSEL0", + "GTXE2_IMUX1_1", + "GTXE2_CHANNEL_TXDATA51", + "GTXE2_IMUX35_3", + "GTXE2_LOGIC_OUTS_B22_10", + "GTXE2_FAN5_7", + "GTXE2_CHANNEL_RXDFETAP3OVRDEN", + "GTXE2_CHANNEL_PMARSVDIN20", + "GTXE2_CHANNEL_RXPHMONITOR2", + "GTXE2_CHANNEL_RXDATA25", + "GTXE2_CHANNEL_RXDATA9", + "GTXE2_CHANNEL_TSTOUT0", + "GTXE2_CHANNEL_TXPRECURSOR4", + "GTXE2_IMUX5_5", + "GTXE2_IMUX22_5", + "GTXE2_IMUX30_10", + "GTXE2_LOGIC_OUTS_B19_3", + "GTXE2_FAN1_3", + "GTXE2_CHANNEL_RXCDRHOLD", + "GTXE2_LOGIC_OUTS_B10_6", + "GTXE2_LOGIC_OUTS_B16_5", + "GTXE2_FAN1_2", + "GTXE2_IMUX45_1", + "GTXE2_IMUX19_7", + "GTXE2_CHANNEL_RXDATA43", + "GTXE2_CHANNEL_TXUSRCLK2", + "GTXE2_IMUX26_6", + "GTXE2_IMUX3_6", + "GTXE2_CHANNEL_TXCHARISK4", + "GTXE2_LOGIC_OUTS_B11_2", + "GTXE2_CHANNEL_TSTPD3", + "GTXE2_IMUX38_3", + "GTXE2_LOGIC_OUTS_B12_3", + "GTXE2_IMUX45_10", + "GTXE2_FAN7_5", + "GTXE2_IMUX38_5", + "GTXE2_BYP5_4", + "GTXE2_CHANNEL_PCSRSVDIN3", + "GTXE2_LOGIC_OUTS_B4_9", + "GTXE2_LOGIC_OUTS_B2_5", + "GTXE2_IMUX26_2", + "GTXE2_CHANNEL_SCANOUT4", + "GTXE2_CHANNEL_CFGRESET", + "GTXE2_IMUX33_3", + "GTXE2_CHANNEL_RXDATA20", + "GTXE2_IMUX38_10", + "GTXE2_CHANNEL_TSTOUT1", + "GTXE2_IMUX1_8", + "GTXE2_CHANNEL_TXDATA20", + "GTXE2_CHANNEL_TSTPD0", + "GTXE2_CHANNEL_TXDATA37", + "GTXE2_IMUX23_1", + "GTXE2_IMUX36_0", + "GTXE2_LOGIC_OUTS_B16_10", + "GTXE2_IMUX4_2", + "GTXE2_IMUX18_1", + "GTXE2_LOGIC_OUTS_B12_0", + "GTXE2_CHANNEL_RXDATA30", + "GTXE2_IMUX44_10", + "GTXE2_IMUX25_6", + "GTXE2_CHANNEL_PMASCANOUT4", + "GTXE2_LOGIC_OUTS_B17_10", + "GTXE2_CHANNEL_TXINHIBIT", + "GTXE2_IMUX3_5", + "GTXE2_CHANNEL_TXDATA39", + "GTXE2_IMUX15_10", + "GTXE2_CHANNEL_TXPDELECIDLEMODE", + "GTXE2_IMUX26_8", + "GTXE2_CHANNEL_GTTXRESET", + "GTXE2_CHANNEL_TXCHARISK2", + "GTXE2_IMUX6_3", + "GTXE2_CHANNEL_RXPRBSSEL1", + "GTXE2_CHANNEL_RXPHSLIPMONITOR0", + "GTXE2_CLK0_10", + "GTXE2_CHANNEL_RXDFELPMRESET", + "GTXE2_IMUX42_10", + "GTXE2_IMUX2_1", + "GTXE2_LOGIC_OUTS_B16_2", + "GTXE2_CHANNEL_TXCOMSAS", + "GTXE2_IMUX6_7", + "GTXE2_IMUX29_6", + "GTXE2_IMUX31_4", + "GTXE2_CHANNEL_RXLPMLFHOLD", + "GTXE2_CHANNEL_PCSRSVDOUT4", + "GTXE2_CHANNEL_RXDATA59", + "GTXE2_CHANNEL_DRPADDR1", + "GTXE2_LOGIC_OUTS_B20_7", + "GTXE2_FAN2_1", + "GTXE2_FAN7_7", + "GTXE2_IMUX12_6", + "GTXE2_CHANNEL_TXDATA21", + "GTXE2_IMUX29_2", + "GTXE2_CHANNEL_RXDATA45", + "GTXE2_CHANNEL_TX8B10BBYPASS1", + "GTXE2_CHANNEL_SCANMODEB", + "GTXE2_IMUX36_7", + "GTXE2_IMUX17_3", + "GTXE2_CHANNEL_TXHEADER0", + "GTXE2_LOGIC_OUTS_B13_7", + "GTXE2_IMUX29_0", + "GTXE2_LOGIC_OUTS_B3_5", + "GTXE2_CHANNEL_TXCHARDISPMODE7", + "GTXE2_CHANNEL_GTRSVD12", + "GTXE2_LOGIC_OUTS_B1_7", + "GTXE2_CHANNEL_SCANOUT0", + "GTXE2_IMUX24_7", + "GTXE2_IMUX15_7", + "GTXE2_CHANNEL_RXDFEXYDEN", + "GTXE2_IMUX1_7", + "GTXE2_IMUX23_3", + "GTXE2_CHANNEL_TX8B10BBYPASS3", + "GTXE2_IMUX34_1", + "GTXE2_CHANNEL_RXCHARISCOMMA6", + "GTXE2_CHANNEL_TXOUTCLK_2", + "GTXE2_CHANNEL_TXDATA56", + "GTXE2_LOGIC_OUTS_B5_10", + "GTXE2_IMUX25_0", + "GTXE2_CHANNEL_PCSRSVDIN11", + "GTXE2_CHANNEL_TXRESETDONE", + "GTXE2_CHANNEL_TSTOUT4", + "GTXE2_IMUX43_9", + "GTXE2_CHANNEL_TSTOUT8", + "GTXE2_LOGIC_OUTS_B1_2", + "GTXE2_BYP7_6", + "GTXE2_FAN2_4", + "GTXE2_IMUX18_8", + "GTXE2_IMUX39_0", + "GTXE2_CHANNEL_RXDFETAP2HOLD", + "GTXE2_BYP6_6", + "GTXE2_CHANNEL_TXPHALIGNDONE", + "GTXE2_LOGIC_OUTS_B2_6", + "GTXE2_IMUX37_5", + "GTXE2_LOGIC_OUTS_B8_1", + "GTXE2_CHANNEL_TXDATA35", + "GTXE2_CHANNEL_TXPRECURSORINV", + "GTXE2_IMUX10_9", + "GTXE2_IMUX38_1", + "GTXE2_IMUX14_6", + "GTXE2_CHANNEL_PMARSVDIN2", + "GTXE2_IMUX18_6", + "GTXE2_FAN0_5", + "GTXE2_CHANNEL_RXCHBONDSLAVE", + "GTXE2_CHANNEL_DRPADDR2", + "GTXE2_CHANNEL_RXDATA29", + "GTXE2_CHANNEL_RXMONITOROUT6", + "GTXE2_CHANNEL_TXDATA54", + "GTXE2_BYP4_0", + "GTXE2_CHANNEL_PCSRSVDOUT10", + "GTXE2_LOGIC_OUTS_B14_10", + "GTXE2_CHANNEL_RXCHBONDI4", + "GTXE2_IMUX44_1", + "GTXE2_CHANNEL_TXDLYEN", + "GTXE2_LOGIC_OUTS_B17_4", + "GTXE2_LOGIC_OUTS_B10_0", + "GTXE2_FAN0_10", + "GTXE2_IMUX39_4", + "GTXE2_CHANNEL_TXMAINCURSOR5", + "GTXE2_IMUX7_7", + "GTXE2_CHANNEL_RXNOTINTABLE2", + "GTXE2_CHANNEL_DRPDI12", + "GTXE2_IMUX14_5", + "GTXE2_LOGIC_OUTS_B5_6", + "GTXE2_FAN2_7", + "GTXE2_CHANNEL_DRPDI7", + "GTXE2_CHANNEL_TXQPIWEAKPUP", + "GTXE2_CHANNEL_RXDISPERR0", + "GTXE2_BYP2_6", + "GTXE2_CHANNEL_RXPHOVRDEN", + "GTXE2_CHANNEL_TX8B10BBYPASS4", + "GTXE2_IMUX21_5", + "GTXE2_CHANNEL_EDTCONFIGURATION", + "GTXE2_CHANNEL_DRPDO0", + "GTXE2_IMUX24_10", + "GTXE2_IMUX43_4", + "GTXE2_LOGIC_OUTS_B13_6", + "GTXE2_FAN1_4", + "GTXE2_CHANNEL_RXOUTCLK_3", + "GTXE2_IMUX0_4", + "GTXE2_LOGIC_OUTS_B8_0", + "GTXE2_CHANNEL_TXDATA33", + "GTXE2_CHANNEL_SCANCLK", + "GTXE2_CHANNEL_TX8B10BBYPASS7", + "GTXE2_IMUX25_7", + "GTXE2_BYP5_0", + "GTXE2_IMUX46_5", + "GTXE2_IMUX13_4", + "GTXE2_LOGIC_OUTS_B8_2", + "GTXE2_CHANNEL_GTRSVD2", + "GTXE2_CHANNEL_GTSOUTHREFCLK1", + "GTXE2_CHANNEL_CLKRSVD3", + "GTXE2_CHANNEL_GTQPLLCLK", + "GTXE2_CHANNEL_RXDLYSRESETDONE", + "GTXE2_CHANNEL_RXDATA48", + "GTXE2_CHANNEL_RXHEADER2", + "GTXE2_FAN7_4", + "GTXE2_IMUX30_7", + "GTXE2_CLK0_6", + "GTXE2_CHANNEL_RXDATA22", + "GTXE2_IMUX3_9", + "GTXE2_CHANNEL_PCSRSVDOUT2", + "GTXE2_IMUX34_10", + "GTXE2_CHANNEL_RXPHSLIPMONITOR2", + "GTXE2_CHANNEL_TXDATA27", + "GTXE2_CHANNEL_PMASCANCLK4", + "GTXE2_CHANNEL_TXGEARBOXREADY", + "GTXE2_IMUX44_7", + "GTXE2_CHANNEL_RXDATA53", + "GTXE2_LOGIC_OUTS_B17_6", + "GTXE2_CHANNEL_TSTIN17", + "GTXE2_CHANNEL_RXCHBONDO1", + "GTXE2_LOGIC_OUTS_B21_4", + "GTXE2_IMUX44_4", + "GTXE2_IMUX13_3", + "GTXE2_FAN7_8", + "GTXE2_CLK0_8", + "GTXE2_IMUX36_8", + "GTXE2_CHANNEL_TXSTARTSEQ", + "GTXE2_IMUX10_2", + "GTXE2_IMUX41_0", + "GTXE2_IMUX3_10", + "GTXE2_CHANNEL_TXSEQUENCE5", + "GTXE2_LOGIC_OUTS_B7_4", + "GTXE2_CHANNEL_TXMARGIN0", + "GTXE2_IMUX15_3", + "GTXE2_BYP7_3", + "GTXE2_CHANNEL_RXDATA41", + "GTXE2_CHANNEL_DRPDI1", + "GTXE2_LOGIC_OUTS_B2_0", + "GTXE2_CHANNEL_RXDATA13", + "GTXE2_LOGIC_OUTS_B15_0", + "GTXE2_CHANNEL_RXDFELFOVRDEN", + "GTXE2_IMUX37_10", + "GTXE2_CHANNEL_PMARSVDIN23", + "GTXE2_CHANNEL_RXDATA63", + "GTXE2_CHANNEL_RXDATA60", + "GTXE2_CHANNEL_EDTCLOCK", + "GTXE2_CHANNEL_RXDATA44", + "GTXE2_CHANNEL_RXCLKCORCNT0", + "GTXE2_FAN4_8", + "GTXE2_CHANNEL_DMONITOROUT7", + "GTXE2_IMUX23_9", + "GTXE2_IMUX2_0", + "GTXE2_IMUX38_4", + "GTXE2_CHANNEL_RXOSOVRDEN", + "GTXE2_IMUX28_5", + "GTXE2_IMUX9_0", + "GTXE2_CHANNEL_RXMONITOROUT0", + "GTXE2_CHANNEL_TXRATE0", + "GTXE2_CHANNEL_TX8B10BEN", + "GTXE2_IMUX42_0", + "GTXE2_IMUX38_8", + "GTXE2_IMUX5_6", + "GTXE2_IMUX7_8", + "GTXE2_CHANNEL_TXDIFFCTRL2", + "GTXE2_CHANNEL_GTRSVD3", + "GTXE2_CHANNEL_DRPDI15", + "GTXE2_IMUX2_8", + "GTXE2_IMUX18_9", + "GTXE2_LOGIC_OUTS_B10_10", + "GTXE2_CHANNEL_RXRATE1", + "GTXE2_LOGIC_OUTS_B8_8", + "GTXE2_CLK1_6", + "GTXE2_CHANNEL_RXMONITOROUT3", + "GTXE2_CHANNEL_TXOUTCLKSEL0", + "GTXE2_CHANNEL_TXSEQUENCE4", + "GTXE2_CHANNEL_TX8B10BBYPASS5", + "GTXE2_CHANNEL_DRPDO11", + "GTXE2_CTRL0_2", + "GTXE2_LOGIC_OUTS_B10_3", + "GTXE2_IMUX46_8", + "GTXE2_LOGIC_OUTS_B19_0", + "GTXE2_BYP0_4", + "GTXE2_CHANNEL_TXCHARDISPMODE4", + "GTXE2_IMUX29_7", + "GTXE2_IMUX26_1", + "GTXE2_CHANNEL_PHYSTATUS", + "GTXE2_LOGIC_OUTS_B23_7", + "GTXE2_CHANNEL_TXPRBSSEL1", + "GTXE2_IMUX0_7", + "GTXE2_IMUX41_4", + "GTXE2_CHANNEL_TXDATA23", + "GTXE2_CHANNEL_RXDATA14", + "GTXE2_CHANNEL_RXDATA26", + "GTXE2_IMUX0_6", + "GTXE2_IMUX33_0", + "GTXE2_LOGIC_OUTS_B15_2", + "GTXE2_LOGIC_OUTS_B3_9", + "GTXE2_CHANNEL_DRPDO14", + "GTXE2_CHANNEL_TXDETECTRX", + "GTXE2_CHANNEL_RXDATA6", + "GTXE2_CHANNEL_TXDATA17", + "GTXE2_IMUX0_0", + "GTXE2_IMUX47_9", + "GTXE2_IMUX3_8", + "GTXE2_IMUX8_1", + "GTXE2_IMUX28_9", + "GTXE2_IMUX13_10", + "GTXE2_CHANNEL_TXSYSCLKSEL0", + "GTXE2_LOGIC_OUTS_B4_8", + "GTXE2_LOGIC_OUTS_B2_2", + "GTXE2_CHANNEL_GTRXRESET", + "GTXE2_IMUX21_4", + "GTXE2_CHANNEL_RXPHALIGNDONE", + "GTXE2_CHANNEL_RXDATA38", + "GTXE2_LOGIC_OUTS_B15_6", + "GTXE2_CHANNEL_GTRSVD14", + "GTXE2_CHANNEL_TXCHARISK6", + "GTXE2_FAN7_9", + "GTXE2_CHANNEL_RXDATA8", + "GTXE2_CHANNEL_DRPDO2", + "GTXE2_CHANNEL_RXDATA33", + "GTXE2_CHANNEL_PMASCANOUT1", + "GTXE2_LOGIC_OUTS_B18_3", + "GTXE2_LOGIC_OUTS_B11_1", + "GTXE2_CHANNEL_SOUTHREFCLK1", + "GTXE2_CHANNEL_TXDLYUPDOWN", + "GTXE2_IMUX38_2", + "GTXE2_LOGIC_OUTS_B20_9", + "GTXE2_LOGIC_OUTS_B17_3", + "GTXE2_LOGIC_OUTS_B15_5", + "GTXE2_IMUX11_3", + "GTXE2_CHANNEL_TXRUNDISP6", + "GTXE2_CHANNEL_TXPRECURSOR1", + "GTXE2_IMUX16_0", + "GTXE2_LOGIC_OUTS_B18_9", + "GTXE2_BYP2_2", + "GTXE2_CHANNEL_RXOUTCLKPCS", + "GTXE2_IMUX29_1", + "GTXE2_FAN6_6", + "GTXE2_FAN0_4", + "GTXE2_IMUX17_6", + "GTXE2_CHANNEL_RXCHARISCOMMA2", + "GTXE2_CHANNEL_RXPHMONITOR3", + "GTXE2_LOGIC_OUTS_B5_0", + "GTXE2_IMUX10_3", + "GTXE2_BYP4_6", + "GTXE2_CHANNEL_PMARSVDIN0", + "GTXE2_IMUX19_3", + "GTXE2_IMUX13_5", + "GTXE2_IMUX15_2", + "GTXE2_LOGIC_OUTS_B2_7", + "GTXE2_CHANNEL_DRPADDR3", + "GTXE2_CHANNEL_RXELECIDLEMODE1", + "GTXE2_LOGIC_OUTS_B6_3", + "GTXE2_LOGIC_OUTS_B3_8", + "GTXE2_LOGIC_OUTS_B1_6", + "GTXE2_CHANNEL_RXDFEAGCOVRDEN", + "GTXE2_CHANNEL_RXDLYBYPASS", + "GTXE2_CHANNEL_CPLLREFCLKSEL2", + "GTXE2_CHANNEL_RXDATA49", + "GTXE2_IMUX41_3", + "GTXE2_LOGIC_OUTS_B3_7", + "GTXE2_IMUX34_9", + "GTXE2_CHANNEL_RXMONITOROUT2", + "GTXE2_LOGIC_OUTS_B2_3", + "GTXE2_BYP6_0", + "GTXE2_CHANNEL_CLKRSVD0", + "GTXE2_IMUX16_4", + "GTXE2_CHANNEL_TSTIN5", + "GTXE2_CHANNEL_RXNOTINTABLE0", + "GTXE2_LOGIC_OUTS_B22_1", + "GTXE2_IMUX7_4", + "GTXE2_IMUX37_3", + "GTXE2_IMUX12_3", + "GTXE2_CHANNEL_TSTIN16", + "GTXE2_CHANNEL_TXDATA52", + "GTXE2_IMUX20_10", + "GTXE2_CHANNEL_DRPADDR5", + "GTXE2_BYP3_5", + "GTXE2_LOGIC_OUTS_B6_5", + "GTXE2_CHANNEL_TXDATA49", + "GTXE2_CHANNEL_SCANIN2", + "GTXE2_CHANNEL_RXDFEAGCHOLD", + "GTXE2_CHANNEL_TXCHARDISPVAL2", + "GTXE2_IMUX8_6", + "GTXE2_CHANNEL_GTRXOUTCLK_1", + "GTXE2_CHANNEL_TXDATA4", + "GTXE2_CTRL0_10", + "GTXE2_IMUX23_2", + "GTXE2_IMUX34_6", + "GTXE2_LOGIC_OUTS_B4_3", + "GTXE2_CHANNEL_RX8B10BEN", + "GTXE2_CHANNEL_RXOUTCLK_2", + "GTXE2_BYP6_1", + "GTXE2_CTRL1_4", + "GTXE2_LOGIC_OUTS_B13_0", + "GTXE2_IMUX26_5", + "GTXE2_IMUX13_0", + "GTXE2_LOGIC_OUTS_B22_2", + "GTXE2_CHANNEL_RXCOMINITDET", + "GTXE2_CHANNEL_TXDLYTESTENB", + "GTXE2_IMUX25_5", + "GTXE2_IMUX45_6", + "GTXE2_LOGIC_OUTS_B14_9", + "GTXE2_CHANNEL_SCANOUT1", + "GTXE2_IMUX22_0", + "GTXE2_IMUX5_3", + "GTXE2_CHANNEL_RXSYSCLKSEL0", + "GTXE2_IMUX22_7", + "GTXE2_LOGIC_OUTS_B23_0", + "GTXE2_IMUX14_3", + "GTXE2_CHANNEL_TXDATA22", + "GTXE2_CHANNEL_RXPHDLYPD", + "GTXE2_IMUX18_2", + "GTXE2_CHANNEL_DRPDI4", + "GTXE2_CHANNEL_RXCHARISK7", + "GTXE2_IMUX24_0", + "GTXE2_CHANNEL_RXDATA37", + "GTXE2_IMUX11_2", + "GTXE2_CHANNEL_TXSYSCLKSEL1", + "GTXE2_CHANNEL_RXRATE2", + "GTXE2_IMUX17_8", + "GTXE2_CHANNEL_RXDATA5", + "GTXE2_CHANNEL_TXDATA25", + "GTXE2_IMUX47_4", + "GTXE2_CHANNEL_PMASCANOUT0", + "GTXE2_IMUX17_2", + "GTXE2_BYP0_1", + "GTXE2_CHANNEL_RXDFETAP5HOLD", + "GTXE2_IMUX5_9", + "GTXE2_CTRL1_9", + "GTXE2_IMUX15_1", + "GTXE2_CHANNEL_RXOUTCLKSEL1", + "GTXE2_CHANNEL_DRPADDR7", + "GTXE2_CLK1_4" + ], + "pips": { + "GTX_CHANNEL_1.GTXE2_IMUX8_2->GTXE2_CHANNEL_TXCHARDISPVAL2": { + "src_wire": "GTXE2_IMUX8_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX21_6->GTXE2_CHANNEL_TXDATA7": { + "src_wire": "GTXE2_IMUX21_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDO0->GTXE2_LOGIC_OUTS_B16_10": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX2_6->GTXE2_CHANNEL_TXPRECURSOR3": { + "src_wire": "GTXE2_IMUX2_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX4_9->GTXE2_CHANNEL_PMARSVDIN1": { + "src_wire": "GTXE2_IMUX4_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCLKCORCNT0->GTXE2_LOGIC_OUTS_B18_5": { + "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL0_5->GTXE2_CHANNEL_GTTXRESET": { + "src_wire": "GTXE2_CTRL0_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTTXRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA0->GTXE2_LOGIC_OUTS_B15_9": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE0->GTXE2_LOGIC_OUTS_B14_10": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX5_1->GTXE2_CHANNEL_TXQPIBIASEN": { + "src_wire": "GTXE2_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXQPIBIASEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA61->GTXE2_LOGIC_OUTS_B2_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA61", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK7->GTXE2_LOGIC_OUTS_B12_3": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX31_0->GTXE2_CHANNEL_TXCHARDISPMODE7": { + "src_wire": "GTXE2_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX7_7->GTXE2_CHANNEL_TXPRECURSOR4": { + "src_wire": "GTXE2_IMUX7_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX3_7->GTXE2_CHANNEL_RXPD0": { + "src_wire": "GTXE2_IMUX3_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL0_7->GTXE2_CHANNEL_RXCDRFREQRESET": { + "src_wire": "GTXE2_CTRL0_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRFREQRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX23_10->GTXE2_CHANNEL_RXCHBONDI4": { + "src_wire": "GTXE2_IMUX23_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX31_7->GTXE2_CHANNEL_TXCHARISK0": { + "src_wire": "GTXE2_IMUX31_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX39_6->GTXE2_CHANNEL_TXELECIDLE": { + "src_wire": "GTXE2_IMUX39_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXELECIDLE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT15->GTXE2_LOGIC_OUTS_B16_1": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT15", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX35_3->GTXE2_CHANNEL_DRPADDR6": { + "src_wire": "GTXE2_IMUX35_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX24_4->GTXE2_CHANNEL_TSTIN13": { + "src_wire": "GTXE2_IMUX24_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX8_5->GTXE2_CHANNEL_TX8B10BBYPASS5": { + "src_wire": "GTXE2_IMUX8_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX17_9->GTXE2_CHANNEL_RXCHBONDEN": { + "src_wire": "GTXE2_IMUX17_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX38_2->GTXE2_CHANNEL_DRPADDR1": { + "src_wire": "GTXE2_IMUX38_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_NORTHREFCLK1->GTXE2_CHANNEL_GTNORTHREFCLK1": { + "src_wire": "GTXE2_CHANNEL_NORTHREFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA35->GTXE2_LOGIC_OUTS_B5_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA35", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT9->GTXE2_LOGIC_OUTS_B11_9": { + "src_wire": "GTXE2_CHANNEL_TSTOUT9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA10->GTXE2_LOGIC_OUTS_B4_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA10", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDO1->GTXE2_LOGIC_OUTS_B16_9": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA27->GTXE2_LOGIC_OUTS_B0_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA27", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX13_7->GTXE2_CHANNEL_TXBUFDIFFCTRL1": { + "src_wire": "GTXE2_IMUX13_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX29_8->GTXE2_CHANNEL_RXOSHOLD": { + "src_wire": "GTXE2_IMUX29_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOSHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX45_10->GTXE2_CHANNEL_RXMONITORSEL0": { + "src_wire": "GTXE2_IMUX45_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX22_4->GTXE2_CHANNEL_TXDATA46": { + "src_wire": "GTXE2_IMUX22_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA46", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX28_8->GTXE2_CHANNEL_RXPD1": { + "src_wire": "GTXE2_IMUX28_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX22_8->GTXE2_CHANNEL_RXPRBSSEL0": { + "src_wire": "GTXE2_IMUX22_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA26->GTXE2_LOGIC_OUTS_B4_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA26", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHANREALIGN->GTXE2_LOGIC_OUTS_B23_9": { + "src_wire": "GTXE2_CHANNEL_RXCHANREALIGN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA9->GTXE2_LOGIC_OUTS_B2_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATAVALID->GTXE2_LOGIC_OUTS_B19_5": { + "src_wire": "GTXE2_CHANNEL_RXDATAVALID", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA0->GTXE2_LOGIC_OUTS_B6_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX21_3->GTXE2_CHANNEL_TXDATA51": { + "src_wire": "GTXE2_IMUX21_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA51", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA44->GTXE2_LOGIC_OUTS_B6_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA44", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE6->GTXE2_LOGIC_OUTS_B14_5": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA49->GTXE2_LOGIC_OUTS_B7_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA49", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXQPISENN->GTXE2_LOGIC_OUTS_B17_1": { + "src_wire": "GTXE2_CHANNEL_RXQPISENN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_REFCLK0->GTXE2_CHANNEL_GTREFCLK0": { + "src_wire": "GTXE2_CHANNEL_REFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX9_7->GTXE2_CHANNEL_PCSRSVDIN12": { + "src_wire": "GTXE2_IMUX9_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX40_7->GTXE2_CHANNEL_TSTIN6": { + "src_wire": "GTXE2_IMUX40_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA13->GTXE2_LOGIC_OUTS_B7_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA13", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK5->GTXE2_LOGIC_OUTS_B12_7": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_QPLLREFCLK->GTXE2_CHANNEL_GTQPLLREFCLK": { + "src_wire": "GTXE2_CHANNEL_QPLLREFCLK", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTQPLLREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR5->GTXE2_LOGIC_OUTS_B22_7": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX29_1->GTXE2_CHANNEL_TXCHARISK7": { + "src_wire": "GTXE2_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXP_PAD->GTXE2_CHANNEL_RXP": { + "src_wire": "GTXE2_CHANNEL_RXP_PAD", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXP", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA20->GTXE2_LOGIC_OUTS_B3_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA20", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA40->GTXE2_LOGIC_OUTS_B3_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA40", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX5_3->GTXE2_CHANNEL_TXMAINCURSOR0": { + "src_wire": "GTXE2_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK1->GTXE2_LOGIC_OUTS_B12_8": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX19_8->GTXE2_CHANNEL_RXDFEVPHOLD": { + "src_wire": "GTXE2_IMUX19_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEVPHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA11->GTXE2_LOGIC_OUTS_B0_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA11", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX44_10->GTXE2_CHANNEL_RXDFETAP2HOLD": { + "src_wire": "GTXE2_IMUX44_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP2HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX40_3->GTXE2_CHANNEL_TSTIN2": { + "src_wire": "GTXE2_IMUX40_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT2->GTXE2_LOGIC_OUTS_B11_2": { + "src_wire": "GTXE2_CHANNEL_TSTOUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX34_9->GTXE2_CHANNEL_RXPCOMMAALIGNEN": { + "src_wire": "GTXE2_IMUX34_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX30_3->GTXE2_CHANNEL_TXPOLARITY": { + "src_wire": "GTXE2_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOLARITY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX42_5->GTXE2_CHANNEL_GTRSVD2": { + "src_wire": "GTXE2_IMUX42_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCDRLOCK->GTXE2_LOGIC_OUTS_B17_5": { + "src_wire": "GTXE2_CHANNEL_RXCDRLOCK", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR6->GTXE2_LOGIC_OUTS_B22_5": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX38_5->GTXE2_CHANNEL_TXSWING": { + "src_wire": "GTXE2_IMUX38_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSWING", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX37_3->GTXE2_CHANNEL_TXPHDLYPD": { + "src_wire": "GTXE2_IMUX37_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHDLYPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXSTATUS2->GTXE2_LOGIC_OUTS_B23_8": { + "src_wire": "GTXE2_CHANNEL_RXSTATUS2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT2->GTXE2_LOGIC_OUTS_B8_8": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT3->GTXE2_LOGIC_OUTS_B13_3": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX17_3->GTXE2_CHANNEL_TXDATA49": { + "src_wire": "GTXE2_IMUX17_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA49", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA62->GTXE2_LOGIC_OUTS_B4_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA62", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX39_3->GTXE2_CHANNEL_DRPADDR4": { + "src_wire": "GTXE2_IMUX39_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX20_0->GTXE2_CHANNEL_TXDATA30": { + "src_wire": "GTXE2_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA30", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX17_4->GTXE2_CHANNEL_TXDATA13": { + "src_wire": "GTXE2_IMUX17_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX22_2->GTXE2_CHANNEL_TXDATA54": { + "src_wire": "GTXE2_IMUX22_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA54", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXN->GTXE2_CHANNEL_TXN_PAD": { + "src_wire": "GTXE2_CHANNEL_TXN", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXN_PAD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA50->GTXE2_LOGIC_OUTS_B1_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA50", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CLK1_6->GTXE2_CHANNEL_GTGREFCLK": { + "src_wire": "GTXE2_CLK1_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTGREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO1->GTXE2_LOGIC_OUTS_B4_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX21_4->GTXE2_CHANNEL_TXDATA15": { + "src_wire": "GTXE2_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX16_4->GTXE2_CHANNEL_TXDATA12": { + "src_wire": "GTXE2_IMUX16_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX0_10->GTXE2_CHANNEL_RXELECIDLEMODE0": { + "src_wire": "GTXE2_IMUX0_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX19_10->GTXE2_CHANNEL_RXCHBONDLEVEL1": { + "src_wire": "GTXE2_IMUX19_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT1->GTXE2_LOGIC_OUTS_B8_9": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX25_3->GTXE2_CHANNEL_PCSRSVDIN0": { + "src_wire": "GTXE2_IMUX25_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_REFCLK1->GTXE2_CHANNEL_GTREFCLK1": { + "src_wire": "GTXE2_CHANNEL_REFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA59->GTXE2_LOGIC_OUTS_B5_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA59", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX25_5->GTXE2_CHANNEL_PCSRSVDIN2": { + "src_wire": "GTXE2_IMUX25_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX35_5->GTXE2_CHANNEL_TXDEEMPH": { + "src_wire": "GTXE2_IMUX35_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDEEMPH", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX7_6->GTXE2_CHANNEL_TXPRECURSOR0": { + "src_wire": "GTXE2_IMUX7_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX13_2->GTXE2_CHANNEL_TXHEADER0": { + "src_wire": "GTXE2_IMUX13_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXHEADER0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT11->GTXE2_LOGIC_OUTS_B9_0": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT11", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXBUFSTATUS1->GTXE2_LOGIC_OUTS_B19_10": { + "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX29_3->GTXE2_CHANNEL_TXCHARISK6": { + "src_wire": "GTXE2_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT2->GTXE2_LOGIC_OUTS_B13_2": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK3->GTXE2_LOGIC_OUTS_B12_4": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CLK0_5->GTXE2_CHANNEL_TXUSRCLK2": { + "src_wire": "GTXE2_CLK0_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXUSRCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA5->GTXE2_LOGIC_OUTS_B15_8": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX28_3->GTXE2_CHANNEL_DRPWE": { + "src_wire": "GTXE2_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPWE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXBYTEISALIGNED->GTXE2_LOGIC_OUTS_B18_10": { + "src_wire": "GTXE2_CHANNEL_RXBYTEISALIGNED", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX9_3->GTXE2_CHANNEL_PCSRSVDIN8": { + "src_wire": "GTXE2_IMUX9_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX35_8->GTXE2_CHANNEL_RXDFEUTOVRDEN": { + "src_wire": "GTXE2_IMUX35_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEUTOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX0_7->GTXE2_CHANNEL_PMARSVDIN23": { + "src_wire": "GTXE2_IMUX0_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX11_10->GTXE2_CHANNEL_RXLPMLFHOLD": { + "src_wire": "GTXE2_IMUX11_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMLFHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX35_2->GTXE2_CHANNEL_DRPADDR2": { + "src_wire": "GTXE2_IMUX35_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT8->GTXE2_LOGIC_OUTS_B11_8": { + "src_wire": "GTXE2_CHANNEL_TSTOUT8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA18->GTXE2_LOGIC_OUTS_B4_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA18", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX7_0->GTXE2_CHANNEL_TXPISOPD": { + "src_wire": "GTXE2_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPISOPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX8_6->GTXE2_CHANNEL_TXCHARDISPVAL0": { + "src_wire": "GTXE2_IMUX8_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX8_8->GTXE2_CHANNEL_RXDDIEN": { + "src_wire": "GTXE2_IMUX8_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDDIEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX19_5->GTXE2_CHANNEL_TXDATA9": { + "src_wire": "GTXE2_IMUX19_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX27_5->GTXE2_CHANNEL_TXPHINIT": { + "src_wire": "GTXE2_IMUX27_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHINIT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX44_9->GTXE2_CHANNEL_RXCOMMADETEN": { + "src_wire": "GTXE2_IMUX44_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCOMMADETEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX28_10->GTXE2_CHANNEL_RXDFETAP2OVRDEN": { + "src_wire": "GTXE2_IMUX28_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX17_1->GTXE2_CHANNEL_TXDATA57": { + "src_wire": "GTXE2_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA57", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL1_3->GTXE2_CHANNEL_TXPMARESET": { + "src_wire": "GTXE2_CTRL1_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPMARESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX15_6->GTXE2_CHANNEL_RXRATE0": { + "src_wire": "GTXE2_IMUX15_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXRATE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA24->GTXE2_LOGIC_OUTS_B6_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA24", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX16_1->GTXE2_CHANNEL_TXDATA56": { + "src_wire": "GTXE2_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA56", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX17_2->GTXE2_CHANNEL_TXDATA21": { + "src_wire": "GTXE2_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX31_3->GTXE2_CHANNEL_TXCHARISK2": { + "src_wire": "GTXE2_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA45->GTXE2_LOGIC_OUTS_B2_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA45", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX5_7->GTXE2_CHANNEL_PMARSVDIN20": { + "src_wire": "GTXE2_IMUX5_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHMONITOR1->GTXE2_LOGIC_OUTS_B1_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX1_7->GTXE2_CHANNEL_PMARSVDIN22": { + "src_wire": "GTXE2_IMUX1_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX1_2->GTXE2_CHANNEL_RXMONITORSEL1": { + "src_wire": "GTXE2_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCOMSASDET->GTXE2_LOGIC_OUTS_B18_7": { + "src_wire": "GTXE2_CHANNEL_RXCOMSASDET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX40_8->GTXE2_CHANNEL_TSTIN7": { + "src_wire": "GTXE2_IMUX40_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX0_9->GTXE2_CHANNEL_PMARSVDIN3": { + "src_wire": "GTXE2_IMUX0_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA16->GTXE2_LOGIC_OUTS_B6_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA16", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHMONITOR4->GTXE2_LOGIC_OUTS_B21_3": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR4->GTXE2_LOGIC_OUTS_B22_9": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA55->GTXE2_LOGIC_OUTS_B0_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA55", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX34_1->GTXE2_CHANNEL_DRPDI7": { + "src_wire": "GTXE2_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX17_0->GTXE2_CHANNEL_TXDATA29": { + "src_wire": "GTXE2_IMUX17_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA29", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA7->GTXE2_LOGIC_OUTS_B15_4": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX24_5->GTXE2_CHANNEL_TSTIN14": { + "src_wire": "GTXE2_IMUX24_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX38_3->GTXE2_CHANNEL_DRPADDR5": { + "src_wire": "GTXE2_IMUX38_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX26_10->GTXE2_CHANNEL_GTRSVD15": { + "src_wire": "GTXE2_IMUX26_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX46_6->GTXE2_CHANNEL_TXRATE1": { + "src_wire": "GTXE2_IMUX46_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXRATE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXCOMFINISH->GTXE2_LOGIC_OUTS_B16_5": { + "src_wire": "GTXE2_CHANNEL_TXCOMFINISH", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA4->GTXE2_LOGIC_OUTS_B3_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX21_5->GTXE2_CHANNEL_TXDATA43": { + "src_wire": "GTXE2_IMUX21_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA43", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT5->GTXE2_LOGIC_OUTS_B8_5": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX43_10->GTXE2_CHANNEL_RXLPMHFHOLD": { + "src_wire": "GTXE2_IMUX43_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMHFHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX25_4->GTXE2_CHANNEL_PCSRSVDIN1": { + "src_wire": "GTXE2_IMUX25_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX23_7->GTXE2_CHANNEL_TXDATA3": { + "src_wire": "GTXE2_IMUX23_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX41_6->GTXE2_CHANNEL_RXPHALIGNEN": { + "src_wire": "GTXE2_IMUX41_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX3_4->GTXE2_CHANNEL_TXPOSTCURSOR2": { + "src_wire": "GTXE2_IMUX3_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT2->GTXE2_LOGIC_OUTS_B9_8": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX9_9->GTXE2_CHANNEL_PCSRSVDIN14": { + "src_wire": "GTXE2_IMUX9_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX39_5->GTXE2_CHANNEL_TXDETECTRX": { + "src_wire": "GTXE2_IMUX39_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDETECTRX", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO6->GTXE2_LOGIC_OUTS_B7_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX27_9->GTXE2_CHANNEL_RXDFELFOVRDEN": { + "src_wire": "GTXE2_IMUX27_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFELFOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX40_5->GTXE2_CHANNEL_TSTIN4": { + "src_wire": "GTXE2_IMUX40_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX18_5->GTXE2_CHANNEL_TXDATA8": { + "src_wire": "GTXE2_IMUX18_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL0_9->GTXE2_CHANNEL_RXDFELPMRESET": { + "src_wire": "GTXE2_CTRL0_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFELPMRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX21_9->GTXE2_CHANNEL_RXDFETAP4OVRDEN": { + "src_wire": "GTXE2_IMUX21_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX24_2->GTXE2_CHANNEL_TSTIN11": { + "src_wire": "GTXE2_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA48->GTXE2_LOGIC_OUTS_B3_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA48", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX31_4->GTXE2_CHANNEL_TXCHARDISPMODE5": { + "src_wire": "GTXE2_IMUX31_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO11->GTXE2_LOGIC_OUTS_B6_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO11", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHSLIPMONITOR2->GTXE2_LOGIC_OUTS_B2_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX12_8->GTXE2_CHANNEL_RXSLIDE": { + "src_wire": "GTXE2_IMUX12_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXSLIDE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX26_6->GTXE2_CHANNEL_GTRSVD11": { + "src_wire": "GTXE2_IMUX26_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX4_3->GTXE2_CHANNEL_TXMAINCURSOR1": { + "src_wire": "GTXE2_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX12_4->GTXE2_CHANNEL_TXPHOVRDEN": { + "src_wire": "GTXE2_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX25_7->GTXE2_CHANNEL_PCSRSVDIN4": { + "src_wire": "GTXE2_IMUX25_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX30_8->GTXE2_CHANNEL_RXCDRHOLD": { + "src_wire": "GTXE2_IMUX30_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_CPLLLOCK->GTXE2_LOGIC_OUTS_B14_1": { + "src_wire": "GTXE2_CHANNEL_CPLLLOCK", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CLK0_7->GTXE2_CHANNEL_RXUSRCLK2": { + "src_wire": "GTXE2_CLK0_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXUSRCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX22_1->GTXE2_CHANNEL_TXDATA26": { + "src_wire": "GTXE2_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA26", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX5_5->GTXE2_CHANNEL_TXSEQUENCE0": { + "src_wire": "GTXE2_IMUX5_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHMONITOR0->GTXE2_LOGIC_OUTS_B5_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXRATEDONE->GTXE2_LOGIC_OUTS_B23_5": { + "src_wire": "GTXE2_CHANNEL_RXRATEDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX15_3->GTXE2_CHANNEL_TX8B10BBYPASS2": { + "src_wire": "GTXE2_IMUX15_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX22_7->GTXE2_CHANNEL_TXDATA2": { + "src_wire": "GTXE2_IMUX22_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX7_8->GTXE2_CHANNEL_TXPRBSSEL2": { + "src_wire": "GTXE2_IMUX7_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT0->GTXE2_LOGIC_OUTS_B8_10": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX35_6->GTXE2_CHANNEL_TXPD1": { + "src_wire": "GTXE2_IMUX35_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA19->GTXE2_LOGIC_OUTS_B0_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA19", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX35_0->GTXE2_CHANNEL_DRPDI2": { + "src_wire": "GTXE2_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX2_8->GTXE2_CHANNEL_RXGEARBOXSLIP": { + "src_wire": "GTXE2_IMUX2_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXGEARBOXSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXRESETDONE->GTXE2_LOGIC_OUTS_B20_8": { + "src_wire": "GTXE2_CHANNEL_RXRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX19_3->GTXE2_CHANNEL_TXDATA17": { + "src_wire": "GTXE2_IMUX19_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA17", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX14_2->GTXE2_CHANNEL_CPLLREFCLKSEL1": { + "src_wire": "GTXE2_IMUX14_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CLK1_7->GTXE2_CHANNEL_CLKRSVD2": { + "src_wire": "GTXE2_CLK1_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX5_4->GTXE2_CHANNEL_TXMAINCURSOR4": { + "src_wire": "GTXE2_IMUX5_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA31->GTXE2_LOGIC_OUTS_B5_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA31", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX16_7->GTXE2_CHANNEL_TXDATA35": { + "src_wire": "GTXE2_IMUX16_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA35", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT4->GTXE2_LOGIC_OUTS_B8_6": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT3->GTXE2_LOGIC_OUTS_B11_3": { + "src_wire": "GTXE2_CHANNEL_TSTOUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX2_9->GTXE2_CHANNEL_RXMCOMMAALIGNEN": { + "src_wire": "GTXE2_IMUX2_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX31_2->GTXE2_CHANNEL_TXCHARDISPMODE6": { + "src_wire": "GTXE2_IMUX31_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX19_2->GTXE2_CHANNEL_TXDATA53": { + "src_wire": "GTXE2_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA53", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX37_9->GTXE2_CHANNEL_RXDFETAP4HOLD": { + "src_wire": "GTXE2_IMUX37_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP4HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX20_1->GTXE2_CHANNEL_TXDATA58": { + "src_wire": "GTXE2_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA58", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHMONITOR3->GTXE2_LOGIC_OUTS_B3_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT3->GTXE2_LOGIC_OUTS_B8_7": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA63->GTXE2_LOGIC_OUTS_B0_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA63", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX28_6->GTXE2_CHANNEL_RXDLYEN": { + "src_wire": "GTXE2_IMUX28_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX27_8->GTXE2_CHANNEL_RXDFEVPOVRDEN": { + "src_wire": "GTXE2_IMUX27_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEVPOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX4_1->GTXE2_CHANNEL_TXPRECURSORINV": { + "src_wire": "GTXE2_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSORINV", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX4_4->GTXE2_CHANNEL_TXMAINCURSOR5": { + "src_wire": "GTXE2_IMUX4_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA3->GTXE2_LOGIC_OUTS_B15_3": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE5->GTXE2_LOGIC_OUTS_B14_7": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX23_6->GTXE2_CHANNEL_TXDATA39": { + "src_wire": "GTXE2_IMUX23_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA39", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHSLIPMONITOR1->GTXE2_LOGIC_OUTS_B4_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX39_0->GTXE2_CHANNEL_DRPDI0": { + "src_wire": "GTXE2_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX19_9->GTXE2_CHANNEL_RXCHBONDI1": { + "src_wire": "GTXE2_IMUX19_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B22_1": { + "src_wire": "GTXE2_CHANNEL_RXDLYSRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX30_9->GTXE2_CHANNEL_RXCHBONDMASTER": { + "src_wire": "GTXE2_IMUX30_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDMASTER", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXOUTCLKPCS->GTXE2_LOGIC_OUTS_B21_9": { + "src_wire": "GTXE2_CHANNEL_RXOUTCLKPCS", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_GTREFCLKMONITOR->GTXE2_LOGIC_OUTS_B23_2": { + "src_wire": "GTXE2_CHANNEL_GTREFCLKMONITOR", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX44_3->GTXE2_CHANNEL_DRPEN": { + "src_wire": "GTXE2_IMUX44_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX29_7->GTXE2_CHANNEL_TXCHARISK4": { + "src_wire": "GTXE2_IMUX29_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO14->GTXE2_LOGIC_OUTS_B7_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO14", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CLK0_4->GTXE2_CHANNEL_TXUSRCLK": { + "src_wire": "GTXE2_CLK0_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXUSRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX21_8->GTXE2_CHANNEL_RXDFEXYDOVRDEN": { + "src_wire": "GTXE2_IMUX21_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXP->GTXE2_CHANNEL_TXP_PAD": { + "src_wire": "GTXE2_CHANNEL_TXP", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXP_PAD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX36_2->GTXE2_CHANNEL_CPLLPD": { + "src_wire": "GTXE2_IMUX36_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX19_6->GTXE2_CHANNEL_TXDATA37": { + "src_wire": "GTXE2_IMUX19_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA37", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT6->GTXE2_LOGIC_OUTS_B8_4": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO12->GTXE2_LOGIC_OUTS_B5_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO12", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX0_2->GTXE2_CHANNEL_TX8B10BEN": { + "src_wire": "GTXE2_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA43->GTXE2_LOGIC_OUTS_B5_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA43", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE2->GTXE2_LOGIC_OUTS_B14_6": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA8->GTXE2_LOGIC_OUTS_B6_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX44_1->GTXE2_CHANNEL_TXCOMINIT": { + "src_wire": "GTXE2_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCOMINIT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX34_10->GTXE2_CHANNEL_PCSRSVDIN20": { + "src_wire": "GTXE2_IMUX34_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX45_9->GTXE2_CHANNEL_RXDFEXYDEN": { + "src_wire": "GTXE2_IMUX45_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEXYDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXHEADER0->GTXE2_LOGIC_OUTS_B19_6": { + "src_wire": "GTXE2_CHANNEL_RXHEADER0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX26_8->GTXE2_CHANNEL_GTRSVD13": { + "src_wire": "GTXE2_IMUX26_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX21_7->GTXE2_CHANNEL_TXDATA32": { + "src_wire": "GTXE2_IMUX21_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA32", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX22_5->GTXE2_CHANNEL_TXDATA10": { + "src_wire": "GTXE2_IMUX22_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX7_5->GTXE2_CHANNEL_TXDIFFCTRL0": { + "src_wire": "GTXE2_IMUX7_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX20_3->GTXE2_CHANNEL_TXDATA50": { + "src_wire": "GTXE2_IMUX20_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA50", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B17_3": { + "src_wire": "GTXE2_CHANNEL_TXDLYSRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX31_5->GTXE2_CHANNEL_TXCHARISK1": { + "src_wire": "GTXE2_IMUX31_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX8_1->GTXE2_CHANNEL_TX8B10BBYPASS7": { + "src_wire": "GTXE2_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX29_2->GTXE2_CHANNEL_TXCHARDISPMODE2": { + "src_wire": "GTXE2_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX1_10->GTXE2_CHANNEL_RXELECIDLEMODE1": { + "src_wire": "GTXE2_IMUX1_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX3_10->GTXE2_CHANNEL_RXLPMLFKLOVRDEN": { + "src_wire": "GTXE2_IMUX3_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA22->GTXE2_LOGIC_OUTS_B1_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA22", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT1->GTXE2_LOGIC_OUTS_B9_9": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_3": { + "src_wire": "GTXE2_CHANNEL_TXPHALIGNDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX19_4->GTXE2_CHANNEL_TXDATA45": { + "src_wire": "GTXE2_IMUX19_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA45", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX41_0->GTXE2_CHANNEL_EYESCANMODE": { + "src_wire": "GTXE2_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_EYESCANMODE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA60->GTXE2_LOGIC_OUTS_B6_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA60", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX20_7->GTXE2_CHANNEL_TXDATA33": { + "src_wire": "GTXE2_IMUX20_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA33", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX23_9->GTXE2_CHANNEL_RXCHBONDI3": { + "src_wire": "GTXE2_IMUX23_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CLK1_2->GTXE2_CHANNEL_TXPHDLYTSTCLK": { + "src_wire": "GTXE2_CLK1_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHDLYTSTCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX24_6->GTXE2_CHANNEL_TSTIN15": { + "src_wire": "GTXE2_IMUX24_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR3->GTXE2_LOGIC_OUTS_B22_4": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT10->GTXE2_LOGIC_OUTS_B13_10": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT10", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX35_1->GTXE2_CHANNEL_DRPDI6": { + "src_wire": "GTXE2_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX14_5->GTXE2_CHANNEL_TXDLYEN": { + "src_wire": "GTXE2_IMUX14_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX29_5->GTXE2_CHANNEL_TXCHARISK5": { + "src_wire": "GTXE2_IMUX29_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXN_PAD->GTXE2_CHANNEL_RXN": { + "src_wire": "GTXE2_CHANNEL_RXN_PAD", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT5->GTXE2_LOGIC_OUTS_B9_5": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCOMMADET->GTXE2_LOGIC_OUTS_B19_7": { + "src_wire": "GTXE2_CHANNEL_RXCOMMADET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX42_8->GTXE2_CHANNEL_GTRSVD5": { + "src_wire": "GTXE2_IMUX42_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX0_6->GTXE2_CHANNEL_PMARSVDIN24": { + "src_wire": "GTXE2_IMUX0_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXQPISENN->GTXE2_LOGIC_OUTS_B20_3": { + "src_wire": "GTXE2_CHANNEL_TXQPISENN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX33_1->GTXE2_CHANNEL_DRPDI14": { + "src_wire": "GTXE2_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA1->GTXE2_LOGIC_OUTS_B2_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX13_8->GTXE2_CHANNEL_RXOSOVRDEN": { + "src_wire": "GTXE2_IMUX13_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOSOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCOMWAKEDET->GTXE2_LOGIC_OUTS_B19_9": { + "src_wire": "GTXE2_CHANNEL_RXCOMWAKEDET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX1_6->GTXE2_CHANNEL_TXSEQUENCE6": { + "src_wire": "GTXE2_IMUX1_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX39_10->GTXE2_CHANNEL_PCSRSVDIN23": { + "src_wire": "GTXE2_IMUX39_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHANISALIGNED->GTXE2_LOGIC_OUTS_B18_9": { + "src_wire": "GTXE2_CHANNEL_RXCHANISALIGNED", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX15_4->GTXE2_CHANNEL_TXPRBSFORCEERR": { + "src_wire": "GTXE2_IMUX15_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSFORCEERR", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX16_3->GTXE2_CHANNEL_TXDATA48": { + "src_wire": "GTXE2_IMUX16_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA48", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX16_6->GTXE2_CHANNEL_TXDATA4": { + "src_wire": "GTXE2_IMUX16_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR2->GTXE2_LOGIC_OUTS_B22_6": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXRESETDONE->GTXE2_LOGIC_OUTS_B16_4": { + "src_wire": "GTXE2_CHANNEL_TXRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX15_2->GTXE2_CHANNEL_CPLLREFCLKSEL0": { + "src_wire": "GTXE2_IMUX15_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL0_3->GTXE2_CHANNEL_CPLLRESET": { + "src_wire": "GTXE2_CTRL0_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX43_9->GTXE2_CHANNEL_LOOPBACK0": { + "src_wire": "GTXE2_IMUX43_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_LOOPBACK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX6_4->GTXE2_CHANNEL_TXPOSTCURSOR1": { + "src_wire": "GTXE2_IMUX6_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK0->GTXE2_LOGIC_OUTS_B12_10": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX39_1->GTXE2_CHANNEL_DRPDI4": { + "src_wire": "GTXE2_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX42_3->GTXE2_CHANNEL_GTRSVD0": { + "src_wire": "GTXE2_IMUX42_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B23_3": { + "src_wire": "GTXE2_CHANNEL_TXOUTCLKFABRIC", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX15_5->GTXE2_CHANNEL_TX8B10BBYPASS1": { + "src_wire": "GTXE2_IMUX15_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX24_8->GTXE2_CHANNEL_TSTIN17": { + "src_wire": "GTXE2_IMUX24_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN17", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CLK0_2->GTXE2_CHANNEL_CPLLLOCKDETCLK": { + "src_wire": "GTXE2_CLK0_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLLOCKDETCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX3_3->GTXE2_CHANNEL_TXSTARTSEQ": { + "src_wire": "GTXE2_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSTARTSEQ", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHSLIPMONITOR0->GTXE2_LOGIC_OUTS_B0_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX28_1->GTXE2_CHANNEL_TXCOMSAS": { + "src_wire": "GTXE2_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCOMSAS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX14_8->GTXE2_CHANNEL_RXCDROVRDEN": { + "src_wire": "GTXE2_IMUX14_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDROVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA4->GTXE2_LOGIC_OUTS_B15_10": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX40_2->GTXE2_CHANNEL_TSTIN1": { + "src_wire": "GTXE2_IMUX40_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX33_2->GTXE2_CHANNEL_TXPHALIGNEN": { + "src_wire": "GTXE2_IMUX33_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX10_4->GTXE2_CHANNEL_TXCHARDISPVAL5": { + "src_wire": "GTXE2_IMUX10_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX11_2->GTXE2_CHANNEL_CPLLREFCLKSEL2": { + "src_wire": "GTXE2_IMUX11_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR7->GTXE2_LOGIC_OUTS_B22_3": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA51->GTXE2_LOGIC_OUTS_B5_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA51", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX2_10->GTXE2_CHANNEL_RXOUTCLKSEL2": { + "src_wire": "GTXE2_IMUX2_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXHEADER2->GTXE2_LOGIC_OUTS_B17_6": { + "src_wire": "GTXE2_CHANNEL_RXHEADER2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_EYESCANDATAERROR->GTXE2_LOGIC_OUTS_B20_10": { + "src_wire": "GTXE2_CHANNEL_EYESCANDATAERROR", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX32_1->GTXE2_CHANNEL_DRPDI15": { + "src_wire": "GTXE2_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA53->GTXE2_LOGIC_OUTS_B2_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA53", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX18_4->GTXE2_CHANNEL_TXDATA44": { + "src_wire": "GTXE2_IMUX18_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA44", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA52->GTXE2_LOGIC_OUTS_B6_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA52", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO13->GTXE2_LOGIC_OUTS_B1_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO13", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX12_7->GTXE2_CHANNEL_TXBUFDIFFCTRL0": { + "src_wire": "GTXE2_IMUX12_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX14_10->GTXE2_CHANNEL_RXPHOVRDEN": { + "src_wire": "GTXE2_IMUX14_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA14->GTXE2_LOGIC_OUTS_B1_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA14", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX18_2->GTXE2_CHANNEL_TXDATA52": { + "src_wire": "GTXE2_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA52", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX40_6->GTXE2_CHANNEL_TSTIN5": { + "src_wire": "GTXE2_IMUX40_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_QPLLCLK->GTXE2_CHANNEL_GTQPLLCLK": { + "src_wire": "GTXE2_CHANNEL_QPLLCLK", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTQPLLCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX26_7->GTXE2_CHANNEL_GTRSVD12": { + "src_wire": "GTXE2_IMUX26_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX0_5->GTXE2_CHANNEL_TXSEQUENCE3": { + "src_wire": "GTXE2_IMUX0_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE3->GTXE2_LOGIC_OUTS_B14_4": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX44_8->GTXE2_CHANNEL_RXUSERRDY": { + "src_wire": "GTXE2_IMUX44_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXUSERRDY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX10_7->GTXE2_CHANNEL_TXBUFDIFFCTRL2": { + "src_wire": "GTXE2_IMUX10_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CLK0_6->GTXE2_CHANNEL_RXUSRCLK": { + "src_wire": "GTXE2_CLK0_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXUSRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT6->GTXE2_LOGIC_OUTS_B9_4": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX35_9->GTXE2_CHANNEL_RXDFELFHOLD": { + "src_wire": "GTXE2_IMUX35_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFELFHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA38->GTXE2_LOGIC_OUTS_B4_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA38", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDO2->GTXE2_LOGIC_OUTS_B16_8": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX9_1->GTXE2_CHANNEL_RXPHDLYPD": { + "src_wire": "GTXE2_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHDLYPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXBUFSTATUS0->GTXE2_LOGIC_OUTS_B23_10": { + "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX3_9->GTXE2_CHANNEL_RXDFEUTHOLD": { + "src_wire": "GTXE2_IMUX3_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEUTHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT4->GTXE2_LOGIC_OUTS_B11_4": { + "src_wire": "GTXE2_CHANNEL_TSTOUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX34_0->GTXE2_CHANNEL_DRPDI3": { + "src_wire": "GTXE2_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX36_1->GTXE2_CHANNEL_DRPDI13": { + "src_wire": "GTXE2_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX21_10->GTXE2_CHANNEL_RXDFEAGCOVRDEN": { + "src_wire": "GTXE2_IMUX21_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXQPISENP->GTXE2_LOGIC_OUTS_B8_3": { + "src_wire": "GTXE2_CHANNEL_TXQPISENP", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT13->GTXE2_LOGIC_OUTS_B9_2": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT13", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX13_10->GTXE2_CHANNEL_RXPRBSCNTRESET": { + "src_wire": "GTXE2_IMUX13_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSCNTRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX45_2->GTXE2_CHANNEL_RXSYSCLKSEL0": { + "src_wire": "GTXE2_IMUX45_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX23_4->GTXE2_CHANNEL_TXDATA47": { + "src_wire": "GTXE2_IMUX23_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA47", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX9_10->GTXE2_CHANNEL_PCSRSVDIN15": { + "src_wire": "GTXE2_IMUX9_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CLK1_4->GTXE2_CHANNEL_CLKRSVD0": { + "src_wire": "GTXE2_CLK1_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX21_1->GTXE2_CHANNEL_TXDATA59": { + "src_wire": "GTXE2_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA59", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK2->GTXE2_LOGIC_OUTS_B12_6": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX19_0->GTXE2_CHANNEL_TXDATA61": { + "src_wire": "GTXE2_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA61", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX18_1->GTXE2_CHANNEL_TXDATA24": { + "src_wire": "GTXE2_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CLK1_8->GTXE2_CHANNEL_CLKRSVD3": { + "src_wire": "GTXE2_CLK1_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX16_0->GTXE2_CHANNEL_TXDATA28": { + "src_wire": "GTXE2_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA28", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX43_6->GTXE2_CHANNEL_TXRATE2": { + "src_wire": "GTXE2_IMUX43_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXRATE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHMONITOR2->GTXE2_LOGIC_OUTS_B7_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL1_7->GTXE2_CHANNEL_RXPMARESET": { + "src_wire": "GTXE2_CTRL1_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPMARESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX28_2->GTXE2_CHANNEL_CPLLLOCKEN": { + "src_wire": "GTXE2_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLLOCKEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT3->GTXE2_LOGIC_OUTS_B9_7": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA6->GTXE2_LOGIC_OUTS_B15_6": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT0->GTXE2_LOGIC_OUTS_B11_0": { + "src_wire": "GTXE2_CHANNEL_TSTOUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX43_5->GTXE2_CHANNEL_TXDLYUPDOWN": { + "src_wire": "GTXE2_IMUX43_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYUPDOWN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHSLIPMONITOR3->GTXE2_LOGIC_OUTS_B6_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX3_8->GTXE2_CHANNEL_TXPRBSSEL0": { + "src_wire": "GTXE2_IMUX3_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL0_10->GTXE2_CHANNEL_GTRESETSEL": { + "src_wire": "GTXE2_CTRL0_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRESETSEL", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_4": { + "src_wire": "GTXE2_CHANNEL_RXPHALIGNDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX17_5->GTXE2_CHANNEL_TXDATA41": { + "src_wire": "GTXE2_IMUX17_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA41", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO10->GTXE2_LOGIC_OUTS_B2_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO10", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX29_9->GTXE2_CHANNEL_RXDFETAP5HOLD": { + "src_wire": "GTXE2_IMUX29_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP5HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX28_4->GTXE2_CHANNEL_TXSYSCLKSEL1": { + "src_wire": "GTXE2_IMUX28_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX2_5->GTXE2_CHANNEL_TXDIFFCTRL3": { + "src_wire": "GTXE2_IMUX2_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX37_0->GTXE2_CHANNEL_DRPDI8": { + "src_wire": "GTXE2_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_SOUTHREFCLK0->GTXE2_CHANNEL_GTSOUTHREFCLK0": { + "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX10_6->GTXE2_CHANNEL_TXCHARDISPVAL4": { + "src_wire": "GTXE2_IMUX10_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX3_6->GTXE2_CHANNEL_TXPRECURSOR2": { + "src_wire": "GTXE2_IMUX3_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX10_0->GTXE2_CHANNEL_TXCHARDISPVAL7": { + "src_wire": "GTXE2_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA6->GTXE2_LOGIC_OUTS_B1_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX34_2->GTXE2_CHANNEL_DRPADDR3": { + "src_wire": "GTXE2_IMUX34_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE4->GTXE2_LOGIC_OUTS_B14_9": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_CPLLFBCLKLOST->GTXE2_LOGIC_OUTS_B8_1": { + "src_wire": "GTXE2_CHANNEL_CPLLFBCLKLOST", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX9_4->GTXE2_CHANNEL_PCSRSVDIN9": { + "src_wire": "GTXE2_IMUX9_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX10_1->GTXE2_CHANNEL_TXPDELECIDLEMODE": { + "src_wire": "GTXE2_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPDELECIDLEMODE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX6_6->GTXE2_CHANNEL_TXPRECURSOR1": { + "src_wire": "GTXE2_IMUX6_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX38_7->GTXE2_CHANNEL_RXDLYOVRDEN": { + "src_wire": "GTXE2_IMUX38_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX22_0->GTXE2_CHANNEL_TXDATA62": { + "src_wire": "GTXE2_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA62", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA7->GTXE2_LOGIC_OUTS_B5_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX10_2->GTXE2_CHANNEL_TXCHARDISPVAL6": { + "src_wire": "GTXE2_IMUX10_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXPHINITDONE->GTXE2_LOGIC_OUTS_B17_0": { + "src_wire": "GTXE2_CHANNEL_TXPHINITDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA37->GTXE2_LOGIC_OUTS_B2_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA37", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX36_5->GTXE2_CHANNEL_TXPHDLYRESET": { + "src_wire": "GTXE2_IMUX36_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHDLYRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX47_9->GTXE2_CHANNEL_LOOPBACK2": { + "src_wire": "GTXE2_IMUX47_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_LOOPBACK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_GTTXOUTCLK_1->GTXE2_CHANNEL_TXOUTCLK_1": { + "src_wire": "GTXE2_CHANNEL_GTTXOUTCLK_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXGEARBOXREADY->GTXE2_LOGIC_OUTS_B23_4": { + "src_wire": "GTXE2_CHANNEL_TXGEARBOXREADY", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA42->GTXE2_LOGIC_OUTS_B1_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA42", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX29_0->GTXE2_CHANNEL_TXCHARDISPMODE3": { + "src_wire": "GTXE2_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA41->GTXE2_LOGIC_OUTS_B7_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA41", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXHEADER1->GTXE2_LOGIC_OUTS_B23_6": { + "src_wire": "GTXE2_CHANNEL_RXHEADER1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXOUTCLKPCS->GTXE2_LOGIC_OUTS_B17_4": { + "src_wire": "GTXE2_CHANNEL_TXOUTCLKPCS", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX30_10->GTXE2_CHANNEL_RXCHBONDSLAVE": { + "src_wire": "GTXE2_IMUX30_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDSLAVE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA3->GTXE2_LOGIC_OUTS_B0_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX23_5->GTXE2_CHANNEL_TXDATA11": { + "src_wire": "GTXE2_IMUX23_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX36_0->GTXE2_CHANNEL_DRPDI9": { + "src_wire": "GTXE2_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA21->GTXE2_LOGIC_OUTS_B7_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA21", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX22_3->GTXE2_CHANNEL_TXDATA18": { + "src_wire": "GTXE2_IMUX22_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA18", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR0->GTXE2_LOGIC_OUTS_B22_10": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO15->GTXE2_LOGIC_OUTS_B3_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO15", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX38_4->GTXE2_CHANNEL_TXMARGIN1": { + "src_wire": "GTXE2_IMUX38_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMARGIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX24_9->GTXE2_CHANNEL_TSTIN18": { + "src_wire": "GTXE2_IMUX24_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN18", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT14->GTXE2_LOGIC_OUTS_B16_0": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT14", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA46->GTXE2_LOGIC_OUTS_B4_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA46", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX4_8->GTXE2_CHANNEL_TXOUTCLKSEL1": { + "src_wire": "GTXE2_IMUX4_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX7_3->GTXE2_CHANNEL_TXPOSTCURSOR4": { + "src_wire": "GTXE2_IMUX7_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX24_10->GTXE2_CHANNEL_TSTIN19": { + "src_wire": "GTXE2_IMUX24_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN19", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX1_5->GTXE2_CHANNEL_TXSEQUENCE2": { + "src_wire": "GTXE2_IMUX1_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA12->GTXE2_LOGIC_OUTS_B3_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA12", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX1_4->GTXE2_CHANNEL_TXMAINCURSOR6": { + "src_wire": "GTXE2_IMUX1_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA29->GTXE2_LOGIC_OUTS_B7_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA29", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA1->GTXE2_LOGIC_OUTS_B15_7": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX25_10->GTXE2_CHANNEL_PCSRSVDIN7": { + "src_wire": "GTXE2_IMUX25_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK6->GTXE2_LOGIC_OUTS_B12_5": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX25_8->GTXE2_CHANNEL_PCSRSVDIN5": { + "src_wire": "GTXE2_IMUX25_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX7_4->GTXE2_CHANNEL_TXPOSTCURSOR0": { + "src_wire": "GTXE2_IMUX7_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA2->GTXE2_LOGIC_OUTS_B15_5": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CLK1_1->GTXE2_CHANNEL_DRPCLK": { + "src_wire": "GTXE2_CLK1_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX8_4->GTXE2_CHANNEL_TXCHARDISPVAL1": { + "src_wire": "GTXE2_IMUX8_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX45_3->GTXE2_CHANNEL_TXDLYSRESET": { + "src_wire": "GTXE2_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX16_2->GTXE2_CHANNEL_TXDATA20": { + "src_wire": "GTXE2_IMUX16_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA36->GTXE2_LOGIC_OUTS_B6_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA36", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX40_1->GTXE2_CHANNEL_TSTIN0": { + "src_wire": "GTXE2_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX18_6->GTXE2_CHANNEL_TXDATA36": { + "src_wire": "GTXE2_IMUX18_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA36", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT0->GTXE2_LOGIC_OUTS_B9_10": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX39_4->GTXE2_CHANNEL_TXMARGIN0": { + "src_wire": "GTXE2_IMUX39_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMARGIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX12_10->GTXE2_CHANNEL_RXDFETAP3OVRDEN": { + "src_wire": "GTXE2_IMUX12_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT8->GTXE2_LOGIC_OUTS_B13_8": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX39_9->GTXE2_CHANNEL_PCSRSVDIN24": { + "src_wire": "GTXE2_IMUX39_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX6_5->GTXE2_CHANNEL_TXDIFFCTRL1": { + "src_wire": "GTXE2_IMUX6_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX6_8->GTXE2_CHANNEL_TXPRBSSEL1": { + "src_wire": "GTXE2_IMUX6_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA57->GTXE2_LOGIC_OUTS_B7_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA57", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX12_5->GTXE2_CHANNEL_TXDLYOVRDEN": { + "src_wire": "GTXE2_IMUX12_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXQPISENP->GTXE2_LOGIC_OUTS_B15_1": { + "src_wire": "GTXE2_CHANNEL_RXQPISENP", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX1_9->GTXE2_CHANNEL_PMARSVDIN2": { + "src_wire": "GTXE2_IMUX1_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT12->GTXE2_LOGIC_OUTS_B9_1": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT12", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX8_7->GTXE2_CHANNEL_TX8B10BBYPASS4": { + "src_wire": "GTXE2_IMUX8_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX12_9->GTXE2_CHANNEL_RX8B10BEN": { + "src_wire": "GTXE2_IMUX12_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RX8B10BEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_SOUTHREFCLK1->GTXE2_CHANNEL_GTSOUTHREFCLK1": { + "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX21_2->GTXE2_CHANNEL_TXDATA23": { + "src_wire": "GTXE2_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX26_5->GTXE2_CHANNEL_GTRSVD10": { + "src_wire": "GTXE2_IMUX26_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX9_8->GTXE2_CHANNEL_PCSRSVDIN13": { + "src_wire": "GTXE2_IMUX9_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX37_8->GTXE2_CHANNEL_RXDFEXYDHOLD": { + "src_wire": "GTXE2_IMUX37_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEXYDHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDO4->GTXE2_LOGIC_OUTS_B16_6": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX32_0->GTXE2_CHANNEL_DRPDI11": { + "src_wire": "GTXE2_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX35_4->GTXE2_CHANNEL_TXMARGIN2": { + "src_wire": "GTXE2_IMUX35_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMARGIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX40_4->GTXE2_CHANNEL_TSTIN3": { + "src_wire": "GTXE2_IMUX40_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT9->GTXE2_LOGIC_OUTS_B13_9": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX23_8->GTXE2_CHANNEL_RXPRBSSEL2": { + "src_wire": "GTXE2_IMUX23_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX42_6->GTXE2_CHANNEL_GTRSVD3": { + "src_wire": "GTXE2_IMUX42_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX41_1->GTXE2_CHANNEL_TXPOSTCURSORINV": { + "src_wire": "GTXE2_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSORINV", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX14_6->GTXE2_CHANNEL_RXRATE1": { + "src_wire": "GTXE2_IMUX14_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXRATE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXSTARTOFSEQ->GTXE2_LOGIC_OUTS_B18_8": { + "src_wire": "GTXE2_CHANNEL_RXSTARTOFSEQ", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX26_3->GTXE2_CHANNEL_GTRSVD8": { + "src_wire": "GTXE2_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX1_3->GTXE2_CHANNEL_TXMAINCURSOR2": { + "src_wire": "GTXE2_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX4_10->GTXE2_CHANNEL_RXOUTCLKSEL0": { + "src_wire": "GTXE2_IMUX4_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPRBSERR->GTXE2_LOGIC_OUTS_B20_6": { + "src_wire": "GTXE2_CHANNEL_RXPRBSERR", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX26_9->GTXE2_CHANNEL_GTRSVD14": { + "src_wire": "GTXE2_IMUX26_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA39->GTXE2_LOGIC_OUTS_B0_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA39", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO2->GTXE2_LOGIC_OUTS_B2_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_NORTHREFCLK0->GTXE2_CHANNEL_GTNORTHREFCLK0": { + "src_wire": "GTXE2_CHANNEL_NORTHREFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO0->GTXE2_LOGIC_OUTS_B0_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX36_10->GTXE2_CHANNEL_RXDFETAP3HOLD": { + "src_wire": "GTXE2_IMUX36_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP3HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX15_1->GTXE2_CHANNEL_TX8B10BBYPASS3": { + "src_wire": "GTXE2_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX24_1->GTXE2_CHANNEL_TSTIN10": { + "src_wire": "GTXE2_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX5_10->GTXE2_CHANNEL_RXOUTCLKSEL1": { + "src_wire": "GTXE2_IMUX5_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX20_5->GTXE2_CHANNEL_TXDATA42": { + "src_wire": "GTXE2_IMUX20_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA42", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA28->GTXE2_LOGIC_OUTS_B3_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA28", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX44_5->GTXE2_CHANNEL_TXDLYBYPASS": { + "src_wire": "GTXE2_IMUX44_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYBYPASS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXSTATUS0->GTXE2_LOGIC_OUTS_B21_8": { + "src_wire": "GTXE2_CHANNEL_RXSTATUS0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX17_7->GTXE2_CHANNEL_TXDATA34": { + "src_wire": "GTXE2_IMUX17_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA34", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX37_4->GTXE2_CHANNEL_TXDIFFPD": { + "src_wire": "GTXE2_IMUX37_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL1_1->GTXE2_CHANNEL_RXPHDLYRESET": { + "src_wire": "GTXE2_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHDLYRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX23_1->GTXE2_CHANNEL_TXDATA27": { + "src_wire": "GTXE2_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA27", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO3->GTXE2_LOGIC_OUTS_B6_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX38_8->GTXE2_CHANNEL_RXPRBSSEL1": { + "src_wire": "GTXE2_IMUX38_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX18_9->GTXE2_CHANNEL_RXCHBONDI0": { + "src_wire": "GTXE2_IMUX18_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX41_5->GTXE2_CHANNEL_RESETOVRD": { + "src_wire": "GTXE2_IMUX41_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RESETOVRD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXRATEDONE->GTXE2_LOGIC_OUTS_B20_4": { + "src_wire": "GTXE2_CHANNEL_TXRATEDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX38_10->GTXE2_CHANNEL_PCSRSVDIN22": { + "src_wire": "GTXE2_IMUX38_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX27_7->GTXE2_CHANNEL_RXPOLARITY": { + "src_wire": "GTXE2_IMUX27_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPOLARITY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX9_2->GTXE2_CHANNEL_TXHEADER2": { + "src_wire": "GTXE2_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXHEADER2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA54->GTXE2_LOGIC_OUTS_B4_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA54", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL1_8->GTXE2_CHANNEL_RXCDRRESETRSV": { + "src_wire": "GTXE2_CTRL1_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRRESETRSV", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX11_8->GTXE2_CHANNEL_RXDFEVSEN": { + "src_wire": "GTXE2_IMUX11_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEVSEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX29_6->GTXE2_CHANNEL_TXCHARDISPMODE0": { + "src_wire": "GTXE2_IMUX29_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA30->GTXE2_LOGIC_OUTS_B1_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA30", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX18_10->GTXE2_CHANNEL_RXCHBONDLEVEL0": { + "src_wire": "GTXE2_IMUX18_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX29_10->GTXE2_CHANNEL_RXDFEAGCHOLD": { + "src_wire": "GTXE2_IMUX29_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEAGCHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA17->GTXE2_LOGIC_OUTS_B2_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA17", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX23_2->GTXE2_CHANNEL_TXDATA55": { + "src_wire": "GTXE2_IMUX23_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA55", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXSTATUS1->GTXE2_LOGIC_OUTS_B17_8": { + "src_wire": "GTXE2_CHANNEL_RXSTATUS1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX14_9->GTXE2_CHANNEL_RXPHALIGN": { + "src_wire": "GTXE2_IMUX14_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHALIGN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX4_6->GTXE2_CHANNEL_TXSEQUENCE5": { + "src_wire": "GTXE2_IMUX4_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT5->GTXE2_LOGIC_OUTS_B13_5": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX5_9->GTXE2_CHANNEL_PMARSVDIN0": { + "src_wire": "GTXE2_IMUX5_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX15_7->GTXE2_CHANNEL_TX8B10BBYPASS0": { + "src_wire": "GTXE2_IMUX15_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX46_9->GTXE2_CHANNEL_LOOPBACK1": { + "src_wire": "GTXE2_IMUX46_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_LOOPBACK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX22_10->GTXE2_CHANNEL_RXCHBONDLEVEL2": { + "src_wire": "GTXE2_IMUX22_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX2_4->GTXE2_CHANNEL_TXPOSTCURSOR3": { + "src_wire": "GTXE2_IMUX2_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR1->GTXE2_LOGIC_OUTS_B22_8": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX24_3->GTXE2_CHANNEL_TSTIN12": { + "src_wire": "GTXE2_IMUX24_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX34_8->GTXE2_CHANNEL_RXLPMEN": { + "src_wire": "GTXE2_IMUX34_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX4_5->GTXE2_CHANNEL_TXSEQUENCE1": { + "src_wire": "GTXE2_IMUX4_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL1_10->GTXE2_CHANNEL_RXOOBRESET": { + "src_wire": "GTXE2_CTRL1_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOOBRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX42_9->GTXE2_CHANNEL_GTRSVD6": { + "src_wire": "GTXE2_IMUX42_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT7->GTXE2_LOGIC_OUTS_B13_7": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX3_5->GTXE2_CHANNEL_TXDIFFCTRL2": { + "src_wire": "GTXE2_IMUX3_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK4->GTXE2_LOGIC_OUTS_B12_9": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX11_5->GTXE2_CHANNEL_TXDLYHOLD": { + "src_wire": "GTXE2_IMUX11_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX38_1->GTXE2_CHANNEL_DRPDI5": { + "src_wire": "GTXE2_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX31_1->GTXE2_CHANNEL_TXCHARISK3": { + "src_wire": "GTXE2_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA23->GTXE2_LOGIC_OUTS_B5_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA23", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX20_4->GTXE2_CHANNEL_TXDATA14": { + "src_wire": "GTXE2_IMUX20_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX2_3->GTXE2_CHANNEL_DRPADDR8": { + "src_wire": "GTXE2_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX12_2->GTXE2_CHANNEL_TXHEADER1": { + "src_wire": "GTXE2_IMUX12_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXHEADER1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX28_5->GTXE2_CHANNEL_TXSYSCLKSEL0": { + "src_wire": "GTXE2_IMUX28_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO9->GTXE2_LOGIC_OUTS_B4_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX8_0->GTXE2_CHANNEL_TXCHARDISPVAL3": { + "src_wire": "GTXE2_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXBUFSTATUS1->GTXE2_LOGIC_OUTS_B21_2": { + "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT1->GTXE2_LOGIC_OUTS_B13_1": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX10_5->GTXE2_CHANNEL_TXUSERRDY": { + "src_wire": "GTXE2_IMUX10_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXUSERRDY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX14_7->GTXE2_CHANNEL_RXPCSRESET": { + "src_wire": "GTXE2_IMUX14_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPCSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT1->GTXE2_LOGIC_OUTS_B11_1": { + "src_wire": "GTXE2_CHANNEL_TSTOUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX38_6->GTXE2_CHANNEL_TXPD0": { + "src_wire": "GTXE2_IMUX38_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX8_3->GTXE2_CHANNEL_TX8B10BBYPASS6": { + "src_wire": "GTXE2_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX45_1->GTXE2_CHANNEL_TXQPIWEAKPUP": { + "src_wire": "GTXE2_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXQPIWEAKPUP", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX34_4->GTXE2_CHANNEL_SETERRSTATUS": { + "src_wire": "GTXE2_IMUX34_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_SETERRSTATUS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX22_6->GTXE2_CHANNEL_TXDATA38": { + "src_wire": "GTXE2_IMUX22_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA38", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX10_9->GTXE2_CHANNEL_RXQPIEN": { + "src_wire": "GTXE2_IMUX10_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXQPIEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX5_6->GTXE2_CHANNEL_TXSEQUENCE4": { + "src_wire": "GTXE2_IMUX5_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX18_3->GTXE2_CHANNEL_TXDATA16": { + "src_wire": "GTXE2_IMUX18_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA16", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX30_7->GTXE2_CHANNEL_TXPCSRESET": { + "src_wire": "GTXE2_IMUX30_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPCSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA5->GTXE2_LOGIC_OUTS_B7_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX34_3->GTXE2_CHANNEL_DRPADDR7": { + "src_wire": "GTXE2_IMUX34_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX40_10->GTXE2_CHANNEL_TSTIN9": { + "src_wire": "GTXE2_IMUX40_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO7->GTXE2_LOGIC_OUTS_B3_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX18_7->GTXE2_CHANNEL_TXDATA0": { + "src_wire": "GTXE2_IMUX18_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHSLIPMONITOR4->GTXE2_LOGIC_OUTS_B16_3": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPRDY->GTXE2_LOGIC_OUTS_B20_0": { + "src_wire": "GTXE2_CHANNEL_DRPRDY", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCLKCORCNT1->GTXE2_LOGIC_OUTS_B20_5": { + "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT6->GTXE2_LOGIC_OUTS_B11_6": { + "src_wire": "GTXE2_CHANNEL_TSTOUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT4->GTXE2_LOGIC_OUTS_B13_4": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PHYSTATUS->GTXE2_LOGIC_OUTS_B10_9": { + "src_wire": "GTXE2_CHANNEL_PHYSTATUS", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCOMINITDET->GTXE2_LOGIC_OUTS_B20_7": { + "src_wire": "GTXE2_CHANNEL_RXCOMINITDET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA2->GTXE2_LOGIC_OUTS_B4_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL0_6->GTXE2_CHANNEL_RXDLYSRESET": { + "src_wire": "GTXE2_CTRL0_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXELECIDLE->GTXE2_LOGIC_OUTS_B19_8": { + "src_wire": "GTXE2_CHANNEL_RXELECIDLE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX20_6->GTXE2_CHANNEL_TXDATA6": { + "src_wire": "GTXE2_IMUX20_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX0_8->GTXE2_CHANNEL_PMARSVDIN4": { + "src_wire": "GTXE2_IMUX0_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE1->GTXE2_LOGIC_OUTS_B14_8": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX31_6->GTXE2_CHANNEL_TXCHARDISPMODE4": { + "src_wire": "GTXE2_IMUX31_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX37_1->GTXE2_CHANNEL_DRPDI12": { + "src_wire": "GTXE2_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX25_9->GTXE2_CHANNEL_PCSRSVDIN6": { + "src_wire": "GTXE2_IMUX25_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX13_1->GTXE2_CHANNEL_TXQPISTRONGPDOWN": { + "src_wire": "GTXE2_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL1_9->GTXE2_CHANNEL_RXCDRRESET": { + "src_wire": "GTXE2_CTRL1_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO8->GTXE2_LOGIC_OUTS_B0_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX23_0->GTXE2_CHANNEL_TXDATA63": { + "src_wire": "GTXE2_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA63", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXHEADERVALID->GTXE2_LOGIC_OUTS_B23_7": { + "src_wire": "GTXE2_CHANNEL_RXHEADERVALID", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_CPLLREFCLKLOST->GTXE2_LOGIC_OUTS_B18_1": { + "src_wire": "GTXE2_CHANNEL_CPLLREFCLKLOST", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX18_0->GTXE2_CHANNEL_TXDATA60": { + "src_wire": "GTXE2_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA60", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXBYTEREALIGN->GTXE2_LOGIC_OUTS_B10_10": { + "src_wire": "GTXE2_CHANNEL_RXBYTEREALIGN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B17_9": { + "src_wire": "GTXE2_CHANNEL_RXOUTCLKFABRIC", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX42_4->GTXE2_CHANNEL_GTRSVD1": { + "src_wire": "GTXE2_IMUX42_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXBUFSTATUS2->GTXE2_LOGIC_OUTS_B17_10": { + "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE7->GTXE2_LOGIC_OUTS_B14_3": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT7->GTXE2_LOGIC_OUTS_B9_3": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX17_6->GTXE2_CHANNEL_TXDATA5": { + "src_wire": "GTXE2_IMUX17_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA33->GTXE2_LOGIC_OUTS_B7_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA33", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX13_9->GTXE2_CHANNEL_RXDFETAP5OVRDEN": { + "src_wire": "GTXE2_IMUX13_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL1_6->GTXE2_CHANNEL_RXBUFRESET": { + "src_wire": "GTXE2_CTRL1_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXBUFRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO4->GTXE2_LOGIC_OUTS_B5_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX32_8->GTXE2_CHANNEL_RXDLYBYPASS": { + "src_wire": "GTXE2_IMUX32_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYBYPASS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX25_6->GTXE2_CHANNEL_PCSRSVDIN3": { + "src_wire": "GTXE2_IMUX25_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX29_4->GTXE2_CHANNEL_TXCHARDISPMODE1": { + "src_wire": "GTXE2_IMUX29_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX47_6->GTXE2_CHANNEL_TXRATE0": { + "src_wire": "GTXE2_IMUX47_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXRATE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA47->GTXE2_LOGIC_OUTS_B0_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA47", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_GTRXOUTCLK_1->GTXE2_CHANNEL_RXOUTCLK_1": { + "src_wire": "GTXE2_CHANNEL_GTRXOUTCLK_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX35_10->GTXE2_CHANNEL_PCSRSVDIN21": { + "src_wire": "GTXE2_IMUX35_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TXBUFSTATUS0->GTXE2_LOGIC_OUTS_B17_2": { + "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT5->GTXE2_LOGIC_OUTS_B11_5": { + "src_wire": "GTXE2_CHANNEL_TSTOUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL1_5->GTXE2_CHANNEL_CFGRESET": { + "src_wire": "GTXE2_CTRL1_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CFGRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX12_1->GTXE2_CHANNEL_TXCOMWAKE": { + "src_wire": "GTXE2_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCOMWAKE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX27_10->GTXE2_CHANNEL_RXLPMHFOVRDEN": { + "src_wire": "GTXE2_IMUX27_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMHFOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT0->GTXE2_LOGIC_OUTS_B13_0": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX21_0->GTXE2_CHANNEL_TXDATA31": { + "src_wire": "GTXE2_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA31", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDO3->GTXE2_LOGIC_OUTS_B16_7": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA25->GTXE2_LOGIC_OUTS_B2_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA25", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX9_5->GTXE2_CHANNEL_PCSRSVDIN10": { + "src_wire": "GTXE2_IMUX9_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA56->GTXE2_LOGIC_OUTS_B3_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA56", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA34->GTXE2_LOGIC_OUTS_B1_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA34", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX1_8->GTXE2_CHANNEL_TXOUTCLKSEL2": { + "src_wire": "GTXE2_IMUX1_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX16_5->GTXE2_CHANNEL_TXDATA40": { + "src_wire": "GTXE2_IMUX16_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA40", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX9_6->GTXE2_CHANNEL_PCSRSVDIN11": { + "src_wire": "GTXE2_IMUX9_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX33_0->GTXE2_CHANNEL_DRPDI10": { + "src_wire": "GTXE2_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX19_7->GTXE2_CHANNEL_TXDATA1": { + "src_wire": "GTXE2_IMUX19_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX42_10->GTXE2_CHANNEL_GTRSVD7": { + "src_wire": "GTXE2_IMUX42_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX22_9->GTXE2_CHANNEL_RXCHBONDI2": { + "src_wire": "GTXE2_IMUX22_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX32_2->GTXE2_CHANNEL_TXINHIBIT": { + "src_wire": "GTXE2_IMUX32_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXINHIBIT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX39_2->GTXE2_CHANNEL_DRPADDR0": { + "src_wire": "GTXE2_IMUX39_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX11_6->GTXE2_CHANNEL_RXRATE2": { + "src_wire": "GTXE2_IMUX11_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXRATE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX0_3->GTXE2_CHANNEL_TXMAINCURSOR3": { + "src_wire": "GTXE2_IMUX0_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHANBONDSEQ->GTXE2_LOGIC_OUTS_B10_8": { + "src_wire": "GTXE2_CHANNEL_RXCHANBONDSEQ", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX16_10->GTXE2_CHANNEL_RXDFECM1EN": { + "src_wire": "GTXE2_IMUX16_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFECM1EN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX24_7->GTXE2_CHANNEL_TSTIN16": { + "src_wire": "GTXE2_IMUX24_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN16", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX19_1->GTXE2_CHANNEL_TXDATA25": { + "src_wire": "GTXE2_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA25", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX25_2->GTXE2_CHANNEL_TXPHALIGN": { + "src_wire": "GTXE2_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHALIGN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX20_2->GTXE2_CHANNEL_TXDATA22": { + "src_wire": "GTXE2_IMUX20_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX42_7->GTXE2_CHANNEL_GTRSVD4": { + "src_wire": "GTXE2_IMUX42_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT4->GTXE2_LOGIC_OUTS_B9_6": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX5_8->GTXE2_CHANNEL_TXOUTCLKSEL0": { + "src_wire": "GTXE2_IMUX5_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT6->GTXE2_LOGIC_OUTS_B13_6": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX23_3->GTXE2_CHANNEL_TXDATA19": { + "src_wire": "GTXE2_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA19", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA15->GTXE2_LOGIC_OUTS_B5_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA15", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX38_0->GTXE2_CHANNEL_DRPDI1": { + "src_wire": "GTXE2_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX45_8->GTXE2_CHANNEL_EYESCANRESET": { + "src_wire": "GTXE2_IMUX45_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_EYESCANRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA58->GTXE2_LOGIC_OUTS_B1_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA58", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX31_8->GTXE2_CHANNEL_EYESCANTRIGGER": { + "src_wire": "GTXE2_IMUX31_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_EYESCANTRIGGER", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX42_2->GTXE2_CHANNEL_RXSYSCLKSEL1": { + "src_wire": "GTXE2_IMUX42_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX26_4->GTXE2_CHANNEL_GTRSVD9": { + "src_wire": "GTXE2_IMUX26_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT7->GTXE2_LOGIC_OUTS_B11_7": { + "src_wire": "GTXE2_CHANNEL_TSTOUT7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX40_9->GTXE2_CHANNEL_TSTIN8": { + "src_wire": "GTXE2_IMUX40_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CLK1_5->GTXE2_CHANNEL_CLKRSVD1": { + "src_wire": "GTXE2_CLK1_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CTRL0_8->GTXE2_CHANNEL_GTRXRESET": { + "src_wire": "GTXE2_CTRL0_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRXRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO5->GTXE2_LOGIC_OUTS_B1_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_IMUX4_7->GTXE2_CHANNEL_PMARSVDIN21": { + "src_wire": "GTXE2_IMUX4_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXVALID->GTXE2_LOGIC_OUTS_B20_9": { + "src_wire": "GTXE2_CHANNEL_RXVALID", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA32->GTXE2_LOGIC_OUTS_B3_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA32", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_10", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_GTX_CHANNEL_2.json b/kintex7/tile_type_GTX_CHANNEL_2.json new file mode 100644 index 0000000..7c103ea --- /dev/null +++ b/kintex7/tile_type_GTX_CHANNEL_2.json @@ -0,0 +1,6854 @@ +{ + "tile_type": "GTX_CHANNEL_2", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "GTXE2_CHANNEL", + "type": "GTXE2_CHANNEL", + "site_pins": { + "RXQPIEN": "GTXE2_CHANNEL_RXQPIEN", + "TXDATA47": "GTXE2_CHANNEL_TXDATA47", + "RXDATA59": "GTXE2_CHANNEL_RXDATA59", + "TXDATA19": "GTXE2_CHANNEL_TXDATA19", + "RXDISPERR3": "GTXE2_CHANNEL_RXDISPERR3", + "RXBUFSTATUS1": "GTXE2_CHANNEL_RXBUFSTATUS1", + "TXCHARDISPMODE5": "GTXE2_CHANNEL_TXCHARDISPMODE5", + "TXCHARDISPMODE3": "GTXE2_CHANNEL_TXCHARDISPMODE3", + "RXDATA47": "GTXE2_CHANNEL_RXDATA47", + "TXDATA24": "GTXE2_CHANNEL_TXDATA24", + "TXHEADER1": "GTXE2_CHANNEL_TXHEADER1", + "TSTIN17": "GTXE2_CHANNEL_TSTIN17", + "TXPHALIGN": "GTXE2_CHANNEL_TXPHALIGN", + "CLKRSVD3": "GTXE2_CHANNEL_CLKRSVD3", + "PCSRSVDIN20": "GTXE2_CHANNEL_PCSRSVDIN20", + "RXDATA25": "GTXE2_CHANNEL_RXDATA25", + "DRPDO9": "GTXE2_CHANNEL_DRPDO9", + "RXDATA20": "GTXE2_CHANNEL_RXDATA20", + "GTRSVD4": "GTXE2_CHANNEL_GTRSVD4", + "TXCOMSAS": "GTXE2_CHANNEL_TXCOMSAS", + "PMASCANCLK2": "GTXE2_CHANNEL_PMASCANCLK2", + "RXBYTEISALIGNED": "GTXE2_CHANNEL_RXBYTEISALIGNED", + "RXPRBSSEL2": "GTXE2_CHANNEL_RXPRBSSEL2", + "TXDATA43": "GTXE2_CHANNEL_TXDATA43", + "RXDATA38": "GTXE2_CHANNEL_RXDATA38", + "RXOUTCLKFABRIC": "GTXE2_CHANNEL_RXOUTCLKFABRIC", + "TSTOUT8": "GTXE2_CHANNEL_TSTOUT8", + "RESETOVRD": "GTXE2_CHANNEL_RESETOVRD", + "GTREFCLK1": "GTXE2_CHANNEL_GTREFCLK1", + "TXSTARTSEQ": "GTXE2_CHANNEL_TXSTARTSEQ", + "RXDATA7": "GTXE2_CHANNEL_RXDATA7", + "RX8B10BEN": "GTXE2_CHANNEL_RX8B10BEN", + "PCSRSVDOUT8": "GTXE2_CHANNEL_PCSRSVDOUT8", + "TXDLYSRESETDONE": "GTXE2_CHANNEL_TXDLYSRESETDONE", + "RXMONITOROUT4": "GTXE2_CHANNEL_RXMONITOROUT4", + "RXOUTCLKSEL1": "GTXE2_CHANNEL_RXOUTCLKSEL1", + "TXPOSTCURSOR0": "GTXE2_CHANNEL_TXPOSTCURSOR0", + "RXCHARISK4": "GTXE2_CHANNEL_RXCHARISK4", + "PCSRSVDOUT11": "GTXE2_CHANNEL_PCSRSVDOUT11", + "SCANENB": "GTXE2_CHANNEL_SCANENB", + "TXCHARDISPMODE1": "GTXE2_CHANNEL_TXCHARDISPMODE1", + "RXDLYTESTENB": "GTXE2_CHANNEL_RXDLYTESTENB", + "RXPCOMMAALIGNEN": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", + "TXPRECURSOR1": "GTXE2_CHANNEL_TXPRECURSOR1", + "RXCHBONDLEVEL1": "GTXE2_CHANNEL_RXCHBONDLEVEL1", + "RXPD0": "GTXE2_CHANNEL_RXPD0", + "DRPDI15": "GTXE2_CHANNEL_DRPDI15", + "TXPOSTCURSORINV": "GTXE2_CHANNEL_TXPOSTCURSORINV", + "GTRSVD7": "GTXE2_CHANNEL_GTRSVD7", + "PMASCANMODEB": "GTXE2_CHANNEL_PMASCANMODEB", + "RXMONITOROUT0": "GTXE2_CHANNEL_RXMONITOROUT0", + "RXRATEDONE": "GTXE2_CHANNEL_RXRATEDONE", + "PMASCANOUT2": "GTXE2_CHANNEL_PMASCANOUT2", + "RXDFETAP4OVRDEN": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", + "RXDATA16": "GTXE2_CHANNEL_RXDATA16", + "TXCHARDISPMODE7": "GTXE2_CHANNEL_TXCHARDISPMODE7", + "RXDATA49": "GTXE2_CHANNEL_RXDATA49", + "SETERRSTATUS": "GTXE2_CHANNEL_SETERRSTATUS", + "TXDLYSRESET": "GTXE2_CHANNEL_TXDLYSRESET", + "TXDATA1": "GTXE2_CHANNEL_TXDATA1", + "TX8B10BBYPASS4": "GTXE2_CHANNEL_TX8B10BBYPASS4", + "PMARSVDIN20": "GTXE2_CHANNEL_PMARSVDIN20", + "TSTOUT0": "GTXE2_CHANNEL_TSTOUT0", + "RXPHDLYRESET": "GTXE2_CHANNEL_RXPHDLYRESET", + "TXDATA30": "GTXE2_CHANNEL_TXDATA30", + "DRPDI12": "GTXE2_CHANNEL_DRPDI12", + "TXRUNDISP4": "GTXE2_CHANNEL_TXRUNDISP4", + "CLKRSVD2": "GTXE2_CHANNEL_CLKRSVD2", + "PCSRSVDIN12": "GTXE2_CHANNEL_PCSRSVDIN12", + "TXCHARDISPMODE0": "GTXE2_CHANNEL_TXCHARDISPMODE0", + "TXDATA51": "GTXE2_CHANNEL_TXDATA51", + "RXMONITOROUT6": "GTXE2_CHANNEL_RXMONITOROUT6", + "CPLLREFCLKLOST": "GTXE2_CHANNEL_CPLLREFCLKLOST", + "SCANOUT2": "GTXE2_CHANNEL_SCANOUT2", + "RXDATA62": "GTXE2_CHANNEL_RXDATA62", + "DRPDI5": "GTXE2_CHANNEL_DRPDI5", + "RXRESETDONE": "GTXE2_CHANNEL_RXRESETDONE", + "TSTCLK0": "GTXE2_CHANNEL_TSTCLK0", + "DRPDO5": "GTXE2_CHANNEL_DRPDO5", + "PCSRSVDIN10": "GTXE2_CHANNEL_PCSRSVDIN10", + "RXCDRHOLD": "GTXE2_CHANNEL_RXCDRHOLD", + "PCSRSVDIN24": "GTXE2_CHANNEL_PCSRSVDIN24", + "TXDIFFCTRL0": "GTXE2_CHANNEL_TXDIFFCTRL0", + "RXMONITOROUT3": "GTXE2_CHANNEL_RXMONITOROUT3", + "TSTIN2": "GTXE2_CHANNEL_TSTIN2", + "RXRATE1": "GTXE2_CHANNEL_RXRATE1", + "PMARSVDIN0": "GTXE2_CHANNEL_PMARSVDIN0", + "RXDFELFHOLD": "GTXE2_CHANNEL_RXDFELFHOLD", + "RXDFEVPHOLD": "GTXE2_CHANNEL_RXDFEVPHOLD", + "RXDATA26": "GTXE2_CHANNEL_RXDATA26", + "TXPRBSSEL2": "GTXE2_CHANNEL_TXPRBSSEL2", + "TXDATA20": "GTXE2_CHANNEL_TXDATA20", + "TXDATA18": "GTXE2_CHANNEL_TXDATA18", + "TXCHARISK7": "GTXE2_CHANNEL_TXCHARISK7", + "LOOPBACK0": "GTXE2_CHANNEL_LOOPBACK0", + "TXPHDLYPD": "GTXE2_CHANNEL_TXPHDLYPD", + "TXPRECURSOR3": "GTXE2_CHANNEL_TXPRECURSOR3", + "DRPDO11": "GTXE2_CHANNEL_DRPDO11", + "GTXRXP": "GTXE2_CHANNEL_RXP", + "TXCHARDISPVAL7": "GTXE2_CHANNEL_TXCHARDISPVAL7", + "RXCHANBONDSEQ": "GTXE2_CHANNEL_RXCHANBONDSEQ", + "DRPDI6": "GTXE2_CHANNEL_DRPDI6", + "TXDATA48": "GTXE2_CHANNEL_TXDATA48", + "CPLLFBCLKLOST": "GTXE2_CHANNEL_CPLLFBCLKLOST", + "RXDATA55": "GTXE2_CHANNEL_RXDATA55", + "TSTIN10": "GTXE2_CHANNEL_TSTIN10", + "RXDATA60": "GTXE2_CHANNEL_RXDATA60", + "RXDATA11": "GTXE2_CHANNEL_RXDATA11", + "SCANIN1": "GTXE2_CHANNEL_SCANIN1", + "DRPDO3": "GTXE2_CHANNEL_DRPDO3", + "TXDATA8": "GTXE2_CHANNEL_TXDATA8", + "RXCHBONDEN": "GTXE2_CHANNEL_RXCHBONDEN", + "PMASCANOUT1": "GTXE2_CHANNEL_PMASCANOUT1", + "DMONITOROUT4": "GTXE2_CHANNEL_DMONITOROUT4", + "SCANOUT3": "GTXE2_CHANNEL_SCANOUT3", + "RXDATA57": "GTXE2_CHANNEL_RXDATA57", + "TXDATA25": "GTXE2_CHANNEL_TXDATA25", + "RXDFEUTOVRDEN": "GTXE2_CHANNEL_RXDFEUTOVRDEN", + "PMASCANIN3": "GTXE2_CHANNEL_PMASCANIN3", + "TXPISOPD": "GTXE2_CHANNEL_TXPISOPD", + "TXCHARDISPMODE6": "GTXE2_CHANNEL_TXCHARDISPMODE6", + "RXCDRFREQRESET": "GTXE2_CHANNEL_RXCDRFREQRESET", + "TXCHARDISPVAL4": "GTXE2_CHANNEL_TXCHARDISPVAL4", + "GTSOUTHREFCLK0": "GTXE2_CHANNEL_GTSOUTHREFCLK0", + "TXCHARDISPVAL5": "GTXE2_CHANNEL_TXCHARDISPVAL5", + "GTXRXN": "GTXE2_CHANNEL_RXN", + "TXDATA53": "GTXE2_CHANNEL_TXDATA53", + "RXPHDLYPD": "GTXE2_CHANNEL_RXPHDLYPD", + "TSTPD2": "GTXE2_CHANNEL_TSTPD2", + "RXCHBONDO1": "GTXE2_CHANNEL_RXCHBONDO1", + "RXBUFSTATUS0": "GTXE2_CHANNEL_RXBUFSTATUS0", + "TXDATA13": "GTXE2_CHANNEL_TXDATA13", + "PMASCANOUT0": "GTXE2_CHANNEL_PMASCANOUT0", + "RXCHARISCOMMA2": "GTXE2_CHANNEL_RXCHARISCOMMA2", + "TXOUTCLKPCS": "GTXE2_CHANNEL_TXOUTCLKPCS", + "PCSRSVDOUT14": "GTXE2_CHANNEL_PCSRSVDOUT14", + "RXDATA24": "GTXE2_CHANNEL_RXDATA24", + "RXDATA37": "GTXE2_CHANNEL_RXDATA37", + "TX8B10BBYPASS1": "GTXE2_CHANNEL_TX8B10BBYPASS1", + "DRPDI9": "GTXE2_CHANNEL_DRPDI9", + "TXCHARDISPMODE2": "GTXE2_CHANNEL_TXCHARDISPMODE2", + "TXOUTCLKSEL1": "GTXE2_CHANNEL_TXOUTCLKSEL1", + "RXCHBONDMASTER": "GTXE2_CHANNEL_RXCHBONDMASTER", + "TXDATA28": "GTXE2_CHANNEL_TXDATA28", + "RXDATA34": "GTXE2_CHANNEL_RXDATA34", + "CFGRESET": "GTXE2_CHANNEL_CFGRESET", + "RXDFEVPOVRDEN": "GTXE2_CHANNEL_RXDFEVPOVRDEN", + "TXDATA29": "GTXE2_CHANNEL_TXDATA29", + "GTRESETSEL": "GTXE2_CHANNEL_GTRESETSEL", + "EDTCONFIGURATION": "GTXE2_CHANNEL_EDTCONFIGURATION", + "TXCHARISK4": "GTXE2_CHANNEL_TXCHARISK4", + "TXQPISENP": "GTXE2_CHANNEL_TXQPISENP", + "RXCHBONDLEVEL0": "GTXE2_CHANNEL_RXCHBONDLEVEL0", + "PCSRSVDIN8": "GTXE2_CHANNEL_PCSRSVDIN8", + "PMASCANIN0": "GTXE2_CHANNEL_PMASCANIN0", + "DRPDO4": "GTXE2_CHANNEL_DRPDO4", + "RXDATA14": "GTXE2_CHANNEL_RXDATA14", + "TSTOUT5": "GTXE2_CHANNEL_TSTOUT5", + "EDTCLOCK": "GTXE2_CHANNEL_EDTCLOCK", + "QPLLREFCLK": "GTXE2_CHANNEL_GTQPLLREFCLK", + "RXDATA39": "GTXE2_CHANNEL_RXDATA39", + "RXLPMEN": "GTXE2_CHANNEL_RXLPMEN", + "EDTUPDATE": "GTXE2_CHANNEL_EDTUPDATE", + "TXSWING": "GTXE2_CHANNEL_TXSWING", + "TXRATE0": "GTXE2_CHANNEL_TXRATE0", + "RXDATA9": "GTXE2_CHANNEL_RXDATA9", + "TXRUNDISP5": "GTXE2_CHANNEL_TXRUNDISP5", + "RXMCOMMAALIGNEN": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", + "SCANIN2": "GTXE2_CHANNEL_SCANIN2", + "TXPOLARITY": "GTXE2_CHANNEL_TXPOLARITY", + "RXDATA32": "GTXE2_CHANNEL_RXDATA32", + "DRPDO2": "GTXE2_CHANNEL_DRPDO2", + "TXPOSTCURSOR3": "GTXE2_CHANNEL_TXPOSTCURSOR3", + "TXDLYTESTENB": "GTXE2_CHANNEL_TXDLYTESTENB", + "RXLPMLFKLOVRDEN": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", + "RXRATE2": "GTXE2_CHANNEL_RXRATE2", + "RXDFECM1EN": "GTXE2_CHANNEL_RXDFECM1EN", + "RXCDRRESETRSV": "GTXE2_CHANNEL_RXCDRRESETRSV", + "SCANCLK": "GTXE2_CHANNEL_SCANCLK", + "TSTIN6": "GTXE2_CHANNEL_TSTIN6", + "TXDLYHOLD": "GTXE2_CHANNEL_TXDLYHOLD", + "RXCHANREALIGN": "GTXE2_CHANNEL_RXCHANREALIGN", + "RXCHBONDO4": "GTXE2_CHANNEL_RXCHBONDO4", + "TXRUNDISP1": "GTXE2_CHANNEL_TXRUNDISP1", + "TXDATA23": "GTXE2_CHANNEL_TXDATA23", + "TXDATA21": "GTXE2_CHANNEL_TXDATA21", + "RXNOTINTABLE7": "GTXE2_CHANNEL_RXNOTINTABLE7", + "RXDATA29": "GTXE2_CHANNEL_RXDATA29", + "TXDATA37": "GTXE2_CHANNEL_TXDATA37", + "DMONITOROUT1": "GTXE2_CHANNEL_DMONITOROUT1", + "PMASCANCLK4": "GTXE2_CHANNEL_PMASCANCLK4", + "PCSRSVDOUT9": "GTXE2_CHANNEL_PCSRSVDOUT9", + "TXPHDLYTSTCLK": "GTXE2_CHANNEL_TXPHDLYTSTCLK", + "TXUSRCLK2": "GTXE2_CHANNEL_TXUSRCLK2", + "DRPDO15": "GTXE2_CHANNEL_DRPDO15", + "TXOUTCLKSEL2": "GTXE2_CHANNEL_TXOUTCLKSEL2", + "TX8B10BBYPASS2": "GTXE2_CHANNEL_TX8B10BBYPASS2", + "CPLLLOCKEN": "GTXE2_CHANNEL_CPLLLOCKEN", + "DRPDI4": "GTXE2_CHANNEL_DRPDI4", + "TXDATA42": "GTXE2_CHANNEL_TXDATA42", + "RXHEADERVALID": "GTXE2_CHANNEL_RXHEADERVALID", + "RXDISPERR2": "GTXE2_CHANNEL_RXDISPERR2", + "RXCHBONDI0": "GTXE2_CHANNEL_RXCHBONDI0", + "TXBUFSTATUS1": "GTXE2_CHANNEL_TXBUFSTATUS1", + "PCSRSVDOUT5": "GTXE2_CHANNEL_PCSRSVDOUT5", + "RXPRBSSEL1": "GTXE2_CHANNEL_RXPRBSSEL1", + "RXDATA2": "GTXE2_CHANNEL_RXDATA2", + "RXDATA18": "GTXE2_CHANNEL_RXDATA18", + "TXOUTCLKFABRIC": "GTXE2_CHANNEL_TXOUTCLKFABRIC", + "PMARSVDIN24": "GTXE2_CHANNEL_PMARSVDIN24", + "TXQPISENN": "GTXE2_CHANNEL_TXQPISENN", + "RXQPISENN": "GTXE2_CHANNEL_RXQPISENN", + "TSTOUT4": "GTXE2_CHANNEL_TSTOUT4", + "TXDATA22": "GTXE2_CHANNEL_TXDATA22", + "DRPWE": "GTXE2_CHANNEL_DRPWE", + "RXCHANISALIGNED": "GTXE2_CHANNEL_RXCHANISALIGNED", + "TXPHOVRDEN": "GTXE2_CHANNEL_TXPHOVRDEN", + "RXDATA54": "GTXE2_CHANNEL_RXDATA54", + "TX8B10BBYPASS6": "GTXE2_CHANNEL_TX8B10BBYPASS6", + "TXDIFFCTRL2": "GTXE2_CHANNEL_TXDIFFCTRL2", + "TXINHIBIT": "GTXE2_CHANNEL_TXINHIBIT", + "TSTIN8": "GTXE2_CHANNEL_TSTIN8", + "TSTIN3": "GTXE2_CHANNEL_TSTIN3", + "TXDATA35": "GTXE2_CHANNEL_TXDATA35", + "TXHEADER0": "GTXE2_CHANNEL_TXHEADER0", + "RXDATA8": "GTXE2_CHANNEL_RXDATA8", + "SCANIN0": "GTXE2_CHANNEL_SCANIN0", + "TXPCSRESET": "GTXE2_CHANNEL_TXPCSRESET", + "TXPOSTCURSOR4": "GTXE2_CHANNEL_TXPOSTCURSOR4", + "RXCHARISK2": "GTXE2_CHANNEL_RXCHARISK2", + "RXDLYBYPASS": "GTXE2_CHANNEL_RXDLYBYPASS", + "PCSRSVDIN14": "GTXE2_CHANNEL_PCSRSVDIN14", + "TXPRECURSORINV": "GTXE2_CHANNEL_TXPRECURSORINV", + "RXDATA40": "GTXE2_CHANNEL_RXDATA40", + "TXCHARDISPVAL2": "GTXE2_CHANNEL_TXCHARDISPVAL2", + "TX8B10BBYPASS3": "GTXE2_CHANNEL_TX8B10BBYPASS3", + "PCSRSVDOUT2": "GTXE2_CHANNEL_PCSRSVDOUT2", + "TXDATA45": "GTXE2_CHANNEL_TXDATA45", + "RXHEADER2": "GTXE2_CHANNEL_RXHEADER2", + "EYESCANTRIGGER": "GTXE2_CHANNEL_EYESCANTRIGGER", + "RXDATA53": "GTXE2_CHANNEL_RXDATA53", + "TXMAINCURSOR0": "GTXE2_CHANNEL_TXMAINCURSOR0", + "PMARSVDIN23": "GTXE2_CHANNEL_PMARSVDIN23", + "RXDATA10": "GTXE2_CHANNEL_RXDATA10", + "DRPDI10": "GTXE2_CHANNEL_DRPDI10", + "RXDATA58": "GTXE2_CHANNEL_RXDATA58", + "CPLLREFCLKSEL0": "GTXE2_CHANNEL_CPLLREFCLKSEL0", + "DMONITOROUT0": "GTXE2_CHANNEL_DMONITOROUT0", + "PCSRSVDIN2": "GTXE2_CHANNEL_PCSRSVDIN2", + "RXDLYEN": "GTXE2_CHANNEL_RXDLYEN", + "EYESCANMODE": "GTXE2_CHANNEL_EYESCANMODE", + "PMASCANOUT4": "GTXE2_CHANNEL_PMASCANOUT4", + "RXBYTEREALIGN": "GTXE2_CHANNEL_RXBYTEREALIGN", + "RXCOMWAKEDET": "GTXE2_CHANNEL_RXCOMWAKEDET", + "TSTOUT2": "GTXE2_CHANNEL_TSTOUT2", + "RXPRBSSEL0": "GTXE2_CHANNEL_RXPRBSSEL0", + "TXSEQUENCE6": "GTXE2_CHANNEL_TXSEQUENCE6", + "TSTIN14": "GTXE2_CHANNEL_TSTIN14", + "CPLLRESET": "GTXE2_CHANNEL_CPLLRESET", + "RXCHARISK1": "GTXE2_CHANNEL_RXCHARISK1", + "GTSOUTHREFCLK1": "GTXE2_CHANNEL_GTSOUTHREFCLK1", + "RXDATA3": "GTXE2_CHANNEL_RXDATA3", + "TXPRBSSEL0": "GTXE2_CHANNEL_TXPRBSSEL0", + "SCANIN4": "GTXE2_CHANNEL_SCANIN4", + "RXDATA36": "GTXE2_CHANNEL_RXDATA36", + "TXGEARBOXREADY": "GTXE2_CHANNEL_TXGEARBOXREADY", + "TXRESETDONE": "GTXE2_CHANNEL_TXRESETDONE", + "DRPDO12": "GTXE2_CHANNEL_DRPDO12", + "PCSRSVDOUT12": "GTXE2_CHANNEL_PCSRSVDOUT12", + "GTNORTHREFCLK0": "GTXE2_CHANNEL_GTNORTHREFCLK0", + "RXPMARESET": "GTXE2_CHANNEL_RXPMARESET", + "TXSYSCLKSEL0": "GTXE2_CHANNEL_TXSYSCLKSEL0", + "TSTIN7": "GTXE2_CHANNEL_TSTIN7", + "DMONITOROUT3": "GTXE2_CHANNEL_DMONITOROUT3", + "PCSRSVDIN9": "GTXE2_CHANNEL_PCSRSVDIN9", + "TXCOMINIT": "GTXE2_CHANNEL_TXCOMINIT", + "TXPD1": "GTXE2_CHANNEL_TXPD1", + "RXCHARISCOMMA7": "GTXE2_CHANNEL_RXCHARISCOMMA7", + "RXMONITORSEL0": "GTXE2_CHANNEL_RXMONITORSEL0", + "RXOUTCLKPCS": "GTXE2_CHANNEL_RXOUTCLKPCS", + "RXMONITOROUT2": "GTXE2_CHANNEL_RXMONITOROUT2", + "RXPHSLIPMONITOR1": "GTXE2_CHANNEL_RXPHSLIPMONITOR1", + "SCANIN3": "GTXE2_CHANNEL_SCANIN3", + "DRPADDR6": "GTXE2_CHANNEL_DRPADDR6", + "RXCHARISK6": "GTXE2_CHANNEL_RXCHARISK6", + "RXLPMHFOVRDEN": "GTXE2_CHANNEL_RXLPMHFOVRDEN", + "RXDLYOVRDEN": "GTXE2_CHANNEL_RXDLYOVRDEN", + "LOOPBACK2": "GTXE2_CHANNEL_LOOPBACK2", + "PCSRSVDIN11": "GTXE2_CHANNEL_PCSRSVDIN11", + "DRPCLK": "GTXE2_CHANNEL_DRPCLK", + "TXMAINCURSOR1": "GTXE2_CHANNEL_TXMAINCURSOR1", + "RXSLIDE": "GTXE2_CHANNEL_RXSLIDE", + "TXUSERRDY": "GTXE2_CHANNEL_TXUSERRDY", + "RXMONITOROUT5": "GTXE2_CHANNEL_RXMONITOROUT5", + "TX8B10BBYPASS5": "GTXE2_CHANNEL_TX8B10BBYPASS5", + "RXPCSRESET": "GTXE2_CHANNEL_RXPCSRESET", + "TXDATA26": "GTXE2_CHANNEL_TXDATA26", + "TXELECIDLE": "GTXE2_CHANNEL_TXELECIDLE", + "DRPADDR8": "GTXE2_CHANNEL_DRPADDR8", + "RXPOLARITY": "GTXE2_CHANNEL_RXPOLARITY", + "TXCHARDISPVAL6": "GTXE2_CHANNEL_TXCHARDISPVAL6", + "RXDATA35": "GTXE2_CHANNEL_RXDATA35", + "TSTPDOVRDB": "GTXE2_CHANNEL_TSTPDOVRDB", + "RXCHARISCOMMA4": "GTXE2_CHANNEL_RXCHARISCOMMA4", + "RXLPMLFHOLD": "GTXE2_CHANNEL_RXLPMLFHOLD", + "DRPDI3": "GTXE2_CHANNEL_DRPDI3", + "TXPOSTCURSOR1": "GTXE2_CHANNEL_TXPOSTCURSOR1", + "RXDATA50": "GTXE2_CHANNEL_RXDATA50", + "TXSEQUENCE5": "GTXE2_CHANNEL_TXSEQUENCE5", + "RXOUTCLK": "GTXE2_CHANNEL_GTRXOUTCLK_2", + "GTRSVD3": "GTXE2_CHANNEL_GTRSVD3", + "RXPHMONITOR3": "GTXE2_CHANNEL_RXPHMONITOR3", + "RXNOTINTABLE2": "GTXE2_CHANNEL_RXNOTINTABLE2", + "RXPHOVRDEN": "GTXE2_CHANNEL_RXPHOVRDEN", + "EYESCANRESET": "GTXE2_CHANNEL_EYESCANRESET", + "RXNOTINTABLE0": "GTXE2_CHANNEL_RXNOTINTABLE0", + "TXMARGIN2": "GTXE2_CHANNEL_TXMARGIN2", + "RXDFETAP3HOLD": "GTXE2_CHANNEL_RXDFETAP3HOLD", + "PCSRSVDIN15": "GTXE2_CHANNEL_PCSRSVDIN15", + "TXDATA38": "GTXE2_CHANNEL_TXDATA38", + "TXSEQUENCE2": "GTXE2_CHANNEL_TXSEQUENCE2", + "DRPADDR0": "GTXE2_CHANNEL_DRPADDR0", + "RXOSOVRDEN": "GTXE2_CHANNEL_RXOSOVRDEN", + "TXPHALIGNDONE": "GTXE2_CHANNEL_TXPHALIGNDONE", + "TXCHARISK3": "GTXE2_CHANNEL_TXCHARISK3", + "TSTPD0": "GTXE2_CHANNEL_TSTPD0", + "PCSRSVDOUT6": "GTXE2_CHANNEL_PCSRSVDOUT6", + "TXBUFDIFFCTRL2": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", + "TXMAINCURSOR4": "GTXE2_CHANNEL_TXMAINCURSOR4", + "RXCHARISCOMMA6": "GTXE2_CHANNEL_RXCHARISCOMMA6", + "RXDFETAP2HOLD": "GTXE2_CHANNEL_RXDFETAP2HOLD", + "RXSTATUS2": "GTXE2_CHANNEL_RXSTATUS2", + "TXRUNDISP3": "GTXE2_CHANNEL_TXRUNDISP3", + "RXDATA48": "GTXE2_CHANNEL_RXDATA48", + "TXDATA5": "GTXE2_CHANNEL_TXDATA5", + "DMONITOROUT5": "GTXE2_CHANNEL_DMONITOROUT5", + "RXCHARISCOMMA0": "GTXE2_CHANNEL_RXCHARISCOMMA0", + "TXDATA63": "GTXE2_CHANNEL_TXDATA63", + "DMONITOROUT6": "GTXE2_CHANNEL_DMONITOROUT6", + "RXELECIDLE": "GTXE2_CHANNEL_RXELECIDLE", + "RXGEARBOXSLIP": "GTXE2_CHANNEL_RXGEARBOXSLIP", + "GTRSVD13": "GTXE2_CHANNEL_GTRSVD13", + "RXMONITORSEL1": "GTXE2_CHANNEL_RXMONITORSEL1", + "RXPHMONITOR4": "GTXE2_CHANNEL_RXPHMONITOR4", + "RXDATA44": "GTXE2_CHANNEL_RXDATA44", + "SCANOUT0": "GTXE2_CHANNEL_SCANOUT0", + "PHYSTATUS": "GTXE2_CHANNEL_PHYSTATUS", + "TXRUNDISP6": "GTXE2_CHANNEL_TXRUNDISP6", + "GTRSVD14": "GTXE2_CHANNEL_GTRSVD14", + "RXDFETAP5OVRDEN": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", + "RXDATA56": "GTXE2_CHANNEL_RXDATA56", + "RXCOMSASDET": "GTXE2_CHANNEL_RXCOMSASDET", + "TXQPIBIASEN": "GTXE2_CHANNEL_TXQPIBIASEN", + "RXCHBONDLEVEL2": "GTXE2_CHANNEL_RXCHBONDLEVEL2", + "RXDATA41": "GTXE2_CHANNEL_RXDATA41", + "RXDATA33": "GTXE2_CHANNEL_RXDATA33", + "RXDATA61": "GTXE2_CHANNEL_RXDATA61", + "RXDATA1": "GTXE2_CHANNEL_RXDATA1", + "RXMONITOROUT1": "GTXE2_CHANNEL_RXMONITOROUT1", + "TXPHALIGNEN": "GTXE2_CHANNEL_TXPHALIGNEN", + "GTRSVD0": "GTXE2_CHANNEL_GTRSVD0", + "RXDISPERR1": "GTXE2_CHANNEL_RXDISPERR1", + "TXDATA56": "GTXE2_CHANNEL_TXDATA56", + "TXDIFFCTRL3": "GTXE2_CHANNEL_TXDIFFCTRL3", + "DRPADDR1": "GTXE2_CHANNEL_DRPADDR1", + "TXCHARISK0": "GTXE2_CHANNEL_TXCHARISK0", + "PCSRSVDOUT10": "GTXE2_CHANNEL_PCSRSVDOUT10", + "CPLLLOCK": "GTXE2_CHANNEL_CPLLLOCK", + "TXBUFSTATUS0": "GTXE2_CHANNEL_TXBUFSTATUS0", + "RXCHARISK7": "GTXE2_CHANNEL_RXCHARISK7", + "RXNOTINTABLE6": "GTXE2_CHANNEL_RXNOTINTABLE6", + "DRPEN": "GTXE2_CHANNEL_DRPEN", + "TXBUFDIFFCTRL0": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", + "TXDATA62": "GTXE2_CHANNEL_TXDATA62", + "TXBUFDIFFCTRL1": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", + "SCANOUT4": "GTXE2_CHANNEL_SCANOUT4", + "DRPDO6": "GTXE2_CHANNEL_DRPDO6", + "DRPADDR7": "GTXE2_CHANNEL_DRPADDR7", + "RXSTATUS1": "GTXE2_CHANNEL_RXSTATUS1", + "RXDISPERR5": "GTXE2_CHANNEL_RXDISPERR5", + "RXVALID": "GTXE2_CHANNEL_RXVALID", + "DRPDI2": "GTXE2_CHANNEL_DRPDI2", + "GTRSVD9": "GTXE2_CHANNEL_GTRSVD9", + "TXDATA60": "GTXE2_CHANNEL_TXDATA60", + "TXDLYUPDOWN": "GTXE2_CHANNEL_TXDLYUPDOWN", + "RXDFETAP3OVRDEN": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", + "RXCOMINITDET": "GTXE2_CHANNEL_RXCOMINITDET", + "RXOUTCLKSEL0": "GTXE2_CHANNEL_RXOUTCLKSEL0", + "TXDATA11": "GTXE2_CHANNEL_TXDATA11", + "RXSYSCLKSEL1": "GTXE2_CHANNEL_RXSYSCLKSEL1", + "RXSTATUS0": "GTXE2_CHANNEL_RXSTATUS0", + "TXDATA52": "GTXE2_CHANNEL_TXDATA52", + "RXDATA46": "GTXE2_CHANNEL_RXDATA46", + "RXOSHOLD": "GTXE2_CHANNEL_RXOSHOLD", + "RXCOMMADET": "GTXE2_CHANNEL_RXCOMMADET", + "RXCHBONDO3": "GTXE2_CHANNEL_RXCHBONDO3", + "RXDATA31": "GTXE2_CHANNEL_RXDATA31", + "RXUSERRDY": "GTXE2_CHANNEL_RXUSERRDY", + "RXCHBONDSLAVE": "GTXE2_CHANNEL_RXCHBONDSLAVE", + "RXCHBONDI2": "GTXE2_CHANNEL_RXCHBONDI2", + "PCSRSVDIN0": "GTXE2_CHANNEL_PCSRSVDIN0", + "TXDATA10": "GTXE2_CHANNEL_TXDATA10", + "TXCHARISK5": "GTXE2_CHANNEL_TXCHARISK5", + "RXPHMONITOR1": "GTXE2_CHANNEL_RXPHMONITOR1", + "TXDATA33": "GTXE2_CHANNEL_TXDATA33", + "TSTIN0": "GTXE2_CHANNEL_TSTIN0", + "TX8B10BEN": "GTXE2_CHANNEL_TX8B10BEN", + "PMASCANOUT3": "GTXE2_CHANNEL_PMASCANOUT3", + "RXDATA45": "GTXE2_CHANNEL_RXDATA45", + "GTREFCLKMONITOR": "GTXE2_CHANNEL_GTREFCLKMONITOR", + "PCSRSVDIN7": "GTXE2_CHANNEL_PCSRSVDIN7", + "TXCHARISK1": "GTXE2_CHANNEL_TXCHARISK1", + "TXRUNDISP0": "GTXE2_CHANNEL_TXRUNDISP0", + "RXDATA52": "GTXE2_CHANNEL_RXDATA52", + "RXPD1": "GTXE2_CHANNEL_RXPD1", + "TXDLYOVRDEN": "GTXE2_CHANNEL_TXDLYOVRDEN", + "TXDATA36": "GTXE2_CHANNEL_TXDATA36", + "RXPHSLIPMONITOR2": "GTXE2_CHANNEL_RXPHSLIPMONITOR2", + "TXMARGIN0": "GTXE2_CHANNEL_TXMARGIN0", + "TXDATA34": "GTXE2_CHANNEL_TXDATA34", + "TXSEQUENCE1": "GTXE2_CHANNEL_TXSEQUENCE1", + "RXCLKCORCNT0": "GTXE2_CHANNEL_RXCLKCORCNT0", + "RXCHBONDI1": "GTXE2_CHANNEL_RXCHBONDI1", + "GTRSVD8": "GTXE2_CHANNEL_GTRSVD8", + "CPLLPD": "GTXE2_CHANNEL_CPLLPD", + "RXDATA21": "GTXE2_CHANNEL_RXDATA21", + "RXCHARISCOMMA3": "GTXE2_CHANNEL_RXCHARISCOMMA3", + "TSTPD3": "GTXE2_CHANNEL_TSTPD3", + "GTRSVD12": "GTXE2_CHANNEL_GTRSVD12", + "RXDATA51": "GTXE2_CHANNEL_RXDATA51", + "PMASCANCLK0": "GTXE2_CHANNEL_PMASCANCLK0", + "TXDATA54": "GTXE2_CHANNEL_TXDATA54", + "TSTPD1": "GTXE2_CHANNEL_TSTPD1", + "GTXTXN": "GTXE2_CHANNEL_TXN", + "TXDATA32": "GTXE2_CHANNEL_TXDATA32", + "RXPHMONITOR2": "GTXE2_CHANNEL_RXPHMONITOR2", + "RXELECIDLEMODE1": "GTXE2_CHANNEL_RXELECIDLEMODE1", + "RXDATA28": "GTXE2_CHANNEL_RXDATA28", + "RXCHARISK5": "GTXE2_CHANNEL_RXCHARISK5", + "RXPHALIGNEN": "GTXE2_CHANNEL_RXPHALIGNEN", + "TSTIN19": "GTXE2_CHANNEL_TSTIN19", + "PMASCANIN2": "GTXE2_CHANNEL_PMASCANIN2", + "PMARSVDIN2": "GTXE2_CHANNEL_PMARSVDIN2", + "PCSRSVDIN5": "GTXE2_CHANNEL_PCSRSVDIN5", + "RXPHALIGNDONE": "GTXE2_CHANNEL_RXPHALIGNDONE", + "RXDATA0": "GTXE2_CHANNEL_RXDATA0", + "TXRATE2": "GTXE2_CHANNEL_TXRATE2", + "CPLLREFCLKSEL1": "GTXE2_CHANNEL_CPLLREFCLKSEL1", + "TSTOUT7": "GTXE2_CHANNEL_TSTOUT7", + "TXPHINITDONE": "GTXE2_CHANNEL_TXPHINITDONE", + "RXDATA15": "GTXE2_CHANNEL_RXDATA15", + "TXDATA16": "GTXE2_CHANNEL_TXDATA16", + "RXPRBSCNTRESET": "GTXE2_CHANNEL_RXPRBSCNTRESET", + "TXDATA14": "GTXE2_CHANNEL_TXDATA14", + "GTRSVD6": "GTXE2_CHANNEL_GTRSVD6", + "RXNOTINTABLE1": "GTXE2_CHANNEL_RXNOTINTABLE1", + "TXDATA2": "GTXE2_CHANNEL_TXDATA2", + "RXCHBONDO0": "GTXE2_CHANNEL_RXCHBONDO0", + "TXDEEMPH": "GTXE2_CHANNEL_TXDEEMPH", + "GTNORTHREFCLK1": "GTXE2_CHANNEL_GTNORTHREFCLK1", + "RXDFETAP4HOLD": "GTXE2_CHANNEL_RXDFETAP4HOLD", + "RXDFETAP5HOLD": "GTXE2_CHANNEL_RXDFETAP5HOLD", + "TXDATA7": "GTXE2_CHANNEL_TXDATA7", + "RXCHBONDO2": "GTXE2_CHANNEL_RXCHBONDO2", + "TXPRECURSOR2": "GTXE2_CHANNEL_TXPRECURSOR2", + "DRPDI11": "GTXE2_CHANNEL_DRPDI11", + "TXDETECTRX": "GTXE2_CHANNEL_TXDETECTRX", + "TXDATA0": "GTXE2_CHANNEL_TXDATA0", + "RXNOTINTABLE5": "GTXE2_CHANNEL_RXNOTINTABLE5", + "DRPADDR3": "GTXE2_CHANNEL_DRPADDR3", + "RXDATA42": "GTXE2_CHANNEL_RXDATA42", + "TXUSRCLK": "GTXE2_CHANNEL_TXUSRCLK", + "TXSYSCLKSEL1": "GTXE2_CHANNEL_TXSYSCLKSEL1", + "TX8B10BBYPASS0": "GTXE2_CHANNEL_TX8B10BBYPASS0", + "RXQPISENP": "GTXE2_CHANNEL_RXQPISENP", + "DRPDI13": "GTXE2_CHANNEL_DRPDI13", + "RXBUFSTATUS2": "GTXE2_CHANNEL_RXBUFSTATUS2", + "RXDISPERR0": "GTXE2_CHANNEL_RXDISPERR0", + "TXDATA46": "GTXE2_CHANNEL_TXDATA46", + "DRPDO1": "GTXE2_CHANNEL_DRPDO1", + "TXDATA15": "GTXE2_CHANNEL_TXDATA15", + "PCSRSVDIN3": "GTXE2_CHANNEL_PCSRSVDIN3", + "RXDLYSRESETDONE": "GTXE2_CHANNEL_RXDLYSRESETDONE", + "PCSRSVDIN1": "GTXE2_CHANNEL_PCSRSVDIN1", + "TXCHARDISPVAL3": "GTXE2_CHANNEL_TXCHARDISPVAL3", + "RXDFELFOVRDEN": "GTXE2_CHANNEL_RXDFELFOVRDEN", + "TXDATA41": "GTXE2_CHANNEL_TXDATA41", + "PCSRSVDOUT13": "GTXE2_CHANNEL_PCSRSVDOUT13", + "RXDATA27": "GTXE2_CHANNEL_RXDATA27", + "RXDATA30": "GTXE2_CHANNEL_RXDATA30", + "RXCHBONDI4": "GTXE2_CHANNEL_RXCHBONDI4", + "EDTSINGLEBYPASSCHAIN": "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", + "RXPRBSERR": "GTXE2_CHANNEL_RXPRBSERR", + "TXCOMWAKE": "GTXE2_CHANNEL_TXCOMWAKE", + "RXRATE0": "GTXE2_CHANNEL_RXRATE0", + "TSTIN4": "GTXE2_CHANNEL_TSTIN4", + "PMARSVDIN4": "GTXE2_CHANNEL_PMARSVDIN4", + "RXOUTCLKSEL2": "GTXE2_CHANNEL_RXOUTCLKSEL2", + "TSTOUT6": "GTXE2_CHANNEL_TSTOUT6", + "RXOOBRESET": "GTXE2_CHANNEL_RXOOBRESET", + "TSTPD4": "GTXE2_CHANNEL_TSTPD4", + "PMASCANRSTEN": "GTXE2_CHANNEL_PMASCANRSTEN", + "DRPDI8": "GTXE2_CHANNEL_DRPDI8", + "RXELECIDLEMODE0": "GTXE2_CHANNEL_RXELECIDLEMODE0", + "RXDATA6": "GTXE2_CHANNEL_RXDATA6", + "TXQPISTRONGPDOWN": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", + "TXHEADER2": "GTXE2_CHANNEL_TXHEADER2", + "PCSRSVDIN6": "GTXE2_CHANNEL_PCSRSVDIN6", + "DMONITOROUT2": "GTXE2_CHANNEL_DMONITOROUT2", + "TXDATA39": "GTXE2_CHANNEL_TXDATA39", + "TXRUNDISP7": "GTXE2_CHANNEL_TXRUNDISP7", + "TXPMARESET": "GTXE2_CHANNEL_TXPMARESET", + "RXDFETAP2OVRDEN": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", + "TX8B10BBYPASS7": "GTXE2_CHANNEL_TX8B10BBYPASS7", + "TSTIN1": "GTXE2_CHANNEL_TSTIN1", + "RXPHSLIPMONITOR0": "GTXE2_CHANNEL_RXPHSLIPMONITOR0", + "DRPDI1": "GTXE2_CHANNEL_DRPDI1", + "RXCDRRESET": "GTXE2_CHANNEL_RXCDRRESET", + "RXCHARISCOMMA1": "GTXE2_CHANNEL_RXCHARISCOMMA1", + "TXPOSTCURSOR2": "GTXE2_CHANNEL_TXPOSTCURSOR2", + "EYESCANDATAERROR": "GTXE2_CHANNEL_EYESCANDATAERROR", + "TXDATA6": "GTXE2_CHANNEL_TXDATA6", + "RXDLYSRESET": "GTXE2_CHANNEL_RXDLYSRESET", + "TXCHARDISPVAL0": "GTXE2_CHANNEL_TXCHARDISPVAL0", + "TXMAINCURSOR2": "GTXE2_CHANNEL_TXMAINCURSOR2", + "EDTBYPASS": "GTXE2_CHANNEL_EDTBYPASS", + "RXDISPERR6": "GTXE2_CHANNEL_RXDISPERR6", + "TXDATA44": "GTXE2_CHANNEL_TXDATA44", + "RXUSRCLK2": "GTXE2_CHANNEL_RXUSRCLK2", + "RXCHBONDI3": "GTXE2_CHANNEL_RXCHBONDI3", + "TSTCLK1": "GTXE2_CHANNEL_TSTCLK1", + "GTREFCLK0": "GTXE2_CHANNEL_GTREFCLK0", + "DRPDO8": "GTXE2_CHANNEL_DRPDO8", + "RXPHMONITOR0": "GTXE2_CHANNEL_RXPHMONITOR0", + "PMARSVDIN22": "GTXE2_CHANNEL_PMARSVDIN22", + "RXCHARISK3": "GTXE2_CHANNEL_RXCHARISK3", + "RXDFEAGCHOLD": "GTXE2_CHANNEL_RXDFEAGCHOLD", + "TXCHARISK2": "GTXE2_CHANNEL_TXCHARISK2", + "PCSRSVDIN23": "GTXE2_CHANNEL_PCSRSVDIN23", + "TSTOUT1": "GTXE2_CHANNEL_TSTOUT1", + "GTRSVD5": "GTXE2_CHANNEL_GTRSVD5", + "RXPHSLIPMONITOR3": "GTXE2_CHANNEL_RXPHSLIPMONITOR3", + "TXCHARDISPMODE4": "GTXE2_CHANNEL_TXCHARDISPMODE4", + "RXHEADER0": "GTXE2_CHANNEL_RXHEADER0", + "DRPDO0": "GTXE2_CHANNEL_DRPDO0", + "TXCHARISK6": "GTXE2_CHANNEL_TXCHARISK6", + "RXCLKCORCNT1": "GTXE2_CHANNEL_RXCLKCORCNT1", + "RXDFEAGCOVRDEN": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", + "TXDATA61": "GTXE2_CHANNEL_TXDATA61", + "RXDFEVSEN": "GTXE2_CHANNEL_RXDFEVSEN", + "DRPDO7": "GTXE2_CHANNEL_DRPDO7", + "PMARSVDIN21": "GTXE2_CHANNEL_PMARSVDIN21", + "PCSRSVDOUT1": "GTXE2_CHANNEL_PCSRSVDOUT1", + "PCSRSVDOUT4": "GTXE2_CHANNEL_PCSRSVDOUT4", + "RXNOTINTABLE4": "GTXE2_CHANNEL_RXNOTINTABLE4", + "RXNOTINTABLE3": "GTXE2_CHANNEL_RXNOTINTABLE3", + "GTRSVD15": "GTXE2_CHANNEL_GTRSVD15", + "TSTIN15": "GTXE2_CHANNEL_TSTIN15", + "DRPDO13": "GTXE2_CHANNEL_DRPDO13", + "RXDATAVALID": "GTXE2_CHANNEL_RXDATAVALID", + "RXDATA19": "GTXE2_CHANNEL_RXDATA19", + "RXBUFRESET": "GTXE2_CHANNEL_RXBUFRESET", + "TXPD0": "GTXE2_CHANNEL_TXPD0", + "PMARSVDIN1": "GTXE2_CHANNEL_PMARSVDIN1", + "RXDATA63": "GTXE2_CHANNEL_RXDATA63", + "TXMAINCURSOR3": "GTXE2_CHANNEL_TXMAINCURSOR3", + "RXDEBUGPULSE": "GTXE2_CHANNEL_RXDEBUGPULSE", + "RXDATA4": "GTXE2_CHANNEL_RXDATA4", + "PMASCANIN1": "GTXE2_CHANNEL_PMASCANIN1", + "TSTIN11": "GTXE2_CHANNEL_TSTIN11", + "CPLLREFCLKSEL2": "GTXE2_CHANNEL_CPLLREFCLKSEL2", + "SCANOUT1": "GTXE2_CHANNEL_SCANOUT1", + "TXRUNDISP2": "GTXE2_CHANNEL_TXRUNDISP2", + "PCSRSVDIN13": "GTXE2_CHANNEL_PCSRSVDIN13", + "SCANMODEB": "GTXE2_CHANNEL_SCANMODEB", + "GTRXRESET": "GTXE2_CHANNEL_GTRXRESET", + "PCSRSVDIN22": "GTXE2_CHANNEL_PCSRSVDIN22", + "TXDATA3": "GTXE2_CHANNEL_TXDATA3", + "TXMAINCURSOR5": "GTXE2_CHANNEL_TXMAINCURSOR5", + "GTRSVD2": "GTXE2_CHANNEL_GTRSVD2", + "CLKRSVD1": "GTXE2_CHANNEL_CLKRSVD1", + "TXOUTCLKSEL0": "GTXE2_CHANNEL_TXOUTCLKSEL0", + "TXDATA57": "GTXE2_CHANNEL_TXDATA57", + "TXPDELECIDLEMODE": "GTXE2_CHANNEL_TXPDELECIDLEMODE", + "PCSRSVDIN21": "GTXE2_CHANNEL_PCSRSVDIN21", + "TSTOUT3": "GTXE2_CHANNEL_TSTOUT3", + "PCSRSVDOUT15": "GTXE2_CHANNEL_PCSRSVDOUT15", + "TXSEQUENCE3": "GTXE2_CHANNEL_TXSEQUENCE3", + "TSTIN18": "GTXE2_CHANNEL_TSTIN18", + "TXRATE1": "GTXE2_CHANNEL_TXRATE1", + "TXSEQUENCE4": "GTXE2_CHANNEL_TXSEQUENCE4", + "RXSTARTOFSEQ": "GTXE2_CHANNEL_RXSTARTOFSEQ", + "RXPHALIGN": "GTXE2_CHANNEL_RXPHALIGN", + "RXDFEUTHOLD": "GTXE2_CHANNEL_RXDFEUTHOLD", + "DRPDI14": "GTXE2_CHANNEL_DRPDI14", + "TXRATEDONE": "GTXE2_CHANNEL_TXRATEDONE", + "TXDIFFPD": "GTXE2_CHANNEL_TXDIFFPD", + "TXCHARDISPVAL1": "GTXE2_CHANNEL_TXCHARDISPVAL1", + "RXDFELPMRESET": "GTXE2_CHANNEL_RXDFELPMRESET", + "RXCDRLOCK": "GTXE2_CHANNEL_RXCDRLOCK", + "TXDATA31": "GTXE2_CHANNEL_TXDATA31", + "RXCHARISK0": "GTXE2_CHANNEL_RXCHARISK0", + "RXDATA43": "GTXE2_CHANNEL_RXDATA43", + "TXDATA55": "GTXE2_CHANNEL_TXDATA55", + "TSTIN9": "GTXE2_CHANNEL_TSTIN9", + "TXQPIWEAKPUP": "GTXE2_CHANNEL_TXQPIWEAKPUP", + "TXDATA4": "GTXE2_CHANNEL_TXDATA4", + "RXSYSCLKSEL0": "GTXE2_CHANNEL_RXSYSCLKSEL0", + "DRPDO14": "GTXE2_CHANNEL_DRPDO14", + "TSTIN12": "GTXE2_CHANNEL_TSTIN12", + "DRPDI7": "GTXE2_CHANNEL_DRPDI7", + "TXSEQUENCE0": "GTXE2_CHANNEL_TXSEQUENCE0", + "RXDISPERR7": "GTXE2_CHANNEL_RXDISPERR7", + "CPLLLOCKDETCLK": "GTXE2_CHANNEL_CPLLLOCKDETCLK", + "DRPADDR4": "GTXE2_CHANNEL_DRPADDR4", + "RXCOMMADETEN": "GTXE2_CHANNEL_RXCOMMADETEN", + "DRPADDR2": "GTXE2_CHANNEL_DRPADDR2", + "TXPRECURSOR0": "GTXE2_CHANNEL_TXPRECURSOR0", + "PCSRSVDOUT7": "GTXE2_CHANNEL_PCSRSVDOUT7", + "RXPHSLIPMONITOR4": "GTXE2_CHANNEL_RXPHSLIPMONITOR4", + "TXPHINIT": "GTXE2_CHANNEL_TXPHINIT", + "DRPADDR5": "GTXE2_CHANNEL_DRPADDR5", + "TXDATA50": "GTXE2_CHANNEL_TXDATA50", + "PMASCANIN4": "GTXE2_CHANNEL_PMASCANIN4", + "TXPRECURSOR4": "GTXE2_CHANNEL_TXPRECURSOR4", + "PMASCANCLK1": "GTXE2_CHANNEL_PMASCANCLK1", + "TXPRBSSEL1": "GTXE2_CHANNEL_TXPRBSSEL1", + "GTRSVD11": "GTXE2_CHANNEL_GTRSVD11", + "DRPDO10": "GTXE2_CHANNEL_DRPDO10", + "TXDATA12": "GTXE2_CHANNEL_TXDATA12", + "RXDATA5": "GTXE2_CHANNEL_RXDATA5", + "TXCOMFINISH": "GTXE2_CHANNEL_TXCOMFINISH", + "TXDATA17": "GTXE2_CHANNEL_TXDATA17", + "GTTXRESET": "GTXE2_CHANNEL_GTTXRESET", + "PMASCANCLK3": "GTXE2_CHANNEL_PMASCANCLK3", + "TXDIFFCTRL1": "GTXE2_CHANNEL_TXDIFFCTRL1", + "TXPHDLYRESET": "GTXE2_CHANNEL_TXPHDLYRESET", + "RXDATA13": "GTXE2_CHANNEL_RXDATA13", + "TXDATA9": "GTXE2_CHANNEL_TXDATA9", + "PCSRSVDIN4": "GTXE2_CHANNEL_PCSRSVDIN4", + "DMONITOROUT7": "GTXE2_CHANNEL_DMONITOROUT7", + "TSTIN5": "GTXE2_CHANNEL_TSTIN5", + "RXDISPERR4": "GTXE2_CHANNEL_RXDISPERR4", + "TXDATA40": "GTXE2_CHANNEL_TXDATA40", + "TXDATA49": "GTXE2_CHANNEL_TXDATA49", + "PMARSVDIN3": "GTXE2_CHANNEL_PMARSVDIN3", + "RXDATA23": "GTXE2_CHANNEL_RXDATA23", + "TXMARGIN1": "GTXE2_CHANNEL_TXMARGIN1", + "TXDLYBYPASS": "GTXE2_CHANNEL_TXDLYBYPASS", + "PCSRSVDOUT0": "GTXE2_CHANNEL_PCSRSVDOUT0", + "TXOUTCLK": "GTXE2_CHANNEL_GTTXOUTCLK_2", + "RXLPMHFHOLD": "GTXE2_CHANNEL_RXLPMHFHOLD", + "RXDFEXYDEN": "GTXE2_CHANNEL_RXDFEXYDEN", + "TSTOUT9": "GTXE2_CHANNEL_TSTOUT9", + "TXDLYEN": "GTXE2_CHANNEL_TXDLYEN", + "RXUSRCLK": "GTXE2_CHANNEL_RXUSRCLK", + "RXDFEXYDHOLD": "GTXE2_CHANNEL_RXDFEXYDHOLD", + "TSTIN13": "GTXE2_CHANNEL_TSTIN13", + "TXPRBSFORCEERR": "GTXE2_CHANNEL_TXPRBSFORCEERR", + "CLKRSVD0": "GTXE2_CHANNEL_CLKRSVD0", + "RXPCD1DONE": "GTXE2_CHANNEL_RXPCD1DONE", + "DRPRDY": "GTXE2_CHANNEL_DRPRDY", + "RXDFEXYDOVRDEN": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", + "LOOPBACK1": "GTXE2_CHANNEL_LOOPBACK1", + "GTGREFCLK": "GTXE2_CHANNEL_GTGREFCLK", + "RXHEADER1": "GTXE2_CHANNEL_RXHEADER1", + "GTRSVD1": "GTXE2_CHANNEL_GTRSVD1", + "TXMAINCURSOR6": "GTXE2_CHANNEL_TXMAINCURSOR6", + "RXDATA17": "GTXE2_CHANNEL_RXDATA17", + "RXDATA22": "GTXE2_CHANNEL_RXDATA22", + "PCSRSVDOUT3": "GTXE2_CHANNEL_PCSRSVDOUT3", + "DRPDI0": "GTXE2_CHANNEL_DRPDI0", + "RXCHARISCOMMA5": "GTXE2_CHANNEL_RXCHARISCOMMA5", + "TXDATA58": "GTXE2_CHANNEL_TXDATA58", + "QPLLCLK": "GTXE2_CHANNEL_GTQPLLCLK", + "RXDDIEN": "GTXE2_CHANNEL_RXDDIEN", + "GTXTXP": "GTXE2_CHANNEL_TXP", + "PMASCANENB": "GTXE2_CHANNEL_PMASCANENB", + "TXDATA59": "GTXE2_CHANNEL_TXDATA59", + "GTRSVD10": "GTXE2_CHANNEL_GTRSVD10", + "RXDATA12": "GTXE2_CHANNEL_RXDATA12", + "RXCDROVRDEN": "GTXE2_CHANNEL_RXCDROVRDEN", + "TSTIN16": "GTXE2_CHANNEL_TSTIN16", + "TXDATA27": "GTXE2_CHANNEL_TXDATA27" + }, + "x_coord": 0 + }, + { + "y_coord": 42, + "name": "X0Y42", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "GTXE2_CHANNEL_RXN_PAD" + }, + "x_coord": 0 + }, + { + "y_coord": 43, + "name": "X0Y43", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "GTXE2_CHANNEL_RXP_PAD" + }, + "x_coord": 0 + }, + { + "y_coord": 6, + "name": "X0Y6", + "prefix": "OPAD", + "type": "OPAD", + "site_pins": { + "I": "GTXE2_CHANNEL_TXN_PAD" + }, + "x_coord": 0 + }, + { + "y_coord": 7, + "name": "X0Y7", + "prefix": "OPAD", + "type": "OPAD", + "site_pins": { + "I": "GTXE2_CHANNEL_TXP_PAD" + }, + "x_coord": 0 + } + ], + "wires": [ + "GTXE2_CHANNEL_PMASCANIN2", + "GTXE2_CHANNEL_RXDFETAP3HOLD", + "GTXE2_CHANNEL_RXHEADER0", + "GTXE2_IMUX29_3", + "GTXE2_LOGIC_OUTS_B21_5", + "GTXE2_CHANNEL_TXQPISENN", + "GTXE2_IMUX42_5", + "GTXE2_CHANNEL_TXDATA44", + "GTXE2_FAN2_6", + "GTXE2_IMUX23_5", + "GTXE2_LOGIC_OUTS_B19_1", + "GTXE2_CHANNEL_GTREFCLKMONITOR", + "GTXE2_CHANNEL_CPLLREFCLKSEL1", + "GTXE2_IMUX29_9", + "GTXE2_FAN5_4", + "GTXE2_LOGIC_OUTS_B23_10", + "GTXE2_CHANNEL_RXBUFSTATUS0", + "GTXE2_CHANNEL_PCSRSVDOUT13", + "GTXE2_CHANNEL_RXNOTINTABLE5", + "GTXE2_IMUX46_0", + "GTXE2_IMUX20_7", + "GTXE2_CHANNEL_DRPDI6", + "GTXE2_BYP2_3", + "GTXE2_CHANNEL_RXCHARISK4", + "GTXE2_CHANNEL_TXDIFFPD", + "GTXE2_IMUX4_4", + "GTXE2_IMUX6_0", + "GTXE2_IMUX25_4", + "GTXE2_IMUX3_2", + "GTXE2_CHANNEL_TSTIN11", + "GTXE2_CHANNEL_TSTIN8", + "GTXE2_IMUX31_7", + "GTXE2_CHANNEL_CPLLFBCLKLOST", + "GTXE2_IMUX41_9", + "GTXE2_CHANNEL_RXDLYEN", + "GTXE2_CHANNEL_RXCHARISK6", + "GTXE2_CHANNEL_GTQPLLREFCLK", + "GTXE2_CHANNEL_RXDISPERR7", + "GTXE2_CHANNEL_TXDLYBYPASS", + "GTXE2_CHANNEL_NORTHREFCLK1", + "GTXE2_IMUX26_0", + "GTXE2_CHANNEL_TXCHARDISPMODE0", + "GTXE2_LOGIC_OUTS_B23_6", + "GTXE2_CHANNEL_PCSRSVDIN24", + "GTXE2_IMUX9_2", + "GTXE2_LOGIC_OUTS_B19_2", + "GTXE2_LOGIC_OUTS_B22_8", + "GTXE2_LOGIC_OUTS_B4_1", + "GTXE2_FAN7_10", + "GTXE2_CHANNEL_RXDATA35", + "GTXE2_IMUX35_10", + "GTXE2_IMUX33_8", + "GTXE2_IMUX42_8", + "GTXE2_FAN3_8", + "GTXE2_BYP0_5", + "GTXE2_CHANNEL_PCSRSVDOUT5", + "GTXE2_CTRL0_4", + "GTXE2_CHANNEL_TXDATA24", + "GTXE2_BYP7_7", + "GTXE2_IMUX7_2", + "GTXE2_IMUX30_8", + "GTXE2_FAN5_10", + "GTXE2_IMUX15_9", + "GTXE2_CHANNEL_RXHEADERVALID", + "GTXE2_BYP1_10", + "GTXE2_CHANNEL_CPLLPD", + "GTXE2_CHANNEL_RXDFETAP2OVRDEN", + "GTXE2_CHANNEL_RXBYTEISALIGNED", + "GTXE2_LOGIC_OUTS_B2_1", + "GTXE2_CHANNEL_TXDATA48", + "GTXE2_CHANNEL_TXDATA32", + "GTXE2_CHANNEL_RXCHBONDO2", + "GTXE2_CHANNEL_PMASCANCLK1", + "GTXE2_CHANNEL_TXDLYSRESET", + "GTXE2_IMUX35_9", + "GTXE2_LOGIC_OUTS_B9_7", + "GTXE2_IMUX43_0", + "GTXE2_IMUX23_7", + "GTXE2_CHANNEL_PMASCANCLK3", + "GTXE2_FAN1_9", + "GTXE2_CHANNEL_CPLLREFCLKSEL0", + "GTXE2_IMUX26_9", + "GTXE2_LOGIC_OUTS_B1_4", + "GTXE2_CHANNEL_TXDATA29", + "GTXE2_LOGIC_OUTS_B20_8", + "GTXE2_FAN3_9", + "GTXE2_IMUX18_7", + "GTXE2_LOGIC_OUTS_B12_4", + "GTXE2_CHANNEL_TXCHARISK7", + "GTXE2_LOGIC_OUTS_B1_9", + "GTXE2_CHANNEL_RXDATA28", + "GTXE2_CHANNEL_RXMCOMMAALIGNEN", + "GTXE2_IMUX47_8", + "GTXE2_CHANNEL_RXCHBONDMASTER", + "GTXE2_CHANNEL_TXCHARDISPVAL5", + "GTXE2_IMUX19_6", + "GTXE2_IMUX10_4", + "GTXE2_FAN5_3", + "GTXE2_CHANNEL_RXPHSLIPMONITOR4", + "GTXE2_FAN1_8", + "GTXE2_CHANNEL_TXCHARISK3", + "GTXE2_BYP1_4", + "GTXE2_FAN0_6", + "GTXE2_CHANNEL_DRPADDR4", + "GTXE2_CHANNEL_RXPRBSSEL2", + "GTXE2_IMUX1_3", + "GTXE2_IMUX1_5", + "GTXE2_IMUX31_10", + "GTXE2_LOGIC_OUTS_B15_9", + "GTXE2_CHANNEL_RXN", + "GTXE2_CHANNEL_TXDEEMPH", + "GTXE2_CHANNEL_TSTIN6", + "GTXE2_CHANNEL_PMASCANRSTEN", + "GTXE2_CHANNEL_LOOPBACK1", + "GTXE2_CHANNEL_TXOUTCLK_0", + "GTXE2_BYP1_2", + "GTXE2_CHANNEL_TXDATA63", + "GTXE2_IMUX6_2", + "GTXE2_LOGIC_OUTS_B23_5", + "GTXE2_CHANNEL_RXDATA15", + "GTXE2_CHANNEL_TXCHARDISPMODE5", + "GTXE2_LOGIC_OUTS_B7_9", + "GTXE2_CHANNEL_RXCDRRESET", + "GTXE2_CHANNEL_TSTIN4", + "GTXE2_CHANNEL_RXOOBRESET", + "GTXE2_FAN7_6", + "GTXE2_CTRL0_7", + "GTXE2_IMUX37_2", + "GTXE2_CHANNEL_RXDATA50", + "GTXE2_CHANNEL_TXDATA36", + "GTXE2_IMUX45_0", + "GTXE2_BYP4_7", + "GTXE2_FAN7_0", + "GTXE2_LOGIC_OUTS_B19_6", + "GTXE2_CHANNEL_RXDATA54", + "GTXE2_CHANNEL_RXCOMMADET", + "GTXE2_CLK1_7", + "GTXE2_IMUX46_1", + "GTXE2_CHANNEL_RXQPIEN", + "GTXE2_CHANNEL_RXSTATUS2", + "GTXE2_IMUX30_2", + "GTXE2_CHANNEL_RXOUTCLKSEL2", + "GTXE2_BYP5_5", + "GTXE2_IMUX22_4", + "GTXE2_BYP2_0", + "GTXE2_IMUX35_1", + "GTXE2_CHANNEL_RXDATA17", + "GTXE2_IMUX15_0", + "GTXE2_BYP5_3", + "GTXE2_LOGIC_OUTS_B6_7", + "GTXE2_CHANNEL_RXCOMWAKEDET", + "GTXE2_LOGIC_OUTS_B3_0", + "GTXE2_BYP1_1", + "GTXE2_LOGIC_OUTS_B3_1", + "GTXE2_IMUX24_4", + "GTXE2_FAN1_5", + "GTXE2_IMUX44_0", + "GTXE2_LOGIC_OUTS_B5_3", + "GTXE2_CHANNEL_RXSTATUS1", + "GTXE2_CHANNEL_RXDATA62", + "GTXE2_BYP0_7", + "GTXE2_LOGIC_OUTS_B19_10", + "GTXE2_CLK1_9", + "GTXE2_CHANNEL_PCSRSVDIN7", + "GTXE2_LOGIC_OUTS_B7_7", + "GTXE2_CHANNEL_TXDATA28", + "GTXE2_IMUX22_10", + "GTXE2_LOGIC_OUTS_B21_3", + "GTXE2_FAN5_8", + "GTXE2_IMUX39_5", + "GTXE2_IMUX22_1", + "GTXE2_CHANNEL_PMARSVDIN24", + "GTXE2_CHANNEL_RXCHBONDI3", + "GTXE2_IMUX8_8", + "GTXE2_IMUX44_2", + "GTXE2_LOGIC_OUTS_B11_4", + "GTXE2_CHANNEL_TSTIN19", + "GTXE2_IMUX23_0", + "GTXE2_CHANNEL_TXDATA13", + "GTXE2_LOGIC_OUTS_B21_8", + "GTXE2_IMUX44_9", + "GTXE2_CHANNEL_GTRSVD0", + "GTXE2_CHANNEL_DRPCLK", + "GTXE2_CHANNEL_GTRSVD13", + "GTXE2_BYP5_8", + "GTXE2_IMUX11_9", + "GTXE2_LOGIC_OUTS_B8_6", + "GTXE2_CHANNEL_RXCHARISCOMMA4", + "GTXE2_IMUX42_2", + "GTXE2_IMUX41_10", + "GTXE2_CHANNEL_TSTPD2", + "GTXE2_CHANNEL_TXPRECURSOR2", + "GTXE2_LOGIC_OUTS_B11_9", + "GTXE2_IMUX2_7", + "GTXE2_CHANNEL_TXDATA19", + "GTXE2_IMUX1_4", + "GTXE2_CHANNEL_TXSEQUENCE6", + "GTXE2_IMUX31_3", + "GTXE2_LOGIC_OUTS_B23_9", + "GTXE2_LOGIC_OUTS_B10_8", + "GTXE2_CHANNEL_CLKRSVD2", + "GTXE2_CLK1_10", + "GTXE2_IMUX13_9", + "GTXE2_IMUX21_10", + "GTXE2_BYP7_10", + "GTXE2_CTRL0_8", + "GTXE2_CHANNEL_TXPHDLYRESET", + "GTXE2_BYP7_2", + "GTXE2_CHANNEL_PCSRSVDOUT15", + "GTXE2_BYP6_8", + "GTXE2_CHANNEL_TXDATA16", + "GTXE2_IMUX11_8", + "GTXE2_CHANNEL_TXMAINCURSOR1", + "GTXE2_CHANNEL_PCSRSVDOUT11", + "GTXE2_IMUX22_8", + "GTXE2_IMUX17_1", + "GTXE2_FAN3_10", + "GTXE2_CHANNEL_TXRUNDISP5", + "GTXE2_CHANNEL_TXPOSTCURSOR0", + "GTXE2_IMUX21_0", + "GTXE2_CTRL1_7", + "GTXE2_CHANNEL_RXOUTCLKFABRIC", + "GTXE2_IMUX45_8", + "GTXE2_CHANNEL_RXCHBONDO4", + "GTXE2_LOGIC_OUTS_B20_0", + "GTXE2_BYP6_5", + "GTXE2_IMUX33_10", + "GTXE2_IMUX46_3", + "GTXE2_IMUX8_7", + "GTXE2_CHANNEL_RXOSHOLD", + "GTXE2_BYP2_10", + "GTXE2_CHANNEL_TXDATA8", + "GTXE2_CHANNEL_RXCHARISK2", + "GTXE2_CHANNEL_DRPDO10", + "GTXE2_LOGIC_OUTS_B17_9", + "GTXE2_IMUX9_1", + "GTXE2_IMUX12_1", + "GTXE2_IMUX0_10", + "GTXE2_CHANNEL_RXELECIDLE", + "GTXE2_CHANNEL_DRPDI10", + "GTXE2_FAN7_1", + "GTXE2_CHANNEL_RXDATA42", + "GTXE2_CHANNEL_TXCHARDISPMODE6", + "GTXE2_IMUX5_8", + "GTXE2_LOGIC_OUTS_B5_8", + "GTXE2_CHANNEL_TXQPISENP", + "GTXE2_CHANNEL_RXDATA21", + "GTXE2_CHANNEL_TXPOSTCURSORINV", + "GTXE2_LOGIC_OUTS_B9_0", + "GTXE2_IMUX0_5", + "GTXE2_BYP1_7", + "GTXE2_FAN4_9", + "GTXE2_IMUX25_10", + "GTXE2_CHANNEL_RXELECIDLEMODE0", + "GTXE2_LOGIC_OUTS_B20_10", + "GTXE2_CHANNEL_RXDATA39", + "GTXE2_CHANNEL_TXPHOVRDEN", + "GTXE2_IMUX22_3", + "GTXE2_CHANNEL_PMARSVDIN22", + "GTXE2_IMUX36_2", + "GTXE2_FAN6_3", + "GTXE2_CHANNEL_GTRSVD5", + "GTXE2_LOGIC_OUTS_B3_2", + "GTXE2_IMUX2_5", + "GTXE2_IMUX33_4", + "GTXE2_CHANNEL_DMONITOROUT4", + "GTXE2_IMUX40_3", + "GTXE2_CHANNEL_DMONITOROUT5", + "GTXE2_CHANNEL_TXRUNDISP4", + "GTXE2_CHANNEL_DRPADDR8", + "GTXE2_IMUX27_4", + "GTXE2_IMUX36_3", + "GTXE2_LOGIC_OUTS_B8_10", + "GTXE2_IMUX31_9", + "GTXE2_LOGIC_OUTS_B16_0", + "GTXE2_IMUX11_0", + "GTXE2_CHANNEL_PCSRSVDOUT1", + "GTXE2_IMUX24_1", + "GTXE2_FAN3_0", + "GTXE2_CHANNEL_RXVALID", + "GTXE2_IMUX5_7", + "GTXE2_BYP6_10", + "GTXE2_CHANNEL_PCSRSVDIN6", + "GTXE2_IMUX23_6", + "GTXE2_CHANNEL_RXNOTINTABLE1", + "GTXE2_CHANNEL_DRPRDY", + "GTXE2_IMUX1_10", + "GTXE2_IMUX25_8", + "GTXE2_LOGIC_OUTS_B14_4", + "GTXE2_CHANNEL_TXSWING", + "GTXE2_IMUX28_8", + "GTXE2_IMUX28_7", + "GTXE2_CHANNEL_PCSRSVDOUT14", + "GTXE2_CHANNEL_TXCOMWAKE", + "GTXE2_IMUX3_3", + "GTXE2_IMUX10_6", + "GTXE2_CHANNEL_TXPHDLYPD", + "GTXE2_CHANNEL_TSTIN7", + "GTXE2_CHANNEL_RESETOVRD", + "GTXE2_IMUX10_0", + "GTXE2_IMUX3_1", + "GTXE2_LOGIC_OUTS_B19_7", + "GTXE2_CHANNEL_DRPDO6", + "GTXE2_CHANNEL_RXDFEVPOVRDEN", + "GTXE2_IMUX37_6", + "GTXE2_IMUX16_9", + "GTXE2_BYP3_6", + "GTXE2_BYP7_5", + "GTXE2_CHANNEL_RXPD0", + "GTXE2_LOGIC_OUTS_B12_5", + "GTXE2_LOGIC_OUTS_B3_3", + "GTXE2_IMUX12_10", + "GTXE2_CHANNEL_RXP_PAD", + "GTXE2_IMUX14_1", + "GTXE2_CHANNEL_TXDATA40", + "GTXE2_IMUX32_8", + "GTXE2_IMUX12_5", + "GTXE2_LOGIC_OUTS_B13_1", + "GTXE2_LOGIC_OUTS_B8_4", + "GTXE2_LOGIC_OUTS_B17_0", + "GTXE2_IMUX44_8", + "GTXE2_CTRL1_1", + "GTXE2_LOGIC_OUTS_B7_1", + "GTXE2_IMUX4_10", + "GTXE2_CHANNEL_DMONITOROUT6", + "GTXE2_CHANNEL_TXDATA3", + "GTXE2_CHANNEL_RXBUFSTATUS2", + "GTXE2_CHANNEL_RXDFEVPHOLD", + "GTXE2_LOGIC_OUTS_B5_4", + "GTXE2_IMUX14_10", + "GTXE2_IMUX27_2", + "GTXE2_IMUX13_8", + "GTXE2_LOGIC_OUTS_B16_6", + "GTXE2_IMUX15_5", + "GTXE2_LOGIC_OUTS_B2_10", + "GTXE2_IMUX41_2", + "GTXE2_CHANNEL_TXRUNDISP2", + "GTXE2_LOGIC_OUTS_B10_1", + "GTXE2_CHANNEL_SCANIN0", + "GTXE2_IMUX23_4", + "GTXE2_CLK1_5", + "GTXE2_IMUX6_9", + "GTXE2_IMUX21_3", + "GTXE2_IMUX11_4", + "GTXE2_IMUX25_9", + "GTXE2_CHANNEL_TXQPISTRONGPDOWN", + "GTXE2_BYP5_7", + "GTXE2_IMUX47_10", + "GTXE2_IMUX22_6", + "GTXE2_CHANNEL_SCANENB", + "GTXE2_CHANNEL_NORTHREFCLK0", + "GTXE2_CHANNEL_RXPHMONITOR0", + "GTXE2_LOGIC_OUTS_B15_1", + "GTXE2_CHANNEL_RXCHANREALIGN", + "GTXE2_CHANNEL_DMONITOROUT2", + "GTXE2_IMUX40_2", + "GTXE2_IMUX39_6", + "GTXE2_CHANNEL_RXCOMSASDET", + "GTXE2_CTRL1_10", + "GTXE2_CHANNEL_TXDATA59", + "GTXE2_IMUX21_6", + "GTXE2_IMUX22_9", + "GTXE2_LOGIC_OUTS_B11_10", + "GTXE2_IMUX1_0", + "GTXE2_LOGIC_OUTS_B0_5", + "GTXE2_FAN5_9", + "GTXE2_LOGIC_OUTS_B22_3", + "GTXE2_FAN5_5", + "GTXE2_FAN4_3", + "GTXE2_LOGIC_OUTS_B1_0", + "GTXE2_LOGIC_OUTS_B9_5", + "GTXE2_CHANNEL_RXCHBONDEN", + "GTXE2_LOGIC_OUTS_B6_6", + "GTXE2_CHANNEL_TXPRBSSEL0", + "GTXE2_BYP0_0", + "GTXE2_IMUX17_10", + "GTXE2_LOGIC_OUTS_B12_2", + "GTXE2_IMUX27_1", + "GTXE2_IMUX12_9", + "GTXE2_IMUX28_4", + "GTXE2_LOGIC_OUTS_B16_3", + "GTXE2_LOGIC_OUTS_B19_5", + "GTXE2_CHANNEL_TXHEADER1", + "GTXE2_IMUX11_7", + "GTXE2_LOGIC_OUTS_B15_4", + "GTXE2_IMUX19_4", + "GTXE2_IMUX32_2", + "GTXE2_LOGIC_OUTS_B12_1", + "GTXE2_CHANNEL_TXCHARDISPMODE2", + "GTXE2_IMUX30_3", + "GTXE2_CHANNEL_RXUSRCLK", + "GTXE2_CHANNEL_TSTCLK0", + "GTXE2_CHANNEL_DRPDI9", + "GTXE2_CHANNEL_TXDATA9", + "GTXE2_LOGIC_OUTS_B21_2", + "GTXE2_IMUX19_5", + "GTXE2_IMUX27_5", + "GTXE2_FAN0_8", + "GTXE2_CHANNEL_DRPDI13", + "GTXE2_FAN2_5", + "GTXE2_CHANNEL_RXDFEVSEN", + "GTXE2_IMUX37_7", + "GTXE2_LOGIC_OUTS_B23_2", + "GTXE2_IMUX2_2", + "GTXE2_CHANNEL_TX8B10BBYPASS6", + "GTXE2_CHANNEL_TXPOSTCURSOR1", + "GTXE2_CHANNEL_RXDATAVALID", + "GTXE2_CHANNEL_TXDATA31", + "GTXE2_CHANNEL_TXPHDLYTSTCLK", + "GTXE2_CHANNEL_TXCHARISK0", + "GTXE2_LOGIC_OUTS_B3_10", + "GTXE2_CHANNEL_PMARSVDIN3", + "GTXE2_IMUX34_5", + "GTXE2_CHANNEL_TXDATA6", + "GTXE2_CHANNEL_RXPRBSCNTRESET", + "GTXE2_IMUX3_7", + "GTXE2_CHANNEL_TXRUNDISP1", + "GTXE2_IMUX40_0", + "GTXE2_IMUX9_5", + "GTXE2_IMUX4_5", + "GTXE2_FAN6_9", + "GTXE2_CHANNEL_TSTIN0", + "GTXE2_FAN4_0", + "GTXE2_CHANNEL_TXDATA14", + "GTXE2_CHANNEL_TSTIN9", + "GTXE2_LOGIC_OUTS_B4_4", + "GTXE2_BYP0_3", + "GTXE2_FAN3_5", + "GTXE2_CHANNEL_TSTIN12", + "GTXE2_CHANNEL_TXCHARISK1", + "GTXE2_IMUX40_9", + "GTXE2_CHANNEL_TXDATA10", + "GTXE2_CHANNEL_RXNOTINTABLE6", + "GTXE2_IMUX39_3", + "GTXE2_LOGIC_OUTS_B4_7", + "GTXE2_IMUX43_7", + "GTXE2_CHANNEL_TXBUFDIFFCTRL2", + "GTXE2_IMUX5_4", + "GTXE2_CHANNEL_TXDATA30", + "GTXE2_IMUX39_1", + "GTXE2_CHANNEL_CPLLREFCLKLOST", + "GTXE2_CTRL0_9", + "GTXE2_LOGIC_OUTS_B21_7", + "GTXE2_CHANNEL_GTREFCLK1", + "GTXE2_BYP0_8", + "GTXE2_CHANNEL_DRPDI14", + "GTXE2_IMUX33_2", + "GTXE2_LOGIC_OUTS_B11_5", + "GTXE2_IMUX17_4", + "GTXE2_CHANNEL_TXDATA0", + "GTXE2_CHANNEL_EYESCANMODE", + "GTXE2_LOGIC_OUTS_B4_2", + "GTXE2_CHANNEL_SCANOUT3", + "GTXE2_IMUX13_2", + "GTXE2_IMUX19_9", + "GTXE2_LOGIC_OUTS_B9_1", + "GTXE2_CHANNEL_GTRSVD11", + "GTXE2_IMUX10_8", + "GTXE2_LOGIC_OUTS_B18_1", + "GTXE2_CHANNEL_RXDDIEN", + "GTXE2_IMUX5_1", + "GTXE2_IMUX35_5", + "GTXE2_IMUX32_6", + "GTXE2_IMUX40_8", + "GTXE2_CTRL1_2", + "GTXE2_LOGIC_OUTS_B6_2", + "GTXE2_LOGIC_OUTS_B16_8", + "GTXE2_IMUX40_10", + "GTXE2_CHANNEL_PMASCANCLK2", + "GTXE2_LOGIC_OUTS_B2_4", + "GTXE2_CHANNEL_PCSRSVDIN22", + "GTXE2_IMUX9_7", + "GTXE2_CHANNEL_DRPDI8", + "GTXE2_CHANNEL_TXPHINITDONE", + "GTXE2_FAN5_2", + "GTXE2_CHANNEL_LOOPBACK0", + "GTXE2_IMUX29_8", + "GTXE2_LOGIC_OUTS_B17_7", + "GTXE2_LOGIC_OUTS_B11_3", + "GTXE2_CHANNEL_CPLLLOCK", + "GTXE2_CHANNEL_RXDFETAP4OVRDEN", + "GTXE2_IMUX0_8", + "GTXE2_BYP4_4", + "GTXE2_LOGIC_OUTS_B10_9", + "GTXE2_CHANNEL_RXBUFRESET", + "GTXE2_CHANNEL_GTRXOUTCLK_2", + "GTXE2_IMUX12_2", + "GTXE2_CHANNEL_PCSRSVDOUT7", + "GTXE2_LOGIC_OUTS_B9_9", + "GTXE2_IMUX5_10", + "GTXE2_LOGIC_OUTS_B20_5", + "GTXE2_CHANNEL_PCSRSVDIN23", + "GTXE2_IMUX8_2", + "GTXE2_CHANNEL_TXDATA42", + "GTXE2_IMUX46_2", + "GTXE2_IMUX40_6", + "GTXE2_IMUX33_1", + "GTXE2_FAN6_0", + "GTXE2_LOGIC_OUTS_B11_7", + "GTXE2_BYP2_8", + "GTXE2_IMUX47_0", + "GTXE2_FAN0_3", + "GTXE2_CHANNEL_RXPHDLYRESET", + "GTXE2_LOGIC_OUTS_B11_6", + "GTXE2_LOGIC_OUTS_B8_3", + "GTXE2_IMUX36_4", + "GTXE2_CHANNEL_GTRESETSEL", + "GTXE2_CHANNEL_GTGREFCLK", + "GTXE2_LOGIC_OUTS_B11_0", + "GTXE2_LOGIC_OUTS_B5_9", + "GTXE2_IMUX34_2", + "GTXE2_IMUX8_3", + "GTXE2_LOGIC_OUTS_B14_1", + "GTXE2_LOGIC_OUTS_B18_6", + "GTXE2_CHANNEL_GTRSVD15", + "GTXE2_CHANNEL_RXDATA7", + "GTXE2_LOGIC_OUTS_B3_6", + "GTXE2_CHANNEL_RXCHARISK0", + "GTXE2_IMUX4_3", + "GTXE2_IMUX16_1", + "GTXE2_CHANNEL_RXDATA11", + "GTXE2_CHANNEL_TX8B10BBYPASS2", + "GTXE2_IMUX19_10", + "GTXE2_CHANNEL_TXDATA61", + "GTXE2_CHANNEL_RXDATA19", + "GTXE2_BYP5_10", + "GTXE2_IMUX20_1", + "GTXE2_IMUX16_6", + "GTXE2_IMUX26_7", + "GTXE2_CHANNEL_PMASCANOUT2", + "GTXE2_CHANNEL_TSTIN2", + "GTXE2_IMUX1_2", + "GTXE2_BYP4_3", + "GTXE2_LOGIC_OUTS_B18_7", + "GTXE2_CHANNEL_PCSRSVDIN21", + "GTXE2_CHANNEL_RXDISPERR3", + "GTXE2_IMUX40_5", + "GTXE2_FAN3_6", + "GTXE2_IMUX20_3", + "GTXE2_FAN7_2", + "GTXE2_CHANNEL_RXDLYTESTENB", + "GTXE2_FAN4_7", + "GTXE2_FAN2_0", + "GTXE2_IMUX32_9", + "GTXE2_IMUX30_9", + "GTXE2_IMUX32_4", + "GTXE2_CHANNEL_GTRSVD10", + "GTXE2_IMUX30_1", + "GTXE2_CHANNEL_DRPDO15", + "GTXE2_CHANNEL_TXDLYSRESETDONE", + "GTXE2_FAN2_3", + "GTXE2_IMUX30_5", + "GTXE2_LOGIC_OUTS_B6_4", + "GTXE2_CHANNEL_TXPOLARITY", + "GTXE2_CHANNEL_GTRSVD8", + "GTXE2_CHANNEL_TXDATA43", + "GTXE2_IMUX43_5", + "GTXE2_LOGIC_OUTS_B18_5", + "GTXE2_BYP3_0", + "GTXE2_BYP6_2", + "GTXE2_CHANNEL_TXDATA57", + "GTXE2_IMUX27_9", + "GTXE2_CHANNEL_DRPADDR0", + "GTXE2_CHANNEL_TXDATA15", + "GTXE2_IMUX10_1", + "GTXE2_CHANNEL_PCSRSVDOUT0", + "GTXE2_CHANNEL_PMARSVDIN1", + "GTXE2_IMUX4_1", + "GTXE2_IMUX39_2", + "GTXE2_CHANNEL_REFCLK1", + "GTXE2_IMUX9_8", + "GTXE2_LOGIC_OUTS_B21_1", + "GTXE2_IMUX4_0", + "GTXE2_BYP3_8", + "GTXE2_CHANNEL_DRPDO8", + "GTXE2_IMUX11_5", + "GTXE2_IMUX24_8", + "GTXE2_IMUX44_3", + "GTXE2_IMUX20_4", + "GTXE2_CHANNEL_RXDLYOVRDEN", + "GTXE2_CTRL1_5", + "GTXE2_CHANNEL_DRPWE", + "GTXE2_IMUX20_0", + "GTXE2_BYP3_10", + "GTXE2_LOGIC_OUTS_B5_1", + "GTXE2_CHANNEL_RXMONITORSEL0", + "GTXE2_CHANNEL_TXPRECURSOR0", + "GTXE2_CHANNEL_RXDATA10", + "GTXE2_CHANNEL_DMONITOROUT3", + "GTXE2_CHANNEL_TXDATA34", + "GTXE2_CHANNEL_TXDATA1", + "GTXE2_IMUX16_10", + "GTXE2_IMUX15_6", + "GTXE2_BYP0_10", + "GTXE2_CHANNEL_RXSTATUS0", + "GTXE2_FAN1_1", + "GTXE2_IMUX12_0", + "GTXE2_FAN0_2", + "GTXE2_LOGIC_OUTS_B0_6", + "GTXE2_IMUX37_8", + "GTXE2_CHANNEL_TXRUNDISP7", + "GTXE2_CHANNEL_DRPDI3", + "GTXE2_IMUX8_4", + "GTXE2_CHANNEL_RXDATA58", + "GTXE2_FAN3_1", + "GTXE2_CHANNEL_TXDATA41", + "GTXE2_BYP7_9", + "GTXE2_BYP4_1", + "GTXE2_LOGIC_OUTS_B18_2", + "GTXE2_CHANNEL_TXRATE1", + "GTXE2_CHANNEL_TXDLYOVRDEN", + "GTXE2_IMUX4_9", + "GTXE2_IMUX34_7", + "GTXE2_LOGIC_OUTS_B2_9", + "GTXE2_IMUX39_9", + "GTXE2_CHANNEL_RXDATA52", + "GTXE2_CHANNEL_GTTXOUTCLK_2", + "GTXE2_IMUX6_6", + "GTXE2_IMUX2_4", + "GTXE2_IMUX9_4", + "GTXE2_CHANNEL_PCSRSVDOUT12", + "GTXE2_IMUX3_4", + "GTXE2_CHANNEL_TSTPDOVRDB", + "GTXE2_CLK1_1", + "GTXE2_IMUX1_6", + "GTXE2_CHANNEL_TXDATA47", + "GTXE2_BYP4_2", + "GTXE2_CHANNEL_RXQPISENN", + "GTXE2_CHANNEL_RXPHMONITOR1", + "GTXE2_FAN6_2", + "GTXE2_CHANNEL_RXMONITOROUT4", + "GTXE2_CHANNEL_TXPRECURSOR3", + "GTXE2_CHANNEL_DRPDO7", + "GTXE2_LOGIC_OUTS_B6_0", + "GTXE2_IMUX17_5", + "GTXE2_LOGIC_OUTS_B10_2", + "GTXE2_CHANNEL_TXN_PAD", + "GTXE2_BYP3_3", + "GTXE2_IMUX2_3", + "GTXE2_CHANNEL_TXDATA62", + "GTXE2_FAN3_7", + "GTXE2_IMUX7_1", + "GTXE2_LOGIC_OUTS_B13_5", + "GTXE2_CHANNEL_RXRESETDONE", + "GTXE2_IMUX40_1", + "GTXE2_CHANNEL_TSTOUT6", + "GTXE2_IMUX36_10", + "GTXE2_CHANNEL_TXCOMINIT", + "GTXE2_LOGIC_OUTS_B0_9", + "GTXE2_IMUX4_8", + "GTXE2_IMUX29_4", + "GTXE2_IMUX45_9", + "GTXE2_FAN2_8", + "GTXE2_IMUX10_10", + "GTXE2_CHANNEL_RXDATA34", + "GTXE2_CHANNEL_PCSRSVDIN5", + "GTXE2_CHANNEL_GTRSVD9", + "GTXE2_IMUX6_1", + "GTXE2_IMUX43_2", + "GTXE2_LOGIC_OUTS_B0_10", + "GTXE2_IMUX30_6", + "GTXE2_LOGIC_OUTS_B14_5", + "GTXE2_IMUX42_7", + "GTXE2_IMUX21_8", + "GTXE2_IMUX35_7", + "GTXE2_CHANNEL_RXLPMHFOVRDEN", + "GTXE2_IMUX18_4", + "GTXE2_CHANNEL_RXPRBSSEL0", + "GTXE2_IMUX0_2", + "GTXE2_CHANNEL_PCSRSVDIN13", + "GTXE2_LOGIC_OUTS_B0_4", + "GTXE2_IMUX46_9", + "GTXE2_CHANNEL_PCSRSVDIN15", + "GTXE2_CHANNEL_TXP", + "GTXE2_CHANNEL_RXCHARISK5", + "GTXE2_CHANNEL_TXMAINCURSOR0", + "GTXE2_CHANNEL_TXDATA53", + "GTXE2_LOGIC_OUTS_B15_8", + "GTXE2_CHANNEL_DRPDO13", + "GTXE2_IMUX33_9", + "GTXE2_IMUX25_3", + "GTXE2_CHANNEL_TXMAINCURSOR3", + "GTXE2_CHANNEL_DRPDO4", + "GTXE2_IMUX42_4", + "GTXE2_IMUX31_5", + "GTXE2_CHANNEL_RXDATA32", + "GTXE2_LOGIC_OUTS_B20_6", + "GTXE2_LOGIC_OUTS_B13_9", + "GTXE2_CHANNEL_TXRATEDONE", + "GTXE2_CHANNEL_RXRATEDONE", + "GTXE2_FAN6_1", + "GTXE2_IMUX43_1", + "GTXE2_IMUX39_8", + "GTXE2_IMUX45_3", + "GTXE2_IMUX45_5", + "GTXE2_CTRL0_3", + "GTXE2_IMUX41_7", + "GTXE2_CHANNEL_RXCHBONDO3", + "GTXE2_CHANNEL_TXCHARDISPVAL3", + "GTXE2_CHANNEL_TXDATA45", + "GTXE2_CHANNEL_TXUSERRDY", + "GTXE2_FAN4_5", + "GTXE2_FAN5_1", + "GTXE2_LOGIC_OUTS_B8_7", + "GTXE2_CHANNEL_TSTPD4", + "GTXE2_CHANNEL_PMASCANCLK0", + "GTXE2_IMUX23_10", + "GTXE2_CHANNEL_TXBUFDIFFCTRL0", + "GTXE2_BYP0_9", + "GTXE2_FAN2_9", + "GTXE2_IMUX15_4", + "GTXE2_IMUX6_4", + "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", + "GTXE2_CHANNEL_TXDATA38", + "GTXE2_CHANNEL_RXDFEUTOVRDEN", + "GTXE2_FAN1_0", + "GTXE2_CHANNEL_RXDATA51", + "GTXE2_CLK0_9", + "GTXE2_CHANNEL_TXPD0", + "GTXE2_CHANNEL_GTRSVD4", + "GTXE2_IMUX2_10", + "GTXE2_IMUX47_6", + "GTXE2_CHANNEL_TXPD1", + "GTXE2_IMUX35_0", + "GTXE2_CHANNEL_TXDLYHOLD", + "GTXE2_CHANNEL_TXPMARESET", + "GTXE2_IMUX28_10", + "GTXE2_LOGIC_OUTS_B22_5", + "GTXE2_LOGIC_OUTS_B17_2", + "GTXE2_LOGIC_OUTS_B19_9", + "GTXE2_IMUX14_2", + "GTXE2_CHANNEL_TXDATA60", + "GTXE2_IMUX38_0", + "GTXE2_BYP6_9", + "GTXE2_CHANNEL_QPLLREFCLK", + "GTXE2_LOGIC_OUTS_B21_10", + "GTXE2_IMUX24_3", + "GTXE2_CHANNEL_DRPDI0", + "GTXE2_LOGIC_OUTS_B9_10", + "GTXE2_CHANNEL_TSTIN15", + "GTXE2_CHANNEL_RXPHSLIPMONITOR1", + "GTXE2_CHANNEL_RXDFETAP4HOLD", + "GTXE2_BYP3_7", + "GTXE2_CHANNEL_TXSEQUENCE3", + "GTXE2_BYP6_4", + "GTXE2_IMUX18_3", + "GTXE2_IMUX45_7", + "GTXE2_CHANNEL_TSTIN14", + "GTXE2_IMUX8_0", + "GTXE2_CHANNEL_RXHEADER1", + "GTXE2_CHANNEL_TXCHARISK5", + "GTXE2_IMUX37_1", + "GTXE2_CHANNEL_RXBYTEREALIGN", + "GTXE2_IMUX5_0", + "GTXE2_CHANNEL_DMONITOROUT0", + "GTXE2_CHANNEL_DRPEN", + "GTXE2_CHANNEL_TXUSRCLK", + "GTXE2_FAN3_4", + "GTXE2_IMUX19_8", + "GTXE2_CHANNEL_PCSRSVDIN10", + "GTXE2_IMUX1_9", + "GTXE2_LOGIC_OUTS_B17_8", + "GTXE2_CHANNEL_RXPHMONITOR4", + "GTXE2_FAN6_7", + "GTXE2_IMUX8_9", + "GTXE2_IMUX2_6", + "GTXE2_CHANNEL_PCSRSVDOUT6", + "GTXE2_IMUX7_9", + "GTXE2_IMUX19_1", + "GTXE2_CHANNEL_PCSRSVDIN4", + "GTXE2_IMUX21_7", + "GTXE2_LOGIC_OUTS_B18_8", + "GTXE2_IMUX7_5", + "GTXE2_IMUX41_1", + "GTXE2_CHANNEL_TXDATA5", + "GTXE2_IMUX9_9", + "GTXE2_CLK1_2", + "GTXE2_LOGIC_OUTS_B6_8", + "GTXE2_BYP6_7", + "GTXE2_CTRL1_8", + "GTXE2_IMUX17_7", + "GTXE2_IMUX46_7", + "GTXE2_CHANNEL_TSTIN3", + "GTXE2_CHANNEL_RXCHBONDLEVEL2", + "GTXE2_CTRL0_1", + "GTXE2_CHANNEL_TXMAINCURSOR4", + "GTXE2_CHANNEL_PCSRSVDIN2", + "GTXE2_IMUX26_4", + "GTXE2_CHANNEL_RXMONITOROUT1", + "GTXE2_CHANNEL_RXCHARISK3", + "GTXE2_IMUX15_8", + "GTXE2_CHANNEL_TSTIN13", + "GTXE2_CHANNEL_PCSRSVDIN1", + "GTXE2_CHANNEL_GTNORTHREFCLK1", + "GTXE2_BYP0_6", + "GTXE2_CHANNEL_RXDATA36", + "GTXE2_CHANNEL_RXQPISENP", + "GTXE2_CHANNEL_RXDATA31", + "GTXE2_LOGIC_OUTS_B0_8", + "GTXE2_LOGIC_OUTS_B0_7", + "GTXE2_IMUX24_6", + "GTXE2_LOGIC_OUTS_B22_9", + "GTXE2_CHANNEL_RXDATA46", + "GTXE2_IMUX33_6", + "GTXE2_LOGIC_OUTS_B21_0", + "GTXE2_IMUX19_0", + "GTXE2_CLK1_3", + "GTXE2_LOGIC_OUTS_B14_2", + "GTXE2_IMUX37_4", + "GTXE2_BYP5_1", + "GTXE2_IMUX6_8", + "GTXE2_IMUX16_2", + "GTXE2_CHANNEL_RXDATA2", + "GTXE2_IMUX31_2", + "GTXE2_FAN4_2", + "GTXE2_LOGIC_OUTS_B18_0", + "GTXE2_CHANNEL_SCANIN4", + "GTXE2_LOGIC_OUTS_B15_10", + "GTXE2_LOGIC_OUTS_B13_3", + "GTXE2_LOGIC_OUTS_B5_7", + "GTXE2_LOGIC_OUTS_B6_9", + "GTXE2_CHANNEL_TXCHARDISPMODE1", + "GTXE2_CHANNEL_RXPCD1DONE", + "GTXE2_IMUX21_2", + "GTXE2_LOGIC_OUTS_B23_3", + "GTXE2_IMUX39_10", + "GTXE2_CHANNEL_TXQPIBIASEN", + "GTXE2_LOGIC_OUTS_B9_2", + "GTXE2_LOGIC_OUTS_B0_2", + "GTXE2_CHANNEL_RXUSERRDY", + "GTXE2_CHANNEL_DRPDO3", + "GTXE2_CHANNEL_EYESCANRESET", + "GTXE2_BYP7_1", + "GTXE2_LOGIC_OUTS_B12_6", + "GTXE2_CLK0_7", + "GTXE2_FAN0_7", + "GTXE2_CHANNEL_RXPHALIGNEN", + "GTXE2_IMUX24_5", + "GTXE2_CHANNEL_TXMARGIN1", + "GTXE2_CHANNEL_TXCHARDISPVAL0", + "GTXE2_IMUX8_5", + "GTXE2_IMUX14_8", + "GTXE2_CHANNEL_RXDATA0", + "GTXE2_FAN1_7", + "GTXE2_CHANNEL_RXPOLARITY", + "GTXE2_IMUX0_1", + "GTXE2_IMUX16_7", + "GTXE2_CHANNEL_TXSEQUENCE2", + "GTXE2_IMUX47_7", + "GTXE2_CHANNEL_RXPCOMMAALIGNEN", + "GTXE2_IMUX42_1", + "GTXE2_LOGIC_OUTS_B18_10", + "GTXE2_CHANNEL_GTRSVD1", + "GTXE2_LOGIC_OUTS_B7_0", + "GTXE2_CLK0_4", + "GTXE2_CHANNEL_TX8B10BBYPASS0", + "GTXE2_LOGIC_OUTS_B18_4", + "GTXE2_LOGIC_OUTS_B23_4", + "GTXE2_CHANNEL_PCSRSVDIN8", + "GTXE2_IMUX0_9", + "GTXE2_LOGIC_OUTS_B1_8", + "GTXE2_BYP1_8", + "GTXE2_LOGIC_OUTS_B7_5", + "GTXE2_CHANNEL_TXPCSRESET", + "GTXE2_CHANNEL_TXOUTCLKSEL2", + "GTXE2_CHANNEL_TXCHARDISPVAL7", + "GTXE2_CHANNEL_RXDATA3", + "GTXE2_IMUX47_5", + "GTXE2_CHANNEL_TXMAINCURSOR6", + "GTXE2_CHANNEL_RXPHSLIPMONITOR3", + "GTXE2_LOGIC_OUTS_B9_4", + "GTXE2_IMUX7_3", + "GTXE2_CHANNEL_PMASCANIN1", + "GTXE2_IMUX36_9", + "GTXE2_CHANNEL_TSTOUT2", + "GTXE2_IMUX27_3", + "GTXE2_LOGIC_OUTS_B19_4", + "GTXE2_IMUX27_0", + "GTXE2_CHANNEL_RXCLKCORCNT1", + "GTXE2_CHANNEL_TXDATA46", + "GTXE2_CHANNEL_RXDFEXYDHOLD", + "GTXE2_LOGIC_OUTS_B22_0", + "GTXE2_BYP2_5", + "GTXE2_CHANNEL_EDTBYPASS", + "GTXE2_CHANNEL_RXDATA40", + "GTXE2_IMUX42_6", + "GTXE2_CHANNEL_TXCHARDISPVAL6", + "GTXE2_LOGIC_OUTS_B16_9", + "GTXE2_LOGIC_OUTS_B11_8", + "GTXE2_LOGIC_OUTS_B14_0", + "GTXE2_CTRL1_3", + "GTXE2_CHANNEL_RXDATA23", + "GTXE2_IMUX32_7", + "GTXE2_CHANNEL_PMASCANIN4", + "GTXE2_IMUX31_8", + "GTXE2_LOGIC_OUTS_B4_6", + "GTXE2_CHANNEL_RXN_PAD", + "GTXE2_BYP2_9", + "GTXE2_IMUX18_5", + "GTXE2_CHANNEL_TXELECIDLE", + "GTXE2_LOGIC_OUTS_B13_8", + "GTXE2_IMUX46_6", + "GTXE2_CHANNEL_RXCHANISALIGNED", + "GTXE2_IMUX32_5", + "GTXE2_IMUX38_6", + "GTXE2_IMUX30_4", + "GTXE2_LOGIC_OUTS_B17_5", + "GTXE2_CLK0_3", + "GTXE2_IMUX25_2", + "GTXE2_IMUX9_3", + "GTXE2_IMUX32_1", + "GTXE2_CHANNEL_TXDIFFCTRL3", + "GTXE2_IMUX31_0", + "GTXE2_CHANNEL_RXDISPERR4", + "GTXE2_IMUX17_9", + "GTXE2_CHANNEL_SCANOUT2", + "GTXE2_FAN0_9", + "GTXE2_CHANNEL_TXPOSTCURSOR3", + "GTXE2_CHANNEL_TXOUTCLKSEL1", + "GTXE2_LOGIC_OUTS_B1_10", + "GTXE2_IMUX28_1", + "GTXE2_CHANNEL_RXPCSRESET", + "GTXE2_CHANNEL_TXHEADER2", + "GTXE2_IMUX7_10", + "GTXE2_CHANNEL_TXPOSTCURSOR2", + "GTXE2_IMUX20_6", + "GTXE2_BYP7_8", + "GTXE2_FAN5_0", + "GTXE2_CHANNEL_SCANIN1", + "GTXE2_CHANNEL_PMASCANMODEB", + "GTXE2_IMUX40_4", + "GTXE2_LOGIC_OUTS_B10_5", + "GTXE2_CHANNEL_TXPISOPD", + "GTXE2_LOGIC_OUTS_B23_1", + "GTXE2_CHANNEL_QPLLCLK", + "GTXE2_IMUX8_10", + "GTXE2_CHANNEL_RXDLYSRESET", + "GTXE2_IMUX16_5", + "GTXE2_IMUX9_6", + "GTXE2_CHANNEL_TXN", + "GTXE2_LOGIC_OUTS_B1_5", + "GTXE2_BYP2_4", + "GTXE2_CHANNEL_PCSRSVDOUT3", + "GTXE2_BYP4_5", + "GTXE2_CLK1_0", + "GTXE2_IMUX44_6", + "GTXE2_IMUX43_8", + "GTXE2_IMUX14_0", + "GTXE2_BYP7_0", + "GTXE2_CHANNEL_REFCLK0", + "GTXE2_CHANNEL_RXPMARESET", + "GTXE2_CHANNEL_RXCHANBONDSEQ", + "GTXE2_CHANNEL_TXCOMFINISH", + "GTXE2_IMUX7_6", + "GTXE2_CHANNEL_TXBUFDIFFCTRL1", + "GTXE2_IMUX17_0", + "GTXE2_CHANNEL_EYESCANDATAERROR", + "GTXE2_IMUX11_1", + "GTXE2_CHANNEL_TXDATA11", + "GTXE2_LOGIC_OUTS_B1_3", + "GTXE2_CHANNEL_RXCHBONDI0", + "GTXE2_CHANNEL_RXCHBONDLEVEL0", + "GTXE2_CHANNEL_RXDATA1", + "GTXE2_LOGIC_OUTS_B4_10", + "GTXE2_IMUX34_3", + "GTXE2_IMUX14_9", + "GTXE2_CHANNEL_RXCHARISCOMMA0", + "GTXE2_FAN4_6", + "GTXE2_IMUX14_4", + "GTXE2_CHANNEL_TSTOUT5", + "GTXE2_LOGIC_OUTS_B15_7", + "GTXE2_CHANNEL_PCSRSVDOUT9", + "GTXE2_IMUX13_7", + "GTXE2_FAN4_4", + "GTXE2_LOGIC_OUTS_B2_8", + "GTXE2_CHANNEL_TXPHALIGNEN", + "GTXE2_IMUX37_0", + "GTXE2_CHANNEL_TXOUTCLK_3", + "GTXE2_CHANNEL_GTRSVD6", + "GTXE2_CHANNEL_RXMONITORSEL1", + "GTXE2_CHANNEL_TXCHARDISPVAL4", + "GTXE2_CHANNEL_RXDATA16", + "GTXE2_IMUX40_7", + "GTXE2_CHANNEL_PCSRSVDIN12", + "GTXE2_IMUX38_9", + "GTXE2_CHANNEL_PMARSVDIN4", + "GTXE2_IMUX28_0", + "GTXE2_BYP4_8", + "GTXE2_CHANNEL_TXBUFSTATUS0", + "GTXE2_CHANNEL_RXCHBONDLEVEL1", + "GTXE2_IMUX19_2", + "GTXE2_LOGIC_OUTS_B7_8", + "GTXE2_CHANNEL_TXMARGIN2", + "GTXE2_IMUX41_6", + "GTXE2_CHANNEL_DRPDO5", + "GTXE2_CHANNEL_RXDATA55", + "GTXE2_IMUX23_8", + "GTXE2_BYP1_5", + "GTXE2_CHANNEL_RXSYSCLKSEL1", + "GTXE2_LOGIC_OUTS_B16_7", + "GTXE2_CHANNEL_RXCHBONDI2", + "GTXE2_CHANNEL_TXSEQUENCE1", + "GTXE2_CHANNEL_SOUTHREFCLK0", + "GTXE2_IMUX16_3", + "GTXE2_IMUX28_6", + "GTXE2_IMUX35_4", + "GTXE2_LOGIC_OUTS_B16_1", + "GTXE2_CHANNEL_RXDATA57", + "GTXE2_CHANNEL_TXDATA18", + "GTXE2_LOGIC_OUTS_B14_3", + "GTXE2_IMUX27_7", + "GTXE2_CHANNEL_DMONITOROUT1", + "GTXE2_IMUX39_7", + "GTXE2_LOGIC_OUTS_B17_1", + "GTXE2_IMUX27_10", + "GTXE2_CHANNEL_RXCHARISCOMMA1", + "GTXE2_CHANNEL_RXLPMHFHOLD", + "GTXE2_IMUX27_6", + "GTXE2_IMUX6_5", + "GTXE2_BYP5_2", + "GTXE2_CHANNEL_SETERRSTATUS", + "GTXE2_CHANNEL_TXCHARDISPVAL1", + "GTXE2_LOGIC_OUTS_B12_9", + "GTXE2_CHANNEL_PCSRSVDIN9", + "GTXE2_IMUX46_4", + "GTXE2_CHANNEL_PMASCANIN3", + "GTXE2_IMUX20_8", + "GTXE2_CHANNEL_CPLLLOCKEN", + "GTXE2_CHANNEL_DRPADDR6", + "GTXE2_IMUX45_4", + "GTXE2_LOGIC_OUTS_B1_1", + "GTXE2_IMUX42_3", + "GTXE2_BYP1_3", + "GTXE2_CTRL1_0", + "GTXE2_CHANNEL_TXRUNDISP0", + "GTXE2_IMUX42_9", + "GTXE2_CHANNEL_RXDFETAP5OVRDEN", + "GTXE2_IMUX47_2", + "GTXE2_IMUX0_3", + "GTXE2_CTRL0_5", + "GTXE2_CHANNEL_PCSRSVDIN20", + "GTXE2_BYP3_9", + "GTXE2_CHANNEL_TSTCLK1", + "GTXE2_BYP2_1", + "GTXE2_CHANNEL_RXCHARISK1", + "GTXE2_IMUX33_7", + "GTXE2_IMUX12_8", + "GTXE2_IMUX35_2", + "GTXE2_IMUX10_5", + "GTXE2_IMUX34_8", + "GTXE2_CHANNEL_TSTPD1", + "GTXE2_IMUX2_9", + "GTXE2_CHANNEL_TXDATA2", + "GTXE2_IMUX21_1", + "GTXE2_LOGIC_OUTS_B22_7", + "GTXE2_CHANNEL_TXOUTCLK_1", + "GTXE2_FAN1_10", + "GTXE2_IMUX32_3", + "GTXE2_LOGIC_OUTS_B13_10", + "GTXE2_LOGIC_OUTS_B7_6", + "GTXE2_FAN7_3", + "GTXE2_CHANNEL_TXOUTCLKPCS", + "GTXE2_IMUX4_6", + "GTXE2_CHANNEL_TSTOUT3", + "GTXE2_CHANNEL_RXNOTINTABLE7", + "GTXE2_LOGIC_OUTS_B12_8", + "GTXE2_CHANNEL_RXDATA61", + "GTXE2_CHANNEL_RXDATA56", + "GTXE2_FAN3_2", + "GTXE2_LOGIC_OUTS_B8_5", + "GTXE2_CLK0_5", + "GTXE2_FAN2_10", + "GTXE2_IMUX41_8", + "GTXE2_BYP5_9", + "GTXE2_CHANNEL_DRPDI5", + "GTXE2_CHANNEL_TXSEQUENCE0", + "GTXE2_IMUX26_10", + "GTXE2_CHANNEL_RXSTARTOFSEQ", + "GTXE2_BYP1_0", + "GTXE2_IMUX47_1", + "GTXE2_CHANNEL_PMARSVDIN21", + "GTXE2_IMUX18_10", + "GTXE2_CHANNEL_TXPOSTCURSOR4", + "GTXE2_LOGIC_OUTS_B15_3", + "GTXE2_CHANNEL_RXCOMMADETEN", + "GTXE2_FAN0_1", + "GTXE2_CHANNEL_GTRSVD7", + "GTXE2_CLK1_8", + "GTXE2_CHANNEL_TXDIFFCTRL0", + "GTXE2_IMUX22_2", + "GTXE2_LOGIC_OUTS_B4_5", + "GTXE2_CHANNEL_TXBUFSTATUS1", + "GTXE2_IMUX6_10", + "GTXE2_CHANNEL_SCANIN3", + "GTXE2_FAN0_0", + "GTXE2_LOGIC_OUTS_B22_6", + "GTXE2_LOGIC_OUTS_B13_4", + "GTXE2_CHANNEL_RXDATA12", + "GTXE2_LOGIC_OUTS_B7_3", + "GTXE2_IMUX41_5", + "GTXE2_CHANNEL_RXOUTCLK_0", + "GTXE2_IMUX20_9", + "GTXE2_IMUX27_8", + "GTXE2_CHANNEL_RXDFELFHOLD", + "GTXE2_CHANNEL_PCSRSVDIN14", + "GTXE2_FAN1_6", + "GTXE2_IMUX34_4", + "GTXE2_CHANNEL_RXDISPERR2", + "GTXE2_CHANNEL_TXRUNDISP3", + "GTXE2_CHANNEL_CPLLRESET", + "GTXE2_BYP5_6", + "GTXE2_LOGIC_OUTS_B6_1", + "GTXE2_IMUX12_4", + "GTXE2_FAN2_2", + "GTXE2_CHANNEL_RXDATA47", + "GTXE2_CHANNEL_DRPDO9", + "GTXE2_LOGIC_OUTS_B14_6", + "GTXE2_CHANNEL_DRPDO1", + "GTXE2_CHANNEL_TXPRBSFORCEERR", + "GTXE2_LOGIC_OUTS_B16_4", + "GTXE2_IMUX16_8", + "GTXE2_LOGIC_OUTS_B14_7", + "GTXE2_LOGIC_OUTS_B23_8", + "GTXE2_FAN6_4", + "GTXE2_LOGIC_OUTS_B0_3", + "GTXE2_IMUX29_5", + "GTXE2_CHANNEL_RXCDRLOCK", + "GTXE2_CHANNEL_GTNORTHREFCLK0", + "GTXE2_IMUX31_1", + "GTXE2_IMUX20_5", + "GTXE2_CHANNEL_LOOPBACK2", + "GTXE2_CHANNEL_RXPRBSERR", + "GTXE2_IMUX7_0", + "GTXE2_BYP0_2", + "GTXE2_CHANNEL_RXGEARBOXSLIP", + "GTXE2_LOGIC_OUTS_B8_9", + "GTXE2_CHANNEL_PMASCANOUT3", + "GTXE2_CHANNEL_TSTIN1", + "GTXE2_LOGIC_OUTS_B21_9", + "GTXE2_FAN4_1", + "GTXE2_LOGIC_OUTS_B6_10", + "GTXE2_IMUX35_6", + "GTXE2_IMUX24_9", + "GTXE2_CHANNEL_TSTIN18", + "GTXE2_CHANNEL_RXDISPERR5", + "GTXE2_FAN6_10", + "GTXE2_IMUX32_0", + "GTXE2_CHANNEL_CLKRSVD1", + "GTXE2_CTRL1_6", + "GTXE2_CHANNEL_TSTOUT7", + "GTXE2_LOGIC_OUTS_B9_8", + "GTXE2_IMUX38_7", + "GTXE2_IMUX5_2", + "GTXE2_CLK0_2", + "GTXE2_CHANNEL_DRPDI11", + "GTXE2_CHANNEL_RXPHALIGN", + "GTXE2_LOGIC_OUTS_B0_0", + "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", + "GTXE2_CHANNEL_TXDATA58", + "GTXE2_LOGIC_OUTS_B3_4", + "GTXE2_CHANNEL_RXUSRCLK2", + "GTXE2_CHANNEL_TXDATA50", + "GTXE2_CHANNEL_RXDATA24", + "GTXE2_CHANNEL_PCSRSVDIN0", + "GTXE2_CHANNEL_RXCHBONDO0", + "GTXE2_LOGIC_OUTS_B22_4", + "GTXE2_IMUX13_1", + "GTXE2_CHANNEL_TXCHARDISPMODE3", + "GTXE2_CHANNEL_RXRATE0", + "GTXE2_CHANNEL_RXDATA27", + "GTXE2_IMUX28_2", + "GTXE2_IMUX14_7", + "GTXE2_LOGIC_OUTS_B20_2", + "GTXE2_IMUX44_5", + "GTXE2_BYP4_9", + "GTXE2_IMUX36_1", + "GTXE2_BYP2_7", + "GTXE2_CHANNEL_TXDATA12", + "GTXE2_CHANNEL_EDTUPDATE", + "GTXE2_IMUX26_3", + "GTXE2_CHANNEL_RXDISPERR6", + "GTXE2_FAN3_3", + "GTXE2_CHANNEL_TXPHALIGN", + "GTXE2_CHANNEL_TXDIFFCTRL1", + "GTXE2_LOGIC_OUTS_B4_0", + "GTXE2_IMUX9_10", + "GTXE2_CHANNEL_TXDATA26", + "GTXE2_CHANNEL_TXP_PAD", + "GTXE2_CHANNEL_RXOUTCLK_1", + "GTXE2_IMUX12_7", + "GTXE2_IMUX33_5", + "GTXE2_IMUX47_3", + "GTXE2_LOGIC_OUTS_B14_8", + "GTXE2_CHANNEL_RXDEBUGPULSE", + "GTXE2_CHANNEL_RXDATA4", + "GTXE2_LOGIC_OUTS_B12_7", + "GTXE2_IMUX20_2", + "GTXE2_CHANNEL_RXNOTINTABLE4", + "GTXE2_CHANNEL_RXDFEUTHOLD", + "GTXE2_CHANNEL_GTREFCLK0", + "GTXE2_IMUX37_9", + "GTXE2_CHANNEL_RXBUFSTATUS1", + "GTXE2_IMUX4_7", + "GTXE2_BYP1_9", + "GTXE2_CHANNEL_DRPDO12", + "GTXE2_IMUX31_6", + "GTXE2_CHANNEL_RXMONITOROUT5", + "GTXE2_FAN5_6", + "GTXE2_CHANNEL_TXDATA7", + "GTXE2_CHANNEL_TSTOUT9", + "GTXE2_CHANNEL_RXNOTINTABLE3", + "GTXE2_CHANNEL_EYESCANTRIGGER", + "GTXE2_IMUX10_7", + "GTXE2_CHANNEL_GTSOUTHREFCLK0", + "GTXE2_LOGIC_OUTS_B19_8", + "GTXE2_LOGIC_OUTS_B7_10", + "GTXE2_CHANNEL_RXCDRRESETRSV", + "GTXE2_CHANNEL_RXSLIDE", + "GTXE2_CHANNEL_TXPRBSSEL2", + "GTXE2_IMUX43_10", + "GTXE2_CHANNEL_RXCHBONDI1", + "GTXE2_BYP3_1", + "GTXE2_CHANNEL_RXP", + "GTXE2_IMUX13_6", + "GTXE2_LOGIC_OUTS_B5_2", + "GTXE2_LOGIC_OUTS_B9_6", + "GTXE2_IMUX35_8", + "GTXE2_CHANNEL_TXRATE2", + "GTXE2_CHANNEL_CPLLLOCKDETCLK", + "GTXE2_IMUX36_5", + "GTXE2_CHANNEL_RXLPMEN", + "GTXE2_CHANNEL_RXCDROVRDEN", + "GTXE2_BYP6_3", + "GTXE2_BYP3_4", + "GTXE2_LOGIC_OUTS_B21_6", + "GTXE2_LOGIC_OUTS_B12_10", + "GTXE2_IMUX43_3", + "GTXE2_FAN4_10", + "GTXE2_IMUX24_2", + "GTXE2_IMUX46_10", + "GTXE2_LOGIC_OUTS_B5_5", + "GTXE2_CHANNEL_TXOUTCLKFABRIC", + "GTXE2_CHANNEL_TSTIN10", + "GTXE2_IMUX36_6", + "GTXE2_BYP4_10", + "GTXE2_CHANNEL_RXDFEXYDOVRDEN", + "GTXE2_IMUX34_0", + "GTXE2_CLK0_1", + "GTXE2_IMUX11_10", + "GTXE2_LOGIC_OUTS_B10_4", + "GTXE2_LOGIC_OUTS_B20_1", + "GTXE2_CHANNEL_TXMAINCURSOR2", + "GTXE2_CHANNEL_RXPD1", + "GTXE2_IMUX32_10", + "GTXE2_LOGIC_OUTS_B7_2", + "GTXE2_LOGIC_OUTS_B0_1", + "GTXE2_CHANNEL_RXDATA18", + "GTXE2_IMUX21_9", + "GTXE2_IMUX3_0", + "GTXE2_CTRL0_6", + "GTXE2_CHANNEL_RXCDRFREQRESET", + "GTXE2_IMUX45_2", + "GTXE2_LOGIC_OUTS_B13_2", + "GTXE2_CHANNEL_RXDISPERR1", + "GTXE2_CTRL0_0", + "GTXE2_FAN6_8", + "GTXE2_IMUX30_0", + "GTXE2_IMUX43_6", + "GTXE2_BYP1_6", + "GTXE2_IMUX28_3", + "GTXE2_IMUX18_0", + "GTXE2_LOGIC_OUTS_B10_7", + "GTXE2_CHANNEL_PCSRSVDOUT8", + "GTXE2_FAN6_5", + "GTXE2_CLK0_0", + "GTXE2_LOGIC_OUTS_B9_3", + "GTXE2_CHANNEL_TXDATA55", + "GTXE2_LOGIC_OUTS_B20_3", + "GTXE2_CHANNEL_PMASCANIN0", + "GTXE2_IMUX29_10", + "GTXE2_CHANNEL_DRPDI2", + "GTXE2_LOGIC_OUTS_B20_4", + "GTXE2_CHANNEL_RXDFECM1EN", + "GTXE2_CHANNEL_RXCHARISCOMMA3", + "GTXE2_CHANNEL_RXCHARISCOMMA5", + "GTXE2_CHANNEL_PMASCANENB", + "GTXE2_IMUX11_6", + "GTXE2_BYP3_2", + "GTXE2_CHANNEL_RXCHARISCOMMA7", + "GTXE2_CHANNEL_TXPHINIT", + "GTXE2_IMUX25_1", + "GTXE2_BYP7_4", + "GTXE2_CHANNEL_RXOUTCLKSEL0", + "GTXE2_IMUX1_1", + "GTXE2_CHANNEL_TXDATA51", + "GTXE2_IMUX35_3", + "GTXE2_LOGIC_OUTS_B22_10", + "GTXE2_FAN5_7", + "GTXE2_CHANNEL_RXDFETAP3OVRDEN", + "GTXE2_CHANNEL_PMARSVDIN20", + "GTXE2_CHANNEL_RXPHMONITOR2", + "GTXE2_CHANNEL_RXDATA25", + "GTXE2_CHANNEL_RXDATA9", + "GTXE2_CHANNEL_TSTOUT0", + "GTXE2_CHANNEL_TXPRECURSOR4", + "GTXE2_IMUX5_5", + "GTXE2_IMUX22_5", + "GTXE2_IMUX30_10", + "GTXE2_LOGIC_OUTS_B19_3", + "GTXE2_FAN1_3", + "GTXE2_CHANNEL_RXCDRHOLD", + "GTXE2_LOGIC_OUTS_B10_6", + "GTXE2_LOGIC_OUTS_B16_5", + "GTXE2_FAN1_2", + "GTXE2_IMUX45_1", + "GTXE2_IMUX19_7", + "GTXE2_CHANNEL_RXDATA43", + "GTXE2_CHANNEL_TXUSRCLK2", + "GTXE2_IMUX26_6", + "GTXE2_IMUX3_6", + "GTXE2_CHANNEL_TXCHARISK4", + "GTXE2_LOGIC_OUTS_B11_2", + "GTXE2_CHANNEL_TSTPD3", + "GTXE2_IMUX38_3", + "GTXE2_LOGIC_OUTS_B12_3", + "GTXE2_IMUX45_10", + "GTXE2_FAN7_5", + "GTXE2_IMUX38_5", + "GTXE2_BYP5_4", + "GTXE2_CHANNEL_PCSRSVDIN3", + "GTXE2_LOGIC_OUTS_B4_9", + "GTXE2_LOGIC_OUTS_B2_5", + "GTXE2_IMUX26_2", + "GTXE2_CHANNEL_SCANOUT4", + "GTXE2_CHANNEL_CFGRESET", + "GTXE2_IMUX33_3", + "GTXE2_CHANNEL_RXDATA20", + "GTXE2_IMUX38_10", + "GTXE2_CHANNEL_TSTOUT1", + "GTXE2_IMUX1_8", + "GTXE2_CHANNEL_TXDATA20", + "GTXE2_CHANNEL_TSTPD0", + "GTXE2_CHANNEL_TXDATA37", + "GTXE2_IMUX23_1", + "GTXE2_IMUX36_0", + "GTXE2_LOGIC_OUTS_B16_10", + "GTXE2_IMUX4_2", + "GTXE2_IMUX18_1", + "GTXE2_LOGIC_OUTS_B12_0", + "GTXE2_CHANNEL_RXDATA30", + "GTXE2_IMUX44_10", + "GTXE2_IMUX25_6", + "GTXE2_CHANNEL_PMASCANOUT4", + "GTXE2_LOGIC_OUTS_B17_10", + "GTXE2_CHANNEL_TXINHIBIT", + "GTXE2_IMUX3_5", + "GTXE2_CHANNEL_TXDATA39", + "GTXE2_IMUX15_10", + "GTXE2_CHANNEL_TXPDELECIDLEMODE", + "GTXE2_IMUX26_8", + "GTXE2_CHANNEL_GTTXRESET", + "GTXE2_CHANNEL_TXCHARISK2", + "GTXE2_IMUX6_3", + "GTXE2_CHANNEL_RXPRBSSEL1", + "GTXE2_CHANNEL_RXPHSLIPMONITOR0", + "GTXE2_CLK0_10", + "GTXE2_CHANNEL_RXDFELPMRESET", + "GTXE2_IMUX42_10", + "GTXE2_IMUX2_1", + "GTXE2_LOGIC_OUTS_B16_2", + "GTXE2_CHANNEL_TXCOMSAS", + "GTXE2_IMUX6_7", + "GTXE2_IMUX29_6", + "GTXE2_IMUX31_4", + "GTXE2_CHANNEL_RXLPMLFHOLD", + "GTXE2_CHANNEL_PCSRSVDOUT4", + "GTXE2_CHANNEL_RXDATA59", + "GTXE2_CHANNEL_DRPADDR1", + "GTXE2_LOGIC_OUTS_B20_7", + "GTXE2_FAN2_1", + "GTXE2_FAN7_7", + "GTXE2_IMUX12_6", + "GTXE2_CHANNEL_TXDATA21", + "GTXE2_IMUX29_2", + "GTXE2_CHANNEL_RXDATA45", + "GTXE2_CHANNEL_TX8B10BBYPASS1", + "GTXE2_CHANNEL_SCANMODEB", + "GTXE2_IMUX36_7", + "GTXE2_IMUX17_3", + "GTXE2_CHANNEL_TXHEADER0", + "GTXE2_LOGIC_OUTS_B13_7", + "GTXE2_IMUX29_0", + "GTXE2_LOGIC_OUTS_B3_5", + "GTXE2_CHANNEL_TXCHARDISPMODE7", + "GTXE2_CHANNEL_GTRSVD12", + "GTXE2_LOGIC_OUTS_B1_7", + "GTXE2_CHANNEL_SCANOUT0", + "GTXE2_IMUX24_7", + "GTXE2_IMUX15_7", + "GTXE2_CHANNEL_RXDFEXYDEN", + "GTXE2_IMUX1_7", + "GTXE2_IMUX23_3", + "GTXE2_CHANNEL_TX8B10BBYPASS3", + "GTXE2_IMUX34_1", + "GTXE2_CHANNEL_RXCHARISCOMMA6", + "GTXE2_CHANNEL_TXOUTCLK_2", + "GTXE2_CHANNEL_TXDATA56", + "GTXE2_LOGIC_OUTS_B5_10", + "GTXE2_IMUX25_0", + "GTXE2_CHANNEL_PCSRSVDIN11", + "GTXE2_CHANNEL_TXRESETDONE", + "GTXE2_CHANNEL_TSTOUT4", + "GTXE2_IMUX43_9", + "GTXE2_CHANNEL_TSTOUT8", + "GTXE2_LOGIC_OUTS_B1_2", + "GTXE2_BYP7_6", + "GTXE2_FAN2_4", + "GTXE2_IMUX18_8", + "GTXE2_IMUX39_0", + "GTXE2_CHANNEL_RXDFETAP2HOLD", + "GTXE2_BYP6_6", + "GTXE2_CHANNEL_TXPHALIGNDONE", + "GTXE2_LOGIC_OUTS_B2_6", + "GTXE2_IMUX37_5", + "GTXE2_LOGIC_OUTS_B8_1", + "GTXE2_CHANNEL_TXDATA35", + "GTXE2_CHANNEL_TXPRECURSORINV", + "GTXE2_IMUX10_9", + "GTXE2_IMUX38_1", + "GTXE2_IMUX14_6", + "GTXE2_CHANNEL_PMARSVDIN2", + "GTXE2_IMUX18_6", + "GTXE2_FAN0_5", + "GTXE2_CHANNEL_RXCHBONDSLAVE", + "GTXE2_CHANNEL_DRPADDR2", + "GTXE2_CHANNEL_RXDATA29", + "GTXE2_CHANNEL_RXMONITOROUT6", + "GTXE2_CHANNEL_TXDATA54", + "GTXE2_BYP4_0", + "GTXE2_CHANNEL_PCSRSVDOUT10", + "GTXE2_LOGIC_OUTS_B14_10", + "GTXE2_CHANNEL_RXCHBONDI4", + "GTXE2_IMUX44_1", + "GTXE2_CHANNEL_TXDLYEN", + "GTXE2_LOGIC_OUTS_B17_4", + "GTXE2_LOGIC_OUTS_B10_0", + "GTXE2_FAN0_10", + "GTXE2_IMUX39_4", + "GTXE2_CHANNEL_TXMAINCURSOR5", + "GTXE2_IMUX7_7", + "GTXE2_CHANNEL_RXNOTINTABLE2", + "GTXE2_CHANNEL_DRPDI12", + "GTXE2_IMUX14_5", + "GTXE2_LOGIC_OUTS_B5_6", + "GTXE2_FAN2_7", + "GTXE2_CHANNEL_DRPDI7", + "GTXE2_CHANNEL_TXQPIWEAKPUP", + "GTXE2_CHANNEL_RXDISPERR0", + "GTXE2_BYP2_6", + "GTXE2_CHANNEL_RXPHOVRDEN", + "GTXE2_CHANNEL_TX8B10BBYPASS4", + "GTXE2_IMUX21_5", + "GTXE2_CHANNEL_EDTCONFIGURATION", + "GTXE2_CHANNEL_DRPDO0", + "GTXE2_IMUX24_10", + "GTXE2_IMUX43_4", + "GTXE2_LOGIC_OUTS_B13_6", + "GTXE2_FAN1_4", + "GTXE2_CHANNEL_RXOUTCLK_3", + "GTXE2_IMUX0_4", + "GTXE2_LOGIC_OUTS_B8_0", + "GTXE2_CHANNEL_TXDATA33", + "GTXE2_CHANNEL_SCANCLK", + "GTXE2_CHANNEL_TX8B10BBYPASS7", + "GTXE2_IMUX25_7", + "GTXE2_BYP5_0", + "GTXE2_IMUX46_5", + "GTXE2_IMUX13_4", + "GTXE2_LOGIC_OUTS_B8_2", + "GTXE2_CHANNEL_GTRSVD2", + "GTXE2_CHANNEL_GTSOUTHREFCLK1", + "GTXE2_CHANNEL_CLKRSVD3", + "GTXE2_CHANNEL_GTQPLLCLK", + "GTXE2_CHANNEL_RXDLYSRESETDONE", + "GTXE2_CHANNEL_RXDATA48", + "GTXE2_CHANNEL_RXHEADER2", + "GTXE2_FAN7_4", + "GTXE2_IMUX30_7", + "GTXE2_CLK0_6", + "GTXE2_CHANNEL_RXDATA22", + "GTXE2_IMUX3_9", + "GTXE2_CHANNEL_PCSRSVDOUT2", + "GTXE2_IMUX34_10", + "GTXE2_CHANNEL_RXPHSLIPMONITOR2", + "GTXE2_CHANNEL_TXDATA27", + "GTXE2_CHANNEL_PMASCANCLK4", + "GTXE2_CHANNEL_TXGEARBOXREADY", + "GTXE2_IMUX44_7", + "GTXE2_CHANNEL_RXDATA53", + "GTXE2_LOGIC_OUTS_B17_6", + "GTXE2_CHANNEL_TSTIN17", + "GTXE2_CHANNEL_RXCHBONDO1", + "GTXE2_LOGIC_OUTS_B21_4", + "GTXE2_IMUX44_4", + "GTXE2_IMUX13_3", + "GTXE2_FAN7_8", + "GTXE2_CLK0_8", + "GTXE2_IMUX36_8", + "GTXE2_CHANNEL_TXSTARTSEQ", + "GTXE2_IMUX10_2", + "GTXE2_IMUX41_0", + "GTXE2_IMUX3_10", + "GTXE2_CHANNEL_TXSEQUENCE5", + "GTXE2_LOGIC_OUTS_B7_4", + "GTXE2_CHANNEL_TXMARGIN0", + "GTXE2_IMUX15_3", + "GTXE2_BYP7_3", + "GTXE2_CHANNEL_RXDATA41", + "GTXE2_CHANNEL_DRPDI1", + "GTXE2_LOGIC_OUTS_B2_0", + "GTXE2_CHANNEL_RXDATA13", + "GTXE2_LOGIC_OUTS_B15_0", + "GTXE2_CHANNEL_RXDFELFOVRDEN", + "GTXE2_IMUX37_10", + "GTXE2_CHANNEL_PMARSVDIN23", + "GTXE2_CHANNEL_RXDATA63", + "GTXE2_CHANNEL_RXDATA60", + "GTXE2_CHANNEL_EDTCLOCK", + "GTXE2_CHANNEL_RXDATA44", + "GTXE2_CHANNEL_RXCLKCORCNT0", + "GTXE2_FAN4_8", + "GTXE2_CHANNEL_DMONITOROUT7", + "GTXE2_IMUX23_9", + "GTXE2_IMUX2_0", + "GTXE2_IMUX38_4", + "GTXE2_CHANNEL_RXOSOVRDEN", + "GTXE2_IMUX28_5", + "GTXE2_IMUX9_0", + "GTXE2_CHANNEL_RXMONITOROUT0", + "GTXE2_CHANNEL_TXRATE0", + "GTXE2_CHANNEL_TX8B10BEN", + "GTXE2_IMUX42_0", + "GTXE2_IMUX38_8", + "GTXE2_IMUX5_6", + "GTXE2_IMUX7_8", + "GTXE2_CHANNEL_TXDIFFCTRL2", + "GTXE2_CHANNEL_GTRSVD3", + "GTXE2_CHANNEL_DRPDI15", + "GTXE2_IMUX2_8", + "GTXE2_IMUX18_9", + "GTXE2_LOGIC_OUTS_B10_10", + "GTXE2_CHANNEL_RXRATE1", + "GTXE2_LOGIC_OUTS_B8_8", + "GTXE2_CLK1_6", + "GTXE2_CHANNEL_RXMONITOROUT3", + "GTXE2_CHANNEL_TXOUTCLKSEL0", + "GTXE2_CHANNEL_TXSEQUENCE4", + "GTXE2_CHANNEL_TX8B10BBYPASS5", + "GTXE2_CHANNEL_DRPDO11", + "GTXE2_CTRL0_2", + "GTXE2_LOGIC_OUTS_B10_3", + "GTXE2_IMUX46_8", + "GTXE2_LOGIC_OUTS_B19_0", + "GTXE2_BYP0_4", + "GTXE2_CHANNEL_TXCHARDISPMODE4", + "GTXE2_IMUX29_7", + "GTXE2_IMUX26_1", + "GTXE2_CHANNEL_PHYSTATUS", + "GTXE2_LOGIC_OUTS_B23_7", + "GTXE2_CHANNEL_TXPRBSSEL1", + "GTXE2_IMUX0_7", + "GTXE2_IMUX41_4", + "GTXE2_CHANNEL_TXDATA23", + "GTXE2_CHANNEL_RXDATA14", + "GTXE2_CHANNEL_RXDATA26", + "GTXE2_IMUX0_6", + "GTXE2_IMUX33_0", + "GTXE2_LOGIC_OUTS_B15_2", + "GTXE2_LOGIC_OUTS_B3_9", + "GTXE2_CHANNEL_DRPDO14", + "GTXE2_CHANNEL_TXDETECTRX", + "GTXE2_CHANNEL_RXDATA6", + "GTXE2_CHANNEL_TXDATA17", + "GTXE2_IMUX0_0", + "GTXE2_IMUX47_9", + "GTXE2_IMUX3_8", + "GTXE2_IMUX8_1", + "GTXE2_IMUX28_9", + "GTXE2_IMUX13_10", + "GTXE2_CHANNEL_TXSYSCLKSEL0", + "GTXE2_LOGIC_OUTS_B4_8", + "GTXE2_LOGIC_OUTS_B2_2", + "GTXE2_CHANNEL_GTRXRESET", + "GTXE2_IMUX21_4", + "GTXE2_CHANNEL_RXPHALIGNDONE", + "GTXE2_CHANNEL_RXDATA38", + "GTXE2_LOGIC_OUTS_B15_6", + "GTXE2_CHANNEL_GTRSVD14", + "GTXE2_CHANNEL_TXCHARISK6", + "GTXE2_FAN7_9", + "GTXE2_CHANNEL_RXDATA8", + "GTXE2_CHANNEL_DRPDO2", + "GTXE2_CHANNEL_RXDATA33", + "GTXE2_CHANNEL_PMASCANOUT1", + "GTXE2_LOGIC_OUTS_B18_3", + "GTXE2_LOGIC_OUTS_B11_1", + "GTXE2_CHANNEL_SOUTHREFCLK1", + "GTXE2_CHANNEL_TXDLYUPDOWN", + "GTXE2_IMUX38_2", + "GTXE2_LOGIC_OUTS_B20_9", + "GTXE2_LOGIC_OUTS_B17_3", + "GTXE2_LOGIC_OUTS_B15_5", + "GTXE2_IMUX11_3", + "GTXE2_CHANNEL_TXRUNDISP6", + "GTXE2_CHANNEL_TXPRECURSOR1", + "GTXE2_IMUX16_0", + "GTXE2_LOGIC_OUTS_B18_9", + "GTXE2_BYP2_2", + "GTXE2_CHANNEL_RXOUTCLKPCS", + "GTXE2_IMUX29_1", + "GTXE2_FAN6_6", + "GTXE2_FAN0_4", + "GTXE2_IMUX17_6", + "GTXE2_CHANNEL_RXCHARISCOMMA2", + "GTXE2_CHANNEL_RXPHMONITOR3", + "GTXE2_LOGIC_OUTS_B5_0", + "GTXE2_IMUX10_3", + "GTXE2_BYP4_6", + "GTXE2_CHANNEL_PMARSVDIN0", + "GTXE2_IMUX19_3", + "GTXE2_IMUX13_5", + "GTXE2_IMUX15_2", + "GTXE2_LOGIC_OUTS_B2_7", + "GTXE2_CHANNEL_DRPADDR3", + "GTXE2_CHANNEL_RXELECIDLEMODE1", + "GTXE2_LOGIC_OUTS_B6_3", + "GTXE2_LOGIC_OUTS_B3_8", + "GTXE2_LOGIC_OUTS_B1_6", + "GTXE2_CHANNEL_RXDFEAGCOVRDEN", + "GTXE2_CHANNEL_RXDLYBYPASS", + "GTXE2_CHANNEL_CPLLREFCLKSEL2", + "GTXE2_CHANNEL_RXDATA49", + "GTXE2_IMUX41_3", + "GTXE2_LOGIC_OUTS_B3_7", + "GTXE2_IMUX34_9", + "GTXE2_CHANNEL_RXMONITOROUT2", + "GTXE2_LOGIC_OUTS_B2_3", + "GTXE2_BYP6_0", + "GTXE2_CHANNEL_CLKRSVD0", + "GTXE2_IMUX16_4", + "GTXE2_CHANNEL_TSTIN5", + "GTXE2_CHANNEL_RXNOTINTABLE0", + "GTXE2_LOGIC_OUTS_B22_1", + "GTXE2_IMUX7_4", + "GTXE2_IMUX37_3", + "GTXE2_IMUX12_3", + "GTXE2_CHANNEL_TSTIN16", + "GTXE2_CHANNEL_TXDATA52", + "GTXE2_IMUX20_10", + "GTXE2_CHANNEL_DRPADDR5", + "GTXE2_BYP3_5", + "GTXE2_LOGIC_OUTS_B6_5", + "GTXE2_CHANNEL_TXDATA49", + "GTXE2_CHANNEL_SCANIN2", + "GTXE2_CHANNEL_RXDFEAGCHOLD", + "GTXE2_CHANNEL_TXCHARDISPVAL2", + "GTXE2_IMUX8_6", + "GTXE2_CHANNEL_TXDATA4", + "GTXE2_CTRL0_10", + "GTXE2_IMUX23_2", + "GTXE2_IMUX34_6", + "GTXE2_LOGIC_OUTS_B4_3", + "GTXE2_CHANNEL_RXOUTCLK_2", + "GTXE2_CHANNEL_RX8B10BEN", + "GTXE2_BYP6_1", + "GTXE2_CTRL1_4", + "GTXE2_LOGIC_OUTS_B13_0", + "GTXE2_IMUX26_5", + "GTXE2_IMUX13_0", + "GTXE2_LOGIC_OUTS_B22_2", + "GTXE2_CHANNEL_RXCOMINITDET", + "GTXE2_CHANNEL_TXDLYTESTENB", + "GTXE2_IMUX25_5", + "GTXE2_IMUX45_6", + "GTXE2_LOGIC_OUTS_B14_9", + "GTXE2_CHANNEL_SCANOUT1", + "GTXE2_IMUX22_0", + "GTXE2_IMUX5_3", + "GTXE2_CHANNEL_RXSYSCLKSEL0", + "GTXE2_IMUX22_7", + "GTXE2_LOGIC_OUTS_B23_0", + "GTXE2_IMUX14_3", + "GTXE2_CHANNEL_TXDATA22", + "GTXE2_CHANNEL_RXPHDLYPD", + "GTXE2_IMUX18_2", + "GTXE2_CHANNEL_DRPDI4", + "GTXE2_CHANNEL_RXCHARISK7", + "GTXE2_IMUX24_0", + "GTXE2_CHANNEL_RXDATA37", + "GTXE2_IMUX11_2", + "GTXE2_CHANNEL_TXSYSCLKSEL1", + "GTXE2_CHANNEL_RXRATE2", + "GTXE2_IMUX17_8", + "GTXE2_CHANNEL_RXDATA5", + "GTXE2_CHANNEL_TXDATA25", + "GTXE2_IMUX47_4", + "GTXE2_CHANNEL_PMASCANOUT0", + "GTXE2_IMUX17_2", + "GTXE2_BYP0_1", + "GTXE2_CHANNEL_RXDFETAP5HOLD", + "GTXE2_IMUX5_9", + "GTXE2_CTRL1_9", + "GTXE2_IMUX15_1", + "GTXE2_CHANNEL_RXOUTCLKSEL1", + "GTXE2_CHANNEL_DRPADDR7", + "GTXE2_CLK1_4" + ], + "pips": { + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO4->GTXE2_LOGIC_OUTS_B5_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXSTARTOFSEQ->GTXE2_LOGIC_OUTS_B18_8": { + "src_wire": "GTXE2_CHANNEL_RXSTARTOFSEQ", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO11->GTXE2_LOGIC_OUTS_B6_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO11", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX45_8->GTXE2_CHANNEL_EYESCANRESET": { + "src_wire": "GTXE2_IMUX45_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_EYESCANRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA27->GTXE2_LOGIC_OUTS_B0_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA27", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA55->GTXE2_LOGIC_OUTS_B0_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA55", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR4->GTXE2_LOGIC_OUTS_B22_9": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX1_9->GTXE2_CHANNEL_PMARSVDIN2": { + "src_wire": "GTXE2_IMUX1_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX29_3->GTXE2_CHANNEL_TXCHARISK6": { + "src_wire": "GTXE2_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX31_2->GTXE2_CHANNEL_TXCHARDISPMODE6": { + "src_wire": "GTXE2_IMUX31_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA32->GTXE2_LOGIC_OUTS_B3_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA32", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK2->GTXE2_LOGIC_OUTS_B12_6": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXBUFSTATUS0->GTXE2_LOGIC_OUTS_B23_10": { + "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE2->GTXE2_LOGIC_OUTS_B14_6": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA24->GTXE2_LOGIC_OUTS_B6_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA24", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT6->GTXE2_LOGIC_OUTS_B11_6": { + "src_wire": "GTXE2_CHANNEL_TSTOUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX0_9->GTXE2_CHANNEL_PMARSVDIN3": { + "src_wire": "GTXE2_IMUX0_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CLK0_7->GTXE2_CHANNEL_RXUSRCLK2": { + "src_wire": "GTXE2_CLK0_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXUSRCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX3_8->GTXE2_CHANNEL_TXPRBSSEL0": { + "src_wire": "GTXE2_IMUX3_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXHEADER2->GTXE2_LOGIC_OUTS_B17_6": { + "src_wire": "GTXE2_CHANNEL_RXHEADER2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXQPISENN->GTXE2_LOGIC_OUTS_B17_1": { + "src_wire": "GTXE2_CHANNEL_RXQPISENN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA4->GTXE2_LOGIC_OUTS_B15_10": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX30_8->GTXE2_CHANNEL_RXCDRHOLD": { + "src_wire": "GTXE2_IMUX30_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHSLIPMONITOR1->GTXE2_LOGIC_OUTS_B4_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX20_0->GTXE2_CHANNEL_TXDATA30": { + "src_wire": "GTXE2_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA30", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX35_9->GTXE2_CHANNEL_RXDFELFHOLD": { + "src_wire": "GTXE2_IMUX35_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFELFHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT2->GTXE2_LOGIC_OUTS_B9_8": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX21_9->GTXE2_CHANNEL_RXDFETAP4OVRDEN": { + "src_wire": "GTXE2_IMUX21_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX9_8->GTXE2_CHANNEL_PCSRSVDIN13": { + "src_wire": "GTXE2_IMUX9_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO1->GTXE2_LOGIC_OUTS_B4_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX1_5->GTXE2_CHANNEL_TXSEQUENCE2": { + "src_wire": "GTXE2_IMUX1_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX19_3->GTXE2_CHANNEL_TXDATA17": { + "src_wire": "GTXE2_IMUX19_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA17", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX25_2->GTXE2_CHANNEL_TXPHALIGN": { + "src_wire": "GTXE2_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHALIGN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX2_8->GTXE2_CHANNEL_RXGEARBOXSLIP": { + "src_wire": "GTXE2_IMUX2_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXGEARBOXSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX32_0->GTXE2_CHANNEL_DRPDI11": { + "src_wire": "GTXE2_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX9_6->GTXE2_CHANNEL_PCSRSVDIN11": { + "src_wire": "GTXE2_IMUX9_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX23_9->GTXE2_CHANNEL_RXCHBONDI3": { + "src_wire": "GTXE2_IMUX23_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX40_10->GTXE2_CHANNEL_TSTIN9": { + "src_wire": "GTXE2_IMUX40_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL0_8->GTXE2_CHANNEL_GTRXRESET": { + "src_wire": "GTXE2_CTRL0_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRXRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA1->GTXE2_LOGIC_OUTS_B15_7": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX21_8->GTXE2_CHANNEL_RXDFEXYDOVRDEN": { + "src_wire": "GTXE2_IMUX21_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO13->GTXE2_LOGIC_OUTS_B1_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO13", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX7_3->GTXE2_CHANNEL_TXPOSTCURSOR4": { + "src_wire": "GTXE2_IMUX7_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CLK1_7->GTXE2_CHANNEL_CLKRSVD2": { + "src_wire": "GTXE2_CLK1_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX12_5->GTXE2_CHANNEL_TXDLYOVRDEN": { + "src_wire": "GTXE2_IMUX12_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX21_3->GTXE2_CHANNEL_TXDATA51": { + "src_wire": "GTXE2_IMUX21_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA51", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX31_5->GTXE2_CHANNEL_TXCHARISK1": { + "src_wire": "GTXE2_IMUX31_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX27_9->GTXE2_CHANNEL_RXDFELFOVRDEN": { + "src_wire": "GTXE2_IMUX27_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFELFOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT1->GTXE2_LOGIC_OUTS_B8_9": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX0_6->GTXE2_CHANNEL_PMARSVDIN24": { + "src_wire": "GTXE2_IMUX0_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX39_5->GTXE2_CHANNEL_TXDETECTRX": { + "src_wire": "GTXE2_IMUX39_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDETECTRX", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX5_8->GTXE2_CHANNEL_TXOUTCLKSEL0": { + "src_wire": "GTXE2_IMUX5_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA50->GTXE2_LOGIC_OUTS_B1_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA50", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CLK1_4->GTXE2_CHANNEL_CLKRSVD0": { + "src_wire": "GTXE2_CLK1_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX21_7->GTXE2_CHANNEL_TXDATA32": { + "src_wire": "GTXE2_IMUX21_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA32", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX38_8->GTXE2_CHANNEL_RXPRBSSEL1": { + "src_wire": "GTXE2_IMUX38_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX40_3->GTXE2_CHANNEL_TSTIN2": { + "src_wire": "GTXE2_IMUX40_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX35_8->GTXE2_CHANNEL_RXDFEUTOVRDEN": { + "src_wire": "GTXE2_IMUX35_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEUTOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA3->GTXE2_LOGIC_OUTS_B15_3": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHMONITOR4->GTXE2_LOGIC_OUTS_B21_3": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX29_4->GTXE2_CHANNEL_TXCHARDISPMODE1": { + "src_wire": "GTXE2_IMUX29_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA40->GTXE2_LOGIC_OUTS_B3_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA40", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHSLIPMONITOR4->GTXE2_LOGIC_OUTS_B16_3": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX22_9->GTXE2_CHANNEL_RXCHBONDI2": { + "src_wire": "GTXE2_IMUX22_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT1->GTXE2_LOGIC_OUTS_B9_9": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX28_5->GTXE2_CHANNEL_TXSYSCLKSEL0": { + "src_wire": "GTXE2_IMUX28_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX40_2->GTXE2_CHANNEL_TSTIN1": { + "src_wire": "GTXE2_IMUX40_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX4_7->GTXE2_CHANNEL_PMARSVDIN21": { + "src_wire": "GTXE2_IMUX4_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX45_1->GTXE2_CHANNEL_TXQPIWEAKPUP": { + "src_wire": "GTXE2_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXQPIWEAKPUP", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX10_7->GTXE2_CHANNEL_TXBUFDIFFCTRL2": { + "src_wire": "GTXE2_IMUX10_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_SOUTHREFCLK1->GTXE2_CHANNEL_GTSOUTHREFCLK1": { + "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_GTREFCLKMONITOR->GTXE2_LOGIC_OUTS_B23_2": { + "src_wire": "GTXE2_CHANNEL_GTREFCLKMONITOR", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT14->GTXE2_LOGIC_OUTS_B16_0": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT14", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX1_7->GTXE2_CHANNEL_PMARSVDIN22": { + "src_wire": "GTXE2_IMUX1_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE6->GTXE2_LOGIC_OUTS_B14_5": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CLK0_4->GTXE2_CHANNEL_TXUSRCLK": { + "src_wire": "GTXE2_CLK0_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXUSRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX16_2->GTXE2_CHANNEL_TXDATA20": { + "src_wire": "GTXE2_IMUX16_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX29_7->GTXE2_CHANNEL_TXCHARISK4": { + "src_wire": "GTXE2_IMUX29_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX19_2->GTXE2_CHANNEL_TXDATA53": { + "src_wire": "GTXE2_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA53", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT4->GTXE2_LOGIC_OUTS_B8_6": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHMONITOR1->GTXE2_LOGIC_OUTS_B1_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX8_1->GTXE2_CHANNEL_TX8B10BBYPASS7": { + "src_wire": "GTXE2_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX3_9->GTXE2_CHANNEL_RXDFEUTHOLD": { + "src_wire": "GTXE2_IMUX3_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEUTHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX22_3->GTXE2_CHANNEL_TXDATA18": { + "src_wire": "GTXE2_IMUX22_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA18", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL1_1->GTXE2_CHANNEL_RXPHDLYRESET": { + "src_wire": "GTXE2_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHDLYRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX10_0->GTXE2_CHANNEL_TXCHARDISPVAL7": { + "src_wire": "GTXE2_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA26->GTXE2_LOGIC_OUTS_B4_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA26", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA9->GTXE2_LOGIC_OUTS_B2_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX16_10->GTXE2_CHANNEL_RXDFECM1EN": { + "src_wire": "GTXE2_IMUX16_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFECM1EN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA30->GTXE2_LOGIC_OUTS_B1_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA30", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA47->GTXE2_LOGIC_OUTS_B0_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA47", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX12_10->GTXE2_CHANNEL_RXDFETAP3OVRDEN": { + "src_wire": "GTXE2_IMUX12_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX28_3->GTXE2_CHANNEL_DRPWE": { + "src_wire": "GTXE2_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPWE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX1_3->GTXE2_CHANNEL_TXMAINCURSOR2": { + "src_wire": "GTXE2_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL0_6->GTXE2_CHANNEL_RXDLYSRESET": { + "src_wire": "GTXE2_CTRL0_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_QPLLREFCLK->GTXE2_CHANNEL_GTQPLLREFCLK": { + "src_wire": "GTXE2_CHANNEL_QPLLREFCLK", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTQPLLREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX5_5->GTXE2_CHANNEL_TXSEQUENCE0": { + "src_wire": "GTXE2_IMUX5_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX20_6->GTXE2_CHANNEL_TXDATA6": { + "src_wire": "GTXE2_IMUX20_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX20_5->GTXE2_CHANNEL_TXDATA42": { + "src_wire": "GTXE2_IMUX20_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA42", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX24_1->GTXE2_CHANNEL_TSTIN10": { + "src_wire": "GTXE2_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX17_1->GTXE2_CHANNEL_TXDATA57": { + "src_wire": "GTXE2_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA57", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CLK1_2->GTXE2_CHANNEL_TXPHDLYTSTCLK": { + "src_wire": "GTXE2_CLK1_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHDLYTSTCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX42_10->GTXE2_CHANNEL_GTRSVD7": { + "src_wire": "GTXE2_IMUX42_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX12_2->GTXE2_CHANNEL_TXHEADER1": { + "src_wire": "GTXE2_IMUX12_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXHEADER1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CLK0_5->GTXE2_CHANNEL_TXUSRCLK2": { + "src_wire": "GTXE2_CLK0_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXUSRCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA62->GTXE2_LOGIC_OUTS_B4_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA62", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX15_5->GTXE2_CHANNEL_TX8B10BBYPASS1": { + "src_wire": "GTXE2_IMUX15_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX10_9->GTXE2_CHANNEL_RXQPIEN": { + "src_wire": "GTXE2_IMUX10_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXQPIEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXSTATUS0->GTXE2_LOGIC_OUTS_B21_8": { + "src_wire": "GTXE2_CHANNEL_RXSTATUS0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_3": { + "src_wire": "GTXE2_CHANNEL_TXPHALIGNDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA0->GTXE2_LOGIC_OUTS_B6_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX39_9->GTXE2_CHANNEL_PCSRSVDIN24": { + "src_wire": "GTXE2_IMUX39_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX3_3->GTXE2_CHANNEL_TXSTARTSEQ": { + "src_wire": "GTXE2_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSTARTSEQ", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX34_2->GTXE2_CHANNEL_DRPADDR3": { + "src_wire": "GTXE2_IMUX34_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA1->GTXE2_LOGIC_OUTS_B2_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX2_4->GTXE2_CHANNEL_TXPOSTCURSOR3": { + "src_wire": "GTXE2_IMUX2_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX18_3->GTXE2_CHANNEL_TXDATA16": { + "src_wire": "GTXE2_IMUX18_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA16", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX36_10->GTXE2_CHANNEL_RXDFETAP3HOLD": { + "src_wire": "GTXE2_IMUX36_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP3HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX28_2->GTXE2_CHANNEL_CPLLLOCKEN": { + "src_wire": "GTXE2_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLLOCKEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT10->GTXE2_LOGIC_OUTS_B13_10": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT10", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX26_3->GTXE2_CHANNEL_GTRSVD8": { + "src_wire": "GTXE2_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK3->GTXE2_LOGIC_OUTS_B12_4": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE7->GTXE2_LOGIC_OUTS_B14_3": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX38_3->GTXE2_CHANNEL_DRPADDR5": { + "src_wire": "GTXE2_IMUX38_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX20_3->GTXE2_CHANNEL_TXDATA50": { + "src_wire": "GTXE2_IMUX20_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA50", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCDRLOCK->GTXE2_LOGIC_OUTS_B17_5": { + "src_wire": "GTXE2_CHANNEL_RXCDRLOCK", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX9_7->GTXE2_CHANNEL_PCSRSVDIN12": { + "src_wire": "GTXE2_IMUX9_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX40_4->GTXE2_CHANNEL_TSTIN3": { + "src_wire": "GTXE2_IMUX40_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHMONITOR3->GTXE2_LOGIC_OUTS_B3_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX34_0->GTXE2_CHANNEL_DRPDI3": { + "src_wire": "GTXE2_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX5_7->GTXE2_CHANNEL_PMARSVDIN20": { + "src_wire": "GTXE2_IMUX5_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX23_2->GTXE2_CHANNEL_TXDATA55": { + "src_wire": "GTXE2_IMUX23_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA55", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA7->GTXE2_LOGIC_OUTS_B15_4": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX47_9->GTXE2_CHANNEL_LOOPBACK2": { + "src_wire": "GTXE2_IMUX47_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_LOOPBACK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX28_4->GTXE2_CHANNEL_TXSYSCLKSEL1": { + "src_wire": "GTXE2_IMUX28_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX4_10->GTXE2_CHANNEL_RXOUTCLKSEL0": { + "src_wire": "GTXE2_IMUX4_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXVALID->GTXE2_LOGIC_OUTS_B20_9": { + "src_wire": "GTXE2_CHANNEL_RXVALID", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDO1->GTXE2_LOGIC_OUTS_B16_9": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA22->GTXE2_LOGIC_OUTS_B1_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA22", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL1_5->GTXE2_CHANNEL_CFGRESET": { + "src_wire": "GTXE2_CTRL1_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CFGRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX10_2->GTXE2_CHANNEL_TXCHARDISPVAL6": { + "src_wire": "GTXE2_IMUX10_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX7_5->GTXE2_CHANNEL_TXDIFFCTRL0": { + "src_wire": "GTXE2_IMUX7_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX7_8->GTXE2_CHANNEL_TXPRBSSEL2": { + "src_wire": "GTXE2_IMUX7_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX18_6->GTXE2_CHANNEL_TXDATA36": { + "src_wire": "GTXE2_IMUX18_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA36", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHSLIPMONITOR0->GTXE2_LOGIC_OUTS_B0_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX35_2->GTXE2_CHANNEL_DRPADDR2": { + "src_wire": "GTXE2_IMUX35_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR1->GTXE2_LOGIC_OUTS_B22_8": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX7_7->GTXE2_CHANNEL_TXPRECURSOR4": { + "src_wire": "GTXE2_IMUX7_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX8_3->GTXE2_CHANNEL_TX8B10BBYPASS6": { + "src_wire": "GTXE2_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX27_5->GTXE2_CHANNEL_TXPHINIT": { + "src_wire": "GTXE2_IMUX27_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHINIT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX19_5->GTXE2_CHANNEL_TXDATA9": { + "src_wire": "GTXE2_IMUX19_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXQPISENP->GTXE2_LOGIC_OUTS_B8_3": { + "src_wire": "GTXE2_CHANNEL_TXQPISENP", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXBUFSTATUS0->GTXE2_LOGIC_OUTS_B17_2": { + "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA63->GTXE2_LOGIC_OUTS_B0_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA63", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX40_7->GTXE2_CHANNEL_TSTIN6": { + "src_wire": "GTXE2_IMUX40_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX15_4->GTXE2_CHANNEL_TXPRBSFORCEERR": { + "src_wire": "GTXE2_IMUX15_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSFORCEERR", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX9_3->GTXE2_CHANNEL_PCSRSVDIN8": { + "src_wire": "GTXE2_IMUX9_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX5_4->GTXE2_CHANNEL_TXMAINCURSOR4": { + "src_wire": "GTXE2_IMUX5_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX17_7->GTXE2_CHANNEL_TXDATA34": { + "src_wire": "GTXE2_IMUX17_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA34", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX16_1->GTXE2_CHANNEL_TXDATA56": { + "src_wire": "GTXE2_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA56", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX22_1->GTXE2_CHANNEL_TXDATA26": { + "src_wire": "GTXE2_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA26", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT0->GTXE2_LOGIC_OUTS_B8_10": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX14_5->GTXE2_CHANNEL_TXDLYEN": { + "src_wire": "GTXE2_IMUX14_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT11->GTXE2_LOGIC_OUTS_B9_0": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT11", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX27_7->GTXE2_CHANNEL_RXPOLARITY": { + "src_wire": "GTXE2_IMUX27_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPOLARITY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA42->GTXE2_LOGIC_OUTS_B1_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA42", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX16_6->GTXE2_CHANNEL_TXDATA4": { + "src_wire": "GTXE2_IMUX16_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX39_4->GTXE2_CHANNEL_TXMARGIN0": { + "src_wire": "GTXE2_IMUX39_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMARGIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXHEADER0->GTXE2_LOGIC_OUTS_B19_6": { + "src_wire": "GTXE2_CHANNEL_RXHEADER0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL1_8->GTXE2_CHANNEL_RXCDRRESETRSV": { + "src_wire": "GTXE2_CTRL1_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRRESETRSV", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX7_0->GTXE2_CHANNEL_TXPISOPD": { + "src_wire": "GTXE2_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPISOPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK7->GTXE2_LOGIC_OUTS_B12_3": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX2_6->GTXE2_CHANNEL_TXPRECURSOR3": { + "src_wire": "GTXE2_IMUX2_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX26_5->GTXE2_CHANNEL_GTRSVD10": { + "src_wire": "GTXE2_IMUX26_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCOMMADET->GTXE2_LOGIC_OUTS_B19_7": { + "src_wire": "GTXE2_CHANNEL_RXCOMMADET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT0->GTXE2_LOGIC_OUTS_B11_0": { + "src_wire": "GTXE2_CHANNEL_TSTOUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX36_5->GTXE2_CHANNEL_TXPHDLYRESET": { + "src_wire": "GTXE2_IMUX36_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHDLYRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_REFCLK0->GTXE2_CHANNEL_GTREFCLK0": { + "src_wire": "GTXE2_CHANNEL_REFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX3_10->GTXE2_CHANNEL_RXLPMLFKLOVRDEN": { + "src_wire": "GTXE2_IMUX3_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX22_4->GTXE2_CHANNEL_TXDATA46": { + "src_wire": "GTXE2_IMUX22_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA46", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX18_2->GTXE2_CHANNEL_TXDATA52": { + "src_wire": "GTXE2_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA52", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX15_3->GTXE2_CHANNEL_TX8B10BBYPASS2": { + "src_wire": "GTXE2_IMUX15_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA45->GTXE2_LOGIC_OUTS_B2_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA45", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX21_0->GTXE2_CHANNEL_TXDATA31": { + "src_wire": "GTXE2_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA31", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT7->GTXE2_LOGIC_OUTS_B11_7": { + "src_wire": "GTXE2_CHANNEL_TSTOUT7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX45_9->GTXE2_CHANNEL_RXDFEXYDEN": { + "src_wire": "GTXE2_IMUX45_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEXYDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXBUFSTATUS1->GTXE2_LOGIC_OUTS_B19_10": { + "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT9->GTXE2_LOGIC_OUTS_B13_9": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CLK1_8->GTXE2_CHANNEL_CLKRSVD3": { + "src_wire": "GTXE2_CLK1_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX37_9->GTXE2_CHANNEL_RXDFETAP4HOLD": { + "src_wire": "GTXE2_IMUX37_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP4HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX42_8->GTXE2_CHANNEL_GTRSVD5": { + "src_wire": "GTXE2_IMUX42_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX33_1->GTXE2_CHANNEL_DRPDI14": { + "src_wire": "GTXE2_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX21_10->GTXE2_CHANNEL_RXDFEAGCOVRDEN": { + "src_wire": "GTXE2_IMUX21_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDO3->GTXE2_LOGIC_OUTS_B16_7": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX41_6->GTXE2_CHANNEL_RXPHALIGNEN": { + "src_wire": "GTXE2_IMUX41_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX35_4->GTXE2_CHANNEL_TXMARGIN2": { + "src_wire": "GTXE2_IMUX35_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMARGIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX9_5->GTXE2_CHANNEL_PCSRSVDIN10": { + "src_wire": "GTXE2_IMUX9_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX23_6->GTXE2_CHANNEL_TXDATA39": { + "src_wire": "GTXE2_IMUX23_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA39", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX44_10->GTXE2_CHANNEL_RXDFETAP2HOLD": { + "src_wire": "GTXE2_IMUX44_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP2HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX12_8->GTXE2_CHANNEL_RXSLIDE": { + "src_wire": "GTXE2_IMUX12_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXSLIDE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_REFCLK1->GTXE2_CHANNEL_GTREFCLK1": { + "src_wire": "GTXE2_CHANNEL_REFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL1_3->GTXE2_CHANNEL_TXPMARESET": { + "src_wire": "GTXE2_CTRL1_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPMARESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX23_7->GTXE2_CHANNEL_TXDATA3": { + "src_wire": "GTXE2_IMUX23_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B17_3": { + "src_wire": "GTXE2_CHANNEL_TXDLYSRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA54->GTXE2_LOGIC_OUTS_B4_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA54", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO10->GTXE2_LOGIC_OUTS_B2_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO10", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE1->GTXE2_LOGIC_OUTS_B14_8": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX5_6->GTXE2_CHANNEL_TXSEQUENCE4": { + "src_wire": "GTXE2_IMUX5_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX6_5->GTXE2_CHANNEL_TXDIFFCTRL1": { + "src_wire": "GTXE2_IMUX6_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA34->GTXE2_LOGIC_OUTS_B1_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA34", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA12->GTXE2_LOGIC_OUTS_B3_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA12", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX19_8->GTXE2_CHANNEL_RXDFEVPHOLD": { + "src_wire": "GTXE2_IMUX19_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEVPHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX23_1->GTXE2_CHANNEL_TXDATA27": { + "src_wire": "GTXE2_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA27", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX29_2->GTXE2_CHANNEL_TXCHARDISPMODE2": { + "src_wire": "GTXE2_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT13->GTXE2_LOGIC_OUTS_B9_2": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT13", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX11_10->GTXE2_CHANNEL_RXLPMLFHOLD": { + "src_wire": "GTXE2_IMUX11_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMLFHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX26_10->GTXE2_CHANNEL_GTRSVD15": { + "src_wire": "GTXE2_IMUX26_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX17_5->GTXE2_CHANNEL_TXDATA41": { + "src_wire": "GTXE2_IMUX17_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA41", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL1_6->GTXE2_CHANNEL_RXBUFRESET": { + "src_wire": "GTXE2_CTRL1_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXBUFRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK0->GTXE2_LOGIC_OUTS_B12_10": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX0_10->GTXE2_CHANNEL_RXELECIDLEMODE0": { + "src_wire": "GTXE2_IMUX0_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXSTATUS1->GTXE2_LOGIC_OUTS_B17_8": { + "src_wire": "GTXE2_CHANNEL_RXSTATUS1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX19_4->GTXE2_CHANNEL_TXDATA45": { + "src_wire": "GTXE2_IMUX19_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA45", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX3_7->GTXE2_CHANNEL_RXPD0": { + "src_wire": "GTXE2_IMUX3_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT2->GTXE2_LOGIC_OUTS_B11_2": { + "src_wire": "GTXE2_CHANNEL_TSTOUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPRDY->GTXE2_LOGIC_OUTS_B20_0": { + "src_wire": "GTXE2_CHANNEL_DRPRDY", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX1_8->GTXE2_CHANNEL_TXOUTCLKSEL2": { + "src_wire": "GTXE2_IMUX1_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX14_10->GTXE2_CHANNEL_RXPHOVRDEN": { + "src_wire": "GTXE2_IMUX14_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXPHINITDONE->GTXE2_LOGIC_OUTS_B17_0": { + "src_wire": "GTXE2_CHANNEL_TXPHINITDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA52->GTXE2_LOGIC_OUTS_B6_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA52", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX12_1->GTXE2_CHANNEL_TXCOMWAKE": { + "src_wire": "GTXE2_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCOMWAKE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX6_6->GTXE2_CHANNEL_TXPRECURSOR1": { + "src_wire": "GTXE2_IMUX6_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX26_8->GTXE2_CHANNEL_GTRSVD13": { + "src_wire": "GTXE2_IMUX26_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX17_4->GTXE2_CHANNEL_TXDATA13": { + "src_wire": "GTXE2_IMUX17_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT6->GTXE2_LOGIC_OUTS_B13_6": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA43->GTXE2_LOGIC_OUTS_B5_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA43", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX45_3->GTXE2_CHANNEL_TXDLYSRESET": { + "src_wire": "GTXE2_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B23_3": { + "src_wire": "GTXE2_CHANNEL_TXOUTCLKFABRIC", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_QPLLCLK->GTXE2_CHANNEL_GTQPLLCLK": { + "src_wire": "GTXE2_CHANNEL_QPLLCLK", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTQPLLCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX1_6->GTXE2_CHANNEL_TXSEQUENCE6": { + "src_wire": "GTXE2_IMUX1_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA18->GTXE2_LOGIC_OUTS_B4_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA18", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_SOUTHREFCLK0->GTXE2_CHANNEL_GTSOUTHREFCLK0": { + "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT7->GTXE2_LOGIC_OUTS_B9_3": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXGEARBOXREADY->GTXE2_LOGIC_OUTS_B23_4": { + "src_wire": "GTXE2_CHANNEL_TXGEARBOXREADY", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_CPLLFBCLKLOST->GTXE2_LOGIC_OUTS_B8_1": { + "src_wire": "GTXE2_CHANNEL_CPLLFBCLKLOST", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX31_7->GTXE2_CHANNEL_TXCHARISK0": { + "src_wire": "GTXE2_IMUX31_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX16_3->GTXE2_CHANNEL_TXDATA48": { + "src_wire": "GTXE2_IMUX16_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA48", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHMONITOR0->GTXE2_LOGIC_OUTS_B5_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX10_6->GTXE2_CHANNEL_TXCHARDISPVAL4": { + "src_wire": "GTXE2_IMUX10_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX37_4->GTXE2_CHANNEL_TXDIFFPD": { + "src_wire": "GTXE2_IMUX37_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK6->GTXE2_LOGIC_OUTS_B12_5": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX21_6->GTXE2_CHANNEL_TXDATA7": { + "src_wire": "GTXE2_IMUX21_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX27_8->GTXE2_CHANNEL_RXDFEVPOVRDEN": { + "src_wire": "GTXE2_IMUX27_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEVPOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX23_8->GTXE2_CHANNEL_RXPRBSSEL2": { + "src_wire": "GTXE2_IMUX23_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX11_5->GTXE2_CHANNEL_TXDLYHOLD": { + "src_wire": "GTXE2_IMUX11_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA33->GTXE2_LOGIC_OUTS_B7_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA33", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX39_1->GTXE2_CHANNEL_DRPDI4": { + "src_wire": "GTXE2_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCOMINITDET->GTXE2_LOGIC_OUTS_B20_7": { + "src_wire": "GTXE2_CHANNEL_RXCOMINITDET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX8_8->GTXE2_CHANNEL_RXDDIEN": { + "src_wire": "GTXE2_IMUX8_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDDIEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX13_9->GTXE2_CHANNEL_RXDFETAP5OVRDEN": { + "src_wire": "GTXE2_IMUX13_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX30_7->GTXE2_CHANNEL_TXPCSRESET": { + "src_wire": "GTXE2_IMUX30_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPCSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA48->GTXE2_LOGIC_OUTS_B3_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA48", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX36_0->GTXE2_CHANNEL_DRPDI9": { + "src_wire": "GTXE2_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX35_6->GTXE2_CHANNEL_TXPD1": { + "src_wire": "GTXE2_IMUX35_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX34_1->GTXE2_CHANNEL_DRPDI7": { + "src_wire": "GTXE2_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX36_2->GTXE2_CHANNEL_CPLLPD": { + "src_wire": "GTXE2_IMUX36_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA13->GTXE2_LOGIC_OUTS_B7_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA13", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXELECIDLE->GTXE2_LOGIC_OUTS_B19_8": { + "src_wire": "GTXE2_CHANNEL_RXELECIDLE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX19_1->GTXE2_CHANNEL_TXDATA25": { + "src_wire": "GTXE2_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA25", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT1->GTXE2_LOGIC_OUTS_B13_1": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX0_2->GTXE2_CHANNEL_TX8B10BEN": { + "src_wire": "GTXE2_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX22_0->GTXE2_CHANNEL_TXDATA62": { + "src_wire": "GTXE2_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA62", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX17_2->GTXE2_CHANNEL_TXDATA21": { + "src_wire": "GTXE2_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CLK1_5->GTXE2_CHANNEL_CLKRSVD1": { + "src_wire": "GTXE2_CLK1_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX3_5->GTXE2_CHANNEL_TXDIFFCTRL2": { + "src_wire": "GTXE2_IMUX3_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL1_9->GTXE2_CHANNEL_RXCDRRESET": { + "src_wire": "GTXE2_CTRL1_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA57->GTXE2_LOGIC_OUTS_B7_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA57", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX24_8->GTXE2_CHANNEL_TSTIN17": { + "src_wire": "GTXE2_IMUX24_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN17", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR6->GTXE2_LOGIC_OUTS_B22_5": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXBYTEREALIGN->GTXE2_LOGIC_OUTS_B10_10": { + "src_wire": "GTXE2_CHANNEL_RXBYTEREALIGN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL0_7->GTXE2_CHANNEL_RXCDRFREQRESET": { + "src_wire": "GTXE2_CTRL0_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRFREQRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX37_1->GTXE2_CHANNEL_DRPDI12": { + "src_wire": "GTXE2_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX45_2->GTXE2_CHANNEL_RXSYSCLKSEL0": { + "src_wire": "GTXE2_IMUX45_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR5->GTXE2_LOGIC_OUTS_B22_7": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX24_6->GTXE2_CHANNEL_TSTIN15": { + "src_wire": "GTXE2_IMUX24_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX17_9->GTXE2_CHANNEL_RXCHBONDEN": { + "src_wire": "GTXE2_IMUX17_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA7->GTXE2_LOGIC_OUTS_B5_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX20_1->GTXE2_CHANNEL_TXDATA58": { + "src_wire": "GTXE2_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA58", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXBUFSTATUS1->GTXE2_LOGIC_OUTS_B21_2": { + "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX10_5->GTXE2_CHANNEL_TXUSERRDY": { + "src_wire": "GTXE2_IMUX10_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXUSERRDY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX35_3->GTXE2_CHANNEL_DRPADDR6": { + "src_wire": "GTXE2_IMUX35_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX29_8->GTXE2_CHANNEL_RXOSHOLD": { + "src_wire": "GTXE2_IMUX29_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOSHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX31_8->GTXE2_CHANNEL_EYESCANTRIGGER": { + "src_wire": "GTXE2_IMUX31_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_EYESCANTRIGGER", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX38_10->GTXE2_CHANNEL_PCSRSVDIN22": { + "src_wire": "GTXE2_IMUX38_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA2->GTXE2_LOGIC_OUTS_B15_5": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX44_8->GTXE2_CHANNEL_RXUSERRDY": { + "src_wire": "GTXE2_IMUX44_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXUSERRDY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA6->GTXE2_LOGIC_OUTS_B15_6": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX25_6->GTXE2_CHANNEL_PCSRSVDIN3": { + "src_wire": "GTXE2_IMUX25_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX19_6->GTXE2_CHANNEL_TXDATA37": { + "src_wire": "GTXE2_IMUX19_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA37", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX4_9->GTXE2_CHANNEL_PMARSVDIN1": { + "src_wire": "GTXE2_IMUX4_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXHEADER1->GTXE2_LOGIC_OUTS_B23_6": { + "src_wire": "GTXE2_CHANNEL_RXHEADER1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT0->GTXE2_LOGIC_OUTS_B9_10": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX1_4->GTXE2_CHANNEL_TXMAINCURSOR6": { + "src_wire": "GTXE2_IMUX1_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA53->GTXE2_LOGIC_OUTS_B2_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA53", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX14_7->GTXE2_CHANNEL_RXPCSRESET": { + "src_wire": "GTXE2_IMUX14_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPCSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA51->GTXE2_LOGIC_OUTS_B5_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA51", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA15->GTXE2_LOGIC_OUTS_B5_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA15", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX45_10->GTXE2_CHANNEL_RXMONITORSEL0": { + "src_wire": "GTXE2_IMUX45_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT8->GTXE2_LOGIC_OUTS_B13_8": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX17_3->GTXE2_CHANNEL_TXDATA49": { + "src_wire": "GTXE2_IMUX17_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA49", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX29_6->GTXE2_CHANNEL_TXCHARDISPMODE0": { + "src_wire": "GTXE2_IMUX29_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX32_8->GTXE2_CHANNEL_RXDLYBYPASS": { + "src_wire": "GTXE2_IMUX32_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYBYPASS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CLK1_1->GTXE2_CHANNEL_DRPCLK": { + "src_wire": "GTXE2_CLK1_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX19_0->GTXE2_CHANNEL_TXDATA61": { + "src_wire": "GTXE2_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA61", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATAVALID->GTXE2_LOGIC_OUTS_B19_5": { + "src_wire": "GTXE2_CHANNEL_RXDATAVALID", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX20_7->GTXE2_CHANNEL_TXDATA33": { + "src_wire": "GTXE2_IMUX20_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA33", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX25_4->GTXE2_CHANNEL_PCSRSVDIN1": { + "src_wire": "GTXE2_IMUX25_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX38_1->GTXE2_CHANNEL_DRPDI5": { + "src_wire": "GTXE2_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX38_4->GTXE2_CHANNEL_TXMARGIN1": { + "src_wire": "GTXE2_IMUX38_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMARGIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX41_1->GTXE2_CHANNEL_TXPOSTCURSORINV": { + "src_wire": "GTXE2_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSORINV", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT5->GTXE2_LOGIC_OUTS_B13_5": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX2_3->GTXE2_CHANNEL_DRPADDR8": { + "src_wire": "GTXE2_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA28->GTXE2_LOGIC_OUTS_B3_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA28", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT2->GTXE2_LOGIC_OUTS_B8_8": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT4->GTXE2_LOGIC_OUTS_B9_6": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT1->GTXE2_LOGIC_OUTS_B11_1": { + "src_wire": "GTXE2_CHANNEL_TSTOUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX24_4->GTXE2_CHANNEL_TSTIN13": { + "src_wire": "GTXE2_IMUX24_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX35_5->GTXE2_CHANNEL_TXDEEMPH": { + "src_wire": "GTXE2_IMUX35_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDEEMPH", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX7_6->GTXE2_CHANNEL_TXPRECURSOR0": { + "src_wire": "GTXE2_IMUX7_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX32_2->GTXE2_CHANNEL_TXINHIBIT": { + "src_wire": "GTXE2_IMUX32_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXINHIBIT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT4->GTXE2_LOGIC_OUTS_B11_4": { + "src_wire": "GTXE2_CHANNEL_TSTOUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_NORTHREFCLK1->GTXE2_CHANNEL_GTNORTHREFCLK1": { + "src_wire": "GTXE2_CHANNEL_NORTHREFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX17_6->GTXE2_CHANNEL_TXDATA5": { + "src_wire": "GTXE2_IMUX17_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX26_6->GTXE2_CHANNEL_GTRSVD11": { + "src_wire": "GTXE2_IMUX26_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO3->GTXE2_LOGIC_OUTS_B6_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX20_2->GTXE2_CHANNEL_TXDATA22": { + "src_wire": "GTXE2_IMUX20_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX46_9->GTXE2_CHANNEL_LOOPBACK1": { + "src_wire": "GTXE2_IMUX46_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_LOOPBACK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT3->GTXE2_LOGIC_OUTS_B13_3": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT5->GTXE2_LOGIC_OUTS_B11_5": { + "src_wire": "GTXE2_CHANNEL_TSTOUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX41_5->GTXE2_CHANNEL_RESETOVRD": { + "src_wire": "GTXE2_IMUX41_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RESETOVRD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX13_1->GTXE2_CHANNEL_TXQPISTRONGPDOWN": { + "src_wire": "GTXE2_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR3->GTXE2_LOGIC_OUTS_B22_4": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX43_6->GTXE2_CHANNEL_TXRATE2": { + "src_wire": "GTXE2_IMUX43_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXRATE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX22_8->GTXE2_CHANNEL_RXPRBSSEL0": { + "src_wire": "GTXE2_IMUX22_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX39_0->GTXE2_CHANNEL_DRPDI0": { + "src_wire": "GTXE2_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX38_2->GTXE2_CHANNEL_DRPADDR1": { + "src_wire": "GTXE2_IMUX38_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL0_3->GTXE2_CHANNEL_CPLLRESET": { + "src_wire": "GTXE2_CTRL0_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX29_1->GTXE2_CHANNEL_TXCHARISK7": { + "src_wire": "GTXE2_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA4->GTXE2_LOGIC_OUTS_B3_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX12_4->GTXE2_CHANNEL_TXPHOVRDEN": { + "src_wire": "GTXE2_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX9_1->GTXE2_CHANNEL_RXPHDLYPD": { + "src_wire": "GTXE2_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHDLYPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXBUFSTATUS2->GTXE2_LOGIC_OUTS_B17_10": { + "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT7->GTXE2_LOGIC_OUTS_B13_7": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_EYESCANDATAERROR->GTXE2_LOGIC_OUTS_B20_10": { + "src_wire": "GTXE2_CHANNEL_EYESCANDATAERROR", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA17->GTXE2_LOGIC_OUTS_B2_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA17", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA20->GTXE2_LOGIC_OUTS_B3_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA20", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX7_4->GTXE2_CHANNEL_TXPOSTCURSOR0": { + "src_wire": "GTXE2_IMUX7_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO5->GTXE2_LOGIC_OUTS_B1_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA25->GTXE2_LOGIC_OUTS_B2_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA25", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX16_0->GTXE2_CHANNEL_TXDATA28": { + "src_wire": "GTXE2_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA28", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CLK0_2->GTXE2_CHANNEL_CPLLLOCKDETCLK": { + "src_wire": "GTXE2_CLK0_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLLOCKDETCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX15_6->GTXE2_CHANNEL_RXRATE0": { + "src_wire": "GTXE2_IMUX15_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXRATE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK1->GTXE2_LOGIC_OUTS_B12_8": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT2->GTXE2_LOGIC_OUTS_B13_2": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX14_9->GTXE2_CHANNEL_RXPHALIGN": { + "src_wire": "GTXE2_IMUX14_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHALIGN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX19_9->GTXE2_CHANNEL_RXCHBONDI1": { + "src_wire": "GTXE2_IMUX19_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX42_2->GTXE2_CHANNEL_RXSYSCLKSEL1": { + "src_wire": "GTXE2_IMUX42_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX22_7->GTXE2_CHANNEL_TXDATA2": { + "src_wire": "GTXE2_IMUX22_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX29_10->GTXE2_CHANNEL_RXDFEAGCHOLD": { + "src_wire": "GTXE2_IMUX29_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEAGCHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA10->GTXE2_LOGIC_OUTS_B4_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA10", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT9->GTXE2_LOGIC_OUTS_B11_9": { + "src_wire": "GTXE2_CHANNEL_TSTOUT9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX2_9->GTXE2_CHANNEL_RXMCOMMAALIGNEN": { + "src_wire": "GTXE2_IMUX2_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA38->GTXE2_LOGIC_OUTS_B4_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA38", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX23_5->GTXE2_CHANNEL_TXDATA11": { + "src_wire": "GTXE2_IMUX23_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHSLIPMONITOR2->GTXE2_LOGIC_OUTS_B2_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX4_1->GTXE2_CHANNEL_TXPRECURSORINV": { + "src_wire": "GTXE2_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSORINV", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX8_6->GTXE2_CHANNEL_TXCHARDISPVAL0": { + "src_wire": "GTXE2_IMUX8_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX24_10->GTXE2_CHANNEL_TSTIN19": { + "src_wire": "GTXE2_IMUX24_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN19", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX4_3->GTXE2_CHANNEL_TXMAINCURSOR1": { + "src_wire": "GTXE2_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX21_2->GTXE2_CHANNEL_TXDATA23": { + "src_wire": "GTXE2_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA6->GTXE2_LOGIC_OUTS_B1_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX47_6->GTXE2_CHANNEL_TXRATE0": { + "src_wire": "GTXE2_IMUX47_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXRATE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX40_8->GTXE2_CHANNEL_TSTIN7": { + "src_wire": "GTXE2_IMUX40_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX26_4->GTXE2_CHANNEL_GTRSVD9": { + "src_wire": "GTXE2_IMUX26_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCOMWAKEDET->GTXE2_LOGIC_OUTS_B19_9": { + "src_wire": "GTXE2_CHANNEL_RXCOMWAKEDET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA61->GTXE2_LOGIC_OUTS_B2_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA61", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA37->GTXE2_LOGIC_OUTS_B2_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA37", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX8_0->GTXE2_CHANNEL_TXCHARDISPVAL3": { + "src_wire": "GTXE2_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX9_10->GTXE2_CHANNEL_PCSRSVDIN15": { + "src_wire": "GTXE2_IMUX9_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX5_1->GTXE2_CHANNEL_TXQPIBIASEN": { + "src_wire": "GTXE2_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXQPIBIASEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX28_8->GTXE2_CHANNEL_RXPD1": { + "src_wire": "GTXE2_IMUX28_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX28_6->GTXE2_CHANNEL_RXDLYEN": { + "src_wire": "GTXE2_IMUX28_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PHYSTATUS->GTXE2_LOGIC_OUTS_B10_9": { + "src_wire": "GTXE2_CHANNEL_PHYSTATUS", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX10_1->GTXE2_CHANNEL_TXPDELECIDLEMODE": { + "src_wire": "GTXE2_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPDELECIDLEMODE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX23_3->GTXE2_CHANNEL_TXDATA19": { + "src_wire": "GTXE2_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA19", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA44->GTXE2_LOGIC_OUTS_B6_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA44", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_CPLLLOCK->GTXE2_LOGIC_OUTS_B14_1": { + "src_wire": "GTXE2_CHANNEL_CPLLLOCK", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CLK1_6->GTXE2_CHANNEL_GTGREFCLK": { + "src_wire": "GTXE2_CLK1_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTGREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA58->GTXE2_LOGIC_OUTS_B1_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA58", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHSLIPMONITOR3->GTXE2_LOGIC_OUTS_B6_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX37_8->GTXE2_CHANNEL_RXDFEXYDHOLD": { + "src_wire": "GTXE2_IMUX37_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEXYDHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHANBONDSEQ->GTXE2_LOGIC_OUTS_B10_8": { + "src_wire": "GTXE2_CHANNEL_RXCHANBONDSEQ", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDO0->GTXE2_LOGIC_OUTS_B16_10": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX25_9->GTXE2_CHANNEL_PCSRSVDIN6": { + "src_wire": "GTXE2_IMUX25_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX33_2->GTXE2_CHANNEL_TXPHALIGNEN": { + "src_wire": "GTXE2_IMUX33_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE3->GTXE2_LOGIC_OUTS_B14_4": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX37_3->GTXE2_CHANNEL_TXPHDLYPD": { + "src_wire": "GTXE2_IMUX37_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHDLYPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA36->GTXE2_LOGIC_OUTS_B6_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA36", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO12->GTXE2_LOGIC_OUTS_B5_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO12", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX44_5->GTXE2_CHANNEL_TXDLYBYPASS": { + "src_wire": "GTXE2_IMUX44_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYBYPASS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT6->GTXE2_LOGIC_OUTS_B9_4": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX25_5->GTXE2_CHANNEL_PCSRSVDIN2": { + "src_wire": "GTXE2_IMUX25_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT3->GTXE2_LOGIC_OUTS_B9_7": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX39_2->GTXE2_CHANNEL_DRPADDR0": { + "src_wire": "GTXE2_IMUX39_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX35_10->GTXE2_CHANNEL_PCSRSVDIN21": { + "src_wire": "GTXE2_IMUX35_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX23_10->GTXE2_CHANNEL_RXCHBONDI4": { + "src_wire": "GTXE2_IMUX23_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX24_5->GTXE2_CHANNEL_TSTIN14": { + "src_wire": "GTXE2_IMUX24_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT6->GTXE2_LOGIC_OUTS_B8_4": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT5->GTXE2_LOGIC_OUTS_B9_5": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO6->GTXE2_LOGIC_OUTS_B7_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX0_8->GTXE2_CHANNEL_PMARSVDIN4": { + "src_wire": "GTXE2_IMUX0_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX24_9->GTXE2_CHANNEL_TSTIN18": { + "src_wire": "GTXE2_IMUX24_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN18", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX44_3->GTXE2_CHANNEL_DRPEN": { + "src_wire": "GTXE2_IMUX44_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX43_5->GTXE2_CHANNEL_TXDLYUPDOWN": { + "src_wire": "GTXE2_IMUX43_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYUPDOWN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX22_2->GTXE2_CHANNEL_TXDATA54": { + "src_wire": "GTXE2_IMUX22_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA54", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX3_6->GTXE2_CHANNEL_TXPRECURSOR2": { + "src_wire": "GTXE2_IMUX3_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR0->GTXE2_LOGIC_OUTS_B22_10": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX25_10->GTXE2_CHANNEL_PCSRSVDIN7": { + "src_wire": "GTXE2_IMUX25_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX31_4->GTXE2_CHANNEL_TXCHARDISPMODE5": { + "src_wire": "GTXE2_IMUX31_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX8_4->GTXE2_CHANNEL_TXCHARDISPVAL1": { + "src_wire": "GTXE2_IMUX8_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX15_1->GTXE2_CHANNEL_TX8B10BBYPASS3": { + "src_wire": "GTXE2_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX27_10->GTXE2_CHANNEL_RXLPMHFOVRDEN": { + "src_wire": "GTXE2_IMUX27_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMHFOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX38_7->GTXE2_CHANNEL_RXDLYOVRDEN": { + "src_wire": "GTXE2_IMUX38_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDO2->GTXE2_LOGIC_OUTS_B16_8": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX22_5->GTXE2_CHANNEL_TXDATA10": { + "src_wire": "GTXE2_IMUX22_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX12_7->GTXE2_CHANNEL_TXBUFDIFFCTRL0": { + "src_wire": "GTXE2_IMUX12_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA5->GTXE2_LOGIC_OUTS_B15_8": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA35->GTXE2_LOGIC_OUTS_B5_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA35", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX46_6->GTXE2_CHANNEL_TXRATE1": { + "src_wire": "GTXE2_IMUX46_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXRATE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX16_7->GTXE2_CHANNEL_TXDATA35": { + "src_wire": "GTXE2_IMUX16_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA35", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX31_0->GTXE2_CHANNEL_TXCHARDISPMODE7": { + "src_wire": "GTXE2_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXN_PAD->GTXE2_CHANNEL_RXN": { + "src_wire": "GTXE2_CHANNEL_RXN_PAD", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX9_4->GTXE2_CHANNEL_PCSRSVDIN9": { + "src_wire": "GTXE2_IMUX9_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX4_4->GTXE2_CHANNEL_TXMAINCURSOR5": { + "src_wire": "GTXE2_IMUX4_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX43_10->GTXE2_CHANNEL_RXLPMHFHOLD": { + "src_wire": "GTXE2_IMUX43_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMHFHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX35_0->GTXE2_CHANNEL_DRPDI2": { + "src_wire": "GTXE2_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX4_5->GTXE2_CHANNEL_TXSEQUENCE1": { + "src_wire": "GTXE2_IMUX4_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX17_0->GTXE2_CHANNEL_TXDATA29": { + "src_wire": "GTXE2_IMUX17_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA29", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX23_0->GTXE2_CHANNEL_TXDATA63": { + "src_wire": "GTXE2_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA63", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CLK0_6->GTXE2_CHANNEL_RXUSRCLK": { + "src_wire": "GTXE2_CLK0_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXUSRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX14_8->GTXE2_CHANNEL_RXCDROVRDEN": { + "src_wire": "GTXE2_IMUX14_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDROVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA8->GTXE2_LOGIC_OUTS_B6_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO14->GTXE2_LOGIC_OUTS_B7_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO14", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA41->GTXE2_LOGIC_OUTS_B7_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA41", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA60->GTXE2_LOGIC_OUTS_B6_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA60", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR2->GTXE2_LOGIC_OUTS_B22_6": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO7->GTXE2_LOGIC_OUTS_B3_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX44_9->GTXE2_CHANNEL_RXCOMMADETEN": { + "src_wire": "GTXE2_IMUX44_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCOMMADETEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX18_9->GTXE2_CHANNEL_RXCHBONDI0": { + "src_wire": "GTXE2_IMUX18_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX38_6->GTXE2_CHANNEL_TXPD0": { + "src_wire": "GTXE2_IMUX38_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX10_4->GTXE2_CHANNEL_TXCHARDISPVAL5": { + "src_wire": "GTXE2_IMUX10_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA31->GTXE2_LOGIC_OUTS_B5_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA31", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXRATEDONE->GTXE2_LOGIC_OUTS_B20_4": { + "src_wire": "GTXE2_CHANNEL_TXRATEDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX9_2->GTXE2_CHANNEL_TXHEADER2": { + "src_wire": "GTXE2_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXHEADER2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXOUTCLKPCS->GTXE2_LOGIC_OUTS_B21_9": { + "src_wire": "GTXE2_CHANNEL_RXOUTCLKPCS", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXQPISENP->GTXE2_LOGIC_OUTS_B15_1": { + "src_wire": "GTXE2_CHANNEL_RXQPISENP", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXRATEDONE->GTXE2_LOGIC_OUTS_B23_5": { + "src_wire": "GTXE2_CHANNEL_RXRATEDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX34_4->GTXE2_CHANNEL_SETERRSTATUS": { + "src_wire": "GTXE2_IMUX34_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_SETERRSTATUS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK4->GTXE2_LOGIC_OUTS_B12_9": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX26_7->GTXE2_CHANNEL_GTRSVD12": { + "src_wire": "GTXE2_IMUX26_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX4_8->GTXE2_CHANNEL_TXOUTCLKSEL1": { + "src_wire": "GTXE2_IMUX4_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX9_9->GTXE2_CHANNEL_PCSRSVDIN14": { + "src_wire": "GTXE2_IMUX9_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX25_7->GTXE2_CHANNEL_PCSRSVDIN4": { + "src_wire": "GTXE2_IMUX25_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT12->GTXE2_LOGIC_OUTS_B9_1": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT12", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX29_9->GTXE2_CHANNEL_RXDFETAP5HOLD": { + "src_wire": "GTXE2_IMUX29_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP5HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT8->GTXE2_LOGIC_OUTS_B11_8": { + "src_wire": "GTXE2_CHANNEL_TSTOUT8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX39_10->GTXE2_CHANNEL_PCSRSVDIN23": { + "src_wire": "GTXE2_IMUX39_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR7->GTXE2_LOGIC_OUTS_B22_3": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX30_3->GTXE2_CHANNEL_TXPOLARITY": { + "src_wire": "GTXE2_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOLARITY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX11_8->GTXE2_CHANNEL_RXDFEVSEN": { + "src_wire": "GTXE2_IMUX11_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEVSEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX13_7->GTXE2_CHANNEL_TXBUFDIFFCTRL1": { + "src_wire": "GTXE2_IMUX13_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX42_9->GTXE2_CHANNEL_GTRSVD6": { + "src_wire": "GTXE2_IMUX42_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE5->GTXE2_LOGIC_OUTS_B14_7": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX18_7->GTXE2_CHANNEL_TXDATA0": { + "src_wire": "GTXE2_IMUX18_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX20_4->GTXE2_CHANNEL_TXDATA14": { + "src_wire": "GTXE2_IMUX20_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX38_0->GTXE2_CHANNEL_DRPDI1": { + "src_wire": "GTXE2_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX42_3->GTXE2_CHANNEL_GTRSVD0": { + "src_wire": "GTXE2_IMUX42_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXP->GTXE2_CHANNEL_TXP_PAD": { + "src_wire": "GTXE2_CHANNEL_TXP", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXP_PAD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX0_7->GTXE2_CHANNEL_PMARSVDIN23": { + "src_wire": "GTXE2_IMUX0_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXSTATUS2->GTXE2_LOGIC_OUTS_B23_8": { + "src_wire": "GTXE2_CHANNEL_RXSTATUS2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX5_9->GTXE2_CHANNEL_PMARSVDIN0": { + "src_wire": "GTXE2_IMUX5_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX40_9->GTXE2_CHANNEL_TSTIN8": { + "src_wire": "GTXE2_IMUX40_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL0_5->GTXE2_CHANNEL_GTTXRESET": { + "src_wire": "GTXE2_CTRL0_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTTXRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B22_1": { + "src_wire": "GTXE2_CHANNEL_RXDLYSRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX38_5->GTXE2_CHANNEL_TXSWING": { + "src_wire": "GTXE2_IMUX38_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSWING", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA2->GTXE2_LOGIC_OUTS_B4_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA16->GTXE2_LOGIC_OUTS_B6_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA16", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXQPISENN->GTXE2_LOGIC_OUTS_B20_3": { + "src_wire": "GTXE2_CHANNEL_TXQPISENN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX24_3->GTXE2_CHANNEL_TSTIN12": { + "src_wire": "GTXE2_IMUX24_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXN->GTXE2_CHANNEL_TXN_PAD": { + "src_wire": "GTXE2_CHANNEL_TXN", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXN_PAD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA23->GTXE2_LOGIC_OUTS_B5_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA23", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX14_2->GTXE2_CHANNEL_CPLLREFCLKSEL1": { + "src_wire": "GTXE2_IMUX14_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX32_1->GTXE2_CHANNEL_DRPDI15": { + "src_wire": "GTXE2_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX34_9->GTXE2_CHANNEL_RXPCOMMAALIGNEN": { + "src_wire": "GTXE2_IMUX34_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO0->GTXE2_LOGIC_OUTS_B0_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHANREALIGN->GTXE2_LOGIC_OUTS_B23_9": { + "src_wire": "GTXE2_CHANNEL_RXCHANREALIGN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX31_6->GTXE2_CHANNEL_TXCHARDISPMODE4": { + "src_wire": "GTXE2_IMUX31_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPRBSERR->GTXE2_LOGIC_OUTS_B20_6": { + "src_wire": "GTXE2_CHANNEL_RXPRBSERR", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_GTRXOUTCLK_2->GTXE2_CHANNEL_RXOUTCLK_2": { + "src_wire": "GTXE2_CHANNEL_GTRXOUTCLK_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCLKCORCNT0->GTXE2_LOGIC_OUTS_B18_5": { + "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX23_4->GTXE2_CHANNEL_TXDATA47": { + "src_wire": "GTXE2_IMUX23_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA47", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX43_9->GTXE2_CHANNEL_LOOPBACK0": { + "src_wire": "GTXE2_IMUX43_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_LOOPBACK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXHEADERVALID->GTXE2_LOGIC_OUTS_B23_7": { + "src_wire": "GTXE2_CHANNEL_RXHEADERVALID", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX22_10->GTXE2_CHANNEL_RXCHBONDLEVEL2": { + "src_wire": "GTXE2_IMUX22_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX21_5->GTXE2_CHANNEL_TXDATA43": { + "src_wire": "GTXE2_IMUX21_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA43", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE0->GTXE2_LOGIC_OUTS_B14_10": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX25_8->GTXE2_CHANNEL_PCSRSVDIN5": { + "src_wire": "GTXE2_IMUX25_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX18_0->GTXE2_CHANNEL_TXDATA60": { + "src_wire": "GTXE2_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA60", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX5_10->GTXE2_CHANNEL_RXOUTCLKSEL1": { + "src_wire": "GTXE2_IMUX5_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_NORTHREFCLK0->GTXE2_CHANNEL_GTNORTHREFCLK0": { + "src_wire": "GTXE2_CHANNEL_NORTHREFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXOUTCLKPCS->GTXE2_LOGIC_OUTS_B17_4": { + "src_wire": "GTXE2_CHANNEL_TXOUTCLKPCS", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX0_3->GTXE2_CHANNEL_TXMAINCURSOR3": { + "src_wire": "GTXE2_IMUX0_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA5->GTXE2_LOGIC_OUTS_B7_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX18_10->GTXE2_CHANNEL_RXCHBONDLEVEL0": { + "src_wire": "GTXE2_IMUX18_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_GTTXOUTCLK_2->GTXE2_CHANNEL_TXOUTCLK_2": { + "src_wire": "GTXE2_CHANNEL_GTTXOUTCLK_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO15->GTXE2_LOGIC_OUTS_B3_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO15", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX18_4->GTXE2_CHANNEL_TXDATA44": { + "src_wire": "GTXE2_IMUX18_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA44", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX39_6->GTXE2_CHANNEL_TXELECIDLE": { + "src_wire": "GTXE2_IMUX39_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXELECIDLE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX2_10->GTXE2_CHANNEL_RXOUTCLKSEL2": { + "src_wire": "GTXE2_IMUX2_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL0_9->GTXE2_CHANNEL_RXDFELPMRESET": { + "src_wire": "GTXE2_CTRL0_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFELPMRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXBYTEISALIGNED->GTXE2_LOGIC_OUTS_B18_10": { + "src_wire": "GTXE2_CHANNEL_RXBYTEISALIGNED", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCOMSASDET->GTXE2_LOGIC_OUTS_B18_7": { + "src_wire": "GTXE2_CHANNEL_RXCOMSASDET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDO4->GTXE2_LOGIC_OUTS_B16_6": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX4_6->GTXE2_CHANNEL_TXSEQUENCE5": { + "src_wire": "GTXE2_IMUX4_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX34_8->GTXE2_CHANNEL_RXLPMEN": { + "src_wire": "GTXE2_IMUX34_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX24_2->GTXE2_CHANNEL_TSTIN11": { + "src_wire": "GTXE2_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_4": { + "src_wire": "GTXE2_CHANNEL_RXPHALIGNDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXRESETDONE->GTXE2_LOGIC_OUTS_B20_8": { + "src_wire": "GTXE2_CHANNEL_RXRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX40_1->GTXE2_CHANNEL_TSTIN0": { + "src_wire": "GTXE2_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX21_4->GTXE2_CHANNEL_TXDATA15": { + "src_wire": "GTXE2_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX8_7->GTXE2_CHANNEL_TX8B10BBYPASS4": { + "src_wire": "GTXE2_IMUX8_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA14->GTXE2_LOGIC_OUTS_B1_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA14", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO8->GTXE2_LOGIC_OUTS_B0_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX24_7->GTXE2_CHANNEL_TSTIN16": { + "src_wire": "GTXE2_IMUX24_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN16", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX19_7->GTXE2_CHANNEL_TXDATA1": { + "src_wire": "GTXE2_IMUX19_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX5_3->GTXE2_CHANNEL_TXMAINCURSOR0": { + "src_wire": "GTXE2_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHANISALIGNED->GTXE2_LOGIC_OUTS_B18_9": { + "src_wire": "GTXE2_CHANNEL_RXCHANISALIGNED", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX8_5->GTXE2_CHANNEL_TX8B10BBYPASS5": { + "src_wire": "GTXE2_IMUX8_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX26_9->GTXE2_CHANNEL_GTRSVD14": { + "src_wire": "GTXE2_IMUX26_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX33_0->GTXE2_CHANNEL_DRPDI10": { + "src_wire": "GTXE2_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX41_0->GTXE2_CHANNEL_EYESCANMODE": { + "src_wire": "GTXE2_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_EYESCANMODE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX2_5->GTXE2_CHANNEL_TXDIFFCTRL3": { + "src_wire": "GTXE2_IMUX2_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA11->GTXE2_LOGIC_OUTS_B0_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA11", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX15_7->GTXE2_CHANNEL_TX8B10BBYPASS0": { + "src_wire": "GTXE2_IMUX15_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX1_10->GTXE2_CHANNEL_RXELECIDLEMODE1": { + "src_wire": "GTXE2_IMUX1_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL1_10->GTXE2_CHANNEL_RXOOBRESET": { + "src_wire": "GTXE2_CTRL1_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOOBRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX3_4->GTXE2_CHANNEL_TXPOSTCURSOR2": { + "src_wire": "GTXE2_IMUX3_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX34_10->GTXE2_CHANNEL_PCSRSVDIN20": { + "src_wire": "GTXE2_IMUX34_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX1_2->GTXE2_CHANNEL_RXMONITORSEL1": { + "src_wire": "GTXE2_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXCOMFINISH->GTXE2_LOGIC_OUTS_B16_5": { + "src_wire": "GTXE2_CHANNEL_TXCOMFINISH", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT4->GTXE2_LOGIC_OUTS_B13_4": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX11_2->GTXE2_CHANNEL_CPLLREFCLKSEL2": { + "src_wire": "GTXE2_IMUX11_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX18_1->GTXE2_CHANNEL_TXDATA24": { + "src_wire": "GTXE2_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX42_7->GTXE2_CHANNEL_GTRSVD4": { + "src_wire": "GTXE2_IMUX42_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA21->GTXE2_LOGIC_OUTS_B7_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA21", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA56->GTXE2_LOGIC_OUTS_B3_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA56", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX16_5->GTXE2_CHANNEL_TXDATA40": { + "src_wire": "GTXE2_IMUX16_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA40", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX29_5->GTXE2_CHANNEL_TXCHARISK5": { + "src_wire": "GTXE2_IMUX29_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX21_1->GTXE2_CHANNEL_TXDATA59": { + "src_wire": "GTXE2_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA59", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL1_7->GTXE2_CHANNEL_RXPMARESET": { + "src_wire": "GTXE2_CTRL1_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPMARESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX16_4->GTXE2_CHANNEL_TXDATA12": { + "src_wire": "GTXE2_IMUX16_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX30_10->GTXE2_CHANNEL_RXCHBONDSLAVE": { + "src_wire": "GTXE2_IMUX30_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDSLAVE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_CPLLREFCLKLOST->GTXE2_LOGIC_OUTS_B18_1": { + "src_wire": "GTXE2_CHANNEL_CPLLREFCLKLOST", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX34_3->GTXE2_CHANNEL_DRPADDR7": { + "src_wire": "GTXE2_IMUX34_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA39->GTXE2_LOGIC_OUTS_B0_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA39", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE4->GTXE2_LOGIC_OUTS_B14_9": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA19->GTXE2_LOGIC_OUTS_B0_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA19", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX0_5->GTXE2_CHANNEL_TXSEQUENCE3": { + "src_wire": "GTXE2_IMUX0_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX13_2->GTXE2_CHANNEL_TXHEADER0": { + "src_wire": "GTXE2_IMUX13_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXHEADER0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX6_8->GTXE2_CHANNEL_TXPRBSSEL1": { + "src_wire": "GTXE2_IMUX6_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX40_6->GTXE2_CHANNEL_TSTIN5": { + "src_wire": "GTXE2_IMUX40_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT5->GTXE2_LOGIC_OUTS_B8_5": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX15_2->GTXE2_CHANNEL_CPLLREFCLKSEL0": { + "src_wire": "GTXE2_IMUX15_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX42_5->GTXE2_CHANNEL_GTRSVD2": { + "src_wire": "GTXE2_IMUX42_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX30_9->GTXE2_CHANNEL_RXCHBONDMASTER": { + "src_wire": "GTXE2_IMUX30_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDMASTER", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA0->GTXE2_LOGIC_OUTS_B15_9": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX13_8->GTXE2_CHANNEL_RXOSOVRDEN": { + "src_wire": "GTXE2_IMUX13_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOSOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX11_6->GTXE2_CHANNEL_RXRATE2": { + "src_wire": "GTXE2_IMUX11_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXRATE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT0->GTXE2_LOGIC_OUTS_B13_0": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX29_0->GTXE2_CHANNEL_TXCHARDISPMODE3": { + "src_wire": "GTXE2_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX35_1->GTXE2_CHANNEL_DRPDI6": { + "src_wire": "GTXE2_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHMONITOR2->GTXE2_LOGIC_OUTS_B7_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA3->GTXE2_LOGIC_OUTS_B0_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT3->GTXE2_LOGIC_OUTS_B8_7": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX22_6->GTXE2_CHANNEL_TXDATA38": { + "src_wire": "GTXE2_IMUX22_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA38", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX31_1->GTXE2_CHANNEL_TXCHARISK3": { + "src_wire": "GTXE2_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK5->GTXE2_LOGIC_OUTS_B12_7": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX28_1->GTXE2_CHANNEL_TXCOMSAS": { + "src_wire": "GTXE2_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCOMSAS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX14_6->GTXE2_CHANNEL_RXRATE1": { + "src_wire": "GTXE2_IMUX14_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXRATE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCLKCORCNT1->GTXE2_LOGIC_OUTS_B20_5": { + "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX36_1->GTXE2_CHANNEL_DRPDI13": { + "src_wire": "GTXE2_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX39_3->GTXE2_CHANNEL_DRPADDR4": { + "src_wire": "GTXE2_IMUX39_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA46->GTXE2_LOGIC_OUTS_B4_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA46", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXP_PAD->GTXE2_CHANNEL_RXP": { + "src_wire": "GTXE2_CHANNEL_RXP_PAD", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXP", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA29->GTXE2_LOGIC_OUTS_B7_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA29", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO9->GTXE2_LOGIC_OUTS_B4_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX13_10->GTXE2_CHANNEL_RXPRBSCNTRESET": { + "src_wire": "GTXE2_IMUX13_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSCNTRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CTRL0_10->GTXE2_CHANNEL_GTRESETSEL": { + "src_wire": "GTXE2_CTRL0_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRESETSEL", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX12_9->GTXE2_CHANNEL_RX8B10BEN": { + "src_wire": "GTXE2_IMUX12_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RX8B10BEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA49->GTXE2_LOGIC_OUTS_B7_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA49", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX40_5->GTXE2_CHANNEL_TSTIN4": { + "src_wire": "GTXE2_IMUX40_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX42_4->GTXE2_CHANNEL_GTRSVD1": { + "src_wire": "GTXE2_IMUX42_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX28_10->GTXE2_CHANNEL_RXDFETAP2OVRDEN": { + "src_wire": "GTXE2_IMUX28_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX8_2->GTXE2_CHANNEL_TXCHARDISPVAL2": { + "src_wire": "GTXE2_IMUX8_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO2->GTXE2_LOGIC_OUTS_B2_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT15->GTXE2_LOGIC_OUTS_B16_1": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT15", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TXRESETDONE->GTXE2_LOGIC_OUTS_B16_4": { + "src_wire": "GTXE2_CHANNEL_TXRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT3->GTXE2_LOGIC_OUTS_B11_3": { + "src_wire": "GTXE2_CHANNEL_TSTOUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX19_10->GTXE2_CHANNEL_RXCHBONDLEVEL1": { + "src_wire": "GTXE2_IMUX19_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX42_6->GTXE2_CHANNEL_GTRSVD3": { + "src_wire": "GTXE2_IMUX42_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX25_3->GTXE2_CHANNEL_PCSRSVDIN0": { + "src_wire": "GTXE2_IMUX25_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX37_0->GTXE2_CHANNEL_DRPDI8": { + "src_wire": "GTXE2_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX18_5->GTXE2_CHANNEL_TXDATA8": { + "src_wire": "GTXE2_IMUX18_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX6_4->GTXE2_CHANNEL_TXPOSTCURSOR1": { + "src_wire": "GTXE2_IMUX6_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX44_1->GTXE2_CHANNEL_TXCOMINIT": { + "src_wire": "GTXE2_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCOMINIT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B17_9": { + "src_wire": "GTXE2_CHANNEL_RXOUTCLKFABRIC", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA59->GTXE2_LOGIC_OUTS_B5_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA59", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_2.GTXE2_IMUX31_3->GTXE2_CHANNEL_TXCHARISK2": { + "src_wire": "GTXE2_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK2", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_GTX_CHANNEL_3.json b/kintex7/tile_type_GTX_CHANNEL_3.json new file mode 100644 index 0000000..7b6fe7f --- /dev/null +++ b/kintex7/tile_type_GTX_CHANNEL_3.json @@ -0,0 +1,6854 @@ +{ + "tile_type": "GTX_CHANNEL_3", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "GTXE2_CHANNEL", + "type": "GTXE2_CHANNEL", + "site_pins": { + "RXQPIEN": "GTXE2_CHANNEL_RXQPIEN", + "TXDATA47": "GTXE2_CHANNEL_TXDATA47", + "RXDATA59": "GTXE2_CHANNEL_RXDATA59", + "TXDATA19": "GTXE2_CHANNEL_TXDATA19", + "RXDISPERR3": "GTXE2_CHANNEL_RXDISPERR3", + "RXBUFSTATUS1": "GTXE2_CHANNEL_RXBUFSTATUS1", + "TXCHARDISPMODE5": "GTXE2_CHANNEL_TXCHARDISPMODE5", + "TXCHARDISPMODE3": "GTXE2_CHANNEL_TXCHARDISPMODE3", + "RXDATA47": "GTXE2_CHANNEL_RXDATA47", + "TXDATA24": "GTXE2_CHANNEL_TXDATA24", + "TXHEADER1": "GTXE2_CHANNEL_TXHEADER1", + "TSTIN17": "GTXE2_CHANNEL_TSTIN17", + "TXPHALIGN": "GTXE2_CHANNEL_TXPHALIGN", + "CLKRSVD3": "GTXE2_CHANNEL_CLKRSVD3", + "PCSRSVDIN20": "GTXE2_CHANNEL_PCSRSVDIN20", + "RXDATA25": "GTXE2_CHANNEL_RXDATA25", + "DRPDO9": "GTXE2_CHANNEL_DRPDO9", + "RXDATA20": "GTXE2_CHANNEL_RXDATA20", + "GTRSVD4": "GTXE2_CHANNEL_GTRSVD4", + "TXCOMSAS": "GTXE2_CHANNEL_TXCOMSAS", + "PMASCANCLK2": "GTXE2_CHANNEL_PMASCANCLK2", + "RXBYTEISALIGNED": "GTXE2_CHANNEL_RXBYTEISALIGNED", + "RXPRBSSEL2": "GTXE2_CHANNEL_RXPRBSSEL2", + "TXDATA43": "GTXE2_CHANNEL_TXDATA43", + "RXDATA38": "GTXE2_CHANNEL_RXDATA38", + "RXOUTCLKFABRIC": "GTXE2_CHANNEL_RXOUTCLKFABRIC", + "TSTOUT8": "GTXE2_CHANNEL_TSTOUT8", + "RESETOVRD": "GTXE2_CHANNEL_RESETOVRD", + "GTREFCLK1": "GTXE2_CHANNEL_GTREFCLK1", + "TXSTARTSEQ": "GTXE2_CHANNEL_TXSTARTSEQ", + "RXDATA7": "GTXE2_CHANNEL_RXDATA7", + "RX8B10BEN": "GTXE2_CHANNEL_RX8B10BEN", + "PCSRSVDOUT8": "GTXE2_CHANNEL_PCSRSVDOUT8", + "TXDLYSRESETDONE": "GTXE2_CHANNEL_TXDLYSRESETDONE", + "RXMONITOROUT4": "GTXE2_CHANNEL_RXMONITOROUT4", + "RXOUTCLKSEL1": "GTXE2_CHANNEL_RXOUTCLKSEL1", + "TXPOSTCURSOR0": "GTXE2_CHANNEL_TXPOSTCURSOR0", + "RXCHARISK4": "GTXE2_CHANNEL_RXCHARISK4", + "PCSRSVDOUT11": "GTXE2_CHANNEL_PCSRSVDOUT11", + "SCANENB": "GTXE2_CHANNEL_SCANENB", + "TXCHARDISPMODE1": "GTXE2_CHANNEL_TXCHARDISPMODE1", + "RXDLYTESTENB": "GTXE2_CHANNEL_RXDLYTESTENB", + "RXPCOMMAALIGNEN": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", + "TXPRECURSOR1": "GTXE2_CHANNEL_TXPRECURSOR1", + "RXCHBONDLEVEL1": "GTXE2_CHANNEL_RXCHBONDLEVEL1", + "RXPD0": "GTXE2_CHANNEL_RXPD0", + "DRPDI15": "GTXE2_CHANNEL_DRPDI15", + "TXPOSTCURSORINV": "GTXE2_CHANNEL_TXPOSTCURSORINV", + "GTRSVD7": "GTXE2_CHANNEL_GTRSVD7", + "PMASCANMODEB": "GTXE2_CHANNEL_PMASCANMODEB", + "RXMONITOROUT0": "GTXE2_CHANNEL_RXMONITOROUT0", + "RXRATEDONE": "GTXE2_CHANNEL_RXRATEDONE", + "PMASCANOUT2": "GTXE2_CHANNEL_PMASCANOUT2", + "RXDFETAP4OVRDEN": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", + "RXDATA16": "GTXE2_CHANNEL_RXDATA16", + "TXCHARDISPMODE7": "GTXE2_CHANNEL_TXCHARDISPMODE7", + "RXDATA49": "GTXE2_CHANNEL_RXDATA49", + "SETERRSTATUS": "GTXE2_CHANNEL_SETERRSTATUS", + "TXDLYSRESET": "GTXE2_CHANNEL_TXDLYSRESET", + "TXDATA1": "GTXE2_CHANNEL_TXDATA1", + "TX8B10BBYPASS4": "GTXE2_CHANNEL_TX8B10BBYPASS4", + "PMARSVDIN20": "GTXE2_CHANNEL_PMARSVDIN20", + "TSTOUT0": "GTXE2_CHANNEL_TSTOUT0", + "RXPHDLYRESET": "GTXE2_CHANNEL_RXPHDLYRESET", + "TXDATA30": "GTXE2_CHANNEL_TXDATA30", + "DRPDI12": "GTXE2_CHANNEL_DRPDI12", + "TXRUNDISP4": "GTXE2_CHANNEL_TXRUNDISP4", + "CLKRSVD2": "GTXE2_CHANNEL_CLKRSVD2", + "PCSRSVDIN12": "GTXE2_CHANNEL_PCSRSVDIN12", + "TXCHARDISPMODE0": "GTXE2_CHANNEL_TXCHARDISPMODE0", + "TXDATA51": "GTXE2_CHANNEL_TXDATA51", + "RXMONITOROUT6": "GTXE2_CHANNEL_RXMONITOROUT6", + "CPLLREFCLKLOST": "GTXE2_CHANNEL_CPLLREFCLKLOST", + "SCANOUT2": "GTXE2_CHANNEL_SCANOUT2", + "RXDATA62": "GTXE2_CHANNEL_RXDATA62", + "DRPDI5": "GTXE2_CHANNEL_DRPDI5", + "RXRESETDONE": "GTXE2_CHANNEL_RXRESETDONE", + "TSTCLK0": "GTXE2_CHANNEL_TSTCLK0", + "DRPDO5": "GTXE2_CHANNEL_DRPDO5", + "PCSRSVDIN10": "GTXE2_CHANNEL_PCSRSVDIN10", + "RXCDRHOLD": "GTXE2_CHANNEL_RXCDRHOLD", + "PCSRSVDIN24": "GTXE2_CHANNEL_PCSRSVDIN24", + "TXDIFFCTRL0": "GTXE2_CHANNEL_TXDIFFCTRL0", + "RXMONITOROUT3": "GTXE2_CHANNEL_RXMONITOROUT3", + "TSTIN2": "GTXE2_CHANNEL_TSTIN2", + "RXRATE1": "GTXE2_CHANNEL_RXRATE1", + "PMARSVDIN0": "GTXE2_CHANNEL_PMARSVDIN0", + "RXDFELFHOLD": "GTXE2_CHANNEL_RXDFELFHOLD", + "RXDFEVPHOLD": "GTXE2_CHANNEL_RXDFEVPHOLD", + "RXDATA26": "GTXE2_CHANNEL_RXDATA26", + "TXPRBSSEL2": "GTXE2_CHANNEL_TXPRBSSEL2", + "TXDATA20": "GTXE2_CHANNEL_TXDATA20", + "TXDATA18": "GTXE2_CHANNEL_TXDATA18", + "TXCHARISK7": "GTXE2_CHANNEL_TXCHARISK7", + "LOOPBACK0": "GTXE2_CHANNEL_LOOPBACK0", + "TXPHDLYPD": "GTXE2_CHANNEL_TXPHDLYPD", + "TXPRECURSOR3": "GTXE2_CHANNEL_TXPRECURSOR3", + "DRPDO11": "GTXE2_CHANNEL_DRPDO11", + "GTXRXP": "GTXE2_CHANNEL_RXP", + "TXCHARDISPVAL7": "GTXE2_CHANNEL_TXCHARDISPVAL7", + "RXCHANBONDSEQ": "GTXE2_CHANNEL_RXCHANBONDSEQ", + "DRPDI6": "GTXE2_CHANNEL_DRPDI6", + "TXDATA48": "GTXE2_CHANNEL_TXDATA48", + "CPLLFBCLKLOST": "GTXE2_CHANNEL_CPLLFBCLKLOST", + "RXDATA55": "GTXE2_CHANNEL_RXDATA55", + "TSTIN10": "GTXE2_CHANNEL_TSTIN10", + "RXDATA60": "GTXE2_CHANNEL_RXDATA60", + "RXDATA11": "GTXE2_CHANNEL_RXDATA11", + "SCANIN1": "GTXE2_CHANNEL_SCANIN1", + "DRPDO3": "GTXE2_CHANNEL_DRPDO3", + "TXDATA8": "GTXE2_CHANNEL_TXDATA8", + "RXCHBONDEN": "GTXE2_CHANNEL_RXCHBONDEN", + "PMASCANOUT1": "GTXE2_CHANNEL_PMASCANOUT1", + "DMONITOROUT4": "GTXE2_CHANNEL_DMONITOROUT4", + "SCANOUT3": "GTXE2_CHANNEL_SCANOUT3", + "RXDATA57": "GTXE2_CHANNEL_RXDATA57", + "TXDATA25": "GTXE2_CHANNEL_TXDATA25", + "RXDFEUTOVRDEN": "GTXE2_CHANNEL_RXDFEUTOVRDEN", + "PMASCANIN3": "GTXE2_CHANNEL_PMASCANIN3", + "TXPISOPD": "GTXE2_CHANNEL_TXPISOPD", + "TXCHARDISPMODE6": "GTXE2_CHANNEL_TXCHARDISPMODE6", + "RXCDRFREQRESET": "GTXE2_CHANNEL_RXCDRFREQRESET", + "TXCHARDISPVAL4": "GTXE2_CHANNEL_TXCHARDISPVAL4", + "GTSOUTHREFCLK0": "GTXE2_CHANNEL_GTSOUTHREFCLK0", + "TXCHARDISPVAL5": "GTXE2_CHANNEL_TXCHARDISPVAL5", + "GTXRXN": "GTXE2_CHANNEL_RXN", + "TXDATA53": "GTXE2_CHANNEL_TXDATA53", + "RXPHDLYPD": "GTXE2_CHANNEL_RXPHDLYPD", + "TSTPD2": "GTXE2_CHANNEL_TSTPD2", + "RXCHBONDO1": "GTXE2_CHANNEL_RXCHBONDO1", + "RXBUFSTATUS0": "GTXE2_CHANNEL_RXBUFSTATUS0", + "TXDATA13": "GTXE2_CHANNEL_TXDATA13", + "PMASCANOUT0": "GTXE2_CHANNEL_PMASCANOUT0", + "RXCHARISCOMMA2": "GTXE2_CHANNEL_RXCHARISCOMMA2", + "TXOUTCLKPCS": "GTXE2_CHANNEL_TXOUTCLKPCS", + "PCSRSVDOUT14": "GTXE2_CHANNEL_PCSRSVDOUT14", + "RXDATA24": "GTXE2_CHANNEL_RXDATA24", + "RXDATA37": "GTXE2_CHANNEL_RXDATA37", + "TX8B10BBYPASS1": "GTXE2_CHANNEL_TX8B10BBYPASS1", + "DRPDI9": "GTXE2_CHANNEL_DRPDI9", + "TXCHARDISPMODE2": "GTXE2_CHANNEL_TXCHARDISPMODE2", + "TXOUTCLKSEL1": "GTXE2_CHANNEL_TXOUTCLKSEL1", + "RXCHBONDMASTER": "GTXE2_CHANNEL_RXCHBONDMASTER", + "TXDATA28": "GTXE2_CHANNEL_TXDATA28", + "RXDATA34": "GTXE2_CHANNEL_RXDATA34", + "CFGRESET": "GTXE2_CHANNEL_CFGRESET", + "RXDFEVPOVRDEN": "GTXE2_CHANNEL_RXDFEVPOVRDEN", + "TXDATA29": "GTXE2_CHANNEL_TXDATA29", + "GTRESETSEL": "GTXE2_CHANNEL_GTRESETSEL", + "EDTCONFIGURATION": "GTXE2_CHANNEL_EDTCONFIGURATION", + "TXCHARISK4": "GTXE2_CHANNEL_TXCHARISK4", + "TXQPISENP": "GTXE2_CHANNEL_TXQPISENP", + "RXCHBONDLEVEL0": "GTXE2_CHANNEL_RXCHBONDLEVEL0", + "PCSRSVDIN8": "GTXE2_CHANNEL_PCSRSVDIN8", + "PMASCANIN0": "GTXE2_CHANNEL_PMASCANIN0", + "DRPDO4": "GTXE2_CHANNEL_DRPDO4", + "RXDATA14": "GTXE2_CHANNEL_RXDATA14", + "TSTOUT5": "GTXE2_CHANNEL_TSTOUT5", + "EDTCLOCK": "GTXE2_CHANNEL_EDTCLOCK", + "QPLLREFCLK": "GTXE2_CHANNEL_GTQPLLREFCLK", + "RXDATA39": "GTXE2_CHANNEL_RXDATA39", + "RXLPMEN": "GTXE2_CHANNEL_RXLPMEN", + "EDTUPDATE": "GTXE2_CHANNEL_EDTUPDATE", + "TXSWING": "GTXE2_CHANNEL_TXSWING", + "TXRATE0": "GTXE2_CHANNEL_TXRATE0", + "RXDATA9": "GTXE2_CHANNEL_RXDATA9", + "TXRUNDISP5": "GTXE2_CHANNEL_TXRUNDISP5", + "RXMCOMMAALIGNEN": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", + "SCANIN2": "GTXE2_CHANNEL_SCANIN2", + "TXPOLARITY": "GTXE2_CHANNEL_TXPOLARITY", + "RXDATA32": "GTXE2_CHANNEL_RXDATA32", + "DRPDO2": "GTXE2_CHANNEL_DRPDO2", + "TXPOSTCURSOR3": "GTXE2_CHANNEL_TXPOSTCURSOR3", + "TXDLYTESTENB": "GTXE2_CHANNEL_TXDLYTESTENB", + "RXLPMLFKLOVRDEN": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", + "RXRATE2": "GTXE2_CHANNEL_RXRATE2", + "RXDFECM1EN": "GTXE2_CHANNEL_RXDFECM1EN", + "RXCDRRESETRSV": "GTXE2_CHANNEL_RXCDRRESETRSV", + "SCANCLK": "GTXE2_CHANNEL_SCANCLK", + "TSTIN6": "GTXE2_CHANNEL_TSTIN6", + "TXDLYHOLD": "GTXE2_CHANNEL_TXDLYHOLD", + "RXCHANREALIGN": "GTXE2_CHANNEL_RXCHANREALIGN", + "RXCHBONDO4": "GTXE2_CHANNEL_RXCHBONDO4", + "TXRUNDISP1": "GTXE2_CHANNEL_TXRUNDISP1", + "TXDATA23": "GTXE2_CHANNEL_TXDATA23", + "TXDATA21": "GTXE2_CHANNEL_TXDATA21", + "RXNOTINTABLE7": "GTXE2_CHANNEL_RXNOTINTABLE7", + "RXDATA29": "GTXE2_CHANNEL_RXDATA29", + "TXDATA37": "GTXE2_CHANNEL_TXDATA37", + "DMONITOROUT1": "GTXE2_CHANNEL_DMONITOROUT1", + "PMASCANCLK4": "GTXE2_CHANNEL_PMASCANCLK4", + "PCSRSVDOUT9": "GTXE2_CHANNEL_PCSRSVDOUT9", + "TXPHDLYTSTCLK": "GTXE2_CHANNEL_TXPHDLYTSTCLK", + "TXUSRCLK2": "GTXE2_CHANNEL_TXUSRCLK2", + "DRPDO15": "GTXE2_CHANNEL_DRPDO15", + "TXOUTCLKSEL2": "GTXE2_CHANNEL_TXOUTCLKSEL2", + "TX8B10BBYPASS2": "GTXE2_CHANNEL_TX8B10BBYPASS2", + "CPLLLOCKEN": "GTXE2_CHANNEL_CPLLLOCKEN", + "DRPDI4": "GTXE2_CHANNEL_DRPDI4", + "TXDATA42": "GTXE2_CHANNEL_TXDATA42", + "RXHEADERVALID": "GTXE2_CHANNEL_RXHEADERVALID", + "RXDISPERR2": "GTXE2_CHANNEL_RXDISPERR2", + "RXCHBONDI0": "GTXE2_CHANNEL_RXCHBONDI0", + "TXBUFSTATUS1": "GTXE2_CHANNEL_TXBUFSTATUS1", + "PCSRSVDOUT5": "GTXE2_CHANNEL_PCSRSVDOUT5", + "RXPRBSSEL1": "GTXE2_CHANNEL_RXPRBSSEL1", + "RXDATA2": "GTXE2_CHANNEL_RXDATA2", + "RXDATA18": "GTXE2_CHANNEL_RXDATA18", + "TXOUTCLKFABRIC": "GTXE2_CHANNEL_TXOUTCLKFABRIC", + "PMARSVDIN24": "GTXE2_CHANNEL_PMARSVDIN24", + "TXQPISENN": "GTXE2_CHANNEL_TXQPISENN", + "RXQPISENN": "GTXE2_CHANNEL_RXQPISENN", + "TSTOUT4": "GTXE2_CHANNEL_TSTOUT4", + "TXDATA22": "GTXE2_CHANNEL_TXDATA22", + "DRPWE": "GTXE2_CHANNEL_DRPWE", + "RXCHANISALIGNED": "GTXE2_CHANNEL_RXCHANISALIGNED", + "TXPHOVRDEN": "GTXE2_CHANNEL_TXPHOVRDEN", + "RXDATA54": "GTXE2_CHANNEL_RXDATA54", + "TX8B10BBYPASS6": "GTXE2_CHANNEL_TX8B10BBYPASS6", + "TXDIFFCTRL2": "GTXE2_CHANNEL_TXDIFFCTRL2", + "TXINHIBIT": "GTXE2_CHANNEL_TXINHIBIT", + "TSTIN8": "GTXE2_CHANNEL_TSTIN8", + "TSTIN3": "GTXE2_CHANNEL_TSTIN3", + "TXDATA35": "GTXE2_CHANNEL_TXDATA35", + "TXHEADER0": "GTXE2_CHANNEL_TXHEADER0", + "RXDATA8": "GTXE2_CHANNEL_RXDATA8", + "SCANIN0": "GTXE2_CHANNEL_SCANIN0", + "TXPCSRESET": "GTXE2_CHANNEL_TXPCSRESET", + "TXPOSTCURSOR4": "GTXE2_CHANNEL_TXPOSTCURSOR4", + "RXCHARISK2": "GTXE2_CHANNEL_RXCHARISK2", + "RXDLYBYPASS": "GTXE2_CHANNEL_RXDLYBYPASS", + "PCSRSVDIN14": "GTXE2_CHANNEL_PCSRSVDIN14", + "TXPRECURSORINV": "GTXE2_CHANNEL_TXPRECURSORINV", + "RXDATA40": "GTXE2_CHANNEL_RXDATA40", + "TXCHARDISPVAL2": "GTXE2_CHANNEL_TXCHARDISPVAL2", + "TX8B10BBYPASS3": "GTXE2_CHANNEL_TX8B10BBYPASS3", + "PCSRSVDOUT2": "GTXE2_CHANNEL_PCSRSVDOUT2", + "TXDATA45": "GTXE2_CHANNEL_TXDATA45", + "RXHEADER2": "GTXE2_CHANNEL_RXHEADER2", + "EYESCANTRIGGER": "GTXE2_CHANNEL_EYESCANTRIGGER", + "RXDATA53": "GTXE2_CHANNEL_RXDATA53", + "TXMAINCURSOR0": "GTXE2_CHANNEL_TXMAINCURSOR0", + "PMARSVDIN23": "GTXE2_CHANNEL_PMARSVDIN23", + "RXDATA10": "GTXE2_CHANNEL_RXDATA10", + "DRPDI10": "GTXE2_CHANNEL_DRPDI10", + "RXDATA58": "GTXE2_CHANNEL_RXDATA58", + "CPLLREFCLKSEL0": "GTXE2_CHANNEL_CPLLREFCLKSEL0", + "DMONITOROUT0": "GTXE2_CHANNEL_DMONITOROUT0", + "PCSRSVDIN2": "GTXE2_CHANNEL_PCSRSVDIN2", + "RXDLYEN": "GTXE2_CHANNEL_RXDLYEN", + "EYESCANMODE": "GTXE2_CHANNEL_EYESCANMODE", + "PMASCANOUT4": "GTXE2_CHANNEL_PMASCANOUT4", + "RXBYTEREALIGN": "GTXE2_CHANNEL_RXBYTEREALIGN", + "RXCOMWAKEDET": "GTXE2_CHANNEL_RXCOMWAKEDET", + "TSTOUT2": "GTXE2_CHANNEL_TSTOUT2", + "RXPRBSSEL0": "GTXE2_CHANNEL_RXPRBSSEL0", + "TXSEQUENCE6": "GTXE2_CHANNEL_TXSEQUENCE6", + "TSTIN14": "GTXE2_CHANNEL_TSTIN14", + "CPLLRESET": "GTXE2_CHANNEL_CPLLRESET", + "RXCHARISK1": "GTXE2_CHANNEL_RXCHARISK1", + "GTSOUTHREFCLK1": "GTXE2_CHANNEL_GTSOUTHREFCLK1", + "RXDATA3": "GTXE2_CHANNEL_RXDATA3", + "TXPRBSSEL0": "GTXE2_CHANNEL_TXPRBSSEL0", + "SCANIN4": "GTXE2_CHANNEL_SCANIN4", + "RXDATA36": "GTXE2_CHANNEL_RXDATA36", + "TXGEARBOXREADY": "GTXE2_CHANNEL_TXGEARBOXREADY", + "TXRESETDONE": "GTXE2_CHANNEL_TXRESETDONE", + "DRPDO12": "GTXE2_CHANNEL_DRPDO12", + "PCSRSVDOUT12": "GTXE2_CHANNEL_PCSRSVDOUT12", + "GTNORTHREFCLK0": "GTXE2_CHANNEL_GTNORTHREFCLK0", + "RXPMARESET": "GTXE2_CHANNEL_RXPMARESET", + "TXSYSCLKSEL0": "GTXE2_CHANNEL_TXSYSCLKSEL0", + "TSTIN7": "GTXE2_CHANNEL_TSTIN7", + "DMONITOROUT3": "GTXE2_CHANNEL_DMONITOROUT3", + "PCSRSVDIN9": "GTXE2_CHANNEL_PCSRSVDIN9", + "TXCOMINIT": "GTXE2_CHANNEL_TXCOMINIT", + "TXPD1": "GTXE2_CHANNEL_TXPD1", + "RXCHARISCOMMA7": "GTXE2_CHANNEL_RXCHARISCOMMA7", + "RXMONITORSEL0": "GTXE2_CHANNEL_RXMONITORSEL0", + "RXOUTCLKPCS": "GTXE2_CHANNEL_RXOUTCLKPCS", + "RXMONITOROUT2": "GTXE2_CHANNEL_RXMONITOROUT2", + "RXPHSLIPMONITOR1": "GTXE2_CHANNEL_RXPHSLIPMONITOR1", + "SCANIN3": "GTXE2_CHANNEL_SCANIN3", + "DRPADDR6": "GTXE2_CHANNEL_DRPADDR6", + "RXCHARISK6": "GTXE2_CHANNEL_RXCHARISK6", + "RXLPMHFOVRDEN": "GTXE2_CHANNEL_RXLPMHFOVRDEN", + "RXDLYOVRDEN": "GTXE2_CHANNEL_RXDLYOVRDEN", + "LOOPBACK2": "GTXE2_CHANNEL_LOOPBACK2", + "PCSRSVDIN11": "GTXE2_CHANNEL_PCSRSVDIN11", + "DRPCLK": "GTXE2_CHANNEL_DRPCLK", + "TXMAINCURSOR1": "GTXE2_CHANNEL_TXMAINCURSOR1", + "RXSLIDE": "GTXE2_CHANNEL_RXSLIDE", + "TXUSERRDY": "GTXE2_CHANNEL_TXUSERRDY", + "RXMONITOROUT5": "GTXE2_CHANNEL_RXMONITOROUT5", + "TX8B10BBYPASS5": "GTXE2_CHANNEL_TX8B10BBYPASS5", + "RXPCSRESET": "GTXE2_CHANNEL_RXPCSRESET", + "TXDATA26": "GTXE2_CHANNEL_TXDATA26", + "TXELECIDLE": "GTXE2_CHANNEL_TXELECIDLE", + "DRPADDR8": "GTXE2_CHANNEL_DRPADDR8", + "RXPOLARITY": "GTXE2_CHANNEL_RXPOLARITY", + "TXCHARDISPVAL6": "GTXE2_CHANNEL_TXCHARDISPVAL6", + "RXDATA35": "GTXE2_CHANNEL_RXDATA35", + "TSTPDOVRDB": "GTXE2_CHANNEL_TSTPDOVRDB", + "RXCHARISCOMMA4": "GTXE2_CHANNEL_RXCHARISCOMMA4", + "RXLPMLFHOLD": "GTXE2_CHANNEL_RXLPMLFHOLD", + "DRPDI3": "GTXE2_CHANNEL_DRPDI3", + "TXPOSTCURSOR1": "GTXE2_CHANNEL_TXPOSTCURSOR1", + "RXDATA50": "GTXE2_CHANNEL_RXDATA50", + "TXSEQUENCE5": "GTXE2_CHANNEL_TXSEQUENCE5", + "RXOUTCLK": "GTXE2_CHANNEL_GTRXOUTCLK_3", + "GTRSVD3": "GTXE2_CHANNEL_GTRSVD3", + "RXPHMONITOR3": "GTXE2_CHANNEL_RXPHMONITOR3", + "RXNOTINTABLE2": "GTXE2_CHANNEL_RXNOTINTABLE2", + "RXPHOVRDEN": "GTXE2_CHANNEL_RXPHOVRDEN", + "EYESCANRESET": "GTXE2_CHANNEL_EYESCANRESET", + "RXNOTINTABLE0": "GTXE2_CHANNEL_RXNOTINTABLE0", + "TXMARGIN2": "GTXE2_CHANNEL_TXMARGIN2", + "RXDFETAP3HOLD": "GTXE2_CHANNEL_RXDFETAP3HOLD", + "PCSRSVDIN15": "GTXE2_CHANNEL_PCSRSVDIN15", + "TXDATA38": "GTXE2_CHANNEL_TXDATA38", + "TXSEQUENCE2": "GTXE2_CHANNEL_TXSEQUENCE2", + "DRPADDR0": "GTXE2_CHANNEL_DRPADDR0", + "RXOSOVRDEN": "GTXE2_CHANNEL_RXOSOVRDEN", + "TXPHALIGNDONE": "GTXE2_CHANNEL_TXPHALIGNDONE", + "TXCHARISK3": "GTXE2_CHANNEL_TXCHARISK3", + "TSTPD0": "GTXE2_CHANNEL_TSTPD0", + "PCSRSVDOUT6": "GTXE2_CHANNEL_PCSRSVDOUT6", + "TXBUFDIFFCTRL2": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", + "TXMAINCURSOR4": "GTXE2_CHANNEL_TXMAINCURSOR4", + "RXCHARISCOMMA6": "GTXE2_CHANNEL_RXCHARISCOMMA6", + "RXDFETAP2HOLD": "GTXE2_CHANNEL_RXDFETAP2HOLD", + "RXSTATUS2": "GTXE2_CHANNEL_RXSTATUS2", + "TXRUNDISP3": "GTXE2_CHANNEL_TXRUNDISP3", + "RXDATA48": "GTXE2_CHANNEL_RXDATA48", + "TXDATA5": "GTXE2_CHANNEL_TXDATA5", + "DMONITOROUT5": "GTXE2_CHANNEL_DMONITOROUT5", + "RXCHARISCOMMA0": "GTXE2_CHANNEL_RXCHARISCOMMA0", + "TXDATA63": "GTXE2_CHANNEL_TXDATA63", + "DMONITOROUT6": "GTXE2_CHANNEL_DMONITOROUT6", + "RXELECIDLE": "GTXE2_CHANNEL_RXELECIDLE", + "RXGEARBOXSLIP": "GTXE2_CHANNEL_RXGEARBOXSLIP", + "GTRSVD13": "GTXE2_CHANNEL_GTRSVD13", + "RXMONITORSEL1": "GTXE2_CHANNEL_RXMONITORSEL1", + "RXPHMONITOR4": "GTXE2_CHANNEL_RXPHMONITOR4", + "RXDATA44": "GTXE2_CHANNEL_RXDATA44", + "SCANOUT0": "GTXE2_CHANNEL_SCANOUT0", + "PHYSTATUS": "GTXE2_CHANNEL_PHYSTATUS", + "TXRUNDISP6": "GTXE2_CHANNEL_TXRUNDISP6", + "GTRSVD14": "GTXE2_CHANNEL_GTRSVD14", + "RXDFETAP5OVRDEN": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", + "RXDATA56": "GTXE2_CHANNEL_RXDATA56", + "RXCOMSASDET": "GTXE2_CHANNEL_RXCOMSASDET", + "TXQPIBIASEN": "GTXE2_CHANNEL_TXQPIBIASEN", + "RXCHBONDLEVEL2": "GTXE2_CHANNEL_RXCHBONDLEVEL2", + "RXDATA41": "GTXE2_CHANNEL_RXDATA41", + "RXDATA33": "GTXE2_CHANNEL_RXDATA33", + "RXDATA61": "GTXE2_CHANNEL_RXDATA61", + "RXDATA1": "GTXE2_CHANNEL_RXDATA1", + "RXMONITOROUT1": "GTXE2_CHANNEL_RXMONITOROUT1", + "TXPHALIGNEN": "GTXE2_CHANNEL_TXPHALIGNEN", + "GTRSVD0": "GTXE2_CHANNEL_GTRSVD0", + "RXDISPERR1": "GTXE2_CHANNEL_RXDISPERR1", + "TXDATA56": "GTXE2_CHANNEL_TXDATA56", + "TXDIFFCTRL3": "GTXE2_CHANNEL_TXDIFFCTRL3", + "DRPADDR1": "GTXE2_CHANNEL_DRPADDR1", + "TXCHARISK0": "GTXE2_CHANNEL_TXCHARISK0", + "PCSRSVDOUT10": "GTXE2_CHANNEL_PCSRSVDOUT10", + "CPLLLOCK": "GTXE2_CHANNEL_CPLLLOCK", + "TXBUFSTATUS0": "GTXE2_CHANNEL_TXBUFSTATUS0", + "RXCHARISK7": "GTXE2_CHANNEL_RXCHARISK7", + "RXNOTINTABLE6": "GTXE2_CHANNEL_RXNOTINTABLE6", + "DRPEN": "GTXE2_CHANNEL_DRPEN", + "TXBUFDIFFCTRL0": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", + "TXDATA62": "GTXE2_CHANNEL_TXDATA62", + "TXBUFDIFFCTRL1": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", + "SCANOUT4": "GTXE2_CHANNEL_SCANOUT4", + "DRPDO6": "GTXE2_CHANNEL_DRPDO6", + "DRPADDR7": "GTXE2_CHANNEL_DRPADDR7", + "RXSTATUS1": "GTXE2_CHANNEL_RXSTATUS1", + "RXDISPERR5": "GTXE2_CHANNEL_RXDISPERR5", + "RXVALID": "GTXE2_CHANNEL_RXVALID", + "DRPDI2": "GTXE2_CHANNEL_DRPDI2", + "GTRSVD9": "GTXE2_CHANNEL_GTRSVD9", + "TXDATA60": "GTXE2_CHANNEL_TXDATA60", + "TXDLYUPDOWN": "GTXE2_CHANNEL_TXDLYUPDOWN", + "RXDFETAP3OVRDEN": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", + "RXCOMINITDET": "GTXE2_CHANNEL_RXCOMINITDET", + "RXOUTCLKSEL0": "GTXE2_CHANNEL_RXOUTCLKSEL0", + "TXDATA11": "GTXE2_CHANNEL_TXDATA11", + "RXSYSCLKSEL1": "GTXE2_CHANNEL_RXSYSCLKSEL1", + "RXSTATUS0": "GTXE2_CHANNEL_RXSTATUS0", + "TXDATA52": "GTXE2_CHANNEL_TXDATA52", + "RXDATA46": "GTXE2_CHANNEL_RXDATA46", + "RXOSHOLD": "GTXE2_CHANNEL_RXOSHOLD", + "RXCOMMADET": "GTXE2_CHANNEL_RXCOMMADET", + "RXCHBONDO3": "GTXE2_CHANNEL_RXCHBONDO3", + "RXDATA31": "GTXE2_CHANNEL_RXDATA31", + "RXUSERRDY": "GTXE2_CHANNEL_RXUSERRDY", + "RXCHBONDSLAVE": "GTXE2_CHANNEL_RXCHBONDSLAVE", + "RXCHBONDI2": "GTXE2_CHANNEL_RXCHBONDI2", + "PCSRSVDIN0": "GTXE2_CHANNEL_PCSRSVDIN0", + "TXDATA10": "GTXE2_CHANNEL_TXDATA10", + "TXCHARISK5": "GTXE2_CHANNEL_TXCHARISK5", + "RXPHMONITOR1": "GTXE2_CHANNEL_RXPHMONITOR1", + "TXDATA33": "GTXE2_CHANNEL_TXDATA33", + "TSTIN0": "GTXE2_CHANNEL_TSTIN0", + "TX8B10BEN": "GTXE2_CHANNEL_TX8B10BEN", + "PMASCANOUT3": "GTXE2_CHANNEL_PMASCANOUT3", + "RXDATA45": "GTXE2_CHANNEL_RXDATA45", + "GTREFCLKMONITOR": "GTXE2_CHANNEL_GTREFCLKMONITOR", + "PCSRSVDIN7": "GTXE2_CHANNEL_PCSRSVDIN7", + "TXCHARISK1": "GTXE2_CHANNEL_TXCHARISK1", + "TXRUNDISP0": "GTXE2_CHANNEL_TXRUNDISP0", + "RXDATA52": "GTXE2_CHANNEL_RXDATA52", + "RXPD1": "GTXE2_CHANNEL_RXPD1", + "TXDLYOVRDEN": "GTXE2_CHANNEL_TXDLYOVRDEN", + "TXDATA36": "GTXE2_CHANNEL_TXDATA36", + "RXPHSLIPMONITOR2": "GTXE2_CHANNEL_RXPHSLIPMONITOR2", + "TXMARGIN0": "GTXE2_CHANNEL_TXMARGIN0", + "TXDATA34": "GTXE2_CHANNEL_TXDATA34", + "TXSEQUENCE1": "GTXE2_CHANNEL_TXSEQUENCE1", + "RXCLKCORCNT0": "GTXE2_CHANNEL_RXCLKCORCNT0", + "RXCHBONDI1": "GTXE2_CHANNEL_RXCHBONDI1", + "GTRSVD8": "GTXE2_CHANNEL_GTRSVD8", + "CPLLPD": "GTXE2_CHANNEL_CPLLPD", + "RXDATA21": "GTXE2_CHANNEL_RXDATA21", + "RXCHARISCOMMA3": "GTXE2_CHANNEL_RXCHARISCOMMA3", + "TSTPD3": "GTXE2_CHANNEL_TSTPD3", + "GTRSVD12": "GTXE2_CHANNEL_GTRSVD12", + "RXDATA51": "GTXE2_CHANNEL_RXDATA51", + "PMASCANCLK0": "GTXE2_CHANNEL_PMASCANCLK0", + "TXDATA54": "GTXE2_CHANNEL_TXDATA54", + "TSTPD1": "GTXE2_CHANNEL_TSTPD1", + "GTXTXN": "GTXE2_CHANNEL_TXN", + "TXDATA32": "GTXE2_CHANNEL_TXDATA32", + "RXPHMONITOR2": "GTXE2_CHANNEL_RXPHMONITOR2", + "RXELECIDLEMODE1": "GTXE2_CHANNEL_RXELECIDLEMODE1", + "RXDATA28": "GTXE2_CHANNEL_RXDATA28", + "RXCHARISK5": "GTXE2_CHANNEL_RXCHARISK5", + "RXPHALIGNEN": "GTXE2_CHANNEL_RXPHALIGNEN", + "TSTIN19": "GTXE2_CHANNEL_TSTIN19", + "PMASCANIN2": "GTXE2_CHANNEL_PMASCANIN2", + "PMARSVDIN2": "GTXE2_CHANNEL_PMARSVDIN2", + "PCSRSVDIN5": "GTXE2_CHANNEL_PCSRSVDIN5", + "RXPHALIGNDONE": "GTXE2_CHANNEL_RXPHALIGNDONE", + "RXDATA0": "GTXE2_CHANNEL_RXDATA0", + "TXRATE2": "GTXE2_CHANNEL_TXRATE2", + "CPLLREFCLKSEL1": "GTXE2_CHANNEL_CPLLREFCLKSEL1", + "TSTOUT7": "GTXE2_CHANNEL_TSTOUT7", + "TXPHINITDONE": "GTXE2_CHANNEL_TXPHINITDONE", + "RXDATA15": "GTXE2_CHANNEL_RXDATA15", + "TXDATA16": "GTXE2_CHANNEL_TXDATA16", + "RXPRBSCNTRESET": "GTXE2_CHANNEL_RXPRBSCNTRESET", + "TXDATA14": "GTXE2_CHANNEL_TXDATA14", + "GTRSVD6": "GTXE2_CHANNEL_GTRSVD6", + "RXNOTINTABLE1": "GTXE2_CHANNEL_RXNOTINTABLE1", + "TXDATA2": "GTXE2_CHANNEL_TXDATA2", + "RXCHBONDO0": "GTXE2_CHANNEL_RXCHBONDO0", + "TXDEEMPH": "GTXE2_CHANNEL_TXDEEMPH", + "GTNORTHREFCLK1": "GTXE2_CHANNEL_GTNORTHREFCLK1", + "RXDFETAP4HOLD": "GTXE2_CHANNEL_RXDFETAP4HOLD", + "RXDFETAP5HOLD": "GTXE2_CHANNEL_RXDFETAP5HOLD", + "TXDATA7": "GTXE2_CHANNEL_TXDATA7", + "RXCHBONDO2": "GTXE2_CHANNEL_RXCHBONDO2", + "TXPRECURSOR2": "GTXE2_CHANNEL_TXPRECURSOR2", + "DRPDI11": "GTXE2_CHANNEL_DRPDI11", + "TXDETECTRX": "GTXE2_CHANNEL_TXDETECTRX", + "TXDATA0": "GTXE2_CHANNEL_TXDATA0", + "RXNOTINTABLE5": "GTXE2_CHANNEL_RXNOTINTABLE5", + "DRPADDR3": "GTXE2_CHANNEL_DRPADDR3", + "RXDATA42": "GTXE2_CHANNEL_RXDATA42", + "TXUSRCLK": "GTXE2_CHANNEL_TXUSRCLK", + "TXSYSCLKSEL1": "GTXE2_CHANNEL_TXSYSCLKSEL1", + "TX8B10BBYPASS0": "GTXE2_CHANNEL_TX8B10BBYPASS0", + "RXQPISENP": "GTXE2_CHANNEL_RXQPISENP", + "DRPDI13": "GTXE2_CHANNEL_DRPDI13", + "RXBUFSTATUS2": "GTXE2_CHANNEL_RXBUFSTATUS2", + "RXDISPERR0": "GTXE2_CHANNEL_RXDISPERR0", + "TXDATA46": "GTXE2_CHANNEL_TXDATA46", + "DRPDO1": "GTXE2_CHANNEL_DRPDO1", + "TXDATA15": "GTXE2_CHANNEL_TXDATA15", + "PCSRSVDIN3": "GTXE2_CHANNEL_PCSRSVDIN3", + "RXDLYSRESETDONE": "GTXE2_CHANNEL_RXDLYSRESETDONE", + "PCSRSVDIN1": "GTXE2_CHANNEL_PCSRSVDIN1", + "TXCHARDISPVAL3": "GTXE2_CHANNEL_TXCHARDISPVAL3", + "RXDFELFOVRDEN": "GTXE2_CHANNEL_RXDFELFOVRDEN", + "TXDATA41": "GTXE2_CHANNEL_TXDATA41", + "PCSRSVDOUT13": "GTXE2_CHANNEL_PCSRSVDOUT13", + "RXDATA27": "GTXE2_CHANNEL_RXDATA27", + "RXDATA30": "GTXE2_CHANNEL_RXDATA30", + "RXCHBONDI4": "GTXE2_CHANNEL_RXCHBONDI4", + "EDTSINGLEBYPASSCHAIN": "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", + "RXPRBSERR": "GTXE2_CHANNEL_RXPRBSERR", + "TXCOMWAKE": "GTXE2_CHANNEL_TXCOMWAKE", + "RXRATE0": "GTXE2_CHANNEL_RXRATE0", + "TSTIN4": "GTXE2_CHANNEL_TSTIN4", + "PMARSVDIN4": "GTXE2_CHANNEL_PMARSVDIN4", + "RXOUTCLKSEL2": "GTXE2_CHANNEL_RXOUTCLKSEL2", + "TSTOUT6": "GTXE2_CHANNEL_TSTOUT6", + "RXOOBRESET": "GTXE2_CHANNEL_RXOOBRESET", + "TSTPD4": "GTXE2_CHANNEL_TSTPD4", + "PMASCANRSTEN": "GTXE2_CHANNEL_PMASCANRSTEN", + "DRPDI8": "GTXE2_CHANNEL_DRPDI8", + "RXELECIDLEMODE0": "GTXE2_CHANNEL_RXELECIDLEMODE0", + "RXDATA6": "GTXE2_CHANNEL_RXDATA6", + "TXQPISTRONGPDOWN": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", + "TXHEADER2": "GTXE2_CHANNEL_TXHEADER2", + "PCSRSVDIN6": "GTXE2_CHANNEL_PCSRSVDIN6", + "DMONITOROUT2": "GTXE2_CHANNEL_DMONITOROUT2", + "TXDATA39": "GTXE2_CHANNEL_TXDATA39", + "TXRUNDISP7": "GTXE2_CHANNEL_TXRUNDISP7", + "TXPMARESET": "GTXE2_CHANNEL_TXPMARESET", + "RXDFETAP2OVRDEN": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", + "TX8B10BBYPASS7": "GTXE2_CHANNEL_TX8B10BBYPASS7", + "TSTIN1": "GTXE2_CHANNEL_TSTIN1", + "RXPHSLIPMONITOR0": "GTXE2_CHANNEL_RXPHSLIPMONITOR0", + "DRPDI1": "GTXE2_CHANNEL_DRPDI1", + "RXCDRRESET": "GTXE2_CHANNEL_RXCDRRESET", + "RXCHARISCOMMA1": "GTXE2_CHANNEL_RXCHARISCOMMA1", + "TXPOSTCURSOR2": "GTXE2_CHANNEL_TXPOSTCURSOR2", + "EYESCANDATAERROR": "GTXE2_CHANNEL_EYESCANDATAERROR", + "TXDATA6": "GTXE2_CHANNEL_TXDATA6", + "RXDLYSRESET": "GTXE2_CHANNEL_RXDLYSRESET", + "TXCHARDISPVAL0": "GTXE2_CHANNEL_TXCHARDISPVAL0", + "TXMAINCURSOR2": "GTXE2_CHANNEL_TXMAINCURSOR2", + "EDTBYPASS": "GTXE2_CHANNEL_EDTBYPASS", + "RXDISPERR6": "GTXE2_CHANNEL_RXDISPERR6", + "TXDATA44": "GTXE2_CHANNEL_TXDATA44", + "RXUSRCLK2": "GTXE2_CHANNEL_RXUSRCLK2", + "RXCHBONDI3": "GTXE2_CHANNEL_RXCHBONDI3", + "TSTCLK1": "GTXE2_CHANNEL_TSTCLK1", + "GTREFCLK0": "GTXE2_CHANNEL_GTREFCLK0", + "DRPDO8": "GTXE2_CHANNEL_DRPDO8", + "RXPHMONITOR0": "GTXE2_CHANNEL_RXPHMONITOR0", + "PMARSVDIN22": "GTXE2_CHANNEL_PMARSVDIN22", + "RXCHARISK3": "GTXE2_CHANNEL_RXCHARISK3", + "RXDFEAGCHOLD": "GTXE2_CHANNEL_RXDFEAGCHOLD", + "TXCHARISK2": "GTXE2_CHANNEL_TXCHARISK2", + "PCSRSVDIN23": "GTXE2_CHANNEL_PCSRSVDIN23", + "TSTOUT1": "GTXE2_CHANNEL_TSTOUT1", + "GTRSVD5": "GTXE2_CHANNEL_GTRSVD5", + "RXPHSLIPMONITOR3": "GTXE2_CHANNEL_RXPHSLIPMONITOR3", + "TXCHARDISPMODE4": "GTXE2_CHANNEL_TXCHARDISPMODE4", + "RXHEADER0": "GTXE2_CHANNEL_RXHEADER0", + "DRPDO0": "GTXE2_CHANNEL_DRPDO0", + "TXCHARISK6": "GTXE2_CHANNEL_TXCHARISK6", + "RXCLKCORCNT1": "GTXE2_CHANNEL_RXCLKCORCNT1", + "RXDFEAGCOVRDEN": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", + "TXDATA61": "GTXE2_CHANNEL_TXDATA61", + "RXDFEVSEN": "GTXE2_CHANNEL_RXDFEVSEN", + "DRPDO7": "GTXE2_CHANNEL_DRPDO7", + "PMARSVDIN21": "GTXE2_CHANNEL_PMARSVDIN21", + "PCSRSVDOUT1": "GTXE2_CHANNEL_PCSRSVDOUT1", + "PCSRSVDOUT4": "GTXE2_CHANNEL_PCSRSVDOUT4", + "RXNOTINTABLE4": "GTXE2_CHANNEL_RXNOTINTABLE4", + "RXNOTINTABLE3": "GTXE2_CHANNEL_RXNOTINTABLE3", + "GTRSVD15": "GTXE2_CHANNEL_GTRSVD15", + "TSTIN15": "GTXE2_CHANNEL_TSTIN15", + "DRPDO13": "GTXE2_CHANNEL_DRPDO13", + "RXDATAVALID": "GTXE2_CHANNEL_RXDATAVALID", + "RXDATA19": "GTXE2_CHANNEL_RXDATA19", + "RXBUFRESET": "GTXE2_CHANNEL_RXBUFRESET", + "TXPD0": "GTXE2_CHANNEL_TXPD0", + "PMARSVDIN1": "GTXE2_CHANNEL_PMARSVDIN1", + "RXDATA63": "GTXE2_CHANNEL_RXDATA63", + "TXMAINCURSOR3": "GTXE2_CHANNEL_TXMAINCURSOR3", + "RXDEBUGPULSE": "GTXE2_CHANNEL_RXDEBUGPULSE", + "RXDATA4": "GTXE2_CHANNEL_RXDATA4", + "PMASCANIN1": "GTXE2_CHANNEL_PMASCANIN1", + "TSTIN11": "GTXE2_CHANNEL_TSTIN11", + "CPLLREFCLKSEL2": "GTXE2_CHANNEL_CPLLREFCLKSEL2", + "SCANOUT1": "GTXE2_CHANNEL_SCANOUT1", + "TXRUNDISP2": "GTXE2_CHANNEL_TXRUNDISP2", + "PCSRSVDIN13": "GTXE2_CHANNEL_PCSRSVDIN13", + "SCANMODEB": "GTXE2_CHANNEL_SCANMODEB", + "GTRXRESET": "GTXE2_CHANNEL_GTRXRESET", + "PCSRSVDIN22": "GTXE2_CHANNEL_PCSRSVDIN22", + "TXDATA3": "GTXE2_CHANNEL_TXDATA3", + "TXMAINCURSOR5": "GTXE2_CHANNEL_TXMAINCURSOR5", + "GTRSVD2": "GTXE2_CHANNEL_GTRSVD2", + "CLKRSVD1": "GTXE2_CHANNEL_CLKRSVD1", + "TXOUTCLKSEL0": "GTXE2_CHANNEL_TXOUTCLKSEL0", + "TXDATA57": "GTXE2_CHANNEL_TXDATA57", + "TXPDELECIDLEMODE": "GTXE2_CHANNEL_TXPDELECIDLEMODE", + "PCSRSVDIN21": "GTXE2_CHANNEL_PCSRSVDIN21", + "TSTOUT3": "GTXE2_CHANNEL_TSTOUT3", + "PCSRSVDOUT15": "GTXE2_CHANNEL_PCSRSVDOUT15", + "TXSEQUENCE3": "GTXE2_CHANNEL_TXSEQUENCE3", + "TSTIN18": "GTXE2_CHANNEL_TSTIN18", + "TXRATE1": "GTXE2_CHANNEL_TXRATE1", + "TXSEQUENCE4": "GTXE2_CHANNEL_TXSEQUENCE4", + "RXSTARTOFSEQ": "GTXE2_CHANNEL_RXSTARTOFSEQ", + "RXPHALIGN": "GTXE2_CHANNEL_RXPHALIGN", + "RXDFEUTHOLD": "GTXE2_CHANNEL_RXDFEUTHOLD", + "DRPDI14": "GTXE2_CHANNEL_DRPDI14", + "TXRATEDONE": "GTXE2_CHANNEL_TXRATEDONE", + "TXDIFFPD": "GTXE2_CHANNEL_TXDIFFPD", + "TXCHARDISPVAL1": "GTXE2_CHANNEL_TXCHARDISPVAL1", + "RXDFELPMRESET": "GTXE2_CHANNEL_RXDFELPMRESET", + "RXCDRLOCK": "GTXE2_CHANNEL_RXCDRLOCK", + "TXDATA31": "GTXE2_CHANNEL_TXDATA31", + "RXCHARISK0": "GTXE2_CHANNEL_RXCHARISK0", + "RXDATA43": "GTXE2_CHANNEL_RXDATA43", + "TXDATA55": "GTXE2_CHANNEL_TXDATA55", + "TSTIN9": "GTXE2_CHANNEL_TSTIN9", + "TXQPIWEAKPUP": "GTXE2_CHANNEL_TXQPIWEAKPUP", + "TXDATA4": "GTXE2_CHANNEL_TXDATA4", + "RXSYSCLKSEL0": "GTXE2_CHANNEL_RXSYSCLKSEL0", + "DRPDO14": "GTXE2_CHANNEL_DRPDO14", + "TSTIN12": "GTXE2_CHANNEL_TSTIN12", + "DRPDI7": "GTXE2_CHANNEL_DRPDI7", + "TXSEQUENCE0": "GTXE2_CHANNEL_TXSEQUENCE0", + "RXDISPERR7": "GTXE2_CHANNEL_RXDISPERR7", + "CPLLLOCKDETCLK": "GTXE2_CHANNEL_CPLLLOCKDETCLK", + "DRPADDR4": "GTXE2_CHANNEL_DRPADDR4", + "RXCOMMADETEN": "GTXE2_CHANNEL_RXCOMMADETEN", + "DRPADDR2": "GTXE2_CHANNEL_DRPADDR2", + "TXPRECURSOR0": "GTXE2_CHANNEL_TXPRECURSOR0", + "PCSRSVDOUT7": "GTXE2_CHANNEL_PCSRSVDOUT7", + "RXPHSLIPMONITOR4": "GTXE2_CHANNEL_RXPHSLIPMONITOR4", + "TXPHINIT": "GTXE2_CHANNEL_TXPHINIT", + "DRPADDR5": "GTXE2_CHANNEL_DRPADDR5", + "TXDATA50": "GTXE2_CHANNEL_TXDATA50", + "PMASCANIN4": "GTXE2_CHANNEL_PMASCANIN4", + "TXPRECURSOR4": "GTXE2_CHANNEL_TXPRECURSOR4", + "PMASCANCLK1": "GTXE2_CHANNEL_PMASCANCLK1", + "TXPRBSSEL1": "GTXE2_CHANNEL_TXPRBSSEL1", + "GTRSVD11": "GTXE2_CHANNEL_GTRSVD11", + "DRPDO10": "GTXE2_CHANNEL_DRPDO10", + "TXDATA12": "GTXE2_CHANNEL_TXDATA12", + "RXDATA5": "GTXE2_CHANNEL_RXDATA5", + "TXCOMFINISH": "GTXE2_CHANNEL_TXCOMFINISH", + "TXDATA17": "GTXE2_CHANNEL_TXDATA17", + "GTTXRESET": "GTXE2_CHANNEL_GTTXRESET", + "PMASCANCLK3": "GTXE2_CHANNEL_PMASCANCLK3", + "TXDIFFCTRL1": "GTXE2_CHANNEL_TXDIFFCTRL1", + "TXPHDLYRESET": "GTXE2_CHANNEL_TXPHDLYRESET", + "RXDATA13": "GTXE2_CHANNEL_RXDATA13", + "TXDATA9": "GTXE2_CHANNEL_TXDATA9", + "PCSRSVDIN4": "GTXE2_CHANNEL_PCSRSVDIN4", + "DMONITOROUT7": "GTXE2_CHANNEL_DMONITOROUT7", + "TSTIN5": "GTXE2_CHANNEL_TSTIN5", + "RXDISPERR4": "GTXE2_CHANNEL_RXDISPERR4", + "TXDATA40": "GTXE2_CHANNEL_TXDATA40", + "TXDATA49": "GTXE2_CHANNEL_TXDATA49", + "PMARSVDIN3": "GTXE2_CHANNEL_PMARSVDIN3", + "RXDATA23": "GTXE2_CHANNEL_RXDATA23", + "TXMARGIN1": "GTXE2_CHANNEL_TXMARGIN1", + "TXDLYBYPASS": "GTXE2_CHANNEL_TXDLYBYPASS", + "PCSRSVDOUT0": "GTXE2_CHANNEL_PCSRSVDOUT0", + "TXOUTCLK": "GTXE2_CHANNEL_GTTXOUTCLK_3", + "RXLPMHFHOLD": "GTXE2_CHANNEL_RXLPMHFHOLD", + "RXDFEXYDEN": "GTXE2_CHANNEL_RXDFEXYDEN", + "TSTOUT9": "GTXE2_CHANNEL_TSTOUT9", + "TXDLYEN": "GTXE2_CHANNEL_TXDLYEN", + "RXUSRCLK": "GTXE2_CHANNEL_RXUSRCLK", + "RXDFEXYDHOLD": "GTXE2_CHANNEL_RXDFEXYDHOLD", + "TSTIN13": "GTXE2_CHANNEL_TSTIN13", + "TXPRBSFORCEERR": "GTXE2_CHANNEL_TXPRBSFORCEERR", + "CLKRSVD0": "GTXE2_CHANNEL_CLKRSVD0", + "RXPCD1DONE": "GTXE2_CHANNEL_RXPCD1DONE", + "DRPRDY": "GTXE2_CHANNEL_DRPRDY", + "RXDFEXYDOVRDEN": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", + "LOOPBACK1": "GTXE2_CHANNEL_LOOPBACK1", + "GTGREFCLK": "GTXE2_CHANNEL_GTGREFCLK", + "RXHEADER1": "GTXE2_CHANNEL_RXHEADER1", + "GTRSVD1": "GTXE2_CHANNEL_GTRSVD1", + "TXMAINCURSOR6": "GTXE2_CHANNEL_TXMAINCURSOR6", + "RXDATA17": "GTXE2_CHANNEL_RXDATA17", + "RXDATA22": "GTXE2_CHANNEL_RXDATA22", + "PCSRSVDOUT3": "GTXE2_CHANNEL_PCSRSVDOUT3", + "DRPDI0": "GTXE2_CHANNEL_DRPDI0", + "RXCHARISCOMMA5": "GTXE2_CHANNEL_RXCHARISCOMMA5", + "TXDATA58": "GTXE2_CHANNEL_TXDATA58", + "QPLLCLK": "GTXE2_CHANNEL_GTQPLLCLK", + "RXDDIEN": "GTXE2_CHANNEL_RXDDIEN", + "GTXTXP": "GTXE2_CHANNEL_TXP", + "PMASCANENB": "GTXE2_CHANNEL_PMASCANENB", + "TXDATA59": "GTXE2_CHANNEL_TXDATA59", + "GTRSVD10": "GTXE2_CHANNEL_GTRSVD10", + "RXDATA12": "GTXE2_CHANNEL_RXDATA12", + "RXCDROVRDEN": "GTXE2_CHANNEL_RXCDROVRDEN", + "TSTIN16": "GTXE2_CHANNEL_TSTIN16", + "TXDATA27": "GTXE2_CHANNEL_TXDATA27" + }, + "x_coord": 0 + }, + { + "y_coord": 47, + "name": "X0Y47", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "GTXE2_CHANNEL_RXN_PAD" + }, + "x_coord": 0 + }, + { + "y_coord": 48, + "name": "X0Y48", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "GTXE2_CHANNEL_RXP_PAD" + }, + "x_coord": 0 + }, + { + "y_coord": 7, + "name": "X0Y7", + "prefix": "OPAD", + "type": "OPAD", + "site_pins": { + "I": "GTXE2_CHANNEL_TXN_PAD" + }, + "x_coord": 0 + }, + { + "y_coord": 8, + "name": "X0Y8", + "prefix": "OPAD", + "type": "OPAD", + "site_pins": { + "I": "GTXE2_CHANNEL_TXP_PAD" + }, + "x_coord": 0 + } + ], + "wires": [ + "GTXE2_CHANNEL_PMASCANIN2", + "GTXE2_CHANNEL_RXDFETAP3HOLD", + "GTXE2_CHANNEL_RXHEADER0", + "GTXE2_IMUX29_3", + "GTXE2_LOGIC_OUTS_B21_5", + "GTXE2_CHANNEL_TXQPISENN", + "GTXE2_IMUX42_5", + "GTXE2_CHANNEL_TXDATA44", + "GTXE2_FAN2_6", + "GTXE2_IMUX23_5", + "GTXE2_LOGIC_OUTS_B19_1", + "GTXE2_CHANNEL_GTREFCLKMONITOR", + "GTXE2_CHANNEL_CPLLREFCLKSEL1", + "GTXE2_IMUX29_9", + "GTXE2_FAN5_4", + "GTXE2_LOGIC_OUTS_B23_10", + "GTXE2_CHANNEL_RXBUFSTATUS0", + "GTXE2_CHANNEL_PCSRSVDOUT13", + "GTXE2_CHANNEL_RXNOTINTABLE5", + "GTXE2_IMUX46_0", + "GTXE2_IMUX20_7", + "GTXE2_CHANNEL_DRPDI6", + "GTXE2_BYP2_3", + "GTXE2_CHANNEL_RXCHARISK4", + "GTXE2_CHANNEL_TXDIFFPD", + "GTXE2_IMUX4_4", + "GTXE2_IMUX6_0", + "GTXE2_IMUX25_4", + "GTXE2_IMUX3_2", + "GTXE2_CHANNEL_TSTIN11", + "GTXE2_CHANNEL_TSTIN8", + "GTXE2_IMUX31_7", + "GTXE2_CHANNEL_CPLLFBCLKLOST", + "GTXE2_IMUX41_9", + "GTXE2_CHANNEL_RXDLYEN", + "GTXE2_CHANNEL_RXCHARISK6", + "GTXE2_CHANNEL_GTQPLLREFCLK", + "GTXE2_CHANNEL_RXDISPERR7", + "GTXE2_CHANNEL_TXDLYBYPASS", + "GTXE2_CHANNEL_NORTHREFCLK1", + "GTXE2_IMUX26_0", + "GTXE2_CHANNEL_TXCHARDISPMODE0", + "GTXE2_LOGIC_OUTS_B23_6", + "GTXE2_CHANNEL_PCSRSVDIN24", + "GTXE2_IMUX9_2", + "GTXE2_LOGIC_OUTS_B19_2", + "GTXE2_LOGIC_OUTS_B22_8", + "GTXE2_LOGIC_OUTS_B4_1", + "GTXE2_FAN7_10", + "GTXE2_CHANNEL_RXDATA35", + "GTXE2_IMUX35_10", + "GTXE2_IMUX33_8", + "GTXE2_IMUX42_8", + "GTXE2_FAN3_8", + "GTXE2_BYP0_5", + "GTXE2_CHANNEL_PCSRSVDOUT5", + "GTXE2_CTRL0_4", + "GTXE2_CHANNEL_TXDATA24", + "GTXE2_BYP7_7", + "GTXE2_IMUX7_2", + "GTXE2_IMUX30_8", + "GTXE2_FAN5_10", + "GTXE2_IMUX15_9", + "GTXE2_CHANNEL_RXHEADERVALID", + "GTXE2_BYP1_10", + "GTXE2_CHANNEL_CPLLPD", + "GTXE2_CHANNEL_RXDFETAP2OVRDEN", + "GTXE2_CHANNEL_RXBYTEISALIGNED", + "GTXE2_LOGIC_OUTS_B2_1", + "GTXE2_CHANNEL_TXDATA48", + "GTXE2_CHANNEL_TXDATA32", + "GTXE2_CHANNEL_RXCHBONDO2", + "GTXE2_CHANNEL_PMASCANCLK1", + "GTXE2_CHANNEL_TXDLYSRESET", + "GTXE2_IMUX35_9", + "GTXE2_LOGIC_OUTS_B9_7", + "GTXE2_IMUX43_0", + "GTXE2_IMUX23_7", + "GTXE2_CHANNEL_PMASCANCLK3", + "GTXE2_FAN1_9", + "GTXE2_CHANNEL_CPLLREFCLKSEL0", + "GTXE2_IMUX26_9", + "GTXE2_LOGIC_OUTS_B1_4", + "GTXE2_CHANNEL_TXDATA29", + "GTXE2_LOGIC_OUTS_B20_8", + "GTXE2_FAN3_9", + "GTXE2_IMUX18_7", + "GTXE2_LOGIC_OUTS_B12_4", + "GTXE2_CHANNEL_TXCHARISK7", + "GTXE2_LOGIC_OUTS_B1_9", + "GTXE2_CHANNEL_RXDATA28", + "GTXE2_CHANNEL_RXMCOMMAALIGNEN", + "GTXE2_IMUX47_8", + "GTXE2_CHANNEL_RXCHBONDMASTER", + "GTXE2_CHANNEL_TXCHARDISPVAL5", + "GTXE2_IMUX19_6", + "GTXE2_IMUX10_4", + "GTXE2_FAN5_3", + "GTXE2_CHANNEL_RXPHSLIPMONITOR4", + "GTXE2_FAN1_8", + "GTXE2_CHANNEL_TXCHARISK3", + "GTXE2_BYP1_4", + "GTXE2_FAN0_6", + "GTXE2_CHANNEL_DRPADDR4", + "GTXE2_CHANNEL_RXPRBSSEL2", + "GTXE2_IMUX1_3", + "GTXE2_IMUX1_5", + "GTXE2_IMUX31_10", + "GTXE2_LOGIC_OUTS_B15_9", + "GTXE2_CHANNEL_RXN", + "GTXE2_CHANNEL_TXDEEMPH", + "GTXE2_CHANNEL_TSTIN6", + "GTXE2_CHANNEL_PMASCANRSTEN", + "GTXE2_CHANNEL_LOOPBACK1", + "GTXE2_CHANNEL_TXOUTCLK_0", + "GTXE2_BYP1_2", + "GTXE2_CHANNEL_TXDATA63", + "GTXE2_IMUX6_2", + "GTXE2_LOGIC_OUTS_B23_5", + "GTXE2_CHANNEL_RXDATA15", + "GTXE2_CHANNEL_TXCHARDISPMODE5", + "GTXE2_LOGIC_OUTS_B7_9", + "GTXE2_CHANNEL_RXCDRRESET", + "GTXE2_CHANNEL_TSTIN4", + "GTXE2_CHANNEL_RXOOBRESET", + "GTXE2_FAN7_6", + "GTXE2_CTRL0_7", + "GTXE2_IMUX37_2", + "GTXE2_CHANNEL_RXDATA50", + "GTXE2_CHANNEL_TXDATA36", + "GTXE2_IMUX45_0", + "GTXE2_BYP4_7", + "GTXE2_FAN7_0", + "GTXE2_LOGIC_OUTS_B19_6", + "GTXE2_CHANNEL_RXDATA54", + "GTXE2_CHANNEL_RXCOMMADET", + "GTXE2_CLK1_7", + "GTXE2_IMUX46_1", + "GTXE2_CHANNEL_RXQPIEN", + "GTXE2_CHANNEL_RXSTATUS2", + "GTXE2_IMUX30_2", + "GTXE2_CHANNEL_RXOUTCLKSEL2", + "GTXE2_BYP5_5", + "GTXE2_IMUX22_4", + "GTXE2_BYP2_0", + "GTXE2_IMUX35_1", + "GTXE2_CHANNEL_RXDATA17", + "GTXE2_IMUX15_0", + "GTXE2_BYP5_3", + "GTXE2_LOGIC_OUTS_B6_7", + "GTXE2_CHANNEL_RXCOMWAKEDET", + "GTXE2_LOGIC_OUTS_B3_0", + "GTXE2_BYP1_1", + "GTXE2_LOGIC_OUTS_B3_1", + "GTXE2_IMUX24_4", + "GTXE2_FAN1_5", + "GTXE2_IMUX44_0", + "GTXE2_LOGIC_OUTS_B5_3", + "GTXE2_CHANNEL_RXSTATUS1", + "GTXE2_CHANNEL_RXDATA62", + "GTXE2_BYP0_7", + "GTXE2_LOGIC_OUTS_B19_10", + "GTXE2_CLK1_9", + "GTXE2_CHANNEL_PCSRSVDIN7", + "GTXE2_LOGIC_OUTS_B7_7", + "GTXE2_CHANNEL_TXDATA28", + "GTXE2_IMUX22_10", + "GTXE2_LOGIC_OUTS_B21_3", + "GTXE2_FAN5_8", + "GTXE2_IMUX39_5", + "GTXE2_IMUX22_1", + "GTXE2_CHANNEL_PMARSVDIN24", + "GTXE2_CHANNEL_RXCHBONDI3", + "GTXE2_IMUX8_8", + "GTXE2_IMUX44_2", + "GTXE2_LOGIC_OUTS_B11_4", + "GTXE2_CHANNEL_TSTIN19", + "GTXE2_IMUX23_0", + "GTXE2_CHANNEL_TXDATA13", + "GTXE2_LOGIC_OUTS_B21_8", + "GTXE2_IMUX44_9", + "GTXE2_CHANNEL_GTRSVD0", + "GTXE2_CHANNEL_DRPCLK", + "GTXE2_CHANNEL_GTRSVD13", + "GTXE2_BYP5_8", + "GTXE2_IMUX11_9", + "GTXE2_LOGIC_OUTS_B8_6", + "GTXE2_CHANNEL_RXCHARISCOMMA4", + "GTXE2_IMUX42_2", + "GTXE2_IMUX41_10", + "GTXE2_CHANNEL_TSTPD2", + "GTXE2_CHANNEL_TXPRECURSOR2", + "GTXE2_LOGIC_OUTS_B11_9", + "GTXE2_IMUX2_7", + "GTXE2_CHANNEL_TXDATA19", + "GTXE2_IMUX1_4", + "GTXE2_CHANNEL_TXSEQUENCE6", + "GTXE2_IMUX31_3", + "GTXE2_LOGIC_OUTS_B23_9", + "GTXE2_LOGIC_OUTS_B10_8", + "GTXE2_CHANNEL_CLKRSVD2", + "GTXE2_CLK1_10", + "GTXE2_IMUX13_9", + "GTXE2_IMUX21_10", + "GTXE2_BYP7_10", + "GTXE2_CTRL0_8", + "GTXE2_CHANNEL_TXPHDLYRESET", + "GTXE2_BYP7_2", + "GTXE2_CHANNEL_PCSRSVDOUT15", + "GTXE2_BYP6_8", + "GTXE2_CHANNEL_TXDATA16", + "GTXE2_IMUX11_8", + "GTXE2_CHANNEL_TXMAINCURSOR1", + "GTXE2_CHANNEL_PCSRSVDOUT11", + "GTXE2_IMUX22_8", + "GTXE2_CHANNEL_GTTXOUTCLK_3", + "GTXE2_IMUX17_1", + "GTXE2_FAN3_10", + "GTXE2_CHANNEL_TXRUNDISP5", + "GTXE2_CHANNEL_TXPOSTCURSOR0", + "GTXE2_IMUX21_0", + "GTXE2_CTRL1_7", + "GTXE2_CHANNEL_RXOUTCLKFABRIC", + "GTXE2_IMUX45_8", + "GTXE2_CHANNEL_RXCHBONDO4", + "GTXE2_LOGIC_OUTS_B20_0", + "GTXE2_BYP6_5", + "GTXE2_IMUX33_10", + "GTXE2_IMUX46_3", + "GTXE2_IMUX8_7", + "GTXE2_CHANNEL_RXOSHOLD", + "GTXE2_BYP2_10", + "GTXE2_CHANNEL_TXDATA8", + "GTXE2_CHANNEL_RXCHARISK2", + "GTXE2_CHANNEL_DRPDO10", + "GTXE2_LOGIC_OUTS_B17_9", + "GTXE2_IMUX9_1", + "GTXE2_IMUX12_1", + "GTXE2_IMUX0_10", + "GTXE2_CHANNEL_RXELECIDLE", + "GTXE2_CHANNEL_DRPDI10", + "GTXE2_FAN7_1", + "GTXE2_CHANNEL_RXDATA42", + "GTXE2_CHANNEL_TXCHARDISPMODE6", + "GTXE2_IMUX5_8", + "GTXE2_LOGIC_OUTS_B5_8", + "GTXE2_CHANNEL_TXQPISENP", + "GTXE2_CHANNEL_RXDATA21", + "GTXE2_CHANNEL_TXPOSTCURSORINV", + "GTXE2_LOGIC_OUTS_B9_0", + "GTXE2_IMUX0_5", + "GTXE2_BYP1_7", + "GTXE2_FAN4_9", + "GTXE2_IMUX25_10", + "GTXE2_CHANNEL_RXELECIDLEMODE0", + "GTXE2_LOGIC_OUTS_B20_10", + "GTXE2_CHANNEL_RXDATA39", + "GTXE2_CHANNEL_TXPHOVRDEN", + "GTXE2_IMUX22_3", + "GTXE2_CHANNEL_PMARSVDIN22", + "GTXE2_IMUX36_2", + "GTXE2_FAN6_3", + "GTXE2_CHANNEL_GTRSVD5", + "GTXE2_LOGIC_OUTS_B3_2", + "GTXE2_IMUX2_5", + "GTXE2_IMUX33_4", + "GTXE2_CHANNEL_DMONITOROUT4", + "GTXE2_IMUX40_3", + "GTXE2_CHANNEL_DMONITOROUT5", + "GTXE2_CHANNEL_TXRUNDISP4", + "GTXE2_CHANNEL_DRPADDR8", + "GTXE2_IMUX27_4", + "GTXE2_IMUX36_3", + "GTXE2_LOGIC_OUTS_B8_10", + "GTXE2_IMUX31_9", + "GTXE2_LOGIC_OUTS_B16_0", + "GTXE2_IMUX11_0", + "GTXE2_CHANNEL_PCSRSVDOUT1", + "GTXE2_IMUX24_1", + "GTXE2_FAN3_0", + "GTXE2_CHANNEL_RXVALID", + "GTXE2_IMUX5_7", + "GTXE2_BYP6_10", + "GTXE2_CHANNEL_PCSRSVDIN6", + "GTXE2_IMUX23_6", + "GTXE2_CHANNEL_RXNOTINTABLE1", + "GTXE2_CHANNEL_DRPRDY", + "GTXE2_IMUX1_10", + "GTXE2_IMUX25_8", + "GTXE2_LOGIC_OUTS_B14_4", + "GTXE2_CHANNEL_TXSWING", + "GTXE2_IMUX28_8", + "GTXE2_IMUX28_7", + "GTXE2_CHANNEL_PCSRSVDOUT14", + "GTXE2_CHANNEL_TXCOMWAKE", + "GTXE2_IMUX3_3", + "GTXE2_IMUX10_6", + "GTXE2_CHANNEL_TXPHDLYPD", + "GTXE2_CHANNEL_TSTIN7", + "GTXE2_CHANNEL_RESETOVRD", + "GTXE2_IMUX10_0", + "GTXE2_IMUX3_1", + "GTXE2_LOGIC_OUTS_B19_7", + "GTXE2_CHANNEL_DRPDO6", + "GTXE2_CHANNEL_RXDFEVPOVRDEN", + "GTXE2_IMUX37_6", + "GTXE2_IMUX16_9", + "GTXE2_BYP3_6", + "GTXE2_BYP7_5", + "GTXE2_CHANNEL_RXPD0", + "GTXE2_LOGIC_OUTS_B12_5", + "GTXE2_LOGIC_OUTS_B3_3", + "GTXE2_IMUX12_10", + "GTXE2_CHANNEL_RXP_PAD", + "GTXE2_IMUX14_1", + "GTXE2_CHANNEL_TXDATA40", + "GTXE2_IMUX32_8", + "GTXE2_IMUX12_5", + "GTXE2_LOGIC_OUTS_B13_1", + "GTXE2_LOGIC_OUTS_B8_4", + "GTXE2_LOGIC_OUTS_B17_0", + "GTXE2_IMUX44_8", + "GTXE2_CTRL1_1", + "GTXE2_LOGIC_OUTS_B7_1", + "GTXE2_IMUX4_10", + "GTXE2_CHANNEL_DMONITOROUT6", + "GTXE2_CHANNEL_TXDATA3", + "GTXE2_CHANNEL_RXBUFSTATUS2", + "GTXE2_CHANNEL_RXDFEVPHOLD", + "GTXE2_LOGIC_OUTS_B5_4", + "GTXE2_IMUX14_10", + "GTXE2_IMUX27_2", + "GTXE2_IMUX13_8", + "GTXE2_LOGIC_OUTS_B16_6", + "GTXE2_IMUX15_5", + "GTXE2_LOGIC_OUTS_B2_10", + "GTXE2_IMUX41_2", + "GTXE2_CHANNEL_TXRUNDISP2", + "GTXE2_LOGIC_OUTS_B10_1", + "GTXE2_CHANNEL_SCANIN0", + "GTXE2_IMUX23_4", + "GTXE2_CLK1_5", + "GTXE2_IMUX6_9", + "GTXE2_IMUX21_3", + "GTXE2_IMUX11_4", + "GTXE2_IMUX25_9", + "GTXE2_CHANNEL_TXQPISTRONGPDOWN", + "GTXE2_BYP5_7", + "GTXE2_IMUX47_10", + "GTXE2_IMUX22_6", + "GTXE2_CHANNEL_SCANENB", + "GTXE2_CHANNEL_NORTHREFCLK0", + "GTXE2_CHANNEL_RXPHMONITOR0", + "GTXE2_LOGIC_OUTS_B15_1", + "GTXE2_CHANNEL_RXCHANREALIGN", + "GTXE2_CHANNEL_DMONITOROUT2", + "GTXE2_IMUX40_2", + "GTXE2_IMUX39_6", + "GTXE2_CHANNEL_RXCOMSASDET", + "GTXE2_CTRL1_10", + "GTXE2_CHANNEL_TXDATA59", + "GTXE2_IMUX21_6", + "GTXE2_IMUX22_9", + "GTXE2_LOGIC_OUTS_B11_10", + "GTXE2_IMUX1_0", + "GTXE2_LOGIC_OUTS_B0_5", + "GTXE2_FAN5_9", + "GTXE2_LOGIC_OUTS_B22_3", + "GTXE2_FAN5_5", + "GTXE2_FAN4_3", + "GTXE2_LOGIC_OUTS_B1_0", + "GTXE2_LOGIC_OUTS_B9_5", + "GTXE2_CHANNEL_RXCHBONDEN", + "GTXE2_LOGIC_OUTS_B6_6", + "GTXE2_CHANNEL_TXPRBSSEL0", + "GTXE2_BYP0_0", + "GTXE2_IMUX17_10", + "GTXE2_LOGIC_OUTS_B12_2", + "GTXE2_IMUX27_1", + "GTXE2_IMUX12_9", + "GTXE2_IMUX28_4", + "GTXE2_LOGIC_OUTS_B16_3", + "GTXE2_LOGIC_OUTS_B19_5", + "GTXE2_CHANNEL_TXHEADER1", + "GTXE2_IMUX11_7", + "GTXE2_LOGIC_OUTS_B15_4", + "GTXE2_IMUX19_4", + "GTXE2_IMUX32_2", + "GTXE2_LOGIC_OUTS_B12_1", + "GTXE2_CHANNEL_TXCHARDISPMODE2", + "GTXE2_IMUX30_3", + "GTXE2_CHANNEL_RXUSRCLK", + "GTXE2_CHANNEL_TSTCLK0", + "GTXE2_CHANNEL_DRPDI9", + "GTXE2_CHANNEL_TXDATA9", + "GTXE2_LOGIC_OUTS_B21_2", + "GTXE2_IMUX19_5", + "GTXE2_IMUX27_5", + "GTXE2_FAN0_8", + "GTXE2_CHANNEL_DRPDI13", + "GTXE2_FAN2_5", + "GTXE2_CHANNEL_RXDFEVSEN", + "GTXE2_IMUX37_7", + "GTXE2_LOGIC_OUTS_B23_2", + "GTXE2_IMUX2_2", + "GTXE2_CHANNEL_TX8B10BBYPASS6", + "GTXE2_CHANNEL_TXPOSTCURSOR1", + "GTXE2_CHANNEL_RXDATAVALID", + "GTXE2_CHANNEL_TXDATA31", + "GTXE2_CHANNEL_TXPHDLYTSTCLK", + "GTXE2_CHANNEL_TXCHARISK0", + "GTXE2_LOGIC_OUTS_B3_10", + "GTXE2_CHANNEL_PMARSVDIN3", + "GTXE2_IMUX34_5", + "GTXE2_CHANNEL_TXDATA6", + "GTXE2_CHANNEL_RXPRBSCNTRESET", + "GTXE2_IMUX3_7", + "GTXE2_CHANNEL_TXRUNDISP1", + "GTXE2_IMUX40_0", + "GTXE2_IMUX9_5", + "GTXE2_IMUX4_5", + "GTXE2_FAN6_9", + "GTXE2_CHANNEL_TSTIN0", + "GTXE2_FAN4_0", + "GTXE2_CHANNEL_TXDATA14", + "GTXE2_CHANNEL_TSTIN9", + "GTXE2_LOGIC_OUTS_B4_4", + "GTXE2_BYP0_3", + "GTXE2_FAN3_5", + "GTXE2_CHANNEL_TSTIN12", + "GTXE2_CHANNEL_TXCHARISK1", + "GTXE2_IMUX40_9", + "GTXE2_CHANNEL_TXDATA10", + "GTXE2_CHANNEL_RXNOTINTABLE6", + "GTXE2_IMUX39_3", + "GTXE2_LOGIC_OUTS_B4_7", + "GTXE2_IMUX43_7", + "GTXE2_CHANNEL_TXBUFDIFFCTRL2", + "GTXE2_IMUX5_4", + "GTXE2_CHANNEL_TXDATA30", + "GTXE2_IMUX39_1", + "GTXE2_CHANNEL_CPLLREFCLKLOST", + "GTXE2_CTRL0_9", + "GTXE2_LOGIC_OUTS_B21_7", + "GTXE2_CHANNEL_GTREFCLK1", + "GTXE2_BYP0_8", + "GTXE2_CHANNEL_DRPDI14", + "GTXE2_IMUX33_2", + "GTXE2_LOGIC_OUTS_B11_5", + "GTXE2_IMUX17_4", + "GTXE2_CHANNEL_TXDATA0", + "GTXE2_CHANNEL_EYESCANMODE", + "GTXE2_LOGIC_OUTS_B4_2", + "GTXE2_CHANNEL_SCANOUT3", + "GTXE2_IMUX13_2", + "GTXE2_IMUX19_9", + "GTXE2_LOGIC_OUTS_B9_1", + "GTXE2_CHANNEL_GTRSVD11", + "GTXE2_IMUX10_8", + "GTXE2_LOGIC_OUTS_B18_1", + "GTXE2_CHANNEL_RXDDIEN", + "GTXE2_IMUX5_1", + "GTXE2_IMUX35_5", + "GTXE2_IMUX32_6", + "GTXE2_IMUX40_8", + "GTXE2_CTRL1_2", + "GTXE2_LOGIC_OUTS_B6_2", + "GTXE2_LOGIC_OUTS_B16_8", + "GTXE2_IMUX40_10", + "GTXE2_CHANNEL_PMASCANCLK2", + "GTXE2_LOGIC_OUTS_B2_4", + "GTXE2_CHANNEL_PCSRSVDIN22", + "GTXE2_IMUX9_7", + "GTXE2_CHANNEL_DRPDI8", + "GTXE2_CHANNEL_TXPHINITDONE", + "GTXE2_FAN5_2", + "GTXE2_CHANNEL_LOOPBACK0", + "GTXE2_IMUX29_8", + "GTXE2_LOGIC_OUTS_B17_7", + "GTXE2_LOGIC_OUTS_B11_3", + "GTXE2_CHANNEL_CPLLLOCK", + "GTXE2_CHANNEL_RXDFETAP4OVRDEN", + "GTXE2_IMUX0_8", + "GTXE2_BYP4_4", + "GTXE2_LOGIC_OUTS_B10_9", + "GTXE2_CHANNEL_RXBUFRESET", + "GTXE2_IMUX12_2", + "GTXE2_CHANNEL_PCSRSVDOUT7", + "GTXE2_LOGIC_OUTS_B9_9", + "GTXE2_IMUX5_10", + "GTXE2_LOGIC_OUTS_B20_5", + "GTXE2_CHANNEL_PCSRSVDIN23", + "GTXE2_IMUX8_2", + "GTXE2_CHANNEL_TXDATA42", + "GTXE2_IMUX46_2", + "GTXE2_IMUX40_6", + "GTXE2_IMUX33_1", + "GTXE2_FAN6_0", + "GTXE2_LOGIC_OUTS_B11_7", + "GTXE2_BYP2_8", + "GTXE2_IMUX47_0", + "GTXE2_FAN0_3", + "GTXE2_CHANNEL_RXPHDLYRESET", + "GTXE2_LOGIC_OUTS_B11_6", + "GTXE2_LOGIC_OUTS_B8_3", + "GTXE2_IMUX36_4", + "GTXE2_CHANNEL_GTRESETSEL", + "GTXE2_CHANNEL_GTGREFCLK", + "GTXE2_LOGIC_OUTS_B11_0", + "GTXE2_LOGIC_OUTS_B5_9", + "GTXE2_IMUX34_2", + "GTXE2_IMUX8_3", + "GTXE2_LOGIC_OUTS_B14_1", + "GTXE2_LOGIC_OUTS_B18_6", + "GTXE2_CHANNEL_GTRSVD15", + "GTXE2_CHANNEL_RXDATA7", + "GTXE2_LOGIC_OUTS_B3_6", + "GTXE2_CHANNEL_RXCHARISK0", + "GTXE2_IMUX4_3", + "GTXE2_IMUX16_1", + "GTXE2_CHANNEL_RXDATA11", + "GTXE2_CHANNEL_TX8B10BBYPASS2", + "GTXE2_IMUX19_10", + "GTXE2_CHANNEL_TXDATA61", + "GTXE2_CHANNEL_RXDATA19", + "GTXE2_BYP5_10", + "GTXE2_IMUX20_1", + "GTXE2_IMUX16_6", + "GTXE2_IMUX26_7", + "GTXE2_CHANNEL_PMASCANOUT2", + "GTXE2_CHANNEL_TSTIN2", + "GTXE2_IMUX1_2", + "GTXE2_BYP4_3", + "GTXE2_LOGIC_OUTS_B18_7", + "GTXE2_CHANNEL_PCSRSVDIN21", + "GTXE2_CHANNEL_RXDISPERR3", + "GTXE2_IMUX40_5", + "GTXE2_FAN3_6", + "GTXE2_IMUX20_3", + "GTXE2_FAN7_2", + "GTXE2_CHANNEL_RXDLYTESTENB", + "GTXE2_FAN4_7", + "GTXE2_FAN2_0", + "GTXE2_IMUX32_9", + "GTXE2_IMUX30_9", + "GTXE2_IMUX32_4", + "GTXE2_CHANNEL_GTRSVD10", + "GTXE2_IMUX30_1", + "GTXE2_CHANNEL_DRPDO15", + "GTXE2_CHANNEL_TXDLYSRESETDONE", + "GTXE2_FAN2_3", + "GTXE2_IMUX30_5", + "GTXE2_LOGIC_OUTS_B6_4", + "GTXE2_CHANNEL_TXPOLARITY", + "GTXE2_CHANNEL_GTRSVD8", + "GTXE2_CHANNEL_TXDATA43", + "GTXE2_IMUX43_5", + "GTXE2_LOGIC_OUTS_B18_5", + "GTXE2_BYP3_0", + "GTXE2_BYP6_2", + "GTXE2_CHANNEL_TXDATA57", + "GTXE2_IMUX27_9", + "GTXE2_CHANNEL_DRPADDR0", + "GTXE2_CHANNEL_TXDATA15", + "GTXE2_IMUX10_1", + "GTXE2_CHANNEL_PCSRSVDOUT0", + "GTXE2_CHANNEL_PMARSVDIN1", + "GTXE2_IMUX4_1", + "GTXE2_IMUX39_2", + "GTXE2_CHANNEL_REFCLK1", + "GTXE2_IMUX9_8", + "GTXE2_LOGIC_OUTS_B21_1", + "GTXE2_IMUX4_0", + "GTXE2_BYP3_8", + "GTXE2_CHANNEL_DRPDO8", + "GTXE2_IMUX11_5", + "GTXE2_IMUX24_8", + "GTXE2_IMUX44_3", + "GTXE2_IMUX20_4", + "GTXE2_CHANNEL_RXDLYOVRDEN", + "GTXE2_CTRL1_5", + "GTXE2_CHANNEL_DRPWE", + "GTXE2_IMUX20_0", + "GTXE2_BYP3_10", + "GTXE2_LOGIC_OUTS_B5_1", + "GTXE2_CHANNEL_RXMONITORSEL0", + "GTXE2_CHANNEL_TXPRECURSOR0", + "GTXE2_CHANNEL_RXDATA10", + "GTXE2_CHANNEL_DMONITOROUT3", + "GTXE2_CHANNEL_TXDATA34", + "GTXE2_CHANNEL_TXDATA1", + "GTXE2_IMUX16_10", + "GTXE2_IMUX15_6", + "GTXE2_BYP0_10", + "GTXE2_CHANNEL_RXSTATUS0", + "GTXE2_FAN1_1", + "GTXE2_IMUX12_0", + "GTXE2_FAN0_2", + "GTXE2_LOGIC_OUTS_B0_6", + "GTXE2_IMUX37_8", + "GTXE2_CHANNEL_TXRUNDISP7", + "GTXE2_CHANNEL_DRPDI3", + "GTXE2_IMUX8_4", + "GTXE2_CHANNEL_RXDATA58", + "GTXE2_FAN3_1", + "GTXE2_CHANNEL_TXDATA41", + "GTXE2_BYP7_9", + "GTXE2_BYP4_1", + "GTXE2_LOGIC_OUTS_B18_2", + "GTXE2_CHANNEL_TXRATE1", + "GTXE2_CHANNEL_TXDLYOVRDEN", + "GTXE2_IMUX4_9", + "GTXE2_IMUX34_7", + "GTXE2_LOGIC_OUTS_B2_9", + "GTXE2_IMUX39_9", + "GTXE2_CHANNEL_RXDATA52", + "GTXE2_IMUX6_6", + "GTXE2_IMUX2_4", + "GTXE2_IMUX9_4", + "GTXE2_CHANNEL_PCSRSVDOUT12", + "GTXE2_IMUX3_4", + "GTXE2_CHANNEL_TSTPDOVRDB", + "GTXE2_CLK1_1", + "GTXE2_IMUX1_6", + "GTXE2_CHANNEL_TXDATA47", + "GTXE2_BYP4_2", + "GTXE2_CHANNEL_RXQPISENN", + "GTXE2_CHANNEL_RXPHMONITOR1", + "GTXE2_FAN6_2", + "GTXE2_CHANNEL_RXMONITOROUT4", + "GTXE2_CHANNEL_TXPRECURSOR3", + "GTXE2_CHANNEL_DRPDO7", + "GTXE2_LOGIC_OUTS_B6_0", + "GTXE2_IMUX17_5", + "GTXE2_LOGIC_OUTS_B10_2", + "GTXE2_CHANNEL_TXN_PAD", + "GTXE2_BYP3_3", + "GTXE2_IMUX2_3", + "GTXE2_CHANNEL_TXDATA62", + "GTXE2_FAN3_7", + "GTXE2_IMUX7_1", + "GTXE2_LOGIC_OUTS_B13_5", + "GTXE2_CHANNEL_RXRESETDONE", + "GTXE2_IMUX40_1", + "GTXE2_CHANNEL_TSTOUT6", + "GTXE2_IMUX36_10", + "GTXE2_CHANNEL_TXCOMINIT", + "GTXE2_LOGIC_OUTS_B0_9", + "GTXE2_IMUX4_8", + "GTXE2_IMUX29_4", + "GTXE2_IMUX45_9", + "GTXE2_FAN2_8", + "GTXE2_IMUX10_10", + "GTXE2_CHANNEL_RXDATA34", + "GTXE2_CHANNEL_PCSRSVDIN5", + "GTXE2_CHANNEL_GTRSVD9", + "GTXE2_IMUX6_1", + "GTXE2_IMUX43_2", + "GTXE2_LOGIC_OUTS_B0_10", + "GTXE2_IMUX30_6", + "GTXE2_LOGIC_OUTS_B14_5", + "GTXE2_IMUX42_7", + "GTXE2_IMUX21_8", + "GTXE2_IMUX35_7", + "GTXE2_CHANNEL_RXLPMHFOVRDEN", + "GTXE2_IMUX18_4", + "GTXE2_CHANNEL_RXPRBSSEL0", + "GTXE2_IMUX0_2", + "GTXE2_CHANNEL_PCSRSVDIN13", + "GTXE2_LOGIC_OUTS_B0_4", + "GTXE2_IMUX46_9", + "GTXE2_CHANNEL_PCSRSVDIN15", + "GTXE2_CHANNEL_TXP", + "GTXE2_CHANNEL_RXCHARISK5", + "GTXE2_CHANNEL_TXMAINCURSOR0", + "GTXE2_CHANNEL_TXDATA53", + "GTXE2_LOGIC_OUTS_B15_8", + "GTXE2_CHANNEL_DRPDO13", + "GTXE2_IMUX33_9", + "GTXE2_IMUX25_3", + "GTXE2_CHANNEL_TXMAINCURSOR3", + "GTXE2_CHANNEL_DRPDO4", + "GTXE2_IMUX42_4", + "GTXE2_IMUX31_5", + "GTXE2_CHANNEL_RXDATA32", + "GTXE2_LOGIC_OUTS_B20_6", + "GTXE2_LOGIC_OUTS_B13_9", + "GTXE2_CHANNEL_TXRATEDONE", + "GTXE2_CHANNEL_RXRATEDONE", + "GTXE2_FAN6_1", + "GTXE2_IMUX43_1", + "GTXE2_IMUX39_8", + "GTXE2_IMUX45_3", + "GTXE2_IMUX45_5", + "GTXE2_CTRL0_3", + "GTXE2_IMUX41_7", + "GTXE2_CHANNEL_RXCHBONDO3", + "GTXE2_CHANNEL_TXCHARDISPVAL3", + "GTXE2_CHANNEL_TXDATA45", + "GTXE2_CHANNEL_TXUSERRDY", + "GTXE2_FAN4_5", + "GTXE2_FAN5_1", + "GTXE2_LOGIC_OUTS_B8_7", + "GTXE2_CHANNEL_TSTPD4", + "GTXE2_CHANNEL_PMASCANCLK0", + "GTXE2_IMUX23_10", + "GTXE2_CHANNEL_TXBUFDIFFCTRL0", + "GTXE2_BYP0_9", + "GTXE2_FAN2_9", + "GTXE2_IMUX15_4", + "GTXE2_IMUX6_4", + "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", + "GTXE2_CHANNEL_TXDATA38", + "GTXE2_CHANNEL_RXDFEUTOVRDEN", + "GTXE2_FAN1_0", + "GTXE2_CHANNEL_RXDATA51", + "GTXE2_CLK0_9", + "GTXE2_CHANNEL_TXPD0", + "GTXE2_CHANNEL_GTRSVD4", + "GTXE2_IMUX2_10", + "GTXE2_IMUX47_6", + "GTXE2_CHANNEL_TXPD1", + "GTXE2_IMUX35_0", + "GTXE2_CHANNEL_TXDLYHOLD", + "GTXE2_CHANNEL_TXPMARESET", + "GTXE2_IMUX28_10", + "GTXE2_LOGIC_OUTS_B22_5", + "GTXE2_LOGIC_OUTS_B17_2", + "GTXE2_LOGIC_OUTS_B19_9", + "GTXE2_IMUX14_2", + "GTXE2_CHANNEL_TXDATA60", + "GTXE2_IMUX38_0", + "GTXE2_BYP6_9", + "GTXE2_CHANNEL_QPLLREFCLK", + "GTXE2_LOGIC_OUTS_B21_10", + "GTXE2_IMUX24_3", + "GTXE2_CHANNEL_DRPDI0", + "GTXE2_LOGIC_OUTS_B9_10", + "GTXE2_CHANNEL_TSTIN15", + "GTXE2_CHANNEL_RXPHSLIPMONITOR1", + "GTXE2_CHANNEL_RXDFETAP4HOLD", + "GTXE2_BYP3_7", + "GTXE2_CHANNEL_TXSEQUENCE3", + "GTXE2_BYP6_4", + "GTXE2_IMUX18_3", + "GTXE2_IMUX45_7", + "GTXE2_CHANNEL_TSTIN14", + "GTXE2_IMUX8_0", + "GTXE2_CHANNEL_RXHEADER1", + "GTXE2_CHANNEL_TXCHARISK5", + "GTXE2_IMUX37_1", + "GTXE2_CHANNEL_RXBYTEREALIGN", + "GTXE2_IMUX5_0", + "GTXE2_CHANNEL_DMONITOROUT0", + "GTXE2_CHANNEL_DRPEN", + "GTXE2_CHANNEL_TXUSRCLK", + "GTXE2_FAN3_4", + "GTXE2_IMUX19_8", + "GTXE2_CHANNEL_PCSRSVDIN10", + "GTXE2_IMUX1_9", + "GTXE2_LOGIC_OUTS_B17_8", + "GTXE2_CHANNEL_RXPHMONITOR4", + "GTXE2_FAN6_7", + "GTXE2_IMUX8_9", + "GTXE2_IMUX2_6", + "GTXE2_CHANNEL_PCSRSVDOUT6", + "GTXE2_IMUX7_9", + "GTXE2_IMUX19_1", + "GTXE2_CHANNEL_PCSRSVDIN4", + "GTXE2_IMUX21_7", + "GTXE2_LOGIC_OUTS_B18_8", + "GTXE2_IMUX7_5", + "GTXE2_IMUX41_1", + "GTXE2_CHANNEL_TXDATA5", + "GTXE2_IMUX9_9", + "GTXE2_CLK1_2", + "GTXE2_LOGIC_OUTS_B6_8", + "GTXE2_BYP6_7", + "GTXE2_CTRL1_8", + "GTXE2_IMUX17_7", + "GTXE2_IMUX46_7", + "GTXE2_CHANNEL_TSTIN3", + "GTXE2_CHANNEL_RXCHBONDLEVEL2", + "GTXE2_CTRL0_1", + "GTXE2_CHANNEL_TXMAINCURSOR4", + "GTXE2_CHANNEL_PCSRSVDIN2", + "GTXE2_IMUX26_4", + "GTXE2_CHANNEL_RXMONITOROUT1", + "GTXE2_CHANNEL_RXCHARISK3", + "GTXE2_IMUX15_8", + "GTXE2_CHANNEL_TSTIN13", + "GTXE2_CHANNEL_PCSRSVDIN1", + "GTXE2_CHANNEL_GTNORTHREFCLK1", + "GTXE2_BYP0_6", + "GTXE2_CHANNEL_RXDATA36", + "GTXE2_CHANNEL_RXQPISENP", + "GTXE2_CHANNEL_RXDATA31", + "GTXE2_LOGIC_OUTS_B0_8", + "GTXE2_LOGIC_OUTS_B0_7", + "GTXE2_IMUX24_6", + "GTXE2_LOGIC_OUTS_B22_9", + "GTXE2_CHANNEL_RXDATA46", + "GTXE2_IMUX33_6", + "GTXE2_LOGIC_OUTS_B21_0", + "GTXE2_IMUX19_0", + "GTXE2_CLK1_3", + "GTXE2_LOGIC_OUTS_B14_2", + "GTXE2_IMUX37_4", + "GTXE2_BYP5_1", + "GTXE2_IMUX6_8", + "GTXE2_IMUX16_2", + "GTXE2_CHANNEL_RXDATA2", + "GTXE2_IMUX31_2", + "GTXE2_FAN4_2", + "GTXE2_LOGIC_OUTS_B18_0", + "GTXE2_CHANNEL_SCANIN4", + "GTXE2_LOGIC_OUTS_B15_10", + "GTXE2_LOGIC_OUTS_B13_3", + "GTXE2_LOGIC_OUTS_B5_7", + "GTXE2_LOGIC_OUTS_B6_9", + "GTXE2_CHANNEL_TXCHARDISPMODE1", + "GTXE2_CHANNEL_RXPCD1DONE", + "GTXE2_IMUX21_2", + "GTXE2_LOGIC_OUTS_B23_3", + "GTXE2_IMUX39_10", + "GTXE2_CHANNEL_TXQPIBIASEN", + "GTXE2_LOGIC_OUTS_B9_2", + "GTXE2_LOGIC_OUTS_B0_2", + "GTXE2_CHANNEL_RXUSERRDY", + "GTXE2_CHANNEL_DRPDO3", + "GTXE2_CHANNEL_EYESCANRESET", + "GTXE2_BYP7_1", + "GTXE2_LOGIC_OUTS_B12_6", + "GTXE2_CLK0_7", + "GTXE2_FAN0_7", + "GTXE2_CHANNEL_RXPHALIGNEN", + "GTXE2_IMUX24_5", + "GTXE2_CHANNEL_TXMARGIN1", + "GTXE2_CHANNEL_TXCHARDISPVAL0", + "GTXE2_IMUX8_5", + "GTXE2_IMUX14_8", + "GTXE2_CHANNEL_RXDATA0", + "GTXE2_FAN1_7", + "GTXE2_CHANNEL_RXPOLARITY", + "GTXE2_IMUX0_1", + "GTXE2_IMUX16_7", + "GTXE2_CHANNEL_TXSEQUENCE2", + "GTXE2_IMUX47_7", + "GTXE2_CHANNEL_RXPCOMMAALIGNEN", + "GTXE2_IMUX42_1", + "GTXE2_LOGIC_OUTS_B18_10", + "GTXE2_CHANNEL_GTRSVD1", + "GTXE2_LOGIC_OUTS_B7_0", + "GTXE2_CLK0_4", + "GTXE2_CHANNEL_TX8B10BBYPASS0", + "GTXE2_LOGIC_OUTS_B18_4", + "GTXE2_LOGIC_OUTS_B23_4", + "GTXE2_CHANNEL_PCSRSVDIN8", + "GTXE2_IMUX0_9", + "GTXE2_LOGIC_OUTS_B1_8", + "GTXE2_BYP1_8", + "GTXE2_LOGIC_OUTS_B7_5", + "GTXE2_CHANNEL_TXPCSRESET", + "GTXE2_CHANNEL_TXOUTCLKSEL2", + "GTXE2_CHANNEL_TXCHARDISPVAL7", + "GTXE2_CHANNEL_RXDATA3", + "GTXE2_IMUX47_5", + "GTXE2_CHANNEL_TXMAINCURSOR6", + "GTXE2_CHANNEL_RXPHSLIPMONITOR3", + "GTXE2_LOGIC_OUTS_B9_4", + "GTXE2_IMUX7_3", + "GTXE2_CHANNEL_PMASCANIN1", + "GTXE2_IMUX36_9", + "GTXE2_CHANNEL_TSTOUT2", + "GTXE2_IMUX27_3", + "GTXE2_LOGIC_OUTS_B19_4", + "GTXE2_IMUX27_0", + "GTXE2_CHANNEL_RXCLKCORCNT1", + "GTXE2_CHANNEL_TXDATA46", + "GTXE2_CHANNEL_RXDFEXYDHOLD", + "GTXE2_LOGIC_OUTS_B22_0", + "GTXE2_BYP2_5", + "GTXE2_CHANNEL_EDTBYPASS", + "GTXE2_CHANNEL_RXDATA40", + "GTXE2_IMUX42_6", + "GTXE2_CHANNEL_TXCHARDISPVAL6", + "GTXE2_LOGIC_OUTS_B16_9", + "GTXE2_LOGIC_OUTS_B11_8", + "GTXE2_LOGIC_OUTS_B14_0", + "GTXE2_CTRL1_3", + "GTXE2_CHANNEL_RXDATA23", + "GTXE2_IMUX32_7", + "GTXE2_CHANNEL_PMASCANIN4", + "GTXE2_IMUX31_8", + "GTXE2_LOGIC_OUTS_B4_6", + "GTXE2_CHANNEL_RXN_PAD", + "GTXE2_BYP2_9", + "GTXE2_IMUX18_5", + "GTXE2_CHANNEL_TXELECIDLE", + "GTXE2_LOGIC_OUTS_B13_8", + "GTXE2_IMUX46_6", + "GTXE2_CHANNEL_RXCHANISALIGNED", + "GTXE2_IMUX32_5", + "GTXE2_IMUX38_6", + "GTXE2_IMUX30_4", + "GTXE2_LOGIC_OUTS_B17_5", + "GTXE2_CLK0_3", + "GTXE2_IMUX25_2", + "GTXE2_IMUX9_3", + "GTXE2_IMUX32_1", + "GTXE2_CHANNEL_TXDIFFCTRL3", + "GTXE2_IMUX31_0", + "GTXE2_CHANNEL_RXDISPERR4", + "GTXE2_IMUX17_9", + "GTXE2_CHANNEL_SCANOUT2", + "GTXE2_FAN0_9", + "GTXE2_CHANNEL_TXPOSTCURSOR3", + "GTXE2_CHANNEL_TXOUTCLKSEL1", + "GTXE2_LOGIC_OUTS_B1_10", + "GTXE2_IMUX28_1", + "GTXE2_CHANNEL_RXPCSRESET", + "GTXE2_CHANNEL_TXHEADER2", + "GTXE2_IMUX7_10", + "GTXE2_CHANNEL_TXPOSTCURSOR2", + "GTXE2_IMUX20_6", + "GTXE2_BYP7_8", + "GTXE2_FAN5_0", + "GTXE2_CHANNEL_SCANIN1", + "GTXE2_CHANNEL_PMASCANMODEB", + "GTXE2_IMUX40_4", + "GTXE2_LOGIC_OUTS_B10_5", + "GTXE2_CHANNEL_TXPISOPD", + "GTXE2_LOGIC_OUTS_B23_1", + "GTXE2_CHANNEL_QPLLCLK", + "GTXE2_IMUX8_10", + "GTXE2_CHANNEL_RXDLYSRESET", + "GTXE2_IMUX16_5", + "GTXE2_IMUX9_6", + "GTXE2_CHANNEL_TXN", + "GTXE2_LOGIC_OUTS_B1_5", + "GTXE2_BYP2_4", + "GTXE2_CHANNEL_PCSRSVDOUT3", + "GTXE2_BYP4_5", + "GTXE2_CLK1_0", + "GTXE2_IMUX44_6", + "GTXE2_IMUX43_8", + "GTXE2_IMUX14_0", + "GTXE2_BYP7_0", + "GTXE2_CHANNEL_REFCLK0", + "GTXE2_CHANNEL_RXPMARESET", + "GTXE2_CHANNEL_RXCHANBONDSEQ", + "GTXE2_CHANNEL_TXCOMFINISH", + "GTXE2_IMUX7_6", + "GTXE2_CHANNEL_TXBUFDIFFCTRL1", + "GTXE2_IMUX17_0", + "GTXE2_CHANNEL_EYESCANDATAERROR", + "GTXE2_IMUX11_1", + "GTXE2_CHANNEL_TXDATA11", + "GTXE2_LOGIC_OUTS_B1_3", + "GTXE2_CHANNEL_RXCHBONDI0", + "GTXE2_CHANNEL_RXCHBONDLEVEL0", + "GTXE2_CHANNEL_RXDATA1", + "GTXE2_LOGIC_OUTS_B4_10", + "GTXE2_IMUX34_3", + "GTXE2_IMUX14_9", + "GTXE2_CHANNEL_RXCHARISCOMMA0", + "GTXE2_FAN4_6", + "GTXE2_IMUX14_4", + "GTXE2_CHANNEL_TSTOUT5", + "GTXE2_LOGIC_OUTS_B15_7", + "GTXE2_CHANNEL_PCSRSVDOUT9", + "GTXE2_IMUX13_7", + "GTXE2_FAN4_4", + "GTXE2_LOGIC_OUTS_B2_8", + "GTXE2_CHANNEL_TXPHALIGNEN", + "GTXE2_IMUX37_0", + "GTXE2_CHANNEL_TXOUTCLK_3", + "GTXE2_CHANNEL_GTRSVD6", + "GTXE2_CHANNEL_RXMONITORSEL1", + "GTXE2_CHANNEL_TXCHARDISPVAL4", + "GTXE2_CHANNEL_RXDATA16", + "GTXE2_IMUX40_7", + "GTXE2_CHANNEL_PCSRSVDIN12", + "GTXE2_IMUX38_9", + "GTXE2_CHANNEL_PMARSVDIN4", + "GTXE2_IMUX28_0", + "GTXE2_BYP4_8", + "GTXE2_CHANNEL_TXBUFSTATUS0", + "GTXE2_CHANNEL_RXCHBONDLEVEL1", + "GTXE2_IMUX19_2", + "GTXE2_LOGIC_OUTS_B7_8", + "GTXE2_CHANNEL_TXMARGIN2", + "GTXE2_IMUX41_6", + "GTXE2_CHANNEL_DRPDO5", + "GTXE2_CHANNEL_RXDATA55", + "GTXE2_IMUX23_8", + "GTXE2_BYP1_5", + "GTXE2_CHANNEL_RXSYSCLKSEL1", + "GTXE2_LOGIC_OUTS_B16_7", + "GTXE2_CHANNEL_RXCHBONDI2", + "GTXE2_CHANNEL_TXSEQUENCE1", + "GTXE2_CHANNEL_SOUTHREFCLK0", + "GTXE2_IMUX16_3", + "GTXE2_IMUX28_6", + "GTXE2_IMUX35_4", + "GTXE2_LOGIC_OUTS_B16_1", + "GTXE2_CHANNEL_RXDATA57", + "GTXE2_CHANNEL_TXDATA18", + "GTXE2_LOGIC_OUTS_B14_3", + "GTXE2_IMUX27_7", + "GTXE2_CHANNEL_DMONITOROUT1", + "GTXE2_IMUX39_7", + "GTXE2_LOGIC_OUTS_B17_1", + "GTXE2_IMUX27_10", + "GTXE2_CHANNEL_RXCHARISCOMMA1", + "GTXE2_CHANNEL_RXLPMHFHOLD", + "GTXE2_IMUX27_6", + "GTXE2_IMUX6_5", + "GTXE2_BYP5_2", + "GTXE2_CHANNEL_SETERRSTATUS", + "GTXE2_CHANNEL_TXCHARDISPVAL1", + "GTXE2_LOGIC_OUTS_B12_9", + "GTXE2_CHANNEL_PCSRSVDIN9", + "GTXE2_IMUX46_4", + "GTXE2_CHANNEL_PMASCANIN3", + "GTXE2_IMUX20_8", + "GTXE2_CHANNEL_CPLLLOCKEN", + "GTXE2_CHANNEL_DRPADDR6", + "GTXE2_IMUX45_4", + "GTXE2_LOGIC_OUTS_B1_1", + "GTXE2_IMUX42_3", + "GTXE2_BYP1_3", + "GTXE2_CTRL1_0", + "GTXE2_CHANNEL_TXRUNDISP0", + "GTXE2_IMUX42_9", + "GTXE2_CHANNEL_RXDFETAP5OVRDEN", + "GTXE2_IMUX47_2", + "GTXE2_IMUX0_3", + "GTXE2_CTRL0_5", + "GTXE2_CHANNEL_PCSRSVDIN20", + "GTXE2_BYP3_9", + "GTXE2_CHANNEL_TSTCLK1", + "GTXE2_BYP2_1", + "GTXE2_CHANNEL_RXCHARISK1", + "GTXE2_IMUX33_7", + "GTXE2_IMUX12_8", + "GTXE2_IMUX35_2", + "GTXE2_IMUX10_5", + "GTXE2_IMUX34_8", + "GTXE2_CHANNEL_TSTPD1", + "GTXE2_IMUX2_9", + "GTXE2_CHANNEL_TXDATA2", + "GTXE2_CHANNEL_GTRXOUTCLK_3", + "GTXE2_IMUX21_1", + "GTXE2_LOGIC_OUTS_B22_7", + "GTXE2_CHANNEL_TXOUTCLK_1", + "GTXE2_FAN1_10", + "GTXE2_IMUX32_3", + "GTXE2_LOGIC_OUTS_B13_10", + "GTXE2_LOGIC_OUTS_B7_6", + "GTXE2_FAN7_3", + "GTXE2_CHANNEL_TXOUTCLKPCS", + "GTXE2_IMUX4_6", + "GTXE2_CHANNEL_TSTOUT3", + "GTXE2_CHANNEL_RXNOTINTABLE7", + "GTXE2_LOGIC_OUTS_B12_8", + "GTXE2_CHANNEL_RXDATA61", + "GTXE2_CHANNEL_RXDATA56", + "GTXE2_FAN3_2", + "GTXE2_LOGIC_OUTS_B8_5", + "GTXE2_CLK0_5", + "GTXE2_FAN2_10", + "GTXE2_IMUX41_8", + "GTXE2_BYP5_9", + "GTXE2_CHANNEL_DRPDI5", + "GTXE2_CHANNEL_TXSEQUENCE0", + "GTXE2_IMUX26_10", + "GTXE2_CHANNEL_RXSTARTOFSEQ", + "GTXE2_BYP1_0", + "GTXE2_IMUX47_1", + "GTXE2_CHANNEL_PMARSVDIN21", + "GTXE2_IMUX18_10", + "GTXE2_CHANNEL_TXPOSTCURSOR4", + "GTXE2_LOGIC_OUTS_B15_3", + "GTXE2_CHANNEL_RXCOMMADETEN", + "GTXE2_FAN0_1", + "GTXE2_CHANNEL_GTRSVD7", + "GTXE2_CLK1_8", + "GTXE2_CHANNEL_TXDIFFCTRL0", + "GTXE2_IMUX22_2", + "GTXE2_LOGIC_OUTS_B4_5", + "GTXE2_CHANNEL_TXBUFSTATUS1", + "GTXE2_IMUX6_10", + "GTXE2_CHANNEL_SCANIN3", + "GTXE2_FAN0_0", + "GTXE2_LOGIC_OUTS_B22_6", + "GTXE2_LOGIC_OUTS_B13_4", + "GTXE2_CHANNEL_RXDATA12", + "GTXE2_LOGIC_OUTS_B7_3", + "GTXE2_IMUX41_5", + "GTXE2_CHANNEL_RXOUTCLK_0", + "GTXE2_IMUX20_9", + "GTXE2_IMUX27_8", + "GTXE2_CHANNEL_RXDFELFHOLD", + "GTXE2_CHANNEL_PCSRSVDIN14", + "GTXE2_FAN1_6", + "GTXE2_IMUX34_4", + "GTXE2_CHANNEL_RXDISPERR2", + "GTXE2_CHANNEL_TXRUNDISP3", + "GTXE2_CHANNEL_CPLLRESET", + "GTXE2_BYP5_6", + "GTXE2_LOGIC_OUTS_B6_1", + "GTXE2_IMUX12_4", + "GTXE2_FAN2_2", + "GTXE2_CHANNEL_RXDATA47", + "GTXE2_CHANNEL_DRPDO9", + "GTXE2_LOGIC_OUTS_B14_6", + "GTXE2_CHANNEL_DRPDO1", + "GTXE2_CHANNEL_TXPRBSFORCEERR", + "GTXE2_LOGIC_OUTS_B16_4", + "GTXE2_IMUX16_8", + "GTXE2_LOGIC_OUTS_B14_7", + "GTXE2_LOGIC_OUTS_B23_8", + "GTXE2_FAN6_4", + "GTXE2_LOGIC_OUTS_B0_3", + "GTXE2_IMUX29_5", + "GTXE2_CHANNEL_RXCDRLOCK", + "GTXE2_CHANNEL_GTNORTHREFCLK0", + "GTXE2_IMUX31_1", + "GTXE2_IMUX20_5", + "GTXE2_CHANNEL_LOOPBACK2", + "GTXE2_CHANNEL_RXPRBSERR", + "GTXE2_IMUX7_0", + "GTXE2_BYP0_2", + "GTXE2_CHANNEL_RXGEARBOXSLIP", + "GTXE2_LOGIC_OUTS_B8_9", + "GTXE2_CHANNEL_PMASCANOUT3", + "GTXE2_CHANNEL_TSTIN1", + "GTXE2_LOGIC_OUTS_B21_9", + "GTXE2_FAN4_1", + "GTXE2_LOGIC_OUTS_B6_10", + "GTXE2_IMUX35_6", + "GTXE2_IMUX24_9", + "GTXE2_CHANNEL_TSTIN18", + "GTXE2_CHANNEL_RXDISPERR5", + "GTXE2_FAN6_10", + "GTXE2_IMUX32_0", + "GTXE2_CHANNEL_CLKRSVD1", + "GTXE2_CTRL1_6", + "GTXE2_CHANNEL_TSTOUT7", + "GTXE2_LOGIC_OUTS_B9_8", + "GTXE2_IMUX38_7", + "GTXE2_IMUX5_2", + "GTXE2_CLK0_2", + "GTXE2_CHANNEL_DRPDI11", + "GTXE2_CHANNEL_RXPHALIGN", + "GTXE2_LOGIC_OUTS_B0_0", + "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", + "GTXE2_CHANNEL_TXDATA58", + "GTXE2_LOGIC_OUTS_B3_4", + "GTXE2_CHANNEL_RXUSRCLK2", + "GTXE2_CHANNEL_TXDATA50", + "GTXE2_CHANNEL_RXDATA24", + "GTXE2_CHANNEL_PCSRSVDIN0", + "GTXE2_CHANNEL_RXCHBONDO0", + "GTXE2_LOGIC_OUTS_B22_4", + "GTXE2_IMUX13_1", + "GTXE2_CHANNEL_TXCHARDISPMODE3", + "GTXE2_CHANNEL_RXRATE0", + "GTXE2_CHANNEL_RXDATA27", + "GTXE2_IMUX28_2", + "GTXE2_IMUX14_7", + "GTXE2_LOGIC_OUTS_B20_2", + "GTXE2_IMUX44_5", + "GTXE2_BYP4_9", + "GTXE2_IMUX36_1", + "GTXE2_BYP2_7", + "GTXE2_CHANNEL_TXDATA12", + "GTXE2_CHANNEL_EDTUPDATE", + "GTXE2_IMUX26_3", + "GTXE2_CHANNEL_RXDISPERR6", + "GTXE2_FAN3_3", + "GTXE2_CHANNEL_TXPHALIGN", + "GTXE2_CHANNEL_TXDIFFCTRL1", + "GTXE2_LOGIC_OUTS_B4_0", + "GTXE2_IMUX9_10", + "GTXE2_CHANNEL_TXDATA26", + "GTXE2_CHANNEL_TXP_PAD", + "GTXE2_CHANNEL_RXOUTCLK_1", + "GTXE2_IMUX12_7", + "GTXE2_IMUX33_5", + "GTXE2_IMUX47_3", + "GTXE2_LOGIC_OUTS_B14_8", + "GTXE2_CHANNEL_RXDEBUGPULSE", + "GTXE2_CHANNEL_RXDATA4", + "GTXE2_LOGIC_OUTS_B12_7", + "GTXE2_IMUX20_2", + "GTXE2_CHANNEL_RXNOTINTABLE4", + "GTXE2_CHANNEL_RXDFEUTHOLD", + "GTXE2_CHANNEL_GTREFCLK0", + "GTXE2_IMUX37_9", + "GTXE2_CHANNEL_RXBUFSTATUS1", + "GTXE2_IMUX4_7", + "GTXE2_BYP1_9", + "GTXE2_CHANNEL_DRPDO12", + "GTXE2_IMUX31_6", + "GTXE2_CHANNEL_RXMONITOROUT5", + "GTXE2_FAN5_6", + "GTXE2_CHANNEL_TXDATA7", + "GTXE2_CHANNEL_TSTOUT9", + "GTXE2_CHANNEL_RXNOTINTABLE3", + "GTXE2_CHANNEL_EYESCANTRIGGER", + "GTXE2_IMUX10_7", + "GTXE2_CHANNEL_GTSOUTHREFCLK0", + "GTXE2_LOGIC_OUTS_B19_8", + "GTXE2_LOGIC_OUTS_B7_10", + "GTXE2_CHANNEL_RXCDRRESETRSV", + "GTXE2_CHANNEL_RXSLIDE", + "GTXE2_CHANNEL_TXPRBSSEL2", + "GTXE2_IMUX43_10", + "GTXE2_CHANNEL_RXCHBONDI1", + "GTXE2_BYP3_1", + "GTXE2_CHANNEL_RXP", + "GTXE2_IMUX13_6", + "GTXE2_LOGIC_OUTS_B5_2", + "GTXE2_LOGIC_OUTS_B9_6", + "GTXE2_IMUX35_8", + "GTXE2_CHANNEL_TXRATE2", + "GTXE2_CHANNEL_CPLLLOCKDETCLK", + "GTXE2_IMUX36_5", + "GTXE2_CHANNEL_RXLPMEN", + "GTXE2_CHANNEL_RXCDROVRDEN", + "GTXE2_BYP6_3", + "GTXE2_BYP3_4", + "GTXE2_LOGIC_OUTS_B21_6", + "GTXE2_LOGIC_OUTS_B12_10", + "GTXE2_IMUX43_3", + "GTXE2_FAN4_10", + "GTXE2_IMUX24_2", + "GTXE2_IMUX46_10", + "GTXE2_LOGIC_OUTS_B5_5", + "GTXE2_CHANNEL_TXOUTCLKFABRIC", + "GTXE2_CHANNEL_TSTIN10", + "GTXE2_IMUX36_6", + "GTXE2_BYP4_10", + "GTXE2_CHANNEL_RXDFEXYDOVRDEN", + "GTXE2_IMUX34_0", + "GTXE2_CLK0_1", + "GTXE2_IMUX11_10", + "GTXE2_LOGIC_OUTS_B10_4", + "GTXE2_LOGIC_OUTS_B20_1", + "GTXE2_CHANNEL_TXMAINCURSOR2", + "GTXE2_CHANNEL_RXPD1", + "GTXE2_IMUX32_10", + "GTXE2_LOGIC_OUTS_B7_2", + "GTXE2_LOGIC_OUTS_B0_1", + "GTXE2_CHANNEL_RXDATA18", + "GTXE2_IMUX21_9", + "GTXE2_IMUX3_0", + "GTXE2_CTRL0_6", + "GTXE2_CHANNEL_RXCDRFREQRESET", + "GTXE2_IMUX45_2", + "GTXE2_LOGIC_OUTS_B13_2", + "GTXE2_CHANNEL_RXDISPERR1", + "GTXE2_CTRL0_0", + "GTXE2_FAN6_8", + "GTXE2_IMUX30_0", + "GTXE2_IMUX43_6", + "GTXE2_BYP1_6", + "GTXE2_IMUX28_3", + "GTXE2_IMUX18_0", + "GTXE2_LOGIC_OUTS_B10_7", + "GTXE2_CHANNEL_PCSRSVDOUT8", + "GTXE2_FAN6_5", + "GTXE2_CLK0_0", + "GTXE2_LOGIC_OUTS_B9_3", + "GTXE2_CHANNEL_TXDATA55", + "GTXE2_LOGIC_OUTS_B20_3", + "GTXE2_CHANNEL_PMASCANIN0", + "GTXE2_IMUX29_10", + "GTXE2_CHANNEL_DRPDI2", + "GTXE2_LOGIC_OUTS_B20_4", + "GTXE2_CHANNEL_RXDFECM1EN", + "GTXE2_CHANNEL_RXCHARISCOMMA3", + "GTXE2_CHANNEL_RXCHARISCOMMA5", + "GTXE2_CHANNEL_PMASCANENB", + "GTXE2_IMUX11_6", + "GTXE2_BYP3_2", + "GTXE2_CHANNEL_RXCHARISCOMMA7", + "GTXE2_CHANNEL_TXPHINIT", + "GTXE2_IMUX25_1", + "GTXE2_BYP7_4", + "GTXE2_CHANNEL_RXOUTCLKSEL0", + "GTXE2_IMUX1_1", + "GTXE2_CHANNEL_TXDATA51", + "GTXE2_IMUX35_3", + "GTXE2_LOGIC_OUTS_B22_10", + "GTXE2_FAN5_7", + "GTXE2_CHANNEL_RXDFETAP3OVRDEN", + "GTXE2_CHANNEL_PMARSVDIN20", + "GTXE2_CHANNEL_RXPHMONITOR2", + "GTXE2_CHANNEL_RXDATA25", + "GTXE2_CHANNEL_RXDATA9", + "GTXE2_CHANNEL_TSTOUT0", + "GTXE2_CHANNEL_TXPRECURSOR4", + "GTXE2_IMUX5_5", + "GTXE2_IMUX22_5", + "GTXE2_IMUX30_10", + "GTXE2_LOGIC_OUTS_B19_3", + "GTXE2_FAN1_3", + "GTXE2_CHANNEL_RXCDRHOLD", + "GTXE2_LOGIC_OUTS_B10_6", + "GTXE2_LOGIC_OUTS_B16_5", + "GTXE2_FAN1_2", + "GTXE2_IMUX45_1", + "GTXE2_IMUX19_7", + "GTXE2_CHANNEL_RXDATA43", + "GTXE2_CHANNEL_TXUSRCLK2", + "GTXE2_IMUX26_6", + "GTXE2_IMUX3_6", + "GTXE2_CHANNEL_TXCHARISK4", + "GTXE2_LOGIC_OUTS_B11_2", + "GTXE2_CHANNEL_TSTPD3", + "GTXE2_IMUX38_3", + "GTXE2_LOGIC_OUTS_B12_3", + "GTXE2_IMUX45_10", + "GTXE2_FAN7_5", + "GTXE2_IMUX38_5", + "GTXE2_BYP5_4", + "GTXE2_CHANNEL_PCSRSVDIN3", + "GTXE2_LOGIC_OUTS_B4_9", + "GTXE2_LOGIC_OUTS_B2_5", + "GTXE2_IMUX26_2", + "GTXE2_CHANNEL_SCANOUT4", + "GTXE2_CHANNEL_CFGRESET", + "GTXE2_IMUX33_3", + "GTXE2_CHANNEL_RXDATA20", + "GTXE2_IMUX38_10", + "GTXE2_CHANNEL_TSTOUT1", + "GTXE2_IMUX1_8", + "GTXE2_CHANNEL_TXDATA20", + "GTXE2_CHANNEL_TSTPD0", + "GTXE2_CHANNEL_TXDATA37", + "GTXE2_IMUX23_1", + "GTXE2_IMUX36_0", + "GTXE2_LOGIC_OUTS_B16_10", + "GTXE2_IMUX4_2", + "GTXE2_IMUX18_1", + "GTXE2_LOGIC_OUTS_B12_0", + "GTXE2_CHANNEL_RXDATA30", + "GTXE2_IMUX44_10", + "GTXE2_IMUX25_6", + "GTXE2_CHANNEL_PMASCANOUT4", + "GTXE2_LOGIC_OUTS_B17_10", + "GTXE2_CHANNEL_TXINHIBIT", + "GTXE2_IMUX3_5", + "GTXE2_CHANNEL_TXDATA39", + "GTXE2_IMUX15_10", + "GTXE2_CHANNEL_TXPDELECIDLEMODE", + "GTXE2_IMUX26_8", + "GTXE2_CHANNEL_GTTXRESET", + "GTXE2_CHANNEL_TXCHARISK2", + "GTXE2_IMUX6_3", + "GTXE2_CHANNEL_RXPRBSSEL1", + "GTXE2_CHANNEL_RXPHSLIPMONITOR0", + "GTXE2_CLK0_10", + "GTXE2_CHANNEL_RXDFELPMRESET", + "GTXE2_IMUX42_10", + "GTXE2_IMUX2_1", + "GTXE2_LOGIC_OUTS_B16_2", + "GTXE2_CHANNEL_TXCOMSAS", + "GTXE2_IMUX6_7", + "GTXE2_IMUX29_6", + "GTXE2_IMUX31_4", + "GTXE2_CHANNEL_RXLPMLFHOLD", + "GTXE2_CHANNEL_PCSRSVDOUT4", + "GTXE2_CHANNEL_RXDATA59", + "GTXE2_CHANNEL_DRPADDR1", + "GTXE2_LOGIC_OUTS_B20_7", + "GTXE2_FAN2_1", + "GTXE2_FAN7_7", + "GTXE2_IMUX12_6", + "GTXE2_CHANNEL_TXDATA21", + "GTXE2_IMUX29_2", + "GTXE2_CHANNEL_RXDATA45", + "GTXE2_CHANNEL_TX8B10BBYPASS1", + "GTXE2_CHANNEL_SCANMODEB", + "GTXE2_IMUX36_7", + "GTXE2_IMUX17_3", + "GTXE2_CHANNEL_TXHEADER0", + "GTXE2_LOGIC_OUTS_B13_7", + "GTXE2_IMUX29_0", + "GTXE2_LOGIC_OUTS_B3_5", + "GTXE2_CHANNEL_TXCHARDISPMODE7", + "GTXE2_CHANNEL_GTRSVD12", + "GTXE2_LOGIC_OUTS_B1_7", + "GTXE2_CHANNEL_SCANOUT0", + "GTXE2_IMUX24_7", + "GTXE2_IMUX15_7", + "GTXE2_CHANNEL_RXDFEXYDEN", + "GTXE2_IMUX1_7", + "GTXE2_IMUX23_3", + "GTXE2_CHANNEL_TX8B10BBYPASS3", + "GTXE2_IMUX34_1", + "GTXE2_CHANNEL_RXCHARISCOMMA6", + "GTXE2_CHANNEL_TXOUTCLK_2", + "GTXE2_CHANNEL_TXDATA56", + "GTXE2_LOGIC_OUTS_B5_10", + "GTXE2_IMUX25_0", + "GTXE2_CHANNEL_PCSRSVDIN11", + "GTXE2_CHANNEL_TXRESETDONE", + "GTXE2_CHANNEL_TSTOUT4", + "GTXE2_IMUX43_9", + "GTXE2_CHANNEL_TSTOUT8", + "GTXE2_LOGIC_OUTS_B1_2", + "GTXE2_BYP7_6", + "GTXE2_FAN2_4", + "GTXE2_IMUX18_8", + "GTXE2_IMUX39_0", + "GTXE2_CHANNEL_RXDFETAP2HOLD", + "GTXE2_BYP6_6", + "GTXE2_CHANNEL_TXPHALIGNDONE", + "GTXE2_LOGIC_OUTS_B2_6", + "GTXE2_IMUX37_5", + "GTXE2_LOGIC_OUTS_B8_1", + "GTXE2_CHANNEL_TXDATA35", + "GTXE2_CHANNEL_TXPRECURSORINV", + "GTXE2_IMUX10_9", + "GTXE2_IMUX38_1", + "GTXE2_IMUX14_6", + "GTXE2_CHANNEL_PMARSVDIN2", + "GTXE2_IMUX18_6", + "GTXE2_FAN0_5", + "GTXE2_CHANNEL_RXCHBONDSLAVE", + "GTXE2_CHANNEL_DRPADDR2", + "GTXE2_CHANNEL_RXDATA29", + "GTXE2_CHANNEL_RXMONITOROUT6", + "GTXE2_CHANNEL_TXDATA54", + "GTXE2_BYP4_0", + "GTXE2_CHANNEL_PCSRSVDOUT10", + "GTXE2_LOGIC_OUTS_B14_10", + "GTXE2_CHANNEL_RXCHBONDI4", + "GTXE2_IMUX44_1", + "GTXE2_CHANNEL_TXDLYEN", + "GTXE2_LOGIC_OUTS_B17_4", + "GTXE2_LOGIC_OUTS_B10_0", + "GTXE2_FAN0_10", + "GTXE2_IMUX39_4", + "GTXE2_CHANNEL_TXMAINCURSOR5", + "GTXE2_IMUX7_7", + "GTXE2_CHANNEL_RXNOTINTABLE2", + "GTXE2_CHANNEL_DRPDI12", + "GTXE2_IMUX14_5", + "GTXE2_LOGIC_OUTS_B5_6", + "GTXE2_FAN2_7", + "GTXE2_CHANNEL_DRPDI7", + "GTXE2_CHANNEL_TXQPIWEAKPUP", + "GTXE2_CHANNEL_RXDISPERR0", + "GTXE2_BYP2_6", + "GTXE2_CHANNEL_RXPHOVRDEN", + "GTXE2_CHANNEL_TX8B10BBYPASS4", + "GTXE2_IMUX21_5", + "GTXE2_CHANNEL_EDTCONFIGURATION", + "GTXE2_CHANNEL_DRPDO0", + "GTXE2_IMUX24_10", + "GTXE2_IMUX43_4", + "GTXE2_LOGIC_OUTS_B13_6", + "GTXE2_FAN1_4", + "GTXE2_CHANNEL_RXOUTCLK_3", + "GTXE2_IMUX0_4", + "GTXE2_LOGIC_OUTS_B8_0", + "GTXE2_CHANNEL_TXDATA33", + "GTXE2_CHANNEL_SCANCLK", + "GTXE2_CHANNEL_TX8B10BBYPASS7", + "GTXE2_IMUX25_7", + "GTXE2_BYP5_0", + "GTXE2_IMUX46_5", + "GTXE2_IMUX13_4", + "GTXE2_LOGIC_OUTS_B8_2", + "GTXE2_CHANNEL_GTRSVD2", + "GTXE2_CHANNEL_GTSOUTHREFCLK1", + "GTXE2_CHANNEL_CLKRSVD3", + "GTXE2_CHANNEL_GTQPLLCLK", + "GTXE2_CHANNEL_RXDLYSRESETDONE", + "GTXE2_CHANNEL_RXDATA48", + "GTXE2_CHANNEL_RXHEADER2", + "GTXE2_FAN7_4", + "GTXE2_IMUX30_7", + "GTXE2_CLK0_6", + "GTXE2_CHANNEL_RXDATA22", + "GTXE2_IMUX3_9", + "GTXE2_CHANNEL_PCSRSVDOUT2", + "GTXE2_IMUX34_10", + "GTXE2_CHANNEL_RXPHSLIPMONITOR2", + "GTXE2_CHANNEL_TXDATA27", + "GTXE2_CHANNEL_PMASCANCLK4", + "GTXE2_CHANNEL_TXGEARBOXREADY", + "GTXE2_IMUX44_7", + "GTXE2_CHANNEL_RXDATA53", + "GTXE2_LOGIC_OUTS_B17_6", + "GTXE2_CHANNEL_TSTIN17", + "GTXE2_CHANNEL_RXCHBONDO1", + "GTXE2_LOGIC_OUTS_B21_4", + "GTXE2_IMUX44_4", + "GTXE2_IMUX13_3", + "GTXE2_FAN7_8", + "GTXE2_CLK0_8", + "GTXE2_IMUX36_8", + "GTXE2_CHANNEL_TXSTARTSEQ", + "GTXE2_IMUX10_2", + "GTXE2_IMUX41_0", + "GTXE2_IMUX3_10", + "GTXE2_CHANNEL_TXSEQUENCE5", + "GTXE2_LOGIC_OUTS_B7_4", + "GTXE2_CHANNEL_TXMARGIN0", + "GTXE2_IMUX15_3", + "GTXE2_BYP7_3", + "GTXE2_CHANNEL_RXDATA41", + "GTXE2_CHANNEL_DRPDI1", + "GTXE2_LOGIC_OUTS_B2_0", + "GTXE2_CHANNEL_RXDATA13", + "GTXE2_LOGIC_OUTS_B15_0", + "GTXE2_CHANNEL_RXDFELFOVRDEN", + "GTXE2_IMUX37_10", + "GTXE2_CHANNEL_PMARSVDIN23", + "GTXE2_CHANNEL_RXDATA63", + "GTXE2_CHANNEL_RXDATA60", + "GTXE2_CHANNEL_EDTCLOCK", + "GTXE2_CHANNEL_RXDATA44", + "GTXE2_CHANNEL_RXCLKCORCNT0", + "GTXE2_FAN4_8", + "GTXE2_CHANNEL_DMONITOROUT7", + "GTXE2_IMUX23_9", + "GTXE2_IMUX2_0", + "GTXE2_IMUX38_4", + "GTXE2_CHANNEL_RXOSOVRDEN", + "GTXE2_IMUX28_5", + "GTXE2_IMUX9_0", + "GTXE2_CHANNEL_RXMONITOROUT0", + "GTXE2_CHANNEL_TXRATE0", + "GTXE2_CHANNEL_TX8B10BEN", + "GTXE2_IMUX42_0", + "GTXE2_IMUX38_8", + "GTXE2_IMUX5_6", + "GTXE2_IMUX7_8", + "GTXE2_CHANNEL_TXDIFFCTRL2", + "GTXE2_CHANNEL_GTRSVD3", + "GTXE2_CHANNEL_DRPDI15", + "GTXE2_IMUX2_8", + "GTXE2_IMUX18_9", + "GTXE2_LOGIC_OUTS_B10_10", + "GTXE2_CHANNEL_RXRATE1", + "GTXE2_LOGIC_OUTS_B8_8", + "GTXE2_CLK1_6", + "GTXE2_CHANNEL_RXMONITOROUT3", + "GTXE2_CHANNEL_TXOUTCLKSEL0", + "GTXE2_CHANNEL_TXSEQUENCE4", + "GTXE2_CHANNEL_TX8B10BBYPASS5", + "GTXE2_CHANNEL_DRPDO11", + "GTXE2_CTRL0_2", + "GTXE2_LOGIC_OUTS_B10_3", + "GTXE2_IMUX46_8", + "GTXE2_LOGIC_OUTS_B19_0", + "GTXE2_BYP0_4", + "GTXE2_CHANNEL_TXCHARDISPMODE4", + "GTXE2_IMUX29_7", + "GTXE2_IMUX26_1", + "GTXE2_CHANNEL_PHYSTATUS", + "GTXE2_LOGIC_OUTS_B23_7", + "GTXE2_CHANNEL_TXPRBSSEL1", + "GTXE2_IMUX0_7", + "GTXE2_IMUX41_4", + "GTXE2_CHANNEL_TXDATA23", + "GTXE2_CHANNEL_RXDATA14", + "GTXE2_CHANNEL_RXDATA26", + "GTXE2_IMUX0_6", + "GTXE2_IMUX33_0", + "GTXE2_LOGIC_OUTS_B15_2", + "GTXE2_LOGIC_OUTS_B3_9", + "GTXE2_CHANNEL_DRPDO14", + "GTXE2_CHANNEL_TXDETECTRX", + "GTXE2_CHANNEL_RXDATA6", + "GTXE2_CHANNEL_TXDATA17", + "GTXE2_IMUX0_0", + "GTXE2_IMUX47_9", + "GTXE2_IMUX3_8", + "GTXE2_IMUX8_1", + "GTXE2_IMUX28_9", + "GTXE2_IMUX13_10", + "GTXE2_CHANNEL_TXSYSCLKSEL0", + "GTXE2_LOGIC_OUTS_B4_8", + "GTXE2_LOGIC_OUTS_B2_2", + "GTXE2_CHANNEL_GTRXRESET", + "GTXE2_IMUX21_4", + "GTXE2_CHANNEL_RXPHALIGNDONE", + "GTXE2_CHANNEL_RXDATA38", + "GTXE2_LOGIC_OUTS_B15_6", + "GTXE2_CHANNEL_GTRSVD14", + "GTXE2_CHANNEL_TXCHARISK6", + "GTXE2_FAN7_9", + "GTXE2_CHANNEL_RXDATA8", + "GTXE2_CHANNEL_DRPDO2", + "GTXE2_CHANNEL_RXDATA33", + "GTXE2_CHANNEL_PMASCANOUT1", + "GTXE2_LOGIC_OUTS_B18_3", + "GTXE2_LOGIC_OUTS_B11_1", + "GTXE2_CHANNEL_SOUTHREFCLK1", + "GTXE2_CHANNEL_TXDLYUPDOWN", + "GTXE2_IMUX38_2", + "GTXE2_LOGIC_OUTS_B20_9", + "GTXE2_LOGIC_OUTS_B17_3", + "GTXE2_LOGIC_OUTS_B15_5", + "GTXE2_IMUX11_3", + "GTXE2_CHANNEL_TXRUNDISP6", + "GTXE2_CHANNEL_TXPRECURSOR1", + "GTXE2_IMUX16_0", + "GTXE2_LOGIC_OUTS_B18_9", + "GTXE2_BYP2_2", + "GTXE2_CHANNEL_RXOUTCLKPCS", + "GTXE2_IMUX29_1", + "GTXE2_FAN6_6", + "GTXE2_FAN0_4", + "GTXE2_IMUX17_6", + "GTXE2_CHANNEL_RXCHARISCOMMA2", + "GTXE2_CHANNEL_RXPHMONITOR3", + "GTXE2_LOGIC_OUTS_B5_0", + "GTXE2_IMUX10_3", + "GTXE2_BYP4_6", + "GTXE2_CHANNEL_PMARSVDIN0", + "GTXE2_IMUX19_3", + "GTXE2_IMUX13_5", + "GTXE2_IMUX15_2", + "GTXE2_LOGIC_OUTS_B2_7", + "GTXE2_CHANNEL_DRPADDR3", + "GTXE2_CHANNEL_RXELECIDLEMODE1", + "GTXE2_LOGIC_OUTS_B6_3", + "GTXE2_LOGIC_OUTS_B3_8", + "GTXE2_LOGIC_OUTS_B1_6", + "GTXE2_CHANNEL_RXDFEAGCOVRDEN", + "GTXE2_CHANNEL_RXDLYBYPASS", + "GTXE2_CHANNEL_CPLLREFCLKSEL2", + "GTXE2_CHANNEL_RXDATA49", + "GTXE2_IMUX41_3", + "GTXE2_LOGIC_OUTS_B3_7", + "GTXE2_IMUX34_9", + "GTXE2_CHANNEL_RXMONITOROUT2", + "GTXE2_LOGIC_OUTS_B2_3", + "GTXE2_BYP6_0", + "GTXE2_CHANNEL_CLKRSVD0", + "GTXE2_IMUX16_4", + "GTXE2_CHANNEL_TSTIN5", + "GTXE2_CHANNEL_RXNOTINTABLE0", + "GTXE2_LOGIC_OUTS_B22_1", + "GTXE2_IMUX7_4", + "GTXE2_IMUX37_3", + "GTXE2_IMUX12_3", + "GTXE2_CHANNEL_TSTIN16", + "GTXE2_CHANNEL_TXDATA52", + "GTXE2_IMUX20_10", + "GTXE2_CHANNEL_DRPADDR5", + "GTXE2_BYP3_5", + "GTXE2_LOGIC_OUTS_B6_5", + "GTXE2_CHANNEL_TXDATA49", + "GTXE2_CHANNEL_SCANIN2", + "GTXE2_CHANNEL_RXDFEAGCHOLD", + "GTXE2_CHANNEL_TXCHARDISPVAL2", + "GTXE2_IMUX8_6", + "GTXE2_CHANNEL_TXDATA4", + "GTXE2_CTRL0_10", + "GTXE2_IMUX23_2", + "GTXE2_IMUX34_6", + "GTXE2_LOGIC_OUTS_B4_3", + "GTXE2_CHANNEL_RX8B10BEN", + "GTXE2_CHANNEL_RXOUTCLK_2", + "GTXE2_BYP6_1", + "GTXE2_CTRL1_4", + "GTXE2_LOGIC_OUTS_B13_0", + "GTXE2_IMUX26_5", + "GTXE2_IMUX13_0", + "GTXE2_LOGIC_OUTS_B22_2", + "GTXE2_CHANNEL_RXCOMINITDET", + "GTXE2_CHANNEL_TXDLYTESTENB", + "GTXE2_IMUX25_5", + "GTXE2_IMUX45_6", + "GTXE2_LOGIC_OUTS_B14_9", + "GTXE2_CHANNEL_SCANOUT1", + "GTXE2_IMUX22_0", + "GTXE2_IMUX5_3", + "GTXE2_CHANNEL_RXSYSCLKSEL0", + "GTXE2_IMUX22_7", + "GTXE2_LOGIC_OUTS_B23_0", + "GTXE2_IMUX14_3", + "GTXE2_CHANNEL_TXDATA22", + "GTXE2_CHANNEL_RXPHDLYPD", + "GTXE2_IMUX18_2", + "GTXE2_CHANNEL_DRPDI4", + "GTXE2_CHANNEL_RXCHARISK7", + "GTXE2_IMUX24_0", + "GTXE2_CHANNEL_RXDATA37", + "GTXE2_IMUX11_2", + "GTXE2_CHANNEL_TXSYSCLKSEL1", + "GTXE2_CHANNEL_RXRATE2", + "GTXE2_IMUX17_8", + "GTXE2_CHANNEL_RXDATA5", + "GTXE2_CHANNEL_TXDATA25", + "GTXE2_IMUX47_4", + "GTXE2_CHANNEL_PMASCANOUT0", + "GTXE2_IMUX17_2", + "GTXE2_BYP0_1", + "GTXE2_CHANNEL_RXDFETAP5HOLD", + "GTXE2_IMUX5_9", + "GTXE2_CTRL1_9", + "GTXE2_IMUX15_1", + "GTXE2_CHANNEL_RXOUTCLKSEL1", + "GTXE2_CHANNEL_DRPADDR7", + "GTXE2_CLK1_4" + ], + "pips": { + "GTX_CHANNEL_3.GTXE2_IMUX28_3->GTXE2_CHANNEL_DRPWE": { + "src_wire": "GTXE2_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPWE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX23_8->GTXE2_CHANNEL_RXPRBSSEL2": { + "src_wire": "GTXE2_IMUX23_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX36_0->GTXE2_CHANNEL_DRPDI9": { + "src_wire": "GTXE2_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO15->GTXE2_LOGIC_OUTS_B3_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO15", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX4_7->GTXE2_CHANNEL_PMARSVDIN21": { + "src_wire": "GTXE2_IMUX4_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA55->GTXE2_LOGIC_OUTS_B0_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA55", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXBYTEREALIGN->GTXE2_LOGIC_OUTS_B10_10": { + "src_wire": "GTXE2_CHANNEL_RXBYTEREALIGN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX24_4->GTXE2_CHANNEL_TSTIN13": { + "src_wire": "GTXE2_IMUX24_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX27_5->GTXE2_CHANNEL_TXPHINIT": { + "src_wire": "GTXE2_IMUX27_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHINIT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX10_9->GTXE2_CHANNEL_RXQPIEN": { + "src_wire": "GTXE2_IMUX10_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXQPIEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA43->GTXE2_LOGIC_OUTS_B5_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA43", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CLK1_2->GTXE2_CHANNEL_TXPHDLYTSTCLK": { + "src_wire": "GTXE2_CLK1_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHDLYTSTCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR6->GTXE2_LOGIC_OUTS_B22_5": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX37_1->GTXE2_CHANNEL_DRPDI12": { + "src_wire": "GTXE2_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX17_9->GTXE2_CHANNEL_RXCHBONDEN": { + "src_wire": "GTXE2_IMUX17_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX38_1->GTXE2_CHANNEL_DRPDI5": { + "src_wire": "GTXE2_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX18_3->GTXE2_CHANNEL_TXDATA16": { + "src_wire": "GTXE2_IMUX18_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA16", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA29->GTXE2_LOGIC_OUTS_B7_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA29", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX19_5->GTXE2_CHANNEL_TXDATA9": { + "src_wire": "GTXE2_IMUX19_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX38_5->GTXE2_CHANNEL_TXSWING": { + "src_wire": "GTXE2_IMUX38_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSWING", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX29_0->GTXE2_CHANNEL_TXCHARDISPMODE3": { + "src_wire": "GTXE2_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX14_10->GTXE2_CHANNEL_RXPHOVRDEN": { + "src_wire": "GTXE2_IMUX14_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO8->GTXE2_LOGIC_OUTS_B0_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA60->GTXE2_LOGIC_OUTS_B6_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA60", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT5->GTXE2_LOGIC_OUTS_B8_5": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXRATEDONE->GTXE2_LOGIC_OUTS_B20_4": { + "src_wire": "GTXE2_CHANNEL_TXRATEDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX35_6->GTXE2_CHANNEL_TXPD1": { + "src_wire": "GTXE2_IMUX35_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO5->GTXE2_LOGIC_OUTS_B1_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT2->GTXE2_LOGIC_OUTS_B13_2": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT6->GTXE2_LOGIC_OUTS_B8_4": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX23_1->GTXE2_CHANNEL_TXDATA27": { + "src_wire": "GTXE2_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA27", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXRATEDONE->GTXE2_LOGIC_OUTS_B23_5": { + "src_wire": "GTXE2_CHANNEL_RXRATEDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX20_4->GTXE2_CHANNEL_TXDATA14": { + "src_wire": "GTXE2_IMUX20_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXBUFSTATUS0->GTXE2_LOGIC_OUTS_B23_10": { + "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX40_8->GTXE2_CHANNEL_TSTIN7": { + "src_wire": "GTXE2_IMUX40_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA25->GTXE2_LOGIC_OUTS_B2_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA25", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX25_5->GTXE2_CHANNEL_PCSRSVDIN2": { + "src_wire": "GTXE2_IMUX25_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX28_6->GTXE2_CHANNEL_RXDLYEN": { + "src_wire": "GTXE2_IMUX28_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX45_8->GTXE2_CHANNEL_EYESCANRESET": { + "src_wire": "GTXE2_IMUX45_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_EYESCANRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX14_9->GTXE2_CHANNEL_RXPHALIGN": { + "src_wire": "GTXE2_IMUX14_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHALIGN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCOMSASDET->GTXE2_LOGIC_OUTS_B18_7": { + "src_wire": "GTXE2_CHANNEL_RXCOMSASDET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX17_6->GTXE2_CHANNEL_TXDATA5": { + "src_wire": "GTXE2_IMUX17_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX36_2->GTXE2_CHANNEL_CPLLPD": { + "src_wire": "GTXE2_IMUX36_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO1->GTXE2_LOGIC_OUTS_B4_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX42_6->GTXE2_CHANNEL_GTRSVD3": { + "src_wire": "GTXE2_IMUX42_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA54->GTXE2_LOGIC_OUTS_B4_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA54", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX19_3->GTXE2_CHANNEL_TXDATA17": { + "src_wire": "GTXE2_IMUX19_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA17", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CLK1_4->GTXE2_CHANNEL_CLKRSVD0": { + "src_wire": "GTXE2_CLK1_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX35_3->GTXE2_CHANNEL_DRPADDR6": { + "src_wire": "GTXE2_IMUX35_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX39_3->GTXE2_CHANNEL_DRPADDR4": { + "src_wire": "GTXE2_IMUX39_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE3->GTXE2_LOGIC_OUTS_B14_4": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX46_6->GTXE2_CHANNEL_TXRATE1": { + "src_wire": "GTXE2_IMUX46_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXRATE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX25_6->GTXE2_CHANNEL_PCSRSVDIN3": { + "src_wire": "GTXE2_IMUX25_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX16_10->GTXE2_CHANNEL_RXDFECM1EN": { + "src_wire": "GTXE2_IMUX16_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFECM1EN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX47_6->GTXE2_CHANNEL_TXRATE0": { + "src_wire": "GTXE2_IMUX47_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXRATE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX2_10->GTXE2_CHANNEL_RXOUTCLKSEL2": { + "src_wire": "GTXE2_IMUX2_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CLK1_8->GTXE2_CHANNEL_CLKRSVD3": { + "src_wire": "GTXE2_CLK1_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX31_8->GTXE2_CHANNEL_EYESCANTRIGGER": { + "src_wire": "GTXE2_IMUX31_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_EYESCANTRIGGER", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX8_4->GTXE2_CHANNEL_TXCHARDISPVAL1": { + "src_wire": "GTXE2_IMUX8_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA47->GTXE2_LOGIC_OUTS_B0_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA47", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX38_6->GTXE2_CHANNEL_TXPD0": { + "src_wire": "GTXE2_IMUX38_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX7_8->GTXE2_CHANNEL_TXPRBSSEL2": { + "src_wire": "GTXE2_IMUX7_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX2_8->GTXE2_CHANNEL_RXGEARBOXSLIP": { + "src_wire": "GTXE2_IMUX2_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXGEARBOXSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX9_8->GTXE2_CHANNEL_PCSRSVDIN13": { + "src_wire": "GTXE2_IMUX9_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_GTREFCLKMONITOR->GTXE2_LOGIC_OUTS_B23_2": { + "src_wire": "GTXE2_CHANNEL_GTREFCLKMONITOR", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL0_6->GTXE2_CHANNEL_RXDLYSRESET": { + "src_wire": "GTXE2_CTRL0_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXQPISENN->GTXE2_LOGIC_OUTS_B17_1": { + "src_wire": "GTXE2_CHANNEL_RXQPISENN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL1_1->GTXE2_CHANNEL_RXPHDLYRESET": { + "src_wire": "GTXE2_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHDLYRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHMONITOR4->GTXE2_LOGIC_OUTS_B21_3": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CLK0_6->GTXE2_CHANNEL_RXUSRCLK": { + "src_wire": "GTXE2_CLK0_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXUSRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX26_9->GTXE2_CHANNEL_GTRSVD14": { + "src_wire": "GTXE2_IMUX26_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX29_3->GTXE2_CHANNEL_TXCHARISK6": { + "src_wire": "GTXE2_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX6_6->GTXE2_CHANNEL_TXPRECURSOR1": { + "src_wire": "GTXE2_IMUX6_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA63->GTXE2_LOGIC_OUTS_B0_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA63", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX4_9->GTXE2_CHANNEL_PMARSVDIN1": { + "src_wire": "GTXE2_IMUX4_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX19_1->GTXE2_CHANNEL_TXDATA25": { + "src_wire": "GTXE2_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA25", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT9->GTXE2_LOGIC_OUTS_B13_9": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX37_9->GTXE2_CHANNEL_RXDFETAP4HOLD": { + "src_wire": "GTXE2_IMUX37_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP4HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX40_5->GTXE2_CHANNEL_TSTIN4": { + "src_wire": "GTXE2_IMUX40_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX19_9->GTXE2_CHANNEL_RXCHBONDI1": { + "src_wire": "GTXE2_IMUX19_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX27_10->GTXE2_CHANNEL_RXLPMHFOVRDEN": { + "src_wire": "GTXE2_IMUX27_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMHFOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B22_1": { + "src_wire": "GTXE2_CHANNEL_RXDLYSRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX1_5->GTXE2_CHANNEL_TXSEQUENCE2": { + "src_wire": "GTXE2_IMUX1_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX13_9->GTXE2_CHANNEL_RXDFETAP5OVRDEN": { + "src_wire": "GTXE2_IMUX13_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT0->GTXE2_LOGIC_OUTS_B8_10": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT4->GTXE2_LOGIC_OUTS_B11_4": { + "src_wire": "GTXE2_CHANNEL_TSTOUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPRDY->GTXE2_LOGIC_OUTS_B20_0": { + "src_wire": "GTXE2_CHANNEL_DRPRDY", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX8_6->GTXE2_CHANNEL_TXCHARDISPVAL0": { + "src_wire": "GTXE2_IMUX8_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA11->GTXE2_LOGIC_OUTS_B0_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA11", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX7_3->GTXE2_CHANNEL_TXPOSTCURSOR4": { + "src_wire": "GTXE2_IMUX7_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCOMINITDET->GTXE2_LOGIC_OUTS_B20_7": { + "src_wire": "GTXE2_CHANNEL_RXCOMINITDET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX10_6->GTXE2_CHANNEL_TXCHARDISPVAL4": { + "src_wire": "GTXE2_IMUX10_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX45_9->GTXE2_CHANNEL_RXDFEXYDEN": { + "src_wire": "GTXE2_IMUX45_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEXYDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX4_8->GTXE2_CHANNEL_TXOUTCLKSEL1": { + "src_wire": "GTXE2_IMUX4_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXSTARTOFSEQ->GTXE2_LOGIC_OUTS_B18_8": { + "src_wire": "GTXE2_CHANNEL_RXSTARTOFSEQ", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX33_0->GTXE2_CHANNEL_DRPDI10": { + "src_wire": "GTXE2_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX1_9->GTXE2_CHANNEL_PMARSVDIN2": { + "src_wire": "GTXE2_IMUX1_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_4": { + "src_wire": "GTXE2_CHANNEL_RXPHALIGNDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX16_5->GTXE2_CHANNEL_TXDATA40": { + "src_wire": "GTXE2_IMUX16_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA40", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CLK1_1->GTXE2_CHANNEL_DRPCLK": { + "src_wire": "GTXE2_CLK1_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX12_7->GTXE2_CHANNEL_TXBUFDIFFCTRL0": { + "src_wire": "GTXE2_IMUX12_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX7_4->GTXE2_CHANNEL_TXPOSTCURSOR0": { + "src_wire": "GTXE2_IMUX7_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX16_6->GTXE2_CHANNEL_TXDATA4": { + "src_wire": "GTXE2_IMUX16_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX29_8->GTXE2_CHANNEL_RXOSHOLD": { + "src_wire": "GTXE2_IMUX29_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOSHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX25_2->GTXE2_CHANNEL_TXPHALIGN": { + "src_wire": "GTXE2_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHALIGN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX7_0->GTXE2_CHANNEL_TXPISOPD": { + "src_wire": "GTXE2_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPISOPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX4_5->GTXE2_CHANNEL_TXSEQUENCE1": { + "src_wire": "GTXE2_IMUX4_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX1_10->GTXE2_CHANNEL_RXELECIDLEMODE1": { + "src_wire": "GTXE2_IMUX1_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX45_10->GTXE2_CHANNEL_RXMONITORSEL0": { + "src_wire": "GTXE2_IMUX45_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX23_9->GTXE2_CHANNEL_RXCHBONDI3": { + "src_wire": "GTXE2_IMUX23_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL1_6->GTXE2_CHANNEL_RXBUFRESET": { + "src_wire": "GTXE2_CTRL1_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXBUFRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX21_7->GTXE2_CHANNEL_TXDATA32": { + "src_wire": "GTXE2_IMUX21_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA32", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT8->GTXE2_LOGIC_OUTS_B11_8": { + "src_wire": "GTXE2_CHANNEL_TSTOUT8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO7->GTXE2_LOGIC_OUTS_B3_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA37->GTXE2_LOGIC_OUTS_B2_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA37", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX39_5->GTXE2_CHANNEL_TXDETECTRX": { + "src_wire": "GTXE2_IMUX39_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDETECTRX", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDO3->GTXE2_LOGIC_OUTS_B16_7": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX24_8->GTXE2_CHANNEL_TSTIN17": { + "src_wire": "GTXE2_IMUX24_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN17", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXBUFSTATUS1->GTXE2_LOGIC_OUTS_B19_10": { + "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA57->GTXE2_LOGIC_OUTS_B7_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA57", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX12_10->GTXE2_CHANNEL_RXDFETAP3OVRDEN": { + "src_wire": "GTXE2_IMUX12_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK0->GTXE2_LOGIC_OUTS_B12_10": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXPHINITDONE->GTXE2_LOGIC_OUTS_B17_0": { + "src_wire": "GTXE2_CHANNEL_TXPHINITDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX37_3->GTXE2_CHANNEL_TXPHDLYPD": { + "src_wire": "GTXE2_IMUX37_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHDLYPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX28_4->GTXE2_CHANNEL_TXSYSCLKSEL1": { + "src_wire": "GTXE2_IMUX28_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX35_1->GTXE2_CHANNEL_DRPDI6": { + "src_wire": "GTXE2_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX34_3->GTXE2_CHANNEL_DRPADDR7": { + "src_wire": "GTXE2_IMUX34_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA4->GTXE2_LOGIC_OUTS_B15_10": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT1->GTXE2_LOGIC_OUTS_B13_1": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX7_7->GTXE2_CHANNEL_TXPRECURSOR4": { + "src_wire": "GTXE2_IMUX7_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXRESETDONE->GTXE2_LOGIC_OUTS_B16_4": { + "src_wire": "GTXE2_CHANNEL_TXRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX41_5->GTXE2_CHANNEL_RESETOVRD": { + "src_wire": "GTXE2_IMUX41_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RESETOVRD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX16_7->GTXE2_CHANNEL_TXDATA35": { + "src_wire": "GTXE2_IMUX16_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA35", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR0->GTXE2_LOGIC_OUTS_B22_10": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA58->GTXE2_LOGIC_OUTS_B1_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA58", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX11_2->GTXE2_CHANNEL_CPLLREFCLKSEL2": { + "src_wire": "GTXE2_IMUX11_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_CPLLFBCLKLOST->GTXE2_LOGIC_OUTS_B8_1": { + "src_wire": "GTXE2_CHANNEL_CPLLFBCLKLOST", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT4->GTXE2_LOGIC_OUTS_B13_4": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO3->GTXE2_LOGIC_OUTS_B6_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX19_7->GTXE2_CHANNEL_TXDATA1": { + "src_wire": "GTXE2_IMUX19_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX4_6->GTXE2_CHANNEL_TXSEQUENCE5": { + "src_wire": "GTXE2_IMUX4_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX3_7->GTXE2_CHANNEL_RXPD0": { + "src_wire": "GTXE2_IMUX3_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX39_6->GTXE2_CHANNEL_TXELECIDLE": { + "src_wire": "GTXE2_IMUX39_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXELECIDLE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHMONITOR2->GTXE2_LOGIC_OUTS_B7_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX37_4->GTXE2_CHANNEL_TXDIFFPD": { + "src_wire": "GTXE2_IMUX37_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL0_8->GTXE2_CHANNEL_GTRXRESET": { + "src_wire": "GTXE2_CTRL0_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRXRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT13->GTXE2_LOGIC_OUTS_B9_2": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT13", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX31_1->GTXE2_CHANNEL_TXCHARISK3": { + "src_wire": "GTXE2_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX18_10->GTXE2_CHANNEL_RXCHBONDLEVEL0": { + "src_wire": "GTXE2_IMUX18_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK4->GTXE2_LOGIC_OUTS_B12_9": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHANBONDSEQ->GTXE2_LOGIC_OUTS_B10_8": { + "src_wire": "GTXE2_CHANNEL_RXCHANBONDSEQ", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA10->GTXE2_LOGIC_OUTS_B4_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA10", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXBUFSTATUS0->GTXE2_LOGIC_OUTS_B17_2": { + "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX16_2->GTXE2_CHANNEL_TXDATA20": { + "src_wire": "GTXE2_IMUX16_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX7_6->GTXE2_CHANNEL_TXPRECURSOR0": { + "src_wire": "GTXE2_IMUX7_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX8_1->GTXE2_CHANNEL_TX8B10BBYPASS7": { + "src_wire": "GTXE2_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX4_10->GTXE2_CHANNEL_RXOUTCLKSEL0": { + "src_wire": "GTXE2_IMUX4_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT5->GTXE2_LOGIC_OUTS_B9_5": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX0_6->GTXE2_CHANNEL_PMARSVDIN24": { + "src_wire": "GTXE2_IMUX0_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX28_5->GTXE2_CHANNEL_TXSYSCLKSEL0": { + "src_wire": "GTXE2_IMUX28_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE0->GTXE2_LOGIC_OUTS_B14_10": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA32->GTXE2_LOGIC_OUTS_B3_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA32", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX42_10->GTXE2_CHANNEL_GTRSVD7": { + "src_wire": "GTXE2_IMUX42_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX42_9->GTXE2_CHANNEL_GTRSVD6": { + "src_wire": "GTXE2_IMUX42_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_REFCLK0->GTXE2_CHANNEL_GTREFCLK0": { + "src_wire": "GTXE2_CHANNEL_REFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX20_3->GTXE2_CHANNEL_TXDATA50": { + "src_wire": "GTXE2_IMUX20_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA50", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX29_2->GTXE2_CHANNEL_TXCHARDISPMODE2": { + "src_wire": "GTXE2_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX24_1->GTXE2_CHANNEL_TSTIN10": { + "src_wire": "GTXE2_IMUX24_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX5_6->GTXE2_CHANNEL_TXSEQUENCE4": { + "src_wire": "GTXE2_IMUX5_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXRESETDONE->GTXE2_LOGIC_OUTS_B20_8": { + "src_wire": "GTXE2_CHANNEL_RXRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX9_3->GTXE2_CHANNEL_PCSRSVDIN8": { + "src_wire": "GTXE2_IMUX9_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_QPLLREFCLK->GTXE2_CHANNEL_GTQPLLREFCLK": { + "src_wire": "GTXE2_CHANNEL_QPLLREFCLK", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTQPLLREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX5_10->GTXE2_CHANNEL_RXOUTCLKSEL1": { + "src_wire": "GTXE2_IMUX5_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CLK0_5->GTXE2_CHANNEL_TXUSRCLK2": { + "src_wire": "GTXE2_CLK0_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXUSRCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX34_10->GTXE2_CHANNEL_PCSRSVDIN20": { + "src_wire": "GTXE2_IMUX34_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX8_7->GTXE2_CHANNEL_TX8B10BBYPASS4": { + "src_wire": "GTXE2_IMUX8_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA7->GTXE2_LOGIC_OUTS_B15_4": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX0_5->GTXE2_CHANNEL_TXSEQUENCE3": { + "src_wire": "GTXE2_IMUX0_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL1_7->GTXE2_CHANNEL_RXPMARESET": { + "src_wire": "GTXE2_CTRL1_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPMARESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO12->GTXE2_LOGIC_OUTS_B5_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO12", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX4_1->GTXE2_CHANNEL_TXPRECURSORINV": { + "src_wire": "GTXE2_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSORINV", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX30_10->GTXE2_CHANNEL_RXCHBONDSLAVE": { + "src_wire": "GTXE2_IMUX30_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDSLAVE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX45_2->GTXE2_CHANNEL_RXSYSCLKSEL0": { + "src_wire": "GTXE2_IMUX45_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX0_9->GTXE2_CHANNEL_PMARSVDIN3": { + "src_wire": "GTXE2_IMUX0_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX31_3->GTXE2_CHANNEL_TXCHARISK2": { + "src_wire": "GTXE2_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX40_1->GTXE2_CHANNEL_TSTIN0": { + "src_wire": "GTXE2_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX22_1->GTXE2_CHANNEL_TXDATA26": { + "src_wire": "GTXE2_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA26", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX10_4->GTXE2_CHANNEL_TXCHARDISPVAL5": { + "src_wire": "GTXE2_IMUX10_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_CPLLREFCLKLOST->GTXE2_LOGIC_OUTS_B18_1": { + "src_wire": "GTXE2_CHANNEL_CPLLREFCLKLOST", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX8_3->GTXE2_CHANNEL_TX8B10BBYPASS6": { + "src_wire": "GTXE2_IMUX8_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX43_9->GTXE2_CHANNEL_LOOPBACK0": { + "src_wire": "GTXE2_IMUX43_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_LOOPBACK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT8->GTXE2_LOGIC_OUTS_B13_8": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX19_4->GTXE2_CHANNEL_TXDATA45": { + "src_wire": "GTXE2_IMUX19_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA45", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX38_8->GTXE2_CHANNEL_RXPRBSSEL1": { + "src_wire": "GTXE2_IMUX38_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL1_3->GTXE2_CHANNEL_TXPMARESET": { + "src_wire": "GTXE2_CTRL1_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPMARESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX4_3->GTXE2_CHANNEL_TXMAINCURSOR1": { + "src_wire": "GTXE2_IMUX4_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA49->GTXE2_LOGIC_OUTS_B7_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA49", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO10->GTXE2_LOGIC_OUTS_B2_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO10", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX6_4->GTXE2_CHANNEL_TXPOSTCURSOR1": { + "src_wire": "GTXE2_IMUX6_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX1_4->GTXE2_CHANNEL_TXMAINCURSOR6": { + "src_wire": "GTXE2_IMUX1_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL0_9->GTXE2_CHANNEL_RXDFELPMRESET": { + "src_wire": "GTXE2_CTRL0_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFELPMRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT10->GTXE2_LOGIC_OUTS_B13_10": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT10", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL0_10->GTXE2_CHANNEL_GTRESETSEL": { + "src_wire": "GTXE2_CTRL0_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRESETSEL", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX35_8->GTXE2_CHANNEL_RXDFEUTOVRDEN": { + "src_wire": "GTXE2_IMUX35_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEUTOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA3->GTXE2_LOGIC_OUTS_B0_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA20->GTXE2_LOGIC_OUTS_B3_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA20", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA44->GTXE2_LOGIC_OUTS_B6_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA44", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX23_2->GTXE2_CHANNEL_TXDATA55": { + "src_wire": "GTXE2_IMUX23_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA55", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX33_2->GTXE2_CHANNEL_TXPHALIGNEN": { + "src_wire": "GTXE2_IMUX33_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL0_7->GTXE2_CHANNEL_RXCDRFREQRESET": { + "src_wire": "GTXE2_CTRL0_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRFREQRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX8_8->GTXE2_CHANNEL_RXDDIEN": { + "src_wire": "GTXE2_IMUX8_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDDIEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_EYESCANDATAERROR->GTXE2_LOGIC_OUTS_B20_10": { + "src_wire": "GTXE2_CHANNEL_EYESCANDATAERROR", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX25_4->GTXE2_CHANNEL_PCSRSVDIN1": { + "src_wire": "GTXE2_IMUX25_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA36->GTXE2_LOGIC_OUTS_B6_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA36", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX40_4->GTXE2_CHANNEL_TSTIN3": { + "src_wire": "GTXE2_IMUX40_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXCOMFINISH->GTXE2_LOGIC_OUTS_B16_5": { + "src_wire": "GTXE2_CHANNEL_TXCOMFINISH", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA46->GTXE2_LOGIC_OUTS_B4_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA46", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXN_PAD->GTXE2_CHANNEL_RXN": { + "src_wire": "GTXE2_CHANNEL_RXN_PAD", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX18_5->GTXE2_CHANNEL_TXDATA8": { + "src_wire": "GTXE2_IMUX18_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX34_0->GTXE2_CHANNEL_DRPDI3": { + "src_wire": "GTXE2_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX3_5->GTXE2_CHANNEL_TXDIFFCTRL2": { + "src_wire": "GTXE2_IMUX3_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT12->GTXE2_LOGIC_OUTS_B9_1": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT12", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX1_3->GTXE2_CHANNEL_TXMAINCURSOR2": { + "src_wire": "GTXE2_IMUX1_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO11->GTXE2_LOGIC_OUTS_B6_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO11", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_NORTHREFCLK1->GTXE2_CHANNEL_GTNORTHREFCLK1": { + "src_wire": "GTXE2_CHANNEL_NORTHREFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX19_10->GTXE2_CHANNEL_RXCHBONDLEVEL1": { + "src_wire": "GTXE2_IMUX19_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX13_7->GTXE2_CHANNEL_TXBUFDIFFCTRL1": { + "src_wire": "GTXE2_IMUX13_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT7->GTXE2_LOGIC_OUTS_B13_7": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX32_2->GTXE2_CHANNEL_TXINHIBIT": { + "src_wire": "GTXE2_IMUX32_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXINHIBIT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA1->GTXE2_LOGIC_OUTS_B15_7": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX26_3->GTXE2_CHANNEL_GTRSVD8": { + "src_wire": "GTXE2_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA6->GTXE2_LOGIC_OUTS_B15_6": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX20_6->GTXE2_CHANNEL_TXDATA6": { + "src_wire": "GTXE2_IMUX20_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX34_1->GTXE2_CHANNEL_DRPDI7": { + "src_wire": "GTXE2_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL1_5->GTXE2_CHANNEL_CFGRESET": { + "src_wire": "GTXE2_CTRL1_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CFGRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXSTATUS0->GTXE2_LOGIC_OUTS_B21_8": { + "src_wire": "GTXE2_CHANNEL_RXSTATUS0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCOMWAKEDET->GTXE2_LOGIC_OUTS_B19_9": { + "src_wire": "GTXE2_CHANNEL_RXCOMWAKEDET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX15_4->GTXE2_CHANNEL_TXPRBSFORCEERR": { + "src_wire": "GTXE2_IMUX15_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSFORCEERR", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX19_6->GTXE2_CHANNEL_TXDATA37": { + "src_wire": "GTXE2_IMUX19_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA37", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX16_3->GTXE2_CHANNEL_TXDATA48": { + "src_wire": "GTXE2_IMUX16_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA48", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA12->GTXE2_LOGIC_OUTS_B3_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA12", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX38_0->GTXE2_CHANNEL_DRPDI1": { + "src_wire": "GTXE2_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXSTATUS2->GTXE2_LOGIC_OUTS_B23_8": { + "src_wire": "GTXE2_CHANNEL_RXSTATUS2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA16->GTXE2_LOGIC_OUTS_B6_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA16", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX18_1->GTXE2_CHANNEL_TXDATA24": { + "src_wire": "GTXE2_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHSLIPMONITOR1->GTXE2_LOGIC_OUTS_B4_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA7->GTXE2_LOGIC_OUTS_B5_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX21_0->GTXE2_CHANNEL_TXDATA31": { + "src_wire": "GTXE2_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA31", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX3_9->GTXE2_CHANNEL_RXDFEUTHOLD": { + "src_wire": "GTXE2_IMUX3_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEUTHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX15_5->GTXE2_CHANNEL_TX8B10BBYPASS1": { + "src_wire": "GTXE2_IMUX15_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX42_8->GTXE2_CHANNEL_GTRSVD5": { + "src_wire": "GTXE2_IMUX42_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX24_10->GTXE2_CHANNEL_TSTIN19": { + "src_wire": "GTXE2_IMUX24_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN19", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA41->GTXE2_LOGIC_OUTS_B7_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA41", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT3->GTXE2_LOGIC_OUTS_B8_7": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA56->GTXE2_LOGIC_OUTS_B3_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA56", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDO4->GTXE2_LOGIC_OUTS_B16_6": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX31_0->GTXE2_CHANNEL_TXCHARDISPMODE7": { + "src_wire": "GTXE2_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX36_1->GTXE2_CHANNEL_DRPDI13": { + "src_wire": "GTXE2_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT3->GTXE2_LOGIC_OUTS_B11_3": { + "src_wire": "GTXE2_CHANNEL_TSTOUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_NORTHREFCLK0->GTXE2_CHANNEL_GTNORTHREFCLK0": { + "src_wire": "GTXE2_CHANNEL_NORTHREFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX26_5->GTXE2_CHANNEL_GTRSVD10": { + "src_wire": "GTXE2_IMUX26_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX43_6->GTXE2_CHANNEL_TXRATE2": { + "src_wire": "GTXE2_IMUX43_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXRATE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX10_2->GTXE2_CHANNEL_TXCHARDISPVAL6": { + "src_wire": "GTXE2_IMUX10_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX25_8->GTXE2_CHANNEL_PCSRSVDIN5": { + "src_wire": "GTXE2_IMUX25_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_GTTXOUTCLK_3->GTXE2_CHANNEL_TXOUTCLK_3": { + "src_wire": "GTXE2_CHANNEL_GTTXOUTCLK_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX40_6->GTXE2_CHANNEL_TSTIN5": { + "src_wire": "GTXE2_IMUX40_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHMONITOR1->GTXE2_LOGIC_OUTS_B1_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX40_3->GTXE2_CHANNEL_TSTIN2": { + "src_wire": "GTXE2_IMUX40_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX28_8->GTXE2_CHANNEL_RXPD1": { + "src_wire": "GTXE2_IMUX28_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXHEADER0->GTXE2_LOGIC_OUTS_B19_6": { + "src_wire": "GTXE2_CHANNEL_RXHEADER0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA0->GTXE2_LOGIC_OUTS_B6_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA51->GTXE2_LOGIC_OUTS_B5_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA51", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE4->GTXE2_LOGIC_OUTS_B14_9": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA40->GTXE2_LOGIC_OUTS_B3_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA40", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX5_4->GTXE2_CHANNEL_TXMAINCURSOR4": { + "src_wire": "GTXE2_IMUX5_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX31_2->GTXE2_CHANNEL_TXCHARDISPMODE6": { + "src_wire": "GTXE2_IMUX31_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA2->GTXE2_LOGIC_OUTS_B15_5": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE5->GTXE2_LOGIC_OUTS_B14_7": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX29_4->GTXE2_CHANNEL_TXCHARDISPMODE1": { + "src_wire": "GTXE2_IMUX29_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR2->GTXE2_LOGIC_OUTS_B22_6": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT7->GTXE2_LOGIC_OUTS_B11_7": { + "src_wire": "GTXE2_CHANNEL_TSTOUT7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX10_7->GTXE2_CHANNEL_TXBUFDIFFCTRL2": { + "src_wire": "GTXE2_IMUX10_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA21->GTXE2_LOGIC_OUTS_B7_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA21", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX22_8->GTXE2_CHANNEL_RXPRBSSEL0": { + "src_wire": "GTXE2_IMUX22_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX25_9->GTXE2_CHANNEL_PCSRSVDIN6": { + "src_wire": "GTXE2_IMUX25_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX34_4->GTXE2_CHANNEL_SETERRSTATUS": { + "src_wire": "GTXE2_IMUX34_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_SETERRSTATUS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX15_2->GTXE2_CHANNEL_CPLLREFCLKSEL0": { + "src_wire": "GTXE2_IMUX15_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXELECIDLE->GTXE2_LOGIC_OUTS_B19_8": { + "src_wire": "GTXE2_CHANNEL_RXELECIDLE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX35_0->GTXE2_CHANNEL_DRPDI2": { + "src_wire": "GTXE2_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO13->GTXE2_LOGIC_OUTS_B1_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO13", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX9_1->GTXE2_CHANNEL_RXPHDLYPD": { + "src_wire": "GTXE2_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHDLYPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX22_5->GTXE2_CHANNEL_TXDATA10": { + "src_wire": "GTXE2_IMUX22_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT4->GTXE2_LOGIC_OUTS_B9_6": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA35->GTXE2_LOGIC_OUTS_B5_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA35", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX17_3->GTXE2_CHANNEL_TXDATA49": { + "src_wire": "GTXE2_IMUX17_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA49", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA53->GTXE2_LOGIC_OUTS_B2_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA53", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK5->GTXE2_LOGIC_OUTS_B12_7": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA62->GTXE2_LOGIC_OUTS_B4_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA62", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX40_7->GTXE2_CHANNEL_TSTIN6": { + "src_wire": "GTXE2_IMUX40_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX3_8->GTXE2_CHANNEL_TXPRBSSEL0": { + "src_wire": "GTXE2_IMUX3_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX29_7->GTXE2_CHANNEL_TXCHARISK4": { + "src_wire": "GTXE2_IMUX29_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX44_5->GTXE2_CHANNEL_TXDLYBYPASS": { + "src_wire": "GTXE2_IMUX44_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYBYPASS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX24_6->GTXE2_CHANNEL_TSTIN15": { + "src_wire": "GTXE2_IMUX24_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT11->GTXE2_LOGIC_OUTS_B9_0": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT11", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA18->GTXE2_LOGIC_OUTS_B4_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA18", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX0_10->GTXE2_CHANNEL_RXELECIDLEMODE0": { + "src_wire": "GTXE2_IMUX0_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXQPISENP->GTXE2_LOGIC_OUTS_B8_3": { + "src_wire": "GTXE2_CHANNEL_TXQPISENP", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX42_4->GTXE2_CHANNEL_GTRSVD1": { + "src_wire": "GTXE2_IMUX42_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT0->GTXE2_LOGIC_OUTS_B13_0": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX39_10->GTXE2_CHANNEL_PCSRSVDIN23": { + "src_wire": "GTXE2_IMUX39_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX35_10->GTXE2_CHANNEL_PCSRSVDIN21": { + "src_wire": "GTXE2_IMUX35_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHSLIPMONITOR2->GTXE2_LOGIC_OUTS_B2_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXQPISENN->GTXE2_LOGIC_OUTS_B20_3": { + "src_wire": "GTXE2_CHANNEL_TXQPISENN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX9_4->GTXE2_CHANNEL_PCSRSVDIN9": { + "src_wire": "GTXE2_IMUX9_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX17_5->GTXE2_CHANNEL_TXDATA41": { + "src_wire": "GTXE2_IMUX17_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA41", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX38_2->GTXE2_CHANNEL_DRPADDR1": { + "src_wire": "GTXE2_IMUX38_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA27->GTXE2_LOGIC_OUTS_B0_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA27", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX26_4->GTXE2_CHANNEL_GTRSVD9": { + "src_wire": "GTXE2_IMUX26_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT0->GTXE2_LOGIC_OUTS_B11_0": { + "src_wire": "GTXE2_CHANNEL_TSTOUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX36_5->GTXE2_CHANNEL_TXPHDLYRESET": { + "src_wire": "GTXE2_IMUX36_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHDLYRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX12_9->GTXE2_CHANNEL_RX8B10BEN": { + "src_wire": "GTXE2_IMUX12_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RX8B10BEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX17_7->GTXE2_CHANNEL_TXDATA34": { + "src_wire": "GTXE2_IMUX17_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA34", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX27_9->GTXE2_CHANNEL_RXDFELFOVRDEN": { + "src_wire": "GTXE2_IMUX27_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFELFOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA2->GTXE2_LOGIC_OUTS_B4_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX34_8->GTXE2_CHANNEL_RXLPMEN": { + "src_wire": "GTXE2_IMUX34_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX19_0->GTXE2_CHANNEL_TXDATA61": { + "src_wire": "GTXE2_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA61", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX41_1->GTXE2_CHANNEL_TXPOSTCURSORINV": { + "src_wire": "GTXE2_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSORINV", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX21_6->GTXE2_CHANNEL_TXDATA7": { + "src_wire": "GTXE2_IMUX21_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX0_7->GTXE2_CHANNEL_PMARSVDIN23": { + "src_wire": "GTXE2_IMUX0_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX22_2->GTXE2_CHANNEL_TXDATA54": { + "src_wire": "GTXE2_IMUX22_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA54", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHSLIPMONITOR3->GTXE2_LOGIC_OUTS_B6_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX23_10->GTXE2_CHANNEL_RXCHBONDI4": { + "src_wire": "GTXE2_IMUX23_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX5_5->GTXE2_CHANNEL_TXSEQUENCE0": { + "src_wire": "GTXE2_IMUX5_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX28_2->GTXE2_CHANNEL_CPLLLOCKEN": { + "src_wire": "GTXE2_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLLOCKEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CLK0_4->GTXE2_CHANNEL_TXUSRCLK": { + "src_wire": "GTXE2_CLK0_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXUSRCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX6_8->GTXE2_CHANNEL_TXPRBSSEL1": { + "src_wire": "GTXE2_IMUX6_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX12_1->GTXE2_CHANNEL_TXCOMWAKE": { + "src_wire": "GTXE2_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCOMWAKE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX42_2->GTXE2_CHANNEL_RXSYSCLKSEL1": { + "src_wire": "GTXE2_IMUX42_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX27_8->GTXE2_CHANNEL_RXDFEVPOVRDEN": { + "src_wire": "GTXE2_IMUX27_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEVPOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX9_10->GTXE2_CHANNEL_PCSRSVDIN15": { + "src_wire": "GTXE2_IMUX9_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA31->GTXE2_LOGIC_OUTS_B5_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA31", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX39_9->GTXE2_CHANNEL_PCSRSVDIN24": { + "src_wire": "GTXE2_IMUX39_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX14_6->GTXE2_CHANNEL_RXRATE1": { + "src_wire": "GTXE2_IMUX14_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXRATE1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT6->GTXE2_LOGIC_OUTS_B11_6": { + "src_wire": "GTXE2_CHANNEL_TSTOUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX21_2->GTXE2_CHANNEL_TXDATA23": { + "src_wire": "GTXE2_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA26->GTXE2_LOGIC_OUTS_B4_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA26", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX21_3->GTXE2_CHANNEL_TXDATA51": { + "src_wire": "GTXE2_IMUX21_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA51", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_SOUTHREFCLK0->GTXE2_CHANNEL_GTSOUTHREFCLK0": { + "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX2_6->GTXE2_CHANNEL_TXPRECURSOR3": { + "src_wire": "GTXE2_IMUX2_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL1_10->GTXE2_CHANNEL_RXOOBRESET": { + "src_wire": "GTXE2_CTRL1_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOOBRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA6->GTXE2_LOGIC_OUTS_B1_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX22_6->GTXE2_CHANNEL_TXDATA38": { + "src_wire": "GTXE2_IMUX22_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA38", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO4->GTXE2_LOGIC_OUTS_B5_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX4_4->GTXE2_CHANNEL_TXMAINCURSOR5": { + "src_wire": "GTXE2_IMUX4_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT2->GTXE2_LOGIC_OUTS_B11_2": { + "src_wire": "GTXE2_CHANNEL_TSTOUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX37_0->GTXE2_CHANNEL_DRPDI8": { + "src_wire": "GTXE2_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA1->GTXE2_LOGIC_OUTS_B2_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT7->GTXE2_LOGIC_OUTS_B9_3": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHANREALIGN->GTXE2_LOGIC_OUTS_B23_9": { + "src_wire": "GTXE2_CHANNEL_RXCHANREALIGN", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX13_8->GTXE2_CHANNEL_RXOSOVRDEN": { + "src_wire": "GTXE2_IMUX13_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOSOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX21_10->GTXE2_CHANNEL_RXDFEAGCOVRDEN": { + "src_wire": "GTXE2_IMUX21_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX2_3->GTXE2_CHANNEL_DRPADDR8": { + "src_wire": "GTXE2_IMUX2_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_GTRXOUTCLK_3->GTXE2_CHANNEL_RXOUTCLK_3": { + "src_wire": "GTXE2_CHANNEL_GTRXOUTCLK_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXOUTCLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX12_4->GTXE2_CHANNEL_TXPHOVRDEN": { + "src_wire": "GTXE2_IMUX12_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPHOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXVALID->GTXE2_LOGIC_OUTS_B20_9": { + "src_wire": "GTXE2_CHANNEL_RXVALID", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT0->GTXE2_LOGIC_OUTS_B9_10": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK7->GTXE2_LOGIC_OUTS_B12_3": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX25_7->GTXE2_CHANNEL_PCSRSVDIN4": { + "src_wire": "GTXE2_IMUX25_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA48->GTXE2_LOGIC_OUTS_B3_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA48", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR5->GTXE2_LOGIC_OUTS_B22_7": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT9->GTXE2_LOGIC_OUTS_B11_9": { + "src_wire": "GTXE2_CHANNEL_TSTOUT9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXBYTEISALIGNED->GTXE2_LOGIC_OUTS_B18_10": { + "src_wire": "GTXE2_CHANNEL_RXBYTEISALIGNED", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO2->GTXE2_LOGIC_OUTS_B2_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXQPISENP->GTXE2_LOGIC_OUTS_B15_1": { + "src_wire": "GTXE2_CHANNEL_RXQPISENP", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCLKCORCNT1->GTXE2_LOGIC_OUTS_B20_5": { + "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT6->GTXE2_LOGIC_OUTS_B13_6": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX32_0->GTXE2_CHANNEL_DRPDI11": { + "src_wire": "GTXE2_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCDRLOCK->GTXE2_LOGIC_OUTS_B17_5": { + "src_wire": "GTXE2_CHANNEL_RXCDRLOCK", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX26_7->GTXE2_CHANNEL_GTRSVD12": { + "src_wire": "GTXE2_IMUX26_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX43_5->GTXE2_CHANNEL_TXDLYUPDOWN": { + "src_wire": "GTXE2_IMUX43_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYUPDOWN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX21_5->GTXE2_CHANNEL_TXDATA43": { + "src_wire": "GTXE2_IMUX21_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA43", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX42_5->GTXE2_CHANNEL_GTRSVD2": { + "src_wire": "GTXE2_IMUX42_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX19_8->GTXE2_CHANNEL_RXDFEVPHOLD": { + "src_wire": "GTXE2_IMUX19_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEVPHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA19->GTXE2_LOGIC_OUTS_B0_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA19", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX1_6->GTXE2_CHANNEL_TXSEQUENCE6": { + "src_wire": "GTXE2_IMUX1_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX9_2->GTXE2_CHANNEL_TXHEADER2": { + "src_wire": "GTXE2_IMUX9_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXHEADER2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX13_10->GTXE2_CHANNEL_RXPRBSCNTRESET": { + "src_wire": "GTXE2_IMUX13_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPRBSCNTRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX41_0->GTXE2_CHANNEL_EYESCANMODE": { + "src_wire": "GTXE2_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_EYESCANMODE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX10_5->GTXE2_CHANNEL_TXUSERRDY": { + "src_wire": "GTXE2_IMUX10_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXUSERRDY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX31_6->GTXE2_CHANNEL_TXCHARDISPMODE4": { + "src_wire": "GTXE2_IMUX31_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX35_5->GTXE2_CHANNEL_TXDEEMPH": { + "src_wire": "GTXE2_IMUX35_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDEEMPH", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXOUTCLKPCS->GTXE2_LOGIC_OUTS_B21_9": { + "src_wire": "GTXE2_CHANNEL_RXOUTCLKPCS", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATAVALID->GTXE2_LOGIC_OUTS_B19_5": { + "src_wire": "GTXE2_CHANNEL_RXDATAVALID", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX23_3->GTXE2_CHANNEL_TXDATA19": { + "src_wire": "GTXE2_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA19", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX15_7->GTXE2_CHANNEL_TX8B10BBYPASS0": { + "src_wire": "GTXE2_IMUX15_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX10_0->GTXE2_CHANNEL_TXCHARDISPVAL7": { + "src_wire": "GTXE2_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX20_0->GTXE2_CHANNEL_TXDATA30": { + "src_wire": "GTXE2_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA30", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCOMMADET->GTXE2_LOGIC_OUTS_B19_7": { + "src_wire": "GTXE2_CHANNEL_RXCOMMADET", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX3_10->GTXE2_CHANNEL_RXLPMLFKLOVRDEN": { + "src_wire": "GTXE2_IMUX3_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL0_5->GTXE2_CHANNEL_GTTXRESET": { + "src_wire": "GTXE2_CTRL0_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTTXRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX30_9->GTXE2_CHANNEL_RXCHBONDMASTER": { + "src_wire": "GTXE2_IMUX30_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDMASTER", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX39_1->GTXE2_CHANNEL_DRPDI4": { + "src_wire": "GTXE2_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK6->GTXE2_LOGIC_OUTS_B12_5": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX14_7->GTXE2_CHANNEL_RXPCSRESET": { + "src_wire": "GTXE2_IMUX14_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPCSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX9_9->GTXE2_CHANNEL_PCSRSVDIN14": { + "src_wire": "GTXE2_IMUX9_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX29_1->GTXE2_CHANNEL_TXCHARISK7": { + "src_wire": "GTXE2_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX39_2->GTXE2_CHANNEL_DRPADDR0": { + "src_wire": "GTXE2_IMUX39_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX11_5->GTXE2_CHANNEL_TXDLYHOLD": { + "src_wire": "GTXE2_IMUX11_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX10_1->GTXE2_CHANNEL_TXPDELECIDLEMODE": { + "src_wire": "GTXE2_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPDELECIDLEMODE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX5_8->GTXE2_CHANNEL_TXOUTCLKSEL0": { + "src_wire": "GTXE2_IMUX5_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX40_9->GTXE2_CHANNEL_TSTIN8": { + "src_wire": "GTXE2_IMUX40_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK2->GTXE2_LOGIC_OUTS_B12_6": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX17_4->GTXE2_CHANNEL_TXDATA13": { + "src_wire": "GTXE2_IMUX17_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX20_5->GTXE2_CHANNEL_TXDATA42": { + "src_wire": "GTXE2_IMUX20_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA42", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CLK0_7->GTXE2_CHANNEL_RXUSRCLK2": { + "src_wire": "GTXE2_CLK0_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXUSRCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX19_2->GTXE2_CHANNEL_TXDATA53": { + "src_wire": "GTXE2_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA53", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX40_10->GTXE2_CHANNEL_TSTIN9": { + "src_wire": "GTXE2_IMUX40_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT3->GTXE2_LOGIC_OUTS_B9_7": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX7_5->GTXE2_CHANNEL_TXDIFFCTRL0": { + "src_wire": "GTXE2_IMUX7_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX12_2->GTXE2_CHANNEL_TXHEADER1": { + "src_wire": "GTXE2_IMUX12_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXHEADER1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT5->GTXE2_LOGIC_OUTS_B11_5": { + "src_wire": "GTXE2_CHANNEL_TSTOUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA45->GTXE2_LOGIC_OUTS_B2_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA45", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX34_9->GTXE2_CHANNEL_RXPCOMMAALIGNEN": { + "src_wire": "GTXE2_IMUX34_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX1_8->GTXE2_CHANNEL_TXOUTCLKSEL2": { + "src_wire": "GTXE2_IMUX1_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX0_8->GTXE2_CHANNEL_PMARSVDIN4": { + "src_wire": "GTXE2_IMUX0_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDO0->GTXE2_LOGIC_OUTS_B16_10": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX23_4->GTXE2_CHANNEL_TXDATA47": { + "src_wire": "GTXE2_IMUX23_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA47", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX45_3->GTXE2_CHANNEL_TXDLYSRESET": { + "src_wire": "GTXE2_IMUX45_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX32_1->GTXE2_CHANNEL_DRPDI15": { + "src_wire": "GTXE2_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX39_4->GTXE2_CHANNEL_TXMARGIN0": { + "src_wire": "GTXE2_IMUX39_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMARGIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA39->GTXE2_LOGIC_OUTS_B0_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA39", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX25_10->GTXE2_CHANNEL_PCSRSVDIN7": { + "src_wire": "GTXE2_IMUX25_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXHEADER1->GTXE2_LOGIC_OUTS_B23_6": { + "src_wire": "GTXE2_CHANNEL_RXHEADER1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX8_5->GTXE2_CHANNEL_TX8B10BBYPASS5": { + "src_wire": "GTXE2_IMUX8_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_CPLLLOCK->GTXE2_LOGIC_OUTS_B14_1": { + "src_wire": "GTXE2_CHANNEL_CPLLLOCK", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO9->GTXE2_LOGIC_OUTS_B4_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX29_10->GTXE2_CHANNEL_RXDFEAGCHOLD": { + "src_wire": "GTXE2_IMUX29_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEAGCHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX2_4->GTXE2_CHANNEL_TXPOSTCURSOR3": { + "src_wire": "GTXE2_IMUX2_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDO2->GTXE2_LOGIC_OUTS_B16_8": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXP_PAD->GTXE2_CHANNEL_RXP": { + "src_wire": "GTXE2_CHANNEL_RXP_PAD", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXP", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CLK0_2->GTXE2_CHANNEL_CPLLLOCKDETCLK": { + "src_wire": "GTXE2_CLK0_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLLOCKDETCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA34->GTXE2_LOGIC_OUTS_B1_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA34", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT3->GTXE2_LOGIC_OUTS_B13_3": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXBUFSTATUS2->GTXE2_LOGIC_OUTS_B17_10": { + "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX14_2->GTXE2_CHANNEL_CPLLREFCLKSEL1": { + "src_wire": "GTXE2_IMUX14_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA50->GTXE2_LOGIC_OUTS_B1_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA50", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX2_9->GTXE2_CHANNEL_RXMCOMMAALIGNEN": { + "src_wire": "GTXE2_IMUX2_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX44_3->GTXE2_CHANNEL_DRPEN": { + "src_wire": "GTXE2_IMUX44_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXHEADER2->GTXE2_LOGIC_OUTS_B17_6": { + "src_wire": "GTXE2_CHANNEL_RXHEADER2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR4->GTXE2_LOGIC_OUTS_B22_9": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDO1->GTXE2_LOGIC_OUTS_B16_9": { + "src_wire": "GTXE2_CHANNEL_RXCHBONDO1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE2->GTXE2_LOGIC_OUTS_B14_6": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX24_9->GTXE2_CHANNEL_TSTIN18": { + "src_wire": "GTXE2_IMUX24_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN18", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL1_8->GTXE2_CHANNEL_RXCDRRESETRSV": { + "src_wire": "GTXE2_CTRL1_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRRESETRSV", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA30->GTXE2_LOGIC_OUTS_B1_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA30", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX22_9->GTXE2_CHANNEL_RXCHBONDI2": { + "src_wire": "GTXE2_IMUX22_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX2_5->GTXE2_CHANNEL_TXDIFFCTRL3": { + "src_wire": "GTXE2_IMUX2_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX43_10->GTXE2_CHANNEL_RXLPMHFHOLD": { + "src_wire": "GTXE2_IMUX43_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMHFHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXBUFSTATUS1->GTXE2_LOGIC_OUTS_B21_2": { + "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX29_6->GTXE2_CHANNEL_TXCHARDISPMODE0": { + "src_wire": "GTXE2_IMUX29_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX6_5->GTXE2_CHANNEL_TXDIFFCTRL1": { + "src_wire": "GTXE2_IMUX6_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX12_8->GTXE2_CHANNEL_RXSLIDE": { + "src_wire": "GTXE2_IMUX12_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXSLIDE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX45_1->GTXE2_CHANNEL_TXQPIWEAKPUP": { + "src_wire": "GTXE2_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXQPIWEAKPUP", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA22->GTXE2_LOGIC_OUTS_B1_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA22", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA23->GTXE2_LOGIC_OUTS_B5_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA23", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX16_0->GTXE2_CHANNEL_TXDATA28": { + "src_wire": "GTXE2_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA28", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX21_4->GTXE2_CHANNEL_TXDATA15": { + "src_wire": "GTXE2_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT6->GTXE2_LOGIC_OUTS_B9_4": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT1->GTXE2_LOGIC_OUTS_B8_9": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX28_10->GTXE2_CHANNEL_RXDFETAP2OVRDEN": { + "src_wire": "GTXE2_IMUX28_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX22_3->GTXE2_CHANNEL_TXDATA18": { + "src_wire": "GTXE2_IMUX22_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA18", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO14->GTXE2_LOGIC_OUTS_B7_1": { + "src_wire": "GTXE2_CHANNEL_DRPDO14", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX15_3->GTXE2_CHANNEL_TX8B10BBYPASS2": { + "src_wire": "GTXE2_IMUX15_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX9_5->GTXE2_CHANNEL_PCSRSVDIN10": { + "src_wire": "GTXE2_IMUX9_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT4->GTXE2_LOGIC_OUTS_B8_6": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX1_7->GTXE2_CHANNEL_PMARSVDIN22": { + "src_wire": "GTXE2_IMUX1_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX33_1->GTXE2_CHANNEL_DRPDI14": { + "src_wire": "GTXE2_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX24_7->GTXE2_CHANNEL_TSTIN16": { + "src_wire": "GTXE2_IMUX24_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN16", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX38_4->GTXE2_CHANNEL_TXMARGIN1": { + "src_wire": "GTXE2_IMUX38_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMARGIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX21_9->GTXE2_CHANNEL_RXDFETAP4OVRDEN": { + "src_wire": "GTXE2_IMUX21_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX3_3->GTXE2_CHANNEL_TXSTARTSEQ": { + "src_wire": "GTXE2_IMUX3_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXSTARTSEQ", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX22_0->GTXE2_CHANNEL_TXDATA62": { + "src_wire": "GTXE2_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA62", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXHEADERVALID->GTXE2_LOGIC_OUTS_B23_7": { + "src_wire": "GTXE2_CHANNEL_RXHEADERVALID", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX31_7->GTXE2_CHANNEL_TXCHARISK0": { + "src_wire": "GTXE2_IMUX31_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA28->GTXE2_LOGIC_OUTS_B3_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA28", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT15->GTXE2_LOGIC_OUTS_B16_1": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT15", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX42_3->GTXE2_CHANNEL_GTRSVD0": { + "src_wire": "GTXE2_IMUX42_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHANISALIGNED->GTXE2_LOGIC_OUTS_B18_9": { + "src_wire": "GTXE2_CHANNEL_RXCHANISALIGNED", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX20_1->GTXE2_CHANNEL_TXDATA58": { + "src_wire": "GTXE2_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA58", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX40_2->GTXE2_CHANNEL_TSTIN1": { + "src_wire": "GTXE2_IMUX40_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX28_1->GTXE2_CHANNEL_TXCOMSAS": { + "src_wire": "GTXE2_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCOMSAS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX21_8->GTXE2_CHANNEL_RXDFEXYDOVRDEN": { + "src_wire": "GTXE2_IMUX21_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX5_1->GTXE2_CHANNEL_TXQPIBIASEN": { + "src_wire": "GTXE2_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXQPIBIASEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX16_1->GTXE2_CHANNEL_TXDATA56": { + "src_wire": "GTXE2_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA56", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX18_6->GTXE2_CHANNEL_TXDATA36": { + "src_wire": "GTXE2_IMUX18_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA36", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO0->GTXE2_LOGIC_OUTS_B0_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX29_9->GTXE2_CHANNEL_RXDFETAP5HOLD": { + "src_wire": "GTXE2_IMUX29_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP5HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA14->GTXE2_LOGIC_OUTS_B1_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA14", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PHYSTATUS->GTXE2_LOGIC_OUTS_B10_9": { + "src_wire": "GTXE2_CHANNEL_PHYSTATUS", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B23_3": { + "src_wire": "GTXE2_CHANNEL_TXOUTCLKFABRIC", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA38->GTXE2_LOGIC_OUTS_B4_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA38", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B4_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHMONITOR0->GTXE2_LOGIC_OUTS_B5_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX5_9->GTXE2_CHANNEL_PMARSVDIN0": { + "src_wire": "GTXE2_IMUX5_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_3": { + "src_wire": "GTXE2_CHANNEL_TXPHALIGNDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA61->GTXE2_LOGIC_OUTS_B2_3": { + "src_wire": "GTXE2_CHANNEL_RXDATA61", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX0_3->GTXE2_CHANNEL_TXMAINCURSOR3": { + "src_wire": "GTXE2_IMUX0_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK1->GTXE2_LOGIC_OUTS_B12_8": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT14->GTXE2_LOGIC_OUTS_B16_0": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT14", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX38_3->GTXE2_CHANNEL_DRPADDR5": { + "src_wire": "GTXE2_IMUX38_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CLK1_7->GTXE2_CHANNEL_CLKRSVD2": { + "src_wire": "GTXE2_CLK1_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX1_2->GTXE2_CHANNEL_RXMONITORSEL1": { + "src_wire": "GTXE2_IMUX1_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT1->GTXE2_LOGIC_OUTS_B9_9": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B17_3": { + "src_wire": "GTXE2_CHANNEL_TXDLYSRESETDONE", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE6->GTXE2_LOGIC_OUTS_B14_5": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX18_4->GTXE2_CHANNEL_TXDATA44": { + "src_wire": "GTXE2_IMUX18_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA44", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX37_8->GTXE2_CHANNEL_RXDFEXYDHOLD": { + "src_wire": "GTXE2_IMUX37_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEXYDHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHMONITOR3->GTXE2_LOGIC_OUTS_B3_2": { + "src_wire": "GTXE2_CHANNEL_RXPHMONITOR3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA3->GTXE2_LOGIC_OUTS_B15_3": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX16_4->GTXE2_CHANNEL_TXDATA12": { + "src_wire": "GTXE2_IMUX16_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX46_9->GTXE2_CHANNEL_LOOPBACK1": { + "src_wire": "GTXE2_IMUX46_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_LOOPBACK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX31_5->GTXE2_CHANNEL_TXCHARISK1": { + "src_wire": "GTXE2_IMUX31_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPRBSERR->GTXE2_LOGIC_OUTS_B20_6": { + "src_wire": "GTXE2_CHANNEL_RXPRBSERR", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX18_7->GTXE2_CHANNEL_TXDATA0": { + "src_wire": "GTXE2_IMUX18_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX24_5->GTXE2_CHANNEL_TSTIN14": { + "src_wire": "GTXE2_IMUX24_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX44_1->GTXE2_CHANNEL_TXCOMINIT": { + "src_wire": "GTXE2_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCOMINIT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX17_0->GTXE2_CHANNEL_TXDATA29": { + "src_wire": "GTXE2_IMUX17_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA29", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA5->GTXE2_LOGIC_OUTS_B15_8": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX20_2->GTXE2_CHANNEL_TXDATA22": { + "src_wire": "GTXE2_IMUX20_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA17->GTXE2_LOGIC_OUTS_B2_6": { + "src_wire": "GTXE2_CHANNEL_RXDATA17", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXOUTCLKPCS->GTXE2_LOGIC_OUTS_B17_4": { + "src_wire": "GTXE2_CHANNEL_TXOUTCLKPCS", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX47_9->GTXE2_CHANNEL_LOOPBACK2": { + "src_wire": "GTXE2_IMUX47_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_LOOPBACK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX39_0->GTXE2_CHANNEL_DRPDI0": { + "src_wire": "GTXE2_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPDI0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX26_8->GTXE2_CHANNEL_GTRSVD13": { + "src_wire": "GTXE2_IMUX26_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B17_9": { + "src_wire": "GTXE2_CHANNEL_RXOUTCLKFABRIC", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHSLIPMONITOR4->GTXE2_LOGIC_OUTS_B16_3": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA42->GTXE2_LOGIC_OUTS_B1_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA42", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B1_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA0->GTXE2_LOGIC_OUTS_B15_9": { + "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX14_5->GTXE2_CHANNEL_TXDLYEN": { + "src_wire": "GTXE2_IMUX14_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX23_6->GTXE2_CHANNEL_TXDATA39": { + "src_wire": "GTXE2_IMUX23_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA39", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX11_10->GTXE2_CHANNEL_RXLPMLFHOLD": { + "src_wire": "GTXE2_IMUX11_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXLPMLFHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX44_9->GTXE2_CHANNEL_RXCOMMADETEN": { + "src_wire": "GTXE2_IMUX44_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCOMMADETEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX32_8->GTXE2_CHANNEL_RXDLYBYPASS": { + "src_wire": "GTXE2_IMUX32_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYBYPASS", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX38_10->GTXE2_CHANNEL_PCSRSVDIN22": { + "src_wire": "GTXE2_IMUX38_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CLK1_6->GTXE2_CHANNEL_GTGREFCLK": { + "src_wire": "GTXE2_CLK1_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTGREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX35_4->GTXE2_CHANNEL_TXMARGIN2": { + "src_wire": "GTXE2_IMUX35_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMARGIN2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX15_1->GTXE2_CHANNEL_TX8B10BBYPASS3": { + "src_wire": "GTXE2_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX18_2->GTXE2_CHANNEL_TXDATA52": { + "src_wire": "GTXE2_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA52", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX22_4->GTXE2_CHANNEL_TXDATA46": { + "src_wire": "GTXE2_IMUX22_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA46", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX30_8->GTXE2_CHANNEL_RXCDRHOLD": { + "src_wire": "GTXE2_IMUX30_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA59->GTXE2_LOGIC_OUTS_B5_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA59", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR1->GTXE2_LOGIC_OUTS_B22_8": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX13_2->GTXE2_CHANNEL_TXHEADER0": { + "src_wire": "GTXE2_IMUX13_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXHEADER0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX44_8->GTXE2_CHANNEL_RXUSERRDY": { + "src_wire": "GTXE2_IMUX44_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXUSERRDY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX22_10->GTXE2_CHANNEL_RXCHBONDLEVEL2": { + "src_wire": "GTXE2_IMUX22_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX8_0->GTXE2_CHANNEL_TXCHARDISPVAL3": { + "src_wire": "GTXE2_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX31_4->GTXE2_CHANNEL_TXCHARDISPMODE5": { + "src_wire": "GTXE2_IMUX31_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA5->GTXE2_LOGIC_OUTS_B7_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE1->GTXE2_LOGIC_OUTS_B14_8": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX17_1->GTXE2_CHANNEL_TXDATA57": { + "src_wire": "GTXE2_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA57", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CLK1_5->GTXE2_CHANNEL_CLKRSVD1": { + "src_wire": "GTXE2_CLK1_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CLKRSVD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX5_3->GTXE2_CHANNEL_TXMAINCURSOR0": { + "src_wire": "GTXE2_IMUX5_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA8->GTXE2_LOGIC_OUTS_B6_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX9_6->GTXE2_CHANNEL_PCSRSVDIN11": { + "src_wire": "GTXE2_IMUX9_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX14_8->GTXE2_CHANNEL_RXCDROVRDEN": { + "src_wire": "GTXE2_IMUX14_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDROVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX21_1->GTXE2_CHANNEL_TXDATA59": { + "src_wire": "GTXE2_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA59", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX26_6->GTXE2_CHANNEL_GTRSVD11": { + "src_wire": "GTXE2_IMUX26_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCLKCORCNT0->GTXE2_LOGIC_OUTS_B18_5": { + "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX30_7->GTXE2_CHANNEL_TXPCSRESET": { + "src_wire": "GTXE2_IMUX30_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPCSRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX18_9->GTXE2_CHANNEL_RXCHBONDI0": { + "src_wire": "GTXE2_IMUX18_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCHBONDI0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX34_2->GTXE2_CHANNEL_DRPADDR3": { + "src_wire": "GTXE2_IMUX34_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK3->GTXE2_LOGIC_OUTS_B12_4": { + "src_wire": "GTXE2_CHANNEL_RXCHARISK3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX13_1->GTXE2_CHANNEL_TXQPISTRONGPDOWN": { + "src_wire": "GTXE2_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA52->GTXE2_LOGIC_OUTS_B6_5": { + "src_wire": "GTXE2_CHANNEL_RXDATA52", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA13->GTXE2_LOGIC_OUTS_B7_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA13", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHSLIPMONITOR0->GTXE2_LOGIC_OUTS_B0_2": { + "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B0_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX0_2->GTXE2_CHANNEL_TX8B10BEN": { + "src_wire": "GTXE2_IMUX0_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TX8B10BEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX22_7->GTXE2_CHANNEL_TXDATA2": { + "src_wire": "GTXE2_IMUX22_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA24->GTXE2_LOGIC_OUTS_B6_4": { + "src_wire": "GTXE2_CHANNEL_RXDATA24", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B6_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX23_0->GTXE2_CHANNEL_TXDATA63": { + "src_wire": "GTXE2_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA63", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX25_3->GTXE2_CHANNEL_PCSRSVDIN0": { + "src_wire": "GTXE2_IMUX25_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX27_7->GTXE2_CHANNEL_RXPOLARITY": { + "src_wire": "GTXE2_IMUX27_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPOLARITY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT1->GTXE2_LOGIC_OUTS_B11_1": { + "src_wire": "GTXE2_CHANNEL_TSTOUT1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXGEARBOXREADY->GTXE2_LOGIC_OUTS_B23_4": { + "src_wire": "GTXE2_CHANNEL_TXGEARBOXREADY", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX5_7->GTXE2_CHANNEL_PMARSVDIN20": { + "src_wire": "GTXE2_IMUX5_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PMARSVDIN20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX11_8->GTXE2_CHANNEL_RXDFEVSEN": { + "src_wire": "GTXE2_IMUX11_8", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFEVSEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA4->GTXE2_LOGIC_OUTS_B3_9": { + "src_wire": "GTXE2_CHANNEL_RXDATA4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B3_9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_QPLLCLK->GTXE2_CHANNEL_GTQPLLCLK": { + "src_wire": "GTXE2_CHANNEL_QPLLCLK", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTQPLLCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX12_5->GTXE2_CHANNEL_TXDLYOVRDEN": { + "src_wire": "GTXE2_IMUX12_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDLYOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX26_10->GTXE2_CHANNEL_GTRSVD15": { + "src_wire": "GTXE2_IMUX26_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX36_10->GTXE2_CHANNEL_RXDFETAP3HOLD": { + "src_wire": "GTXE2_IMUX36_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP3HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA33->GTXE2_LOGIC_OUTS_B7_10": { + "src_wire": "GTXE2_CHANNEL_RXDATA33", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL0_3->GTXE2_CHANNEL_CPLLRESET": { + "src_wire": "GTXE2_CTRL0_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_CPLLRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX17_2->GTXE2_CHANNEL_TXDATA21": { + "src_wire": "GTXE2_IMUX17_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT2->GTXE2_LOGIC_OUTS_B8_8": { + "src_wire": "GTXE2_CHANNEL_RXMONITOROUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR3->GTXE2_LOGIC_OUTS_B22_4": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX3_4->GTXE2_CHANNEL_TXPOSTCURSOR2": { + "src_wire": "GTXE2_IMUX3_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX38_7->GTXE2_CHANNEL_RXDLYOVRDEN": { + "src_wire": "GTXE2_IMUX38_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDLYOVRDEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX20_7->GTXE2_CHANNEL_TXDATA33": { + "src_wire": "GTXE2_IMUX20_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA33", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX42_7->GTXE2_CHANNEL_GTRSVD4": { + "src_wire": "GTXE2_IMUX42_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTRSVD4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_SOUTHREFCLK1->GTXE2_CHANNEL_GTSOUTHREFCLK1": { + "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX11_6->GTXE2_CHANNEL_RXRATE2": { + "src_wire": "GTXE2_IMUX11_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXRATE2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXSTATUS1->GTXE2_LOGIC_OUTS_B17_8": { + "src_wire": "GTXE2_CHANNEL_RXSTATUS1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CTRL1_9->GTXE2_CHANNEL_RXCDRRESET": { + "src_wire": "GTXE2_CTRL1_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXCDRRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX15_6->GTXE2_CHANNEL_RXRATE0": { + "src_wire": "GTXE2_IMUX15_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXRATE0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX24_3->GTXE2_CHANNEL_TSTIN12": { + "src_wire": "GTXE2_IMUX24_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX41_6->GTXE2_CHANNEL_RXPHALIGNEN": { + "src_wire": "GTXE2_IMUX41_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXPHALIGNEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX8_2->GTXE2_CHANNEL_TXCHARDISPVAL2": { + "src_wire": "GTXE2_IMUX8_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_REFCLK1->GTXE2_CHANNEL_GTREFCLK1": { + "src_wire": "GTXE2_CHANNEL_REFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_GTREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX29_5->GTXE2_CHANNEL_TXCHARISK5": { + "src_wire": "GTXE2_IMUX29_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXCHARISK5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXN->GTXE2_CHANNEL_TXN_PAD": { + "src_wire": "GTXE2_CHANNEL_TXN", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXN_PAD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT2->GTXE2_LOGIC_OUTS_B9_8": { + "src_wire": "GTXE2_CHANNEL_DMONITOROUT2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX35_9->GTXE2_CHANNEL_RXDFELFHOLD": { + "src_wire": "GTXE2_IMUX35_9", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFELFHOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR7->GTXE2_LOGIC_OUTS_B22_3": { + "src_wire": "GTXE2_CHANNEL_RXDISPERR7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT5->GTXE2_LOGIC_OUTS_B13_5": { + "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE7->GTXE2_LOGIC_OUTS_B14_3": { + "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX3_6->GTXE2_CHANNEL_TXPRECURSOR2": { + "src_wire": "GTXE2_IMUX3_6", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX9_7->GTXE2_CHANNEL_PCSRSVDIN12": { + "src_wire": "GTXE2_IMUX9_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX24_2->GTXE2_CHANNEL_TSTIN11": { + "src_wire": "GTXE2_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TSTIN11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX44_10->GTXE2_CHANNEL_RXDFETAP2HOLD": { + "src_wire": "GTXE2_IMUX44_10", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_RXDFETAP2HOLD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX23_7->GTXE2_CHANNEL_TXDATA3": { + "src_wire": "GTXE2_IMUX23_7", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX23_5->GTXE2_CHANNEL_TXDATA11": { + "src_wire": "GTXE2_IMUX23_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_TXP->GTXE2_CHANNEL_TXP_PAD": { + "src_wire": "GTXE2_CHANNEL_TXP", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXP_PAD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA15->GTXE2_LOGIC_OUTS_B5_7": { + "src_wire": "GTXE2_CHANNEL_RXDATA15", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B5_7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX35_2->GTXE2_CHANNEL_DRPADDR2": { + "src_wire": "GTXE2_IMUX35_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_DRPADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA9->GTXE2_LOGIC_OUTS_B2_8": { + "src_wire": "GTXE2_CHANNEL_RXDATA9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX30_3->GTXE2_CHANNEL_TXPOLARITY": { + "src_wire": "GTXE2_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXPOLARITY", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_IMUX18_0->GTXE2_CHANNEL_TXDATA60": { + "src_wire": "GTXE2_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_CHANNEL_TXDATA60", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO6->GTXE2_LOGIC_OUTS_B7_0": { + "src_wire": "GTXE2_CHANNEL_DRPDO6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B7_0", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_GTX_COMMON.json b/kintex7/tile_type_GTX_COMMON.json new file mode 100644 index 0000000..81e3d11 --- /dev/null +++ b/kintex7/tile_type_GTX_COMMON.json @@ -0,0 +1,1873 @@ +{ + "tile_type": "GTX_COMMON", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "GTXE2_COMMON", + "type": "GTXE2_COMMON", + "site_pins": { + "PMARSVD1": "GTXE2_COMMON_PMARSVD1", + "PMARSVD7": "GTXE2_COMMON_PMARSVD7", + "DRPDO8": "GTXE2_COMMON_DRPDO8", + "QPLLRSVD16": "GTXE2_COMMON_QPLLRSVD16", + "QPLLRSVD22": "GTXE2_COMMON_QPLLRSVD22", + "DRPDO2": "GTXE2_COMMON_DRPDO2", + "DRPDI1": "GTXE2_COMMON_DRPDI1", + "QDPMASCANRSTEN": "GTXE2_COMMON_QDPMASCANRSTEN", + "QPLLRSVD12": "GTXE2_COMMON_QPLLRSVD12", + "QPLLLOCKDETCLK": "GTXE2_COMMON_QPLLLOCKDETCLK", + "QPLLREFCLKSEL1": "GTXE2_COMMON_QPLLREFCLKSEL1", + "DRPADDR1": "GTXE2_COMMON_DRPADDR1", + "BGRCALOVRD1": "GTXE2_COMMON_BGRCALOVRD1", + "DRPEN": "GTXE2_COMMON_DRPEN", + "DRPDI4": "GTXE2_COMMON_DRPDI4", + "GTREFCLK1": "GTXE2_COMMON_GTREFCLK1", + "RCALENB": "GTXE2_COMMON_RCALENB", + "QPLLRSVD110": "GTXE2_COMMON_QPLLRSVD110", + "QPLLRSVD10": "GTXE2_COMMON_QPLLRSVD10", + "DRPDO6": "GTXE2_COMMON_DRPDO6", + "DRPADDR7": "GTXE2_COMMON_DRPADDR7", + "PMARSVD6": "GTXE2_COMMON_PMARSVD6", + "REFCLKOUTMONITOR": "GTXE2_COMMON_REFCLKOUTMONITOR", + "QPLLRSVD17": "GTXE2_COMMON_QPLLRSVD17", + "QPLLCLKSPARE0": "GTXE2_COMMON_QPLLCLKSPARE0", + "DRPDO9": "GTXE2_COMMON_DRPDO9", + "QPLLDMONITOR0": "GTXE2_COMMON_QPLLDMONITOR0", + "DRPDI2": "GTXE2_COMMON_DRPDI2", + "DRPDO0": "GTXE2_COMMON_DRPDO0", + "DRPWE": "GTXE2_COMMON_DRPWE", + "BGBYPASSB": "GTXE2_COMMON_BGBYPASSB", + "DRPDO7": "GTXE2_COMMON_DRPDO7", + "DRPDI14": "GTXE2_COMMON_DRPDI14", + "QPLLRSVD11": "GTXE2_COMMON_QPLLRSVD11", + "QPLLRSVD13": "GTXE2_COMMON_QPLLRSVD13", + "QPLLDMONITOR5": "GTXE2_COMMON_QPLLDMONITOR5", + "DRPDI15": "GTXE2_COMMON_DRPDI15", + "PMASCANIN4": "GTXE2_COMMON_PMASCANIN4", + "QPLLRSVD23": "GTXE2_COMMON_QPLLRSVD23", + "QPLLRSVD115": "GTXE2_COMMON_QPLLRSVD115", + "QPLLREFCLKLOST": "GTXE2_COMMON_QPLLREFCLKLOST", + "QPLLRSVD15": "GTXE2_COMMON_QPLLRSVD15", + "QPLLRSVD14": "GTXE2_COMMON_QPLLRSVD14", + "PMASCANIN1": "GTXE2_COMMON_PMASCANIN1", + "QPLLRSVD113": "GTXE2_COMMON_QPLLRSVD113", + "PMASCANOUT3": "GTXE2_COMMON_PMASCANOUT3", + "GTSOUTHREFCLK0": "GTXE2_COMMON_GTSOUTHREFCLK0", + "QPLLRSVD18": "GTXE2_COMMON_QPLLRSVD18", + "DRPDI12": "GTXE2_COMMON_DRPDI12", + "QPLLPD": "GTXE2_COMMON_QPLLPD", + "QPLLDMONITOR1": "GTXE2_COMMON_QPLLDMONITOR1", + "PMASCANOUT4": "GTXE2_COMMON_PMASCANOUT4", + "BGMONITORENB": "GTXE2_COMMON_BGMONITORENB", + "DRPDO1": "GTXE2_COMMON_DRPDO1", + "DRPDI9": "GTXE2_COMMON_DRPDI9", + "QPLLFBCLKLOST": "GTXE2_COMMON_QPLLFBCLKLOST", + "DRPDO5": "GTXE2_COMMON_DRPDO5", + "PMASCANIN0": "GTXE2_COMMON_PMASCANIN0", + "DRPDI5": "GTXE2_COMMON_DRPDI5", + "QPLLRSVD114": "GTXE2_COMMON_QPLLRSVD114", + "PMARSVD3": "GTXE2_COMMON_PMARSVD3", + "DRPDO12": "GTXE2_COMMON_DRPDO12", + "GTNORTHREFCLK0": "GTXE2_COMMON_GTNORTHREFCLK0", + "PMASCANCLK0": "GTXE2_COMMON_PMASCANCLK0", + "DRPDO15": "GTXE2_COMMON_DRPDO15", + "QPLLDMONITOR7": "GTXE2_COMMON_QPLLDMONITOR7", + "DRPDO13": "GTXE2_COMMON_DRPDO13", + "BGRCALOVRD4": "GTXE2_COMMON_BGRCALOVRD4", + "QPLLDMONITOR4": "GTXE2_COMMON_QPLLDMONITOR4", + "DRPDO11": "GTXE2_COMMON_DRPDO11", + "QPLLRSVD19": "GTXE2_COMMON_QPLLRSVD19", + "DRPADDR6": "GTXE2_COMMON_DRPADDR6", + "PMASCANIN2": "GTXE2_COMMON_PMASCANIN2", + "DRPDI6": "GTXE2_COMMON_DRPDI6", + "QPLLRESET": "GTXE2_COMMON_QPLLRESET", + "DRPDO14": "GTXE2_COMMON_DRPDO14", + "DRPCLK": "GTXE2_COMMON_DRPCLK", + "DRPDI7": "GTXE2_COMMON_DRPDI7", + "DRPDO3": "GTXE2_COMMON_DRPDO3", + "DRPADDR4": "GTXE2_COMMON_DRPADDR4", + "DRPADDR2": "GTXE2_COMMON_DRPADDR2", + "QPLLLOCKEN": "GTXE2_COMMON_QPLLLOCKEN", + "QPLLDMONITOR3": "GTXE2_COMMON_QPLLDMONITOR3", + "QPLLRSVD21": "GTXE2_COMMON_QPLLRSVD21", + "QPLLCLKSPARE1": "GTXE2_COMMON_QPLLCLKSPARE1", + "PMASCANIN3": "GTXE2_COMMON_PMASCANIN3", + "DRPADDR5": "GTXE2_COMMON_DRPADDR5", + "QPLLOUTRESET": "GTXE2_COMMON_QPLLOUTRESET", + "QPLLDMONITOR6": "GTXE2_COMMON_QPLLDMONITOR6", + "PMARSVD0": "GTXE2_COMMON_PMARSVD0", + "BGRCALOVRD3": "GTXE2_COMMON_BGRCALOVRD3", + "QPLLRSVD24": "GTXE2_COMMON_QPLLRSVD24", + "GTNORTHREFCLK1": "GTXE2_COMMON_GTNORTHREFCLK1", + "QPLLLOCK": "GTXE2_COMMON_QPLLLOCK", + "DRPDO10": "GTXE2_COMMON_DRPDO10", + "PMARSVD4": "GTXE2_COMMON_PMARSVD4", + "DRPDI3": "GTXE2_COMMON_DRPDI3", + "DRPDI11": "GTXE2_COMMON_DRPDI11", + "DRPADDR3": "GTXE2_COMMON_DRPADDR3", + "PMASCANOUT0": "GTXE2_COMMON_PMASCANOUT0", + "DRPDI13": "GTXE2_COMMON_DRPDI13", + "QPLLOUTCLK": "GTXE2_COMMON_GTQPLLOUTCLK", + "DRPADDR0": "GTXE2_COMMON_DRPADDR0", + "QPLLRSVD111": "GTXE2_COMMON_QPLLRSVD111", + "BGRCALOVRD2": "GTXE2_COMMON_BGRCALOVRD2", + "QPLLRSVD20": "GTXE2_COMMON_QPLLRSVD20", + "QDPMASCANMODEB": "GTXE2_COMMON_QDPMASCANMODEB", + "PMARSVD2": "GTXE2_COMMON_PMARSVD2", + "BGRCALOVRD0": "GTXE2_COMMON_BGRCALOVRD0", + "BGPDB": "GTXE2_COMMON_BGPDB", + "PMARSVD5": "GTXE2_COMMON_PMARSVD5", + "QPLLREFCLKSEL2": "GTXE2_COMMON_QPLLREFCLKSEL2", + "PMASCANOUT1": "GTXE2_COMMON_PMASCANOUT1", + "GTSOUTHREFCLK1": "GTXE2_COMMON_GTSOUTHREFCLK1", + "DRPDI10": "GTXE2_COMMON_DRPDI10", + "DRPRDY": "GTXE2_COMMON_DRPRDY", + "DRPDO4": "GTXE2_COMMON_DRPDO4", + "GTGREFCLK": "GTXE2_COMMON_GTGREFCLK", + "QPLLREFCLKSEL0": "GTXE2_COMMON_QPLLREFCLKSEL0", + "PMASCANOUT2": "GTXE2_COMMON_PMASCANOUT2", + "DRPDI0": "GTXE2_COMMON_DRPDI0", + "QPLLOUTREFCLK": "GTXE2_COMMON_GTQPLLOUTREFCLK", + "QPLLRSVD112": "GTXE2_COMMON_QPLLRSVD112", + "DRPDI8": "GTXE2_COMMON_DRPDI8", + "QPLLDMONITOR2": "GTXE2_COMMON_QPLLDMONITOR2", + "PMASCANENB": "GTXE2_COMMON_PMASCANENB", + "PMASCANCLK1": "GTXE2_COMMON_PMASCANCLK1", + "GTREFCLK0": "GTXE2_COMMON_GTREFCLK0" + }, + "x_coord": 0 + }, + { + "y_coord": 38, + "name": "X0Y38", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "IBUFDS_GTE2_0_IB" + }, + "x_coord": 0 + }, + { + "y_coord": 37, + "name": "X0Y37", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "IBUFDS_GTE2_0_I" + }, + "x_coord": 0 + }, + { + "y_coord": 40, + "name": "X0Y40", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "IBUFDS_GTE2_1_IB" + }, + "x_coord": 0 + }, + { + "y_coord": 39, + "name": "X0Y39", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "IBUFDS_GTE2_1_I" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "IBUFDS_GTE2", + "type": "IBUFDS_GTE2", + "site_pins": { + "CEB": "IBUFDS_GTE2_0_CEB", + "CLKTESTSIG": "IBUFDS_GTE2_0_CLKTESTSIG", + "IB": "IBUFDS_GTE2_0_IB_SEG", + "O": "IBUFDS_GTE2_0_O", + "I": "IBUFDS_GTE2_0_I_SEG", + "ODIV2": "IBUFDS_GTE2_0_ODIV2" + }, + "x_coord": 0 + }, + { + "y_coord": 2, + "name": "X0Y2", + "prefix": "IBUFDS_GTE2", + "type": "IBUFDS_GTE2", + "site_pins": { + "CEB": "IBUFDS_GTE2_1_CEB", + "CLKTESTSIG": "IBUFDS_GTE2_1_CLKTESTSIG", + "IB": "IBUFDS_GTE2_1_IB_SEG", + "O": "IBUFDS_GTE2_1_O", + "I": "IBUFDS_GTE2_1_I_SEG", + "ODIV2": "IBUFDS_GTE2_1_ODIV2" + }, + "x_coord": 0 + } + ], + "wires": [ + "GTXE2_COMMON_DRPDO11", + "GTXE2_IMUX42_1", + "GTXE2_IMUX29_3", + "GTXE2_LOGIC_OUTS_B21_5", + "GTXE2_LOGIC_OUTS_B7_0", + "GTXE2_CLK0_4", + "GTXE2_LOGIC_OUTS_B18_4", + "GTXE2_LOGIC_OUTS_B23_4", + "GTXE2_IMUX42_5", + "GTXE2_IMUX23_5", + "GTXE2_LOGIC_OUTS_B19_1", + "GTXE2_LOGIC_OUTS_B7_5", + "GTXE2_COMMON_QPLLRSVD16", + "GTXE2_COMMON_QDPMASCANMODEB", + "GTXE2_FAN5_4", + "GTXE2_COMMON_DRPDI11", + "GTXE2_IMUX47_5", + "GTXE2_LOGIC_OUTS_B9_4", + "GTXE2_IMUX7_3", + "GTXE2_IMUX27_3", + "GTXE2_IMUX46_0", + "GTXE2_LOGIC_OUTS_B19_4", + "GTXE2_IMUX27_0", + "GTXE2_BYP2_3", + "GTXE2_BYP2_5", + "GTXE2_LOGIC_OUTS_B22_0", + "GTXE2_IMUX4_4", + "GTXE2_COMMON_RCALENB", + "GTXE2_COMMON_QPLLRSVD113", + "GTXE2_COMMON_BGPDB", + "GTXE2_IMUX6_0", + "GTXE2_LOGIC_OUTS_B14_0", + "GTXE2_CTRL1_3", + "GTXE2_IMUX25_4", + "GTXE2_COMMON_RXOUTCLK_2", + "GTXE2_IMUX3_2", + "GTXE2_IMUX18_5", + "GTXE2_IMUX32_5", + "GTXE2_IMUX30_4", + "GTXE2_LOGIC_OUTS_B17_5", + "GTXE2_IMUX26_0", + "GTXE2_IMUX25_2", + "GTXE2_CLK0_3", + "GTXE2_IMUX9_3", + "GTXE2_IMUX32_1", + "GTXE2_IMUX9_2", + "GTXE2_IMUX31_0", + "GTXE2_LOGIC_OUTS_B19_2", + "GTXE2_IMUX28_1", + "GTXE2_COMMON_QPLLRSVD112", + "GTXE2_LOGIC_OUTS_B4_1", + "GTXE2_COMMON_QPLLRSVD22", + "GTXE2_COMMON_QPLLLOCKDETCLK", + "GTXE2_BYP0_5", + "GTXE2_FAN5_0", + "GTXE2_CTRL0_4", + "GTXE2_COMMON_SOUTHREFCLK1", + "GTXE2_IMUX7_2", + "GTXE2_COMMON_DRPDI5", + "GTXE2_COMMON_REFCLK0", + "GTXE2_IMUX40_4", + "GTXE2_LOGIC_OUTS_B10_5", + "GTXE2_LOGIC_OUTS_B2_1", + "GTXE2_LOGIC_OUTS_B23_1", + "GTXE2_IMUX16_5", + "GTXE2_LOGIC_OUTS_B1_5", + "GTXE2_COMMON_REFCLK1", + "GTXE2_IMUX43_0", + "GTXE2_BYP2_4", + "GTXE2_COMMON_PMARSVD5", + "GTXE2_COMMON_QPLLDMONITOR3", + "GTXE2_BYP4_5", + "GTXE2_CLK1_0", + "GTXE2_LOGIC_OUTS_B1_4", + "GTXE2_COMMON_PMASCANIN4", + "GTXE2_IMUX14_0", + "GTXE2_BYP7_0", + "GTXE2_COMMON_QPLLLOCK", + "GTXE2_COMMON_DRPWE", + "GTXE2_LOGIC_OUTS_B12_4", + "GTXE2_IMUX17_0", + "GTXE2_COMMON_PMASCANENB", + "GTXE2_IMUX11_1", + "GTXE2_LOGIC_OUTS_B1_3", + "GTXE2_COMMON_PMARSVD6", + "GTXE2_IMUX34_3", + "IBUFDS_GTE2_0_I_SEG", + "GTXE2_IMUX14_4", + "GTXE2_IMUX10_4", + "GTXE2_FAN4_4", + "GTXE2_FAN5_3", + "GTXE2_COMMON_DRPDI3", + "GTXE2_IMUX37_0", + "GTXE2_BYP1_4", + "GTXE2_IMUX1_3", + "IBUFDS_GTE2_1_ODIV2", + "GTXE2_IMUX1_5", + "GTXE2_IMUX28_0", + "GTXE2_COMMON_DRPDI15", + "GTXE2_IMUX19_2", + "GTXE2_COMMON_DRPDI2", + "GTXE2_BYP1_5", + "IBUFDS_GTE2_0_I", + "GTXE2_BYP1_2", + "GTXE2_COMMON_DRPADDR5", + "GTXE2_IMUX6_2", + "GTXE2_LOGIC_OUTS_B23_5", + "GTXE2_COMMON_DRPDI10", + "GTXE2_COMMON_QPLLCLKSPARE1", + "GTXE2_IMUX16_3", + "GTXE2_IMUX35_4", + "GTXE2_LOGIC_OUTS_B16_1", + "GTXE2_COMMON_MGT_CLK7", + "GTXE2_LOGIC_OUTS_B14_3", + "GTXE2_LOGIC_OUTS_B17_1", + "GTXE2_IMUX37_2", + "GTXE2_IMUX6_5", + "GTXE2_FAN7_0", + "GTXE2_BYP5_2", + "GTXE2_IMUX45_0", + "GTXE2_COMMON_DRPDI9", + "GTXE2_COMMON_DRPADDR7", + "GTXE2_IMUX46_1", + "GTXE2_IMUX30_2", + "GTXE2_BYP5_5", + "GTXE2_IMUX22_4", + "GTXE2_IMUX46_4", + "GTXE2_BYP2_0", + "GTXE2_IMUX35_1", + "GTXE2_COMMON_DRPDO15", + "GTXE2_IMUX15_0", + "GTXE2_BYP5_3", + "GTXE2_IMUX45_4", + "GTXE2_COMMON_GTQPLLOUTCLK", + "GTXE2_LOGIC_OUTS_B3_0", + "GTXE2_COMMON_QPLLDMONITOR2", + "GTXE2_BYP1_1", + "GTXE2_LOGIC_OUTS_B1_1", + "GTXE2_IMUX42_3", + "GTXE2_BYP1_3", + "GTXE2_LOGIC_OUTS_B3_1", + "GTXE2_CTRL1_0", + "GTXE2_IMUX24_4", + "GTXE2_IMUX47_2", + "GTXE2_FAN1_5", + "GTXE2_IMUX0_3", + "GTXE2_IMUX44_0", + "GTXE2_CTRL0_5", + "GTXE2_LOGIC_OUTS_B5_3", + "GTXE2_BYP2_1", + "GTXE2_LOGIC_OUTS_B21_3", + "GTXE2_IMUX39_5", + "GTXE2_IMUX22_1", + "GTXE2_IMUX35_2", + "GTXE2_IMUX10_5", + "GTXE2_IMUX44_2", + "GTXE2_LOGIC_OUTS_B11_4", + "GTXE2_IMUX23_0", + "GTXE2_IMUX21_1", + "GTXE2_COMMON_DRPDO12", + "GTXE2_IMUX32_3", + "GTXE2_COMMON_DRPADDR2", + "GTXE2_FAN7_3", + "GTXE2_COMMON_QPLLREFCLKSEL1", + "GTXE2_IMUX42_2", + "GTXE2_COMMON_PMASCANOUT2", + "GTXE2_COMMON_GTSOUTHREFCLK1", + "GTXE2_IMUX1_4", + "GTXE2_FAN3_2", + "GTXE2_IMUX31_3", + "GTXE2_LOGIC_OUTS_B8_5", + "GTXE2_COMMON_DRPDO13", + "GTXE2_CLK0_5", + "GTXE2_COMMON_TXOUTCLK_3", + "GTXE2_BYP7_2", + "GTXE2_COMMON_QPLLRSVD111", + "GTXE2_BYP1_0", + "GTXE2_IMUX47_1", + "GTXE2_COMMON_PMASCANIN2", + "GTXE2_LOGIC_OUTS_B15_3", + "GTXE2_FAN0_1", + "GTXE2_IMUX17_1", + "GTXE2_IMUX22_2", + "GTXE2_LOGIC_OUTS_B4_5", + "GTXE2_IMUX21_0", + "GTXE2_COMMON_DRPCLK", + "GTXE2_LOGIC_OUTS_B20_0", + "GTXE2_COMMON_QPLLRSVD23", + "GTXE2_FAN0_0", + "GTXE2_LOGIC_OUTS_B13_4", + "GTXE2_LOGIC_OUTS_B7_3", + "GTXE2_BYP6_5", + "GTXE2_IMUX41_5", + "GTXE2_IMUX46_3", + "GTXE2_IMUX9_1", + "GTXE2_IMUX12_1", + "GTXE2_COMMON_PMARSVD2", + "GTXE2_COMMON_GTNORTHREFCLK1", + "GTXE2_IMUX34_4", + "GTXE2_FAN7_1", + "GTXE2_COMMON_QPLLDMONITOR0", + "GTXE2_LOGIC_OUTS_B6_1", + "GTXE2_IMUX12_4", + "GTXE2_FAN2_2", + "GTXE2_LOGIC_OUTS_B9_0", + "GTXE2_IMUX0_5", + "GTXE2_LOGIC_OUTS_B16_4", + "GTXE2_COMMON_BGRCALOVRD2", + "GTXE2_FAN6_4", + "GTXE2_LOGIC_OUTS_B0_3", + "GTXE2_IMUX29_5", + "GTXE2_IMUX31_1", + "GTXE2_IMUX20_5", + "GTXE2_IMUX7_0", + "GTXE2_BYP0_2", + "GTXE2_IMUX22_3", + "GTXE2_COMMON_GTSOUTHREFCLK0", + "GTXE2_FAN4_1", + "GTXE2_IMUX36_2", + "GTXE2_COMMON_MGT_CLK8", + "GTXE2_FAN6_3", + "GTXE2_COMMON_QPLLDMONITOR4", + "GTXE2_LOGIC_OUTS_B3_2", + "GTXE2_IMUX32_0", + "GTXE2_IMUX2_5", + "GTXE2_IMUX33_4", + "GTXE2_COMMON_DRPDI4", + "GTXE2_IMUX40_3", + "GTXE2_COMMON_DRPDO2", + "GTXE2_IMUX5_2", + "GTXE2_CLK0_2", + "GTXE2_IMUX27_4", + "GTXE2_LOGIC_OUTS_B0_0", + "GTXE2_IMUX36_3", + "GTXE2_LOGIC_OUTS_B3_4", + "GTXE2_COMMON_QPLLDMONITOR5", + "GTXE2_LOGIC_OUTS_B16_0", + "GTXE2_IMUX11_0", + "GTXE2_COMMON_TXOUTCLK_1", + "GTXE2_IMUX24_1", + "GTXE2_FAN3_0", + "GTXE2_LOGIC_OUTS_B22_4", + "GTXE2_IMUX13_1", + "GTXE2_IMUX28_2", + "GTXE2_COMMON_QPLLDMONITOR6", + "GTXE2_LOGIC_OUTS_B20_2", + "GTXE2_IMUX44_5", + "GTXE2_IMUX36_1", + "GTXE2_COMMON_DRPDO6", + "GTXE2_IMUX26_3", + "GTXE2_LOGIC_OUTS_B14_4", + "GTXE2_COMMON_MGT_CLK6", + "GTXE2_FAN3_3", + "GTXE2_IMUX3_3", + "GTXE2_LOGIC_OUTS_B4_0", + "GTXE2_IMUX10_0", + "GTXE2_IMUX3_1", + "GTXE2_BYP7_5", + "GTXE2_IMUX33_5", + "GTXE2_IMUX47_3", + "GTXE2_COMMON_QPLLRSVD114", + "GTXE2_IMUX20_2", + "GTXE2_LOGIC_OUTS_B12_5", + "IBUFDS_GTE2_0_O", + "GTXE2_COMMON_PMASCANOUT4", + "GTXE2_LOGIC_OUTS_B3_3", + "GTXE2_IMUX14_1", + "GTXE2_COMMON_QPLLRSVD13", + "GTXE2_IMUX12_5", + "GTXE2_LOGIC_OUTS_B13_1", + "GTXE2_COMMON_QPLLRSVD115", + "IBUFDS_GTE2_0_CEB", + "GTXE2_COMMON_QPLLOUTREFCLK", + "GTXE2_LOGIC_OUTS_B8_4", + "GTXE2_LOGIC_OUTS_B17_0", + "GTXE2_CTRL1_1", + "GTXE2_LOGIC_OUTS_B7_1", + "GTXE2_LOGIC_OUTS_B5_4", + "GTXE2_COMMON_QPLLLOCKEN", + "GTXE2_COMMON_NORTHREFCLK1", + "GTXE2_BYP3_1", + "GTXE2_IMUX27_2", + "GTXE2_LOGIC_OUTS_B5_2", + "GTXE2_IMUX15_5", + "GTXE2_IMUX36_5", + "GTXE2_COMMON_PMASCANOUT3", + "GTXE2_IMUX41_2", + "GTXE2_COMMON_DRPDI7", + "GTXE2_BYP6_3", + "GTXE2_LOGIC_OUTS_B10_1", + "GTXE2_BYP3_4", + "GTXE2_IMUX23_4", + "GTXE2_CLK1_5", + "GTXE2_IMUX43_3", + "GTXE2_IMUX21_3", + "GTXE2_IMUX24_2", + "GTXE2_IMUX11_4", + "GTXE2_LOGIC_OUTS_B5_5", + "GTXE2_LOGIC_OUTS_B15_1", + "GTXE2_IMUX34_0", + "GTXE2_CLK0_1", + "GTXE2_COMMON_GTREFCLK1", + "GTXE2_COMMON_QPLLDMONITOR1", + "GTXE2_LOGIC_OUTS_B10_4", + "GTXE2_IMUX40_2", + "GTXE2_LOGIC_OUTS_B20_1", + "GTXE2_LOGIC_OUTS_B7_2", + "GTXE2_IMUX1_0", + "GTXE2_LOGIC_OUTS_B0_5", + "GTXE2_LOGIC_OUTS_B0_1", + "GTXE2_LOGIC_OUTS_B22_3", + "GTXE2_IMUX3_0", + "GTXE2_COMMON_DRPDI13", + "GTXE2_IMUX45_2", + "GTXE2_LOGIC_OUTS_B13_2", + "GTXE2_COMMON_DRPDI14", + "GTXE2_COMMON_DRPDI12", + "GTXE2_FAN5_5", + "GTXE2_COMMON_QPLLRSVD17", + "GTXE2_FAN4_3", + "GTXE2_LOGIC_OUTS_B1_0", + "GTXE2_LOGIC_OUTS_B9_5", + "GTXE2_CTRL0_0", + "GTXE2_BYP0_0", + "GTXE2_IMUX30_0", + "GTXE2_LOGIC_OUTS_B12_2", + "GTXE2_IMUX27_1", + "GTXE2_COMMON_DRPDO0", + "GTXE2_IMUX28_4", + "GTXE2_IMUX18_0", + "GTXE2_IMUX28_3", + "GTXE2_LOGIC_OUTS_B16_3", + "GTXE2_LOGIC_OUTS_B19_5", + "GTXE2_LOGIC_OUTS_B15_4", + "GTXE2_COMMON_RXOUTCLK_3", + "GTXE2_IMUX19_4", + "GTXE2_FAN6_5", + "GTXE2_IMUX32_2", + "GTXE2_COMMON_GTQPLLOUTREFCLK", + "GTXE2_CLK0_0", + "GTXE2_LOGIC_OUTS_B9_3", + "GTXE2_LOGIC_OUTS_B12_1", + "GTXE2_IMUX30_3", + "GTXE2_LOGIC_OUTS_B20_3", + "GTXE2_LOGIC_OUTS_B20_4", + "GTXE2_COMMON_PMASCANOUT1", + "GTXE2_BYP3_2", + "GTXE2_IMUX25_1", + "GTXE2_COMMON_QPLLRSVD110", + "GTXE2_BYP7_4", + "GTXE2_IMUX1_1", + "GTXE2_LOGIC_OUTS_B21_2", + "GTXE2_IMUX19_5", + "GTXE2_IMUX35_3", + "GTXE2_IMUX27_5", + "GTXE2_FAN2_5", + "IBUFDS_GTE2_0_IB", + "GTXE2_LOGIC_OUTS_B23_2", + "GTXE2_COMMON_BGRCALOVRD1", + "GTXE2_COMMON_QPLLOUTCLK", + "GTXE2_IMUX2_2", + "GTXE2_COMMON_REFCLKOUTMONITOR", + "GTXE2_IMUX5_5", + "GTXE2_IMUX22_5", + "GTXE2_LOGIC_OUTS_B19_3", + "GTXE2_FAN1_3", + "GTXE2_COMMON_QPLLPD", + "GTXE2_COMMON_QPLLCLKSPARE0", + "GTXE2_LOGIC_OUTS_B16_5", + "GTXE2_FAN1_2", + "GTXE2_IMUX45_1", + "GTXE2_LOGIC_OUTS_B11_2", + "GTXE2_IMUX34_5", + "GTXE2_IMUX38_3", + "GTXE2_LOGIC_OUTS_B12_3", + "GTXE2_COMMON_BGBYPASSB", + "GTXE2_IMUX40_0", + "GTXE2_IMUX9_5", + "GTXE2_FAN7_5", + "GTXE2_COMMON_QPLLRSVD12", + "GTXE2_IMUX4_5", + "GTXE2_IMUX38_5", + "GTXE2_BYP5_4", + "GTXE2_FAN4_0", + "GTXE2_IMUX26_2", + "GTXE2_LOGIC_OUTS_B4_4", + "GTXE2_LOGIC_OUTS_B2_5", + "GTXE2_IMUX33_3", + "GTXE2_BYP0_3", + "GTXE2_FAN3_5", + "GTXE2_COMMON_PMARSVD7", + "GTXE2_IMUX39_3", + "GTXE2_COMMON_DRPDO10", + "GTXE2_IMUX5_4", + "GTXE2_IMUX39_1", + "GTXE2_IMUX23_1", + "GTXE2_IMUX36_0", + "GTXE2_COMMON_MGT_CLK5", + "GTXE2_IMUX4_2", + "GTXE2_IMUX18_1", + "GTXE2_IMUX33_2", + "IBUFDS_GTE2_0_MGTCLKOUT", + "GTXE2_LOGIC_OUTS_B11_5", + "GTXE2_IMUX17_4", + "GTXE2_LOGIC_OUTS_B12_0", + "GTXE2_COMMON_MGT_CLK1", + "GTXE2_LOGIC_OUTS_B4_2", + "GTXE2_COMMON_BGRCALOVRD4", + "GTXE2_IMUX13_2", + "GTXE2_LOGIC_OUTS_B9_1", + "GTXE2_COMMON_RXOUTCLK_1", + "GTXE2_LOGIC_OUTS_B18_1", + "GTXE2_IMUX3_5", + "GTXE2_IMUX5_1", + "GTXE2_IMUX35_5", + "GTXE2_COMMON_QPLLOUTRESET", + "IBUFDS_GTE2_1_I", + "GTXE2_CTRL1_2", + "GTXE2_IMUX6_3", + "GTXE2_LOGIC_OUTS_B6_2", + "GTXE2_LOGIC_OUTS_B2_4", + "GTXE2_IMUX2_1", + "GTXE2_LOGIC_OUTS_B16_2", + "GTXE2_FAN5_2", + "GTXE2_IMUX31_4", + "GTXE2_LOGIC_OUTS_B11_3", + "GTXE2_BYP4_4", + "GTXE2_FAN2_1", + "GTXE2_IMUX12_2", + "GTXE2_COMMON_QPLLRESET", + "GTXE2_COMMON_MGT_CLK9", + "GTXE2_IMUX29_2", + "GTXE2_COMMON_DRPADDR6", + "GTXE2_LOGIC_OUTS_B20_5", + "GTXE2_IMUX46_2", + "GTXE2_IMUX8_2", + "GTXE2_IMUX33_1", + "GTXE2_FAN6_0", + "GTXE2_IMUX17_3", + "GTXE2_COMMON_DRPADDR1", + "GTXE2_IMUX29_0", + "GTXE2_IMUX47_0", + "GTXE2_LOGIC_OUTS_B3_5", + "GTXE2_FAN0_3", + "GTXE2_COMMON_TXOUTCLK_0", + "GTXE2_LOGIC_OUTS_B8_3", + "GTXE2_IMUX36_4", + "GTXE2_COMMON_GTREFCLK0", + "GTXE2_LOGIC_OUTS_B11_0", + "GTXE2_IMUX34_2", + "GTXE2_COMMON_DRPDO9", + "GTXE2_IMUX8_3", + "GTXE2_LOGIC_OUTS_B14_1", + "GTXE2_IMUX23_3", + "GTXE2_IMUX34_1", + "GTXE2_IMUX16_1", + "GTXE2_IMUX4_3", + "GTXE2_IMUX25_0", + "GTXE2_COMMON_MGT_CLK2", + "GTXE2_COMMON_PMASCANOUT0", + "GTXE2_COMMON_DRPDO14", + "GTXE2_IMUX20_1", + "GTXE2_FAN2_4", + "GTXE2_LOGIC_OUTS_B1_2", + "GTXE2_IMUX39_0", + "GTXE2_IMUX1_2", + "GTXE2_BYP4_3", + "GTXE2_COMMON_PMASCANIN1", + "GTXE2_IMUX37_5", + "GTXE2_LOGIC_OUTS_B8_1", + "GTXE2_IMUX40_5", + "GTXE2_IMUX20_3", + "GTXE2_COMMON_DRPRDY", + "GTXE2_FAN7_2", + "GTXE2_IMUX38_1", + "GTXE2_COMMON_DRPDI1", + "GTXE2_FAN2_0", + "GTXE2_COMMON_DRPADDR4", + "GTXE2_COMMON_DRPEN", + "GTXE2_FAN0_5", + "GTXE2_IMUX32_4", + "GTXE2_IMUX30_1", + "IBUFDS_GTE2_1_I_SEG", + "GTXE2_FAN2_3", + "GTXE2_IMUX30_5", + "GTXE2_LOGIC_OUTS_B6_4", + "GTXE2_IMUX43_5", + "GTXE2_BYP4_0", + "GTXE2_LOGIC_OUTS_B18_5", + "GTXE2_BYP3_0", + "IBUFDS_GTE2_1_CLKTESTSIG_SEG", + "GTXE2_BYP6_2", + "GTXE2_IMUX44_1", + "GTXE2_LOGIC_OUTS_B10_0", + "GTXE2_LOGIC_OUTS_B17_4", + "GTXE2_IMUX39_4", + "GTXE2_IMUX10_1", + "GTXE2_IMUX14_5", + "IBUFDS_GTE2_1_MGTCLKOUT", + "GTXE2_IMUX21_5", + "GTXE2_IMUX4_1", + "GTXE2_IMUX39_2", + "GTXE2_COMMON_QPLLFBCLKLOST", + "GTXE2_IMUX43_4", + "GTXE2_LOGIC_OUTS_B21_1", + "GTXE2_IMUX4_0", + "GTXE2_FAN1_4", + "GTXE2_IMUX0_4", + "GTXE2_LOGIC_OUTS_B8_0", + "GTXE2_IMUX11_5", + "GTXE2_BYP5_0", + "GTXE2_IMUX46_5", + "GTXE2_IMUX13_4", + "GTXE2_LOGIC_OUTS_B8_2", + "GTXE2_COMMON_PMARSVD1", + "GTXE2_IMUX44_3", + "GTXE2_IMUX20_4", + "GTXE2_CTRL1_5", + "GTXE2_IMUX20_0", + "GTXE2_LOGIC_OUTS_B5_1", + "GTXE2_FAN7_4", + "GTXE2_COMMON_DRPDO5", + "GTXE2_FAN1_1", + "GTXE2_IMUX12_0", + "GTXE2_FAN0_2", + "GTXE2_COMMON_PMARSVD0", + "GTXE2_LOGIC_OUTS_B21_4", + "GTXE2_IMUX13_3", + "GTXE2_IMUX44_4", + "GTXE2_IMUX8_4", + "GTXE2_FAN3_1", + "GTXE2_BYP4_1", + "GTXE2_LOGIC_OUTS_B18_2", + "GTXE2_COMMON_PMASCANIN3", + "GTXE2_IMUX10_2", + "GTXE2_IMUX41_0", + "GTXE2_LOGIC_OUTS_B7_4", + "GTXE2_IMUX2_4", + "GTXE2_IMUX15_3", + "GTXE2_IMUX9_4", + "GTXE2_IMUX3_4", + "GTXE2_BYP7_3", + "GTXE2_LOGIC_OUTS_B2_0", + "GTXE2_CLK1_1", + "GTXE2_BYP4_2", + "GTXE2_LOGIC_OUTS_B15_0", + "GTXE2_FAN6_2", + "GTXE2_COMMON_QPLLRSVD18", + "GTXE2_COMMON_PMARSVD3", + "GTXE2_LOGIC_OUTS_B6_0", + "GTXE2_COMMON_QPLLRSVD20", + "GTXE2_IMUX17_5", + "GTXE2_LOGIC_OUTS_B10_2", + "GTXE2_BYP3_3", + "GTXE2_IMUX2_0", + "GTXE2_IMUX38_4", + "GTXE2_IMUX2_3", + "GTXE2_COMMON_QPLLRSVD14", + "GTXE2_IMUX28_5", + "IBUFDS_GTE2_1_IB", + "GTXE2_IMUX7_1", + "GTXE2_LOGIC_OUTS_B13_5", + "GTXE2_IMUX40_1", + "GTXE2_IMUX9_0", + "GTXE2_COMMON_QPLLRSVD19", + "IBUFDS_GTE2_0_IB_SEG", + "GTXE2_IMUX42_0", + "GTXE2_IMUX29_4", + "GTXE2_COMMON_NORTHREFCLK0", + "GTXE2_COMMON_DRPDO7", + "GTXE2_IMUX6_1", + "GTXE2_IMUX43_2", + "GTXE2_LOGIC_OUTS_B14_5", + "GTXE2_COMMON_DRPDO8", + "GTXE2_IMUX18_4", + "IBUFDS_GTE2_1_CEB", + "GTXE2_IMUX0_2", + "GTXE2_CTRL0_2", + "GTXE2_LOGIC_OUTS_B10_3", + "GTXE2_LOGIC_OUTS_B0_4", + "GTXE2_COMMON_DRPADDR0", + "GTXE2_COMMON_DRPDI8", + "GTXE2_BYP0_4", + "GTXE2_LOGIC_OUTS_B19_0", + "GTXE2_IMUX26_1", + "GTXE2_IMUX41_4", + "GTXE2_COMMON_DRPDO1", + "GTXE2_IMUX25_3", + "GTXE2_COMMON_BGRCALOVRD3", + "GTXE2_IMUX33_0", + "GTXE2_IMUX42_4", + "GTXE2_IMUX31_5", + "GTXE2_COMMON_PMASCANCLK1", + "GTXE2_LOGIC_OUTS_B15_2", + "GTXE2_FAN6_1", + "GTXE2_COMMON_MGT_CLK0", + "GTXE2_IMUX0_0", + "GTXE2_COMMON_QPLLREFCLKLOST", + "GTXE2_IMUX43_1", + "GTXE2_IMUX8_1", + "GTXE2_IMUX45_3", + "GTXE2_IMUX45_5", + "GTXE2_COMMON_DRPDI0", + "GTXE2_CTRL0_3", + "GTXE2_LOGIC_OUTS_B2_2", + "GTXE2_IMUX21_4", + "IBUFDS_GTE2_1_CLKTESTSIG", + "GTXE2_COMMON_DRPDI6", + "GTXE2_FAN4_5", + "GTXE2_FAN5_1", + "GTXE2_COMMON_DRPADDR3", + "GTXE2_LOGIC_OUTS_B18_3", + "GTXE2_COMMON_QDPMASCANRSTEN", + "GTXE2_LOGIC_OUTS_B11_1", + "GTXE2_COMMON_QPLLRSVD21", + "GTXE2_IMUX15_4", + "GTXE2_IMUX6_4", + "GTXE2_IMUX38_2", + "GTXE2_FAN1_0", + "GTXE2_LOGIC_OUTS_B17_3", + "GTXE2_LOGIC_OUTS_B15_5", + "GTXE2_IMUX11_3", + "GTXE2_IMUX35_0", + "GTXE2_IMUX16_0", + "GTXE2_LOGIC_OUTS_B22_5", + "GTXE2_BYP2_2", + "GTXE2_LOGIC_OUTS_B17_2", + "GTXE2_IMUX29_1", + "GTXE2_IMUX14_2", + "GTXE2_COMMON_QPLLREFCLKSEL0", + "GTXE2_IMUX38_0", + "GTXE2_COMMON_QPLLRSVD24", + "GTXE2_IMUX24_3", + "GTXE2_FAN0_4", + "GTXE2_COMMON_GTNORTHREFCLK0", + "GTXE2_COMMON_BGMONITORENB", + "GTXE2_BYP6_4", + "GTXE2_IMUX18_3", + "GTXE2_LOGIC_OUTS_B5_0", + "GTXE2_IMUX10_3", + "GTXE2_IMUX8_0", + "GTXE2_COMMON_DRPDO4", + "GTXE2_IMUX37_1", + "GTXE2_COMMON_DRPDO3", + "GTXE2_COMMON_PMASCANCLK0", + "GTXE2_IMUX19_3", + "GTXE2_IMUX13_5", + "GTXE2_IMUX15_2", + "GTXE2_IMUX5_0", + "GTXE2_LOGIC_OUTS_B6_3", + "GTXE2_FAN3_4", + "IBUFDS_GTE2_1_O", + "GTXE2_IMUX41_3", + "GTXE2_IMUX19_1", + "GTXE2_LOGIC_OUTS_B2_3", + "GTXE2_IMUX7_5", + "GTXE2_BYP6_0", + "GTXE2_IMUX41_1", + "GTXE2_IMUX16_4", + "GTXE2_CLK1_2", + "GTXE2_COMMON_MGT_CLK3", + "IBUFDS_GTE2_0_CLKTESTSIG_SEG", + "GTXE2_COMMON_GTGREFCLK", + "GTXE2_LOGIC_OUTS_B22_1", + "GTXE2_IMUX7_4", + "GTXE2_COMMON_PMASCANIN0", + "GTXE2_COMMON_QPLLREFCLKSEL2", + "GTXE2_CTRL0_1", + "IBUFDS_GTE2_0_ODIV2", + "GTXE2_IMUX26_4", + "GTXE2_IMUX37_3", + "GTXE2_COMMON_TXOUTCLK_2", + "GTXE2_IMUX12_3", + "GTXE2_BYP3_5", + "GTXE2_LOGIC_OUTS_B6_5", + "GTXE2_LOGIC_OUTS_B21_0", + "GTXE2_IMUX23_2", + "GTXE2_IMUX19_0", + "GTXE2_COMMON_SOUTHREFCLK0", + "GTXE2_LOGIC_OUTS_B4_3", + "GTXE2_CLK1_3", + "GTXE2_LOGIC_OUTS_B14_2", + "GTXE2_IMUX37_4", + "GTXE2_BYP6_1", + "GTXE2_COMMON_QPLLRSVD11", + "GTXE2_BYP5_1", + "GTXE2_IMUX16_2", + "GTXE2_CTRL1_4", + "GTXE2_LOGIC_OUTS_B13_0", + "GTXE2_IMUX26_5", + "GTXE2_IMUX13_0", + "GTXE2_LOGIC_OUTS_B22_2", + "GTXE2_IMUX31_2", + "GTXE2_COMMON_MGT_CLK4", + "GTXE2_FAN4_2", + "GTXE2_LOGIC_OUTS_B18_0", + "GTXE2_COMMON_RXOUTCLK_0", + "GTXE2_COMMON_QPLLDMONITOR7", + "GTXE2_IMUX25_5", + "GTXE2_LOGIC_OUTS_B13_3", + "GTXE2_IMUX22_0", + "GTXE2_IMUX21_2", + "GTXE2_IMUX5_3", + "IBUFDS_GTE2_0_CLKTESTSIG", + "GTXE2_LOGIC_OUTS_B23_3", + "GTXE2_LOGIC_OUTS_B23_0", + "GTXE2_IMUX14_3", + "GTXE2_COMMON_BGRCALOVRD0", + "GTXE2_LOGIC_OUTS_B9_2", + "GTXE2_LOGIC_OUTS_B0_2", + "GTXE2_IMUX18_2", + "GTXE2_BYP7_1", + "GTXE2_IMUX24_0", + "GTXE2_IMUX11_2", + "GTXE2_COMMON_PMARSVD4", + "IBUFDS_GTE2_1_IB_SEG", + "GTXE2_COMMON_QPLLRSVD15", + "GTXE2_IMUX47_4", + "GTXE2_IMUX17_2", + "GTXE2_IMUX24_5", + "GTXE2_IMUX8_5", + "GTXE2_BYP0_1", + "GTXE2_IMUX0_1", + "GTXE2_IMUX15_1", + "GTXE2_COMMON_QPLLRSVD10", + "GTXE2_CLK1_4" + ], + "pips": { + "GTX_COMMON.GTXE2_IMUX18_5->GTXE2_COMMON_QPLLRSVD115": { + "src_wire": "GTXE2_IMUX18_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD115", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_NORTHREFCLK1->>GTXE2_COMMON_GTNORTHREFCLK1": { + "src_wire": "GTXE2_COMMON_NORTHREFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_GTNORTHREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_CTRL1_2->GTXE2_COMMON_QPLLOUTRESET": { + "src_wire": "GTXE2_CTRL1_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLOUTRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_QPLLREFCLKLOST->GTXE2_LOGIC_OUTS_B10_2": { + "src_wire": "GTXE2_COMMON_QPLLREFCLKLOST", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX30_5->GTXE2_COMMON_BGBYPASSB": { + "src_wire": "GTXE2_IMUX30_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_BGBYPASSB", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX19_3->GTXE2_COMMON_QPLLRSVD16": { + "src_wire": "GTXE2_IMUX19_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD16", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO9->GTXE2_LOGIC_OUTS_B11_1": { + "src_wire": "GTXE2_COMMON_DRPDO9", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX18_2->GTXE2_COMMON_QPLLRSVD13": { + "src_wire": "GTXE2_IMUX18_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX22_0->GTXE2_COMMON_DRPDI1": { + "src_wire": "GTXE2_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR0->GTXE2_LOGIC_OUTS_B19_3": { + "src_wire": "GTXE2_COMMON_QPLLDMONITOR0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX29_2->GTXE2_COMMON_DRPADDR3": { + "src_wire": "GTXE2_IMUX29_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR3->GTXE2_LOGIC_OUTS_B21_3": { + "src_wire": "GTXE2_COMMON_QPLLDMONITOR3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPRDY->GTXE2_LOGIC_OUTS_B21_0": { + "src_wire": "GTXE2_COMMON_DRPRDY", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX22_1->GTXE2_COMMON_DRPDI9": { + "src_wire": "GTXE2_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX28_4->GTXE2_COMMON_RCALENB": { + "src_wire": "GTXE2_IMUX28_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_RCALENB", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO13->GTXE2_LOGIC_OUTS_B14_1": { + "src_wire": "GTXE2_COMMON_DRPDO13", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX21_5->GTXE2_COMMON_PMARSVD3": { + "src_wire": "GTXE2_IMUX21_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_PMARSVD3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX27_3->GTXE2_COMMON_QPLLREFCLKSEL2": { + "src_wire": "GTXE2_IMUX27_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLREFCLKSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.IBUFDS_GTE2_1_O->IBUFDS_GTE2_1_MGTCLKOUT": { + "src_wire": "IBUFDS_GTE2_1_O", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTE2_1_MGTCLKOUT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX16_1->GTXE2_COMMON_DRPDI15": { + "src_wire": "GTXE2_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO8->GTXE2_LOGIC_OUTS_B15_1": { + "src_wire": "GTXE2_COMMON_DRPDO8", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX22_5->GTXE2_COMMON_QPLLRSVD113": { + "src_wire": "GTXE2_IMUX22_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD113", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO14->GTXE2_LOGIC_OUTS_B8_1": { + "src_wire": "GTXE2_COMMON_DRPDO14", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.IBUFDS_GTE2_0_O->GTXE2_COMMON_REFCLK0": { + "src_wire": "IBUFDS_GTE2_0_O", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_REFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO4->GTXE2_LOGIC_OUTS_B10_0": { + "src_wire": "GTXE2_COMMON_DRPDO4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_TXOUTCLK_3->>GTXE2_COMMON_MGT_CLK9": { + "src_wire": "GTXE2_COMMON_TXOUTCLK_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_MGT_CLK9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX26_4->GTXE2_COMMON_BGRCALOVRD3": { + "src_wire": "GTXE2_IMUX26_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_BGRCALOVRD3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX22_4->GTXE2_COMMON_QPLLRSVD19": { + "src_wire": "GTXE2_IMUX22_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD19", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX16_0->GTXE2_COMMON_DRPDI7": { + "src_wire": "GTXE2_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX20_2->GTXE2_COMMON_PMARSVD4": { + "src_wire": "GTXE2_IMUX20_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_PMARSVD4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX20_1->GTXE2_COMMON_DRPDI13": { + "src_wire": "GTXE2_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.IBUFDS_GTE2_1_ODIV2->IBUFDS_GTE2_1_MGTCLKOUT": { + "src_wire": "IBUFDS_GTE2_1_ODIV2", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTE2_1_MGTCLKOUT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX29_0->GTXE2_COMMON_DRPWE": { + "src_wire": "GTXE2_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPWE", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO0->GTXE2_LOGIC_OUTS_B15_0": { + "src_wire": "GTXE2_COMMON_DRPDO0", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B15_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX27_5->GTXE2_COMMON_BGMONITORENB": { + "src_wire": "GTXE2_IMUX27_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_BGMONITORENB", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX18_1->GTXE2_COMMON_DRPDI11": { + "src_wire": "GTXE2_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_QPLLLOCK->GTXE2_LOGIC_OUTS_B14_2": { + "src_wire": "GTXE2_COMMON_QPLLLOCK", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX23_0->GTXE2_COMMON_DRPDI0": { + "src_wire": "GTXE2_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR5->GTXE2_LOGIC_OUTS_B18_4": { + "src_wire": "GTXE2_COMMON_QPLLDMONITOR5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B18_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX26_2->GTXE2_COMMON_DRPADDR4": { + "src_wire": "GTXE2_IMUX26_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO5->GTXE2_LOGIC_OUTS_B14_0": { + "src_wire": "GTXE2_COMMON_DRPDO5", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B14_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX17_0->GTXE2_COMMON_DRPDI6": { + "src_wire": "GTXE2_IMUX17_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX26_3->IBUFDS_GTE2_0_CEB": { + "src_wire": "GTXE2_IMUX26_3", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTE2_0_CEB", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_NORTHREFCLK0->>GTXE2_COMMON_GTNORTHREFCLK0": { + "src_wire": "GTXE2_COMMON_NORTHREFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_GTNORTHREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX20_0->GTXE2_COMMON_DRPDI5": { + "src_wire": "GTXE2_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_QPLLFBCLKLOST->GTXE2_LOGIC_OUTS_B19_2": { + "src_wire": "GTXE2_COMMON_QPLLFBCLKLOST", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B19_2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX20_4->GTXE2_COMMON_PMARSVD6": { + "src_wire": "GTXE2_IMUX20_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_PMARSVD6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO12->GTXE2_LOGIC_OUTS_B10_1": { + "src_wire": "GTXE2_COMMON_DRPDO12", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B10_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR4->GTXE2_LOGIC_OUTS_B22_4": { + "src_wire": "GTXE2_COMMON_QPLLDMONITOR4", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B22_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.IBUFDS_GTE2_0_I->IBUFDS_GTE2_0_I_SEG": { + "src_wire": "IBUFDS_GTE2_0_I", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTE2_0_I_SEG", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO10->GTXE2_LOGIC_OUTS_B13_1": { + "src_wire": "GTXE2_COMMON_DRPDO10", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX18_0->GTXE2_COMMON_DRPDI3": { + "src_wire": "GTXE2_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX26_5->GTXE2_COMMON_BGPDB": { + "src_wire": "GTXE2_IMUX26_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_BGPDB", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX22_3->GTXE2_COMMON_QPLLRSVD15": { + "src_wire": "GTXE2_IMUX22_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_CLK0_2->GTXE2_COMMON_GTGREFCLK": { + "src_wire": "GTXE2_CLK0_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_GTGREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_GTQPLLOUTCLK->GTXE2_COMMON_QPLLOUTCLK": { + "src_wire": "GTXE2_COMMON_GTQPLLOUTCLK", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLOUTCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX19_1->GTXE2_COMMON_DRPDI10": { + "src_wire": "GTXE2_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX30_4->GTXE2_COMMON_BGRCALOVRD1": { + "src_wire": "GTXE2_IMUX30_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_BGRCALOVRD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_RXOUTCLK_2->>GTXE2_COMMON_MGT_CLK6": { + "src_wire": "GTXE2_COMMON_RXOUTCLK_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_MGT_CLK6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO3->GTXE2_LOGIC_OUTS_B9_0": { + "src_wire": "GTXE2_COMMON_DRPDO3", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX29_1->GTXE2_COMMON_DRPEN": { + "src_wire": "GTXE2_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_REFCLKOUTMONITOR->GTXE2_LOGIC_OUTS_B2_3": { + "src_wire": "GTXE2_COMMON_REFCLKOUTMONITOR", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B2_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX19_2->GTXE2_COMMON_QPLLRSVD12": { + "src_wire": "GTXE2_IMUX19_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX19_4->GTXE2_COMMON_QPLLRSVD110": { + "src_wire": "GTXE2_IMUX19_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD110", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_CLK1_3->GTXE2_COMMON_QPLLLOCKDETCLK": { + "src_wire": "GTXE2_CLK1_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLLOCKDETCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX21_4->GTXE2_COMMON_PMARSVD2": { + "src_wire": "GTXE2_IMUX21_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_PMARSVD2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_RXOUTCLK_1->>GTXE2_COMMON_MGT_CLK1": { + "src_wire": "GTXE2_COMMON_RXOUTCLK_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_MGT_CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO11->GTXE2_LOGIC_OUTS_B9_1": { + "src_wire": "GTXE2_COMMON_DRPDO11", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B9_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.IBUFDS_GTE2_0_IB->IBUFDS_GTE2_0_IB_SEG": { + "src_wire": "IBUFDS_GTE2_0_IB", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTE2_0_IB_SEG", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.IBUFDS_GTE2_0_O->IBUFDS_GTE2_0_MGTCLKOUT": { + "src_wire": "IBUFDS_GTE2_0_O", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTE2_0_MGTCLKOUT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_RXOUTCLK_3->>GTXE2_COMMON_MGT_CLK7": { + "src_wire": "GTXE2_COMMON_RXOUTCLK_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_MGT_CLK7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO6->GTXE2_LOGIC_OUTS_B8_0": { + "src_wire": "GTXE2_COMMON_DRPDO6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B8_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR2->GTXE2_LOGIC_OUTS_B17_3": { + "src_wire": "GTXE2_COMMON_QPLLDMONITOR2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B17_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.IBUFDS_GTE2_1_I->IBUFDS_GTE2_1_I_SEG": { + "src_wire": "IBUFDS_GTE2_1_I", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTE2_1_I_SEG", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX31_3->GTXE2_COMMON_QPLLREFCLKSEL0": { + "src_wire": "GTXE2_IMUX31_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLREFCLKSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_SOUTHREFCLK1->>GTXE2_COMMON_GTSOUTHREFCLK1": { + "src_wire": "GTXE2_COMMON_SOUTHREFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_GTSOUTHREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR1->GTXE2_LOGIC_OUTS_B23_3": { + "src_wire": "GTXE2_COMMON_QPLLDMONITOR1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B23_3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX21_1->GTXE2_COMMON_DRPDI12": { + "src_wire": "GTXE2_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX18_3->GTXE2_COMMON_QPLLRSVD17": { + "src_wire": "GTXE2_IMUX18_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD17", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_SOUTHREFCLK0->>GTXE2_COMMON_GTSOUTHREFCLK0": { + "src_wire": "GTXE2_COMMON_SOUTHREFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_GTSOUTHREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX22_2->GTXE2_COMMON_QPLLRSVD11": { + "src_wire": "GTXE2_IMUX22_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.IBUFDS_GTE2_0_ODIV2->IBUFDS_GTE2_0_MGTCLKOUT": { + "src_wire": "IBUFDS_GTE2_0_ODIV2", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTE2_0_MGTCLKOUT", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_TXOUTCLK_1->>GTXE2_COMMON_MGT_CLK3": { + "src_wire": "GTXE2_COMMON_TXOUTCLK_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_MGT_CLK3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX23_2->GTXE2_COMMON_QPLLRSVD10": { + "src_wire": "GTXE2_IMUX23_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX28_2->GTXE2_COMMON_DRPADDR2": { + "src_wire": "GTXE2_IMUX28_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO1->GTXE2_LOGIC_OUTS_B11_0": { + "src_wire": "GTXE2_COMMON_DRPDO1", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B11_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX29_3->IBUFDS_GTE2_1_CEB": { + "src_wire": "GTXE2_IMUX29_3", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTE2_1_CEB", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.IBUFDS_GTE2_0_MGTCLKOUT->>GTXE2_COMMON_MGT_CLK4": { + "src_wire": "IBUFDS_GTE2_0_MGTCLKOUT", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_MGT_CLK4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX30_3->GTXE2_COMMON_QPLLREFCLKSEL1": { + "src_wire": "GTXE2_IMUX30_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLREFCLKSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX18_4->GTXE2_COMMON_QPLLRSVD111": { + "src_wire": "GTXE2_IMUX18_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD111", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX30_2->GTXE2_COMMON_DRPADDR6": { + "src_wire": "GTXE2_IMUX30_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX16_2->GTXE2_COMMON_QPLLRSVD20": { + "src_wire": "GTXE2_IMUX16_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO7->GTXE2_LOGIC_OUTS_B12_0": { + "src_wire": "GTXE2_COMMON_DRPDO7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX19_5->GTXE2_COMMON_QPLLRSVD114": { + "src_wire": "GTXE2_IMUX19_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD114", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_RXOUTCLK_0->>GTXE2_COMMON_MGT_CLK0": { + "src_wire": "GTXE2_COMMON_RXOUTCLK_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_MGT_CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO15->GTXE2_LOGIC_OUTS_B12_1": { + "src_wire": "GTXE2_COMMON_DRPDO15", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B12_1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX27_4->GTXE2_COMMON_BGRCALOVRD2": { + "src_wire": "GTXE2_IMUX27_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_BGRCALOVRD2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX20_5->GTXE2_COMMON_PMARSVD7": { + "src_wire": "GTXE2_IMUX20_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_PMARSVD7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_REFCLK1->>GTXE2_COMMON_GTREFCLK1": { + "src_wire": "GTXE2_COMMON_REFCLK1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_GTREFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_DRPDO2->GTXE2_LOGIC_OUTS_B13_0": { + "src_wire": "GTXE2_COMMON_DRPDO2", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX29_4->GTXE2_COMMON_BGRCALOVRD4": { + "src_wire": "GTXE2_IMUX29_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_BGRCALOVRD4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX23_1->GTXE2_COMMON_DRPDI8": { + "src_wire": "GTXE2_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX31_4->GTXE2_COMMON_BGRCALOVRD0": { + "src_wire": "GTXE2_IMUX31_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_BGRCALOVRD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR6->GTXE2_LOGIC_OUTS_B20_4": { + "src_wire": "GTXE2_COMMON_QPLLDMONITOR6", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B20_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX23_4->GTXE2_COMMON_QPLLRSVD18": { + "src_wire": "GTXE2_IMUX23_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD18", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX28_3->GTXE2_COMMON_QPLLPD": { + "src_wire": "GTXE2_IMUX28_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLPD", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX24_2->GTXE2_COMMON_DRPADDR0": { + "src_wire": "GTXE2_IMUX24_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_CLK1_1->GTXE2_COMMON_DRPCLK": { + "src_wire": "GTXE2_CLK1_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_TXOUTCLK_2->>GTXE2_COMMON_MGT_CLK8": { + "src_wire": "GTXE2_COMMON_TXOUTCLK_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_MGT_CLK8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX21_2->GTXE2_COMMON_PMARSVD0": { + "src_wire": "GTXE2_IMUX21_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_PMARSVD0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX31_2->GTXE2_COMMON_DRPADDR7": { + "src_wire": "GTXE2_IMUX31_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX16_4->GTXE2_COMMON_QPLLRSVD22": { + "src_wire": "GTXE2_IMUX16_4", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX23_3->GTXE2_COMMON_QPLLRSVD14": { + "src_wire": "GTXE2_IMUX23_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX21_3->GTXE2_COMMON_PMARSVD1": { + "src_wire": "GTXE2_IMUX21_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_PMARSVD1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX17_1->GTXE2_COMMON_DRPDI14": { + "src_wire": "GTXE2_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_CTRL0_3->GTXE2_COMMON_QPLLRESET": { + "src_wire": "GTXE2_CTRL0_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRESET", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_TXOUTCLK_0->>GTXE2_COMMON_MGT_CLK2": { + "src_wire": "GTXE2_COMMON_TXOUTCLK_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_MGT_CLK2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX19_0->GTXE2_COMMON_DRPDI2": { + "src_wire": "GTXE2_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.IBUFDS_GTE2_1_O->GTXE2_COMMON_REFCLK1": { + "src_wire": "IBUFDS_GTE2_1_O", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_REFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX23_5->GTXE2_COMMON_QPLLRSVD112": { + "src_wire": "GTXE2_IMUX23_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD112", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR7->GTXE2_LOGIC_OUTS_B16_4": { + "src_wire": "GTXE2_COMMON_QPLLDMONITOR7", + "is_pseudo": "0", + "dst_wire": "GTXE2_LOGIC_OUTS_B16_4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX25_2->GTXE2_COMMON_DRPADDR1": { + "src_wire": "GTXE2_IMUX25_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.IBUFDS_GTE2_1_IB->IBUFDS_GTE2_1_IB_SEG": { + "src_wire": "IBUFDS_GTE2_1_IB", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTE2_1_IB_SEG", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX16_3->GTXE2_COMMON_QPLLRSVD21": { + "src_wire": "GTXE2_IMUX16_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_REFCLK0->>GTXE2_COMMON_GTREFCLK0": { + "src_wire": "GTXE2_COMMON_REFCLK0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_GTREFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX16_5->GTXE2_COMMON_QPLLRSVD23": { + "src_wire": "GTXE2_IMUX16_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_COMMON_GTQPLLOUTREFCLK->GTXE2_COMMON_QPLLOUTREFCLK": { + "src_wire": "GTXE2_COMMON_GTQPLLOUTREFCLK", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLOUTREFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX27_2->GTXE2_COMMON_DRPADDR5": { + "src_wire": "GTXE2_IMUX27_2", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX20_3->GTXE2_COMMON_PMARSVD5": { + "src_wire": "GTXE2_IMUX20_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_PMARSVD5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.IBUFDS_GTE2_1_MGTCLKOUT->>GTXE2_COMMON_MGT_CLK5": { + "src_wire": "IBUFDS_GTE2_1_MGTCLKOUT", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_MGT_CLK5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX21_0->GTXE2_COMMON_DRPDI4": { + "src_wire": "GTXE2_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_DRPDI4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX24_3->GTXE2_COMMON_QPLLLOCKEN": { + "src_wire": "GTXE2_IMUX24_3", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLLOCKEN", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_COMMON.GTXE2_IMUX17_5->GTXE2_COMMON_QPLLRSVD24": { + "src_wire": "GTXE2_IMUX17_5", + "is_pseudo": "0", + "dst_wire": "GTXE2_COMMON_QPLLRSVD24", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_GTX_INT_INTERFACE.json b/kintex7/tile_type_GTX_INT_INTERFACE.json new file mode 100644 index 0000000..66b78c2 --- /dev/null +++ b/kintex7/tile_type_GTX_INT_INTERFACE.json @@ -0,0 +1,1526 @@ +{ + "tile_type": "GTX_INT_INTERFACE", + "sites": [], + "wires": [ + "GTXE2_INT_INTERFACE_IMUX46", + "GTXE2_INT_INTERFACE_IMUX44", + "INT_INTERFACE_LH7", + "INT_INTERFACE_EE4C3", + "GTXE2_INT_INTERFACE_IMUX39", + "GTXE2_INT_INTERFACE_IMUX_DELAY8", + "GTXE2_INT_INTERFACE_IMUX0", + "GTXE2_INT_INTERFACE_IMUX3", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_LOGIC_OUTS_B22", + "GTXE2_INT_INTERFACE_IMUX_OUT15", + "GTXE2_INT_INTERFACE_IMUX_OUT7", + "INT_INTERFACE_EE2A2", + "GTXE2_INT_INTERFACE_IMUX33", + "GTXE2_INT_INTERFACE_IMUX_DELAY5", + "INT_INTERFACE_LOGIC_OUTS3", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_NW4A1", + "GTXE2_INT_INTERFACE_IMUX_DELAY2", + "GTXE2_INT_INTERFACE_IMUX_DELAY39", + "GTXE2_INT_INTERFACE_IMUX18", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_LH8", + "INT_INTERFACE_LOGIC_OUTS1", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_LOGIC_OUTS0", + "INT_INTERFACE_BLOCK_OUTS_B0", + "INT_INTERFACE_SE2A2", + "GTXE2_INT_INTERFACE_IMUX_OUT13", + "INT_INTERFACE_SW2A3", + "GTXE2_INT_INTERFACE_IMUX_DELAY40", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_LH5", + "GTXE2_INT_INTERFACE_IMUX6", + "INT_INTERFACE_BLOCK_OUTS_B3", + "INT_INTERFACE_FAN6", + "GTXE2_INT_INTERFACE_IMUX_OUT30", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_SE4BEG3", + "GTXE2_INT_INTERFACE_IMUX_DELAY3", + "GTXE2_INT_INTERFACE_IMUX_DELAY15", + "GTXE2_INT_INTERFACE_IMUX12", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_WL1END1", + "GTXE2_INT_INTERFACE_IMUX_DELAY13", + "GTXE2_INT_INTERFACE_IMUX20", + "INT_INTERFACE_WW4A2", + "GTXE2_INT_INTERFACE_IMUX30", + "INT_INTERFACE_LH10", + "GTXE2_INT_INTERFACE_IMUX9", + "GTXE2_INT_INTERFACE_IMUX_DELAY18", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_LOGIC_OUTS18", + "INT_INTERFACE_EL1BEG1", + "GTXE2_INT_INTERFACE_IMUX_DELAY41", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_CTRL1", + "GTXE2_INT_INTERFACE_IMUX_OUT20", + "INT_INTERFACE_EE2A1", + "GTXE2_INT_INTERFACE_IMUX_OUT34", + "INT_INTERFACE_LOGIC_OUTS23", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_EE4A3", + "GTXE2_INT_INTERFACE_IMUX_OUT8", + "INT_INTERFACE_LH9", + "GTXE2_INT_INTERFACE_IMUX_DELAY7", + "GTXE2_INT_INTERFACE_IMUX_OUT40", + "GTXE2_INT_INTERFACE_IMUX_DELAY22", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_ER1BEG1", + "GTXE2_INT_INTERFACE_IMUX36", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_LOGIC_OUTS11", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_LH3", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_BYP4", + "GTXE2_INT_INTERFACE_IMUX_OUT36", + "GTXE2_INT_INTERFACE_IMUX_DELAY30", + "GTXE2_INT_INTERFACE_IMUX_DELAY16", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_LOGIC_OUTS8", + "INT_INTERFACE_LOGIC_OUTS4", + "GTXE2_INT_INTERFACE_IMUX_OUT14", + "INT_INTERFACE_LOGIC_OUTS_B3", + "INT_INTERFACE_LOGIC_OUTS21", + "GTXE2_INT_INTERFACE_IMUX_OUT26", + "GTXE2_INT_INTERFACE_IMUX1", + "GTXE2_INT_INTERFACE_IMUX15", + "INT_INTERFACE_CLK1", + "GTXE2_INT_INTERFACE_IMUX_OUT25", + "INT_INTERFACE_SE4C1", + "GTXE2_INT_INTERFACE_IMUX11", + "GTXE2_INT_INTERFACE_IMUX27", + "INT_INTERFACE_SE2A0", + "GTXE2_INT_INTERFACE_IMUX_DELAY34", + "INT_INTERFACE_SE4BEG1", + "GTXE2_INT_INTERFACE_IMUX_DELAY43", + "INT_INTERFACE_NE4BEG0", + "GTXE2_INT_INTERFACE_IMUX_DELAY45", + "INT_INTERFACE_SW2A1", + "GTXE2_INT_INTERFACE_IMUX_OUT27", + "GTXE2_INT_INTERFACE_IMUX19", + "GTXE2_INT_INTERFACE_IMUX_DELAY17", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_LOGIC_OUTS_B21", + "GTXE2_INT_INTERFACE_IMUX_OUT18", + "GTXE2_INT_INTERFACE_IMUX_DELAY20", + "INT_INTERFACE_BYP0", + "GTXE2_INT_INTERFACE_IMUX_OUT6", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_WW4C0", + "GTXE2_INT_INTERFACE_IMUX_OUT19", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_EE2BEG1", + "GTXE2_INT_INTERFACE_IMUX_OUT24", + "INT_INTERFACE_LH6", + "GTXE2_INT_INTERFACE_IMUX43", + "INT_INTERFACE_EE4C0", + "GTXE2_INT_INTERFACE_IMUX_OUT16", + "INT_INTERFACE_WR1END0", + "GTXE2_INT_INTERFACE_IMUX_DELAY47", + "INT_INTERFACE_LOGIC_OUTS10", + "GTXE2_INT_INTERFACE_IMUX_OUT44", + "GTXE2_INT_INTERFACE_IMUX_OUT5", + "INT_INTERFACE_LOGIC_OUTS_B11", + "GTXE2_INT_INTERFACE_IMUX_OUT42", + "GTXE2_INT_INTERFACE_IMUX23", + "INT_INTERFACE_LOGIC_OUTS_B10", + "INT_INTERFACE_SE4C2", + "GTXE2_INT_INTERFACE_IMUX_OUT28", + "INT_INTERFACE_WW4END0", + "GTXE2_INT_INTERFACE_IMUX_DELAY46", + "INT_INTERFACE_LOGIC_OUTS17", + "INT_INTERFACE_LOGIC_OUTS_B13", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_EE2A3", + "GTXE2_INT_INTERFACE_IMUX_DELAY44", + "INT_INTERFACE_LOGIC_OUTS2", + "GTXE2_INT_INTERFACE_IMUX_DELAY12", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_LOGIC_OUTS_B12", + "GTXE2_INT_INTERFACE_IMUX7", + "INT_INTERFACE_EE4C1", + "GTXE2_INT_INTERFACE_IMUX_OUT46", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_EE4B1", + "GTXE2_INT_INTERFACE_IMUX_OUT32", + "INT_INTERFACE_WW4C2", + "GTXE2_INT_INTERFACE_IMUX40", + "GTXE2_INT_INTERFACE_IMUX28", + "GTXE2_INT_INTERFACE_IMUX_OUT11", + "INT_INTERFACE_BYP2", + "GTXE2_INT_INTERFACE_IMUX_OUT31", + "GTXE2_INT_INTERFACE_IMUX_DELAY9", + "GTXE2_INT_INTERFACE_IMUX_DELAY19", + "INT_INTERFACE_LOGIC_OUTS16", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_NW4A0", + "GTXE2_INT_INTERFACE_IMUX_OUT2", + "GTXE2_INT_INTERFACE_IMUX_DELAY21", + "GTXE2_INT_INTERFACE_IMUX_OUT0", + "INT_INTERFACE_LOGIC_OUTS20", + "INT_INTERFACE_LOGIC_OUTS22", + "GTXE2_INT_INTERFACE_IMUX_OUT1", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_LH11", + "INT_INTERFACE_NW4A3", + "GTXE2_INT_INTERFACE_IMUX42", + "GTXE2_INT_INTERFACE_IMUX32", + "INT_INTERFACE_WW4C1", + "GTXE2_INT_INTERFACE_IMUX_DELAY29", + "GTXE2_INT_INTERFACE_IMUX_OUT33", + "GTXE2_INT_INTERFACE_IMUX21", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_EL1BEG3", + "GTXE2_INT_INTERFACE_IMUX_DELAY37", + "INT_INTERFACE_EE4A1", + "GTXE2_INT_INTERFACE_IMUX_OUT23", + "GTXE2_INT_INTERFACE_IMUX24", + "INT_INTERFACE_LOGIC_OUTS_B2", + "INT_INTERFACE_LOGIC_OUTS_B20", + "INT_INTERFACE_NE2A2", + "GTXE2_INT_INTERFACE_IMUX10", + "INT_INTERFACE_BYP6", + "GTXE2_INT_INTERFACE_IMUX_DELAY23", + "INT_INTERFACE_LOGIC_OUTS_B23", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_LOGIC_OUTS_B6", + "GTXE2_INT_INTERFACE_IMUX2", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_LOGIC_OUTS_B16", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_LH2", + "INT_INTERFACE_LOGIC_OUTS_B14", + "GTXE2_INT_INTERFACE_IMUX34", + "GTXE2_INT_INTERFACE_IMUX26", + "GTXE2_INT_INTERFACE_IMUX_DELAY6", + "INT_INTERFACE_SW4A2", + "GTXE2_INT_INTERFACE_IMUX_DELAY0", + "GTXE2_INT_INTERFACE_IMUX_DELAY14", + "INT_INTERFACE_LH1", + "INT_INTERFACE_LOGIC_OUTS5", + "INT_INTERFACE_WW4A3", + "GTXE2_INT_INTERFACE_IMUX_DELAY25", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_LH4", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_WR1END3", + "GTXE2_INT_INTERFACE_IMUX_OUT45", + "GTXE2_INT_INTERFACE_IMUX_OUT3", + "INT_INTERFACE_LOGIC_OUTS15", + "INT_INTERFACE_LOGIC_OUTS_B19", + "GTXE2_INT_INTERFACE_IMUX_OUT47", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LOGIC_OUTS_B17", + "GTXE2_INT_INTERFACE_IMUX_DELAY28", + "GTXE2_INT_INTERFACE_IMUX8", + "GTXE2_INT_INTERFACE_IMUX_DELAY11", + "INT_INTERFACE_LOGIC_OUTS_B15", + "INT_INTERFACE_LOGIC_OUTS_B9", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_LOGIC_OUTS_B0", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_BLOCK_OUTS_B1", + "GTXE2_INT_INTERFACE_IMUX_DELAY36", + "INT_INTERFACE_LOGIC_OUTS_B7", + "GTXE2_INT_INTERFACE_IMUX25", + "INT_INTERFACE_LOGIC_OUTS_B8", + "INT_INTERFACE_LOGIC_OUTS14", + "INT_INTERFACE_CTRL0", + "GTXE2_INT_INTERFACE_IMUX_OUT21", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_LOGIC_OUTS12", + "GTXE2_INT_INTERFACE_IMUX_OUT43", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_SW2A0", + "GTXE2_INT_INTERFACE_IMUX38", + "GTXE2_INT_INTERFACE_IMUX37", + "GTXE2_INT_INTERFACE_IMUX16", + "INT_INTERFACE_WW4A0", + "GTXE2_INT_INTERFACE_IMUX14", + "INT_INTERFACE_FAN5", + "GTXE2_INT_INTERFACE_IMUX13", + "INT_INTERFACE_LOGIC_OUTS7", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_LOGIC_OUTS_B18", + "INT_INTERFACE_BYP5", + "GTXE2_INT_INTERFACE_IMUX_DELAY31", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_ER1BEG3", + "GTXE2_INT_INTERFACE_IMUX_OUT4", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_LOGIC_OUTS_B4", + "GTXE2_INT_INTERFACE_IMUX_DELAY42", + "GTXE2_INT_INTERFACE_IMUX5", + "GTXE2_INT_INTERFACE_IMUX_OUT29", + "GTXE2_INT_INTERFACE_IMUX47", + "GTXE2_INT_INTERFACE_IMUX29", + "GTXE2_INT_INTERFACE_IMUX_OUT39", + "GTXE2_INT_INTERFACE_IMUX4", + "GTXE2_INT_INTERFACE_IMUX_OUT35", + "GTXE2_INT_INTERFACE_IMUX_OUT9", + "INT_INTERFACE_WW4B1", + "GTXE2_INT_INTERFACE_IMUX_DELAY38", + "GTXE2_INT_INTERFACE_IMUX_OUT10", + "GTXE2_INT_INTERFACE_IMUX_DELAY32", + "GTXE2_INT_INTERFACE_IMUX17", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_WW4A1", + "GTXE2_INT_INTERFACE_IMUX_DELAY1", + "INT_INTERFACE_FAN2", + "GTXE2_INT_INTERFACE_IMUX_DELAY33", + "GTXE2_INT_INTERFACE_IMUX_OUT38", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_LH12", + "GTXE2_INT_INTERFACE_IMUX_DELAY27", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_WR1END1", + "GTXE2_INT_INTERFACE_IMUX_DELAY4", + "GTXE2_INT_INTERFACE_IMUX31", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_LOGIC_OUTS13", + "GTXE2_INT_INTERFACE_IMUX_DELAY26", + "GTXE2_INT_INTERFACE_IMUX_OUT41", + "INT_INTERFACE_LOGIC_OUTS9", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_EE2A0", + "GTXE2_INT_INTERFACE_IMUX_DELAY35", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_LOGIC_OUTS_B5", + "GTXE2_INT_INTERFACE_IMUX_DELAY24", + "INT_INTERFACE_LOGIC_OUTS19", + "INT_INTERFACE_SE2A3", + "GTXE2_INT_INTERFACE_IMUX45", + "INT_INTERFACE_BLOCK_OUTS_B2", + "GTXE2_INT_INTERFACE_IMUX22", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_WW2END1", + "GTXE2_INT_INTERFACE_IMUX_OUT22", + "GTXE2_INT_INTERFACE_IMUX41", + "INT_INTERFACE_LOGIC_OUTS6", + "INT_INTERFACE_BYP7", + "GTXE2_INT_INTERFACE_IMUX_OUT17", + "GTXE2_INT_INTERFACE_IMUX_OUT12", + "GTXE2_INT_INTERFACE_IMUX35", + "INT_INTERFACE_EE2BEG0", + "GTXE2_INT_INTERFACE_IMUX_DELAY10", + "GTXE2_INT_INTERFACE_IMUX_OUT37", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + "pips": { + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX36->>GTXE2_INT_INTERFACE_IMUX_DELAY36": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX36", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY36", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX44->>GTXE2_INT_INTERFACE_IMUX_OUT44": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX44", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT44", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX44->>GTXE2_INT_INTERFACE_IMUX_DELAY44": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX44", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY44", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX16->>GTXE2_INT_INTERFACE_IMUX_DELAY16": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX16", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY16", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX14->>GTXE2_INT_INTERFACE_IMUX_DELAY14": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX14", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B6", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY29->GTXE2_INT_INTERFACE_IMUX_OUT29": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY29", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT29", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX37->>GTXE2_INT_INTERFACE_IMUX_DELAY37": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX37", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY37", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX1->>GTXE2_INT_INTERFACE_IMUX_DELAY1": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX1", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX39->>GTXE2_INT_INTERFACE_IMUX_DELAY39": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX39", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY39", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX29->>GTXE2_INT_INTERFACE_IMUX_OUT29": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX29", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT29", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX27->>GTXE2_INT_INTERFACE_IMUX_DELAY27": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX27", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY27", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY31->GTXE2_INT_INTERFACE_IMUX_OUT31": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY31", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT31", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY8->GTXE2_INT_INTERFACE_IMUX_OUT8": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY8", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY39->GTXE2_INT_INTERFACE_IMUX_OUT39": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY39", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT39", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX13->>GTXE2_INT_INTERFACE_IMUX_OUT13": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX13", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY36->GTXE2_INT_INTERFACE_IMUX_OUT36": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY36", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT36", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX1->>GTXE2_INT_INTERFACE_IMUX_OUT1": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX1", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX35->>GTXE2_INT_INTERFACE_IMUX_OUT35": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX35", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT35", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX11->>GTXE2_INT_INTERFACE_IMUX_OUT11": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX11", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX40->>GTXE2_INT_INTERFACE_IMUX_DELAY40": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX40", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY40", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY25->GTXE2_INT_INTERFACE_IMUX_OUT25": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY25", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT25", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B13", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX47->>GTXE2_INT_INTERFACE_IMUX_OUT47": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX47", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT47", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX7->>GTXE2_INT_INTERFACE_IMUX_OUT7": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX7", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY42->GTXE2_INT_INTERFACE_IMUX_OUT42": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY42", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT42", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY44->GTXE2_INT_INTERFACE_IMUX_OUT44": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY44", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT44", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B8", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY41->GTXE2_INT_INTERFACE_IMUX_OUT41": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY41", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT41", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX20->>GTXE2_INT_INTERFACE_IMUX_OUT20": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX20", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX42->>GTXE2_INT_INTERFACE_IMUX_OUT42": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX42", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT42", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY17->GTXE2_INT_INTERFACE_IMUX_OUT17": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY17", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT17", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY43->GTXE2_INT_INTERFACE_IMUX_OUT43": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY43", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT43", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX38->>GTXE2_INT_INTERFACE_IMUX_DELAY38": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX38", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY38", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY35->GTXE2_INT_INTERFACE_IMUX_OUT35": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY35", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT35", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY26->GTXE2_INT_INTERFACE_IMUX_OUT26": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY26", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT26", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY20->GTXE2_INT_INTERFACE_IMUX_OUT20": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY20", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY45->GTXE2_INT_INTERFACE_IMUX_OUT45": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY45", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT45", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX42->>GTXE2_INT_INTERFACE_IMUX_DELAY42": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX42", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY42", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY33->GTXE2_INT_INTERFACE_IMUX_OUT33": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY33", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT33", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX27->>GTXE2_INT_INTERFACE_IMUX_OUT27": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX27", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT27", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX22->>GTXE2_INT_INTERFACE_IMUX_OUT22": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX22", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX8->>GTXE2_INT_INTERFACE_IMUX_DELAY8": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX8", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX30->>GTXE2_INT_INTERFACE_IMUX_OUT30": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX30", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT30", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX13->>GTXE2_INT_INTERFACE_IMUX_DELAY13": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX13", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX28->>GTXE2_INT_INTERFACE_IMUX_DELAY28": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX28", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY28", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B14", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX24->>GTXE2_INT_INTERFACE_IMUX_DELAY24": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX24", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX40->>GTXE2_INT_INTERFACE_IMUX_OUT40": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX40", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT40", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX5->>GTXE2_INT_INTERFACE_IMUX_DELAY5": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX5", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B3", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX26->>GTXE2_INT_INTERFACE_IMUX_DELAY26": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX26", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY26", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX11->>GTXE2_INT_INTERFACE_IMUX_DELAY11": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX11", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX41->>GTXE2_INT_INTERFACE_IMUX_OUT41": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX41", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT41", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY28->GTXE2_INT_INTERFACE_IMUX_OUT28": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY28", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT28", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX19->>GTXE2_INT_INTERFACE_IMUX_DELAY19": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX19", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY19", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX46->>GTXE2_INT_INTERFACE_IMUX_DELAY46": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX46", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY46", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX22->>GTXE2_INT_INTERFACE_IMUX_DELAY22": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX22", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX15->>GTXE2_INT_INTERFACE_IMUX_DELAY15": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX15", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B15", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B18", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS18", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX33->>GTXE2_INT_INTERFACE_IMUX_DELAY33": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX33", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY33", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX28->>GTXE2_INT_INTERFACE_IMUX_OUT28": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX28", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT28", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY18->GTXE2_INT_INTERFACE_IMUX_OUT18": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY18", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT18", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX12->>GTXE2_INT_INTERFACE_IMUX_DELAY12": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX12", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX47->>GTXE2_INT_INTERFACE_IMUX_DELAY47": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX47", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY47", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX39->>GTXE2_INT_INTERFACE_IMUX_OUT39": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX39", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT39", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY38->GTXE2_INT_INTERFACE_IMUX_OUT38": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY38", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT38", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX4->>GTXE2_INT_INTERFACE_IMUX_DELAY4": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX4", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY46->GTXE2_INT_INTERFACE_IMUX_OUT46": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY46", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT46", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B0", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX41->>GTXE2_INT_INTERFACE_IMUX_DELAY41": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX41", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY41", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY1->GTXE2_INT_INTERFACE_IMUX_OUT1": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY1", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT1", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX9->>GTXE2_INT_INTERFACE_IMUX_OUT9": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX9", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY10->GTXE2_INT_INTERFACE_IMUX_OUT10": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY10", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B11", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX18->>GTXE2_INT_INTERFACE_IMUX_OUT18": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX18", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT18", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY5->GTXE2_INT_INTERFACE_IMUX_OUT5": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY5", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY27->GTXE2_INT_INTERFACE_IMUX_OUT27": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY27", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT27", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY0->GTXE2_INT_INTERFACE_IMUX_OUT0": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY0", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY32->GTXE2_INT_INTERFACE_IMUX_OUT32": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY32", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT32", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY3->GTXE2_INT_INTERFACE_IMUX_OUT3": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY3", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY34->GTXE2_INT_INTERFACE_IMUX_OUT34": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY34", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT34", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX17->>GTXE2_INT_INTERFACE_IMUX_OUT17": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX17", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT17", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY19->GTXE2_INT_INTERFACE_IMUX_OUT19": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY19", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT19", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX14->>GTXE2_INT_INTERFACE_IMUX_OUT14": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX14", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX16->>GTXE2_INT_INTERFACE_IMUX_OUT16": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX16", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT16", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B17", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS17", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX45->>GTXE2_INT_INTERFACE_IMUX_OUT45": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX45", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT45", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY11->GTXE2_INT_INTERFACE_IMUX_OUT11": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY11", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT11", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX19->>GTXE2_INT_INTERFACE_IMUX_OUT19": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX19", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT19", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B12", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX25->>GTXE2_INT_INTERFACE_IMUX_OUT25": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX25", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT25", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX31->>GTXE2_INT_INTERFACE_IMUX_OUT31": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX31", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT31", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX2->>GTXE2_INT_INTERFACE_IMUX_DELAY2": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX2", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX23->>GTXE2_INT_INTERFACE_IMUX_OUT23": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX23", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY4->GTXE2_INT_INTERFACE_IMUX_OUT4": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY4", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY22->GTXE2_INT_INTERFACE_IMUX_OUT22": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY22", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY14->GTXE2_INT_INTERFACE_IMUX_OUT14": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY14", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT14", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX10->>GTXE2_INT_INTERFACE_IMUX_DELAY10": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX10", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX0->>GTXE2_INT_INTERFACE_IMUX_DELAY0": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX0", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX32->>GTXE2_INT_INTERFACE_IMUX_OUT32": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX32", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT32", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY2->GTXE2_INT_INTERFACE_IMUX_OUT2": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY2", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX17->>GTXE2_INT_INTERFACE_IMUX_DELAY17": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX17", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY17", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY23->GTXE2_INT_INTERFACE_IMUX_OUT23": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY23", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY9->GTXE2_INT_INTERFACE_IMUX_OUT9": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY9", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX23->>GTXE2_INT_INTERFACE_IMUX_DELAY23": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX23", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B9", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY6->GTXE2_INT_INTERFACE_IMUX_OUT6": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY6", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY37->GTXE2_INT_INTERFACE_IMUX_OUT37": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY37", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT37", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX20->>GTXE2_INT_INTERFACE_IMUX_DELAY20": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX20", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX4->>GTXE2_INT_INTERFACE_IMUX_OUT4": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX4", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX26->>GTXE2_INT_INTERFACE_IMUX_OUT26": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX26", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT26", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX24->>GTXE2_INT_INTERFACE_IMUX_OUT24": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX24", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY16->GTXE2_INT_INTERFACE_IMUX_OUT16": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY16", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT16", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX18->>GTXE2_INT_INTERFACE_IMUX_DELAY18": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX18", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY18", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX43->>GTXE2_INT_INTERFACE_IMUX_DELAY43": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX43", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY43", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY40->GTXE2_INT_INTERFACE_IMUX_OUT40": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY40", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT40", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B21", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX36->>GTXE2_INT_INTERFACE_IMUX_OUT36": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX36", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT36", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX37->>GTXE2_INT_INTERFACE_IMUX_OUT37": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX37", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT37", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B20", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS20", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX3->>GTXE2_INT_INTERFACE_IMUX_DELAY3": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX3", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX30->>GTXE2_INT_INTERFACE_IMUX_DELAY30": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX30", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY30", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX32->>GTXE2_INT_INTERFACE_IMUX_DELAY32": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX32", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY32", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX34->>GTXE2_INT_INTERFACE_IMUX_OUT34": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX34", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT34", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX5->>GTXE2_INT_INTERFACE_IMUX_OUT5": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX5", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B19", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS19", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX6->>GTXE2_INT_INTERFACE_IMUX_DELAY6": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX6", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX25->>GTXE2_INT_INTERFACE_IMUX_DELAY25": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX25", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY25", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX33->>GTXE2_INT_INTERFACE_IMUX_OUT33": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX33", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT33", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY47->GTXE2_INT_INTERFACE_IMUX_OUT47": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY47", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT47", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY13->GTXE2_INT_INTERFACE_IMUX_OUT13": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY13", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT13", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX43->>GTXE2_INT_INTERFACE_IMUX_OUT43": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX43", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT43", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY21->GTXE2_INT_INTERFACE_IMUX_OUT21": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY21", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B5", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS5", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX31->>GTXE2_INT_INTERFACE_IMUX_DELAY31": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX31", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY31", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX0->>GTXE2_INT_INTERFACE_IMUX_OUT0": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX0", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX46->>GTXE2_INT_INTERFACE_IMUX_OUT46": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX46", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT46", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B7", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX8->>GTXE2_INT_INTERFACE_IMUX_OUT8": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX8", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT8", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX35->>GTXE2_INT_INTERFACE_IMUX_DELAY35": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX35", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY35", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX15->>GTXE2_INT_INTERFACE_IMUX_OUT15": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX15", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX10->>GTXE2_INT_INTERFACE_IMUX_OUT10": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX10", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX6->>GTXE2_INT_INTERFACE_IMUX_OUT6": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX6", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT6", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX21->>GTXE2_INT_INTERFACE_IMUX_OUT21": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX21", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY30->GTXE2_INT_INTERFACE_IMUX_OUT30": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY30", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT30", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX38->>GTXE2_INT_INTERFACE_IMUX_OUT38": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX38", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT38", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX9->>GTXE2_INT_INTERFACE_IMUX_DELAY9": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX9", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY9", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX45->>GTXE2_INT_INTERFACE_IMUX_DELAY45": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX45", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY45", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B16", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS16", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY24->GTXE2_INT_INTERFACE_IMUX_OUT24": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY24", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT24", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY7->GTXE2_INT_INTERFACE_IMUX_OUT7": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY7", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY15->GTXE2_INT_INTERFACE_IMUX_OUT15": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY15", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT15", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX12->>GTXE2_INT_INTERFACE_IMUX_OUT12": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX12", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX29->>GTXE2_INT_INTERFACE_IMUX_DELAY29": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX29", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY29", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B22", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS22", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX_DELAY12->GTXE2_INT_INTERFACE_IMUX_OUT12": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY12", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT12", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B10", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS10", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX3->>GTXE2_INT_INTERFACE_IMUX_OUT3": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX3", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT3", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B2", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B23", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS23", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B4", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS4", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX7->>GTXE2_INT_INTERFACE_IMUX_DELAY7": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX7", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY7", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX21->>GTXE2_INT_INTERFACE_IMUX_DELAY21": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX21", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY21", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX2->>GTXE2_INT_INTERFACE_IMUX_OUT2": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX2", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_OUT2", + "is_directional": "1", + "can_invert": "0" + }, + "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX34->>GTXE2_INT_INTERFACE_IMUX_DELAY34": { + "src_wire": "GTXE2_INT_INTERFACE_IMUX34", + "is_pseudo": "0", + "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY34", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_BRAM.json b/kintex7/tile_type_HCLK_BRAM.json new file mode 100644 index 0000000..6780067 --- /dev/null +++ b/kintex7/tile_type_HCLK_BRAM.json @@ -0,0 +1,108 @@ +{ + "tile_type": "HCLK_BRAM", + "sites": [], + "wires": [ + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14", + "HCLK_BRAM_CK_IN3", + "HCLK_BRAM_CK_IN7", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12", + "HCLK_BRAM_CK_IN8", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6", + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12", + "HCLK_BRAM_CK_IN9", + "HCLK_BRAM_CK_IN11", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2", + "HCLK_BRAM_CASCADEA_R", + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13", + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_BRAM_CK_IN1", + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14", + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_BRAM_CASCADEB_L", + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0", + "HCLK_BRAM_PMVBRAM_ODIV2", + "HCLK_BRAM_CK_IN10", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1", + "HCLK_BRAM_CK_IN13", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6", + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9", + "HCLK_BRAM_PMVBRAM_O", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3", + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_BRAM_CK_IN5", + "HCLK_BRAM_CK_IN6", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3", + "HCLK_BRAM_PMVBRAM_SELECT2", + "HCLK_BRAM_CK_IN12", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12", + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7", + "HCLK_BRAM_CASCADEB_R", + "HCLK_BRAM_CK_IN0", + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_BRAM_PMVBRAM_SELECT1", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10", + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_BRAM_CK_IN4", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5", + "HCLK_BRAM_CASCADEA_L", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2", + "HCLK_BRAM_CK_IN2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7", + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_BRAM_PMVBRAM_ODIV4", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8", + "HCLK_BRAM_PMVBRAM_SELECT3", + "HCLK_BRAM_PMVBRAM_SELECT4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_CLB.json b/kintex7/tile_type_HCLK_CLB.json new file mode 100644 index 0000000..37ddbb2 --- /dev/null +++ b/kintex7/tile_type_HCLK_CLB.json @@ -0,0 +1,49 @@ +{ + "tile_type": "HCLK_CLB", + "sites": [], + "wires": [ + "HCLK_CLB_PERFCLK2", + "HCLK_CLB_CK_IN12", + "HCLK_CLB_REFCK_WESTCLK1", + "HCLK_CLB_CK_IN5", + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CLB_CK_IN0", + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CLB_COUT0_L", + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CLB_CK_IN2", + "HCLK_CLB_CK_IN13", + "HCLK_CLB_PERFCLK3", + "HCLK_CLB_REFCK_EASTCLK0", + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CLB_CK_IN3", + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CLB_CK_IN11", + "HCLK_CLB_CK_IN1", + "HCLK_CLB_PERFCLK1", + "HCLK_CLB_CK_IN4", + "HCLK_CLB_REFCK_WESTCLK0", + "HCLK_CLB_COUT1_L", + "HCLK_CLB_CK_IN7", + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CLB_CK_IN8", + "HCLK_CLB_CK_IN6", + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CLB_CK_IN9", + "HCLK_CLB_PERFCLK0", + "HCLK_CLB_COUT1_R", + "HCLK_CLB_CK_IN10", + "HCLK_CLB_REFCK_EASTCLK1", + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CLB_COUT0_R", + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CLB_CK_BUFHCLK0" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_CMT.json b/kintex7/tile_type_HCLK_CMT.json new file mode 100644 index 0000000..8da264b --- /dev/null +++ b/kintex7/tile_type_HCLK_CMT.json @@ -0,0 +1,7067 @@ +{ + "tile_type": "HCLK_CMT", + "sites": [ + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "BUFMRCE", + "type": "BUFMRCE", + "site_pins": { + "CE": "HCLK_CMT_BUFMRCE_CEINP1", + "O": "HCLK_CMT_BUFMRCE_O1", + "I": "HCLK_CMT_BUFMR_INP1" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "BUFMRCE", + "type": "BUFMRCE", + "site_pins": { + "CE": "HCLK_CMT_BUFMRCE_CEINP0", + "O": "HCLK_CMT_BUFMRCE_O0", + "I": "HCLK_CMT_BUFMR_INP0" + }, + "x_coord": 0 + } + ], + "wires": [ + "HCLK_CMT_MUX_CLK_11", + "HCLK_CMT_BUFMR_CE1", + "HCLK_CMT_MUX_CLK_LEAF_UP0", + "HCLK_CMT_FREQ_PHASER_REFMUX_2", + "HCLK_CMT_FREQ_PHASER_REFMUX_1", + "HCLK_CMT_CK_IN1", + "HCLK_CMT_MUX_CLKINT_2", + "HCLK_CMT_OBURSTPENDING1", + "HCLK_CMT_CCIO0", + "HCLK_CMT_PHASEREF_BELOW0", + "HCLK_CMT_MUX_CLK_MMCM1", + "HCLK_CMT_PREF_TMUXOUT", + "HCLK_CMT_PHASEROUTA_OCLKDIV", + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_CMT_FREQ_REF_NS0", + "HCLK_CMT_MUX_CLK_PLL6", + "HCLK_CMT_MUX_CLK_3", + "HCLK_CMT_MUX_CLK_5", + "HCLK_CMT_CK_IN12", + "HCLK_CMT_PHASEROUTB_OCLKDIV", + "HCLK_CMT_PHY_CONTROL_IRANKB1", + "HCLK_CMT_MUX_CLK_MMCM5", + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_CMT_PHASERIND_ICLK", + "HCLK_CMT_MUX_CLK_6", + "HCLK_CMT_MUX_PLLE2_CLKIN1", + "HCLK_CMT_MUX_CLKINT_3", + "HCLK_CMT_CCIO3", + "HCLK_CMT_PHASERIND_ICLKDIV", + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_CMT_PREF_BOUNCE3", + "HCLK_CMT_PHASEROUTB_OCLK1X_90", + "HCLK_CMT_MUX_CLK_12", + "HCLK_CMT_MUX_MMCM_CLKIN1", + "HCLK_CMT_CCIO1", + "HCLK_CMT_MUX_CLK_MMCM9", + "HCLK_CMT_MUX_CLK_MMCM8", + "HCLK_CMT_OBURSTPENDING0", + "HCLK_CMT_PHASERINC_ICLKDIV", + "HCLK_CMT_CK_IN4", + "HCLK_CMT_MUX_CLK_MMCM11", + "HCLK_CMT_PHY_CONTROL_IRANKB0", + "HCLK_CMT_PHASEREF_BELOW1", + "HCLK_CMT_PHASEROUTA_OCLK1X_90", + "HCLK_CMT_PHASERINB_ICLK", + "HCLK_CMT_MUX_CLK_MMCM0", + "HCLK_CMT_MUX_OUT_FREQ_REF1", + "HCLK_CMT_MUX_OUT_FREQ_REF0", + "HCLK_CMT_MUX_CLK_LEAF_UP1", + "HCLK_CMT_BUFMR_PHASEREF1", + "HCLK_CMT_PHASERINA_ICLKDIV", + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_CMT_FREQ_REF_NS1", + "HCLK_CMT_PHASEROUTC_OCLK", + "HCLK_CMT_BUFMR_CE0", + "HCLK_CMT_PHASEROUTD_OCLK", + "HCLK_CMT_PREF_BOUNCE2", + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_CMT_MUX_CLK_7", + "HCLK_CMT_MUX_MMCM_CLKIN2", + "HCLK_CMT_PHASEROUTB_OCLK", + "HCLK_CMT_MUX_CLK_PLL5", + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_CMT_CK_IN11", + "HCLK_CMT_MUX_CLK_LEAF_DN1", + "HCLK_CMT_MUX_CLK_13", + "HCLK_CMT_MUX_CLK_PLL0", + "HCLK_CMT_PHASERIN_RCLK2", + "HCLK_CMT_CK_IN3", + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_CMT_PHASEROUTC_OCLK1X_90", + "HCLK_CMT_PHASERIN_RCLK3", + "HCLK_CMT_MUX_CLK_LEAF_DN0", + "HCLK_CMT_MUX_CLK_PLL3", + "HCLK_CMT_MUX_CLK_MMCM3", + "HCLK_CMT_ECALIB1", + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_CMT_CK_IN2", + "HCLK_CMT_MUX_MMCM_MUXED2", + "HCLK_CMT_PHASEROUTC_OCLKDIV", + "HCLK_CMT_PHASEREF_ABOVE0", + "HCLK_CMT_MUX_CLK_MMCM12", + "HCLK_CMT_CK_IN13", + "HCLK_CMT_MUX_CLK_MMCM4", + "HCLK_CMT_MUX_MMCM_MUXED3", + "HCLK_CMT_PHASEREF_ABOVE1", + "HCLK_CMT_CCIO2", + "HCLK_CMT_MUX_CLK_MMCM7", + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_CMT_MUX_CLK_9", + "HCLK_CMT_MUX_CLK_10", + "HCLK_CMT_IBURSTPENDING1", + "HCLK_CMT_MUX_MMCM_MUXED1", + "HCLK_CMT_MUX_CLK_4", + "HCLK_CMT_CK_IN8", + "HCLK_CMT_FREQ_REF_NS3", + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_CMT_MUX_MMCM_CLKFBIN", + "HCLK_CMT_BUFMR_PHASEREF0", + "HCLK_CMT_IBURSTPENDING0", + "HCLK_CMT_BUFMRCE_CEINP1", + "HCLK_CMT_MUX_CLKINT_0", + "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "HCLK_CMT_MUX_CLK_MMCM2", + "HCLK_CMT_MUX_CLK_0", + "HCLK_CMT_PHASEROUTD_OCLKDIV", + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_CMT_MUX_CLK_PLL7", + "HCLK_CMT_MUX_CLK_MMCM13", + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_CMT_PHASERIN_RCLK1", + "HCLK_CMT_PHASEROUTD_OCLK1X_90", + "HCLK_CMT_BUFMRCE_O0", + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_CMT_BUFMRCE_O1", + "HCLK_CMT_CK_IN9", + "HCLK_CMT_MUX_CLK_PLL1", + "HCLK_CMT_PHY_CONTROL_IRANKA0", + "HCLK_CMT_MUX_MMCM_MUXED0", + "HCLK_CMT_IBURST1", + "HCLK_CMT_FREQ_REF_NS2", + "HCLK_CMT_MUX_OUT_FREQ_REF2", + "HCLK_CMT_PREF_BOUNCE1", + "HCLK_CMT_PHASERINC_ICLK", + "HCLK_CMT_CK_IN5", + "HCLK_CMT_PREF_BOUNCE0", + "HCLK_CMT_CK_IN7", + "HCLK_CMT_MUX_CLK_2", + "HCLK_CMT_BUFMRCE_CEINP0", + "HCLK_CMT_PHY_CONTROL_IRANKA1", + "HCLK_CMT_FREQ_PHASER_REFMUX_0", + "HCLK_CMT_PHASERINB_ICLKDIV", + "HCLK_CMT_IBURST0", + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_CMT_MUX_CLKINT_1", + "HCLK_CMT_PHASERIN_RCLK0", + "HCLK_CMT_MUX_CLK_PLL2", + "HCLK_CMT_MUX_CLK_MMCM6", + "HCLK_CMT_MUX_CLK_8", + "HCLK_CMT_MUX_OUT_FREQ_REF3", + "HCLK_CMT_CK_IN6", + "HCLK_CMT_CK_IN0", + "HCLK_CMT_MUX_PLLE2_CLKIN2", + "HCLK_CMT_MUX_CLK_1", + "HCLK_CMT_BUFMR_INP0", + "HCLK_CMT_BUFMR_INP1", + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_CMT_CK_IN10", + "HCLK_CMT_PHASERINA_ICLK", + "HCLK_CMT_MUX_CLK_MMCM10", + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_CMT_PHY_SYNC_BB", + "HCLK_CMT_ECALIB0", + "HCLK_CMT_MUX_CLK_PLL4", + "HCLK_CMT_PHASEROUTA_OCLK", + "HCLK_CMT_PREF_CLKOUT", + "HCLK_CMT_CK_BUFHCLK5" + ], + "pips": { + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_BUFMR_CE1->HCLK_CMT_BUFMRCE_CEINP1": { + "src_wire": "HCLK_CMT_BUFMR_CE1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMRCE_CEINP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF0->>HCLK_CMT_FREQ_REF_NS0": { + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { + "src_wire": "HCLK_CMT_MUX_CLKINT_2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLKINT_1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { + "src_wire": "HCLK_CMT_MUX_CLKINT_3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { + "src_wire": "HCLK_CMT_MUX_CLKINT_0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_BUFMRCE_O1->>HCLK_CMT_BUFMR_PHASEREF1": { + "src_wire": "HCLK_CMT_BUFMRCE_O1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_PHASEREF1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLKINT_0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLKINT_0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { + "src_wire": "HCLK_CMT_MUX_CLKINT_1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF2->>HCLK_CMT_FREQ_REF_NS2": { + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_BUFMRCE_O0->>HCLK_CMT_BUFMR_PHASEREF0": { + "src_wire": "HCLK_CMT_BUFMRCE_O0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_PHASEREF0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF3->>HCLK_CMT_FREQ_REF_NS3": { + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_BUFMR_CE0->HCLK_CMT_BUFMRCE_CEINP0": { + "src_wire": "HCLK_CMT_BUFMR_CE0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMRCE_CEINP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLKINT_1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_6": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_IN7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_5": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF1->>HCLK_CMT_FREQ_REF_NS1": { + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_10": { + "src_wire": "HCLK_CMT_CK_IN11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_IN6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_IN10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_IN8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_IN5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_IN9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_IN4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_8": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_0": { + "src_wire": "HCLK_CMT_CK_IN12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_CMT_L.json b/kintex7/tile_type_HCLK_CMT_L.json new file mode 100644 index 0000000..dba8142 --- /dev/null +++ b/kintex7/tile_type_HCLK_CMT_L.json @@ -0,0 +1,7047 @@ +{ + "tile_type": "HCLK_CMT_L", + "sites": [ + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "BUFMRCE", + "type": "BUFMRCE", + "site_pins": { + "CE": "HCLK_CMT_BUFMRCE_CEINP1", + "O": "HCLK_CMT_BUFMRCE_O1", + "I": "HCLK_CMT_BUFMR_INP1" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "BUFMRCE", + "type": "BUFMRCE", + "site_pins": { + "CE": "HCLK_CMT_BUFMRCE_CEINP0", + "O": "HCLK_CMT_BUFMRCE_O0", + "I": "HCLK_CMT_BUFMR_INP0" + }, + "x_coord": 0 + } + ], + "wires": [ + "HCLK_CMT_MUX_CLK_11", + "HCLK_CMT_BUFMR_CE1", + "HCLK_CMT_MUX_CLK_LEAF_UP0", + "HCLK_CMT_FREQ_PHASER_REFMUX_2", + "HCLK_CMT_FREQ_PHASER_REFMUX_1", + "HCLK_CMT_CK_IN1", + "HCLK_CMT_MUX_CLKINT_2", + "HCLK_CMT_OBURSTPENDING1", + "HCLK_CMT_CCIO0", + "HCLK_CMT_PHASEREF_BELOW0", + "HCLK_CMT_MUX_CLK_MMCM1", + "HCLK_CMT_PREF_TMUXOUT", + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_CMT_FREQ_REF_NS0", + "HCLK_CMT_MUX_CLK_PLL6", + "HCLK_CMT_MUX_CLK_3", + "HCLK_CMT_MUX_CLK_5", + "HCLK_CMT_CK_IN12", + "HCLK_CMT_PHY_CONTROL_IRANKB1", + "HCLK_CMT_MUX_CLK_MMCM5", + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_CMT_MUX_CLK_6", + "HCLK_CMT_MUX_PLLE2_CLKIN1", + "HCLK_CMT_MUX_CLKINT_3", + "HCLK_CMT_CCIO3", + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_CMT_PREF_BOUNCE3", + "HCLK_CMT_MUX_CLK_12", + "HCLK_CMT_MUX_MMCM_CLKIN1", + "HCLK_CMT_CCIO1", + "HCLK_CMT_MUX_CLK_MMCM9", + "HCLK_CMT_MUX_CLK_MMCM8", + "HCLK_CMT_OBURSTPENDING0", + "HCLK_CMT_CK_IN4", + "HCLK_CMT_MUX_CLK_MMCM11", + "HCLK_CMT_PHY_CONTROL_IRANKB0", + "HCLK_CMT_PHASEREF_BELOW1", + "HCLK_CMT_MUX_CLK_MMCM0", + "HCLK_CMT_MUX_OUT_FREQ_REF1", + "HCLK_CMT_MUX_OUT_FREQ_REF0", + "HCLK_CMT_MUX_CLK_LEAF_UP1", + "HCLK_CMT_BUFMR_PHASEREF1", + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_CMT_FREQ_REF_NS1", + "HCLK_CMT_BUFMR_CE0", + "HCLK_CMT_PREF_BOUNCE2", + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_CMT_MUX_CLK_7", + "HCLK_CMT_MUX_MMCM_CLKIN2", + "HCLK_CMT_MUX_CLK_PLL5", + "HCLK_CMT_CK_IN11", + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_CMT_MUX_CLK_LEAF_DN1", + "HCLK_CMT_MUX_CLK_13", + "HCLK_CMT_MUX_CLK_PLL0", + "HCLK_CMT_PHASERIN_RCLK2", + "HCLK_CMT_CK_IN3", + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_CMT_PHASERIN_RCLK3", + "HCLK_CMT_MUX_CLK_PLL3", + "HCLK_CMT_MUX_CLK_LEAF_DN0", + "HCLK_CMT_MUX_CLK_MMCM3", + "HCLK_CMT_ECALIB1", + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_CMT_CK_IN2", + "HCLK_CMT_MUX_MMCM_MUXED2", + "HCLK_CMT_PHASEREF_ABOVE0", + "HCLK_CMT_MUX_CLK_MMCM12", + "HCLK_CMT_CK_IN13", + "HCLK_CMT_MUX_CLK_MMCM4", + "HCLK_CMT_MUX_MMCM_MUXED3", + "HCLK_CMT_PHASEREF_ABOVE1", + "HCLK_CMT_CCIO2", + "HCLK_CMT_MUX_CLK_MMCM7", + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_CMT_MUX_CLK_9", + "HCLK_CMT_MUX_CLK_10", + "HCLK_CMT_IBURSTPENDING1", + "HCLK_CMT_MUX_MMCM_MUXED1", + "HCLK_CMT_CK_IN8", + "HCLK_CMT_MUX_CLK_4", + "HCLK_CMT_FREQ_REF_NS3", + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_CMT_MUX_MMCM_CLKFBIN", + "HCLK_CMT_BUFMR_PHASEREF0", + "HCLK_CMT_IBURSTPENDING0", + "HCLK_CMT_BUFMRCE_CEINP1", + "HCLK_CMT_MUX_CLKINT_0", + "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "HCLK_CMT_MUX_CLK_MMCM2", + "HCLK_CMT_MUX_CLK_0", + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_CMT_MUX_CLK_PLL7", + "HCLK_CMT_MUX_CLK_MMCM13", + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_CMT_PHASERIN_RCLK1", + "HCLK_CMT_BUFMRCE_O0", + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_CMT_BUFMRCE_O1", + "HCLK_CMT_CK_IN9", + "HCLK_CMT_MUX_CLK_PLL1", + "HCLK_CMT_PHY_CONTROL_IRANKA0", + "HCLK_CMT_MUX_MMCM_MUXED0", + "HCLK_CMT_IBURST1", + "HCLK_CMT_FREQ_REF_NS2", + "HCLK_CMT_MUX_OUT_FREQ_REF2", + "HCLK_CMT_PREF_BOUNCE1", + "HCLK_CMT_CK_IN5", + "HCLK_CMT_PREF_BOUNCE0", + "HCLK_CMT_CK_IN7", + "HCLK_CMT_MUX_CLK_2", + "HCLK_CMT_BUFMRCE_CEINP0", + "HCLK_CMT_PHY_CONTROL_IRANKA1", + "HCLK_CMT_IBURST0", + "HCLK_CMT_FREQ_PHASER_REFMUX_0", + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_CMT_MUX_CLKINT_1", + "HCLK_CMT_PHASERIN_RCLK0", + "HCLK_CMT_MUX_CLK_PLL2", + "HCLK_CMT_MUX_CLK_MMCM6", + "HCLK_CMT_CK_IN6", + "HCLK_CMT_MUX_OUT_FREQ_REF3", + "HCLK_CMT_MUX_CLK_8", + "HCLK_CMT_CK_IN0", + "HCLK_CMT_MUX_PLLE2_CLKIN2", + "HCLK_CMT_MUX_CLK_1", + "HCLK_CMT_BUFMR_INP0", + "HCLK_CMT_BUFMR_INP1", + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_CMT_CK_IN10", + "HCLK_CMT_MUX_CLK_MMCM10", + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_CMT_PHY_SYNC_BB", + "HCLK_CMT_ECALIB0", + "HCLK_CMT_MUX_CLK_PLL4", + "HCLK_CMT_PREF_CLKOUT", + "HCLK_CMT_CK_BUFHCLK5" + ], + "pips": { + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_BUFMRCE_O0->>HCLK_CMT_BUFMR_PHASEREF0": { + "src_wire": "HCLK_CMT_BUFMRCE_O0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_PHASEREF0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_BUFMRCE_O1->>HCLK_CMT_BUFMR_PHASEREF1": { + "src_wire": "HCLK_CMT_BUFMRCE_O1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_PHASEREF1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLKINT_0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLKINT_1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { + "src_wire": "HCLK_CMT_MUX_CLKINT_0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF3->>HCLK_CMT_FREQ_REF_NS3": { + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_BUFMR_CE1->HCLK_CMT_BUFMRCE_CEINP1": { + "src_wire": "HCLK_CMT_BUFMR_CE1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMRCE_CEINP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_BUFMR_CE0->HCLK_CMT_BUFMRCE_CEINP0": { + "src_wire": "HCLK_CMT_BUFMR_CE0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMRCE_CEINP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { + "src_wire": "HCLK_CMT_MUX_CLKINT_3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { + "src_wire": "HCLK_CMT_MUX_CLKINT_1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF1->>HCLK_CMT_FREQ_REF_NS1": { + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLKINT_0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { + "src_wire": "HCLK_CMT_MUX_CLKINT_2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CCIO1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF2->>HCLK_CMT_FREQ_REF_NS2": { + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP0": { + "src_wire": "HCLK_CMT_MUX_CLKINT_1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { + "src_wire": "HCLK_CMT_CCIO3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN9": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN11": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CCIO0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN0": { + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN7": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_BUFMR_INP1": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN10": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF0->>HCLK_CMT_FREQ_REF_NS0": { + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN2": { + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN1": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN12": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN4": { + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN5": { + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN8": { + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN6": { + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN3": { + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN13": { + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_DSP_L.json b/kintex7/tile_type_HCLK_DSP_L.json new file mode 100644 index 0000000..35e5029 --- /dev/null +++ b/kintex7/tile_type_HCLK_DSP_L.json @@ -0,0 +1,135 @@ +{ + "tile_type": "HCLK_DSP_L", + "sites": [], + "wires": [ + "HCLK_DSP_ACIN18", + "HCLK_DSP_PCIN28", + "HCLK_DSP_ACIN12", + "HCLK_DSP_ACIN29", + "HCLK_DSP_CK_IN10", + "HCLK_DSP_PCIN20", + "HCLK_DSP_MULTSIGNIN", + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_DSP_CK_IN12", + "HCLK_DSP_ACIN28", + "HCLK_DSP_BCIN13", + "HCLK_DSP_PCIN13", + "HCLK_DSP_BCIN12", + "HCLK_DSP_BCIN1", + "HCLK_DSP_BCIN17", + "HCLK_DSP_PCIN46", + "HCLK_DSP_PCIN43", + "HCLK_DSP_CK_IN5", + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_DSP_BCIN5", + "HCLK_DSP_CK_IN2", + "HCLK_DSP_ACIN4", + "HCLK_DSP_PCIN14", + "HCLK_DSP_ACIN8", + "HCLK_DSP_PCIN32", + "HCLK_DSP_PCIN2", + "HCLK_DSP_PCIN24", + "HCLK_DSP_PCIN25", + "HCLK_DSP_PCIN4", + "HCLK_DSP_CK_IN3", + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_DSP_ACIN6", + "HCLK_DSP_CK_IN4", + "HCLK_DSP_PCIN10", + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_DSP_PCIN45", + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_DSP_BCIN9", + "HCLK_DSP_ACIN11", + "HCLK_DSP_PCIN6", + "HCLK_DSP_PCIN39", + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_DSP_PCIN16", + "HCLK_DSP_BCIN0", + "HCLK_DSP_PCIN36", + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_DSP_BCIN14", + "HCLK_DSP_PCIN47", + "HCLK_DSP_ACIN24", + "HCLK_DSP_ACIN16", + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_DSP_PCIN19", + "HCLK_DSP_PCIN34", + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_DSP_PCIN11", + "HCLK_DSP_ACIN1", + "HCLK_DSP_BCIN2", + "HCLK_DSP_PCIN7", + "HCLK_DSP_CK_IN0", + "HCLK_DSP_PCIN30", + "HCLK_DSP_BCIN3", + "HCLK_DSP_PCIN17", + "HCLK_DSP_ACIN15", + "HCLK_DSP_PCIN12", + "HCLK_DSP_PCIN38", + "HCLK_DSP_ACIN7", + "HCLK_DSP_BCIN11", + "HCLK_DSP_CK_IN13", + "HCLK_DSP_ACIN23", + "HCLK_DSP_ACIN19", + "HCLK_DSP_BCIN8", + "HCLK_DSP_BCIN7", + "HCLK_DSP_PCIN1", + "HCLK_DSP_PCIN22", + "HCLK_DSP_ACIN0", + "HCLK_DSP_PCIN29", + "HCLK_DSP_ACIN27", + "HCLK_DSP_PCIN40", + "HCLK_DSP_PCIN33", + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_DSP_PCIN0", + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_DSP_BCIN16", + "HCLK_DSP_ACIN26", + "HCLK_DSP_ACIN22", + "HCLK_DSP_ACIN14", + "HCLK_DSP_ACIN20", + "HCLK_DSP_PCIN41", + "HCLK_DSP_CK_IN1", + "HCLK_DSP_PCIN18", + "HCLK_DSP_CK_IN9", + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_DSP_BCIN10", + "HCLK_DSP_ACIN17", + "HCLK_DSP_PCIN42", + "HCLK_DSP_CK_IN8", + "HCLK_DSP_PCIN35", + "HCLK_DSP_CK_IN6", + "HCLK_DSP_ACIN10", + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_DSP_ACIN3", + "HCLK_DSP_PCIN15", + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_DSP_ACIN21", + "HCLK_DSP_PCIN27", + "HCLK_DSP_CARRYCASCIN", + "HCLK_DSP_BCIN4", + "HCLK_DSP_BCIN6", + "HCLK_DSP_PCIN23", + "HCLK_DSP_CK_IN7", + "HCLK_DSP_ACIN9", + "HCLK_DSP_PCIN31", + "HCLK_DSP_PCIN44", + "HCLK_DSP_CK_IN11", + "HCLK_DSP_PCIN5", + "HCLK_DSP_PCIN26", + "HCLK_DSP_ACIN13", + "HCLK_DSP_PCIN9", + "HCLK_DSP_PCIN37", + "HCLK_DSP_ACIN5", + "HCLK_DSP_PCIN21", + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_DSP_PCIN8", + "HCLK_DSP_ACIN2", + "HCLK_DSP_BCIN15", + "HCLK_DSP_PCIN3", + "HCLK_DSP_ACIN25" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_DSP_R.json b/kintex7/tile_type_HCLK_DSP_R.json new file mode 100644 index 0000000..50e350b --- /dev/null +++ b/kintex7/tile_type_HCLK_DSP_R.json @@ -0,0 +1,135 @@ +{ + "tile_type": "HCLK_DSP_R", + "sites": [], + "wires": [ + "HCLK_DSP_ACIN18", + "HCLK_DSP_PCIN28", + "HCLK_DSP_ACIN12", + "HCLK_DSP_ACIN29", + "HCLK_DSP_CK_IN10", + "HCLK_DSP_PCIN20", + "HCLK_DSP_MULTSIGNIN", + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_DSP_CK_IN12", + "HCLK_DSP_ACIN28", + "HCLK_DSP_BCIN13", + "HCLK_DSP_PCIN13", + "HCLK_DSP_BCIN12", + "HCLK_DSP_BCIN1", + "HCLK_DSP_BCIN17", + "HCLK_DSP_PCIN46", + "HCLK_DSP_PCIN43", + "HCLK_DSP_CK_IN5", + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_DSP_BCIN5", + "HCLK_DSP_CK_IN2", + "HCLK_DSP_ACIN4", + "HCLK_DSP_PCIN14", + "HCLK_DSP_ACIN8", + "HCLK_DSP_PCIN32", + "HCLK_DSP_PCIN2", + "HCLK_DSP_PCIN24", + "HCLK_DSP_PCIN25", + "HCLK_DSP_PCIN4", + "HCLK_DSP_CK_IN3", + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_DSP_ACIN6", + "HCLK_DSP_CK_IN4", + "HCLK_DSP_PCIN10", + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_DSP_PCIN45", + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_DSP_BCIN9", + "HCLK_DSP_ACIN11", + "HCLK_DSP_PCIN6", + "HCLK_DSP_PCIN39", + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_DSP_PCIN16", + "HCLK_DSP_BCIN0", + "HCLK_DSP_PCIN36", + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_DSP_BCIN14", + "HCLK_DSP_PCIN47", + "HCLK_DSP_ACIN24", + "HCLK_DSP_ACIN16", + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_DSP_PCIN19", + "HCLK_DSP_PCIN34", + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_DSP_PCIN11", + "HCLK_DSP_ACIN1", + "HCLK_DSP_BCIN2", + "HCLK_DSP_PCIN7", + "HCLK_DSP_CK_IN0", + "HCLK_DSP_PCIN30", + "HCLK_DSP_BCIN3", + "HCLK_DSP_PCIN17", + "HCLK_DSP_ACIN15", + "HCLK_DSP_PCIN12", + "HCLK_DSP_PCIN38", + "HCLK_DSP_ACIN7", + "HCLK_DSP_BCIN11", + "HCLK_DSP_CK_IN13", + "HCLK_DSP_ACIN23", + "HCLK_DSP_ACIN19", + "HCLK_DSP_BCIN8", + "HCLK_DSP_BCIN7", + "HCLK_DSP_PCIN1", + "HCLK_DSP_PCIN22", + "HCLK_DSP_ACIN0", + "HCLK_DSP_PCIN29", + "HCLK_DSP_ACIN27", + "HCLK_DSP_PCIN40", + "HCLK_DSP_PCIN33", + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_DSP_PCIN0", + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_DSP_BCIN16", + "HCLK_DSP_ACIN26", + "HCLK_DSP_ACIN22", + "HCLK_DSP_ACIN14", + "HCLK_DSP_ACIN20", + "HCLK_DSP_PCIN41", + "HCLK_DSP_CK_IN1", + "HCLK_DSP_PCIN18", + "HCLK_DSP_CK_IN9", + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_DSP_BCIN10", + "HCLK_DSP_ACIN17", + "HCLK_DSP_PCIN42", + "HCLK_DSP_CK_IN8", + "HCLK_DSP_PCIN35", + "HCLK_DSP_CK_IN6", + "HCLK_DSP_ACIN10", + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_DSP_ACIN3", + "HCLK_DSP_PCIN15", + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_DSP_ACIN21", + "HCLK_DSP_PCIN27", + "HCLK_DSP_CARRYCASCIN", + "HCLK_DSP_BCIN4", + "HCLK_DSP_BCIN6", + "HCLK_DSP_PCIN23", + "HCLK_DSP_CK_IN7", + "HCLK_DSP_ACIN9", + "HCLK_DSP_PCIN31", + "HCLK_DSP_PCIN44", + "HCLK_DSP_CK_IN11", + "HCLK_DSP_PCIN5", + "HCLK_DSP_PCIN26", + "HCLK_DSP_ACIN13", + "HCLK_DSP_PCIN9", + "HCLK_DSP_PCIN37", + "HCLK_DSP_ACIN5", + "HCLK_DSP_PCIN21", + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_DSP_PCIN8", + "HCLK_DSP_ACIN2", + "HCLK_DSP_BCIN15", + "HCLK_DSP_PCIN3", + "HCLK_DSP_ACIN25" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_FEEDTHRU_1.json b/kintex7/tile_type_HCLK_FEEDTHRU_1.json new file mode 100644 index 0000000..ea7da35 --- /dev/null +++ b/kintex7/tile_type_HCLK_FEEDTHRU_1.json @@ -0,0 +1,37 @@ +{ + "tile_type": "HCLK_FEEDTHRU_1", + "sites": [], + "wires": [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK3", + "HCLK_FEEDTHRU_1_CK_BUFHCLK5", + "HCLK_FEEDTHRU_1_CK_IN11", + "HCLK_FEEDTHRU_1_CK_BUFHCLK9", + "HCLK_FEEDTHRU_1_CK_IN12", + "HCLK_FEEDTHRU_1_CK_BUFRCLK0", + "HCLK_FEEDTHRU_1_CK_IN8", + "HCLK_FEEDTHRU_1_CK_BUFHCLK1", + "HCLK_FEEDTHRU_1_CK_BUFRCLK1", + "HCLK_FEEDTHRU_1_CK_IN1", + "HCLK_FEEDTHRU_1_CK_BUFHCLK7", + "HCLK_FEEDTHRU_1_CK_IN4", + "HCLK_FEEDTHRU_1_CK_BUFRCLK2", + "HCLK_FEEDTHRU_1_CK_IN9", + "HCLK_FEEDTHRU_1_CK_BUFHCLK0", + "HCLK_FEEDTHRU_1_CK_IN3", + "HCLK_FEEDTHRU_1_CK_BUFHCLK2", + "HCLK_FEEDTHRU_1_CK_BUFHCLK10", + "HCLK_FEEDTHRU_1_CK_BUFHCLK3", + "HCLK_FEEDTHRU_1_CK_IN2", + "HCLK_FEEDTHRU_1_CK_BUFHCLK6", + "HCLK_FEEDTHRU_1_CK_IN10", + "HCLK_FEEDTHRU_1_CK_IN13", + "HCLK_FEEDTHRU_1_CK_IN6", + "HCLK_FEEDTHRU_1_CK_BUFHCLK11", + "HCLK_FEEDTHRU_1_CK_BUFHCLK8", + "HCLK_FEEDTHRU_1_CK_IN7", + "HCLK_FEEDTHRU_1_CK_IN0", + "HCLK_FEEDTHRU_1_CK_BUFHCLK4", + "HCLK_FEEDTHRU_1_CK_IN5" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_FEEDTHRU_2.json b/kintex7/tile_type_HCLK_FEEDTHRU_2.json new file mode 100644 index 0000000..7717189 --- /dev/null +++ b/kintex7/tile_type_HCLK_FEEDTHRU_2.json @@ -0,0 +1,37 @@ +{ + "tile_type": "HCLK_FEEDTHRU_2", + "sites": [], + "wires": [ + "HCLK_FEEDTHRU_2_CK_BUFHCLK8", + "HCLK_FEEDTHRU_2_CK_BUFHCLK5", + "HCLK_FEEDTHRU_2_CK_IN11", + "HCLK_FEEDTHRU_2_CK_IN1", + "HCLK_FEEDTHRU_2_CK_BUFRCLK0", + "HCLK_FEEDTHRU_2_CK_BUFHCLK2", + "HCLK_FEEDTHRU_2_CK_IN9", + "HCLK_FEEDTHRU_2_CK_IN2", + "HCLK_FEEDTHRU_2_CK_BUFHCLK11", + "HCLK_FEEDTHRU_2_CK_BUFHCLK6", + "HCLK_FEEDTHRU_2_CK_IN0", + "HCLK_FEEDTHRU_2_CK_BUFHCLK7", + "HCLK_FEEDTHRU_2_CK_IN6", + "HCLK_FEEDTHRU_2_CK_BUFHCLK4", + "HCLK_FEEDTHRU_2_CK_BUFRCLK2", + "HCLK_FEEDTHRU_2_CK_IN13", + "HCLK_FEEDTHRU_2_CK_BUFHCLK3", + "HCLK_FEEDTHRU_2_CK_IN12", + "HCLK_FEEDTHRU_2_CK_IN7", + "HCLK_FEEDTHRU_2_CK_BUFRCLK3", + "HCLK_FEEDTHRU_2_CK_BUFHCLK10", + "HCLK_FEEDTHRU_2_CK_BUFRCLK1", + "HCLK_FEEDTHRU_2_CK_IN3", + "HCLK_FEEDTHRU_2_CK_IN10", + "HCLK_FEEDTHRU_2_CK_BUFHCLK0", + "HCLK_FEEDTHRU_2_CK_BUFHCLK9", + "HCLK_FEEDTHRU_2_CK_IN4", + "HCLK_FEEDTHRU_2_CK_BUFHCLK1", + "HCLK_FEEDTHRU_2_CK_IN8", + "HCLK_FEEDTHRU_2_CK_IN5" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_FIFO_L.json b/kintex7/tile_type_HCLK_FIFO_L.json new file mode 100644 index 0000000..79bafba --- /dev/null +++ b/kintex7/tile_type_HCLK_FIFO_L.json @@ -0,0 +1,45 @@ +{ + "tile_type": "HCLK_FIFO_L", + "sites": [], + "wires": [ + "HCLK_FIFO_CK_IN1", + "HCLK_FIFO_CK_IN3", + "HCLK_FIFO_CK_BUFHCLK8", + "HCLK_FIFO_PERFCLK1", + "HCLK_FIFO_PERFCLK3", + "HCLK_FIFO_CK_BUFHCLK6", + "HCLK_FIFO_CCIO0", + "HCLK_FIFO_CK_BUFHCLK1", + "HCLK_FIFO_CK_BUFHCLK10", + "HCLK_FIFO_PERFCLK2", + "HCLK_FIFO_CK_IN7", + "HCLK_FIFO_CK_IN13", + "HCLK_FIFO_CK_IN2", + "HCLK_FIFO_CK_BUFHCLK4", + "HCLK_FIFO_CK_IN4", + "HCLK_FIFO_CK_IN8", + "HCLK_FIFO_CCIO1", + "HCLK_FIFO_CK_BUFHCLK9", + "HCLK_FIFO_CK_IN12", + "HCLK_FIFO_CK_BUFHCLK3", + "HCLK_FIFO_CK_BUFHCLK5", + "HCLK_FIFO_CK_IN10", + "HCLK_FIFO_CCIO2", + "HCLK_FIFO_CK_BUFHCLK7", + "HCLK_FIFO_PERFCLK0", + "HCLK_FIFO_CK_BUFHCLK0", + "HCLK_FIFO_CK_BUFHCLK2", + "HCLK_FIFO_CK_IN11", + "HCLK_FIFO_CK_IN0", + "HCLK_FIFO_CK_IN6", + "HCLK_FIFO_CK_IN5", + "HCLK_FIFO_CK_BUFHCLK11", + "HCLK_FIFO_CK_BUFRCLK3", + "HCLK_FIFO_CK_BUFRCLK1", + "HCLK_FIFO_CK_IN9", + "HCLK_FIFO_CCIO3", + "HCLK_FIFO_CK_BUFRCLK0", + "HCLK_FIFO_CK_BUFRCLK2" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_GTX.json b/kintex7/tile_type_HCLK_GTX.json new file mode 100644 index 0000000..a70a1fc --- /dev/null +++ b/kintex7/tile_type_HCLK_GTX.json @@ -0,0 +1,21 @@ +{ + "tile_type": "HCLK_GTX", + "sites": [], + "wires": [ + "HCLK_GTX_CK_IN1", + "HCLK_GTX_CK_IN6", + "HCLK_GTX_CK_IN13", + "HCLK_GTX_CK_IN9", + "HCLK_GTX_CK_IN3", + "HCLK_GTX_CK_IN2", + "HCLK_GTX_CK_IN12", + "HCLK_GTX_CK_IN8", + "HCLK_GTX_CK_IN5", + "HCLK_GTX_CK_IN11", + "HCLK_GTX_CK_IN7", + "HCLK_GTX_CK_IN10", + "HCLK_GTX_CK_IN0", + "HCLK_GTX_CK_IN4" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_INT_INTERFACE.json b/kintex7/tile_type_HCLK_INT_INTERFACE.json new file mode 100644 index 0000000..e499fba --- /dev/null +++ b/kintex7/tile_type_HCLK_INT_INTERFACE.json @@ -0,0 +1,49 @@ +{ + "tile_type": "HCLK_INT_INTERFACE", + "sites": [], + "wires": [ + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_INT_INTERFACE_REFCK_EASTCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_REFCK_WESTCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_IN7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CCIO1", + "HCLK_INT_INTERFACE_REFCK_WESTCLK0", + "HCLK_INT_INTERFACE_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN10", + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN0", + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_INT_INTERFACE_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN9", + "HCLK_INT_INTERFACE_CCIO0", + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_IN3", + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CCIO2", + "HCLK_INT_INTERFACE_REFCK_EASTCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_IN4", + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_INT_INTERFACE_CK_IN12", + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_INT_INTERFACE_CK_IN1", + "HCLK_INT_INTERFACE_CCIO3", + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_IN6" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_IOB.json b/kintex7/tile_type_HCLK_IOB.json new file mode 100644 index 0000000..d3c22d7 --- /dev/null +++ b/kintex7/tile_type_HCLK_IOB.json @@ -0,0 +1,41 @@ +{ + "tile_type": "HCLK_IOB", + "sites": [], + "wires": [ + "HCLK_IOB_PERFCLK2", + "HCLK_IOB_CK_BUFHCLK11", + "HCLK_IOB_CK_BUFHCLK7", + "HCLK_IOB_PERFCLK3", + "HCLK_IOB_CK_BUFHCLK1", + "HCLK_IOB_CK_IN9", + "HCLK_IOB_CK_BUFHCLK6", + "HCLK_IOB_CK_BUFHCLK4", + "HCLK_IOB_CK_BUFHCLK0", + "HCLK_IOB_CK_IN5", + "HCLK_IOB_CK_IN1", + "HCLK_IOB_PERFCLK1", + "HCLK_IOB_PERFCLK0", + "HCLK_IOB_CK_BUFRCLK1", + "HCLK_IOB_CK_IN10", + "HCLK_IOB_CK_BUFHCLK8", + "HCLK_IOB_CK_BUFHCLK3", + "HCLK_IOB_CK_BUFHCLK5", + "HCLK_IOB_CK_BUFRCLK0", + "HCLK_IOB_CK_IN2", + "HCLK_IOB_CK_IN7", + "HCLK_IOB_CK_IN6", + "HCLK_IOB_CK_BUFRCLK2", + "HCLK_IOB_CK_IN0", + "HCLK_IOB_CK_IN4", + "HCLK_IOB_CK_IN8", + "HCLK_IOB_CK_IN11", + "HCLK_IOB_CK_BUFRCLK3", + "HCLK_IOB_CK_BUFHCLK9", + "HCLK_IOB_CK_BUFHCLK2", + "HCLK_IOB_CK_IN12", + "HCLK_IOB_CK_IN13", + "HCLK_IOB_CK_BUFHCLK10", + "HCLK_IOB_CK_IN3" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_IOI.json b/kintex7/tile_type_HCLK_IOI.json new file mode 100644 index 0000000..73e4663 --- /dev/null +++ b/kintex7/tile_type_HCLK_IOI.json @@ -0,0 +1,1967 @@ +{ + "tile_type": "HCLK_IOI", + "sites": [ + { + "y_coord": 4, + "name": "X0Y4", + "prefix": "BUFIO", + "type": "BUFIO", + "site_pins": { + "O": "HCLK_IOI_BUFIO_O3", + "I": "HCLK_IOI_IO_PLL_CLK3" + }, + "x_coord": 0 + }, + { + "y_coord": 3, + "name": "X0Y3", + "prefix": "BUFIO", + "type": "BUFIO", + "site_pins": { + "O": "HCLK_IOI_BUFIO_O2", + "I": "HCLK_IOI_IO_PLL_CLK2" + }, + "x_coord": 0 + }, + { + "y_coord": 6, + "name": "X0Y6", + "prefix": "BUFIO", + "type": "BUFIO", + "site_pins": { + "O": "HCLK_IOI_BUFIO_O1", + "I": "HCLK_IOI_IO_PLL_CLK1" + }, + "x_coord": 0 + }, + { + "y_coord": 5, + "name": "X0Y5", + "prefix": "BUFIO", + "type": "BUFIO", + "site_pins": { + "O": "HCLK_IOI_BUFIO_O0", + "I": "HCLK_IOI_IO_PLL_CLK0" + }, + "x_coord": 0 + }, + { + "y_coord": 4, + "name": "X0Y4", + "prefix": "BUFR", + "type": "BUFR", + "site_pins": { + "CE": "HCLK_IOI_BUFR3_CE", + "O": "HCLK_IOI_RCLK_OUT3", + "I": "HCLK_IOI_RCLK_BEFORE_DIV3", + "CLR": "HCLK_IOI_BUFR3_CLR" + }, + "x_coord": 0 + }, + { + "y_coord": 3, + "name": "X0Y3", + "prefix": "BUFR", + "type": "BUFR", + "site_pins": { + "CE": "HCLK_IOI_BUFR2_CE", + "O": "HCLK_IOI_RCLK_OUT2", + "I": "HCLK_IOI_RCLK_BEFORE_DIV2", + "CLR": "HCLK_IOI_BUFR2_CLR" + }, + "x_coord": 0 + }, + { + "y_coord": 6, + "name": "X0Y6", + "prefix": "BUFR", + "type": "BUFR", + "site_pins": { + "CE": "HCLK_IOI_BUFR1_CE", + "O": "HCLK_IOI_RCLK_OUT1", + "I": "HCLK_IOI_RCLK_BEFORE_DIV1", + "CLR": "HCLK_IOI_BUFR1_CLR" + }, + "x_coord": 0 + }, + { + "y_coord": 5, + "name": "X0Y5", + "prefix": "BUFR", + "type": "BUFR", + "site_pins": { + "CE": "HCLK_IOI_BUFR0_CE", + "O": "HCLK_IOI_RCLK_OUT0", + "I": "HCLK_IOI_RCLK_BEFORE_DIV0", + "CLR": "HCLK_IOI_BUFR0_CLR" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IDELAYCTRL", + "type": "IDELAYCTRL", + "site_pins": { + "UPPULSEOUT": "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "OUTN65": "HCLK_IOI_IDELAYCTRL_OUTN65", + "REFCLK": "HCLK_IOI_IDELAYCTRL_REFCLK", + "DNPULSEOUT": "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "RDY": "HCLK_IOI_IDELAYCTRL_RDY", + "OUTN1": "HCLK_IOI_IDELAYCTRL_OUTN1", + "RST": "HCLK_IOI_IDELAYCTRL_RST" + }, + "x_coord": 0 + } + ], + "wires": [ + "HCLK_IOI_IO_PLL_CLK1", + "HCLK_IOI_IOCLK_PLL2", + "HCLK_IOI_CK_IN7", + "HCLK_IOI_CK_IN3", + "HCLK_IOI_CK_BUFHCLK7", + "HCLK_IOI_CK_BUFRCLK2", + "HCLK_DCI_DCISCLK", + "HCLK_IOI_RCLK_IMUX3", + "HCLK_IOI_RCLK2RCLK0", + "HCLK_IOI_IOCLK3", + "HCLK_IOI_IDELAYCTRL_OUTN1", + "HCLK_IOI_IDELAYCTRL_RDY", + "HCLK_IOI_CK_BUFHCLK3", + "HCLK_IOI_BUFR0_CE", + "HCLK_IOI_BUFR2_CE", + "HCLK_IOI_BUFIO_O0", + "HCLK_IOI_RCLK_OUT1", + "HCLK_IOI_IO_PLL_CLK3_DMUX", + "HCLK_IOI_DCI_TSTHLP", + "HCLK_IOI_CK_IN4", + "HCLK_IOI_CK_IGCLK7", + "HCLK_RCLK_DIV_CLR3", + "HCLK_IOI_CK_BUFHCLK9", + "HCLK_IOI_IDELAYCTRL_RST", + "HCLK_IOI_RCLK_OUT2", + "HCLK_IOI_BUFIO_O3", + "HCLK_IOI_CK_IN6", + "HCLK_DCI_DCIADDRESS0", + "HCLK_RCLK_DIV_CE1", + "HCLK_IOI_CK_IGCLK11", + "HCLK_IOI_RCLK_BEFORE_DIV1", + "HCLK_IOI_CK_IGCLK6", + "HCLK_IOI_LEAF_GCLK_TOP2", + "HCLK_IOI_RCLK2IO2", + "HCLK_IOI_IOCLK_PLL1", + "HCLK_IOI_CK_IGCLK2", + "HCLK_IOI_LEAF_GCLK_BOT5", + "HCLK_IOI_RCLK_IMUX0", + "HCLK_IOI_CK_BUFHCLK2", + "HCLK_IOI_BUFIO_O1", + "HCLK_IOI_CK_BUFHCLK1", + "HCLK_IOI_RCLK3", + "HCLK_IOI_CK_IN2", + "HCLK_RCLK_DIV_CLR1", + "HCLK_IOI_CK_IGCLK8", + "HCLK_IOI_LEAF_GCLK_BOT2", + "HCLK_IOI_CK_IN11", + "HCLK_IOI_IO_PLL_CLK3", + "HCLK_IOI_CK_BUFHCLK11", + "HCLK_IOI_BUFR2_CLR", + "HCLK_IOI_CK_IGCLK9", + "HCLK_IOI_RCLK2RCLK2", + "HCLK_DCI_DCIADDRESS1", + "HCLK_IOI_DCI_TSTRST", + "HCLK_IOI_CK_IN12", + "HCLK_IOI_RCLK2IO1", + "HCLK_IOI_INT_DCI_EN", + "HCLK_IOI_RCLK2", + "HCLK_IOI_LEAF_GCLK_BOT4", + "HCLK_DCI_DCIDATA", + "HCLK_IOI_I2IOCLK_BOT1", + "HCLK_IOI_RCLK2IO3", + "HCLK_IOI_I2IOCLK_TOP1", + "HCLK_IOI_RCLK_BEFORE_DIV0", + "HCLK_IOI_I2IOCLK_TOP0", + "HCLK_IOI_CK_IGCLK5", + "HCLK_IOI_CK_IGCLK0", + "HCLK_RCLK_DIV_CE0", + "HCLK_IOI_DCI_TSTHLN", + "HCLK_IOI_IO_PLL_CLK0_DMUX", + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "HCLK_IOI_BUFR3_CLR", + "HCLK_IOI_IO_PLL_CLK2", + "HCLK_IOI_CK_IN8", + "HCLK_IOI_CK_IN13", + "HCLK_IOI_RCLK1", + "HCLK_IOI_CK_IN5", + "HCLK_IOI_RCLK_OUT3", + "HCLK_IOI_I2IOCLK_BOT0", + "HCLK_IOI_CK_BUFRCLK0", + "HCLK_IOI_RCLK2IO0", + "HCLK_IOI_CK_BUFHCLK4", + "HCLK_IOI_LEAF_GCLK_TOP1", + "HCLK_IOI_IO_PLL_CLK2_DMUX", + "HCLK_IOI_BUFR1_CE", + "HCLK_IOI_CK_IN9", + "HCLK_DCI_DCIADDRESS2", + "HCLK_IOI_RCLK_BEFORE_DIV2", + "HCLK_IOI_LEAF_GCLK_TOP4", + "HCLK_IOI_CK_BUFHCLK10", + "HCLK_IOI_LEAF_GCLK_BOT0", + "HCLK_IOI_BUFR1_CLR", + "HCLK_IOI_BUFR0_CLR", + "HCLK_IOI_IOCLK_PLL3", + "HCLK_IOI_LEAF_GCLK_BOT1", + "HCLK_IOI_BUFR3_CE", + "HCLK_IOI_CK_IGCLK10", + "HCLK_IOI_DCI_DCIDONE", + "HCLK_DCI_DCIREFIOUPDATE", + "HCLK_IOI_IO_PLL_CLK1_DMUX", + "HCLK_IOI_IO_PLL_CLK0", + "HCLK_IOI_LEAF_GCLK_BOT3", + "HCLK_IOI_LEAF_GCLK_TOP3", + "HCLK_IOI_RCLK_OUT0", + "HCLK_IOI_CK_BUFHCLK0", + "HCLK_RCLK_DIV_CE3", + "HCLK_RCLK_DIV_CLR0", + "HCLK_IOI_CK_IN10", + "HCLK_DCI_DCIIOUPDATE", + "HCLK_IOI_CK_BUFHCLK5", + "HCLK_IOI_CK_IGCLK4", + "HCLK_IOI_CK_BUFRCLK3", + "HCLK_IOI_CK_IGCLK1", + "HCLK_RCLK_DIV_CE2", + "HCLK_IOI_DCI_TSTCLK", + "HCLK_IOI_RCLK2RCLK3", + "HCLK_IOI_RCLK_IMUX1", + "HCLK_IOI_IOCLK2", + "HCLK_IOI_LEAF_GCLK_TOP5", + "HCLK_RCLK_DIV_CLR2", + "HCLK_IOI_RCLK0", + "HCLK_IOI_RCLK_BEFORE_DIV3", + "HCLK_IOI_IDELAYCTRL_OUTN65", + "HCLK_IOI_BUFIO_O2", + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "HCLK_IOI_RCLK2RCLK1", + "HCLK_IOI_CK_IN0", + "HCLK_IOI_IOCLK_PLL0", + "HCLK_IOI_IOCLK0", + "HCLK_IOI_CK_BUFRCLK1", + "HCLK_IOI_RCLK_IMUX2", + "HCLK_IOI_CK_IN1", + "HCLK_IOI_CK_BUFHCLK6", + "HCLK_IOI_IOCLK1", + "HCLK_IOI_CK_IGCLK3", + "HCLK_IOI_CK_BUFHCLK8", + "HCLK_IOI_LEAF_GCLK_TOP0", + "HCLK_IOI_IDELAYCTRL_REFCLK" + ], + "pips": { + "HCLK_IOI.HCLK_IOI_RCLK2RCLK2->>HCLK_IOI_CK_BUFRCLK2": { + "src_wire": "HCLK_IOI_RCLK2RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_BUFRCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK2RCLK1->>HCLK_IOI_CK_BUFRCLK1": { + "src_wire": "HCLK_IOI_RCLK2RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_BUFRCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFHCLK7->>HCLK_IOI_CK_IGCLK7": { + "src_wire": "HCLK_IOI_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK_IMUX2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_IO_PLL_CLK3": { + "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFHCLK10->>HCLK_IOI_CK_IGCLK10": { + "src_wire": "HCLK_IOI_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK_IMUX3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK_IMUX1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_BUFIO_O0->>HCLK_IOI_IOCLK0": { + "src_wire": "HCLK_IOI_BUFIO_O0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IOCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_RCLK_DIV_CE2->HCLK_IOI_BUFR2_CE": { + "src_wire": "HCLK_RCLK_DIV_CE2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR2_CE", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT3->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFHCLK5->>HCLK_IOI_CK_IGCLK5": { + "src_wire": "HCLK_IOI_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK_IMUX2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFHCLK0->>HCLK_IOI_CK_IGCLK0": { + "src_wire": "HCLK_IOI_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_IOCLK_PLL3->>HCLK_IOI_IO_PLL_CLK3_DMUX": { + "src_wire": "HCLK_IOI_IOCLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP2->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT4->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_BUFIO_O1->>HCLK_IOI_IOCLK1": { + "src_wire": "HCLK_IOI_BUFIO_O1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IOCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK_IMUX0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT1->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_BEFORE_DIV1->>HCLK_IOI_RCLK_OUT1": { + "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_pseudo": "1", + "dst_wire": "HCLK_IOI_RCLK_OUT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_BEFORE_DIV2->>HCLK_IOI_RCLK_OUT2": { + "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_pseudo": "1", + "dst_wire": "HCLK_IOI_RCLK_OUT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_I2IOCLK_BOT1->>HCLK_IOI_IO_PLL_CLK3_DMUX": { + "src_wire": "HCLK_IOI_I2IOCLK_BOT1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK_IMUX0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP0->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_I2IOCLK_BOT0->>HCLK_IOI_IO_PLL_CLK2_DMUX": { + "src_wire": "HCLK_IOI_I2IOCLK_BOT0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP5->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_I2IOCLK_TOP0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { + "src_wire": "HCLK_IOI_I2IOCLK_TOP0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFHCLK4->>HCLK_IOI_CK_IGCLK4": { + "src_wire": "HCLK_IOI_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_IO_PLL_CLK1": { + "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK_IMUX3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_OUT2->>HCLK_IOI_RCLK2RCLK2": { + "src_wire": "HCLK_IOI_RCLK_OUT2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2RCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_BUFIO_O3->>HCLK_IOI_IOCLK3": { + "src_wire": "HCLK_IOI_BUFIO_O3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IOCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFRCLK0->>HCLK_IOI_RCLK2IO0": { + "src_wire": "HCLK_IOI_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2IO0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK_IMUX0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK2RCLK3->>HCLK_IOI_CK_BUFRCLK3": { + "src_wire": "HCLK_IOI_RCLK2RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_BUFRCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFHCLK3->>HCLK_IOI_CK_IGCLK3": { + "src_wire": "HCLK_IOI_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK_IMUX1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_BUFIO_O2->>HCLK_IOI_IOCLK2": { + "src_wire": "HCLK_IOI_BUFIO_O2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IOCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_BEFORE_DIV3->>HCLK_IOI_RCLK_OUT3": { + "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_pseudo": "1", + "dst_wire": "HCLK_IOI_RCLK_OUT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_OUT0->>HCLK_IOI_RCLK2RCLK0": { + "src_wire": "HCLK_IOI_RCLK_OUT0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2RCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT5->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK_IMUX2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_IOCLK_PLL2->>HCLK_IOI_IO_PLL_CLK2_DMUX": { + "src_wire": "HCLK_IOI_IOCLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFRCLK3->>HCLK_IOI_RCLK2IO3": { + "src_wire": "HCLK_IOI_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2IO3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_RCLK_DIV_CLR3->HCLK_IOI_BUFR3_CLR": { + "src_wire": "HCLK_RCLK_DIV_CLR3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR3_CLR", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFHCLK8->>HCLK_IOI_CK_IGCLK8": { + "src_wire": "HCLK_IOI_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_BEFORE_DIV0->>HCLK_IOI_RCLK_OUT0": { + "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_pseudo": "1", + "dst_wire": "HCLK_IOI_RCLK_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_RCLK_DIV_CLR0->HCLK_IOI_BUFR0_CLR": { + "src_wire": "HCLK_RCLK_DIV_CLR0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR0_CLR", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK_IMUX1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_RCLK_DIV_CE3->HCLK_IOI_BUFR3_CE": { + "src_wire": "HCLK_RCLK_DIV_CE3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR3_CE", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK2RCLK0->>HCLK_IOI_CK_BUFRCLK0": { + "src_wire": "HCLK_IOI_RCLK2RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_BUFRCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_IO_PLL_CLK0": { + "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_OUT1->>HCLK_IOI_RCLK2RCLK1": { + "src_wire": "HCLK_IOI_RCLK_OUT1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2RCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_RCLK_DIV_CLR1->HCLK_IOI_BUFR1_CLR": { + "src_wire": "HCLK_RCLK_DIV_CLR1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR1_CLR", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_RCLK3": { + "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP1->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK_IMUX1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_RCLK1": { + "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK_IMUX3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP3->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFHCLK6->>HCLK_IOI_CK_IGCLK6": { + "src_wire": "HCLK_IOI_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK_IMUX0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT2->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFHCLK11->>HCLK_IOI_CK_IGCLK11": { + "src_wire": "HCLK_IOI_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_IOCLK_PLL0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { + "src_wire": "HCLK_IOI_IOCLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_RCLK2": { + "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP4->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFHCLK9->>HCLK_IOI_CK_IGCLK9": { + "src_wire": "HCLK_IOI_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT0->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_I2IOCLK_TOP1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { + "src_wire": "HCLK_IOI_I2IOCLK_TOP1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFHCLK1->>HCLK_IOI_CK_IGCLK1": { + "src_wire": "HCLK_IOI_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK_IMUX3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_IOCLK_PLL1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { + "src_wire": "HCLK_IOI_IOCLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_RCLK_DIV_CE1->HCLK_IOI_BUFR1_CE": { + "src_wire": "HCLK_RCLK_DIV_CE1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR1_CE", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFRCLK1->>HCLK_IOI_RCLK2IO1": { + "src_wire": "HCLK_IOI_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2IO1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_RCLK_DIV_CE0->HCLK_IOI_BUFR0_CE": { + "src_wire": "HCLK_RCLK_DIV_CE0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK_IMUX2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFRCLK2->>HCLK_IOI_RCLK2IO2": { + "src_wire": "HCLK_IOI_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2IO2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_IO_PLL_CLK2": { + "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_BUFHCLK2->>HCLK_IOI_CK_IGCLK2": { + "src_wire": "HCLK_IOI_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_RCLK_DIV_CLR2->HCLK_IOI_BUFR2_CLR": { + "src_wire": "HCLK_RCLK_DIV_CLR2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR2_CLR", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_RCLK0": { + "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI.HCLK_IOI_RCLK_OUT3->>HCLK_IOI_RCLK2RCLK3": { + "src_wire": "HCLK_IOI_RCLK_OUT3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2RCLK3", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_IOI3.json b/kintex7/tile_type_HCLK_IOI3.json new file mode 100644 index 0000000..d9f7480 --- /dev/null +++ b/kintex7/tile_type_HCLK_IOI3.json @@ -0,0 +1,1954 @@ +{ + "tile_type": "HCLK_IOI3", + "sites": [ + { + "y_coord": 10, + "name": "X0Y10", + "prefix": "BUFIO", + "type": "BUFIO", + "site_pins": { + "O": "HCLK_IOI_BUFIO_O3", + "I": "HCLK_IOI_IO_PLL_CLK3" + }, + "x_coord": 0 + }, + { + "y_coord": 9, + "name": "X0Y9", + "prefix": "BUFIO", + "type": "BUFIO", + "site_pins": { + "O": "HCLK_IOI_BUFIO_O2", + "I": "HCLK_IOI_IO_PLL_CLK2" + }, + "x_coord": 0 + }, + { + "y_coord": 12, + "name": "X0Y12", + "prefix": "BUFIO", + "type": "BUFIO", + "site_pins": { + "O": "HCLK_IOI_BUFIO_O1", + "I": "HCLK_IOI_IO_PLL_CLK1" + }, + "x_coord": 0 + }, + { + "y_coord": 11, + "name": "X0Y11", + "prefix": "BUFIO", + "type": "BUFIO", + "site_pins": { + "O": "HCLK_IOI_BUFIO_O0", + "I": "HCLK_IOI_IO_PLL_CLK0" + }, + "x_coord": 0 + }, + { + "y_coord": 10, + "name": "X0Y10", + "prefix": "BUFR", + "type": "BUFR", + "site_pins": { + "CE": "HCLK_IOI_BUFR3_CE", + "O": "HCLK_IOI_RCLK_OUT3", + "I": "HCLK_IOI_RCLK_BEFORE_DIV3", + "CLR": "HCLK_IOI_BUFR3_CLR" + }, + "x_coord": 0 + }, + { + "y_coord": 9, + "name": "X0Y9", + "prefix": "BUFR", + "type": "BUFR", + "site_pins": { + "CE": "HCLK_IOI_BUFR2_CE", + "O": "HCLK_IOI_RCLK_OUT2", + "I": "HCLK_IOI_RCLK_BEFORE_DIV2", + "CLR": "HCLK_IOI_BUFR2_CLR" + }, + "x_coord": 0 + }, + { + "y_coord": 12, + "name": "X0Y12", + "prefix": "BUFR", + "type": "BUFR", + "site_pins": { + "CE": "HCLK_IOI_BUFR1_CE", + "O": "HCLK_IOI_RCLK_OUT1", + "I": "HCLK_IOI_RCLK_BEFORE_DIV1", + "CLR": "HCLK_IOI_BUFR1_CLR" + }, + "x_coord": 0 + }, + { + "y_coord": 11, + "name": "X0Y11", + "prefix": "BUFR", + "type": "BUFR", + "site_pins": { + "CE": "HCLK_IOI_BUFR0_CE", + "O": "HCLK_IOI_RCLK_OUT0", + "I": "HCLK_IOI_RCLK_BEFORE_DIV0", + "CLR": "HCLK_IOI_BUFR0_CLR" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IDELAYCTRL", + "type": "IDELAYCTRL", + "site_pins": { + "UPPULSEOUT": "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "OUTN65": "HCLK_IOI_IDELAYCTRL_OUTN65", + "REFCLK": "HCLK_IOI_IDELAYCTRL_REFCLK", + "DNPULSEOUT": "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "RDY": "HCLK_IOI_IDELAYCTRL_RDY", + "OUTN1": "HCLK_IOI_IDELAYCTRL_OUTN1", + "RST": "HCLK_IOI_IDELAYCTRL_RST" + }, + "x_coord": 0 + } + ], + "wires": [ + "HCLK_IOI_IO_PLL_CLK1", + "HCLK_IOI_IOCLK_PLL2", + "HCLK_IOI_CK_IN7", + "HCLK_IOI_CK_IN3", + "HCLK_IOI_CK_BUFHCLK7", + "HCLK_IOI_CK_BUFRCLK2", + "HCLK_IOI_RCLK_IMUX3", + "HCLK_IOI_RCLK2RCLK0", + "HCLK_IOI_IOCLK3", + "HCLK_IOI_IDELAYCTRL_OUTN1", + "HCLK_IOI_IDELAYCTRL_RDY", + "HCLK_IOI_CK_BUFHCLK3", + "HCLK_IOI_BUFR0_CE", + "HCLK_IOI_BUFR2_CE", + "HCLK_IOI_BUFIO_O0", + "HCLK_IOI_RCLK_OUT1", + "HCLK_IOI_IO_PLL_CLK3_DMUX", + "HCLK_IOI_CK_IN4", + "HCLK_IOI_CK_IGCLK7", + "HCLK_RCLK_DIV_CLR3", + "HCLK_IOI_CK_BUFHCLK9", + "HCLK_IOI_IDELAYCTRL_RST", + "HCLK_IOI_RCLK_OUT2", + "HCLK_IOI_BUFIO_O3", + "HCLK_IOI_CK_IN6", + "HCLK_RCLK_DIV_CE1", + "HCLK_IOI_CK_IGCLK11", + "HCLK_IOI_RCLK_BEFORE_DIV1", + "HCLK_IOI_CK_IGCLK6", + "HCLK_IOI_LEAF_GCLK_TOP2", + "HCLK_IOI_RCLK2IO2", + "HCLK_IOI_IOCLK_PLL1", + "HCLK_IOI_CK_IGCLK2", + "HCLK_IOI_LEAF_GCLK_BOT5", + "HCLK_IOI_RCLK_IMUX0", + "HCLK_IOI_CK_BUFHCLK2", + "HCLK_IOI_BUFIO_O1", + "HCLK_IOI_CK_BUFHCLK1", + "HCLK_IOI_RCLK3", + "HCLK_IOI_CK_IN2", + "HCLK_RCLK_DIV_CLR1", + "HCLK_IOI_CK_IGCLK8", + "HCLK_IOI_LEAF_GCLK_BOT2", + "HCLK_IOI_CK_IN11", + "HCLK_IOI_IO_PLL_CLK3", + "HCLK_IOI_CK_BUFHCLK11", + "HCLK_IOI_BUFR2_CLR", + "HCLK_IOI_CK_IGCLK9", + "HCLK_IOI_RCLK2RCLK2", + "HCLK_IOI_CK_IN12", + "HCLK_IOI_RCLK2IO1", + "HCLK_IOI_RCLK2", + "HCLK_IOI_LEAF_GCLK_BOT4", + "HCLK_IOI_I2IOCLK_BOT1", + "HCLK_IOI_RCLK2IO3", + "HCLK_IOI_I2IOCLK_TOP1", + "HCLK_IOI_RCLK_BEFORE_DIV0", + "HCLK_IOI_I2IOCLK_TOP0", + "HCLK_IOI_CK_IGCLK5", + "HCLK_IOI_CK_IGCLK0", + "HCLK_RCLK_DIV_CE0", + "HCLK_IOI_IO_PLL_CLK0_DMUX", + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "HCLK_IOI_IO_PLL_CLK2", + "HCLK_IOI_BUFR3_CLR", + "HCLK_IOI_CK_IN8", + "HCLK_IOI_CK_IN13", + "HCLK_IOI_RCLK1", + "HCLK_IOI_CK_IN5", + "HCLK_IOI_RCLK_OUT3", + "HCLK_IOI_I2IOCLK_BOT0", + "HCLK_IOI_CK_BUFRCLK0", + "HCLK_IOI_RCLK2IO0", + "HCLK_IOI_CK_BUFHCLK4", + "HCLK_IOI_LEAF_GCLK_TOP1", + "HCLK_IOI_IO_PLL_CLK2_DMUX", + "HCLK_IOI_BUFR1_CE", + "HCLK_IOI_CK_IN9", + "HCLK_IOI_RCLK_BEFORE_DIV2", + "HCLK_IOI_LEAF_GCLK_TOP4", + "HCLK_IOI_CK_BUFHCLK10", + "HCLK_IOI_LEAF_GCLK_BOT0", + "HCLK_IOI_BUFR1_CLR", + "HCLK_IOI_BUFR0_CLR", + "HCLK_IOI_IOCLK_PLL3", + "HCLK_IOI_LEAF_GCLK_BOT1", + "HCLK_IOI_BUFR3_CE", + "HCLK_IOI_CK_IGCLK10", + "HCLK_IOI_IO_PLL_CLK0", + "HCLK_IOI_IO_PLL_CLK1_DMUX", + "HCLK_IOI_LEAF_GCLK_BOT3", + "HCLK_IOI_LEAF_GCLK_TOP3", + "HCLK_IOI_RCLK_OUT0", + "HCLK_IOI_CK_BUFHCLK0", + "HCLK_RCLK_DIV_CE3", + "HCLK_RCLK_DIV_CLR0", + "HCLK_IOI_CK_IN10", + "HCLK_IOI_CK_BUFHCLK5", + "HCLK_IOI_CK_IGCLK4", + "HCLK_IOI_CK_BUFRCLK3", + "HCLK_IOI_CK_IGCLK1", + "HCLK_RCLK_DIV_CE2", + "HCLK_IOI_RCLK2RCLK3", + "HCLK_IOI_RCLK_IMUX1", + "HCLK_IOI_IOCLK2", + "HCLK_IOI_LEAF_GCLK_TOP5", + "HCLK_RCLK_DIV_CLR2", + "HCLK_IOI_RCLK0", + "HCLK_IOI_RCLK_BEFORE_DIV3", + "HCLK_IOI_IDELAYCTRL_OUTN65", + "HCLK_IOI_BUFIO_O2", + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "HCLK_IOI_RCLK2RCLK1", + "HCLK_IOI_CK_IN0", + "HCLK_IOI_IOCLK_PLL0", + "HCLK_IOI_IOCLK0", + "HCLK_IOI_CK_BUFRCLK1", + "HCLK_IOI_RCLK_IMUX2", + "HCLK_IOI_CK_IN1", + "HCLK_IOI_CK_BUFHCLK6", + "HCLK_IOI_IOCLK1", + "HCLK_IOI_CK_IGCLK3", + "HCLK_IOI_CK_BUFHCLK8", + "HCLK_IOI_LEAF_GCLK_TOP0", + "HCLK_IOI_IDELAYCTRL_REFCLK" + ], + "pips": { + "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_OUT3->>HCLK_IOI_RCLK2RCLK3": { + "src_wire": "HCLK_IOI_RCLK_OUT3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2RCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK3->>HCLK_IOI_RCLK2IO3": { + "src_wire": "HCLK_IOI_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2IO3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_I2IOCLK_BOT1->>HCLK_IOI_IO_PLL_CLK3_DMUX": { + "src_wire": "HCLK_IOI_I2IOCLK_BOT1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK11->>HCLK_IOI_CK_IGCLK11": { + "src_wire": "HCLK_IOI_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2RCLK3->>HCLK_IOI_CK_BUFRCLK3": { + "src_wire": "HCLK_IOI_RCLK2RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_BUFRCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_OUT0->>HCLK_IOI_RCLK2RCLK0": { + "src_wire": "HCLK_IOI_RCLK_OUT0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2RCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK_IMUX1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK_IMUX3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_BUFIO_O1->>HCLK_IOI_IOCLK1": { + "src_wire": "HCLK_IOI_BUFIO_O1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IOCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_IO_PLL_CLK0": { + "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV2->>HCLK_IOI_RCLK_OUT2": { + "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_pseudo": "1", + "dst_wire": "HCLK_IOI_RCLK_OUT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_BUFIO_O2->>HCLK_IOI_IOCLK2": { + "src_wire": "HCLK_IOI_BUFIO_O2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IOCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP5->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK2->>HCLK_IOI_RCLK2IO2": { + "src_wire": "HCLK_IOI_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2IO2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK_IMUX1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK_IMUX0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV1->>HCLK_IOI_RCLK_OUT1": { + "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_pseudo": "1", + "dst_wire": "HCLK_IOI_RCLK_OUT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_RCLK0": { + "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK_IMUX0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP3->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_I2IOCLK_BOT0->>HCLK_IOI_IO_PLL_CLK2_DMUX": { + "src_wire": "HCLK_IOI_I2IOCLK_BOT0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK1->>HCLK_IOI_RCLK2IO1": { + "src_wire": "HCLK_IOI_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2IO1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK_IMUX0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK8->>HCLK_IOI_CK_IGCLK8": { + "src_wire": "HCLK_IOI_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_IOCLK_PLL2->>HCLK_IOI_IO_PLL_CLK2_DMUX": { + "src_wire": "HCLK_IOI_IOCLK_PLL2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CE0->HCLK_IOI_BUFR0_CE": { + "src_wire": "HCLK_RCLK_DIV_CE0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK_IMUX1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_IOCLK_PLL1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { + "src_wire": "HCLK_IOI_IOCLK_PLL1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK_IMUX2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK_IMUX3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK6->>HCLK_IOI_CK_IGCLK6": { + "src_wire": "HCLK_IOI_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2RCLK0->>HCLK_IOI_CK_BUFRCLK0": { + "src_wire": "HCLK_IOI_RCLK2RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_BUFRCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV0->>HCLK_IOI_RCLK_OUT0": { + "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_pseudo": "1", + "dst_wire": "HCLK_IOI_RCLK_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK_IMUX2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CE3->HCLK_IOI_BUFR3_CE": { + "src_wire": "HCLK_RCLK_DIV_CE3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR3_CE", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK7->>HCLK_IOI_CK_IGCLK7": { + "src_wire": "HCLK_IOI_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_IO_PLL_CLK3": { + "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT3->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_I2IOCLK_TOP1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { + "src_wire": "HCLK_IOI_I2IOCLK_TOP1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_RCLK2": { + "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_BUFIO_O0->>HCLK_IOI_IOCLK0": { + "src_wire": "HCLK_IOI_BUFIO_O0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IOCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2RCLK2->>HCLK_IOI_CK_BUFRCLK2": { + "src_wire": "HCLK_IOI_RCLK2RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_BUFRCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK_IMUX2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_RCLK3": { + "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK5->>HCLK_IOI_CK_IGCLK5": { + "src_wire": "HCLK_IOI_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK2->>HCLK_IOI_CK_IGCLK2": { + "src_wire": "HCLK_IOI_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK9->>HCLK_IOI_CK_IGCLK9": { + "src_wire": "HCLK_IOI_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK0->>HCLK_IOI_CK_IGCLK0": { + "src_wire": "HCLK_IOI_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT4->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK_IMUX2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK_IMUX1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_BUFIO_O3->>HCLK_IOI_IOCLK3": { + "src_wire": "HCLK_IOI_BUFIO_O3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IOCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP1->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_OUT2->>HCLK_IOI_RCLK2RCLK2": { + "src_wire": "HCLK_IOI_RCLK_OUT2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2RCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP0->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CLR3->HCLK_IOI_BUFR3_CLR": { + "src_wire": "HCLK_RCLK_DIV_CLR3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR3_CLR", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK4->>HCLK_IOI_CK_IGCLK4": { + "src_wire": "HCLK_IOI_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT5->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT0->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT1->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_OUT1->>HCLK_IOI_RCLK2RCLK1": { + "src_wire": "HCLK_IOI_RCLK_OUT1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2RCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV3->>HCLK_IOI_RCLK_OUT3": { + "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_pseudo": "1", + "dst_wire": "HCLK_IOI_RCLK_OUT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CE2->HCLK_IOI_BUFR2_CE": { + "src_wire": "HCLK_RCLK_DIV_CE2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR2_CE", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT2": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_IOCLK_PLL0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { + "src_wire": "HCLK_IOI_IOCLK_PLL0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CLR2->HCLK_IOI_BUFR2_CLR": { + "src_wire": "HCLK_RCLK_DIV_CLR2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR2_CLR", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CE1->HCLK_IOI_BUFR1_CE": { + "src_wire": "HCLK_RCLK_DIV_CE1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR1_CE", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK_IMUX3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_RCLK1": { + "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "src_wire": "HCLK_IOI_RCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK3->>HCLK_IOI_CK_IGCLK3": { + "src_wire": "HCLK_IOI_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_IO_PLL_CLK1": { + "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CLR0->HCLK_IOI_BUFR0_CLR": { + "src_wire": "HCLK_RCLK_DIV_CLR0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR0_CLR", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK0->>HCLK_IOI_RCLK2IO0": { + "src_wire": "HCLK_IOI_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2IO0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP2->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP0": { + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP2": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2RCLK1->>HCLK_IOI_CK_BUFRCLK1": { + "src_wire": "HCLK_IOI_RCLK2RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_BUFRCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP4->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP5": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_I2IOCLK_TOP0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { + "src_wire": "HCLK_IOI_I2IOCLK_TOP0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT2->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "src_wire": "HCLK_IOI_RCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CLR1->HCLK_IOI_BUFR1_CLR": { + "src_wire": "HCLK_RCLK_DIV_CLR1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR1_CLR", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_IOCLK_PLL3->>HCLK_IOI_IO_PLL_CLK3_DMUX": { + "src_wire": "HCLK_IOI_IOCLK_PLL3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "src_wire": "HCLK_IOI_RCLK_IMUX0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK1->>HCLK_IOI_CK_IGCLK1": { + "src_wire": "HCLK_IOI_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT5": { + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "src_wire": "HCLK_IOI_RCLK_IMUX3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT4": { + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP1": { + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP3": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT0": { + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK10->>HCLK_IOI_CK_IGCLK10": { + "src_wire": "HCLK_IOI_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT1": { + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT3": { + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_IO_PLL_CLK2": { + "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP4": { + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_L.json b/kintex7/tile_type_HCLK_L.json new file mode 100644 index 0000000..3416a41 --- /dev/null +++ b/kintex7/tile_type_HCLK_L.json @@ -0,0 +1,1695 @@ +{ + "tile_type": "HCLK_L", + "sites": [], + "wires": [ + "HCLK_NE6B0", + "HCLK_CK_IN1", + "HCLK_CK_OUTIN_L1", + "HCLK_SE6C3", + "HCLK_SW6D3", + "HCLK_LV5", + "HCLK_SE6D0", + "HCLK_CK_IN3", + "HCLK_CK_INOUT_L0", + "HCLK_SS6D2", + "HCLK_LV13", + "HCLK_CK_OUTIN_L2", + "HCLK_NW2A0", + "HCLK_WW4END_S0_0", + "HCLK_REFCK_WESTCLK1", + "HCLK_NN2A1", + "HCLK_NN2BEG3", + "HCLK_SL1END2", + "HCLK_SS2A3", + "HCLK_INT_PERFCLK0", + "HCLK_NE6A3", + "HCLK_CK_IN0", + "HCLK_LEAF_CLK_B_BOTL5", + "HCLK_NN6C0", + "HCLK_LEAF_CLK_B_BOTL2", + "HCLK_SS2A0", + "HCLK_WL1END3", + "HCLK_NW6A2", + "HCLK_NW6C1", + "HCLK_CK_IN9", + "HCLK_NE6D1", + "HCLK_LV16", + "HCLK_SS2END1", + "HCLK_LVB4", + "HCLK_FAN_BOUNCE_S3_0", + "HCLK_SE6E1", + "HCLK_SS6END_N0_3", + "HCLK_SS6B2", + "HCLK_SE6E3", + "HCLK_LVB11", + "HCLK_NN6B3", + "HCLK_SE6D1", + "HCLK_LVB12", + "HCLK_LEAF_CLK_B_BOTL4", + "HCLK_SS6B0", + "HCLK_EL1BEG3", + "HCLK_SW6C1", + "HCLK_NN6BEG3", + "HCLK_SE2A0", + "HCLK_ER1END3", + "HCLK_CK_INOUT_L7", + "HCLK_NN2A0", + "HCLK_LV6", + "HCLK_SS2END_N0_3", + "HCLK_CK_BUFHCLK0", + "HCLK_NW6B2", + "HCLK_NN6END_S1_0", + "HCLK_LVB9", + "HCLK_SS6A3", + "HCLK_CK_IN13", + "HCLK_NN6B2", + "HCLK_NE6B2", + "HCLK_LV8", + "HCLK_NE2END_S3_0", + "HCLK_CK_INOUT_L4", + "HCLK_CK_BUFHCLK1", + "HCLK_NE6D2", + "HCLK_SS6E2", + "HCLK_NN6BEG1", + "HCLK_SE6C1", + "HCLK_CK_INOUT_L3", + "HCLK_NN2A3", + "HCLK_NE6C0", + "HCLK_NW6C0", + "HCLK_NN2BEG2", + "HCLK_SR1END_N3_3", + "HCLK_NN6B0", + "HCLK_NL1BEG0", + "HCLK_CK_IN5", + "HCLK_NN2BEG0", + "HCLK_LV7", + "HCLK_NN6C3", + "HCLK_SE6C0", + "HCLK_NE6D3", + "HCLK_SW6E3", + "HCLK_NN2BEG1", + "HCLK_SR1END1", + "HCLK_NE6B3", + "HCLK_CCIO2", + "HCLK_CK_IN8", + "HCLK_NL1BEG1", + "HCLK_NN6A1", + "HCLK_NN6C2", + "HCLK_LVB8", + "HCLK_BYP_BOUNCE3", + "HCLK_NE6C3", + "HCLK_NE2BEG0", + "HCLK_SS2A1", + "HCLK_LV14", + "HCLK_LEAF_CLK_B_TOPL2", + "HCLK_FAN_BOUNCE_S3_2", + "HCLK_CK_BUFHCLK4", + "HCLK_SW6C2", + "HCLK_LV17", + "HCLK_NW6A0", + "HCLK_LVB1", + "HCLK_NE6C1", + "HCLK_SW2A3", + "HCLK_LEAF_CLK_B_TOPL0", + "HCLK_LVB2", + "HCLK_CK_BUFHCLK11", + "HCLK_SE6B3", + "HCLK_SE6E2", + "HCLK_SS6B3", + "HCLK_SW6B2", + "HCLK_SE2A2", + "HCLK_LEAF_CLK_B_TOPL5", + "HCLK_SW2END0", + "HCLK_NN6E1", + "HCLK_NE6B1", + "HCLK_SW6C0", + "HCLK_LEAF_CLK_B_TOPL4", + "HCLK_NW6D1", + "HCLK_NW6D2", + "HCLK_NW6B3", + "HCLK_SW6B0", + "HCLK_CK_OUTIN_L3", + "HCLK_NN6BEG2", + "HCLK_CK_BUFRCLK0", + "HCLK_NE6A0", + "HCLK_SL1END1", + "HCLK_NE6A1", + "HCLK_SW6END3", + "HCLK_SS6C2", + "HCLK_LV11", + "HCLK_CK_OUTIN_L7", + "HCLK_NN6D2", + "HCLK_NN6E2", + "HCLK_SS6D1", + "HCLK_CK_BUFRCLK3", + "HCLK_INT_PERFCLK1", + "HCLK_CK_IN11", + "HCLK_LVB3", + "HCLK_CK_BUFHCLK5", + "HCLK_ER1BEG_S0", + "HCLK_CK_INOUT_L5", + "HCLK_CK_BUFRCLK1", + "HCLK_NW2A3", + "HCLK_CCIO0", + "HCLK_CK_INOUT_L2", + "HCLK_LVB10", + "HCLK_NW6D0", + "HCLK_SE6D2", + "HCLK_NW2A2", + "HCLK_CK_BUFRCLK2", + "HCLK_LVB6", + "HCLK_SE6E0", + "HCLK_SS6END1", + "HCLK_NW2END_S0_0", + "HCLK_SW6E0", + "HCLK_NE6D0", + "HCLK_CK_IN4", + "HCLK_SS6B1", + "HCLK_CK_BUFHCLK10", + "HCLK_SS6A0", + "HCLK_SS6C0", + "HCLK_SL1END0", + "HCLK_SS6C3", + "HCLK_REFCK_EASTCLK0", + "HCLK_SE6C2", + "HCLK_CK_IN10", + "HCLK_LV2", + "HCLK_SE2A3", + "HCLK_NN6D0", + "HCLK_SE2A1", + "HCLK_CCIO3", + "HCLK_SW6E1", + "HCLK_NL1END_S3_0", + "HCLK_INT_PERFCLK3", + "HCLK_NN6BEG0", + "HCLK_LV3", + "HCLK_NN6D3", + "HCLK_SE6B0", + "HCLK_NN6C1", + "HCLK_LV10", + "HCLK_NN6A2", + "HCLK_NN6A0", + "HCLK_SW2END_N0_3", + "HCLK_LEAF_CLK_B_TOPL1", + "HCLK_NN6A3", + "HCLK_SW6D2", + "HCLK_SE6B2", + "HCLK_SW6B1", + "HCLK_NL1BEG2", + "HCLK_SW2END1", + "HCLK_SW2END2", + "HCLK_WL1BEG3", + "HCLK_SE6B1", + "HCLK_CK_BUFHCLK7", + "HCLK_NW6C3", + "HCLK_CCIO1", + "HCLK_CK_INOUT_L1", + "HCLK_CK_IN2", + "HCLK_NR1BEG1", + "HCLK_NE2BEG3", + "HCLK_NE6C2", + "HCLK_SS6D3", + "HCLK_WW2END3", + "HCLK_SS6E1", + "HCLK_LV0", + "HCLK_NN6E0", + "HCLK_EL1END_S3_0", + "HCLK_SR1END2", + "HCLK_NE2BEG2", + "HCLK_LVB7", + "HCLK_NW6D3", + "HCLK_CK_IN6", + "HCLK_SW6B3", + "HCLK_SE6D3", + "HCLK_NN2END_S2_0", + "HCLK_SS6A1", + "HCLK_LVB5", + "HCLK_NE2BEG1", + "HCLK_CK_INOUT_L6", + "HCLK_NW6A3", + "HCLK_LV4", + "HCLK_INT_PERFCLK2", + "HCLK_CK_BUFHCLK9", + "HCLK_SS6END0", + "HCLK_LV12", + "HCLK_LV1", + "HCLK_NW6C2", + "HCLK_LV15", + "HCLK_REFCK_EASTCLK1", + "HCLK_CK_OUTIN_L0", + "HCLK_NW2A1", + "HCLK_NR1BEG3", + "HCLK_SW6D1", + "HCLK_FAN_BOUNCE_S3_6", + "HCLK_SS2END2", + "HCLK_CK_BUFHCLK8", + "HCLK_CK_OUTIN_L5", + "HCLK_NW6B0", + "HCLK_SR1BEG3", + "HCLK_BYP_BOUNCE7", + "HCLK_SW6D0", + "HCLK_SW6E2", + "HCLK_NW6B1", + "HCLK_SS2BEG3", + "HCLK_LEAF_CLK_B_BOTL0", + "HCLK_SS2END0", + "HCLK_CK_BUFHCLK3", + "HCLK_SS6A2", + "HCLK_SS6END2", + "HCLK_SS6C1", + "HCLK_NN6E3", + "HCLK_SS6END3", + "HCLK_NW6END_S0_0", + "HCLK_WR1BEG_S0", + "HCLK_BYP_BOUNCE6", + "HCLK_CK_BUFHCLK6", + "HCLK_NE6A2", + "HCLK_NN2A2", + "HCLK_SL1END3", + "HCLK_CK_IN12", + "HCLK_SS6D0", + "HCLK_NW6A1", + "HCLK_SS2A2", + "HCLK_CK_IN7", + "HCLK_LEAF_CLK_B_BOTL1", + "HCLK_CK_OUTIN_L6", + "HCLK_WR1END_S1_0", + "HCLK_SW6C3", + "HCLK_NR1BEG0", + "HCLK_BYP_BOUNCE2", + "HCLK_REFCK_WESTCLK0", + "HCLK_LEAF_CLK_B_TOPL3", + "HCLK_LV9", + "HCLK_CK_OUTIN_L4", + "HCLK_NR1BEG2", + "HCLK_CK_BUFHCLK2", + "HCLK_FAN_BOUNCE_S3_4", + "HCLK_SS6E3", + "HCLK_NN6D1", + "HCLK_LEAF_CLK_B_BOTL3", + "HCLK_SS6E0", + "HCLK_NN6B1" + ], + "pips": { + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_CK_INOUT_L3": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_CK_INOUT_L5": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_CK_INOUT_L0": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_CK_INOUT_L4": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_CK_INOUT_L2": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_CK_INOUT_L6": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_CK_INOUT_L7": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_CK_INOUT_L1": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_L_BOT_UTURN.json b/kintex7/tile_type_HCLK_L_BOT_UTURN.json new file mode 100644 index 0000000..13b8562 --- /dev/null +++ b/kintex7/tile_type_HCLK_L_BOT_UTURN.json @@ -0,0 +1,908 @@ +{ + "tile_type": "HCLK_L_BOT_UTURN", + "sites": [], + "wires": [ + "B_TERM_UTURN_INT_SW6D0", + "B_TERM_UTURN_INT_SS6A1", + "B_TERM_UTURN_INT_SS2BEG2", + "HCLK_CK_IN1", + "HCLK_CK_OUTIN_L1", + "HCLK_CK_BUFRCLK3", + "HCLK_INT_PERFCLK1", + "B_TERM_UTURN_INT_LV8", + "HCLK_CK_IN11", + "HCLK_CK_IN3", + "B_TERM_UTURN_INT_SW2BEG2", + "HCLK_CK_INOUT_L0", + "HCLK_CK_BUFHCLK5", + "B_TERM_UTURN_INT_SS6E0", + "HCLK_CK_INOUT_L5", + "B_TERM_UTURN_INT_SE6A0", + "B_TERM_UTURN_INT_SS6B3", + "HCLK_CK_OUTIN_L2", + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "HCLK_CK_BUFRCLK1", + "B_TERM_UTURN_INT_LV9", + "B_TERM_UTURN_INT_SS6A2", + "B_TERM_UTURN_INT_SS6B0", + "HCLK_CCIO0", + "HCLK_CK_INOUT_L2", + "B_TERM_UTURN_INT_SR1BEG3", + "HCLK_INT_PERFCLK0", + "B_TERM_UTURN_INT_LVB_L4", + "B_TERM_UTURN_INT_LV_L2", + "B_TERM_UTURN_INT_SS6BEG3", + "B_TERM_UTURN_INT_SW6A2", + "B_TERM_UTURN_INT_SE6C0", + "HCLK_CK_IN0", + "B_TERM_UTURN_INT_LVB_L5", + "HCLK_CK_BUFRCLK2", + "B_TERM_UTURN_INT_ER1BEG0", + "B_TERM_UTURN_INT_LVB_L3", + "HCLK_CK_IN4", + "HCLK_CK_IN9", + "B_TERM_UTURN_INT_SE6C3", + "B_TERM_UTURN_INT_SS6C3", + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "HCLK_CK_BUFHCLK10", + "B_TERM_UTURN_INT_LV_L9", + "B_TERM_UTURN_INT_LV2", + "B_TERM_UTURN_INT_SS6D0", + "B_TERM_UTURN_INT_LVB_L1", + "B_TERM_UTURN_INT_SS6E2", + "B_TERM_UTURN_INT_SE6D3", + "B_TERM_UTURN_INT_SW6D3", + "B_TERM_UTURN_INT_SS2BEG0", + "HCLK_CK_IN10", + "B_TERM_UTURN_INT_SS6D2", + "B_TERM_UTURN_INT_SR1BEG1", + "B_TERM_UTURN_INT_SS6E3", + "B_TERM_UTURN_INT_SW2BEG0", + "B_TERM_UTURN_INT_SS6D1", + "HCLK_CCIO3", + "B_TERM_UTURN_INT_SS6BEG1", + "B_TERM_UTURN_INT_SE6D2", + "B_TERM_UTURN_INT_SR1BEG2", + "B_TERM_UTURN_INT_SE6B1", + "B_TERM_UTURN_INT_SL1BEG1", + "HCLK_INT_PERFCLK3", + "HCLK_CK_INOUT_L7", + "B_TERM_UTURN_INT_LV_L7", + "B_TERM_UTURN_INT_LVB_L2", + "B_TERM_UTURN_INT_SW6A0", + "B_TERM_UTURN_INT_SW6A1", + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "B_TERM_UTURN_INT_LV_L8", + "B_TERM_UTURN_INT_SW6C3", + "HCLK_CK_BUFHCLK0", + "B_TERM_UTURN_INT_SW6B2", + "B_TERM_UTURN_INT_SS6B2", + "B_TERM_UTURN_INT_SS6BEG0", + "B_TERM_UTURN_INT_SS6BEG2", + "HCLK_CK_IN13", + "HCLK_LEAF_CLK_B_TOPL1", + "B_TERM_UTURN_INT_SE6B3", + "B_TERM_UTURN_INT_SS2BEG3", + "B_TERM_UTURN_INT_SS2A0", + "HCLK_CK_INOUT_L4", + "HCLK_CK_BUFHCLK1", + "B_TERM_UTURN_INT_LV3", + "HCLK_CK_BUFHCLK7", + "B_TERM_UTURN_INT_SW6C1", + "HCLK_CK_INOUT_L3", + "B_TERM_UTURN_INT_LV7", + "B_TERM_UTURN_INT_SS6C0", + "HCLK_CCIO1", + "HCLK_CK_IN2", + "HCLK_CK_INOUT_L1", + "B_TERM_UTURN_INT_LV_L5", + "B_TERM_UTURN_INT_SE6B0", + "B_TERM_UTURN_INT_SE2BEG1", + "B_TERM_UTURN_INT_SE6A3", + "B_TERM_UTURN_INT_SW6B1", + "B_TERM_UTURN_INT_SW6A3", + "B_TERM_UTURN_INT_SE2BEG0", + "HCLK_CK_IN5", + "B_TERM_UTURN_INT_SS6B1", + "HCLK_CK_IN6", + "B_TERM_UTURN_INT_SE6C2", + "B_TERM_UTURN_INT_SW6D2", + "B_TERM_UTURN_INT_SW2BEG1", + "B_TERM_UTURN_INT_SE6B2", + "HCLK_CK_INOUT_L6", + "B_TERM_UTURN_INT_SW6D1", + "B_TERM_UTURN_INT_SW6C0", + "B_TERM_UTURN_INT_SE6A2", + "B_TERM_UTURN_INT_ER1END_N3_3", + "HCLK_CK_IN8", + "B_TERM_UTURN_INT_SW2BEG3", + "HCLK_CK_BUFHCLK9", + "HCLK_INT_PERFCLK2", + "HCLK_CCIO2", + "B_TERM_UTURN_INT_LV_L4", + "B_TERM_UTURN_INT_SS6A3", + "B_TERM_UTURN_INT_SL1BEG0", + "HCLK_CK_OUTIN_L0", + "B_TERM_UTURN_INT_SE6A1", + "B_TERM_UTURN_INT_LV4", + "B_TERM_UTURN_INT_SS2A2", + "HCLK_CK_BUFHCLK8", + "B_TERM_UTURN_INT_SE6C1", + "HCLK_CK_OUTIN_L5", + "B_TERM_UTURN_INT_SS2BEG1", + "HCLK_LEAF_CLK_B_TOPL2", + "HCLK_CK_BUFHCLK4", + "B_TERM_UTURN_INT_LVB_L0", + "B_TERM_UTURN_INT_SS6A0", + "B_TERM_UTURN_INT_SE6D1", + "B_TERM_UTURN_INT_SE2BEG3", + "B_TERM_UTURN_INT_SL1BEG3", + "HCLK_LEAF_CLK_B_TOPL0", + "B_TERM_UTURN_INT_LV_L3", + "HCLK_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK3", + "B_TERM_UTURN_INT_SW6B0", + "B_TERM_UTURN_INT_LV5", + "B_TERM_UTURN_INT_WR1END0", + "HCLK_CK_BUFHCLK6", + "B_TERM_UTURN_INT_LV_L6", + "B_TERM_UTURN_INT_LV_L18", + "B_TERM_UTURN_INT_SE2BEG2", + "B_TERM_UTURN_INT_SS2A3", + "HCLK_CK_IN12", + "HCLK_LEAF_CLK_B_TOPL5", + "B_TERM_UTURN_INT_SW6B3", + "B_TERM_UTURN_INT_SS6C1", + "B_TERM_UTURN_INT_WR1BEG0", + "HCLK_LEAF_CLK_B_TOPL4", + "HCLK_CK_IN7", + "B_TERM_UTURN_INT_SE6D0", + "HCLK_CK_OUTIN_L6", + "B_TERM_UTURN_INT_SL1BEG2", + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "B_TERM_UTURN_INT_SW6END_N0_3", + "B_TERM_UTURN_INT_SS6E1", + "HCLK_LEAF_CLK_B_TOPL3", + "HCLK_CK_OUTIN_L4", + "HCLK_CK_OUTIN_L3", + "HCLK_CK_BUFHCLK2", + "B_TERM_UTURN_INT_SS6C2", + "HCLK_CK_BUFRCLK0", + "B_TERM_UTURN_INT_SS6D3", + "B_TERM_UTURN_INT_LV6", + "B_TERM_UTURN_INT_SS2A1", + "B_TERM_UTURN_INT_SW6C2", + "HCLK_CK_OUTIN_L7", + "B_TERM_UTURN_INT_LV18" + ], + "pips": { + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_CK_INOUT_L1": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_CK_INOUT_L0": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_CK_INOUT_L7": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_CK_INOUT_L3": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_CK_INOUT_L6": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_CK_INOUT_L5": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFHCLK8", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFRCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFHCLK11", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_CK_INOUT_L4": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFHCLK9", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFRCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFRCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFRCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_CK_INOUT_L2": { + "src_wire": "HCLK_CK_BUFHCLK10", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_R.json b/kintex7/tile_type_HCLK_R.json new file mode 100644 index 0000000..f2057cb --- /dev/null +++ b/kintex7/tile_type_HCLK_R.json @@ -0,0 +1,1695 @@ +{ + "tile_type": "HCLK_R", + "sites": [], + "wires": [ + "HCLK_NE6B0", + "HCLK_CK_IN1", + "HCLK_SE6C3", + "HCLK_SW6D3", + "HCLK_LV5", + "HCLK_SE6D0", + "HCLK_CK_IN3", + "HCLK_SS6D2", + "HCLK_LV13", + "HCLK_NW2A0", + "HCLK_WW4END_S0_0", + "HCLK_REFCK_WESTCLK1", + "HCLK_NN2A1", + "HCLK_NN2BEG3", + "HCLK_SL1END2", + "HCLK_SS2A3", + "HCLK_INT_PERFCLK0", + "HCLK_NE6A3", + "HCLK_CK_INOUT_R0", + "HCLK_CK_IN0", + "HCLK_NN6C0", + "HCLK_SS2A0", + "HCLK_WL1END3", + "HCLK_NW6A2", + "HCLK_NW6C1", + "HCLK_CK_IN9", + "HCLK_NE6D1", + "HCLK_LV16", + "HCLK_SS2END1", + "HCLK_LVB4", + "HCLK_FAN_BOUNCE_S3_0", + "HCLK_SE6E1", + "HCLK_SS6END_N0_3", + "HCLK_SS6B2", + "HCLK_SE6E3", + "HCLK_LVB11", + "HCLK_NN6B3", + "HCLK_SE6D1", + "HCLK_LVB12", + "HCLK_SS6B0", + "HCLK_EL1BEG3", + "HCLK_LEAF_CLK_B_BOT1", + "HCLK_SW6C1", + "HCLK_NN6BEG3", + "HCLK_SE2A0", + "HCLK_ER1END3", + "HCLK_NN2A0", + "HCLK_CK_INOUT_R2", + "HCLK_LV6", + "HCLK_LEAF_CLK_B_TOP3", + "HCLK_CK_BUFHCLK0", + "HCLK_NW6B2", + "HCLK_SS2END_N0_3", + "HCLK_NN6END_S1_0", + "HCLK_LVB9", + "HCLK_SS6A3", + "HCLK_CK_IN13", + "HCLK_NN6B2", + "HCLK_NE6B2", + "HCLK_LV8", + "HCLK_NE2END_S3_0", + "HCLK_LEAF_CLK_B_BOT3", + "HCLK_CK_BUFHCLK1", + "HCLK_CK_INOUT_R6", + "HCLK_NE6D2", + "HCLK_SS6E2", + "HCLK_NN6BEG1", + "HCLK_SE6C1", + "HCLK_NN2A3", + "HCLK_NE6C0", + "HCLK_NW6C0", + "HCLK_LEAF_CLK_B_BOT2", + "HCLK_NN2BEG2", + "HCLK_SR1END_N3_3", + "HCLK_NN6B0", + "HCLK_LEAF_CLK_B_BOT0", + "HCLK_NL1BEG0", + "HCLK_CK_IN5", + "HCLK_NN2BEG0", + "HCLK_LV7", + "HCLK_NN6C3", + "HCLK_SE6C0", + "HCLK_NE6D3", + "HCLK_CK_OUTIN_R7", + "HCLK_SW6E3", + "HCLK_NN2BEG1", + "HCLK_SR1END1", + "HCLK_NE6B3", + "HCLK_CCIO2", + "HCLK_CK_IN8", + "HCLK_NL1BEG1", + "HCLK_NN6A1", + "HCLK_NN6C2", + "HCLK_LVB8", + "HCLK_BYP_BOUNCE3", + "HCLK_NE6C3", + "HCLK_CK_OUTIN_R2", + "HCLK_NE2BEG0", + "HCLK_SS2A1", + "HCLK_LV14", + "HCLK_FAN_BOUNCE_S3_2", + "HCLK_CK_BUFHCLK4", + "HCLK_SW6C2", + "HCLK_LEAF_CLK_B_TOP0", + "HCLK_LV17", + "HCLK_NW6A0", + "HCLK_LVB1", + "HCLK_NE6C1", + "HCLK_SW2A3", + "HCLK_CK_INOUT_R1", + "HCLK_LVB2", + "HCLK_CK_BUFHCLK11", + "HCLK_SE6B3", + "HCLK_SE6E2", + "HCLK_SS6B3", + "HCLK_SW6B2", + "HCLK_LEAF_CLK_B_BOT4", + "HCLK_SE2A2", + "HCLK_SW2END0", + "HCLK_CK_INOUT_R5", + "HCLK_NN6E1", + "HCLK_NE6B1", + "HCLK_SW6C0", + "HCLK_CK_INOUT_R7", + "HCLK_NW6D1", + "HCLK_NW6D2", + "HCLK_NW6B3", + "HCLK_SW6B0", + "HCLK_NN6BEG2", + "HCLK_CK_BUFRCLK0", + "HCLK_NE6A0", + "HCLK_SL1END1", + "HCLK_NE6A1", + "HCLK_SW6END3", + "HCLK_SS6C2", + "HCLK_LV11", + "HCLK_CK_OUTIN_R5", + "HCLK_NN6D2", + "HCLK_SS6D1", + "HCLK_NN6E2", + "HCLK_CK_BUFRCLK3", + "HCLK_INT_PERFCLK1", + "HCLK_CK_IN11", + "HCLK_LVB3", + "HCLK_CK_BUFHCLK5", + "HCLK_ER1BEG_S0", + "HCLK_NW2A3", + "HCLK_CK_BUFRCLK1", + "HCLK_LEAF_CLK_B_TOP4", + "HCLK_CCIO0", + "HCLK_LVB10", + "HCLK_NW6D0", + "HCLK_SE6D2", + "HCLK_NW2A2", + "HCLK_CK_BUFRCLK2", + "HCLK_LVB6", + "HCLK_SE6E0", + "HCLK_SS6END1", + "HCLK_NW2END_S0_0", + "HCLK_SW6E0", + "HCLK_NE6D0", + "HCLK_CK_IN4", + "HCLK_SS6B1", + "HCLK_CK_BUFHCLK10", + "HCLK_SS6A0", + "HCLK_SS6C0", + "HCLK_SL1END0", + "HCLK_SS6C3", + "HCLK_REFCK_EASTCLK0", + "HCLK_SE6C2", + "HCLK_LEAF_CLK_B_TOP5", + "HCLK_CK_IN10", + "HCLK_LV2", + "HCLK_SE2A3", + "HCLK_NN6D0", + "HCLK_CK_OUTIN_R1", + "HCLK_SE2A1", + "HCLK_CCIO3", + "HCLK_SW6E1", + "HCLK_NL1END_S3_0", + "HCLK_INT_PERFCLK3", + "HCLK_NN6BEG0", + "HCLK_LV3", + "HCLK_NN6D3", + "HCLK_SE6B0", + "HCLK_NN6C1", + "HCLK_LV10", + "HCLK_NN6A2", + "HCLK_LEAF_CLK_B_TOP2", + "HCLK_NN6A0", + "HCLK_SW2END_N0_3", + "HCLK_NN6A3", + "HCLK_SW6D2", + "HCLK_SE6B2", + "HCLK_SW6B1", + "HCLK_NL1BEG2", + "HCLK_SW2END1", + "HCLK_SW2END2", + "HCLK_CK_BUFHCLK7", + "HCLK_SE6B1", + "HCLK_WL1BEG3", + "HCLK_CK_OUTIN_R3", + "HCLK_NW6C3", + "HCLK_CCIO1", + "HCLK_CK_IN2", + "HCLK_NE2BEG3", + "HCLK_NR1BEG1", + "HCLK_NE6C2", + "HCLK_SS6D3", + "HCLK_WW2END3", + "HCLK_SS6E1", + "HCLK_LV0", + "HCLK_NN6E0", + "HCLK_EL1END_S3_0", + "HCLK_SR1END2", + "HCLK_NE2BEG2", + "HCLK_LVB7", + "HCLK_NW6D3", + "HCLK_CK_INOUT_R4", + "HCLK_CK_IN6", + "HCLK_SW6B3", + "HCLK_SE6D3", + "HCLK_NN2END_S2_0", + "HCLK_SS6A1", + "HCLK_LVB5", + "HCLK_NE2BEG1", + "HCLK_NW6A3", + "HCLK_LV4", + "HCLK_INT_PERFCLK2", + "HCLK_CK_BUFHCLK9", + "HCLK_SS6END0", + "HCLK_LV12", + "HCLK_LV1", + "HCLK_NW6C2", + "HCLK_LV15", + "HCLK_REFCK_EASTCLK1", + "HCLK_NW2A1", + "HCLK_NR1BEG3", + "HCLK_SW6D1", + "HCLK_FAN_BOUNCE_S3_6", + "HCLK_SS2END2", + "HCLK_LEAF_CLK_B_TOP1", + "HCLK_LEAF_CLK_B_BOT5", + "HCLK_CK_BUFHCLK8", + "HCLK_NW6B0", + "HCLK_SR1BEG3", + "HCLK_BYP_BOUNCE7", + "HCLK_SW6D0", + "HCLK_SW6E2", + "HCLK_NW6B1", + "HCLK_SS2BEG3", + "HCLK_SS2END0", + "HCLK_CK_BUFHCLK3", + "HCLK_SS6A2", + "HCLK_SS6END2", + "HCLK_CK_OUTIN_R4", + "HCLK_SS6C1", + "HCLK_NN6E3", + "HCLK_SS6END3", + "HCLK_NW6END_S0_0", + "HCLK_WR1BEG_S0", + "HCLK_CK_BUFHCLK6", + "HCLK_BYP_BOUNCE6", + "HCLK_NE6A2", + "HCLK_NN2A2", + "HCLK_SL1END3", + "HCLK_CK_OUTIN_R6", + "HCLK_CK_IN12", + "HCLK_SS6D0", + "HCLK_NW6A1", + "HCLK_CK_INOUT_R3", + "HCLK_SS2A2", + "HCLK_CK_IN7", + "HCLK_WR1END_S1_0", + "HCLK_SW6C3", + "HCLK_NR1BEG0", + "HCLK_BYP_BOUNCE2", + "HCLK_REFCK_WESTCLK0", + "HCLK_LV9", + "HCLK_CK_OUTIN_R0", + "HCLK_CK_BUFHCLK2", + "HCLK_NR1BEG2", + "HCLK_FAN_BOUNCE_S3_4", + "HCLK_SS6E3", + "HCLK_NN6D1", + "HCLK_SS6E0", + "HCLK_NN6B1" + ], + "pips": { + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_CK_INOUT_R5": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_CK_INOUT_R6": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_CK_INOUT_R4": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_CK_INOUT_R2": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_CK_INOUT_R0": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_CK_INOUT_R3": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_CK_INOUT_R1": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_CK_INOUT_R7": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_R_BOT_UTURN.json b/kintex7/tile_type_HCLK_R_BOT_UTURN.json new file mode 100644 index 0000000..367360d --- /dev/null +++ b/kintex7/tile_type_HCLK_R_BOT_UTURN.json @@ -0,0 +1,908 @@ +{ + "tile_type": "HCLK_R_BOT_UTURN", + "sites": [], + "wires": [ + "HCLK_CK_OUTIN_R5", + "B_TERM_UTURN_INT_SW6D0", + "B_TERM_UTURN_INT_SS6A1", + "B_TERM_UTURN_INT_LVB5", + "B_TERM_UTURN_INT_SS2BEG2", + "HCLK_CK_IN1", + "HCLK_CK_BUFRCLK3", + "HCLK_INT_PERFCLK1", + "B_TERM_UTURN_INT_LV8", + "HCLK_CK_IN11", + "HCLK_CK_IN3", + "B_TERM_UTURN_INT_SW2BEG2", + "HCLK_CK_BUFHCLK5", + "B_TERM_UTURN_INT_SS6E0", + "B_TERM_UTURN_INT_SE6A0", + "B_TERM_UTURN_INT_SS6B3", + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "HCLK_CK_BUFRCLK1", + "HCLK_LEAF_CLK_B_TOP4", + "B_TERM_UTURN_INT_LV9", + "B_TERM_UTURN_INT_SS6A2", + "B_TERM_UTURN_INT_SS6B0", + "HCLK_CCIO0", + "B_TERM_UTURN_INT_SR1BEG3", + "HCLK_INT_PERFCLK0", + "B_TERM_UTURN_INT_LV_L2", + "B_TERM_UTURN_INT_SS6BEG3", + "HCLK_CK_INOUT_R0", + "B_TERM_UTURN_INT_SW6A2", + "B_TERM_UTURN_INT_SE6C0", + "HCLK_CK_IN0", + "HCLK_CK_BUFRCLK2", + "B_TERM_UTURN_INT_ER1BEG0", + "B_TERM_UTURN_INT_LVB1", + "HCLK_CK_IN4", + "HCLK_CK_IN9", + "B_TERM_UTURN_INT_SE6C3", + "B_TERM_UTURN_INT_SS6C3", + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "HCLK_CK_BUFHCLK10", + "B_TERM_UTURN_INT_LV_L9", + "B_TERM_UTURN_INT_LV2", + "B_TERM_UTURN_INT_SS6D0", + "B_TERM_UTURN_INT_SS6E2", + "B_TERM_UTURN_INT_SE6D3", + "B_TERM_UTURN_INT_SW6D3", + "B_TERM_UTURN_INT_LVB0", + "B_TERM_UTURN_INT_SS2BEG0", + "HCLK_LEAF_CLK_B_TOP5", + "HCLK_CK_IN10", + "B_TERM_UTURN_INT_SS6D2", + "B_TERM_UTURN_INT_SR1BEG1", + "B_TERM_UTURN_INT_SS6E3", + "B_TERM_UTURN_INT_SW2BEG0", + "B_TERM_UTURN_INT_SS6D1", + "HCLK_CK_OUTIN_R1", + "HCLK_CCIO3", + "B_TERM_UTURN_INT_LVB2", + "B_TERM_UTURN_INT_SS6BEG1", + "B_TERM_UTURN_INT_SE6D2", + "B_TERM_UTURN_INT_SR1BEG2", + "B_TERM_UTURN_INT_SE6B1", + "B_TERM_UTURN_INT_SL1BEG1", + "HCLK_INT_PERFCLK3", + "B_TERM_UTURN_INT_LV_L7", + "B_TERM_UTURN_INT_SW6A0", + "HCLK_CK_INOUT_R2", + "B_TERM_UTURN_INT_SW6A1", + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "B_TERM_UTURN_INT_LV_L8", + "HCLK_LEAF_CLK_B_TOP3", + "HCLK_CK_BUFHCLK0", + "B_TERM_UTURN_INT_SW6C3", + "HCLK_LEAF_CLK_B_TOP2", + "B_TERM_UTURN_INT_SW6B2", + "B_TERM_UTURN_INT_SS6B2", + "B_TERM_UTURN_INT_SS6BEG0", + "B_TERM_UTURN_INT_SS6BEG2", + "HCLK_CK_IN13", + "B_TERM_UTURN_INT_LVB3", + "B_TERM_UTURN_INT_SE6B3", + "B_TERM_UTURN_INT_SS2BEG3", + "B_TERM_UTURN_INT_SS2A0", + "HCLK_CK_BUFHCLK1", + "B_TERM_UTURN_INT_LV3", + "HCLK_CK_INOUT_R6", + "HCLK_CK_BUFHCLK7", + "HCLK_CK_OUTIN_R3", + "B_TERM_UTURN_INT_SW6C1", + "B_TERM_UTURN_INT_LV7", + "B_TERM_UTURN_INT_SS6C0", + "HCLK_CCIO1", + "HCLK_CK_IN2", + "B_TERM_UTURN_INT_LV_L5", + "B_TERM_UTURN_INT_SE6B0", + "B_TERM_UTURN_INT_SE2BEG1", + "B_TERM_UTURN_INT_SE6A3", + "B_TERM_UTURN_INT_SW6B1", + "B_TERM_UTURN_INT_SW6A3", + "B_TERM_UTURN_INT_SE2BEG0", + "HCLK_CK_IN5", + "HCLK_CK_INOUT_R4", + "B_TERM_UTURN_INT_SS6B1", + "HCLK_CK_IN6", + "B_TERM_UTURN_INT_SE6C2", + "HCLK_CK_OUTIN_R7", + "B_TERM_UTURN_INT_SW6D2", + "B_TERM_UTURN_INT_SW2BEG1", + "B_TERM_UTURN_INT_SE6B2", + "B_TERM_UTURN_INT_SW6D1", + "B_TERM_UTURN_INT_SW6C0", + "B_TERM_UTURN_INT_SE6A2", + "B_TERM_UTURN_INT_ER1END_N3_3", + "HCLK_CK_IN8", + "B_TERM_UTURN_INT_SW2BEG3", + "HCLK_INT_PERFCLK2", + "HCLK_CK_BUFHCLK9", + "HCLK_CCIO2", + "B_TERM_UTURN_INT_LV_L4", + "B_TERM_UTURN_INT_SS6A3", + "B_TERM_UTURN_INT_SL1BEG0", + "B_TERM_UTURN_INT_SE6A1", + "B_TERM_UTURN_INT_LV4", + "HCLK_LEAF_CLK_B_TOP1", + "B_TERM_UTURN_INT_SS2A2", + "HCLK_CK_OUTIN_R2", + "HCLK_CK_BUFHCLK8", + "B_TERM_UTURN_INT_SE6C1", + "B_TERM_UTURN_INT_SS2BEG1", + "HCLK_CK_BUFHCLK4", + "B_TERM_UTURN_INT_SS6A0", + "B_TERM_UTURN_INT_SE6D1", + "B_TERM_UTURN_INT_SE2BEG3", + "HCLK_LEAF_CLK_B_TOP0", + "B_TERM_UTURN_INT_SL1BEG3", + "HCLK_CK_INOUT_R1", + "B_TERM_UTURN_INT_LV_L3", + "HCLK_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK3", + "B_TERM_UTURN_INT_SW6B0", + "HCLK_CK_OUTIN_R4", + "B_TERM_UTURN_INT_LV5", + "B_TERM_UTURN_INT_LVB4", + "B_TERM_UTURN_INT_WR1END0", + "HCLK_CK_BUFHCLK6", + "B_TERM_UTURN_INT_LV_L6", + "B_TERM_UTURN_INT_LV_L18", + "HCLK_CK_OUTIN_R6", + "B_TERM_UTURN_INT_SE2BEG2", + "HCLK_CK_IN12", + "B_TERM_UTURN_INT_SS2A3", + "HCLK_CK_INOUT_R5", + "B_TERM_UTURN_INT_SW6B3", + "B_TERM_UTURN_INT_SS6C1", + "B_TERM_UTURN_INT_WR1BEG0", + "HCLK_CK_INOUT_R3", + "HCLK_CK_IN7", + "B_TERM_UTURN_INT_SE6D0", + "HCLK_CK_INOUT_R7", + "B_TERM_UTURN_INT_SL1BEG2", + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "B_TERM_UTURN_INT_SW6END_N0_3", + "B_TERM_UTURN_INT_SS6E1", + "HCLK_CK_OUTIN_R0", + "B_TERM_UTURN_INT_SS6C2", + "HCLK_CK_BUFHCLK2", + "HCLK_CK_BUFRCLK0", + "B_TERM_UTURN_INT_SS6D3", + "B_TERM_UTURN_INT_LV6", + "B_TERM_UTURN_INT_SS2A1", + "B_TERM_UTURN_INT_SW6C2", + "B_TERM_UTURN_INT_LV18" + ], + "pips": { + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_CK_INOUT_R3": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_CK_INOUT_R6": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R6", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_CK_INOUT_R0": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_CK_INOUT_R5": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_CK_INOUT_R4": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_CK_INOUT_R7": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R7", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_CK_INOUT_R2": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK5", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_CK_INOUT_R1": { + "src_wire": "HCLK_CK_BUFHCLK1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R7", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R4", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK2", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R6", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R0", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "is_directional": "1", + "can_invert": "0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK3", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_TERM.json b/kintex7/tile_type_HCLK_TERM.json new file mode 100644 index 0000000..00bb081 --- /dev/null +++ b/kintex7/tile_type_HCLK_TERM.json @@ -0,0 +1,45 @@ +{ + "tile_type": "HCLK_TERM", + "sites": [], + "wires": [ + "HCLK_TERM_CK_IN13", + "HCLK_TERM_CK_IN6", + "HCLK_TERM_CK_IN8", + "HCLK_TERM_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFRCLK3", + "HCLK_TERM_CK_IN10", + "HCLK_TERM_CK_IN11", + "HCLK_TERM_PERFCLK0", + "HCLK_TERM_CK_IN0", + "HCLK_TERM_CK_BUFHCLK7", + "HCLK_TERM_PERFCLK3", + "HCLK_TERM_CK_BUFHCLK6", + "HCLK_TERM_CK_IN4", + "HCLK_TERM_CK_IN7", + "HCLK_TERM_CCIO0", + "HCLK_TERM_CCIO1", + "HCLK_TERM_CK_BUFRCLK2", + "HCLK_TERM_CK_IN9", + "HCLK_TERM_PERFCLK1", + "HCLK_TERM_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFRCLK0", + "HCLK_TERM_CK_IN3", + "HCLK_TERM_CK_IN1", + "HCLK_TERM_CCIO2", + "HCLK_TERM_CK_BUFHCLK3", + "HCLK_TERM_CCIO3", + "HCLK_TERM_CK_IN2", + "HCLK_TERM_CK_BUFHCLK9", + "HCLK_TERM_PERFCLK2", + "HCLK_TERM_CK_IN5", + "HCLK_TERM_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK5", + "HCLK_TERM_CK_IN12" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_TERM_GTX.json b/kintex7/tile_type_HCLK_TERM_GTX.json new file mode 100644 index 0000000..6233cec --- /dev/null +++ b/kintex7/tile_type_HCLK_TERM_GTX.json @@ -0,0 +1,21 @@ +{ + "tile_type": "HCLK_TERM_GTX", + "sites": [], + "wires": [ + "HCLK_TERM_GTX_CK_IN12", + "HCLK_TERM_GTX_CK_IN7", + "HCLK_TERM_GTX_CK_IN6", + "HCLK_TERM_GTX_CK_IN13", + "HCLK_TERM_GTX_CK_IN0", + "HCLK_TERM_GTX_CK_IN5", + "HCLK_TERM_GTX_CK_IN9", + "HCLK_TERM_GTX_CK_IN10", + "HCLK_TERM_GTX_CK_IN11", + "HCLK_TERM_GTX_CK_IN2", + "HCLK_TERM_GTX_CK_IN1", + "HCLK_TERM_GTX_CK_IN4", + "HCLK_TERM_GTX_CK_IN8", + "HCLK_TERM_GTX_CK_IN3" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_VBRK.json b/kintex7/tile_type_HCLK_VBRK.json new file mode 100644 index 0000000..adf9ced --- /dev/null +++ b/kintex7/tile_type_HCLK_VBRK.json @@ -0,0 +1,45 @@ +{ + "tile_type": "HCLK_VBRK", + "sites": [], + "wires": [ + "HCLK_VBRK_CK_BUFHCLK8", + "HCLK_VBRK_MUX_CLK5", + "HCLK_VBRK_REFCK_EASTCLK0", + "HCLK_VBRK_MUX_CLK11", + "HCLK_VBRK_CK_BUFHCLK7", + "HCLK_VBRK_MUX_CLK9", + "HCLK_VBRK_PHSR_PERFCLK3", + "HCLK_VBRK_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFHCLK11", + "HCLK_VBRK_MUX_CLK8", + "HCLK_VBRK_MUX_CLK2", + "HCLK_VBRK_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK1", + "HCLK_VBRK_PHSR_PERFCLK1", + "HCLK_VBRK_CK_BUFRCLK2", + "HCLK_VBRK_MUX_CLK1", + "HCLK_VBRK_MUX_CLK10", + "HCLK_VBRK_MUX_CLK4", + "HCLK_VBRK_MUX_CLK12", + "HCLK_VBRK_MUX_CLK7", + "HCLK_VBRK_MUX_CLK6", + "HCLK_VBRK_CK_BUFHCLK10", + "HCLK_VBRK_PHSR_PERFCLK0", + "HCLK_VBRK_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFHCLK2", + "HCLK_VBRK_PHSR_PERFCLK2", + "HCLK_VBRK_REFCK_WESTCLK0", + "HCLK_VBRK_REFCK_EASTCLK1", + "HCLK_VBRK_CK_BUFHCLK4", + "HCLK_VBRK_MUX_CLK0", + "HCLK_VBRK_MUX_CLK13", + "HCLK_VBRK_CK_BUFRCLK1", + "HCLK_VBRK_MUX_CLK3", + "HCLK_VBRK_REFCK_WESTCLK1", + "HCLK_VBRK_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK5" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_HCLK_VFRAME.json b/kintex7/tile_type_HCLK_VFRAME.json new file mode 100644 index 0000000..9260b6c --- /dev/null +++ b/kintex7/tile_type_HCLK_VFRAME.json @@ -0,0 +1,37 @@ +{ + "tile_type": "HCLK_VFRAME", + "sites": [], + "wires": [ + "HCLK_VFRAME_CK_BUFHCLK1", + "HCLK_VFRAME_CK_IN12", + "HCLK_VFRAME_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK11", + "HCLK_VFRAME_CK_IN2", + "HCLK_VFRAME_CK_IN3", + "HCLK_VFRAME_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFHCLK6", + "HCLK_VFRAME_CK_IN7", + "HCLK_VFRAME_CK_IN5", + "HCLK_VFRAME_CK_BUFRCLK2", + "HCLK_VFRAME_CK_IN4", + "HCLK_VFRAME_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK3", + "HCLK_VFRAME_CK_IN10", + "HCLK_VFRAME_CK_BUFHCLK4", + "HCLK_VFRAME_CK_IN13", + "HCLK_VFRAME_CK_IN6", + "HCLK_VFRAME_CK_IN0", + "HCLK_VFRAME_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK0", + "HCLK_VFRAME_CK_BUFHCLK7", + "HCLK_VFRAME_CK_IN9", + "HCLK_VFRAME_CK_BUFHCLK2", + "HCLK_VFRAME_CK_IN8", + "HCLK_VFRAME_CK_IN1", + "HCLK_VFRAME_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFHCLK8", + "HCLK_VFRAME_CK_IN11" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_INT_FEEDTHRU_1.json b/kintex7/tile_type_INT_FEEDTHRU_1.json new file mode 100644 index 0000000..07f495b --- /dev/null +++ b/kintex7/tile_type_INT_FEEDTHRU_1.json @@ -0,0 +1,133 @@ +{ + "tile_type": "INT_FEEDTHRU_1", + "sites": [], + "wires": [ + "INT_FEEDTHRU_1_SE4C3", + "INT_FEEDTHRU_1_NW4END2", + "INT_FEEDTHRU_1_ER1BEG2", + "INT_FEEDTHRU_1_SE4BEG0", + "INT_FEEDTHRU_1_LH7", + "INT_FEEDTHRU_1_EE4C2", + "INT_FEEDTHRU_1_NE4C2", + "INT_FEEDTHRU_1_NE4C3", + "INT_FEEDTHRU_1_LH10", + "INT_FEEDTHRU_1_LH5", + "INT_FEEDTHRU_1_WW4C2", + "INT_FEEDTHRU_1_NW4A0", + "INT_FEEDTHRU_1_LH3", + "INT_FEEDTHRU_1_EE4BEG1", + "INT_FEEDTHRU_1_SW2A2", + "INT_FEEDTHRU_1_SE2A1", + "INT_FEEDTHRU_1_ER1BEG3", + "INT_FEEDTHRU_1_SW4A3", + "INT_FEEDTHRU_1_EE4A2", + "INT_FEEDTHRU_1_EE2A0", + "INT_FEEDTHRU_1_NE4BEG0", + "INT_FEEDTHRU_1_SW4END0", + "INT_FEEDTHRU_1_MONITOR_P", + "INT_FEEDTHRU_1_NE2A0", + "INT_FEEDTHRU_1_MONITOR_N", + "INT_FEEDTHRU_1_LH12", + "INT_FEEDTHRU_1_LH8", + "INT_FEEDTHRU_1_LH4", + "INT_FEEDTHRU_1_EE2BEG2", + "INT_FEEDTHRU_1_LH1", + "INT_FEEDTHRU_1_SE2A3", + "INT_FEEDTHRU_1_EE2BEG3", + "INT_FEEDTHRU_1_SE4C2", + "INT_FEEDTHRU_1_NW4END3", + "INT_FEEDTHRU_1_SW2A1", + "INT_FEEDTHRU_1_NW2A1", + "INT_FEEDTHRU_1_WL1END2", + "INT_FEEDTHRU_1_EE4A1", + "INT_FEEDTHRU_1_LH11", + "INT_FEEDTHRU_1_EE2BEG1", + "INT_FEEDTHRU_1_NE4C0", + "INT_FEEDTHRU_1_WW2END3", + "INT_FEEDTHRU_1_EE4BEG0", + "INT_FEEDTHRU_1_NW2A3", + "INT_FEEDTHRU_1_NE4BEG3", + "INT_FEEDTHRU_1_EE4B1", + "INT_FEEDTHRU_1_WL1END0", + "INT_FEEDTHRU_1_WR1END3", + "INT_FEEDTHRU_1_EE4BEG2", + "INT_FEEDTHRU_1_SW2A0", + "INT_FEEDTHRU_1_LH2", + "INT_FEEDTHRU_1_EL1BEG2", + "INT_FEEDTHRU_1_WW4A2", + "INT_FEEDTHRU_1_NW2A0", + "INT_FEEDTHRU_1_WW2A1", + "INT_FEEDTHRU_1_EL1BEG3", + "INT_FEEDTHRU_1_EE4C0", + "INT_FEEDTHRU_1_EE4BEG3", + "INT_FEEDTHRU_1_SE2A0", + "INT_FEEDTHRU_1_EE4A3", + "INT_FEEDTHRU_1_WW2END2", + "INT_FEEDTHRU_1_WW2END0", + "INT_FEEDTHRU_1_WW4B2", + "INT_FEEDTHRU_1_SW4END3", + "INT_FEEDTHRU_1_WW2A3", + "INT_FEEDTHRU_1_WW2A0", + "INT_FEEDTHRU_1_NW4A2", + "INT_FEEDTHRU_1_SE4C0", + "INT_FEEDTHRU_1_EE4C3", + "INT_FEEDTHRU_1_EE2BEG0", + "INT_FEEDTHRU_1_NW4END1", + "INT_FEEDTHRU_1_EE4C1", + "INT_FEEDTHRU_1_WW4END3", + "INT_FEEDTHRU_1_LH6", + "INT_FEEDTHRU_1_SE4BEG1", + "INT_FEEDTHRU_1_WW4B0", + "INT_FEEDTHRU_1_NE4C1", + "INT_FEEDTHRU_1_SW4A0", + "INT_FEEDTHRU_1_WW4A0", + "INT_FEEDTHRU_1_WW4END0", + "INT_FEEDTHRU_1_SW4A1", + "INT_FEEDTHRU_1_EL1BEG0", + "INT_FEEDTHRU_1_EE4B3", + "INT_FEEDTHRU_1_EE4A0", + "INT_FEEDTHRU_1_SE2A2", + "INT_FEEDTHRU_1_WW4END2", + "INT_FEEDTHRU_1_SW4END2", + "INT_FEEDTHRU_1_SE4BEG3", + "INT_FEEDTHRU_1_EE4B2", + "INT_FEEDTHRU_1_SW4A2", + "INT_FEEDTHRU_1_WW4C0", + "INT_FEEDTHRU_1_WR1END1", + "INT_FEEDTHRU_1_EE2A2", + "INT_FEEDTHRU_1_ER1BEG0", + "INT_FEEDTHRU_1_WW4C3", + "INT_FEEDTHRU_1_SW2A3", + "INT_FEEDTHRU_1_EE4B0", + "INT_FEEDTHRU_1_WR1END0", + "INT_FEEDTHRU_1_SW4END1", + "INT_FEEDTHRU_1_ER1BEG1", + "INT_FEEDTHRU_1_NW4A3", + "INT_FEEDTHRU_1_WL1END1", + "INT_FEEDTHRU_1_WR1END2", + "INT_FEEDTHRU_1_NW4A1", + "INT_FEEDTHRU_1_WW4END1", + "INT_FEEDTHRU_1_WW4B1", + "INT_FEEDTHRU_1_NE2A1", + "INT_FEEDTHRU_1_NE4BEG2", + "INT_FEEDTHRU_1_WW2A2", + "INT_FEEDTHRU_1_NW4END0", + "INT_FEEDTHRU_1_EL1BEG1", + "INT_FEEDTHRU_1_EE2A1", + "INT_FEEDTHRU_1_SE4C1", + "INT_FEEDTHRU_1_EE2A3", + "INT_FEEDTHRU_1_WW4C1", + "INT_FEEDTHRU_1_NE2A2", + "INT_FEEDTHRU_1_WW4B3", + "INT_FEEDTHRU_1_WW4A3", + "INT_FEEDTHRU_1_WW4A1", + "INT_FEEDTHRU_1_LH9", + "INT_FEEDTHRU_1_SE4BEG2", + "INT_FEEDTHRU_1_NE4BEG1", + "INT_FEEDTHRU_1_NE2A3", + "INT_FEEDTHRU_1_WW2END1", + "INT_FEEDTHRU_1_WL1END3", + "INT_FEEDTHRU_1_NW2A2" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_INT_FEEDTHRU_2.json b/kintex7/tile_type_INT_FEEDTHRU_2.json new file mode 100644 index 0000000..5cd05b1 --- /dev/null +++ b/kintex7/tile_type_INT_FEEDTHRU_2.json @@ -0,0 +1,133 @@ +{ + "tile_type": "INT_FEEDTHRU_2", + "sites": [], + "wires": [ + "INT_FEEDTHRU_2_SE4BEG3", + "INT_FEEDTHRU_2_NE4BEG3", + "INT_FEEDTHRU_2_WW4END0", + "INT_FEEDTHRU_2_NE2A0", + "INT_FEEDTHRU_2_SW4END0", + "INT_FEEDTHRU_2_SE2A0", + "INT_FEEDTHRU_2_EE4BEG1", + "INT_FEEDTHRU_2_WW4A3", + "INT_FEEDTHRU_2_LH5", + "INT_FEEDTHRU_2_NW4A1", + "INT_FEEDTHRU_2_SE2A2", + "INT_FEEDTHRU_2_EE4B3", + "INT_FEEDTHRU_2_WW4C2", + "INT_FEEDTHRU_2_WW2END3", + "INT_FEEDTHRU_2_LH6", + "INT_FEEDTHRU_2_EE4BEG0", + "INT_FEEDTHRU_2_WW2END0", + "INT_FEEDTHRU_2_NW2A1", + "INT_FEEDTHRU_2_SW4A3", + "INT_FEEDTHRU_2_SW4A2", + "INT_FEEDTHRU_2_MONITOR_P", + "INT_FEEDTHRU_2_WW4A0", + "INT_FEEDTHRU_2_WW4END2", + "INT_FEEDTHRU_2_LH7", + "INT_FEEDTHRU_2_EE4A3", + "INT_FEEDTHRU_2_EE4A2", + "INT_FEEDTHRU_2_WL1END0", + "INT_FEEDTHRU_2_EE2A0", + "INT_FEEDTHRU_2_WL1END2", + "INT_FEEDTHRU_2_SW2A0", + "INT_FEEDTHRU_2_SE4C0", + "INT_FEEDTHRU_2_NE4C2", + "INT_FEEDTHRU_2_EE2BEG3", + "INT_FEEDTHRU_2_EE2A1", + "INT_FEEDTHRU_2_EE4C0", + "INT_FEEDTHRU_2_EE4B2", + "INT_FEEDTHRU_2_LH3", + "INT_FEEDTHRU_2_SE2A3", + "INT_FEEDTHRU_2_SW4A1", + "INT_FEEDTHRU_2_NW4A2", + "INT_FEEDTHRU_2_WW4C1", + "INT_FEEDTHRU_2_NE4BEG0", + "INT_FEEDTHRU_2_WW4B3", + "INT_FEEDTHRU_2_WW2A1", + "INT_FEEDTHRU_2_ER1BEG0", + "INT_FEEDTHRU_2_NW4A3", + "INT_FEEDTHRU_2_LH8", + "INT_FEEDTHRU_2_SW2A2", + "INT_FEEDTHRU_2_SW2A3", + "INT_FEEDTHRU_2_NW4END2", + "INT_FEEDTHRU_2_LH10", + "INT_FEEDTHRU_2_EE2BEG0", + "INT_FEEDTHRU_2_WW2A0", + "INT_FEEDTHRU_2_EE4B1", + "INT_FEEDTHRU_2_ER1BEG3", + "INT_FEEDTHRU_2_WW2A3", + "INT_FEEDTHRU_2_NE2A1", + "INT_FEEDTHRU_2_LH2", + "INT_FEEDTHRU_2_EE4A0", + "INT_FEEDTHRU_2_WW2END1", + "INT_FEEDTHRU_2_WW4C0", + "INT_FEEDTHRU_2_EE4C1", + "INT_FEEDTHRU_2_EE4BEG2", + "INT_FEEDTHRU_2_SE4C1", + "INT_FEEDTHRU_2_SW4END2", + "INT_FEEDTHRU_2_MONITOR_N", + "INT_FEEDTHRU_2_NE4C0", + "INT_FEEDTHRU_2_WW2END2", + "INT_FEEDTHRU_2_SE4C2", + "INT_FEEDTHRU_2_WW4B0", + "INT_FEEDTHRU_2_NW2A2", + "INT_FEEDTHRU_2_ER1BEG1", + "INT_FEEDTHRU_2_NW2A0", + "INT_FEEDTHRU_2_SE2A1", + "INT_FEEDTHRU_2_WR1END2", + "INT_FEEDTHRU_2_WW4END1", + "INT_FEEDTHRU_2_LH12", + "INT_FEEDTHRU_2_WR1END0", + "INT_FEEDTHRU_2_WR1END3", + "INT_FEEDTHRU_2_ER1BEG2", + "INT_FEEDTHRU_2_LH11", + "INT_FEEDTHRU_2_LH1", + "INT_FEEDTHRU_2_WW4END3", + "INT_FEEDTHRU_2_EE2BEG1", + "INT_FEEDTHRU_2_LH4", + "INT_FEEDTHRU_2_WL1END1", + "INT_FEEDTHRU_2_WL1END3", + "INT_FEEDTHRU_2_WR1END1", + "INT_FEEDTHRU_2_EE2BEG2", + "INT_FEEDTHRU_2_EL1BEG3", + "INT_FEEDTHRU_2_NW4END3", + "INT_FEEDTHRU_2_NW2A3", + "INT_FEEDTHRU_2_EE2A3", + "INT_FEEDTHRU_2_EE4A1", + "INT_FEEDTHRU_2_NE4BEG2", + "INT_FEEDTHRU_2_SE4BEG0", + "INT_FEEDTHRU_2_NE4C1", + "INT_FEEDTHRU_2_SW2A1", + "INT_FEEDTHRU_2_EL1BEG2", + "INT_FEEDTHRU_2_EL1BEG1", + "INT_FEEDTHRU_2_SE4C3", + "INT_FEEDTHRU_2_EL1BEG0", + "INT_FEEDTHRU_2_WW2A2", + "INT_FEEDTHRU_2_WW4B1", + "INT_FEEDTHRU_2_NE4C3", + "INT_FEEDTHRU_2_WW4B2", + "INT_FEEDTHRU_2_EE4C2", + "INT_FEEDTHRU_2_EE4B0", + "INT_FEEDTHRU_2_NE2A3", + "INT_FEEDTHRU_2_SE4BEG1", + "INT_FEEDTHRU_2_WW4A2", + "INT_FEEDTHRU_2_WW4C3", + "INT_FEEDTHRU_2_EE2A2", + "INT_FEEDTHRU_2_WW4A1", + "INT_FEEDTHRU_2_LH9", + "INT_FEEDTHRU_2_EE4BEG3", + "INT_FEEDTHRU_2_SW4END1", + "INT_FEEDTHRU_2_SW4A0", + "INT_FEEDTHRU_2_NW4END1", + "INT_FEEDTHRU_2_NW4END0", + "INT_FEEDTHRU_2_NE2A2", + "INT_FEEDTHRU_2_NW4A0", + "INT_FEEDTHRU_2_SE4BEG2", + "INT_FEEDTHRU_2_EE4C3", + "INT_FEEDTHRU_2_SW4END3", + "INT_FEEDTHRU_2_NE4BEG1" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_INT_INTERFACE_L.json b/kintex7/tile_type_INT_INTERFACE_L.json new file mode 100644 index 0000000..cb2ca73 --- /dev/null +++ b/kintex7/tile_type_INT_INTERFACE_L.json @@ -0,0 +1,428 @@ +{ + "tile_type": "INT_INTERFACE_L", + "sites": [], + "wires": [ + "INT_INTERFACE_LOGIC_OUTS_L15", + "INT_INTERFACE_EE4C1", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_IMUX34", + "INT_INTERFACE_WW4C2", + "INT_INTERFACE_LH7", + "INT_INTERFACE_EE4C3", + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "INT_INTERFACE_LOGIC_OUTS_L11", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_IMUX12", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "INT_INTERFACE_BLOCK_OUTS_L_B3", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_IMUX3", + "INT_INTERFACE_LOGIC_OUTS_L23", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_LOGIC_OUTS_L7", + "INT_INTERFACE_IMUX5", + "INT_INTERFACE_LOGIC_OUTS_L3", + "INT_INTERFACE_LH11", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_LH8", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_SE2A2", + "INT_INTERFACE_IMUX46", + "INT_INTERFACE_WW4C1", + "INT_INTERFACE_IMUX29", + "INT_INTERFACE_SW2A3", + "INT_INTERFACE_IMUX24", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_IMUX47", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_IMUX9", + "INT_INTERFACE_EL1BEG3", + "L_INT_INTER_DQS_IOTOPHASER", + "INT_INTERFACE_LH5", + "INT_INTERFACE_IMUX17", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_INTERFACE_IMUX43", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_IMUX32", + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_SE4BEG3", + "INT_INTERFACE_IMUX36", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_LOGIC_OUTS_L13", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_IMUX10", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_WL1END1", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_LH10", + "INT_INTERFACE_LOGIC_OUTS_L22", + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_LOGIC_OUTS_L4", + "INT_INTERFACE_IMUX41", + "INT_INTERFACE_IMUX15", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_IMUX7", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_LH2", + "INT_INTERFACE_BLOCK_OUTS_L_B0", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_IMUX33", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_LH1", + "INT_INTERFACE_LOGIC_OUTS_L6", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_LH9", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_IMUX8", + "INT_INTERFACE_LH4", + "INT_INTERFACE_IMUX16", + "INT_INTERFACE_LOGIC_OUTS_L19", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_IMUX22", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_IMUX30", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_LOGIC_OUTS_L12", + "INT_INTERFACE_IMUX40", + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_BLOCK_OUTS_L_B1", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LH3", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_LOGIC_OUTS_L18", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "INT_INTERFACE_LOGIC_OUTS_L1", + "INT_INTERFACE_IMUX28", + "INT_INTERFACE_LOGIC_OUTS_L2", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_IMUX23", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "INT_INTERFACE_IMUX0", + "INT_INTERFACE_IMUX19", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_IMUX6", + "INT_INTERFACE_FAN5", + "INT_INTERFACE_LOGIC_OUTS_L8", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_IMUX37", + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_LOGIC_OUTS_L21", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_BYP5", + "INT_INTERFACE_IMUX25", + "INT_INTERFACE_IMUX39", + "INT_INTERFACE_IMUX26", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_LOGIC_OUTS_L14", + "INT_INTERFACE_LOGIC_OUTS_L10", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_IMUX14", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "INT_INTERFACE_IMUX35", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_IMUX42", + "INT_INTERFACE_IMUX4", + "INT_INTERFACE_WW4B1", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_IMUX45", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_IMUX1", + "INT_INTERFACE_IMUX18", + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "INT_INTERFACE_WW4A1", + "INT_INTERFACE_IMUX20", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_LOGIC_OUTS_L16", + "INT_INTERFACE_IMUX38", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_IMUX11", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_IMUX13", + "INT_INTERFACE_LH6", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_LH12", + "INT_INTERFACE_LOGIC_OUTS_L20", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "INT_INTERFACE_WR1END1", + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "INT_INTERFACE_IMUX31", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_IMUX44", + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_IMUX27", + "INT_INTERFACE_IMUX2", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_WW4END0", + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_EE2A3", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_LOGIC_OUTS_L5", + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_IMUX21", + "INT_INTERFACE_LOGIC_OUTS_L9", + "INT_INTERFACE_BYP7", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_BLOCK_OUTS_L_B2", + "INT_INTERFACE_LOGIC_OUTS_L17", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_LOGIC_OUTS_L0" + ], + "pips": { + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_INT_INTERFACE_R.json b/kintex7/tile_type_INT_INTERFACE_R.json new file mode 100644 index 0000000..17f0643 --- /dev/null +++ b/kintex7/tile_type_INT_INTERFACE_R.json @@ -0,0 +1,428 @@ +{ + "tile_type": "INT_INTERFACE_R", + "sites": [], + "wires": [ + "INT_INTERFACE_EE4C1", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_IMUX34", + "INT_INTERFACE_WW4C2", + "INT_INTERFACE_LH7", + "INT_INTERFACE_EE4C3", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_LOGIC_OUTS_B22", + "INT_INTERFACE_IMUX12", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_LOGIC_OUTS16", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_LOGIC_OUTS3", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_LOGIC_OUTS20", + "INT_INTERFACE_LOGIC_OUTS22", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_IMUX3", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_LH8", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_LH11", + "INT_INTERFACE_IMUX5", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_LOGIC_OUTS1", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_LOGIC_OUTS0", + "INT_INTERFACE_BLOCK_OUTS_B0", + "INT_INTERFACE_SE2A2", + "INT_INTERFACE_IMUX46", + "INT_INTERFACE_WW4C1", + "INT_INTERFACE_IMUX29", + "INT_INTERFACE_SW2A3", + "INT_INTERFACE_IMUX24", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_IMUX47", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_IMUX9", + "INT_INTERFACE_EL1BEG3", + "L_INT_INTER_DQS_IOTOPHASER", + "INT_INTERFACE_LH5", + "INT_INTERFACE_IMUX17", + "INT_INTERFACE_BLOCK_OUTS_B3", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_INTERFACE_IMUX43", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_IMUX32", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_SE4BEG3", + "INT_INTERFACE_IMUX36", + "INT_INTERFACE_LOGIC_OUTS_B2", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_LOGIC_OUTS_B20", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_IMUX10", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_WL1END1", + "INT_INTERFACE_LOGIC_OUTS_B23", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_LH10", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_LOGIC_OUTS_B6", + "INT_INTERFACE_IMUX41", + "INT_INTERFACE_IMUX15", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_IMUX7", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_LOGIC_OUTS18", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_LOGIC_OUTS_B16", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_LH2", + "INT_INTERFACE_LOGIC_OUTS_B14", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_IMUX33", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_LOGIC_OUTS23", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_LH1", + "INT_INTERFACE_LOGIC_OUTS5", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_LH9", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_IMUX8", + "INT_INTERFACE_LH4", + "INT_INTERFACE_IMUX16", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_IMUX22", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_IMUX30", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_LOGIC_OUTS15", + "INT_INTERFACE_IMUX40", + "INT_INTERFACE_LOGIC_OUTS_B19", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_LOGIC_OUTS11", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LOGIC_OUTS_B17", + "INT_INTERFACE_LH3", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_LOGIC_OUTS_B15", + "INT_INTERFACE_LOGIC_OUTS_B9", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_LOGIC_OUTS_B0", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_BLOCK_OUTS_B1", + "INT_INTERFACE_LOGIC_OUTS_B7", + "INT_INTERFACE_LOGIC_OUTS_B8", + "INT_INTERFACE_LOGIC_OUTS14", + "INT_INTERFACE_IMUX28", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_LOGIC_OUTS8", + "INT_INTERFACE_IMUX23", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_LOGIC_OUTS12", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_LOGIC_OUTS4", + "INT_INTERFACE_IMUX0", + "INT_INTERFACE_IMUX19", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_LOGIC_OUTS_B3", + "INT_INTERFACE_IMUX6", + "INT_INTERFACE_LOGIC_OUTS21", + "INT_INTERFACE_FAN5", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_IMUX37", + "INT_INTERFACE_LOGIC_OUTS7", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_LOGIC_OUTS_B18", + "INT_INTERFACE_BYP5", + "INT_INTERFACE_IMUX25", + "INT_INTERFACE_IMUX39", + "INT_INTERFACE_IMUX26", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_IMUX14", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_LOGIC_OUTS_B4", + "INT_INTERFACE_IMUX35", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_IMUX42", + "INT_INTERFACE_IMUX4", + "INT_INTERFACE_WW4B1", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_IMUX45", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_LOGIC_OUTS_B21", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_IMUX1", + "INT_INTERFACE_IMUX18", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_WW4A1", + "INT_INTERFACE_IMUX20", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_IMUX38", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_IMUX11", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_IMUX13", + "INT_INTERFACE_LH6", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_LH12", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_WR1END1", + "INT_INTERFACE_LOGIC_OUTS10", + "INT_INTERFACE_IMUX31", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_LOGIC_OUTS13", + "INT_INTERFACE_IMUX44", + "INT_INTERFACE_LOGIC_OUTS_B11", + "INT_INTERFACE_LOGIC_OUTS9", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_IMUX27", + "INT_INTERFACE_IMUX2", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_LOGIC_OUTS_B10", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_LOGIC_OUTS_B5", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_LOGIC_OUTS19", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_BLOCK_OUTS_B2", + "INT_INTERFACE_WW4END0", + "INT_INTERFACE_LOGIC_OUTS17", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_LOGIC_OUTS_B13", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_EE2A3", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_LOGIC_OUTS2", + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_IMUX21", + "INT_INTERFACE_LOGIC_OUTS6", + "INT_INTERFACE_BYP7", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LOGIC_OUTS_B12", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + "pips": { + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B17", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B0", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B2", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B20", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B19", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B22", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B14", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B11", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B5", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B6", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B7", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B9", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B16", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B10", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B12", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B13", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B23", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B4", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B18", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B8", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B3", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B15", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B21", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS21", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_INT_L.json b/kintex7/tile_type_INT_L.json new file mode 100644 index 0000000..2a8754f --- /dev/null +++ b/kintex7/tile_type_INT_L.json @@ -0,0 +1,26779 @@ +{ + "tile_type": "INT_L", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "TIEOFF", + "type": "TIEOFF", + "site_pins": { + "HARD0": "GND_WIRE", + "HARD1": "VCC_WIRE" + }, + "x_coord": 0 + } + ], + "wires": [ + "EE4BEG2", + "LOGIC_OUTS_L12", + "SW6E2", + "WW4END2", + "GND_WIRE", + "WR1BEG_S0", + "FAN_BOUNCE_S3_6", + "EE2A3", + "SE6D2", + "EE4END0", + "SR1END2", + "SW6A1", + "LV_L4", + "SS2END2", + "IMUX_L41", + "IMUX_L36", + "FAN_L5", + "EE4BEG0", + "SS6D0", + "GCLK_L_B2", + "SE6B1", + "WW4C0", + "BYP_L2", + "SR1END3", + "EE4END2", + "GCLK_L_B0", + "SL1END1", + "LOGIC_OUTS_L14", + "SL1BEG0", + "MONITOR_P", + "SS6A1", + "LOGIC_OUTS_L9", + "NE6A1", + "NN6END0", + "SE6A3", + "SE2END2", + "WL1BEG3", + "LV_L14", + "SS2BEG1", + "LOGIC_OUTS_L3", + "IMUX_L44", + "INT_DQS_IOTOPHASER", + "FAN_L3", + "SE2BEG3", + "GFAN0", + "GCLK_L_B11_WEST", + "WW4B2", + "NE6E1", + "SS6END0", + "EE4B3", + "NW6BEG0", + "SE2A3", + "NW2END2", + "SS2BEG0", + "WR1END1", + "LOGIC_OUTS_L16", + "NW6E1", + "IMUX_L37", + "IMUX_L15", + "EE2BEG2", + "SW6C1", + "SE6D0", + "GCLK_L_B6", + "WW2A2", + "NN6C2", + "LH1", + "NE6B0", + "SW6A3", + "FAN_BOUNCE5", + "FAN_BOUNCE7", + "SE6BEG3", + "NL1END_S3_0", + "SS6END1", + "LVB_L5", + "LH7", + "SS2END_N0_3", + "SW2END_N0_3", + "LH4", + "EE2BEG0", + "BYP_BOUNCE3", + "SW6E1", + "EL1END0", + "SS2A1", + "NN6A1", + "SW2END0", + "FAN_L7", + "SR1BEG_S0", + "SW6END_N0_3", + "CTRL_L1", + "SE6B3", + "SE6END1", + "SE6D1", + "IMUX_L28", + "BYP_BOUNCE_N3_6", + "EE4C3", + "NN2BEG0", + "LOGIC_OUTS_L0", + "WL1BEG1", + "NR1BEG1", + "NW6E2", + "SE6C1", + "SE6E1", + "NW6E0", + "LV_L15", + "SE6END0", + "LV_L6", + "EL1BEG2", + "LH0", + "WW4B1", + "SE6A2", + "LVB_L3", + "BYP_L4", + "NN2END2", + "FAN_ALT2", + "ER1BEG0", + "EE2BEG1", + "SW2END3", + "IMUX_L1", + "IMUX_L5", + "IMUX_L18", + "LVB_L0", + "BYP_L6", + "BYP_ALT7", + "SE2BEG0", + "NE6D2", + "BYP_ALT1", + "EL1END_S3_0", + "LV_L11", + "SS6END3", + "NN6D1", + "EL1END3", + "LOGIC_OUTS_L13", + "LOGIC_OUTS_L2", + "NW6C0", + "IMUX_L10", + "SS6BEG1", + "SL1END0", + "GCLK_L_B3", + "LVB_L9", + "SE2A0", + "LH11", + "LOGIC_OUTS_L23", + "NN6D2", + "IMUX_L27", + "NW6A0", + "GCLK_L_B8_WEST", + "GCLK_L_B7_EAST", + "SW2A0", + "WW4B0", + "WW4B3", + "SS2END1", + "LOGIC_OUTS_L4", + "WW2END1", + "IMUX_L38", + "INT_PHASER_TO_IO_OCLK1X_90", + "LV_L2", + "LOGIC_OUTS_L22", + "SW6A2", + "WW2END_N0_3", + "FAN_ALT6", + "EE4BEG1", + "NE6C0", + "LOGIC_OUTS_L11", + "LV_L17", + "EE4C2", + "SS6B1", + "GCLK_L_B11_EAST", + "BYP_BOUNCE4", + "NW6A2", + "NE6END2", + "WW2BEG1", + "NW6END0", + "SL1BEG3", + "NW2A1", + "GCLK_L_B9", + "NN6D3", + "SE2END0", + "EL1END1", + "NN6A2", + "NN6END3", + "SS6D3", + "NW2END3", + "NR1BEG3", + "NE2BEG1", + "BYP_BOUNCE5", + "SS6E2", + "LV_L13", + "SE6BEG2", + "NW6END3", + "SE2BEG1", + "LVB_L4", + "NN2END1", + "SW6B2", + "BYP_L7", + "SE6A1", + "EE4BEG3", + "GCLK_L_B4", + "WR1BEG0", + "SW6C0", + "SS6C3", + "INT_PHASER_TO_IO_ICLK", + "IMUX_L42", + "SW6BEG0", + "CLK_L0", + "LV_L5", + "SE6A0", + "SS6D2", + "SW2BEG1", + "NW6C3", + "SE6C3", + "INT_PHASER_TO_IO_ICLKDIV", + "GCLK_L_B10_WEST", + "NL1BEG1", + "FAN_ALT7", + "LOGIC_OUTS_L15", + "LV_L9", + "NN6E3", + "NW2A3", + "IMUX_L6", + "NR1BEG0", + "WR1END0", + "LOGIC_OUTS_L19", + "IMUX_L12", + "SE6E0", + "SW2END1", + "SE6D3", + "SR1BEG1", + "EE2A1", + "FAN_L0", + "GCLK_L_B7_WEST", + "NW2BEG0", + "LVB_L8", + "LV_L7", + "LH5", + "NN6B2", + "IMUX_L24", + "NW2END1", + "NN6C0", + "NE6A0", + "SE2BEG2", + "LVB_L1", + "IMUX_L34", + "NE6C2", + "NW2A2", + "LOGIC_OUTS_L6", + "SS6E0", + "NR1END2", + "IMUX_L43", + "SR1BEG3", + "SS2BEG3", + "BYP_ALT5", + "BYP_BOUNCE_N3_2", + "NE2BEG2", + "NW6E3", + "SE2A2", + "SW6END1", + "FAN_BOUNCE_S3_4", + "NE6BEG1", + "LOGIC_OUTS_L17", + "NW6B2", + "WW2A0", + "WW4BEG3", + "SS6BEG0", + "EE4C0", + "BYP_BOUNCE_N3_7", + "NN6C1", + "WL1END3", + "NN6BEG3", + "EE2END0", + "NL1END0", + "BYP_BOUNCE_N3_3", + "SW2END2", + "SS6BEG2", + "GCLK_L_B8_EAST", + "NW6D1", + "LOGIC_OUTS_L10", + "NE2END0", + "EE4END1", + "IMUX_L4", + "SS6B2", + "LOGIC_OUTS_L21", + "FAN_L1", + "IMUX_L46", + "NN6B0", + "SE6C2", + "NN6END2", + "NE2END2", + "FAN_ALT4", + "SS6END2", + "SS2END0", + "EL1BEG3", + "NW6A1", + "IMUX_L32", + "FAN_BOUNCE1", + "NE2A0", + "SS6B0", + "SS6D1", + "SW6C2", + "FAN_BOUNCE6", + "GCLK_L_B9_EAST", + "LOGIC_OUTS_L18", + "WR1BEG3", + "EE4B1", + "SW2A3", + "NL1END2", + "EE4B2", + "FAN_BOUNCE_S3_2", + "BYP_ALT2", + "SW6BEG2", + "NN6END1", + "INT_PHASER_TO_IO_OCLKDIV", + "IMUX_L3", + "ER1BEG3", + "EE4A3", + "ER1END3", + "NW6D2", + "NW2END_S0_0", + "NN6D0", + "FAN_ALT1", + "NR1END3", + "EE4C1", + "NN6BEG1", + "WR1BEG1", + "NW6A3", + "NE6BEG0", + "SS2A0", + "SS6E1", + "WW2END2", + "SW6END2", + "EL1BEG0", + "NN2END3", + "SW6E3", + "EE4A2", + "GFAN1", + "IMUX_L21", + "LV_L8", + "SS6C0", + "SR1END_N3_3", + "GCLK_L_B8", + "NE6B2", + "ER1END2", + "ER1BEG2", + "EE4END3", + "IMUX_L39", + "NW6END2", + "EE2END3", + "NR1END0", + "LV_L16", + "SS6BEG3", + "SL1BEG2", + "EL1BEG1", + "BYP_L1", + "NN6C3", + "NN6BEG0", + "LVB_L7", + "NW6C1", + "NW6BEG3", + "NE2A3", + "SS2END3", + "FAN_BOUNCE2", + "WW4A3", + "NE6D3", + "SS6C1", + "NE6END3", + "INT_PHASER_TO_IO_OCLK", + "GCLK_L_B7", + "WW2BEG2", + "NN2A3", + "SS6C2", + "IMUX_L30", + "IMUX_L13", + "EL1BEG_N3", + "GCLK_L_B6_WEST", + "LH6", + "IMUX_L31", + "ER1BEG1", + "LH10", + "NN6A0", + "GCLK_L_B1", + "SL1END2", + "NE6C3", + "WW4END0", + "SW6D2", + "LV_L3", + "LV_L12", + "GCLK_L_B6_EAST", + "WW2A1", + "NW6D3", + "LV_L10", + "WL1END0", + "NE6D1", + "NE6A2", + "GCLK_L_B10", + "SW6D0", + "GCLK_L_B11", + "IMUX_L35", + "BYP_ALT3", + "NN2END0", + "LOGIC_OUTS_L5", + "IMUX_L22", + "NE6E0", + "NE2A1", + "EE4A1", + "LOGIC_OUTS_L20", + "NN6E0", + "NE6D0", + "IMUX_L25", + "BYP_BOUNCE7", + "NE2A2", + "BYP_BOUNCE6", + "NN6B3", + "EE2A2", + "LVB_L11", + "IMUX_L26", + "IMUX_L47", + "FAN_L2", + "WL1BEG2", + "NN2BEG1", + "NE6END1", + "NN6E2", + "SW6END3", + "IMUX_L20", + "NW2BEG1", + "WW4C2", + "ER1END_N3_3", + "IMUX_L0", + "WW4BEG2", + "IMUX_L7", + "ER1END0", + "IMUX_L45", + "NN6END_S1_0", + "FAN_L6", + "LVB_L2", + "NL1BEG_N3", + "WL1END_N1_3", + "SL1END3", + "NE6END0", + "IMUX_L17", + "WW4C3", + "WW2END3", + "NE6BEG3", + "NN6B1", + "NE2END1", + "SS6E3", + "SE6E3", + "NW6C2", + "GCLK_L_B5", + "NW6D0", + "MONITOR_N", + "WW2BEG0", + "SW6D1", + "NW6B3", + "WW2A3", + "FAN_BOUNCE_S3_0", + "BYP_L5", + "LH3", + "SE6END3", + "WL1BEG0", + "BYP_BOUNCE2", + "NN6E1", + "FAN_ALT0", + "NL1BEG0", + "LVB_L6", + "FAN_ALT3", + "WW4END1", + "IMUX_L16", + "SR1BEG2", + "LV_L0", + "SW6D3", + "SE2END1", + "SE6END2", + "WW4END3", + "CTRL_L0", + "SE6C0", + "NW6END1", + "WW4A2", + "SE2A1", + "SW6BEG1", + "NW6BEG1", + "LH2", + "NE6BEG2", + "SS6A0", + "NN2A0", + "IMUX_L40", + "SL1BEG1", + "SW2BEG0", + "GCLK_L_B9_WEST", + "WW4BEG0", + "EL1END2", + "SR1END1", + "NN6A3", + "NW6BEG2", + "WW4END_S0_0", + "EE2A0", + "NW2A0", + "LVB_L10", + "SW6B0", + "BYP_ALT0", + "SS6A3", + "LV_L18", + "SS2BEG2", + "IMUX_L11", + "WW2BEG3", + "SE6BEG0", + "FAN_L4", + "NE6C1", + "WL1END1", + "SW2A2", + "NE6A3", + "WR1BEG2", + "SS6B3", + "WL1END2", + "BYP_L3", + "EE4B0", + "SW6B1", + "SW6E0", + "SS6A2", + "NE6E3", + "FAN_BOUNCE4", + "NE2END3", + "NN2A2", + "EE2BEG3", + "NE2BEG0", + "SW6END0", + "NW6B1", + "SS2A3", + "FAN_BOUNCE3", + "SE2END3", + "IMUX_L9", + "LOGIC_OUTS_L7", + "WW4C1", + "NW6END_S0_0", + "SW2BEG2", + "CLK_L1", + "SS6END_N0_3", + "SW6BEG3", + "FAN_ALT5", + "LV_L1", + "LOGIC_OUTS_L8", + "BYP_BOUNCE1", + "IMUX_L33", + "BYP_ALT6", + "LH9", + "ER1END1", + "EE2END2", + "NE6B1", + "ER1BEG_S0", + "NE2END_S3_0", + "SW2BEG3", + "WW4A0", + "IMUX_L14", + "FAN_BOUNCE0", + "WR1END_S1_0", + "WW2END0", + "LH8", + "NL1END1", + "NW2END0", + "NN2A1", + "IMUX_L23", + "SW6C3", + "WR1END2", + "IMUX_L2", + "LH12", + "NL1BEG2", + "NW2BEG3", + "WL1BEG_N3", + "NN2BEG2", + "WW4BEG1", + "NR1END1", + "SE6B0", + "SW6B3", + "EE2END1", + "IMUX_L8", + "NW2BEG2", + "NR1BEG2", + "NE2BEG3", + "SS2A2", + "BYP_ALT4", + "SE6BEG1", + "IMUX_L19", + "NN6BEG2", + "NN2END_S2_0", + "SW2A1", + "NW6B0", + "BYP_L0", + "WR1END3", + "IMUX_L29", + "GCLK_L_B10_EAST", + "VCC_WIRE", + "SE6B2", + "SE6E2", + "NE6E2", + "BYP_BOUNCE0", + "LOGIC_OUTS_L1", + "NN2BEG3", + "EE4A0", + "NE6B3", + "WW4A1", + "SW6A0", + "LVB_L12" + ], + "pips": { + "INT_L.NN6END0->>WR1BEG1": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>EL1BEG1": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>IMUX_L17": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>WR1BEG2": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>IMUX_L8": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>IMUX_L24": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>NR1BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>IMUX_L26": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>SL1BEG0": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>IMUX_L29": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>EE2BEG1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END_N0_3->>IMUX_L16": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>IMUX_L39": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>FAN_ALT1": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>SE2BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>IMUX_L21": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>SL1BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>IMUX_L22": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH12->>SE6BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>IMUX_L24": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>SL1BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>SE2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>SL1BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>IMUX_L27": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>ER1BEG1": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>SR1BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>SE2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>NW6BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>NN6BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>IMUX_L13": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>LV_L0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "LV_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>NN2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>IMUX_L9": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L25": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>WW2BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>FAN_ALT3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>LV_L18": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "LV_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>SE2BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L37": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>IMUX_L46": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>SR1BEG1": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>GFAN1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>IMUX_L37": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>SW2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>WR1BEG2": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>SL1BEG1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH6->>SW6BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>FAN_ALT3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L44": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>SW6BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>SE2BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>WR1BEG2": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>NW2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>SR1BEG_S0": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>IMUX_L37": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L9->>NW6BEG1": { + "src_wire": "LV_L9", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>NL1BEG0": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>IMUX_L15": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>IMUX_L17": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>EE2BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE6->>IMUX_L33": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>IMUX_L1": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>IMUX_L10": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>SS2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L30": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>IMUX_L2": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L13": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>FAN_ALT2": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>IMUX_L23": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>NE6BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>NW6BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>NR1BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>NN6BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>WW4BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L12": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>NN6BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>SW2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>IMUX_L33": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>IMUX_L7": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>IMUX_L5": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L45": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>IMUX_L12": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>SW6BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>EL1BEG1": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>IMUX_L37": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>IMUX_L37": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>BYP_ALT5": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>SW6BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>FAN_ALT7": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>BYP_ALT4": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>IMUX_L5": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>ER1BEG1": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>EL1BEG0": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>IMUX_L12": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>NW6BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>LVB_L0": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>WR1BEG_S0": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>SS2BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B1->>CLK_L1": { + "src_wire": "GCLK_L_B1", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>NW6BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>EL1BEG0": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>WW2BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>IMUX_L31": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>BYP_ALT2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>IMUX_L36": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>IMUX_L18": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>IMUX_L12": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>SR1BEG1": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L6": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_2->>IMUX_L22": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>IMUX_L42": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L47": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>FAN_ALT6": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>SW6BEG2": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>NW6BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L21": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>SW2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>WW2BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>CTRL_L0": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>NE6BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>ER1BEG1": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>BYP_ALT0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>EL1BEG0": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>IMUX_L7": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>IMUX_L1": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>WW4BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END_N3_3->>IMUX_L8": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>EE2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>WR1BEG1": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END_S2_0->>SR1BEG_S0": { + "src_wire": "NN2END_S2_0", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>IMUX_L30": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>NN6BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>FAN_ALT1": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>SE2BEG2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>GFAN0": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>EE2BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>IMUX_L5": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B2->>CLK_L1": { + "src_wire": "GCLK_L_B2", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>IMUX_L45": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>BYP_ALT1": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>NN2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>NE2BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>IMUX_L14": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>NE2BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L11": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>SW2BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>NL1BEG1": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>WW4BEG1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>NW6BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>IMUX_L45": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>SL1BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>IMUX_L3": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>SS6BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>SW2BEG3": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>SW6BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>BYP_ALT5": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>IMUX_L19": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>IMUX_L43": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L29": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>IMUX_L40": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>WR1BEG3": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>IMUX_L30": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>IMUX_L11": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>SW6BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END_S3_0->>IMUX_L31": { + "src_wire": "EL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>SS6BEG0": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L42": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>SE2BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L15": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>ER1BEG1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L12->>SE6BEG2": { + "src_wire": "LVB_L12", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>SW6BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B3->>CLK_L1": { + "src_wire": "GCLK_L_B3", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>SW2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>BYP_ALT2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>SE2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>IMUX_L40": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>NW2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>NL1BEG0": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L27": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>IMUX_L39": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>FAN_ALT4": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>LH0": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>BYP_ALT2": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>ER1BEG2": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>WL1BEG0": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>WR1BEG1": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B9->>GCLK_L_B9_WEST": { + "src_wire": "GCLK_L_B9", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B9_WEST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>IMUX_L38": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>FAN_ALT7": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>BYP_ALT0": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L2": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>NW2BEG1": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>IMUX_L40": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>NR1BEG2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>IMUX_L35": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>IMUX_L40": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>IMUX_L20": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>BYP_ALT2": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B10->>GCLK_L_B10_WEST": { + "src_wire": "GCLK_L_B10", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B10_WEST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>IMUX_L19": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>WR1BEG3": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_6->>IMUX_L31": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>BYP_ALT5": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>IMUX_L23": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L19": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>EL1BEG2": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>SE6BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>NL1BEG1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>NE2BEG0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>IMUX_L43": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>IMUX_L32": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>SE6BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L18": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>NN6BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>IMUX_L11": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>FAN_ALT6": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>FAN_ALT1": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END0->>NW6BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END_N0_3->>WW4BEG0": { + "src_wire": "SS2END_N0_3", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>NL1BEG_N3": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>SE6BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>NL1BEG2": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>IMUX_L28": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>NN6BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L42": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>SR1BEG1": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L9->>NE6BEG1": { + "src_wire": "LV_L9", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L20": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>SL1BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>IMUX_L13": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>IMUX_L23": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L12": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>IMUX_L34": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>NE6BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>NN2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>WW4BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>IMUX_L30": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>NW2BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>WR1BEG1": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L11": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT6->>BYP_L6": { + "src_wire": "BYP_ALT6", + "is_pseudo": "0", + "dst_wire": "BYP_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>SS6BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>IMUX_L24": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>IMUX_L12": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>EL1BEG0": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_3->>FAN_ALT4": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B3->>CLK_L0": { + "src_wire": "GCLK_L_B3", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>IMUX_L47": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>IMUX_L43": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>NR1BEG0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>NN6BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>IMUX_L27": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>IMUX_L43": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>SW6BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>WL1BEG_N3": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>WR1BEG_S0": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>NN2BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>SW2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>BYP_ALT0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>SR1BEG2": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>IMUX_L24": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>FAN_ALT6": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>IMUX_L41": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>SL1BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>SS2BEG1": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>NE2BEG0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>IMUX_L22": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L8": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>FAN_ALT2": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>LV_L0": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "LV_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>FAN_ALT2": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>NN6BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>IMUX_L14": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>SE6BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L26": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>FAN_ALT0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>IMUX_L6": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>NE2BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>IMUX_L28": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END0->>WR1BEG1": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>IMUX_L12": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>IMUX_L17": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>NE6BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>NR1BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>IMUX_L21": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>CLK_L1": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>BYP_ALT1": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>LVB_L12": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B11_WEST->>CLK_L1": { + "src_wire": "GCLK_L_B11_WEST", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>IMUX_L28": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L18": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END_N0_3->>IMUX_L0": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>IMUX_L13": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>SE6BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>IMUX_L36": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>NW2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>FAN_ALT0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>WW2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>IMUX_L33": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>NE6BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>BYP_ALT2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>ER1BEG2": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>IMUX_L3": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>SE2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>FAN_ALT7": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>EE4BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>SL1BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>FAN_ALT0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>SE6BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>IMUX_L44": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>SE6BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>IMUX_L27": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>IMUX_L44": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>IMUX_L44": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>NW2BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>IMUX_L2": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE2->>BYP_ALT0": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END_N0_3->>NL1BEG_N3": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>SL1BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>BYP_ALT6": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>IMUX_L31": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>SE6BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>NR1BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>IMUX_L24": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH0->>SW6BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>SS2BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>SW2BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>IMUX_L27": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>SE6BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>SE2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>SE6BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>IMUX_L6": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L28": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>SS2BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>SL1BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>BYP_ALT5": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH12->>LVB_L0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>NE2BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>IMUX_L41": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>IMUX_L3": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>FAN_ALT1": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>WL1BEG2": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>SR1BEG1": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>WL1BEG1": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>WR1BEG_S0": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>WW4BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>SE6BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>NR1BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>SR1BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L5": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>BYP_ALT3": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>IMUX_L18": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>SW6BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE3->>IMUX_L7": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L9->>NN6BEG1": { + "src_wire": "LV_L9", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>FAN_ALT5": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B9_WEST->>CLK_L0": { + "src_wire": "GCLK_L_B9_WEST", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>EL1BEG2": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>SL1BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>NN6BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>IMUX_L29": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>WR1BEG3": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>NE6BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>BYP_ALT7": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>IMUX_L41": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>WW4BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B9->>GCLK_L_B9_EAST": { + "src_wire": "GCLK_L_B9", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B9_EAST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>NL1BEG2": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>ER1BEG2": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>CTRL_L0": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>WR1BEG2": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>EE4BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>NR1BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>NW2BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B5->>GFAN0": { + "src_wire": "GCLK_L_B5", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>SW2BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>IMUX_L42": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L22": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>IMUX_L38": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>SW6BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L12->>NE6BEG2": { + "src_wire": "LVB_L12", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>SS6BEG2": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>NN6BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>FAN_ALT3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>SS6BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>SW2BEG1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>NE2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>IMUX_L36": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>SS2BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>EE4BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_2->>IMUX_L24": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>SW6BEG1": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>IMUX_L40": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>NR1BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH6->>LVB_L0": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>IMUX_L14": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>FAN_ALT1": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>SL1BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>NR1BEG0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L41": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>SS2BEG1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>NN2BEG2": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>NE6BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>WW2BEG2": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>IMUX_L6": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>NL1BEG_N3": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>SE2BEG2": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>IMUX_L2": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>SW2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>SL1BEG3": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L31": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>SE2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>NE6BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>IMUX_L32": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>NW2BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>WR1BEG3": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>ER1BEG2": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>FAN_ALT5": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>WW4BEG3": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>ER1BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>NL1BEG1": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>SS6BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>NW6BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>CTRL_L0": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH6->>SS6BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>IMUX_L0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>EE4BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>IMUX_L38": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L17": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>IMUX_L29": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>NE2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>WW2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L18->>EE4BEG3": { + "src_wire": "LV_L18", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>FAN_ALT1": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L8": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>NN6BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>FAN_ALT0": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END0->>NL1BEG_N3": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>EE4BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>NW6BEG3": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>IMUX_L37": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>SL1BEG3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L39": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>ER1BEG_S0": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L41": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>WW2BEG1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>IMUX_L1": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>SS6BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>EE2BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>IMUX_L15": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>BYP_ALT2": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>NE6BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>SL1BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>IMUX_L14": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>NN2BEG1": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>NE2BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L13": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT1->>FAN_L1": { + "src_wire": "FAN_ALT1", + "is_pseudo": "0", + "dst_wire": "FAN_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L0->>LVB_L0": { + "src_wire": "LV_L0", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>IMUX_L1": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>NN6BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>NE2BEG1": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>SR1BEG_S0": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>NW2BEG3": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B7_WEST->>GFAN1": { + "src_wire": "GCLK_L_B7_WEST", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>SS6BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>NW6BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>IMUX_L10": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>IMUX_L25": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>SW2BEG0": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>IMUX_L10": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B4->>GFAN0": { + "src_wire": "GCLK_L_B4", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L28": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>IMUX_L16": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>WR1BEG2": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>IMUX_L20": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>SS2BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>SW2BEG1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B2->>CLK_L0": { + "src_wire": "GCLK_L_B2", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>SS2BEG3": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L18->>WW4BEG3": { + "src_wire": "LV_L18", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>WW4BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>NR1BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>IMUX_L20": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>IMUX_L27": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>IMUX_L7": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>NN2BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>NE6BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>NE6BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>SS2BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L2": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>NN6BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>SL1BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>NN2BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>IMUX_L21": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>NE6BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>WW4BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>IMUX_L30": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>IMUX_L30": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>NW2BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>IMUX_L35": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>FAN_ALT4": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>IMUX_L42": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>BYP_ALT4": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>CTRL_L1": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>IMUX_L14": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>SW2BEG2": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>SE2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>NE6BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>SE6BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>NN2BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>BYP_ALT4": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>SS2BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>FAN_ALT0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L43": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>IMUX_L26": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B9_WEST->>GFAN1": { + "src_wire": "GCLK_L_B9_WEST", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>IMUX_L22": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B11_WEST->>GFAN1": { + "src_wire": "GCLK_L_B11_WEST", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>IMUX_L29": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>EE4BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END_N0_3->>IMUX_L16": { + "src_wire": "SS2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>NN6BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>WW2BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>BYP_ALT2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>NE2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>WW2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>IMUX_L24": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>EE4BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L0": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L29": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>IMUX_L38": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>NW6BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>NN6BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>LVB_L12": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>SS2BEG2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>IMUX_L2": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>SW2BEG3": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>EE4BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE2->>IMUX_L8": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>IMUX_L11": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>BYP_ALT6": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>SS2BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>WL1BEG1": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>NE2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH0->>EE4BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>BYP_ALT3": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END0->>NE6BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT7->>FAN_L7": { + "src_wire": "FAN_ALT7", + "is_pseudo": "0", + "dst_wire": "FAN_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>EE4BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>EL1BEG2": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>NN2BEG1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>IMUX_L46": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>NW2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>EE4BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>SE2BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>IMUX_L28": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>NN2BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>IMUX_L15": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>WW2BEG3": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>IMUX_L13": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>FAN_ALT6": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>FAN_ALT5": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L21": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>SS2BEG2": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>IMUX_L2": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>NR1BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>EE4BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>SW6BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>NL1BEG1": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>IMUX_L1": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>BYP_ALT3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>IMUX_L14": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>SW6BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>IMUX_L0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>NW2BEG0": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>ER1BEG_S0": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>IMUX_L27": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>GFAN0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>IMUX_L2": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>EE2BEG0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>IMUX_L32": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>SW6BEG2": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>EE2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>IMUX_L25": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>BYP_ALT4": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L10": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE2->>FAN_ALT4": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>EE2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>IMUX_L30": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>WL1BEG1": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>IMUX_L32": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>NE2BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>NN6BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>NL1BEG1": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>IMUX_L46": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>IMUX_L4": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>WW4BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>WL1BEG2": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END_S1_0->>IMUX_L31": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>WW4BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>FAN_ALT4": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B9_WEST->>CLK_L1": { + "src_wire": "GCLK_L_B9_WEST", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>IMUX_L13": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L6": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>SR1BEG1": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>SE2BEG1": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>IMUX_L6": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>NR1BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>EL1BEG2": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>NW6BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L4": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>WL1BEG2": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>IMUX_L14": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>WR1BEG2": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>SR1BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_2->>IMUX_L32": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>NL1BEG2": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>SS2BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT1->>BYP_BOUNCE1": { + "src_wire": "BYP_ALT1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>SE2BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>WW2BEG0": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>IMUX_L26": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT2->>BYP_L2": { + "src_wire": "BYP_ALT2", + "is_pseudo": "0", + "dst_wire": "BYP_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>SE2BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>IMUX_L41": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>NE6BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>BYP_ALT0": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>WW2BEG2": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>IMUX_L8": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>IMUX_L7": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L45": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>BYP_ALT1": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>IMUX_L2": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>SW2BEG0": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>WW4BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>NE6BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>SS6BEG0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>NW2BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>SS6BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>SE2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>IMUX_L3": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>FAN_ALT5": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>WL1BEG0": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L12->>NW6BEG2": { + "src_wire": "LVB_L12", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END_N1_3->>NW2BEG0": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>SS2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>SE2BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>BYP_ALT3": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>SS2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>SS6BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>IMUX_L17": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>EE4BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>FAN_ALT5": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>NN6BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>ER1BEG2": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>SW6BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>NR1BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>NE6BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>IMUX_L15": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>NW2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L43": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE2->>IMUX_L6": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>IMUX_L4": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L18": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>WR1BEG3": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>EL1BEG2": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>NR1BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>IMUX_L44": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>NN2BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>SW6BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>IMUX_L22": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>WW2BEG3": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>NN2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>SW2BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>IMUX_L5": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>EE2BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE2->>IMUX_L24": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>WR1BEG2": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>FAN_ALT6": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>NE2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>SR1BEG1": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>NR1BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>IMUX_L33": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>BYP_ALT2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>IMUX_L8": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>SL1BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>IMUX_L19": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>SS2BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>NN2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L36": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>WW2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_6->>IMUX_L15": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>SL1BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>NR1BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>IMUX_L24": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>SE6BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>NL1BEG_N3": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>IMUX_L29": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L30": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END0->>LV_L0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "LV_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>SS6BEG1": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>FAN_ALT7": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>BYP_ALT5": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L32": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L30": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END_S0_0->>SS6BEG3": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>IMUX_L0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L44": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>WR1BEG3": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>EL1BEG_N3": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END_S3_0->>IMUX_L47": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>IMUX_L11": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L12->>NN6BEG2": { + "src_wire": "LVB_L12", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END0->>NN2BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>NR1BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>IMUX_L45": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>IMUX_L33": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>NE6BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>IMUX_L21": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>SE6BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>WL1BEG2": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>SE6BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>BYP_ALT4": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>BYP_ALT1": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L28": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>NW2BEG2": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>IMUX_L14": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>FAN_ALT7": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH6->>LV_L18": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "LV_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>FAN_ALT2": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>SE6BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>SS2BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>SE2BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>SW2BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>NN2BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>FAN_ALT1": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>SS2BEG0": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>NR1BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>SL1BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>IMUX_L9": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>NE2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>IMUX_L32": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>IMUX_L23": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>BYP_ALT6": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>ER1BEG_S0": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>NN6BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>WW4BEG2": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L21": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>IMUX_L46": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>NL1BEG0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>IMUX_L13": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B5->>CLK_L0": { + "src_wire": "GCLK_L_B5", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>IMUX_L46": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>IMUX_L9": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>SW6BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>NR1BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>WL1BEG_N3": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END_N0_3->>NW2BEG0": { + "src_wire": "SW6END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>FAN_ALT6": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>NW2BEG0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>IMUX_L15": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>SR1BEG_S0": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>IMUX_L28": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>NW6BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END0->>NN6BEG0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>EE2BEG2": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L40": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>FAN_ALT3": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>EE4BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>IMUX_L20": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>NR1BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>NE6BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>IMUX_L29": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>WW4BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>NR1BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>SS6BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>SR1BEG3": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L11": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>FAN_ALT4": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L40": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>IMUX_L19": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>WR1BEG1": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>NW6BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH6->>SE6BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>IMUX_L47": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>EE4BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>FAN_ALT3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>IMUX_L42": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>ER1BEG2": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>NL1BEG2": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>WL1BEG0": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>EE2BEG3": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L15": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>IMUX_L24": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>IMUX_L41": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>IMUX_L47": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>BYP_ALT0": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>NW2BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>SS2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>IMUX_L20": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>IMUX_L19": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>SW2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>SR1BEG1": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>NR1BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L23": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>NN6BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>BYP_ALT7": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>SS2BEG1": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>NE6BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>IMUX_L38": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>WR1BEG_S0": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>EE4BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>NL1BEG0": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>IMUX_L4": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>IMUX_L23": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>FAN_ALT5": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>IMUX_L40": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>NN6BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>IMUX_L45": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>NW2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>IMUX_L30": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>IMUX_L6": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>IMUX_L6": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>CTRL_L1": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>WW2BEG1": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>SE6BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>IMUX_L18": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>IMUX_L36": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>LH0": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>EL1BEG2": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B10_WEST->>CLK_L1": { + "src_wire": "GCLK_L_B10_WEST", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>SW6BEG0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>NR1BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>EE2BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>BYP_ALT5": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>IMUX_L28": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B0->>CLK_L1": { + "src_wire": "GCLK_L_B0", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L0->>SW6BEG2": { + "src_wire": "LVB_L0", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>SW6BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>BYP_ALT3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>IMUX_L6": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L9->>SW6BEG1": { + "src_wire": "LV_L9", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>EL1BEG2": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>IMUX_L12": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>EE2BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>NW2BEG0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>NN6BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>BYP_ALT1": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>SE2BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>SL1BEG2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>CLK_L0": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>NE6BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END_S1_0->>IMUX_L47": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>SE6BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>FAN_ALT6": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>NW2BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>FAN_ALT1": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>IMUX_L11": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>IMUX_L45": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>SS2BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>IMUX_L13": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>IMUX_L10": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>SS2BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>SE6BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>IMUX_L20": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>SE2BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>BYP_ALT5": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L3": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>IMUX_L17": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>NN6BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L19": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>EE2BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>IMUX_L6": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>IMUX_L45": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>SW6BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>EL1BEG0": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L32": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>NW6BEG2": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L3": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>FAN_ALT2": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>NE6BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>IMUX_L6": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>ER1BEG_S0": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>NN2BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>NW6BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>IMUX_L5": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END_N1_3->>WR1BEG1": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>IMUX_L11": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>IMUX_L45": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>SS6BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>NW2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>IMUX_L16": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>IMUX_L25": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L26": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>IMUX_L40": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>WL1BEG2": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>NN6BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L4": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>IMUX_L41": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>SS6BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>WL1BEG0": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>WW2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>EE4BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>IMUX_L45": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>EE2BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>EE4BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L0->>WW4BEG0": { + "src_wire": "LV_L0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>EE4BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>IMUX_L27": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L46": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>SL1BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>IMUX_L25": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>SL1BEG0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>IMUX_L41": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>SE2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>NE2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>NE6BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>NN6BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>NE2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>IMUX_L17": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>IMUX_L20": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L35": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>IMUX_L1": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>BYP_ALT4": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>SS2BEG3": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>WW4BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>SS6BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>NE2BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>SE6BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>SS6BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>IMUX_L21": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>WL1BEG0": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>CTRL_L1": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L6": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>IMUX_L23": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>IMUX_L44": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>WW2BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>NR1BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>IMUX_L19": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>SS2BEG3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>IMUX_L19": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>SL1BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>WW2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>WR1BEG1": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>IMUX_L17": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>SW6BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>NW2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>SE6BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>IMUX_L44": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>SE2BEG1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>SE2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT0->>FAN_L0": { + "src_wire": "FAN_ALT0", + "is_pseudo": "0", + "dst_wire": "FAN_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>SS2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>IMUX_L32": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>SR1BEG2": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>NN6BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>IMUX_L40": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>EE2BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>NE6BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>EL1BEG2": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>FAN_ALT1": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>CTRL_L0": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>ER1BEG3": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>SS2BEG3": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END_S0_0->>SR1BEG_S0": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>FAN_ALT1": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT6->>FAN_BOUNCE6": { + "src_wire": "FAN_ALT6", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>SR1BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT5->>BYP_L5": { + "src_wire": "BYP_ALT5", + "is_pseudo": "0", + "dst_wire": "BYP_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>IMUX_L41": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>IMUX_L17": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>SW6BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B3->>GFAN1": { + "src_wire": "GCLK_L_B3", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>NW6BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>IMUX_L46": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>IMUX_L32": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>WW4BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>CLK_L1": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>NW2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>BYP_ALT2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>IMUX_L27": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>EE4BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>IMUX_L24": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END_S1_0->>SR1BEG_S0": { + "src_wire": "NN6END_S1_0", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>SS2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>FAN_ALT3": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>IMUX_L36": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>FAN_ALT7": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>IMUX_L28": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_6->>IMUX_L39": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>IMUX_L5": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>NN2BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END_S3_0->>IMUX_L39": { + "src_wire": "EL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>IMUX_L0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>EE4BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>IMUX_L40": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>SE6BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L27": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>IMUX_L31": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>SS2BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>IMUX_L26": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>IMUX_L4": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>EL1BEG_N3": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>SL1BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>WL1BEG_N3": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B7_WEST->>GFAN0": { + "src_wire": "GCLK_L_B7_WEST", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>BYP_ALT3": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>SW6BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>IMUX_L14": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>SS2BEG2": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>NE6BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>IMUX_L12": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_6->>BYP_ALT7": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>WW2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>BYP_ALT1": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>NN2BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>EE4BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>NN2BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>IMUX_L17": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>NN6BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>NE6BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>LV_L0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "LV_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>IMUX_L17": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>BYP_ALT1": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>NE2BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>IMUX_L38": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END_S3_0->>IMUX_L47": { + "src_wire": "EL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>IMUX_L6": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END_N1_3->>FAN_ALT0": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B7_WEST->>CLK_L0": { + "src_wire": "GCLK_L_B7_WEST", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>FAN_ALT2": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>NL1BEG1": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>FAN_ALT5": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>EL1BEG1": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>EE2BEG2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>NE2BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>BYP_ALT2": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>EE4BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>CTRL_L0": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>IMUX_L3": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>NN6BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>SW6BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>IMUX_L8": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L11": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>IMUX_L9": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>FAN_ALT1": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>NE6BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>BYP_ALT3": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>SW6BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>SE6BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>SE2BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>BYP_ALT7": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>SS2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>IMUX_L10": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>SE2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>NN6BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>SL1BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>IMUX_L5": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L44": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>EE4BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>NN6BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>NE2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>IMUX_L7": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>SW6BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>IMUX_L35": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L27": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>EE2BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>NN6BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>FAN_ALT0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>IMUX_L25": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L24": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>LVB_L0": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L1": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>SW2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>IMUX_L32": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>FAN_ALT3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>ER1BEG2": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>WW4BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L18<<->>LH0": { + "src_wire": "LV_L18", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "0", + "can_invert": "0" + }, + "INT_L.ER1END3->>IMUX_L47": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>IMUX_L7": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>IMUX_L22": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>SW6BEG0": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>SL1BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>NE2BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>SS6BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>BYP_ALT7": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>IMUX_L42": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>SE6BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>SW2BEG1": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L0->>NE6BEG2": { + "src_wire": "LVB_L0", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B6_WEST->>GFAN1": { + "src_wire": "GCLK_L_B6_WEST", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>FAN_ALT6": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>SS6BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END_S0_0->>WL1BEG2": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L23": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>IMUX_L10": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>NL1BEG1": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>IMUX_L13": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L0->>SE6BEG0": { + "src_wire": "LV_L0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>SW2BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>SE2BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT4->>BYP_BOUNCE4": { + "src_wire": "BYP_ALT4", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>EE4BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>SW2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L12->>WW4BEG2": { + "src_wire": "LVB_L12", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>IMUX_L20": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>FAN_ALT3": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>IMUX_L33": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L34": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>SW6BEG2": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>WW4BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>SW6BEG3": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>IMUX_L46": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>WW4BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>NE2BEG2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>FAN_ALT3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>IMUX_L6": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>WR1BEG3": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L21": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>WL1BEG2": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>NR1BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>SE6BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>LVB_L0": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>ER1BEG3": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>SW2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>WW4BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>SS6BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>EE2BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>FAN_ALT0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>NR1BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>SE6BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>WR1BEG2": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>NL1BEG_N3": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>NR1BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>FAN_ALT3": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>NN6BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>NW2BEG3": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>EE2BEG0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>IMUX_L41": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>EE2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>IMUX_L36": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>NE2BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>WW2BEG1": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>SS6BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>NR1BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>NN2BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>IMUX_L1": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>IMUX_L25": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>NW6BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>SE2BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>IMUX_L5": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>NE2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>SR1BEG2": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>FAN_ALT6": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>IMUX_L5": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END0->>NN2BEG0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>EE2BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>NN2BEG0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>IMUX_L13": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>IMUX_L21": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>FAN_ALT1": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>WL1BEG0": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>IMUX_L42": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>IMUX_L20": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>SE2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>SE2BEG3": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B1->>GFAN1": { + "src_wire": "GCLK_L_B1", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>WR1BEG2": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>SS6BEG1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>SR1BEG3": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>NW6BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>IMUX_L29": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>FAN_ALT2": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>SS2BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>IMUX_L27": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>IMUX_L46": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>IMUX_L18": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>IMUX_L35": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L44": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>LVB_L0": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END_N3_3->>IMUX_L0": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>NR1BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>SR1BEG1": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>IMUX_L9": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>IMUX_L29": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B5->>GFAN1": { + "src_wire": "GCLK_L_B5", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>NW2BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>SE6BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>WW4BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>NR1BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>BYP_ALT5": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>EE2BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>WW2BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>BYP_ALT6": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>IMUX_L45": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>SE2BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH6->>LV_L0": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "LV_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>NE6BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>NN2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B11->>GCLK_L_B11_WEST": { + "src_wire": "GCLK_L_B11", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B11_WEST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>NN2BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>NN2BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L0<<->>LV_L18": { + "src_wire": "LV_L0", + "is_pseudo": "0", + "dst_wire": "LV_L18", + "is_directional": "0", + "can_invert": "0" + }, + "INT_L.LV_L9->>SS6BEG1": { + "src_wire": "LV_L9", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>NW2BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>FAN_ALT1": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>IMUX_L10": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>NE2BEG0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>WL1BEG_N3": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>IMUX_L3": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>FAN_ALT4": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>EL1BEG0": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>NN2BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>SS2BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>NN6BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>IMUX_L32": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>NN6BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>IMUX_L0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>EL1BEG0": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>IMUX_L35": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>EL1BEG0": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>FAN_ALT7": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L0->>EE4BEG2": { + "src_wire": "LVB_L0", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>FAN_ALT7": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>NW6BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>BYP_ALT0": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>LH0": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>SE2BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>EL1BEG1": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>IMUX_L36": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>NL1BEG0": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>NR1BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>IMUX_L46": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>NN6BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE6->>IMUX_L9": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>WW2BEG0": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>FAN_ALT1": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>IMUX_L46": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>IMUX_L9": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>EE4BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>NN6BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END_S2_0->>IMUX_L47": { + "src_wire": "NN2END_S2_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>GFAN1": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>SL1BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>BYP_ALT0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L26": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>EE2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>IMUX_L1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>SS2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L38": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>NL1BEG2": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L43": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>IMUX_L22": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE6->>IMUX_L1": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L1": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>NW6BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>FAN_ALT0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>BYP_ALT0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>IMUX_L2": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>IMUX_L39": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>IMUX_L34": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B1->>GFAN0": { + "src_wire": "GCLK_L_B1", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>WW4BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>WW4BEG3": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>EE2BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>SW6BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>IMUX_L41": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END0->>LV_L18": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "LV_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END_N0_3->>FAN_ALT0": { + "src_wire": "SS2END_N0_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>BYP_ALT6": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L5": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L47": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>NE6BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>IMUX_L18": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>LVB_L0": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GND_WIRE->>GFAN0": { + "src_wire": "GND_WIRE", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>NL1BEG1": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_6->>IMUX_L23": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>EE2BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>SR1BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L17": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>WW4BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>IMUX_L4": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>SW6BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END_S0_0->>SW6BEG3": { + "src_wire": "NW6END_S0_0", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>BYP_ALT1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>IMUX_L35": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>IMUX_L3": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>IMUX_L34": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B5->>CLK_L1": { + "src_wire": "GCLK_L_B5", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L29": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT7->>FAN_BOUNCE7": { + "src_wire": "FAN_ALT7", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>IMUX_L47": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END0->>WW4BEG0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>BYP_ALT1": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B8->>GCLK_L_B8_WEST": { + "src_wire": "GCLK_L_B8", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B8_WEST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>FAN_ALT5": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>IMUX_L27": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>NN6BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>IMUX_L37": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>EL1BEG2": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>SL1BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>IMUX_L39": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>ER1BEG2": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L42": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>IMUX_L8": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>IMUX_L37": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>FAN_ALT6": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>IMUX_L42": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>EL1BEG1": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>IMUX_L16": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>CTRL_L0": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>BYP_ALT1": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>SW2BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>NE6BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>SW2BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L9": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>SW6BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>WL1BEG1": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>NE6BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>IMUX_L9": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>ER1BEG1": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>WW4BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>FAN_ALT2": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>FAN_ALT4": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>SR1BEG1": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>SR1BEG_S0": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L0->>NE6BEG0": { + "src_wire": "LV_L0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>BYP_ALT6": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>IMUX_L34": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>IMUX_L44": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>BYP_ALT5": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>NE2BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>NL1BEG_N3": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>IMUX_L21": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END_N0_3->>NL1BEG_N3": { + "src_wire": "SW6END_N0_3", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>IMUX_L28": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>NW6BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>IMUX_L35": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L0->>SS6BEG2": { + "src_wire": "LVB_L0", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>IMUX_L30": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>NR1BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>ER1BEG3": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L41": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>IMUX_L3": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>NW6BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>SE2BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L34": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>NE2BEG3": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>SE2BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>ER1BEG2": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L20": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>FAN_ALT5": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>IMUX_L16": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>IMUX_L3": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>SW2BEG2": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>NE2BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>FAN_ALT6": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>IMUX_L44": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END_S0_0->>WL1BEG2": { + "src_wire": "NW6END_S0_0", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>FAN_ALT0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>BYP_ALT0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>SE2BEG2": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT4->>FAN_BOUNCE4": { + "src_wire": "FAN_ALT4", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END_S0_0->>SW2BEG3": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>IMUX_L28": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>IMUX_L5": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>LVB_L12": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END0->>NW2BEG0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>IMUX_L42": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L14": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>WR1BEG1": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>SS2BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>SW6BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>IMUX_L9": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE6->>BYP_ALT1": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>NW2BEG1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L15": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>EE2BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>FAN_ALT2": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>IMUX_L26": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>NW2BEG2": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>NR1BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END_N0_3->>IMUX_L8": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>IMUX_L36": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>IMUX_L39": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>EE2BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>IMUX_L6": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>NR1BEG3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END_N3_3->>IMUX_L0": { + "src_wire": "ER1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>BYP_ALT2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>NL1BEG2": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>NR1BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>NN6BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>SL1BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L17": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>IMUX_L47": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>BYP_ALT2": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>NW2BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>NW6BEG2": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>NE6BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>NL1BEG0": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>SS6BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>IMUX_L4": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>SL1BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>NR1BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>SE2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>IMUX_L41": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>SR1BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L18->>NW6BEG3": { + "src_wire": "LV_L18", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>BYP_ALT6": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>LH0": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>WR1BEG2": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>CTRL_L1": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>SS6BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>SS2BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L36": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>BYP_ALT1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>NW6BEG3": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>ER1BEG3": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>IMUX_L36": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>NN6BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>IMUX_L9": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>IMUX_L14": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>BYP_ALT4": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>FAN_ALT7": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>IMUX_L22": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>IMUX_L36": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>SR1BEG_S0": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>SR1BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>IMUX_L22": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>EL1BEG0": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>SS2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>SL1BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>FAN_ALT1": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>IMUX_L17": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_3->>IMUX_L1": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>NR1BEG1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>IMUX_L18": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>IMUX_L17": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>SE6BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>IMUX_L38": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>BYP_ALT0": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>NN2BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>SE6BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>EE2BEG3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>SS6BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>NE2BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>IMUX_L29": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>NE2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>EE4BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>NW6BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>WW4BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L24": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>WL1BEG0": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>NL1BEG0": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>SW6BEG1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>IMUX_L3": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>BYP_ALT1": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>IMUX_L31": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B0->>CLK_L0": { + "src_wire": "GCLK_L_B0", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>NN6BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>SW6BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>ER1BEG3": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>NN2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>LVB_L0": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>CTRL_L0": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>NE6BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L0->>LVB_L12": { + "src_wire": "LV_L0", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>BYP_ALT3": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>IMUX_L37": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>SE2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>SW2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>FAN_ALT3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L33": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>BYP_ALT4": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>WW2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>NL1BEG2": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END_S3_0->>BYP_ALT7": { + "src_wire": "NE2END_S3_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>IMUX_L14": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>IMUX_L22": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END_S2_0->>BYP_ALT7": { + "src_wire": "NN2END_S2_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>SW2BEG1": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>SW6BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>IMUX_L10": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L38": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>NE2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>IMUX_L7": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>FAN_ALT4": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>NW2BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH0->>NW6BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>IMUX_L30": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>NW6BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>SS6BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>NW6BEG1": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_3->>IMUX_L17": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE2->>IMUX_L40": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>SE6BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>EL1BEG_N3": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L6": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>WW2BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>IMUX_L35": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>IMUX_L15": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>IMUX_L42": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>BYP_ALT2": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>IMUX_L1": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>EE4BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>SE6BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>NR1BEG3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L0->>SE6BEG2": { + "src_wire": "LVB_L0", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>EL1BEG1": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>SS6BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>NW6BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>NR1BEG0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH0->>SE6BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END_N3_3->>BYP_ALT0": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>EE4BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>BYP_ALT5": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>NN2BEG0": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>NE6BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>IMUX_L19": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>WW4BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>IMUX_L9": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>IMUX_L13": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>ER1BEG3": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>SS6BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>NE6BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L22": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>IMUX_L16": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE3->>BYP_ALT6": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>CLK_L0": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE6->>IMUX_L25": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>EE2BEG3": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE6->>IMUX_L17": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>IMUX_L9": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>EE2BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>SE2BEG0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>SW6BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>NW2BEG2": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>IMUX_L9": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>SE6BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>BYP_ALT4": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>IMUX_L18": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L35": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT6->>BYP_BOUNCE6": { + "src_wire": "BYP_ALT6", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L31": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>IMUX_L22": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>NE2BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>WW4BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>NW6BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>BYP_ALT3": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END_N3_3->>IMUX_L16": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT7->>BYP_BOUNCE7": { + "src_wire": "BYP_ALT7", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>SW2BEG2": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>SE6BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT2->>BYP_BOUNCE2": { + "src_wire": "BYP_ALT2", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>EL1BEG1": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>SW6BEG0": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>FAN_ALT5": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>NW2BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>NN2BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>EE4BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>EE4BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>GFAN0": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>FAN_ALT7": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L19": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>WW4BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L5": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>WW2BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>SL1BEG1": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L31": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>SL1BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>IMUX_L5": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>SW6BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>SW2BEG0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>NW2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>NL1BEG0": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>BYP_ALT4": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>SE6BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>NW6BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>IMUX_L4": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END_S3_0->>IMUX_L39": { + "src_wire": "NE2END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>WW2BEG2": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>NL1BEG0": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>IMUX_L9": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>SS2BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>BYP_ALT2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>SE6BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>WW4BEG1": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>NN2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>BYP_ALT7": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>IMUX_L19": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>WR1BEG2": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>NL1BEG2": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>BYP_ALT5": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_2->>IMUX_L14": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>IMUX_L19": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>NE2BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>NE6BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>IMUX_L2": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>NW2BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>IMUX_L11": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>LH12": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>WL1BEG_N3": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>SL1BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>IMUX_L25": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>NE2BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>WR1BEG3": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>ER1BEG2": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>SL1BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L40": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>IMUX_L42": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>IMUX_L31": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>CTRL_L1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>EL1BEG1": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L27": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L29": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>IMUX_L41": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH0->>LVB_L12": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>IMUX_L44": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>IMUX_L25": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>NE6BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>IMUX_L5": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>WR1BEG1": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>EL1BEG2": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B11->>GCLK_L_B11_EAST": { + "src_wire": "GCLK_L_B11", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B11_EAST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH12->>LVB_L12": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>SE2BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>SW2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L0->>SS6BEG0": { + "src_wire": "LV_L0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>IMUX_L44": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>SS2BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>IMUX_L27": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L13": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>BYP_ALT5": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>NW2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>BYP_ALT0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END0->>LV_L18": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "LV_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>IMUX_L4": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>SS6BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>SL1BEG2": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>NW2BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>NW2BEG0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>WW2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>ER1BEG_S0": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>NR1BEG2": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>BYP_ALT6": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>IMUX_L40": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>NW6BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>FAN_ALT3": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>CTRL_L0": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>ER1BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>BYP_ALT3": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>FAN_ALT1": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>EL1BEG_N3": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>FAN_ALT7": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L24": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>NW2BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>EE4BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>EE4BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>IMUX_L15": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L20": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L11": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>SE2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>IMUX_L47": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L3": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>FAN_ALT4": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>IMUX_L16": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>NW6BEG1": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>SS6BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END_S1_0->>WW2BEG3": { + "src_wire": "NN6END_S1_0", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>WW4BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B7->>GCLK_L_B7_EAST": { + "src_wire": "GCLK_L_B7", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B7_EAST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>SS2BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END_N0_3->>IMUX_L8": { + "src_wire": "SS2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>BYP_ALT3": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>ER1BEG3": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>SS6BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>SS2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>SE2BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>IMUX_L0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>EL1BEG2": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>NL1BEG_N3": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>NN6BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>BYP_ALT1": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>IMUX_L15": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>IMUX_L6": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>SR1BEG2": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>IMUX_L32": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>FAN_ALT5": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>IMUX_L10": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>WL1BEG1": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>ER1BEG1": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END_N3_3->>IMUX_L8": { + "src_wire": "ER1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>NE2BEG1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>NN2BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>IMUX_L17": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>EE4BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>IMUX_L2": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>SW2BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END_S3_0->>IMUX_L7": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>IMUX_L46": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>BYP_ALT4": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>IMUX_L18": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE6->>FAN_ALT2": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>SW6BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>WR1BEG3": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>WR1BEG_S0": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>SL1BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>BYP_ALT0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>SL1BEG3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>NE6BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END_S1_0->>WW2BEG3": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>SW6BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>NE2BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>WL1BEG_N3": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L20": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>IMUX_L29": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>IMUX_L24": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>BYP_ALT1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>NR1BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>SW6BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>SR1BEG3": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>SW2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>NN6BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>SL1BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>EL1BEG0": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>NN6BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>WW2BEG0": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>NE6BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>IMUX_L29": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>SS6BEG1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>NN2BEG3": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>NE2BEG0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>SW6BEG3": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>NW6BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L27": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>IMUX_L4": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>ER1BEG3": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>SR1BEG_S0": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>IMUX_L24": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>SE2BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>EE2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>IMUX_L25": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>NR1BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B8_WEST->>CLK_L0": { + "src_wire": "GCLK_L_B8_WEST", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>NL1BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_3->>BYP_ALT0": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE2->>FAN_ALT1": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>IMUX_L24": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>ER1BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>IMUX_L22": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>IMUX_L29": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>NN2BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L12": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>IMUX_L16": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>NR1BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B11_WEST->>CLK_L0": { + "src_wire": "GCLK_L_B11_WEST", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>IMUX_L30": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>NN2BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L42": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>NN2BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>ER1BEG3": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>SE2BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>IMUX_L8": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>IMUX_L19": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>SW2BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>IMUX_L19": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L43": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>SR1BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>NL1BEG0": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>IMUX_L37": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END_S3_0->>IMUX_L23": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>WR1BEG1": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>IMUX_L41": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>NL1BEG0": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>ER1BEG_S0": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>CLK_L1": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>IMUX_L34": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>ER1BEG1": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>IMUX_L36": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>NR1BEG1": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>NW2BEG3": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>IMUX_L3": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>IMUX_L24": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_3->>IMUX_L33": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L14": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_2->>IMUX_L46": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>IMUX_L46": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>FAN_ALT7": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>FAN_ALT4": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>SE6BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>NE2BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_6->>IMUX_L7": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>WW2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>IMUX_L34": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>WR1BEG_S0": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>NE6BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>NR1BEG3": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>IMUX_L28": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>NW6BEG2": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>BYP_ALT5": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>IMUX_L22": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>WR1BEG1": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>IMUX_L38": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>SE2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>NW6BEG1": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT0->>FAN_BOUNCE0": { + "src_wire": "FAN_ALT0", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>SL1BEG1": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>SW6BEG1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>NW6BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH6->>NN6BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>EL1BEG1": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>NE6BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>IMUX_L17": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>SE6BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>IMUX_L5": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>EE4BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>WL1BEG2": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>NR1BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>SW6BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>SE6BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>BYP_ALT2": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>IMUX_L4": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>IMUX_L38": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH12->>WW4BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>SS6BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END_N0_3->>WW4BEG0": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>EL1BEG_N3": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>SS2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>WW4BEG2": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>BYP_ALT0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>IMUX_L21": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>WW4BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>IMUX_L14": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>FAN_ALT4": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>WW2BEG1": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>CTRL_L0": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>EL1BEG1": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT6->>FAN_L6": { + "src_wire": "FAN_ALT6", + "is_pseudo": "0", + "dst_wire": "FAN_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>IMUX_L37": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>BYP_ALT1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>SW2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L18<<->>LH12": { + "src_wire": "LV_L18", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "0", + "can_invert": "0" + }, + "INT_L.WR1END3->>WW2BEG2": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>IMUX_L13": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>IMUX_L27": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>SE6BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>NR1BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END_S3_0->>IMUX_L47": { + "src_wire": "NE2END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>SE2BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>SR1BEG3": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>SR1BEG2": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>IMUX_L46": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>SR1BEG1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>FAN_ALT4": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>IMUX_L43": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>SE6BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>BYP_ALT6": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>FAN_ALT7": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>EE4BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>WR1BEG1": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>EL1BEG0": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L0->>SW6BEG0": { + "src_wire": "LV_L0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L29": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>IMUX_L6": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>IMUX_L34": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>SL1BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END_N3_3->>IMUX_L16": { + "src_wire": "ER1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>EE2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>WW2BEG0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>BYP_ALT5": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>IMUX_L12": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>ER1BEG3": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>BYP_ALT5": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>LV_L18": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "LV_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>LH12": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END_N0_3->>IMUX_L0": { + "src_wire": "SS2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>WW2BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>FAN_ALT4": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>SL1BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END0->>NE6BEG0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>NL1BEG2": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>EE4BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>IMUX_L4": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L0->>WW4BEG2": { + "src_wire": "LVB_L0", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>SW2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>IMUX_L34": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>IMUX_L23": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L33": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>IMUX_L23": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>WL1BEG1": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>IMUX_L11": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>CTRL_L1": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH6->>EE4BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>IMUX_L35": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>IMUX_L15": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE2->>IMUX_L16": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>IMUX_L44": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>IMUX_L12": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>SS2BEG0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>WR1BEG1": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>NL1BEG0": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>EL1BEG0": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>IMUX_L1": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>NW6BEG2": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END_S3_0->>IMUX_L31": { + "src_wire": "NE2END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L13": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>NE2BEG2": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>WW4BEG1": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>IMUX_L15": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L9": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>IMUX_L24": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>SE2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>SW2BEG2": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L45": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>SS6BEG3": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>SE2BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>IMUX_L21": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L2": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>FAN_ALT2": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>EL1BEG_N3": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>NW6BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B6_WEST->>CLK_L0": { + "src_wire": "GCLK_L_B6_WEST", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>IMUX_L33": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L0<<->>LH12": { + "src_wire": "LV_L0", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "0", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>NN6BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>IMUX_L45": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>IMUX_L9": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END_S2_0->>WW2BEG3": { + "src_wire": "NN2END_S2_0", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>IMUX_L40": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>SS6BEG3": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>EL1BEG1": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>FAN_ALT0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH0->>WW4BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L12->>EE4BEG2": { + "src_wire": "LVB_L12", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT5->>FAN_L5": { + "src_wire": "FAN_ALT5", + "is_pseudo": "0", + "dst_wire": "FAN_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>EE2BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>IMUX_L44": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>IMUX_L16": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END_S2_0->>IMUX_L31": { + "src_wire": "NN2END_S2_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>SR1BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT0->>BYP_BOUNCE0": { + "src_wire": "BYP_ALT0", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>EL1BEG0": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>IMUX_L1": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L12->>SS6BEG2": { + "src_wire": "LVB_L12", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L37": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>BYP_ALT4": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>WL1BEG1": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE2->>IMUX_L14": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>NL1BEG1": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>EE2BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>NN6BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>IMUX_L33": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>WR1BEG_S0": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>IMUX_L7": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>IMUX_L15": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>BYP_ALT7": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>SW6BEG2": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>SS2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>IMUX_L13": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>IMUX_L31": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>BYP_ALT6": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>SW2BEG2": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>EE2BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>EE2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>IMUX_L35": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>BYP_ALT2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>WL1BEG2": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>IMUX_L13": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>BYP_ALT2": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>EE2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>NW6BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>EL1BEG1": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>NW6BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>NR1BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>NE6BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>NW2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>EE2BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>EE4BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>NE2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>WL1BEG1": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L18": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>SE6BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>IMUX_L26": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>SL1BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>NE2BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>IMUX_L36": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>WR1BEG2": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>LV_L18": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "LV_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>NL1BEG2": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>FAN_ALT1": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L5": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>IMUX_L18": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>FAN_ALT4": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>ER1BEG3": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>NR1BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>SW2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH0->>SS6BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>IMUX_L11": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>SR1BEG2": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>IMUX_L38": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>SE2BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>SW6BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>EL1BEG1": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>NR1BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>NN2BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>WR1BEG3": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>EE4BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>NE2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>IMUX_L42": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE2->>IMUX_L30": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>NW6BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>IMUX_L26": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>SE2BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>EE2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>SS6BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>SW6BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>IMUX_L7": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>NE2BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L38": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>NR1BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>SW2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>EE4BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>NR1BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>SS2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>WR1BEG_S0": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>NE6BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT5->>FAN_BOUNCE5": { + "src_wire": "FAN_ALT5", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>SS2BEG0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END0->>NW2BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>NL1BEG_N3": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>SS2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>SS6BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>SS6BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L14": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>SE6BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>FAN_ALT5": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>IMUX_L5": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END_S0_0->>ER1BEG_S0": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>EE4BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>WR1BEG3": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>FAN_ALT0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END0->>NL1BEG_N3": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>FAN_ALT4": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>WR1BEG_S0": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>SW2BEG1": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>NN2BEG3": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>IMUX_L18": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>IMUX_L23": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>EE4BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>IMUX_L33": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>CTRL_L1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>LVB_L0": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>WW2BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>SL1BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>BYP_ALT6": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L19": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>WR1BEG2": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>IMUX_L40": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>SR1BEG1": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>SS6BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>IMUX_L44": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>NL1BEG_N3": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>IMUX_L20": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>IMUX_L37": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>NW2BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>SL1BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>SE2BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>EE2BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>IMUX_L9": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>FAN_ALT2": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>NN2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END0->>NW6BEG0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>NN2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>NN6BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>IMUX_L1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>EE2BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L10": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>EE2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>NR1BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>IMUX_L22": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_2->>FAN_ALT3": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>NW2BEG3": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>IMUX_L37": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>FAN_ALT3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L9": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>EL1BEG_N3": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>BYP_ALT4": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>SL1BEG1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>WW4BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>NN2BEG3": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>WW2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>WW4BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END0->>WW4BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>IMUX_L21": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>BYP_ALT0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>BYP_ALT5": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>IMUX_L21": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>IMUX_L8": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>WR1BEG3": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH0->>NE6BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>IMUX_L12": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>EE4BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT3->>FAN_L3": { + "src_wire": "FAN_ALT3", + "is_pseudo": "0", + "dst_wire": "FAN_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>NN2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>IMUX_L11": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>IMUX_L14": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>FAN_ALT7": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>IMUX_L22": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>SS2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>IMUX_L35": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>SS2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>IMUX_L17": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>SS2BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>IMUX_L39": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>NE2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>SS6BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>SS2BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>IMUX_L10": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>SL1BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT1->>FAN_BOUNCE1": { + "src_wire": "FAN_ALT1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>NE6BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>ER1BEG1": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>NW2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>SW2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>ER1BEG_S0": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>IMUX_L25": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>SE2BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>WL1BEG_N3": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>SE6BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>EE2BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>SW2BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L23": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>SR1BEG3": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>FAN_ALT5": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END_S3_0->>IMUX_L15": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>NE6BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>WW2BEG2": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>NW6BEG1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>EL1BEG0": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>IMUX_L29": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>BYP_ALT7": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_2->>IMUX_L0": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>WW4BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>SL1BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>NE2BEG3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>EE4BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L34": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>IMUX_L26": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>IMUX_L46": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>IMUX_L38": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>WL1BEG1": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>IMUX_L1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>BYP_ALT0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>WR1BEG2": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>BYP_ALT1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>NW6BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>IMUX_L23": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>WL1BEG2": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>NW6BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L18->>NE6BEG3": { + "src_wire": "LV_L18", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>IMUX_L32": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>NL1BEG2": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>BYP_ALT3": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>IMUX_L25": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>IMUX_L3": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>SS2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>SL1BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>SL1BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>WL1BEG1": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>IMUX_L32": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>SS6BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>IMUX_L40": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>SW2BEG3": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>EE2BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>WW4BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L0<<->>LH0": { + "src_wire": "LV_L0", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "0", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>NW2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>CTRL_L1": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>IMUX_L34": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>WW2BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>EE4BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>IMUX_L28": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>WR1BEG3": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>FAN_ALT5": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>NE6BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>WW2BEG1": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>EE2BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>NN6BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>NN2BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>IMUX_L9": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>SR1BEG3": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>IMUX_L7": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>EE4BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>SW2BEG0": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>SW2BEG2": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>WW2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>NN2BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>EE2BEG2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE2->>IMUX_L46": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>NW2BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>SL1BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>NL1BEG1": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L19": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>NW6BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>ER1BEG1": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L0": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>IMUX_L34": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>ER1BEG1": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>NW2BEG1": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>ER1BEG1": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>IMUX_L46": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>IMUX_L28": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>BYP_ALT2": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>SW2BEG0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>IMUX_L0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>NW6BEG3": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>IMUX_L31": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>EL1BEG_N3": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>FAN_ALT2": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L18": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>LVB_L12": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>NL1BEG0": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>BYP_ALT5": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>NE6BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>SS2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>IMUX_L23": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>IMUX_L18": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>SS2BEG1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>IMUX_L13": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>SS6BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>EE2BEG2": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B10_WEST->>CLK_L0": { + "src_wire": "GCLK_L_B10_WEST", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>IMUX_L43": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>SS6BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>BYP_ALT7": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>EE4BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>WR1BEG_S0": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>WW2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L33": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>IMUX_L25": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END0->>NN6BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>IMUX_L27": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>LVB_L12": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>IMUX_L41": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>BYP_ALT1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>WW4BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>ER1BEG3": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L45": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L38": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>FAN_ALT5": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>IMUX_L21": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>SR1BEG3": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>IMUX_L14": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>SS6BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L34": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>WW2BEG0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>SE6BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>IMUX_L39": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>FAN_ALT7": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L0->>NN6BEG2": { + "src_wire": "LVB_L0", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>SE2BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>CTRL_L0": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>IMUX_L33": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>SE6BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>NE2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>WW4BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>IMUX_L13": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>NE2BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>IMUX_L26": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>BYP_ALT3": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>SS2BEG1": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>NW6BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>FAN_ALT5": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>LVB_L0": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>WW4BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>IMUX_L45": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>NE6BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>SS6BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>NW6BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>SE2BEG1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>IMUX_L35": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT7->>BYP_L7": { + "src_wire": "BYP_ALT7", + "is_pseudo": "0", + "dst_wire": "BYP_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>LH0": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END_S0_0->>SW6BEG3": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>SE6BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B3->>GFAN0": { + "src_wire": "GCLK_L_B3", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>CTRL_L0": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>IMUX_L2": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>NW6BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>LV_L18": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "LV_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>NE2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>LV_L18": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "LV_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>IMUX_L40": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>WL1BEG2": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>NN6BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>IMUX_L44": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>WW4BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH12->>NE6BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>IMUX_L2": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B6_WEST->>CLK_L1": { + "src_wire": "GCLK_L_B6_WEST", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>FAN_ALT5": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L17": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>WL1BEG0": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>BYP_ALT2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>BYP_ALT6": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE3->>IMUX_L15": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>WW4BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>WW4BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>EE2BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>IMUX_L46": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>IMUX_L3": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>SE6BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>IMUX_L21": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>EE2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>NR1BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>IMUX_L11": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>SE6BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>SW6BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>SE6BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>SS2BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>IMUX_L3": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>IMUX_L34": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>WW4BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>CTRL_L0": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>SE2BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>IMUX_L6": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>BYP_ALT2": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH0->>NN6BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>IMUX_L36": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L44": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>SW2BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>IMUX_L42": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>NN6BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>WW2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>IMUX_L10": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END_N0_3->>NW6BEG0": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>ER1BEG_S0": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>EL1BEG_N3": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>WW2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B6->>GCLK_L_B6_WEST": { + "src_wire": "GCLK_L_B6", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B6_WEST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>NW6BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>BYP_ALT3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>IMUX_L5": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>SR1BEG2": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>EL1BEG0": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>WL1BEG0": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_3->>IMUX_L25": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>NN2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>NE6BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH6->>NE6BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>IMUX_L30": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>SS6BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>IMUX_L34": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>EL1BEG2": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>EE4BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>ER1BEG2": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>SS6BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>SS2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>IMUX_L39": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>NW6BEG0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>SR1BEG2": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>IMUX_L13": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>WW2BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>SS6BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>IMUX_L29": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>WW2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>WL1BEG0": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>IMUX_L37": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>SW2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>WR1BEG3": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>NE2BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>IMUX_L12": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>FAN_ALT5": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>NL1BEG2": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH0<<->>LH12": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "0", + "can_invert": "0" + }, + "INT_L.WL1END2->>SR1BEG3": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_2->>IMUX_L38": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>NE2BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>NE6BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>SW2BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>NN2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE2->>IMUX_L22": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>EE2BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>BYP_ALT6": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>SS2BEG3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END_N1_3->>NN2BEG0": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>SR1BEG1": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>BYP_ALT4": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>NE6BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>IMUX_L24": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>IMUX_L18": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>SW2BEG1": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>IMUX_L1": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>IMUX_L44": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>IMUX_L20": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>FAN_ALT0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>IMUX_L10": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>IMUX_L39": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L0": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>IMUX_L29": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>BYP_ALT4": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>NW6BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>WW2BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>NN2BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>BYP_ALT7": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L3": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>BYP_ALT7": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B8_WEST->>GFAN0": { + "src_wire": "GCLK_L_B8_WEST", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L43": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>BYP_ALT0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>FAN_ALT5": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L32": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>LH12": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L31": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>IMUX_L19": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L45": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>IMUX_L47": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>SE2BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>WR1BEG3": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>IMUX_L18": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>IMUX_L26": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>FAN_ALT6": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>ER1BEG2": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>WW4BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>NR1BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END_S3_0->>FAN_ALT3": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>ER1BEG1": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>SE6BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L7": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>WR1BEG1": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>IMUX_L33": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>NW6BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>SE2BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>SR1BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>NE2BEG2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>FAN_ALT6": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L46": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>WW4BEG3": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END_N0_3->>NW6BEG0": { + "src_wire": "SS6END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L35": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>EL1BEG1": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>BYP_ALT3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>NE2BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>NN6BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>EL1BEG0": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>EE2BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>WW2BEG0": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>LV_L0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "LV_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>IMUX_L23": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>FAN_ALT3": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L18->>SS6BEG3": { + "src_wire": "LV_L18", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>IMUX_L43": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>WR1BEG2": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>BYP_ALT3": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L42": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>WW4BEG2": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>BYP_ALT0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT3->>FAN_BOUNCE3": { + "src_wire": "FAN_ALT3", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>NR1BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END_N3_3->>IMUX_L40": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>WW4BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L7": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>IMUX_L26": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT4->>FAN_L4": { + "src_wire": "FAN_ALT4", + "is_pseudo": "0", + "dst_wire": "FAN_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>NE2BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>NW6BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>NW2BEG2": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>FAN_ALT0": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L12->>SW6BEG2": { + "src_wire": "LVB_L12", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L0->>EE4BEG0": { + "src_wire": "LV_L0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L25": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>EE4BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>NW2BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>IMUX_L29": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>NE2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>SW2BEG2": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>FAN_ALT6": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>BYP_ALT0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>IMUX_L28": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>IMUX_L8": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>SE6BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>IMUX_L0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>BYP_ALT6": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>IMUX_L36": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>WR1BEG2": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>IMUX_L17": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>WW2BEG2": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>NN2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>SE2BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>IMUX_L7": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>WW2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>EL1BEG2": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>FAN_ALT3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>FAN_ALT6": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>IMUX_L25": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>IMUX_L33": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>SR1BEG2": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>EL1BEG2": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>NN2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>IMUX_L2": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>SW6BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>SE6BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>NW2BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L4": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH12->>SS6BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE3->>IMUX_L39": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>SS2BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>BYP_ALT4": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>IMUX_L44": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>NN2BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>IMUX_L26": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>IMUX_L7": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>NL1BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B11_WEST->>GFAN0": { + "src_wire": "GCLK_L_B11_WEST", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>EE2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>EE2BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END_S0_0->>SW2BEG3": { + "src_wire": "NW6END_S0_0", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L40": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>CTRL_L1": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>LVB_L12": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>SS2BEG0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>ER1BEG2": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>ER1BEG_S0": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L9->>LH12": { + "src_wire": "LV_L9", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L37": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>EE2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>IMUX_L36": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>EE4BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>SE6BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>NN2BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>SW2BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>BYP_ALT7": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>IMUX_L30": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L1": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>IMUX_L47": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>SL1BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>BYP_ALT6": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L18->>LVB_L0": { + "src_wire": "LV_L18", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>IMUX_L43": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT2->>FAN_BOUNCE2": { + "src_wire": "FAN_ALT2", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>FAN_ALT6": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>SL1BEG0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>NW6BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L21": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE3->>IMUX_L23": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>IMUX_L2": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>BYP_ALT3": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>IMUX_L18": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>NR1BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>NN2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>EL1BEG1": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>NL1BEG0": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>BYP_ALT5": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>SW2BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>SS6BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>BYP_ALT7": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>IMUX_L11": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>IMUX_L30": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>EE2BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>SS2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B0->>GFAN1": { + "src_wire": "GCLK_L_B0", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>IMUX_L26": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>WR1BEG_S0": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L9->>WW4BEG1": { + "src_wire": "LV_L9", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>SL1BEG3": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L25": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>IMUX_L23": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>IMUX_L41": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>WW4BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>NW2BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L35": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>EE2BEG3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>NL1BEG_N3": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END_S1_0->>WL1BEG2": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>IMUX_L45": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>IMUX_L40": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>IMUX_L12": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>IMUX_L36": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>NL1BEG0": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L15": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L2": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>SE6BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L46": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>SW2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>EL1BEG0": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>WW2BEG2": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE6->>IMUX_L41": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>IMUX_L34": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B6->>GCLK_L_B6_EAST": { + "src_wire": "GCLK_L_B6", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B6_EAST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>NE2BEG3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>IMUX_L4": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END0->>LV_L0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "LV_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>IMUX_L0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>WL1BEG_N3": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>CTRL_L1": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>EE2BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>NE2BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>IMUX_L14": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>BYP_ALT3": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>FAN_ALT1": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>IMUX_L29": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B8->>GCLK_L_B8_EAST": { + "src_wire": "GCLK_L_B8", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B8_EAST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>IMUX_L1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L8": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>EE4BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>NN2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>WR1BEG_S0": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>NW6BEG3": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>EL1BEG1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>IMUX_L11": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L19": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>SS2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>IMUX_L15": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>IMUX_L38": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>NE2BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>SS6BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>IMUX_L30": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>IMUX_L45": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END_N1_3->>NL1BEG_N3": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>IMUX_L22": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>BYP_ALT5": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>IMUX_L20": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>IMUX_L26": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>BYP_ALT7": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>FAN_ALT4": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END0->>NE2BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>BYP_ALT3": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>NN2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>BYP_ALT7": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>NR1BEG2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>IMUX_L23": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT5->>BYP_BOUNCE5": { + "src_wire": "BYP_ALT5", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>IMUX_L24": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>NN6BEG0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>EE2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>BYP_ALT6": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>NW2BEG1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>IMUX_L29": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT3->>BYP_BOUNCE3": { + "src_wire": "BYP_ALT3", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>NW2BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>NW2BEG1": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>IMUX_L33": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>SW6BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L2": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>IMUX_L40": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L26": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L2": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>SL1BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>WW2BEG1": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>EE4BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>SR1BEG2": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>WR1BEG1": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>FAN_ALT6": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>WL1BEG2": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>BYP_ALT3": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>WW2BEG1": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L24": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>IMUX_L4": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>IMUX_L43": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>NR1BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>NW6BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>FAN_ALT2": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L5": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>EL1BEG1": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>IMUX_L27": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L13": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>WL1BEG2": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>BYP_ALT5": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>SE2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>SW2BEG0": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L4": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>IMUX_L25": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>EL1BEG2": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>IMUX_L35": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>IMUX_L38": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>IMUX_L0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>FAN_ALT3": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>FAN_ALT5": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>IMUX_L28": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>NE2BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>IMUX_L37": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>IMUX_L1": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>IMUX_L14": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>NE2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>SW2BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L44": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>WW2BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>IMUX_L5": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>BYP_ALT6": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>SL1BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>ER1BEG3": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>IMUX_L30": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>IMUX_L5": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END_S1_0->>SR1BEG_S0": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>NR1BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>WW2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END_N3_3->>IMUX_L24": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT1->>BYP_L1": { + "src_wire": "BYP_ALT1", + "is_pseudo": "0", + "dst_wire": "BYP_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>IMUX_L41": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>LH0": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>WR1BEG1": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>IMUX_L31": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>IMUX_L43": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L0->>NW6BEG2": { + "src_wire": "LVB_L0", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>NE2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>IMUX_L9": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>EL1BEG_N3": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>SW2BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>IMUX_L7": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>WW4BEG2": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>NW2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>IMUX_L18": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>SS6BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>IMUX_L47": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>IMUX_L19": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>WL1BEG_N3": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>IMUX_L13": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>SW6BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>IMUX_L8": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L9->>SE6BEG1": { + "src_wire": "LV_L9", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L30": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>NN2BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>BYP_ALT2": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L0": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>IMUX_L43": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>NW6BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>ER1BEG3": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>LH12": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>IMUX_L28": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>NE2BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>WL1BEG0": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>IMUX_L45": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>NW2BEG2": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>IMUX_L0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>EE4BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>IMUX_L27": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>IMUX_L23": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L5": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>NN2BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>WL1BEG2": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>WW4BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>NN2BEG0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>WL1BEG2": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>IMUX_L37": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L14": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>FAN_ALT4": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>SW6BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>FAN_ALT5": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>ER1BEG2": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>FAN_ALT2": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>IMUX_L39": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>NR1BEG1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>LV_L0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "LV_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>WW2BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>NE6BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>EE2BEG1": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>WW2BEG2": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>FAN_ALT2": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>IMUX_L25": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>BYP_ALT6": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>IMUX_L24": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>SS2BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>IMUX_L42": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>BYP_ALT5": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>BYP_ALT3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>NN2BEG2": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>NR1BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>EL1BEG2": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>FAN_ALT4": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>WW4BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>IMUX_L20": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>CLK_L0": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>NN2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>NN2BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>NW6BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>BYP_ALT5": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>EE4BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>SW6BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>FAN_ALT1": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>NR1BEG1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>NW6BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L34": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>IMUX_L13": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L47": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>SL1BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>EE2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>SE2BEG1": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>SR1BEG3": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>WL1BEG0": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>SS2BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>SE2BEG2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>FAN_ALT5": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>CTRL_L1": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L11": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>FAN_ALT2": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>IMUX_L8": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>NE6BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>NL1BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>NW2BEG3": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>IMUX_L3": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END1->>WW4BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>IMUX_L44": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>IMUX_L31": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>SW6BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_2->>IMUX_L30": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>BYP_ALT5": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>SE2BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>IMUX_L32": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>IMUX_L18": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT4->>BYP_L4": { + "src_wire": "BYP_ALT4", + "is_pseudo": "0", + "dst_wire": "BYP_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L4": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>IMUX_L42": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>SR1BEG2": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>SW6BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L36": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L16": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>BYP_ALT3": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>SW2BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>NE6BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>IMUX_L30": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>IMUX_L18": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>FAN_ALT2": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>IMUX_L15": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_2->>BYP_ALT6": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>SE2BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH6->>WW4BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>IMUX_L36": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>EL1BEG_N3": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>SR1BEG3": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>IMUX_L33": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>SE6BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>SS2BEG0": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>SR1BEG3": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>WL1BEG1": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>SW6BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>IMUX_L39": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>SE6BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>NE6BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>LVB_L0": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>NN2BEG0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>FAN_ALT7": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>NW2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>IMUX_L12": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>WL1BEG1": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>LVB_L12": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>IMUX_L2": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>WW2BEG0": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>WW2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>NE6BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>EE4BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END_S1_0->>BYP_ALT7": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>NN6BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>IMUX_L33": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>SL1BEG0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>NN2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>WW4BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>LH12": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>IMUX_L14": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>FAN_ALT7": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>SE6BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>NN6BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>FAN_ALT6": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>SW6BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>SL1BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>IMUX_L11": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>NE2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B4->>CLK_L0": { + "src_wire": "GCLK_L_B4", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>IMUX_L33": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>NR1BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>FAN_ALT3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>SS6BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END0->>WR1BEG1": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>BYP_ALT4": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>EE2BEG0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>NN6BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>IMUX_L7": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>SE2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>CTRL_L1": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L23": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>NW2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>SR1BEG3": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>BYP_ALT1": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>IMUX_L35": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>SS6BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>SS6BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>IMUX_L20": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH12->>NN6BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>BYP_ALT2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>SS6BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>LH0": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>IMUX_L40": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>FAN_ALT4": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>NW2BEG3": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>WR1BEG2": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>EE4BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>FAN_ALT4": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>EE4BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>SR1BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>IMUX_L38": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>WL1BEG2": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>NW2BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>EL1BEG2": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_2->>FAN_ALT0": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>SE2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>NR1BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>NL1BEG1": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>IMUX_L35": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>WL1BEG1": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>NW2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>EE2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>IMUX_L41": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END_N0_3->>NW6BEG0": { + "src_wire": "SS2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>IMUX_L13": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>FAN_ALT2": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>BYP_ALT2": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L33": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>IMUX_L21": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>SS2BEG2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>WL1BEG1": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>IMUX_L6": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>IMUX_L30": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L25": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>NW6BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L10": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE4->>FAN_ALT0": { + "src_wire": "FAN_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>NE6BEG0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>BYP_ALT0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>WL1BEG0": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>SL1BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>NN6BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>EE4BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>IMUX_L34": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>NL1BEG1": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>FAN_ALT3": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>IMUX_L24": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>ER1BEG1": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>IMUX_L39": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>SE6BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L36": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>NE2BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>SW6BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>WL1BEG1": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>SW6BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L36": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>NL1BEG1": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>EE4BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>IMUX_L19": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L26": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>BYP_ALT4": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>SR1BEG_S0": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END_N1_3->>IMUX_L8": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>SE2BEG0": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>NE6BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>WL1BEG0": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>WR1BEG3": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>FAN_ALT0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>NL1BEG2": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>IMUX_L44": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>WW4BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>IMUX_L4": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>NE2BEG1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>SR1BEG2": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>SE6BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>NW2BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>WL1BEG0": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>IMUX_L18": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT0->>BYP_L0": { + "src_wire": "BYP_ALT0", + "is_pseudo": "0", + "dst_wire": "BYP_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>SE2BEG3": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>IMUX_L6": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>NL1BEG1": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>CLK_L1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>NR1BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END1->>SW2BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>IMUX_L4": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>NE2BEG2": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>LVB_L0": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>IMUX_L26": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>BYP_ALT0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>ER1BEG_S0": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>SL1BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>FAN_ALT7": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>SL1BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE6->>BYP_ALT7": { + "src_wire": "BYP_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>NN6BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>FAN_ALT7": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>IMUX_L11": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>IMUX_L40": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>SE6BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>SL1BEG2": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B4->>GFAN1": { + "src_wire": "GCLK_L_B4", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>NN2BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>EE2BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>ER1BEG1": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>IMUX_L14": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>SW2BEG0": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>SE2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>NN2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B2->>GFAN1": { + "src_wire": "GCLK_L_B2", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>IMUX_L12": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>SE6BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>IMUX_L16": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END0->>EE2BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>IMUX_L43": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>IMUX_L34": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>NW2BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>IMUX_L45": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>NR1BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>FAN_ALT0": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>WW2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>FAN_ALT6": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B6_WEST->>GFAN0": { + "src_wire": "GCLK_L_B6_WEST", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L3": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>SL1BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>NE6BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>SL1BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>CLK_L0": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>FAN_ALT0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>ER1BEG3": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>NW2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>NL1BEG1": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>NL1BEG0": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>CTRL_L1": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>IMUX_L42": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>NN6BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>IMUX_L7": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>NW2BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>EE2BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>IMUX_L26": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L12": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>NW2BEG2": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>IMUX_L10": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>IMUX_L4": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>IMUX_L37": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END_S3_0->>BYP_ALT7": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>SW2BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>FAN_ALT4": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>NL1BEG2": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>IMUX_L32": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>WR1BEG1": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>EE2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>WR1BEG_S0": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>FAN_ALT6": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>FAN_ALT1": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>FAN_ALT7": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>LVB_L12": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END_S0_0->>WW2BEG3": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>SR1BEG_S0": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>SE2BEG3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>SS2BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END_N3_3->>IMUX_L32": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>FAN_ALT1": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>WW2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L12": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_2->>IMUX_L6": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>IMUX_L5": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L18->>SW6BEG3": { + "src_wire": "LV_L18", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>SW2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>EL1BEG2": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>IMUX_L11": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>IMUX_L8": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>FAN_ALT3": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>IMUX_L1": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>IMUX_L41": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>IMUX_L8": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH0->>LVB_L0": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>SS6BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>ER1BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>IMUX_L1": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B10_WEST->>GFAN1": { + "src_wire": "GCLK_L_B10_WEST", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE3->>IMUX_L31": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>NL1BEG2": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>BYP_ALT1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L16": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>WW2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>NN6BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>IMUX_L39": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>IMUX_L3": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>WW2BEG3": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>NN6BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>IMUX_L20": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>WL1BEG_N3": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L9->>LH0": { + "src_wire": "LV_L9", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>SW2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>EE4BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>BYP_ALT6": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>NL1BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>WR1BEG2": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>EE2BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_3->>IMUX_L41": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>SW6BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>LV_L0": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "LV_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>IMUX_L8": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>WW2BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>SS6BEG2": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>BYP_ALT4": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L22": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>NL1BEG1": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>FAN_ALT3": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>SS6BEG0": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>FAN_ALT2": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>SW2BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END_N0_3->>WW4BEG0": { + "src_wire": "SW6END_N0_3", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>NW6BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L9->>EE4BEG1": { + "src_wire": "LV_L9", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>EE4BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>IMUX_L21": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>FAN_ALT5": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>BYP_ALT1": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>IMUX_L14": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END_S0_0->>SR1BEG_S0": { + "src_wire": "NW6END_S0_0", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>IMUX_L43": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>EE4BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L16": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>WR1BEG3": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>NN2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>IMUX_L37": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>NE2BEG3": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>SS2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>CTRL_L0": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>NE2BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END_S3_0->>BYP_ALT7": { + "src_wire": "EL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>WL1BEG_N3": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>IMUX_L47": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>IMUX_L35": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L42": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>IMUX_L12": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>IMUX_L7": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>IMUX_L11": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L37": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>BYP_ALT0": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>WW2BEG1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>NL1BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>BYP_ALT1": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>FAN_ALT2": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>EE4BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>NW6BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END2->>IMUX_L27": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>IMUX_L47": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>NE6BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B10_WEST->>GFAN0": { + "src_wire": "GCLK_L_B10_WEST", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L18->>LVB_L12": { + "src_wire": "LV_L18", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>IMUX_L39": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>SS6BEG2": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>SE2BEG0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L34": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>WW4BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE2->>BYP_ALT7": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>WW4BEG3": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>IMUX_L3": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L20": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END2->>IMUX_L36": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>FAN_ALT7": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B8_WEST->>CLK_L1": { + "src_wire": "GCLK_L_B8_WEST", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L10": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>IMUX_L22": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>FAN_ALT6": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>WL1BEG_N3": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>IMUX_L15": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_2->>IMUX_L40": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "IMUX_L40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>EE4BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>NR1BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>ER1BEG1": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>WW2BEG1": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>SW2BEG3": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L18->>NN6BEG3": { + "src_wire": "LV_L18", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>NN2BEG2": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B8_WEST->>GFAN1": { + "src_wire": "GCLK_L_B8_WEST", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH12->>NW6BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>IMUX_L34": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>SS6BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>WL1BEG0": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>IMUX_L1": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>SR1BEG3": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>EE2BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>NN2BEG1": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>SE2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>EL1BEG1": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>IMUX_L16": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B10->>GCLK_L_B10_EAST": { + "src_wire": "GCLK_L_B10", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B10_EAST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END_S1_0->>IMUX_L39": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>NN2BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L46": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>WL1BEG2": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>SR1BEG1": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>IMUX_L27": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>IMUX_L10": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>SE2BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>IMUX_L46": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L18": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_3->>IMUX_L9": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>IMUX_L21": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>BYP_ALT5": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L4": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END_S3_0->>IMUX_L31": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L12": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L39": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L32": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>WW2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH12->>EE4BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>IMUX_L10": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END_N3_3->>FAN_ALT0": { + "src_wire": "ER1END_N3_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>NR1BEG0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END_N0_3->>NW6BEG0": { + "src_wire": "SW6END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>SL1BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>IMUX_L7": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>LH12": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>SW6BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>NR1BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>SE2BEG3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END3->>LVB_L12": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>EE2BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>SS2BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>EL1BEG_N3": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>ER1BEG1": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>WW4BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L35": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>EL1BEG1": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>WL1BEG_N3": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>IMUX_L43": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>SW2BEG1": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>SW6BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>IMUX_L43": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L39": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>SE6BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>FAN_ALT2": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>IMUX_L45": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>BYP_ALT2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END_N0_3->>FAN_ALT0": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>NR1BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>IMUX_L28": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>NN2BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>EE4BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>SR1BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>IMUX_L20": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END0->>EE2BEG0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>SE6BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>SL1BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>IMUX_L38": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>LVB_L12": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>IMUX_L42": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L0->>NW6BEG0": { + "src_wire": "LV_L0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>WL1BEG1": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>WR1BEG1": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>IMUX_L20": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>WL1BEG2": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>SW2BEG1": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>NE6BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>SS2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END_S3_0->>IMUX_L39": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>IMUX_L46": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L39": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>EE2BEG1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>SW6BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>FAN_ALT4": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>IMUX_L31": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END0->>NE2BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>IMUX_L0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L36": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>IMUX_L37": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>ER1BEG2": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>SL1BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>NW6BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>ER1BEG3": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>SR1BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>ER1BEG2": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>FAN_ALT6": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>SW6BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L8": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>SE2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>IMUX_L3": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>SS2BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END0->>EL1BEG_N3": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>ER1BEG2": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>IMUX_L10": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>BYP_ALT5": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>IMUX_L43": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>IMUX_L11": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>SS6BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END3->>SW2BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>WW2BEG1": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>BYP_ALT4": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END_N1_3->>IMUX_L0": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>IMUX_L17": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>SE2BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>NE2BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>WL1BEG1": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>IMUX_L20": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L0->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>IMUX_L21": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>NL1BEG0": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>IMUX_L22": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END2->>BYP_ALT2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>NN6BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L26": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>SS6BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L37": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>BYP_ALT3": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>IMUX_L44": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>ER1BEG_S0": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>NN2BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L28": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>LVB_L12": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>FAN_ALT0": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>IMUX_L25": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>WW2BEG3": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>IMUX_L10": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>BYP_ALT7": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>NW2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END3->>IMUX_L38": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>FAN_ALT7": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>IMUX_L47": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>IMUX_L11": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>SS6BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>EL1BEG0": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>SR1BEG1": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>NN6BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>FAN_ALT7": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>IMUX_L43": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>IMUX_L15": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>FAN_ALT3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>IMUX_L16": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>EE4BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>SR1BEG3": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>SS6BEG1": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>CTRL_L1": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END_S0_0->>SS6BEG3": { + "src_wire": "NW6END_S0_0", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>WR1BEG3": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>SS6BEG2": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>SW6BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>SE6BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>LVB_L0": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>SL1BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>IMUX_L45": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>NN6BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L10": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>FAN_ALT6": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>SE6BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END1->>SW2BEG0": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>NE2BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>IMUX_L42": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>SR1BEG2": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>IMUX_L4": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>IMUX_L32": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>NL1BEG1": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>NE2BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>BYP_ALT6": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>IMUX_L17": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>NL1BEG2": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L41": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>BYP_ALT6": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L14->>IMUX_L12": { + "src_wire": "LOGIC_OUTS_L14", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>NW6BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END0->>IMUX_L32": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>BYP_ALT4": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE6->>FAN_ALT0": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>IMUX_L16": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L47": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>IMUX_L34": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>IMUX_L43": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>EE4BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>NL1BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>WW4BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>NR1BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>ER1BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>IMUX_L6": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>SE6BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>NE6BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END1->>NE6BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>SL1BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>WW4BEG1": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>NE2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>NR1BEG3": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>IMUX_L47": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>EL1BEG2": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>SS6BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>NN2BEG3": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>NN2BEG2": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>IMUX_L2": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>ER1BEG2": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>LH12": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>NR1BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>IMUX_L9": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L27": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END2->>SS6BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>EL1BEG_N3": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>EE2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>WW2BEG0": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>FAN_ALT2": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>IMUX_L12": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>SL1BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END2->>BYP_ALT3": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>IMUX_L2": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_ALT3->>BYP_L3": { + "src_wire": "BYP_ALT3", + "is_pseudo": "0", + "dst_wire": "BYP_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>BYP_ALT4": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GND_WIRE->>GFAN1": { + "src_wire": "GND_WIRE", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>IMUX_L41": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>NW2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>IMUX_L28": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END0->>IMUX_L0": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>IMUX_L25": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>BYP_ALT7": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>IMUX_L34": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>IMUX_L33": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>SS6BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B0->>GFAN0": { + "src_wire": "GCLK_L_B0", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L9": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>WL1BEG0": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END0->>IMUX_L0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>WL1BEG0": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>NL1BEG2": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>BYP_ALT6": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B1->>CLK_L0": { + "src_wire": "GCLK_L_B1", + "is_pseudo": "0", + "dst_wire": "CLK_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>IMUX_L26": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B2->>GFAN0": { + "src_wire": "GCLK_L_B2", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B4->>CLK_L1": { + "src_wire": "GCLK_L_B4", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B7_WEST->>CLK_L1": { + "src_wire": "GCLK_L_B7_WEST", + "is_pseudo": "0", + "dst_wire": "CLK_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>WW2BEG3": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L0->>NN6BEG0": { + "src_wire": "LV_L0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>WW4BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>ER1BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>IMUX_L30": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>IMUX_L35": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END0->>WL1BEG_N3": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>CTRL_L1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>IMUX_L6": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>SE6BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L16": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>NL1BEG1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>WW4BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>WW2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L22->>EE2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>NE6BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE4->>CTRL_L0": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END_S1_0->>SW2BEG3": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE2->>IMUX_L38": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>NN6BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>WW4BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>ER1BEG1": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>SS2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>IMUX_L37": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>IMUX_L36": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>NW2BEG1": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>SE2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>IMUX_L31": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>NR1BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>FAN_ALT2": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>BYP_ALT1": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>NN2BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>NE6BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>NR1BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L9->>IMUX_L42": { + "src_wire": "LOGIC_OUTS_L9", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END3->>ER1BEG_S0": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>IMUX_L46": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L11->>NN6BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>FAN_ALT1": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>SL1BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>IMUX_L26": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>SE2BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END_N0_3->>NW2BEG0": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>IMUX_L23": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>IMUX_L28": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END_N3_3->>FAN_ALT0": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>NW2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>EL1BEG2": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>IMUX_L31": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>FAN_ALT7": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>IMUX_L45": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>WW2BEG2": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>IMUX_L7": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>IMUX_L21": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>NN2BEG1": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN1->>CTRL_L0": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L3": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>WL1BEG1": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>IMUX_L15": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>NL1BEG2": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>WR1BEG_S0": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_6->>IMUX_L47": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>WW2BEG0": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>IMUX_L7": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>SS2BEG2": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>SL1BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END1->>SR1BEG2": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>NN2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>IMUX_L3": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "IMUX_L3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END2->>NR1BEG2": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>WR1BEG2": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L23->>EE2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_2->>IMUX_L8": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END1->>IMUX_L28": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>EL1BEG0": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END3->>ER1BEG_S0": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>FAN_ALT7": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>IMUX_L42": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L20->>EE2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>IMUX_L10": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>IMUX_L18": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_ALT2->>FAN_L2": { + "src_wire": "FAN_ALT2", + "is_pseudo": "0", + "dst_wire": "FAN_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END2->>WR1BEG3": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L37": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END1->>IMUX_L35": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>BYP_ALT7": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>NE6BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>SE6BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH6->>LVB_L12": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH12->>SW6BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>IMUX_L16": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>NR1BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>IMUX_L26": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>BYP_ALT4": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END_S0_0->>WW2BEG3": { + "src_wire": "NW6END_S0_0", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L12->>BYP_ALT0": { + "src_wire": "LOGIC_OUTS_L12", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LV_L18->>SE6BEG3": { + "src_wire": "LV_L18", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END2->>WW2BEG2": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>IMUX_L38": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE2->>IMUX_L32": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>SW2BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>NN2BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>IMUX_L10": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END3->>IMUX_L15": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>LV_L18": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "LV_L18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>IMUX_L4": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>SS2BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END2->>FAN_ALT5": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>NE6BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>EE4BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END0->>SE2BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>EE4BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END0->>SS2BEG0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>EE2BEG1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>NN6BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1BEG_N3->>IMUX_L45": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>NE2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>SE6BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>NN2BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>NW2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END3->>IMUX_L23": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L13": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>IMUX_L2": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L28": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>NE6BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END3->>LH0": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>NN2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END_S0_0->>FAN_ALT3": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END2->>ER1BEG3": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END1->>NE2BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L19->>EE4BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L15->>NN6BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L21->>IMUX_L31": { + "src_wire": "LOGIC_OUTS_L21", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SL1END3->>IMUX_L31": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END1->>SS2BEG1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END3->>FAN_ALT1": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>IMUX_L5": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>SS6BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END3->>LH12": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_2->>IMUX_L16": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>EE2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END2->>SR1BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END1->>IMUX_L19": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>IMUX_L29": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>WL1BEG0": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>NN6BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END3->>LVB_L0": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "LVB_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE2->>IMUX_L0": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END2->>SL1BEG2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>IMUX_L19": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END3->>FAN_ALT1": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE2->>BYP_ALT3": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END1->>IMUX_L34": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>SW2BEG2": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B7->>GCLK_L_B7_WEST": { + "src_wire": "GCLK_L_B7", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B7_WEST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END_S2_0->>IMUX_L39": { + "src_wire": "NN2END_S2_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>SR1BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>IMUX_L25": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LVB_L0<<->>LVB_L12": { + "src_wire": "LVB_L0", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "0", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>SW2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END_N1_3->>IMUX_L16": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LH6->>NW6BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L5->>FAN_ALT2": { + "src_wire": "LOGIC_OUTS_L5", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>NW2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END2->>LVB_L12": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "LVB_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>BYP_ALT4": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END3->>WL1BEG1": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>SE2BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>SE6BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L20": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>FAN_ALT5": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>SR1BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>SR1BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END2->>SR1BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L1": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L43": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW2END1->>SL1BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE3->>FAN_ALT3": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END1->>WL1BEG0": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GCLK_L_B9_WEST->>GFAN0": { + "src_wire": "GCLK_L_B9_WEST", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>NE6BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END1->>WR1BEG2": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>SW6BEG1": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE6END2->>EE4BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE5->>BYP_ALT1": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>NE2BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>NE2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>NN6BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>SW6BEG0": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L1->>FAN_ALT6": { + "src_wire": "LOGIC_OUTS_L1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L29": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>IMUX_L33": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>IMUX_L27": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L13->>IMUX_L19": { + "src_wire": "LOGIC_OUTS_L13", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>IMUX_L43": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>SE6BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>EL1BEG0": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END0->>SL1BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>SW2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>IMUX_L30": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>IMUX_L32": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END_N0_3->>WW4BEG0": { + "src_wire": "SS6END_N0_3", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END3->>SE6BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L8->>IMUX_L33": { + "src_wire": "LOGIC_OUTS_L8", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW6END2->>NW2BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>NE6BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1BEG_S0->>IMUX_L17": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX_L17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END1->>BYP_ALT4": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>WR1BEG3": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END_S0_0->>SS2BEG3": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L22": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L17->>EE2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>NL1BEG0": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>CTRL_L0": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "CTRL_L0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>IMUX_L23": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "IMUX_L23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>IMUX_L22": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END3->>SW2BEG3": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L10->>WL1BEG1": { + "src_wire": "LOGIC_OUTS_L10", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END3->>SS2BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NL1END0->>IMUX_L8": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L7->>IMUX_L22": { + "src_wire": "LOGIC_OUTS_L7", + "is_pseudo": "0", + "dst_wire": "IMUX_L22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WL1END0->>FAN_ALT4": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.ER1END0->>SE2BEG0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>WW4BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END1->>IMUX_L27": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.GFAN0->>IMUX_L10": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX_L10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>BYP_ALT6": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L2->>IMUX_L4": { + "src_wire": "LOGIC_OUTS_L2", + "is_pseudo": "0", + "dst_wire": "IMUX_L4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END2->>IMUX_L20": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SW6END0->>EE4BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END2->>NE2BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L4->>SL1BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END2->>ER1BEG3": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END_N0_3->>WW4BEG0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>SW6BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>NE2BEG1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS6END1->>EE2BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END0->>IMUX_L33": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L45": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END2->>SS2BEG2": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L18->>ER1BEG1": { + "src_wire": "LOGIC_OUTS_L18", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SR1END3->>SR1BEG_S0": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END0->>IMUX_L32": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>NW2BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.VCC_WIRE->>IMUX_L28": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX_L28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>IMUX_L21": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN2END1->>WW2BEG0": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END3->>IMUX_L38": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END1->>IMUX_L9": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EL1END1->>FAN_ALT6": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END0->>IMUX_L16": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>IMUX_L25": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX_L25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L7": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX_L7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L3->>IMUX_L15": { + "src_wire": "LOGIC_OUTS_L3", + "is_pseudo": "0", + "dst_wire": "IMUX_L15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>IMUX_L12": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END3->>NR1BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END2->>EE4BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE2END1->>IMUX_L2": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_7->>FAN_ALT4": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE_N3_6->>BYP_ALT1": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END3->>NE6BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NW2END2->>EL1BEG1": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>IMUX_L12": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SE6END0->>NN6BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NN6END1->>NW2BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END0->>SS6BEG0": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L6->>SL1BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE1->>GFAN1": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW4END2->>NN6BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.LOGIC_OUTS_L16->>NW6BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.BYP_BOUNCE3->>IMUX_L47": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WR1END2->>IMUX_L35": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE1->>CTRL_L1": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE2END3->>SL1BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.SS2END0->>SW2BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.EE4END0->>SW6BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L35": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX_L35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L21": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX_L21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.WW2END1->>NN6BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NE2END1->>IMUX_L19": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_L.NR1END3->>IMUX_L38": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX_L38", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_INT_R.json b/kintex7/tile_type_INT_R.json new file mode 100644 index 0000000..794aede --- /dev/null +++ b/kintex7/tile_type_INT_R.json @@ -0,0 +1,26779 @@ +{ + "tile_type": "INT_R", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "TIEOFF", + "type": "TIEOFF", + "site_pins": { + "HARD0": "GND_WIRE", + "HARD1": "VCC_WIRE" + }, + "x_coord": 0 + } + ], + "wires": [ + "EE4BEG2", + "SW6E2", + "LOGIC_OUTS19", + "WW4END2", + "GND_WIRE", + "WR1BEG_S0", + "FAN_BOUNCE_S3_6", + "EE2A3", + "IMUX25", + "SE6D2", + "EE4END0", + "LOGIC_OUTS9", + "SR1END2", + "SW6A1", + "SS2END2", + "CTRL0", + "IMUX12", + "EE4BEG0", + "GCLK_B5_WEST", + "SS6D0", + "SE6B1", + "WW4C0", + "SR1END3", + "EE4END2", + "IMUX0", + "LOGIC_OUTS22", + "IMUX46", + "SL1END1", + "LV2", + "SL1BEG0", + "MONITOR_P", + "SS6A1", + "FAN6", + "NE6A1", + "NN6END0", + "SE6A3", + "IMUX22", + "BYP0", + "SE2END2", + "SS2BEG1", + "WL1BEG3", + "LOGIC_OUTS12", + "INT_DQS_IOTOPHASER", + "NE6E1", + "SE2BEG3", + "GFAN0", + "WW4B2", + "IMUX29", + "SS6END0", + "EE4B3", + "IMUX17", + "NW6BEG0", + "SE2A3", + "NW2END2", + "SS2BEG0", + "WR1END1", + "NW6E1", + "EE2BEG2", + "SW6C1", + "SE6D0", + "WW2A2", + "NN6C2", + "IMUX36", + "LH1", + "NE6B0", + "GCLK_B5_EAST", + "SW6A3", + "FAN_BOUNCE5", + "IMUX34", + "FAN_BOUNCE7", + "SE6BEG3", + "IMUX21", + "FAN2", + "NL1END_S3_0", + "SS6END1", + "GCLK_B6", + "LH7", + "SS2END_N0_3", + "SW2END_N0_3", + "LH4", + "CLK0", + "EE2BEG0", + "BYP_BOUNCE3", + "GCLK_B7", + "SW6E1", + "EL1END0", + "SS2A1", + "BYP1", + "NN6A1", + "SW2END0", + "SR1BEG_S0", + "SW6END_N0_3", + "LV10", + "SE6B3", + "SE6END1", + "SE6D1", + "LVB2", + "GCLK_B1_EAST", + "GCLK_B1_WEST", + "BYP_BOUNCE_N3_6", + "GCLK_B4_EAST", + "EE4C3", + "NN2BEG0", + "LOGIC_OUTS10", + "WL1BEG1", + "IMUX3", + "NR1BEG1", + "NW6E2", + "SE6C1", + "SE6E1", + "NW6E0", + "SE6END0", + "EL1BEG2", + "LH0", + "WW4B1", + "SE6A2", + "NN2END2", + "FAN_ALT2", + "LOGIC_OUTS7", + "ER1BEG0", + "EE2BEG1", + "IMUX28", + "SW2END3", + "IMUX8", + "BYP_ALT7", + "SE2BEG0", + "NE6D2", + "BYP_ALT1", + "IMUX6", + "EL1END_S3_0", + "SS6END3", + "NN6D1", + "EL1END3", + "NW6C0", + "SS6BEG1", + "SL1END0", + "GCLK_B3_WEST", + "SE2A0", + "LH11", + "NN6D2", + "NW6A0", + "IMUX40", + "IMUX5", + "IMUX39", + "SW2A0", + "WW4B0", + "WW4B3", + "SS2END1", + "IMUX35", + "LV16", + "WW2END1", + "INT_PHASER_TO_IO_OCLK1X_90", + "LOGIC_OUTS0", + "GCLK_B4", + "GCLK_B1", + "SW6A2", + "WW2END_N0_3", + "FAN_ALT6", + "EE4BEG1", + "LVB3", + "NE6C0", + "IMUX41", + "EE4C2", + "BYP6", + "SS6B1", + "BYP_BOUNCE4", + "NW6A2", + "NE6END2", + "WW2BEG1", + "NW6END0", + "SL1BEG3", + "IMUX2", + "IMUX18", + "NW2A1", + "LOGIC_OUTS14", + "NN6D3", + "SE2END0", + "EL1END1", + "NN6A2", + "NN6END3", + "SS6D3", + "NW2END3", + "NR1BEG3", + "NE2BEG1", + "BYP_BOUNCE5", + "SS6E2", + "SE6BEG2", + "NW6END3", + "SE2BEG1", + "NN2END1", + "SW6B2", + "IMUX15", + "LV1", + "FAN4", + "IMUX38", + "SE6A1", + "EE4BEG3", + "WR1BEG0", + "SW6C0", + "SS6C3", + "LOGIC_OUTS8", + "INT_PHASER_TO_IO_ICLK", + "IMUX4", + "SW6BEG0", + "LOGIC_OUTS23", + "SE6A0", + "FAN7", + "SS6D2", + "SW2BEG1", + "NW6C3", + "SE6C3", + "INT_PHASER_TO_IO_ICLKDIV", + "NL1BEG1", + "FAN0", + "FAN_ALT7", + "NN6E3", + "NW2A3", + "NR1BEG0", + "WR1END0", + "LVB5", + "SE6E0", + "SW2END1", + "SE6D3", + "GCLK_B2_WEST", + "SR1BEG1", + "EE2A1", + "NW2BEG0", + "LH5", + "NN6B2", + "NW2END1", + "NN6C0", + "NE6A0", + "SE2BEG2", + "NE6C2", + "NW2A2", + "SS6E0", + "NR1END2", + "SR1BEG3", + "SS2BEG3", + "BYP_ALT5", + "LV0", + "BYP_BOUNCE_N3_2", + "LVB11", + "CTRL1", + "NE2BEG2", + "NW6E3", + "IMUX31", + "SE2A2", + "SW6END1", + "FAN_BOUNCE_S3_4", + "NE6BEG1", + "LV12", + "NW6B2", + "WW2A0", + "WW4BEG3", + "SS6BEG0", + "EE4C0", + "BYP_BOUNCE_N3_7", + "LV7", + "NN6C1", + "WL1END3", + "NN6BEG3", + "IMUX37", + "EE2END0", + "NL1END0", + "BYP_BOUNCE_N3_3", + "SW2END2", + "SS6BEG2", + "NW6D1", + "NE2END0", + "LOGIC_OUTS17", + "EE4END1", + "SS6B2", + "SE6C2", + "NN6B0", + "NN6END2", + "NE2END2", + "FAN_ALT4", + "SS6END2", + "IMUX47", + "BYP2", + "NW6A1", + "SS2END0", + "EL1BEG3", + "FAN_BOUNCE1", + "LOGIC_OUTS4", + "NE2A0", + "SS6B0", + "SS6D1", + "SW6C2", + "FAN_BOUNCE6", + "IMUX13", + "WR1BEG3", + "EE4B1", + "SW2A3", + "NL1END2", + "EE4B2", + "BYP_ALT2", + "FAN_BOUNCE_S3_2", + "GCLK_B2", + "SW6BEG2", + "INT_PHASER_TO_IO_OCLKDIV", + "NN6END1", + "ER1BEG3", + "EE4A3", + "ER1END3", + "NW6D2", + "NW2END_S0_0", + "NN6D0", + "FAN_ALT1", + "IMUX19", + "NR1END3", + "EE4C1", + "NN6BEG1", + "WR1BEG1", + "NE6BEG0", + "NW6A3", + "FAN5", + "LVB9", + "SS2A0", + "SS6E1", + "WW2END2", + "SW6END2", + "EL1BEG0", + "NN2END3", + "SW6E3", + "LV6", + "EE4A2", + "GFAN1", + "SS6C0", + "IMUX24", + "IMUX16", + "SR1END_N3_3", + "NE6B2", + "ER1END2", + "ER1BEG2", + "EE4END3", + "NW6END2", + "EE2END3", + "NR1END0", + "LV14", + "SS6BEG3", + "SL1BEG2", + "EL1BEG1", + "GCLK_B3", + "NN6C3", + "NN6BEG0", + "NW6C1", + "NW6BEG3", + "NE2A3", + "SS2END3", + "FAN_BOUNCE2", + "WW4A3", + "NE6D3", + "SS6C1", + "NE6END3", + "INT_PHASER_TO_IO_OCLK", + "WW2BEG2", + "LVB8", + "NN2A3", + "SS6C2", + "LV18", + "LVB1", + "EL1BEG_N3", + "LH6", + "LH10", + "ER1BEG1", + "LV13", + "NN6A0", + "GCLK_B10", + "GCLK_B11", + "SL1END2", + "NE6C3", + "WW4END0", + "SW6D2", + "WW2A1", + "NW6D3", + "WL1END0", + "NE6D1", + "NE6A2", + "SW6D0", + "IMUX27", + "BYP_ALT3", + "NN2END0", + "NE6E0", + "NE2A1", + "EE4A1", + "NN6E0", + "NE6D0", + "BYP_BOUNCE7", + "NE2A2", + "BYP_BOUNCE6", + "NN6B3", + "EE2A2", + "GCLK_B5", + "LVB0", + "LV5", + "WL1BEG2", + "NN2BEG1", + "LOGIC_OUTS21", + "NE6END1", + "NN6E2", + "SW6END3", + "NW2BEG1", + "WW4C2", + "ER1END_N3_3", + "GCLK_B8", + "WW4BEG2", + "ER1END0", + "LVB7", + "NN6END_S1_0", + "LV9", + "NL1BEG_N3", + "GCLK_B2_EAST", + "WL1END_N1_3", + "SL1END3", + "NE6END0", + "IMUX1", + "WW4C3", + "WW2END3", + "NE6BEG3", + "NN6B1", + "NE2END1", + "LV3", + "LV17", + "SS6E3", + "SE6E3", + "NW6C2", + "BYP7", + "NW6D0", + "MONITOR_N", + "WW2BEG0", + "SW6D1", + "NW6B3", + "BYP5", + "WW2A3", + "FAN_BOUNCE_S3_0", + "IMUX11", + "LH3", + "SE6END3", + "LV15", + "WL1BEG0", + "LOGIC_OUTS20", + "BYP_BOUNCE2", + "NN6E1", + "FAN_ALT0", + "NL1BEG0", + "IMUX33", + "LVB4", + "GCLK_B4_WEST", + "FAN_ALT3", + "WW4END1", + "LOGIC_OUTS5", + "SR1BEG2", + "IMUX9", + "SW6D3", + "SE2END1", + "WW4END3", + "SE6END2", + "SE6C0", + "NW6END1", + "WW4A2", + "SE2A1", + "SW6BEG1", + "IMUX14", + "FAN3", + "NW6BEG1", + "LH2", + "NE6BEG2", + "SS6A0", + "NN2A0", + "SL1BEG1", + "SW2BEG0", + "IMUX32", + "WW4BEG0", + "EL1END2", + "LVB10", + "SR1END1", + "NN6A3", + "LOGIC_OUTS13", + "NW6BEG2", + "LVB12", + "LOGIC_OUTS6", + "WW4END_S0_0", + "EE2A0", + "NW2A0", + "SW6B0", + "BYP_ALT0", + "SS6A3", + "SS2BEG2", + "WW2BEG3", + "SE6BEG0", + "NE6C1", + "LOGIC_OUTS2", + "WL1END1", + "SW2A2", + "NE6A3", + "WR1BEG2", + "LV11", + "SS6B3", + "WL1END2", + "EE4B0", + "IMUX43", + "SW6B1", + "SW6E0", + "SS6A2", + "NE6E3", + "IMUX45", + "FAN_BOUNCE4", + "NE2END3", + "NN2A2", + "IMUX23", + "EE2BEG3", + "IMUX30", + "NE2BEG0", + "SW6END0", + "NW6B1", + "IMUX7", + "CLK1", + "GCLK_B3_EAST", + "SS2A3", + "FAN_BOUNCE3", + "LOGIC_OUTS3", + "SE2END3", + "WW4C1", + "NW6END_S0_0", + "SW2BEG2", + "SS6END_N0_3", + "SW6BEG3", + "FAN_ALT5", + "IMUX20", + "BYP_BOUNCE1", + "BYP_ALT6", + "LH9", + "ER1END1", + "EE2END2", + "NE6B1", + "ER1BEG_S0", + "LOGIC_OUTS18", + "NE2END_S3_0", + "SW2BEG3", + "WW4A0", + "FAN_BOUNCE0", + "WR1END_S1_0", + "WW2END0", + "GCLK_B0_WEST", + "LH8", + "IMUX44", + "NL1END1", + "NW2END0", + "NN2A1", + "GCLK_B0_EAST", + "SW6C3", + "LOGIC_OUTS16", + "WR1END2", + "LH12", + "NL1BEG2", + "NW2BEG3", + "LV4", + "WL1BEG_N3", + "NN2BEG2", + "WW4BEG1", + "NR1END1", + "BYP3", + "LOGIC_OUTS11", + "SE6B0", + "LVB6", + "IMUX42", + "IMUX26", + "EE2END1", + "SW6B3", + "NW2BEG2", + "NR1BEG2", + "NE2BEG3", + "SS2A2", + "BYP_ALT4", + "SE6BEG1", + "LV8", + "NN6BEG2", + "NN2END_S2_0", + "IMUX10", + "SW2A1", + "NW6B0", + "GCLK_B0", + "WR1END3", + "LOGIC_OUTS1", + "VCC_WIRE", + "SE6B2", + "SE6E2", + "LOGIC_OUTS15", + "GCLK_B9", + "NE6E2", + "BYP_BOUNCE0", + "NN2BEG3", + "EE4A0", + "NE6B3", + "WW4A1", + "FAN1", + "SW6A0", + "BYP4" + ], + "pips": { + "INT_R.LOGIC_OUTS2->>NE2BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>WW4BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>IMUX26": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT0->>FAN_BOUNCE0": { + "src_wire": "FAN_ALT0", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>BYP_ALT2": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>NE6BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>WW4BEG3": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX44": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>FAN_ALT5": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>EE2BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>NE2BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>IMUX21": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>IMUX19": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END_N0_3->>WW4BEG0": { + "src_wire": "SW6END_N0_3", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>FAN_ALT3": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>IMUX47": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>WL1BEG1": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_6->>IMUX7": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B0_EAST->>GFAN0": { + "src_wire": "GCLK_B0_EAST", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB0<<->>LVB12": { + "src_wire": "LVB0", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "0", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX40": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>FAN_ALT1": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B4_EAST->>GFAN1": { + "src_wire": "GCLK_B4_EAST", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>IMUX12": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>WW2BEG2": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>WL1BEG2": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX27": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>BYP_ALT7": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>WW2BEG0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>SE2BEG1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE6->>IMUX17": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>IMUX19": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>EE2BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>SW2BEG0": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>SW2BEG2": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>WW2BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>IMUX5": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>IMUX13": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>IMUX36": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>SR1BEG3": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>NW6BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>IMUX9": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>IMUX7": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>IMUX1": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>WW4BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>LVB0": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>WW4BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>IMUX38": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX28": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>WR1BEG3": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>EL1BEG2": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>IMUX24": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>IMUX1": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>WW2BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>SE6BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>IMUX46": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B1_EAST->>CLK0": { + "src_wire": "GCLK_B1_EAST", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>NW2BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>SS6BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>IMUX5": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>LV0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "LV0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>BYP_ALT1": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>IMUX3": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>SW6BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>BYP_ALT4": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>NE6BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>IMUX19": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>NN6BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>IMUX35": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>WR1BEG_S0": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>SR1BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>IMUX28": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>CTRL1": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>FAN_ALT7": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV0->>SW6BEG0": { + "src_wire": "LV0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>EE2BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>EE2BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>SE2BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>FAN_ALT1": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>NE2BEG2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_2->>IMUX24": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>ER1BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>BYP_ALT0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>SW2BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>SS6BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>BYP_ALT5": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>IMUX10": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>ER1BEG2": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>WW2BEG2": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>SE6BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH0->>LVB12": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>NN2BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END0->>NL1BEG_N3": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>SE2BEG1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>SW6BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>IMUX28": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>NW2BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>EE2BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>IMUX35": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>SS6BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX1": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>BYP_ALT5": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>NE2BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>IMUX12": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>NE6BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>SE6BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>NW2BEG3": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_2->>IMUX16": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV18->>SE6BEG3": { + "src_wire": "LV18", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>IMUX4": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>IMUX6": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>EE4BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B5_EAST->>CLK0": { + "src_wire": "GCLK_B5_EAST", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>SS2BEG3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>BYP_ALT1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX19": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>IMUX18": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>IMUX32": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>EE4BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>WW2BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT0->>BYP_BOUNCE0": { + "src_wire": "BYP_ALT0", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>FAN_ALT0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV0->>SS6BEG0": { + "src_wire": "LV0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>ER1BEG3": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>IMUX6": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>IMUX11": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>IMUX40": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>ER1BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END_S3_0->>IMUX7": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>IMUX25": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>NW6BEG2": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>IMUX10": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>IMUX22": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END_S0_0->>SS6BEG3": { + "src_wire": "NW6END_S0_0", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>NR1BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>IMUX42": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>IMUX2": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>SW6BEG3": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>SW6BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>IMUX0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>LVB0": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE2->>IMUX46": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH6->>WW4BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>IMUX39": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END_N1_3->>NL1BEG_N3": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>IMUX33": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>SL1BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>IMUX16": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B8->>CLK0": { + "src_wire": "GCLK_B8", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END_S3_0->>BYP_ALT7": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>WW2BEG0": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_2->>IMUX8": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>NN2BEG0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>NW2BEG3": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>IMUX14": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>SS2BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>IMUX37": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>ER1BEG1": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>ER1BEG3": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>NE6BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>EL1BEG0": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>BYP_ALT1": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>BYP_ALT5": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>IMUX23": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>IMUX41": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>BYP_ALT6": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>NE6BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>BYP_ALT4": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>IMUX39": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>IMUX1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>IMUX4": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>IMUX28": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>IMUX20": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>IMUX19": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>WW2BEG3": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>IMUX39": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB0->>SS6BEG2": { + "src_wire": "LVB0", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>EL1BEG_N3": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>SW6BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>IMUX12": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>WR1BEG2": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE2->>IMUX14": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>IMUX21": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>SE2BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>SW2BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>WW2BEG3": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>IMUX2": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>NR1BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>IMUX20": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END_N0_3->>WW4BEG0": { + "src_wire": "SS6END_N0_3", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>EE4BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>IMUX12": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>NE2BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>IMUX8": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>BYP_ALT2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>IMUX12": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>WW4BEG2": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>IMUX7": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>NN2BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>IMUX27": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>IMUX21": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>IMUX27": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>SE2BEG1": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>NW2BEG2": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>IMUX41": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>IMUX45": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>IMUX6": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>NE2BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>IMUX24": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>NW6BEG1": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH6->>LVB12": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>IMUX11": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END_S3_0->>IMUX47": { + "src_wire": "NE2END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH12->>LVB12": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>FAN_ALT6": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>FAN_ALT0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>IMUX33": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>IMUX21": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>FAN_ALT6": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE3->>IMUX7": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB12->>EE4BEG2": { + "src_wire": "LVB12", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GND_WIRE->>GFAN1": { + "src_wire": "GND_WIRE", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>SE6BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>NN2BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>NN6BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>IMUX9": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>IMUX6": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>ER1BEG3": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>IMUX7": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>SR1BEG_S0": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>NE2BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>EE2BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>ER1BEG_S0": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>NL1BEG1": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>NN6BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>IMUX27": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>IMUX47": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>NR1BEG3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>IMUX17": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>IMUX8": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>SS6BEG2": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>SE6BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>BYP_ALT0": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END_N0_3->>IMUX16": { + "src_wire": "SS2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>NE2BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>NR1BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>EL1BEG1": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>IMUX24": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>BYP_ALT7": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END_S2_0->>BYP_ALT7": { + "src_wire": "NN2END_S2_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>SE2BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>IMUX4": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>BYP_ALT7": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>ER1BEG1": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>CTRL1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>SL1BEG2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>NE6BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>NW2BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>WW4BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>SS6BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>IMUX20": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>BYP_ALT6": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>IMUX19": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX28": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>EE4BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>ER1BEG2": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>BYP_ALT5": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>EL1BEG_N3": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>SR1BEG_S0": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>IMUX15": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>SL1BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>SE6BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END_N3_3->>IMUX32": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>IMUX19": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>NR1BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>SS6BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>IMUX12": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>FAN_ALT2": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>NN2BEG0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>CTRL0": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>NW2BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>IMUX0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX37": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>BYP_ALT7": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>IMUX23": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>IMUX9": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>NW2BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>NN2BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>FAN_ALT3": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B1_EAST->>GFAN0": { + "src_wire": "GCLK_B1_EAST", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B0_EAST->>CLK1": { + "src_wire": "GCLK_B0_EAST", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>SE6BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>NL1BEG2": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>NW6BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>NR1BEG0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>WL1BEG_N3": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>IMUX20": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>WR1BEG3": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>SW6BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>NN2BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>IMUX20": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>FAN_ALT7": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>WL1BEG_N3": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX10": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>ER1BEG1": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_3->>FAN_ALT4": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>WR1BEG1": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>NE2BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>SW6BEG2": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>SL1BEG0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>IMUX12": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>NL1BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>IMUX44": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>FAN_ALT4": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>SE6BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>WR1BEG3": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>FAN_ALT1": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>NL1BEG0": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>IMUX44": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END_N3_3->>IMUX40": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>NN6BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>IMUX15": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>FAN_ALT3": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>BYP_ALT7": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>EE4BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>NN6BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B11->>GFAN0": { + "src_wire": "GCLK_B11", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX13": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>SE6BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>NW6BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>NE6BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>WW4BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>NE2BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>EE2BEG2": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>SR1BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>SE2BEG0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>SL1BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>NW6BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>ER1BEG3": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>NW2BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>SE6BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>SE6BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>EE4BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>IMUX14": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>IMUX10": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>FAN_ALT7": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END_S0_0->>WL1BEG2": { + "src_wire": "NW6END_S0_0", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>IMUX30": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>NN2BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>SE6BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>NW2BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>EL1BEG0": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>SE2BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>SS6BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>IMUX15": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB0->>NW6BEG2": { + "src_wire": "LVB0", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>EL1BEG1": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>IMUX14": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT4->>BYP_BOUNCE4": { + "src_wire": "BYP_ALT4", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END0->>NE6BEG0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>WW2BEG2": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>SW6BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>BYP_ALT4": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>WW4BEG2": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>SW2BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>SW2BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>WL1BEG0": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>SL1BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>IMUX25": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX24": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>ER1BEG1": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>IMUX28": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>SS6BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>NE2BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>WL1BEG_N3": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>ER1BEG2": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>LV18": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "LV18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>SE6BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>IMUX18": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV18->>SS6BEG3": { + "src_wire": "LV18", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>EL1BEG2": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH0->>SW6BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>IMUX26": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>IMUX17": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT3->>BYP_BOUNCE3": { + "src_wire": "BYP_ALT3", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>SS2BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>IMUX22": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>WW4BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>LVB12": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>WL1BEG_N3": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>NR1BEG0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>SW6BEG2": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>SE6BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>IMUX9": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>FAN_ALT7": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>SL1BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>NN2BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>IMUX37": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX25": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>LVB12": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>IMUX22": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>NW6BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX45": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>ER1BEG2": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>IMUX44": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>IMUX20": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>NE2BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>IMUX15": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>FAN_ALT0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>SW6BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>NN6BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT1->>FAN1": { + "src_wire": "FAN_ALT1", + "is_pseudo": "0", + "dst_wire": "FAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>WR1BEG3": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>NN2BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>SE2BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>NE6BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>EE4BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>LVB12": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>SW2BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>SR1BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B9->>GFAN0": { + "src_wire": "GCLK_B9", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>FAN_ALT7": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>CTRL1": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>IMUX29": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>SE2BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>NW2BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>IMUX1": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>IMUX21": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>EE2BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>NW2BEG1": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX20": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX38": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>EE2BEG0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>IMUX33": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>IMUX19": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX3": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>BYP_ALT2": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>WR1BEG3": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>SL1BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>IMUX21": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>CLK0": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>EE2BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>FAN_ALT5": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>IMUX26": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>NE6BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>IMUX3": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>IMUX4": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>EL1BEG0": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>SR1BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>IMUX2": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX26": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>SS6BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>SE2BEG2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>NE2BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>SS2BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>IMUX36": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>FAN_ALT0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>SE6BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>IMUX45": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>EL1BEG2": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>FAN_ALT6": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>NL1BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>BYP_ALT6": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>WL1BEG1": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>IMUX25": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>EE4BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>SR1BEG1": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>IMUX7": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX1": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>WL1BEG1": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>EE2BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>EE4BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>NN6BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>SS2BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>IMUX32": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>IMUX37": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>IMUX11": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>IMUX33": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>IMUX12": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>EE2BEG2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>SW2BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>WW4BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>BYP_ALT5": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B9->>CLK0": { + "src_wire": "GCLK_B9", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>IMUX5": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>NR1BEG3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX15": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX44": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>EE2BEG0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>BYP_ALT4": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>FAN_ALT2": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>SW6BEG0": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>FAN_ALT1": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>EE2BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>FAN_ALT7": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>NN2BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>SL1BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>IMUX23": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>SR1BEG1": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX30": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>NN6BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>NR1BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>NN2BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>NR1BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>EE2BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>SW6BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>EE2BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>SS2BEG1": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>WR1BEG3": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>SR1BEG2": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH0->>NN6BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>BYP_ALT5": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>WR1BEG2": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>BYP_ALT2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>SS6BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>SS2BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>IMUX7": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>GFAN0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>SL1BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>SW6BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B7->>GFAN0": { + "src_wire": "GCLK_B7", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT4->>BYP4": { + "src_wire": "BYP_ALT4", + "is_pseudo": "0", + "dst_wire": "BYP4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>IMUX20": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>BYP_ALT3": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>SR1BEG1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>SE2BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>SR1BEG3": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>NW2BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>IMUX9": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>EL1BEG_N3": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>SS2BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX41": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>IMUX33": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>IMUX8": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END_N0_3->>NW2BEG0": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>EE2BEG3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>BYP_ALT5": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>ER1BEG3": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>NR1BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX43": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>FAN_ALT0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>NW2BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>CTRL0": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>SW6BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>IMUX17": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>BYP_ALT0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>LH12": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV9->>NW6BEG1": { + "src_wire": "LV9", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>NL1BEG2": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>SS2BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>IMUX9": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>LVB12": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>WW2BEG0": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>SW2BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>BYP_ALT1": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>SE2BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>WR1BEG2": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>NE2BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END_S3_0->>IMUX31": { + "src_wire": "NE2END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>SS2BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>SS2BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>NL1BEG1": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>IMUX22": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>SW2BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>IMUX30": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>IMUX28": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE6->>BYP_ALT1": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>NE6BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>IMUX28": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>IMUX3": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>EE4BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>IMUX7": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>FAN_ALT0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>IMUX2": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>IMUX47": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>SE6BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>SW6BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>NW6BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B2_EAST->>GFAN0": { + "src_wire": "GCLK_B2_EAST", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>NW2BEG2": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>EL1BEG2": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>WR1BEG3": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>SS6BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>WR1BEG2": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>NN2BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>WW4BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>IMUX13": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>BYP_ALT3": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>EL1BEG2": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>WR1BEG2": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>WR1BEG_S0": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>IMUX25": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END_S0_0->>WW2BEG3": { + "src_wire": "NW6END_S0_0", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>NW6BEG2": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>WL1BEG2": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX8": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>EE4BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>EE2BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>BYP_ALT7": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>SS2BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>NE2BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>BYP_ALT1": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE3->>IMUX15": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>BYP_ALT1": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>WW4BEG1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX12": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>SS2BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>IMUX41": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>SR1BEG3": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>FAN_ALT2": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>EE4BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX25": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>SW2BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>IMUX22": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>IMUX44": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END_N0_3->>FAN_ALT0": { + "src_wire": "SS2END_N0_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>IMUX1": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>IMUX0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>CLK0": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>WL1BEG2": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>IMUX19": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>FAN_ALT2": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>ER1BEG3": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX32": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>NR1BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX47": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>IMUX46": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>NR1BEG1": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>IMUX17": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>NE6BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B6->>GFAN0": { + "src_wire": "GCLK_B6", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>EE4BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>BYP_ALT4": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>IMUX1": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV18->>WW4BEG3": { + "src_wire": "LV18", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH0->>SS6BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>SE6BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>IMUX43": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B3_EAST->>GFAN0": { + "src_wire": "GCLK_B3_EAST", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>NW2BEG1": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>SR1BEG_S0": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>NE6BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END_N3_3->>IMUX8": { + "src_wire": "ER1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>IMUX32": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END_S0_0->>SR1BEG_S0": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>SE6BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX34": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>IMUX3": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>BYP_ALT4": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>IMUX38": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>WR1BEG2": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>IMUX6": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>SS2BEG2": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>IMUX42": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX20": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>FAN_ALT3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>IMUX31": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>NW6BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_2->>BYP_ALT6": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>SE2BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>NL1BEG2": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT2->>FAN_BOUNCE2": { + "src_wire": "FAN_ALT2", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>EL1BEG_N3": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>NR1BEG1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>IMUX41": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>IMUX26": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>WW2BEG1": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>IMUX8": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX4": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>FAN_ALT1": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>IMUX0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>IMUX1": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>SW2BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>IMUX27": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH6->>LV18": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "LV18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>SW2BEG1": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>SW6BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>FAN_ALT5": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>IMUX7": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>SS2BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>NN6BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>NE6BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>IMUX21": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>SR1BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>BYP_ALT3": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>BYP_ALT2": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>WR1BEG_S0": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>IMUX10": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>FAN_ALT3": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>IMUX37": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>FAN_ALT6": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>IMUX2": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>LVB0": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>IMUX9": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>FAN_ALT7": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>NL1BEG_N3": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>IMUX31": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>IMUX26": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>FAN_ALT3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>FAN_ALT5": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>IMUX26": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>IMUX35": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>IMUX7": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>IMUX1": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>CTRL1": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>NW2BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>NN6BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>WL1BEG2": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B3_EAST->>GFAN1": { + "src_wire": "GCLK_B3_EAST", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>IMUX13": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>IMUX4": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>WW4BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>IMUX42": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>NR1BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>FAN_ALT0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>IMUX7": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>NR1BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>WW4BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>FAN_ALT1": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>IMUX33": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B4_EAST->>GFAN0": { + "src_wire": "GCLK_B4_EAST", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>LVB12": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>IMUX43": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>IMUX41": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>IMUX7": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>BYP_ALT2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>IMUX18": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>IMUX20": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>WR1BEG3": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>ER1BEG1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>SW2BEG2": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>SE2BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>SW2BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>IMUX45": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>SE6BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>SE2BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX6": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>IMUX35": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>WR1BEG_S0": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>BYP_ALT2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>IMUX2": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>IMUX14": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>BYP_ALT6": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV0->>LVB0": { + "src_wire": "LV0", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>FAN_ALT6": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>EE4BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>NW6BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>EL1BEG_N3": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>NR1BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>CTRL1": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>NW2BEG0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX38": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>EE2BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>WW4BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>SW6BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>GFAN1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>BYP_ALT6": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT4->>FAN4": { + "src_wire": "FAN_ALT4", + "is_pseudo": "0", + "dst_wire": "FAN4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B3->>GCLK_B3_EAST": { + "src_wire": "GCLK_B3", + "is_pseudo": "0", + "dst_wire": "GCLK_B3_EAST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>EE4BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>EL1BEG2": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX28": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>NR1BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>BYP_ALT3": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>EE4BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>IMUX31": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>SE2BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>SL1BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>IMUX0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>SS6BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END_N0_3->>IMUX0": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>WW2BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>WW4BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>SE2BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>IMUX25": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX16": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>SE2BEG3": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>SS2BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>IMUX36": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>WR1BEG2": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>SS6BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB12->>WW4BEG2": { + "src_wire": "LVB12", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>SS2BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>SW6BEG2": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>BYP_ALT5": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>IMUX40": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>SE2BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>NW2BEG2": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>EE2BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>FAN_ALT2": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>BYP_ALT0": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>NR1BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX33": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>IMUX25": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END_N1_3->>FAN_ALT0": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>SW2BEG2": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>ER1BEG2": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>WW4BEG1": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>WW2BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>NW2BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>SW6BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>SS2BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>WW2BEG2": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>IMUX1": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>SR1BEG3": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>SS6BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>SE2BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT6->>BYP6": { + "src_wire": "BYP_ALT6", + "is_pseudo": "0", + "dst_wire": "BYP6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>ER1BEG3": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>IMUX13": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>IMUX10": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>BYP_ALT1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX18": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>SW6BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>NN2BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>ER1BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>NE2BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>WW2BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>CTRL0": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>NN6BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>SW6BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>IMUX38": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>IMUX38": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>IMUX40": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>IMUX46": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>EE4BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>WR1BEG2": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>IMUX22": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>SE6BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>NR1BEG3": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>IMUX11": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>NR1BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>LV0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "LV0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>IMUX19": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>IMUX27": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>IMUX32": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>BYP_ALT3": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>IMUX29": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>IMUX33": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>WR1BEG3": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>SL1BEG3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT3->>FAN_BOUNCE3": { + "src_wire": "FAN_ALT3", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>ER1BEG3": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>IMUX34": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>EE2BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>SS6BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END_N0_3->>IMUX8": { + "src_wire": "SS2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>IMUX31": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_2->>IMUX46": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>WW2BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>SS2BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>NW6BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX37": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>NE2BEG2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>WL1BEG1": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>IMUX39": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>EL1BEG_N3": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>FAN_ALT7": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>IMUX35": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>ER1BEG1": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>IMUX32": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>EE2BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>SL1BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>SL1BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END0->>NW6BEG0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>NE2BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>SW2BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>IMUX1": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>IMUX2": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END0->>WR1BEG1": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>NE6BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH6->>LVB0": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>IMUX45": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>FAN_ALT5": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>IMUX7": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>FAN_ALT3": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>EE2BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>IMUX6": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>IMUX2": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>SW6BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT7->>BYP7": { + "src_wire": "BYP_ALT7", + "is_pseudo": "0", + "dst_wire": "BYP7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>WW2BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>IMUX39": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>SR1BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B8->>GFAN1": { + "src_wire": "GCLK_B8", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>NE6BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>BYP_ALT7": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>FAN_ALT1": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>NL1BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT0->>BYP0": { + "src_wire": "BYP_ALT0", + "is_pseudo": "0", + "dst_wire": "BYP0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT6->>FAN_BOUNCE6": { + "src_wire": "FAN_ALT6", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>NN2BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>SL1BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END_N0_3->>NL1BEG_N3": { + "src_wire": "SW6END_N0_3", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>NN6BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>SR1BEG2": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>SL1BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>IMUX16": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>IMUX41": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>SW2BEG3": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>IMUX46": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>IMUX4": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>IMUX45": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B1->>GCLK_B1_EAST": { + "src_wire": "GCLK_B1", + "is_pseudo": "0", + "dst_wire": "GCLK_B1_EAST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>IMUX45": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>SW6BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>IMUX36": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>WL1BEG1": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>IMUX38": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>WL1BEG0": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>EE4BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>IMUX25": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>FAN_ALT4": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>NE2BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>SE2BEG2": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX9": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>IMUX35": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>IMUX42": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>NW2BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>IMUX3": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>IMUX44": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH6->>NE6BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END0->>NE2BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>EE4BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>NR1BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>IMUX27": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>NE2BEG0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>IMUX37": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>FAN_ALT4": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>WW2BEG1": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>ER1BEG2": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>FAN_ALT1": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX3": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>IMUX27": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX35": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>IMUX30": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX13": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>NW2BEG2": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>FAN_ALT7": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>SR1BEG2": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>NL1BEG_N3": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>IMUX36": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX22": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>SS2BEG0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV0->>WW4BEG0": { + "src_wire": "LV0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>NR1BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>WW2BEG2": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>IMUX18": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>IMUX28": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>NR1BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>ER1BEG_S0": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>NR1BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>EE4BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>WW4BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX35": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B9->>GFAN1": { + "src_wire": "GCLK_B9", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END_S0_0->>ER1BEG_S0": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>SS2BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>IMUX22": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX12": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>IMUX26": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>SS2BEG0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>BYP_ALT0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>WW4BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>IMUX24": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>IMUX27": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>SW2BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B4_EAST->>CLK0": { + "src_wire": "GCLK_B4_EAST", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>NW2BEG1": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>IMUX3": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>NN2BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>SR1BEG_S0": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>EE4BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>IMUX1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX13": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>EL1BEG2": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>WW2BEG1": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>SW6BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>SW6BEG0": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>FAN_ALT1": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>WL1BEG0": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>NW2BEG3": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>NE6BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH0->>NW6BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>CTRL0": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>IMUX37": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>NL1BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>IMUX28": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>EE2BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>IMUX3": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>SW6BEG1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>SS6BEG1": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>IMUX20": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>NW2BEG3": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>IMUX46": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>NE6BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>SL1BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>IMUX34": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>IMUX2": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>FAN_ALT6": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>IMUX3": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>EL1BEG2": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>WW4BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>SS6BEG2": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B6->>CLK1": { + "src_wire": "GCLK_B6", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>IMUX3": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>IMUX5": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>NE2BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>IMUX26": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>EE2BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>CTRL0": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT5->>BYP_BOUNCE5": { + "src_wire": "BYP_ALT5", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV18<<->>LH0": { + "src_wire": "LV18", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "0", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>NN6BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>WW2BEG2": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>BYP_ALT5": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>SW6BEG1": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>NW6BEG3": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>IMUX18": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>IMUX33": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>SE2BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>SE6BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>NL1BEG1": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>IMUX7": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>SL1BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>WW2BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>IMUX17": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>SL1BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>WW4BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>IMUX18": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>WW4BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>SL1BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>BYP_ALT0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>WL1BEG0": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>NL1BEG2": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>NL1BEG2": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>EL1BEG0": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>FAN_ALT0": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>EL1BEG1": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>IMUX41": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>FAN_ALT7": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE3->>FAN_ALT3": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END_N3_3->>FAN_ALT0": { + "src_wire": "ER1END_N3_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>EL1BEG0": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>BYP_ALT6": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX43": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>FAN_ALT5": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>NN6BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>FAN_ALT1": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>FAN_ALT3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>NL1BEG1": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END_N1_3->>IMUX0": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>IMUX6": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>SS6BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>IMUX7": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>IMUX34": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_2->>IMUX0": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>IMUX37": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>IMUX2": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>IMUX29": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>EE2BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>EE4BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>EL1BEG1": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>SS2BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>IMUX25": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV0->>NE6BEG0": { + "src_wire": "LV0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>NN6BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>NE6BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>IMUX20": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>CLK1": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>IMUX5": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>SE6BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>BYP_ALT5": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>NL1BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>SW6BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END_S1_0->>IMUX39": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>BYP_ALT3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>IMUX41": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>IMUX9": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>IMUX33": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>EE2BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>NW6BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX46": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>SW6BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>ER1BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>EE2BEG3": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>NL1BEG1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>EE4BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>NL1BEG_N3": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>EE2BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>SS6BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>IMUX8": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>SS6BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX18": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>IMUX35": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>IMUX4": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>SL1BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>IMUX41": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV0<<->>LH12": { + "src_wire": "LV0", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "0", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>NE2BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>IMUX27": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>IMUX34": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>IMUX2": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>FAN_ALT6": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>NL1BEG_N3": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX5": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>SW2BEG2": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>NR1BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>IMUX27": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>SW2BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>NL1BEG1": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>NE2BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>BYP_ALT2": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>IMUX21": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>SW6BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>SL1BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>EE4BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX36": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT6->>FAN6": { + "src_wire": "FAN_ALT6", + "is_pseudo": "0", + "dst_wire": "FAN6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>BYP_ALT2": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>SW6BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>SS6BEG0": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>WL1BEG0": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>NN2BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE2->>IMUX22": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>SW6BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>NW2BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B8->>GFAN0": { + "src_wire": "GCLK_B8", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>SW2BEG3": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>NE6BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>SL1BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>NN2BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>WR1BEG3": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>NN2BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>EE4BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>IMUX0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>NN6BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>WR1BEG_S0": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>SW2BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>EE2BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>IMUX33": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>SS6BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>SE2BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>NE6BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>EE4BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>SE2BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH0->>NE6BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>IMUX24": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>ER1BEG3": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>WL1BEG1": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>EE4BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>NW6BEG1": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>NE6BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>SS6BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>NR1BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>BYP_ALT3": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>IMUX9": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>IMUX32": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>NN6BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>SL1BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>SW6BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>IMUX42": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>SE2BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>SE2BEG1": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>NN2BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>SS2BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>FAN_ALT5": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END_N0_3->>NL1BEG_N3": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B7->>CLK1": { + "src_wire": "GCLK_B7", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>EL1BEG2": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>IMUX21": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>NR1BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>SE6BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>IMUX17": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>LH12": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>IMUX19": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>WW4BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>FAN_ALT5": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>WW2BEG3": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END0->>NE6BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>FAN_ALT2": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>SE6BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>FAN_ALT2": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>IMUX45": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>IMUX36": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>WR1BEG_S0": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>WR1BEG_S0": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>NW2BEG0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>NW2BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>SR1BEG2": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV0->>LVB12": { + "src_wire": "LV0", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END0->>NN6BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>EL1BEG1": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>IMUX5": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>NL1BEG2": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>IMUX39": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>SE6BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>IMUX36": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END_N0_3->>IMUX0": { + "src_wire": "SS2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX0": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>SR1BEG3": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>IMUX2": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>EE4BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>FAN_ALT6": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>IMUX40": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>ER1BEG_S0": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>IMUX3": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>WL1BEG2": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>NR1BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>ER1BEG2": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>BYP_ALT3": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>IMUX11": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>IMUX21": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>ER1BEG1": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>LH0": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>EE4BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>IMUX41": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>IMUX38": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>IMUX19": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>SW6BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>SL1BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>IMUX37": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>NN2BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>EL1BEG2": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>NR1BEG1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>IMUX46": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>IMUX15": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>IMUX42": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>IMUX31": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>IMUX10": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>BYP_ALT5": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>SS2BEG2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT5->>BYP5": { + "src_wire": "BYP_ALT5", + "is_pseudo": "0", + "dst_wire": "BYP5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>IMUX45": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>SW2BEG1": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B6->>CLK0": { + "src_wire": "GCLK_B6", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>NW2BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>WL1BEG0": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>IMUX15": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END_S0_0->>SW2BEG3": { + "src_wire": "NW6END_S0_0", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>IMUX29": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>FAN_ALT3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>SE6BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>NN6BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>WL1BEG1": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>EE4BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>IMUX14": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END_S1_0->>IMUX47": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX47": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>IMUX34": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>IMUX13": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>IMUX0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>IMUX18": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>EE4BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>SR1BEG_S0": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>IMUX31": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END0->>LV18": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "LV18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>SS6BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>IMUX38": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B0_EAST->>GFAN1": { + "src_wire": "GCLK_B0_EAST", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>NE6BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>IMUX33": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX44": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>NN6BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>NN6BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>BYP_ALT2": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>SS6BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>NW6BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>CTRL0": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>SE6BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>CTRL0": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>SR1BEG3": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>NN2BEG1": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>IMUX22": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>SE6BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>IMUX43": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>IMUX27": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>IMUX38": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>SE6BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>NW6BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>SR1BEG1": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>SW2BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>BYP_ALT3": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>BYP_ALT5": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>IMUX10": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>NE6BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>NN6BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>IMUX21": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>IMUX31": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END_N3_3->>IMUX16": { + "src_wire": "ER1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>CTRL1": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>FAN_ALT1": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>BYP_ALT4": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>SE2BEG0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>IMUX24": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END0->>NN2BEG0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>SL1BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>IMUX29": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>IMUX13": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>WL1BEG_N3": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>IMUX13": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>NE2BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>WW2BEG3": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B5_EAST->>GFAN1": { + "src_wire": "GCLK_B5_EAST", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>NE6BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>IMUX12": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END0->>WW4BEG0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>SE2BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>FAN_ALT6": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>WL1BEG2": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>SR1BEG2": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>IMUX28": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>IMUX7": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>WL1BEG1": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>SS2BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>IMUX11": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>NR1BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>CLK1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV18->>LVB0": { + "src_wire": "LV18", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>WR1BEG1": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END_S3_0->>FAN_ALT3": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>FAN_ALT4": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>NL1BEG1": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>IMUX0": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B10->>GFAN1": { + "src_wire": "GCLK_B10", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>EE2BEG3": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH6->>SE6BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>EE2BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>SW2BEG0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX15": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>SS2BEG3": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>IMUX34": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>EL1BEG_N3": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>NW2BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>IMUX32": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>NN6BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>SR1BEG1": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>IMUX45": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>SR1BEG1": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>SR1BEG3": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>SS2BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>WW2BEG2": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>EL1BEG_N3": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE2->>BYP_ALT7": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>BYP_ALT3": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>CTRL0": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>WR1BEG2": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>EE2BEG1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>IMUX27": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>EL1BEG0": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>IMUX16": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>EE2BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>BYP_ALT4": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>SS2BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>IMUX36": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>IMUX33": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH12->>LVB0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>IMUX2": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>IMUX6": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>BYP_ALT6": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>FAN_ALT3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>NW2BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>IMUX29": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>WR1BEG2": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>FAN_ALT6": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B11->>GFAN1": { + "src_wire": "GCLK_B11", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>NR1BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>EE4BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>NW2BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>NW2BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>ER1BEG_S0": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>WW4BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B11->>CLK1": { + "src_wire": "GCLK_B11", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>IMUX34": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>SE2BEG2": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>SS2BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>BYP_ALT4": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>CTRL1": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>IMUX1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>EL1BEG0": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE3->>IMUX39": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B2_EAST->>CLK0": { + "src_wire": "GCLK_B2_EAST", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>NN2BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>BYP_ALT5": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>IMUX44": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX24": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>NE6BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>SW6BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>WL1BEG0": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>IMUX42": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX21": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>FAN_ALT7": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>EE2BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT1->>FAN_BOUNCE1": { + "src_wire": "FAN_ALT1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>IMUX2": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>IMUX14": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX14": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>IMUX32": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>IMUX39": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>IMUX23": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>IMUX37": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>SL1BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>IMUX38": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>NL1BEG0": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>EE2BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>SW6BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>ER1BEG_S0": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>ER1BEG1": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>IMUX44": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>SW2BEG3": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>EE4BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B3_EAST->>CLK0": { + "src_wire": "GCLK_B3_EAST", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>IMUX5": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>FAN_ALT4": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>NN6BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>NR1BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>IMUX36": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>IMUX7": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>LH12": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>EE2BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>WL1BEG1": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>IMUX46": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>BYP_ALT5": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>NE2BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B2_EAST->>GFAN1": { + "src_wire": "GCLK_B2_EAST", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>ER1BEG1": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>IMUX45": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>IMUX3": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>IMUX9": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GND_WIRE->>GFAN0": { + "src_wire": "GND_WIRE", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>EL1BEG1": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>WW2BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END0->>NL1BEG_N3": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>SL1BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>IMUX47": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>SS6BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV9->>SW6BEG1": { + "src_wire": "LV9", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>NE2BEG1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>WL1BEG0": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>IMUX35": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>NW2BEG1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>IMUX13": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>IMUX15": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>WW2BEG1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>EE4BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>NE6BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>IMUX26": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>IMUX45": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>EE2BEG3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>WL1BEG1": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX32": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>SW6BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>SS2BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>CTRL0": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>IMUX43": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>SL1BEG0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>IMUX35": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>WR1BEG_S0": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>SW6BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>IMUX9": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>FAN_ALT6": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>LVB0": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>SW2BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>IMUX34": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>SS6BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB12->>NN6BEG2": { + "src_wire": "LVB12", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>IMUX13": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>NN6BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>IMUX46": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>NL1BEG0": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>EE2BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>IMUX35": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>IMUX43": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>WW4BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>NE2BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE2->>IMUX40": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>NN2BEG2": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>NN2BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>NL1BEG0": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>IMUX47": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>SS2BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>SW2BEG3": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>NW6BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>IMUX28": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>EE2BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>IMUX38": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>EL1BEG0": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>SW6BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>BYP_ALT5": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>IMUX36": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>NE2BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END_S3_0->>IMUX39": { + "src_wire": "NE2END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>WW4BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>WW4BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>WL1BEG0": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>IMUX23": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>NE2BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>WR1BEG3": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END_S0_0->>SS6BEG3": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>IMUX19": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX22": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>FAN_ALT2": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>FAN_ALT4": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT1->>BYP1": { + "src_wire": "BYP_ALT1", + "is_pseudo": "0", + "dst_wire": "BYP1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>NN2BEG3": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>SS6BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>IMUX4": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>IMUX10": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>ER1BEG_S0": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>SE2BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>IMUX11": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>IMUX22": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>EE4BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>IMUX25": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX9": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>BYP_ALT6": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>FAN_ALT5": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>SR1BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX23": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>SS6BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>FAN_ALT1": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_3->>BYP_ALT0": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>IMUX0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>SW2BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>FAN_ALT6": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>SS2BEG1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE2->>FAN_ALT4": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>SR1BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>SS6BEG3": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>CTRL1": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>WR1BEG2": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX41": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>IMUX24": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>BYP_ALT4": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>NW6BEG2": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>NN2BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>SE2BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>IMUX18": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>IMUX43": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>IMUX23": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>SL1BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>NE6BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>NW6BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>CTRL0": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>IMUX27": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>SS6BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>ER1BEG1": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>SS6BEG3": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>NE2BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>IMUX30": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>SS2BEG2": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_6->>IMUX23": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>IMUX14": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>SE6BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>FAN_ALT3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>LV18": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "LV18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>IMUX34": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>NL1BEG0": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>NW2BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>IMUX15": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>EE2BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>LVB12": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>NE6BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END_S0_0->>WL1BEG2": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>SS6BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>NN6BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>FAN_ALT3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>SW2BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>IMUX10": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>SL1BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>NL1BEG1": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>SS2BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>FAN_ALT7": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>IMUX3": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B0->>GCLK_B0_WEST": { + "src_wire": "GCLK_B0", + "is_pseudo": "0", + "dst_wire": "GCLK_B0_WEST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>FAN_ALT7": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>IMUX31": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B10->>CLK0": { + "src_wire": "GCLK_B10", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX5": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>BYP_ALT0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END_S1_0->>WL1BEG2": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX45": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>NN6BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>NW6BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>IMUX41": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>IMUX19": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>IMUX13": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>EE4BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>WW2BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>SS2BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>WR1BEG_S0": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>IMUX38": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>NL1BEG1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>NE2BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>SW6BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>IMUX42": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX29": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>IMUX30": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>BYP_ALT5": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>NW6BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>NN6BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>WW4BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH6->>SS6BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B5_EAST->>GFAN0": { + "src_wire": "GCLK_B5_EAST", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>GFAN0": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>IMUX0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>FAN_ALT6": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>CTRL0": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>SE6BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>NW6BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>BYP_ALT6": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>IMUX8": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_2->>IMUX30": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>SL1BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>IMUX11": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>EE4BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>EL1BEG2": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>IMUX31": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>EE2BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>IMUX35": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>NN2BEG3": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH12->>NW6BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>BYP_ALT7": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>EE2BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>NR1BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV0->>NW6BEG0": { + "src_wire": "LV0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>WW4BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>IMUX24": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>IMUX23": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>WW2BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>CLK1": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>SL1BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>SS6BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>FAN_ALT7": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>EL1BEG1": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH12->>WW4BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>WW2BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>IMUX41": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>SW2BEG1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>NR1BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>SL1BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>SS2BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>IMUX16": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>NW2BEG0": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>LH12": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>EE4BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>ER1BEG1": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>IMUX5": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>BYP_ALT2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>IMUX14": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>WL1BEG2": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX19": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>BYP_ALT7": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>EE2BEG0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>IMUX26": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_6->>IMUX39": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>EL1BEG1": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>EE4BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB0->>NE6BEG2": { + "src_wire": "LVB0", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>IMUX29": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>FAN_ALT4": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>FAN_ALT2": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>EL1BEG0": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>EE2BEG1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>SW6BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>IMUX20": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>SS2BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>SL1BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>IMUX8": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX9": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>SW2BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>SE2BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>BYP_ALT3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>ER1BEG3": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>SE6BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>WL1BEG2": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>GFAN0": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>EE4BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>NR1BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>SE2BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>SE6BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>BYP_ALT1": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>NR1BEG1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>IMUX9": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>LH0": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_3->>IMUX41": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>WL1BEG0": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>NE6BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>NW6BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>IMUX17": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>NR1BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>IMUX40": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>IMUX37": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_2->>FAN_ALT0": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>NN2BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>SL1BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX30": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>IMUX31": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>NN6BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB0->>NN6BEG2": { + "src_wire": "LVB0", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>NW6BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>IMUX22": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>BYP_ALT5": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END_S1_0->>WW2BEG3": { + "src_wire": "NN6END_S1_0", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>LH0": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>CTRL1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>WW4BEG2": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>NN6BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE6->>IMUX41": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>IMUX4": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>NN2BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>IMUX40": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>IMUX36": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>EE4BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>WR1BEG1": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>SW2BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>SL1BEG0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>IMUX10": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV9->>EE4BEG1": { + "src_wire": "LV9", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>IMUX2": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>IMUX5": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>IMUX32": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>IMUX28": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>IMUX17": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>FAN_ALT4": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB12->>NE6BEG2": { + "src_wire": "LVB12", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>FAN_ALT5": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>NN2BEG1": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>BYP_ALT4": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>NW6BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>CTRL1": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>NE2BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>NE6BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>EE4BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>SW6BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>SE6BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>IMUX29": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>IMUX24": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>BYP_ALT4": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>SS2BEG2": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX16": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>EE2BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>SE6BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>SE6BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>IMUX39": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END_N0_3->>NW2BEG0": { + "src_wire": "SW6END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>BYP_ALT4": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>WW4BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>SE6BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT7->>BYP_BOUNCE7": { + "src_wire": "BYP_ALT7", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX23": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>SR1BEG3": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>SS6BEG0": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>WR1BEG3": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>WL1BEG2": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>NE2BEG2": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV18->>NW6BEG3": { + "src_wire": "LV18", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>IMUX18": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX42": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>WW4BEG3": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>NW2BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>NN6BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>NN6BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>BYP_ALT4": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>FAN_ALT2": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>SE2BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>IMUX5": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>EL1BEG0": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>FAN_ALT0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>IMUX18": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>FAN_ALT4": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>IMUX42": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>NN2BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV18->>NN6BEG3": { + "src_wire": "LV18", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B6->>GFAN1": { + "src_wire": "GCLK_B6", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV9->>LH0": { + "src_wire": "LV9", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>IMUX1": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>IMUX17": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>IMUX15": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>SE2BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>IMUX20": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>SS6BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>BYP_ALT0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>IMUX19": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>IMUX38": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>SL1BEG1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>WL1BEG0": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>LVB0": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>SS6BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>BYP_ALT0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>SL1BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>WL1BEG_N3": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>IMUX7": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>WW2BEG1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>IMUX26": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>IMUX19": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>FAN_ALT0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>NE2BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>SL1BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>IMUX32": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX34": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>EE4BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>IMUX44": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>LVB0": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>ER1BEG3": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>SS2BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>IMUX28": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>EE2BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>SS6BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>SS6BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END_S2_0->>IMUX39": { + "src_wire": "NN2END_S2_0", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>IMUX9": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>NN2BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX42": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>WL1BEG2": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>IMUX11": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>WW2BEG0": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>NW6BEG1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>SR1BEG1": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>NN2BEG1": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>SS2BEG0": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>WR1BEG3": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>IMUX32": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>SE2BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>IMUX35": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>WL1BEG_N3": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>SE6BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>SS2BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>SW2BEG1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>IMUX30": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>WL1BEG_N3": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>IMUX43": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>IMUX47": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>WW4BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END_S3_0->>IMUX31": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>IMUX20": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>EL1BEG1": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>NL1BEG0": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>IMUX5": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>IMUX37": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>WR1BEG2": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>NW2BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>SE6BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>BYP_ALT5": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>IMUX26": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>FAN_ALT3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE3->>IMUX23": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>EL1BEG2": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>BYP_ALT6": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX17": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>WW4BEG1": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>IMUX22": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>SL1BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>BYP_ALT2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>EE2BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>WR1BEG_S0": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH6->>NN6BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>NL1BEG2": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>NE2BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX7": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>NE6BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>EE4BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END_S3_0->>BYP_ALT7": { + "src_wire": "EL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>IMUX29": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>NW6BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>IMUX1": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>IMUX40": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH0->>SE6BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>SE6BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>IMUX24": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>NN6BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX23": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>IMUX33": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>IMUX27": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>IMUX25": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>IMUX21": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>IMUX17": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>IMUX39": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>IMUX35": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END0->>EL1BEG_N3": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH12->>SE6BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>SE6BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>NN6BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>LVB12": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>NN6BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>BYP_ALT1": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>SS6BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>IMUX17": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>WR1BEG1": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE6->>IMUX25": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>NN6BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>SW2BEG2": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>EE4BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>FAN_ALT5": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>NW2BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>NE2BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>SW2BEG0": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>NW2BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>IMUX6": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>IMUX8": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>BYP_ALT2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>SR1BEG_S0": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>SE6BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>NL1BEG2": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>SR1BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>WR1BEG_S0": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>SL1BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>NE2BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>IMUX25": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>NN6BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>FAN_ALT2": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>BYP_ALT6": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>IMUX30": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>BYP_ALT6": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>IMUX41": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>IMUX4": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>NW6BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>IMUX43": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>IMUX14": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>EL1BEG1": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>IMUX45": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>NE6BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>IMUX15": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT1->>BYP_BOUNCE1": { + "src_wire": "BYP_ALT1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>IMUX12": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>IMUX13": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END_S1_0->>BYP_ALT7": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>IMUX30": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>IMUX17": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>NE2BEG0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>CTRL1": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX47": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>BYP_ALT1": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>EE2BEG2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>NE2BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>IMUX33": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>NE6BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>SW6BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END_S2_0->>IMUX47": { + "src_wire": "NN2END_S2_0", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>FAN_ALT7": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>FAN_ALT0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE2->>IMUX8": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>EL1BEG2": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>SS6BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>SS2BEG1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>IMUX37": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>SE6BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>WL1BEG_N3": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>WL1BEG1": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE3->>IMUX47": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>NR1BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>BYP_ALT2": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>NL1BEG1": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>IMUX3": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>NN2BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>NN2BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>NW2BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>IMUX24": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>IMUX2": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>NE2BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>NL1BEG2": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>ER1BEG3": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>SR1BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>IMUX41": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>EE4BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>IMUX7": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>IMUX5": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>IMUX4": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>IMUX16": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_2->>IMUX22": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>IMUX9": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>BYP_ALT2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>NE2BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX17": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>IMUX6": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>IMUX30": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>ER1BEG_S0": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>IMUX46": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>EL1BEG1": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX31": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>NW6BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>NL1BEG0": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>ER1BEG2": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>IMUX42": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>IMUX44": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>ER1BEG1": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH0->>LVB0": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>SE2BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>SW2BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>FAN_ALT5": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>NW2BEG3": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>NW2BEG3": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>SW6BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>BYP_ALT7": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>IMUX17": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>IMUX31": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>LH12": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX11": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>NL1BEG0": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>SS6BEG1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_2->>IMUX6": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>WL1BEG2": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>FAN_ALT6": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>NN2BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>BYP_ALT2": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>SS6BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>EE4BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>SE6BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>LH0": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>NE2BEG1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>SE2BEG2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>FAN_ALT0": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>FAN_ALT1": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>SL1BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>BYP_ALT2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>NE2BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>EL1BEG0": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>IMUX21": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>SE6BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>NL1BEG0": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>IMUX16": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>IMUX22": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>SE2BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END_N0_3->>IMUX16": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>WW2BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>SR1BEG3": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>SL1BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END0->>NN2BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>SR1BEG2": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>NW6BEG1": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>IMUX37": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>IMUX5": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>IMUX36": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>IMUX11": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE6->>FAN_ALT0": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>IMUX36": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX27": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>EL1BEG1": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>IMUX36": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE2->>IMUX0": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT3->>BYP3": { + "src_wire": "BYP_ALT3", + "is_pseudo": "0", + "dst_wire": "BYP3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>SW2BEG2": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>NW2BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>NN2BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>EE2BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>IMUX6": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END_S0_0->>WW2BEG3": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>SE2BEG3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>BYP_ALT6": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT3->>FAN3": { + "src_wire": "FAN_ALT3", + "is_pseudo": "0", + "dst_wire": "FAN3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>CTRL0": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX4": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>SR1BEG3": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>NL1BEG1": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>NR1BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>EE2BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>NR1BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>NW2BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>NE2BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END_S3_0->>IMUX23": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>IMUX23": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>NE6BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_2->>IMUX38": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>NL1BEG_N3": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>SW2BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>WL1BEG_N3": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>SE6BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>BYP_ALT5": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>EE4BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>IMUX38": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>IMUX18": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>SL1BEG2": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>NN6BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>WR1BEG2": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>IMUX37": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>BYP_ALT1": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>IMUX27": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>NW2BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>EL1BEG2": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX0": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>IMUX10": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>WW2BEG0": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>IMUX23": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>FAN_ALT2": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>BYP_ALT4": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX6": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>WW4BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT7->>FAN7": { + "src_wire": "FAN_ALT7", + "is_pseudo": "0", + "dst_wire": "FAN7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>IMUX18": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>NE6BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END_S3_0->>IMUX15": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>IMUX10": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>IMUX10": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>IMUX21": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>SS6BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>IMUX12": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>SS2BEG3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>SR1BEG2": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>SR1BEG1": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>IMUX16": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>EE4BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>IMUX42": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>SS2BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>IMUX13": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>BYP_ALT0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B5->>GCLK_B5_EAST": { + "src_wire": "GCLK_B5", + "is_pseudo": "0", + "dst_wire": "GCLK_B5_EAST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>IMUX28": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>BYP_ALT6": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>FAN_ALT1": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>BYP_ALT6": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B0_EAST->>CLK0": { + "src_wire": "GCLK_B0_EAST", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>SW6BEG1": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>NR1BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>IMUX42": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>EE2BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>BYP_ALT4": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>SR1BEG1": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>EE2BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>IMUX1": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END_S3_0->>IMUX47": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>IMUX3": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>SE2BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END_N0_3->>WW4BEG0": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>IMUX12": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>WR1BEG1": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>IMUX39": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>NW2BEG1": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>IMUX40": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>CLK1": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>NE2BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>IMUX16": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>SL1BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>FAN_ALT0": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>NL1BEG0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>IMUX23": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>IMUX2": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>IMUX21": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>NN2BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>FAN_ALT2": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>IMUX15": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>WR1BEG3": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>IMUX25": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>NN6BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>IMUX29": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>WR1BEG3": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>SW6BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>EE4BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>SS6BEG2": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>FAN_ALT3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>IMUX5": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>SR1BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>SE6BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>IMUX26": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>IMUX39": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>NW6BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>NR1BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>WW4BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>NW6BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>NW2BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>BYP_ALT7": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>FAN_ALT4": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END_N3_3->>IMUX16": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>SE6BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>WL1BEG1": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>IMUX32": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>BYP_ALT4": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>IMUX5": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>IMUX30": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>SW2BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>ER1BEG3": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>IMUX6": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>NR1BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE6->>IMUX9": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>IMUX8": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>IMUX7": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>NE2BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>FAN_ALT2": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END_S0_0->>SW6BEG3": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>FAN_ALT2": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END_N1_3->>NN2BEG0": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>NR1BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>SW6BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>NE6BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>NW2BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>SW6BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>FAN_ALT3": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END_S1_0->>IMUX31": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>EE4BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>IMUX46": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>NW2BEG0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>IMUX43": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>NR1BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>BYP_ALT2": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH12->>NE6BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE6->>IMUX33": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>WR1BEG3": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX29": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>IMUX32": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>NE2BEG1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>SS6BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>NE2BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>NN6BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>IMUX31": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>NW6BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>SW6BEG3": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>NN2BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>IMUX39": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX31": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>NL1BEG_N3": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>BYP_ALT0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>IMUX34": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>NE2BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>IMUX32": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>SE6BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>IMUX12": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>NE2BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>WL1BEG0": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>IMUX11": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>IMUX20": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>EL1BEG_N3": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>IMUX34": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>BYP_ALT0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>NR1BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>EL1BEG0": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB0->>SE6BEG2": { + "src_wire": "LVB0", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>IMUX40": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>IMUX28": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>FAN_ALT2": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>IMUX42": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>IMUX43": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>FAN_ALT6": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>NE2BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>WW2BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>WW2BEG3": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>NR1BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>NN2BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>NN2BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>NE2BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>EE4BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>WW4BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>IMUX20": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_6->>IMUX31": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>SS2BEG2": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>IMUX6": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>FAN_ALT7": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>SR1BEG_S0": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>EE4BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>SE2BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>NW6BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END_S1_0->>SR1BEG_S0": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>LV18": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "LV18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>IMUX45": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>SE6BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX40": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>NR1BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>SW2BEG2": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>NR1BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>IMUX33": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>NL1BEG0": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>NR1BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>IMUX3": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>NL1BEG2": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>NL1BEG2": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>IMUX45": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>ER1BEG3": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>IMUX22": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>IMUX2": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>IMUX0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>EE2BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV18->>LVB12": { + "src_wire": "LV18", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>SS2BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>LVB0": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>IMUX33": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>IMUX21": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>IMUX34": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>IMUX33": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END_S3_0->>IMUX47": { + "src_wire": "EL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>IMUX34": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>BYP_ALT2": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>WW2BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>SL1BEG1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>NN6BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>SS2BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>ER1BEG_S0": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>NN6BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>IMUX34": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX45": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>WW2BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>NN2BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>BYP_ALT6": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB12->>NW6BEG2": { + "src_wire": "LVB12", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>SR1BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>WW2BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>SR1BEG3": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>IMUX18": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>IMUX30": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>WW2BEG1": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>SW2BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV0<<->>LH0": { + "src_wire": "LV0", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "0", + "can_invert": "0" + }, + "INT_R.WW2END2->>FAN_ALT1": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>BYP_ALT6": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>NW2BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>IMUX41": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>WW2BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>IMUX21": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>ER1BEG2": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>NN2BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>FAN_ALT7": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>BYP_ALT0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>NE2BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>IMUX34": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>IMUX12": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>SW2BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>IMUX27": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>EE2BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>IMUX37": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>NE6BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>IMUX19": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>NN2BEG2": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>IMUX27": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>EE2BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>LVB12": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>BYP_ALT6": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV18->>SW6BEG3": { + "src_wire": "LV18", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>WW2BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>NE6BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>FAN_ALT7": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>IMUX46": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>BYP_ALT4": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>BYP_ALT4": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>EL1BEG1": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END0->>WW4BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>SE6BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>IMUX8": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>SE2BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>BYP_ALT2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE2->>IMUX16": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>SW6BEG0": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>WW4BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>IMUX12": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>SS2BEG0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END0->>NW6BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>NR1BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>SR1BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>SE2BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>NN6BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>IMUX8": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>SW6BEG1": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>IMUX44": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>IMUX42": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>IMUX22": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>WL1BEG1": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>NE2BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>SE2BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>NE6BEG1": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>IMUX45": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_2->>IMUX32": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>WR1BEG3": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>IMUX5": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>WR1BEG3": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>NR1BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>NN6BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>IMUX45": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>LH0": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>IMUX28": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>CTRL0": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>SR1BEG2": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>NN2BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>SS6BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>BYP_ALT3": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH6->>LV0": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "LV0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END0->>NW2BEG0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>BYP_ALT2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>FAN_ALT0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>WW2BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>EL1BEG_N3": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>SL1BEG0": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>IMUX10": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>BYP_ALT2": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX35": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B1_EAST->>CLK1": { + "src_wire": "GCLK_B1_EAST", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>IMUX35": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>FAN_ALT5": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>FAN_ALT0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>BYP_ALT7": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>IMUX45": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>FAN_ALT2": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>IMUX40": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>WR1BEG2": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>ER1BEG3": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>SW2BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>EL1BEG_N3": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>SW2BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>EE4BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>SW6BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>WL1BEG1": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>IMUX28": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX36": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>IMUX44": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>SE6BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>WW2BEG0": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>SW2BEG1": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>WL1BEG0": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>ER1BEG2": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT5->>FAN5": { + "src_wire": "FAN_ALT5", + "is_pseudo": "0", + "dst_wire": "FAN5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>NE2BEG1": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>IMUX27": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>IMUX12": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>SW6BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>BYP_ALT4": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B1_EAST->>GFAN1": { + "src_wire": "GCLK_B1_EAST", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>WW4BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>NN6BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>IMUX3": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>SE6BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>WR1BEG1": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>LVB0": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B11->>CLK0": { + "src_wire": "GCLK_B11", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>BYP_ALT4": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>LV18": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "LV18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>IMUX4": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>IMUX29": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>IMUX15": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>IMUX43": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>SS6BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>LH0": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>IMUX6": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>SS2BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV9->>SS6BEG1": { + "src_wire": "LV9", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>NW6BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>FAN_ALT1": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>WW2BEG0": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>SE2BEG2": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>WW2BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>WW4BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>SS2BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>WW2BEG0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>SW6BEG0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>NW6BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>SS6BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>SE6BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX1": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>IMUX29": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END_S1_0->>WW2BEG3": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>IMUX16": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END_N3_3->>IMUX8": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>IMUX38": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>NW2BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END_S3_0->>IMUX31": { + "src_wire": "EL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>IMUX29": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END0->>WR1BEG1": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END0->>LV18": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "LV18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>WL1BEG0": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_6->>BYP_ALT7": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>SW6BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>WR1BEG_S0": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>SS6BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB0->>EE4BEG2": { + "src_wire": "LVB0", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END_N0_3->>NW6BEG0": { + "src_wire": "SS6END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>NR1BEG2": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>NR1BEG0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>SW6BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>IMUX42": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>EE4BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>WR1BEG1": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>IMUX19": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>SE2BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>WW4BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH0<<->>LH12": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "0", + "can_invert": "0" + }, + "INT_R.SE2END2->>SW2BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>IMUX11": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>FAN_ALT7": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>EL1BEG1": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END_S2_0->>IMUX31": { + "src_wire": "NN2END_S2_0", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>ER1BEG2": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>WL1BEG2": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>NW2BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>EE4BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>IMUX8": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>SE2BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>IMUX37": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>FAN_ALT5": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX46": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>SW2BEG1": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>NR1BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>SR1BEG2": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>WW4BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX11": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>SS2BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>IMUX44": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>NN6BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>SS6BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX38": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>IMUX13": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX0": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>WR1BEG3": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>IMUX23": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>IMUX16": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>NE2BEG3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>WR1BEG1": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>IMUX13": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>ER1BEG3": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>IMUX27": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>SE2BEG3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH12->>NN6BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>FAN_ALT2": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>BYP_ALT5": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>FAN_ALT5": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>SW2BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>IMUX29": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>IMUX11": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>IMUX19": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>NW6BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>IMUX36": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>ER1BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>NW6BEG3": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>EE2BEG1": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB0->>SW6BEG2": { + "src_wire": "LVB0", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>IMUX33": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>NW6BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>IMUX28": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>NW6BEG2": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV9->>NE6BEG1": { + "src_wire": "LV9", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>IMUX42": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>IMUX40": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>IMUX37": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>IMUX40": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>LH12": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>LH0": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT2->>BYP_BOUNCE2": { + "src_wire": "BYP_ALT2", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>IMUX30": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>SL1BEG1": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>SS2BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END_N3_3->>FAN_ALT0": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT0->>FAN0": { + "src_wire": "FAN_ALT0", + "is_pseudo": "0", + "dst_wire": "FAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>IMUX14": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>LH12": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>FAN_ALT6": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>EL1BEG1": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>EE2BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>IMUX13": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>IMUX16": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>IMUX13": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>IMUX6": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>FAN_ALT4": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>IMUX1": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE2->>IMUX38": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>EE4BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>NE6BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>FAN_ALT4": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>IMUX22": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>WW2BEG2": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>NN6BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>WW4BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>IMUX34": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>NN6BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>NN2BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>FAN_ALT3": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>IMUX28": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>SE6BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>BYP_ALT6": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>IMUX37": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>IMUX5": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>IMUX45": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>FAN_ALT0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>SW2BEG3": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>BYP_ALT5": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>SW2BEG0": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>SS6BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX26": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>WW4BEG2": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>WW4BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>IMUX20": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>SW6BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>SW2BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>IMUX43": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX2": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>NN6BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>BYP_ALT7": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>SS6BEG0": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>EE4BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>IMUX6": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>SW6BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>SR1BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>IMUX42": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>IMUX3": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX39": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>WW2BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>IMUX6": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>CTRL1": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>WW2BEG2": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>SW6BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>IMUX25": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>SS6BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>SE2BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>NL1BEG1": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>NR1BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>SW2BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>NL1BEG0": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX39": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>FAN_ALT4": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>NR1BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX4": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>ER1BEG2": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>NN2BEG1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>IMUX26": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>WW2BEG0": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>FAN_ALT6": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>IMUX9": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>EE4BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>WW2BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>IMUX40": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END_S3_0->>BYP_ALT7": { + "src_wire": "NE2END_S3_0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>EL1BEG2": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>NN6BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>BYP_ALT1": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>SE2BEG3": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>SW2BEG0": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>SW6BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>FAN_ALT0": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>IMUX23": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>IMUX14": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>IMUX11": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>NL1BEG1": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>IMUX46": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>WL1BEG_N3": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>IMUX33": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>NN6BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>IMUX18": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV9->>WW4BEG1": { + "src_wire": "LV9", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>WL1BEG_N3": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>SL1BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_3->>IMUX17": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>IMUX47": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>NE6BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>FAN_ALT3": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>SL1BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>FAN_ALT6": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>IMUX16": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>SL1BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>SS2BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B8->>CLK1": { + "src_wire": "GCLK_B8", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>FAN_ALT5": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>IMUX26": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_3->>IMUX1": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>LVB0": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>SS6BEG0": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>SW2BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>IMUX43": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>IMUX12": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>SL1BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT7->>FAN_BOUNCE7": { + "src_wire": "FAN_ALT7", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>NE6BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>FAN_ALT1": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>NN6BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>IMUX15": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX40": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>NR1BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>WR1BEG2": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>NN2BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>WW4BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>BYP_ALT3": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>WR1BEG2": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>BYP_ALT0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>WW2BEG1": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH12->>SS6BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "SS6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>EE4BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>NE6BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>BYP_ALT5": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>IMUX4": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>EL1BEG2": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>NE2BEG3": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>IMUX25": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>IMUX18": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>IMUX11": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>NN2BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>NN6BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>NN2BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>IMUX34": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>NR1BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH6->>EE4BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>NN2BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>SW6BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>SE6BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>SW2BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>BYP_ALT4": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>EL1BEG1": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>EE2BEG1": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>EE4BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>NN2BEG3": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>FAN_ALT4": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END_N3_3->>IMUX0": { + "src_wire": "ER1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>LVB0": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>IMUX42": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>IMUX40": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>NN2BEG2": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE3->>BYP_ALT6": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>NR1BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>WL1BEG0": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>IMUX4": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_2->>IMUX14": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB12->>SE6BEG2": { + "src_wire": "LVB12", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>WW2BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>IMUX0": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>BYP_ALT4": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>BYP_ALT6": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END_N1_3->>WR1BEG1": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE2->>FAN_ALT1": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX39": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>IMUX41": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV0<<->>LV18": { + "src_wire": "LV0", + "is_pseudo": "0", + "dst_wire": "LV18", + "is_directional": "0", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>NW2BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>IMUX3": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>SE6BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>LH0": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "LH0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>SR1BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>WW4BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>IMUX11": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX30": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>NW6BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>SL1BEG3": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>SL1BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>NW6BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>IMUX15": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>BYP_ALT0": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>SE2BEG0": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>FAN_ALT3": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>NW2BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>NW2BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>NN2BEG2": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>SR1BEG_S0": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>BYP_ALT0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>NN2BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>WW2BEG2": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>BYP_ALT1": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>SR1BEG1": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>IMUX18": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>IMUX12": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>IMUX1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>CTRL1": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>IMUX40": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>NN2BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>NN6BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>IMUX31": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>IMUX41": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>FAN_ALT7": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>SW2BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>NE6BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>SS2BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>IMUX42": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END_N0_3->>NW6BEG0": { + "src_wire": "SS2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>NW6BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>NL1BEG_N3": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX14": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>WW2BEG1": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>IMUX30": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>IMUX45": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>EE4BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>NN2BEG3": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>IMUX23": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>WL1BEG1": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>SS2BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>NN2BEG0": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>SE2BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>ER1BEG2": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>SR1BEG2": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>LVB12": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>ER1BEG1": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>IMUX29": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>EE2BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>IMUX19": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>NL1BEG_N3": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>LV0": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "LV0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>IMUX5": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>IMUX13": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH6->>SW6BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "SW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>IMUX3": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>IMUX11": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>IMUX44": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>SS2BEG3": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>SW6BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>EL1BEG1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>NW6BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB12->>SS6BEG2": { + "src_wire": "LVB12", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>NE2BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>IMUX47": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>IMUX36": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>SS2BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>IMUX41": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>IMUX35": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>LV0": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "LV0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>IMUX43": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>WW2BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>SL1BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>SE2BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>ER1BEG1": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END_N1_3->>IMUX8": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>WW2BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>NE6BEG0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX5": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>SS2BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX10": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>NN2BEG0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>IMUX29": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>IMUX10": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>FAN_ALT1": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>IMUX47": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>NE2BEG3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>SL1BEG3": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>SL1BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>IMUX38": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>NL1BEG1": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>IMUX28": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>WL1BEG1": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>WW4BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>SR1BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>IMUX4": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>CTRL0": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>FAN_ALT6": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B2->>GCLK_B2_WEST": { + "src_wire": "GCLK_B2", + "is_pseudo": "0", + "dst_wire": "GCLK_B2_WEST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>IMUX5": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>IMUX17": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B2_EAST->>CLK1": { + "src_wire": "GCLK_B2_EAST", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>WW4BEG3": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>IMUX37": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>FAN_ALT7": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>WR1BEG1": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX6": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>IMUX11": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>NN6BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>IMUX22": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>NE2BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>FAN_ALT5": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>BYP_ALT6": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>IMUX36": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>SE6BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>BYP_ALT3": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>SW6BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>SR1BEG2": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>FAN_ALT1": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>IMUX4": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>NL1BEG0": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>NN6BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>SR1BEG2": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>NW2BEG1": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>SW2BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>IMUX36": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX33": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX46": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B3->>GCLK_B3_WEST": { + "src_wire": "GCLK_B3", + "is_pseudo": "0", + "dst_wire": "GCLK_B3_WEST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END0->>NN6BEG0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>IMUX26": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>IMUX5": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>SL1BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>BYP_ALT4": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>EE2BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>SE2BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>NL1BEG1": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>ER1BEG2": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>NE2BEG0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX26": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>IMUX20": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>IMUX32": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>NN2BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>IMUX26": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>NE6BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>WW2BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>SW2BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>NE2BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>CLK0": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>NE6BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>IMUX32": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>NL1BEG_N3": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>SS2BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>SE6BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>IMUX24": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>NR1BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>IMUX43": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>IMUX2": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>FAN_ALT4": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>SE2BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>WW4BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>SR1BEG_S0": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>IMUX0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE2->>IMUX32": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>NE6BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>NE6BEG3": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>NE2BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>IMUX44": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>WR1BEG1": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>WL1BEG2": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>BYP_ALT1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>IMUX30": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END0->>LV0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "LV0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE2->>BYP_ALT0": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>SW6BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>NW6BEG1": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>NL1BEG1": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>NW6BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>BYP_ALT7": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>SE6BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END3->>NL1BEG2": { + "src_wire": "NW6END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>EE2BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>IMUX0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>IMUX13": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>IMUX32": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>SS2BEG0": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>FAN_ALT4": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>NR1BEG2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>SE6BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>NW2BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B5->>GCLK_B5_WEST": { + "src_wire": "GCLK_B5", + "is_pseudo": "0", + "dst_wire": "GCLK_B5_WEST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>NW6BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX27": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>NE2BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>IMUX38": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>IMUX10": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX7": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>IMUX39": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>WW2BEG1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>EE2BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>SS6BEG3": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>LVB0": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>IMUX14": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>BYP_ALT2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX21": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>EL1BEG2": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>SL1BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>IMUX43": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>IMUX38": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>SR1BEG1": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>WW4BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX43": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>WL1BEG2": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>NE6BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV0->>EE4BEG0": { + "src_wire": "LV0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX24": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>IMUX38": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B1->>GCLK_B1_WEST": { + "src_wire": "GCLK_B1", + "is_pseudo": "0", + "dst_wire": "GCLK_B1_WEST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B5_EAST->>CLK1": { + "src_wire": "GCLK_B5_EAST", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>EE4BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>IMUX39": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>SR1BEG1": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>LV18": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "LV18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>NR1BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>IMUX32": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>IMUX24": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>EE2BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>NN6BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>NR1BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END_S1_0->>SW2BEG3": { + "src_wire": "WR1END_S1_0", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>IMUX9": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>WL1BEG0": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>EE2BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>FAN_ALT5": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>WW4BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>FAN_ALT4": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>ER1BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH6->>NW6BEG1": { + "src_wire": "LH6", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>FAN_ALT5": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>EL1BEG0": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>FAN_ALT4": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>NN6BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>IMUX24": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>IMUX44": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>NW6BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>FAN_ALT4": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX33": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>IMUX23": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>IMUX18": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>ER1BEG1": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>FAN_ALT4": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>NN6BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>IMUX26": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>IMUX17": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>FAN_ALT1": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>FAN_ALT6": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>NL1BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>NE2BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>BYP_ALT5": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>IMUX47": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>ER1BEG2": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>FAN_ALT6": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_3->>IMUX33": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>NE6BEG2": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>NL1BEG2": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>WW2BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>SE2BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>LV0": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "LV0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>BYP_ALT1": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>ER1BEG_S0": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>NE6BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_2->>FAN_ALT3": { + "src_wire": "FAN_BOUNCE_S3_2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>IMUX12": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>IMUX22": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>BYP_ALT1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>SE6BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>SW2BEG2": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>SE2BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>EL1BEG1": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>IMUX9": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>WW4BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>EE2BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>NW6BEG3": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>NN6BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>WR1BEG_S0": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>IMUX9": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>SE2BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>IMUX19": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>EE2BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>SS2BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH12->>SW6BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>SW6BEG2": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>NL1BEG0": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>SS2BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END_S0_0->>SW6BEG3": { + "src_wire": "NW6END_S0_0", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>SS2BEG1": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>EL1BEG0": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>IMUX4": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>NL1BEG0": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>SE2BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>BYP_ALT0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>EE2BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>FAN_ALT5": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>IMUX16": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>NE6BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>EE2BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>IMUX23": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>NE6BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>BYP_ALT1": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>WR1BEG2": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>IMUX24": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>NR1BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>NE2BEG3": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>BYP_ALT3": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>IMUX13": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>NW2BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>NN2BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>BYP_ALT5": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>SW2BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>IMUX17": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>SR1BEG2": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>SE2BEG0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>IMUX10": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT6->>BYP_BOUNCE6": { + "src_wire": "BYP_ALT6", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>WW4BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>NN2BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>EL1BEG1": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>NW2BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>SL1BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV18->>EE4BEG3": { + "src_wire": "LV18", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>SS6BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>IMUX16": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE2->>BYP_ALT3": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>IMUX21": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>WW4BEG0": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>NN2BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>BYP_ALT1": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>NW2BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>WL1BEG2": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>EL1BEG2": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>FAN_ALT7": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>SE6BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>LVB12": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>SL1BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>CTRL0": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>EE4BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>NE2BEG3": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>BYP_ALT1": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>NN6BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX18": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>WW4BEG1": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>FAN_ALT1": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>IMUX17": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>BYP_ALT5": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B0->>GCLK_B0_EAST": { + "src_wire": "GCLK_B0", + "is_pseudo": "0", + "dst_wire": "GCLK_B0_EAST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>SW2BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE4->>FAN_ALT0": { + "src_wire": "FAN_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>BYP_ALT1": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>FAN_ALT6": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>BYP_ALT3": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>BYP_ALT1": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>IMUX31": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>NR1BEG2": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>EE4BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>NE6BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>IMUX37": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE2->>IMUX30": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX20": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>IMUX34": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>NE6BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>LV0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "LV0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B7->>CLK0": { + "src_wire": "GCLK_B7", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>IMUX10": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B7->>GFAN1": { + "src_wire": "GCLK_B7", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>IMUX19": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>NE6BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>NW6BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>IMUX26": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>IMUX10": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>IMUX24": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>SE2BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>BYP_ALT6": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>EL1BEG0": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>NR1BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>FAN_ALT5": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>NR1BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>WW4BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>NE2BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>WW4BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE2->>IMUX6": { + "src_wire": "BYP_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>NW2BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>IMUX28": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>SS6BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>SS6BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>IMUX28": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>NW2BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>SS6BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>SS6BEG1": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>NN6BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B10->>CLK1": { + "src_wire": "GCLK_B10", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>SW2BEG1": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>IMUX5": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END_N3_3->>BYP_ALT0": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>EL1BEG0": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>IMUX20": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>IMUX30": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>CTRL1": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>WL1BEG1": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>BYP_ALT1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>IMUX45": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>IMUX7": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>IMUX25": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX15": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>NR1BEG2": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>IMUX35": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>IMUX46": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>IMUX15": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>WL1BEG_N3": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>SE6BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>FAN_ALT2": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>WR1BEG3": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "WR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>SE6BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>EL1BEG2": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>WL1BEG1": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>IMUX15": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>EE2BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>IMUX4": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_ALT2->>BYP2": { + "src_wire": "BYP_ALT2", + "is_pseudo": "0", + "dst_wire": "BYP2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>SL1BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>IMUX35": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>IMUX35": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>IMUX3": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>SS2BEG1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>BYP_ALT3": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>SE2BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>EE4BEG0": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>WW4BEG3": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B10->>GFAN0": { + "src_wire": "GCLK_B10", + "is_pseudo": "0", + "dst_wire": "GFAN0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>IMUX30": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX16": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>NE2BEG2": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX2": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>IMUX14": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>IMUX15": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B4->>GCLK_B4_EAST": { + "src_wire": "GCLK_B4", + "is_pseudo": "0", + "dst_wire": "GCLK_B4_EAST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>NW6BEG3": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>IMUX4": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>NW2BEG2": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>IMUX21": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>NE2BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>CTRL0": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "CTRL0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>SE6BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV9->>LH12": { + "src_wire": "LV9", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>WW2BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>EE4BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "EE4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END0->>LV0": { + "src_wire": "WW4END0", + "is_pseudo": "0", + "dst_wire": "LV0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>EL1BEG0": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END_N0_3->>NW6BEG0": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>IMUX34": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>IMUX43": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>NN6BEG0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>BYP_ALT7": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>WW2BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>SW6BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>IMUX35": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>IMUX8": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX25": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>IMUX26": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>IMUX29": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>NE2BEG0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>WR1BEG1": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>EL1BEG_N3": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>NE6BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>BYP_ALT2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>SW2BEG1": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV0->>NN6BEG0": { + "src_wire": "LV0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>IMUX25": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>SS2BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>IMUX14": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>IMUX20": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>NR1BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>IMUX44": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>WW4BEG0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>IMUX46": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>IMUX27": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>IMUX30": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>IMUX36": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>SR1BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>IMUX18": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>BYP_ALT0": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>WW4BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>EE2BEG0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>IMUX13": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>IMUX34": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>WW2BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>EL1BEG_N3": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>NW6BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>FAN_ALT2": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>FAN_ALT6": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>SW2BEG0": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>IMUX32": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>SE2BEG3": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV0->>SE6BEG0": { + "src_wire": "LV0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE6->>IMUX1": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>IMUX29": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>FAN_ALT7": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END2->>IMUX44": { + "src_wire": "NR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>SR1BEG3": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>IMUX18": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END_S0_0->>SS2BEG3": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>BYP_ALT6": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>NN2BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>SR1BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>SR1BEG3": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>EE2BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>WR1BEG1": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>EE4BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX41": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>WW2BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>IMUX44": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>NR1BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>FAN_ALT1": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>NW2BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>NN6BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>IMUX25": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>SL1BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX12": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>IMUX11": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>NN6BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NN6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>NW2BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>SW2BEG0": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>SS2BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END_N1_3->>IMUX16": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV18<<->>LH12": { + "src_wire": "LV18", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "0", + "can_invert": "0" + }, + "INT_R.EE4END2->>NR1BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>IMUX10": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>IMUX43": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>IMUX14": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>SE2BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>SL1BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END3->>LVB12": { + "src_wire": "NN6END3", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END0->>NW2BEG0": { + "src_wire": "NW6END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX31": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>SE2BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>FAN_ALT7": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>FAN_ALT6": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>NE6BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>NW6BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>IMUX25": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV9->>SE6BEG1": { + "src_wire": "LV9", + "is_pseudo": "0", + "dst_wire": "SE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>IMUX11": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>FAN_ALT2": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>IMUX10": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>SW2BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END_N3_3->>IMUX24": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>IMUX40": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END_N0_3->>WW4BEG0": { + "src_wire": "SS2END_N0_3", + "is_pseudo": "0", + "dst_wire": "WW4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>NN2BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>IMUX26": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>IMUX20": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>IMUX1": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>BYP_ALT3": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>SS2BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX37": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>SR1BEG1": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>SL1BEG2": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>FAN_ALT4": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_3->>IMUX25": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>NL1BEG2": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>BYP_ALT4": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>ER1BEG_S0": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>FAN_ALT3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX19": { + "src_wire": "BYP_BOUNCE_N3_7", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>NN6BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>SS6BEG2": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>IMUX36": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>IMUX27": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>BYP_ALT0": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>SE2BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>NW6BEG0": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>IMUX6": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>IMUX46": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END0->>SW6BEG0": { + "src_wire": "EE4END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>WL1BEG0": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX2": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>SE6BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END1->>NE6BEG1": { + "src_wire": "NW2END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>BYP_ALT0": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END_N3_3->>IMUX0": { + "src_wire": "SR1END_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>BYP_ALT0": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>IMUX16": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX16", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>IMUX38": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>WW4BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>SS6BEG1": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>WW2BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END0->>NW6BEG0": { + "src_wire": "NW2END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>NL1BEG0": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>NW6BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>SW2BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END1->>SL1BEG1": { + "src_wire": "SS6END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>FAN_ALT5": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>IMUX27": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX27", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>WW2BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>EE2BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>ER1BEG3": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>WW4BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "WW4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>SW2BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>FAN_ALT2": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>IMUX6": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>NN2BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>BYP_ALT2": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END3->>NW2BEG3": { + "src_wire": "WW4END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END_S1_0->>SR1BEG_S0": { + "src_wire": "NN6END_S1_0", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>IMUX6": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX17": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>NL1BEG2": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>IMUX22": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS20->>WL1BEG1": { + "src_wire": "LOGIC_OUTS20", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>IMUX29": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>WR1BEG2": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>IMUX8": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX11": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>NE6BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>SS6BEG1": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>IMUX17": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END0->>SE6BEG0": { + "src_wire": "SS6END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>SL1BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>SS2BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>IMUX43": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>WL1BEG2": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>SE6BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END0->>IMUX0": { + "src_wire": "NL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX8": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH12->>EE4BEG0": { + "src_wire": "LH12", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>NE2BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>NR1BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B4->>GCLK_B4_WEST": { + "src_wire": "GCLK_B4", + "is_pseudo": "0", + "dst_wire": "GCLK_B4_WEST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>ER1BEG2": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B4_EAST->>CLK1": { + "src_wire": "GCLK_B4_EAST", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END0->>IMUX17": { + "src_wire": "NE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>SE2BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>NR1BEG3": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>NW2BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>WW4BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>EE2BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "EE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END3->>SW6BEG3": { + "src_wire": "SS6END3", + "is_pseudo": "0", + "dst_wire": "SW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>CTRL1": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>NL1BEG0": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>WL1BEG0": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>EE2BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>FAN_ALT2": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>SL1BEG1": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>NN6BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>SW6BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>IMUX14": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>NW6BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT2->>FAN2": { + "src_wire": "FAN_ALT2", + "is_pseudo": "0", + "dst_wire": "FAN2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>WW2BEG1": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END3->>IMUX46": { + "src_wire": "WR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>IMUX23": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>EL1BEG0": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>NE2BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>SE2BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV18->>NE6BEG3": { + "src_wire": "LV18", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>IMUX9": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>IMUX46": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>SS2BEG2": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>IMUX21": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>SS2BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>NN2BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_2->>IMUX40": { + "src_wire": "BYP_BOUNCE_N3_2", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END_S2_0->>WW2BEG3": { + "src_wire": "NN2END_S2_0", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>FAN_ALT2": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END_S3_0->>IMUX39": { + "src_wire": "NL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>IMUX45": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>WW2BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "WW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>NR1BEG2": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "NR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>ER1BEG1": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>NE6BEG1": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>SE2BEG0": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>IMUX24": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>WR1BEG1": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>NR1BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>WL1BEG1": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "WL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>SE2BEG3": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>NN2BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>SS2BEG0": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END_N0_3->>NW6BEG0": { + "src_wire": "SW6END_N0_3", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END1->>CTRL1": { + "src_wire": "SW6END1", + "is_pseudo": "0", + "dst_wire": "CTRL1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>BYP_ALT7": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>SW2BEG3": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>EL1BEG2": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "EL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>EE4BEG3": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>NE6BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>IMUX22": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>SL1BEG2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>EL1BEG0": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>NE6BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN0->>IMUX32": { + "src_wire": "GFAN0", + "is_pseudo": "0", + "dst_wire": "IMUX32", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>WL1BEG_N3": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>NE2BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "NE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE1->>IMUX2": { + "src_wire": "FAN_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX3": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>EE4BEG0": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "EE4BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX21": { + "src_wire": "FAN_BOUNCE_S3_4", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>IMUX47": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END1->>IMUX18": { + "src_wire": "EL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>IMUX5": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>NN2BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "NN2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>SL1BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>IMUX36": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX29": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>IMUX34": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>NN2BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>IMUX4": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>NE2BEG2": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>NE2BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>SS2BEG1": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END2->>NW6BEG2": { + "src_wire": "WW4END2", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>SW2BEG2": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX8": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH0->>WW4BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>NW2BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "NW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>NE2BEG3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "NE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>IMUX37": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END_N0_3->>FAN_ALT0": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>WR1BEG1": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>IMUX19": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX19", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>SR1BEG1": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "SR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS6END2->>SS2BEG2": { + "src_wire": "SS6END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX36": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>IMUX40": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END0->>IMUX9": { + "src_wire": "SW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>SS6BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>IMUX4": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>IMUX29": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>NL1BEG2": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>NE6BEG2": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>NL1BEG2": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>IMUX38": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX38", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX22": { + "src_wire": "FAN_BOUNCE_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>IMUX21": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>IMUX12": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>FAN_ALT6": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>SL1BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>BYP_ALT1": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END2->>SR1BEG3": { + "src_wire": "SW2END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>SE2BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END1->>IMUX34": { + "src_wire": "SL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>SE6BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "SE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END0->>IMUX24": { + "src_wire": "NR1END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END2->>IMUX44": { + "src_wire": "SS2END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>IMUX47": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>IMUX15": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>ER1BEG1": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB12->>SW6BEG2": { + "src_wire": "LVB12", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>SS2BEG2": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE7->>IMUX42": { + "src_wire": "FAN_BOUNCE7", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>WW4BEG3": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "WW4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>SE6BEG0": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "SE6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>FAN_ALT5": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>IMUX11": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END1->>WW4BEG2": { + "src_wire": "WW2END1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>IMUX41": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>NL1BEG2": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "NL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>SL1BEG1": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>NW6BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>NW2BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE6->>BYP_ALT7": { + "src_wire": "BYP_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END2->>IMUX44": { + "src_wire": "WL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>SE2BEG1": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>BYP_ALT3": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END2->>IMUX20": { + "src_wire": "EE2END2", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>WW2BEG1": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END_N0_3->>IMUX8": { + "src_wire": "SW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE5->>IMUX43": { + "src_wire": "FAN_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>SS2BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>NN2BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>SR1BEG2": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "SR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END3->>SS2BEG3": { + "src_wire": "SR1END3", + "is_pseudo": "0", + "dst_wire": "SS2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX14": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>IMUX13": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>CLK0": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "CLK0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>LVB12": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "LVB12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END3->>ER1BEG_S0": { + "src_wire": "SE6END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>SS6BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1BEG_N3->>BYP_ALT3": { + "src_wire": "NL1BEG_N3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS1->>NW2BEG1": { + "src_wire": "LOGIC_OUTS1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>IMUX40": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>IMUX25": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END2->>IMUX46": { + "src_wire": "SR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END_N1_3->>NW2BEG0": { + "src_wire": "WL1END_N1_3", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>IMUX35": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END0->>NW6BEG0": { + "src_wire": "NN2END0", + "is_pseudo": "0", + "dst_wire": "NW6BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END2->>IMUX4": { + "src_wire": "EL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>NR1BEG0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "NR1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GFAN1->>IMUX7": { + "src_wire": "GFAN1", + "is_pseudo": "0", + "dst_wire": "IMUX7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>EE2BEG0": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END3->>EE4BEG3": { + "src_wire": "SS2END3", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>NN2BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "NN2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>IMUX45": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX45", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END0->>FAN_ALT4": { + "src_wire": "WR1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_6->>IMUX15": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>NL1BEG1": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>FAN_ALT1": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_3->>IMUX9": { + "src_wire": "BYP_BOUNCE_N3_3", + "is_pseudo": "0", + "dst_wire": "IMUX9", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B3_EAST->>CLK1": { + "src_wire": "GCLK_B3_EAST", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX10": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>SS6BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>SW2BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS4->>SL1BEG0": { + "src_wire": "LOGIC_OUTS4", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>FAN_ALT5": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>IMUX31": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END_S0_0->>SW2BEG3": { + "src_wire": "WW4END_S0_0", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>EL1BEG1": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "EL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS16->>NL1BEG1": { + "src_wire": "LOGIC_OUTS16", + "is_pseudo": "0", + "dst_wire": "NL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>NN6BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "NN6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END1->>IMUX12": { + "src_wire": "SS2END1", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS18->>IMUX1": { + "src_wire": "LOGIC_OUTS18", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END3->>SS6BEG3": { + "src_wire": "SW2END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>ER1BEG1": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "ER1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END3->>IMUX47": { + "src_wire": "WL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>IMUX46": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT4->>FAN_BOUNCE4": { + "src_wire": "FAN_ALT4", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>NE6BEG3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>IMUX36": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX36", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END1->>ER1BEG2": { + "src_wire": "EE4END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>NN2BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B9->>CLK1": { + "src_wire": "GCLK_B9", + "is_pseudo": "0", + "dst_wire": "CLK1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END2->>IMUX30": { + "src_wire": "WW2END2", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>IMUX37": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "IMUX37", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>SS2BEG2": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "SS2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX42": { + "src_wire": "BYP_BOUNCE_N3_6", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>NN6BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "NN6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>BYP_ALT1": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>SL1BEG3": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "SL1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>EL1BEG0": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END2->>NE6BEG2": { + "src_wire": "NN6END2", + "is_pseudo": "0", + "dst_wire": "NE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>NL1BEG0": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "NL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END0->>IMUX25": { + "src_wire": "WW2END0", + "is_pseudo": "0", + "dst_wire": "IMUX25", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>IMUX20": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "IMUX20", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END_S2_0->>SR1BEG_S0": { + "src_wire": "NN2END_S2_0", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE2->>IMUX24": { + "src_wire": "FAN_BOUNCE2", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>IMUX41": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX41", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END3->>BYP_ALT3": { + "src_wire": "EL1END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>IMUX23": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS21->>NR1BEG3": { + "src_wire": "LOGIC_OUTS21", + "is_pseudo": "0", + "dst_wire": "NR1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>WR1BEG1": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>IMUX29": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>IMUX43": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>SS2BEG0": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "SS2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>WL1BEG0": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>IMUX21": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX21", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>NW6BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>WR1BEG1": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END_S0_0->>SR1BEG_S0": { + "src_wire": "NW6END_S0_0", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS12->>SE2BEG0": { + "src_wire": "LOGIC_OUTS12", + "is_pseudo": "0", + "dst_wire": "SE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>WL1BEG0": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE5->>IMUX39": { + "src_wire": "BYP_BOUNCE5", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>IMUX14": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END1->>IMUX18": { + "src_wire": "NL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>SL1BEG0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS6->>NW6BEG2": { + "src_wire": "LOGIC_OUTS6", + "is_pseudo": "0", + "dst_wire": "NW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>FAN_ALT3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>IMUX44": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END2->>LVB0": { + "src_wire": "NW2END2", + "is_pseudo": "0", + "dst_wire": "LVB0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END2->>SW2BEG2": { + "src_wire": "SW6END2", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END_S0_0->>IMUX47": { + "src_wire": "NW2END_S0_0", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>IMUX29": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX29", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>SL1BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "SL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE6->>FAN_ALT2": { + "src_wire": "FAN_BOUNCE6", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END0->>EE2BEG0": { + "src_wire": "NN6END0", + "is_pseudo": "0", + "dst_wire": "EE2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS22->>WW2BEG0": { + "src_wire": "LOGIC_OUTS22", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>NE6BEG3": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "NE6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>SE2BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>FAN_ALT1": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS11->>SE2BEG3": { + "src_wire": "LOGIC_OUTS11", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>NE6BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END1->>WW2BEG0": { + "src_wire": "NW6END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END0->>SW2BEG0": { + "src_wire": "SL1END0", + "is_pseudo": "0", + "dst_wire": "SW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>NN6BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>LH12": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "LH12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>ER1BEG_S0": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>EE4BEG1": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>IMUX34": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "IMUX34", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>ER1BEG2": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW6END2->>NW2BEG2": { + "src_wire": "NW6END2", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS17->>NW6BEG3": { + "src_wire": "LOGIC_OUTS17", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>IMUX47": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>FAN_ALT4": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END1->>SE2BEG1": { + "src_wire": "SE2END1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END2->>BYP_ALT3": { + "src_wire": "SE2END2", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>IMUX28": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX28", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>IMUX14": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1BEG_S0->>IMUX42": { + "src_wire": "SR1BEG_S0", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END1->>WR1BEG2": { + "src_wire": "WR1END1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS10->>SW2BEG2": { + "src_wire": "LOGIC_OUTS10", + "is_pseudo": "0", + "dst_wire": "SW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS5->>NE2BEG1": { + "src_wire": "LOGIC_OUTS5", + "is_pseudo": "0", + "dst_wire": "NE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>IMUX2": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SR1END1->>IMUX3": { + "src_wire": "SR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END1->>EE2BEG1": { + "src_wire": "NE6END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>NN6BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END0->>LV18": { + "src_wire": "SW6END0", + "is_pseudo": "0", + "dst_wire": "LV18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END0->>IMUX1": { + "src_wire": "EE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END0->>IMUX40": { + "src_wire": "SE2END0", + "is_pseudo": "0", + "dst_wire": "IMUX40", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>IMUX23": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE_S3_6->>IMUX47": { + "src_wire": "FAN_BOUNCE_S3_6", + "is_pseudo": "0", + "dst_wire": "IMUX47", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>SS6BEG1": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>IMUX18": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX18", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE3->>IMUX31": { + "src_wire": "BYP_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX31", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END1->>EE2BEG1": { + "src_wire": "ER1END1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END0->>WR1BEG2": { + "src_wire": "WL1END0", + "is_pseudo": "0", + "dst_wire": "WR1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END1->>IMUX10": { + "src_wire": "NN2END1", + "is_pseudo": "0", + "dst_wire": "IMUX10", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.VCC_WIRE->>FAN_ALT3": { + "src_wire": "VCC_WIRE", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>IMUX24": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX24", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NW2END3->>BYP_ALT3": { + "src_wire": "NW2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS2->>IMUX44": { + "src_wire": "LOGIC_OUTS2", + "is_pseudo": "0", + "dst_wire": "IMUX44", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END3->>IMUX30": { + "src_wire": "SL1END3", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE4->>IMUX30": { + "src_wire": "BYP_BOUNCE4", + "is_pseudo": "0", + "dst_wire": "IMUX30", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END2->>NN2BEG2": { + "src_wire": "NE6END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS9->>IMUX2": { + "src_wire": "LOGIC_OUTS9", + "is_pseudo": "0", + "dst_wire": "IMUX2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END3->>WR1BEG_S0": { + "src_wire": "NE6END3", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>SW2BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "SW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LVB0->>WW4BEG2": { + "src_wire": "LVB0", + "is_pseudo": "0", + "dst_wire": "WW4BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END2->>FAN_ALT5": { + "src_wire": "NN2END2", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>NN2BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END1->>IMUX35": { + "src_wire": "EE2END1", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_ALT5->>FAN_BOUNCE5": { + "src_wire": "FAN_ALT5", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE5", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN2END3->>IMUX14": { + "src_wire": "NN2END3", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>IMUX42": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX42", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WR1END2->>NN2BEG2": { + "src_wire": "WR1END2", + "is_pseudo": "0", + "dst_wire": "NN2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>ER1BEG3": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "ER1BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS0->>BYP_ALT0": { + "src_wire": "LOGIC_OUTS0", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NN6END1->>NW6BEG1": { + "src_wire": "NN6END1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END3->>BYP_ALT3": { + "src_wire": "NE2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>WL1BEG2": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "WL1BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>IMUX23": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX23", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS3->>NW6BEG3": { + "src_wire": "LOGIC_OUTS3", + "is_pseudo": "0", + "dst_wire": "NW6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END1->>NW2BEG1": { + "src_wire": "NE2END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS19->>SL1BEG1": { + "src_wire": "LOGIC_OUTS19", + "is_pseudo": "0", + "dst_wire": "SL1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>IMUX43": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "IMUX43", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NL1END2->>EE2BEG2": { + "src_wire": "NL1END2", + "is_pseudo": "0", + "dst_wire": "EE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS8->>SL1BEG0": { + "src_wire": "LOGIC_OUTS8", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS14->>SE2BEG2": { + "src_wire": "LOGIC_OUTS14", + "is_pseudo": "0", + "dst_wire": "SE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END2->>SW6BEG2": { + "src_wire": "EE4END2", + "is_pseudo": "0", + "dst_wire": "SW6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS7->>SE2BEG3": { + "src_wire": "LOGIC_OUTS7", + "is_pseudo": "0", + "dst_wire": "SE2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SL1END2->>IMUX13": { + "src_wire": "SL1END2", + "is_pseudo": "0", + "dst_wire": "IMUX13", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END3->>IMUX46": { + "src_wire": "NR1END3", + "is_pseudo": "0", + "dst_wire": "IMUX46", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE2END3->>BYP_ALT7": { + "src_wire": "SE2END3", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW6END3->>ER1BEG_S0": { + "src_wire": "SW6END3", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LV9->>NN6BEG1": { + "src_wire": "LV9", + "is_pseudo": "0", + "dst_wire": "NN6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE4END3->>SS6BEG3": { + "src_wire": "EE4END3", + "is_pseudo": "0", + "dst_wire": "SS6BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE1->>GFAN1": { + "src_wire": "BYP_BOUNCE1", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END3->>IMUX15": { + "src_wire": "ER1END3", + "is_pseudo": "0", + "dst_wire": "IMUX15", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END_N0_3->>WR1BEG1": { + "src_wire": "WW2END_N0_3", + "is_pseudo": "0", + "dst_wire": "WR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END0->>SL1BEG0": { + "src_wire": "SE6END0", + "is_pseudo": "0", + "dst_wire": "SL1BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW4END1->>NE6BEG1": { + "src_wire": "WW4END1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS15->>WW2BEG3": { + "src_wire": "LOGIC_OUTS15", + "is_pseudo": "0", + "dst_wire": "WW2BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LH0->>EE4BEG3": { + "src_wire": "LH0", + "is_pseudo": "0", + "dst_wire": "EE4BEG3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>WW2BEG1": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NR1END1->>GFAN1": { + "src_wire": "NR1END1", + "is_pseudo": "0", + "dst_wire": "GFAN1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.FAN_BOUNCE3->>IMUX11": { + "src_wire": "FAN_BOUNCE3", + "is_pseudo": "0", + "dst_wire": "IMUX11", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE6END0->>NW2BEG0": { + "src_wire": "NE6END0", + "is_pseudo": "0", + "dst_wire": "NW2BEG0", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SW2END1->>NW2BEG2": { + "src_wire": "SW2END1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EE2END3->>IMUX22": { + "src_wire": "EE2END3", + "is_pseudo": "0", + "dst_wire": "IMUX22", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.NE2END2->>SE6BEG2": { + "src_wire": "NE2END2", + "is_pseudo": "0", + "dst_wire": "SE6BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END2->>IMUX14": { + "src_wire": "ER1END2", + "is_pseudo": "0", + "dst_wire": "IMUX14", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END2->>NE2BEG2": { + "src_wire": "SE6END2", + "is_pseudo": "0", + "dst_wire": "NE2BEG2", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WW2END3->>FAN_ALT3": { + "src_wire": "WW2END3", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>IMUX12": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "IMUX12", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS13->>IMUX35": { + "src_wire": "LOGIC_OUTS13", + "is_pseudo": "0", + "dst_wire": "IMUX35", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.LOGIC_OUTS23->>IMUX3": { + "src_wire": "LOGIC_OUTS23", + "is_pseudo": "0", + "dst_wire": "IMUX3", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END0->>IMUX8": { + "src_wire": "EL1END0", + "is_pseudo": "0", + "dst_wire": "IMUX8", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.GCLK_B2->>GCLK_B2_EAST": { + "src_wire": "GCLK_B2", + "is_pseudo": "0", + "dst_wire": "GCLK_B2_EAST", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.BYP_BOUNCE0->>IMUX26": { + "src_wire": "BYP_BOUNCE0", + "is_pseudo": "0", + "dst_wire": "IMUX26", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SS2END0->>IMUX17": { + "src_wire": "SS2END0", + "is_pseudo": "0", + "dst_wire": "IMUX17", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.WL1END1->>FAN_ALT7": { + "src_wire": "WL1END1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.ER1END0->>IMUX33": { + "src_wire": "ER1END0", + "is_pseudo": "0", + "dst_wire": "IMUX33", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.SE6END1->>NR1BEG1": { + "src_wire": "SE6END1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1", + "is_directional": "1", + "can_invert": "0" + }, + "INT_R.EL1END_S3_0->>IMUX39": { + "src_wire": "EL1END_S3_0", + "is_pseudo": "0", + "dst_wire": "IMUX39", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_IO_INT_INTERFACE_L.json b/kintex7/tile_type_IO_INT_INTERFACE_L.json new file mode 100644 index 0000000..73cf710 --- /dev/null +++ b/kintex7/tile_type_IO_INT_INTERFACE_L.json @@ -0,0 +1,428 @@ +{ + "tile_type": "IO_INT_INTERFACE_L", + "sites": [], + "wires": [ + "INT_INTERFACE_LOGIC_OUTS_L15", + "INT_INTERFACE_EE4C1", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_IMUX34", + "INT_INTERFACE_WW4C2", + "INT_INTERFACE_LH7", + "INT_INTERFACE_EE4C3", + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "INT_INTERFACE_LOGIC_OUTS_L11", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_IMUX12", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "INT_INTERFACE_BLOCK_OUTS_L_B3", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_IMUX3", + "INT_INTERFACE_LOGIC_OUTS_L23", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_LOGIC_OUTS_L7", + "INT_INTERFACE_IMUX5", + "INT_INTERFACE_LOGIC_OUTS_L3", + "INT_INTERFACE_LH11", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_LH8", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_SE2A2", + "INT_INTERFACE_IMUX46", + "INT_INTERFACE_WW4C1", + "INT_INTERFACE_IMUX29", + "INT_INTERFACE_SW2A3", + "INT_INTERFACE_IMUX24", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_IMUX47", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_IMUX9", + "INT_INTERFACE_EL1BEG3", + "L_INT_INTER_DQS_IOTOPHASER", + "INT_INTERFACE_LH5", + "INT_INTERFACE_IMUX17", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_INTERFACE_IMUX43", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_IMUX32", + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_SE4BEG3", + "INT_INTERFACE_IMUX36", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_LOGIC_OUTS_L13", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_IMUX10", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_WL1END1", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_LH10", + "INT_INTERFACE_LOGIC_OUTS_L22", + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_LOGIC_OUTS_L4", + "INT_INTERFACE_IMUX41", + "INT_INTERFACE_IMUX15", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_IMUX7", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_LH2", + "INT_INTERFACE_BLOCK_OUTS_L_B0", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_IMUX33", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_LH1", + "INT_INTERFACE_LOGIC_OUTS_L6", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_LH9", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_IMUX8", + "INT_INTERFACE_LH4", + "INT_INTERFACE_IMUX16", + "INT_INTERFACE_LOGIC_OUTS_L19", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_IMUX22", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_IMUX30", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_LOGIC_OUTS_L12", + "INT_INTERFACE_IMUX40", + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_BLOCK_OUTS_L_B1", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LH3", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_LOGIC_OUTS_L18", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "INT_INTERFACE_LOGIC_OUTS_L1", + "INT_INTERFACE_IMUX28", + "INT_INTERFACE_LOGIC_OUTS_L2", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_IMUX23", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "INT_INTERFACE_IMUX0", + "INT_INTERFACE_IMUX19", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_IMUX6", + "INT_INTERFACE_FAN5", + "INT_INTERFACE_LOGIC_OUTS_L8", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_IMUX37", + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_LOGIC_OUTS_L21", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_BYP5", + "INT_INTERFACE_IMUX25", + "INT_INTERFACE_IMUX39", + "INT_INTERFACE_IMUX26", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_LOGIC_OUTS_L14", + "INT_INTERFACE_LOGIC_OUTS_L10", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_IMUX14", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "INT_INTERFACE_IMUX35", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_IMUX42", + "INT_INTERFACE_IMUX4", + "INT_INTERFACE_WW4B1", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_IMUX45", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_IMUX1", + "INT_INTERFACE_IMUX18", + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "INT_INTERFACE_WW4A1", + "INT_INTERFACE_IMUX20", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_LOGIC_OUTS_L16", + "INT_INTERFACE_IMUX38", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_IMUX11", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_IMUX13", + "INT_INTERFACE_LH6", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_LH12", + "INT_INTERFACE_LOGIC_OUTS_L20", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "INT_INTERFACE_WR1END1", + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "INT_INTERFACE_IMUX31", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_IMUX44", + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_IMUX27", + "INT_INTERFACE_IMUX2", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_WW4END0", + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_EE2A3", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_LOGIC_OUTS_L5", + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_IMUX21", + "INT_INTERFACE_LOGIC_OUTS_L9", + "INT_INTERFACE_BYP7", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_BLOCK_OUTS_L_B2", + "INT_INTERFACE_LOGIC_OUTS_L17", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_LOGIC_OUTS_L0" + ], + "pips": { + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_IO_INT_INTERFACE_R.json b/kintex7/tile_type_IO_INT_INTERFACE_R.json new file mode 100644 index 0000000..fada41f --- /dev/null +++ b/kintex7/tile_type_IO_INT_INTERFACE_R.json @@ -0,0 +1,428 @@ +{ + "tile_type": "IO_INT_INTERFACE_R", + "sites": [], + "wires": [ + "INT_INTERFACE_EE4C1", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_IMUX34", + "INT_INTERFACE_WW4C2", + "INT_INTERFACE_LH7", + "INT_INTERFACE_EE4C3", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_LOGIC_OUTS_B22", + "INT_INTERFACE_IMUX12", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_LOGIC_OUTS16", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_LOGIC_OUTS3", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_LOGIC_OUTS20", + "INT_INTERFACE_LOGIC_OUTS22", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_IMUX3", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_LH8", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_LH11", + "INT_INTERFACE_IMUX5", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_LOGIC_OUTS1", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_LOGIC_OUTS0", + "INT_INTERFACE_BLOCK_OUTS_B0", + "INT_INTERFACE_SE2A2", + "INT_INTERFACE_IMUX46", + "INT_INTERFACE_WW4C1", + "INT_INTERFACE_IMUX29", + "INT_INTERFACE_SW2A3", + "INT_INTERFACE_IMUX24", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_IMUX47", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_IMUX9", + "INT_INTERFACE_EL1BEG3", + "L_INT_INTER_DQS_IOTOPHASER", + "INT_INTERFACE_LH5", + "INT_INTERFACE_IMUX17", + "INT_INTERFACE_BLOCK_OUTS_B3", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_INTERFACE_IMUX43", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_IMUX32", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_SE4BEG3", + "INT_INTERFACE_IMUX36", + "INT_INTERFACE_LOGIC_OUTS_B2", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_LOGIC_OUTS_B20", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_IMUX10", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_WL1END1", + "INT_INTERFACE_LOGIC_OUTS_B23", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_LH10", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_LOGIC_OUTS_B6", + "INT_INTERFACE_IMUX41", + "INT_INTERFACE_IMUX15", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_IMUX7", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_LOGIC_OUTS18", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_LOGIC_OUTS_B16", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_LH2", + "INT_INTERFACE_LOGIC_OUTS_B14", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_IMUX33", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_LOGIC_OUTS23", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_LH1", + "INT_INTERFACE_LOGIC_OUTS5", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_LH9", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_IMUX8", + "INT_INTERFACE_LH4", + "INT_INTERFACE_IMUX16", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_IMUX22", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_IMUX30", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_LOGIC_OUTS15", + "INT_INTERFACE_IMUX40", + "INT_INTERFACE_LOGIC_OUTS_B19", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_LOGIC_OUTS11", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LOGIC_OUTS_B17", + "INT_INTERFACE_LH3", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_LOGIC_OUTS_B15", + "INT_INTERFACE_LOGIC_OUTS_B9", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_LOGIC_OUTS_B0", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_BLOCK_OUTS_B1", + "INT_INTERFACE_LOGIC_OUTS_B7", + "INT_INTERFACE_LOGIC_OUTS_B8", + "INT_INTERFACE_LOGIC_OUTS14", + "INT_INTERFACE_IMUX28", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_LOGIC_OUTS8", + "INT_INTERFACE_IMUX23", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_LOGIC_OUTS12", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_LOGIC_OUTS4", + "INT_INTERFACE_IMUX0", + "INT_INTERFACE_IMUX19", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_LOGIC_OUTS_B3", + "INT_INTERFACE_IMUX6", + "INT_INTERFACE_LOGIC_OUTS21", + "INT_INTERFACE_FAN5", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_IMUX37", + "INT_INTERFACE_LOGIC_OUTS7", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_LOGIC_OUTS_B18", + "INT_INTERFACE_BYP5", + "INT_INTERFACE_IMUX25", + "INT_INTERFACE_IMUX39", + "INT_INTERFACE_IMUX26", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_IMUX14", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_LOGIC_OUTS_B4", + "INT_INTERFACE_IMUX35", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_IMUX42", + "INT_INTERFACE_IMUX4", + "INT_INTERFACE_WW4B1", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_IMUX45", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_LOGIC_OUTS_B21", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_IMUX1", + "INT_INTERFACE_IMUX18", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_WW4A1", + "INT_INTERFACE_IMUX20", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_IMUX38", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_IMUX11", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_IMUX13", + "INT_INTERFACE_LH6", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_LH12", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_WR1END1", + "INT_INTERFACE_LOGIC_OUTS10", + "INT_INTERFACE_IMUX31", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_LOGIC_OUTS13", + "INT_INTERFACE_IMUX44", + "INT_INTERFACE_LOGIC_OUTS_B11", + "INT_INTERFACE_LOGIC_OUTS9", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_IMUX27", + "INT_INTERFACE_IMUX2", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_LOGIC_OUTS_B10", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_LOGIC_OUTS_B5", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_LOGIC_OUTS19", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_BLOCK_OUTS_B2", + "INT_INTERFACE_WW4END0", + "INT_INTERFACE_LOGIC_OUTS17", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_LOGIC_OUTS_B13", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_EE2A3", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_LOGIC_OUTS2", + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_IMUX21", + "INT_INTERFACE_LOGIC_OUTS6", + "INT_INTERFACE_BYP7", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LOGIC_OUTS_B12", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + "pips": { + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B13", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS13", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS1", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B22", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS22", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B9", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS9", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B16", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS16", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B2", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS2", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B11", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS11", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B20", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS20", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B18", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS18", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B3", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS3", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B14", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS14", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B15", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS15", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B17", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS17", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B4", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS4", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B12", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS12", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B6", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS6", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B0", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS0", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B23", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS23", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B7", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS7", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B19", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS19", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B5", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS5", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B10", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS10", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B21", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS21", + "is_directional": "1", + "can_invert": "0" + }, + "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B8", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS8", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_LIOB33.json b/kintex7/tile_type_LIOB33.json new file mode 100644 index 0000000..aad7894 --- /dev/null +++ b/kintex7/tile_type_LIOB33.json @@ -0,0 +1,415 @@ +{ + "tile_type": "LIOB33", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IOB", + "type": "IOB33S", + "site_pins": { + "PU_INT_EN": "IOB_PU_INT_EN_0", + "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_0", + "DIFFO_OUT": "IOB_DIFFO_OUT1", + "PADOUT": "IOB_PADOUT1", + "O_IN": "IOB_O_IN1", + "DIFFI_IN": "IOB_DIFFI_IN1", + "O_OUT": "IOB_O_OUT1", + "INTERMDISABLE": "LIOB_IN_TERM1", + "O": "IOB_O1", + "DIFF_TERM_INT_EN": "IOB_DIFF_TERM_INT_EN", + "T": "IOB_T1", + "DIFFO_IN": "IOB_DIFFO_IN1", + "I": "IOB_IBUF1", + "PD_INT_EN": "IOB_PD_INT_EN_0", + "IBUFDISABLE": "IOB_IBUF_DISABLE1", + "T_OUT": "IOB_T_OUT1", + "T_IN": "IOB_T_IN1" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "IOB", + "type": "IOB33M", + "site_pins": { + "PU_INT_EN": "IOB_PU_INT_EN_1", + "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", + "DIFFO_OUT": "IOB_DIFFO_OUT0", + "PADOUT": "IOB_PADOUT0", + "O_IN": null, + "DIFFI_IN": "IOB_DIFFI_IN0", + "O_OUT": "IOB_O_OUT0", + "INTERMDISABLE": "LIOB_IN_TERM0", + "O": "IOB_O0", + "DIFF_TERM_INT_EN": null, + "T": "IOB_T0", + "DIFFO_IN": null, + "I": "IOB_IBUF0", + "PD_INT_EN": "IOB_PD_INT_EN_1", + "IBUFDISABLE": "IOB_IBUF_DISABLE0", + "T_OUT": "IOB_T_OUT0", + "T_IN": null + }, + "x_coord": 0 + } + ], + "wires": [ + "LIOB_WW4END0_0", + "LIOB_SW2A3_0", + "LIOB_SE2A0_1", + "LIOB_WW4B1_1", + "LIOB_EE2BEG0_1", + "LIOB_SE4BEG2_1", + "LIOB_NE4C1_0", + "IOB_DIFFO_OUT1", + "LIOB_EE4B3_0", + "LIOB_SW4A1_0", + "LIOB_EE4BEG0_1", + "LIOB_EE2BEG1_1", + "LIOB_EL1BEG1_1", + "LIOB_EE2BEG3_1", + "LIOB_EE4A0_0", + "LIOB_WR1END0_0", + "LIOB_NW2A3_1", + "LIOB_LH1_0", + "LIOB_EE2BEG2_0", + "LIOB_SW4A2_0", + "LIOB_WW4B1_0", + "IOB_PU_INT_EN_0", + "LIOB_EL1BEG0_1", + "LIOB_WW2END3_0", + "LIOB_NE4C0_0", + "LIOB_LH9_0", + "LIOB_WW4END3_0", + "LIOB_NW4A2_0", + "IOB_KEEPER_INT_EN_1", + "LIOB_WW4B2_0", + "LIOB_WL1END0_0", + "LIOB_EE4BEG3_1", + "IOB_O_OUT1", + "IOB_DIFFI_IN1", + "LIOB_SW2A0_1", + "IOB_T_IN0", + "LIOB_SE2A1_1", + "LIOB_EE4BEG1_0", + "LIOB_SE4C0_0", + "LIOB_EE4A1_1", + "LIOB_SW4END2_1", + "LIOB_LH5_1", + "LIOB_LH5_0", + "LIOB_IN_TERM0", + "LIOB_NW2A2_0", + "LIOB_SW4END3_1", + "LIOB_SW4END3_0", + "LIOB_WR1END3_1", + "LIOB_LH11_0", + "LIOB_NE4BEG0_1", + "LIOB_SE4C2_1", + "IOB_PD_INT_EN_1", + "LIOB_LH6_1", + "LIOB_WW4END2_1", + "LIOB_EE4C0_1", + "LIOB_NE4BEG0_0", + "IOB_DIFF_TERM_INT_EN", + "LIOB_WW2END1_0", + "IOB_IBUF1", + "IOB_IBUF0", + "LIOB_LH1_1", + "LIOB_EE4C2_0", + "LIOB_WW4A1_0", + "LIOB_EE4C3_0", + "LIOB_SW4END2_0", + "LIOB_WW4A0_0", + "IOB_DIFF_TERM_INT_EN_STUB", + "LIOB_MONITOR_N", + "LIOB_EE4B1_1", + "LIOB_NE4C3_0", + "LIOB_SW2A2_1", + "LIOB_EE4B0_0", + "LIOB_ER1BEG3_0", + "LIOB_LH7_1", + "LIOB_EE4A3_1", + "LIOB_SW2A2_0", + "LIOB_EE2A1_1", + "LIOB_EE4B2_1", + "LIOB_ER1BEG0_0", + "LIOB_SW4A2_1", + "LIOB_LH11_1", + "LIOB_EE4BEG2_0", + "LIOB_NE2A2_1", + "LIOB_NE2A1_1", + "LIOB_WW4END2_0", + "LIOB_ER1BEG1_0", + "LIOB_EL1BEG3_1", + "LIOB_EE4A3_0", + "LIOB_WW2A0_1", + "LIOB_NE2A2_0", + "LIOB_EE4A2_1", + "LIOB_WR1END1_0", + "LIOB_NW2A0_1", + "LIOB_EE4C0_0", + "LIOB_NW4A1_0", + "LIOB_SE4C0_1", + "LIOB_LH10_0", + "LIOB_NW2A1_0", + "IOB_T1", + "IOB_O0", + "LIOB_WW2A1_0", + "LIOB_EE4BEG0_0", + "IOB_O_IN0", + "LIOB_EL1BEG3_0", + "LIOB_NE2A1_0", + "LIOB_WL1END3_1", + "IOB_DIFFO_IN1", + "LIOB_SW4END1_1", + "LIOB_WW4C2_1", + "LIOB_EE2BEG3_0", + "LIOB_WW2A2_0", + "IOB_T_IN1", + "IOB_T_OUT1", + "IOB_O_IN1", + "LIOB_EE4B1_0", + "LIOB_NE4C1_1", + "LIOB_LH7_0", + "LIOB_WW4END0_1", + "LIOB_EE2A2_1", + "LIOB_NE4C2_1", + "LIOB_SE2A2_0", + "LIOB_SW4END1_0", + "LIOB_WW4END1_1", + "LIOB_WW4C2_0", + "IOB_KEEPER_INT_EN_0", + "LIOB_EE2A3_1", + "LIOB_EE2A1_0", + "LIOB_NW2A1_1", + "LIOB_NE2A3_1", + "LIOB_LH4_0", + "LIOB_NW4END1_1", + "LIOB_SW4END0_0", + "LIOB_WL1END0_1", + "LIOB_EE4BEG3_0", + "LIOB_NW4A3_0", + "LIOB_NE4C0_1", + "LIOB_SW4A1_1", + "LIOB_NW4END0_1", + "LIOB_SE4BEG0_0", + "IOB_DIFFI_IN0", + "LIOB_SE2A1_0", + "LIOB_NE4BEG2_1", + "LIOB_LH2_0", + "LIOB_EE4BEG2_1", + "LIOB_WW4C1_1", + "LIOB_WW4B0_1", + "LIOB_LH2_1", + "LIOB_NE4BEG2_0", + "IOB_PADOUT1", + "LIOB_LH6_0", + "LIOB_SW2A0_0", + "LIOB_WW4C3_1", + "LIOB_SE4C1_1", + "LIOB_MONITOR_P", + "LIOB_WW2END1_1", + "LIOB_WL1END3_0", + "LIOB_WW2A3_0", + "IOB_O1", + "LIOB_WW4END1_0", + "LIOB_WW4A1_1", + "LIOB_WW4A2_0", + "LIOB_LH3_0", + "LIOB_WW4A3_0", + "LIOB_WL1END1_1", + "LIOB_WW4A0_1", + "LIOB_EE4C2_1", + "LIOB_WW4B3_1", + "LIOB_SE4C1_0", + "LIOB_WW4C0_0", + "IOB_O_OUT0", + "LIOB_NW4A1_1", + "IOB_PD_INT_EN_0", + "LIOB_WW4C0_1", + "LIOB_EE4C1_0", + "LIOB_EE2BEG1_0", + "LIOB_LH10_1", + "IOB_T_OUT0", + "LIOB_ER1BEG2_1", + "LIOB_EL1BEG2_0", + "LIOB_ER1BEG0_1", + "LIOB_LH9_1", + "LIOB_NW4A3_1", + "LIOB_NW4END3_1", + "LIOB_EE4B0_1", + "LIOB_EE2BEG2_1", + "LIOB_EE4A0_1", + "LIOB_NW2A0_0", + "LIOB_NE4BEG3_0", + "LIOB_NW4END3_0", + "LIOB_EE2BEG0_0", + "LIOB_LH12_0", + "LIOB_EE4A1_0", + "LIOB_EE4C3_1", + "LIOB_EE4BEG1_1", + "LIOB_NE4C2_0", + "LIOB_SW4A3_1", + "LIOB_EE4A2_0", + "LIOB_LH8_0", + "IOB_DIFFO_IN0", + "LIOB_SE4C3_1", + "LIOB_WR1END0_1", + "LIOB_ER1BEG1_1", + "LIOB_LH12_1", + "LIOB_SE2A0_0", + "LIOB_NW2A2_1", + "LIOB_WW4B2_1", + "LIOB_EE2A0_1", + "LIOB_EL1BEG1_0", + "LIOB_SW4END0_1", + "LIOB_WW2A3_1", + "LIOB_SE2A3_0", + "LIOB_WW4END3_1", + "LIOB_SE4BEG3_0", + "IOB_PU_INT_EN_1", + "LIOB_NE2A3_0", + "LIOB_WW2A2_1", + "LIOB_SW4A0_0", + "LIOB_WW4A2_1", + "LIOB_WW2END3_1", + "LIOB_NW4A0_1", + "LIOB_EE2A0_0", + "LIOB_NE4BEG1_1", + "LIOB_NE2A0_0", + "LIOB_NW4END1_0", + "LIOB_WW2END2_0", + "LIOB_ER1BEG3_1", + "LIOB_SW2A3_1", + "LIOB_EL1BEG0_0", + "LIOB_LH3_1", + "LIOB_SE2A2_1", + "LIOB_SE4C2_0", + "LIOB_WW4B0_0", + "LIOB_IN_TERM1", + "LIOB_NW4END2_0", + "LIOB_NW4A2_1", + "LIOB_EE2A3_0", + "LIOB_LH4_1", + "LIOB_WW4B3_0", + "LIOB_WL1END2_0", + "LIOB_WR1END2_0", + "LIOB_NE2A0_1", + "LIOB_WR1END1_1", + "LIOB_WW4C1_0", + "LIOB_SW2A1_0", + "LIOB_WW4C3_0", + "LIOB_EE2A2_0", + "LIOB_WW2END2_1", + "LIOB_SE4BEG2_0", + "LIOB_NW2A3_0", + "LIOB_NW4END2_1", + "LIOB_SE2A3_1", + "LIOB_SW4A3_0", + "LIOB_WW2END0_1", + "LIOB_WW4A3_1", + "IOB_DIFFO_OUT0", + "LIOB_SE4BEG0_1", + "LIOB_NW4A0_0", + "LIOB_WL1END2_1", + "IOB_IBUF_DISABLE1", + "LIOB_SW4A0_1", + "LIOB_WR1END2_1", + "LIOB_SE4BEG1_0", + "LIOB_WW2A1_1", + "LIOB_EE4C1_1", + "IOB_IBUF_DISABLE0", + "LIOB_SE4C3_0", + "LIOB_NE4BEG1_0", + "IOB_T0", + "LIOB_ER1BEG2_0", + "LIOB_SE4BEG3_1", + "LIOB_WW2END0_0", + "LIOB_NE4BEG3_1", + "LIOB_WR1END3_0", + "LIOB_WW2A0_0", + "LIOB_NW4END0_0", + "LIOB_WL1END1_0", + "IOB_PADOUT0", + "LIOB_SW2A1_1", + "LIOB_EL1BEG2_1", + "LIOB_EE4B2_0", + "LIOB_LH8_1", + "LIOB_SE4BEG1_1", + "LIOB_NE4C3_1", + "LIOB_EE4B3_1" + ], + "pips": { + "LIOB33.IOB_DIFFO_OUT0->IOB_DIFFO_IN1": { + "src_wire": "IOB_DIFFO_OUT0", + "is_pseudo": "0", + "dst_wire": "IOB_DIFFO_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOB33.IOB_PADOUT1->LIOB_MONITOR_N": { + "src_wire": "IOB_PADOUT1", + "is_pseudo": "0", + "dst_wire": "LIOB_MONITOR_N", + "is_directional": "1", + "can_invert": "0" + }, + "LIOB33.IOB_PADOUT1->IOB_DIFFI_IN0": { + "src_wire": "IOB_PADOUT1", + "is_pseudo": "0", + "dst_wire": "IOB_DIFFI_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOB33.IOB_O0->>IOB_O_OUT0": { + "src_wire": "IOB_O0", + "is_pseudo": "1", + "dst_wire": "IOB_O_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOB33.IOB_PADOUT0->IOB_DIFFI_IN1": { + "src_wire": "IOB_PADOUT0", + "is_pseudo": "0", + "dst_wire": "IOB_DIFFI_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOB33.IOB_PADOUT0->LIOB_MONITOR_P": { + "src_wire": "IOB_PADOUT0", + "is_pseudo": "0", + "dst_wire": "LIOB_MONITOR_P", + "is_directional": "1", + "can_invert": "0" + }, + "LIOB33.IOB_O_OUT0->IOB_O_IN1": { + "src_wire": "IOB_O_OUT0", + "is_pseudo": "0", + "dst_wire": "IOB_O_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOB33.IOB_T0->>IOB_T_OUT0": { + "src_wire": "IOB_T0", + "is_pseudo": "1", + "dst_wire": "IOB_T_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOB33.IOB_T_OUT0->IOB_T_IN1": { + "src_wire": "IOB_T_OUT0", + "is_pseudo": "0", + "dst_wire": "IOB_T_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOB33.IOB_DIFFO_IN1->>IOB_PADOUT1": { + "src_wire": "IOB_DIFFO_IN1", + "is_pseudo": "1", + "dst_wire": "IOB_PADOUT1", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_LIOB33_SING.json b/kintex7/tile_type_LIOB33_SING.json new file mode 100644 index 0000000..c20d22a --- /dev/null +++ b/kintex7/tile_type_LIOB33_SING.json @@ -0,0 +1,175 @@ +{ + "tile_type": "LIOB33_SING", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IOB", + "type": "IOB33", + "site_pins": { + "O_OUT": "IOB_O_OUT0", + "INTERMDISABLE": "LIOB_IN_TERM0", + "O": "IOB_O0", + "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", + "T": "IOB_T0", + "T_OUT": "IOB_T_OUT0", + "DIFFI_IN": null, + "PU_INT_EN": "IOB_PU_INT_EN_1", + "DIFF_TERM_INT_EN": null, + "PADOUT": "IOB_PADOUT0", + "O_IN": null, + "IBUFDISABLE": "IOB_IBUF_DISABLE0", + "DIFFO_IN": null, + "DIFFO_OUT": "IOB_DIFFO_OUT0", + "PD_INT_EN": "IOB_PD_INT_EN_1", + "I": "IOB_IBUF0", + "T_IN": null + }, + "x_coord": 0 + } + ], + "wires": [ + "LIOB_SE2A1_0", + "LIOB_WW4END0_0", + "LIOB_LH2_0", + "LIOB_SW2A3_0", + "LIOB_NE4BEG2_0", + "LIOB_LH6_0", + "LIOB_SW2A0_0", + "LIOB_NE4C1_0", + "LIOB_EE4B3_0", + "LIOB_WL1END3_0", + "LIOB_SW4A1_0", + "LIOB_WW2A3_0", + "LIOB_EE4A0_0", + "LIOB_WW4END1_0", + "LIOB_WR1END0_0", + "LIOB_LH1_0", + "LIOB_EE2BEG2_0", + "LIOB_WW4A2_0", + "LIOB_LH3_0", + "LIOB_WW4A3_0", + "LIOB_SW4A2_0", + "LIOB_WW4B1_0", + "LIOB_SE4C1_0", + "LIOB_WW4C0_0", + "IOB_O_OUT0", + "LIOB_EE4C1_0", + "LIOB_WW2END3_0", + "LIOB_EE2BEG1_0", + "LIOB_NE4C0_0", + "IOB_T_OUT0", + "LIOB_EL1BEG2_0", + "LIOB_LH9_0", + "LIOB_WW4END3_0", + "LIOB_NW4A2_0", + "IOB_KEEPER_INT_EN_1", + "LIOB_WW4B2_0", + "LIOB_WL1END0_0", + "LIOB_NW2A0_0", + "LIOB_NE4BEG3_0", + "LIOB_NW4END3_0", + "IOB_T_IN0", + "LIOB_EE2BEG0_0", + "LIOB_EE4BEG1_0", + "LIOB_LH12_0", + "LIOB_SE4C0_0", + "LIOB_EE4A1_0", + "LIOB_LH5_0", + "LIOB_IN_TERM0", + "LIOB_NW2A2_0", + "LIOB_SW4END3_0", + "LIOB_NE4C2_0", + "LIOB_EE4A2_0", + "LIOB_LH11_0", + "LIOB_LH8_0", + "IOB_DIFFO_IN0", + "IOB_PD_INT_EN_1", + "LIOB_NE4BEG0_0", + "LIOB_WW2END1_0", + "IOB_IBUF0", + "LIOB_SE2A0_0", + "LIOB_EE4C2_0", + "LIOB_WW4A1_0", + "LIOB_EE4C3_0", + "LIOB_SW4END2_0", + "LIOB_WW4A0_0", + "IOB_DIFF_TERM_INT_EN_STUB", + "LIOB_EL1BEG1_0", + "LIOB_NE4C3_0", + "LIOB_EE4B0_0", + "LIOB_ER1BEG3_0", + "LIOB_SW2A2_0", + "LIOB_SE2A3_0", + "LIOB_SE4BEG3_0", + "IOB_PU_INT_EN_1", + "LIOB_ER1BEG0_0", + "LIOB_NE2A3_0", + "LIOB_SW4A0_0", + "LIOB_EE4BEG2_0", + "LIOB_WW4END2_0", + "LIOB_EE2A0_0", + "LIOB_ER1BEG1_0", + "LIOB_NE2A0_0", + "LIOB_NW4END1_0", + "LIOB_WW2END2_0", + "LIOB_EE4A3_0", + "LIOB_EL1BEG0_0", + "LIOB_NE2A2_0", + "LIOB_SE4C2_0", + "LIOB_WW4B0_0", + "LIOB_NW4END2_0", + "LIOB_EE2A3_0", + "LIOB_WR1END1_0", + "LIOB_WW4B3_0", + "LIOB_WR1END2_0", + "LIOB_WL1END2_0", + "LIOB_EE4C0_0", + "LIOB_NW4A1_0", + "LIOB_LH10_0", + "LIOB_WW4C1_0", + "LIOB_SW2A1_0", + "LIOB_WW4C3_0", + "LIOB_NW2A1_0", + "LIOB_EE2A2_0", + "LIOB_SE4BEG2_0", + "LIOB_NW2A3_0", + "IOB_O0", + "LIOB_WW2A1_0", + "LIOB_SW4A3_0", + "LIOB_EE4BEG0_0", + "IOB_O_IN0", + "LIOB_EL1BEG3_0", + "LIOB_NE2A1_0", + "IOB_DIFFO_OUT0", + "LIOB_NW4A0_0", + "LIOB_EE2BEG3_0", + "LIOB_WW2A2_0", + "LIOB_SE4BEG1_0", + "IOB_IBUF_DISABLE0", + "LIOB_SE4C3_0", + "LIOB_EE4B1_0", + "LIOB_LH7_0", + "LIOB_NE4BEG1_0", + "LIOB_SE2A2_0", + "LIOB_SW4END1_0", + "IOB_T0", + "LIOB_ER1BEG2_0", + "LIOB_WW4C2_0", + "LIOB_WW2END0_0", + "LIOB_EE2A1_0", + "LIOB_WW2A0_0", + "LIOB_WR1END3_0", + "LIOB_NW4END0_0", + "LIOB_SW4END0_0", + "LIOB_WL1END1_0", + "LIOB_LH4_0", + "LIOB_EE4BEG3_0", + "IOB_PADOUT0", + "LIOB_EE4B2_0", + "LIOB_NW4A3_0", + "LIOB_SE4BEG0_0", + "IOB_DIFFI_IN0" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_LIOI3.json b/kintex7/tile_type_LIOI3.json new file mode 100644 index 0000000..edef9c0 --- /dev/null +++ b/kintex7/tile_type_LIOI3.json @@ -0,0 +1,3928 @@ +{ + "tile_type": "LIOI3", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "OLOGIC", + "type": "OLOGICE3", + "site_pins": { + "TQ": "LIOI_OLOGIC1_TQ", + "D3": "IOI_OLOGIC1_D3", + "D4": "IOI_OLOGIC1_D4", + "CLKDIV": "IOI_OLOGIC1_CLKDIV", + "SHIFTOUT1": "LIOI_OSOUT11", + "SR": "IOI_OLOGIC1_SR", + "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", + "T4": "IOI_OLOGIC1_T4", + "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", + "CLKB": "IOI_OLOGIC1_CLKB", + "SHIFTIN1": null, + "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", + "T2": "IOI_OLOGIC1_T2", + "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", + "D2": "IOI_OLOGIC1_D2", + "CLK": "IOI_OLOGIC1_CLK", + "OFB": "LIOI_OLOGIC1_OFB", + "T1": "IOI_OLOGIC1_T1", + "D6": "IOI_OLOGIC1_D6", + "SHIFTIN2": null, + "TCE": "IOI_OLOGIC1_TCE", + "OCE": "IOI_OLOGIC1_OCE", + "SHIFTOUT2": "LIOI_OSOUT21", + "TFB": "LIOI_OLOGIC1_TFB", + "REV": null, + "D5": "IOI_OLOGIC1_D5", + "OQ": "LIOI_OLOGIC1_OQ", + "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", + "T3": "IOI_OLOGIC1_T3", + "D1": "IOI_OLOGIC1_D1", + "CLKDIVF": "LIOI_OLOGIC1_CLKDIVF", + "D7": "IOI_OLOGIC1_D7", + "D8": "IOI_OLOGIC1_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "ILOGIC", + "type": "ILOGICE3", + "site_pins": { + "Q4": "IOI_ILOGIC1_Q4", + "Q3": "IOI_ILOGIC1_Q3", + "Q5": "IOI_ILOGIC1_Q5", + "O": "IOI_ILOGIC1_O", + "Q1": "IOI_ILOGIC1_Q1", + "Q6": "IOI_ILOGIC1_Q6", + "Q7": "IOI_ILOGIC1_Q7", + "Q8": "IOI_ILOGIC1_Q8", + "CLKB": "IOI_ILOGIC1_CLKB", + "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", + "SHIFTIN1": "LIOI_ISIN11", + "Q2": "IOI_ILOGIC1_Q2", + "CE1": "IOI_ILOGIC1_CE1", + "CE2": "IOI_ILOGIC1_CE2", + "SR": "IOI_ILOGIC1_SR", + "D": "LIOI_ILOGIC1_D", + "CLK": "IOI_ILOGIC1_CLK", + "TFB": "LIOI_ILOGIC1_TFB", + "DDLY": "LIOI_ILOGIC1_DDLY", + "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", + "SHIFTIN2": "LIOI_ISIN21", + "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", + "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "SHIFTOUT2": "LIOI_ISOUT21", + "OFB": "LIOI_ILOGIC1_OFB", + "REV": null, + "OCLKB": "IOI_ILOGIC1_OCLKB", + "SHIFTOUT1": "LIOI_ISOUT11", + "OCLK": "IOI_ILOGIC1_OCLK", + "CLKDIV": "IOI_ILOGIC1_CLKDIV", + "BITSLIP": "IOI_ILOGIC1_BITSLIP" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "OLOGIC", + "type": "OLOGICE3", + "site_pins": { + "TQ": "LIOI_OLOGIC0_TQ", + "D3": "IOI_OLOGIC0_D3", + "D4": "IOI_OLOGIC0_D4", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "SHIFTOUT1": "LIOI_OSOUT10", + "SR": "IOI_OLOGIC0_SR", + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "T4": "IOI_OLOGIC0_T4", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "CLKB": "IOI_OLOGIC0_CLKB", + "SHIFTIN1": "LIOI_OSIN10", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "T2": "IOI_OLOGIC0_T2", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "D2": "IOI_OLOGIC0_D2", + "CLK": "IOI_OLOGIC0_CLK", + "OFB": "LIOI_OLOGIC0_OFB", + "T1": "IOI_OLOGIC0_T1", + "D6": "IOI_OLOGIC0_D6", + "SHIFTIN2": "LIOI_OSIN20", + "TCE": "IOI_OLOGIC0_TCE", + "OCE": "IOI_OLOGIC0_OCE", + "SHIFTOUT2": "LIOI_OSOUT20", + "TFB": "LIOI_OLOGIC0_TFB", + "REV": null, + "D5": "IOI_OLOGIC0_D5", + "OQ": "LIOI_OLOGIC0_OQ", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "T3": "IOI_OLOGIC0_T3", + "D1": "IOI_OLOGIC0_D1", + "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF", + "D7": "IOI_OLOGIC0_D7", + "D8": "IOI_OLOGIC0_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "ILOGIC", + "type": "ILOGICE3", + "site_pins": { + "Q4": "IOI_ILOGIC0_Q4", + "Q3": "IOI_ILOGIC0_Q3", + "Q5": "IOI_ILOGIC0_Q5", + "O": "IOI_ILOGIC0_O", + "Q1": "IOI_ILOGIC0_Q1", + "Q6": "IOI_ILOGIC0_Q6", + "Q7": "IOI_ILOGIC0_Q7", + "Q8": "IOI_ILOGIC0_Q8", + "CLKB": "IOI_ILOGIC0_CLKB", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "SHIFTIN1": null, + "Q2": "IOI_ILOGIC0_Q2", + "CE1": "IOI_ILOGIC0_CE1", + "CE2": "IOI_ILOGIC0_CE2", + "SR": "IOI_ILOGIC0_SR", + "D": "LIOI_ILOGIC0_D", + "CLK": "IOI_ILOGIC0_CLK", + "TFB": "LIOI_ILOGIC0_TFB", + "DDLY": "LIOI_ILOGIC0_DDLY", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "SHIFTIN2": null, + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "SHIFTOUT2": "LIOI_ISOUT20", + "OFB": "LIOI_ILOGIC0_OFB", + "REV": null, + "OCLKB": "IOI_ILOGIC0_OCLKB", + "SHIFTOUT1": "LIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "BITSLIP": "IOI_ILOGIC0_BITSLIP" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IDELAY", + "type": "IDELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", + "DATAOUT": "LIOI_IDELAY1_DATAOUT", + "IDATAIN": "LIOI_IDELAY1_IDATAIN", + "REGRST": "IOI_IDELAY1_REGRST", + "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", + "C": "IOI_IDELAY1_C", + "IFDLY0": "LIOI3_IDELAY1_IFDLY0", + "DATAIN": "IOI_IDELAY1_DATAIN", + "LD": "IOI_IDELAY1_LD", + "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", + "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", + "CINVCTRL": "IOI_IDELAY1_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", + "IFDLY1": "LIOI3_IDELAY1_IFDLY1", + "IFDLY2": "LIOI3_IDELAY1_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", + "INC": "IOI_IDELAY1_INC", + "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", + "CE": "IOI_IDELAY1_CE", + "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "IDELAY", + "type": "IDELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "DATAOUT": "LIOI_IDELAY0_DATAOUT", + "IDATAIN": "LIOI_IDELAY0_IDATAIN", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "C": "IOI_IDELAY0_C", + "IFDLY0": "LIOI3_IDELAY0_IFDLY0", + "DATAIN": "IOI_IDELAY0_DATAIN", + "LD": "IOI_IDELAY0_LD", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "IFDLY1": "LIOI3_IDELAY0_IFDLY1", + "IFDLY2": "LIOI3_IDELAY0_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2" + }, + "x_coord": 0 + } + ], + "wires": [ + "IOI_RCLK_DIV_CLR0_1", + "IOI_WL1END0_0", + "IOI_IDELAYCTRL_RST", + "LIOI_OLOGIC1_CLKDIVF", + "IOI_IMUX12_0", + "IOI_LH12_0", + "IOI_DCI_TSTHLN", + "IOI_IDELAYCTRL_OUTN1", + "IOI_EE2BEG2_0", + "IOI_SE4C2_0", + "IOI_OLOGIC0_D5", + "IOI_IOCLK1", + "IOI_IMUX2_0", + "IOI_WW4A3_0", + "IOI_OLOGIC1_SR", + "IOI_EL1BEG2_0", + "IOI_ILOGIC1_REV", + "IOI_EL1BEG2_1", + "LIOI_I2GCLK_TOP0", + "IOI_SE4BEG2_0", + "LIOI_OSOUT21", + "IOI_IDELAYCTRL_RDY", + "IOI_EE4A0_1", + "IOI_RCLK_DIV_CE1", + "LIOI_ILOGIC0_TFB", + "IOI_OLOGIC1_CLKB", + "LIOI_PD_INT_EN_0", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_LOGIC_OUTS8_1", + "IOI_SW4END2_0", + "IOI_IMUX_RC1", + "IOI_ODELAY1_CNTVALUEOUT2", + "LIOI_OLOGIC0_TQ", + "IOI_IMUX39_0", + "IOI_WW4B0_0", + "IOI_ER1BEG3_1", + "IOI_BYP1_1", + "IOI_IMUX5_1", + "IOI_PHASER_TO_IO_ICLKDIV_0", + "IOI_IMUX46_1", + "IOI_ILOGIC0_Q6", + "IOI_IMUX4_0", + "IOI_ODELAY1_CNTVALUEOUT4", + "LIOI_I0", + "IOI_NW4END3_1", + "IOI_ILOGIC1_OCLKB", + "IOI_FAN1_0", + "IOI_LOGIC_OUTS19_0", + "IOI_IMUX29_1", + "IOI_IMUX10_1", + "IOI_ILOGIC1_DYNCLKDIVPSEL", + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "IOI_ILOGIC1_Q1", + "IOI_OLOGIC1_D7", + "IOI_LH5_1", + "IOI_ODELAY0_REGRST", + "LIOI_T1", + "IOI_IOCLK2", + "IOI_WW4END0_0", + "IOI_WW4END2_1", + "IOI_IMUX32_1", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS20_0", + "IOI_PHASER_TO_IO_OCLK", + "IOI_LOGIC_OUTS5_1", + "IOI_RCLK_DIV_CE0", + "IOI_LOGIC_OUTS9_0", + "LIOI3_IDELAY0_IFDLY1", + "IOI_EE2A1_1", + "IOI_EE2A3_1", + "IOI_FAN6_0", + "IOI_WW2END1_0", + "IOI_IOCLK3", + "IOI_WW2END0_1", + "IOI_SE2A3_0", + "IOI_SE4C0_1", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_EE2A0_1", + "IOI_DCI_DCIDONE", + "IOI_IMUX25_0", + "IOI_LOGIC_OUTS8_0", + "IOI_ODELAY0_CLKIN", + "IOI_FAN4_1", + "IOI_BLOCK_OUTS2_0", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_NE4C2_1", + "IOI_IMUX44_0", + "IOI_IMUX29_0", + "IOI_WR1END2_1", + "IOI_OLOGIC0_CLKDIV", + "IOI_EE4C3_1", + "IOI_EE2BEG3_1", + "LIOI_ISIN21", + "IOI_IMUX22_0", + "IOI_ILOGIC0_REV", + "IOI_IMUX15_1", + "IOI_IMUX21_0", + "LIOI_OLOGIC1_OQ", + "IOI_BYP4_1", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_ODELAY0_LDPIPEEN", + "IOI_NE2A3_1", + "IOI_ILOGIC1_Q3", + "IOI_BYP2_1", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_WW4A2_0", + "IOI_NE4BEG1_0", + "IOI_LOGIC_OUTS18_1", + "IOI_OLOGIC0_D2", + "LIOI_ODELAY0_OFDLY1", + "IOI_ILOGIC0_Q7", + "IOI_ILOGIC1_CLK", + "IOI_ODELAY0_CNTVALUEOUT0", + "LIOI_I1", + "IOI_IDELAY0_REGRST", + "IOI_ODELAY1_INC", + "LIOI3_IDELAY0_IFDLY2", + "LIOI_I2GCLK_BOT1", + "IOI_SE4BEG1_1", + "IOI_IMUX33_1", + "IOI_WW4END3_0", + "IOI_WR1END1_1", + "IOI_ILOGIC1_CE2", + "IOI_SE4C0_0", + "IOI_LOGIC_OUTS21_1", + "IOI_ILOGIC0_CLKDIV", + "IOI_SE2A1_0", + "IOI_IMUX8_0", + "IOI_LH5_0", + "LIOI_ISOUT21", + "LIOI_KEEPER_INT_EN_1", + "IOI_IDELAYCTRL_OUTN65", + "IOI_NE2A1_1", + "IOI_EE4C3_0", + "IOI_LOGIC_OUTS14_1", + "IOI_OLOGIC0_CLKB", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_SE4BEG0_0", + "IOI_ILOGIC0_OCLKB", + "IOI_SE4C1_1", + "IOI_IMUX47_1", + "IOI_CLK1_1", + "IOI_IDELAY1_DATAIN", + "IOI_ODELAY1_CNTVALUEIN0", + "LIOI_OLOGIC0_TFB_LOCAL", + "IOI_IMUX28_0", + "IOI_LOGIC_OUTS6_1", + "IOI_SE2A2_1", + "IOI_LH9_0", + "IOI_EE2BEG3_0", + "LIOI_IDELAY0_DATAOUT", + "LIOI3_IDELAY1_IFDLY2", + "IOI_SE2A0_1", + "IOI_IMUX40_1", + "IOI_IMUX8_1", + "IOI_ILOGIC1_DYNCLKSEL", + "IOI_EE2BEG1_1", + "IOI_SW4END1_0", + "IOI_SW4A3_0", + "IOI_IMUX16_0", + "IOI_LOGIC_OUTS0_1", + "IOI_ER1BEG0_1", + "IOI_OLOGIC0_TCE", + "IOI_NW4A1_0", + "IOI_NW2A0_0", + "IOI_IDELAY1_CNTVALUEIN4", + "IOI_EL1BEG0_0", + "IOI_ILOGIC0_CE1", + "IOI_NW4A3_0", + "IOI_IDELAY1_CNTVALUEOUT1", + "IOI_SE2A2_0", + "IOI_WL1END1_1", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_ILOGIC1_O", + "IOI_IDELAY0_INC", + "IOI_IMUX28_1", + "IOI_WW4A1_0", + "IOI_IDELAY1_CNTVALUEOUT0", + "IOI_IMUX37_1", + "IOI_ODELAY1_CINVCTRL", + "IOI_MONITOR_P", + "IOI_EE4C0_1", + "IOI_OLOGIC1_TBYTEOUT", + "IOI_LEAF_GCLK0", + "IOI_LOGIC_OUTS7_1", + "LIOI_ISIN20", + "IOI_IMUX35_1", + "IOI_WW2END3_0", + "IOI_IDELAY1_CNTVALUEOUT4", + "IOI_EE4C2_1", + "IOI_NE4BEG2_1", + "IOI_SE4BEG3_0", + "IOI_ILOGIC1_Q6", + "IOI_ILOGIC0_Q4", + "IOI_SE4BEG0_1", + "IOI_RCLK_DIV_CE2_1", + "IOI_LOGIC_OUTS0_0", + "IOI_BYP4_0", + "LIOI3_IDELAY1_IFDLY1", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "IOI_OLOGIC0_D6", + "IOI_WL1END3_1", + "IOI_DCI_TSTCLK", + "IOI_WW4C2_1", + "IOI_WW4B1_0", + "IOI_PHASER_TO_IO_OCLK_0", + "IOI_PHASER_TO_IO_OCLKDIV_0", + "IOI_IMUX45_0", + "IOI_ILOGIC0_Q2", + "IOI_SW2A0_1", + "IOI_SE4BEG1_0", + "IOI_WW2A1_0", + "IOI_LOGIC_OUTS12_0", + "IOI_ILOGIC0_OCLK", + "IOI_EE4B3_0", + "IOI_WW4END1_1", + "IOI_IMUX19_0", + "IOI_NE4C2_0", + "IOI_OLOGIC0_CLK", + "IOI_WL1END1_0", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_IMUX_RC2", + "LIOI3_IDELAY1_IFDLY0", + "IOI_IMUX35_0", + "IOI_IMUX2_1", + "IOI_WW4A0_0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_IMUX15_0", + "IOI_WL1END2_0", + "IOI_WW2END3_1", + "IOI_IMUX41_1", + "IOI_WW4END1_0", + "LIOI_IDELAY1_DATAOUT", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS14_0", + "IOI_OLOGIC0_D7", + "IOI_IMUX31_1", + "IOI_SW2A3_0", + "LIOI_OLOGIC1_TQ", + "IOI_OLOGIC1_TBYTEIN", + "IOI_SW4A2_1", + "IOI_IDELAY1_LDPIPEEN", + "IOI_IMUX6_1", + "IOI_IMUX_RC0", + "LIOI_IDELAY0_IDATAIN", + "IOI_IMUX9_0", + "IOI_WW2END2_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_EE4BEG2_1", + "IOI_FAN6_1", + "IOI_ODELAY1_REGRST", + "IOI_IMUX11_0", + "LIOI_ISOUT11", + "IOI_RCLK_FORIO1", + "IOI_SW4A0_1", + "IOI_WW4C0_1", + "IOI_IMUX30_1", + "IOI_SE2A3_1", + "IOI_SW4A1_1", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OLOGIC1_D4", + "IOI_WW2A1_1", + "IOI_RCLK_DIV_CLR0", + "IOI_NW2A3_0", + "IOI_OLOGIC1_OCE", + "LIOI_ILOGIC1_D", + "IOI_IMUX40_0", + "IOI_SW4END0_1", + "IOI_SW4END1_1", + "IOI_ILOGIC1_Q4", + "IOI_LOGIC_OUTS16_1", + "IOI_IMUX20_1", + "IOI_NE4C1_1", + "IOI_ILOGIC1_CLKB", + "IOI_RCLK_DIV_CE3", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_LEAF_GCLK1", + "IOI_ILOGIC0_Q1", + "IOI_EE4BEG0_0", + "IOI_IMUX46_0", + "IOI_IMUX45_1", + "IOI_EE4BEG3_1", + "IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IMUX38_1", + "IOI_MONITOR_N", + "IOI_LEAF_GCLK5", + "IOI_WW4A3_1", + "IOI_ODELAY0_CNTVALUEIN2", + "IOI_NW4END3_0", + "IOI_WW2A3_1", + "LIOI_IBUF_DISABLE1", + "IOI_SE4BEG2_1", + "IOI_BYP5_1", + "IOI_ODELAY0_CINVCTRL", + "IOI_OLOGIC0_D1", + "IOI_WW4A2_1", + "LIOI_OSIN10", + "IOI_ODELAY1_CE", + "IOI_WW4C0_0", + "IOI_FAN1_1", + "IOI_IMUX26_0", + "LIOI_OLOGIC1_TFB", + "IOI_ODELAY0_LD", + "LIOI_ILOGIC1_DDLY", + "IOI_EE4B2_0", + "IOI_NW4A0_0", + "IOI_SE2A0_0", + "IOI_EE4C0_0", + "IOI_LOGIC_OUTS21_0", + "IOI_IDELAY0_LD", + "IOI_IMUX23_0", + "IOI_WR1END0_0", + "IOI_WW4END3_1", + "IOI_ODELAY1_CNTVALUEIN1", + "IOI_LOGIC_OUTS15_0", + "IOI_OLOGIC1_D1", + "IOI_LOGIC_OUTS23_0", + "IOI_WW2END2_1", + "IOI_DCI_TSTRST", + "IOI_IMUX22_1", + "IOI_LOGIC_OUTS1_1", + "IOI_EE4B1_0", + "IOI_IMUX7_0", + "IOI_EE4A2_1", + "IOI_BLOCK_OUTS1_0", + "IOI_IMUX42_0", + "IOI_SW2A2_1", + "IOI_WW4C1_0", + "IOI_OLOGIC0_REV", + "IOI_BYP0_1", + "IOI_IMUX39_1", + "IOI_NW4A0_1", + "IOI_BYP6_0", + "LIOI_IBUF0", + "IOI_IMUX13_1", + "IOI_OLOGIC0_D4", + "IOI_ODELAY0_CNTVALUEIN3", + "IOI_IMUX24_1", + "IOI_ILOGIC0_CLKDIVP", + "IOI_IMUX13_0", + "IOI_RCLK_DIV_CE2", + "IOI_IDELAY1_REGRST", + "LIOI_PU_INT_EN_1", + "IOI_WR1END3_1", + "IOI_IDELAY1_C", + "IOI_IDELAY1_LD", + "LIOI_IBUF1", + "IOI_IMUX47_0", + "IOI_ILOGIC0_O", + "IOI_ILOGIC1_Q8", + "IOI_BYP0_0", + "IOI_IMUX27_0", + "LIOI_O0", + "IOI_SW4END3_1", + "LIOI_ILOGIC1_TFB", + "IOI_LH1_0", + "IOI_SW4A0_0", + "IOI_SE4BEG3_1", + "LIOI_OSOUT20", + "IOI_IDELAY1_CNTVALUEIN0", + "IOI_SW4END0_0", + "IOI_WW4B1_1", + "LIOI_ISOUT10", + "IOI_IDELAY0_DATAIN", + "IOI_SW4A2_0", + "IOI_LOGIC_OUTS10_0", + "IOI_CLK0_1", + "IOI_IMUX11_1", + "IOI_WW4C1_1", + "IOI_OLOGIC0_T2", + "IOI_BYP6_1", + "IOI_LOGIC_OUTS2_0", + "IOI_BLOCK_OUTS0_0", + "IOI_NW4A3_1", + "IOI_ILOGIC1_BITSLIP", + "IOI_ODELAY0_CE", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_OLOGIC1_CLK", + "IOI_ILOGIC1_CLKDIV", + "IOI_IMUX20_0", + "IOI_LOGIC_OUTS10_1", + "LIOI_KEEPER_INT_EN_0", + "IOI_IDELAY0_LDPIPEEN", + "IOI_LOGIC_OUTS6_0", + "IOI_EL1BEG3_1", + "LIOI_ODELAY1_OFDLY1", + "LIOI_OSIN11", + "IOI_ILOGIC0_CLKB", + "IOI_LH6_0", + "IOI_EE4A2_0", + "IOI_LOGIC_OUTS22_0", + "IOI_NW2A1_0", + "IOI_WW2A0_0", + "IOI_PHASER_TO_IO_OCLK1X_90", + "LIOI_ILOGIC0_OFB", + "IOI_ILOGIC1_Q5", + "IOI_CTRL0_0", + "IOI_IDELAY0_CE", + "LIOI_OLOGIC0_OFB", + "IOI_ILOGIC0_BITSLIP", + "IOI_IMUX14_0", + "IOI_LOGIC_OUTS3_0", + "IOI_IMUX4_1", + "IOI_IMUX3_1", + "IOI_IMUX34_0", + "IOI_WL1END3_0", + "IOI_OLOGIC0_D8", + "IOI_IMUX17_1", + "IOI_OLOGIC1_TCE", + "IOI_LOGIC_OUTS4_1", + "IOI_OLOGIC0_T3", + "IOI_ILOGIC0_Q5", + "IOI_LOGIC_OUTS5_0", + "IOI_IMUX43_1", + "LIOI_OLOGIC0_CLKDIVF", + "IOI_ODELAY0_C", + "IOI_EE2BEG2_1", + "IOI_LOGIC_OUTS22_1", + "IOI_FAN3_0", + "IOI_SW2A3_1", + "LIOI_ODELAY0_OFDLY0", + "IOI_LOGIC_OUTS13_0", + "IOI_ODELAY1_LD", + "IOI_IDELAY1_CNTVALUEOUT3", + "IOI_ILOGIC1_Q2", + "IOI_ODELAY1_CNTVALUEIN3", + "IOI_EE4A3_1", + "IOI_WR1END3_0", + "IOI_IDELAY0_C", + "IOI_WW2END0_0", + "LIOI_ODELAY1_OFDLY2", + "IOI_FAN0_1", + "IOI_ILOGIC0_Q3", + "IOI_IDELAY0_CINVCTRL", + "IOI_NW2A1_1", + "IOI_IMUX26_1", + "IOI_EE2BEG1_0", + "IOI_OLOGIC1_IOCLKGLITCH", + "IOI_FAN3_1", + "IOI_NE2A0_1", + "LIOI_OLOGIC0_OQ", + "IOI_WR1END2_0", + "IOI_ODELAY1_CNTVALUEIN2", + "IOI_CTRL1_1", + "IOI_ODELAY0_INC", + "IOI_IMUX0_0", + "IOI_BYP3_1", + "IOI_IMUX19_1", + "IOI_LH7_0", + "IOI_SE4C2_1", + "IOI_BLOCK_OUTS2_1", + "IOI_WW4C2_0", + "IOI_NW2A2_0", + "IOI_NW4END2_1", + "IOI_NE4BEG1_1", + "LIOI_ISIN11", + "IOI_NW4A1_1", + "IOI_IMUX3_0", + "IOI_OLOGIC1_CLKDIV", + "IOI_LEAF_GCLK4", + "IOI_WW4C3_0", + "IOI_EL1BEG1_0", + "IOI_IMUX0_1", + "IOI_WR1END0_1", + "IOI_LH4_1", + "IOI_IDELAY1_CE", + "IOI_NE4C3_1", + "IOI_BLOCK_OUTS0_1", + "IOI_IDELAY1_CINVCTRL", + "IOI_LH3_0", + "IOI_NE2A1_0", + "IOI_IMUX43_0", + "IOI_RCLK_DIV_CLR2", + "IOI_NE4BEG3_1", + "IOI_IMUX_RC3", + "IOI_LOGIC_OUTS9_1", + "IOI_BLOCK_OUTS3_1", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_OLOGIC1_T3", + "IOI_NE4BEG0_0", + "IOI_NE4C1_0", + "IOI_IMUX38_0", + "IOI_LH10_1", + "IOI_IMUX34_1", + "IOI_SE4C3_0", + "IOI_ILOGIC1_Q7", + "IOI_EL1BEG3_0", + "IOI_LOGIC_OUTS11_0", + "IOI_EE4BEG1_0", + "IOI_FAN0_0", + "IOI_FAN2_1", + "IOI_IDELAY1_CNTVALUEIN2", + "LIOI_ODELAY0_OFDLY2", + "IOI_IMUX10_0", + "IOI_EE4B3_1", + "IOI_IMUX44_1", + "LIOI_ODELAY0_DATAOUT", + "IOI_WW2END1_1", + "IOI_IMUX31_0", + "IOI_ER1BEG1_0", + "IOI_NW2A2_1", + "IOI_WW4B3_0", + "IOI_RCLK_FORIO0", + "IOI_SE4C1_0", + "LIOI_PD_INT_EN_1", + "IOI_ILOGIC0_CE2", + "IOI_IMUX16_1", + "IOI_ODELAY1_CNTVALUEOUT0", + "IOI_FAN5_1", + "IOI_RCLK_DIV_CE3_1", + "IOI_FAN4_0", + "IOI_IMUX42_1", + "IOI_OLOGIC1_D2", + "IOI_IMUX17_0", + "IOI_WW4C3_1", + "IOI_OLOGIC0_CLKDIVB", + "IOI_LH12_1", + "IOI_EE4B1_1", + "IOI_TBYTEIN", + "IOI_NW4A2_0", + "IOI_LH2_1", + "IOI_EE4B0_0", + "IOI_EE4BEG0_1", + "LIOI_PU_INT_EN_0", + "IOI_OLOGIC1_REV", + "IOI_WW4B2_0", + "IOI_NE2A0_0", + "IOI_FAN5_0", + "IOI_IMUX36_0", + "IOI_NW4A2_1", + "LIOI_T0", + "IOI_IMUX33_0", + "IOI_BYP1_0", + "IOI_OLOGIC1_T2", + "IOI_RCLK_FORIO2", + "IOI_EE2A3_0", + "IOI_RCLK_DIV_CLR1", + "IOI_IDELAY1_CNTVALUEOUT2", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_NE2A2_1", + "LIOI_OLOGIC1_TFB_LOCAL", + "IOI_WW2A2_0", + "IOI_EE4A1_1", + "IOI_EE4B2_1", + "LIOI_ODELAY1_ODATAIN", + "IOI_LEAF_GCLK3", + "IOI_NW4END1_1", + "IOI_ODELAY1_CNTVALUEOUT1", + "IOI_WL1END2_1", + "IOI_LH3_1", + "IOI_LH6_1", + "IOI_RCLK_DIV_CLR3", + "IOI_EE4A0_0", + "IOI_CLK0_0", + "IOI_IMUX30_0", + "IOI_LH10_0", + "IOI_OLOGIC1_CLKDIVFB", + "LIOI_OLOGIC1_OFB", + "IOI_BYP5_0", + "IOI_BLOCK_OUTS3_0", + "IOI_SW4A3_1", + "IOI_CLK1_0", + "IOI_LOGIC_OUTS2_1", + "IOI_ILOGIC1_CLKDIVP", + "LIOI_I2GCLK_TOP1", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "LIOI_ODELAY0_ODATAIN", + "IOI_EL1BEG0_1", + "IOI_NE4C0_1", + "LIOI_OLOGIC0_TFB", + "IOI_WL1END0_1", + "IOI_IMUX32_0", + "IOI_ODELAY1_CNTVALUEOUT3", + "IOI_LOGIC_OUTS3_1", + "IOI_EE4BEG1_1", + "IOI_IMUX7_1", + "IOI_WW4B0_1", + "IOI_LOGIC_OUTS4_0", + "IOI_LOGIC_OUTS12_1", + "IOI_SW2A1_1", + "LIOI_ISIN10", + "IOI_ILOGIC1_CE1", + "IOI_WW4END0_1", + "IOI_IMUX18_0", + "IOI_RCLK_FORIO3", + "IOI_ODELAY1_LDPIPEEN", + "IOI_WW2A0_1", + "LIOI_OSOUT11", + "IOI_ER1BEG2_1", + "LIOI_ILOGIC1_OFB", + "IOI_IMUX25_1", + "IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_LH11_1", + "IOI_OLOGIC1_D6", + "IOI_IMUX1_1", + "IOI_LOGIC_OUTS15_1", + "IOI_IMUX12_1", + "IOI_SE4C3_1", + "IOI_WR1END1_0", + "IOI_LH8_1", + "IOI_SE2A1_1", + "IOI_EE4A1_0", + "IOI_SW4END3_0", + "IOI_LH1_1", + "IOI_LH8_0", + "IOI_DCI_TSTRST0", + "LIOI_IBUF_DISABLE0", + "IOI_LOGIC_OUTS23_1", + "IOI_LH2_0", + "IOI_BYP7_1", + "IOI_OCLKM_0", + "IOI_SW4END2_1", + "IOI_EE4A3_0", + "IOI_IMUX1_0", + "IOI_BYP3_0", + "IOI_NE2A2_0", + "IOI_ER1BEG0_0", + "IOI_NW4END2_0", + "IOI_ER1BEG3_0", + "IOI_EE2A2_1", + "IOI_FAN2_0", + "IOI_SW2A1_0", + "IOI_CTRL1_0", + "IOI_WW2A2_1", + "IOI_ODELAY1_CLKIN", + "IOI_OLOGIC0_OCE", + "IOI_OCLKM_1", + "IOI_IMUX41_0", + "IOI_NW2A0_1", + "IOI_IMUX24_0", + "LIOI_DIFF_TERM_INT_EN", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WW2A3_0", + "LIOI_ILOGIC0_DDLY", + "IOI_OLOGIC1_D3", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_LH9_1", + "IOI_IMUX5_0", + "IOI_OLOGIC1_T4", + "IOI_LOGIC_OUTS20_1", + "IOI_IMUX9_1", + "IOI_SW4A1_0", + "IOI_LH11_0", + "IOI_OLOGIC1_T1", + "IOI_EE4C1_0", + "IOI_IDELAY1_CNTVALUEIN1", + "LIOI_DCI_T_TERM0", + "IOI_BYP2_0", + "IOI_RCLK_DIV_CLR1_1", + "LIOI_IDELAY1_IDATAIN", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_WW4B3_1", + "IOI_EE4C1_1", + "IOI_ODELAY0_CNTVALUEIN0", + "IOI_WW4B2_1", + "IOI_IMUX36_1", + "IOI_BLOCK_OUTS1_1", + "IOI_LOGIC_OUTS18_0", + "IOI_IMUX27_1", + "IOI_EL1BEG1_1", + "IOI_LOGIC_OUTS16_0", + "IOI_PHASER_TO_IO_ICLKDIV", + "LIOI_ODELAY1_DATAOUT", + "LIOI_OSIN20", + "IOI_LOGIC_OUTS1_0", + "IOI_EE4BEG3_0", + "IOI_ER1BEG2_0", + "IOI_EE4BEG2_0", + "IOI_DCI_TSTHLP", + "IOI_EE2A0_0", + "IOI_WW4A0_1", + "IOI_LOGIC_OUTS11_1", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_IDELAY0_CNTVALUEIN0", + "IOI_IOCLK0", + "LIOI_OSIN21", + "IOI_IMUX37_0", + "IOI_OLOGIC1_D8", + "IOI_ODELAY1_CNTVALUEIN4", + "LIOI_ODELAY1_OFDLY0", + "LIOI_DCI_T_TERM1", + "IOI_LOGIC_OUTS7_0", + "IOI_NE4BEG2_0", + "IOI_EE2BEG0_0", + "IOI_ILOGIC1_SR", + "IOI_OLOGIC0_T1", + "IOI_OLOGIC1_CLKDIVB", + "IOI_NE4C3_0", + "IOI_ILOGIC0_SR", + "IOI_ODELAY1_C", + "IOI_EE2A2_0", + "IOI_IMUX6_0", + "IOI_LOGIC_OUTS13_1", + "LIOI_O1", + "IOI_LH7_1", + "IOI_NW4END0_0", + "IOI_NE2A3_0", + "IOI_NW2A3_1", + "IOI_LOGIC_OUTS19_1", + "IOI_LEAF_GCLK2", + "IOI_OLOGIC0_SR", + "IOI_EE2BEG0_1", + "IOI_NE4BEG3_0", + "IOI_ILOGIC0_Q8", + "IOI_INT_DCI_EN", + "IOI_SW2A0_0", + "IOI_ODELAY0_CNTVALUEIN4", + "IOI_WW4END2_0", + "IOI_FAN7_1", + "IOI_IMUX23_1", + "IOI_BYP7_0", + "IOI_IMUX18_1", + "IOI_ILOGIC1_DYNCLKDIVSEL", + "IOI_NW4END0_1", + "IOI_OCLK_1", + "IOI_IMUX21_1", + "IOI_FAN7_0", + "IOI_NW4END1_0", + "IOI_IDELAY1_CNTVALUEIN3", + "LIOI_OSOUT10", + "IOI_ILOGIC1_OCLK", + "IOI_LOGIC_OUTS17_0", + "IOI_NE4BEG0_1", + "IOI_PHASER_TO_IO_ICLK_0", + "IOI_EE4B0_1", + "IOI_OLOGIC0_D3", + "IOI_LOGIC_OUTS17_1", + "LIOI3_IDELAY0_IFDLY0", + "IOI_EE2A1_0", + "IOI_WW4A1_1", + "IOI_OLOGIC0_TBYTEIN", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_ER1BEG1_1", + "IOI_CTRL0_1", + "IOI_IMUX14_1", + "LIOI_ISOUT20", + "LIOI_ILOGIC0_D", + "IOI_OLOGIC1_D5", + "IOI_OCLK_0", + "IOI_IDELAY1_INC", + "IOI_NE4C0_0", + "IOI_LH4_0", + "IOI_OLOGIC0_T4" + ], + "pips": { + "LIOI3.IOI_CLK1_1->IOI_IDELAY0_C": { + "src_wire": "IOI_CLK1_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { + "src_wire": "IOI_ILOGIC0_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { + "src_wire": "IOI_BYP7_0", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { + "src_wire": "IOI_ILOGIC0_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "src_wire": "LIOI_ILOGIC0_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP3_1->IOI_IMUX_RC3": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC0_TQ->>LIOI_T0": { + "src_wire": "LIOI_OLOGIC0_TQ", + "is_pseudo": "0", + "dst_wire": "LIOI_T0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAYCTRL_RDY->IOI_LOGIC_OUTS22_1": { + "src_wire": "IOI_IDELAYCTRL_RDY", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS22_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX44_0->IOI_OLOGIC1_D3": { + "src_wire": "IOI_IMUX44_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { + "src_wire": "IOI_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX31_0->>IOI_OCLK_1": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX32_1->IOI_IDELAY0_CE": { + "src_wire": "IOI_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { + "src_wire": "IOI_BYP7_1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX26_0->IOI_IDELAY1_INC": { + "src_wire": "IOI_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_INC", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_CTRL0_0->IOI_OLOGIC1_SR": { + "src_wire": "IOI_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX13_1->IOI_OLOGIC0_T3": { + "src_wire": "IOI_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX46_0->IOI_OLOGIC1_D7": { + "src_wire": "IOI_IMUX46_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D7", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_IBUF0->LIOI_I0": { + "src_wire": "LIOI_IBUF0", + "is_pseudo": "0", + "dst_wire": "LIOI_I0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_CLK1_0->IOI_IDELAY1_C": { + "src_wire": "IOI_CLK1_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_C", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX7_1->IOI_OLOGIC0_T2": { + "src_wire": "IOI_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { + "src_wire": "IOI_ILOGIC1_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { + "src_wire": "IOI_FAN4_0", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR0_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX21_1->IOI_OLOGIC0_T4": { + "src_wire": "IOI_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { + "src_wire": "IOI_TBYTEIN", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX31_0->>IOI_OCLKM_1": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX26_1->IOI_IDELAY0_INC": { + "src_wire": "IOI_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP3_0->IOI_IMUX_RC0": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { + "src_wire": "IOI_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAYCTRL_OUTN1->IOI_LOGIC_OUTS13_1": { + "src_wire": "IOI_IDELAYCTRL_OUTN1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS13_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { + "src_wire": "IOI_ILOGIC1_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OQ": { + "src_wire": "IOI_OLOGIC1_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { + "src_wire": "IOI_FAN5_0", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { + "src_wire": "IOI_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX45_0->IOI_OLOGIC1_D6": { + "src_wire": "IOI_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D6", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX45_1->IOI_OLOGIC0_D6": { + "src_wire": "IOI_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { + "src_wire": "IOI_ILOGIC1_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TQ": { + "src_wire": "IOI_OLOGIC1_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR1_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { + "src_wire": "IOI_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC1_OQ->>LIOI_OLOGIC1_OFB": { + "src_wire": "LIOI_OLOGIC1_OQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { + "src_wire": "IOI_BYP6_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC1_TFB->LIOI_OLOGIC1_TFB_LOCAL": { + "src_wire": "LIOI_OLOGIC1_TFB", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { + "src_wire": "LIOI_OLOGIC0_OFB", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { + "src_wire": "IOI_TBYTEIN", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX32_0->IOI_IDELAY1_CE": { + "src_wire": "IOI_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX43_0->IOI_OLOGIC1_D5": { + "src_wire": "IOI_IMUX43_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D5", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { + "src_wire": "IOI_ILOGIC0_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX47_0->IOI_OLOGIC1_D8": { + "src_wire": "IOI_IMUX47_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D8", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { + "src_wire": "LIOI_ILOGIC1_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OFB": { + "src_wire": "IOI_OLOGIC1_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { + "src_wire": "IOI_FAN4_1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { + "src_wire": "IOI_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX43_1->IOI_OLOGIC0_D5": { + "src_wire": "IOI_IMUX43_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "src_wire": "LIOI_ILOGIC0_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { + "src_wire": "IOI_FAN5_1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { + "src_wire": "LIOI_OLOGIC0_TFB", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { + "src_wire": "IOI_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { + "src_wire": "IOI_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAYCTRL_OUTN65->IOI_LOGIC_OUTS16_1": { + "src_wire": "IOI_IDELAYCTRL_OUTN65", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS16_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_CTRL0_1->IOI_OLOGIC0_SR": { + "src_wire": "IOI_CTRL0_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX42_0->IOI_OLOGIC1_D4": { + "src_wire": "IOI_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX34_1->IOI_OLOGIC0_D1": { + "src_wire": "IOI_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { + "src_wire": "IOI_ILOGIC1_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { + "src_wire": "IOI_ILOGIC1_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX34_0->IOI_OLOGIC1_D1": { + "src_wire": "IOI_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_CLK0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX8_1->LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { + "src_wire": "IOI_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX13_0->IOI_OLOGIC1_T3": { + "src_wire": "IOI_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { + "src_wire": "IOI_ILOGIC1_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OSOUT11->LIOI_OSIN10": { + "src_wire": "LIOI_OSOUT11", + "is_pseudo": "0", + "dst_wire": "LIOI_OSIN10", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_I1->LIOI_IDELAY1_IDATAIN": { + "src_wire": "LIOI_I1", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY1_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { + "src_wire": "IOI_ILOGIC1_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX40_1->IOI_OLOGIC0_D2": { + "src_wire": "IOI_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAYCTRL_UPPULSEOUT->IOI_LOGIC_OUTS16_0": { + "src_wire": "IOI_IDELAYCTRL_UPPULSEOUT", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS16_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { + "src_wire": "IOI_ILOGIC0_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX31_1->>IOI_OCLK_0": { + "src_wire": "IOI_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { + "src_wire": "LIOI_IDELAY0_IDATAIN", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX7_0->IOI_OLOGIC1_T2": { + "src_wire": "IOI_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_IBUF1->LIOI_I1": { + "src_wire": "LIOI_IBUF1", + "is_pseudo": "0", + "dst_wire": "LIOI_I1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE2_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX46_1->IOI_OLOGIC0_D7": { + "src_wire": "IOI_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { + "src_wire": "IOI_ILOGIC0_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_IDELAY1_DATAOUT->LIOI_ILOGIC1_DDLY": { + "src_wire": "LIOI_IDELAY1_DATAOUT", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TFB": { + "src_wire": "IOI_OLOGIC1_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX15_0->IOI_OLOGIC1_T1": { + "src_wire": "IOI_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_CTRL1_0->IOI_ILOGIC1_SR": { + "src_wire": "IOI_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { + "src_wire": "IOI_ILOGIC0_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OSOUT21->LIOI_OSIN20": { + "src_wire": "LIOI_OSOUT21", + "is_pseudo": "0", + "dst_wire": "LIOI_OSIN20", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { + "src_wire": "IOI_CLK0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX40_0->IOI_OLOGIC1_D2": { + "src_wire": "IOI_IMUX40_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { + "src_wire": "IOI_ILOGIC0_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAYCTRL_DNPULSEOUT->IOI_LOGIC_OUTS13_0": { + "src_wire": "IOI_IDELAYCTRL_DNPULSEOUT", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS13_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC1_TQ->>LIOI_OLOGIC1_TFB": { + "src_wire": "LIOI_OLOGIC1_TQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC1_TFB_LOCAL->LIOI_ILOGIC1_TFB": { + "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { + "src_wire": "IOI_IMUX9_0", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_CTRL1_1->IOI_ILOGIC0_SR": { + "src_wire": "IOI_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { + "src_wire": "LIOI_OLOGIC0_OQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "src_wire": "IOI_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP4_0->IOI_IMUX_RC1": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { + "src_wire": "IOI_ILOGIC1_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX30_0->IOI_IDELAY1_LD": { + "src_wire": "IOI_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LD", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_I0->LIOI_ILOGIC0_D": { + "src_wire": "LIOI_I0", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_D", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { + "src_wire": "IOI_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { + "src_wire": "LIOI_ILOGIC1_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { + "src_wire": "IOI_ILOGIC1_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { + "src_wire": "IOI_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { + "src_wire": "IOI_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { + "src_wire": "IOI_ILOGIC0_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_ISOUT10->LIOI_ISIN11": { + "src_wire": "LIOI_ISOUT10", + "is_pseudo": "0", + "dst_wire": "LIOI_ISIN11", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX44_1->IOI_OLOGIC0_D3": { + "src_wire": "IOI_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC1_TQ->>LIOI_T1": { + "src_wire": "LIOI_OLOGIC1_TQ", + "is_pseudo": "0", + "dst_wire": "LIOI_T1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP4_1->IOI_IMUX_RC2": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX47_1->IOI_OLOGIC0_D8": { + "src_wire": "IOI_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX21_0->IOI_OLOGIC1_T4": { + "src_wire": "IOI_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC1_OQ->>LIOI_O1": { + "src_wire": "LIOI_OLOGIC1_OQ", + "is_pseudo": "0", + "dst_wire": "LIOI_O1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_IDELAY1_IDATAIN->>LIOI_IDELAY1_DATAOUT": { + "src_wire": "LIOI_IDELAY1_IDATAIN", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY1_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { + "src_wire": "IOI_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX42_1->IOI_OLOGIC0_D4": { + "src_wire": "IOI_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX24_0->IOI_IDELAYCTRL_RST": { + "src_wire": "IOI_IMUX24_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAYCTRL_RST", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC0_O->LIOI_I2GCLK_TOP0": { + "src_wire": "IOI_ILOGIC0_O", + "is_pseudo": "0", + "dst_wire": "LIOI_I2GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_ISOUT20->LIOI_ISIN21": { + "src_wire": "LIOI_ISOUT20", + "is_pseudo": "0", + "dst_wire": "LIOI_ISIN21", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { + "src_wire": "LIOI_OLOGIC0_TQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { + "src_wire": "IOI_BYP6_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE3_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK4->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { + "src_wire": "IOI_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { + "src_wire": "IOI_ILOGIC0_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { + "src_wire": "IOI_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { + "src_wire": "IOI_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLK": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { + "src_wire": "IOI_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC1_OFB->LIOI_ILOGIC1_OFB": { + "src_wire": "LIOI_OLOGIC1_OFB", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX15_1->IOI_OLOGIC0_T1": { + "src_wire": "IOI_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_I1->LIOI_ILOGIC1_D": { + "src_wire": "LIOI_I1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_D", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { + "src_wire": "LIOI_IDELAY0_DATAOUT", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLKM_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX31_1->>IOI_OCLKM_0": { + "src_wire": "IOI_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_I0->LIOI_IDELAY0_IDATAIN": { + "src_wire": "LIOI_I0", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLKM_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IOCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { + "src_wire": "IOI_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX30_1->IOI_IDELAY0_LD": { + "src_wire": "IOI_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.LIOI_OLOGIC0_OQ->>LIOI_O0": { + "src_wire": "LIOI_OLOGIC0_OQ", + "is_pseudo": "0", + "dst_wire": "LIOI_O0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { + "src_wire": "IOI_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_LIOI3_SING.json b/kintex7/tile_type_LIOI3_SING.json new file mode 100644 index 0000000..64e49e6 --- /dev/null +++ b/kintex7/tile_type_LIOI3_SING.json @@ -0,0 +1,1878 @@ +{ + "tile_type": "LIOI3_SING", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "OLOGIC", + "type": "OLOGICE3", + "site_pins": { + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "OFB": "LIOI_OLOGIC0_OFB", + "T1": "IOI_OLOGIC0_T1", + "D6": "IOI_OLOGIC0_D6", + "SHIFTIN2": null, + "TCE": "IOI_OLOGIC0_TCE", + "OCE": "IOI_OLOGIC0_OCE", + "SHIFTOUT2": "LIOI_OSOUT20", + "REV": null, + "OQ": "LIOI_OLOGIC0_OQ", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "TQ": "LIOI_OLOGIC0_TQ", + "D3": "IOI_OLOGIC0_D3", + "D4": "IOI_OLOGIC0_D4", + "SR": "IOI_OLOGIC0_SR", + "CLKB": "IOI_OLOGIC0_CLKB", + "SHIFTIN1": null, + "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF", + "D2": "IOI_OLOGIC0_D2", + "CLK": "IOI_OLOGIC0_CLK", + "T4": "IOI_OLOGIC0_T4", + "T2": "IOI_OLOGIC0_T2", + "TFB": "LIOI_OLOGIC0_TFB", + "SHIFTOUT1": "LIOI_OSOUT10", + "T3": "IOI_OLOGIC0_T3", + "D1": "IOI_OLOGIC0_D1", + "D5": "IOI_OLOGIC0_D5", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "D8": "IOI_OLOGIC0_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "ILOGIC", + "type": "ILOGICE3", + "site_pins": { + "Q4": "IOI_ILOGIC0_Q4", + "D": "LIOI_ILOGIC0_D", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN2": null, + "O": "IOI_ILOGIC0_O", + "Q6": "IOI_ILOGIC0_Q6", + "Q7": "IOI_ILOGIC0_Q7", + "TFB": "LIOI_ILOGIC0_TFB", + "Q2": "IOI_ILOGIC0_Q2", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "SHIFTIN1": null, + "Q8": "IOI_ILOGIC0_Q8", + "CE1": "IOI_ILOGIC0_CE1", + "CE2": "IOI_ILOGIC0_CE2", + "SR": "IOI_ILOGIC0_SR", + "Q3": "IOI_ILOGIC0_Q3", + "CLK": "IOI_ILOGIC0_CLK", + "OFB": "LIOI_ILOGIC0_OFB", + "DDLY": "LIOI_ILOGIC0_DDLY", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "CLKB": "IOI_ILOGIC0_CLKB", + "REV": null, + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "OCLKB": "IOI_ILOGIC0_OCLKB", + "SHIFTOUT1": "LIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "Q1": "IOI_ILOGIC0_Q1", + "SHIFTOUT2": "LIOI_ISOUT20" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IDELAY", + "type": "IDELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "DATAOUT": "LIOI_IDELAY0_DATAOUT", + "IDATAIN": "LIOI_IDELAY0_IDATAIN", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "C": "IOI_IDELAY0_C", + "IFDLY0": "LIOI3_IDELAY0_IFDLY0", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "LD": "IOI_IDELAY0_LD", + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "IFDLY1": "LIOI3_IDELAY0_IFDLY1", + "IFDLY2": "LIOI3_IDELAY0_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2" + }, + "x_coord": 0 + } + ], + "wires": [ + "IOI_WL1END0_0", + "IOI_IDELAY0_LDPIPEEN", + "IOI_LOGIC_OUTS6_0", + "IOI_IMUX12_0", + "IOI_ILOGIC0_CLKB", + "IOI_LH12_0", + "IOI_LH6_0", + "IOI_EE2BEG2_0", + "IOI_SE4C2_0", + "IOI_OLOGIC0_D5", + "IOI_IMUX2_0", + "IOI_EE4A2_0", + "IOI_WW4A3_0", + "IOI_LOGIC_OUTS22_0", + "IOI_NW2A1_0", + "IOI_WW2A0_0", + "IOI_EL1BEG2_0", + "IOI_PHASER_TO_IO_OCLK1X_90", + "LIOI_ILOGIC0_OFB", + "IOI_CTRL0_0", + "IOI_IDELAY0_CE", + "LIOI_OLOGIC0_OFB", + "IOI_SE4BEG2_0", + "IOI_ILOGIC0_BITSLIP", + "IOI_IMUX14_0", + "IOI_LOGIC_OUTS3_0", + "LIOI_ILOGIC0_TFB", + "IOI_IMUX34_0", + "IOI_WL1END3_0", + "IOI_OLOGIC0_D8", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_SW4END2_0", + "IOI_OLOGIC0_T3", + "IOI_LOGIC_OUTS5_0", + "IOI_ILOGIC0_Q5", + "LIOI_OLOGIC0_CLKDIVF", + "IOI_ODELAY0_C", + "LIOI_OLOGIC0_TQ", + "IOI_FAN3_0", + "LIOI_ODELAY0_OFDLY0", + "IOI_LOGIC_OUTS13_0", + "IOI_IMUX39_0", + "IOI_WW4B0_0", + "IOI_ILOGIC0_Q6", + "IOI_WR1END3_0", + "IOI_IDELAY0_C", + "LIOI_I0", + "IOI_IMUX4_0", + "IOI_WW2END0_0", + "IOI_FAN1_0", + "IOI_ILOGIC0_Q3", + "IOI_IDELAY0_CINVCTRL", + "IOI_LOGIC_OUTS19_0", + "IOI_EE2BEG1_0", + "LIOI_OLOGIC0_OQ", + "IOI_WR1END2_0", + "IOI_ODELAY0_REGRST", + "IOI_WW4END0_0", + "IOI_ODELAY0_INC", + "IOI_IMUX0_0", + "IOI_LH7_0", + "IOI_WW4C2_0", + "IOI_NW2A2_0", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS20_0", + "IOI_IMUX3_0", + "IOI_PHASER_TO_IO_OCLK", + "IOI_LOGIC_OUTS9_0", + "LIOI3_IDELAY0_IFDLY1", + "IOI_FAN6_0", + "IOI_WW4C3_0", + "IOI_WW2END1_0", + "IOI_EL1BEG1_0", + "IOI_SE2A3_0", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_LH3_0", + "IOI_IMUX25_0", + "IOI_NE2A1_0", + "IOI_LOGIC_OUTS8_0", + "IOI_ODELAY0_CLKIN", + "IOI_BLOCK_OUTS2_0", + "IOI_IMUX43_0", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_IMUX44_0", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_IMUX29_0", + "IOI_OLOGIC0_CLKDIV", + "IOI_IMUX22_0", + "IOI_NE4BEG0_0", + "IOI_NE4C1_0", + "IOI_ILOGIC0_REV", + "IOI_IMUX21_0", + "IOI_IMUX38_0", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_ODELAY0_LDPIPEEN", + "IOI_SE4C3_0", + "IOI_EL1BEG3_0", + "IOI_LOGIC_OUTS11_0", + "IOI_EE4BEG1_0", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_WW4A2_0", + "IOI_FAN0_0", + "IOI_NE4BEG1_0", + "IOI_SING_LEAF_GCLK1", + "IOI_OLOGIC0_D2", + "LIOI_ODELAY0_OFDLY1", + "IOI_ILOGIC0_Q7", + "IOI_ODELAY0_CNTVALUEOUT0", + "IOI_IDELAY0_REGRST", + "LIOI3_IDELAY0_IFDLY2", + "LIOI_ODELAY0_OFDLY2", + "IOI_IMUX10_0", + "LIOI_ODELAY0_DATAOUT", + "IOI_WW4END3_0", + "IOI_IMUX31_0", + "IOI_SE4C0_0", + "IOI_ER1BEG1_0", + "IOI_ILOGIC0_CLKDIV", + "IOI_SE2A1_0", + "IOI_IMUX8_0", + "IOI_LH5_0", + "LIOI_KEEPER_INT_EN_1", + "IOI_WW4B3_0", + "IOI_EE4C3_0", + "IOI_OLOGIC0_CLKB", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_SE4BEG0_0", + "IOI_SE4C1_0", + "LIOI_PD_INT_EN_1", + "IOI_ILOGIC0_CE2", + "IOI_FAN4_0", + "IOI_ILOGIC0_OCLKB", + "IOI_IMUX17_0", + "IOI_OLOGIC0_CLKDIVB", + "LIOI_OLOGIC0_TFB_LOCAL", + "IOI_IMUX28_0", + "IOI_NW4A2_0", + "IOI_LH9_0", + "IOI_EE4B0_0", + "IOI_EE2BEG3_0", + "LIOI_IDELAY0_DATAOUT", + "IOI_SING_IOCLK2", + "IOI_SW4END1_0", + "IOI_SW4A3_0", + "IOI_IMUX16_0", + "IOI_OLOGIC0_TCE", + "IOI_NW4A1_0", + "IOI_NW2A0_0", + "IOI_WW4B2_0", + "IOI_NE2A0_0", + "IOI_EL1BEG0_0", + "IOI_ILOGIC0_CE1", + "IOI_SING_IOCLK3", + "IOI_IMUX36_0", + "IOI_FAN5_0", + "IOI_NW4A3_0", + "LIOI_T0", + "IOI_SE2A2_0", + "IOI_IMUX33_0", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_BYP1_0", + "IOI_EE2A3_0", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_IDELAY0_INC", + "IOI_WW2A2_0", + "IOI_WW4A1_0", + "IOI_EE4A0_0", + "IOI_CLK0_0", + "IOI_IMUX30_0", + "IOI_LH10_0", + "LIOI_ISIN20", + "IOI_WW2END3_0", + "IOI_SING_IOCLK1", + "IOI_BYP5_0", + "IOI_BLOCK_OUTS3_0", + "IOI_CLK1_0", + "IOI_SE4BEG3_0", + "IOI_ILOGIC0_Q4", + "IOI_LOGIC_OUTS0_0", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "LIOI_ODELAY0_ODATAIN", + "IOI_BYP4_0", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "IOI_OLOGIC0_D6", + "IOI_WW4B1_0", + "LIOI_OLOGIC0_TFB", + "IOI_SING_RCLK_FORIO1", + "IOI_IMUX32_0", + "IOI_SING_LEAF_GCLK3", + "IOI_IMUX45_0", + "IOI_ILOGIC0_Q2", + "IOI_SE4BEG1_0", + "IOI_WW2A1_0", + "IOI_LOGIC_OUTS12_0", + "IOI_ILOGIC0_OCLK", + "IOI_LOGIC_OUTS4_0", + "IOI_EE4B3_0", + "IOI_IMUX19_0", + "IOI_NE4C2_0", + "IOI_OLOGIC0_CLK", + "IOI_WL1END1_0", + "IOI_OLOGIC0_CLKDIVFB", + "LIOI_ISIN10", + "IOI_IMUX35_0", + "IOI_WW4A0_0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_IMUX15_0", + "IOI_WL1END2_0", + "IOI_IMUX18_0", + "IOI_WW4END1_0", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS14_0", + "IOI_OLOGIC0_D7", + "IOI_SW2A3_0", + "IOI_SING_IOCLK0", + "LIOI_IDELAY0_IDATAIN", + "IOI_WR1END1_0", + "IOI_IMUX9_0", + "IOI_WW2END2_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_EE4A1_0", + "IOI_SW4END3_0", + "IOI_IMUX11_0", + "IOI_SING_LEAF_GCLK4", + "IOI_LH8_0", + "IOI_SING_TBYTEIN", + "LIOI_IBUF_DISABLE0", + "IOI_LH2_0", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OCLKM_0", + "IOI_EE4A3_0", + "IOI_IMUX1_0", + "IOI_BYP3_0", + "IOI_NE2A2_0", + "IOI_ER1BEG0_0", + "IOI_NW2A3_0", + "IOI_NW4END2_0", + "IOI_IMUX40_0", + "IOI_ER1BEG3_0", + "IOI_FAN2_0", + "IOI_SW2A1_0", + "IOI_SING_LEAF_GCLK2", + "IOI_CTRL1_0", + "IOI_SING_RCLK_FORIO3", + "IOI_OLOGIC0_OCE", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_ILOGIC0_Q1", + "IOI_SING_LEAF_GCLK0", + "IOI_EE4BEG0_0", + "IOI_IMUX41_0", + "IOI_IMUX24_0", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WW2A3_0", + "LIOI_ILOGIC0_DDLY", + "IOI_IMUX46_0", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_IMUX5_0", + "IOI_ODELAY0_CNTVALUEIN2", + "IOI_SW4A1_0", + "IOI_NW4END3_0", + "IOI_LH11_0", + "IOI_EE4C1_0", + "IOI_ODELAY0_CINVCTRL", + "IOI_OLOGIC0_D1", + "LIOI_DCI_T_TERM0", + "IOI_BYP2_0", + "LIOI_OSIN10", + "IOI_WW4C0_0", + "IOI_IMUX26_0", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_ODELAY0_LD", + "IOI_ODELAY0_CNTVALUEIN0", + "IOI_EE4B2_0", + "IOI_NW4A0_0", + "IOI_SE2A0_0", + "IOI_EE4C0_0", + "IOI_LOGIC_OUTS18_0", + "IOI_LOGIC_OUTS21_0", + "IOI_LOGIC_OUTS16_0", + "IOI_PHASER_TO_IO_ICLKDIV", + "IOI_IDELAY0_LD", + "IOI_IMUX23_0", + "LIOI_OSIN20", + "IOI_LOGIC_OUTS1_0", + "IOI_WR1END0_0", + "IOI_EE4BEG3_0", + "IOI_LOGIC_OUTS15_0", + "IOI_LOGIC_OUTS23_0", + "IOI_ER1BEG2_0", + "IOI_EE4BEG2_0", + "IOI_EE2A0_0", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_EE4B1_0", + "IOI_IMUX7_0", + "IOI_IDELAY0_CNTVALUEIN0", + "IOI_BLOCK_OUTS1_0", + "IOI_IMUX42_0", + "IOI_WW4C1_0", + "IOI_OLOGIC0_REV", + "IOI_IMUX37_0", + "IOI_BYP6_0", + "LIOI_IBUF0", + "IOI_SING_RCLK_FORIO0", + "IOI_LOGIC_OUTS7_0", + "IOI_NE4BEG2_0", + "IOI_OLOGIC0_D4", + "IOI_EE2BEG0_0", + "IOI_SING_RCLK_FORIO2", + "IOI_ODELAY0_CNTVALUEIN3", + "IOI_ILOGIC0_CLKDIVP", + "IOI_OLOGIC0_T1", + "IOI_IMUX13_0", + "IOI_NE4C3_0", + "IOI_ILOGIC0_SR", + "IOI_EE2A2_0", + "IOI_IMUX6_0", + "LIOI_PU_INT_EN_1", + "IOI_NW4END0_0", + "IOI_NE2A3_0", + "IOI_OLOGIC0_SR", + "IOI_IMUX47_0", + "IOI_NE4BEG3_0", + "IOI_ILOGIC0_Q8", + "IOI_ILOGIC0_O", + "IOI_BYP0_0", + "IOI_IMUX27_0", + "LIOI_O0", + "IOI_SW2A0_0", + "IOI_ODELAY0_CNTVALUEIN4", + "IOI_LH1_0", + "IOI_WW4END2_0", + "IOI_BYP7_0", + "IOI_SW4A0_0", + "LIOI_OSOUT20", + "IOI_SW4END0_0", + "IOI_FAN7_0", + "IOI_NW4END1_0", + "LIOI_ISOUT10", + "IOI_IDELAY0_DATAIN", + "IOI_SW4A2_0", + "LIOI_OSOUT10", + "IOI_LOGIC_OUTS10_0", + "IOI_LOGIC_OUTS17_0", + "IOI_OLOGIC0_D3", + "IOI_OLOGIC0_T2", + "IOI_SING_LEAF_GCLK5", + "LIOI3_IDELAY0_IFDLY0", + "IOI_EE2A1_0", + "IOI_OLOGIC0_TBYTEIN", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "LIOI_ISOUT20", + "IOI_LOGIC_OUTS2_0", + "IOI_BLOCK_OUTS0_0", + "LIOI_ILOGIC0_D", + "IOI_ODELAY0_CE", + "IOI_OCLK_0", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_NE4C0_0", + "IOI_IMUX20_0", + "IOI_LH4_0", + "IOI_OLOGIC0_T4" + ], + "pips": { + "LIOI3_SING.IOI_IMUX39_0->IOI_IDELAY0_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX26_0->IOI_IDELAY0_INC": { + "src_wire": "IOI_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX34_0->IOI_OLOGIC0_D1": { + "src_wire": "IOI_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLK_0": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { + "src_wire": "LIOI_IDELAY0_IDATAIN", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX46_0->IOI_OLOGIC0_D7": { + "src_wire": "IOI_IMUX46_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX14_0->IOI_ILOGIC0_CE2": { + "src_wire": "IOI_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX12_0->IOI_IDELAY0_REGRST": { + "src_wire": "IOI_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX1_0->IOI_OLOGIC0_TCE": { + "src_wire": "IOI_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { + "src_wire": "LIOI_OLOGIC0_TFB", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX31_0->>IOI_OCLKM_0": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_0": { + "src_wire": "IOI_ILOGIC0_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX37_0->IOI_ILOGIC0_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_SING_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX32_0->IOI_IDELAY0_CE": { + "src_wire": "IOI_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { + "src_wire": "LIOI_OLOGIC0_TQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX25_0->IOI_IDELAY0_DATAIN": { + "src_wire": "IOI_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX10_0->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX35_0->IOI_IDELAY0_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "src_wire": "LIOI_ILOGIC0_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX45_0->IOI_OLOGIC0_D6": { + "src_wire": "IOI_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLK_0": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "src_wire": "LIOI_ILOGIC0_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_FAN4_0->LIOI3_IDELAY0_IFDLY0": { + "src_wire": "IOI_FAN4_0", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_I0->LIOI_IDELAY0_IDATAIN": { + "src_wire": "LIOI_I0", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX13_0->IOI_OLOGIC0_T3": { + "src_wire": "IOI_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_BYP7_0->LIOI3_IDELAY0_IFDLY2": { + "src_wire": "IOI_BYP7_0", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_BYP6_0->IOI_IDELAY0_CINVCTRL": { + "src_wire": "IOI_BYP6_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_0": { + "src_wire": "IOI_ILOGIC0_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX29_0->IOI_OLOGIC0_OCE": { + "src_wire": "IOI_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { + "src_wire": "LIOI_IDELAY0_DATAOUT", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_FAN5_0->LIOI3_IDELAY0_IFDLY1": { + "src_wire": "IOI_FAN5_0", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX42_0->IOI_OLOGIC0_D4": { + "src_wire": "IOI_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_0": { + "src_wire": "IOI_ILOGIC0_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX33_0->IOI_IDELAY0_LDPIPEEN": { + "src_wire": "IOI_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLK_0": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_CTRL1_0->IOI_ILOGIC0_SR": { + "src_wire": "IOI_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX21_0->IOI_OLOGIC0_T4": { + "src_wire": "IOI_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX41_0->IOI_IDELAY0_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLK_0": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX30_0->IOI_IDELAY0_LD": { + "src_wire": "IOI_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_0": { + "src_wire": "IOI_ILOGIC0_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_CTRL0_0->IOI_OLOGIC0_SR": { + "src_wire": "IOI_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX44_0->IOI_OLOGIC0_D3": { + "src_wire": "IOI_IMUX44_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX38_0->IOI_IDELAY0_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_0": { + "src_wire": "IOI_ILOGIC0_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX15_0->IOI_OLOGIC0_T1": { + "src_wire": "IOI_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX6_0->LIOI_DCI_T_TERM0": { + "src_wire": "IOI_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX8_0->IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_IBUF0->LIOI_I0": { + "src_wire": "LIOI_IBUF0", + "is_pseudo": "0", + "dst_wire": "LIOI_I0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX40_0->IOI_OLOGIC0_D2": { + "src_wire": "IOI_IMUX40_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_SING_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_I0->LIOI_ILOGIC0_D": { + "src_wire": "LIOI_I0", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_D", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX0_0->IOI_ILOGIC0_BITSLIP": { + "src_wire": "IOI_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { + "src_wire": "LIOI_OLOGIC0_OQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX36_0->IOI_IDELAY0_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_0": { + "src_wire": "IOI_ILOGIC0_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX31_0->>IOI_OCLK_0": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX43_0->IOI_OLOGIC0_D5": { + "src_wire": "IOI_IMUX43_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX8_0->LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_SING_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIV": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX9_0->LIOI_IBUF_DISABLE0": { + "src_wire": "IOI_IMUX9_0", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX5_0->IOI_ILOGIC0_CE1": { + "src_wire": "IOI_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_0": { + "src_wire": "IOI_ILOGIC0_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_SING_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { + "src_wire": "IOI_SING_TBYTEIN", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_0": { + "src_wire": "IOI_ILOGIC0_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_CLK1_0->IOI_IDELAY0_C": { + "src_wire": "IOI_CLK1_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLK_0": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_OLOGIC0_OQ->>LIOI_O0": { + "src_wire": "LIOI_OLOGIC0_OQ", + "is_pseudo": "0", + "dst_wire": "LIOI_O0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX7_0->IOI_OLOGIC0_T2": { + "src_wire": "IOI_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_OLOGIC0_TQ->>LIOI_T0": { + "src_wire": "LIOI_OLOGIC0_TQ", + "is_pseudo": "0", + "dst_wire": "LIOI_T0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { + "src_wire": "LIOI_OLOGIC0_OFB", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX47_0->IOI_OLOGIC0_D8": { + "src_wire": "IOI_IMUX47_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX4_0->IOI_ILOGIC0_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_0": { + "src_wire": "IOI_ILOGIC0_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLK_0": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_LIOI3_TBYTESRC.json b/kintex7/tile_type_LIOI3_TBYTESRC.json new file mode 100644 index 0000000..e64d260 --- /dev/null +++ b/kintex7/tile_type_LIOI3_TBYTESRC.json @@ -0,0 +1,3893 @@ +{ + "tile_type": "LIOI3_TBYTESRC", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "OLOGIC", + "type": "OLOGICE3", + "site_pins": { + "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", + "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", + "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", + "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", + "OFB": "LIOI_OLOGIC1_OFB", + "T1": "IOI_OLOGIC1_T1", + "D6": "IOI_OLOGIC1_D6", + "SHIFTIN2": null, + "TCE": "IOI_OLOGIC1_TCE", + "OCE": "IOI_OLOGIC1_OCE", + "SHIFTOUT2": "LIOI_OSOUT21", + "REV": null, + "OQ": "LIOI_OLOGIC1_OQ", + "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", + "D7": "IOI_OLOGIC1_D7", + "TQ": "LIOI_OLOGIC1_TQ", + "D3": "IOI_OLOGIC1_D3", + "D4": "IOI_OLOGIC1_D4", + "SR": "IOI_OLOGIC1_SR", + "CLKB": "IOI_OLOGIC1_CLKB", + "SHIFTIN1": null, + "CLKDIVF": "LIOI_OLOGIC1_CLKDIVF", + "D2": "IOI_OLOGIC1_D2", + "CLK": "IOI_OLOGIC1_CLK", + "T4": "IOI_OLOGIC1_T4", + "T2": "IOI_OLOGIC1_T2", + "TFB": "LIOI_OLOGIC1_TFB", + "SHIFTOUT1": "LIOI_OSOUT11", + "T3": "IOI_OLOGIC1_T3", + "D1": "IOI_OLOGIC1_D1", + "D5": "IOI_OLOGIC1_D5", + "CLKDIV": "IOI_OLOGIC1_CLKDIV", + "D8": "IOI_OLOGIC1_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "ILOGIC", + "type": "ILOGICE3", + "site_pins": { + "Q4": "IOI_ILOGIC1_Q4", + "D": "LIOI_ILOGIC1_D", + "Q5": "IOI_ILOGIC1_Q5", + "SHIFTIN2": "LIOI_ISIN21", + "O": "IOI_ILOGIC1_O", + "Q6": "IOI_ILOGIC1_Q6", + "Q7": "IOI_ILOGIC1_Q7", + "TFB": "LIOI_ILOGIC1_TFB", + "Q2": "IOI_ILOGIC1_Q2", + "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", + "SHIFTIN1": "LIOI_ISIN11", + "Q8": "IOI_ILOGIC1_Q8", + "CE1": "IOI_ILOGIC1_CE1", + "CE2": "IOI_ILOGIC1_CE2", + "SR": "IOI_ILOGIC1_SR", + "Q3": "IOI_ILOGIC1_Q3", + "CLK": "IOI_ILOGIC1_CLK", + "OFB": "LIOI_ILOGIC1_OFB", + "DDLY": "LIOI_ILOGIC1_DDLY", + "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", + "CLKB": "IOI_ILOGIC1_CLKB", + "REV": null, + "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "CLKDIV": "IOI_ILOGIC1_CLKDIV", + "BITSLIP": "IOI_ILOGIC1_BITSLIP", + "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", + "OCLKB": "IOI_ILOGIC1_OCLKB", + "SHIFTOUT1": "LIOI_ISOUT11", + "OCLK": "IOI_ILOGIC1_OCLK", + "Q1": "IOI_ILOGIC1_Q1", + "SHIFTOUT2": "LIOI_ISOUT21" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "OLOGIC", + "type": "OLOGICE3", + "site_pins": { + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "OFB": "LIOI_OLOGIC0_OFB", + "T1": "IOI_OLOGIC0_T1", + "D6": "IOI_OLOGIC0_D6", + "SHIFTIN2": "LIOI_OSIN20", + "TCE": "IOI_OLOGIC0_TCE", + "OCE": "IOI_OLOGIC0_OCE", + "SHIFTOUT2": "LIOI_OSOUT20", + "REV": null, + "OQ": "LIOI_OLOGIC0_OQ", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "TQ": "LIOI_OLOGIC0_TQ", + "D3": "IOI_OLOGIC0_D3", + "D4": "IOI_OLOGIC0_D4", + "SR": "IOI_OLOGIC0_SR", + "CLKB": "IOI_OLOGIC0_CLKB", + "SHIFTIN1": "LIOI_OSIN10", + "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF", + "D2": "IOI_OLOGIC0_D2", + "CLK": "IOI_OLOGIC0_CLK", + "T4": "IOI_OLOGIC0_T4", + "T2": "IOI_OLOGIC0_T2", + "TFB": "LIOI_OLOGIC0_TFB", + "SHIFTOUT1": "LIOI_OSOUT10", + "T3": "IOI_OLOGIC0_T3", + "D1": "IOI_OLOGIC0_D1", + "D5": "IOI_OLOGIC0_D5", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "D8": "IOI_OLOGIC0_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "ILOGIC", + "type": "ILOGICE3", + "site_pins": { + "Q4": "IOI_ILOGIC0_Q4", + "D": "LIOI_ILOGIC0_D", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN2": null, + "O": "IOI_ILOGIC0_O", + "Q6": "IOI_ILOGIC0_Q6", + "Q7": "IOI_ILOGIC0_Q7", + "TFB": "LIOI_ILOGIC0_TFB", + "Q2": "IOI_ILOGIC0_Q2", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "SHIFTIN1": null, + "Q8": "IOI_ILOGIC0_Q8", + "CE1": "IOI_ILOGIC0_CE1", + "CE2": "IOI_ILOGIC0_CE2", + "SR": "IOI_ILOGIC0_SR", + "Q3": "IOI_ILOGIC0_Q3", + "CLK": "IOI_ILOGIC0_CLK", + "OFB": "LIOI_ILOGIC0_OFB", + "DDLY": "LIOI_ILOGIC0_DDLY", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "CLKB": "IOI_ILOGIC0_CLKB", + "REV": null, + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "OCLKB": "IOI_ILOGIC0_OCLKB", + "SHIFTOUT1": "LIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "Q1": "IOI_ILOGIC0_Q1", + "SHIFTOUT2": "LIOI_ISOUT20" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IDELAY", + "type": "IDELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", + "DATAOUT": "LIOI_IDELAY1_DATAOUT", + "IDATAIN": "LIOI_IDELAY1_IDATAIN", + "REGRST": "IOI_IDELAY1_REGRST", + "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", + "C": "IOI_IDELAY1_C", + "IFDLY0": "LIOI3_IDELAY1_IFDLY0", + "DATAIN": "IOI_IDELAY1_DATAIN", + "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", + "LD": "IOI_IDELAY1_LD", + "CINVCTRL": "IOI_IDELAY1_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", + "IFDLY1": "LIOI3_IDELAY1_IFDLY1", + "IFDLY2": "LIOI3_IDELAY1_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", + "INC": "IOI_IDELAY1_INC", + "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", + "CE": "IOI_IDELAY1_CE", + "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "IDELAY", + "type": "IDELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "DATAOUT": "LIOI_IDELAY0_DATAOUT", + "IDATAIN": "LIOI_IDELAY0_IDATAIN", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "C": "IOI_IDELAY0_C", + "IFDLY0": "LIOI3_IDELAY0_IFDLY0", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "LD": "IOI_IDELAY0_LD", + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "IFDLY1": "LIOI3_IDELAY0_IFDLY1", + "IFDLY2": "LIOI3_IDELAY0_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2" + }, + "x_coord": 0 + } + ], + "wires": [ + "IOI_RCLK_DIV_CLR0_1", + "IOI_WL1END0_0", + "IOI_IDELAYCTRL_RST", + "LIOI_OLOGIC1_CLKDIVF", + "IOI_IMUX12_0", + "IOI_LH12_0", + "IOI_DCI_TSTHLN", + "IOI_IDELAYCTRL_OUTN1", + "IOI_EE2BEG2_0", + "IOI_SE4C2_0", + "IOI_OLOGIC0_D5", + "IOI_IOCLK1", + "IOI_IMUX2_0", + "IOI_WW4A3_0", + "IOI_OLOGIC1_SR", + "IOI_EL1BEG2_0", + "IOI_ILOGIC1_REV", + "IOI_EL1BEG2_1", + "LIOI_I2GCLK_TOP0", + "IOI_SE4BEG2_0", + "LIOI_OSOUT21", + "IOI_IDELAYCTRL_RDY", + "IOI_EE4A0_1", + "IOI_RCLK_DIV_CE1", + "LIOI_ILOGIC0_TFB", + "IOI_OLOGIC1_CLKB", + "LIOI_PD_INT_EN_0", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_LOGIC_OUTS8_1", + "IOI_SW4END2_0", + "IOI_IMUX_RC1", + "IOI_ODELAY1_CNTVALUEOUT2", + "LIOI_OLOGIC0_TQ", + "IOI_IMUX39_0", + "IOI_WW4B0_0", + "IOI_ER1BEG3_1", + "IOI_BYP1_1", + "IOI_IMUX5_1", + "IOI_PHASER_TO_IO_ICLKDIV_0", + "IOI_IMUX46_1", + "IOI_ILOGIC0_Q6", + "IOI_IMUX4_0", + "IOI_ODELAY1_CNTVALUEOUT4", + "LIOI_I0", + "IOI_NW4END3_1", + "IOI_ILOGIC1_OCLKB", + "IOI_FAN1_0", + "IOI_LOGIC_OUTS19_0", + "IOI_IMUX29_1", + "IOI_IMUX10_1", + "IOI_ILOGIC1_DYNCLKDIVPSEL", + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "IOI_ILOGIC1_Q1", + "IOI_OLOGIC1_D7", + "IOI_LH5_1", + "IOI_ODELAY0_REGRST", + "LIOI_T1", + "IOI_IOCLK2", + "IOI_WW4END0_0", + "IOI_WW4END2_1", + "IOI_IMUX32_1", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS20_0", + "IOI_PHASER_TO_IO_OCLK", + "IOI_LOGIC_OUTS5_1", + "IOI_RCLK_DIV_CE0", + "IOI_LOGIC_OUTS9_0", + "LIOI3_IDELAY0_IFDLY1", + "IOI_EE2A1_1", + "IOI_EE2A3_1", + "IOI_FAN6_0", + "IOI_WW2END1_0", + "IOI_IOCLK3", + "IOI_WW2END0_1", + "IOI_SE2A3_0", + "IOI_SE4C0_1", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_EE2A0_1", + "IOI_DCI_DCIDONE", + "IOI_IMUX25_0", + "IOI_LOGIC_OUTS8_0", + "IOI_ODELAY0_CLKIN", + "IOI_BLOCK_OUTS2_0", + "IOI_FAN4_1", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_NE4C2_1", + "IOI_IMUX44_0", + "IOI_IMUX29_0", + "IOI_WR1END2_1", + "IOI_OLOGIC0_CLKDIV", + "IOI_EE4C3_1", + "IOI_EE2BEG3_1", + "IOI_IMUX22_0", + "LIOI_ISIN21", + "IOI_ILOGIC0_REV", + "IOI_IMUX21_0", + "IOI_IMUX15_1", + "LIOI_OLOGIC1_OQ", + "IOI_BYP4_1", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_ODELAY0_LDPIPEEN", + "IOI_NE2A3_1", + "IOI_ILOGIC1_Q3", + "IOI_BYP2_1", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_WW4A2_0", + "IOI_NE4BEG1_0", + "IOI_LOGIC_OUTS18_1", + "IOI_OLOGIC0_D2", + "LIOI_ODELAY0_OFDLY1", + "IOI_ILOGIC0_Q7", + "IOI_ILOGIC1_CLK", + "IOI_ODELAY0_CNTVALUEOUT0", + "LIOI_I1", + "IOI_IDELAY0_REGRST", + "IOI_ODELAY1_INC", + "LIOI3_IDELAY0_IFDLY2", + "LIOI_I2GCLK_BOT1", + "IOI_SE4BEG1_1", + "IOI_IMUX33_1", + "IOI_WW4END3_0", + "IOI_WR1END1_1", + "IOI_ILOGIC1_CE2", + "IOI_SE4C0_0", + "IOI_LOGIC_OUTS21_1", + "IOI_ILOGIC0_CLKDIV", + "IOI_SE2A1_0", + "IOI_IMUX8_0", + "IOI_LH5_0", + "LIOI_ISOUT21", + "LIOI_KEEPER_INT_EN_1", + "IOI_IDELAYCTRL_OUTN65", + "IOI_NE2A1_1", + "IOI_EE4C3_0", + "IOI_LOGIC_OUTS14_1", + "IOI_OLOGIC0_CLKB", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_SE4BEG0_0", + "IOI_ILOGIC0_OCLKB", + "IOI_SE4C1_1", + "IOI_IMUX47_1", + "IOI_CLK1_1", + "IOI_IDELAY1_DATAIN", + "IOI_ODELAY1_CNTVALUEIN0", + "LIOI_OLOGIC0_TFB_LOCAL", + "IOI_IMUX28_0", + "IOI_LOGIC_OUTS6_1", + "IOI_SE2A2_1", + "IOI_LH9_0", + "IOI_EE2BEG3_0", + "LIOI_IDELAY0_DATAOUT", + "LIOI3_IDELAY1_IFDLY2", + "IOI_SE2A0_1", + "IOI_IMUX40_1", + "IOI_IMUX8_1", + "IOI_ILOGIC1_DYNCLKSEL", + "IOI_EE2BEG1_1", + "IOI_SW4END1_0", + "IOI_SW4A3_0", + "IOI_IMUX16_0", + "IOI_LOGIC_OUTS0_1", + "IOI_ER1BEG0_1", + "IOI_OLOGIC0_TCE", + "IOI_NW4A1_0", + "IOI_NW2A0_0", + "IOI_IDELAY1_CNTVALUEIN4", + "IOI_EL1BEG0_0", + "IOI_ILOGIC0_CE1", + "IOI_NW4A3_0", + "IOI_IDELAY1_CNTVALUEOUT1", + "IOI_SE2A2_0", + "IOI_WL1END1_1", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_ILOGIC1_O", + "IOI_IDELAY0_INC", + "IOI_IMUX28_1", + "IOI_WW4A1_0", + "IOI_IDELAY1_CNTVALUEOUT0", + "IOI_IMUX37_1", + "IOI_ODELAY1_CINVCTRL", + "IOI_MONITOR_P", + "IOI_EE4C0_1", + "IOI_OLOGIC1_TBYTEOUT", + "IOI_LEAF_GCLK0", + "IOI_LOGIC_OUTS7_1", + "LIOI_ISIN20", + "IOI_IMUX35_1", + "IOI_WW2END3_0", + "IOI_IDELAY1_CNTVALUEOUT4", + "IOI_EE4C2_1", + "IOI_NE4BEG2_1", + "IOI_SE4BEG3_0", + "IOI_ILOGIC1_Q6", + "IOI_ILOGIC0_Q4", + "IOI_SE4BEG0_1", + "IOI_RCLK_DIV_CE2_1", + "IOI_LOGIC_OUTS0_0", + "IOI_BYP4_0", + "LIOI3_IDELAY1_IFDLY1", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "IOI_OLOGIC0_D6", + "IOI_WL1END3_1", + "IOI_DCI_TSTCLK", + "IOI_WW4B1_0", + "IOI_WW4C2_1", + "IOI_PHASER_TO_IO_OCLK_0", + "IOI_PHASER_TO_IO_OCLKDIV_0", + "IOI_IMUX45_0", + "IOI_ILOGIC0_Q2", + "IOI_SW2A0_1", + "IOI_SE4BEG1_0", + "IOI_WW2A1_0", + "IOI_LOGIC_OUTS12_0", + "IOI_ILOGIC0_OCLK", + "IOI_EE4B3_0", + "IOI_WW4END1_1", + "IOI_IMUX19_0", + "IOI_NE4C2_0", + "IOI_OLOGIC0_CLK", + "IOI_WL1END1_0", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_IMUX_RC2", + "LIOI3_IDELAY1_IFDLY0", + "IOI_IMUX35_0", + "IOI_IMUX2_1", + "IOI_WW4A0_0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_IMUX15_0", + "IOI_WL1END2_0", + "IOI_WW2END3_1", + "IOI_IMUX41_1", + "IOI_WW4END1_0", + "LIOI_IDELAY1_DATAOUT", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS14_0", + "IOI_OLOGIC0_D7", + "IOI_IMUX31_1", + "IOI_SW2A3_0", + "LIOI_OLOGIC1_TQ", + "IOI_OLOGIC1_TBYTEIN", + "IOI_SW4A2_1", + "IOI_IDELAY1_LDPIPEEN", + "IOI_IMUX6_1", + "IOI_IMUX_RC0", + "LIOI_IDELAY0_IDATAIN", + "IOI_IMUX9_0", + "IOI_WW2END2_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_EE4BEG2_1", + "IOI_FAN6_1", + "IOI_ODELAY1_REGRST", + "IOI_IMUX11_0", + "LIOI_ISOUT11", + "IOI_RCLK_FORIO1", + "IOI_SW4A0_1", + "IOI_WW4C0_1", + "IOI_IMUX30_1", + "IOI_SE2A3_1", + "IOI_SW4A1_1", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OLOGIC1_D4", + "IOI_WW2A1_1", + "IOI_RCLK_DIV_CLR0", + "IOI_NW2A3_0", + "IOI_OLOGIC1_OCE", + "LIOI_ILOGIC1_D", + "IOI_IMUX40_0", + "IOI_SW4END0_1", + "IOI_SW4END1_1", + "IOI_ILOGIC1_Q4", + "IOI_LOGIC_OUTS16_1", + "IOI_IMUX20_1", + "IOI_NE4C1_1", + "IOI_ILOGIC1_CLKB", + "IOI_RCLK_DIV_CE3", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_LEAF_GCLK1", + "IOI_ILOGIC0_Q1", + "IOI_EE4BEG0_0", + "IOI_IMUX46_0", + "IOI_IMUX45_1", + "IOI_EE4BEG3_1", + "IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IMUX38_1", + "IOI_MONITOR_N", + "IOI_LEAF_GCLK5", + "IOI_WW4A3_1", + "IOI_ODELAY0_CNTVALUEIN2", + "IOI_NW4END3_0", + "IOI_WW2A3_1", + "LIOI_IBUF_DISABLE1", + "IOI_SE4BEG2_1", + "IOI_BYP5_1", + "IOI_ODELAY0_CINVCTRL", + "IOI_OLOGIC0_D1", + "IOI_WW4A2_1", + "LIOI_OSIN10", + "IOI_ODELAY1_CE", + "IOI_WW4C0_0", + "IOI_FAN1_1", + "IOI_IMUX26_0", + "LIOI_OLOGIC1_TFB", + "IOI_ODELAY0_LD", + "LIOI_ILOGIC1_DDLY", + "IOI_EE4B2_0", + "IOI_NW4A0_0", + "IOI_SE2A0_0", + "IOI_EE4C0_0", + "IOI_LOGIC_OUTS21_0", + "IOI_IDELAY0_LD", + "IOI_IMUX23_0", + "IOI_WR1END0_0", + "IOI_WW4END3_1", + "IOI_ODELAY1_CNTVALUEIN1", + "IOI_LOGIC_OUTS15_0", + "IOI_OLOGIC1_D1", + "IOI_LOGIC_OUTS23_0", + "IOI_WW2END2_1", + "IOI_DCI_TSTRST", + "IOI_IMUX22_1", + "IOI_LOGIC_OUTS1_1", + "IOI_EE4B1_0", + "IOI_IMUX7_0", + "IOI_EE4A2_1", + "IOI_BLOCK_OUTS1_0", + "IOI_IMUX42_0", + "IOI_SW2A2_1", + "IOI_WW4C1_0", + "IOI_OLOGIC0_REV", + "IOI_BYP0_1", + "IOI_IMUX39_1", + "IOI_NW4A0_1", + "IOI_BYP6_0", + "LIOI_IBUF0", + "IOI_IMUX13_1", + "IOI_OLOGIC0_D4", + "IOI_ODELAY0_CNTVALUEIN3", + "IOI_IMUX24_1", + "IOI_ILOGIC0_CLKDIVP", + "IOI_IMUX13_0", + "IOI_RCLK_DIV_CE2", + "IOI_IDELAY1_REGRST", + "LIOI_PU_INT_EN_1", + "IOI_WR1END3_1", + "IOI_IDELAY1_C", + "IOI_IDELAY1_LD", + "LIOI_IBUF1", + "IOI_IMUX47_0", + "IOI_ILOGIC0_O", + "IOI_ILOGIC1_Q8", + "IOI_BYP0_0", + "IOI_IMUX27_0", + "LIOI_O0", + "IOI_SW4END3_1", + "LIOI_ILOGIC1_TFB", + "IOI_LH1_0", + "IOI_SW4A0_0", + "IOI_SE4BEG3_1", + "LIOI_OSOUT20", + "IOI_IDELAY1_CNTVALUEIN0", + "IOI_SW4END0_0", + "IOI_WW4B1_1", + "LIOI_ISOUT10", + "IOI_IDELAY0_DATAIN", + "IOI_SW4A2_0", + "IOI_LOGIC_OUTS10_0", + "IOI_CLK0_1", + "IOI_IMUX11_1", + "IOI_WW4C1_1", + "IOI_OLOGIC0_T2", + "IOI_BYP6_1", + "IOI_LOGIC_OUTS2_0", + "IOI_BLOCK_OUTS0_0", + "IOI_NW4A3_1", + "IOI_ILOGIC1_BITSLIP", + "IOI_ODELAY0_CE", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_OLOGIC1_CLK", + "IOI_ILOGIC1_CLKDIV", + "IOI_IMUX20_0", + "IOI_LOGIC_OUTS10_1", + "LIOI_KEEPER_INT_EN_0", + "IOI_IDELAY0_LDPIPEEN", + "IOI_LOGIC_OUTS6_0", + "IOI_EL1BEG3_1", + "LIOI_ODELAY1_OFDLY1", + "LIOI_OSIN11", + "IOI_ILOGIC0_CLKB", + "IOI_LH6_0", + "IOI_EE4A2_0", + "IOI_LOGIC_OUTS22_0", + "IOI_NW2A1_0", + "IOI_WW2A0_0", + "IOI_PHASER_TO_IO_OCLK1X_90", + "LIOI_ILOGIC0_OFB", + "IOI_ILOGIC1_Q5", + "IOI_CTRL0_0", + "IOI_IDELAY0_CE", + "LIOI_OLOGIC0_OFB", + "IOI_ILOGIC0_BITSLIP", + "IOI_IMUX14_0", + "IOI_LOGIC_OUTS3_0", + "IOI_IMUX4_1", + "IOI_IMUX3_1", + "IOI_IMUX34_0", + "IOI_WL1END3_0", + "IOI_OLOGIC0_D8", + "IOI_IMUX17_1", + "IOI_OLOGIC1_TCE", + "IOI_LOGIC_OUTS4_1", + "IOI_OLOGIC0_T3", + "IOI_LOGIC_OUTS5_0", + "IOI_ILOGIC0_Q5", + "IOI_IMUX43_1", + "LIOI_OLOGIC0_CLKDIVF", + "IOI_ODELAY0_C", + "IOI_EE2BEG2_1", + "IOI_LOGIC_OUTS22_1", + "IOI_FAN3_0", + "IOI_SW2A3_1", + "LIOI_ODELAY0_OFDLY0", + "IOI_LOGIC_OUTS13_0", + "IOI_ODELAY1_LD", + "IOI_IDELAY1_CNTVALUEOUT3", + "IOI_ILOGIC1_Q2", + "IOI_ODELAY1_CNTVALUEIN3", + "IOI_EE4A3_1", + "IOI_WR1END3_0", + "IOI_IDELAY0_C", + "IOI_WW2END0_0", + "LIOI_ODELAY1_OFDLY2", + "IOI_FAN0_1", + "IOI_ILOGIC0_Q3", + "IOI_IDELAY0_CINVCTRL", + "IOI_NW2A1_1", + "IOI_IMUX26_1", + "IOI_EE2BEG1_0", + "IOI_OLOGIC1_IOCLKGLITCH", + "IOI_FAN3_1", + "IOI_NE2A0_1", + "LIOI_OLOGIC0_OQ", + "IOI_WR1END2_0", + "IOI_ODELAY1_CNTVALUEIN2", + "IOI_CTRL1_1", + "IOI_ODELAY0_INC", + "IOI_IMUX0_0", + "IOI_BYP3_1", + "IOI_IMUX19_1", + "IOI_LH7_0", + "IOI_SE4C2_1", + "IOI_BLOCK_OUTS2_1", + "IOI_WW4C2_0", + "IOI_NW2A2_0", + "IOI_NW4END2_1", + "IOI_NE4BEG1_1", + "LIOI_ISIN11", + "IOI_NW4A1_1", + "IOI_IMUX3_0", + "IOI_OLOGIC1_CLKDIV", + "IOI_LEAF_GCLK4", + "IOI_WW4C3_0", + "IOI_EL1BEG1_0", + "IOI_IMUX0_1", + "IOI_WR1END0_1", + "IOI_LH4_1", + "IOI_IDELAY1_CE", + "IOI_NE4C3_1", + "IOI_BLOCK_OUTS0_1", + "IOI_IDELAY1_CINVCTRL", + "IOI_LH3_0", + "IOI_NE2A1_0", + "IOI_IMUX43_0", + "IOI_RCLK_DIV_CLR2", + "IOI_NE4BEG3_1", + "IOI_IMUX_RC3", + "IOI_LOGIC_OUTS9_1", + "IOI_BLOCK_OUTS3_1", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_OLOGIC1_T3", + "IOI_NE4BEG0_0", + "IOI_NE4C1_0", + "IOI_IMUX38_0", + "IOI_LH10_1", + "IOI_IMUX34_1", + "IOI_SE4C3_0", + "IOI_ILOGIC1_Q7", + "IOI_EL1BEG3_0", + "IOI_LOGIC_OUTS11_0", + "IOI_EE4BEG1_0", + "IOI_FAN0_0", + "IOI_FAN2_1", + "IOI_IDELAY1_CNTVALUEIN2", + "LIOI_ODELAY0_OFDLY2", + "IOI_IMUX10_0", + "IOI_EE4B3_1", + "IOI_IMUX44_1", + "LIOI_ODELAY0_DATAOUT", + "IOI_WW2END1_1", + "IOI_IMUX31_0", + "IOI_ER1BEG1_0", + "IOI_NW2A2_1", + "IOI_WW4B3_0", + "IOI_RCLK_FORIO0", + "IOI_SE4C1_0", + "LIOI_PD_INT_EN_1", + "IOI_ILOGIC0_CE2", + "IOI_IMUX16_1", + "IOI_ODELAY1_CNTVALUEOUT0", + "IOI_FAN5_1", + "IOI_RCLK_DIV_CE3_1", + "IOI_FAN4_0", + "IOI_IMUX42_1", + "IOI_OLOGIC1_D2", + "IOI_IMUX17_0", + "IOI_WW4C3_1", + "IOI_OLOGIC0_CLKDIVB", + "IOI_LH12_1", + "IOI_EE4B1_1", + "IOI_TBYTEIN", + "IOI_NW4A2_0", + "IOI_LH2_1", + "IOI_EE4B0_0", + "IOI_EE4BEG0_1", + "LIOI_PU_INT_EN_0", + "IOI_OLOGIC1_REV", + "IOI_WW4B2_0", + "IOI_NE2A0_0", + "IOI_FAN5_0", + "IOI_IMUX36_0", + "IOI_NW4A2_1", + "LIOI_T0", + "IOI_IMUX33_0", + "IOI_BYP1_0", + "IOI_OLOGIC1_T2", + "IOI_RCLK_FORIO2", + "IOI_EE2A3_0", + "IOI_RCLK_DIV_CLR1", + "IOI_IDELAY1_CNTVALUEOUT2", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_NE2A2_1", + "LIOI_OLOGIC1_TFB_LOCAL", + "IOI_WW2A2_0", + "IOI_EE4A1_1", + "IOI_EE4B2_1", + "LIOI_ODELAY1_ODATAIN", + "IOI_LEAF_GCLK3", + "IOI_NW4END1_1", + "IOI_ODELAY1_CNTVALUEOUT1", + "IOI_WL1END2_1", + "IOI_LH3_1", + "IOI_LH6_1", + "IOI_RCLK_DIV_CLR3", + "IOI_EE4A0_0", + "IOI_CLK0_0", + "IOI_IMUX30_0", + "IOI_LH10_0", + "IOI_OLOGIC1_CLKDIVFB", + "LIOI_OLOGIC1_OFB", + "IOI_BYP5_0", + "IOI_BLOCK_OUTS3_0", + "IOI_SW4A3_1", + "IOI_CLK1_0", + "IOI_LOGIC_OUTS2_1", + "IOI_ILOGIC1_CLKDIVP", + "LIOI_I2GCLK_TOP1", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "LIOI_ODELAY0_ODATAIN", + "IOI_EL1BEG0_1", + "IOI_NE4C0_1", + "LIOI_OLOGIC0_TFB", + "IOI_WL1END0_1", + "IOI_IMUX32_0", + "IOI_ODELAY1_CNTVALUEOUT3", + "IOI_LOGIC_OUTS3_1", + "IOI_EE4BEG1_1", + "IOI_IMUX7_1", + "IOI_WW4B0_1", + "IOI_LOGIC_OUTS4_0", + "IOI_LOGIC_OUTS12_1", + "IOI_SW2A1_1", + "LIOI_ISIN10", + "IOI_ILOGIC1_CE1", + "IOI_WW4END0_1", + "IOI_IMUX18_0", + "IOI_RCLK_FORIO3", + "IOI_ODELAY1_LDPIPEEN", + "IOI_WW2A0_1", + "LIOI_OSOUT11", + "IOI_ER1BEG2_1", + "LIOI_ILOGIC1_OFB", + "IOI_IMUX25_1", + "IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_LH11_1", + "IOI_OLOGIC1_D6", + "IOI_LOGIC_OUTS15_1", + "IOI_IMUX1_1", + "IOI_IMUX12_1", + "IOI_SE4C3_1", + "IOI_WR1END1_0", + "IOI_LH8_1", + "IOI_SE2A1_1", + "IOI_EE4A1_0", + "IOI_SW4END3_0", + "IOI_LH1_1", + "IOI_LH8_0", + "IOI_DCI_TSTRST0", + "LIOI_IBUF_DISABLE0", + "IOI_LOGIC_OUTS23_1", + "IOI_LH2_0", + "IOI_BYP7_1", + "IOI_OCLKM_0", + "IOI_SW4END2_1", + "IOI_EE4A3_0", + "IOI_IMUX1_0", + "IOI_BYP3_0", + "IOI_NE2A2_0", + "IOI_ER1BEG0_0", + "IOI_NW4END2_0", + "IOI_ER1BEG3_0", + "IOI_EE2A2_1", + "IOI_FAN2_0", + "IOI_SW2A1_0", + "IOI_CTRL1_0", + "IOI_WW2A2_1", + "IOI_ODELAY1_CLKIN", + "IOI_OLOGIC0_OCE", + "IOI_OCLKM_1", + "IOI_IMUX41_0", + "IOI_NW2A0_1", + "IOI_IMUX24_0", + "LIOI_DIFF_TERM_INT_EN", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WW2A3_0", + "LIOI_ILOGIC0_DDLY", + "IOI_OLOGIC1_D3", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_LH9_1", + "IOI_IMUX5_0", + "IOI_OLOGIC1_T4", + "IOI_LOGIC_OUTS20_1", + "IOI_IMUX9_1", + "IOI_SW4A1_0", + "IOI_LH11_0", + "IOI_OLOGIC1_T1", + "IOI_EE4C1_0", + "IOI_IDELAY1_CNTVALUEIN1", + "LIOI_DCI_T_TERM0", + "IOI_BYP2_0", + "IOI_RCLK_DIV_CLR1_1", + "LIOI_IDELAY1_IDATAIN", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_WW4B3_1", + "IOI_EE4C1_1", + "IOI_ODELAY0_CNTVALUEIN0", + "IOI_WW4B2_1", + "IOI_IMUX36_1", + "IOI_BLOCK_OUTS1_1", + "IOI_LOGIC_OUTS18_0", + "IOI_IMUX27_1", + "IOI_EL1BEG1_1", + "IOI_LOGIC_OUTS16_0", + "IOI_PHASER_TO_IO_ICLKDIV", + "LIOI_ODELAY1_DATAOUT", + "LIOI_OSIN20", + "IOI_LOGIC_OUTS1_0", + "IOI_EE4BEG3_0", + "IOI_ER1BEG2_0", + "IOI_EE4BEG2_0", + "IOI_DCI_TSTHLP", + "IOI_EE2A0_0", + "IOI_WW4A0_1", + "IOI_LOGIC_OUTS11_1", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_IDELAY0_CNTVALUEIN0", + "IOI_IOCLK0", + "LIOI_OSIN21", + "IOI_IMUX37_0", + "IOI_OLOGIC1_D8", + "IOI_ODELAY1_CNTVALUEIN4", + "LIOI_ODELAY1_OFDLY0", + "LIOI_DCI_T_TERM1", + "IOI_LOGIC_OUTS7_0", + "IOI_NE4BEG2_0", + "IOI_EE2BEG0_0", + "IOI_ILOGIC1_SR", + "IOI_OLOGIC0_T1", + "IOI_OLOGIC1_CLKDIVB", + "IOI_NE4C3_0", + "IOI_ILOGIC0_SR", + "IOI_ODELAY1_C", + "IOI_EE2A2_0", + "IOI_IMUX6_0", + "IOI_LOGIC_OUTS13_1", + "LIOI_O1", + "IOI_LH7_1", + "IOI_NW4END0_0", + "IOI_NE2A3_0", + "IOI_NW2A3_1", + "IOI_LOGIC_OUTS19_1", + "IOI_LEAF_GCLK2", + "IOI_OLOGIC0_SR", + "IOI_EE2BEG0_1", + "IOI_NE4BEG3_0", + "IOI_ILOGIC0_Q8", + "IOI_INT_DCI_EN", + "IOI_SW2A0_0", + "IOI_ODELAY0_CNTVALUEIN4", + "IOI_WW4END2_0", + "IOI_FAN7_1", + "IOI_IMUX23_1", + "IOI_BYP7_0", + "IOI_IMUX18_1", + "IOI_ILOGIC1_DYNCLKDIVSEL", + "IOI_NW4END0_1", + "IOI_OCLK_1", + "IOI_IMUX21_1", + "IOI_FAN7_0", + "IOI_NW4END1_0", + "IOI_IDELAY1_CNTVALUEIN3", + "LIOI_OSOUT10", + "IOI_ILOGIC1_OCLK", + "IOI_LOGIC_OUTS17_0", + "IOI_NE4BEG0_1", + "IOI_PHASER_TO_IO_ICLK_0", + "IOI_EE4B0_1", + "IOI_OLOGIC0_D3", + "IOI_LOGIC_OUTS17_1", + "LIOI3_IDELAY0_IFDLY0", + "IOI_EE2A1_0", + "IOI_WW4A1_1", + "IOI_OLOGIC0_TBYTEIN", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_ER1BEG1_1", + "IOI_CTRL0_1", + "IOI_IMUX14_1", + "LIOI_ISOUT20", + "LIOI_ILOGIC0_D", + "IOI_OLOGIC1_D5", + "IOI_OCLK_0", + "IOI_IDELAY1_INC", + "IOI_NE4C0_0", + "IOI_LH4_0", + "IOI_OLOGIC0_T4" + ], + "pips": { + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX45_0->IOI_OLOGIC1_D6": { + "src_wire": "IOI_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D6", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { + "src_wire": "IOI_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { + "src_wire": "IOI_ILOGIC1_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { + "src_wire": "IOI_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_OQ->>LIOI_OLOGIC1_OFB": { + "src_wire": "LIOI_OLOGIC1_OQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX46_1->IOI_OLOGIC0_D7": { + "src_wire": "IOI_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { + "src_wire": "IOI_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { + "src_wire": "IOI_ILOGIC0_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { + "src_wire": "IOI_FAN5_0", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX45_1->IOI_OLOGIC0_D6": { + "src_wire": "IOI_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR0_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { + "src_wire": "IOI_TBYTEIN", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLKM_1": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { + "src_wire": "IOI_ILOGIC0_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { + "src_wire": "LIOI_OLOGIC0_OQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "src_wire": "LIOI_ILOGIC0_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX7_1->IOI_OLOGIC0_T2": { + "src_wire": "IOI_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR1_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX30_1->IOI_IDELAY0_LD": { + "src_wire": "IOI_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_TQ->>LIOI_T0": { + "src_wire": "LIOI_OLOGIC0_TQ", + "is_pseudo": "0", + "dst_wire": "LIOI_T0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE3_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLKM_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_IMUX_RC0": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { + "src_wire": "LIOI_ILOGIC1_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_I0->LIOI_IDELAY0_IDATAIN": { + "src_wire": "LIOI_I0", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { + "src_wire": "IOI_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { + "src_wire": "LIOI_OLOGIC0_OFB", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_IDELAY1_IDATAIN->>LIOI_IDELAY1_DATAOUT": { + "src_wire": "LIOI_IDELAY1_IDATAIN", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY1_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { + "src_wire": "IOI_ILOGIC0_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { + "src_wire": "IOI_ILOGIC0_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { + "src_wire": "IOI_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX34_0->IOI_OLOGIC1_D1": { + "src_wire": "IOI_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OFB": { + "src_wire": "IOI_OLOGIC1_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_TFB_LOCAL->LIOI_ILOGIC1_TFB": { + "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLK_1": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX13_0->IOI_OLOGIC1_T3": { + "src_wire": "IOI_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { + "src_wire": "IOI_BYP6_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_TQ->>LIOI_OLOGIC1_TFB": { + "src_wire": "LIOI_OLOGIC1_TQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "src_wire": "LIOI_ILOGIC0_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX42_0->IOI_OLOGIC1_D4": { + "src_wire": "IOI_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_OFB->LIOI_ILOGIC1_OFB": { + "src_wire": "LIOI_OLOGIC1_OFB", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_TFB->LIOI_OLOGIC1_TFB_LOCAL": { + "src_wire": "LIOI_OLOGIC1_TFB", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX32_0->IOI_IDELAY1_CE": { + "src_wire": "IOI_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX34_1->IOI_OLOGIC0_D1": { + "src_wire": "IOI_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { + "src_wire": "IOI_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX40_1->IOI_OLOGIC0_D2": { + "src_wire": "IOI_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_IDELAY1_DATAOUT->LIOI_ILOGIC1_DDLY": { + "src_wire": "LIOI_IDELAY1_DATAOUT", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX40_0->IOI_OLOGIC1_D2": { + "src_wire": "IOI_IMUX40_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_CTRL1_0->IOI_ILOGIC1_SR": { + "src_wire": "IOI_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { + "src_wire": "IOI_ILOGIC1_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { + "src_wire": "IOI_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OSOUT11->LIOI_OSIN10": { + "src_wire": "LIOI_OSOUT11", + "is_pseudo": "0", + "dst_wire": "LIOI_OSIN10", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { + "src_wire": "LIOI_OLOGIC0_TQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX32_1->IOI_IDELAY0_CE": { + "src_wire": "IOI_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX21_0->IOI_OLOGIC1_T4": { + "src_wire": "IOI_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OSOUT21->LIOI_OSIN20": { + "src_wire": "LIOI_OSOUT21", + "is_pseudo": "0", + "dst_wire": "LIOI_OSIN20", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_I0->LIOI_ILOGIC0_D": { + "src_wire": "LIOI_I0", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_D", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { + "src_wire": "IOI_FAN4_1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { + "src_wire": "IOI_BYP7_1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { + "src_wire": "IOI_BYP7_0", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { + "src_wire": "IOI_ILOGIC0_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_IMUX_RC1": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_CTRL0_0->IOI_OLOGIC1_SR": { + "src_wire": "IOI_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLK": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { + "src_wire": "IOI_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { + "src_wire": "IOI_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX43_0->IOI_OLOGIC1_D5": { + "src_wire": "IOI_IMUX43_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D5", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { + "src_wire": "IOI_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TQ": { + "src_wire": "IOI_OLOGIC1_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_TQ->>LIOI_T1": { + "src_wire": "LIOI_OLOGIC1_TQ", + "is_pseudo": "0", + "dst_wire": "LIOI_T1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { + "src_wire": "IOI_ILOGIC1_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX44_1->IOI_OLOGIC0_D3": { + "src_wire": "IOI_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_IMUX_RC3": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_OQ->>LIOI_O0": { + "src_wire": "LIOI_OLOGIC0_OQ", + "is_pseudo": "0", + "dst_wire": "LIOI_O0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { + "src_wire": "IOI_ILOGIC1_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { + "src_wire": "IOI_BYP6_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX47_1->IOI_OLOGIC0_D8": { + "src_wire": "IOI_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC1_TBYTEOUT->>IOI_TBYTEIN": { + "src_wire": "IOI_OLOGIC1_TBYTEOUT", + "is_pseudo": "0", + "dst_wire": "IOI_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { + "src_wire": "IOI_ILOGIC0_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { + "src_wire": "IOI_FAN5_1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { + "src_wire": "IOI_ILOGIC1_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_CLK0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { + "src_wire": "IOI_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_O->LIOI_I2GCLK_TOP0": { + "src_wire": "IOI_ILOGIC0_O", + "is_pseudo": "0", + "dst_wire": "LIOI_I2GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TFB": { + "src_wire": "IOI_OLOGIC1_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "src_wire": "IOI_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { + "src_wire": "IOI_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_ISOUT10->LIOI_ISIN11": { + "src_wire": "LIOI_ISOUT10", + "is_pseudo": "0", + "dst_wire": "LIOI_ISIN11", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX46_0->IOI_OLOGIC1_D7": { + "src_wire": "IOI_IMUX46_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D7", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX15_0->IOI_OLOGIC1_T1": { + "src_wire": "IOI_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_CTRL0_1->IOI_OLOGIC0_SR": { + "src_wire": "IOI_CTRL0_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX26_1->IOI_IDELAY0_INC": { + "src_wire": "IOI_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE2_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX42_1->IOI_OLOGIC0_D4": { + "src_wire": "IOI_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { + "src_wire": "IOI_ILOGIC0_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { + "src_wire": "IOI_ILOGIC1_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { + "src_wire": "IOI_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_ISOUT20->LIOI_ISIN21": { + "src_wire": "LIOI_ISOUT20", + "is_pseudo": "0", + "dst_wire": "LIOI_ISIN21", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { + "src_wire": "IOI_ILOGIC0_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { + "src_wire": "IOI_IMUX9_0", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX15_1->IOI_OLOGIC0_T1": { + "src_wire": "IOI_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { + "src_wire": "IOI_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_IMUX_RC2": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_CLK1_0->IOI_IDELAY1_C": { + "src_wire": "IOI_CLK1_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_C", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_1->LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_IBUF0->LIOI_I0": { + "src_wire": "LIOI_IBUF0", + "is_pseudo": "0", + "dst_wire": "LIOI_I0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLKM_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { + "src_wire": "LIOI_IDELAY0_IDATAIN", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_CLK1_1->IOI_IDELAY0_C": { + "src_wire": "IOI_CLK1_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_OQ->>LIOI_O1": { + "src_wire": "LIOI_OLOGIC1_OQ", + "is_pseudo": "0", + "dst_wire": "LIOI_O1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX7_0->IOI_OLOGIC1_T2": { + "src_wire": "IOI_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { + "src_wire": "LIOI_IDELAY0_DATAOUT", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX47_0->IOI_OLOGIC1_D8": { + "src_wire": "IOI_IMUX47_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D8", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { + "src_wire": "IOI_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { + "src_wire": "IOI_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX44_0->IOI_OLOGIC1_D3": { + "src_wire": "IOI_IMUX44_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { + "src_wire": "IOI_ILOGIC0_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { + "src_wire": "IOI_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { + "src_wire": "IOI_TBYTEIN", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { + "src_wire": "IOI_ILOGIC1_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OQ": { + "src_wire": "IOI_OLOGIC1_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_CTRL1_1->IOI_ILOGIC0_SR": { + "src_wire": "IOI_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLKM_0": { + "src_wire": "IOI_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX30_0->IOI_IDELAY1_LD": { + "src_wire": "IOI_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LD", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLK_0": { + "src_wire": "IOI_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { + "src_wire": "IOI_CLK0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_IBUF1->LIOI_I1": { + "src_wire": "LIOI_IBUF1", + "is_pseudo": "0", + "dst_wire": "LIOI_I1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { + "src_wire": "IOI_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX43_1->IOI_OLOGIC0_D5": { + "src_wire": "IOI_IMUX43_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { + "src_wire": "IOI_FAN4_0", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX21_1->IOI_OLOGIC0_T4": { + "src_wire": "IOI_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_I1->LIOI_IDELAY1_IDATAIN": { + "src_wire": "LIOI_I1", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY1_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { + "src_wire": "LIOI_ILOGIC1_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { + "src_wire": "IOI_ILOGIC1_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX13_1->IOI_OLOGIC0_T3": { + "src_wire": "IOI_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { + "src_wire": "IOI_ILOGIC1_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { + "src_wire": "LIOI_OLOGIC0_TFB", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.LIOI_I1->LIOI_ILOGIC1_D": { + "src_wire": "LIOI_I1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_D", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTESRC.IOI_IMUX26_0->IOI_IDELAY1_INC": { + "src_wire": "IOI_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_INC", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_LIOI3_TBYTETERM.json b/kintex7/tile_type_LIOI3_TBYTETERM.json new file mode 100644 index 0000000..da5282b --- /dev/null +++ b/kintex7/tile_type_LIOI3_TBYTETERM.json @@ -0,0 +1,3879 @@ +{ + "tile_type": "LIOI3_TBYTETERM", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "OLOGIC", + "type": "OLOGICE3", + "site_pins": { + "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", + "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", + "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", + "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", + "OFB": "LIOI_OLOGIC1_OFB", + "T1": "IOI_OLOGIC1_T1", + "D6": "IOI_OLOGIC1_D6", + "SHIFTIN2": null, + "TCE": "IOI_OLOGIC1_TCE", + "OCE": "IOI_OLOGIC1_OCE", + "SHIFTOUT2": "LIOI_OSOUT21", + "REV": null, + "OQ": "LIOI_OLOGIC1_OQ", + "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", + "D7": "IOI_OLOGIC1_D7", + "TQ": "LIOI_OLOGIC1_TQ", + "D3": "IOI_OLOGIC1_D3", + "D4": "IOI_OLOGIC1_D4", + "SR": "IOI_OLOGIC1_SR", + "CLKB": "IOI_OLOGIC1_CLKB", + "SHIFTIN1": null, + "CLKDIVF": "LIOI_OLOGIC1_CLKDIVF", + "D2": "IOI_OLOGIC1_D2", + "CLK": "IOI_OLOGIC1_CLK", + "T4": "IOI_OLOGIC1_T4", + "T2": "IOI_OLOGIC1_T2", + "TFB": "LIOI_OLOGIC1_TFB", + "SHIFTOUT1": "LIOI_OSOUT11", + "T3": "IOI_OLOGIC1_T3", + "D1": "IOI_OLOGIC1_D1", + "D5": "IOI_OLOGIC1_D5", + "CLKDIV": "IOI_OLOGIC1_CLKDIV", + "D8": "IOI_OLOGIC1_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "ILOGIC", + "type": "ILOGICE3", + "site_pins": { + "Q4": "IOI_ILOGIC1_Q4", + "D": "LIOI_ILOGIC1_D", + "Q5": "IOI_ILOGIC1_Q5", + "SHIFTIN2": "LIOI_ISIN21", + "O": "IOI_ILOGIC1_O", + "Q6": "IOI_ILOGIC1_Q6", + "Q7": "IOI_ILOGIC1_Q7", + "TFB": "LIOI_ILOGIC1_TFB", + "Q2": "IOI_ILOGIC1_Q2", + "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", + "SHIFTIN1": "LIOI_ISIN11", + "Q8": "IOI_ILOGIC1_Q8", + "CE1": "IOI_ILOGIC1_CE1", + "CE2": "IOI_ILOGIC1_CE2", + "SR": "IOI_ILOGIC1_SR", + "Q3": "IOI_ILOGIC1_Q3", + "CLK": "IOI_ILOGIC1_CLK", + "OFB": "LIOI_ILOGIC1_OFB", + "DDLY": "LIOI_ILOGIC1_DDLY", + "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", + "CLKB": "IOI_ILOGIC1_CLKB", + "REV": null, + "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "CLKDIV": "IOI_ILOGIC1_CLKDIV", + "BITSLIP": "IOI_ILOGIC1_BITSLIP", + "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", + "OCLKB": "IOI_ILOGIC1_OCLKB", + "SHIFTOUT1": "LIOI_ISOUT11", + "OCLK": "IOI_ILOGIC1_OCLK", + "Q1": "IOI_ILOGIC1_Q1", + "SHIFTOUT2": "LIOI_ISOUT21" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "OLOGIC", + "type": "OLOGICE3", + "site_pins": { + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "OFB": "LIOI_OLOGIC0_OFB", + "T1": "IOI_OLOGIC0_T1", + "D6": "IOI_OLOGIC0_D6", + "SHIFTIN2": "LIOI_OSIN20", + "TCE": "IOI_OLOGIC0_TCE", + "OCE": "IOI_OLOGIC0_OCE", + "SHIFTOUT2": "LIOI_OSOUT20", + "REV": null, + "OQ": "LIOI_OLOGIC0_OQ", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "TQ": "LIOI_OLOGIC0_TQ", + "D3": "IOI_OLOGIC0_D3", + "D4": "IOI_OLOGIC0_D4", + "SR": "IOI_OLOGIC0_SR", + "CLKB": "IOI_OLOGIC0_CLKB", + "SHIFTIN1": "LIOI_OSIN10", + "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF", + "D2": "IOI_OLOGIC0_D2", + "CLK": "IOI_OLOGIC0_CLK", + "T4": "IOI_OLOGIC0_T4", + "T2": "IOI_OLOGIC0_T2", + "TFB": "LIOI_OLOGIC0_TFB", + "SHIFTOUT1": "LIOI_OSOUT10", + "T3": "IOI_OLOGIC0_T3", + "D1": "IOI_OLOGIC0_D1", + "D5": "IOI_OLOGIC0_D5", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "D8": "IOI_OLOGIC0_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "ILOGIC", + "type": "ILOGICE3", + "site_pins": { + "Q4": "IOI_ILOGIC0_Q4", + "D": "LIOI_ILOGIC0_D", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN2": null, + "O": "IOI_ILOGIC0_O", + "Q6": "IOI_ILOGIC0_Q6", + "Q7": "IOI_ILOGIC0_Q7", + "TFB": "LIOI_ILOGIC0_TFB", + "Q2": "IOI_ILOGIC0_Q2", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "SHIFTIN1": null, + "Q8": "IOI_ILOGIC0_Q8", + "CE1": "IOI_ILOGIC0_CE1", + "CE2": "IOI_ILOGIC0_CE2", + "SR": "IOI_ILOGIC0_SR", + "Q3": "IOI_ILOGIC0_Q3", + "CLK": "IOI_ILOGIC0_CLK", + "OFB": "LIOI_ILOGIC0_OFB", + "DDLY": "LIOI_ILOGIC0_DDLY", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "CLKB": "IOI_ILOGIC0_CLKB", + "REV": null, + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "OCLKB": "IOI_ILOGIC0_OCLKB", + "SHIFTOUT1": "LIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "Q1": "IOI_ILOGIC0_Q1", + "SHIFTOUT2": "LIOI_ISOUT20" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IDELAY", + "type": "IDELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", + "DATAOUT": "LIOI_IDELAY1_DATAOUT", + "IDATAIN": "LIOI_IDELAY1_IDATAIN", + "REGRST": "IOI_IDELAY1_REGRST", + "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", + "C": "IOI_IDELAY1_C", + "IFDLY0": "LIOI3_IDELAY1_IFDLY0", + "DATAIN": "IOI_IDELAY1_DATAIN", + "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", + "LD": "IOI_IDELAY1_LD", + "CINVCTRL": "IOI_IDELAY1_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", + "IFDLY1": "LIOI3_IDELAY1_IFDLY1", + "IFDLY2": "LIOI3_IDELAY1_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", + "INC": "IOI_IDELAY1_INC", + "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", + "CE": "IOI_IDELAY1_CE", + "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "IDELAY", + "type": "IDELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "DATAOUT": "LIOI_IDELAY0_DATAOUT", + "IDATAIN": "LIOI_IDELAY0_IDATAIN", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "C": "IOI_IDELAY0_C", + "IFDLY0": "LIOI3_IDELAY0_IFDLY0", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "LD": "IOI_IDELAY0_LD", + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "IFDLY1": "LIOI3_IDELAY0_IFDLY1", + "IFDLY2": "LIOI3_IDELAY0_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2" + }, + "x_coord": 0 + } + ], + "wires": [ + "IOI_RCLK_DIV_CLR0_1", + "IOI_WL1END0_0", + "IOI_IDELAYCTRL_RST", + "LIOI_OLOGIC1_CLKDIVF", + "IOI_IMUX12_0", + "IOI_LH12_0", + "IOI_DCI_TSTHLN", + "IOI_IDELAYCTRL_OUTN1", + "IOI_EE2BEG2_0", + "IOI_SE4C2_0", + "IOI_OLOGIC0_D5", + "IOI_IOCLK1", + "IOI_IMUX2_0", + "IOI_WW4A3_0", + "IOI_OLOGIC1_SR", + "IOI_EL1BEG2_0", + "IOI_ILOGIC1_REV", + "IOI_EL1BEG2_1", + "IOI_SE4BEG2_0", + "LIOI_I2GCLK_TOP0", + "LIOI_OSOUT21", + "IOI_IDELAYCTRL_RDY", + "IOI_EE4A0_1", + "IOI_RCLK_DIV_CE1", + "LIOI_ILOGIC0_TFB", + "IOI_OLOGIC1_CLKB", + "LIOI_PD_INT_EN_0", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_LOGIC_OUTS8_1", + "IOI_SW4END2_0", + "IOI_IMUX_RC1", + "IOI_ODELAY1_CNTVALUEOUT2", + "LIOI_OLOGIC0_TQ", + "IOI_IMUX39_0", + "IOI_WW4B0_0", + "IOI_ER1BEG3_1", + "IOI_BYP1_1", + "IOI_IMUX5_1", + "IOI_PHASER_TO_IO_ICLKDIV_0", + "IOI_IMUX46_1", + "IOI_ILOGIC0_Q6", + "IOI_IMUX4_0", + "IOI_ODELAY1_CNTVALUEOUT4", + "LIOI_I0", + "IOI_NW4END3_1", + "IOI_ILOGIC1_OCLKB", + "IOI_FAN1_0", + "IOI_LOGIC_OUTS19_0", + "IOI_IMUX29_1", + "IOI_IMUX10_1", + "IOI_ILOGIC1_DYNCLKDIVPSEL", + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "IOI_ILOGIC1_Q1", + "IOI_OLOGIC1_D7", + "IOI_LH5_1", + "IOI_ODELAY0_REGRST", + "LIOI_T1", + "IOI_IOCLK2", + "IOI_WW4END0_0", + "IOI_WW4END2_1", + "IOI_IMUX32_1", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS20_0", + "IOI_PHASER_TO_IO_OCLK", + "IOI_LOGIC_OUTS5_1", + "IOI_RCLK_DIV_CE0", + "IOI_LOGIC_OUTS9_0", + "LIOI3_IDELAY0_IFDLY1", + "IOI_EE2A1_1", + "IOI_EE2A3_1", + "IOI_FAN6_0", + "IOI_WW2END1_0", + "IOI_IOCLK3", + "IOI_WW2END0_1", + "IOI_SE2A3_0", + "IOI_SE4C0_1", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_EE2A0_1", + "IOI_DCI_DCIDONE", + "IOI_IMUX25_0", + "IOI_LOGIC_OUTS8_0", + "IOI_ODELAY0_CLKIN", + "IOI_BLOCK_OUTS2_0", + "IOI_FAN4_1", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_NE4C2_1", + "IOI_IMUX44_0", + "IOI_IMUX29_0", + "IOI_WR1END2_1", + "IOI_OLOGIC0_CLKDIV", + "IOI_EE4C3_1", + "IOI_EE2BEG3_1", + "IOI_IMUX22_0", + "LIOI_ISIN21", + "IOI_ILOGIC0_REV", + "IOI_IMUX21_0", + "IOI_IMUX15_1", + "LIOI_OLOGIC1_OQ", + "IOI_BYP4_1", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_ODELAY0_LDPIPEEN", + "IOI_NE2A3_1", + "IOI_ILOGIC1_Q3", + "IOI_BYP2_1", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_WW4A2_0", + "IOI_NE4BEG1_0", + "IOI_LOGIC_OUTS18_1", + "IOI_OLOGIC0_D2", + "LIOI_ODELAY0_OFDLY1", + "IOI_ILOGIC0_Q7", + "IOI_ILOGIC1_CLK", + "IOI_ODELAY0_CNTVALUEOUT0", + "LIOI_I1", + "IOI_IDELAY0_REGRST", + "IOI_ODELAY1_INC", + "LIOI3_IDELAY0_IFDLY2", + "LIOI_I2GCLK_BOT1", + "IOI_SE4BEG1_1", + "IOI_IMUX33_1", + "IOI_WW4END3_0", + "IOI_TBYTEIN_TERM", + "IOI_WR1END1_1", + "IOI_ILOGIC1_CE2", + "IOI_SE4C0_0", + "IOI_LOGIC_OUTS21_1", + "IOI_ILOGIC0_CLKDIV", + "IOI_SE2A1_0", + "IOI_IMUX8_0", + "IOI_LH5_0", + "LIOI_ISOUT21", + "LIOI_KEEPER_INT_EN_1", + "IOI_IDELAYCTRL_OUTN65", + "IOI_NE2A1_1", + "IOI_EE4C3_0", + "IOI_LOGIC_OUTS14_1", + "IOI_OLOGIC0_CLKB", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_SE4BEG0_0", + "IOI_ILOGIC0_OCLKB", + "IOI_SE4C1_1", + "IOI_IMUX47_1", + "IOI_CLK1_1", + "IOI_IDELAY1_DATAIN", + "IOI_ODELAY1_CNTVALUEIN0", + "LIOI_OLOGIC0_TFB_LOCAL", + "IOI_IMUX28_0", + "IOI_LOGIC_OUTS6_1", + "IOI_SE2A2_1", + "IOI_LH9_0", + "IOI_EE2BEG3_0", + "LIOI_IDELAY0_DATAOUT", + "LIOI3_IDELAY1_IFDLY2", + "IOI_SE2A0_1", + "IOI_IMUX40_1", + "IOI_IMUX8_1", + "IOI_ILOGIC1_DYNCLKSEL", + "IOI_EE2BEG1_1", + "IOI_SW4END1_0", + "IOI_SW4A3_0", + "IOI_IMUX16_0", + "IOI_LOGIC_OUTS0_1", + "IOI_ER1BEG0_1", + "IOI_OLOGIC0_TCE", + "IOI_NW4A1_0", + "IOI_NW2A0_0", + "IOI_IDELAY1_CNTVALUEIN4", + "IOI_EL1BEG0_0", + "IOI_ILOGIC0_CE1", + "IOI_NW4A3_0", + "IOI_IDELAY1_CNTVALUEOUT1", + "IOI_SE2A2_0", + "IOI_WL1END1_1", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_ILOGIC1_O", + "IOI_IDELAY0_INC", + "IOI_IMUX28_1", + "IOI_WW4A1_0", + "IOI_IDELAY1_CNTVALUEOUT0", + "IOI_IMUX37_1", + "IOI_ODELAY1_CINVCTRL", + "IOI_MONITOR_P", + "IOI_EE4C0_1", + "IOI_OLOGIC1_TBYTEOUT", + "IOI_LEAF_GCLK0", + "IOI_LOGIC_OUTS7_1", + "LIOI_ISIN20", + "IOI_IMUX35_1", + "IOI_WW2END3_0", + "IOI_IDELAY1_CNTVALUEOUT4", + "IOI_EE4C2_1", + "IOI_NE4BEG2_1", + "IOI_SE4BEG3_0", + "IOI_ILOGIC1_Q6", + "IOI_ILOGIC0_Q4", + "IOI_SE4BEG0_1", + "IOI_RCLK_DIV_CE2_1", + "IOI_LOGIC_OUTS0_0", + "IOI_BYP4_0", + "LIOI3_IDELAY1_IFDLY1", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "IOI_OLOGIC0_D6", + "IOI_WL1END3_1", + "IOI_DCI_TSTCLK", + "IOI_WW4B1_0", + "IOI_WW4C2_1", + "IOI_PHASER_TO_IO_OCLK_0", + "IOI_PHASER_TO_IO_OCLKDIV_0", + "IOI_IMUX45_0", + "IOI_ILOGIC0_Q2", + "IOI_SW2A0_1", + "IOI_SE4BEG1_0", + "IOI_WW2A1_0", + "IOI_LOGIC_OUTS12_0", + "IOI_ILOGIC0_OCLK", + "IOI_EE4B3_0", + "IOI_WW4END1_1", + "IOI_IMUX19_0", + "IOI_NE4C2_0", + "IOI_OLOGIC0_CLK", + "IOI_WL1END1_0", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_IMUX_RC2", + "LIOI3_IDELAY1_IFDLY0", + "IOI_IMUX35_0", + "IOI_IMUX2_1", + "IOI_WW4A0_0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_IMUX15_0", + "IOI_WL1END2_0", + "IOI_WW2END3_1", + "IOI_IMUX41_1", + "IOI_WW4END1_0", + "LIOI_IDELAY1_DATAOUT", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS14_0", + "IOI_OLOGIC0_D7", + "IOI_IMUX31_1", + "IOI_SW2A3_0", + "LIOI_OLOGIC1_TQ", + "IOI_OLOGIC1_TBYTEIN", + "IOI_SW4A2_1", + "IOI_IDELAY1_LDPIPEEN", + "IOI_IMUX6_1", + "IOI_IMUX_RC0", + "LIOI_IDELAY0_IDATAIN", + "IOI_IMUX9_0", + "IOI_WW2END2_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_EE4BEG2_1", + "IOI_FAN6_1", + "IOI_ODELAY1_REGRST", + "IOI_IMUX11_0", + "LIOI_ISOUT11", + "IOI_RCLK_FORIO1", + "IOI_SW4A0_1", + "IOI_WW4C0_1", + "IOI_IMUX30_1", + "IOI_SE2A3_1", + "IOI_SW4A1_1", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OLOGIC1_D4", + "IOI_WW2A1_1", + "IOI_RCLK_DIV_CLR0", + "IOI_NW2A3_0", + "IOI_OLOGIC1_OCE", + "LIOI_ILOGIC1_D", + "IOI_IMUX40_0", + "IOI_SW4END0_1", + "IOI_SW4END1_1", + "IOI_ILOGIC1_Q4", + "IOI_LOGIC_OUTS16_1", + "IOI_IMUX20_1", + "IOI_NE4C1_1", + "IOI_ILOGIC1_CLKB", + "IOI_RCLK_DIV_CE3", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_LEAF_GCLK1", + "IOI_ILOGIC0_Q1", + "IOI_EE4BEG0_0", + "IOI_IMUX46_0", + "IOI_IMUX45_1", + "IOI_EE4BEG3_1", + "IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IMUX38_1", + "IOI_MONITOR_N", + "IOI_LEAF_GCLK5", + "IOI_WW4A3_1", + "IOI_ODELAY0_CNTVALUEIN2", + "IOI_NW4END3_0", + "IOI_WW2A3_1", + "LIOI_IBUF_DISABLE1", + "IOI_SE4BEG2_1", + "IOI_BYP5_1", + "IOI_ODELAY0_CINVCTRL", + "IOI_OLOGIC0_D1", + "IOI_WW4A2_1", + "LIOI_OSIN10", + "IOI_ODELAY1_CE", + "IOI_WW4C0_0", + "IOI_FAN1_1", + "IOI_IMUX26_0", + "LIOI_OLOGIC1_TFB", + "IOI_ODELAY0_LD", + "LIOI_ILOGIC1_DDLY", + "IOI_EE4B2_0", + "IOI_NW4A0_0", + "IOI_SE2A0_0", + "IOI_EE4C0_0", + "IOI_LOGIC_OUTS21_0", + "IOI_IDELAY0_LD", + "IOI_IMUX23_0", + "IOI_WR1END0_0", + "IOI_WW4END3_1", + "IOI_ODELAY1_CNTVALUEIN1", + "IOI_LOGIC_OUTS15_0", + "IOI_OLOGIC1_D1", + "IOI_LOGIC_OUTS23_0", + "IOI_WW2END2_1", + "IOI_DCI_TSTRST", + "IOI_IMUX22_1", + "IOI_LOGIC_OUTS1_1", + "IOI_EE4B1_0", + "IOI_IMUX7_0", + "IOI_EE4A2_1", + "IOI_BLOCK_OUTS1_0", + "IOI_IMUX42_0", + "IOI_SW2A2_1", + "IOI_WW4C1_0", + "IOI_OLOGIC0_REV", + "IOI_BYP0_1", + "IOI_IMUX39_1", + "IOI_NW4A0_1", + "IOI_BYP6_0", + "LIOI_IBUF0", + "IOI_IMUX13_1", + "IOI_OLOGIC0_D4", + "IOI_ODELAY0_CNTVALUEIN3", + "IOI_IMUX24_1", + "IOI_ILOGIC0_CLKDIVP", + "IOI_IMUX13_0", + "IOI_RCLK_DIV_CE2", + "IOI_IDELAY1_REGRST", + "LIOI_PU_INT_EN_1", + "IOI_WR1END3_1", + "IOI_IDELAY1_C", + "IOI_IDELAY1_LD", + "LIOI_IBUF1", + "IOI_IMUX47_0", + "IOI_ILOGIC0_O", + "IOI_ILOGIC1_Q8", + "IOI_BYP0_0", + "IOI_IMUX27_0", + "LIOI_O0", + "IOI_SW4END3_1", + "LIOI_ILOGIC1_TFB", + "IOI_LH1_0", + "IOI_SW4A0_0", + "IOI_SE4BEG3_1", + "LIOI_OSOUT20", + "IOI_IDELAY1_CNTVALUEIN0", + "IOI_SW4END0_0", + "IOI_WW4B1_1", + "LIOI_ISOUT10", + "IOI_IDELAY0_DATAIN", + "IOI_SW4A2_0", + "IOI_LOGIC_OUTS10_0", + "IOI_CLK0_1", + "IOI_IMUX11_1", + "IOI_WW4C1_1", + "IOI_OLOGIC0_T2", + "IOI_BYP6_1", + "IOI_LOGIC_OUTS2_0", + "IOI_BLOCK_OUTS0_0", + "IOI_NW4A3_1", + "IOI_ILOGIC1_BITSLIP", + "IOI_ODELAY0_CE", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_OLOGIC1_CLK", + "IOI_ILOGIC1_CLKDIV", + "IOI_IMUX20_0", + "IOI_LOGIC_OUTS10_1", + "LIOI_KEEPER_INT_EN_0", + "IOI_IDELAY0_LDPIPEEN", + "IOI_LOGIC_OUTS6_0", + "IOI_EL1BEG3_1", + "LIOI_ODELAY1_OFDLY1", + "LIOI_OSIN11", + "IOI_ILOGIC0_CLKB", + "IOI_LH6_0", + "IOI_EE4A2_0", + "IOI_LOGIC_OUTS22_0", + "IOI_NW2A1_0", + "IOI_WW2A0_0", + "IOI_PHASER_TO_IO_OCLK1X_90", + "LIOI_ILOGIC0_OFB", + "IOI_ILOGIC1_Q5", + "IOI_CTRL0_0", + "IOI_IDELAY0_CE", + "LIOI_OLOGIC0_OFB", + "IOI_ILOGIC0_BITSLIP", + "IOI_IMUX14_0", + "IOI_LOGIC_OUTS3_0", + "IOI_IMUX4_1", + "IOI_IMUX3_1", + "IOI_IMUX34_0", + "IOI_WL1END3_0", + "IOI_OLOGIC0_D8", + "IOI_IMUX17_1", + "IOI_OLOGIC1_TCE", + "IOI_LOGIC_OUTS4_1", + "IOI_OLOGIC0_T3", + "IOI_LOGIC_OUTS5_0", + "IOI_ILOGIC0_Q5", + "IOI_IMUX43_1", + "LIOI_OLOGIC0_CLKDIVF", + "IOI_ODELAY0_C", + "IOI_EE2BEG2_1", + "IOI_LOGIC_OUTS22_1", + "IOI_FAN3_0", + "IOI_SW2A3_1", + "LIOI_ODELAY0_OFDLY0", + "IOI_LOGIC_OUTS13_0", + "IOI_ODELAY1_LD", + "IOI_IDELAY1_CNTVALUEOUT3", + "IOI_ILOGIC1_Q2", + "IOI_ODELAY1_CNTVALUEIN3", + "IOI_EE4A3_1", + "IOI_WR1END3_0", + "IOI_IDELAY0_C", + "IOI_WW2END0_0", + "LIOI_ODELAY1_OFDLY2", + "IOI_FAN0_1", + "IOI_ILOGIC0_Q3", + "IOI_IDELAY0_CINVCTRL", + "IOI_NW2A1_1", + "IOI_IMUX26_1", + "IOI_EE2BEG1_0", + "IOI_OLOGIC1_IOCLKGLITCH", + "IOI_FAN3_1", + "IOI_NE2A0_1", + "LIOI_OLOGIC0_OQ", + "IOI_WR1END2_0", + "IOI_ODELAY1_CNTVALUEIN2", + "IOI_CTRL1_1", + "IOI_ODELAY0_INC", + "IOI_IMUX0_0", + "IOI_BYP3_1", + "IOI_IMUX19_1", + "IOI_LH7_0", + "IOI_SE4C2_1", + "IOI_BLOCK_OUTS2_1", + "IOI_WW4C2_0", + "IOI_NW2A2_0", + "IOI_NW4END2_1", + "IOI_NE4BEG1_1", + "LIOI_ISIN11", + "IOI_NW4A1_1", + "IOI_IMUX3_0", + "IOI_OLOGIC1_CLKDIV", + "IOI_LEAF_GCLK4", + "IOI_WW4C3_0", + "IOI_EL1BEG1_0", + "IOI_IMUX0_1", + "IOI_WR1END0_1", + "IOI_LH4_1", + "IOI_IDELAY1_CE", + "IOI_NE4C3_1", + "IOI_BLOCK_OUTS0_1", + "IOI_IDELAY1_CINVCTRL", + "IOI_LH3_0", + "IOI_NE2A1_0", + "IOI_IMUX43_0", + "IOI_RCLK_DIV_CLR2", + "IOI_NE4BEG3_1", + "IOI_IMUX_RC3", + "IOI_LOGIC_OUTS9_1", + "IOI_BLOCK_OUTS3_1", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_OLOGIC1_T3", + "IOI_NE4BEG0_0", + "IOI_NE4C1_0", + "IOI_IMUX38_0", + "IOI_LH10_1", + "IOI_IMUX34_1", + "IOI_SE4C3_0", + "IOI_ILOGIC1_Q7", + "IOI_EL1BEG3_0", + "IOI_LOGIC_OUTS11_0", + "IOI_EE4BEG1_0", + "IOI_FAN0_0", + "IOI_FAN2_1", + "IOI_IDELAY1_CNTVALUEIN2", + "LIOI_ODELAY0_OFDLY2", + "IOI_IMUX10_0", + "IOI_EE4B3_1", + "IOI_IMUX44_1", + "LIOI_ODELAY0_DATAOUT", + "IOI_WW2END1_1", + "IOI_IMUX31_0", + "IOI_ER1BEG1_0", + "IOI_NW2A2_1", + "IOI_WW4B3_0", + "IOI_RCLK_FORIO0", + "IOI_SE4C1_0", + "LIOI_PD_INT_EN_1", + "IOI_ILOGIC0_CE2", + "IOI_IMUX16_1", + "IOI_ODELAY1_CNTVALUEOUT0", + "IOI_FAN5_1", + "IOI_RCLK_DIV_CE3_1", + "IOI_FAN4_0", + "IOI_IMUX42_1", + "IOI_OLOGIC1_D2", + "IOI_IMUX17_0", + "IOI_WW4C3_1", + "IOI_OLOGIC0_CLKDIVB", + "IOI_LH12_1", + "IOI_EE4B1_1", + "IOI_NW4A2_0", + "IOI_LH2_1", + "IOI_EE4B0_0", + "IOI_EE4BEG0_1", + "LIOI_PU_INT_EN_0", + "IOI_OLOGIC1_REV", + "IOI_WW4B2_0", + "IOI_NE2A0_0", + "IOI_FAN5_0", + "IOI_IMUX36_0", + "IOI_NW4A2_1", + "LIOI_T0", + "IOI_IMUX33_0", + "IOI_BYP1_0", + "IOI_OLOGIC1_T2", + "IOI_RCLK_FORIO2", + "IOI_EE2A3_0", + "IOI_RCLK_DIV_CLR1", + "IOI_IDELAY1_CNTVALUEOUT2", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_NE2A2_1", + "LIOI_OLOGIC1_TFB_LOCAL", + "IOI_WW2A2_0", + "IOI_EE4A1_1", + "IOI_EE4B2_1", + "LIOI_ODELAY1_ODATAIN", + "IOI_LEAF_GCLK3", + "IOI_NW4END1_1", + "IOI_ODELAY1_CNTVALUEOUT1", + "IOI_WL1END2_1", + "IOI_LH3_1", + "IOI_LH6_1", + "IOI_RCLK_DIV_CLR3", + "IOI_EE4A0_0", + "IOI_CLK0_0", + "IOI_IMUX30_0", + "IOI_LH10_0", + "IOI_OLOGIC1_CLKDIVFB", + "LIOI_OLOGIC1_OFB", + "IOI_BYP5_0", + "IOI_BLOCK_OUTS3_0", + "IOI_SW4A3_1", + "IOI_CLK1_0", + "IOI_LOGIC_OUTS2_1", + "IOI_ILOGIC1_CLKDIVP", + "LIOI_I2GCLK_TOP1", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "LIOI_ODELAY0_ODATAIN", + "IOI_EL1BEG0_1", + "IOI_NE4C0_1", + "LIOI_OLOGIC0_TFB", + "IOI_WL1END0_1", + "IOI_IMUX32_0", + "IOI_ODELAY1_CNTVALUEOUT3", + "IOI_LOGIC_OUTS3_1", + "IOI_EE4BEG1_1", + "IOI_IMUX7_1", + "IOI_WW4B0_1", + "IOI_LOGIC_OUTS4_0", + "IOI_LOGIC_OUTS12_1", + "IOI_SW2A1_1", + "LIOI_ISIN10", + "IOI_ILOGIC1_CE1", + "IOI_WW4END0_1", + "IOI_IMUX18_0", + "IOI_RCLK_FORIO3", + "IOI_ODELAY1_LDPIPEEN", + "IOI_WW2A0_1", + "LIOI_OSOUT11", + "IOI_ER1BEG2_1", + "LIOI_ILOGIC1_OFB", + "IOI_IMUX25_1", + "IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_LH11_1", + "IOI_OLOGIC1_D6", + "IOI_LOGIC_OUTS15_1", + "IOI_IMUX1_1", + "IOI_IMUX12_1", + "IOI_SE4C3_1", + "IOI_WR1END1_0", + "IOI_LH8_1", + "IOI_SE2A1_1", + "IOI_EE4A1_0", + "IOI_SW4END3_0", + "IOI_LH1_1", + "IOI_LH8_0", + "IOI_DCI_TSTRST0", + "LIOI_IBUF_DISABLE0", + "IOI_LOGIC_OUTS23_1", + "IOI_LH2_0", + "IOI_BYP7_1", + "IOI_OCLKM_0", + "IOI_SW4END2_1", + "IOI_EE4A3_0", + "IOI_IMUX1_0", + "IOI_BYP3_0", + "IOI_NE2A2_0", + "IOI_ER1BEG0_0", + "IOI_NW4END2_0", + "IOI_ER1BEG3_0", + "IOI_EE2A2_1", + "IOI_FAN2_0", + "IOI_SW2A1_0", + "IOI_CTRL1_0", + "IOI_WW2A2_1", + "IOI_ODELAY1_CLKIN", + "IOI_OLOGIC0_OCE", + "IOI_OCLKM_1", + "IOI_IMUX41_0", + "IOI_NW2A0_1", + "IOI_IMUX24_0", + "LIOI_DIFF_TERM_INT_EN", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WW2A3_0", + "LIOI_ILOGIC0_DDLY", + "IOI_OLOGIC1_D3", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_LH9_1", + "IOI_IMUX5_0", + "IOI_OLOGIC1_T4", + "IOI_LOGIC_OUTS20_1", + "IOI_IMUX9_1", + "IOI_SW4A1_0", + "IOI_LH11_0", + "IOI_OLOGIC1_T1", + "IOI_EE4C1_0", + "IOI_IDELAY1_CNTVALUEIN1", + "LIOI_DCI_T_TERM0", + "IOI_BYP2_0", + "IOI_RCLK_DIV_CLR1_1", + "LIOI_IDELAY1_IDATAIN", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_WW4B3_1", + "IOI_EE4C1_1", + "IOI_ODELAY0_CNTVALUEIN0", + "IOI_WW4B2_1", + "IOI_IMUX36_1", + "IOI_BLOCK_OUTS1_1", + "IOI_LOGIC_OUTS18_0", + "IOI_IMUX27_1", + "IOI_EL1BEG1_1", + "IOI_LOGIC_OUTS16_0", + "IOI_PHASER_TO_IO_ICLKDIV", + "LIOI_ODELAY1_DATAOUT", + "LIOI_OSIN20", + "IOI_LOGIC_OUTS1_0", + "IOI_EE4BEG3_0", + "IOI_ER1BEG2_0", + "IOI_EE4BEG2_0", + "IOI_DCI_TSTHLP", + "IOI_EE2A0_0", + "IOI_WW4A0_1", + "IOI_LOGIC_OUTS11_1", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_IDELAY0_CNTVALUEIN0", + "IOI_IOCLK0", + "LIOI_OSIN21", + "IOI_IMUX37_0", + "IOI_OLOGIC1_D8", + "IOI_ODELAY1_CNTVALUEIN4", + "LIOI_ODELAY1_OFDLY0", + "LIOI_DCI_T_TERM1", + "IOI_LOGIC_OUTS7_0", + "IOI_NE4BEG2_0", + "IOI_EE2BEG0_0", + "IOI_ILOGIC1_SR", + "IOI_OLOGIC0_T1", + "IOI_OLOGIC1_CLKDIVB", + "IOI_NE4C3_0", + "IOI_ILOGIC0_SR", + "IOI_ODELAY1_C", + "IOI_EE2A2_0", + "IOI_IMUX6_0", + "IOI_LOGIC_OUTS13_1", + "LIOI_O1", + "IOI_LH7_1", + "IOI_NW4END0_0", + "IOI_NE2A3_0", + "IOI_NW2A3_1", + "IOI_LOGIC_OUTS19_1", + "IOI_LEAF_GCLK2", + "IOI_OLOGIC0_SR", + "IOI_EE2BEG0_1", + "IOI_NE4BEG3_0", + "IOI_ILOGIC0_Q8", + "IOI_INT_DCI_EN", + "IOI_SW2A0_0", + "IOI_ODELAY0_CNTVALUEIN4", + "IOI_WW4END2_0", + "IOI_FAN7_1", + "IOI_IMUX23_1", + "IOI_BYP7_0", + "IOI_IMUX18_1", + "IOI_ILOGIC1_DYNCLKDIVSEL", + "IOI_NW4END0_1", + "IOI_OCLK_1", + "IOI_IMUX21_1", + "IOI_FAN7_0", + "IOI_NW4END1_0", + "IOI_IDELAY1_CNTVALUEIN3", + "LIOI_OSOUT10", + "IOI_ILOGIC1_OCLK", + "IOI_LOGIC_OUTS17_0", + "IOI_NE4BEG0_1", + "IOI_PHASER_TO_IO_ICLK_0", + "IOI_EE4B0_1", + "IOI_OLOGIC0_D3", + "IOI_LOGIC_OUTS17_1", + "LIOI3_IDELAY0_IFDLY0", + "IOI_EE2A1_0", + "IOI_WW4A1_1", + "IOI_OLOGIC0_TBYTEIN", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_ER1BEG1_1", + "IOI_CTRL0_1", + "IOI_IMUX14_1", + "LIOI_ISOUT20", + "LIOI_ILOGIC0_D", + "IOI_OLOGIC1_D5", + "IOI_OCLK_0", + "IOI_IDELAY1_INC", + "IOI_NE4C0_0", + "IOI_LH4_0", + "IOI_OLOGIC0_T4" + ], + "pips": { + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR1_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { + "src_wire": "LIOI_OLOGIC0_TQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX47_0->IOI_OLOGIC1_D8": { + "src_wire": "IOI_IMUX47_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D8", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { + "src_wire": "IOI_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { + "src_wire": "IOI_IMUX9_0", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { + "src_wire": "IOI_ILOGIC1_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { + "src_wire": "IOI_BYP7_0", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { + "src_wire": "IOI_ILOGIC0_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_TBYTEIN_TERM->>IOI_OLOGIC1_TBYTEIN": { + "src_wire": "IOI_TBYTEIN_TERM", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_TFB->LIOI_OLOGIC1_TFB_LOCAL": { + "src_wire": "LIOI_OLOGIC1_TFB", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { + "src_wire": "IOI_ILOGIC1_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { + "src_wire": "IOI_ILOGIC0_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX7_0->IOI_OLOGIC1_T2": { + "src_wire": "IOI_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { + "src_wire": "IOI_ILOGIC0_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { + "src_wire": "IOI_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "src_wire": "IOI_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TQ": { + "src_wire": "IOI_OLOGIC1_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { + "src_wire": "IOI_FAN5_1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLK_1": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "src_wire": "LIOI_ILOGIC0_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { + "src_wire": "LIOI_OLOGIC0_OQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { + "src_wire": "IOI_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { + "src_wire": "LIOI_IDELAY0_DATAOUT", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_TFB_LOCAL->LIOI_ILOGIC1_TFB": { + "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { + "src_wire": "IOI_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX32_0->IOI_IDELAY1_CE": { + "src_wire": "IOI_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_CTRL0_0->IOI_OLOGIC1_SR": { + "src_wire": "IOI_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP4_0->IOI_IMUX_RC1": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { + "src_wire": "IOI_ILOGIC1_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { + "src_wire": "IOI_ILOGIC1_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP3_0->IOI_IMUX_RC0": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_OFB->LIOI_ILOGIC1_OFB": { + "src_wire": "LIOI_OLOGIC1_OFB", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLK_0": { + "src_wire": "IOI_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OSOUT11->LIOI_OSIN10": { + "src_wire": "LIOI_OSOUT11", + "is_pseudo": "0", + "dst_wire": "LIOI_OSIN10", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_OQ->>LIOI_O1": { + "src_wire": "LIOI_OLOGIC1_OQ", + "is_pseudo": "0", + "dst_wire": "LIOI_O1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { + "src_wire": "IOI_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_TQ->>LIOI_T1": { + "src_wire": "LIOI_OLOGIC1_TQ", + "is_pseudo": "0", + "dst_wire": "LIOI_T1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX26_1->IOI_IDELAY0_INC": { + "src_wire": "IOI_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { + "src_wire": "IOI_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP4_1->IOI_IMUX_RC2": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { + "src_wire": "IOI_ILOGIC1_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_IDELAY1_DATAOUT->LIOI_ILOGIC1_DDLY": { + "src_wire": "LIOI_IDELAY1_DATAOUT", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX26_0->IOI_IDELAY1_INC": { + "src_wire": "IOI_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_INC", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX34_1->IOI_OLOGIC0_D1": { + "src_wire": "IOI_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { + "src_wire": "IOI_ILOGIC0_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_CLK1_0->IOI_IDELAY1_C": { + "src_wire": "IOI_CLK1_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_C", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { + "src_wire": "IOI_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLKM_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_I0->LIOI_IDELAY0_IDATAIN": { + "src_wire": "LIOI_I0", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE2_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TFB": { + "src_wire": "IOI_OLOGIC1_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { + "src_wire": "IOI_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX15_0->IOI_OLOGIC1_T1": { + "src_wire": "IOI_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OQ": { + "src_wire": "IOI_OLOGIC1_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX44_0->IOI_OLOGIC1_D3": { + "src_wire": "IOI_IMUX44_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX43_1->IOI_OLOGIC0_D5": { + "src_wire": "IOI_IMUX43_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX7_1->IOI_OLOGIC0_T2": { + "src_wire": "IOI_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLKM_0": { + "src_wire": "IOI_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX13_1->IOI_OLOGIC0_T3": { + "src_wire": "IOI_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX21_0->IOI_OLOGIC1_T4": { + "src_wire": "IOI_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { + "src_wire": "IOI_ILOGIC0_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { + "src_wire": "IOI_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLK": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_ISOUT20->LIOI_ISIN21": { + "src_wire": "LIOI_ISOUT20", + "is_pseudo": "0", + "dst_wire": "LIOI_ISIN21", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_I1->LIOI_IDELAY1_IDATAIN": { + "src_wire": "LIOI_I1", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY1_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_1->LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { + "src_wire": "LIOI_IDELAY0_IDATAIN", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX30_1->IOI_IDELAY0_LD": { + "src_wire": "IOI_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX45_0->IOI_OLOGIC1_D6": { + "src_wire": "IOI_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D6", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_OQ->>LIOI_O0": { + "src_wire": "LIOI_OLOGIC0_OQ", + "is_pseudo": "0", + "dst_wire": "LIOI_O0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { + "src_wire": "IOI_ILOGIC1_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP3_1->IOI_IMUX_RC3": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { + "src_wire": "IOI_FAN5_0", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE3_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { + "src_wire": "IOI_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_TQ->>LIOI_OLOGIC1_TFB": { + "src_wire": "LIOI_OLOGIC1_TQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { + "src_wire": "LIOI_OLOGIC0_OFB", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLKM_1": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { + "src_wire": "IOI_ILOGIC0_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { + "src_wire": "IOI_BYP6_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_TBYTEIN_TERM->>IOI_OLOGIC0_TBYTEIN": { + "src_wire": "IOI_TBYTEIN_TERM", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX21_1->IOI_OLOGIC0_T4": { + "src_wire": "IOI_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { + "src_wire": "IOI_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR0_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { + "src_wire": "IOI_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { + "src_wire": "IOI_ILOGIC1_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_IBUF0->LIOI_I0": { + "src_wire": "LIOI_IBUF0", + "is_pseudo": "0", + "dst_wire": "LIOI_I0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX46_1->IOI_OLOGIC0_D7": { + "src_wire": "IOI_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { + "src_wire": "IOI_ILOGIC1_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX42_1->IOI_OLOGIC0_D4": { + "src_wire": "IOI_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "src_wire": "LIOI_ILOGIC0_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { + "src_wire": "IOI_FAN4_0", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_ISOUT10->LIOI_ISIN11": { + "src_wire": "LIOI_ISOUT10", + "is_pseudo": "0", + "dst_wire": "LIOI_ISIN11", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX40_0->IOI_OLOGIC1_D2": { + "src_wire": "IOI_IMUX40_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { + "src_wire": "IOI_FAN4_1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_CLK1_1->IOI_IDELAY0_C": { + "src_wire": "IOI_CLK1_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { + "src_wire": "LIOI_ILOGIC1_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { + "src_wire": "IOI_ILOGIC1_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_CTRL1_1->IOI_ILOGIC0_SR": { + "src_wire": "IOI_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX40_1->IOI_OLOGIC0_D2": { + "src_wire": "IOI_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OSOUT21->LIOI_OSIN20": { + "src_wire": "LIOI_OSOUT21", + "is_pseudo": "0", + "dst_wire": "LIOI_OSIN20", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX44_1->IOI_OLOGIC0_D3": { + "src_wire": "IOI_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_CLK0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { + "src_wire": "IOI_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { + "src_wire": "IOI_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLKM_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { + "src_wire": "IOI_BYP6_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_CTRL1_0->IOI_ILOGIC1_SR": { + "src_wire": "IOI_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX47_1->IOI_OLOGIC0_D8": { + "src_wire": "IOI_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX15_1->IOI_OLOGIC0_T1": { + "src_wire": "IOI_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { + "src_wire": "LIOI_OLOGIC0_TFB", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX13_0->IOI_OLOGIC1_T3": { + "src_wire": "IOI_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX34_0->IOI_OLOGIC1_D1": { + "src_wire": "IOI_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX30_0->IOI_IDELAY1_LD": { + "src_wire": "IOI_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LD", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { + "src_wire": "IOI_BYP7_1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { + "src_wire": "IOI_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_I1->LIOI_ILOGIC1_D": { + "src_wire": "LIOI_I1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_D", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_CTRL0_1->IOI_OLOGIC0_SR": { + "src_wire": "IOI_CTRL0_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_IDELAY1_IDATAIN->>LIOI_IDELAY1_DATAOUT": { + "src_wire": "LIOI_IDELAY1_IDATAIN", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY1_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { + "src_wire": "IOI_CLK0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { + "src_wire": "IOI_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX42_0->IOI_OLOGIC1_D4": { + "src_wire": "IOI_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D4", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { + "src_wire": "LIOI_ILOGIC1_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_I0->LIOI_ILOGIC0_D": { + "src_wire": "LIOI_I0", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_D", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { + "src_wire": "IOI_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { + "src_wire": "IOI_ILOGIC0_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX45_1->IOI_OLOGIC0_D6": { + "src_wire": "IOI_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_IBUF1->LIOI_I1": { + "src_wire": "LIOI_IBUF1", + "is_pseudo": "0", + "dst_wire": "LIOI_I1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { + "src_wire": "IOI_ILOGIC0_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX43_0->IOI_OLOGIC1_D5": { + "src_wire": "IOI_IMUX43_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D5", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX46_0->IOI_OLOGIC1_D7": { + "src_wire": "IOI_IMUX46_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D7", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_TQ->>LIOI_T0": { + "src_wire": "LIOI_OLOGIC0_TQ", + "is_pseudo": "0", + "dst_wire": "LIOI_T0", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { + "src_wire": "IOI_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM1", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OFB": { + "src_wire": "IOI_OLOGIC1_D1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_IMUX32_1->IOI_IDELAY0_CE": { + "src_wire": "IOI_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_OQ->>LIOI_OLOGIC1_OFB": { + "src_wire": "LIOI_OLOGIC1_OQ", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { + "src_wire": "IOI_ILOGIC0_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_1", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_L_TERM_INT.json b/kintex7/tile_type_L_TERM_INT.json new file mode 100644 index 0000000..d45548b --- /dev/null +++ b/kintex7/tile_type_L_TERM_INT.json @@ -0,0 +1,173 @@ +{ + "tile_type": "L_TERM_INT", + "sites": [], + "wires": [ + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "TERM_INT_CTRL1", + "TERM_INT_LOGIC_OUTS_L_B1", + "TERM_INT_LOGIC_OUTS_L_B7", + "L_TERM_INT_SW4BEG0", + "L_TERM_INT_SW4BEG3", + "L_TERM_INT_WW4B1", + "TERM_INT_IMUX6", + "L_TERM_INT_SW4C2", + "L_TERM_INT_SW2BEG1", + "L_TERM_INT_LH3", + "L_TERM_INT_NW4BEG0", + "TERM_INT_LOGIC_OUTS_L_B8", + "TERM_INT_IMUX41", + "TERM_INT_BYP1", + "TERM_INT_LOGIC_OUTS_L_B22", + "TERM_INT_FAN7", + "L_TERM_INT_SW4BEG1", + "TERM_INT_IMUX24", + "L_TERM_INT_SW4C1", + "L_TERM_INT_WW4BEG0", + "TERM_INT_LOGIC_OUTS_L_B5", + "TERM_INT_IMUX14", + "L_TERM_INT_SW2BEG2", + "L_TERM_INT_NW4C3", + "TERM_INT_CLK0", + "TERM_INT_BLOCK_OUTS_L_B3", + "TERM_INT_IMUX7", + "TERM_INT_IMUX10", + "L_TERM_INT_DQS_IOTOPHASER", + "TERM_INT_IMUX22", + "L_TERM_INT_SW2BEG3", + "TERM_INT_MONITOR_N", + "TERM_INT_BYP7", + "TERM_INT_IMUX28", + "L_TERM_INT_WL1BEG2", + "TERM_INT_IMUX21", + "TERM_INT_IMUX5", + "TERM_INT_IMUX11", + "L_TERM_INT_WW2BEG1", + "L_TERM_INT_LH0", + "L_TERM_INT_WW2A3", + "TERM_INT_IMUX4", + "L_TERM_INT_NW4BEG1", + "L_TERM_INT_WL1BEG3", + "TERM_INT_LOGIC_OUTS_L_B15", + "TERM_INT_IMUX34", + "L_TERM_INT_WW4A2", + "L_TERM_INT_SW4C0", + "TERM_INT_LOGIC_OUTS_L_B12", + "TERM_INT_IMUX35", + "L_TERM_INT_WW2BEG0", + "L_TERM_INT_NW2BEG0", + "L_TERM_INT_LH4", + "L_TERM_INT_WW4C0", + "TERM_INT_FAN4", + "TERM_INT_LOGIC_OUTS_L_B11", + "L_TERM_INT_WW4BEG2", + "L_TERM_INT_WR1BEG1", + "L_TERM_INT_WW4B0", + "TERM_INT_IMUX13", + "TERM_INT_FAN6", + "TERM_INT_LOGIC_OUTS_L_B18", + "TERM_INT_IMUX40", + "TERM_INT_IMUX31", + "TERM_INT_FAN2", + "TERM_INT_IMUX46", + "TERM_INT_FAN1", + "L_TERM_INT_WW2BEG2", + "L_TERM_INT_WW2A1", + "L_TERM_INT_WW4BEG3", + "TERM_INT_LOGIC_OUTS_L_B20", + "TERM_INT_IMUX47", + "TERM_INT_IMUX9", + "TERM_INT_LOGIC_OUTS_L_B16", + "L_TERM_INT_WR1BEG3", + "TERM_INT_IMUX30", + "L_TERM_INT_NW4BEG2", + "TERM_INT_FAN3", + "TERM_INT_BLOCK_OUTS_L_B0", + "TERM_INT_LOGIC_OUTS_L_B6", + "TERM_INT_IMUX29", + "L_TERM_INT_WW4C3", + "TERM_INT_IMUX1", + "L_TERM_INT_SW4C3", + "TERM_INT_IMUX36", + "TERM_INT_LOGIC_OUTS_L_B10", + "TERM_INT_BYP5", + "TERM_INT_IMUX38", + "TERM_INT_IMUX26", + "L_TERM_INT_NW2BEG1", + "L_TERM_INT_WW4A1", + "L_TERM_INT_NW4C0", + "TERM_INT_CLK1", + "L_TERM_INT_NW2BEG2", + "L_TERM_INT_WW4A3", + "L_TERM_INT_WW4C1", + "L_TERM_INT_WL1BEG1", + "L_TERM_INT_LH5", + "TERM_INT_IMUX17", + "L_TERM_INT_WW2BEG3", + "TERM_INT_IMUX32", + "L_TERM_INT_NW2BEG3", + "L_TERM_INT_WW4C2", + "TERM_INT_IMUX16", + "L_TERM_INT_NW4C2", + "TERM_INT_FAN5", + "L_TERM_INT_PHASER_TO_IO_OCLK", + "L_TERM_INT_NW4BEG3", + "L_TERM_INT_WR1BEG2", + "L_TERM_INT_WL1BEG0", + "TERM_INT_LOGIC_OUTS_L_B4", + "TERM_INT_BYP4", + "TERM_INT_IMUX39", + "TERM_INT_BYP0", + "L_TERM_INT_WW2A0", + "TERM_INT_BLOCK_OUTS_L_B1", + "TERM_INT_IMUX37", + "TERM_INT_IMUX8", + "TERM_INT_LOGIC_OUTS_L_B23", + "L_TERM_INT_LH2", + "L_TERM_INT_WW4B3", + "TERM_INT_IMUX20", + "L_TERM_INT_LH1", + "TERM_INT_BYP6", + "L_TERM_INT_WR1BEG0", + "TERM_INT_IMUX27", + "TERM_INT_IMUX18", + "TERM_INT_CTRL0", + "TERM_INT_IMUX23", + "TERM_INT_LOGIC_OUTS_L_B9", + "TERM_INT_IMUX2", + "TERM_INT_LOGIC_OUTS_L_B0", + "TERM_INT_IMUX44", + "TERM_INT_IMUX19", + "TERM_INT_LOGIC_OUTS_L_B19", + "TERM_INT_IMUX3", + "L_TERM_INT_PHASER_TO_IO_ICLK", + "L_TERM_INT_WW4A0", + "TERM_INT_FAN0", + "TERM_INT_IMUX15", + "TERM_INT_IMUX33", + "TERM_INT_LOGIC_OUTS_L_B2", + "L_TERM_INT_NW4C1", + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", + "TERM_INT_LOGIC_OUTS_L_B3", + "TERM_INT_BLOCK_OUTS_L_B2", + "TERM_INT_IMUX43", + "TERM_INT_IMUX25", + "TERM_INT_LOGIC_OUTS_L_B21", + "TERM_INT_IMUX45", + "L_TERM_INT_WW4BEG1", + "TERM_INT_LOGIC_OUTS_L_B13", + "TERM_INT_IMUX0", + "TERM_INT_MONITOR_P", + "TERM_INT_LOGIC_OUTS_L_B17", + "L_TERM_INT_SW2BEG0", + "TERM_INT_IMUX12", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "L_TERM_INT_SW4BEG2", + "TERM_INT_BYP3", + "L_TERM_INT_WW4B2", + "TERM_INT_LOGIC_OUTS_L_B14", + "L_TERM_INT_WW2A2", + "TERM_INT_BYP2", + "TERM_INT_IMUX42" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_MONITOR_BOT_FUJI2.json b/kintex7/tile_type_MONITOR_BOT_FUJI2.json new file mode 100644 index 0000000..c44a94b --- /dev/null +++ b/kintex7/tile_type_MONITOR_BOT_FUJI2.json @@ -0,0 +1,3457 @@ +{ + "tile_type": "MONITOR_BOT_FUJI2", + "sites": [ + { + "y_coord": 67, + "name": "X0Y67", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "MONITOR_SEG_VN" + }, + "x_coord": 0 + }, + { + "y_coord": 66, + "name": "X0Y66", + "prefix": "IPAD", + "type": "IPAD", + "site_pins": { + "O": "MONITOR_SEG_VP" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "XADC", + "type": "XADC", + "site_pins": { + "TESTSO1": "MONITOR_TESTSO1", + "TESTADCIN11": "MONITOR_TESTADCIN11", + "TESTDB14": "MONITOR_TESTDB14", + "TESTSI2": "MONITOR_TESTSI2", + "TESTADCIN216": "MONITOR_TESTADCIN216", + "TESTADCIN13": "MONITOR_TESTADCIN13", + "TESTDB1": "MONITOR_TESTDB1", + "TESTDB13": "MONITOR_TESTDB13", + "DEN": "MONITOR_DEN", + "TESTADCOUT11": "MONITOR_TESTADCOUT11", + "OT": "MONITOR_OT", + "DI11": "MONITOR_DI11", + "TESTADCIN14": "MONITOR_TESTADCIN14", + "TESTADCIN213": "MONITOR_TESTADCIN213", + "TESTENJTAG": "MONITOR_TESTENJTAG", + "VAUXP7": null, + "VAUXN8": "MONITOR_VAUXN8", + "TESTADCIN27": "MONITOR_TESTADCIN27", + "TESTADCIN10": "MONITOR_TESTADCIN10", + "VAUXN0": "MONITOR_VAUXN0", + "VAUXP5": "MONITOR_VAUXP5", + "DI15": "MONITOR_DI15", + "TESTADCIN18": "MONITOR_TESTADCIN18", + "VAUXP14": null, + "ALM3": "MONITOR_ALM3", + "DI12": "MONITOR_DI12", + "DO15": "MONITOR_DO15", + "ALM6": "MONITOR_ALM6", + "VAUXN14": null, + "TESTDRCK": "MONITOR_TESTDRCK", + "TESTSCANMODE2": "MONITOR_TESTSCANMODE2", + "TESTADCIN2": "MONITOR_TESTADCIN2", + "VAUXP3": "MONITOR_VAUXP3", + "TESTADCIN8": "MONITOR_TESTADCIN8", + "ALM7": "MONITOR_ALM7", + "VAUXP11": "MONITOR_VAUXP11", + "CHANNEL2": "MONITOR_CHANNEL2", + "ALM1": "MONITOR_ALM1", + "MUXADDR0": "MONITOR_MUXADDR0", + "TESTDB7": "MONITOR_TESTDB7", + "TESTADCIN3": "MONITOR_TESTADCIN3", + "TESTADCOUT12": "MONITOR_TESTADCOUT12", + "VAUXP6": null, + "TESTSE3": "MONITOR_TESTSE3", + "ALM5": "MONITOR_ALM5", + "TESTADCIN0": "MONITOR_TESTADCIN0", + "TESTADCOUT17": "MONITOR_TESTADCOUT17", + "TESTSE2": "MONITOR_TESTSE2", + "DO10": "MONITOR_DO10", + "TESTADCOUT16": "MONITOR_TESTADCOUT16", + "TESTSI3": "MONITOR_TESTSI3", + "TESTSCANCLK1": "MONITOR_TESTSCANCLK1", + "TESTADCOUT2": "MONITOR_TESTADCOUT2", + "VAUXN15": null, + "DO0": "MONITOR_DO0", + "DI6": "MONITOR_DI6", + "DI8": "MONITOR_DI8", + "DADDR0": "MONITOR_DADDR0", + "TESTCAPTURE": "MONITOR_TESTCAPTURE", + "TESTADCIN19": "MONITOR_TESTADCIN19", + "TESTADCIN6": "MONITOR_TESTADCIN6", + "TESTDB10": "MONITOR_TESTDB10", + "TESTADCIN17": "MONITOR_TESTADCIN17", + "TESTADCIN12": "MONITOR_TESTADCIN12", + "TESTADCIN217": "MONITOR_TESTADCIN217", + "DI3": "MONITOR_DI3", + "TESTSEL": "MONITOR_TESTSEL", + "VAUXN2": "MONITOR_VAUXN2", + "TESTDB5": "MONITOR_TESTDB5", + "VAUXN4": "MONITOR_VAUXN4", + "TESTSI1": "MONITOR_TESTSI1", + "TESTSI4": "MONITOR_TESTSI4", + "TESTDB3": "MONITOR_TESTDB3", + "TESTADCIN26": "MONITOR_TESTADCIN26", + "DADDR3": "MONITOR_DADDR3", + "BUSY": "MONITOR_BUSY", + "CHANNEL0": "MONITOR_CHANNEL0", + "MUXADDR2": "MONITOR_MUXADDR2", + "VAUXN10": "MONITOR_VAUXN10", + "TESTADCOUT3": "MONITOR_TESTADCOUT3", + "TESTUPDATE": "MONITOR_TESTUPDATE", + "VAUXP0": "MONITOR_VAUXP0", + "TESTSCANCLK0": "MONITOR_TESTSCANCLK0", + "TESTDB15": "MONITOR_TESTDB15", + "DI0": "MONITOR_DI0", + "TESTADCOUT1": "MONITOR_TESTADCOUT1", + "DI9": "MONITOR_DI9", + "TESTADCIN24": "MONITOR_TESTADCIN24", + "TESTADCIN215": "MONITOR_TESTADCIN215", + "CHANNEL1": "MONITOR_CHANNEL1", + "TESTADCIN212": "MONITOR_TESTADCIN212", + "DO5": "MONITOR_DO5", + "DADDR6": "MONITOR_DADDR6", + "TESTADCIN7": "MONITOR_TESTADCIN7", + "CONVST": "MONITOR_CONVST", + "DO11": "MONITOR_DO11", + "TESTSI0": "MONITOR_TESTSI0", + "DI5": "MONITOR_DI5", + "TESTADCIN21": "MONITOR_TESTADCIN21", + "JTAGLOCKED": "MONITOR_JTAGLOCKED", + "VAUXP8": "MONITOR_VAUXP8", + "TESTDB11": "MONITOR_TESTDB11", + "TESTSCANCLK2": "MONITOR_TESTSCANCLK2", + "VAUXP4": "MONITOR_VAUXP4", + "VAUXN13": null, + "DADDR1": "MONITOR_DADDR1", + "TESTRST": "MONITOR_TESTRST", + "DADDR4": "MONITOR_DADDR4", + "DADDR2": "MONITOR_DADDR2", + "TESTDB4": "MONITOR_TESTDB4", + "VAUXN6": null, + "CHANNEL4": "MONITOR_CHANNEL4", + "TESTSO0": "MONITOR_TESTSO0", + "VN": "MONITOR_VN", + "TESTADCOUT18": "MONITOR_TESTADCOUT18", + "TESTADCIN5": "MONITOR_TESTADCIN5", + "JTAGMODIFIED": "MONITOR_JTAGMODIFIED", + "TESTADCOUT19": "MONITOR_TESTADCOUT19", + "DRDY": "MONITOR_DRDY", + "VAUXP1": "MONITOR_VAUXP1", + "DI14": "MONITOR_DI14", + "CONVSTCLK": "MONITOR_CONVSTCLK", + "TESTADCIN20": "MONITOR_TESTADCIN20", + "TESTADCOUT7": "MONITOR_TESTADCOUT7", + "DO6": "MONITOR_DO6", + "JTAGBUSY": "MONITOR_JTAGBUSY", + "TESTADCOUT14": "MONITOR_TESTADCOUT14", + "DO8": "MONITOR_DO8", + "TESTTDO": "MONITOR_TESTTDO", + "VAUXN3": "MONITOR_VAUXN3", + "TESTSE0": "MONITOR_TESTSE0", + "TESTADCIN15": "MONITOR_TESTADCIN15", + "TESTSCANMODE0": "MONITOR_TESTSCANMODE0", + "VAUXN9": "MONITOR_VAUXN9", + "VAUXP13": null, + "TESTADCCLK1": "MONITOR_TESTADCCLK1", + "VAUXN11": "MONITOR_VAUXN11", + "TESTADCIN25": "MONITOR_TESTADCIN25", + "TESTDB8": "MONITOR_TESTDB8", + "DO4": "MONITOR_DO4", + "TESTADCIN211": "MONITOR_TESTADCIN211", + "EOS": "MONITOR_EOS", + "VAUXP12": "MONITOR_VAUXP12", + "DI4": "MONITOR_DI4", + "DO9": "MONITOR_DO9", + "TESTADCOUT5": "MONITOR_TESTADCOUT5", + "MUXADDR4": "MONITOR_MUXADDR4", + "TESTADCOUT10": "MONITOR_TESTADCOUT10", + "TESTSE4": "MONITOR_TESTSE4", + "TESTSCANCLK3": "MONITOR_TESTSCANCLK3", + "VAUXN5": "MONITOR_VAUXN5", + "TESTDB9": "MONITOR_TESTDB9", + "TESTSHIFT": "MONITOR_TESTSHIFT", + "TESTADCCLK0": "MONITOR_TESTADCCLK0", + "ALM0": "MONITOR_ALM0", + "VAUXN7": null, + "TESTADCIN1": "MONITOR_TESTADCIN1", + "RESET": "MONITOR_RESET", + "TESTTDI": "MONITOR_TESTTDI", + "TESTADCIN218": "MONITOR_TESTADCIN218", + "TESTADCIN214": "MONITOR_TESTADCIN214", + "TESTSCANMODE3": "MONITOR_TESTSCANMODE3", + "DCLK": "MONITOR_DCLK", + "TESTDB12": "MONITOR_TESTDB12", + "DI7": "MONITOR_DI7", + "VAUXP10": "MONITOR_VAUXP10", + "DI2": "MONITOR_DI2", + "TESTSCANCLK4": "MONITOR_TESTSCANCLK4", + "DADDR5": "MONITOR_DADDR5", + "ALM4": "MONITOR_ALM4", + "TESTSO4": "MONITOR_TESTSO4", + "TESTADCOUT4": "MONITOR_TESTADCOUT4", + "TESTADCIN23": "MONITOR_TESTADCIN23", + "TESTADCCLK2": "MONITOR_TESTADCCLK2", + "TESTSO2": "MONITOR_TESTSO2", + "TESTADCOUT15": "MONITOR_TESTADCOUT15", + "DO14": "MONITOR_DO14", + "DO12": "MONITOR_DO12", + "TESTADCOUT6": "MONITOR_TESTADCOUT6", + "VAUXN12": "MONITOR_VAUXN12", + "TESTADCCLK3": "MONITOR_TESTADCCLK3", + "DI13": "MONITOR_DI13", + "TESTSCANRESET": "MONITOR_TESTSCANRESET", + "DO13": "MONITOR_DO13", + "TESTSO3": "MONITOR_TESTSO3", + "TESTSCANMODE4": "MONITOR_TESTSCANMODE4", + "TESTADCOUT9": "MONITOR_TESTADCOUT9", + "TESTDB0": "MONITOR_TESTDB0", + "VAUXP15": null, + "ALM2": "MONITOR_ALM2", + "VAUXP2": "MONITOR_VAUXP2", + "DO3": "MONITOR_DO3", + "DI1": "MONITOR_DI1", + "TESTSE1": "MONITOR_TESTSE1", + "TESTADCOUT0": "MONITOR_TESTADCOUT0", + "TESTADCIN219": "MONITOR_TESTADCIN219", + "TESTADCOUT13": "MONITOR_TESTADCOUT13", + "TESTADCOUT8": "MONITOR_TESTADCOUT8", + "TESTADCIN210": "MONITOR_TESTADCIN210", + "DO1": "MONITOR_DO1", + "VAUXN1": "MONITOR_VAUXN1", + "VP": "MONITOR_VP", + "DWE": "MONITOR_DWE", + "DO2": "MONITOR_DO2", + "TESTADCIN22": "MONITOR_TESTADCIN22", + "TESTDB2": "MONITOR_TESTDB2", + "EOC": "MONITOR_EOC", + "MUXADDR3": "MONITOR_MUXADDR3", + "MUXADDR1": "MONITOR_MUXADDR1", + "TESTADCIN4": "MONITOR_TESTADCIN4", + "DO7": "MONITOR_DO7", + "TESTADCIN16": "MONITOR_TESTADCIN16", + "DI10": "MONITOR_DI10", + "TESTADCIN9": "MONITOR_TESTADCIN9", + "TESTADCIN29": "MONITOR_TESTADCIN29", + "TESTADCIN28": "MONITOR_TESTADCIN28", + "TESTDB6": "MONITOR_TESTDB6", + "CHANNEL3": "MONITOR_CHANNEL3", + "VAUXP9": "MONITOR_VAUXP9", + "TESTSCANMODE1": "MONITOR_TESTSCANMODE1" + }, + "x_coord": 0 + } + ], + "wires": [ + "MONITOR_BYP1_6", + "MONITOR_SE4BEG0_6", + "MONITOR_IMUX5_6", + "MONITOR_LH12_4", + "MONITOR_LOGIC_OUTS_B2_9", + "MONITOR_CTRL0_8", + "MONITOR_EE4C1_8", + "MONITOR_IMUX36_2", + "MONITOR_IMUX35_4", + "MONITOR_WW4C1_3", + "MONITOR_EE4B3_8", + "MONITOR_EE2A1_7", + "MONITOR_NW2A2_8", + "MONITOR_EE2BEG1_0", + "MONITOR_ALM5", + "MONITOR_BYP2_4", + "MONITOR_NW4END2_3", + "MONITOR_BLOCK_OUTS_B2_3", + "MONITOR_LOGIC_OUTS_B0_7", + "MONITOR_CLK0_2", + "MONITOR_LOGIC_OUTS_B8_3", + "MONITOR_WW4END0_0", + "MONITOR_WW2A0_4", + "MONITOR_EE2BEG2_6", + "MONITOR_EE4A1_7", + "MONITOR_IMUX37_2", + "MONITOR_WW2END3_1", + "MONITOR_LH2_4", + "MONITOR_WL1END1_8", + "MONITOR_EE4B2_2", + "MONITOR_FAN4_3", + "MONITOR_IMUX34_5", + "MONITOR_WW2END1_5", + "MONITOR_BYP2_2", + "MONITOR_WW2A1_2", + "MONITOR_EE2A3_0", + "MONITOR_WW2END3_0", + "MONITOR_SE2A2_3", + "MONITOR_NW4A2_8", + "MONITOR_EE2BEG2_0", + "MONITOR_LOGIC_OUTS_B8_0", + "MONITOR_NE4BEG0_8", + "MONITOR_SW4END3_4", + "MONITOR_EE4C3_6", + "MONITOR_EE4BEG3_4", + "MONITOR_WL1END3_8", + "MONITOR_LOGIC_OUTS_B15_8", + "MONITOR_WW4B1_9", + "MONITOR_LOGIC_OUTS_B23_7", + "MONITOR_EE4C0_3", + "MONITOR_EE4B2_1", + "MONITOR_WW4B3_3", + "MONITOR_NE4C0_6", + "MONITOR_IMUX45_6", + "MONITOR_SE2A1_5", + "MONITOR_DI13", + "MONITOR_SE4C2_6", + "MONITOR_NE2A2_7", + "MONITOR_IMUX29_0", + "MONITOR_IMUX19_0", + "MONITOR_TESTSCANRESET", + "MONITOR_LH1_2", + "MONITOR_ALM7", + "MONITOR_BYP7_7", + "MONITOR_BYP5_0", + "MONITOR_LH1_9", + "MONITOR_NE4C3_1", + "MONITOR_EL1BEG0_8", + "MONITOR_SW4END1_4", + "MONITOR_EE2A1_0", + "MONITOR_TESTADCIN23", + "MONITOR_ER1BEG3_9", + "MONITOR_SE2A0_6", + "MONITOR_IMUX34_0", + "MONITOR_SE4BEG1_5", + "MONITOR_LOGIC_OUTS_B3_6", + "MONITOR_IMUX32_6", + "MONITOR_IMUX27_1", + "MONITOR_IMUX38_7", + "MONITOR_NW2A2_1", + "MONITOR_LOGIC_OUTS_B23_2", + "MONITOR_EE4A3_3", + "MONITOR_CLK0_8", + "MONITOR_IMUX21_8", + "MONITOR_WW2A2_2", + "MONITOR_IMUX42_4", + "MONITOR_WW4A0_6", + "MONITOR_SE2A2_2", + "MONITOR_WW4C1_8", + "MONITOR_WW4B0_7", + "MONITOR_SE4C3_9", + "MONITOR_SW4A0_9", + "MONITOR_BYP4_0", + "MONITOR_LH7_7", + "MONITOR_WW4A0_9", + "MONITOR_IMUX28_8", + "MONITOR_IMUX30_5", + "MONITOR_LOGIC_OUTS_B10_6", + "MONITOR_LOGIC_OUTS_B19_6", + "MONITOR_IMUX25_7", + "MONITOR_CHANNEL0", + "MONITOR_IMUX18_4", + "MONITOR_LOGIC_OUTS_B19_8", + "MONITOR_WW4B0_0", + "MONITOR_LH1_3", + "MONITOR_SW2A2_8", + "MONITOR_WW4A1_5", + "MONITOR_ER1BEG3_1", + "MONITOR_SE4C0_0", + "MONITOR_IMUX0_8", + "MONITOR_LH5_0", + "MONITOR_IMUX13_4", + "MONITOR_EE4A1_0", + "MONITOR_LH12_0", + "MONITOR_BYP0_5", + "MONITOR_EOS", + "MONITOR_CHANNEL3", + "MONITOR_TESTADCOUT11", + "MONITOR_LOGIC_OUTS_B6_9", + "MONITOR_IMUX34_9", + "MONITOR_SE4C1_9", + "MONITOR_IMUX3_1", + "MONITOR_EE4C2_6", + "MONITOR_NE2A1_8", + "MONITOR_CLK0_3", + "MONITOR_WR1END1_0", + "MONITOR_LOGIC_OUTS_B20_6", + "MONITOR_SW4A0_8", + "MONITOR_FAN7_6", + "MONITOR_IMUX40_9", + "MONITOR_IMUX17_9", + "MONITOR_NE2A0_7", + "MONITOR_IMUX36_0", + "MONITOR_EE4C2_4", + "MONITOR_LOGIC_OUTS_B10_3", + "MONITOR_BYP1_8", + "MONITOR_EL1BEG2_8", + "MONITOR_NE2A3_1", + "MONITOR_LH4_4", + "MONITOR_LOGIC_OUTS_B6_7", + "MONITOR_IMUX16_3", + "MONITOR_VAUXP15", + "MONITOR_IMUX40_1", + "MONITOR_EE4C3_4", + "MONITOR_WW4A0_0", + "MONITOR_IMUX0_3", + "MONITOR_LH6_2", + "MONITOR_IMUX4_0", + "MONITOR_BLOCK_OUTS_B1_2", + "MONITOR_TESTADCOUT2", + "MONITOR_WL1END1_3", + "MONITOR_SE4C2_5", + "MONITOR_SE4BEG3_2", + "MONITOR_EE2BEG0_9", + "MONITOR_EE4BEG0_1", + "MONITOR_IMUX23_8", + "MONITOR_SE4BEG3_9", + "MONITOR_IMUX33_9", + "MONITOR_IMUX5_9", + "MONITOR_NW4A3_2", + "MONITOR_EE2A3_1", + "MONITOR_EL1BEG2_2", + "MONITOR_WR1END2_2", + "MONITOR_IMUX8_9", + "MONITOR_WW4C2_1", + "MONITOR_EE2BEG0_8", + "MONITOR_NE4C2_2", + "MONITOR_WL1END3_6", + "MONITOR_VERT_VAUXN5", + "MONITOR_NE4BEG0_6", + "MONITOR_SW4END0_8", + "MONITOR_EE2A1_9", + "MONITOR_LOGIC_OUTS_B12_3", + "MONITOR_TESTDB4", + "MONITOR_SW4A2_1", + "MONITOR_WW2END0_7", + "MONITOR_SW4END3_5", + "MONITOR_LH2_9", + "MONITOR_IMUX40_8", + "MONITOR_IMUX30_0", + "MONITOR_EL1BEG1_3", + "MONITOR_SW4A3_2", + "MONITOR_TESTADCIN6", + "MONITOR_LOGIC_OUTS_B13_3", + "MONITOR_NE4C2_9", + "MONITOR_SW4A2_4", + "MONITOR_LOGIC_OUTS_B0_0", + "MONITOR_SW4END2_4", + "MONITOR_TESTSEL", + "MONITOR_LH5_1", + "MONITOR_WW2END0_9", + "MONITOR_WW4C2_5", + "MONITOR_EE4A1_4", + "MONITOR_IMUX23_7", + "MONITOR_EE4C2_5", + "MONITOR_WW2A1_7", + "MONITOR_SE4BEG0_5", + "MONITOR_NE2A2_4", + "MONITOR_LOGIC_OUTS_B10_9", + "MONITOR_IMUX46_1", + "MONITOR_DO10", + "MONITOR_NW4END3_9", + "MONITOR_FAN5_8", + "MONITOR_ER1BEG0_4", + "MONITOR_TESTADCIN26", + "MONITOR_IMUX25_5", + "MONITOR_LH4_9", + "MONITOR_IMUX29_6", + "MONITOR_IMUX1_9", + "MONITOR_LOGIC_OUTS_B10_4", + "MONITOR_IMUX13_9", + "MONITOR_WW4C3_5", + "MONITOR_ER1BEG1_3", + "MONITOR_IMUX40_2", + "MONITOR_LOGIC_OUTS_B8_2", + "MONITOR_WR1END2_9", + "MONITOR_LH12_8", + "MONITOR_IMUX36_8", + "MONITOR_IMUX41_2", + "MONITOR_IMUX21_3", + "MONITOR_EE4C0_4", + "MONITOR_FAN6_2", + "MONITOR_SW4A2_9", + "MONITOR_NW2A1_8", + "MONITOR_EL1BEG3_0", + "MONITOR_IMUX45_5", + "MONITOR_CONVST", + "MONITOR_FAN0_9", + "MONITOR_LOGIC_OUTS_B18_8", + "MONITOR_SE4C0_5", + "MONITOR_LOGIC_OUTS_B0_2", + "MONITOR_LOGIC_OUTS_B7_7", + "MONITOR_SW2A0_3", + "MONITOR_SE4C1_7", + "MONITOR_EE4A3_8", + "MONITOR_CLK0_9", + "MONITOR_FAN7_3", + "MONITOR_NW4END1_2", + "MONITOR_WW2END1_2", + "MONITOR_WW4A2_0", + "MONITOR_SE4C2_7", + "MONITOR_WW4B0_4", + "MONITOR_NW4END3_0", + "MONITOR_TESTADCIN3", + "MONITOR_LOGIC_OUTS_B16_9", + "MONITOR_IMUX31_8", + "MONITOR_LH8_0", + "MONITOR_FAN1_5", + "MONITOR_IMUX41_8", + "MONITOR_EL1BEG1_4", + "MONITOR_IMUX34_4", + "MONITOR_IMUX29_3", + "MONITOR_DI10", + "MONITOR_EE2BEG0_6", + "MONITOR_IMUX36_5", + "MONITOR_VERT_VAUXN8", + "MONITOR_IMUX7_5", + "MONITOR_LH6_6", + "MONITOR_EE4C2_0", + "MONITOR_EE4C1_6", + "MONITOR_NW4END1_5", + "MONITOR_WR1END2_5", + "MONITOR_IMUX30_3", + "MONITOR_IMUX4_4", + "MONITOR_NE4BEG1_3", + "MONITOR_BLOCK_OUTS_B2_7", + "MONITOR_VAUXP14", + "MONITOR_TESTTDO", + "MONITOR_LH3_2", + "MONITOR_SW4END0_0", + "MONITOR_LH10_1", + "MONITOR_IMUX29_9", + "MONITOR_EE4BEG3_0", + "MONITOR_TESTADCOUT0", + "MONITOR_IMUX28_1", + "MONITOR_WL1END1_7", + "MONITOR_SW2A2_9", + "MONITOR_TESTSI4", + "MONITOR_LOGIC_OUTS_B10_2", + "MONITOR_WL1END1_0", + "MONITOR_SE4BEG2_1", + "MONITOR_NW4END2_7", + "MONITOR_SW4A3_9", + "MONITOR_SE4C0_1", + "MONITOR_EE4BEG0_0", + "MONITOR_BYP3_0", + "MONITOR_EE4B0_0", + "MONITOR_SW4END2_9", + "MONITOR_TESTADCIN4", + "MONITOR_EE2BEG0_2", + "MONITOR_BYP2_5", + "MONITOR_WW4A1_8", + "MONITOR_EE4C0_1", + "MONITOR_DO15", + "MONITOR_SW4END1_6", + "MONITOR_EE4BEG2_6", + "MONITOR_HORIZ_VAUXP11", + "MONITOR_IMUX8_6", + "MONITOR_EE4BEG3_5", + "MONITOR_IMUX3_3", + "MONITOR_LH10_5", + "MONITOR_CTRL0_1", + "MONITOR_WR1END2_8", + "MONITOR_WR1END3_8", + "MONITOR_WW4END0_1", + "MONITOR_NE4C0_4", + "MONITOR_WW2END1_9", + "MONITOR_WW4END3_3", + "MONITOR_EE4A3_9", + "MONITOR_EE2A1_2", + "MONITOR_LH11_5", + "MONITOR_WW4C3_0", + "MONITOR_TESTADCIN25", + "MONITOR_EE2BEG2_8", + "MONITOR_VAUXP8", + "MONITOR_JTAGMODIFIED", + "MONITOR_IMUX46_0", + "MONITOR_BLOCK_OUTS_B0_7", + "MONITOR_SW4END0_2", + "MONITOR_LOGIC_OUTS_B22_1", + "MONITOR_EL1BEG1_0", + "MONITOR_EL1BEG1_7", + "MONITOR_LOGIC_OUTS_B18_2", + "MONITOR_WW4B3_6", + "MONITOR_NW2A0_0", + "MONITOR_EE2BEG2_3", + "MONITOR_NE2A1_7", + "MONITOR_LOGIC_OUTS_B9_2", + "MONITOR_EE4A3_1", + "MONITOR_HORIZ_VAUXP4_LEFT", + "MONITOR_LOGIC_OUTS_B2_6", + "MONITOR_WR1END0_6", + "MONITOR_NW4END0_5", + "MONITOR_LOGIC_OUTS_B3_4", + "MONITOR_SE2A1_4", + "MONITOR_WW2END0_8", + "MONITOR_ALM1", + "MONITOR_WW4B1_6", + "MONITOR_EE4C0_9", + "MONITOR_LOGIC_OUTS_B9_4", + "MONITOR_LOGIC_OUTS_B3_3", + "MONITOR_BYP4_6", + "MONITOR_TESTDB5", + "MONITOR_WW2END0_4", + "MONITOR_NW4A1_2", + "MONITOR_WW4B3_5", + "MONITOR_FAN2_3", + "MONITOR_HORIZ_VAUXN12_LEFT", + "MONITOR_IMUX26_0", + "MONITOR_WW4C0_2", + "MONITOR_WR1END2_7", + "MONITOR_IMUX33_0", + "MONITOR_EE4C3_0", + "MONITOR_LOGIC_OUTS_B7_4", + "MONITOR_FAN3_5", + "MONITOR_DADDR0", + "MONITOR_SE4C1_3", + "MONITOR_TESTTDI", + "MONITOR_EL1BEG1_5", + "MONITOR_WW2A2_8", + "MONITOR_SW2A2_1", + "MONITOR_IMUX7_2", + "MONITOR_ER1BEG2_0", + "MONITOR_IMUX18_9", + "MONITOR_EL1BEG1_8", + "MONITOR_LH6_3", + "MONITOR_LH9_0", + "MONITOR_IMUX22_2", + "MONITOR_IMUX13_6", + "MONITOR_VAUXP11", + "MONITOR_DI9", + "MONITOR_WR1END0_0", + "MONITOR_SW2A3_8", + "MONITOR_IMUX8_4", + "MONITOR_NW2A1_3", + "MONITOR_WW4C0_3", + "MONITOR_SW4A1_9", + "MONITOR_WW4B0_1", + "MONITOR_IMUX15_6", + "MONITOR_WW2A2_6", + "MONITOR_DO9", + "MONITOR_LOGIC_OUTS_B20_1", + "MONITOR_FAN7_1", + "MONITOR_IMUX24_9", + "MONITOR_EL1BEG2_7", + "MONITOR_IMUX31_0", + "MONITOR_WL1END0_3", + "MONITOR_FAN4_8", + "MONITOR_DI6", + "MONITOR_NW4END0_3", + "MONITOR_NE4C3_6", + "MONITOR_LOGIC_OUTS_B21_0", + "MONITOR_TESTADCIN5", + "MONITOR_LOGIC_OUTS_B1_4", + "MONITOR_TESTDB15", + "MONITOR_SE4C0_4", + "MONITOR_CLK1_8", + "MONITOR_BLOCK_OUTS_B3_5", + "MONITOR_SE4BEG0_4", + "MONITOR_NW2A1_5", + "MONITOR_IMUX2_2", + "MONITOR_IMUX25_0", + "MONITOR_IMUX4_3", + "MONITOR_SW2A1_8", + "MONITOR_LH10_3", + "MONITOR_IMUX33_2", + "MONITOR_ER1BEG2_9", + "MONITOR_LOGIC_OUTS_B17_4", + "MONITOR_BYP5_4", + "MONITOR_IMUX32_5", + "MONITOR_LOGIC_OUTS_B7_9", + "MONITOR_LOGIC_OUTS_B12_2", + "MONITOR_SW4END1_8", + "MONITOR_LOGIC_OUTS_B1_0", + "MONITOR_IMUX38_6", + "MONITOR_NW4A3_8", + "MONITOR_WW2A3_4", + "MONITOR_LH12_2", + "MONITOR_LOGIC_OUTS_B22_5", + "MONITOR_EE2BEG1_1", + "MONITOR_WW4A2_6", + "MONITOR_SE4C3_2", + "MONITOR_SW4END1_1", + "MONITOR_FAN0_2", + "MONITOR_WW4B2_9", + "MONITOR_IMUX41_7", + "MONITOR_WW4B1_5", + "MONITOR_FAN0_8", + "MONITOR_VERT_VAUXN7", + "MONITOR_BLOCK_OUTS_B1_0", + "MONITOR_LOGIC_OUTS_B14_7", + "MONITOR_LH3_7", + "MONITOR_IMUX29_2", + "MONITOR_IMUX0_4", + "MONITOR_NE2A2_6", + "MONITOR_WW4C2_6", + "MONITOR_EL1BEG0_0", + "MONITOR_EE4B2_8", + "MONITOR_IMUX30_2", + "MONITOR_TESTADCIN15", + "MONITOR_EL1BEG2_5", + "MONITOR_NW4A2_3", + "MONITOR_WW2A0_2", + "MONITOR_LOGIC_OUTS_B16_2", + "MONITOR_LH3_9", + "MONITOR_IMUX1_5", + "MONITOR_BYP1_2", + "MONITOR_LOGIC_OUTS_B23_5", + "MONITOR_HORIZ_VAUXP5_LEFT", + "MONITOR_LOGIC_OUTS_B4_5", + "MONITOR_NW2A0_3", + "MONITOR_ER1BEG3_5", + "MONITOR_LOGIC_OUTS_B15_0", + "MONITOR_SW4END3_0", + "MONITOR_TESTSCANCLK1", + "MONITOR_IMUX40_4", + "MONITOR_IMUX47_1", + "MONITOR_IMUX26_6", + "MONITOR_NE4BEG1_6", + "MONITOR_LOGIC_OUTS_B13_7", + "MONITOR_LOGIC_OUTS_B15_6", + "MONITOR_WW2END1_7", + "MONITOR_FAN5_9", + "MONITOR_LOGIC_OUTS_B5_7", + "MONITOR_IMUX27_5", + "MONITOR_NE4BEG2_9", + "MONITOR_WL1END0_4", + "MONITOR_ER1BEG0_3", + "MONITOR_IMUX45_2", + "MONITOR_WL1END0_2", + "MONITOR_NW4A1_6", + "MONITOR_LOGIC_OUTS_B12_6", + "MONITOR_IMUX34_3", + "MONITOR_LH9_8", + "MONITOR_TESTADCOUT6", + "MONITOR_IMUX23_4", + "MONITOR_SE2A0_4", + "MONITOR_NE2A3_2", + "MONITOR_IMUX21_2", + "MONITOR_EE4C2_2", + "MONITOR_VERT_VAUXP9", + "MONITOR_IMUX5_5", + "MONITOR_NW2A0_6", + "MONITOR_CTRL1_5", + "MONITOR_SW2A1_1", + "MONITOR_WL1END0_7", + "MONITOR_ER1BEG1_7", + "MONITOR_IMUX13_3", + "MONITOR_BYP4_3", + "MONITOR_LOGIC_OUTS_B0_1", + "MONITOR_IMUX24_0", + "MONITOR_IMUX37_1", + "MONITOR_NE4C1_3", + "MONITOR_BYP2_9", + "MONITOR_WL1END2_9", + "MONITOR_EE4A3_4", + "MONITOR_IMUX11_2", + "MONITOR_EE4A0_1", + "MONITOR_NE4C2_3", + "MONITOR_NE4BEG2_3", + "MONITOR_LOGIC_OUTS_B7_3", + "MONITOR_EE4BEG2_1", + "MONITOR_SW4END3_8", + "MONITOR_WR1END3_2", + "MONITOR_EE4B2_6", + "MONITOR_CTRL0_7", + "MONITOR_LH12_7", + "MONITOR_NE4BEG2_0", + "MONITOR_IMUX3_9", + "MONITOR_WW4B0_9", + "MONITOR_WW4END3_9", + "MONITOR_SE4C3_1", + "MONITOR_LH7_0", + "MONITOR_TESTADCIN10", + "MONITOR_VERT_VAUXP6", + "MONITOR_IMUX2_6", + "MONITOR_NW4A0_0", + "MONITOR_EE2A3_5", + "MONITOR_IMUX16_0", + "MONITOR_EE4B0_8", + "MONITOR_BYP4_4", + "MONITOR_NW4END3_1", + "MONITOR_EE2A0_7", + "MONITOR_VAUXN1", + "MONITOR_CLK1_2", + "MONITOR_IMUX10_1", + "MONITOR_NW4A0_8", + "MONITOR_IMUX5_4", + "MONITOR_WW4C3_2", + "MONITOR_ALM0", + "MONITOR_IMUX41_3", + "MONITOR_LH8_5", + "MONITOR_FAN6_3", + "MONITOR_IMUX12_3", + "MONITOR_SW4A1_7", + "MONITOR_EE4BEG3_6", + "MONITOR_IMUX4_7", + "MONITOR_IMUX4_2", + "MONITOR_SW4A1_5", + "MONITOR_EE4B3_9", + "MONITOR_IMUX6_3", + "MONITOR_WL1END2_5", + "MONITOR_EE4A2_6", + "MONITOR_IMUX17_0", + "MONITOR_IMUX32_9", + "MONITOR_WW2A2_9", + "MONITOR_LOGIC_OUTS_B16_5", + "MONITOR_DO11", + "MONITOR_LOGIC_OUTS_B23_0", + "MONITOR_SE4BEG1_2", + "MONITOR_IMUX32_4", + "MONITOR_LOGIC_OUTS_B10_8", + "MONITOR_NW4A1_0", + "MONITOR_WW4B0_5", + "MONITOR_NE4C3_2", + "MONITOR_IMUX20_3", + "MONITOR_LH11_4", + "MONITOR_EE4C2_9", + "MONITOR_DADDR3", + "MONITOR_VAUXN14", + "MONITOR_LH11_1", + "MONITOR_SE2A3_3", + "MONITOR_EE4A3_6", + "MONITOR_LOGIC_OUTS_B21_8", + "MONITOR_SE4C2_1", + "MONITOR_NW4A2_5", + "MONITOR_NE4C1_4", + "MONITOR_LOGIC_OUTS_B11_3", + "MONITOR_FAN4_2", + "MONITOR_EE4A2_2", + "MONITOR_LOGIC_OUTS_B5_9", + "MONITOR_NE4C0_3", + "MONITOR_SW4END1_2", + "MONITOR_IMUX43_7", + "MONITOR_LOGIC_OUTS_B8_1", + "MONITOR_EE4C0_6", + "MONITOR_BYP4_9", + "MONITOR_DO4", + "MONITOR_IMUX37_0", + "MONITOR_FAN0_5", + "MONITOR_WW4END0_8", + "MONITOR_WW4B1_8", + "MONITOR_TESTDRCK", + "MONITOR_SE4C2_4", + "MONITOR_WR1END1_4", + "MONITOR_IMUX4_6", + "MONITOR_DO2", + "MONITOR_ER1BEG2_4", + "MONITOR_IMUX14_8", + "MONITOR_WW2END1_6", + "MONITOR_WW4A2_2", + "MONITOR_WW4B2_6", + "MONITOR_SW4A0_2", + "MONITOR_FAN7_7", + "MONITOR_IMUX46_2", + "MONITOR_IMUX16_2", + "MONITOR_IMUX25_6", + "MONITOR_IMUX0_0", + "MONITOR_IMUX43_0", + "MONITOR_IMUX38_4", + "MONITOR_EE4B0_6", + "MONITOR_LOGIC_OUTS_B9_8", + "MONITOR_LOGIC_OUTS_B20_0", + "MONITOR_IMUX31_9", + "MONITOR_FAN2_1", + "MONITOR_NE2A1_4", + "MONITOR_LH2_6", + "MONITOR_IMUX43_9", + "MONITOR_WL1END1_2", + "MONITOR_DI7", + "MONITOR_IMUX39_1", + "MONITOR_LOGIC_OUTS_B21_7", + "MONITOR_EE4C3_3", + "MONITOR_LH7_2", + "MONITOR_WW4A0_3", + "MONITOR_NE4BEG1_7", + "MONITOR_VERT_VAUXN2", + "MONITOR_LH11_9", + "MONITOR_WW2END3_9", + "MONITOR_CLK0_4", + "MONITOR_NW2A1_4", + "MONITOR_EL1BEG1_2", + "MONITOR_TESTADCOUT15", + "MONITOR_FAN1_6", + "MONITOR_TESTDB7", + "MONITOR_EE4C1_5", + "MONITOR_VAUXP13", + "MONITOR_BYP1_7", + "MONITOR_IMUX18_0", + "MONITOR_WW4A2_5", + "MONITOR_ER1BEG0_1", + "MONITOR_WW4C3_9", + "MONITOR_NW4END0_4", + "MONITOR_DI11", + "MONITOR_LH4_2", + "MONITOR_IMUX28_3", + "MONITOR_TESTADCIN21", + "MONITOR_SE2A3_7", + "MONITOR_EL1BEG0_4", + "MONITOR_SW4END0_4", + "MONITOR_NE4C0_2", + "MONITOR_NE4C1_1", + "MONITOR_WW4END2_0", + "MONITOR_LH3_1", + "MONITOR_SE2A3_4", + "MONITOR_VAUXN5", + "MONITOR_ER1BEG3_8", + "MONITOR_IMUX39_8", + "MONITOR_LOGIC_OUTS_B21_1", + "MONITOR_IMUX18_3", + "MONITOR_TESTADCIN210", + "MONITOR_NW4A3_9", + "MONITOR_NE2A1_5", + "MONITOR_FAN0_4", + "MONITOR_LOGIC_OUTS_B6_5", + "MONITOR_BYP0_2", + "MONITOR_IMUX12_6", + "MONITOR_WR1END1_6", + "MONITOR_WR1END3_0", + "MONITOR_LH11_2", + "MONITOR_SE2A0_8", + "MONITOR_LOGIC_OUTS_B1_5", + "MONITOR_BYP6_7", + "MONITOR_LH4_1", + "MONITOR_EE2A0_1", + "MONITOR_LOGIC_OUTS_B11_8", + "MONITOR_SW4END2_1", + "MONITOR_IMUX10_0", + "MONITOR_EL1BEG0_3", + "MONITOR_LOGIC_OUTS_B4_1", + "MONITOR_LH5_7", + "MONITOR_NW4END2_9", + "MONITOR_SW4A0_4", + "MONITOR_VERT_VAUXN15", + "MONITOR_EE4B3_1", + "MONITOR_IMUX20_6", + "MONITOR_SE4C2_3", + "MONITOR_SE4C2_2", + "MONITOR_TESTADCIN16", + "MONITOR_BYP1_9", + "MONITOR_LOGIC_OUTS_B0_5", + "MONITOR_IMUX12_7", + "MONITOR_WW4C0_9", + "MONITOR_EE4B2_9", + "MONITOR_EE2BEG2_2", + "MONITOR_WW4B2_1", + "MONITOR_BYP0_8", + "MONITOR_IMUX24_5", + "MONITOR_IMUX17_3", + "MONITOR_WW4C3_6", + "MONITOR_NE4C0_1", + "MONITOR_LH11_0", + "MONITOR_LOGIC_OUTS_B19_9", + "MONITOR_IMUX11_4", + "MONITOR_BLOCK_OUTS_B1_9", + "MONITOR_EE4C1_7", + "MONITOR_WW4C1_1", + "MONITOR_EE4C1_1", + "MONITOR_SE2A3_2", + "MONITOR_LH12_5", + "MONITOR_FAN7_0", + "MONITOR_WW4A1_9", + "MONITOR_IMUX44_2", + "MONITOR_IMUX42_8", + "MONITOR_NE4C3_3", + "MONITOR_WW4END0_4", + "MONITOR_CONVSTCLK", + "MONITOR_EE2A3_8", + "MONITOR_WW4A3_4", + "MONITOR_IMUX9_5", + "MONITOR_EE4BEG1_5", + "MONITOR_LH3_0", + "MONITOR_IMUX31_2", + "MONITOR_FAN6_6", + "MONITOR_IMUX47_8", + "MONITOR_NW2A0_4", + "MONITOR_EE4C0_2", + "MONITOR_SW4A1_8", + "MONITOR_LH6_1", + "MONITOR_IMUX35_5", + "MONITOR_LOGIC_OUTS_B6_2", + "MONITOR_LH9_9", + "MONITOR_LOGIC_OUTS_B19_2", + "MONITOR_LOGIC_OUTS_B14_4", + "MONITOR_LOGIC_OUTS_B8_4", + "MONITOR_EOC", + "MONITOR_IMUX21_7", + "MONITOR_VERT_VAUXN12", + "MONITOR_WR1END1_3", + "MONITOR_BYP1_3", + "MONITOR_SE4C3_6", + "MONITOR_NE2A2_1", + "MONITOR_HORIZ_VAUXP3", + "MONITOR_SW2A2_3", + "MONITOR_SW2A3_4", + "MONITOR_IMUX0_1", + "MONITOR_SE2A1_0", + "MONITOR_IMUX47_4", + "MONITOR_IMUX15_0", + "MONITOR_IMUX38_3", + "MONITOR_FAN3_1", + "MONITOR_IMUX14_4", + "MONITOR_DEN", + "MONITOR_ER1BEG0_8", + "MONITOR_BYP4_7", + "MONITOR_WW4A3_6", + "MONITOR_IMUX22_1", + "MONITOR_IMUX39_5", + "MONITOR_IMUX39_4", + "MONITOR_SW4END0_6", + "MONITOR_LOGIC_OUTS_B4_0", + "MONITOR_IMUX16_7", + "MONITOR_LOGIC_OUTS_B14_8", + "MONITOR_IMUX26_4", + "MONITOR_IMUX1_0", + "MONITOR_EL1BEG0_9", + "MONITOR_HORIZ_VAUXN5_LEFT", + "MONITOR_IMUX26_7", + "MONITOR_TESTDB11", + "MONITOR_LOGIC_OUTS_B17_3", + "MONITOR_EE2A1_8", + "MONITOR_IMUX31_7", + "MONITOR_EE4C1_0", + "MONITOR_LOGIC_OUTS_B18_1", + "MONITOR_BYP7_0", + "MONITOR_IMUX42_2", + "MONITOR_BYP2_0", + "MONITOR_WW4A3_9", + "MONITOR_WW4B2_7", + "MONITOR_SW4A3_5", + "MONITOR_IMUX4_1", + "MONITOR_WW2A0_7", + "MONITOR_VAUXP4", + "MONITOR_BYP0_9", + "MONITOR_IMUX45_9", + "MONITOR_VAUXN6", + "MONITOR_IMUX29_5", + "MONITOR_BYP7_3", + "MONITOR_IMUX10_5", + "MONITOR_EE4BEG0_7", + "MONITOR_NW4END0_9", + "MONITOR_NE4C0_8", + "MONITOR_EE2A1_1", + "MONITOR_IMUX4_5", + "MONITOR_NW4A0_6", + "MONITOR_NE4C0_9", + "MONITOR_WW2A0_3", + "MONITOR_TESTDB1", + "MONITOR_IMUX16_8", + "MONITOR_IMUX27_3", + "MONITOR_NW4A0_5", + "MONITOR_EE4BEG1_0", + "MONITOR_ER1BEG0_2", + "MONITOR_CLK0_0", + "MONITOR_SW4END1_9", + "MONITOR_BLOCK_OUTS_B2_9", + "MONITOR_WW2A0_5", + "MONITOR_IMUX14_6", + "MONITOR_IMUX32_2", + "MONITOR_TESTCAPTURE", + "MONITOR_TESTSI2", + "MONITOR_EE4A0_4", + "MONITOR_IMUX39_2", + "MONITOR_WL1END1_6", + "MONITOR_VAUXP7", + "MONITOR_EE4B2_4", + "MONITOR_WL1END1_1", + "MONITOR_LH7_8", + "MONITOR_SW4A2_6", + "MONITOR_DI2", + "MONITOR_LOGIC_OUTS_B14_1", + "MONITOR_WW4C2_2", + "MONITOR_LOGIC_OUTS_B16_6", + "MONITOR_WW4B0_8", + "MONITOR_LH7_1", + "MONITOR_IMUX12_8", + "MONITOR_EL1BEG2_4", + "MONITOR_IMUX10_7", + "MONITOR_SE2A1_8", + "MONITOR_CHANNEL1", + "MONITOR_BYP0_1", + "MONITOR_SW4A3_8", + "MONITOR_LH5_8", + "MONITOR_ER1BEG2_5", + "MONITOR_TESTADCIN212", + "MONITOR_SW4A3_0", + "MONITOR_NE2A3_9", + "MONITOR_LH4_5", + "MONITOR_WL1END2_6", + "MONITOR_TESTSCANCLK0", + "MONITOR_LOGIC_OUTS_B21_4", + "MONITOR_SW4A2_7", + "MONITOR_LH11_8", + "MONITOR_IMUX39_9", + "MONITOR_ER1BEG2_2", + "MONITOR_NW2A2_0", + "MONITOR_WW4B3_4", + "MONITOR_CTRL1_3", + "MONITOR_LOGIC_OUTS_B3_1", + "MONITOR_IMUX35_1", + "MONITOR_SE4BEG2_9", + "MONITOR_CLK1_9", + "MONITOR_NE4C2_7", + "MONITOR_WW2END0_5", + "MONITOR_SW2A0_5", + "MONITOR_NW4END0_7", + "MONITOR_IMUX9_1", + "MONITOR_IMUX11_1", + "MONITOR_WW4B3_1", + "MONITOR_VERT_VAUXN6", + "MONITOR_SE2A2_6", + "MONITOR_LH2_2", + "MONITOR_BYP2_3", + "MONITOR_SE4C0_7", + "MONITOR_EE2A3_6", + "MONITOR_IMUX1_1", + "MONITOR_TESTADCIN8", + "MONITOR_SW4A0_5", + "MONITOR_LOGIC_OUTS_B22_7", + "MONITOR_TESTSI0", + "MONITOR_CTRL0_5", + "MONITOR_LOGIC_OUTS_B17_7", + "MONITOR_TESTADCIN14", + "MONITOR_WW2END0_1", + "MONITOR_EE2BEG2_4", + "MONITOR_IMUX10_4", + "MONITOR_IMUX11_9", + "MONITOR_IMUX41_9", + "MONITOR_LH8_7", + "MONITOR_SW2A1_7", + "MONITOR_IMUX1_2", + "MONITOR_NE4C1_9", + "MONITOR_SEG_VN", + "MONITOR_TESTSCANMODE1", + "MONITOR_IMUX5_0", + "MONITOR_IMUX23_9", + "MONITOR_LH12_9", + "MONITOR_WW4C1_6", + "MONITOR_WL1END2_4", + "MONITOR_SW2A0_1", + "MONITOR_CTRL1_9", + "MONITOR_SE2A3_6", + "MONITOR_WW4B2_2", + "MONITOR_NW2A0_5", + "MONITOR_LOGIC_OUTS_B16_8", + "MONITOR_BLOCK_OUTS_B1_3", + "MONITOR_WR1END2_0", + "MONITOR_DI5", + "MONITOR_WL1END0_9", + "MONITOR_LH9_4", + "MONITOR_IMUX7_0", + "MONITOR_IMUX27_8", + "MONITOR_WR1END3_7", + "MONITOR_IMUX15_3", + "MONITOR_NW4END1_9", + "MONITOR_EE4A3_0", + "MONITOR_IMUX35_9", + "MONITOR_IMUX25_3", + "MONITOR_BYP1_4", + "MONITOR_WW2A3_5", + "MONITOR_EL1BEG0_6", + "MONITOR_LH3_4", + "MONITOR_FAN0_0", + "MONITOR_EE2BEG0_4", + "MONITOR_LH10_2", + "MONITOR_SE2A2_8", + "MONITOR_EE4A1_6", + "MONITOR_LOGIC_OUTS_B2_5", + "MONITOR_LH10_0", + "MONITOR_IMUX7_4", + "MONITOR_SW4END2_2", + "MONITOR_WW4A0_5", + "MONITOR_WL1END0_6", + "MONITOR_SE4C1_4", + "MONITOR_SE2A3_9", + "MONITOR_EE4B2_5", + "MONITOR_BLOCK_OUTS_B2_6", + "MONITOR_WR1END3_4", + "MONITOR_WR1END1_5", + "MONITOR_SE2A1_9", + "MONITOR_SW2A3_9", + "MONITOR_WL1END3_7", + "MONITOR_LOGIC_OUTS_B12_5", + "MONITOR_WW4END1_3", + "MONITOR_IMUX7_3", + "MONITOR_IMUX28_6", + "MONITOR_LOGIC_OUTS_B13_5", + "MONITOR_NW4A2_7", + "MONITOR_TESTDB0", + "MONITOR_IMUX11_3", + "MONITOR_EL1BEG3_1", + "MONITOR_SW4A1_0", + "MONITOR_IMUX3_6", + "MONITOR_IMUX2_1", + "MONITOR_SW4END0_9", + "MONITOR_IMUX22_4", + "MONITOR_IMUX0_6", + "MONITOR_EE4A3_2", + "MONITOR_TESTSHIFT", + "MONITOR_EE4A3_5", + "MONITOR_IMUX16_6", + "MONITOR_NE2A2_5", + "MONITOR_SW4A0_7", + "MONITOR_LOGIC_OUTS_B18_9", + "MONITOR_WW4C2_3", + "MONITOR_WW2A3_7", + "MONITOR_IMUX33_5", + "MONITOR_SE2A2_5", + "MONITOR_EE4BEG2_3", + "MONITOR_SE2A0_5", + "MONITOR_DO1", + "MONITOR_NE4C1_8", + "MONITOR_TESTSE4", + "MONITOR_LOGIC_OUTS_B13_8", + "MONITOR_NW4END1_8", + "MONITOR_EL1BEG3_7", + "MONITOR_LOGIC_OUTS_B8_7", + "MONITOR_SW2A1_4", + "MONITOR_LOGIC_OUTS_B10_1", + "MONITOR_FAN3_7", + "MONITOR_EE4B1_8", + "MONITOR_SW4A2_5", + "MONITOR_IMUX18_6", + "MONITOR_VAUXN7", + "MONITOR_NE2A3_4", + "MONITOR_NE4BEG1_9", + "MONITOR_WW4A0_1", + "MONITOR_WR1END0_2", + "MONITOR_IMUX20_1", + "MONITOR_LOGIC_OUTS_B14_9", + "MONITOR_EE4A0_2", + "MONITOR_CTRL0_2", + "MONITOR_EE4C2_1", + "MONITOR_IMUX6_8", + "MONITOR_IMUX35_6", + "MONITOR_IMUX10_9", + "MONITOR_HORIZ_VAUXN3", + "MONITOR_EE4BEG0_9", + "MONITOR_TESTADCIN12", + "MONITOR_IMUX6_7", + "MONITOR_VERT_VAUXN1", + "MONITOR_IMUX43_3", + "MONITOR_LOGIC_OUTS_B6_1", + "MONITOR_WW4C2_4", + "MONITOR_NE4C3_8", + "MONITOR_NE2A3_5", + "MONITOR_WW4B3_2", + "MONITOR_SW4A2_0", + "MONITOR_NW4A2_4", + "MONITOR_WW4B2_4", + "MONITOR_SE4BEG1_1", + "MONITOR_DADDR1", + "MONITOR_IMUX19_2", + "MONITOR_VERT_VAUXP14", + "MONITOR_IMUX8_3", + "MONITOR_LH1_5", + "MONITOR_TESTUPDATE", + "MONITOR_LOGIC_OUTS_B9_7", + "MONITOR_SW4A2_3", + "MONITOR_BLOCK_OUTS_B0_5", + "MONITOR_IMUX44_8", + "MONITOR_IMUX22_5", + "MONITOR_LH9_7", + "MONITOR_SW2A0_9", + "MONITOR_LOGIC_OUTS_B12_8", + "MONITOR_LOGIC_OUTS_B18_4", + "MONITOR_LOGIC_OUTS_B13_0", + "MONITOR_IMUX40_5", + "MONITOR_WW4A1_3", + "MONITOR_IMUX35_8", + "MONITOR_IMUX19_6", + "MONITOR_CTRL0_6", + "MONITOR_FAN0_6", + "MONITOR_IMUX37_6", + "MONITOR_IMUX23_5", + "MONITOR_EE4BEG2_4", + "MONITOR_IMUX20_0", + "MONITOR_WL1END0_8", + "MONITOR_LOGIC_OUTS_B4_6", + "MONITOR_WW2END3_6", + "MONITOR_IMUX21_0", + "MONITOR_WW4B3_0", + "MONITOR_IMUX19_4", + "MONITOR_IMUX15_4", + "MONITOR_FAN7_2", + "MONITOR_EE2BEG3_5", + "MONITOR_SE2A0_0", + "MONITOR_WR1END3_3", + "MONITOR_WL1END3_2", + "MONITOR_WL1END2_7", + "MONITOR_IMUX44_1", + "MONITOR_IMUX21_9", + "MONITOR_DCLK", + "MONITOR_BYP0_3", + "MONITOR_WW4B2_3", + "MONITOR_SEG_VP", + "MONITOR_LH4_8", + "MONITOR_EE4BEG2_7", + "MONITOR_DI4", + "MONITOR_IMUX8_5", + "MONITOR_EE4BEG1_6", + "MONITOR_EE4BEG2_9", + "MONITOR_LOGIC_OUTS_B17_6", + "MONITOR_IMUX38_0", + "MONITOR_NW4A1_5", + "MONITOR_EE2A2_1", + "MONITOR_FAN5_4", + "MONITOR_LOGIC_OUTS_B20_4", + "MONITOR_EL1BEG3_9", + "MONITOR_LOGIC_OUTS_B16_7", + "MONITOR_BYP4_1", + "MONITOR_WR1END3_6", + "MONITOR_TESTSE2", + "MONITOR_TESTADCIN24", + "MONITOR_TESTDB2", + "MONITOR_NW4END0_8", + "MONITOR_WW4END3_6", + "MONITOR_LOGIC_OUTS_B7_6", + "MONITOR_LOGIC_OUTS_B19_4", + "MONITOR_EE2BEG0_3", + "MONITOR_BLOCK_OUTS_B0_3", + "MONITOR_EE2A1_5", + "MONITOR_IMUX14_5", + "MONITOR_LOGIC_OUTS_B2_1", + "MONITOR_WW4A2_9", + "MONITOR_BYP4_2", + "MONITOR_EE4A0_7", + "MONITOR_WW4C1_9", + "MONITOR_WR1END1_8", + "MONITOR_LH5_6", + "MONITOR_EE4B0_2", + "MONITOR_EE4BEG0_2", + "MONITOR_EE4A0_3", + "MONITOR_CTRL0_0", + "MONITOR_CLK1_0", + "MONITOR_IMUX17_4", + "MONITOR_EE4BEG3_2", + "MONITOR_IMUX44_9", + "MONITOR_EE4B1_3", + "MONITOR_EE4BEG2_5", + "MONITOR_SW2A2_4", + "MONITOR_WW2A3_3", + "MONITOR_FAN6_0", + "MONITOR_NW4END3_3", + "MONITOR_IMUX40_3", + "MONITOR_FAN2_0", + "MONITOR_LOGIC_OUTS_B22_9", + "MONITOR_WW4C3_3", + "MONITOR_WW2A0_6", + "MONITOR_WR1END0_8", + "MONITOR_NW4A2_6", + "MONITOR_IMUX38_1", + "MONITOR_WR1END0_1", + "MONITOR_LOGIC_OUTS_B16_3", + "MONITOR_NE4C1_5", + "MONITOR_NW2A1_0", + "MONITOR_IMUX47_7", + "MONITOR_EE4B0_7", + "MONITOR_LOGIC_OUTS_B11_7", + "MONITOR_WW2A1_3", + "MONITOR_WW2END2_5", + "MONITOR_IMUX11_5", + "MONITOR_EE4BEG1_4", + "MONITOR_SW4END0_5", + "MONITOR_IMUX30_1", + "MONITOR_IMUX17_7", + "MONITOR_SE4C0_9", + "MONITOR_EE4C2_8", + "MONITOR_IMUX46_5", + "MONITOR_WW4END2_4", + "MONITOR_EE2BEG0_0", + "MONITOR_LH9_5", + "MONITOR_WW2END3_5", + "MONITOR_WR1END0_3", + "MONITOR_BLOCK_OUTS_B1_1", + "MONITOR_IMUX19_7", + "MONITOR_FAN1_7", + "MONITOR_IMUX5_8", + "MONITOR_EE4C1_3", + "MONITOR_BLOCK_OUTS_B3_4", + "MONITOR_FAN4_5", + "MONITOR_WR1END2_1", + "MONITOR_LOGIC_OUTS_B22_2", + "MONITOR_IMUX28_7", + "MONITOR_NW4A3_0", + "MONITOR_ER1BEG1_6", + "MONITOR_WR1END3_9", + "MONITOR_WW4C0_4", + "MONITOR_ER1BEG0_9", + "MONITOR_FAN3_3", + "MONITOR_WW2A1_1", + "MONITOR_LOGIC_OUTS_B19_0", + "MONITOR_EE4C2_3", + "MONITOR_WW4B0_3", + "MONITOR_SE4BEG3_1", + "MONITOR_WR1END2_4", + "MONITOR_NE2A2_9", + "MONITOR_WL1END1_4", + "MONITOR_TESTADCIN9", + "MONITOR_FAN3_6", + "MONITOR_WW4END0_9", + "MONITOR_FAN2_5", + "MONITOR_IMUX46_4", + "MONITOR_IMUX41_5", + "MONITOR_NW4A2_1", + "MONITOR_BYP5_2", + "MONITOR_NW4END3_4", + "MONITOR_IMUX26_8", + "MONITOR_LOGIC_OUTS_B6_8", + "MONITOR_SW2A3_0", + "MONITOR_LOGIC_OUTS_B17_5", + "MONITOR_SE4BEG2_0", + "MONITOR_WW4A3_1", + "MONITOR_BLOCK_OUTS_B1_4", + "MONITOR_EE2BEG3_6", + "MONITOR_CHANNEL2", + "MONITOR_WR1END1_1", + "MONITOR_IMUX42_1", + "MONITOR_IMUX26_2", + "MONITOR_NW4END1_0", + "MONITOR_SW2A0_8", + "MONITOR_BYP6_6", + "MONITOR_NE4BEG2_5", + "MONITOR_LOGIC_OUTS_B4_7", + "MONITOR_RESET", + "MONITOR_VERT_VAUXN3", + "MONITOR_NW2A3_0", + "MONITOR_LOGIC_OUTS_B5_3", + "MONITOR_BYP3_8", + "MONITOR_NE4BEG0_2", + "MONITOR_NE4C0_5", + "MONITOR_LOGIC_OUTS_B3_8", + "MONITOR_TESTDB14", + "MONITOR_WW4END0_7", + "MONITOR_SE2A0_3", + "MONITOR_SW4END2_0", + "MONITOR_FAN7_9", + "MONITOR_WW4END2_8", + "MONITOR_SE2A2_7", + "MONITOR_NE2A3_3", + "MONITOR_WW2END0_3", + "MONITOR_EE4B3_3", + "MONITOR_LOGIC_OUTS_B23_6", + "MONITOR_SE2A2_4", + "MONITOR_IMUX29_4", + "MONITOR_VERT_VAUXP4", + "MONITOR_WW2A3_2", + "MONITOR_IMUX7_7", + "MONITOR_CLK0_5", + "MONITOR_LH9_6", + "MONITOR_WW2END1_8", + "MONITOR_NE2A0_4", + "MONITOR_WW2A1_5", + "MONITOR_NW4END0_2", + "MONITOR_LOGIC_OUTS_B4_9", + "MONITOR_LOGIC_OUTS_B14_0", + "MONITOR_LH6_0", + "MONITOR_WW4END2_5", + "MONITOR_CLK1_3", + "MONITOR_FAN3_8", + "MONITOR_IMUX19_3", + "MONITOR_LOGIC_OUTS_B15_4", + "MONITOR_EE4B1_1", + "MONITOR_IMUX30_6", + "MONITOR_LH2_1", + "MONITOR_IMUX7_6", + "MONITOR_EE2A2_4", + "MONITOR_EL1BEG2_0", + "MONITOR_EE4A1_8", + "MONITOR_IMUX14_9", + "MONITOR_SW4END2_8", + "MONITOR_WW2A3_0", + "MONITOR_EE2A3_3", + "MONITOR_ER1BEG3_6", + "MONITOR_EE4BEG0_4", + "MONITOR_WW2END1_4", + "MONITOR_IMUX0_9", + "MONITOR_EE4A0_0", + "MONITOR_LH1_8", + "MONITOR_WL1END3_0", + "MONITOR_SW4A3_4", + "MONITOR_SW2A3_6", + "MONITOR_IMUX25_4", + "MONITOR_LH11_7", + "MONITOR_WW4END2_9", + "MONITOR_NE2A0_6", + "MONITOR_LOGIC_OUTS_B22_4", + "MONITOR_EE4A1_9", + "MONITOR_LOGIC_OUTS_B0_9", + "MONITOR_EE4BEG1_7", + "MONITOR_LOGIC_OUTS_B17_8", + "MONITOR_DO5", + "MONITOR_SE4C1_2", + "MONITOR_NE4BEG2_6", + "MONITOR_IMUX8_2", + "MONITOR_SE4BEG3_6", + "MONITOR_IMUX15_7", + "MONITOR_EL1BEG2_9", + "MONITOR_EE4C1_9", + "MONITOR_BYP2_1", + "MONITOR_LOGIC_OUTS_B6_0", + "MONITOR_IMUX12_2", + "MONITOR_ALM3", + "MONITOR_TESTADCOUT16", + "MONITOR_EE2BEG3_0", + "MONITOR_WW4END3_0", + "MONITOR_DI3", + "MONITOR_SE4C3_0", + "MONITOR_LOGIC_OUTS_B21_9", + "MONITOR_IMUX9_4", + "MONITOR_FAN1_0", + "MONITOR_WW2A2_0", + "MONITOR_LOGIC_OUTS_B10_0", + "MONITOR_IMUX36_1", + "MONITOR_CLK1_7", + "MONITOR_WW2END3_3", + "MONITOR_EL1BEG3_4", + "MONITOR_EE2A1_4", + "MONITOR_IMUX15_5", + "MONITOR_IMUX14_7", + "MONITOR_SE2A3_0", + "MONITOR_IMUX20_9", + "MONITOR_EE4A2_4", + "MONITOR_SE4C0_2", + "MONITOR_IMUX9_2", + "MONITOR_NW4A1_3", + "MONITOR_NW4END3_5", + "MONITOR_WW4A3_7", + "MONITOR_SW2A1_2", + "MONITOR_LH2_8", + "MONITOR_WW4A2_3", + "MONITOR_IMUX2_0", + "MONITOR_WW2END1_3", + "MONITOR_EE4C3_5", + "MONITOR_SW4END0_7", + "MONITOR_TESTSI3", + "MONITOR_WW2A0_9", + "MONITOR_WW4C1_5", + "MONITOR_TESTDB12", + "MONITOR_WW4A3_3", + "MONITOR_WW4B3_9", + "MONITOR_SE2A3_5", + "MONITOR_FAN5_3", + "MONITOR_WW4END3_8", + "MONITOR_LOGIC_OUTS_B4_8", + "MONITOR_WW2END3_4", + "MONITOR_BYP3_9", + "MONITOR_SE4C3_3", + "MONITOR_WW4B2_5", + "MONITOR_SE4BEG1_7", + "MONITOR_ALM4", + "MONITOR_NE4C3_4", + "MONITOR_ER1BEG2_1", + "MONITOR_NW2A1_9", + "MONITOR_BYP3_1", + "MONITOR_IMUX20_8", + "MONITOR_IMUX27_6", + "MONITOR_LOGIC_OUTS_B20_7", + "MONITOR_ER1BEG0_0", + "MONITOR_IMUX15_9", + "MONITOR_WW2END3_8", + "MONITOR_LOGIC_OUTS_B11_2", + "MONITOR_SW2A1_5", + "MONITOR_EL1BEG0_1", + "MONITOR_LOGIC_OUTS_B12_4", + "MONITOR_WW4A0_2", + "MONITOR_SW4END3_2", + "MONITOR_FAN2_6", + "MONITOR_TESTADCIN28", + "MONITOR_BLOCK_OUTS_B0_4", + "MONITOR_LOGIC_OUTS_B23_3", + "MONITOR_VAUXP2", + "MONITOR_NW2A2_4", + "MONITOR_LOGIC_OUTS_B3_0", + "MONITOR_FAN6_7", + "MONITOR_EE2BEG3_9", + "MONITOR_LOGIC_OUTS_B11_0", + "MONITOR_WW4END1_1", + "MONITOR_NE2A0_9", + "MONITOR_VERT_VAUXP7", + "MONITOR_IMUX24_7", + "MONITOR_IMUX39_7", + "MONITOR_NW4A0_9", + "MONITOR_LOGIC_OUTS_B5_4", + "MONITOR_BYP6_3", + "MONITOR_LH11_6", + "MONITOR_NW2A3_8", + "MONITOR_NE4C1_0", + "MONITOR_WW4C0_8", + "MONITOR_SW4A1_4", + "MONITOR_EL1BEG1_9", + "MONITOR_SW4A3_1", + "MONITOR_EE2BEG3_7", + "MONITOR_DI12", + "MONITOR_TESTADCIN0", + "MONITOR_ER1BEG3_3", + "MONITOR_WW4C1_0", + "MONITOR_LH12_6", + "MONITOR_IMUX8_8", + "MONITOR_IMUX34_1", + "MONITOR_IMUX43_1", + "MONITOR_NW2A2_3", + "MONITOR_IMUX2_4", + "MONITOR_NW2A1_6", + "MONITOR_EE4C3_9", + "MONITOR_LOGIC_OUTS_B1_3", + "MONITOR_EE4A0_9", + "MONITOR_FAN2_8", + "MONITOR_IMUX12_5", + "MONITOR_BLOCK_OUTS_B3_9", + "MONITOR_LH4_3", + "MONITOR_SE4BEG2_5", + "MONITOR_LH8_9", + "MONITOR_WW2END2_8", + "MONITOR_LH3_8", + "MONITOR_LH8_8", + "MONITOR_LOGIC_OUTS_B19_3", + "MONITOR_LOGIC_OUTS_B15_5", + "MONITOR_LOGIC_OUTS_B7_5", + "MONITOR_FAN2_4", + "MONITOR_IMUX26_5", + "MONITOR_FAN0_1", + "MONITOR_WL1END1_9", + "MONITOR_DADDR5", + "MONITOR_IMUX32_8", + "MONITOR_WW2END2_0", + "MONITOR_LH3_6", + "MONITOR_LOGIC_OUTS_B0_8", + "MONITOR_IMUX3_5", + "MONITOR_VAUXN9", + "MONITOR_WW4END3_1", + "MONITOR_EE2BEG1_8", + "MONITOR_NW4A0_2", + "MONITOR_IMUX17_1", + "MONITOR_LH2_3", + "MONITOR_TESTADCIN213", + "MONITOR_SW2A2_6", + "MONITOR_IMUX30_4", + "MONITOR_WW4END2_7", + "MONITOR_EE4A2_5", + "MONITOR_NW4END1_3", + "MONITOR_LOGIC_OUTS_B11_6", + "MONITOR_WW2A2_5", + "MONITOR_IMUX47_9", + "MONITOR_WW4C0_0", + "MONITOR_TESTADCIN11", + "MONITOR_VN", + "MONITOR_TESTDB3", + "MONITOR_TESTADCCLK2", + "MONITOR_TESTDB8", + "MONITOR_WW2END2_6", + "MONITOR_LOGIC_OUTS_B12_0", + "MONITOR_NE4BEG3_1", + "MONITOR_NW2A0_2", + "MONITOR_IMUX6_6", + "MONITOR_EE2BEG1_9", + "MONITOR_FAN5_2", + "MONITOR_BLOCK_OUTS_B0_0", + "MONITOR_WW4END3_4", + "MONITOR_LOGIC_OUTS_B22_6", + "MONITOR_WW4A2_8", + "MONITOR_EL1BEG1_1", + "MONITOR_MUXADDR1", + "MONITOR_TESTADCOUT10", + "MONITOR_LH10_8", + "MONITOR_IMUX5_3", + "MONITOR_IMUX25_1", + "MONITOR_FAN4_4", + "MONITOR_EE4A1_2", + "MONITOR_SW4END2_7", + "MONITOR_BLOCK_OUTS_B1_5", + "MONITOR_SW2A0_2", + "MONITOR_NW4A3_7", + "MONITOR_IMUX16_5", + "MONITOR_FAN6_8", + "MONITOR_IMUX2_8", + "MONITOR_WW4END1_8", + "MONITOR_NE4BEG0_9", + "MONITOR_IMUX0_7", + "MONITOR_IMUX22_6", + "MONITOR_EE4BEG0_5", + "MONITOR_NE4BEG3_7", + "MONITOR_IMUX6_1", + "MONITOR_LOGIC_OUTS_B0_6", + "MONITOR_IMUX37_8", + "MONITOR_NW4A1_9", + "MONITOR_LOGIC_OUTS_B17_0", + "MONITOR_WW2END2_9", + "MONITOR_WW4END1_0", + "MONITOR_TESTADCOUT1", + "MONITOR_NW2A2_6", + "MONITOR_SW2A1_9", + "MONITOR_IMUX31_3", + "MONITOR_IMUX30_8", + "MONITOR_LH10_6", + "MONITOR_BLOCK_OUTS_B0_8", + "MONITOR_IMUX9_7", + "MONITOR_IMUX28_5", + "MONITOR_NE2A3_7", + "MONITOR_LOGIC_OUTS_B23_9", + "MONITOR_BLOCK_OUTS_B3_0", + "MONITOR_BYP6_5", + "MONITOR_VERT_VAUXN13", + "MONITOR_LOGIC_OUTS_B0_4", + "MONITOR_BLOCK_OUTS_B1_6", + "MONITOR_SE4C1_1", + "MONITOR_FAN2_7", + "MONITOR_FAN3_2", + "MONITOR_IMUX36_6", + "MONITOR_VERT_VAUXN14", + "MONITOR_WW4END1_6", + "MONITOR_NW4A3_6", + "MONITOR_WW4END0_3", + "MONITOR_IMUX7_8", + "MONITOR_EL1BEG2_3", + "MONITOR_BYP6_4", + "MONITOR_LOGIC_OUTS_B9_3", + "MONITOR_IMUX42_6", + "MONITOR_WR1END0_7", + "MONITOR_SW2A2_7", + "MONITOR_LH5_9", + "MONITOR_LOGIC_OUTS_B11_5", + "MONITOR_BLOCK_OUTS_B0_2", + "MONITOR_LOGIC_OUTS_B9_5", + "MONITOR_FAN4_7", + "MONITOR_TESTADCIN20", + "MONITOR_CLK0_1", + "MONITOR_IMUX31_6", + "MONITOR_TESTSCANMODE0", + "MONITOR_NE4BEG1_4", + "MONITOR_IMUX44_7", + "MONITOR_WL1END2_1", + "MONITOR_IMUX21_4", + "MONITOR_WR1END2_6", + "MONITOR_IMUX23_3", + "MONITOR_EE4C1_4", + "MONITOR_EE4C0_0", + "MONITOR_LH2_0", + "MONITOR_NE4C3_9", + "MONITOR_SW2A3_2", + "MONITOR_LH4_6", + "MONITOR_NW4A3_3", + "MONITOR_IMUX27_4", + "MONITOR_TESTDB6", + "MONITOR_IMUX37_4", + "MONITOR_LOGIC_OUTS_B13_9", + "MONITOR_IMUX44_3", + "MONITOR_TESTADCOUT19", + "MONITOR_EE2A0_6", + "MONITOR_IMUX33_7", + "MONITOR_SW4A1_2", + "MONITOR_NW4END2_4", + "MONITOR_WW2A2_1", + "MONITOR_IMUX47_5", + "MONITOR_CTRL1_4", + "MONITOR_SW4END3_3", + "MONITOR_LOGIC_OUTS_B5_8", + "MONITOR_LH6_8", + "MONITOR_SW2A3_3", + "MONITOR_BLOCK_OUTS_B2_4", + "MONITOR_LOGIC_OUTS_B17_2", + "MONITOR_NW4A2_2", + "MONITOR_WW4A0_8", + "MONITOR_WW2A2_3", + "MONITOR_MUXADDR0", + "MONITOR_SE2A2_0", + "MONITOR_IMUX16_1", + "MONITOR_MUXADDR4", + "MONITOR_WL1END2_0", + "MONITOR_SW4A3_6", + "MONITOR_IMUX3_0", + "MONITOR_WR1END0_4", + "MONITOR_NE4BEG0_4", + "MONITOR_BYP0_4", + "MONITOR_NE2A2_2", + "MONITOR_LH1_0", + "MONITOR_IMUX27_0", + "MONITOR_WW4C1_4", + "MONITOR_TESTADCIN13", + "MONITOR_TESTADCIN219", + "MONITOR_LOGIC_OUTS_B13_2", + "MONITOR_SE2A0_7", + "MONITOR_IMUX39_6", + "MONITOR_BYP2_7", + "MONITOR_IMUX18_1", + "MONITOR_IMUX28_2", + "MONITOR_IMUX9_3", + "MONITOR_SE2A3_8", + "MONITOR_SE4BEG3_3", + "MONITOR_LOGIC_OUTS_B5_0", + "MONITOR_IMUX23_0", + "MONITOR_NE4C1_2", + "MONITOR_LOGIC_OUTS_B22_0", + "MONITOR_WW4C2_0", + "MONITOR_NE2A1_2", + "MONITOR_MUXADDR3", + "MONITOR_WW4B0_2", + "MONITOR_SE4BEG0_8", + "MONITOR_IMUX28_0", + "MONITOR_IMUX21_6", + "MONITOR_EE4BEG1_3", + "MONITOR_TESTADCIN218", + "MONITOR_TESTADCIN215", + "MONITOR_EE2A0_9", + "MONITOR_TESTADCOUT8", + "MONITOR_LOGIC_OUTS_B16_0", + "MONITOR_EE2BEG3_2", + "MONITOR_FAN3_9", + "MONITOR_LOGIC_OUTS_B6_6", + "MONITOR_LH4_7", + "MONITOR_WW2A1_6", + "MONITOR_TESTADCOUT3", + "MONITOR_DI15", + "MONITOR_NE4BEG0_0", + "MONITOR_LOGIC_OUTS_B1_6", + "MONITOR_SE2A1_7", + "MONITOR_IMUX2_5", + "MONITOR_LOGIC_OUTS_B2_2", + "MONITOR_LOGIC_OUTS_B2_3", + "MONITOR_NE2A3_0", + "MONITOR_EE4A2_9", + "MONITOR_VERT_VAUXP3", + "MONITOR_SE4C1_5", + "MONITOR_VAUXN2", + "MONITOR_SW4A3_7", + "MONITOR_WW2A0_0", + "MONITOR_NW2A3_9", + "MONITOR_DO0", + "MONITOR_FAN4_9", + "MONITOR_WW4C0_6", + "MONITOR_EE2A0_0", + "MONITOR_IMUX40_6", + "MONITOR_BYP4_5", + "MONITOR_WW4END3_7", + "MONITOR_IMUX0_5", + "MONITOR_IMUX31_4", + "MONITOR_WW2END0_6", + "MONITOR_ER1BEG0_5", + "MONITOR_NW2A1_7", + "MONITOR_SW4END2_6", + "MONITOR_WW4B2_8", + "MONITOR_SW4END2_3", + "MONITOR_CLK1_1", + "MONITOR_LH9_2", + "MONITOR_NE4C0_7", + "MONITOR_VERT_VAUXP1", + "MONITOR_TESTADCCLK3", + "MONITOR_LOGIC_OUTS_B10_7", + "MONITOR_IMUX33_4", + "MONITOR_WW2A3_9", + "MONITOR_BYP3_7", + "MONITOR_IMUX6_9", + "MONITOR_BYP3_2", + "MONITOR_IMUX2_3", + "MONITOR_WW4C3_8", + "MONITOR_IMUX18_2", + "MONITOR_NE4BEG3_8", + "MONITOR_TESTADCIN27", + "MONITOR_IMUX35_2", + "MONITOR_SE4C3_4", + "MONITOR_SW2A3_5", + "MONITOR_LOGIC_OUTS_B22_3", + "MONITOR_EE4BEG1_1", + "MONITOR_WW4B1_4", + "MONITOR_LOGIC_OUTS_B3_5", + "MONITOR_LOGIC_OUTS_B13_6", + "MONITOR_EE4C0_8", + "MONITOR_LOGIC_OUTS_B14_2", + "MONITOR_NE2A1_0", + "MONITOR_LOGIC_OUTS_B15_2", + "MONITOR_LOGIC_OUTS_B6_4", + "MONITOR_LH2_7", + "MONITOR_EE4C0_7", + "MONITOR_NE2A1_1", + "MONITOR_LOGIC_OUTS_B19_1", + "MONITOR_SW4A2_2", + "MONITOR_IMUX1_3", + "MONITOR_DO6", + "MONITOR_WW4C1_7", + "MONITOR_SW2A1_0", + "MONITOR_BYP5_6", + "MONITOR_EE2A1_3", + "MONITOR_SE4BEG1_4", + "MONITOR_IMUX26_9", + "MONITOR_ER1BEG1_9", + "MONITOR_BYP6_1", + "MONITOR_EL1BEG0_5", + "MONITOR_IMUX10_3", + "MONITOR_LOGIC_OUTS_B18_5", + "MONITOR_SE4BEG2_7", + "MONITOR_ER1BEG3_7", + "MONITOR_EE2A0_5", + "MONITOR_WW4C3_1", + "MONITOR_LOGIC_OUTS_B9_1", + "MONITOR_EE4B2_7", + "MONITOR_EE4A2_1", + "MONITOR_IMUX5_1", + "MONITOR_DO12", + "MONITOR_LOGIC_OUTS_B8_6", + "MONITOR_WW4END3_2", + "MONITOR_BYP0_0", + "MONITOR_NE4BEG2_7", + "MONITOR_EE4A1_5", + "MONITOR_WL1END2_3", + "MONITOR_IMUX27_7", + "MONITOR_SW2A2_2", + "MONITOR_NW4END0_6", + "MONITOR_LOGIC_OUTS_B5_1", + "MONITOR_NW4A1_1", + "MONITOR_SE4C1_0", + "MONITOR_IMUX23_6", + "MONITOR_IMUX43_6", + "MONITOR_IMUX45_1", + "MONITOR_EE2BEG2_1", + "MONITOR_NE2A3_8", + "MONITOR_LOGIC_OUTS_B8_9", + "MONITOR_WL1END3_1", + "MONITOR_EE2BEG1_3", + "MONITOR_EE2BEG3_8", + "MONITOR_TESTADCOUT5", + "MONITOR_LH10_9", + "MONITOR_LOGIC_OUTS_B12_9", + "MONITOR_EE4B1_0", + "MONITOR_IMUX24_8", + "MONITOR_IMUX24_4", + "MONITOR_HORIZ_VAUXN4_LEFT", + "MONITOR_NW4END3_8", + "MONITOR_LH11_3", + "MONITOR_LOGIC_OUTS_B21_6", + "MONITOR_LOGIC_OUTS_B21_5", + "MONITOR_IMUX35_7", + "MONITOR_WW2A2_4", + "MONITOR_IMUX19_5", + "MONITOR_SE4BEG3_7", + "MONITOR_IMUX42_7", + "MONITOR_WR1END2_3", + "MONITOR_WR1END0_9", + "MONITOR_FAN1_1", + "MONITOR_LOGIC_OUTS_B1_7", + "MONITOR_EE4A0_5", + "MONITOR_CLK1_6", + "MONITOR_NE4BEG1_0", + "MONITOR_IMUX6_2", + "MONITOR_IMUX41_1", + "MONITOR_IMUX13_5", + "MONITOR_EE2A0_8", + "MONITOR_EE2A3_2", + "MONITOR_NW4END1_7", + "MONITOR_IMUX10_8", + "MONITOR_SE2A3_1", + "MONITOR_EE2A0_2", + "MONITOR_SE4C0_6", + "MONITOR_TESTADCIN18", + "MONITOR_NW2A2_5", + "MONITOR_WW2A3_8", + "MONITOR_IMUX6_5", + "MONITOR_IMUX31_1", + "MONITOR_SE2A2_1", + "MONITOR_IMUX19_8", + "MONITOR_LH12_3", + "MONITOR_VAUXP9", + "MONITOR_SE4BEG0_2", + "MONITOR_VAUXP1", + "MONITOR_VAUXN13", + "MONITOR_WR1END1_7", + "MONITOR_WW2A2_7", + "MONITOR_TESTADCOUT9", + "MONITOR_WW2END2_1", + "MONITOR_FAN0_7", + "MONITOR_TESTADCOUT7", + "MONITOR_SW2A1_6", + "MONITOR_TESTSCANMODE4", + "MONITOR_NE2A0_8", + "MONITOR_BLOCK_OUTS_B2_1", + "MONITOR_IMUX32_1", + "MONITOR_NE4BEG2_4", + "MONITOR_BLOCK_OUTS_B3_1", + "MONITOR_NW4A1_7", + "MONITOR_LOGIC_OUTS_B3_7", + "MONITOR_LOGIC_OUTS_B4_4", + "MONITOR_BYP0_6", + "MONITOR_VAUXP12", + "MONITOR_SE4BEG0_3", + "MONITOR_WL1END3_3", + "MONITOR_NW4END0_1", + "MONITOR_EE4BEG2_0", + "MONITOR_IMUX9_0", + "MONITOR_IMUX1_7", + "MONITOR_NW2A3_3", + "MONITOR_EE4B2_0", + "MONITOR_SE2A1_3", + "MONITOR_SE4BEG2_2", + "MONITOR_LH9_1", + "MONITOR_NE2A1_3", + "MONITOR_ER1BEG3_0", + "MONITOR_ER1BEG1_0", + "MONITOR_IMUX1_6", + "MONITOR_TESTADCIN22", + "MONITOR_IMUX39_0", + "MONITOR_SE2A0_1", + "MONITOR_IMUX0_2", + "MONITOR_BLOCK_OUTS_B3_2", + "MONITOR_FAN2_9", + "MONITOR_EE4B1_7", + "MONITOR_WW4A1_7", + "MONITOR_IMUX22_0", + "MONITOR_TESTADCOUT13", + "MONITOR_LOGIC_OUTS_B20_5", + "MONITOR_VERT_VAUXP2", + "MONITOR_NW4END2_2", + "MONITOR_SW2A1_3", + "MONITOR_IMUX1_8", + "MONITOR_BYP3_6", + "MONITOR_WW4END1_5", + "MONITOR_EE4B3_2", + "MONITOR_IMUX20_2", + "MONITOR_NW4END2_5", + "MONITOR_LOGIC_OUTS_B0_3", + "MONITOR_IMUX29_1", + "MONITOR_WR1END3_1", + "MONITOR_TESTDB10", + "MONITOR_IMUX13_0", + "MONITOR_LOGIC_OUTS_B7_1", + "MONITOR_TESTSCANMODE3", + "MONITOR_IMUX12_1", + "MONITOR_IMUX23_1", + "MONITOR_IMUX32_0", + "MONITOR_SE2A0_2", + "MONITOR_NE2A1_6", + "MONITOR_IMUX43_2", + "MONITOR_NW2A0_1", + "MONITOR_WW2END1_1", + "MONITOR_JTAGLOCKED", + "MONITOR_SE4BEG2_8", + "MONITOR_EE2BEG1_7", + "MONITOR_LOGIC_OUTS_B12_7", + "MONITOR_ER1BEG3_2", + "MONITOR_WW2END3_2", + "MONITOR_LH1_6", + "MONITOR_LOGIC_OUTS_B18_3", + "MONITOR_DRDY", + "MONITOR_IMUX39_3", + "MONITOR_EE2A2_0", + "MONITOR_IMUX1_4", + "MONITOR_LOGIC_OUTS_B17_9", + "MONITOR_LOGIC_OUTS_B23_1", + "MONITOR_IMUX27_9", + "MONITOR_EE4B2_3", + "MONITOR_NE4BEG0_1", + "MONITOR_IMUX15_1", + "MONITOR_NW4END2_6", + "MONITOR_IMUX32_7", + "MONITOR_BYP5_8", + "MONITOR_FAN5_5", + "MONITOR_EE2BEG3_1", + "MONITOR_VAUXN10", + "MONITOR_LOGIC_OUTS_B15_1", + "MONITOR_HORIZ_VAUXP12_LEFT", + "MONITOR_LOGIC_OUTS_B1_8", + "MONITOR_SE4C3_7", + "MONITOR_BYP6_8", + "MONITOR_CLK0_7", + "MONITOR_EE4BEG0_8", + "MONITOR_WW4A3_8", + "MONITOR_BYP1_5", + "MONITOR_LOGIC_OUTS_B19_7", + "MONITOR_TESTADCIN2", + "MONITOR_NE4BEG0_7", + "MONITOR_WW4END0_6", + "MONITOR_EE4C3_7", + "MONITOR_EE2A2_3", + "MONITOR_NE2A3_6", + "MONITOR_TESTSO3", + "MONITOR_IMUX15_8", + "MONITOR_WW2A3_1", + "MONITOR_SW4END3_7", + "MONITOR_DO13", + "MONITOR_BYP3_3", + "MONITOR_NW2A0_9", + "MONITOR_LOGIC_OUTS_B14_6", + "MONITOR_TESTSO1", + "MONITOR_LOGIC_OUTS_B18_7", + "MONITOR_NE4C3_7", + "MONITOR_WW4C0_5", + "MONITOR_IMUX16_4", + "MONITOR_NW4A3_1", + "MONITOR_EE4BEG3_1", + "MONITOR_TESTADCOUT4", + "MONITOR_EE4BEG1_2", + "MONITOR_EE4A2_7", + "MONITOR_ALM2", + "MONITOR_BYP3_5", + "MONITOR_FAN6_5", + "MONITOR_LOGIC_OUTS_B10_5", + "MONITOR_IMUX45_3", + "MONITOR_NW4A3_5", + "MONITOR_SW4A0_3", + "MONITOR_SW4END1_5", + "MONITOR_TESTSCANCLK2", + "MONITOR_NE4C1_7", + "MONITOR_DI14", + "MONITOR_TESTDB13", + "MONITOR_SE4C0_8", + "MONITOR_LH7_4", + "MONITOR_EE4BEG2_2", + "MONITOR_IMUX46_3", + "MONITOR_WW4B3_8", + "MONITOR_EE4BEG3_7", + "MONITOR_IMUX17_8", + "MONITOR_SE2A1_6", + "MONITOR_EE4B1_4", + "MONITOR_IMUX47_2", + "MONITOR_LOGIC_OUTS_B15_3", + "MONITOR_SW2A2_0", + "MONITOR_IMUX46_8", + "MONITOR_EE4B0_9", + "MONITOR_IMUX41_4", + "MONITOR_ER1BEG0_7", + "MONITOR_EE2BEG0_1", + "MONITOR_FAN4_6", + "MONITOR_LOGIC_OUTS_B11_1", + "MONITOR_IMUX8_1", + "MONITOR_IMUX34_8", + "MONITOR_VAUXN15", + "MONITOR_IMUX24_2", + "MONITOR_SW4END3_9", + "MONITOR_LOGIC_OUTS_B16_4", + "MONITOR_LOGIC_OUTS_B21_2", + "MONITOR_FAN4_0", + "MONITOR_LH8_2", + "MONITOR_IMUX38_2", + "MONITOR_DADDR4", + "MONITOR_EE2BEG2_7", + "MONITOR_IMUX14_0", + "MONITOR_WW4C3_7", + "MONITOR_IMUX20_4", + "MONITOR_LH6_4", + "MONITOR_VERT_VAUXP11", + "MONITOR_DO14", + "MONITOR_BYP2_8", + "MONITOR_FAN1_2", + "MONITOR_EE2A0_3", + "MONITOR_LOGIC_OUTS_B20_8", + "MONITOR_EE4B3_0", + "MONITOR_FAN2_2", + "MONITOR_EE4BEG3_8", + "MONITOR_LOGIC_OUTS_B18_0", + "MONITOR_IMUX5_7", + "MONITOR_DADDR2", + "MONITOR_ER1BEG2_6", + "MONITOR_IMUX7_9", + "MONITOR_IMUX27_2", + "MONITOR_LOGIC_OUTS_B4_2", + "MONITOR_SW4END1_0", + "MONITOR_CTRL1_2", + "MONITOR_WW2A3_6", + "MONITOR_IMUX25_8", + "MONITOR_NE4BEG0_5", + "MONITOR_NW4END2_1", + "MONITOR_IMUX20_5", + "MONITOR_IMUX35_3", + "MONITOR_IMUX46_9", + "MONITOR_EE4A2_0", + "MONITOR_WW4B2_0", + "MONITOR_IMUX14_2", + "MONITOR_EL1BEG1_6", + "MONITOR_EE2A0_4", + "MONITOR_EE2BEG1_5", + "MONITOR_IMUX43_4", + "MONITOR_WW4A1_0", + "MONITOR_IMUX46_7", + "MONITOR_IMUX10_2", + "MONITOR_LOGIC_OUTS_B13_1", + "MONITOR_IMUX9_8", + "MONITOR_EE4A3_7", + "MONITOR_LOGIC_OUTS_B1_1", + "MONITOR_LH4_0", + "MONITOR_IMUX41_6", + "MONITOR_VERT_VAUXN10", + "MONITOR_NE2A0_1", + "MONITOR_WL1END3_5", + "MONITOR_WW2A1_8", + "MONITOR_TESTADCCLK0", + "MONITOR_OT", + "MONITOR_FAN7_5", + "MONITOR_CTRL0_3", + "MONITOR_BYP7_2", + "MONITOR_WW4B1_2", + "MONITOR_EE4B0_1", + "MONITOR_SE4BEG3_0", + "MONITOR_IMUX34_2", + "MONITOR_WW2A1_9", + "MONITOR_NE2A0_2", + "MONITOR_NW2A2_2", + "MONITOR_IMUX37_3", + "MONITOR_WW4END2_6", + "MONITOR_SW4A0_0", + "MONITOR_LH12_1", + "MONITOR_NE4BEG3_5", + "MONITOR_TESTRST", + "MONITOR_VERT_VAUXN4", + "MONITOR_TESTADCOUT18", + "MONITOR_TESTSCANCLK3", + "MONITOR_WW4A1_1", + "MONITOR_NE4BEG3_9", + "MONITOR_WW4END2_1", + "MONITOR_ER1BEG1_8", + "MONITOR_FAN5_7", + "MONITOR_WL1END3_9", + "MONITOR_SW4A0_1", + "MONITOR_LOGIC_OUTS_B7_2", + "MONITOR_EE4A2_3", + "MONITOR_NW4A0_4", + "MONITOR_BLOCK_OUTS_B0_1", + "MONITOR_BYP1_1", + "MONITOR_IMUX9_9", + "MONITOR_IMUX26_1", + "MONITOR_VP", + "MONITOR_LH7_6", + "MONITOR_WW4END1_7", + "MONITOR_LH1_1", + "MONITOR_LH10_7", + "MONITOR_IMUX33_3", + "MONITOR_LOGIC_OUTS_B2_7", + "MONITOR_WL1END0_5", + "MONITOR_IMUX45_4", + "MONITOR_NE2A0_3", + "MONITOR_EE4C3_2", + "MONITOR_IMUX24_3", + "MONITOR_DO7", + "MONITOR_NE4C2_1", + "MONITOR_LH1_4", + "MONITOR_EE2A3_4", + "MONITOR_NW4END3_2", + "MONITOR_NE4C1_6", + "MONITOR_LOGIC_OUTS_B7_0", + "MONITOR_IMUX22_8", + "MONITOR_TESTADCIN217", + "MONITOR_IMUX3_4", + "MONITOR_NE4BEG1_1", + "MONITOR_EL1BEG3_8", + "MONITOR_EE2A2_9", + "MONITOR_EE4B1_9", + "MONITOR_EE4B1_6", + "MONITOR_SE4BEG1_9", + "MONITOR_WW2A1_0", + "MONITOR_WR1END0_5", + "MONITOR_EE4B1_2", + "MONITOR_NW2A0_7", + "MONITOR_SE4BEG3_8", + "MONITOR_LOGIC_OUTS_B23_8", + "MONITOR_NW2A2_7", + "MONITOR_TESTADCOUT14", + "MONITOR_EE2A2_5", + "MONITOR_EE2A2_8", + "MONITOR_NW4END0_0", + "MONITOR_NE4BEG2_8", + "MONITOR_NE4C2_8", + "MONITOR_SW4A1_3", + "MONITOR_IMUX8_0", + "MONITOR_LOGIC_OUTS_B1_2", + "MONITOR_IMUX42_9", + "MONITOR_WW4A1_4", + "MONITOR_WW4C2_8", + "MONITOR_SW2A0_7", + "MONITOR_NW4A2_0", + "MONITOR_EE4C1_2", + "MONITOR_EE2BEG1_4", + "MONITOR_IMUX28_9", + "MONITOR_IMUX10_6", + "MONITOR_BYP4_8", + "MONITOR_TESTADCIN17", + "MONITOR_BYP0_7", + "MONITOR_SW2A3_7", + "MONITOR_DO3", + "MONITOR_WW2END0_0", + "MONITOR_VERT_VAUXP13", + "MONITOR_IMUX18_7", + "MONITOR_WR1END3_5", + "MONITOR_WW4END2_2", + "MONITOR_FAN5_6", + "MONITOR_NE4BEG3_3", + "MONITOR_WW2END2_4", + "MONITOR_EE4A2_8", + "MONITOR_NW4END1_1", + "MONITOR_TESTSCANMODE2", + "MONITOR_SE4BEG0_9", + "MONITOR_VERT_VAUXP15", + "MONITOR_EE2A1_6", + "MONITOR_BYP1_0", + "MONITOR_NE4C0_0", + "MONITOR_EL1BEG3_3", + "MONITOR_IMUX7_1", + "MONITOR_LH8_3", + "MONITOR_NE4C2_5", + "MONITOR_IMUX23_2", + "MONITOR_EE4A0_6", + "MONITOR_ER1BEG1_5", + "MONITOR_CTRL0_9", + "MONITOR_LOGIC_OUTS_B22_8", + "MONITOR_SE4C1_6", + "MONITOR_WW4END1_2", + "MONITOR_DADDR6", + "MONITOR_BLOCK_OUTS_B2_8", + "MONITOR_EE4BEG1_8", + "MONITOR_IMUX42_5", + "MONITOR_EE4B0_5", + "MONITOR_SE4BEG1_8", + "MONITOR_BYP5_9", + "MONITOR_TESTADCOUT17", + "MONITOR_IMUX13_7", + "MONITOR_IMUX45_8", + "MONITOR_NE4BEG3_2", + "MONITOR_WW2END3_7", + "MONITOR_BLOCK_OUTS_B0_9", + "MONITOR_IMUX35_0", + "MONITOR_IMUX33_8", + "MONITOR_EE4BEG0_6", + "MONITOR_VAUXN12", + "MONITOR_LOGIC_OUTS_B8_5", + "MONITOR_LOGIC_OUTS_B9_0", + "MONITOR_EE2BEG2_5", + "MONITOR_BLOCK_OUTS_B3_6", + "MONITOR_TESTSE0", + "MONITOR_TESTADCIN7", + "MONITOR_SW4END0_1", + "MONITOR_IMUX37_9", + "MONITOR_ER1BEG1_4", + "MONITOR_LOGIC_OUTS_B7_8", + "MONITOR_IMUX3_7", + "MONITOR_JTAGBUSY", + "MONITOR_LOGIC_OUTS_B16_1", + "MONITOR_EE2A2_2", + "MONITOR_WW2END2_2", + "MONITOR_BYP5_1", + "MONITOR_FAN4_1", + "MONITOR_LOGIC_OUTS_B13_4", + "MONITOR_BYP7_6", + "MONITOR_NE4BEG2_1", + "MONITOR_WR1END1_2", + "MONITOR_IMUX8_7", + "MONITOR_LH8_1", + "MONITOR_LOGIC_OUTS_B2_4", + "MONITOR_WL1END2_8", + "MONITOR_NW4A3_4", + "MONITOR_BLOCK_OUTS_B3_3", + "MONITOR_SE4C3_5", + "MONITOR_WW4C0_7", + "MONITOR_FAN1_3", + "MONITOR_BYP5_7", + "MONITOR_WW4A1_2", + "MONITOR_SE4BEG1_0", + "MONITOR_FAN7_4", + "MONITOR_WW4A0_4", + "MONITOR_VERT_VAUXP12", + "MONITOR_EE4A0_8", + "MONITOR_EE4B1_5", + "MONITOR_WW2A1_4", + "MONITOR_EE4A1_3", + "MONITOR_BYP3_4", + "MONITOR_NW4A1_8", + "MONITOR_IMUX11_0", + "MONITOR_VAUXP3", + "MONITOR_SE4BEG3_5", + "MONITOR_IMUX6_0", + "MONITOR_IMUX4_8", + "MONITOR_IMUX12_4", + "MONITOR_IMUX30_9", + "MONITOR_IMUX25_2", + "MONITOR_VAUXP5", + "MONITOR_BYP7_4", + "MONITOR_NW4END1_6", + "MONITOR_LOGIC_OUTS_B6_3", + "MONITOR_VERT_VAUXP8", + "MONITOR_LOGIC_OUTS_B8_8", + "MONITOR_EE4A1_1", + "MONITOR_IMUX46_6", + "MONITOR_LOGIC_OUTS_B20_2", + "MONITOR_WW4A3_5", + "MONITOR_IMUX2_7", + "MONITOR_WW2END2_3", + "MONITOR_NE4C2_6", + "MONITOR_BYP5_5", + "MONITOR_VAUXN0", + "MONITOR_LOGIC_OUTS_B1_9", + "MONITOR_SE4C2_9", + "MONITOR_EE4BEG1_9", + "MONITOR_IMUX17_5", + "MONITOR_NW4A0_3", + "MONITOR_WW2END2_7", + "MONITOR_SW2A2_5", + "MONITOR_SW4A1_6", + "MONITOR_WW4B1_1", + "MONITOR_IMUX40_7", + "MONITOR_LOGIC_OUTS_B5_6", + "MONITOR_IMUX37_7", + "MONITOR_NE2A2_3", + "MONITOR_FAN0_3", + "MONITOR_SE4C0_3", + "MONITOR_IMUX22_7", + "MONITOR_SW2A0_6", + "MONITOR_LOGIC_OUTS_B14_5", + "MONITOR_LH6_5", + "MONITOR_IMUX44_0", + "MONITOR_IMUX43_8", + "MONITOR_NE2A0_0", + "MONITOR_NW2A3_6", + "MONITOR_ER1BEG1_2", + "MONITOR_HORIZ_VAUXN11", + "MONITOR_FAN3_0", + "MONITOR_LOGIC_OUTS_B14_3", + "MONITOR_IMUX41_0", + "MONITOR_NE4C2_0", + "MONITOR_NW2A3_4", + "MONITOR_LOGIC_OUTS_B5_5", + "MONITOR_LH5_2", + "MONITOR_LOGIC_OUTS_B3_2", + "MONITOR_EL1BEG0_2", + "MONITOR_CLK0_6", + "MONITOR_SW4END3_1", + "MONITOR_IMUX17_6", + "MONITOR_EE4C3_1", + "MONITOR_CHANNEL4", + "MONITOR_IMUX13_1", + "MONITOR_LH9_3", + "MONITOR_EE2BEG0_7", + "MONITOR_VERT_VAUXN0", + "MONITOR_FAN7_8", + "MONITOR_TESTDB9", + "MONITOR_FAN5_0", + "MONITOR_SE4BEG0_7", + "MONITOR_LOGIC_OUTS_B20_9", + "MONITOR_LOGIC_OUTS_B11_4", + "MONITOR_NW4END2_8", + "MONITOR_IMUX37_5", + "MONITOR_IMUX26_3", + "MONITOR_LOGIC_OUTS_B9_9", + "MONITOR_LH7_3", + "MONITOR_IMUX18_5", + "MONITOR_WR1END1_9", + "MONITOR_EE4C0_5", + "MONITOR_NW4END1_4", + "MONITOR_LH2_5", + "MONITOR_EL1BEG2_1", + "MONITOR_NW4A1_4", + "MONITOR_VERT_VAUXN9", + "MONITOR_LOGIC_OUTS_B15_7", + "MONITOR_VERT_VAUXP5", + "MONITOR_BYP6_2", + "MONITOR_IMUX21_5", + "MONITOR_IMUX20_7", + "MONITOR_SW4END1_7", + "MONITOR_IMUX45_0", + "MONITOR_EE4B0_4", + "MONITOR_FAN3_4", + "MONITOR_TESTSCANCLK4", + "MONITOR_NW2A0_8", + "MONITOR_FAN1_8", + "MONITOR_SE4BEG3_4", + "MONITOR_LH5_5", + "MONITOR_NE4BEG3_0", + "MONITOR_NW2A1_1", + "MONITOR_BLOCK_OUTS_B1_7", + "MONITOR_IMUX9_6", + "MONITOR_SE4BEG2_6", + "MONITOR_LH7_9", + "MONITOR_FAN1_9", + "MONITOR_WW2END0_2", + "MONITOR_IMUX44_5", + "MONITOR_IMUX22_9", + "MONITOR_IMUX19_1", + "MONITOR_DWE", + "MONITOR_IMUX36_4", + "MONITOR_NW2A1_2", + "MONITOR_SW4A1_1", + "MONITOR_IMUX18_8", + "MONITOR_VERT_VAUXN11", + "MONITOR_DI0", + "MONITOR_WW4C2_7", + "MONITOR_IMUX16_9", + "MONITOR_EE4B3_4", + "MONITOR_IMUX19_9", + "MONITOR_IMUX38_5", + "MONITOR_WL1END1_5", + "MONITOR_VAUXP6", + "MONITOR_CTRL1_6", + "MONITOR_IMUX38_9", + "MONITOR_NW4END2_0", + "MONITOR_IMUX36_9", + "MONITOR_EE4B0_3", + "MONITOR_ER1BEG0_6", + "MONITOR_CLK1_4", + "MONITOR_WW4B0_6", + "MONITOR_NE4BEG1_5", + "MONITOR_SW4END0_3", + "MONITOR_BYP6_0", + "MONITOR_NW2A3_5", + "MONITOR_ER1BEG1_1", + "MONITOR_SE4BEG2_4", + "MONITOR_EE2BEG3_3", + "MONITOR_NE2A2_0", + "MONITOR_LOGIC_OUTS_B4_3", + "MONITOR_TESTADCOUT12", + "MONITOR_EL1BEG3_5", + "MONITOR_WW4B1_7", + "MONITOR_WL1END0_1", + "MONITOR_NW2A2_9", + "MONITOR_TESTADCCLK1", + "MONITOR_IMUX29_7", + "MONITOR_IMUX43_5", + "MONITOR_EE4B3_5", + "MONITOR_EE2A3_9", + "MONITOR_SE2A1_2", + "MONITOR_EE2BEG1_2", + "MONITOR_NE4C2_4", + "MONITOR_WW4END3_5", + "MONITOR_SE4BEG2_3", + "MONITOR_SE4BEG0_1", + "MONITOR_LOGIC_OUTS_B17_1", + "MONITOR_LH10_4", + "MONITOR_LH8_6", + "MONITOR_NW4A0_1", + "MONITOR_CTRL1_8", + "MONITOR_LOGIC_OUTS_B11_9", + "MONITOR_IMUX11_7", + "MONITOR_TESTADCIN214", + "MONITOR_WW4C1_2", + "MONITOR_DI1", + "MONITOR_IMUX34_6", + "MONITOR_WW2END1_0", + "MONITOR_WW4A1_6", + "MONITOR_IMUX12_0", + "MONITOR_LOGIC_OUTS_B23_4", + "MONITOR_SW2A0_0", + "MONITOR_BYP2_6", + "MONITOR_IMUX38_8", + "MONITOR_SE4BEG1_3", + "MONITOR_SE4C2_8", + "MONITOR_SE2A1_1", + "MONITOR_BLOCK_OUTS_B3_7", + "MONITOR_SE4C2_0", + "MONITOR_IMUX11_8", + "MONITOR_IMUX34_7", + "MONITOR_IMUX42_3", + "MONITOR_EE4BEG3_9", + "MONITOR_TESTSO4", + "MONITOR_WW4END1_4", + "MONITOR_EE4C3_8", + "MONITOR_IMUX47_3", + "MONITOR_EE2BEG1_6", + "MONITOR_IMUX45_7", + "MONITOR_NE4BEG2_2", + "MONITOR_IMUX12_9", + "MONITOR_VERT_VAUXP10", + "MONITOR_ER1BEG2_8", + "MONITOR_WL1END3_4", + "MONITOR_FAN6_4", + "MONITOR_WW4C0_1", + "MONITOR_LH7_5", + "MONITOR_LOGIC_OUTS_B20_3", + "MONITOR_LOGIC_OUTS_B21_3", + "MONITOR_NW4END3_6", + "MONITOR_WL1END0_0", + "MONITOR_IMUX31_5", + "MONITOR_EL1BEG3_6", + "MONITOR_IMUX32_3", + "MONITOR_EE2A2_7", + "MONITOR_SE4C1_8", + "MONITOR_VAUXN8", + "MONITOR_IMUX29_8", + "MONITOR_TESTADCIN29", + "MONITOR_WW4A3_2", + "MONITOR_ER1BEG3_4", + "MONITOR_IMUX36_7", + "MONITOR_IMUX36_3", + "MONITOR_WW4C3_4", + "MONITOR_WW4B1_3", + "MONITOR_LH8_4", + "MONITOR_IMUX14_3", + "MONITOR_SW4END3_6", + "MONITOR_NW2A3_7", + "MONITOR_NW4A2_9", + "MONITOR_NE4BEG0_3", + "MONITOR_EE4C2_7", + "MONITOR_TESTSE3", + "MONITOR_SE4BEG1_6", + "MONITOR_SE4C3_8", + "MONITOR_WW4A0_7", + "MONITOR_BLOCK_OUTS_B3_8", + "MONITOR_NW2A3_1", + "MONITOR_IMUX42_0", + "MONITOR_FAN5_1", + "MONITOR_CTRL0_4", + "MONITOR_BLOCK_OUTS_B1_8", + "MONITOR_BUSY", + "MONITOR_VAUXN3", + "MONITOR_IMUX15_2", + "MONITOR_IMUX6_4", + "MONITOR_EE2BEG2_9", + "MONITOR_IMUX25_9", + "MONITOR_ER1BEG2_7", + "MONITOR_IMUX28_4", + "MONITOR_IMUX33_6", + "MONITOR_LOGIC_OUTS_B9_6", + "MONITOR_WW4A3_0", + "MONITOR_WW4END1_9", + "MONITOR_TESTSO0", + "MONITOR_VAUXN4", + "MONITOR_SE2A0_9", + "MONITOR_NE2A2_8", + "MONITOR_SW2A0_4", + "MONITOR_NW4END3_7", + "MONITOR_LOGIC_OUTS_B15_9", + "MONITOR_EE4BEG2_8", + "MONITOR_WW4B3_7", + "MONITOR_IMUX44_4", + "MONITOR_TESTSI1", + "MONITOR_NE4C3_0", + "MONITOR_LOGIC_OUTS_B2_8", + "MONITOR_LOGIC_OUTS_B12_1", + "MONITOR_BLOCK_OUTS_B2_0", + "MONITOR_CTRL1_1", + "MONITOR_NW4A0_7", + "MONITOR_EE2A2_6", + "MONITOR_IMUX21_1", + "MONITOR_WW4END0_2", + "MONITOR_LH3_5", + "MONITOR_BLOCK_OUTS_B2_2", + "MONITOR_LH5_3", + "MONITOR_WW4END0_5", + "MONITOR_VERT_VAUXP0", + "MONITOR_WW2A0_8", + "MONITOR_LH6_9", + "MONITOR_EE2BEG0_5", + "MONITOR_LH1_7", + "MONITOR_CLK1_5", + "MONITOR_LOGIC_OUTS_B19_5", + "MONITOR_ALM6", + "MONITOR_EL1BEG3_2", + "MONITOR_EE4BEG3_3", + "MONITOR_TESTADCIN216", + "MONITOR_BYP7_1", + "MONITOR_TESTSE1", + "MONITOR_BLOCK_OUTS_B0_6", + "MONITOR_IMUX33_1", + "MONITOR_IMUX22_3", + "MONITOR_BYP7_8", + "MONITOR_EE4BEG0_3", + "MONITOR_LH6_7", + "MONITOR_VAUXN11", + "MONITOR_NE2A1_9", + "MONITOR_WW4A2_4", + "MONITOR_LH3_3", + "MONITOR_TESTADCIN1", + "MONITOR_NE4BEG1_2", + "MONITOR_SE2A2_9", + "MONITOR_DO8", + "MONITOR_VAUXP0", + "MONITOR_FAN1_4", + "MONITOR_IMUX24_1", + "MONITOR_IMUX2_9", + "MONITOR_SW4END1_3", + "MONITOR_WW4C2_9", + "MONITOR_NE4C3_5", + "MONITOR_IMUX13_2", + "MONITOR_IMUX24_6", + "MONITOR_IMUX5_2", + "MONITOR_NE2A0_5", + "MONITOR_LOGIC_OUTS_B18_6", + "MONITOR_TESTADCIN19", + "MONITOR_IMUX13_8", + "MONITOR_BLOCK_OUTS_B2_5", + "MONITOR_LOGIC_OUTS_B3_9", + "MONITOR_LOGIC_OUTS_B5_2", + "MONITOR_TESTADCIN211", + "MONITOR_LH5_4", + "MONITOR_LOGIC_OUTS_B2_0", + "MONITOR_WW4A2_7", + "MONITOR_BYP7_9", + "MONITOR_CTRL1_7", + "MONITOR_EE2A3_7", + "MONITOR_NE4BEG3_4", + "MONITOR_IMUX14_1", + "MONITOR_SW4A2_8", + "MONITOR_IMUX17_2", + "MONITOR_WW4END2_3", + "MONITOR_TESTSO2", + "MONITOR_DI8", + "MONITOR_WW2A0_1", + "MONITOR_IMUX30_7", + "MONITOR_IMUX11_6", + "MONITOR_VAUXP10", + "MONITOR_WW4A2_1", + "MONITOR_IMUX3_8", + "MONITOR_EE2BEG3_4", + "MONITOR_EE4B3_6", + "MONITOR_IMUX47_6", + "MONITOR_WL1END2_2", + "MONITOR_NE4BEG1_8", + "MONITOR_MUXADDR2", + "MONITOR_IMUX4_9", + "MONITOR_SW4A0_6", + "MONITOR_SW4END2_5", + "MONITOR_EE4B3_7", + "MONITOR_IMUX44_6", + "MONITOR_NW2A3_2", + "MONITOR_ER1BEG2_3", + "MONITOR_SW4A3_3", + "MONITOR_WW4B1_0", + "MONITOR_FAN6_9", + "MONITOR_SW2A3_1", + "MONITOR_IMUX3_2", + "MONITOR_CTRL1_0", + "MONITOR_IMUX47_0", + "MONITOR_SE4BEG0_0", + "MONITOR_TESTENJTAG", + "MONITOR_BYP5_3", + "MONITOR_NE4BEG3_6", + "MONITOR_EL1BEG0_7", + "MONITOR_BYP6_9", + "MONITOR_FAN6_1", + "MONITOR_IMUX40_0", + "MONITOR_BYP7_5", + "MONITOR_EL1BEG2_6" + ], + "pips": { + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP2->MONITOR_VAUXP2": { + "src_wire": "MONITOR_VERT_VAUXP2", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_ALM7->MONITOR_LOGIC_OUTS_B18_2": { + "src_wire": "MONITOR_ALM7", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B18_2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_JTAGBUSY->MONITOR_LOGIC_OUTS_B13_1": { + "src_wire": "MONITOR_JTAGBUSY", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B13_1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO2->MONITOR_LOGIC_OUTS_B10_0": { + "src_wire": "MONITOR_DO2", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B10_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_ALM5->MONITOR_LOGIC_OUTS_B16_2": { + "src_wire": "MONITOR_ALM5", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B16_2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX40_1->MONITOR_DADDR6": { + "src_wire": "MONITOR_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX33_0->MONITOR_DI5": { + "src_wire": "MONITOR_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI5", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP12->MONITOR_VAUXP12": { + "src_wire": "MONITOR_VERT_VAUXP12", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP12", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP11->MONITOR_VAUXP11": { + "src_wire": "MONITOR_VERT_VAUXP11", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP11", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_BUSY->MONITOR_LOGIC_OUTS_B20_1": { + "src_wire": "MONITOR_BUSY", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B20_1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP5->MONITOR_VAUXP5": { + "src_wire": "MONITOR_VERT_VAUXP5", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP5", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN4->MONITOR_VAUXN4": { + "src_wire": "MONITOR_VERT_VAUXN4", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN4", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO15->MONITOR_LOGIC_OUTS_B23_0": { + "src_wire": "MONITOR_DO15", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B23_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO10->MONITOR_LOGIC_OUTS_B18_0": { + "src_wire": "MONITOR_DO10", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B18_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX35_1->MONITOR_DADDR1": { + "src_wire": "MONITOR_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX36_0->MONITOR_DI8": { + "src_wire": "MONITOR_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI8", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP0->MONITOR_VAUXP0": { + "src_wire": "MONITOR_VERT_VAUXP0", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO1->MONITOR_LOGIC_OUTS_B9_0": { + "src_wire": "MONITOR_DO1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B9_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXP12_LEFT->MONITOR_VERT_VAUXP12": { + "src_wire": "MONITOR_HORIZ_VAUXP12_LEFT", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP12", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX29_0->MONITOR_DI1": { + "src_wire": "MONITOR_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO11->MONITOR_LOGIC_OUTS_B19_0": { + "src_wire": "MONITOR_DO11", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B19_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO3->MONITOR_LOGIC_OUTS_B11_0": { + "src_wire": "MONITOR_DO3", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B11_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_SEG_VP->MONITOR_VP": { + "src_wire": "MONITOR_SEG_VP", + "is_pseudo": "0", + "dst_wire": "MONITOR_VP", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO9->MONITOR_LOGIC_OUTS_B17_0": { + "src_wire": "MONITOR_DO9", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B17_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO4->MONITOR_LOGIC_OUTS_B12_0": { + "src_wire": "MONITOR_DO4", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B12_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_CHANNEL2->MONITOR_LOGIC_OUTS_B17_1": { + "src_wire": "MONITOR_CHANNEL2", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B17_1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_CHANNEL4->MONITOR_LOGIC_OUTS_B19_1": { + "src_wire": "MONITOR_CHANNEL4", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B19_1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXP4_LEFT->MONITOR_VERT_VAUXP4": { + "src_wire": "MONITOR_HORIZ_VAUXP4_LEFT", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP4", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO0->MONITOR_LOGIC_OUTS_B8_0": { + "src_wire": "MONITOR_DO0", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B8_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX38_1->MONITOR_DADDR4": { + "src_wire": "MONITOR_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX36_1->MONITOR_DADDR2": { + "src_wire": "MONITOR_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN5->MONITOR_VAUXN5": { + "src_wire": "MONITOR_VERT_VAUXN5", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN5", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_ALM4->MONITOR_LOGIC_OUTS_B15_2": { + "src_wire": "MONITOR_ALM4", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B15_2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX30_0->MONITOR_DI2": { + "src_wire": "MONITOR_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN2->MONITOR_VAUXN2": { + "src_wire": "MONITOR_VERT_VAUXN2", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN12->MONITOR_VAUXN12": { + "src_wire": "MONITOR_VERT_VAUXN12", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN12", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_ALM2->MONITOR_LOGIC_OUTS_B13_2": { + "src_wire": "MONITOR_ALM2", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B13_2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP10->MONITOR_VAUXP10": { + "src_wire": "MONITOR_VERT_VAUXP10", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP10", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX37_0->MONITOR_DI9": { + "src_wire": "MONITOR_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI9", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN11->MONITOR_VAUXN11": { + "src_wire": "MONITOR_VERT_VAUXN11", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN11", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX41_0->MONITOR_DI13": { + "src_wire": "MONITOR_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI13", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX43_1->MONITOR_CONVST": { + "src_wire": "MONITOR_IMUX43_1", + "is_pseudo": "0", + "dst_wire": "MONITOR_CONVST", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXN3->MONITOR_VERT_VAUXN3": { + "src_wire": "MONITOR_HORIZ_VAUXN3", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN3", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_EOC->MONITOR_LOGIC_OUTS_B22_1": { + "src_wire": "MONITOR_EOC", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B22_1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO6->MONITOR_LOGIC_OUTS_B14_0": { + "src_wire": "MONITOR_DO6", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B14_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX34_0->MONITOR_DI6": { + "src_wire": "MONITOR_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI6", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO8->MONITOR_LOGIC_OUTS_B16_0": { + "src_wire": "MONITOR_DO8", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B16_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN10->MONITOR_VAUXN10": { + "src_wire": "MONITOR_VERT_VAUXN10", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN10", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_OT->MONITOR_LOGIC_OUTS_B21_1": { + "src_wire": "MONITOR_OT", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B21_1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_CLK1_0->MONITOR_DCLK": { + "src_wire": "MONITOR_CLK1_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DCLK", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX42_1->MONITOR_DWE": { + "src_wire": "MONITOR_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DWE", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_CHANNEL1->MONITOR_LOGIC_OUTS_B16_1": { + "src_wire": "MONITOR_CHANNEL1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B16_1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN3->MONITOR_VAUXN3": { + "src_wire": "MONITOR_VERT_VAUXN3", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN3", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO7->MONITOR_LOGIC_OUTS_B15_0": { + "src_wire": "MONITOR_DO7", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B15_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO13->MONITOR_LOGIC_OUTS_B21_0": { + "src_wire": "MONITOR_DO13", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B21_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_MUXADDR0->MONITOR_LOGIC_OUTS_B19_2": { + "src_wire": "MONITOR_MUXADDR0", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B19_2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN1->MONITOR_VAUXN1": { + "src_wire": "MONITOR_VERT_VAUXN1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_CHANNEL0->MONITOR_LOGIC_OUTS_B15_1": { + "src_wire": "MONITOR_CHANNEL0", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B15_1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_ALM6->MONITOR_LOGIC_OUTS_B17_2": { + "src_wire": "MONITOR_ALM6", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B17_2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP1->MONITOR_VAUXP1": { + "src_wire": "MONITOR_VERT_VAUXP1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXN5_LEFT->MONITOR_VERT_VAUXN5": { + "src_wire": "MONITOR_HORIZ_VAUXN5_LEFT", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN5", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_MUXADDR1->MONITOR_LOGIC_OUTS_B20_2": { + "src_wire": "MONITOR_MUXADDR1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B20_2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_CLK1_1->MONITOR_CONVSTCLK": { + "src_wire": "MONITOR_CLK1_1", + "is_pseudo": "0", + "dst_wire": "MONITOR_CONVSTCLK", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_ALM0->MONITOR_LOGIC_OUTS_B11_2": { + "src_wire": "MONITOR_ALM0", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B11_2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP9->MONITOR_VAUXP9": { + "src_wire": "MONITOR_VERT_VAUXP9", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP9", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXP11->MONITOR_VERT_VAUXP11": { + "src_wire": "MONITOR_HORIZ_VAUXP11", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP11", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX43_0->MONITOR_DI15": { + "src_wire": "MONITOR_IMUX43_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI15", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXP5_LEFT->MONITOR_VERT_VAUXP5": { + "src_wire": "MONITOR_HORIZ_VAUXP5_LEFT", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP5", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX40_0->MONITOR_DI12": { + "src_wire": "MONITOR_IMUX40_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI12", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO5->MONITOR_LOGIC_OUTS_B13_0": { + "src_wire": "MONITOR_DO5", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B13_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO12->MONITOR_LOGIC_OUTS_B20_0": { + "src_wire": "MONITOR_DO12", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B20_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN9->MONITOR_VAUXN9": { + "src_wire": "MONITOR_VERT_VAUXN9", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN9", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_ALM3->MONITOR_LOGIC_OUTS_B14_2": { + "src_wire": "MONITOR_ALM3", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B14_2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX32_0->MONITOR_DI4": { + "src_wire": "MONITOR_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI4", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX39_1->MONITOR_DADDR5": { + "src_wire": "MONITOR_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXP3->MONITOR_VERT_VAUXP3": { + "src_wire": "MONITOR_HORIZ_VAUXP3", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP3", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX28_0->MONITOR_DI0": { + "src_wire": "MONITOR_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_CHANNEL3->MONITOR_LOGIC_OUTS_B18_1": { + "src_wire": "MONITOR_CHANNEL3", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B18_1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DRDY->MONITOR_LOGIC_OUTS_B14_1": { + "src_wire": "MONITOR_DRDY", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B14_1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX42_0->MONITOR_DI14": { + "src_wire": "MONITOR_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI14", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN0->MONITOR_VAUXN0": { + "src_wire": "MONITOR_VERT_VAUXN0", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXN4_LEFT->MONITOR_VERT_VAUXN4": { + "src_wire": "MONITOR_HORIZ_VAUXN4_LEFT", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN4", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX37_1->MONITOR_DADDR3": { + "src_wire": "MONITOR_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN8->MONITOR_VAUXN8": { + "src_wire": "MONITOR_VERT_VAUXN8", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN8", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX41_1->MONITOR_DEN": { + "src_wire": "MONITOR_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DEN", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_DO14->MONITOR_LOGIC_OUTS_B22_0": { + "src_wire": "MONITOR_DO14", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B22_0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP4->MONITOR_VAUXP4": { + "src_wire": "MONITOR_VERT_VAUXP4", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP4", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_JTAGMODIFIED->MONITOR_LOGIC_OUTS_B12_1": { + "src_wire": "MONITOR_JTAGMODIFIED", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B12_1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXN12_LEFT->MONITOR_VERT_VAUXN12": { + "src_wire": "MONITOR_HORIZ_VAUXN12_LEFT", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN12", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_MUXADDR4->MONITOR_LOGIC_OUTS_B23_2": { + "src_wire": "MONITOR_MUXADDR4", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B23_2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX38_0->MONITOR_DI10": { + "src_wire": "MONITOR_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI10", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_CTRL1_2->MONITOR_RESET": { + "src_wire": "MONITOR_CTRL1_2", + "is_pseudo": "0", + "dst_wire": "MONITOR_RESET", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP3->MONITOR_VAUXP3": { + "src_wire": "MONITOR_VERT_VAUXP3", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP3", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX39_0->MONITOR_DI11": { + "src_wire": "MONITOR_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI11", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_ALM1->MONITOR_LOGIC_OUTS_B12_2": { + "src_wire": "MONITOR_ALM1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B12_2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXN11->MONITOR_VERT_VAUXN11": { + "src_wire": "MONITOR_HORIZ_VAUXN11", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN11", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_MUXADDR2->MONITOR_LOGIC_OUTS_B21_2": { + "src_wire": "MONITOR_MUXADDR2", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B21_2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX35_0->MONITOR_DI7": { + "src_wire": "MONITOR_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI7", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_MUXADDR3->MONITOR_LOGIC_OUTS_B22_2": { + "src_wire": "MONITOR_MUXADDR3", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B22_2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_EOS->MONITOR_LOGIC_OUTS_B23_1": { + "src_wire": "MONITOR_EOS", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B23_1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_SEG_VN->MONITOR_VN": { + "src_wire": "MONITOR_SEG_VN", + "is_pseudo": "0", + "dst_wire": "MONITOR_VN", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_JTAGLOCKED->MONITOR_LOGIC_OUTS_B11_1": { + "src_wire": "MONITOR_JTAGLOCKED", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B11_1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP8->MONITOR_VAUXP8": { + "src_wire": "MONITOR_VERT_VAUXP8", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP8", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX34_1->MONITOR_DADDR0": { + "src_wire": "MONITOR_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_BOT_FUJI2.MONITOR_IMUX31_0->MONITOR_DI3": { + "src_wire": "MONITOR_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI3", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_MONITOR_MID_FUJI2.json b/kintex7/tile_type_MONITOR_MID_FUJI2.json new file mode 100644 index 0000000..ac5619d --- /dev/null +++ b/kintex7/tile_type_MONITOR_MID_FUJI2.json @@ -0,0 +1,2304 @@ +{ + "tile_type": "MONITOR_MID_FUJI2", + "sites": [], + "wires": [ + "MONITOR_BYP1_6", + "MONITOR_SE4BEG0_6", + "MONITOR_IMUX5_6", + "MONITOR_LH12_4", + "MONITOR_LOGIC_OUTS_B2_9", + "MONITOR_CTRL0_8", + "MONITOR_EE4C1_8", + "MONITOR_IMUX36_2", + "MONITOR_IMUX35_4", + "MONITOR_WW4C1_3", + "MONITOR_EE4B3_8", + "MONITOR_EE2A1_7", + "MONITOR_NW2A2_8", + "MONITOR_EE2BEG1_0", + "MONITOR_BYP2_4", + "MONITOR_NW4END2_3", + "MONITOR_BLOCK_OUTS_B2_3", + "MONITOR_LOGIC_OUTS_B0_7", + "MONITOR_CLK0_2", + "MONITOR_LOGIC_OUTS_B8_3", + "MONITOR_WW4END0_0", + "MONITOR_WW2A0_4", + "MONITOR_EE2BEG2_6", + "MONITOR_EE4A1_7", + "MONITOR_IMUX37_2", + "MONITOR_HORIZ_VAUXP9", + "MONITOR_WW2END3_1", + "MONITOR_LH2_4", + "MONITOR_WL1END1_8", + "MONITOR_EE4B2_2", + "MONITOR_FAN4_3", + "MONITOR_IMUX34_5", + "MONITOR_WW2END1_5", + "MONITOR_BYP2_2", + "MONITOR_WW2A1_2", + "MONITOR_EE2A3_0", + "MONITOR_WW2END3_0", + "MONITOR_SE2A2_3", + "MONITOR_NW4A2_8", + "MONITOR_EE2BEG2_0", + "MONITOR_NE4BEG0_8", + "MONITOR_LOGIC_OUTS_B8_0", + "MONITOR_SW4END3_4", + "MONITOR_EE4C3_6", + "MONITOR_EE4BEG3_4", + "MONITOR_LOGIC_OUTS_B15_8", + "MONITOR_WL1END3_8", + "MONITOR_WW4B1_9", + "MONITOR_LOGIC_OUTS_B23_7", + "MONITOR_EE4C0_3", + "MONITOR_EE4B2_1", + "MONITOR_WW4B3_3", + "MONITOR_NE4C0_6", + "MONITOR_IMUX45_6", + "MONITOR_SE2A1_5", + "MONITOR_SE4C2_6", + "MONITOR_NE2A2_7", + "MONITOR_IMUX29_0", + "MONITOR_IMUX19_0", + "MONITOR_LH1_2", + "MONITOR_BYP7_7", + "MONITOR_BYP5_0", + "MONITOR_LH1_9", + "MONITOR_NE4C3_1", + "MONITOR_EL1BEG0_8", + "MONITOR_SW4END1_4", + "MONITOR_EE2A1_0", + "MONITOR_ER1BEG3_9", + "MONITOR_SE2A0_6", + "MONITOR_SE4BEG1_5", + "MONITOR_IMUX34_0", + "MONITOR_LOGIC_OUTS_B3_6", + "MONITOR_IMUX32_6", + "MONITOR_IMUX27_1", + "MONITOR_IMUX38_7", + "MONITOR_NW2A2_1", + "MONITOR_LOGIC_OUTS_B23_2", + "MONITOR_EE4A3_3", + "MONITOR_CLK0_8", + "MONITOR_IMUX21_8", + "MONITOR_WW2A2_2", + "MONITOR_IMUX42_4", + "MONITOR_WW4A0_6", + "MONITOR_SE2A2_2", + "MONITOR_WW4C1_8", + "MONITOR_WW4B0_7", + "MONITOR_SE4C3_9", + "MONITOR_SW4A0_9", + "MONITOR_BYP4_0", + "MONITOR_LH7_7", + "MONITOR_WW4A0_9", + "MONITOR_IMUX28_8", + "MONITOR_LOGIC_OUTS_B10_6", + "MONITOR_LOGIC_OUTS_B19_6", + "MONITOR_IMUX30_5", + "MONITOR_IMUX25_7", + "MONITOR_IMUX18_4", + "MONITOR_LOGIC_OUTS_B19_8", + "MONITOR_WW4B0_0", + "MONITOR_LH1_3", + "MONITOR_SW2A2_8", + "MONITOR_WW4A1_5", + "MONITOR_ER1BEG3_1", + "MONITOR_SE4C0_0", + "MONITOR_IMUX0_8", + "MONITOR_LH5_0", + "MONITOR_IMUX13_4", + "MONITOR_EE4A1_0", + "MONITOR_LH12_0", + "MONITOR_BYP0_5", + "MONITOR_LOGIC_OUTS_B6_9", + "MONITOR_IMUX34_9", + "MONITOR_SE4C1_9", + "MONITOR_IMUX3_1", + "MONITOR_EE4C2_6", + "MONITOR_NE2A1_8", + "MONITOR_CLK0_3", + "MONITOR_WR1END1_0", + "MONITOR_LOGIC_OUTS_B20_6", + "MONITOR_SW4A0_8", + "MONITOR_FAN7_6", + "MONITOR_IMUX40_9", + "MONITOR_IMUX17_9", + "MONITOR_NE2A0_7", + "MONITOR_LOGIC_OUTS_B10_3", + "MONITOR_EE4C2_4", + "MONITOR_IMUX36_0", + "MONITOR_BYP1_8", + "MONITOR_EL1BEG2_8", + "MONITOR_NE2A3_1", + "MONITOR_LH4_4", + "MONITOR_LOGIC_OUTS_B6_7", + "MONITOR_IMUX16_3", + "MONITOR_IMUX40_1", + "MONITOR_EE4C3_4", + "MONITOR_WW4A0_0", + "MONITOR_IMUX0_3", + "MONITOR_LH6_2", + "MONITOR_IMUX4_0", + "MONITOR_BLOCK_OUTS_B1_2", + "MONITOR_WL1END1_3", + "MONITOR_SE4C2_5", + "MONITOR_SE4BEG3_2", + "MONITOR_EE2BEG0_9", + "MONITOR_EE4BEG0_1", + "MONITOR_IMUX23_8", + "MONITOR_SE4BEG3_9", + "MONITOR_IMUX33_9", + "MONITOR_IMUX5_9", + "MONITOR_NW4A3_2", + "MONITOR_EE2A3_1", + "MONITOR_EL1BEG2_2", + "MONITOR_WR1END2_2", + "MONITOR_IMUX8_9", + "MONITOR_WW4C2_1", + "MONITOR_EE2BEG0_8", + "MONITOR_NE4C2_2", + "MONITOR_WL1END3_6", + "MONITOR_NE4BEG0_6", + "MONITOR_VERT_VAUXN5", + "MONITOR_SW4END0_8", + "MONITOR_EE2A1_9", + "MONITOR_LOGIC_OUTS_B12_3", + "MONITOR_HORIZ_VAUXN1", + "MONITOR_SW4A2_1", + "MONITOR_WW2END0_7", + "MONITOR_SW4END3_5", + "MONITOR_LH2_9", + "MONITOR_IMUX40_8", + "MONITOR_IMUX30_0", + "MONITOR_EL1BEG1_3", + "MONITOR_SW4A3_2", + "MONITOR_LOGIC_OUTS_B13_3", + "MONITOR_NE4C2_9", + "MONITOR_LOGIC_OUTS_B0_0", + "MONITOR_SW4A2_4", + "MONITOR_SW4END2_4", + "MONITOR_LH5_1", + "MONITOR_WW2END0_9", + "MONITOR_WW4C2_5", + "MONITOR_EE4A1_4", + "MONITOR_IMUX23_7", + "MONITOR_EE4C2_5", + "MONITOR_WW2A1_7", + "MONITOR_SE4BEG0_5", + "MONITOR_NE2A2_4", + "MONITOR_LOGIC_OUTS_B10_9", + "MONITOR_IMUX46_1", + "MONITOR_FAN5_8", + "MONITOR_NW4END3_9", + "MONITOR_ER1BEG0_4", + "MONITOR_IMUX25_5", + "MONITOR_LH4_9", + "MONITOR_IMUX29_6", + "MONITOR_IMUX1_9", + "MONITOR_LOGIC_OUTS_B10_4", + "MONITOR_IMUX13_9", + "MONITOR_WW4C3_5", + "MONITOR_ER1BEG1_3", + "MONITOR_IMUX40_2", + "MONITOR_LOGIC_OUTS_B8_2", + "MONITOR_WR1END2_9", + "MONITOR_LH12_8", + "MONITOR_IMUX36_8", + "MONITOR_IMUX41_2", + "MONITOR_IMUX21_3", + "MONITOR_EE4C0_4", + "MONITOR_FAN6_2", + "MONITOR_SW4A2_9", + "MONITOR_NW2A1_8", + "MONITOR_EL1BEG3_0", + "MONITOR_IMUX45_5", + "MONITOR_FAN0_9", + "MONITOR_LOGIC_OUTS_B18_8", + "MONITOR_SE4C0_5", + "MONITOR_LOGIC_OUTS_B0_2", + "MONITOR_LOGIC_OUTS_B7_7", + "MONITOR_SW2A0_3", + "MONITOR_SE4C1_7", + "MONITOR_EE4A3_8", + "MONITOR_CLK0_9", + "MONITOR_FAN7_3", + "MONITOR_NW4END1_2", + "MONITOR_WW2END1_2", + "MONITOR_WW4A2_0", + "MONITOR_SE4C2_7", + "MONITOR_WW4B0_4", + "MONITOR_NW4END3_0", + "MONITOR_LOGIC_OUTS_B16_9", + "MONITOR_IMUX31_8", + "MONITOR_LH8_0", + "MONITOR_FAN1_5", + "MONITOR_IMUX41_8", + "MONITOR_EL1BEG1_4", + "MONITOR_IMUX34_4", + "MONITOR_IMUX29_3", + "MONITOR_EE2BEG0_6", + "MONITOR_IMUX36_5", + "MONITOR_VERT_VAUXN8", + "MONITOR_LH6_6", + "MONITOR_IMUX7_5", + "MONITOR_EE4C2_0", + "MONITOR_EE4C1_6", + "MONITOR_NW4END1_5", + "MONITOR_WR1END2_5", + "MONITOR_IMUX30_3", + "MONITOR_IMUX4_4", + "MONITOR_NE4BEG1_3", + "MONITOR_BLOCK_OUTS_B2_7", + "MONITOR_LH3_2", + "MONITOR_SW4END0_0", + "MONITOR_LH10_1", + "MONITOR_IMUX29_9", + "MONITOR_EE4BEG3_0", + "MONITOR_IMUX28_1", + "MONITOR_WL1END1_7", + "MONITOR_SW2A2_9", + "MONITOR_LOGIC_OUTS_B10_2", + "MONITOR_WL1END1_0", + "MONITOR_SE4BEG2_1", + "MONITOR_NW4END2_7", + "MONITOR_SW4A3_9", + "MONITOR_SE4C0_1", + "MONITOR_EE4BEG0_0", + "MONITOR_BYP3_0", + "MONITOR_EE4B0_0", + "MONITOR_SW4END2_9", + "MONITOR_HORIZ_VAUXN9", + "MONITOR_EE2BEG0_2", + "MONITOR_BYP2_5", + "MONITOR_WW4A1_8", + "MONITOR_EE4C0_1", + "MONITOR_SW4END1_6", + "MONITOR_EE4BEG2_6", + "MONITOR_IMUX8_6", + "MONITOR_EE4BEG3_5", + "MONITOR_IMUX3_3", + "MONITOR_LH10_5", + "MONITOR_CTRL0_1", + "MONITOR_WR1END2_8", + "MONITOR_WR1END3_8", + "MONITOR_WW4END0_1", + "MONITOR_NE4C0_4", + "MONITOR_WW2END1_9", + "MONITOR_WW4END3_3", + "MONITOR_EE4A3_9", + "MONITOR_EE2A1_2", + "MONITOR_LH11_5", + "MONITOR_WW4C3_0", + "MONITOR_EE2BEG2_8", + "MONITOR_IMUX46_0", + "MONITOR_BLOCK_OUTS_B0_7", + "MONITOR_SW4END0_2", + "MONITOR_LOGIC_OUTS_B22_1", + "MONITOR_EL1BEG1_0", + "MONITOR_EL1BEG1_7", + "MONITOR_LOGIC_OUTS_B18_2", + "MONITOR_WW4B3_6", + "MONITOR_NW2A0_0", + "MONITOR_EE2BEG2_3", + "MONITOR_NE2A1_7", + "MONITOR_LOGIC_OUTS_B9_2", + "MONITOR_EE4A3_1", + "MONITOR_WR1END0_6", + "MONITOR_LOGIC_OUTS_B2_6", + "MONITOR_NW4END0_5", + "MONITOR_LOGIC_OUTS_B3_4", + "MONITOR_SE2A1_4", + "MONITOR_WW2END0_8", + "MONITOR_WW4B1_6", + "MONITOR_EE4C0_9", + "MONITOR_LOGIC_OUTS_B3_3", + "MONITOR_LOGIC_OUTS_B9_4", + "MONITOR_BYP4_6", + "MONITOR_WW2END0_4", + "MONITOR_WW4B3_5", + "MONITOR_NW4A1_2", + "MONITOR_FAN2_3", + "MONITOR_IMUX26_0", + "MONITOR_WW4C0_2", + "MONITOR_WR1END2_7", + "MONITOR_IMUX33_0", + "MONITOR_EE4C3_0", + "MONITOR_LOGIC_OUTS_B7_4", + "MONITOR_FAN3_5", + "MONITOR_SE4C1_3", + "MONITOR_EL1BEG1_5", + "MONITOR_WW2A2_8", + "MONITOR_SW2A2_1", + "MONITOR_IMUX7_2", + "MONITOR_ER1BEG2_0", + "MONITOR_IMUX18_9", + "MONITOR_EL1BEG1_8", + "MONITOR_LH6_3", + "MONITOR_LH9_0", + "MONITOR_IMUX22_2", + "MONITOR_IMUX13_6", + "MONITOR_WR1END0_0", + "MONITOR_SW2A3_8", + "MONITOR_IMUX8_4", + "MONITOR_NW2A1_3", + "MONITOR_WW4C0_3", + "MONITOR_SW4A1_9", + "MONITOR_WW4B0_1", + "MONITOR_IMUX15_6", + "MONITOR_WW2A2_6", + "MONITOR_LOGIC_OUTS_B20_1", + "MONITOR_FAN7_1", + "MONITOR_IMUX24_9", + "MONITOR_EL1BEG2_7", + "MONITOR_IMUX31_0", + "MONITOR_WL1END0_3", + "MONITOR_FAN4_8", + "MONITOR_NW4END0_3", + "MONITOR_NE4C3_6", + "MONITOR_LOGIC_OUTS_B21_0", + "MONITOR_LOGIC_OUTS_B1_4", + "MONITOR_SE4C0_4", + "MONITOR_CLK1_8", + "MONITOR_BLOCK_OUTS_B3_5", + "MONITOR_SE4BEG0_4", + "MONITOR_NW2A1_5", + "MONITOR_IMUX2_2", + "MONITOR_IMUX25_0", + "MONITOR_IMUX4_3", + "MONITOR_SW2A1_8", + "MONITOR_LH10_3", + "MONITOR_IMUX33_2", + "MONITOR_ER1BEG2_9", + "MONITOR_LOGIC_OUTS_B17_4", + "MONITOR_LOGIC_OUTS_B1_0", + "MONITOR_BYP5_4", + "MONITOR_LOGIC_OUTS_B7_9", + "MONITOR_LOGIC_OUTS_B12_2", + "MONITOR_SW4END1_8", + "MONITOR_IMUX32_5", + "MONITOR_IMUX38_6", + "MONITOR_NW4A3_8", + "MONITOR_WW2A3_4", + "MONITOR_LH12_2", + "MONITOR_LOGIC_OUTS_B22_5", + "MONITOR_EE2BEG1_1", + "MONITOR_WW4A2_6", + "MONITOR_SE4C3_2", + "MONITOR_SW4END1_1", + "MONITOR_FAN0_2", + "MONITOR_WW4B2_9", + "MONITOR_IMUX41_7", + "MONITOR_WW4B1_5", + "MONITOR_FAN0_8", + "MONITOR_VERT_VAUXN7", + "MONITOR_BLOCK_OUTS_B1_0", + "MONITOR_LOGIC_OUTS_B14_7", + "MONITOR_LH3_7", + "MONITOR_IMUX29_2", + "MONITOR_IMUX0_4", + "MONITOR_NE2A2_6", + "MONITOR_WW4C2_6", + "MONITOR_EL1BEG0_0", + "MONITOR_EE4B2_8", + "MONITOR_IMUX30_2", + "MONITOR_EL1BEG2_5", + "MONITOR_NW4A2_3", + "MONITOR_WW2A0_2", + "MONITOR_LOGIC_OUTS_B16_2", + "MONITOR_LH3_9", + "MONITOR_IMUX1_5", + "MONITOR_BYP1_2", + "MONITOR_LOGIC_OUTS_B23_5", + "MONITOR_LOGIC_OUTS_B4_5", + "MONITOR_NW2A0_3", + "MONITOR_ER1BEG3_5", + "MONITOR_LOGIC_OUTS_B15_0", + "MONITOR_SW4END3_0", + "MONITOR_IMUX47_1", + "MONITOR_IMUX40_4", + "MONITOR_IMUX26_6", + "MONITOR_NE4BEG1_6", + "MONITOR_LOGIC_OUTS_B13_7", + "MONITOR_LOGIC_OUTS_B15_6", + "MONITOR_WW2END1_7", + "MONITOR_FAN5_9", + "MONITOR_LOGIC_OUTS_B5_7", + "MONITOR_NE4BEG2_9", + "MONITOR_WL1END0_4", + "MONITOR_ER1BEG0_3", + "MONITOR_IMUX45_2", + "MONITOR_IMUX27_5", + "MONITOR_WL1END0_2", + "MONITOR_NW4A1_6", + "MONITOR_LOGIC_OUTS_B12_6", + "MONITOR_IMUX34_3", + "MONITOR_LH9_8", + "MONITOR_IMUX23_4", + "MONITOR_NE2A3_2", + "MONITOR_SE2A0_4", + "MONITOR_IMUX21_2", + "MONITOR_EE4C2_2", + "MONITOR_VERT_VAUXP9", + "MONITOR_IMUX5_5", + "MONITOR_NW2A0_6", + "MONITOR_CTRL1_5", + "MONITOR_SW2A1_1", + "MONITOR_WL1END0_7", + "MONITOR_ER1BEG1_7", + "MONITOR_IMUX13_3", + "MONITOR_BYP4_3", + "MONITOR_LOGIC_OUTS_B0_1", + "MONITOR_IMUX24_0", + "MONITOR_NE4C1_3", + "MONITOR_IMUX37_1", + "MONITOR_BYP2_9", + "MONITOR_WL1END2_9", + "MONITOR_EE4A3_4", + "MONITOR_IMUX11_2", + "MONITOR_EE4A0_1", + "MONITOR_NE4C2_3", + "MONITOR_NE4BEG2_3", + "MONITOR_LOGIC_OUTS_B7_3", + "MONITOR_EE4BEG2_1", + "MONITOR_SW4END3_8", + "MONITOR_WR1END3_2", + "MONITOR_EE4B2_6", + "MONITOR_CTRL0_7", + "MONITOR_LH12_7", + "MONITOR_NE4BEG2_0", + "MONITOR_IMUX3_9", + "MONITOR_WW4B0_9", + "MONITOR_WW4END3_9", + "MONITOR_LH7_0", + "MONITOR_SE4C3_1", + "MONITOR_VERT_VAUXP6", + "MONITOR_IMUX2_6", + "MONITOR_NW4A0_0", + "MONITOR_EE2A3_5", + "MONITOR_IMUX16_0", + "MONITOR_EE4B0_8", + "MONITOR_BYP4_4", + "MONITOR_NW4END3_1", + "MONITOR_EE2A0_7", + "MONITOR_CLK1_2", + "MONITOR_IMUX10_1", + "MONITOR_NW4A0_8", + "MONITOR_IMUX5_4", + "MONITOR_WW4C3_2", + "MONITOR_IMUX41_3", + "MONITOR_LH8_5", + "MONITOR_FAN6_3", + "MONITOR_IMUX12_3", + "MONITOR_SW4A1_7", + "MONITOR_EE4BEG3_6", + "MONITOR_IMUX4_7", + "MONITOR_IMUX4_2", + "MONITOR_SW4A1_5", + "MONITOR_EE4B3_9", + "MONITOR_IMUX6_3", + "MONITOR_WL1END2_5", + "MONITOR_EE4A2_6", + "MONITOR_IMUX17_0", + "MONITOR_IMUX32_9", + "MONITOR_WW2A2_9", + "MONITOR_LOGIC_OUTS_B16_5", + "MONITOR_SE4BEG1_2", + "MONITOR_LOGIC_OUTS_B23_0", + "MONITOR_IMUX32_4", + "MONITOR_LOGIC_OUTS_B10_8", + "MONITOR_NW4A1_0", + "MONITOR_WW4B0_5", + "MONITOR_NE4C3_2", + "MONITOR_IMUX20_3", + "MONITOR_LH11_4", + "MONITOR_EE4C2_9", + "MONITOR_LH11_1", + "MONITOR_SE2A3_3", + "MONITOR_EE4A3_6", + "MONITOR_LOGIC_OUTS_B21_8", + "MONITOR_SE4C2_1", + "MONITOR_NW4A2_5", + "MONITOR_NE4C1_4", + "MONITOR_LOGIC_OUTS_B11_3", + "MONITOR_FAN4_2", + "MONITOR_EE4A2_2", + "MONITOR_LOGIC_OUTS_B5_9", + "MONITOR_NE4C0_3", + "MONITOR_SW4END1_2", + "MONITOR_IMUX43_7", + "MONITOR_LOGIC_OUTS_B8_1", + "MONITOR_EE4C0_6", + "MONITOR_BYP4_9", + "MONITOR_IMUX37_0", + "MONITOR_FAN0_5", + "MONITOR_WW4END0_8", + "MONITOR_WW4B1_8", + "MONITOR_SE4C2_4", + "MONITOR_WR1END1_4", + "MONITOR_IMUX4_6", + "MONITOR_ER1BEG2_4", + "MONITOR_IMUX14_8", + "MONITOR_WW2END1_6", + "MONITOR_WW4A2_2", + "MONITOR_WW4B2_6", + "MONITOR_SW4A0_2", + "MONITOR_FAN7_7", + "MONITOR_IMUX46_2", + "MONITOR_IMUX16_2", + "MONITOR_IMUX25_6", + "MONITOR_IMUX0_0", + "MONITOR_IMUX43_0", + "MONITOR_EE4B0_6", + "MONITOR_IMUX38_4", + "MONITOR_LOGIC_OUTS_B9_8", + "MONITOR_LOGIC_OUTS_B20_0", + "MONITOR_IMUX31_9", + "MONITOR_FAN2_1", + "MONITOR_NE2A1_4", + "MONITOR_LH2_6", + "MONITOR_IMUX43_9", + "MONITOR_WL1END1_2", + "MONITOR_IMUX39_1", + "MONITOR_LOGIC_OUTS_B21_7", + "MONITOR_LH7_2", + "MONITOR_EE4C3_3", + "MONITOR_WW4A0_3", + "MONITOR_NE4BEG1_7", + "MONITOR_VERT_VAUXN2", + "MONITOR_LH11_9", + "MONITOR_WW2END3_9", + "MONITOR_CLK0_4", + "MONITOR_NW2A1_4", + "MONITOR_EL1BEG1_2", + "MONITOR_FAN1_6", + "MONITOR_EE4C1_5", + "MONITOR_BYP1_7", + "MONITOR_IMUX18_0", + "MONITOR_WW4A2_5", + "MONITOR_ER1BEG0_1", + "MONITOR_WW4C3_9", + "MONITOR_NW4END0_4", + "MONITOR_LH4_2", + "MONITOR_IMUX28_3", + "MONITOR_SE2A3_7", + "MONITOR_EL1BEG0_4", + "MONITOR_SW4END0_4", + "MONITOR_NE4C0_2", + "MONITOR_NE4C1_1", + "MONITOR_WW4END2_0", + "MONITOR_LH3_1", + "MONITOR_SE2A3_4", + "MONITOR_ER1BEG3_8", + "MONITOR_IMUX39_8", + "MONITOR_LOGIC_OUTS_B21_1", + "MONITOR_IMUX18_3", + "MONITOR_NW4A3_9", + "MONITOR_NE2A1_5", + "MONITOR_FAN0_4", + "MONITOR_LOGIC_OUTS_B6_5", + "MONITOR_BYP0_2", + "MONITOR_IMUX12_6", + "MONITOR_WR1END1_6", + "MONITOR_WR1END3_0", + "MONITOR_LH11_2", + "MONITOR_SE2A0_8", + "MONITOR_LOGIC_OUTS_B1_5", + "MONITOR_BYP6_7", + "MONITOR_LH4_1", + "MONITOR_LOGIC_OUTS_B11_8", + "MONITOR_EE2A0_1", + "MONITOR_SW4END2_1", + "MONITOR_IMUX10_0", + "MONITOR_EL1BEG0_3", + "MONITOR_LOGIC_OUTS_B4_1", + "MONITOR_LH5_7", + "MONITOR_NW4END2_9", + "MONITOR_SW4A0_4", + "MONITOR_VERT_VAUXN15", + "MONITOR_EE4B3_1", + "MONITOR_IMUX20_6", + "MONITOR_SE4C2_3", + "MONITOR_SE4C2_2", + "MONITOR_BYP1_9", + "MONITOR_LOGIC_OUTS_B0_5", + "MONITOR_IMUX12_7", + "MONITOR_WW4C0_9", + "MONITOR_EE4B2_9", + "MONITOR_EE2BEG2_2", + "MONITOR_WW4B2_1", + "MONITOR_BYP0_8", + "MONITOR_IMUX24_5", + "MONITOR_IMUX17_3", + "MONITOR_WW4C3_6", + "MONITOR_NE4C0_1", + "MONITOR_LOGIC_OUTS_B19_9", + "MONITOR_LH11_0", + "MONITOR_IMUX11_4", + "MONITOR_BLOCK_OUTS_B1_9", + "MONITOR_EE4C1_7", + "MONITOR_WW4C1_1", + "MONITOR_EE4C1_1", + "MONITOR_SE2A3_2", + "MONITOR_LH12_5", + "MONITOR_FAN7_0", + "MONITOR_WW4A1_9", + "MONITOR_IMUX44_2", + "MONITOR_IMUX42_8", + "MONITOR_NE4C3_3", + "MONITOR_WW4END0_4", + "MONITOR_EE2A3_8", + "MONITOR_WW4A3_4", + "MONITOR_IMUX9_5", + "MONITOR_EE4BEG1_5", + "MONITOR_LH3_0", + "MONITOR_FAN6_6", + "MONITOR_IMUX31_2", + "MONITOR_IMUX47_8", + "MONITOR_NW2A0_4", + "MONITOR_EE4C0_2", + "MONITOR_SW4A1_8", + "MONITOR_LH6_1", + "MONITOR_LH9_9", + "MONITOR_LOGIC_OUTS_B6_2", + "MONITOR_IMUX35_5", + "MONITOR_LOGIC_OUTS_B19_2", + "MONITOR_LOGIC_OUTS_B14_4", + "MONITOR_LOGIC_OUTS_B8_4", + "MONITOR_IMUX21_7", + "MONITOR_VERT_VAUXN12", + "MONITOR_WR1END1_3", + "MONITOR_BYP1_3", + "MONITOR_SE4C3_6", + "MONITOR_NE2A2_1", + "MONITOR_SW2A3_4", + "MONITOR_SW2A2_3", + "MONITOR_IMUX0_1", + "MONITOR_SE2A1_0", + "MONITOR_IMUX47_4", + "MONITOR_IMUX15_0", + "MONITOR_IMUX38_3", + "MONITOR_FAN3_1", + "MONITOR_IMUX14_4", + "MONITOR_ER1BEG0_8", + "MONITOR_BYP4_7", + "MONITOR_WW4A3_6", + "MONITOR_IMUX22_1", + "MONITOR_IMUX39_5", + "MONITOR_LOGIC_OUTS_B4_0", + "MONITOR_SW4END0_6", + "MONITOR_IMUX39_4", + "MONITOR_IMUX16_7", + "MONITOR_LOGIC_OUTS_B14_8", + "MONITOR_IMUX26_4", + "MONITOR_IMUX1_0", + "MONITOR_EL1BEG0_9", + "MONITOR_IMUX26_7", + "MONITOR_LOGIC_OUTS_B17_3", + "MONITOR_EE2A1_8", + "MONITOR_IMUX31_7", + "MONITOR_EE4C1_0", + "MONITOR_LOGIC_OUTS_B18_1", + "MONITOR_BYP7_0", + "MONITOR_IMUX42_2", + "MONITOR_BYP2_0", + "MONITOR_WW4A3_9", + "MONITOR_WW4B2_7", + "MONITOR_SW4A3_5", + "MONITOR_IMUX4_1", + "MONITOR_WW2A0_7", + "MONITOR_BYP0_9", + "MONITOR_IMUX45_9", + "MONITOR_IMUX29_5", + "MONITOR_BYP7_3", + "MONITOR_IMUX10_5", + "MONITOR_EE4BEG0_7", + "MONITOR_NW4END0_9", + "MONITOR_NE4C0_8", + "MONITOR_EE2A1_1", + "MONITOR_IMUX4_5", + "MONITOR_NW4A0_6", + "MONITOR_NE4C0_9", + "MONITOR_WW2A0_3", + "MONITOR_IMUX16_8", + "MONITOR_IMUX27_3", + "MONITOR_NW4A0_5", + "MONITOR_EE4BEG1_0", + "MONITOR_ER1BEG0_2", + "MONITOR_CLK0_0", + "MONITOR_SW4END1_9", + "MONITOR_BLOCK_OUTS_B2_9", + "MONITOR_WW2A0_5", + "MONITOR_IMUX14_6", + "MONITOR_IMUX32_2", + "MONITOR_EE4A0_4", + "MONITOR_IMUX39_2", + "MONITOR_WL1END1_6", + "MONITOR_EE4B2_4", + "MONITOR_WL1END1_1", + "MONITOR_LH7_8", + "MONITOR_SW4A2_6", + "MONITOR_WW4C2_2", + "MONITOR_LOGIC_OUTS_B14_1", + "MONITOR_LOGIC_OUTS_B16_6", + "MONITOR_LH7_1", + "MONITOR_WW4B0_8", + "MONITOR_IMUX12_8", + "MONITOR_EL1BEG2_4", + "MONITOR_IMUX10_7", + "MONITOR_SE2A1_8", + "MONITOR_BYP0_1", + "MONITOR_SW4A3_8", + "MONITOR_LH5_8", + "MONITOR_ER1BEG2_5", + "MONITOR_SW4A3_0", + "MONITOR_NE2A3_9", + "MONITOR_LH4_5", + "MONITOR_WL1END2_6", + "MONITOR_LOGIC_OUTS_B21_4", + "MONITOR_SW4A2_7", + "MONITOR_LH11_8", + "MONITOR_IMUX39_9", + "MONITOR_ER1BEG2_2", + "MONITOR_NW2A2_0", + "MONITOR_WW4B3_4", + "MONITOR_CTRL1_3", + "MONITOR_HORIZ_VAUXN2", + "MONITOR_LOGIC_OUTS_B3_1", + "MONITOR_IMUX35_1", + "MONITOR_SE4BEG2_9", + "MONITOR_CLK1_9", + "MONITOR_NE4C2_7", + "MONITOR_WW2END0_5", + "MONITOR_SW2A0_5", + "MONITOR_NW4END0_7", + "MONITOR_IMUX9_1", + "MONITOR_IMUX11_1", + "MONITOR_WW4B3_1", + "MONITOR_VERT_VAUXN6", + "MONITOR_SE2A2_6", + "MONITOR_LH2_2", + "MONITOR_BYP2_3", + "MONITOR_SE4C0_7", + "MONITOR_EE2A3_6", + "MONITOR_IMUX1_1", + "MONITOR_SW4A0_5", + "MONITOR_LOGIC_OUTS_B22_7", + "MONITOR_CTRL0_5", + "MONITOR_LOGIC_OUTS_B17_7", + "MONITOR_WW2END0_1", + "MONITOR_EE2BEG2_4", + "MONITOR_IMUX10_4", + "MONITOR_IMUX11_9", + "MONITOR_IMUX41_9", + "MONITOR_LH8_7", + "MONITOR_SW2A1_7", + "MONITOR_IMUX1_2", + "MONITOR_NE4C1_9", + "MONITOR_IMUX5_0", + "MONITOR_IMUX23_9", + "MONITOR_LH12_9", + "MONITOR_WW4C1_6", + "MONITOR_WL1END2_4", + "MONITOR_SW2A0_1", + "MONITOR_CTRL1_9", + "MONITOR_SE2A3_6", + "MONITOR_WW4B2_2", + "MONITOR_NW2A0_5", + "MONITOR_LOGIC_OUTS_B16_8", + "MONITOR_BLOCK_OUTS_B1_3", + "MONITOR_WR1END2_0", + "MONITOR_WL1END0_9", + "MONITOR_LH9_4", + "MONITOR_IMUX7_0", + "MONITOR_IMUX27_8", + "MONITOR_WR1END3_7", + "MONITOR_IMUX15_3", + "MONITOR_NW4END1_9", + "MONITOR_EE4A3_0", + "MONITOR_IMUX35_9", + "MONITOR_IMUX25_3", + "MONITOR_BYP1_4", + "MONITOR_WW2A3_5", + "MONITOR_EL1BEG0_6", + "MONITOR_LH3_4", + "MONITOR_FAN0_0", + "MONITOR_EE2BEG0_4", + "MONITOR_LH10_2", + "MONITOR_SE2A2_8", + "MONITOR_EE4A1_6", + "MONITOR_LOGIC_OUTS_B2_5", + "MONITOR_LH10_0", + "MONITOR_IMUX7_4", + "MONITOR_SW4END2_2", + "MONITOR_WW4A0_5", + "MONITOR_WL1END0_6", + "MONITOR_SE4C1_4", + "MONITOR_SE2A3_9", + "MONITOR_EE4B2_5", + "MONITOR_BLOCK_OUTS_B2_6", + "MONITOR_WR1END3_4", + "MONITOR_WR1END1_5", + "MONITOR_SE2A1_9", + "MONITOR_SW2A3_9", + "MONITOR_WL1END3_7", + "MONITOR_LOGIC_OUTS_B12_5", + "MONITOR_WW4END1_3", + "MONITOR_IMUX7_3", + "MONITOR_IMUX28_6", + "MONITOR_LOGIC_OUTS_B13_5", + "MONITOR_NW4A2_7", + "MONITOR_IMUX11_3", + "MONITOR_EL1BEG3_1", + "MONITOR_SW4A1_0", + "MONITOR_IMUX3_6", + "MONITOR_IMUX2_1", + "MONITOR_SW4END0_9", + "MONITOR_IMUX22_4", + "MONITOR_IMUX0_6", + "MONITOR_EE4A3_2", + "MONITOR_EE4A3_5", + "MONITOR_IMUX16_6", + "MONITOR_NE2A2_5", + "MONITOR_SW4A0_7", + "MONITOR_LOGIC_OUTS_B18_9", + "MONITOR_WW4C2_3", + "MONITOR_WW2A3_7", + "MONITOR_IMUX33_5", + "MONITOR_SE2A2_5", + "MONITOR_EE4BEG2_3", + "MONITOR_SE2A0_5", + "MONITOR_NE4C1_8", + "MONITOR_LOGIC_OUTS_B13_8", + "MONITOR_NW4END1_8", + "MONITOR_EL1BEG3_7", + "MONITOR_LOGIC_OUTS_B10_1", + "MONITOR_LOGIC_OUTS_B8_7", + "MONITOR_SW2A1_4", + "MONITOR_FAN3_7", + "MONITOR_EE4B1_8", + "MONITOR_SW4A2_5", + "MONITOR_IMUX18_6", + "MONITOR_NE4BEG1_9", + "MONITOR_NE2A3_4", + "MONITOR_WW4A0_1", + "MONITOR_WR1END0_2", + "MONITOR_IMUX20_1", + "MONITOR_LOGIC_OUTS_B14_9", + "MONITOR_EE4A0_2", + "MONITOR_CTRL0_2", + "MONITOR_EE4C2_1", + "MONITOR_IMUX35_6", + "MONITOR_IMUX6_8", + "MONITOR_IMUX10_9", + "MONITOR_EE4BEG0_9", + "MONITOR_IMUX6_7", + "MONITOR_VERT_VAUXN1", + "MONITOR_IMUX43_3", + "MONITOR_LOGIC_OUTS_B6_1", + "MONITOR_WW4C2_4", + "MONITOR_NE4C3_8", + "MONITOR_NE2A3_5", + "MONITOR_WW4B3_2", + "MONITOR_SW4A2_0", + "MONITOR_NW4A2_4", + "MONITOR_WW4B2_4", + "MONITOR_SE4BEG1_1", + "MONITOR_IMUX19_2", + "MONITOR_VERT_VAUXP14", + "MONITOR_LH1_5", + "MONITOR_IMUX8_3", + "MONITOR_LOGIC_OUTS_B9_7", + "MONITOR_SW4A2_3", + "MONITOR_BLOCK_OUTS_B0_5", + "MONITOR_IMUX44_8", + "MONITOR_IMUX22_5", + "MONITOR_LH9_7", + "MONITOR_SW2A0_9", + "MONITOR_LOGIC_OUTS_B12_8", + "MONITOR_LOGIC_OUTS_B18_4", + "MONITOR_LOGIC_OUTS_B13_0", + "MONITOR_IMUX40_5", + "MONITOR_WW4A1_3", + "MONITOR_IMUX35_8", + "MONITOR_IMUX19_6", + "MONITOR_CTRL0_6", + "MONITOR_FAN0_6", + "MONITOR_IMUX37_6", + "MONITOR_IMUX23_5", + "MONITOR_EE4BEG2_4", + "MONITOR_IMUX20_0", + "MONITOR_WL1END0_8", + "MONITOR_LOGIC_OUTS_B4_6", + "MONITOR_WW2END3_6", + "MONITOR_IMUX21_0", + "MONITOR_WW4B3_0", + "MONITOR_IMUX19_4", + "MONITOR_IMUX15_4", + "MONITOR_FAN7_2", + "MONITOR_EE2BEG3_5", + "MONITOR_SE2A0_0", + "MONITOR_WR1END3_3", + "MONITOR_WL1END3_2", + "MONITOR_WL1END2_7", + "MONITOR_IMUX44_1", + "MONITOR_IMUX21_9", + "MONITOR_BYP0_3", + "MONITOR_WW4B2_3", + "MONITOR_LH4_8", + "MONITOR_EE4BEG2_7", + "MONITOR_IMUX8_5", + "MONITOR_EE4BEG1_6", + "MONITOR_EE4BEG2_9", + "MONITOR_LOGIC_OUTS_B17_6", + "MONITOR_IMUX38_0", + "MONITOR_NW4A1_5", + "MONITOR_EE2A2_1", + "MONITOR_FAN5_4", + "MONITOR_LOGIC_OUTS_B20_4", + "MONITOR_EL1BEG3_9", + "MONITOR_LOGIC_OUTS_B16_7", + "MONITOR_BYP4_1", + "MONITOR_WR1END3_6", + "MONITOR_NW4END0_8", + "MONITOR_WW4END3_6", + "MONITOR_LOGIC_OUTS_B7_6", + "MONITOR_LOGIC_OUTS_B19_4", + "MONITOR_EE2BEG0_3", + "MONITOR_BLOCK_OUTS_B0_3", + "MONITOR_EE2A1_5", + "MONITOR_IMUX14_5", + "MONITOR_LOGIC_OUTS_B2_1", + "MONITOR_WW4A2_9", + "MONITOR_BYP4_2", + "MONITOR_EE4A0_7", + "MONITOR_WW4C1_9", + "MONITOR_LH5_6", + "MONITOR_WR1END1_8", + "MONITOR_EE4B0_2", + "MONITOR_EE4BEG0_2", + "MONITOR_EE4A0_3", + "MONITOR_CTRL0_0", + "MONITOR_CLK1_0", + "MONITOR_IMUX17_4", + "MONITOR_EE4BEG3_2", + "MONITOR_IMUX44_9", + "MONITOR_EE4B1_3", + "MONITOR_EE4BEG2_5", + "MONITOR_SW2A2_4", + "MONITOR_WW2A3_3", + "MONITOR_FAN6_0", + "MONITOR_NW4END3_3", + "MONITOR_IMUX40_3", + "MONITOR_FAN2_0", + "MONITOR_LOGIC_OUTS_B22_9", + "MONITOR_WW4C3_3", + "MONITOR_WW2A0_6", + "MONITOR_WR1END0_8", + "MONITOR_NW4A2_6", + "MONITOR_IMUX38_1", + "MONITOR_WR1END0_1", + "MONITOR_NE4C1_5", + "MONITOR_LOGIC_OUTS_B16_3", + "MONITOR_NW2A1_0", + "MONITOR_IMUX47_7", + "MONITOR_LOGIC_OUTS_B11_7", + "MONITOR_EE4B0_7", + "MONITOR_WW2A1_3", + "MONITOR_WW2END2_5", + "MONITOR_IMUX11_5", + "MONITOR_EE4BEG1_4", + "MONITOR_SW4END0_5", + "MONITOR_IMUX30_1", + "MONITOR_IMUX17_7", + "MONITOR_SE4C0_9", + "MONITOR_EE4C2_8", + "MONITOR_IMUX46_5", + "MONITOR_WW4END2_4", + "MONITOR_LH9_5", + "MONITOR_EE2BEG0_0", + "MONITOR_WW2END3_5", + "MONITOR_WR1END0_3", + "MONITOR_BLOCK_OUTS_B1_1", + "MONITOR_IMUX19_7", + "MONITOR_FAN1_7", + "MONITOR_IMUX5_8", + "MONITOR_EE4C1_3", + "MONITOR_BLOCK_OUTS_B3_4", + "MONITOR_FAN4_5", + "MONITOR_WR1END2_1", + "MONITOR_LOGIC_OUTS_B22_2", + "MONITOR_IMUX28_7", + "MONITOR_NW4A3_0", + "MONITOR_ER1BEG1_6", + "MONITOR_WR1END3_9", + "MONITOR_WW4C0_4", + "MONITOR_ER1BEG0_9", + "MONITOR_FAN3_3", + "MONITOR_WW2A1_1", + "MONITOR_LOGIC_OUTS_B19_0", + "MONITOR_EE4C2_3", + "MONITOR_WW4B0_3", + "MONITOR_SE4BEG3_1", + "MONITOR_WR1END2_4", + "MONITOR_NE2A2_9", + "MONITOR_WL1END1_4", + "MONITOR_FAN3_6", + "MONITOR_WW4END0_9", + "MONITOR_FAN2_5", + "MONITOR_IMUX46_4", + "MONITOR_IMUX41_5", + "MONITOR_NW4A2_1", + "MONITOR_BYP5_2", + "MONITOR_NW4END3_4", + "MONITOR_IMUX26_8", + "MONITOR_LOGIC_OUTS_B6_8", + "MONITOR_SW2A3_0", + "MONITOR_LOGIC_OUTS_B17_5", + "MONITOR_SE4BEG2_0", + "MONITOR_WW4A3_1", + "MONITOR_BLOCK_OUTS_B1_4", + "MONITOR_EE2BEG3_6", + "MONITOR_WR1END1_1", + "MONITOR_IMUX42_1", + "MONITOR_SW2A0_8", + "MONITOR_NW4END1_0", + "MONITOR_BYP6_6", + "MONITOR_IMUX26_2", + "MONITOR_NE4BEG2_5", + "MONITOR_LOGIC_OUTS_B4_7", + "MONITOR_VERT_VAUXN3", + "MONITOR_NW2A3_0", + "MONITOR_LOGIC_OUTS_B5_3", + "MONITOR_BYP3_8", + "MONITOR_NE4BEG0_2", + "MONITOR_NE4C0_5", + "MONITOR_LOGIC_OUTS_B3_8", + "MONITOR_WW4END0_7", + "MONITOR_SE2A0_3", + "MONITOR_SW4END2_0", + "MONITOR_FAN7_9", + "MONITOR_WW4END2_8", + "MONITOR_SE2A2_7", + "MONITOR_NE2A3_3", + "MONITOR_WW2END0_3", + "MONITOR_EE4B3_3", + "MONITOR_LOGIC_OUTS_B23_6", + "MONITOR_SE2A2_4", + "MONITOR_IMUX29_4", + "MONITOR_VERT_VAUXP4", + "MONITOR_WW2A3_2", + "MONITOR_IMUX7_7", + "MONITOR_CLK0_5", + "MONITOR_LH9_6", + "MONITOR_WW2END1_8", + "MONITOR_NE2A0_4", + "MONITOR_WW2A1_5", + "MONITOR_NW4END0_2", + "MONITOR_LOGIC_OUTS_B4_9", + "MONITOR_LOGIC_OUTS_B14_0", + "MONITOR_LH6_0", + "MONITOR_WW4END2_5", + "MONITOR_FAN3_8", + "MONITOR_CLK1_3", + "MONITOR_IMUX19_3", + "MONITOR_LOGIC_OUTS_B15_4", + "MONITOR_EE4B1_1", + "MONITOR_IMUX30_6", + "MONITOR_LH2_1", + "MONITOR_IMUX7_6", + "MONITOR_EE2A2_4", + "MONITOR_EL1BEG2_0", + "MONITOR_EE4A1_8", + "MONITOR_IMUX14_9", + "MONITOR_WW2A3_0", + "MONITOR_SW4END2_8", + "MONITOR_EE2A3_3", + "MONITOR_ER1BEG3_6", + "MONITOR_EE4BEG0_4", + "MONITOR_WW2END1_4", + "MONITOR_IMUX0_9", + "MONITOR_EE4A0_0", + "MONITOR_LH1_8", + "MONITOR_WL1END3_0", + "MONITOR_SW4A3_4", + "MONITOR_SW2A3_6", + "MONITOR_IMUX25_4", + "MONITOR_LH11_7", + "MONITOR_WW4END2_9", + "MONITOR_NE2A0_6", + "MONITOR_LOGIC_OUTS_B22_4", + "MONITOR_EE4A1_9", + "MONITOR_HORIZ_VAUXP10", + "MONITOR_LOGIC_OUTS_B0_9", + "MONITOR_EE4BEG1_7", + "MONITOR_LOGIC_OUTS_B17_8", + "MONITOR_SE4C1_2", + "MONITOR_NE4BEG2_6", + "MONITOR_IMUX8_2", + "MONITOR_SE4BEG3_6", + "MONITOR_IMUX15_7", + "MONITOR_EL1BEG2_9", + "MONITOR_EE4C1_9", + "MONITOR_BYP2_1", + "MONITOR_LOGIC_OUTS_B6_0", + "MONITOR_IMUX12_2", + "MONITOR_EE2BEG3_0", + "MONITOR_WW4END3_0", + "MONITOR_SE4C3_0", + "MONITOR_LOGIC_OUTS_B21_9", + "MONITOR_IMUX9_4", + "MONITOR_FAN1_0", + "MONITOR_WW2A2_0", + "MONITOR_LOGIC_OUTS_B10_0", + "MONITOR_IMUX36_1", + "MONITOR_CLK1_7", + "MONITOR_WW2END3_3", + "MONITOR_EL1BEG3_4", + "MONITOR_EE2A1_4", + "MONITOR_IMUX15_5", + "MONITOR_IMUX14_7", + "MONITOR_SE2A3_0", + "MONITOR_IMUX20_9", + "MONITOR_EE4A2_4", + "MONITOR_SE4C0_2", + "MONITOR_IMUX9_2", + "MONITOR_NW4A1_3", + "MONITOR_NW4END3_5", + "MONITOR_WW4A3_7", + "MONITOR_SW2A1_2", + "MONITOR_LH2_8", + "MONITOR_WW4A2_3", + "MONITOR_IMUX2_0", + "MONITOR_WW2END1_3", + "MONITOR_EE4C3_5", + "MONITOR_SW4END0_7", + "MONITOR_WW2A0_9", + "MONITOR_WW4C1_5", + "MONITOR_WW4A3_3", + "MONITOR_WW4B3_9", + "MONITOR_SE2A3_5", + "MONITOR_FAN5_3", + "MONITOR_WW4END3_8", + "MONITOR_LOGIC_OUTS_B4_8", + "MONITOR_WW2END3_4", + "MONITOR_BYP3_9", + "MONITOR_SE4C3_3", + "MONITOR_WW4B2_5", + "MONITOR_SE4BEG1_7", + "MONITOR_IMUX27_6", + "MONITOR_NE4C3_4", + "MONITOR_ER1BEG2_1", + "MONITOR_NW2A1_9", + "MONITOR_BYP3_1", + "MONITOR_IMUX20_8", + "MONITOR_LOGIC_OUTS_B20_7", + "MONITOR_ER1BEG0_0", + "MONITOR_IMUX15_9", + "MONITOR_WW2END3_8", + "MONITOR_LOGIC_OUTS_B11_2", + "MONITOR_SW2A1_5", + "MONITOR_EL1BEG0_1", + "MONITOR_LOGIC_OUTS_B12_4", + "MONITOR_WW4A0_2", + "MONITOR_SW4END3_2", + "MONITOR_FAN2_6", + "MONITOR_BLOCK_OUTS_B0_4", + "MONITOR_LOGIC_OUTS_B23_3", + "MONITOR_FAN6_7", + "MONITOR_NW2A2_4", + "MONITOR_LOGIC_OUTS_B3_0", + "MONITOR_EE2BEG3_9", + "MONITOR_LOGIC_OUTS_B11_0", + "MONITOR_WW4END1_1", + "MONITOR_NE2A0_9", + "MONITOR_VERT_VAUXP7", + "MONITOR_IMUX24_7", + "MONITOR_IMUX39_7", + "MONITOR_NW4A0_9", + "MONITOR_LOGIC_OUTS_B5_4", + "MONITOR_BYP6_3", + "MONITOR_LH11_6", + "MONITOR_NW2A3_8", + "MONITOR_NE4C1_0", + "MONITOR_WW4C0_8", + "MONITOR_SW4A1_4", + "MONITOR_EL1BEG1_9", + "MONITOR_SW4A3_1", + "MONITOR_EE2BEG3_7", + "MONITOR_ER1BEG3_3", + "MONITOR_WW4C1_0", + "MONITOR_LH12_6", + "MONITOR_IMUX8_8", + "MONITOR_IMUX34_1", + "MONITOR_NW2A2_3", + "MONITOR_IMUX43_1", + "MONITOR_IMUX2_4", + "MONITOR_NW2A1_6", + "MONITOR_EE4C3_9", + "MONITOR_LOGIC_OUTS_B1_3", + "MONITOR_EE4A0_9", + "MONITOR_FAN2_8", + "MONITOR_IMUX12_5", + "MONITOR_BLOCK_OUTS_B3_9", + "MONITOR_LH4_3", + "MONITOR_SE4BEG2_5", + "MONITOR_LH8_9", + "MONITOR_WW2END2_8", + "MONITOR_LH3_8", + "MONITOR_LH8_8", + "MONITOR_LOGIC_OUTS_B19_3", + "MONITOR_LOGIC_OUTS_B15_5", + "MONITOR_LOGIC_OUTS_B7_5", + "MONITOR_FAN2_4", + "MONITOR_IMUX26_5", + "MONITOR_FAN0_1", + "MONITOR_WL1END1_9", + "MONITOR_IMUX32_8", + "MONITOR_WW2END2_0", + "MONITOR_LH3_6", + "MONITOR_LOGIC_OUTS_B0_8", + "MONITOR_IMUX3_5", + "MONITOR_WW4END3_1", + "MONITOR_EE2BEG1_8", + "MONITOR_NW4A0_2", + "MONITOR_IMUX17_1", + "MONITOR_LH2_3", + "MONITOR_SW2A2_6", + "MONITOR_IMUX30_4", + "MONITOR_WW4END2_7", + "MONITOR_EE4A2_5", + "MONITOR_NW4END1_3", + "MONITOR_LOGIC_OUTS_B11_6", + "MONITOR_WW2A2_5", + "MONITOR_IMUX47_9", + "MONITOR_WW4C0_0", + "MONITOR_WW2END2_6", + "MONITOR_NE4BEG3_1", + "MONITOR_NW2A0_2", + "MONITOR_LOGIC_OUTS_B12_0", + "MONITOR_IMUX6_6", + "MONITOR_EE2BEG1_9", + "MONITOR_FAN5_2", + "MONITOR_BLOCK_OUTS_B0_0", + "MONITOR_WW4END3_4", + "MONITOR_LOGIC_OUTS_B22_6", + "MONITOR_WW4A2_8", + "MONITOR_EL1BEG1_1", + "MONITOR_LH10_8", + "MONITOR_IMUX5_3", + "MONITOR_IMUX25_1", + "MONITOR_FAN4_4", + "MONITOR_EE4A1_2", + "MONITOR_SW4END2_7", + "MONITOR_BLOCK_OUTS_B1_5", + "MONITOR_SW2A0_2", + "MONITOR_NW4A3_7", + "MONITOR_IMUX16_5", + "MONITOR_FAN6_8", + "MONITOR_IMUX2_8", + "MONITOR_WW4END1_8", + "MONITOR_NE4BEG0_9", + "MONITOR_IMUX0_7", + "MONITOR_IMUX22_6", + "MONITOR_EE4BEG0_5", + "MONITOR_NE4BEG3_7", + "MONITOR_IMUX6_1", + "MONITOR_LOGIC_OUTS_B0_6", + "MONITOR_IMUX37_8", + "MONITOR_NW4A1_9", + "MONITOR_LOGIC_OUTS_B17_0", + "MONITOR_WW2END2_9", + "MONITOR_WW4END1_0", + "MONITOR_NW2A2_6", + "MONITOR_SW2A1_9", + "MONITOR_IMUX31_3", + "MONITOR_IMUX30_8", + "MONITOR_LH10_6", + "MONITOR_BLOCK_OUTS_B0_8", + "MONITOR_IMUX9_7", + "MONITOR_NE2A3_7", + "MONITOR_LOGIC_OUTS_B23_9", + "MONITOR_IMUX28_5", + "MONITOR_BLOCK_OUTS_B3_0", + "MONITOR_BYP6_5", + "MONITOR_LOGIC_OUTS_B0_4", + "MONITOR_VERT_VAUXN13", + "MONITOR_BLOCK_OUTS_B1_6", + "MONITOR_SE4C1_1", + "MONITOR_FAN2_7", + "MONITOR_FAN3_2", + "MONITOR_IMUX36_6", + "MONITOR_VERT_VAUXN14", + "MONITOR_WW4END1_6", + "MONITOR_NW4A3_6", + "MONITOR_WW4END0_3", + "MONITOR_IMUX7_8", + "MONITOR_EL1BEG2_3", + "MONITOR_BYP6_4", + "MONITOR_LOGIC_OUTS_B9_3", + "MONITOR_IMUX42_6", + "MONITOR_WR1END0_7", + "MONITOR_LH5_9", + "MONITOR_SW2A2_7", + "MONITOR_HORIZ_VAUXP1", + "MONITOR_LOGIC_OUTS_B11_5", + "MONITOR_BLOCK_OUTS_B0_2", + "MONITOR_LOGIC_OUTS_B9_5", + "MONITOR_FAN4_7", + "MONITOR_CLK0_1", + "MONITOR_IMUX31_6", + "MONITOR_NE4BEG1_4", + "MONITOR_IMUX44_7", + "MONITOR_WL1END2_1", + "MONITOR_IMUX21_4", + "MONITOR_WR1END2_6", + "MONITOR_IMUX23_3", + "MONITOR_EE4C1_4", + "MONITOR_EE4C0_0", + "MONITOR_LH2_0", + "MONITOR_NE4C3_9", + "MONITOR_SW2A3_2", + "MONITOR_LH4_6", + "MONITOR_NW4A3_3", + "MONITOR_IMUX27_4", + "MONITOR_IMUX37_4", + "MONITOR_LOGIC_OUTS_B13_9", + "MONITOR_IMUX44_3", + "MONITOR_EE2A0_6", + "MONITOR_IMUX33_7", + "MONITOR_SW4A1_2", + "MONITOR_NW4END2_4", + "MONITOR_WW2A2_1", + "MONITOR_IMUX47_5", + "MONITOR_CTRL1_4", + "MONITOR_SW4END3_3", + "MONITOR_LOGIC_OUTS_B5_8", + "MONITOR_LH6_8", + "MONITOR_SW2A3_3", + "MONITOR_BLOCK_OUTS_B2_4", + "MONITOR_LOGIC_OUTS_B17_2", + "MONITOR_NW4A2_2", + "MONITOR_WW4A0_8", + "MONITOR_WW2A2_3", + "MONITOR_SE2A2_0", + "MONITOR_IMUX16_1", + "MONITOR_WL1END2_0", + "MONITOR_SW4A3_6", + "MONITOR_IMUX3_0", + "MONITOR_WR1END0_4", + "MONITOR_NE4BEG0_4", + "MONITOR_BYP0_4", + "MONITOR_NE2A2_2", + "MONITOR_LH1_0", + "MONITOR_IMUX27_0", + "MONITOR_WW4C1_4", + "MONITOR_LOGIC_OUTS_B13_2", + "MONITOR_SE2A0_7", + "MONITOR_IMUX39_6", + "MONITOR_BYP2_7", + "MONITOR_IMUX18_1", + "MONITOR_IMUX28_2", + "MONITOR_IMUX9_3", + "MONITOR_SE2A3_8", + "MONITOR_SE4BEG3_3", + "MONITOR_LOGIC_OUTS_B5_0", + "MONITOR_IMUX23_0", + "MONITOR_NE4C1_2", + "MONITOR_LOGIC_OUTS_B22_0", + "MONITOR_WW4C2_0", + "MONITOR_NE2A1_2", + "MONITOR_WW4B0_2", + "MONITOR_SE4BEG0_8", + "MONITOR_IMUX21_6", + "MONITOR_IMUX28_0", + "MONITOR_EE4BEG1_3", + "MONITOR_EE2A0_9", + "MONITOR_LOGIC_OUTS_B16_0", + "MONITOR_EE2BEG3_2", + "MONITOR_FAN3_9", + "MONITOR_LOGIC_OUTS_B6_6", + "MONITOR_LH4_7", + "MONITOR_WW2A1_6", + "MONITOR_NE4BEG0_0", + "MONITOR_LOGIC_OUTS_B1_6", + "MONITOR_SE2A1_7", + "MONITOR_IMUX2_5", + "MONITOR_LOGIC_OUTS_B2_2", + "MONITOR_LOGIC_OUTS_B2_3", + "MONITOR_NE2A3_0", + "MONITOR_EE4A2_9", + "MONITOR_VERT_VAUXP3", + "MONITOR_SE4C1_5", + "MONITOR_SW4A3_7", + "MONITOR_WW2A0_0", + "MONITOR_NW2A3_9", + "MONITOR_FAN4_9", + "MONITOR_WW4C0_6", + "MONITOR_EE2A0_0", + "MONITOR_IMUX40_6", + "MONITOR_BYP4_5", + "MONITOR_WW4END3_7", + "MONITOR_IMUX0_5", + "MONITOR_ER1BEG0_5", + "MONITOR_WW2END0_6", + "MONITOR_IMUX31_4", + "MONITOR_NW2A1_7", + "MONITOR_SW4END2_6", + "MONITOR_WW4B2_8", + "MONITOR_SW4END2_3", + "MONITOR_CLK1_1", + "MONITOR_LH9_2", + "MONITOR_NE4C0_7", + "MONITOR_VERT_VAUXP1", + "MONITOR_LOGIC_OUTS_B10_7", + "MONITOR_IMUX33_4", + "MONITOR_WW2A3_9", + "MONITOR_BYP3_7", + "MONITOR_IMUX6_9", + "MONITOR_BYP3_2", + "MONITOR_IMUX2_3", + "MONITOR_WW4C3_8", + "MONITOR_IMUX18_2", + "MONITOR_NE4BEG3_8", + "MONITOR_IMUX35_2", + "MONITOR_SE4C3_4", + "MONITOR_SW2A3_5", + "MONITOR_LOGIC_OUTS_B22_3", + "MONITOR_EE4BEG1_1", + "MONITOR_WW4B1_4", + "MONITOR_LOGIC_OUTS_B13_6", + "MONITOR_LOGIC_OUTS_B3_5", + "MONITOR_EE4C0_8", + "MONITOR_LOGIC_OUTS_B14_2", + "MONITOR_NE2A1_0", + "MONITOR_LOGIC_OUTS_B15_2", + "MONITOR_LOGIC_OUTS_B6_4", + "MONITOR_LH2_7", + "MONITOR_EE4C0_7", + "MONITOR_NE2A1_1", + "MONITOR_LOGIC_OUTS_B19_1", + "MONITOR_SW4A2_2", + "MONITOR_IMUX1_3", + "MONITOR_WW4C1_7", + "MONITOR_SW2A1_0", + "MONITOR_BYP5_6", + "MONITOR_EE2A1_3", + "MONITOR_SE4BEG1_4", + "MONITOR_IMUX26_9", + "MONITOR_ER1BEG1_9", + "MONITOR_BYP6_1", + "MONITOR_EL1BEG0_5", + "MONITOR_IMUX10_3", + "MONITOR_LOGIC_OUTS_B18_5", + "MONITOR_SE4BEG2_7", + "MONITOR_ER1BEG3_7", + "MONITOR_EE2A0_5", + "MONITOR_WW4C3_1", + "MONITOR_LOGIC_OUTS_B9_1", + "MONITOR_EE4B2_7", + "MONITOR_EE4A2_1", + "MONITOR_IMUX5_1", + "MONITOR_LOGIC_OUTS_B8_6", + "MONITOR_WW4END3_2", + "MONITOR_BYP0_0", + "MONITOR_NE4BEG2_7", + "MONITOR_EE4A1_5", + "MONITOR_WL1END2_3", + "MONITOR_IMUX27_7", + "MONITOR_SW2A2_2", + "MONITOR_NW4END0_6", + "MONITOR_LOGIC_OUTS_B5_1", + "MONITOR_NW4A1_1", + "MONITOR_SE4C1_0", + "MONITOR_IMUX23_6", + "MONITOR_IMUX43_6", + "MONITOR_IMUX45_1", + "MONITOR_EE2BEG1_3", + "MONITOR_NE2A3_8", + "MONITOR_LOGIC_OUTS_B8_9", + "MONITOR_WL1END3_1", + "MONITOR_EE2BEG2_1", + "MONITOR_EE2BEG3_8", + "MONITOR_LOGIC_OUTS_B12_9", + "MONITOR_LH10_9", + "MONITOR_EE4B1_0", + "MONITOR_IMUX24_8", + "MONITOR_IMUX24_4", + "MONITOR_NW4END3_8", + "MONITOR_LH11_3", + "MONITOR_LOGIC_OUTS_B21_6", + "MONITOR_LOGIC_OUTS_B21_5", + "MONITOR_IMUX35_7", + "MONITOR_WW2A2_4", + "MONITOR_IMUX19_5", + "MONITOR_SE4BEG3_7", + "MONITOR_IMUX42_7", + "MONITOR_WR1END2_3", + "MONITOR_WR1END0_9", + "MONITOR_FAN1_1", + "MONITOR_LOGIC_OUTS_B1_7", + "MONITOR_EE4A0_5", + "MONITOR_CLK1_6", + "MONITOR_NE4BEG1_0", + "MONITOR_IMUX6_2", + "MONITOR_IMUX41_1", + "MONITOR_IMUX13_5", + "MONITOR_EE2A0_8", + "MONITOR_EE2A3_2", + "MONITOR_NW4END1_7", + "MONITOR_IMUX10_8", + "MONITOR_SE2A3_1", + "MONITOR_EE2A0_2", + "MONITOR_SE4C0_6", + "MONITOR_NW2A2_5", + "MONITOR_WW2A3_8", + "MONITOR_IMUX6_5", + "MONITOR_IMUX31_1", + "MONITOR_SE2A2_1", + "MONITOR_IMUX19_8", + "MONITOR_LH12_3", + "MONITOR_SE4BEG0_2", + "MONITOR_WR1END1_7", + "MONITOR_WW2A2_7", + "MONITOR_WW2END2_1", + "MONITOR_FAN0_7", + "MONITOR_SW2A1_6", + "MONITOR_NE2A0_8", + "MONITOR_BLOCK_OUTS_B2_1", + "MONITOR_IMUX32_1", + "MONITOR_NE4BEG2_4", + "MONITOR_BLOCK_OUTS_B3_1", + "MONITOR_NW4A1_7", + "MONITOR_LOGIC_OUTS_B3_7", + "MONITOR_LOGIC_OUTS_B4_4", + "MONITOR_BYP0_6", + "MONITOR_SE4BEG0_3", + "MONITOR_WL1END3_3", + "MONITOR_NW4END0_1", + "MONITOR_EE4BEG2_0", + "MONITOR_IMUX9_0", + "MONITOR_IMUX1_7", + "MONITOR_NW2A3_3", + "MONITOR_EE4B2_0", + "MONITOR_SE2A1_3", + "MONITOR_SE4BEG2_2", + "MONITOR_LH9_1", + "MONITOR_NE2A1_3", + "MONITOR_ER1BEG3_0", + "MONITOR_ER1BEG1_0", + "MONITOR_IMUX1_6", + "MONITOR_SE2A0_1", + "MONITOR_IMUX39_0", + "MONITOR_IMUX0_2", + "MONITOR_BLOCK_OUTS_B3_2", + "MONITOR_FAN2_9", + "MONITOR_EE4B1_7", + "MONITOR_WW4A1_7", + "MONITOR_IMUX22_0", + "MONITOR_LOGIC_OUTS_B20_5", + "MONITOR_VERT_VAUXP2", + "MONITOR_NW4END2_2", + "MONITOR_SW2A1_3", + "MONITOR_IMUX1_8", + "MONITOR_BYP3_6", + "MONITOR_WW4END1_5", + "MONITOR_EE4B3_2", + "MONITOR_IMUX20_2", + "MONITOR_NW4END2_5", + "MONITOR_LOGIC_OUTS_B0_3", + "MONITOR_IMUX29_1", + "MONITOR_WR1END3_1", + "MONITOR_IMUX13_0", + "MONITOR_LOGIC_OUTS_B7_1", + "MONITOR_IMUX12_1", + "MONITOR_IMUX23_1", + "MONITOR_IMUX32_0", + "MONITOR_SE2A0_2", + "MONITOR_NE2A1_6", + "MONITOR_IMUX43_2", + "MONITOR_NW2A0_1", + "MONITOR_WW2END1_1", + "MONITOR_SE4BEG2_8", + "MONITOR_EE2BEG1_7", + "MONITOR_LOGIC_OUTS_B12_7", + "MONITOR_ER1BEG3_2", + "MONITOR_WW2END3_2", + "MONITOR_LH1_6", + "MONITOR_LOGIC_OUTS_B18_3", + "MONITOR_IMUX39_3", + "MONITOR_EE2A2_0", + "MONITOR_IMUX1_4", + "MONITOR_LOGIC_OUTS_B17_9", + "MONITOR_LOGIC_OUTS_B23_1", + "MONITOR_IMUX27_9", + "MONITOR_EE4B2_3", + "MONITOR_NE4BEG0_1", + "MONITOR_IMUX15_1", + "MONITOR_NW4END2_6", + "MONITOR_IMUX32_7", + "MONITOR_BYP5_8", + "MONITOR_FAN5_5", + "MONITOR_EE2BEG3_1", + "MONITOR_LOGIC_OUTS_B15_1", + "MONITOR_LOGIC_OUTS_B1_8", + "MONITOR_SE4C3_7", + "MONITOR_BYP6_8", + "MONITOR_CLK0_7", + "MONITOR_EE4BEG0_8", + "MONITOR_WW4A3_8", + "MONITOR_BYP1_5", + "MONITOR_LOGIC_OUTS_B19_7", + "MONITOR_WW4END0_6", + "MONITOR_NE4BEG0_7", + "MONITOR_EE4C3_7", + "MONITOR_EE2A2_3", + "MONITOR_NE2A3_6", + "MONITOR_IMUX15_8", + "MONITOR_WW2A3_1", + "MONITOR_SW4END3_7", + "MONITOR_LOGIC_OUTS_B14_6", + "MONITOR_NW2A0_9", + "MONITOR_BYP3_3", + "MONITOR_LOGIC_OUTS_B18_7", + "MONITOR_NE4C3_7", + "MONITOR_WW4C0_5", + "MONITOR_IMUX16_4", + "MONITOR_NW4A3_1", + "MONITOR_EE4BEG3_1", + "MONITOR_EE4BEG1_2", + "MONITOR_EE4A2_7", + "MONITOR_BYP3_5", + "MONITOR_FAN6_5", + "MONITOR_LOGIC_OUTS_B10_5", + "MONITOR_IMUX45_3", + "MONITOR_NW4A3_5", + "MONITOR_SW4A0_3", + "MONITOR_SW4END1_5", + "MONITOR_NE4C1_7", + "MONITOR_SE4C0_8", + "MONITOR_LH7_4", + "MONITOR_EE4BEG2_2", + "MONITOR_IMUX46_3", + "MONITOR_WW4B3_8", + "MONITOR_EE4BEG3_7", + "MONITOR_IMUX17_8", + "MONITOR_SE2A1_6", + "MONITOR_EE4B1_4", + "MONITOR_IMUX47_2", + "MONITOR_LOGIC_OUTS_B15_3", + "MONITOR_SW2A2_0", + "MONITOR_IMUX46_8", + "MONITOR_EE4B0_9", + "MONITOR_ER1BEG0_7", + "MONITOR_IMUX41_4", + "MONITOR_EE2BEG0_1", + "MONITOR_FAN4_6", + "MONITOR_LOGIC_OUTS_B11_1", + "MONITOR_IMUX8_1", + "MONITOR_IMUX34_8", + "MONITOR_IMUX24_2", + "MONITOR_SW4END3_9", + "MONITOR_LOGIC_OUTS_B16_4", + "MONITOR_LOGIC_OUTS_B21_2", + "MONITOR_LH8_2", + "MONITOR_FAN4_0", + "MONITOR_EE2BEG2_7", + "MONITOR_IMUX38_2", + "MONITOR_IMUX14_0", + "MONITOR_WW4C3_7", + "MONITOR_IMUX20_4", + "MONITOR_LH6_4", + "MONITOR_VERT_VAUXP11", + "MONITOR_BYP2_8", + "MONITOR_FAN1_2", + "MONITOR_EE2A0_3", + "MONITOR_LOGIC_OUTS_B20_8", + "MONITOR_EE4B3_0", + "MONITOR_FAN2_2", + "MONITOR_EE4BEG3_8", + "MONITOR_LOGIC_OUTS_B18_0", + "MONITOR_IMUX5_7", + "MONITOR_ER1BEG2_6", + "MONITOR_IMUX7_9", + "MONITOR_IMUX27_2", + "MONITOR_LOGIC_OUTS_B4_2", + "MONITOR_SW4END1_0", + "MONITOR_CTRL1_2", + "MONITOR_WW2A3_6", + "MONITOR_IMUX25_8", + "MONITOR_NE4BEG0_5", + "MONITOR_NW4END2_1", + "MONITOR_IMUX20_5", + "MONITOR_IMUX46_9", + "MONITOR_IMUX35_3", + "MONITOR_EE4A2_0", + "MONITOR_WW4B2_0", + "MONITOR_IMUX14_2", + "MONITOR_EL1BEG1_6", + "MONITOR_EE2A0_4", + "MONITOR_EE2BEG1_5", + "MONITOR_IMUX43_4", + "MONITOR_WW4A1_0", + "MONITOR_IMUX46_7", + "MONITOR_IMUX10_2", + "MONITOR_LOGIC_OUTS_B13_1", + "MONITOR_IMUX9_8", + "MONITOR_EE4A3_7", + "MONITOR_LOGIC_OUTS_B1_1", + "MONITOR_IMUX41_6", + "MONITOR_LH4_0", + "MONITOR_VERT_VAUXN10", + "MONITOR_NE2A0_1", + "MONITOR_WL1END3_5", + "MONITOR_WW2A1_8", + "MONITOR_FAN7_5", + "MONITOR_CTRL0_3", + "MONITOR_BYP7_2", + "MONITOR_WW4B1_2", + "MONITOR_EE4B0_1", + "MONITOR_SE4BEG3_0", + "MONITOR_IMUX34_2", + "MONITOR_WW2A1_9", + "MONITOR_NE2A0_2", + "MONITOR_NW2A2_2", + "MONITOR_IMUX37_3", + "MONITOR_WW4END2_6", + "MONITOR_SW4A0_0", + "MONITOR_LH12_1", + "MONITOR_NE4BEG3_5", + "MONITOR_VERT_VAUXN4", + "MONITOR_WW4A1_1", + "MONITOR_NE4BEG3_9", + "MONITOR_WW4END2_1", + "MONITOR_ER1BEG1_8", + "MONITOR_FAN5_7", + "MONITOR_WL1END3_9", + "MONITOR_SW4A0_1", + "MONITOR_LOGIC_OUTS_B7_2", + "MONITOR_EE4A2_3", + "MONITOR_NW4A0_4", + "MONITOR_BLOCK_OUTS_B0_1", + "MONITOR_BYP1_1", + "MONITOR_IMUX9_9", + "MONITOR_IMUX26_1", + "MONITOR_LH7_6", + "MONITOR_WW4END1_7", + "MONITOR_LH1_1", + "MONITOR_LH10_7", + "MONITOR_IMUX33_3", + "MONITOR_LOGIC_OUTS_B2_7", + "MONITOR_WL1END0_5", + "MONITOR_IMUX45_4", + "MONITOR_NE2A0_3", + "MONITOR_EE4C3_2", + "MONITOR_IMUX24_3", + "MONITOR_NE4C2_1", + "MONITOR_LH1_4", + "MONITOR_EE2A3_4", + "MONITOR_NE4C1_6", + "MONITOR_NW4END3_2", + "MONITOR_LOGIC_OUTS_B7_0", + "MONITOR_IMUX22_8", + "MONITOR_IMUX3_4", + "MONITOR_NE4BEG1_1", + "MONITOR_EL1BEG3_8", + "MONITOR_EE2A2_9", + "MONITOR_EE4B1_9", + "MONITOR_EE4B1_6", + "MONITOR_SE4BEG1_9", + "MONITOR_WR1END0_5", + "MONITOR_WW2A1_0", + "MONITOR_EE4B1_2", + "MONITOR_NW2A0_7", + "MONITOR_SE4BEG3_8", + "MONITOR_LOGIC_OUTS_B23_8", + "MONITOR_NW2A2_7", + "MONITOR_EE2A2_5", + "MONITOR_EE2A2_8", + "MONITOR_NW4END0_0", + "MONITOR_NE4BEG2_8", + "MONITOR_NE4C2_8", + "MONITOR_SW4A1_3", + "MONITOR_IMUX8_0", + "MONITOR_LOGIC_OUTS_B1_2", + "MONITOR_IMUX42_9", + "MONITOR_WW4A1_4", + "MONITOR_WW4C2_8", + "MONITOR_SW2A0_7", + "MONITOR_NW4A2_0", + "MONITOR_EE4C1_2", + "MONITOR_EE2BEG1_4", + "MONITOR_IMUX28_9", + "MONITOR_IMUX10_6", + "MONITOR_BYP4_8", + "MONITOR_BYP0_7", + "MONITOR_SW2A3_7", + "MONITOR_WW2END0_0", + "MONITOR_VERT_VAUXP13", + "MONITOR_IMUX18_7", + "MONITOR_WR1END3_5", + "MONITOR_WW4END2_2", + "MONITOR_FAN5_6", + "MONITOR_NE4BEG3_3", + "MONITOR_WW2END2_4", + "MONITOR_EE4A2_8", + "MONITOR_NW4END1_1", + "MONITOR_SE4BEG0_9", + "MONITOR_VERT_VAUXP15", + "MONITOR_EE2A1_6", + "MONITOR_BYP1_0", + "MONITOR_NE4C0_0", + "MONITOR_EL1BEG3_3", + "MONITOR_LH8_3", + "MONITOR_IMUX7_1", + "MONITOR_NE4C2_5", + "MONITOR_IMUX23_2", + "MONITOR_EE4A0_6", + "MONITOR_ER1BEG1_5", + "MONITOR_CTRL0_9", + "MONITOR_LOGIC_OUTS_B22_8", + "MONITOR_SE4C1_6", + "MONITOR_WW4END1_2", + "MONITOR_BLOCK_OUTS_B2_8", + "MONITOR_EE4BEG1_8", + "MONITOR_IMUX42_5", + "MONITOR_EE4B0_5", + "MONITOR_SE4BEG1_8", + "MONITOR_BYP5_9", + "MONITOR_IMUX13_7", + "MONITOR_IMUX45_8", + "MONITOR_NE4BEG3_2", + "MONITOR_WW2END3_7", + "MONITOR_BLOCK_OUTS_B0_9", + "MONITOR_IMUX35_0", + "MONITOR_IMUX33_8", + "MONITOR_EE4BEG0_6", + "MONITOR_LOGIC_OUTS_B8_5", + "MONITOR_LOGIC_OUTS_B9_0", + "MONITOR_EE2BEG2_5", + "MONITOR_BLOCK_OUTS_B3_6", + "MONITOR_SW4END0_1", + "MONITOR_IMUX37_9", + "MONITOR_ER1BEG1_4", + "MONITOR_LOGIC_OUTS_B7_8", + "MONITOR_IMUX3_7", + "MONITOR_LOGIC_OUTS_B16_1", + "MONITOR_EE2A2_2", + "MONITOR_WW2END2_2", + "MONITOR_BYP5_1", + "MONITOR_FAN4_1", + "MONITOR_LOGIC_OUTS_B13_4", + "MONITOR_BYP7_6", + "MONITOR_NE4BEG2_1", + "MONITOR_WR1END1_2", + "MONITOR_IMUX8_7", + "MONITOR_LH8_1", + "MONITOR_LOGIC_OUTS_B2_4", + "MONITOR_WL1END2_8", + "MONITOR_NW4A3_4", + "MONITOR_BLOCK_OUTS_B3_3", + "MONITOR_SE4C3_5", + "MONITOR_WW4C0_7", + "MONITOR_FAN1_3", + "MONITOR_BYP5_7", + "MONITOR_WW4A1_2", + "MONITOR_SE4BEG1_0", + "MONITOR_FAN7_4", + "MONITOR_WW4A0_4", + "MONITOR_VERT_VAUXP12", + "MONITOR_EE4A0_8", + "MONITOR_EE4B1_5", + "MONITOR_WW2A1_4", + "MONITOR_EE4A1_3", + "MONITOR_BYP3_4", + "MONITOR_NW4A1_8", + "MONITOR_IMUX11_0", + "MONITOR_SE4BEG3_5", + "MONITOR_IMUX6_0", + "MONITOR_IMUX4_8", + "MONITOR_IMUX12_4", + "MONITOR_IMUX30_9", + "MONITOR_IMUX25_2", + "MONITOR_BYP7_4", + "MONITOR_NW4END1_6", + "MONITOR_LOGIC_OUTS_B6_3", + "MONITOR_LOGIC_OUTS_B8_8", + "MONITOR_VERT_VAUXP8", + "MONITOR_EE4A1_1", + "MONITOR_IMUX46_6", + "MONITOR_LOGIC_OUTS_B20_2", + "MONITOR_WW4A3_5", + "MONITOR_IMUX2_7", + "MONITOR_WW2END2_3", + "MONITOR_NE4C2_6", + "MONITOR_BYP5_5", + "MONITOR_LOGIC_OUTS_B1_9", + "MONITOR_SE4C2_9", + "MONITOR_EE4BEG1_9", + "MONITOR_IMUX17_5", + "MONITOR_NW4A0_3", + "MONITOR_WW2END2_7", + "MONITOR_SW2A2_5", + "MONITOR_SW4A1_6", + "MONITOR_WW4B1_1", + "MONITOR_IMUX40_7", + "MONITOR_LOGIC_OUTS_B5_6", + "MONITOR_IMUX37_7", + "MONITOR_NE2A2_3", + "MONITOR_FAN0_3", + "MONITOR_SE4C0_3", + "MONITOR_IMUX22_7", + "MONITOR_SW2A0_6", + "MONITOR_HORIZ_VAUXN10", + "MONITOR_LOGIC_OUTS_B14_5", + "MONITOR_LH6_5", + "MONITOR_IMUX44_0", + "MONITOR_IMUX43_8", + "MONITOR_NE2A0_0", + "MONITOR_NW2A3_6", + "MONITOR_ER1BEG1_2", + "MONITOR_FAN3_0", + "MONITOR_LOGIC_OUTS_B14_3", + "MONITOR_IMUX41_0", + "MONITOR_NE4C2_0", + "MONITOR_NW2A3_4", + "MONITOR_LOGIC_OUTS_B5_5", + "MONITOR_LH5_2", + "MONITOR_LOGIC_OUTS_B3_2", + "MONITOR_EL1BEG0_2", + "MONITOR_CLK0_6", + "MONITOR_SW4END3_1", + "MONITOR_IMUX17_6", + "MONITOR_EE4C3_1", + "MONITOR_IMUX13_1", + "MONITOR_LH9_3", + "MONITOR_EE2BEG0_7", + "MONITOR_VERT_VAUXN0", + "MONITOR_FAN7_8", + "MONITOR_FAN5_0", + "MONITOR_SE4BEG0_7", + "MONITOR_LOGIC_OUTS_B20_9", + "MONITOR_LOGIC_OUTS_B11_4", + "MONITOR_NW4END2_8", + "MONITOR_LH7_3", + "MONITOR_LOGIC_OUTS_B9_9", + "MONITOR_IMUX37_5", + "MONITOR_IMUX26_3", + "MONITOR_IMUX18_5", + "MONITOR_WR1END1_9", + "MONITOR_EE4C0_5", + "MONITOR_NW4END1_4", + "MONITOR_LH2_5", + "MONITOR_EL1BEG2_1", + "MONITOR_NW4A1_4", + "MONITOR_VERT_VAUXN9", + "MONITOR_LOGIC_OUTS_B15_7", + "MONITOR_VERT_VAUXP5", + "MONITOR_BYP6_2", + "MONITOR_IMUX21_5", + "MONITOR_IMUX20_7", + "MONITOR_SW4END1_7", + "MONITOR_IMUX45_0", + "MONITOR_EE4B0_4", + "MONITOR_FAN3_4", + "MONITOR_NW2A0_8", + "MONITOR_FAN1_8", + "MONITOR_SE4BEG3_4", + "MONITOR_LH5_5", + "MONITOR_NE4BEG3_0", + "MONITOR_NW2A1_1", + "MONITOR_BLOCK_OUTS_B1_7", + "MONITOR_IMUX9_6", + "MONITOR_SE4BEG2_6", + "MONITOR_LH7_9", + "MONITOR_FAN1_9", + "MONITOR_WW2END0_2", + "MONITOR_IMUX44_5", + "MONITOR_IMUX22_9", + "MONITOR_IMUX19_1", + "MONITOR_IMUX36_4", + "MONITOR_NW2A1_2", + "MONITOR_SW4A1_1", + "MONITOR_IMUX18_8", + "MONITOR_VERT_VAUXN11", + "MONITOR_WW4C2_7", + "MONITOR_IMUX16_9", + "MONITOR_EE4B3_4", + "MONITOR_IMUX19_9", + "MONITOR_WL1END1_5", + "MONITOR_IMUX38_5", + "MONITOR_CTRL1_6", + "MONITOR_IMUX38_9", + "MONITOR_NW4END2_0", + "MONITOR_IMUX36_9", + "MONITOR_EE4B0_3", + "MONITOR_ER1BEG0_6", + "MONITOR_CLK1_4", + "MONITOR_WW4B0_6", + "MONITOR_NE4BEG1_5", + "MONITOR_SW4END0_3", + "MONITOR_BYP6_0", + "MONITOR_NW2A3_5", + "MONITOR_ER1BEG1_1", + "MONITOR_SE4BEG2_4", + "MONITOR_EE2BEG3_3", + "MONITOR_NE2A2_0", + "MONITOR_LOGIC_OUTS_B4_3", + "MONITOR_EL1BEG3_5", + "MONITOR_WW4B1_7", + "MONITOR_WL1END0_1", + "MONITOR_NW2A2_9", + "MONITOR_IMUX29_7", + "MONITOR_IMUX43_5", + "MONITOR_EE4B3_5", + "MONITOR_EE2A3_9", + "MONITOR_SE2A1_2", + "MONITOR_EE2BEG1_2", + "MONITOR_NE4C2_4", + "MONITOR_WW4END3_5", + "MONITOR_SE4BEG2_3", + "MONITOR_SE4BEG0_1", + "MONITOR_LOGIC_OUTS_B17_1", + "MONITOR_LH10_4", + "MONITOR_LH8_6", + "MONITOR_NW4A0_1", + "MONITOR_CTRL1_8", + "MONITOR_LOGIC_OUTS_B11_9", + "MONITOR_IMUX11_7", + "MONITOR_WW4C1_2", + "MONITOR_IMUX34_6", + "MONITOR_WW2END1_0", + "MONITOR_WW4A1_6", + "MONITOR_IMUX12_0", + "MONITOR_LOGIC_OUTS_B23_4", + "MONITOR_SW2A0_0", + "MONITOR_BYP2_6", + "MONITOR_IMUX38_8", + "MONITOR_SE4BEG1_3", + "MONITOR_SE4C2_8", + "MONITOR_SE2A1_1", + "MONITOR_BLOCK_OUTS_B3_7", + "MONITOR_SE4C2_0", + "MONITOR_IMUX11_8", + "MONITOR_IMUX34_7", + "MONITOR_IMUX42_3", + "MONITOR_EE4BEG3_9", + "MONITOR_WW4END1_4", + "MONITOR_EE4C3_8", + "MONITOR_IMUX47_3", + "MONITOR_EE2BEG1_6", + "MONITOR_IMUX45_7", + "MONITOR_NE4BEG2_2", + "MONITOR_IMUX12_9", + "MONITOR_VERT_VAUXP10", + "MONITOR_ER1BEG2_8", + "MONITOR_WL1END3_4", + "MONITOR_FAN6_4", + "MONITOR_WW4C0_1", + "MONITOR_LH7_5", + "MONITOR_LOGIC_OUTS_B20_3", + "MONITOR_LOGIC_OUTS_B21_3", + "MONITOR_NW4END3_6", + "MONITOR_WL1END0_0", + "MONITOR_IMUX31_5", + "MONITOR_EL1BEG3_6", + "MONITOR_IMUX32_3", + "MONITOR_EE2A2_7", + "MONITOR_SE4C1_8", + "MONITOR_IMUX29_8", + "MONITOR_WW4A3_2", + "MONITOR_ER1BEG3_4", + "MONITOR_IMUX36_7", + "MONITOR_IMUX36_3", + "MONITOR_WW4C3_4", + "MONITOR_WW4B1_3", + "MONITOR_LH8_4", + "MONITOR_IMUX14_3", + "MONITOR_SW4END3_6", + "MONITOR_NW2A3_7", + "MONITOR_NW4A2_9", + "MONITOR_NE4BEG0_3", + "MONITOR_EE4C2_7", + "MONITOR_SE4BEG1_6", + "MONITOR_SE4C3_8", + "MONITOR_WW4A0_7", + "MONITOR_BLOCK_OUTS_B3_8", + "MONITOR_NW2A3_1", + "MONITOR_FAN5_1", + "MONITOR_IMUX42_0", + "MONITOR_CTRL0_4", + "MONITOR_BLOCK_OUTS_B1_8", + "MONITOR_IMUX15_2", + "MONITOR_IMUX6_4", + "MONITOR_EE2BEG2_9", + "MONITOR_IMUX25_9", + "MONITOR_ER1BEG2_7", + "MONITOR_IMUX28_4", + "MONITOR_IMUX33_6", + "MONITOR_LOGIC_OUTS_B9_6", + "MONITOR_WW4A3_0", + "MONITOR_WW4END1_9", + "MONITOR_NE2A2_8", + "MONITOR_SE2A0_9", + "MONITOR_SW2A0_4", + "MONITOR_NW4END3_7", + "MONITOR_LOGIC_OUTS_B15_9", + "MONITOR_EE4BEG2_8", + "MONITOR_WW4B3_7", + "MONITOR_IMUX44_4", + "MONITOR_NE4C3_0", + "MONITOR_LOGIC_OUTS_B2_8", + "MONITOR_LOGIC_OUTS_B12_1", + "MONITOR_BLOCK_OUTS_B2_0", + "MONITOR_CTRL1_1", + "MONITOR_NW4A0_7", + "MONITOR_EE2A2_6", + "MONITOR_IMUX21_1", + "MONITOR_WW4END0_2", + "MONITOR_LH3_5", + "MONITOR_BLOCK_OUTS_B2_2", + "MONITOR_LH5_3", + "MONITOR_WW4END0_5", + "MONITOR_VERT_VAUXP0", + "MONITOR_WW2A0_8", + "MONITOR_LH6_9", + "MONITOR_EE2BEG0_5", + "MONITOR_LH1_7", + "MONITOR_CLK1_5", + "MONITOR_LOGIC_OUTS_B19_5", + "MONITOR_EL1BEG3_2", + "MONITOR_EE4BEG3_3", + "MONITOR_BYP7_1", + "MONITOR_BLOCK_OUTS_B0_6", + "MONITOR_IMUX33_1", + "MONITOR_IMUX22_3", + "MONITOR_BYP7_8", + "MONITOR_LH6_7", + "MONITOR_EE4BEG0_3", + "MONITOR_NE2A1_9", + "MONITOR_WW4A2_4", + "MONITOR_LH3_3", + "MONITOR_NE4BEG1_2", + "MONITOR_SE2A2_9", + "MONITOR_HORIZ_VAUXP2", + "MONITOR_FAN1_4", + "MONITOR_IMUX24_1", + "MONITOR_IMUX2_9", + "MONITOR_SW4END1_3", + "MONITOR_WW4C2_9", + "MONITOR_NE4C3_5", + "MONITOR_IMUX13_2", + "MONITOR_IMUX24_6", + "MONITOR_IMUX5_2", + "MONITOR_NE2A0_5", + "MONITOR_LOGIC_OUTS_B18_6", + "MONITOR_IMUX13_8", + "MONITOR_BLOCK_OUTS_B2_5", + "MONITOR_LOGIC_OUTS_B3_9", + "MONITOR_LOGIC_OUTS_B5_2", + "MONITOR_LH5_4", + "MONITOR_LOGIC_OUTS_B2_0", + "MONITOR_WW4A2_7", + "MONITOR_BYP7_9", + "MONITOR_CTRL1_7", + "MONITOR_EE2A3_7", + "MONITOR_NE4BEG3_4", + "MONITOR_IMUX14_1", + "MONITOR_SW4A2_8", + "MONITOR_IMUX17_2", + "MONITOR_WW4END2_3", + "MONITOR_WW2A0_1", + "MONITOR_IMUX30_7", + "MONITOR_IMUX11_6", + "MONITOR_WW4A2_1", + "MONITOR_IMUX3_8", + "MONITOR_EE2BEG3_4", + "MONITOR_EE4B3_6", + "MONITOR_IMUX47_6", + "MONITOR_WL1END2_2", + "MONITOR_NE4BEG1_8", + "MONITOR_IMUX4_9", + "MONITOR_SW4A0_6", + "MONITOR_SW4END2_5", + "MONITOR_EE4B3_7", + "MONITOR_IMUX44_6", + "MONITOR_NW2A3_2", + "MONITOR_ER1BEG2_3", + "MONITOR_FAN6_9", + "MONITOR_WW4B1_0", + "MONITOR_SW4A3_3", + "MONITOR_SW2A3_1", + "MONITOR_IMUX3_2", + "MONITOR_CTRL1_0", + "MONITOR_IMUX47_0", + "MONITOR_SE4BEG0_0", + "MONITOR_BYP5_3", + "MONITOR_NE4BEG3_6", + "MONITOR_EL1BEG0_7", + "MONITOR_BYP6_9", + "MONITOR_FAN6_1", + "MONITOR_IMUX40_0", + "MONITOR_BYP7_5", + "MONITOR_EL1BEG2_6" + ], + "pips": { + "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXP10->MONITOR_VERT_VAUXP10": { + "src_wire": "MONITOR_HORIZ_VAUXP10", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP10", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXP2->MONITOR_VERT_VAUXP2": { + "src_wire": "MONITOR_HORIZ_VAUXP2", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXN1->MONITOR_VERT_VAUXN1": { + "src_wire": "MONITOR_HORIZ_VAUXN1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXN2->MONITOR_VERT_VAUXN2": { + "src_wire": "MONITOR_HORIZ_VAUXN2", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN2", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXP1->MONITOR_VERT_VAUXP1": { + "src_wire": "MONITOR_HORIZ_VAUXP1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP1", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXP9->MONITOR_VERT_VAUXP9": { + "src_wire": "MONITOR_HORIZ_VAUXP9", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP9", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXN9->MONITOR_VERT_VAUXN9": { + "src_wire": "MONITOR_HORIZ_VAUXN9", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN9", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXN10->MONITOR_VERT_VAUXN10": { + "src_wire": "MONITOR_HORIZ_VAUXN10", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN10", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_MONITOR_TOP_FUJI2.json b/kintex7/tile_type_MONITOR_TOP_FUJI2.json new file mode 100644 index 0000000..08bfd31 --- /dev/null +++ b/kintex7/tile_type_MONITOR_TOP_FUJI2.json @@ -0,0 +1,1172 @@ +{ + "tile_type": "MONITOR_TOP_FUJI2", + "sites": [], + "wires": [ + "MONITOR_LH12_4", + "MONITOR_WW2END3_4", + "MONITOR_IMUX36_2", + "MONITOR_IMUX35_4", + "MONITOR_SE4C3_3", + "MONITOR_WW4C1_3", + "MONITOR_NE4C3_4", + "MONITOR_ER1BEG2_1", + "MONITOR_BYP3_1", + "MONITOR_ER1BEG0_0", + "MONITOR_EE2BEG1_0", + "MONITOR_LOGIC_OUTS_B11_2", + "MONITOR_BYP2_4", + "MONITOR_EL1BEG0_1", + "MONITOR_NW4END2_3", + "MONITOR_BLOCK_OUTS_B2_3", + "MONITOR_LOGIC_OUTS_B12_4", + "MONITOR_WW4A0_2", + "MONITOR_SW4END3_2", + "MONITOR_CLK0_2", + "MONITOR_LOGIC_OUTS_B8_3", + "MONITOR_LOGIC_OUTS_B23_3", + "MONITOR_WW2A0_4", + "MONITOR_NW2A2_4", + "MONITOR_LOGIC_OUTS_B3_0", + "MONITOR_WW4END0_0", + "MONITOR_BLOCK_OUTS_B0_4", + "MONITOR_LOGIC_OUTS_B11_0", + "MONITOR_WW4END1_1", + "MONITOR_IMUX37_2", + "MONITOR_WW2END3_1", + "MONITOR_LH2_4", + "MONITOR_LOGIC_OUTS_B5_4", + "MONITOR_EE4B2_2", + "MONITOR_FAN4_3", + "MONITOR_BYP6_3", + "MONITOR_BYP2_2", + "MONITOR_WW2A1_2", + "MONITOR_EE2A3_0", + "MONITOR_WW2END3_0", + "MONITOR_NE4C1_0", + "MONITOR_SE2A2_3", + "MONITOR_SW4A1_4", + "MONITOR_EE2BEG2_0", + "MONITOR_SW4A3_1", + "MONITOR_LOGIC_OUTS_B8_0", + "MONITOR_SW4END3_4", + "MONITOR_VERT_SHORT_VAUXP11", + "MONITOR_EE4BEG3_4", + "MONITOR_EE4C0_3", + "MONITOR_EE4B2_1", + "MONITOR_WW4B3_3", + "MONITOR_ER1BEG3_3", + "MONITOR_WW4C1_0", + "MONITOR_IMUX34_1", + "MONITOR_NW2A2_3", + "MONITOR_IMUX43_1", + "MONITOR_IMUX19_0", + "MONITOR_IMUX29_0", + "MONITOR_IMUX2_4", + "MONITOR_LH1_2", + "MONITOR_LOGIC_OUTS_B1_3", + "MONITOR_BYP5_0", + "MONITOR_NE4C3_1", + "MONITOR_LH4_3", + "MONITOR_SW4END1_4", + "MONITOR_EE2A1_0", + "MONITOR_IMUX34_0", + "MONITOR_LOGIC_OUTS_B19_3", + "MONITOR_IMUX27_1", + "MONITOR_NW2A2_1", + "MONITOR_FAN2_4", + "MONITOR_LOGIC_OUTS_B23_2", + "MONITOR_FAN0_1", + "MONITOR_EE4A3_3", + "MONITOR_WW2A2_2", + "MONITOR_WW2END2_0", + "MONITOR_IMUX42_4", + "MONITOR_SE2A2_2", + "MONITOR_WW4END3_1", + "MONITOR_IMUX17_1", + "MONITOR_NW4A0_2", + "MONITOR_LH2_3", + "MONITOR_IMUX30_4", + "MONITOR_BYP4_0", + "MONITOR_IMUX18_4", + "MONITOR_NW4END1_3", + "MONITOR_WW4B0_0", + "MONITOR_WW4C0_0", + "MONITOR_LH1_3", + "MONITOR_ER1BEG3_1", + "MONITOR_SE4C0_0", + "MONITOR_LH5_0", + "MONITOR_IMUX13_4", + "MONITOR_LH12_0", + "MONITOR_EE4A1_0", + "MONITOR_NE4BEG3_1", + "MONITOR_NW2A0_2", + "MONITOR_LOGIC_OUTS_B12_0", + "MONITOR_FAN5_2", + "MONITOR_BLOCK_OUTS_B0_0", + "MONITOR_IMUX3_1", + "MONITOR_WW4END3_4", + "MONITOR_CLK0_3", + "MONITOR_EL1BEG1_1", + "MONITOR_WR1END1_0", + "MONITOR_IMUX5_3", + "MONITOR_IMUX25_1", + "MONITOR_FAN4_4", + "MONITOR_LOGIC_OUTS_B10_3", + "MONITOR_EE4A1_2", + "MONITOR_EE4C2_4", + "MONITOR_SW2A0_2", + "MONITOR_IMUX36_0", + "MONITOR_NE2A3_1", + "MONITOR_LH4_4", + "MONITOR_IMUX16_3", + "MONITOR_IMUX40_1", + "MONITOR_EE4C3_4", + "MONITOR_WW4A0_0", + "MONITOR_IMUX0_3", + "MONITOR_LH6_2", + "MONITOR_IMUX4_0", + "MONITOR_IMUX6_1", + "MONITOR_BLOCK_OUTS_B1_2", + "MONITOR_WW4END1_0", + "MONITOR_LOGIC_OUTS_B17_0", + "MONITOR_WL1END1_3", + "MONITOR_SE4BEG3_2", + "MONITOR_IMUX31_3", + "MONITOR_EE4BEG0_1", + "MONITOR_NW4A3_2", + "MONITOR_BLOCK_OUTS_B3_0", + "MONITOR_EE2A3_1", + "MONITOR_LOGIC_OUTS_B0_4", + "MONITOR_EL1BEG2_2", + "MONITOR_WR1END2_2", + "MONITOR_WW4C2_1", + "MONITOR_SE4C1_1", + "MONITOR_NE4C2_2", + "MONITOR_FAN3_2", + "MONITOR_HORIZ_VAUXP8", + "MONITOR_LOGIC_OUTS_B12_3", + "MONITOR_WW4END0_3", + "MONITOR_EL1BEG2_3", + "MONITOR_BYP6_4", + "MONITOR_VERT_SHORT_VAUXN10", + "MONITOR_LOGIC_OUTS_B9_3", + "MONITOR_SW4A2_1", + "MONITOR_BLOCK_OUTS_B0_2", + "MONITOR_IMUX30_0", + "MONITOR_CLK0_1", + "MONITOR_EL1BEG1_3", + "MONITOR_SW4A3_2", + "MONITOR_NE4BEG1_4", + "MONITOR_LOGIC_OUTS_B13_3", + "MONITOR_WL1END2_1", + "MONITOR_IMUX21_4", + "MONITOR_LOGIC_OUTS_B0_0", + "MONITOR_SW4A2_4", + "MONITOR_SW4END2_4", + "MONITOR_LH5_1", + "MONITOR_IMUX23_3", + "MONITOR_EE4C1_4", + "MONITOR_EE4C0_0", + "MONITOR_LH2_0", + "MONITOR_EE4A1_4", + "MONITOR_SW2A3_2", + "MONITOR_NE2A2_4", + "MONITOR_NW4A3_3", + "MONITOR_IMUX46_1", + "MONITOR_IMUX27_4", + "MONITOR_IMUX37_4", + "MONITOR_ER1BEG0_4", + "MONITOR_IMUX44_3", + "MONITOR_VERT_SHORT_VAUXP3", + "MONITOR_LOGIC_OUTS_B10_4", + "MONITOR_SW4A1_2", + "MONITOR_NW4END2_4", + "MONITOR_WW2A2_1", + "MONITOR_ER1BEG1_3", + "MONITOR_IMUX40_2", + "MONITOR_LOGIC_OUTS_B8_2", + "MONITOR_SW4END3_3", + "MONITOR_CTRL1_4", + "MONITOR_IMUX41_2", + "MONITOR_IMUX21_3", + "MONITOR_SW2A3_3", + "MONITOR_EE4C0_4", + "MONITOR_LOGIC_OUTS_B17_2", + "MONITOR_FAN6_2", + "MONITOR_BLOCK_OUTS_B2_4", + "MONITOR_NW4A2_2", + "MONITOR_WW2A2_3", + "MONITOR_EL1BEG3_0", + "MONITOR_SE2A2_0", + "MONITOR_VERT_SHORT_VAUXN15", + "MONITOR_IMUX16_1", + "MONITOR_LOGIC_OUTS_B0_2", + "MONITOR_WL1END2_0", + "MONITOR_SW2A0_3", + "MONITOR_IMUX3_0", + "MONITOR_WR1END0_4", + "MONITOR_FAN7_3", + "MONITOR_NW4END1_2", + "MONITOR_WW2END1_2", + "MONITOR_NE4BEG0_4", + "MONITOR_WW4A2_0", + "MONITOR_BYP0_4", + "MONITOR_WW4B0_4", + "MONITOR_NW4END3_0", + "MONITOR_NE2A2_2", + "MONITOR_LH8_0", + "MONITOR_EL1BEG1_4", + "MONITOR_LH1_0", + "MONITOR_IMUX34_4", + "MONITOR_HORIZ_VAUXN0", + "MONITOR_VERT_SHORT_VAUXN14", + "MONITOR_IMUX29_3", + "MONITOR_IMUX27_0", + "MONITOR_WW4C1_4", + "MONITOR_VERT_SHORT_VAUXP6", + "MONITOR_LOGIC_OUTS_B13_2", + "MONITOR_EE4C2_0", + "MONITOR_IMUX30_3", + "MONITOR_IMUX18_1", + "MONITOR_IMUX28_2", + "MONITOR_IMUX4_4", + "MONITOR_IMUX9_3", + "MONITOR_NE4BEG1_3", + "MONITOR_LH3_2", + "MONITOR_SW4END0_0", + "MONITOR_LH10_1", + "MONITOR_SE4BEG3_3", + "MONITOR_EE4BEG3_0", + "MONITOR_LOGIC_OUTS_B5_0", + "MONITOR_IMUX23_0", + "MONITOR_NE4C1_2", + "MONITOR_LOGIC_OUTS_B22_0", + "MONITOR_IMUX28_1", + "MONITOR_WW4C2_0", + "MONITOR_NE2A1_2", + "MONITOR_VERT_SHORT_VAUXN6", + "MONITOR_LOGIC_OUTS_B10_2", + "MONITOR_WL1END1_0", + "MONITOR_SE4BEG2_1", + "MONITOR_SE4C0_1", + "MONITOR_EE4BEG0_0", + "MONITOR_BYP3_0", + "MONITOR_EE4B0_0", + "MONITOR_WW4B0_2", + "MONITOR_IMUX28_0", + "MONITOR_EE4BEG1_3", + "MONITOR_VERT_SHORT_VAUXN11", + "MONITOR_LOGIC_OUTS_B16_0", + "MONITOR_EE2BEG3_2", + "MONITOR_EE2BEG0_2", + "MONITOR_EE4C0_1", + "MONITOR_NE4BEG0_0", + "MONITOR_LOGIC_OUTS_B2_3", + "MONITOR_LOGIC_OUTS_B2_2", + "MONITOR_IMUX3_3", + "MONITOR_NE2A3_0", + "MONITOR_CTRL0_1", + "MONITOR_VERT_SHORT_VAUXN8", + "MONITOR_WW4END0_1", + "MONITOR_NE4C0_4", + "MONITOR_WW4END3_3", + "MONITOR_EE2A1_2", + "MONITOR_WW4C3_0", + "MONITOR_WW2A0_0", + "MONITOR_IMUX46_0", + "MONITOR_EE2A0_0", + "MONITOR_SW4END0_2", + "MONITOR_LOGIC_OUTS_B22_1", + "MONITOR_EL1BEG1_0", + "MONITOR_IMUX31_4", + "MONITOR_LOGIC_OUTS_B18_2", + "MONITOR_SW4END2_3", + "MONITOR_NW2A0_0", + "MONITOR_CLK1_1", + "MONITOR_LH9_2", + "MONITOR_EE2BEG2_3", + "MONITOR_LOGIC_OUTS_B9_2", + "MONITOR_EE4A3_1", + "MONITOR_LOGIC_OUTS_B3_4", + "MONITOR_SE2A1_4", + "MONITOR_IMUX33_4", + "MONITOR_LOGIC_OUTS_B9_4", + "MONITOR_LOGIC_OUTS_B3_3", + "MONITOR_BYP3_2", + "MONITOR_IMUX2_3", + "MONITOR_IMUX18_2", + "MONITOR_WW2END0_4", + "MONITOR_NW4A1_2", + "MONITOR_IMUX35_2", + "MONITOR_FAN2_3", + "MONITOR_SE4C3_4", + "MONITOR_LOGIC_OUTS_B22_3", + "MONITOR_EE4BEG1_1", + "MONITOR_WW4B1_4", + "MONITOR_IMUX26_0", + "MONITOR_WW4C0_2", + "MONITOR_IMUX33_0", + "MONITOR_EE4C3_0", + "MONITOR_LOGIC_OUTS_B7_4", + "MONITOR_VERT_SHORT_VAUXP14", + "MONITOR_SE4C1_3", + "MONITOR_LOGIC_OUTS_B14_2", + "MONITOR_NE2A1_0", + "MONITOR_LOGIC_OUTS_B15_2", + "MONITOR_IMUX7_2", + "MONITOR_SW2A2_1", + "MONITOR_LOGIC_OUTS_B6_4", + "MONITOR_NE2A1_1", + "MONITOR_VERT_SHORT_VAUXP8", + "MONITOR_LOGIC_OUTS_B19_1", + "MONITOR_ER1BEG2_0", + "MONITOR_IMUX22_2", + "MONITOR_LH6_3", + "MONITOR_LH9_0", + "MONITOR_WR1END0_0", + "MONITOR_IMUX8_4", + "MONITOR_SW4A2_2", + "MONITOR_IMUX1_3", + "MONITOR_NW2A1_3", + "MONITOR_SW2A1_0", + "MONITOR_EE2A1_3", + "MONITOR_WW4C0_3", + "MONITOR_SE4BEG1_4", + "MONITOR_BYP6_1", + "MONITOR_IMUX10_3", + "MONITOR_WW4B0_1", + "MONITOR_WW4C3_1", + "MONITOR_LOGIC_OUTS_B9_1", + "MONITOR_LOGIC_OUTS_B20_1", + "MONITOR_EE4A2_1", + "MONITOR_IMUX5_1", + "MONITOR_FAN7_1", + "MONITOR_IMUX31_0", + "MONITOR_WW4END3_2", + "MONITOR_WL1END0_3", + "MONITOR_BYP0_0", + "MONITOR_NW4END0_3", + "MONITOR_HORIZ_VAUXN8", + "MONITOR_LOGIC_OUTS_B21_0", + "MONITOR_WL1END2_3", + "MONITOR_SW2A2_2", + "MONITOR_LOGIC_OUTS_B5_1", + "MONITOR_NW4A1_1", + "MONITOR_LOGIC_OUTS_B1_4", + "MONITOR_SE4C0_4", + "MONITOR_SE4C1_0", + "MONITOR_SE4BEG0_4", + "MONITOR_IMUX45_1", + "MONITOR_EE2BEG2_1", + "MONITOR_EE2BEG1_3", + "MONITOR_WL1END3_1", + "MONITOR_IMUX2_2", + "MONITOR_EE4B1_0", + "MONITOR_IMUX25_0", + "MONITOR_IMUX24_4", + "MONITOR_IMUX4_3", + "MONITOR_LH10_3", + "MONITOR_IMUX33_2", + "MONITOR_LH11_3", + "MONITOR_LOGIC_OUTS_B17_4", + "MONITOR_LOGIC_OUTS_B1_0", + "MONITOR_BYP5_4", + "MONITOR_WW2A2_4", + "MONITOR_LOGIC_OUTS_B12_2", + "MONITOR_WR1END2_3", + "MONITOR_WW2A3_4", + "MONITOR_LH12_2", + "MONITOR_FAN1_1", + "MONITOR_EE2BEG1_1", + "MONITOR_SE4C3_2", + "MONITOR_SW4END1_1", + "MONITOR_NE4BEG1_0", + "MONITOR_FAN0_2", + "MONITOR_IMUX6_2", + "MONITOR_IMUX41_1", + "MONITOR_EE2A3_2", + "MONITOR_VERT_SHORT_VAUXN2", + "MONITOR_VERT_SHORT_VAUXN7", + "MONITOR_SE2A3_1", + "MONITOR_EE2A0_2", + "MONITOR_BLOCK_OUTS_B1_0", + "MONITOR_IMUX29_2", + "MONITOR_IMUX0_4", + "MONITOR_EL1BEG0_0", + "MONITOR_IMUX30_2", + "MONITOR_NW4A2_3", + "MONITOR_SE2A2_1", + "MONITOR_WW2A0_2", + "MONITOR_LOGIC_OUTS_B16_2", + "MONITOR_IMUX31_1", + "MONITOR_BYP1_2", + "MONITOR_LH12_3", + "MONITOR_NW2A0_3", + "MONITOR_SE4BEG0_2", + "MONITOR_LOGIC_OUTS_B15_0", + "MONITOR_SW4END3_0", + "MONITOR_IMUX47_1", + "MONITOR_IMUX40_4", + "MONITOR_WW2END2_1", + "MONITOR_BLOCK_OUTS_B2_1", + "MONITOR_IMUX32_1", + "MONITOR_NE4BEG2_4", + "MONITOR_WL1END0_4", + "MONITOR_ER1BEG0_3", + "MONITOR_IMUX45_2", + "MONITOR_BLOCK_OUTS_B3_1", + "MONITOR_WL1END0_2", + "MONITOR_IMUX34_3", + "MONITOR_LOGIC_OUTS_B4_4", + "MONITOR_IMUX23_4", + "MONITOR_NE2A3_2", + "MONITOR_SE2A0_4", + "MONITOR_VERT_SHORT_VAUXP0", + "MONITOR_IMUX21_2", + "MONITOR_SE4BEG0_3", + "MONITOR_EE4C2_2", + "MONITOR_WL1END3_3", + "MONITOR_NW4END0_1", + "MONITOR_EE4BEG2_0", + "MONITOR_IMUX9_0", + "MONITOR_NW2A3_3", + "MONITOR_EE4B2_0", + "MONITOR_SE2A1_3", + "MONITOR_SW2A1_1", + "MONITOR_IMUX13_3", + "MONITOR_SE4BEG2_2", + "MONITOR_BYP4_3", + "MONITOR_LH9_1", + "MONITOR_NE2A1_3", + "MONITOR_ER1BEG3_0", + "MONITOR_ER1BEG1_0", + "MONITOR_SE2A0_1", + "MONITOR_IMUX39_0", + "MONITOR_IMUX0_2", + "MONITOR_LOGIC_OUTS_B0_1", + "MONITOR_BLOCK_OUTS_B3_2", + "MONITOR_IMUX24_0", + "MONITOR_NE4C1_3", + "MONITOR_IMUX37_1", + "MONITOR_IMUX22_0", + "MONITOR_EE4A3_4", + "MONITOR_IMUX11_2", + "MONITOR_EE4A0_1", + "MONITOR_NE4C2_3", + "MONITOR_NW4END2_2", + "MONITOR_SW2A1_3", + "MONITOR_NE4BEG2_3", + "MONITOR_LOGIC_OUTS_B7_3", + "MONITOR_EE4B3_2", + "MONITOR_EE4BEG2_1", + "MONITOR_IMUX20_2", + "MONITOR_LOGIC_OUTS_B0_3", + "MONITOR_IMUX29_1", + "MONITOR_WR1END3_1", + "MONITOR_WR1END3_2", + "MONITOR_IMUX13_0", + "MONITOR_LOGIC_OUTS_B7_1", + "MONITOR_IMUX12_1", + "MONITOR_IMUX23_1", + "MONITOR_NE4BEG2_0", + "MONITOR_IMUX32_0", + "MONITOR_SE2A0_2", + "MONITOR_IMUX43_2", + "MONITOR_SE4C3_1", + "MONITOR_LH7_0", + "MONITOR_NW2A0_1", + "MONITOR_WW2END1_1", + "MONITOR_NW4A0_0", + "MONITOR_IMUX16_0", + "MONITOR_ER1BEG3_2", + "MONITOR_WW2END3_2", + "MONITOR_LOGIC_OUTS_B18_3", + "MONITOR_BYP4_4", + "MONITOR_EE2A2_0", + "MONITOR_NW4END3_1", + "MONITOR_IMUX1_4", + "MONITOR_IMUX39_3", + "MONITOR_LOGIC_OUTS_B23_1", + "MONITOR_EE4B2_3", + "MONITOR_NE4BEG0_1", + "MONITOR_CLK1_2", + "MONITOR_IMUX10_1", + "MONITOR_IMUX15_1", + "MONITOR_IMUX5_4", + "MONITOR_WW4C3_2", + "MONITOR_EE2BEG3_1", + "MONITOR_IMUX41_3", + "MONITOR_FAN6_3", + "MONITOR_LOGIC_OUTS_B15_1", + "MONITOR_IMUX12_3", + "MONITOR_IMUX4_2", + "MONITOR_VERT_SHORT_VAUXP2", + "MONITOR_IMUX6_3", + "MONITOR_EE2A2_3", + "MONITOR_WW2A3_1", + "MONITOR_BYP3_3", + "MONITOR_IMUX17_0", + "MONITOR_IMUX16_4", + "MONITOR_LOGIC_OUTS_B23_0", + "MONITOR_NW4A3_1", + "MONITOR_SE4BEG1_2", + "MONITOR_EE4BEG3_1", + "MONITOR_IMUX32_4", + "MONITOR_EE4BEG1_2", + "MONITOR_NW4A1_0", + "MONITOR_NE4C3_2", + "MONITOR_IMUX20_3", + "MONITOR_LH11_4", + "MONITOR_IMUX45_3", + "MONITOR_SW4A0_3", + "MONITOR_LH11_1", + "MONITOR_SE2A3_3", + "MONITOR_SE4C2_1", + "MONITOR_NE4C1_4", + "MONITOR_LH7_4", + "MONITOR_LOGIC_OUTS_B11_3", + "MONITOR_FAN4_2", + "MONITOR_EE4A2_2", + "MONITOR_EE4BEG2_2", + "MONITOR_IMUX46_3", + "MONITOR_NE4C0_3", + "MONITOR_SW4END1_2", + "MONITOR_LOGIC_OUTS_B8_1", + "MONITOR_EE4B1_4", + "MONITOR_IMUX47_2", + "MONITOR_LOGIC_OUTS_B15_3", + "MONITOR_IMUX37_0", + "MONITOR_SW2A2_0", + "MONITOR_SE4C2_4", + "MONITOR_WR1END1_4", + "MONITOR_ER1BEG2_4", + "MONITOR_IMUX41_4", + "MONITOR_EE2BEG0_1", + "MONITOR_WW4A2_2", + "MONITOR_SW4A0_2", + "MONITOR_IMUX16_2", + "MONITOR_IMUX46_2", + "MONITOR_LOGIC_OUTS_B11_1", + "MONITOR_IMUX8_1", + "MONITOR_IMUX0_0", + "MONITOR_IMUX43_0", + "MONITOR_IMUX24_2", + "MONITOR_LOGIC_OUTS_B16_4", + "MONITOR_IMUX38_4", + "MONITOR_LOGIC_OUTS_B21_2", + "MONITOR_LH8_2", + "MONITOR_LOGIC_OUTS_B20_0", + "MONITOR_FAN4_0", + "MONITOR_IMUX38_2", + "MONITOR_IMUX14_0", + "MONITOR_FAN2_1", + "MONITOR_NE2A1_4", + "MONITOR_LH6_4", + "MONITOR_IMUX20_4", + "MONITOR_WL1END1_2", + "MONITOR_IMUX39_1", + "MONITOR_EE4C3_3", + "MONITOR_LH7_2", + "MONITOR_WW4A0_3", + "MONITOR_CLK0_4", + "MONITOR_FAN1_2", + "MONITOR_NW2A1_4", + "MONITOR_EE2A0_3", + "MONITOR_EL1BEG1_2", + "MONITOR_EE4B3_0", + "MONITOR_FAN2_2", + "MONITOR_LOGIC_OUTS_B18_0", + "MONITOR_IMUX27_2", + "MONITOR_LOGIC_OUTS_B4_2", + "MONITOR_SW4END1_0", + "MONITOR_IMUX18_0", + "MONITOR_ER1BEG0_1", + "MONITOR_NW4END0_4", + "MONITOR_LH4_2", + "MONITOR_CTRL1_2", + "MONITOR_IMUX28_3", + "MONITOR_NW4END2_1", + "MONITOR_IMUX35_3", + "MONITOR_EE4A2_0", + "MONITOR_EL1BEG0_4", + "MONITOR_WW4B2_0", + "MONITOR_SW4END0_4", + "MONITOR_IMUX14_2", + "MONITOR_NE4C0_2", + "MONITOR_NE4C1_1", + "MONITOR_WW4END2_0", + "MONITOR_EE2A0_4", + "MONITOR_LH3_1", + "MONITOR_IMUX43_4", + "MONITOR_SE2A3_4", + "MONITOR_WW4A1_0", + "MONITOR_IMUX10_2", + "MONITOR_VERT_SHORT_VAUXP13", + "MONITOR_LOGIC_OUTS_B13_1", + "MONITOR_LOGIC_OUTS_B21_1", + "MONITOR_IMUX18_3", + "MONITOR_LOGIC_OUTS_B1_1", + "MONITOR_LH4_0", + "MONITOR_NE2A0_1", + "MONITOR_FAN0_4", + "MONITOR_BYP0_2", + "MONITOR_CTRL0_3", + "MONITOR_BYP7_2", + "MONITOR_VERT_SHORT_VAUXP7", + "MONITOR_WW4B1_2", + "MONITOR_EE4B0_1", + "MONITOR_WR1END3_0", + "MONITOR_LH11_2", + "MONITOR_SE4BEG3_0", + "MONITOR_IMUX34_2", + "MONITOR_NE2A0_2", + "MONITOR_NW2A2_2", + "MONITOR_IMUX37_3", + "MONITOR_LH12_1", + "MONITOR_SW4A0_0", + "MONITOR_LH4_1", + "MONITOR_EE2A0_1", + "MONITOR_IMUX10_0", + "MONITOR_SW4END2_1", + "MONITOR_EL1BEG0_3", + "MONITOR_LOGIC_OUTS_B4_1", + "MONITOR_WW4A1_1", + "MONITOR_SW4A0_4", + "MONITOR_WW4END2_1", + "MONITOR_EE4B3_1", + "MONITOR_SE4C2_3", + "MONITOR_SE4C2_2", + "MONITOR_SW4A0_1", + "MONITOR_LOGIC_OUTS_B7_2", + "MONITOR_EE4A2_3", + "MONITOR_NW4A0_4", + "MONITOR_BLOCK_OUTS_B0_1", + "MONITOR_BYP1_1", + "MONITOR_IMUX26_1", + "MONITOR_EE2BEG2_2", + "MONITOR_WW4B2_1", + "MONITOR_IMUX17_3", + "MONITOR_LH1_1", + "MONITOR_NE4C0_1", + "MONITOR_LH11_0", + "MONITOR_IMUX33_3", + "MONITOR_IMUX11_4", + "MONITOR_IMUX45_4", + "MONITOR_NE2A0_3", + "MONITOR_EE4C3_2", + "MONITOR_WW4C1_1", + "MONITOR_IMUX24_3", + "MONITOR_NE4C2_1", + "MONITOR_LH1_4", + "MONITOR_EE2A3_4", + "MONITOR_EE4C1_1", + "MONITOR_NW4END3_2", + "MONITOR_SE2A3_2", + "MONITOR_FAN7_0", + "MONITOR_IMUX44_2", + "MONITOR_LOGIC_OUTS_B7_0", + "MONITOR_NE4C3_3", + "MONITOR_WW4END0_4", + "MONITOR_IMUX3_4", + "MONITOR_NE4BEG1_1", + "MONITOR_WW4A3_4", + "MONITOR_LH3_0", + "MONITOR_IMUX31_2", + "MONITOR_NW2A0_4", + "MONITOR_WW2A1_0", + "MONITOR_EE4B1_2", + "MONITOR_EE4C0_2", + "MONITOR_LH6_1", + "MONITOR_LOGIC_OUTS_B6_2", + "MONITOR_NW4END0_0", + "MONITOR_SW4A1_3", + "MONITOR_IMUX8_0", + "MONITOR_LOGIC_OUTS_B19_2", + "MONITOR_LOGIC_OUTS_B14_4", + "MONITOR_LOGIC_OUTS_B8_4", + "MONITOR_LOGIC_OUTS_B1_2", + "MONITOR_WW4A1_4", + "MONITOR_WR1END1_3", + "MONITOR_BYP1_3", + "MONITOR_EE2BEG1_4", + "MONITOR_NW4A2_0", + "MONITOR_NE2A2_1", + "MONITOR_EE4C1_2", + "MONITOR_SW2A3_4", + "MONITOR_SW2A2_3", + "MONITOR_IMUX0_1", + "MONITOR_SE2A1_0", + "MONITOR_VERT_SHORT_VAUXN13", + "MONITOR_IMUX47_4", + "MONITOR_IMUX15_0", + "MONITOR_IMUX38_3", + "MONITOR_FAN3_1", + "MONITOR_IMUX14_4", + "MONITOR_IMUX22_1", + "MONITOR_WW2END0_0", + "MONITOR_LOGIC_OUTS_B4_0", + "MONITOR_IMUX39_4", + "MONITOR_IMUX26_4", + "MONITOR_IMUX1_0", + "MONITOR_WW4END2_2", + "MONITOR_NE4BEG3_3", + "MONITOR_WW2END2_4", + "MONITOR_NW4END1_1", + "MONITOR_HORIZ_VAUXP0", + "MONITOR_LOGIC_OUTS_B17_3", + "MONITOR_EE4C1_0", + "MONITOR_LOGIC_OUTS_B18_1", + "MONITOR_BYP7_0", + "MONITOR_BYP1_0", + "MONITOR_BYP2_0", + "MONITOR_IMUX42_2", + "MONITOR_NE4C0_0", + "MONITOR_EL1BEG3_3", + "MONITOR_LH8_3", + "MONITOR_IMUX7_1", + "MONITOR_IMUX4_1", + "MONITOR_IMUX23_2", + "MONITOR_VERT_SHORT_VAUXP9", + "MONITOR_WW4END1_2", + "MONITOR_BYP7_3", + "MONITOR_EE2A1_1", + "MONITOR_NE4BEG3_2", + "MONITOR_WW2A0_3", + "MONITOR_IMUX35_0", + "MONITOR_IMUX27_3", + "MONITOR_EE4BEG1_0", + "MONITOR_ER1BEG0_2", + "MONITOR_CLK0_0", + "MONITOR_IMUX32_2", + "MONITOR_EE4A0_4", + "MONITOR_IMUX39_2", + "MONITOR_EE4B2_4", + "MONITOR_WL1END1_1", + "MONITOR_WW4C2_2", + "MONITOR_LOGIC_OUTS_B14_1", + "MONITOR_LOGIC_OUTS_B9_0", + "MONITOR_LH7_1", + "MONITOR_SW4END0_1", + "MONITOR_EL1BEG2_4", + "MONITOR_ER1BEG1_4", + "MONITOR_BYP0_1", + "MONITOR_LOGIC_OUTS_B16_1", + "MONITOR_EE2A2_2", + "MONITOR_SW4A3_0", + "MONITOR_WW2END2_2", + "MONITOR_BYP5_1", + "MONITOR_FAN4_1", + "MONITOR_LOGIC_OUTS_B13_4", + "MONITOR_LOGIC_OUTS_B21_4", + "MONITOR_ER1BEG2_2", + "MONITOR_NE4BEG2_1", + "MONITOR_VERT_SHORT_VAUXP4", + "MONITOR_NW2A2_0", + "MONITOR_WW4B3_4", + "MONITOR_WR1END1_2", + "MONITOR_CTRL1_3", + "MONITOR_LOGIC_OUTS_B3_1", + "MONITOR_LH8_1", + "MONITOR_IMUX35_1", + "MONITOR_LOGIC_OUTS_B2_4", + "MONITOR_BLOCK_OUTS_B3_3", + "MONITOR_NW4A3_4", + "MONITOR_IMUX9_1", + "MONITOR_FAN1_3", + "MONITOR_IMUX11_1", + "MONITOR_WW4A1_2", + "MONITOR_SE4BEG1_0", + "MONITOR_WW4B3_1", + "MONITOR_FAN7_4", + "MONITOR_WW4A0_4", + "MONITOR_LH2_2", + "MONITOR_BYP2_3", + "MONITOR_IMUX1_1", + "MONITOR_WW2A1_4", + "MONITOR_EE4A1_3", + "MONITOR_BYP3_4", + "MONITOR_IMUX11_0", + "MONITOR_WW2END0_1", + "MONITOR_EE2BEG2_4", + "MONITOR_IMUX6_0", + "MONITOR_IMUX10_4", + "MONITOR_IMUX12_4", + "MONITOR_IMUX1_2", + "MONITOR_IMUX25_2", + "MONITOR_VERT_SHORT_VAUXP10", + "MONITOR_BYP7_4", + "MONITOR_LOGIC_OUTS_B6_3", + "MONITOR_EE4A1_1", + "MONITOR_IMUX5_0", + "MONITOR_LOGIC_OUTS_B20_2", + "MONITOR_WL1END2_4", + "MONITOR_SW2A0_1", + "MONITOR_WW4B2_2", + "MONITOR_WW2END2_3", + "MONITOR_BLOCK_OUTS_B1_3", + "MONITOR_WR1END2_0", + "MONITOR_LH9_4", + "MONITOR_IMUX7_0", + "MONITOR_NW4A0_3", + "MONITOR_WW4B1_1", + "MONITOR_IMUX15_3", + "MONITOR_EE4A3_0", + "MONITOR_NE2A2_3", + "MONITOR_VERT_SHORT_VAUXN1", + "MONITOR_FAN0_3", + "MONITOR_IMUX25_3", + "MONITOR_SE4C0_3", + "MONITOR_BYP1_4", + "MONITOR_LH3_4", + "MONITOR_FAN0_0", + "MONITOR_EE2BEG0_4", + "MONITOR_LH10_2", + "MONITOR_IMUX44_0", + "MONITOR_LH10_0", + "MONITOR_IMUX7_4", + "MONITOR_NE2A0_0", + "MONITOR_SW4END2_2", + "MONITOR_ER1BEG1_2", + "MONITOR_FAN3_0", + "MONITOR_LOGIC_OUTS_B14_3", + "MONITOR_SE4C1_4", + "MONITOR_IMUX41_0", + "MONITOR_NE4C2_0", + "MONITOR_NW2A3_4", + "MONITOR_LH5_2", + "MONITOR_WR1END3_4", + "MONITOR_LOGIC_OUTS_B3_2", + "MONITOR_EL1BEG0_2", + "MONITOR_VERT_SHORT_VAUXN12", + "MONITOR_SW4END3_1", + "MONITOR_EE4C3_1", + "MONITOR_WW4END1_3", + "MONITOR_IMUX7_3", + "MONITOR_IMUX13_1", + "MONITOR_LH9_3", + "MONITOR_IMUX11_3", + "MONITOR_EL1BEG3_1", + "MONITOR_SW4A1_0", + "MONITOR_IMUX2_1", + "MONITOR_IMUX22_4", + "MONITOR_FAN5_0", + "MONITOR_LOGIC_OUTS_B11_4", + "MONITOR_EE4A3_2", + "MONITOR_LH7_3", + "MONITOR_IMUX26_3", + "MONITOR_WW4C2_3", + "MONITOR_EE4BEG2_3", + "MONITOR_NW4END1_4", + "MONITOR_EL1BEG2_1", + "MONITOR_NW4A1_4", + "MONITOR_VERT_SHORT_VAUXN9", + "MONITOR_LOGIC_OUTS_B10_1", + "MONITOR_SW2A1_4", + "MONITOR_BYP6_2", + "MONITOR_NE2A3_4", + "MONITOR_WW4A0_1", + "MONITOR_WR1END0_2", + "MONITOR_EE4B0_4", + "MONITOR_FAN3_4", + "MONITOR_IMUX45_0", + "MONITOR_IMUX20_1", + "MONITOR_EE4A0_2", + "MONITOR_CTRL0_2", + "MONITOR_EE4C2_1", + "MONITOR_SE4BEG3_4", + "MONITOR_VERT_SHORT_VAUXP1", + "MONITOR_IMUX43_3", + "MONITOR_NE4BEG3_0", + "MONITOR_NW2A1_1", + "MONITOR_LOGIC_OUTS_B6_1", + "MONITOR_WW4C2_4", + "MONITOR_WW4B3_2", + "MONITOR_SW4A2_0", + "MONITOR_NW4A2_4", + "MONITOR_WW2END0_2", + "MONITOR_SE4BEG1_1", + "MONITOR_WW4B2_4", + "MONITOR_IMUX19_2", + "MONITOR_IMUX8_3", + "MONITOR_IMUX19_1", + "MONITOR_IMUX36_4", + "MONITOR_NW2A1_2", + "MONITOR_SW4A2_3", + "MONITOR_SW4A1_1", + "MONITOR_EE4B3_4", + "MONITOR_LOGIC_OUTS_B18_4", + "MONITOR_VERT_SHORT_VAUXN3", + "MONITOR_LOGIC_OUTS_B13_0", + "MONITOR_WW4A1_3", + "MONITOR_NW4END2_0", + "MONITOR_EE4B0_3", + "MONITOR_EE4BEG2_4", + "MONITOR_CLK1_4", + "MONITOR_SW4END0_3", + "MONITOR_BYP6_0", + "MONITOR_IMUX20_0", + "MONITOR_VERT_SHORT_VAUXP5", + "MONITOR_ER1BEG1_1", + "MONITOR_SE4BEG2_4", + "MONITOR_EE2BEG3_3", + "MONITOR_IMUX21_0", + "MONITOR_WW4B3_0", + "MONITOR_IMUX19_4", + "MONITOR_NE2A2_0", + "MONITOR_LOGIC_OUTS_B4_3", + "MONITOR_FAN7_2", + "MONITOR_IMUX15_4", + "MONITOR_WL1END0_1", + "MONITOR_SE2A0_0", + "MONITOR_WR1END3_3", + "MONITOR_WL1END3_2", + "MONITOR_IMUX44_1", + "MONITOR_SE2A1_2", + "MONITOR_EE2BEG1_2", + "MONITOR_BYP0_3", + "MONITOR_NE4C2_4", + "MONITOR_WW4B2_3", + "MONITOR_SE4BEG2_3", + "MONITOR_SE4BEG0_1", + "MONITOR_LOGIC_OUTS_B17_1", + "MONITOR_IMUX38_0", + "MONITOR_LH10_4", + "MONITOR_EE2A2_1", + "MONITOR_FAN5_4", + "MONITOR_LOGIC_OUTS_B20_4", + "MONITOR_BYP4_1", + "MONITOR_NW4A0_1", + "MONITOR_LOGIC_OUTS_B19_4", + "MONITOR_EE2BEG0_3", + "MONITOR_BLOCK_OUTS_B0_3", + "MONITOR_LOGIC_OUTS_B2_1", + "MONITOR_VERT_SHORT_VAUXP12", + "MONITOR_BYP4_2", + "MONITOR_WW4C1_2", + "MONITOR_VERT_SHORT_VAUXP15", + "MONITOR_WW2END1_0", + "MONITOR_EE4B0_2", + "MONITOR_EE4BEG0_2", + "MONITOR_EE4A0_3", + "MONITOR_IMUX12_0", + "MONITOR_CTRL0_0", + "MONITOR_LOGIC_OUTS_B23_4", + "MONITOR_SW2A0_0", + "MONITOR_CLK1_0", + "MONITOR_IMUX17_4", + "MONITOR_EE4BEG3_2", + "MONITOR_EE4B1_3", + "MONITOR_SE4BEG1_3", + "MONITOR_SE2A1_1", + "MONITOR_SW2A2_4", + "MONITOR_SE4C2_0", + "MONITOR_WW2A3_3", + "MONITOR_FAN6_0", + "MONITOR_NW4END3_3", + "MONITOR_IMUX42_3", + "MONITOR_WW4END1_4", + "MONITOR_IMUX40_3", + "MONITOR_FAN2_0", + "MONITOR_IMUX47_3", + "MONITOR_WW4C3_3", + "MONITOR_NE4BEG2_2", + "MONITOR_IMUX38_1", + "MONITOR_WR1END0_1", + "MONITOR_WL1END3_4", + "MONITOR_LOGIC_OUTS_B16_3", + "MONITOR_NW2A1_0", + "MONITOR_FAN6_4", + "MONITOR_WW2A1_3", + "MONITOR_WW4C0_1", + "MONITOR_LOGIC_OUTS_B20_3", + "MONITOR_EE4BEG1_4", + "MONITOR_LOGIC_OUTS_B21_3", + "MONITOR_IMUX30_1", + "MONITOR_WL1END0_0", + "MONITOR_WW4END2_4", + "MONITOR_EE2BEG0_0", + "MONITOR_IMUX32_3", + "MONITOR_WR1END0_3", + "MONITOR_BLOCK_OUTS_B1_1", + "MONITOR_WW4A3_2", + "MONITOR_EE4C1_3", + "MONITOR_ER1BEG3_4", + "MONITOR_BLOCK_OUTS_B3_4", + "MONITOR_IMUX36_3", + "MONITOR_WW4C3_4", + "MONITOR_WW4B1_3", + "MONITOR_LH8_4", + "MONITOR_WR1END2_1", + "MONITOR_IMUX14_3", + "MONITOR_LOGIC_OUTS_B22_2", + "MONITOR_NE4BEG0_3", + "MONITOR_NW4A3_0", + "MONITOR_NW2A3_1", + "MONITOR_WW4C0_4", + "MONITOR_FAN5_1", + "MONITOR_IMUX42_0", + "MONITOR_FAN3_3", + "MONITOR_WW2A1_1", + "MONITOR_LOGIC_OUTS_B19_0", + "MONITOR_CTRL0_4", + "MONITOR_EE4C2_3", + "MONITOR_WW4B0_3", + "MONITOR_SE4BEG3_1", + "MONITOR_IMUX15_2", + "MONITOR_WR1END2_4", + "MONITOR_IMUX6_4", + "MONITOR_WL1END1_4", + "MONITOR_IMUX28_4", + "MONITOR_IMUX46_4", + "MONITOR_NW4A2_1", + "MONITOR_BYP5_2", + "MONITOR_NW4END3_4", + "MONITOR_WW4A3_0", + "MONITOR_SW2A3_0", + "MONITOR_SE4BEG2_0", + "MONITOR_WW4A3_1", + "MONITOR_BLOCK_OUTS_B1_4", + "MONITOR_WR1END1_1", + "MONITOR_SW2A0_4", + "MONITOR_IMUX42_1", + "MONITOR_IMUX26_2", + "MONITOR_NW4END1_0", + "MONITOR_IMUX44_4", + "MONITOR_NE4C3_0", + "MONITOR_LOGIC_OUTS_B12_1", + "MONITOR_VERT_SHORT_VAUXN4", + "MONITOR_NW2A3_0", + "MONITOR_LOGIC_OUTS_B5_3", + "MONITOR_BLOCK_OUTS_B2_0", + "MONITOR_CTRL1_1", + "MONITOR_NE4BEG0_2", + "MONITOR_IMUX21_1", + "MONITOR_WW4END0_2", + "MONITOR_SE2A0_3", + "MONITOR_SW4END2_0", + "MONITOR_BLOCK_OUTS_B2_2", + "MONITOR_LH5_3", + "MONITOR_NE2A3_3", + "MONITOR_WW2END0_3", + "MONITOR_EE4B3_3", + "MONITOR_SE2A2_4", + "MONITOR_IMUX29_4", + "MONITOR_WW2A3_2", + "MONITOR_NE2A0_4", + "MONITOR_NW4END0_2", + "MONITOR_VERT_SHORT_VAUXN5", + "MONITOR_LOGIC_OUTS_B14_0", + "MONITOR_LH6_0", + "MONITOR_EL1BEG3_2", + "MONITOR_VERT_SHORT_VAUXN0", + "MONITOR_EE4BEG3_3", + "MONITOR_CLK1_3", + "MONITOR_BYP7_1", + "MONITOR_IMUX19_3", + "MONITOR_LOGIC_OUTS_B15_4", + "MONITOR_EE4B1_1", + "MONITOR_IMUX33_1", + "MONITOR_LH2_1", + "MONITOR_IMUX22_3", + "MONITOR_EE2A2_4", + "MONITOR_EL1BEG2_0", + "MONITOR_EE4BEG0_3", + "MONITOR_WW2A3_0", + "MONITOR_EE2A3_3", + "MONITOR_LH3_3", + "MONITOR_WW4A2_4", + "MONITOR_EE4BEG0_4", + "MONITOR_NE4BEG1_2", + "MONITOR_WW2END1_4", + "MONITOR_EE4A0_0", + "MONITOR_WL1END3_0", + "MONITOR_SW4A3_4", + "MONITOR_IMUX25_4", + "MONITOR_FAN1_4", + "MONITOR_IMUX24_1", + "MONITOR_SW4END1_3", + "MONITOR_LOGIC_OUTS_B22_4", + "MONITOR_IMUX13_2", + "MONITOR_IMUX5_2", + "MONITOR_SE4C1_2", + "MONITOR_IMUX8_2", + "MONITOR_BYP2_1", + "MONITOR_LOGIC_OUTS_B6_0", + "MONITOR_IMUX12_2", + "MONITOR_LOGIC_OUTS_B5_2", + "MONITOR_LH5_4", + "MONITOR_LOGIC_OUTS_B2_0", + "MONITOR_EE2BEG3_0", + "MONITOR_NE4BEG3_4", + "MONITOR_IMUX14_1", + "MONITOR_WW4END3_0", + "MONITOR_SE4C3_0", + "MONITOR_IMUX17_2", + "MONITOR_WW4END2_3", + "MONITOR_IMUX9_4", + "MONITOR_FAN1_0", + "MONITOR_WW2A2_0", + "MONITOR_WW2A0_1", + "MONITOR_LOGIC_OUTS_B10_0", + "MONITOR_IMUX36_1", + "MONITOR_WW4A2_1", + "MONITOR_WW2END3_3", + "MONITOR_EL1BEG3_4", + "MONITOR_EE2A1_4", + "MONITOR_EE2BEG3_4", + "MONITOR_WL1END2_2", + "MONITOR_SE2A3_0", + "MONITOR_EE4A2_4", + "MONITOR_SE4C0_2", + "MONITOR_IMUX9_2", + "MONITOR_NW4A1_3", + "MONITOR_NW2A3_2", + "MONITOR_ER1BEG2_3", + "MONITOR_SW2A1_2", + "MONITOR_IMUX2_0", + "MONITOR_WW4B1_0", + "MONITOR_WW4A2_3", + "MONITOR_SW4A3_3", + "MONITOR_SW2A3_1", + "MONITOR_IMUX3_2", + "MONITOR_WW2END1_3", + "MONITOR_CTRL1_0", + "MONITOR_IMUX47_0", + "MONITOR_SE4BEG0_0", + "MONITOR_BYP5_3", + "MONITOR_FAN6_1", + "MONITOR_IMUX40_0", + "MONITOR_WW4A3_3", + "MONITOR_FAN5_3" + ], + "pips": { + "MONITOR_TOP_FUJI2.MONITOR_HORIZ_VAUXN0->MONITOR_VERT_SHORT_VAUXN0": { + "src_wire": "MONITOR_HORIZ_VAUXN0", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_SHORT_VAUXN0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_TOP_FUJI2.MONITOR_HORIZ_VAUXN8->MONITOR_VERT_SHORT_VAUXN8": { + "src_wire": "MONITOR_HORIZ_VAUXN8", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_SHORT_VAUXN8", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_TOP_FUJI2.MONITOR_HORIZ_VAUXP0->MONITOR_VERT_SHORT_VAUXP0": { + "src_wire": "MONITOR_HORIZ_VAUXP0", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_SHORT_VAUXP0", + "is_directional": "1", + "can_invert": "0" + }, + "MONITOR_TOP_FUJI2.MONITOR_HORIZ_VAUXP8->MONITOR_VERT_SHORT_VAUXP8": { + "src_wire": "MONITOR_HORIZ_VAUXP8", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_SHORT_VAUXP8", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_NULL.json b/kintex7/tile_type_NULL.json new file mode 100644 index 0000000..a0eb51b --- /dev/null +++ b/kintex7/tile_type_NULL.json @@ -0,0 +1,8 @@ +{ + "tile_type": "NULL", + "sites": [], + "wires": [ + "DUMMYFOO" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_PCIE_BOT.json b/kintex7/tile_type_PCIE_BOT.json new file mode 100644 index 0000000..53c708d --- /dev/null +++ b/kintex7/tile_type_PCIE_BOT.json @@ -0,0 +1,23028 @@ +{ + "tile_type": "PCIE_BOT", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "PCIE", + "type": "PCIE_2_1", + "site_pins": { + "XILUNCONNOUT1": "PCIE_XILUNCONNOUT1", + "PIPETX0CHARISK1": "PCIE_PIPETX0CHARISK1", + "MIMRXRDATA58": "PCIE_MIMRXRDATA58", + "CFGPMHALTASPML0SN": "PCIE_CFGPMHALTASPML0SN", + "PMVDIVIDE0": "PCIE_PMVDIVIDE0", + "TL2ERRHDR35": "PCIE_TL2ERRHDR35", + "PIPERX7STATUS2": "PCIE_PIPERX7STATUS2", + "MIMRXRDATA19": "PCIE_MIMRXRDATA19", + "CFGMGMTDO6": "PCIE_CFGMGMTDO6", + "CFGSUBSYSID11": "PCIE_CFGSUBSYSID11", + "PIPERX5DATA7": "PCIE_PIPERX5DATA7", + "TRNRBARHIT4": "PCIE_TRNRBARHIT4", + "TRNFCNPH5": "PCIE_TRNFCNPH5", + "CFGERRAERHEADERLOG0": "PCIE_CFGERRAERHEADERLOG0", + "CFGSUBSYSID8": "PCIE_CFGSUBSYSID8", + "MIMTXRADDR5": "PCIE_MIMTXRADDR5", + "EDTCHANNELSOUT5": "PCIE_EDTCHANNELSOUT5", + "CFGDSN18": "PCIE_CFGDSN18", + "MIMRXWADDR12": "PCIE_MIMRXWADDR12", + "MIMTXWDATA30": "PCIE_MIMTXWDATA30", + "MIMTXRDATA52": "PCIE_MIMTXRDATA52", + "CFGLINKSTATUSNEGOTIATEDWIDTH1": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1", + "CFGMSGDATA10": "PCIE_CFGMSGDATA10", + "CFGERRTLPCPLHEADER30": "PCIE_CFGERRTLPCPLHEADER30", + "CFGINTERRUPTMMENABLE1": "PCIE_CFGINTERRUPTMMENABLE1", + "TRNTD61": "PCIE_TRNTD61", + "MIMTXRDATA29": "PCIE_MIMTXRDATA29", + "MIMRXWDATA4": "PCIE_MIMRXWDATA4", + "DBGVECB60": "PCIE_DBGVECB60", + "PIPETX4CHARISK1": "PCIE_PIPETX4CHARISK1", + "MIMRXRDATA20": "PCIE_MIMRXRDATA20", + "MIMRXRADDR6": "PCIE_MIMRXRADDR6", + "PIPETX4DATA1": "PCIE_PIPETX4DATA1", + "TRNFCPD7": "PCIE_TRNFCPD7", + "MIMRXWDATA33": "PCIE_MIMRXWDATA33", + "CFGMGMTDO16": "PCIE_CFGMGMTDO16", + "TRNTD121": "PCIE_TRNTD121", + "TRNRD47": "PCIE_TRNRD47", + "PLLINKUPCFGCAP": "PCIE_PLLINKUPCFGCAP", + "PLDIRECTEDLINKAUTON": "PCIE_PLDIRECTEDLINKAUTON", + "TRNRD25": "PCIE_TRNRD25", + "PIPERX4CHANISALIGNED": "PCIE_PIPERX4CHANISALIGNED", + "TRNTD108": "PCIE_TRNTD108", + "DBGVECB49": "PCIE_DBGVECB49", + "CFGDSDEVICENUMBER2": "PCIE_CFGDSDEVICENUMBER2", + "MIMTXWDATA24": "PCIE_MIMTXWDATA24", + "TRNRD126": "PCIE_TRNRD126", + "TRNTD109": "PCIE_TRNTD109", + "CFGERRTLPCPLHEADER34": "PCIE_CFGERRTLPCPLHEADER34", + "FUNCLVLRSTN": "PCIE_FUNCLVLRSTN", + "PIPERX1CHARISK1": "PCIE_PIPERX1CHARISK1", + "MIMRXWADDR1": "PCIE_MIMRXWADDR1", + "CFGDSN8": "PCIE_CFGDSN8", + "PLDBGVEC10": "PCIE_PLDBGVEC10", + "CFGERRAERHEADERLOG30": "PCIE_CFGERRAERHEADERLOG30", + "PLRECEIVEDHOTRST": "PCIE_PLRECEIVEDHOTRST", + "DBGVECB12": "PCIE_DBGVECB12", + "CFGMGMTDI20": "PCIE_CFGMGMTDI20", + "CFGDSN14": "PCIE_CFGDSN14", + "XILUNCONNOUT16": "PCIE_XILUNCONNOUT16", + "MIMRXWDATA7": "PCIE_MIMRXWDATA7", + "TRNTDLLPDATA26": "PCIE_TRNTDLLPDATA26", + "CFGERRAERHEADERLOG62": "PCIE_CFGERRAERHEADERLOG62", + "PIPERX4DATA13": "PCIE_PIPERX4DATA13", + "PIPERX3PHYSTATUS": "PCIE_PIPERX3PHYSTATUS", + "DBGVECC8": "PCIE_DBGVECC8", + "CFGDSN27": "PCIE_CFGDSN27", + "PL2DIRECTEDLSTATE0": "PCIE_PL2DIRECTEDLSTATE0", + "DBGVECA34": "PCIE_DBGVECA34", + "TRNRD85": "PCIE_TRNRD85", + "PIPETX3DATA8": "PCIE_PIPETX3DATA8", + "CFGVENDID1": "PCIE_CFGVENDID1", + "TRNTDLLPDATA12": "PCIE_TRNTDLLPDATA12", + "CFGERRURN": "PCIE_CFGERRURN", + "CFGERRAERHEADERLOG8": "PCIE_CFGERRAERHEADERLOG8", + "MIMRXWDATA12": "PCIE_MIMRXWDATA12", + "PIPERX2DATA14": "PCIE_PIPERX2DATA14", + "DBGVECA32": "PCIE_DBGVECA32", + "TL2PPMSUSPENDREQ": "PCIE_TL2PPMSUSPENDREQ", + "TRNRD44": "PCIE_TRNRD44", + "TRNRD114": "PCIE_TRNRD114", + "CFGSUBSYSVENDID8": "PCIE_CFGSUBSYSVENDID8", + "DBGVECB20": "PCIE_DBGVECB20", + "TRNTD63": "PCIE_TRNTD63", + "TRNTCFGGNT": "PCIE_TRNTCFGGNT", + "LL2SUSPENDNOW": "PCIE_LL2SUSPENDNOW", + "PIPERX6DATA5": "PCIE_PIPERX6DATA5", + "TRNRD10": "PCIE_TRNRD10", + "CFGSUBSYSID0": "PCIE_CFGSUBSYSID0", + "TRNTBUFAV5": "PCIE_TRNTBUFAV5", + "MIMTXRDATA1": "PCIE_MIMTXRDATA1", + "TRNRDLLPDATA62": "PCIE_TRNRDLLPDATA62", + "PIPECLK": "PCIE_PIPECLK", + "DBGVECA43": "PCIE_DBGVECA43", + "CFGERRAERHEADERLOG65": "PCIE_CFGERRAERHEADERLOG65", + "CFGERRAERHEADERLOG86": "PCIE_CFGERRAERHEADERLOG86", + "TRNRDLLPDATA3": "PCIE_TRNRDLLPDATA3", + "PIPERX7DATA2": "PCIE_PIPERX7DATA2", + "TL2ERRHDR54": "PCIE_TL2ERRHDR54", + "TL2ERRHDR48": "PCIE_TL2ERRHDR48", + "DBGVECB18": "PCIE_DBGVECB18", + "CFGERRAERHEADERLOG83": "PCIE_CFGERRAERHEADERLOG83", + "EDTCHANNELSIN5": "PCIE_EDTCHANNELSIN5", + "CFGAERINTERRUPTMSGNUM0": "PCIE_CFGAERINTERRUPTMSGNUM0", + "CFGERRAERHEADERLOG12": "PCIE_CFGERRAERHEADERLOG12", + "CFGPCIECAPINTERRUPTMSGNUM1": "PCIE_CFGPCIECAPINTERRUPTMSGNUM1", + "CFGERRAERHEADERLOG7": "PCIE_CFGERRAERHEADERLOG7", + "MIMRXWDATA13": "PCIE_MIMRXWDATA13", + "MIMTXRDATA43": "PCIE_MIMTXRDATA43", + "CFGINTERRUPTDO1": "PCIE_CFGINTERRUPTDO1", + "PL2RXPMSTATE0": "PCIE_PL2RXPMSTATE0", + "MIMTXWADDR9": "PCIE_MIMTXWADDR9", + "PIPERX2DATA5": "PCIE_PIPERX2DATA5", + "CFGERRAERHEADERLOG85": "PCIE_CFGERRAERHEADERLOG85", + "TRNTD111": "PCIE_TRNTD111", + "CFGERRAERHEADERLOG109": "PCIE_CFGERRAERHEADERLOG109", + "PIPERX3CHARISK0": "PCIE_PIPERX3CHARISK0", + "TRNTDSTRDY0": "PCIE_TRNTDSTRDY0", + "CFGAERINTERRUPTMSGNUM2": "PCIE_CFGAERINTERRUPTMSGNUM2", + "MIMRXWDATA43": "PCIE_MIMRXWDATA43", + "CFGPMRCVREQACKN": "PCIE_CFGPMRCVREQACKN", + "PLDBGMODE0": "PCIE_PLDBGMODE0", + "PIPETX0DATA2": "PCIE_PIPETX0DATA2", + "PIPERX0DATA11": "PCIE_PIPERX0DATA11", + "TRNRD64": "PCIE_TRNRD64", + "MIMRXWDATA9": "PCIE_MIMRXWDATA9", + "CFGTRANSACTIONTYPE": "PCIE_CFGTRANSACTIONTYPE", + "MIMRXRDATA38": "PCIE_MIMRXRDATA38", + "MIMRXRADDR4": "PCIE_MIMRXRADDR4", + "TRNTD126": "PCIE_TRNTD126", + "TRNTD58": "PCIE_TRNTD58", + "MIMRXWDATA67": "PCIE_MIMRXWDATA67", + "CFGERRINTERNALUNCORN": "PCIE_CFGERRINTERNALUNCORN", + "PIPERX0DATA4": "PCIE_PIPERX0DATA4", + "PIPETX2DATA11": "PCIE_PIPETX2DATA11", + "PLDIRECTEDLTSSMNEW0": "PCIE_PLDIRECTEDLTSSMNEW0", + "DBGVECB50": "PCIE_DBGVECB50", + "PIPETX7DATA11": "PCIE_PIPETX7DATA11", + "DBGVECA20": "PCIE_DBGVECA20", + "DRPDO2": "PCIE_DRPDO2", + "DBGVECC6": "PCIE_DBGVECC6", + "EDTCHANNELSIN7": "PCIE_EDTCHANNELSIN7", + "CFGDSN11": "PCIE_CFGDSN11", + "TRNFCSEL1": "PCIE_TRNFCSEL1", + "CFGERRAERHEADERLOG6": "PCIE_CFGERRAERHEADERLOG6", + "DBGVECA5": "PCIE_DBGVECA5", + "MIMTXRDATA2": "PCIE_MIMTXRDATA2", + "TRNRD76": "PCIE_TRNRD76", + "CFGAERECRCCHECKEN": "PCIE_CFGAERECRCCHECKEN", + "PIPETX2DATA13": "PCIE_PIPETX2DATA13", + "TRNTD39": "PCIE_TRNTD39", + "CFGERRTLPCPLHEADER39": "PCIE_CFGERRTLPCPLHEADER39", + "CFGMSGDATA5": "PCIE_CFGMSGDATA5", + "LL2SENDENTERL23": "PCIE_LL2SENDENTERL23", + "XILUNCONNOUT7": "PCIE_XILUNCONNOUT7", + "PIPERX1DATA2": "PCIE_PIPERX1DATA2", + "TRNFCCPLD6": "PCIE_TRNFCCPLD6", + "TRNRDLLPDATA59": "PCIE_TRNRDLLPDATA59", + "TRNRD35": "PCIE_TRNRD35", + "TRNRD61": "PCIE_TRNRD61", + "TRNTSTR": "PCIE_TRNTSTR", + "TL2ERRHDR50": "PCIE_TL2ERRHDR50", + "CFGERRAERHEADERLOG45": "PCIE_CFGERRAERHEADERLOG45", + "TRNFCNPD4": "PCIE_TRNFCNPD4", + "TRNRDLLPDATA10": "PCIE_TRNRDLLPDATA10", + "PIPETX0DATA1": "PCIE_PIPETX0DATA1", + "CFGMGMTBYTEENN3": "PCIE_CFGMGMTBYTEENN3", + "PIPETX7DATA8": "PCIE_PIPETX7DATA8", + "CFGMGMTDWADDR1": "PCIE_CFGMGMTDWADDR1", + "CFGMGMTDI15": "PCIE_CFGMGMTDI15", + "PIPERX4DATA14": "PCIE_PIPERX4DATA14", + "PIPERX4DATA4": "PCIE_PIPERX4DATA4", + "MIMTXWDATA7": "PCIE_MIMTXWDATA7", + "EDTCHANNELSIN8": "PCIE_EDTCHANNELSIN8", + "MIMTXWDATA17": "PCIE_MIMTXWDATA17", + "PIPERX4DATA2": "PCIE_PIPERX4DATA2", + "CFGERRAERHEADERLOG100": "PCIE_CFGERRAERHEADERLOG100", + "PIPERX5DATA6": "PCIE_PIPERX5DATA6", + "CFGDSN41": "PCIE_CFGDSN41", + "CFGDEVID12": "PCIE_CFGDEVID12", + "PIPETX1DATA1": "PCIE_PIPETX1DATA1", + "TRNTREM1": "PCIE_TRNTREM1", + "CFGMGMTDI19": "PCIE_CFGMGMTDI19", + "PIPERX7DATA14": "PCIE_PIPERX7DATA14", + "DBGVECA24": "PCIE_DBGVECA24", + "TRNTD8": "PCIE_TRNTD8", + "CFGMGMTDWADDR0": "PCIE_CFGMGMTDWADDR0", + "DBGVECB6": "PCIE_DBGVECB6", + "PIPETX5DATA12": "PCIE_PIPETX5DATA12", + "CFGDSN43": "PCIE_CFGDSN43", + "PIPETX1DATA6": "PCIE_PIPETX1DATA6", + "CFGDEVCONTROLMAXPAYLOAD2": "PCIE_CFGDEVCONTROLMAXPAYLOAD2", + "XILUNCONNOUT32": "PCIE_XILUNCONNOUT32", + "CFGDEVID6": "PCIE_CFGDEVID6", + "CFGMGMTDI1": "PCIE_CFGMGMTDI1", + "TRNRDLLPDATA58": "PCIE_TRNRDLLPDATA58", + "PIPETX5DATA5": "PCIE_PIPETX5DATA5", + "MIMTXWDATA42": "PCIE_MIMTXWDATA42", + "MIMTXRDATA24": "PCIE_MIMTXRDATA24", + "TRNTD44": "PCIE_TRNTD44", + "CFGSUBSYSID9": "PCIE_CFGSUBSYSID9", + "MIMRXWDATA38": "PCIE_MIMRXWDATA38", + "PLRXPMSTATE0": "PCIE_PLRXPMSTATE0", + "PIPETX2DATA14": "PCIE_PIPETX2DATA14", + "CFGERRTLPCPLHEADER12": "PCIE_CFGERRTLPCPLHEADER12", + "CFGERRAERHEADERLOG111": "PCIE_CFGERRAERHEADERLOG111", + "DRPDO12": "PCIE_DRPDO12", + "PIPETX5DATA6": "PCIE_PIPETX5DATA6", + "PIPERX5VALID": "PCIE_PIPERX5VALID", + "PIPERX2CHANISALIGNED": "PCIE_PIPERX2CHANISALIGNED", + "TRNRECRCERR": "PCIE_TRNRECRCERR", + "MIMTXWDATA35": "PCIE_MIMTXWDATA35", + "CFGDEVCONTROLURERRREPORTINGEN": "PCIE_CFGDEVCONTROLURERRREPORTINGEN", + "PIPERX3DATA9": "PCIE_PIPERX3DATA9", + "DBGSCLRK": "PCIE_DBGSCLRK", + "TRNTD5": "PCIE_TRNTD5", + "XILUNCONNOUT33": "PCIE_XILUNCONNOUT33", + "PMVSELECT1": "PCIE_PMVSELECT1", + "MIMTXRDATA64": "PCIE_MIMTXRDATA64", + "MIMTXWDATA26": "PCIE_MIMTXWDATA26", + "PIPETX7DATA7": "PCIE_PIPETX7DATA7", + "CFGERRTLPCPLHEADER4": "PCIE_CFGERRTLPCPLHEADER4", + "PIPERX4DATA6": "PCIE_PIPERX4DATA6", + "PIPETX0CHARISK0": "PCIE_PIPETX0CHARISK0", + "PIPETX4POWERDOWN0": "PCIE_PIPETX4POWERDOWN0", + "CFGDSN19": "PCIE_CFGDSN19", + "CFGMSGRECEIVEDERRFATAL": "PCIE_CFGMSGRECEIVEDERRFATAL", + "TL2ERRHDR38": "PCIE_TL2ERRHDR38", + "DBGVECA14": "PCIE_DBGVECA14", + "TL2ERRHDR23": "PCIE_TL2ERRHDR23", + "PLINITIALLINKWIDTH2": "PCIE_PLINITIALLINKWIDTH2", + "PIPETX4DATA14": "PCIE_PIPETX4DATA14", + "TRNTD74": "PCIE_TRNTD74", + "DBGVECA36": "PCIE_DBGVECA36", + "TRNRFCPRET": "PCIE_TRNRFCPRET", + "MIMRXWDATA60": "PCIE_MIMRXWDATA60", + "PIPERX5DATA4": "PCIE_PIPERX5DATA4", + "USERRSTN": "PCIE_USERRSTN", + "MIMRXRDATA37": "PCIE_MIMRXRDATA37", + "CFGERRMCBLOCKEDN": "PCIE_CFGERRMCBLOCKEDN", + "PIPETX2DATA6": "PCIE_PIPETX2DATA6", + "TRNRDLLPDATA19": "PCIE_TRNRDLLPDATA19", + "TRNRNPOK": "PCIE_TRNRNPOK", + "TL2ERRHDR4": "PCIE_TL2ERRHDR4", + "TRNRD95": "PCIE_TRNRD95", + "TRNTD103": "PCIE_TRNTD103", + "MIMRXRDATA12": "PCIE_MIMRXRDATA12", + "MIMRXRDATA56": "PCIE_MIMRXRDATA56", + "TRNRSRCDSC": "PCIE_TRNRSRCDSC", + "DBGVECA0": "PCIE_DBGVECA0", + "PIPERX6DATA0": "PCIE_PIPERX6DATA0", + "SCANMODEN": "PCIE_SCANMODEN", + "CFGMGMTDO23": "PCIE_CFGMGMTDO23", + "CFGROOTCONTROLPMEINTEN": "PCIE_CFGROOTCONTROLPMEINTEN", + "MIMTXRADDR0": "PCIE_MIMTXRADDR0", + "CFGINTERRUPTDI2": "PCIE_CFGINTERRUPTDI2", + "CFGSLOTCONTROLELECTROMECHILCTLPULSE": "PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE", + "TRNTDLLPDATA29": "PCIE_TRNTDLLPDATA29", + "CFGMSGRECEIVEDDEASSERTINTC": "PCIE_CFGMSGRECEIVEDDEASSERTINTC", + "PIPERX3STATUS2": "PCIE_PIPERX3STATUS2", + "CFGERRTLPCPLHEADER15": "PCIE_CFGERRTLPCPLHEADER15", + "PIPETX6DATA10": "PCIE_PIPETX6DATA10", + "MIMTXWDATA67": "PCIE_MIMTXWDATA67", + "TRNRDLLPDATA39": "PCIE_TRNRDLLPDATA39", + "XILUNCONNOUT28": "PCIE_XILUNCONNOUT28", + "TRNRBARHIT3": "PCIE_TRNRBARHIT3", + "PIPERX1CHARISK0": "PCIE_PIPERX1CHARISK0", + "CFGDSN56": "PCIE_CFGDSN56", + "MIMTXRDATA30": "PCIE_MIMTXRDATA30", + "MIMRXRDATA67": "PCIE_MIMRXRDATA67", + "CFGDSN46": "PCIE_CFGDSN46", + "CFGSUBSYSID14": "PCIE_CFGSUBSYSID14", + "CFGSUBSYSVENDID2": "PCIE_CFGSUBSYSVENDID2", + "CFGERRAERHEADERLOG58": "PCIE_CFGERRAERHEADERLOG58", + "MIMTXWDATA6": "PCIE_MIMTXWDATA6", + "PIPERX7DATA3": "PCIE_PIPERX7DATA3", + "TRNRD71": "PCIE_TRNRD71", + "CFGDSDEVICENUMBER4": "PCIE_CFGDSDEVICENUMBER4", + "TRNTD79": "PCIE_TRNTD79", + "CFGMGMTDI10": "PCIE_CFGMGMTDI10", + "PIPERX5DATA15": "PCIE_PIPERX5DATA15", + "DBGVECB53": "PCIE_DBGVECB53", + "TRNRD17": "PCIE_TRNRD17", + "TRNTD102": "PCIE_TRNTD102", + "PIPETX2DATA9": "PCIE_PIPETX2DATA9", + "PIPERX6DATA3": "PCIE_PIPERX6DATA3", + "CFGDSN25": "PCIE_CFGDSN25", + "MIMRXRDATA18": "PCIE_MIMRXRDATA18", + "CFGTRANSACTIONADDR2": "PCIE_CFGTRANSACTIONADDR2", + "MIMRXRDATA29": "PCIE_MIMRXRDATA29", + "CFGMSGDATA11": "PCIE_CFGMSGDATA11", + "PIPETX5ELECIDLE": "PCIE_PIPETX5ELECIDLE", + "MIMTXRADDR9": "PCIE_MIMTXRADDR9", + "CFGINTERRUPTDO0": "PCIE_CFGINTERRUPTDO0", + "PLPHYLNKUPN": "PCIE_PLPHYLNKUPN", + "DRPADDR1": "PCIE_DRPADDR1", + "TRNTD110": "PCIE_TRNTD110", + "TRNTBUFAV0": "PCIE_TRNTBUFAV0", + "DBGVECB2": "PCIE_DBGVECB2", + "PIPERX3CHARISK1": "PCIE_PIPERX3CHARISK1", + "PIPERX5DATA5": "PCIE_PIPERX5DATA5", + "PLLINKGEN2CAP": "PCIE_PLLINKGEN2CAP", + "MIMRXWADDR11": "PCIE_MIMRXWADDR11", + "EDTCHANNELSIN6": "PCIE_EDTCHANNELSIN6", + "TRNRD83": "PCIE_TRNRD83", + "DBGVECB11": "PCIE_DBGVECB11", + "DRPDI2": "PCIE_DRPDI2", + "DBGVECB23": "PCIE_DBGVECB23", + "CFGERRTLPCPLHEADER44": "PCIE_CFGERRTLPCPLHEADER44", + "DBGSCLRC": "PCIE_DBGSCLRC", + "TRNFCPD0": "PCIE_TRNFCPD0", + "MIMTXWDATA37": "PCIE_MIMTXWDATA37", + "CFGERRAERHEADERLOG50": "PCIE_CFGERRAERHEADERLOG50", + "CFGERRAERHEADERLOG16": "PCIE_CFGERRAERHEADERLOG16", + "MIMRXWDATA27": "PCIE_MIMRXWDATA27", + "PIPERX0CHARISK0": "PCIE_PIPERX0CHARISK0", + "PIPERX6DATA8": "PCIE_PIPERX6DATA8", + "CFGERRAERHEADERLOG91": "PCIE_CFGERRAERHEADERLOG91", + "PIPERX6DATA7": "PCIE_PIPERX6DATA7", + "PIPERX0DATA9": "PCIE_PIPERX0DATA9", + "PIPETX2DATA10": "PCIE_PIPETX2DATA10", + "PIPERX4ELECIDLE": "PCIE_PIPERX4ELECIDLE", + "CFGERRINTERNALCORN": "PCIE_CFGERRINTERNALCORN", + "PLDOWNSTREAMDEEMPHSOURCE": "PCIE_PLDOWNSTREAMDEEMPHSOURCE", + "CFGMGMTBYTEENN0": "PCIE_CFGMGMTBYTEENN0", + "PLSELLNKWIDTH1": "PCIE_PLSELLNKWIDTH1", + "PIPERX1STATUS0": "PCIE_PIPERX1STATUS0", + "PLINITIALLINKWIDTH0": "PCIE_PLINITIALLINKWIDTH0", + "DBGVECA19": "PCIE_DBGVECA19", + "PIPERX3POLARITY": "PCIE_PIPERX3POLARITY", + "MIMRXRDATA11": "PCIE_MIMRXRDATA11", + "CFGAERROOTERRCORRERRREPORTINGEN": "PCIE_CFGAERROOTERRCORRERRREPORTINGEN", + "TRNRD11": "PCIE_TRNRD11", + "MIMTXWDATA34": "PCIE_MIMTXWDATA34", + "CFGREVID7": "PCIE_CFGREVID7", + "PIPETX1ELECIDLE": "PCIE_PIPETX1ELECIDLE", + "DBGVECA63": "PCIE_DBGVECA63", + "CFGVCTCVCMAP4": "PCIE_CFGVCTCVCMAP4", + "PIPETX1DATA10": "PCIE_PIPETX1DATA10", + "CFGERRAERHEADERLOG2": "PCIE_CFGERRAERHEADERLOG2", + "DBGVECB1": "PCIE_DBGVECB1", + "DRPDI3": "PCIE_DRPDI3", + "MIMRXRDATA47": "PCIE_MIMRXRDATA47", + "PIPETX0DATA0": "PCIE_PIPETX0DATA0", + "CFGPMCSRPMEEN": "PCIE_CFGPMCSRPMEEN", + "TRNRDLLPDATA57": "PCIE_TRNRDLLPDATA57", + "TRNTDLLPDATA20": "PCIE_TRNTDLLPDATA20", + "TRNTDLLPDATA0": "PCIE_TRNTDLLPDATA0", + "TRNRD52": "PCIE_TRNRD52", + "MIMRXWDATA62": "PCIE_MIMRXWDATA62", + "DBGVECB32": "PCIE_DBGVECB32", + "PIPETX7DATA3": "PCIE_PIPETX7DATA3", + "PIPETX0COMPLIANCE": "PCIE_PIPETX0COMPLIANCE", + "TRNRD33": "PCIE_TRNRD33", + "XILUNCONNOUT27": "PCIE_XILUNCONNOUT27", + "TRNFCPD1": "PCIE_TRNFCPD1", + "PLDIRECTEDLTSSMNEW3": "PCIE_PLDIRECTEDLTSSMNEW3", + "PIPETX1DATA12": "PCIE_PIPETX1DATA12", + "TRNTDLLPDATA21": "PCIE_TRNTDLLPDATA21", + "CFGINTERRUPTDI5": "PCIE_CFGINTERRUPTDI5", + "PLLINKPARTNERGEN2SUPPORTED": "PCIE_PLLINKPARTNERGEN2SUPPORTED", + "MIMRXRDATA42": "PCIE_MIMRXRDATA42", + "CFGMSGRECEIVEDASSERTINTB": "PCIE_CFGMSGRECEIVEDASSERTINTB", + "TRNTREM0": "PCIE_TRNTREM0", + "CFGERRAERHEADERLOG110": "PCIE_CFGERRAERHEADERLOG110", + "CFGMGMTDO5": "PCIE_CFGMGMTDO5", + "CFGMGMTDI18": "PCIE_CFGMGMTDI18", + "MIMRXWDATA3": "PCIE_MIMRXWDATA3", + "CFGERRTLPCPLHEADER22": "PCIE_CFGERRTLPCPLHEADER22", + "TRNRDLLPDATA50": "PCIE_TRNRDLLPDATA50", + "CFGMSGDATA6": "PCIE_CFGMSGDATA6", + "TRNTD70": "PCIE_TRNTD70", + "PIPETX7CHARISK1": "PCIE_PIPETX7CHARISK1", + "DBGVECA35": "PCIE_DBGVECA35", + "MIMTXWDATA56": "PCIE_MIMTXWDATA56", + "MIMRXWDATA6": "PCIE_MIMRXWDATA6", + "PIPETXRCVRDET": "PCIE_PIPETXRCVRDET", + "DBGVECB16": "PCIE_DBGVECB16", + "MIMRXWDATA10": "PCIE_MIMRXWDATA10", + "MIMTXRDATA25": "PCIE_MIMTXRDATA25", + "CFGERRTLPCPLHEADER35": "PCIE_CFGERRTLPCPLHEADER35", + "TRNFCNPD10": "PCIE_TRNFCNPD10", + "DBGVECB3": "PCIE_DBGVECB3", + "MIMRXWDATA17": "PCIE_MIMRXWDATA17", + "CFGERRAERHEADERLOG93": "PCIE_CFGERRAERHEADERLOG93", + "PIPETX5DATA10": "PCIE_PIPETX5DATA10", + "CFGMGMTBYTEENN1": "PCIE_CFGMGMTBYTEENN1", + "CFGMSGDATA12": "PCIE_CFGMSGDATA12", + "TRNTD127": "PCIE_TRNTD127", + "CFGERRAERHEADERLOG22": "PCIE_CFGERRAERHEADERLOG22", + "DRPDI13": "PCIE_DRPDI13", + "CFGDEVCONTROLEXTTAGEN": "PCIE_CFGDEVCONTROLEXTTAGEN", + "CFGAERROOTERRNONFATALERRRECEIVED": "PCIE_CFGAERROOTERRNONFATALERRRECEIVED", + "CFGERRPOISONEDN": "PCIE_CFGERRPOISONEDN", + "CFGSUBSYSVENDID6": "PCIE_CFGSUBSYSVENDID6", + "DBGVECB44": "PCIE_DBGVECB44", + "PIPETX5DATA1": "PCIE_PIPETX5DATA1", + "CFGMSGRECEIVEDDEASSERTINTD": "PCIE_CFGMSGRECEIVEDDEASSERTINTD", + "CFGERRAERHEADERLOG95": "PCIE_CFGERRAERHEADERLOG95", + "MIMTXWDATA8": "PCIE_MIMTXWDATA8", + "LL2TXIDLE": "PCIE_LL2TXIDLE", + "PIPERX5CHANISALIGNED": "PCIE_PIPERX5CHANISALIGNED", + "TRNRD20": "PCIE_TRNRD20", + "MIMTXWDATA13": "PCIE_MIMTXWDATA13", + "CFGINTERRUPTMSIENABLE": "PCIE_CFGINTERRUPTMSIENABLE", + "MIMRXRDATA27": "PCIE_MIMRXRDATA27", + "TRNRD40": "PCIE_TRNRD40", + "PIPERX0ELECIDLE": "PCIE_PIPERX0ELECIDLE", + "DRPDI8": "PCIE_DRPDI8", + "MIMTXRDATA61": "PCIE_MIMTXRDATA61", + "MIMRXRDATA2": "PCIE_MIMRXRDATA2", + "PLDBGVEC5": "PCIE_PLDBGVEC5", + "CFGTRANSACTION": "PCIE_CFGTRANSACTION", + "TRNTD41": "PCIE_TRNTD41", + "CFGMGMTDI13": "PCIE_CFGMGMTDI13", + "MIMRXRDATA40": "PCIE_MIMRXRDATA40", + "MIMTXWDATA0": "PCIE_MIMTXWDATA0", + "PIPERX6DATA6": "PCIE_PIPERX6DATA6", + "TRNRD107": "PCIE_TRNRD107", + "PLDIRECTEDLINKWIDTH1": "PCIE_PLDIRECTEDLINKWIDTH1", + "TL2ERRHDR52": "PCIE_TL2ERRHDR52", + "TRNRD90": "PCIE_TRNRD90", + "DBGVECA26": "PCIE_DBGVECA26", + "CFGERRAERHEADERLOG118": "PCIE_CFGERRAERHEADERLOG118", + "PIPERX2DATA4": "PCIE_PIPERX2DATA4", + "PIPETX0DATA14": "PCIE_PIPETX0DATA14", + "MIMTXRDATA16": "PCIE_MIMTXRDATA16", + "CFGMGMTDWADDR3": "PCIE_CFGMGMTDWADDR3", + "PIPERX7DATA8": "PCIE_PIPERX7DATA8", + "PLLTSSMSTATE1": "PCIE_PLLTSSMSTATE1", + "PIPETX0DATA6": "PCIE_PIPETX0DATA6", + "CFGERRAERHEADERLOG122": "PCIE_CFGERRAERHEADERLOG122", + "CFGERRAERHEADERLOG72": "PCIE_CFGERRAERHEADERLOG72", + "CFGPORTNUMBER6": "PCIE_CFGPORTNUMBER6", + "TRNFCPD9": "PCIE_TRNFCPD9", + "TRNRBARHIT7": "PCIE_TRNRBARHIT7", + "PIPETX1DATA5": "PCIE_PIPETX1DATA5", + "TRNRD79": "PCIE_TRNRD79", + "CFGPMFORCESTATEENN": "PCIE_CFGPMFORCESTATEENN", + "TRNRD110": "PCIE_TRNRD110", + "CFGDSN61": "PCIE_CFGDSN61", + "PIPETX2DATA7": "PCIE_PIPETX2DATA7", + "CFGSUBSYSID13": "PCIE_CFGSUBSYSID13", + "DBGVECA6": "PCIE_DBGVECA6", + "CFGMGMTDWADDR6": "PCIE_CFGMGMTDWADDR6", + "CFGERRAERHEADERLOG33": "PCIE_CFGERRAERHEADERLOG33", + "TL2ERRHDR11": "PCIE_TL2ERRHDR11", + "CFGDSN33": "PCIE_CFGDSN33", + "DRPDI14": "PCIE_DRPDI14", + "PIPETX0DATA3": "PCIE_PIPETX0DATA3", + "XILUNCONNOUT14": "PCIE_XILUNCONNOUT14", + "PIPERX7CHARISK1": "PCIE_PIPERX7CHARISK1", + "CFGINTERRUPTMMENABLE2": "PCIE_CFGINTERRUPTMMENABLE2", + "CFGDSN17": "PCIE_CFGDSN17", + "CFGERRAERHEADERLOG60": "PCIE_CFGERRAERHEADERLOG60", + "CFGMGMTDO17": "PCIE_CFGMGMTDO17", + "CFGDSBUSNUMBER3": "PCIE_CFGDSBUSNUMBER3", + "MIMTXWDATA19": "PCIE_MIMTXWDATA19", + "TRNTD122": "PCIE_TRNTD122", + "PIPETX1DATA4": "PCIE_PIPETX1DATA4", + "MIMTXWDATA68": "PCIE_MIMTXWDATA68", + "CFGFORCEMPS1": "PCIE_CFGFORCEMPS1", + "TRNFCCPLH4": "PCIE_TRNFCCPLH4", + "PIPETX2DATA0": "PCIE_PIPETX2DATA0", + "MIMRXWDATA29": "PCIE_MIMRXWDATA29", + "TL2ERRHDR63": "PCIE_TL2ERRHDR63", + "PLDBGVEC3": "PCIE_PLDBGVEC3", + "CFGMSGDATA4": "PCIE_CFGMSGDATA4", + "CFGDEVCONTROLMAXREADREQ1": "PCIE_CFGDEVCONTROLMAXREADREQ1", + "CFGMGMTDO20": "PCIE_CFGMGMTDO20", + "PIPERX0DATA0": "PCIE_PIPERX0DATA0", + "PIPERX0PHYSTATUS": "PCIE_PIPERX0PHYSTATUS", + "CFGDSN30": "PCIE_CFGDSN30", + "CFGFORCEMPS0": "PCIE_CFGFORCEMPS0", + "MIMRXWDATA35": "PCIE_MIMRXWDATA35", + "MIMTXWDATA29": "PCIE_MIMTXWDATA29", + "XILUNCONNOUT10": "PCIE_XILUNCONNOUT10", + "PLLTSSMSTATE3": "PCIE_PLLTSSMSTATE3", + "TRNRD6": "PCIE_TRNRD6", + "CFGERRAERHEADERLOG25": "PCIE_CFGERRAERHEADERLOG25", + "PIPETX7DATA14": "PCIE_PIPETX7DATA14", + "PIPERX5DATA9": "PCIE_PIPERX5DATA9", + "DBGVECA37": "PCIE_DBGVECA37", + "PIPERX5CHARISK1": "PCIE_PIPERX5CHARISK1", + "CFGERRTLPCPLHEADER45": "PCIE_CFGERRTLPCPLHEADER45", + "DRPDO15": "PCIE_DRPDO15", + "CFGPORTNUMBER5": "PCIE_CFGPORTNUMBER5", + "TRNTDSTRDY3": "PCIE_TRNTDSTRDY3", + "MIMTXRDATA18": "PCIE_MIMTXRDATA18", + "TRNRDLLPDATA1": "PCIE_TRNRDLLPDATA1", + "CFGTRANSACTIONADDR6": "PCIE_CFGTRANSACTIONADDR6", + "CFGERRAERHEADERLOG112": "PCIE_CFGERRAERHEADERLOG112", + "CFGMGMTWRENN": "PCIE_CFGMGMTWRENN", + "TRNTD37": "PCIE_TRNTD37", + "TRNTDLLPDATA25": "PCIE_TRNTDLLPDATA25", + "PIPETX6DATA12": "PCIE_PIPETX6DATA12", + "TRNRD58": "PCIE_TRNRD58", + "XILUNCONNOUT3": "PCIE_XILUNCONNOUT3", + "TRNRDLLPDATA22": "PCIE_TRNRDLLPDATA22", + "CFGERRTLPCPLHEADER38": "PCIE_CFGERRTLPCPLHEADER38", + "DRPDO14": "PCIE_DRPDO14", + "CFGDEVCONTROL2ATOMICEGRESSBLOCK": "PCIE_CFGDEVCONTROL2ATOMICEGRESSBLOCK", + "CFGERRTLPCPLHEADER5": "PCIE_CFGERRTLPCPLHEADER5", + "MIMTXRDATA3": "PCIE_MIMTXRDATA3", + "PIPETX0DATA15": "PCIE_PIPETX0DATA15", + "PIPETX6DATA14": "PCIE_PIPETX6DATA14", + "PIPETX2POWERDOWN1": "PCIE_PIPETX2POWERDOWN1", + "DRPADDR2": "PCIE_DRPADDR2", + "DBGVECB59": "PCIE_DBGVECB59", + "PIPERX4DATA11": "PCIE_PIPERX4DATA11", + "MIMTXRDATA36": "PCIE_MIMTXRDATA36", + "CFGDEVID11": "PCIE_CFGDEVID11", + "TL2ERRHDR12": "PCIE_TL2ERRHDR12", + "PIPETX6DATA3": "PCIE_PIPETX6DATA3", + "PIPETX2DATA8": "PCIE_PIPETX2DATA8", + "DBGVECB30": "PCIE_DBGVECB30", + "PIPERX7DATA0": "PCIE_PIPERX7DATA0", + "CFGINTERRUPTDI1": "PCIE_CFGINTERRUPTDI1", + "PIPETX6DATA8": "PCIE_PIPETX6DATA8", + "MIMRXRDATA48": "PCIE_MIMRXRDATA48", + "CFGERRAERHEADERLOG31": "PCIE_CFGERRAERHEADERLOG31", + "PIPERX4STATUS2": "PCIE_PIPERX4STATUS2", + "PMVENABLEN": "PCIE_PMVENABLEN", + "PIPERX2DATA6": "PCIE_PIPERX2DATA6", + "TRNRD66": "PCIE_TRNRD66", + "TRNRD62": "PCIE_TRNRD62", + "TRNRBARHIT0": "PCIE_TRNRBARHIT0", + "DBGVECA42": "PCIE_DBGVECA42", + "TRNRD112": "PCIE_TRNRD112", + "MIMRXWDATA8": "PCIE_MIMRXWDATA8", + "MIMTXRDATA56": "PCIE_MIMTXRDATA56", + "MIMTXWADDR5": "PCIE_MIMTXWADDR5", + "CFGPMCSRPOWERSTATE1": "PCIE_CFGPMCSRPOWERSTATE1", + "CFGPCIECAPINTERRUPTMSGNUM4": "PCIE_CFGPCIECAPINTERRUPTMSGNUM4", + "MIMRXRDATA21": "PCIE_MIMRXRDATA21", + "TRNTD107": "PCIE_TRNTD107", + "TRNFCNPD1": "PCIE_TRNFCNPD1", + "DBGVECB52": "PCIE_DBGVECB52", + "PIPETX2DATA15": "PCIE_PIPETX2DATA15", + "PIPERX6CHARISK1": "PCIE_PIPERX6CHARISK1", + "PIPETX4DATA2": "PCIE_PIPETX4DATA2", + "DBGVECA8": "PCIE_DBGVECA8", + "TRNRDLLPDATA41": "PCIE_TRNRDLLPDATA41", + "CFGLINKCONTROLHWAUTOWIDTHDIS": "PCIE_CFGLINKCONTROLHWAUTOWIDTHDIS", + "CFGERRACSN": "PCIE_CFGERRACSN", + "TRNRD116": "PCIE_TRNRD116", + "CFGERRTLPCPLHEADER27": "PCIE_CFGERRTLPCPLHEADER27", + "DBGVECA39": "PCIE_DBGVECA39", + "CFGERRAERHEADERLOG114": "PCIE_CFGERRAERHEADERLOG114", + "TRNFCNPD5": "PCIE_TRNFCNPD5", + "CFGDEVCONTROL2TLPPREFIXBLOCK": "PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK", + "MIMRXWDATA36": "PCIE_MIMRXWDATA36", + "CFGDSN52": "PCIE_CFGDSN52", + "CFGVENDID2": "PCIE_CFGVENDID2", + "CFGSUBSYSVENDID11": "PCIE_CFGSUBSYSVENDID11", + "TRNFCCPLD5": "PCIE_TRNFCCPLD5", + "TRNRD99": "PCIE_TRNRD99", + "TRNTDLLPDATA14": "PCIE_TRNTDLLPDATA14", + "DBGSCLRF": "PCIE_DBGSCLRF", + "MIMTXWDATA50": "PCIE_MIMTXWDATA50", + "DRPDO9": "PCIE_DRPDO9", + "PIPERX2VALID": "PCIE_PIPERX2VALID", + "MIMTXRDATA8": "PCIE_MIMTXRDATA8", + "CFGDSN21": "PCIE_CFGDSN21", + "PIPERX4DATA3": "PCIE_PIPERX4DATA3", + "PIPETX5POWERDOWN1": "PCIE_PIPETX5POWERDOWN1", + "PIPERX3DATA8": "PCIE_PIPERX3DATA8", + "MIMTXWDATA38": "PCIE_MIMTXWDATA38", + "CFGMGMTRDWRDONEN": "PCIE_CFGMGMTRDWRDONEN", + "CFGMGMTDO12": "PCIE_CFGMGMTDO12", + "PLDIRECTEDLINKSPEED": "PCIE_PLDIRECTEDLINKSPEED", + "TRNRD41": "PCIE_TRNRD41", + "TRNRDLLPDATA40": "PCIE_TRNRDLLPDATA40", + "CFGDSN5": "PCIE_CFGDSN5", + "CFGINTERRUPTDI3": "PCIE_CFGINTERRUPTDI3", + "PLDIRECTEDLINKCHANGE0": "PCIE_PLDIRECTEDLINKCHANGE0", + "TRNRDLLPDATA36": "PCIE_TRNRDLLPDATA36", + "CFGDEVCONTROL2ATOMICREQUESTEREN": "PCIE_CFGDEVCONTROL2ATOMICREQUESTEREN", + "TL2ERRHDR29": "PCIE_TL2ERRHDR29", + "PIPETX6DATA0": "PCIE_PIPETX6DATA0", + "CFGLINKCONTROLRETRAINLINK": "PCIE_CFGLINKCONTROLRETRAINLINK", + "TRNFCPH5": "PCIE_TRNFCPH5", + "MIMRXWDATA59": "PCIE_MIMRXWDATA59", + "PIPERX5STATUS2": "PCIE_PIPERX5STATUS2", + "PIPETX3DATA10": "PCIE_PIPETX3DATA10", + "MIMTXRDATA6": "PCIE_MIMTXRDATA6", + "CFGMGMTDI24": "PCIE_CFGMGMTDI24", + "TL2ERRHDR62": "PCIE_TL2ERRHDR62", + "TRNTD97": "PCIE_TRNTD97", + "DRPDI15": "PCIE_DRPDI15", + "MIMRXWDATA47": "PCIE_MIMRXWDATA47", + "CFGDEVCONTROLCORRERRREPORTINGEN": "PCIE_CFGDEVCONTROLCORRERRREPORTINGEN", + "TRNRDLLPDATA25": "PCIE_TRNRDLLPDATA25", + "CFGSUBSYSVENDID10": "PCIE_CFGSUBSYSVENDID10", + "TRNTBUFAV1": "PCIE_TRNTBUFAV1", + "MIMTXRADDR7": "PCIE_MIMTXRADDR7", + "MIMTXRDATA13": "PCIE_MIMTXRDATA13", + "MIMTXRDATA48": "PCIE_MIMTXRDATA48", + "CFGMGMTDI4": "PCIE_CFGMGMTDI4", + "PIPETX5DATA7": "PCIE_PIPETX5DATA7", + "CFGERRAERHEADERLOG37": "PCIE_CFGERRAERHEADERLOG37", + "MIMTXWDATA27": "PCIE_MIMTXWDATA27", + "MIMTXWDATA1": "PCIE_MIMTXWDATA1", + "TRNRDLLPDATA46": "PCIE_TRNRDLLPDATA46", + "CFGMSGDATA0": "PCIE_CFGMSGDATA0", + "PIPETX3DATA9": "PCIE_PIPETX3DATA9", + "CFGVENDID6": "PCIE_CFGVENDID6", + "PIPETX3DATA4": "PCIE_PIPETX3DATA4", + "TRNRNPREQ": "PCIE_TRNRNPREQ", + "TRNTD24": "PCIE_TRNTD24", + "MIMTXWDATA48": "PCIE_MIMTXWDATA48", + "MIMRXRDATA8": "PCIE_MIMRXRDATA8", + "CFGERRAERHEADERLOG26": "PCIE_CFGERRAERHEADERLOG26", + "CFGERRTLPCPLHEADER3": "PCIE_CFGERRTLPCPLHEADER3", + "TRNRD54": "PCIE_TRNRD54", + "CFGREVID2": "PCIE_CFGREVID2", + "CFGDSDEVICENUMBER1": "PCIE_CFGDSDEVICENUMBER1", + "TRNRD94": "PCIE_TRNRD94", + "PIPETX6CHARISK0": "PCIE_PIPETX6CHARISK0", + "DBGVECB62": "PCIE_DBGVECB62", + "TRNRD53": "PCIE_TRNRD53", + "CFGMSGRECEIVEDERRNONFATAL": "PCIE_CFGMSGRECEIVEDERRNONFATAL", + "CFGINTERRUPTN": "PCIE_CFGINTERRUPTN", + "TRNRDLLPDATA38": "PCIE_TRNRDLLPDATA38", + "TRNRD19": "PCIE_TRNRD19", + "XILUNCONNOUT17": "PCIE_XILUNCONNOUT17", + "TRNFCNPH1": "PCIE_TRNFCNPH1", + "DRPDO11": "PCIE_DRPDO11", + "CFGDSN58": "PCIE_CFGDSN58", + "CFGLINKSTATUSNEGOTIATEDWIDTH3": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3", + "PIPERX6DATA4": "PCIE_PIPERX6DATA4", + "CFGERRTLPCPLHEADER43": "PCIE_CFGERRTLPCPLHEADER43", + "TL2ERRHDR5": "PCIE_TL2ERRHDR5", + "PIPETX2POWERDOWN0": "PCIE_PIPETX2POWERDOWN0", + "PIPERX5STATUS1": "PCIE_PIPERX5STATUS1", + "PIPERX7DATA6": "PCIE_PIPERX7DATA6", + "MIMRXWDATA51": "PCIE_MIMRXWDATA51", + "CFGSUBSYSID4": "PCIE_CFGSUBSYSID4", + "MIMTXRDATA35": "PCIE_MIMTXRDATA35", + "PL2DIRECTEDLSTATE3": "PCIE_PL2DIRECTEDLSTATE3", + "DBGVECA1": "PCIE_DBGVECA1", + "PIPETX1DATA7": "PCIE_PIPETX1DATA7", + "CFGINTERRUPTMSIXFM": "PCIE_CFGINTERRUPTMSIXFM", + "TRNRDLLPDATA21": "PCIE_TRNRDLLPDATA21", + "CFGDSN13": "PCIE_CFGDSN13", + "DBGSCLRD": "PCIE_DBGSCLRD", + "DBGVECA59": "PCIE_DBGVECA59", + "CFGERRAERHEADERLOG51": "PCIE_CFGERRAERHEADERLOG51", + "CFGMGMTRDENN": "PCIE_CFGMGMTRDENN", + "PIPETX0DATA8": "PCIE_PIPETX0DATA8", + "DBGVECA13": "PCIE_DBGVECA13", + "TRNRD92": "PCIE_TRNRD92", + "CFGDSN51": "PCIE_CFGDSN51", + "TRNTD32": "PCIE_TRNTD32", + "MIMRXRDATA62": "PCIE_MIMRXRDATA62", + "CFGPMRCVASREQL1N": "PCIE_CFGPMRCVASREQL1N", + "CFGVENDID12": "PCIE_CFGVENDID12", + "TRNTD100": "PCIE_TRNTD100", + "CFGERRAERHEADERLOG13": "PCIE_CFGERRAERHEADERLOG13", + "CFGERRAERHEADERLOG90": "PCIE_CFGERRAERHEADERLOG90", + "MIMRXRDATA46": "PCIE_MIMRXRDATA46", + "DBGVECB57": "PCIE_DBGVECB57", + "MIMTXWDATA16": "PCIE_MIMTXWDATA16", + "TRNTDLLPDATA27": "PCIE_TRNTDLLPDATA27", + "TRNRD30": "PCIE_TRNRD30", + "TL2ERRHDR0": "PCIE_TL2ERRHDR0", + "CFGERRTLPCPLHEADER13": "PCIE_CFGERRTLPCPLHEADER13", + "DBGVECC2": "PCIE_DBGVECC2", + "TRNTDLLPDATA1": "PCIE_TRNTDLLPDATA1", + "CFGERRAERHEADERLOG35": "PCIE_CFGERRAERHEADERLOG35", + "PIPERX7DATA11": "PCIE_PIPERX7DATA11", + "PIPERX2DATA10": "PCIE_PIPERX2DATA10", + "PLLTSSMSTATE0": "PCIE_PLLTSSMSTATE0", + "PIPERX3DATA5": "PCIE_PIPERX3DATA5", + "CFGERRTLPCPLHEADER20": "PCIE_CFGERRTLPCPLHEADER20", + "CFGPMFORCESTATE0": "PCIE_CFGPMFORCESTATE0", + "CFGSUBSYSID6": "PCIE_CFGSUBSYSID6", + "PIPERX2DATA1": "PCIE_PIPERX2DATA1", + "TRNTD80": "PCIE_TRNTD80", + "PIPERX1STATUS2": "PCIE_PIPERX1STATUS2", + "EDTCONFIGURATION": "PCIE_EDTCONFIGURATION", + "DRPDI10": "PCIE_DRPDI10", + "PIPETX5DATA14": "PCIE_PIPETX5DATA14", + "TRNTD52": "PCIE_TRNTD52", + "CFGINTERRUPTRDYN": "PCIE_CFGINTERRUPTRDYN", + "TRNRD120": "PCIE_TRNRD120", + "TRNFCNPD11": "PCIE_TRNFCNPD11", + "LL2SENDPMACK": "PCIE_LL2SENDPMACK", + "CFGERRAERHEADERLOG59": "PCIE_CFGERRAERHEADERLOG59", + "PIPETX6DATA15": "PCIE_PIPETX6DATA15", + "TRNTD68": "PCIE_TRNTD68", + "TRNTD13": "PCIE_TRNTD13", + "PIPETX7POWERDOWN0": "PCIE_PIPETX7POWERDOWN0", + "TRNFCCPLD2": "PCIE_TRNFCCPLD2", + "CFGMGMTDI22": "PCIE_CFGMGMTDI22", + "EDTCHANNELSOUT6": "PCIE_EDTCHANNELSOUT6", + "TRNRD77": "PCIE_TRNRD77", + "PIPERX4DATA0": "PCIE_PIPERX4DATA0", + "TRNFCCPLD3": "PCIE_TRNFCCPLD3", + "MIMTXWADDR7": "PCIE_MIMTXWADDR7", + "TL2ERRHDR31": "PCIE_TL2ERRHDR31", + "TRNFCNPD6": "PCIE_TRNFCNPD6", + "CFGPMCSRPMESTATUS": "PCIE_CFGPMCSRPMESTATUS", + "PIPERX2PHYSTATUS": "PCIE_PIPERX2PHYSTATUS", + "TRNTD18": "PCIE_TRNTD18", + "MIMRXRDATA49": "PCIE_MIMRXRDATA49", + "XILUNCONNOUT5": "PCIE_XILUNCONNOUT5", + "CFGERRTLPCPLHEADER29": "PCIE_CFGERRTLPCPLHEADER29", + "MIMTXRDATA0": "PCIE_MIMTXRDATA0", + "CFGSUBSYSID5": "PCIE_CFGSUBSYSID5", + "CFGMGMTDI28": "PCIE_CFGMGMTDI28", + "MIMTXRDATA58": "PCIE_MIMTXRDATA58", + "MIMRXRDATA31": "PCIE_MIMRXRDATA31", + "CFGVCTCVCMAP1": "PCIE_CFGVCTCVCMAP1", + "CFGERRAERHEADERLOG80": "PCIE_CFGERRAERHEADERLOG80", + "CFGMSGRECEIVEDASSERTINTA": "PCIE_CFGMSGRECEIVEDASSERTINTA", + "PIPETX4DATA15": "PCIE_PIPETX4DATA15", + "MIMRXWDATA32": "PCIE_MIMRXWDATA32", + "TRNFCPD5": "PCIE_TRNFCPD5", + "CFGMGMTDI0": "PCIE_CFGMGMTDI0", + "EDTCHANNELSIN1": "PCIE_EDTCHANNELSIN1", + "PLDIRECTEDLTSSMNEW5": "PCIE_PLDIRECTEDLTSSMNEW5", + "CFGERRTLPCPLHEADER40": "PCIE_CFGERRTLPCPLHEADER40", + "CFGDSDEVICENUMBER0": "PCIE_CFGDSDEVICENUMBER0", + "CFGERRAERHEADERLOG34": "PCIE_CFGERRAERHEADERLOG34", + "CFGLINKSTATUSCURRENTSPEED1": "PCIE_CFGLINKSTATUSCURRENTSPEED1", + "CFGDSN29": "PCIE_CFGDSN29", + "TRNRD125": "PCIE_TRNRD125", + "MIMRXRDATA3": "PCIE_MIMRXRDATA3", + "CFGCOMMANDBUSMASTERENABLE": "PCIE_CFGCOMMANDBUSMASTERENABLE", + "MIMTXWDATA41": "PCIE_MIMTXWDATA41", + "DRPDO0": "PCIE_DRPDO0", + "PIPETX3DATA7": "PCIE_PIPETX3DATA7", + "PIPERX4VALID": "PCIE_PIPERX4VALID", + "CFGERRECRCN": "PCIE_CFGERRECRCN", + "PIPERX5PHYSTATUS": "PCIE_PIPERX5PHYSTATUS", + "PIPETX3DATA1": "PCIE_PIPETX3DATA1", + "MIMTXWDATA3": "PCIE_MIMTXWDATA3", + "CFGSUBSYSVENDID5": "PCIE_CFGSUBSYSVENDID5", + "PIPERX3STATUS1": "PCIE_PIPERX3STATUS1", + "CFGVENDID14": "PCIE_CFGVENDID14", + "TRNTD73": "PCIE_TRNTD73", + "TRNTD81": "PCIE_TRNTD81", + "CFGTRANSACTIONADDR0": "PCIE_CFGTRANSACTIONADDR0", + "TRNFCPD3": "PCIE_TRNFCPD3", + "CFGDSN15": "PCIE_CFGDSN15", + "PIPERX1DATA11": "PCIE_PIPERX1DATA11", + "PIPETX2DATA4": "PCIE_PIPETX2DATA4", + "CFGMGMTWRREADONLYN": "PCIE_CFGMGMTWRREADONLYN", + "TRNRD124": "PCIE_TRNRD124", + "PLLANEREVERSALMODE0": "PCIE_PLLANEREVERSALMODE0", + "PIPERX3DATA1": "PCIE_PIPERX3DATA1", + "CFGVENDID10": "PCIE_CFGVENDID10", + "CFGREVID6": "PCIE_CFGREVID6", + "CFGDSN60": "PCIE_CFGDSN60", + "CFGERRAERHEADERLOG29": "PCIE_CFGERRAERHEADERLOG29", + "TRNFCPH4": "PCIE_TRNFCPH4", + "TRNTD84": "PCIE_TRNTD84", + "TRNRD21": "PCIE_TRNRD21", + "CFGFORCECOMMONCLOCKOFF": "PCIE_CFGFORCECOMMONCLOCKOFF", + "PIPETX6DATA7": "PCIE_PIPETX6DATA7", + "CFGDSN34": "PCIE_CFGDSN34", + "PIPERX3DATA10": "PCIE_PIPERX3DATA10", + "EDTCHANNELSIN3": "PCIE_EDTCHANNELSIN3", + "TRNRD56": "PCIE_TRNRD56", + "CFGDEVID4": "PCIE_CFGDEVID4", + "CFGERRAERHEADERLOG79": "PCIE_CFGERRAERHEADERLOG79", + "MIMTXRDATA68": "PCIE_MIMTXRDATA68", + "XILUNCONNOUT36": "PCIE_XILUNCONNOUT36", + "PLSELLNKWIDTH0": "PCIE_PLSELLNKWIDTH0", + "CFGTRANSACTIONADDR4": "PCIE_CFGTRANSACTIONADDR4", + "CFGERRAERHEADERLOG40": "PCIE_CFGERRAERHEADERLOG40", + "PIPETXMARGIN1": "PCIE_PIPETXMARGIN1", + "CFGMGMTDO22": "PCIE_CFGMGMTDO22", + "TRNTDLLPDATA3": "PCIE_TRNTDLLPDATA3", + "PIPERX5DATA11": "PCIE_PIPERX5DATA11", + "CFGERRAERHEADERLOG1": "PCIE_CFGERRAERHEADERLOG1", + "TL2ERRRXOVERFLOW": "PCIE_TL2ERRRXOVERFLOW", + "DRPCLK": "PCIE_DRPCLK", + "CFGSUBSYSID1": "PCIE_CFGSUBSYSID1", + "TRNTD125": "PCIE_TRNTD125", + "CFGINTERRUPTDO2": "PCIE_CFGINTERRUPTDO2", + "PIPERX2CHARISK0": "PCIE_PIPERX2CHARISK0", + "MIMTXWADDR2": "PCIE_MIMTXWADDR2", + "MIMTXWDATA15": "PCIE_MIMTXWDATA15", + "TRNTDLLPDSTRDY": "PCIE_TRNTDLLPDSTRDY", + "PIPERX3DATA7": "PCIE_PIPERX3DATA7", + "CFGMGMTDO4": "PCIE_CFGMGMTDO4", + "CFGMSGRECEIVEDASSERTINTC": "PCIE_CFGMSGRECEIVEDASSERTINTC", + "TRNRDLLPDATA12": "PCIE_TRNRDLLPDATA12", + "TRNTD11": "PCIE_TRNTD11", + "MIMTXWADDR3": "PCIE_MIMTXWADDR3", + "CFGERRTLPCPLHEADER2": "PCIE_CFGERRTLPCPLHEADER2", + "MIMTXRDATA59": "PCIE_MIMTXRDATA59", + "PIPERX3DATA2": "PCIE_PIPERX3DATA2", + "CFGDEVCONTROLPHANTOMEN": "PCIE_CFGDEVCONTROLPHANTOMEN", + "CFGMGMTDI7": "PCIE_CFGMGMTDI7", + "PIPERX1DATA4": "PCIE_PIPERX1DATA4", + "TLRSTN": "PCIE_TLRSTN", + "PIPETX1DATA0": "PCIE_PIPETX1DATA0", + "CFGERRTLPCPLHEADER26": "PCIE_CFGERRTLPCPLHEADER26", + "TRNLNKUP": "PCIE_TRNLNKUP", + "PIPERX6STATUS2": "PCIE_PIPERX6STATUS2", + "CFGDEVSTATUSCORRERRDETECTED": "PCIE_CFGDEVSTATUSCORRERRDETECTED", + "TL2ERRHDR10": "PCIE_TL2ERRHDR10", + "MIMRXWDATA65": "PCIE_MIMRXWDATA65", + "CFGERRAERHEADERLOG97": "PCIE_CFGERRAERHEADERLOG97", + "DLRSTN": "PCIE_DLRSTN", + "MIMTXWDATA52": "PCIE_MIMTXWDATA52", + "CFGDEVCONTROLMAXPAYLOAD0": "PCIE_CFGDEVCONTROLMAXPAYLOAD0", + "CFGERRAERHEADERLOG120": "PCIE_CFGERRAERHEADERLOG120", + "TRNRD16": "PCIE_TRNRD16", + "MIMRXWDATA63": "PCIE_MIMRXWDATA63", + "CFGVENDID7": "PCIE_CFGVENDID7", + "MIMTXRDATA31": "PCIE_MIMTXRDATA31", + "CFGMGMTDO26": "PCIE_CFGMGMTDO26", + "PIPERX0DATA12": "PCIE_PIPERX0DATA12", + "MIMRXWDATA46": "PCIE_MIMRXWDATA46", + "SYSRSTN": "PCIE_SYSRSTN", + "CFGVENDID8": "PCIE_CFGVENDID8", + "PIPERX5DATA14": "PCIE_PIPERX5DATA14", + "PIPETX3CHARISK1": "PCIE_PIPETX3CHARISK1", + "TRNRD105": "PCIE_TRNRD105", + "TRNTDLLPDATA16": "PCIE_TRNTDLLPDATA16", + "CFGERRAERHEADERLOG126": "PCIE_CFGERRAERHEADERLOG126", + "MIMRXWDATA49": "PCIE_MIMRXWDATA49", + "PIPETX2CHARISK1": "PCIE_PIPETX2CHARISK1", + "TRNTD9": "PCIE_TRNTD9", + "PIPETX6DATA5": "PCIE_PIPETX6DATA5", + "PLLTSSMSTATE2": "PCIE_PLLTSSMSTATE2", + "DBGVECA17": "PCIE_DBGVECA17", + "CFGMSGDATA15": "PCIE_CFGMSGDATA15", + "MIMRXWDATA45": "PCIE_MIMRXWDATA45", + "TRNFCCPLD4": "PCIE_TRNFCCPLD4", + "TRNRD22": "PCIE_TRNRD22", + "MIMTXREN": "PCIE_MIMTXREN", + "CFGERRTLPCPLHEADER21": "PCIE_CFGERRTLPCPLHEADER21", + "TRNRD7": "PCIE_TRNRD7", + "TRNRDLLPDATA14": "PCIE_TRNRDLLPDATA14", + "DBGSCLRA": "PCIE_DBGSCLRA", + "PIPETX4DATA10": "PCIE_PIPETX4DATA10", + "PIPERX1DATA15": "PCIE_PIPERX1DATA15", + "PLDBGVEC7": "PCIE_PLDBGVEC7", + "PIPETX3DATA13": "PCIE_PIPETX3DATA13", + "TRNTDLLPDATA18": "PCIE_TRNTDLLPDATA18", + "DBGVECA12": "PCIE_DBGVECA12", + "PIPERX6CHARISK0": "PCIE_PIPERX6CHARISK0", + "CFGERRCPLTIMEOUTN": "PCIE_CFGERRCPLTIMEOUTN", + "CFGDEVID7": "PCIE_CFGDEVID7", + "CFGLINKSTATUSNEGOTIATEDWIDTH2": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2", + "PIPETX5DATA2": "PCIE_PIPETX5DATA2", + "PLDBGMODE1": "PCIE_PLDBGMODE1", + "CFGDSBUSNUMBER7": "PCIE_CFGDSBUSNUMBER7", + "CFGMGMTDI9": "PCIE_CFGMGMTDI9", + "CFGERRTLPCPLHEADER33": "PCIE_CFGERRTLPCPLHEADER33", + "CFGERRAERHEADERLOG113": "PCIE_CFGERRAERHEADERLOG113", + "TRNRDLLPDATA34": "PCIE_TRNRDLLPDATA34", + "DRPDO6": "PCIE_DRPDO6", + "DBGVECB13": "PCIE_DBGVECB13", + "MIMTXRDATA62": "PCIE_MIMTXRDATA62", + "PIPETX4DATA8": "PCIE_PIPETX4DATA8", + "TRNTEOF": "PCIE_TRNTEOF", + "TRNTDSTRDY2": "PCIE_TRNTDSTRDY2", + "PIPETX7ELECIDLE": "PCIE_PIPETX7ELECIDLE", + "DBGVECC0": "PCIE_DBGVECC0", + "PIPETX5DATA9": "PCIE_PIPETX5DATA9", + "PIPERX4DATA5": "PCIE_PIPERX4DATA5", + "CFGVCTCVCMAP6": "PCIE_CFGVCTCVCMAP6", + "CFGINTERRUPTDO3": "PCIE_CFGINTERRUPTDO3", + "TRNTD67": "PCIE_TRNTD67", + "CFGLINKSTATUSLINKTRAINING": "PCIE_CFGLINKSTATUSLINKTRAINING", + "PIPETX6DATA13": "PCIE_PIPETX6DATA13", + "TRNTD15": "PCIE_TRNTD15", + "TRNRD88": "PCIE_TRNRD88", + "CFGERRTLPCPLHEADER47": "PCIE_CFGERRTLPCPLHEADER47", + "CFGDSN57": "PCIE_CFGDSN57", + "CFGTRANSACTIONADDR1": "PCIE_CFGTRANSACTIONADDR1", + "CFGSUBSYSVENDID15": "PCIE_CFGSUBSYSVENDID15", + "PIPERX0DATA5": "PCIE_PIPERX0DATA5", + "CFGDEVCONTROL2CPLTIMEOUTVAL2": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL2", + "PIPERX0STATUS1": "PCIE_PIPERX0STATUS1", + "PIPERX1DATA12": "PCIE_PIPERX1DATA12", + "PIPETX7DATA5": "PCIE_PIPETX7DATA5", + "CFGMSGDATA2": "PCIE_CFGMSGDATA2", + "TRNTDLLPDATA10": "PCIE_TRNTDLLPDATA10", + "PIPETX5COMPLIANCE": "PCIE_PIPETX5COMPLIANCE", + "PIPETX7DATA13": "PCIE_PIPETX7DATA13", + "PIPETX3DATA5": "PCIE_PIPETX3DATA5", + "PIPETX3COMPLIANCE": "PCIE_PIPETX3COMPLIANCE", + "DBGSCLRE": "PCIE_DBGSCLRE", + "PIPERX1PHYSTATUS": "PCIE_PIPERX1PHYSTATUS", + "PIPETX7DATA4": "PCIE_PIPETX7DATA4", + "CFGPMWAKEN": "PCIE_CFGPMWAKEN", + "CFGDSDEVICENUMBER3": "PCIE_CFGDSDEVICENUMBER3", + "MIMRXRDATA65": "PCIE_MIMRXRDATA65", + "PIPETX3ELECIDLE": "PCIE_PIPETX3ELECIDLE", + "CFGERRAERHEADERLOG107": "PCIE_CFGERRAERHEADERLOG107", + "CFGMGMTDO9": "PCIE_CFGMGMTDO9", + "DBGVECB8": "PCIE_DBGVECB8", + "TRNRD63": "PCIE_TRNRD63", + "TRNFCNPD9": "PCIE_TRNFCNPD9", + "TRNTD53": "PCIE_TRNTD53", + "MIMTXRDATA51": "PCIE_MIMTXRDATA51", + "CFGMGMTDO28": "PCIE_CFGMGMTDO28", + "MIMRXRDATA5": "PCIE_MIMRXRDATA5", + "PIPETX5DATA3": "PCIE_PIPETX5DATA3", + "TL2ERRHDR60": "PCIE_TL2ERRHDR60", + "TRNFCNPD3": "PCIE_TRNFCNPD3", + "CFGDSN42": "PCIE_CFGDSN42", + "DBGVECA4": "PCIE_DBGVECA4", + "TRNTD95": "PCIE_TRNTD95", + "DRPDO13": "PCIE_DRPDO13", + "MIMRXRDATA25": "PCIE_MIMRXRDATA25", + "TRNTD59": "PCIE_TRNTD59", + "TRNTD16": "PCIE_TRNTD16", + "PIPERX0DATA7": "PCIE_PIPERX0DATA7", + "TRNFCCPLD11": "PCIE_TRNFCCPLD11", + "CFGERRAERHEADERLOG101": "PCIE_CFGERRAERHEADERLOG101", + "DBGVECB45": "PCIE_DBGVECB45", + "CFGDSFUNCTIONNUMBER2": "PCIE_CFGDSFUNCTIONNUMBER2", + "CFGLINKCONTROLRCB": "PCIE_CFGLINKCONTROLRCB", + "XILUNCONNOUT15": "PCIE_XILUNCONNOUT15", + "PIPETX1COMPLIANCE": "PCIE_PIPETX1COMPLIANCE", + "TRNRD45": "PCIE_TRNRD45", + "PIPETX6DATA6": "PCIE_PIPETX6DATA6", + "PIPERX3DATA6": "PCIE_PIPERX3DATA6", + "CFGMSGRECEIVEDPMETOACK": "PCIE_CFGMSGRECEIVEDPMETOACK", + "CFGREVID5": "PCIE_CFGREVID5", + "DBGVECC7": "PCIE_DBGVECC7", + "PIPETX7DATA0": "PCIE_PIPETX7DATA0", + "TRNFCCPLD1": "PCIE_TRNFCCPLD1", + "PIPETX4DATA7": "PCIE_PIPETX4DATA7", + "MIMTXWADDR1": "PCIE_MIMTXWADDR1", + "CFGROOTCONTROLSYSERRCORRERREN": "PCIE_CFGROOTCONTROLSYSERRCORRERREN", + "MIMTXWDATA64": "PCIE_MIMTXWDATA64", + "TRNFCCPLH7": "PCIE_TRNFCCPLH7", + "CFGINTERRUPTDI7": "PCIE_CFGINTERRUPTDI7", + "CFGERRAERHEADERLOG69": "PCIE_CFGERRAERHEADERLOG69", + "CFGSUBSYSVENDID1": "PCIE_CFGSUBSYSVENDID1", + "MIMTXRDATA65": "PCIE_MIMTXRDATA65", + "TRNRDLLPDATA29": "PCIE_TRNRDLLPDATA29", + "TRNTD78": "PCIE_TRNTD78", + "TRNFCPH6": "PCIE_TRNFCPH6", + "PIPERX7DATA7": "PCIE_PIPERX7DATA7", + "MIMTXRDATA41": "PCIE_MIMTXRDATA41", + "CFGLINKSTATUSAUTOBANDWIDTHSTATUS": "PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS", + "PL2DIRECTEDLSTATE4": "PCIE_PL2DIRECTEDLSTATE4", + "PIPERX0POLARITY": "PCIE_PIPERX0POLARITY", + "TRNRDLLPDATA15": "PCIE_TRNRDLLPDATA15", + "PIPETX7POWERDOWN1": "PCIE_PIPETX7POWERDOWN1", + "DBGVECA29": "PCIE_DBGVECA29", + "CFGSUBSYSID2": "PCIE_CFGSUBSYSID2", + "DBGVECB47": "PCIE_DBGVECB47", + "DRPADDR3": "PCIE_DRPADDR3", + "PIPERX7PHYSTATUS": "PCIE_PIPERX7PHYSTATUS", + "DBGVECA58": "PCIE_DBGVECA58", + "TL2ERRHDR2": "PCIE_TL2ERRHDR2", + "MIMRXRDATA23": "PCIE_MIMRXRDATA23", + "MIMTXRDATA57": "PCIE_MIMTXRDATA57", + "CFGDSBUSNUMBER4": "PCIE_CFGDSBUSNUMBER4", + "TRNRDLLPDATA49": "PCIE_TRNRDLLPDATA49", + "CFGDSFUNCTIONNUMBER1": "PCIE_CFGDSFUNCTIONNUMBER1", + "CFGERRTLPCPLHEADER1": "PCIE_CFGERRTLPCPLHEADER1", + "CFGDEVSTATUSURDETECTED": "PCIE_CFGDEVSTATUSURDETECTED", + "TL2ERRHDR22": "PCIE_TL2ERRHDR22", + "TL2ERRHDR24": "PCIE_TL2ERRHDR24", + "PIPERX6DATA12": "PCIE_PIPERX6DATA12", + "EDTSINGLEBYPASSCHAIN": "PCIE_EDTSINGLEBYPASSCHAIN", + "CFGCOMMANDINTERRUPTDISABLE": "PCIE_CFGCOMMANDINTERRUPTDISABLE", + "MIMTXWDATA43": "PCIE_MIMTXWDATA43", + "MIMRXWDATA22": "PCIE_MIMRXWDATA22", + "CFGDSN0": "PCIE_CFGDSN0", + "MIMTXWADDR8": "PCIE_MIMTXWADDR8", + "PIPERX1DATA3": "PCIE_PIPERX1DATA3", + "PIPETX1DATA8": "PCIE_PIPETX1DATA8", + "CFGDSN7": "PCIE_CFGDSN7", + "CFGMGMTDO31": "PCIE_CFGMGMTDO31", + "CFGERRAERHEADERLOG61": "PCIE_CFGERRAERHEADERLOG61", + "CFGDEVID8": "PCIE_CFGDEVID8", + "MIMRXRDATA45": "PCIE_MIMRXRDATA45", + "TRNTD113": "PCIE_TRNTD113", + "CFGMGMTDO1": "PCIE_CFGMGMTDO1", + "MIMTXWDATA5": "PCIE_MIMTXWDATA5", + "CFGERRTLPCPLHEADER10": "PCIE_CFGERRTLPCPLHEADER10", + "DBGVECA47": "PCIE_DBGVECA47", + "PIPETX3CHARISK0": "PCIE_PIPETX3CHARISK0", + "TRNTERRDROP": "PCIE_TRNTERRDROP", + "TRNTD57": "PCIE_TRNTD57", + "CFGERRAERHEADERLOG94": "PCIE_CFGERRAERHEADERLOG94", + "TRNTD49": "PCIE_TRNTD49", + "CFGERRTLPCPLHEADER42": "PCIE_CFGERRTLPCPLHEADER42", + "MIMRXRADDR9": "PCIE_MIMRXRADDR9", + "DRPDI1": "PCIE_DRPDI1", + "TRNRD118": "PCIE_TRNRD118", + "PIPERX6DATA13": "PCIE_PIPERX6DATA13", + "PMVDIVIDE1": "PCIE_PMVDIVIDE1", + "TRNRD55": "PCIE_TRNRD55", + "MIMRXRDATA57": "PCIE_MIMRXRDATA57", + "CFGCOMMANDSERREN": "PCIE_CFGCOMMANDSERREN", + "TRNTCFGREQ": "PCIE_TRNTCFGREQ", + "PIPERX0DATA13": "PCIE_PIPERX0DATA13", + "TRNRDLLPDATA27": "PCIE_TRNRDLLPDATA27", + "PIPERX0CHARISK1": "PCIE_PIPERX0CHARISK1", + "DBGVECB19": "PCIE_DBGVECB19", + "TRNTD60": "PCIE_TRNTD60", + "USERCLK2": "PCIE_USERCLK2", + "CFGLINKCONTROLEXTENDEDSYNC": "PCIE_CFGLINKCONTROLEXTENDEDSYNC", + "TL2ERRHDR55": "PCIE_TL2ERRHDR55", + "TL2ERRHDR42": "PCIE_TL2ERRHDR42", + "TRNTDSTRDY1": "PCIE_TRNTDSTRDY1", + "TL2ERRHDR8": "PCIE_TL2ERRHDR8", + "TRNRSRCRDY": "PCIE_TRNRSRCRDY", + "PIPERX2STATUS1": "PCIE_PIPERX2STATUS1", + "CFGERRTLPCPLHEADER8": "PCIE_CFGERRTLPCPLHEADER8", + "LL2BADTLPERR": "PCIE_LL2BADTLPERR", + "PLTRANSMITHOTRST": "PCIE_PLTRANSMITHOTRST", + "MIMTXRDATA45": "PCIE_MIMTXRDATA45", + "MIMRXRDATA4": "PCIE_MIMRXRDATA4", + "MIMTXWADDR6": "PCIE_MIMTXWADDR6", + "CFGERRAERHEADERLOG39": "PCIE_CFGERRAERHEADERLOG39", + "DBGVECB29": "PCIE_DBGVECB29", + "DBGVECB4": "PCIE_DBGVECB4", + "MIMTXWDATA49": "PCIE_MIMTXWDATA49", + "PIPETX5DATA15": "PCIE_PIPETX5DATA15", + "PIPETX1DATA14": "PCIE_PIPETX1DATA14", + "DBGVECB24": "PCIE_DBGVECB24", + "TL2ERRHDR6": "PCIE_TL2ERRHDR6", + "TRNTDLLPDATA8": "PCIE_TRNTDLLPDATA8", + "PIPERX1VALID": "PCIE_PIPERX1VALID", + "PIPERX3VALID": "PCIE_PIPERX3VALID", + "CFGMGMTDI3": "PCIE_CFGMGMTDI3", + "CFGDEVCONTROLMAXPAYLOAD1": "PCIE_CFGDEVCONTROLMAXPAYLOAD1", + "PLDBGVEC2": "PCIE_PLDBGVEC2", + "TRNTD86": "PCIE_TRNTD86", + "TRNRD96": "PCIE_TRNRD96", + "LL2SENDENTERL1": "PCIE_LL2SENDENTERL1", + "CFGERRTLPCPLHEADER16": "PCIE_CFGERRTLPCPLHEADER16", + "PIPETX4DATA3": "PCIE_PIPETX4DATA3", + "CFGMGMTDI29": "PCIE_CFGMGMTDI29", + "MIMRXWDATA34": "PCIE_MIMRXWDATA34", + "PIPERX0STATUS0": "PCIE_PIPERX0STATUS0", + "PIPETX7DATA6": "PCIE_PIPETX7DATA6", + "CFGMGMTDWADDR9": "PCIE_CFGMGMTDWADDR9", + "TL2ERRHDR43": "PCIE_TL2ERRHDR43", + "CFGPMTURNOFFOKN": "PCIE_CFGPMTURNOFFOKN", + "MIMRXWDATA16": "PCIE_MIMRXWDATA16", + "TRNTD51": "PCIE_TRNTD51", + "PIPERX4DATA15": "PCIE_PIPERX4DATA15", + "TRNRD24": "PCIE_TRNRD24", + "TRNRD117": "PCIE_TRNRD117", + "MIMTXRDATA7": "PCIE_MIMTXRDATA7", + "MIMRXWDATA2": "PCIE_MIMRXWDATA2", + "DRPRDY": "PCIE_DRPRDY", + "CFGDSN31": "PCIE_CFGDSN31", + "PIPERX7DATA10": "PCIE_PIPERX7DATA10", + "PIPETX4DATA0": "PCIE_PIPETX4DATA0", + "PIPETX4DATA5": "PCIE_PIPETX4DATA5", + "PIPETX4DATA12": "PCIE_PIPETX4DATA12", + "MIMRXRDATA33": "PCIE_MIMRXRDATA33", + "TRNRDLLPDATA35": "PCIE_TRNRDLLPDATA35", + "CFGDSN35": "PCIE_CFGDSN35", + "TRNRDLLPDATA55": "PCIE_TRNRDLLPDATA55", + "XILUNCONNOUT6": "PCIE_XILUNCONNOUT6", + "PLDIRECTEDLINKWIDTH0": "PCIE_PLDIRECTEDLINKWIDTH0", + "MIMRXRDATA13": "PCIE_MIMRXRDATA13", + "MIMRXWDATA66": "PCIE_MIMRXWDATA66", + "TL2ERRHDR57": "PCIE_TL2ERRHDR57", + "CFGERRAERHEADERLOG98": "PCIE_CFGERRAERHEADERLOG98", + "LL2PROTOCOLERR": "PCIE_LL2PROTOCOLERR", + "CFGLINKCONTROLCOMMONCLOCK": "PCIE_CFGLINKCONTROLCOMMONCLOCK", + "DRPDI7": "PCIE_DRPDI7", + "PIPERX5ELECIDLE": "PCIE_PIPERX5ELECIDLE", + "CFGMSGDATA3": "PCIE_CFGMSGDATA3", + "CFGDSN63": "PCIE_CFGDSN63", + "DRPADDR4": "PCIE_DRPADDR4", + "PIPERX7DATA13": "PCIE_PIPERX7DATA13", + "DBGVECB43": "PCIE_DBGVECB43", + "TRNRDLLPDATA61": "PCIE_TRNRDLLPDATA61", + "CFGSUBSYSVENDID7": "PCIE_CFGSUBSYSVENDID7", + "PIPERX6STATUS0": "PCIE_PIPERX6STATUS0", + "XILUNCONNOUT37": "PCIE_XILUNCONNOUT37", + "TL2ERRHDR41": "PCIE_TL2ERRHDR41", + "DRPADDR5": "PCIE_DRPADDR5", + "CFGERRAERHEADERLOG36": "PCIE_CFGERRAERHEADERLOG36", + "MIMRXWDATA40": "PCIE_MIMRXWDATA40", + "MIMTXRADDR3": "PCIE_MIMTXRADDR3", + "TRNTD87": "PCIE_TRNTD87", + "DRPDO10": "PCIE_DRPDO10", + "PLDIRECTEDLTSSMNEW4": "PCIE_PLDIRECTEDLTSSMNEW4", + "PLDBGVEC8": "PCIE_PLDBGVEC8", + "PIPERX2DATA2": "PCIE_PIPERX2DATA2", + "MIMTXRADDR2": "PCIE_MIMTXRADDR2", + "CFGERRAERHEADERLOG10": "PCIE_CFGERRAERHEADERLOG10", + "PL2RECOVERY": "PCIE_PL2RECOVERY", + "TRNFCCPLD8": "PCIE_TRNFCCPLD8", + "MIMRXWDATA50": "PCIE_MIMRXWDATA50", + "TL2ASPMSUSPENDREQ": "PCIE_TL2ASPMSUSPENDREQ", + "CFGSUBSYSID15": "PCIE_CFGSUBSYSID15", + "MIMRXWADDR8": "PCIE_MIMRXWADDR8", + "MIMTXWDATA28": "PCIE_MIMTXWDATA28", + "MIMTXRADDR10": "PCIE_MIMTXRADDR10", + "PIPERX6DATA1": "PCIE_PIPERX6DATA1", + "TRNRD103": "PCIE_TRNRD103", + "TRNRDLLPDATA4": "PCIE_TRNRDLLPDATA4", + "TRNTSRCDSC": "PCIE_TRNTSRCDSC", + "TL2ERRHDR53": "PCIE_TL2ERRHDR53", + "CFGERRLOCKEDN": "PCIE_CFGERRLOCKEDN", + "TRNRD106": "PCIE_TRNRD106", + "PIPERX0DATA1": "PCIE_PIPERX0DATA1", + "TRNRDLLPDATA2": "PCIE_TRNRDLLPDATA2", + "CFGERRAERHEADERLOG70": "PCIE_CFGERRAERHEADERLOG70", + "PIPERX3DATA15": "PCIE_PIPERX3DATA15", + "CFGERRAERHEADERLOG99": "PCIE_CFGERRAERHEADERLOG99", + "LL2LINKSTATUS2": "PCIE_LL2LINKSTATUS2", + "CFGERRAERHEADERLOG11": "PCIE_CFGERRAERHEADERLOG11", + "PL2LINKUP": "PCIE_PL2LINKUP", + "TRNTD88": "PCIE_TRNTD88", + "MIMTXRDATA26": "PCIE_MIMTXRDATA26", + "CFGERRAERHEADERLOG49": "PCIE_CFGERRAERHEADERLOG49", + "PIPERX6DATA14": "PCIE_PIPERX6DATA14", + "EDTCHANNELSIN2": "PCIE_EDTCHANNELSIN2", + "XILUNCONNOUT35": "PCIE_XILUNCONNOUT35", + "MIMTXRDATA20": "PCIE_MIMTXRDATA20", + "CFGAERECRCGENEN": "PCIE_CFGAERECRCGENEN", + "MIMRXRADDR12": "PCIE_MIMRXRADDR12", + "PIPETXMARGIN2": "PCIE_PIPETXMARGIN2", + "CFGINTERRUPTDI4": "PCIE_CFGINTERRUPTDI4", + "MIMRXRDATA36": "PCIE_MIMRXRDATA36", + "TRNTD92": "PCIE_TRNTD92", + "MIMRXRADDR3": "PCIE_MIMRXRADDR3", + "PIPETX4POWERDOWN1": "PCIE_PIPETX4POWERDOWN1", + "MIMRXRDATA54": "PCIE_MIMRXRDATA54", + "TRNFCNPH0": "PCIE_TRNFCNPH0", + "TRNFCPD11": "PCIE_TRNFCPD11", + "PIPERX1DATA0": "PCIE_PIPERX1DATA0", + "MIMTXRDATA27": "PCIE_MIMTXRDATA27", + "CFGMGMTDI21": "PCIE_CFGMGMTDI21", + "TRNRD34": "PCIE_TRNRD34", + "LL2REPLAYROERR": "PCIE_LL2REPLAYROERR", + "MIMRXRDATA61": "PCIE_MIMRXRDATA61", + "PIPETX4DATA6": "PCIE_PIPETX4DATA6", + "CFGPORTNUMBER0": "PCIE_CFGPORTNUMBER0", + "CFGCOMMANDMEMENABLE": "PCIE_CFGCOMMANDMEMENABLE", + "PIPERX1DATA7": "PCIE_PIPERX1DATA7", + "CFGDSN59": "PCIE_CFGDSN59", + "MIMTXWDATA66": "PCIE_MIMTXWDATA66", + "CFGPMSENDPMETON": "PCIE_CFGPMSENDPMETON", + "MIMTXRDATA44": "PCIE_MIMTXRDATA44", + "TL2ERRHDR17": "PCIE_TL2ERRHDR17", + "CFGERRAERHEADERLOG56": "PCIE_CFGERRAERHEADERLOG56", + "TRNTD94": "PCIE_TRNTD94", + "PIPERX5DATA1": "PCIE_PIPERX5DATA1", + "TRNRD115": "PCIE_TRNRD115", + "PIPETX0DATA10": "PCIE_PIPETX0DATA10", + "CFGDSN12": "PCIE_CFGDSN12", + "CFGMGMTDO14": "PCIE_CFGMGMTDO14", + "MIMTXRDATA11": "PCIE_MIMTXRDATA11", + "CFGPORTNUMBER2": "PCIE_CFGPORTNUMBER2", + "PIPERX7DATA5": "PCIE_PIPERX7DATA5", + "DBGVECA21": "PCIE_DBGVECA21", + "DBGVECB51": "PCIE_DBGVECB51", + "PIPETX2COMPLIANCE": "PCIE_PIPETX2COMPLIANCE", + "TRNRDLLPDATA43": "PCIE_TRNRDLLPDATA43", + "CFGAERINTERRUPTMSGNUM3": "PCIE_CFGAERINTERRUPTMSGNUM3", + "TRNRD14": "PCIE_TRNRD14", + "MIMTXRDATA4": "PCIE_MIMTXRDATA4", + "CFGINTERRUPTMMENABLE0": "PCIE_CFGINTERRUPTMMENABLE0", + "CFGMGMTDWADDR2": "PCIE_CFGMGMTDWADDR2", + "PIPERX4DATA1": "PCIE_PIPERX4DATA1", + "MIMTXRADDR6": "PCIE_MIMTXRADDR6", + "DBGVECA45": "PCIE_DBGVECA45", + "CFGERRAERHEADERLOG44": "PCIE_CFGERRAERHEADERLOG44", + "TL2ERRHDR40": "PCIE_TL2ERRHDR40", + "MIMRXWADDR5": "PCIE_MIMRXWADDR5", + "CFGINTERRUPTDI0": "PCIE_CFGINTERRUPTDI0", + "DBGVECB15": "PCIE_DBGVECB15", + "CFGMGMTDI31": "PCIE_CFGMGMTDI31", + "CFGDSN6": "PCIE_CFGDSN6", + "PIPETX3POWERDOWN1": "PCIE_PIPETX3POWERDOWN1", + "TL2ERRHDR44": "PCIE_TL2ERRHDR44", + "PIPERX0DATA6": "PCIE_PIPERX0DATA6", + "LL2REPLAYTOERR": "PCIE_LL2REPLAYTOERR", + "USERCLK": "PCIE_USERCLK", + "PIPERX5DATA12": "PCIE_PIPERX5DATA12", + "CFGPCIECAPINTERRUPTMSGNUM0": "PCIE_CFGPCIECAPINTERRUPTMSGNUM0", + "MIMTXWDATA39": "PCIE_MIMTXWDATA39", + "CFGMGMTDI30": "PCIE_CFGMGMTDI30", + "TRNRD102": "PCIE_TRNRD102", + "PIPERX7DATA15": "PCIE_PIPERX7DATA15", + "TRNRD32": "PCIE_TRNRD32", + "PIPETX2DATA5": "PCIE_PIPETX2DATA5", + "XILUNCONNOUT18": "PCIE_XILUNCONNOUT18", + "CFGSUBSYSVENDID9": "PCIE_CFGSUBSYSVENDID9", + "DBGVECA49": "PCIE_DBGVECA49", + "TRNRD59": "PCIE_TRNRD59", + "TRNRD91": "PCIE_TRNRD91", + "MIMTXWDATA46": "PCIE_MIMTXWDATA46", + "PIPETX7DATA10": "PCIE_PIPETX7DATA10", + "PIPETX1DATA3": "PCIE_PIPETX1DATA3", + "PIPETX4COMPLIANCE": "PCIE_PIPETX4COMPLIANCE", + "TRNRD28": "PCIE_TRNRD28", + "TRNTDLLPDATA4": "PCIE_TRNTDLLPDATA4", + "TRNRD4": "PCIE_TRNRD4", + "CFGERRTLPCPLHEADER24": "PCIE_CFGERRTLPCPLHEADER24", + "MIMRXRDATA52": "PCIE_MIMRXRDATA52", + "DBGVECA61": "PCIE_DBGVECA61", + "TRNRD69": "PCIE_TRNRD69", + "CFGDSN38": "PCIE_CFGDSN38", + "DBGVECC11": "PCIE_DBGVECC11", + "DRPDI11": "PCIE_DRPDI11", + "PIPERX5DATA13": "PCIE_PIPERX5DATA13", + "CFGERRAERHEADERLOG117": "PCIE_CFGERRAERHEADERLOG117", + "TRNFCPH2": "PCIE_TRNFCPH2", + "MIMTXWDATA40": "PCIE_MIMTXWDATA40", + "PLRSTN": "PCIE_PLRSTN", + "DBGVECB7": "PCIE_DBGVECB7", + "DRPDO3": "PCIE_DRPDO3", + "MIMTXRADDR1": "PCIE_MIMTXRADDR1", + "PIPERX3DATA3": "PCIE_PIPERX3DATA3", + "TRNFCNPD7": "PCIE_TRNFCNPD7", + "TL2ERRHDR36": "PCIE_TL2ERRHDR36", + "TRNTD6": "PCIE_TRNTD6", + "PIPETX6DATA9": "PCIE_PIPETX6DATA9", + "TRNTD89": "PCIE_TRNTD89", + "TRNRD67": "PCIE_TRNRD67", + "CFGERRAERHEADERLOG125": "PCIE_CFGERRAERHEADERLOG125", + "TRNTD10": "PCIE_TRNTD10", + "PIPERX6CHANISALIGNED": "PCIE_PIPERX6CHANISALIGNED", + "CFGERRAERHEADERLOG121": "PCIE_CFGERRAERHEADERLOG121", + "CFGLINKSTATUSDLLACTIVE": "PCIE_CFGLINKSTATUSDLLACTIVE", + "MIMRXRDATA60": "PCIE_MIMRXRDATA60", + "PL2RXPMSTATE1": "PCIE_PL2RXPMSTATE1", + "PIPETX7COMPLIANCE": "PCIE_PIPETX7COMPLIANCE", + "MIMTXWDATA45": "PCIE_MIMTXWDATA45", + "TRNRD27": "PCIE_TRNRD27", + "TRNTDLLPDATA24": "PCIE_TRNTDLLPDATA24", + "CFGPORTNUMBER1": "PCIE_CFGPORTNUMBER1", + "TL2ERRHDR21": "PCIE_TL2ERRHDR21", + "CFGFORCEEXTENDEDSYNCON": "PCIE_CFGFORCEEXTENDEDSYNCON", + "MIMTXRDATA23": "PCIE_MIMTXRDATA23", + "TRNRD60": "PCIE_TRNRD60", + "PIPERX5DATA2": "PCIE_PIPERX5DATA2", + "CFGDEVCONTROL2CPLTIMEOUTVAL1": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL1", + "CFGVENDID3": "PCIE_CFGVENDID3", + "PIPETXRATE": "PCIE_PIPETXRATE", + "TRNTD85": "PCIE_TRNTD85", + "PIPETX1DATA9": "PCIE_PIPETX1DATA9", + "CFGDEVID15": "PCIE_CFGDEVID15", + "PIPETX3DATA11": "PCIE_PIPETX3DATA11", + "CFGERRAERHEADERLOG32": "PCIE_CFGERRAERHEADERLOG32", + "TL2ASPMSUSPENDCREDITCHECKOK": "PCIE_TL2ASPMSUSPENDCREDITCHECKOK", + "PIPETX0DATA9": "PCIE_PIPETX0DATA9", + "TRNFCPH7": "PCIE_TRNFCPH7", + "TRNRDLLPDATA7": "PCIE_TRNRDLLPDATA7", + "MIMTXRADDR11": "PCIE_MIMTXRADDR11", + "DBGVECB31": "PCIE_DBGVECB31", + "TRNRD97": "PCIE_TRNRD97", + "MIMRXWDATA20": "PCIE_MIMRXWDATA20", + "CFGBRIDGESERREN": "PCIE_CFGBRIDGESERREN", + "DBGVECA9": "PCIE_DBGVECA9", + "MIMRXRDATA34": "PCIE_MIMRXRDATA34", + "TL2ERRHDR61": "PCIE_TL2ERRHDR61", + "PIPERX1DATA9": "PCIE_PIPERX1DATA9", + "TL2ERRHDR39": "PCIE_TL2ERRHDR39", + "TRNTD20": "PCIE_TRNTD20", + "CFGINTERRUPTASSERTN": "PCIE_CFGINTERRUPTASSERTN", + "CFGERRAERHEADERLOG71": "PCIE_CFGERRAERHEADERLOG71", + "TRNTD54": "PCIE_TRNTD54", + "TRNFCCPLD0": "PCIE_TRNFCCPLD0", + "MIMRXRDATA35": "PCIE_MIMRXRDATA35", + "MIMTXWDATA33": "PCIE_MIMTXWDATA33", + "DBGVECB41": "PCIE_DBGVECB41", + "PIPERX7DATA1": "PCIE_PIPERX7DATA1", + "TRNRDLLPDATA42": "PCIE_TRNRDLLPDATA42", + "DBGVECB63": "PCIE_DBGVECB63", + "CFGROOTCONTROLSYSERRNONFATALERREN": "PCIE_CFGROOTCONTROLSYSERRNONFATALERREN", + "PIPERX4POLARITY": "PCIE_PIPERX4POLARITY", + "CFGDEVSTATUSFATALERRDETECTED": "PCIE_CFGDEVSTATUSFATALERRDETECTED", + "TRNFCPD10": "PCIE_TRNFCPD10", + "MIMRXWDATA53": "PCIE_MIMRXWDATA53", + "TRNFCCPLD9": "PCIE_TRNFCCPLD9", + "TRNRD57": "PCIE_TRNRD57", + "CFGDEVID0": "PCIE_CFGDEVID0", + "PIPERX0DATA15": "PCIE_PIPERX0DATA15", + "TRNRD15": "PCIE_TRNRD15", + "PIPERX2DATA12": "PCIE_PIPERX2DATA12", + "CFGDEVCONTROLENABLERO": "PCIE_CFGDEVCONTROLENABLERO", + "PIPERX0DATA10": "PCIE_PIPERX0DATA10", + "CFGMSGRECEIVEDSETSLOTPOWERLIMIT": "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT", + "TL2ERRHDR32": "PCIE_TL2ERRHDR32", + "CFGERRAERHEADERLOG17": "PCIE_CFGERRAERHEADERLOG17", + "MIMTXRDATA54": "PCIE_MIMTXRDATA54", + "TL2ERRHDR20": "PCIE_TL2ERRHDR20", + "DBGVECA44": "PCIE_DBGVECA44", + "PIPETX1DATA11": "PCIE_PIPETX1DATA11", + "CFGMGMTDWADDR5": "PCIE_CFGMGMTDWADDR5", + "CFGERRAERHEADERLOG103": "PCIE_CFGERRAERHEADERLOG103", + "PIPERX1CHANISALIGNED": "PCIE_PIPERX1CHANISALIGNED", + "MIMTXRDATA21": "PCIE_MIMTXRDATA21", + "TRNTD112": "PCIE_TRNTD112", + "CFGPORTNUMBER3": "PCIE_CFGPORTNUMBER3", + "TRNRD31": "PCIE_TRNRD31", + "PIPETX2DATA2": "PCIE_PIPETX2DATA2", + "XILUNCONNOUT30": "PCIE_XILUNCONNOUT30", + "TRNRD108": "PCIE_TRNRD108", + "MIMRXWDATA14": "PCIE_MIMRXWDATA14", + "TRNFCSEL0": "PCIE_TRNFCSEL0", + "CFGMSGDATA8": "PCIE_CFGMSGDATA8", + "XILUNCONNOUT26": "PCIE_XILUNCONNOUT26", + "TRNTD90": "PCIE_TRNTD90", + "CFGDSN62": "PCIE_CFGDSN62", + "PIPERX6DATA9": "PCIE_PIPERX6DATA9", + "PIPERX7CHANISALIGNED": "PCIE_PIPERX7CHANISALIGNED", + "CFGERRAERHEADERLOG106": "PCIE_CFGERRAERHEADERLOG106", + "DBGVECB14": "PCIE_DBGVECB14", + "PIPERX7POLARITY": "PCIE_PIPERX7POLARITY", + "CFGERRAERHEADERLOG4": "PCIE_CFGERRAERHEADERLOG4", + "TRNFCPD8": "PCIE_TRNFCPD8", + "LNKCLKEN": "PCIE_LNKCLKEN", + "PIPERX2POLARITY": "PCIE_PIPERX2POLARITY", + "PLSELLNKRATE": "PCIE_PLSELLNKRATE", + "TRNTD42": "PCIE_TRNTD42", + "CFGDSN23": "PCIE_CFGDSN23", + "CFGMSGRECEIVED": "PCIE_CFGMSGRECEIVED", + "PIPERX0VALID": "PCIE_PIPERX0VALID", + "DBGVECA2": "PCIE_DBGVECA2", + "TRNRDLLPDATA44": "PCIE_TRNRDLLPDATA44", + "MIMRXWDATA54": "PCIE_MIMRXWDATA54", + "MIMRXWDATA25": "PCIE_MIMRXWDATA25", + "CFGSUBSYSVENDID4": "PCIE_CFGSUBSYSVENDID4", + "PIPERX6DATA11": "PCIE_PIPERX6DATA11", + "CMRSTN": "PCIE_CMRSTN", + "CFGSUBSYSVENDID14": "PCIE_CFGSUBSYSVENDID14", + "PIPETX0POWERDOWN1": "PCIE_PIPETX0POWERDOWN1", + "MIMTXRDATA53": "PCIE_MIMTXRDATA53", + "TL2ERRHDR51": "PCIE_TL2ERRHDR51", + "CFGMGMTDO0": "PCIE_CFGMGMTDO0", + "MIMTXRDATA67": "PCIE_MIMTXRDATA67", + "PIPETX6DATA2": "PCIE_PIPETX6DATA2", + "CFGERRTLPCPLHEADER19": "PCIE_CFGERRTLPCPLHEADER19", + "CFGPMHALTASPML1N": "PCIE_CFGPMHALTASPML1N", + "CFGDEVSTATUSNONFATALERRDETECTED": "PCIE_CFGDEVSTATUSNONFATALERRDETECTED", + "DRPDI9": "PCIE_DRPDI9", + "DBGVECA55": "PCIE_DBGVECA55", + "CFGERRTLPCPLHEADER6": "PCIE_CFGERRTLPCPLHEADER6", + "MIMTXRDATA42": "PCIE_MIMTXRDATA42", + "TL2ERRHDR28": "PCIE_TL2ERRHDR28", + "CFGERRAERHEADERLOG41": "PCIE_CFGERRAERHEADERLOG41", + "TRNRDLLPDATA18": "PCIE_TRNRDLLPDATA18", + "DRPADDR6": "PCIE_DRPADDR6", + "TRNTD118": "PCIE_TRNTD118", + "MIMTXWADDR0": "PCIE_MIMTXWADDR0", + "MIMTXRDATA63": "PCIE_MIMTXRDATA63", + "CFGAERINTERRUPTMSGNUM4": "PCIE_CFGAERINTERRUPTMSGNUM4", + "CFGERRAERHEADERLOG115": "PCIE_CFGERRAERHEADERLOG115", + "TRNRD127": "PCIE_TRNRD127", + "DBGVECA11": "PCIE_DBGVECA11", + "PLLTSSMSTATE5": "PCIE_PLLTSSMSTATE5", + "CFGDSN1": "PCIE_CFGDSN1", + "CFGVENDID13": "PCIE_CFGVENDID13", + "TRNRD43": "PCIE_TRNRD43", + "LL2LINKSTATUS1": "PCIE_LL2LINKSTATUS1", + "TRNTDLLPDATA7": "PCIE_TRNTDLLPDATA7", + "CFGERRTLPCPLHEADER23": "PCIE_CFGERRTLPCPLHEADER23", + "CFGDSN10": "PCIE_CFGDSN10", + "CFGERRTLPCPLHEADER17": "PCIE_CFGERRTLPCPLHEADER17", + "PIPERX2DATA11": "PCIE_PIPERX2DATA11", + "CFGMGMTDO29": "PCIE_CFGMGMTDO29", + "TL2ERRHDR47": "PCIE_TL2ERRHDR47", + "DRPADDR8": "PCIE_DRPADDR8", + "CFGCOMMANDIOENABLE": "PCIE_CFGCOMMANDIOENABLE", + "TRNTD23": "PCIE_TRNTD23", + "PLDIRECTEDLTSSMSTALL": "PCIE_PLDIRECTEDLTSSMSTALL", + "TRNTD27": "PCIE_TRNTD27", + "CFGERRAERHEADERLOG9": "PCIE_CFGERRAERHEADERLOG9", + "TRNTD56": "PCIE_TRNTD56", + "PIPERX6STATUS1": "PCIE_PIPERX6STATUS1", + "MIMRXWDATA15": "PCIE_MIMRXWDATA15", + "PIPETX3DATA0": "PCIE_PIPETX3DATA0", + "CFGVCTCVCMAP3": "PCIE_CFGVCTCVCMAP3", + "MIMTXWDATA53": "PCIE_MIMTXWDATA53", + "PIPERX6POLARITY": "PCIE_PIPERX6POLARITY", + "CFGDSN26": "PCIE_CFGDSN26", + "MIMRXWDATA0": "PCIE_MIMRXWDATA0", + "PIPETX4DATA9": "PCIE_PIPETX4DATA9", + "TRNTD76": "PCIE_TRNTD76", + "MIMTXRDATA55": "PCIE_MIMTXRDATA55", + "CFGERRTLPCPLHEADER9": "PCIE_CFGERRTLPCPLHEADER9", + "CFGERRTLPCPLHEADER46": "PCIE_CFGERRTLPCPLHEADER46", + "DBGVECC4": "PCIE_DBGVECC4", + "CFGLINKSTATUSCURRENTSPEED0": "PCIE_CFGLINKSTATUSCURRENTSPEED0", + "CFGERRAERHEADERLOG19": "PCIE_CFGERRAERHEADERLOG19", + "TL2ERRHDR15": "PCIE_TL2ERRHDR15", + "CFGVENDID15": "PCIE_CFGVENDID15", + "CFGERRAERHEADERLOG119": "PCIE_CFGERRAERHEADERLOG119", + "CFGMGMTWRRW1CASRWN": "PCIE_CFGMGMTWRRW1CASRWN", + "TRNTD64": "PCIE_TRNTD64", + "PIPERX1DATA8": "PCIE_PIPERX1DATA8", + "CFGINTERRUPTDI6": "PCIE_CFGINTERRUPTDI6", + "DBGVECA15": "PCIE_DBGVECA15", + "MIMTXWDATA51": "PCIE_MIMTXWDATA51", + "MIMRXWADDR7": "PCIE_MIMRXWADDR7", + "TRNRD37": "PCIE_TRNRD37", + "TRNRD49": "PCIE_TRNRD49", + "TRNTD65": "PCIE_TRNTD65", + "PIPETX0DATA13": "PCIE_PIPETX0DATA13", + "TRNFCPD2": "PCIE_TRNFCPD2", + "CFGINTERRUPTDO4": "PCIE_CFGINTERRUPTDO4", + "CFGMGMTDWADDR4": "PCIE_CFGMGMTDWADDR4", + "MIMTXRDATA37": "PCIE_MIMTXRDATA37", + "PIPETX0DATA12": "PCIE_PIPETX0DATA12", + "XILUNCONNOUT12": "PCIE_XILUNCONNOUT12", + "PIPETX7DATA1": "PCIE_PIPETX7DATA1", + "CFGMGMTDI5": "PCIE_CFGMGMTDI5", + "TRNTD7": "PCIE_TRNTD7", + "MIMRXWADDR6": "PCIE_MIMRXWADDR6", + "CFGERRAERHEADERLOG3": "PCIE_CFGERRAERHEADERLOG3", + "PIPERX7STATUS1": "PCIE_PIPERX7STATUS1", + "MIMRXWADDR9": "PCIE_MIMRXWADDR9", + "TRNTD22": "PCIE_TRNTD22", + "TRNTD123": "PCIE_TRNTD123", + "CFGERRCPLRDYN": "PCIE_CFGERRCPLRDYN", + "PIPERX7ELECIDLE": "PCIE_PIPERX7ELECIDLE", + "PIPETX3DATA2": "PCIE_PIPETX3DATA2", + "DBGVECB10": "PCIE_DBGVECB10", + "CFGMSGRECEIVEDPMPME": "PCIE_CFGMSGRECEIVEDPMPME", + "TRNTSRCRDY": "PCIE_TRNTSRCRDY", + "PIPERX4DATA9": "PCIE_PIPERX4DATA9", + "CFGVENDID0": "PCIE_CFGVENDID0", + "EDTUPDATE": "PCIE_EDTUPDATE", + "MIMRXRDATA28": "PCIE_MIMRXRDATA28", + "CFGDSFUNCTIONNUMBER0": "PCIE_CFGDSFUNCTIONNUMBER0", + "CFGMGMTDO24": "PCIE_CFGMGMTDO24", + "CFGDEVID5": "PCIE_CFGDEVID5", + "DBGVECB42": "PCIE_DBGVECB42", + "PIPETX1CHARISK1": "PCIE_PIPETX1CHARISK1", + "TRNRDLLPSRCRDY1": "PCIE_TRNRDLLPSRCRDY1", + "CFGERRTLPCPLHEADER18": "PCIE_CFGERRTLPCPLHEADER18", + "MIMRXWDATA44": "PCIE_MIMRXWDATA44", + "PLDBGVEC4": "PCIE_PLDBGVEC4", + "PL2L0REQ": "PCIE_PL2L0REQ", + "MIMRXRDATA22": "PCIE_MIMRXRDATA22", + "LL2RECEIVERERR": "PCIE_LL2RECEIVERERR", + "PIPERX6DATA15": "PCIE_PIPERX6DATA15", + "PIPERX4STATUS1": "PCIE_PIPERX4STATUS1", + "CFGDEVID3": "PCIE_CFGDEVID3", + "MIMTXRDATA40": "PCIE_MIMTXRDATA40", + "TRNFCNPD0": "PCIE_TRNFCNPD0", + "CFGPMRCVENTERL1N": "PCIE_CFGPMRCVENTERL1N", + "CFGDSN22": "PCIE_CFGDSN22", + "PLTXPMSTATE2": "PCIE_PLTXPMSTATE2", + "MIMTXRADDR8": "PCIE_MIMTXRADDR8", + "TRNTD19": "PCIE_TRNTD19", + "TRNFCNPD8": "PCIE_TRNFCNPD8", + "CFGVENDID4": "PCIE_CFGVENDID4", + "MIMRXWDATA41": "PCIE_MIMRXWDATA41", + "CFGINTERRUPTDO6": "PCIE_CFGINTERRUPTDO6", + "MIMRXRADDR1": "PCIE_MIMRXRADDR1", + "CFGMGMTDO2": "PCIE_CFGMGMTDO2", + "MIMRXRDATA1": "PCIE_MIMRXRDATA1", + "PIPERX3DATA12": "PCIE_PIPERX3DATA12", + "MIMTXWDATA61": "PCIE_MIMTXWDATA61", + "CFGERRTLPCPLHEADER36": "PCIE_CFGERRTLPCPLHEADER36", + "CFGERRAERHEADERLOG88": "PCIE_CFGERRAERHEADERLOG88", + "DBGVECB34": "PCIE_DBGVECB34", + "DBGMODE0": "PCIE_DBGMODE0", + "TRNTECRCGEN": "PCIE_TRNTECRCGEN", + "TRNTSOF": "PCIE_TRNTSOF", + "CFGERRCPLABORTN": "PCIE_CFGERRCPLABORTN", + "TRNTD98": "PCIE_TRNTD98", + "TRNTD105": "PCIE_TRNTD105", + "CFGDSBUSNUMBER5": "PCIE_CFGDSBUSNUMBER5", + "PIPETX0DATA5": "PCIE_PIPETX0DATA5", + "CFGERRNORECOVERYN": "PCIE_CFGERRNORECOVERYN", + "CFGROOTCONTROLSYSERRFATALERREN": "PCIE_CFGROOTCONTROLSYSERRFATALERREN", + "CFGDEVCONTROLAUXPOWEREN": "PCIE_CFGDEVCONTROLAUXPOWEREN", + "PIPETX7DATA12": "PCIE_PIPETX7DATA12", + "PIPERX2DATA3": "PCIE_PIPERX2DATA3", + "TRNRD75": "PCIE_TRNRD75", + "CFGVENDID9": "PCIE_CFGVENDID9", + "TRNRD68": "PCIE_TRNRD68", + "TRNREOF": "PCIE_TRNREOF", + "CFGDEVCONTROL2ARIFORWARDEN": "PCIE_CFGDEVCONTROL2ARIFORWARDEN", + "EDTCHANNELSOUT7": "PCIE_EDTCHANNELSOUT7", + "TRNRD78": "PCIE_TRNRD78", + "CFGAERROOTERRNONFATALERRREPORTINGEN": "PCIE_CFGAERROOTERRNONFATALERRREPORTINGEN", + "TRNRD1": "PCIE_TRNRD1", + "PIPERX3STATUS0": "PCIE_PIPERX3STATUS0", + "PIPETX6CHARISK1": "PCIE_PIPETX6CHARISK1", + "CFGERRAERHEADERLOG28": "PCIE_CFGERRAERHEADERLOG28", + "TRNTD120": "PCIE_TRNTD120", + "CFGMSGRECEIVEDASSERTINTD": "PCIE_CFGMSGRECEIVEDASSERTINTD", + "DBGVECB27": "PCIE_DBGVECB27", + "PIPETX2CHARISK0": "PCIE_PIPETX2CHARISK0", + "PIPETX5DATA0": "PCIE_PIPETX5DATA0", + "PLLTSSMSTATE4": "PCIE_PLLTSSMSTATE4", + "TRNRD39": "PCIE_TRNRD39", + "PIPETX4DATA13": "PCIE_PIPETX4DATA13", + "CFGMSGDATA14": "PCIE_CFGMSGDATA14", + "TRNRD3": "PCIE_TRNRD3", + "CFGMGMTDO10": "PCIE_CFGMGMTDO10", + "XILUNCONNOUT39": "PCIE_XILUNCONNOUT39", + "TRNRDLLPDATA32": "PCIE_TRNRDLLPDATA32", + "CFGSUBSYSID10": "PCIE_CFGSUBSYSID10", + "PIPERX7DATA12": "PCIE_PIPERX7DATA12", + "MIMTXWDATA18": "PCIE_MIMTXWDATA18", + "PIPERX2ELECIDLE": "PCIE_PIPERX2ELECIDLE", + "MIMRXRADDR11": "PCIE_MIMRXRADDR11", + "TL2ERRFCPE": "PCIE_TL2ERRFCPE", + "CFGDEVID10": "PCIE_CFGDEVID10", + "PIPERX0STATUS2": "PCIE_PIPERX0STATUS2", + "PIPETX3DATA14": "PCIE_PIPETX3DATA14", + "CFGDEVCONTROL2CPLTIMEOUTVAL3": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL3", + "MIMRXRDATA9": "PCIE_MIMRXRDATA9", + "PIPERX2DATA0": "PCIE_PIPERX2DATA0", + "TRNTDLLPDATA11": "PCIE_TRNTDLLPDATA11", + "TL2ERRMALFORMED": "PCIE_TL2ERRMALFORMED", + "PIPETX0DATA4": "PCIE_PIPETX0DATA4", + "CFGAERROOTERRFATALERRREPORTINGEN": "PCIE_CFGAERROOTERRFATALERRREPORTINGEN", + "TRNRDLLPDATA37": "PCIE_TRNRDLLPDATA37", + "CFGDSN24": "PCIE_CFGDSN24", + "CFGLINKCONTROLASPMCONTROL1": "PCIE_CFGLINKCONTROLASPMCONTROL1", + "TRNRD123": "PCIE_TRNRD123", + "CFGERRAERHEADERLOG82": "PCIE_CFGERRAERHEADERLOG82", + "MIMRXWDATA21": "PCIE_MIMRXWDATA21", + "CFGDEVID1": "PCIE_CFGDEVID1", + "TRNRDLLPDATA9": "PCIE_TRNRDLLPDATA9", + "PIPETX5DATA13": "PCIE_PIPETX5DATA13", + "MIMRXWDATA64": "PCIE_MIMRXWDATA64", + "TRNTD83": "PCIE_TRNTD83", + "PIPETX7DATA15": "PCIE_PIPETX7DATA15", + "CFGERRMALFORMEDN": "PCIE_CFGERRMALFORMEDN", + "TRNFCPH1": "PCIE_TRNFCPH1", + "MIMTXRDATA17": "PCIE_MIMTXRDATA17", + "CFGMSGDATA13": "PCIE_CFGMSGDATA13", + "EDTCHANNELSOUT2": "PCIE_EDTCHANNELSOUT2", + "TL2ERRHDR58": "PCIE_TL2ERRHDR58", + "TRNTD93": "PCIE_TRNTD93", + "CFGDSN40": "PCIE_CFGDSN40", + "LL2LINKSTATUS3": "PCIE_LL2LINKSTATUS3", + "DBGVECB9": "PCIE_DBGVECB9", + "DBGSCLRB": "PCIE_DBGSCLRB", + "PIPETX1DATA15": "PCIE_PIPETX1DATA15", + "XILUNCONNOUT31": "PCIE_XILUNCONNOUT31", + "PIPERX1ELECIDLE": "PCIE_PIPERX1ELECIDLE", + "TRNTD48": "PCIE_TRNTD48", + "CFGTRANSACTIONADDR5": "PCIE_CFGTRANSACTIONADDR5", + "PIPETX0DATA7": "PCIE_PIPETX0DATA7", + "PIPERX5CHARISK0": "PCIE_PIPERX5CHARISK0", + "DBGVECA53": "PCIE_DBGVECA53", + "MIMRXWDATA52": "PCIE_MIMRXWDATA52", + "CFGERRAERHEADERLOGSETN": "PCIE_CFGERRAERHEADERLOGSETN", + "CFGDEVCONTROLMAXREADREQ2": "PCIE_CFGDEVCONTROLMAXREADREQ2", + "DBGVECA40": "PCIE_DBGVECA40", + "PIPETX7DATA9": "PCIE_PIPETX7DATA9", + "TRNRD80": "PCIE_TRNRD80", + "TRNTD75": "PCIE_TRNTD75", + "EDTBYPASS": "PCIE_EDTBYPASS", + "TRNTDLLPDATA23": "PCIE_TRNTDLLPDATA23", + "TRNRD72": "PCIE_TRNRD72", + "CFGVCTCVCMAP5": "PCIE_CFGVCTCVCMAP5", + "TL2ERRHDR9": "PCIE_TL2ERRHDR9", + "CFGAERINTERRUPTMSGNUM1": "PCIE_CFGAERINTERRUPTMSGNUM1", + "TRNFCNPD2": "PCIE_TRNFCNPD2", + "MIMRXRDATA15": "PCIE_MIMRXRDATA15", + "CFGMGMTBYTEENN2": "PCIE_CFGMGMTBYTEENN2", + "MIMRXRDATA6": "PCIE_MIMRXRDATA6", + "PIPETX3DATA12": "PCIE_PIPETX3DATA12", + "CFGMSGDATA1": "PCIE_CFGMSGDATA1", + "PIPERX2STATUS0": "PCIE_PIPERX2STATUS0", + "PMVSELECT2": "PCIE_PMVSELECT2", + "TRNTD33": "PCIE_TRNTD33", + "PIPETX7CHARISK0": "PCIE_PIPETX7CHARISK0", + "TRNRD8": "PCIE_TRNRD8", + "MIMTXRDATA12": "PCIE_MIMTXRDATA12", + "CFGINTERRUPTSTATN": "PCIE_CFGINTERRUPTSTATN", + "CFGDSN2": "PCIE_CFGDSN2", + "CFGMGMTDI16": "PCIE_CFGMGMTDI16", + "XILUNCONNOUT29": "PCIE_XILUNCONNOUT29", + "CFGERRAERHEADERLOG18": "PCIE_CFGERRAERHEADERLOG18", + "PLTXPMSTATE1": "PCIE_PLTXPMSTATE1", + "CFGDEVID2": "PCIE_CFGDEVID2", + "TRNRD36": "PCIE_TRNRD36", + "MIMTXWADDR10": "PCIE_MIMTXWADDR10", + "EDTCHANNELSOUT1": "PCIE_EDTCHANNELSOUT1", + "DBGVECB46": "PCIE_DBGVECB46", + "MIMTXWDATA11": "PCIE_MIMTXWDATA11", + "PIPERX3ELECIDLE": "PCIE_PIPERX3ELECIDLE", + "CFGMSGRECEIVEDDEASSERTINTA": "PCIE_CFGMSGRECEIVEDDEASSERTINTA", + "MIMRXWDATA31": "PCIE_MIMRXWDATA31", + "PIPERX1STATUS1": "PCIE_PIPERX1STATUS1", + "MIMTXRDATA22": "PCIE_MIMTXRDATA22", + "CFGDSN32": "PCIE_CFGDSN32", + "TRNTD29": "PCIE_TRNTD29", + "CFGERRAERHEADERLOG54": "PCIE_CFGERRAERHEADERLOG54", + "PIPETX0POWERDOWN0": "PCIE_PIPETX0POWERDOWN0", + "MIMRXWDATA30": "PCIE_MIMRXWDATA30", + "MIMTXRDATA10": "PCIE_MIMTXRDATA10", + "TRNFCCPLH0": "PCIE_TRNFCCPLH0", + "MIMTXRDATA33": "PCIE_MIMTXRDATA33", + "TRNRDLLPDATA63": "PCIE_TRNRDLLPDATA63", + "TRNTD117": "PCIE_TRNTD117", + "TRNTBUFAV4": "PCIE_TRNTBUFAV4", + "TRNTD14": "PCIE_TRNTD14", + "PL2SUSPENDOK": "PCIE_PL2SUSPENDOK", + "DBGVECB39": "PCIE_DBGVECB39", + "PLTXPMSTATE0": "PCIE_PLTXPMSTATE0", + "MIMRXRDATA53": "PCIE_MIMRXRDATA53", + "PL2RXELECIDLE": "PCIE_PL2RXELECIDLE", + "XILUNCONNOUT8": "PCIE_XILUNCONNOUT8", + "PIPERX0DATA3": "PCIE_PIPERX0DATA3", + "DBGVECA7": "PCIE_DBGVECA7", + "DRPDO7": "PCIE_DRPDO7", + "MIMTXRDATA34": "PCIE_MIMTXRDATA34", + "TRNFCPD4": "PCIE_TRNFCPD4", + "TRNRDLLPDATA30": "PCIE_TRNRDLLPDATA30", + "CFGERRAERHEADERLOG57": "PCIE_CFGERRAERHEADERLOG57", + "CFGDSN20": "PCIE_CFGDSN20", + "CFGREVID4": "PCIE_CFGREVID4", + "CFGERRAERHEADERLOG81": "PCIE_CFGERRAERHEADERLOG81", + "MIMTXRDATA47": "PCIE_MIMTXRDATA47", + "CFGTRNPENDINGN": "PCIE_CFGTRNPENDINGN", + "CFGLINKCONTROLCLOCKPMEN": "PCIE_CFGLINKCONTROLCLOCKPMEN", + "DRPDI6": "PCIE_DRPDI6", + "CFGMGMTDI12": "PCIE_CFGMGMTDI12", + "MIMTXRDATA15": "PCIE_MIMTXRDATA15", + "PIPERX4DATA7": "PCIE_PIPERX4DATA7", + "PIPETXMARGIN0": "PCIE_PIPETXMARGIN0", + "LL2BADDLLPERR": "PCIE_LL2BADDLLPERR", + "TRNTDLLPDATA5": "PCIE_TRNTDLLPDATA5", + "MIMRXRADDR5": "PCIE_MIMRXRADDR5", + "CFGSUBSYSVENDID0": "PCIE_CFGSUBSYSVENDID0", + "MIMRXRADDR2": "PCIE_MIMRXRADDR2", + "MIMTXWDATA12": "PCIE_MIMTXWDATA12", + "DBGSCLRG": "PCIE_DBGSCLRG", + "PIPETX5DATA11": "PCIE_PIPETX5DATA11", + "CFGSUBSYSID12": "PCIE_CFGSUBSYSID12", + "TL2ERRHDR18": "PCIE_TL2ERRHDR18", + "TRNRDLLPDATA16": "PCIE_TRNRDLLPDATA16", + "MIMRXRDATA24": "PCIE_MIMRXRDATA24", + "MIMTXWADDR4": "PCIE_MIMTXWADDR4", + "TRNFCCPLD10": "PCIE_TRNFCCPLD10", + "CFGERRTLPCPLHEADER31": "PCIE_CFGERRTLPCPLHEADER31", + "MIMTXWDATA59": "PCIE_MIMTXWDATA59", + "TL2ERRHDR26": "PCIE_TL2ERRHDR26", + "MIMTXWDATA31": "PCIE_MIMTXWDATA31", + "TRNRDLLPDATA6": "PCIE_TRNRDLLPDATA6", + "CFGERRTLPCPLHEADER7": "PCIE_CFGERRTLPCPLHEADER7", + "CFGPCIELINKSTATE1": "PCIE_CFGPCIELINKSTATE1", + "CFGERRTLPCPLHEADER0": "PCIE_CFGERRTLPCPLHEADER0", + "DBGVECC5": "PCIE_DBGVECC5", + "LL2SENDASREQL1": "PCIE_LL2SENDASREQL1", + "MIMTXRDATA5": "PCIE_MIMTXRDATA5", + "TRNRD23": "PCIE_TRNRD23", + "DBGVECB0": "PCIE_DBGVECB0", + "CFGMGMTDO7": "PCIE_CFGMGMTDO7", + "CFGMGMTDO11": "PCIE_CFGMGMTDO11", + "TRNRDLLPDATA53": "PCIE_TRNRDLLPDATA53", + "DBGVECA38": "PCIE_DBGVECA38", + "CFGERRAERHEADERLOG43": "PCIE_CFGERRAERHEADERLOG43", + "MIMRXRADDR0": "PCIE_MIMRXRADDR0", + "SCANENABLEN": "PCIE_SCANENABLEN", + "MIMTXWDATA20": "PCIE_MIMTXWDATA20", + "CFGERRAERHEADERLOG55": "PCIE_CFGERRAERHEADERLOG55", + "LL2TFCINIT2SEQ": "PCIE_LL2TFCINIT2SEQ", + "PIPETX3DATA6": "PCIE_PIPETX3DATA6", + "PIPERX2STATUS2": "PCIE_PIPERX2STATUS2", + "DRPDI0": "PCIE_DRPDI0", + "DBGVECA41": "PCIE_DBGVECA41", + "DBGVECA30": "PCIE_DBGVECA30", + "TRNTDLLPSRCRDY": "PCIE_TRNTDLLPSRCRDY", + "TRNRD29": "PCIE_TRNRD29", + "CFGERRAERHEADERLOG14": "PCIE_CFGERRAERHEADERLOG14", + "TRNTD12": "PCIE_TRNTD12", + "PIPETX0DATA11": "PCIE_PIPETX0DATA11", + "MIMRXWDATA56": "PCIE_MIMRXWDATA56", + "CFGMGMTDO27": "PCIE_CFGMGMTDO27", + "MIMTXRDATA9": "PCIE_MIMTXRDATA9", + "CFGERRTLPCPLHEADER14": "PCIE_CFGERRTLPCPLHEADER14", + "PIPETX6POWERDOWN0": "PCIE_PIPETX6POWERDOWN0", + "XILUNCONNOUT34": "PCIE_XILUNCONNOUT34", + "TRNTD55": "PCIE_TRNTD55", + "DBGVECB28": "PCIE_DBGVECB28", + "TRNTDLLPDATA22": "PCIE_TRNTDLLPDATA22", + "TRNRDLLPSRCRDY0": "PCIE_TRNRDLLPSRCRDY0", + "DBGSUBMODE": "PCIE_DBGSUBMODE", + "PIPERX4CHARISK1": "PCIE_PIPERX4CHARISK1", + "CFGDEVID14": "PCIE_CFGDEVID14", + "CFGERRAERHEADERLOG53": "PCIE_CFGERRAERHEADERLOG53", + "DBGVECB55": "PCIE_DBGVECB55", + "TRNTD26": "PCIE_TRNTD26", + "TRNTD35": "PCIE_TRNTD35", + "CFGLINKSTATUSNEGOTIATEDWIDTH0": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0", + "DBGVECB61": "PCIE_DBGVECB61", + "PIPERX7DATA9": "PCIE_PIPERX7DATA9", + "XILUNCONNOUT19": "PCIE_XILUNCONNOUT19", + "DBGVECA54": "PCIE_DBGVECA54", + "PIPERX3DATA14": "PCIE_PIPERX3DATA14", + "CFGDSN9": "PCIE_CFGDSN9", + "TRNTD124": "PCIE_TRNTD124", + "TRNRDLLPDATA31": "PCIE_TRNRDLLPDATA31", + "TRNTD3": "PCIE_TRNTD3", + "TRNTD28": "PCIE_TRNTD28", + "CFGMGMTDI8": "PCIE_CFGMGMTDI8", + "PIPERX1DATA5": "PCIE_PIPERX1DATA5", + "CFGERRAERHEADERLOG87": "PCIE_CFGERRAERHEADERLOG87", + "TRNTD2": "PCIE_TRNTD2", + "TRNTDLLPDATA2": "PCIE_TRNTDLLPDATA2", + "TRNRD100": "PCIE_TRNRD100", + "PIPETX1DATA13": "PCIE_PIPETX1DATA13", + "DBGVECB48": "PCIE_DBGVECB48", + "CFGVCTCVCMAP0": "PCIE_CFGVCTCVCMAP0", + "PIPERX4DATA12": "PCIE_PIPERX4DATA12", + "CFGREVID0": "PCIE_CFGREVID0", + "DBGMODE1": "PCIE_DBGMODE1", + "PIPERX6DATA10": "PCIE_PIPERX6DATA10", + "EDTCHANNELSOUT4": "PCIE_EDTCHANNELSOUT4", + "MIMRXWDATA28": "PCIE_MIMRXWDATA28", + "CFGDEVCONTROLNONFATALREPORTINGEN": "PCIE_CFGDEVCONTROLNONFATALREPORTINGEN", + "PIPERX1DATA1": "PCIE_PIPERX1DATA1", + "DBGVECB35": "PCIE_DBGVECB35", + "TRNRBARHIT6": "PCIE_TRNRBARHIT6", + "CFGAERROOTERRCORRERRRECEIVED": "PCIE_CFGAERROOTERRCORRERRRECEIVED", + "CFGMGMTDO8": "PCIE_CFGMGMTDO8", + "MIMRXRDATA16": "PCIE_MIMRXRDATA16", + "TRNRDLLPDATA48": "PCIE_TRNRDLLPDATA48", + "DRPDI12": "PCIE_DRPDI12", + "TRNRDLLPDATA47": "PCIE_TRNRDLLPDATA47", + "CFGDSBUSNUMBER1": "PCIE_CFGDSBUSNUMBER1", + "PIPERX4DATA10": "PCIE_PIPERX4DATA10", + "PIPETX5CHARISK1": "PCIE_PIPETX5CHARISK1", + "CFGMSGDATA9": "PCIE_CFGMSGDATA9", + "MIMRXWDATA23": "PCIE_MIMRXWDATA23", + "DBGVECA62": "PCIE_DBGVECA62", + "DRPDI5": "PCIE_DRPDI5", + "XILUNCONNOUT22": "PCIE_XILUNCONNOUT22", + "CFGDSN48": "PCIE_CFGDSN48", + "DRPDO5": "PCIE_DRPDO5", + "CFGERRAERHEADERLOG63": "PCIE_CFGERRAERHEADERLOG63", + "CFGVCTCVCMAP2": "PCIE_CFGVCTCVCMAP2", + "PIPERX7VALID": "PCIE_PIPERX7VALID", + "TRNRD46": "PCIE_TRNRD46", + "CFGREVID3": "PCIE_CFGREVID3", + "CFGMGMTDO13": "PCIE_CFGMGMTDO13", + "CFGMGMTDWADDR8": "PCIE_CFGMGMTDWADDR8", + "PIPERX7DATA4": "PCIE_PIPERX7DATA4", + "TL2ERRHDR25": "PCIE_TL2ERRHDR25", + "TRNRD13": "PCIE_TRNRD13", + "USERCLKPREBUF": "PCIE_USERCLKPREBUF", + "XILUNCONNOUT38": "PCIE_XILUNCONNOUT38", + "TRNFCNPH7": "PCIE_TRNFCNPH7", + "PIPETX3DATA3": "PCIE_PIPETX3DATA3", + "XILUNCONNOUT9": "PCIE_XILUNCONNOUT9", + "TRNRREM0": "PCIE_TRNRREM0", + "PLDIRECTEDLTSSMNEWVLD": "PCIE_PLDIRECTEDLTSSMNEWVLD", + "TRNRD122": "PCIE_TRNRD122", + "DBGSCLRH": "PCIE_DBGSCLRH", + "MIMRXRDATA30": "PCIE_MIMRXRDATA30", + "DBGVECB25": "PCIE_DBGVECB25", + "TRNFCSEL2": "PCIE_TRNFCSEL2", + "MIMTXRADDR12": "PCIE_MIMTXRADDR12", + "CFGPCIECAPINTERRUPTMSGNUM3": "PCIE_CFGPCIECAPINTERRUPTMSGNUM3", + "DBGVECB5": "PCIE_DBGVECB5", + "TRNRDLLPDATA54": "PCIE_TRNRDLLPDATA54", + "TRNRD73": "PCIE_TRNRD73", + "MIMTXRDATA49": "PCIE_MIMTXRDATA49", + "CFGERRAERHEADERLOG52": "PCIE_CFGERRAERHEADERLOG52", + "CFGERRAERHEADERLOG74": "PCIE_CFGERRAERHEADERLOG74", + "DBGVECB33": "PCIE_DBGVECB33", + "CFGERRAERHEADERLOG20": "PCIE_CFGERRAERHEADERLOG20", + "CFGERRAERHEADERLOG78": "PCIE_CFGERRAERHEADERLOG78", + "MIMRXRDATA10": "PCIE_MIMRXRDATA10", + "TRNFCPH0": "PCIE_TRNFCPH0", + "MIMRXRDATA66": "PCIE_MIMRXRDATA66", + "CFGDEVCONTROL2IDOREQEN": "PCIE_CFGDEVCONTROL2IDOREQEN", + "DBGVECB36": "PCIE_DBGVECB36", + "PIPERX7CHARISK0": "PCIE_PIPERX7CHARISK0", + "CFGMGMTDI17": "PCIE_CFGMGMTDI17", + "CFGMGMTDI26": "PCIE_CFGMGMTDI26", + "MIMRXRDATA26": "PCIE_MIMRXRDATA26", + "PIPETX6ELECIDLE": "PCIE_PIPETX6ELECIDLE", + "TRNFCCPLH3": "PCIE_TRNFCCPLH3", + "TRNTD114": "PCIE_TRNTD114", + "TL2ERRHDR1": "PCIE_TL2ERRHDR1", + "PLDBGVEC6": "PCIE_PLDBGVEC6", + "DBGVECC9": "PCIE_DBGVECC9", + "CFGERRAERHEADERLOG27": "PCIE_CFGERRAERHEADERLOG27", + "MIMRXWEN": "PCIE_MIMRXWEN", + "CFGDSN4": "PCIE_CFGDSN4", + "PMVSELECT0": "PCIE_PMVSELECT0", + "MIMRXRDATA14": "PCIE_MIMRXRDATA14", + "MIMTXWDATA36": "PCIE_MIMTXWDATA36", + "DBGVECB38": "PCIE_DBGVECB38", + "PIPETX3POWERDOWN0": "PCIE_PIPETX3POWERDOWN0", + "TRNRDLLPDATA26": "PCIE_TRNRDLLPDATA26", + "MIMRXRDATA64": "PCIE_MIMRXRDATA64", + "MIMRXWDATA58": "PCIE_MIMRXWDATA58", + "TRNRD0": "PCIE_TRNRD0", + "MIMRXRDATA50": "PCIE_MIMRXRDATA50", + "DBGVECA33": "PCIE_DBGVECA33", + "USERCLKPREBUFEN": "PCIE_USERCLKPREBUFEN", + "CFGMGMTDO3": "PCIE_CFGMGMTDO3", + "CFGDSN55": "PCIE_CFGDSN55", + "TRNFCNPH4": "PCIE_TRNFCNPH4", + "TRNTD38": "PCIE_TRNTD38", + "TRNTDLLPDATA15": "PCIE_TRNTDLLPDATA15", + "MIMRXWDATA26": "PCIE_MIMRXWDATA26", + "PIPERX2CHARISK1": "PCIE_PIPERX2CHARISK1", + "TRNTDLLPDATA19": "PCIE_TRNTDLLPDATA19", + "PIPETX4CHARISK0": "PCIE_PIPETX4CHARISK0", + "TRNRD111": "PCIE_TRNRD111", + "MIMRXRDATA55": "PCIE_MIMRXRDATA55", + "TRNRBARHIT2": "PCIE_TRNRBARHIT2", + "CFGERRTLPCPLHEADER37": "PCIE_CFGERRTLPCPLHEADER37", + "PIPERX3DATA13": "PCIE_PIPERX3DATA13", + "MIMTXRDATA38": "PCIE_MIMTXRDATA38", + "TRNRD109": "PCIE_TRNRD109", + "TL2ERRHDR14": "PCIE_TL2ERRHDR14", + "TRNTD115": "PCIE_TRNTD115", + "PLINITIALLINKWIDTH1": "PCIE_PLINITIALLINKWIDTH1", + "CFGLINKCONTROLAUTOBANDWIDTHINTEN": "PCIE_CFGLINKCONTROLAUTOBANDWIDTHINTEN", + "PIPERX5DATA10": "PCIE_PIPERX5DATA10", + "CFGDSN37": "PCIE_CFGDSN37", + "TRNRD87": "PCIE_TRNRD87", + "CFGLINKSTATUSBANDWIDTHSTATUS": "PCIE_CFGLINKSTATUSBANDWIDTHSTATUS", + "DBGVECB21": "PCIE_DBGVECB21", + "MIMTXWDATA21": "PCIE_MIMTXWDATA21", + "MIMTXWDATA47": "PCIE_MIMTXWDATA47", + "PLDBGVEC9": "PCIE_PLDBGVEC9", + "TL2ERRHDR27": "PCIE_TL2ERRHDR27", + "DRPADDR7": "PCIE_DRPADDR7", + "MIMRXWDATA37": "PCIE_MIMRXWDATA37", + "TL2ERRHDR19": "PCIE_TL2ERRHDR19", + "CFGSUBSYSID7": "PCIE_CFGSUBSYSID7", + "TRNTD21": "PCIE_TRNTD21", + "TRNTD30": "PCIE_TRNTD30", + "PIPERX2DATA13": "PCIE_PIPERX2DATA13", + "CFGREVID1": "PCIE_CFGREVID1", + "TRNRD74": "PCIE_TRNRD74", + "CFGDSBUSNUMBER0": "PCIE_CFGDSBUSNUMBER0", + "TRNRD101": "PCIE_TRNRD101", + "DBGSCLRJ": "PCIE_DBGSCLRJ", + "TRNTD71": "PCIE_TRNTD71", + "MIMRXWDATA11": "PCIE_MIMRXWDATA11", + "DBGVECA51": "PCIE_DBGVECA51", + "DRPWE": "PCIE_DRPWE", + "MIMRXRDATA39": "PCIE_MIMRXRDATA39", + "MIMRXWDATA55": "PCIE_MIMRXWDATA55", + "TRNTD72": "PCIE_TRNTD72", + "CFGDSN45": "PCIE_CFGDSN45", + "CMSTICKYRSTN": "PCIE_CMSTICKYRSTN", + "CFGERRCORN": "PCIE_CFGERRCORN", + "CFGERRAERHEADERLOG23": "PCIE_CFGERRAERHEADERLOG23", + "MIMRXRDATA7": "PCIE_MIMRXRDATA7", + "CFGMSGRECEIVEDPMASNAK": "PCIE_CFGMSGRECEIVEDPMASNAK", + "MIMTXWDATA25": "PCIE_MIMTXWDATA25", + "CFGERRATOMICEGRESSBLOCKEDN": "PCIE_CFGERRATOMICEGRESSBLOCKEDN", + "TRNTDLLPDATA17": "PCIE_TRNTDLLPDATA17", + "DBGVECA22": "PCIE_DBGVECA22", + "CFGLINKCONTROLASPMCONTROL0": "PCIE_CFGLINKCONTROLASPMCONTROL0", + "CFGMGMTDO21": "PCIE_CFGMGMTDO21", + "PIPERX0DATA2": "PCIE_PIPERX0DATA2", + "CFGINTERRUPTDO5": "PCIE_CFGINTERRUPTDO5", + "DBGVECA18": "PCIE_DBGVECA18", + "CFGERRAERHEADERLOG104": "PCIE_CFGERRAERHEADERLOG104", + "DBGVECB37": "PCIE_DBGVECB37", + "MIMTXWEN": "PCIE_MIMTXWEN", + "DBGVECB40": "PCIE_DBGVECB40", + "TRNRD50": "PCIE_TRNRD50", + "TRNTD34": "PCIE_TRNTD34", + "MIMTXWDATA44": "PCIE_MIMTXWDATA44", + "CFGERRAERHEADERLOG5": "PCIE_CFGERRAERHEADERLOG5", + "MIMRXRDATA63": "PCIE_MIMRXRDATA63", + "MIMRXRDATA51": "PCIE_MIMRXRDATA51", + "MIMTXWDATA54": "PCIE_MIMTXWDATA54", + "TRNRD121": "PCIE_TRNRD121", + "TRNRD119": "PCIE_TRNRD119", + "TRNRDLLPDATA23": "PCIE_TRNRDLLPDATA23", + "CFGMGMTDI14": "PCIE_CFGMGMTDI14", + "CFGERRAERHEADERLOG96": "PCIE_CFGERRAERHEADERLOG96", + "PIPERX4PHYSTATUS": "PCIE_PIPERX4PHYSTATUS", + "PIPERX6ELECIDLE": "PCIE_PIPERX6ELECIDLE", + "TRNRD84": "PCIE_TRNRD84", + "DRPDO4": "PCIE_DRPDO4", + "MIMRXRADDR7": "PCIE_MIMRXRADDR7", + "CFGPMRCVENTERL23N": "PCIE_CFGPMRCVENTERL23N", + "PLDBGVEC1": "PCIE_PLDBGVEC1", + "CFGPCIELINKSTATE2": "PCIE_CFGPCIELINKSTATE2", + "TRNRD48": "PCIE_TRNRD48", + "TRNTD17": "PCIE_TRNTD17", + "TRNRDLLPDATA56": "PCIE_TRNRDLLPDATA56", + "CFGERRAERHEADERLOG124": "PCIE_CFGERRAERHEADERLOG124", + "PIPERX1DATA10": "PCIE_PIPERX1DATA10", + "PIPETX5POWERDOWN0": "PCIE_PIPETX5POWERDOWN0", + "MIMRXRDATA17": "PCIE_MIMRXRDATA17", + "CFGERRAERHEADERLOG48": "PCIE_CFGERRAERHEADERLOG48", + "TRNFCCPLH2": "PCIE_TRNFCCPLH2", + "CFGDSN53": "PCIE_CFGDSN53", + "CFGDSN28": "PCIE_CFGDSN28", + "PL2DIRECTEDLSTATE1": "PCIE_PL2DIRECTEDLSTATE1", + "PIPETX6DATA11": "PCIE_PIPETX6DATA11", + "DBGVECA48": "PCIE_DBGVECA48", + "PIPERX6PHYSTATUS": "PCIE_PIPERX6PHYSTATUS", + "TRNRD42": "PCIE_TRNRD42", + "MIMRXRDATA44": "PCIE_MIMRXRDATA44", + "CFGPMCSRPOWERSTATE0": "PCIE_CFGPMCSRPOWERSTATE0", + "MIMTXWDATA62": "PCIE_MIMTXWDATA62", + "TL2PPMSUSPENDOK": "PCIE_TL2PPMSUSPENDOK", + "PIPETX0ELECIDLE": "PCIE_PIPETX0ELECIDLE", + "TRNRDSTRDY": "PCIE_TRNRDSTRDY", + "TRNTD31": "PCIE_TRNTD31", + "CFGPORTNUMBER7": "PCIE_CFGPORTNUMBER7", + "PIPERX1DATA13": "PCIE_PIPERX1DATA13", + "TRNTD62": "PCIE_TRNTD62", + "MIMRXWDATA57": "PCIE_MIMRXWDATA57", + "PLUPSTREAMPREFERDEEMPH": "PCIE_PLUPSTREAMPREFERDEEMPH", + "XILUNCONNOUT21": "PCIE_XILUNCONNOUT21", + "CFGMSGDATA7": "PCIE_CFGMSGDATA7", + "DBGVECC1": "PCIE_DBGVECC1", + "CFGSUBSYSVENDID12": "PCIE_CFGSUBSYSVENDID12", + "MIMTXWDATA32": "PCIE_MIMTXWDATA32", + "CFGDEVID13": "PCIE_CFGDEVID13", + "XILUNCONNOUT2": "PCIE_XILUNCONNOUT2", + "TRNTD36": "PCIE_TRNTD36", + "PIPETX2ELECIDLE": "PCIE_PIPETX2ELECIDLE", + "TRNRD93": "PCIE_TRNRD93", + "MIMRXRADDR8": "PCIE_MIMRXRADDR8", + "PLDBGVEC0": "PCIE_PLDBGVEC0", + "MIMTXRDATA28": "PCIE_MIMTXRDATA28", + "DBGVECA16": "PCIE_DBGVECA16", + "TRNTD43": "PCIE_TRNTD43", + "PIPERX0DATA8": "PCIE_PIPERX0DATA8", + "TRNRDLLPDATA51": "PCIE_TRNRDLLPDATA51", + "TRNTD50": "PCIE_TRNTD50", + "TRNRD70": "PCIE_TRNRD70", + "DBGVECA56": "PCIE_DBGVECA56", + "DRPADDR0": "PCIE_DRPADDR0", + "PIPETX7DATA2": "PCIE_PIPETX7DATA2", + "TL2ERRHDR33": "PCIE_TL2ERRHDR33", + "DBGVECA60": "PCIE_DBGVECA60", + "TRNRD81": "PCIE_TRNRD81", + "CFGERRAERHEADERLOG76": "PCIE_CFGERRAERHEADERLOG76", + "CFGERRAERHEADERLOG66": "PCIE_CFGERRAERHEADERLOG66", + "CFGERRAERHEADERLOG42": "PCIE_CFGERRAERHEADERLOG42", + "TRNRD38": "PCIE_TRNRD38", + "MIMRXWADDR0": "PCIE_MIMRXWADDR0", + "MIMTXWDATA23": "PCIE_MIMTXWDATA23", + "CFGERRTLPCPLHEADER28": "PCIE_CFGERRTLPCPLHEADER28", + "TRNTD116": "PCIE_TRNTD116", + "TRNTD96": "PCIE_TRNTD96", + "PIPETX5DATA4": "PCIE_PIPETX5DATA4", + "MIMRXRDATA0": "PCIE_MIMRXRDATA0", + "CFGINTERRUPTMSIXENABLE": "PCIE_CFGINTERRUPTMSIXENABLE", + "TRNRDLLPDATA13": "PCIE_TRNRDLLPDATA13", + "DBGVECB54": "PCIE_DBGVECB54", + "TRNTBUFAV2": "PCIE_TRNTBUFAV2", + "DBGVECA50": "PCIE_DBGVECA50", + "MIMTXRDATA46": "PCIE_MIMTXRDATA46", + "CFGDEVID9": "PCIE_CFGDEVID9", + "PIPETX2DATA12": "PCIE_PIPETX2DATA12", + "TRNRDLLPDATA20": "PCIE_TRNRDLLPDATA20", + "TRNRDLLPDATA24": "PCIE_TRNRDLLPDATA24", + "TRNRDLLPDATA11": "PCIE_TRNRDLLPDATA11", + "MIMTXRDATA14": "PCIE_MIMTXRDATA14", + "CFGPCIECAPINTERRUPTMSGNUM2": "PCIE_CFGPCIECAPINTERRUPTMSGNUM2", + "CFGMGMTDI11": "PCIE_CFGMGMTDI11", + "TRNTD0": "PCIE_TRNTD0", + "PIPERX6VALID": "PCIE_PIPERX6VALID", + "MIMRXRDATA43": "PCIE_MIMRXRDATA43", + "TL2ERRHDR56": "PCIE_TL2ERRHDR56", + "CFGERRAERHEADERLOG84": "PCIE_CFGERRAERHEADERLOG84", + "TRNTDLLPDATA30": "PCIE_TRNTDLLPDATA30", + "CFGERRAERHEADERLOG123": "PCIE_CFGERRAERHEADERLOG123", + "CFGERRAERHEADERLOG68": "PCIE_CFGERRAERHEADERLOG68", + "PIPETX1DATA2": "PCIE_PIPETX1DATA2", + "TRNTDLLPDATA13": "PCIE_TRNTDLLPDATA13", + "PLDIRECTEDCHANGEDONE": "PCIE_PLDIRECTEDCHANGEDONE", + "MIMTXWDATA65": "PCIE_MIMTXWDATA65", + "CFGMGMTDI27": "PCIE_CFGMGMTDI27", + "TRNTD82": "PCIE_TRNTD82", + "TRNRDLLPDATA17": "PCIE_TRNRDLLPDATA17", + "CFGDSN54": "PCIE_CFGDSN54", + "PIPERX3CHANISALIGNED": "PCIE_PIPERX3CHANISALIGNED", + "CFGDSN44": "PCIE_CFGDSN44", + "TRNRD26": "PCIE_TRNRD26", + "DRPEN": "PCIE_DRPEN", + "PIPERX5STATUS0": "PCIE_PIPERX5STATUS0", + "TRNTD69": "PCIE_TRNTD69", + "TRNTD25": "PCIE_TRNTD25", + "MIMRXWDATA61": "PCIE_MIMRXWDATA61", + "DBGVECB22": "PCIE_DBGVECB22", + "MIMRXWDATA18": "PCIE_MIMRXWDATA18", + "CFGERRPOSTEDN": "PCIE_CFGERRPOSTEDN", + "PIPERX2DATA7": "PCIE_PIPERX2DATA7", + "PIPETX1POWERDOWN1": "PCIE_PIPETX1POWERDOWN1", + "MIMRXWDATA39": "PCIE_MIMRXWDATA39", + "CFGDSBUSNUMBER6": "PCIE_CFGDSBUSNUMBER6", + "TL2ERRHDR34": "PCIE_TL2ERRHDR34", + "MIMTXWDATA57": "PCIE_MIMTXWDATA57", + "TRNRD113": "PCIE_TRNRD113", + "MIMTXWDATA63": "PCIE_MIMTXWDATA63", + "MIMRXRADDR10": "PCIE_MIMRXRADDR10", + "CFGLINKCONTROLBANDWIDTHINTEN": "PCIE_CFGLINKCONTROLBANDWIDTHINTEN", + "TRNTBUFAV3": "PCIE_TRNTBUFAV3", + "PIPERX3DATA4": "PCIE_PIPERX3DATA4", + "CFGVENDID5": "PCIE_CFGVENDID5", + "MIMTXWDATA4": "PCIE_MIMTXWDATA4", + "DBGVECC10": "PCIE_DBGVECC10", + "TRNTD91": "PCIE_TRNTD91", + "CFGLINKCONTROLLINKDISABLE": "PCIE_CFGLINKCONTROLLINKDISABLE", + "TRNRREM1": "PCIE_TRNRREM1", + "DBGVECA57": "PCIE_DBGVECA57", + "TRNTD47": "PCIE_TRNTD47", + "CFGERRAERHEADERLOG47": "PCIE_CFGERRAERHEADERLOG47", + "MIMRXWADDR4": "PCIE_MIMRXWADDR4", + "TRNRDLLPDATA33": "PCIE_TRNRDLLPDATA33", + "DBGSCLRI": "PCIE_DBGSCLRI", + "PLDIRECTEDLTSSMNEW1": "PCIE_PLDIRECTEDLTSSMNEW1", + "RECEIVEDFUNCLVLRSTN": "PCIE_RECEIVEDFUNCLVLRSTN", + "PLDIRECTEDLTSSMNEW2": "PCIE_PLDIRECTEDLTSSMNEW2", + "TRNTERRFWD": "PCIE_TRNTERRFWD", + "CFGDSN39": "PCIE_CFGDSN39", + "CFGMGMTDO25": "PCIE_CFGMGMTDO25", + "CFGMGMTDO15": "PCIE_CFGMGMTDO15", + "CFGDEVCONTROL2LTREN": "PCIE_CFGDEVCONTROL2LTREN", + "PIPETX4ELECIDLE": "PCIE_PIPETX4ELECIDLE", + "PIPERX6DATA2": "PCIE_PIPERX6DATA2", + "TRNTD106": "PCIE_TRNTD106", + "CFGDEVCONTROLNOSNOOPEN": "PCIE_CFGDEVCONTROLNOSNOOPEN", + "CFGINTERRUPTDO7": "PCIE_CFGINTERRUPTDO7", + "PIPERX2DATA15": "PCIE_PIPERX2DATA15", + "PIPERX4DATA8": "PCIE_PIPERX4DATA8", + "DRPDO1": "PCIE_DRPDO1", + "TL2ERRHDR13": "PCIE_TL2ERRHDR13", + "TRNRD89": "PCIE_TRNRD89", + "TRNTD4": "PCIE_TRNTD4", + "DBGVECB58": "PCIE_DBGVECB58", + "CFGDSN36": "PCIE_CFGDSN36", + "TL2ERRHDR46": "PCIE_TL2ERRHDR46", + "DBGVECA25": "PCIE_DBGVECA25", + "CFGPORTNUMBER4": "PCIE_CFGPORTNUMBER4", + "TRNRD2": "PCIE_TRNRD2", + "PIPERX5POLARITY": "PCIE_PIPERX5POLARITY", + "PL2RECEIVERERR": "PCIE_PL2RECEIVERERR", + "PIPERX3DATA0": "PCIE_PIPERX3DATA0", + "XILUNCONNOUT4": "PCIE_XILUNCONNOUT4", + "XILUNCONNOUT23": "PCIE_XILUNCONNOUT23", + "DBGVECB56": "PCIE_DBGVECB56", + "MIMTXRDATA32": "PCIE_MIMTXRDATA32", + "MIMRXRDATA41": "PCIE_MIMRXRDATA41", + "TRNFCCPLH6": "PCIE_TRNFCCPLH6", + "DBGVECA3": "PCIE_DBGVECA3", + "CFGERRAERHEADERLOG75": "PCIE_CFGERRAERHEADERLOG75", + "CFGMSGRECEIVEDERRCOR": "PCIE_CFGMSGRECEIVEDERRCOR", + "PIPETX2DATA1": "PCIE_PIPETX2DATA1", + "TL2ERRHDR49": "PCIE_TL2ERRHDR49", + "MIMTXWDATA14": "PCIE_MIMTXWDATA14", + "LL2TLPRCV": "PCIE_LL2TLPRCV", + "CFGERRAERHEADERLOG77": "PCIE_CFGERRAERHEADERLOG77", + "CFGERRAERHEADERLOG89": "PCIE_CFGERRAERHEADERLOG89", + "MIMRXRDATA59": "PCIE_MIMRXRDATA59", + "CFGSUBSYSID3": "PCIE_CFGSUBSYSID3", + "DBGVECA46": "PCIE_DBGVECA46", + "CFGMGMTDWADDR7": "PCIE_CFGMGMTDWADDR7", + "CFGDSBUSNUMBER2": "PCIE_CFGDSBUSNUMBER2", + "DBGVECA52": "PCIE_DBGVECA52", + "CFGERRAERHEADERLOG67": "PCIE_CFGERRAERHEADERLOG67", + "PLLANEREVERSALMODE1": "PCIE_PLLANEREVERSALMODE1", + "CFGMSGRECEIVEDUNLOCK": "PCIE_CFGMSGRECEIVEDUNLOCK", + "CFGERRAERHEADERLOG73": "PCIE_CFGERRAERHEADERLOG73", + "TRNRDLLPDATA45": "PCIE_TRNRDLLPDATA45", + "TRNRDLLPDATA0": "PCIE_TRNRDLLPDATA0", + "PIPERX1POLARITY": "PCIE_PIPERX1POLARITY", + "CFGDSN50": "PCIE_CFGDSN50", + "TRNTD45": "PCIE_TRNTD45", + "TRNTD99": "PCIE_TRNTD99", + "CFGPMFORCESTATE1": "PCIE_CFGPMFORCESTATE1", + "CFGMGMTDI2": "PCIE_CFGMGMTDI2", + "PIPERX5DATA0": "PCIE_PIPERX5DATA0", + "DBGVECA27": "PCIE_DBGVECA27", + "TL2ASPMSUSPENDCREDITCHECK": "PCIE_TL2ASPMSUSPENDCREDITCHECK", + "PIPERX2DATA8": "PCIE_PIPERX2DATA8", + "PIPERX5DATA8": "PCIE_PIPERX5DATA8", + "CFGERRTLPCPLHEADER11": "PCIE_CFGERRTLPCPLHEADER11", + "TRNTD119": "PCIE_TRNTD119", + "CFGMSGRECEIVEDDEASSERTINTB": "PCIE_CFGMSGRECEIVEDDEASSERTINTB", + "CFGTRANSACTIONADDR3": "PCIE_CFGTRANSACTIONADDR3", + "MIMTXWADDR11": "PCIE_MIMTXWADDR11", + "CFGMGMTDO18": "PCIE_CFGMGMTDO18", + "PIPERX7STATUS0": "PCIE_PIPERX7STATUS0", + "MIMTXRDATA19": "PCIE_MIMTXRDATA19", + "PIPERX1DATA6": "PCIE_PIPERX1DATA6", + "TRNRERRFWD": "PCIE_TRNRERRFWD", + "PLDIRECTEDLINKCHANGE1": "PCIE_PLDIRECTEDLINKCHANGE1", + "MIMRXWDATA42": "PCIE_MIMRXWDATA42", + "MIMRXWADDR3": "PCIE_MIMRXWADDR3", + "PIPETX1CHARISK0": "PCIE_PIPETX1CHARISK0", + "MIMTXRADDR4": "PCIE_MIMTXRADDR4", + "TRNFCNPH6": "PCIE_TRNFCNPH6", + "MIMRXWDATA1": "PCIE_MIMRXWDATA1", + "CFGERRAERHEADERLOG127": "PCIE_CFGERRAERHEADERLOG127", + "DBGVECB17": "PCIE_DBGVECB17", + "CFGERRAERHEADERLOG116": "PCIE_CFGERRAERHEADERLOG116", + "CFGDSN16": "PCIE_CFGDSN16", + "TL2ERRHDR30": "PCIE_TL2ERRHDR30", + "DRPDI4": "PCIE_DRPDI4", + "CFGERRAERHEADERLOG46": "PCIE_CFGERRAERHEADERLOG46", + "TL2ERRHDR59": "PCIE_TL2ERRHDR59", + "PIPERX3DATA11": "PCIE_PIPERX3DATA11", + "PIPERX0DATA14": "PCIE_PIPERX0DATA14", + "MIMTXWADDR12": "PCIE_MIMTXWADDR12", + "CFGERRAERHEADERLOG102": "PCIE_CFGERRAERHEADERLOG102", + "TRNFCNPH2": "PCIE_TRNFCNPH2", + "XILUNCONNOUT11": "PCIE_XILUNCONNOUT11", + "DBGVECA23": "PCIE_DBGVECA23", + "TRNRDLLPDATA5": "PCIE_TRNRDLLPDATA5", + "CFGDSN47": "PCIE_CFGDSN47", + "TL2ERRHDR45": "PCIE_TL2ERRHDR45", + "CFGERRAERHEADERLOG21": "PCIE_CFGERRAERHEADERLOG21", + "PIPERX1DATA14": "PCIE_PIPERX1DATA14", + "TRNRD18": "PCIE_TRNRD18", + "TRNTD46": "PCIE_TRNTD46", + "DBGVECB26": "PCIE_DBGVECB26", + "MIMTXWDATA60": "PCIE_MIMTXWDATA60", + "CFGERRAERHEADERLOG38": "PCIE_CFGERRAERHEADERLOG38", + "CFGERRTLPCPLHEADER41": "PCIE_CFGERRTLPCPLHEADER41", + "PIPERX2DATA9": "PCIE_PIPERX2DATA9", + "CFGMGMTDO19": "PCIE_CFGMGMTDO19", + "PIPETX5DATA8": "PCIE_PIPETX5DATA8", + "TRNFCPD6": "PCIE_TRNFCPD6", + "TL2ERRHDR3": "PCIE_TL2ERRHDR3", + "TRNTDLLPDATA9": "PCIE_TRNTDLLPDATA9", + "MIMTXRDATA50": "PCIE_MIMTXRDATA50", + "DRPDO8": "PCIE_DRPDO8", + "TRNRD86": "PCIE_TRNRD86", + "CFGMGMTDI6": "PCIE_CFGMGMTDI6", + "TRNRD98": "PCIE_TRNRD98", + "TRNTDLLPDATA6": "PCIE_TRNTDLLPDATA6", + "TRNFCCPLD7": "PCIE_TRNFCCPLD7", + "CFGERRTLPCPLHEADER25": "PCIE_CFGERRTLPCPLHEADER25", + "MIMRXREN": "PCIE_MIMRXREN", + "XILUNCONNOUT24": "PCIE_XILUNCONNOUT24", + "CFGERRCPLUNEXPECTN": "PCIE_CFGERRCPLUNEXPECTN", + "MIMTXRDATA39": "PCIE_MIMTXRDATA39", + "CFGERRAERHEADERLOG92": "PCIE_CFGERRAERHEADERLOG92", + "PIPETX6POWERDOWN1": "PCIE_PIPETX6POWERDOWN1", + "CFGDSN3": "PCIE_CFGDSN3", + "MIMRXWADDR2": "PCIE_MIMRXWADDR2", + "TRNTD66": "PCIE_TRNTD66", + "TRNRD82": "PCIE_TRNRD82", + "PIPETX3DATA15": "PCIE_PIPETX3DATA15", + "PLDBGVEC11": "PCIE_PLDBGVEC11", + "TRNRSOF": "PCIE_TRNRSOF", + "CFGERRAERHEADERLOG105": "PCIE_CFGERRAERHEADERLOG105", + "MIMRXWDATA5": "PCIE_MIMRXWDATA5", + "LL2TFCINIT1SEQ": "PCIE_LL2TFCINIT1SEQ", + "XILUNCONNOUT25": "PCIE_XILUNCONNOUT25", + "EDTCHANNELSOUT8": "PCIE_EDTCHANNELSOUT8", + "TL2ERRHDR7": "PCIE_TL2ERRHDR7", + "CFGERRAERHEADERLOG24": "PCIE_CFGERRAERHEADERLOG24", + "PIPETX1POWERDOWN0": "PCIE_PIPETX1POWERDOWN0", + "TRNFCCPLH5": "PCIE_TRNFCCPLH5", + "TRNRDLLPDATA8": "PCIE_TRNRDLLPDATA8", + "LL2SUSPENDOK": "PCIE_LL2SUSPENDOK", + "PIPETX6DATA4": "PCIE_PIPETX6DATA4", + "MIMRXWDATA19": "PCIE_MIMRXWDATA19", + "CFGDSN49": "PCIE_CFGDSN49", + "TRNFCPH3": "PCIE_TRNFCPH3", + "PIPERX5DATA3": "PCIE_PIPERX5DATA3", + "CFGERRTLPCPLHEADER32": "PCIE_CFGERRTLPCPLHEADER32", + "MIMTXWDATA55": "PCIE_MIMTXWDATA55", + "CFGERRAERHEADERLOG15": "PCIE_CFGERRAERHEADERLOG15", + "CFGDEVCONTROL2IDOCPLEN": "PCIE_CFGDEVCONTROL2IDOCPLEN", + "TRNFCCPLH1": "PCIE_TRNFCCPLH1", + "TRNRD104": "PCIE_TRNRD104", + "MIMTXWDATA22": "PCIE_MIMTXWDATA22", + "PIPETXRESET": "PCIE_PIPETXRESET", + "EDTCHANNELSOUT3": "PCIE_EDTCHANNELSOUT3", + "TRNTD77": "PCIE_TRNTD77", + "TRNRD65": "PCIE_TRNRD65", + "TRNRDLLPDATA28": "PCIE_TRNRDLLPDATA28", + "DBGVECC3": "PCIE_DBGVECC3", + "TRNRD12": "PCIE_TRNRD12", + "MIMTXWDATA10": "PCIE_MIMTXWDATA10", + "PIPETX6COMPLIANCE": "PCIE_PIPETX6COMPLIANCE", + "PIPETX6DATA1": "PCIE_PIPETX6DATA1", + "EDTCLK": "PCIE_EDTCLK", + "CFGMGMTDI23": "PCIE_CFGMGMTDI23", + "TRNRDLLPDATA60": "PCIE_TRNRDLLPDATA60", + "PLDBGMODE2": "PCIE_PLDBGMODE2", + "TRNTD101": "PCIE_TRNTD101", + "TRNTD1": "PCIE_TRNTD1", + "CFGVENDID11": "PCIE_CFGVENDID11", + "TRNTDLLPDATA28": "PCIE_TRNTDLLPDATA28", + "CFGDEVCONTROL2CPLTIMEOUTVAL0": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL0", + "PMVOUT": "PCIE_PMVOUT", + "CFGDEVCONTROL2CPLTIMEOUTDIS": "PCIE_CFGDEVCONTROL2CPLTIMEOUTDIS", + "TRNRD9": "PCIE_TRNRD9", + "TRNTD104": "PCIE_TRNTD104", + "PIPETX5CHARISK0": "PCIE_PIPETX5CHARISK0", + "CFGDEVCONTROLMAXREADREQ0": "PCIE_CFGDEVCONTROLMAXREADREQ0", + "MIMTXWDATA9": "PCIE_MIMTXWDATA9", + "CFGSUBSYSVENDID13": "PCIE_CFGSUBSYSVENDID13", + "CFGSUBSYSVENDID3": "PCIE_CFGSUBSYSVENDID3", + "PLRXPMSTATE1": "PCIE_PLRXPMSTATE1", + "PIPETX4DATA11": "PCIE_PIPETX4DATA11", + "MIMRXWDATA24": "PCIE_MIMRXWDATA24", + "CFGAERROOTERRFATALERRRECEIVED": "PCIE_CFGAERROOTERRFATALERRRECEIVED", + "PIPETX2DATA3": "PCIE_PIPETX2DATA3", + "MIMTXWDATA58": "PCIE_MIMTXWDATA58", + "EDTCHANNELSIN4": "PCIE_EDTCHANNELSIN4", + "TRNRDLLPDATA52": "PCIE_TRNRDLLPDATA52", + "XILUNCONNOUT20": "PCIE_XILUNCONNOUT20", + "DBGVECA31": "PCIE_DBGVECA31", + "PIPERX0CHANISALIGNED": "PCIE_PIPERX0CHANISALIGNED", + "DBGVECA28": "PCIE_DBGVECA28", + "TL2ERRHDR16": "PCIE_TL2ERRHDR16", + "MIMRXRDATA32": "PCIE_MIMRXRDATA32", + "XILUNCONNOUT0": "PCIE_XILUNCONNOUT0", + "MIMRXWDATA48": "PCIE_MIMRXWDATA48", + "PL2DIRECTEDLSTATE2": "PCIE_PL2DIRECTEDLSTATE2", + "CFGMSGRECEIVEDPMETO": "PCIE_CFGMSGRECEIVEDPMETO", + "TRNRBARHIT1": "PCIE_TRNRBARHIT1", + "CFGERRAERHEADERLOG64": "PCIE_CFGERRAERHEADERLOG64", + "TRNTDLLPDATA31": "PCIE_TRNTDLLPDATA31", + "TRNRD5": "PCIE_TRNRD5", + "TRNTD40": "PCIE_TRNTD40", + "LL2LINKSTATUS0": "PCIE_LL2LINKSTATUS0", + "PIPETXDEEMPH": "PCIE_PIPETXDEEMPH", + "DBGVECA10": "PCIE_DBGVECA10", + "XILUNCONNOUT13": "PCIE_XILUNCONNOUT13", + "TRNRD51": "PCIE_TRNRD51", + "PIPERX4STATUS0": "PCIE_PIPERX4STATUS0", + "MIMRXWADDR10": "PCIE_MIMRXWADDR10", + "TRNRBARHIT5": "PCIE_TRNRBARHIT5", + "MIMTXRDATA60": "PCIE_MIMTXRDATA60", + "MIMTXWDATA2": "PCIE_MIMTXWDATA2", + "CFGDEVCONTROLFATALERRREPORTINGEN": "PCIE_CFGDEVCONTROLFATALERRREPORTINGEN", + "PIPERX4CHARISK0": "PCIE_PIPERX4CHARISK0", + "PIPETX4DATA4": "PCIE_PIPETX4DATA4", + "CFGERRAERHEADERLOG108": "PCIE_CFGERRAERHEADERLOG108", + "TRNFCNPH3": "PCIE_TRNFCNPH3", + "CFGFORCEMPS2": "PCIE_CFGFORCEMPS2", + "CFGMGMTDI25": "PCIE_CFGMGMTDI25", + "LL2LINKSTATUS4": "PCIE_LL2LINKSTATUS4", + "CFGMGMTDO30": "PCIE_CFGMGMTDO30", + "TL2ERRHDR37": "PCIE_TL2ERRHDR37", + "CFGPCIELINKSTATE0": "PCIE_CFGPCIELINKSTATE0", + "MIMTXRDATA66": "PCIE_MIMTXRDATA66" + }, + "x_coord": 0 + } + ], + "wires": [ + "PCIE_IMUX33_L_17", + "PCIE_LH12_0", + "PCIE_LOGIC_OUTS_B22_L_0", + "PCIE_CFGMGMTDI11", + "PCIE_EE4B3_8", + "PCIE_IMUX20_L_0", + "PCIE_ER1BEG3_5", + "PCIE_WL1END1_13", + "PCIE_IMUX0_R_8", + "PCIE_IMUX2_L_15", + "PCIE_IMUX23_L_10", + "PCIE_WW2END2_13", + "PCIE_BLOCK_OUTS_B1_L_0", + "PCIE_SW4END0_15", + "PCIE_NW4A3_6", + "PCIE_MIMTXWDATA30", + "PCIE_LOGIC_OUTS_B23_R_10", + "PCIE_CTRL1_R_3", + "PCIE_IMUX2_L_9", + "PCIE_NW2A0_17", + "PCIE_TRNRD43", + "PCIE_NE4C0_15", + "PCIE_FAN5_R_19", + "PCIE_NE4BEG0_9", + "PCIE_DBGSCLRI", + "PCIE_EE2A2_17", + "PCIE_CTRL1_L_19", + "PCIE_TL2ERRHDR9", + "PCIE_LH1_5", + "PCIE_TRNFCPH6", + "PCIE_CFGREVID0", + "PCIE_EE4C3_13", + "PCIE_BYP5_R_3", + "PCIE_NW4A1_4", + "PCIE_IMUX14_R_8", + "PCIE_BYP3_R_3", + "PCIE_LH2_14", + "PCIE_MONITOR_P_8", + "PCIE_MIMRXWDATA49", + "PCIE_CLK1_R_0", + "PCIE_LOGIC_OUTS_B15_L_2", + "PCIE_BYP7_L_0", + "PCIE_LOGIC_OUTS_B4_L_12", + "PCIE_IMUX3_L_18", + "PCIE_IMUX15_R_17", + "PCIE_CFGDSN16", + "PCIE_WW4END2_1", + "PCIE_CFGMGMTDO13", + "PCIE_EE4B2_18", + "PCIE_CFGERRTLPCPLHEADER41", + "PCIE_IMUX36_R_8", + "PCIE_TRNRD20", + "PCIE_IMUX2_L_19", + "PCIE_BYP6_R_1", + "PCIE_NW2A2_18", + "PCIE_IMUX23_L_11", + "PCIE_EE4C0_11", + "PCIE_SE2A2_12", + "PCIE_CFGMGMTDI31", + "PCIE_IMUX47_R_15", + "PCIE_TRNTDLLPDATA19", + "PCIE_IMUX24_L_0", + "PCIE_NE4BEG0_11", + "PCIE_WW4C0_6", + "PCIE_FAN6_L_5", + "PCIE_EE4A1_2", + "PCIE_LH4_9", + "PCIE_IMUX30_R_19", + "PCIE_IMUX20_R_10", + "PCIE_PIPETX6DATA12", + "PCIE_IMUX2_R_2", + "PCIE_IMUX12_R_7", + "PCIE_WL1END3_7", + "PCIE_CFGVENDID13", + "PCIE_PIPETX1DATA15", + "PCIE_IMUX7_L_17", + "PCIE_IMUX24_R_3", + "PCIE_WR1END2_11", + "PCIE_LOGIC_OUTS_B1_L_19", + "PCIE_BLOCK_OUTS_B2_L_10", + "PCIE_EL1BEG3_17", + "PCIE_PIPETX0DATA15", + "PCIE_EE2BEG3_5", + "PCIE_BYP3_L_18", + "PCIE_IMUX14_L_0", + "PCIE_FAN4_L_18", + "PCIE_BYP2_R_17", + "PCIE_PIPERX7DATA10", + "PCIE_WL1END3_10", + "PCIE_TRNFCNPD1", + "PCIE_MIMTXRDATA36", + "PCIE_LH9_2", + "PCIE_LOGIC_OUTS_B9_L_2", + "PCIE_PIPETX0DATA9", + "PCIE_IMUX22_R_7", + "PCIE_IMUX5_L_16", + "PCIE_LOGIC_OUTS_B21_L_5", + "PCIE_LOGIC_OUTS_B12_R_17", + "PCIE_LOGIC_OUTS_B6_R_0", + "PCIE_TL2ERRFCPE", + "PCIE_SE4C3_5", + "PCIE_IMUX44_R_9", + "PCIE_IMUX41_L_10", + "PCIE_LOGIC_OUTS_B0_R_13", + "PCIE_IMUX33_R_17", + "PCIE_CFGMSGRECEIVED", + "PCIE_PIPERX4STATUS0", + "PCIE_NE4BEG1_12", + "PCIE_EE4A1_3", + "PCIE_NW4A3_18", + "PCIE_NE2A2_18", + "PCIE_TRNRD96", + "PCIE_CFGERRTLPCPLHEADER23", + "PCIE_LOGIC_OUTS_B23_L_6", + "PCIE_FAN5_L_16", + "PCIE_TRNTD17", + "PCIE_WW4END1_16", + "PCIE_IMUX39_R_4", + "PCIE_SW2A0_9", + "PCIE_WR1END2_0", + "PCIE_BYP0_R_7", + "PCIE_LOGIC_OUTS_B23_R_3", + "PCIE_LH9_8", + "PCIE_MIMRXWDATA10", + "PCIE_IMUX26_L_12", + "PCIE_LOGIC_OUTS_B1_L_14", + "PCIE_MONITOR_P_13", + "PCIE_PIPETX5POWERDOWN1", + "PCIE_IMUX16_L_0", + "PCIE_NW4END0_13", + "PCIE_PIPETX5CHARISK0", + "PCIE_IMUX1_L_10", + "PCIE_IMUX47_R_6", + "PCIE_WW4C1_19", + "PCIE_IMUX12_R_19", + "PCIE_FAN4_L_11", + "PCIE_IMUX15_L_9", + "PCIE_MONITOR_N_5", + "PCIE_LOGIC_OUTS_B0_R_4", + "PCIE_IMUX37_R_0", + "PCIE_EE4A2_13", + "PCIE_LL2TXIDLE", + "PCIE_IMUX44_L_12", + "PCIE_BLOCK_OUTS_B0_R_18", + "PCIE_MIMRXWDATA30", + "PCIE_WW2A2_1", + "PCIE_IMUX17_L_13", + "PCIE_MIMRXWDATA53", + "PCIE_CFGMSGDATA2", + "PCIE_PL2DIRECTEDLSTATE1", + "PCIE_IMUX8_R_13", + "PCIE_BYP4_L_8", + "PCIE_MIMTXRDATA38", + "PCIE_FAN1_R_3", + "PCIE_IMUX5_R_17", + "PCIE_TRNRD89", + "PCIE_BYP0_L_10", + "PCIE_LOGIC_OUTS_B5_L_15", + "PCIE_IMUX12_L_2", + "PCIE_WL1END3_8", + "PCIE_LH5_7", + "PCIE_LH7_1", + "PCIE_LH7_5", + "PCIE_IMUX1_L_5", + "PCIE_SE4C0_17", + "PCIE_PLDBGVEC0", + "PCIE_MIMTXRDATA53", + "PCIE_LOGIC_OUTS_B3_L_3", + "PCIE_IMUX5_R_1", + "PCIE_EE4C3_11", + "PCIE_MIMTXWDATA52", + "PCIE_WW4C2_2", + "PCIE_LOGIC_OUTS_B8_R_1", + "PCIE_CFGERRAERHEADERLOG111", + "PCIE_MIMTXWDATA61", + "PCIE_IMUX45_R_18", + "PCIE_IMUX39_L_1", + "PCIE_LOGIC_OUTS_B18_R_9", + "PCIE_BLOCK_OUTS_B3_R_10", + "PCIE_BYP7_L_18", + "PCIE_SW4A3_7", + "PCIE_IMUX13_R_14", + "PCIE_NW4END1_4", + "PCIE_SW4END2_18", + "PCIE_FAN4_R_1", + "PCIE_CLK1_R_15", + "PCIE_LH3_2", + "PCIE_PIPETX6DATA11", + "PCIE_CFGSUBSYSID5", + "PCIE_CFGERRAERHEADERLOG36", + "PCIE_EL1BEG2_12", + "PCIE_TRNFCCPLD6", + "PCIE_BYP4_R_18", + "PCIE_FAN0_R_9", + "PCIE_TRNFCNPD9", + "PCIE_TL2ERRHDR13", + "PCIE_IMUX18_L_2", + "PCIE_IMUX36_R_6", + "PCIE_CFGAERINTERRUPTMSGNUM0", + "PCIE_TRNTCFGREQ", + "PCIE_ER1BEG3_18", + "PCIE_WW2END0_10", + "PCIE_IMUX6_L_9", + "PCIE_TRNFCCPLD8", + "PCIE_TRNFCCPLD1", + "PCIE_CTRL1_L_10", + "PCIE_TL2ASPMSUSPENDREQ", + "PCIE_LOGIC_OUTS_B0_R_19", + "PCIE_LOGIC_OUTS_B2_L_14", + "PCIE_TRNRD52", + "PCIE_ER1BEG0_5", + "PCIE_CFGERRAERHEADERLOG44", + "PCIE_LOGIC_OUTS_B5_R_8", + "PCIE_EE2BEG1_0", + "PCIE_EE4BEG3_2", + "PCIE_IMUX29_L_15", + "PCIE_XILUNCONNOUT27", + "PCIE_IMUX41_L_14", + "PCIE_PIPETX4DATA1", + "PCIE_MIMRXRDATA3", + "PCIE_EL1BEG2_8", + "PCIE_IMUX7_R_5", + "PCIE_WL1END3_18", + "PCIE_ER1BEG0_12", + "PCIE_FAN5_L_3", + "PCIE_IMUX10_L_4", + "PCIE_DRPDO13", + "PCIE_EE4BEG0_11", + "PCIE_EL1BEG0_3", + "PCIE_CTRL0_R_10", + "PCIE_ER1BEG2_14", + "PCIE_CFGERRAERHEADERLOG37", + "PCIE_CFGDSN56", + "PCIE_TRNFCNPD6", + "PCIE_NE2A0_15", + "PCIE_LH12_11", + "PCIE_IMUX34_R_12", + "PCIE_IMUX43_L_2", + "PCIE_IMUX17_L_8", + "PCIE_IMUX18_R_3", + "PCIE_ER1BEG2_13", + "PCIE_XILUNCONNOUT12", + "PCIE_IMUX15_L_15", + "PCIE_WW4C3_12", + "PCIE_BLOCK_OUTS_B2_R_4", + "PCIE_IMUX18_R_16", + "PCIE_PIPERX2DATA0", + "PCIE_WW2END3_17", + "PCIE_CFGMGMTDI25", + "PCIE_IMUX47_R_14", + "PCIE_NW4A3_16", + "PCIE_TRNTD57", + "PCIE_IMUX7_R_6", + "PCIE_FAN7_L_5", + "PCIE_CFGPMRCVREQACKN", + "PCIE_IMUX10_R_1", + "PCIE_WW4A2_1", + "PCIE_LH3_1", + "PCIE_LH7_15", + "PCIE_CFGDSN34", + "PCIE_LOGIC_OUTS_B16_R_7", + "PCIE_LOGIC_OUTS_B15_R_1", + "PCIE_IMUX30_R_1", + "PCIE_IMUX10_L_5", + "PCIE_BLOCK_OUTS_B0_L_9", + "PCIE_WW4B1_18", + "PCIE_LOGIC_OUTS_B12_L_17", + "PCIE_XILUNCONNOUT31", + "PCIE_BLOCK_OUTS_B2_R_7", + "PCIE_PIPETX6DATA5", + "PCIE_FAN6_R_3", + "PCIE_BLOCK_OUTS_B3_R_14", + "PCIE_TRNRD72", + "PCIE_IMUX34_L_7", + "PCIE_IMUX34_R_18", + "PCIE_WW4B3_15", + "PCIE_SW4A1_6", + "PCIE_TRNTD66", + "PCIE_SE4BEG3_1", + "PCIE_SE4BEG0_19", + "PCIE_IMUX10_R_17", + "PCIE_CFGERRTLPCPLHEADER32", + "PCIE_IMUX12_R_3", + "PCIE_WL1END3_4", + "PCIE_BLOCK_OUTS_B0_R_11", + "PCIE_IMUX46_R_13", + "PCIE_LOGIC_OUTS_B10_L_17", + "PCIE_LOGIC_OUTS_B17_L_16", + "PCIE_SE4C2_14", + "PCIE_WW2END1_6", + "PCIE_MIMTXWDATA40", + "PCIE_IMUX38_R_9", + "PCIE_IMUX25_L_14", + "PCIE_IMUX10_L_10", + "PCIE_EE4B0_8", + "PCIE_BYP4_R_1", + "PCIE_CFGERRAERHEADERLOG39", + "PCIE_ER1BEG3_17", + "PCIE_IMUX6_R_2", + "PCIE_EE4BEG3_16", + "PCIE_LOGIC_OUTS_B18_R_5", + "PCIE_MIMRXRDATA51", + "PCIE_SW4A3_9", + "PCIE_LOGIC_OUTS_B22_L_15", + "PCIE_BYP1_R_7", + "PCIE_WR1END1_18", + "PCIE_IMUX22_L_1", + "PCIE_LOGIC_OUTS_B14_L_17", + "PCIE_IMUX42_L_16", + "PCIE_LOGIC_OUTS_B19_R_4", + "PCIE_BYP0_R_19", + "PCIE_SW4A2_4", + "PCIE_SW4END0_9", + "PCIE_PIPERX4DATA2", + "PCIE_CFGMGMTDO0", + "PCIE_PIPETX3DATA5", + "PCIE_MIMRXRDATA21", + "PCIE_NW4END2_7", + "PCIE_IMUX9_R_19", + "PCIE_TRNTD122", + "PCIE_LOGIC_OUTS_B7_L_14", + "PCIE_EE2A3_12", + "PCIE_IMUX9_L_8", + "PCIE_LOGIC_OUTS_B19_L_12", + "PCIE_LOGIC_OUTS_B0_R_12", + "PCIE_BYP6_L_19", + "PCIE_IMUX4_L_1", + "PCIE_PIPERX0DATA10", + "PCIE_LOGIC_OUTS_B12_R_1", + "PCIE_CFGDSN58", + "PCIE_WW4A0_3", + "PCIE_IMUX11_L_19", + "PCIE_IMUX20_R_7", + "PCIE_IMUX36_L_10", + "PCIE_PIPERX2DATA2", + "PCIE_IMUX43_R_15", + "PCIE_LH6_10", + "PCIE_IMUX38_R_17", + "PCIE_PIPERX4ELECIDLE", + "PCIE_MIMRXWDATA33", + "PCIE_PLDIRECTEDLINKCHANGE0", + "PCIE_TRNRD10", + "PCIE_ER1BEG3_13", + "PCIE_SW2A2_16", + "PCIE_FAN7_L_1", + "PCIE_IMUX35_L_7", + "PCIE_PIPETX6DATA2", + "PCIE_LOGIC_OUTS_B2_L_0", + "PCIE_BYP3_L_11", + "PCIE_IMUX28_R_4", + "PCIE_LOGIC_OUTS_B11_R_1", + "PCIE_PIPERX0DATA0", + "PCIE_LH5_4", + "PCIE_PIPERX4CHARISK1", + "PCIE_CFGMGMTDI16", + "PCIE_WW2END3_14", + "PCIE_MIMTXWADDR6", + "PCIE_DBGVECA30", + "PCIE_MIMRXRDATA13", + "PCIE_IMUX36_L_2", + "PCIE_SE4BEG2_16", + "PCIE_BLOCK_OUTS_B2_R_12", + "PCIE_CFGDSN61", + "PCIE_CTRL1_L_15", + "PCIE_BYP4_L_1", + "PCIE_EE2A3_10", + "PCIE_BYP7_R_19", + "PCIE_WW4END3_6", + "PCIE_PIPETX1DATA6", + "PCIE_CFGMGMTDO30", + "PCIE_IMUX11_L_7", + "PCIE_MIMRXWADDR9", + "PCIE_IMUX15_L_4", + "PCIE_PIPETX6ELECIDLE", + "PCIE_CFGERRTLPCPLHEADER18", + "PCIE_WL1END2_9", + "PCIE_IMUX30_L_8", + "PCIE_TRNTD83", + "PCIE_CTRL1_R_4", + "PCIE_IMUX12_R_10", + "PCIE_LOGIC_OUTS_B21_L_18", + "PCIE_IMUX6_L_4", + "PCIE_TRNRD100", + "PCIE_SW2A0_7", + "PCIE_TRNRDLLPDATA48", + "PCIE_LOGIC_OUTS_B14_R_2", + "PCIE_PIPERX3DATA7", + "PCIE_CLK0_R_1", + "PCIE_TL2ERRHDR8", + "PCIE_LOGIC_OUTS_B10_L_3", + "PCIE_IMUX12_R_14", + "PCIE_LOGIC_OUTS_B3_R_12", + "PCIE_IMUX30_L_13", + "PCIE_CFGDSN2", + "PCIE_LOGIC_OUTS_B16_L_0", + "PCIE_IMUX10_R_11", + "PCIE_IMUX19_L_0", + "PCIE_NE4BEG2_7", + "PCIE_LOGIC_OUTS_B18_L_3", + "PCIE_IMUX10_R_18", + "PCIE_LH11_13", + "PCIE_IMUX15_R_4", + "PCIE_LOGIC_OUTS_B2_L_15", + "PCIE_EE4B2_9", + "PCIE_PIPERX2POLARITY", + "PCIE_CFGDSBUSNUMBER7", + "PCIE_DBGVECA20", + "PCIE_SW2A1_14", + "PCIE_BYP1_L_10", + "PCIE_EE4B2_11", + "PCIE_BYP1_R_17", + "PCIE_FAN7_L_17", + "PCIE_FAN3_L_13", + "PCIE_NW4A1_17", + "PCIE_NE4C0_11", + "PCIE_IMUX8_R_10", + "PCIE_EE4B1_18", + "PCIE_TRNTD126", + "PCIE_TRNTDLLPDATA2", + "PCIE_BLOCK_OUTS_B1_R_14", + "PCIE_EE4C1_8", + "PCIE_CFGMGMTDO2", + "PCIE_LOGIC_OUTS_B21_R_10", + "PCIE_IMUX17_L_5", + "PCIE_BYP2_L_14", + "PCIE_LOGIC_OUTS_B12_L_11", + "PCIE_IMUX14_R_16", + "PCIE_WW4B0_17", + "PCIE_IMUX40_R_11", + "PCIE_LOGIC_OUTS_B7_L_16", + "PCIE_LOGIC_OUTS_B10_L_7", + "PCIE_PIPERX2DATA10", + "PCIE_PIPETX6DATA8", + "PCIE_WW4B2_11", + "PCIE_PIPERX4DATA15", + "PCIE_IMUX11_L_12", + "PCIE_NE2A0_14", + "PCIE_NW2A0_12", + "PCIE_IMUX31_R_10", + "PCIE_WL1END1_9", + "PCIE_LOGIC_OUTS_B21_R_4", + "PCIE_EE4B1_0", + "PCIE_LOGIC_OUTS_B13_R_13", + "PCIE_EE2A3_13", + "PCIE_LOGIC_OUTS_B20_L_15", + "PCIE_WR1END1_12", + "PCIE_DBGVECB3", + "PCIE_LOGIC_OUTS_B10_R_0", + "PCIE_EE4B3_9", + "PCIE_EE4A1_18", + "PCIE_BYP2_R_2", + "PCIE_IMUX9_R_6", + "PCIE_LOGIC_OUTS_B7_L_9", + "PCIE_CFGMGMTDI9", + "PCIE_IMUX3_R_13", + "PCIE_IMUX40_L_1", + "PCIE_IMUX31_R_12", + "PCIE_CLK0_R_12", + "PCIE_EL1BEG2_4", + "PCIE_IMUX20_R_14", + "PCIE_NE4C0_17", + "PCIE_IMUX37_R_8", + "PCIE_IMUX0_R_5", + "PCIE_CFGDSBUSNUMBER2", + "PCIE_WW2A0_6", + "PCIE_IMUX37_L_17", + "PCIE_LOGIC_OUTS_B0_L_18", + "PCIE_EE4C3_17", + "PCIE_FAN6_L_0", + "PCIE_TRNTD106", + "PCIE_DBGVECA62", + "PCIE_FAN5_R_12", + "PCIE_IMUX37_L_6", + "PCIE_IMUX26_R_4", + "PCIE_IMUX27_L_1", + "PCIE_DBGVECA56", + "PCIE_LOGIC_OUTS_B11_R_5", + "PCIE_TL2ERRHDR26", + "PCIE_SW2A1_17", + "PCIE_TRNRDLLPDATA5", + "PCIE_NE4BEG3_4", + "PCIE_IMUX9_R_10", + "PCIE_BYP4_L_4", + "PCIE_LH10_4", + "PCIE_EE2A0_1", + "PCIE_LOGIC_OUTS_B15_R_12", + "PCIE_BYP0_R_4", + "PCIE_TL2ERRHDR56", + "PCIE_CFGPMRCVENTERL23N", + "PCIE_CFGSUBSYSVENDID13", + "PCIE_BYP2_R_8", + "PCIE_CFGDEVCONTROLMAXREADREQ1", + "PCIE_WW4B3_8", + "PCIE_IMUX14_R_11", + "PCIE_ER1BEG3_11", + "PCIE_SE2A2_7", + "PCIE_BYP4_R_10", + "PCIE_IMUX46_L_6", + "PCIE_NE4C3_8", + "PCIE_MIMTXRADDR0", + "PCIE_BYP5_L_18", + "PCIE_CFGPMSENDPMETON", + "PCIE_MIMRXWDATA13", + "PCIE_PIPERX6DATA15", + "PCIE_IMUX39_R_3", + "PCIE_BYP5_R_14", + "PCIE_IMUX43_R_2", + "PCIE_EE2A1_16", + "PCIE_LOGIC_OUTS_B23_L_19", + "PCIE_LL2SENDPMACK", + "PCIE_EE4C1_5", + "PCIE_PIPETX3POWERDOWN1", + "PCIE_IMUX29_R_9", + "PCIE_IMUX46_L_0", + "PCIE_BYP5_R_10", + "PCIE_PIPETX3DATA3", + "PCIE_LOGIC_OUTS_B6_R_9", + "PCIE_EE2BEG2_10", + "PCIE_IMUX41_L_6", + "PCIE_PIPETX7DATA13", + "PCIE_EE4A0_4", + "PCIE_IMUX2_R_4", + "PCIE_WW2END3_10", + "PCIE_EE4C1_11", + "PCIE_NW4END1_0", + "PCIE_NW2A1_11", + "PCIE_LOGIC_OUTS_B7_L_6", + "PCIE_PIPETX7DATA9", + "PCIE_FAN6_L_15", + "PCIE_WW4C1_13", + "PCIE_TRNFCCPLD9", + "PCIE_LOGIC_OUTS_B22_L_7", + "PCIE_NW4END0_6", + "PCIE_WW4C3_11", + "PCIE_PIPETX1DATA1", + "PCIE_PIPERX1CHARISK1", + "PCIE_PIPERX5DATA3", + "PCIE_SE2A3_4", + "PCIE_IMUX22_R_4", + "PCIE_WL1END2_13", + "PCIE_WW4B1_11", + "PCIE_IMUX16_L_5", + "PCIE_FAN4_R_2", + "PCIE_EE2BEG0_0", + "PCIE_BYP4_L_15", + "PCIE_TRNRD32", + "PCIE_TRNFCNPD5", + "PCIE_CLK0_R_5", + "PCIE_CTRL0_R_1", + "PCIE_TL2ERRHDR54", + "PCIE_TRNTCFGGNT", + "PCIE_LL2LINKSTATUS4", + "PCIE_WW2END1_14", + "PCIE_LOGIC_OUTS_B0_R_6", + "PCIE_IMUX41_L_12", + "PCIE_LOGIC_OUTS_B23_R_9", + "PCIE_MIMRXWDATA23", + "PCIE_BYP7_R_4", + "PCIE_LOGIC_OUTS_B10_R_14", + "PCIE_LOGIC_OUTS_B7_L_4", + "PCIE_PMVOUT", + "PCIE_IMUX44_L_15", + "PCIE_WW2A2_13", + "PCIE_IMUX30_L_9", + "PCIE_LOGIC_OUTS_B15_R_18", + "PCIE_EE2A3_3", + "PCIE_TRNRD49", + "PCIE_TRNRDLLPDATA1", + "PCIE_IMUX30_L_4", + "PCIE_LOGIC_OUTS_B18_R_2", + "PCIE_SE2A2_14", + "PCIE_EE4C2_19", + "PCIE_LOGIC_OUTS_B12_R_12", + "PCIE_LH10_17", + "PCIE_LOGIC_OUTS_B12_R_9", + "PCIE_EE4A0_18", + "PCIE_IMUX4_R_15", + "PCIE_IMUX4_L_6", + "PCIE_WW4C3_8", + "PCIE_SE4BEG1_10", + "PCIE_SW4A1_0", + "PCIE_WL1END2_0", + "PCIE_PIPETX0DATA4", + "PCIE_SE4BEG1_19", + "PCIE_EE2BEG0_13", + "PCIE_SW4A0_3", + "PCIE_BYP6_R_4", + "PCIE_IMUX25_R_6", + "PCIE_PIPERX0DATA14", + "PCIE_PIPETX4DATA14", + "PCIE_LOGIC_OUTS_B0_R_16", + "PCIE_SE4C2_17", + "PCIE_CTRL1_L_12", + "PCIE_EE4B1_8", + "PCIE_NW4END0_9", + "PCIE_LOGIC_OUTS_B11_R_4", + "PCIE_IMUX42_L_19", + "PCIE_IMUX40_R_16", + "PCIE_SW2A1_0", + "PCIE_BLOCK_OUTS_B3_R_15", + "PCIE_MIMTXWDATA68", + "PCIE_DBGVECA21", + "PCIE_PIPETX0DATA3", + "PCIE_IMUX34_R_1", + "PCIE_TL2ERRHDR38", + "PCIE_WR1END3_1", + "PCIE_TRNTD23", + "PCIE_CTRL0_L_8", + "PCIE_LH10_2", + "PCIE_CFGDSFUNCTIONNUMBER0", + "PCIE_WW4END2_10", + "PCIE_WW4A1_11", + "PCIE_IMUX25_L_6", + "PCIE_PIPERX6DATA12", + "PCIE_CFGCOMMANDIOENABLE", + "PCIE_LOGIC_OUTS_B16_L_19", + "PCIE_FAN2_R_15", + "PCIE_WW4C0_17", + "PCIE_TRNRD34", + "PCIE_IMUX13_L_7", + "PCIE_CFGMSGRECEIVEDDEASSERTINTD", + "PCIE_NW4A1_11", + "PCIE_IMUX22_R_6", + "PCIE_LOGIC_OUTS_B21_L_8", + "PCIE_TRNFCPD4", + "PCIE_WW2A2_15", + "PCIE_CFGERRTLPCPLHEADER16", + "PCIE_ER1BEG2_15", + "PCIE_SE4BEG3_2", + "PCIE_FAN5_L_8", + "PCIE_LOGIC_OUTS_B22_R_4", + "PCIE_CFGVENDID10", + "PCIE_BYP4_R_14", + "PCIE_MIMTXWDATA28", + "PCIE_LH11_10", + "PCIE_FAN1_L_6", + "PCIE_CFGDSN43", + "PCIE_TRNRDLLPDATA13", + "PCIE_LOGIC_OUTS_B18_L_7", + "PCIE_LOGIC_OUTS_B22_L_12", + "PCIE_PIPERX7DATA3", + "PCIE_LOGIC_OUTS_B18_R_1", + "PCIE_LOGIC_OUTS_B13_L_4", + "PCIE_MIMTXWDATA1", + "PCIE_LOGIC_OUTS_B5_L_12", + "PCIE_IMUX45_R_16", + "PCIE_SE4C0_6", + "PCIE_IMUX16_L_17", + "PCIE_IMUX0_L_15", + "PCIE_EE4B0_9", + "PCIE_TRNTD18", + "PCIE_CFGINTERRUPTDO7", + "PCIE_SW4A2_10", + "PCIE_LH10_19", + "PCIE_LOGIC_OUTS_B22_R_6", + "PCIE_PIPETX7DATA4", + "PCIE_FAN1_R_19", + "PCIE_TRNTD60", + "PCIE_WL1END3_15", + "PCIE_EE2BEG1_16", + "PCIE_WW4A1_4", + "PCIE_BYP7_L_8", + "PCIE_BLOCK_OUTS_B0_L_5", + "PCIE_LOGIC_OUTS_B21_L_2", + "PCIE_IMUX40_L_10", + "PCIE_WW4B1_2", + "PCIE_MIMTXWDATA16", + "PCIE_IMUX38_R_10", + "PCIE_TRNTD82", + "PCIE_IMUX15_R_12", + "PCIE_TRNRD64", + "PCIE_IMUX20_R_13", + "PCIE_SW4A0_6", + "PCIE_EE4BEG0_12", + "PCIE_IMUX47_R_8", + "PCIE_CFGMGMTDI28", + "PCIE_IMUX21_R_13", + "PCIE_TRNRDLLPDATA23", + "PCIE_LH10_14", + "PCIE_LH7_18", + "PCIE_MIMRXRDATA15", + "PCIE_IMUX36_R_2", + "PCIE_LH1_18", + "PCIE_IMUX22_L_5", + "PCIE_IMUX18_R_8", + "PCIE_FAN3_L_4", + "PCIE_IMUX11_R_12", + "PCIE_IMUX3_L_8", + "PCIE_MIMTXRADDR5", + "PCIE_SW4A3_6", + "PCIE_EE2BEG3_0", + "PCIE_CFGDSN29", + "PCIE_IMUX37_R_6", + "PCIE_WW2END3_6", + "PCIE_NW2A2_9", + "PCIE_IMUX22_R_2", + "PCIE_IMUX33_L_15", + "PCIE_IMUX5_L_19", + "PCIE_CFGERRAERHEADERLOG119", + "PCIE_DBGVECA25", + "PCIE_EE4A1_10", + "PCIE_IMUX45_R_0", + "PCIE_LOGIC_OUTS_B22_L_1", + "PCIE_DBGVECB53", + "PCIE_LOGIC_OUTS_B18_R_17", + "PCIE_TRNRDLLPDATA11", + "PCIE_IMUX3_R_19", + "PCIE_LH4_7", + "PCIE_LOGIC_OUTS_B17_L_0", + "PCIE_LOGIC_OUTS_B21_R_7", + "PCIE_IMUX5_L_11", + "PCIE_SE2A3_14", + "PCIE_IMUX43_R_6", + "PCIE_MIMTXRADDR3", + "PCIE_IMUX46_L_10", + "PCIE_WW2A1_5", + "PCIE_IMUX21_L_10", + "PCIE_TRNTD3", + "PCIE_EE4BEG3_0", + "PCIE_WL1END3_14", + "PCIE_IMUX46_L_16", + "PCIE_CFGVENDID7", + "PCIE_BYP0_R_13", + "PCIE_IMUX0_R_12", + "PCIE_WW4A3_3", + "PCIE_LOGIC_OUTS_B12_R_3", + "PCIE_IMUX44_R_14", + "PCIE_BLOCK_OUTS_B2_R_0", + "PCIE_IMUX43_R_10", + "PCIE_NW4A2_15", + "PCIE_LOGIC_OUTS_B19_L_5", + "PCIE_BYP1_R_8", + "PCIE_NW4END2_10", + "PCIE_CTRL0_L_2", + "PCIE_LOGIC_OUTS_B6_R_11", + "PCIE_WL1END2_7", + "PCIE_PIPERX1DATA14", + "PCIE_MIMRXRDATA24", + "PCIE_SE4BEG2_4", + "PCIE_CFGDEVCONTROLURERRREPORTINGEN", + "PCIE_TRNRD29", + "PCIE_PIPETX6CHARISK0", + "PCIE_PLDBGVEC6", + "PCIE_WW2A2_0", + "PCIE_PIPETX7CHARISK1", + "PCIE_DBGVECA9", + "PCIE_BLOCK_OUTS_B2_R_8", + "PCIE_LNKCLKEN", + "PCIE_MIMRXRDATA10", + "PCIE_IMUX27_L_15", + "PCIE_IMUX8_R_15", + "PCIE_IMUX30_L_14", + "PCIE_PIPETX3CHARISK0", + "PCIE_IMUX36_R_14", + "PCIE_EE4BEG1_4", + "PCIE_CFGVCTCVCMAP0", + "PCIE_WR1END0_0", + "PCIE_PIPERX0PHYSTATUS", + "PCIE_DBGVECC3", + "PCIE_NE4BEG2_11", + "PCIE_NW4A0_8", + "PCIE_LH3_7", + "PCIE_LH5_5", + "PCIE_LOGIC_OUTS_B17_L_8", + "PCIE_WW4END1_12", + "PCIE_MIMRXRDATA6", + "PCIE_IMUX37_R_17", + "PCIE_EE4B2_17", + "PCIE_IMUX5_L_5", + "PCIE_CFGMSGRECEIVEDDEASSERTINTA", + "PCIE_DBGVECA36", + "PCIE_SE4C1_8", + "PCIE_WW4A0_19", + "PCIE_CFGCOMMANDBUSMASTERENABLE", + "PCIE_EE2A2_16", + "PCIE_IMUX22_L_7", + "PCIE_FAN1_L_16", + "PCIE_LOGIC_OUTS_B3_L_7", + "PCIE_DBGVECB0", + "PCIE_WW4A3_2", + "PCIE_IMUX44_R_5", + "PCIE_NE2A2_8", + "PCIE_CFGERRAERHEADERLOG19", + "PCIE_DBGVECB20", + "PCIE_BLOCK_OUTS_B3_L_0", + "PCIE_LOGIC_OUTS_B22_L_9", + "PCIE_ER1BEG2_8", + "PCIE_TRNTD65", + "PCIE_IMUX41_L_16", + "PCIE_TRNRD16", + "PCIE_EL1BEG3_10", + "PCIE_LOGIC_OUTS_B22_L_18", + "PCIE_IMUX23_L_13", + "PCIE_IMUX44_R_13", + "PCIE_IMUX22_R_16", + "PCIE_IMUX44_R_8", + "PCIE_TL2ERRHDR32", + "PCIE_IMUX46_R_4", + "PCIE_LOGIC_OUTS_B4_L_9", + "PCIE_LH12_14", + "PCIE_CFGDSN18", + "PCIE_IMUX42_R_4", + "PCIE_MIMTXRADDR1", + "PCIE_LOGIC_OUTS_B4_L_18", + "PCIE_WW4B1_10", + "PCIE_IMUX42_L_3", + "PCIE_EE4BEG3_19", + "PCIE_IMUX34_L_17", + "PCIE_EE4B3_15", + "PCIE_LOGIC_OUTS_B12_R_5", + "PCIE_IMUX26_R_15", + "PCIE_SE2A0_2", + "PCIE_TRNTD61", + "PCIE_PLTXPMSTATE1", + "PCIE_LOGIC_OUTS_B3_L_0", + "PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS", + "PCIE_DBGVECA55", + "PCIE_IMUX18_L_16", + "PCIE_WR1END3_14", + "PCIE_EE4BEG2_1", + "PCIE_NE2A3_10", + "PCIE_IMUX41_R_11", + "PCIE_CTRL1_R_7", + "PCIE_BLOCK_OUTS_B1_R_5", + "PCIE_DBGVECB49", + "PCIE_EL1BEG0_10", + "PCIE_CTRL0_L_7", + "PCIE_IMUX0_L_11", + "PCIE_LOGIC_OUTS_B17_L_4", + "PCIE_IMUX35_R_7", + "PCIE_CTRL0_L_17", + "PCIE_CFGERRAERHEADERLOG10", + "PCIE_EE2BEG1_11", + "PCIE_SW4END3_9", + "PCIE_IMUX17_R_9", + "PCIE_CFGDEVCONTROLFATALERRREPORTINGEN", + "PCIE_CTRL0_R_8", + "PCIE_MIMRXWDATA32", + "PCIE_PLLTSSMSTATE4", + "PCIE_LH5_14", + "PCIE_LOGIC_OUTS_B19_L_2", + "PCIE_SW2A2_7", + "PCIE_LOGIC_OUTS_B13_L_1", + "PCIE_BYP2_R_16", + "PCIE_IMUX1_L_14", + "PCIE_CFGERRATOMICEGRESSBLOCKEDN", + "PCIE_FAN5_R_8", + "PCIE_PIPETXRESET", + "PCIE_TL2ERRHDR12", + "PCIE_MIMRXWDATA25", + "PCIE_TL2ERRHDR50", + "PCIE_TRNTD52", + "PCIE_EE4C1_3", + "PCIE_CFGSUBSYSVENDID7", + "PCIE_XILUNCONNOUT18", + "PCIE_WL1END0_8", + "PCIE_WW4A1_5", + "PCIE_WW4END2_9", + "PCIE_DBGVECA40", + "PCIE_MIMTXWDATA10", + "PCIE_LOGIC_OUTS_B8_R_0", + "PCIE_IMUX19_R_15", + "PCIE_IMUX16_R_11", + "PCIE_EE2A0_18", + "PCIE_EE4A0_13", + "PCIE_IMUX45_L_14", + "PCIE_SE2A3_11", + "PCIE_TRNRD18", + "PCIE_TRNFCNPD4", + "PCIE_IMUX24_R_6", + "PCIE_EE4BEG2_11", + "PCIE_MIMTXRDATA50", + "PCIE_TRNRBARHIT7", + "PCIE_LOGIC_OUTS_B18_L_4", + "PCIE_NE4BEG3_2", + "PCIE_LOGIC_OUTS_B9_R_2", + "PCIE_IMUX33_R_0", + "PCIE_NW4A2_0", + "PCIE_PIPETX1CHARISK1", + "PCIE_LH9_3", + "PCIE_TRNTD49", + "PCIE_LOGIC_OUTS_B6_R_14", + "PCIE_MIMRXWADDR11", + "PCIE_EL1BEG1_16", + "PCIE_EE2BEG1_18", + "PCIE_FAN7_R_7", + "PCIE_EE4BEG1_14", + "PCIE_IMUX2_L_18", + "PCIE_IMUX12_R_16", + "PCIE_LOGIC_OUTS_B20_L_4", + "PCIE_EE4C3_14", + "PCIE_EE4A2_5", + "PCIE_IMUX15_L_17", + "PCIE_TRNRBARHIT0", + "PCIE_CTRL1_L_14", + "PCIE_IMUX5_L_4", + "PCIE_WW2END1_0", + "PCIE_SE2A0_12", + "PCIE_BYP0_L_15", + "PCIE_CFGPORTNUMBER1", + "PCIE_LOGIC_OUTS_B22_L_2", + "PCIE_FAN4_R_13", + "PCIE_IMUX39_R_5", + "PCIE_SW4A3_3", + "PCIE_LOGIC_OUTS_B20_R_19", + "PCIE_CFGSUBSYSID14", + "PCIE_WW4END3_0", + "PCIE_WW4END0_12", + "PCIE_PIPERX6VALID", + "PCIE_BYP1_L_12", + "PCIE_TRNTD112", + "PCIE_IMUX26_R_7", + "PCIE_BYP5_R_15", + "PCIE_BYP3_L_0", + "PCIE_USERCLKPREBUF", + "PCIE_IMUX23_L_19", + "PCIE_MIMRXWDATA26", + "PCIE_CFGMGMTDWADDR7", + "PCIE_NW4A2_9", + "PCIE_LOGIC_OUTS_B10_L_9", + "PCIE_IMUX15_L_7", + "PCIE_WR1END1_19", + "PCIE_SW2A2_17", + "PCIE_FAN6_L_2", + "PCIE_NE4C3_19", + "PCIE_SE2A2_13", + "PCIE_IMUX43_R_14", + "PCIE_MIMRXRDATA62", + "PCIE_TRNRDLLPDATA47", + "PCIE_IMUX17_L_14", + "PCIE_IMUX25_R_8", + "PCIE_TRNRD66", + "PCIE_LOGIC_OUTS_B0_R_17", + "PCIE_WR1END0_8", + "PCIE_LOGIC_OUTS_B23_L_4", + "PCIE_LOGIC_OUTS_B8_L_18", + "PCIE_PLRECEIVEDHOTRST", + "PCIE_CFGERRAERHEADERLOG32", + "PCIE_IMUX27_L_19", + "PCIE_IMUX24_L_3", + "PCIE_IMUX22_L_12", + "PCIE_EL1BEG1_14", + "PCIE_CFGDSFUNCTIONNUMBER2", + "PCIE_LOGIC_OUTS_B0_R_15", + "PCIE_LOGIC_OUTS_B18_R_19", + "PCIE_LOGIC_OUTS_B16_R_1", + "PCIE_FAN6_R_12", + "PCIE_IMUX14_L_13", + "PCIE_PIPERX6DATA1", + "PCIE_TRNFCPD8", + "PCIE_LOGIC_OUTS_B7_L_10", + "PCIE_PIPERX6STATUS2", + "PCIE_LOGIC_OUTS_B1_R_10", + "PCIE_CTRL0_R_4", + "PCIE_BLOCK_OUTS_B1_L_5", + "PCIE_IMUX17_L_0", + "PCIE_IMUX24_L_6", + "PCIE_WW4C1_3", + "PCIE_IMUX32_R_9", + "PCIE_LOGIC_OUTS_B9_R_1", + "PCIE_NW2A2_0", + "PCIE_LOGIC_OUTS_B7_L_5", + "PCIE_CFGDEVID9", + "PCIE_CFGMGMTDWADDR3", + "PCIE_WL1END2_15", + "PCIE_MIMTXRDATA31", + "PCIE_SE2A2_16", + "PCIE_IMUX23_R_13", + "PCIE_IMUX14_R_10", + "PCIE_LOGIC_OUTS_B3_L_4", + "PCIE_PIPERX2DATA11", + "PCIE_WL1END1_0", + "PCIE_NW4END0_3", + "PCIE_CFGERRAERHEADERLOG22", + "PCIE_LOGIC_OUTS_B5_L_4", + "PCIE_PIPERX7DATA11", + "PCIE_IMUX11_L_5", + "PCIE_TRNFCNPD2", + "PCIE_LOGIC_OUTS_B16_R_0", + "PCIE_LOGIC_OUTS_B9_R_14", + "PCIE_BLOCK_OUTS_B3_L_4", + "PCIE_SE4BEG3_0", + "PCIE_WW2END1_19", + "PCIE_IMUX43_L_10", + "PCIE_LOGIC_OUTS_B17_R_1", + "PCIE_LOGIC_OUTS_B16_L_17", + "PCIE_IMUX33_L_10", + "PCIE_SW4END3_15", + "PCIE_EE4A2_18", + "PCIE_MIMRXRDATA2", + "PCIE_SW2A3_0", + "PCIE_CFGINTERRUPTN", + "PCIE_TL2ERRHDR61", + "PCIE_PIPERX5DATA4", + "PCIE_TRNTD120", + "PCIE_EE4B3_17", + "PCIE_TRNRD112", + "PCIE_IMUX45_L_17", + "PCIE_EE4C0_16", + "PCIE_CFGSUBSYSVENDID15", + "PCIE_EE4B3_4", + "PCIE_EE2A1_17", + "PCIE_DBGVECA41", + "PCIE_MIMTXWDATA48", + "PCIE_IMUX34_L_11", + "PCIE_SE4BEG1_11", + "PCIE_PLDIRECTEDLTSSMNEW3", + "PCIE_PIPERX6DATA14", + "PCIE_CFGVENDID9", + "PCIE_SW4A2_0", + "PCIE_BYP6_R_17", + "PCIE_CLK1_L_16", + "PCIE_IMUX40_R_10", + "PCIE_CFGSUBSYSVENDID2", + "PCIE_IMUX22_R_19", + "PCIE_DBGVECB17", + "PCIE_IMUX4_L_2", + "PCIE_EE4A2_8", + "PCIE_IMUX20_L_7", + "PCIE_LOGIC_OUTS_B9_L_15", + "PCIE_BYP7_L_17", + "PCIE_EE4B1_7", + "PCIE_IMUX9_L_18", + "PCIE_WR1END3_3", + "PCIE_IMUX17_R_6", + "PCIE_TL2ERRHDR35", + "PCIE_CFGSUBSYSID9", + "PCIE_IMUX31_R_14", + "PCIE_PIPERX1DATA15", + "PCIE_LOGIC_OUTS_B9_L_1", + "PCIE_LOGIC_OUTS_B4_L_2", + "PCIE_LOGIC_OUTS_B19_R_10", + "PCIE_NE4BEG3_3", + "PCIE_PIPETX5DATA8", + "PCIE_LOGIC_OUTS_B0_L_10", + "PCIE_CTRL0_L_3", + "PCIE_IMUX38_R_5", + "PCIE_IMUX41_R_18", + "PCIE_TRNRDLLPDATA43", + "PCIE_PLDBGMODE1", + "PCIE_MIMTXWDATA9", + "PCIE_CFGDSDEVICENUMBER4", + "PCIE_FAN0_R_19", + "PCIE_LOGIC_OUTS_B5_R_3", + "PCIE_IMUX25_R_2", + "PCIE_SW2A0_11", + "PCIE_TRNTD98", + "PCIE_LOGIC_OUTS_B11_R_16", + "PCIE_FAN7_L_12", + "PCIE_SE2A1_17", + "PCIE_LOGIC_OUTS_B7_R_15", + "PCIE_TRNRD123", + "PCIE_BYP7_R_17", + "PCIE_TRNTD117", + "PCIE_CFGMSGDATA3", + "PCIE_IMUX12_L_5", + "PCIE_BYP3_R_13", + "PCIE_WW4C0_19", + "PCIE_PIPERX4DATA8", + "PCIE_TRNTSTR", + "PCIE_SE4C1_11", + "PCIE_WW4C2_14", + "PCIE_WR1END1_5", + "PCIE_MIMTXWDATA43", + "PCIE_LOGIC_OUTS_B21_R_16", + "PCIE_FAN0_R_6", + "PCIE_PIPERX5DATA14", + "PCIE_CFGERRAERHEADERLOG51", + "PCIE_PIPERX2DATA3", + "PCIE_MIMRXRDATA33", + "PCIE_TRNRDLLPDATA39", + "PCIE_EE2A0_9", + "PCIE_IMUX23_L_12", + "PCIE_IMUX29_L_0", + "PCIE_IMUX44_L_10", + "PCIE_BYP7_R_5", + "PCIE_TL2ERRHDR62", + "PCIE_IMUX34_L_2", + "PCIE_BYP2_R_13", + "PCIE_PIPERX5VALID", + "PCIE_IMUX11_L_2", + "PCIE_MIMTXRDATA23", + "PCIE_LH8_16", + "PCIE_FAN7_L_9", + "PCIE_WW2A1_0", + "PCIE_TRNRDLLPDATA28", + "PCIE_PLDBGVEC10", + "PCIE_BLOCK_OUTS_B3_L_12", + "PCIE_WR1END1_11", + "PCIE_CFGMSGDATA14", + "PCIE_IMUX0_L_10", + "PCIE_IMUX25_L_2", + "PCIE_PIPETX4DATA5", + "PCIE_EE4A0_12", + "PCIE_IMUX25_L_17", + "PCIE_EE2BEG0_9", + "PCIE_LH12_17", + "PCIE_WW4C3_3", + "PCIE_LOGIC_OUTS_B9_R_17", + "PCIE_EE4B1_13", + "PCIE_DBGVECB10", + "PCIE_LOGIC_OUTS_B23_R_0", + "PCIE_IMUX18_R_19", + "PCIE_IMUX46_R_2", + "PCIE_TL2ERRHDR43", + "PCIE_LOGIC_OUTS_B3_L_12", + "PCIE_IMUX3_L_9", + "PCIE_CTRL1_R_0", + "PCIE_SW2A2_1", + "PCIE_SW4END0_19", + "PCIE_TRNTSOF", + "PCIE_IMUX39_R_15", + "PCIE_TRNTD25", + "PCIE_IMUX10_R_4", + "PCIE_NE4BEG3_16", + "PCIE_IMUX10_R_0", + "PCIE_WL1END1_10", + "PCIE_IMUX2_R_15", + "PCIE_LOGIC_OUTS_B0_R_9", + "PCIE_LOGIC_OUTS_B4_L_13", + "PCIE_FAN2_L_19", + "PCIE_CTRL1_R_6", + "PCIE_LOGIC_OUTS_B18_L_14", + "PCIE_MIMTXRADDR4", + "PCIE_BYP7_L_14", + "PCIE_CFGREVID3", + "PCIE_IMUX29_L_17", + "PCIE_NW2A3_13", + "PCIE_DBGVECA5", + "PCIE_IMUX27_L_9", + "PCIE_IMUX34_L_19", + "PCIE_EE4B3_12", + "PCIE_PIPERX5DATA10", + "PCIE_SE4C2_12", + "PCIE_CLK1_L_9", + "PCIE_TRNRD110", + "PCIE_PIPETX3DATA14", + "PCIE_IMUX19_R_16", + "PCIE_FAN6_R_1", + "PCIE_NW4A3_8", + "PCIE_TRNFCNPD8", + "PCIE_PIPERX0DATA8", + "PCIE_IMUX0_R_2", + "PCIE_MIMTXWDATA62", + "PCIE_TRNFCNPH5", + "PCIE_IMUX16_L_10", + "PCIE_LOGIC_OUTS_B14_L_5", + "PCIE_NE2A0_6", + "PCIE_DRPDO10", + "PCIE_BYP7_L_13", + "PCIE_IMUX45_R_1", + "PCIE_TRNRDLLPDATA16", + "PCIE_IMUX14_L_14", + "PCIE_IMUX23_L_17", + "PCIE_IMUX0_L_5", + "PCIE_FAN2_L_16", + "PCIE_LOGIC_OUTS_B21_R_9", + "PCIE_IMUX3_R_4", + "PCIE_TRNTD118", + "PCIE_TRNRD113", + "PCIE_SE4BEG0_7", + "PCIE_BLOCK_OUTS_B0_L_15", + "PCIE_NE2A0_1", + "PCIE_CFGMGMTDO10", + "PCIE_MIMTXWDATA59", + "PCIE_EE4BEG2_0", + "PCIE_LH5_2", + "PCIE_LOGIC_OUTS_B21_L_12", + "PCIE_IMUX16_R_5", + "PCIE_LOGIC_OUTS_B17_L_17", + "PCIE_BYP5_L_16", + "PCIE_BYP7_R_11", + "PCIE_MIMRXRDATA42", + "PCIE_BYP0_R_2", + "PCIE_IMUX38_R_19", + "PCIE_SW4END2_4", + "PCIE_LOGIC_OUTS_B9_R_7", + "PCIE_LOGIC_OUTS_B19_R_3", + "PCIE_WW4END3_11", + "PCIE_LOGIC_OUTS_B2_L_17", + "PCIE_MIMTXRDATA9", + "PCIE_IMUX6_L_8", + "PCIE_CFGERRAERHEADERLOG102", + "PCIE_IMUX9_R_2", + "PCIE_WW4C3_13", + "PCIE_IMUX45_R_17", + "PCIE_WL1END0_14", + "PCIE_NE4BEG1_15", + "PCIE_PIPERX5DATA11", + "PCIE_NE2A2_5", + "PCIE_PLDBGVEC11", + "PCIE_CTRL1_R_19", + "PCIE_CFGREVID6", + "PCIE_NE4BEG0_19", + "PCIE_TL2ERRHDR34", + "PCIE_SE2A2_3", + "PCIE_LOGIC_OUTS_B20_L_9", + "PCIE_FAN4_L_7", + "PCIE_IMUX37_L_1", + "PCIE_FAN5_R_0", + "PCIE_BYP4_L_18", + "PCIE_PIPERX1STATUS0", + "PCIE_IMUX27_R_5", + "PCIE_TL2ERRHDR24", + "PCIE_IMUX39_R_19", + "PCIE_IMUX7_R_18", + "PCIE_MIMRXWDATA58", + "PCIE_LH1_2", + "PCIE_SE4C1_15", + "PCIE_IMUX26_L_2", + "PCIE_IMUX15_R_7", + "PCIE_LOGIC_OUTS_B1_R_14", + "PCIE_NE4BEG1_2", + "PCIE_IMUX17_R_4", + "PCIE_LOGIC_OUTS_B3_R_19", + "PCIE_IMUX26_R_9", + "PCIE_IMUX8_L_9", + "PCIE_PIPETX0DATA8", + "PCIE_SW4END3_2", + "PCIE_LOGIC_OUTS_B20_L_6", + "PCIE_TRNTD28", + "PCIE_MIMRXWDATA57", + "PCIE_IMUX0_L_1", + "PCIE_IMUX4_R_16", + "PCIE_LOGIC_OUTS_B13_L_2", + "PCIE_MIMRXRDATA57", + "PCIE_IMUX4_L_15", + "PCIE_FAN1_R_11", + "PCIE_CFGPMHALTASPML0SN", + "PCIE_EE2BEG1_15", + "PCIE_NE2A3_1", + "PCIE_CFGMSGRECEIVEDUNLOCK", + "PCIE_LOGIC_OUTS_B10_L_0", + "PCIE_IMUX32_L_7", + "PCIE_LOGIC_OUTS_B14_L_10", + "PCIE_IMUX22_L_10", + "PCIE_WW4B3_19", + "PCIE_WW4END3_9", + "PCIE_LL2REPLAYTOERR", + "PCIE_MIMTXRDATA22", + "PCIE_LH3_12", + "PCIE_IMUX44_R_17", + "PCIE_NE2A3_11", + "PCIE_CFGERRTLPCPLHEADER26", + "PCIE_CFGMGMTDO9", + "PCIE_TRNRDLLPDATA25", + "PCIE_LH9_17", + "PCIE_MIMTXWDATA8", + "PCIE_MIMTXRDATA25", + "PCIE_IMUX3_R_5", + "PCIE_TRNTD75", + "PCIE_IMUX10_R_8", + "PCIE_IMUX17_R_18", + "PCIE_CFGDSN14", + "PCIE_LH6_19", + "PCIE_SE4C3_19", + "PCIE_NE2A1_16", + "PCIE_MIMRXRDATA56", + "PCIE_PIPETX5COMPLIANCE", + "PCIE_FAN4_R_9", + "PCIE_CFGAERROOTERRCORRERRRECEIVED", + "PCIE_TRNTD33", + "PCIE_PIPETX3DATA8", + "PCIE_IMUX39_L_8", + "PCIE_NW2A2_6", + "PCIE_LL2LINKSTATUS3", + "PCIE_IMUX40_L_5", + "PCIE_LOGIC_OUTS_B16_R_12", + "PCIE_LOGIC_OUTS_B4_L_14", + "PCIE_CTRL0_R_12", + "PCIE_IMUX8_L_16", + "PCIE_WW4END0_7", + "PCIE_PLRXPMSTATE0", + "PCIE_CFGPMRCVENTERL1N", + "PCIE_IMUX14_L_1", + "PCIE_LH1_15", + "PCIE_TRNRD103", + "PCIE_IMUX18_R_9", + "PCIE_BLOCK_OUTS_B2_R_10", + "PCIE_SW2A0_4", + "PCIE_PIPETX7DATA1", + "PCIE_WW4A1_1", + "PCIE_FAN5_R_7", + "PCIE_WW4END3_15", + "PCIE_SE4BEG2_15", + "PCIE_NE4C2_18", + "PCIE_WW4END3_8", + "PCIE_LOGIC_OUTS_B8_L_15", + "PCIE_IMUX42_L_0", + "PCIE_WW4B3_4", + "PCIE_WW2END0_8", + "PCIE_IMUX23_R_10", + "PCIE_WW2END0_15", + "PCIE_BYP1_R_19", + "PCIE_WW4A0_9", + "PCIE_LOGIC_OUTS_B8_L_3", + "PCIE_SE4C0_14", + "PCIE_CFGERRAERHEADERLOG41", + "PCIE_WL1END2_5", + "PCIE_IMUX45_L_19", + "PCIE_EE4B1_16", + "PCIE_BYP6_L_3", + "PCIE_NE4C3_5", + "PCIE_FAN3_L_7", + "PCIE_PL2SUSPENDOK", + "PCIE_WW4A1_18", + "PCIE_WL1END3_17", + "PCIE_FAN5_L_2", + "PCIE_DBGVECB41", + "PCIE_WL1END1_6", + "PCIE_PIPETX5DATA0", + "PCIE_WW2END2_5", + "PCIE_SE4BEG3_13", + "PCIE_NW4END3_3", + "PCIE_TRNTD29", + "PCIE_WW4A2_13", + "PCIE_WL1END1_18", + "PCIE_WR1END2_3", + "PCIE_TRNTD11", + "PCIE_PLDBGVEC9", + "PCIE_LH1_9", + "PCIE_PLSELLNKWIDTH0", + "PCIE_NE2A3_15", + "PCIE_EE4A2_7", + "PCIE_MIMTXWDATA17", + "PCIE_TRNRD90", + "PCIE_BYP1_L_4", + "PCIE_CLK0_R_6", + "PCIE_CLK0_L_17", + "PCIE_WW4C2_4", + "PCIE_IMUX3_R_9", + "PCIE_IMUX37_L_7", + "PCIE_SW4END2_19", + "PCIE_LOGIC_OUTS_B3_R_15", + "PCIE_EE4BEG1_16", + "PCIE_CFGDEVCONTROLAUXPOWEREN", + "PCIE_LL2LINKSTATUS1", + "PCIE_TRNRD79", + "PCIE_FAN3_R_5", + "PCIE_NE4C1_17", + "PCIE_CFGERRAERHEADERLOG85", + "PCIE_IMUX25_R_5", + "PCIE_WL1END3_13", + "PCIE_LOGIC_OUTS_B15_L_5", + "PCIE_IMUX9_R_5", + "PCIE_SW4END3_5", + "PCIE_IMUX36_L_18", + "PCIE_PIPERX5DATA0", + "PCIE_IMUX17_R_1", + "PCIE_TRNRDLLPDATA26", + "PCIE_TRNRDLLPDATA22", + "PCIE_TRNTDSTRDY0", + "PCIE_PL2L0REQ", + "PCIE_FAN6_L_10", + "PCIE_PIPERX5DATA9", + "PCIE_IMUX3_R_8", + "PCIE_IMUX36_R_1", + "PCIE_IMUX13_L_9", + "PCIE_PIPERX3CHARISK1", + "PCIE_TRNRDLLPDATA20", + "PCIE_IMUX35_L_15", + "PCIE_SE4C2_7", + "PCIE_NW4A2_5", + "PCIE_LOGIC_OUTS_B2_L_1", + "PCIE_LOGIC_OUTS_B3_R_17", + "PCIE_EE2BEG3_16", + "PCIE_IMUX36_R_12", + "PCIE_IMUX2_R_11", + "PCIE_LOGIC_OUTS_B8_R_15", + "PCIE_LOGIC_OUTS_B17_R_12", + "PCIE_EL1BEG0_19", + "PCIE_LOGIC_OUTS_B20_R_14", + "PCIE_CFGAERROOTERRFATALERRRECEIVED", + "PCIE_SW4A2_11", + "PCIE_LOGIC_OUTS_B19_L_1", + "PCIE_IMUX25_L_0", + "PCIE_LOGIC_OUTS_B14_L_3", + "PCIE_TRNTDSTRDY2", + "PCIE_WR1END0_7", + "PCIE_IMUX24_R_2", + "PCIE_EE2A2_10", + "PCIE_NE2A1_12", + "PCIE_ER1BEG3_10", + "PCIE_IMUX1_R_11", + "PCIE_LH2_9", + "PCIE_TRNTBUFAV0", + "PCIE_SW4A2_8", + "PCIE_LOGIC_OUTS_B20_R_3", + "PCIE_CLK1_R_1", + "PCIE_TRNTD7", + "PCIE_EDTCHANNELSIN4", + "PCIE_PIPETX2DATA6", + "PCIE_PIPETX7DATA10", + "PCIE_IMUX25_R_1", + "PCIE_BLOCK_OUTS_B1_R_10", + "PCIE_DBGVECB7", + "PCIE_NE2A0_5", + "PCIE_LOGIC_OUTS_B21_R_19", + "PCIE_PIPERX3DATA10", + "PCIE_TRNTD39", + "PCIE_IMUX45_L_15", + "PCIE_IMUX44_L_8", + "PCIE_FAN0_L_9", + "PCIE_SW4END3_7", + "PCIE_LOGIC_OUTS_B16_L_1", + "PCIE_LH8_10", + "PCIE_TRNTD124", + "PCIE_IMUX35_R_15", + "PCIE_DBGVECC8", + "PCIE_SE4C3_17", + "PCIE_FAN7_R_4", + "PCIE_IMUX32_R_17", + "PCIE_FAN5_R_3", + "PCIE_PIPETX7CHARISK0", + "PCIE_CFGERRTLPCPLHEADER42", + "PCIE_PLDIRECTEDLINKAUTON", + "PCIE_IMUX12_L_7", + "PCIE_BYP1_L_17", + "PCIE_NE2A2_6", + "PCIE_NW4A3_0", + "PCIE_PIPERX6POLARITY", + "PCIE_FAN0_L_15", + "PCIE_TRNTD119", + "PCIE_SW4A3_13", + "PCIE_LOGIC_OUTS_B14_R_7", + "PCIE_WW4B0_12", + "PCIE_CFGERRNORECOVERYN", + "PCIE_EL1BEG1_4", + "PCIE_LOGIC_OUTS_B9_L_5", + "PCIE_NW4END3_17", + "PCIE_SW4END2_2", + "PCIE_BYP2_L_5", + "PCIE_MIMRXWDATA28", + "PCIE_WW4END1_14", + "PCIE_WW4END3_17", + "PCIE_PIPERX3DATA6", + "PCIE_IMUX36_R_5", + "PCIE_FAN7_L_13", + "PCIE_IMUX40_R_4", + "PCIE_FAN5_L_9", + "PCIE_PIPETX6POWERDOWN0", + "PCIE_CTRL1_L_2", + "PCIE_LOGIC_OUTS_B13_R_3", + "PCIE_NE4C1_2", + "PCIE_IMUX20_L_9", + "PCIE_PLDBGVEC8", + "PCIE_MIMTXWDATA13", + "PCIE_EE2A1_14", + "PCIE_IMUX40_R_12", + "PCIE_IMUX40_L_11", + "PCIE_NW2A1_5", + "PCIE_TRNRDLLPDATA49", + "PCIE_LOGIC_OUTS_B3_R_7", + "PCIE_TRNRREM0", + "PCIE_IMUX13_L_13", + "PCIE_MIMRXWDATA4", + "PCIE_IMUX20_L_1", + "PCIE_CFGPCIELINKSTATE2", + "PCIE_EE4BEG1_12", + "PCIE_WW4A1_0", + "PCIE_SE2A3_9", + "PCIE_LH4_1", + "PCIE_EE2BEG0_3", + "PCIE_FAN3_R_13", + "PCIE_WL1END0_9", + "PCIE_SE4C1_5", + "PCIE_DBGVECA49", + "PCIE_WR1END1_8", + "PCIE_LOGIC_OUTS_B11_L_1", + "PCIE_TRNTDLLPDATA21", + "PCIE_CFGSUBSYSID6", + "PCIE_PIPERX6DATA0", + "PCIE_EL1BEG3_1", + "PCIE_IMUX37_L_8", + "PCIE_IMUX13_L_10", + "PCIE_PIPERX3STATUS0", + "PCIE_PLDBGMODE2", + "PCIE_IMUX47_R_16", + "PCIE_LH1_8", + "PCIE_SE4BEG3_6", + "PCIE_ER1BEG3_6", + "PCIE_LOGIC_OUTS_B23_L_14", + "PCIE_PIPETX2POWERDOWN0", + "PCIE_NW4A0_10", + "PCIE_BYP7_R_6", + "PCIE_LOGIC_OUTS_B14_L_19", + "PCIE_EE4C2_15", + "PCIE_PLDIRECTEDLTSSMNEW5", + "PCIE_SE2A3_12", + "PCIE_EE2A2_0", + "PCIE_FAN4_R_5", + "PCIE_LOGIC_OUTS_B17_L_3", + "PCIE_MONITOR_N_9", + "PCIE_WW2END0_9", + "PCIE_LOGIC_OUTS_B21_R_2", + "PCIE_NE2A2_12", + "PCIE_SE4BEG2_17", + "PCIE_TL2ERRHDR57", + "PCIE_NW4END0_10", + "PCIE_BYP0_L_2", + "PCIE_SE2A1_7", + "PCIE_CFGMSGDATA15", + "PCIE_MIMRXRDATA50", + "PCIE_XILUNCONNOUT9", + "PCIE_IMUX37_R_5", + "PCIE_EE2BEG2_18", + "PCIE_LOGIC_OUTS_B17_R_18", + "PCIE_IMUX28_R_17", + "PCIE_LOGIC_OUTS_B6_R_15", + "PCIE_TRNRDLLPDATA46", + "PCIE_DBGSCLRJ", + "PCIE_LH12_3", + "PCIE_IMUX45_L_9", + "PCIE_LOGIC_OUTS_B17_R_14", + "PCIE_SE4BEG2_8", + "PCIE_LOGIC_OUTS_B5_R_4", + "PCIE_IMUX33_L_16", + "PCIE_TL2ERRHDR49", + "PCIE_CFGERRAERHEADERLOG18", + "PCIE_WW4END1_11", + "PCIE_IMUX10_L_9", + "PCIE_BYP7_L_16", + "PCIE_NE4C0_16", + "PCIE_WW2END0_0", + "PCIE_LOGIC_OUTS_B18_L_6", + "PCIE_WW4C0_15", + "PCIE_WW2END3_12", + "PCIE_BLOCK_OUTS_B0_R_16", + "PCIE_ER1BEG2_11", + "PCIE_IMUX12_R_9", + "PCIE_IMUX17_L_15", + "PCIE_TRNRD41", + "PCIE_TRNRD119", + "PCIE_BYP2_L_12", + "PCIE_IMUX11_L_6", + "PCIE_CFGPORTNUMBER4", + "PCIE_TRNTD85", + "PCIE_EE4BEG2_17", + "PCIE_IMUX11_R_4", + "PCIE_TRNFCCPLD2", + "PCIE_SE2A1_16", + "PCIE_IMUX41_R_2", + "PCIE_IMUX37_R_3", + "PCIE_EL1BEG2_13", + "PCIE_DBGMODE0", + "PCIE_DBGVECB8", + "PCIE_WW2A3_4", + "PCIE_SE2A2_1", + "PCIE_LOGIC_OUTS_B7_L_19", + "PCIE_WW4B3_12", + "PCIE_SW4END0_5", + "PCIE_LOGIC_OUTS_B23_L_18", + "PCIE_WW2END1_9", + "PCIE_BYP0_L_19", + "PCIE_BYP6_L_14", + "PCIE_FAN1_R_8", + "PCIE_LH1_14", + "PCIE_IMUX20_L_13", + "PCIE_SW4END3_18", + "PCIE_BLOCK_OUTS_B3_R_5", + "PCIE_SW2A1_1", + "PCIE_IMUX21_R_11", + "PCIE_TRNTD15", + "PCIE_LOGIC_OUTS_B17_R_8", + "PCIE_EE2A3_14", + "PCIE_IMUX27_L_10", + "PCIE_LOGIC_OUTS_B21_R_17", + "PCIE_WW4C2_6", + "PCIE_WW4C3_14", + "PCIE_SW4A1_13", + "PCIE_IMUX11_R_11", + "PCIE_IMUX11_L_14", + "PCIE_LOGIC_OUTS_B2_L_6", + "PCIE_FAN1_R_16", + "PCIE_CFGERRAERHEADERLOG11", + "PCIE_NW4END0_4", + "PCIE_TRNRBARHIT6", + "PCIE_LOGIC_OUTS_B19_L_7", + "PCIE_LOGIC_OUTS_B23_R_1", + "PCIE_WW2A2_12", + "PCIE_TRNTD88", + "PCIE_SE2A3_13", + "PCIE_LOGIC_OUTS_B2_R_4", + "PCIE_CFGMGMTDO1", + "PCIE_PIPETX4DATA10", + "PCIE_NW4A2_3", + "PCIE_NW4A2_6", + "PCIE_NE4BEG2_6", + "PCIE_WW2END1_8", + "PCIE_LOGIC_OUTS_B4_R_12", + "PCIE_IMUX12_L_13", + "PCIE_IMUX30_L_6", + "PCIE_EL1BEG2_5", + "PCIE_IMUX32_L_19", + "PCIE_IMUX25_R_4", + "PCIE_IMUX4_R_10", + "PCIE_EL1BEG0_2", + "PCIE_CFGDSDEVICENUMBER3", + "PCIE_IMUX37_L_14", + "PCIE_IMUX47_R_7", + "PCIE_TRNRD106", + "PCIE_NW2A1_10", + "PCIE_EE4BEG1_1", + "PCIE_IMUX3_L_4", + "PCIE_NW4A2_12", + "PCIE_MIMRXRDATA4", + "PCIE_LOGIC_OUTS_B11_R_11", + "PCIE_SE4C1_2", + "PCIE_IMUX15_R_16", + "PCIE_DBGVECA53", + "PCIE_TRNRD127", + "PCIE_NW4END1_9", + "PCIE_BLOCK_OUTS_B3_L_11", + "PCIE_TRNFCSEL2", + "PCIE_IMUX7_R_19", + "PCIE_NE2A1_18", + "PCIE_BYP0_L_18", + "PCIE_CFGDSBUSNUMBER0", + "PCIE_NW4A1_15", + "PCIE_LOGIC_OUTS_B4_L_5", + "PCIE_IMUX5_L_18", + "PCIE_TRNRD115", + "PCIE_LH11_6", + "PCIE_MIMTXWDATA26", + "PCIE_IMUX30_R_18", + "PCIE_SW2A2_11", + "PCIE_EE4C0_9", + "PCIE_CTRL1_L_13", + "PCIE_WW2END0_6", + "PCIE_EL1BEG1_11", + "PCIE_LOGIC_OUTS_B4_L_7", + "PCIE_DBGVECA1", + "PCIE_IMUX23_L_16", + "PCIE_FAN0_L_11", + "PCIE_FAN1_L_4", + "PCIE_LOGIC_OUTS_B13_R_12", + "PCIE_EE4C1_0", + "PCIE_DBGVECB2", + "PCIE_EE4BEG0_9", + "PCIE_WW2A1_6", + "PCIE_SW2A2_3", + "PCIE_IMUX1_L_19", + "PCIE_BLOCK_OUTS_B3_L_6", + "PCIE_FAN1_R_18", + "PCIE_TRNTD94", + "PCIE_IMUX45_L_3", + "PCIE_PL2LINKUP", + "PCIE_EE2A0_2", + "PCIE_NW4A2_2", + "PCIE_IMUX36_L_9", + "PCIE_MIMTXWDATA38", + "PCIE_EE4A3_18", + "PCIE_DRPDO8", + "PCIE_IMUX13_L_15", + "PCIE_IMUX34_L_13", + "PCIE_IMUX20_R_19", + "PCIE_DRPDI14", + "PCIE_DBGVECB38", + "PCIE_LOGIC_OUTS_B12_L_12", + "PCIE_BYP4_L_19", + "PCIE_SW4END3_11", + "PCIE_CFGDEVCONTROL2ATOMICEGRESSBLOCK", + "PCIE_IMUX44_L_7", + "PCIE_SW4A2_6", + "PCIE_LL2BADTLPERR", + "PCIE_NW4A1_0", + "PCIE_IMUX1_L_16", + "PCIE_EE4A3_6", + "PCIE_BLOCK_OUTS_B1_R_4", + "PCIE_WR1END0_4", + "PCIE_IMUX21_R_7", + "PCIE_IMUX1_L_0", + "PCIE_CFGINTERRUPTDI2", + "PCIE_FAN1_L_19", + "PCIE_PIPERX4DATA4", + "PCIE_PIPERX6DATA4", + "PCIE_IMUX11_R_1", + "PCIE_NW4A0_2", + "PCIE_FAN1_L_2", + "PCIE_IMUX26_R_16", + "PCIE_IMUX46_R_5", + "PCIE_BYP4_L_0", + "PCIE_IMUX28_L_3", + "PCIE_IMUX47_L_9", + "PCIE_FAN0_L_18", + "PCIE_LOGIC_OUTS_B22_L_19", + "PCIE_IMUX41_L_3", + "PCIE_IMUX19_L_18", + "PCIE_WW4C3_17", + "PCIE_IMUX26_L_13", + "PCIE_EE2BEG0_7", + "PCIE_IMUX30_L_10", + "PCIE_CLK1_R_6", + "PCIE_LOGIC_OUTS_B11_R_2", + "PCIE_TRNTDLLPDATA4", + "PCIE_IMUX7_R_16", + "PCIE_TRNTD74", + "PCIE_SE4C3_8", + "PCIE_TRNTBUFAV2", + "PCIE_MIMRXWDATA43", + "PCIE_IMUX4_R_17", + "PCIE_MONITOR_N_10", + "PCIE_LOGIC_OUTS_B17_R_19", + "PCIE_LOGIC_OUTS_B7_L_3", + "PCIE_ER1BEG1_3", + "PCIE_LOGIC_OUTS_B7_L_8", + "PCIE_DBGVECA10", + "PCIE_SE4C1_16", + "PCIE_LOGIC_OUTS_B10_L_10", + "PCIE_IMUX19_L_14", + "PCIE_LOGIC_OUTS_B3_R_16", + "PCIE_WR1END1_13", + "PCIE_MIMRXWEN", + "PCIE_IMUX46_R_8", + "PCIE_MONITOR_N_17", + "PCIE_IMUX44_L_2", + "PCIE_NE2A3_16", + "PCIE_TRNTD36", + "PCIE_XILUNCONNOUT36", + "PCIE_PIPERX4CHANISALIGNED", + "PCIE_CFGERRTLPCPLHEADER21", + "PCIE_WL1END0_7", + "PCIE_WR1END0_14", + "PCIE_BLOCK_OUTS_B1_R_2", + "PCIE_DBGVECA48", + "PCIE_BLOCK_OUTS_B3_L_3", + "PCIE_TRNRDLLPDATA24", + "PCIE_IMUX23_R_3", + "PCIE_BYP4_L_2", + "PCIE_LOGIC_OUTS_B5_L_8", + "PCIE_MIMTXRDATA11", + "PCIE_SE2A0_9", + "PCIE_IMUX15_R_10", + "PCIE_IMUX44_R_12", + "PCIE_LOGIC_OUTS_B20_L_0", + "PCIE_IMUX39_R_13", + "PCIE_SW4END3_3", + "PCIE_EE4A2_0", + "PCIE_IMUX23_R_7", + "PCIE_LH5_10", + "PCIE_SW4END1_8", + "PCIE_IMUX23_L_9", + "PCIE_CTRL1_R_8", + "PCIE_IMUX8_R_17", + "PCIE_IMUX32_R_5", + "PCIE_PIPETX2DATA0", + "PCIE_IMUX7_L_0", + "PCIE_LH4_19", + "PCIE_IMUX18_L_13", + "PCIE_LOGIC_OUTS_B14_R_18", + "PCIE_NE4C3_10", + "PCIE_EE4BEG0_1", + "PCIE_EE4A1_1", + "PCIE_NW4A3_17", + "PCIE_EE2BEG1_19", + "PCIE_CFGSUBSYSVENDID10", + "PCIE_NW2A0_18", + "PCIE_WR1END3_15", + "PCIE_WW2END3_2", + "PCIE_CFGSUBSYSID8", + "PCIE_IMUX31_R_5", + "PCIE_IMUX23_R_19", + "PCIE_MONITOR_P_4", + "PCIE_LOGIC_OUTS_B16_R_10", + "PCIE_TRNRDLLPDATA59", + "PCIE_IMUX44_L_0", + "PCIE_LOGIC_OUTS_B6_L_9", + "PCIE_SE2A2_2", + "PCIE_NE4BEG0_0", + "PCIE_IMUX31_R_8", + "PCIE_TRNRD77", + "PCIE_IMUX14_R_13", + "PCIE_IMUX34_L_0", + "PCIE_LOGIC_OUTS_B23_R_15", + "PCIE_IMUX29_L_6", + "PCIE_NW2A3_17", + "PCIE_IMUX27_R_9", + "PCIE_LOGIC_OUTS_B15_L_6", + "PCIE_BYP4_L_13", + "PCIE_ER1BEG0_9", + "PCIE_TL2ERRRXOVERFLOW", + "PCIE_IMUX9_L_14", + "PCIE_LH8_19", + "PCIE_IMUX34_L_5", + "PCIE_SE4C3_9", + "PCIE_WR1END3_0", + "PCIE_NE4C1_19", + "PCIE_IMUX40_R_14", + "PCIE_SW2A1_2", + "PCIE_XILUNCONNOUT35", + "PCIE_BYP2_R_0", + "PCIE_SE2A1_2", + "PCIE_LOGIC_OUTS_B11_R_12", + "PCIE_CFGDEVCONTROL2IDOCPLEN", + "PCIE_SW2A2_14", + "PCIE_IMUX3_R_1", + "PCIE_SW2A1_8", + "PCIE_WW4B2_7", + "PCIE_IMUX27_L_11", + "PCIE_IMUX35_L_1", + "PCIE_WW4END3_18", + "PCIE_TRNTDLLPDATA12", + "PCIE_IMUX15_R_0", + "PCIE_IMUX46_L_3", + "PCIE_WW4C0_1", + "PCIE_IMUX28_L_4", + "PCIE_WW2A0_2", + "PCIE_LOGIC_OUTS_B20_R_10", + "PCIE_CFGERRAERHEADERLOG67", + "PCIE_WW4C0_9", + "PCIE_TL2ERRHDR52", + "PCIE_CTRL0_L_18", + "PCIE_NE4BEG3_6", + "PCIE_FAN6_L_19", + "PCIE_CFGDEVCONTROLMAXPAYLOAD2", + "PCIE_NE2A3_18", + "PCIE_IMUX36_R_4", + "PCIE_PIPERX3ELECIDLE", + "PCIE_MIMRXWDATA42", + "PCIE_CLK0_R_17", + "PCIE_FAN5_R_11", + "PCIE_CTRL1_L_9", + "PCIE_IMUX28_L_12", + "PCIE_ER1BEG0_15", + "PCIE_NE2A1_0", + "PCIE_IMUX12_L_9", + "PCIE_CTRL0_R_6", + "PCIE_WW4B2_12", + "PCIE_NE4BEG2_8", + "PCIE_NE4C2_16", + "PCIE_WL1END3_12", + "PCIE_FAN0_L_8", + "PCIE_LH7_13", + "PCIE_LOGIC_OUTS_B15_R_11", + "PCIE_NE2A3_14", + "PCIE_LOGIC_OUTS_B11_R_3", + "PCIE_PIPETX5DATA7", + "PCIE_CLK0_R_2", + "PCIE_IMUX37_L_12", + "PCIE_IMUX14_L_10", + "PCIE_IMUX44_L_3", + "PCIE_WW2END2_4", + "PCIE_MIMTXWDATA50", + "PCIE_IMUX2_R_5", + "PCIE_IMUX44_L_11", + "PCIE_SW2A3_12", + "PCIE_LH6_5", + "PCIE_CFGVENDID11", + "PCIE_LOGIC_OUTS_B5_L_10", + "PCIE_WW4C0_2", + "PCIE_EDTCHANNELSOUT2", + "PCIE_NE2A3_7", + "PCIE_PIPETX2DATA13", + "PCIE_IMUX16_R_9", + "PCIE_LOGIC_OUTS_B12_L_18", + "PCIE_EE4C0_14", + "PCIE_LOGIC_OUTS_B15_L_8", + "PCIE_IMUX42_R_11", + "PCIE_LOGIC_OUTS_B16_R_18", + "PCIE_IMUX16_R_16", + "PCIE_EE4C3_3", + "PCIE_LL2RECEIVERERR", + "PCIE_WW4C3_0", + "PCIE_PIPERX7ELECIDLE", + "PCIE_NE2A2_9", + "PCIE_SW2A3_1", + "PCIE_FAN0_R_1", + "PCIE_PLSELLNKWIDTH1", + "PCIE_LOGIC_OUTS_B15_R_8", + "PCIE_FAN2_L_3", + "PCIE_IMUX23_R_9", + "PCIE_EE4B1_17", + "PCIE_NW4END2_14", + "PCIE_CLK0_L_18", + "PCIE_PIPERX3CHANISALIGNED", + "PCIE_PIPETX4POWERDOWN1", + "PCIE_CFGAERROOTERRCORRERRREPORTINGEN", + "PCIE_EE2A1_10", + "PCIE_LH3_11", + "PCIE_WL1END0_2", + "PCIE_TL2ERRHDR0", + "PCIE_IMUX2_R_14", + "PCIE_LOGIC_OUTS_B13_R_18", + "PCIE_IMUX17_R_12", + "PCIE_IMUX13_R_12", + "PCIE_NW4A3_5", + "PCIE_LOGIC_OUTS_B7_R_8", + "PCIE_EE4B0_2", + "PCIE_CFGERRTLPCPLHEADER20", + "PCIE_LOGIC_OUTS_B0_R_18", + "PCIE_EL1BEG0_6", + "PCIE_TL2ERRHDR7", + "PCIE_TRNRD67", + "PCIE_LOGIC_OUTS_B0_L_17", + "PCIE_IMUX42_L_9", + "PCIE_EE2A1_2", + "PCIE_PL2RXPMSTATE0", + "PCIE_WW2A1_13", + "PCIE_EE2A0_19", + "PCIE_LH9_0", + "PCIE_LH2_8", + "PCIE_CLK0_R_19", + "PCIE_IMUX23_R_14", + "PCIE_BYP1_L_9", + "PCIE_PIPERX3DATA15", + "PCIE_FAN1_L_17", + "PCIE_SE4BEG3_9", + "PCIE_MIMRXRDATA14", + "PCIE_TRNRD74", + "PCIE_LOGIC_OUTS_B0_L_19", + "PCIE_IMUX5_R_0", + "PCIE_WW4END1_1", + "PCIE_IMUX2_L_17", + "PCIE_MIMTXRADDR12", + "PCIE_IMUX31_L_0", + "PCIE_LOGIC_OUTS_B21_R_14", + "PCIE_TRNRD54", + "PCIE_WW4A0_18", + "PCIE_LOGIC_OUTS_B22_R_2", + "PCIE_WL1END2_8", + "PCIE_FAN1_R_4", + "PCIE_CFGPORTNUMBER0", + "PCIE_CTRL1_L_17", + "PCIE_BYP3_R_5", + "PCIE_MIMTXWDATA41", + "PCIE_TRNTD104", + "PCIE_CFGMGMTDO22", + "PCIE_ER1BEG0_4", + "PCIE_WW4B3_0", + "PCIE_WW4B2_0", + "PCIE_FAN0_R_12", + "PCIE_BYP4_R_19", + "PCIE_PLLTSSMSTATE1", + "PCIE_TRNFCCPLD10", + "PCIE_PIPETX0DATA6", + "PCIE_TRNRNPOK", + "PCIE_EE4C1_7", + "PCIE_CLK1_R_5", + "PCIE_IMUX21_R_3", + "PCIE_IMUX9_L_7", + "PCIE_LH5_12", + "PCIE_ER1BEG0_10", + "PCIE_WL1END2_18", + "PCIE_CFGMGMTDI27", + "PCIE_CFGREVID5", + "PCIE_EE4A3_3", + "PCIE_MIMTXWADDR12", + "PCIE_TRNFCPD3", + "PCIE_LOGIC_OUTS_B2_R_13", + "PCIE_SE4BEG1_15", + "PCIE_IMUX25_R_9", + "PCIE_IMUX13_R_17", + "PCIE_FAN4_R_17", + "PCIE_TRNRDLLPDATA21", + "PCIE_IMUX32_L_5", + "PCIE_MIMRXWADDR1", + "PCIE_FAN1_R_7", + "PCIE_XILUNCONNOUT30", + "PCIE_LOGIC_OUTS_B17_L_18", + "PCIE_LOGIC_OUTS_B20_L_11", + "PCIE_NE4C1_6", + "PCIE_MIMRXRADDR11", + "PCIE_EE4A1_12", + "PCIE_LOGIC_OUTS_B17_R_13", + "PCIE_FAN0_R_15", + "PCIE_SE4C0_18", + "PCIE_CFGDSN48", + "PCIE_MIMTXWADDR2", + "PCIE_IMUX9_L_0", + "PCIE_CFGERRAERHEADERLOG46", + "PCIE_NE2A0_13", + "PCIE_BLOCK_OUTS_B1_R_18", + "PCIE_SW4END1_5", + "PCIE_EE2BEG1_13", + "PCIE_WR1END1_17", + "PCIE_CLK1_L_2", + "PCIE_IMUX40_R_6", + "PCIE_CFGERRAERHEADERLOGSETN", + "PCIE_IMUX17_R_5", + "PCIE_IMUX30_R_5", + "PCIE_CFGDSN52", + "PCIE_CFGINTERRUPTDO1", + "PCIE_CFGINTERRUPTDI5", + "PCIE_EL1BEG1_6", + "PCIE_EL1BEG3_5", + "PCIE_WW4C0_11", + "PCIE_EE4BEG0_15", + "PCIE_IMUX5_L_3", + "PCIE_BYP2_L_13", + "PCIE_IMUX17_L_1", + "PCIE_PIPERX6DATA7", + "PCIE_LOGIC_OUTS_B8_R_11", + "PCIE_LOGIC_OUTS_B10_R_8", + "PCIE_DBGVECC2", + "PCIE_SE4C0_16", + "PCIE_IMUX40_R_8", + "PCIE_FAN6_L_4", + "PCIE_BYP0_L_11", + "PCIE_IMUX26_L_6", + "PCIE_IMUX30_R_13", + "PCIE_WW2A3_2", + "PCIE_LOGIC_OUTS_B22_R_18", + "PCIE_BYP1_R_4", + "PCIE_BLOCK_OUTS_B2_L_15", + "PCIE_BLOCK_OUTS_B3_L_5", + "PCIE_PIPERX7DATA1", + "PCIE_SW4END2_9", + "PCIE_IMUX37_L_15", + "PCIE_EE4A3_10", + "PCIE_EE4C0_13", + "PCIE_PIPERX1DATA8", + "PCIE_CFGDSN37", + "PCIE_LOGIC_OUTS_B23_R_7", + "PCIE_PIPERX0CHANISALIGNED", + "PCIE_PIPETX1DATA11", + "PCIE_IMUX29_R_18", + "PCIE_WW4END1_0", + "PCIE_LOGIC_OUTS_B9_R_3", + "PCIE_LOGIC_OUTS_B2_R_9", + "PCIE_IMUX46_L_5", + "PCIE_MIMRXWDATA3", + "PCIE_IMUX3_L_6", + "PCIE_CFGERRTLPCPLHEADER12", + "PCIE_CFGMGMTWRRW1CASRWN", + "PCIE_BLOCK_OUTS_B1_L_14", + "PCIE_FAN2_L_14", + "PCIE_IMUX34_R_3", + "PCIE_WL1END1_14", + "PCIE_NE4BEG3_11", + "PCIE_EE4A0_7", + "PCIE_XILUNCONNOUT15", + "PCIE_IMUX41_L_9", + "PCIE_IMUX32_L_9", + "PCIE_CTRL0_L_13", + "PCIE_WW4END1_8", + "PCIE_BLOCK_OUTS_B0_L_18", + "PCIE_LOGIC_OUTS_B7_R_13", + "PCIE_IMUX9_L_9", + "PCIE_BYP5_R_16", + "PCIE_IMUX33_R_10", + "PCIE_CFGLINKCONTROLRCB", + "PCIE_TRNRD97", + "PCIE_IMUX33_L_14", + "PCIE_LOGIC_OUTS_B9_R_8", + "PCIE_TRNRDLLPDATA36", + "PCIE_IMUX29_L_5", + "PCIE_IMUX4_R_2", + "PCIE_IMUX36_L_12", + "PCIE_IMUX13_L_0", + "PCIE_NW2A0_16", + "PCIE_WW4B1_16", + "PCIE_TRNRD107", + "PCIE_ER1BEG0_3", + "PCIE_CFGDSN13", + "PCIE_IMUX11_R_3", + "PCIE_IMUX7_R_14", + "PCIE_CLK0_L_4", + "PCIE_MONITOR_N_15", + "PCIE_LOGIC_OUTS_B9_L_16", + "PCIE_MIMRXWDATA67", + "PCIE_IMUX44_R_3", + "PCIE_FAN0_L_5", + "PCIE_CTRL1_L_3", + "PCIE_SE4BEG0_6", + "PCIE_IMUX47_L_2", + "PCIE_IMUX45_R_14", + "PCIE_IMUX37_R_19", + "PCIE_CFGDEVID2", + "PCIE_SW2A1_6", + "PCIE_TRNFCPH4", + "PCIE_ER1BEG3_14", + "PCIE_FAN0_L_0", + "PCIE_IMUX22_R_17", + "PCIE_TRNTD91", + "PCIE_EL1BEG1_13", + "PCIE_PIPERX7DATA14", + "PCIE_IMUX23_L_7", + "PCIE_PIPERX3VALID", + "PCIE_IMUX5_L_14", + "PCIE_NE2A1_9", + "PCIE_WW2A3_8", + "PCIE_IMUX43_L_8", + "PCIE_NW4END1_2", + "PCIE_EL1BEG2_10", + "PCIE_LOGIC_OUTS_B8_R_4", + "PCIE_IMUX21_L_3", + "PCIE_PIPETX5DATA2", + "PCIE_IMUX43_L_15", + "PCIE_DRPCLK", + "PCIE_IMUX4_L_17", + "PCIE_IMUX17_R_17", + "PCIE_IMUX40_R_17", + "PCIE_XILUNCONNOUT19", + "PCIE_PIPETX0ELECIDLE", + "PCIE_IMUX10_R_12", + "PCIE_PLLTSSMSTATE3", + "PCIE_SW4A2_1", + "PCIE_IMUX16_L_13", + "PCIE_DBGVECB27", + "PCIE_EE2A2_9", + "PCIE_IMUX39_L_17", + "PCIE_LOGIC_OUTS_B5_L_17", + "PCIE_LH10_5", + "PCIE_MIMTXWDATA22", + "PCIE_LOGIC_OUTS_B0_R_5", + "PCIE_IMUX10_L_15", + "PCIE_WW4B0_14", + "PCIE_SW2A0_0", + "PCIE_IMUX44_L_18", + "PCIE_BLOCK_OUTS_B1_L_7", + "PCIE_CTRL0_R_7", + "PCIE_EE2A3_6", + "PCIE_IMUX34_L_12", + "PCIE_IMUX20_R_8", + "PCIE_BYP1_R_5", + "PCIE_FAN2_L_4", + "PCIE_NE2A0_0", + "PCIE_IMUX8_R_8", + "PCIE_PIPETX5DATA1", + "PCIE_LOGIC_OUTS_B9_R_15", + "PCIE_LOGIC_OUTS_B2_R_6", + "PCIE_IMUX28_R_13", + "PCIE_NW4A0_14", + "PCIE_TRNTDSTRDY1", + "PCIE_SW2A1_16", + "PCIE_TRNRD108", + "PCIE_TL2ASPMSUSPENDCREDITCHECK", + "PCIE_FAN7_L_0", + "PCIE_LOGIC_OUTS_B23_L_8", + "PCIE_CFGLINKCONTROLCLOCKPMEN", + "PCIE_IMUX15_L_10", + "PCIE_LOGIC_OUTS_B0_R_7", + "PCIE_XILUNCONNOUT33", + "PCIE_CLK1_R_4", + "PCIE_IMUX36_R_9", + "PCIE_NW4END3_6", + "PCIE_LOGIC_OUTS_B10_L_1", + "PCIE_SW4END2_15", + "PCIE_CFGDSBUSNUMBER6", + "PCIE_LOGIC_OUTS_B3_L_15", + "PCIE_BYP6_L_1", + "PCIE_WW4C3_7", + "PCIE_PIPERX1PHYSTATUS", + "PCIE_LH12_12", + "PCIE_LOGIC_OUTS_B16_L_6", + "PCIE_BLOCK_OUTS_B3_R_18", + "PCIE_LOGIC_OUTS_B11_R_18", + "PCIE_CFGDSBUSNUMBER3", + "PCIE_TL2ERRHDR58", + "PCIE_LOGIC_OUTS_B22_R_15", + "PCIE_LH4_17", + "PCIE_FAN2_L_7", + "PCIE_FAN3_L_11", + "PCIE_CFGERRACSN", + "PCIE_LH6_2", + "PCIE_IMUX4_L_0", + "PCIE_TRNFCPD11", + "PCIE_NE4C1_5", + "PCIE_BYP7_R_10", + "PCIE_TRNREOF", + "PCIE_WW4A0_6", + "PCIE_WW4A1_19", + "PCIE_CFGPORTNUMBER7", + "PCIE_IMUX26_L_16", + "PCIE_NW4END2_19", + "PCIE_IMUX43_R_19", + "PCIE_LH1_12", + "PCIE_EE2A0_4", + "PCIE_BYP3_R_10", + "PCIE_PIPERX0DATA9", + "PCIE_IMUX43_L_13", + "PCIE_EE4C3_15", + "PCIE_IMUX29_R_11", + "PCIE_LH8_12", + "PCIE_TRNRDLLPDATA44", + "PCIE_IMUX26_L_11", + "PCIE_NW4END2_9", + "PCIE_BYP0_R_14", + "PCIE_SE4C1_10", + "PCIE_NE4BEG0_17", + "PCIE_NE4BEG2_12", + "PCIE_BLOCK_OUTS_B3_R_2", + "PCIE_SE2A0_14", + "PCIE_EE4C2_3", + "PCIE_NE4C1_4", + "PCIE_NW4END1_5", + "PCIE_TL2ERRHDR17", + "PCIE_IMUX24_R_7", + "PCIE_WW4A2_5", + "PCIE_PIPERX0DATA4", + "PCIE_SE4BEG2_19", + "PCIE_IMUX31_L_14", + "PCIE_CLK0_L_12", + "PCIE_FAN4_R_12", + "PCIE_NW2A0_1", + "PCIE_CLK1_L_13", + "PCIE_IMUX24_R_18", + "PCIE_EE4BEG1_6", + "PCIE_IMUX18_R_0", + "PCIE_DBGVECB61", + "PCIE_IMUX18_R_17", + "PCIE_PIPETXMARGIN2", + "PCIE_IMUX19_L_2", + "PCIE_IMUX6_L_12", + "PCIE_SW4END0_3", + "PCIE_CFGPMRCVASREQL1N", + "PCIE_WW4END0_18", + "PCIE_MIMTXRDATA54", + "PCIE_FAN3_L_15", + "PCIE_PIPERX1STATUS1", + "PCIE_LOGIC_OUTS_B23_R_12", + "PCIE_LOGIC_OUTS_B19_L_18", + "PCIE_IMUX32_R_15", + "PCIE_FAN1_R_0", + "PCIE_BLOCK_OUTS_B3_R_1", + "PCIE_CFGREVID1", + "PCIE_WW4B3_7", + "PCIE_WL1END1_12", + "PCIE_SE4C2_9", + "PCIE_FAN3_L_16", + "PCIE_IMUX11_L_16", + "PCIE_IMUX29_L_7", + "PCIE_IMUX24_R_10", + "PCIE_PIPETX0DATA7", + "PCIE_TRNTD37", + "PCIE_IMUX4_R_9", + "PCIE_CLK0_R_4", + "PCIE_NE4C0_19", + "PCIE_IMUX8_L_18", + "PCIE_LOGIC_OUTS_B22_L_3", + "PCIE_WW4END1_17", + "PCIE_BYP2_L_0", + "PCIE_WW2A0_8", + "PCIE_TRNRDLLPDATA62", + "PCIE_LOGIC_OUTS_B21_R_15", + "PCIE_SE4C3_18", + "PCIE_TRNTD47", + "PCIE_SE4BEG2_12", + "PCIE_IMUX41_L_2", + "PCIE_LOGIC_OUTS_B5_L_11", + "PCIE_EE4A1_11", + "PCIE_CFGMSGDATA7", + "PCIE_SE4C3_2", + "PCIE_BYP7_L_19", + "PCIE_WL1END3_16", + "PCIE_LOGIC_OUTS_B13_R_9", + "PCIE_IMUX31_L_12", + "PCIE_BYP5_L_19", + "PCIE_FAN1_L_8", + "PCIE_MIMRXRDATA28", + "PCIE_IMUX36_L_4", + "PCIE_SE4BEG1_7", + "PCIE_EE2A2_14", + "PCIE_IMUX37_L_10", + "PCIE_PLINITIALLINKWIDTH1", + "PCIE_PIPETX0DATA5", + "PCIE_WR1END3_5", + "PCIE_EE2BEG2_3", + "PCIE_EE2BEG0_17", + "PCIE_SE4BEG3_15", + "PCIE_WW4B2_15", + "PCIE_NE2A0_3", + "PCIE_TRNRD62", + "PCIE_MIMRXRDATA37", + "PCIE_DBGSUBMODE", + "PCIE_LOGIC_OUTS_B20_R_6", + "PCIE_IMUX46_L_7", + "PCIE_EE4BEG3_6", + "PCIE_LH4_10", + "PCIE_LOGIC_OUTS_B15_R_10", + "PCIE_WW2END1_10", + "PCIE_LOGIC_OUTS_B19_R_7", + "PCIE_TL2ERRHDR33", + "PCIE_EE2BEG0_15", + "PCIE_CFGSUBSYSVENDID6", + "PCIE_WW2A3_17", + "PCIE_LOGIC_OUTS_B4_L_0", + "PCIE_IMUX4_L_14", + "PCIE_PIPERX4DATA11", + "PCIE_FAN3_L_18", + "PCIE_FAN1_L_5", + "PCIE_MIMRXRDATA54", + "PCIE_PIPETX0DATA12", + "PCIE_TRNRD88", + "PCIE_TRNFCCPLH3", + "PCIE_FAN6_R_11", + "PCIE_CTRL0_L_15", + "PCIE_IMUX1_R_5", + "PCIE_IMUX24_R_17", + "PCIE_CFGDSN62", + "PCIE_IMUX10_L_8", + "PCIE_CFGDSN26", + "PCIE_LOGIC_OUTS_B17_L_2", + "PCIE_CFGERRAERHEADERLOG103", + "PCIE_SE4BEG3_8", + "PCIE_LOGIC_OUTS_B19_R_13", + "PCIE_LH8_11", + "PCIE_EE2BEG1_12", + "PCIE_FAN5_R_16", + "PCIE_PIPERX1DATA13", + "PCIE_FAN6_L_8", + "PCIE_IMUX42_R_5", + "PCIE_BYP1_R_14", + "PCIE_WW4END1_3", + "PCIE_CFGMGMTDI20", + "PCIE_LOGIC_OUTS_B8_L_8", + "PCIE_LOGIC_OUTS_B4_R_7", + "PCIE_EE2A0_17", + "PCIE_LOGIC_OUTS_B20_L_13", + "PCIE_IMUX40_R_5", + "PCIE_SE4BEG2_13", + "PCIE_BLOCK_OUTS_B1_R_9", + "PCIE_FAN7_R_11", + "PCIE_IMUX38_L_1", + "PCIE_LOGIC_OUTS_B11_L_18", + "PCIE_LOGIC_OUTS_B2_R_16", + "PCIE_EE2A0_8", + "PCIE_WW4END0_15", + "PCIE_LOGIC_OUTS_B15_R_9", + "PCIE_WW2A0_9", + "PCIE_LOGIC_OUTS_B7_R_11", + "PCIE_LOGIC_OUTS_B16_L_4", + "PCIE_IMUX11_R_6", + "PCIE_WW4C2_16", + "PCIE_TRNRDLLPDATA41", + "PCIE_IMUX26_L_10", + "PCIE_IMUX41_L_0", + "PCIE_CFGERRTLPCPLHEADER44", + "PCIE_IMUX14_L_7", + "PCIE_DBGVECB31", + "PCIE_CFGERRAERHEADERLOG90", + "PCIE_EE4B3_6", + "PCIE_BYP1_R_13", + "PCIE_DBGVECB39", + "PCIE_LOGIC_OUTS_B23_R_5", + "PCIE_IMUX38_R_3", + "PCIE_SE4C0_4", + "PCIE_WW2A3_7", + "PCIE_IMUX3_L_5", + "PCIE_IMUX9_R_12", + "PCIE_IMUX3_R_3", + "PCIE_CFGPMFORCESTATE1", + "PCIE_IMUX40_L_15", + "PCIE_IMUX33_R_15", + "PCIE_LOGIC_OUTS_B18_L_17", + "PCIE_CFGERRAERHEADERLOG66", + "PCIE_WW4END0_4", + "PCIE_BYP3_L_3", + "PCIE_FAN3_R_1", + "PCIE_EE4B2_10", + "PCIE_TRNTD111", + "PCIE_CFGSUBSYSID13", + "PCIE_IMUX21_R_16", + "PCIE_FAN6_L_14", + "PCIE_LOGIC_OUTS_B14_L_9", + "PCIE_PIPERX7DATA15", + "PCIE_FAN1_R_13", + "PCIE_LOGIC_OUTS_B14_R_14", + "PCIE_SW2A2_18", + "PCIE_BYP1_L_16", + "PCIE_WW4END3_16", + "PCIE_DBGSCLRK", + "PCIE_IMUX20_R_6", + "PCIE_WW2END3_9", + "PCIE_MIMTXRDATA39", + "PCIE_PLDIRECTEDLINKWIDTH0", + "PCIE_MIMTXRDATA37", + "PCIE_DBGVECB15", + "PCIE_PLDIRECTEDLINKCHANGE1", + "PCIE_LOGIC_OUTS_B21_R_8", + "PCIE_DBGVECA44", + "PCIE_IMUX44_R_7", + "PCIE_IMUX9_R_3", + "PCIE_TRNRD47", + "PCIE_TRNTBUFAV5", + "PCIE_WW4B0_11", + "PCIE_IMUX27_L_17", + "PCIE_LH8_14", + "PCIE_LH5_18", + "PCIE_SE4C0_2", + "PCIE_CLK0_L_9", + "PCIE_LOGIC_OUTS_B0_R_8", + "PCIE_FAN2_R_13", + "PCIE_LH5_19", + "PCIE_IMUX10_R_3", + "PCIE_LOGIC_OUTS_B16_R_8", + "PCIE_WW2END2_3", + "PCIE_WW4END3_4", + "PCIE_CFGERRAERHEADERLOG124", + "PCIE_IMUX21_L_6", + "PCIE_WW4A1_12", + "PCIE_IMUX39_R_16", + "PCIE_IMUX15_R_14", + "PCIE_SW4A3_2", + "PCIE_CFGFORCEMPS2", + "PCIE_IMUX12_L_18", + "PCIE_LOGIC_OUTS_B8_L_19", + "PCIE_IMUX5_R_15", + "PCIE_FAN2_R_3", + "PCIE_LOGIC_OUTS_B15_L_0", + "PCIE_LOGIC_OUTS_B3_L_2", + "PCIE_CFGERRPOSTEDN", + "PCIE_IMUX33_L_3", + "PCIE_WR1END0_6", + "PCIE_MIMRXWDATA40", + "PCIE_LOGIC_OUTS_B23_R_14", + "PCIE_IMUX29_R_0", + "PCIE_FAN1_L_14", + "PCIE_EE4BEG3_1", + "PCIE_WW4B1_0", + "PCIE_FAN3_R_18", + "PCIE_NE4C0_0", + "PCIE_IMUX2_L_14", + "PCIE_IMUX35_L_18", + "PCIE_EE4C3_4", + "PCIE_LH3_15", + "PCIE_BYP4_R_6", + "PCIE_TRNRDLLPDATA61", + "PCIE_LOGIC_OUTS_B5_L_1", + "PCIE_IMUX11_R_8", + "PCIE_MIMRXWDATA54", + "PCIE_LOGIC_OUTS_B1_R_19", + "PCIE_TRNFCPH2", + "PCIE_PIPERX5DATA13", + "PCIE_CFGPORTNUMBER5", + "PCIE_EE4B0_1", + "PCIE_NW4END1_18", + "PCIE_SW4A3_18", + "PCIE_PIPETX5POWERDOWN0", + "PCIE_BYP7_L_9", + "PCIE_LOGIC_OUTS_B13_L_18", + "PCIE_BYP3_R_7", + "PCIE_DBGVECB40", + "PCIE_SE4BEG0_8", + "PCIE_PIPERX5DATA5", + "PCIE_PIPERX0ELECIDLE", + "PCIE_SE4BEG3_7", + "PCIE_TRNTD55", + "PCIE_WW4C2_15", + "PCIE_IMUX2_R_0", + "PCIE_LH11_17", + "PCIE_IMUX24_L_13", + "PCIE_NW4END3_1", + "PCIE_CFGERRAERHEADERLOG63", + "PCIE_NE4C0_6", + "PCIE_LOGIC_OUTS_B21_L_17", + "PCIE_BYP6_L_10", + "PCIE_CFGERRAERHEADERLOG109", + "PCIE_LOGIC_OUTS_B6_R_2", + "PCIE_LH1_16", + "PCIE_EE4C0_15", + "PCIE_EE4B1_10", + "PCIE_XILUNCONNOUT16", + "PCIE_PIPETX6DATA9", + "PCIE_BYP5_L_13", + "PCIE_IMUX3_R_11", + "PCIE_IMUX30_L_1", + "PCIE_TL2ERRHDR11", + "PCIE_TRNRDLLPDATA58", + "PCIE_BYP5_R_1", + "PCIE_WL1END2_14", + "PCIE_EE4BEG3_9", + "PCIE_IMUX29_L_13", + "PCIE_LOGIC_OUTS_B2_R_3", + "PCIE_TRNTDLLPDATA28", + "PCIE_TRNRD38", + "PCIE_IMUX13_L_3", + "PCIE_SE2A0_5", + "PCIE_IMUX27_R_4", + "PCIE_BLOCK_OUTS_B1_L_11", + "PCIE_SE4C3_14", + "PCIE_LH7_12", + "PCIE_EE2A0_14", + "PCIE_MIMRXWDATA6", + "PCIE_LH7_4", + "PCIE_EE4B1_19", + "PCIE_PIPETX4DATA0", + "PCIE_CFGERRAERHEADERLOG73", + "PCIE_LOGIC_OUTS_B22_R_11", + "PCIE_FAN1_L_1", + "PCIE_IMUX15_R_19", + "PCIE_LOGIC_OUTS_B15_R_0", + "PCIE_IMUX32_R_14", + "PCIE_BYP3_L_4", + "PCIE_NE4C2_15", + "PCIE_CFGMGMTBYTEENN0", + "PCIE_NW4END0_16", + "PCIE_MIMTXWDATA57", + "PCIE_IMUX4_L_18", + "PCIE_LOGIC_OUTS_B1_R_5", + "PCIE_XILUNCONNOUT4", + "PCIE_DRPDO1", + "PCIE_MIMRXWDATA56", + "PCIE_NW4A2_1", + "PCIE_IMUX24_L_19", + "PCIE_LH3_8", + "PCIE_IMUX38_L_14", + "PCIE_BLOCK_OUTS_B1_R_15", + "PCIE_NE2A3_0", + "PCIE_LH12_6", + "PCIE_TRNRD71", + "PCIE_LOGIC_OUTS_B6_R_1", + "PCIE_TRNFCCPLD4", + "PCIE_TRNRDLLPSRCRDY0", + "PCIE_BLOCK_OUTS_B1_L_16", + "PCIE_MIMRXWDATA59", + "PCIE_LH2_10", + "PCIE_BLOCK_OUTS_B2_R_16", + "PCIE_IMUX21_R_5", + "PCIE_LOGIC_OUTS_B15_R_3", + "PCIE_WL1END2_4", + "PCIE_TRNRD8", + "PCIE_WW2END1_15", + "PCIE_IMUX31_R_15", + "PCIE_LOGIC_OUTS_B9_R_0", + "PCIE_MIMRXWDATA48", + "PCIE_CFGMGMTDO15", + "PCIE_CFGERRAERHEADERLOG80", + "PCIE_CFGAERINTERRUPTMSGNUM3", + "PCIE_WR1END1_14", + "PCIE_EE4BEG3_13", + "PCIE_CFGLINKSTATUSCURRENTSPEED1", + "PCIE_BYP0_L_3", + "PCIE_EE4C2_6", + "PCIE_IMUX13_L_4", + "PCIE_PIPERX3DATA1", + "PCIE_IMUX0_R_3", + "PCIE_SE4BEG2_11", + "PCIE_IMUX42_L_1", + "PCIE_CFGSUBSYSVENDID3", + "PCIE_IMUX11_R_7", + "PCIE_LOGIC_OUTS_B15_R_7", + "PCIE_IMUX19_L_15", + "PCIE_LOGIC_OUTS_B19_L_15", + "PCIE_LOGIC_OUTS_B23_R_8", + "PCIE_LOGIC_OUTS_B21_R_13", + "PCIE_CFGERRAERHEADERLOG35", + "PCIE_PIPETX3DATA12", + "PCIE_IMUX42_R_18", + "PCIE_EE2A0_7", + "PCIE_EDTCHANNELSIN2", + "PCIE_CTRL0_L_10", + "PCIE_SE2A3_18", + "PCIE_EE4A0_19", + "PCIE_EL1BEG0_0", + "PCIE_IMUX26_R_5", + "PCIE_CFGERRAERHEADERLOG23", + "PCIE_XILUNCONNOUT39", + "PCIE_LOGIC_OUTS_B6_L_13", + "PCIE_WL1END0_11", + "PCIE_PIPERX0DATA2", + "PCIE_MONITOR_N_18", + "PCIE_LOGIC_OUTS_B7_R_19", + "PCIE_IMUX42_L_15", + "PCIE_LOGIC_OUTS_B23_L_2", + "PCIE_CFGMGMTDO29", + "PCIE_LOGIC_OUTS_B9_R_5", + "PCIE_SE4C3_0", + "PCIE_BYP3_L_6", + "PCIE_NW2A1_17", + "PCIE_LOGIC_OUTS_B15_R_19", + "PCIE_LOGIC_OUTS_B12_R_6", + "PCIE_LOGIC_OUTS_B9_L_3", + "PCIE_BLOCK_OUTS_B2_L_0", + "PCIE_FAN3_L_10", + "PCIE_DBGVECB54", + "PCIE_CFGMSGDATA10", + "PCIE_MONITOR_P_7", + "PCIE_LOGIC_OUTS_B23_L_12", + "PCIE_TRNRD75", + "PCIE_TRNTD43", + "PCIE_MIMRXWDATA5", + "PCIE_TRNTD107", + "PCIE_IMUX42_R_10", + "PCIE_IMUX7_R_9", + "PCIE_WR1END0_16", + "PCIE_LH1_10", + "PCIE_LOGIC_OUTS_B8_R_13", + "PCIE_SW4END2_14", + "PCIE_TRNTDLLPDATA25", + "PCIE_WW4C3_16", + "PCIE_PIPETX6DATA0", + "PCIE_LOGIC_OUTS_B23_L_9", + "PCIE_BYP7_R_2", + "PCIE_MIMTXWADDR4", + "PCIE_IMUX34_L_3", + "PCIE_IMUX41_L_18", + "PCIE_LOGIC_OUTS_B4_R_17", + "PCIE_IMUX37_L_19", + "PCIE_ER1BEG3_9", + "PCIE_IMUX20_R_5", + "PCIE_LOGIC_OUTS_B9_L_7", + "PCIE_CFGERRTLPCPLHEADER14", + "PCIE_LOGIC_OUTS_B3_R_9", + "PCIE_SE4C1_19", + "PCIE_BYP5_R_13", + "PCIE_MIMTXRDATA62", + "PCIE_IMUX14_L_3", + "PCIE_IMUX39_R_12", + "PCIE_DRPDI8", + "PCIE_WW4A1_6", + "PCIE_MIMTXRDATA29", + "PCIE_CFGERRAERHEADERLOG76", + "PCIE_CFGERRAERHEADERLOG12", + "PCIE_LH6_16", + "PCIE_WW2A3_5", + "PCIE_CFGMGMTDI26", + "PCIE_LH4_5", + "PCIE_IMUX41_R_10", + "PCIE_IMUX15_L_16", + "PCIE_FAN3_R_14", + "PCIE_PIPERX3STATUS2", + "PCIE_BLOCK_OUTS_B0_L_19", + "PCIE_SW2A1_19", + "PCIE_WW4B1_3", + "PCIE_PLDIRECTEDLTSSMSTALL", + "PCIE_WL1END2_6", + "PCIE_LOGIC_OUTS_B23_R_6", + "PCIE_NE2A3_4", + "PCIE_PIPERX5STATUS0", + "PCIE_LOGIC_OUTS_B15_R_13", + "PCIE_CFGERRTLPCPLHEADER45", + "PCIE_BYP7_L_10", + "PCIE_PIPERX4DATA1", + "PCIE_SCANENABLEN", + "PCIE_LOGIC_OUTS_B5_L_14", + "PCIE_NW2A2_5", + "PCIE_LL2PROTOCOLERR", + "PCIE_CFGERRAERHEADERLOG113", + "PCIE_NW2A3_2", + "PCIE_EE2A0_11", + "PCIE_IMUX38_R_15", + "PCIE_BYP4_R_13", + "PCIE_TRNTD76", + "PCIE_IMUX34_R_0", + "PCIE_IMUX21_L_13", + "PCIE_FAN6_R_17", + "PCIE_CFGMGMTDI17", + "PCIE_LOGIC_OUTS_B14_L_15", + "PCIE_EL1BEG3_11", + "PCIE_BYP1_L_15", + "PCIE_CFGMGMTDWADDR2", + "PCIE_EE4C1_18", + "PCIE_IMUX1_R_4", + "PCIE_EL1BEG2_17", + "PCIE_EE4A3_0", + "PCIE_LL2SUSPENDNOW", + "PCIE_IMUX36_R_19", + "PCIE_IMUX46_R_17", + "PCIE_BLOCK_OUTS_B2_R_15", + "PCIE_PIPERX7DATA6", + "PCIE_LOGIC_OUTS_B4_L_15", + "PCIE_IMUX43_R_17", + "PCIE_TRNTD89", + "PCIE_LH11_1", + "PCIE_WW2A2_11", + "PCIE_IMUX40_L_14", + "PCIE_NE4BEG1_10", + "PCIE_IMUX10_L_7", + "PCIE_IMUX16_L_19", + "PCIE_IMUX39_L_15", + "PCIE_CLK1_L_19", + "PCIE_CFGERRAERHEADERLOG125", + "PCIE_IMUX11_L_8", + "PCIE_LOGIC_OUTS_B11_L_7", + "PCIE_EE2BEG1_9", + "PCIE_TRNTERRDROP", + "PCIE_PIPERX4POLARITY", + "PCIE_TLRSTN", + "PCIE_FAN5_R_13", + "PCIE_IMUX1_L_6", + "PCIE_ER1BEG0_17", + "PCIE_WR1END0_11", + "PCIE_LOGIC_OUTS_B21_R_5", + "PCIE_IMUX44_R_18", + "PCIE_BYP6_L_13", + "PCIE_IMUX23_L_3", + "PCIE_BYP6_R_15", + "PCIE_SW4A0_5", + "PCIE_MIMRXRDATA55", + "PCIE_EE2A0_0", + "PCIE_IMUX40_L_0", + "PCIE_PLTRANSMITHOTRST", + "PCIE_IMUX26_L_17", + "PCIE_MIMTXRDATA19", + "PCIE_NW4A3_9", + "PCIE_DRPEN", + "PCIE_PIPETX7ELECIDLE", + "PCIE_SW4END1_15", + "PCIE_ER1BEG3_0", + "PCIE_CFGPCIELINKSTATE1", + "PCIE_NE2A1_15", + "PCIE_NE4C2_14", + "PCIE_IMUX2_R_18", + "PCIE_IMUX17_R_16", + "PCIE_IMUX0_L_4", + "PCIE_PIPETX4DATA11", + "PCIE_IMUX5_R_18", + "PCIE_EE4B3_14", + "PCIE_IMUX38_L_2", + "PCIE_PIPETX7COMPLIANCE", + "PCIE_BLOCK_OUTS_B2_L_5", + "PCIE_TRNRDLLPDATA34", + "PCIE_BYP6_L_15", + "PCIE_LOGIC_OUTS_B1_L_15", + "PCIE_LOGIC_OUTS_B19_R_1", + "PCIE_BLOCK_OUTS_B2_R_19", + "PCIE_LOGIC_OUTS_B17_R_17", + "PCIE_SW4END2_7", + "PCIE_MIMTXRDATA8", + "PCIE_CFGERRAERHEADERLOG106", + "PCIE_IMUX19_R_2", + "PCIE_EDTCHANNELSOUT4", + "PCIE_LOGIC_OUTS_B5_L_16", + "PCIE_TRNRD33", + "PCIE_CFGSUBSYSVENDID11", + "PCIE_TRNRDLLPDATA51", + "PCIE_IMUX8_R_16", + "PCIE_DBGVECB5", + "PCIE_FAN3_L_0", + "PCIE_SE4BEG0_5", + "PCIE_PIPERX3DATA13", + "PCIE_LOGIC_OUTS_B20_L_7", + "PCIE_BYP1_R_15", + "PCIE_FAN2_R_7", + "PCIE_LOGIC_OUTS_B20_R_11", + "PCIE_IMUX31_L_3", + "PCIE_IMUX15_R_13", + "PCIE_LOGIC_OUTS_B2_R_10", + "PCIE_BYP7_L_15", + "PCIE_SW2A0_10", + "PCIE_IMUX43_R_5", + "PCIE_PLLTSSMSTATE2", + "PCIE_TRNTD79", + "PCIE_IMUX36_L_19", + "PCIE_CLK0_L_13", + "PCIE_IMUX9_L_17", + "PCIE_PIPETX1DATA10", + "PCIE_IMUX45_R_15", + "PCIE_CFGMSGRECEIVEDPMETOACK", + "PCIE_IMUX41_R_15", + "PCIE_LOGIC_OUTS_B10_L_14", + "PCIE_IMUX29_R_12", + "PCIE_IMUX24_L_7", + "PCIE_CTRL1_L_4", + "PCIE_TRNRD73", + "PCIE_TRNRD84", + "PCIE_PLDBGVEC2", + "PCIE_DRPDI5", + "PCIE_IMUX4_R_4", + "PCIE_NE4C0_9", + "PCIE_IMUX13_R_3", + "PCIE_FAN1_L_0", + "PCIE_PIPETX2DATA2", + "PCIE_CLK0_L_16", + "PCIE_FAN4_L_17", + "PCIE_WW4C1_8", + "PCIE_FAN4_R_6", + "PCIE_LOGIC_OUTS_B17_L_11", + "PCIE_IMUX5_L_8", + "PCIE_WW4B0_19", + "PCIE_CTRL0_R_19", + "PCIE_CFGINTERRUPTMMENABLE0", + "PCIE_EE2BEG3_2", + "PCIE_IMUX47_R_12", + "PCIE_EE2BEG2_0", + "PCIE_IMUX16_L_11", + "PCIE_WW4B0_3", + "PCIE_PLLTSSMSTATE5", + "PCIE_SW4END3_6", + "PCIE_WW2A0_10", + "PCIE_IMUX19_L_5", + "PCIE_NW4A3_7", + "PCIE_TRNRD22", + "PCIE_CFGMSGDATA12", + "PCIE_IMUX5_R_16", + "PCIE_LOGIC_OUTS_B20_L_14", + "PCIE_LOGIC_OUTS_B7_L_11", + "PCIE_IMUX25_R_18", + "PCIE_CFGERRTLPCPLHEADER9", + "PCIE_IMUX14_L_5", + "PCIE_FAN7_L_7", + "PCIE_IMUX9_L_13", + "PCIE_PIPETX2DATA15", + "PCIE_IMUX40_R_15", + "PCIE_LH8_17", + "PCIE_PIPERX6DATA5", + "PCIE_TRNTD99", + "PCIE_CFGLINKCONTROLCOMMONCLOCK", + "PCIE_EE4C0_17", + "PCIE_DBGSCLRC", + "PCIE_NW4END3_8", + "PCIE_SW2A2_15", + "PCIE_PL2DIRECTEDLSTATE2", + "PCIE_PLINITIALLINKWIDTH0", + "PCIE_IMUX27_R_10", + "PCIE_EE4C3_1", + "PCIE_PIPERX5STATUS2", + "PCIE_CFGINTERRUPTMMENABLE1", + "PCIE_LOGIC_OUTS_B12_R_19", + "PCIE_WW4A2_11", + "PCIE_WW4B2_5", + "PCIE_NE4BEG2_18", + "PCIE_DBGVECB13", + "PCIE_PIPERX7DATA4", + "PCIE_WW2A3_14", + "PCIE_MIMRXWDATA16", + "PCIE_WW4B1_8", + "PCIE_BYP0_R_18", + "PCIE_IMUX13_R_2", + "PCIE_IMUX35_L_0", + "PCIE_LH2_12", + "PCIE_NE2A0_16", + "PCIE_BYP2_L_17", + "PCIE_EE2BEG1_17", + "PCIE_CFGDEVID13", + "PCIE_IMUX21_R_0", + "PCIE_IMUX42_R_0", + "PCIE_TRNFCPD5", + "PCIE_LOGIC_OUTS_B10_L_8", + "PCIE_TL2ERRHDR31", + "PCIE_TRNFCCPLD5", + "PCIE_PIPETX4DATA7", + "PCIE_WW2A0_18", + "PCIE_IMUX8_L_1", + "PCIE_WW2A0_12", + "PCIE_IMUX14_R_9", + "PCIE_IMUX0_L_7", + "PCIE_IMUX17_L_7", + "PCIE_LOGIC_OUTS_B21_L_14", + "PCIE_IMUX27_R_7", + "PCIE_CFGDEVCONTROLPHANTOMEN", + "PCIE_NE2A0_2", + "PCIE_IMUX31_R_1", + "PCIE_IMUX1_L_1", + "PCIE_TRNFCCPLH5", + "PCIE_CFGMGMTDO23", + "PCIE_BYP2_R_1", + "PCIE_MIMTXWADDR0", + "PCIE_LH6_17", + "PCIE_IMUX43_L_3", + "PCIE_LOGIC_OUTS_B19_R_9", + "PCIE_WW4A2_19", + "PCIE_BLOCK_OUTS_B2_R_17", + "PCIE_NE4C1_12", + "PCIE_LOGIC_OUTS_B22_R_16", + "PCIE_IMUX9_L_3", + "PCIE_LOGIC_OUTS_B1_L_4", + "PCIE_LOGIC_OUTS_B5_L_9", + "PCIE_TRNTD34", + "PCIE_CFGMGMTDI3", + "PCIE_NW4END2_18", + "PCIE_WW2A2_4", + "PCIE_WW4C1_2", + "PCIE_IMUX37_R_13", + "PCIE_LOGIC_OUTS_B1_L_17", + "PCIE_ER1BEG1_16", + "PCIE_CFGERRTLPCPLHEADER25", + "PCIE_SE4BEG1_13", + "PCIE_WR1END1_2", + "PCIE_TRNRD102", + "PCIE_TRNTD102", + "PCIE_IMUX24_R_8", + "PCIE_CLK1_R_17", + "PCIE_IMUX43_R_12", + "PCIE_CLK0_L_3", + "PCIE_CFGMSGDATA5", + "PCIE_IMUX32_R_19", + "PCIE_IMUX40_R_3", + "PCIE_EE2BEG0_14", + "PCIE_FAN7_R_14", + "PCIE_FAN2_R_1", + "PCIE_SE2A0_6", + "PCIE_DBGVECA61", + "PCIE_LOGIC_OUTS_B11_L_14", + "PCIE_IMUX42_L_4", + "PCIE_BLOCK_OUTS_B2_L_17", + "PCIE_NE2A1_6", + "PCIE_BYP5_L_12", + "PCIE_EE2BEG2_19", + "PCIE_CFGVENDID0", + "PCIE_PIPERX0CHARISK0", + "PCIE_IMUX28_L_7", + "PCIE_IMUX41_L_1", + "PCIE_FAN4_L_14", + "PCIE_LOGIC_OUTS_B5_L_2", + "PCIE_LOGIC_OUTS_B13_R_10", + "PCIE_IMUX47_R_19", + "PCIE_IMUX39_L_5", + "PCIE_CTRL0_L_4", + "PCIE_EE2BEG1_2", + "PCIE_XILUNCONNOUT14", + "PCIE_IMUX40_L_12", + "PCIE_BYP6_L_18", + "PCIE_LOGIC_OUTS_B16_L_10", + "PCIE_IMUX15_R_3", + "PCIE_BLOCK_OUTS_B3_R_12", + "PCIE_PIPETX7DATA2", + "PCIE_PIPETXRCVRDET", + "PCIE_CFGSUBSYSVENDID0", + "PCIE_IMUX4_R_8", + "PCIE_SW4A3_0", + "PCIE_BYP5_L_15", + "PCIE_MONITOR_P_5", + "PCIE_IMUX2_L_2", + "PCIE_LOGIC_OUTS_B16_R_6", + "PCIE_IMUX22_L_19", + "PCIE_SE4BEG1_9", + "PCIE_IMUX8_L_7", + "PCIE_EE4B2_14", + "PCIE_WW2A1_16", + "PCIE_IMUX42_L_7", + "PCIE_ER1BEG2_19", + "PCIE_IMUX13_R_0", + "PCIE_IMUX41_R_7", + "PCIE_BYP4_L_7", + "PCIE_BYP2_R_12", + "PCIE_IMUX21_R_6", + "PCIE_SE2A3_8", + "PCIE_FAN1_L_9", + "PCIE_SW4A1_17", + "PCIE_BLOCK_OUTS_B2_R_6", + "PCIE_IMUX41_R_6", + "PCIE_IMUX24_L_1", + "PCIE_MIMTXWDATA51", + "PCIE_LH3_5", + "PCIE_MIMRXRADDR8", + "PCIE_FAN3_R_8", + "PCIE_EE4A0_3", + "PCIE_CFGMGMTDO25", + "PCIE_TRNTD19", + "PCIE_EE2A3_17", + "PCIE_IMUX11_L_13", + "PCIE_EE4A3_12", + "PCIE_CFGAERINTERRUPTMSGNUM4", + "PCIE_TRNFCPH7", + "PCIE_DBGVECB9", + "PCIE_EE2BEG2_7", + "PCIE_TRNTD109", + "PCIE_PIPERX0DATA7", + "PCIE_FAN1_L_10", + "PCIE_CFGMGMTDI30", + "PCIE_EE2BEG0_8", + "PCIE_IMUX42_L_17", + "PCIE_IMUX8_R_6", + "PCIE_IMUX1_R_18", + "PCIE_ER1BEG3_3", + "PCIE_CFGMSGDATA6", + "PCIE_IMUX12_R_1", + "PCIE_IMUX26_R_3", + "PCIE_TRNTD81", + "PCIE_SE4BEG1_3", + "PCIE_WW2END3_1", + "PCIE_IMUX44_L_17", + "PCIE_MIMRXRDATA34", + "PCIE_IMUX28_L_1", + "PCIE_CFGMGMTRDENN", + "PCIE_MIMRXRDATA60", + "PCIE_BLOCK_OUTS_B2_L_12", + "PCIE_IMUX11_R_16", + "PCIE_EL1BEG3_4", + "PCIE_PIPETX7DATA7", + "PCIE_IMUX8_R_18", + "PCIE_WW4A0_8", + "PCIE_LH8_5", + "PCIE_EL1BEG0_9", + "PCIE_DRPDO9", + "PCIE_MIMTXRADDR2", + "PCIE_MIMRXRDATA29", + "PCIE_IMUX27_L_6", + "PCIE_LH4_13", + "PCIE_EE4C0_18", + "PCIE_TRNFCPD2", + "PCIE_WW4C3_19", + "PCIE_EL1BEG0_16", + "PCIE_EE4BEG1_0", + "PCIE_IMUX43_L_12", + "PCIE_LOGIC_OUTS_B18_L_1", + "PCIE_BLOCK_OUTS_B2_L_2", + "PCIE_BYP6_L_17", + "PCIE_XILUNCONNOUT10", + "PCIE_TRNTD114", + "PCIE_TRNRDLLPDATA17", + "PCIE_CFGSUBSYSID12", + "PCIE_IMUX8_L_15", + "PCIE_WW4B1_15", + "PCIE_LOGIC_OUTS_B22_R_8", + "PCIE_EE4B0_14", + "PCIE_MIMRXWDATA52", + "PCIE_BYP2_L_15", + "PCIE_SW2A2_13", + "PCIE_WW2A3_3", + "PCIE_LOGIC_OUTS_B8_L_17", + "PCIE_CFGERRAERHEADERLOG91", + "PCIE_IMUX45_R_5", + "PCIE_CTRL0_R_2", + "PCIE_IMUX5_L_15", + "PCIE_MIMRXWADDR4", + "PCIE_PIPETX7DATA3", + "PCIE_EL1BEG1_9", + "PCIE_EE2BEG3_4", + "PCIE_MIMTXRDATA58", + "PCIE_CLK0_L_7", + "PCIE_CFGINTERRUPTDO3", + "PCIE_WW4A1_8", + "PCIE_EE4A1_7", + "PCIE_SE2A2_11", + "PCIE_CFGERRAERHEADERLOG54", + "PCIE_IMUX29_R_14", + "PCIE_WW4A2_14", + "PCIE_WL1END0_1", + "PCIE_IMUX24_R_0", + "PCIE_MIMTXRDATA4", + "PCIE_NW2A1_2", + "PCIE_IMUX43_L_5", + "PCIE_LOGIC_OUTS_B9_R_18", + "PCIE_NE4C3_18", + "PCIE_FAN2_R_17", + "PCIE_WW2END0_12", + "PCIE_NW4A3_11", + "PCIE_NW2A1_19", + "PCIE_TRNRDLLPDATA57", + "PCIE_LH9_4", + "PCIE_LOGIC_OUTS_B18_L_2", + "PCIE_LH6_8", + "PCIE_WW2A1_4", + "PCIE_FAN5_L_17", + "PCIE_MIMRXWADDR12", + "PCIE_SE4BEG3_4", + "PCIE_MIMTXRADDR6", + "PCIE_TRNFCSEL1", + "PCIE_IMUX39_L_12", + "PCIE_IMUX19_R_11", + "PCIE_IMUX3_L_0", + "PCIE_NE4BEG0_3", + "PCIE_CFGERRAERHEADERLOG4", + "PCIE_NW2A1_15", + "PCIE_LOGIC_OUTS_B4_R_19", + "PCIE_MIMRXRADDR7", + "PCIE_ER1BEG3_12", + "PCIE_WW4END2_15", + "PCIE_FAN3_L_17", + "PCIE_LOGIC_OUTS_B6_R_7", + "PCIE_PMVSELECT0", + "PCIE_MIMTXRDATA52", + "PCIE_WW4B2_14", + "PCIE_FAN4_R_15", + "PCIE_IMUX31_L_19", + "PCIE_PIPERX4CHARISK0", + "PCIE_IMUX28_R_9", + "PCIE_PIPERX1DATA4", + "PCIE_IMUX20_R_18", + "PCIE_IMUX3_R_7", + "PCIE_EE4BEG3_4", + "PCIE_IMUX47_R_17", + "PCIE_LOGIC_OUTS_B8_R_2", + "PCIE_LOGIC_OUTS_B11_L_3", + "PCIE_NW2A1_0", + "PCIE_LOGIC_OUTS_B17_R_16", + "PCIE_CFGAERECRCCHECKEN", + "PCIE_LOGIC_OUTS_B14_L_7", + "PCIE_IMUX41_L_13", + "PCIE_IMUX17_R_11", + "PCIE_TRNRDLLPDATA45", + "PCIE_WW4A1_14", + "PCIE_IMUX0_R_14", + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL3", + "PCIE_IMUX38_L_6", + "PCIE_LOGIC_OUTS_B22_L_4", + "PCIE_NW4A1_13", + "PCIE_FAN4_L_13", + "PCIE_LOGIC_OUTS_B5_R_2", + "PCIE_CLK1_R_7", + "PCIE_CFGMGMTDWADDR5", + "PCIE_PIPERX3PHYSTATUS", + "PCIE_TRNRDLLPDATA29", + "PCIE_IMUX2_L_6", + "PCIE_NE2A2_16", + "PCIE_TRNRDLLPDATA52", + "PCIE_NE2A2_17", + "PCIE_FAN0_L_4", + "PCIE_IMUX18_R_6", + "PCIE_IMUX43_R_0", + "PCIE_CFGERRAERHEADERLOG101", + "PCIE_SW4END1_16", + "PCIE_IMUX29_L_14", + "PCIE_IMUX16_L_6", + "PCIE_FAN6_R_16", + "PCIE_MIMTXRDATA28", + "PCIE_NW2A1_12", + "PCIE_CFGDEVID5", + "PCIE_IMUX3_L_11", + "PCIE_LOGIC_OUTS_B13_L_10", + "PCIE_IMUX23_R_2", + "PCIE_CTRL0_R_0", + "PCIE_MIMTXWADDR8", + "PCIE_CFGDSN12", + "PCIE_NE2A3_5", + "PCIE_LOGIC_OUTS_B8_L_1", + "PCIE_IMUX45_L_5", + "PCIE_CLK0_L_8", + "PCIE_IMUX3_R_10", + "PCIE_IMUX14_L_2", + "PCIE_WW2END0_7", + "PCIE_TRNTD10", + "PCIE_BYP3_R_15", + "PCIE_IMUX26_L_0", + "PCIE_NW2A0_9", + "PCIE_IMUX26_L_19", + "PCIE_IMUX4_L_19", + "PCIE_IMUX37_L_2", + "PCIE_LOGIC_OUTS_B18_L_18", + "PCIE_IMUX40_R_19", + "PCIE_IMUX37_R_2", + "PCIE_EDTCHANNELSIN1", + "PCIE_LOGIC_OUTS_B23_R_2", + "PCIE_BLOCK_OUTS_B3_R_6", + "PCIE_NE4BEG3_17", + "PCIE_TRNRD109", + "PCIE_EE4BEG1_5", + "PCIE_SW4A0_10", + "PCIE_BLOCK_OUTS_B3_R_13", + "PCIE_BYP5_R_18", + "PCIE_IMUX27_R_11", + "PCIE_IMUX4_R_14", + "PCIE_TRNTSRCRDY", + "PCIE_EE2A0_13", + "PCIE_IMUX24_L_12", + "PCIE_IMUX22_R_15", + "PCIE_NE4BEG3_7", + "PCIE_NW2A0_13", + "PCIE_IMUX28_L_0", + "PCIE_LH12_1", + "PCIE_EDTCHANNELSIN3", + "PCIE_LOGIC_OUTS_B15_R_6", + "PCIE_IMUX7_L_4", + "PCIE_CFGMGMTBYTEENN2", + "PCIE_PIPETX3DATA2", + "PCIE_WW4END3_14", + "PCIE_WR1END1_7", + "PCIE_MIMTXWDATA3", + "PCIE_IMUX10_L_17", + "PCIE_BYP4_L_17", + "PCIE_IMUX26_L_3", + "PCIE_SW4A3_15", + "PCIE_IMUX6_L_6", + "PCIE_BYP1_R_11", + "PCIE_EE4BEG2_18", + "PCIE_WL1END2_3", + "PCIE_CFGDEVCONTROL2CPLTIMEOUTDIS", + "PCIE_TRNTD100", + "PCIE_IMUX15_R_5", + "PCIE_TL2ERRHDR25", + "PCIE_PIPETX7DATA15", + "PCIE_SE4C0_19", + "PCIE_LOGIC_OUTS_B22_R_12", + "PCIE_LOGIC_OUTS_B13_R_6", + "PCIE_CFGLINKSTATUSDLLACTIVE", + "PCIE_LH4_16", + "PCIE_WW4END3_5", + "PCIE_IMUX30_R_4", + "PCIE_CFGERRAERHEADERLOG53", + "PCIE_SW2A1_10", + "PCIE_LOGIC_OUTS_B0_L_1", + "PCIE_LOGIC_OUTS_B5_R_10", + "PCIE_PIPERX6PHYSTATUS", + "PCIE_SE4C3_6", + "PCIE_IMUX17_L_17", + "PCIE_TRNFCCPLH7", + "PCIE_FAN3_L_9", + "PCIE_MIMTXWDATA14", + "PCIE_NE4C0_18", + "PCIE_CTRL1_L_6", + "PCIE_IMUX10_R_6", + "PCIE_WL1END2_2", + "PCIE_MIMTXRDATA16", + "PCIE_LOGIC_OUTS_B21_R_1", + "PCIE_WR1END2_14", + "PCIE_IMUX36_L_8", + "PCIE_IMUX35_R_3", + "PCIE_NW2A3_10", + "PCIE_BYP4_L_5", + "PCIE_IMUX45_L_11", + "PCIE_WW4END2_11", + "PCIE_LH8_3", + "PCIE_TRNTD87", + "PCIE_LOGIC_OUTS_B10_R_13", + "PCIE_PIPERX6STATUS0", + "PCIE_LOGIC_OUTS_B6_L_5", + "PCIE_IMUX15_L_19", + "PCIE_LOGIC_OUTS_B14_L_11", + "PCIE_IMUX19_R_18", + "PCIE_WW4C2_12", + "PCIE_BYP3_R_2", + "PCIE_EE4B2_16", + "PCIE_LOGIC_OUTS_B16_R_4", + "PCIE_MIMRXRDATA67", + "PCIE_IMUX44_L_13", + "PCIE_IMUX32_L_15", + "PCIE_CTRL0_R_13", + "PCIE_IMUX8_R_5", + "PCIE_IMUX43_L_19", + "PCIE_TRNTD27", + "PCIE_PIPETXMARGIN1", + "PCIE_WW2A0_4", + "PCIE_IMUX30_L_2", + "PCIE_EL1BEG2_7", + "PCIE_IMUX3_L_14", + "PCIE_TRNTD92", + "PCIE_NE2A1_17", + "PCIE_EE4B1_3", + "PCIE_TRNFCCPLH2", + "PCIE_IMUX36_L_1", + "PCIE_LOGIC_OUTS_B18_R_0", + "PCIE_TRNRD37", + "PCIE_CFGERRTLPCPLHEADER47", + "PCIE_IMUX35_R_6", + "PCIE_SE4C3_13", + "PCIE_WW4B3_10", + "PCIE_LOGIC_OUTS_B2_R_11", + "PCIE_MIMTXWADDR3", + "PCIE_IMUX9_R_9", + "PCIE_IMUX20_L_16", + "PCIE_MIMRXRDATA36", + "PCIE_PIPERX6DATA10", + "PCIE_BYP5_R_8", + "PCIE_IMUX30_R_3", + "PCIE_IMUX33_R_3", + "PCIE_WW4C2_5", + "PCIE_IMUX13_L_17", + "PCIE_PL2RECOVERY", + "PCIE_IMUX6_L_16", + "PCIE_LH5_13", + "PCIE_IMUX42_R_13", + "PCIE_WL1END0_3", + "PCIE_LOGIC_OUTS_B20_L_18", + "PCIE_CFGDSN49", + "PCIE_SW2A1_4", + "PCIE_WL1END1_17", + "PCIE_LOGIC_OUTS_B13_R_16", + "PCIE_LOGIC_OUTS_B11_R_10", + "PCIE_NW2A0_5", + "PCIE_IMUX22_R_12", + "PCIE_CFGERRTLPCPLHEADER6", + "PCIE_LOGIC_OUTS_B17_L_9", + "PCIE_CFGVENDID2", + "PCIE_PIPETX6DATA14", + "PCIE_IMUX46_R_16", + "PCIE_PIPERX4DATA14", + "PCIE_EL1BEG2_16", + "PCIE_LOGIC_OUTS_B6_L_3", + "PCIE_SW2A3_17", + "PCIE_SE2A0_19", + "PCIE_EE2A2_11", + "PCIE_IMUX7_L_2", + "PCIE_WW2A1_11", + "PCIE_PMVSELECT1", + "PCIE_EE2A2_1", + "PCIE_NW4END2_5", + "PCIE_EE2BEG0_6", + "PCIE_IMUX31_R_18", + "PCIE_LOGIC_OUTS_B10_R_15", + "PCIE_BYP5_L_9", + "PCIE_DRPDO4", + "PCIE_NW4END2_11", + "PCIE_PIPERX1DATA5", + "PCIE_IMUX46_R_18", + "PCIE_DRPDI7", + "PCIE_LH9_19", + "PCIE_IMUX29_L_9", + "PCIE_MIMTXWADDR9", + "PCIE_PIPERX0DATA6", + "PCIE_TRNRD30", + "PCIE_EE4BEG3_3", + "PCIE_BYP0_L_7", + "PCIE_WW2A2_16", + "PCIE_EE4B1_12", + "PCIE_PIPERX0DATA11", + "PCIE_PIPERX5POLARITY", + "PCIE_IMUX1_L_18", + "PCIE_IMUX10_R_9", + "PCIE_NE2A2_2", + "PCIE_IMUX27_R_13", + "PCIE_TRNRD35", + "PCIE_TRNTD4", + "PCIE_EE2A2_5", + "PCIE_LOGIC_OUTS_B6_L_6", + "PCIE_WW4C3_2", + "PCIE_NE4C1_11", + "PCIE_WL1END3_0", + "PCIE_WW4C0_14", + "PCIE_LOGIC_OUTS_B11_R_0", + "PCIE_IMUX25_R_3", + "PCIE_WW2A0_17", + "PCIE_WW4END3_13", + "PCIE_BYP5_L_17", + "PCIE_NW4END0_2", + "PCIE_EE2A2_8", + "PCIE_EE4C2_14", + "PCIE_IMUX20_R_1", + "PCIE_IMUX43_R_7", + "PCIE_NE2A0_17", + "PCIE_TRNTDLLPDATA7", + "PCIE_BYP0_R_6", + "PCIE_WW4A2_10", + "PCIE_IMUX40_L_3", + "PCIE_IMUX21_R_12", + "PCIE_BYP1_L_1", + "PCIE_SW4A2_18", + "PCIE_LOGIC_OUTS_B14_R_13", + "PCIE_EE4A3_5", + "PCIE_MONITOR_P_11", + "PCIE_IMUX12_L_8", + "PCIE_BLOCK_OUTS_B0_L_1", + "PCIE_MONITOR_N_3", + "PCIE_SW2A2_12", + "PCIE_CFGSUBSYSID7", + "PCIE_MIMTXWDATA54", + "PCIE_TRNFCCPLH4", + "PCIE_LOGIC_OUTS_B4_R_14", + "PCIE_BYP4_R_7", + "PCIE_CFGERRAERHEADERLOG17", + "PCIE_TRNTDLLPDATA24", + "PCIE_IMUX41_R_14", + "PCIE_CFGMSGRECEIVEDDEASSERTINTC", + "PCIE_ER1BEG0_0", + "PCIE_PIPETX2DATA9", + "PCIE_IMUX17_R_7", + "PCIE_CFGPMWAKEN", + "PCIE_DBGVECB44", + "PCIE_SE4BEG0_4", + "PCIE_IMUX1_R_7", + "PCIE_LOGIC_OUTS_B16_L_14", + "PCIE_IMUX32_L_6", + "PCIE_BLOCK_OUTS_B1_L_15", + "PCIE_PIPERX0STATUS1", + "PCIE_FAN4_L_12", + "PCIE_CFGERRTLPCPLHEADER22", + "PCIE_WW4END0_2", + "PCIE_ER1BEG1_2", + "PCIE_WW4A3_12", + "PCIE_IMUX12_R_8", + "PCIE_MIMTXWDATA39", + "PCIE_BLOCK_OUTS_B0_L_0", + "PCIE_MIMRXRDATA23", + "PCIE_LOGIC_OUTS_B12_L_0", + "PCIE_LOGIC_OUTS_B13_L_0", + "PCIE_SW4A2_5", + "PCIE_LOGIC_OUTS_B15_L_18", + "PCIE_EE4B0_15", + "PCIE_LOGIC_OUTS_B3_R_8", + "PCIE_SE4C2_10", + "PCIE_WW2END1_13", + "PCIE_BYP2_R_18", + "PCIE_SE4C1_1", + "PCIE_LH9_11", + "PCIE_IMUX35_R_11", + "PCIE_IMUX47_R_5", + "PCIE_EE4A0_0", + "PCIE_IMUX41_R_9", + "PCIE_NE4C2_19", + "PCIE_LOGIC_OUTS_B17_L_6", + "PCIE_DBGVECB59", + "PCIE_PIPETXRATE", + "PCIE_SW4END2_13", + "PCIE_LOGIC_OUTS_B8_R_9", + "PCIE_IMUX22_L_8", + "PCIE_MIMRXRDATA58", + "PCIE_BLOCK_OUTS_B2_L_8", + "PCIE_SW2A0_8", + "PCIE_WR1END1_16", + "PCIE_IMUX43_L_14", + "PCIE_IMUX29_R_19", + "PCIE_CMRSTN", + "PCIE_LOGIC_OUTS_B5_R_19", + "PCIE_NW2A2_8", + "PCIE_FAN2_R_12", + "PCIE_XILUNCONNOUT21", + "PCIE_CFGMGMTDWADDR8", + "PCIE_CFGMGMTDI24", + "PCIE_MONITOR_N_14", + "PCIE_LOGIC_OUTS_B21_L_7", + "PCIE_MIMRXRDATA65", + "PCIE_FAN2_L_9", + "PCIE_CFGDSN9", + "PCIE_IMUX6_R_19", + "PCIE_BYP0_R_8", + "PCIE_IMUX8_L_10", + "PCIE_IMUX33_R_18", + "PCIE_IMUX11_L_4", + "PCIE_SW4END3_19", + "PCIE_WR1END3_6", + "PCIE_MONITOR_P_18", + "PCIE_FAN2_L_6", + "PCIE_LOGIC_OUTS_B4_R_5", + "PCIE_BYP1_L_2", + "PCIE_MONITOR_P_3", + "PCIE_WW4END2_5", + "PCIE_PLTXPMSTATE2", + "PCIE_BYP7_R_7", + "PCIE_WR1END0_3", + "PCIE_CFGSUBSYSVENDID14", + "PCIE_CLK1_R_14", + "PCIE_LOGIC_OUTS_B8_R_14", + "PCIE_LOGIC_OUTS_B7_R_17", + "PCIE_IMUX46_L_13", + "PCIE_LOGIC_OUTS_B19_L_6", + "PCIE_LOGIC_OUTS_B20_L_16", + "PCIE_EE4BEG0_3", + "PCIE_EL1BEG2_3", + "PCIE_LH5_0", + "PCIE_NW2A1_8", + "PCIE_SW4A2_19", + "PCIE_FAN1_R_1", + "PCIE_EE4A0_2", + "PCIE_BYP6_L_8", + "PCIE_EE2BEG0_11", + "PCIE_LH2_16", + "PCIE_LOGIC_OUTS_B17_R_2", + "PCIE_TL2ERRHDR36", + "PCIE_EE4C1_19", + "PCIE_CFGERRAERHEADERLOG0", + "PCIE_IMUX0_R_16", + "PCIE_NE4C2_17", + "PCIE_LOGIC_OUTS_B21_R_0", + "PCIE_SW4END1_10", + "PCIE_IMUX45_L_18", + "PCIE_IMUX45_L_16", + "PCIE_IMUX44_R_19", + "PCIE_DBGVECA33", + "PCIE_WW4A2_3", + "PCIE_EE2BEG2_1", + "PCIE_IMUX4_L_11", + "PCIE_CFGERRAERHEADERLOG14", + "PCIE_IMUX35_R_2", + "PCIE_IMUX16_L_9", + "PCIE_LOGIC_OUTS_B4_L_17", + "PCIE_BLOCK_OUTS_B1_R_1", + "PCIE_PLLINKGEN2CAP", + "PCIE_DBGVECB21", + "PCIE_CFGMGMTDO16", + "PCIE_CFGDEVID6", + "PCIE_CLK1_L_7", + "PCIE_IMUX36_R_10", + "PCIE_EE4B2_15", + "PCIE_LOGIC_OUTS_B20_L_19", + "PCIE_WL1END3_19", + "PCIE_SW2A0_13", + "PCIE_FAN5_L_7", + "PCIE_IMUX8_L_13", + "PCIE_IMUX3_L_7", + "PCIE_LOGIC_OUTS_B1_R_6", + "PCIE_IMUX13_R_18", + "PCIE_WW4C3_1", + "PCIE_LOGIC_OUTS_B8_R_17", + "PCIE_WR1END0_9", + "PCIE_MIMTXRDATA67", + "PCIE_IMUX12_L_12", + "PCIE_LOGIC_OUTS_B19_L_0", + "PCIE_WL1END1_5", + "PCIE_NE4C3_2", + "PCIE_XILUNCONNOUT34", + "PCIE_LOGIC_OUTS_B11_R_7", + "PCIE_BYP2_R_6", + "PCIE_LOGIC_OUTS_B3_R_5", + "PCIE_BYP6_R_19", + "PCIE_BYP3_R_0", + "PCIE_DBGMODE1", + "PCIE_IMUX6_R_9", + "PCIE_WW4END1_19", + "PCIE_ER1BEG3_15", + "PCIE_IMUX39_L_7", + "PCIE_CFGDSDEVICENUMBER1", + "PCIE_IMUX40_R_7", + "PCIE_EL1BEG1_2", + "PCIE_EE2A3_5", + "PCIE_IMUX2_R_6", + "PCIE_SE4BEG1_18", + "PCIE_IMUX42_L_13", + "PCIE_IMUX24_R_14", + "PCIE_WL1END3_11", + "PCIE_LH11_9", + "PCIE_NW4A0_18", + "PCIE_IMUX20_L_11", + "PCIE_EL1BEG1_8", + "PCIE_SW4A0_16", + "PCIE_IMUX9_R_15", + "PCIE_XILUNCONNOUT37", + "PCIE_LOGIC_OUTS_B23_L_15", + "PCIE_NW4END2_2", + "PCIE_MIMTXWDATA42", + "PCIE_PL2DIRECTEDLSTATE4", + "PCIE_EE4C3_7", + "PCIE_NE2A2_3", + "PCIE_IMUX47_R_18", + "PCIE_IMUX21_L_16", + "PCIE_IMUX22_R_9", + "PCIE_LOGIC_OUTS_B14_R_15", + "PCIE_IMUX6_L_14", + "PCIE_WL1END0_18", + "PCIE_PIPETXMARGIN0", + "PCIE_SW2A3_19", + "PCIE_SE4C0_1", + "PCIE_EE2BEG2_14", + "PCIE_TRNTD22", + "PCIE_IMUX19_R_4", + "PCIE_IMUX19_L_4", + "PCIE_EL1BEG1_12", + "PCIE_IMUX4_R_3", + "PCIE_LOGIC_OUTS_B4_L_8", + "PCIE_TL2ERRHDR19", + "PCIE_CTRL1_R_1", + "PCIE_IMUX1_R_9", + "PCIE_LOGIC_OUTS_B21_R_6", + "PCIE_BYP6_R_5", + "PCIE_LH10_12", + "PCIE_DRPDO14", + "PCIE_LOGIC_OUTS_B14_R_19", + "PCIE_TL2ERRHDR6", + "PCIE_ER1BEG0_13", + "PCIE_LH7_10", + "PCIE_WW4A2_9", + "PCIE_LOGIC_OUTS_B6_R_17", + "PCIE_LOGIC_OUTS_B9_L_14", + "PCIE_NW4A1_6", + "PCIE_FAN4_L_15", + "PCIE_LH7_2", + "PCIE_NE4C1_14", + "PCIE_LOGIC_OUTS_B16_R_11", + "PCIE_EE2A2_15", + "PCIE_LOGIC_OUTS_B2_L_16", + "PCIE_LOGIC_OUTS_B6_R_6", + "PCIE_CFGERRAERHEADERLOG75", + "PCIE_PIPERX1DATA2", + "PCIE_EE2BEG3_1", + "PCIE_IMUX37_L_11", + "PCIE_IMUX45_R_13", + "PCIE_BYP0_L_14", + "PCIE_PIPERX6DATA13", + "PCIE_FAN0_L_10", + "PCIE_EL1BEG0_5", + "PCIE_IMUX23_L_6", + "PCIE_CFGTRANSACTIONADDR6", + "PCIE_IMUX37_R_11", + "PCIE_IMUX19_L_19", + "PCIE_LOGIC_OUTS_B6_R_4", + "PCIE_IMUX6_R_18", + "PCIE_LOGIC_OUTS_B5_R_1", + "PCIE_CFGPCIECAPINTERRUPTMSGNUM1", + "PCIE_CFGDSN11", + "PCIE_IMUX25_L_11", + "PCIE_CFGMSGDATA1", + "PCIE_CLK0_R_11", + "PCIE_CFGERRAERHEADERLOG123", + "PCIE_SE4BEG3_16", + "PCIE_WW4B3_11", + "PCIE_IMUX12_L_4", + "PCIE_MIMTXWDATA20", + "PCIE_NW2A3_7", + "PCIE_IMUX6_R_7", + "PCIE_ER1BEG2_6", + "PCIE_NE4BEG3_9", + "PCIE_IMUX39_R_8", + "PCIE_WW4B1_5", + "PCIE_WR1END0_13", + "PCIE_LH11_11", + "PCIE_IMUX17_L_2", + "PCIE_LOGIC_OUTS_B21_R_11", + "PCIE_LOGIC_OUTS_B22_R_17", + "PCIE_IMUX38_L_9", + "PCIE_IMUX42_R_9", + "PCIE_IMUX33_R_4", + "PCIE_MONITOR_N_16", + "PCIE_SE4C3_11", + "PCIE_IMUX46_R_7", + "PCIE_IMUX38_L_5", + "PCIE_NE4C3_7", + "PCIE_IMUX6_R_11", + "PCIE_ER1BEG2_10", + "PCIE_CFGERRMALFORMEDN", + "PCIE_DBGVECB1", + "PCIE_EE2A1_13", + "PCIE_BYP3_L_13", + "PCIE_MIMTXWDATA44", + "PCIE_LOGIC_OUTS_B23_R_11", + "PCIE_IMUX41_L_19", + "PCIE_IMUX15_R_9", + "PCIE_TRNTD73", + "PCIE_LH3_10", + "PCIE_IMUX21_L_14", + "PCIE_BLOCK_OUTS_B0_L_10", + "PCIE_LOGIC_OUTS_B0_R_1", + "PCIE_WR1END3_4", + "PCIE_IMUX32_R_1", + "PCIE_IMUX37_R_14", + "PCIE_SW4END3_17", + "PCIE_CFGERRTLPCPLHEADER1", + "PCIE_PIPERX2VALID", + "PCIE_CFGERRTLPCPLHEADER33", + "PCIE_IMUX15_R_2", + "PCIE_TRNTD110", + "PCIE_PIPETX7DATA14", + "PCIE_CFGMGMTBYTEENN3", + "PCIE_IMUX31_L_11", + "PCIE_IMUX29_R_10", + "PCIE_LOGIC_OUTS_B18_L_19", + "PCIE_IMUX15_R_15", + "PCIE_CFGPMCSRPOWERSTATE1", + "PCIE_TRNRD50", + "PCIE_IMUX15_R_1", + "PCIE_EE4A3_8", + "PCIE_IMUX47_L_6", + "PCIE_EE4A2_3", + "PCIE_FAN2_R_9", + "PCIE_CFGLINKSTATUSCURRENTSPEED0", + "PCIE_TRNRD3", + "PCIE_PIPETX3DATA0", + "PCIE_IMUX45_L_2", + "PCIE_LOGIC_OUTS_B23_R_16", + "PCIE_LOGIC_OUTS_B16_R_13", + "PCIE_IMUX44_L_19", + "PCIE_CFGDSN31", + "PCIE_IMUX1_R_17", + "PCIE_TRNTD77", + "PCIE_IMUX43_R_4", + "PCIE_TL2ERRHDR40", + "PCIE_MIMRXWDATA17", + "PCIE_BYP6_R_14", + "PCIE_IMUX43_R_16", + "PCIE_LH5_6", + "PCIE_PIPERX6CHANISALIGNED", + "PCIE_LOGIC_OUTS_B7_R_0", + "PCIE_EE2BEG2_8", + "PCIE_WW2A2_10", + "PCIE_IMUX22_L_6", + "PCIE_ER1BEG2_3", + "PCIE_NW4END2_13", + "PCIE_IMUX9_R_14", + "PCIE_CFGDSN59", + "PCIE_PIPERX5PHYSTATUS", + "PCIE_XILUNCONNOUT26", + "PCIE_EE4A0_5", + "PCIE_LOGIC_OUTS_B8_L_16", + "PCIE_NW4A0_11", + "PCIE_CFGMGMTDO27", + "PCIE_IMUX44_R_0", + "PCIE_TRNFCPD1", + "PCIE_EL1BEG2_11", + "PCIE_CTRL0_L_11", + "PCIE_FAN7_R_2", + "PCIE_IMUX33_L_2", + "PCIE_PIPERX6CHARISK0", + "PCIE_LH12_15", + "PCIE_IMUX47_L_7", + "PCIE_LOGIC_OUTS_B19_L_14", + "PCIE_IMUX15_L_14", + "PCIE_IMUX4_L_16", + "PCIE_PLLANEREVERSALMODE0", + "PCIE_ER1BEG1_7", + "PCIE_MIMTXRADDR8", + "PCIE_EL1BEG0_17", + "PCIE_EE4A2_10", + "PCIE_NE4BEG1_0", + "PCIE_LOGIC_OUTS_B23_R_17", + "PCIE_NW4A2_10", + "PCIE_IMUX12_R_4", + "PCIE_CLK0_L_19", + "PCIE_WW4C2_19", + "PCIE_LOGIC_OUTS_B10_L_19", + "PCIE_ER1BEG2_18", + "PCIE_LOGIC_OUTS_B8_R_3", + "PCIE_FAN5_L_10", + "PCIE_BYP5_R_12", + "PCIE_IMUX42_R_14", + "PCIE_LH5_9", + "PCIE_TL2ERRHDR16", + "PCIE_IMUX47_L_17", + "PCIE_MIMTXWDATA33", + "PCIE_LOGIC_OUTS_B13_L_14", + "PCIE_EE4B2_12", + "PCIE_EE4BEG0_2", + "PCIE_LOGIC_OUTS_B19_R_8", + "PCIE_MIMTXWDATA18", + "PCIE_PLDIRECTEDLTSSMNEW4", + "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0", + "PCIE_EL1BEG2_18", + "PCIE_LOGIC_OUTS_B11_L_4", + "PCIE_BYP0_L_16", + "PCIE_MIMTXRDATA1", + "PCIE_TL2ERRHDR47", + "PCIE_PIPERX7STATUS2", + "PCIE_SE4C1_4", + "PCIE_FAN3_R_0", + "PCIE_CFGSUBSYSID3", + "PCIE_LOGIC_OUTS_B18_R_18", + "PCIE_LOGIC_OUTS_B21_L_16", + "PCIE_TRNRD2", + "PCIE_IMUX24_R_16", + "PCIE_WW4C0_4", + "PCIE_NE4BEG1_6", + "PCIE_FAN4_R_3", + "PCIE_BYP3_R_14", + "PCIE_LOGIC_OUTS_B21_L_3", + "PCIE_IMUX38_L_10", + "PCIE_IMUX30_R_11", + "PCIE_IMUX12_R_12", + "PCIE_SW4A1_2", + "PCIE_FAN7_R_6", + "PCIE_PIPETX3DATA13", + "PCIE_EDTCHANNELSIN8", + "PCIE_WR1END0_18", + "PCIE_BYP3_R_19", + "PCIE_LOGIC_OUTS_B6_R_13", + "PCIE_TRNTD56", + "PCIE_WW2END0_3", + "PCIE_PIPERX4DATA5", + "PCIE_EE2A0_10", + "PCIE_NE2A1_10", + "PCIE_LOGIC_OUTS_B9_R_11", + "PCIE_IMUX30_L_7", + "PCIE_CFGDEVID11", + "PCIE_MIMRXRDATA1", + "PCIE_CFGERRAERHEADERLOG31", + "PCIE_BLOCK_OUTS_B1_R_17", + "PCIE_CFGDSN44", + "PCIE_CFGERRAERHEADERLOG34", + "PCIE_LOGIC_OUTS_B22_R_3", + "PCIE_BYP5_R_9", + "PCIE_WW2END3_0", + "PCIE_IMUX38_L_15", + "PCIE_NW2A0_14", + "PCIE_LOGIC_OUTS_B23_L_10", + "PCIE_IMUX26_L_1", + "PCIE_LH1_1", + "PCIE_LOGIC_OUTS_B10_L_18", + "PCIE_TRNTD59", + "PCIE_SE2A1_19", + "PCIE_IMUX3_L_12", + "PCIE_TRNTD105", + "PCIE_PIPERX2STATUS2", + "PCIE_WW2END3_3", + "PCIE_LOGIC_OUTS_B1_L_8", + "PCIE_PIPERX1DATA7", + "PCIE_LOGIC_OUTS_B14_L_8", + "PCIE_IMUX21_L_7", + "PCIE_LOGIC_OUTS_B1_R_11", + "PCIE_IMUX0_R_18", + "PCIE_CTRL0_R_15", + "PCIE_IMUX41_R_0", + "PCIE_FAN6_L_16", + "PCIE_MIMRXRDATA16", + "PCIE_LOGIC_OUTS_B15_R_5", + "PCIE_IMUX45_L_4", + "PCIE_IMUX13_L_1", + "PCIE_CFGERRTLPCPLHEADER40", + "PCIE_IMUX18_R_4", + "PCIE_IMUX30_L_3", + "PCIE_MIMRXWADDR3", + "PCIE_SW2A0_12", + "PCIE_WW2END0_14", + "PCIE_BLOCK_OUTS_B1_L_12", + "PCIE_IMUX32_R_2", + "PCIE_BYP4_R_3", + "PCIE_PIPERX1DATA9", + "PCIE_LH3_4", + "PCIE_IMUX26_L_4", + "PCIE_NE4C3_0", + "PCIE_TRNFCPH0", + "PCIE_BYP5_R_2", + "PCIE_WW2A2_7", + "PCIE_IMUX38_L_19", + "PCIE_IMUX24_L_5", + "PCIE_NW2A2_12", + "PCIE_TRNTD103", + "PCIE_PIPERX1STATUS2", + "PCIE_SE2A0_15", + "PCIE_FAN6_R_2", + "PCIE_LOGIC_OUTS_B9_R_12", + "PCIE_LH10_13", + "PCIE_PIPERX2DATA5", + "PCIE_BLOCK_OUTS_B0_R_3", + "PCIE_IMUX47_L_3", + "PCIE_TRNFCPH1", + "PCIE_CFGDEVID10", + "PCIE_LOGIC_OUTS_B12_R_13", + "PCIE_TRNRD28", + "PCIE_IMUX19_L_17", + "PCIE_IMUX4_R_11", + "PCIE_IMUX33_L_12", + "PCIE_IMUX31_L_4", + "PCIE_CFGDSN4", + "PCIE_IMUX8_R_4", + "PCIE_EE4C3_10", + "PCIE_CFGERRAERHEADERLOG89", + "PCIE_IMUX11_R_18", + "PCIE_IMUX1_R_6", + "PCIE_NE4BEG1_14", + "PCIE_WW2END0_11", + "PCIE_BYP4_L_12", + "PCIE_EL1BEG1_19", + "PCIE_BYP2_L_11", + "PCIE_LOGIC_OUTS_B1_R_15", + "PCIE_NW4A2_14", + "PCIE_WW4B3_2", + "PCIE_WR1END2_19", + "PCIE_BYP7_R_16", + "PCIE_XILUNCONNOUT11", + "PCIE_NW2A1_9", + "PCIE_IMUX23_L_1", + "PCIE_CFGVCTCVCMAP1", + "PCIE_WR1END0_17", + "PCIE_MIMTXWDATA45", + "PCIE_DBGVECB25", + "PCIE_NW2A3_16", + "PCIE_DBGVECC1", + "PCIE_LH4_6", + "PCIE_SE4BEG1_12", + "PCIE_FAN2_R_2", + "PCIE_IMUX13_R_4", + "PCIE_CLK0_L_10", + "PCIE_IMUX22_R_18", + "PCIE_PIPERX2PHYSTATUS", + "PCIE_IMUX38_L_3", + "PCIE_LOGIC_OUTS_B11_L_11", + "PCIE_SE4BEG1_2", + "PCIE_IMUX46_L_2", + "PCIE_SE4BEG2_9", + "PCIE_CFGDSN27", + "PCIE_IMUX18_R_10", + "PCIE_CLK1_L_8", + "PCIE_LOGIC_OUTS_B2_L_11", + "PCIE_PLDBGVEC1", + "PCIE_NW2A2_13", + "PCIE_TRNRD105", + "PCIE_CFGMSGRECEIVEDASSERTINTB", + "PCIE_TRNRD78", + "PCIE_LH4_14", + "PCIE_SW2A1_3", + "PCIE_BLOCK_OUTS_B0_R_19", + "PCIE_CFGFORCECOMMONCLOCKOFF", + "PCIE_IMUX5_L_17", + "PCIE_SW2A1_11", + "PCIE_LOGIC_OUTS_B1_L_5", + "PCIE_PIPERX0VALID", + "PCIE_WW4END3_19", + "PCIE_BLOCK_OUTS_B3_L_7", + "PCIE_IMUX29_R_5", + "PCIE_IMUX41_L_7", + "PCIE_IMUX19_R_6", + "PCIE_EE2A3_15", + "PCIE_IMUX34_L_18", + "PCIE_MIMRXRDATA18", + "PCIE_TRNRD92", + "PCIE_EE2BEG2_12", + "PCIE_NW4END2_15", + "PCIE_MIMTXRDATA57", + "PCIE_CLK1_L_5", + "PCIE_LOGIC_OUTS_B4_R_10", + "PCIE_TRNTD31", + "PCIE_SW4A3_12", + "PCIE_XILUNCONNOUT1", + "PCIE_LOGIC_OUTS_B8_R_8", + "PCIE_CFGDEVID14", + "PCIE_IMUX47_L_13", + "PCIE_BYP0_R_5", + "PCIE_XILUNCONNOUT7", + "PCIE_BYP1_L_7", + "PCIE_IMUX25_L_19", + "PCIE_DRPDI9", + "PCIE_IMUX23_R_16", + "PCIE_NE4C2_7", + "PCIE_LOGIC_OUTS_B9_L_17", + "PCIE_IMUX12_L_1", + "PCIE_EE4A2_15", + "PCIE_LH6_0", + "PCIE_FAN7_L_11", + "PCIE_FAN3_R_17", + "PCIE_LOGIC_OUTS_B20_R_8", + "PCIE_BLOCK_OUTS_B1_L_10", + "PCIE_WW2END3_16", + "PCIE_WW4C0_18", + "PCIE_BYP3_R_6", + "PCIE_DBGVECA42", + "PCIE_IMUX11_L_3", + "PCIE_WW4END2_18", + "PCIE_IMUX10_L_2", + "PCIE_SW4A0_15", + "PCIE_TRNRD69", + "PCIE_EL1BEG3_0", + "PCIE_BLOCK_OUTS_B3_L_15", + "PCIE_PIPERX3DATA2", + "PCIE_SE2A2_0", + "PCIE_IMUX1_R_12", + "PCIE_EE4A2_12", + "PCIE_WW4C2_18", + "PCIE_LOGIC_OUTS_B10_R_17", + "PCIE_MIMRXWDATA65", + "PCIE_DBGVECB23", + "PCIE_IMUX23_L_2", + "PCIE_TL2ERRHDR59", + "PCIE_IMUX11_R_19", + "PCIE_SE2A3_15", + "PCIE_FAN7_L_18", + "PCIE_FAN6_L_12", + "PCIE_EL1BEG1_1", + "PCIE_IMUX4_R_18", + "PCIE_PIPERX6DATA3", + "PCIE_BYP2_R_11", + "PCIE_CLK0_R_16", + "PCIE_IMUX35_L_9", + "PCIE_NW4END3_5", + "PCIE_LOGIC_OUTS_B12_L_1", + "PCIE_LOGIC_OUTS_B6_R_5", + "PCIE_LOGIC_OUTS_B8_L_0", + "PCIE_WR1END2_4", + "PCIE_BYP3_L_15", + "PCIE_IMUX14_R_4", + "PCIE_FAN6_L_9", + "PCIE_IMUX3_R_2", + "PCIE_LOGIC_OUTS_B22_R_1", + "PCIE_PIPETX3DATA15", + "PCIE_CLK1_R_13", + "PCIE_IMUX32_R_18", + "PCIE_EE2A3_16", + "PCIE_SE4BEG2_6", + "PCIE_WR1END3_10", + "PCIE_WW4END1_9", + "PCIE_NE4C3_6", + "PCIE_WW4C1_12", + "PCIE_XILUNCONNOUT23", + "PCIE_MONITOR_N_2", + "PCIE_IMUX38_R_12", + "PCIE_IMUX34_L_16", + "PCIE_WW4B0_7", + "PCIE_BLOCK_OUTS_B2_L_14", + "PCIE_NE4C0_10", + "PCIE_BYP6_L_9", + "PCIE_XILUNCONNOUT38", + "PCIE_CFGMSGDATA8", + "PCIE_SE4BEG3_18", + "PCIE_PIPERX2CHARISK1", + "PCIE_SE4BEG3_12", + "PCIE_LOGIC_OUTS_B3_R_11", + "PCIE_NE4C2_2", + "PCIE_NE4BEG1_3", + "PCIE_EE4A1_16", + "PCIE_LOGIC_OUTS_B11_L_5", + "PCIE_IMUX23_R_1", + "PCIE_CFGERRTLPCPLHEADER29", + "PCIE_MONITOR_N_19", + "PCIE_WW4C1_10", + "PCIE_CLK1_R_9", + "PCIE_NW4END3_19", + "PCIE_IMUX27_L_12", + "PCIE_IMUX40_L_17", + "PCIE_IMUX20_R_9", + "PCIE_IMUX30_L_17", + "PCIE_CFGERRAERHEADERLOG33", + "PCIE_IMUX7_R_4", + "PCIE_IMUX38_R_0", + "PCIE_MIMTXRDATA55", + "PCIE_MIMRXWDATA36", + "PCIE_PLDBGVEC7", + "PCIE_LOGIC_OUTS_B19_R_5", + "PCIE_MIMRXRADDR1", + "PCIE_CFGINTERRUPTDI7", + "PCIE_LOGIC_OUTS_B8_L_14", + "PCIE_BLOCK_OUTS_B2_L_9", + "PCIE_LOGIC_OUTS_B8_L_13", + "PCIE_EL1BEG2_0", + "PCIE_SW2A3_2", + "PCIE_IMUX0_R_17", + "PCIE_IMUX13_L_5", + "PCIE_IMUX12_L_10", + "PCIE_IMUX18_L_0", + "PCIE_DBGVECA38", + "PCIE_MIMTXRDATA40", + "PCIE_PIPETX1ELECIDLE", + "PCIE_PIPERX5DATA1", + "PCIE_SE4C2_2", + "PCIE_IMUX44_R_1", + "PCIE_IMUX14_R_7", + "PCIE_SE4C0_10", + "PCIE_LH1_3", + "PCIE_LOGIC_OUTS_B20_L_10", + "PCIE_WW2A0_14", + "PCIE_BLOCK_OUTS_B2_L_19", + "PCIE_CLK1_R_8", + "PCIE_IMUX5_R_6", + "PCIE_WW2END2_15", + "PCIE_CFGVENDID8", + "PCIE_EE4BEG2_16", + "PCIE_TL2ERRHDR48", + "PCIE_IMUX37_L_9", + "PCIE_SE4C2_4", + "PCIE_IMUX24_L_10", + "PCIE_NE2A1_2", + "PCIE_FAN6_R_19", + "PCIE_CFGERRAERHEADERLOG58", + "PCIE_EE4C1_12", + "PCIE_IMUX45_L_7", + "PCIE_TRNFCNPH2", + "PCIE_IMUX31_L_6", + "PCIE_TRNTD123", + "PCIE_NE4BEG0_10", + "PCIE_WW4B1_12", + "PCIE_CFGMGMTDI7", + "PCIE_CFGDSN25", + "PCIE_MIMRXRDATA43", + "PCIE_CFGMGMTDI29", + "PCIE_LH1_7", + "PCIE_NW2A2_15", + "PCIE_IMUX20_R_3", + "PCIE_EE2BEG0_10", + "PCIE_CFGMGMTDI10", + "PCIE_MIMTXWDATA67", + "PCIE_CFGERRAERHEADERLOG42", + "PCIE_WW4C0_13", + "PCIE_EE4B3_0", + "PCIE_WR1END3_9", + "PCIE_XILUNCONNOUT13", + "PCIE_ER1BEG1_19", + "PCIE_NE4C2_5", + "PCIE_IMUX44_R_4", + "PCIE_EE4B2_1", + "PCIE_LOGIC_OUTS_B20_R_13", + "PCIE_WW4A1_2", + "PCIE_IMUX26_R_1", + "PCIE_LH9_16", + "PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE", + "PCIE_BLOCK_OUTS_B2_R_3", + "PCIE_IMUX2_R_7", + "PCIE_CFGERRTLPCPLHEADER30", + "PCIE_IMUX16_R_0", + "PCIE_CFGERRAERHEADERLOG112", + "PCIE_WW4C1_14", + "PCIE_EE4BEG0_5", + "PCIE_WW4B2_3", + "PCIE_WR1END3_7", + "PCIE_FAN6_L_18", + "PCIE_IMUX15_L_11", + "PCIE_TRNTD50", + "PCIE_IMUX22_L_16", + "PCIE_DBGVECB12", + "PCIE_TRNRDLLPDATA27", + "PCIE_LOGIC_OUTS_B18_R_16", + "PCIE_LOGIC_OUTS_B5_L_18", + "PCIE_IMUX47_L_15", + "PCIE_WL1END1_16", + "PCIE_WW2END2_6", + "PCIE_IMUX22_R_14", + "PCIE_IMUX27_R_2", + "PCIE_PIPERX7POLARITY", + "PCIE_PIPERX5STATUS1", + "PCIE_MIMRXRDATA48", + "PCIE_BYP1_L_5", + "PCIE_DBGVECC0", + "PCIE_SE2A0_10", + "PCIE_DRPDO12", + "PCIE_LOGIC_OUTS_B6_L_18", + "PCIE_MIMRXWDATA22", + "PCIE_LH6_4", + "PCIE_LOGIC_OUTS_B12_R_15", + "PCIE_IMUX32_R_8", + "PCIE_PIPETX5DATA3", + "PCIE_LOGIC_OUTS_B12_L_6", + "PCIE_IMUX34_L_15", + "PCIE_WW2A1_14", + "PCIE_FAN0_L_6", + "PCIE_IMUX29_R_17", + "PCIE_IMUX1_L_13", + "PCIE_PIPERX0DATA1", + "PCIE_IMUX20_L_15", + "PCIE_PIPETX7DATA0", + "PCIE_IMUX7_R_12", + "PCIE_ER1BEG1_8", + "PCIE_IMUX12_L_17", + "PCIE_FAN4_L_10", + "PCIE_BYP5_L_10", + "PCIE_LOGIC_OUTS_B15_R_14", + "PCIE_IMUX28_L_19", + "PCIE_IMUX27_R_18", + "PCIE_BLOCK_OUTS_B0_L_16", + "PCIE_FAN2_R_5", + "PCIE_MIMTXRDATA24", + "PCIE_PIPETX5DATA11", + "PCIE_IMUX4_L_13", + "PCIE_FAN0_L_12", + "PCIE_IMUX45_L_1", + "PCIE_IMUX47_L_1", + "PCIE_IMUX46_L_1", + "PCIE_DBGVECA46", + "PCIE_IMUX29_L_11", + "PCIE_SE2A1_3", + "PCIE_WW4B2_13", + "PCIE_FAN5_R_15", + "PCIE_IMUX0_L_9", + "PCIE_CFGDSBUSNUMBER4", + "PCIE_NW4END1_19", + "PCIE_SW4A3_16", + "PCIE_LOGIC_OUTS_B8_R_5", + "PCIE_IMUX43_L_4", + "PCIE_WW4B0_10", + "PCIE_CFGINTERRUPTASSERTN", + "PCIE_CTRL1_L_7", + "PCIE_PIPETX6DATA4", + "PCIE_BYP5_R_19", + "PCIE_MIMRXRDATA64", + "PCIE_CFGINTERRUPTMSIXENABLE", + "PCIE_LOGIC_OUTS_B2_L_2", + "PCIE_SE4C0_15", + "PCIE_EE4B0_16", + "PCIE_WW4A1_17", + "PCIE_TRNRDLLPDATA6", + "PCIE_CFGTRANSACTIONADDR2", + "PCIE_IMUX14_L_12", + "PCIE_CFGPORTNUMBER3", + "PCIE_CFGMGMTDO6", + "PCIE_MONITOR_N_12", + "PCIE_CFGERRAERHEADERLOG86", + "PCIE_NE2A3_2", + "PCIE_TL2ERRHDR2", + "PCIE_IMUX41_R_19", + "PCIE_IMUX22_R_1", + "PCIE_FAN0_L_14", + "PCIE_DBGVECA2", + "PCIE_IMUX33_L_19", + "PCIE_TRNRD93", + "PCIE_EE2A1_11", + "PCIE_IMUX1_L_9", + "PCIE_IMUX37_L_5", + "PCIE_PIPERX1DATA12", + "PCIE_IMUX21_L_11", + "PCIE_LOGIC_OUTS_B5_R_5", + "PCIE_IMUX8_L_4", + "PCIE_FAN2_L_0", + "PCIE_PIPETX4DATA2", + "PCIE_EE2A1_12", + "PCIE_CFGPMHALTASPML1N", + "PCIE_EE4BEG0_19", + "PCIE_IMUX33_L_1", + "PCIE_MIMRXWDATA66", + "PCIE_WW2A0_19", + "PCIE_IMUX13_L_12", + "PCIE_IMUX9_L_5", + "PCIE_EE2BEG2_15", + "PCIE_LOGIC_OUTS_B15_R_17", + "PCIE_IMUX3_L_13", + "PCIE_EE4BEG3_17", + "PCIE_IMUX18_R_2", + "PCIE_IMUX14_L_15", + "PCIE_EE4BEG1_3", + "PCIE_LOGIC_OUTS_B11_L_6", + "PCIE_IMUX46_R_1", + "PCIE_IMUX29_R_2", + "PCIE_WW4C0_12", + "PCIE_IMUX8_L_3", + "PCIE_CLK0_R_15", + "PCIE_LOGIC_OUTS_B17_L_15", + "PCIE_LOGIC_OUTS_B3_L_5", + "PCIE_CFGTRANSACTIONADDR3", + "PCIE_EE4A2_14", + "PCIE_SE2A3_2", + "PCIE_NE4C3_1", + "PCIE_MIMTXWADDR11", + "PCIE_NW4END2_8", + "PCIE_IMUX36_L_0", + "PCIE_WW4A1_3", + "PCIE_DRPDO7", + "PCIE_LOGIC_OUTS_B2_R_0", + "PCIE_DBGVECA50", + "PCIE_CFGMGMTDO11", + "PCIE_FAN4_L_0", + "PCIE_PIPETX7DATA12", + "PCIE_BYP2_L_8", + "PCIE_PIPETX5DATA4", + "PCIE_LOGIC_OUTS_B6_R_3", + "PCIE_IMUX5_L_12", + "PCIE_WW4B2_9", + "PCIE_LOGIC_OUTS_B11_L_16", + "PCIE_IMUX34_R_14", + "PCIE_IMUX40_L_6", + "PCIE_WW4A0_2", + "PCIE_IMUX23_R_6", + "PCIE_PLRSTN", + "PCIE_EE4C1_9", + "PCIE_CFGINTERRUPTDI0", + "PCIE_BYP2_R_5", + "PCIE_CFGERRAERHEADERLOG117", + "PCIE_FAN2_L_2", + "PCIE_WL1END0_15", + "PCIE_LOGIC_OUTS_B2_L_4", + "PCIE_WW2END0_13", + "PCIE_IMUX41_L_15", + "PCIE_FAN4_R_14", + "PCIE_IMUX42_L_2", + "PCIE_IMUX10_L_0", + "PCIE_IMUX43_L_7", + "PCIE_BLOCK_OUTS_B0_R_7", + "PCIE_EE2A1_19", + "PCIE_IMUX36_R_3", + "PCIE_IMUX27_L_5", + "PCIE_NW2A3_4", + "PCIE_SE2A1_12", + "PCIE_SW4A2_3", + "PCIE_CFGERRTLPCPLHEADER27", + "PCIE_TRNRDLLPDATA15", + "PCIE_LOGIC_OUTS_B13_L_13", + "PCIE_BLOCK_OUTS_B1_R_3", + "PCIE_IMUX13_L_2", + "PCIE_CFGMSGDATA9", + "PCIE_CFGERRTLPCPLHEADER3", + "PCIE_BLOCK_OUTS_B2_R_9", + "PCIE_PMVDIVIDE0", + "PCIE_LH11_19", + "PCIE_IMUX1_L_11", + "PCIE_TRNTDLLPDATA27", + "PCIE_WW2END2_8", + "PCIE_NE2A1_19", + "PCIE_IMUX17_R_19", + "PCIE_FAN3_L_6", + "PCIE_IMUX32_L_13", + "PCIE_LOGIC_OUTS_B1_L_9", + "PCIE_WR1END3_12", + "PCIE_EE4BEG1_18", + "PCIE_WR1END3_19", + "PCIE_PIPETX1DATA3", + "PCIE_EE4C2_16", + "PCIE_NW2A1_4", + "PCIE_CFGERRAERHEADERLOG93", + "PCIE_SE2A3_10", + "PCIE_PIPERX2CHARISK0", + "PCIE_BYP3_L_9", + "PCIE_CLK1_R_10", + "PCIE_SE4BEG3_17", + "PCIE_WW4A2_15", + "PCIE_LOGIC_OUTS_B3_R_6", + "PCIE_CFGDSN60", + "PCIE_IMUX7_R_3", + "PCIE_IMUX8_R_11", + "PCIE_EE2BEG0_1", + "PCIE_IMUX14_L_19", + "PCIE_FAN7_L_16", + "PCIE_IMUX18_L_8", + "PCIE_WL1END0_13", + "PCIE_EE2BEG2_16", + "PCIE_CLK1_R_16", + "PCIE_WW2END0_5", + "PCIE_IMUX15_L_5", + "PCIE_CFGLINKCONTROLRETRAINLINK", + "PCIE_FAN7_R_0", + "PCIE_EE4BEG0_14", + "PCIE_LOGIC_OUTS_B5_L_5", + "PCIE_WW4A2_8", + "PCIE_PIPERX2STATUS1", + "PCIE_TRNRD122", + "PCIE_IMUX45_L_12", + "PCIE_WW4B3_17", + "PCIE_IMUX25_L_4", + "PCIE_IMUX44_L_4", + "PCIE_PIPERX6DATA9", + "PCIE_LOGIC_OUTS_B21_L_11", + "PCIE_CFGDSN24", + "PCIE_BYP4_L_16", + "PCIE_TRNTD70", + "PCIE_EE2BEG0_2", + "PCIE_MIMTXWDATA0", + "PCIE_DRPADDR7", + "PCIE_PIPERX2STATUS0", + "PCIE_CFGTRANSACTIONTYPE", + "PCIE_LOGIC_OUTS_B2_L_9", + "PCIE_WL1END3_6", + "PCIE_BLOCK_OUTS_B1_L_19", + "PCIE_TL2ERRHDR28", + "PCIE_IMUX45_R_2", + "PCIE_FAN2_L_18", + "PCIE_PIPERX7DATA5", + "PCIE_LOGIC_OUTS_B0_L_3", + "PCIE_NE4BEG2_0", + "PCIE_LOGIC_OUTS_B16_L_2", + "PCIE_TRNRSRCDSC", + "PCIE_NE2A0_11", + "PCIE_WW4B3_14", + "PCIE_CFGERRAERHEADERLOG6", + "PCIE_PIPETX3DATA1", + "PCIE_IMUX0_L_2", + "PCIE_IMUX36_R_7", + "PCIE_LOGIC_OUTS_B1_R_9", + "PCIE_IMUX27_L_4", + "PCIE_BYP2_R_3", + "PCIE_PL2DIRECTEDLSTATE3", + "PCIE_NE4C3_11", + "PCIE_WR1END1_4", + "PCIE_PIPETX6DATA6", + "PCIE_LOGIC_OUTS_B1_R_8", + "PCIE_LOGIC_OUTS_B2_R_12", + "PCIE_LOGIC_OUTS_B3_R_13", + "PCIE_CLK1_L_4", + "PCIE_TRNRD24", + "PCIE_DBGVECA11", + "PCIE_CFGBRIDGESERREN", + "PCIE_NW4A0_15", + "PCIE_IMUX34_R_15", + "PCIE_IMUX9_L_2", + "PCIE_WW4END2_7", + "PCIE_SE4BEG2_1", + "PCIE_XILUNCONNOUT29", + "PCIE_EE4C2_5", + "PCIE_DBGVECB36", + "PCIE_WR1END3_13", + "PCIE_IMUX30_L_15", + "PCIE_LOGIC_OUTS_B15_R_2", + "PCIE_EE2A3_7", + "PCIE_SE4BEG3_5", + "PCIE_LOGIC_OUTS_B13_L_3", + "PCIE_WW2A1_2", + "PCIE_WW2A0_13", + "PCIE_WW4B0_4", + "PCIE_TRNRD118", + "PCIE_NE4BEG2_9", + "PCIE_EE4C3_2", + "PCIE_LOGIC_OUTS_B16_L_11", + "PCIE_MIMRXWDATA8", + "PCIE_FAN3_L_8", + "PCIE_LOGIC_OUTS_B1_L_11", + "PCIE_EE4A2_1", + "PCIE_NE4BEG1_1", + "PCIE_NE4BEG0_13", + "PCIE_CFGERRAERHEADERLOG74", + "PCIE_MIMTXRDATA51", + "PCIE_BYP3_R_16", + "PCIE_IMUX35_L_8", + "PCIE_IMUX18_L_6", + "PCIE_NE4BEG1_11", + "PCIE_IMUX42_R_12", + "PCIE_NW4A2_8", + "PCIE_WW4A2_7", + "PCIE_WW4END2_16", + "PCIE_LOGIC_OUTS_B11_L_13", + "PCIE_LOGIC_OUTS_B16_L_15", + "PCIE_PIPETX6DATA7", + "PCIE_IMUX17_R_10", + "PCIE_BYP5_R_4", + "PCIE_PIPETXDEEMPH", + "PCIE_IMUX29_L_12", + "PCIE_PIPERX2DATA6", + "PCIE_CFGLINKCONTROLLINKDISABLE", + "PCIE_LOGIC_OUTS_B5_R_0", + "PCIE_IMUX23_L_18", + "PCIE_PIPETX3POWERDOWN0", + "PCIE_IMUX28_R_2", + "PCIE_LOGIC_OUTS_B15_L_10", + "PCIE_CFGDSN46", + "PCIE_BYP1_L_8", + "PCIE_IMUX16_L_12", + "PCIE_CFGDEVCONTROLMAXPAYLOAD1", + "PCIE_NW4END0_8", + "PCIE_IMUX22_R_10", + "PCIE_ER1BEG2_17", + "PCIE_CTRL1_L_8", + "PCIE_IMUX33_R_1", + "PCIE_LOGIC_OUTS_B6_R_16", + "PCIE_IMUX0_R_4", + "PCIE_BYP2_L_7", + "PCIE_CFGERRTLPCPLHEADER4", + "PCIE_SE4C0_11", + "PCIE_IMUX2_R_16", + "PCIE_LH11_18", + "PCIE_LOGIC_OUTS_B16_L_5", + "PCIE_NW4A0_9", + "PCIE_EE2A2_6", + "PCIE_NE4C0_12", + "PCIE_DRPDO3", + "PCIE_IMUX20_L_12", + "PCIE_IMUX18_R_7", + "PCIE_DRPDI11", + "PCIE_CTRL0_R_17", + "PCIE_NE4C2_6", + "PCIE_DBGVECB30", + "PCIE_PIPERX6CHARISK1", + "PCIE_LOGIC_OUTS_B16_L_18", + "PCIE_WW2A2_18", + "PCIE_NW4END1_12", + "PCIE_MONITOR_P_1", + "PCIE_WW2A1_10", + "PCIE_CFGERRINTERNALCORN", + "PCIE_BLOCK_OUTS_B0_L_12", + "PCIE_WW4C0_5", + "PCIE_SE4C2_6", + "PCIE_EE4C0_6", + "PCIE_LOGIC_OUTS_B1_R_4", + "PCIE_IMUX28_L_2", + "PCIE_LOGIC_OUTS_B14_L_0", + "PCIE_CFGINTERRUPTDO4", + "PCIE_IMUX34_R_4", + "PCIE_WW4B1_4", + "PCIE_SW2A3_13", + "PCIE_LOGIC_OUTS_B6_R_12", + "PCIE_WW4C1_11", + "PCIE_TRNRBARHIT1", + "PCIE_LOGIC_OUTS_B17_R_10", + "PCIE_LOGIC_OUTS_B21_L_6", + "PCIE_MIMTXRDATA42", + "PCIE_IMUX1_L_4", + "PCIE_CLK0_R_14", + "PCIE_TRNTD44", + "PCIE_NE2A3_3", + "PCIE_IMUX2_R_17", + "PCIE_EE2BEG3_17", + "PCIE_SW2A1_7", + "PCIE_LOGIC_OUTS_B3_L_14", + "PCIE_LOGIC_OUTS_B9_R_4", + "PCIE_WL1END1_11", + "PCIE_CFGERRAERHEADERLOG52", + "PCIE_NW2A3_14", + "PCIE_PIPETX5DATA13", + "PCIE_LOGIC_OUTS_B11_L_15", + "PCIE_CFGMGMTDI22", + "PCIE_BYP2_L_2", + "PCIE_WW4END0_9", + "PCIE_TRNRD14", + "PCIE_WL1END3_5", + "PCIE_IMUX12_L_14", + "PCIE_SW2A3_16", + "PCIE_NW2A3_15", + "PCIE_WW4END2_6", + "PCIE_LOGIC_OUTS_B20_R_17", + "PCIE_TRNTD67", + "PCIE_EE2A0_16", + "PCIE_IMUX16_L_15", + "PCIE_EE2BEG1_1", + "PCIE_LOGIC_OUTS_B12_R_4", + "PCIE_NE4BEG1_13", + "PCIE_CFGMGMTDI1", + "PCIE_LOGIC_OUTS_B3_L_18", + "PCIE_WW4END1_7", + "PCIE_EE4B3_10", + "PCIE_LH10_18", + "PCIE_TRNTD0", + "PCIE_SW2A3_4", + "PCIE_LH6_13", + "PCIE_NW4A3_19", + "PCIE_IMUX13_L_11", + "PCIE_DBGVECB14", + "PCIE_DBGVECB19", + "PCIE_CFGERRTLPCPLHEADER28", + "PCIE_TRNRD111", + "PCIE_NW4END2_6", + "PCIE_EE4C3_0", + "PCIE_EDTCHANNELSOUT7", + "PCIE_LOGIC_OUTS_B22_R_13", + "PCIE_IMUX13_R_7", + "PCIE_CFGDSN3", + "PCIE_IMUX6_R_12", + "PCIE_IMUX28_L_14", + "PCIE_IMUX24_R_9", + "PCIE_IMUX12_R_5", + "PCIE_IMUX9_R_4", + "PCIE_TL2ERRHDR18", + "PCIE_IMUX11_L_11", + "PCIE_CFGDSN42", + "PCIE_LOGIC_OUTS_B11_L_10", + "PCIE_IMUX43_L_17", + "PCIE_SW4A1_1", + "PCIE_CLK0_L_0", + "PCIE_LOGIC_OUTS_B15_R_4", + "PCIE_EL1BEG2_14", + "PCIE_DBGVECB57", + "PCIE_CFGMGMTDO17", + "PCIE_LOGIC_OUTS_B0_L_8", + "PCIE_PIPERX7DATA9", + "PCIE_EE4C0_8", + "PCIE_IMUX9_L_4", + "PCIE_WW4C1_16", + "PCIE_BYP7_L_4", + "PCIE_ER1BEG2_7", + "PCIE_MIMTXRDATA7", + "PCIE_IMUX21_R_9", + "PCIE_BYP4_L_11", + "PCIE_NE4C0_1", + "PCIE_IMUX42_L_5", + "PCIE_WW2END2_2", + "PCIE_CLK1_L_3", + "PCIE_CFGMGMTDI23", + "PCIE_TRNRD0", + "PCIE_NW4A3_10", + "PCIE_TRNRD5", + "PCIE_CFGERRCORN", + "PCIE_SE4BEG0_15", + "PCIE_IMUX11_L_1", + "PCIE_TRNRERRFWD", + "PCIE_MIMTXRDATA10", + "PCIE_PIPETX6POWERDOWN1", + "PCIE_MIMRXRDATA20", + "PCIE_EDTCHANNELSIN6", + "PCIE_BLOCK_OUTS_B3_R_8", + "PCIE_NW4A0_5", + "PCIE_IMUX4_R_13", + "PCIE_LOGIC_OUTS_B12_R_16", + "PCIE_SE4BEG2_5", + "PCIE_IMUX34_R_11", + "PCIE_MIMTXRDATA49", + "PCIE_MIMRXWDATA12", + "PCIE_DBGVECA18", + "PCIE_CFGERRCPLABORTN", + "PCIE_LOGIC_OUTS_B9_L_11", + "PCIE_BYP5_L_2", + "PCIE_FAN5_L_14", + "PCIE_IMUX9_L_15", + "PCIE_CFGERRTLPCPLHEADER36", + "PCIE_SE4BEG2_18", + "PCIE_TRNRD121", + "PCIE_LH11_8", + "PCIE_MIMTXWDATA35", + "PCIE_IMUX31_L_13", + "PCIE_FAN6_L_6", + "PCIE_TRNTDLLPDATA26", + "PCIE_LOGIC_OUTS_B6_L_17", + "PCIE_IMUX7_L_1", + "PCIE_DBGVECB34", + "PCIE_BLOCK_OUTS_B1_R_0", + "PCIE_IMUX31_R_2", + "PCIE_LOGIC_OUTS_B15_L_17", + "PCIE_IMUX19_R_19", + "PCIE_LH4_11", + "PCIE_DRPDI13", + "PCIE_DBGVECA47", + "PCIE_IMUX46_L_9", + "PCIE_EL1BEG0_15", + "PCIE_IMUX13_L_19", + "PCIE_TRNTD20", + "PCIE_SW4END3_13", + "PCIE_EE4A2_17", + "PCIE_EE4C2_9", + "PCIE_TRNRSRCRDY", + "PCIE_DBGVECB63", + "PCIE_IMUX35_R_14", + "PCIE_WW4C1_0", + "PCIE_NW2A2_4", + "PCIE_TRNTD97", + "PCIE_EE4BEG0_17", + "PCIE_WW2END2_0", + "PCIE_IMUX15_L_13", + "PCIE_WW2A3_11", + "PCIE_NE4BEG0_8", + "PCIE_DBGVECA58", + "PCIE_IMUX7_L_19", + "PCIE_IMUX35_R_8", + "PCIE_PIPETX3DATA9", + "PCIE_BYP1_L_13", + "PCIE_ER1BEG2_4", + "PCIE_LH3_18", + "PCIE_CFGPORTNUMBER2", + "PCIE_LOGIC_OUTS_B11_R_19", + "PCIE_MIMRXWDATA55", + "PCIE_CLK0_L_5", + "PCIE_CFGMSGRECEIVEDDEASSERTINTB", + "PCIE_CFGDSN55", + "PCIE_IMUX27_L_0", + "PCIE_NE4C2_8", + "PCIE_SE4BEG1_14", + "PCIE_SW4A1_15", + "PCIE_EL1BEG2_9", + "PCIE_NW4END3_14", + "PCIE_NE4C3_4", + "PCIE_TRNRBARHIT5", + "PCIE_IMUX41_R_3", + "PCIE_EE4A1_19", + "PCIE_IMUX41_L_11", + "PCIE_EL1BEG2_6", + "PCIE_SW2A2_2", + "PCIE_LOGIC_OUTS_B7_L_18", + "PCIE_LOGIC_OUTS_B12_R_7", + "PCIE_NE4C1_7", + "PCIE_TRNFCCPLH1", + "PCIE_FAN4_R_19", + "PCIE_SW4END1_9", + "PCIE_ER1BEG0_8", + "PCIE_IMUX29_L_1", + "PCIE_WW4C1_1", + "PCIE_IMUX18_L_9", + "PCIE_IMUX1_R_8", + "PCIE_SE2A1_13", + "PCIE_CFGERRAERHEADERLOG88", + "PCIE_IMUX5_L_13", + "PCIE_CFGVENDID15", + "PCIE_IMUX29_L_2", + "PCIE_MIMTXWDATA15", + "PCIE_WW2A1_15", + "PCIE_FAN2_L_5", + "PCIE_SE4BEG2_14", + "PCIE_TL2ERRHDR20", + "PCIE_TRNRD126", + "PCIE_IMUX5_R_8", + "PCIE_CFGSUBSYSVENDID5", + "PCIE_DRPDO15", + "PCIE_DBGVECC4", + "PCIE_NW2A0_2", + "PCIE_DRPADDR1", + "PCIE_CFGERRAERHEADERLOG107", + "PCIE_FAN6_R_9", + "PCIE_FAN0_R_13", + "PCIE_WW4END3_10", + "PCIE_CFGDSFUNCTIONNUMBER1", + "PCIE_PIPERX7CHARISK0", + "PCIE_LOGIC_OUTS_B7_R_18", + "PCIE_CFGERRAERHEADERLOG3", + "PCIE_CFGMGMTDI12", + "PCIE_EE2A3_1", + "PCIE_IMUX3_L_16", + "PCIE_IMUX28_L_13", + "PCIE_IMUX25_L_3", + "PCIE_LOGIC_OUTS_B2_L_3", + "PCIE_LOGIC_OUTS_B17_L_12", + "PCIE_IMUX33_L_7", + "PCIE_IMUX44_R_6", + "PCIE_IMUX36_L_7", + "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT", + "PCIE_TL2ERRHDR53", + "PCIE_IMUX22_L_0", + "PCIE_LH7_6", + "PCIE_IMUX7_R_13", + "PCIE_CFGDSN10", + "PCIE_CLK1_L_15", + "PCIE_EL1BEG2_15", + "PCIE_BLOCK_OUTS_B1_L_1", + "PCIE_IMUX4_R_6", + "PCIE_DBGVECA35", + "PCIE_FAN6_L_1", + "PCIE_TRNRD87", + "PCIE_BLOCK_OUTS_B3_R_9", + "PCIE_BYP0_L_9", + "PCIE_SE2A2_9", + "PCIE_CFGERRTLPCPLHEADER43", + "PCIE_BYP7_L_1", + "PCIE_SW2A1_15", + "PCIE_PIPERX2DATA13", + "PCIE_IMUX18_L_18", + "PCIE_NE2A0_4", + "PCIE_IMUX42_R_17", + "PCIE_IMUX46_R_19", + "PCIE_BLOCK_OUTS_B2_L_1", + "PCIE_IMUX16_R_17", + "PCIE_CFGSUBSYSVENDID9", + "PCIE_CFGDEVCONTROLMAXPAYLOAD0", + "PCIE_IMUX25_R_12", + "PCIE_PLDIRECTEDLTSSMNEW0", + "PCIE_SW4A0_19", + "PCIE_EE2A1_1", + "PCIE_DBGVECA7", + "PCIE_CFGERRAERHEADERLOG114", + "PCIE_SW4A1_12", + "PCIE_IMUX26_L_9", + "PCIE_PIPETX2DATA14", + "PCIE_NW4END0_5", + "PCIE_IMUX22_L_13", + "PCIE_IMUX29_R_3", + "PCIE_EE4A1_15", + "PCIE_SE2A1_8", + "PCIE_EE2A1_6", + "PCIE_LH4_15", + "PCIE_IMUX43_L_1", + "PCIE_PIPERX3CHARISK0", + "PCIE_LOGIC_OUTS_B12_L_7", + "PCIE_IMUX42_R_16", + "PCIE_FAN7_R_15", + "PCIE_IMUX7_R_11", + "PCIE_CFGERRAERHEADERLOG48", + "PCIE_IMUX33_R_2", + "PCIE_BYP2_L_1", + "PCIE_NW4A1_8", + "PCIE_NW4A1_10", + "PCIE_IMUX2_L_12", + "PCIE_LOGIC_OUTS_B2_L_13", + "PCIE_NW4END1_11", + "PCIE_CFGROOTCONTROLPMEINTEN", + "PCIE_LOGIC_OUTS_B5_R_16", + "PCIE_EE4C0_1", + "PCIE_WW2A2_19", + "PCIE_NW4END2_0", + "PCIE_IMUX35_L_10", + "PCIE_IMUX4_L_7", + "PCIE_LOGIC_OUTS_B17_R_9", + "PCIE_TRNRDLLPDATA12", + "PCIE_EE4BEG1_2", + "PCIE_LOGIC_OUTS_B8_L_12", + "PCIE_LOGIC_OUTS_B2_L_8", + "PCIE_IMUX3_L_15", + "PCIE_DRPADDR5", + "PCIE_EE4BEG2_6", + "PCIE_PIPETX7POWERDOWN1", + "PCIE_BYP3_R_11", + "PCIE_IMUX8_L_8", + "PCIE_LOGIC_OUTS_B12_L_3", + "PCIE_TRNFCPH3", + "PCIE_SE2A2_6", + "PCIE_LOGIC_OUTS_B16_L_8", + "PCIE_TRNTDLLPDATA14", + "PCIE_EE4B0_18", + "PCIE_ER1BEG1_11", + "PCIE_IMUX7_L_3", + "PCIE_WW4END2_17", + "PCIE_LOGIC_OUTS_B1_L_0", + "PCIE_IMUX27_R_19", + "PCIE_MIMRXWDATA19", + "PCIE_WW4A3_4", + "PCIE_LH4_4", + "PCIE_CFGLINKCONTROLASPMCONTROL0", + "PCIE_IMUX31_R_7", + "PCIE_LOGIC_OUTS_B3_L_1", + "PCIE_XILUNCONNOUT20", + "PCIE_TRNRDLLPDATA42", + "PCIE_LOGIC_OUTS_B9_R_9", + "PCIE_DBGVECB32", + "PCIE_CFGERRAERHEADERLOG9", + "PCIE_IMUX6_R_5", + "PCIE_EE4C2_11", + "PCIE_TRNRD46", + "PCIE_CFGTRNPENDINGN", + "PCIE_MIMRXRDATA12", + "PCIE_EE2BEG3_3", + "PCIE_PIPERX7CHANISALIGNED", + "PCIE_SE2A3_7", + "PCIE_MIMRXWDATA37", + "PCIE_SW4A3_5", + "PCIE_EE4A3_13", + "PCIE_IMUX13_R_15", + "PCIE_TL2ERRHDR14", + "PCIE_IMUX31_R_19", + "PCIE_NW4END0_1", + "PCIE_BLOCK_OUTS_B2_L_4", + "PCIE_MIMTXRDATA0", + "PCIE_IMUX29_R_4", + "PCIE_WW4A3_16", + "PCIE_SW2A2_0", + "PCIE_FAN5_R_14", + "PCIE_BYP5_L_14", + "PCIE_LOGIC_OUTS_B0_L_13", + "PCIE_LOGIC_OUTS_B13_R_4", + "PCIE_WW4END0_19", + "PCIE_SW2A0_3", + "PCIE_SW2A3_11", + "PCIE_TRNTD115", + "PCIE_NW4END3_12", + "PCIE_EE2A0_3", + "PCIE_WW4C1_18", + "PCIE_LOGIC_OUTS_B5_R_15", + "PCIE_IMUX8_R_14", + "PCIE_TRNTD68", + "PCIE_FAN5_L_13", + "PCIE_IMUX18_R_18", + "PCIE_PIPETX0DATA1", + "PCIE_WW2END0_1", + "PCIE_CFGDSN33", + "PCIE_BYP3_L_19", + "PCIE_NW2A2_11", + "PCIE_EL1BEG3_18", + "PCIE_MIMTXWDATA65", + "PCIE_SW4A0_11", + "PCIE_IMUX21_L_17", + "PCIE_FAN4_R_11", + "PCIE_EE2BEG2_4", + "PCIE_IMUX45_R_3", + "PCIE_WW4C2_8", + "PCIE_TRNRD124", + "PCIE_IMUX9_R_16", + "PCIE_CFGMGMTDO5", + "PCIE_NW2A2_17", + "PCIE_IMUX16_R_19", + "PCIE_PIPECLK", + "PCIE_WW2END3_11", + "PCIE_NE2A1_5", + "PCIE_IMUX6_R_17", + "PCIE_EL1BEG0_12", + "PCIE_SE4C2_18", + "PCIE_IMUX17_L_4", + "PCIE_BLOCK_OUTS_B2_R_2", + "PCIE_LOGIC_OUTS_B2_R_8", + "PCIE_PLDIRECTEDLTSSMNEW1", + "PCIE_IMUX0_L_0", + "PCIE_NW4A1_19", + "PCIE_SW2A0_17", + "PCIE_EE4BEG1_9", + "PCIE_EE4C2_1", + "PCIE_IMUX16_R_3", + "PCIE_EE2A0_5", + "PCIE_EE2BEG1_8", + "PCIE_WW4A3_5", + "PCIE_IMUX6_R_3", + "PCIE_MIMTXWADDR1", + "PCIE_BYP6_R_8", + "PCIE_EE4B1_5", + "PCIE_CFGMGMTDI15", + "PCIE_LOGIC_OUTS_B4_L_6", + "PCIE_IMUX7_R_10", + "PCIE_IMUX16_R_6", + "PCIE_EE4B3_7", + "PCIE_EE2A0_15", + "PCIE_NE4BEG0_5", + "PCIE_LOGIC_OUTS_B10_R_5", + "PCIE_IMUX31_R_0", + "PCIE_SE2A0_18", + "PCIE_IMUX9_L_12", + "PCIE_IMUX35_L_3", + "PCIE_IMUX19_L_9", + "PCIE_WW4END2_0", + "PCIE_NW4A0_0", + "PCIE_SE2A0_13", + "PCIE_IMUX0_R_11", + "PCIE_TRNFCNPD10", + "PCIE_DBGVECA8", + "PCIE_IMUX4_L_12", + "PCIE_DBGVECB52", + "PCIE_NE4C3_17", + "PCIE_IMUX2_R_12", + "PCIE_IMUX20_R_11", + "PCIE_IMUX13_R_11", + "PCIE_LOGIC_OUTS_B8_L_10", + "PCIE_MIMRXWADDR8", + "PCIE_CFGVENDID6", + "PCIE_EE4A0_8", + "PCIE_BYP4_R_0", + "PCIE_FAN0_R_11", + "PCIE_TRNRD114", + "PCIE_TRNRD42", + "PCIE_IMUX30_R_12", + "PCIE_TRNRD13", + "PCIE_LOGIC_OUTS_B13_L_16", + "PCIE_BLOCK_OUTS_B1_R_6", + "PCIE_EE2BEG2_17", + "PCIE_NE4BEG1_4", + "PCIE_PIPERX0CHARISK1", + "PCIE_CFGERRECRCN", + "PCIE_FAN7_R_16", + "PCIE_SW2A0_6", + "PCIE_BYP0_R_10", + "PCIE_CFGERRTLPCPLHEADER2", + "PCIE_EE4BEG2_15", + "PCIE_IMUX24_L_2", + "PCIE_IMUX18_R_15", + "PCIE_IMUX16_R_12", + "PCIE_IMUX1_R_0", + "PCIE_NE2A1_13", + "PCIE_FAN7_L_3", + "PCIE_PIPETX3ELECIDLE", + "PCIE_SE4C3_1", + "PCIE_LOGIC_OUTS_B6_L_12", + "PCIE_DRPADDR4", + "PCIE_WW4B0_9", + "PCIE_IMUX26_R_18", + "PCIE_IMUX33_L_8", + "PCIE_LOGIC_OUTS_B11_R_8", + "PCIE_BYP5_L_6", + "PCIE_IMUX42_R_2", + "PCIE_PIPETX4DATA9", + "PCIE_TRNRDLLPDATA9", + "PCIE_NW4END1_10", + "PCIE_BLOCK_OUTS_B2_R_13", + "PCIE_BLOCK_OUTS_B1_L_8", + "PCIE_MIMRXRDATA0", + "PCIE_LOGIC_OUTS_B0_R_10", + "PCIE_MIMRXRDATA32", + "PCIE_IMUX11_R_5", + "PCIE_IMUX17_L_16", + "PCIE_SE2A1_5", + "PCIE_WW2A1_18", + "PCIE_NE4BEG1_7", + "PCIE_CLK1_L_11", + "PCIE_MIMRXRDATA8", + "PCIE_IMUX28_L_16", + "PCIE_LOGIC_OUTS_B8_L_5", + "PCIE_CTRL1_R_5", + "PCIE_EE4B3_19", + "PCIE_NE4BEG0_4", + "PCIE_BLOCK_OUTS_B3_L_2", + "PCIE_LOGIC_OUTS_B14_L_4", + "PCIE_LH9_18", + "PCIE_WW4C3_18", + "PCIE_BLOCK_OUTS_B3_R_3", + "PCIE_LOGIC_OUTS_B18_L_15", + "PCIE_IMUX47_L_12", + "PCIE_SE2A3_16", + "PCIE_IMUX22_R_3", + "PCIE_BYP6_R_3", + "PCIE_BYP1_R_18", + "PCIE_NW2A1_16", + "PCIE_LOGIC_OUTS_B22_L_8", + "PCIE_EE4C2_0", + "PCIE_IMUX7_R_17", + "PCIE_IMUX30_L_16", + "PCIE_LOGIC_OUTS_B17_L_7", + "PCIE_NE4C3_9", + "PCIE_FAN1_R_10", + "PCIE_SE2A2_10", + "PCIE_LH10_6", + "PCIE_LOGIC_OUTS_B19_L_4", + "PCIE_SW4END3_8", + "PCIE_LH10_8", + "PCIE_EDTCHANNELSIN5", + "PCIE_BYP3_L_1", + "PCIE_IMUX11_R_15", + "PCIE_PIPETX2DATA4", + "PCIE_SW2A3_8", + "PCIE_IMUX24_L_4", + "PCIE_IMUX46_L_18", + "PCIE_IMUX14_R_5", + "PCIE_TL2ERRHDR4", + "PCIE_IMUX27_L_2", + "PCIE_WL1END0_5", + "PCIE_LOGIC_OUTS_B18_L_13", + "PCIE_DBGVECB29", + "PCIE_MIMRXWDATA2", + "PCIE_NE4BEG0_1", + "PCIE_IMUX42_L_8", + "PCIE_LOGIC_OUTS_B19_L_13", + "PCIE_SE2A0_16", + "PCIE_EE4A3_9", + "PCIE_WW4B1_19", + "PCIE_LOGIC_OUTS_B15_L_19", + "PCIE_SW4END0_8", + "PCIE_WR1END0_2", + "PCIE_EE4A0_10", + "PCIE_CFGMGMTDI13", + "PCIE_EE2BEG3_19", + "PCIE_CFGERRCPLTIMEOUTN", + "PCIE_LH11_7", + "PCIE_CFGLINKCONTROLEXTENDEDSYNC", + "PCIE_BLOCK_OUTS_B0_L_13", + "PCIE_CFGPCIECAPINTERRUPTMSGNUM2", + "PCIE_CFGMGMTDO8", + "PCIE_WL1END1_19", + "PCIE_CFGINTERRUPTDI1", + "PCIE_IMUX3_L_19", + "PCIE_IMUX24_R_4", + "PCIE_BYP4_L_9", + "PCIE_IMUX32_R_13", + "PCIE_SW4END3_1", + "PCIE_MIMRXWDATA11", + "PCIE_LOGIC_OUTS_B9_L_6", + "PCIE_FAN7_R_19", + "PCIE_LOGIC_OUTS_B11_R_17", + "PCIE_SW4A0_7", + "PCIE_DBGVECA4", + "PCIE_CFGSUBSYSID10", + "PCIE_CTRL1_R_13", + "PCIE_BYP5_L_4", + "PCIE_LOGIC_OUTS_B10_R_9", + "PCIE_EE4BEG0_7", + "PCIE_MIMRXRDATA22", + "PCIE_NW4END2_17", + "PCIE_IMUX25_L_12", + "PCIE_LOGIC_OUTS_B4_L_4", + "PCIE_EE2BEG2_9", + "PCIE_CFGERRTLPCPLHEADER39", + "PCIE_BYP2_L_19", + "PCIE_LOGIC_OUTS_B14_L_13", + "PCIE_MIMTXWDATA23", + "PCIE_LOGIC_OUTS_B2_R_7", + "PCIE_LOGIC_OUTS_B14_R_0", + "PCIE_ER1BEG0_7", + "PCIE_EE4A1_4", + "PCIE_MIMTXRDATA18", + "PCIE_LOGIC_OUTS_B3_R_14", + "PCIE_CFGSUBSYSID2", + "PCIE_TRNRD15", + "PCIE_BYP2_R_14", + "PCIE_FAN0_L_7", + "PCIE_NE4C2_11", + "PCIE_BYP4_R_15", + "PCIE_FAN2_R_4", + "PCIE_IMUX18_R_11", + "PCIE_LOGIC_OUTS_B12_L_14", + "PCIE_BYP2_L_4", + "PCIE_IMUX10_L_11", + "PCIE_WW4B2_1", + "PCIE_CFGERRMCBLOCKEDN", + "PCIE_IMUX42_R_1", + "PCIE_IMUX19_L_1", + "PCIE_SW4END1_18", + "PCIE_SW4END3_14", + "PCIE_FAN3_R_19", + "PCIE_SW4END2_0", + "PCIE_SE4C1_18", + "PCIE_IMUX3_L_10", + "PCIE_CFGERRINTERNALUNCORN", + "PCIE_NE2A1_4", + "PCIE_IMUX26_R_8", + "PCIE_LOGIC_OUTS_B14_L_6", + "PCIE_EE4BEG0_6", + "PCIE_IMUX7_R_8", + "PCIE_EE2BEG0_5", + "PCIE_LH9_13", + "PCIE_IMUX30_L_0", + "PCIE_SE4BEG0_18", + "PCIE_WL1END0_12", + "PCIE_IMUX25_R_17", + "PCIE_MIMTXRDATA59", + "PCIE_IMUX15_L_6", + "PCIE_WW4END1_15", + "PCIE_LH9_1", + "PCIE_SW4END3_12", + "PCIE_LH8_18", + "PCIE_CFGERRAERHEADERLOG68", + "PCIE_IMUX25_R_7", + "PCIE_TL2ERRMALFORMED", + "PCIE_IMUX35_R_16", + "PCIE_CFGDSN45", + "PCIE_PIPETX4DATA12", + "PCIE_PL2RXELECIDLE", + "PCIE_NE4C2_9", + "PCIE_PIPERX1VALID", + "PCIE_LOGIC_OUTS_B13_L_15", + "PCIE_EE2BEG1_6", + "PCIE_EE2BEG2_2", + "PCIE_BYP6_R_18", + "PCIE_NE4C3_16", + "PCIE_XILUNCONNOUT22", + "PCIE_PLDOWNSTREAMDEEMPHSOURCE", + "PCIE_LOGIC_OUTS_B9_L_0", + "PCIE_TL2ERRHDR46", + "PCIE_LOGIC_OUTS_B17_R_0", + "PCIE_IMUX31_R_16", + "PCIE_LH10_0", + "PCIE_LOGIC_OUTS_B13_L_7", + "PCIE_BYP1_L_3", + "PCIE_EE4BEG1_13", + "PCIE_WL1END2_19", + "PCIE_EE4C1_17", + "PCIE_IMUX6_L_3", + "PCIE_TRNTD58", + "PCIE_ER1BEG1_0", + "PCIE_CFGMSGRECEIVEDERRNONFATAL", + "PCIE_IMUX31_L_15", + "PCIE_PIPETX2DATA1", + "PCIE_WW4END3_12", + "PCIE_WW4C0_8", + "PCIE_CFGERRAERHEADERLOG61", + "PCIE_LOGIC_OUTS_B1_L_12", + "PCIE_CFGMGMTDO26", + "PCIE_FAN2_L_17", + "PCIE_LOGIC_OUTS_B5_L_3", + "PCIE_CFGMSGRECEIVEDPMETO", + "PCIE_WW4A3_7", + "PCIE_IMUX0_R_19", + "PCIE_IMUX32_R_4", + "PCIE_IMUX41_R_12", + "PCIE_DBGVECA29", + "PCIE_IMUX39_R_0", + "PCIE_CFGERRAERHEADERLOG104", + "PCIE_IMUX8_R_9", + "PCIE_IMUX25_L_5", + "PCIE_EE4A2_6", + "PCIE_IMUX39_L_2", + "PCIE_EDTCHANNELSOUT5", + "PCIE_EE2BEG0_19", + "PCIE_LOGIC_OUTS_B12_L_16", + "PCIE_SE2A1_18", + "PCIE_LOGIC_OUTS_B11_R_15", + "PCIE_RECEIVEDFUNCLVLRSTN", + "PCIE_BLOCK_OUTS_B2_L_16", + "PCIE_TRNRD27", + "PCIE_IMUX14_L_9", + "PCIE_DLRSTN", + "PCIE_EE2BEG3_9", + "PCIE_SW4A3_10", + "PCIE_NE4BEG3_18", + "PCIE_FAN1_R_15", + "PCIE_NE2A3_8", + "PCIE_MONITOR_P_16", + "PCIE_FAN5_L_6", + "PCIE_CFGERRAERHEADERLOG59", + "PCIE_DBGVECB47", + "PCIE_EE2BEG3_15", + "PCIE_WL1END0_6", + "PCIE_BYP2_R_10", + "PCIE_TL2PPMSUSPENDREQ", + "PCIE_WW4B1_9", + "PCIE_MIMRXWDATA21", + "PCIE_IMUX35_R_13", + "PCIE_LH8_4", + "PCIE_IMUX9_L_6", + "PCIE_IMUX27_R_0", + "PCIE_LH4_2", + "PCIE_TRNTD78", + "PCIE_LOGIC_OUTS_B23_L_17", + "PCIE_IMUX30_R_6", + "PCIE_LOGIC_OUTS_B23_L_5", + "PCIE_IMUX32_L_4", + "PCIE_LOGIC_OUTS_B0_L_2", + "PCIE_LOGIC_OUTS_B12_L_4", + "PCIE_IMUX1_R_10", + "PCIE_MONITOR_N_6", + "PCIE_FAN5_L_11", + "PCIE_SW4END1_17", + "PCIE_TRNTD62", + "PCIE_IMUX42_L_18", + "PCIE_EE4A1_8", + "PCIE_IMUX8_L_6", + "PCIE_TRNRDLLPDATA8", + "PCIE_LOGIC_OUTS_B14_R_3", + "PCIE_IMUX20_L_18", + "PCIE_BYP0_L_6", + "PCIE_IMUX28_L_18", + "PCIE_NW4A1_14", + "PCIE_LOGIC_OUTS_B16_R_3", + "PCIE_LH1_17", + "PCIE_IMUX4_R_7", + "PCIE_LOGIC_OUTS_B17_R_4", + "PCIE_MIMTXRDATA2", + "PCIE_SW4END1_4", + "PCIE_ER1BEG2_12", + "PCIE_LH12_7", + "PCIE_IMUX31_R_13", + "PCIE_WW2END3_4", + "PCIE_LH5_11", + "PCIE_EDTUPDATE", + "PCIE_IMUX19_L_8", + "PCIE_IMUX29_L_3", + "PCIE_IMUX37_L_18", + "PCIE_BYP3_L_5", + "PCIE_BYP3_L_7", + "PCIE_SE2A2_4", + "PCIE_EE2BEG3_10", + "PCIE_CFGERRAERHEADERLOG50", + "PCIE_IMUX18_L_19", + "PCIE_IMUX40_L_2", + "PCIE_NW2A1_18", + "PCIE_LOGIC_OUTS_B6_L_16", + "PCIE_SE2A0_17", + "PCIE_FAN3_L_2", + "PCIE_LOGIC_OUTS_B7_L_13", + "PCIE_TRNTBUFAV4", + "PCIE_IMUX18_L_5", + "PCIE_CFGMGMTWRENN", + "PCIE_SW2A0_2", + "PCIE_CTRL0_R_18", + "PCIE_DBGVECA32", + "PCIE_IMUX30_R_10", + "PCIE_BYP0_L_0", + "PCIE_CTRL0_L_9", + "PCIE_IMUX0_L_16", + "PCIE_IMUX47_R_10", + "PCIE_EE2A3_2", + "PCIE_IMUX9_R_13", + "PCIE_EL1BEG1_3", + "PCIE_WL1END1_2", + "PCIE_CFGERRAERHEADERLOG118", + "PCIE_CFGROOTCONTROLSYSERRNONFATALERREN", + "PCIE_PIPERX7STATUS0", + "PCIE_BYP3_L_8", + "PCIE_NW4A0_13", + "PCIE_EE4BEG1_8", + "PCIE_NE4C0_3", + "PCIE_MIMTXWDATA60", + "PCIE_TRNTDLLPDATA29", + "PCIE_IMUX7_R_0", + "PCIE_CFGDEVCONTROLMAXREADREQ0", + "PCIE_TRNFCNPH0", + "PCIE_IMUX35_L_19", + "PCIE_WW4C2_9", + "PCIE_TRNRD101", + "PCIE_LH7_3", + "PCIE_FAN4_L_19", + "PCIE_SW4END0_14", + "PCIE_BLOCK_OUTS_B1_L_9", + "PCIE_WW4A0_4", + "PCIE_WW4END3_3", + "PCIE_PIPETX6DATA15", + "PCIE_IMUX31_L_7", + "PCIE_MIMTXWDATA53", + "PCIE_SE4C0_12", + "PCIE_MIMTXWDATA63", + "PCIE_MIMTXWDATA56", + "PCIE_NW4END3_15", + "PCIE_IMUX37_L_0", + "PCIE_LH7_7", + "PCIE_LH8_0", + "PCIE_FAN0_L_1", + "PCIE_IMUX27_L_13", + "PCIE_IMUX5_R_3", + "PCIE_FAN2_L_8", + "PCIE_LOGIC_OUTS_B4_R_6", + "PCIE_EE4B0_12", + "PCIE_FAN1_R_6", + "PCIE_TRNTD64", + "PCIE_ER1BEG3_7", + "PCIE_IMUX43_L_11", + "PCIE_EL1BEG2_1", + "PCIE_LH7_14", + "PCIE_EE4B0_10", + "PCIE_LOGIC_OUTS_B1_R_3", + "PCIE_LOGIC_OUTS_B7_L_17", + "PCIE_IMUX32_R_0", + "PCIE_MONITOR_P_6", + "PCIE_DBGVECA6", + "PCIE_EL1BEG0_8", + "PCIE_NW4A3_2", + "PCIE_TRNTDLLPDATA1", + "PCIE_WW4END2_19", + "PCIE_LH9_14", + "PCIE_IMUX43_L_16", + "PCIE_CFGPCIECAPINTERRUPTMSGNUM0", + "PCIE_CTRL0_L_1", + "PCIE_IMUX45_R_6", + "PCIE_IMUX18_L_3", + "PCIE_IMUX20_R_16", + "PCIE_PIPERX3DATA11", + "PCIE_WW4END1_10", + "PCIE_CFGDSN41", + "PCIE_NW4A0_4", + "PCIE_BYP3_L_12", + "PCIE_NE2A3_19", + "PCIE_WW4B1_17", + "PCIE_TRNRDLLPDATA37", + "PCIE_CFGLINKSTATUSBANDWIDTHSTATUS", + "PCIE_IMUX19_L_16", + "PCIE_IMUX35_R_9", + "PCIE_WW4B0_2", + "PCIE_SE4C2_8", + "PCIE_SE4BEG1_16", + "PCIE_IMUX47_R_1", + "PCIE_LOGIC_OUTS_B18_R_11", + "PCIE_EE4A1_13", + "PCIE_IMUX36_R_13", + "PCIE_CFGPMFORCESTATE0", + "PCIE_SW4END0_16", + "PCIE_MIMRXWDATA64", + "PCIE_NE2A2_19", + "PCIE_PIPETX6DATA10", + "PCIE_LOGIC_OUTS_B1_L_18", + "PCIE_CFGERRAERHEADERLOG84", + "PCIE_FAN3_L_19", + "PCIE_MIMRXRDATA11", + "PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK", + "PCIE_TRNRD117", + "PCIE_IMUX2_L_4", + "PCIE_IMUX44_L_14", + "PCIE_IMUX13_R_19", + "PCIE_WW2END1_18", + "PCIE_LOGIC_OUTS_B3_R_10", + "PCIE_TRNFCCPLD0", + "PCIE_MIMTXWEN", + "PCIE_PLDBGMODE0", + "PCIE_EL1BEG3_6", + "PCIE_IMUX14_R_0", + "PCIE_NW4END1_16", + "PCIE_PIPETX5DATA5", + "PCIE_PIPETX6COMPLIANCE", + "PCIE_EL1BEG3_19", + "PCIE_WL1END0_4", + "PCIE_BLOCK_OUTS_B1_R_11", + "PCIE_MIMTXWDATA32", + "PCIE_DBGSCLRA", + "PCIE_BLOCK_OUTS_B0_L_17", + "PCIE_PLTXPMSTATE0", + "PCIE_PIPETX1DATA9", + "PCIE_SE4C3_10", + "PCIE_CFGERRPOISONEDN", + "PCIE_IMUX19_R_0", + "PCIE_LH2_19", + "PCIE_FAN4_L_6", + "PCIE_IMUX37_R_12", + "PCIE_NE2A2_11", + "PCIE_SE4C3_15", + "PCIE_IMUX25_R_0", + "PCIE_NW4END3_9", + "PCIE_WW2END0_4", + "PCIE_PIPETX6DATA1", + "PCIE_CFGERRAERHEADERLOG72", + "PCIE_IMUX39_R_7", + "PCIE_BLOCK_OUTS_B0_R_2", + "PCIE_CTRL1_L_5", + "PCIE_CTRL1_R_11", + "PCIE_EE4BEG3_7", + "PCIE_IMUX35_L_2", + "PCIE_PLDBGVEC3", + "PCIE_WW4C2_10", + "PCIE_LOGIC_OUTS_B15_R_15", + "PCIE_SE2A2_18", + "PCIE_LOGIC_OUTS_B22_L_17", + "PCIE_LH6_15", + "PCIE_MONITOR_P_2", + "PCIE_CFGERRTLPCPLHEADER11", + "PCIE_TRNTD101", + "PCIE_LOGIC_OUTS_B20_R_1", + "PCIE_FAN1_R_17", + "PCIE_FAN7_L_15", + "PCIE_EE4BEG0_18", + "PCIE_IMUX39_L_11", + "PCIE_IMUX40_R_2", + "PCIE_LOGIC_OUTS_B19_L_11", + "PCIE_MIMRXRDATA63", + "PCIE_CLK1_L_6", + "PCIE_NW2A3_18", + "PCIE_LOGIC_OUTS_B9_R_19", + "PCIE_EL1BEG0_18", + "PCIE_CFGERRAERHEADERLOG120", + "PCIE_BLOCK_OUTS_B0_R_14", + "PCIE_IMUX46_R_15", + "PCIE_IMUX16_R_1", + "PCIE_FAN6_R_4", + "PCIE_BYP4_R_2", + "PCIE_EE4A0_6", + "PCIE_MIMRXREN", + "PCIE_PLSELLNKRATE", + "PCIE_BYP7_L_12", + "PCIE_SW4END1_2", + "PCIE_PIPETX1DATA13", + "PCIE_IMUX24_R_19", + "PCIE_BLOCK_OUTS_B0_R_5", + "PCIE_CFGERRAERHEADERLOG81", + "PCIE_CFGERRAERHEADERLOG115", + "PCIE_PIPETX4DATA13", + "PCIE_TRNTD108", + "PCIE_TRNTERRFWD", + "PCIE_EE4BEG1_17", + "PCIE_WW4END1_5", + "PCIE_LOGIC_OUTS_B18_R_14", + "PCIE_LOGIC_OUTS_B7_L_15", + "PCIE_WL1END3_1", + "PCIE_EE4B2_0", + "PCIE_TRNRDLLPDATA2", + "PCIE_WW4A2_18", + "PCIE_IMUX0_R_7", + "PCIE_SE4BEG0_16", + "PCIE_LH11_3", + "PCIE_LOGIC_OUTS_B3_R_3", + "PCIE_MIMRXRDATA17", + "PCIE_IMUX35_R_4", + "PCIE_CFGERRAERHEADERLOG57", + "PCIE_BLOCK_OUTS_B0_R_10", + "PCIE_EE4A1_5", + "PCIE_LOGIC_OUTS_B12_L_2", + "PCIE_IMUX38_R_2", + "PCIE_IMUX22_L_4", + "PCIE_BLOCK_OUTS_B3_L_10", + "PCIE_IMUX12_L_3", + "PCIE_IMUX4_R_1", + "PCIE_CTRL0_R_5", + "PCIE_IMUX2_R_1", + "PCIE_CLK0_R_3", + "PCIE_IMUX16_L_14", + "PCIE_FAN1_L_15", + "PCIE_LOGIC_OUTS_B0_L_7", + "PCIE_WW2END2_17", + "PCIE_ER1BEG1_6", + "PCIE_CLK0_R_9", + "PCIE_IMUX40_L_7", + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL2", + "PCIE_PIPERX4DATA6", + "PCIE_PIPERX4DATA0", + "PCIE_CLK0_R_18", + "PCIE_TRNRDLLPDATA4", + "PCIE_MIMRXRADDR9", + "PCIE_LOGIC_OUTS_B20_L_12", + "PCIE_LL2SENDENTERL1", + "PCIE_LOGIC_OUTS_B13_R_2", + "PCIE_WW2A0_0", + "PCIE_PIPERX3DATA12", + "PCIE_FAN3_R_11", + "PCIE_PIPETX5DATA6", + "PCIE_LOGIC_OUTS_B3_R_4", + "PCIE_NW4END0_19", + "PCIE_LOGIC_OUTS_B7_R_1", + "PCIE_IMUX24_R_1", + "PCIE_PIPERX7DATA13", + "PCIE_NW4A1_9", + "PCIE_IMUX6_R_6", + "PCIE_EE4BEG1_11", + "PCIE_IMUX32_R_12", + "PCIE_PIPERX5DATA12", + "PCIE_DBGVECB51", + "PCIE_IMUX34_R_10", + "PCIE_TRNRD45", + "PCIE_BYP6_L_0", + "PCIE_IMUX24_L_8", + "PCIE_IMUX0_R_0", + "PCIE_IMUX17_L_12", + "PCIE_IMUX19_R_12", + "PCIE_IMUX5_L_2", + "PCIE_DRPDO0", + "PCIE_FAN0_R_10", + "PCIE_LOGIC_OUTS_B11_L_9", + "PCIE_LOGIC_OUTS_B22_L_5", + "PCIE_MIMRXRDATA46", + "PCIE_EE4C2_18", + "PCIE_MIMRXRDATA53", + "PCIE_LOGIC_OUTS_B10_L_15", + "PCIE_TRNTDLLPDATA5", + "PCIE_DBGVECB16", + "PCIE_IMUX14_R_2", + "PCIE_LOGIC_OUTS_B3_R_2", + "PCIE_WW4B2_8", + "PCIE_TL2PPMSUSPENDOK", + "PCIE_PIPETX5DATA12", + "PCIE_MIMRXWDATA41", + "PCIE_IMUX14_R_3", + "PCIE_WW4B3_6", + "PCIE_CLK1_L_14", + "PCIE_ER1BEG1_5", + "PCIE_DBGVECB28", + "PCIE_IMUX12_L_6", + "PCIE_NE4C1_1", + "PCIE_IMUX37_R_4", + "PCIE_LOGIC_OUTS_B4_L_3", + "PCIE_TRNTDLLPDATA6", + "PCIE_MIMTXRDATA34", + "PCIE_EDTCONFIGURATION", + "PCIE_IMUX12_R_13", + "PCIE_LOGIC_OUTS_B12_L_10", + "PCIE_LOGIC_OUTS_B3_L_13", + "PCIE_MIMTXWDATA46", + "PCIE_FAN7_L_10", + "PCIE_LOGIC_OUTS_B18_R_15", + "PCIE_SW2A3_6", + "PCIE_PIPETX7DATA5", + "PCIE_SE4BEG1_17", + "PCIE_EE4B3_13", + "PCIE_IMUX26_R_11", + "PCIE_CFGMGMTDO3", + "PCIE_NE4BEG0_14", + "PCIE_TRNRD31", + "PCIE_SE4BEG0_1", + "PCIE_TRNRD55", + "PCIE_CLK1_L_12", + "PCIE_WR1END3_18", + "PCIE_IMUX13_L_16", + "PCIE_LOGIC_OUTS_B14_R_5", + "PCIE_DBGVECA59", + "PCIE_PIPETX2DATA12", + "PCIE_FAN0_R_7", + "PCIE_ER1BEG1_15", + "PCIE_IMUX33_R_16", + "PCIE_IMUX36_R_11", + "PCIE_SW4END2_16", + "PCIE_LL2TFCINIT2SEQ", + "PCIE_LOGIC_OUTS_B19_L_3", + "PCIE_SE2A0_1", + "PCIE_WW4A1_10", + "PCIE_IMUX8_R_1", + "PCIE_IMUX21_L_4", + "PCIE_SW4END0_7", + "PCIE_LOGIC_OUTS_B4_L_1", + "PCIE_SW4A0_9", + "PCIE_WW4END0_14", + "PCIE_SE4BEG0_10", + "PCIE_LOGIC_OUTS_B17_L_13", + "PCIE_FAN5_L_15", + "PCIE_EE4C0_4", + "PCIE_CFGDSN57", + "PCIE_IMUX8_L_12", + "PCIE_CFGMGMTDO28", + "PCIE_NE2A2_4", + "PCIE_BYP5_L_7", + "PCIE_DBGVECB48", + "PCIE_LOGIC_OUTS_B7_R_2", + "PCIE_IMUX7_L_12", + "PCIE_TRNTSRCDSC", + "PCIE_EE4BEG1_19", + "PCIE_BYP1_L_11", + "PCIE_SE4BEG1_1", + "PCIE_TL2ERRHDR41", + "PCIE_IMUX31_R_9", + "PCIE_SW4A2_14", + "PCIE_IMUX30_L_19", + "PCIE_SW2A1_12", + "PCIE_LOGIC_OUTS_B21_R_12", + "PCIE_CFGINTERRUPTMMENABLE2", + "PCIE_IMUX6_R_10", + "PCIE_CFGERRAERHEADERLOG8", + "PCIE_IMUX0_L_18", + "PCIE_IMUX47_L_18", + "PCIE_EE4A1_14", + "PCIE_CFGDEVCONTROLMAXREADREQ2", + "PCIE_LOGIC_OUTS_B5_R_14", + "PCIE_IMUX12_L_16", + "PCIE_BYP1_R_3", + "PCIE_EE2BEG3_7", + "PCIE_LOGIC_OUTS_B1_L_6", + "PCIE_SE4BEG3_11", + "PCIE_IMUX0_R_1", + "PCIE_WW2A3_19", + "PCIE_CFGERRAERHEADERLOG108", + "PCIE_IMUX45_L_8", + "PCIE_NE4C2_3", + "PCIE_NW4A0_1", + "PCIE_IMUX6_L_15", + "PCIE_TRNRDLLPDATA19", + "PCIE_SE4C2_3", + "PCIE_SW2A1_18", + "PCIE_EE4BEG0_0", + "PCIE_EE4BEG0_4", + "PCIE_MIMTXRDATA63", + "PCIE_IMUX28_R_7", + "PCIE_PIPETX2COMPLIANCE", + "PCIE_TRNTD40", + "PCIE_MIMTXRDATA33", + "PCIE_MIMTXWDATA25", + "PCIE_LH7_8", + "PCIE_BLOCK_OUTS_B0_R_0", + "PCIE_TRNFCCPLD11", + "PCIE_NW4END0_7", + "PCIE_LOGIC_OUTS_B13_L_5", + "PCIE_WR1END0_19", + "PCIE_IMUX11_R_0", + "PCIE_BYP1_L_14", + "PCIE_PMVDIVIDE1", + "PCIE_IMUX40_L_8", + "PCIE_FAN0_R_17", + "PCIE_LOGIC_OUTS_B7_L_12", + "PCIE_PIPETX5DATA10", + "PCIE_LOGIC_OUTS_B19_R_6", + "PCIE_BYP3_R_9", + "PCIE_SW4END0_10", + "PCIE_BYP5_L_5", + "PCIE_WW4END0_13", + "PCIE_IMUX22_R_0", + "PCIE_IMUX35_L_16", + "PCIE_NE4C2_12", + "PCIE_TRNTD48", + "PCIE_IMUX22_R_8", + "PCIE_NE4C3_14", + "PCIE_SE2A2_19", + "PCIE_NE4BEG1_5", + "PCIE_TRNTD1", + "PCIE_PIPETX1DATA12", + "PCIE_IMUX19_R_13", + "PCIE_EE4B0_3", + "PCIE_NE4C1_10", + "PCIE_SW4END0_2", + "PCIE_CLK1_L_1", + "PCIE_EE4A0_15", + "PCIE_WW4A2_17", + "PCIE_IMUX40_R_9", + "PCIE_IMUX34_L_9", + "PCIE_IMUX19_R_14", + "PCIE_EE4A3_2", + "PCIE_TL2ERRHDR1", + "PCIE_IMUX33_R_9", + "PCIE_PIPERX2DATA8", + "PCIE_LOGIC_OUTS_B6_R_10", + "PCIE_EDTCHANNELSIN7", + "PCIE_SE4BEG3_19", + "PCIE_LOGIC_OUTS_B2_R_5", + "PCIE_LH2_5", + "PCIE_CFGERRAERHEADERLOG127", + "PCIE_CFGERRAERHEADERLOG29", + "PCIE_IMUX7_L_7", + "PCIE_LH11_0", + "PCIE_NE2A2_14", + "PCIE_MIMRXRDATA27", + "PCIE_IMUX1_R_19", + "PCIE_WW4C3_10", + "PCIE_CFGINTERRUPTDI4", + "PCIE_LH12_2", + "PCIE_FAN6_R_18", + "PCIE_IMUX23_R_12", + "PCIE_EE2A1_15", + "PCIE_LOGIC_OUTS_B12_R_14", + "PCIE_PIPETX1DATA0", + "PCIE_MIMRXWADDR7", + "PCIE_LOGIC_OUTS_B6_R_19", + "PCIE_SW2A0_18", + "PCIE_SW2A3_15", + "PCIE_NE2A0_19", + "PCIE_LOGIC_OUTS_B11_L_17", + "PCIE_MIMTXWDATA27", + "PCIE_CFGMSGRECEIVEDASSERTINTC", + "PCIE_FAN0_R_2", + "PCIE_IMUX29_L_8", + "PCIE_MIMTXRDATA5", + "PCIE_IMUX17_R_3", + "PCIE_IMUX21_L_12", + "PCIE_EE4BEG3_15", + "PCIE_IMUX33_L_6", + "PCIE_MIMRXWDATA38", + "PCIE_TRNRD104", + "PCIE_TRNRDLLPDATA33", + "PCIE_PIPERX3DATA9", + "PCIE_IMUX26_L_15", + "PCIE_FAN0_L_2", + "PCIE_LOGIC_OUTS_B8_R_18", + "PCIE_SE4BEG1_6", + "PCIE_IMUX2_L_0", + "PCIE_TL2ERRHDR60", + "PCIE_WL1END0_10", + "PCIE_WL1END1_4", + "PCIE_IMUX1_L_15", + "PCIE_NW4A0_19", + "PCIE_IMUX46_R_9", + "PCIE_FAN0_L_16", + "PCIE_EE4B3_11", + "PCIE_PIPERX1ELECIDLE", + "PCIE_WR1END2_17", + "PCIE_BYP1_R_0", + "PCIE_LOGIC_OUTS_B15_L_7", + "PCIE_TRNTD30", + "PCIE_WL1END1_1", + "PCIE_CFGSUBSYSVENDID12", + "PCIE_WW2END2_14", + "PCIE_TRNTDLLPDATA10", + "PCIE_IMUX23_R_4", + "PCIE_SE4BEG1_4", + "PCIE_FAN7_L_6", + "PCIE_CFGMSGDATA11", + "PCIE_MONITOR_N_11", + "PCIE_LL2LINKSTATUS0", + "PCIE_FAN7_R_8", + "PCIE_IMUX35_L_4", + "PCIE_CMSTICKYRSTN", + "PCIE_LH9_15", + "PCIE_NE2A3_17", + "PCIE_IMUX22_L_3", + "PCIE_WW4A3_10", + "PCIE_CFGDSN7", + "PCIE_NE4BEG2_3", + "PCIE_TRNRD11", + "PCIE_IMUX39_L_9", + "PCIE_EE4B3_18", + "PCIE_BLOCK_OUTS_B2_R_1", + "PCIE_PIPETX4DATA8", + "PCIE_LOGIC_OUTS_B14_R_11", + "PCIE_BYP7_R_15", + "PCIE_IMUX11_R_13", + "PCIE_SW2A2_5", + "PCIE_CFGDSN40", + "PCIE_IMUX35_R_5", + "PCIE_TRNRDLLPDATA53", + "PCIE_PIPERX6ELECIDLE", + "PCIE_WW4B3_1", + "PCIE_WL1END2_12", + "PCIE_IMUX37_R_1", + "PCIE_NW4END1_8", + "PCIE_WW2END3_18", + "PCIE_SW4END3_16", + "PCIE_BYP2_R_7", + "PCIE_LOGIC_OUTS_B7_R_3", + "PCIE_IMUX21_L_8", + "PCIE_CFGERRTLPCPLHEADER31", + "PCIE_PIPERX3POLARITY", + "PCIE_CFGREVID7", + "PCIE_WW4C1_9", + "PCIE_PIPETX0DATA13", + "PCIE_WW4B1_7", + "PCIE_LOGIC_OUTS_B19_L_16", + "PCIE_FUNCLVLRSTN", + "PCIE_NE4BEG0_2", + "PCIE_IMUX14_L_4", + "PCIE_DRPADDR6", + "PCIE_LOGIC_OUTS_B9_L_13", + "PCIE_IMUX10_L_13", + "PCIE_CFGDEVCONTROLENABLERO", + "PCIE_LOGIC_OUTS_B21_R_3", + "PCIE_IMUX47_L_4", + "PCIE_IMUX0_L_17", + "PCIE_BLOCK_OUTS_B2_L_7", + "PCIE_LOGIC_OUTS_B18_R_7", + "PCIE_FAN2_L_15", + "PCIE_PIPERX1POLARITY", + "PCIE_IMUX23_R_18", + "PCIE_CFGLINKSTATUSLINKTRAINING", + "PCIE_IMUX36_L_15", + "PCIE_IMUX3_R_12", + "PCIE_PLLINKUPCFGCAP", + "PCIE_IMUX28_R_18", + "PCIE_MIMRXWDATA24", + "PCIE_LOGIC_OUTS_B10_L_2", + "PCIE_SE4C2_13", + "PCIE_WW4C3_6", + "PCIE_SE4BEG2_3", + "PCIE_EL1BEG1_10", + "PCIE_TRNRD94", + "PCIE_TRNTDLLPDATA22", + "PCIE_PIPERX5CHARISK1", + "PCIE_IMUX14_R_15", + "PCIE_LOGIC_OUTS_B16_R_17", + "PCIE_WR1END2_8", + "PCIE_EE4BEG0_10", + "PCIE_EDTCHANNELSOUT8", + "PCIE_IMUX9_R_8", + "PCIE_IMUX5_R_10", + "PCIE_ER1BEG1_10", + "PCIE_WR1END2_6", + "PCIE_CFGSUBSYSVENDID1", + "PCIE_BYP4_R_16", + "PCIE_IMUX17_R_8", + "PCIE_WW4A3_14", + "PCIE_IMUX12_R_0", + "PCIE_IMUX6_L_10", + "PCIE_IMUX33_R_12", + "PCIE_FAN1_L_7", + "PCIE_IMUX30_R_0", + "PCIE_LH5_3", + "PCIE_BLOCK_OUTS_B2_R_18", + "PCIE_EL1BEG0_13", + "PCIE_LOGIC_OUTS_B16_R_2", + "PCIE_WW4B0_18", + "PCIE_EL1BEG3_16", + "PCIE_CFGERRAERHEADERLOG5", + "PCIE_EE4BEG2_9", + "PCIE_MIMRXRADDR10", + "PCIE_IMUX46_R_10", + "PCIE_TRNRD7", + "PCIE_NW4END1_13", + "PCIE_EE4BEG2_7", + "PCIE_EE4A1_9", + "PCIE_IMUX19_R_1", + "PCIE_MIMTXRDATA47", + "PCIE_SE4C2_0", + "PCIE_IMUX31_L_5", + "PCIE_SW2A1_5", + "PCIE_WW4B0_0", + "PCIE_LOGIC_OUTS_B14_R_8", + "PCIE_MIMTXRDATA68", + "PCIE_SE2A0_3", + "PCIE_PIPETX0DATA14", + "PCIE_MONITOR_P_14", + "PCIE_CFGVENDID12", + "PCIE_IMUX19_L_12", + "PCIE_MIMRXRADDR6", + "PCIE_CFGMGMTDO4", + "PCIE_CFGERRAERHEADERLOG25", + "PCIE_LH12_10", + "PCIE_MIMRXWDATA29", + "PCIE_MIMRXRDATA47", + "PCIE_LOGIC_OUTS_B0_L_15", + "PCIE_FAN7_R_12", + "PCIE_NE4C1_16", + "PCIE_TRNTD9", + "PCIE_CFGERRTLPCPLHEADER38", + "PCIE_TL2ERRHDR44", + "PCIE_LOGIC_OUTS_B7_R_10", + "PCIE_TRNTD69", + "PCIE_EE2BEG3_6", + "PCIE_NW2A1_13", + "PCIE_NW4END2_3", + "PCIE_MIMRXRDATA31", + "PCIE_LH12_4", + "PCIE_DRPDI10", + "PCIE_FAN4_L_3", + "PCIE_CTRL0_L_16", + "PCIE_NW4END0_17", + "PCIE_LOGIC_OUTS_B23_L_11", + "PCIE_LH3_13", + "PCIE_IMUX10_L_16", + "PCIE_MIMTXRDATA64", + "PCIE_EE4B0_6", + "PCIE_DRPRDY", + "PCIE_BLOCK_OUTS_B3_L_8", + "PCIE_IMUX26_L_5", + "PCIE_IMUX39_L_3", + "PCIE_FAN6_R_6", + "PCIE_LOGIC_OUTS_B2_L_19", + "PCIE_MIMRXWDATA31", + "PCIE_IMUX15_L_8", + "PCIE_CFGDEVCONTROL2IDOREQEN", + "PCIE_TRNFCPD10", + "PCIE_TRNRBARHIT4", + "PCIE_DBGVECB24", + "PCIE_PIPETX1CHARISK0", + "PCIE_TRNTD8", + "PCIE_PIPERX3DATA0", + "PCIE_WW2A1_12", + "PCIE_EE2A1_8", + "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3", + "PCIE_CFGERRTLPCPLHEADER15", + "PCIE_BLOCK_OUTS_B0_L_8", + "PCIE_BYP7_L_7", + "PCIE_LH10_9", + "PCIE_FAN2_R_6", + "PCIE_PIPERX1DATA3", + "PCIE_WR1END3_16", + "PCIE_WW2END3_7", + "PCIE_TRNRD83", + "PCIE_WW4A0_13", + "PCIE_LOGIC_OUTS_B14_R_12", + "PCIE_CFGERRTLPCPLHEADER37", + "PCIE_IMUX18_R_14", + "PCIE_LH7_16", + "PCIE_IMUX38_L_13", + "PCIE_IMUX18_R_5", + "PCIE_LOGIC_OUTS_B0_L_4", + "PCIE_SW4END1_13", + "PCIE_IMUX25_L_1", + "PCIE_SW2A3_5", + "PCIE_BYP3_R_4", + "PCIE_IMUX5_R_7", + "PCIE_PIPERX1CHANISALIGNED", + "PCIE_MIMRXWDATA63", + "PCIE_WW2END0_18", + "PCIE_CFGERRURN", + "PCIE_IMUX47_L_19", + "PCIE_LOGIC_OUTS_B11_L_2", + "PCIE_IMUX15_R_18", + "PCIE_TRNRFCPRET", + "PCIE_MIMRXWDATA34", + "PCIE_SW4A1_10", + "PCIE_CFGVCTCVCMAP2", + "PCIE_CFGSUBSYSVENDID4", + "PCIE_BYP7_R_13", + "PCIE_SW2A0_16", + "PCIE_CFGERRAERHEADERLOG45", + "PCIE_TRNRDLLPDATA60", + "PCIE_IMUX35_L_11", + "PCIE_IMUX38_L_17", + "PCIE_TRNLNKUP", + "PCIE_MIMTXWDATA12", + "PCIE_LOGIC_OUTS_B23_L_1", + "PCIE_ER1BEG1_9", + "PCIE_SE4C3_16", + "PCIE_IMUX21_L_9", + "PCIE_TRNTBUFAV1", + "PCIE_FAN2_R_0", + "PCIE_MIMTXRDATA12", + "PCIE_SW2A3_9", + "PCIE_IMUX47_L_11", + "PCIE_SW4A0_18", + "PCIE_IMUX0_R_13", + "PCIE_EE4A2_16", + "PCIE_DBGVECB18", + "PCIE_LOGIC_OUTS_B22_R_10", + "PCIE_MIMRXWDATA47", + "PCIE_PIPETX6CHARISK1", + "PCIE_LOGIC_OUTS_B1_R_16", + "PCIE_IMUX16_L_8", + "PCIE_WR1END0_10", + "PCIE_BLOCK_OUTS_B3_L_18", + "PCIE_CTRL1_R_17", + "PCIE_LH2_13", + "PCIE_SW2A0_15", + "PCIE_WW4B0_6", + "PCIE_IMUX42_L_14", + "PCIE_LH6_14", + "PCIE_WW4B0_15", + "PCIE_EE2A1_3", + "PCIE_LOGIC_OUTS_B1_L_2", + "PCIE_MIMRXRDATA49", + "PCIE_IMUX42_R_6", + "PCIE_IMUX20_R_2", + "PCIE_IMUX10_R_19", + "PCIE_MIMTXRDATA65", + "PCIE_TRNTD12", + "PCIE_LOGIC_OUTS_B16_R_5", + "PCIE_CFGINTERRUPTMSIXFM", + "PCIE_DRPDI4", + "PCIE_SW4END1_1", + "PCIE_BLOCK_OUTS_B2_R_11", + "PCIE_IMUX4_R_19", + "PCIE_IMUX13_L_14", + "PCIE_FAN0_R_0", + "PCIE_EE4A1_6", + "PCIE_NE2A0_12", + "PCIE_BYP3_L_16", + "PCIE_NW4A1_16", + "PCIE_EE4B0_5", + "PCIE_LH7_0", + "PCIE_EE4A3_16", + "PCIE_WW4A2_16", + "PCIE_NW2A0_7", + "PCIE_WW2END0_2", + "PCIE_LOGIC_OUTS_B9_L_19", + "PCIE_MIMRXRDATA35", + "PCIE_TRNTD35", + "PCIE_EE4C1_16", + "PCIE_PIPERX0DATA15", + "PCIE_PIPERX7DATA2", + "PCIE_CTRL0_L_14", + "PCIE_LH8_7", + "PCIE_EE2A1_4", + "PCIE_SW4A0_0", + "PCIE_LOGIC_OUTS_B15_L_1", + "PCIE_FAN7_R_17", + "PCIE_BLOCK_OUTS_B3_R_7", + "PCIE_TRNTDLLPDATA16", + "PCIE_MIMTXWDATA7", + "PCIE_SE2A1_4", + "PCIE_WW2A2_5", + "PCIE_NW4END2_4", + "PCIE_SW4END3_10", + "PCIE_IMUX41_R_1", + "PCIE_LOGIC_OUTS_B12_R_11", + "PCIE_LH2_11", + "PCIE_MIMRXRADDR12", + "PCIE_LOGIC_OUTS_B19_R_19", + "PCIE_XILUNCONNOUT24", + "PCIE_DBGVECA0", + "PCIE_IMUX47_R_11", + "PCIE_SW4END3_0", + "PCIE_TRNRBARHIT3", + "PCIE_BLOCK_OUTS_B1_R_7", + "PCIE_BYP7_R_9", + "PCIE_CTRL1_R_15", + "PCIE_NE4C0_2", + "PCIE_CFGTRANSACTIONADDR4", + "PCIE_TRNRDLLPDATA63", + "PCIE_TRNFCNPD11", + "PCIE_CFGERRAERHEADERLOG43", + "PCIE_LOGIC_OUTS_B12_R_10", + "PCIE_IMUX6_L_7", + "PCIE_BYP7_L_6", + "PCIE_TRNRD58", + "PCIE_IMUX29_R_1", + "PCIE_PIPERX3DATA3", + "PCIE_WR1END1_1", + "PCIE_TRNRD68", + "PCIE_LOGIC_OUTS_B22_R_7", + "PCIE_NE4C1_9", + "PCIE_CFGINTERRUPTSTATN", + "PCIE_SE4C0_3", + "PCIE_LOGIC_OUTS_B13_R_5", + "PCIE_EE4C0_0", + "PCIE_IMUX33_R_7", + "PCIE_EE4BEG3_11", + "PCIE_IMUX27_R_14", + "PCIE_IMUX34_R_8", + "PCIE_CFGPMCSRPMEEN", + "PCIE_IMUX0_L_13", + "PCIE_IMUX12_L_15", + "PCIE_CFGDEVID4", + "PCIE_SW4END2_12", + "PCIE_MIMRXRADDR2", + "PCIE_LOGIC_OUTS_B21_R_18", + "PCIE_MIMTXWADDR7", + "PCIE_IMUX8_L_0", + "PCIE_NE4BEG3_1", + "PCIE_CFGERRCPLRDYN", + "PCIE_LOGIC_OUTS_B6_L_0", + "PCIE_IMUX0_R_6", + "PCIE_PIPERX4VALID", + "PCIE_IMUX31_L_9", + "PCIE_IMUX33_L_5", + "PCIE_IMUX35_L_13", + "PCIE_IMUX35_R_12", + "PCIE_ER1BEG1_4", + "PCIE_EE2A0_12", + "PCIE_NW2A3_12", + "PCIE_CFGVENDID1", + "PCIE_IMUX45_R_4", + "PCIE_TRNRD6", + "PCIE_NW4A2_19", + "PCIE_SE4BEG0_14", + "PCIE_IMUX22_L_15", + "PCIE_FAN0_R_14", + "PCIE_MIMRXWDATA45", + "PCIE_WW4C1_17", + "PCIE_PIPETX2ELECIDLE", + "PCIE_CFGDEVSTATUSNONFATALERRDETECTED", + "PCIE_PLDBGVEC5", + "PCIE_IMUX2_R_3", + "PCIE_LOGIC_OUTS_B22_R_14", + "PCIE_FAN2_R_16", + "PCIE_DBGVECB42", + "PCIE_IMUX32_L_12", + "PCIE_CFGERRTLPCPLHEADER13", + "PCIE_BYP5_L_8", + "PCIE_IMUX38_R_18", + "PCIE_SE4BEG1_0", + "PCIE_IMUX29_L_19", + "PCIE_IMUX38_R_8", + "PCIE_LOGIC_OUTS_B10_R_11", + "PCIE_TRNRD12", + "PCIE_LOGIC_OUTS_B6_L_8", + "PCIE_CTRL0_R_9", + "PCIE_EE4C1_6", + "PCIE_FAN1_L_18", + "PCIE_NW2A1_3", + "PCIE_CFGDEVID0", + "PCIE_IMUX7_L_8", + "PCIE_DRPDO5", + "PCIE_PIPETX6DATA13", + "PCIE_IMUX27_R_6", + "PCIE_NW4A2_7", + "PCIE_LOGIC_OUTS_B19_R_18", + "PCIE_LH3_14", + "PCIE_NW4END1_17", + "PCIE_TRNTEOF", + "PCIE_WW2A3_16", + "PCIE_SE4BEG0_17", + "PCIE_IMUX13_R_16", + "PCIE_TRNFCSEL0", + "PCIE_SW2A2_6", + "PCIE_NE4BEG2_2", + "PCIE_BYP3_R_12", + "PCIE_SW4A1_16", + "PCIE_IMUX5_R_5", + "PCIE_EE2A2_18", + "PCIE_EL1BEG0_11", + "PCIE_CTRL1_R_12", + "PCIE_IMUX34_R_6", + "PCIE_IMUX9_R_0", + "PCIE_SW4A3_19", + "PCIE_EE4A3_11", + "PCIE_WR1END3_8", + "PCIE_IMUX15_L_2", + "PCIE_IMUX36_L_3", + "PCIE_IMUX47_L_10", + "PCIE_IMUX38_R_6", + "PCIE_TL2ERRHDR63", + "PCIE_IMUX15_L_0", + "PCIE_ER1BEG2_1", + "PCIE_NE2A2_15", + "PCIE_IMUX47_L_16", + "PCIE_IMUX8_R_19", + "PCIE_CFGDSN8", + "PCIE_LOGIC_OUTS_B9_L_4", + "PCIE_LOGIC_OUTS_B21_L_9", + "PCIE_LOGIC_OUTS_B4_R_18", + "PCIE_IMUX21_R_8", + "PCIE_USERCLK2", + "PCIE_WW2END3_8", + "PCIE_TRNRECRCERR", + "PCIE_ER1BEG1_12", + "PCIE_LOGIC_OUTS_B15_L_13", + "PCIE_NE4BEG0_12", + "PCIE_CTRL1_L_1", + "PCIE_LL2SUSPENDOK", + "PCIE_BYP4_L_6", + "PCIE_IMUX33_L_0", + "PCIE_IMUX3_L_17", + "PCIE_IMUX41_L_4", + "PCIE_TRNRD48", + "PCIE_IMUX7_L_15", + "PCIE_CFGERRAERHEADERLOG1", + "PCIE_LOGIC_OUTS_B0_L_6", + "PCIE_NE4BEG1_8", + "PCIE_CFGERRAERHEADERLOG69", + "PCIE_IMUX25_R_19", + "PCIE_SW4A2_9", + "PCIE_PIPETX1POWERDOWN0", + "PCIE_CFGERRAERHEADERLOG27", + "PCIE_BYP7_L_5", + "PCIE_TRNRD125", + "PCIE_ER1BEG2_2", + "PCIE_MIMTXWDATA2", + "PCIE_PIPETX4POWERDOWN0", + "PCIE_FAN4_L_1", + "PCIE_LOGIC_OUTS_B16_R_14", + "PCIE_IMUX35_L_14", + "PCIE_LOGIC_OUTS_B17_L_5", + "PCIE_FAN3_L_12", + "PCIE_BYP7_R_0", + "PCIE_TRNTD5", + "PCIE_WW2END1_16", + "PCIE_IMUX1_L_12", + "PCIE_SW4END0_1", + "PCIE_EE4B0_17", + "PCIE_CLK1_L_17", + "PCIE_NW2A2_10", + "PCIE_PIPERX5DATA6", + "PCIE_IMUX17_R_0", + "PCIE_BYP7_L_2", + "PCIE_IMUX45_L_10", + "PCIE_SW4A1_18", + "PCIE_DBGSCLRB", + "PCIE_LOGIC_OUTS_B15_R_16", + "PCIE_IMUX12_R_6", + "PCIE_EE4A3_14", + "PCIE_CFGLINKCONTROLAUTOBANDWIDTHINTEN", + "PCIE_WW4C2_13", + "PCIE_WW4C2_1", + "PCIE_FAN7_R_10", + "PCIE_IMUX38_R_11", + "PCIE_IMUX27_R_16", + "PCIE_LOGIC_OUTS_B10_R_4", + "PCIE_EE2BEG2_6", + "PCIE_BYP0_R_1", + "PCIE_IMUX35_R_17", + "PCIE_IMUX24_R_12", + "PCIE_SW4END1_19", + "PCIE_IMUX20_L_4", + "PCIE_IMUX28_L_9", + "PCIE_BYP2_L_3", + "PCIE_NE2A3_9", + "PCIE_CFGERRAERHEADERLOG28", + "PCIE_CFGERRTLPCPLHEADER46", + "PCIE_NE4BEG2_19", + "PCIE_CFGMSGRECEIVEDPMPME", + "PCIE_EE4C1_13", + "PCIE_LOGIC_OUTS_B4_R_0", + "PCIE_IMUX21_R_10", + "PCIE_PIPERX3DATA5", + "PCIE_IMUX3_R_16", + "PCIE_TRNFCPH5", + "PCIE_NW2A1_14", + "PCIE_TRNTDLLPDATA0", + "PCIE_CFGERRAERHEADERLOG126", + "PCIE_TRNRD23", + "PCIE_DRPDI1", + "PCIE_LOGIC_OUTS_B10_L_12", + "PCIE_IMUX43_L_6", + "PCIE_TRNRDLLPDATA56", + "PCIE_WW4B0_5", + "PCIE_IMUX17_L_3", + "PCIE_NW2A0_8", + "PCIE_IMUX41_R_17", + "PCIE_WR1END2_9", + "PCIE_IMUX5_L_7", + "PCIE_MIMRXRDATA19", + "PCIE_BYP5_L_0", + "PCIE_IMUX45_R_10", + "PCIE_NE4BEG2_17", + "PCIE_LOGIC_OUTS_B9_R_10", + "PCIE_IMUX17_L_18", + "PCIE_PIPETX4CHARISK0", + "PCIE_LH7_9", + "PCIE_IMUX24_R_11", + "PCIE_SE4C0_13", + "PCIE_NW4END0_11", + "PCIE_ER1BEG2_0", + "PCIE_LOGIC_OUTS_B20_L_3", + "PCIE_BYP5_R_0", + "PCIE_LH8_15", + "PCIE_DBGVECB46", + "PCIE_LOGIC_OUTS_B17_R_6", + "PCIE_TRNRD51", + "PCIE_EE4A0_9", + "PCIE_PIPERX1DATA6", + "PCIE_IMUX2_L_13", + "PCIE_IMUX44_R_2", + "PCIE_IMUX25_R_15", + "PCIE_CFGMGMTDI21", + "PCIE_SW4A3_8", + "PCIE_IMUX4_R_12", + "PCIE_LOGIC_OUTS_B3_R_0", + "PCIE_IMUX10_L_12", + "PCIE_IMUX30_L_18", + "PCIE_NE2A1_11", + "PCIE_LOGIC_OUTS_B17_R_15", + "PCIE_SE4BEG2_0", + "PCIE_IMUX28_R_5", + "PCIE_EE4A1_17", + "PCIE_WW2END1_2", + "PCIE_IMUX20_R_0", + "PCIE_LOGIC_OUTS_B22_L_10", + "PCIE_TL2ERRHDR10", + "PCIE_WW4A2_0", + "PCIE_LOGIC_OUTS_B4_R_8", + "PCIE_LOGIC_OUTS_B18_R_13", + "PCIE_SW4A2_15", + "PCIE_WW2A1_3", + "PCIE_TRNRD95", + "PCIE_IMUX4_L_3", + "PCIE_FAN0_L_19", + "PCIE_NW2A3_0", + "PCIE_EDTCLK", + "PCIE_WW4END3_2", + "PCIE_IMUX45_L_13", + "PCIE_BYP2_L_18", + "PCIE_NE4BEG1_9", + "PCIE_WW4END1_18", + "PCIE_DBGSCLRE", + "PCIE_FAN1_L_11", + "PCIE_BLOCK_OUTS_B1_L_2", + "PCIE_SE4C1_7", + "PCIE_DBGVECA45", + "PCIE_TRNRDLLPDATA32", + "PCIE_PIPETX1COMPLIANCE", + "PCIE_CFGERRAERHEADERLOG26", + "PCIE_PIPETX2DATA8", + "PCIE_LOGIC_OUTS_B13_L_8", + "PCIE_EE4BEG3_8", + "PCIE_DBGVECA26", + "PCIE_WW4END3_7", + "PCIE_IMUX41_R_8", + "PCIE_NE4BEG2_5", + "PCIE_FAN0_R_3", + "PCIE_SE4C1_3", + "PCIE_IMUX9_L_11", + "PCIE_CFGAERROOTERRNONFATALERRRECEIVED", + "PCIE_LOGIC_OUTS_B18_L_16", + "PCIE_TRNTD72", + "PCIE_IMUX12_R_15", + "PCIE_BLOCK_OUTS_B1_L_18", + "PCIE_MIMTXRDATA48", + "PCIE_IMUX39_L_13", + "PCIE_IMUX19_R_8", + "PCIE_LOGIC_OUTS_B13_L_12", + "PCIE_LOGIC_OUTS_B14_R_9", + "PCIE_SE2A1_9", + "PCIE_IMUX19_L_7", + "PCIE_PL2DIRECTEDLSTATE0", + "PCIE_IMUX28_L_5", + "PCIE_NW4END3_7", + "PCIE_PIPERX7DATA12", + "PCIE_LOGIC_OUTS_B13_R_19", + "PCIE_LOGIC_OUTS_B0_L_5", + "PCIE_LOGIC_OUTS_B3_L_11", + "PCIE_SW2A3_10", + "PCIE_LH6_9", + "PCIE_WW2END2_11", + "PCIE_BLOCK_OUTS_B0_L_3", + "PCIE_IMUX33_R_8", + "PCIE_WW4END2_3", + "PCIE_WW4A2_12", + "PCIE_PL2RXPMSTATE1", + "PCIE_WW2END1_4", + "PCIE_EE4BEG1_10", + "PCIE_MIMTXWDATA21", + "PCIE_IMUX1_L_2", + "PCIE_LOGIC_OUTS_B4_L_19", + "PCIE_NW4END1_6", + "PCIE_CFGERRAERHEADERLOG65", + "PCIE_CTRL1_R_10", + "PCIE_CLK1_R_18", + "PCIE_IMUX25_R_14", + "PCIE_LOGIC_OUTS_B12_L_19", + "PCIE_NE4BEG3_10", + "PCIE_FAN5_R_4", + "PCIE_TRNRBARHIT2", + "PCIE_BYP1_R_10", + "PCIE_IMUX34_R_5", + "PCIE_LOGIC_OUTS_B12_L_13", + "PCIE_NE4C0_8", + "PCIE_TRNRD44", + "PCIE_EE2BEG1_5", + "PCIE_LH1_19", + "PCIE_TRNTREM1", + "PCIE_SCANMODEN", + "PCIE_WW4B3_16", + "PCIE_IMUX1_L_8", + "PCIE_BYP1_L_18", + "PCIE_IMUX11_R_2", + "PCIE_IMUX41_R_13", + "PCIE_SW4END0_11", + "PCIE_TRNTD46", + "PCIE_SE4BEG0_13", + "PCIE_PIPETX7DATA8", + "PCIE_SW4A2_12", + "PCIE_NE4BEG3_0", + "PCIE_IMUX4_L_5", + "PCIE_LOGIC_OUTS_B12_L_8", + "PCIE_IMUX2_R_10", + "PCIE_DBGVECC5", + "PCIE_EE4B2_8", + "PCIE_WR1END2_16", + "PCIE_USERCLKPREBUFEN", + "PCIE_NW4A3_13", + "PCIE_FAN7_L_14", + "PCIE_FAN4_R_4", + "PCIE_SW2A0_14", + "PCIE_CFGDSN54", + "PCIE_CFGERRAERHEADERLOG96", + "PCIE_PIPERX1DATA0", + "PCIE_WW4B2_6", + "PCIE_DRPDI2", + "PCIE_IMUX22_R_5", + "PCIE_LOGIC_OUTS_B20_R_16", + "PCIE_CFGPCIELINKSTATE0", + "PCIE_IMUX41_R_4", + "PCIE_LOGIC_OUTS_B5_R_7", + "PCIE_WW2A0_16", + "PCIE_SE2A1_0", + "PCIE_IMUX1_R_2", + "PCIE_IMUX14_L_11", + "PCIE_IMUX17_L_10", + "PCIE_BYP2_R_9", + "PCIE_PIPETX0POWERDOWN1", + "PCIE_NW2A2_14", + "PCIE_IMUX13_R_13", + "PCIE_IMUX8_R_7", + "PCIE_IMUX23_L_5", + "PCIE_BLOCK_OUTS_B0_R_4", + "PCIE_EE2BEG2_11", + "PCIE_BYP0_R_17", + "PCIE_WW4END0_5", + "PCIE_SW4A1_5", + "PCIE_TRNRD60", + "PCIE_CFGDSBUSNUMBER5", + "PCIE_EL1BEG1_0", + "PCIE_NE4BEG2_10", + "PCIE_LH8_9", + "PCIE_CFGDEVCONTROLNOSNOOPEN", + "PCIE_SW4A0_12", + "PCIE_LL2BADDLLPERR", + "PCIE_IMUX9_R_7", + "PCIE_TRNRD59", + "PCIE_CFGERRAERHEADERLOG20", + "PCIE_IMUX7_L_13", + "PCIE_IMUX31_L_2", + "PCIE_SE4BEG1_5", + "PCIE_WW4C3_15", + "PCIE_WW2END3_13", + "PCIE_PIPERX6DATA6", + "PCIE_LOGIC_OUTS_B9_L_8", + "PCIE_EE4BEG2_2", + "PCIE_NW2A0_6", + "PCIE_LOGIC_OUTS_B10_R_3", + "PCIE_WR1END1_0", + "PCIE_MONITOR_P_10", + "PCIE_BLOCK_OUTS_B0_L_11", + "PCIE_TRNTD51", + "PCIE_IMUX31_R_4", + "PCIE_LOGIC_OUTS_B12_L_15", + "PCIE_CTRL0_R_3", + "PCIE_IMUX37_R_16", + "PCIE_DBGVECA14", + "PCIE_CTRL0_L_6", + "PCIE_EE4A2_4", + "PCIE_NE4C3_13", + "PCIE_NW4A3_4", + "PCIE_WW4A2_2", + "PCIE_MIMTXWDATA55", + "PCIE_SW4END2_11", + "PCIE_MONITOR_N_7", + "PCIE_LH8_8", + "PCIE_CFGERRAERHEADERLOG99", + "PCIE_CFGMGMTDI2", + "PCIE_LH6_1", + "PCIE_IMUX17_R_15", + "PCIE_IMUX24_L_14", + "PCIE_WW2A1_8", + "PCIE_IMUX32_R_3", + "PCIE_IMUX23_L_8", + "PCIE_SW4END0_0", + "PCIE_TRNTD93", + "PCIE_IMUX37_R_9", + "PCIE_FAN7_R_3", + "PCIE_MIMRXRDATA39", + "PCIE_MIMTXWDATA34", + "PCIE_SW2A1_9", + "PCIE_WW4A2_6", + "PCIE_IMUX32_R_10", + "PCIE_SE2A3_17", + "PCIE_WW2A1_19", + "PCIE_IMUX16_L_16", + "PCIE_EE2A2_4", + "PCIE_LOGIC_OUTS_B2_R_1", + "PCIE_IMUX31_L_10", + "PCIE_IMUX26_R_6", + "PCIE_EE4B2_3", + "PCIE_LH6_18", + "PCIE_BYP0_R_15", + "PCIE_BYP1_L_0", + "PCIE_EDTCHANNELSOUT3", + "PCIE_TRNTD116", + "PCIE_LH4_18", + "PCIE_WW4C2_0", + "PCIE_TRNFCCPLD7", + "PCIE_PIPERX5CHANISALIGNED", + "PCIE_BYP6_L_11", + "PCIE_CFGAERINTERRUPTMSGNUM1", + "PCIE_IMUX5_R_4", + "PCIE_FAN0_R_8", + "PCIE_SE4BEG0_3", + "PCIE_DBGVECC9", + "PCIE_EE2A3_9", + "PCIE_IMUX4_L_8", + "PCIE_TRNRD116", + "PCIE_TRNRD1", + "PCIE_EL1BEG1_7", + "PCIE_NE4C1_0", + "PCIE_LOGIC_OUTS_B2_R_2", + "PCIE_TRNFCPD6", + "PCIE_DBGVECB22", + "PCIE_IMUX35_R_10", + "PCIE_CFGMGMTDWADDR0", + "PCIE_WW4C1_5", + "PCIE_BLOCK_OUTS_B0_R_1", + "PCIE_MIMTXRADDR10", + "PCIE_CFGVCTCVCMAP6", + "PCIE_WW2END1_1", + "PCIE_CFGMGMTDI6", + "PCIE_IMUX13_R_10", + "PCIE_IMUX16_L_1", + "PCIE_IMUX33_R_13", + "PCIE_LOGIC_OUTS_B0_R_2", + "PCIE_ER1BEG1_17", + "PCIE_LOGIC_OUTS_B17_R_11", + "PCIE_PIPERX7STATUS1", + "PCIE_TRNFCNPH7", + "PCIE_CFGMSGDATA4", + "PCIE_EE4BEG0_13", + "PCIE_NW2A2_1", + "PCIE_CFGMGMTDO12", + "PCIE_LH2_4", + "PCIE_IMUX17_L_9", + "PCIE_PLDIRECTEDLINKWIDTH1", + "PCIE_CFGMSGRECEIVEDPMASNAK", + "PCIE_SE4C3_4", + "PCIE_WW4END0_16", + "PCIE_LH1_6", + "PCIE_MIMTXRDATA6", + "PCIE_TRNTBUFAV3", + "PCIE_PIPETX7DATA11", + "PCIE_IMUX45_R_9", + "PCIE_EE4B0_11", + "PCIE_NE4BEG2_13", + "PCIE_NW4END3_13", + "PCIE_FAN3_L_3", + "PCIE_BYP5_L_11", + "PCIE_IMUX38_R_1", + "PCIE_SE4BEG0_0", + "PCIE_SE4BEG2_7", + "PCIE_CFGERRTLPCPLHEADER8", + "PCIE_SW4A2_2", + "PCIE_WL1END3_3", + "PCIE_PIPERX1DATA10", + "PCIE_PIPERX4STATUS2", + "PCIE_LOGIC_OUTS_B6_L_2", + "PCIE_IMUX42_R_3", + "PCIE_NE4BEG2_14", + "PCIE_BYP6_R_11", + "PCIE_WW2A3_12", + "PCIE_EE4B3_5", + "PCIE_IMUX8_L_5", + "PCIE_IMUX39_L_6", + "PCIE_LOGIC_OUTS_B2_L_18", + "PCIE_SE4C3_7", + "PCIE_IMUX25_L_16", + "PCIE_WL1END2_16", + "PCIE_SE4C1_13", + "PCIE_BYP3_L_10", + "PCIE_WW4END3_1", + "PCIE_IMUX10_L_1", + "PCIE_SE4C3_3", + "PCIE_SW2A0_1", + "PCIE_SW2A2_10", + "PCIE_BYP6_R_12", + "PCIE_IMUX23_L_0", + "PCIE_IMUX22_L_18", + "PCIE_IMUX35_R_1", + "PCIE_IMUX3_R_15", + "PCIE_IMUX5_R_19", + "PCIE_NW4END1_15", + "PCIE_LOGIC_OUTS_B17_L_19", + "PCIE_WW2A2_9", + "PCIE_IMUX47_L_0", + "PCIE_LOGIC_OUTS_B20_L_5", + "PCIE_CFGMSGRECEIVEDERRCOR", + "PCIE_IMUX18_L_1", + "PCIE_IMUX18_L_7", + "PCIE_LOGIC_OUTS_B4_L_16", + "PCIE_CFGDSN36", + "PCIE_SE4C0_0", + "PCIE_EL1BEG2_19", + "PCIE_LOGIC_OUTS_B0_R_14", + "PCIE_IMUX28_L_6", + "PCIE_IMUX44_R_16", + "PCIE_IMUX11_L_15", + "PCIE_IMUX28_R_11", + "PCIE_LOGIC_OUTS_B14_L_18", + "PCIE_LH5_1", + "PCIE_NW2A2_7", + "PCIE_CFGERRAERHEADERLOG110", + "PCIE_SE2A2_8", + "PCIE_XILUNCONNOUT5", + "PCIE_ER1BEG0_18", + "PCIE_LOGIC_OUTS_B14_R_10", + "PCIE_CFGPCIECAPINTERRUPTMSGNUM4", + "PCIE_EE4A3_4", + "PCIE_WL1END1_3", + "PCIE_IMUX17_R_2", + "PCIE_MIMTXWADDR5", + "PCIE_CTRL1_R_16", + "PCIE_WW4END0_6", + "PCIE_NE4C0_7", + "PCIE_IMUX47_L_8", + "PCIE_IMUX32_R_11", + "PCIE_PIPERX2DATA15", + "PCIE_IMUX11_L_18", + "PCIE_BYP5_R_7", + "PCIE_IMUX4_R_0", + "PCIE_SW4A0_2", + "PCIE_EE2BEG1_10", + "PCIE_BYP2_R_19", + "PCIE_PIPERX4STATUS1", + "PCIE_EE4B1_9", + "PCIE_LOGIC_OUTS_B1_L_3", + "PCIE_WW4A0_14", + "PCIE_IMUX18_L_15", + "PCIE_FAN6_R_5", + "PCIE_EE4C1_10", + "PCIE_IMUX14_R_14", + "PCIE_IMUX2_R_8", + "PCIE_PIPERX5CHARISK0", + "PCIE_IMUX0_L_19", + "PCIE_NW2A0_3", + "PCIE_WR1END1_10", + "PCIE_FAN5_R_6", + "PCIE_DBGVECA52", + "PCIE_PIPERX5ELECIDLE", + "PCIE_LL2SENDASREQL1", + "PCIE_LOGIC_OUTS_B16_R_15", + "PCIE_IMUX6_R_4", + "PCIE_IMUX16_R_15", + "PCIE_LOGIC_OUTS_B20_R_9", + "PCIE_WW2END2_7", + "PCIE_FAN6_L_7", + "PCIE_NW4END3_16", + "PCIE_IMUX2_R_19", + "PCIE_DRPDI6", + "PCIE_IMUX3_R_18", + "PCIE_BLOCK_OUTS_B3_L_13", + "PCIE_IMUX38_R_14", + "PCIE_TRNRDLLPDATA14", + "PCIE_FAN3_R_2", + "PCIE_WW4C1_4", + "PCIE_LOGIC_OUTS_B10_R_2", + "PCIE_EL1BEG3_12", + "PCIE_IMUX22_R_11", + "PCIE_LOGIC_OUTS_B18_L_9", + "PCIE_IMUX3_R_0", + "PCIE_DBGVECA16", + "PCIE_LOGIC_OUTS_B8_L_7", + "PCIE_TL2ERRHDR29", + "PCIE_NW4A0_16", + "PCIE_SW2A0_5", + "PCIE_BYP0_L_12", + "PCIE_WW4C2_7", + "PCIE_CFGDSN50", + "PCIE_NE4C2_0", + "PCIE_BLOCK_OUTS_B0_L_6", + "PCIE_NW4END1_7", + "PCIE_BLOCK_OUTS_B0_R_9", + "PCIE_LOGIC_OUTS_B20_L_8", + "PCIE_FAN1_R_5", + "PCIE_TRNRDLLPSRCRDY1", + "PCIE_IMUX4_L_4", + "PCIE_IMUX13_R_1", + "PCIE_WW2END2_19", + "PCIE_NW2A3_5", + "PCIE_WR1END2_7", + "PCIE_BYP6_R_0", + "PCIE_IMUX8_R_3", + "PCIE_IMUX23_R_0", + "PCIE_LOGIC_OUTS_B10_R_12", + "PCIE_TRNRD4", + "PCIE_CFGPMCSRPOWERSTATE0", + "PCIE_PIPERX6STATUS1", + "PCIE_LOGIC_OUTS_B19_R_12", + "PCIE_IMUX17_R_14", + "PCIE_IMUX23_R_17", + "PCIE_LOGIC_OUTS_B18_R_4", + "PCIE_IMUX27_L_14", + "PCIE_CFGDEVID12", + "PCIE_LOGIC_OUTS_B14_R_17", + "PCIE_LH10_1", + "PCIE_SE2A1_14", + "PCIE_LOGIC_OUTS_B5_L_7", + "PCIE_IMUX13_L_6", + "PCIE_SW2A3_18", + "PCIE_LOGIC_OUTS_B11_R_14", + "PCIE_IMUX25_R_11", + "PCIE_IMUX40_R_1", + "PCIE_TRNFCNPD3", + "PCIE_EL1BEG3_9", + "PCIE_DBGVECA57", + "PCIE_CFGDEVID1", + "PCIE_TRNRD21", + "PCIE_SE4BEG0_12", + "PCIE_IMUX36_L_17", + "PCIE_IMUX6_L_0", + "PCIE_LOGIC_OUTS_B18_L_12", + "PCIE_LOGIC_OUTS_B11_L_8", + "PCIE_CFGERRAERHEADERLOG77", + "PCIE_IMUX12_L_19", + "PCIE_EE2A2_2", + "PCIE_IMUX25_L_10", + "PCIE_LOGIC_OUTS_B19_R_2", + "PCIE_DRPDO11", + "PCIE_LH4_8", + "PCIE_MIMTXRDATA60", + "PCIE_BYP7_R_18", + "PCIE_TL2ERRHDR21", + "PCIE_CTRL1_R_18", + "PCIE_LOGIC_OUTS_B11_L_0", + "PCIE_NE2A1_7", + "PCIE_NE4C1_13", + "PCIE_IMUX2_R_13", + "PCIE_EE4BEG2_5", + "PCIE_IMUX23_L_15", + "PCIE_MIMTXWDATA31", + "PCIE_NW2A3_8", + "PCIE_CFGERRAERHEADERLOG30", + "PCIE_WW4A0_16", + "PCIE_PIPETX0DATA10", + "PCIE_LOGIC_OUTS_B21_L_13", + "PCIE_XILUNCONNOUT6", + "PCIE_IMUX28_R_15", + "PCIE_LOGIC_OUTS_B2_L_10", + "PCIE_IMUX21_R_17", + "PCIE_IMUX27_L_16", + "PCIE_FAN4_R_10", + "PCIE_WW2END0_16", + "PCIE_USERRSTN", + "PCIE_SW4END0_18", + "PCIE_IMUX44_L_5", + "PCIE_CFGLINKCONTROLBANDWIDTHINTEN", + "PCIE_LOGIC_OUTS_B20_L_2", + "PCIE_SW4END1_14", + "PCIE_TRNTDLLPDATA18", + "PCIE_IMUX26_R_0", + "PCIE_IMUX30_R_9", + "PCIE_IMUX18_R_1", + "PCIE_NE2A0_18", + "PCIE_IMUX35_R_18", + "PCIE_FAN5_L_19", + "PCIE_CFGERRAERHEADERLOG105", + "PCIE_LOGIC_OUTS_B4_R_13", + "PCIE_NE2A0_9", + "PCIE_LH12_13", + "PCIE_WW4END1_6", + "PCIE_BYP1_R_6", + "PCIE_LH9_6", + "PCIE_IMUX46_L_15", + "PCIE_MIMRXRDATA7", + "PCIE_IMUX40_L_9", + "PCIE_LOGIC_OUTS_B11_R_13", + "PCIE_IMUX39_L_14", + "PCIE_LOGIC_OUTS_B8_R_16", + "PCIE_LOGIC_OUTS_B12_L_9", + "PCIE_CFGAERECRCGENEN", + "PCIE_LOGIC_OUTS_B20_R_18", + "PCIE_FAN0_L_3", + "PCIE_LH11_4", + "PCIE_LOGIC_OUTS_B14_R_4", + "PCIE_TRNTD96", + "PCIE_CFGSUBSYSID11", + "PCIE_BLOCK_OUTS_B0_R_12", + "PCIE_IMUX22_L_17", + "PCIE_IMUX23_R_8", + "PCIE_EE4BEG2_13", + "PCIE_MIMTXWDATA6", + "PCIE_PIPETX6DATA3", + "PCIE_WW4END2_13", + "PCIE_PIPETX3DATA7", + "PCIE_DRPDI3", + "PCIE_TRNRDLLPDATA55", + "PCIE_IMUX21_R_2", + "PCIE_SW4A2_16", + "PCIE_TRNRD17", + "PCIE_DRPADDR3", + "PCIE_IMUX11_L_0", + "PCIE_TRNTDLLPDSTRDY", + "PCIE_CFGDEVID15", + "PCIE_IMUX15_R_11", + "PCIE_LOGIC_OUTS_B2_L_7", + "PCIE_LOGIC_OUTS_B0_R_0", + "PCIE_MIMRXRDATA59", + "PCIE_CFGCOMMANDMEMENABLE", + "PCIE_BLOCK_OUTS_B2_R_5", + "PCIE_LOGIC_OUTS_B19_L_8", + "PCIE_LOGIC_OUTS_B22_R_19", + "PCIE_CLK1_R_3", + "PCIE_DBGVECC7", + "PCIE_CFGERRAERHEADERLOG15", + "PCIE_LOGIC_OUTS_B17_L_1", + "PCIE_NW2A3_1", + "PCIE_DBGVECA31", + "PCIE_MIMTXREN", + "PCIE_IMUX7_R_7", + "PCIE_LH1_13", + "PCIE_PIPERX0STATUS0", + "PCIE_WR1END3_11", + "PCIE_WW2A3_18", + "PCIE_WW2A2_6", + "PCIE_NW4A2_17", + "PCIE_IMUX38_R_4", + "PCIE_IMUX37_R_10", + "PCIE_IMUX37_L_3", + "PCIE_IMUX43_R_8", + "PCIE_IMUX10_L_14", + "PCIE_CFGMSGDATA0", + "PCIE_PLUPSTREAMPREFERDEEMPH", + "PCIE_MIMTXRDATA41", + "PCIE_WL1END1_8", + "PCIE_NW2A1_1", + "PCIE_DRPDO6", + "PCIE_CFGDEVCONTROLCORRERRREPORTINGEN", + "PCIE_LOGIC_OUTS_B18_R_6", + "PCIE_SE4C3_12", + "PCIE_IMUX9_L_1", + "PCIE_SE2A0_4", + "PCIE_LH3_17", + "PCIE_IMUX18_L_11", + "PCIE_TRNTD6", + "PCIE_IMUX1_R_14", + "PCIE_CFGERRAERHEADERLOG121", + "PCIE_WR1END2_10", + "PCIE_WW2A1_9", + "PCIE_PLRXPMSTATE1", + "PCIE_WW4END0_17", + "PCIE_LOGIC_OUTS_B16_L_9", + "PCIE_WW4B3_18", + "PCIE_NW2A2_16", + "PCIE_PIPETX2DATA7", + "PCIE_WW4C1_6", + "PCIE_MIMTXRDATA20", + "PCIE_TRNRD98", + "PCIE_LOGIC_OUTS_B14_R_16", + "PCIE_EE4BEG2_14", + "PCIE_IMUX10_R_2", + "PCIE_IMUX13_R_9", + "PCIE_CFGSUBSYSID1", + "PCIE_LOGIC_OUTS_B6_L_15", + "PCIE_CFGAERROOTERRNONFATALERRREPORTINGEN", + "PCIE_LOGIC_OUTS_B20_R_7", + "PCIE_PIPETX4CHARISK1", + "PCIE_PIPERX2ELECIDLE", + "PCIE_EL1BEG3_8", + "PCIE_EE4BEG3_12", + "PCIE_SE2A1_11", + "PCIE_EE4C3_18", + "PCIE_FAN3_R_10", + "PCIE_LOGIC_OUTS_B20_L_1", + "PCIE_LOGIC_OUTS_B15_L_11", + "PCIE_MIMRXRDATA61", + "PCIE_IMUX13_L_18", + "PCIE_SE2A0_0", + "PCIE_LOGIC_OUTS_B10_L_4", + "PCIE_LH2_17", + "PCIE_EE4C3_12", + "PCIE_IMUX20_L_5", + "PCIE_PIPERX6DATA8", + "PCIE_FAN3_L_14", + "PCIE_MIMTXRADDR7", + "PCIE_EE4B3_3", + "PCIE_WW4A0_11", + "PCIE_DBGVECA15", + "PCIE_MIMRXRDATA66", + "PCIE_CFGVENDID3", + "PCIE_NW2A3_3", + "PCIE_IMUX27_R_12", + "PCIE_CFGDSN30", + "PCIE_IMUX5_L_9", + "PCIE_SW4A1_19", + "PCIE_IMUX43_L_9", + "PCIE_LOGIC_OUTS_B18_L_0", + "PCIE_MIMTXRDATA56", + "PCIE_BYP0_L_17", + "PCIE_CFGERRAERHEADERLOG122", + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL0", + "PCIE_IMUX26_L_18", + "PCIE_CFGERRAERHEADERLOG78", + "PCIE_EE4B3_16", + "PCIE_FAN6_L_13", + "PCIE_SE2A1_10", + "PCIE_BYP0_R_12", + "PCIE_CFGTRANSACTIONADDR5", + "PCIE_IMUX21_L_2", + "PCIE_CFGLINKCONTROLASPMCONTROL1", + "PCIE_WW4C1_7", + "PCIE_WW4A1_7", + "PCIE_LH2_2", + "PCIE_IMUX34_R_2", + "PCIE_WW4C0_7", + "PCIE_SW4A0_14", + "PCIE_IMUX33_R_14", + "PCIE_LOGIC_OUTS_B16_L_12", + "PCIE_TRNTD63", + "PCIE_TRNTDLLPDATA13", + "PCIE_SE2A1_6", + "PCIE_NE4C0_4", + "PCIE_LOGIC_OUTS_B23_R_13", + "PCIE_LOGIC_OUTS_B23_L_16", + "PCIE_MONITOR_N_8", + "PCIE_EE4C3_5", + "PCIE_IMUX40_R_0", + "PCIE_PIPETX2DATA5", + "PCIE_IMUX46_R_14", + "PCIE_BLOCK_OUTS_B1_L_3", + "PCIE_CTRL1_R_2", + "PCIE_WR1END3_17", + "PCIE_BYP7_R_8", + "PCIE_CFGERRAERHEADERLOG49", + "PCIE_MIMTXRDATA45", + "PCIE_WW2A3_6", + "PCIE_IMUX9_R_18", + "PCIE_DBGVECC10", + "PCIE_FAN1_R_9", + "PCIE_EE4C0_7", + "PCIE_IMUX46_L_12", + "PCIE_LOGIC_OUTS_B4_L_10", + "PCIE_DBGVECB6", + "PCIE_IMUX41_R_5", + "PCIE_LOGIC_OUTS_B17_R_3", + "PCIE_NE4BEG3_12", + "PCIE_LOGIC_OUTS_B1_R_18", + "PCIE_IMUX38_L_8", + "PCIE_WW2A1_17", + "PCIE_IMUX18_L_4", + "PCIE_EL1BEG3_7", + "PCIE_SW4A3_4", + "PCIE_WL1END0_19", + "PCIE_IMUX23_L_14", + "PCIE_IMUX1_R_16", + "PCIE_DBGVECA43", + "PCIE_EE4C0_3", + "PCIE_WL1END0_16", + "PCIE_CLK1_R_11", + "PCIE_WW4A0_1", + "PCIE_NW4END3_11", + "PCIE_IMUX26_L_8", + "PCIE_EE4BEG1_15", + "PCIE_NW4END2_12", + "PCIE_IMUX26_R_2", + "PCIE_LH3_0", + "PCIE_TRNRSOF", + "PCIE_PIPETX0CHARISK0", + "PCIE_MIMTXWDATA29", + "PCIE_SE4C1_17", + "PCIE_CFGDSN23", + "PCIE_WR1END0_1", + "PCIE_CFGERRAERHEADERLOG56", + "PCIE_PLDBGVEC4", + "PCIE_BYP4_L_3", + "PCIE_FAN0_R_16", + "PCIE_IMUX27_R_17", + "PCIE_LOGIC_OUTS_B17_L_10", + "PCIE_LH3_3", + "PCIE_TRNTDLLPDATA31", + "PCIE_BYP5_R_6", + "PCIE_TRNRD63", + "PCIE_CFGTRANSACTION", + "PCIE_WW2END1_5", + "PCIE_IMUX14_R_12", + "PCIE_CLK0_L_15", + "PCIE_WW4END0_1", + "PCIE_CFGERRTLPCPLHEADER7", + "PCIE_BYP6_L_6", + "PCIE_IMUX44_L_1", + "PCIE_CFGVCTCVCMAP5", + "PCIE_DRPDI15", + "PCIE_CFGPCIECAPINTERRUPTMSGNUM3", + "PCIE_LOGIC_OUTS_B8_R_7", + "PCIE_LOGIC_OUTS_B16_L_13", + "PCIE_BYP4_R_12", + "PCIE_TRNRDLLPDATA0", + "PCIE_CTRL0_R_16", + "PCIE_SW2A1_13", + "PCIE_LH7_17", + "PCIE_WR1END2_12", + "PCIE_NE4BEG2_1", + "PCIE_EL1BEG0_14", + "PCIE_WW4B3_9", + "PCIE_LOGIC_OUTS_B8_L_6", + "PCIE_CFGDSN21", + "PCIE_MIMRXRDATA38", + "PCIE_FAN6_R_13", + "PCIE_IMUX29_R_6", + "PCIE_LOGIC_OUTS_B7_R_16", + "PCIE_IMUX16_R_2", + "PCIE_BYP2_L_9", + "PCIE_MONITOR_P_9", + "PCIE_IMUX42_R_7", + "PCIE_IMUX34_R_17", + "PCIE_FAN2_L_10", + "PCIE_WW4C3_4", + "PCIE_IMUX18_R_12", + "PCIE_IMUX34_L_8", + "PCIE_IMUX14_L_16", + "PCIE_IMUX24_R_5", + "PCIE_MIMRXWDATA15", + "PCIE_IMUX14_L_17", + "PCIE_CFGERRAERHEADERLOG47", + "PCIE_TRNRDLLPDATA40", + "PCIE_MIMRXRADDR0", + "PCIE_WW4A2_4", + "PCIE_SW4END1_7", + "PCIE_PIPETX2POWERDOWN1", + "PCIE_CFGAERROOTERRFATALERRREPORTINGEN", + "PCIE_IMUX44_L_9", + "PCIE_PIPERX4PHYSTATUS", + "PCIE_BLOCK_OUTS_B3_R_16", + "PCIE_SW4END0_12", + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL1", + "PCIE_SW4END1_0", + "PCIE_WW2END2_18", + "PCIE_IMUX17_L_6", + "PCIE_TRNTD54", + "PCIE_NE2A1_14", + "PCIE_NE4BEG0_6", + "PCIE_PIPERX4DATA3", + "PCIE_IMUX46_R_12", + "PCIE_IMUX21_L_1", + "PCIE_SE2A3_19", + "PCIE_IMUX38_L_11", + "PCIE_LOGIC_OUTS_B13_R_0", + "PCIE_SE4BEG0_2", + "PCIE_MONITOR_N_4", + "PCIE_TRNRDSTRDY", + "PCIE_MIMTXWDATA4", + "PCIE_WR1END3_2", + "PCIE_IMUX20_R_17", + "PCIE_IMUX28_L_10", + "PCIE_BYP3_L_2", + "PCIE_BYP0_L_1", + "PCIE_IMUX21_L_19", + "PCIE_IMUX40_L_18", + "PCIE_IMUX33_L_11", + "PCIE_NE4BEG0_16", + "PCIE_PIPETX0CHARISK1", + "PCIE_LOGIC_OUTS_B4_R_4", + "PCIE_ER1BEG3_4", + "PCIE_WW4A3_13", + "PCIE_FAN4_L_5", + "PCIE_CFGERRAERHEADERLOG116", + "PCIE_NE4C3_3", + "PCIE_EE2BEG2_13", + "PCIE_IMUX41_L_17", + "PCIE_IMUX0_L_14", + "PCIE_IMUX39_L_10", + "PCIE_IMUX33_R_19", + "PCIE_NW4END0_15", + "PCIE_WW2A1_7", + "PCIE_IMUX22_L_2", + "PCIE_WL1END2_1", + "PCIE_IMUX21_L_15", + "PCIE_FAN1_R_14", + "PCIE_IMUX32_L_1", + "PCIE_SE4C0_5", + "PCIE_PLPHYLNKUPN", + "PCIE_DRPADDR2", + "PCIE_BLOCK_OUTS_B3_L_14", + "PCIE_IMUX44_R_15", + "PCIE_NE4C1_8", + "PCIE_BYP1_R_9", + "PCIE_BYP2_L_6", + "PCIE_MIMRXRDATA30", + "PCIE_IMUX15_L_3", + "PCIE_EE4BEG0_8", + "PCIE_MONITOR_N_13", + "PCIE_BYP6_L_7", + "PCIE_MIMRXWDATA51", + "PCIE_BLOCK_OUTS_B1_R_13", + "PCIE_IMUX39_R_18", + "PCIE_IMUX10_L_19", + "PCIE_EL1BEG1_18", + "PCIE_LOGIC_OUTS_B14_R_1", + "PCIE_LOGIC_OUTS_B0_L_11", + "PCIE_WW2A0_5", + "PCIE_LH8_2", + "PCIE_IMUX24_L_11", + "PCIE_IMUX2_L_10", + "PCIE_IMUX20_L_8", + "PCIE_TRNRD120", + "PCIE_IMUX6_L_2", + "PCIE_LOGIC_OUTS_B8_R_19", + "PCIE_CFGMGMTDI18", + "PCIE_WW4END0_3", + "PCIE_LH10_16", + "PCIE_IMUX15_R_8", + "PCIE_NW4END1_3", + "PCIE_EE4BEG3_14", + "PCIE_LH6_7", + "PCIE_CLK1_L_0", + "PCIE_IMUX25_R_16", + "PCIE_CTRL0_R_11", + "PCIE_PIPETX4DATA6", + "PCIE_BLOCK_OUTS_B0_L_14", + "PCIE_PIPETX2DATA11", + "PCIE_TRNRD61", + "PCIE_IMUX3_R_14", + "PCIE_FAN2_L_1", + "PCIE_NE4BEG3_15", + "PCIE_FAN6_L_3", + "PCIE_CFGDSN38", + "PCIE_TRNTD2", + "PCIE_WW4B0_1", + "PCIE_WW2END0_19", + "PCIE_IMUX0_R_9", + "PCIE_LOGIC_OUTS_B10_L_16", + "PCIE_BYP2_R_15", + "PCIE_FAN3_R_4", + "PCIE_BLOCK_OUTS_B0_L_2", + "PCIE_IMUX9_R_11", + "PCIE_FAN5_R_17", + "PCIE_FAN1_L_12", + "PCIE_MIMTXWDATA58", + "PCIE_WR1END2_18", + "PCIE_CFGERRAERHEADERLOG13", + "PCIE_DBGSCLRG", + "PCIE_TRNFCCPLD3", + "PCIE_TRNFCNPD0", + "PCIE_DBGVECB4", + "PCIE_CFGPMFORCESTATEENN", + "PCIE_IMUX21_R_1", + "PCIE_MIMRXRDATA41", + "PCIE_BYP5_R_17", + "PCIE_MIMTXWDATA36", + "PCIE_CFGMGMTDWADDR4", + "PCIE_TRNRD76", + "PCIE_IMUX26_R_19", + "PCIE_NW4A3_14", + "PCIE_CFGREVID4", + "PCIE_LOGIC_OUTS_B11_L_12", + "PCIE_DRPADDR8", + "PCIE_IMUX19_R_5", + "PCIE_CFGERRAERHEADERLOG70", + "PCIE_BYP0_R_9", + "PCIE_DBGVECB62", + "PCIE_PIPERX2DATA9", + "PCIE_CTRL0_L_5", + "PCIE_IMUX24_L_18", + "PCIE_WW2END3_5", + "PCIE_IMUX30_R_7", + "PCIE_EE2BEG2_5", + "PCIE_WW4A3_18", + "PCIE_EL1BEG3_3", + "PCIE_PIPERX3DATA8", + "PCIE_MIMRXWDATA35", + "PCIE_EE4BEG1_7", + "PCIE_IMUX29_R_8", + "PCIE_IMUX11_L_10", + "PCIE_CFGERRTLPCPLHEADER24", + "PCIE_SW4A1_14", + "PCIE_TL2ERRHDR27", + "PCIE_TRNRREM1", + "PCIE_LOGIC_OUTS_B5_L_0", + "PCIE_MIMTXRDATA26", + "PCIE_IMUX45_R_11", + "PCIE_CFGERRAERHEADERLOG94", + "PCIE_IMUX15_L_1", + "PCIE_MIMRXWDATA62", + "PCIE_BYP0_L_5", + "PCIE_WW2END3_15", + "PCIE_NW4END3_4", + "PCIE_WW2A0_1", + "PCIE_EE4BEG2_19", + "PCIE_BLOCK_OUTS_B1_R_8", + "PCIE_MIMTXWDATA64", + "PCIE_TRNTDSTRDY3", + "PCIE_CFGTRANSACTIONADDR1", + "PCIE_IMUX38_L_4", + "PCIE_IMUX39_R_17", + "PCIE_ER1BEG3_1", + "PCIE_WW2A1_1", + "PCIE_LOGIC_OUTS_B21_L_10", + "PCIE_IMUX6_R_14", + "PCIE_WW4A0_17", + "PCIE_BYP3_R_8", + "PCIE_LOGIC_OUTS_B22_R_5", + "PCIE_WW2END0_17", + "PCIE_LL2SENDENTERL23", + "PCIE_ER1BEG2_9", + "PCIE_WW2END2_12", + "PCIE_ER1BEG3_2", + "PCIE_IMUX44_L_6", + "PCIE_EE4C3_8", + "PCIE_LOGIC_OUTS_B11_L_19", + "PCIE_IMUX31_R_3", + "PCIE_IMUX42_R_19", + "PCIE_IMUX31_R_17", + "PCIE_PIPETX1POWERDOWN1", + "PCIE_IMUX44_R_11", + "PCIE_BYP6_L_5", + "PCIE_WW4B2_16", + "PCIE_WW4B2_10", + "PCIE_WR1END0_12", + "PCIE_BYP6_L_12", + "PCIE_IMUX47_L_14", + "PCIE_CFGDEVCONTROL2ATOMICREQUESTEREN", + "PCIE_LOGIC_OUTS_B18_R_12", + "PCIE_IMUX36_R_0", + "PCIE_PIPETX3COMPLIANCE", + "PCIE_WW4A3_19", + "PCIE_WW4END0_10", + "PCIE_CFGERRAERHEADERLOG97", + "PCIE_CFGDSBUSNUMBER1", + "PCIE_BLOCK_OUTS_B1_L_17", + "PCIE_PIPERX0STATUS2", + "PCIE_EE4B2_2", + "PCIE_IMUX29_L_4", + "PCIE_FAN5_R_1", + "PCIE_LOGIC_OUTS_B22_L_16", + "PCIE_SW4END1_6", + "PCIE_IMUX11_R_9", + "PCIE_CLK1_L_18", + "PCIE_LOGIC_OUTS_B7_L_7", + "PCIE_PIPERX5DATA8", + "PCIE_EE4A3_19", + "PCIE_LH5_16", + "PCIE_LOGIC_OUTS_B17_R_7", + "PCIE_BLOCK_OUTS_B1_R_16", + "PCIE_PIPETX3DATA11", + "PCIE_TL2ERRHDR39", + "PCIE_TRNFCCPLH0", + "PCIE_BLOCK_OUTS_B1_L_13", + "PCIE_IMUX46_L_14", + "PCIE_FAN5_R_5", + "PCIE_PIPETX2CHARISK1", + "PCIE_IMUX1_R_15", + "PCIE_BYP7_L_3", + "PCIE_BYP4_L_10", + "PCIE_DBGVECA19", + "PCIE_IMUX28_R_8", + "PCIE_EE2BEG0_4", + "PCIE_IMUX7_R_1", + "PCIE_NE4BEG2_4", + "PCIE_XILUNCONNOUT0", + "PCIE_WW4END2_8", + "PCIE_IMUX19_L_3", + "PCIE_IMUX39_L_16", + "PCIE_EE2A1_5", + "PCIE_WR1END2_5", + "PCIE_SE4BEG0_11", + "PCIE_SE2A0_7", + "PCIE_BYP1_R_1", + "PCIE_EE4A1_0", + "PCIE_SW4A2_17", + "PCIE_PMVSELECT2", + "PCIE_NE4C1_18", + "PCIE_DBGVECB35", + "PCIE_IMUX15_L_18", + "PCIE_TL2ERRHDR42", + "PCIE_SE2A2_5", + "PCIE_BYP5_L_3", + "PCIE_IMUX43_L_18", + "PCIE_CLK1_R_19", + "PCIE_LOGIC_OUTS_B3_L_19", + "PCIE_MIMTXWDATA19", + "PCIE_BLOCK_OUTS_B3_R_17", + "PCIE_MONITOR_N_0", + "PCIE_IMUX28_R_19", + "PCIE_LOGIC_OUTS_B3_L_9", + "PCIE_CFGMGMTBYTEENN1", + "PCIE_MIMTXWDATA37", + "PCIE_LOGIC_OUTS_B20_R_12", + "PCIE_FAN6_R_10", + "PCIE_WW4A3_17", + "PCIE_CFGMSGDATA13", + "PCIE_SE2A3_3", + "PCIE_IMUX6_R_1", + "PCIE_CFGERRAERHEADERLOG16", + "PCIE_TRNRD19", + "PCIE_TRNRD36", + "PCIE_SE2A1_1", + "PCIE_NW2A3_6", + "PCIE_LOGIC_OUTS_B14_L_12", + "PCIE_CFGDEVID3", + "PCIE_BYP7_R_14", + "PCIE_WL1END2_17", + "PCIE_LH10_10", + "PCIE_IMUX46_L_19", + "PCIE_LOGIC_OUTS_B13_L_17", + "PCIE_LOGIC_OUTS_B2_R_14", + "PCIE_WW4A1_15", + "PCIE_EE4A3_15", + "PCIE_FAN5_R_2", + "PCIE_CFGDEVID8", + "PCIE_IMUX39_L_0", + "PCIE_IMUX1_L_3", + "PCIE_LH4_0", + "PCIE_WL1END0_17", + "PCIE_MIMRXWADDR0", + "PCIE_TRNTDLLPDATA20", + "PCIE_IMUX10_R_10", + "PCIE_MIMTXWDATA66", + "PCIE_IMUX46_R_3", + "PCIE_IMUX6_L_18", + "PCIE_CTRL1_L_16", + "PCIE_WW2A3_9", + "PCIE_BLOCK_OUTS_B3_R_0", + "PCIE_NE4C2_1", + "PCIE_IMUX20_R_15", + "PCIE_LOGIC_OUTS_B2_L_12", + "PCIE_EE4C1_4", + "PCIE_IMUX43_R_1", + "PCIE_TRNTDLLPDATA11", + "PCIE_TRNRDLLPDATA18", + "PCIE_IMUX10_R_7", + "PCIE_LH9_12", + "PCIE_EE2A3_18", + "PCIE_EE2A1_18", + "PCIE_TRNTD125", + "PCIE_EE4A0_11", + "PCIE_TRNTDLLPSRCRDY", + "PCIE_NE2A3_6", + "PCIE_EL1BEG0_7", + "PCIE_CFGDEVCONTROLEXTTAGEN", + "PCIE_IMUX10_L_3", + "PCIE_DBGVECC11", + "PCIE_FAN4_L_16", + "PCIE_IMUX44_R_10", + "PCIE_MIMRXRADDR3", + "PCIE_WR1END1_15", + "PCIE_CFGFORCEMPS0", + "PCIE_SW4A2_7", + "PCIE_MIMRXWADDR2", + "PCIE_EE4BEG3_18", + "PCIE_WW4A0_7", + "PCIE_SE4C2_15", + "PCIE_TRNRDLLPDATA54", + "PCIE_EL1BEG1_15", + "PCIE_TRNRNPREQ", + "PCIE_SW4A0_4", + "PCIE_DBGVECB43", + "PCIE_IMUX9_L_16", + "PCIE_LH5_8", + "PCIE_IMUX36_R_16", + "PCIE_BYP4_R_8", + "PCIE_EE2A2_7", + "PCIE_CFGINTERRUPTDO2", + "PCIE_LH7_11", + "PCIE_MIMRXRDATA45", + "PCIE_TRNFCCPLH6", + "PCIE_IMUX17_L_11", + "PCIE_IMUX34_L_4", + "PCIE_CFGERRAERHEADERLOG95", + "PCIE_IMUX32_L_10", + "PCIE_LOGIC_OUTS_B23_L_0", + "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2", + "PCIE_FAN1_L_13", + "PCIE_LOGIC_OUTS_B6_R_8", + "PCIE_MONITOR_N_1", + "PCIE_LOGIC_OUTS_B3_L_16", + "PCIE_CLK0_L_6", + "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1", + "PCIE_WL1END1_7", + "PCIE_CFGFORCEMPS1", + "PCIE_NW2A3_9", + "PCIE_IMUX39_R_2", + "PCIE_BYP7_R_1", + "PCIE_NE4BEG3_14", + "PCIE_CFGDSN20", + "PCIE_WW4A3_8", + "PCIE_PIPETX3DATA4", + "PCIE_ER1BEG0_14", + "PCIE_IMUX26_R_13", + "PCIE_EE4B1_1", + "PCIE_LOGIC_OUTS_B16_R_16", + "PCIE_LH2_15", + "PCIE_NW4A1_5", + "PCIE_CFGERRAERHEADERLOG98", + "PCIE_BLOCK_OUTS_B0_R_15", + "PCIE_CFGPMCSRPMESTATUS", + "PCIE_BYP4_R_4", + "PCIE_IMUX28_L_17", + "PCIE_IMUX33_R_6", + "PCIE_LOGIC_OUTS_B8_R_6", + "PCIE_LOGIC_OUTS_B20_R_15", + "PCIE_ER1BEG0_11", + "PCIE_TRNRD53", + "PCIE_TRNRD86", + "PCIE_IMUX31_L_17", + "PCIE_BYP2_R_4", + "PCIE_BLOCK_OUTS_B2_L_11", + "PCIE_LH12_9", + "PCIE_IMUX32_R_6", + "PCIE_LH12_5", + "PCIE_CLK1_R_2", + "PCIE_TRNRDLLPDATA50", + "PCIE_TRNTDLLPDATA3", + "PCIE_LH3_9", + "PCIE_IMUX16_L_18", + "PCIE_IMUX21_R_15", + "PCIE_MIMRXRDATA26", + "PCIE_LOGIC_OUTS_B19_R_16", + "PCIE_MIMRXWDATA9", + "PCIE_CFGERRTLPCPLHEADER35", + "PCIE_WW2A2_2", + "PCIE_LOGIC_OUTS_B7_L_0", + "PCIE_CFGDSN17", + "PCIE_IMUX43_R_9", + "PCIE_PIPERX2DATA4", + "PCIE_FAN7_L_8", + "PCIE_MONITOR_P_19", + "PCIE_IMUX21_R_19", + "PCIE_EE4BEG0_16", + "PCIE_BLOCK_OUTS_B0_R_17", + "PCIE_EE4B1_6", + "PCIE_IMUX19_L_10", + "PCIE_TRNRD70", + "PCIE_EE4B1_14", + "PCIE_WR1END2_15", + "PCIE_NE4C2_10", + "PCIE_IMUX42_R_8", + "PCIE_LOGIC_OUTS_B9_L_10", + "PCIE_NE2A0_8", + "PCIE_FAN6_R_15", + "PCIE_SW4END0_13", + "PCIE_LOGIC_OUTS_B2_R_17", + "PCIE_LOGIC_OUTS_B22_L_14", + "PCIE_IMUX28_L_8", + "PCIE_NW4END1_1", + "PCIE_NW4A0_12", + "PCIE_IMUX19_R_7", + "PCIE_LOGIC_OUTS_B5_R_11", + "PCIE_CTRL1_R_14", + "PCIE_BYP6_L_16", + "PCIE_PIPERX6DATA11", + "PCIE_IMUX37_L_13", + "PCIE_PIPETX2CHARISK0", + "PCIE_PIPERX2DATA14", + "PCIE_IMUX47_R_0", + "PCIE_MIMTXRDATA27", + "PCIE_EE4B2_5", + "PCIE_XILUNCONNOUT3", + "PCIE_WW4END1_13", + "PCIE_LOGIC_OUTS_B22_L_6", + "PCIE_IMUX0_L_3", + "PCIE_NE2A1_8", + "PCIE_EE2BEG0_16", + "PCIE_FAN0_L_17", + "PCIE_PIPERX2DATA1", + "PCIE_LH3_6", + "PCIE_SE4C1_9", + "PCIE_BYP3_R_1", + "PCIE_SW2A3_14", + "PCIE_EE4B2_4", + "PCIE_SE2A0_8", + "PCIE_FAN7_R_5", + "PCIE_SW2A2_8", + "PCIE_IMUX12_R_11", + "PCIE_IMUX1_L_17", + "PCIE_TRNTDLLPDATA15", + "PCIE_TRNTD86", + "PCIE_CTRL0_L_19", + "PCIE_IMUX44_L_16", + "PCIE_IMUX10_R_13", + "PCIE_NE2A1_3", + "PCIE_TRNTD42", + "PCIE_LOGIC_OUTS_B1_R_17", + "PCIE_TRNTD26", + "PCIE_CFGERRAERHEADERLOG7", + "PCIE_ER1BEG0_6", + "PCIE_FAN2_R_14", + "PCIE_CFGCOMMANDINTERRUPTDISABLE", + "PCIE_LOGIC_OUTS_B15_L_14", + "PCIE_XILUNCONNOUT28", + "PCIE_CFGTRANSACTIONADDR0", + "PCIE_EE2A0_6", + "PCIE_SE4BEG0_9", + "PCIE_CFGMGMTWRREADONLYN", + "PCIE_BLOCK_OUTS_B1_R_19", + "PCIE_EE2A3_8", + "PCIE_LH8_13", + "PCIE_IMUX14_R_18", + "PCIE_IMUX29_L_16", + "PCIE_LOGIC_OUTS_B16_R_9", + "PCIE_CFGDSN47", + "PCIE_DBGSCLRF", + "PCIE_PLLANEREVERSALMODE1", + "PCIE_NE2A0_7", + "PCIE_LH10_3", + "PCIE_MONITOR_P_17", + "PCIE_IMUX10_R_14", + "PCIE_IMUX6_L_5", + "PCIE_SE2A0_11", + "PCIE_LOGIC_OUTS_B6_L_7", + "PCIE_SW4A1_8", + "PCIE_NW4A0_3", + "PCIE_IMUX26_R_14", + "PCIE_LOGIC_OUTS_B16_L_3", + "PCIE_SE4C2_11", + "PCIE_IMUX26_L_14", + "PCIE_SW4A2_13", + "PCIE_WW4A1_13", + "PCIE_LOGIC_OUTS_B1_R_0", + "PCIE_EE4C2_10", + "PCIE_IMUX39_R_9", + "PCIE_IMUX16_R_13", + "PCIE_FAN4_R_8", + "PCIE_LH2_18", + "PCIE_IMUX3_L_3", + "PCIE_LH6_12", + "PCIE_IMUX24_L_15", + "PCIE_MIMTXWDATA47", + "PCIE_TRNRD39", + "PCIE_SW4END2_8", + "PCIE_LOGIC_OUTS_B4_R_11", + "PCIE_WR1END2_13", + "PCIE_LH8_6", + "PCIE_LL2LINKSTATUS2", + "PCIE_CFGERRAERHEADERLOG71", + "PCIE_FAN4_R_16", + "PCIE_NW4A3_12", + "PCIE_CFGAERINTERRUPTMSGNUM2", + "PCIE_IMUX30_L_5", + "PCIE_IMUX1_R_13", + "PCIE_NW2A2_19", + "PCIE_NW2A2_3", + "PCIE_SW4END2_17", + "PCIE_CFGERRCPLUNEXPECTN", + "PCIE_WW2A2_14", + "PCIE_BYP4_R_17", + "PCIE_CFGMGMTDO19", + "PCIE_TRNTD127", + "PCIE_IMUX25_R_13", + "PCIE_WW4C2_3", + "PCIE_IMUX5_R_12", + "PCIE_CFGDEVCONTROL2LTREN", + "PCIE_IMUX12_L_11", + "PCIE_IMUX6_L_13", + "PCIE_ER1BEG1_14", + "PCIE_IMUX8_L_2", + "PCIE_IMUX8_L_19", + "PCIE_BYP1_R_12", + "PCIE_IMUX32_L_14", + "PCIE_CFGMSGRECEIVEDASSERTINTD", + "PCIE_EE4B0_0", + "PCIE_IMUX29_L_10", + "PCIE_EE4C1_2", + "PCIE_EDTSINGLEBYPASSCHAIN", + "PCIE_FAN7_L_4", + "PCIE_MIMTXRDATA15", + "PCIE_EE2A2_12", + "PCIE_WW4END2_12", + "PCIE_BYP5_R_5", + "PCIE_BYP5_R_11", + "PCIE_SE4C1_6", + "PCIE_NE4BEG3_8", + "PCIE_PIPERX2DATA7", + "PCIE_IMUX7_L_14", + "PCIE_PIPETX4DATA15", + "PCIE_SW4END0_4", + "PCIE_CFGINTERRUPTDI6", + "PCIE_MIMTXWDATA49", + "PCIE_DBGVECA34", + "PCIE_WW4B1_6", + "PCIE_NW2A0_0", + "PCIE_SE2A3_6", + "PCIE_WW4END2_2", + "PCIE_IMUX11_L_9", + "PCIE_IMUX39_R_1", + "PCIE_WW4A3_1", + "PCIE_NW4END3_18", + "PCIE_SW4A0_8", + "PCIE_LOGIC_OUTS_B16_R_19", + "PCIE_LOGIC_OUTS_B1_L_10", + "PCIE_CFGERRAERHEADERLOG64", + "PCIE_IMUX6_L_19", + "PCIE_BLOCK_OUTS_B3_R_4", + "PCIE_NE4BEG1_18", + "PCIE_LOGIC_OUTS_B20_L_17", + "PCIE_LOGIC_OUTS_B13_R_14", + "PCIE_SE2A1_15", + "PCIE_CFGERRAERHEADERLOG82", + "PCIE_NE4C1_3", + "PCIE_IMUX46_L_11", + "PCIE_FAN7_R_9", + "PCIE_DBGVECB58", + "PCIE_IMUX34_L_14", + "PCIE_SW4END2_6", + "PCIE_ER1BEG3_19", + "PCIE_IMUX3_R_6", + "PCIE_NE4BEG3_13", + "PCIE_LOGIC_OUTS_B23_R_18", + "PCIE_WW2END2_9", + "PCIE_IMUX38_L_7", + "PCIE_LOGIC_OUTS_B16_L_7", + "PCIE_LOGIC_OUTS_B10_L_5", + "PCIE_CLK0_L_14", + "PCIE_CLK0_R_8", + "PCIE_LH11_2", + "PCIE_LOGIC_OUTS_B0_R_3", + "PCIE_FAN6_R_7", + "PCIE_IMUX37_R_18", + "PCIE_EL1BEG0_1", + "PCIE_LH6_11", + "PCIE_IMUX10_R_16", + "PCIE_LH10_15", + "PCIE_MIMTXRDATA13", + "PCIE_NE4C0_5", + "PCIE_TRNRD81", + "PCIE_LOGIC_OUTS_B7_L_2", + "PCIE_EE4BEG2_3", + "PCIE_LOGIC_OUTS_B5_R_12", + "PCIE_LOGIC_OUTS_B3_R_1", + "PCIE_LOGIC_OUTS_B6_L_11", + "PCIE_DBGVECB33", + "PCIE_SW4A3_11", + "PCIE_BYP7_R_12", + "PCIE_IMUX46_L_17", + "PCIE_WW4C0_10", + "PCIE_BYP3_R_17", + "PCIE_EL1BEG0_4", + "PCIE_BYP4_R_9", + "PCIE_MIMRXRDATA25", + "PCIE_BYP6_L_2", + "PCIE_CTRL1_L_11", + "PCIE_LOGIC_OUTS_B10_L_11", + "PCIE_IMUX23_R_15", + "PCIE_EE4C0_19", + "PCIE_IMUX24_L_16", + "PCIE_IMUX2_L_8", + "PCIE_NE4BEG2_16", + "PCIE_IMUX16_R_14", + "PCIE_LOGIC_OUTS_B3_L_10", + "PCIE_IMUX13_R_6", + "PCIE_EE4C1_15", + "PCIE_CFGERRAERHEADERLOG62", + "PCIE_PIPETX7POWERDOWN0", + "PCIE_IMUX35_L_12", + "PCIE_MIMTXWDATA11", + "PCIE_LH9_7", + "PCIE_EE4C2_7", + "PCIE_FAN5_R_18", + "PCIE_EE4B0_4", + "PCIE_IMUX32_L_17", + "PCIE_WW4B1_13", + "PCIE_IMUX2_R_9", + "PCIE_NW4END0_14", + "PCIE_WL1END0_0", + "PCIE_SE4C1_0", + "PCIE_WW4B2_18", + "PCIE_LH4_12", + "PCIE_NW4A0_7", + "PCIE_IMUX8_L_14", + "PCIE_BYP4_L_14", + "PCIE_EE2A2_3", + "PCIE_ER1BEG1_1", + "PCIE_LH4_3", + "PCIE_IMUX46_L_4", + "PCIE_FAN7_R_1", + "PCIE_FAN2_R_8", + "PCIE_IMUX23_L_4", + "PCIE_FAN2_R_11", + "PCIE_SW4A1_9", + "PCIE_IMUX46_L_8", + "PCIE_ER1BEG2_16", + "PCIE_NE4C0_14", + "PCIE_IMUX6_R_15", + "PCIE_LOGIC_OUTS_B6_R_18", + "PCIE_LOGIC_OUTS_B3_L_6", + "PCIE_DBGSCLRH", + "PCIE_LOGIC_OUTS_B8_L_2", + "PCIE_EE4BEG3_10", + "PCIE_PLLINKPARTNERGEN2SUPPORTED", + "PCIE_MIMTXWADDR10", + "PCIE_IMUX21_R_18", + "PCIE_LH7_19", + "PCIE_WW2A2_8", + "PCIE_NE4BEG2_15", + "PCIE_IMUX17_R_13", + "PCIE_IMUX30_R_2", + "PCIE_IMUX29_R_7", + "PCIE_LOGIC_OUTS_B20_R_0", + "PCIE_CFGDSN6", + "PCIE_IMUX15_L_12", + "PCIE_NW2A0_10", + "PCIE_CFGERRAERHEADERLOG83", + "PCIE_NW4END0_18", + "PCIE_IMUX27_L_8", + "PCIE_WW4END2_4", + "PCIE_FAN7_R_18", + "PCIE_BLOCK_OUTS_B2_L_18", + "PCIE_TRNFCNPH3", + "PCIE_DBGVECB37", + "PCIE_EE4C1_14", + "PCIE_LOGIC_OUTS_B5_L_13", + "PCIE_IMUX14_R_19", + "PCIE_ER1BEG0_2", + "PCIE_LOGIC_OUTS_B0_L_14", + "PCIE_CFGDSN1", + "PCIE_SW4A0_17", + "PCIE_TRNTD90", + "PCIE_LOGIC_OUTS_B15_L_4", + "PCIE_IMUX36_L_13", + "PCIE_EE4A2_19", + "PCIE_IMUX27_L_7", + "PCIE_WW2A0_15", + "PCIE_TRNRD9", + "PCIE_IMUX38_L_12", + "PCIE_LOGIC_OUTS_B13_R_15", + "PCIE_IMUX18_L_14", + "PCIE_IMUX38_L_18", + "PCIE_TRNTECRCGEN", + "PCIE_IMUX16_R_4", + "PCIE_LH2_6", + "PCIE_IMUX39_R_14", + "PCIE_IMUX35_R_0", + "PCIE_CFGDSN28", + "PCIE_TRNRD26", + "PCIE_TL2ERRHDR5", + "PCIE_NW2A1_6", + "PCIE_LOGIC_OUTS_B4_R_15", + "PCIE_EE4BEG2_12", + "PCIE_CFGVCTCVCMAP3", + "PCIE_EE2A2_19", + "PCIE_MIMTXRDATA61", + "PCIE_LOGIC_OUTS_B23_R_4", + "PCIE_BYP0_L_4", + "PCIE_ER1BEG0_19", + "PCIE_LOGIC_OUTS_B21_L_1", + "PCIE_BYP1_R_16", + "PCIE_LOGIC_OUTS_B6_L_4", + "PCIE_BYP1_L_6", + "PCIE_LOGIC_OUTS_B18_R_3", + "PCIE_EE4A3_17", + "PCIE_LOGIC_OUTS_B5_R_18", + "PCIE_TRNRDLLPDATA35", + "PCIE_CFGMGMTDO21", + "PCIE_EDTBYPASS", + "PCIE_IMUX7_L_9", + "PCIE_PIPERX0DATA13", + "PCIE_IMUX5_R_13", + "PCIE_BYP6_R_9", + "PCIE_IMUX42_L_6", + "PCIE_SE4BEG2_2", + "PCIE_WW2A0_11", + "PCIE_NE2A2_13", + "PCIE_EE2BEG1_14", + "PCIE_LOGIC_OUTS_B14_L_2", + "PCIE_NW4A0_6", + "PCIE_MIMRXWDATA39", + "PCIE_TRNTDLLPDATA8", + "PCIE_WW4C2_17", + "PCIE_PLLTSSMSTATE0", + "PCIE_IMUX2_L_5", + "PCIE_DBGVECB26", + "PCIE_CFGDSN51", + "PCIE_MONITOR_P_0", + "PCIE_IMUX28_R_6", + "PCIE_CTRL0_L_12", + "PCIE_TRNRD25", + "PCIE_IMUX23_R_5", + "PCIE_PIPERX4DATA12", + "PCIE_PIPERX3STATUS1", + "PCIE_LH11_14", + "PCIE_BYP4_R_5", + "PCIE_LOGIC_OUTS_B0_L_12", + "PCIE_BYP4_R_11", + "PCIE_LOGIC_OUTS_B9_R_6", + "PCIE_MIMRXWDATA14", + "PCIE_LOGIC_OUTS_B7_R_14", + "PCIE_IMUX16_L_7", + "PCIE_LOGIC_OUTS_B17_L_14", + "PCIE_IMUX21_R_4", + "PCIE_MIMRXWADDR5", + "PCIE_IMUX45_L_6", + "PCIE_BLOCK_OUTS_B3_L_17", + "PCIE_FAN3_R_16", + "PCIE_LOGIC_OUTS_B18_R_8", + "PCIE_DBGVECA13", + "PCIE_BLOCK_OUTS_B2_L_6", + "PCIE_BYP1_R_2", + "PCIE_PIPETX5DATA14", + "PCIE_DBGVECB45", + "PCIE_LOGIC_OUTS_B10_R_7", + "PCIE_CFGMGMTDO31", + "PCIE_NE4C0_13", + "PCIE_LOGIC_OUTS_B7_R_7", + "PCIE_IMUX12_R_2", + "PCIE_IMUX43_R_18", + "PCIE_CLK1_L_10", + "PCIE_IMUX27_R_3", + "PCIE_EL1BEG2_2", + "PCIE_IMUX15_R_6", + "PCIE_MIMRXRDATA52", + "PCIE_IMUX5_R_2", + "PCIE_MIMTXRDATA43", + "PCIE_DBGVECA3", + "PCIE_FAN3_R_15", + "PCIE_CTRL1_L_0", + "PCIE_IMUX13_R_8", + "PCIE_WW2END3_19", + "PCIE_IMUX21_L_0", + "PCIE_NW2A2_2", + "PCIE_TRNRD91", + "PCIE_TRNTD41", + "PCIE_CFGDEVID7", + "PCIE_IMUX35_L_5", + "PCIE_NW2A0_15", + "PCIE_CFGERRAERHEADERLOG21", + "PCIE_CFGERRAERHEADERLOG40", + "PCIE_EE4B0_19", + "PCIE_EE4A0_16", + "PCIE_EL1BEG3_2", + "PCIE_LH12_19", + "PCIE_LOGIC_OUTS_B16_L_16", + "PCIE_PIPETX2DATA3", + "PCIE_EE4A2_11", + "PCIE_IMUX47_R_2", + "PCIE_WW2A3_15", + "PCIE_CFGINTERRUPTRDYN", + "PCIE_IMUX30_L_11", + "PCIE_CFGDSDEVICENUMBER2", + "PCIE_IMUX38_L_0", + "PCIE_IMUX16_R_10", + "PCIE_WW4END2_14", + "PCIE_IMUX42_R_15", + "PCIE_NW4A0_17", + "PCIE_BYP3_R_18", + "PCIE_IMUX39_R_11", + "PCIE_SW4END1_12", + "PCIE_IMUX7_L_6", + "PCIE_LOGIC_OUTS_B17_R_5", + "PCIE_FAN5_R_10", + "PCIE_IMUX31_L_18", + "PCIE_CFGVENDID4", + "PCIE_EE2BEG3_13", + "PCIE_IMUX25_R_10", + "PCIE_LOGIC_OUTS_B4_R_9", + "PCIE_EL1BEG3_14", + "PCIE_IMUX30_L_12", + "PCIE_WW4C2_11", + "PCIE_NE2A2_10", + "PCIE_IMUX28_R_1", + "PCIE_LOGIC_OUTS_B18_L_10", + "PCIE_IMUX34_R_7", + "PCIE_LH6_3", + "PCIE_SE4BEG1_8", + "PCIE_PIPETX0POWERDOWN0", + "PCIE_MIMRXWADDR10", + "PCIE_IMUX34_R_19", + "PCIE_BYP7_L_11", + "PCIE_NW2A0_19", + "PCIE_DBGVECB50", + "PCIE_CFGERRTLPCPLHEADER34", + "PCIE_IMUX34_R_16", + "PCIE_TRNRD82", + "PCIE_TRNTREM0", + "PCIE_IMUX36_L_14", + "PCIE_IMUX5_L_10", + "PCIE_WW4END0_11", + "PCIE_WW4B3_5", + "PCIE_BYP6_R_13", + "PCIE_LH12_18", + "PCIE_EE4B2_6", + "PCIE_PIPERX0DATA12", + "PCIE_IMUX14_R_1", + "PCIE_CLK0_R_0", + "PCIE_LOGIC_OUTS_B13_L_9", + "PCIE_PIPERX1DATA11", + "PCIE_XILUNCONNOUT32", + "PCIE_WW4B0_13", + "PCIE_IMUX19_R_17", + "PCIE_SE2A2_17", + "PCIE_IMUX47_R_3", + "PCIE_IMUX43_R_3", + "PCIE_WW2END2_10", + "PCIE_CFGMGMTDI5", + "PCIE_NW4A1_1", + "PCIE_LOGIC_OUTS_B15_L_15", + "PCIE_WR1END2_1", + "PCIE_EE4A3_1", + "PCIE_DBGVECA37", + "PCIE_CFGERRTLPCPLHEADER5", + "PCIE_LOGIC_OUTS_B13_R_8", + "PCIE_PMVENABLEN", + "PCIE_IMUX36_L_5", + "PCIE_SE4C2_16", + "PCIE_WW2A2_17", + "PCIE_MONITOR_P_15", + "PCIE_PIPETX1DATA8", + "PCIE_LOGIC_OUTS_B15_L_16", + "PCIE_IMUX46_R_0", + "PCIE_LOGIC_OUTS_B18_L_5", + "PCIE_FAN1_R_2", + "PCIE_IMUX22_L_9", + "PCIE_MIMRXWDATA27", + "PCIE_FAN5_L_18", + "PCIE_IMUX42_L_12", + "PCIE_IMUX5_R_9", + "PCIE_CFGDSN0", + "PCIE_IMUX22_L_14", + "PCIE_BLOCK_OUTS_B3_L_19", + "PCIE_NE4C2_4", + "PCIE_IMUX20_R_4", + "PCIE_SE4C1_14", + "PCIE_LH2_0", + "PCIE_IMUX36_L_6", + "PCIE_IMUX40_R_18", + "PCIE_LOGIC_OUTS_B1_R_7", + "PCIE_SE4BEG3_10", + "PCIE_TRNFCNPH4", + "PCIE_IMUX0_R_10", + "PCIE_WW4C0_16", + "PCIE_EE2A3_11", + "PCIE_IMUX14_L_6", + "PCIE_CFGERRTLPCPLHEADER10", + "PCIE_IMUX37_L_4", + "PCIE_WW4B1_14", + "PCIE_LH11_5", + "PCIE_TRNTD38", + "PCIE_NE4C3_12", + "PCIE_IMUX0_L_6", + "PCIE_LOGIC_OUTS_B21_L_19", + "PCIE_PIPETX7DATA6", + "PCIE_BYP6_R_6", + "PCIE_LOGIC_OUTS_B23_L_13", + "PCIE_IMUX30_R_17", + "PCIE_PIPERX1DATA1", + "PCIE_WW4A3_6", + "PCIE_SW4END3_4", + "PCIE_FAN7_L_2", + "PCIE_DBGVECB11", + "PCIE_IMUX19_L_11", + "PCIE_LOGIC_OUTS_B9_L_9", + "PCIE_EE4A0_1", + "PCIE_IMUX41_R_16", + "PCIE_TL2ERRHDR37", + "PCIE_IMUX33_L_4", + "PCIE_DBGVECA24", + "PCIE_NW4END0_0", + "PCIE_LOGIC_OUTS_B12_R_18", + "PCIE_WW4B3_13", + "PCIE_IMUX47_L_5", + "PCIE_LOGIC_OUTS_B12_L_5", + "PCIE_LOGIC_OUTS_B21_L_0", + "PCIE_BLOCK_OUTS_B3_L_16", + "PCIE_IMUX6_L_17", + "PCIE_LOGIC_OUTS_B1_L_7", + "PCIE_PIPETX4DATA3", + "PCIE_IMUX31_L_8", + "PCIE_FAN4_R_0", + "PCIE_CFGERRTLPCPLHEADER0", + "PCIE_IMUX47_R_4", + "PCIE_LOGIC_OUTS_B14_L_14", + "PCIE_WW4C3_9", + "PCIE_DBGVECB60", + "PCIE_IMUX39_L_4", + "PCIE_IMUX32_R_16", + "PCIE_EL1BEG3_13", + "PCIE_NE4BEG3_19", + "PCIE_PIPERX7DATA0", + "PCIE_PIPERX7CHARISK1", + "PCIE_WW4A3_15", + "PCIE_FAN2_R_18", + "PCIE_IMUX37_L_16", + "PCIE_MIMTXRDATA17", + "PCIE_IMUX26_R_12", + "PCIE_DBGVECA27", + "PCIE_CFGDSN39", + "PCIE_IMUX16_L_3", + "PCIE_MIMTXRDATA30", + "PCIE_IMUX24_R_13", + "PCIE_CFGDSDEVICENUMBER0", + "PCIE_EE2BEG3_11", + "PCIE_TRNRD65", + "PCIE_NE4C1_15", + "PCIE_NE4BEG3_5", + "PCIE_EE4A3_7", + "PCIE_DBGVECA28", + "PCIE_SW4A1_3", + "PCIE_SW4END1_11", + "PCIE_CLK0_R_13", + "PCIE_WW4END1_4", + "PCIE_IMUX28_L_11", + "PCIE_EE2A1_9", + "PCIE_IMUX12_R_17", + "PCIE_WW2END2_1", + "PCIE_DRPDO2", + "PCIE_MIMTXRADDR9", + "PCIE_IMUX29_R_16", + "PCIE_MIMRXRADDR5", + "PCIE_FAN2_L_12", + "PCIE_PIPETX5CHARISK1", + "PCIE_LH6_6", + "PCIE_IMUX27_R_1", + "PCIE_PIPERX4DATA7", + "PCIE_CFGINTERRUPTDI3", + "PCIE_SE4C0_7", + "PCIE_ER1BEG1_13", + "PCIE_PIPETX3CHARISK1", + "PCIE_NW4END1_14", + "PCIE_NW4A1_12", + "PCIE_EE4A0_17", + "PCIE_LOGIC_OUTS_B10_R_18", + "PCIE_SW4END0_6", + "PCIE_CFGERRAERHEADERLOG79", + "PCIE_CFGSUBSYSVENDID8", + "PCIE_CFGMGMTDO18", + "PCIE_SW2A2_4", + "PCIE_EE4B1_11", + "PCIE_PIPERX7DATA8", + "PCIE_IMUX34_R_9", + "PCIE_SW4END0_17", + "PCIE_LOGIC_OUTS_B1_L_1", + "PCIE_LOGIC_OUTS_B23_L_3", + "PCIE_TRNFCNPH6", + "PCIE_BYP2_L_10", + "PCIE_NE4BEG1_16", + "PCIE_PIPERX7DATA7", + "PCIE_MIMTXRDATA44", + "PCIE_IMUX33_L_18", + "PCIE_PIPETX2DATA10", + "PCIE_IMUX20_L_17", + "PCIE_LOGIC_OUTS_B13_R_17", + "PCIE_IMUX32_L_3", + "PCIE_DBGVECA63", + "PCIE_PIPETX0DATA11", + "PCIE_SW4A3_14", + "PCIE_IMUX38_R_7", + "PCIE_IMUX47_R_13", + "PCIE_WW4A3_9", + "PCIE_FAN5_L_5", + "PCIE_SE4C0_8", + "PCIE_LOGIC_OUTS_B13_R_1", + "PCIE_SW4A1_11", + "PCIE_EE2BEG1_4", + "PCIE_IMUX31_R_11", + "PCIE_LOGIC_OUTS_B7_R_6", + "PCIE_IMUX36_L_16", + "PCIE_WW4B3_3", + "PCIE_PIPERX4DATA10", + "PCIE_CLK0_L_2", + "PCIE_WW2A3_10", + "PCIE_BLOCK_OUTS_B2_R_14", + "PCIE_NE2A2_0", + "PCIE_IMUX4_L_10", + "PCIE_NE2A2_7", + "PCIE_NW2A3_19", + "PCIE_TRNRD80", + "PCIE_IMUX7_L_11", + "PCIE_IMUX17_L_19", + "PCIE_IMUX26_R_10", + "PCIE_NE4C3_15", + "PCIE_IMUX45_R_8", + "PCIE_CLK0_L_11", + "PCIE_FAN1_L_3", + "PCIE_IMUX35_L_6", + "PCIE_NW2A1_7", + "PCIE_EE4B2_19", + "PCIE_CFGERRTLPCPLHEADER17", + "PCIE_MIMTXRDATA14", + "PCIE_IMUX6_R_13", + "PCIE_WW2A3_13", + "PCIE_WW4B2_2", + "PCIE_LOGIC_OUTS_B2_L_5", + "PCIE_TRNTDLLPDATA17", + "PCIE_EL1BEG1_5", + "PCIE_CFGDSN32", + "PCIE_EE2BEG1_3", + "PCIE_CFGLINKCONTROLHWAUTOWIDTHDIS", + "PCIE_CFGERRAERHEADERLOG24", + "PCIE_WR1END1_9", + "PCIE_WW2END1_12", + "PCIE_IMUX45_R_7", + "PCIE_EE4B3_2", + "PCIE_LOGIC_OUTS_B1_L_16", + "PCIE_PIPERX0DATA3", + "PCIE_NE4BEG0_15", + "PCIE_WW4B1_1", + "PCIE_EE4C0_5", + "PCIE_CFGERRAERHEADERLOG100", + "PCIE_BYP0_L_13", + "PCIE_LH9_10", + "PCIE_PIPETX5DATA9", + "PCIE_DBGVECA17", + "PCIE_LOGIC_OUTS_B0_L_9", + "PCIE_ER1BEG0_1", + "PCIE_IMUX46_R_11", + "PCIE_IMUX18_L_10", + "PCIE_SW4END2_10", + "PCIE_IMUX25_L_7", + "PCIE_IMUX28_R_14", + "PCIE_ER1BEG0_16", + "PCIE_WL1END2_10", + "PCIE_PIPERX2DATA12", + "PCIE_SE4BEG3_3", + "PCIE_IMUX13_R_5", + "PCIE_TRNTD113", + "PCIE_LOGIC_OUTS_B4_R_1", + "PCIE_MIMRXRDATA9", + "PCIE_MIMTXRDATA66", + "PCIE_WW4END0_0", + "PCIE_NW2A3_11", + "PCIE_PIPETX1DATA14", + "PCIE_LH10_11", + "PCIE_NW4END0_12", + "PCIE_IMUX22_L_11", + "PCIE_PIPERX0POLARITY", + "PCIE_FAN3_R_3", + "PCIE_WR1END2_2", + "PCIE_FAN4_L_8", + "PCIE_EE2A1_7", + "PCIE_SW4A1_4", + "PCIE_LOGIC_OUTS_B9_R_16", + "PCIE_IMUX0_L_8", + "PCIE_TRNFCNPD7", + "PCIE_IMUX7_L_5", + "PCIE_LOGIC_OUTS_B22_R_9", + "PCIE_LOGIC_OUTS_B18_L_11", + "PCIE_IMUX29_R_13", + "PCIE_LOGIC_OUTS_B13_R_11", + "PCIE_LOGIC_OUTS_B10_L_13", + "PCIE_WW4A0_10", + "PCIE_EE2A1_0", + "PCIE_IMUX34_L_6", + "PCIE_IMUX30_R_16", + "PCIE_TRNRDLLPDATA30", + "PCIE_WL1END2_11", + "PCIE_PIPERX6DATA2", + "PCIE_PLDIRECTEDLINKSPEED", + "PCIE_LOGIC_OUTS_B1_R_13", + "PCIE_TRNTD71", + "PCIE_LOGIC_OUTS_B19_L_10", + "PCIE_SE2A3_1", + "PCIE_BYP3_L_17", + "PCIE_LOGIC_OUTS_B8_L_4", + "PCIE_NW4A2_16", + "PCIE_FAN6_L_11", + "PCIE_LOGIC_OUTS_B5_L_19", + "PCIE_LOGIC_OUTS_B5_R_17", + "PCIE_LL2REPLAYROERR", + "PCIE_IMUX36_R_15", + "PCIE_IMUX2_L_3", + "PCIE_IMUX19_R_10", + "PCIE_BYP5_L_1", + "PCIE_LOGIC_OUTS_B22_L_13", + "PCIE_NE2A1_1", + "PCIE_LOGIC_OUTS_B8_R_12", + "PCIE_LOGIC_OUTS_B1_R_1", + "PCIE_IMUX8_R_2", + "PCIE_MIMRXWDATA7", + "PCIE_IMUX36_L_11", + "PCIE_EE4C1_1", + "PCIE_NW4END2_16", + "PCIE_IMUX6_R_16", + "PCIE_EE4C3_6", + "PCIE_BYP6_R_16", + "PCIE_EE2A3_19", + "PCIE_LOGIC_OUTS_B11_R_9", + "PCIE_EE4BEG2_10", + "PCIE_PIPETX4COMPLIANCE", + "PCIE_PIPETX1DATA7", + "PCIE_WW4B2_17", + "PCIE_TL2ERRHDR23", + "PCIE_NE4BEG0_18", + "PCIE_CFGINTERRUPTDO0", + "PCIE_LOGIC_OUTS_B8_L_11", + "PCIE_LOGIC_OUTS_B5_R_13", + "PCIE_TRNRD56", + "PCIE_MIMRXWDATA60", + "PCIE_IMUX32_L_2", + "PCIE_MIMTXRDATA3", + "PCIE_IMUX35_R_19", + "PCIE_TRNTD53", + "PCIE_SE2A3_5", + "PCIE_IMUX20_L_3", + "PCIE_EE2BEG1_7", + "PCIE_IMUX7_L_16", + "PCIE_TRNRD99", + "PCIE_TL2ERRHDR45", + "PCIE_MIMTXRDATA21", + "PCIE_WW4END1_2", + "PCIE_PIPETX3DATA10", + "PCIE_CFGMGMTDO20", + "PCIE_LOGIC_OUTS_B8_L_9", + "PCIE_DRPDI0", + "PCIE_TL2ERRHDR15", + "PCIE_WR1END1_3", + "PCIE_MIMRXWDATA50", + "PCIE_IMUX5_R_14", + "PCIE_IMUX43_R_11", + "PCIE_FAN6_R_0", + "PCIE_LOGIC_OUTS_B13_L_11", + "PCIE_LOGIC_OUTS_B13_L_6", + "PCIE_CTRL1_L_18", + "PCIE_FAN3_R_6", + "PCIE_CFGDSN19", + "PCIE_IMUX28_R_10", + "PCIE_FAN0_R_5", + "PCIE_WL1END3_9", + "PCIE_LOGIC_OUTS_B23_R_19", + "PCIE_USERCLK", + "PCIE_IMUX16_R_8", + "PCIE_MIMRXWDATA1", + "PCIE_SW2A2_9", + "PCIE_FAN5_L_0", + "PCIE_LOGIC_OUTS_B7_R_9", + "PCIE_EE4B1_2", + "PCIE_LOGIC_OUTS_B13_R_7", + "PCIE_IMUX7_L_18", + "PCIE_CFGDSN63", + "PCIE_LOGIC_OUTS_B21_L_4", + "PCIE_WW4A3_0", + "PCIE_EE4B3_1", + "PCIE_CLK0_R_10", + "PCIE_CFGVENDID5", + "PCIE_IMUX19_L_13", + "PCIE_TRNRDLLPDATA3", + "PCIE_CFGDSN53", + "PCIE_IMUX16_L_4", + "PCIE_WW4A3_11", + "PCIE_LOGIC_OUTS_B7_R_4", + "PCIE_MIMRXWDATA0", + "PCIE_BYP6_R_10", + "PCIE_CFGROOTCONTROLSYSERRCORRERREN", + "PCIE_IMUX30_R_14", + "PCIE_NW4END3_0", + "PCIE_LOGIC_OUTS_B3_L_17", + "PCIE_TL2ERRHDR3", + "PCIE_TL2ERRHDR30", + "PCIE_XILUNCONNOUT8", + "PCIE_EE4C3_16", + "PCIE_LH11_16", + "PCIE_CFGERRAERHEADERLOG60", + "PCIE_CFGPMTURNOFFOKN", + "PCIE_CFGMGMTDI19", + "PCIE_EE2BEG3_14", + "PCIE_WW4C3_5", + "PCIE_PIPETX1DATA5", + "PCIE_SW4A3_1", + "PCIE_IMUX5_L_6", + "PCIE_BLOCK_OUTS_B3_L_9", + "PCIE_CFGDSN35", + "PCIE_DBGVECA54", + "PCIE_LH8_1", + "PCIE_IMUX43_R_13", + "PCIE_IMUX25_L_15", + "PCIE_DBGVECB55", + "PCIE_IMUX20_L_2", + "PCIE_MIMRXRDATA44", + "PCIE_EE4C2_8", + "PCIE_PIPERX4DATA9", + "PCIE_IMUX3_L_2", + "PCIE_PLDIRECTEDLTSSMNEWVLD", + "PCIE_DBGVECA60", + "PCIE_TL2ASPMSUSPENDCREDITCHECKOK", + "PCIE_LH5_17", + "PCIE_IMUX14_R_17", + "PCIE_LOGIC_OUTS_B5_L_6", + "PCIE_IMUX0_R_15", + "PCIE_LOGIC_OUTS_B10_R_6", + "PCIE_EE4B1_15", + "PCIE_WW4C0_0", + "PCIE_WW2END2_16", + "PCIE_IMUX9_R_1", + "PCIE_LOGIC_OUTS_B19_R_11", + "PCIE_MIMRXRDATA5", + "PCIE_PIPERX7PHYSTATUS", + "PCIE_EE4BEG2_8", + "PCIE_CFGMGMTDWADDR1", + "PCIE_IMUX45_R_12", + "PCIE_IMUX35_L_17", + "PCIE_IMUX4_L_9", + "PCIE_IMUX19_R_3", + "PCIE_SW4END2_3", + "PCIE_IMUX32_L_8", + "PCIE_FAN7_L_19", + "PCIE_FAN0_R_4", + "PCIE_LL2TLPRCV", + "PCIE_CFGROOTCONTROLSYSERRFATALERREN", + "PCIE_IMUX10_R_5", + "PCIE_BLOCK_OUTS_B1_L_4", + "PCIE_EDTCHANNELSOUT1", + "PCIE_IMUX27_R_8", + "PCIE_NE4C2_13", + "PCIE_BYP7_R_3", + "PCIE_CFGERRTLPCPLHEADER19", + "PCIE_PIPERX3DATA14", + "PCIE_WW2A2_3", + "PCIE_LOGIC_OUTS_B3_L_8", + "PCIE_IMUX4_R_5", + "PCIE_BLOCK_OUTS_B2_L_13", + "PCIE_IMUX33_L_13", + "PCIE_IMUX39_R_6", + "PCIE_MIMRXRADDR4", + "PCIE_NW4A2_13", + "PCIE_PIPETX0COMPLIANCE", + "PCIE_WW4A0_12", + "PCIE_SW2A3_7", + "PCIE_IMUX24_L_9", + "PCIE_TRNTDLLPDATA30", + "PCIE_EE4BEG3_5", + "PCIE_IMUX6_R_0", + "PCIE_CFGSUBSYSID0", + "PCIE_FAN2_L_13", + "PCIE_LH1_4", + "PCIE_IMUX31_R_6", + "PCIE_LOGIC_OUTS_B5_R_9", + "PCIE_CFGERRAERHEADERLOG92", + "PCIE_LOGIC_OUTS_B2_R_19", + "PCIE_BYP6_L_4", + "PCIE_LOGIC_OUTS_B20_R_2", + "PCIE_LH9_9", + "PCIE_WW2END1_11", + "PCIE_WR1END0_15", + "PCIE_IMUX27_L_18", + "PCIE_IMUX34_L_10", + "PCIE_TRNTD80", + "PCIE_LOGIC_OUTS_B1_L_13", + "PCIE_TL2ERRHDR51", + "PCIE_TRNFCPD0", + "PCIE_EE4C3_19", + "PCIE_LOGIC_OUTS_B20_R_4", + "PCIE_IMUX18_L_17", + "PCIE_FAN7_R_13", + "PCIE_FAN4_R_18", + "PCIE_IMUX41_L_8", + "PCIE_WW4C0_3", + "PCIE_IMUX16_R_7", + "PCIE_IMUX16_R_18", + "PCIE_EE2A3_0", + "PCIE_IMUX28_R_3", + "PCIE_LOGIC_OUTS_B10_R_10", + "PCIE_IMUX8_R_12", + "PCIE_LOGIC_OUTS_B0_R_11", + "PCIE_SW4END1_3", + "PCIE_NE2A3_13", + "PCIE_TRNTD121", + "PCIE_IMUX38_R_16", + "PCIE_SE4C2_19", + "PCIE_TRNFCPD7", + "PCIE_IMUX9_L_10", + "PCIE_NE4BEG0_7", + "PCIE_IMUX11_R_10", + "PCIE_PLDIRECTEDCHANGEDONE", + "PCIE_NE2A0_10", + "PCIE_CFGDEVSTATUSURDETECTED", + "PCIE_DRPDI12", + "PCIE_WW4B2_4", + "PCIE_IMUX8_L_11", + "PCIE_IMUX6_L_11", + "PCIE_WW4B2_19", + "PCIE_IMUX2_L_1", + "PCIE_IMUX25_L_18", + "PCIE_DBGVECC6", + "PCIE_ER1BEG3_8", + "PCIE_SW2A2_19", + "PCIE_LOGIC_OUTS_B2_R_18", + "PCIE_LH3_16", + "PCIE_FAN2_L_11", + "PCIE_LOGIC_OUTS_B10_R_16", + "PCIE_IMUX7_L_10", + "PCIE_WR1END0_5", + "PCIE_MIMTXRDATA32", + "PCIE_TRNTDLLPDATA9", + "PCIE_NW4A1_7", + "PCIE_FAN6_R_14", + "PCIE_NW4A3_3", + "PCIE_FAN3_R_9", + "PCIE_NW2A0_4", + "PCIE_LOGIC_OUTS_B6_L_1", + "PCIE_IMUX31_L_1", + "PCIE_PIPERX1CHARISK0", + "PCIE_EE4C2_2", + "PCIE_FAN4_L_9", + "PCIE_XILUNCONNOUT25", + "PCIE_DRPADDR0", + "PCIE_MIMRXWDATA61", + "PCIE_FAN5_L_12", + "PCIE_LOGIC_OUTS_B7_R_5", + "PCIE_SW4A3_17", + "PCIE_CFGPORTNUMBER6", + "PCIE_DBGVECA22", + "PCIE_PIPETX4ELECIDLE", + "PCIE_WW2A0_3", + "PCIE_EE4C0_12", + "PCIE_LH3_19", + "PCIE_BLOCK_OUTS_B1_R_12", + "PCIE_IMUX37_R_7", + "PCIE_LOGIC_OUTS_B12_R_2", + "PCIE_PIPETX0DATA2", + "PCIE_EL1BEG3_15", + "PCIE_SW4END2_5", + "PCIE_CLK0_R_7", + "PCIE_LOGIC_OUTS_B4_R_2", + "PCIE_LOGIC_OUTS_B23_L_7", + "PCIE_TRNRDLLPDATA38", + "PCIE_EE4B2_13", + "PCIE_IMUX42_L_10", + "PCIE_FAN2_R_19", + "PCIE_BLOCK_OUTS_B3_R_11", + "PCIE_PL2RECEIVERERR", + "PCIE_IMUX47_R_9", + "PCIE_BLOCK_OUTS_B0_R_8", + "PCIE_IMUX1_L_7", + "PCIE_TRNTD32", + "PCIE_WL1END3_2", + "PCIE_BLOCK_OUTS_B0_L_7", + "PCIE_EE4C0_10", + "PCIE_LOGIC_OUTS_B10_R_1", + "PCIE_CFGDEVCONTROLNONFATALREPORTINGEN", + "PCIE_IMUX29_L_18", + "PCIE_IMUX28_R_16", + "PCIE_TRNRD85", + "PCIE_CFGMGMTDO7", + "PCIE_MIMRXWDATA20", + "PCIE_IMUX39_L_19", + "PCIE_CFGERRAERHEADERLOG38", + "PCIE_WW4B0_8", + "PCIE_LOGIC_OUTS_B22_L_11", + "PCIE_IMUX19_R_9", + "PCIE_WW4B0_16", + "PCIE_PIPETX5ELECIDLE", + "PCIE_IMUX22_R_13", + "PCIE_IMUX16_L_2", + "PCIE_SE4BEG3_14", + "PCIE_TRNTDLLPDATA23", + "PCIE_IMUX39_L_18", + "PCIE_IMUX32_L_11", + "PCIE_IMUX23_R_11", + "PCIE_FAN5_R_9", + "PCIE_FAN4_R_7", + "PCIE_TL2ERRHDR22", + "PCIE_BYP0_R_0", + "PCIE_CFGCOMMANDSERREN", + "PCIE_MIMRXWDATA18", + "PCIE_IMUX20_R_12", + "PCIE_EE4C2_13", + "PCIE_LOGIC_OUTS_B13_L_19", + "PCIE_IMUX6_R_8", + "PCIE_IMUX27_L_3", + "PCIE_IMUX14_L_8", + "PCIE_LOGIC_OUTS_B14_L_16", + "PCIE_EE4B1_4", + "PCIE_CFGDSN22", + "PCIE_EDTCHANNELSOUT6", + "PCIE_MIMRXWADDR6", + "PCIE_CFGFORCEEXTENDEDSYNCON", + "PCIE_IMUX9_L_19", + "PCIE_IMUX11_L_17", + "PCIE_LOGIC_OUTS_B4_R_3", + "PCIE_CFGMGMTDI0", + "PCIE_SE2A3_0", + "PCIE_LOGIC_OUTS_B8_R_10", + "PCIE_LOGIC_OUTS_B9_R_13", + "PCIE_DBGVECA51", + "PCIE_WW4C1_15", + "PCIE_LOGIC_OUTS_B7_R_12", + "PCIE_IMUX8_L_17", + "PCIE_NW4A1_18", + "PCIE_TL2ERRHDR55", + "PCIE_WW2END1_3", + "PCIE_MIMTXWDATA24", + "PCIE_TRNRD57", + "PCIE_NE4BEG1_19", + "PCIE_LH2_7", + "PCIE_IMUX7_R_2", + "PCIE_TRNRDLLPDATA10", + "PCIE_IMUX26_L_7", + "PCIE_PLDIRECTEDLTSSMNEW2", + "PCIE_LOGIC_OUTS_B19_R_15", + "PCIE_NE2A2_1", + "PCIE_BYP6_R_7", + "PCIE_IMUX25_L_13", + "PCIE_TRNTD16", + "PCIE_WW4A1_9", + "PCIE_LOGIC_OUTS_B19_R_0", + "PCIE_IMUX32_R_7", + "PCIE_PLINITIALLINKWIDTH2", + "PCIE_EE4A2_2", + "PCIE_FAN4_L_2", + "PCIE_FAN0_R_18", + "PCIE_FAN5_L_1", + "PCIE_PIPERX0DATA5", + "PCIE_LL2TFCINIT1SEQ", + "PCIE_EL1BEG1_17", + "PCIE_EE2BEG3_18", + "PCIE_SE4C1_12", + "PCIE_IMUX21_L_5", + "PCIE_LOGIC_OUTS_B22_R_0", + "PCIE_EE4A0_14", + "PCIE_DBGVECB56", + "PCIE_CFGDSN5", + "PCIE_SW2A3_3", + "PCIE_BLOCK_OUTS_B1_L_6", + "PCIE_SE4C0_9", + "PCIE_IMUX11_R_14", + "PCIE_LOGIC_OUTS_B10_R_19", + "PCIE_LH2_1", + "PCIE_CFGVCTCVCMAP4", + "PCIE_LOGIC_OUTS_B18_L_8", + "PCIE_IMUX12_L_0", + "PCIE_PIPETX4DATA4", + "PCIE_CFGMGMTDWADDR9", + "PCIE_LOGIC_OUTS_B1_R_12", + "PCIE_IMUX40_L_19", + "PCIE_LOGIC_OUTS_B15_L_12", + "PCIE_IMUX13_L_8", + "PCIE_IMUX20_L_14", + "PCIE_FAN3_L_1", + "PCIE_SYSRSTN", + "PCIE_PIPERX5DATA15", + "PCIE_IMUX30_R_15", + "PCIE_WW4A1_16", + "PCIE_DRPWE", + "PCIE_PIPERX2CHANISALIGNED", + "PCIE_LH9_5", + "PCIE_DBGVECA23", + "PCIE_CFGMGMTDO14", + "PCIE_TRNTD84", + "PCIE_IMUX36_R_18", + "PCIE_SE4C2_1", + "PCIE_EE4A2_9", + "PCIE_IMUX14_R_6", + "PCIE_IMUX25_L_9", + "PCIE_LH1_0", + "PCIE_LH12_16", + "PCIE_SW4A0_13", + "PCIE_IMUX19_L_6", + "PCIE_BLOCK_OUTS_B0_R_6", + "PCIE_IMUX2_L_7", + "PCIE_LOGIC_OUTS_B2_R_15", + "PCIE_TRNTD13", + "PCIE_IMUX9_R_17", + "PCIE_LH1_11", + "PCIE_IMUX40_R_13", + "PCIE_CTRL0_R_14", + "PCIE_EE4C3_9", + "PCIE_IMUX26_R_17", + "PCIE_CFGMGMTRDWRDONEN", + "PCIE_CFGREVID2", + "PCIE_PIPERX4DATA13", + "PCIE_CFGERRAERHEADERLOG55", + "PCIE_CLK0_L_1", + "PCIE_IMUX5_R_11", + "PCIE_LOGIC_OUTS_B15_L_9", + "PCIE_IMUX33_L_9", + "PCIE_EE2A3_4", + "PCIE_LOGIC_OUTS_B20_R_5", + "PCIE_LOGIC_OUTS_B4_L_11", + "PCIE_LOGIC_OUTS_B15_L_3", + "PCIE_SW2A0_19", + "PCIE_IMUX33_R_11", + "PCIE_PIPETX5DATA15", + "PCIE_CFGDEVSTATUSFATALERRDETECTED", + "PCIE_IMUX29_R_15", + "PCIE_WW4END0_8", + "PCIE_LOGIC_OUTS_B3_R_18", + "PCIE_IMUX43_L_0", + "PCIE_MIMTXRADDR11", + "PCIE_LOGIC_OUTS_B6_L_14", + "PCIE_LOGIC_OUTS_B5_R_6", + "PCIE_IMUX14_L_18", + "PCIE_BLOCK_OUTS_B2_L_3", + "PCIE_MIMTXRDATA46", + "PCIE_IMUX28_R_0", + "PCIE_XILUNCONNOUT2", + "PCIE_CFGVENDID14", + "PCIE_LOGIC_OUTS_B4_R_16", + "PCIE_LH12_8", + "PCIE_IMUX40_L_16", + "PCIE_TRNTD95", + "PCIE_SE4C2_5", + "PCIE_LOGIC_OUTS_B12_R_0", + "PCIE_LOGIC_OUTS_B7_L_1", + "PCIE_IMUX25_L_8", + "PCIE_NW4A2_11", + "PCIE_CTRL1_R_9", + "PCIE_NW4END3_10", + "PCIE_WR1END1_6", + "PCIE_NW2A0_11", + "PCIE_LOGIC_OUTS_B19_L_17", + "PCIE_LOGIC_OUTS_B1_R_2", + "PCIE_IMUX10_L_18", + "PCIE_LOGIC_OUTS_B19_R_14", + "PCIE_IMUX40_L_4", + "PCIE_TRNFCPD9", + "PCIE_CFGMSGRECEIVEDERRFATAL", + "PCIE_MIMTXRDATA35", + "PCIE_LOGIC_OUTS_B21_L_15", + "PCIE_PIPETX3DATA6", + "PCIE_IMUX2_L_11", + "PCIE_LOGIC_OUTS_B9_L_12", + "PCIE_IMUX27_R_15", + "PCIE_CFGMGMTDI14", + "PCIE_ER1BEG1_18", + "PCIE_CFGERRAERHEADERLOG87", + "PCIE_IMUX32_L_0", + "PCIE_IMUX46_R_6", + "PCIE_CFGERRLOCKEDN", + "PCIE_DBGVECA12", + "PCIE_IMUX6_L_1", + "PCIE_LOGIC_OUTS_B12_R_8", + "PCIE_LH2_3", + "PCIE_LH11_15", + "PCIE_IMUX30_R_8", + "PCIE_EE2BEG0_12", + "PCIE_IMUX18_L_12", + "PCIE_IMUX34_L_1", + "PCIE_CFGINTERRUPTDO6", + "PCIE_EE4C2_17", + "PCIE_LOGIC_OUTS_B11_R_6", + "PCIE_WW4A0_15", + "PCIE_LOGIC_OUTS_B18_R_10", + "PCIE_ER1BEG2_5", + "PCIE_IMUX39_R_10", + "PCIE_LOGIC_OUTS_B19_L_19", + "PCIE_SW4END2_1", + "PCIE_XILUNCONNOUT17", + "PCIE_CLK1_R_12", + "PCIE_LOGIC_OUTS_B10_L_6", + "PCIE_EE4C0_2", + "PCIE_BYP0_R_11", + "PCIE_LOGIC_OUTS_B14_L_1", + "PCIE_IMUX5_L_0", + "PCIE_EE2BEG0_18", + "PCIE_IMUX3_R_17", + "PCIE_IMUX40_L_13", + "PCIE_PIPETX1DATA2", + "PCIE_FAN6_L_17", + "PCIE_FAN1_R_12", + "PCIE_CFGDSN15", + "PCIE_IMUX2_L_16", + "PCIE_IMUX37_R_15", + "PCIE_EE2BEG3_8", + "PCIE_MIMRXRDATA40", + "PCIE_PIPERX7VALID", + "PCIE_BLOCK_OUTS_B0_L_4", + "PCIE_WW2END1_7", + "PCIE_NW4A1_3", + "PCIE_IMUX45_L_0", + "PCIE_WW2A3_1", + "PCIE_MIMRXWDATA46", + "PCIE_CFGDEVSTATUSCORRERRDETECTED", + "PCIE_IMUX32_L_16", + "PCIE_EE2BEG3_12", + "PCIE_TRNRD40", + "PCIE_BYP2_L_16", + "PCIE_CFGSUBSYSID4", + "PCIE_CFGMGMTDI4", + "PCIE_NW4A3_1", + "PCIE_IMUX21_R_14", + "PCIE_NW4A1_2", + "PCIE_FAN3_L_5", + "PCIE_IMUX5_L_1", + "PCIE_TRNTD21", + "PCIE_IMUX38_R_13", + "PCIE_WW4A0_0", + "PCIE_IMUX12_R_18", + "PCIE_CFGMGMTDWADDR6", + "PCIE_IMUX11_R_17", + "PCIE_CFGSUBSYSID15", + "PCIE_SW4A1_7", + "PCIE_IMUX24_R_15", + "PCIE_IMUX42_L_11", + "PCIE_TRNTD45", + "PCIE_FAN4_L_4", + "PCIE_LOGIC_OUTS_B0_L_16", + "PCIE_LOGIC_OUTS_B9_L_18", + "PCIE_LOGIC_OUTS_B0_L_0", + "PCIE_MIMTXWDATA5", + "PCIE_TRNFCNPH1", + "PCIE_BLOCK_OUTS_B0_R_13", + "PCIE_EE4C2_4", + "PCIE_ER1BEG3_16", + "PCIE_TRNRDLLPDATA7", + "PCIE_IMUX33_R_5", + "PCIE_NE2A3_12", + "PCIE_WL1END1_15", + "PCIE_LOGIC_OUTS_B14_R_6", + "PCIE_CFGINTERRUPTDO5", + "PCIE_SE2A2_15", + "PCIE_BYP3_L_14", + "PCIE_NW4A2_18", + "PCIE_IMUX31_L_16", + "PCIE_EE2A2_13", + "PCIE_IMUX41_L_5", + "PCIE_CFGERRAERHEADERLOG2", + "PCIE_IMUX10_R_15", + "PCIE_PIPETX0DATA0", + "PCIE_IMUX20_L_10", + "PCIE_CFGINTERRUPTMSIENABLE", + "PCIE_LH11_12", + "PCIE_CFGMSGRECEIVEDASSERTINTA", + "PCIE_EE4B2_7", + "PCIE_CFGDEVCONTROL2ARIFORWARDEN", + "PCIE_FAN5_L_4", + "PCIE_IMUX8_R_0", + "PCIE_BYP6_R_2", + "PCIE_WW2A0_7", + "PCIE_IMUX36_R_17", + "PCIE_IMUX18_R_13", + "PCIE_IMUX20_L_6", + "PCIE_IMUX28_R_12", + "PCIE_FAN6_R_8", + "PCIE_CFGMGMTDO24", + "PCIE_BYP0_R_3", + "PCIE_IMUX45_R_19", + "PCIE_WW4A0_5", + "PCIE_NW4A2_4", + "PCIE_LOGIC_OUTS_B19_L_9", + "PCIE_IMUX24_L_17", + "PCIE_NW4END3_2", + "PCIE_FAN3_R_12", + "PCIE_IMUX7_R_15", + "PCIE_EE4C2_12", + "PCIE_PIPERX5DATA7", + "PCIE_BLOCK_OUTS_B3_R_19", + "PCIE_NE4BEG1_17", + "PCIE_PIPERX5DATA2", + "PCIE_CFGMGMTDI8", + "PCIE_FAN0_L_13", + "PCIE_PIPERX3DATA4", + "PCIE_TRNTD24", + "PCIE_IMUX28_L_15", + "PCIE_IMUX32_L_18", + "PCIE_IMUX38_L_16", + "PCIE_FAN2_R_10", + "PCIE_SW4A0_1", + "PCIE_WW2END1_17", + "PCIE_CTRL0_L_0", + "PCIE_IMUX3_L_1", + "PCIE_WW2A3_0", + "PCIE_IMUX0_L_12", + "PCIE_SE4BEG2_10", + "PCIE_NW4END2_1", + "PCIE_BYP0_L_8", + "PCIE_MIMRXWDATA44", + "PCIE_TRNTD14", + "PCIE_LOGIC_OUTS_B6_L_10", + "PCIE_LOGIC_OUTS_B19_R_17", + "PCIE_IMUX20_L_19", + "PCIE_EE4BEG2_4", + "PCIE_TRNRDLLPDATA31", + "PCIE_LOGIC_OUTS_B6_L_19", + "PCIE_DBGSCLRD", + "PCIE_BLOCK_OUTS_B3_L_1", + "PCIE_BYP1_L_19", + "PCIE_DBGVECA39", + "PCIE_IMUX1_R_1", + "PCIE_LH5_15", + "PCIE_IMUX21_L_18", + "PCIE_IMUX10_L_6", + "PCIE_PIPETX1DATA4", + "PCIE_FAN3_R_7", + "PCIE_IMUX1_R_3", + "PCIE_IMUX34_R_13", + "PCIE_EE4B0_13", + "PCIE_LH10_7", + "PCIE_MONITOR_P_12", + "PCIE_EE4B0_7", + "PCIE_NW4A3_15", + "PCIE_BYP0_R_16" + ], + "pips": { + "PCIE_BOT.PCIE_PIPETX2DATA5->PCIE_LOGIC_OUTS_B4_L_13": { + "src_wire": "PCIE_PIPETX2DATA5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_L_7->PCIE_PIPERX1DATA15": { + "src_wire": "PCIE_IMUX34_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA23->PCIE_LOGIC_OUTS_B14_L_17": { + "src_wire": "PCIE_TRNRDLLPDATA23", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_1->PCIE_CFGPMFORCESTATEENN": { + "src_wire": "PCIE_IMUX10_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMFORCESTATEENN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_6->PCIE_CFGERRAERHEADERLOG99": { + "src_wire": "PCIE_IMUX5_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG99", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWADDR10->PCIE_LOGIC_OUTS_B23_R_8": { + "src_wire": "PCIE_MIMTXWADDR10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_L_15->PCIE_PIPERX2DATA10": { + "src_wire": "PCIE_IMUX33_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA61->PCIE_LOGIC_OUTS_B12_R_19": { + "src_wire": "PCIE_MIMRXWDATA61", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPD2->PCIE_LOGIC_OUTS_B0_R_1": { + "src_wire": "PCIE_TRNFCPD2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECC1->PCIE_LOGIC_OUTS_B20_L_7": { + "src_wire": "PCIE_DBGVECC1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPH5->PCIE_LOGIC_OUTS_B6_L_3": { + "src_wire": "PCIE_TRNFCNPH5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPD4->PCIE_LOGIC_OUTS_B2_R_1": { + "src_wire": "PCIE_TRNFCPD4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLSELLNKRATE->PCIE_LOGIC_OUTS_B1_L_0": { + "src_wire": "PCIE_PLSELLNKRATE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD100->PCIE_LOGIC_OUTS_B3_R_19": { + "src_wire": "PCIE_TRNRD100", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA15->PCIE_LOGIC_OUTS_B6_L_4": { + "src_wire": "PCIE_PIPETX1DATA15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_1->PCIE_MIMTXRDATA7": { + "src_wire": "PCIE_IMUX3_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPERX0POLARITY->PCIE_LOGIC_OUTS_B1_L_18": { + "src_wire": "PCIE_PIPERX0POLARITY", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_18->PCIE_TRNTD44": { + "src_wire": "PCIE_IMUX14_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD44", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_12->PCIE_CFGDSN25": { + "src_wire": "PCIE_IMUX8_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_L_16->PCIE_PIPERX2DATA5": { + "src_wire": "PCIE_IMUX38_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPD2->PCIE_LOGIC_OUTS_B9_L_4": { + "src_wire": "PCIE_TRNFCNPD2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_13->PCIE_TRNTD65": { + "src_wire": "PCIE_IMUX3_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD65", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPH3->PCIE_LOGIC_OUTS_B13_L_2": { + "src_wire": "PCIE_TRNFCNPH3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_R_9->PCIE_PIPERX5DATA6": { + "src_wire": "PCIE_IMUX35_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWADDR11->PCIE_LOGIC_OUTS_B14_R_16": { + "src_wire": "PCIE_MIMRXWADDR11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_16->PCIE_CFGERRAERHEADERLOG12": { + "src_wire": "PCIE_IMUX13_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA2->PCIE_LOGIC_OUTS_B11_L_18": { + "src_wire": "PCIE_PIPETX0DATA2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_1->PCIE_CFGREVID1": { + "src_wire": "PCIE_IMUX13_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO3->PCIE_LOGIC_OUTS_B13_R_11": { + "src_wire": "PCIE_CFGMGMTDO3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_L_8->PCIE_PIPERX1STATUS1": { + "src_wire": "PCIE_IMUX38_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1STATUS1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD45->PCIE_LOGIC_OUTS_B2_L_16": { + "src_wire": "PCIE_TRNRD45", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_L_2->PCIE_CFGREVID7": { + "src_wire": "PCIE_IMUX15_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_R_14->PCIE_PIPERX6DATA15": { + "src_wire": "PCIE_IMUX34_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_3->PCIE_CFGERRAERHEADERLOG58": { + "src_wire": "PCIE_IMUX13_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG58", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_L_5->PCIE_PIPERX3CHANISALIGNED": { + "src_wire": "PCIE_IMUX33_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3CHANISALIGNED", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA6->PCIE_LOGIC_OUTS_B2_R_17": { + "src_wire": "PCIE_PIPETX4DATA6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA3->PCIE_LOGIC_OUTS_B15_L_3": { + "src_wire": "PCIE_PIPETX3DATA3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_11->PCIE_CFGERRAERHEADERLOG120": { + "src_wire": "PCIE_IMUX6_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG120", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_8->PCIE_MIMTXRDATA34": { + "src_wire": "PCIE_IMUX2_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA34", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO5->PCIE_LOGIC_OUTS_B15_R_11": { + "src_wire": "PCIE_CFGMGMTDO5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA20->PCIE_LOGIC_OUTS_B11_L_17": { + "src_wire": "PCIE_TRNRDLLPDATA20", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_1->PCIE_MIMTXRDATA4": { + "src_wire": "PCIE_IMUX0_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECC6->PCIE_LOGIC_OUTS_B21_L_8": { + "src_wire": "PCIE_DBGVECC6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPH7->PCIE_LOGIC_OUTS_B4_R_3": { + "src_wire": "PCIE_TRNFCPH7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGSCLRB->PCIE_LOGIC_OUTS_B20_L_10": { + "src_wire": "PCIE_DBGSCLRB", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSDLLACTIVE->PCIE_LOGIC_OUTS_B12_L_19": { + "src_wire": "PCIE_CFGLINKSTATUSDLLACTIVE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_8->PCIE_CFGERRAERHEADERLOG106": { + "src_wire": "PCIE_IMUX4_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG106", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRREM0->PCIE_LOGIC_OUTS_B1_R_11": { + "src_wire": "PCIE_TRNRREM0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_7->PCIE_TRNTD113": { + "src_wire": "PCIE_IMUX1_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD113", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4CHARISK1->PCIE_LOGIC_OUTS_B16_R_15": { + "src_wire": "PCIE_PIPETX4CHARISK1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB12->PCIE_LOGIC_OUTS_B10_R_7": { + "src_wire": "PCIE_DBGVECB12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA15->PCIE_LOGIC_OUTS_B6_R_15": { + "src_wire": "PCIE_PIPETX4DATA15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVSTATUSURDETECTED->PCIE_LOGIC_OUTS_B17_L_10": { + "src_wire": "PCIE_CFGDEVSTATUSURDETECTED", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_13->PCIE_CFGERRAERHEADERLOG21": { + "src_wire": "PCIE_IMUX12_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA10->PCIE_LOGIC_OUTS_B11_L_1": { + "src_wire": "PCIE_PIPETX3DATA10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPH5->PCIE_LOGIC_OUTS_B5_R_4": { + "src_wire": "PCIE_TRNFCPH5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_R_4->PCIE_PIPERX7STATUS2": { + "src_wire": "PCIE_IMUX35_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7STATUS2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1POWERDOWN1->PCIE_LOGIC_OUTS_B7_L_6": { + "src_wire": "PCIE_PIPETX1POWERDOWN1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA45->PCIE_LOGIC_OUTS_B17_R_18": { + "src_wire": "PCIE_MIMRXWDATA45", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLD10->PCIE_LOGIC_OUTS_B9_L_11": { + "src_wire": "PCIE_TRNFCCPLD10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD5->PCIE_LOGIC_OUTS_B9_L_6": { + "src_wire": "PCIE_TRNRD5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA53->PCIE_LOGIC_OUTS_B21_R_11": { + "src_wire": "PCIE_DBGVECA53", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_6->PCIE_CFGDSN4": { + "src_wire": "PCIE_IMUX11_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_16->PCIE_MIMRXRDATA6": { + "src_wire": "PCIE_IMUX2_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA21->PCIE_LOGIC_OUTS_B5_R_8": { + "src_wire": "PCIE_MIMTXWDATA21", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR38->PCIE_LOGIC_OUTS_B17_L_6": { + "src_wire": "PCIE_TL2ERRHDR38", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_18->PCIE_TRNTD42": { + "src_wire": "PCIE_IMUX12_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD42", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO0->PCIE_LOGIC_OUTS_B11_R_10": { + "src_wire": "PCIE_CFGMGMTDO0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLRECEIVEDHOTRST->PCIE_LOGIC_OUTS_B13_R_8": { + "src_wire": "PCIE_PLRECEIVEDHOTRST", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_R_8->PCIE_PIPERX5DATA11": { + "src_wire": "PCIE_IMUX32_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_R_4->PCIE_PIPERX7DATA10": { + "src_wire": "PCIE_IMUX33_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_16->PCIE_CFGERRTLPCPLHEADER12": { + "src_wire": "PCIE_IMUX6_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLLANEREVERSALMODE0->PCIE_LOGIC_OUTS_B13_L_0": { + "src_wire": "PCIE_PLLANEREVERSALMODE0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_3->PCIE_MIMTXRDATA50": { + "src_wire": "PCIE_IMUX4_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA50", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_6->PCIE_CFGSUBSYSID7": { + "src_wire": "PCIE_IMUX13_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_17->PCIE_CFGERRTLPCPLHEADER17": { + "src_wire": "PCIE_IMUX7_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR5->PCIE_LOGIC_OUTS_B12_R_11": { + "src_wire": "PCIE_TL2ERRHDR5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_3->PCIE_CFGPCIECAPINTERRUPTMSGNUM0": { + "src_wire": "PCIE_IMUX8_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA55->PCIE_LOGIC_OUTS_B19_R_10": { + "src_wire": "PCIE_DBGVECA55", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_R_15->PCIE_PIPERX6DATA9": { + "src_wire": "PCIE_IMUX36_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA48->PCIE_LOGIC_OUTS_B14_R_1": { + "src_wire": "PCIE_MIMTXWDATA48", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_R_10->PCIE_PIPERX5DATA0": { + "src_wire": "PCIE_IMUX37_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB23->PCIE_LOGIC_OUTS_B8_R_4": { + "src_wire": "PCIE_DBGVECB23", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD3->PCIE_LOGIC_OUTS_B5_L_6": { + "src_wire": "PCIE_TRNRD3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLPHYLNKUPN->PCIE_LOGIC_OUTS_B15_L_0": { + "src_wire": "PCIE_PLPHYLNKUPN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLMAXPAYLOAD1->PCIE_LOGIC_OUTS_B20_L_14": { + "src_wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWADDR6->PCIE_LOGIC_OUTS_B17_R_17": { + "src_wire": "PCIE_MIMRXWADDR6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_L_1->PCIE_CFGREVID2": { + "src_wire": "PCIE_IMUX14_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_18->PCIE_TRNTDLLPDATA14": { + "src_wire": "PCIE_IMUX3_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_L_10->PCIE_CFGSUBSYSVENDID3": { + "src_wire": "PCIE_IMUX15_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA5->PCIE_LOGIC_OUTS_B18_L_11": { + "src_wire": "PCIE_CFGMSGDATA5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_L_5->PCIE_PIPERX3DATA4": { + "src_wire": "PCIE_IMUX39_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR48->PCIE_LOGIC_OUTS_B9_L_9": { + "src_wire": "PCIE_TL2ERRHDR48", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_R_18->PCIE_CFGERRPOSTEDN": { + "src_wire": "PCIE_IMUX17_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRPOSTEDN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_14->PCIE_CFGDSN35": { + "src_wire": "PCIE_IMUX10_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN35", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA15->PCIE_LOGIC_OUTS_B11_L_15": { + "src_wire": "PCIE_TRNRDLLPDATA15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO5->PCIE_LOGIC_OUTS_B12_L_9": { + "src_wire": "PCIE_CFGINTERRUPTDO5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR10->PCIE_LOGIC_OUTS_B6_R_9": { + "src_wire": "PCIE_TL2ERRHDR10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_3->PCIE_MIMTXRDATA15": { + "src_wire": "PCIE_IMUX3_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLENABLERO->PCIE_LOGIC_OUTS_B18_L_14": { + "src_wire": "PCIE_CFGDEVCONTROLENABLERO", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_9->PCIE_CFGSUBSYSID14": { + "src_wire": "PCIE_IMUX12_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_0->PCIE_MIMTXRDATA1": { + "src_wire": "PCIE_IMUX1_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_7->PCIE_CFGERRAERHEADERLOG102": { + "src_wire": "PCIE_IMUX4_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG102", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_12->PCIE_TRNTD67": { + "src_wire": "PCIE_IMUX1_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD67", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_R_0->PCIE_CFGPORTNUMBER1": { + "src_wire": "PCIE_IMUX17_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_7->PCIE_MIMTXRDATA28": { + "src_wire": "PCIE_IMUX0_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXRADDR6->PCIE_LOGIC_OUTS_B9_R_19": { + "src_wire": "PCIE_MIMRXRADDR6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD43->PCIE_LOGIC_OUTS_B0_L_16": { + "src_wire": "PCIE_TRNRD43", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_0->PCIE_CFGERRAERHEADERLOG70": { + "src_wire": "PCIE_IMUX12_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG70", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA14->PCIE_LOGIC_OUTS_B12_L_15": { + "src_wire": "PCIE_CFGMSGDATA14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_19->PCIE_CFGDSN56": { + "src_wire": "PCIE_IMUX11_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN56", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_L_12->PCIE_CFGSUBSYSVENDID11": { + "src_wire": "PCIE_IMUX15_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMASNAK->PCIE_LOGIC_OUTS_B10_L_19": { + "src_wire": "PCIE_CFGMSGRECEIVEDPMASNAK", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWADDR7->PCIE_LOGIC_OUTS_B15_R_4": { + "src_wire": "PCIE_MIMTXWADDR7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5COMPLIANCE->PCIE_LOGIC_OUTS_B3_R_7": { + "src_wire": "PCIE_PIPETX5COMPLIANCE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR62->PCIE_LOGIC_OUTS_B14_L_12": { + "src_wire": "PCIE_TL2ERRHDR62", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_0->PCIE_PLDIRECTEDLTSSMNEW0": { + "src_wire": "PCIE_IMUX9_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLDBGVEC9->PCIE_LOGIC_OUTS_B20_R_7": { + "src_wire": "PCIE_PLDBGVEC9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA13->PCIE_LOGIC_OUTS_B4_R_0": { + "src_wire": "PCIE_PIPETX7DATA13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_R_8->PCIE_PIPERX5DATA9": { + "src_wire": "PCIE_IMUX36_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_4->PCIE_CFGERRAERHEADERLOG54": { + "src_wire": "PCIE_IMUX8_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG54", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNTBUFAV0->PCIE_LOGIC_OUTS_B4_L_3": { + "src_wire": "PCIE_TRNTBUFAV0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_7->PCIE_CFGSUBSYSID11": { + "src_wire": "PCIE_IMUX13_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_4->PCIE_CFGERRAERHEADERLOG56": { + "src_wire": "PCIE_IMUX10_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG56", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_14->PCIE_CFGDSN36": { + "src_wire": "PCIE_IMUX11_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN36", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA1->PCIE_LOGIC_OUTS_B13_R_7": { + "src_wire": "PCIE_PIPETX5DATA1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_3->PCIE_CFGERRAERHEADERLOG61": { + "src_wire": "PCIE_IMUX16_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG61", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_R_15->PCIE_PIPERX6ELECIDLE": { + "src_wire": "PCIE_IMUX34_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6ELECIDLE", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRBARHIT4->PCIE_LOGIC_OUTS_B1_R_8": { + "src_wire": "PCIE_TRNRBARHIT4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_5->PCIE_CFGERRAERHEADERLOG53": { + "src_wire": "PCIE_IMUX14_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG53", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA14->PCIE_LOGIC_OUTS_B10_L_15": { + "src_wire": "PCIE_TRNRDLLPDATA14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA51->PCIE_LOGIC_OUTS_B14_R_5": { + "src_wire": "PCIE_MIMTXWDATA51", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB45->PCIE_LOGIC_OUTS_B20_L_2": { + "src_wire": "PCIE_DBGVECB45", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_2->PCIE_CFGERRAERHEADERLOG85": { + "src_wire": "PCIE_IMUX7_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG85", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_13->PCIE_CFGDSN30": { + "src_wire": "PCIE_IMUX9_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_0->PCIE_PLDOWNSTREAMDEEMPHSOURCE": { + "src_wire": "PCIE_IMUX7_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDOWNSTREAMDEEMPHSOURCE", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_15->PCIE_TRNFCSEL2": { + "src_wire": "PCIE_IMUX0_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNFCSEL2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA0->PCIE_LOGIC_OUTS_B9_R_18": { + "src_wire": "PCIE_PIPETX4DATA0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD123->PCIE_LOGIC_OUTS_B10_R_13": { + "src_wire": "PCIE_TRNRD123", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD9->PCIE_LOGIC_OUTS_B4_L_7": { + "src_wire": "PCIE_TRNRD9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_0->PCIE_MIMTXRDATA62": { + "src_wire": "PCIE_IMUX4_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA62", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD20->PCIE_LOGIC_OUTS_B1_L_10": { + "src_wire": "PCIE_TRNRD20", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLH3->PCIE_LOGIC_OUTS_B8_L_7": { + "src_wire": "PCIE_TRNFCCPLH3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA17->PCIE_LOGIC_OUTS_B5_L_16": { + "src_wire": "PCIE_TRNRDLLPDATA17", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO2->PCIE_LOGIC_OUTS_B13_R_10": { + "src_wire": "PCIE_CFGMGMTDO2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA1->PCIE_LOGIC_OUTS_B13_R_14": { + "src_wire": "PCIE_PIPETX6DATA1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_L_19->PCIE_PIPERX0ELECIDLE": { + "src_wire": "PCIE_IMUX34_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0ELECIDLE", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD12->PCIE_LOGIC_OUTS_B1_L_8": { + "src_wire": "PCIE_TRNRD12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_R_4->PCIE_PIPERX7STATUS0": { + "src_wire": "PCIE_IMUX39_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7STATUS0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTMMENABLE2->PCIE_LOGIC_OUTS_B16_L_1": { + "src_wire": "PCIE_CFGINTERRUPTMMENABLE2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNTDSTRDY0->PCIE_LOGIC_OUTS_B1_R_10": { + "src_wire": "PCIE_TRNTDSTRDY0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNTBUFAV3->PCIE_LOGIC_OUTS_B3_L_4": { + "src_wire": "PCIE_TRNTBUFAV3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_L_17->PCIE_DRPADDR2": { + "src_wire": "PCIE_IMUX15_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA3->PCIE_LOGIC_OUTS_B15_R_7": { + "src_wire": "PCIE_PIPETX5DATA3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4CHARISK0->PCIE_LOGIC_OUTS_B16_R_17": { + "src_wire": "PCIE_PIPETX4CHARISK0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_10->PCIE_TRNTD76": { + "src_wire": "PCIE_IMUX2_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD76", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2CHARISK0->PCIE_LOGIC_OUTS_B16_L_13": { + "src_wire": "PCIE_PIPETX2CHARISK0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_9->PCIE_MIMTXRDATA39": { + "src_wire": "PCIE_IMUX3_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA39", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_9->PCIE_CFGERRAERHEADERLOG36": { + "src_wire": "PCIE_IMUX13_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG36", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_16->PCIE_TRNTDLLPDATA5": { + "src_wire": "PCIE_IMUX2_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5POWERDOWN1->PCIE_LOGIC_OUTS_B7_R_6": { + "src_wire": "PCIE_PIPETX5POWERDOWN1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB61->PCIE_LOGIC_OUTS_B20_L_6": { + "src_wire": "PCIE_DBGVECB61", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_14->PCIE_CFGERRAERHEADERLOG16": { + "src_wire": "PCIE_IMUX11_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_4->PCIE_CFGERRAERHEADERLOG92": { + "src_wire": "PCIE_IMUX6_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG92", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_R_3->PCIE_PIPERX7DATA13": { + "src_wire": "PCIE_IMUX38_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPD8->PCIE_LOGIC_OUTS_B7_L_5": { + "src_wire": "PCIE_TRNFCNPD8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_19->PCIE_CFGERRTLPCPLHEADER23": { + "src_wire": "PCIE_IMUX5_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA63->PCIE_LOGIC_OUTS_B10_R_3": { + "src_wire": "PCIE_MIMTXWDATA63", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_L_13->PCIE_CFGSUBSYSVENDID15": { + "src_wire": "PCIE_IMUX15_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD40->PCIE_LOGIC_OUTS_B3_L_15": { + "src_wire": "PCIE_TRNRD40", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_9->PCIE_MIMTXRDATA36": { + "src_wire": "PCIE_IMUX0_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA36", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPH6->PCIE_LOGIC_OUTS_B0_R_3": { + "src_wire": "PCIE_TRNFCPH6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_3->PCIE_TRNTD78": { + "src_wire": "PCIE_IMUX8_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD78", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA68->PCIE_LOGIC_OUTS_B5_R_2": { + "src_wire": "PCIE_MIMTXWDATA68", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_6->PCIE_TRNTD109": { + "src_wire": "PCIE_IMUX1_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD109", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_11->PCIE_CFGMGMTBYTEENN3": { + "src_wire": "PCIE_IMUX5_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTBYTEENN3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA1->PCIE_LOGIC_OUTS_B13_R_3": { + "src_wire": "PCIE_PIPETX7DATA1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLTXPMSTATE1->PCIE_LOGIC_OUTS_B18_L_0": { + "src_wire": "PCIE_PLTXPMSTATE1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD27->PCIE_LOGIC_OUTS_B0_L_12": { + "src_wire": "PCIE_TRNRD27", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_1->PCIE_TRNTD85": { + "src_wire": "PCIE_IMUX10_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD85", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_17->PCIE_TRNTDLLPDATA9": { + "src_wire": "PCIE_IMUX2_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_8->PCIE_CFGERRAERHEADERLOG40": { + "src_wire": "PCIE_IMUX11_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG40", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_14->PCIE_CFGMGMTWRREADONLYN": { + "src_wire": "PCIE_IMUX5_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTWRREADONLYN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTD->PCIE_LOGIC_OUTS_B19_L_17": { + "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTD", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLRXPMSTATE1->PCIE_LOGIC_OUTS_B1_L_1": { + "src_wire": "PCIE_PLRXPMSTATE1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLINITIALLINKWIDTH2->PCIE_LOGIC_OUTS_B10_L_2": { + "src_wire": "PCIE_PLINITIALLINKWIDTH2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLRXPMSTATE0->PCIE_LOGIC_OUTS_B0_L_1": { + "src_wire": "PCIE_PLRXPMSTATE0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_L_4->PCIE_PIPERX3STATUS0": { + "src_wire": "PCIE_IMUX39_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3STATUS0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGROOTCONTROLSYSERRFATALERREN->PCIE_LOGIC_OUTS_B22_L_18": { + "src_wire": "PCIE_CFGROOTCONTROLSYSERRFATALERREN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRBARHIT5->PCIE_LOGIC_OUTS_B2_R_8": { + "src_wire": "PCIE_TRNRBARHIT5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_10->PCIE_TRNTD75": { + "src_wire": "PCIE_IMUX1_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD75", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_L_8->PCIE_PIPERX1CHARISK1": { + "src_wire": "PCIE_IMUX16_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1CHARISK1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_13->PCIE_CFGERRAERHEADERLOG126": { + "src_wire": "PCIE_IMUX4_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG126", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_L_3->PCIE_PIPERX3DATA14": { + "src_wire": "PCIE_IMUX35_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_L_15->PCIE_PIPERX2ELECIDLE": { + "src_wire": "PCIE_IMUX34_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2ELECIDLE", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_14->PCIE_TRNTD58": { + "src_wire": "PCIE_IMUX0_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD58", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA14->PCIE_LOGIC_OUTS_B2_L_15": { + "src_wire": "PCIE_PIPETX0DATA14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_USERRSTN->PCIE_LOGIC_OUTS_B12_R_8": { + "src_wire": "PCIE_USERRSTN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_R_4->PCIE_PIPERX7DATA11": { + "src_wire": "PCIE_IMUX32_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA9->PCIE_LOGIC_OUTS_B13_L_16": { + "src_wire": "PCIE_PIPETX0DATA9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA61->PCIE_LOGIC_OUTS_B21_R_9": { + "src_wire": "PCIE_DBGVECA61", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA0->PCIE_LOGIC_OUTS_B9_R_14": { + "src_wire": "PCIE_PIPETX6DATA0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR1->PCIE_LOGIC_OUTS_B7_R_12": { + "src_wire": "PCIE_TL2ERRHDR1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_1->PCIE_CFGPMHALTASPML1N": { + "src_wire": "PCIE_IMUX9_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMHALTASPML1N", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LL2LINKSTATUS3->PCIE_LOGIC_OUTS_B4_R_16": { + "src_wire": "PCIE_LL2LINKSTATUS3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA13->PCIE_LOGIC_OUTS_B4_L_4": { + "src_wire": "PCIE_PIPETX1DATA13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_2->PCIE_MIMTXRDATA57": { + "src_wire": "PCIE_IMUX7_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA57", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CLK1_R_11->PCIE_DRPCLK": { + "src_wire": "PCIE_CLK1_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPCLK", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLLANEREVERSALMODE1->PCIE_LOGIC_OUTS_B14_L_0": { + "src_wire": "PCIE_PLLANEREVERSALMODE1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LL2BADTLPERR->PCIE_LOGIC_OUTS_B13_R_13": { + "src_wire": "PCIE_LL2BADTLPERR", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_11->PCIE_CFGERRAERHEADERLOG119": { + "src_wire": "PCIE_IMUX5_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG119", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPH0->PCIE_LOGIC_OUTS_B7_L_1": { + "src_wire": "PCIE_TRNFCNPH0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_17->PCIE_TRNTD48": { + "src_wire": "PCIE_IMUX10_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD48", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPH4->PCIE_LOGIC_OUTS_B4_R_5": { + "src_wire": "PCIE_TRNFCPH4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_R_5->PCIE_PIPERX7DATA6": { + "src_wire": "PCIE_IMUX35_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA7->PCIE_LOGIC_OUTS_B6_R_17": { + "src_wire": "PCIE_PIPETX4DATA7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLD5->PCIE_LOGIC_OUTS_B4_L_10": { + "src_wire": "PCIE_TRNFCCPLD5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWADDR7->PCIE_LOGIC_OUTS_B11_R_19": { + "src_wire": "PCIE_MIMRXWADDR7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_8->PCIE_TRNTD117": { + "src_wire": "PCIE_IMUX1_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD117", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_R_1->PCIE_CFGERRAERHEADERLOG69": { + "src_wire": "PCIE_IMUX15_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG69", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPH1->PCIE_LOGIC_OUTS_B6_R_7": { + "src_wire": "PCIE_TRNFCPH1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLD2->PCIE_LOGIC_OUTS_B5_L_9": { + "src_wire": "PCIE_TRNFCCPLD2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGSCLRF->PCIE_LOGIC_OUTS_B21_L_11": { + "src_wire": "PCIE_DBGSCLRF", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_7->PCIE_CFGDSN6": { + "src_wire": "PCIE_IMUX9_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LL2LINKSTATUS2->PCIE_LOGIC_OUTS_B3_R_16": { + "src_wire": "PCIE_LL2LINKSTATUS2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_18->PCIE_MIMRXRDATA14": { + "src_wire": "PCIE_IMUX2_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_9->PCIE_CFGSUBSYSID15": { + "src_wire": "PCIE_IMUX13_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECC9->PCIE_LOGIC_OUTS_B20_L_9": { + "src_wire": "PCIE_DBGVECC9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_12->PCIE_CFGDSBUSNUMBER0": { + "src_wire": "PCIE_IMUX14_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_11->PCIE_CFGDSBUSNUMBER4": { + "src_wire": "PCIE_IMUX14_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_R_6->PCIE_CFGERRAERHEADERLOG49": { + "src_wire": "PCIE_IMUX17_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG49", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA29->PCIE_LOGIC_OUTS_B5_L_19": { + "src_wire": "PCIE_TRNRDLLPDATA29", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_0->PCIE_TRNTD88": { + "src_wire": "PCIE_IMUX9_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD88", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD115->PCIE_LOGIC_OUTS_B8_R_15": { + "src_wire": "PCIE_TRNRD115", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_L_18->PCIE_PIPERX0DATA13": { + "src_wire": "PCIE_IMUX38_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_2->PCIE_TRNTD95": { + "src_wire": "PCIE_IMUX3_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD95", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA3->PCIE_LOGIC_OUTS_B7_L_12": { + "src_wire": "PCIE_TRNRDLLPDATA3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_9->PCIE_TRNTD121": { + "src_wire": "PCIE_IMUX1_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD121", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6POWERDOWN1->PCIE_LOGIC_OUTS_B7_R_13": { + "src_wire": "PCIE_PIPETX6POWERDOWN1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_13->PCIE_CFGDSN29": { + "src_wire": "PCIE_IMUX8_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_R_4->PCIE_PIPERX7DATA9": { + "src_wire": "PCIE_IMUX36_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD57->PCIE_LOGIC_OUTS_B2_L_19": { + "src_wire": "PCIE_TRNRD57", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD34->PCIE_LOGIC_OUTS_B10_L_13": { + "src_wire": "PCIE_TRNRD34", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD42->PCIE_LOGIC_OUTS_B7_L_15": { + "src_wire": "PCIE_TRNRD42", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0POWERDOWN1->PCIE_LOGIC_OUTS_B7_L_17": { + "src_wire": "PCIE_PIPETX0POWERDOWN1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPD6->PCIE_LOGIC_OUTS_B5_L_5": { + "src_wire": "PCIE_TRNFCNPD6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB11->PCIE_LOGIC_OUTS_B18_R_8": { + "src_wire": "PCIE_DBGVECB11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CTRL1_R_0->PCIE_CMRSTN": { + "src_wire": "PCIE_CTRL1_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CMRSTN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_5->PCIE_CFGFORCEMPS2": { + "src_wire": "PCIE_IMUX8_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGFORCEMPS2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_3->PCIE_CFGPCIECAPINTERRUPTMSGNUM2": { + "src_wire": "PCIE_IMUX10_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_11->PCIE_CFGSUBSYSVENDID4": { + "src_wire": "PCIE_IMUX12_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_5->PCIE_CFGFORCEEXTENDEDSYNCON": { + "src_wire": "PCIE_IMUX10_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGFORCEEXTENDEDSYNCON", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA62->PCIE_LOGIC_OUTS_B19_R_16": { + "src_wire": "PCIE_MIMRXWDATA62", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_L_17->PCIE_DRPADDR1": { + "src_wire": "PCIE_IMUX14_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRBARHIT7->PCIE_LOGIC_OUTS_B6_R_8": { + "src_wire": "PCIE_TRNRBARHIT7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_10->PCIE_TRNTD74": { + "src_wire": "PCIE_IMUX0_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD74", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_10->PCIE_CFGSUBSYSVENDID0": { + "src_wire": "PCIE_IMUX12_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLNOSNOOPEN->PCIE_LOGIC_OUTS_B20_L_15": { + "src_wire": "PCIE_CFGDEVCONTROLNOSNOOPEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4ELECIDLE->PCIE_LOGIC_OUTS_B3_R_17": { + "src_wire": "PCIE_PIPETX4ELECIDLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_3->PCIE_MIMTXRDATA53": { + "src_wire": "PCIE_IMUX7_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA53", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_17->PCIE_TRNTD47": { + "src_wire": "PCIE_IMUX9_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD47", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_2->PCIE_TRNTD94": { + "src_wire": "PCIE_IMUX2_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD94", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXRADDR12->PCIE_LOGIC_OUTS_B8_R_7": { + "src_wire": "PCIE_MIMTXRADDR12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB57->PCIE_LOGIC_OUTS_B20_L_5": { + "src_wire": "PCIE_DBGVECB57", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR16->PCIE_LOGIC_OUTS_B9_R_8": { + "src_wire": "PCIE_TL2ERRHDR16", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVSTATUSNONFATALERRDETECTED->PCIE_LOGIC_OUTS_B17_L_9": { + "src_wire": "PCIE_CFGDEVSTATUSNONFATALERRDETECTED", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA3->PCIE_LOGIC_OUTS_B15_L_7": { + "src_wire": "PCIE_PIPETX1DATA3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA6->PCIE_LOGIC_OUTS_B20_R_5": { + "src_wire": "PCIE_MIMTXWDATA6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_0->PCIE_MIMTXRDATA3": { + "src_wire": "PCIE_IMUX3_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_2->PCIE_MIMTXRDATA56": { + "src_wire": "PCIE_IMUX6_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA56", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA24->PCIE_LOGIC_OUTS_B23_R_19": { + "src_wire": "PCIE_DBGVECA24", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_18->PCIE_CFGERRTLPCPLHEADER19": { + "src_wire": "PCIE_IMUX5_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD11->PCIE_LOGIC_OUTS_B0_L_8": { + "src_wire": "PCIE_TRNRD11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_14->PCIE_CFGMGMTRDENN": { + "src_wire": "PCIE_IMUX7_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTRDENN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA8->PCIE_LOGIC_OUTS_B9_L_16": { + "src_wire": "PCIE_PIPETX0DATA8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWADDR3->PCIE_LOGIC_OUTS_B23_R_5": { + "src_wire": "PCIE_MIMTXWADDR3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_13->PCIE_CFGINTERRUPTDI5": { + "src_wire": "PCIE_IMUX13_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_15->PCIE_MIMRXRDATA0": { + "src_wire": "PCIE_IMUX0_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_8->PCIE_CFGERRAERHEADERLOG41": { + "src_wire": "PCIE_IMUX12_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG41", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_1->PCIE_CFGERRAERHEADERLOG79": { + "src_wire": "PCIE_IMUX5_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG79", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLINITIALLINKWIDTH1->PCIE_LOGIC_OUTS_B9_L_2": { + "src_wire": "PCIE_PLINITIALLINKWIDTH1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_0->PCIE_PLDIRECTEDLTSSMNEW1": { + "src_wire": "PCIE_IMUX10_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA12->PCIE_LOGIC_OUTS_B0_R_0": { + "src_wire": "PCIE_PIPETX7DATA12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR51->PCIE_LOGIC_OUTS_B8_L_10": { + "src_wire": "PCIE_TL2ERRHDR51", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR27->PCIE_LOGIC_OUTS_B16_L_3": { + "src_wire": "PCIE_TL2ERRHDR27", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA1->PCIE_LOGIC_OUTS_B5_L_12": { + "src_wire": "PCIE_TRNRDLLPDATA1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLTXPMSTATE2->PCIE_LOGIC_OUTS_B19_L_0": { + "src_wire": "PCIE_PLTXPMSTATE2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA4->PCIE_LOGIC_OUTS_B0_R_17": { + "src_wire": "PCIE_PIPETX4DATA4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_16->PCIE_CFGDSN42": { + "src_wire": "PCIE_IMUX9_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN42", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_15->PCIE_CFGERRTLPCPLHEADER6": { + "src_wire": "PCIE_IMUX4_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLPHANTOMEN->PCIE_LOGIC_OUTS_B18_L_15": { + "src_wire": "PCIE_CFGDEVCONTROLPHANTOMEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR9->PCIE_LOGIC_OUTS_B9_R_10": { + "src_wire": "PCIE_TL2ERRHDR9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_5->PCIE_MIMTXRDATA49": { + "src_wire": "PCIE_IMUX5_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA49", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_3->PCIE_MIMTXRDATA13": { + "src_wire": "PCIE_IMUX1_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB36->PCIE_LOGIC_OUTS_B20_L_0": { + "src_wire": "PCIE_DBGVECB36", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_2->PCIE_CFGMGMTDI1": { + "src_wire": "PCIE_IMUX14_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD117->PCIE_LOGIC_OUTS_B2_R_14": { + "src_wire": "PCIE_TRNRD117", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR46->PCIE_LOGIC_OUTS_B11_L_8": { + "src_wire": "PCIE_TL2ERRHDR46", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR53->PCIE_LOGIC_OUTS_B10_L_10": { + "src_wire": "PCIE_TL2ERRHDR53", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD53->PCIE_LOGIC_OUTS_B4_L_18": { + "src_wire": "PCIE_TRNRD53", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX19_R_2->PCIE_CFGERRAERHEADERLOG65": { + "src_wire": "PCIE_IMUX19_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG65", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPH2->PCIE_LOGIC_OUTS_B2_R_5": { + "src_wire": "PCIE_TRNFCPH2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_14->PCIE_CFGERRAERHEADERLOG17": { + "src_wire": "PCIE_IMUX12_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLD8->PCIE_LOGIC_OUTS_B7_L_10": { + "src_wire": "PCIE_TRNFCCPLD8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_L_17->PCIE_PIPERX2DATA2": { + "src_wire": "PCIE_IMUX33_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRBARHIT3->PCIE_LOGIC_OUTS_B3_R_9": { + "src_wire": "PCIE_TRNRBARHIT3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB31->PCIE_LOGIC_OUTS_B13_R_2": { + "src_wire": "PCIE_DBGVECB31", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_18->PCIE_DRPADDR3": { + "src_wire": "PCIE_IMUX12_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD41->PCIE_LOGIC_OUTS_B5_L_15": { + "src_wire": "PCIE_TRNRD41", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR17->PCIE_LOGIC_OUTS_B11_R_8": { + "src_wire": "PCIE_TL2ERRHDR17", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD16->PCIE_LOGIC_OUTS_B1_L_9": { + "src_wire": "PCIE_TRNRD16", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_0->PCIE_PLDIRECTEDLINKAUTON": { + "src_wire": "PCIE_IMUX5_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLINKAUTON", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_R_7->PCIE_CFGERRAERHEADERLOG45": { + "src_wire": "PCIE_IMUX17_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG45", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA2->PCIE_LOGIC_OUTS_B11_R_7": { + "src_wire": "PCIE_PIPETX5DATA2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_14->PCIE_CFGAERINTERRUPTMSGNUM1": { + "src_wire": "PCIE_IMUX13_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA5->PCIE_LOGIC_OUTS_B4_R_2": { + "src_wire": "PCIE_PIPETX7DATA5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA5->PCIE_LOGIC_OUTS_B4_R_6": { + "src_wire": "PCIE_PIPETX5DATA5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_3->PCIE_CFGSUBSYSID1": { + "src_wire": "PCIE_IMUX13_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_4->PCIE_MIMTXRDATA17": { + "src_wire": "PCIE_IMUX1_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_L_18->PCIE_PIPERX0DATA14": { + "src_wire": "PCIE_IMUX35_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_19->PCIE_TRNTD4": { + "src_wire": "PCIE_IMUX8_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA2->PCIE_LOGIC_OUTS_B11_L_3": { + "src_wire": "PCIE_PIPETX3DATA2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_4->PCIE_MIMTXRDATA16": { + "src_wire": "PCIE_IMUX0_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWADDR11->PCIE_LOGIC_OUTS_B2_R_3": { + "src_wire": "PCIE_MIMTXWADDR11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB32->PCIE_LOGIC_OUTS_B15_R_2": { + "src_wire": "PCIE_DBGVECB32", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX19_R_1->PCIE_CFGDSFUNCTIONNUMBER2": { + "src_wire": "PCIE_IMUX19_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSFUNCTIONNUMBER2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3->PCIE_LOGIC_OUTS_B20_L_18": { + "src_wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_17->PCIE_TRNTDLLPDATA10": { + "src_wire": "PCIE_IMUX3_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_L_9->PCIE_PIPERX1CHANISALIGNED": { + "src_wire": "PCIE_IMUX33_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1CHANISALIGNED", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPERX3POLARITY->PCIE_LOGIC_OUTS_B1_L_3": { + "src_wire": "PCIE_PIPERX3POLARITY", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA4->PCIE_LOGIC_OUTS_B0_R_13": { + "src_wire": "PCIE_PIPETX6DATA4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWADDR6->PCIE_LOGIC_OUTS_B11_R_2": { + "src_wire": "PCIE_MIMTXWADDR6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPD0->PCIE_LOGIC_OUTS_B10_L_3": { + "src_wire": "PCIE_TRNFCNPD0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPERX6POLARITY->PCIE_LOGIC_OUTS_B1_R_14": { + "src_wire": "PCIE_PIPERX6POLARITY", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPERX2POLARITY->PCIE_LOGIC_OUTS_B1_L_14": { + "src_wire": "PCIE_PIPERX2POLARITY", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLH1->PCIE_LOGIC_OUTS_B6_L_7": { + "src_wire": "PCIE_TRNFCCPLH1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA36->PCIE_LOGIC_OUTS_B11_R_0": { + "src_wire": "PCIE_MIMTXWDATA36", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA2->PCIE_LOGIC_OUTS_B14_L_10": { + "src_wire": "PCIE_CFGMSGDATA2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_L_10->PCIE_CFGSUBSYSVENDID2": { + "src_wire": "PCIE_IMUX14_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CTRL0_R_2->PCIE_TLRSTN": { + "src_wire": "PCIE_CTRL0_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TLRSTN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_9->PCIE_TRNTD120": { + "src_wire": "PCIE_IMUX0_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD120", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_19->PCIE_PIPERX4CHARISK1": { + "src_wire": "PCIE_IMUX16_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4CHARISK1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA7->PCIE_LOGIC_OUTS_B19_R_8": { + "src_wire": "PCIE_MIMTXWDATA7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_15->PCIE_TRNTD54": { + "src_wire": "PCIE_IMUX4_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD54", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX20_L_0->PCIE_CFGPORTNUMBER7": { + "src_wire": "PCIE_IMUX20_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA9->PCIE_LOGIC_OUTS_B13_R_12": { + "src_wire": "PCIE_PIPETX6DATA9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_1->PCIE_PLDIRECTEDLTSSMNEW5": { + "src_wire": "PCIE_IMUX1_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA11->PCIE_LOGIC_OUTS_B14_L_14": { + "src_wire": "PCIE_CFGMSGDATA11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA54->PCIE_LOGIC_OUTS_B18_R_10": { + "src_wire": "PCIE_DBGVECA54", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_1->PCIE_TRNTD83": { + "src_wire": "PCIE_IMUX8_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD83", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_18->PCIE_DRPADDR4": { + "src_wire": "PCIE_IMUX13_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGLINKCONTROLASPMCONTROL0->PCIE_LOGIC_OUTS_B15_L_19": { + "src_wire": "PCIE_CFGLINKCONTROLASPMCONTROL0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA5->PCIE_LOGIC_OUTS_B4_L_2": { + "src_wire": "PCIE_PIPETX3DATA5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2->PCIE_LOGIC_OUTS_B19_L_18": { + "src_wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_15->PCIE_CFGERRECRCN": { + "src_wire": "PCIE_IMUX11_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRECRCN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_R_4->PCIE_PIPERX7DATA8": { + "src_wire": "PCIE_IMUX37_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPD9->PCIE_LOGIC_OUTS_B4_L_1": { + "src_wire": "PCIE_TRNFCPD9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_7->PCIE_CFGERRAERHEADERLOG44": { + "src_wire": "PCIE_IMUX16_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG44", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLSELLNKWIDTH1->PCIE_LOGIC_OUTS_B5_L_0": { + "src_wire": "PCIE_PLSELLNKWIDTH1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_2->PCIE_TRNTD80": { + "src_wire": "PCIE_IMUX9_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD80", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DRPDO7->PCIE_LOGIC_OUTS_B20_L_19": { + "src_wire": "PCIE_DRPDO7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR11->PCIE_LOGIC_OUTS_B9_R_9": { + "src_wire": "PCIE_TL2ERRHDR11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTMMENABLE1->PCIE_LOGIC_OUTS_B17_R_10": { + "src_wire": "PCIE_CFGINTERRUPTMMENABLE1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7CHARISK1->PCIE_LOGIC_OUTS_B16_R_0": { + "src_wire": "PCIE_PIPETX7CHARISK1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD125->PCIE_LOGIC_OUTS_B1_R_12": { + "src_wire": "PCIE_TRNRD125", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA0->PCIE_LOGIC_OUTS_B9_L_14": { + "src_wire": "PCIE_PIPETX2DATA0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA46->PCIE_LOGIC_OUTS_B23_R_16": { + "src_wire": "PCIE_MIMRXWDATA46", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_3->PCIE_TRNTD97": { + "src_wire": "PCIE_IMUX1_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD97", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_17->PCIE_MIMRXRDATA8": { + "src_wire": "PCIE_IMUX0_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA11->PCIE_LOGIC_OUTS_B10_L_14": { + "src_wire": "PCIE_TRNRDLLPDATA11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_L_6->PCIE_PIPERX3DATA3": { + "src_wire": "PCIE_IMUX32_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_R_14->PCIE_PIPERX6DATA13": { + "src_wire": "PCIE_IMUX38_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA44->PCIE_LOGIC_OUTS_B18_R_16": { + "src_wire": "PCIE_MIMRXWDATA44", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA10->PCIE_LOGIC_OUTS_B12_L_14": { + "src_wire": "PCIE_CFGMSGDATA10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB0->PCIE_LOGIC_OUTS_B16_R_8": { + "src_wire": "PCIE_DBGVECB0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_R_5->PCIE_PIPERX7DATA5": { + "src_wire": "PCIE_IMUX38_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_4->PCIE_CFGMGMTDI7": { + "src_wire": "PCIE_IMUX4_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA8->PCIE_LOGIC_OUTS_B9_L_1": { + "src_wire": "PCIE_PIPETX3DATA8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CTRL0_R_1->PCIE_CMSTICKYRSTN": { + "src_wire": "PCIE_CTRL0_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CMSTICKYRSTN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB60->PCIE_LOGIC_OUTS_B19_L_6": { + "src_wire": "PCIE_DBGVECB60", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_L_14->PCIE_PIPERX2DATA15": { + "src_wire": "PCIE_IMUX34_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_16->PCIE_TRNTD53": { + "src_wire": "PCIE_IMUX7_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD53", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD10->PCIE_LOGIC_OUTS_B5_L_7": { + "src_wire": "PCIE_TRNRD10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4POWERDOWN1->PCIE_LOGIC_OUTS_B7_R_17": { + "src_wire": "PCIE_PIPETX4POWERDOWN1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB14->PCIE_LOGIC_OUTS_B17_R_7": { + "src_wire": "PCIE_DBGVECB14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB38->PCIE_LOGIC_OUTS_B22_L_0": { + "src_wire": "PCIE_DBGVECB38", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_5->PCIE_TRNTD107": { + "src_wire": "PCIE_IMUX3_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD107", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX20_R_11->PCIE_CFGVENDID13": { + "src_wire": "PCIE_IMUX20_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRNONFATAL->PCIE_LOGIC_OUTS_B15_L_15": { + "src_wire": "PCIE_CFGMSGRECEIVEDERRNONFATAL", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA58->PCIE_LOGIC_OUTS_B15_R_15": { + "src_wire": "PCIE_MIMRXWDATA58", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB4->PCIE_LOGIC_OUTS_B22_R_11": { + "src_wire": "PCIE_DBGVECB4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_7->PCIE_CFGERRAERHEADERLOG103": { + "src_wire": "PCIE_IMUX5_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG103", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB56->PCIE_LOGIC_OUTS_B19_L_5": { + "src_wire": "PCIE_DBGVECB56", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_7->PCIE_CFGERRAERHEADERLOG42": { + "src_wire": "PCIE_IMUX14_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG42", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_16->PCIE_CFGDSN41": { + "src_wire": "PCIE_IMUX8_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN41", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_0->PCIE_CFGERRAERHEADERLOG72": { + "src_wire": "PCIE_IMUX14_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG72", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_19->PCIE_MIMRXRDATA16": { + "src_wire": "PCIE_IMUX0_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX18_R_1->PCIE_CFGDSFUNCTIONNUMBER1": { + "src_wire": "PCIE_IMUX18_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSFUNCTIONNUMBER1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_13->PCIE_CFGERRAERHEADERLOG20": { + "src_wire": "PCIE_IMUX11_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA9->PCIE_LOGIC_OUTS_B13_R_5": { + "src_wire": "PCIE_PIPETX5DATA9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLH6->PCIE_LOGIC_OUTS_B5_L_8": { + "src_wire": "PCIE_TRNFCCPLH6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_5->PCIE_CFGMGMTDI12": { + "src_wire": "PCIE_IMUX8_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA57->PCIE_LOGIC_OUTS_B5_R_19": { + "src_wire": "PCIE_MIMRXWDATA57", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA3->PCIE_LOGIC_OUTS_B15_R_3": { + "src_wire": "PCIE_PIPETX7DATA3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB54->PCIE_LOGIC_OUTS_B21_L_4": { + "src_wire": "PCIE_DBGVECB54", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_R_10->PCIE_CFGDSDEVICENUMBER1": { + "src_wire": "PCIE_IMUX15_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSDEVICENUMBER1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_9->PCIE_CFGMGMTDI28": { + "src_wire": "PCIE_IMUX8_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB41->PCIE_LOGIC_OUTS_B20_L_1": { + "src_wire": "PCIE_DBGVECB41", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR50->PCIE_LOGIC_OUTS_B11_L_9": { + "src_wire": "PCIE_TL2ERRHDR50", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_R_8->PCIE_PIPERX5DATA8": { + "src_wire": "PCIE_IMUX37_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_15->PCIE_CFGDSN37": { + "src_wire": "PCIE_IMUX8_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN37", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_1->PCIE_CFGPMFORCESTATE0": { + "src_wire": "PCIE_IMUX11_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMFORCESTATE0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD50->PCIE_LOGIC_OUTS_B10_L_17": { + "src_wire": "PCIE_TRNRD50", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA14->PCIE_LOGIC_OUTS_B2_R_4": { + "src_wire": "PCIE_PIPETX5DATA14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CTRL1_R_2->PCIE_DLRSTN": { + "src_wire": "PCIE_CTRL1_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_DLRSTN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD119->PCIE_LOGIC_OUTS_B5_R_14": { + "src_wire": "PCIE_TRNRD119", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA13->PCIE_LOGIC_OUTS_B4_L_11": { + "src_wire": "PCIE_PIPETX2DATA13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_5->PCIE_CFGMGMTDI14": { + "src_wire": "PCIE_IMUX10_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_R_14->PCIE_PIPERX6DATA14": { + "src_wire": "PCIE_IMUX35_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_17->PCIE_CFGERRMCBLOCKEDN": { + "src_wire": "PCIE_IMUX14_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRMCBLOCKEDN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_R_8->PCIE_PIPERX5STATUS0": { + "src_wire": "PCIE_IMUX39_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5STATUS0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_8->PCIE_CFGMGMTDI26": { + "src_wire": "PCIE_IMUX8_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA31->PCIE_LOGIC_OUTS_B7_L_19": { + "src_wire": "PCIE_TRNRDLLPDATA31", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_7->PCIE_CFGDSN7": { + "src_wire": "PCIE_IMUX10_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA52->PCIE_LOGIC_OUTS_B18_R_15": { + "src_wire": "PCIE_MIMRXWDATA52", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_16->PCIE_MIMRXRDATA4": { + "src_wire": "PCIE_IMUX0_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_16->PCIE_TRNTD51": { + "src_wire": "PCIE_IMUX5_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD51", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_4->PCIE_MIMTXRDATA18": { + "src_wire": "PCIE_IMUX2_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_L_3->PCIE_CFGSUBSYSID3": { + "src_wire": "PCIE_IMUX15_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_4->PCIE_CFGMGMTDI8": { + "src_wire": "PCIE_IMUX5_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_8->PCIE_MIMTXRDATA32": { + "src_wire": "PCIE_IMUX0_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA32", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECC8->PCIE_LOGIC_OUTS_B19_L_9": { + "src_wire": "PCIE_DBGVECC8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_R_7->PCIE_PIPERX5DATA14": { + "src_wire": "PCIE_IMUX35_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA14->PCIE_LOGIC_OUTS_B2_L_11": { + "src_wire": "PCIE_PIPETX2DATA14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_13->PCIE_TRNTCFGGNT": { + "src_wire": "PCIE_IMUX1_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTCFGGNT", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD6->PCIE_LOGIC_OUTS_B10_L_6": { + "src_wire": "PCIE_TRNRD6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECC10->PCIE_LOGIC_OUTS_B21_L_9": { + "src_wire": "PCIE_DBGVECC10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA10->PCIE_LOGIC_OUTS_B11_L_5": { + "src_wire": "PCIE_PIPETX1DATA10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_1->PCIE_CFGERRAERHEADERLOG67": { + "src_wire": "PCIE_IMUX13_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG67", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_5->PCIE_CFGMGMTDI11": { + "src_wire": "PCIE_IMUX7_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA55->PCIE_LOGIC_OUTS_B12_R_18": { + "src_wire": "PCIE_MIMRXWDATA55", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGROOTCONTROLSYSERRNONFATALERREN->PCIE_LOGIC_OUTS_B21_L_16": { + "src_wire": "PCIE_CFGROOTCONTROLSYSERRNONFATALERREN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_0->PCIE_MIMTXRDATA2": { + "src_wire": "PCIE_IMUX2_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_6->PCIE_PIPERX7CHARISK0": { + "src_wire": "PCIE_IMUX16_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7CHARISK0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA7->PCIE_LOGIC_OUTS_B6_R_13": { + "src_wire": "PCIE_PIPETX6DATA7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_R_19->PCIE_PIPERX4STATUS2": { + "src_wire": "PCIE_IMUX35_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4STATUS2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_L_4->PCIE_PIPERX3STATUS2": { + "src_wire": "PCIE_IMUX35_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3STATUS2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLINITIALLINKWIDTH0->PCIE_LOGIC_OUTS_B8_L_2": { + "src_wire": "PCIE_PLINITIALLINKWIDTH0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B20_L_13": { + "src_wire": "PCIE_CFGDEVCONTROLFATALERRREPORTINGEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_0->PCIE_PLUPSTREAMPREFERDEEMPH": { + "src_wire": "PCIE_IMUX6_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_PLUPSTREAMPREFERDEEMPH", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD32->PCIE_LOGIC_OUTS_B8_L_13": { + "src_wire": "PCIE_TRNRD32", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR8->PCIE_LOGIC_OUTS_B8_R_10": { + "src_wire": "PCIE_TL2ERRHDR8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_6->PCIE_CFGDSN2": { + "src_wire": "PCIE_IMUX9_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA6->PCIE_LOGIC_OUTS_B2_L_13": { + "src_wire": "PCIE_PIPETX2DATA6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_10->PCIE_CFGMGMTDI31": { + "src_wire": "PCIE_IMUX5_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_15->PCIE_CFGERRTLPCPLHEADER8": { + "src_wire": "PCIE_IMUX6_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB28->PCIE_LOGIC_OUTS_B16_R_3": { + "src_wire": "PCIE_DBGVECB28", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_12->PCIE_TRNTSRCDSC": { + "src_wire": "PCIE_IMUX1_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTSRCDSC", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA32->PCIE_LOGIC_OUTS_B2_R_16": { + "src_wire": "PCIE_DBGVECA32", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_6->PCIE_CFGMGMTDI17": { + "src_wire": "PCIE_IMUX11_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LL2TXIDLE->PCIE_LOGIC_OUTS_B13_R_17": { + "src_wire": "PCIE_LL2TXIDLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR28->PCIE_LOGIC_OUTS_B17_L_3": { + "src_wire": "PCIE_TL2ERRHDR28", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGSCLRI->PCIE_LOGIC_OUTS_B23_L_12": { + "src_wire": "PCIE_DBGSCLRI", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_14->PCIE_TRNFCSEL0": { + "src_wire": "PCIE_IMUX2_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNFCSEL0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRFCPE->PCIE_LOGIC_OUTS_B19_L_13": { + "src_wire": "PCIE_TL2ERRFCPE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_1->PCIE_MIMTXRDATA58": { + "src_wire": "PCIE_IMUX4_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA58", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_3->PCIE_MIMTXRDATA12": { + "src_wire": "PCIE_IMUX0_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA1->PCIE_LOGIC_OUTS_B13_L_3": { + "src_wire": "PCIE_PIPETX3DATA1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_3->PCIE_CFGERRAERHEADERLOG89": { + "src_wire": "PCIE_IMUX7_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG89", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_L_3->PCIE_PIPERX3DATA12": { + "src_wire": "PCIE_IMUX39_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA15->PCIE_LOGIC_OUTS_B6_R_4": { + "src_wire": "PCIE_PIPETX5DATA15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_15->PCIE_CFGDSN38": { + "src_wire": "PCIE_IMUX9_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN38", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_11->PCIE_CFGDSN22": { + "src_wire": "PCIE_IMUX9_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA16->PCIE_LOGIC_OUTS_B0_R_19": { + "src_wire": "PCIE_MIMRXWDATA16", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA3->PCIE_LOGIC_OUTS_B15_L_10": { + "src_wire": "PCIE_CFGMSGDATA3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB8->PCIE_LOGIC_OUTS_B22_R_15": { + "src_wire": "PCIE_DBGVECB8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA42->PCIE_LOGIC_OUTS_B14_R_15": { + "src_wire": "PCIE_MIMRXWDATA42", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR33->PCIE_LOGIC_OUTS_B8_L_5": { + "src_wire": "PCIE_TL2ERRHDR33", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA39->PCIE_LOGIC_OUTS_B23_R_17": { + "src_wire": "PCIE_MIMRXWDATA39", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_2->PCIE_CFGERRAERHEADERLOG83": { + "src_wire": "PCIE_IMUX5_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG83", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA45->PCIE_LOGIC_OUTS_B17_R_3": { + "src_wire": "PCIE_MIMTXWDATA45", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_6->PCIE_CFGDSN1": { + "src_wire": "PCIE_IMUX8_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD55->PCIE_LOGIC_OUTS_B0_L_19": { + "src_wire": "PCIE_TRNRD55", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_2->PCIE_MIMTXRDATA9": { + "src_wire": "PCIE_IMUX1_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_4->PCIE_CFGERRAERHEADERLOG93": { + "src_wire": "PCIE_IMUX7_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG93", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD46->PCIE_LOGIC_OUTS_B3_L_16": { + "src_wire": "PCIE_TRNRD46", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLDBGVEC4->PCIE_LOGIC_OUTS_B23_L_16": { + "src_wire": "PCIE_PLDBGVEC4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_13->PCIE_CFGERRAERHEADERLOG19": { + "src_wire": "PCIE_IMUX10_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA7->PCIE_LOGIC_OUTS_B6_R_2": { + "src_wire": "PCIE_PIPETX7DATA7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_R_19->PCIE_PIPERX4STATUS1": { + "src_wire": "PCIE_IMUX38_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4STATUS1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_9->PCIE_CFGERRAERHEADERLOG111": { + "src_wire": "PCIE_IMUX5_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG111", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_19->PCIE_MIMRXRDATA57": { + "src_wire": "PCIE_IMUX5_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA57", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_2->PCIE_TRNTD92": { + "src_wire": "PCIE_IMUX0_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD92", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_8->PCIE_MIMTXRDATA35": { + "src_wire": "PCIE_IMUX3_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA35", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWADDR9->PCIE_LOGIC_OUTS_B21_R_4": { + "src_wire": "PCIE_MIMTXWADDR9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA12->PCIE_LOGIC_OUTS_B0_L_4": { + "src_wire": "PCIE_PIPETX1DATA12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_14->PCIE_CFGINTERRUPTDI4": { + "src_wire": "PCIE_IMUX16_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_18->PCIE_CFGDSN50": { + "src_wire": "PCIE_IMUX9_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN50", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_R_18->PCIE_PIPERX4DATA15": { + "src_wire": "PCIE_IMUX34_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_L_19->PCIE_PIPERX0STATUS0": { + "src_wire": "PCIE_IMUX39_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0STATUS0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_L_15->PCIE_PIPERX2CHARISK1": { + "src_wire": "PCIE_IMUX16_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2CHARISK1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLMAXPAYLOAD0->PCIE_LOGIC_OUTS_B19_L_14": { + "src_wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA42->PCIE_LOGIC_OUTS_B18_R_13": { + "src_wire": "PCIE_DBGVECA42", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD35->PCIE_LOGIC_OUTS_B0_L_14": { + "src_wire": "PCIE_TRNRD35", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_11->PCIE_CFGERRAERHEADERLOG118": { + "src_wire": "PCIE_IMUX4_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG118", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_17->PCIE_TRNTDLLPDATA7": { + "src_wire": "PCIE_IMUX0_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_L_18->PCIE_PIPERX0DATA12": { + "src_wire": "PCIE_IMUX39_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX21_R_13->PCIE_DBGMODE1": { + "src_wire": "PCIE_IMUX21_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_DBGMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_3->PCIE_CFGSUBSYSID0": { + "src_wire": "PCIE_IMUX12_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_R_6->PCIE_PIPERX7DATA0": { + "src_wire": "PCIE_IMUX37_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_6->PCIE_MIMTXRDATA24": { + "src_wire": "PCIE_IMUX0_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_11->PCIE_CFGERRAERHEADERLOG27": { + "src_wire": "PCIE_IMUX10_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG27", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA40->PCIE_LOGIC_OUTS_B1_R_0": { + "src_wire": "PCIE_MIMTXWDATA40", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_0->PCIE_MIMTXRDATA63": { + "src_wire": "PCIE_IMUX5_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA63", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_18->PCIE_TRNTD0": { + "src_wire": "PCIE_IMUX8_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD116->PCIE_LOGIC_OUTS_B0_R_14": { + "src_wire": "PCIE_TRNRD116", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA7->PCIE_LOGIC_OUTS_B17_L_12": { + "src_wire": "PCIE_CFGMSGDATA7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_1->PCIE_CFGPMHALTASPML0SN": { + "src_wire": "PCIE_IMUX8_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMHALTASPML0SN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB47->PCIE_LOGIC_OUTS_B18_L_3": { + "src_wire": "PCIE_DBGVECB47", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_10->PCIE_TRNTD77": { + "src_wire": "PCIE_IMUX3_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD77", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA34->PCIE_LOGIC_OUTS_B15_R_6": { + "src_wire": "PCIE_MIMTXWDATA34", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2POWERDOWN1->PCIE_LOGIC_OUTS_B7_L_13": { + "src_wire": "PCIE_PIPETX2POWERDOWN1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXRADDR8->PCIE_LOGIC_OUTS_B22_R_3": { + "src_wire": "PCIE_MIMTXRADDR8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD4->PCIE_LOGIC_OUTS_B8_L_6": { + "src_wire": "PCIE_TRNRD4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_R_19->PCIE_PIPERX4DATA10": { + "src_wire": "PCIE_IMUX33_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_10->PCIE_CFGDSDEVICENUMBER0": { + "src_wire": "PCIE_IMUX14_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSDEVICENUMBER0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSCURRENTSPEED1->PCIE_LOGIC_OUTS_B20_L_17": { + "src_wire": "PCIE_CFGLINKSTATUSCURRENTSPEED1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_L_10->PCIE_PIPERX1DATA3": { + "src_wire": "PCIE_IMUX32_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA2->PCIE_LOGIC_OUTS_B6_L_12": { + "src_wire": "PCIE_TRNRDLLPDATA2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA28->PCIE_LOGIC_OUTS_B4_L_19": { + "src_wire": "PCIE_TRNRDLLPDATA28", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB3->PCIE_LOGIC_OUTS_B22_R_10": { + "src_wire": "PCIE_DBGVECB3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_3->PCIE_TRNTD98": { + "src_wire": "PCIE_IMUX2_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD98", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB26->PCIE_LOGIC_OUTS_B7_R_3": { + "src_wire": "PCIE_DBGVECB26", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA2->PCIE_LOGIC_OUTS_B11_R_14": { + "src_wire": "PCIE_PIPETX6DATA2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2PPMSUSPENDOK->PCIE_LOGIC_OUTS_B21_R_16": { + "src_wire": "PCIE_TL2PPMSUSPENDOK", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR3->PCIE_LOGIC_OUTS_B10_R_11": { + "src_wire": "PCIE_TL2ERRHDR3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB58->PCIE_LOGIC_OUTS_B21_L_5": { + "src_wire": "PCIE_DBGVECB58", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_11->PCIE_CFGERRAERHEADERLOG29": { + "src_wire": "PCIE_IMUX12_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA6->PCIE_LOGIC_OUTS_B2_L_2": { + "src_wire": "PCIE_PIPETX3DATA6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR6->PCIE_LOGIC_OUTS_B6_R_10": { + "src_wire": "PCIE_TL2ERRHDR6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_12->PCIE_CFGERRAERHEADERLOG122": { + "src_wire": "PCIE_IMUX4_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG122", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA15->PCIE_LOGIC_OUTS_B6_L_0": { + "src_wire": "PCIE_PIPETX3DATA15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_L_16->PCIE_PIPERX2CHANISALIGNED": { + "src_wire": "PCIE_IMUX33_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2CHANISALIGNED", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA2->PCIE_LOGIC_OUTS_B11_R_3": { + "src_wire": "PCIE_PIPETX7DATA2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPD0->PCIE_LOGIC_OUTS_B5_R_3": { + "src_wire": "PCIE_TRNFCPD0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTB->PCIE_LOGIC_OUTS_B15_L_17": { + "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTB", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_R_7->PCIE_PIPERX5DATA15": { + "src_wire": "PCIE_IMUX34_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA13->PCIE_LOGIC_OUTS_B4_R_15": { + "src_wire": "PCIE_PIPETX4DATA13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PL2LINKUP->PCIE_LOGIC_OUTS_B8_R_14": { + "src_wire": "PCIE_PL2LINKUP", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_18->PCIE_CFGDSN49": { + "src_wire": "PCIE_IMUX8_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN49", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_14->PCIE_TRNRNPOK": { + "src_wire": "PCIE_IMUX1_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNRNPOK", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_13->PCIE_CFGDSN32": { + "src_wire": "PCIE_IMUX11_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN32", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA61->PCIE_LOGIC_OUTS_B6_R_3": { + "src_wire": "PCIE_MIMTXWDATA61", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLH5->PCIE_LOGIC_OUTS_B4_L_8": { + "src_wire": "PCIE_TRNFCCPLH5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR22->PCIE_LOGIC_OUTS_B14_L_1": { + "src_wire": "PCIE_TL2ERRHDR22", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA8->PCIE_LOGIC_OUTS_B9_L_12": { + "src_wire": "PCIE_PIPETX2DATA8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX18_R_12->PCIE_CFGVENDID7": { + "src_wire": "PCIE_IMUX18_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_6->PCIE_TRNTD108": { + "src_wire": "PCIE_IMUX0_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD108", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR2->PCIE_LOGIC_OUTS_B8_R_11": { + "src_wire": "PCIE_TL2ERRHDR2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_9->PCIE_MIMTXRDATA37": { + "src_wire": "PCIE_IMUX1_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA37", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR61->PCIE_LOGIC_OUTS_B12_L_12": { + "src_wire": "PCIE_TL2ERRHDR61", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_R_4->PCIE_PIPERX7ELECIDLE": { + "src_wire": "PCIE_IMUX34_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7ELECIDLE", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_L_4->PCIE_PIPERX3DATA8": { + "src_wire": "PCIE_IMUX37_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_10->PCIE_CFGMGMTBYTEENN0": { + "src_wire": "PCIE_IMUX6_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTBYTEENN0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA8->PCIE_LOGIC_OUTS_B9_R_5": { + "src_wire": "PCIE_PIPETX5DATA8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLH0->PCIE_LOGIC_OUTS_B14_L_6": { + "src_wire": "PCIE_TRNFCCPLH0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_13->PCIE_CFGMGMTDWADDR8": { + "src_wire": "PCIE_IMUX6_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_R_10->PCIE_CFGDSDEVICENUMBER2": { + "src_wire": "PCIE_IMUX17_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSDEVICENUMBER2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_12->PCIE_TRNTD68": { + "src_wire": "PCIE_IMUX2_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD68", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO8->PCIE_LOGIC_OUTS_B12_R_12": { + "src_wire": "PCIE_CFGMGMTDO8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA59->PCIE_LOGIC_OUTS_B19_R_9": { + "src_wire": "PCIE_DBGVECA59", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_R_13->PCIE_CFGINTERRUPTDI7": { + "src_wire": "PCIE_IMUX15_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWADDR2->PCIE_LOGIC_OUTS_B12_R_7": { + "src_wire": "PCIE_MIMTXWADDR2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_14->PCIE_CFGERRAERHEADERLOG15": { + "src_wire": "PCIE_IMUX10_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_R_18->PCIE_TRNTD45": { + "src_wire": "PCIE_IMUX15_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD45", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGSCLRE->PCIE_LOGIC_OUTS_B20_L_11": { + "src_wire": "PCIE_DBGSCLRE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_3->PCIE_CFGERRAERHEADERLOG88": { + "src_wire": "PCIE_IMUX6_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG88", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_14->PCIE_CFGERRTLPCPLHEADER4": { + "src_wire": "PCIE_IMUX6_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_8->PCIE_PIPERX5CHARISK1": { + "src_wire": "PCIE_IMUX16_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5CHARISK1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_13->PCIE_CFGERRTLPCPLHEADER0": { + "src_wire": "PCIE_IMUX6_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRBARHIT6->PCIE_LOGIC_OUTS_B3_R_8": { + "src_wire": "PCIE_TRNRBARHIT6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_12->PCIE_CFGDSN27": { + "src_wire": "PCIE_IMUX10_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN27", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0COMPLIANCE->PCIE_LOGIC_OUTS_B3_L_18": { + "src_wire": "PCIE_PIPETX0COMPLIANCE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA30->PCIE_LOGIC_OUTS_B20_R_6": { + "src_wire": "PCIE_MIMTXWDATA30", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR57->PCIE_LOGIC_OUTS_B14_L_11": { + "src_wire": "PCIE_TL2ERRHDR57", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLLTSSMSTATE2->PCIE_LOGIC_OUTS_B9_L_0": { + "src_wire": "PCIE_PLLTSSMSTATE2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR56->PCIE_LOGIC_OUTS_B13_L_11": { + "src_wire": "PCIE_TL2ERRHDR56", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_1->PCIE_CFGERRAERHEADERLOG81": { + "src_wire": "PCIE_IMUX7_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG81", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD0->PCIE_LOGIC_OUTS_B1_L_5": { + "src_wire": "PCIE_TRNRD0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR36->PCIE_LOGIC_OUTS_B14_L_5": { + "src_wire": "PCIE_TL2ERRHDR36", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_L_7->PCIE_PIPERX1DATA13": { + "src_wire": "PCIE_IMUX38_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA58->PCIE_LOGIC_OUTS_B14_R_9": { + "src_wire": "PCIE_DBGVECA58", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_7->PCIE_CFGERRAERHEADERLOG104": { + "src_wire": "PCIE_IMUX6_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG104", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA57->PCIE_LOGIC_OUTS_B21_R_10": { + "src_wire": "PCIE_DBGVECA57", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB43->PCIE_LOGIC_OUTS_B18_L_2": { + "src_wire": "PCIE_DBGVECB43", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_R_18->PCIE_PIPERX4DATA13": { + "src_wire": "PCIE_IMUX38_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLD0->PCIE_LOGIC_OUTS_B7_L_8": { + "src_wire": "PCIE_TRNFCCPLD0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_8->PCIE_MIMTXRDATA33": { + "src_wire": "PCIE_IMUX1_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA33", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6CHARISK0->PCIE_LOGIC_OUTS_B16_R_13": { + "src_wire": "PCIE_PIPETX6CHARISK0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLURERRREPORTINGEN->PCIE_LOGIC_OUTS_B21_L_13": { + "src_wire": "PCIE_CFGDEVCONTROLURERRREPORTINGEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_14->PCIE_CFGDSN33": { + "src_wire": "PCIE_IMUX8_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN33", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLDBGVEC3->PCIE_LOGIC_OUTS_B22_L_16": { + "src_wire": "PCIE_PLDBGVEC3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA6->PCIE_LOGIC_OUTS_B2_L_17": { + "src_wire": "PCIE_PIPETX0DATA6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_L_4->PCIE_PIPERX3DATA11": { + "src_wire": "PCIE_IMUX32_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_16->PCIE_DRPEN": { + "src_wire": "PCIE_IMUX13_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPEN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD126->PCIE_LOGIC_OUTS_B2_R_12": { + "src_wire": "PCIE_TRNRD126", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_13->PCIE_CFGMGMTWRRW1CASRWN": { + "src_wire": "PCIE_IMUX8_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTWRRW1CASRWN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB30->PCIE_LOGIC_OUTS_B12_R_2": { + "src_wire": "PCIE_DBGVECB30", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_0->PCIE_MIMTXRDATA0": { + "src_wire": "PCIE_IMUX0_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4POWERDOWN0->PCIE_LOGIC_OUTS_B1_R_17": { + "src_wire": "PCIE_PIPETX4POWERDOWN0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA19->PCIE_LOGIC_OUTS_B4_R_8": { + "src_wire": "PCIE_MIMTXWDATA19", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_9->PCIE_TRNTD123": { + "src_wire": "PCIE_IMUX3_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD123", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_17->PCIE_CFGDSN45": { + "src_wire": "PCIE_IMUX8_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN45", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO3->PCIE_LOGIC_OUTS_B14_L_8": { + "src_wire": "PCIE_CFGINTERRUPTDO3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPD10->PCIE_LOGIC_OUTS_B5_L_1": { + "src_wire": "PCIE_TRNFCPD10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA41->PCIE_LOGIC_OUTS_B18_R_18": { + "src_wire": "PCIE_MIMRXWDATA41", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR63->PCIE_LOGIC_OUTS_B15_L_13": { + "src_wire": "PCIE_TL2ERRHDR63", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_2->PCIE_TRNTD79": { + "src_wire": "PCIE_IMUX8_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD79", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6ELECIDLE->PCIE_LOGIC_OUTS_B3_R_13": { + "src_wire": "PCIE_PIPETX6ELECIDLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR14->PCIE_LOGIC_OUTS_B7_R_8": { + "src_wire": "PCIE_TL2ERRHDR14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA51->PCIE_LOGIC_OUTS_B18_R_11": { + "src_wire": "PCIE_DBGVECA51", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_3->PCIE_CFGERRAERHEADERLOG59": { + "src_wire": "PCIE_IMUX14_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG59", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_R_9->PCIE_PIPERX5DATA4": { + "src_wire": "PCIE_IMUX39_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_13->PCIE_CFGDSN31": { + "src_wire": "PCIE_IMUX10_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_L_17->PCIE_PIPERX2DATA1": { + "src_wire": "PCIE_IMUX36_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA29->PCIE_LOGIC_OUTS_B2_R_10": { + "src_wire": "PCIE_MIMTXWDATA29", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPD10->PCIE_LOGIC_OUTS_B12_L_6": { + "src_wire": "PCIE_TRNFCNPD10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_16->PCIE_CFGERRPOISONEDN": { + "src_wire": "PCIE_IMUX11_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRPOISONEDN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA27->PCIE_LOGIC_OUTS_B10_L_18": { + "src_wire": "PCIE_TRNRDLLPDATA27", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_18->PCIE_MIMRXRDATA60": { + "src_wire": "PCIE_IMUX4_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA60", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLDBGVEC0->PCIE_LOGIC_OUTS_B22_L_14": { + "src_wire": "PCIE_PLDBGVEC0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_3->PCIE_CFGMGMTDI3": { + "src_wire": "PCIE_IMUX9_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_4->PCIE_CFGPCIECAPINTERRUPTMSGNUM4": { + "src_wire": "PCIE_IMUX8_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA44->PCIE_LOGIC_OUTS_B8_R_1": { + "src_wire": "PCIE_MIMTXWDATA44", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD17->PCIE_LOGIC_OUTS_B2_L_9": { + "src_wire": "PCIE_TRNRD17", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_6->PCIE_MIMTXRDATA25": { + "src_wire": "PCIE_IMUX1_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_12->PCIE_CFGERRAERHEADERLOG124": { + "src_wire": "PCIE_IMUX6_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG124", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LNKCLKEN->PCIE_LOGIC_OUTS_B10_R_10": { + "src_wire": "PCIE_LNKCLKEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR39->PCIE_LOGIC_OUTS_B12_L_7": { + "src_wire": "PCIE_TL2ERRHDR39", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA22->PCIE_LOGIC_OUTS_B13_L_17": { + "src_wire": "PCIE_TRNRDLLPDATA22", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA64->PCIE_LOGIC_OUTS_B10_R_16": { + "src_wire": "PCIE_MIMRXWDATA64", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_2->PCIE_CFGERRAERHEADERLOG84": { + "src_wire": "PCIE_IMUX6_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG84", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_17->PCIE_MIMRXRDATA9": { + "src_wire": "PCIE_IMUX1_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_R_3->PCIE_CFGERRAERHEADERLOG60": { + "src_wire": "PCIE_IMUX15_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG60", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA66->PCIE_LOGIC_OUTS_B18_R_17": { + "src_wire": "PCIE_MIMRXWDATA66", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO7->PCIE_LOGIC_OUTS_B14_L_9": { + "src_wire": "PCIE_CFGINTERRUPTDO7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_2->PCIE_CFGPMWAKEN": { + "src_wire": "PCIE_IMUX9_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMWAKEN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA4->PCIE_LOGIC_OUTS_B0_L_13": { + "src_wire": "PCIE_PIPETX2DATA4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA27->PCIE_LOGIC_OUTS_B20_R_18": { + "src_wire": "PCIE_DBGVECA27", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA50->PCIE_LOGIC_OUTS_B17_R_11": { + "src_wire": "PCIE_DBGVECA50", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_18->PCIE_CFGERRTLPCPLHEADER18": { + "src_wire": "PCIE_IMUX4_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2POWERDOWN0->PCIE_LOGIC_OUTS_B1_L_13": { + "src_wire": "PCIE_PIPETX2POWERDOWN0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA13->PCIE_LOGIC_OUTS_B4_L_0": { + "src_wire": "PCIE_PIPETX3DATA13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA11->PCIE_LOGIC_OUTS_B15_R_16": { + "src_wire": "PCIE_PIPETX4DATA11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB39->PCIE_LOGIC_OUTS_B18_L_1": { + "src_wire": "PCIE_DBGVECB39", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD120->PCIE_LOGIC_OUTS_B5_R_13": { + "src_wire": "PCIE_TRNRD120", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA11->PCIE_LOGIC_OUTS_B15_L_16": { + "src_wire": "PCIE_PIPETX0DATA11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_11->PCIE_CFGERRAERHEADERLOG26": { + "src_wire": "PCIE_IMUX9_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_19->PCIE_MIMRXRDATA18": { + "src_wire": "PCIE_IMUX2_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_L_6->PCIE_PIPERX3DATA1": { + "src_wire": "PCIE_IMUX36_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_L_8->PCIE_PIPERX1STATUS0": { + "src_wire": "PCIE_IMUX39_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1STATUS0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_R_8->PCIE_PIPERX5DATA10": { + "src_wire": "PCIE_IMUX33_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA5->PCIE_LOGIC_OUTS_B4_R_17": { + "src_wire": "PCIE_PIPETX4DATA5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7COMPLIANCE->PCIE_LOGIC_OUTS_B3_R_3": { + "src_wire": "PCIE_PIPETX7COMPLIANCE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_17->PCIE_CFGDSN48": { + "src_wire": "PCIE_IMUX11_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN48", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA15->PCIE_LOGIC_OUTS_B6_L_15": { + "src_wire": "PCIE_PIPETX0DATA15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPH4->PCIE_LOGIC_OUTS_B14_L_2": { + "src_wire": "PCIE_TRNFCNPH4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_0->PCIE_PLDIRECTEDLINKSPEED": { + "src_wire": "PCIE_IMUX4_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLINKSPEED", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGAERECRCGENEN->PCIE_LOGIC_OUTS_B18_L_19": { + "src_wire": "PCIE_CFGAERECRCGENEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_0->PCIE_PLDIRECTEDLINKWIDTH0": { + "src_wire": "PCIE_IMUX2_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLINKWIDTH0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA67->PCIE_LOGIC_OUTS_B14_R_2": { + "src_wire": "PCIE_MIMTXWDATA67", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_0->PCIE_CFGPORTNUMBER0": { + "src_wire": "PCIE_IMUX16_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA26->PCIE_LOGIC_OUTS_B8_L_18": { + "src_wire": "PCIE_TRNRDLLPDATA26", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_L_10->PCIE_PIPERX1CHARISK0": { + "src_wire": "PCIE_IMUX16_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1CHARISK0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA19->PCIE_LOGIC_OUTS_B7_L_16": { + "src_wire": "PCIE_TRNRDLLPDATA19", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA2->PCIE_LOGIC_OUTS_B12_R_5": { + "src_wire": "PCIE_MIMTXWDATA2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX18_R_0->PCIE_CFGPORTNUMBER2": { + "src_wire": "PCIE_IMUX18_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_1->PCIE_TRNTD91": { + "src_wire": "PCIE_IMUX3_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD91", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD2->PCIE_LOGIC_OUTS_B3_L_5": { + "src_wire": "PCIE_TRNRD2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_L_4->PCIE_PIPERX3CHARISK1": { + "src_wire": "PCIE_IMUX16_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3CHARISK1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD21->PCIE_LOGIC_OUTS_B2_L_10": { + "src_wire": "PCIE_TRNRD21", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_2->PCIE_TRNTD93": { + "src_wire": "PCIE_IMUX1_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD93", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR31->PCIE_LOGIC_OUTS_B14_L_4": { + "src_wire": "PCIE_TL2ERRHDR31", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_L_4->PCIE_PIPERX3ELECIDLE": { + "src_wire": "PCIE_IMUX34_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3ELECIDLE", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DRPDO9->PCIE_LOGIC_OUTS_B22_L_19": { + "src_wire": "PCIE_DRPDO9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD124->PCIE_LOGIC_OUTS_B0_R_12": { + "src_wire": "PCIE_TRNRD124", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB33->PCIE_LOGIC_OUTS_B22_R_2": { + "src_wire": "PCIE_DBGVECB33", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA3->PCIE_LOGIC_OUTS_B15_L_18": { + "src_wire": "PCIE_PIPETX0DATA3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA65->PCIE_LOGIC_OUTS_B10_R_19": { + "src_wire": "PCIE_MIMRXWDATA65", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_R_8->PCIE_PIPERX5ELECIDLE": { + "src_wire": "PCIE_IMUX34_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5ELECIDLE", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LL2LINKSTATUS0->PCIE_LOGIC_OUTS_B15_R_17": { + "src_wire": "PCIE_LL2LINKSTATUS0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_12->PCIE_CFGDSN26": { + "src_wire": "PCIE_IMUX9_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLEXTTAGEN->PCIE_LOGIC_OUTS_B17_L_15": { + "src_wire": "PCIE_CFGDEVCONTROLEXTTAGEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTMSIENABLE->PCIE_LOGIC_OUTS_B17_L_1": { + "src_wire": "PCIE_CFGINTERRUPTMSIENABLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5CHARISK1->PCIE_LOGIC_OUTS_B16_R_4": { + "src_wire": "PCIE_PIPETX5CHARISK1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_L_14->PCIE_PIPERX2DATA12": { + "src_wire": "PCIE_IMUX39_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA9->PCIE_LOGIC_OUTS_B19_L_12": { + "src_wire": "PCIE_CFGMSGDATA9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_L_0->PCIE_CFGERRAERHEADERLOG75": { + "src_wire": "PCIE_IMUX14_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG75", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD52->PCIE_LOGIC_OUTS_B2_L_18": { + "src_wire": "PCIE_TRNRD52", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_15->PCIE_CFGERRTLPCPLHEADER9": { + "src_wire": "PCIE_IMUX7_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_R_5->PCIE_PIPERX7VALID": { + "src_wire": "PCIE_IMUX36_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7VALID", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_R_15->PCIE_PIPERX6STATUS0": { + "src_wire": "PCIE_IMUX39_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6STATUS0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA3->PCIE_LOGIC_OUTS_B7_R_7": { + "src_wire": "PCIE_MIMTXWDATA3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PL2L0REQ->PCIE_LOGIC_OUTS_B20_R_19": { + "src_wire": "PCIE_PL2L0REQ", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT->PCIE_LOGIC_OUTS_B8_L_19": { + "src_wire": "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA48->PCIE_LOGIC_OUTS_B16_R_16": { + "src_wire": "PCIE_MIMRXWDATA48", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA6->PCIE_LOGIC_OUTS_B2_R_13": { + "src_wire": "PCIE_PIPETX6DATA6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_15->PCIE_TRNTD56": { + "src_wire": "PCIE_IMUX6_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD56", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_7->PCIE_CFGMGMTDI19": { + "src_wire": "PCIE_IMUX10_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO4->PCIE_LOGIC_OUTS_B14_R_11": { + "src_wire": "PCIE_CFGMGMTDO4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD14->PCIE_LOGIC_OUTS_B3_L_8": { + "src_wire": "PCIE_TRNRD14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1COMPLIANCE->PCIE_LOGIC_OUTS_B3_L_7": { + "src_wire": "PCIE_PIPETX1COMPLIANCE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA42->PCIE_LOGIC_OUTS_B14_R_0": { + "src_wire": "PCIE_MIMTXWDATA42", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_19->PCIE_MIMRXRDATA58": { + "src_wire": "PCIE_IMUX6_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA58", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA40->PCIE_LOGIC_OUTS_B13_R_15": { + "src_wire": "PCIE_MIMRXWDATA40", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA62->PCIE_LOGIC_OUTS_B5_R_1": { + "src_wire": "PCIE_MIMTXWDATA62", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_11->PCIE_CFGERRAERHEADERLOG121": { + "src_wire": "PCIE_IMUX7_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG121", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLLINKUPCFGCAP->PCIE_LOGIC_OUTS_B2_L_1": { + "src_wire": "PCIE_PLLINKUPCFGCAP", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_L_16->PCIE_PIPERX2DATA7": { + "src_wire": "PCIE_IMUX34_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_9->PCIE_MIMTXRDATA66": { + "src_wire": "PCIE_IMUX4_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA66", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB20->PCIE_LOGIC_OUTS_B16_R_5": { + "src_wire": "PCIE_DBGVECB20", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_9->PCIE_CFGERRAERHEADERLOG112": { + "src_wire": "PCIE_IMUX6_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG112", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_12->PCIE_CFGMGMTDWADDR5": { + "src_wire": "PCIE_IMUX7_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGSCLRD->PCIE_LOGIC_OUTS_B19_L_11": { + "src_wire": "PCIE_DBGSCLRD", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_L_7->PCIE_PIPERX1DATA12": { + "src_wire": "PCIE_IMUX39_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0CHARISK1->PCIE_LOGIC_OUTS_B16_L_15": { + "src_wire": "PCIE_PIPETX0CHARISK1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LL2BADDLLPERR->PCIE_LOGIC_OUTS_B14_R_13": { + "src_wire": "PCIE_LL2BADDLLPERR", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA0->PCIE_LOGIC_OUTS_B17_R_5": { + "src_wire": "PCIE_MIMTXWDATA0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA9->PCIE_LOGIC_OUTS_B13_L_12": { + "src_wire": "PCIE_PIPETX2DATA9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_6->PCIE_CFGSUBSYSID6": { + "src_wire": "PCIE_IMUX12_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PL2RECEIVERERR->PCIE_LOGIC_OUTS_B10_R_14": { + "src_wire": "PCIE_PL2RECEIVERERR", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTMSIXFM->PCIE_LOGIC_OUTS_B16_L_5": { + "src_wire": "PCIE_CFGINTERRUPTMSIXFM", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLD7->PCIE_LOGIC_OUTS_B6_L_10": { + "src_wire": "PCIE_TRNFCCPLD7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_10->PCIE_CFGDSBUSNUMBER7": { + "src_wire": "PCIE_IMUX13_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA14->PCIE_LOGIC_OUTS_B4_R_18": { + "src_wire": "PCIE_MIMRXWDATA14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_0->PCIE_TRNTD89": { + "src_wire": "PCIE_IMUX10_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD89", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_17->PCIE_CFGERRTLPCPLHEADER14": { + "src_wire": "PCIE_IMUX4_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXRADDR3->PCIE_LOGIC_OUTS_B10_R_2": { + "src_wire": "PCIE_MIMTXRADDR3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_L_0->PCIE_CFGPORTNUMBER4": { + "src_wire": "PCIE_IMUX17_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD1->PCIE_LOGIC_OUTS_B2_L_5": { + "src_wire": "PCIE_TRNRD1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_11->PCIE_TRNTD71": { + "src_wire": "PCIE_IMUX1_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD71", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_L_3->PCIE_CFGSUBSYSID2": { + "src_wire": "PCIE_IMUX14_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_12->PCIE_TRNTD66": { + "src_wire": "PCIE_IMUX0_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD66", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA1->PCIE_LOGIC_OUTS_B13_L_10": { + "src_wire": "PCIE_CFGMSGDATA1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTC->PCIE_LOGIC_OUTS_B17_L_17": { + "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTC", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_10->PCIE_TRNTD126": { + "src_wire": "PCIE_IMUX2_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD126", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWADDR8->PCIE_LOGIC_OUTS_B12_R_3": { + "src_wire": "PCIE_MIMTXWADDR8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA15->PCIE_LOGIC_OUTS_B13_L_15": { + "src_wire": "PCIE_CFGMSGDATA15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRMALFORMED->PCIE_LOGIC_OUTS_B17_L_13": { + "src_wire": "PCIE_TL2ERRMALFORMED", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_L_5->PCIE_PIPERX3VALID": { + "src_wire": "PCIE_IMUX36_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3VALID", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_L_14->PCIE_PIPERX2DATA13": { + "src_wire": "PCIE_IMUX38_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTC->PCIE_LOGIC_OUTS_B18_L_17": { + "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTC", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_12->PCIE_CFGMGMTDWADDR4": { + "src_wire": "PCIE_IMUX6_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXRADDR4->PCIE_LOGIC_OUTS_B14_R_4": { + "src_wire": "PCIE_MIMTXRADDR4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSBANDWIDTHSTATUS->PCIE_LOGIC_OUTS_B13_L_19": { + "src_wire": "PCIE_CFGLINKSTATUSBANDWIDTHSTATUS", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLH2->PCIE_LOGIC_OUTS_B7_L_7": { + "src_wire": "PCIE_TRNFCCPLH2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPD9->PCIE_LOGIC_OUTS_B11_L_6": { + "src_wire": "PCIE_TRNFCNPD9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_16->PCIE_CFGAERINTERRUPTMSGNUM4": { + "src_wire": "PCIE_IMUX12_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_1->PCIE_CFGERRAERHEADERLOG78": { + "src_wire": "PCIE_IMUX4_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG78", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA0->PCIE_LOGIC_OUTS_B9_R_3": { + "src_wire": "PCIE_PIPETX7DATA0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_L_1->PCIE_CFGREVID3": { + "src_wire": "PCIE_IMUX15_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_R_19->PCIE_PIPERX4DATA9": { + "src_wire": "PCIE_IMUX36_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_4->PCIE_PIPERX7CHARISK1": { + "src_wire": "PCIE_IMUX16_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7CHARISK1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA67->PCIE_LOGIC_OUTS_B14_R_17": { + "src_wire": "PCIE_MIMRXWDATA67", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR43->PCIE_LOGIC_OUTS_B8_L_8": { + "src_wire": "PCIE_TL2ERRHDR43", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_9->PCIE_CFGERRAERHEADERLOG110": { + "src_wire": "PCIE_IMUX4_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG110", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR52->PCIE_LOGIC_OUTS_B9_L_10": { + "src_wire": "PCIE_TL2ERRHDR52", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVED->PCIE_LOGIC_OUTS_B15_L_9": { + "src_wire": "PCIE_CFGMSGRECEIVED", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_R_7->PCIE_PIPERX5DATA13": { + "src_wire": "PCIE_IMUX38_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRSRCDSC->PCIE_LOGIC_OUTS_B3_R_10": { + "src_wire": "PCIE_TRNRSRCDSC", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXRADDR9->PCIE_LOGIC_OUTS_B3_R_4": { + "src_wire": "PCIE_MIMTXRADDR9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_17->PCIE_DRPWE": { + "src_wire": "PCIE_IMUX12_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPWE", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_16->PCIE_TRNTD52": { + "src_wire": "PCIE_IMUX6_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD52", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_14->PCIE_CFGDSN34": { + "src_wire": "PCIE_IMUX9_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN34", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA33->PCIE_LOGIC_OUTS_B4_R_7": { + "src_wire": "PCIE_MIMTXWDATA33", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_L_9->PCIE_PIPERX1PHYSTATUS": { + "src_wire": "PCIE_IMUX37_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1PHYSTATUS", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA10->PCIE_LOGIC_OUTS_B11_L_16": { + "src_wire": "PCIE_PIPETX0DATA10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_16->PCIE_TRNTD50": { + "src_wire": "PCIE_IMUX4_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD50", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECC3->PCIE_LOGIC_OUTS_B18_L_8": { + "src_wire": "PCIE_DBGVECC3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_L_1->PCIE_PLDBGMODE2": { + "src_wire": "PCIE_IMUX17_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDBGMODE2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLLTSSMSTATE0->PCIE_LOGIC_OUTS_B7_L_0": { + "src_wire": "PCIE_PLLTSSMSTATE0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4COMPLIANCE->PCIE_LOGIC_OUTS_B3_R_18": { + "src_wire": "PCIE_PIPETX4COMPLIANCE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_11->PCIE_CFGDSN24": { + "src_wire": "PCIE_IMUX11_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_1->PCIE_PLDIRECTEDLTSSMSTALL": { + "src_wire": "PCIE_IMUX2_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMSTALL", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR58->PCIE_LOGIC_OUTS_B15_L_11": { + "src_wire": "PCIE_TL2ERRHDR58", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_16->PCIE_MIMRXRDATA5": { + "src_wire": "PCIE_IMUX1_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_14->PCIE_CFGERRTLPCPLHEADER5": { + "src_wire": "PCIE_IMUX7_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA21->PCIE_LOGIC_OUTS_B12_L_17": { + "src_wire": "PCIE_TRNRDLLPDATA21", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_R_17->PCIE_PIPERX6DATA3": { + "src_wire": "PCIE_IMUX32_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_10->PCIE_TRNTD124": { + "src_wire": "PCIE_IMUX0_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD124", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA1->PCIE_LOGIC_OUTS_B13_L_14": { + "src_wire": "PCIE_PIPETX2DATA1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ASPMSUSPENDCREDITCHECKOK->PCIE_LOGIC_OUTS_B7_R_14": { + "src_wire": "PCIE_TL2ASPMSUSPENDCREDITCHECKOK", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_3->PCIE_CFGMGMTDI5": { + "src_wire": "PCIE_IMUX11_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_8->PCIE_TRNTD118": { + "src_wire": "PCIE_IMUX2_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD118", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB17->PCIE_LOGIC_OUTS_B13_R_6": { + "src_wire": "PCIE_DBGVECB17", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_14->PCIE_TRNFCSEL1": { + "src_wire": "PCIE_IMUX3_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNFCSEL1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_9->PCIE_CFGERRAERHEADERLOG34": { + "src_wire": "PCIE_IMUX11_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG34", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_14->PCIE_CFGAERINTERRUPTMSGNUM0": { + "src_wire": "PCIE_IMUX12_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_1->PCIE_CFGERRAERHEADERLOG68": { + "src_wire": "PCIE_IMUX14_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG68", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_18->PCIE_MIMRXRDATA62": { + "src_wire": "PCIE_IMUX6_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA62", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_12->PCIE_CFGMGMTDWADDR6": { + "src_wire": "PCIE_IMUX8_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_7->PCIE_TRNTD112": { + "src_wire": "PCIE_IMUX0_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD112", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_L_7->PCIE_CFGSUBSYSID13": { + "src_wire": "PCIE_IMUX15_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWADDR9->PCIE_LOGIC_OUTS_B17_R_19": { + "src_wire": "PCIE_MIMRXWADDR9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA63->PCIE_LOGIC_OUTS_B10_R_18": { + "src_wire": "PCIE_MIMRXWDATA63", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA50->PCIE_LOGIC_OUTS_B17_R_16": { + "src_wire": "PCIE_MIMRXWDATA50", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_15->PCIE_CFGERRTLPCPLHEADER7": { + "src_wire": "PCIE_IMUX5_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_9->PCIE_CFGMGMTDI27": { + "src_wire": "PCIE_IMUX7_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI27", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA27->PCIE_LOGIC_OUTS_B13_R_9": { + "src_wire": "PCIE_MIMTXWDATA27", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA23->PCIE_LOGIC_OUTS_B20_R_8": { + "src_wire": "PCIE_MIMTXWDATA23", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_12->PCIE_CFGINTERRUPTSTATN": { + "src_wire": "PCIE_IMUX13_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTSTATN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB9->PCIE_LOGIC_OUTS_B22_R_18": { + "src_wire": "PCIE_DBGVECB9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWADDR0->PCIE_LOGIC_OUTS_B14_R_19": { + "src_wire": "PCIE_MIMRXWADDR0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA9->PCIE_LOGIC_OUTS_B13_R_16": { + "src_wire": "PCIE_PIPETX4DATA9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_8->PCIE_TRNTD116": { + "src_wire": "PCIE_IMUX0_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD116", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWADDR10->PCIE_LOGIC_OUTS_B12_R_16": { + "src_wire": "PCIE_MIMRXWADDR10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR25->PCIE_LOGIC_OUTS_B12_L_3": { + "src_wire": "PCIE_TL2ERRHDR25", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD15->PCIE_LOGIC_OUTS_B0_L_9": { + "src_wire": "PCIE_TRNRD15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA14->PCIE_LOGIC_OUTS_B2_L_4": { + "src_wire": "PCIE_PIPETX1DATA14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB22->PCIE_LOGIC_OUTS_B7_R_4": { + "src_wire": "PCIE_DBGVECB22", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA5->PCIE_LOGIC_OUTS_B4_R_9": { + "src_wire": "PCIE_MIMTXWDATA5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_5->PCIE_CFGSUBSYSID4": { + "src_wire": "PCIE_IMUX12_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA60->PCIE_LOGIC_OUTS_B20_R_9": { + "src_wire": "PCIE_DBGVECA60", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_13->PCIE_CFGMGMTDWADDR9": { + "src_wire": "PCIE_IMUX7_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_12->PCIE_CFGERRAERHEADERLOG23": { + "src_wire": "PCIE_IMUX10_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_L_18->PCIE_PIPERX0DATA15": { + "src_wire": "PCIE_IMUX34_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_4->PCIE_CFGTRNPENDINGN": { + "src_wire": "PCIE_IMUX9_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGTRNPENDINGN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA52->PCIE_LOGIC_OUTS_B12_R_0": { + "src_wire": "PCIE_MIMTXWDATA52", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LL2SUSPENDOK->PCIE_LOGIC_OUTS_B12_R_17": { + "src_wire": "PCIE_LL2SUSPENDOK", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_13->PCIE_TRNTD62": { + "src_wire": "PCIE_IMUX0_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD62", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0->PCIE_LOGIC_OUTS_B21_L_17": { + "src_wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_0->PCIE_MIMTXRDATA65": { + "src_wire": "PCIE_IMUX7_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA65", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO4->PCIE_LOGIC_OUTS_B15_L_8": { + "src_wire": "PCIE_CFGINTERRUPTDO4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB42->PCIE_LOGIC_OUTS_B21_L_1": { + "src_wire": "PCIE_DBGVECB42", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_14->PCIE_CFGMGMTWRENN": { + "src_wire": "PCIE_IMUX6_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTWRENN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR60->PCIE_LOGIC_OUTS_B10_L_12": { + "src_wire": "PCIE_TL2ERRHDR60", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB24->PCIE_LOGIC_OUTS_B12_R_4": { + "src_wire": "PCIE_DBGVECB24", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_9->PCIE_MIMTXRDATA38": { + "src_wire": "PCIE_IMUX2_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA38", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_18->PCIE_CFGERRTLPCPLHEADER20": { + "src_wire": "PCIE_IMUX6_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA28->PCIE_LOGIC_OUTS_B16_R_7": { + "src_wire": "PCIE_MIMTXWDATA28", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_11->PCIE_CFGSUBSYSVENDID5": { + "src_wire": "PCIE_IMUX13_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_1->PCIE_CFGREVID0": { + "src_wire": "PCIE_IMUX12_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO0->PCIE_LOGIC_OUTS_B17_L_5": { + "src_wire": "PCIE_CFGINTERRUPTDO0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA13->PCIE_LOGIC_OUTS_B4_R_4": { + "src_wire": "PCIE_PIPETX5DATA13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA8->PCIE_LOGIC_OUTS_B9_R_12": { + "src_wire": "PCIE_PIPETX6DATA8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_R_12->PCIE_CFGVENDID6": { + "src_wire": "PCIE_IMUX17_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR4->PCIE_LOGIC_OUTS_B11_R_11": { + "src_wire": "PCIE_TL2ERRHDR4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA26->PCIE_LOGIC_OUTS_B8_R_18": { + "src_wire": "PCIE_DBGVECA26", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA40->PCIE_LOGIC_OUTS_B21_R_14": { + "src_wire": "PCIE_DBGVECA40", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA11->PCIE_LOGIC_OUTS_B15_R_1": { + "src_wire": "PCIE_PIPETX7DATA11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_18->PCIE_MIMRXRDATA61": { + "src_wire": "PCIE_IMUX5_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA61", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGAERECRCCHECKEN->PCIE_LOGIC_OUTS_B17_L_19": { + "src_wire": "PCIE_CFGAERECRCCHECKEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_17->PCIE_MIMRXRDATA11": { + "src_wire": "PCIE_IMUX3_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA50->PCIE_LOGIC_OUTS_B7_R_1": { + "src_wire": "PCIE_MIMTXWDATA50", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXRADDR7->PCIE_LOGIC_OUTS_B15_R_19": { + "src_wire": "PCIE_MIMRXRADDR7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO11->PCIE_LOGIC_OUTS_B17_R_13": { + "src_wire": "PCIE_CFGMGMTDO11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_8->PCIE_CFGMGMTDI23": { + "src_wire": "PCIE_IMUX5_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLH7->PCIE_LOGIC_OUTS_B6_L_8": { + "src_wire": "PCIE_TRNFCCPLH7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTD->PCIE_LOGIC_OUTS_B12_L_18": { + "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTD", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ASPMSUSPENDREQ->PCIE_LOGIC_OUTS_B6_R_14": { + "src_wire": "PCIE_TL2ASPMSUSPENDREQ", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA48->PCIE_LOGIC_OUTS_B20_R_12": { + "src_wire": "PCIE_DBGVECA48", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR45->PCIE_LOGIC_OUTS_B10_L_8": { + "src_wire": "PCIE_TL2ERRHDR45", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_R_14->PCIE_CFGVENDID1": { + "src_wire": "PCIE_IMUX17_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_9->PCIE_CFGERRAERHEADERLOG35": { + "src_wire": "PCIE_IMUX12_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG35", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR18->PCIE_LOGIC_OUTS_B4_R_1": { + "src_wire": "PCIE_TL2ERRHDR18", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRREM1->PCIE_LOGIC_OUTS_B3_R_11": { + "src_wire": "PCIE_TRNRREM1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1POWERDOWN0->PCIE_LOGIC_OUTS_B1_L_6": { + "src_wire": "PCIE_PIPETX1POWERDOWN0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_14->PCIE_CFGERRMALFORMEDN": { + "src_wire": "PCIE_IMUX8_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRMALFORMEDN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_12->PCIE_CFGSUBSYSVENDID8": { + "src_wire": "PCIE_IMUX12_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_15->PCIE_TRNTDLLPDATA2": { + "src_wire": "PCIE_IMUX3_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_18->PCIE_MIMRXRDATA15": { + "src_wire": "PCIE_IMUX3_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_8->PCIE_CFGMGMTDI25": { + "src_wire": "PCIE_IMUX7_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA13->PCIE_LOGIC_OUTS_B9_L_15": { + "src_wire": "PCIE_TRNRDLLPDATA13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX20_R_1->PCIE_CFGVENDID14": { + "src_wire": "PCIE_IMUX20_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA9->PCIE_LOGIC_OUTS_B7_L_14": { + "src_wire": "PCIE_TRNRDLLPDATA9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_R_3->PCIE_PIPERX7DATA15": { + "src_wire": "PCIE_IMUX34_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_19->PCIE_CFGERRTLPCPLHEADER22": { + "src_wire": "PCIE_IMUX4_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DRPDO10->PCIE_LOGIC_OUTS_B23_L_19": { + "src_wire": "PCIE_DRPDO10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK->PCIE_LOGIC_OUTS_B21_L_15": { + "src_wire": "PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_11->PCIE_TRNTD73": { + "src_wire": "PCIE_IMUX3_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD73", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_10->PCIE_CFGERRAERHEADERLOG32": { + "src_wire": "PCIE_IMUX11_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG32", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA12->PCIE_LOGIC_OUTS_B16_L_14": { + "src_wire": "PCIE_CFGMSGDATA12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWEN->PCIE_LOGIC_OUTS_B12_R_6": { + "src_wire": "PCIE_MIMTXWEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR24->PCIE_LOGIC_OUTS_B17_L_2": { + "src_wire": "PCIE_TL2ERRHDR24", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXRADDR11->PCIE_LOGIC_OUTS_B8_R_5": { + "src_wire": "PCIE_MIMTXRADDR11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_L_19->PCIE_PIPERX0DATA9": { + "src_wire": "PCIE_IMUX36_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA1->PCIE_LOGIC_OUTS_B19_R_5": { + "src_wire": "PCIE_MIMTXWDATA1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0ELECIDLE->PCIE_LOGIC_OUTS_B3_L_17": { + "src_wire": "PCIE_PIPETX0ELECIDLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LL2RECEIVERERR->PCIE_LOGIC_OUTS_B11_R_13": { + "src_wire": "PCIE_LL2RECEIVERERR", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_7->PCIE_MIMTXRDATA68": { + "src_wire": "PCIE_IMUX8_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA68", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTMMENABLE0->PCIE_LOGIC_OUTS_B16_R_10": { + "src_wire": "PCIE_CFGINTERRUPTMMENABLE0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPD1->PCIE_LOGIC_OUTS_B8_L_4": { + "src_wire": "PCIE_TRNFCNPD1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA1->PCIE_LOGIC_OUTS_B13_L_7": { + "src_wire": "PCIE_PIPETX1DATA1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_5->PCIE_MIMTXRDATA22": { + "src_wire": "PCIE_IMUX2_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPH1->PCIE_LOGIC_OUTS_B11_L_2": { + "src_wire": "PCIE_TRNFCNPH1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGSCLRC->PCIE_LOGIC_OUTS_B21_L_10": { + "src_wire": "PCIE_DBGSCLRC", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_18->PCIE_TRNTDLLPDATA13": { + "src_wire": "PCIE_IMUX2_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNTBUFAV4->PCIE_LOGIC_OUTS_B5_L_4": { + "src_wire": "PCIE_TRNTBUFAV4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1->PCIE_LOGIC_OUTS_B18_L_18": { + "src_wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CTRL0_R_0->PCIE_SYSRSTN": { + "src_wire": "PCIE_CTRL0_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_SYSRSTN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRSRCRDY->PCIE_LOGIC_OUTS_B0_R_10": { + "src_wire": "PCIE_TRNRSRCRDY", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPERX5POLARITY->PCIE_LOGIC_OUTS_B1_R_7": { + "src_wire": "PCIE_PIPERX5POLARITY", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_17->PCIE_CFGDSN46": { + "src_wire": "PCIE_IMUX9_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN46", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA66->PCIE_LOGIC_OUTS_B18_R_2": { + "src_wire": "PCIE_MIMTXWDATA66", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_8->PCIE_CFGDSN12": { + "src_wire": "PCIE_IMUX11_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD7->PCIE_LOGIC_OUTS_B0_L_7": { + "src_wire": "PCIE_TRNRD7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_3->PCIE_TRNTD96": { + "src_wire": "PCIE_IMUX0_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD96", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA47->PCIE_LOGIC_OUTS_B19_R_12": { + "src_wire": "PCIE_DBGVECA47", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLDBGVEC7->PCIE_LOGIC_OUTS_B23_L_18": { + "src_wire": "PCIE_PLDBGVEC7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_11->PCIE_CFGMGMTDWADDR1": { + "src_wire": "PCIE_IMUX7_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA14->PCIE_LOGIC_OUTS_B2_R_11": { + "src_wire": "PCIE_PIPETX6DATA14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_R_14->PCIE_CFGINTERRUPTDI3": { + "src_wire": "PCIE_IMUX15_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_R_3->PCIE_PIPERX7DATA14": { + "src_wire": "PCIE_IMUX35_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_L_0->PCIE_CFGERRAERHEADERLOG77": { + "src_wire": "PCIE_IMUX16_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG77", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLDBGVEC6->PCIE_LOGIC_OUTS_B23_L_17": { + "src_wire": "PCIE_PLDBGVEC6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_19->PCIE_CFGDSN53": { + "src_wire": "PCIE_IMUX8_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN53", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_13->PCIE_CFGMGMTDWADDR7": { + "src_wire": "PCIE_IMUX5_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PL2RXELECIDLE->PCIE_LOGIC_OUTS_B7_R_19": { + "src_wire": "PCIE_PL2RXELECIDLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_17->PCIE_CFGERRATOMICEGRESSBLOCKEDN": { + "src_wire": "PCIE_IMUX13_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRATOMICEGRESSBLOCKEDN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_L_14->PCIE_CFGAERINTERRUPTMSGNUM2": { + "src_wire": "PCIE_IMUX14_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_2->PCIE_TRNTD82": { + "src_wire": "PCIE_IMUX11_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD82", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_R_13->PCIE_CFGVENDID2": { + "src_wire": "PCIE_IMUX17_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA56->PCIE_LOGIC_OUTS_B20_R_10": { + "src_wire": "PCIE_DBGVECA56", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNTBUFAV5->PCIE_LOGIC_OUTS_B7_L_4": { + "src_wire": "PCIE_TRNTBUFAV5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPD4->PCIE_LOGIC_OUTS_B11_L_4": { + "src_wire": "PCIE_TRNFCNPD4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_L_19->PCIE_PIPERX0CHARISK1": { + "src_wire": "PCIE_IMUX16_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0CHARISK1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR40->PCIE_LOGIC_OUTS_B14_L_7": { + "src_wire": "PCIE_TL2ERRHDR40", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_L_15->PCIE_PIPERX2STATUS1": { + "src_wire": "PCIE_IMUX38_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2STATUS1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD23->PCIE_LOGIC_OUTS_B1_L_11": { + "src_wire": "PCIE_TRNRD23", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_4->PCIE_TRNTD103": { + "src_wire": "PCIE_IMUX3_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD103", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_13->PCIE_CFGINTERRUPTDI6": { + "src_wire": "PCIE_IMUX14_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX19_L_0->PCIE_CFGPORTNUMBER6": { + "src_wire": "PCIE_IMUX19_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD106->PCIE_LOGIC_OUTS_B5_R_17": { + "src_wire": "PCIE_TRNRD106", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA10->PCIE_LOGIC_OUTS_B11_R_16": { + "src_wire": "PCIE_PIPETX4DATA10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD28->PCIE_LOGIC_OUTS_B1_L_12": { + "src_wire": "PCIE_TRNRD28", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_13->PCIE_CFGERRAERHEADERLOG127": { + "src_wire": "PCIE_IMUX5_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG127", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECC7->PCIE_LOGIC_OUTS_B18_L_9": { + "src_wire": "PCIE_DBGVECC7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_19->PCIE_CFGDSN54": { + "src_wire": "PCIE_IMUX9_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN54", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA20->PCIE_LOGIC_OUTS_B0_R_5": { + "src_wire": "PCIE_MIMTXWDATA20", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA37->PCIE_LOGIC_OUTS_B20_R_15": { + "src_wire": "PCIE_DBGVECA37", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA6->PCIE_LOGIC_OUTS_B2_R_6": { + "src_wire": "PCIE_PIPETX5DATA6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_3->PCIE_CFGERRAERHEADERLOG86": { + "src_wire": "PCIE_IMUX4_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG86", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_R_9->PCIE_PIPERX5DATA7": { + "src_wire": "PCIE_IMUX34_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA38->PCIE_LOGIC_OUTS_B12_R_15": { + "src_wire": "PCIE_MIMRXWDATA38", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_14->PCIE_CFGINTERRUPTDI1": { + "src_wire": "PCIE_IMUX13_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDUNLOCK->PCIE_LOGIC_OUTS_B9_L_19": { + "src_wire": "PCIE_CFGMSGRECEIVEDUNLOCK", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_1->PCIE_TRNTD86": { + "src_wire": "PCIE_IMUX11_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD86", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LL2LINKSTATUS4->PCIE_LOGIC_OUTS_B20_R_16": { + "src_wire": "PCIE_LL2LINKSTATUS4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_7->PCIE_CFGMGMTDI21": { + "src_wire": "PCIE_IMUX12_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_0->PCIE_CFGERRAERHEADERLOG71": { + "src_wire": "PCIE_IMUX13_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG71", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD109->PCIE_LOGIC_OUTS_B10_R_17": { + "src_wire": "PCIE_TRNRD109", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_4->PCIE_CFGERRAERHEADERLOG90": { + "src_wire": "PCIE_IMUX4_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG90", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLD3->PCIE_LOGIC_OUTS_B6_L_9": { + "src_wire": "PCIE_TRNFCCPLD3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_17->PCIE_TRNTD46": { + "src_wire": "PCIE_IMUX8_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD46", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_R_16->PCIE_PIPERX6DATA7": { + "src_wire": "PCIE_IMUX34_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_L_9->PCIE_PIPERX1DATA5": { + "src_wire": "PCIE_IMUX38_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_3->PCIE_CFGPCIECAPINTERRUPTMSGNUM3": { + "src_wire": "PCIE_IMUX11_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA30->PCIE_LOGIC_OUTS_B21_R_17": { + "src_wire": "PCIE_DBGVECA30", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLMAXREADREQ0->PCIE_LOGIC_OUTS_B16_L_16": { + "src_wire": "PCIE_CFGDEVCONTROLMAXREADREQ0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR41->PCIE_LOGIC_OUTS_B16_L_7": { + "src_wire": "PCIE_TL2ERRHDR41", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_R_15->PCIE_PIPERX6STATUS2": { + "src_wire": "PCIE_IMUX35_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6STATUS2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3CHARISK1->PCIE_LOGIC_OUTS_B16_L_0": { + "src_wire": "PCIE_PIPETX3CHARISK1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA64->PCIE_LOGIC_OUTS_B16_R_1": { + "src_wire": "PCIE_MIMTXWDATA64", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPH7->PCIE_LOGIC_OUTS_B8_L_3": { + "src_wire": "PCIE_TRNFCNPH7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA12->PCIE_LOGIC_OUTS_B8_L_15": { + "src_wire": "PCIE_TRNRDLLPDATA12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR13->PCIE_LOGIC_OUTS_B11_R_9": { + "src_wire": "PCIE_TL2ERRHDR13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_12->PCIE_CFGERRAERHEADERLOG25": { + "src_wire": "PCIE_IMUX12_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA18->PCIE_LOGIC_OUTS_B1_R_5": { + "src_wire": "PCIE_MIMTXWDATA18", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA38->PCIE_LOGIC_OUTS_B19_R_14": { + "src_wire": "PCIE_DBGVECA38", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA4->PCIE_LOGIC_OUTS_B11_L_13": { + "src_wire": "PCIE_TRNRDLLPDATA4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_4->PCIE_CFGMGMTDI9": { + "src_wire": "PCIE_IMUX6_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_11->PCIE_CFGDSBUSNUMBER6": { + "src_wire": "PCIE_IMUX16_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO10->PCIE_LOGIC_OUTS_B15_R_13": { + "src_wire": "PCIE_CFGMGMTDO10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3POWERDOWN0->PCIE_LOGIC_OUTS_B1_L_2": { + "src_wire": "PCIE_PIPETX3POWERDOWN0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB27->PCIE_LOGIC_OUTS_B8_R_3": { + "src_wire": "PCIE_DBGVECB27", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_L_17->PCIE_PIPERX2DATA3": { + "src_wire": "PCIE_IMUX32_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLLTSSMSTATE4->PCIE_LOGIC_OUTS_B11_L_0": { + "src_wire": "PCIE_PLLTSSMSTATE4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA47->PCIE_LOGIC_OUTS_B18_R_19": { + "src_wire": "PCIE_MIMRXWDATA47", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA4->PCIE_LOGIC_OUTS_B0_L_2": { + "src_wire": "PCIE_PIPETX3DATA4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_10->PCIE_CFGERRAERHEADERLOG115": { + "src_wire": "PCIE_IMUX5_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG115", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRECRCERR->PCIE_LOGIC_OUTS_B4_R_10": { + "src_wire": "PCIE_TRNRECRCERR", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA7->PCIE_LOGIC_OUTS_B6_R_6": { + "src_wire": "PCIE_PIPETX5DATA7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_6->PCIE_CFGERRAERHEADERLOG98": { + "src_wire": "PCIE_IMUX4_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG98", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_7->PCIE_TRNTD115": { + "src_wire": "PCIE_IMUX3_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD115", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD8->PCIE_LOGIC_OUTS_B2_L_7": { + "src_wire": "PCIE_TRNRD8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMPME->PCIE_LOGIC_OUTS_B14_L_18": { + "src_wire": "PCIE_CFGMSGRECEIVEDPMPME", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_L_10->PCIE_PIPERX1DATA2": { + "src_wire": "PCIE_IMUX33_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA24->PCIE_LOGIC_OUTS_B6_L_18": { + "src_wire": "PCIE_TRNRDLLPDATA24", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNTBUFAV2->PCIE_LOGIC_OUTS_B1_L_4": { + "src_wire": "PCIE_TRNTBUFAV2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_13->PCIE_TRNTD63": { + "src_wire": "PCIE_IMUX1_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD63", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_13->PCIE_TRNRNPREQ": { + "src_wire": "PCIE_IMUX3_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNRNPREQ", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLD11->PCIE_LOGIC_OUTS_B10_L_11": { + "src_wire": "PCIE_TRNFCCPLD11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_4->PCIE_CFGFORCEMPS0": { + "src_wire": "PCIE_IMUX10_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGFORCEMPS0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA4->PCIE_LOGIC_OUTS_B0_L_17": { + "src_wire": "PCIE_PIPETX0DATA4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA47->PCIE_LOGIC_OUTS_B18_R_4": { + "src_wire": "PCIE_MIMTXWDATA47", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR44->PCIE_LOGIC_OUTS_B9_L_8": { + "src_wire": "PCIE_TL2ERRHDR44", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_R_19->PCIE_PIPERX4DATA8": { + "src_wire": "PCIE_IMUX37_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA7->PCIE_LOGIC_OUTS_B6_L_17": { + "src_wire": "PCIE_PIPETX0DATA7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA28->PCIE_LOGIC_OUTS_B21_R_18": { + "src_wire": "PCIE_DBGVECA28", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLMAXPAYLOAD2->PCIE_LOGIC_OUTS_B21_L_14": { + "src_wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_15->PCIE_PIPERX6CHARISK1": { + "src_wire": "PCIE_IMUX16_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6CHARISK1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA49->PCIE_LOGIC_OUTS_B13_R_4": { + "src_wire": "PCIE_MIMTXWDATA49", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB2->PCIE_LOGIC_OUTS_B22_R_9": { + "src_wire": "PCIE_DBGVECB2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA53->PCIE_LOGIC_OUTS_B19_R_2": { + "src_wire": "PCIE_MIMTXWDATA53", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXRADDR7->PCIE_LOGIC_OUTS_B17_R_4": { + "src_wire": "PCIE_MIMTXRADDR7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR55->PCIE_LOGIC_OUTS_B12_L_11": { + "src_wire": "PCIE_TL2ERRHDR55", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA35->PCIE_LOGIC_OUTS_B17_R_9": { + "src_wire": "PCIE_MIMTXWDATA35", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_4->PCIE_CFGERRAERHEADERLOG91": { + "src_wire": "PCIE_IMUX5_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG91", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_7->PCIE_MIMTXRDATA40": { + "src_wire": "PCIE_IMUX4_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA40", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXRADDR6->PCIE_LOGIC_OUTS_B17_R_2": { + "src_wire": "PCIE_MIMTXRADDR6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_7->PCIE_CFGERRAERHEADERLOG105": { + "src_wire": "PCIE_IMUX7_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG105", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA12->PCIE_LOGIC_OUTS_B0_R_4": { + "src_wire": "PCIE_PIPETX5DATA12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_10->PCIE_TRNTD125": { + "src_wire": "PCIE_IMUX1_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD125", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_16->PCIE_TRNTDLLPDATA6": { + "src_wire": "PCIE_IMUX3_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_19->PCIE_TRNTDLLPDATA16": { + "src_wire": "PCIE_IMUX1_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPH2->PCIE_LOGIC_OUTS_B12_L_2": { + "src_wire": "PCIE_TRNFCNPH2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB18->PCIE_LOGIC_OUTS_B6_R_5": { + "src_wire": "PCIE_DBGVECB18", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_4->PCIE_CFGERRAERHEADERLOG57": { + "src_wire": "PCIE_IMUX11_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG57", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_5->PCIE_MIMTXRDATA20": { + "src_wire": "PCIE_IMUX0_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_10->PCIE_CFGDSN19": { + "src_wire": "PCIE_IMUX10_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLDBGVEC2->PCIE_LOGIC_OUTS_B23_L_15": { + "src_wire": "PCIE_PLDBGVEC2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_L_8->PCIE_PIPERX1DATA9": { + "src_wire": "PCIE_IMUX36_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_R_2->PCIE_CFGMGMTDI2": { + "src_wire": "PCIE_IMUX15_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA8->PCIE_LOGIC_OUTS_B22_R_6": { + "src_wire": "PCIE_MIMTXWDATA8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA6->PCIE_LOGIC_OUTS_B2_L_6": { + "src_wire": "PCIE_PIPETX1DATA6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_R_11->PCIE_CFGVENDID10": { + "src_wire": "PCIE_IMUX17_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO6->PCIE_LOGIC_OUTS_B13_L_9": { + "src_wire": "PCIE_CFGINTERRUPTDO6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD51->PCIE_LOGIC_OUTS_B0_L_18": { + "src_wire": "PCIE_TRNRD51", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_0->PCIE_CFGERRAERHEADERLOG74": { + "src_wire": "PCIE_IMUX13_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG74", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGSCLRK->PCIE_LOGIC_OUTS_B23_L_13": { + "src_wire": "PCIE_DBGSCLRK", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA52->PCIE_LOGIC_OUTS_B20_R_11": { + "src_wire": "PCIE_DBGVECA52", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2COMPLIANCE->PCIE_LOGIC_OUTS_B3_L_14": { + "src_wire": "PCIE_PIPETX2COMPLIANCE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_17->PCIE_MIMRXRDATA10": { + "src_wire": "PCIE_IMUX2_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_7->PCIE_MIMTXRDATA43": { + "src_wire": "PCIE_IMUX7_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA43", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO15->PCIE_LOGIC_OUTS_B17_R_14": { + "src_wire": "PCIE_CFGMGMTDO15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB21->PCIE_LOGIC_OUTS_B18_R_5": { + "src_wire": "PCIE_DBGVECB21", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_L_2->PCIE_CFGREVID6": { + "src_wire": "PCIE_IMUX14_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_4->PCIE_CFGERRAERHEADERLOG55": { + "src_wire": "PCIE_IMUX9_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG55", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_16->PCIE_CFGERRACSN": { + "src_wire": "PCIE_IMUX12_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRACSN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_8->PCIE_CFGERRAERHEADERLOG108": { + "src_wire": "PCIE_IMUX6_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG108", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGSCLRA->PCIE_LOGIC_OUTS_B19_L_10": { + "src_wire": "PCIE_DBGSCLRA", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_14->PCIE_CFGINTERRUPTDI2": { + "src_wire": "PCIE_IMUX14_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB48->PCIE_LOGIC_OUTS_B19_L_3": { + "src_wire": "PCIE_DBGVECB48", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_L_8->PCIE_PIPERX1DATA10": { + "src_wire": "PCIE_IMUX33_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD103->PCIE_LOGIC_OUTS_B0_R_18": { + "src_wire": "PCIE_TRNRD103", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA8->PCIE_LOGIC_OUTS_B9_R_16": { + "src_wire": "PCIE_PIPETX4DATA8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLDBGVEC5->PCIE_LOGIC_OUTS_B22_L_17": { + "src_wire": "PCIE_PLDBGVEC5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_R_4->PCIE_PIPERX7STATUS1": { + "src_wire": "PCIE_IMUX38_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7STATUS1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA56->PCIE_LOGIC_OUTS_B10_R_0": { + "src_wire": "PCIE_MIMTXWDATA56", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPD11->PCIE_LOGIC_OUTS_B13_L_6": { + "src_wire": "PCIE_TRNFCNPD11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX18_R_13->PCIE_CFGVENDID3": { + "src_wire": "PCIE_IMUX18_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_14->PCIE_TRNTD60": { + "src_wire": "PCIE_IMUX2_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD60", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA8->PCIE_LOGIC_OUTS_B9_R_1": { + "src_wire": "PCIE_PIPETX7DATA8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_6->PCIE_TRNTD111": { + "src_wire": "PCIE_IMUX3_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD111", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_5->PCIE_MIMTXRDATA48": { + "src_wire": "PCIE_IMUX4_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA48", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA54->PCIE_LOGIC_OUTS_B13_R_0": { + "src_wire": "PCIE_MIMTXWDATA54", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA36->PCIE_LOGIC_OUTS_B19_R_15": { + "src_wire": "PCIE_DBGVECA36", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_R_10->PCIE_PIPERX5DATA1": { + "src_wire": "PCIE_IMUX36_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_9->PCIE_CFGDSN16": { + "src_wire": "PCIE_IMUX11_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR7->PCIE_LOGIC_OUTS_B7_R_10": { + "src_wire": "PCIE_TL2ERRHDR7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLDBGVEC10->PCIE_LOGIC_OUTS_B21_R_5": { + "src_wire": "PCIE_PLDBGVEC10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA0->PCIE_LOGIC_OUTS_B9_L_18": { + "src_wire": "PCIE_PIPETX0DATA0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_12->PCIE_CFGERRAERHEADERLOG24": { + "src_wire": "PCIE_IMUX11_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_L_16->PCIE_PIPERX2DATA4": { + "src_wire": "PCIE_IMUX39_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_13->PCIE_CFGERRTLPCPLHEADER1": { + "src_wire": "PCIE_IMUX7_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA43->PCIE_LOGIC_OUTS_B19_R_13": { + "src_wire": "PCIE_DBGVECA43", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPD3->PCIE_LOGIC_OUTS_B1_R_1": { + "src_wire": "PCIE_TRNFCPD3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_4->PCIE_TRNTD101": { + "src_wire": "PCIE_IMUX1_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD101", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB15->PCIE_LOGIC_OUTS_B18_R_7": { + "src_wire": "PCIE_DBGVECB15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_R_6->PCIE_PIPERX7DATA3": { + "src_wire": "PCIE_IMUX32_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX18_L_0->PCIE_CFGPORTNUMBER5": { + "src_wire": "PCIE_IMUX18_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD31->PCIE_LOGIC_OUTS_B5_L_13": { + "src_wire": "PCIE_TRNRD31", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_2->PCIE_CFGPMTURNOFFOKN": { + "src_wire": "PCIE_IMUX10_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMTURNOFFOKN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_17->PCIE_TRNTDLLPDATA8": { + "src_wire": "PCIE_IMUX1_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX20_R_12->PCIE_CFGVENDID9": { + "src_wire": "PCIE_IMUX20_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGERRAERHEADERLOGSETN->PCIE_LOGIC_OUTS_B17_R_12": { + "src_wire": "PCIE_CFGERRAERHEADERLOGSETN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNTCFGREQ->PCIE_LOGIC_OUTS_B0_L_5": { + "src_wire": "PCIE_TRNTCFGREQ", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_0->PCIE_PLDIRECTEDLTSSMNEW3": { + "src_wire": "PCIE_IMUX12_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_R_6->PCIE_PIPERX7DATA2": { + "src_wire": "PCIE_IMUX33_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLH4->PCIE_LOGIC_OUTS_B10_L_7": { + "src_wire": "PCIE_TRNFCCPLH4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_7->PCIE_TRNTD114": { + "src_wire": "PCIE_IMUX2_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD114", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA7->PCIE_LOGIC_OUTS_B14_L_13": { + "src_wire": "PCIE_TRNRDLLPDATA7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA12->PCIE_LOGIC_OUTS_B0_L_15": { + "src_wire": "PCIE_PIPETX0DATA12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_14->PCIE_TRNTD59": { + "src_wire": "PCIE_IMUX1_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD59", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_16->PCIE_TRNTDLLPDATA4": { + "src_wire": "PCIE_IMUX1_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA6->PCIE_LOGIC_OUTS_B2_R_2": { + "src_wire": "PCIE_PIPETX7DATA6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_R_5->PCIE_PIPERX7CHANISALIGNED": { + "src_wire": "PCIE_IMUX33_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7CHANISALIGNED", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3CHARISK0->PCIE_LOGIC_OUTS_B16_L_2": { + "src_wire": "PCIE_PIPETX3CHARISK0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_6->PCIE_CFGMGMTDI15": { + "src_wire": "PCIE_IMUX9_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_18->PCIE_CFGERRTLPCPLHEADER21": { + "src_wire": "PCIE_IMUX7_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_R_7->PCIE_PIPERX5DATA12": { + "src_wire": "PCIE_IMUX39_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR42->PCIE_LOGIC_OUTS_B17_L_7": { + "src_wire": "PCIE_TL2ERRHDR42", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXRADDR10->PCIE_LOGIC_OUTS_B8_R_9": { + "src_wire": "PCIE_MIMTXRADDR10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD111->PCIE_LOGIC_OUTS_B1_R_16": { + "src_wire": "PCIE_TRNRD111", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2ELECIDLE->PCIE_LOGIC_OUTS_B3_L_13": { + "src_wire": "PCIE_PIPETX2ELECIDLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX19_R_0->PCIE_CFGPORTNUMBER3": { + "src_wire": "PCIE_IMUX19_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD33->PCIE_LOGIC_OUTS_B9_L_13": { + "src_wire": "PCIE_TRNRD33", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_19->PCIE_MIMRXRDATA17": { + "src_wire": "PCIE_IMUX1_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA46->PCIE_LOGIC_OUTS_B19_R_1": { + "src_wire": "PCIE_MIMTXWDATA46", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXRADDR12->PCIE_LOGIC_OUTS_B21_R_15": { + "src_wire": "PCIE_MIMRXRADDR12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA45->PCIE_LOGIC_OUTS_B21_R_13": { + "src_wire": "PCIE_DBGVECA45", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB51->PCIE_LOGIC_OUTS_B18_L_4": { + "src_wire": "PCIE_DBGVECB51", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_L_19->PCIE_PIPERX0STATUS1": { + "src_wire": "PCIE_IMUX38_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0STATUS1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXRADDR0->PCIE_LOGIC_OUTS_B20_R_4": { + "src_wire": "PCIE_MIMTXRADDR0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR35->PCIE_LOGIC_OUTS_B12_L_5": { + "src_wire": "PCIE_TL2ERRHDR35", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_1->PCIE_CFGERRAERHEADERLOG80": { + "src_wire": "PCIE_IMUX6_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG80", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0POWERDOWN0->PCIE_LOGIC_OUTS_B1_L_17": { + "src_wire": "PCIE_PIPETX0POWERDOWN0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_9->PCIE_CFGDSN15": { + "src_wire": "PCIE_IMUX10_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGROOTCONTROLSYSERRCORRERREN->PCIE_LOGIC_OUTS_B20_L_16": { + "src_wire": "PCIE_CFGROOTCONTROLSYSERRCORRERREN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA57->PCIE_LOGIC_OUTS_B9_R_4": { + "src_wire": "PCIE_MIMTXWDATA57", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_14->PCIE_TRNRFCPRET": { + "src_wire": "PCIE_IMUX0_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNRFCPRET", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPD5->PCIE_LOGIC_OUTS_B3_R_1": { + "src_wire": "PCIE_TRNFCPD5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_L_19->PCIE_PIPERX0DATA8": { + "src_wire": "PCIE_IMUX37_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA15->PCIE_LOGIC_OUTS_B6_R_0": { + "src_wire": "PCIE_PIPETX7DATA15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLAUXPOWEREN->PCIE_LOGIC_OUTS_B19_L_15": { + "src_wire": "PCIE_CFGDEVCONTROLAUXPOWEREN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6COMPLIANCE->PCIE_LOGIC_OUTS_B3_R_14": { + "src_wire": "PCIE_PIPETX6COMPLIANCE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA31->PCIE_LOGIC_OUTS_B22_R_17": { + "src_wire": "PCIE_DBGVECA31", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_3->PCIE_MIMTXRDATA14": { + "src_wire": "PCIE_IMUX2_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPH3->PCIE_LOGIC_OUTS_B3_R_5": { + "src_wire": "PCIE_TRNFCPH3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB52->PCIE_LOGIC_OUTS_B19_L_4": { + "src_wire": "PCIE_DBGVECB52", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMETO->PCIE_LOGIC_OUTS_B17_L_18": { + "src_wire": "PCIE_CFGMSGRECEIVEDPMETO", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTA->PCIE_LOGIC_OUTS_B10_L_16": { + "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTA", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO9->PCIE_LOGIC_OUTS_B14_R_12": { + "src_wire": "PCIE_CFGMGMTDO9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA12->PCIE_LOGIC_OUTS_B0_L_0": { + "src_wire": "PCIE_PIPETX3DATA12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR54->PCIE_LOGIC_OUTS_B11_L_10": { + "src_wire": "PCIE_TL2ERRHDR54", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_1->PCIE_MIMTXRDATA60": { + "src_wire": "PCIE_IMUX6_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA60", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_0->PCIE_PLDIRECTEDLINKCHANGE1": { + "src_wire": "PCIE_IMUX1_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLINKCHANGE1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR32->PCIE_LOGIC_OUTS_B15_L_4": { + "src_wire": "PCIE_TL2ERRHDR32", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGPCIELINKSTATE0->PCIE_LOGIC_OUTS_B11_L_19": { + "src_wire": "PCIE_CFGPCIELINKSTATE0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGSCLRG->PCIE_LOGIC_OUTS_B22_L_11": { + "src_wire": "PCIE_DBGSCLRG", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_R_16->PCIE_PIPERX6DATA5": { + "src_wire": "PCIE_IMUX38_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA11->PCIE_LOGIC_OUTS_B15_R_12": { + "src_wire": "PCIE_PIPETX6DATA11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_6->PCIE_CFGERRAERHEADERLOG47": { + "src_wire": "PCIE_IMUX14_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG47", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR47->PCIE_LOGIC_OUTS_B8_L_9": { + "src_wire": "PCIE_TL2ERRHDR47", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA9->PCIE_LOGIC_OUTS_B13_R_1": { + "src_wire": "PCIE_PIPETX7DATA9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LL2REPLAYTOERR->PCIE_LOGIC_OUTS_B5_R_12": { + "src_wire": "PCIE_LL2REPLAYTOERR", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB46->PCIE_LOGIC_OUTS_B21_L_2": { + "src_wire": "PCIE_DBGVECB46", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_17->PCIE_MIMRXRDATA66": { + "src_wire": "PCIE_IMUX6_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA66", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA3->PCIE_LOGIC_OUTS_B15_R_14": { + "src_wire": "PCIE_PIPETX6DATA3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_6->PCIE_CFGDSN3": { + "src_wire": "PCIE_IMUX10_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_13->PCIE_CFGSUBSYSVENDID12": { + "src_wire": "PCIE_IMUX12_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_11->PCIE_CFGDSN21": { + "src_wire": "PCIE_IMUX8_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD13->PCIE_LOGIC_OUTS_B2_L_8": { + "src_wire": "PCIE_TRNRD13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPH6->PCIE_LOGIC_OUTS_B7_L_3": { + "src_wire": "PCIE_TRNFCNPH6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_1->PCIE_TRNTD84": { + "src_wire": "PCIE_IMUX9_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD84", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNLNKUP->PCIE_LOGIC_OUTS_B0_R_7": { + "src_wire": "PCIE_TRNLNKUP", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXRADDR3->PCIE_LOGIC_OUTS_B16_R_18": { + "src_wire": "PCIE_MIMRXRADDR3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR30->PCIE_LOGIC_OUTS_B13_L_4": { + "src_wire": "PCIE_TL2ERRHDR30", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLDIRECTEDCHANGEDONE->PCIE_LOGIC_OUTS_B0_L_3": { + "src_wire": "PCIE_PLDIRECTEDCHANGEDONE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_R_19->PCIE_PIPERX4STATUS0": { + "src_wire": "PCIE_IMUX39_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4STATUS0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRFATAL->PCIE_LOGIC_OUTS_B8_L_16": { + "src_wire": "PCIE_CFGMSGRECEIVEDERRFATAL", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_3->PCIE_CFGMGMTDI4": { + "src_wire": "PCIE_IMUX10_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_9->PCIE_CFGMGMTDI29": { + "src_wire": "PCIE_IMUX9_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX20_R_13->PCIE_CFGVENDID5": { + "src_wire": "PCIE_IMUX20_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_4->PCIE_TRNTD102": { + "src_wire": "PCIE_IMUX2_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD102", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGBRIDGESERREN->PCIE_LOGIC_OUTS_B17_L_8": { + "src_wire": "PCIE_CFGBRIDGESERREN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETXRATE->PCIE_LOGIC_OUTS_B19_R_11": { + "src_wire": "PCIE_PIPETXRATE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_9->PCIE_CFGDSN13": { + "src_wire": "PCIE_IMUX8_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVSTATUSCORRERRDETECTED->PCIE_LOGIC_OUTS_B16_L_9": { + "src_wire": "PCIE_CFGDEVSTATUSCORRERRDETECTED", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_L_19->PCIE_PIPERX0DATA11": { + "src_wire": "PCIE_IMUX32_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_10->PCIE_CFGERRAERHEADERLOG30": { + "src_wire": "PCIE_IMUX9_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_5->PCIE_CFGFORCECOMMONCLOCKOFF": { + "src_wire": "PCIE_IMUX9_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGFORCECOMMONCLOCKOFF", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_2->PCIE_CFGMGMTDI0": { + "src_wire": "PCIE_IMUX13_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA5->PCIE_LOGIC_OUTS_B4_L_6": { + "src_wire": "PCIE_PIPETX1DATA5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA10->PCIE_LOGIC_OUTS_B11_L_12": { + "src_wire": "PCIE_PIPETX2DATA10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_1->PCIE_CFGERRAERHEADERLOG66": { + "src_wire": "PCIE_IMUX12_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG66", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_5->PCIE_CFGERRAERHEADERLOG94": { + "src_wire": "PCIE_IMUX4_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG94", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_R_17->PCIE_CFGERRINTERNALCORN": { + "src_wire": "PCIE_IMUX17_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRINTERNALCORN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMETOACK->PCIE_LOGIC_OUTS_B16_L_18": { + "src_wire": "PCIE_CFGMSGRECEIVEDPMETOACK", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_3->PCIE_MIMTXRDATA52": { + "src_wire": "PCIE_IMUX6_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA52", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA59->PCIE_LOGIC_OUTS_B11_R_4": { + "src_wire": "PCIE_MIMTXWDATA59", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB63->PCIE_LOGIC_OUTS_B18_L_7": { + "src_wire": "PCIE_DBGVECB63", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_11->PCIE_TRNTSOF": { + "src_wire": "PCIE_IMUX2_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTSOF", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA4->PCIE_LOGIC_OUTS_B17_L_11": { + "src_wire": "PCIE_CFGMSGDATA4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_16->PCIE_CFGERRAERHEADERLOG13": { + "src_wire": "PCIE_IMUX14_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB40->PCIE_LOGIC_OUTS_B19_L_1": { + "src_wire": "PCIE_DBGVECB40", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPD5->PCIE_LOGIC_OUTS_B4_L_5": { + "src_wire": "PCIE_TRNFCNPD5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA4->PCIE_LOGIC_OUTS_B0_L_6": { + "src_wire": "PCIE_PIPETX1DATA4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3COMPLIANCE->PCIE_LOGIC_OUTS_B3_L_3": { + "src_wire": "PCIE_PIPETX3COMPLIANCE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_5->PCIE_CFGERRAERHEADERLOG96": { + "src_wire": "PCIE_IMUX6_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG96", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_L_8->PCIE_PIPERX1STATUS2": { + "src_wire": "PCIE_IMUX35_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1STATUS2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_R_16->PCIE_PIPERX6DATA6": { + "src_wire": "PCIE_IMUX35_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CTRL1_R_1->PCIE_FUNCLVLRSTN": { + "src_wire": "PCIE_CTRL1_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_FUNCLVLRSTN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_18->PCIE_TRNTDLLPDATA12": { + "src_wire": "PCIE_IMUX1_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_R_9->PCIE_PIPERX5DATA5": { + "src_wire": "PCIE_IMUX38_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA11->PCIE_LOGIC_OUTS_B15_L_5": { + "src_wire": "PCIE_PIPETX1DATA11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_15->PCIE_TRNTDLLPDATA0": { + "src_wire": "PCIE_IMUX1_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR59->PCIE_LOGIC_OUTS_B8_L_12": { + "src_wire": "PCIE_TL2ERRHDR59", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPD1->PCIE_LOGIC_OUTS_B8_R_2": { + "src_wire": "PCIE_TRNFCPD1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA14->PCIE_LOGIC_OUTS_B2_R_0": { + "src_wire": "PCIE_PIPETX7DATA14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNREOF->PCIE_LOGIC_OUTS_B7_R_11": { + "src_wire": "PCIE_TRNREOF", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_14->PCIE_TRNTD61": { + "src_wire": "PCIE_IMUX3_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD61", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA5->PCIE_LOGIC_OUTS_B4_L_17": { + "src_wire": "PCIE_PIPETX0DATA5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_8->PCIE_CFGERRAERHEADERLOG39": { + "src_wire": "PCIE_IMUX10_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG39", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_R_9->PCIE_PIPERX5PHYSTATUS": { + "src_wire": "PCIE_IMUX37_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5PHYSTATUS", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_2->PCIE_MIMTXRDATA11": { + "src_wire": "PCIE_IMUX3_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA62->PCIE_LOGIC_OUTS_B14_R_8": { + "src_wire": "PCIE_DBGVECA62", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_10->PCIE_CFGMGMTBYTEENN2": { + "src_wire": "PCIE_IMUX8_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTBYTEENN2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_6->PCIE_CFGERRAERHEADERLOG101": { + "src_wire": "PCIE_IMUX7_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG101", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3POWERDOWN1->PCIE_LOGIC_OUTS_B7_L_2": { + "src_wire": "PCIE_PIPETX3POWERDOWN1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_L_15->PCIE_PIPERX2DATA8": { + "src_wire": "PCIE_IMUX37_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_L_8->PCIE_PIPERX1DATA11": { + "src_wire": "PCIE_IMUX32_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_R_11->PCIE_CFGDSBUSNUMBER5": { + "src_wire": "PCIE_IMUX15_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA3->PCIE_LOGIC_OUTS_B15_L_14": { + "src_wire": "PCIE_PIPETX2DATA3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_L_9->PCIE_PIPERX1DATA4": { + "src_wire": "PCIE_IMUX39_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD47->PCIE_LOGIC_OUTS_B5_L_17": { + "src_wire": "PCIE_TRNRD47", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXRADDR5->PCIE_LOGIC_OUTS_B19_R_6": { + "src_wire": "PCIE_MIMTXRADDR5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA18->PCIE_LOGIC_OUTS_B6_L_16": { + "src_wire": "PCIE_TRNRDLLPDATA18", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_R_7->PCIE_CFGERRAERHEADERLOG43": { + "src_wire": "PCIE_IMUX15_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG43", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA0->PCIE_LOGIC_OUTS_B9_L_7": { + "src_wire": "PCIE_PIPETX1DATA0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_2->PCIE_TRNTD81": { + "src_wire": "PCIE_IMUX10_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD81", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR15->PCIE_LOGIC_OUTS_B8_R_8": { + "src_wire": "PCIE_TL2ERRHDR15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA15->PCIE_LOGIC_OUTS_B6_L_11": { + "src_wire": "PCIE_PIPETX2DATA15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGCOMMANDSERREN->PCIE_LOGIC_OUTS_B16_L_8": { + "src_wire": "PCIE_CFGCOMMANDSERREN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_2->PCIE_MIMTXRDATA10": { + "src_wire": "PCIE_IMUX2_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_L_15->PCIE_PIPERX2DATA9": { + "src_wire": "PCIE_IMUX36_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_1->PCIE_MIMTXRDATA61": { + "src_wire": "PCIE_IMUX7_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA61", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_19->PCIE_TRNTDLLPDATA18": { + "src_wire": "PCIE_IMUX3_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_19->PCIE_TRNTD7": { + "src_wire": "PCIE_IMUX11_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNTBUFAV1->PCIE_LOGIC_OUTS_B5_L_3": { + "src_wire": "PCIE_TRNTBUFAV1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_10->PCIE_CFGSUBSYSVENDID1": { + "src_wire": "PCIE_IMUX13_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLMAXREADREQ1->PCIE_LOGIC_OUTS_B17_L_16": { + "src_wire": "PCIE_CFGDEVCONTROLMAXREADREQ1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB35->PCIE_LOGIC_OUTS_B22_R_0": { + "src_wire": "PCIE_DBGVECB35", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA5->PCIE_LOGIC_OUTS_B4_R_13": { + "src_wire": "PCIE_PIPETX6DATA5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD49->PCIE_LOGIC_OUTS_B9_L_17": { + "src_wire": "PCIE_TRNRD49", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_16->PCIE_CFGERRTLPCPLHEADER11": { + "src_wire": "PCIE_IMUX5_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_R_9->PCIE_PIPERX5CHANISALIGNED": { + "src_wire": "PCIE_IMUX33_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5CHANISALIGNED", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_2->PCIE_MIMTXRDATA54": { + "src_wire": "PCIE_IMUX4_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA54", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_R_17->PCIE_PIPERX6DATA2": { + "src_wire": "PCIE_IMUX33_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_2->PCIE_CFGPMSENDPMETON": { + "src_wire": "PCIE_IMUX11_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMSENDPMETON", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_L_7->PCIE_CFGSUBSYSID12": { + "src_wire": "PCIE_IMUX14_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_5->PCIE_TRNTD104": { + "src_wire": "PCIE_IMUX0_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD104", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLNONFATALREPORTINGEN->PCIE_LOGIC_OUTS_B21_L_12": { + "src_wire": "PCIE_CFGDEVCONTROLNONFATALREPORTINGEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTRDYN->PCIE_LOGIC_OUTS_B15_R_10": { + "src_wire": "PCIE_CFGINTERRUPTRDYN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_6->PCIE_CFGERRAERHEADERLOG46": { + "src_wire": "PCIE_IMUX13_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG46", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWADDR4->PCIE_LOGIC_OUTS_B16_R_19": { + "src_wire": "PCIE_MIMRXWADDR4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_8->PCIE_CFGERRAERHEADERLOG109": { + "src_wire": "PCIE_IMUX7_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG109", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_12->PCIE_CFGDSBUSNUMBER2": { + "src_wire": "PCIE_IMUX16_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD25->PCIE_LOGIC_OUTS_B5_L_11": { + "src_wire": "PCIE_TRNRD25", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX19_R_13->PCIE_CFGVENDID4": { + "src_wire": "PCIE_IMUX19_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA39->PCIE_LOGIC_OUTS_B21_R_2": { + "src_wire": "PCIE_MIMTXWDATA39", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CLK0_R_12->PCIE_USERCLK": { + "src_wire": "PCIE_CLK0_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_USERCLK", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA12->PCIE_LOGIC_OUTS_B0_L_11": { + "src_wire": "PCIE_PIPETX2DATA12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_0->PCIE_PLDIRECTEDLTSSMNEWVLD": { + "src_wire": "PCIE_IMUX8_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEWVLD", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_8->PCIE_CFGERRAERHEADERLOG107": { + "src_wire": "PCIE_IMUX5_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG107", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_R_15->PCIE_PIPERX6DATA8": { + "src_wire": "PCIE_IMUX37_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0CHARISK0->PCIE_LOGIC_OUTS_B16_L_17": { + "src_wire": "PCIE_PIPETX0CHARISK0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA37->PCIE_LOGIC_OUTS_B9_R_15": { + "src_wire": "PCIE_MIMRXWDATA37", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6POWERDOWN0->PCIE_LOGIC_OUTS_B1_R_13": { + "src_wire": "PCIE_PIPETX6POWERDOWN0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_1->PCIE_MIMTXRDATA6": { + "src_wire": "PCIE_IMUX2_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_7->PCIE_MIMTXRDATA29": { + "src_wire": "PCIE_IMUX1_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_R_17->PCIE_CFGERRINTERNALUNCORN": { + "src_wire": "PCIE_IMUX15_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRINTERNALUNCORN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_11->PCIE_TRNTD72": { + "src_wire": "PCIE_IMUX2_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD72", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA10->PCIE_LOGIC_OUTS_B8_L_14": { + "src_wire": "PCIE_TRNRDLLPDATA10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO1->PCIE_LOGIC_OUTS_B12_L_8": { + "src_wire": "PCIE_CFGINTERRUPTDO1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA12->PCIE_LOGIC_OUTS_B0_R_15": { + "src_wire": "PCIE_PIPETX4DATA12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_R_6->PCIE_PIPERX7DATA1": { + "src_wire": "PCIE_IMUX36_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGSCLRJ->PCIE_LOGIC_OUTS_B22_L_13": { + "src_wire": "PCIE_DBGSCLRJ", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_L_9->PCIE_PIPERX1DATA7": { + "src_wire": "PCIE_IMUX34_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPD8->PCIE_LOGIC_OUTS_B8_R_0": { + "src_wire": "PCIE_TRNFCPD8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA11->PCIE_LOGIC_OUTS_B15_L_12": { + "src_wire": "PCIE_PIPETX2DATA11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX21_R_11->PCIE_PLDBGMODE0": { + "src_wire": "PCIE_IMUX21_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDBGMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRRXOVERFLOW->PCIE_LOGIC_OUTS_B18_L_13": { + "src_wire": "PCIE_TL2ERRRXOVERFLOW", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_R_19->PCIE_PIPERX4ELECIDLE": { + "src_wire": "PCIE_IMUX34_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4ELECIDLE", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_L_6->PCIE_PIPERX3DATA2": { + "src_wire": "PCIE_IMUX33_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_16->PCIE_CFGERRCPLUNEXPECTN": { + "src_wire": "PCIE_IMUX10_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRCPLUNEXPECTN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLD1->PCIE_LOGIC_OUTS_B4_L_9": { + "src_wire": "PCIE_TRNFCCPLD1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_7->PCIE_MIMTXRDATA41": { + "src_wire": "PCIE_IMUX5_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA41", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_L_8->PCIE_PIPERX1ELECIDLE": { + "src_wire": "PCIE_IMUX34_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1ELECIDLE", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5POWERDOWN0->PCIE_LOGIC_OUTS_B1_R_6": { + "src_wire": "PCIE_PIPETX5POWERDOWN0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_11->PCIE_CFGMGMTDWADDR0": { + "src_wire": "PCIE_IMUX6_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD38->PCIE_LOGIC_OUTS_B5_L_14": { + "src_wire": "PCIE_TRNRD38", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_L_5->PCIE_PIPERX3DATA7": { + "src_wire": "PCIE_IMUX34_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_15->PCIE_CFGDSN40": { + "src_wire": "PCIE_IMUX11_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN40", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LL2LINKSTATUS1->PCIE_LOGIC_OUTS_B19_R_17": { + "src_wire": "PCIE_LL2LINKSTATUS1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_6->PCIE_MIMTXRDATA45": { + "src_wire": "PCIE_IMUX5_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA45", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_15->PCIE_MIMRXRDATA1": { + "src_wire": "PCIE_IMUX1_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_R_16->PCIE_PIPERX6VALID": { + "src_wire": "PCIE_IMUX36_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6VALID", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA41->PCIE_LOGIC_OUTS_B18_R_3": { + "src_wire": "PCIE_MIMTXWDATA41", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA11->PCIE_LOGIC_OUTS_B15_L_1": { + "src_wire": "PCIE_PIPETX3DATA11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA7->PCIE_LOGIC_OUTS_B6_L_6": { + "src_wire": "PCIE_PIPETX1DATA7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_R_5->PCIE_PIPERX7PHYSTATUS": { + "src_wire": "PCIE_IMUX37_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7PHYSTATUS", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6CHARISK1->PCIE_LOGIC_OUTS_B16_R_11": { + "src_wire": "PCIE_PIPETX6CHARISK1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_19->PCIE_CFGERRTLPCPLHEADER24": { + "src_wire": "PCIE_IMUX6_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_8->PCIE_CFGERRAERHEADERLOG38": { + "src_wire": "PCIE_IMUX9_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG38", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_10->PCIE_PIPERX5CHARISK0": { + "src_wire": "PCIE_IMUX16_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5CHARISK0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_16->PCIE_CFGDSN44": { + "src_wire": "PCIE_IMUX11_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN44", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_R_1->PCIE_CFGDSFUNCTIONNUMBER0": { + "src_wire": "PCIE_IMUX17_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSFUNCTIONNUMBER0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_14->PCIE_CFGERRAERHEADERLOG14": { + "src_wire": "PCIE_IMUX9_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA9->PCIE_LOGIC_OUTS_B13_L_1": { + "src_wire": "PCIE_PIPETX3DATA9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA0->PCIE_LOGIC_OUTS_B9_R_7": { + "src_wire": "PCIE_PIPETX5DATA0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRSOF->PCIE_LOGIC_OUTS_B5_R_11": { + "src_wire": "PCIE_TRNRSOF", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_18->PCIE_TRNTD2": { + "src_wire": "PCIE_IMUX10_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_7->PCIE_CFGDSN8": { + "src_wire": "PCIE_IMUX11_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_R_17->PCIE_PIPERX6DATA1": { + "src_wire": "PCIE_IMUX36_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_L_15->PCIE_PIPERX2STATUS0": { + "src_wire": "PCIE_IMUX39_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2STATUS0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD24->PCIE_LOGIC_OUTS_B3_L_11": { + "src_wire": "PCIE_TRNRD24", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO12->PCIE_LOGIC_OUTS_B12_R_14": { + "src_wire": "PCIE_CFGMGMTDO12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7CHARISK0->PCIE_LOGIC_OUTS_B16_R_2": { + "src_wire": "PCIE_PIPETX7CHARISK0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_19->PCIE_MIMRXRDATA19": { + "src_wire": "PCIE_IMUX3_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_7->PCIE_CFGSUBSYSID10": { + "src_wire": "PCIE_IMUX12_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR34->PCIE_LOGIC_OUTS_B10_L_5": { + "src_wire": "PCIE_TL2ERRHDR34", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_4->PCIE_CFGMGMTDI10": { + "src_wire": "PCIE_IMUX7_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB62->PCIE_LOGIC_OUTS_B21_L_6": { + "src_wire": "PCIE_DBGVECB62", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_7->PCIE_CFGMGMTDI22": { + "src_wire": "PCIE_IMUX13_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_4->PCIE_MIMTXRDATA19": { + "src_wire": "PCIE_IMUX3_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA49->PCIE_LOGIC_OUTS_B21_R_12": { + "src_wire": "PCIE_DBGVECA49", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_17->PCIE_MIMRXRDATA64": { + "src_wire": "PCIE_IMUX4_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA64", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLDBGVEC11->PCIE_LOGIC_OUTS_B22_R_4": { + "src_wire": "PCIE_PLDBGVEC11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_L_16->PCIE_PIPERX2PHYSTATUS": { + "src_wire": "PCIE_IMUX37_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2PHYSTATUS", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA1->PCIE_LOGIC_OUTS_B13_R_18": { + "src_wire": "PCIE_PIPETX4DATA1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA10->PCIE_LOGIC_OUTS_B11_R_1": { + "src_wire": "PCIE_PIPETX7DATA10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA9->PCIE_LOGIC_OUTS_B21_R_8": { + "src_wire": "PCIE_MIMTXWDATA9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA16->PCIE_LOGIC_OUTS_B4_L_16": { + "src_wire": "PCIE_TRNRDLLPDATA16", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLD4->PCIE_LOGIC_OUTS_B7_L_9": { + "src_wire": "PCIE_TRNFCCPLD4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNTDSTRDY1->PCIE_LOGIC_OUTS_B1_R_15": { + "src_wire": "PCIE_TRNTDSTRDY1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_L_4->PCIE_PIPERX3DATA9": { + "src_wire": "PCIE_IMUX36_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_17->PCIE_MIMRXRDATA67": { + "src_wire": "PCIE_IMUX7_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA67", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTRDWRDONEN->PCIE_LOGIC_OUTS_B16_R_12": { + "src_wire": "PCIE_CFGMGMTRDWRDONEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_0->PCIE_PLDIRECTEDLINKCHANGE0": { + "src_wire": "PCIE_IMUX0_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLINKCHANGE0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_15->PCIE_MIMRXRDATA2": { + "src_wire": "PCIE_IMUX2_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_L_5->PCIE_PIPERX3DATA5": { + "src_wire": "PCIE_IMUX38_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_17->PCIE_MIMRXRDATA65": { + "src_wire": "PCIE_IMUX5_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA65", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPD3->PCIE_LOGIC_OUTS_B10_L_4": { + "src_wire": "PCIE_TRNFCNPD3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD104->PCIE_LOGIC_OUTS_B2_R_18": { + "src_wire": "PCIE_TRNRD104", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRBARHIT0->PCIE_LOGIC_OUTS_B0_R_9": { + "src_wire": "PCIE_TRNRBARHIT0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD107->PCIE_LOGIC_OUTS_B8_R_17": { + "src_wire": "PCIE_TRNRD107", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA25->PCIE_LOGIC_OUTS_B7_L_18": { + "src_wire": "PCIE_TRNRDLLPDATA25", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA8->PCIE_LOGIC_OUTS_B18_L_12": { + "src_wire": "PCIE_CFGMSGDATA8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA14->PCIE_LOGIC_OUTS_B21_R_6": { + "src_wire": "PCIE_MIMTXWDATA14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_11->PCIE_TRNTREM1": { + "src_wire": "PCIE_IMUX1_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTREM1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA26->PCIE_LOGIC_OUTS_B5_R_6": { + "src_wire": "PCIE_MIMTXWDATA26", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX18_R_11->PCIE_CFGVENDID11": { + "src_wire": "PCIE_IMUX18_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_19->PCIE_CFGERRTLPCPLHEADER25": { + "src_wire": "PCIE_IMUX7_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_12->PCIE_TRNTERRFWD": { + "src_wire": "PCIE_IMUX2_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTERRFWD", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB25->PCIE_LOGIC_OUTS_B19_R_4": { + "src_wire": "PCIE_DBGVECB25", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_4->PCIE_TRNTD100": { + "src_wire": "PCIE_IMUX0_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD100", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_18->PCIE_TRNTDLLPDATA11": { + "src_wire": "PCIE_IMUX0_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA31->PCIE_LOGIC_OUTS_B7_R_9": { + "src_wire": "PCIE_MIMTXWDATA31", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLTXPMSTATE0->PCIE_LOGIC_OUTS_B17_L_0": { + "src_wire": "PCIE_PLTXPMSTATE0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LL2PROTOCOLERR->PCIE_LOGIC_OUTS_B12_R_13": { + "src_wire": "PCIE_LL2PROTOCOLERR", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_R_8->PCIE_PIPERX5STATUS1": { + "src_wire": "PCIE_IMUX38_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5STATUS1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_17->PCIE_PIPERX6CHARISK0": { + "src_wire": "PCIE_IMUX16_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6CHARISK0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLLTSSMSTATE5->PCIE_LOGIC_OUTS_B12_L_0": { + "src_wire": "PCIE_PLLTSSMSTATE5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_18->PCIE_MIMRXRDATA13": { + "src_wire": "PCIE_IMUX1_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPD7->PCIE_LOGIC_OUTS_B7_R_0": { + "src_wire": "PCIE_TRNFCPD7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB13->PCIE_LOGIC_OUTS_B14_R_7": { + "src_wire": "PCIE_DBGVECB13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA0->PCIE_LOGIC_OUTS_B9_L_3": { + "src_wire": "PCIE_PIPETX3DATA0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA29->PCIE_LOGIC_OUTS_B20_R_17": { + "src_wire": "PCIE_DBGVECA29", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_18->PCIE_TRNTD3": { + "src_wire": "PCIE_IMUX11_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_L_11->PCIE_CFGSUBSYSVENDID6": { + "src_wire": "PCIE_IMUX14_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD19->PCIE_LOGIC_OUTS_B0_L_10": { + "src_wire": "PCIE_TRNRD19", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_5->PCIE_CFGDSN0": { + "src_wire": "PCIE_IMUX11_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD48->PCIE_LOGIC_OUTS_B8_L_17": { + "src_wire": "PCIE_TRNRD48", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_8->PCIE_CFGDSN11": { + "src_wire": "PCIE_IMUX10_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_11->PCIE_TRNTD70": { + "src_wire": "PCIE_IMUX0_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD70", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA59->PCIE_LOGIC_OUTS_B14_R_18": { + "src_wire": "PCIE_MIMRXWDATA59", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7ELECIDLE->PCIE_LOGIC_OUTS_B3_R_2": { + "src_wire": "PCIE_PIPETX7ELECIDLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLMAXREADREQ2->PCIE_LOGIC_OUTS_B18_L_16": { + "src_wire": "PCIE_CFGDEVCONTROLMAXREADREQ2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7POWERDOWN1->PCIE_LOGIC_OUTS_B7_R_2": { + "src_wire": "PCIE_PIPETX7POWERDOWN1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD127->PCIE_LOGIC_OUTS_B3_R_12": { + "src_wire": "PCIE_TRNRD127", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA22->PCIE_LOGIC_OUTS_B17_R_6": { + "src_wire": "PCIE_MIMTXWDATA22", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_R_15->PCIE_PIPERX6DATA11": { + "src_wire": "PCIE_IMUX32_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA0->PCIE_LOGIC_OUTS_B12_L_10": { + "src_wire": "PCIE_CFGMSGDATA0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_10->PCIE_CFGERRAERHEADERLOG31": { + "src_wire": "PCIE_IMUX10_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_10->PCIE_CFGMGMTBYTEENN1": { + "src_wire": "PCIE_IMUX7_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTBYTEENN1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_6->PCIE_CFGMGMTDI18": { + "src_wire": "PCIE_IMUX12_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCNPD7->PCIE_LOGIC_OUTS_B6_L_5": { + "src_wire": "PCIE_TRNFCNPD7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_R_16->PCIE_PIPERX6DATA4": { + "src_wire": "PCIE_IMUX39_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNTDSTRDY2->PCIE_LOGIC_OUTS_B3_R_0": { + "src_wire": "PCIE_TRNTDSTRDY2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWADDR1->PCIE_LOGIC_OUTS_B6_R_1": { + "src_wire": "PCIE_MIMTXWADDR1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_R_14->PCIE_PIPERX6DATA12": { + "src_wire": "PCIE_IMUX39_R_14", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXRADDR5->PCIE_LOGIC_OUTS_B8_R_19": { + "src_wire": "PCIE_MIMRXRADDR5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_L_9->PCIE_PIPERX1DATA6": { + "src_wire": "PCIE_IMUX35_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB7->PCIE_LOGIC_OUTS_B23_R_14": { + "src_wire": "PCIE_DBGVECB7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_L_9->PCIE_PIPERX1VALID": { + "src_wire": "PCIE_IMUX36_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1VALID", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA13->PCIE_LOGIC_OUTS_B4_R_11": { + "src_wire": "PCIE_PIPETX6DATA13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD18->PCIE_LOGIC_OUTS_B3_L_9": { + "src_wire": "PCIE_TRNRD18", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_L_11->PCIE_CFGSUBSYSVENDID7": { + "src_wire": "PCIE_IMUX15_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CLK1_R_12->PCIE_USERCLK2": { + "src_wire": "PCIE_CLK1_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_USERCLK2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWADDR0->PCIE_LOGIC_OUTS_B23_R_7": { + "src_wire": "PCIE_MIMTXWADDR0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_3->PCIE_CFGMGMTDI6": { + "src_wire": "PCIE_IMUX12_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS->PCIE_LOGIC_OUTS_B14_L_19": { + "src_wire": "PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLLINKGEN2CAP->PCIE_LOGIC_OUTS_B3_L_1": { + "src_wire": "PCIE_PLLINKGEN2CAP", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB1->PCIE_LOGIC_OUTS_B17_R_8": { + "src_wire": "PCIE_DBGVECB1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA10->PCIE_LOGIC_OUTS_B11_R_5": { + "src_wire": "PCIE_PIPETX5DATA10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR23->PCIE_LOGIC_OUTS_B15_L_2": { + "src_wire": "PCIE_TL2ERRHDR23", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD26->PCIE_LOGIC_OUTS_B7_L_11": { + "src_wire": "PCIE_TRNRD26", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_10->PCIE_CFGERRAERHEADERLOG33": { + "src_wire": "PCIE_IMUX12_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG33", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLCORRERRREPORTINGEN->PCIE_LOGIC_OUTS_B20_L_12": { + "src_wire": "PCIE_CFGDEVCONTROLCORRERRREPORTINGEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWADDR3->PCIE_LOGIC_OUTS_B7_R_16": { + "src_wire": "PCIE_MIMRXWADDR3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_13->PCIE_CFGERRAERHEADERLOG18": { + "src_wire": "PCIE_IMUX9_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD56->PCIE_LOGIC_OUTS_B1_L_19": { + "src_wire": "PCIE_TRNRD56", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD29->PCIE_LOGIC_OUTS_B2_L_12": { + "src_wire": "PCIE_TRNRD29", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_11->PCIE_CFGDSBUSNUMBER3": { + "src_wire": "PCIE_IMUX13_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLLINKPARTNERGEN2SUPPORTED->PCIE_LOGIC_OUTS_B5_L_2": { + "src_wire": "PCIE_PLLINKPARTNERGEN2SUPPORTED", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_15->PCIE_CFGERRCORN": { + "src_wire": "PCIE_IMUX9_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRCORN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_10->PCIE_CFGERRAERHEADERLOG114": { + "src_wire": "PCIE_IMUX4_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG114", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLD9->PCIE_LOGIC_OUTS_B8_L_11": { + "src_wire": "PCIE_TRNFCCPLD9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD110->PCIE_LOGIC_OUTS_B0_R_16": { + "src_wire": "PCIE_TRNRD110", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX19_R_12->PCIE_CFGVENDID8": { + "src_wire": "PCIE_IMUX19_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_L_3->PCIE_PIPERX3DATA13": { + "src_wire": "PCIE_IMUX38_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWADDR12->PCIE_LOGIC_OUTS_B10_R_1": { + "src_wire": "PCIE_MIMTXWADDR12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPD11->PCIE_LOGIC_OUTS_B6_L_1": { + "src_wire": "PCIE_TRNFCPD11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_15->PCIE_CFGERRCPLTIMEOUTN": { + "src_wire": "PCIE_IMUX12_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRCPLTIMEOUTN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD44->PCIE_LOGIC_OUTS_B1_L_16": { + "src_wire": "PCIE_TRNRD44", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA25->PCIE_LOGIC_OUTS_B7_R_18": { + "src_wire": "PCIE_DBGVECA25", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD102->PCIE_LOGIC_OUTS_B6_R_19": { + "src_wire": "PCIE_TRNRD102", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX19_R_11->PCIE_CFGVENDID12": { + "src_wire": "PCIE_IMUX19_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA24->PCIE_LOGIC_OUTS_B18_R_6": { + "src_wire": "PCIE_MIMTXWDATA24", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_9->PCIE_CFGERRAERHEADERLOG113": { + "src_wire": "PCIE_IMUX7_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG113", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR0->PCIE_LOGIC_OUTS_B6_R_12": { + "src_wire": "PCIE_TL2ERRHDR0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_9->PCIE_TRNTD122": { + "src_wire": "PCIE_IMUX2_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD122", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB34->PCIE_LOGIC_OUTS_B22_R_1": { + "src_wire": "PCIE_DBGVECB34", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECC2->PCIE_LOGIC_OUTS_B21_L_7": { + "src_wire": "PCIE_DBGVECC2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_6->PCIE_MIMTXRDATA26": { + "src_wire": "PCIE_IMUX2_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_6->PCIE_MIMTXRDATA46": { + "src_wire": "PCIE_IMUX6_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA46", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_L_6->PCIE_CFGSUBSYSID9": { + "src_wire": "PCIE_IMUX15_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_L_8->PCIE_PIPERX1DATA8": { + "src_wire": "PCIE_IMUX37_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_R_15->PCIE_PIPERX6DATA10": { + "src_wire": "PCIE_IMUX33_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA5->PCIE_LOGIC_OUTS_B12_L_13": { + "src_wire": "PCIE_TRNRDLLPDATA5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA10->PCIE_LOGIC_OUTS_B11_R_12": { + "src_wire": "PCIE_PIPETX6DATA10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA7->PCIE_LOGIC_OUTS_B6_L_13": { + "src_wire": "PCIE_PIPETX2DATA7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_12->PCIE_CFGERRAERHEADERLOG125": { + "src_wire": "PCIE_IMUX7_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG125", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_5->PCIE_CFGERRAERHEADERLOG97": { + "src_wire": "PCIE_IMUX7_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG97", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECC4->PCIE_LOGIC_OUTS_B19_L_8": { + "src_wire": "PCIE_DBGVECC4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_18->PCIE_TRNTD1": { + "src_wire": "PCIE_IMUX9_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPERX4POLARITY->PCIE_LOGIC_OUTS_B1_R_18": { + "src_wire": "PCIE_PIPERX4POLARITY", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXREN->PCIE_LOGIC_OUTS_B8_R_6": { + "src_wire": "PCIE_MIMTXREN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_L_7->PCIE_PIPERX1DATA14": { + "src_wire": "PCIE_IMUX35_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_L_6->PCIE_CFGSUBSYSID8": { + "src_wire": "PCIE_IMUX14_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGERRCPLRDYN->PCIE_LOGIC_OUTS_B14_R_10": { + "src_wire": "PCIE_CFGERRCPLRDYN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO31->PCIE_LOGIC_OUTS_B18_R_14": { + "src_wire": "PCIE_CFGMGMTDO31", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA4->PCIE_LOGIC_OUTS_B0_R_6": { + "src_wire": "PCIE_PIPETX5DATA4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGSCLRH->PCIE_LOGIC_OUTS_B22_L_12": { + "src_wire": "PCIE_DBGSCLRH", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_L_6->PCIE_PIPERX3DATA0": { + "src_wire": "PCIE_IMUX37_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_14->PCIE_CFGERRTLPCPLHEADER3": { + "src_wire": "PCIE_IMUX5_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_3->PCIE_MIMTXRDATA51": { + "src_wire": "PCIE_IMUX5_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA51", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_12->PCIE_CFGMGMTDWADDR3": { + "src_wire": "PCIE_IMUX5_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA53->PCIE_LOGIC_OUTS_B11_R_17": { + "src_wire": "PCIE_MIMRXWDATA53", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_19->PCIE_TRNTDLLPDATA15": { + "src_wire": "PCIE_IMUX0_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_1->PCIE_PLDIRECTEDLTSSMNEW4": { + "src_wire": "PCIE_IMUX0_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA55->PCIE_LOGIC_OUTS_B20_R_2": { + "src_wire": "PCIE_MIMTXWDATA55", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD54->PCIE_LOGIC_OUTS_B5_L_18": { + "src_wire": "PCIE_TRNRD54", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA54->PCIE_LOGIC_OUTS_B5_R_16": { + "src_wire": "PCIE_MIMRXWDATA54", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_14->PCIE_CFGERRTLPCPLHEADER2": { + "src_wire": "PCIE_IMUX4_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_17->PCIE_CFGDSN47": { + "src_wire": "PCIE_IMUX10_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN47", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_R_10->PCIE_PIPERX5DATA3": { + "src_wire": "PCIE_IMUX32_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA65->PCIE_LOGIC_OUTS_B10_R_5": { + "src_wire": "PCIE_MIMTXWDATA65", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGROOTCONTROLPMEINTEN->PCIE_LOGIC_OUTS_B16_L_19": { + "src_wire": "PCIE_CFGROOTCONTROLPMEINTEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECC11->PCIE_LOGIC_OUTS_B18_L_10": { + "src_wire": "PCIE_DBGVECC11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CTRL0_R_3->PCIE_PLRSTN": { + "src_wire": "PCIE_CTRL0_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_PLRSTN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_3->PCIE_TRNTD99": { + "src_wire": "PCIE_IMUX3_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD99", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLLTSSMSTATE3->PCIE_LOGIC_OUTS_B10_L_0": { + "src_wire": "PCIE_PLLTSSMSTATE3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_8->PCIE_CFGDSN9": { + "src_wire": "PCIE_IMUX8_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR19->PCIE_LOGIC_OUTS_B8_L_1": { + "src_wire": "PCIE_TL2ERRHDR19", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_7->PCIE_CFGMGMTDI20": { + "src_wire": "PCIE_IMUX11_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_4->PCIE_CFGFORCEMPS1": { + "src_wire": "PCIE_IMUX11_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGFORCEMPS1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA60->PCIE_LOGIC_OUTS_B12_R_1": { + "src_wire": "PCIE_MIMTXWDATA60", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD36->PCIE_LOGIC_OUTS_B2_L_14": { + "src_wire": "PCIE_TRNRD36", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO1->PCIE_LOGIC_OUTS_B12_R_10": { + "src_wire": "PCIE_CFGMGMTDO1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_12->PCIE_TRNTD69": { + "src_wire": "PCIE_IMUX3_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD69", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_R_15->PCIE_PIPERX6STATUS1": { + "src_wire": "PCIE_IMUX38_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6STATUS1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD105->PCIE_LOGIC_OUTS_B5_R_18": { + "src_wire": "PCIE_TRNRD105", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_R_18->PCIE_PIPERX4DATA14": { + "src_wire": "PCIE_IMUX35_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_R_8->PCIE_PIPERX5STATUS2": { + "src_wire": "PCIE_IMUX35_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5STATUS2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWADDR5->PCIE_LOGIC_OUTS_B14_R_3": { + "src_wire": "PCIE_MIMTXWADDR5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_L_16->PCIE_PIPERX2DATA6": { + "src_wire": "PCIE_IMUX35_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX21_R_12->PCIE_DBGSUBMODE": { + "src_wire": "PCIE_IMUX21_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_DBGSUBMODE", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_10->PCIE_CFGDSN18": { + "src_wire": "PCIE_IMUX9_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_11->PCIE_CFGMGMTDWADDR2": { + "src_wire": "PCIE_IMUX8_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD114->PCIE_LOGIC_OUTS_B7_R_15": { + "src_wire": "PCIE_TRNRD114", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO6->PCIE_LOGIC_OUTS_B8_R_12": { + "src_wire": "PCIE_CFGMGMTDO6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXRADDR1->PCIE_LOGIC_OUTS_B11_R_6": { + "src_wire": "PCIE_MIMTXRADDR1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA2->PCIE_LOGIC_OUTS_B11_R_18": { + "src_wire": "PCIE_PIPETX4DATA2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_11->PCIE_CFGERRAERHEADERLOG28": { + "src_wire": "PCIE_IMUX11_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA43->PCIE_LOGIC_OUTS_B19_R_3": { + "src_wire": "PCIE_MIMTXWDATA43", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_R_0->PCIE_TRNTD87": { + "src_wire": "PCIE_IMUX8_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD87", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLDBGVEC1->PCIE_LOGIC_OUTS_B23_L_14": { + "src_wire": "PCIE_PLDBGVEC1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX20_R_2->PCIE_CFGDSDEVICENUMBER3": { + "src_wire": "PCIE_IMUX20_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSDEVICENUMBER3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRBARHIT2->PCIE_LOGIC_OUTS_B2_R_9": { + "src_wire": "PCIE_TRNRBARHIT2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_19->PCIE_CFGDSN55": { + "src_wire": "PCIE_IMUX10_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN55", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_9->PCIE_MIMTXRDATA67": { + "src_wire": "PCIE_IMUX5_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA67", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPERX1POLARITY->PCIE_LOGIC_OUTS_B1_L_7": { + "src_wire": "PCIE_PIPERX1POLARITY", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX18_R_2->PCIE_CFGERRAERHEADERLOG64": { + "src_wire": "PCIE_IMUX18_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG64", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_1->PCIE_CFGDSDEVICENUMBER4": { + "src_wire": "PCIE_IMUX16_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSDEVICENUMBER4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWADDR8->PCIE_LOGIC_OUTS_B8_R_16": { + "src_wire": "PCIE_MIMRXWADDR8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB55->PCIE_LOGIC_OUTS_B18_L_5": { + "src_wire": "PCIE_DBGVECB55", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR26->PCIE_LOGIC_OUTS_B14_L_3": { + "src_wire": "PCIE_TL2ERRHDR26", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_12->PCIE_CFGDSN28": { + "src_wire": "PCIE_IMUX11_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECC5->PCIE_LOGIC_OUTS_B20_L_8": { + "src_wire": "PCIE_DBGVECC5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_R_16->PCIE_PIPERX6PHYSTATUS": { + "src_wire": "PCIE_IMUX37_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6PHYSTATUS", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_18->PCIE_CFGDSN51": { + "src_wire": "PCIE_IMUX10_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN51", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_2->PCIE_CFGREVID5": { + "src_wire": "PCIE_IMUX13_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA8->PCIE_LOGIC_OUTS_B6_L_14": { + "src_wire": "PCIE_TRNRDLLPDATA8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR20->PCIE_LOGIC_OUTS_B10_L_1": { + "src_wire": "PCIE_TL2ERRHDR20", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_2->PCIE_CFGERRAERHEADERLOG82": { + "src_wire": "PCIE_IMUX4_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG82", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCCPLD6->PCIE_LOGIC_OUTS_B5_L_10": { + "src_wire": "PCIE_TRNFCCPLD6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_19->PCIE_TRNTD6": { + "src_wire": "PCIE_IMUX10_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNTERRDROP->PCIE_LOGIC_OUTS_B2_L_3": { + "src_wire": "PCIE_TRNTERRDROP", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_10->PCIE_CFGERRAERHEADERLOG117": { + "src_wire": "PCIE_IMUX7_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG117", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETXRCVRDET->PCIE_LOGIC_OUTS_B15_R_9": { + "src_wire": "PCIE_PIPETXRCVRDET", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA39->PCIE_LOGIC_OUTS_B20_R_14": { + "src_wire": "PCIE_DBGVECA39", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_9->PCIE_CFGDSN14": { + "src_wire": "PCIE_IMUX9_L_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_12->PCIE_TRNTSRCRDY": { + "src_wire": "PCIE_IMUX0_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTSRCRDY", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSLINKTRAINING->PCIE_LOGIC_OUTS_B21_L_18": { + "src_wire": "PCIE_CFGLINKSTATUSLINKTRAINING", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA33->PCIE_LOGIC_OUTS_B22_R_16": { + "src_wire": "PCIE_DBGVECA33", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3ELECIDLE->PCIE_LOGIC_OUTS_B3_L_2": { + "src_wire": "PCIE_PIPETX3ELECIDLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTB->PCIE_LOGIC_OUTS_B14_L_16": { + "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTB", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA4->PCIE_LOGIC_OUTS_B0_R_2": { + "src_wire": "PCIE_PIPETX7DATA4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA22->PCIE_LOGIC_OUTS_B21_R_19": { + "src_wire": "PCIE_DBGVECA22", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_2->PCIE_CFGPMFORCESTATE1": { + "src_wire": "PCIE_IMUX8_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMFORCESTATE1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1CHARISK0->PCIE_LOGIC_OUTS_B16_L_6": { + "src_wire": "PCIE_PIPETX1CHARISK0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD108->PCIE_LOGIC_OUTS_B9_R_17": { + "src_wire": "PCIE_TRNRD108", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_9->PCIE_CFGMGMTDI30": { + "src_wire": "PCIE_IMUX10_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_5->PCIE_CFGMGMTDI13": { + "src_wire": "PCIE_IMUX9_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA0->PCIE_LOGIC_OUTS_B4_L_12": { + "src_wire": "PCIE_TRNRDLLPDATA0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB6->PCIE_LOGIC_OUTS_B22_R_13": { + "src_wire": "PCIE_DBGVECB6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO2->PCIE_LOGIC_OUTS_B13_L_8": { + "src_wire": "PCIE_CFGINTERRUPTDO2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTA->PCIE_LOGIC_OUTS_B12_L_16": { + "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTA", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA7->PCIE_LOGIC_OUTS_B6_L_2": { + "src_wire": "PCIE_PIPETX3DATA7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD118->PCIE_LOGIC_OUTS_B4_R_14": { + "src_wire": "PCIE_TRNRD118", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLSELLNKWIDTH0->PCIE_LOGIC_OUTS_B3_L_0": { + "src_wire": "PCIE_PLSELLNKWIDTH0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_L_16->PCIE_PIPERX2VALID": { + "src_wire": "PCIE_IMUX36_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2VALID", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA6->PCIE_LOGIC_OUTS_B16_L_12": { + "src_wire": "PCIE_CFGMSGDATA6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_18->PCIE_MIMRXRDATA63": { + "src_wire": "PCIE_IMUX7_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA63", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA46->PCIE_LOGIC_OUTS_B18_R_12": { + "src_wire": "PCIE_DBGVECA46", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA15->PCIE_LOGIC_OUTS_B6_R_11": { + "src_wire": "PCIE_PIPETX6DATA15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA9->PCIE_LOGIC_OUTS_B13_L_5": { + "src_wire": "PCIE_PIPETX1DATA9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA13->PCIE_LOGIC_OUTS_B4_L_15": { + "src_wire": "PCIE_PIPETX0DATA13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_L_5->PCIE_TRNTD105": { + "src_wire": "PCIE_IMUX1_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD105", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR37->PCIE_LOGIC_OUTS_B15_L_6": { + "src_wire": "PCIE_TL2ERRHDR37", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_L_17->PCIE_PIPERX2DATA0": { + "src_wire": "PCIE_IMUX37_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_15->PCIE_TRNTD55": { + "src_wire": "PCIE_IMUX5_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD55", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_0->PCIE_PLDIRECTEDLINKWIDTH1": { + "src_wire": "PCIE_IMUX3_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLINKWIDTH1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_R_12->PCIE_CFGDSBUSNUMBER1": { + "src_wire": "PCIE_IMUX15_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_1->PCIE_MIMTXRDATA59": { + "src_wire": "PCIE_IMUX5_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA59", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRBARHIT1->PCIE_LOGIC_OUTS_B1_R_9": { + "src_wire": "PCIE_TRNRBARHIT1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA14->PCIE_LOGIC_OUTS_B2_L_0": { + "src_wire": "PCIE_PIPETX3DATA14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPH0->PCIE_LOGIC_OUTS_B2_R_7": { + "src_wire": "PCIE_TRNFCPH0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA43->PCIE_LOGIC_OUTS_B19_R_18": { + "src_wire": "PCIE_MIMRXWDATA43", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_7->PCIE_MIMTXRDATA42": { + "src_wire": "PCIE_IMUX6_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA42", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR29->PCIE_LOGIC_OUTS_B12_L_4": { + "src_wire": "PCIE_TL2ERRHDR29", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGAERROOTERRCORRERRREPORTINGEN->PCIE_LOGIC_OUTS_B19_L_19": { + "src_wire": "PCIE_CFGAERROOTERRCORRERRREPORTINGEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD101->PCIE_LOGIC_OUTS_B4_R_19": { + "src_wire": "PCIE_TRNRD101", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD112->PCIE_LOGIC_OUTS_B3_R_15": { + "src_wire": "PCIE_TRNRD112", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA17->PCIE_LOGIC_OUTS_B5_R_7": { + "src_wire": "PCIE_MIMTXWDATA17", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA34->PCIE_LOGIC_OUTS_B10_R_15": { + "src_wire": "PCIE_DBGVECA34", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_R_5->PCIE_PIPERX7DATA7": { + "src_wire": "PCIE_IMUX34_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CLK0_R_11->PCIE_PIPECLK": { + "src_wire": "PCIE_CLK0_R_11", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPECLK", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DRPDO8->PCIE_LOGIC_OUTS_B21_L_19": { + "src_wire": "PCIE_DRPDO8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_15->PCIE_CFGERRURN": { + "src_wire": "PCIE_IMUX10_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRURN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB16->PCIE_LOGIC_OUTS_B9_R_6": { + "src_wire": "PCIE_DBGVECB16", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE->PCIE_LOGIC_OUTS_B22_L_15": { + "src_wire": "PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_10->PCIE_TRNTD127": { + "src_wire": "PCIE_IMUX3_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD127", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA13->PCIE_LOGIC_OUTS_B5_R_9": { + "src_wire": "PCIE_MIMTXWDATA13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA11->PCIE_LOGIC_OUTS_B18_R_9": { + "src_wire": "PCIE_MIMTXWDATA11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_18->PCIE_MIMRXRDATA12": { + "src_wire": "PCIE_IMUX0_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PL2RXPMSTATE0->PCIE_LOGIC_OUTS_B13_R_19": { + "src_wire": "PCIE_PL2RXPMSTATE0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB49->PCIE_LOGIC_OUTS_B20_L_3": { + "src_wire": "PCIE_DBGVECB49", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB44->PCIE_LOGIC_OUTS_B19_L_2": { + "src_wire": "PCIE_DBGVECB44", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_L_15->PCIE_PIPERX2STATUS2": { + "src_wire": "PCIE_IMUX35_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2STATUS2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_L_4->PCIE_PIPERX3DATA10": { + "src_wire": "PCIE_IMUX33_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_3->PCIE_CFGERRAERHEADERLOG87": { + "src_wire": "PCIE_IMUX5_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG87", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO7->PCIE_LOGIC_OUTS_B10_R_12": { + "src_wire": "PCIE_CFGMGMTDO7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_19->PCIE_TRNTDLLPDATA17": { + "src_wire": "PCIE_IMUX2_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB29->PCIE_LOGIC_OUTS_B20_R_3": { + "src_wire": "PCIE_DBGVECB29", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECC0->PCIE_LOGIC_OUTS_B19_L_7": { + "src_wire": "PCIE_DBGVECC0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1CHARISK1->PCIE_LOGIC_OUTS_B16_L_4": { + "src_wire": "PCIE_PIPETX1CHARISK1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_17->PCIE_TRNTD49": { + "src_wire": "PCIE_IMUX11_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD49", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_L_13->PCIE_CFGSUBSYSVENDID14": { + "src_wire": "PCIE_IMUX14_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_8->PCIE_CFGDSN10": { + "src_wire": "PCIE_IMUX9_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_15->PCIE_TRNTDLLPDATA1": { + "src_wire": "PCIE_IMUX2_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA14->PCIE_LOGIC_OUTS_B2_R_15": { + "src_wire": "PCIE_PIPETX4DATA14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_19->PCIE_TRNTD5": { + "src_wire": "PCIE_IMUX9_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_6->PCIE_TRNTD110": { + "src_wire": "PCIE_IMUX2_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD110", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA10->PCIE_LOGIC_OUTS_B23_R_6": { + "src_wire": "PCIE_MIMTXWDATA10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_L_18->PCIE_DRPADDR5": { + "src_wire": "PCIE_IMUX14_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSCURRENTSPEED0->PCIE_LOGIC_OUTS_B19_L_16": { + "src_wire": "PCIE_CFGLINKSTATUSCURRENTSPEED0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR49->PCIE_LOGIC_OUTS_B10_L_9": { + "src_wire": "PCIE_TL2ERRHDR49", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_L_0->PCIE_CFGERRAERHEADERLOG76": { + "src_wire": "PCIE_IMUX15_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG76", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD122->PCIE_LOGIC_OUTS_B9_R_13": { + "src_wire": "PCIE_TRNRD122", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_L_10->PCIE_PIPERX1DATA0": { + "src_wire": "PCIE_IMUX37_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_R_3->PCIE_PIPERX7DATA12": { + "src_wire": "PCIE_IMUX39_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_L_18->PCIE_DRPADDR6": { + "src_wire": "PCIE_IMUX15_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRERRFWD->PCIE_LOGIC_OUTS_B5_R_10": { + "src_wire": "PCIE_TRNRERRFWD", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_R_16->PCIE_PIPERX6CHANISALIGNED": { + "src_wire": "PCIE_IMUX33_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6CHANISALIGNED", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_RECEIVEDFUNCLVLRSTN->PCIE_LOGIC_OUTS_B12_R_9": { + "src_wire": "PCIE_RECEIVEDFUNCLVLRSTN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA15->PCIE_LOGIC_OUTS_B16_R_9": { + "src_wire": "PCIE_MIMTXWDATA15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_5->PCIE_CFGERRAERHEADERLOG52": { + "src_wire": "PCIE_IMUX13_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG52", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_7->PCIE_CFGDSN5": { + "src_wire": "PCIE_IMUX8_L_7", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR12->PCIE_LOGIC_OUTS_B10_R_9": { + "src_wire": "PCIE_TL2ERRHDR12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_L_15->PCIE_PIPERX2DATA11": { + "src_wire": "PCIE_IMUX32_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_6->PCIE_MIMTXRDATA47": { + "src_wire": "PCIE_IMUX7_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA47", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_11->PCIE_CFGDSN23": { + "src_wire": "PCIE_IMUX10_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX17_R_2->PCIE_CFGERRAERHEADERLOG63": { + "src_wire": "PCIE_IMUX17_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG63", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA1->PCIE_LOGIC_OUTS_B13_L_18": { + "src_wire": "PCIE_PIPETX0DATA1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX20_R_0->PCIE_CFGVENDID15": { + "src_wire": "PCIE_IMUX20_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_5->PCIE_MIMTXRDATA21": { + "src_wire": "PCIE_IMUX1_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_L_12->PCIE_CFGSUBSYSVENDID10": { + "src_wire": "PCIE_IMUX14_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_7->PCIE_MIMTXRDATA31": { + "src_wire": "PCIE_IMUX3_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_17->PCIE_DRPADDR0": { + "src_wire": "PCIE_IMUX13_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5DATA11->PCIE_LOGIC_OUTS_B15_R_5": { + "src_wire": "PCIE_PIPETX5DATA11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_5->PCIE_CFGSUBSYSID5": { + "src_wire": "PCIE_IMUX13_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_L_16->PCIE_CFGERRTLPCPLHEADER13": { + "src_wire": "PCIE_IMUX7_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_L_19->PCIE_PIPERX0DATA10": { + "src_wire": "PCIE_IMUX33_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETXDEEMPH->PCIE_LOGIC_OUTS_B0_R_8": { + "src_wire": "PCIE_PIPETXDEEMPH", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX34_L_3->PCIE_PIPERX3DATA15": { + "src_wire": "PCIE_IMUX34_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_L_2->PCIE_CFGREVID4": { + "src_wire": "PCIE_IMUX12_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_L_6->PCIE_PIPERX3CHARISK0": { + "src_wire": "PCIE_IMUX16_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3CHARISK0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA13->PCIE_LOGIC_OUTS_B17_L_14": { + "src_wire": "PCIE_CFGMSGDATA13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA16->PCIE_LOGIC_OUTS_B1_R_4": { + "src_wire": "PCIE_MIMTXWDATA16", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1ELECIDLE->PCIE_LOGIC_OUTS_B3_L_6": { + "src_wire": "PCIE_PIPETX1ELECIDLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_R_9->PCIE_PIPERX5VALID": { + "src_wire": "PCIE_IMUX36_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5VALID", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_2->PCIE_PLTRANSMITHOTRST": { + "src_wire": "PCIE_IMUX12_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_PLTRANSMITHOTRST", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_7->PCIE_MIMTXRDATA30": { + "src_wire": "PCIE_IMUX2_R_7", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_L_19->PCIE_PIPERX0STATUS2": { + "src_wire": "PCIE_IMUX35_L_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0STATUS2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_19->PCIE_MIMRXRDATA56": { + "src_wire": "PCIE_IMUX4_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA56", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_18->PCIE_CFGDSN52": { + "src_wire": "PCIE_IMUX11_L_18", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN52", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD99->PCIE_LOGIC_OUTS_B1_R_19": { + "src_wire": "PCIE_TRNRD99", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTMSIXENABLE->PCIE_LOGIC_OUTS_B17_L_4": { + "src_wire": "PCIE_CFGINTERRUPTMSIXENABLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_16->PCIE_CFGERRCPLABORTN": { + "src_wire": "PCIE_IMUX9_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRCPLABORTN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_13->PCIE_CFGINTERRUPTASSERTN": { + "src_wire": "PCIE_IMUX16_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTASSERTN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_R_6->PCIE_CFGERRAERHEADERLOG48": { + "src_wire": "PCIE_IMUX15_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG48", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWADDR4->PCIE_LOGIC_OUTS_B10_R_4": { + "src_wire": "PCIE_MIMTXWADDR4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX6DATA12->PCIE_LOGIC_OUTS_B0_R_11": { + "src_wire": "PCIE_PIPETX6DATA12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA8->PCIE_LOGIC_OUTS_B9_L_5": { + "src_wire": "PCIE_PIPETX1DATA8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_R_6->PCIE_CFGMGMTDI16": { + "src_wire": "PCIE_IMUX10_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA2->PCIE_LOGIC_OUTS_B11_L_14": { + "src_wire": "PCIE_PIPETX2DATA2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_10->PCIE_CFGERRAERHEADERLOG116": { + "src_wire": "PCIE_IMUX6_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG116", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_R_2->PCIE_MIMTXRDATA55": { + "src_wire": "PCIE_IMUX5_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA55", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_5->PCIE_CFGERRAERHEADERLOG50": { + "src_wire": "PCIE_IMUX11_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG50", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA4->PCIE_LOGIC_OUTS_B5_R_5": { + "src_wire": "PCIE_MIMTXWDATA4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA6->PCIE_LOGIC_OUTS_B13_L_13": { + "src_wire": "PCIE_TRNRDLLPDATA6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_11->PCIE_TRNTREM0": { + "src_wire": "PCIE_IMUX0_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTREM0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_R_0->PCIE_CFGERRAERHEADERLOG73": { + "src_wire": "PCIE_IMUX15_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG73", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA32->PCIE_LOGIC_OUTS_B19_R_7": { + "src_wire": "PCIE_MIMTXWDATA32", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_12->PCIE_CFGSUBSYSVENDID9": { + "src_wire": "PCIE_IMUX13_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_15->PCIE_CFGDSN39": { + "src_wire": "PCIE_IMUX10_L_15", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN39", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_R_2->PCIE_MIMTXRDATA8": { + "src_wire": "PCIE_IMUX0_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRCOR->PCIE_LOGIC_OUTS_B14_L_15": { + "src_wire": "PCIE_CFGMSGRECEIVEDERRCOR", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA35->PCIE_LOGIC_OUTS_B11_R_15": { + "src_wire": "PCIE_DBGVECA35", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PLLTSSMSTATE1->PCIE_LOGIC_OUTS_B8_L_0": { + "src_wire": "PCIE_PLLTSSMSTATE1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA58->PCIE_LOGIC_OUTS_B17_R_0": { + "src_wire": "PCIE_MIMTXWDATA58", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD39->PCIE_LOGIC_OUTS_B1_L_15": { + "src_wire": "PCIE_TRNRD39", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX10_L_16->PCIE_CFGDSN43": { + "src_wire": "PCIE_IMUX10_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN43", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX15_L_14->PCIE_CFGAERINTERRUPTMSGNUM3": { + "src_wire": "PCIE_IMUX15_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_13->PCIE_TRNTSTR": { + "src_wire": "PCIE_IMUX0_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTSTR", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO14->PCIE_LOGIC_OUTS_B16_R_14": { + "src_wire": "PCIE_CFGMGMTDO14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_L_17->PCIE_PIPERX2CHARISK0": { + "src_wire": "PCIE_IMUX16_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2CHARISK0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX8_L_10->PCIE_CFGDSN17": { + "src_wire": "PCIE_IMUX8_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX32_R_19->PCIE_PIPERX4DATA11": { + "src_wire": "PCIE_IMUX32_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA44->PCIE_LOGIC_OUTS_B20_R_13": { + "src_wire": "PCIE_DBGVECA44", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5CHARISK0->PCIE_LOGIC_OUTS_B16_R_6": { + "src_wire": "PCIE_PIPETX5CHARISK0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB59->PCIE_LOGIC_OUTS_B18_L_6": { + "src_wire": "PCIE_DBGVECB59", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX12_R_5->PCIE_CFGERRAERHEADERLOG51": { + "src_wire": "PCIE_IMUX12_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG51", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX36_L_10->PCIE_PIPERX1DATA1": { + "src_wire": "PCIE_IMUX36_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX2CHARISK1->PCIE_LOGIC_OUTS_B16_L_11": { + "src_wire": "PCIE_PIPETX2CHARISK1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_11->PCIE_TRNTEOF": { + "src_wire": "PCIE_IMUX3_L_11", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTEOF", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_13->PCIE_TRNRDSTRDY": { + "src_wire": "PCIE_IMUX2_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNRDSTRDY", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_L_14->PCIE_PIPERX2DATA14": { + "src_wire": "PCIE_IMUX35_L_14", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB50->PCIE_LOGIC_OUTS_B21_L_3": { + "src_wire": "PCIE_DBGVECB50", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_R_2->PCIE_CFGERRAERHEADERLOG62": { + "src_wire": "PCIE_IMUX16_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG62", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB53->PCIE_LOGIC_OUTS_B20_L_4": { + "src_wire": "PCIE_DBGVECB53", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD22->PCIE_LOGIC_OUTS_B3_L_10": { + "src_wire": "PCIE_TRNRD22", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_15->PCIE_MIMRXRDATA3": { + "src_wire": "PCIE_IMUX3_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_R_12->PCIE_CFGERRAERHEADERLOG22": { + "src_wire": "PCIE_IMUX9_R_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_0->PCIE_MIMTXRDATA64": { + "src_wire": "PCIE_IMUX6_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA64", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_R_17->PCIE_PIPERX6DATA0": { + "src_wire": "PCIE_IMUX37_R_17", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX4DATA3->PCIE_LOGIC_OUTS_B15_R_18": { + "src_wire": "PCIE_PIPETX4DATA3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA23->PCIE_LOGIC_OUTS_B22_R_19": { + "src_wire": "PCIE_DBGVECA23", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX33_R_10->PCIE_PIPERX5DATA2": { + "src_wire": "PCIE_IMUX33_R_10", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX7POWERDOWN0->PCIE_LOGIC_OUTS_B1_R_2": { + "src_wire": "PCIE_PIPETX7POWERDOWN0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX14_R_9->PCIE_CFGERRAERHEADERLOG37": { + "src_wire": "PCIE_IMUX14_R_9", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG37", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA12->PCIE_LOGIC_OUTS_B10_R_6": { + "src_wire": "PCIE_MIMTXWDATA12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA18->PCIE_LOGIC_OUTS_B2_R_19": { + "src_wire": "PCIE_MIMRXWDATA18", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD30->PCIE_LOGIC_OUTS_B3_L_12": { + "src_wire": "PCIE_TRNRD30", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPERX7POLARITY->PCIE_LOGIC_OUTS_B1_R_3": { + "src_wire": "PCIE_PIPERX7POLARITY", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGDEVSTATUSFATALERRDETECTED->PCIE_LOGIC_OUTS_B16_L_10": { + "src_wire": "PCIE_CFGDEVSTATUSFATALERRDETECTED", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_19->PCIE_MIMRXRDATA59": { + "src_wire": "PCIE_IMUX7_R_19", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA59", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_17->PCIE_CFGERRTLPCPLHEADER15": { + "src_wire": "PCIE_IMUX5_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNTDLLPDSTRDY->PCIE_LOGIC_OUTS_B11_L_11": { + "src_wire": "PCIE_TRNTDLLPDSTRDY", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA60->PCIE_LOGIC_OUTS_B6_R_18": { + "src_wire": "PCIE_MIMRXWDATA60", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX9_L_3->PCIE_CFGPCIECAPINTERRUPTMSGNUM1": { + "src_wire": "PCIE_IMUX9_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO13->PCIE_LOGIC_OUTS_B14_R_14": { + "src_wire": "PCIE_CFGMGMTDO13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_5->PCIE_CFGERRAERHEADERLOG95": { + "src_wire": "PCIE_IMUX5_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG95", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD113->PCIE_LOGIC_OUTS_B5_R_15": { + "src_wire": "PCIE_TRNRD113", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX5_L_12->PCIE_CFGERRAERHEADERLOG123": { + "src_wire": "PCIE_IMUX5_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG123", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA38->PCIE_LOGIC_OUTS_B18_R_0": { + "src_wire": "PCIE_MIMTXWDATA38", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_12->PCIE_TRNTECRCGEN": { + "src_wire": "PCIE_IMUX3_L_12", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTECRCGEN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_R_18->PCIE_PIPERX4DATA12": { + "src_wire": "PCIE_IMUX39_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_6->PCIE_CFGERRAERHEADERLOG100": { + "src_wire": "PCIE_IMUX6_L_6", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG100", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR21->PCIE_LOGIC_OUTS_B12_L_1": { + "src_wire": "PCIE_TL2ERRHDR21", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_5->PCIE_MIMTXRDATA23": { + "src_wire": "PCIE_IMUX3_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_10->PCIE_CFGDSN20": { + "src_wire": "PCIE_IMUX11_L_10", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_L_0->PCIE_PLDIRECTEDLTSSMNEW2": { + "src_wire": "PCIE_IMUX11_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA30->PCIE_LOGIC_OUTS_B6_L_19": { + "src_wire": "PCIE_TRNRDLLPDATA30", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_L_16->PCIE_CFGERRTLPCPLHEADER10": { + "src_wire": "PCIE_IMUX4_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETXRESET->PCIE_LOGIC_OUTS_B9_R_11": { + "src_wire": "PCIE_PIPETXRESET", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA36->PCIE_LOGIC_OUTS_B17_R_15": { + "src_wire": "PCIE_MIMRXWDATA36", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD121->PCIE_LOGIC_OUTS_B8_R_13": { + "src_wire": "PCIE_TRNRD121", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX7_R_15->PCIE_TRNTD57": { + "src_wire": "PCIE_IMUX7_R_15", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD57", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNFCPD6->PCIE_LOGIC_OUTS_B5_R_0": { + "src_wire": "PCIE_TRNFCPD6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX11_R_0->PCIE_TRNTD90": { + "src_wire": "PCIE_IMUX11_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD90", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA63->PCIE_LOGIC_OUTS_B15_R_8": { + "src_wire": "PCIE_DBGVECA63", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_L_8->PCIE_TRNTD119": { + "src_wire": "PCIE_IMUX3_L_8", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD119", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB19->PCIE_LOGIC_OUTS_B7_R_5": { + "src_wire": "PCIE_DBGVECB19", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX39_R_5->PCIE_PIPERX7DATA4": { + "src_wire": "PCIE_IMUX39_R_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECA41->PCIE_LOGIC_OUTS_B22_R_14": { + "src_wire": "PCIE_DBGVECA41", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX0_L_16->PCIE_TRNTDLLPDATA3": { + "src_wire": "PCIE_IMUX0_L_16", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_L_17->PCIE_CFGERRTLPCPLHEADER16": { + "src_wire": "PCIE_IMUX6_L_17", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB5->PCIE_LOGIC_OUTS_B22_R_12": { + "src_wire": "PCIE_DBGVECB5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXRADDR2->PCIE_LOGIC_OUTS_B22_R_7": { + "src_wire": "PCIE_MIMTXRADDR2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX6_R_8->PCIE_CFGMGMTDI24": { + "src_wire": "PCIE_IMUX6_R_8", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_LL2REPLAYROERR->PCIE_LOGIC_OUTS_B4_R_12": { + "src_wire": "PCIE_LL2REPLAYROERR", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX35_L_5->PCIE_PIPERX3DATA6": { + "src_wire": "PCIE_IMUX35_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX1_R_1->PCIE_MIMTXRDATA5": { + "src_wire": "PCIE_IMUX1_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA25->PCIE_LOGIC_OUTS_B10_R_8": { + "src_wire": "PCIE_MIMTXWDATA25", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX38_L_4->PCIE_PIPERX3STATUS1": { + "src_wire": "PCIE_IMUX38_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3STATUS1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_R_13->PCIE_TRNTD64": { + "src_wire": "PCIE_IMUX2_R_13", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD64", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX5ELECIDLE->PCIE_LOGIC_OUTS_B3_R_6": { + "src_wire": "PCIE_PIPETX5ELECIDLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_R_18->PCIE_TRNTD43": { + "src_wire": "PCIE_IMUX13_R_18", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD43", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX37_L_5->PCIE_PIPERX3PHYSTATUS": { + "src_wire": "PCIE_IMUX37_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3PHYSTATUS", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD58->PCIE_LOGIC_OUTS_B3_L_19": { + "src_wire": "PCIE_TRNRD58", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_6->PCIE_MIMTXRDATA27": { + "src_wire": "PCIE_IMUX3_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA27", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_DBGVECB37->PCIE_LOGIC_OUTS_B21_L_0": { + "src_wire": "PCIE_DBGVECB37", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX3_R_16->PCIE_MIMRXRDATA7": { + "src_wire": "PCIE_IMUX3_R_16", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX4_R_6->PCIE_MIMTXRDATA44": { + "src_wire": "PCIE_IMUX4_R_6", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA44", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA37->PCIE_LOGIC_OUTS_B9_R_0": { + "src_wire": "PCIE_MIMTXWDATA37", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PL2RXPMSTATE1->PCIE_LOGIC_OUTS_B19_R_19": { + "src_wire": "PCIE_PL2RXPMSTATE1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX16_L_1->PCIE_PLDBGMODE1": { + "src_wire": "PCIE_IMUX16_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDBGMODE1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX13_L_13->PCIE_CFGSUBSYSVENDID13": { + "src_wire": "PCIE_IMUX13_L_13", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA56->PCIE_LOGIC_OUTS_B6_R_16": { + "src_wire": "PCIE_MIMRXWDATA56", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_IMUX2_L_5->PCIE_TRNTD106": { + "src_wire": "PCIE_IMUX2_L_5", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD106", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_TRNRD37->PCIE_LOGIC_OUTS_B4_L_14": { + "src_wire": "PCIE_TRNRD37", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA2->PCIE_LOGIC_OUTS_B11_L_7": { + "src_wire": "PCIE_PIPETX1DATA2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_7", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_PCIE_INT_INTERFACE_L.json b/kintex7/tile_type_PCIE_INT_INTERFACE_L.json new file mode 100644 index 0000000..af53025 --- /dev/null +++ b/kintex7/tile_type_PCIE_INT_INTERFACE_L.json @@ -0,0 +1,1526 @@ +{ + "tile_type": "PCIE_INT_INTERFACE_L", + "sites": [], + "wires": [ + "PCIE_INT_INTERFACE_IMUX_L_DELAY34", + "INT_INTERFACE_LH7", + "INT_INTERFACE_EE4C3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY11", + "INT_INTERFACE_LOGIC_OUTS_L11", + "INT_INTERFACE_WL1END2", + "PCIE_INT_INTERFACE_IMUX_L_DELAY33", + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "PCIE_INT_INTERFACE_IMUX_L11", + "INT_INTERFACE_BLOCK_OUTS_L_B3", + "INT_INTERFACE_EE2A2", + "PCIE_INT_INTERFACE_IMUX_L3", + "PCIE_INT_INTERFACE_IMUX_L6", + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_NW4A1", + "PCIE_INT_INTERFACE_IMUX_L_DELAY1", + "INT_INTERFACE_WW2A1", + "PCIE_INT_INTERFACE_IMUX_L_OUT34", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_LH8", + "INT_INTERFACE_LOGIC_OUTS_L3", + "PCIE_INT_INTERFACE_IMUX_L_OUT37", + "PCIE_INT_INTERFACE_IMUX_L_DELAY21", + "INT_INTERFACE_EE4A2", + "PCIE_INT_INTERFACE_IMUX_L_OUT41", + "INT_INTERFACE_SE2A2", + "PCIE_INT_INTERFACE_IMUX_L_DELAY42", + "PCIE_INT_INTERFACE_IMUX_L5", + "INT_INTERFACE_SW2A3", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_LH5", + "PCIE_INT_INTERFACE_IMUX_L0", + "PCIE_INT_INTERFACE_IMUX_L_OUT24", + "INT_INTERFACE_FAN6", + "PCIE_INT_INTERFACE_IMUX_L_OUT4", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "INT_INTERFACE_SE4BEG3", + "PCIE_INT_INTERFACE_IMUX_L29", + "PCIE_INT_INTERFACE_IMUX_L43", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END3", + "PCIE_INT_INTERFACE_IMUX_L_OUT1", + "PCIE_INT_INTERFACE_IMUX_L_OUT45", + "INT_INTERFACE_SW2A2", + "PCIE_INT_INTERFACE_IMUX_L_OUT36", + "PCIE_INT_INTERFACE_IMUX_L_OUT11", + "PCIE_INT_INTERFACE_IMUX_L_OUT39", + "INT_INTERFACE_WL1END1", + "PCIE_INT_INTERFACE_IMUX_L_OUT31", + "PCIE_INT_INTERFACE_IMUX_L_OUT14", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_LH10", + "INT_INTERFACE_LOGIC_OUTS_L4", + "PCIE_INT_INTERFACE_IMUX_L_DELAY28", + "PCIE_INT_INTERFACE_IMUX_L15", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_CTRL1", + "PCIE_INT_INTERFACE_IMUX_L25", + "PCIE_INT_INTERFACE_IMUX_L_DELAY31", + "PCIE_INT_INTERFACE_IMUX_L10", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "PCIE_INT_INTERFACE_IMUX_L13", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_EE4A3", + "PCIE_INT_INTERFACE_IMUX_L38", + "PCIE_INT_INTERFACE_IMUX_L19", + "PCIE_INT_INTERFACE_IMUX_L7", + "INT_INTERFACE_LH9", + "PCIE_INT_INTERFACE_IMUX_L_OUT35", + "PCIE_INT_INTERFACE_IMUX_L24", + "INT_INTERFACE_NE4C1", + "PCIE_INT_INTERFACE_IMUX_L_OUT29", + "INT_INTERFACE_BYP3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY41", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_BLOCK_OUTS_L_B1", + "INT_INTERFACE_WL1END0", + "PCIE_INT_INTERFACE_IMUX_L_OUT20", + "INT_INTERFACE_LH3", + "PCIE_INT_INTERFACE_IMUX_L_OUT47", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "PCIE_INT_INTERFACE_IMUX_L9", + "INT_INTERFACE_LOGIC_OUTS_L2", + "PCIE_INT_INTERFACE_IMUX_L_OUT7", + "PCIE_INT_INTERFACE_IMUX_L_DELAY18", + "PCIE_INT_INTERFACE_IMUX_L45", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "INT_INTERFACE_LOGIC_OUTS_L21", + "INT_INTERFACE_SE4C1", + "PCIE_INT_INTERFACE_IMUX_L35", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_LOGIC_OUTS_L14", + "PCIE_INT_INTERFACE_IMUX_L8", + "PCIE_INT_INTERFACE_IMUX_L_OUT6", + "INT_INTERFACE_NE4BEG0", + "PCIE_INT_INTERFACE_IMUX_L42", + "PCIE_INT_INTERFACE_IMUX_L_DELAY43", + "INT_INTERFACE_SW2A1", + "PCIE_INT_INTERFACE_IMUX_L_OUT3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY16", + "PCIE_INT_INTERFACE_IMUX_L_DELAY23", + "PCIE_INT_INTERFACE_IMUX_L_DELAY7", + "PCIE_INT_INTERFACE_IMUX_L44", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_WW2END3", + "PCIE_INT_INTERFACE_IMUX_L_OUT30", + "INT_INTERFACE_EE2BEG3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY38", + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_EE4BEG0", + "PCIE_INT_INTERFACE_IMUX_L_OUT18", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_LH6", + "PCIE_INT_INTERFACE_IMUX_L_DELAY46", + "PCIE_INT_INTERFACE_IMUX_L37", + "PCIE_INT_INTERFACE_IMUX_L_OUT16", + "INT_INTERFACE_LOGIC_OUTS_L20", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_WR1END0", + "PCIE_INT_INTERFACE_IMUX_L_DELAY40", + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "PCIE_INT_INTERFACE_IMUX_L_DELAY32", + "PCIE_INT_INTERFACE_IMUX_L_DELAY15", + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "PCIE_INT_INTERFACE_IMUX_L20", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_WW4END0", + "PCIE_INT_INTERFACE_IMUX_L_OUT10", + "PCIE_INT_INTERFACE_IMUX_L_OUT0", + "PCIE_INT_INTERFACE_IMUX_L14", + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_EE2A3", + "PCIE_INT_INTERFACE_IMUX_L26", + "INT_INTERFACE_LOGIC_OUTS_L5", + "PCIE_INT_INTERFACE_IMUX_L39", + "PCIE_INT_INTERFACE_IMUX_L_DELAY19", + "INT_INTERFACE_LOGIC_OUTS_L9", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "PCIE_INT_INTERFACE_IMUX_L_OUT26", + "INT_INTERFACE_LOGIC_OUTS_L0", + "INT_INTERFACE_LOGIC_OUTS_L15", + "INT_INTERFACE_EE4C1", + "PCIE_INT_INTERFACE_IMUX_L_OUT22", + "PCIE_INT_INTERFACE_IMUX_L_OUT13", + "PCIE_INT_INTERFACE_IMUX_L_OUT38", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_WW4C2", + "PCIE_INT_INTERFACE_IMUX_L1", + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "PCIE_INT_INTERFACE_IMUX_L_OUT8", + "PCIE_INT_INTERFACE_IMUX_L_DELAY9", + "PCIE_INT_INTERFACE_IMUX_L_DELAY5", + "INT_INTERFACE_BYP2", + "PCIE_INT_INTERFACE_IMUX_L2", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_NW4A0", + "PCIE_INT_INTERFACE_IMUX_L_OUT28", + "PCIE_INT_INTERFACE_IMUX_L_OUT23", + "INT_INTERFACE_LOGIC_OUTS_L23", + "PCIE_INT_INTERFACE_IMUX_L_DELAY44", + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "INT_INTERFACE_LOGIC_OUTS_L7", + "INT_INTERFACE_LH11", + "PCIE_INT_INTERFACE_IMUX_L_OUT15", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_NW4A3", + "PCIE_INT_INTERFACE_IMUX_L12", + "PCIE_INT_INTERFACE_IMUX_L_DELAY6", + "PCIE_INT_INTERFACE_IMUX_L_DELAY2", + "INT_INTERFACE_WW4C1", + "PCIE_INT_INTERFACE_IMUX_L_DELAY12", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_EL1BEG3", + "PCIE_INT_INTERFACE_IMUX_L4", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "PCIE_INT_INTERFACE_IMUX_L_OUT33", + "INT_INTERFACE_LOGIC_OUTS_L13", + "INT_INTERFACE_NE2A2", + "PCIE_INT_INTERFACE_IMUX_L21", + "INT_INTERFACE_BYP6", + "PCIE_INT_INTERFACE_IMUX_L_OUT42", + "PCIE_INT_INTERFACE_IMUX_L28", + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "PCIE_INT_INTERFACE_IMUX_L_DELAY30", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_LOGIC_OUTS_L22", + "PCIE_INT_INTERFACE_IMUX_L23", + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "INT_INTERFACE_NW4END0", + "PCIE_INT_INTERFACE_IMUX_L_DELAY35", + "PCIE_INT_INTERFACE_IMUX_L_DELAY26", + "INT_INTERFACE_NE4C3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY39", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_LH2", + "INT_INTERFACE_BLOCK_OUTS_L_B0", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_LH1", + "INT_INTERFACE_LOGIC_OUTS_L6", + "INT_INTERFACE_WW4A3", + "PCIE_INT_INTERFACE_IMUX_L31", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_LH4", + "INT_INTERFACE_LOGIC_OUTS_L19", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_LOGIC_OUTS_L12", + "PCIE_INT_INTERFACE_IMUX_L_DELAY25", + "PCIE_INT_INTERFACE_IMUX_L_DELAY20", + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "INT_INTERFACE_SW4END2", + "PCIE_INT_INTERFACE_IMUX_L_OUT2", + "INT_INTERFACE_LOGIC_OUTS_L18", + "PCIE_INT_INTERFACE_IMUX_L_DELAY27", + "PCIE_INT_INTERFACE_IMUX_L36", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_EE4B2", + "PCIE_INT_INTERFACE_IMUX_L_DELAY24", + "PCIE_INT_INTERFACE_IMUX_L18", + "PCIE_INT_INTERFACE_IMUX_L_OUT9", + "INT_INTERFACE_LOGIC_OUTS_L1", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_WW4B2", + "PCIE_INT_INTERFACE_IMUX_L_DELAY8", + "PCIE_INT_INTERFACE_IMUX_L_OUT5", + "PCIE_INT_INTERFACE_IMUX_L_OUT32", + "PCIE_INT_INTERFACE_IMUX_L_OUT43", + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "INT_INTERFACE_WW4A0", + "PCIE_INT_INTERFACE_IMUX_L33", + "PCIE_INT_INTERFACE_IMUX_L_OUT19", + "INT_INTERFACE_FAN5", + "INT_INTERFACE_LOGIC_OUTS_L8", + "PCIE_INT_INTERFACE_IMUX_L_DELAY4", + "PCIE_INT_INTERFACE_IMUX_L30", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_BYP5", + "INT_INTERFACE_EE4BEG2", + "PCIE_INT_INTERFACE_IMUX_L_DELAY29", + "PCIE_INT_INTERFACE_IMUX_L16", + "INT_INTERFACE_LOGIC_OUTS_L10", + "PCIE_INT_INTERFACE_IMUX_L17", + "PCIE_INT_INTERFACE_IMUX_L40", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_ER1BEG3", + "PCIE_INT_INTERFACE_IMUX_L_OUT40", + "PCIE_INT_INTERFACE_IMUX_L_DELAY13", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "INT_INTERFACE_WW4B1", + "PCIE_INT_INTERFACE_IMUX_L_DELAY47", + "PCIE_INT_INTERFACE_IMUX_L_DELAY3", + "PCIE_INT_INTERFACE_IMUX_L_OUT25", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_WW4A1", + "PCIE_INT_INTERFACE_IMUX_L27", + "INT_INTERFACE_LOGIC_OUTS_L16", + "PCIE_INT_INTERFACE_IMUX_L_DELAY10", + "PCIE_INT_INTERFACE_IMUX_L32", + "PCIE_INT_INTERFACE_IMUX_L22", + "PCIE_INT_INTERFACE_IMUX_L_DELAY22", + "INT_INTERFACE_FAN2", + "PCIE_INT_INTERFACE_IMUX_L_OUT46", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_EL1BEG0", + "PCIE_INT_INTERFACE_IMUX_L_DELAY36", + "INT_INTERFACE_LH12", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_WR1END2", + "PCIE_INT_INTERFACE_IMUX_L46", + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "INT_INTERFACE_WR1END1", + "PCIE_INT_INTERFACE_IMUX_L_DELAY37", + "PCIE_INT_INTERFACE_IMUX_L_DELAY45", + "INT_INTERFACE_NE4BEG3", + "PCIE_INT_INTERFACE_IMUX_L_OUT44", + "INT_INTERFACE_NE4C0", + "PCIE_INT_INTERFACE_IMUX_L_OUT27", + "INT_INTERFACE_BYP1", + "PCIE_INT_INTERFACE_IMUX_L47", + "PCIE_INT_INTERFACE_IMUX_L_DELAY14", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_SE2A3", + "PCIE_INT_INTERFACE_IMUX_L_OUT12", + "PCIE_INT_INTERFACE_IMUX_L_OUT21", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_NW4END3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY17", + "PCIE_INT_INTERFACE_IMUX_L34", + "INT_INTERFACE_NE2A0", + "PCIE_INT_INTERFACE_IMUX_L41", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_BYP7", + "PCIE_INT_INTERFACE_IMUX_L_OUT17", + "INT_INTERFACE_BLOCK_OUTS_L_B2", + "INT_INTERFACE_LOGIC_OUTS_L17", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_NE4BEG2", + "PCIE_INT_INTERFACE_IMUX_L_DELAY0" + ], + "pips": { + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L21->>PCIE_INT_INTERFACE_IMUX_L_OUT21": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L21", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L36->>PCIE_INT_INTERFACE_IMUX_L_OUT36": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L36", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT36", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L2->>PCIE_INT_INTERFACE_IMUX_L_DELAY2": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L2", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L17->>PCIE_INT_INTERFACE_IMUX_L_OUT17": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L17", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L29->>PCIE_INT_INTERFACE_IMUX_L_DELAY29": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L29", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L33->>PCIE_INT_INTERFACE_IMUX_L_OUT33": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L33", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT33", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L3->>PCIE_INT_INTERFACE_IMUX_L_OUT3": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L3", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L28->>PCIE_INT_INTERFACE_IMUX_L_DELAY28": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L28", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L5->>PCIE_INT_INTERFACE_IMUX_L_DELAY5": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L5", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY3->PCIE_INT_INTERFACE_IMUX_L_OUT3": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY3", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L26->>PCIE_INT_INTERFACE_IMUX_L_OUT26": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L26", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L29->>PCIE_INT_INTERFACE_IMUX_L_OUT29": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L29", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L18->>PCIE_INT_INTERFACE_IMUX_L_OUT18": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L18", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L35->>PCIE_INT_INTERFACE_IMUX_L_OUT35": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L35", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT35", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L15->>PCIE_INT_INTERFACE_IMUX_L_DELAY15": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L15", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L38->>PCIE_INT_INTERFACE_IMUX_L_OUT38": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L38", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT38", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L47->>PCIE_INT_INTERFACE_IMUX_L_OUT47": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L47", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT47", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L28->>PCIE_INT_INTERFACE_IMUX_L_OUT28": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L28", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY20->PCIE_INT_INTERFACE_IMUX_L_OUT20": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY20", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY16->PCIE_INT_INTERFACE_IMUX_L_OUT16": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY16", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L45->>PCIE_INT_INTERFACE_IMUX_L_OUT45": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L45", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT45", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L4->>PCIE_INT_INTERFACE_IMUX_L_DELAY4": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L4", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L4->>PCIE_INT_INTERFACE_IMUX_L_OUT4": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L4", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L27->>PCIE_INT_INTERFACE_IMUX_L_OUT27": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L27", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT27", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L21->>PCIE_INT_INTERFACE_IMUX_L_DELAY21": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L21", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L8->>PCIE_INT_INTERFACE_IMUX_L_DELAY8": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L8", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY18->PCIE_INT_INTERFACE_IMUX_L_OUT18": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY18", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L16->>PCIE_INT_INTERFACE_IMUX_L_DELAY16": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L16", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L46->>PCIE_INT_INTERFACE_IMUX_L_DELAY46": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L46", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY46", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L13->>PCIE_INT_INTERFACE_IMUX_L_DELAY13": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L13", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L19->>PCIE_INT_INTERFACE_IMUX_L_DELAY19": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L19", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L6->>PCIE_INT_INTERFACE_IMUX_L_OUT6": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L6", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L31->>PCIE_INT_INTERFACE_IMUX_L_OUT31": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L31", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY6->PCIE_INT_INTERFACE_IMUX_L_OUT6": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY6", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY39->PCIE_INT_INTERFACE_IMUX_L_OUT39": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY39", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT39", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L0->>PCIE_INT_INTERFACE_IMUX_L_OUT0": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L0", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L47->>PCIE_INT_INTERFACE_IMUX_L_DELAY47": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L47", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY47", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L13->>PCIE_INT_INTERFACE_IMUX_L_OUT13": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L13", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY8->PCIE_INT_INTERFACE_IMUX_L_OUT8": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY8", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L12->>PCIE_INT_INTERFACE_IMUX_L_DELAY12": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L12", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L34->>PCIE_INT_INTERFACE_IMUX_L_OUT34": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L34", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT34", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L5->>PCIE_INT_INTERFACE_IMUX_L_OUT5": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L5", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY43->PCIE_INT_INTERFACE_IMUX_L_OUT43": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY43", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT43", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY38->PCIE_INT_INTERFACE_IMUX_L_OUT38": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY38", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT38", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L16->>PCIE_INT_INTERFACE_IMUX_L_OUT16": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L16", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L24->>PCIE_INT_INTERFACE_IMUX_L_OUT24": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L24", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY2->PCIE_INT_INTERFACE_IMUX_L_OUT2": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY2", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY13->PCIE_INT_INTERFACE_IMUX_L_OUT13": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY13", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L42->>PCIE_INT_INTERFACE_IMUX_L_OUT42": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L42", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT42", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L20->>PCIE_INT_INTERFACE_IMUX_L_OUT20": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L20", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L14->>PCIE_INT_INTERFACE_IMUX_L_OUT14": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L14", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L37->>PCIE_INT_INTERFACE_IMUX_L_DELAY37": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L37", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY37", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L9->>PCIE_INT_INTERFACE_IMUX_L_OUT9": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L9", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L35->>PCIE_INT_INTERFACE_IMUX_L_DELAY35": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L35", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY35", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L10->>PCIE_INT_INTERFACE_IMUX_L_OUT10": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L10", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L11->>PCIE_INT_INTERFACE_IMUX_L_DELAY11": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L11", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L8->>PCIE_INT_INTERFACE_IMUX_L_OUT8": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L8", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L45->>PCIE_INT_INTERFACE_IMUX_L_DELAY45": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L45", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY45", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY31->PCIE_INT_INTERFACE_IMUX_L_OUT31": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY31", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L25->>PCIE_INT_INTERFACE_IMUX_L_DELAY25": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L25", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L2->>PCIE_INT_INTERFACE_IMUX_L_OUT2": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L2", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY41->PCIE_INT_INTERFACE_IMUX_L_OUT41": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY41", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT41", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L32->>PCIE_INT_INTERFACE_IMUX_L_DELAY32": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L32", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY32", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L31->>PCIE_INT_INTERFACE_IMUX_L_DELAY31": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L31", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L19->>PCIE_INT_INTERFACE_IMUX_L_OUT19": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L19", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY22->PCIE_INT_INTERFACE_IMUX_L_OUT22": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY22", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L41->>PCIE_INT_INTERFACE_IMUX_L_OUT41": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L41", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT41", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY12->PCIE_INT_INTERFACE_IMUX_L_OUT12": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY12", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L44->>PCIE_INT_INTERFACE_IMUX_L_OUT44": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L44", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT44", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L15->>PCIE_INT_INTERFACE_IMUX_L_OUT15": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L15", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY46->PCIE_INT_INTERFACE_IMUX_L_OUT46": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY46", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT46", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY15->PCIE_INT_INTERFACE_IMUX_L_OUT15": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY15", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L12->>PCIE_INT_INTERFACE_IMUX_L_OUT12": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L12", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY19->PCIE_INT_INTERFACE_IMUX_L_OUT19": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY19", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L32->>PCIE_INT_INTERFACE_IMUX_L_OUT32": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L32", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT32", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY33->PCIE_INT_INTERFACE_IMUX_L_OUT33": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY33", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT33", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY30->PCIE_INT_INTERFACE_IMUX_L_OUT30": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY30", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY26->PCIE_INT_INTERFACE_IMUX_L_OUT26": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY26", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L1->>PCIE_INT_INTERFACE_IMUX_L_DELAY1": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L38->>PCIE_INT_INTERFACE_IMUX_L_DELAY38": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L38", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY38", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY36->PCIE_INT_INTERFACE_IMUX_L_OUT36": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY36", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT36", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY29->PCIE_INT_INTERFACE_IMUX_L_OUT29": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY29", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L26->>PCIE_INT_INTERFACE_IMUX_L_DELAY26": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L26", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L39->>PCIE_INT_INTERFACE_IMUX_L_DELAY39": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L39", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY39", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L30->>PCIE_INT_INTERFACE_IMUX_L_OUT30": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L30", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L30->>PCIE_INT_INTERFACE_IMUX_L_DELAY30": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L30", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L22->>PCIE_INT_INTERFACE_IMUX_L_DELAY22": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L22", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY37->PCIE_INT_INTERFACE_IMUX_L_OUT37": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY37", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT37", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L25->>PCIE_INT_INTERFACE_IMUX_L_OUT25": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L25", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L23->>PCIE_INT_INTERFACE_IMUX_L_OUT23": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L23", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY42->PCIE_INT_INTERFACE_IMUX_L_OUT42": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY42", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT42", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L0->>PCIE_INT_INTERFACE_IMUX_L_DELAY0": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L0", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY40->PCIE_INT_INTERFACE_IMUX_L_OUT40": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY40", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT40", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L40->>PCIE_INT_INTERFACE_IMUX_L_DELAY40": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L40", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY40", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY11->PCIE_INT_INTERFACE_IMUX_L_OUT11": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY11", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY0->PCIE_INT_INTERFACE_IMUX_L_OUT0": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY0", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY14->PCIE_INT_INTERFACE_IMUX_L_OUT14": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY14", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L43->>PCIE_INT_INTERFACE_IMUX_L_DELAY43": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L43", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY43", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L23->>PCIE_INT_INTERFACE_IMUX_L_DELAY23": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L23", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY34->PCIE_INT_INTERFACE_IMUX_L_OUT34": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY34", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT34", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L24->>PCIE_INT_INTERFACE_IMUX_L_DELAY24": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L24", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L44->>PCIE_INT_INTERFACE_IMUX_L_DELAY44": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L44", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY44", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY45->PCIE_INT_INTERFACE_IMUX_L_OUT45": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY45", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT45", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY27->PCIE_INT_INTERFACE_IMUX_L_OUT27": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY27", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT27", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L9->>PCIE_INT_INTERFACE_IMUX_L_DELAY9": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L9", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L10->>PCIE_INT_INTERFACE_IMUX_L_DELAY10": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L10", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L20->>PCIE_INT_INTERFACE_IMUX_L_DELAY20": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L20", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L18->>PCIE_INT_INTERFACE_IMUX_L_DELAY18": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L18", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY9->PCIE_INT_INTERFACE_IMUX_L_OUT9": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY9", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L27->>PCIE_INT_INTERFACE_IMUX_L_DELAY27": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L27", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY27", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L43->>PCIE_INT_INTERFACE_IMUX_L_OUT43": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L43", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT43", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY17->PCIE_INT_INTERFACE_IMUX_L_OUT17": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY17", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L37->>PCIE_INT_INTERFACE_IMUX_L_OUT37": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L37", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT37", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY47->PCIE_INT_INTERFACE_IMUX_L_OUT47": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY47", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT47", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L41->>PCIE_INT_INTERFACE_IMUX_L_DELAY41": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L41", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY41", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY35->PCIE_INT_INTERFACE_IMUX_L_OUT35": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY35", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT35", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY7->PCIE_INT_INTERFACE_IMUX_L_OUT7": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY7", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L34->>PCIE_INT_INTERFACE_IMUX_L_DELAY34": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L34", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY34", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L14->>PCIE_INT_INTERFACE_IMUX_L_DELAY14": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L14", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L42->>PCIE_INT_INTERFACE_IMUX_L_DELAY42": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L42", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY42", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L36->>PCIE_INT_INTERFACE_IMUX_L_DELAY36": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L36", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY36", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L46->>PCIE_INT_INTERFACE_IMUX_L_OUT46": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L46", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT46", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY25->PCIE_INT_INTERFACE_IMUX_L_OUT25": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY25", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L1->>PCIE_INT_INTERFACE_IMUX_L_OUT1": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY44->PCIE_INT_INTERFACE_IMUX_L_OUT44": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY44", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT44", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY4->PCIE_INT_INTERFACE_IMUX_L_OUT4": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY4", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY24->PCIE_INT_INTERFACE_IMUX_L_OUT24": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY24", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY28->PCIE_INT_INTERFACE_IMUX_L_OUT28": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY28", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L7->>PCIE_INT_INTERFACE_IMUX_L_DELAY7": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L7", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY32->PCIE_INT_INTERFACE_IMUX_L_OUT32": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY32", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT32", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L33->>PCIE_INT_INTERFACE_IMUX_L_DELAY33": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L33", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY33", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY10->PCIE_INT_INTERFACE_IMUX_L_OUT10": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY10", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY5->PCIE_INT_INTERFACE_IMUX_L_OUT5": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY5", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L40->>PCIE_INT_INTERFACE_IMUX_L_OUT40": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L40", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT40", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L3->>PCIE_INT_INTERFACE_IMUX_L_DELAY3": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L3", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY21->PCIE_INT_INTERFACE_IMUX_L_OUT21": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY21", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L22->>PCIE_INT_INTERFACE_IMUX_L_OUT22": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L22", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L39->>PCIE_INT_INTERFACE_IMUX_L_OUT39": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L39", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT39", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L6->>PCIE_INT_INTERFACE_IMUX_L_DELAY6": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L6", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY1->PCIE_INT_INTERFACE_IMUX_L_OUT1": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L11->>PCIE_INT_INTERFACE_IMUX_L_OUT11": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L11", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY23->PCIE_INT_INTERFACE_IMUX_L_OUT23": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY23", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L7->>PCIE_INT_INTERFACE_IMUX_L_OUT7": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L7", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L17->>PCIE_INT_INTERFACE_IMUX_L_DELAY17": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_L17", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY17", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_PCIE_INT_INTERFACE_R.json b/kintex7/tile_type_PCIE_INT_INTERFACE_R.json new file mode 100644 index 0000000..f42870f --- /dev/null +++ b/kintex7/tile_type_PCIE_INT_INTERFACE_R.json @@ -0,0 +1,1526 @@ +{ + "tile_type": "PCIE_INT_INTERFACE_R", + "sites": [], + "wires": [ + "PCIE_INT_INTERFACE_IMUX24", + "PCIE_INT_INTERFACE_IMUX_OUT28", + "PCIE_INT_INTERFACE_IMUX29", + "PCIE_INT_INTERFACE_IMUX_OUT36", + "PCIE_INT_INTERFACE_IMUX6", + "PCIE_INT_INTERFACE_IMUX1", + "INT_INTERFACE_LH7", + "PCIE_INT_INTERFACE_IMUX_DELAY8", + "INT_INTERFACE_EE4C3", + "PCIE_INT_INTERFACE_IMUX_DELAY30", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_LOGIC_OUTS_B22", + "PCIE_INT_INTERFACE_IMUX_DELAY17", + "PCIE_INT_INTERFACE_IMUX_DELAY35", + "INT_INTERFACE_EE2A2", + "PCIE_INT_INTERFACE_IMUX_OUT41", + "INT_INTERFACE_LOGIC_OUTS3", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_NW4A1", + "PCIE_INT_INTERFACE_IMUX_OUT46", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_LH8", + "INT_INTERFACE_WW2A3", + "PCIE_INT_INTERFACE_IMUX_DELAY10", + "INT_INTERFACE_LOGIC_OUTS1", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_LOGIC_OUTS0", + "INT_INTERFACE_BLOCK_OUTS_B0", + "INT_INTERFACE_SE2A2", + "PCIE_INT_INTERFACE_IMUX_OUT23", + "PCIE_INT_INTERFACE_IMUX_DELAY23", + "PCIE_INT_INTERFACE_IMUX_DELAY18", + "INT_INTERFACE_SW2A3", + "PCIE_INT_INTERFACE_IMUX42", + "INT_INTERFACE_SE4BEG2", + "PCIE_INT_INTERFACE_IMUX_OUT17", + "INT_INTERFACE_LH5", + "INT_INTERFACE_BLOCK_OUTS_B3", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_WW4B3", + "PCIE_INT_INTERFACE_IMUX_DELAY16", + "INT_INTERFACE_SW4END1", + "PCIE_INT_INTERFACE_IMUX_DELAY12", + "INT_INTERFACE_SE4BEG3", + "PCIE_INT_INTERFACE_IMUX_DELAY3", + "PCIE_INT_INTERFACE_IMUX_DELAY20", + "PCIE_INT_INTERFACE_IMUX_OUT30", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END3", + "PCIE_INT_INTERFACE_IMUX43", + "PCIE_INT_INTERFACE_IMUX_DELAY21", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_WL1END1", + "PCIE_INT_INTERFACE_IMUX_DELAY9", + "PCIE_INT_INTERFACE_IMUX34", + "PCIE_INT_INTERFACE_IMUX_DELAY40", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_LH10", + "PCIE_INT_INTERFACE_IMUX_DELAY13", + "PCIE_INT_INTERFACE_IMUX_OUT4", + "INT_INTERFACE_EE4C2", + "PCIE_INT_INTERFACE_IMUX_DELAY42", + "INT_INTERFACE_LOGIC_OUTS18", + "PCIE_INT_INTERFACE_IMUX_OUT29", + "INT_INTERFACE_EL1BEG1", + "PCIE_INT_INTERFACE_IMUX_OUT47", + "PCIE_INT_INTERFACE_IMUX_OUT38", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_CTRL1", + "PCIE_INT_INTERFACE_IMUX26", + "PCIE_INT_INTERFACE_IMUX31", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_LOGIC_OUTS23", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_EE4A3", + "PCIE_INT_INTERFACE_IMUX_DELAY4", + "PCIE_INT_INTERFACE_IMUX_DELAY47", + "PCIE_INT_INTERFACE_IMUX_DELAY6", + "PCIE_INT_INTERFACE_IMUX_DELAY11", + "PCIE_INT_INTERFACE_IMUX_DELAY14", + "PCIE_INT_INTERFACE_IMUX_OUT2", + "PCIE_INT_INTERFACE_IMUX_OUT0", + "INT_INTERFACE_LH9", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_ER1BEG1", + "PCIE_INT_INTERFACE_IMUX_OUT7", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_LOGIC_OUTS11", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_LH3", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_BYP4", + "PCIE_INT_INTERFACE_IMUX_OUT34", + "INT_INTERFACE_SW4A1", + "PCIE_INT_INTERFACE_IMUX40", + "INT_INTERFACE_LOGIC_OUTS8", + "PCIE_INT_INTERFACE_IMUX30", + "PCIE_INT_INTERFACE_IMUX_DELAY15", + "INT_INTERFACE_LOGIC_OUTS4", + "PCIE_INT_INTERFACE_IMUX_OUT3", + "PCIE_INT_INTERFACE_IMUX_DELAY43", + "INT_INTERFACE_LOGIC_OUTS_B3", + "INT_INTERFACE_LOGIC_OUTS21", + "PCIE_INT_INTERFACE_IMUX_DELAY1", + "PCIE_INT_INTERFACE_IMUX36", + "INT_INTERFACE_CLK1", + "PCIE_INT_INTERFACE_IMUX0", + "PCIE_INT_INTERFACE_IMUX32", + "INT_INTERFACE_SE4C1", + "PCIE_INT_INTERFACE_IMUX_OUT43", + "PCIE_INT_INTERFACE_IMUX44", + "PCIE_INT_INTERFACE_IMUX21", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_SE4BEG1", + "PCIE_INT_INTERFACE_IMUX_OUT42", + "PCIE_INT_INTERFACE_IMUX18", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_WW2END3", + "PCIE_INT_INTERFACE_IMUX_DELAY44", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_LOGIC_OUTS_B21", + "INT_INTERFACE_BYP0", + "PCIE_INT_INTERFACE_IMUX_OUT6", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_LH6", + "PCIE_INT_INTERFACE_IMUX_OUT12", + "PCIE_INT_INTERFACE_IMUX_OUT15", + "PCIE_INT_INTERFACE_IMUX_DELAY22", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_WR1END0", + "PCIE_INT_INTERFACE_IMUX_DELAY5", + "INT_INTERFACE_LOGIC_OUTS10", + "PCIE_INT_INTERFACE_IMUX_DELAY32", + "INT_INTERFACE_LOGIC_OUTS_B11", + "PCIE_INT_INTERFACE_IMUX_DELAY31", + "PCIE_INT_INTERFACE_IMUX_OUT44", + "INT_INTERFACE_LOGIC_OUTS_B10", + "INT_INTERFACE_SE4C2", + "PCIE_INT_INTERFACE_IMUX_DELAY41", + "INT_INTERFACE_WW4END0", + "PCIE_INT_INTERFACE_IMUX_OUT20", + "INT_INTERFACE_LOGIC_OUTS17", + "INT_INTERFACE_LOGIC_OUTS_B13", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_EE2A3", + "PCIE_INT_INTERFACE_IMUX2", + "PCIE_INT_INTERFACE_IMUX9", + "PCIE_INT_INTERFACE_IMUX_OUT9", + "INT_INTERFACE_LOGIC_OUTS2", + "PCIE_INT_INTERFACE_IMUX17", + "PCIE_INT_INTERFACE_IMUX_OUT13", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_LOGIC_OUTS_B12", + "PCIE_INT_INTERFACE_IMUX46", + "PCIE_INT_INTERFACE_IMUX33", + "INT_INTERFACE_EE4C1", + "PCIE_INT_INTERFACE_IMUX14", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_EE4B1", + "PCIE_INT_INTERFACE_IMUX_DELAY38", + "INT_INTERFACE_WW4C2", + "PCIE_INT_INTERFACE_IMUX_OUT21", + "PCIE_INT_INTERFACE_IMUX23", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_LOGIC_OUTS16", + "INT_INTERFACE_NW2A1", + "PCIE_INT_INTERFACE_IMUX_OUT16", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_LOGIC_OUTS20", + "INT_INTERFACE_LOGIC_OUTS22", + "PCIE_INT_INTERFACE_IMUX_OUT37", + "PCIE_INT_INTERFACE_IMUX39", + "PCIE_INT_INTERFACE_IMUX3", + "INT_INTERFACE_LH11", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_WW4C1", + "PCIE_INT_INTERFACE_IMUX5", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_EL1BEG3", + "PCIE_INT_INTERFACE_IMUX28", + "PCIE_INT_INTERFACE_IMUX_DELAY37", + "INT_INTERFACE_EE4A1", + "PCIE_INT_INTERFACE_IMUX15", + "INT_INTERFACE_LOGIC_OUTS_B2", + "INT_INTERFACE_LOGIC_OUTS_B20", + "PCIE_INT_INTERFACE_IMUX_OUT39", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_LOGIC_OUTS_B23", + "INT_INTERFACE_NW4END1", + "PCIE_INT_INTERFACE_IMUX19", + "INT_INTERFACE_NW4END0", + "PCIE_INT_INTERFACE_IMUX8", + "INT_INTERFACE_LOGIC_OUTS_B6", + "INT_INTERFACE_NE4C3", + "PCIE_INT_INTERFACE_IMUX37", + "PCIE_INT_INTERFACE_IMUX_OUT5", + "PCIE_INT_INTERFACE_IMUX_OUT26", + "INT_INTERFACE_LOGIC_OUTS_B16", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_LH2", + "PCIE_INT_INTERFACE_IMUX27", + "INT_INTERFACE_LOGIC_OUTS_B14", + "PCIE_INT_INTERFACE_IMUX_DELAY39", + "PCIE_INT_INTERFACE_IMUX_DELAY2", + "INT_INTERFACE_SW4A2", + "PCIE_INT_INTERFACE_IMUX_DELAY33", + "INT_INTERFACE_LH1", + "PCIE_INT_INTERFACE_IMUX22", + "PCIE_INT_INTERFACE_IMUX_DELAY24", + "INT_INTERFACE_LOGIC_OUTS5", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_ER1BEG0", + "PCIE_INT_INTERFACE_IMUX7", + "PCIE_INT_INTERFACE_IMUX_DELAY28", + "INT_INTERFACE_NW4END2", + "PCIE_INT_INTERFACE_IMUX_OUT45", + "PCIE_INT_INTERFACE_IMUX_DELAY45", + "INT_INTERFACE_LH4", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_NE4BEG1", + "PCIE_INT_INTERFACE_IMUX11", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_WR1END3", + "PCIE_INT_INTERFACE_IMUX_OUT19", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_LOGIC_OUTS15", + "INT_INTERFACE_LOGIC_OUTS_B19", + "PCIE_INT_INTERFACE_IMUX_OUT27", + "PCIE_INT_INTERFACE_IMUX_OUT31", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LOGIC_OUTS_B17", + "PCIE_INT_INTERFACE_IMUX_DELAY36", + "INT_INTERFACE_LOGIC_OUTS_B15", + "PCIE_INT_INTERFACE_IMUX_OUT22", + "PCIE_INT_INTERFACE_IMUX_OUT35", + "PCIE_INT_INTERFACE_IMUX_DELAY46", + "INT_INTERFACE_LOGIC_OUTS_B9", + "INT_INTERFACE_LOGIC_OUTS_B0", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_BLOCK_OUTS_B1", + "INT_INTERFACE_LOGIC_OUTS_B7", + "INT_INTERFACE_LOGIC_OUTS_B8", + "INT_INTERFACE_LOGIC_OUTS14", + "INT_INTERFACE_CTRL0", + "PCIE_INT_INTERFACE_IMUX41", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_LOGIC_OUTS12", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_SW2A0", + "PCIE_INT_INTERFACE_IMUX_OUT1", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_FAN5", + "PCIE_INT_INTERFACE_IMUX4", + "INT_INTERFACE_LOGIC_OUTS7", + "INT_INTERFACE_SE4C3", + "PCIE_INT_INTERFACE_IMUX45", + "INT_INTERFACE_LOGIC_OUTS_B18", + "PCIE_INT_INTERFACE_IMUX_OUT14", + "INT_INTERFACE_BYP5", + "PCIE_INT_INTERFACE_IMUX_DELAY19", + "INT_INTERFACE_EE4BEG2", + "PCIE_INT_INTERFACE_IMUX10", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_LOGIC_OUTS_B4", + "PCIE_INT_INTERFACE_IMUX_OUT40", + "PCIE_INT_INTERFACE_IMUX16", + "PCIE_INT_INTERFACE_IMUX25", + "INT_INTERFACE_WW4B1", + "PCIE_INT_INTERFACE_IMUX12", + "INT_INTERFACE_NW2A2", + "PCIE_INT_INTERFACE_IMUX38", + "INT_INTERFACE_WW4A1", + "PCIE_INT_INTERFACE_IMUX20", + "PCIE_INT_INTERFACE_IMUX_OUT32", + "INT_INTERFACE_FAN2", + "PCIE_INT_INTERFACE_IMUX_OUT8", + "PCIE_INT_INTERFACE_IMUX_DELAY29", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_LH12", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_WR1END2", + "PCIE_INT_INTERFACE_IMUX_DELAY25", + "INT_INTERFACE_WR1END1", + "PCIE_INT_INTERFACE_IMUX_OUT25", + "PCIE_INT_INTERFACE_IMUX47", + "PCIE_INT_INTERFACE_IMUX_OUT24", + "PCIE_INT_INTERFACE_IMUX_DELAY0", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_LOGIC_OUTS13", + "PCIE_INT_INTERFACE_IMUX_OUT11", + "PCIE_INT_INTERFACE_IMUX13", + "INT_INTERFACE_LOGIC_OUTS9", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_LOGIC_OUTS_B5", + "PCIE_INT_INTERFACE_IMUX_DELAY34", + "INT_INTERFACE_LOGIC_OUTS19", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_BLOCK_OUTS_B2", + "PCIE_INT_INTERFACE_IMUX_DELAY26", + "PCIE_INT_INTERFACE_IMUX_DELAY7", + "PCIE_INT_INTERFACE_IMUX_OUT10", + "PCIE_INT_INTERFACE_IMUX_DELAY27", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_NE2A0", + "PCIE_INT_INTERFACE_IMUX_OUT18", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_LOGIC_OUTS6", + "INT_INTERFACE_BYP7", + "PCIE_INT_INTERFACE_IMUX35", + "PCIE_INT_INTERFACE_IMUX_OUT33", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + "pips": { + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B19", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY17->PCIE_INT_INTERFACE_IMUX_OUT17": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY17", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX24->>PCIE_INT_INTERFACE_IMUX_DELAY24": { + "src_wire": "PCIE_INT_INTERFACE_IMUX24", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY3->PCIE_INT_INTERFACE_IMUX_OUT3": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY3", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY18->PCIE_INT_INTERFACE_IMUX_OUT18": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY18", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX8->>PCIE_INT_INTERFACE_IMUX_OUT8": { + "src_wire": "PCIE_INT_INTERFACE_IMUX8", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY36->PCIE_INT_INTERFACE_IMUX_OUT36": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY36", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT36", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B15", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX18->>PCIE_INT_INTERFACE_IMUX_DELAY18": { + "src_wire": "PCIE_INT_INTERFACE_IMUX18", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY4->PCIE_INT_INTERFACE_IMUX_OUT4": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY4", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX20->>PCIE_INT_INTERFACE_IMUX_DELAY20": { + "src_wire": "PCIE_INT_INTERFACE_IMUX20", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX40->>PCIE_INT_INTERFACE_IMUX_DELAY40": { + "src_wire": "PCIE_INT_INTERFACE_IMUX40", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY40", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX36->>PCIE_INT_INTERFACE_IMUX_OUT36": { + "src_wire": "PCIE_INT_INTERFACE_IMUX36", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT36", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX31->>PCIE_INT_INTERFACE_IMUX_DELAY31": { + "src_wire": "PCIE_INT_INTERFACE_IMUX31", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX25->>PCIE_INT_INTERFACE_IMUX_OUT25": { + "src_wire": "PCIE_INT_INTERFACE_IMUX25", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX47->>PCIE_INT_INTERFACE_IMUX_DELAY47": { + "src_wire": "PCIE_INT_INTERFACE_IMUX47", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY47", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX45->>PCIE_INT_INTERFACE_IMUX_DELAY45": { + "src_wire": "PCIE_INT_INTERFACE_IMUX45", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY45", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX7->>PCIE_INT_INTERFACE_IMUX_OUT7": { + "src_wire": "PCIE_INT_INTERFACE_IMUX7", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY13->PCIE_INT_INTERFACE_IMUX_OUT13": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY13", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B12", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX15->>PCIE_INT_INTERFACE_IMUX_OUT15": { + "src_wire": "PCIE_INT_INTERFACE_IMUX15", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX13->>PCIE_INT_INTERFACE_IMUX_DELAY13": { + "src_wire": "PCIE_INT_INTERFACE_IMUX13", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX11->>PCIE_INT_INTERFACE_IMUX_OUT11": { + "src_wire": "PCIE_INT_INTERFACE_IMUX11", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX32->>PCIE_INT_INTERFACE_IMUX_OUT32": { + "src_wire": "PCIE_INT_INTERFACE_IMUX32", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT32", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B9", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX19->>PCIE_INT_INTERFACE_IMUX_DELAY19": { + "src_wire": "PCIE_INT_INTERFACE_IMUX19", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX23->>PCIE_INT_INTERFACE_IMUX_OUT23": { + "src_wire": "PCIE_INT_INTERFACE_IMUX23", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX36->>PCIE_INT_INTERFACE_IMUX_DELAY36": { + "src_wire": "PCIE_INT_INTERFACE_IMUX36", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY36", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY5->PCIE_INT_INTERFACE_IMUX_OUT5": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY5", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX17->>PCIE_INT_INTERFACE_IMUX_OUT17": { + "src_wire": "PCIE_INT_INTERFACE_IMUX17", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX41->>PCIE_INT_INTERFACE_IMUX_DELAY41": { + "src_wire": "PCIE_INT_INTERFACE_IMUX41", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY41", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B7", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY9->PCIE_INT_INTERFACE_IMUX_OUT9": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY9", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX17->>PCIE_INT_INTERFACE_IMUX_DELAY17": { + "src_wire": "PCIE_INT_INTERFACE_IMUX17", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX6->>PCIE_INT_INTERFACE_IMUX_DELAY6": { + "src_wire": "PCIE_INT_INTERFACE_IMUX6", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX5->>PCIE_INT_INTERFACE_IMUX_DELAY5": { + "src_wire": "PCIE_INT_INTERFACE_IMUX5", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX30->>PCIE_INT_INTERFACE_IMUX_DELAY30": { + "src_wire": "PCIE_INT_INTERFACE_IMUX30", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX10->>PCIE_INT_INTERFACE_IMUX_OUT10": { + "src_wire": "PCIE_INT_INTERFACE_IMUX10", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY38->PCIE_INT_INTERFACE_IMUX_OUT38": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY38", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT38", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B10", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY15->PCIE_INT_INTERFACE_IMUX_OUT15": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY15", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX14->>PCIE_INT_INTERFACE_IMUX_DELAY14": { + "src_wire": "PCIE_INT_INTERFACE_IMUX14", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX38->>PCIE_INT_INTERFACE_IMUX_OUT38": { + "src_wire": "PCIE_INT_INTERFACE_IMUX38", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT38", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY0->PCIE_INT_INTERFACE_IMUX_OUT0": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY0", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX35->>PCIE_INT_INTERFACE_IMUX_OUT35": { + "src_wire": "PCIE_INT_INTERFACE_IMUX35", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT35", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX22->>PCIE_INT_INTERFACE_IMUX_DELAY22": { + "src_wire": "PCIE_INT_INTERFACE_IMUX22", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY37->PCIE_INT_INTERFACE_IMUX_OUT37": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY37", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT37", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX11->>PCIE_INT_INTERFACE_IMUX_DELAY11": { + "src_wire": "PCIE_INT_INTERFACE_IMUX11", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY35->PCIE_INT_INTERFACE_IMUX_OUT35": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY35", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT35", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX30->>PCIE_INT_INTERFACE_IMUX_OUT30": { + "src_wire": "PCIE_INT_INTERFACE_IMUX30", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX28->>PCIE_INT_INTERFACE_IMUX_DELAY28": { + "src_wire": "PCIE_INT_INTERFACE_IMUX28", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX35->>PCIE_INT_INTERFACE_IMUX_DELAY35": { + "src_wire": "PCIE_INT_INTERFACE_IMUX35", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY35", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B5", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B22", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY28->PCIE_INT_INTERFACE_IMUX_OUT28": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY28", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY25->PCIE_INT_INTERFACE_IMUX_OUT25": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY25", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX40->>PCIE_INT_INTERFACE_IMUX_OUT40": { + "src_wire": "PCIE_INT_INTERFACE_IMUX40", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT40", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX14->>PCIE_INT_INTERFACE_IMUX_OUT14": { + "src_wire": "PCIE_INT_INTERFACE_IMUX14", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX7->>PCIE_INT_INTERFACE_IMUX_DELAY7": { + "src_wire": "PCIE_INT_INTERFACE_IMUX7", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX43->>PCIE_INT_INTERFACE_IMUX_OUT43": { + "src_wire": "PCIE_INT_INTERFACE_IMUX43", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT43", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY16->PCIE_INT_INTERFACE_IMUX_OUT16": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY16", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY30->PCIE_INT_INTERFACE_IMUX_OUT30": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY30", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX19->>PCIE_INT_INTERFACE_IMUX_OUT19": { + "src_wire": "PCIE_INT_INTERFACE_IMUX19", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX46->>PCIE_INT_INTERFACE_IMUX_OUT46": { + "src_wire": "PCIE_INT_INTERFACE_IMUX46", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT46", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX6->>PCIE_INT_INTERFACE_IMUX_OUT6": { + "src_wire": "PCIE_INT_INTERFACE_IMUX6", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX5->>PCIE_INT_INTERFACE_IMUX_OUT5": { + "src_wire": "PCIE_INT_INTERFACE_IMUX5", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY32->PCIE_INT_INTERFACE_IMUX_OUT32": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY32", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT32", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY2->PCIE_INT_INTERFACE_IMUX_OUT2": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY2", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY7->PCIE_INT_INTERFACE_IMUX_OUT7": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY7", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX18->>PCIE_INT_INTERFACE_IMUX_OUT18": { + "src_wire": "PCIE_INT_INTERFACE_IMUX18", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B13", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX42->>PCIE_INT_INTERFACE_IMUX_DELAY42": { + "src_wire": "PCIE_INT_INTERFACE_IMUX42", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY42", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY26->PCIE_INT_INTERFACE_IMUX_OUT26": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY26", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX21->>PCIE_INT_INTERFACE_IMUX_DELAY21": { + "src_wire": "PCIE_INT_INTERFACE_IMUX21", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX12->>PCIE_INT_INTERFACE_IMUX_DELAY12": { + "src_wire": "PCIE_INT_INTERFACE_IMUX12", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY42->PCIE_INT_INTERFACE_IMUX_OUT42": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY42", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT42", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY43->PCIE_INT_INTERFACE_IMUX_OUT43": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY43", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT43", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY40->PCIE_INT_INTERFACE_IMUX_OUT40": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY40", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT40", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX34->>PCIE_INT_INTERFACE_IMUX_OUT34": { + "src_wire": "PCIE_INT_INTERFACE_IMUX34", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT34", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX20->>PCIE_INT_INTERFACE_IMUX_OUT20": { + "src_wire": "PCIE_INT_INTERFACE_IMUX20", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY8->PCIE_INT_INTERFACE_IMUX_OUT8": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY8", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX27->>PCIE_INT_INTERFACE_IMUX_OUT27": { + "src_wire": "PCIE_INT_INTERFACE_IMUX27", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT27", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX32->>PCIE_INT_INTERFACE_IMUX_DELAY32": { + "src_wire": "PCIE_INT_INTERFACE_IMUX32", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY32", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B3", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY44->PCIE_INT_INTERFACE_IMUX_OUT44": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY44", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT44", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX26->>PCIE_INT_INTERFACE_IMUX_OUT26": { + "src_wire": "PCIE_INT_INTERFACE_IMUX26", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX1->>PCIE_INT_INTERFACE_IMUX_OUT1": { + "src_wire": "PCIE_INT_INTERFACE_IMUX1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX2->>PCIE_INT_INTERFACE_IMUX_DELAY2": { + "src_wire": "PCIE_INT_INTERFACE_IMUX2", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX9->>PCIE_INT_INTERFACE_IMUX_OUT9": { + "src_wire": "PCIE_INT_INTERFACE_IMUX9", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B2", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX34->>PCIE_INT_INTERFACE_IMUX_DELAY34": { + "src_wire": "PCIE_INT_INTERFACE_IMUX34", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY34", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY34->PCIE_INT_INTERFACE_IMUX_OUT34": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY34", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT34", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX37->>PCIE_INT_INTERFACE_IMUX_OUT37": { + "src_wire": "PCIE_INT_INTERFACE_IMUX37", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT37", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B11", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B16", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX33->>PCIE_INT_INTERFACE_IMUX_OUT33": { + "src_wire": "PCIE_INT_INTERFACE_IMUX33", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT33", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY22->PCIE_INT_INTERFACE_IMUX_OUT22": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY22", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX24->>PCIE_INT_INTERFACE_IMUX_OUT24": { + "src_wire": "PCIE_INT_INTERFACE_IMUX24", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY24->PCIE_INT_INTERFACE_IMUX_OUT24": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY24", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY11->PCIE_INT_INTERFACE_IMUX_OUT11": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY11", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY39->PCIE_INT_INTERFACE_IMUX_OUT39": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY39", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT39", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY31->PCIE_INT_INTERFACE_IMUX_OUT31": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY31", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX47->>PCIE_INT_INTERFACE_IMUX_OUT47": { + "src_wire": "PCIE_INT_INTERFACE_IMUX47", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT47", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX43->>PCIE_INT_INTERFACE_IMUX_DELAY43": { + "src_wire": "PCIE_INT_INTERFACE_IMUX43", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY43", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX16->>PCIE_INT_INTERFACE_IMUX_DELAY16": { + "src_wire": "PCIE_INT_INTERFACE_IMUX16", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX16->>PCIE_INT_INTERFACE_IMUX_OUT16": { + "src_wire": "PCIE_INT_INTERFACE_IMUX16", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX3->>PCIE_INT_INTERFACE_IMUX_DELAY3": { + "src_wire": "PCIE_INT_INTERFACE_IMUX3", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX45->>PCIE_INT_INTERFACE_IMUX_OUT45": { + "src_wire": "PCIE_INT_INTERFACE_IMUX45", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT45", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX27->>PCIE_INT_INTERFACE_IMUX_DELAY27": { + "src_wire": "PCIE_INT_INTERFACE_IMUX27", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY27", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY41->PCIE_INT_INTERFACE_IMUX_OUT41": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY41", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT41", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX10->>PCIE_INT_INTERFACE_IMUX_DELAY10": { + "src_wire": "PCIE_INT_INTERFACE_IMUX10", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B4", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX4->>PCIE_INT_INTERFACE_IMUX_OUT4": { + "src_wire": "PCIE_INT_INTERFACE_IMUX4", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX0->>PCIE_INT_INTERFACE_IMUX_DELAY0": { + "src_wire": "PCIE_INT_INTERFACE_IMUX0", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX13->>PCIE_INT_INTERFACE_IMUX_OUT13": { + "src_wire": "PCIE_INT_INTERFACE_IMUX13", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY10->PCIE_INT_INTERFACE_IMUX_OUT10": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY10", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY14->PCIE_INT_INTERFACE_IMUX_OUT14": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY14", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B6", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY46->PCIE_INT_INTERFACE_IMUX_OUT46": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY46", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT46", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX2->>PCIE_INT_INTERFACE_IMUX_OUT2": { + "src_wire": "PCIE_INT_INTERFACE_IMUX2", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX1->>PCIE_INT_INTERFACE_IMUX_DELAY1": { + "src_wire": "PCIE_INT_INTERFACE_IMUX1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY1->PCIE_INT_INTERFACE_IMUX_OUT1": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX42->>PCIE_INT_INTERFACE_IMUX_OUT42": { + "src_wire": "PCIE_INT_INTERFACE_IMUX42", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT42", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX39->>PCIE_INT_INTERFACE_IMUX_DELAY39": { + "src_wire": "PCIE_INT_INTERFACE_IMUX39", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY39", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B18", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY27->PCIE_INT_INTERFACE_IMUX_OUT27": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY27", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT27", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY29->PCIE_INT_INTERFACE_IMUX_OUT29": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY29", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX22->>PCIE_INT_INTERFACE_IMUX_OUT22": { + "src_wire": "PCIE_INT_INTERFACE_IMUX22", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY21->PCIE_INT_INTERFACE_IMUX_OUT21": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY21", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY20->PCIE_INT_INTERFACE_IMUX_OUT20": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY20", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX29->>PCIE_INT_INTERFACE_IMUX_DELAY29": { + "src_wire": "PCIE_INT_INTERFACE_IMUX29", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX39->>PCIE_INT_INTERFACE_IMUX_OUT39": { + "src_wire": "PCIE_INT_INTERFACE_IMUX39", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT39", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX41->>PCIE_INT_INTERFACE_IMUX_OUT41": { + "src_wire": "PCIE_INT_INTERFACE_IMUX41", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT41", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX4->>PCIE_INT_INTERFACE_IMUX_DELAY4": { + "src_wire": "PCIE_INT_INTERFACE_IMUX4", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B23", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX26->>PCIE_INT_INTERFACE_IMUX_DELAY26": { + "src_wire": "PCIE_INT_INTERFACE_IMUX26", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX28->>PCIE_INT_INTERFACE_IMUX_OUT28": { + "src_wire": "PCIE_INT_INTERFACE_IMUX28", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX3->>PCIE_INT_INTERFACE_IMUX_OUT3": { + "src_wire": "PCIE_INT_INTERFACE_IMUX3", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY12->PCIE_INT_INTERFACE_IMUX_OUT12": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY12", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX46->>PCIE_INT_INTERFACE_IMUX_DELAY46": { + "src_wire": "PCIE_INT_INTERFACE_IMUX46", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY46", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY19->PCIE_INT_INTERFACE_IMUX_OUT19": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY19", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX44->>PCIE_INT_INTERFACE_IMUX_DELAY44": { + "src_wire": "PCIE_INT_INTERFACE_IMUX44", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY44", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX9->>PCIE_INT_INTERFACE_IMUX_DELAY9": { + "src_wire": "PCIE_INT_INTERFACE_IMUX9", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX33->>PCIE_INT_INTERFACE_IMUX_DELAY33": { + "src_wire": "PCIE_INT_INTERFACE_IMUX33", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY33", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B8", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY45->PCIE_INT_INTERFACE_IMUX_OUT45": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY45", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT45", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B21", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B14", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX8->>PCIE_INT_INTERFACE_IMUX_DELAY8": { + "src_wire": "PCIE_INT_INTERFACE_IMUX8", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX21->>PCIE_INT_INTERFACE_IMUX_OUT21": { + "src_wire": "PCIE_INT_INTERFACE_IMUX21", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX12->>PCIE_INT_INTERFACE_IMUX_OUT12": { + "src_wire": "PCIE_INT_INTERFACE_IMUX12", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX44->>PCIE_INT_INTERFACE_IMUX_OUT44": { + "src_wire": "PCIE_INT_INTERFACE_IMUX44", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT44", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX29->>PCIE_INT_INTERFACE_IMUX_OUT29": { + "src_wire": "PCIE_INT_INTERFACE_IMUX29", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY47->PCIE_INT_INTERFACE_IMUX_OUT47": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY47", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT47", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX25->>PCIE_INT_INTERFACE_IMUX_DELAY25": { + "src_wire": "PCIE_INT_INTERFACE_IMUX25", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX31->>PCIE_INT_INTERFACE_IMUX_OUT31": { + "src_wire": "PCIE_INT_INTERFACE_IMUX31", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B20", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B0", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX38->>PCIE_INT_INTERFACE_IMUX_DELAY38": { + "src_wire": "PCIE_INT_INTERFACE_IMUX38", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY38", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY33->PCIE_INT_INTERFACE_IMUX_OUT33": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY33", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT33", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY6->PCIE_INT_INTERFACE_IMUX_OUT6": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY6", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX0->>PCIE_INT_INTERFACE_IMUX_OUT0": { + "src_wire": "PCIE_INT_INTERFACE_IMUX0", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX37->>PCIE_INT_INTERFACE_IMUX_DELAY37": { + "src_wire": "PCIE_INT_INTERFACE_IMUX37", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY37", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B17", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY23->PCIE_INT_INTERFACE_IMUX_OUT23": { + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY23", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX23->>PCIE_INT_INTERFACE_IMUX_DELAY23": { + "src_wire": "PCIE_INT_INTERFACE_IMUX23", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX15->>PCIE_INT_INTERFACE_IMUX_DELAY15": { + "src_wire": "PCIE_INT_INTERFACE_IMUX15", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY15", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_PCIE_NULL.json b/kintex7/tile_type_PCIE_NULL.json new file mode 100644 index 0000000..d121130 --- /dev/null +++ b/kintex7/tile_type_PCIE_NULL.json @@ -0,0 +1,8 @@ +{ + "tile_type": "PCIE_NULL", + "sites": [], + "wires": [ + "DUMMYFOO" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_PCIE_TOP.json b/kintex7/tile_type_PCIE_TOP.json new file mode 100644 index 0000000..740c377 --- /dev/null +++ b/kintex7/tile_type_PCIE_TOP.json @@ -0,0 +1,5132 @@ +{ + "tile_type": "PCIE_TOP", + "sites": [], + "wires": [ + "PCIE_TOP_TRNTD23", + "PCIE_LH12_0", + "PCIE_LOGIC_OUTS_B22_L_0", + "PCIE_LOGIC_OUTS_B15_R_2", + "PCIE_LOGIC_OUTS_B15_L_4", + "PCIE_LOGIC_OUTS_B19_L_3", + "PCIE_SE2A0_1", + "PCIE_IMUX20_L_0", + "PCIE_CTRL1_R_0", + "PCIE_SW2A2_1", + "PCIE_TOP_CFGDSN58", + "PCIE_IMUX8_R_1", + "PCIE_EE4BEG3_3", + "PCIE_TOP_MIMRXWADDR2", + "PCIE_LOGIC_OUTS_B13_L_3", + "PCIE_WW2A1_2", + "PCIE_WW4B0_4", + "PCIE_IMUX21_L_4", + "PCIE_EE2A0_4", + "PCIE_IMUX10_R_4", + "PCIE_TOP_TRNRD87", + "PCIE_FAN3_R_2", + "PCIE_IMUX10_R_0", + "PCIE_WW4C1_4", + "PCIE_TOP_TRNTD16", + "PCIE_LOGIC_OUTS_B4_L_1", + "PCIE_LOGIC_OUTS_B10_R_2", + "PCIE_EE4C3_2", + "PCIE_EE4A2_1", + "PCIE_BLOCK_OUTS_B1_L_0", + "PCIE_NE4BEG1_1", + "PCIE_NE2A2_2", + "PCIE_TOP_PIPERX4DATA3", + "PCIE_TOP_TRNRD76", + "PCIE_IMUX16_R_4", + "PCIE_IMUX3_R_0", + "PCIE_EE4C2_3", + "PCIE_BLOCK_OUTS_B3_R_2", + "PCIE_CTRL1_R_3", + "PCIE_IMUX35_R_0", + "PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED", + "PCIE_NE4C1_4", + "PCIE_EE4C0_4", + "PCIE_TOP_TRNRDLLPDATA59", + "PCIE_WW4C3_2", + "PCIE_TOP_TRNTD29", + "PCIE_NE2A2_4", + "PCIE_TOP_EDTBYPASS", + "PCIE_TOP_CFGTRANSACTIONADDR0", + "PCIE_TOP_SCANMODEN", + "PCIE_NW2A0_1", + "PCIE_NE4C2_0", + "PCIE_LOGIC_OUTS_B7_R_2", + "PCIE_TOP_MIMRXWDATA27", + "PCIE_WL1END3_0", + "PCIE_LOGIC_OUTS_B11_R_0", + "PCIE_LOGIC_OUTS_B23_R_4", + "PCIE_IMUX25_R_3", + "PCIE_TOP_TRNRD96", + "PCIE_BYP0_L_4", + "PCIE_FAN6_R_1", + "PCIE_SE4BEG1_1", + "PCIE_IMUX18_R_0", + "PCIE_NW4END0_2", + "PCIE_NW4A1_4", + "PCIE_BYP5_R_3", + "PCIE_LOGIC_OUTS_B21_L_1", + "PCIE_LOGIC_OUTS_B6_L_4", + "PCIE_IMUX0_R_2", + "PCIE_BYP5_R_4", + "PCIE_IMUX19_L_2", + "PCIE_BYP3_R_3", + "PCIE_TOP_TRNRD64", + "PCIE_LOGIC_OUTS_B18_R_3", + "PCIE_IMUX20_R_1", + "PCIE_LOGIC_OUTS_B5_R_0", + "PCIE_CLK1_R_0", + "PCIE_TOP_PIPERX0DATA6", + "PCIE_LOGIC_OUTS_B15_L_2", + "PCIE_SW4END0_3", + "PCIE_IMUX4_L_4", + "PCIE_IMUX13_R_1", + "PCIE_BYP7_L_0", + "PCIE_BYP6_R_0", + "PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK", + "PCIE_IMUX8_R_3", + "PCIE_IMUX23_R_0", + "PCIE_IMUX40_L_3", + "PCIE_IMUX45_R_1", + "PCIE_TOP_MIMRXRDATA55", + "PCIE_BYP1_R_3", + "PCIE_TOP_EDTUPDATE", + "PCIE_IMUX28_R_2", + "PCIE_BYP1_L_1", + "PCIE_TOP_TRNRDLLPDATA56", + "PCIE_TOP_MIMRXWDATA22", + "PCIE_TOP_TRNRD79", + "PCIE_IMUX0_R_1", + "PCIE_IMUX3_R_4", + "PCIE_WW4END2_1", + "PCIE_SE4BEG2_2", + "PCIE_NE2A0_1", + "PCIE_LOGIC_OUTS_B18_R_4", + "PCIE_BLOCK_OUTS_B0_L_1", + "PCIE_NE4C2_3", + "PCIE_EE4BEG2_0", + "PCIE_MONITOR_N_3", + "PCIE_LH10_1", + "PCIE_NW4A0_1", + "PCIE_TOP_TRNTD27", + "PCIE_LH5_2", + "PCIE_BYP6_R_1", + "PCIE_TOP_DBGVECA5", + "PCIE_SE4C2_3", + "PCIE_FAN1_R_0", + "PCIE_IMUX33_R_1", + "PCIE_LOGIC_OUTS_B14_L_2", + "PCIE_BLOCK_OUTS_B3_R_1", + "PCIE_IMUX0_R_4", + "PCIE_TOP_DRPRDY", + "PCIE_EE4BEG0_0", + "PCIE_EE4BEG0_4", + "PCIE_IMUX24_L_0", + "PCIE_ER1BEG0_0", + "PCIE_TOP_TRNRD66", + "PCIE_EE4A1_2", + "PCIE_BYP0_R_2", + "PCIE_SW4END2_4", + "PCIE_IMUX2_R_2", + "PCIE_LOGIC_OUTS_B19_R_3", + "PCIE_SE4BEG0_4", + "PCIE_MONITOR_P_0", + "PCIE_BLOCK_OUTS_B0_R_0", + "PCIE_TOP_TRNRDLLPDATA50", + "PCIE_CLK0_R_4", + "PCIE_IMUX40_R_1", + "PCIE_WW4END0_2", + "PCIE_IMUX9_R_2", + "PCIE_IMUX11_R_0", + "PCIE_IMUX24_R_3", + "PCIE_LOGIC_OUTS_B22_L_3", + "PCIE_ER1BEG1_2", + "PCIE_TOP_CFGTRANSACTIONADDR1", + "PCIE_BLOCK_OUTS_B0_L_0", + "PCIE_BYP2_L_0", + "PCIE_IMUX6_L_0", + "PCIE_LOGIC_OUTS_B12_L_0", + "PCIE_LOGIC_OUTS_B13_L_0", + "PCIE_MONITOR_P_1", + "PCIE_IMUX14_L_0", + "PCIE_SE2A2_3", + "PCIE_LOGIC_OUTS_B1_R_4", + "PCIE_IMUX28_L_2", + "PCIE_LOGIC_OUTS_B14_L_0", + "PCIE_IMUX37_L_1", + "PCIE_FAN5_R_0", + "PCIE_EE2A2_2", + "PCIE_IMUX41_L_2", + "PCIE_IMUX34_R_4", + "PCIE_IMUX21_R_4", + "PCIE_LH9_2", + "PCIE_SE4C1_1", + "PCIE_LOGIC_OUTS_B9_L_2", + "PCIE_LOGIC_OUTS_B19_R_2", + "PCIE_IMUX22_R_0", + "PCIE_TOP_PIPERX0PHYSTATUS", + "PCIE_EE4A0_0", + "PCIE_LH1_2", + "PCIE_WW4B1_4", + "PCIE_SE4C3_2", + "PCIE_IMUX26_L_2", + "PCIE_TOP_TRNTD15", + "PCIE_LOGIC_OUTS_B6_R_0", + "PCIE_NE4BEG1_2", + "PCIE_BYP1_R_2", + "PCIE_IMUX17_R_4", + "PCIE_LOGIC_OUTS_B11_L_0", + "PCIE_IMUX1_L_4", + "PCIE_TOP_MIMRXRDATA23", + "PCIE_TOP_TRNRDLLPDATA35", + "PCIE_TOP_TRNRD82", + "PCIE_NE2A3_3", + "PCIE_IMUX36_L_4", + "PCIE_IMUX12_R_2", + "PCIE_EE4B0_3", + "PCIE_TOP_CFGMGMTDO22", + "PCIE_SW4END3_2", + "PCIE_SW4END0_2", + "PCIE_EE4A1_3", + "PCIE_CLK1_L_1", + "PCIE_TOP_CFGLINKCONTROLASPMCONTROL1", + "PCIE_IMUX0_L_1", + "PCIE_IMUX27_R_3", + "PCIE_TOP_TRNTD17", + "PCIE_EL1BEG2_2", + "PCIE_LOGIC_OUTS_B13_L_2", + "PCIE_LOGIC_OUTS_B9_R_4", + "PCIE_TOP_CFGLINKCONTROLRCB", + "PCIE_TOP_CFGCOMMANDBUSMASTERENABLE", + "PCIE_TOP_DBGVECA10", + "PCIE_BYP2_L_2", + "PCIE_EE4A3_2", + "PCIE_NE2A3_1", + "PCIE_EE2BEG2_3", + "PCIE_TOP_TRNTD30", + "PCIE_IMUX5_R_2", + "PCIE_TOP_TRNRDLLPDATA49", + "PCIE_LOGIC_OUTS_B10_L_0", + "PCIE_NE2A0_3", + "PCIE_TOP_MIMRXWDATA10", + "PCIE_WR1END2_0", + "PCIE_IMUX39_R_4", + "PCIE_TOP_LL2TLPRCV", + "PCIE_TOP_PLDBGVEC8", + "PCIE_LOGIC_OUTS_B20_L_2", + "PCIE_CTRL1_L_0", + "PCIE_LOGIC_OUTS_B23_R_3", + "PCIE_LH11_0", + "PCIE_IMUX21_L_0", + "PCIE_NW2A2_2", + "PCIE_TOP_TL2PPMSUSPENDREQ", + "PCIE_IMUX26_R_0", + "PCIE_EE2BEG1_1", + "PCIE_LOGIC_OUTS_B12_R_4", + "PCIE_IMUX18_R_1", + "PCIE_IMUX16_L_0", + "PCIE_LH12_2", + "PCIE_TOP_MIMRXRDATA43", + "PCIE_TOP_TRNTD13", + "PCIE_TOP_MIMRXRDATA46", + "PCIE_SW2A3_4", + "PCIE_LOGIC_OUTS_B4_L_0", + "PCIE_TOP_MIMRXRDATA45", + "PCIE_TOP_CFGTRANSACTIONTYPE", + "PCIE_EE4C3_0", + "PCIE_EL1BEG3_2", + "PCIE_TOP_DRPDI15", + "PCIE_TOP_MIMRXRDATA37", + "PCIE_TOP_TRNTD24", + "PCIE_FAN0_L_3", + "PCIE_IMUX47_R_2", + "PCIE_IMUX11_L_4", + "PCIE_LH11_4", + "PCIE_TOP_CFGERRTLPCPLHEADER38", + "PCIE_LOGIC_OUTS_B0_R_4", + "PCIE_LOGIC_OUTS_B14_R_4", + "PCIE_FAN0_R_2", + "PCIE_IMUX37_R_0", + "PCIE_IMUX9_R_4", + "PCIE_LOGIC_OUTS_B17_L_2", + "PCIE_IMUX17_R_3", + "PCIE_BYP1_L_2", + "PCIE_TOP_DRPDI0", + "PCIE_MONITOR_P_3", + "PCIE_IMUX38_L_0", + "PCIE_SW4A1_1", + "PCIE_WR1END0_3", + "PCIE_TOP_DRPDI5", + "PCIE_WW4END1_3", + "PCIE_CLK0_L_0", + "PCIE_LOGIC_OUTS_B15_R_4", + "PCIE_FAN0_L_2", + "PCIE_TOP_CFGLINKCONTROLLINKDISABLE", + "PCIE_TOP_TRNRDLLPDATA40", + "PCIE_IMUX21_R_2", + "PCIE_WW2A2_1", + "PCIE_IMUX11_L_0", + "PCIE_IMUX2_L_0", + "PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN", + "PCIE_TOP_TRNTDLLPDATA23", + "PCIE_FAN1_R_3", + "PCIE_LOGIC_OUTS_B0_R_0", + "PCIE_WL1END1_4", + "PCIE_BYP7_L_4", + "PCIE_IMUX9_L_4", + "PCIE_IMUX38_L_1", + "PCIE_EE4BEG0_3", + "PCIE_IMUX14_L_1", + "PCIE_NE4C0_1", + "PCIE_EL1BEG2_3", + "PCIE_IMUX12_L_2", + "PCIE_LH5_0", + "PCIE_SW2A0_4", + "PCIE_CLK1_R_3", + "PCIE_WW2END2_2", + "PCIE_CLK1_L_3", + "PCIE_LH7_1", + "PCIE_FAN1_R_1", + "PCIE_LOGIC_OUTS_B17_L_1", + "PCIE_NW2A3_1", + "PCIE_WW4A1_1", + "PCIE_EE4A0_2", + "PCIE_BYP1_R_0", + "PCIE_LOGIC_OUTS_B3_L_3", + "PCIE_IMUX42_L_0", + "PCIE_TOP_MIMRXRADDR4", + "PCIE_WW4B3_4", + "PCIE_IMUX5_R_1", + "PCIE_LOGIC_OUTS_B16_L_4", + "PCIE_WL1END1_1", + "PCIE_IMUX41_L_0", + "PCIE_IMUX38_R_4", + "PCIE_LOGIC_OUTS_B17_R_2", + "PCIE_WW4C2_2", + "PCIE_LOGIC_OUTS_B8_R_1", + "PCIE_TOP_PIPERX4DATA7", + "PCIE_IMUX11_L_1", + "PCIE_IMUX37_L_3", + "PCIE_IMUX23_R_4", + "PCIE_LOGIC_OUTS_B8_L_3", + "PCIE_TOP_CFGMGMTDO29", + "PCIE_IMUX39_L_1", + "PCIE_SE4BEG1_4", + "PCIE_IMUX28_R_1", + "PCIE_IMUX38_R_3", + "PCIE_TOP_MIMRXWADDR1", + "PCIE_SE4C0_4", + "PCIE_LOGIC_OUTS_B21_R_0", + "PCIE_BYP6_L_3", + "PCIE_LH6_3", + "PCIE_IMUX35_L_4", + "PCIE_TOP_CFGDEVCONTROL2IDOREQEN", + "PCIE_NW2A1_1", + "PCIE_FAN5_L_2", + "PCIE_NW4END1_4", + "PCIE_TOP_TRNRD62", + "PCIE_WW4A2_3", + "PCIE_FAN4_R_1", + "PCIE_IMUX22_L_3", + "PCIE_LH3_2", + "PCIE_TOP_CFGDEVCONTROL2LTREN", + "PCIE_NW4END3_3", + "PCIE_EE2BEG2_1", + "PCIE_NE4BEG2_3", + "PCIE_IMUX9_L_1", + "PCIE_IMUX35_R_2", + "PCIE_SE2A0_4", + "PCIE_TOP_CFGERRAERHEADERLOG2", + "PCIE_BLOCK_OUTS_B1_R_1", + "PCIE_WR1END2_3", + "PCIE_BYP5_L_2", + "PCIE_IMUX3_R_3", + "PCIE_BLOCK_OUTS_B2_R_1", + "PCIE_IMUX14_R_1", + "PCIE_CLK0_R_0", + "PCIE_IMUX18_L_2", + "PCIE_TOP_PIPERX4PHYSTATUS", + "PCIE_WW4END0_4", + "PCIE_BYP3_L_3", + "PCIE_FAN3_R_1", + "PCIE_IMUX7_L_1", + "PCIE_BLOCK_OUTS_B1_R_0", + "PCIE_IMUX31_R_2", + "PCIE_IMUX47_R_3", + "PCIE_TOP_MIMRXWDATA4", + "PCIE_IMUX43_R_3", + "PCIE_IMUX10_R_2", + "PCIE_BYP1_L_4", + "PCIE_NW4A1_1", + "PCIE_WR1END2_1", + "PCIE_TOP_CFGDEVID14", + "PCIE_WW4C3_1", + "PCIE_TOP_TRNRD84", + "PCIE_WW4C2_4", + "PCIE_WW4B3_1", + "PCIE_EE4A3_1", + "PCIE_IMUX37_R_1", + "PCIE_LOGIC_OUTS_B20_L_1", + "PCIE_TOP_MIMRXRDATA25", + "PCIE_LOGIC_OUTS_B7_R_3", + "PCIE_LOGIC_OUTS_B19_L_0", + "PCIE_NE4C3_2", + "PCIE_IMUX46_R_0", + "PCIE_TOP_CFGERRTLPCPLHEADER34", + "PCIE_FAN1_R_2", + "PCIE_SE2A0_0", + "PCIE_LOGIC_OUTS_B10_L_4", + "PCIE_BYP3_R_0", + "PCIE_TOP_MIMRXWDATA19", + "PCIE_WW4C1_0", + "PCIE_NW2A2_4", + "PCIE_NE4BEG0_2", + "PCIE_EE2BEG1_0", + "PCIE_TOP_PIPERX0CHANISALIGNED", + "PCIE_IMUX9_R_3", + "PCIE_EE4BEG3_2", + "PCIE_WW2END2_0", + "PCIE_IMUX14_L_4", + "PCIE_EE4B3_3", + "PCIE_TOP_TRNRDLLPDATA62", + "PCIE_NW2A3_3", + "PCIE_LOGIC_OUTS_B21_R_3", + "PCIE_IMUX47_L_4", + "PCIE_FAN5_L_3", + "PCIE_TOP_CFGMGMTDO25", + "PCIE_ER1BEG2_4", + "PCIE_LOGIC_OUTS_B18_L_0", + "PCIE_NE4C2_4", + "PCIE_SE4C0_2", + "PCIE_IMUX10_L_4", + "PCIE_TOP_CFGPCIELINKSTATE2", + "PCIE_IMUX20_R_4", + "PCIE_IMUX17_R_1", + "PCIE_EL1BEG0_3", + "PCIE_TOP_CFGDSN63", + "PCIE_LH2_0", + "PCIE_EL1BEG1_2", + "PCIE_IMUX10_R_3", + "PCIE_WW2END2_3", + "PCIE_IMUX21_L_2", + "PCIE_TOP_DBGVECA20", + "PCIE_TOP_DBGVECA0", + "PCIE_IMUX43_L_2", + "PCIE_TOP_CFGMGMTDO26", + "PCIE_WW4END3_4", + "PCIE_LOGIC_OUTS_B10_L_2", + "PCIE_IMUX18_R_3", + "PCIE_TOP_DRPDO1", + "PCIE_TOP_DRPDI10", + "PCIE_LH2_2", + "PCIE_TOP_MIMRXRDATA42", + "PCIE_TOP_CFGMGMTDO23", + "PCIE_IMUX36_R_1", + "PCIE_IMUX27_L_0", + "PCIE_BLOCK_OUTS_B2_R_4", + "PCIE_TOP_MIMRXRADDR1", + "PCIE_SE4BEG2_3", + "PCIE_TOP_MIMRXRDATA54", + "PCIE_NE4C3_4", + "PCIE_IMUX34_R_2", + "PCIE_TOP_TRNTDLLPDATA21", + "PCIE_LOGIC_OUTS_B2_L_1", + "PCIE_IMUX41_R_3", + "PCIE_IMUX37_L_4", + "PCIE_NE4C0_4", + "PCIE_SW2A2_2", + "PCIE_SW4A3_2", + "PCIE_TOP_TRNRD75", + "PCIE_TOP_CFGINTERRUPTN", + "PCIE_TOP_CFGVCTCVCMAP3", + "PCIE_TOP_CFGVCTCVCMAP6", + "PCIE_IMUX40_R_0", + "PCIE_TOP_CFGERRNORECOVERYN", + "PCIE_IMUX29_L_1", + "PCIE_BLOCK_OUTS_B1_L_3", + "PCIE_IMUX25_L_0", + "PCIE_CTRL1_R_2", + "PCIE_WW4C1_1", + "PCIE_TOP_MIMRXRDATA44", + "PCIE_LOGIC_OUTS_B19_L_1", + "PCIE_FAN2_R_3", + "PCIE_LOGIC_OUTS_B15_L_0", + "PCIE_LOGIC_OUTS_B3_L_2", + "PCIE_IMUX10_R_1", + "PCIE_WW4A2_1", + "PCIE_LH3_1", + "PCIE_IMUX33_L_3", + "PCIE_LOGIC_OUTS_B14_L_3", + "PCIE_TOP_MIMRXWDATA8", + "PCIE_NW4END2_2", + "PCIE_IMUX12_R_0", + "PCIE_SW4END3_4", + "PCIE_IMUX29_R_0", + "PCIE_TOP_CFGMGMTDO20", + "PCIE_FAN7_L_2", + "PCIE_LOGIC_OUTS_B15_R_1", + "PCIE_IMUX30_R_1", + "PCIE_EE4A0_1", + "PCIE_IMUX29_L_2", + "PCIE_IMUX24_R_2", + "PCIE_LH5_3", + "PCIE_IMUX30_R_0", + "PCIE_EE4BEG3_1", + "PCIE_TOP_TRNRDLLPSRCRDY1", + "PCIE_NE2A2_3", + "PCIE_NW4END0_0", + "PCIE_IMUX33_L_4", + "PCIE_WW4B1_0", + "PCIE_LOGIC_OUTS_B16_R_2", + "PCIE_TOP_CFGVCTCVCMAP0", + "PCIE_FAN6_R_3", + "PCIE_NE4C0_0", + "PCIE_TOP_MIMRXRADDR2", + "PCIE_EE4C3_4", + "PCIE_LOGIC_OUTS_B21_L_0", + "PCIE_LOGIC_OUTS_B17_R_3", + "PCIE_SE4BEG3_1", + "PCIE_SE4C0_1", + "PCIE_IMUX19_L_4", + "PCIE_LOGIC_OUTS_B5_L_1", + "PCIE_IMUX18_L_4", + "PCIE_IMUX19_R_4", + "PCIE_FAN4_R_0", + "PCIE_IMUX4_R_3", + "PCIE_NW2A0_2", + "PCIE_TOP_CFGERRAERHEADERLOG8", + "PCIE_TOP_CFGDEVID12", + "PCIE_IMUX12_R_3", + "PCIE_SW4A3_4", + "PCIE_LOGIC_OUTS_B20_R_3", + "PCIE_TOP_MIMRXWDATA9", + "PCIE_CLK1_R_1", + "PCIE_WL1END3_4", + "PCIE_IMUX47_R_4", + "PCIE_CTRL1_R_1", + "PCIE_IMUX19_R_1", + "PCIE_SE4C2_0", + "PCIE_EE4C0_3", + "PCIE_WW4B0_0", + "PCIE_TOP_CFGERRTLPCPLHEADER35", + "PCIE_TOP_MIMRXWDATA29", + "PCIE_IMUX39_L_4", + "PCIE_IMUX25_R_1", + "PCIE_EE4B0_1", + "PCIE_TOP_PIPERX4DATA0", + "PCIE_EE2A3_1", + "PCIE_WW4A0_1", + "PCIE_TOP_CFGLINKCONTROLRETRAINLINK", + "PCIE_BYP4_R_1", + "PCIE_IMUX25_L_3", + "PCIE_SE2A0_3", + "PCIE_LOGIC_OUTS_B2_L_3", + "PCIE_IMUX26_R_2", + "PCIE_LOGIC_OUTS_B16_L_1", + "PCIE_LH3_0", + "PCIE_IMUX6_R_2", + "PCIE_LH7_2", + "PCIE_IMUX22_L_0", + "PCIE_TOP_DBGVECA17", + "PCIE_WR1END0_1", + "PCIE_TOP_LL2TFCINIT2SEQ", + "PCIE_IMUX2_R_0", + "PCIE_BYP4_L_3", + "PCIE_BLOCK_OUTS_B1_L_1", + "PCIE_NW4END3_1", + "PCIE_FAN7_R_4", + "PCIE_EE2BEG3_1", + "PCIE_FAN6_L_1", + "PCIE_IMUX22_L_1", + "PCIE_FAN5_R_3", + "PCIE_TOP_CFGERRTLPCPLHEADER40", + "PCIE_LH3_3", + "PCIE_LOGIC_OUTS_B6_R_2", + "PCIE_IMUX16_L_3", + "PCIE_LOGIC_OUTS_B19_R_4", + "PCIE_SW4A2_4", + "PCIE_BYP7_L_1", + "PCIE_NW4END2_3", + "PCIE_LH12_4", + "PCIE_TOP_CFGERRAERHEADERLOG7", + "PCIE_NE2A0_4", + "PCIE_FAN4_L_3", + "PCIE_WW4END0_1", + "PCIE_NW4A3_0", + "PCIE_TOP_DBGVECA11", + "PCIE_TOP_CFGDEVID3", + "PCIE_IMUX30_L_1", + "PCIE_BYP5_R_1", + "PCIE_LOGIC_OUTS_B6_R_4", + "PCIE_IMUX44_L_1", + "PCIE_TOP_TRNRD80", + "PCIE_BLOCK_OUTS_B2_L_1", + "PCIE_LOGIC_OUTS_B2_R_3", + "PCIE_SW4A1_3", + "PCIE_LOGIC_OUTS_B5_R_1", + "PCIE_EL1BEG1_4", + "PCIE_WW4END1_4", + "PCIE_IMUX4_L_1", + "PCIE_TOP_DBGVECA7", + "PCIE_EE2A1_1", + "PCIE_SW4END2_2", + "PCIE_IMUX39_L_3", + "PCIE_TOP_PL2RECOVERY", + "PCIE_LOGIC_OUTS_B12_R_1", + "PCIE_WW4A0_3", + "PCIE_IMUX13_L_3", + "PCIE_WW2END2_1", + "PCIE_TOP_CFGERRTLPCPLHEADER43", + "PCIE_TOP_TRNTD40", + "PCIE_IMUX12_L_4", + "PCIE_IMUX27_R_4", + "PCIE_TOP_CFGMGMTDO17", + "PCIE_NE4BEG2_1", + "PCIE_IMUX29_R_3", + "PCIE_LH7_4", + "PCIE_TOP_CFGPMRCVREQACKN", + "PCIE_TOP_MIMRXRDATA29", + "PCIE_IMUX27_R_1", + "PCIE_TOP_DBGMODE0", + "PCIE_IMUX16_R_2", + "PCIE_FAN7_L_1", + "PCIE_FAN1_L_1", + "PCIE_TOP_DRPDO12", + "PCIE_IMUX43_L_1", + "PCIE_LOGIC_OUTS_B15_R_0", + "PCIE_TOP_TRNTD25", + "PCIE_IMUX17_L_2", + "PCIE_LOGIC_OUTS_B2_L_0", + "PCIE_WW4C3_4", + "PCIE_BYP3_L_4", + "PCIE_IMUX28_R_4", + "PCIE_LOGIC_OUTS_B11_R_1", + "PCIE_LH5_4", + "PCIE_TOP_MIMRXWDATA49", + "PCIE_TOP_DRPDI12", + "PCIE_IMUX33_R_4", + "PCIE_SW2A2_4", + "PCIE_IMUX33_R_2", + "PCIE_BYP2_L_1", + "PCIE_IMUX36_L_2", + "PCIE_IMUX40_R_4", + "PCIE_TOP_DRPDO13", + "PCIE_TOP_CFGINTERRUPTDI0", + "PCIE_LOGIC_OUTS_B0_L_4", + "PCIE_TOP_TRNRD83", + "PCIE_IMUX25_L_1", + "PCIE_NW4A2_1", + "PCIE_BYP3_R_4", + "PCIE_LOGIC_OUTS_B1_L_1", + "PCIE_LOGIC_OUTS_B23_L_3", + "PCIE_CTRL1_L_2", + "PCIE_BYP4_L_1", + "PCIE_WW4A2_4", + "PCIE_LOGIC_OUTS_B13_R_3", + "PCIE_NE4C1_2", + "PCIE_EE4C0_1", + "PCIE_NE2A3_0", + "PCIE_TOP_TRNRDLLPDATA45", + "PCIE_TOP_LL2SENDENTERL23", + "PCIE_LOGIC_OUTS_B6_R_1", + "PCIE_NW4END2_0", + "PCIE_SW4END1_0", + "PCIE_LOGIC_OUTS_B11_L_2", + "PCIE_IMUX32_L_3", + "PCIE_EE4BEG1_2", + "PCIE_IMUX15_L_4", + "PCIE_TOP_TRNTDLLPDATA31", + "PCIE_LOGIC_OUTS_B0_R_1", + "PCIE_LOGIC_OUTS_B15_R_3", + "PCIE_WR1END3_4", + "PCIE_IMUX21_L_1", + "PCIE_IMUX32_R_1", + "PCIE_MONITOR_N_4", + "PCIE_LOGIC_OUTS_B13_R_0", + "PCIE_SE4BEG0_2", + "PCIE_WL1END2_4", + "PCIE_CTRL1_R_4", + "PCIE_IMUX15_R_2", + "PCIE_IMUX20_L_1", + "PCIE_IMUX6_L_4", + "PCIE_LOGIC_OUTS_B9_R_0", + "PCIE_LOGIC_OUTS_B12_L_3", + "PCIE_LOGIC_OUTS_B23_L_1", + "PCIE_TOP_MIMRXRADDR11", + "PCIE_LOGIC_OUTS_B14_R_2", + "PCIE_CLK0_R_1", + "PCIE_WR1END3_2", + "PCIE_LOGIC_OUTS_B10_L_3", + "PCIE_TOP_TRNTDLLPSRCRDY", + "PCIE_IMUX15_R_1", + "PCIE_WW4A1_0", + "PCIE_BYP3_L_2", + "PCIE_BYP0_L_1", + "PCIE_TOP_MIMRXRDATA40", + "PCIE_LOGIC_OUTS_B13_R_1", + "PCIE_EE2BEG1_4", + "PCIE_IMUX7_L_3", + "PCIE_LOGIC_OUTS_B1_L_0", + "PCIE_BYP0_L_3", + "PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN", + "PCIE_LOGIC_OUTS_B16_L_0", + "PCIE_TOP_MIMRXRADDR9", + "PCIE_TOP_MIMRXWDATA2", + "PCIE_FAN2_R_0", + "PCIE_IMUX13_L_4", + "PCIE_TOP_PIPERX4DATA6", + "PCIE_WW4A3_4", + "PCIE_IMUX19_L_0", + "PCIE_LH4_4", + "PCIE_IMUX0_R_3", + "PCIE_LH4_1", + "PCIE_TOP_TRNRD94", + "PCIE_TOP_CFGMGMTDO28", + "PCIE_EE4A2_3", + "PCIE_LOGIC_OUTS_B18_L_3", + "PCIE_TOP_DRPDI4", + "PCIE_LOGIC_OUTS_B4_R_4", + "PCIE_IMUX42_L_1", + "PCIE_EE2BEG0_3", + "PCIE_WW4B3_3", + "PCIE_ER1BEG3_4", + "PCIE_CLK0_L_2", + "PCIE_NE2A2_0", + "PCIE_LOGIC_OUTS_B3_L_1", + "PCIE_TOP_TRNRDLLPDATA39", + "PCIE_TOP_DRPDO0", + "PCIE_IMUX45_L_2", + "PCIE_NE4C3_3", + "PCIE_IMUX15_R_4", + "PCIE_TOP_DRPDI11", + "PCIE_TOP_MIMRXRDATA41", + "PCIE_TOP_CFGMGMTDO16", + "PCIE_IMUX43_R_4", + "PCIE_LOGIC_OUTS_B11_L_1", + "PCIE_EE2BEG3_3", + "PCIE_FAN1_L_3", + "PCIE_TOP_TRNTD39", + "PCIE_TOP_TRNTD26", + "PCIE_EL1BEG3_1", + "PCIE_EL1BEG0_0", + "PCIE_LOGIC_OUTS_B7_R_0", + "PCIE_IMUX22_L_2", + "PCIE_ER1BEG2_3", + "PCIE_NW4END0_1", + "PCIE_BLOCK_OUTS_B2_L_4", + "PCIE_EE2A1_3", + "PCIE_LOGIC_OUTS_B1_L_2", + "PCIE_WL1END2_1", + "PCIE_IMUX29_R_4", + "PCIE_IMUX20_R_2", + "PCIE_WW4B2_2", + "PCIE_TOP_MIMRXRDATA22", + "PCIE_TOP_MIMRXWDATA21", + "PCIE_SW2A2_0", + "PCIE_LOGIC_OUTS_B23_L_2", + "PCIE_IMUX32_L_1", + "PCIE_TOP_PL2DIRECTEDLSTATE0", + "PCIE_LOGIC_OUTS_B13_R_4", + "PCIE_EE2BEG1_3", + "PCIE_TOP_MIMRXWDATA35", + "PCIE_SW4END1_1", + "PCIE_IMUX44_R_0", + "PCIE_SW2A0_3", + "PCIE_TOP_TRNRD85", + "PCIE_SE4C3_0", + "PCIE_TOP_CFGDEVID7", + "PCIE_FAN0_R_0", + "PCIE_LOGIC_OUTS_B9_L_3", + "PCIE_BLOCK_OUTS_B2_L_0", + "PCIE_TOP_TRNRDLLPDATA46", + "PCIE_IMUX15_L_3", + "PCIE_EE2A0_3", + "PCIE_EE4B3_2", + "PCIE_LH7_0", + "PCIE_TOP_CFGERRTLPCPLHEADER46", + "PCIE_EE2A2_0", + "PCIE_TOP_TRNRD59", + "PCIE_FAN7_R_2", + "PCIE_IMUX33_L_2", + "PCIE_WW4B1_1", + "PCIE_LOGIC_OUTS_B21_R_4", + "PCIE_TOP_MIMRXWDATA11", + "PCIE_TOP_MIMRXRDATA28", + "PCIE_LOGIC_OUTS_B17_L_3", + "PCIE_TOP_CFGDEVID5", + "PCIE_WW2END0_2", + "PCIE_WW2END0_1", + "PCIE_LOGIC_OUTS_B21_R_2", + "PCIE_TOP_TRNTD38", + "PCIE_TOP_MIMRXWDATA34", + "PCIE_EE4B1_0", + "PCIE_TOP_CFGTRANSACTION", + "PCIE_LOGIC_OUTS_B14_R_1", + "PCIE_BYP0_L_2", + "PCIE_LH8_2", + "PCIE_NE4BEG1_0", + "PCIE_EE2BEG2_4", + "PCIE_TOP_PIPERX0DATA5", + "PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE", + "PCIE_IMUX6_L_2", + "PCIE_WW4END0_3", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3", + "PCIE_IMUX12_R_4", + "PCIE_IMUX45_R_3", + "PCIE_EE2A1_4", + "PCIE_SW4A0_0", + "PCIE_LOGIC_OUTS_B15_L_1", + "PCIE_NW4END1_3", + "PCIE_TOP_MIMRXWDATA30", + "PCIE_ER1BEG0_1", + "PCIE_CLK1_L_0", + "PCIE_TOP_MIMRXWDATA25", + "PCIE_SE2A1_4", + "PCIE_LH12_3", + "PCIE_NW4END2_4", + "PCIE_LOGIC_OUTS_B10_R_0", + "PCIE_TOP_PIPERX0CHARISK0", + "PCIE_TOP_DBGVECA2", + "PCIE_LOGIC_OUTS_B8_R_3", + "PCIE_TOP_TRNRD95", + "PCIE_IMUX41_R_1", + "PCIE_BYP2_R_2", + "PCIE_TOP_TRNTD34", + "PCIE_BYP7_R_2", + "PCIE_IMUX34_L_3", + "PCIE_TOP_CFGERRTLPCPLHEADER30", + "PCIE_LOGIC_OUTS_B5_R_4", + "PCIE_SW4END3_0", + "PCIE_IMUX40_L_1", + "PCIE_EL1BEG2_4", + "PCIE_TOP_CFGERRAERHEADERLOG1", + "PCIE_SE4BEG3_3", + "PCIE_TOP_CFGPMRCVENTERL1N", + "PCIE_TOP_CFGPMRCVASREQL1N", + "PCIE_IMUX17_L_4", + "PCIE_BLOCK_OUTS_B2_R_2", + "PCIE_NE4C0_2", + "PCIE_LOGIC_OUTS_B4_R_1", + "PCIE_WW2END0_0", + "PCIE_IMUX0_L_0", + "PCIE_WW4END0_0", + "PCIE_IMUX14_L_3", + "PCIE_FAN2_L_1", + "PCIE_EE4BEG0_2", + "PCIE_EE4C2_1", + "PCIE_FAN6_L_0", + "PCIE_IMUX16_R_3", + "PCIE_FAN6_L_3", + "PCIE_IMUX6_R_3", + "PCIE_TOP_CFGERRAERHEADERLOG5", + "PCIE_IMUX26_R_4", + "PCIE_WW4B0_1", + "PCIE_TOP_CFGDEVID2", + "PCIE_IMUX27_L_1", + "PCIE_FAN3_R_3", + "PCIE_WR1END2_2", + "PCIE_IMUX29_R_1", + "PCIE_SW4A1_4", + "PCIE_TOP_DBGVECA16", + "PCIE_WR1END1_1", + "PCIE_NE4BEG3_4", + "PCIE_TOP_TRNTDLLPDATA27", + "PCIE_IMUX31_R_0", + "PCIE_FAN3_R_4", + "PCIE_TOP_TRNRDLLPDATA32", + "PCIE_BYP4_L_4", + "PCIE_BLOCK_OUTS_B0_L_2", + "PCIE_SE4C0_3", + "PCIE_LOGIC_OUTS_B11_L_4", + "PCIE_LH10_4", + "PCIE_IMUX35_L_3", + "PCIE_EE4C0_0", + "PCIE_EE2A0_1", + "PCIE_IMUX11_R_4", + "PCIE_TOP_DRPDI6", + "PCIE_TOP_CFGDEVID1", + "PCIE_TOP_CFGERRTLPCPLHEADER45", + "PCIE_WW4END2_0", + "PCIE_NW4A0_0", + "PCIE_IMUX41_R_2", + "PCIE_WW4B1_3", + "PCIE_BYP0_R_4", + "PCIE_IMUX37_R_3", + "PCIE_WW2A3_4", + "PCIE_TOP_TRNRDLLPDATA54", + "PCIE_EE2A1_0", + "PCIE_SE2A2_1", + "PCIE_SE4C1_4", + "PCIE_IMUX21_R_1", + "PCIE_FAN3_R_0", + "PCIE_NE2A3_4", + "PCIE_TOP_TRNTD12", + "PCIE_TOP_TRNRD90", + "PCIE_TOP_MIMRXRDATA24", + "PCIE_IMUX8_L_0", + "PCIE_TOP_TRNRD77", + "PCIE_NE4BEG3_1", + "PCIE_TOP_MIMRXWEN", + "PCIE_LOGIC_OUTS_B6_L_0", + "PCIE_IMUX39_R_3", + "PCIE_SE2A3_1", + "PCIE_TOP_MIMRXRDATA51", + "PCIE_SW2A1_1", + "PCIE_LOGIC_OUTS_B8_L_4", + "PCIE_WW4C0_4", + "PCIE_FAN4_R_3", + "PCIE_NW2A3_2", + "PCIE_ER1BEG1_4", + "PCIE_IMUX43_R_2", + "PCIE_BYP4_R_0", + "PCIE_LOGIC_OUTS_B21_L_3", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2", + "PCIE_TOP_CFGPMCSRPMESTATUS", + "PCIE_SW4A1_2", + "PCIE_IMUX45_R_4", + "PCIE_IMUX2_L_3", + "PCIE_IMUX34_R_0", + "PCIE_TOP_CFGERRLOCKEDN", + "PCIE_BYP5_L_1", + "PCIE_NE2A1_1", + "PCIE_TOP_CFGERRAERHEADERLOG4", + "PCIE_TOP_MIMRXRADDR10", + "PCIE_TOP_MIMRXRDATA38", + "PCIE_LOGIC_OUTS_B1_R_1", + "PCIE_NE4BEG1_4", + "PCIE_IMUX8_R_2", + "PCIE_NW4END0_4", + "PCIE_IMUX46_L_0", + "PCIE_IMUX1_R_4", + "PCIE_TOP_TRNTD10", + "PCIE_EE4A3_0", + "PCIE_LOGIC_OUTS_B23_R_1", + "PCIE_TOP_CFGERRTLPCPLHEADER27", + "PCIE_WW2END0_3", + "PCIE_TOP_DBGVECA9", + "PCIE_EE4C1_1", + "PCIE_EL1BEG3_3", + "PCIE_IMUX24_L_2", + "PCIE_LOGIC_OUTS_B2_R_4", + "PCIE_TOP_CFGDEVID11", + "PCIE_EE4A0_4", + "PCIE_NW4A2_3", + "PCIE_IMUX2_R_4", + "PCIE_IMUX1_R_0", + "PCIE_FAN7_L_3", + "PCIE_TOP_PIPERX0DATA2", + "PCIE_NW4END1_0", + "PCIE_SE4C3_1", + "PCIE_LH11_1", + "PCIE_IMUX2_R_3", + "PCIE_LOGIC_OUTS_B22_R_3", + "PCIE_WW2END3_0", + "PCIE_TOP_TRNRD93", + "PCIE_IMUX25_R_4", + "PCIE_IMUX42_R_2", + "PCIE_TOP_DBGVECA6", + "PCIE_TOP_PIPERX4CHANISALIGNED", + "PCIE_EL1BEG0_2", + "PCIE_SE4BEG1_0", + "PCIE_LH1_1", + "PCIE_IMUX26_L_1", + "PCIE_TOP_TRNTD31", + "PCIE_LOGIC_OUTS_B5_L_0", + "PCIE_TOP_MIMRXRDATA34", + "PCIE_TOP_DRPADDR8", + "PCIE_IMUX15_L_1", + "PCIE_TOP_DBGVECA8", + "PCIE_WW2END3_3", + "PCIE_EE4BEG1_1", + "PCIE_SE2A3_4", + "PCIE_NW4END3_4", + "PCIE_TOP_MIMRXWADDR5", + "PCIE_IMUX22_R_4", + "PCIE_TOP_DRPDO14", + "PCIE_WW2A0_1", + "PCIE_IMUX3_L_4", + "PCIE_IMUX32_L_2", + "PCIE_NW2A1_3", + "PCIE_IMUX20_L_3", + "PCIE_SE4C1_2", + "PCIE_IMUX23_L_3", + "PCIE_WW4END1_2", + "PCIE_IMUX40_L_0", + "PCIE_EE2A0_0", + "PCIE_FAN4_R_2", + "PCIE_TOP_DRPDI3", + "PCIE_ER1BEG3_1", + "PCIE_EE2BEG0_0", + "PCIE_IMUX38_L_4", + "PCIE_TOP_TRNRDLLPDATA36", + "PCIE_IMUX41_R_0", + "PCIE_TOP_MIMRXWDATA12", + "PCIE_TOP_LL2SENDPMACK", + "PCIE_TOP_CFGVCTCVCMAP4", + "PCIE_IMUX45_L_4", + "PCIE_CTRL0_R_1", + "PCIE_WW2A1_1", + "PCIE_NE4BEG0_4", + "PCIE_TOP_MIMRXRDATA31", + "PCIE_TOP_PIPETXMARGIN2", + "PCIE_IMUX13_L_1", + "PCIE_BLOCK_OUTS_B3_L_2", + "PCIE_WR1END1_3", + "PCIE_IMUX18_R_4", + "PCIE_TOP_DBGVECB10", + "PCIE_FAN6_R_0", + "PCIE_ER1BEG3_0", + "PCIE_LOGIC_OUTS_B14_L_4", + "PCIE_IMUX30_L_3", + "PCIE_TOP_TRNTDLLPDATA19", + "PCIE_BLOCK_OUTS_B3_R_3", + "PCIE_BYP7_R_4", + "PCIE_LOGIC_OUTS_B7_L_4", + "PCIE_IMUX32_R_2", + "PCIE_IMUX22_R_3", + "PCIE_IMUX0_L_4", + "PCIE_BYP6_R_3", + "PCIE_ER1BEG3_2", + "PCIE_IMUX38_L_2", + "PCIE_EE2A3_3", + "PCIE_NE4BEG2_2", + "PCIE_TOP_CFGTRANSACTIONADDR2", + "PCIE_BYP4_R_3", + "PCIE_IMUX31_R_3", + "PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN", + "PCIE_LOGIC_OUTS_B19_R_1", + "PCIE_FAN5_L_0", + "PCIE_LH3_4", + "PCIE_EE4B1_2", + "PCIE_IMUX30_L_4", + "PCIE_IMUX19_R_2", + "PCIE_IMUX26_L_4", + "PCIE_EE4C2_0", + "PCIE_LOGIC_OUTS_B18_R_2", + "PCIE_NE4C3_0", + "PCIE_WW4A3_0", + "PCIE_LOGIC_OUTS_B21_L_4", + "PCIE_BYP5_R_2", + "PCIE_IMUX9_R_0", + "PCIE_EE4B3_1", + "PCIE_FAN1_L_4", + "PCIE_TOP_DRPDO2", + "PCIE_FAN3_L_0", + "PCIE_TOP_MIMRXRDATA52", + "PCIE_TOP_CFGERRAERHEADERLOG6", + "PCIE_IMUX15_L_2", + "PCIE_TOP_CFGDEVID10", + "PCIE_IMUX36_R_0", + "PCIE_EE4C1_0", + "PCIE_IMUX36_L_3", + "PCIE_LOGIC_OUTS_B19_L_4", + "PCIE_SW4A1_0", + "PCIE_WL1END2_0", + "PCIE_IMUX31_L_3", + "PCIE_SW2A2_3", + "PCIE_IMUX15_L_0", + "PCIE_ER1BEG2_1", + "PCIE_BYP3_L_1", + "PCIE_TOP_DRPDO4", + "PCIE_EE4B2_2", + "PCIE_IMUX29_L_4", + "PCIE_IMUX16_L_4", + "PCIE_LOGIC_OUTS_B7_R_4", + "PCIE_FAN6_R_2", + "PCIE_IMUX24_L_4", + "PCIE_TOP_TRNRD60", + "PCIE_FAN5_R_1", + "PCIE_IMUX45_L_3", + "PCIE_NW4A2_2", + "PCIE_TOP_MIMRXRDATA32", + "PCIE_NW4END3_0", + "PCIE_SW4A0_3", + "PCIE_BYP6_R_4", + "PCIE_IMUX27_L_2", + "PCIE_LOGIC_OUTS_B9_L_4", + "PCIE_EE2A0_2", + "PCIE_BLOCK_OUTS_B0_R_3", + "PCIE_IMUX47_L_3", + "PCIE_CTRL1_L_4", + "PCIE_IMUX4_R_4", + "PCIE_IMUX13_R_3", + "PCIE_FAN1_L_0", + "PCIE_CTRL1_L_1", + "PCIE_NE4BEG0_1", + "PCIE_IMUX33_L_0", + "PCIE_TOP_TRNRD91", + "PCIE_IMUX41_L_4", + "PCIE_IMUX31_L_4", + "PCIE_SW4A3_1", + "PCIE_TOP_CFGERRAERHEADERLOG3", + "PCIE_IMUX8_R_4", + "PCIE_BYP7_L_3", + "PCIE_LOGIC_OUTS_B11_R_4", + "PCIE_TOP_DRPDO3", + "PCIE_EE2BEG0_4", + "PCIE_IMUX7_R_1", + "PCIE_SW2A1_0", + "PCIE_NE4BEG2_4", + "PCIE_NW4A1_0", + "PCIE_LH8_1", + "PCIE_WR1END0_2", + "PCIE_IMUX19_L_3", + "PCIE_TOP_PL2DIRECTEDLSTATE4", + "PCIE_IMUX20_L_2", + "PCIE_TOP_PIPETXMARGIN1", + "PCIE_WW4B3_2", + "PCIE_BLOCK_OUTS_B1_R_4", + "PCIE_TOP_CFGDSN59", + "PCIE_IMUX3_L_2", + "PCIE_EE2BEG3_2", + "PCIE_WR1END0_4", + "PCIE_IMUX1_L_0", + "PCIE_TOP_LL2TFCINIT1SEQ", + "PCIE_EE2BEG2_0", + "PCIE_IMUX34_R_1", + "PCIE_WR1END3_1", + "PCIE_WW4B0_3", + "PCIE_EE4A1_0", + "PCIE_BYP1_R_1", + "PCIE_IMUX23_L_1", + "PCIE_IMUX11_R_1", + "PCIE_LH10_2", + "PCIE_NW4A0_2", + "PCIE_FAN1_L_2", + "PCIE_ER1BEG2_2", + "PCIE_TOP_CFGMGMTDO27", + "PCIE_TOP_CFGDSN60", + "PCIE_IMUX24_R_4", + "PCIE_BYP4_L_0", + "PCIE_IMUX28_L_3", + "PCIE_FAN2_R_2", + "PCIE_TOP_MIMRXRDATA48", + "PCIE_SW4END3_1", + "PCIE_IMUX13_R_4", + "PCIE_WW4C0_0", + "PCIE_IMUX9_R_1", + "PCIE_IMUX41_L_3", + "PCIE_BYP5_L_3", + "PCIE_FAN4_L_1", + "PCIE_IMUX19_R_3", + "PCIE_LOGIC_OUTS_B11_R_2", + "PCIE_BYP5_L_4", + "PCIE_BYP7_R_0", + "PCIE_MONITOR_N_0", + "PCIE_SW4END2_3", + "PCIE_IMUX38_L_3", + "PCIE_FAN0_R_4", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1", + "PCIE_SE4BEG1_2", + "PCIE_SW4END0_1", + "PCIE_SE4BEG3_2", + "PCIE_IMUX46_L_2", + "PCIE_LOGIC_OUTS_B22_R_4", + "PCIE_TOP_CFGMGMTDO24", + "PCIE_BLOCK_OUTS_B1_L_4", + "PCIE_LOGIC_OUTS_B4_L_4", + "PCIE_SE2A3_3", + "PCIE_BYP7_R_3", + "PCIE_IMUX6_R_1", + "PCIE_BYP7_L_2", + "PCIE_IMUX17_R_0", + "PCIE_EE4C3_1", + "PCIE_SE2A1_1", + "PCIE_LOGIC_OUTS_B14_R_0", + "PCIE_LOGIC_OUTS_B7_L_3", + "PCIE_EE4A1_4", + "PCIE_WW2A2_3", + "PCIE_ER1BEG1_3", + "PCIE_TOP_CFGLINKCONTROLCLOCKPMEN", + "PCIE_LOGIC_OUTS_B18_R_1", + "PCIE_LOGIC_OUTS_B13_L_4", + "PCIE_WW4C2_1", + "PCIE_TOP_MIMRXRDATA53", + "PCIE_TOP_MIMRXRDATA39", + "PCIE_TOP_CFGERRTLPCPLHEADER47", + "PCIE_TOP_PIPERX0DATA1", + "PCIE_LOGIC_OUTS_B10_R_4", + "PCIE_TOP_CFGERRAERHEADERLOG9", + "PCIE_SW2A1_3", + "PCIE_TOP_CFGERRTLPCPLHEADER42", + "PCIE_TOP_TRNRD73", + "PCIE_BYP0_R_1", + "PCIE_TOP_PL2DIRECTEDLSTATE2", + "PCIE_IMUX20_L_4", + "PCIE_TOP_TRNRD67", + "PCIE_TOP_MIMRXWDATA26", + "PCIE_TOP_TRNRD78", + "PCIE_BYP2_L_3", + "PCIE_TOP_CFGMGMTDO19", + "PCIE_IMUX13_R_2", + "PCIE_IMUX44_L_2", + "PCIE_IMUX35_L_0", + "PCIE_FAN2_R_4", + "PCIE_IMUX6_R_0", + "PCIE_TOP_TRNRDLLPDATA44", + "PCIE_WW4A1_4", + "PCIE_TOP_TRNTD14", + "PCIE_TOP_MIMRXWDATA13", + "PCIE_LOGIC_OUTS_B21_L_2", + "PCIE_IMUX42_R_0", + "PCIE_TOP_MIMRXWDATA1", + "PCIE_WW4B1_2", + "PCIE_FAN5_R_2", + "PCIE_BYP2_L_4", + "PCIE_IMUX21_R_0", + "PCIE_WW4B2_1", + "PCIE_TOP_CFGCOMMANDIOENABLE", + "PCIE_TOP_TRNRDLLPDATA33", + "PCIE_IMUX42_R_1", + "PCIE_IMUX19_L_1", + "PCIE_LH1_4", + "PCIE_TOP_TRNRD69", + "PCIE_BLOCK_OUTS_B1_R_2", + "PCIE_TOP_TRNRDLLPDATA47", + "PCIE_IMUX39_L_0", + "PCIE_TOP_DRPDO11", + "PCIE_IMUX8_L_1", + "PCIE_IMUX1_L_3", + "PCIE_BLOCK_OUTS_B3_L_3", + "PCIE_LOGIC_OUTS_B4_R_0", + "PCIE_TOP_TRNTD18", + "PCIE_IMUX23_R_3", + "PCIE_SW4END2_0", + "PCIE_BYP4_L_2", + "PCIE_LH4_0", + "PCIE_IMUX12_L_1", + "PCIE_LH6_0", + "PCIE_TOP_MIMRXRDATA50", + "PCIE_IMUX36_R_2", + "PCIE_NE2A1_4", + "PCIE_BYP6_L_4", + "PCIE_LOGIC_OUTS_B20_R_2", + "PCIE_TOP_CFGDSN57", + "PCIE_NE2A0_2", + "PCIE_LOGIC_OUTS_B20_L_0", + "PCIE_TOP_CFGVCTCVCMAP1", + "PCIE_SW4END3_3", + "PCIE_FAN3_L_4", + "PCIE_IMUX30_L_0", + "PCIE_IMUX31_R_1", + "PCIE_IMUX11_L_3", + "PCIE_LOGIC_OUTS_B20_R_4", + "PCIE_EE4A2_0", + "PCIE_IMUX10_L_2", + "PCIE_TOP_MIMRXRDATA20", + "PCIE_IMUX1_L_1", + "PCIE_WW4C0_3", + "PCIE_EE2BEG3_0", + "PCIE_IMUX46_R_3", + "PCIE_LH9_1", + "PCIE_EE2A3_0", + "PCIE_IMUX28_R_3", + "PCIE_EL1BEG3_0", + "PCIE_IMUX17_L_3", + "PCIE_BYP2_R_1", + "PCIE_IMUX22_R_2", + "PCIE_SE2A2_0", + "PCIE_SW4END1_3", + "PCIE_IMUX43_L_3", + "PCIE_TOP_CFGDEVID6", + "PCIE_BLOCK_OUTS_B3_R_0", + "PCIE_IMUX45_R_0", + "PCIE_LOGIC_OUTS_B22_L_1", + "PCIE_IMUX7_L_0", + "PCIE_IMUX9_L_3", + "PCIE_NE4C2_1", + "PCIE_LOGIC_OUTS_B1_L_4", + "PCIE_BYP5_L_0", + "PCIE_IMUX23_L_2", + "PCIE_EE4C1_4", + "PCIE_TOP_TRNRD63", + "PCIE_EL1BEG1_1", + "PCIE_IMUX43_R_1", + "PCIE_TOP_PIPERX4DATA2", + "PCIE_WW2A2_4", + "PCIE_WW4C1_2", + "PCIE_EE4BEG0_1", + "PCIE_LOGIC_OUTS_B17_L_0", + "PCIE_TOP_TRNRD70", + "PCIE_ER1BEG2_0", + "PCIE_WW4B2_4", + "PCIE_EE4A1_1", + "PCIE_LOGIC_OUTS_B20_L_3", + "PCIE_EE2BEG2_2", + "PCIE_BYP5_R_0", + "PCIE_IMUX2_L_1", + "PCIE_LOGIC_OUTS_B12_L_1", + "PCIE_LOGIC_OUTS_B9_L_0", + "PCIE_TOP_MIMRXWDATA32", + "PCIE_WR1END1_2", + "PCIE_LOGIC_OUTS_B17_R_0", + "PCIE_TOP_XILUNCONNOUT28", + "PCIE_LH10_0", + "PCIE_IMUX10_L_3", + "PCIE_LOGIC_OUTS_B8_L_0", + "PCIE_BYP1_L_3", + "PCIE_WR1END2_4", + "PCIE_IMUX14_R_4", + "PCIE_TOP_CFGDEVCONTROL2IDOCPLEN", + "PCIE_WW2END3_2", + "PCIE_IMUX3_R_2", + "PCIE_IMUX44_R_2", + "PCIE_LOGIC_OUTS_B22_R_1", + "PCIE_IMUX6_L_3", + "PCIE_EE4BEG3_0", + "PCIE_MONITOR_P_4", + "PCIE_TOP_MIMRXWDATA51", + "PCIE_CLK0_L_3", + "PCIE_IMUX40_R_3", + "PCIE_TOP_CFGPMRCVENTERL23N", + "PCIE_ER1BEG1_0", + "PCIE_IMUX44_L_0", + "PCIE_TOP_TRNRDLLPDATA57", + "PCIE_FAN2_R_1", + "PCIE_WW4A3_3", + "PCIE_NW4A3_3", + "PCIE_LOGIC_OUTS_B12_R_3", + "PCIE_NW2A0_4", + "PCIE_MONITOR_N_2", + "PCIE_TOP_PIPERX0DATA3", + "PCIE_LOGIC_OUTS_B3_R_0", + "PCIE_BLOCK_OUTS_B2_R_0", + "PCIE_SE2A2_2", + "PCIE_TOP_CFGDSN61", + "PCIE_NE4BEG0_0", + "PCIE_LOGIC_OUTS_B6_L_1", + "PCIE_IMUX31_L_1", + "PCIE_SE4BEG2_0", + "PCIE_IMUX34_L_0", + "PCIE_IMUX42_L_4", + "PCIE_WW2END1_2", + "PCIE_TOP_PIPETXMARGIN0", + "PCIE_IMUX20_R_0", + "PCIE_TOP_TRNTDLLPDATA29", + "PCIE_CTRL0_L_2", + "PCIE_TOP_DRPDO6", + "PCIE_WW4A2_0", + "PCIE_TOP_TRNTD20", + "PCIE_LOGIC_OUTS_B5_L_3", + "PCIE_SE4BEG2_4", + "PCIE_SW4A0_4", + "PCIE_NE4C2_2", + "PCIE_WW2A2_0", + "PCIE_EE4C2_2", + "PCIE_NE4BEG1_3", + "PCIE_IMUX32_R_4", + "PCIE_IMUX23_R_1", + "PCIE_TOP_TRNRDLLPDATA37", + "PCIE_IMUX39_R_0", + "PCIE_TOP_MIMRXWDATA20", + "PCIE_TOP_CFGTRANSACTIONADDR6", + "PCIE_TOP_CFGPMCSRPOWERSTATE0", + "PCIE_IMUX41_L_1", + "PCIE_WW2A1_3", + "PCIE_WR1END3_0", + "PCIE_LOGIC_OUTS_B5_L_2", + "PCIE_IMUX39_L_2", + "PCIE_IMUX4_L_3", + "PCIE_SW2A1_2", + "PCIE_NW2A3_0", + "PCIE_EE4BEG1_4", + "PCIE_WR1END0_0", + "PCIE_WW2A0_3", + "PCIE_WW4END3_2", + "PCIE_BYP2_R_0", + "PCIE_TOP_TRNRD81", + "PCIE_CTRL0_L_4", + "PCIE_EE2BEG1_2", + "PCIE_SE2A1_2", + "PCIE_IMUX34_L_4", + "PCIE_IMUX7_R_4", + "PCIE_LOGIC_OUTS_B12_R_2", + "PCIE_TOP_DBGVECA1", + "PCIE_IMUX3_R_1", + "PCIE_IMUX15_R_3", + "PCIE_BLOCK_OUTS_B1_L_2", + "PCIE_LOGIC_OUTS_B23_L_0", + "PCIE_IMUX38_R_0", + "PCIE_TOP_TRNRDLLPDATA61", + "PCIE_FAN0_R_3", + "PCIE_SW4A3_0", + "PCIE_LOGIC_OUTS_B4_R_2", + "PCIE_IMUX35_L_1", + "PCIE_MONITOR_N_1", + "PCIE_SE4C1_3", + "PCIE_IMUX46_L_3", + "PCIE_WW4C0_1", + "PCIE_IMUX15_R_0", + "PCIE_IMUX2_L_2", + "PCIE_IMUX28_L_4", + "PCIE_WW2A0_2", + "PCIE_TOP_TRNTDLLPDATA24", + "PCIE_IMUX13_R_0", + "PCIE_EL1BEG2_0", + "PCIE_WL1END3_2", + "PCIE_SW2A3_2", + "PCIE_TOP_MIMRXWDATA17", + "PCIE_TOP_TRNRDLLPDATA48", + "PCIE_IMUX39_R_2", + "PCIE_TOP_MIMRXWDATA6", + "PCIE_LH8_4", + "PCIE_IMUX24_L_1", + "PCIE_IMUX36_R_4", + "PCIE_BYP7_R_1", + "PCIE_TOP_DBGVECA13", + "PCIE_LOGIC_OUTS_B10_R_1", + "PCIE_WW4A3_2", + "PCIE_IMUX27_R_0", + "PCIE_EE4A0_3", + "PCIE_TOP_CFGTRANSACTIONADDR3", + "PCIE_IMUX18_L_0", + "PCIE_SE4C2_2", + "PCIE_TOP_EDTCONFIGURATION", + "PCIE_IMUX44_R_1", + "PCIE_TOP_CFGPCIELINKSTATE1", + "PCIE_LH4_2", + "PCIE_LH1_3", + "PCIE_TOP_DBGVECA18", + "PCIE_EE4B1_1", + "PCIE_IMUX32_L_4", + "PCIE_LOGIC_OUTS_B0_L_2", + "PCIE_LOGIC_OUTS_B12_L_4", + "PCIE_TOP_TRNTDLLPDATA28", + "PCIE_BLOCK_OUTS_B3_L_0", + "PCIE_NE2A1_0", + "PCIE_TOP_DRPDI13", + "PCIE_TOP_DRPDI7", + "PCIE_BLOCK_OUTS_B0_L_3", + "PCIE_BYP4_R_4", + "PCIE_TOP_TRNTD19", + "PCIE_IMUX16_L_2", + "PCIE_TOP_TRNTD22", + "PCIE_WW4END2_3", + "PCIE_TOP_DRPDI14", + "PCIE_TOP_CFGPMCSRPMEEN", + "PCIE_TOP_TRNRDLLPDATA60", + "PCIE_LOGIC_OUTS_B11_R_3", + "PCIE_WW2END1_4", + "PCIE_SE4C2_4", + "PCIE_CLK0_R_2", + "PCIE_LOGIC_OUTS_B14_R_3", + "PCIE_IMUX1_L_2", + "PCIE_BYP2_R_4", + "PCIE_IMUX44_L_3", + "PCIE_NE2A1_2", + "PCIE_WW2END2_4", + "PCIE_LOGIC_OUTS_B16_R_3", + "PCIE_IMUX46_R_4", + "PCIE_IMUX42_R_4", + "PCIE_ER1BEG3_3", + "PCIE_IMUX12_R_1", + "PCIE_TOP_TRNTD28", + "PCIE_IMUX26_R_3", + "PCIE_BYP0_R_0", + "PCIE_SE4BEG1_3", + "PCIE_CLK1_R_2", + "PCIE_TOP_DRPDI8", + "PCIE_WW2END3_1", + "PCIE_IMUX42_L_3", + "PCIE_TOP_CFGERRAERHEADERLOG0", + "PCIE_FAN5_R_4", + "PCIE_LOGIC_OUTS_B17_R_4", + "PCIE_SW4END1_4", + "PCIE_IMUX28_L_1", + "PCIE_SE2A0_2", + "PCIE_EL1BEG3_4", + "PCIE_IMUX27_L_3", + "PCIE_IMUX20_R_3", + "PCIE_WW2END3_4", + "PCIE_TOP_CFGERRTLPCPLHEADER33", + "PCIE_EE4B1_4", + "PCIE_IMUX29_L_3", + "PCIE_WW2A2_2", + "PCIE_TOP_TRNTDLLPDATA30", + "PCIE_WW4C0_2", + "PCIE_TOP_TRNTD36", + "PCIE_LOGIC_OUTS_B3_L_0", + "PCIE_LOGIC_OUTS_B7_L_0", + "PCIE_TOP_DRPDI1", + "PCIE_EE4B3_0", + "PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED", + "PCIE_TOP_TRNRDLLPDATA55", + "PCIE_SE2A2_4", + "PCIE_IMUX44_R_4", + "PCIE_TOP_SCANENABLEN", + "PCIE_IMUX11_R_2", + "PCIE_EE4BEG2_1", + "PCIE_WW4A1_2", + "PCIE_EE4B2_1", + "PCIE_IMUX26_R_1", + "PCIE_IMUX40_L_2", + "PCIE_TOP_TRNTD33", + "PCIE_LOGIC_OUTS_B4_R_3", + "PCIE_BLOCK_OUTS_B2_R_3", + "PCIE_EE4BEG1_0", + "PCIE_TOP_TRNTD21", + "PCIE_TOP_MIMRXWDATA15", + "PCIE_EE4C3_3", + "PCIE_IMUX16_R_0", + "PCIE_LOGIC_OUTS_B18_L_1", + "PCIE_BLOCK_OUTS_B2_L_2", + "PCIE_SE2A3_0", + "PCIE_LOGIC_OUTS_B17_L_4", + "PCIE_FAN3_L_2", + "PCIE_WW4C3_0", + "PCIE_NE4BEG3_0", + "PCIE_WW4B2_3", + "PCIE_SW2A3_1", + "PCIE_FAN0_R_1", + "PCIE_NW4END1_1", + "PCIE_SW2A0_2", + "PCIE_FAN2_L_3", + "PCIE_TOP_TRNTD37", + "PCIE_TOP_DRPADDR7", + "PCIE_BYP0_L_0", + "PCIE_WW2END1_3", + "PCIE_EE2A3_2", + "PCIE_WW2A3_3", + "PCIE_EL1BEG1_3", + "PCIE_TOP_MIMRXRDATA33", + "PCIE_WL1END1_2", + "PCIE_TOP_MIMRXRDATA36", + "PCIE_CTRL0_R_2", + "PCIE_FAN4_R_4", + "PCIE_LOGIC_OUTS_B19_L_2", + "PCIE_IMUX47_R_0", + "PCIE_IMUX7_R_2", + "PCIE_LOGIC_OUTS_B13_L_1", + "PCIE_EE2BEG3_4", + "PCIE_NE4C0_3", + "PCIE_WL1END0_2", + "PCIE_IMUX41_R_4", + "PCIE_TOP_TRNTD11", + "PCIE_IMUX7_R_0", + "PCIE_TOP_TRNTD35", + "PCIE_TOP_DRPDO5", + "PCIE_TOP_CFGERRAERHEADERLOG11", + "PCIE_EE4C1_3", + "PCIE_NE2A2_1", + "PCIE_TOP_TRNTDSTRDY3", + "PCIE_IMUX27_R_2", + "PCIE_TOP_MIMRXRDATA49", + "PCIE_EE4B0_2", + "PCIE_WL1END0_1", + "PCIE_IMUX24_R_0", + "PCIE_NW2A1_2", + "PCIE_LOGIC_OUTS_B8_R_0", + "PCIE_LH7_3", + "PCIE_SE2A1_0", + "PCIE_TOP_MIMRXWDATA28", + "PCIE_IMUX0_L_3", + "PCIE_LOGIC_OUTS_B19_R_0", + "PCIE_IMUX1_R_2", + "PCIE_LH6_4", + "PCIE_EE2A1_2", + "PCIE_WW4A0_4", + "PCIE_WW4END3_3", + "PCIE_EE4A2_2", + "PCIE_LH9_4", + "PCIE_FAN4_L_2", + "PCIE_LOGIC_OUTS_B18_L_2", + "PCIE_BYP3_R_1", + "PCIE_TOP_MIMRXRADDR0", + "PCIE_FAN5_L_1", + "PCIE_EE4B2_4", + "PCIE_TOP_TRNRD97", + "PCIE_LH9_0", + "PCIE_TOP_TRNRDLLPDATA43", + "PCIE_WW2A1_4", + "PCIE_IMUX37_L_0", + "PCIE_SE4BEG3_4", + "PCIE_LOGIC_OUTS_B18_L_4", + "PCIE_NE4BEG3_2", + "PCIE_LOGIC_OUTS_B22_R_0", + "PCIE_LH8_0", + "PCIE_FAN0_L_1", + "PCIE_LOGIC_OUTS_B9_R_2", + "PCIE_BLOCK_OUTS_B0_R_4", + "PCIE_TOP_CFGERRAERHEADERLOG10", + "PCIE_IMUX5_R_3", + "PCIE_SW2A3_3", + "PCIE_IMUX3_L_0", + "PCIE_NE2A1_3", + "PCIE_IMUX33_R_0", + "PCIE_NE4BEG0_3", + "PCIE_NW4A2_0", + "PCIE_TOP_CFGDEVID4", + "PCIE_IMUX5_R_0", + "PCIE_LH9_3", + "PCIE_EL1BEG2_1", + "PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK", + "PCIE_LH2_1", + "PCIE_WW4END1_1", + "PCIE_EL1BEG1_0", + "PCIE_LOGIC_OUTS_B1_R_3", + "PCIE_TOP_TRNRD72", + "PCIE_IMUX32_R_0", + "PCIE_IMUX12_L_0", + "PCIE_TOP_TRNRDLLPSRCRDY0", + "PCIE_IMUX45_L_1", + "PCIE_IMUX31_L_0", + "PCIE_TOP_CFGERRTLPCPLHEADER29", + "PCIE_IMUX47_L_1", + "PCIE_TOP_MIMRXWDATA7", + "PCIE_IMUX46_L_1", + "PCIE_TOP_DRPDI9", + "PCIE_NW4A3_2", + "PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK", + "PCIE_TOP_MIMRXRDATA30", + "PCIE_SE2A1_3", + "PCIE_LOGIC_OUTS_B20_L_4", + "PCIE_FAN3_L_1", + "PCIE_LOGIC_OUTS_B22_R_2", + "PCIE_FAN1_R_4", + "PCIE_IMUX5_L_4", + "PCIE_WW2END1_0", + "PCIE_TOP_CFGVCTCVCMAP5", + "PCIE_CTRL0_L_1", + "PCIE_TOP_CFGERRTLPCPLHEADER28", + "PCIE_LH10_3", + "PCIE_TOP_TRNRD68", + "PCIE_IMUX31_L_2", + "PCIE_LOGIC_OUTS_B22_L_2", + "PCIE_TOP_MIMRXWDATA0", + "PCIE_IMUX18_L_3", + "PCIE_TOP_TRNTD32", + "PCIE_SW4A3_3", + "PCIE_EE4BEG3_4", + "PCIE_TOP_CFGTRANSACTIONADDR4", + "PCIE_ER1BEG0_4", + "PCIE_LOGIC_OUTS_B8_R_2", + "PCIE_WW4END3_0", + "PCIE_WW4B3_0", + "PCIE_LOGIC_OUTS_B11_L_3", + "PCIE_WW4B2_0", + "PCIE_NW2A1_0", + "PCIE_EE4BEG2_2", + "PCIE_TOP_MIMRXRDATA21", + "PCIE_NW4A0_3", + "PCIE_LOGIC_OUTS_B10_R_3", + "PCIE_WR1END1_0", + "PCIE_IMUX43_L_4", + "PCIE_LOGIC_OUTS_B16_L_3", + "PCIE_BYP3_L_0", + "PCIE_TOP_CFGDEVID0", + "PCIE_TOP_CFGERRTLPCPLHEADER26", + "PCIE_SE4C2_1", + "PCIE_TOP_DBGVECA3", + "PCIE_TOP_MIMRXRDATA35", + "PCIE_TOP_PIPERX4DATA5", + "PCIE_NW4A0_4", + "PCIE_IMUX21_R_3", + "PCIE_IMUX31_R_4", + "PCIE_LOGIC_OUTS_B2_L_2", + "PCIE_TOP_TRNTDLLPDATA25", + "PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN", + "PCIE_CTRL0_R_3", + "PCIE_LH1_0", + "PCIE_LOGIC_OUTS_B1_R_0", + "PCIE_WW4B0_2", + "PCIE_LOGIC_OUTS_B22_L_4", + "PCIE_EE4A3_3", + "PCIE_TOP_TRNRDLLPDATA52", + "PCIE_TOP_DBGVECA19", + "PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS", + "PCIE_LOGIC_OUTS_B5_R_2", + "PCIE_IMUX47_R_1", + "PCIE_NE2A3_2", + "PCIE_FAN6_L_2", + "PCIE_IMUX3_L_3", + "PCIE_EE4A2_4", + "PCIE_CLK0_L_1", + "PCIE_NW4A3_4", + "PCIE_TOP_CFGERRTLPCPLHEADER39", + "PCIE_WW4A2_2", + "PCIE_IMUX22_R_1", + "PCIE_EE2A3_4", + "PCIE_TOP_DBGVECA4", + "PCIE_LOGIC_OUTS_B15_L_3", + "PCIE_TOP_TRNRD61", + "PCIE_LOGIC_OUTS_B23_L_4", + "PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC", + "PCIE_TOP_CFGVCTCVCMAP2", + "PCIE_FAN0_L_4", + "PCIE_TOP_TRNTD41", + "PCIE_IMUX43_L_0", + "PCIE_IMUX43_R_0", + "PCIE_IMUX2_L_4", + "PCIE_IMUX8_L_4", + "PCIE_IMUX24_L_3", + "PCIE_FAN2_L_0", + "PCIE_NW2A2_3", + "PCIE_LH6_1", + "PCIE_TOP_MIMRXWDATA5", + "PCIE_IMUX9_L_0", + "PCIE_TOP_PIPERX0DATA0", + "PCIE_TOP_PIPERX0VALID", + "PCIE_TOP_PIPERX0DATA7", + "PCIE_IMUX14_R_0", + "PCIE_BLOCK_OUTS_B2_L_3", + "PCIE_LOGIC_OUTS_B16_R_1", + "PCIE_CLK1_L_2", + "PCIE_IMUX33_L_1", + "PCIE_IMUX28_R_0", + "PCIE_IMUX32_R_3", + "PCIE_TOP_MIMRXWDATA33", + "PCIE_SW4END0_0", + "PCIE_TOP_CFGDEVID8", + "PCIE_TOP_MIMRXWDATA31", + "PCIE_IMUX23_R_2", + "PCIE_CTRL0_R_0", + "PCIE_TOP_DBGVECA12", + "PCIE_FAN7_R_3", + "PCIE_TOP_CFGVENDID0", + "PCIE_WL1END0_4", + "PCIE_IMUX5_L_3", + "PCIE_WW4C2_3", + "PCIE_CTRL0_R_4", + "PCIE_LOGIC_OUTS_B8_L_1", + "PCIE_IMUX17_L_1", + "PCIE_IMUX17_L_0", + "PCIE_IMUX18_R_2", + "PCIE_EE4BEG1_3", + "PCIE_LOGIC_OUTS_B12_R_0", + "PCIE_WW4C1_3", + "PCIE_LOGIC_OUTS_B7_L_1", + "PCIE_IMUX19_R_0", + "PCIE_FAN6_L_4", + "PCIE_EE2A2_4", + "PCIE_IMUX46_R_1", + "PCIE_IMUX14_L_2", + "PCIE_LOGIC_OUTS_B9_R_1", + "PCIE_TOP_LL2SENDENTERL1", + "PCIE_LOGIC_OUTS_B2_R_1", + "PCIE_IMUX26_L_0", + "PCIE_WW2A3_2", + "PCIE_IMUX29_R_2", + "PCIE_EE4B2_3", + "PCIE_IMUX8_L_2", + "PCIE_BYP1_R_4", + "PCIE_NW2A2_0", + "PCIE_IMUX8_L_3", + "PCIE_IMUX37_L_2", + "PCIE_TOP_CFGERRTLPCPLHEADER31", + "PCIE_TOP_CFGMGMTDO18", + "PCIE_IMUX37_R_2", + "PCIE_EE4B0_0", + "PCIE_IMUX25_R_0", + "PCIE_LOGIC_OUTS_B23_R_2", + "PCIE_BYP1_L_0", + "PCIE_WW2END0_4", + "PCIE_EE4C1_2", + "PCIE_LOGIC_OUTS_B1_R_2", + "PCIE_WW4C2_0", + "PCIE_TOP_CFGMGMTDO30", + "PCIE_IMUX40_L_4", + "PCIE_FAN7_L_4", + "PCIE_BLOCK_OUTS_B0_R_2", + "PCIE_TOP_CFGDSN62", + "PCIE_TOP_CFGCOMMANDMEMENABLE", + "PCIE_SE2A3_2", + "PCIE_NE4C3_1", + "PCIE_TOP_MIMRXRADDR8", + "PCIE_IMUX35_L_2", + "PCIE_TOP_PIPERX4VALID", + "PCIE_IMUX5_R_4", + "PCIE_TOP_MIMRXWDATA23", + "PCIE_LOGIC_OUTS_B3_L_4", + "PCIE_WL1END1_0", + "PCIE_LH12_1", + "PCIE_NW4END0_3", + "PCIE_IMUX28_L_0", + "PCIE_TOP_MIMRXWDATA24", + "PCIE_SW4END0_4", + "PCIE_TOP_TRNRD74", + "PCIE_WW4END1_0", + "PCIE_LOGIC_OUTS_B9_R_3", + "PCIE_SE4BEG0_3", + "PCIE_TOP_DRPDI2", + "PCIE_MONITOR_P_2", + "PCIE_LOGIC_OUTS_B5_L_4", + "PCIE_TOP_DRPDO15", + "PCIE_IMUX32_L_0", + "PCIE_NW2A0_0", + "PCIE_IMUX36_L_0", + "PCIE_IMUX7_L_4", + "PCIE_LOGIC_OUTS_B20_R_1", + "PCIE_WW4END2_2", + "PCIE_IMUX6_L_1", + "PCIE_WW4A1_3", + "PCIE_NE4C1_0", + "PCIE_LH2_3", + "PCIE_LOGIC_OUTS_B2_R_0", + "PCIE_TOP_MIMRXRDATA26", + "PCIE_LOGIC_OUTS_B2_R_2", + "PCIE_IMUX39_R_1", + "PCIE_FAN4_L_0", + "PCIE_IMUX40_R_2", + "PCIE_WW4A3_1", + "PCIE_LOGIC_OUTS_B16_R_0", + "PCIE_IMUX34_R_3", + "PCIE_IMUX34_L_1", + "PCIE_LOGIC_OUTS_B6_R_3", + "PCIE_BLOCK_OUTS_B3_L_4", + "PCIE_SE4BEG3_0", + "PCIE_TOP_TRNRDLLPDATA34", + "PCIE_IMUX26_L_3", + "PCIE_WW4A0_2", + "PCIE_LOGIC_OUTS_B17_R_1", + "PCIE_WL1END2_3", + "PCIE_BLOCK_OUTS_B0_R_1", + "PCIE_BLOCK_OUTS_B3_R_4", + "PCIE_TOP_PIPERX4DATA1", + "PCIE_SW4END2_1", + "PCIE_IMUX16_L_1", + "PCIE_WW2END1_1", + "PCIE_IMUX16_R_1", + "PCIE_FAN6_R_4", + "PCIE_BYP4_R_2", + "PCIE_LOGIC_OUTS_B0_R_2", + "PCIE_EE4C0_2", + "PCIE_FAN2_L_2", + "PCIE_LOGIC_OUTS_B14_L_1", + "PCIE_TOP_PIPERX4DATA4", + "PCIE_IMUX5_L_0", + "PCIE_LOGIC_OUTS_B2_L_4", + "PCIE_SW4END1_2", + "PCIE_SW2A3_0", + "PCIE_TOP_TRNRD92", + "PCIE_IMUX4_R_2", + "PCIE_TOP_LL2SENDASREQL1", + "PCIE_NE4C1_3", + "PCIE_TOP_TRNTDLLPDATA22", + "PCIE_IMUX42_L_2", + "PCIE_IMUX13_L_0", + "PCIE_IMUX10_L_0", + "PCIE_WL1END3_1", + "PCIE_EE4B2_0", + "PCIE_IMUX30_R_4", + "PCIE_NW2A2_1", + "PCIE_IMUX36_R_3", + "PCIE_BLOCK_OUTS_B0_L_4", + "PCIE_NW4A1_3", + "PCIE_NW2A3_4", + "PCIE_LOGIC_OUTS_B0_L_1", + "PCIE_IMUX45_L_0", + "PCIE_LH2_4", + "PCIE_WW2A3_1", + "PCIE_ER1BEG0_3", + "PCIE_EE4B3_4", + "PCIE_SW4A2_3", + "PCIE_TOP_CFGTRANSACTIONADDR5", + "PCIE_TOP_CFGERRTLPCPLHEADER36", + "PCIE_LH11_2", + "PCIE_LH11_3", + "PCIE_IMUX11_R_3", + "PCIE_BLOCK_OUTS_B1_R_3", + "PCIE_LOGIC_OUTS_B3_R_3", + "PCIE_SE4C3_4", + "PCIE_LOGIC_OUTS_B0_R_3", + "PCIE_TOP_TRNRD89", + "PCIE_IMUX35_R_4", + "PCIE_IMUX13_L_2", + "PCIE_TOP_CFGPMCSRPOWERSTATE1", + "PCIE_LOGIC_OUTS_B12_L_2", + "PCIE_EL1BEG0_1", + "PCIE_NW4A1_2", + "PCIE_IMUX38_R_2", + "PCIE_NW4A3_1", + "PCIE_CLK0_L_4", + "PCIE_IMUX5_L_1", + "PCIE_IMUX22_L_4", + "PCIE_WW4A0_0", + "PCIE_SW4A2_0", + "PCIE_IMUX44_R_3", + "PCIE_IMUX12_L_3", + "PCIE_TOP_TRNRD86", + "PCIE_TOP_TRNRD65", + "PCIE_CTRL1_L_3", + "PCIE_IMUX4_R_1", + "PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED", + "PCIE_WL1END2_2", + "PCIE_IMUX2_R_1", + "PCIE_LOGIC_OUTS_B21_R_1", + "PCIE_TOP_MIMRXREN", + "PCIE_IMUX4_L_2", + "PCIE_CLK0_R_3", + "PCIE_IMUX47_L_2", + "PCIE_TOP_TRNTDLLPDATA20", + "PCIE_TOP_PL2SUSPENDOK", + "PCIE_FAN3_L_3", + "PCIE_LOGIC_OUTS_B7_L_2", + "PCIE_EE4BEG2_3", + "PCIE_TOP_LL2SUSPENDNOW", + "PCIE_FAN4_L_4", + "PCIE_IMUX38_R_1", + "PCIE_SE4BEG0_0", + "PCIE_FAN0_L_0", + "PCIE_TOP_CFGERRTLPCPLHEADER44", + "PCIE_IMUX35_R_3", + "PCIE_WR1END3_3", + "PCIE_SW4A2_2", + "PCIE_LOGIC_OUTS_B3_R_1", + "PCIE_WL1END3_3", + "PCIE_LOGIC_OUTS_B0_L_0", + "PCIE_LH8_3", + "PCIE_LOGIC_OUTS_B6_L_2", + "PCIE_IMUX42_R_3", + "PCIE_TOP_PIPERX0DATA4", + "PCIE_TOP_CFGERRTLPCPLHEADER37", + "PCIE_TOP_TRNRDLLPDATA42", + "PCIE_NW2A1_4", + "PCIE_TOP_TRNRDLLPDATA53", + "PCIE_EE4C2_4", + "PCIE_LOGIC_OUTS_B9_L_1", + "PCIE_LOGIC_OUTS_B4_L_2", + "PCIE_NE4BEG3_3", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS", + "PCIE_LOGIC_OUTS_B13_R_2", + "PCIE_EL1BEG0_4", + "PCIE_WW2A0_0", + "PCIE_CTRL0_L_3", + "PCIE_BYP6_L_2", + "PCIE_WW4END3_1", + "PCIE_IMUX10_L_1", + "PCIE_TOP_TRNTDLLPDATA26", + "PCIE_BYP3_R_2", + "PCIE_SE4C3_3", + "PCIE_TOP_MIMRXWADDR12", + "PCIE_NW4END1_2", + "PCIE_IMUX7_R_3", + "PCIE_LOGIC_OUTS_B16_R_4", + "PCIE_LOGIC_OUTS_B3_R_4", + "PCIE_TOP_TRNRDLLPDATA38", + "PCIE_SW2A0_1", + "PCIE_EE2BEG0_1", + "PCIE_LOGIC_OUTS_B7_R_1", + "PCIE_IMUX23_L_0", + "PCIE_IMUX24_R_1", + "PCIE_LOGIC_OUTS_B5_R_3", + "PCIE_LOGIC_OUTS_B8_R_4", + "PCIE_IMUX25_R_2", + "PCIE_IMUX35_R_1", + "PCIE_IMUX21_L_3", + "PCIE_WW2A0_4", + "PCIE_IMUX30_L_2", + "PCIE_TOP_TRNRD71", + "PCIE_TOP_DBGVECA14", + "PCIE_FAN5_L_4", + "PCIE_IMUX47_L_0", + "PCIE_IMUX8_R_0", + "PCIE_BYP6_R_2", + "PCIE_TOP_CFGERRTLPCPLHEADER32", + "PCIE_FAN7_R_0", + "PCIE_EE4B1_3", + "PCIE_IMUX36_L_1", + "PCIE_LOGIC_OUTS_B18_R_0", + "PCIE_BYP6_L_0", + "PCIE_SW4A2_1", + "PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN", + "PCIE_IMUX0_R_0", + "PCIE_IMUX18_L_1", + "PCIE_TOP_DBGVECA21", + "PCIE_TOP_CFGDEVID15", + "PCIE_EE4B0_4", + "PCIE_BYP0_R_3", + "PCIE_SE4C0_0", + "PCIE_IMUX5_L_2", + "PCIE_TOP_TRNRDLLPDATA63", + "PCIE_NW4A2_4", + "PCIE_TOP_TRNRD98", + "PCIE_NW4END3_2", + "PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN", + "PCIE_WL1END0_0", + "PCIE_SE4C1_0", + "PCIE_IMUX25_L_4", + "PCIE_LH5_1", + "PCIE_IMUX44_L_4", + "PCIE_IMUX30_R_3", + "PCIE_IMUX33_R_3", + "PCIE_EE2A2_3", + "PCIE_TOP_CFGDEVID9", + "PCIE_WL1END0_3", + "PCIE_ER1BEG1_1", + "PCIE_IMUX14_R_2", + "PCIE_LOGIC_OUTS_B3_R_2", + "PCIE_SW2A0_0", + "PCIE_TOP_MIMRXWDATA3", + "PCIE_TOP_PIPERX4CHARISK0", + "PCIE_IMUX46_L_4", + "PCIE_LH4_3", + "PCIE_TOP_MIMRXRDATA27", + "PCIE_EE4A3_4", + "PCIE_SW2A1_4", + "PCIE_IMUX29_L_0", + "PCIE_FAN7_R_1", + "PCIE_EE2BEG0_2", + "PCIE_IMUX23_L_4", + "PCIE_IMUX45_R_2", + "PCIE_WL1END1_3", + "PCIE_TOP_CFGERRTLPCPLHEADER41", + "PCIE_IMUX17_R_2", + "PCIE_FAN2_L_4", + "PCIE_NE2A0_0", + "PCIE_LOGIC_OUTS_B0_L_3", + "PCIE_IMUX14_R_3", + "PCIE_IMUX34_L_2", + "PCIE_LOGIC_OUTS_B8_L_2", + "PCIE_TOP_TRNRDLLPDATA58", + "PCIE_SW4A0_1", + "PCIE_NE4BEG2_0", + "PCIE_LOGIC_OUTS_B16_L_2", + "PCIE_TOP_TRNRDLLPDATA41", + "PCIE_CTRL0_L_0", + "PCIE_IMUX11_L_2", + "PCIE_NE4C1_1", + "PCIE_IMUX3_L_1", + "PCIE_WW2A3_0", + "PCIE_IMUX37_R_4", + "PCIE_LOGIC_OUTS_B4_L_3", + "PCIE_TOP_TRNRDLLPDATA51", + "PCIE_IMUX4_R_0", + "PCIE_FAN7_L_0", + "PCIE_TOP_CFGDEVID13", + "PCIE_NW4END2_1", + "PCIE_SW4A0_2", + "PCIE_IMUX0_L_2", + "PCIE_LOGIC_OUTS_B6_L_3", + "PCIE_TOP_PL2DIRECTEDLSTATE3", + "PCIE_WW2A1_0", + "PCIE_CLK1_R_4", + "PCIE_IMUX27_L_4", + "PCIE_IMUX7_L_2", + "PCIE_BYP2_R_3", + "PCIE_LOGIC_OUTS_B1_L_3", + "PCIE_TOP_DBGVECA15", + "PCIE_TOP_CFGMGMTDO21", + "PCIE_IMUX30_R_2", + "PCIE_WR1END1_4", + "PCIE_TOP_TRNTD8", + "PCIE_LOGIC_OUTS_B10_L_1", + "PCIE_IMUX25_L_2", + "PCIE_EE4BEG2_4", + "PCIE_BLOCK_OUTS_B3_L_1", + "PCIE_BYP6_L_1", + "PCIE_LOGIC_OUTS_B20_R_0", + "PCIE_CLK1_L_4", + "PCIE_TOP_MIMRXRDATA47", + "PCIE_TOP_PL2DIRECTEDLSTATE1", + "PCIE_EE2A2_1", + "PCIE_WW4C3_3", + "PCIE_IMUX1_R_1", + "PCIE_NW2A0_3", + "PCIE_WW4END2_4", + "PCIE_SE4BEG0_1", + "PCIE_IMUX9_L_2", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0", + "PCIE_ER1BEG0_2", + "PCIE_IMUX6_R_4", + "PCIE_LOGIC_OUTS_B23_R_0", + "PCIE_TOP_TRNTD9", + "PCIE_TOP_TRNRD88", + "PCIE_IMUX1_R_3", + "PCIE_SE4BEG2_1", + "PCIE_IMUX46_R_2", + "PCIE_LH6_2", + "PCIE_IMUX4_L_0" + ], + "pips": { + "PCIE_TOP.PCIE_IMUX13_L_2->PCIE_TOP_DRPDI5": { + "src_wire": "PCIE_IMUX13_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP0->PCIE_LOGIC_OUTS_B17_L_1": { + "src_wire": "PCIE_TOP_CFGVCTCVCMAP0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD81->PCIE_LOGIC_OUTS_B3_R_4": { + "src_wire": "PCIE_TOP_TRNRD81", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX8_R_3->PCIE_TOP_TRNTD20": { + "src_wire": "PCIE_IMUX8_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX32_R_1->PCIE_TOP_PIPERX4DATA3": { + "src_wire": "PCIE_IMUX32_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX6_L_4->PCIE_TOP_CFGERRTLPCPLHEADER44": { + "src_wire": "PCIE_IMUX6_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER44", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO23->PCIE_LOGIC_OUTS_B15_R_3": { + "src_wire": "PCIE_TOP_CFGMGMTDO23", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX13_L_3->PCIE_TOP_DRPDI9": { + "src_wire": "PCIE_IMUX13_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX3_L_2->PCIE_TOP_TRNTDLLPDATA30": { + "src_wire": "PCIE_IMUX3_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA43->PCIE_LOGIC_OUTS_B7_L_2": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA43", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED->PCIE_LOGIC_OUTS_B16_L_1": { + "src_wire": "PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD90->PCIE_LOGIC_OUTS_B6_R_2": { + "src_wire": "PCIE_TOP_TRNRD90", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWEN->PCIE_LOGIC_OUTS_B18_R_1": { + "src_wire": "PCIE_TOP_MIMRXWEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGCOMMANDIOENABLE->PCIE_LOGIC_OUTS_B11_L_4": { + "src_wire": "PCIE_TOP_CFGCOMMANDIOENABLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX8_L_3->PCIE_TOP_CFGDEVID5": { + "src_wire": "PCIE_IMUX8_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS->PCIE_LOGIC_OUTS_B15_L_1": { + "src_wire": "PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD74->PCIE_LOGIC_OUTS_B3_L_3": { + "src_wire": "PCIE_TOP_TRNRD74", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX3_R_2->PCIE_TOP_MIMRXRDATA31": { + "src_wire": "PCIE_IMUX3_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX6_L_2->PCIE_TOP_CFGERRTLPCPLHEADER36": { + "src_wire": "PCIE_IMUX6_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER36", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX14_R_2->PCIE_TOP_TRNTD34": { + "src_wire": "PCIE_IMUX14_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD34", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN->PCIE_LOGIC_OUTS_B12_L_2": { + "src_wire": "PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX14_L_4->PCIE_TOP_DRPDI14": { + "src_wire": "PCIE_IMUX14_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX12_R_1->PCIE_TOP_TRNTD36": { + "src_wire": "PCIE_IMUX12_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD36", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGPMRCVREQACKN->PCIE_LOGIC_OUTS_B9_L_1": { + "src_wire": "PCIE_TOP_CFGPMRCVREQACKN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX12_L_4->PCIE_TOP_DRPDI12": { + "src_wire": "PCIE_IMUX12_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX22_R_3->PCIE_TOP_CFGERRAERHEADERLOG4": { + "src_wire": "PCIE_IMUX22_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX5_L_4->PCIE_TOP_CFGERRTLPCPLHEADER43": { + "src_wire": "PCIE_IMUX5_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER43", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLLINKDISABLE->PCIE_LOGIC_OUTS_B15_L_0": { + "src_wire": "PCIE_TOP_CFGLINKCONTROLLINKDISABLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA19->PCIE_LOGIC_OUTS_B8_R_3": { + "src_wire": "PCIE_TOP_MIMRXWDATA19", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO20->PCIE_LOGIC_OUTS_B11_R_3": { + "src_wire": "PCIE_TOP_CFGMGMTDO20", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX21_R_4->PCIE_TOP_CFGDEVID13": { + "src_wire": "PCIE_IMUX21_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX0_R_0->PCIE_TOP_MIMRXRDATA20": { + "src_wire": "PCIE_IMUX0_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX11_L_3->PCIE_TOP_CFGDEVID8": { + "src_wire": "PCIE_IMUX11_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA5->PCIE_LOGIC_OUTS_B22_R_3": { + "src_wire": "PCIE_TOP_MIMRXWDATA5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX11_R_3->PCIE_TOP_TRNTD23": { + "src_wire": "PCIE_IMUX11_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX12_L_3->PCIE_TOP_DRPDI8": { + "src_wire": "PCIE_IMUX12_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX5_R_0->PCIE_TOP_MIMRXRDATA53": { + "src_wire": "PCIE_IMUX5_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA53", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR4->PCIE_LOGIC_OUTS_B5_R_2": { + "src_wire": "PCIE_TOP_MIMRXRADDR4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX5_L_3->PCIE_TOP_CFGERRTLPCPLHEADER39": { + "src_wire": "PCIE_IMUX5_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER39", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX35_R_0->PCIE_TOP_PIPERX4DATA6": { + "src_wire": "PCIE_IMUX35_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWADDR1->PCIE_LOGIC_OUTS_B15_R_1": { + "src_wire": "PCIE_TOP_MIMRXWADDR1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA0->PCIE_LOGIC_OUTS_B11_R_0": { + "src_wire": "PCIE_TOP_MIMRXWDATA0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX4_L_2->PCIE_TOP_CFGERRTLPCPLHEADER34": { + "src_wire": "PCIE_IMUX4_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER34", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_PLDBGVEC8->PCIE_LOGIC_OUTS_B23_L_0": { + "src_wire": "PCIE_TOP_PLDBGVEC8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWADDR5->PCIE_LOGIC_OUTS_B9_R_1": { + "src_wire": "PCIE_TOP_MIMRXWADDR5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX3_L_4->PCIE_TOP_PL2DIRECTEDLSTATE0": { + "src_wire": "PCIE_IMUX3_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK->PCIE_LOGIC_OUTS_B12_L_1": { + "src_wire": "PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD64->PCIE_LOGIC_OUTS_B1_L_1": { + "src_wire": "PCIE_TOP_TRNRD64", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX7_R_0->PCIE_TOP_MIMRXRDATA55": { + "src_wire": "PCIE_IMUX7_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA55", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWADDR2->PCIE_LOGIC_OUTS_B0_R_2": { + "src_wire": "PCIE_TOP_MIMRXWADDR2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX3_R_3->PCIE_TOP_MIMRXRDATA35": { + "src_wire": "PCIE_IMUX3_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA35", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA12->PCIE_LOGIC_OUTS_B20_R_3": { + "src_wire": "PCIE_TOP_DBGVECA12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX11_L_0->PCIE_TOP_CFGDSN60": { + "src_wire": "PCIE_IMUX11_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN60", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX12_L_2->PCIE_TOP_DRPDI4": { + "src_wire": "PCIE_IMUX12_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD86->PCIE_LOGIC_OUTS_B4_R_3": { + "src_wire": "PCIE_TOP_TRNRD86", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGPMRCVENTERL23N->PCIE_LOGIC_OUTS_B8_L_1": { + "src_wire": "PCIE_TOP_CFGPMRCVENTERL23N", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA19->PCIE_LOGIC_OUTS_B19_R_0": { + "src_wire": "PCIE_TOP_DBGVECA19", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE->PCIE_LOGIC_OUTS_B21_R_4": { + "src_wire": "PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_PIPETXMARGIN2->PCIE_LOGIC_OUTS_B6_L_0": { + "src_wire": "PCIE_TOP_PIPETXMARGIN2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA21->PCIE_LOGIC_OUTS_B19_R_3": { + "src_wire": "PCIE_TOP_MIMRXWDATA21", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA59->PCIE_LOGIC_OUTS_B9_R_3": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA59", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX33_L_0->PCIE_TOP_PIPERX0CHANISALIGNED": { + "src_wire": "PCIE_IMUX33_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0CHANISALIGNED", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX15_R_2->PCIE_TOP_TRNTD35": { + "src_wire": "PCIE_IMUX15_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD35", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX18_R_4->PCIE_TOP_CFGERRTLPCPLHEADER47": { + "src_wire": "PCIE_IMUX18_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER47", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX5_R_2->PCIE_TOP_MIMRXRDATA45": { + "src_wire": "PCIE_IMUX5_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA45", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA51->PCIE_LOGIC_OUTS_B7_R_1": { + "src_wire": "PCIE_TOP_MIMRXWDATA51", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA52->PCIE_LOGIC_OUTS_B5_R_4": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA52", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX35_L_0->PCIE_TOP_PIPERX0DATA6": { + "src_wire": "PCIE_IMUX35_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX13_L_0->PCIE_TOP_DRPADDR8": { + "src_wire": "PCIE_IMUX13_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPADDR8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX12_R_3->PCIE_TOP_TRNTD28": { + "src_wire": "PCIE_IMUX12_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX10_L_3->PCIE_TOP_CFGDEVID7": { + "src_wire": "PCIE_IMUX10_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX7_L_3->PCIE_TOP_CFGERRTLPCPLHEADER41": { + "src_wire": "PCIE_IMUX7_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER41", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX12_L_0->PCIE_TOP_DRPADDR7": { + "src_wire": "PCIE_IMUX12_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPADDR7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX17_R_3->PCIE_TOP_TL2PPMSUSPENDREQ": { + "src_wire": "PCIE_IMUX17_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TL2PPMSUSPENDREQ", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD83->PCIE_LOGIC_OUTS_B0_R_3": { + "src_wire": "PCIE_TOP_TRNRD83", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX16_R_1->PCIE_TOP_PIPERX4CHARISK0": { + "src_wire": "PCIE_IMUX16_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4CHARISK0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX1_R_4->PCIE_TOP_MIMRXRDATA37": { + "src_wire": "PCIE_IMUX1_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA37", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA49->PCIE_LOGIC_OUTS_B5_R_1": { + "src_wire": "PCIE_TOP_MIMRXWDATA49", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX15_L_4->PCIE_TOP_DRPDI15": { + "src_wire": "PCIE_IMUX15_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DRPDO3->PCIE_LOGIC_OUTS_B16_L_4": { + "src_wire": "PCIE_TOP_DRPDO3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN->PCIE_LOGIC_OUTS_B15_L_3": { + "src_wire": "PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD77->PCIE_LOGIC_OUTS_B2_L_4": { + "src_wire": "PCIE_TOP_TRNRD77", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD66->PCIE_LOGIC_OUTS_B3_L_1": { + "src_wire": "PCIE_TOP_TRNRD66", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_PL2RECOVERY->PCIE_LOGIC_OUTS_B12_R_0": { + "src_wire": "PCIE_TOP_PL2RECOVERY", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD93->PCIE_LOGIC_OUTS_B4_R_1": { + "src_wire": "PCIE_TOP_TRNRD93", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX34_R_0->PCIE_TOP_PIPERX4DATA7": { + "src_wire": "PCIE_IMUX34_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP1->PCIE_LOGIC_OUTS_B18_L_1": { + "src_wire": "PCIE_TOP_CFGVCTCVCMAP1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA29->PCIE_LOGIC_OUTS_B8_R_4": { + "src_wire": "PCIE_TOP_MIMRXWDATA29", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX4_R_3->PCIE_TOP_MIMRXRDATA40": { + "src_wire": "PCIE_IMUX4_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA40", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX7_R_2->PCIE_TOP_MIMRXRDATA47": { + "src_wire": "PCIE_IMUX7_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA47", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA32->PCIE_LOGIC_OUTS_B1_R_2": { + "src_wire": "PCIE_TOP_MIMRXWDATA32", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX9_R_0->PCIE_TOP_TRNTD9": { + "src_wire": "PCIE_IMUX9_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX5_R_4->PCIE_TOP_TRNTD25": { + "src_wire": "PCIE_IMUX5_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA62->PCIE_LOGIC_OUTS_B10_R_2": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA62", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX4_R_2->PCIE_TOP_MIMRXRDATA44": { + "src_wire": "PCIE_IMUX4_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA44", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX6_L_3->PCIE_TOP_CFGERRTLPCPLHEADER40": { + "src_wire": "PCIE_IMUX6_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER40", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0->PCIE_LOGIC_OUTS_B14_L_2": { + "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN->PCIE_LOGIC_OUTS_B12_L_4": { + "src_wire": "PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX23_R_3->PCIE_TOP_CFGERRAERHEADERLOG5": { + "src_wire": "PCIE_IMUX23_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX17_R_4->PCIE_TOP_CFGERRTLPCPLHEADER46": { + "src_wire": "PCIE_IMUX17_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER46", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA6->PCIE_LOGIC_OUTS_B23_L_3": { + "src_wire": "PCIE_TOP_DBGVECA6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX37_R_0->PCIE_TOP_PIPERX4PHYSTATUS": { + "src_wire": "PCIE_IMUX37_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4PHYSTATUS", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX18_R_3->PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK": { + "src_wire": "PCIE_IMUX18_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX36_R_0->PCIE_TOP_PIPERX4VALID": { + "src_wire": "PCIE_IMUX36_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4VALID", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA11->PCIE_LOGIC_OUTS_B22_R_4": { + "src_wire": "PCIE_TOP_DBGVECA11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1->PCIE_LOGIC_OUTS_B15_L_2": { + "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLASPMCONTROL1->PCIE_LOGIC_OUTS_B13_L_0": { + "src_wire": "PCIE_TOP_CFGLINKCONTROLASPMCONTROL1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_PIPETXMARGIN0->PCIE_LOGIC_OUTS_B18_L_0": { + "src_wire": "PCIE_TOP_PIPETXMARGIN0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX15_R_3->PCIE_TOP_TRNTD31": { + "src_wire": "PCIE_IMUX15_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX0_L_4->PCIE_TOP_LL2SENDENTERL23": { + "src_wire": "PCIE_IMUX0_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_LL2SENDENTERL23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR11->PCIE_LOGIC_OUTS_B10_R_0": { + "src_wire": "PCIE_TOP_MIMRXRADDR11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX2_L_2->PCIE_TOP_TRNTDLLPDATA29": { + "src_wire": "PCIE_IMUX2_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX11_L_4->PCIE_TOP_CFGDEVID12": { + "src_wire": "PCIE_IMUX11_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA39->PCIE_LOGIC_OUTS_B7_L_1": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA39", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX14_R_4->PCIE_TOP_CFGERRAERHEADERLOG7": { + "src_wire": "PCIE_IMUX14_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX20_R_2->PCIE_TOP_CFGERRAERHEADERLOG1": { + "src_wire": "PCIE_IMUX20_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO27->PCIE_LOGIC_OUTS_B16_R_4": { + "src_wire": "PCIE_TOP_CFGMGMTDO27", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX0_L_1->PCIE_TOP_TRNTDLLPDATA23": { + "src_wire": "PCIE_IMUX0_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX3_L_1->PCIE_TOP_TRNTDLLPDATA26": { + "src_wire": "PCIE_IMUX3_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO30->PCIE_LOGIC_OUTS_B18_R_3": { + "src_wire": "PCIE_TOP_CFGMGMTDO30", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX10_R_2->PCIE_TOP_TRNTD18": { + "src_wire": "PCIE_IMUX10_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD18", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA23->PCIE_LOGIC_OUTS_B14_R_3": { + "src_wire": "PCIE_TOP_MIMRXWDATA23", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA34->PCIE_LOGIC_OUTS_B17_R_1": { + "src_wire": "PCIE_TOP_MIMRXWDATA34", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD73->PCIE_LOGIC_OUTS_B2_L_3": { + "src_wire": "PCIE_TOP_TRNRD73", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX7_R_4->PCIE_TOP_TRNTD27": { + "src_wire": "PCIE_IMUX7_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD27", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA8->PCIE_LOGIC_OUTS_B21_L_4": { + "src_wire": "PCIE_TOP_DBGVECA8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA25->PCIE_LOGIC_OUTS_B10_R_3": { + "src_wire": "PCIE_TOP_MIMRXWDATA25", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD70->PCIE_LOGIC_OUTS_B3_L_2": { + "src_wire": "PCIE_TOP_TRNRD70", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO16->PCIE_LOGIC_OUTS_B21_R_1": { + "src_wire": "PCIE_TOP_CFGMGMTDO16", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX9_L_4->PCIE_TOP_CFGDEVID10": { + "src_wire": "PCIE_IMUX9_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECB10->PCIE_LOGIC_OUTS_B22_R_0": { + "src_wire": "PCIE_TOP_DBGVECB10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA9->PCIE_LOGIC_OUTS_B22_L_4": { + "src_wire": "PCIE_TOP_DBGVECA9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX36_L_0->PCIE_TOP_PIPERX0VALID": { + "src_wire": "PCIE_IMUX36_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0VALID", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B19_L_0": { + "src_wire": "PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA55->PCIE_LOGIC_OUTS_B12_R_4": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA55", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGPCIELINKSTATE1->PCIE_LOGIC_OUTS_B9_L_0": { + "src_wire": "PCIE_TOP_CFGPCIELINKSTATE1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA50->PCIE_LOGIC_OUTS_B6_L_4": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA50", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX3_R_1->PCIE_TOP_MIMRXRDATA27": { + "src_wire": "PCIE_IMUX3_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA27", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA30->PCIE_LOGIC_OUTS_B18_R_2": { + "src_wire": "PCIE_TOP_MIMRXWDATA30", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX0_L_0->PCIE_TOP_TRNTDLLPDATA19": { + "src_wire": "PCIE_IMUX0_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA40->PCIE_LOGIC_OUTS_B4_L_2": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA40", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA36->PCIE_LOGIC_OUTS_B4_L_1": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA36", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX21_R_2->PCIE_TOP_CFGERRAERHEADERLOG11": { + "src_wire": "PCIE_IMUX21_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA45->PCIE_LOGIC_OUTS_B5_L_3": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA45", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA47->PCIE_LOGIC_OUTS_B7_L_3": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA47", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX4_L_3->PCIE_TOP_CFGERRTLPCPLHEADER38": { + "src_wire": "PCIE_IMUX4_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER38", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX33_L_1->PCIE_TOP_PIPERX0DATA2": { + "src_wire": "PCIE_IMUX33_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD95->PCIE_LOGIC_OUTS_B2_R_0": { + "src_wire": "PCIE_TOP_TRNRD95", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP2->PCIE_LOGIC_OUTS_B19_L_1": { + "src_wire": "PCIE_TOP_CFGVCTCVCMAP2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX39_R_0->PCIE_TOP_PIPERX4DATA4": { + "src_wire": "PCIE_IMUX39_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA2->PCIE_LOGIC_OUTS_B23_L_2": { + "src_wire": "PCIE_TOP_DBGVECA2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR3->PCIE_LOGIC_OUTS_B11_L_3": { + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA22->PCIE_LOGIC_OUTS_B15_R_0": { + "src_wire": "PCIE_TOP_MIMRXWDATA22", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX11_R_1->PCIE_TOP_TRNTD15": { + "src_wire": "PCIE_IMUX11_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR10->PCIE_LOGIC_OUTS_B3_R_0": { + "src_wire": "PCIE_TOP_MIMRXRADDR10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA1->PCIE_LOGIC_OUTS_B22_L_2": { + "src_wire": "PCIE_TOP_DBGVECA1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD87->PCIE_LOGIC_OUTS_B2_R_2": { + "src_wire": "PCIE_TOP_TRNRD87", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA4->PCIE_LOGIC_OUTS_B21_L_3": { + "src_wire": "PCIE_TOP_DBGVECA4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX14_R_1->PCIE_TOP_TRNTD38": { + "src_wire": "PCIE_IMUX14_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD38", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX12_L_1->PCIE_TOP_DRPDI0": { + "src_wire": "PCIE_IMUX12_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DRPDO5->PCIE_LOGIC_OUTS_B18_L_4": { + "src_wire": "PCIE_TOP_DRPDO5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR9->PCIE_LOGIC_OUTS_B8_R_0": { + "src_wire": "PCIE_TOP_MIMRXRADDR9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX2_R_4->PCIE_TOP_MIMRXRDATA38": { + "src_wire": "PCIE_IMUX2_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA38", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX11_L_1->PCIE_TOP_CFGDEVID0": { + "src_wire": "PCIE_IMUX11_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA38->PCIE_LOGIC_OUTS_B6_L_1": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA38", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA4->PCIE_LOGIC_OUTS_B9_R_0": { + "src_wire": "PCIE_TOP_MIMRXWDATA4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO21->PCIE_LOGIC_OUTS_B12_R_3": { + "src_wire": "PCIE_TOP_CFGMGMTDO21", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA3->PCIE_LOGIC_OUTS_B20_L_3": { + "src_wire": "PCIE_TOP_DBGVECA3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX2_R_1->PCIE_TOP_MIMRXRDATA26": { + "src_wire": "PCIE_IMUX2_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX13_R_1->PCIE_TOP_TRNTD37": { + "src_wire": "PCIE_IMUX13_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD37", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA13->PCIE_LOGIC_OUTS_B9_R_4": { + "src_wire": "PCIE_TOP_MIMRXWDATA13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA27->PCIE_LOGIC_OUTS_B19_R_4": { + "src_wire": "PCIE_TOP_MIMRXWDATA27", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX13_R_0->PCIE_TOP_TRNTD41": { + "src_wire": "PCIE_IMUX13_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD41", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX13_L_4->PCIE_TOP_DRPDI13": { + "src_wire": "PCIE_IMUX13_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA5->PCIE_LOGIC_OUTS_B22_L_3": { + "src_wire": "PCIE_TOP_DBGVECA5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD69->PCIE_LOGIC_OUTS_B2_L_2": { + "src_wire": "PCIE_TOP_TRNRD69", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX13_L_1->PCIE_TOP_DRPDI1": { + "src_wire": "PCIE_IMUX13_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX1_L_1->PCIE_TOP_TRNTDLLPDATA24": { + "src_wire": "PCIE_IMUX1_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONTYPE->PCIE_LOGIC_OUTS_B11_L_2": { + "src_wire": "PCIE_TOP_CFGTRANSACTIONTYPE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX10_R_0->PCIE_TOP_TRNTD10": { + "src_wire": "PCIE_IMUX10_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA13->PCIE_LOGIC_OUTS_B21_R_3": { + "src_wire": "PCIE_TOP_DBGVECA13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA15->PCIE_LOGIC_OUTS_B23_R_2": { + "src_wire": "PCIE_TOP_DBGVECA15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA14->PCIE_LOGIC_OUTS_B20_R_2": { + "src_wire": "PCIE_TOP_DBGVECA14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO22->PCIE_LOGIC_OUTS_B13_R_3": { + "src_wire": "PCIE_TOP_CFGMGMTDO22", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX24_R_4->PCIE_TOP_CFGVENDID0": { + "src_wire": "PCIE_IMUX24_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGVENDID0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGPMRCVENTERL1N->PCIE_LOGIC_OUTS_B12_L_0": { + "src_wire": "PCIE_TOP_CFGPMRCVENTERL1N", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX6_R_3->PCIE_TOP_MIMRXRDATA42": { + "src_wire": "PCIE_IMUX6_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA42", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX33_R_1->PCIE_TOP_PIPERX4DATA2": { + "src_wire": "PCIE_IMUX33_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO28->PCIE_LOGIC_OUTS_B16_R_3": { + "src_wire": "PCIE_TOP_CFGMGMTDO28", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA7->PCIE_LOGIC_OUTS_B23_R_3": { + "src_wire": "PCIE_TOP_MIMRXWDATA7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX9_L_1->PCIE_TOP_CFGDSN62": { + "src_wire": "PCIE_IMUX9_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN62", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA1->PCIE_LOGIC_OUTS_B13_R_0": { + "src_wire": "PCIE_TOP_MIMRXWDATA1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX1_R_2->PCIE_TOP_MIMRXRDATA29": { + "src_wire": "PCIE_IMUX1_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX7_L_4->PCIE_TOP_CFGERRTLPCPLHEADER45": { + "src_wire": "PCIE_IMUX7_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER45", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA12->PCIE_LOGIC_OUTS_B2_R_1": { + "src_wire": "PCIE_TOP_MIMRXWDATA12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLRCB->PCIE_LOGIC_OUTS_B14_L_0": { + "src_wire": "PCIE_TOP_CFGLINKCONTROLRCB", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX12_R_2->PCIE_TOP_TRNTD32": { + "src_wire": "PCIE_IMUX12_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD32", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DRPDO11->PCIE_LOGIC_OUTS_B20_L_1": { + "src_wire": "PCIE_TOP_DRPDO11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_PIPETXMARGIN1->PCIE_LOGIC_OUTS_B16_L_0": { + "src_wire": "PCIE_TOP_PIPETXMARGIN1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2LTREN->PCIE_LOGIC_OUTS_B23_R_4": { + "src_wire": "PCIE_TOP_CFGDEVCONTROL2LTREN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA2->PCIE_LOGIC_OUTS_B18_R_0": { + "src_wire": "PCIE_TOP_MIMRXWDATA2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX32_L_1->PCIE_TOP_PIPERX0DATA3": { + "src_wire": "PCIE_IMUX32_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX14_L_2->PCIE_TOP_DRPDI6": { + "src_wire": "PCIE_IMUX14_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX7_L_1->PCIE_TOP_CFGERRTLPCPLHEADER33": { + "src_wire": "PCIE_IMUX7_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER33", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX1_L_4->PCIE_TOP_LL2SENDASREQL1": { + "src_wire": "PCIE_IMUX1_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_LL2SENDASREQL1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPSRCRDY0->PCIE_LOGIC_OUTS_B10_R_1": { + "src_wire": "PCIE_TOP_TRNRDLLPSRCRDY0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX15_L_3->PCIE_TOP_DRPDI11": { + "src_wire": "PCIE_IMUX15_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX9_L_0->PCIE_TOP_CFGDSN58": { + "src_wire": "PCIE_IMUX9_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN58", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX13_R_4->PCIE_TOP_CFGERRAERHEADERLOG6": { + "src_wire": "PCIE_IMUX13_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA49->PCIE_LOGIC_OUTS_B5_L_4": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA49", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA51->PCIE_LOGIC_OUTS_B7_L_4": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA51", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR0->PCIE_LOGIC_OUTS_B8_L_3": { + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX10_L_0->PCIE_TOP_CFGDSN59": { + "src_wire": "PCIE_IMUX10_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN59", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX0_L_2->PCIE_TOP_TRNTDLLPDATA27": { + "src_wire": "PCIE_IMUX0_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA27", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGPCIELINKSTATE2->PCIE_LOGIC_OUTS_B10_L_0": { + "src_wire": "PCIE_TOP_CFGPCIELINKSTATE2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX16_L_1->PCIE_TOP_PIPERX0CHARISK0": { + "src_wire": "PCIE_IMUX16_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0CHARISK0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA17->PCIE_LOGIC_OUTS_B23_R_1": { + "src_wire": "PCIE_TOP_DBGVECA17", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR2->PCIE_LOGIC_OUTS_B12_R_2": { + "src_wire": "PCIE_TOP_MIMRXRADDR2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX1_R_1->PCIE_TOP_MIMRXRDATA25": { + "src_wire": "PCIE_IMUX1_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGPMCSRPMEEN->PCIE_LOGIC_OUTS_B8_L_2": { + "src_wire": "PCIE_TOP_CFGPMCSRPMEEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA28->PCIE_LOGIC_OUTS_B14_R_2": { + "src_wire": "PCIE_TOP_MIMRXWDATA28", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX9_R_2->PCIE_TOP_TRNTD17": { + "src_wire": "PCIE_IMUX9_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD17", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DRPDO14->PCIE_LOGIC_OUTS_B23_L_1": { + "src_wire": "PCIE_TOP_DRPDO14", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX19_R_2->PCIE_TOP_CFGERRAERHEADERLOG0": { + "src_wire": "PCIE_IMUX19_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX33_R_0->PCIE_TOP_PIPERX4CHANISALIGNED": { + "src_wire": "PCIE_IMUX33_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4CHANISALIGNED", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA15->PCIE_LOGIC_OUTS_B10_R_4": { + "src_wire": "PCIE_TOP_MIMRXWDATA15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX7_R_1->PCIE_TOP_MIMRXRDATA51": { + "src_wire": "PCIE_IMUX7_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA51", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX9_L_3->PCIE_TOP_CFGDEVID6": { + "src_wire": "PCIE_IMUX9_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID6", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3->PCIE_LOGIC_OUTS_B13_L_3": { + "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX21_R_3->PCIE_TOP_CFGERRAERHEADERLOG3": { + "src_wire": "PCIE_IMUX21_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWADDR12->PCIE_LOGIC_OUTS_B1_R_0": { + "src_wire": "PCIE_TOP_MIMRXWADDR12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX2_L_0->PCIE_TOP_TRNTDLLPDATA21": { + "src_wire": "PCIE_IMUX2_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX9_L_2->PCIE_TOP_CFGDEVID2": { + "src_wire": "PCIE_IMUX9_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DRPDO2->PCIE_LOGIC_OUTS_B19_L_3": { + "src_wire": "PCIE_TOP_DRPDO2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD71->PCIE_LOGIC_OUTS_B0_L_3": { + "src_wire": "PCIE_TOP_TRNRD71", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX4_R_0->PCIE_TOP_MIMRXRDATA52": { + "src_wire": "PCIE_IMUX4_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA52", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX17_R_2->PCIE_TOP_CFGERRLOCKEDN": { + "src_wire": "PCIE_IMUX17_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRLOCKEDN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX6_R_1->PCIE_TOP_MIMRXRDATA50": { + "src_wire": "PCIE_IMUX6_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA50", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA34->PCIE_LOGIC_OUTS_B7_L_0": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA34", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX7_R_3->PCIE_TOP_MIMRXRDATA43": { + "src_wire": "PCIE_IMUX7_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA43", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX38_R_0->PCIE_TOP_PIPERX4DATA5": { + "src_wire": "PCIE_IMUX38_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX6_R_4->PCIE_TOP_TRNTD26": { + "src_wire": "PCIE_IMUX6_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLCLOCKPMEN->PCIE_LOGIC_OUTS_B14_L_1": { + "src_wire": "PCIE_TOP_CFGLINKCONTROLCLOCKPMEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA44->PCIE_LOGIC_OUTS_B4_L_3": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA44", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX6_L_1->PCIE_TOP_CFGERRTLPCPLHEADER32": { + "src_wire": "PCIE_IMUX6_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER32", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA37->PCIE_LOGIC_OUTS_B5_L_1": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA37", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX1_R_3->PCIE_TOP_MIMRXRDATA33": { + "src_wire": "PCIE_IMUX1_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA33", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX10_R_1->PCIE_TOP_TRNTD14": { + "src_wire": "PCIE_IMUX10_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR5->PCIE_LOGIC_OUTS_B9_L_4": { + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD67->PCIE_LOGIC_OUTS_B0_L_2": { + "src_wire": "PCIE_TOP_TRNRD67", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP4->PCIE_LOGIC_OUTS_B17_L_2": { + "src_wire": "PCIE_TOP_CFGVCTCVCMAP4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD92->PCIE_LOGIC_OUTS_B3_R_1": { + "src_wire": "PCIE_TOP_TRNRD92", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX5_L_1->PCIE_TOP_CFGERRTLPCPLHEADER31": { + "src_wire": "PCIE_IMUX5_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA24->PCIE_LOGIC_OUTS_B0_R_1": { + "src_wire": "PCIE_TOP_MIMRXWDATA24", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX3_R_0->PCIE_TOP_MIMRXRDATA23": { + "src_wire": "PCIE_IMUX3_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA23", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B20_L_0": { + "src_wire": "PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX16_R_4->PCIE_TOP_CFGERRAERHEADERLOG9": { + "src_wire": "PCIE_IMUX16_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX15_R_4->PCIE_TOP_CFGERRAERHEADERLOG8": { + "src_wire": "PCIE_IMUX15_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DRPDO1->PCIE_LOGIC_OUTS_B18_L_3": { + "src_wire": "PCIE_TOP_DRPDO1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA16->PCIE_LOGIC_OUTS_B22_R_1": { + "src_wire": "PCIE_TOP_DBGVECA16", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX8_L_0->PCIE_TOP_CFGDSN57": { + "src_wire": "PCIE_IMUX8_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN57", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO25->PCIE_LOGIC_OUTS_B14_R_4": { + "src_wire": "PCIE_TOP_CFGMGMTDO25", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLRETRAINLINK->PCIE_LOGIC_OUTS_B17_L_0": { + "src_wire": "PCIE_TOP_CFGLINKCONTROLRETRAINLINK", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD85->PCIE_LOGIC_OUTS_B2_R_3": { + "src_wire": "PCIE_TOP_TRNRD85", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD61->PCIE_LOGIC_OUTS_B2_L_0": { + "src_wire": "PCIE_TOP_TRNRD61", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN->PCIE_LOGIC_OUTS_B13_L_2": { + "src_wire": "PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX11_R_0->PCIE_TOP_TRNTD11": { + "src_wire": "PCIE_IMUX11_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA0->PCIE_LOGIC_OUTS_B21_L_2": { + "src_wire": "PCIE_TOP_DBGVECA0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA57->PCIE_LOGIC_OUTS_B6_R_3": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA57", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2->PCIE_LOGIC_OUTS_B12_L_3": { + "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD78->PCIE_LOGIC_OUTS_B3_L_4": { + "src_wire": "PCIE_TOP_TRNRD78", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD79->PCIE_LOGIC_OUTS_B0_R_4": { + "src_wire": "PCIE_TOP_TRNRD79", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX0_R_1->PCIE_TOP_MIMRXRDATA24": { + "src_wire": "PCIE_IMUX0_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO24->PCIE_LOGIC_OUTS_B13_R_4": { + "src_wire": "PCIE_TOP_CFGMGMTDO24", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX13_R_2->PCIE_TOP_TRNTD33": { + "src_wire": "PCIE_IMUX13_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD33", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_PL2SUSPENDOK->PCIE_LOGIC_OUTS_B7_R_0": { + "src_wire": "PCIE_TOP_PL2SUSPENDOK", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR2->PCIE_LOGIC_OUTS_B10_L_3": { + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR2", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX1_L_3->PCIE_TOP_TRNTDLLPSRCRDY": { + "src_wire": "PCIE_IMUX1_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPSRCRDY", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED->PCIE_LOGIC_OUTS_B21_L_0": { + "src_wire": "PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR1->PCIE_LOGIC_OUTS_B11_R_1": { + "src_wire": "PCIE_TOP_MIMRXRADDR1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGPMRCVASREQL1N->PCIE_LOGIC_OUTS_B11_L_0": { + "src_wire": "PCIE_TOP_CFGPMRCVASREQL1N", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX10_L_1->PCIE_TOP_CFGDSN63": { + "src_wire": "PCIE_IMUX10_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN63", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX36_L_1->PCIE_TOP_PIPERX0DATA1": { + "src_wire": "PCIE_IMUX36_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR0->PCIE_LOGIC_OUTS_B13_R_2": { + "src_wire": "PCIE_TOP_MIMRXRADDR0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX20_R_3->PCIE_TOP_CFGERRAERHEADERLOG2": { + "src_wire": "PCIE_IMUX20_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA32->PCIE_LOGIC_OUTS_B4_L_0": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA32", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX2_R_2->PCIE_TOP_MIMRXRDATA30": { + "src_wire": "PCIE_IMUX2_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX15_R_1->PCIE_TOP_TRNTD39": { + "src_wire": "PCIE_IMUX15_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD39", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX9_R_4->PCIE_TOP_PL2DIRECTEDLSTATE2": { + "src_wire": "PCIE_IMUX9_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD91->PCIE_LOGIC_OUTS_B1_R_1": { + "src_wire": "PCIE_TOP_TRNRD91", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD88->PCIE_LOGIC_OUTS_B3_R_2": { + "src_wire": "PCIE_TOP_TRNRD88", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX4_L_0->PCIE_TOP_CFGERRTLPCPLHEADER26": { + "src_wire": "PCIE_IMUX4_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER26", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX12_R_0->PCIE_TOP_TRNTD40": { + "src_wire": "PCIE_IMUX12_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD40", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DRPDO12->PCIE_LOGIC_OUTS_B21_L_1": { + "src_wire": "PCIE_TOP_DRPDO12", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX7_L_2->PCIE_TOP_CFGERRTLPCPLHEADER37": { + "src_wire": "PCIE_IMUX7_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER37", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DRPRDY->PCIE_LOGIC_OUTS_B16_L_3": { + "src_wire": "PCIE_TOP_DRPRDY", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD65->PCIE_LOGIC_OUTS_B2_L_1": { + "src_wire": "PCIE_TOP_TRNRD65", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX10_R_4->PCIE_TOP_PL2DIRECTEDLSTATE3": { + "src_wire": "PCIE_IMUX10_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX18_R_2->PCIE_TOP_CFGERRNORECOVERYN": { + "src_wire": "PCIE_IMUX18_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRNORECOVERYN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX8_R_0->PCIE_TOP_TRNTD8": { + "src_wire": "PCIE_IMUX8_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD8", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD62->PCIE_LOGIC_OUTS_B3_L_0": { + "src_wire": "PCIE_TOP_TRNRD62", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX9_R_3->PCIE_TOP_TRNTD21": { + "src_wire": "PCIE_IMUX9_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX4_L_1->PCIE_TOP_CFGERRTLPCPLHEADER30": { + "src_wire": "PCIE_IMUX4_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS->PCIE_LOGIC_OUTS_B14_L_3": { + "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO18->PCIE_LOGIC_OUTS_B17_R_2": { + "src_wire": "PCIE_TOP_CFGMGMTDO18", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD72->PCIE_LOGIC_OUTS_B1_L_3": { + "src_wire": "PCIE_TOP_TRNRD72", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX37_L_0->PCIE_TOP_PIPERX0PHYSTATUS": { + "src_wire": "PCIE_IMUX37_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0PHYSTATUS", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD76->PCIE_LOGIC_OUTS_B1_L_4": { + "src_wire": "PCIE_TOP_TRNRD76", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD80->PCIE_LOGIC_OUTS_B2_R_4": { + "src_wire": "PCIE_TOP_TRNRD80", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA53->PCIE_LOGIC_OUTS_B6_R_4": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA53", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX5_R_3->PCIE_TOP_MIMRXRDATA41": { + "src_wire": "PCIE_IMUX5_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA41", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGPMCSRPOWERSTATE0->PCIE_LOGIC_OUTS_B10_L_1": { + "src_wire": "PCIE_TOP_CFGPMCSRPOWERSTATE0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX8_L_4->PCIE_TOP_CFGDEVID9": { + "src_wire": "PCIE_IMUX8_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID9", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA11->PCIE_LOGIC_OUTS_B18_R_4": { + "src_wire": "PCIE_TOP_MIMRXWDATA11", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX1_L_0->PCIE_TOP_TRNTDLLPDATA20": { + "src_wire": "PCIE_IMUX1_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA20", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX15_L_1->PCIE_TOP_DRPDI3": { + "src_wire": "PCIE_IMUX15_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR1->PCIE_LOGIC_OUTS_B9_L_3": { + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC->PCIE_LOGIC_OUTS_B13_L_1": { + "src_wire": "PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP5->PCIE_LOGIC_OUTS_B18_L_2": { + "src_wire": "PCIE_TOP_CFGVCTCVCMAP5", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP6->PCIE_LOGIC_OUTS_B19_L_2": { + "src_wire": "PCIE_TOP_CFGVCTCVCMAP6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA54->PCIE_LOGIC_OUTS_B7_R_4": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA54", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX4_L_4->PCIE_TOP_CFGERRTLPCPLHEADER42": { + "src_wire": "PCIE_IMUX4_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER42", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX24_R_3->PCIE_TOP_CFGERRAERHEADERLOG10": { + "src_wire": "PCIE_IMUX24_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA7->PCIE_LOGIC_OUTS_B20_L_4": { + "src_wire": "PCIE_TOP_DBGVECA7", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX39_L_0->PCIE_TOP_PIPERX0DATA4": { + "src_wire": "PCIE_IMUX39_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX38_L_0->PCIE_TOP_PIPERX0DATA5": { + "src_wire": "PCIE_IMUX38_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA5", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX8_R_1->PCIE_TOP_TRNTD12": { + "src_wire": "PCIE_IMUX8_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD12", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXREN->PCIE_LOGIC_OUTS_B12_R_1": { + "src_wire": "PCIE_TOP_MIMRXREN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA10->PCIE_LOGIC_OUTS_B19_R_1": { + "src_wire": "PCIE_TOP_MIMRXWDATA10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX34_L_0->PCIE_TOP_PIPERX0DATA7": { + "src_wire": "PCIE_IMUX34_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA42->PCIE_LOGIC_OUTS_B6_L_2": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA42", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD63->PCIE_LOGIC_OUTS_B0_L_1": { + "src_wire": "PCIE_TOP_TRNRD63", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX15_L_2->PCIE_TOP_DRPDI7": { + "src_wire": "PCIE_IMUX15_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI7", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX2_R_0->PCIE_TOP_MIMRXRDATA22": { + "src_wire": "PCIE_IMUX2_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA20->PCIE_LOGIC_OUTS_B20_R_0": { + "src_wire": "PCIE_TOP_DBGVECA20", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA35->PCIE_LOGIC_OUTS_B8_L_0": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA35", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX37_L_1->PCIE_TOP_PIPERX0DATA0": { + "src_wire": "PCIE_IMUX37_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD89->PCIE_LOGIC_OUTS_B4_R_2": { + "src_wire": "PCIE_TOP_TRNRD89", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX9_R_1->PCIE_TOP_TRNTD13": { + "src_wire": "PCIE_IMUX9_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD13", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX0_R_4->PCIE_TOP_MIMRXRDATA36": { + "src_wire": "PCIE_IMUX0_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA36", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX8_R_4->PCIE_TOP_PL2DIRECTEDLSTATE1": { + "src_wire": "PCIE_IMUX8_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA48->PCIE_LOGIC_OUTS_B4_L_4": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA48", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX7_L_0->PCIE_TOP_CFGERRTLPCPLHEADER29": { + "src_wire": "PCIE_IMUX7_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGPMCSRPMESTATUS->PCIE_LOGIC_OUTS_B9_L_2": { + "src_wire": "PCIE_TOP_CFGPMCSRPMESTATUS", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD60->PCIE_LOGIC_OUTS_B1_L_0": { + "src_wire": "PCIE_TOP_TRNRD60", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA17->PCIE_LOGIC_OUTS_B9_R_2": { + "src_wire": "PCIE_TOP_MIMRXWDATA17", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGCOMMANDMEMENABLE->PCIE_LOGIC_OUTS_B17_R_4": { + "src_wire": "PCIE_TOP_CFGCOMMANDMEMENABLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX2_R_3->PCIE_TOP_MIMRXRDATA34": { + "src_wire": "PCIE_IMUX2_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA34", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA6->PCIE_LOGIC_OUTS_B16_R_0": { + "src_wire": "PCIE_TOP_MIMRXWDATA6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX6_L_0->PCIE_TOP_CFGERRTLPCPLHEADER28": { + "src_wire": "PCIE_IMUX6_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD59->PCIE_LOGIC_OUTS_B0_L_0": { + "src_wire": "PCIE_TOP_TRNRD59", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR8->PCIE_LOGIC_OUTS_B17_R_0": { + "src_wire": "PCIE_TOP_MIMRXRADDR8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DRPDO13->PCIE_LOGIC_OUTS_B22_L_1": { + "src_wire": "PCIE_TOP_DRPDO13", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD75->PCIE_LOGIC_OUTS_B0_L_4": { + "src_wire": "PCIE_TOP_TRNRD75", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA10->PCIE_LOGIC_OUTS_B23_L_4": { + "src_wire": "PCIE_TOP_DBGVECA10", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA33->PCIE_LOGIC_OUTS_B22_R_2": { + "src_wire": "PCIE_TOP_MIMRXWDATA33", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX13_R_3->PCIE_TOP_TRNTD29": { + "src_wire": "PCIE_IMUX13_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD29", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX14_R_3->PCIE_TOP_TRNTD30": { + "src_wire": "PCIE_IMUX14_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD30", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD84->PCIE_LOGIC_OUTS_B1_R_3": { + "src_wire": "PCIE_TOP_TRNRD84", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD68->PCIE_LOGIC_OUTS_B1_L_2": { + "src_wire": "PCIE_TOP_TRNRD68", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX16_R_3->PCIE_TOP_LL2SUSPENDNOW": { + "src_wire": "PCIE_IMUX16_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_LL2SUSPENDNOW", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX8_L_1->PCIE_TOP_CFGDSN61": { + "src_wire": "PCIE_IMUX8_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN61", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA56->PCIE_LOGIC_OUTS_B5_R_3": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA56", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA31->PCIE_LOGIC_OUTS_B21_R_2": { + "src_wire": "PCIE_TOP_MIMRXWDATA31", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPSRCRDY1->PCIE_LOGIC_OUTS_B14_R_1": { + "src_wire": "PCIE_TOP_TRNRDLLPSRCRDY1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX14_L_3->PCIE_TOP_DRPDI10": { + "src_wire": "PCIE_IMUX14_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI10", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA3->PCIE_LOGIC_OUTS_B15_R_2": { + "src_wire": "PCIE_TOP_MIMRXWDATA3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA61->PCIE_LOGIC_OUTS_B8_R_2": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA61", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA8->PCIE_LOGIC_OUTS_B8_R_1": { + "src_wire": "PCIE_TOP_MIMRXWDATA8", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD96->PCIE_LOGIC_OUTS_B4_R_0": { + "src_wire": "PCIE_TOP_TRNRD96", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX1_R_0->PCIE_TOP_MIMRXRDATA21": { + "src_wire": "PCIE_IMUX1_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA21", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED->PCIE_LOGIC_OUTS_B22_L_0": { + "src_wire": "PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX11_R_4->PCIE_TOP_PL2DIRECTEDLSTATE4": { + "src_wire": "PCIE_IMUX11_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX23_R_4->PCIE_TOP_CFGDEVID15": { + "src_wire": "PCIE_IMUX23_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID15", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX14_L_1->PCIE_TOP_DRPDI2": { + "src_wire": "PCIE_IMUX14_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX37_R_1->PCIE_TOP_PIPERX4DATA0": { + "src_wire": "PCIE_IMUX37_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD94->PCIE_LOGIC_OUTS_B6_R_1": { + "src_wire": "PCIE_TOP_TRNRD94", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD82->PCIE_LOGIC_OUTS_B4_R_4": { + "src_wire": "PCIE_TOP_TRNRD82", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX22_R_4->PCIE_TOP_CFGDEVID14": { + "src_wire": "PCIE_IMUX22_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID14", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA46->PCIE_LOGIC_OUTS_B6_L_3": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA46", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX0_R_3->PCIE_TOP_MIMRXRDATA32": { + "src_wire": "PCIE_IMUX0_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA32", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGPMCSRPOWERSTATE1->PCIE_LOGIC_OUTS_B11_L_1": { + "src_wire": "PCIE_TOP_CFGPMCSRPOWERSTATE1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR4->PCIE_LOGIC_OUTS_B8_L_4": { + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX19_R_4->PCIE_TOP_CFGINTERRUPTN": { + "src_wire": "PCIE_IMUX19_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGINTERRUPTN", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA20->PCIE_LOGIC_OUTS_B0_R_0": { + "src_wire": "PCIE_TOP_MIMRXWDATA20", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNTDSTRDY3->PCIE_LOGIC_OUTS_B1_R_4": { + "src_wire": "PCIE_TOP_TRNTDSTRDY3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX4_R_1->PCIE_TOP_MIMRXRDATA48": { + "src_wire": "PCIE_IMUX4_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA48", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX3_L_3->PCIE_TOP_LL2SENDENTERL1": { + "src_wire": "PCIE_IMUX3_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_LL2SENDENTERL1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP3->PCIE_LOGIC_OUTS_B16_L_2": { + "src_wire": "PCIE_TOP_CFGVCTCVCMAP3", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX11_L_2->PCIE_TOP_CFGDEVID4": { + "src_wire": "PCIE_IMUX11_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX6_R_0->PCIE_TOP_MIMRXRDATA54": { + "src_wire": "PCIE_IMUX6_R_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA54", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA9->PCIE_LOGIC_OUTS_B3_R_3": { + "src_wire": "PCIE_TOP_MIMRXWDATA9", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD97->PCIE_LOGIC_OUTS_B5_R_0": { + "src_wire": "PCIE_TOP_TRNRD97", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA41->PCIE_LOGIC_OUTS_B5_L_2": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA41", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO17->PCIE_LOGIC_OUTS_B16_R_2": { + "src_wire": "PCIE_TOP_CFGMGMTDO17", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX0_L_3->PCIE_TOP_TRNTDLLPDATA31": { + "src_wire": "PCIE_IMUX0_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA31", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA63->PCIE_LOGIC_OUTS_B11_R_2": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA63", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO19->PCIE_LOGIC_OUTS_B19_R_2": { + "src_wire": "PCIE_TOP_CFGMGMTDO19", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX11_R_2->PCIE_TOP_TRNTD19": { + "src_wire": "PCIE_IMUX11_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD19", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2IDOCPLEN->PCIE_LOGIC_OUTS_B15_L_4": { + "src_wire": "PCIE_TOP_CFGDEVCONTROL2IDOCPLEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX2_L_3->PCIE_TOP_LL2TLPRCV": { + "src_wire": "PCIE_IMUX2_L_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_LL2TLPRCV", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA35->PCIE_LOGIC_OUTS_B11_R_4": { + "src_wire": "PCIE_TOP_MIMRXWDATA35", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX25_R_4->PCIE_TOP_DBGMODE0": { + "src_wire": "PCIE_IMUX25_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DBGMODE0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX1_L_2->PCIE_TOP_TRNTDLLPDATA28": { + "src_wire": "PCIE_IMUX1_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA60->PCIE_LOGIC_OUTS_B7_R_2": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA60", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA26->PCIE_LOGIC_OUTS_B13_R_1": { + "src_wire": "PCIE_TOP_MIMRXWDATA26", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DRPDO0->PCIE_LOGIC_OUTS_B17_L_3": { + "src_wire": "PCIE_TOP_DRPDO0", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA33->PCIE_LOGIC_OUTS_B5_L_0": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA33", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX36_R_1->PCIE_TOP_PIPERX4DATA1": { + "src_wire": "PCIE_IMUX36_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX2_L_4->PCIE_TOP_LL2SENDPMACK": { + "src_wire": "PCIE_IMUX2_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_LL2SENDPMACK", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX5_R_1->PCIE_TOP_MIMRXRDATA49": { + "src_wire": "PCIE_IMUX5_R_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA49", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX8_L_2->PCIE_TOP_CFGDEVID1": { + "src_wire": "PCIE_IMUX8_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTION->PCIE_LOGIC_OUTS_B10_L_2": { + "src_wire": "PCIE_TOP_CFGTRANSACTION", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX3_R_4->PCIE_TOP_MIMRXRDATA39": { + "src_wire": "PCIE_IMUX3_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA39", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX20_R_4->PCIE_TOP_CFGINTERRUPTDI0": { + "src_wire": "PCIE_IMUX20_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGINTERRUPTDI0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO29->PCIE_LOGIC_OUTS_B17_R_3": { + "src_wire": "PCIE_TOP_CFGMGMTDO29", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DRPDO15->PCIE_LOGIC_OUTS_B20_L_2": { + "src_wire": "PCIE_TOP_DRPDO15", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_2", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO26->PCIE_LOGIC_OUTS_B15_R_4": { + "src_wire": "PCIE_TOP_CFGMGMTDO26", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX2_L_1->PCIE_TOP_TRNTDLLPDATA25": { + "src_wire": "PCIE_IMUX2_L_1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA25", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_LL2TFCINIT2SEQ->PCIE_LOGIC_OUTS_B20_R_1": { + "src_wire": "PCIE_TOP_LL2TFCINIT2SEQ", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX4_R_4->PCIE_TOP_TRNTD24": { + "src_wire": "PCIE_IMUX4_R_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD24", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX3_L_0->PCIE_TOP_TRNTDLLPDATA22": { + "src_wire": "PCIE_IMUX3_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX10_L_4->PCIE_TOP_CFGDEVID11": { + "src_wire": "PCIE_IMUX10_L_4", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID11", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_LL2TFCINIT1SEQ->PCIE_LOGIC_OUTS_B16_R_1": { + "src_wire": "PCIE_TOP_LL2TFCINIT1SEQ", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_1", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK->PCIE_LOGIC_OUTS_B13_L_4": { + "src_wire": "PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA58->PCIE_LOGIC_OUTS_B7_R_3": { + "src_wire": "PCIE_TOP_TRNRDLLPDATA58", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX10_L_2->PCIE_TOP_CFGDEVID3": { + "src_wire": "PCIE_IMUX10_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID3", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD98->PCIE_LOGIC_OUTS_B6_R_0": { + "src_wire": "PCIE_TOP_TRNRD98", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGCOMMANDBUSMASTERENABLE->PCIE_LOGIC_OUTS_B20_R_4": { + "src_wire": "PCIE_TOP_CFGCOMMANDBUSMASTERENABLE", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA21->PCIE_LOGIC_OUTS_B21_R_0": { + "src_wire": "PCIE_TOP_DBGVECA21", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DRPDO6->PCIE_LOGIC_OUTS_B19_L_4": { + "src_wire": "PCIE_TOP_DRPDO6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2IDOREQEN->PCIE_LOGIC_OUTS_B14_L_4": { + "src_wire": "PCIE_TOP_CFGDEVCONTROL2IDOREQEN", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX0_R_2->PCIE_TOP_MIMRXRDATA28": { + "src_wire": "PCIE_IMUX0_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA28", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR6->PCIE_LOGIC_OUTS_B10_L_4": { + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR6", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA18->PCIE_LOGIC_OUTS_B14_R_0": { + "src_wire": "PCIE_TOP_DBGVECA18", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_0", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX8_R_2->PCIE_TOP_TRNTD16": { + "src_wire": "PCIE_IMUX8_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD16", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX10_R_3->PCIE_TOP_TRNTD22": { + "src_wire": "PCIE_IMUX10_R_3", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD22", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX6_R_2->PCIE_TOP_MIMRXRDATA46": { + "src_wire": "PCIE_IMUX6_R_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA46", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_TOP_DRPDO4->PCIE_LOGIC_OUTS_B17_L_4": { + "src_wire": "PCIE_TOP_DRPDO4", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_4", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX5_L_2->PCIE_TOP_CFGERRTLPCPLHEADER35": { + "src_wire": "PCIE_IMUX5_L_2", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER35", + "is_directional": "1", + "can_invert": "0" + }, + "PCIE_TOP.PCIE_IMUX5_L_0->PCIE_TOP_CFGERRTLPCPLHEADER27": { + "src_wire": "PCIE_IMUX5_L_0", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER27", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_RIOB18.json b/kintex7/tile_type_RIOB18.json new file mode 100644 index 0000000..78c6627 --- /dev/null +++ b/kintex7/tile_type_RIOB18.json @@ -0,0 +1,415 @@ +{ + "tile_type": "RIOB18", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IOB", + "type": "IOB18S", + "site_pins": { + "PU_INT_EN": "IOB_PU_INT_EN_0", + "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_0", + "DIFFO_OUT": "IOB_DIFFO_OUT1", + "PADOUT": "IOB_PADOUT1", + "O_IN": "IOB_O_IN1", + "DIFFI_IN": "IOB_DIFFI_IN1", + "O_OUT": "IOB_O_OUT1", + "IBUFDISABLE": "IOB_IBUF_DISABLE1", + "O": "IOB_O1", + "DIFF_TERM_INT_EN": "IOB_DIFF_TERM_INT_EN", + "T": "IOB_T1", + "DIFFO_IN": "IOB_DIFFO_IN1", + "I": "IOB_IBUF1", + "PD_INT_EN": "IOB_PD_INT_EN_0", + "DCITERMDISABLE": "IOB_DCI_T_TERM1", + "T_OUT": "IOB_T_OUT1", + "T_IN": "IOB_T_IN1" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "IOB", + "type": "IOB18M", + "site_pins": { + "PU_INT_EN": "IOB_PU_INT_EN_1", + "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", + "DIFFO_OUT": "IOB_DIFFO_OUT0", + "PADOUT": "IOB_PADOUT0", + "O_IN": null, + "DIFFI_IN": "IOB_DIFFI_IN0", + "O_OUT": "IOB_O_OUT0", + "IBUFDISABLE": "IOB_IBUF_DISABLE0", + "O": "IOB_O0", + "DIFF_TERM_INT_EN": null, + "T": "IOB_T0", + "DIFFO_IN": null, + "I": "IOB_IBUF0", + "PD_INT_EN": "IOB_PD_INT_EN_1", + "DCITERMDISABLE": "IOB_DCI_T_TERM0", + "T_OUT": "IOB_T_OUT0", + "T_IN": null + }, + "x_coord": 0 + } + ], + "wires": [ + "RIOB_EL1BEG3_1", + "RIOB_SE4C1_0", + "RIOB_EE4B3_1", + "RIOB_WW4A1_0", + "RIOB_EE4BEG3_1", + "RIOB_WW4END2_1", + "RIOB_NE2A0_0", + "RIOB_SW4A0_1", + "RIOB_EE4A3_1", + "RIOB_EE4A1_1", + "RIOB_WL1END0_0", + "RIOB_WR1END0_0", + "RIOB_LH12_0", + "IOB_DIFFO_OUT1", + "RIOB_WW4C2_1", + "RIOB_WW4END0_0", + "RIOB_NE4BEG3_1", + "RIOB_ER1BEG0_0", + "RIOB_LH6_1", + "RIOB_EL1BEG2_1", + "RIOB_NE2A2_1", + "RIOB_LH12_1", + "RIOB_WW2A1_0", + "RIOB_SE4BEG0_1", + "RIOB_EL1BEG1_1", + "RIOB_WR1END1_1", + "RIOB_LH7_0", + "RIOB_WW4C3_1", + "RIOB_EE4C2_1", + "IOB_PU_INT_EN_0", + "RIOB_SW2A2_0", + "IOB_DCI_T_TERM0", + "RIOB_SE2A1_1", + "RIOB_EL1BEG2_0", + "RIOB_LH9_1", + "RIOB_ER1BEG0_1", + "RIOB_NW4END0_1", + "RIOB_EE2BEG0_1", + "IOB_KEEPER_INT_EN_1", + "RIOB_WW2A3_0", + "RIOB_LH9_0", + "RIOB_EE4B1_0", + "IOB_O_OUT1", + "IOB_DIFFI_IN1", + "RIOB_NW4END3_1", + "IOB_T_IN0", + "RIOB_NE4C1_1", + "RIOB_WR1END2_0", + "RIOB_SE4BEG3_1", + "RIOB_EE2BEG1_1", + "RIOB_ER1BEG2_1", + "RIOB_SE4BEG1_1", + "RIOB_WW4END2_0", + "RIOB_NW4END0_0", + "RIOB_LH1_0", + "RIOB_NW2A0_1", + "RIOB_SW4END2_1", + "RIOB_EE2A1_0", + "RIOB_EE2A0_0", + "RIOB_SW4END1_1", + "IOB_PD_INT_EN_1", + "RIOB_LH6_0", + "RIOB_SE4C0_1", + "RIOB_SE2A3_0", + "RIOB_NW4END3_0", + "RIOB_WW4C3_0", + "RIOB_SW4END3_0", + "RIOB_WL1END2_0", + "RIOB_EE2A0_1", + "RIOB_EE2BEG3_0", + "RIOB_EE4B0_1", + "IOB_DIFF_TERM_INT_EN", + "IOB_IBUF1", + "IOB_IBUF0", + "RIOB_EE4BEG0_1", + "RIOB_NE4BEG3_0", + "RIOB_NE4C1_0", + "RIOB_NW2A2_0", + "RIOB_NW4END2_0", + "RIOB_SE4BEG1_0", + "RIOB_NE2A0_1", + "IOB_DIFF_TERM_INT_EN_STUB", + "RIOB_SE4C2_0", + "RIOB_SE4C3_1", + "RIOB_NE2A1_1", + "RIOB_NE4BEG2_1", + "RIOB_SW4A2_0", + "RIOB_EE2BEG0_0", + "RIOB_NW4END1_0", + "RIOB_SE4BEG2_1", + "RIOB_NE2A3_0", + "RIOB_WW2A0_0", + "RIOB_SE2A0_1", + "RIOB_EE4C3_0", + "RIOB_SW4END2_0", + "RIOB_WW4B0_0", + "RIOB_SW2A1_1", + "RIOB_EE2A3_0", + "RIOB_WL1END3_1", + "RIOB_SW2A3_1", + "RIOB_EL1BEG3_0", + "RIOB_SE4BEG0_0", + "IOB_T1", + "RIOB_LH2_1", + "RIOB_NW4A1_0", + "RIOB_WW2A3_1", + "RIOB_EE4BEG1_0", + "IOB_O0", + "RIOB_EE2BEG3_1", + "RIOB_NE4C0_0", + "IOB_O_IN0", + "IOB_DIFFO_IN1", + "RIOB_WW2A2_0", + "RIOB_ER1BEG1_1", + "RIOB_WL1END1_0", + "RIOB_EE4A3_0", + "RIOB_SW4END1_0", + "RIOB_EE2A3_1", + "RIOB_EE4B0_0", + "RIOB_NW2A2_1", + "IOB_T_IN1", + "IOB_T_OUT1", + "IOB_O_IN1", + "RIOB_SE4BEG2_0", + "RIOB_WW4END3_1", + "RIOB_EE4A0_1", + "RIOB_WW4B2_1", + "RIOB_LH4_1", + "RIOB_NW4A2_0", + "RIOB_WW2A2_1", + "RIOB_WW4C0_0", + "RIOB_LH11_1", + "IOB_KEEPER_INT_EN_0", + "RIOB_WW2A0_1", + "RIOB_EE2BEG2_0", + "RIOB_EE2BEG1_0", + "RIOB_NW2A3_0", + "RIOB_LH1_1", + "RIOB_SW2A1_0", + "RIOB_SE4C1_1", + "RIOB_EE4C2_0", + "RIOB_SW4END3_1", + "RIOB_NW2A3_1", + "RIOB_NW4END1_1", + "IOB_DIFFI_IN0", + "RIOB_EE4BEG2_1", + "RIOB_EE4B2_1", + "RIOB_WW4A2_0", + "RIOB_WW2END3_0", + "RIOB_WW4END1_0", + "RIOB_NE4C2_0", + "RIOB_NW4A2_1", + "IOB_PADOUT1", + "RIOB_NW2A1_1", + "RIOB_WW4A3_0", + "RIOB_WR1END3_0", + "RIOB_MONITOR_N", + "RIOB_NE4BEG0_0", + "RIOB_LH11_0", + "RIOB_WW2END2_1", + "RIOB_NE4BEG1_1", + "IOB_O1", + "RIOB_WW2END3_1", + "RIOB_NE4C2_1", + "RIOB_EE4A1_0", + "RIOB_EE4A2_1", + "RIOB_NE2A2_0", + "RIOB_SW4END0_1", + "RIOB_WW2END0_1", + "RIOB_NW4A1_1", + "RIOB_SE2A3_1", + "RIOB_NW2A1_0", + "IOB_O_OUT0", + "RIOB_WR1END2_1", + "IOB_PD_INT_EN_0", + "RIOB_WW4C1_0", + "RIOB_LH2_0", + "IOB_T_OUT0", + "RIOB_SW2A3_0", + "RIOB_NE4BEG1_0", + "RIOB_EE4C0_1", + "RIOB_WW4END0_1", + "RIOB_EE4A0_0", + "RIOB_WW4B3_1", + "RIOB_WL1END1_1", + "RIOB_LH7_1", + "RIOB_NE4BEG0_1", + "RIOB_WR1END0_1", + "RIOB_SW2A0_1", + "RIOB_SE4C2_1", + "RIOB_WW4END3_0", + "RIOB_SW4A3_1", + "RIOB_SW2A0_0", + "RIOB_WW2END1_1", + "RIOB_NE2A3_1", + "RIOB_SE2A0_0", + "RIOB_ER1BEG3_0", + "RIOB_EE4B3_0", + "RIOB_SW4A1_1", + "RIOB_WL1END0_1", + "RIOB_EE4C3_1", + "RIOB_ER1BEG1_0", + "IOB_DIFFO_IN0", + "RIOB_WW2A1_1", + "RIOB_EE2A1_1", + "RIOB_NE2A1_0", + "RIOB_WW4END1_1", + "RIOB_SE4C3_0", + "RIOB_SW4A1_0", + "RIOB_EE2A2_1", + "RIOB_SE2A2_1", + "RIOB_NE4BEG2_0", + "RIOB_WW2END1_0", + "RIOB_EE4BEG3_0", + "RIOB_WW4C1_1", + "RIOB_SW4A0_0", + "RIOB_SW4A3_0", + "RIOB_WW4B0_1", + "RIOB_LH3_0", + "RIOB_LH8_1", + "RIOB_WW4A0_0", + "IOB_PU_INT_EN_1", + "RIOB_NE4C3_0", + "RIOB_EE4B1_1", + "RIOB_WW4B1_0", + "RIOB_LH10_0", + "RIOB_WW4B2_0", + "RIOB_EE4C1_1", + "RIOB_EE4BEG2_0", + "RIOB_NE4C3_1", + "RIOB_LH8_0", + "RIOB_LH10_1", + "RIOB_NW4A3_1", + "RIOB_WW2END0_0", + "RIOB_LH5_0", + "RIOB_NE4C0_1", + "RIOB_WW4A2_1", + "RIOB_WW4B3_0", + "RIOB_SE4BEG3_0", + "RIOB_MONITOR_P", + "RIOB_WW4B1_1", + "IOB_DCI_T_TERM1", + "RIOB_SE4C0_0", + "RIOB_ER1BEG3_1", + "RIOB_LH5_1", + "RIOB_WW4A3_1", + "RIOB_EL1BEG1_0", + "RIOB_WW4A1_1", + "RIOB_LH3_1", + "RIOB_WR1END1_0", + "RIOB_WW2END2_0", + "RIOB_EE4BEG0_0", + "RIOB_WW4C2_0", + "IOB_DIFFO_OUT0", + "RIOB_WW4C0_1", + "RIOB_NW4A0_1", + "RIOB_WL1END2_1", + "RIOB_NW2A0_0", + "RIOB_WW4A0_1", + "RIOB_WL1END3_0", + "RIOB_SW4END0_0", + "RIOB_WR1END3_1", + "RIOB_EE4A2_0", + "RIOB_LH4_0", + "IOB_IBUF_DISABLE1", + "RIOB_EE4C1_0", + "RIOB_EE4B2_0", + "IOB_IBUF_DISABLE0", + "RIOB_EE4BEG1_1", + "RIOB_ER1BEG2_0", + "RIOB_SE2A1_0", + "IOB_T0", + "RIOB_EE4C0_0", + "RIOB_EL1BEG0_0", + "RIOB_EL1BEG0_1", + "RIOB_SE2A2_0", + "RIOB_SW2A2_1", + "RIOB_NW4A3_0", + "RIOB_NW4END2_1", + "RIOB_NW4A0_0", + "IOB_PADOUT0", + "RIOB_EE2BEG2_1", + "RIOB_EE2A2_0", + "RIOB_SW4A2_1" + ], + "pips": { + "RIOB18.IOB_PADOUT0->IOB_DIFFI_IN1": { + "src_wire": "IOB_PADOUT0", + "is_pseudo": "0", + "dst_wire": "IOB_DIFFI_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOB18.IOB_PADOUT0->RIOB_MONITOR_P": { + "src_wire": "IOB_PADOUT0", + "is_pseudo": "0", + "dst_wire": "RIOB_MONITOR_P", + "is_directional": "1", + "can_invert": "0" + }, + "RIOB18.IOB_PADOUT1->RIOB_MONITOR_N": { + "src_wire": "IOB_PADOUT1", + "is_pseudo": "0", + "dst_wire": "RIOB_MONITOR_N", + "is_directional": "1", + "can_invert": "0" + }, + "RIOB18.IOB_T0->>IOB_T_OUT0": { + "src_wire": "IOB_T0", + "is_pseudo": "1", + "dst_wire": "IOB_T_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOB18.IOB_T_OUT0->IOB_T_IN1": { + "src_wire": "IOB_T_OUT0", + "is_pseudo": "0", + "dst_wire": "IOB_T_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOB18.IOB_DIFFO_IN1->>IOB_PADOUT1": { + "src_wire": "IOB_DIFFO_IN1", + "is_pseudo": "1", + "dst_wire": "IOB_PADOUT1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOB18.IOB_O0->>IOB_O_OUT0": { + "src_wire": "IOB_O0", + "is_pseudo": "1", + "dst_wire": "IOB_O_OUT0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOB18.IOB_PADOUT1->IOB_DIFFI_IN0": { + "src_wire": "IOB_PADOUT1", + "is_pseudo": "0", + "dst_wire": "IOB_DIFFI_IN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOB18.IOB_DIFFO_OUT0->IOB_DIFFO_IN1": { + "src_wire": "IOB_DIFFO_OUT0", + "is_pseudo": "0", + "dst_wire": "IOB_DIFFO_IN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOB18.IOB_O_OUT0->IOB_O_IN1": { + "src_wire": "IOB_O_OUT0", + "is_pseudo": "0", + "dst_wire": "IOB_O_IN1", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_RIOB18_SING.json b/kintex7/tile_type_RIOB18_SING.json new file mode 100644 index 0000000..88f2986 --- /dev/null +++ b/kintex7/tile_type_RIOB18_SING.json @@ -0,0 +1,175 @@ +{ + "tile_type": "RIOB18_SING", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IOB", + "type": "IOB18", + "site_pins": { + "O_OUT": "IOB_O_OUT0", + "O": "IOB_O0", + "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", + "T": "IOB_T0", + "T_OUT": "IOB_T_OUT0", + "DIFFI_IN": null, + "PU_INT_EN": "IOB_PU_INT_EN_1", + "DIFF_TERM_INT_EN": null, + "PADOUT": "IOB_PADOUT0", + "O_IN": null, + "IBUFDISABLE": "IOB_IBUF_DISABLE0", + "DIFFO_IN": null, + "DIFFO_OUT": "IOB_DIFFO_OUT0", + "PD_INT_EN": "IOB_PD_INT_EN_1", + "DCITERMDISABLE": "IOB_DCI_T_TERM0", + "I": "IOB_IBUF0", + "T_IN": null + }, + "x_coord": 0 + } + ], + "wires": [ + "RIOB_WW2END3_0", + "RIOB_WW4END1_0", + "RIOB_NE4C2_0", + "RIOB_SE4C1_0", + "RIOB_WW4A1_0", + "RIOB_NE2A0_0", + "RIOB_WW4A3_0", + "RIOB_WR1END3_0", + "RIOB_WL1END0_0", + "RIOB_WR1END0_0", + "RIOB_LH12_0", + "RIOB_WW4END0_0", + "RIOB_ER1BEG0_0", + "RIOB_NE4BEG0_0", + "RIOB_LH11_0", + "RIOB_EE4A1_0", + "RIOB_NE2A2_0", + "RIOB_WW2A1_0", + "RIOB_LH7_0", + "RIOB_NW2A1_0", + "RIOB_SW2A2_0", + "IOB_O_OUT0", + "IOB_DCI_T_TERM0", + "RIOB_EL1BEG2_0", + "RIOB_WW4C1_0", + "RIOB_LH2_0", + "IOB_T_OUT0", + "RIOB_SW2A3_0", + "RIOB_NE4BEG1_0", + "IOB_KEEPER_INT_EN_1", + "RIOB_EE4A0_0", + "RIOB_WW2A3_0", + "RIOB_LH9_0", + "RIOB_EE4B1_0", + "IOB_T_IN0", + "RIOB_WW4END3_0", + "RIOB_WR1END2_0", + "RIOB_SW2A0_0", + "RIOB_WW4END2_0", + "RIOB_NW4END0_0", + "RIOB_SE2A0_0", + "RIOB_ER1BEG3_0", + "RIOB_EE4B3_0", + "RIOB_LH1_0", + "RIOB_ER1BEG1_0", + "RIOB_EE2A1_0", + "IOB_DIFFO_IN0", + "RIOB_EE2A0_0", + "RIOB_LH6_0", + "IOB_PD_INT_EN_1", + "RIOB_NE2A1_0", + "RIOB_SE2A3_0", + "RIOB_NW4END3_0", + "RIOB_WW4C3_0", + "RIOB_SE4C3_0", + "RIOB_SW4END3_0", + "RIOB_WL1END2_0", + "RIOB_EE2BEG3_0", + "RIOB_SW4A1_0", + "IOB_IBUF0", + "RIOB_NE4BEG2_0", + "RIOB_NE4BEG3_0", + "RIOB_NE4C1_0", + "RIOB_WW2END1_0", + "RIOB_NW2A2_0", + "RIOB_NW4END2_0", + "RIOB_SE4BEG1_0", + "IOB_DIFF_TERM_INT_EN_STUB", + "RIOB_SE4C2_0", + "RIOB_EE4BEG3_0", + "RIOB_SW4A0_0", + "RIOB_SW4A3_0", + "RIOB_SW4A2_0", + "RIOB_LH3_0", + "RIOB_WW4A0_0", + "IOB_PU_INT_EN_1", + "RIOB_NE4C3_0", + "RIOB_EE2BEG0_0", + "RIOB_WW4B1_0", + "RIOB_LH10_0", + "RIOB_NW4END1_0", + "RIOB_WW4B2_0", + "RIOB_EE4BEG2_0", + "RIOB_LH8_0", + "RIOB_NE2A3_0", + "RIOB_WW2END0_0", + "RIOB_WW2A0_0", + "RIOB_EE4C3_0", + "RIOB_SW4END2_0", + "RIOB_WW4B0_0", + "RIOB_LH5_0", + "RIOB_EE2A3_0", + "RIOB_WW4B3_0", + "RIOB_SE4BEG3_0", + "RIOB_EL1BEG3_0", + "RIOB_SE4BEG0_0", + "RIOB_SE4C0_0", + "RIOB_EL1BEG1_0", + "RIOB_NW4A1_0", + "RIOB_WR1END1_0", + "IOB_O0", + "RIOB_WW2END2_0", + "RIOB_EE4BEG1_0", + "RIOB_EE4BEG0_0", + "RIOB_NE4C0_0", + "IOB_O_IN0", + "RIOB_WW4C2_0", + "IOB_DIFFO_OUT0", + "RIOB_WW2A2_0", + "RIOB_WL1END3_0", + "RIOB_EE4A2_0", + "RIOB_NW2A0_0", + "RIOB_SW4END0_0", + "RIOB_WL1END1_0", + "RIOB_EE4A3_0", + "RIOB_LH4_0", + "RIOB_SW4END1_0", + "RIOB_EE4C1_0", + "RIOB_EE4B0_0", + "RIOB_EE4B2_0", + "RIOB_SE4BEG2_0", + "IOB_IBUF_DISABLE0", + "RIOB_NW4A2_0", + "RIOB_ER1BEG2_0", + "RIOB_SE2A1_0", + "IOB_T0", + "RIOB_EE4C0_0", + "RIOB_WW4C0_0", + "RIOB_EL1BEG0_0", + "RIOB_SE2A2_0", + "RIOB_NW4A3_0", + "RIOB_EE2BEG2_0", + "RIOB_EE2BEG1_0", + "RIOB_NW4A0_0", + "RIOB_NW2A3_0", + "IOB_PADOUT0", + "RIOB_SW2A1_0", + "RIOB_EE4C2_0", + "RIOB_EE2A2_0", + "IOB_DIFFI_IN0", + "RIOB_WW4A2_0" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_RIOI.json b/kintex7/tile_type_RIOI.json new file mode 100644 index 0000000..135bbcc --- /dev/null +++ b/kintex7/tile_type_RIOI.json @@ -0,0 +1,4314 @@ +{ + "tile_type": "RIOI", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "OLOGIC", + "type": "OLOGICE2", + "site_pins": { + "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", + "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", + "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", + "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", + "OFB": "RIOI_OLOGIC1_OFB", + "T1": "IOI_OLOGIC1_T1", + "D6": "IOI_OLOGIC1_D6", + "SHIFTIN2": null, + "TCE": "IOI_OLOGIC1_TCE", + "OCE": "IOI_OLOGIC1_OCE", + "SHIFTOUT2": "RIOI_OSOUT21", + "REV": null, + "OQ": "RIOI_OLOGIC1_OQ", + "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", + "D7": "IOI_OLOGIC1_D7", + "TQ": "RIOI_OLOGIC1_TQ", + "D3": "IOI_OLOGIC1_D3", + "D4": "IOI_OLOGIC1_D4", + "SR": "IOI_OLOGIC1_SR", + "CLKB": "IOI_OLOGIC1_CLKB", + "SHIFTIN1": null, + "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF", + "D2": "IOI_OLOGIC1_D2", + "CLK": "IOI_OLOGIC1_CLK", + "T4": "IOI_OLOGIC1_T4", + "T2": "IOI_OLOGIC1_T2", + "TFB": "RIOI_OLOGIC1_TFB", + "SHIFTOUT1": "RIOI_OSOUT11", + "T3": "IOI_OLOGIC1_T3", + "D1": "IOI_OLOGIC1_D1", + "D5": "IOI_OLOGIC1_D5", + "CLKDIV": "IOI_OLOGIC1_CLKDIV", + "D8": "IOI_OLOGIC1_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "ODELAY", + "type": "ODELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_ODELAY1_CNTVALUEIN1", + "OFDLY1": "RIOI_ODELAY1_OFDLY1", + "REGRST": "IOI_ODELAY1_REGRST", + "CNTVALUEIN3": "IOI_ODELAY1_CNTVALUEIN3", + "CE": "IOI_ODELAY1_CE", + "C": "IOI_ODELAY1_C", + "ODATAIN": "RIOI_ODELAY1_ODATAIN", + "OFDLY0": "RIOI_ODELAY1_OFDLY0", + "CNTVALUEIN4": "IOI_ODELAY1_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_ODELAY1_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_ODELAY1_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_ODELAY1_CNTVALUEOUT3", + "LD": "IOI_ODELAY1_LD", + "CINVCTRL": "IOI_ODELAY1_CINVCTRL", + "CNTVALUEOUT4": "IOI_ODELAY1_CNTVALUEOUT4", + "DATAOUT": "RIOI_ODELAY1_DATAOUT", + "LDPIPEEN": "IOI_ODELAY1_LDPIPEEN", + "CNTVALUEIN0": "IOI_ODELAY1_CNTVALUEIN0", + "CLKIN": "IOI_ODELAY1_CLKIN", + "INC": "IOI_ODELAY1_INC", + "CNTVALUEOUT2": "IOI_ODELAY1_CNTVALUEOUT2", + "OFDLY2": "RIOI_ODELAY1_OFDLY2", + "CNTVALUEIN2": "IOI_ODELAY1_CNTVALUEIN2" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "ILOGIC", + "type": "ILOGICE2", + "site_pins": { + "Q4": "IOI_ILOGIC1_Q4", + "D": "RIOI_ILOGIC1_D", + "Q5": "IOI_ILOGIC1_Q5", + "SHIFTIN2": "RIOI_ISIN21", + "O": "IOI_ILOGIC1_O", + "Q6": "IOI_ILOGIC1_Q6", + "Q7": "IOI_ILOGIC1_Q7", + "TFB": "RIOI_ILOGIC1_TFB", + "Q2": "IOI_ILOGIC1_Q2", + "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", + "SHIFTIN1": "RIOI_ISIN11", + "Q8": "IOI_ILOGIC1_Q8", + "CE1": "IOI_ILOGIC1_CE1", + "CE2": "IOI_ILOGIC1_CE2", + "SR": "IOI_ILOGIC1_SR", + "Q3": "IOI_ILOGIC1_Q3", + "CLK": "IOI_ILOGIC1_CLK", + "OFB": "RIOI_ILOGIC1_OFB", + "DDLY": "RIOI_ILOGIC1_DDLY", + "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", + "CLKB": "IOI_ILOGIC1_CLKB", + "REV": null, + "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "CLKDIV": "IOI_ILOGIC1_CLKDIV", + "BITSLIP": "IOI_ILOGIC1_BITSLIP", + "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", + "OCLKB": "IOI_ILOGIC1_OCLKB", + "SHIFTOUT1": "RIOI_ISOUT11", + "OCLK": "IOI_ILOGIC1_OCLK", + "Q1": "IOI_ILOGIC1_Q1", + "SHIFTOUT2": "RIOI_ISOUT21" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "OLOGIC", + "type": "OLOGICE2", + "site_pins": { + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "OFB": "RIOI_OLOGIC0_OFB", + "T1": "IOI_OLOGIC0_T1", + "D6": "IOI_OLOGIC0_D6", + "SHIFTIN2": "RIOI_OSIN20", + "TCE": "IOI_OLOGIC0_TCE", + "OCE": "IOI_OLOGIC0_OCE", + "SHIFTOUT2": "RIOI_OSOUT20", + "REV": null, + "OQ": "RIOI_OLOGIC0_OQ", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "TQ": "RIOI_OLOGIC0_TQ", + "D3": "IOI_OLOGIC0_D3", + "D4": "IOI_OLOGIC0_D4", + "SR": "IOI_OLOGIC0_SR", + "CLKB": "IOI_OLOGIC0_CLKB", + "SHIFTIN1": "RIOI_OSIN10", + "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", + "D2": "IOI_OLOGIC0_D2", + "CLK": "IOI_OLOGIC0_CLK", + "T4": "IOI_OLOGIC0_T4", + "T2": "IOI_OLOGIC0_T2", + "TFB": "RIOI_OLOGIC0_TFB", + "SHIFTOUT1": "RIOI_OSOUT10", + "T3": "IOI_OLOGIC0_T3", + "D1": "IOI_OLOGIC0_D1", + "D5": "IOI_OLOGIC0_D5", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "D8": "IOI_OLOGIC0_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "ODELAY", + "type": "ODELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_ODELAY0_CNTVALUEIN1", + "OFDLY1": "RIOI_ODELAY0_OFDLY1", + "REGRST": "IOI_ODELAY0_REGRST", + "CNTVALUEIN3": "IOI_ODELAY0_CNTVALUEIN3", + "CE": "IOI_ODELAY0_CE", + "C": "IOI_ODELAY0_C", + "ODATAIN": "RIOI_ODELAY0_ODATAIN", + "OFDLY0": "RIOI_ODELAY0_OFDLY0", + "CNTVALUEIN4": "IOI_ODELAY0_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_ODELAY0_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_ODELAY0_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_ODELAY0_CNTVALUEOUT3", + "LD": "IOI_ODELAY0_LD", + "CINVCTRL": "IOI_ODELAY0_CINVCTRL", + "CNTVALUEOUT4": "IOI_ODELAY0_CNTVALUEOUT4", + "DATAOUT": "RIOI_ODELAY0_DATAOUT", + "LDPIPEEN": "IOI_ODELAY0_LDPIPEEN", + "CNTVALUEIN0": "IOI_ODELAY0_CNTVALUEIN0", + "CLKIN": "IOI_ODELAY0_CLKIN", + "INC": "IOI_ODELAY0_INC", + "CNTVALUEOUT2": "IOI_ODELAY0_CNTVALUEOUT2", + "OFDLY2": "RIOI_ODELAY0_OFDLY2", + "CNTVALUEIN2": "IOI_ODELAY0_CNTVALUEIN2" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "ILOGIC", + "type": "ILOGICE2", + "site_pins": { + "Q4": "IOI_ILOGIC0_Q4", + "D": "RIOI_ILOGIC0_D", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN2": null, + "O": "IOI_ILOGIC0_O", + "Q6": "IOI_ILOGIC0_Q6", + "Q7": "IOI_ILOGIC0_Q7", + "TFB": "RIOI_ILOGIC0_TFB", + "Q2": "IOI_ILOGIC0_Q2", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "SHIFTIN1": null, + "Q8": "IOI_ILOGIC0_Q8", + "CE1": "IOI_ILOGIC0_CE1", + "CE2": "IOI_ILOGIC0_CE2", + "SR": "IOI_ILOGIC0_SR", + "Q3": "IOI_ILOGIC0_Q3", + "CLK": "IOI_ILOGIC0_CLK", + "OFB": "RIOI_ILOGIC0_OFB", + "DDLY": "RIOI_ILOGIC0_DDLY", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "CLKB": "IOI_ILOGIC0_CLKB", + "REV": null, + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "OCLKB": "IOI_ILOGIC0_OCLKB", + "SHIFTOUT1": "RIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "Q1": "IOI_ILOGIC0_Q1", + "SHIFTOUT2": "RIOI_ISOUT20" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IDELAY", + "type": "IDELAYE2_FINEDELAY", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", + "DATAOUT": "RIOI_IDELAY1_DATAOUT", + "IDATAIN": "RIOI_IDELAY1_IDATAIN", + "REGRST": "IOI_IDELAY1_REGRST", + "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", + "C": "IOI_IDELAY1_C", + "IFDLY0": "RIOI_IDELAY1_IFDLY0", + "DATAIN": "IOI_IDELAY1_DATAIN", + "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", + "LD": "IOI_IDELAY1_LD", + "CINVCTRL": "IOI_IDELAY1_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", + "IFDLY1": "RIOI_IDELAY1_IFDLY1", + "IFDLY2": "RIOI_IDELAY1_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", + "INC": "IOI_IDELAY1_INC", + "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", + "CE": "IOI_IDELAY1_CE", + "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "IDELAY", + "type": "IDELAYE2_FINEDELAY", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "DATAOUT": "RIOI_IDELAY0_DATAOUT", + "IDATAIN": "RIOI_IDELAY0_IDATAIN", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "C": "IOI_IDELAY0_C", + "IFDLY0": "RIOI_IDELAY0_IFDLY0", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "LD": "IOI_IDELAY0_LD", + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "IFDLY1": "RIOI_IDELAY0_IFDLY1", + "IFDLY2": "RIOI_IDELAY0_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2" + }, + "x_coord": 0 + } + ], + "wires": [ + "IOI_RCLK_DIV_CLR0_1", + "IOI_WL1END0_0", + "IOI_IDELAYCTRL_RST", + "RIOI_OLOGIC0_OQ", + "RIOI_I2GCLK_BOT1", + "IOI_IMUX12_0", + "IOI_DCI_TSTHLN", + "IOI_LH12_0", + "IOI_IDELAYCTRL_OUTN1", + "IOI_EE2BEG2_0", + "IOI_SE4C2_0", + "IOI_OLOGIC0_D5", + "IOI_IOCLK1", + "IOI_IMUX2_0", + "IOI_WW4A3_0", + "IOI_OLOGIC1_SR", + "RIOI_ODELAY0_OFDLY2", + "IOI_EL1BEG2_0", + "IOI_ILOGIC1_REV", + "IOI_EL1BEG2_1", + "IOI_SE4BEG2_0", + "IOI_IDELAYCTRL_RDY", + "IOI_EE4A0_1", + "IOI_RCLK_DIV_CE1", + "IOI_OLOGIC1_CLKB", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_LOGIC_OUTS8_1", + "IOI_SW4END2_0", + "IOI_IMUX_RC1", + "IOI_ODELAY1_CNTVALUEOUT2", + "RIOI_OSIN20", + "RIOI_IDELAY1_IDATAIN", + "IOI_IMUX39_0", + "IOI_WW4B0_0", + "IOI_ER1BEG3_1", + "IOI_BYP1_1", + "RIOI_ODELAY0_OFDLY0", + "IOI_IMUX5_1", + "IOI_PHASER_TO_IO_ICLKDIV_0", + "IOI_IMUX46_1", + "IOI_ILOGIC0_Q6", + "IOI_IMUX4_0", + "IOI_ODELAY1_CNTVALUEOUT4", + "IOI_NW4END3_1", + "IOI_ILOGIC1_OCLKB", + "IOI_FAN1_0", + "IOI_LOGIC_OUTS19_0", + "IOI_IMUX29_1", + "IOI_IMUX10_1", + "IOI_ILOGIC1_DYNCLKDIVPSEL", + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "RIOI_DIFF_TERM_INT_EN", + "IOI_ILOGIC1_Q1", + "IOI_OLOGIC1_D7", + "RIOI_IDELAY0_IFDLY0", + "IOI_LH5_1", + "IOI_ODELAY0_REGRST", + "IOI_IOCLK2", + "IOI_WW4END0_0", + "RIOI_PU_INT_EN_1", + "RIOI_KEEPER_INT_EN_1", + "IOI_WW4END2_1", + "RIOI_ODELAY1_ODATAIN", + "IOI_IMUX32_1", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS20_0", + "IOI_PHASER_TO_IO_OCLK", + "IOI_LOGIC_OUTS5_1", + "IOI_RCLK_DIV_CE0", + "RIOI_OSOUT11", + "IOI_LOGIC_OUTS9_0", + "IOI_EE2A3_1", + "IOI_EE2A1_1", + "IOI_FAN6_0", + "IOI_WW2END1_0", + "IOI_IOCLK3", + "IOI_WW2END0_1", + "IOI_SE2A3_0", + "IOI_SE4C0_1", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_EE2A0_1", + "IOI_DCI_DCIDONE", + "RIOI_DCI_T_TERM0", + "IOI_IMUX25_0", + "RIOI_OSIN11", + "IOI_LOGIC_OUTS8_0", + "IOI_ODELAY0_CLKIN", + "IOI_BLOCK_OUTS2_0", + "IOI_FAN4_1", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_NE4C2_1", + "IOI_IMUX44_0", + "IOI_IMUX29_0", + "IOI_WR1END2_1", + "IOI_OLOGIC0_CLKDIV", + "IOI_EE4C3_1", + "IOI_EE2BEG3_1", + "IOI_IMUX22_0", + "IOI_ILOGIC0_REV", + "IOI_IMUX21_0", + "IOI_IMUX15_1", + "IOI_BYP4_1", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_ODELAY0_LDPIPEEN", + "IOI_NE2A3_1", + "IOI_ILOGIC1_Q3", + "IOI_BYP2_1", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_WW4A2_0", + "IOI_NE4BEG1_0", + "IOI_LOGIC_OUTS18_1", + "IOI_OLOGIC0_D2", + "RIOI_ILOGIC0_OFB", + "IOI_ILOGIC0_Q7", + "IOI_ILOGIC1_CLK", + "IOI_ODELAY0_CNTVALUEOUT0", + "IOI_ODELAY1_INC", + "IOI_IDELAY0_REGRST", + "IOI_SE4BEG1_1", + "IOI_IMUX33_1", + "IOI_WW4END3_0", + "IOI_WR1END1_1", + "IOI_ILOGIC1_CE2", + "IOI_SE4C0_0", + "IOI_LOGIC_OUTS21_1", + "IOI_ILOGIC0_CLKDIV", + "IOI_SE2A1_0", + "IOI_IMUX8_0", + "IOI_LH5_0", + "IOI_IDELAYCTRL_OUTN65", + "IOI_NE2A1_1", + "IOI_EE4C3_0", + "IOI_LOGIC_OUTS14_1", + "IOI_OLOGIC0_CLKB", + "RIOI_OLOGIC0_CLKDIVF", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_SE4BEG0_0", + "IOI_ILOGIC0_OCLKB", + "IOI_SE4C1_1", + "IOI_IMUX47_1", + "RIOI_OLOGIC1_TFB_LOCAL", + "IOI_CLK1_1", + "IOI_IDELAY1_DATAIN", + "IOI_ODELAY1_CNTVALUEIN0", + "RIOI_ISOUT11", + "IOI_IMUX28_0", + "IOI_LOGIC_OUTS6_1", + "IOI_SE2A2_1", + "IOI_LH9_0", + "RIOI_I0", + "IOI_EE2BEG3_0", + "IOI_SE2A0_1", + "RIOI_ILOGIC0_TFB", + "IOI_IMUX40_1", + "IOI_IMUX8_1", + "IOI_ILOGIC1_DYNCLKSEL", + "IOI_EE2BEG1_1", + "IOI_SW4END1_0", + "IOI_SW4A3_0", + "IOI_IMUX16_0", + "IOI_LOGIC_OUTS0_1", + "IOI_ER1BEG0_1", + "IOI_OLOGIC0_TCE", + "IOI_NW4A1_0", + "IOI_NW2A0_0", + "IOI_IDELAY1_CNTVALUEIN4", + "IOI_EL1BEG0_0", + "IOI_ILOGIC0_CE1", + "IOI_NW4A3_0", + "IOI_IDELAY1_CNTVALUEOUT1", + "IOI_SE2A2_0", + "IOI_WL1END1_1", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_ILOGIC1_O", + "IOI_IDELAY0_INC", + "IOI_IMUX28_1", + "IOI_WW4A1_0", + "IOI_IDELAY1_CNTVALUEOUT0", + "IOI_ODELAY1_CINVCTRL", + "IOI_IMUX37_1", + "IOI_MONITOR_P", + "IOI_EE4C0_1", + "IOI_OLOGIC1_TBYTEOUT", + "IOI_LEAF_GCLK0", + "IOI_LOGIC_OUTS7_1", + "RIOI_ISIN21", + "RIOI_ODELAY1_OFDLY1", + "IOI_IMUX35_1", + "IOI_WW2END3_0", + "IOI_IDELAY1_CNTVALUEOUT4", + "IOI_EE4C2_1", + "IOI_NE4BEG2_1", + "IOI_SE4BEG3_0", + "IOI_ILOGIC1_Q6", + "IOI_ILOGIC0_Q4", + "IOI_SE4BEG0_1", + "IOI_RCLK_DIV_CE2_1", + "RIOI_IDELAY1_IFDLY1", + "IOI_LOGIC_OUTS0_0", + "IOI_BYP4_0", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "RIOI_PD_INT_EN_1", + "IOI_OLOGIC0_D6", + "IOI_WL1END3_1", + "IOI_DCI_TSTCLK", + "IOI_WW4C2_1", + "IOI_WW4B1_0", + "IOI_PHASER_TO_IO_OCLK_0", + "IOI_PHASER_TO_IO_OCLKDIV_0", + "IOI_IMUX45_0", + "IOI_ILOGIC0_Q2", + "IOI_SW2A0_1", + "IOI_SE4BEG1_0", + "IOI_WW2A1_0", + "IOI_LOGIC_OUTS12_0", + "IOI_ILOGIC0_OCLK", + "IOI_EE4B3_0", + "IOI_WW4END1_1", + "IOI_IMUX19_0", + "IOI_NE4C2_0", + "IOI_OLOGIC0_CLK", + "IOI_WL1END1_0", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_IMUX_RC2", + "IOI_IMUX35_0", + "IOI_IMUX2_1", + "IOI_WW4A0_0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_IMUX15_0", + "IOI_WL1END2_0", + "IOI_WW2END3_1", + "IOI_IMUX41_1", + "IOI_WW4END1_0", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS14_0", + "IOI_OLOGIC0_D7", + "IOI_IMUX31_1", + "IOI_SW2A3_0", + "RIOI_IDELAY1_IFDLY2", + "IOI_OLOGIC1_TBYTEIN", + "IOI_SW4A2_1", + "IOI_IDELAY1_LDPIPEEN", + "IOI_IMUX6_1", + "IOI_IMUX_RC0", + "IOI_IMUX9_0", + "IOI_WW2END2_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_EE4BEG2_1", + "IOI_FAN6_1", + "IOI_ODELAY1_REGRST", + "IOI_IMUX11_0", + "IOI_RCLK_FORIO1", + "IOI_SW4A0_1", + "RIOI_OLOGIC0_TFB_LOCAL", + "IOI_WW4C0_1", + "RIOI_IBUF_DISABLE0", + "IOI_IMUX30_1", + "IOI_SE2A3_1", + "IOI_SW4A1_1", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OLOGIC1_D4", + "IOI_WW2A1_1", + "IOI_RCLK_DIV_CLR0", + "IOI_NW2A3_0", + "IOI_OLOGIC1_OCE", + "IOI_IMUX40_0", + "IOI_SW4END0_1", + "IOI_SW4END1_1", + "IOI_ILOGIC1_Q4", + "IOI_LOGIC_OUTS16_1", + "IOI_IMUX20_1", + "IOI_NE4C1_1", + "IOI_ILOGIC1_CLKB", + "IOI_RCLK_DIV_CE3", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_LEAF_GCLK1", + "IOI_ILOGIC0_Q1", + "IOI_EE4BEG0_0", + "RIOI_OLOGIC1_OQ", + "RIOI_ODELAY1_DATAOUT", + "IOI_IMUX46_0", + "IOI_IMUX45_1", + "IOI_EE4BEG3_1", + "IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IMUX38_1", + "RIOI_OLOGIC0_TQ", + "IOI_MONITOR_N", + "IOI_LEAF_GCLK5", + "IOI_ODELAY0_CNTVALUEIN2", + "IOI_WW4A3_1", + "RIOI_OSOUT21", + "IOI_NW4END3_0", + "IOI_WW2A3_1", + "IOI_SE4BEG2_1", + "IOI_BYP5_1", + "IOI_ODELAY0_CINVCTRL", + "IOI_OLOGIC0_D1", + "IOI_WW4A2_1", + "IOI_ODELAY1_CE", + "IOI_WW4C0_0", + "IOI_FAN1_1", + "IOI_IMUX26_0", + "IOI_ODELAY0_LD", + "IOI_EE4B2_0", + "IOI_NW4A0_0", + "IOI_SE2A0_0", + "IOI_EE4C0_0", + "IOI_LOGIC_OUTS21_0", + "RIOI_IBUF_DISABLE1", + "IOI_IDELAY0_LD", + "IOI_IMUX23_0", + "IOI_WR1END0_0", + "IOI_WW4END3_1", + "IOI_ODELAY1_CNTVALUEIN1", + "RIOI_OSIN10", + "IOI_LOGIC_OUTS15_0", + "IOI_OLOGIC1_D1", + "IOI_LOGIC_OUTS23_0", + "IOI_WW2END2_1", + "IOI_DCI_TSTRST", + "IOI_IMUX22_1", + "IOI_LOGIC_OUTS1_1", + "IOI_EE4B1_0", + "IOI_IMUX7_0", + "IOI_EE4A2_1", + "IOI_BLOCK_OUTS1_0", + "IOI_IMUX42_0", + "IOI_SW2A2_1", + "IOI_WW4C1_0", + "IOI_OLOGIC0_REV", + "IOI_BYP0_1", + "IOI_IMUX39_1", + "RIOI_ODELAY0_ODATAIN", + "IOI_NW4A0_1", + "IOI_BYP6_0", + "IOI_IMUX13_1", + "IOI_OLOGIC0_D4", + "RIOI_DCI_T_TERM1", + "IOI_ODELAY0_CNTVALUEIN3", + "RIOI_I1", + "IOI_IMUX24_1", + "IOI_ILOGIC0_CLKDIVP", + "RIOI_ISIN11", + "RIOI_IDELAY0_IFDLY1", + "IOI_IMUX13_0", + "IOI_RCLK_DIV_CE2", + "IOI_IDELAY1_REGRST", + "IOI_WR1END3_1", + "RIOI_OLOGIC1_TQ", + "RIOI_KEEPER_INT_EN_0", + "IOI_IDELAY1_C", + "IOI_IDELAY1_LD", + "IOI_IMUX47_0", + "IOI_ILOGIC0_O", + "IOI_ILOGIC1_Q8", + "IOI_BYP0_0", + "IOI_IMUX27_0", + "IOI_SW4END3_1", + "IOI_LH1_0", + "RIOI_IDELAY1_IFDLY0", + "IOI_SW4A0_0", + "IOI_SE4BEG3_1", + "IOI_IDELAY1_CNTVALUEIN0", + "IOI_SW4END0_0", + "IOI_WW4B1_1", + "IOI_IDELAY0_DATAIN", + "IOI_SW4A2_0", + "IOI_LOGIC_OUTS10_0", + "IOI_CLK0_1", + "IOI_IMUX11_1", + "IOI_WW4C1_1", + "IOI_OLOGIC0_T2", + "IOI_BYP6_1", + "IOI_LOGIC_OUTS2_0", + "IOI_BLOCK_OUTS0_0", + "IOI_NW4A3_1", + "IOI_ODELAY0_CE", + "IOI_ILOGIC1_BITSLIP", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_OLOGIC1_CLK", + "IOI_ILOGIC1_CLKDIV", + "IOI_IMUX20_0", + "IOI_LOGIC_OUTS10_1", + "RIOI_IDELAY0_DATAOUT", + "IOI_IDELAY0_LDPIPEEN", + "IOI_LOGIC_OUTS6_0", + "IOI_EL1BEG3_1", + "IOI_ILOGIC0_CLKB", + "IOI_LH6_0", + "IOI_EE4A2_0", + "IOI_LOGIC_OUTS22_0", + "IOI_NW2A1_0", + "IOI_WW2A0_0", + "IOI_PHASER_TO_IO_OCLK1X_90", + "IOI_ILOGIC1_Q5", + "IOI_CTRL0_0", + "IOI_IDELAY0_CE", + "IOI_ILOGIC0_BITSLIP", + "IOI_IMUX14_0", + "IOI_LOGIC_OUTS3_0", + "IOI_IMUX4_1", + "IOI_IMUX3_1", + "IOI_IMUX34_0", + "IOI_WL1END3_0", + "IOI_OLOGIC0_D8", + "IOI_IMUX17_1", + "RIOI_OLOGIC1_TFB", + "IOI_OLOGIC1_TCE", + "IOI_LOGIC_OUTS4_1", + "IOI_OLOGIC0_T3", + "IOI_LOGIC_OUTS5_0", + "IOI_ILOGIC0_Q5", + "RIOI_IDELAY0_IDATAIN", + "IOI_IMUX43_1", + "IOI_ODELAY0_C", + "IOI_EE2BEG2_1", + "IOI_LOGIC_OUTS22_1", + "IOI_FAN3_0", + "IOI_SW2A3_1", + "IOI_LOGIC_OUTS13_0", + "IOI_ODELAY1_LD", + "IOI_IDELAY1_CNTVALUEOUT3", + "IOI_ILOGIC1_Q2", + "IOI_ODELAY1_CNTVALUEIN3", + "IOI_EE4A3_1", + "IOI_WR1END3_0", + "IOI_IDELAY0_C", + "IOI_WW2END0_0", + "IOI_FAN0_1", + "IOI_ILOGIC0_Q3", + "IOI_IDELAY0_CINVCTRL", + "IOI_NW2A1_1", + "IOI_IMUX26_1", + "IOI_EE2BEG1_0", + "IOI_OLOGIC1_IOCLKGLITCH", + "IOI_FAN3_1", + "IOI_NE2A0_1", + "IOI_WR1END2_0", + "IOI_ODELAY1_CNTVALUEIN2", + "IOI_CTRL1_1", + "IOI_ODELAY0_INC", + "IOI_IMUX0_0", + "IOI_BYP3_1", + "IOI_IMUX19_1", + "IOI_LH7_0", + "IOI_SE4C2_1", + "IOI_BLOCK_OUTS2_1", + "IOI_WW4C2_0", + "IOI_NW2A2_0", + "IOI_NW4END2_1", + "IOI_NE4BEG1_1", + "IOI_NW4A1_1", + "IOI_IMUX3_0", + "IOI_OLOGIC1_CLKDIV", + "IOI_LEAF_GCLK4", + "RIOI_PU_INT_EN_0", + "IOI_WW4C3_0", + "IOI_EL1BEG1_0", + "IOI_IMUX0_1", + "IOI_WR1END0_1", + "IOI_LH4_1", + "IOI_IDELAY1_CE", + "IOI_NE4C3_1", + "IOI_BLOCK_OUTS0_1", + "IOI_IDELAY1_CINVCTRL", + "IOI_LH3_0", + "IOI_NE2A1_0", + "RIOI_OLOGIC0_OFB", + "IOI_IMUX43_0", + "IOI_RCLK_DIV_CLR2", + "IOI_NE4BEG3_1", + "IOI_IMUX_RC3", + "RIOI_OSIN21", + "IOI_LOGIC_OUTS9_1", + "IOI_BLOCK_OUTS3_1", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_OLOGIC1_T3", + "IOI_NE4BEG0_0", + "IOI_NE4C1_0", + "IOI_IMUX38_0", + "IOI_LH10_1", + "IOI_IMUX34_1", + "IOI_SE4C3_0", + "IOI_ILOGIC1_Q7", + "IOI_EL1BEG3_0", + "IOI_LOGIC_OUTS11_0", + "IOI_EE4BEG1_0", + "IOI_FAN0_0", + "IOI_FAN2_1", + "IOI_IDELAY1_CNTVALUEIN2", + "IOI_IMUX10_0", + "IOI_EE4B3_1", + "RIOI_O0", + "IOI_IMUX44_1", + "RIOI_ISOUT10", + "IOI_IMUX31_0", + "IOI_WW2END1_1", + "IOI_ER1BEG1_0", + "RIOI_I2GCLK_TOP0", + "IOI_NW2A2_1", + "RIOI_ILOGIC1_DDLY", + "IOI_WW4B3_0", + "IOI_RCLK_FORIO0", + "RIOI_ILOGIC0_DDLY", + "IOI_SE4C1_0", + "IOI_ILOGIC0_CE2", + "IOI_ODELAY1_CNTVALUEOUT0", + "IOI_IMUX16_1", + "IOI_FAN5_1", + "IOI_RCLK_DIV_CE3_1", + "IOI_IMUX42_1", + "IOI_FAN4_0", + "IOI_OLOGIC1_D2", + "IOI_IMUX17_0", + "RIOI_ILOGIC1_D", + "IOI_WW4C3_1", + "IOI_OLOGIC0_CLKDIVB", + "IOI_LH12_1", + "IOI_EE4B1_1", + "IOI_TBYTEIN", + "RIOI_ISIN20", + "IOI_NW4A2_0", + "IOI_LH2_1", + "IOI_EE4B0_0", + "RIOI_ISOUT21", + "RIOI_ODELAY0_OFDLY1", + "IOI_EE4BEG0_1", + "IOI_OLOGIC1_REV", + "IOI_WW4B2_0", + "IOI_NE2A0_0", + "IOI_FAN5_0", + "IOI_IMUX36_0", + "IOI_NW4A2_1", + "IOI_IMUX33_0", + "IOI_BYP1_0", + "IOI_OLOGIC1_T2", + "IOI_RCLK_FORIO2", + "IOI_EE2A3_0", + "IOI_RCLK_DIV_CLR1", + "IOI_IDELAY1_CNTVALUEOUT2", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_NE2A2_1", + "IOI_WW2A2_0", + "IOI_EE4A1_1", + "IOI_EE4B2_1", + "IOI_LEAF_GCLK3", + "IOI_NW4END1_1", + "IOI_ODELAY1_CNTVALUEOUT1", + "IOI_WL1END2_1", + "IOI_LH3_1", + "IOI_LH6_1", + "IOI_RCLK_DIV_CLR3", + "RIOI_T1", + "RIOI_ODELAY0_DATAOUT", + "IOI_EE4A0_0", + "IOI_CLK0_0", + "IOI_IMUX30_0", + "IOI_LH10_0", + "IOI_OLOGIC1_CLKDIVFB", + "RIOI_T0", + "IOI_BYP5_0", + "IOI_BLOCK_OUTS3_0", + "IOI_SW4A3_1", + "IOI_CLK1_0", + "RIOI_I2GCLK_TOP1", + "IOI_LOGIC_OUTS2_1", + "IOI_ILOGIC1_CLKDIVP", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "IOI_EL1BEG0_1", + "IOI_NE4C0_1", + "IOI_WL1END0_1", + "IOI_IMUX32_0", + "RIOI_PD_INT_EN_0", + "IOI_ODELAY1_CNTVALUEOUT3", + "IOI_LOGIC_OUTS3_1", + "IOI_EE4BEG1_1", + "IOI_IMUX7_1", + "IOI_WW4B0_1", + "IOI_LOGIC_OUTS4_0", + "IOI_LOGIC_OUTS12_1", + "IOI_SW2A1_1", + "IOI_ILOGIC1_CE1", + "IOI_WW4END0_1", + "IOI_IMUX18_0", + "RIOI_IDELAY0_IFDLY2", + "IOI_RCLK_FORIO3", + "IOI_ODELAY1_LDPIPEEN", + "IOI_WW2A0_1", + "IOI_ER1BEG2_1", + "RIOI_ILOGIC1_OFB", + "IOI_IMUX25_1", + "IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_LH11_1", + "IOI_OLOGIC1_D6", + "IOI_LOGIC_OUTS15_1", + "IOI_IMUX1_1", + "IOI_IMUX12_1", + "IOI_SE4C3_1", + "IOI_WR1END1_0", + "IOI_LH8_1", + "IOI_EE4A1_0", + "IOI_SE2A1_1", + "IOI_SW4END3_0", + "IOI_LH1_1", + "IOI_LH8_0", + "IOI_DCI_TSTRST0", + "IOI_LOGIC_OUTS23_1", + "IOI_LH2_0", + "IOI_BYP7_1", + "IOI_OCLKM_0", + "IOI_SW4END2_1", + "IOI_EE4A3_0", + "IOI_IMUX1_0", + "IOI_BYP3_0", + "IOI_NE2A2_0", + "IOI_ER1BEG0_0", + "RIOI_OSOUT20", + "IOI_NW4END2_0", + "IOI_ER1BEG3_0", + "IOI_EE2A2_1", + "RIOI_IBUF1", + "IOI_FAN2_0", + "IOI_SW2A1_0", + "IOI_ODELAY1_CLKIN", + "IOI_CTRL1_0", + "IOI_WW2A2_1", + "IOI_OLOGIC0_OCE", + "IOI_OCLKM_1", + "IOI_IMUX41_0", + "IOI_NW2A0_1", + "IOI_IMUX24_0", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WW2A3_0", + "IOI_OLOGIC1_D3", + "RIOI_OLOGIC0_TFB", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_LH9_1", + "RIOI_IBUF0", + "IOI_IMUX5_0", + "IOI_OLOGIC1_T4", + "IOI_LOGIC_OUTS20_1", + "IOI_IMUX9_1", + "IOI_SW4A1_0", + "RIOI_OLOGIC1_OFB", + "IOI_LH11_0", + "IOI_OLOGIC1_T1", + "IOI_EE4C1_0", + "IOI_IDELAY1_CNTVALUEIN1", + "IOI_BYP2_0", + "RIOI_ILOGIC1_TFB", + "IOI_RCLK_DIV_CLR1_1", + "RIOI_O1", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_WW4B3_1", + "IOI_ODELAY0_CNTVALUEIN0", + "IOI_EE4C1_1", + "IOI_WW4B2_1", + "IOI_IMUX36_1", + "RIOI_ILOGIC0_D", + "IOI_BLOCK_OUTS1_1", + "RIOI_ISIN10", + "IOI_LOGIC_OUTS18_0", + "IOI_IMUX27_1", + "IOI_EL1BEG1_1", + "RIOI_ISOUT20", + "IOI_LOGIC_OUTS16_0", + "IOI_PHASER_TO_IO_ICLKDIV", + "IOI_LOGIC_OUTS1_0", + "RIOI_OLOGIC1_CLKDIVF", + "IOI_EE4BEG3_0", + "IOI_ER1BEG2_0", + "IOI_DCI_TSTHLP", + "IOI_EE4BEG2_0", + "IOI_EE2A0_0", + "IOI_WW4A0_1", + "IOI_LOGIC_OUTS11_1", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_IDELAY0_CNTVALUEIN0", + "IOI_IOCLK0", + "IOI_IMUX37_0", + "IOI_OLOGIC1_D8", + "IOI_ODELAY1_CNTVALUEIN4", + "RIOI_OSOUT10", + "IOI_LOGIC_OUTS7_0", + "IOI_NE4BEG2_0", + "IOI_EE2BEG0_0", + "IOI_ILOGIC1_SR", + "RIOI_IDELAY1_DATAOUT", + "IOI_OLOGIC0_T1", + "IOI_OLOGIC1_CLKDIVB", + "RIOI_ODELAY1_OFDLY0", + "IOI_NE4C3_0", + "IOI_ILOGIC0_SR", + "IOI_ODELAY1_C", + "IOI_EE2A2_0", + "IOI_IMUX6_0", + "IOI_LOGIC_OUTS13_1", + "IOI_LH7_1", + "IOI_NW4END0_0", + "IOI_NE2A3_0", + "IOI_NW2A3_1", + "IOI_LOGIC_OUTS19_1", + "IOI_LEAF_GCLK2", + "IOI_OLOGIC0_SR", + "IOI_EE2BEG0_1", + "RIOI_ODELAY1_OFDLY2", + "IOI_NE4BEG3_0", + "IOI_INT_DCI_EN", + "IOI_ILOGIC0_Q8", + "IOI_SW2A0_0", + "IOI_ODELAY0_CNTVALUEIN4", + "IOI_WW4END2_0", + "IOI_FAN7_1", + "IOI_IMUX23_1", + "IOI_BYP7_0", + "IOI_IMUX18_1", + "IOI_ILOGIC1_DYNCLKDIVSEL", + "IOI_NW4END0_1", + "IOI_OCLK_1", + "IOI_IMUX21_1", + "IOI_FAN7_0", + "IOI_NW4END1_0", + "IOI_IDELAY1_CNTVALUEIN3", + "IOI_ILOGIC1_OCLK", + "IOI_LOGIC_OUTS17_0", + "IOI_NE4BEG0_1", + "IOI_PHASER_TO_IO_ICLK_0", + "IOI_EE4B0_1", + "IOI_OLOGIC0_D3", + "IOI_LOGIC_OUTS17_1", + "IOI_EE2A1_0", + "IOI_WW4A1_1", + "IOI_OLOGIC0_TBYTEIN", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_ER1BEG1_1", + "IOI_CTRL0_1", + "IOI_IMUX14_1", + "IOI_OLOGIC1_D5", + "IOI_OCLK_0", + "IOI_IDELAY1_INC", + "IOI_NE4C0_0", + "IOI_LH4_0", + "IOI_OLOGIC0_T4" + ], + "pips": { + "RIOI.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_CTRL1_1->IOI_ILOGIC0_SR": { + "src_wire": "IOI_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX3_1->IOI_ODELAY0_INC": { + "src_wire": "IOI_IMUX3_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP2_0->IOI_ODELAY1_CINVCTRL": { + "src_wire": "IOI_BYP2_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX31_0->>IOI_OCLKM_1": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX26_0->IOI_IDELAY1_INC": { + "src_wire": "IOI_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_ODELAY1_DATAOUT->RIOI_O1": { + "src_wire": "RIOI_ODELAY1_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_O1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { + "src_wire": "RIOI_OLOGIC0_TQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { + "src_wire": "IOI_OLOGIC1_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP7_0->RIOI_IDELAY1_IFDLY2": { + "src_wire": "IOI_BYP7_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC1_OQ->>RIOI_O1": { + "src_wire": "RIOI_OLOGIC1_OQ", + "is_pseudo": "0", + "dst_wire": "RIOI_O1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { + "src_wire": "RIOI_OLOGIC1_TQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { + "src_wire": "IOI_ILOGIC1_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { + "src_wire": "IOI_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ODELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS12_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS12_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX47_1->IOI_OLOGIC0_D8": { + "src_wire": "IOI_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX27_0->IOI_ODELAY1_LDPIPEEN": { + "src_wire": "IOI_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX3_0->IOI_ODELAY1_INC": { + "src_wire": "IOI_IMUX3_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_FAN5_0->RIOI_IDELAY1_IFDLY1": { + "src_wire": "IOI_FAN5_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_I1->RIOI_IDELAY1_IDATAIN": { + "src_wire": "RIOI_I1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { + "src_wire": "IOI_ILOGIC1_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { + "src_wire": "IOI_ILOGIC0_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC0_OFB->RIOI_ODELAY0_ODATAIN": { + "src_wire": "RIOI_OLOGIC0_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_ODATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE3_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP7_1->RIOI_IDELAY0_IFDLY2": { + "src_wire": "IOI_BYP7_1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC0_OQ->>RIOI_O0": { + "src_wire": "RIOI_OLOGIC0_OQ", + "is_pseudo": "0", + "dst_wire": "RIOI_O0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_IBUF0->RIOI_I0": { + "src_wire": "RIOI_IBUF0", + "is_pseudo": "0", + "dst_wire": "RIOI_I0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX26_1->IOI_IDELAY0_INC": { + "src_wire": "IOI_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { + "src_wire": "IOI_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ODELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS17_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS17_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_CLK0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX28_1->IOI_ODELAY0_LD": { + "src_wire": "IOI_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { + "src_wire": "IOI_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { + "src_wire": "RIOI_IDELAY0_IDATAIN", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ODELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS21_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS21_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX19_1->IOI_ODELAY0_CNTVALUEIN3": { + "src_wire": "IOI_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX32_1->IOI_IDELAY0_CE": { + "src_wire": "IOI_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { + "src_wire": "IOI_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX15_0->IOI_OLOGIC1_T1": { + "src_wire": "IOI_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX23_0->IOI_ODELAY1_CNTVALUEIN0": { + "src_wire": "IOI_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAYCTRL_UPPULSEOUT->IOI_LOGIC_OUTS16_0": { + "src_wire": "IOI_IDELAYCTRL_UPPULSEOUT", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS16_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX30_1->IOI_IDELAY0_LD": { + "src_wire": "IOI_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { + "src_wire": "IOI_ILOGIC0_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX42_1->IOI_OLOGIC0_D4": { + "src_wire": "IOI_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX15_1->IOI_OLOGIC0_T1": { + "src_wire": "IOI_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ODELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS6_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS6_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { + "src_wire": "IOI_ILOGIC0_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { + "src_wire": "IOI_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX34_1->IOI_OLOGIC0_D1": { + "src_wire": "IOI_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { + "src_wire": "IOI_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX2_0->IOI_ODELAY1_CE": { + "src_wire": "IOI_IMUX2_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX7_0->IOI_OLOGIC1_T2": { + "src_wire": "IOI_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX13_0->IOI_OLOGIC1_T3": { + "src_wire": "IOI_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX2_1->IOI_ODELAY0_CE": { + "src_wire": "IOI_IMUX2_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP0_1->RIOI_ODELAY0_OFDLY0": { + "src_wire": "IOI_BYP0_1", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_OFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC1_OFB->RIOI_ODELAY1_ODATAIN": { + "src_wire": "RIOI_OLOGIC1_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY1_ODATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX30_0->IOI_IDELAY1_LD": { + "src_wire": "IOI_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { + "src_wire": "IOI_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLK_1->IOI_OLOGIC1_CLK": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX31_1->>IOI_OCLK_0": { + "src_wire": "IOI_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX31_1->>IOI_OCLKM_0": { + "src_wire": "IOI_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX44_0->IOI_OLOGIC1_D3": { + "src_wire": "IOI_IMUX44_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "src_wire": "RIOI_ILOGIC0_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { + "src_wire": "IOI_ILOGIC0_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { + "src_wire": "IOI_TBYTEIN", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_CLK1_0->IOI_ODELAY1_C": { + "src_wire": "IOI_CLK1_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { + "src_wire": "IOI_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_CTRL0_1->IOI_OLOGIC0_SR": { + "src_wire": "IOI_CTRL0_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ODELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS17_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS17_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC0_O->RIOI_I2GCLK_TOP0": { + "src_wire": "IOI_ILOGIC0_O", + "is_pseudo": "0", + "dst_wire": "RIOI_I2GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { + "src_wire": "RIOI_OLOGIC1_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX40_1->IOI_OLOGIC0_D2": { + "src_wire": "IOI_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { + "src_wire": "IOI_ILOGIC0_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_IDELAY1_IDATAIN->>RIOI_IDELAY1_DATAOUT": { + "src_wire": "RIOI_IDELAY1_IDATAIN", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY1_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAYCTRL_OUTN1->IOI_LOGIC_OUTS13_1": { + "src_wire": "IOI_IDELAYCTRL_OUTN1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS13_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP5_1->RIOI_ODELAY0_OFDLY2": { + "src_wire": "IOI_BYP5_1", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_OFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ODELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS4_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS4_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAYCTRL_OUTN65->IOI_LOGIC_OUTS16_1": { + "src_wire": "IOI_IDELAYCTRL_OUTN65", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS16_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP0_0->RIOI_ODELAY1_OFDLY0": { + "src_wire": "IOI_BYP0_0", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY1_OFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { + "src_wire": "IOI_ILOGIC0_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { + "src_wire": "IOI_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX17_1->IOI_ODELAY0_CNTVALUEIN2": { + "src_wire": "IOI_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX18_1->IOI_ODELAY0_CNTVALUEIN4": { + "src_wire": "IOI_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { + "src_wire": "IOI_ILOGIC1_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { + "src_wire": "RIOI_OLOGIC0_OQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX11_1->IOI_ODELAY0_REGRST": { + "src_wire": "IOI_IMUX11_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLKM_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLK_0->IOI_ODELAY0_CLKIN": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CLKIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { + "src_wire": "IOI_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { + "src_wire": "IOI_OLOGIC1_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX7_1->IOI_OLOGIC0_T2": { + "src_wire": "IOI_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { + "src_wire": "IOI_CLK0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP4_0->IOI_IMUX_RC1": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { + "src_wire": "RIOI_ILOGIC1_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { + "src_wire": "RIOI_OLOGIC0_TFB", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAYCTRL_RDY->IOI_LOGIC_OUTS22_1": { + "src_wire": "IOI_IDELAYCTRL_RDY", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS22_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX42_0->IOI_OLOGIC1_D4": { + "src_wire": "IOI_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX44_1->IOI_OLOGIC0_D3": { + "src_wire": "IOI_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX18_0->IOI_ODELAY1_CNTVALUEIN4": { + "src_wire": "IOI_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_I0->RIOI_ILOGIC0_D": { + "src_wire": "RIOI_I0", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_D", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_IBUF1->RIOI_I1": { + "src_wire": "RIOI_IBUF1", + "is_pseudo": "0", + "dst_wire": "RIOI_I1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX27_1->IOI_ODELAY0_LDPIPEEN": { + "src_wire": "IOI_IMUX27_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { + "src_wire": "RIOI_OLOGIC0_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { + "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX21_1->IOI_OLOGIC0_T4": { + "src_wire": "IOI_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { + "src_wire": "IOI_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX24_0->IOI_IDELAYCTRL_RST": { + "src_wire": "IOI_IMUX24_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAYCTRL_RST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP3_0->IOI_IMUX_RC0": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX40_0->IOI_OLOGIC1_D2": { + "src_wire": "IOI_IMUX40_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ODELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS12_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS12_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { + "src_wire": "IOI_ILOGIC1_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "src_wire": "IOI_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX32_0->IOI_IDELAY1_CE": { + "src_wire": "IOI_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OSOUT11->RIOI_OSIN10": { + "src_wire": "RIOI_OSOUT11", + "is_pseudo": "0", + "dst_wire": "RIOI_OSIN10", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLK_1->IOI_ODELAY1_CLKIN": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CLKIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP5_0->RIOI_ODELAY1_OFDLY2": { + "src_wire": "IOI_BYP5_0", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY1_OFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { + "src_wire": "IOI_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX45_1->IOI_OLOGIC0_D6": { + "src_wire": "IOI_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { + "src_wire": "RIOI_IDELAY0_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX46_0->IOI_OLOGIC1_D7": { + "src_wire": "IOI_IMUX46_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D7", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP1_0->RIOI_ODELAY1_OFDLY1": { + "src_wire": "IOI_BYP1_0", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY1_OFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX43_1->IOI_OLOGIC0_D5": { + "src_wire": "IOI_IMUX43_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX28_0->IOI_ODELAY1_LD": { + "src_wire": "IOI_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { + "src_wire": "IOI_ILOGIC0_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX13_1->IOI_OLOGIC0_T3": { + "src_wire": "IOI_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_FAN5_1->RIOI_IDELAY0_IFDLY1": { + "src_wire": "IOI_FAN5_1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ODELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS21_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS21_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { + "src_wire": "IOI_OLOGIC1_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR1_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { + "src_wire": "RIOI_OLOGIC1_TFB", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OSOUT21->RIOI_OSIN20": { + "src_wire": "RIOI_OSOUT21", + "is_pseudo": "0", + "dst_wire": "RIOI_OSIN20", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "src_wire": "RIOI_ILOGIC0_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { + "src_wire": "IOI_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { + "src_wire": "RIOI_OLOGIC1_OQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_CLK1_1->IOI_ODELAY0_C": { + "src_wire": "IOI_CLK1_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE2_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX47_0->IOI_OLOGIC1_D8": { + "src_wire": "IOI_IMUX47_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D8", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { + "src_wire": "IOI_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { + "src_wire": "IOI_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLKM_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX16_1->IOI_ODELAY0_CNTVALUEIN1": { + "src_wire": "IOI_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { + "src_wire": "IOI_ILOGIC1_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX45_0->IOI_OLOGIC1_D6": { + "src_wire": "IOI_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D6", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX43_0->IOI_OLOGIC1_D5": { + "src_wire": "IOI_IMUX43_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D5", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { + "src_wire": "IOI_OLOGIC1_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR0_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { + "src_wire": "IOI_TBYTEIN", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX17_0->IOI_ODELAY1_CNTVALUEIN2": { + "src_wire": "IOI_IMUX17_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX19_0->IOI_ODELAY1_CNTVALUEIN3": { + "src_wire": "IOI_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_CLK1_1->IOI_IDELAY0_C": { + "src_wire": "IOI_CLK1_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { + "src_wire": "IOI_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { + "src_wire": "IOI_ILOGIC1_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { + "src_wire": "IOI_ILOGIC1_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ODELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS4_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS4_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { + "src_wire": "IOI_BYP6_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP2_1->IOI_ODELAY0_CINVCTRL": { + "src_wire": "IOI_BYP2_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { + "src_wire": "IOI_IMUX9_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO2->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC1_TQ->>RIOI_T1": { + "src_wire": "RIOI_OLOGIC1_TQ", + "is_pseudo": "0", + "dst_wire": "RIOI_T1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX21_0->IOI_OLOGIC1_T4": { + "src_wire": "IOI_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ODELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS6_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS6_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_ISOUT20->RIOI_ISIN21": { + "src_wire": "RIOI_ISOUT20", + "is_pseudo": "0", + "dst_wire": "RIOI_ISIN21", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { + "src_wire": "IOI_ILOGIC0_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP3_1->IOI_IMUX_RC3": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { + "src_wire": "IOI_ILOGIC0_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_ISOUT10->RIOI_ISIN11": { + "src_wire": "RIOI_ISOUT10", + "is_pseudo": "0", + "dst_wire": "RIOI_ISIN11", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_CTRL1_0->IOI_ILOGIC1_SR": { + "src_wire": "IOI_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { + "src_wire": "IOI_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX34_0->IOI_OLOGIC1_D1": { + "src_wire": "IOI_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_FAN4_1->RIOI_IDELAY0_IFDLY0": { + "src_wire": "IOI_FAN4_1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { + "src_wire": "IOI_BYP6_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX16_0->IOI_ODELAY1_CNTVALUEIN1": { + "src_wire": "IOI_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX23_1->IOI_ODELAY0_CNTVALUEIN0": { + "src_wire": "IOI_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { + "src_wire": "RIOI_ILOGIC1_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { + "src_wire": "IOI_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP1_1->RIOI_ODELAY0_OFDLY1": { + "src_wire": "IOI_BYP1_1", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_OFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_OLOGIC0_TQ->>RIOI_T0": { + "src_wire": "RIOI_OLOGIC0_TQ", + "is_pseudo": "0", + "dst_wire": "RIOI_T0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_CLK1_0->IOI_IDELAY1_C": { + "src_wire": "IOI_CLK1_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAYCTRL_DNPULSEOUT->IOI_LOGIC_OUTS13_0": { + "src_wire": "IOI_IDELAYCTRL_DNPULSEOUT", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS13_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_I1->RIOI_ILOGIC1_D": { + "src_wire": "RIOI_I1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_D", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_I0->RIOI_IDELAY0_IDATAIN": { + "src_wire": "RIOI_I0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_ODELAY0_DATAOUT->RIOI_O0": { + "src_wire": "RIOI_ODELAY0_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_O0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP4_1->IOI_IMUX_RC2": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_CTRL0_0->IOI_OLOGIC1_SR": { + "src_wire": "IOI_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IOCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX31_0->>IOI_OCLK_1": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_FAN4_0->RIOI_IDELAY1_IFDLY0": { + "src_wire": "IOI_FAN4_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.RIOI_IDELAY1_DATAOUT->RIOI_ILOGIC1_DDLY": { + "src_wire": "RIOI_IDELAY1_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO1->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { + "src_wire": "IOI_ILOGIC1_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { + "src_wire": "IOI_ILOGIC1_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX46_1->IOI_OLOGIC0_D7": { + "src_wire": "IOI_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_IMUX11_0->IOI_ODELAY1_REGRST": { + "src_wire": "IOI_IMUX11_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_RCLK_FORIO3->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_RIOI_SING.json b/kintex7/tile_type_RIOI_SING.json new file mode 100644 index 0000000..4203771 --- /dev/null +++ b/kintex7/tile_type_RIOI_SING.json @@ -0,0 +1,2071 @@ +{ + "tile_type": "RIOI_SING", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "OLOGIC", + "type": "OLOGICE2", + "site_pins": { + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "OFB": "RIOI_OLOGIC0_OFB", + "T1": "IOI_OLOGIC0_T1", + "D6": "IOI_OLOGIC0_D6", + "SHIFTIN2": null, + "TCE": "IOI_OLOGIC0_TCE", + "OCE": "IOI_OLOGIC0_OCE", + "SHIFTOUT2": "RIOI_OSOUT20", + "REV": null, + "OQ": "RIOI_OLOGIC0_OQ", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "TQ": "RIOI_OLOGIC0_TQ", + "D3": "IOI_OLOGIC0_D3", + "D4": "IOI_OLOGIC0_D4", + "SR": "IOI_OLOGIC0_SR", + "CLKB": "IOI_OLOGIC0_CLKB", + "SHIFTIN1": null, + "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", + "D2": "IOI_OLOGIC0_D2", + "CLK": "IOI_OLOGIC0_CLK", + "T4": "IOI_OLOGIC0_T4", + "T2": "IOI_OLOGIC0_T2", + "TFB": "RIOI_OLOGIC0_TFB", + "SHIFTOUT1": "RIOI_OSOUT10", + "T3": "IOI_OLOGIC0_T3", + "D1": "IOI_OLOGIC0_D1", + "D5": "IOI_OLOGIC0_D5", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "D8": "IOI_OLOGIC0_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "ODELAY", + "type": "ODELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_ODELAY0_CNTVALUEIN1", + "OFDLY1": "RIOI_ODELAY0_OFDLY1", + "REGRST": "IOI_ODELAY0_REGRST", + "CNTVALUEIN3": "IOI_ODELAY0_CNTVALUEIN3", + "CE": "IOI_ODELAY0_CE", + "C": "IOI_ODELAY0_C", + "ODATAIN": "RIOI_ODELAY0_ODATAIN", + "OFDLY0": "RIOI_ODELAY0_OFDLY0", + "CNTVALUEIN4": "IOI_ODELAY0_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_ODELAY0_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_ODELAY0_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_ODELAY0_CNTVALUEOUT3", + "LD": "IOI_ODELAY0_LD", + "CINVCTRL": "IOI_ODELAY0_CINVCTRL", + "CNTVALUEOUT4": "IOI_ODELAY0_CNTVALUEOUT4", + "DATAOUT": "RIOI_ODELAY0_DATAOUT", + "LDPIPEEN": "IOI_ODELAY0_LDPIPEEN", + "CNTVALUEIN0": "IOI_ODELAY0_CNTVALUEIN0", + "CLKIN": "IOI_ODELAY0_CLKIN", + "INC": "IOI_ODELAY0_INC", + "CNTVALUEOUT2": "IOI_ODELAY0_CNTVALUEOUT2", + "OFDLY2": "RIOI_ODELAY0_OFDLY2", + "CNTVALUEIN2": "IOI_ODELAY0_CNTVALUEIN2" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "ILOGIC", + "type": "ILOGICE2", + "site_pins": { + "Q4": "IOI_ILOGIC0_Q4", + "D": "RIOI_ILOGIC0_D", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN2": null, + "O": "IOI_ILOGIC0_O", + "Q6": "IOI_ILOGIC0_Q6", + "Q7": "IOI_ILOGIC0_Q7", + "TFB": "RIOI_ILOGIC0_TFB", + "Q2": "IOI_ILOGIC0_Q2", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "SHIFTIN1": null, + "Q8": "IOI_ILOGIC0_Q8", + "CE1": "IOI_ILOGIC0_CE1", + "CE2": "IOI_ILOGIC0_CE2", + "SR": "IOI_ILOGIC0_SR", + "Q3": "IOI_ILOGIC0_Q3", + "CLK": "IOI_ILOGIC0_CLK", + "OFB": "RIOI_ILOGIC0_OFB", + "DDLY": "RIOI_ILOGIC0_DDLY", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "CLKB": "IOI_ILOGIC0_CLKB", + "REV": null, + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "OCLKB": "IOI_ILOGIC0_OCLKB", + "SHIFTOUT1": "RIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "Q1": "IOI_ILOGIC0_Q1", + "SHIFTOUT2": "RIOI_ISOUT20" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IDELAY", + "type": "IDELAYE2_FINEDELAY", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "DATAOUT": "RIOI_IDELAY0_DATAOUT", + "IDATAIN": "RIOI_IDELAY0_IDATAIN", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "C": "IOI_IDELAY0_C", + "IFDLY0": "RIOI_IDELAY0_IFDLY0", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "LD": "IOI_IDELAY0_LD", + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "IFDLY1": "RIOI_IDELAY0_IFDLY1", + "IFDLY2": "RIOI_IDELAY0_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2" + }, + "x_coord": 0 + } + ], + "wires": [ + "IOI_WL1END0_0", + "RIOI_OLOGIC0_OQ", + "IOI_IDELAY0_LDPIPEEN", + "IOI_LOGIC_OUTS6_0", + "IOI_IMUX12_0", + "IOI_ILOGIC0_CLKB", + "IOI_LH12_0", + "IOI_LH6_0", + "IOI_EE2BEG2_0", + "IOI_SE4C2_0", + "IOI_OLOGIC0_D5", + "IOI_IMUX2_0", + "IOI_EE4A2_0", + "IOI_WW4A3_0", + "IOI_LOGIC_OUTS22_0", + "RIOI_ODELAY0_OFDLY2", + "IOI_NW2A1_0", + "IOI_WW2A0_0", + "IOI_EL1BEG2_0", + "IOI_PHASER_TO_IO_OCLK1X_90", + "IOI_CTRL0_0", + "IOI_IDELAY0_CE", + "IOI_SE4BEG2_0", + "IOI_ILOGIC0_BITSLIP", + "IOI_IMUX14_0", + "IOI_LOGIC_OUTS3_0", + "IOI_IMUX34_0", + "IOI_WL1END3_0", + "IOI_OLOGIC0_D8", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_SW4END2_0", + "IOI_OLOGIC0_T3", + "IOI_LOGIC_OUTS5_0", + "IOI_ILOGIC0_Q5", + "RIOI_IDELAY0_IDATAIN", + "IOI_ODELAY0_C", + "IOI_FAN3_0", + "RIOI_OSIN20", + "IOI_LOGIC_OUTS13_0", + "IOI_IMUX39_0", + "IOI_WW4B0_0", + "RIOI_ODELAY0_OFDLY0", + "IOI_ILOGIC0_Q6", + "IOI_IMUX4_0", + "IOI_IDELAY0_C", + "IOI_WR1END3_0", + "IOI_WW2END0_0", + "IOI_FAN1_0", + "IOI_ILOGIC0_Q3", + "IOI_IDELAY0_CINVCTRL", + "IOI_LOGIC_OUTS19_0", + "IOI_EE2BEG1_0", + "RIOI_IDELAY0_IFDLY0", + "IOI_WR1END2_0", + "IOI_ODELAY0_REGRST", + "IOI_WW4END0_0", + "IOI_ODELAY0_INC", + "RIOI_PU_INT_EN_1", + "IOI_IMUX0_0", + "RIOI_KEEPER_INT_EN_1", + "IOI_LH7_0", + "IOI_WW4C2_0", + "IOI_NW2A2_0", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS20_0", + "IOI_IMUX3_0", + "IOI_PHASER_TO_IO_OCLK", + "IOI_LOGIC_OUTS9_0", + "IOI_FAN6_0", + "IOI_WW4C3_0", + "IOI_WW2END1_0", + "IOI_EL1BEG1_0", + "IOI_SE2A3_0", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_LH3_0", + "RIOI_DCI_T_TERM0", + "IOI_IMUX25_0", + "IOI_NE2A1_0", + "IOI_LOGIC_OUTS8_0", + "RIOI_OLOGIC0_OFB", + "IOI_ODELAY0_CLKIN", + "IOI_BLOCK_OUTS2_0", + "IOI_IMUX43_0", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_IMUX44_0", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_IMUX29_0", + "IOI_OLOGIC0_CLKDIV", + "IOI_IMUX22_0", + "IOI_NE4BEG0_0", + "IOI_NE4C1_0", + "IOI_ILOGIC0_REV", + "IOI_IMUX21_0", + "IOI_IMUX38_0", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_ODELAY0_LDPIPEEN", + "IOI_SE4C3_0", + "IOI_EL1BEG3_0", + "IOI_LOGIC_OUTS11_0", + "IOI_EE4BEG1_0", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_WW4A2_0", + "IOI_FAN0_0", + "IOI_NE4BEG1_0", + "IOI_SING_LEAF_GCLK1", + "IOI_OLOGIC0_D2", + "RIOI_ILOGIC0_OFB", + "IOI_ILOGIC0_Q7", + "IOI_ODELAY0_CNTVALUEOUT0", + "IOI_IDELAY0_REGRST", + "IOI_IMUX10_0", + "RIOI_O0", + "IOI_WW4END3_0", + "RIOI_ISOUT10", + "IOI_IMUX31_0", + "IOI_SE4C0_0", + "IOI_ER1BEG1_0", + "IOI_ILOGIC0_CLKDIV", + "IOI_SE2A1_0", + "IOI_IMUX8_0", + "IOI_LH5_0", + "IOI_WW4B3_0", + "IOI_EE4C3_0", + "IOI_OLOGIC0_CLKB", + "RIOI_OLOGIC0_CLKDIVF", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_SE4BEG0_0", + "RIOI_ILOGIC0_DDLY", + "IOI_SE4C1_0", + "IOI_ILOGIC0_CE2", + "IOI_FAN4_0", + "IOI_ILOGIC0_OCLKB", + "IOI_IMUX17_0", + "IOI_OLOGIC0_CLKDIVB", + "RIOI_ISIN20", + "IOI_IMUX28_0", + "IOI_NW4A2_0", + "IOI_LH9_0", + "RIOI_I0", + "IOI_EE4B0_0", + "IOI_EE2BEG3_0", + "IOI_SING_IOCLK2", + "RIOI_ILOGIC0_TFB", + "RIOI_ODELAY0_OFDLY1", + "IOI_SW4END1_0", + "IOI_SW4A3_0", + "IOI_IMUX16_0", + "IOI_OLOGIC0_TCE", + "IOI_NW4A1_0", + "IOI_NW2A0_0", + "IOI_WW4B2_0", + "IOI_NE2A0_0", + "IOI_EL1BEG0_0", + "IOI_ILOGIC0_CE1", + "IOI_SING_IOCLK3", + "IOI_FAN5_0", + "IOI_IMUX36_0", + "IOI_NW4A3_0", + "IOI_SE2A2_0", + "IOI_IMUX33_0", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_BYP1_0", + "IOI_EE2A3_0", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_IDELAY0_INC", + "IOI_WW2A2_0", + "IOI_WW4A1_0", + "RIOI_ODELAY0_DATAOUT", + "IOI_EE4A0_0", + "IOI_CLK0_0", + "IOI_IMUX30_0", + "IOI_LH10_0", + "IOI_WW2END3_0", + "RIOI_T0", + "IOI_SING_IOCLK1", + "IOI_BYP5_0", + "IOI_BLOCK_OUTS3_0", + "IOI_CLK1_0", + "IOI_SE4BEG3_0", + "IOI_ILOGIC0_Q4", + "IOI_LOGIC_OUTS0_0", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "IOI_BYP4_0", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "RIOI_PD_INT_EN_1", + "IOI_OLOGIC0_D6", + "IOI_WW4B1_0", + "IOI_SING_RCLK_FORIO1", + "IOI_IMUX32_0", + "IOI_SING_LEAF_GCLK3", + "IOI_IMUX45_0", + "IOI_ILOGIC0_Q2", + "IOI_SE4BEG1_0", + "IOI_WW2A1_0", + "IOI_LOGIC_OUTS12_0", + "IOI_ILOGIC0_OCLK", + "IOI_LOGIC_OUTS4_0", + "IOI_EE4B3_0", + "IOI_IMUX19_0", + "IOI_NE4C2_0", + "IOI_OLOGIC0_CLK", + "IOI_WL1END1_0", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_IMUX35_0", + "IOI_WW4A0_0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_IMUX15_0", + "IOI_WL1END2_0", + "IOI_IMUX18_0", + "RIOI_IDELAY0_IFDLY2", + "IOI_WW4END1_0", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS14_0", + "IOI_OLOGIC0_D7", + "IOI_SW2A3_0", + "IOI_SING_IOCLK0", + "IOI_WR1END1_0", + "IOI_IMUX9_0", + "IOI_WW2END2_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_EE4A1_0", + "IOI_SW4END3_0", + "IOI_IMUX11_0", + "IOI_SING_LEAF_GCLK4", + "RIOI_OLOGIC0_TFB_LOCAL", + "IOI_LH8_0", + "IOI_SING_TBYTEIN", + "RIOI_IBUF_DISABLE0", + "IOI_LH2_0", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OCLKM_0", + "IOI_EE4A3_0", + "IOI_IMUX1_0", + "IOI_BYP3_0", + "IOI_NE2A2_0", + "IOI_ER1BEG0_0", + "IOI_NW2A3_0", + "RIOI_OSOUT20", + "IOI_NW4END2_0", + "IOI_IMUX40_0", + "IOI_ER1BEG3_0", + "IOI_FAN2_0", + "IOI_SW2A1_0", + "IOI_SING_LEAF_GCLK2", + "IOI_CTRL1_0", + "IOI_SING_RCLK_FORIO3", + "IOI_OLOGIC0_OCE", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_ILOGIC0_Q1", + "IOI_SING_LEAF_GCLK0", + "IOI_EE4BEG0_0", + "IOI_IMUX41_0", + "IOI_IMUX24_0", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WW2A3_0", + "RIOI_OLOGIC0_TFB", + "IOI_IMUX46_0", + "IOI_OLOGIC0_IOCLKGLITCH", + "RIOI_IBUF0", + "IOI_IMUX5_0", + "RIOI_OLOGIC0_TQ", + "IOI_ODELAY0_CNTVALUEIN2", + "IOI_SW4A1_0", + "IOI_NW4END3_0", + "IOI_LH11_0", + "IOI_ODELAY0_CINVCTRL", + "IOI_EE4C1_0", + "IOI_OLOGIC0_D1", + "IOI_BYP2_0", + "IOI_WW4C0_0", + "IOI_IMUX26_0", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_ODELAY0_LD", + "IOI_ODELAY0_CNTVALUEIN0", + "IOI_EE4B2_0", + "IOI_NW4A0_0", + "IOI_SE2A0_0", + "RIOI_ILOGIC0_D", + "IOI_EE4C0_0", + "RIOI_ISIN10", + "IOI_LOGIC_OUTS18_0", + "IOI_LOGIC_OUTS21_0", + "RIOI_ISOUT20", + "IOI_LOGIC_OUTS16_0", + "IOI_PHASER_TO_IO_ICLKDIV", + "IOI_IDELAY0_LD", + "IOI_IMUX23_0", + "IOI_LOGIC_OUTS1_0", + "IOI_WR1END0_0", + "IOI_EE4BEG3_0", + "RIOI_OSIN10", + "IOI_LOGIC_OUTS15_0", + "IOI_LOGIC_OUTS23_0", + "IOI_ER1BEG2_0", + "IOI_EE4BEG2_0", + "IOI_EE2A0_0", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_EE4B1_0", + "IOI_IMUX7_0", + "IOI_IDELAY0_CNTVALUEIN0", + "IOI_BLOCK_OUTS1_0", + "IOI_IMUX42_0", + "IOI_WW4C1_0", + "IOI_OLOGIC0_REV", + "IOI_IMUX37_0", + "RIOI_OSOUT10", + "RIOI_ODELAY0_ODATAIN", + "IOI_BYP6_0", + "IOI_SING_RCLK_FORIO0", + "IOI_LOGIC_OUTS7_0", + "IOI_NE4BEG2_0", + "IOI_OLOGIC0_D4", + "IOI_EE2BEG0_0", + "IOI_SING_RCLK_FORIO2", + "IOI_ODELAY0_CNTVALUEIN3", + "IOI_ILOGIC0_CLKDIVP", + "IOI_OLOGIC0_T1", + "RIOI_IDELAY0_IFDLY1", + "IOI_IMUX13_0", + "IOI_NE4C3_0", + "IOI_ILOGIC0_SR", + "IOI_EE2A2_0", + "IOI_IMUX6_0", + "IOI_NW4END0_0", + "IOI_NE2A3_0", + "IOI_OLOGIC0_SR", + "IOI_IMUX47_0", + "IOI_NE4BEG3_0", + "IOI_ILOGIC0_Q8", + "IOI_ILOGIC0_O", + "IOI_BYP0_0", + "IOI_IMUX27_0", + "IOI_SW2A0_0", + "IOI_ODELAY0_CNTVALUEIN4", + "IOI_LH1_0", + "IOI_WW4END2_0", + "IOI_BYP7_0", + "IOI_SW4A0_0", + "IOI_SW4END0_0", + "IOI_FAN7_0", + "IOI_NW4END1_0", + "IOI_IDELAY0_DATAIN", + "IOI_SW4A2_0", + "IOI_LOGIC_OUTS10_0", + "IOI_LOGIC_OUTS17_0", + "IOI_OLOGIC0_D3", + "IOI_OLOGIC0_T2", + "IOI_SING_LEAF_GCLK5", + "IOI_EE2A1_0", + "IOI_OLOGIC0_TBYTEIN", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_LOGIC_OUTS2_0", + "IOI_BLOCK_OUTS0_0", + "IOI_ODELAY0_CE", + "IOI_OCLK_0", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_NE4C0_0", + "IOI_IMUX20_0", + "IOI_LH4_0", + "RIOI_IDELAY0_DATAOUT", + "IOI_OLOGIC0_T4" + ], + "pips": { + "RIOI_SING.IOI_BYP5_0->RIOI_ODELAY0_OFDLY2": { + "src_wire": "IOI_BYP5_0", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_OFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX18_0->IOI_ODELAY0_CNTVALUEIN4": { + "src_wire": "IOI_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_ODELAY0_DATAOUT->RIOI_O0": { + "src_wire": "RIOI_ODELAY0_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_O0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLK_0": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_OCLK_0->IOI_ODELAY0_CLKIN": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CLKIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX17_0->IOI_ODELAY0_CNTVALUEIN2": { + "src_wire": "IOI_IMUX17_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX8_0->IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLK_0": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_0": { + "src_wire": "IOI_ILOGIC0_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX46_0->IOI_OLOGIC0_D7": { + "src_wire": "IOI_IMUX46_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX0_0->IOI_ILOGIC0_BITSLIP": { + "src_wire": "IOI_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX27_0->IOI_ODELAY0_LDPIPEEN": { + "src_wire": "IOI_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ODELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS21_0": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS21_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX1_0->IOI_OLOGIC0_TCE": { + "src_wire": "IOI_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX8_0->RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX15_0->IOI_OLOGIC0_T1": { + "src_wire": "IOI_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO1->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_SING_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_BYP2_0->IOI_ODELAY0_CINVCTRL": { + "src_wire": "IOI_BYP2_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX30_0->IOI_IDELAY0_LD": { + "src_wire": "IOI_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX47_0->IOI_OLOGIC0_D8": { + "src_wire": "IOI_IMUX47_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO2->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX2_0->IOI_ODELAY0_CE": { + "src_wire": "IOI_IMUX2_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX19_0->IOI_ODELAY0_CNTVALUEIN3": { + "src_wire": "IOI_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { + "src_wire": "RIOI_OLOGIC0_TQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_SING_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_FAN4_0->RIOI_IDELAY0_IFDLY0": { + "src_wire": "IOI_FAN4_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_OLOGIC0_TQ->>RIOI_T0": { + "src_wire": "RIOI_OLOGIC0_TQ", + "is_pseudo": "0", + "dst_wire": "RIOI_T0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX23_0->IOI_ODELAY0_CNTVALUEIN0": { + "src_wire": "IOI_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX45_0->IOI_OLOGIC0_D6": { + "src_wire": "IOI_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX44_0->IOI_OLOGIC0_D3": { + "src_wire": "IOI_IMUX44_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_I0->RIOI_IDELAY0_IDATAIN": { + "src_wire": "RIOI_I0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX10_0->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX26_0->IOI_IDELAY0_INC": { + "src_wire": "IOI_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX29_0->IOI_OLOGIC0_OCE": { + "src_wire": "IOI_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX16_0->IOI_ODELAY0_CNTVALUEIN1": { + "src_wire": "IOI_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX43_0->IOI_OLOGIC0_D5": { + "src_wire": "IOI_IMUX43_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_BYP0_0->RIOI_ODELAY0_OFDLY0": { + "src_wire": "IOI_BYP0_0", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_OFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { + "src_wire": "RIOI_OLOGIC0_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX5_0->IOI_ILOGIC0_CE1": { + "src_wire": "IOI_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_0": { + "src_wire": "IOI_ILOGIC0_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_SING_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_OLOGIC0_OFB->RIOI_ODELAY0_ODATAIN": { + "src_wire": "RIOI_OLOGIC0_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_ODATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX11_0->IOI_ODELAY0_REGRST": { + "src_wire": "IOI_IMUX11_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ODELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS6_0": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS6_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX9_0->RIOI_IBUF_DISABLE0": { + "src_wire": "IOI_IMUX9_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { + "src_wire": "RIOI_IDELAY0_IDATAIN", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_I0->RIOI_ILOGIC0_D": { + "src_wire": "RIOI_I0", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_D", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_SING_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLK_0": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX3_0->IOI_ODELAY0_INC": { + "src_wire": "IOI_IMUX3_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_BYP7_0->RIOI_IDELAY0_IFDLY2": { + "src_wire": "IOI_BYP7_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX31_0->>IOI_OCLK_0": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIV": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_CTRL0_0->IOI_OLOGIC0_SR": { + "src_wire": "IOI_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLK_0": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_0": { + "src_wire": "IOI_ILOGIC0_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_0": { + "src_wire": "IOI_ILOGIC0_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX31_0->>IOI_OCLKM_0": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX33_0->IOI_IDELAY0_LDPIPEEN": { + "src_wire": "IOI_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_FAN5_0->RIOI_IDELAY0_IFDLY1": { + "src_wire": "IOI_FAN5_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX6_0->RIOI_DCI_T_TERM0": { + "src_wire": "IOI_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX4_0->IOI_ILOGIC0_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { + "src_wire": "IOI_SING_TBYTEIN", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX41_0->IOI_IDELAY0_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_0": { + "src_wire": "IOI_ILOGIC0_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX35_0->IOI_IDELAY0_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_0": { + "src_wire": "IOI_ILOGIC0_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX14_0->IOI_ILOGIC0_CE2": { + "src_wire": "IOI_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_OLOGIC0_OQ->>RIOI_O0": { + "src_wire": "RIOI_OLOGIC0_OQ", + "is_pseudo": "0", + "dst_wire": "RIOI_O0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { + "src_wire": "RIOI_IDELAY0_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX13_0->IOI_OLOGIC0_T3": { + "src_wire": "IOI_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_0": { + "src_wire": "IOI_ILOGIC0_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_0": { + "src_wire": "IOI_ILOGIC0_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX34_0->IOI_OLOGIC0_D1": { + "src_wire": "IOI_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ODELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS12_0": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS12_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX21_0->IOI_OLOGIC0_T4": { + "src_wire": "IOI_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX25_0->IOI_IDELAY0_DATAIN": { + "src_wire": "IOI_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX42_0->IOI_OLOGIC0_D4": { + "src_wire": "IOI_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX28_0->IOI_ODELAY0_LD": { + "src_wire": "IOI_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX36_0->IOI_IDELAY0_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX39_0->IOI_IDELAY0_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { + "src_wire": "RIOI_OLOGIC0_OQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX38_0->IOI_IDELAY0_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLK_0": { + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLK_0": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "src_wire": "RIOI_ILOGIC0_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX7_0->IOI_OLOGIC0_T2": { + "src_wire": "IOI_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { + "src_wire": "RIOI_OLOGIC0_TFB", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_BYP6_0->IOI_IDELAY0_CINVCTRL": { + "src_wire": "IOI_BYP6_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_RCLK_FORIO0->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ODELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS17_0": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS17_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX40_0->IOI_OLOGIC0_D2": { + "src_wire": "IOI_IMUX40_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_CLK1_0->IOI_IDELAY0_C": { + "src_wire": "IOI_CLK1_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX37_0->IOI_ILOGIC0_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_IBUF0->RIOI_I0": { + "src_wire": "RIOI_IBUF0", + "is_pseudo": "0", + "dst_wire": "RIOI_I0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_BYP1_0->RIOI_ODELAY0_OFDLY1": { + "src_wire": "IOI_BYP1_0", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_OFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "src_wire": "RIOI_ILOGIC0_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX32_0->IOI_IDELAY0_CE": { + "src_wire": "IOI_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ODELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS4_0": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS4_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_CTRL1_0->IOI_ILOGIC0_SR": { + "src_wire": "IOI_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_0": { + "src_wire": "IOI_ILOGIC0_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_IMUX12_0->IOI_IDELAY0_REGRST": { + "src_wire": "IOI_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_CLK1_0->IOI_ODELAY0_C": { + "src_wire": "IOI_CLK1_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_RIOI_TBYTESRC.json b/kintex7/tile_type_RIOI_TBYTESRC.json new file mode 100644 index 0000000..bb3618f --- /dev/null +++ b/kintex7/tile_type_RIOI_TBYTESRC.json @@ -0,0 +1,4279 @@ +{ + "tile_type": "RIOI_TBYTESRC", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "OLOGIC", + "type": "OLOGICE2", + "site_pins": { + "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", + "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", + "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", + "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", + "OFB": "RIOI_OLOGIC1_OFB", + "T1": "IOI_OLOGIC1_T1", + "D6": "IOI_OLOGIC1_D6", + "SHIFTIN2": null, + "TCE": "IOI_OLOGIC1_TCE", + "OCE": "IOI_OLOGIC1_OCE", + "SHIFTOUT2": "RIOI_OSOUT21", + "REV": null, + "OQ": "RIOI_OLOGIC1_OQ", + "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", + "D7": "IOI_OLOGIC1_D7", + "TQ": "RIOI_OLOGIC1_TQ", + "D3": "IOI_OLOGIC1_D3", + "D4": "IOI_OLOGIC1_D4", + "SR": "IOI_OLOGIC1_SR", + "CLKB": "IOI_OLOGIC1_CLKB", + "SHIFTIN1": null, + "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF", + "D2": "IOI_OLOGIC1_D2", + "CLK": "IOI_OLOGIC1_CLK", + "T4": "IOI_OLOGIC1_T4", + "T2": "IOI_OLOGIC1_T2", + "TFB": "RIOI_OLOGIC1_TFB", + "SHIFTOUT1": "RIOI_OSOUT11", + "T3": "IOI_OLOGIC1_T3", + "D1": "IOI_OLOGIC1_D1", + "D5": "IOI_OLOGIC1_D5", + "CLKDIV": "IOI_OLOGIC1_CLKDIV", + "D8": "IOI_OLOGIC1_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "ODELAY", + "type": "ODELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_ODELAY1_CNTVALUEIN1", + "OFDLY1": "RIOI_ODELAY1_OFDLY1", + "REGRST": "IOI_ODELAY1_REGRST", + "CNTVALUEIN3": "IOI_ODELAY1_CNTVALUEIN3", + "CE": "IOI_ODELAY1_CE", + "C": "IOI_ODELAY1_C", + "ODATAIN": "RIOI_ODELAY1_ODATAIN", + "OFDLY0": "RIOI_ODELAY1_OFDLY0", + "CNTVALUEIN4": "IOI_ODELAY1_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_ODELAY1_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_ODELAY1_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_ODELAY1_CNTVALUEOUT3", + "LD": "IOI_ODELAY1_LD", + "CINVCTRL": "IOI_ODELAY1_CINVCTRL", + "CNTVALUEOUT4": "IOI_ODELAY1_CNTVALUEOUT4", + "DATAOUT": "RIOI_ODELAY1_DATAOUT", + "LDPIPEEN": "IOI_ODELAY1_LDPIPEEN", + "CNTVALUEIN0": "IOI_ODELAY1_CNTVALUEIN0", + "CLKIN": "IOI_ODELAY1_CLKIN", + "INC": "IOI_ODELAY1_INC", + "CNTVALUEOUT2": "IOI_ODELAY1_CNTVALUEOUT2", + "OFDLY2": "RIOI_ODELAY1_OFDLY2", + "CNTVALUEIN2": "IOI_ODELAY1_CNTVALUEIN2" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "ILOGIC", + "type": "ILOGICE2", + "site_pins": { + "Q4": "IOI_ILOGIC1_Q4", + "D": "RIOI_ILOGIC1_D", + "Q5": "IOI_ILOGIC1_Q5", + "SHIFTIN2": "RIOI_ISIN21", + "O": "IOI_ILOGIC1_O", + "Q6": "IOI_ILOGIC1_Q6", + "Q7": "IOI_ILOGIC1_Q7", + "TFB": "RIOI_ILOGIC1_TFB", + "Q2": "IOI_ILOGIC1_Q2", + "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", + "SHIFTIN1": "RIOI_ISIN11", + "Q8": "IOI_ILOGIC1_Q8", + "CE1": "IOI_ILOGIC1_CE1", + "CE2": "IOI_ILOGIC1_CE2", + "SR": "IOI_ILOGIC1_SR", + "Q3": "IOI_ILOGIC1_Q3", + "CLK": "IOI_ILOGIC1_CLK", + "OFB": "RIOI_ILOGIC1_OFB", + "DDLY": "RIOI_ILOGIC1_DDLY", + "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", + "CLKB": "IOI_ILOGIC1_CLKB", + "REV": null, + "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "CLKDIV": "IOI_ILOGIC1_CLKDIV", + "BITSLIP": "IOI_ILOGIC1_BITSLIP", + "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", + "OCLKB": "IOI_ILOGIC1_OCLKB", + "SHIFTOUT1": "RIOI_ISOUT11", + "OCLK": "IOI_ILOGIC1_OCLK", + "Q1": "IOI_ILOGIC1_Q1", + "SHIFTOUT2": "RIOI_ISOUT21" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "OLOGIC", + "type": "OLOGICE2", + "site_pins": { + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "OFB": "RIOI_OLOGIC0_OFB", + "T1": "IOI_OLOGIC0_T1", + "D6": "IOI_OLOGIC0_D6", + "SHIFTIN2": "RIOI_OSIN20", + "TCE": "IOI_OLOGIC0_TCE", + "OCE": "IOI_OLOGIC0_OCE", + "SHIFTOUT2": "RIOI_OSOUT20", + "REV": null, + "OQ": "RIOI_OLOGIC0_OQ", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "TQ": "RIOI_OLOGIC0_TQ", + "D3": "IOI_OLOGIC0_D3", + "D4": "IOI_OLOGIC0_D4", + "SR": "IOI_OLOGIC0_SR", + "CLKB": "IOI_OLOGIC0_CLKB", + "SHIFTIN1": "RIOI_OSIN10", + "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", + "D2": "IOI_OLOGIC0_D2", + "CLK": "IOI_OLOGIC0_CLK", + "T4": "IOI_OLOGIC0_T4", + "T2": "IOI_OLOGIC0_T2", + "TFB": "RIOI_OLOGIC0_TFB", + "SHIFTOUT1": "RIOI_OSOUT10", + "T3": "IOI_OLOGIC0_T3", + "D1": "IOI_OLOGIC0_D1", + "D5": "IOI_OLOGIC0_D5", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "D8": "IOI_OLOGIC0_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "ODELAY", + "type": "ODELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_ODELAY0_CNTVALUEIN1", + "OFDLY1": "RIOI_ODELAY0_OFDLY1", + "REGRST": "IOI_ODELAY0_REGRST", + "CNTVALUEIN3": "IOI_ODELAY0_CNTVALUEIN3", + "CE": "IOI_ODELAY0_CE", + "C": "IOI_ODELAY0_C", + "ODATAIN": "RIOI_ODELAY0_ODATAIN", + "OFDLY0": "RIOI_ODELAY0_OFDLY0", + "CNTVALUEIN4": "IOI_ODELAY0_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_ODELAY0_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_ODELAY0_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_ODELAY0_CNTVALUEOUT3", + "LD": "IOI_ODELAY0_LD", + "CINVCTRL": "IOI_ODELAY0_CINVCTRL", + "CNTVALUEOUT4": "IOI_ODELAY0_CNTVALUEOUT4", + "DATAOUT": "RIOI_ODELAY0_DATAOUT", + "LDPIPEEN": "IOI_ODELAY0_LDPIPEEN", + "CNTVALUEIN0": "IOI_ODELAY0_CNTVALUEIN0", + "CLKIN": "IOI_ODELAY0_CLKIN", + "INC": "IOI_ODELAY0_INC", + "CNTVALUEOUT2": "IOI_ODELAY0_CNTVALUEOUT2", + "OFDLY2": "RIOI_ODELAY0_OFDLY2", + "CNTVALUEIN2": "IOI_ODELAY0_CNTVALUEIN2" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "ILOGIC", + "type": "ILOGICE2", + "site_pins": { + "Q4": "IOI_ILOGIC0_Q4", + "D": "RIOI_ILOGIC0_D", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN2": null, + "O": "IOI_ILOGIC0_O", + "Q6": "IOI_ILOGIC0_Q6", + "Q7": "IOI_ILOGIC0_Q7", + "TFB": "RIOI_ILOGIC0_TFB", + "Q2": "IOI_ILOGIC0_Q2", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "SHIFTIN1": null, + "Q8": "IOI_ILOGIC0_Q8", + "CE1": "IOI_ILOGIC0_CE1", + "CE2": "IOI_ILOGIC0_CE2", + "SR": "IOI_ILOGIC0_SR", + "Q3": "IOI_ILOGIC0_Q3", + "CLK": "IOI_ILOGIC0_CLK", + "OFB": "RIOI_ILOGIC0_OFB", + "DDLY": "RIOI_ILOGIC0_DDLY", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "CLKB": "IOI_ILOGIC0_CLKB", + "REV": null, + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "OCLKB": "IOI_ILOGIC0_OCLKB", + "SHIFTOUT1": "RIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "Q1": "IOI_ILOGIC0_Q1", + "SHIFTOUT2": "RIOI_ISOUT20" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IDELAY", + "type": "IDELAYE2_FINEDELAY", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", + "DATAOUT": "RIOI_IDELAY1_DATAOUT", + "IDATAIN": "RIOI_IDELAY1_IDATAIN", + "REGRST": "IOI_IDELAY1_REGRST", + "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", + "C": "IOI_IDELAY1_C", + "IFDLY0": "RIOI_IDELAY1_IFDLY0", + "DATAIN": "IOI_IDELAY1_DATAIN", + "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", + "LD": "IOI_IDELAY1_LD", + "CINVCTRL": "IOI_IDELAY1_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", + "IFDLY1": "RIOI_IDELAY1_IFDLY1", + "IFDLY2": "RIOI_IDELAY1_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", + "INC": "IOI_IDELAY1_INC", + "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", + "CE": "IOI_IDELAY1_CE", + "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "IDELAY", + "type": "IDELAYE2_FINEDELAY", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "DATAOUT": "RIOI_IDELAY0_DATAOUT", + "IDATAIN": "RIOI_IDELAY0_IDATAIN", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "C": "IOI_IDELAY0_C", + "IFDLY0": "RIOI_IDELAY0_IFDLY0", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "LD": "IOI_IDELAY0_LD", + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "IFDLY1": "RIOI_IDELAY0_IFDLY1", + "IFDLY2": "RIOI_IDELAY0_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2" + }, + "x_coord": 0 + } + ], + "wires": [ + "IOI_RCLK_DIV_CLR0_1", + "IOI_WL1END0_0", + "RIOI_OLOGIC0_OQ", + "IOI_IDELAYCTRL_RST", + "RIOI_I2GCLK_BOT1", + "IOI_IMUX12_0", + "IOI_LH12_0", + "IOI_DCI_TSTHLN", + "IOI_IDELAYCTRL_OUTN1", + "IOI_EE2BEG2_0", + "IOI_SE4C2_0", + "IOI_OLOGIC0_D5", + "IOI_IOCLK1", + "IOI_IMUX2_0", + "IOI_WW4A3_0", + "IOI_OLOGIC1_SR", + "RIOI_ODELAY0_OFDLY2", + "IOI_EL1BEG2_0", + "IOI_ILOGIC1_REV", + "IOI_EL1BEG2_1", + "IOI_SE4BEG2_0", + "IOI_IDELAYCTRL_RDY", + "IOI_EE4A0_1", + "IOI_RCLK_DIV_CE1", + "IOI_OLOGIC1_CLKB", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_LOGIC_OUTS8_1", + "IOI_SW4END2_0", + "IOI_IMUX_RC1", + "IOI_ODELAY1_CNTVALUEOUT2", + "RIOI_OSIN20", + "RIOI_IDELAY1_IDATAIN", + "IOI_IMUX39_0", + "IOI_WW4B0_0", + "IOI_ER1BEG3_1", + "IOI_BYP1_1", + "RIOI_ODELAY0_OFDLY0", + "IOI_IMUX5_1", + "IOI_PHASER_TO_IO_ICLKDIV_0", + "IOI_IMUX46_1", + "IOI_ILOGIC0_Q6", + "IOI_IMUX4_0", + "IOI_ODELAY1_CNTVALUEOUT4", + "IOI_NW4END3_1", + "IOI_ILOGIC1_OCLKB", + "IOI_FAN1_0", + "IOI_LOGIC_OUTS19_0", + "IOI_IMUX29_1", + "IOI_IMUX10_1", + "IOI_ILOGIC1_DYNCLKDIVPSEL", + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "RIOI_DIFF_TERM_INT_EN", + "IOI_ILOGIC1_Q1", + "IOI_OLOGIC1_D7", + "RIOI_IDELAY0_IFDLY0", + "IOI_LH5_1", + "IOI_ODELAY0_REGRST", + "IOI_IOCLK2", + "IOI_WW4END0_0", + "RIOI_PU_INT_EN_1", + "RIOI_KEEPER_INT_EN_1", + "IOI_WW4END2_1", + "RIOI_ODELAY1_ODATAIN", + "IOI_IMUX32_1", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS20_0", + "IOI_PHASER_TO_IO_OCLK", + "IOI_LOGIC_OUTS5_1", + "IOI_RCLK_DIV_CE0", + "RIOI_OSOUT11", + "IOI_LOGIC_OUTS9_0", + "IOI_EE2A1_1", + "IOI_EE2A3_1", + "IOI_FAN6_0", + "IOI_WW2END1_0", + "IOI_IOCLK3", + "IOI_WW2END0_1", + "IOI_SE2A3_0", + "IOI_SE4C0_1", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_EE2A0_1", + "IOI_DCI_DCIDONE", + "RIOI_DCI_T_TERM0", + "IOI_IMUX25_0", + "RIOI_OSIN11", + "IOI_LOGIC_OUTS8_0", + "IOI_ODELAY0_CLKIN", + "IOI_BLOCK_OUTS2_0", + "IOI_FAN4_1", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_NE4C2_1", + "IOI_IMUX44_0", + "IOI_IMUX29_0", + "IOI_WR1END2_1", + "IOI_OLOGIC0_CLKDIV", + "IOI_EE4C3_1", + "IOI_EE2BEG3_1", + "IOI_IMUX22_0", + "IOI_ILOGIC0_REV", + "IOI_IMUX15_1", + "IOI_IMUX21_0", + "IOI_BYP4_1", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_ODELAY0_LDPIPEEN", + "IOI_NE2A3_1", + "IOI_ILOGIC1_Q3", + "IOI_BYP2_1", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_WW4A2_0", + "IOI_NE4BEG1_0", + "IOI_LOGIC_OUTS18_1", + "IOI_OLOGIC0_D2", + "RIOI_ILOGIC0_OFB", + "IOI_ILOGIC0_Q7", + "IOI_ILOGIC1_CLK", + "IOI_ODELAY0_CNTVALUEOUT0", + "IOI_ODELAY1_INC", + "IOI_IDELAY0_REGRST", + "IOI_SE4BEG1_1", + "IOI_IMUX33_1", + "IOI_WW4END3_0", + "IOI_WR1END1_1", + "IOI_ILOGIC1_CE2", + "IOI_SE4C0_0", + "IOI_LOGIC_OUTS21_1", + "IOI_ILOGIC0_CLKDIV", + "IOI_SE2A1_0", + "IOI_IMUX8_0", + "IOI_LH5_0", + "IOI_IDELAYCTRL_OUTN65", + "IOI_NE2A1_1", + "IOI_EE4C3_0", + "IOI_LOGIC_OUTS14_1", + "IOI_OLOGIC0_CLKB", + "RIOI_OLOGIC0_CLKDIVF", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_SE4BEG0_0", + "IOI_ILOGIC0_OCLKB", + "IOI_SE4C1_1", + "IOI_IMUX47_1", + "RIOI_OLOGIC1_TFB_LOCAL", + "IOI_CLK1_1", + "IOI_IDELAY1_DATAIN", + "IOI_ODELAY1_CNTVALUEIN0", + "RIOI_ISOUT11", + "IOI_IMUX28_0", + "IOI_LOGIC_OUTS6_1", + "IOI_SE2A2_1", + "IOI_LH9_0", + "RIOI_I0", + "IOI_EE2BEG3_0", + "IOI_SE2A0_1", + "RIOI_ILOGIC0_TFB", + "IOI_IMUX40_1", + "IOI_IMUX8_1", + "IOI_ILOGIC1_DYNCLKSEL", + "IOI_EE2BEG1_1", + "IOI_SW4END1_0", + "IOI_SW4A3_0", + "IOI_IMUX16_0", + "IOI_LOGIC_OUTS0_1", + "IOI_ER1BEG0_1", + "IOI_OLOGIC0_TCE", + "IOI_NW4A1_0", + "IOI_NW2A0_0", + "IOI_IDELAY1_CNTVALUEIN4", + "IOI_EL1BEG0_0", + "IOI_ILOGIC0_CE1", + "IOI_NW4A3_0", + "IOI_IDELAY1_CNTVALUEOUT1", + "IOI_SE2A2_0", + "IOI_WL1END1_1", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_ILOGIC1_O", + "IOI_IDELAY0_INC", + "IOI_IMUX28_1", + "IOI_WW4A1_0", + "IOI_IDELAY1_CNTVALUEOUT0", + "IOI_ODELAY1_CINVCTRL", + "IOI_IMUX37_1", + "IOI_MONITOR_P", + "IOI_EE4C0_1", + "IOI_OLOGIC1_TBYTEOUT", + "IOI_LEAF_GCLK0", + "IOI_LOGIC_OUTS7_1", + "RIOI_ISIN21", + "RIOI_ODELAY1_OFDLY1", + "IOI_IMUX35_1", + "IOI_WW2END3_0", + "IOI_IDELAY1_CNTVALUEOUT4", + "IOI_EE4C2_1", + "IOI_NE4BEG2_1", + "IOI_SE4BEG3_0", + "IOI_ILOGIC1_Q6", + "IOI_ILOGIC0_Q4", + "IOI_SE4BEG0_1", + "IOI_RCLK_DIV_CE2_1", + "RIOI_IDELAY1_IFDLY1", + "IOI_LOGIC_OUTS0_0", + "IOI_BYP4_0", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "RIOI_PD_INT_EN_1", + "IOI_OLOGIC0_D6", + "IOI_WL1END3_1", + "IOI_DCI_TSTCLK", + "IOI_WW4B1_0", + "IOI_WW4C2_1", + "IOI_PHASER_TO_IO_OCLK_0", + "IOI_PHASER_TO_IO_OCLKDIV_0", + "IOI_IMUX45_0", + "IOI_ILOGIC0_Q2", + "IOI_SW2A0_1", + "IOI_SE4BEG1_0", + "IOI_WW2A1_0", + "IOI_LOGIC_OUTS12_0", + "IOI_ILOGIC0_OCLK", + "IOI_EE4B3_0", + "IOI_WW4END1_1", + "IOI_IMUX19_0", + "IOI_NE4C2_0", + "IOI_OLOGIC0_CLK", + "IOI_WL1END1_0", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_IMUX_RC2", + "IOI_IMUX2_1", + "IOI_IMUX35_0", + "IOI_WW4A0_0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_IMUX15_0", + "IOI_WL1END2_0", + "IOI_WW2END3_1", + "IOI_IMUX41_1", + "IOI_WW4END1_0", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS14_0", + "IOI_OLOGIC0_D7", + "IOI_IMUX31_1", + "IOI_SW2A3_0", + "RIOI_IDELAY1_IFDLY2", + "IOI_OLOGIC1_TBYTEIN", + "IOI_SW4A2_1", + "IOI_IDELAY1_LDPIPEEN", + "IOI_IMUX6_1", + "IOI_IMUX_RC0", + "IOI_IMUX9_0", + "IOI_WW2END2_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_EE4BEG2_1", + "IOI_FAN6_1", + "IOI_ODELAY1_REGRST", + "IOI_IMUX11_0", + "IOI_RCLK_FORIO1", + "IOI_SW4A0_1", + "RIOI_OLOGIC0_TFB_LOCAL", + "IOI_WW4C0_1", + "RIOI_IBUF_DISABLE0", + "IOI_IMUX30_1", + "IOI_SE2A3_1", + "IOI_SW4A1_1", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OLOGIC1_D4", + "IOI_WW2A1_1", + "IOI_RCLK_DIV_CLR0", + "IOI_NW2A3_0", + "IOI_OLOGIC1_OCE", + "IOI_IMUX40_0", + "IOI_SW4END0_1", + "IOI_SW4END1_1", + "IOI_ILOGIC1_Q4", + "IOI_LOGIC_OUTS16_1", + "IOI_IMUX20_1", + "IOI_NE4C1_1", + "IOI_ILOGIC1_CLKB", + "IOI_RCLK_DIV_CE3", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_LEAF_GCLK1", + "IOI_ILOGIC0_Q1", + "IOI_EE4BEG0_0", + "RIOI_OLOGIC1_OQ", + "RIOI_ODELAY1_DATAOUT", + "IOI_IMUX46_0", + "IOI_IMUX45_1", + "IOI_EE4BEG3_1", + "IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IMUX38_1", + "RIOI_OLOGIC0_TQ", + "IOI_MONITOR_N", + "IOI_LEAF_GCLK5", + "IOI_ODELAY0_CNTVALUEIN2", + "IOI_WW4A3_1", + "RIOI_OSOUT21", + "IOI_NW4END3_0", + "IOI_WW2A3_1", + "IOI_SE4BEG2_1", + "IOI_BYP5_1", + "IOI_ODELAY0_CINVCTRL", + "IOI_OLOGIC0_D1", + "IOI_WW4A2_1", + "IOI_ODELAY1_CE", + "IOI_WW4C0_0", + "IOI_FAN1_1", + "IOI_IMUX26_0", + "IOI_ODELAY0_LD", + "IOI_EE4B2_0", + "IOI_NW4A0_0", + "IOI_SE2A0_0", + "IOI_EE4C0_0", + "IOI_LOGIC_OUTS21_0", + "RIOI_IBUF_DISABLE1", + "IOI_IDELAY0_LD", + "IOI_IMUX23_0", + "IOI_WR1END0_0", + "IOI_WW4END3_1", + "IOI_ODELAY1_CNTVALUEIN1", + "RIOI_OSIN10", + "IOI_LOGIC_OUTS15_0", + "IOI_OLOGIC1_D1", + "IOI_LOGIC_OUTS23_0", + "IOI_WW2END2_1", + "IOI_DCI_TSTRST", + "IOI_IMUX22_1", + "IOI_LOGIC_OUTS1_1", + "IOI_EE4B1_0", + "IOI_IMUX7_0", + "IOI_EE4A2_1", + "IOI_BLOCK_OUTS1_0", + "IOI_IMUX42_0", + "IOI_SW2A2_1", + "IOI_WW4C1_0", + "IOI_OLOGIC0_REV", + "IOI_BYP0_1", + "IOI_IMUX39_1", + "RIOI_ODELAY0_ODATAIN", + "IOI_NW4A0_1", + "IOI_BYP6_0", + "IOI_IMUX13_1", + "IOI_OLOGIC0_D4", + "RIOI_DCI_T_TERM1", + "IOI_ODELAY0_CNTVALUEIN3", + "RIOI_I1", + "IOI_IMUX24_1", + "IOI_ILOGIC0_CLKDIVP", + "RIOI_ISIN11", + "RIOI_IDELAY0_IFDLY1", + "IOI_IMUX13_0", + "IOI_RCLK_DIV_CE2", + "IOI_IDELAY1_REGRST", + "IOI_WR1END3_1", + "RIOI_OLOGIC1_TQ", + "RIOI_KEEPER_INT_EN_0", + "IOI_IDELAY1_C", + "IOI_IDELAY1_LD", + "IOI_IMUX47_0", + "IOI_ILOGIC0_O", + "IOI_ILOGIC1_Q8", + "IOI_BYP0_0", + "IOI_IMUX27_0", + "IOI_SW4END3_1", + "IOI_LH1_0", + "RIOI_IDELAY1_IFDLY0", + "IOI_SW4A0_0", + "IOI_SE4BEG3_1", + "IOI_IDELAY1_CNTVALUEIN0", + "IOI_SW4END0_0", + "IOI_WW4B1_1", + "IOI_IDELAY0_DATAIN", + "IOI_SW4A2_0", + "IOI_LOGIC_OUTS10_0", + "IOI_CLK0_1", + "IOI_IMUX11_1", + "IOI_WW4C1_1", + "IOI_OLOGIC0_T2", + "IOI_BYP6_1", + "IOI_LOGIC_OUTS2_0", + "IOI_BLOCK_OUTS0_0", + "IOI_NW4A3_1", + "IOI_ODELAY0_CE", + "IOI_ILOGIC1_BITSLIP", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_OLOGIC1_CLK", + "IOI_ILOGIC1_CLKDIV", + "IOI_IMUX20_0", + "IOI_LOGIC_OUTS10_1", + "RIOI_IDELAY0_DATAOUT", + "IOI_IDELAY0_LDPIPEEN", + "IOI_LOGIC_OUTS6_0", + "IOI_EL1BEG3_1", + "IOI_ILOGIC0_CLKB", + "IOI_LH6_0", + "IOI_EE4A2_0", + "IOI_LOGIC_OUTS22_0", + "IOI_NW2A1_0", + "IOI_WW2A0_0", + "IOI_PHASER_TO_IO_OCLK1X_90", + "IOI_ILOGIC1_Q5", + "IOI_CTRL0_0", + "IOI_IDELAY0_CE", + "IOI_ILOGIC0_BITSLIP", + "IOI_IMUX14_0", + "IOI_LOGIC_OUTS3_0", + "IOI_IMUX4_1", + "IOI_IMUX3_1", + "IOI_IMUX34_0", + "IOI_WL1END3_0", + "IOI_OLOGIC0_D8", + "IOI_IMUX17_1", + "RIOI_OLOGIC1_TFB", + "IOI_OLOGIC1_TCE", + "IOI_LOGIC_OUTS4_1", + "IOI_OLOGIC0_T3", + "IOI_LOGIC_OUTS5_0", + "IOI_ILOGIC0_Q5", + "RIOI_IDELAY0_IDATAIN", + "IOI_IMUX43_1", + "IOI_ODELAY0_C", + "IOI_EE2BEG2_1", + "IOI_LOGIC_OUTS22_1", + "IOI_FAN3_0", + "IOI_SW2A3_1", + "IOI_LOGIC_OUTS13_0", + "IOI_ODELAY1_LD", + "IOI_ILOGIC1_Q2", + "IOI_IDELAY1_CNTVALUEOUT3", + "IOI_ODELAY1_CNTVALUEIN3", + "IOI_EE4A3_1", + "IOI_WR1END3_0", + "IOI_IDELAY0_C", + "IOI_WW2END0_0", + "IOI_FAN0_1", + "IOI_ILOGIC0_Q3", + "IOI_IDELAY0_CINVCTRL", + "IOI_NW2A1_1", + "IOI_IMUX26_1", + "IOI_EE2BEG1_0", + "IOI_OLOGIC1_IOCLKGLITCH", + "IOI_FAN3_1", + "IOI_NE2A0_1", + "IOI_WR1END2_0", + "IOI_ODELAY1_CNTVALUEIN2", + "IOI_CTRL1_1", + "IOI_ODELAY0_INC", + "IOI_IMUX0_0", + "IOI_BYP3_1", + "IOI_IMUX19_1", + "IOI_LH7_0", + "IOI_SE4C2_1", + "IOI_BLOCK_OUTS2_1", + "IOI_WW4C2_0", + "IOI_NW2A2_0", + "IOI_NW4END2_1", + "IOI_NE4BEG1_1", + "IOI_NW4A1_1", + "IOI_IMUX3_0", + "IOI_OLOGIC1_CLKDIV", + "IOI_LEAF_GCLK4", + "RIOI_PU_INT_EN_0", + "IOI_WW4C3_0", + "IOI_EL1BEG1_0", + "IOI_IMUX0_1", + "IOI_WR1END0_1", + "IOI_LH4_1", + "IOI_IDELAY1_CE", + "IOI_NE4C3_1", + "IOI_BLOCK_OUTS0_1", + "IOI_IDELAY1_CINVCTRL", + "IOI_LH3_0", + "IOI_NE2A1_0", + "RIOI_OLOGIC0_OFB", + "IOI_IMUX43_0", + "IOI_RCLK_DIV_CLR2", + "IOI_NE4BEG3_1", + "IOI_IMUX_RC3", + "RIOI_OSIN21", + "IOI_LOGIC_OUTS9_1", + "IOI_BLOCK_OUTS3_1", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_OLOGIC1_T3", + "IOI_NE4BEG0_0", + "IOI_NE4C1_0", + "IOI_IMUX38_0", + "IOI_LH10_1", + "IOI_IMUX34_1", + "IOI_SE4C3_0", + "IOI_ILOGIC1_Q7", + "IOI_EL1BEG3_0", + "IOI_LOGIC_OUTS11_0", + "IOI_EE4BEG1_0", + "IOI_FAN0_0", + "IOI_FAN2_1", + "IOI_IDELAY1_CNTVALUEIN2", + "IOI_IMUX10_0", + "IOI_EE4B3_1", + "RIOI_O0", + "IOI_IMUX44_1", + "RIOI_ISOUT10", + "IOI_IMUX31_0", + "IOI_WW2END1_1", + "IOI_ER1BEG1_0", + "RIOI_I2GCLK_TOP0", + "IOI_NW2A2_1", + "RIOI_ILOGIC1_DDLY", + "IOI_WW4B3_0", + "IOI_RCLK_FORIO0", + "RIOI_ILOGIC0_DDLY", + "IOI_SE4C1_0", + "IOI_ILOGIC0_CE2", + "IOI_ODELAY1_CNTVALUEOUT0", + "IOI_IMUX16_1", + "IOI_FAN5_1", + "IOI_RCLK_DIV_CE3_1", + "IOI_FAN4_0", + "IOI_IMUX42_1", + "IOI_OLOGIC1_D2", + "IOI_IMUX17_0", + "RIOI_ILOGIC1_D", + "IOI_WW4C3_1", + "IOI_OLOGIC0_CLKDIVB", + "IOI_LH12_1", + "IOI_EE4B1_1", + "IOI_TBYTEIN", + "RIOI_ISIN20", + "IOI_NW4A2_0", + "IOI_LH2_1", + "IOI_EE4B0_0", + "RIOI_ISOUT21", + "RIOI_ODELAY0_OFDLY1", + "IOI_EE4BEG0_1", + "IOI_OLOGIC1_REV", + "IOI_WW4B2_0", + "IOI_NE2A0_0", + "IOI_FAN5_0", + "IOI_IMUX36_0", + "IOI_NW4A2_1", + "IOI_IMUX33_0", + "IOI_BYP1_0", + "IOI_OLOGIC1_T2", + "IOI_RCLK_FORIO2", + "IOI_EE2A3_0", + "IOI_RCLK_DIV_CLR1", + "IOI_IDELAY1_CNTVALUEOUT2", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_NE2A2_1", + "IOI_WW2A2_0", + "IOI_EE4A1_1", + "IOI_EE4B2_1", + "IOI_LEAF_GCLK3", + "IOI_NW4END1_1", + "IOI_ODELAY1_CNTVALUEOUT1", + "IOI_WL1END2_1", + "IOI_LH3_1", + "IOI_LH6_1", + "IOI_RCLK_DIV_CLR3", + "RIOI_T1", + "RIOI_ODELAY0_DATAOUT", + "IOI_EE4A0_0", + "IOI_CLK0_0", + "IOI_IMUX30_0", + "IOI_LH10_0", + "IOI_OLOGIC1_CLKDIVFB", + "RIOI_T0", + "IOI_BYP5_0", + "IOI_BLOCK_OUTS3_0", + "IOI_SW4A3_1", + "IOI_CLK1_0", + "RIOI_I2GCLK_TOP1", + "IOI_LOGIC_OUTS2_1", + "IOI_ILOGIC1_CLKDIVP", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "IOI_EL1BEG0_1", + "IOI_NE4C0_1", + "IOI_WL1END0_1", + "IOI_IMUX32_0", + "RIOI_PD_INT_EN_0", + "IOI_ODELAY1_CNTVALUEOUT3", + "IOI_LOGIC_OUTS3_1", + "IOI_EE4BEG1_1", + "IOI_IMUX7_1", + "IOI_WW4B0_1", + "IOI_LOGIC_OUTS4_0", + "IOI_LOGIC_OUTS12_1", + "IOI_SW2A1_1", + "IOI_ILOGIC1_CE1", + "IOI_WW4END0_1", + "IOI_IMUX18_0", + "RIOI_IDELAY0_IFDLY2", + "IOI_RCLK_FORIO3", + "IOI_ODELAY1_LDPIPEEN", + "IOI_WW2A0_1", + "IOI_ER1BEG2_1", + "RIOI_ILOGIC1_OFB", + "IOI_IMUX25_1", + "IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_LH11_1", + "IOI_OLOGIC1_D6", + "IOI_LOGIC_OUTS15_1", + "IOI_IMUX12_1", + "IOI_IMUX1_1", + "IOI_SE4C3_1", + "IOI_WR1END1_0", + "IOI_LH8_1", + "IOI_EE4A1_0", + "IOI_SE2A1_1", + "IOI_SW4END3_0", + "IOI_LH1_1", + "IOI_LH8_0", + "IOI_DCI_TSTRST0", + "IOI_LOGIC_OUTS23_1", + "IOI_LH2_0", + "IOI_BYP7_1", + "IOI_OCLKM_0", + "IOI_SW4END2_1", + "IOI_EE4A3_0", + "IOI_IMUX1_0", + "IOI_BYP3_0", + "IOI_NE2A2_0", + "IOI_ER1BEG0_0", + "RIOI_OSOUT20", + "IOI_NW4END2_0", + "IOI_ER1BEG3_0", + "IOI_EE2A2_1", + "RIOI_IBUF1", + "IOI_FAN2_0", + "IOI_SW2A1_0", + "IOI_ODELAY1_CLKIN", + "IOI_CTRL1_0", + "IOI_WW2A2_1", + "IOI_OLOGIC0_OCE", + "IOI_OCLKM_1", + "IOI_IMUX41_0", + "IOI_NW2A0_1", + "IOI_IMUX24_0", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WW2A3_0", + "IOI_OLOGIC1_D3", + "RIOI_OLOGIC0_TFB", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_LH9_1", + "RIOI_IBUF0", + "IOI_IMUX5_0", + "IOI_OLOGIC1_T4", + "IOI_LOGIC_OUTS20_1", + "IOI_IMUX9_1", + "IOI_SW4A1_0", + "RIOI_OLOGIC1_OFB", + "IOI_LH11_0", + "IOI_OLOGIC1_T1", + "IOI_EE4C1_0", + "IOI_IDELAY1_CNTVALUEIN1", + "IOI_BYP2_0", + "RIOI_ILOGIC1_TFB", + "IOI_RCLK_DIV_CLR1_1", + "RIOI_O1", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_WW4B3_1", + "IOI_ODELAY0_CNTVALUEIN0", + "IOI_EE4C1_1", + "IOI_WW4B2_1", + "IOI_IMUX36_1", + "RIOI_ILOGIC0_D", + "IOI_BLOCK_OUTS1_1", + "RIOI_ISIN10", + "IOI_LOGIC_OUTS18_0", + "IOI_IMUX27_1", + "IOI_EL1BEG1_1", + "RIOI_ISOUT20", + "IOI_LOGIC_OUTS16_0", + "IOI_PHASER_TO_IO_ICLKDIV", + "IOI_LOGIC_OUTS1_0", + "RIOI_OLOGIC1_CLKDIVF", + "IOI_EE4BEG3_0", + "IOI_ER1BEG2_0", + "IOI_EE4BEG2_0", + "IOI_DCI_TSTHLP", + "IOI_EE2A0_0", + "IOI_WW4A0_1", + "IOI_LOGIC_OUTS11_1", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_IDELAY0_CNTVALUEIN0", + "IOI_IOCLK0", + "IOI_IMUX37_0", + "IOI_OLOGIC1_D8", + "IOI_ODELAY1_CNTVALUEIN4", + "RIOI_OSOUT10", + "IOI_LOGIC_OUTS7_0", + "IOI_NE4BEG2_0", + "IOI_EE2BEG0_0", + "IOI_ILOGIC1_SR", + "RIOI_IDELAY1_DATAOUT", + "IOI_OLOGIC0_T1", + "IOI_OLOGIC1_CLKDIVB", + "RIOI_ODELAY1_OFDLY0", + "IOI_NE4C3_0", + "IOI_ILOGIC0_SR", + "IOI_ODELAY1_C", + "IOI_EE2A2_0", + "IOI_IMUX6_0", + "IOI_LOGIC_OUTS13_1", + "IOI_LH7_1", + "IOI_NW4END0_0", + "IOI_NE2A3_0", + "IOI_NW2A3_1", + "IOI_LOGIC_OUTS19_1", + "IOI_LEAF_GCLK2", + "IOI_OLOGIC0_SR", + "IOI_EE2BEG0_1", + "RIOI_ODELAY1_OFDLY2", + "IOI_NE4BEG3_0", + "IOI_ILOGIC0_Q8", + "IOI_INT_DCI_EN", + "IOI_SW2A0_0", + "IOI_ODELAY0_CNTVALUEIN4", + "IOI_WW4END2_0", + "IOI_FAN7_1", + "IOI_IMUX23_1", + "IOI_BYP7_0", + "IOI_IMUX18_1", + "IOI_ILOGIC1_DYNCLKDIVSEL", + "IOI_NW4END0_1", + "IOI_OCLK_1", + "IOI_IMUX21_1", + "IOI_FAN7_0", + "IOI_NW4END1_0", + "IOI_IDELAY1_CNTVALUEIN3", + "IOI_ILOGIC1_OCLK", + "IOI_LOGIC_OUTS17_0", + "IOI_NE4BEG0_1", + "IOI_PHASER_TO_IO_ICLK_0", + "IOI_EE4B0_1", + "IOI_OLOGIC0_D3", + "IOI_LOGIC_OUTS17_1", + "IOI_EE2A1_0", + "IOI_WW4A1_1", + "IOI_OLOGIC0_TBYTEIN", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_ER1BEG1_1", + "IOI_CTRL0_1", + "IOI_IMUX14_1", + "IOI_OLOGIC1_D5", + "IOI_OCLK_0", + "IOI_IDELAY1_INC", + "IOI_NE4C0_0", + "IOI_LH4_0", + "IOI_OLOGIC0_T4" + ], + "pips": { + "RIOI_TBYTESRC.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { + "src_wire": "IOI_ILOGIC1_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { + "src_wire": "RIOI_OLOGIC1_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX21_0->IOI_OLOGIC1_T4": { + "src_wire": "IOI_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC0_O->RIOI_I2GCLK_TOP0": { + "src_wire": "IOI_ILOGIC0_O", + "is_pseudo": "0", + "dst_wire": "RIOI_I2GCLK_TOP0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_CTRL1_0->IOI_ILOGIC1_SR": { + "src_wire": "IOI_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR1_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX19_1->IOI_ODELAY0_CNTVALUEIN3": { + "src_wire": "IOI_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { + "src_wire": "IOI_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC1_TQ->>RIOI_T1": { + "src_wire": "RIOI_OLOGIC1_TQ", + "is_pseudo": "0", + "dst_wire": "RIOI_T1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_FAN4_0->RIOI_IDELAY1_IFDLY0": { + "src_wire": "IOI_FAN4_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { + "src_wire": "IOI_ILOGIC0_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP2_1->IOI_ODELAY0_CINVCTRL": { + "src_wire": "IOI_BYP2_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { + "src_wire": "IOI_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { + "src_wire": "IOI_ILOGIC1_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX28_1->IOI_ODELAY0_LD": { + "src_wire": "IOI_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS4_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS4_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLKM_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX11_0->IOI_ODELAY1_REGRST": { + "src_wire": "IOI_IMUX11_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX21_1->IOI_OLOGIC0_T4": { + "src_wire": "IOI_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE2_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP4_1->IOI_IMUX_RC2": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_I0->RIOI_ILOGIC0_D": { + "src_wire": "RIOI_I0", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_D", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX11_1->IOI_ODELAY0_REGRST": { + "src_wire": "IOI_IMUX11_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_FAN5_0->RIOI_IDELAY1_IFDLY1": { + "src_wire": "IOI_FAN5_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS6_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS6_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX26_0->IOI_IDELAY1_INC": { + "src_wire": "IOI_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { + "src_wire": "IOI_ILOGIC1_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { + "src_wire": "RIOI_OLOGIC0_TFB", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX32_0->IOI_IDELAY1_CE": { + "src_wire": "IOI_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { + "src_wire": "RIOI_OLOGIC1_TQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { + "src_wire": "IOI_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { + "src_wire": "RIOI_ILOGIC1_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP3_1->IOI_IMUX_RC3": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { + "src_wire": "IOI_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { + "src_wire": "IOI_OLOGIC1_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX16_1->IOI_ODELAY0_CNTVALUEIN1": { + "src_wire": "IOI_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { + "src_wire": "IOI_ILOGIC0_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_IDELAY1_DATAOUT->RIOI_ILOGIC1_DDLY": { + "src_wire": "RIOI_IDELAY1_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP5_0->RIOI_ODELAY1_OFDLY2": { + "src_wire": "IOI_BYP5_0", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY1_OFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_CTRL1_1->IOI_ILOGIC0_SR": { + "src_wire": "IOI_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { + "src_wire": "IOI_ILOGIC1_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC1_OQ->>RIOI_O1": { + "src_wire": "RIOI_OLOGIC1_OQ", + "is_pseudo": "0", + "dst_wire": "RIOI_O1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { + "src_wire": "IOI_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX31_0->>IOI_OCLKM_1": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX43_0->IOI_OLOGIC1_D5": { + "src_wire": "IOI_IMUX43_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D5", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { + "src_wire": "RIOI_ILOGIC1_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { + "src_wire": "IOI_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_CLK1_1->IOI_IDELAY0_C": { + "src_wire": "IOI_CLK1_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { + "src_wire": "RIOI_OLOGIC1_OQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC1_OFB->RIOI_ODELAY1_ODATAIN": { + "src_wire": "RIOI_OLOGIC1_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY1_ODATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS4_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS4_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_CTRL0_0->IOI_OLOGIC1_SR": { + "src_wire": "IOI_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP3_0->IOI_IMUX_RC0": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX43_1->IOI_OLOGIC0_D5": { + "src_wire": "IOI_IMUX43_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX32_1->IOI_IDELAY0_CE": { + "src_wire": "IOI_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { + "src_wire": "IOI_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLK": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLK_1->IOI_ODELAY1_CLKIN": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CLKIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_CLK1_0->IOI_ODELAY1_C": { + "src_wire": "IOI_CLK1_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { + "src_wire": "IOI_OLOGIC1_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX7_0->IOI_OLOGIC1_T2": { + "src_wire": "IOI_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { + "src_wire": "IOI_BYP6_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX47_1->IOI_OLOGIC0_D8": { + "src_wire": "IOI_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_CTRL0_1->IOI_OLOGIC0_SR": { + "src_wire": "IOI_CTRL0_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX27_1->IOI_ODELAY0_LDPIPEEN": { + "src_wire": "IOI_IMUX27_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP7_0->RIOI_IDELAY1_IFDLY2": { + "src_wire": "IOI_BYP7_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_I1->RIOI_ILOGIC1_D": { + "src_wire": "RIOI_I1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_D", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX7_1->IOI_OLOGIC0_T2": { + "src_wire": "IOI_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX28_0->IOI_ODELAY1_LD": { + "src_wire": "IOI_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX42_1->IOI_OLOGIC0_D4": { + "src_wire": "IOI_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { + "src_wire": "RIOI_IDELAY0_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { + "src_wire": "IOI_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX27_0->IOI_ODELAY1_LDPIPEEN": { + "src_wire": "IOI_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX40_0->IOI_OLOGIC1_D2": { + "src_wire": "IOI_IMUX40_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX3_0->IOI_ODELAY1_INC": { + "src_wire": "IOI_IMUX3_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { + "src_wire": "IOI_OLOGIC1_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS17_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS17_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { + "src_wire": "IOI_ILOGIC0_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX40_1->IOI_OLOGIC0_D2": { + "src_wire": "IOI_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS17_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS17_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX3_1->IOI_ODELAY0_INC": { + "src_wire": "IOI_IMUX3_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { + "src_wire": "IOI_TBYTEIN", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX31_1->>IOI_OCLKM_0": { + "src_wire": "IOI_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS12_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS12_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { + "src_wire": "IOI_TBYTEIN", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX47_0->IOI_OLOGIC1_D8": { + "src_wire": "IOI_IMUX47_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D8", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP0_1->RIOI_ODELAY0_OFDLY0": { + "src_wire": "IOI_BYP0_1", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_OFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP1_1->RIOI_ODELAY0_OFDLY1": { + "src_wire": "IOI_BYP1_1", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_OFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { + "src_wire": "RIOI_OLOGIC0_OQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_CLK1_0->IOI_IDELAY1_C": { + "src_wire": "IOI_CLK1_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { + "src_wire": "IOI_ILOGIC0_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_I0->RIOI_IDELAY0_IDATAIN": { + "src_wire": "RIOI_I0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { + "src_wire": "IOI_ILOGIC1_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_FAN5_1->RIOI_IDELAY0_IFDLY1": { + "src_wire": "IOI_FAN5_1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX18_0->IOI_ODELAY1_CNTVALUEIN4": { + "src_wire": "IOI_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { + "src_wire": "IOI_ILOGIC1_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX30_1->IOI_IDELAY0_LD": { + "src_wire": "IOI_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX34_1->IOI_OLOGIC0_D1": { + "src_wire": "IOI_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { + "src_wire": "RIOI_OLOGIC1_TFB", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OSOUT11->RIOI_OSIN10": { + "src_wire": "RIOI_OSOUT11", + "is_pseudo": "0", + "dst_wire": "RIOI_OSIN10", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX13_1->IOI_OLOGIC0_T3": { + "src_wire": "IOI_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { + "src_wire": "IOI_ILOGIC1_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_IDELAY1_IDATAIN->>RIOI_IDELAY1_DATAOUT": { + "src_wire": "RIOI_IDELAY1_IDATAIN", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY1_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX17_1->IOI_ODELAY0_CNTVALUEIN2": { + "src_wire": "IOI_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_I1->RIOI_IDELAY1_IDATAIN": { + "src_wire": "RIOI_I1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { + "src_wire": "IOI_OLOGIC1_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX2_0->IOI_ODELAY1_CE": { + "src_wire": "IOI_IMUX2_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { + "src_wire": "IOI_ILOGIC1_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { + "src_wire": "RIOI_OLOGIC0_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { + "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { + "src_wire": "IOI_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX23_1->IOI_ODELAY0_CNTVALUEIN0": { + "src_wire": "IOI_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX42_0->IOI_OLOGIC1_D4": { + "src_wire": "IOI_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { + "src_wire": "IOI_IMUX9_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP0_0->RIOI_ODELAY1_OFDLY0": { + "src_wire": "IOI_BYP0_0", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY1_OFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX2_1->IOI_ODELAY0_CE": { + "src_wire": "IOI_IMUX2_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OSOUT21->RIOI_OSIN20": { + "src_wire": "RIOI_OSOUT21", + "is_pseudo": "0", + "dst_wire": "RIOI_OSIN20", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX13_0->IOI_OLOGIC1_T3": { + "src_wire": "IOI_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS6_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS6_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC0_OQ->>RIOI_O0": { + "src_wire": "RIOI_OLOGIC0_OQ", + "is_pseudo": "0", + "dst_wire": "RIOI_O0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { + "src_wire": "IOI_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX44_0->IOI_OLOGIC1_D3": { + "src_wire": "IOI_IMUX44_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "src_wire": "RIOI_ILOGIC0_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "src_wire": "RIOI_ILOGIC0_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { + "src_wire": "IOI_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX15_1->IOI_OLOGIC0_T1": { + "src_wire": "IOI_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP2_0->IOI_ODELAY1_CINVCTRL": { + "src_wire": "IOI_BYP2_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_CLK1_1->IOI_ODELAY0_C": { + "src_wire": "IOI_CLK1_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP4_0->IOI_IMUX_RC1": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { + "src_wire": "RIOI_OLOGIC0_TQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR0_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { + "src_wire": "IOI_ILOGIC0_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX30_0->IOI_IDELAY1_LD": { + "src_wire": "IOI_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { + "src_wire": "IOI_ILOGIC0_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS21_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS21_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX44_1->IOI_OLOGIC0_D3": { + "src_wire": "IOI_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP5_1->RIOI_ODELAY0_OFDLY2": { + "src_wire": "IOI_BYP5_1", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_OFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX34_0->IOI_OLOGIC1_D1": { + "src_wire": "IOI_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { + "src_wire": "IOI_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OLOGIC1_TBYTEOUT->>IOI_TBYTEIN": { + "src_wire": "IOI_OLOGIC1_TBYTEOUT", + "is_pseudo": "0", + "dst_wire": "IOI_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS12_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS12_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { + "src_wire": "IOI_ILOGIC0_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_ODELAY1_DATAOUT->RIOI_O1": { + "src_wire": "RIOI_ODELAY1_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_O1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX45_1->IOI_OLOGIC0_D6": { + "src_wire": "IOI_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP1_0->RIOI_ODELAY1_OFDLY1": { + "src_wire": "IOI_BYP1_0", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY1_OFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_FAN4_1->RIOI_IDELAY0_IFDLY0": { + "src_wire": "IOI_FAN4_1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX18_1->IOI_ODELAY0_CNTVALUEIN4": { + "src_wire": "IOI_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX46_0->IOI_OLOGIC1_D7": { + "src_wire": "IOI_IMUX46_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D7", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX17_0->IOI_ODELAY1_CNTVALUEIN2": { + "src_wire": "IOI_IMUX17_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { + "src_wire": "IOI_CLK0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_IBUF1->RIOI_I1": { + "src_wire": "RIOI_IBUF1", + "is_pseudo": "0", + "dst_wire": "RIOI_I1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { + "src_wire": "IOI_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_ISOUT10->RIOI_ISIN11": { + "src_wire": "RIOI_ISOUT10", + "is_pseudo": "0", + "dst_wire": "RIOI_ISIN11", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { + "src_wire": "IOI_ILOGIC0_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { + "src_wire": "IOI_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { + "src_wire": "IOI_ILOGIC0_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX31_0->>IOI_OCLK_1": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_CLK0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { + "src_wire": "IOI_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { + "src_wire": "RIOI_IDELAY0_IDATAIN", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_ISOUT20->RIOI_ISIN21": { + "src_wire": "RIOI_ISOUT20", + "is_pseudo": "0", + "dst_wire": "RIOI_ISIN21", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_IBUF0->RIOI_I0": { + "src_wire": "RIOI_IBUF0", + "is_pseudo": "0", + "dst_wire": "RIOI_I0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP7_1->RIOI_IDELAY0_IFDLY2": { + "src_wire": "IOI_BYP7_1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC0_TQ->>RIOI_T0": { + "src_wire": "RIOI_OLOGIC0_TQ", + "is_pseudo": "0", + "dst_wire": "RIOI_T0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX15_0->IOI_OLOGIC1_T1": { + "src_wire": "IOI_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX46_1->IOI_OLOGIC0_D7": { + "src_wire": "IOI_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "src_wire": "IOI_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS21_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS21_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLKM_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE3_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX19_0->IOI_ODELAY1_CNTVALUEIN3": { + "src_wire": "IOI_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_OLOGIC0_OFB->RIOI_ODELAY0_ODATAIN": { + "src_wire": "RIOI_OLOGIC0_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_ODATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { + "src_wire": "IOI_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { + "src_wire": "IOI_ILOGIC1_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { + "src_wire": "IOI_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX45_0->IOI_OLOGIC1_D6": { + "src_wire": "IOI_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D6", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.RIOI_ODELAY0_DATAOUT->RIOI_O0": { + "src_wire": "RIOI_ODELAY0_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_O0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX23_0->IOI_ODELAY1_CNTVALUEIN0": { + "src_wire": "IOI_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { + "src_wire": "IOI_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_OCLK_0->IOI_ODELAY0_CLKIN": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CLKIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX16_0->IOI_ODELAY1_CNTVALUEIN1": { + "src_wire": "IOI_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX26_1->IOI_IDELAY0_INC": { + "src_wire": "IOI_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { + "src_wire": "IOI_BYP6_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX31_1->>IOI_OCLK_0": { + "src_wire": "IOI_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_RIOI_TBYTETERM.json b/kintex7/tile_type_RIOI_TBYTETERM.json new file mode 100644 index 0000000..d6cd27c --- /dev/null +++ b/kintex7/tile_type_RIOI_TBYTETERM.json @@ -0,0 +1,4265 @@ +{ + "tile_type": "RIOI_TBYTETERM", + "sites": [ + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "OLOGIC", + "type": "OLOGICE2", + "site_pins": { + "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", + "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", + "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", + "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", + "OFB": "RIOI_OLOGIC1_OFB", + "T1": "IOI_OLOGIC1_T1", + "D6": "IOI_OLOGIC1_D6", + "SHIFTIN2": null, + "TCE": "IOI_OLOGIC1_TCE", + "OCE": "IOI_OLOGIC1_OCE", + "SHIFTOUT2": "RIOI_OSOUT21", + "REV": null, + "OQ": "RIOI_OLOGIC1_OQ", + "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", + "D7": "IOI_OLOGIC1_D7", + "TQ": "RIOI_OLOGIC1_TQ", + "D3": "IOI_OLOGIC1_D3", + "D4": "IOI_OLOGIC1_D4", + "SR": "IOI_OLOGIC1_SR", + "CLKB": "IOI_OLOGIC1_CLKB", + "SHIFTIN1": null, + "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF", + "D2": "IOI_OLOGIC1_D2", + "CLK": "IOI_OLOGIC1_CLK", + "T4": "IOI_OLOGIC1_T4", + "T2": "IOI_OLOGIC1_T2", + "TFB": "RIOI_OLOGIC1_TFB", + "SHIFTOUT1": "RIOI_OSOUT11", + "T3": "IOI_OLOGIC1_T3", + "D1": "IOI_OLOGIC1_D1", + "D5": "IOI_OLOGIC1_D5", + "CLKDIV": "IOI_OLOGIC1_CLKDIV", + "D8": "IOI_OLOGIC1_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "ODELAY", + "type": "ODELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_ODELAY1_CNTVALUEIN1", + "OFDLY1": "RIOI_ODELAY1_OFDLY1", + "REGRST": "IOI_ODELAY1_REGRST", + "CNTVALUEIN3": "IOI_ODELAY1_CNTVALUEIN3", + "CE": "IOI_ODELAY1_CE", + "C": "IOI_ODELAY1_C", + "ODATAIN": "RIOI_ODELAY1_ODATAIN", + "OFDLY0": "RIOI_ODELAY1_OFDLY0", + "CNTVALUEIN4": "IOI_ODELAY1_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_ODELAY1_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_ODELAY1_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_ODELAY1_CNTVALUEOUT3", + "LD": "IOI_ODELAY1_LD", + "CINVCTRL": "IOI_ODELAY1_CINVCTRL", + "CNTVALUEOUT4": "IOI_ODELAY1_CNTVALUEOUT4", + "DATAOUT": "RIOI_ODELAY1_DATAOUT", + "LDPIPEEN": "IOI_ODELAY1_LDPIPEEN", + "CNTVALUEIN0": "IOI_ODELAY1_CNTVALUEIN0", + "CLKIN": "IOI_ODELAY1_CLKIN", + "INC": "IOI_ODELAY1_INC", + "CNTVALUEOUT2": "IOI_ODELAY1_CNTVALUEOUT2", + "OFDLY2": "RIOI_ODELAY1_OFDLY2", + "CNTVALUEIN2": "IOI_ODELAY1_CNTVALUEIN2" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "ILOGIC", + "type": "ILOGICE2", + "site_pins": { + "Q4": "IOI_ILOGIC1_Q4", + "D": "RIOI_ILOGIC1_D", + "Q5": "IOI_ILOGIC1_Q5", + "SHIFTIN2": "RIOI_ISIN21", + "O": "IOI_ILOGIC1_O", + "Q6": "IOI_ILOGIC1_Q6", + "Q7": "IOI_ILOGIC1_Q7", + "TFB": "RIOI_ILOGIC1_TFB", + "Q2": "IOI_ILOGIC1_Q2", + "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", + "SHIFTIN1": "RIOI_ISIN11", + "Q8": "IOI_ILOGIC1_Q8", + "CE1": "IOI_ILOGIC1_CE1", + "CE2": "IOI_ILOGIC1_CE2", + "SR": "IOI_ILOGIC1_SR", + "Q3": "IOI_ILOGIC1_Q3", + "CLK": "IOI_ILOGIC1_CLK", + "OFB": "RIOI_ILOGIC1_OFB", + "DDLY": "RIOI_ILOGIC1_DDLY", + "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", + "CLKB": "IOI_ILOGIC1_CLKB", + "REV": null, + "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "CLKDIV": "IOI_ILOGIC1_CLKDIV", + "BITSLIP": "IOI_ILOGIC1_BITSLIP", + "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", + "OCLKB": "IOI_ILOGIC1_OCLKB", + "SHIFTOUT1": "RIOI_ISOUT11", + "OCLK": "IOI_ILOGIC1_OCLK", + "Q1": "IOI_ILOGIC1_Q1", + "SHIFTOUT2": "RIOI_ISOUT21" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "OLOGIC", + "type": "OLOGICE2", + "site_pins": { + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "OFB": "RIOI_OLOGIC0_OFB", + "T1": "IOI_OLOGIC0_T1", + "D6": "IOI_OLOGIC0_D6", + "SHIFTIN2": "RIOI_OSIN20", + "TCE": "IOI_OLOGIC0_TCE", + "OCE": "IOI_OLOGIC0_OCE", + "SHIFTOUT2": "RIOI_OSOUT20", + "REV": null, + "OQ": "RIOI_OLOGIC0_OQ", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "TQ": "RIOI_OLOGIC0_TQ", + "D3": "IOI_OLOGIC0_D3", + "D4": "IOI_OLOGIC0_D4", + "SR": "IOI_OLOGIC0_SR", + "CLKB": "IOI_OLOGIC0_CLKB", + "SHIFTIN1": "RIOI_OSIN10", + "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", + "D2": "IOI_OLOGIC0_D2", + "CLK": "IOI_OLOGIC0_CLK", + "T4": "IOI_OLOGIC0_T4", + "T2": "IOI_OLOGIC0_T2", + "TFB": "RIOI_OLOGIC0_TFB", + "SHIFTOUT1": "RIOI_OSOUT10", + "T3": "IOI_OLOGIC0_T3", + "D1": "IOI_OLOGIC0_D1", + "D5": "IOI_OLOGIC0_D5", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "D8": "IOI_OLOGIC0_D8" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "ODELAY", + "type": "ODELAYE2", + "site_pins": { + "CNTVALUEIN1": "IOI_ODELAY0_CNTVALUEIN1", + "OFDLY1": "RIOI_ODELAY0_OFDLY1", + "REGRST": "IOI_ODELAY0_REGRST", + "CNTVALUEIN3": "IOI_ODELAY0_CNTVALUEIN3", + "CE": "IOI_ODELAY0_CE", + "C": "IOI_ODELAY0_C", + "ODATAIN": "RIOI_ODELAY0_ODATAIN", + "OFDLY0": "RIOI_ODELAY0_OFDLY0", + "CNTVALUEIN4": "IOI_ODELAY0_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_ODELAY0_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_ODELAY0_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_ODELAY0_CNTVALUEOUT3", + "LD": "IOI_ODELAY0_LD", + "CINVCTRL": "IOI_ODELAY0_CINVCTRL", + "CNTVALUEOUT4": "IOI_ODELAY0_CNTVALUEOUT4", + "DATAOUT": "RIOI_ODELAY0_DATAOUT", + "LDPIPEEN": "IOI_ODELAY0_LDPIPEEN", + "CNTVALUEIN0": "IOI_ODELAY0_CNTVALUEIN0", + "CLKIN": "IOI_ODELAY0_CLKIN", + "INC": "IOI_ODELAY0_INC", + "CNTVALUEOUT2": "IOI_ODELAY0_CNTVALUEOUT2", + "OFDLY2": "RIOI_ODELAY0_OFDLY2", + "CNTVALUEIN2": "IOI_ODELAY0_CNTVALUEIN2" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "ILOGIC", + "type": "ILOGICE2", + "site_pins": { + "Q4": "IOI_ILOGIC0_Q4", + "D": "RIOI_ILOGIC0_D", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN2": null, + "O": "IOI_ILOGIC0_O", + "Q6": "IOI_ILOGIC0_Q6", + "Q7": "IOI_ILOGIC0_Q7", + "TFB": "RIOI_ILOGIC0_TFB", + "Q2": "IOI_ILOGIC0_Q2", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "SHIFTIN1": null, + "Q8": "IOI_ILOGIC0_Q8", + "CE1": "IOI_ILOGIC0_CE1", + "CE2": "IOI_ILOGIC0_CE2", + "SR": "IOI_ILOGIC0_SR", + "Q3": "IOI_ILOGIC0_Q3", + "CLK": "IOI_ILOGIC0_CLK", + "OFB": "RIOI_ILOGIC0_OFB", + "DDLY": "RIOI_ILOGIC0_DDLY", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "CLKB": "IOI_ILOGIC0_CLKB", + "REV": null, + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "OCLKB": "IOI_ILOGIC0_OCLKB", + "SHIFTOUT1": "RIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "Q1": "IOI_ILOGIC0_Q1", + "SHIFTOUT2": "RIOI_ISOUT20" + }, + "x_coord": 0 + }, + { + "y_coord": 0, + "name": "X0Y0", + "prefix": "IDELAY", + "type": "IDELAYE2_FINEDELAY", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", + "DATAOUT": "RIOI_IDELAY1_DATAOUT", + "IDATAIN": "RIOI_IDELAY1_IDATAIN", + "REGRST": "IOI_IDELAY1_REGRST", + "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", + "C": "IOI_IDELAY1_C", + "IFDLY0": "RIOI_IDELAY1_IFDLY0", + "DATAIN": "IOI_IDELAY1_DATAIN", + "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", + "LD": "IOI_IDELAY1_LD", + "CINVCTRL": "IOI_IDELAY1_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", + "IFDLY1": "RIOI_IDELAY1_IFDLY1", + "IFDLY2": "RIOI_IDELAY1_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", + "INC": "IOI_IDELAY1_INC", + "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", + "CE": "IOI_IDELAY1_CE", + "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2" + }, + "x_coord": 0 + }, + { + "y_coord": 1, + "name": "X0Y1", + "prefix": "IDELAY", + "type": "IDELAYE2_FINEDELAY", + "site_pins": { + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "DATAOUT": "RIOI_IDELAY0_DATAOUT", + "IDATAIN": "RIOI_IDELAY0_IDATAIN", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "C": "IOI_IDELAY0_C", + "IFDLY0": "RIOI_IDELAY0_IFDLY0", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "LD": "IOI_IDELAY0_LD", + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "IFDLY1": "RIOI_IDELAY0_IFDLY1", + "IFDLY2": "RIOI_IDELAY0_IFDLY2", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2" + }, + "x_coord": 0 + } + ], + "wires": [ + "IOI_RCLK_DIV_CLR0_1", + "IOI_WL1END0_0", + "RIOI_OLOGIC0_OQ", + "IOI_IDELAYCTRL_RST", + "RIOI_I2GCLK_BOT1", + "IOI_IMUX12_0", + "IOI_LH12_0", + "IOI_DCI_TSTHLN", + "IOI_IDELAYCTRL_OUTN1", + "IOI_EE2BEG2_0", + "IOI_SE4C2_0", + "IOI_OLOGIC0_D5", + "IOI_IOCLK1", + "IOI_IMUX2_0", + "IOI_WW4A3_0", + "IOI_OLOGIC1_SR", + "RIOI_ODELAY0_OFDLY2", + "IOI_EL1BEG2_0", + "IOI_ILOGIC1_REV", + "IOI_EL1BEG2_1", + "IOI_SE4BEG2_0", + "IOI_IDELAYCTRL_RDY", + "IOI_EE4A0_1", + "IOI_RCLK_DIV_CE1", + "IOI_OLOGIC1_CLKB", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_LOGIC_OUTS8_1", + "IOI_SW4END2_0", + "IOI_IMUX_RC1", + "IOI_ODELAY1_CNTVALUEOUT2", + "RIOI_OSIN20", + "RIOI_IDELAY1_IDATAIN", + "IOI_IMUX39_0", + "IOI_WW4B0_0", + "IOI_ER1BEG3_1", + "IOI_BYP1_1", + "RIOI_ODELAY0_OFDLY0", + "IOI_IMUX5_1", + "IOI_IMUX46_1", + "IOI_PHASER_TO_IO_ICLKDIV_0", + "IOI_ILOGIC0_Q6", + "IOI_IMUX4_0", + "IOI_ODELAY1_CNTVALUEOUT4", + "IOI_NW4END3_1", + "IOI_ILOGIC1_OCLKB", + "IOI_FAN1_0", + "IOI_LOGIC_OUTS19_0", + "IOI_IMUX29_1", + "IOI_IMUX10_1", + "IOI_ILOGIC1_DYNCLKDIVPSEL", + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "RIOI_DIFF_TERM_INT_EN", + "IOI_ILOGIC1_Q1", + "IOI_OLOGIC1_D7", + "RIOI_IDELAY0_IFDLY0", + "IOI_LH5_1", + "IOI_ODELAY0_REGRST", + "IOI_IOCLK2", + "IOI_WW4END0_0", + "RIOI_PU_INT_EN_1", + "RIOI_KEEPER_INT_EN_1", + "IOI_WW4END2_1", + "RIOI_ODELAY1_ODATAIN", + "IOI_IMUX32_1", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS20_0", + "IOI_PHASER_TO_IO_OCLK", + "IOI_LOGIC_OUTS5_1", + "IOI_RCLK_DIV_CE0", + "RIOI_OSOUT11", + "IOI_LOGIC_OUTS9_0", + "IOI_EE2A1_1", + "IOI_EE2A3_1", + "IOI_FAN6_0", + "IOI_WW2END1_0", + "IOI_IOCLK3", + "IOI_WW2END0_1", + "IOI_SE2A3_0", + "IOI_SE4C0_1", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_EE2A0_1", + "IOI_DCI_DCIDONE", + "RIOI_DCI_T_TERM0", + "IOI_IMUX25_0", + "RIOI_OSIN11", + "IOI_LOGIC_OUTS8_0", + "IOI_ODELAY0_CLKIN", + "IOI_BLOCK_OUTS2_0", + "IOI_FAN4_1", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_NE4C2_1", + "IOI_IMUX44_0", + "IOI_IMUX29_0", + "IOI_WR1END2_1", + "IOI_OLOGIC0_CLKDIV", + "IOI_EE4C3_1", + "IOI_EE2BEG3_1", + "IOI_IMUX22_0", + "IOI_ILOGIC0_REV", + "IOI_IMUX15_1", + "IOI_IMUX21_0", + "IOI_BYP4_1", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_ODELAY0_LDPIPEEN", + "IOI_NE2A3_1", + "IOI_ILOGIC1_Q3", + "IOI_BYP2_1", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_WW4A2_0", + "IOI_NE4BEG1_0", + "IOI_LOGIC_OUTS18_1", + "IOI_OLOGIC0_D2", + "RIOI_ILOGIC0_OFB", + "IOI_ILOGIC0_Q7", + "IOI_ILOGIC1_CLK", + "IOI_ODELAY0_CNTVALUEOUT0", + "IOI_ODELAY1_INC", + "IOI_IDELAY0_REGRST", + "IOI_SE4BEG1_1", + "IOI_IMUX33_1", + "IOI_WW4END3_0", + "IOI_TBYTEIN_TERM", + "IOI_WR1END1_1", + "IOI_ILOGIC1_CE2", + "IOI_SE4C0_0", + "IOI_LOGIC_OUTS21_1", + "IOI_ILOGIC0_CLKDIV", + "IOI_SE2A1_0", + "IOI_IMUX8_0", + "IOI_LH5_0", + "IOI_IDELAYCTRL_OUTN65", + "IOI_NE2A1_1", + "IOI_EE4C3_0", + "IOI_LOGIC_OUTS14_1", + "IOI_OLOGIC0_CLKB", + "RIOI_OLOGIC0_CLKDIVF", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_SE4BEG0_0", + "IOI_ILOGIC0_OCLKB", + "IOI_SE4C1_1", + "IOI_IMUX47_1", + "RIOI_OLOGIC1_TFB_LOCAL", + "IOI_CLK1_1", + "IOI_IDELAY1_DATAIN", + "IOI_ODELAY1_CNTVALUEIN0", + "RIOI_ISOUT11", + "IOI_IMUX28_0", + "IOI_LOGIC_OUTS6_1", + "IOI_SE2A2_1", + "IOI_LH9_0", + "RIOI_I0", + "IOI_EE2BEG3_0", + "IOI_SE2A0_1", + "RIOI_ILOGIC0_TFB", + "IOI_IMUX40_1", + "IOI_IMUX8_1", + "IOI_ILOGIC1_DYNCLKSEL", + "IOI_EE2BEG1_1", + "IOI_SW4END1_0", + "IOI_SW4A3_0", + "IOI_IMUX16_0", + "IOI_LOGIC_OUTS0_1", + "IOI_ER1BEG0_1", + "IOI_OLOGIC0_TCE", + "IOI_NW4A1_0", + "IOI_NW2A0_0", + "IOI_IDELAY1_CNTVALUEIN4", + "IOI_EL1BEG0_0", + "IOI_ILOGIC0_CE1", + "IOI_NW4A3_0", + "IOI_IDELAY1_CNTVALUEOUT1", + "IOI_SE2A2_0", + "IOI_WL1END1_1", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_ILOGIC1_O", + "IOI_IDELAY0_INC", + "IOI_IMUX28_1", + "IOI_WW4A1_0", + "IOI_IDELAY1_CNTVALUEOUT0", + "IOI_ODELAY1_CINVCTRL", + "IOI_IMUX37_1", + "IOI_MONITOR_P", + "IOI_EE4C0_1", + "IOI_OLOGIC1_TBYTEOUT", + "IOI_LEAF_GCLK0", + "IOI_LOGIC_OUTS7_1", + "RIOI_ISIN21", + "RIOI_ODELAY1_OFDLY1", + "IOI_IMUX35_1", + "IOI_WW2END3_0", + "IOI_IDELAY1_CNTVALUEOUT4", + "IOI_EE4C2_1", + "IOI_NE4BEG2_1", + "IOI_SE4BEG3_0", + "IOI_ILOGIC1_Q6", + "IOI_ILOGIC0_Q4", + "IOI_SE4BEG0_1", + "IOI_RCLK_DIV_CE2_1", + "RIOI_IDELAY1_IFDLY1", + "IOI_LOGIC_OUTS0_0", + "IOI_BYP4_0", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "RIOI_PD_INT_EN_1", + "IOI_OLOGIC0_D6", + "IOI_WL1END3_1", + "IOI_DCI_TSTCLK", + "IOI_WW4B1_0", + "IOI_WW4C2_1", + "IOI_PHASER_TO_IO_OCLK_0", + "IOI_PHASER_TO_IO_OCLKDIV_0", + "IOI_IMUX45_0", + "IOI_ILOGIC0_Q2", + "IOI_SW2A0_1", + "IOI_SE4BEG1_0", + "IOI_WW2A1_0", + "IOI_LOGIC_OUTS12_0", + "IOI_ILOGIC0_OCLK", + "IOI_EE4B3_0", + "IOI_WW4END1_1", + "IOI_IMUX19_0", + "IOI_NE4C2_0", + "IOI_OLOGIC0_CLK", + "IOI_WL1END1_0", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_IMUX_RC2", + "IOI_IMUX2_1", + "IOI_IMUX35_0", + "IOI_WW4A0_0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_IMUX15_0", + "IOI_WL1END2_0", + "IOI_WW2END3_1", + "IOI_IMUX41_1", + "IOI_WW4END1_0", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS14_0", + "IOI_OLOGIC0_D7", + "IOI_IMUX31_1", + "IOI_SW2A3_0", + "RIOI_IDELAY1_IFDLY2", + "IOI_OLOGIC1_TBYTEIN", + "IOI_SW4A2_1", + "IOI_IDELAY1_LDPIPEEN", + "IOI_IMUX6_1", + "IOI_IMUX_RC0", + "IOI_IMUX9_0", + "IOI_WW2END2_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_EE4BEG2_1", + "IOI_FAN6_1", + "IOI_ODELAY1_REGRST", + "IOI_IMUX11_0", + "IOI_RCLK_FORIO1", + "IOI_SW4A0_1", + "RIOI_OLOGIC0_TFB_LOCAL", + "IOI_WW4C0_1", + "RIOI_IBUF_DISABLE0", + "IOI_IMUX30_1", + "IOI_SE2A3_1", + "IOI_SW4A1_1", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OLOGIC1_D4", + "IOI_WW2A1_1", + "IOI_RCLK_DIV_CLR0", + "IOI_NW2A3_0", + "IOI_OLOGIC1_OCE", + "IOI_IMUX40_0", + "IOI_SW4END0_1", + "IOI_SW4END1_1", + "IOI_ILOGIC1_Q4", + "IOI_LOGIC_OUTS16_1", + "IOI_IMUX20_1", + "IOI_NE4C1_1", + "IOI_ILOGIC1_CLKB", + "IOI_RCLK_DIV_CE3", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_LEAF_GCLK1", + "IOI_ILOGIC0_Q1", + "IOI_EE4BEG0_0", + "RIOI_OLOGIC1_OQ", + "RIOI_ODELAY1_DATAOUT", + "IOI_IMUX46_0", + "IOI_IMUX45_1", + "IOI_EE4BEG3_1", + "IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IMUX38_1", + "RIOI_OLOGIC0_TQ", + "IOI_MONITOR_N", + "IOI_LEAF_GCLK5", + "IOI_ODELAY0_CNTVALUEIN2", + "IOI_WW4A3_1", + "RIOI_OSOUT21", + "IOI_NW4END3_0", + "IOI_WW2A3_1", + "IOI_SE4BEG2_1", + "IOI_BYP5_1", + "IOI_ODELAY0_CINVCTRL", + "IOI_OLOGIC0_D1", + "IOI_WW4A2_1", + "IOI_ODELAY1_CE", + "IOI_WW4C0_0", + "IOI_FAN1_1", + "IOI_IMUX26_0", + "IOI_ODELAY0_LD", + "IOI_EE4B2_0", + "IOI_NW4A0_0", + "IOI_SE2A0_0", + "IOI_EE4C0_0", + "IOI_LOGIC_OUTS21_0", + "RIOI_IBUF_DISABLE1", + "IOI_IDELAY0_LD", + "IOI_IMUX23_0", + "IOI_WR1END0_0", + "IOI_WW4END3_1", + "IOI_ODELAY1_CNTVALUEIN1", + "RIOI_OSIN10", + "IOI_LOGIC_OUTS15_0", + "IOI_OLOGIC1_D1", + "IOI_LOGIC_OUTS23_0", + "IOI_WW2END2_1", + "IOI_DCI_TSTRST", + "IOI_IMUX22_1", + "IOI_LOGIC_OUTS1_1", + "IOI_EE4B1_0", + "IOI_IMUX7_0", + "IOI_EE4A2_1", + "IOI_BLOCK_OUTS1_0", + "IOI_IMUX42_0", + "IOI_SW2A2_1", + "IOI_WW4C1_0", + "IOI_OLOGIC0_REV", + "IOI_BYP0_1", + "IOI_IMUX39_1", + "RIOI_ODELAY0_ODATAIN", + "IOI_NW4A0_1", + "IOI_BYP6_0", + "IOI_IMUX13_1", + "IOI_OLOGIC0_D4", + "RIOI_DCI_T_TERM1", + "IOI_ODELAY0_CNTVALUEIN3", + "RIOI_I1", + "IOI_IMUX24_1", + "IOI_ILOGIC0_CLKDIVP", + "RIOI_ISIN11", + "RIOI_IDELAY0_IFDLY1", + "IOI_IMUX13_0", + "IOI_RCLK_DIV_CE2", + "IOI_IDELAY1_REGRST", + "IOI_WR1END3_1", + "RIOI_OLOGIC1_TQ", + "RIOI_KEEPER_INT_EN_0", + "IOI_IDELAY1_C", + "IOI_IDELAY1_LD", + "IOI_IMUX47_0", + "IOI_ILOGIC0_O", + "IOI_ILOGIC1_Q8", + "IOI_BYP0_0", + "IOI_IMUX27_0", + "IOI_SW4END3_1", + "IOI_LH1_0", + "RIOI_IDELAY1_IFDLY0", + "IOI_SW4A0_0", + "IOI_SE4BEG3_1", + "IOI_IDELAY1_CNTVALUEIN0", + "IOI_SW4END0_0", + "IOI_WW4B1_1", + "IOI_IDELAY0_DATAIN", + "IOI_SW4A2_0", + "IOI_LOGIC_OUTS10_0", + "IOI_CLK0_1", + "IOI_IMUX11_1", + "IOI_WW4C1_1", + "IOI_OLOGIC0_T2", + "IOI_BYP6_1", + "IOI_LOGIC_OUTS2_0", + "IOI_BLOCK_OUTS0_0", + "IOI_NW4A3_1", + "IOI_ODELAY0_CE", + "IOI_ILOGIC1_BITSLIP", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_OLOGIC1_CLK", + "IOI_ILOGIC1_CLKDIV", + "IOI_IMUX20_0", + "IOI_LOGIC_OUTS10_1", + "RIOI_IDELAY0_DATAOUT", + "IOI_IDELAY0_LDPIPEEN", + "IOI_LOGIC_OUTS6_0", + "IOI_EL1BEG3_1", + "IOI_ILOGIC0_CLKB", + "IOI_LH6_0", + "IOI_EE4A2_0", + "IOI_LOGIC_OUTS22_0", + "IOI_NW2A1_0", + "IOI_WW2A0_0", + "IOI_PHASER_TO_IO_OCLK1X_90", + "IOI_ILOGIC1_Q5", + "IOI_CTRL0_0", + "IOI_IDELAY0_CE", + "IOI_ILOGIC0_BITSLIP", + "IOI_IMUX14_0", + "IOI_LOGIC_OUTS3_0", + "IOI_IMUX4_1", + "IOI_IMUX3_1", + "IOI_IMUX34_0", + "IOI_WL1END3_0", + "IOI_OLOGIC0_D8", + "IOI_IMUX17_1", + "RIOI_OLOGIC1_TFB", + "IOI_OLOGIC1_TCE", + "IOI_LOGIC_OUTS4_1", + "IOI_OLOGIC0_T3", + "IOI_LOGIC_OUTS5_0", + "IOI_ILOGIC0_Q5", + "RIOI_IDELAY0_IDATAIN", + "IOI_IMUX43_1", + "IOI_ODELAY0_C", + "IOI_EE2BEG2_1", + "IOI_LOGIC_OUTS22_1", + "IOI_FAN3_0", + "IOI_SW2A3_1", + "IOI_LOGIC_OUTS13_0", + "IOI_ODELAY1_LD", + "IOI_IDELAY1_CNTVALUEOUT3", + "IOI_ILOGIC1_Q2", + "IOI_ODELAY1_CNTVALUEIN3", + "IOI_EE4A3_1", + "IOI_WR1END3_0", + "IOI_IDELAY0_C", + "IOI_WW2END0_0", + "IOI_FAN0_1", + "IOI_ILOGIC0_Q3", + "IOI_IDELAY0_CINVCTRL", + "IOI_NW2A1_1", + "IOI_IMUX26_1", + "IOI_EE2BEG1_0", + "IOI_OLOGIC1_IOCLKGLITCH", + "IOI_FAN3_1", + "IOI_NE2A0_1", + "IOI_WR1END2_0", + "IOI_ODELAY1_CNTVALUEIN2", + "IOI_CTRL1_1", + "IOI_ODELAY0_INC", + "IOI_IMUX0_0", + "IOI_BYP3_1", + "IOI_IMUX19_1", + "IOI_LH7_0", + "IOI_SE4C2_1", + "IOI_BLOCK_OUTS2_1", + "IOI_WW4C2_0", + "IOI_NW2A2_0", + "IOI_NW4END2_1", + "IOI_NE4BEG1_1", + "IOI_NW4A1_1", + "IOI_IMUX3_0", + "IOI_OLOGIC1_CLKDIV", + "IOI_LEAF_GCLK4", + "RIOI_PU_INT_EN_0", + "IOI_WW4C3_0", + "IOI_EL1BEG1_0", + "IOI_IMUX0_1", + "IOI_WR1END0_1", + "IOI_LH4_1", + "IOI_IDELAY1_CE", + "IOI_NE4C3_1", + "IOI_BLOCK_OUTS0_1", + "IOI_IDELAY1_CINVCTRL", + "IOI_LH3_0", + "IOI_NE2A1_0", + "RIOI_OLOGIC0_OFB", + "IOI_IMUX43_0", + "IOI_RCLK_DIV_CLR2", + "IOI_NE4BEG3_1", + "IOI_IMUX_RC3", + "RIOI_OSIN21", + "IOI_LOGIC_OUTS9_1", + "IOI_BLOCK_OUTS3_1", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_OLOGIC1_T3", + "IOI_NE4BEG0_0", + "IOI_NE4C1_0", + "IOI_IMUX38_0", + "IOI_LH10_1", + "IOI_IMUX34_1", + "IOI_SE4C3_0", + "IOI_ILOGIC1_Q7", + "IOI_EL1BEG3_0", + "IOI_LOGIC_OUTS11_0", + "IOI_EE4BEG1_0", + "IOI_FAN0_0", + "IOI_FAN2_1", + "IOI_IDELAY1_CNTVALUEIN2", + "IOI_IMUX10_0", + "IOI_EE4B3_1", + "RIOI_O0", + "IOI_IMUX44_1", + "RIOI_ISOUT10", + "IOI_IMUX31_0", + "IOI_WW2END1_1", + "IOI_ER1BEG1_0", + "RIOI_I2GCLK_TOP0", + "IOI_NW2A2_1", + "RIOI_ILOGIC1_DDLY", + "IOI_WW4B3_0", + "IOI_RCLK_FORIO0", + "RIOI_ILOGIC0_DDLY", + "IOI_SE4C1_0", + "IOI_ILOGIC0_CE2", + "IOI_ODELAY1_CNTVALUEOUT0", + "IOI_IMUX16_1", + "IOI_FAN5_1", + "IOI_RCLK_DIV_CE3_1", + "IOI_IMUX42_1", + "IOI_FAN4_0", + "IOI_OLOGIC1_D2", + "IOI_IMUX17_0", + "RIOI_ILOGIC1_D", + "IOI_WW4C3_1", + "IOI_OLOGIC0_CLKDIVB", + "IOI_LH12_1", + "IOI_EE4B1_1", + "RIOI_ISIN20", + "IOI_NW4A2_0", + "IOI_LH2_1", + "IOI_EE4B0_0", + "RIOI_ISOUT21", + "RIOI_ODELAY0_OFDLY1", + "IOI_EE4BEG0_1", + "IOI_OLOGIC1_REV", + "IOI_WW4B2_0", + "IOI_NE2A0_0", + "IOI_FAN5_0", + "IOI_IMUX36_0", + "IOI_NW4A2_1", + "IOI_IMUX33_0", + "IOI_BYP1_0", + "IOI_OLOGIC1_T2", + "IOI_RCLK_FORIO2", + "IOI_EE2A3_0", + "IOI_RCLK_DIV_CLR1", + "IOI_IDELAY1_CNTVALUEOUT2", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_NE2A2_1", + "IOI_WW2A2_0", + "IOI_EE4A1_1", + "IOI_EE4B2_1", + "IOI_LEAF_GCLK3", + "IOI_NW4END1_1", + "IOI_ODELAY1_CNTVALUEOUT1", + "IOI_WL1END2_1", + "IOI_LH3_1", + "IOI_LH6_1", + "IOI_RCLK_DIV_CLR3", + "RIOI_T1", + "RIOI_ODELAY0_DATAOUT", + "IOI_EE4A0_0", + "IOI_CLK0_0", + "IOI_IMUX30_0", + "IOI_LH10_0", + "IOI_OLOGIC1_CLKDIVFB", + "RIOI_T0", + "IOI_BYP5_0", + "IOI_BLOCK_OUTS3_0", + "IOI_SW4A3_1", + "IOI_CLK1_0", + "RIOI_I2GCLK_TOP1", + "IOI_LOGIC_OUTS2_1", + "IOI_ILOGIC1_CLKDIVP", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "IOI_EL1BEG0_1", + "IOI_NE4C0_1", + "IOI_WL1END0_1", + "IOI_IMUX32_0", + "RIOI_PD_INT_EN_0", + "IOI_ODELAY1_CNTVALUEOUT3", + "IOI_LOGIC_OUTS3_1", + "IOI_EE4BEG1_1", + "IOI_IMUX7_1", + "IOI_WW4B0_1", + "IOI_LOGIC_OUTS4_0", + "IOI_LOGIC_OUTS12_1", + "IOI_SW2A1_1", + "IOI_ILOGIC1_CE1", + "IOI_WW4END0_1", + "IOI_IMUX18_0", + "RIOI_IDELAY0_IFDLY2", + "IOI_RCLK_FORIO3", + "IOI_ODELAY1_LDPIPEEN", + "IOI_WW2A0_1", + "IOI_ER1BEG2_1", + "RIOI_ILOGIC1_OFB", + "IOI_IMUX25_1", + "IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_LH11_1", + "IOI_OLOGIC1_D6", + "IOI_LOGIC_OUTS15_1", + "IOI_IMUX12_1", + "IOI_IMUX1_1", + "IOI_SE4C3_1", + "IOI_WR1END1_0", + "IOI_LH8_1", + "IOI_EE4A1_0", + "IOI_SE2A1_1", + "IOI_SW4END3_0", + "IOI_LH1_1", + "IOI_LH8_0", + "IOI_DCI_TSTRST0", + "IOI_LOGIC_OUTS23_1", + "IOI_LH2_0", + "IOI_BYP7_1", + "IOI_OCLKM_0", + "IOI_SW4END2_1", + "IOI_EE4A3_0", + "IOI_IMUX1_0", + "IOI_BYP3_0", + "IOI_NE2A2_0", + "IOI_ER1BEG0_0", + "RIOI_OSOUT20", + "IOI_NW4END2_0", + "IOI_ER1BEG3_0", + "IOI_EE2A2_1", + "RIOI_IBUF1", + "IOI_FAN2_0", + "IOI_SW2A1_0", + "IOI_ODELAY1_CLKIN", + "IOI_CTRL1_0", + "IOI_WW2A2_1", + "IOI_OLOGIC0_OCE", + "IOI_OCLKM_1", + "IOI_IMUX41_0", + "IOI_NW2A0_1", + "IOI_IMUX24_0", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WW2A3_0", + "IOI_OLOGIC1_D3", + "RIOI_OLOGIC0_TFB", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_LH9_1", + "RIOI_IBUF0", + "IOI_IMUX5_0", + "IOI_OLOGIC1_T4", + "IOI_LOGIC_OUTS20_1", + "IOI_IMUX9_1", + "IOI_SW4A1_0", + "RIOI_OLOGIC1_OFB", + "IOI_LH11_0", + "IOI_OLOGIC1_T1", + "IOI_EE4C1_0", + "IOI_IDELAY1_CNTVALUEIN1", + "IOI_BYP2_0", + "RIOI_ILOGIC1_TFB", + "IOI_RCLK_DIV_CLR1_1", + "RIOI_O1", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_WW4B3_1", + "IOI_ODELAY0_CNTVALUEIN0", + "IOI_EE4C1_1", + "IOI_WW4B2_1", + "IOI_IMUX36_1", + "RIOI_ILOGIC0_D", + "IOI_BLOCK_OUTS1_1", + "RIOI_ISIN10", + "IOI_LOGIC_OUTS18_0", + "IOI_IMUX27_1", + "IOI_EL1BEG1_1", + "RIOI_ISOUT20", + "IOI_LOGIC_OUTS16_0", + "IOI_PHASER_TO_IO_ICLKDIV", + "IOI_LOGIC_OUTS1_0", + "RIOI_OLOGIC1_CLKDIVF", + "IOI_EE4BEG3_0", + "IOI_ER1BEG2_0", + "IOI_EE4BEG2_0", + "IOI_DCI_TSTHLP", + "IOI_EE2A0_0", + "IOI_WW4A0_1", + "IOI_LOGIC_OUTS11_1", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_IDELAY0_CNTVALUEIN0", + "IOI_IOCLK0", + "IOI_IMUX37_0", + "IOI_OLOGIC1_D8", + "IOI_ODELAY1_CNTVALUEIN4", + "RIOI_OSOUT10", + "IOI_LOGIC_OUTS7_0", + "IOI_NE4BEG2_0", + "IOI_EE2BEG0_0", + "IOI_ILOGIC1_SR", + "RIOI_IDELAY1_DATAOUT", + "IOI_OLOGIC0_T1", + "IOI_OLOGIC1_CLKDIVB", + "RIOI_ODELAY1_OFDLY0", + "IOI_NE4C3_0", + "IOI_ILOGIC0_SR", + "IOI_ODELAY1_C", + "IOI_EE2A2_0", + "IOI_IMUX6_0", + "IOI_LOGIC_OUTS13_1", + "IOI_LH7_1", + "IOI_NW4END0_0", + "IOI_NE2A3_0", + "IOI_NW2A3_1", + "IOI_LOGIC_OUTS19_1", + "IOI_LEAF_GCLK2", + "IOI_OLOGIC0_SR", + "IOI_EE2BEG0_1", + "RIOI_ODELAY1_OFDLY2", + "IOI_NE4BEG3_0", + "IOI_ILOGIC0_Q8", + "IOI_INT_DCI_EN", + "IOI_SW2A0_0", + "IOI_ODELAY0_CNTVALUEIN4", + "IOI_WW4END2_0", + "IOI_FAN7_1", + "IOI_IMUX23_1", + "IOI_BYP7_0", + "IOI_IMUX18_1", + "IOI_ILOGIC1_DYNCLKDIVSEL", + "IOI_NW4END0_1", + "IOI_OCLK_1", + "IOI_IMUX21_1", + "IOI_FAN7_0", + "IOI_NW4END1_0", + "IOI_IDELAY1_CNTVALUEIN3", + "IOI_ILOGIC1_OCLK", + "IOI_LOGIC_OUTS17_0", + "IOI_NE4BEG0_1", + "IOI_PHASER_TO_IO_ICLK_0", + "IOI_EE4B0_1", + "IOI_OLOGIC0_D3", + "IOI_LOGIC_OUTS17_1", + "IOI_EE2A1_0", + "IOI_WW4A1_1", + "IOI_OLOGIC0_TBYTEIN", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_ER1BEG1_1", + "IOI_CTRL0_1", + "IOI_IMUX14_1", + "IOI_OLOGIC1_D5", + "IOI_OCLK_0", + "IOI_IDELAY1_INC", + "IOI_NE4C0_0", + "IOI_LH4_0", + "IOI_OLOGIC0_T4" + ], + "pips": { + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "src_wire": "IOI_IMUX14_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP1_0->RIOI_ODELAY1_OFDLY1": { + "src_wire": "IOI_BYP1_0", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY1_OFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "src_wire": "RIOI_ILOGIC0_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { + "src_wire": "IOI_OLOGIC1_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX13_0->IOI_OLOGIC1_T3": { + "src_wire": "IOI_IMUX13_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { + "src_wire": "IOI_ILOGIC1_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_FAN4_1->RIOI_IDELAY0_IFDLY0": { + "src_wire": "IOI_FAN4_1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_FAN5_0->RIOI_IDELAY1_IFDLY1": { + "src_wire": "IOI_FAN5_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { + "src_wire": "IOI_ILOGIC1_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX2_1->IOI_ODELAY0_CE": { + "src_wire": "IOI_IMUX2_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX27_0->IOI_ODELAY1_LDPIPEEN": { + "src_wire": "IOI_IMUX27_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { + "src_wire": "IOI_ILOGIC0_Q2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLK": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX15_1->IOI_OLOGIC0_T1": { + "src_wire": "IOI_IMUX15_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { + "src_wire": "IOI_ILOGIC0_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { + "src_wire": "IOI_BYP6_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS21_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS21_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX31_0->>IOI_OCLKM_1": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX11_1->IOI_ODELAY0_REGRST": { + "src_wire": "IOI_IMUX11_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { + "src_wire": "RIOI_IDELAY0_IDATAIN", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { + "src_wire": "IOI_IMUX1_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { + "src_wire": "IOI_IMUX9_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX31_0->>IOI_OCLK_1": { + "src_wire": "IOI_IMUX31_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { + "src_wire": "IOI_IMUX0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_I1->RIOI_IDELAY1_IDATAIN": { + "src_wire": "RIOI_I1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_ODELAY1_DATAOUT->RIOI_O1": { + "src_wire": "RIOI_ODELAY1_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_O1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX44_1->IOI_OLOGIC0_D3": { + "src_wire": "IOI_IMUX44_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OSOUT11->RIOI_OSIN10": { + "src_wire": "RIOI_OSOUT11", + "is_pseudo": "0", + "dst_wire": "RIOI_OSIN10", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { + "src_wire": "IOI_ILOGIC1_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX32_1->IOI_IDELAY0_CE": { + "src_wire": "IOI_IMUX32_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX45_1->IOI_OLOGIC0_D6": { + "src_wire": "IOI_IMUX45_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { + "src_wire": "IOI_IMUX29_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { + "src_wire": "IOI_OLOGIC1_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX11_0->IOI_ODELAY1_REGRST": { + "src_wire": "IOI_IMUX11_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP1_1->RIOI_ODELAY0_OFDLY1": { + "src_wire": "IOI_BYP1_1", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_OFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { + "src_wire": "IOI_IMUX5_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX16_1->IOI_ODELAY0_CNTVALUEIN1": { + "src_wire": "IOI_IMUX16_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { + "src_wire": "IOI_IMUX33_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP0_0->RIOI_ODELAY1_OFDLY0": { + "src_wire": "IOI_BYP0_0", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY1_OFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { + "src_wire": "IOI_IMUX25_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_I1->RIOI_ILOGIC1_D": { + "src_wire": "RIOI_I1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_D", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX34_1->IOI_OLOGIC0_D1": { + "src_wire": "IOI_IMUX34_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS17_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS17_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_TBYTEIN_TERM->>IOI_OLOGIC1_TBYTEIN": { + "src_wire": "IOI_TBYTEIN_TERM", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "src_wire": "RIOI_ILOGIC0_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX20_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX26_1->IOI_IDELAY0_INC": { + "src_wire": "IOI_IMUX26_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP7_1->RIOI_IDELAY0_IFDLY2": { + "src_wire": "IOI_BYP7_1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { + "src_wire": "IOI_ILOGIC0_O", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { + "src_wire": "IOI_ILOGIC1_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { + "src_wire": "RIOI_ILOGIC1_D", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { + "src_wire": "IOI_ILOGIC0_Q7", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { + "src_wire": "RIOI_ILOGIC1_DDLY", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS4_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS4_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { + "src_wire": "IOI_ILOGIC0_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX28_1->IOI_ODELAY0_LD": { + "src_wire": "IOI_IMUX28_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { + "src_wire": "IOI_IMUX9_1", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS6_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS6_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { + "src_wire": "RIOI_OLOGIC1_TQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP4_0->IOI_IMUX_RC1": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_FAN5_1->RIOI_IDELAY0_IFDLY1": { + "src_wire": "IOI_FAN5_1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IFDLY1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { + "src_wire": "IOI_ILOGIC0_Q6", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP4_1->IOI_IMUX_RC2": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_CLK1_0->IOI_ODELAY1_C": { + "src_wire": "IOI_CLK1_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS17_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS17_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS4_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS4_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR0_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_ISOUT10->RIOI_ISIN11": { + "src_wire": "RIOI_ISOUT10", + "is_pseudo": "0", + "dst_wire": "RIOI_ISIN11", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_ISOUT20->RIOI_ISIN21": { + "src_wire": "RIOI_ISOUT20", + "is_pseudo": "0", + "dst_wire": "RIOI_ISIN21", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_CTRL1_0->IOI_ILOGIC1_SR": { + "src_wire": "IOI_CTRL1_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLK_0->IOI_ODELAY0_CLKIN": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CLKIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP2_1->IOI_ODELAY0_CINVCTRL": { + "src_wire": "IOI_BYP2_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX43_0->IOI_OLOGIC1_D5": { + "src_wire": "IOI_IMUX43_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D5", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX19_0->IOI_ODELAY1_CNTVALUEIN3": { + "src_wire": "IOI_IMUX19_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { + "src_wire": "IOI_ILOGIC1_Q5", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OSOUT21->RIOI_OSIN20": { + "src_wire": "RIOI_OSOUT21", + "is_pseudo": "0", + "dst_wire": "RIOI_OSIN20", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { + "src_wire": "IOI_OLOGIC0_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE3_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_CLK0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX28_0->IOI_ODELAY1_LD": { + "src_wire": "IOI_IMUX28_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX16_0->IOI_ODELAY1_CNTVALUEIN1": { + "src_wire": "IOI_IMUX16_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { + "src_wire": "IOI_IMUX29_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { + "src_wire": "IOI_IMUX25_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_DATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX15_0->IOI_OLOGIC1_T1": { + "src_wire": "IOI_IMUX15_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX47_1->IOI_OLOGIC0_D8": { + "src_wire": "IOI_IMUX47_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OQ", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { + "src_wire": "IOI_IMUX5_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { + "src_wire": "IOI_IMUX14_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { + "src_wire": "RIOI_OLOGIC0_OQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX23_0->IOI_ODELAY1_CNTVALUEIN0": { + "src_wire": "IOI_IMUX23_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC1_OQ->>RIOI_O1": { + "src_wire": "RIOI_OLOGIC1_OQ", + "is_pseudo": "0", + "dst_wire": "RIOI_O1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { + "src_wire": "RIOI_OLOGIC0_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX46_0->IOI_OLOGIC1_D7": { + "src_wire": "IOI_IMUX46_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D7", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS12_0": { + "src_wire": "IOI_ODELAY1_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS12_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC1_OFB->RIOI_ODELAY1_ODATAIN": { + "src_wire": "RIOI_OLOGIC1_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY1_ODATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX22_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX30_0->IOI_IDELAY1_LD": { + "src_wire": "IOI_IMUX30_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { + "src_wire": "RIOI_IDELAY0_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { + "src_wire": "IOI_BYP6_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC1_TQ->>RIOI_T1": { + "src_wire": "RIOI_OLOGIC1_TQ", + "is_pseudo": "0", + "dst_wire": "RIOI_T1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX45_0->IOI_OLOGIC1_D6": { + "src_wire": "IOI_IMUX45_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D6", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { + "src_wire": "IOI_IMUX6_0", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX31_1->>IOI_OCLKM_0": { + "src_wire": "IOI_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { + "src_wire": "IOI_ILOGIC1_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_ODELAY0_DATAOUT->RIOI_O0": { + "src_wire": "RIOI_ODELAY0_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_O0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX21_0->IOI_OLOGIC1_T4": { + "src_wire": "IOI_IMUX21_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_IMUX8_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { + "src_wire": "IOI_IMUX12_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLKM_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { + "src_wire": "IOI_CLK0_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX17_0->IOI_ODELAY1_CNTVALUEIN2": { + "src_wire": "IOI_IMUX17_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_IBUF1->RIOI_I1": { + "src_wire": "RIOI_IBUF1", + "is_pseudo": "0", + "dst_wire": "RIOI_I1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_CLK1_1->IOI_ODELAY0_C": { + "src_wire": "IOI_CLK1_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { + "src_wire": "IOI_IMUX33_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { + "src_wire": "RIOI_OLOGIC1_TFB", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { + "src_wire": "IOI_ILOGIC1_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX26_0->IOI_IDELAY1_INC": { + "src_wire": "IOI_IMUX26_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC0_OFB->RIOI_ODELAY0_ODATAIN": { + "src_wire": "RIOI_OLOGIC0_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_ODATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { + "src_wire": "IOI_BYP4_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR1_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP3_0->IOI_IMUX_RC0": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_IDELAY1_DATAOUT->RIOI_ILOGIC1_DDLY": { + "src_wire": "RIOI_IDELAY1_DATAOUT", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_DDLY", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX21_1->IOI_OLOGIC0_T4": { + "src_wire": "IOI_IMUX21_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS12_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT0", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS12_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { + "src_wire": "RIOI_OLOGIC0_TFB", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP5_0->RIOI_ODELAY1_OFDLY2": { + "src_wire": "IOI_BYP5_0", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY1_OFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { + "src_wire": "IOI_OLOGIC1_T1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { + "src_wire": "IOI_IMUX0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { + "src_wire": "IOI_ILOGIC1_Q3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX18_1->IOI_ODELAY0_CNTVALUEIN4": { + "src_wire": "IOI_IMUX18_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { + "src_wire": "IOI_OLOGIC1_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX27_1->IOI_ODELAY0_LDPIPEEN": { + "src_wire": "IOI_IMUX27_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_LDPIPEEN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_I0->RIOI_ILOGIC0_D": { + "src_wire": "RIOI_I0", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_D", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { + "src_wire": "RIOI_OLOGIC1_OFB", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX19_1->IOI_ODELAY0_CNTVALUEIN3": { + "src_wire": "IOI_IMUX19_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { + "src_wire": "IOI_ILOGIC1_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX2_0->IOI_ODELAY1_CE": { + "src_wire": "IOI_IMUX2_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_IBUF0->RIOI_I0": { + "src_wire": "RIOI_IBUF0", + "is_pseudo": "0", + "dst_wire": "RIOI_I0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX18_0->IOI_ODELAY1_CNTVALUEIN4": { + "src_wire": "IOI_IMUX18_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CNTVALUEIN4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { + "src_wire": "IOI_IMUX1_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TCE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX32_0->IOI_IDELAY1_CE": { + "src_wire": "IOI_IMUX32_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CE", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { + "src_wire": "IOI_ILOGIC0_Q1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_I0->RIOI_IDELAY0_IDATAIN": { + "src_wire": "RIOI_I0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX23_1->IOI_ODELAY0_CNTVALUEIN0": { + "src_wire": "IOI_IMUX23_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX31_1->>IOI_OCLK_0": { + "src_wire": "IOI_IMUX31_1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX7_0->IOI_OLOGIC1_T2": { + "src_wire": "IOI_IMUX7_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { + "src_wire": "IOI_BYP3_0", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_TBYTEIN_TERM->>IOI_OLOGIC0_TBYTEIN": { + "src_wire": "IOI_TBYTEIN_TERM", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX47_0->IOI_OLOGIC1_D8": { + "src_wire": "IOI_IMUX47_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D8", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLKM_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { + "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX42_1->IOI_OLOGIC0_D4": { + "src_wire": "IOI_IMUX42_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX22_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_CLK1_0->IOI_IDELAY1_C": { + "src_wire": "IOI_CLK1_0", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX20_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP2_0->IOI_ODELAY1_CINVCTRL": { + "src_wire": "IOI_BYP2_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CINVCTRL", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_IMUX8_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_IDELAY1_IDATAIN->>RIOI_IDELAY1_DATAOUT": { + "src_wire": "RIOI_IDELAY1_IDATAIN", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY1_DATAOUT", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP5_1->RIOI_ODELAY0_OFDLY2": { + "src_wire": "IOI_BYP5_1", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_OFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX13_1->IOI_OLOGIC0_T3": { + "src_wire": "IOI_IMUX13_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { + "src_wire": "IOI_ILOGIC0_Q8", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_FAN4_0->RIOI_IDELAY1_IFDLY0": { + "src_wire": "IOI_FAN4_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX3_0->IOI_ODELAY1_INC": { + "src_wire": "IOI_IMUX3_0", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { + "src_wire": "RIOI_OLOGIC0_TQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX30_1->IOI_IDELAY0_LD": { + "src_wire": "IOI_IMUX30_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP3_1->IOI_IMUX_RC3": { + "src_wire": "IOI_BYP3_1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX3_1->IOI_ODELAY0_INC": { + "src_wire": "IOI_IMUX3_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_INC", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP0_1->RIOI_ODELAY0_OFDLY0": { + "src_wire": "IOI_BYP0_1", + "is_pseudo": "0", + "dst_wire": "RIOI_ODELAY0_OFDLY0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX34_0->IOI_OLOGIC1_D1": { + "src_wire": "IOI_IMUX34_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP7_0->RIOI_IDELAY1_IFDLY2": { + "src_wire": "IOI_BYP7_0", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IFDLY2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS6_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS6_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_CTRL0_0->IOI_OLOGIC1_SR": { + "src_wire": "IOI_CTRL0_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX7_1->IOI_OLOGIC0_T2": { + "src_wire": "IOI_IMUX7_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLK_1->IOI_ODELAY1_CLKIN": { + "src_wire": "IOI_OCLK_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY1_CLKIN", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { + "src_wire": "IOI_OLOGIC0_D1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_CTRL0_1->IOI_OLOGIC0_SR": { + "src_wire": "IOI_CTRL0_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>RIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { + "src_wire": "IOI_ILOGIC0_Q4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX42_0->IOI_OLOGIC1_D4": { + "src_wire": "IOI_IMUX42_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D4", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX44_0->IOI_OLOGIC1_D3": { + "src_wire": "IOI_IMUX44_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D3", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { + "src_wire": "IOI_IMUX6_1", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { + "src_wire": "IOI_BYP4_1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE2_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX46_1->IOI_OLOGIC0_D7": { + "src_wire": "IOI_IMUX46_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX17_1->IOI_ODELAY0_CNTVALUEIN2": { + "src_wire": "IOI_IMUX17_1", + "is_pseudo": "0", + "dst_wire": "IOI_ODELAY0_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "src_wire": "IOI_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS21_1": { + "src_wire": "IOI_ODELAY0_CNTVALUEOUT4", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS21_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC0_TQ->>RIOI_T0": { + "src_wire": "RIOI_OLOGIC0_TQ", + "is_pseudo": "0", + "dst_wire": "RIOI_T0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_CLK1_1->IOI_IDELAY0_C": { + "src_wire": "IOI_CLK1_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX40_0->IOI_OLOGIC1_D2": { + "src_wire": "IOI_IMUX40_0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_CTRL1_1->IOI_ILOGIC0_SR": { + "src_wire": "IOI_CTRL1_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { + "src_wire": "IOI_IMUX12_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO1->>RIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX40_1->IOI_OLOGIC0_D2": { + "src_wire": "IOI_IMUX40_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC0_OQ->>RIOI_O0": { + "src_wire": "RIOI_OLOGIC0_OQ", + "is_pseudo": "0", + "dst_wire": "RIOI_O0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLKM_0", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IMUX43_1->IOI_OLOGIC0_D5": { + "src_wire": "IOI_IMUX43_1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { + "src_wire": "IOI_CLK0_1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { + "src_wire": "RIOI_OLOGIC1_OQ", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OFB", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_1", + "is_directional": "1", + "can_invert": "0" + }, + "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV", + "is_directional": "1", + "can_invert": "0" + } + } +} \ No newline at end of file diff --git a/kintex7/tile_type_R_TERM_INT.json b/kintex7/tile_type_R_TERM_INT.json new file mode 100644 index 0000000..df693a8 --- /dev/null +++ b/kintex7/tile_type_R_TERM_INT.json @@ -0,0 +1,173 @@ +{ + "tile_type": "R_TERM_INT", + "sites": [], + "wires": [ + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "TERM_INT_CTRL1", + "TERM_INT_LOGIC_OUTS_L_B1", + "TERM_INT_LOGIC_OUTS_L_B7", + "R_TERM_INT_WW4B3", + "TERM_INT_IMUX6", + "R_TERM_INT_WW2A3", + "R_TERM_INT_NW4A0", + "TERM_INT_LOGIC_OUTS_L_B8", + "TERM_INT_IMUX41", + "TERM_INT_BYP1", + "R_TERM_INT_WW4A0", + "TERM_INT_LOGIC_OUTS_L_B22", + "R_TERM_INT_WW4A3", + "R_TERM_INT_NW2A3", + "R_TERM_INT_NW2A0", + "TERM_INT_FAN7", + "R_TERM_INT_WW4C1", + "R_TERM_INT_LH2", + "TERM_INT_IMUX24", + "TERM_INT_LOGIC_OUTS_L_B5", + "TERM_INT_IMUX14", + "R_TERM_INT_NW4A2", + "TERM_INT_CLK0", + "R_TERM_INT_NW4END1", + "TERM_INT_BLOCK_OUTS_L_B3", + "R_TERM_INT_WW4A1", + "TERM_INT_IMUX7", + "TERM_INT_IMUX10", + "L_TERM_INT_DQS_IOTOPHASER", + "R_TERM_INT_NW2A2", + "TERM_INT_IMUX22", + "R_TERM_INT_SW4END2", + "R_TERM_INT_WR1END3", + "TERM_INT_MONITOR_N", + "R_TERM_INT_SW2A0", + "TERM_INT_BYP7", + "R_TERM_INT_WW4END1", + "TERM_INT_IMUX28", + "TERM_INT_IMUX21", + "TERM_INT_IMUX5", + "R_TERM_INT_SW4END0", + "TERM_INT_IMUX11", + "R_TERM_INT_WL1END2", + "R_TERM_INT_WW4C2", + "R_TERM_INT_NW4A1", + "TERM_INT_IMUX4", + "TERM_INT_LOGIC_OUTS_L_B15", + "TERM_INT_IMUX34", + "R_TERM_INT_WW4END2", + "R_TERM_INT_WW4C0", + "TERM_INT_LOGIC_OUTS_L_B12", + "TERM_INT_IMUX35", + "R_TERM_INT_WL1END0", + "TERM_INT_FAN4", + "TERM_INT_BYP2", + "R_TERM_INT_LH3", + "R_TERM_INT_WW4A2", + "TERM_INT_LOGIC_OUTS_L_B11", + "R_TERM_INT_WW4B0", + "TERM_INT_IMUX13", + "TERM_INT_FAN6", + "R_TERM_INT_SW2A1", + "TERM_INT_LOGIC_OUTS_L_B18", + "TERM_INT_IMUX40", + "R_TERM_INT_NW4END0", + "TERM_INT_IMUX31", + "R_TERM_INT_SW2A2", + "TERM_INT_FAN2", + "R_TERM_INT_WW2A2", + "TERM_INT_IMUX46", + "TERM_INT_FAN1", + "R_TERM_INT_SW4END1", + "R_TERM_INT_WW4B2", + "R_TERM_INT_SW2A3", + "R_TERM_INT_SW4A3", + "TERM_INT_LOGIC_OUTS_L_B20", + "TERM_INT_IMUX47", + "R_TERM_INT_WW2END2", + "TERM_INT_IMUX9", + "TERM_INT_LOGIC_OUTS_L_B16", + "R_TERM_INT_LH0", + "TERM_INT_IMUX30", + "TERM_INT_FAN3", + "R_TERM_INT_SW4A1", + "TERM_INT_LOGIC_OUTS_L_B6", + "R_TERM_INT_SW4END3", + "TERM_INT_BLOCK_OUTS_L_B0", + "TERM_INT_IMUX29", + "R_TERM_INT_NW4A3", + "TERM_INT_IMUX1", + "TERM_INT_IMUX36", + "R_TERM_INT_WW4END0", + "TERM_INT_LOGIC_OUTS_L_B10", + "R_TERM_INT_WW4END3", + "TERM_INT_BYP5", + "R_TERM_INT_WW2END3", + "R_TERM_INT_NW4END2", + "TERM_INT_IMUX38", + "R_TERM_INT_WW4B1", + "TERM_INT_IMUX26", + "R_TERM_INT_WL1END1", + "TERM_INT_CLK1", + "R_TERM_INT_NW2A1", + "R_TERM_INT_SW4A0", + "R_TERM_INT_WW4C3", + "R_TERM_INT_WW2A0", + "TERM_INT_IMUX17", + "TERM_INT_IMUX32", + "TERM_INT_IMUX16", + "TERM_INT_FAN5", + "L_TERM_INT_PHASER_TO_IO_OCLK", + "R_TERM_INT_LH1", + "R_TERM_INT_WW2END0", + "R_TERM_INT_LH5", + "TERM_INT_LOGIC_OUTS_L_B4", + "TERM_INT_BYP4", + "R_TERM_INT_WL1END3", + "R_TERM_INT_SW4A2", + "TERM_INT_IMUX39", + "R_TERM_INT_WR1END0", + "TERM_INT_BYP0", + "TERM_INT_BLOCK_OUTS_L_B1", + "TERM_INT_IMUX37", + "TERM_INT_IMUX8", + "R_TERM_INT_WR1END2", + "TERM_INT_LOGIC_OUTS_L_B23", + "TERM_INT_IMUX20", + "TERM_INT_BYP6", + "TERM_INT_CTRL0", + "TERM_INT_IMUX27", + "TERM_INT_IMUX18", + "TERM_INT_IMUX23", + "R_TERM_INT_WR1END1", + "TERM_INT_LOGIC_OUTS_L_B9", + "TERM_INT_IMUX2", + "TERM_INT_LOGIC_OUTS_L_B0", + "TERM_INT_IMUX44", + "R_TERM_INT_LH4", + "TERM_INT_IMUX19", + "TERM_INT_LOGIC_OUTS_L_B19", + "TERM_INT_IMUX3", + "L_TERM_INT_PHASER_TO_IO_ICLK", + "TERM_INT_FAN0", + "TERM_INT_IMUX15", + "TERM_INT_IMUX33", + "TERM_INT_LOGIC_OUTS_L_B2", + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", + "TERM_INT_LOGIC_OUTS_L_B3", + "TERM_INT_BLOCK_OUTS_L_B2", + "TERM_INT_IMUX43", + "TERM_INT_IMUX25", + "TERM_INT_LOGIC_OUTS_L_B21", + "TERM_INT_IMUX45", + "TERM_INT_LOGIC_OUTS_L_B13", + "TERM_INT_IMUX0", + "TERM_INT_MONITOR_P", + "TERM_INT_LOGIC_OUTS_L_B17", + "R_TERM_INT_WW2END1", + "TERM_INT_IMUX12", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "TERM_INT_BYP3", + "TERM_INT_LOGIC_OUTS_L_B14", + "R_TERM_INT_NW4END3", + "R_TERM_INT_WW2A1", + "TERM_INT_IMUX42" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_R_TERM_INT_GTX.json b/kintex7/tile_type_R_TERM_INT_GTX.json new file mode 100644 index 0000000..d110ee5 --- /dev/null +++ b/kintex7/tile_type_R_TERM_INT_GTX.json @@ -0,0 +1,161 @@ +{ + "tile_type": "R_TERM_INT_GTX", + "sites": [], + "wires": [ + "R_TERM_INT_GTX_FAN1", + "R_TERM_INT_GTX_IMUX37", + "R_TERM_INT_WW4B3", + "R_TERM_INT_GTX_IMUX46", + "R_TERM_INT_GTX_CLK0", + "R_TERM_INT_GTX_LOGIC_OUTS_B6", + "R_TERM_INT_WW2A3", + "R_TERM_INT_NW4A0", + "R_TERM_INT_WW4A0", + "R_TERM_INT_GTX_LOGIC_OUTS_B15", + "R_TERM_INT_WW4A3", + "R_TERM_INT_NW2A3", + "R_TERM_INT_NW2A0", + "R_TERM_INT_GTX_IMUX13", + "R_TERM_INT_WW4C1", + "R_TERM_INT_LH2", + "R_TERM_INT_GTX_LOGIC_OUTS_B8", + "R_TERM_INT_NW4A2", + "R_TERM_INT_NW4END1", + "R_TERM_INT_WW4A1", + "R_TERM_INT_GTX_CLK1", + "R_TERM_INT_GTX_IMUX26", + "R_TERM_INT_GTX_BYP3", + "R_TERM_INT_GTX_IMUX17", + "R_TERM_INT_GTX_FAN6", + "R_TERM_INT_NW2A2", + "R_TERM_INT_GTX_IMUX1", + "R_TERM_INT_GTX_IMUX15", + "R_TERM_INT_SW4END2", + "R_TERM_INT_WR1END3", + "R_TERM_INT_SW2A0", + "R_TERM_INT_GTX_IMUX43", + "R_TERM_INT_GTX_LOGIC_OUTS_B11", + "R_TERM_INT_WW4END1", + "R_TERM_INT_GTX_LOGIC_OUTS_B5", + "R_TERM_INT_GTX_IMUX44", + "R_TERM_INT_GTX_IMUX5", + "R_TERM_INT_SW4END0", + "R_TERM_INT_GTX_IMUX19", + "R_TERM_INT_GTX_LOGIC_OUTS_B21", + "R_TERM_INT_GTX_LOGIC_OUTS_B10", + "R_TERM_INT_WL1END2", + "R_TERM_INT_WW4C2", + "R_TERM_INT_NW4A1", + "R_TERM_INT_GTX_LOGIC_OUTS_B17", + "R_TERM_INT_GTX_FAN7", + "R_TERM_INT_GTX_LOGIC_OUTS_B12", + "R_TERM_INT_GTX_BYP5", + "R_TERM_INT_WW4END2", + "R_TERM_INT_WW4C0", + "R_TERM_INT_GTX_FAN2", + "R_TERM_INT_GTX_IMUX39", + "R_TERM_INT_GTX_BYP4", + "R_TERM_INT_GTX_FAN3", + "R_TERM_INT_GTX_IMUX31", + "R_TERM_INT_GTX_LOGIC_OUTS_B2", + "R_TERM_INT_GTX_IMUX11", + "R_TERM_INT_WL1END0", + "R_TERM_INT_GTX_IMUX16", + "R_TERM_INT_GTX_LOGIC_OUTS_B23", + "R_TERM_INT_LH3", + "R_TERM_INT_WW4A2", + "R_TERM_INT_GTX_IMUX0", + "R_TERM_INT_GTX_IMUX32", + "R_TERM_INT_GTX_IMUX22", + "R_TERM_INT_WW4B0", + "R_TERM_INT_NW4END0", + "R_TERM_INT_SW2A1", + "R_TERM_INT_GTX_BYP2", + "R_TERM_INT_GTX_IMUX14", + "R_TERM_INT_SW2A2", + "R_TERM_INT_GTX_IMUX21", + "R_TERM_INT_WW2A2", + "R_TERM_INT_GTX_IMUX3", + "R_TERM_INT_SW4END1", + "R_TERM_INT_WW4B2", + "R_TERM_INT_GTX_LOGIC_OUTS_B14", + "R_TERM_INT_SW2A3", + "R_TERM_INT_SW4A3", + "R_TERM_INT_GTX_LOGIC_OUTS_B3", + "R_TERM_INT_WW2END2", + "R_TERM_INT_GTX_LOGIC_OUTS_B19", + "R_TERM_INT_GTX_IMUX27", + "R_TERM_INT_GTX_IMUX45", + "R_TERM_INT_GTX_IMUX42", + "R_TERM_INT_LH0", + "R_TERM_INT_GTX_LOGIC_OUTS_B4", + "R_TERM_INT_SW4A1", + "R_TERM_INT_SW4END3", + "R_TERM_INT_NW4A3", + "R_TERM_INT_GTX_CTRL0", + "R_TERM_INT_GTX_IMUX47", + "R_TERM_INT_GTX_FAN4", + "R_TERM_INT_WW4END0", + "R_TERM_INT_WW4END3", + "R_TERM_INT_GTX_LOGIC_OUTS_B20", + "R_TERM_INT_WW4B1", + "R_TERM_INT_WW2END3", + "R_TERM_INT_NW4END2", + "R_TERM_INT_GTX_LOGIC_OUTS_B18", + "R_TERM_INT_GTX_IMUX24", + "R_TERM_INT_WL1END1", + "R_TERM_INT_GTX_LOGIC_OUTS_B16", + "R_TERM_INT_NW2A1", + "R_TERM_INT_GTX_IMUX29", + "R_TERM_INT_SW4A0", + "R_TERM_INT_WW4C3", + "R_TERM_INT_WW2A0", + "R_TERM_INT_GTX_LOGIC_OUTS_B7", + "R_TERM_INT_GTX_LOGIC_OUTS_B22", + "R_TERM_INT_GTX_IMUX35", + "R_TERM_INT_GTX_IMUX28", + "R_TERM_INT_GTX_IMUX4", + "R_TERM_INT_GTX_LOGIC_OUTS_B13", + "R_TERM_INT_LH1", + "R_TERM_INT_WW2END0", + "R_TERM_INT_LH5", + "R_TERM_INT_GTX_FAN0", + "R_TERM_INT_WL1END3", + "R_TERM_INT_GTX_IMUX34", + "R_TERM_INT_GTX_IMUX23", + "R_TERM_INT_SW4A2", + "R_TERM_INT_GTX_CTRL1", + "R_TERM_INT_WR1END0", + "R_TERM_INT_GTX_IMUX30", + "R_TERM_INT_GTX_IMUX20", + "R_TERM_INT_GTX_IMUX18", + "R_TERM_INT_GTX_IMUX8", + "R_TERM_INT_GTX_IMUX40", + "R_TERM_INT_WR1END2", + "R_TERM_INT_WR1END1", + "R_TERM_INT_GTX_BYP6", + "R_TERM_INT_GTX_FAN5", + "R_TERM_INT_GTX_IMUX9", + "R_TERM_INT_LH4", + "R_TERM_INT_GTX_LOGIC_OUTS_B1", + "R_TERM_INT_GTX_IMUX12", + "R_TERM_INT_GTX_LOGIC_OUTS_B0", + "R_TERM_INT_GTX_IMUX25", + "R_TERM_INT_GTX_BYP0", + "R_TERM_INT_GTX_IMUX10", + "R_TERM_INT_GTX_IMUX33", + "R_TERM_INT_GTX_IMUX38", + "R_TERM_INT_GTX_IMUX6", + "R_TERM_INT_GTX_BYP7", + "R_TERM_INT_GTX_IMUX2", + "R_TERM_INT_GTX_IMUX7", + "R_TERM_INT_WW2END1", + "R_TERM_INT_GTX_IMUX41", + "R_TERM_INT_GTX_LOGIC_OUTS_B9", + "R_TERM_INT_GTX_IMUX36", + "R_TERM_INT_GTX_BYP1", + "R_TERM_INT_NW4END3", + "R_TERM_INT_WW2A1" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_TERM_CMT.json b/kintex7/tile_type_TERM_CMT.json new file mode 100644 index 0000000..9ed32f4 --- /dev/null +++ b/kintex7/tile_type_TERM_CMT.json @@ -0,0 +1,11 @@ +{ + "tile_type": "TERM_CMT", + "sites": [], + "wires": [ + "TERM_CMT_FREQ_REF_NS0", + "TERM_CMT_FREQ_REF_NS1", + "TERM_CMT_FREQ_REF_NS3", + "TERM_CMT_FREQ_REF_NS2" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_T_TERM_INT.json b/kintex7/tile_type_T_TERM_INT.json new file mode 100644 index 0000000..29e75f0 --- /dev/null +++ b/kintex7/tile_type_T_TERM_INT.json @@ -0,0 +1,124 @@ +{ + "tile_type": "T_TERM_INT", + "sites": [], + "wires": [ + "T_TERM_UTURN_INT_SE6D1", + "T_TERM_UTURN_INT_SW6E2", + "T_TERM_INT_UTURN_LV_R7", + "T_TERM_UTURN_INT_SW6C0", + "T_TERM_UTURN_INT_SW6D1", + "T_TERM_UTURN_INT_LV_L3", + "T_TERM_UTURN_INT_SW6E3", + "T_TERM_INT_UTURN_LV_R17", + "T_TERM_UTURN_INT_SS6A3", + "T_TERM_UTURN_INT_SE6E2", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", + "T_TERM_UTURN_INT_SS2END3", + "T_TERM_UTURN_INT_SS6A0", + "T_TERM_UTURN_INT_LVB2", + "T_TERM_UTURN_INT_SL1END0", + "T_TERM_UTURN_INT_SE6B3", + "T_TERM_UTURN_INT_SS6E2", + "T_TERM_UTURN_INT_SW2A1", + "T_TERM_UTURN_INT_SR1END2", + "T_TERM_UTURN_INT_LVB1", + "T_TERM_UTURN_INT_SS2A1", + "T_TERM_UTURN_INT_SS6E3", + "T_TERM_UTURN_INT_SS6END3", + "T_TERM_UTURN_INT_SW6C3", + "T_TERM_UTURN_INT_SE6E0", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", + "T_TERM_UTURN_INT_SS6D3", + "T_TERM_UTURN_INT_SW2A0", + "T_TERM_UTURN_INT_SE6B1", + "T_TERM_UTURN_INT_SS6END0", + "T_TERM_UTURN_INT_SE6B0", + "T_TERM_UTURN_INT_LV_L5", + "T_TERM_UTURN_INT_LV_L17", + "T_TERM_UTURN_INT_SS6D1", + "T_TERM_UTURN_INT_SE2A2", + "T_TERM_UTURN_INT_SE6C1", + "T_TERM_UTURN_INT_LV_L6", + "T_TERM_UTURN_INT_SS6C3", + "T_TERM_UTURN_INT_SW6C2", + "T_TERM_UTURN_INT_SE2A3", + "T_TERM_UTURN_INT_SS2END0", + "T_TERM_UTURN_INT_SW6D0", + "T_TERM_UTURN_INT_LVB_L4", + "T_TERM_UTURN_INT_SW6E0", + "T_TERM_UTURN_INT_SW2A3", + "T_TERM_UTURN_INT_LV_L16", + "T_TERM_UTURN_INT_SL1END2", + "T_TERM_UTURN_INT_LV_L9", + "T_TERM_UTURN_INT_SE6D2", + "T_TERM_UTURN_INT_SS2A0", + "T_TERM_UTURN_INT_SE6C0", + "T_TERM_UTURN_INT_SS2END2", + "T_TERM_UTURN_INT_LVB3", + "T_TERM_UTURN_INT_SS6D0", + "T_TERM_UTURN_INT_SE2A0", + "T_TERM_UTURN_INT_SS6E1", + "T_TERM_UTURN_INT_SE6E3", + "T_TERM_UTURN_INT_ER1BEG_S0", + "T_TERM_UTURN_INT_LVB4", + "T_TERM_UTURN_INT_SE6D3", + "T_TERM_UTURN_INT_SS6END2", + "T_TERM_UTURN_INT_LV_L7", + "T_TERM_UTURN_INT_SS6B2", + "T_TERM_UTURN_INT_LVB_L5", + "T_TERM_UTURN_INT_SS6B3", + "T_TERM_UTURN_INT_LVB5", + "T_TERM_UTURN_INT_SW6D3", + "T_TERM_INT_UTURN_LV_R5", + "T_TERM_UTURN_INT_SS6C0", + "T_TERM_UTURN_INT_SS2END1", + "T_TERM_UTURN_INT_SS6B0", + "T_TERM_INT_UTURN_LV_R16", + "T_TERM_UTURN_INT_SS2A3", + "T_TERM_UTURN_INT_SW6B1", + "T_TERM_UTURN_INT_SW6B2", + "T_TERM_INT_UTURN_LV_R3", + "T_TERM_UTURN_INT_SW6E1", + "T_TERM_INT_UTURN_LV_R6", + "T_TERM_UTURN_INT_SE6C2", + "T_TERM_UTURN_INT_LVB_L0", + "T_TERM_INT_UTURN_LV_R4", + "T_TERM_UTURN_INT_SS6E0", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", + "T_TERM_UTURN_INT_WR1END_S1_0", + "T_TERM_UTURN_INT_SL1END3", + "T_TERM_UTURN_INT_ER1END3", + "T_TERM_UTURN_INT_SS6A1", + "T_TERM_UTURN_INT_SS6B1", + "T_TERM_UTURN_INT_SS6A2", + "T_TERM_UTURN_INT_SS6D2", + "T_TERM_UTURN_INT_SW2A2", + "T_TERM_UTURN_INT_LVB_L2", + "T_TERM_UTURN_INT_SE6D0", + "T_TERM_UTURN_INT_SW6B3", + "T_TERM_INT_UTURN_LV_R9", + "T_TERM_INT_UTURN_LV_R2", + "T_TERM_UTURN_INT_SE6E1", + "T_TERM_UTURN_INT_SW6D2", + "T_TERM_UTURN_INT_SS2A2", + "T_TERM_UTURN_INT_LV_L2", + "T_TERM_UTURN_INT_SE2A1", + "T_TERM_UTURN_INT_SS6C1", + "T_TERM_UTURN_INT_SR1END1", + "T_TERM_UTURN_INT_SS6END1", + "T_TERM_UTURN_INT_LV_L4", + "T_TERM_UTURN_INT_WR1BEG_S0", + "T_TERM_UTURN_INT_SE6B2", + "T_TERM_UTURN_INT_SL1END1", + "T_TERM_UTURN_INT_SE6C3", + "T_TERM_UTURN_INT_SS6C2", + "T_TERM_UTURN_INT_LVB0", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", + "T_TERM_UTURN_INT_LVB_L3", + "T_TERM_UTURN_INT_SW6B0", + "T_TERM_UTURN_INT_LVB_L1", + "T_TERM_UTURN_INT_SR1END3", + "T_TERM_UTURN_INT_SW6C1" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_VBRK.json b/kintex7/tile_type_VBRK.json new file mode 100644 index 0000000..a7c4446 --- /dev/null +++ b/kintex7/tile_type_VBRK.json @@ -0,0 +1,133 @@ +{ + "tile_type": "VBRK", + "sites": [], + "wires": [ + "VBRK_WL1END1", + "VBRK_NE4C2", + "VBRK_EE4C0", + "VBRK_NW4A1", + "VBRK_NW2A1", + "VBRK_WW2END3", + "VBRK_NE4C0", + "VBRK_WL1END3", + "VBRK_SW4END2", + "VBRK_EE4B2", + "VBRK_MONITOR_N", + "VBRK_WW4B2", + "VBRK_WW4A1", + "VBRK_SW2A2", + "VBRK_EE4C3", + "VBRK_NE4BEG3", + "VBRK_WW2A1", + "VBRK_WW4END0", + "VBRK_WW2END2", + "VBRK_NE4C3", + "VBRK_WR1END1", + "VBRK_SW4A1", + "VBRK_EE2A0", + "VBRK_LH10", + "VBRK_WW4B1", + "VBRK_SE4BEG2", + "VBRK_WW4C3", + "VBRK_NE4C1", + "VBRK_WW2END0", + "VBRK_LH4", + "VBRK_WW2A2", + "VBRK_WR1END2", + "VBRK_NW2A2", + "VBRK_SW4A0", + "VBRK_SW4A3", + "VBRK_SE4C3", + "VBRK_NW4END0", + "VBRK_WW2END1", + "VBRK_LH5", + "VBRK_EE4A0", + "VBRK_SW4A2", + "VBRK_LH2", + "VBRK_NW4END3", + "VBRK_SE2A3", + "VBRK_EE4C1", + "VBRK_EE4B0", + "VBRK_NE2A3", + "VBRK_LH3", + "VBRK_LH6", + "VBRK_WL1END0", + "VBRK_ER1BEG0", + "VBRK_WW4B0", + "VBRK_SW2A0", + "VBRK_NE2A0", + "VBRK_SW2A3", + "VBRK_WW4B3", + "VBRK_NW4A3", + "VBRK_SE4BEG0", + "VBRK_WR1END0", + "VBRK_WW4A3", + "VBRK_NW4END2", + "VBRK_EE2BEG3", + "VBRK_WW2A3", + "VBRK_EE4B1", + "VBRK_MONITOR_P", + "VBRK_EE4A1", + "VBRK_WW4A2", + "VBRK_EE4A2", + "VBRK_LH1", + "VBRK_SE2A0", + "VBRK_SE4C0", + "VBRK_LH9", + "VBRK_EE4BEG0", + "VBRK_SE2A2", + "VBRK_SW2A1", + "VBRK_LH8", + "VBRK_EL1BEG2", + "VBRK_EE4BEG1", + "VBRK_WW4C1", + "VBRK_EE2BEG1", + "VBRK_SE4BEG1", + "VBRK_NE2A1", + "VBRK_EE2BEG0", + "VBRK_SE4C2", + "VBRK_ER1BEG3", + "VBRK_NW4END1", + "VBRK_ER1BEG1", + "VBRK_LH12", + "VBRK_WL1END2", + "VBRK_NW2A0", + "VBRK_WR1END3", + "VBRK_WW4C2", + "VBRK_ER1BEG2", + "VBRK_NW4A2", + "VBRK_EE2BEG2", + "VBRK_LH7", + "VBRK_SE4BEG3", + "VBRK_SW4END3", + "VBRK_SW4END0", + "VBRK_WW4END2", + "VBRK_EE2A2", + "VBRK_NE2A2", + "VBRK_EE2A3", + "VBRK_WW4END1", + "VBRK_EE4BEG2", + "VBRK_NE4BEG0", + "VBRK_LH11", + "VBRK_SW4END1", + "VBRK_EE4C2", + "VBRK_WW2A0", + "VBRK_EL1BEG0", + "VBRK_SE2A1", + "VBRK_EE4A3", + "VBRK_EL1BEG1", + "VBRK_NW4A0", + "VBRK_SE4C1", + "VBRK_WW4C0", + "VBRK_NW2A3", + "VBRK_NE4BEG1", + "VBRK_EE4B3", + "VBRK_NE4BEG2", + "VBRK_WW4A0", + "VBRK_EE4BEG3", + "VBRK_EE2A1", + "VBRK_EL1BEG3", + "VBRK_WW4END3" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_VBRK_EXT.json b/kintex7/tile_type_VBRK_EXT.json new file mode 100644 index 0000000..a598d1b --- /dev/null +++ b/kintex7/tile_type_VBRK_EXT.json @@ -0,0 +1,99 @@ +{ + "tile_type": "VBRK_EXT", + "sites": [], + "wires": [ + "VBRK_EXT_BYP0", + "VBRK_EXT_FAN1", + "VBRK_EXT_BYP2", + "VBRK_EXT_BYP6", + "VBRK_EXT_IMUX31", + "VBRK_EXT_BYP1", + "VBRK_EXT_LOGIC_OUTS_B19", + "VBRK_EXT_IMUX33", + "VBRK_EXT_FAN3", + "VBRK_EXT_IMUX0", + "VBRK_EXT_LOGIC_OUTS_B1", + "VBRK_EXT_LOGIC_OUTS_B22", + "VBRK_EXT_IMUX21", + "VBRK_EXT_IMUX24", + "VBRK_EXT_IMUX4", + "VBRK_EXT_IMUX12", + "VBRK_EXT_IMUX7", + "VBRK_EXT_IMUX39", + "VBRK_EXT_IMUX6", + "VBRK_EXT_IMUX18", + "VBRK_EXT_LOGIC_OUTS_B0", + "VBRK_EXT_IMUX26", + "VBRK_EXT_IMUX15", + "VBRK_EXT_IMUX8", + "VBRK_EXT_IMUX42", + "VBRK_EXT_IMUX38", + "VBRK_EXT_LOGIC_OUTS_B21", + "VBRK_EXT_IMUX36", + "VBRK_EXT_LOGIC_OUTS_B12", + "VBRK_EXT_FAN5", + "VBRK_EXT_BYP3", + "VBRK_EXT_LOGIC_OUTS_B16", + "VBRK_EXT_LOGIC_OUTS_B11", + "VBRK_EXT_IMUX44", + "VBRK_EXT_FAN2", + "VBRK_EXT_IMUX46", + "VBRK_EXT_IMUX40", + "VBRK_EXT_IMUX43", + "VBRK_EXT_LOGIC_OUTS_B23", + "VBRK_EXT_IMUX45", + "VBRK_EXT_IMUX29", + "VBRK_EXT_IMUX28", + "VBRK_EXT_LOGIC_OUTS_B6", + "VBRK_EXT_LOGIC_OUTS_B5", + "VBRK_EXT_LOGIC_OUTS_B14", + "VBRK_EXT_LOGIC_OUTS_B20", + "VBRK_EXT_LOGIC_OUTS_B7", + "VBRK_EXT_LOGIC_OUTS_B17", + "VBRK_EXT_IMUX27", + "VBRK_EXT_IMUX47", + "VBRK_EXT_LOGIC_OUTS_B10", + "VBRK_EXT_IMUX14", + "VBRK_EXT_IMUX3", + "VBRK_EXT_IMUX23", + "VBRK_EXT_IMUX2", + "VBRK_EXT_IMUX41", + "VBRK_EXT_IMUX32", + "VBRK_EXT_FAN4", + "VBRK_EXT_LOGIC_OUTS_B4", + "VBRK_EXT_BYP4", + "VBRK_EXT_IMUX5", + "VBRK_EXT_BYP7", + "VBRK_EXT_CLK1", + "VBRK_EXT_IMUX22", + "VBRK_EXT_LOGIC_OUTS_B18", + "VBRK_EXT_FAN7", + "VBRK_EXT_IMUX11", + "VBRK_EXT_BYP5", + "VBRK_EXT_CTRL0", + "VBRK_EXT_IMUX30", + "VBRK_EXT_CTRL1", + "VBRK_EXT_LOGIC_OUTS_B9", + "VBRK_EXT_IMUX9", + "VBRK_EXT_IMUX20", + "VBRK_EXT_CLK0", + "VBRK_EXT_IMUX34", + "VBRK_EXT_IMUX1", + "VBRK_EXT_LOGIC_OUTS_B13", + "VBRK_EXT_IMUX10", + "VBRK_EXT_IMUX19", + "VBRK_EXT_IMUX25", + "VBRK_EXT_IMUX37", + "VBRK_EXT_IMUX35", + "VBRK_EXT_FAN6", + "VBRK_EXT_LOGIC_OUTS_B15", + "VBRK_EXT_IMUX17", + "VBRK_EXT_FAN0", + "VBRK_EXT_LOGIC_OUTS_B2", + "VBRK_EXT_IMUX13", + "VBRK_EXT_LOGIC_OUTS_B8", + "VBRK_EXT_LOGIC_OUTS_B3", + "VBRK_EXT_IMUX16" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tile_type_VFRAME.json b/kintex7/tile_type_VFRAME.json new file mode 100644 index 0000000..a6ea7ad --- /dev/null +++ b/kintex7/tile_type_VFRAME.json @@ -0,0 +1,229 @@ +{ + "tile_type": "VFRAME", + "sites": [], + "wires": [ + "VFRAME_NE2A0", + "VFRAME_IMUX40", + "VFRAME_LH1", + "VFRAME_IMUX19", + "VFRAME_FAN4", + "VFRAME_NW2A0", + "VFRAME_LOGIC_OUTS_B0", + "VFRAME_NE4BEG3", + "VFRAME_EE4B1", + "VFRAME_IMUX46", + "VFRAME_IMUX21", + "VFRAME_ER1BEG1", + "VFRAME_FAN3", + "VFRAME_IMUX37", + "VFRAME_LH7", + "VFRAME_NE4BEG2", + "VFRAME_SW4END1", + "VFRAME_EE4BEG1", + "VFRAME_WW4B2", + "VFRAME_EE2BEG2", + "VFRAME_NE2A2", + "VFRAME_EE4BEG3", + "VFRAME_LOGIC_OUTS_B7", + "VFRAME_LOGIC_OUTS_B23", + "VFRAME_EE2A0", + "VFRAME_IMUX17", + "VFRAME_CLK0", + "VFRAME_WR1END1", + "VFRAME_SE4BEG1", + "VFRAME_IMUX23", + "VFRAME_WW2A1", + "VFRAME_SW4A0", + "VFRAME_BYP4", + "VFRAME_SE4C2", + "VFRAME_EE2A2", + "VFRAME_LH10", + "VFRAME_EL1BEG2", + "VFRAME_WW4A1", + "VFRAME_NE4C1", + "VFRAME_WW4C2", + "VFRAME_EL1BEG0", + "VFRAME_WW2A2", + "VFRAME_IMUX38", + "VFRAME_IMUX1", + "VFRAME_IMUX39", + "VFRAME_LOGIC_OUTS_B14", + "VFRAME_IMUX47", + "VFRAME_NE4C0", + "VFRAME_IMUX30", + "VFRAME_LH2", + "VFRAME_LOGIC_OUTS_B6", + "VFRAME_WR1END0", + "VFRAME_SW4A2", + "VFRAME_IMUX0", + "VFRAME_WW4A0", + "VFRAME_BLOCK_OUTS_B3", + "VFRAME_NW4A2", + "VFRAME_BYP7", + "VFRAME_IMUX10", + "VFRAME_NE4BEG1", + "VFRAME_EL1BEG3", + "VFRAME_LOGIC_OUTS_B10", + "VFRAME_SW2A1", + "VFRAME_IMUX15", + "VFRAME_LH11", + "VFRAME_WW4B0", + "VFRAME_SW4A3", + "VFRAME_LOGIC_OUTS_B5", + "VFRAME_SW4END0", + "VFRAME_WW2A0", + "VFRAME_WW4END2", + "VFRAME_LH6", + "VFRAME_MONITOR_P", + "VFRAME_LOGIC_OUTS_B20", + "VFRAME_BLOCK_OUTS_B2", + "VFRAME_WW4B1", + "VFRAME_NE4C3", + "VFRAME_WW4C0", + "VFRAME_ER1BEG3", + "VFRAME_WW4END1", + "VFRAME_BLOCK_OUTS_B1", + "VFRAME_FAN5", + "VFRAME_LOGIC_OUTS_B12", + "VFRAME_NW4A0", + "VFRAME_LOGIC_OUTS_B17", + "VFRAME_FAN1", + "VFRAME_LOGIC_OUTS_B15", + "VFRAME_SW4END2", + "VFRAME_LOGIC_OUTS_B9", + "VFRAME_WL1END1", + "VFRAME_CTRL0", + "VFRAME_WL1END3", + "VFRAME_SE4BEG3", + "VFRAME_NE4C2", + "VFRAME_LOGIC_OUTS_B21", + "VFRAME_IMUX12", + "VFRAME_WL1END2", + "VFRAME_SE4BEG0", + "VFRAME_SE2A2", + "VFRAME_LOGIC_OUTS_B13", + "VFRAME_IMUX11", + "VFRAME_LH12", + "VFRAME_CTRL1", + "VFRAME_WW4A2", + "VFRAME_IMUX35", + "VFRAME_IMUX41", + "VFRAME_WW2A3", + "VFRAME_LH5", + "VFRAME_WW2END0", + "VFRAME_NW4END1", + "VFRAME_IMUX33", + "VFRAME_FAN0", + "VFRAME_LOGIC_OUTS_B4", + "VFRAME_EE2BEG3", + "VFRAME_ER1BEG2", + "VFRAME_EE4A2", + "VFRAME_SE2A0", + "VFRAME_WW4END3", + "VFRAME_IMUX14", + "VFRAME_WW2END1", + "VFRAME_BYP1", + "VFRAME_CLK1", + "VFRAME_SW4A1", + "VFRAME_BYP3", + "VFRAME_WW4C1", + "VFRAME_EL1BEG1", + "VFRAME_WL1END0", + "VFRAME_NW2A3", + "VFRAME_IMUX24", + "VFRAME_FAN2", + "VFRAME_LH3", + "VFRAME_LOGIC_OUTS_B18", + "VFRAME_SE4BEG2", + "VFRAME_EE4C1", + "VFRAME_WW2END2", + "VFRAME_IMUX43", + "VFRAME_NW4A1", + "VFRAME_EE2A1", + "VFRAME_SW2A2", + "VFRAME_NW4END3", + "VFRAME_EE4B3", + "VFRAME_FAN6", + "VFRAME_NE2A3", + "VFRAME_IMUX29", + "VFRAME_SE4C0", + "VFRAME_IMUX32", + "VFRAME_SE2A1", + "VFRAME_IMUX7", + "VFRAME_EE4A0", + "VFRAME_BLOCK_OUTS_B0", + "VFRAME_EE4C3", + "VFRAME_LOGIC_OUTS_B16", + "VFRAME_IMUX44", + "VFRAME_NE4BEG0", + "VFRAME_WW4C3", + "VFRAME_LH4", + "VFRAME_NW4A3", + "VFRAME_LOGIC_OUTS_B2", + "VFRAME_BYP5", + "VFRAME_IMUX28", + "VFRAME_LOGIC_OUTS_B19", + "VFRAME_IMUX16", + "VFRAME_EE2BEG0", + "VFRAME_LOGIC_OUTS_B8", + "VFRAME_IMUX42", + "VFRAME_BYP6", + "VFRAME_WR1END2", + "VFRAME_IMUX8", + "VFRAME_NW4END0", + "VFRAME_WW2END3", + "VFRAME_LOGIC_OUTS_B1", + "VFRAME_IMUX36", + "VFRAME_NW2A1", + "VFRAME_EE4C0", + "VFRAME_EE4BEG0", + "VFRAME_IMUX18", + "VFRAME_EE4A3", + "VFRAME_IMUX4", + "VFRAME_SW4END3", + "VFRAME_IMUX22", + "VFRAME_IMUX25", + "VFRAME_LOGIC_OUTS_B22", + "VFRAME_IMUX26", + "VFRAME_WW4A3", + "VFRAME_IMUX45", + "VFRAME_IMUX5", + "VFRAME_FAN7", + "VFRAME_SW2A3", + "VFRAME_IMUX6", + "VFRAME_BYP0", + "VFRAME_EE4C2", + "VFRAME_LOGIC_OUTS_B11", + "VFRAME_IMUX2", + "VFRAME_IMUX31", + "VFRAME_IMUX13", + "VFRAME_MONITOR_N", + "VFRAME_IMUX34", + "VFRAME_WR1END3", + "VFRAME_IMUX3", + "VFRAME_SW2A0", + "VFRAME_BYP2", + "VFRAME_ER1BEG0", + "VFRAME_EE2BEG1", + "VFRAME_SE2A3", + "VFRAME_NW2A2", + "VFRAME_SE4C3", + "VFRAME_EE4B2", + "VFRAME_EE4B0", + "VFRAME_NW4END2", + "VFRAME_IMUX20", + "VFRAME_LH8", + "VFRAME_LH9", + "VFRAME_LOGIC_OUTS_B3", + "VFRAME_IMUX27", + "VFRAME_WW4B3", + "VFRAME_WW4END0", + "VFRAME_IMUX9", + "VFRAME_EE2A3", + "VFRAME_EE4A1", + "VFRAME_SE4C1", + "VFRAME_EE4BEG2", + "VFRAME_NE2A1" + ], + "pips": {} +} \ No newline at end of file diff --git a/kintex7/tileconn.json b/kintex7/tileconn.json new file mode 100644 index 0000000..98142fc --- /dev/null +++ b/kintex7/tileconn.json @@ -0,0 +1,477302 @@ +[ + { + "grid_deltas": [ + 1, + -6 + ], + "wire_pairs": [ + [ + "CFG_CENTER_CTRL0_16", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX11_16", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX6_16", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_NW2A1_16", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_SE4C0_16", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_IMUX42_16", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_EE4A1_16", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_SE4C1_16", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_LH7_16", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_LH2_16", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_SW4END0_16", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_SW4A0_16", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_EE4B1_16", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_SW4A1_16", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_EE4B0_16", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_SW2A1_16", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_EE4C3_16", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE4BEG0_16", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_IMUX37_16", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_WW4C1_16", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_NW4A3_16", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_NE2A2_16", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_LH6_16", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_LH1_16", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_BYP2_16", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_IMUX8_16", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW2END0_16", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_CTRL1_16", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_EE4A2_16", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX31_16", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_FAN5_16", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_IMUX46_16", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_LH11_16", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_NE4C1_16", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_EE4A3_16", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_FAN7_16", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_WW4A1_16", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_IMUX7_16", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_SW4END2_16", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_IMUX25_16", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_IMUX36_16", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_FAN0_16", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_NW4A0_16", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NE2A0_16", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX12_16", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_ER1BEG0_16", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_FAN3_16", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_IMUX43_16", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX30_16", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_WW4C3_16", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_SE2A0_16", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_WL1END3_16", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_IMUX34_16", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_IMUX3_16", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_IMUX32_16", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_SW4A2_16", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_WW4END1_16", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_SE4BEG1_16", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_WW2END2_16", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_NE4BEG0_16", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_EE4BEG2_16", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_NW4END3_16", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_WW4B3_16", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_WW4END3_16", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX41_16", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_WW4A2_16", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_IMUX1_16", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_NW2A0_16", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_IMUX47_16", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_EE4BEG3_16", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG1_16", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_LH4_16", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_SE4C2_16", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_LH5_16", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_SE2A3_16", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_CLK0_16", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_NW4END1_16", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SE4BEG3_16", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX44_16", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_BYP3_16", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_IMUX17_16", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX20_16", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_EE4C1_16", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_WW4A3_16", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_EL1BEG3_16", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_IMUX15_16", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_IMUX35_16", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_EE4C2_16", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_LH9_16", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EL1BEG2_16", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_WR1END3_16", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_NE2A1_16", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_ER1BEG1_16", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_EE2BEG3_16", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_EL1BEG0_16", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_FAN4_16", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_ER1BEG2_16", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_EE4C0_16", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_EE2BEG0_16", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_EE4B3_16", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_IMUX13_16", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_IMUX4_16", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_NW4A2_16", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_IMUX40_16", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_IMUX18_16", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_FAN2_16", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_IMUX22_16", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW2A0_16", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_WW4C0_16", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_NW2A2_16", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_SW2A0_16", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_SE2A2_16", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_FAN1_16", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX16_16", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX2_16", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_IMUX24_16", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_IMUX29_16", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_BYP5_16", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_EE2A1_16", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_ER1BEG3_16", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_SW4A3_16", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_WL1END2_16", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WW4A0_16", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_EE2A3_16", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_IMUX45_16", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_FAN6_16", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_NE4C0_16", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_IMUX26_16", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX21_16", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_IMUX5_16", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX23_16", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NE4BEG3_16", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NE2A3_16", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_NE4BEG2_16", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW4B0_16", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_LH8_16", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_EE2A2_16", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_SW4END3_16", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_EE4A0_16", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_NE4C2_16", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_SW4END1_16", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_IMUX28_16", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX10_16", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_EE4BEG1_16", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_EE2BEG2_16", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_EE4B2_16", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_CLK1_16", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_SW2A3_16", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_BYP7_16", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_BYP6_16", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_SW2A2_16", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_NW4A1_16", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_WW4B1_16", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_NW2A3_16", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_WW2A3_16", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_BYP0_16", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX27_16", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_WL1END1_16", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_NW4END0_16", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_WW2A1_16", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_BYP4_16", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WW4END2_16", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX39_16", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_WW2END3_16", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_NE4BEG1_16", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG2_16", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_LH3_16", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_WW2A2_16", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_SE2A1_16", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_WL1END0_16", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_WR1END2_16", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_LH12_16", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_LH10_16", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_SE4C3_16", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_WR1END1_16", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_IMUX9_16", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX0_16", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_IMUX19_16", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_WW4C2_16", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WW4END0_16", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_EE2BEG1_16", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_EE2A0_16", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WR1END0_16", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_SE4BEG0_16", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_IMUX14_16", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_BYP1_16", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW2END1_16", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_NE4C3_16", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_IMUX38_16", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX33_16", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_NW4END2_16", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_WW4B2_16", + "VFRAME_WW4B2" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_NE4BEG1_10", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_SW4END1_10", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_EE4C3_10", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_SW4END3_10", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_SE4BEG1_10", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX22_10", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_SW4END2_10", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_LH12_10", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_10", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "CMT_FIFO_WW4C0_10", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_NW4A3_10", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_L_IMUX21_10", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_SW4END0_10", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_WW4B0_10", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_EE4BEG1_10", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX16_10", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_WR1END2_10", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_NW2A1_10", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_10", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "CMT_FIFO_WW2A1_10", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_NE4C0_10", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_10", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "CMT_FIFO_SE2A2_10", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_L_BYP6_10", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_NW2A3_10", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_L_IMUX38_10", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_LH7_10", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_NE4BEG0_10", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_WW4END0_10", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_IMUX7_10", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_NW4A2_10", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_WW4C1_10", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_L_IMUX18_10", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_ER1BEG0_10", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_10", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_10", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "CMT_FIFO_NW4A0_10", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_EE4BEG3_10", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_SW4A2_10", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_WR1END1_10", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_WW4END1_10", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_WL1END3_10", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_NE4BEG2_10", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_EL1BEG0_10", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_EE2BEG1_10", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_WW4C3_10", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_WW2END2_10", + "INT_INTERFACE_WW2END2" + ], + [ + "FIFO_DQS_IOTOPHASER_5", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "CMT_FIFO_L_BYP4_10", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_L_IMUX13_10", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_EE2A0_10", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_10", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "CMT_FIFO_L_FAN1_10", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_L_IMUX33_10", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_WW4A2_10", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_SE2A0_10", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_NW4END2_10", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_EE4C2_10", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_NE2A1_10", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_LH6_10", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_L_FAN5_10", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_SW2A0_10", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_L_IMUX8_10", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_IMUX30_10", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_NE2A3_10", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_NE2A2_10", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_NE4C3_10", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_NE2A0_10", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_10", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "CMT_FIFO_EL1BEG2_10", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_WW4B1_10", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_WW4B3_10", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_EE2A1_10", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_L_FAN4_10", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_LH2_10", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_ER1BEG1_10", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_10", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_10", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "CMT_FIFO_L_IMUX34_10", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_SW4A3_10", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_WW4C2_10", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_IMUX41_10", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_FAN3_10", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_SE4C1_10", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_EL1BEG3_10", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_EE4B3_10", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_EE2A2_10", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_L_CTRL0_10", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_WW4END2_10", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_L_IMUX19_10", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_EL1BEG1_10", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_WW4END3_10", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_L_IMUX44_10", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_CLK0_10", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_WW4B2_10", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_L_IMUX37_10", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_SW2A1_10", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_L_IMUX43_10", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_WW4A3_10", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_EE2BEG3_10", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_NW4A1_10", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_WR1END3_10", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_10", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_10", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "CMT_FIFO_L_IMUX39_10", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_10", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "CMT_FIFO_WW2END3_10", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_L_BYP5_10", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_L_IMUX3_10", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_10", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "CMT_FIFO_LH9_10", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_L_IMUX32_10", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_NW2A0_10", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_10", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "CMT_FIFO_WW2END0_10", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_L_IMUX17_10", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_L_IMUX25_10", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_L_IMUX14_10", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_SE4C0_10", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_SE4BEG0_10", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX5_10", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_L_IMUX15_10", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_IMUX4_10", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_L_IMUX46_10", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_L_FAN7_10", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_WL1END2_10", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_EE4C0_10", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_NW4END0_10", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_SE4C2_10", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_L_BYP7_10", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_EE4B2_10", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_EE4BEG2_10", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_WW4A0_10", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_L_BYP0_10", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_L_IMUX47_10", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_L_IMUX11_10", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_EE2BEG2_10", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_ER1BEG2_10", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_10", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "CMT_FIFO_L_IMUX45_10", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_L_IMUX36_10", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_ER1BEG3_10", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_WW2A0_10", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_NE4BEG3_10", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_WW2A2_10", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_NW2A2_10", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_WL1END0_10", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_10", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "CMT_FIFO_L_IMUX10_10", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_L_IMUX12_10", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_L_FAN0_10", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_SE4BEG2_10", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_EE4BEG0_10", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_10", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "CMT_FIFO_EE4A0_10", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_L_IMUX2_10", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_L_IMUX42_10", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_10", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "CMT_FIFO_EE4C1_10", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_L_IMUX31_10", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_WR1END0_10", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_SE2A1_10", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_SE4C3_10", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_FAN6_10", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_LH10_10", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_SW4A1_10", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_NW4END3_10", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_NE4C2_10", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_L_CTRL1_10", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_EE4A1_10", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_LH3_10", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_WW2A3_10", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_L_IMUX28_10", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_L_IMUX24_10", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_L_BYP3_10", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_SW4A0_10", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_L_BYP2_10", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_MONITOR_P_10", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CMT_FIFO_L_IMUX26_10", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_CLK1_10", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_SW2A2_10", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_MONITOR_N_10", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CMT_FIFO_L_IMUX35_10", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_10", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "CMT_FIFO_NE4C1_10", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_L_FAN2_10", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_WW2END1_10", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_10", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "CMT_FIFO_EE4A2_10", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_10", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "CMT_FIFO_EE4A3_10", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_IMUX40_10", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_10", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "CMT_FIFO_NW4END1_10", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_L_IMUX29_10", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_LH1_10", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_10", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "CMT_FIFO_EE2A3_10", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_L_IMUX1_10", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_IMUX9_10", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX27_10", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_WL1END1_10", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_L_IMUX6_10", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_LH4_10", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_SW2A3_10", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_SE4BEG3_10", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_LH11_10", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_LH8_10", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_IMUX23_10", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_EE2BEG0_10", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_LH5_10", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_EE4B1_10", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_L_IMUX0_10", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_SE2A3_10", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_L_IMUX20_10", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_L_BYP1_10", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_EE4B0_10", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_WW4A1_10", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_10", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + -1, + 5 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_IMUX25_1", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_SW4END3_1", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_WW2END2_1", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_NE4C2_1", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_NW4END0_1", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_LH6_1", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_WW2END3_1", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_1", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CMT_FIFO_SE4C0_1", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_EE4B0_1", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_EE2A3_1", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_ER1BEG2_1", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_BYP3_1", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_NE4BEG0_1", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_L_CTRL1_1", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_SE2A2_1", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_SW4A2_1", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_L_FAN1_1", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_LH8_1", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_SW4A0_1", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_L_IMUX15_1", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_1", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CMT_FIFO_L_FAN6_1", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_L_IMUX40_1", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_1", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "CMT_FIFO_NE4C3_1", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_EE2BEG1_1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_SE4BEG2_1", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_1", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "CMT_FIFO_SW4END2_1", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_L_BYP7_1", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_NW2A0_1", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_L_IMUX2_1", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_L_CLK0_1", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_SW2A2_1", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_WW4END3_1", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_NE4C1_1", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_1", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CMT_FIFO_L_IMUX30_1", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_WW4C0_1", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_L_IMUX21_1", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_1", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CMT_FIFO_ER1BEG0_1", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_L_IMUX45_1", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_1", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "CMT_FIFO_WW2END1_1", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_L_IMUX16_1", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_1", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CMT_FIFO_SE4C3_1", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_LH12_1", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_L_IMUX43_1", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_L_IMUX10_1", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_EE2BEG0_1", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_IMUX34_1", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_NW4A2_1", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_1", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CMT_FIFO_L_IMUX3_1", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_SE4C2_1", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_L_FAN7_1", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_1", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CMT_FIFO_L_IMUX5_1", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_EL1BEG1_1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_1", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CMT_FIFO_SW4END0_1", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_EE4B3_1", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_WW4END1_1", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_WL1END3_1", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_L_IMUX14_1", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_SW2A0_1", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_NW4END2_1", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_BYP0_1", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_L_IMUX9_1", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX20_1", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_EE2A2_1", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_WW2A0_1", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_1", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_WL1END0_1", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_BYP5_1", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_L_FAN0_1", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_1", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CMT_FIFO_WW4B2_1", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_L_IMUX38_1", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_NW2A1_1", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_L_IMUX11_1", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_EE4BEG2_1", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_L_CTRL0_1", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_WR1END3_1", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_L_IMUX32_1", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_EE4C2_1", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_WW4C2_1", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_LH11_1", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_L_IMUX4_1", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_NE4BEG2_1", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_WW4C3_1", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_L_IMUX39_1", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_EE2BEG2_1", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_NE2A3_1", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_NE4BEG3_1", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX46_1", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_L_BYP4_1", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_L_IMUX6_1", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_L_IMUX44_1", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_IMUX23_1", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_EE2A0_1", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_EE4A1_1", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_L_FAN2_1", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_L_IMUX41_1", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_IMUX28_1", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_WR1END2_1", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_LH9_1", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_LH3_1", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_SE2A0_1", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_WW4B1_1", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_SW4END1_1", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_L_BYP1_1", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_WL1END2_1", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_L_IMUX24_1", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_LH10_1", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_WW4END0_1", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_IMUX1_1", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_FAN4_1", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_WW4B3_1", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_SE4BEG0_1", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX8_1", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_IMUX47_1", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_WW4A3_1", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_L_IMUX29_1", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_SW4A3_1", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_1", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "CMT_FIFO_EE4BEG0_1", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_NE2A2_1", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_EE4A3_1", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_LH2_1", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_NW4A3_1", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_WR1END1_1", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_EE4C3_1", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_WW2END0_1", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_WW4A2_1", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_L_IMUX19_1", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_LH5_1", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_EE2A1_1", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_LH7_1", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_NE2A1_1", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_L_IMUX7_1", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_WW4B0_1", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_EE2BEG3_1", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_SW2A3_1", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_SE2A3_1", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_WR1END0_1", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_L_IMUX18_1", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_L_BYP2_1", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_L_FAN5_1", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_SE4C1_1", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_1", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "CMT_FIFO_LH1_1", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_SE4BEG1_1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_SE4BEG3_1", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_SE2A1_1", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_EL1BEG3_1", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_NW4A0_1", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_L_BYP6_1", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_NW2A3_1", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_L_IMUX26_1", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_EE4C1_1", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_EE4B2_1", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_NE4C0_1", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_ER1BEG3_1", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_EE4C0_1", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_EL1BEG0_1", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_EE4BEG3_1", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_NW4A1_1", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_NW4END3_1", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_EE4A2_1", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_IMUX31_1", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_L_IMUX12_1", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_WW4C1_1", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_L_IMUX42_1", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_1", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "CMT_FIFO_L_IMUX33_1", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_1", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "CMT_FIFO_SW4A1_1", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_L_IMUX35_1", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_L_IMUX22_1", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_EE4A0_1", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_WW4A0_1", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_WW4A1_1", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_L_IMUX37_1", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_1", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_1", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CMT_FIFO_ER1BEG1_1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_IMUX17_1", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_EE4BEG1_1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_L_CLK1_1", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_1", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CMT_FIFO_WL1END1_1", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_NE4BEG1_1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX36_1", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_NW2A2_1", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_L_IMUX13_1", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_NE2A0_1", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_1", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "CMT_FIFO_L_IMUX0_1", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_LH4_1", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_L_IMUX27_1", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_EE4B1_1", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_L_FAN3_1", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_NW4END1_1", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_EL1BEG2_1", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_1", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_1", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "CMT_FIFO_WW4END2_1", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_SW2A1_1", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_WW2A3_1", + "INT_INTERFACE_WW2A3" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW4C0_7", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_WL1END1_7", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_WW4A0_7", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_NW4A3_7", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_NW4END2_7", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_SW4END0_7", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EE4C0_7", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EL1BEG1_7", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NE4BEG0_7", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_SW4A2_7", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NW4A2_7", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_SW2A3_7", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_WW4C3_7", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_NE4C0_7", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_LH6_7", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_EE4B3_7", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SE4C0_7", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_NW2A0_7", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_EE4C2_7", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW2A2_7", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_EE4B1_7", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EE2A2_7", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_NE4BEG3_7", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_LH9_7", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_LH8_7", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_LH2_7", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_EL1BEG0_7", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_WW2A3_7", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_SW2A2_7", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WW2END2_7", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_NW4A1_7", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_EE2BEG0_7", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_SE4BEG2_7", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_NW4END1_7", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_WW4END3_7", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_SW4END1_7", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_WW4END1_7", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EL1BEG3_7", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WL1END2_7", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SE2A1_7", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW4END0_7", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WW4B1_7", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_EE4BEG0_7", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE4C1_7", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_ER1BEG0_7", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_WL1END0_7", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SW2A0_7", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_EE4B0_7", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WW4A1_7", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EE4C3_7", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW4C1_7", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SE4BEG1_7", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_NW2A1_7", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SE2A3_7", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_EE2A3_7", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_EE4A1_7", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NE2A2_7", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_WR1END1_7", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SW4A3_7", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE4A3_7", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_SW4A0_7", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WR1END3_7", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_LH1_7", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_NE2A3_7", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_LH4_7", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_WW2A2_7", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_SE2A2_7", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_WW4C2_7", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_LH5_7", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_NE4BEG1_7", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_ER1BEG3_7", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW4B0_7", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_SW4END3_7", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NE2A0_7", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EE2A1_7", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_NE4C1_7", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_SE4C1_7", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_NE4BEG2_7", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG2_7", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_WW2END0_7", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_LH10_7", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WL1END3_7", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_LH11_7", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_LH3_7", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SE2A0_7", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE4A2_7", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4A0_7", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE2BEG1_7", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_EE2A0_7", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_NW4A0_7", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_WW4A3_7", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NW2A3_7", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NW4END0_7", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SE4BEG0_7", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_ER1BEG2_7", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_SE4C2_7", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_ER1BEG1_7", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WR1END0_7", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_EE4BEG1_7", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_EE2BEG3_7", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_EE4BEG3_7", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WW4END2_7", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_SW4A1_7", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_SE4BEG3_7", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EE4B2_7", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_LH7_7", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4A2_7", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WW4B2_7", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_NE4C2_7", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW2A0_7", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_NE4C3_7", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WW2END3_7", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_WW4B3_7", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SW4END2_7", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SE4C3_7", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_NW4END3_7", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_EE4BEG2_7", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_LH12_7", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW2END1_7", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE2BEG2_7", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW2A1_7", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_NE2A1_7", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_SW2A1_7", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_WR1END2_7", + "INT_FEEDTHRU_2_WR1END2" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -7 + ], + "wire_pairs": [ + [ + "CFG_CENTER_LH4_7", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_EE2BEG2_7", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX46_7", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW4C2_7", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WW4A1_7", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_LH11_7", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_CTRL0_7", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX16_7", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX7_7", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_CLK1_7", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_NW2A1_7", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_BYP3_7", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_BYP6_7", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_SE2A3_7", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_WW2END3_7", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_IMUX37_7", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SW4A1_7", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_NW4A0_7", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NW4A1_7", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_LH12_7", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX2_7", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_IMUX40_7", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_NW4A2_7", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_WL1END2_7", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_EE4C0_7", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_IMUX8_7", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_EE2A2_7", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_CTRL1_7", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_7", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_ER1BEG0_7", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_SW2A0_7", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_EE4BEG2_7", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX34_7", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_NE4C2_7", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_NW4END3_7", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_WR1END0_7", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EE4C1_7", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_LH10_7", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW4END1_7", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX27_7", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_WW2A2_7", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_WW4B1_7", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_SE2A1_7", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_IMUX39_7", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_WR1END3_7", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX21_7", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_EE4A0_7", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_SW2A1_7", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_EE4BEG0_7", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_EE2BEG1_7", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX41_7", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_LH1_7", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_SW2A2_7", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_EE4B0_7", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_EE2BEG0_7", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_NE4BEG2_7", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_FAN5_7", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SE4BEG1_7", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_WW4B2_7", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_IMUX44_7", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WW4END0_7", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX22_7", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_SW4A0_7", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_NW4END1_7", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SW4A3_7", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_WW4C3_7", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_SE4BEG0_7", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_SW2A3_7", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_IMUX45_7", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_EE4A1_7", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX1_7", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_NE2A0_7", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_FAN4_7", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_LH5_7", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_SE4BEG3_7", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX47_7", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_FAN1_7", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_NW4A3_7", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SW4END2_7", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_EL1BEG0_7", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_BYP4_7", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WW2END2_7", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_WW4A0_7", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_EE2A0_7", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WW2A1_7", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_EE4B2_7", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_SE2A0_7", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_LH3_7", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX38_7", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_7", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_7", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_IMUX25_7", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_EE4BEG1_7", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_IMUX30_7", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_EE4BEG3_7", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_NE4BEG1_7", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_7", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_IMUX42_7", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX4_7", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_WL1END1_7", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_IMUX32_7", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_NW4END2_7", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_NE4BEG0_7", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX3_7", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_WL1END0_7", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_SE2A2_7", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX28_7", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX10_7", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_BYP0_7", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_LH6_7", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX11_7", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX43_7", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_NE2A3_7", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_EL1BEG3_7", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW4C1_7", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_EE4A2_7", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX31_7", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_NW4END0_7", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_SW4END3_7", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX5_7", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_ER1BEG2_7", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_LH8_7", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_NE4C0_7", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_IMUX15_7", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_IMUX9_7", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_EL1BEG2_7", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX17_7", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_NW2A3_7", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_IMUX12_7", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_FAN6_7", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX23_7", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WL1END3_7", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_NW2A2_7", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW4B0_7", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_CLK0_7", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_WW2A0_7", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_EE4C3_7", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_WW2A3_7", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX18_7", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_EE4B1_7", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_SW4END0_7", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_NE4BEG3_7", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_EE2BEG3_7", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX36_7", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_FAN0_7", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX6_7", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_WW4C0_7", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX19_7", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_WW2END1_7", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_NE4C3_7", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_FAN3_7", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_7", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_SE4C3_7", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_NE4C1_7", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_ER1BEG1_7", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SE4C2_7", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WW4END2_7", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_7", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_WW2END0_7", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_LH7_7", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_BYP2_7", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_BYP7_7", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_SE4C1_7", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_EE4C2_7", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_EE4A3_7", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_SW4A2_7", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NW2A0_7", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_LH9_7", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_7", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_SW4END1_7", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_IMUX33_7", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_WW4A3_7", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_LH2_7", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX35_7", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_BYP5_7", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_EE4B3_7", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_IMUX0_7", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW4END3_7", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_EE2A1_7", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX13_7", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_SE4C0_7", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_WW4B3_7", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_WR1END2_7", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_ER1BEG3_7", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_BYP1_7", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_EE2A3_7", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EL1BEG1_7", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_IMUX14_7", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_FAN7_7", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX24_7", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_7", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_SE4BEG2_7", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_WW4A2_7", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_NE2A2_7", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WR1END1_7", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NE2A1_7", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX29_7", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX20_7", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_IMUX26_7", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_FAN2_7", + "VFRAME_FAN2" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CLK_HROW_SW4A2_4", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_IMUX28_4", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_IMUX43_4", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_IMUX4_4", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_SE4C3_4", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_IMUX14_4", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_EL1BEG3_4", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_NW4A0_4", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_IMUX5_4", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_SW4END0_4", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_IMUX35_4", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_LH3_4", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_NE4BEG1_4", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_EE4B0_4", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_WW2END0_4", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_NE4BEG2_4", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_EE4B1_4", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_EE4A0_4", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_FAN0_4", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_WW4B3_4", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_EE4C0_4", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_EE4A3_4", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_WR1END1_4", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_EE4A2_4", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_IMUX0_4", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_WL1END2_4", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_LH10_4", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_EE2BEG1_4", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_SW2A0_4", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_NE4C3_4", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_WW4C1_4", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_WW4C2_4", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_IMUX8_4", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_EE4BEG0_4", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_NW4END1_4", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_IMUX41_4", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_EL1BEG2_4", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_EE2A0_4", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_SE4BEG1_4", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_ER1BEG0_4", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_IMUX3_4", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_SE4BEG2_4", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_EE2BEG3_4", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_FAN5_4", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_SW2A3_4", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_LH5_4", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_IMUX23_4", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_CTRL1_4", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_WW4C3_4", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_EE2BEG2_4", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_WW2A1_4", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_WW2END2_4", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_IMUX30_4", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_BYP0_4", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_EE4BEG3_4", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_NE2A1_4", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_IMUX26_4", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_FAN1_4", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_IMUX13_4", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_MONITOR_P_4", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_HROW_IMUX7_4", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_WW4A3_4", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_EE4A1_4", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_ER1BEG1_4", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_NW4END2_4", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_WW4END0_4", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_WR1END3_4", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_IMUX29_4", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_WW4B0_4", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_SE2A3_4", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_IMUX19_4", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_LH11_4", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_BYP2_4", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_SW4A0_4", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_SE4C2_4", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_BYP3_4", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_NE4C1_4", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_NE2A0_4", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_WL1END1_4", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_LH2_4", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_NW4A1_4", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_IMUX1_4", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_IMUX31_4", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_FAN4_4", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_FAN3_4", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_SW4END3_4", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_IMUX2_4", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_NE2A3_4", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_MONITOR_N_4", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_HROW_LH8_4", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_CLK1_4", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_IMUX27_4", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_IMUX21_4", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_EL1BEG1_4", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_SE4C1_4", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_EL1BEG0_4", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_WW4A1_4", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_EE4B3_4", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_BYP7_4", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_SW2A2_4", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_IMUX37_4", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_IMUX34_4", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_BYP4_4", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_WW2A0_4", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_IMUX10_4", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_SE2A2_4", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_EE4C3_4", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_LH12_4", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_FAN2_4", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_EE2A1_4", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_BYP5_4", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_LH6_4", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_IMUX25_4", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_LH7_4", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_EE4C1_4", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_WW4END3_4", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_SW2A1_4", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_NE2A2_4", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_IMUX32_4", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_NW4END3_4", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_IMUX45_4", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_IMUX11_4", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_WL1END0_4", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_IMUX42_4", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_WW4B2_4", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_CTRL0_4", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_EE4BEG2_4", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_IMUX39_4", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_IMUX33_4", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_FAN6_4", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_NW2A3_4", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_LH4_4", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_IMUX24_4", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_WW4END1_4", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_SW4A3_4", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_LH1_4", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_WR1END2_4", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_SE2A0_4", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_WR1END0_4", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_ER1BEG3_4", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_IMUX46_4", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_ER1BEG2_4", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_LH9_4", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_EE2A2_4", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_NW2A0_4", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_IMUX47_4", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_NW2A2_4", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_WW4C0_4", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_CLK0_4", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_EE2A3_4", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_FAN7_4", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_IMUX44_4", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_SW4A1_4", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_IMUX38_4", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_IMUX12_4", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_WW2A3_4", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_EE4B2_4", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_IMUX16_4", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_SE4BEG3_4", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_SE4BEG0_4", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_BYP1_4", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_IMUX36_4", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_IMUX40_4", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_WW4A2_4", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_NE4C0_4", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_BYP6_4", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_SE4C0_4", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_IMUX18_4", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_NW4A3_4", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WL1END3_4", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_IMUX22_4", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_NE4BEG0_4", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_WW4A0_4", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_WW2A2_4", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_IMUX9_4", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_WW2END3_4", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_WW2END1_4", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_IMUX15_4", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_NE4BEG3_4", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_NW4END0_4", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_SW4END1_4", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_IMUX20_4", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_EE2BEG0_4", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_SW4END2_4", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_IMUX6_4", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_NW2A1_4", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_WW4B1_4", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_NE4C2_4", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_EE4BEG1_4", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_IMUX17_4", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_NW4A2_4", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_EE4C2_4", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_SE2A1_4", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_WW4END2_4", + "INT_INTERFACE_WW4END2" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "PCIE_LH4_7", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_EE4C1_7", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_MONITOR_N_7", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_EE2A2_7", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_EE2BEG2_7", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_SE2A3_7", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_IMUX2_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_WL1END2_7", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_SW4A3_7", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_SW4END0_7", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_WL1END3_7", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_IMUX28_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_NW4END3_7", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_7", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_SW4END2_7", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_7", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_WW2END3_7", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_CTRL0_R_7", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_EE4C0_7", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_ER1BEG3_7", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_IMUX12_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_EE4B0_7", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_WW4END0_7", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_WW4A0_7", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_WW4B0_7", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_IMUX39_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_WW4A2_7", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_BYP2_R_7", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_SE4BEG0_7", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_CLK0_R_7", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_NW4A2_7", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_WR1END1_7", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_NE4BEG2_7", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_WW4B2_7", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_IMUX1_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_IMUX35_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_7", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_IMUX4_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_LH9_7", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_EE2A3_7", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_IMUX45_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_IMUX40_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_EE2A1_7", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_SE2A2_7", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_EE4C3_7", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_WW4B1_7", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_EE4A3_7", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_IMUX0_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_NE4BEG1_7", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_SE4BEG2_7", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_IMUX29_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_7", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_WW4C3_7", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_LH3_7", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_SE2A1_7", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_SE4C1_7", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_NW4END1_7", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_WL1END1_7", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_7", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_NE2A3_7", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_7", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_IMUX15_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_SE2A0_7", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_ER1BEG2_7", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_WW2END1_7", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_SE4C0_7", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_EE4A1_7", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_WW2END0_7", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_7", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_EE2BEG3_7", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_FAN1_R_7", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_NW2A0_7", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_IMUX9_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_NE4BEG3_7", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_WW4A3_7", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_ER1BEG1_7", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_IMUX13_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_IMUX26_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_WW4C0_7", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_WR1END0_7", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_IMUX31_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_IMUX47_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_NW4END0_7", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_NW4A3_7", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_EE4BEG3_7", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_WW4END2_7", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_7", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_FAN2_R_7", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_NE2A0_7", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_ER1BEG0_7", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_BYP4_R_7", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_NW4A0_7", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_IMUX11_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_WR1END2_7", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_SW4A1_7", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_NE4C1_7", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_SW2A3_7", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX20_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_LH7_7", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_SW4END1_7", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_EL1BEG3_7", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_EL1BEG0_7", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_7", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_7", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_MONITOR_P_7", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_EE4A2_7", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_EE4BEG2_7", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX10_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_7", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_CTRL1_R_7", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_LH6_7", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_WW2END2_7", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_WW4B3_7", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_NE2A1_7", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_BYP6_R_7", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_IMUX8_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_LH10_7", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_WW2A3_7", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_7", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_7", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_NW4END2_7", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_IMUX17_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_7", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_IMUX36_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_7", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_EE4B3_7", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_EE4B2_7", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_SW2A2_7", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_BYP0_R_7", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_SW2A0_7", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_SE4BEG1_7", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_IMUX23_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_WW4C2_7", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_IMUX43_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_IMUX46_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_SE4C2_7", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_FAN4_R_7", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_CLK1_R_7", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_EL1BEG2_7", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_IMUX44_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_WW4END3_7", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_EE2BEG1_7", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX42_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_NW2A1_7", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_WW4END1_7", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_FAN0_R_7", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_IMUX33_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_FAN3_R_7", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_NW4A1_7", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_NE4BEG0_7", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_WL1END0_7", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_EE2A0_7", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_SW4END3_7", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_IMUX27_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_IMUX25_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_LH11_7", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_IMUX7_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_IMUX30_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_WW2A0_7", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_IMUX22_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_LH1_7", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_7", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_NW2A3_7", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_IMUX3_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_SE4BEG3_7", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_FAN5_R_7", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_LH12_7", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_IMUX34_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_WW2A2_7", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_IMUX16_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_BYP3_R_7", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_EE2BEG0_7", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_IMUX6_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_NE4C3_7", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_7", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_SW2A1_7", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_LH2_7", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_EE4C2_7", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_NW2A2_7", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_BYP1_R_7", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_IMUX37_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_7", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_EE4BEG0_7", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX38_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_7", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_SE4C3_7", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_IMUX32_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_IMUX14_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_WW2A1_7", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_NE4C2_7", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_NE2A2_7", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_NE4C0_7", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_WW4A1_7", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_FAN7_R_7", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_WR1END3_7", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_LH5_7", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_IMUX5_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_IMUX24_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_IMUX18_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_IMUX19_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_EE4A0_7", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_7", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_IMUX21_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_7", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_IMUX41_R_7", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_7", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_LH8_7", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_SW4A0_7", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_EE4B1_7", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_FAN6_R_7", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_BYP7_R_7", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_SW4A2_7", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_WW4C1_7", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_7", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_BYP5_R_7", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_EE4BEG1_7", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_7", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_EL1BEG1_7", + "INT_INTERFACE_EL1BEG1" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_TERM_R_GCLK0" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_TERM_R_GCLK31" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_TERM_R_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_TERM_R_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_TERM_R_GCLK29" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_TERM_R_GCLK15" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_TERM_R_GCLK24" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_TERM_R_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_TERM_R_GCLK22" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_TERM_R_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_TERM_R_GCLK14" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_TERM_R_GCLK16" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_TERM_R_GCLK9" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_TERM_R_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_TERM_R_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_TERM_R_GCLK10" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_TERM_R_GCLK3" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_TERM_R_GCLK4" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_TERM_R_GCLK26" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_TERM_R_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_TERM_R_GCLK28" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_TERM_R_GCLK25" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_TERM_R_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_TERM_R_GCLK18" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_TERM_R_GCLK20" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_TERM_R_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_TERM_R_GCLK12" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_TERM_R_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_TERM_R_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_TERM_R_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_TERM_R_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_TERM_R_GCLK6" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_TERM" + ] + }, + { + "grid_deltas": [ + 0, + 9 + ], + "wire_pairs": [ + [ + "MMCM_CLK_FREQ_BB_REBUF3_NS", + "TERM_CMT_FREQ_REF_NS3" + ], + [ + "MMCM_CLK_FREQ_BB_REBUF0_NS", + "TERM_CMT_FREQ_REF_NS0" + ], + [ + "MMCM_CLK_FREQ_BB_REBUF1_NS", + "TERM_CMT_FREQ_REF_NS1" + ], + [ + "MMCM_CLK_FREQ_BB_REBUF2_NS", + "TERM_CMT_FREQ_REF_NS2" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "TERM_CMT" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH12_0", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH9_0", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH1_0", + "VBRK_LH1" + ], + [ + "CMT_TOP_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH8_0", + "VBRK_LH8" + ], + [ + "CMT_TOP_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH5_0", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH4_0", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH3_0", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_LH10_0", + "VBRK_LH10" + ], + [ + "CMT_TOP_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH11_0", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH7_0", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH2_0", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH6_0", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SW4A1_0", + "VBRK_SW4A1" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 3 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX14", + "BRAM_IMUX14_UTURN_3" + ], + [ + "INT_INTERFACE_WW4END1", + "BRAM_WW4END1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B13", + "BRAM_LOGIC_OUTS_B13_3" + ], + [ + "INT_INTERFACE_LH10", + "BRAM_LH10_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX30", + "BRAM_IMUX30_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX27", + "BRAM_IMUX27_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX25", + "BRAM_IMUX25_UTURN_3" + ], + [ + "INT_INTERFACE_SW2A3", + "BRAM_SW2A3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B12", + "BRAM_LOGIC_OUTS_B12_3" + ], + [ + "INT_INTERFACE_WW4B2", + "BRAM_WW4B2_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX31", + "BRAM_IMUX31_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX27", + "BRAM_IMUX27_UTURN_3" + ], + [ + "INT_INTERFACE_EE4A3", + "BRAM_EE4A3_3" + ], + [ + "INT_INTERFACE_ER1BEG0", + "BRAM_ER1BEG0_3" + ], + [ + "INT_INTERFACE_EE4BEG3", + "BRAM_EE4BEG3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_3" + ], + [ + "INT_INTERFACE_SE4BEG2", + "BRAM_SE4BEG2_3" + ], + [ + "INT_INTERFACE_FAN3", + "BRAM_FAN3_3" + ], + [ + "INT_INTERFACE_LH1", + "BRAM_LH1_3" + ], + [ + "INT_INTERFACE_EE4C2", + "BRAM_EE4C2_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX41", + "BRAM_IMUX41_3" + ], + [ + "INT_INTERFACE_NW4A0", + "BRAM_NW4A0_3" + ], + [ + "INT_INTERFACE_NE4BEG0", + "BRAM_NE4BEG0_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B8", + "BRAM_LOGIC_OUTS_B8_3" + ], + [ + "INT_INTERFACE_LH11", + "BRAM_LH11_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX44", + "BRAM_IMUX44_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B3", + "BRAM_LOGIC_OUTS_B3_3" + ], + [ + "INT_INTERFACE_WR1END2", + "BRAM_WR1END2_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX39", + "BRAM_IMUX39_UTURN_3" + ], + [ + "INT_INTERFACE_EL1BEG0", + "BRAM_EL1BEG0_3" + ], + [ + "INT_INTERFACE_SE4C2", + "BRAM_SE4C2_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B2", + "BRAM_LOGIC_OUTS_B2_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX28", + "BRAM_IMUX28_UTURN_3" + ], + [ + "INT_INTERFACE_FAN0", + "BRAM_FAN0_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX35", + "BRAM_IMUX35_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX43", + "BRAM_IMUX43_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX11", + "BRAM_IMUX11_UTURN_3" + ], + [ + "INT_INTERFACE_WW4B1", + "BRAM_WW4B1_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_3" + ], + [ + "INT_INTERFACE_EE2A1", + "BRAM_EE2A1_3" + ], + [ + "INT_INTERFACE_FAN2", + "BRAM_FAN2_3" + ], + [ + "INT_INTERFACE_WL1END2", + "BRAM_WL1END2_3" + ], + [ + "INT_INTERFACE_ER1BEG3", + "BRAM_ER1BEG3_3" + ], + [ + "INT_INTERFACE_EE4BEG2", + "BRAM_EE4BEG2_3" + ], + [ + "INT_INTERFACE_NW2A0", + "BRAM_NW2A0_3" + ], + [ + "INT_INTERFACE_BYP6", + "BRAM_BYP6_3" + ], + [ + "INT_INTERFACE_EE4B2", + "BRAM_EE4B2_3" + ], + [ + "INT_INTERFACE_NE2A1", + "BRAM_NE2A1_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX37", + "BRAM_IMUX37_3" + ], + [ + "INT_INTERFACE_SE2A3", + "BRAM_SE2A3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX26", + "BRAM_IMUX26_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX10", + "BRAM_IMUX10_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_3" + ], + [ + "INT_INTERFACE_EE4B1", + "BRAM_EE4B1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX16", + "BRAM_IMUX16_UTURN_3" + ], + [ + "INT_INTERFACE_NW2A3", + "BRAM_NW2A3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B22", + "BRAM_LOGIC_OUTS_B22_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX18", + "BRAM_IMUX18_UTURN_3" + ], + [ + "INT_INTERFACE_WW2END2", + "BRAM_WW2END2_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX1", + "BRAM_IMUX1_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX21", + "BRAM_IMUX21_UTURN_3" + ], + [ + "INT_INTERFACE_WR1END1", + "BRAM_WR1END1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B1", + "BRAM_LOGIC_OUTS_B1_3" + ], + [ + "INT_INTERFACE_SE4BEG0", + "BRAM_SE4BEG0_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX13", + "BRAM_IMUX13_UTURN_3" + ], + [ + "INT_INTERFACE_WL1END0", + "BRAM_WL1END0_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX42", + "BRAM_IMUX42_3" + ], + [ + "INT_INTERFACE_EE2A3", + "BRAM_EE2A3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B19", + "BRAM_LOGIC_OUTS_B19_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B14", + "BRAM_LOGIC_OUTS_B14_3" + ], + [ + "INT_INTERFACE_SE2A2", + "BRAM_SE2A2_3" + ], + [ + "INT_INTERFACE_CTRL1", + "BRAM_CTRL1_3" + ], + [ + "INT_INTERFACE_EE4C0", + "BRAM_EE4C0_3" + ], + [ + "INT_INTERFACE_WW4END0", + "BRAM_WW4END0_3" + ], + [ + "INT_INTERFACE_SW4END0", + "BRAM_SW4END0_3" + ], + [ + "INT_INTERFACE_SW4END3", + "BRAM_SW4END3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B5", + "BRAM_LOGIC_OUTS_B5_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX43", + "BRAM_IMUX43_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX22", + "BRAM_IMUX22_3" + ], + [ + "INT_INTERFACE_LH8", + "BRAM_LH8_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_3" + ], + [ + "INT_INTERFACE_NE4BEG1", + "BRAM_NE4BEG1_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_3" + ], + [ + "INT_INTERFACE_SE4C3", + "BRAM_SE4C3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX25", + "BRAM_IMUX25_3" + ], + [ + "INT_INTERFACE_BYP7", + "BRAM_BYP7_3" + ], + [ + "INT_INTERFACE_WW4A2", + "BRAM_WW4A2_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX21", + "BRAM_IMUX21_3" + ], + [ + "INT_INTERFACE_FAN1", + "BRAM_FAN1_3" + ], + [ + "INT_INTERFACE_NE4C0", + "BRAM_NE4C0_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX3", + "BRAM_IMUX3_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX47", + "BRAM_IMUX47_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_3" + ], + [ + "INT_INTERFACE_EE4B0", + "BRAM_EE4B0_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX45", + "BRAM_IMUX45_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B9", + "BRAM_LOGIC_OUTS_B9_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX22", + "BRAM_IMUX22_UTURN_3" + ], + [ + "INT_INTERFACE_WW4B0", + "BRAM_WW4B0_3" + ], + [ + "INT_INTERFACE_NE4BEG3", + "BRAM_NE4BEG3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX12", + "BRAM_IMUX12_UTURN_3" + ], + [ + "INT_INTERFACE_NW4END1", + "BRAM_NW4END1_3" + ], + [ + "INT_INTERFACE_NW4A3", + "BRAM_NW4A3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX29", + "BRAM_IMUX29_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX40", + "BRAM_IMUX40_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX15", + "BRAM_IMUX15_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX8", + "BRAM_IMUX8_UTURN_3" + ], + [ + "INT_INTERFACE_WW4A0", + "BRAM_WW4A0_3" + ], + [ + "INT_INTERFACE_EE2A0", + "BRAM_EE2A0_3" + ], + [ + "INT_INTERFACE_WW2A2", + "BRAM_WW2A2_3" + ], + [ + "INT_INTERFACE_EE4B3", + "BRAM_EE4B3_3" + ], + [ + "INT_INTERFACE_NE2A3", + "BRAM_NE2A3_3" + ], + [ + "INT_INTERFACE_EE4A1", + "BRAM_EE4A1_3" + ], + [ + "INT_INTERFACE_SW4A1", + "BRAM_SW4A1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX44", + "BRAM_IMUX44_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_3" + ], + [ + "INT_INTERFACE_EL1BEG3", + "BRAM_EL1BEG3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_3" + ], + [ + "INT_INTERFACE_NW2A1", + "BRAM_NW2A1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX32", + "BRAM_IMUX32_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX26", + "BRAM_IMUX26_UTURN_3" + ], + [ + "INT_INTERFACE_SW4A2", + "BRAM_SW4A2_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX42", + "BRAM_IMUX42_UTURN_3" + ], + [ + "INT_INTERFACE_BYP3", + "BRAM_BYP3_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX34", + "BRAM_IMUX34_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_3" + ], + [ + "INT_INTERFACE_FAN6", + "BRAM_FAN6_3" + ], + [ + "INT_INTERFACE_EE2BEG3", + "BRAM_EE2BEG3_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX40", + "BRAM_IMUX40_UTURN_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B16", + "BRAM_LOGIC_OUTS_B16_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX46", + "BRAM_IMUX46_UTURN_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B0", + "BRAM_LOGIC_OUTS_B0_3" + ], + [ + "INT_INTERFACE_NE4C3", + "BRAM_NE4C3_3" + ], + [ + "INT_INTERFACE_NE4C1", + "BRAM_NE4C1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX4", + "BRAM_IMUX4_UTURN_3" + ], + [ + "INT_INTERFACE_EE4BEG1", + "BRAM_EE4BEG1_3" + ], + [ + "INT_INTERFACE_SE2A1", + "BRAM_SE2A1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX20", + "BRAM_IMUX20_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX35", + "BRAM_IMUX35_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX9", + "BRAM_IMUX9_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX47", + "BRAM_IMUX47_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX24", + "BRAM_IMUX24_3" + ], + [ + "INT_INTERFACE_NW4END0", + "BRAM_NW4END0_3" + ], + [ + "INT_INTERFACE_WW4A3", + "BRAM_WW4A3_3" + ], + [ + "INT_INTERFACE_SW4END2", + "BRAM_SW4END2_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B15", + "BRAM_LOGIC_OUTS_B15_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX2", + "BRAM_IMUX2_UTURN_3" + ], + [ + "INT_INTERFACE_WW4A1", + "BRAM_WW4A1_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_3" + ], + [ + "INT_INTERFACE_WW4END3", + "BRAM_WW4END3_3" + ], + [ + "INT_INTERFACE_SW2A0", + "BRAM_SW2A0_3" + ], + [ + "INT_INTERFACE_SE4C1", + "BRAM_SE4C1_3" + ], + [ + "INT_INTERFACE_WW2A3", + "BRAM_WW2A3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX36", + "BRAM_IMUX36_3" + ], + [ + "INT_INTERFACE_WW4C1", + "BRAM_WW4C1_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX23", + "BRAM_IMUX23_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B4", + "BRAM_LOGIC_OUTS_B4_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B21", + "BRAM_LOGIC_OUTS_B21_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX5", + "BRAM_IMUX5_UTURN_3" + ], + [ + "INT_INTERFACE_EE4C1", + "BRAM_EE4C1_3" + ], + [ + "INT_INTERFACE_SE4C0", + "BRAM_SE4C0_3" + ], + [ + "INT_INTERFACE_BYP2", + "BRAM_BYP2_3" + ], + [ + "INT_INTERFACE_LH4", + "BRAM_LH4_3" + ], + [ + "INT_INTERFACE_FAN7", + "BRAM_FAN7_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX0", + "BRAM_IMUX0_UTURN_3" + ], + [ + "INT_INTERFACE_CLK1", + "BRAM_CLK1_3" + ], + [ + "INT_INTERFACE_SE4BEG1", + "BRAM_SE4BEG1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX23", + "BRAM_IMUX23_UTURN_3" + ], + [ + "INT_INTERFACE_EE4BEG0", + "BRAM_EE4BEG0_3" + ], + [ + "INT_INTERFACE_CTRL0", + "BRAM_CTRL0_3" + ], + [ + "INT_INTERFACE_WL1END1", + "BRAM_WL1END1_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX33", + "BRAM_IMUX33_3" + ], + [ + "INT_INTERFACE_LH3", + "BRAM_LH3_3" + ], + [ + "INT_INTERFACE_WW4C3", + "BRAM_WW4C3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_3" + ], + [ + "INT_INTERFACE_NW4A2", + "BRAM_NW4A2_3" + ], + [ + "INT_INTERFACE_MONITOR_N", + "BRAM_MONITOR_N_3" + ], + [ + "INT_INTERFACE_NE4BEG2", + "BRAM_NE4BEG2_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX38", + "BRAM_IMUX38_UTURN_3" + ], + [ + "INT_INTERFACE_EL1BEG1", + "BRAM_EL1BEG1_3" + ], + [ + "INT_INTERFACE_NE2A2", + "BRAM_NE2A2_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX39", + "BRAM_IMUX39_3" + ], + [ + "INT_INTERFACE_SW2A1", + "BRAM_SW2A1_3" + ], + [ + "INT_INTERFACE_LH5", + "BRAM_LH5_3" + ], + [ + "INT_INTERFACE_SW4END1", + "BRAM_SW4END1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B23", + "BRAM_LOGIC_OUTS_B23_3" + ], + [ + "INT_INTERFACE_EE4A0", + "BRAM_EE4A0_3" + ], + [ + "INT_INTERFACE_WW2END1", + "BRAM_WW2END1_3" + ], + [ + "INT_INTERFACE_WR1END3", + "BRAM_WR1END3_3" + ], + [ + "INT_INTERFACE_SW2A2", + "BRAM_SW2A2_3" + ], + [ + "INT_INTERFACE_NW4END2", + "BRAM_NW4END2_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B18", + "BRAM_LOGIC_OUTS_B18_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX34", + "BRAM_IMUX34_3" + ], + [ + "INT_INTERFACE_ER1BEG1", + "BRAM_ER1BEG1_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX46", + "BRAM_IMUX46_3" + ], + [ + "INT_INTERFACE_WW4B3", + "BRAM_WW4B3_3" + ], + [ + "INT_INTERFACE_FAN4", + "BRAM_FAN4_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX30", + "BRAM_IMUX30_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B7", + "BRAM_LOGIC_OUTS_B7_3" + ], + [ + "INT_INTERFACE_LH7", + "BRAM_LH7_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX24", + "BRAM_IMUX24_UTURN_3" + ], + [ + "INT_INTERFACE_BYP5", + "BRAM_BYP5_3" + ], + [ + "INT_INTERFACE_EE2BEG2", + "BRAM_EE2BEG2_3" + ], + [ + "INT_INTERFACE_EL1BEG2", + "BRAM_EL1BEG2_3" + ], + [ + "INT_INTERFACE_WR1END0", + "BRAM_WR1END0_3" + ], + [ + "INT_INTERFACE_MONITOR_P", + "BRAM_MONITOR_P_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX17", + "BRAM_IMUX17_UTURN_3" + ], + [ + "INT_INTERFACE_WL1END3", + "BRAM_WL1END3_3" + ], + [ + "INT_INTERFACE_SW4A3", + "BRAM_SW4A3_3" + ], + [ + "INT_INTERFACE_SE4BEG3", + "BRAM_SE4BEG3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX38", + "BRAM_IMUX38_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX33", + "BRAM_IMUX33_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_3" + ], + [ + "INT_INTERFACE_WW4END2", + "BRAM_WW4END2_3" + ], + [ + "INT_INTERFACE_CLK0", + "BRAM_CLK0_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX32", + "BRAM_IMUX32_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX36", + "BRAM_IMUX36_UTURN_3" + ], + [ + "INT_INTERFACE_EE2A2", + "BRAM_EE2A2_3" + ], + [ + "INT_INTERFACE_NE2A0", + "BRAM_NE2A0_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B6", + "BRAM_LOGIC_OUTS_B6_3" + ], + [ + "INT_INTERFACE_WW4C2", + "BRAM_WW4C2_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_3" + ], + [ + "INT_INTERFACE_SE2A0", + "BRAM_SE2A0_3" + ], + [ + "INT_INTERFACE_LH2", + "BRAM_LH2_3" + ], + [ + "INT_INTERFACE_SW4A0", + "BRAM_SW4A0_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B20", + "BRAM_LOGIC_OUTS_B20_3" + ], + [ + "INT_INTERFACE_EE2BEG0", + "BRAM_EE2BEG0_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX45", + "BRAM_IMUX45_UTURN_3" + ], + [ + "INT_INTERFACE_EE2BEG1", + "BRAM_EE2BEG1_3" + ], + [ + "INT_INTERFACE_EE4C3", + "BRAM_EE4C3_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX6", + "BRAM_IMUX6_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX19", + "BRAM_IMUX19_UTURN_3" + ], + [ + "INT_INTERFACE_LH9", + "BRAM_LH9_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX31", + "BRAM_IMUX31_3" + ], + [ + "INT_INTERFACE_WW2END3", + "BRAM_WW2END3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B11", + "BRAM_LOGIC_OUTS_B11_3" + ], + [ + "INT_INTERFACE_NE4C2", + "BRAM_NE4C2_3" + ], + [ + "INT_INTERFACE_LH6", + "BRAM_LH6_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_3" + ], + [ + "INT_INTERFACE_WW2A1", + "BRAM_WW2A1_3" + ], + [ + "INT_INTERFACE_NW4END3", + "BRAM_NW4END3_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX7", + "BRAM_IMUX7_UTURN_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B10", + "BRAM_LOGIC_OUTS_B10_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX37", + "BRAM_IMUX37_UTURN_3" + ], + [ + "INT_INTERFACE_BYP1", + "BRAM_BYP1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX41", + "BRAM_IMUX41_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX29", + "BRAM_IMUX29_UTURN_3" + ], + [ + "INT_INTERFACE_ER1BEG2", + "BRAM_ER1BEG2_3" + ], + [ + "INT_INTERFACE_WW2A0", + "BRAM_WW2A0_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_3" + ], + [ + "INT_INTERFACE_NW4A1", + "BRAM_NW4A1_3" + ], + [ + "INT_INTERFACE_WW4C0", + "BRAM_WW4C0_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_3" + ], + [ + "INT_INTERFACE_WW2END0", + "BRAM_WW2END0_3" + ], + [ + "INT_INTERFACE_FAN5", + "BRAM_FAN5_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_3" + ], + [ + "INT_INTERFACE_LH12", + "BRAM_LH12_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX28", + "BRAM_IMUX28_3" + ], + [ + "INT_INTERFACE_BYP0", + "BRAM_BYP0_3" + ], + [ + "INT_INTERFACE_BYP4", + "BRAM_BYP4_3" + ], + [ + "INT_INTERFACE_NW2A2", + "BRAM_NW2A2_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B17", + "BRAM_LOGIC_OUTS_B17_3" + ], + [ + "INT_INTERFACE_EE4A2", + "BRAM_EE4A2_3" + ] + ], + "tile_types": [ + "BRAM_INT_INTERFACE_R", + "BRAM_R" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "CMT_FIFO_NW2A3_5", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_EE2BEG3_5", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_EE2A1_5", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_L_IMUX23_5", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_EE4A2_5", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_5", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_NW4A1_5", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_LH7_5", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_EE4BEG2_5", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_SW2A0_5", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_ER1BEG3_5", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_L_IMUX8_5", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_5", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "CMT_FIFO_EE4C1_5", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_SE4BEG0_5", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX42_5", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_5", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "CMT_FIFO_SE4BEG1_5", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_NE2A3_5", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_SW4END2_5", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_NE2A2_5", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_L_IMUX30_5", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_LH4_5", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_EL1BEG2_5", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_L_IMUX33_5", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_L_IMUX21_5", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_NW4END1_5", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_5", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "CMT_FIFO_SE4BEG3_5", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_L_FAN1_5", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_NE4BEG0_5", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_NE4C3_5", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_5", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "CMT_FIFO_L_FAN7_5", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_L_IMUX14_5", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_5", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "CMT_FIFO_EL1BEG0_5", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_L_IMUX2_5", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_SW4A0_5", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_SE4C0_5", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_EE4BEG3_5", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_5", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "CMT_FIFO_EE4A0_5", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_L_IMUX19_5", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_L_CLK1_5", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_LH1_5", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_SW4A1_5", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_L_FAN5_5", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_5", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "CMT_FIFO_WW4C1_5", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_SE4BEG2_5", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_L_BYP2_5", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_L_FAN4_5", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_5", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "CMT_FIFO_WW4END2_5", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_WW4B2_5", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_EE4BEG1_5", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_WW2A2_5", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_WW2END2_5", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_L_IMUX40_5", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_WW4C2_5", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_ER1BEG1_5", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_5", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "CMT_FIFO_WR1END1_5", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_NW2A2_5", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_WW4A2_5", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_5", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_5", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "CMT_FIFO_LH8_5", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_IMUX16_5", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_WW4C3_5", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_L_IMUX4_5", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_WR1END3_5", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_WW2END0_5", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_SE4C1_5", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_SW4END1_5", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_LH3_5", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_EE4A3_5", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_SE4C2_5", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_5", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "CMT_FIFO_EE4BEG0_5", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_5", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "CMT_FIFO_L_IMUX41_5", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_IMUX7_5", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_WW4END0_5", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_LH12_5", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_ER1BEG0_5", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_5", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "CMT_FIFO_WW4A0_5", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_WW4B0_5", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_5", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "CMT_FIFO_WW4A3_5", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_LH10_5", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_WW4C0_5", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_SW4A3_5", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_L_IMUX27_5", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_WR1END0_5", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_NW2A0_5", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_L_IMUX6_5", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_EL1BEG1_5", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_LH5_5", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_L_IMUX0_5", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_EE2BEG0_5", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_IMUX26_5", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_WW4B1_5", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_5", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "CMT_FIFO_L_IMUX32_5", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_L_BYP1_5", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_L_FAN0_5", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_EE4B3_5", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_5", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "CMT_FIFO_NE2A1_5", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_EE4C0_5", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_EL1BEG3_5", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_SE2A1_5", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_L_IMUX44_5", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_IMUX24_5", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_WW2A1_5", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_WW2END3_5", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_L_IMUX12_5", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_L_CTRL0_5", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_EE4B0_5", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_L_IMUX25_5", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_SW4END0_5", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_SE2A3_5", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_SE4C3_5", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_FAN3_5", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_EE4C2_5", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_L_BYP0_5", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_L_IMUX1_5", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_SW2A1_5", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_L_IMUX15_5", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_FAN6_5", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_L_IMUX39_5", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_L_BYP4_5", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_L_IMUX20_5", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_SW2A3_5", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_EE2BEG2_5", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_NW4END2_5", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_5", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "CMT_FIFO_L_IMUX13_5", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_NW4END0_5", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_L_IMUX34_5", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_NW4A3_5", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_NW4A2_5", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_L_IMUX9_5", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX38_5", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_LH11_5", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_EE2BEG1_5", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_NW4A0_5", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_SE2A2_5", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_LH9_5", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_L_IMUX31_5", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_WW4END3_5", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_WW4B3_5", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_LH6_5", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_EE4C3_5", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_L_BYP6_5", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_L_IMUX47_5", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_NE4BEG1_5", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_SW4A2_5", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_L_BYP3_5", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_SW2A2_5", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_NE4BEG3_5", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_NE4BEG2_5", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_L_CLK0_5", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_WW2A3_5", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_L_BYP7_5", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_NE4C0_5", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_EE2A3_5", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_EE4A1_5", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_L_FAN2_5", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_WW2END1_5", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_NE4C1_5", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_L_CTRL1_5", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_SE2A0_5", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_EE4B2_5", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_ER1BEG2_5", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_WL1END3_5", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_WL1END2_5", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_WW4END1_5", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_NE2A0_5", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_IMUX37_5", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_SW4END3_5", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_EE2A2_5", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_5", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "CMT_FIFO_WL1END0_5", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_IMUX29_5", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_LH2_5", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_L_IMUX3_5", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_EE2A0_5", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_5", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "CMT_FIFO_L_IMUX43_5", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_NE4C2_5", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_WR1END2_5", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_L_IMUX28_5", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_L_IMUX45_5", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_L_IMUX18_5", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_L_BYP5_5", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_L_IMUX11_5", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_WW2A0_5", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_5", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "CMT_FIFO_L_IMUX5_5", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_WW4A1_5", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_L_IMUX17_5", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_WL1END1_5", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_L_IMUX46_5", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_NW4END3_5", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_5", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "CMT_FIFO_L_IMUX36_5", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_NW2A1_5", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_L_IMUX35_5", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_EE4B1_5", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_L_IMUX10_5", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_5", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "CMT_FIFO_L_IMUX22_5", + "INT_INTERFACE_IMUX22" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLBLM_M_CIN", + "HCLK_CLB_COUT1_R" + ], + [ + "CLBLM_L_CIN", + "HCLK_CLB_COUT0_R" + ] + ], + "tile_types": [ + "CLBLM_R", + "HCLK_CLB" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "BRKH_DSP_ACIN20", + "DSP_0_ACIN20" + ], + [ + "BRKH_DSP_ACIN13", + "DSP_0_ACIN13" + ], + [ + "BRKH_DSP_BCIN0", + "DSP_0_BCIN0" + ], + [ + "BRKH_DSP_PCIN42", + "DSP_0_PCIN42" + ], + [ + "BRKH_DSP_PCIN3", + "DSP_0_PCIN3" + ], + [ + "BRKH_DSP_PCIN7", + "DSP_0_PCIN7" + ], + [ + "BRKH_DSP_PCIN37", + "DSP_0_PCIN37" + ], + [ + "BRKH_DSP_ACIN24", + "DSP_0_ACIN24" + ], + [ + "BRKH_DSP_PCIN31", + "DSP_0_PCIN31" + ], + [ + "BRKH_DSP_ACIN25", + "DSP_0_ACIN25" + ], + [ + "BRKH_DSP_PCIN40", + "DSP_0_PCIN40" + ], + [ + "BRKH_DSP_BCIN7", + "DSP_0_BCIN7" + ], + [ + "BRKH_DSP_ACIN15", + "DSP_0_ACIN15" + ], + [ + "BRKH_DSP_BCIN4", + "DSP_0_BCIN4" + ], + [ + "BRKH_DSP_ACIN23", + "DSP_0_ACIN23" + ], + [ + "BRKH_DSP_ACIN6", + "DSP_0_ACIN6" + ], + [ + "BRKH_DSP_BCIN14", + "DSP_0_BCIN14" + ], + [ + "BRKH_DSP_PCIN16", + "DSP_0_PCIN16" + ], + [ + "BRKH_DSP_PCIN24", + "DSP_0_PCIN24" + ], + [ + "BRKH_DSP_BCIN8", + "DSP_0_BCIN8" + ], + [ + "BRKH_DSP_PCIN45", + "DSP_0_PCIN45" + ], + [ + "BRKH_DSP_BCIN15", + "DSP_0_BCIN15" + ], + [ + "BRKH_DSP_ACIN26", + "DSP_0_ACIN26" + ], + [ + "BRKH_DSP_PCIN41", + "DSP_0_PCIN41" + ], + [ + "BRKH_DSP_ACIN2", + "DSP_0_ACIN2" + ], + [ + "BRKH_DSP_PCIN5", + "DSP_0_PCIN5" + ], + [ + "BRKH_DSP_ACIN4", + "DSP_0_ACIN4" + ], + [ + "BRKH_DSP_BCIN10", + "DSP_0_BCIN10" + ], + [ + "BRKH_DSP_BCIN16", + "DSP_0_BCIN16" + ], + [ + "BRKH_DSP_ACIN8", + "DSP_0_ACIN8" + ], + [ + "BRKH_DSP_ACIN7", + "DSP_0_ACIN7" + ], + [ + "BRKH_DSP_ACIN16", + "DSP_0_ACIN16" + ], + [ + "BRKH_DSP_PCIN15", + "DSP_0_PCIN15" + ], + [ + "BRKH_DSP_MULTSIGNIN", + "DSP_0_MULTSIGNIN" + ], + [ + "BRKH_DSP_PCIN13", + "DSP_0_PCIN13" + ], + [ + "BRKH_DSP_ACIN27", + "DSP_0_ACIN27" + ], + [ + "BRKH_DSP_PCIN19", + "DSP_0_PCIN19" + ], + [ + "BRKH_DSP_PCIN38", + "DSP_0_PCIN38" + ], + [ + "BRKH_DSP_ACIN1", + "DSP_0_ACIN1" + ], + [ + "BRKH_DSP_ACIN17", + "DSP_0_ACIN17" + ], + [ + "BRKH_DSP_ACIN10", + "DSP_0_ACIN10" + ], + [ + "BRKH_DSP_BCIN13", + "DSP_0_BCIN13" + ], + [ + "BRKH_DSP_PCIN43", + "DSP_0_PCIN43" + ], + [ + "BRKH_DSP_PCIN1", + "DSP_0_PCIN1" + ], + [ + "BRKH_DSP_PCIN25", + "DSP_0_PCIN25" + ], + [ + "BRKH_DSP_BCIN6", + "DSP_0_BCIN6" + ], + [ + "BRKH_DSP_ACIN29", + "DSP_0_ACIN29" + ], + [ + "BRKH_DSP_PCIN6", + "DSP_0_PCIN6" + ], + [ + "BRKH_DSP_PCIN20", + "DSP_0_PCIN20" + ], + [ + "BRKH_DSP_PCIN12", + "DSP_0_PCIN12" + ], + [ + "BRKH_DSP_BCIN3", + "DSP_0_BCIN3" + ], + [ + "BRKH_DSP_BCIN11", + "DSP_0_BCIN11" + ], + [ + "BRKH_DSP_BCIN17", + "DSP_0_BCIN17" + ], + [ + "BRKH_DSP_PCIN35", + "DSP_0_PCIN35" + ], + [ + "BRKH_DSP_PCIN14", + "DSP_0_PCIN14" + ], + [ + "BRKH_DSP_PCIN28", + "DSP_0_PCIN28" + ], + [ + "BRKH_DSP_ACIN3", + "DSP_0_ACIN3" + ], + [ + "BRKH_DSP_PCIN46", + "DSP_0_PCIN46" + ], + [ + "BRKH_DSP_PCIN21", + "DSP_0_PCIN21" + ], + [ + "BRKH_DSP_PCIN36", + "DSP_0_PCIN36" + ], + [ + "BRKH_DSP_ACIN21", + "DSP_0_ACIN21" + ], + [ + "BRKH_DSP_ACIN28", + "DSP_0_ACIN28" + ], + [ + "BRKH_DSP_PCIN34", + "DSP_0_PCIN34" + ], + [ + "BRKH_DSP_BCIN5", + "DSP_0_BCIN5" + ], + [ + "BRKH_DSP_ACIN18", + "DSP_0_ACIN18" + ], + [ + "BRKH_DSP_BCIN2", + "DSP_0_BCIN2" + ], + [ + "BRKH_DSP_PCIN8", + "DSP_0_PCIN8" + ], + [ + "BRKH_DSP_BCIN9", + "DSP_0_BCIN9" + ], + [ + "BRKH_DSP_PCIN23", + "DSP_0_PCIN23" + ], + [ + "BRKH_DSP_ACIN22", + "DSP_0_ACIN22" + ], + [ + "BRKH_DSP_PCIN44", + "DSP_0_PCIN44" + ], + [ + "BRKH_DSP_BCIN12", + "DSP_0_BCIN12" + ], + [ + "BRKH_DSP_ACIN19", + "DSP_0_ACIN19" + ], + [ + "BRKH_DSP_PCIN17", + "DSP_0_PCIN17" + ], + [ + "BRKH_DSP_BCIN1", + "DSP_0_BCIN1" + ], + [ + "BRKH_DSP_CARRYCASCIN", + "DSP_0_CARRYCASCIN" + ], + [ + "BRKH_DSP_PCIN11", + "DSP_0_PCIN11" + ], + [ + "BRKH_DSP_ACIN0", + "DSP_0_ACIN0" + ], + [ + "BRKH_DSP_PCIN30", + "DSP_0_PCIN30" + ], + [ + "BRKH_DSP_PCIN10", + "DSP_0_PCIN10" + ], + [ + "BRKH_DSP_ACIN5", + "DSP_0_ACIN5" + ], + [ + "BRKH_DSP_ACIN9", + "DSP_0_ACIN9" + ], + [ + "BRKH_DSP_PCIN26", + "DSP_0_PCIN26" + ], + [ + "BRKH_DSP_PCIN32", + "DSP_0_PCIN32" + ], + [ + "BRKH_DSP_PCIN0", + "DSP_0_PCIN0" + ], + [ + "BRKH_DSP_ACIN11", + "DSP_0_ACIN11" + ], + [ + "BRKH_DSP_PCIN4", + "DSP_0_PCIN4" + ], + [ + "BRKH_DSP_PCIN39", + "DSP_0_PCIN39" + ], + [ + "BRKH_DSP_PCIN18", + "DSP_0_PCIN18" + ], + [ + "BRKH_DSP_PCIN22", + "DSP_0_PCIN22" + ], + [ + "BRKH_DSP_PCIN29", + "DSP_0_PCIN29" + ], + [ + "BRKH_DSP_ACIN12", + "DSP_0_ACIN12" + ], + [ + "BRKH_DSP_ACIN14", + "DSP_0_ACIN14" + ], + [ + "BRKH_DSP_PCIN33", + "DSP_0_PCIN33" + ], + [ + "BRKH_DSP_PCIN47", + "DSP_0_PCIN47" + ], + [ + "BRKH_DSP_PCIN2", + "DSP_0_PCIN2" + ], + [ + "BRKH_DSP_PCIN9", + "DSP_0_PCIN9" + ], + [ + "BRKH_DSP_PCIN27", + "DSP_0_PCIN27" + ] + ], + "tile_types": [ + "BRKH_DSP_R", + "DSP_R" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_IN8", + "HCLK_DSP_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_DSP_CK_IN12" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_DSP_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_DSP_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_DSP_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_DSP_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_DSP_CK_IN0" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_DSP_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_DSP_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_DSP_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_DSP_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_DSP_CK_IN2" + ], + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_DSP_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_DSP_CK_IN5" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_DSP_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_DSP_CK_IN9" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_DSP_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_DSP_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_DSP_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_DSP_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_DSP_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_DSP_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_DSP_CK_IN10" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_DSP_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_DSP_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_DSP_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_DSP_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_DSP_CK_IN13" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_DSP_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_DSP_CK_BUFHCLK11" + ] + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_DSP_R" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B21_3", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_LOGIC_OUTS_B9_3", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX40_3", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B10_3", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_CTRL0_3", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_BYP0_3", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_BYP3_3", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_BYP5_3", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX2_3", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_FAN2_3", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_FAN1_3", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B8_3", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_LOGIC_OUTS_B13_3", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_CTRL1_3", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX47_3", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_LOGIC_OUTS_B0_3", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX9_3", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX32_3", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX25_3", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX39_3", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX4_3", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX6_3", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX14_3", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX36_3", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX43_3", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX46_3", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_FAN5_3", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX16_3", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX31_3", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B2_3", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_LOGIC_OUTS_B4_3", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B3_3", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX29_3", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_FAN4_3", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX3_3", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX5_3", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B23_3", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX45_3", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX41_3", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX12_3", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX42_3", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_FAN7_3", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B20_3", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX23_3", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_LOGIC_OUTS_B11_3", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_IMUX30_3", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX33_3", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX10_3", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX27_3", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX7_3", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX37_3", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX38_3", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX26_3", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_CLK1_3", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX17_3", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX21_3", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_LOGIC_OUTS_B6_3", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX18_3", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_FAN6_3", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_LOGIC_OUTS_B22_3", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B12_3", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX35_3", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_LOGIC_OUTS_B18_3", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX44_3", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX34_3", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX15_3", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX13_3", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP6_3", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX0_3", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX22_3", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX20_3", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_LOGIC_OUTS_B14_3", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_CLK0_3", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX24_3", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B7_3", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_FAN3_3", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX1_3", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_LOGIC_OUTS_B16_3", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B17_3", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B5_3", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_BYP1_3", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX28_3", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_LOGIC_OUTS_B1_3", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_3", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_BYP2_3", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_BYP4_3", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX8_3", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_LOGIC_OUTS_B15_3", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX19_3", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX11_3", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP7_3", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_FAN0_3", + "VBRK_EXT_FAN0" + ] + ], + "tile_types": [ + "GTX_CHANNEL_0", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "CLBLM_M_COUT_N", + "HCLK_CLB_COUT1_R" + ], + [ + "CLBLM_L_COUT_N", + "HCLK_CLB_COUT0_R" + ] + ], + "tile_types": [ + "CLBLM_R", + "HCLK_CLB" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "CLK_HROW_WW4A3_7", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_NE4BEG1_7", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_ER1BEG0_7", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_ER1BEG1_7", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_NE2A1_7", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_LH11_7", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH8_7", + "VBRK_LH8" + ], + [ + "CLK_HROW_LH9_7", + "VBRK_LH9" + ], + [ + "CLK_HROW_NE4C2_7", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_SW4A2_7", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_SW4END2_7", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_EE4B0_7", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WW4B3_7", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_EE4A1_7", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_SW2A0_7", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_SE4C1_7", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_EE4BEG1_7", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WW4B2_7", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_LH7_7", + "VBRK_LH7" + ], + [ + "CLK_HROW_SE2A0_7", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_WW4B1_7", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_EE4C0_7", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_EE4C2_7", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_WW4END2_7", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_EE2A2_7", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_NW4A3_7", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_EL1BEG0_7", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_WW2END3_7", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_EE2BEG1_7", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_SW2A1_7", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_NE4BEG0_7", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_EE2BEG0_7", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_LH1_7", + "VBRK_LH1" + ], + [ + "CLK_HROW_SE4C0_7", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_SE2A3_7", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_SE4C2_7", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_NE4C3_7", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_SW4END0_7", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_WL1END1_7", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_WW2END2_7", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_LH12_7", + "VBRK_LH12" + ], + [ + "CLK_HROW_WR1END2_7", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_NE4BEG2_7", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WL1END3_7", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_SE4BEG1_7", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_WW4A0_7", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_EE4A3_7", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_EL1BEG1_7", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_LH3_7", + "VBRK_LH3" + ], + [ + "CLK_HROW_WW4A1_7", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_NW4END2_7", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_WW4C3_7", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_EE4BEG2_7", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_WR1END1_7", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_EE2A1_7", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_WL1END0_7", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_NW2A1_7", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_NW4A1_7", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_WW4END3_7", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_NW2A0_7", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_LH4_7", + "VBRK_LH4" + ], + [ + "CLK_HROW_EL1BEG3_7", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_NW2A2_7", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_SW2A3_7", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_NW4A0_7", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_WW2A1_7", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_SE4BEG3_7", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_NE2A3_7", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_EE4BEG3_7", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_SE2A1_7", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_SW2A2_7", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_SE4C3_7", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_WR1END3_7", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_SW4A3_7", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_WW4C0_7", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_SE2A2_7", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_WW4A2_7", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_EE2BEG3_7", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_SE4BEG2_7", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_NW4A2_7", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_WW4C1_7", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_SW4END1_7", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_EE4B1_7", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_ER1BEG2_7", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_WW2END0_7", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_EE4A0_7", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_LH10_7", + "VBRK_LH10" + ], + [ + "CLK_HROW_SW4END3_7", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_NW4END0_7", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_EE4B2_7", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_SE4BEG0_7", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_NW4END1_7", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_EE2A0_7", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_ER1BEG3_7", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_LH5_7", + "VBRK_LH5" + ], + [ + "CLK_HROW_EE4C1_7", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WW4END1_7", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_NE2A2_7", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_EE2A3_7", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_EL1BEG2_7", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_NE4BEG3_7", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_WW4C2_7", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_NW2A3_7", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_NW4END3_7", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_WW2A2_7", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_WW2A0_7", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_EE4BEG0_7", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_NE4C0_7", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WW2A3_7", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_LH6_7", + "VBRK_LH6" + ], + [ + "CLK_HROW_WW4B0_7", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EE2BEG2_7", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_WL1END2_7", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_WR1END0_7", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_LH2_7", + "VBRK_LH2" + ], + [ + "CLK_HROW_SW4A0_7", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_EE4B3_7", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_NE2A0_7", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_NE4C1_7", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_SW4A1_7", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_WW2END1_7", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_EE4C3_7", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_EE4A2_7", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_WW4END0_7", + "VBRK_WW4END0" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "CFG_CENTER_IMUX2_9", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_EE4A0_9", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_WL1END3_9", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_EE4BEG1_9", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_EE4C2_9", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX10_9", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_ER1BEG3_9", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_WR1END2_9", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SE2A3_9", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SE4BEG0_9", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_NW2A3_9", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NE4C2_9", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_IMUX27_9", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_SW2A2_9", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_IMUX15_9", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_LH3_9", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_EE4B0_9", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_EE2BEG0_9", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_ER1BEG2_9", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_SW4END0_9", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_NW4A3_9", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SW2A1_9", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_SW4A3_9", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EE2A1_9", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_SW4END1_9", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_NW4END2_9", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_IMUX38_9", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_EE4A3_9", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX19_9", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_NE4BEG1_9", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX4_9", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_WW4C2_9", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_NW4A2_9", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_NE2A0_9", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX5_9", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_LH8_9", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_LH11_9", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_NW2A2_9", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_IMUX37_9", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_EL1BEG3_9", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_BYP1_9", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_LH1_9", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_IMUX34_9", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_IMUX45_9", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX42_9", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_EE4BEG2_9", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_SW4END2_9", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_BYP6_9", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_EE4A2_9", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX16_9", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX24_9", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_IMUX46_9", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW4C1_9", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_IMUX41_9", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX26_9", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_LH6_9", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_SW2A3_9", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_EE4BEG3_9", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX28_9", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_FAN3_9", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_BYP4_9", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_CTRL1_9", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_WR1END3_9", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_SE2A0_9", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_FAN7_9", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_NW4A0_9", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_EL1BEG1_9", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_EL1BEG0_9", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_IMUX35_9", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_WW2A0_9", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_WW2END1_9", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_WL1END1_9", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_CLK1_9", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX18_9", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX3_9", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_SE4C1_9", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_EE4BEG0_9", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_FAN2_9", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_EE4B1_9", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_BYP7_9", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_IMUX32_9", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_WW4B0_9", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_IMUX9_9", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_NW2A0_9", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_BYP2_9", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_WW4END3_9", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_CTRL0_9", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_SE4C2_9", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WW4B3_9", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_IMUX17_9", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX33_9", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_SW2A0_9", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_WW4A2_9", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_LH4_9", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_WR1END0_9", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EE2A3_9", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_IMUX11_9", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_NE4C0_9", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_WW4A0_9", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_SE4BEG1_9", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE2A0_9", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_NE2A2_9", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE4A1_9", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_EE4C3_9", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_NE4BEG0_9", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_LH2_9", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_NE4BEG2_9", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW2END2_9", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_9", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_NW4A1_9", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SE4C3_9", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_SE4BEG3_9", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX25_9", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_WL1END2_9", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_FAN0_9", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_LH12_9", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX0_9", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW2A1_9", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_IMUX29_9", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX43_9", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_EL1BEG2_9", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NE4C3_9", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_WW4B1_9", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_EE4B2_9", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX21_9", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_NW2A1_9", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_WL1END0_9", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_9", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_IMUX20_9", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_IMUX14_9", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_IMUX12_9", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_WW4END0_9", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_NW4END3_9", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_WW4A3_9", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW4A1_9", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_IMUX13_9", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_FAN4_9", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW4B2_9", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_NW4END1_9", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_EE2A2_9", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_CLK0_9", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX36_9", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW4A2_9", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_IMUX39_9", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_LH5_9", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_WR1END1_9", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_IMUX22_9", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_SW4A1_9", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_FAN1_9", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_NE2A1_9", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX31_9", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_WW2A2_9", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_WW4C3_9", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_LH10_9", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_NW4END0_9", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_WW2A3_9", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_NE4BEG3_9", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_9", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_FAN5_9", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_IMUX8_9", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW4END1_9", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX40_9", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_BYP5_9", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_NE4C1_9", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_WW4END2_9", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_9", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_EE4C0_9", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_SE4BEG2_9", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_BYP0_9", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX7_9", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_EE4B3_9", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_LH9_9", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_SW4END3_9", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_LH7_9", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_BYP3_9", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_WW2END0_9", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_IMUX23_9", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW4C0_9", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_ER1BEG1_9", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SE2A2_9", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_EE2BEG3_9", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_SE2A1_9", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_WW2END3_9", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_EE4C1_9", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX1_9", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_NE2A3_9", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_FAN6_9", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX44_9", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_ER1BEG0_9", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_EE2BEG1_9", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_SW4A0_9", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_SE4C0_9", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_EE2BEG2_9", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX47_9", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX30_9", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_IMUX6_9", + "VFRAME_IMUX6" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX15_8", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX45_8", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX12_8", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B4_8", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B2_8", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_FAN2_8", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_LOGIC_OUTS_B0_8", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_BYP5_8", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX39_8", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX40_8", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B9_8", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX16_8", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX0_8", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX13_8", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX14_8", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX10_8", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX20_8", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX38_8", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_FAN5_8", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX46_8", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP6_8", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX2_8", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_LOGIC_OUTS_B10_8", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX5_8", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX19_8", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX41_8", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B15_8", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_LOGIC_OUTS_B7_8", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B20_8", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_FAN6_8", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX23_8", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX44_8", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_LOGIC_OUTS_B6_8", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX28_8", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX22_8", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX47_8", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX21_8", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX1_8", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX27_8", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_FAN0_8", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX9_8", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_BYP7_8", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B8_8", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_FAN1_8", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX18_8", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_BYP3_8", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B11_8", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_LOGIC_OUTS_B22_8", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B23_8", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX8_8", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX4_8", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_CLK1_8", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX24_8", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B1_8", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX7_8", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX31_8", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX6_8", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B18_8", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX32_8", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B16_8", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_FAN7_8", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX30_8", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX34_8", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX26_8", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_LOGIC_OUTS_B21_8", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_CLK0_8", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX17_8", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX35_8", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_LOGIC_OUTS_B13_8", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_BYP4_8", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_LOGIC_OUTS_B19_8", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX11_8", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP0_8", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX36_8", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX25_8", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B3_8", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX29_8", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_CTRL1_8", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX43_8", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_BYP2_8", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX33_8", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_CTRL0_8", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX42_8", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_FAN3_8", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_LOGIC_OUTS_B14_8", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_LOGIC_OUTS_B17_8", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B5_8", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX3_8", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX37_8", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_BYP1_8", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B12_8", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_FAN4_8", + "VBRK_EXT_FAN4" + ] + ], + "tile_types": [ + "GTX_CHANNEL_1", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 0, + -5 + ], + "wire_pairs": [ + [ + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" + ], + [ + "BRAM_FIFO36_CASCADEOUTA_1", + "HCLK_BRAM_CASCADEA_R" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" + ], + [ + "BRAM_FIFO36_CASCADEOUTB_1", + "HCLK_BRAM_CASCADEB_R" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" + ] + ], + "tile_types": [ + "BRAM_R", + "HCLK_BRAM" + ] + }, + { + "grid_deltas": [ + 1, + 4 + ], + "wire_pairs": [ + [ + "CLK_HROW_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_SW4A1_0", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_MONITOR_P_0", + "VBRK_MONITOR_P" + ], + [ + "CLK_HROW_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_LH4_0", + "VBRK_LH4" + ], + [ + "CLK_HROW_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_LH11_0", + "VBRK_LH11" + ], + [ + "CLK_HROW_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_MONITOR_N_0", + "VBRK_MONITOR_N" + ], + [ + "CLK_HROW_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_LH6_0", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_LH1_0", + "VBRK_LH1" + ], + [ + "CLK_HROW_LH10_0", + "VBRK_LH10" + ], + [ + "CLK_HROW_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_LH5_0", + "VBRK_LH5" + ], + [ + "CLK_HROW_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_LH8_0", + "VBRK_LH8" + ], + [ + "CLK_HROW_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_LH2_0", + "VBRK_LH2" + ], + [ + "CLK_HROW_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_LH12_0", + "VBRK_LH12" + ], + [ + "CLK_HROW_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_LH3_0", + "VBRK_LH3" + ], + [ + "CLK_HROW_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_LH7_0", + "VBRK_LH7" + ], + [ + "CLK_HROW_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_LH9_0", + "VBRK_LH9" + ], + [ + "CLK_HROW_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_WW4C2_0", + "VBRK_WW4C2" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "CMT_FIFO_NW2A3_5", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_EE2BEG3_5", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_5", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "CMT_FIFO_EE2A1_5", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_L_IMUX23_5", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_EE4A2_5", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_5", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "CMT_FIFO_NW4A1_5", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_LH7_5", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_5", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "CMT_FIFO_SW2A0_5", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_L_IMUX8_5", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_ER1BEG3_5", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_EE4BEG2_5", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_EE4C1_5", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_L_IMUX42_5", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_SE4BEG0_5", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_5", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CMT_FIFO_SE4BEG1_5", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_NE2A3_5", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_SW4END2_5", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_NE2A2_5", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_L_IMUX30_5", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_EL1BEG2_5", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_L_IMUX33_5", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_LH4_5", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_L_IMUX21_5", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_5", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "CMT_FIFO_NW4END1_5", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_SE4BEG3_5", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_L_FAN1_5", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_NE4BEG0_5", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_NE4C3_5", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_5", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CMT_FIFO_L_FAN7_5", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_L_IMUX14_5", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_EL1BEG0_5", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_L_IMUX2_5", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_SW4A0_5", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_SE4C0_5", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_EE4BEG3_5", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_EE4A0_5", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_L_IMUX19_5", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_5", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CMT_FIFO_L_CLK1_5", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_LH1_5", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_SW4A1_5", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_L_FAN5_5", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_WW4C1_5", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_SE4BEG2_5", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_L_BYP2_5", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_L_FAN4_5", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_5", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CMT_FIFO_WW4END2_5", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_WW4B2_5", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_EE4BEG1_5", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_WW2A2_5", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_5", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CMT_FIFO_WW2END2_5", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_L_IMUX40_5", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_WW4C2_5", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_ER1BEG1_5", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_NW2A2_5", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_WR1END1_5", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_WW4A2_5", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_LH8_5", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_IMUX16_5", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_WW4C3_5", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_L_IMUX4_5", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_WR1END3_5", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_WW2END0_5", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_SE4C1_5", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_SW4END1_5", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_LH3_5", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_EE4A3_5", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_SE4C2_5", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_EE4BEG0_5", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX41_5", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_IMUX7_5", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_5", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "CMT_FIFO_LH12_5", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_WW4END0_5", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_ER1BEG0_5", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_WW4A0_5", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_WW4B0_5", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_5", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CMT_FIFO_WW4A3_5", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_LH10_5", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_WW4C0_5", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_SW4A3_5", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_L_IMUX27_5", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_WR1END0_5", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_NW2A0_5", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_L_IMUX6_5", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_EL1BEG1_5", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_LH5_5", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_L_IMUX0_5", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_EE2BEG0_5", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_IMUX26_5", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_WW4B1_5", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_L_IMUX32_5", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_L_BYP1_5", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_L_FAN0_5", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_EE4B3_5", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_NE2A1_5", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_EE4C0_5", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_EL1BEG3_5", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_SE2A1_5", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_L_IMUX44_5", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_L_IMUX24_5", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_WW2A1_5", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_WW2END3_5", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_5", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "CMT_FIFO_L_IMUX12_5", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_L_CTRL0_5", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_EE4B0_5", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_L_IMUX25_5", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_SW4END0_5", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_SE2A3_5", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_SE4C3_5", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_5", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CMT_FIFO_L_FAN3_5", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_EE4C2_5", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_L_BYP0_5", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_L_IMUX1_5", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_SW2A1_5", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_L_IMUX15_5", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_FAN6_5", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_L_IMUX39_5", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_L_BYP4_5", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_L_IMUX20_5", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_SW2A3_5", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_EE2BEG2_5", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_NW4END2_5", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_5", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CMT_FIFO_L_IMUX13_5", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_5", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CMT_FIFO_NW4END0_5", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_L_IMUX34_5", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_5", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CMT_FIFO_NW4A3_5", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_NW4A2_5", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_L_IMUX9_5", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX38_5", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_LH11_5", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_EE2BEG1_5", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_5", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "CMT_FIFO_NW4A0_5", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_SE2A2_5", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_LH9_5", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_L_IMUX31_5", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_5", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "CMT_FIFO_WW4END3_5", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_WW4B3_5", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_LH6_5", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_5", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CMT_FIFO_EE4C3_5", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_L_BYP6_5", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_L_IMUX47_5", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_NE4BEG1_5", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_BYP7_5", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_L_BYP3_5", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_SW2A2_5", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_5", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "CMT_FIFO_NE4BEG3_5", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_NE4BEG2_5", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_L_CLK0_5", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_SW4A2_5", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_WW2A3_5", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_NE4C0_5", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_EE2A3_5", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_EE4A1_5", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_L_FAN2_5", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_WW2END1_5", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_5", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_5", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CMT_FIFO_L_CTRL1_5", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_NE4C1_5", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_SE2A0_5", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_EE4B2_5", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_ER1BEG2_5", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_WL1END3_5", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_WL1END2_5", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_WW4END1_5", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_NE2A0_5", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_IMUX37_5", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_SW4END3_5", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_EE2A2_5", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_WL1END0_5", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_IMUX29_5", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_LH2_5", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_L_IMUX3_5", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_EE2A0_5", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_IMUX43_5", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_NE4C2_5", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_WR1END2_5", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_L_IMUX28_5", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_L_IMUX45_5", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_L_IMUX18_5", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_L_BYP5_5", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_L_IMUX11_5", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_WW2A0_5", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_L_IMUX5_5", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_WW4A1_5", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_L_IMUX17_5", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_WL1END1_5", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_L_IMUX46_5", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_NW4END3_5", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_L_IMUX36_5", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_5", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "CMT_FIFO_NW2A1_5", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_L_IMUX35_5", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_EE4B1_5", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_L_IMUX10_5", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_L_IMUX22_5", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_5", + "INT_INTERFACE_LOGIC_OUTS_B13" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 6 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_6" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_6" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_6" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_6" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_6" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_6" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_6" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_6" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_6" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_6" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_6" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_6" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_6" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_6" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_6" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_6" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_6" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_6" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_6" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_6" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_6" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_6" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_6" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_6" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_6" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_6" + ], + [ + "INT_FEEDTHRU_2_MONITOR_P", + "MONITOR_HORIZ_VAUXP9" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_6" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_6" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_6" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_6" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_6" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_6" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_6" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_6" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_6" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_6" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_6" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_6" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_6" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_6" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_6" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_6" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_6" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_6" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_6" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_6" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_6" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_6" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_6" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_6" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_6" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_6" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_6" + ], + [ + "INT_FEEDTHRU_2_MONITOR_N", + "MONITOR_HORIZ_VAUXN9" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_6" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_6" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_6" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_6" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_6" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_6" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_6" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_6" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_6" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_6" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_6" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_6" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_6" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_6" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_6" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_6" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_6" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_6" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_6" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_6" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_6" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_6" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_6" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_6" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_6" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_6" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_6" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_6" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_6" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_6" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_6" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_6" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_6" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_6" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_6" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_6" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_6" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_6" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_6" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_6" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_6" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_6" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_6" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_6" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_6" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_6" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_6" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_6" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_6" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_6" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_6" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_6" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_6" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_6" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_6" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_6" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_6" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_6" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_6" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_6" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_6" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_6" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_6" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_6" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_6" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_6" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_6" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_6" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_6" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_6" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_6" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_MID_FUJI2" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "CMT_TOP_LH12_7", + "VBRK_LH12" + ], + [ + "CMT_TOP_SW4END1_7", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_7", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE4C2_7", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_ER1BEG3_7", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END1_7", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WL1END2_7", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_NW4A0_7", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WR1END2_7", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW4A2_7", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG3_7", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EL1BEG0_7", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH11_7", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW2END2_7", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4A1_7", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NE2A1_7", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SW2A2_7", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_ER1BEG0_7", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_7", + "VBRK_LH1" + ], + [ + "CMT_TOP_SW4A3_7", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH10_7", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4BEG3_7", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C3_7", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4END3_7", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_ER1BEG1_7", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_7", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW2END0_7", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END2_7", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NE4C0_7", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EL1BEG1_7", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4END0_7", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EE2BEG3_7", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4C1_7", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A2_7", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_7", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE2A3_7", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4A1_7", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_LH2_7", + "VBRK_LH2" + ], + [ + "CMT_TOP_EL1BEG2_7", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WL1END0_7", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4C1_7", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW2END1_7", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2BEG0_7", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4B0_7", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C2_7", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A0_7", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_7", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_EE4B2_7", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG2_7", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A0_7", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG0_7", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW4A1_7", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_SE2A1_7", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4END2_7", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE2A3_7", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW4C0_7", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_7", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE4BEG2_7", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_SE4C0_7", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_ER1BEG2_7", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NE2A0_7", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4A3_7", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4BEG2_7", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_7", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4B3_7", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END3_7", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WW4C1_7", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WL1END3_7", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH9_7", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2A0_7", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG1_7", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_7", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_LH3_7", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_7", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE4BEG1_7", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EE4A2_7", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG0_7", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE4BEG2_7", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW4END3_7", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NE4BEG1_7", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A2_7", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NW4END0_7", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_7", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4A0_7", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END0_7", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_7", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW4END1_7", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH7_7", + "VBRK_LH7" + ], + [ + "CMT_TOP_SE4BEG1_7", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE4A3_7", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C2_7", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A3_7", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW2A1_7", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C3_7", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE2A2_7", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NE4C3_7", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE4C0_7", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WR1END1_7", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NW4END3_7", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_WW4B1_7", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C1_7", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_7", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE2A1_7", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_7", + "VBRK_LH5" + ], + [ + "CMT_TOP_SE4C2_7", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B0_7", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE2A0_7", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW4A1_7", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SW2A0_7", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW2A3_7", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW2A0_7", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_7", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EL1BEG3_7", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_NW4A2_7", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG3_7", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NW2A3_7", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW4C3_7", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_7", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_LH4_7", + "VBRK_LH4" + ], + [ + "CMT_TOP_LH8_7", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B3_7", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NE2A2_7", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4BEG0_7", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2A3_7", + "VBRK_EE2A3" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CLK_PMV_WW4B0_1", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_PMV_BYP4_1", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_PMV_SW2A1_1", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_PMV_BYP1_1", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_PMV_NE4C1_1", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_PMV_WR1END2_1", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_PMV_IMUX1_1", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_PMV_SW2A2_1", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_PMV_LH12_1", + "INT_INTERFACE_LH12" + ], + [ + "CLK_PMV_SW4A2_1", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_PMV_WL1END2_1", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_PMV_IMUX14_1", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_PMV_EE4B2_1", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_PMV_IMUX41_1", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_PMV_IMUX8_1", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_PMV_EE4A0_1", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_PMV_SW4A3_1", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_PMV_EE4C0_1", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_PMV_IMUX39_1", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_PMV_IMUX46_1", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_PMV_NE2A1_1", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_PMV_EE2BEG2_1", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_PMV_WL1END3_1", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_PMV_LH8_1", + "INT_INTERFACE_LH8" + ], + [ + "CLK_PMV_NE2A0_1", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_PMV_SW4END1_1", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_PMV_EE2A3_1", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_PMV_IMUX27_1", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_PMV_EE2BEG0_1", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_PMV_WW4END2_1", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_PMV_SE4BEG3_1", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_PMV_IMUX4_1", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_PMV_NW4END2_1", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_PMV_IMUX17_1", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_PMV_WW4A1_1", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_PMV_SW4END0_1", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_PMV_CTRL0_1", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_PMV_WW4C0_1", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_PMV_NE4BEG1_1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_PMV_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_PMV_IMUX26_1", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_PMV_EL1BEG2_1", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_PMV_IMUX19_1", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_PMV_BYP6_1", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_PMV_EE2A0_1", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_PMV_IMUX37_1", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_PMV_LH10_1", + "INT_INTERFACE_LH10" + ], + [ + "CLK_PMV_BYP2_1", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_PMV_EE4BEG1_1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_PMV_SE2A3_1", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_PMV_NW4END3_1", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_PMV_IMUX7_1", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_PMV_NE4BEG3_1", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_PMV_NE4C3_1", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_PMV_LH3_1", + "INT_INTERFACE_LH3" + ], + [ + "CLK_PMV_IMUX6_1", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_PMV_FAN3_1", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_PMV_EE4A3_1", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_PMV_NW4A3_1", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_PMV_EE2A2_1", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_PMV_IMUX0_1", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_PMV_WL1END1_1", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_PMV_WW2END2_1", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_PMV_SE4BEG1_1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_PMV_CLK1_1", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_PMV_IMUX40_1", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_PMV_EE4C3_1", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_PMV_FAN4_1", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_PMV_WR1END1_1", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_PMV_SE4BEG2_1", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_PMV_EE4A2_1", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_PMV_WW4C3_1", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_PMV_WW2A3_1", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_PMV_WR1END3_1", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_PMV_SW4END3_1", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_PMV_NE4C2_1", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_PMV_IMUX24_1", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_PMV_EE4BEG3_1", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_PMV_NE2A2_1", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_PMV_BYP7_1", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_PMV_EE2BEG3_1", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_PMV_NW2A2_1", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_PMV_IMUX28_1", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_PMV_WW4B1_1", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_PMV_CLK0_1", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_PMV_FAN6_1", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_PMV_IMUX25_1", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_PMV_NW4A1_1", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_PMV_EE4B1_1", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_PMV_WW4C2_1", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_PMV_EE2A1_1", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_PMV_SE4C0_1", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_PMV_NE2A3_1", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_PMV_NW4END0_1", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_PMV_IMUX45_1", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_PMV_LH4_1", + "INT_INTERFACE_LH4" + ], + [ + "CLK_PMV_EE4B0_1", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_PMV_IMUX18_1", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_PMV_SW4A0_1", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_PMV_WW4C1_1", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_PMV_IMUX21_1", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_PMV_LH5_1", + "INT_INTERFACE_LH5" + ], + [ + "CLK_PMV_SE2A0_1", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_PMV_FAN7_1", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_PMV_WW4END0_1", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_PMV_WW2A0_1", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_PMV_IMUX22_1", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_PMV_WW2END1_1", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_PMV_EE4C1_1", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_PMV_IMUX30_1", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_PMV_SE4C1_1", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_PMV_EE4C2_1", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_PMV_IMUX42_1", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_PMV_IMUX11_1", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_PMV_IMUX12_1", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_PMV_EL1BEG0_1", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_PMV_IMUX29_1", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_PMV_NW2A1_1", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_PMV_ER1BEG3_1", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_PMV_LH7_1", + "INT_INTERFACE_LH7" + ], + [ + "CLK_PMV_IMUX43_1", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_PMV_LH6_1", + "INT_INTERFACE_LH6" + ], + [ + "CLK_PMV_NE4BEG2_1", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_PMV_NE4BEG0_1", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_PMV_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_PMV_SE2A2_1", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_PMV_SW2A3_1", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_PMV_IMUX38_1", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_PMV_LH2_1", + "INT_INTERFACE_LH2" + ], + [ + "CLK_PMV_WW4A3_1", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_PMV_WL1END0_1", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_PMV_WW4B2_1", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_PMV_WR1END0_1", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_PMV_EE4BEG0_1", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_PMV_FAN1_1", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_PMV_WW2END3_1", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_PMV_BYP0_1", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_PMV_SE4C2_1", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_PMV_ER1BEG0_1", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_PMV_BYP3_1", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_PMV_NE4C0_1", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_PMV_IMUX34_1", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_PMV_NW2A0_1", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_PMV_IMUX31_1", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_PMV_IMUX36_1", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_PMV_IMUX2_1", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_PMV_IMUX15_1", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_PMV_LH11_1", + "INT_INTERFACE_LH11" + ], + [ + "CLK_PMV_EE2BEG1_1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_PMV_IMUX16_1", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_PMV_EE4B3_1", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_PMV_SE4C3_1", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_PMV_SW2A0_1", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_PMV_EE4A1_1", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_PMV_IMUX47_1", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_PMV_IMUX13_1", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_PMV_SW4END2_1", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_PMV_ER1BEG2_1", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_PMV_SW4A1_1", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_PMV_IMUX33_1", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_PMV_IMUX10_1", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_PMV_WW4A0_1", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_PMV_IMUX9_1", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_PMV_SE4BEG0_1", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_PMV_NW2A3_1", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_PMV_ER1BEG1_1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_PMV_WW2END0_1", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_PMV_IMUX32_1", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_PMV_LH9_1", + "INT_INTERFACE_LH9" + ], + [ + "CLK_PMV_WW4A2_1", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_PMV_NW4A0_1", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_PMV_IMUX3_1", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_PMV_BYP5_1", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_PMV_LH1_1", + "INT_INTERFACE_LH1" + ], + [ + "CLK_PMV_IMUX5_1", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_PMV_WW4END1_1", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_PMV_NW4A2_1", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_PMV_FAN5_1", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_PMV_IMUX20_1", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_PMV_FAN0_1", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_PMV_WW4END3_1", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_PMV_SE2A1_1", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_PMV_FAN2_1", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_PMV_CTRL1_1", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_PMV_EL1BEG1_1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_PMV_IMUX44_1", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_PMV_EE4BEG2_1", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_PMV_IMUX35_1", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_PMV_IMUX23_1", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_PMV_EL1BEG3_1", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_PMV_WW4B3_1", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_PMV_NW4END1_1", + "INT_INTERFACE_NW4END1" + ] + ], + "tile_types": [ + "CLK_PMV", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "wire_pairs": [ + [ + "IOI_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2_1" + ], + [ + "IOI_IMUX_RC0", + "IOI_IMUX_RC2" + ], + [ + "IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_LEAF_GCLK3" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_LEAF_GCLK1" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_LEAF_GCLK0" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_RCLK_FORIO1" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_RCLK_FORIO0" + ], + [ + "IOI_TBYTEIN", + "IOI_TBYTEIN" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_RCLK_FORIO3" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_RCLK_FORIO2" + ], + [ + "IOI_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3_1" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_LEAF_GCLK5" + ], + [ + "IOI_IMUX_RC1", + "IOI_IMUX_RC3" + ], + [ + "LIOI_I2GCLK_BOT1", + "LIOI_I2GCLK_TOP0" + ], + [ + "IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "LIOI_I2GCLK_TOP0", + "LIOI_I2GCLK_TOP1" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_LEAF_GCLK4" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_LEAF_GCLK2" + ] + ], + "tile_types": [ + "LIOI3", + "LIOI3" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "CLBLL_LL_COUT_N", + "HCLK_CLB_COUT1_R" + ], + [ + "CLBLL_L_COUT_N", + "HCLK_CLB_COUT0_R" + ] + ], + "tile_types": [ + "CLBLL_R", + "HCLK_CLB" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX23_10", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_BYP6_10", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_CLK0_10", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_LOGIC_OUTS_B19_10", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX7_10", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX12_10", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX28_10", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX18_10", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_FAN0_10", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_FAN6_10", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX31_10", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B8_10", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_BYP2_10", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX36_10", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX42_10", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX45_10", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX22_10", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B2_10", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_LOGIC_OUTS_B0_10", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX21_10", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX14_10", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX9_10", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX3_10", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_LOGIC_OUTS_B17_10", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX33_10", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_LOGIC_OUTS_B10_10", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX17_10", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_LOGIC_OUTS_B12_10", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX15_10", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX24_10", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B7_10", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_IMUX44_10", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_FAN3_10", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_BYP3_10", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX8_10", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_BYP7_10", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B23_10", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX38_10", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX19_10", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_BYP1_10", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX29_10", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX10_10", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_FAN7_10", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B16_10", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX46_10", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_LOGIC_OUTS_B15_10", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX0_10", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX11_10", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX4_10", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_BYP0_10", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX26_10", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX40_10", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_FAN2_10", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX43_10", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_CTRL0_10", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX5_10", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX41_10", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX13_10", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_FAN5_10", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_FAN4_10", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_LOGIC_OUTS_B18_10", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX27_10", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_BYP4_10", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_CTRL1_10", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX1_10", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX30_10", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_LOGIC_OUTS_B4_10", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B20_10", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX20_10", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX47_10", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX2_10", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_LOGIC_OUTS_B9_10", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_LOGIC_OUTS_B5_10", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_FAN1_10", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX35_10", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_CLK1_10", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX16_10", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_LOGIC_OUTS_B14_10", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_LOGIC_OUTS_B1_10", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX37_10", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_LOGIC_OUTS_B13_10", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B22_10", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX32_10", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX25_10", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_BYP5_10", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B3_10", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX34_10", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_LOGIC_OUTS_B6_10", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX6_10", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX39_10", + "VBRK_EXT_IMUX39" + ] + ], + "tile_types": [ + "GTX_CHANNEL_1", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW2A2_5", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A0_5", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END2_5", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SE4C1_5", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SW4END3_5", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NW4END0_5", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW2A0_5", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WL1END3_5", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SE2A2_5", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4B3_5", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE2A2_5", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_5", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_LH3_5", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE4C2_5", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2A0_5", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG1_5", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A1_5", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4A2_5", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END1_5", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW4C0_5", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_5", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4END3_5", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4BEG0_5", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_EL1BEG1_5", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH6_5", + "VBRK_LH6" + ], + [ + "CMT_TOP_EE4A1_5", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_MONITOR_N_5", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW4A2_5", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4A3_5", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NE4BEG0_5", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW2A2_5", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C3_5", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH7_5", + "VBRK_LH7" + ], + [ + "CMT_TOP_WW4B2_5", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH5_5", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4A1_5", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4A0_5", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C1_5", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW2A0_5", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WL1END2_5", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_SE4C0_5", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SW4END2_5", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END1_5", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG0_5", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_WR1END1_5", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EE4C1_5", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG0_5", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NW4END2_5", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_EE2BEG2_5", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4B1_5", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_ER1BEG3_5", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NW2A1_5", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B0_5", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END2_5", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A1_5", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE2A3_5", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_LH11_5", + "VBRK_LH11" + ], + [ + "CMT_TOP_WL1END0_5", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SW4END0_5", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4BEG3_5", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C3_5", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_SE4BEG1_5", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NE2A2_5", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B0_5", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_ER1BEG2_5", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_5", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NE2A0_5", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4BEG1_5", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE2A3_5", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG2_5", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_LH9_5", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4END2_5", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4BEG2_5", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2END0_5", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_ER1BEG0_5", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE2A1_5", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH4_5", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2BEG1_5", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_NE4BEG3_5", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C0_5", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_MONITOR_P_5", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_LH8_5", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4A3_5", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2BEG0_5", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_NE2A1_5", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C3_5", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WL1END1_5", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW4A1_5", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_5", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4A0_5", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4END1_5", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH2_5", + "VBRK_LH2" + ], + [ + "CMT_TOP_NE2A3_5", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW4A0_5", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4A3_5", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4C0_5", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_LH12_5", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH1_5", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_5", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_ER1BEG1_5", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2BEG3_5", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH10_5", + "VBRK_LH10" + ], + [ + "CMT_TOP_SW2A2_5", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WR1END3_5", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NW4END1_5", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NW4A1_5", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WW4C2_5", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WR1END0_5", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4END3_5", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW4A3_5", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW2A3_5", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4END0_5", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4C2_5", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG3_5", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW2A3_5", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4A2_5", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4BEG3_5", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE4B2_5", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW2A0_5", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SE2A0_5", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SE4BEG2_5", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B1_5", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4C1_5", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C2_5", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4C3_5", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_EL1BEG2_5", + "VBRK_EL1BEG2" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH3_4", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH4_4", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH12_4", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH11_4", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH9_4", + "VBRK_LH9" + ], + [ + "CMT_TOP_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH1_4", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_MONITOR_N_4", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_LH10_4", + "VBRK_LH10" + ], + [ + "CMT_TOP_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH2_4", + "VBRK_LH2" + ], + [ + "CMT_TOP_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_MONITOR_P_4", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_LH8_4", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH7_4", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_4", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH6_4", + "VBRK_LH6" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -9 + ], + "wire_pairs": [ + [ + "BRKH_CMT_FREQ_REF_NS2", + "MMCM_CLK_FREQ_BB_REBUF2_NS" + ], + [ + "BRKH_CMT_FREQ_REF_NS0", + "MMCM_CLK_FREQ_BB_REBUF0_NS" + ], + [ + "BRKH_CMT_FREQ_REF_NS1", + "MMCM_CLK_FREQ_BB_REBUF1_NS" + ], + [ + "BRKH_CMT_PHASEREF_BELOW0", + "CMT_MMCM_PHASERREF_BELOW0" + ], + [ + "BRKH_CMT_PHASEREF1", + "CMT_MMCM_PHASERREF1" + ], + [ + "BRKH_CMT_PHYCTRL_SYNC_BB", + "CMT_MMCM_PHYCTRL_SYNC_BB_DN" + ], + [ + "BRKH_CMT_PHASEREF_BELOW1", + "CMT_MMCM_PHASERREF_BELOW1" + ], + [ + "BRKH_CMT_FREQ_REF_NS3", + "MMCM_CLK_FREQ_BB_REBUF3_NS" + ], + [ + "BRKH_CMT_PHASEREF0", + "CMT_MMCM_PHASERREF0" + ] + ], + "tile_types": [ + "BRKH_CMT", + "CMT_TOP_L_LOWER_B" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "DSP_WW2END2_3", + "INT_INTERFACE_WW2END2" + ], + [ + "DSP_SE4C0_3", + "INT_INTERFACE_SE4C0" + ], + [ + "DSP_NE2A1_3", + "INT_INTERFACE_NE2A1" + ], + [ + "DSP_IMUX14_3", + "INT_INTERFACE_IMUX14" + ], + [ + "DSP_NE4C0_3", + "INT_INTERFACE_NE4C0" + ], + [ + "DSP_IMUX7_3", + "INT_INTERFACE_IMUX7" + ], + [ + "DSP_IMUX1_3", + "INT_INTERFACE_IMUX1" + ], + [ + "DSP_SW4END3_3", + "INT_INTERFACE_SW4END3" + ], + [ + "DSP_NW4END0_3", + "INT_INTERFACE_NW4END0" + ], + [ + "DSP_EE4BEG0_3", + "INT_INTERFACE_EE4BEG0" + ], + [ + "DSP_WR1END3_3", + "INT_INTERFACE_WR1END3" + ], + [ + "DSP_WL1END0_3", + "INT_INTERFACE_WL1END0" + ], + [ + "DSP_WW4C3_3", + "INT_INTERFACE_WW4C3" + ], + [ + "DSP_IMUX19_3", + "INT_INTERFACE_IMUX19" + ], + [ + "DSP_SW4A0_3", + "INT_INTERFACE_SW4A0" + ], + [ + "DSP_LOGIC_OUTS_B3_3", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "DSP_EE2A0_3", + "INT_INTERFACE_EE2A0" + ], + [ + "DSP_ER1BEG1_3", + "INT_INTERFACE_ER1BEG1" + ], + [ + "DSP_IMUX39_3", + "INT_INTERFACE_IMUX39" + ], + [ + "DSP_NE4BEG0_3", + "INT_INTERFACE_NE4BEG0" + ], + [ + "DSP_LH1_3", + "INT_INTERFACE_LH1" + ], + [ + "DSP_LOGIC_OUTS_B23_3", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "DSP_EL1BEG0_3", + "INT_INTERFACE_EL1BEG0" + ], + [ + "DSP_CTRL0_3", + "INT_INTERFACE_CTRL0" + ], + [ + "DSP_NE4C3_3", + "INT_INTERFACE_NE4C3" + ], + [ + "DSP_SW4A1_3", + "INT_INTERFACE_SW4A1" + ], + [ + "DSP_WW2END3_3", + "INT_INTERFACE_WW2END3" + ], + [ + "DSP_FAN4_3", + "INT_INTERFACE_FAN4" + ], + [ + "DSP_EL1BEG3_3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "DSP_WW2A1_3", + "INT_INTERFACE_WW2A1" + ], + [ + "DSP_SW2A3_3", + "INT_INTERFACE_SW2A3" + ], + [ + "DSP_LOGIC_OUTS_B21_3", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "DSP_NW4END3_3", + "INT_INTERFACE_NW4END3" + ], + [ + "DSP_EE2BEG2_3", + "INT_INTERFACE_EE2BEG2" + ], + [ + "DSP_EE4BEG2_3", + "INT_INTERFACE_EE4BEG2" + ], + [ + "DSP_EE4C0_3", + "INT_INTERFACE_EE4C0" + ], + [ + "DSP_WW4A2_3", + "INT_INTERFACE_WW4A2" + ], + [ + "DSP_WW2A3_3", + "INT_INTERFACE_WW2A3" + ], + [ + "DSP_NE2A3_3", + "INT_INTERFACE_NE2A3" + ], + [ + "DSP_LOGIC_OUTS_B0_3", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "DSP_SE2A2_3", + "INT_INTERFACE_SE2A2" + ], + [ + "DSP_EE4C1_3", + "INT_INTERFACE_EE4C1" + ], + [ + "DSP_LH8_3", + "INT_INTERFACE_LH8" + ], + [ + "DSP_NW2A2_3", + "INT_INTERFACE_NW2A2" + ], + [ + "DSP_SW4END2_3", + "INT_INTERFACE_SW4END2" + ], + [ + "DSP_IMUX4_3", + "INT_INTERFACE_IMUX4" + ], + [ + "DSP_IMUX23_3", + "INT_INTERFACE_IMUX23" + ], + [ + "DSP_NE4BEG1_3", + "INT_INTERFACE_NE4BEG1" + ], + [ + "DSP_IMUX6_3", + "INT_INTERFACE_IMUX6" + ], + [ + "DSP_FAN1_3", + "INT_INTERFACE_FAN1" + ], + [ + "DSP_LOGIC_OUTS_B15_3", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "DSP_MONITOR_N_3", + "INT_INTERFACE_MONITOR_N" + ], + [ + "DSP_NW4A2_3", + "INT_INTERFACE_NW4A2" + ], + [ + "DSP_ER1BEG3_3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "DSP_IMUX11_3", + "INT_INTERFACE_IMUX11" + ], + [ + "DSP_IMUX15_3", + "INT_INTERFACE_IMUX15" + ], + [ + "DSP_NW2A1_3", + "INT_INTERFACE_NW2A1" + ], + [ + "DSP_LOGIC_OUTS_B10_3", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "DSP_SE4BEG3_3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "DSP_SW2A2_3", + "INT_INTERFACE_SW2A2" + ], + [ + "DSP_BYP4_3", + "INT_INTERFACE_BYP4" + ], + [ + "DSP_FAN2_3", + "INT_INTERFACE_FAN2" + ], + [ + "DSP_EE2BEG0_3", + "INT_INTERFACE_EE2BEG0" + ], + [ + "DSP_WW4A3_3", + "INT_INTERFACE_WW4A3" + ], + [ + "DSP_LH10_3", + "INT_INTERFACE_LH10" + ], + [ + "DSP_EE4B0_3", + "INT_INTERFACE_EE4B0" + ], + [ + "DSP_NW4A1_3", + "INT_INTERFACE_NW4A1" + ], + [ + "DSP_BYP6_3", + "INT_INTERFACE_BYP6" + ], + [ + "DSP_IMUX37_3", + "INT_INTERFACE_IMUX37" + ], + [ + "DSP_NE2A0_3", + "INT_INTERFACE_NE2A0" + ], + [ + "DSP_WW4END2_3", + "INT_INTERFACE_WW4END2" + ], + [ + "DSP_IMUX30_3", + "INT_INTERFACE_IMUX30" + ], + [ + "DSP_EE4BEG3_3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "DSP_FAN6_3", + "INT_INTERFACE_FAN6" + ], + [ + "DSP_NE4C1_3", + "INT_INTERFACE_NE4C1" + ], + [ + "DSP_IMUX45_3", + "INT_INTERFACE_IMUX45" + ], + [ + "DSP_WW4B0_3", + "INT_INTERFACE_WW4B0" + ], + [ + "DSP_ER1BEG0_3", + "INT_INTERFACE_ER1BEG0" + ], + [ + "DSP_WW4END3_3", + "INT_INTERFACE_WW4END3" + ], + [ + "DSP_LOGIC_OUTS_B8_3", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "DSP_LH3_3", + "INT_INTERFACE_LH3" + ], + [ + "DSP_SE4BEG1_3", + "INT_INTERFACE_SE4BEG1" + ], + [ + "DSP_SE4C3_3", + "INT_INTERFACE_SE4C3" + ], + [ + "DSP_FAN3_3", + "INT_INTERFACE_FAN3" + ], + [ + "DSP_BYP0_3", + "INT_INTERFACE_BYP0" + ], + [ + "DSP_LH5_3", + "INT_INTERFACE_LH5" + ], + [ + "DSP_SE4C1_3", + "INT_INTERFACE_SE4C1" + ], + [ + "DSP_EE4A2_3", + "INT_INTERFACE_EE4A2" + ], + [ + "DSP_NE4C2_3", + "INT_INTERFACE_NE4C2" + ], + [ + "DSP_NW4A0_3", + "INT_INTERFACE_NW4A0" + ], + [ + "DSP_EE4C2_3", + "INT_INTERFACE_EE4C2" + ], + [ + "DSP_NW4END1_3", + "INT_INTERFACE_NW4END1" + ], + [ + "DSP_WW4B1_3", + "INT_INTERFACE_WW4B1" + ], + [ + "DSP_IMUX44_3", + "INT_INTERFACE_IMUX44" + ], + [ + "DSP_SE2A1_3", + "INT_INTERFACE_SE2A1" + ], + [ + "DSP_IMUX0_3", + "INT_INTERFACE_IMUX0" + ], + [ + "DSP_SW2A0_3", + "INT_INTERFACE_SW2A0" + ], + [ + "DSP_WW2A0_3", + "INT_INTERFACE_WW2A0" + ], + [ + "DSP_LH9_3", + "INT_INTERFACE_LH9" + ], + [ + "DSP_LOGIC_OUTS_B20_3", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "DSP_IMUX32_3", + "INT_INTERFACE_IMUX32" + ], + [ + "DSP_WR1END0_3", + "INT_INTERFACE_WR1END0" + ], + [ + "DSP_BYP2_3", + "INT_INTERFACE_BYP2" + ], + [ + "DSP_LOGIC_OUTS_B4_3", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "DSP_IMUX16_3", + "INT_INTERFACE_IMUX16" + ], + [ + "DSP_IMUX33_3", + "INT_INTERFACE_IMUX33" + ], + [ + "DSP_LH11_3", + "INT_INTERFACE_LH11" + ], + [ + "DSP_SE4BEG2_3", + "INT_INTERFACE_SE4BEG2" + ], + [ + "DSP_WW4C1_3", + "INT_INTERFACE_WW4C1" + ], + [ + "DSP_LOGIC_OUTS_B22_3", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "DSP_IMUX31_3", + "INT_INTERFACE_IMUX31" + ], + [ + "DSP_IMUX40_3", + "INT_INTERFACE_IMUX40" + ], + [ + "DSP_EE2BEG3_3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "DSP_LOGIC_OUTS_B19_3", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "DSP_IMUX46_3", + "INT_INTERFACE_IMUX46" + ], + [ + "DSP_EE4C3_3", + "INT_INTERFACE_EE4C3" + ], + [ + "DSP_SE4BEG0_3", + "INT_INTERFACE_SE4BEG0" + ], + [ + "DSP_IMUX35_3", + "INT_INTERFACE_IMUX35" + ], + [ + "DSP_WW4A0_3", + "INT_INTERFACE_WW4A0" + ], + [ + "DSP_EL1BEG2_3", + "INT_INTERFACE_EL1BEG2" + ], + [ + "DSP_CLK0_3", + "INT_INTERFACE_CLK0" + ], + [ + "DSP_WL1END3_3", + "INT_INTERFACE_WL1END3" + ], + [ + "DSP_NW4A3_3", + "INT_INTERFACE_NW4A3" + ], + [ + "DSP_WW2END1_3", + "INT_INTERFACE_WW2END1" + ], + [ + "DSP_WL1END1_3", + "INT_INTERFACE_WL1END1" + ], + [ + "DSP_LOGIC_OUTS_B6_3", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "DSP_SW2A1_3", + "INT_INTERFACE_SW2A1" + ], + [ + "DSP_MONITOR_P_3", + "INT_INTERFACE_MONITOR_P" + ], + [ + "DSP_BYP5_3", + "INT_INTERFACE_BYP5" + ], + [ + "DSP_IMUX12_3", + "INT_INTERFACE_IMUX12" + ], + [ + "DSP_SE2A0_3", + "INT_INTERFACE_SE2A0" + ], + [ + "DSP_LOGIC_OUTS_B5_3", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "DSP_IMUX2_3", + "INT_INTERFACE_IMUX2" + ], + [ + "DSP_IMUX10_3", + "INT_INTERFACE_IMUX10" + ], + [ + "DSP_WW4B3_3", + "INT_INTERFACE_WW4B3" + ], + [ + "DSP_LOGIC_OUTS_B7_3", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "DSP_IMUX43_3", + "INT_INTERFACE_IMUX43" + ], + [ + "DSP_BYP3_3", + "INT_INTERFACE_BYP3" + ], + [ + "DSP_LOGIC_OUTS_B17_3", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "DSP_LOGIC_OUTS_B18_3", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "DSP_SE4C2_3", + "INT_INTERFACE_SE4C2" + ], + [ + "DSP_IMUX5_3", + "INT_INTERFACE_IMUX5" + ], + [ + "DSP_EL1BEG1_3", + "INT_INTERFACE_EL1BEG1" + ], + [ + "DSP_IMUX36_3", + "INT_INTERFACE_IMUX36" + ], + [ + "DSP_EE2BEG1_3", + "INT_INTERFACE_EE2BEG1" + ], + [ + "DSP_BYP1_3", + "INT_INTERFACE_BYP1" + ], + [ + "DSP_FAN0_3", + "INT_INTERFACE_FAN0" + ], + [ + "DSP_WW4END0_3", + "INT_INTERFACE_WW4END0" + ], + [ + "DSP_NW2A3_3", + "INT_INTERFACE_NW2A3" + ], + [ + "DSP_SW4A3_3", + "INT_INTERFACE_SW4A3" + ], + [ + "DSP_WW2A2_3", + "INT_INTERFACE_WW2A2" + ], + [ + "DSP_WW4END1_3", + "INT_INTERFACE_WW4END1" + ], + [ + "DSP_LOGIC_OUTS_B1_3", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "DSP_NE4BEG2_3", + "INT_INTERFACE_NE4BEG2" + ], + [ + "DSP_IMUX28_3", + "INT_INTERFACE_IMUX28" + ], + [ + "DSP_LH4_3", + "INT_INTERFACE_LH4" + ], + [ + "DSP_LOGIC_OUTS_B16_3", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "DSP_LH2_3", + "INT_INTERFACE_LH2" + ], + [ + "DSP_EE2A3_3", + "INT_INTERFACE_EE2A3" + ], + [ + "DSP_IMUX3_3", + "INT_INTERFACE_IMUX3" + ], + [ + "DSP_WR1END1_3", + "INT_INTERFACE_WR1END1" + ], + [ + "DSP_IMUX26_3", + "INT_INTERFACE_IMUX26" + ], + [ + "DSP_IMUX22_3", + "INT_INTERFACE_IMUX22" + ], + [ + "DSP_SE2A3_3", + "INT_INTERFACE_SE2A3" + ], + [ + "DSP_LOGIC_OUTS_B2_3", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "DSP_FAN5_3", + "INT_INTERFACE_FAN5" + ], + [ + "DSP_WL1END2_3", + "INT_INTERFACE_WL1END2" + ], + [ + "DSP_CTRL1_3", + "INT_INTERFACE_CTRL1" + ], + [ + "DSP_IMUX27_3", + "INT_INTERFACE_IMUX27" + ], + [ + "DSP_LH7_3", + "INT_INTERFACE_LH7" + ], + [ + "DSP_EE4B2_3", + "INT_INTERFACE_EE4B2" + ], + [ + "DSP_EE4A3_3", + "INT_INTERFACE_EE4A3" + ], + [ + "DSP_IMUX17_3", + "INT_INTERFACE_IMUX17" + ], + [ + "DSP_EE4B3_3", + "INT_INTERFACE_EE4B3" + ], + [ + "DSP_FAN7_3", + "INT_INTERFACE_FAN7" + ], + [ + "DSP_SW4END1_3", + "INT_INTERFACE_SW4END1" + ], + [ + "DSP_SW4A2_3", + "INT_INTERFACE_SW4A2" + ], + [ + "DSP_IMUX29_3", + "INT_INTERFACE_IMUX29" + ], + [ + "DSP_CLK1_3", + "INT_INTERFACE_CLK1" + ], + [ + "DSP_IMUX8_3", + "INT_INTERFACE_IMUX8" + ], + [ + "DSP_NW4END2_3", + "INT_INTERFACE_NW4END2" + ], + [ + "DSP_WW4C0_3", + "INT_INTERFACE_WW4C0" + ], + [ + "DSP_LOGIC_OUTS_B11_3", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "DSP_WR1END2_3", + "INT_INTERFACE_WR1END2" + ], + [ + "DSP_SW4END0_3", + "INT_INTERFACE_SW4END0" + ], + [ + "DSP_EE4B1_3", + "INT_INTERFACE_EE4B1" + ], + [ + "DSP_IMUX20_3", + "INT_INTERFACE_IMUX20" + ], + [ + "DSP_IMUX21_3", + "INT_INTERFACE_IMUX21" + ], + [ + "DSP_NE2A2_3", + "INT_INTERFACE_NE2A2" + ], + [ + "DSP_IMUX42_3", + "INT_INTERFACE_IMUX42" + ], + [ + "DSP_IMUX34_3", + "INT_INTERFACE_IMUX34" + ], + [ + "DSP_LOGIC_OUTS_B14_3", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "DSP_LH12_3", + "INT_INTERFACE_LH12" + ], + [ + "DSP_IMUX13_3", + "INT_INTERFACE_IMUX13" + ], + [ + "DSP_WW4C2_3", + "INT_INTERFACE_WW4C2" + ], + [ + "DSP_WW4A1_3", + "INT_INTERFACE_WW4A1" + ], + [ + "DSP_EE4BEG1_3", + "INT_INTERFACE_EE4BEG1" + ], + [ + "DSP_ER1BEG2_3", + "INT_INTERFACE_ER1BEG2" + ], + [ + "DSP_IMUX41_3", + "INT_INTERFACE_IMUX41" + ], + [ + "DSP_WW2END0_3", + "INT_INTERFACE_WW2END0" + ], + [ + "DSP_IMUX24_3", + "INT_INTERFACE_IMUX24" + ], + [ + "DSP_LH6_3", + "INT_INTERFACE_LH6" + ], + [ + "DSP_EE4A0_3", + "INT_INTERFACE_EE4A0" + ], + [ + "DSP_IMUX25_3", + "INT_INTERFACE_IMUX25" + ], + [ + "DSP_EE4A1_3", + "INT_INTERFACE_EE4A1" + ], + [ + "DSP_NW2A0_3", + "INT_INTERFACE_NW2A0" + ], + [ + "DSP_IMUX47_3", + "INT_INTERFACE_IMUX47" + ], + [ + "DSP_IMUX38_3", + "INT_INTERFACE_IMUX38" + ], + [ + "DSP_IMUX18_3", + "INT_INTERFACE_IMUX18" + ], + [ + "DSP_IMUX9_3", + "INT_INTERFACE_IMUX9" + ], + [ + "DSP_NE4BEG3_3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "DSP_BYP7_3", + "INT_INTERFACE_BYP7" + ], + [ + "DSP_EE2A2_3", + "INT_INTERFACE_EE2A2" + ], + [ + "DSP_WW4B2_3", + "INT_INTERFACE_WW4B2" + ], + [ + "DSP_EE2A1_3", + "INT_INTERFACE_EE2A1" + ] + ], + "tile_types": [ + "DSP_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE2A2_14", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_ER1BEG2_14", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_LH9_14", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_ER1BEG1_14", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_WW2END0_14", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WW4END1_14", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX41_14", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX18_14", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_FAN4_14", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_LH8_14", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_14", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_EE4A2_14", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_FAN0_14", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_LH3_14", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_EE4BEG2_14", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_WW2END1_14", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_IMUX26_14", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_NW4A1_14", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SW2A2_14", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_IMUX5_14", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX0_14", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_LH10_14", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_NW4A3_14", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SW4A1_14", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_LH1_14", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_EE2A3_14", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EL1BEG3_14", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_IMUX46_14", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW2END3_14", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW4C2_14", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_14", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_WW4END2_14", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX42_14", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_WW2END2_14", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_EE2A0_14", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WW4C1_14", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_NW4END2_14", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_LH4_14", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_IMUX29_14", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_NE2A0_14", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX34_14", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_IMUX20_14", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SE2A3_14", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SE4BEG1_14", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_IMUX23_14", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NE4C2_14", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_SW4END2_14", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_NE4C0_14", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_NE4BEG0_14", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_NW4A2_14", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_WW4A0_14", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX43_14", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_EE2BEG2_14", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_EL1BEG2_14", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_WW4END0_14", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_SW4END0_14", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_ER1BEG0_14", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_WW2A2_14", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_NW4END1_14", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_WR1END3_14", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_14", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_IMUX25_14", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_BYP7_14", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_NW4A0_14", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_BYP2_14", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_IMUX8_14", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_CLK1_14", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX30_14", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_WW4A1_14", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_WW4A3_14", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_14", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_14", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B10_14", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_14", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_WL1END2_14", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WR1END2_14", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_14", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_WW4C0_14", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_SW4END3_14", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_EE2BEG0_14", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_EE4B3_14", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_LH6_14", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX2_14", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_EE4A3_14", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B11_14", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "CFG_CENTER_IMUX19_14", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_WL1END3_14", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_EE4C1_14", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_BYP6_14", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX36_14", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW2A0_14", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_NE4C3_14", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_EE2A1_14", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX7_14", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_IMUX38_14", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_EE2BEG3_14", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_SW4A0_14", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_WW4B1_14", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_WW2A3_14", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX10_14", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_NE2A1_14", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_SE4C1_14", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_LH2_14", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_NE2A3_14", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX16_14", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX33_14", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_SE2A0_14", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_FAN3_14", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_WW4A2_14", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_EE4C3_14", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_WW4B3_14", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_LH12_14", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX31_14", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_ER1BEG3_14", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_EE4B2_14", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_EL1BEG1_14", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_EE4A0_14", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_IMUX11_14", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_SE4BEG3_14", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_EE4BEG0_14", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_IMUX13_14", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_IMUX39_14", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_SE4C3_14", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX37_14", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_FAN2_14", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_FAN1_14", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_WW4B2_14", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_NW2A3_14", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_SE4C2_14", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_SW2A1_14", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_SE4C0_14", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_IMUX12_14", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX4_14", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX44_14", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WR1END1_14", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_14", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_EE4B0_14", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_EE2BEG1_14", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_SE4BEG0_14", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_CTRL1_14", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_NE4BEG1_14", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX15_14", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_SW4A3_14", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EE4BEG1_14", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_FAN5_14", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SE2A1_14", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NE4BEG3_14", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX32_14", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_WW4C3_14", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_BYP4_14", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WR1END0_14", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_IMUX28_14", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_14", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_IMUX22_14", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_LH5_14", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_FAN7_14", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_LH11_14", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_IMUX35_14", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_IMUX9_14", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_NW2A0_14", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_IMUX47_14", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_SE2A2_14", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_WW4B0_14", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_WW2A0_14", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_SW2A3_14", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_IMUX14_14", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_NW4END0_14", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_BYP3_14", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_NW4END3_14", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_IMUX40_14", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_IMUX6_14", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX21_14", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_WW4END3_14", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_14", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_BYP0_14", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_EL1BEG0_14", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_CLK0_14", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_SW4A2_14", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_14", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_EE4C0_14", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_IMUX45_14", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_NE4C1_14", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_WL1END0_14", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_SW4END1_14", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_14", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_IMUX27_14", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX3_14", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_EE4BEG3_14", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX24_14", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_WL1END1_14", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_NE2A2_14", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE4A1_14", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_SE4BEG2_14", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE4C2_14", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX17_14", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_NE4BEG2_14", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_CTRL0_14", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_BYP5_14", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_FAN6_14", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_EE4B1_14", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_NW2A2_14", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW2A1_14", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_LH7_14", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_IMUX1_14", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_BYP1_14", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_NW2A1_14", + "VFRAME_NW2A1" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "PCIE_BYP0_R_8", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_SE2A2_8", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_IMUX40_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_WW2END1_8", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_WW2A1_8", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_NE4BEG2_8", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_IMUX28_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_8", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_IMUX14_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_SW4END1_8", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_EE4C1_8", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_EE2A1_8", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_WW2A2_8", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_WW4B3_8", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_EE2A3_8", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_CLK1_R_8", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_SW4A1_8", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_LH9_8", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_WW4END2_8", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_IMUX46_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_NW4A2_8", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_8", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_IMUX12_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_SW4END0_8", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_WW4A1_8", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_FAN7_R_8", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_WW4B1_8", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_NW2A1_8", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_EE4BEG2_8", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_EE4A3_8", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_NW4END1_8", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_FAN4_R_8", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_LH11_8", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_WW4END3_8", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_IMUX21_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_8", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_8", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_8", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_IMUX35_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_IMUX33_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_8", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_BYP4_R_8", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_IMUX17_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_EL1BEG3_8", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_SE2A0_8", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_WR1END3_8", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_BYP6_R_8", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_LH6_8", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_8", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_IMUX15_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_NE4BEG3_8", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_NE2A2_8", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_WW2END3_8", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_WW4END1_8", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_8", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_SW2A1_8", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_CTRL1_R_8", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_SE4C0_8", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_NW4A3_8", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_IMUX26_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_IMUX38_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_IMUX10_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_WR1END2_8", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_EE2BEG3_8", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_WW4C0_8", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_IMUX27_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_ER1BEG0_8", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_IMUX4_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_EE4B1_8", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_BYP7_R_8", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_SE4C2_8", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_EE2A2_8", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_WW4B2_8", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_EE4B0_8", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX25_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_EE4A1_8", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_SW2A0_8", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_EL1BEG1_8", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_IMUX19_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_WW4C1_8", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_8", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_NE4C3_8", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_IMUX0_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_SE4BEG0_8", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_WW4B0_8", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_ER1BEG1_8", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_FAN1_R_8", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_IMUX47_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_8", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_8", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_EE4B3_8", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_SW4A2_8", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_IMUX34_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_CTRL0_R_8", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_EE4C0_8", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_FAN3_R_8", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_SE4BEG3_8", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_WW2END2_8", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_IMUX23_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_LH4_8", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_NE4C2_8", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_EE4BEG3_8", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_WR1END1_8", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_NE2A1_8", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_LH3_8", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_SE4C1_8", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_IMUX3_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_WW4A3_8", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_LH7_8", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_WW2END0_8", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_IMUX41_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_WR1END0_8", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_8", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_8", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_IMUX1_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_8", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_ER1BEG2_8", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_WL1END2_8", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_IMUX16_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_IMUX39_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_LH12_8", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_WW4C2_8", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_EE4A0_8", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_NW4A1_8", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_IMUX24_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_IMUX13_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_IMUX42_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_8", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_SE4BEG2_8", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_WW4A2_8", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_NW4END0_8", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_WW2A0_8", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_WL1END1_8", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_8", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_EL1BEG0_8", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_LH5_8", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_IMUX36_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_8", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_BYP5_R_8", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_IMUX22_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_8", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_SE4BEG1_8", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_IMUX37_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_NE4C1_8", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_FAN6_R_8", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_SW4A0_8", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_IMUX11_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_8", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_CLK0_R_8", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_IMUX7_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_NE2A0_8", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_NE4C0_8", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_IMUX2_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_WL1END0_8", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_EE2BEG1_8", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_NW2A0_8", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_IMUX5_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_SW4A3_8", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_LH2_8", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_FAN0_R_8", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_BYP3_R_8", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_SW4END2_8", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_EE4C2_8", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_SW2A3_8", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX32_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_IMUX45_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_EE2BEG2_8", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_ER1BEG3_8", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_IMUX20_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_NW2A3_8", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_NW4END2_8", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_EE2A0_8", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_IMUX18_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_EE2BEG0_8", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_EE4B2_8", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_IMUX43_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_EE4A2_8", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_NE2A3_8", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_EE4BEG0_8", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX9_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_SE2A3_8", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_IMUX29_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_FAN2_R_8", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_BYP1_R_8", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_SW2A2_8", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_IMUX30_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_SE2A1_8", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_SE4C3_8", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_NE4BEG1_8", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX8_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_LH8_8", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4C3_8", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_IMUX6_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_IMUX44_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_LH1_8", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_WW4C3_8", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_8", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_SW4END3_8", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_8", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_FAN5_R_8", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_WW2A3_8", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_EL1BEG2_8", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_NW2A2_8", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_BYP2_R_8", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_8", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_WL1END3_8", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_8", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_8", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_LH10_8", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_EE4BEG1_8", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_NE4BEG0_8", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_NW4A0_8", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_NW4END3_8", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_IMUX31_R_8", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_WW4A0_8", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_WW4END0_8", + "INT_INTERFACE_WW4END0" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SW4A0_0", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EL1BEG1_0", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_EE4A3_0", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE4C1_0", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_NW2A2_0", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_SE4BEG2_0", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW4C2_0", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_EE4B3_0", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SW4A3_0", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_NE4C2_0", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_ER1BEG1_0", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_EE2A2_0", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_EE2A3_0", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NE2A0_0", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_NW4A2_0", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NE4C1_0", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW2A1_0", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_SE4BEG0_0", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_WW4END0_0", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_NE4BEG3_0", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_EE4BEG2_0", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SE2A3_0", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SE2A1_0", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_ER1BEG0_0", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_SW4END1_0", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_WW4A2_0", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_NW4END0_0", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_EE2BEG1_0", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_WW4B1_0", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW4END2_0", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_SE4BEG3_0", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_LH1_0", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_LH3_0", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_NW2A3_0", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_EE4B2_0", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_SE4BEG1_0", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SW2A3_0", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_EL1BEG0_0", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_SW2A2_0", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_ER1BEG3_0", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW4B0_0", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_EE2A1_0", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_LH10_0", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WW4END1_0", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE4C3_0", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_EE2A0_0", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_EE2BEG2_0", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NW4END3_0", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_NW4END2_0", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4END3_0", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_EE4A0_0", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4B0_0", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH2_0", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_SE2A0_0", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SE4C2_0", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_LH5_0", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_WW4A0_0", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_NE4C3_0", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WL1END3_0", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_WW2A3_0", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WW4C0_0", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_LH7_0", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_NE4BEG2_0", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_WL1END1_0", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_WW2END2_0", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_WW2END1_0", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_SE4C3_0", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WW4B2_0", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE4B1_0", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_WL1END2_0", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WW2END0_0", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NE4BEG0_0", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NE4BEG1_0", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_LH9_0", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_EL1BEG2_0", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_WW4A3_0", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_LH11_0", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW2A0_0", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WR1END1_0", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_NW2A0_0", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_SW4A1_0", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_LH8_0", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_EE2BEG3_0", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_SE2A2_0", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4A2_0", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SW2A0_0", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WL1END0_0", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_EE4BEG3_0", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WR1END3_0", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_NE2A2_0", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_SW4END0_0", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_LH4_0", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE4BEG0_0", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NW4END1_0", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_SW4END3_0", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_EE2BEG0_0", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_NW4A1_0", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SW4A2_0", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_EL1BEG3_0", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WW4C1_0", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_LH6_0", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_NW4A0_0", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SE4C1_0", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_NE2A3_0", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_WW4A1_0", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_WW4C3_0", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE4C0_0", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_LH12_0", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_ER1BEG2_0", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_WR1END2_0", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_EE4A1_0", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_WW2A2_0", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WW2END3_0", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_NW4A3_0", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_EE4C2_0", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NE4C0_0", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_SW2A1_0", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4BEG1_0", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_WW4B3_0", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SE4C0_0", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_SW4END2_0", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WR1END0_0", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_NW2A1_0", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_NE2A1_0", + "INT_FEEDTHRU_2_NE2A1" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_RCLK_DIV_CE0", + "IOI_RCLK_DIV_CE0" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "RIOI_I2GCLK_TOP1" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0" + ], + [ + "HCLK_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP0", + "RIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_DCI_TSTHLN", + "IOI_DCI_TSTHLN" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IDELAYCTRL_UPPULSEOUT" + ], + [ + "HCLK_RCLK_DIV_CE1", + "IOI_RCLK_DIV_CE1" + ], + [ + "HCLK_IOI_DCI_TSTHLP", + "IOI_DCI_TSTHLP" + ], + [ + "HCLK_IOI_DCI_DCIDONE", + "IOI_DCI_DCIDONE" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_RCLK_IMUX1", + "IOI_IMUX_RC1" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_RCLK_IMUX0", + "IOI_IMUX_RC0" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_IDELAYCTRL_RST", + "IOI_IDELAYCTRL_RST" + ], + [ + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IDELAYCTRL_DNPULSEOUT" + ], + [ + "HCLK_IOI_DCI_TSTRST", + "IOI_DCI_TSTRST0" + ] + ], + "tile_types": [ + "HCLK_IOI", + "RIOI" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "CLK_HROW_SW4END2_3", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_CTRL1_3", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_IMUX24_3", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_WW4C2_3", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_EE4A3_3", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_IMUX7_3", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_CLK0_3", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_FAN2_3", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_SE4BEG2_3", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_IMUX35_3", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_EE4C1_3", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_NE2A1_3", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_FAN0_3", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_WW2A3_3", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_FAN4_3", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_EE2BEG3_3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_WW4A3_3", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_SE4BEG3_3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_NW2A2_3", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_IMUX21_3", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_WW4END1_3", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_SW2A1_3", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_SE4C3_3", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_IMUX27_3", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_EE4BEG0_3", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_SE4BEG0_3", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_WR1END0_3", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_EL1BEG3_3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_IMUX43_3", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_NW4A1_3", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_WL1END0_3", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_WL1END1_3", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_IMUX6_3", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_SE2A1_3", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_NW4END1_3", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_SW4END1_3", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_NW2A1_3", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_ER1BEG2_3", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_IMUX39_3", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_EE2BEG0_3", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_WW2END0_3", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_SW4END3_3", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_NE4C2_3", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_IMUX42_3", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_BYP6_3", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_EE2A0_3", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_WL1END3_3", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_WW4B2_3", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_LH9_3", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_IMUX30_3", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_BYP4_3", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_IMUX23_3", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_WW4A1_3", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_LH12_3", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_SW2A3_3", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_NE2A0_3", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_EE2BEG2_3", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_ER1BEG0_3", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_IMUX36_3", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_IMUX0_3", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_LH4_3", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_IMUX19_3", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_WW2A2_3", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_ER1BEG1_3", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_SE2A3_3", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_EE4B3_3", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_IMUX5_3", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_IMUX1_3", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_WW4END3_3", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_LH1_3", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_EE2A1_3", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_EE4B2_3", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_BYP5_3", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_NW4END2_3", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_BYP2_3", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_WW2END1_3", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_SE4C1_3", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_EE2BEG1_3", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_WW4A2_3", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_EE4A0_3", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_EE4C3_3", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_IMUX46_3", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_IMUX9_3", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_IMUX18_3", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_NE4BEG1_3", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_WW2END2_3", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_IMUX28_3", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_WW4C0_3", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_EE2A3_3", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_IMUX3_3", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_EL1BEG2_3", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_SW4A2_3", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_WW2A1_3", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_CTRL0_3", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_WW4END0_3", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_SW4A0_3", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_EL1BEG1_3", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_IMUX2_3", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_SE2A0_3", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_LH6_3", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_EE4C0_3", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_EE4B0_3", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_NE4C0_3", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_IMUX22_3", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_BYP1_3", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_FAN5_3", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_EE4C2_3", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_EE2A2_3", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_WW4B3_3", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_LH2_3", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_IMUX13_3", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_NW2A0_3", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_BYP7_3", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_IMUX37_3", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_SE4C0_3", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_NE4C1_3", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_WW2END3_3", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_IMUX44_3", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_IMUX20_3", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_SE2A2_3", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_IMUX31_3", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_NE4C3_3", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_WL1END2_3", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_SW4END0_3", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_IMUX4_3", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_SW2A2_3", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_WR1END2_3", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_NE2A3_3", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_SW4A3_3", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_NW4A0_3", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_NW4A2_3", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_FAN7_3", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_IMUX26_3", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_WW4B0_3", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_IMUX10_3", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_IMUX14_3", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_BYP0_3", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_CLK1_3", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_ER1BEG3_3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_SW2A0_3", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE4A2_3", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_LH5_3", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_NW2A3_3", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_NE2A2_3", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_WW2A0_3", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_IMUX47_3", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_NE4BEG3_3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_FAN6_3", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_FAN1_3", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_BYP3_3", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_WW4END2_3", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_WW4A0_3", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_SE4BEG1_3", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_NW4A3_3", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_EE4BEG2_3", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_IMUX25_3", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_IMUX32_3", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_IMUX33_3", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_LH10_3", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_IMUX15_3", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_EL1BEG0_3", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_FAN3_3", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_IMUX40_3", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_WW4B1_3", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_IMUX34_3", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_NW4END0_3", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_LH7_3", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_IMUX17_3", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_LH8_3", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_EE4A1_3", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_EE4BEG3_3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_IMUX11_3", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_SW4A1_3", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_LH11_3", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_WR1END1_3", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_WW4C3_3", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_IMUX45_3", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_NE4BEG2_3", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_IMUX41_3", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_LH3_3", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_IMUX38_3", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_IMUX8_3", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_EE4BEG1_3", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_EE4B1_3", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_SE4C2_3", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_IMUX16_3", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_IMUX29_3", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_IMUX12_3", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_NE4BEG0_3", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_NW4END3_3", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_WW4C1_3", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_WR1END3_3", + "INT_INTERFACE_WR1END3" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CLK_HROW_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_LH2_4", + "VBRK_LH2" + ], + [ + "CLK_HROW_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_LH8_4", + "VBRK_LH8" + ], + [ + "CLK_HROW_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_LH1_4", + "VBRK_LH1" + ], + [ + "CLK_HROW_LH10_4", + "VBRK_LH10" + ], + [ + "CLK_HROW_LH6_4", + "VBRK_LH6" + ], + [ + "CLK_HROW_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_LH12_4", + "VBRK_LH12" + ], + [ + "CLK_HROW_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_LH5_4", + "VBRK_LH5" + ], + [ + "CLK_HROW_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_LH4_4", + "VBRK_LH4" + ], + [ + "CLK_HROW_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_MONITOR_N_4", + "VBRK_MONITOR_N" + ], + [ + "CLK_HROW_LH3_4", + "VBRK_LH3" + ], + [ + "CLK_HROW_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_LH7_4", + "VBRK_LH7" + ], + [ + "CLK_HROW_LH11_4", + "VBRK_LH11" + ], + [ + "CLK_HROW_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_MONITOR_P_4", + "VBRK_MONITOR_P" + ], + [ + "CLK_HROW_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_LH9_4", + "VBRK_LH9" + ], + [ + "CLK_HROW_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_NE2A0_4", + "VBRK_NE2A0" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -9 + ], + "wire_pairs": [ + [ + "MONITOR_WW2END3_9", + "VFRAME_WW2END3" + ], + [ + "MONITOR_NE4C1_9", + "VFRAME_NE4C1" + ], + [ + "MONITOR_SW2A3_9", + "VFRAME_SW2A3" + ], + [ + "MONITOR_NE4BEG3_9", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_LH10_9", + "VFRAME_LH10" + ], + [ + "MONITOR_IMUX2_9", + "VFRAME_IMUX2" + ], + [ + "MONITOR_WW4C3_9", + "VFRAME_WW4C3" + ], + [ + "MONITOR_IMUX30_9", + "VFRAME_IMUX30" + ], + [ + "MONITOR_SW4A0_9", + "VFRAME_SW4A0" + ], + [ + "MONITOR_IMUX27_9", + "VFRAME_IMUX27" + ], + [ + "MONITOR_NW2A3_9", + "VFRAME_NW2A3" + ], + [ + "MONITOR_SW4END2_9", + "VFRAME_SW4END2" + ], + [ + "MONITOR_WL1END0_9", + "VFRAME_WL1END0" + ], + [ + "MONITOR_IMUX41_9", + "VFRAME_IMUX41" + ], + [ + "MONITOR_SE4BEG3_9", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_FAN4_9", + "VFRAME_FAN4" + ], + [ + "MONITOR_FAN0_9", + "VFRAME_FAN0" + ], + [ + "MONITOR_LH4_9", + "VFRAME_LH4" + ], + [ + "MONITOR_IMUX21_9", + "VFRAME_IMUX21" + ], + [ + "MONITOR_IMUX6_9", + "VFRAME_IMUX6" + ], + [ + "MONITOR_ER1BEG3_9", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_IMUX5_9", + "VFRAME_IMUX5" + ], + [ + "MONITOR_SW2A2_9", + "VFRAME_SW2A2" + ], + [ + "MONITOR_BYP3_9", + "VFRAME_BYP3" + ], + [ + "MONITOR_LH9_9", + "VFRAME_LH9" + ], + [ + "MONITOR_SE4C0_9", + "VFRAME_SE4C0" + ], + [ + "MONITOR_IMUX25_9", + "VFRAME_IMUX25" + ], + [ + "MONITOR_IMUX20_9", + "VFRAME_IMUX20" + ], + [ + "MONITOR_EE2BEG1_9", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_NE4BEG2_9", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_IMUX44_9", + "VFRAME_IMUX44" + ], + [ + "MONITOR_NW4END2_9", + "VFRAME_NW4END2" + ], + [ + "MONITOR_ER1BEG2_9", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_LH12_9", + "VFRAME_LH12" + ], + [ + "MONITOR_IMUX14_9", + "VFRAME_IMUX14" + ], + [ + "MONITOR_IMUX35_9", + "VFRAME_IMUX35" + ], + [ + "MONITOR_BYP1_9", + "VFRAME_BYP1" + ], + [ + "MONITOR_WW2A3_9", + "VFRAME_WW2A3" + ], + [ + "MONITOR_NW2A1_9", + "VFRAME_NW2A1" + ], + [ + "MONITOR_SE4C1_9", + "VFRAME_SE4C1" + ], + [ + "MONITOR_EE4A2_9", + "VFRAME_EE4A2" + ], + [ + "MONITOR_IMUX38_9", + "VFRAME_IMUX38" + ], + [ + "MONITOR_EE2BEG0_9", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_IMUX46_9", + "VFRAME_IMUX46" + ], + [ + "MONITOR_EE4C2_9", + "VFRAME_EE4C2" + ], + [ + "MONITOR_LH3_9", + "VFRAME_LH3" + ], + [ + "MONITOR_CLK1_9", + "VFRAME_CLK1" + ], + [ + "MONITOR_SW2A0_9", + "VFRAME_SW2A0" + ], + [ + "MONITOR_IMUX32_9", + "VFRAME_IMUX32" + ], + [ + "MONITOR_NW4A0_9", + "VFRAME_NW4A0" + ], + [ + "MONITOR_IMUX26_9", + "VFRAME_IMUX26" + ], + [ + "MONITOR_NE4C0_9", + "VFRAME_NE4C0" + ], + [ + "MONITOR_IMUX10_9", + "VFRAME_IMUX10" + ], + [ + "MONITOR_WW2END0_9", + "VFRAME_WW2END0" + ], + [ + "MONITOR_WW4B3_9", + "VFRAME_WW4B3" + ], + [ + "MONITOR_EE2A2_9", + "VFRAME_EE2A2" + ], + [ + "MONITOR_IMUX37_9", + "VFRAME_IMUX37" + ], + [ + "MONITOR_IMUX24_9", + "VFRAME_IMUX24" + ], + [ + "MONITOR_IMUX23_9", + "VFRAME_IMUX23" + ], + [ + "MONITOR_IMUX22_9", + "VFRAME_IMUX22" + ], + [ + "MONITOR_IMUX11_9", + "VFRAME_IMUX11" + ], + [ + "MONITOR_NW4END1_9", + "VFRAME_NW4END1" + ], + [ + "MONITOR_WR1END2_9", + "VFRAME_WR1END2" + ], + [ + "MONITOR_WW4A1_9", + "VFRAME_WW4A1" + ], + [ + "MONITOR_WW4B2_9", + "VFRAME_WW4B2" + ], + [ + "MONITOR_EE4B2_9", + "VFRAME_EE4B2" + ], + [ + "MONITOR_LH11_9", + "VFRAME_LH11" + ], + [ + "MONITOR_IMUX40_9", + "VFRAME_IMUX40" + ], + [ + "MONITOR_WL1END1_9", + "VFRAME_WL1END1" + ], + [ + "MONITOR_IMUX39_9", + "VFRAME_IMUX39" + ], + [ + "MONITOR_LH2_9", + "VFRAME_LH2" + ], + [ + "MONITOR_BYP2_9", + "VFRAME_BYP2" + ], + [ + "MONITOR_NE2A2_9", + "VFRAME_NE2A2" + ], + [ + "MONITOR_SE2A3_9", + "VFRAME_SE2A3" + ], + [ + "MONITOR_SE4BEG1_9", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_IMUX19_9", + "VFRAME_IMUX19" + ], + [ + "MONITOR_IMUX3_9", + "VFRAME_IMUX3" + ], + [ + "MONITOR_EE2BEG2_9", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_SE2A1_9", + "VFRAME_SE2A1" + ], + [ + "MONITOR_BYP5_9", + "VFRAME_BYP5" + ], + [ + "MONITOR_IMUX43_9", + "VFRAME_IMUX43" + ], + [ + "MONITOR_IMUX31_9", + "VFRAME_IMUX31" + ], + [ + "MONITOR_FAN2_9", + "VFRAME_FAN2" + ], + [ + "MONITOR_SW4END1_9", + "VFRAME_SW4END1" + ], + [ + "MONITOR_SW4A3_9", + "VFRAME_SW4A3" + ], + [ + "MONITOR_EE4B1_9", + "VFRAME_EE4B1" + ], + [ + "MONITOR_CTRL0_9", + "VFRAME_CTRL0" + ], + [ + "MONITOR_IMUX9_9", + "VFRAME_IMUX9" + ], + [ + "MONITOR_IMUX42_9", + "VFRAME_IMUX42" + ], + [ + "MONITOR_BYP7_9", + "VFRAME_BYP7" + ], + [ + "MONITOR_IMUX13_9", + "VFRAME_IMUX13" + ], + [ + "MONITOR_NE4C3_9", + "VFRAME_NE4C3" + ], + [ + "MONITOR_EL1BEG3_9", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_NW4A3_9", + "VFRAME_NW4A3" + ], + [ + "MONITOR_WW2A2_9", + "VFRAME_WW2A2" + ], + [ + "MONITOR_SE4C2_9", + "VFRAME_SE4C2" + ], + [ + "MONITOR_SE4BEG0_9", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_SW4END0_9", + "VFRAME_SW4END0" + ], + [ + "MONITOR_EE2BEG3_9", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_LH1_9", + "VFRAME_LH1" + ], + [ + "MONITOR_WW4C0_9", + "VFRAME_WW4C0" + ], + [ + "MONITOR_NW2A0_9", + "VFRAME_NW2A0" + ], + [ + "MONITOR_IMUX1_9", + "VFRAME_IMUX1" + ], + [ + "MONITOR_IMUX28_9", + "VFRAME_IMUX28" + ], + [ + "MONITOR_EE4A0_9", + "VFRAME_EE4A0" + ], + [ + "MONITOR_NE2A3_9", + "VFRAME_NE2A3" + ], + [ + "MONITOR_SE2A0_9", + "VFRAME_SE2A0" + ], + [ + "MONITOR_NW4END3_9", + "VFRAME_NW4END3" + ], + [ + "MONITOR_SW4END3_9", + "VFRAME_SW4END3" + ], + [ + "MONITOR_EE4BEG1_9", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_NE4C2_9", + "VFRAME_NE4C2" + ], + [ + "MONITOR_NE2A0_9", + "VFRAME_NE2A0" + ], + [ + "MONITOR_EE4B0_9", + "VFRAME_EE4B0" + ], + [ + "MONITOR_EE2A3_9", + "VFRAME_EE2A3" + ], + [ + "MONITOR_NE2A1_9", + "VFRAME_NE2A1" + ], + [ + "MONITOR_LH8_9", + "VFRAME_LH8" + ], + [ + "MONITOR_ER1BEG1_9", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_LH7_9", + "VFRAME_LH7" + ], + [ + "MONITOR_IMUX0_9", + "VFRAME_IMUX0" + ], + [ + "MONITOR_NW4A1_9", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WW4A2_9", + "VFRAME_WW4A2" + ], + [ + "MONITOR_EE4BEG2_9", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_ER1BEG0_9", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_EE4BEG3_9", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_WW4END2_9", + "VFRAME_WW4END2" + ], + [ + "MONITOR_NW2A2_9", + "VFRAME_NW2A2" + ], + [ + "MONITOR_BYP4_9", + "VFRAME_BYP4" + ], + [ + "MONITOR_LH6_9", + "VFRAME_LH6" + ], + [ + "MONITOR_SW2A1_9", + "VFRAME_SW2A1" + ], + [ + "MONITOR_IMUX29_9", + "VFRAME_IMUX29" + ], + [ + "MONITOR_EE4B3_9", + "VFRAME_EE4B3" + ], + [ + "MONITOR_IMUX7_9", + "VFRAME_IMUX7" + ], + [ + "MONITOR_WW2A0_9", + "VFRAME_WW2A0" + ], + [ + "MONITOR_IMUX4_9", + "VFRAME_IMUX4" + ], + [ + "MONITOR_EE4C3_9", + "VFRAME_EE4C3" + ], + [ + "MONITOR_WW4END1_9", + "VFRAME_WW4END1" + ], + [ + "MONITOR_WR1END0_9", + "VFRAME_WR1END0" + ], + [ + "MONITOR_EE4A3_9", + "VFRAME_EE4A3" + ], + [ + "MONITOR_WW4END0_9", + "VFRAME_WW4END0" + ], + [ + "MONITOR_SE2A2_9", + "VFRAME_SE2A2" + ], + [ + "MONITOR_WW4C2_9", + "VFRAME_WW4C2" + ], + [ + "MONITOR_NW4A2_9", + "VFRAME_NW4A2" + ], + [ + "MONITOR_FAN3_9", + "VFRAME_FAN3" + ], + [ + "MONITOR_SE4BEG2_9", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_FAN5_9", + "VFRAME_FAN5" + ], + [ + "MONITOR_NW4END0_9", + "VFRAME_NW4END0" + ], + [ + "MONITOR_WR1END1_9", + "VFRAME_WR1END1" + ], + [ + "MONITOR_IMUX34_9", + "VFRAME_IMUX34" + ], + [ + "MONITOR_LH5_9", + "VFRAME_LH5" + ], + [ + "MONITOR_WW4A0_9", + "VFRAME_WW4A0" + ], + [ + "MONITOR_FAN1_9", + "VFRAME_FAN1" + ], + [ + "MONITOR_SE4C3_9", + "VFRAME_SE4C3" + ], + [ + "MONITOR_IMUX47_9", + "VFRAME_IMUX47" + ], + [ + "MONITOR_IMUX36_9", + "VFRAME_IMUX36" + ], + [ + "MONITOR_WW2A1_9", + "VFRAME_WW2A1" + ], + [ + "MONITOR_NE4BEG0_9", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_IMUX45_9", + "VFRAME_IMUX45" + ], + [ + "MONITOR_WR1END3_9", + "VFRAME_WR1END3" + ], + [ + "MONITOR_SW4A1_9", + "VFRAME_SW4A1" + ], + [ + "MONITOR_IMUX16_9", + "VFRAME_IMUX16" + ], + [ + "MONITOR_EE4A1_9", + "VFRAME_EE4A1" + ], + [ + "MONITOR_IMUX12_9", + "VFRAME_IMUX12" + ], + [ + "MONITOR_NE4BEG1_9", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_WW4B1_9", + "VFRAME_WW4B1" + ], + [ + "MONITOR_EE2A1_9", + "VFRAME_EE2A1" + ], + [ + "MONITOR_EL1BEG2_9", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_IMUX15_9", + "VFRAME_IMUX15" + ], + [ + "MONITOR_IMUX17_9", + "VFRAME_IMUX17" + ], + [ + "MONITOR_WW4A3_9", + "VFRAME_WW4A3" + ], + [ + "MONITOR_WW4C1_9", + "VFRAME_WW4C1" + ], + [ + "MONITOR_EL1BEG0_9", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_IMUX33_9", + "VFRAME_IMUX33" + ], + [ + "MONITOR_WW4END3_9", + "VFRAME_WW4END3" + ], + [ + "MONITOR_BYP0_9", + "VFRAME_BYP0" + ], + [ + "MONITOR_FAN6_9", + "VFRAME_FAN6" + ], + [ + "MONITOR_EE4BEG0_9", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_CTRL1_9", + "VFRAME_CTRL1" + ], + [ + "MONITOR_IMUX18_9", + "VFRAME_IMUX18" + ], + [ + "MONITOR_WL1END3_9", + "VFRAME_WL1END3" + ], + [ + "MONITOR_WW4B0_9", + "VFRAME_WW4B0" + ], + [ + "MONITOR_EE2A0_9", + "VFRAME_EE2A0" + ], + [ + "MONITOR_WL1END2_9", + "VFRAME_WL1END2" + ], + [ + "MONITOR_WW2END2_9", + "VFRAME_WW2END2" + ], + [ + "MONITOR_BYP6_9", + "VFRAME_BYP6" + ], + [ + "MONITOR_CLK0_9", + "VFRAME_CLK0" + ], + [ + "MONITOR_SW4A2_9", + "VFRAME_SW4A2" + ], + [ + "MONITOR_EE4C1_9", + "VFRAME_EE4C1" + ], + [ + "MONITOR_EE4C0_9", + "VFRAME_EE4C0" + ], + [ + "MONITOR_IMUX8_9", + "VFRAME_IMUX8" + ], + [ + "MONITOR_FAN7_9", + "VFRAME_FAN7" + ], + [ + "MONITOR_EL1BEG1_9", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_WW2END1_9", + "VFRAME_WW2END1" + ] + ], + "tile_types": [ + "MONITOR_MID_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + -8 + ], + "wire_pairs": [ + [ + "CFG_CENTER_NE2A2_18", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_WW2END0_18", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NE4C1_18", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE2A3_18", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_NW4END2_18", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_NW4A0_18", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_EE4B2_18", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_WL1END0_18", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_LH3_18", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_NE4C2_18", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EL1BEG1_18", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SE4C3_18", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_LH6_18", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WL1END3_18", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_SW4END3_18", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NW4END1_18", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_LH7_18", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_NW2A3_18", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_SW4A3_18", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_WW4END1_18", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_WW2A0_18", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WW2A2_18", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_LH11_18", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW2END3_18", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_EL1BEG0_18", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_SE4BEG1_18", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_NE2A0_18", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_WL1END1_18", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_EE4A0_18", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_SW4A2_18", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_ER1BEG2_18", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_SW4END2_18", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_NE4BEG1_18", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WW4C3_18", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4B1_18", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW2A1_18", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_SW2A3_18", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_SE4BEG3_18", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_NE4BEG2_18", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EE2A0_18", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW4A0_18", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_NW2A1_18", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SW4A0_18", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WW4B3_18", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SW4END0_18", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EE4C3_18", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_EE2A1_18", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_EE4BEG1_18", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_SW2A2_18", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_LH1_18", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_SW2A1_18", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE2BEG2_18", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW4A2_18", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE2BEG0_18", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_SW4END1_18", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EE4BEG0_18", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EL1BEG2_18", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_EE4B3_18", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NW4A1_18", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_EE4B0_18", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_EE2BEG3_18", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_SW2A0_18", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_LH12_18", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WR1END1_18", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SE4C2_18", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_WW4B0_18", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_EE4A1_18", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EE2A2_18", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_EL1BEG3_18", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WW4A3_18", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_WW4END3_18", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4END0_18", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EE4C2_18", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_WW2END1_18", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE4C1_18", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_ER1BEG0_18", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_SE2A1_18", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW2A3_18", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WW4END2_18", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_LH4_18", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SE2A2_18", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_WW4B2_18", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE2A3_18", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_SE2A3_18", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_EE4BEG3_18", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_SW4A1_18", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NW2A0_18", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WR1END0_18", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_WR1END2_18", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_NE2A1_18", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_SE4BEG0_18", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_EE4A2_18", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4B1_18", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_LH5_18", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE2BEG1_18", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NW2A2_18", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_SE4BEG2_18", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_LH2_18", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NE4BEG0_18", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_LH10_18", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_EE4C0_18", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WL1END2_18", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WW4C0_18", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NW4END3_18", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_SE4C1_18", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_NW4A3_18", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_ER1BEG1_18", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WW4C2_18", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_WW4A1_18", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_LH9_18", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NE4BEG3_18", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_EE4A3_18", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_NW4A2_18", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NE4C0_18", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_SE2A0_18", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SE4C0_18", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_LH8_18", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_ER1BEG3_18", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_EE4BEG2_18", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WR1END3_18", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_WW4C1_18", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_NW4END0_18", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_WW2END2_18", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_NE4C3_18", + "INT_FEEDTHRU_2_NE4C3" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX44_4", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX34_4", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX28_4", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_LOGIC_OUTS_B11_4", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_IMUX6_4", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B22_4", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX36_4", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX4_4", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_CTRL1_4", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX29_4", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX30_4", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX35_4", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX12_4", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX45_4", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_LOGIC_OUTS_B14_4", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX7_4", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX10_4", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX39_4", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX23_4", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX33_4", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_LOGIC_OUTS_B15_4", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_FAN4_4", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_LOGIC_OUTS_B0_4", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_LOGIC_OUTS_B23_4", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_BYP6_4", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX27_4", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B8_4", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX15_4", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_FAN0_4", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_BYP3_4", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B13_4", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_IMUX5_4", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B12_4", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_LOGIC_OUTS_B16_4", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_CTRL0_4", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX9_4", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX11_4", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX19_4", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX21_4", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX17_4", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX16_4", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_LOGIC_OUTS_B9_4", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_FAN7_4", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX37_4", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_LOGIC_OUTS_B19_4", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B17_4", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B5_4", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_BYP0_4", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX26_4", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX22_4", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B6_4", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX2_4", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_BYP1_4", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B7_4", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_BYP2_4", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX8_4", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_FAN5_4", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX38_4", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX43_4", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_CLK1_4", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX41_4", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B18_4", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX1_4", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_FAN3_4", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN1_4", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B4_4", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B10_4", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_LOGIC_OUTS_B3_4", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_LOGIC_OUTS_B20_4", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX20_4", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX24_4", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_FAN2_4", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX46_4", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX13_4", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX3_4", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX42_4", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX18_4", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX0_4", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_BYP4_4", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX32_4", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN6_4", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX14_4", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_BYP7_4", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B1_4", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX31_4", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX40_4", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B2_4", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX25_4", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_BYP5_4", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX47_4", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_CLK0_4", + "VBRK_EXT_CLK0" + ] + ], + "tile_types": [ + "GTX_CHANNEL_3", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "MONITOR_IMUX46_2", + "VFRAME_IMUX46" + ], + [ + "MONITOR_IMUX44_2", + "VFRAME_IMUX44" + ], + [ + "MONITOR_IMUX7_2", + "VFRAME_IMUX7" + ], + [ + "MONITOR_IMUX23_2", + "VFRAME_IMUX23" + ], + [ + "MONITOR_NE4BEG1_2", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_SW4END3_2", + "VFRAME_SW4END3" + ], + [ + "MONITOR_BYP4_2", + "VFRAME_BYP4" + ], + [ + "MONITOR_IMUX34_2", + "VFRAME_IMUX34" + ], + [ + "MONITOR_LOGIC_OUTS_B12_2", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "MONITOR_SE4C0_2", + "VFRAME_SE4C0" + ], + [ + "MONITOR_IMUX13_2", + "VFRAME_IMUX13" + ], + [ + "MONITOR_IMUX6_2", + "VFRAME_IMUX6" + ], + [ + "MONITOR_EE4BEG2_2", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_IMUX19_2", + "VFRAME_IMUX19" + ], + [ + "MONITOR_NW4A2_2", + "VFRAME_NW4A2" + ], + [ + "MONITOR_IMUX9_2", + "VFRAME_IMUX9" + ], + [ + "MONITOR_NE4C2_2", + "VFRAME_NE4C2" + ], + [ + "MONITOR_EE4C1_2", + "VFRAME_EE4C1" + ], + [ + "MONITOR_SE2A2_2", + "VFRAME_SE2A2" + ], + [ + "MONITOR_LH3_2", + "VFRAME_LH3" + ], + [ + "MONITOR_IMUX42_2", + "VFRAME_IMUX42" + ], + [ + "MONITOR_IMUX17_2", + "VFRAME_IMUX17" + ], + [ + "MONITOR_SE2A0_2", + "VFRAME_SE2A0" + ], + [ + "MONITOR_BYP2_2", + "VFRAME_BYP2" + ], + [ + "MONITOR_LH2_2", + "VFRAME_LH2" + ], + [ + "MONITOR_NE2A2_2", + "VFRAME_NE2A2" + ], + [ + "MONITOR_WW4B1_2", + "VFRAME_WW4B1" + ], + [ + "MONITOR_LOGIC_OUTS_B19_2", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "MONITOR_EE4BEG0_2", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_FAN2_2", + "VFRAME_FAN2" + ], + [ + "MONITOR_EE4B0_2", + "VFRAME_EE4B0" + ], + [ + "MONITOR_WW2END0_2", + "VFRAME_WW2END0" + ], + [ + "MONITOR_SE4BEG0_2", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_FAN3_2", + "VFRAME_FAN3" + ], + [ + "MONITOR_BYP5_2", + "VFRAME_BYP5" + ], + [ + "MONITOR_BYP0_2", + "VFRAME_BYP0" + ], + [ + "MONITOR_WW4C1_2", + "VFRAME_WW4C1" + ], + [ + "MONITOR_SE4C3_2", + "VFRAME_SE4C3" + ], + [ + "MONITOR_EE4B1_2", + "VFRAME_EE4B1" + ], + [ + "MONITOR_IMUX33_2", + "VFRAME_IMUX33" + ], + [ + "MONITOR_IMUX14_2", + "VFRAME_IMUX14" + ], + [ + "MONITOR_NE4BEG2_2", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_IMUX16_2", + "VFRAME_IMUX16" + ], + [ + "MONITOR_WW4A1_2", + "VFRAME_WW4A1" + ], + [ + "MONITOR_WR1END1_2", + "VFRAME_WR1END1" + ], + [ + "MONITOR_WW4C0_2", + "VFRAME_WW4C0" + ], + [ + "MONITOR_LOGIC_OUTS_B15_2", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "MONITOR_LH11_2", + "VFRAME_LH11" + ], + [ + "MONITOR_NW2A1_2", + "VFRAME_NW2A1" + ], + [ + "MONITOR_SW2A0_2", + "VFRAME_SW2A0" + ], + [ + "MONITOR_WW4C2_2", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE4C3_2", + "VFRAME_EE4C3" + ], + [ + "MONITOR_WW4A3_2", + "VFRAME_WW4A3" + ], + [ + "MONITOR_EE4B3_2", + "VFRAME_EE4B3" + ], + [ + "MONITOR_EE2BEG0_2", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_EE4BEG1_2", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX8_2", + "VFRAME_IMUX8" + ], + [ + "MONITOR_LH10_2", + "VFRAME_LH10" + ], + [ + "MONITOR_WW4END3_2", + "VFRAME_WW4END3" + ], + [ + "MONITOR_LH4_2", + "VFRAME_LH4" + ], + [ + "MONITOR_LH6_2", + "VFRAME_LH6" + ], + [ + "MONITOR_IMUX47_2", + "VFRAME_IMUX47" + ], + [ + "MONITOR_SW4A2_2", + "VFRAME_SW4A2" + ], + [ + "MONITOR_BYP1_2", + "VFRAME_BYP1" + ], + [ + "MONITOR_NW4END1_2", + "VFRAME_NW4END1" + ], + [ + "MONITOR_SE2A3_2", + "VFRAME_SE2A3" + ], + [ + "MONITOR_IMUX21_2", + "VFRAME_IMUX21" + ], + [ + "MONITOR_LOGIC_OUTS_B22_2", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "MONITOR_SE4C1_2", + "VFRAME_SE4C1" + ], + [ + "MONITOR_BYP6_2", + "VFRAME_BYP6" + ], + [ + "MONITOR_WW4B3_2", + "VFRAME_WW4B3" + ], + [ + "MONITOR_EE2A2_2", + "VFRAME_EE2A2" + ], + [ + "MONITOR_ER1BEG0_2", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_IMUX45_2", + "VFRAME_IMUX45" + ], + [ + "MONITOR_WR1END2_2", + "VFRAME_WR1END2" + ], + [ + "MONITOR_EE2A3_2", + "VFRAME_EE2A3" + ], + [ + "MONITOR_SW4END2_2", + "VFRAME_SW4END2" + ], + [ + "MONITOR_WL1END2_2", + "VFRAME_WL1END2" + ], + [ + "MONITOR_WR1END3_2", + "VFRAME_WR1END3" + ], + [ + "MONITOR_IMUX24_2", + "VFRAME_IMUX24" + ], + [ + "MONITOR_IMUX37_2", + "VFRAME_IMUX37" + ], + [ + "MONITOR_WW2A0_2", + "VFRAME_WW2A0" + ], + [ + "MONITOR_WR1END0_2", + "VFRAME_WR1END0" + ], + [ + "MONITOR_CLK1_2", + "VFRAME_CLK1" + ], + [ + "MONITOR_NW4A0_2", + "VFRAME_NW4A0" + ], + [ + "MONITOR_SW2A3_2", + "VFRAME_SW2A3" + ], + [ + "MONITOR_SE4BEG3_2", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_IMUX31_2", + "VFRAME_IMUX31" + ], + [ + "MONITOR_WW2END1_2", + "VFRAME_WW2END1" + ], + [ + "MONITOR_BYP3_2", + "VFRAME_BYP3" + ], + [ + "MONITOR_NE2A0_2", + "VFRAME_NE2A0" + ], + [ + "MONITOR_IMUX38_2", + "VFRAME_IMUX38" + ], + [ + "MONITOR_IMUX29_2", + "VFRAME_IMUX29" + ], + [ + "MONITOR_SE4C2_2", + "VFRAME_SE4C2" + ], + [ + "MONITOR_WW4A2_2", + "VFRAME_WW4A2" + ], + [ + "MONITOR_NW4END2_2", + "VFRAME_NW4END2" + ], + [ + "MONITOR_EE2BEG3_2", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_BYP7_2", + "VFRAME_BYP7" + ], + [ + "MONITOR_EE2A1_2", + "VFRAME_EE2A1" + ], + [ + "MONITOR_FAN4_2", + "VFRAME_FAN4" + ], + [ + "MONITOR_EE2BEG2_2", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_ER1BEG3_2", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_SE4BEG2_2", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_WW2A2_2", + "VFRAME_WW2A2" + ], + [ + "MONITOR_LH1_2", + "VFRAME_LH1" + ], + [ + "MONITOR_IMUX12_2", + "VFRAME_IMUX12" + ], + [ + "MONITOR_LOGIC_OUTS_B17_2", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "MONITOR_IMUX2_2", + "VFRAME_IMUX2" + ], + [ + "MONITOR_IMUX30_2", + "VFRAME_IMUX30" + ], + [ + "MONITOR_CTRL0_2", + "VFRAME_CTRL0" + ], + [ + "MONITOR_EE4BEG3_2", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_FAN5_2", + "VFRAME_FAN5" + ], + [ + "MONITOR_LOGIC_OUTS_B20_2", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "MONITOR_IMUX1_2", + "VFRAME_IMUX1" + ], + [ + "MONITOR_EL1BEG0_2", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_SW4A1_2", + "VFRAME_SW4A1" + ], + [ + "MONITOR_LH9_2", + "VFRAME_LH9" + ], + [ + "MONITOR_SW2A1_2", + "VFRAME_SW2A1" + ], + [ + "MONITOR_EE4B2_2", + "VFRAME_EE4B2" + ], + [ + "MONITOR_IMUX3_2", + "VFRAME_IMUX3" + ], + [ + "MONITOR_IMUX27_2", + "VFRAME_IMUX27" + ], + [ + "MONITOR_SE2A1_2", + "VFRAME_SE2A1" + ], + [ + "MONITOR_IMUX36_2", + "VFRAME_IMUX36" + ], + [ + "MONITOR_WW2A1_2", + "VFRAME_WW2A1" + ], + [ + "MONITOR_LOGIC_OUTS_B14_2", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "MONITOR_EL1BEG2_2", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_IMUX35_2", + "VFRAME_IMUX35" + ], + [ + "MONITOR_IMUX26_2", + "VFRAME_IMUX26" + ], + [ + "MONITOR_SW2A2_2", + "VFRAME_SW2A2" + ], + [ + "MONITOR_LH8_2", + "VFRAME_LH8" + ], + [ + "MONITOR_IMUX40_2", + "VFRAME_IMUX40" + ], + [ + "MONITOR_NE2A3_2", + "VFRAME_NE2A3" + ], + [ + "MONITOR_WL1END0_2", + "VFRAME_WL1END0" + ], + [ + "MONITOR_NW2A3_2", + "VFRAME_NW2A3" + ], + [ + "MONITOR_WL1END1_2", + "VFRAME_WL1END1" + ], + [ + "MONITOR_LOGIC_OUTS_B11_2", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "MONITOR_NE4C3_2", + "VFRAME_NE4C3" + ], + [ + "MONITOR_LH12_2", + "VFRAME_LH12" + ], + [ + "MONITOR_NW2A2_2", + "VFRAME_NW2A2" + ], + [ + "MONITOR_EE4A2_2", + "VFRAME_EE4A2" + ], + [ + "MONITOR_WL1END3_2", + "VFRAME_WL1END3" + ], + [ + "MONITOR_WW2END3_2", + "VFRAME_WW2END3" + ], + [ + "MONITOR_IMUX20_2", + "VFRAME_IMUX20" + ], + [ + "MONITOR_LH7_2", + "VFRAME_LH7" + ], + [ + "MONITOR_IMUX15_2", + "VFRAME_IMUX15" + ], + [ + "MONITOR_EL1BEG1_2", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_LOGIC_OUTS_B23_2", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "MONITOR_IMUX39_2", + "VFRAME_IMUX39" + ], + [ + "MONITOR_NW2A0_2", + "VFRAME_NW2A0" + ], + [ + "MONITOR_LOGIC_OUTS_B16_2", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "MONITOR_IMUX11_2", + "VFRAME_IMUX11" + ], + [ + "MONITOR_NE2A1_2", + "VFRAME_NE2A1" + ], + [ + "MONITOR_ER1BEG1_2", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_WW4END2_2", + "VFRAME_WW4END2" + ], + [ + "MONITOR_WW4END1_2", + "VFRAME_WW4END1" + ], + [ + "MONITOR_NW4END3_2", + "VFRAME_NW4END3" + ], + [ + "MONITOR_SW4END1_2", + "VFRAME_SW4END1" + ], + [ + "MONITOR_SW4END0_2", + "VFRAME_SW4END0" + ], + [ + "MONITOR_NE4C1_2", + "VFRAME_NE4C1" + ], + [ + "MONITOR_IMUX5_2", + "VFRAME_IMUX5" + ], + [ + "MONITOR_EE4C0_2", + "VFRAME_EE4C0" + ], + [ + "MONITOR_SW4A3_2", + "VFRAME_SW4A3" + ], + [ + "MONITOR_IMUX41_2", + "VFRAME_IMUX41" + ], + [ + "MONITOR_IMUX10_2", + "VFRAME_IMUX10" + ], + [ + "MONITOR_LH5_2", + "VFRAME_LH5" + ], + [ + "MONITOR_IMUX4_2", + "VFRAME_IMUX4" + ], + [ + "MONITOR_EL1BEG3_2", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_EE4A1_2", + "VFRAME_EE4A1" + ], + [ + "MONITOR_FAN6_2", + "VFRAME_FAN6" + ], + [ + "MONITOR_EE2BEG1_2", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_IMUX22_2", + "VFRAME_IMUX22" + ], + [ + "MONITOR_ER1BEG2_2", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_EE4C2_2", + "VFRAME_EE4C2" + ], + [ + "MONITOR_WW4B2_2", + "VFRAME_WW4B2" + ], + [ + "MONITOR_IMUX32_2", + "VFRAME_IMUX32" + ], + [ + "MONITOR_FAN7_2", + "VFRAME_FAN7" + ], + [ + "MONITOR_LOGIC_OUTS_B21_2", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "MONITOR_CLK0_2", + "VFRAME_CLK0" + ], + [ + "MONITOR_NE4C0_2", + "VFRAME_NE4C0" + ], + [ + "MONITOR_WW4END0_2", + "VFRAME_WW4END0" + ], + [ + "MONITOR_IMUX25_2", + "VFRAME_IMUX25" + ], + [ + "MONITOR_NW4A3_2", + "VFRAME_NW4A3" + ], + [ + "MONITOR_WW4B0_2", + "VFRAME_WW4B0" + ], + [ + "MONITOR_SE4BEG1_2", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_EE4A3_2", + "VFRAME_EE4A3" + ], + [ + "MONITOR_NE4BEG3_2", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_FAN1_2", + "VFRAME_FAN1" + ], + [ + "MONITOR_NW4END0_2", + "VFRAME_NW4END0" + ], + [ + "MONITOR_IMUX28_2", + "VFRAME_IMUX28" + ], + [ + "MONITOR_IMUX43_2", + "VFRAME_IMUX43" + ], + [ + "MONITOR_EE2A0_2", + "VFRAME_EE2A0" + ], + [ + "MONITOR_LOGIC_OUTS_B13_2", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "MONITOR_SW4A0_2", + "VFRAME_SW4A0" + ], + [ + "MONITOR_IMUX18_2", + "VFRAME_IMUX18" + ], + [ + "MONITOR_WW4A0_2", + "VFRAME_WW4A0" + ], + [ + "MONITOR_WW2A3_2", + "VFRAME_WW2A3" + ], + [ + "MONITOR_LOGIC_OUTS_B18_2", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "MONITOR_WW2END2_2", + "VFRAME_WW2END2" + ], + [ + "MONITOR_NE4BEG0_2", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_IMUX0_2", + "VFRAME_IMUX0" + ], + [ + "MONITOR_FAN0_2", + "VFRAME_FAN0" + ], + [ + "MONITOR_WW4C3_2", + "VFRAME_WW4C3" + ], + [ + "MONITOR_NW4A1_2", + "VFRAME_NW4A1" + ], + [ + "MONITOR_EE4A0_2", + "VFRAME_EE4A0" + ], + [ + "MONITOR_CTRL1_2", + "VFRAME_CTRL1" + ] + ], + "tile_types": [ + "MONITOR_BOT_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -5, + 0 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_0" + ], + [ + "INT_INTERFACE_LH5", + "PCIE_LH5_0" + ], + [ + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_0" + ], + [ + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_0" + ], + [ + "INT_INTERFACE_EE4C1", + "PCIE_EE4C1_0" + ], + [ + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "PCIE_LOGIC_OUTS_B14_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT44", + "PCIE_IMUX44_L_0" + ], + [ + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT42", + "PCIE_IMUX42_L_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "PCIE_LOGIC_OUTS_B17_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT9", + "PCIE_IMUX9_L_0" + ], + [ + "INT_INTERFACE_FAN5", + "PCIE_FAN5_L_0" + ], + [ + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_0" + ], + [ + "INT_INTERFACE_LH12", + "PCIE_LH12_0" + ], + [ + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_0" + ], + [ + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_0" + ], + [ + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT21", + "PCIE_IMUX21_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT23", + "PCIE_IMUX23_L_0" + ], + [ + "INT_INTERFACE_CLK0", + "PCIE_CLK0_L_0" + ], + [ + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_0" + ], + [ + "INT_INTERFACE_EE2BEG1", + "PCIE_EE2BEG1_0" + ], + [ + "INT_INTERFACE_EE2BEG3", + "PCIE_EE2BEG3_0" + ], + [ + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_0" + ], + [ + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_0" + ], + [ + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT40", + "PCIE_IMUX40_L_0" + ], + [ + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_0" + ], + [ + "INT_INTERFACE_LH8", + "PCIE_LH8_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT0", + "PCIE_IMUX0_L_0" + ], + [ + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_0" + ], + [ + "INT_INTERFACE_LH7", + "PCIE_LH7_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "PCIE_LOGIC_OUTS_B19_L_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "PCIE_LOGIC_OUTS_B23_L_0" + ], + [ + "INT_INTERFACE_FAN0", + "PCIE_FAN0_L_0" + ], + [ + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "PCIE_LOGIC_OUTS_B12_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT39", + "PCIE_IMUX39_L_0" + ], + [ + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_0" + ], + [ + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT47", + "PCIE_IMUX47_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT30", + "PCIE_IMUX30_L_0" + ], + [ + "INT_INTERFACE_EE2BEG2", + "PCIE_EE2BEG2_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT29", + "PCIE_IMUX29_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT13", + "PCIE_IMUX13_L_0" + ], + [ + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_0" + ], + [ + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT36", + "PCIE_IMUX36_L_0" + ], + [ + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_0" + ], + [ + "INT_INTERFACE_EE2A0", + "PCIE_EE2A0_0" + ], + [ + "INT_INTERFACE_CTRL1", + "PCIE_CTRL1_L_0" + ], + [ + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_0" + ], + [ + "INT_INTERFACE_BYP0", + "PCIE_BYP0_L_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "PCIE_LOGIC_OUTS_B22_L_0" + ], + [ + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT15", + "PCIE_IMUX15_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT16", + "PCIE_IMUX16_L_0" + ], + [ + "INT_INTERFACE_EE4C2", + "PCIE_EE4C2_0" + ], + [ + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_0" + ], + [ + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_0" + ], + [ + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_0" + ], + [ + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "PCIE_LOGIC_OUTS_B15_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT34", + "PCIE_IMUX34_L_0" + ], + [ + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_0" + ], + [ + "INT_INTERFACE_EL1BEG3", + "PCIE_EL1BEG3_0" + ], + [ + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT27", + "PCIE_IMUX27_L_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "PCIE_LOGIC_OUTS_B9_L_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "PCIE_LOGIC_OUTS_B21_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT2", + "PCIE_IMUX2_L_0" + ], + [ + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_0" + ], + [ + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_0" + ], + [ + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "PCIE_LOGIC_OUTS_B2_L_0" + ], + [ + "INT_INTERFACE_LH3", + "PCIE_LH3_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT26", + "PCIE_IMUX26_L_0" + ], + [ + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_0" + ], + [ + "INT_INTERFACE_EE2A1", + "PCIE_EE2A1_0" + ], + [ + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_0" + ], + [ + "INT_INTERFACE_BYP2", + "PCIE_BYP2_L_0" + ], + [ + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_0" + ], + [ + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT12", + "PCIE_IMUX12_L_0" + ], + [ + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT33", + "PCIE_IMUX33_L_0" + ], + [ + "INT_INTERFACE_LH6", + "PCIE_LH6_0" + ], + [ + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_0" + ], + [ + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_0" + ], + [ + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_0" + ], + [ + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_0" + ], + [ + "INT_INTERFACE_LH11", + "PCIE_LH11_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT35", + "PCIE_IMUX35_L_0" + ], + [ + "INT_INTERFACE_BYP6", + "PCIE_BYP6_L_0" + ], + [ + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_0" + ], + [ + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_0" + ], + [ + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_0" + ], + [ + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_0" + ], + [ + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT38", + "PCIE_IMUX38_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT4", + "PCIE_IMUX4_L_0" + ], + [ + "INT_INTERFACE_EE2A2", + "PCIE_EE2A2_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT37", + "PCIE_IMUX37_L_0" + ], + [ + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_0" + ], + [ + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT3", + "PCIE_IMUX3_L_0" + ], + [ + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "PCIE_LOGIC_OUTS_B8_L_0" + ], + [ + "INT_INTERFACE_BYP7", + "PCIE_BYP7_L_0" + ], + [ + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_0" + ], + [ + "INT_INTERFACE_LH10", + "PCIE_LH10_0" + ], + [ + "INT_INTERFACE_FAN2", + "PCIE_FAN2_L_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "PCIE_LOGIC_OUTS_B10_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT8", + "PCIE_IMUX8_L_0" + ], + [ + "INT_INTERFACE_FAN6", + "PCIE_FAN6_L_0" + ], + [ + "INT_INTERFACE_EE4A0", + "PCIE_EE4A0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT28", + "PCIE_IMUX28_L_0" + ], + [ + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "PCIE_LOGIC_OUTS_B7_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT14", + "PCIE_IMUX14_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT19", + "PCIE_IMUX19_L_0" + ], + [ + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_0" + ], + [ + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_0" + ], + [ + "INT_INTERFACE_EE4C0", + "PCIE_EE4C0_0" + ], + [ + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_0" + ], + [ + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_0" + ], + [ + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_0" + ], + [ + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_0" + ], + [ + "INT_INTERFACE_BYP5", + "PCIE_BYP5_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT5", + "PCIE_IMUX5_L_0" + ], + [ + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "PCIE_LOGIC_OUTS_B6_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT32", + "PCIE_IMUX32_L_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "PCIE_LOGIC_OUTS_B11_L_0" + ], + [ + "INT_INTERFACE_EE4A2", + "PCIE_EE4A2_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "PCIE_LOGIC_OUTS_B4_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT11", + "PCIE_IMUX11_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT6", + "PCIE_IMUX6_L_0" + ], + [ + "INT_INTERFACE_BYP1", + "PCIE_BYP1_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT43", + "PCIE_IMUX43_L_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "PCIE_LOGIC_OUTS_B13_L_0" + ], + [ + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_0" + ], + [ + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_0" + ], + [ + "INT_INTERFACE_FAN7", + "PCIE_FAN7_L_0" + ], + [ + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT20", + "PCIE_IMUX20_L_0" + ], + [ + "INT_INTERFACE_LH4", + "PCIE_LH4_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "PCIE_LOGIC_OUTS_B16_L_0" + ], + [ + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_0" + ], + [ + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_0" + ], + [ + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_0" + ], + [ + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "PCIE_LOGIC_OUTS_B3_L_0" + ], + [ + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_0" + ], + [ + "INT_INTERFACE_CTRL0", + "PCIE_CTRL0_L_0" + ], + [ + "INT_INTERFACE_CLK1", + "PCIE_CLK1_L_0" + ], + [ + "INT_INTERFACE_EE2BEG0", + "PCIE_EE2BEG0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "PCIE_LOGIC_OUTS_B18_L_0" + ], + [ + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_0" + ], + [ + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_0" + ], + [ + "INT_INTERFACE_BYP3", + "PCIE_BYP3_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT45", + "PCIE_IMUX45_L_0" + ], + [ + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_0" + ], + [ + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_0" + ], + [ + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_0" + ], + [ + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT1", + "PCIE_IMUX1_L_0" + ], + [ + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_0" + ], + [ + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_0" + ], + [ + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_0" + ], + [ + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "PCIE_LOGIC_OUTS_B1_L_0" + ], + [ + "INT_INTERFACE_LH1", + "PCIE_LH1_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT46", + "PCIE_IMUX46_L_0" + ], + [ + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT7", + "PCIE_IMUX7_L_0" + ], + [ + "INT_INTERFACE_BYP4", + "PCIE_BYP4_L_0" + ], + [ + "INT_INTERFACE_FAN1", + "PCIE_FAN1_L_0" + ], + [ + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_0" + ], + [ + "INT_INTERFACE_LH2", + "PCIE_LH2_0" + ], + [ + "INT_INTERFACE_EE4B0", + "PCIE_EE4B0_0" + ], + [ + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_0" + ], + [ + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_0" + ], + [ + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_0" + ], + [ + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "PCIE_LOGIC_OUTS_B0_L_0" + ], + [ + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_0" + ], + [ + "INT_INTERFACE_FAN4", + "PCIE_FAN4_L_0" + ], + [ + "INT_INTERFACE_EE4A1", + "PCIE_EE4A1_0" + ], + [ + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_0" + ], + [ + "INT_INTERFACE_EE2A3", + "PCIE_EE2A3_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT17", + "PCIE_IMUX17_L_0" + ], + [ + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_0" + ], + [ + "INT_INTERFACE_ER1BEG0", + "PCIE_ER1BEG0_0" + ], + [ + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "PCIE_LOGIC_OUTS_B5_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT22", + "PCIE_IMUX22_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT41", + "PCIE_IMUX41_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT24", + "PCIE_IMUX24_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT10", + "PCIE_IMUX10_L_0" + ], + [ + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_0" + ], + [ + "INT_INTERFACE_FAN3", + "PCIE_FAN3_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT31", + "PCIE_IMUX31_L_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT25", + "PCIE_IMUX25_L_0" + ], + [ + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_0" + ], + [ + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT18", + "PCIE_IMUX18_L_0" + ], + [ + "INT_INTERFACE_LH9", + "PCIE_LH9_0" + ], + [ + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_0" + ], + [ + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_0" + ], + [ + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_0" + ], + [ + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "PCIE_LOGIC_OUTS_B20_L_0" + ], + [ + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_0" + ], + [ + "INT_INTERFACE_EE4A3", + "PCIE_EE4A3_0" + ] + ], + "tile_types": [ + "PCIE_INT_INTERFACE_L", + "PCIE_TOP" + ] + }, + { + "grid_deltas": [ + -1, + -9 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4B0_9", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_EE4A1_9", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EE4BEG3_9", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WW2END0_9", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WW4C3_9", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE2BEG3_9", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NW2A3_9", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_EE4A0_9", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_SE4BEG3_9", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_NW4END2_9", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_EL1BEG1_9", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SW4A0_9", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_NE2A3_9", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_NE2A2_9", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_NE4BEG0_9", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_SW2A2_9", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_LH3_9", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SW4END3_9", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_WW4B1_9", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_EE4C3_9", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_NE4C1_9", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_EE2A1_9", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_NE4C3_9", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WW4A3_9", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_SW4A1_9", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_LH10_9", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WW2END2_9", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SE4BEG1_9", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_LH9_9", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_SE4BEG2_9", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_EE4B2_9", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE4B3_9", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NE4BEG1_9", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WR1END1_9", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_EL1BEG2_9", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_NW2A0_9", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_LH11_9", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EE2BEG1_9", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_SW2A1_9", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_LH1_9", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_LH2_9", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_SE2A2_9", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_ER1BEG2_9", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_LH5_9", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE2BEG0_9", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4B3_9", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_WR1END2_9", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_NE2A1_9", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NW4A3_9", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_SW2A3_9", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_WW4A0_9", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SE4C1_9", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_WW4B0_9", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_ER1BEG3_9", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_SE2A0_9", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SE4C2_9", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_NW4A2_9", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NE2A0_9", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_WW2END1_9", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE2A0_9", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_EE4C1_9", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EL1BEG3_9", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WL1END1_9", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_NW4A1_9", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WW2A0_9", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WW2END3_9", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_NE4C0_9", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_ER1BEG1_9", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SE4C3_9", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WL1END0_9", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SW2A0_9", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WR1END3_9", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE2BEG2_9", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_EE4A3_9", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE4BEG1_9", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_EE4A2_9", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_LH4_9", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE4C2_9", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_WW2A1_9", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WW4B2_9", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE4C0_9", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WW4A2_9", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WW4END3_9", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4END2_9", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_NW4END3_9", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_EE4BEG0_9", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WW2A2_9", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WW4C0_9", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NE4BEG2_9", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_NW2A2_9", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_LH8_9", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW2A3_9", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_NW4A0_9", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_LH6_9", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_EE4BEG2_9", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SW4A2_9", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_SE4BEG0_9", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_LH7_9", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4C2_9", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_WW4C1_9", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_LH12_9", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW4A1_9", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_SW4END1_9", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_NW4END0_9", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_ER1BEG0_9", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_WR1END0_9", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_EE4B1_9", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NE4C2_9", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_SE4C0_9", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_WW4END0_9", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_NW4END1_9", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_EL1BEG0_9", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE2A3_9", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NE4BEG3_9", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW4END1_9", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_SE2A3_9", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SW4A3_9", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE2A2_9", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_SW4END0_9", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_SW4END2_9", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WL1END3_9", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_NW2A1_9", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_WL1END2_9", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SE2A1_9", + "INT_FEEDTHRU_2_SE2A1" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_1" + ], + [ + "INT_INTERFACE_ER1BEG2", + "BRAM_ER1BEG2_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX44", + "BRAM_IMUX44_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_1" + ], + [ + "INT_INTERFACE_EE4A0", + "BRAM_EE4A0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX29", + "BRAM_IMUX29_1" + ], + [ + "INT_INTERFACE_SW4END0", + "BRAM_SW4END0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX27", + "BRAM_IMUX27_1" + ], + [ + "INT_INTERFACE_SW2A2", + "BRAM_SW2A2_1" + ], + [ + "INT_INTERFACE_CLK0", + "BRAM_CLK0_1" + ], + [ + "INT_INTERFACE_FAN6", + "BRAM_FAN6_1" + ], + [ + "INT_INTERFACE_EE4A1", + "BRAM_EE4A1_1" + ], + [ + "INT_INTERFACE_NW4A2", + "BRAM_NW4A2_1" + ], + [ + "INT_INTERFACE_WR1END1", + "BRAM_WR1END1_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX42", + "BRAM_IMUX42_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX14", + "BRAM_IMUX14_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_1" + ], + [ + "INT_INTERFACE_ER1BEG3", + "BRAM_ER1BEG3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX10", + "BRAM_IMUX10_UTURN_1" + ], + [ + "INT_INTERFACE_LH3", + "BRAM_LH3_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX31", + "BRAM_IMUX31_1" + ], + [ + "INT_INTERFACE_SE2A0", + "BRAM_SE2A0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX36", + "BRAM_IMUX36_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX38", + "BRAM_IMUX38_1" + ], + [ + "INT_INTERFACE_BYP0", + "BRAM_BYP0_1" + ], + [ + "INT_INTERFACE_NW4A1", + "BRAM_NW4A1_1" + ], + [ + "INT_INTERFACE_BYP1", + "BRAM_BYP1_1" + ], + [ + "INT_INTERFACE_WW4END0", + "BRAM_WW4END0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX33", + "BRAM_IMUX33_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX25", + "BRAM_IMUX25_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_1" + ], + [ + "INT_INTERFACE_FAN7", + "BRAM_FAN7_1" + ], + [ + "INT_INTERFACE_NE2A2", + "BRAM_NE2A2_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX23", + "BRAM_IMUX23_UTURN_1" + ], + [ + "INT_INTERFACE_NE2A1", + "BRAM_NE2A1_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_1" + ], + [ + "INT_INTERFACE_CLK1", + "BRAM_CLK1_1" + ], + [ + "INT_INTERFACE_EE2BEG2", + "BRAM_EE2BEG2_1" + ], + [ + "INT_INTERFACE_EE2A2", + "BRAM_EE2A2_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_1" + ], + [ + "INT_INTERFACE_WW4B1", + "BRAM_WW4B1_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX21", + "BRAM_IMUX21_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX5", + "BRAM_IMUX5_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX24", + "BRAM_IMUX24_1" + ], + [ + "INT_INTERFACE_WW4B0", + "BRAM_WW4B0_1" + ], + [ + "INT_INTERFACE_BYP4", + "BRAM_BYP4_1" + ], + [ + "INT_INTERFACE_SW4A2", + "BRAM_SW4A2_1" + ], + [ + "INT_INTERFACE_EE4C2", + "BRAM_EE4C2_1" + ], + [ + "INT_INTERFACE_EE4BEG2", + "BRAM_EE4BEG2_1" + ], + [ + "INT_INTERFACE_LH6", + "BRAM_LH6_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX7", + "BRAM_IMUX7_UTURN_1" + ], + [ + "INT_INTERFACE_EE4B2", + "BRAM_EE4B2_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX45", + "BRAM_IMUX45_UTURN_1" + ], + [ + "INT_INTERFACE_LH12", + "BRAM_LH12_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B0", + "BRAM_LOGIC_OUTS_B0_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX35", + "BRAM_IMUX35_UTURN_1" + ], + [ + "INT_INTERFACE_NE4BEG2", + "BRAM_NE4BEG2_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_1" + ], + [ + "INT_INTERFACE_EE4B3", + "BRAM_EE4B3_1" + ], + [ + "INT_INTERFACE_EE4A3", + "BRAM_EE4A3_1" + ], + [ + "INT_INTERFACE_FAN4", + "BRAM_FAN4_1" + ], + [ + "INT_INTERFACE_WW2A2", + "BRAM_WW2A2_1" + ], + [ + "INT_INTERFACE_FAN1", + "BRAM_FAN1_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX33", + "BRAM_IMUX33_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX37", + "BRAM_IMUX37_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX37", + "BRAM_IMUX37_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX24", + "BRAM_IMUX24_UTURN_1" + ], + [ + "INT_INTERFACE_NW2A0", + "BRAM_NW2A0_1" + ], + [ + "INT_INTERFACE_WR1END0", + "BRAM_WR1END0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_1" + ], + [ + "INT_INTERFACE_FAN5", + "BRAM_FAN5_1" + ], + [ + "INT_INTERFACE_NE2A3", + "BRAM_NE2A3_1" + ], + [ + "INT_INTERFACE_NE4C3", + "BRAM_NE4C3_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX26", + "BRAM_IMUX26_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B8", + "BRAM_LOGIC_OUTS_B8_1" + ], + [ + "INT_INTERFACE_WW2A1", + "BRAM_WW2A1_1" + ], + [ + "INT_INTERFACE_WR1END3", + "BRAM_WR1END3_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B19", + "BRAM_LOGIC_OUTS_B19_1" + ], + [ + "INT_INTERFACE_EE4C3", + "BRAM_EE4C3_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX30", + "BRAM_IMUX30_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX26", + "BRAM_IMUX26_UTURN_1" + ], + [ + "INT_INTERFACE_NE4BEG1", + "BRAM_NE4BEG1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B1", + "BRAM_LOGIC_OUTS_B1_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX19", + "BRAM_IMUX19_UTURN_1" + ], + [ + "INT_INTERFACE_SW2A1", + "BRAM_SW2A1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B11", + "BRAM_LOGIC_OUTS_B11_1" + ], + [ + "INT_INTERFACE_SE4BEG1", + "BRAM_SE4BEG1_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX43", + "BRAM_IMUX43_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX43", + "BRAM_IMUX43_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B13", + "BRAM_LOGIC_OUTS_B13_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B15", + "BRAM_LOGIC_OUTS_B15_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX15", + "BRAM_IMUX15_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX35", + "BRAM_IMUX35_1" + ], + [ + "INT_INTERFACE_BYP5", + "BRAM_BYP5_1" + ], + [ + "INT_INTERFACE_LH7", + "BRAM_LH7_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX0", + "BRAM_IMUX0_UTURN_1" + ], + [ + "INT_INTERFACE_LH9", + "BRAM_LH9_1" + ], + [ + "INT_INTERFACE_WW2END1", + "BRAM_WW2END1_1" + ], + [ + "INT_INTERFACE_SE2A1", + "BRAM_SE2A1_1" + ], + [ + "INT_INTERFACE_EL1BEG3", + "BRAM_EL1BEG3_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX21", + "BRAM_IMUX21_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX30", + "BRAM_IMUX30_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX6", + "BRAM_IMUX6_UTURN_1" + ], + [ + "INT_INTERFACE_SW4A1", + "BRAM_SW4A1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B18", + "BRAM_LOGIC_OUTS_B18_1" + ], + [ + "INT_INTERFACE_LH1", + "BRAM_LH1_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX2", + "BRAM_IMUX2_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX11", + "BRAM_IMUX11_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX16", + "BRAM_IMUX16_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX8", + "BRAM_IMUX8_UTURN_1" + ], + [ + "INT_INTERFACE_EE2A3", + "BRAM_EE2A3_1" + ], + [ + "INT_INTERFACE_WL1END1", + "BRAM_WL1END1_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX22", + "BRAM_IMUX22_UTURN_1" + ], + [ + "INT_INTERFACE_SE2A2", + "BRAM_SE2A2_1" + ], + [ + "INT_INTERFACE_FAN0", + "BRAM_FAN0_1" + ], + [ + "INT_INTERFACE_SE2A3", + "BRAM_SE2A3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX27", + "BRAM_IMUX27_UTURN_1" + ], + [ + "INT_INTERFACE_NW2A3", + "BRAM_NW2A3_1" + ], + [ + "INT_INTERFACE_NW2A2", + "BRAM_NW2A2_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX36", + "BRAM_IMUX36_UTURN_1" + ], + [ + "INT_INTERFACE_WW4C0", + "BRAM_WW4C0_1" + ], + [ + "INT_INTERFACE_EL1BEG1", + "BRAM_EL1BEG1_1" + ], + [ + "INT_INTERFACE_NE4BEG3", + "BRAM_NE4BEG3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX3", + "BRAM_IMUX3_UTURN_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B12", + "BRAM_LOGIC_OUTS_B12_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_1" + ], + [ + "INT_INTERFACE_SE4C2", + "BRAM_SE4C2_1" + ], + [ + "INT_INTERFACE_EL1BEG2", + "BRAM_EL1BEG2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B20", + "BRAM_LOGIC_OUTS_B20_1" + ], + [ + "INT_INTERFACE_NW2A1", + "BRAM_NW2A1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B23", + "BRAM_LOGIC_OUTS_B23_1" + ], + [ + "INT_INTERFACE_EE2A0", + "BRAM_EE2A0_1" + ], + [ + "INT_INTERFACE_CTRL0", + "BRAM_CTRL0_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX34", + "BRAM_IMUX34_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX47", + "BRAM_IMUX47_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_1" + ], + [ + "INT_INTERFACE_WL1END3", + "BRAM_WL1END3_1" + ], + [ + "INT_INTERFACE_WW2A0", + "BRAM_WW2A0_1" + ], + [ + "INT_INTERFACE_EE4B0", + "BRAM_EE4B0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX41", + "BRAM_IMUX41_1" + ], + [ + "INT_INTERFACE_WW2END3", + "BRAM_WW2END3_1" + ], + [ + "INT_INTERFACE_WW4C1", + "BRAM_WW4C1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B6", + "BRAM_LOGIC_OUTS_B6_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX1", + "BRAM_IMUX1_UTURN_1" + ], + [ + "INT_INTERFACE_SE4BEG3", + "BRAM_SE4BEG3_1" + ], + [ + "INT_INTERFACE_EE4BEG0", + "BRAM_EE4BEG0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B10", + "BRAM_LOGIC_OUTS_B10_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX20", + "BRAM_IMUX20_UTURN_1" + ], + [ + "INT_INTERFACE_WW4A1", + "BRAM_WW4A1_1" + ], + [ + "INT_INTERFACE_WW4END1", + "BRAM_WW4END1_1" + ], + [ + "INT_INTERFACE_SW2A3", + "BRAM_SW2A3_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B22", + "BRAM_LOGIC_OUTS_B22_1" + ], + [ + "INT_INTERFACE_SW4END1", + "BRAM_SW4END1_1" + ], + [ + "INT_INTERFACE_WW4A3", + "BRAM_WW4A3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX39", + "BRAM_IMUX39_UTURN_1" + ], + [ + "INT_INTERFACE_EE4C1", + "BRAM_EE4C1_1" + ], + [ + "INT_INTERFACE_WW2A3", + "BRAM_WW2A3_1" + ], + [ + "INT_INTERFACE_NE4C0", + "BRAM_NE4C0_1" + ], + [ + "INT_INTERFACE_EE4B1", + "BRAM_EE4B1_1" + ], + [ + "INT_INTERFACE_WW4END3", + "BRAM_WW4END3_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX44", + "BRAM_IMUX44_1" + ], + [ + "INT_INTERFACE_EE2A1", + "BRAM_EE2A1_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_1" + ], + [ + "INT_INTERFACE_NW4A0", + "BRAM_NW4A0_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B7", + "BRAM_LOGIC_OUTS_B7_1" + ], + [ + "INT_INTERFACE_BYP6", + "BRAM_BYP6_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B17", + "BRAM_LOGIC_OUTS_B17_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX32", + "BRAM_IMUX32_UTURN_1" + ], + [ + "INT_INTERFACE_SE4BEG2", + "BRAM_SE4BEG2_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX34", + "BRAM_IMUX34_1" + ], + [ + "INT_INTERFACE_EE4BEG3", + "BRAM_EE4BEG3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX38", + "BRAM_IMUX38_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX9", + "BRAM_IMUX9_UTURN_1" + ], + [ + "INT_INTERFACE_WW4B3", + "BRAM_WW4B3_1" + ], + [ + "INT_INTERFACE_SE4BEG0", + "BRAM_SE4BEG0_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B2", + "BRAM_LOGIC_OUTS_B2_1" + ], + [ + "INT_INTERFACE_NE4C1", + "BRAM_NE4C1_1" + ], + [ + "INT_INTERFACE_WR1END2", + "BRAM_WR1END2_1" + ], + [ + "INT_INTERFACE_SW2A0", + "BRAM_SW2A0_1" + ], + [ + "INT_INTERFACE_LH8", + "BRAM_LH8_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX42", + "BRAM_IMUX42_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX25", + "BRAM_IMUX25_UTURN_1" + ], + [ + "INT_INTERFACE_EE4C0", + "BRAM_EE4C0_1" + ], + [ + "INT_INTERFACE_SW4END3", + "BRAM_SW4END3_1" + ], + [ + "INT_INTERFACE_LH5", + "BRAM_LH5_1" + ], + [ + "INT_INTERFACE_ER1BEG1", + "BRAM_ER1BEG1_1" + ], + [ + "INT_INTERFACE_SW4A3", + "BRAM_SW4A3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX18", + "BRAM_IMUX18_UTURN_1" + ], + [ + "INT_INTERFACE_BYP7", + "BRAM_BYP7_1" + ], + [ + "INT_INTERFACE_NW4END0", + "BRAM_NW4END0_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B5", + "BRAM_LOGIC_OUTS_B5_1" + ], + [ + "INT_INTERFACE_WW4C3", + "BRAM_WW4C3_1" + ], + [ + "INT_INTERFACE_NE2A0", + "BRAM_NE2A0_1" + ], + [ + "INT_INTERFACE_NW4A3", + "BRAM_NW4A3_1" + ], + [ + "INT_INTERFACE_SE4C1", + "BRAM_SE4C1_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX46", + "BRAM_IMUX46_1" + ], + [ + "INT_INTERFACE_EE4BEG1", + "BRAM_EE4BEG1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B4", + "BRAM_LOGIC_OUTS_B4_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX23", + "BRAM_IMUX23_1" + ], + [ + "INT_INTERFACE_LH4", + "BRAM_LH4_1" + ], + [ + "INT_INTERFACE_WW2END0", + "BRAM_WW2END0_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX13", + "BRAM_IMUX13_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX46", + "BRAM_IMUX46_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX4", + "BRAM_IMUX4_UTURN_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B16", + "BRAM_LOGIC_OUTS_B16_1" + ], + [ + "INT_INTERFACE_LH11", + "BRAM_LH11_1" + ], + [ + "INT_INTERFACE_EE2BEG0", + "BRAM_EE2BEG0_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX41", + "BRAM_IMUX41_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_1" + ], + [ + "INT_INTERFACE_FAN3", + "BRAM_FAN3_1" + ], + [ + "INT_INTERFACE_EE2BEG1", + "BRAM_EE2BEG1_1" + ], + [ + "INT_INTERFACE_WW4B2", + "BRAM_WW4B2_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX40", + "BRAM_IMUX40_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX47", + "BRAM_IMUX47_1" + ], + [ + "INT_INTERFACE_NE4BEG0", + "BRAM_NE4BEG0_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX17", + "BRAM_IMUX17_UTURN_1" + ], + [ + "INT_INTERFACE_BYP3", + "BRAM_BYP3_1" + ], + [ + "INT_INTERFACE_MONITOR_N", + "BRAM_MONITOR_N_1" + ], + [ + "INT_INTERFACE_EE4A2", + "BRAM_EE4A2_1" + ], + [ + "INT_INTERFACE_FAN2", + "BRAM_FAN2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B14", + "BRAM_LOGIC_OUTS_B14_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX28", + "BRAM_IMUX28_1" + ], + [ + "INT_INTERFACE_WL1END0", + "BRAM_WL1END0_1" + ], + [ + "INT_INTERFACE_LH10", + "BRAM_LH10_1" + ], + [ + "INT_INTERFACE_SW4A0", + "BRAM_SW4A0_1" + ], + [ + "INT_INTERFACE_NW4END2", + "BRAM_NW4END2_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_1" + ], + [ + "INT_INTERFACE_EE2BEG3", + "BRAM_EE2BEG3_1" + ], + [ + "INT_INTERFACE_ER1BEG0", + "BRAM_ER1BEG0_1" + ], + [ + "INT_INTERFACE_EL1BEG0", + "BRAM_EL1BEG0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX22", + "BRAM_IMUX22_1" + ], + [ + "INT_INTERFACE_NW4END1", + "BRAM_NW4END1_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX28", + "BRAM_IMUX28_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX12", + "BRAM_IMUX12_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX39", + "BRAM_IMUX39_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX40", + "BRAM_IMUX40_1" + ], + [ + "INT_INTERFACE_BYP2", + "BRAM_BYP2_1" + ], + [ + "INT_INTERFACE_NE4C2", + "BRAM_NE4C2_1" + ], + [ + "INT_INTERFACE_WW4C2", + "BRAM_WW4C2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B3", + "BRAM_LOGIC_OUTS_B3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX31", + "BRAM_IMUX31_UTURN_1" + ], + [ + "INT_INTERFACE_WL1END2", + "BRAM_WL1END2_1" + ], + [ + "INT_INTERFACE_CTRL1", + "BRAM_CTRL1_1" + ], + [ + "INT_INTERFACE_SE4C0", + "BRAM_SE4C0_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B9", + "BRAM_LOGIC_OUTS_B9_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_1" + ], + [ + "INT_INTERFACE_WW4A2", + "BRAM_WW4A2_1" + ], + [ + "INT_INTERFACE_WW2END2", + "BRAM_WW2END2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B21", + "BRAM_LOGIC_OUTS_B21_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX45", + "BRAM_IMUX45_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX29", + "BRAM_IMUX29_UTURN_1" + ], + [ + "INT_INTERFACE_SE4C3", + "BRAM_SE4C3_1" + ], + [ + "INT_INTERFACE_LH2", + "BRAM_LH2_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX32", + "BRAM_IMUX32_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_1" + ], + [ + "INT_INTERFACE_SW4END2", + "BRAM_SW4END2_1" + ], + [ + "INT_INTERFACE_WW4A0", + "BRAM_WW4A0_1" + ], + [ + "INT_INTERFACE_WW4END2", + "BRAM_WW4END2_1" + ], + [ + "INT_INTERFACE_NW4END3", + "BRAM_NW4END3_1" + ], + [ + "INT_INTERFACE_MONITOR_P", + "BRAM_MONITOR_P_1" + ] + ], + "tile_types": [ + "BRAM_INT_INTERFACE_R", + "BRAM_R" + ] + }, + { + "grid_deltas": [ + 1, + -5 + ], + "wire_pairs": [ + [ + "MONITOR_IMUX46_5", + "VFRAME_IMUX46" + ], + [ + "MONITOR_FAN5_5", + "VFRAME_FAN5" + ], + [ + "MONITOR_SW4A1_5", + "VFRAME_SW4A1" + ], + [ + "MONITOR_WW4C2_5", + "VFRAME_WW4C2" + ], + [ + "MONITOR_LOGIC_OUTS_B10_5", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "MONITOR_IMUX31_5", + "VFRAME_IMUX31" + ], + [ + "MONITOR_IMUX26_5", + "VFRAME_IMUX26" + ], + [ + "MONITOR_EE4BEG1_5", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_ER1BEG3_5", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_WR1END1_5", + "VFRAME_WR1END1" + ], + [ + "MONITOR_NW2A2_5", + "VFRAME_NW2A2" + ], + [ + "MONITOR_EE4A1_5", + "VFRAME_EE4A1" + ], + [ + "MONITOR_SE2A3_5", + "VFRAME_SE2A3" + ], + [ + "MONITOR_EL1BEG3_5", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_CLK1_5", + "VFRAME_CLK1" + ], + [ + "MONITOR_WW4C0_5", + "VFRAME_WW4C0" + ], + [ + "MONITOR_BYP3_5", + "VFRAME_BYP3" + ], + [ + "MONITOR_EE4B3_5", + "VFRAME_EE4B3" + ], + [ + "MONITOR_NW4A1_5", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WW2END2_5", + "VFRAME_WW2END2" + ], + [ + "MONITOR_IMUX15_5", + "VFRAME_IMUX15" + ], + [ + "MONITOR_NW4A3_5", + "VFRAME_NW4A3" + ], + [ + "MONITOR_EE4B2_5", + "VFRAME_EE4B2" + ], + [ + "MONITOR_IMUX30_5", + "VFRAME_IMUX30" + ], + [ + "MONITOR_LOGIC_OUTS_B23_5", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "MONITOR_WW2A1_5", + "VFRAME_WW2A1" + ], + [ + "MONITOR_LOGIC_OUTS_B13_5", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "MONITOR_SE2A0_5", + "VFRAME_SE2A0" + ], + [ + "MONITOR_IMUX38_5", + "VFRAME_IMUX38" + ], + [ + "MONITOR_BYP1_5", + "VFRAME_BYP1" + ], + [ + "MONITOR_FAN6_5", + "VFRAME_FAN6" + ], + [ + "MONITOR_IMUX24_5", + "VFRAME_IMUX24" + ], + [ + "MONITOR_SW4A0_5", + "VFRAME_SW4A0" + ], + [ + "MONITOR_LOGIC_OUTS_B15_5", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "MONITOR_CLK0_5", + "VFRAME_CLK0" + ], + [ + "MONITOR_IMUX8_5", + "VFRAME_IMUX8" + ], + [ + "MONITOR_SW4END2_5", + "VFRAME_SW4END2" + ], + [ + "MONITOR_LH8_5", + "VFRAME_LH8" + ], + [ + "MONITOR_SE4C3_5", + "VFRAME_SE4C3" + ], + [ + "MONITOR_LH11_5", + "VFRAME_LH11" + ], + [ + "MONITOR_EE4A3_5", + "VFRAME_EE4A3" + ], + [ + "MONITOR_NW4END3_5", + "VFRAME_NW4END3" + ], + [ + "MONITOR_LOGIC_OUTS_B11_5", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "MONITOR_IMUX18_5", + "VFRAME_IMUX18" + ], + [ + "MONITOR_NE4BEG3_5", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_NE4C2_5", + "VFRAME_NE4C2" + ], + [ + "MONITOR_IMUX7_5", + "VFRAME_IMUX7" + ], + [ + "MONITOR_BYP6_5", + "VFRAME_BYP6" + ], + [ + "MONITOR_SE4C2_5", + "VFRAME_SE4C2" + ], + [ + "MONITOR_IMUX16_5", + "VFRAME_IMUX16" + ], + [ + "MONITOR_IMUX41_5", + "VFRAME_IMUX41" + ], + [ + "MONITOR_SW4END1_5", + "VFRAME_SW4END1" + ], + [ + "MONITOR_EE2BEG2_5", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_EE4C0_5", + "VFRAME_EE4C0" + ], + [ + "MONITOR_NE2A0_5", + "VFRAME_NE2A0" + ], + [ + "MONITOR_LOGIC_OUTS_B21_5", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "MONITOR_EL1BEG0_5", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_LH9_5", + "VFRAME_LH9" + ], + [ + "MONITOR_NE2A2_5", + "VFRAME_NE2A2" + ], + [ + "MONITOR_LOGIC_OUTS_B8_5", + "VFRAME_LOGIC_OUTS_B8" + ], + [ + "MONITOR_WW4B0_5", + "VFRAME_WW4B0" + ], + [ + "MONITOR_WR1END3_5", + "VFRAME_WR1END3" + ], + [ + "MONITOR_WW4END1_5", + "VFRAME_WW4END1" + ], + [ + "MONITOR_NW4END0_5", + "VFRAME_NW4END0" + ], + [ + "MONITOR_SE2A1_5", + "VFRAME_SE2A1" + ], + [ + "MONITOR_WW4B2_5", + "VFRAME_WW4B2" + ], + [ + "MONITOR_WW4A1_5", + "VFRAME_WW4A1" + ], + [ + "MONITOR_LOGIC_OUTS_B22_5", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "MONITOR_NW4END1_5", + "VFRAME_NW4END1" + ], + [ + "MONITOR_LH3_5", + "VFRAME_LH3" + ], + [ + "MONITOR_LOGIC_OUTS_B20_5", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "MONITOR_BYP2_5", + "VFRAME_BYP2" + ], + [ + "MONITOR_LOGIC_OUTS_B14_5", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "MONITOR_FAN0_5", + "VFRAME_FAN0" + ], + [ + "MONITOR_WR1END0_5", + "VFRAME_WR1END0" + ], + [ + "MONITOR_IMUX39_5", + "VFRAME_IMUX39" + ], + [ + "MONITOR_FAN3_5", + "VFRAME_FAN3" + ], + [ + "MONITOR_IMUX22_5", + "VFRAME_IMUX22" + ], + [ + "MONITOR_EE2BEG0_5", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_SW4A2_5", + "VFRAME_SW4A2" + ], + [ + "MONITOR_NW4A0_5", + "VFRAME_NW4A0" + ], + [ + "MONITOR_WW4B1_5", + "VFRAME_WW4B1" + ], + [ + "MONITOR_NE4C3_5", + "VFRAME_NE4C3" + ], + [ + "MONITOR_IMUX32_5", + "VFRAME_IMUX32" + ], + [ + "MONITOR_WW4A2_5", + "VFRAME_WW4A2" + ], + [ + "MONITOR_LH4_5", + "VFRAME_LH4" + ], + [ + "MONITOR_ER1BEG1_5", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_EE4C2_5", + "VFRAME_EE4C2" + ], + [ + "MONITOR_BYP0_5", + "VFRAME_BYP0" + ], + [ + "MONITOR_NE4C0_5", + "VFRAME_NE4C0" + ], + [ + "MONITOR_NE2A1_5", + "VFRAME_NE2A1" + ], + [ + "MONITOR_SW4END3_5", + "VFRAME_SW4END3" + ], + [ + "MONITOR_SE4BEG3_5", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_LH5_5", + "VFRAME_LH5" + ], + [ + "MONITOR_FAN7_5", + "VFRAME_FAN7" + ], + [ + "MONITOR_WW4END0_5", + "VFRAME_WW4END0" + ], + [ + "MONITOR_NW2A1_5", + "VFRAME_NW2A1" + ], + [ + "MONITOR_ER1BEG0_5", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_IMUX5_5", + "VFRAME_IMUX5" + ], + [ + "MONITOR_IMUX10_5", + "VFRAME_IMUX10" + ], + [ + "MONITOR_EE2A2_5", + "VFRAME_EE2A2" + ], + [ + "MONITOR_IMUX11_5", + "VFRAME_IMUX11" + ], + [ + "MONITOR_WL1END0_5", + "VFRAME_WL1END0" + ], + [ + "MONITOR_EE4BEG3_5", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_WW2END3_5", + "VFRAME_WW2END3" + ], + [ + "MONITOR_SE2A2_5", + "VFRAME_SE2A2" + ], + [ + "MONITOR_IMUX13_5", + "VFRAME_IMUX13" + ], + [ + "MONITOR_LOGIC_OUTS_B9_5", + "VFRAME_LOGIC_OUTS_B9" + ], + [ + "MONITOR_IMUX27_5", + "VFRAME_IMUX27" + ], + [ + "MONITOR_SE4BEG0_5", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_SW2A0_5", + "VFRAME_SW2A0" + ], + [ + "MONITOR_ER1BEG2_5", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_NW4END2_5", + "VFRAME_NW4END2" + ], + [ + "MONITOR_EE2BEG1_5", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_EE2A3_5", + "VFRAME_EE2A3" + ], + [ + "MONITOR_IMUX19_5", + "VFRAME_IMUX19" + ], + [ + "MONITOR_IMUX12_5", + "VFRAME_IMUX12" + ], + [ + "MONITOR_WL1END2_5", + "VFRAME_WL1END2" + ], + [ + "MONITOR_LOGIC_OUTS_B16_5", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "MONITOR_EE4B1_5", + "VFRAME_EE4B1" + ], + [ + "MONITOR_NE4BEG2_5", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_SW2A1_5", + "VFRAME_SW2A1" + ], + [ + "MONITOR_IMUX36_5", + "VFRAME_IMUX36" + ], + [ + "MONITOR_SE4BEG1_5", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_EE4BEG2_5", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_WW2END1_5", + "VFRAME_WW2END1" + ], + [ + "MONITOR_LOGIC_OUTS_B18_5", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "MONITOR_NE4C1_5", + "VFRAME_NE4C1" + ], + [ + "MONITOR_EE4C3_5", + "VFRAME_EE4C3" + ], + [ + "MONITOR_EE4B0_5", + "VFRAME_EE4B0" + ], + [ + "MONITOR_EE4C1_5", + "VFRAME_EE4C1" + ], + [ + "MONITOR_WL1END1_5", + "VFRAME_WL1END1" + ], + [ + "MONITOR_IMUX33_5", + "VFRAME_IMUX33" + ], + [ + "MONITOR_LH12_5", + "VFRAME_LH12" + ], + [ + "MONITOR_WW2A0_5", + "VFRAME_WW2A0" + ], + [ + "MONITOR_SE4C0_5", + "VFRAME_SE4C0" + ], + [ + "MONITOR_WW4END3_5", + "VFRAME_WW4END3" + ], + [ + "MONITOR_WW4C3_5", + "VFRAME_WW4C3" + ], + [ + "MONITOR_EE4A2_5", + "VFRAME_EE4A2" + ], + [ + "MONITOR_NW2A0_5", + "VFRAME_NW2A0" + ], + [ + "MONITOR_IMUX23_5", + "VFRAME_IMUX23" + ], + [ + "MONITOR_FAN2_5", + "VFRAME_FAN2" + ], + [ + "MONITOR_WW2A3_5", + "VFRAME_WW2A3" + ], + [ + "MONITOR_IMUX21_5", + "VFRAME_IMUX21" + ], + [ + "MONITOR_IMUX3_5", + "VFRAME_IMUX3" + ], + [ + "MONITOR_LH6_5", + "VFRAME_LH6" + ], + [ + "MONITOR_LH7_5", + "VFRAME_LH7" + ], + [ + "MONITOR_LH10_5", + "VFRAME_LH10" + ], + [ + "MONITOR_IMUX2_5", + "VFRAME_IMUX2" + ], + [ + "MONITOR_IMUX4_5", + "VFRAME_IMUX4" + ], + [ + "MONITOR_NW4A2_5", + "VFRAME_NW4A2" + ], + [ + "MONITOR_IMUX25_5", + "VFRAME_IMUX25" + ], + [ + "MONITOR_NE4BEG1_5", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_EE4A0_5", + "VFRAME_EE4A0" + ], + [ + "MONITOR_EE2A0_5", + "VFRAME_EE2A0" + ], + [ + "MONITOR_SE4BEG2_5", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_LOGIC_OUTS_B19_5", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "MONITOR_EE4BEG0_5", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_CTRL0_5", + "VFRAME_CTRL0" + ], + [ + "MONITOR_IMUX0_5", + "VFRAME_IMUX0" + ], + [ + "MONITOR_WW2END0_5", + "VFRAME_WW2END0" + ], + [ + "MONITOR_WR1END2_5", + "VFRAME_WR1END2" + ], + [ + "MONITOR_IMUX17_5", + "VFRAME_IMUX17" + ], + [ + "MONITOR_NW2A3_5", + "VFRAME_NW2A3" + ], + [ + "MONITOR_IMUX29_5", + "VFRAME_IMUX29" + ], + [ + "MONITOR_FAN1_5", + "VFRAME_FAN1" + ], + [ + "MONITOR_IMUX47_5", + "VFRAME_IMUX47" + ], + [ + "MONITOR_IMUX20_5", + "VFRAME_IMUX20" + ], + [ + "MONITOR_BYP7_5", + "VFRAME_BYP7" + ], + [ + "MONITOR_BYP5_5", + "VFRAME_BYP5" + ], + [ + "MONITOR_IMUX35_5", + "VFRAME_IMUX35" + ], + [ + "MONITOR_SE4C1_5", + "VFRAME_SE4C1" + ], + [ + "MONITOR_SW4A3_5", + "VFRAME_SW4A3" + ], + [ + "MONITOR_IMUX40_5", + "VFRAME_IMUX40" + ], + [ + "MONITOR_WW4END2_5", + "VFRAME_WW4END2" + ], + [ + "MONITOR_SW2A2_5", + "VFRAME_SW2A2" + ], + [ + "MONITOR_IMUX28_5", + "VFRAME_IMUX28" + ], + [ + "MONITOR_EL1BEG2_5", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_SW2A3_5", + "VFRAME_SW2A3" + ], + [ + "MONITOR_WW4A0_5", + "VFRAME_WW4A0" + ], + [ + "MONITOR_LH2_5", + "VFRAME_LH2" + ], + [ + "MONITOR_IMUX9_5", + "VFRAME_IMUX9" + ], + [ + "MONITOR_WL1END3_5", + "VFRAME_WL1END3" + ], + [ + "MONITOR_WW2A2_5", + "VFRAME_WW2A2" + ], + [ + "MONITOR_IMUX37_5", + "VFRAME_IMUX37" + ], + [ + "MONITOR_IMUX42_5", + "VFRAME_IMUX42" + ], + [ + "MONITOR_EL1BEG1_5", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_IMUX45_5", + "VFRAME_IMUX45" + ], + [ + "MONITOR_IMUX1_5", + "VFRAME_IMUX1" + ], + [ + "MONITOR_IMUX44_5", + "VFRAME_IMUX44" + ], + [ + "MONITOR_LH1_5", + "VFRAME_LH1" + ], + [ + "MONITOR_EE2A1_5", + "VFRAME_EE2A1" + ], + [ + "MONITOR_SW4END0_5", + "VFRAME_SW4END0" + ], + [ + "MONITOR_IMUX43_5", + "VFRAME_IMUX43" + ], + [ + "MONITOR_CTRL1_5", + "VFRAME_CTRL1" + ], + [ + "MONITOR_WW4C1_5", + "VFRAME_WW4C1" + ], + [ + "MONITOR_FAN4_5", + "VFRAME_FAN4" + ], + [ + "MONITOR_LOGIC_OUTS_B17_5", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "MONITOR_WW4B3_5", + "VFRAME_WW4B3" + ], + [ + "MONITOR_IMUX6_5", + "VFRAME_IMUX6" + ], + [ + "MONITOR_NE2A3_5", + "VFRAME_NE2A3" + ], + [ + "MONITOR_NE4BEG0_5", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_IMUX14_5", + "VFRAME_IMUX14" + ], + [ + "MONITOR_IMUX34_5", + "VFRAME_IMUX34" + ], + [ + "MONITOR_BYP4_5", + "VFRAME_BYP4" + ], + [ + "MONITOR_WW4A3_5", + "VFRAME_WW4A3" + ], + [ + "MONITOR_LOGIC_OUTS_B12_5", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "MONITOR_EE2BEG3_5", + "VFRAME_EE2BEG3" + ] + ], + "tile_types": [ + "MONITOR_BOT_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH3_4", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH4_4", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH12_4", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH11_4", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH9_4", + "VBRK_LH9" + ], + [ + "CMT_TOP_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH1_4", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_LH10_4", + "VBRK_LH10" + ], + [ + "CMT_TOP_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH2_4", + "VBRK_LH2" + ], + [ + "CMT_TOP_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_LH8_4", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH7_4", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_4", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH6_4", + "VBRK_LH6" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "CLBLM_L_COUT_N", + "HCLK_CLB_COUT1_L" + ], + [ + "CLBLM_M_COUT_N", + "HCLK_CLB_COUT0_L" + ] + ], + "tile_types": [ + "CLBLM_L", + "HCLK_CLB" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_2" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_2" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_2" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_2" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_2" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_2" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_2" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_2" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_2" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_2" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_2" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_2" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_2" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_2" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_2" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_2" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_2" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_2" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_2" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_2" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_2" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_2" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_2" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_2" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_2" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_2" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_2" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_2" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_2" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_2" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_2" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_2" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_2" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_2" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_2" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_2" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_2" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_2" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_2" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_2" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_2" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_2" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_2" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_2" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_2" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_2" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_2" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_2" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_2" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_2" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_2" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_2" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_2" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_2" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_2" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_2" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_2" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_2" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_2" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_2" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_2" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_2" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_2" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_2" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_2" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_2" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_2" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_2" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_2" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_2" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_2" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_2" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_2" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_2" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_2" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_2" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_2" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_2" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_2" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_2" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_2" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_2" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_2" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_2" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_2" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_2" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_2" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_2" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_2" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_2" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_2" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_2" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_2" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_2" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_2" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_2" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_2" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_2" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_2" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_2" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_2" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_2" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_2" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_2" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_2" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_2" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_2" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_2" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_2" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_2" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_2" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_2" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_2" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_2" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_2" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_2" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_2" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_2" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_2" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_2" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_MID_FUJI2" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_3" + ], + [ + "INT_INTERFACE_WW4END1", + "BRAM_WW4END1_3" + ], + [ + "INT_INTERFACE_LH10", + "BRAM_LH10_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "BRAM_LOGIC_OUTS_B11_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX27", + "BRAM_IMUX27_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX20", + "BRAM_IMUX20_UTURN_3" + ], + [ + "INT_INTERFACE_SW2A3", + "BRAM_SW2A3_3" + ], + [ + "INT_INTERFACE_WW4B2", + "BRAM_WW4B2_3" + ], + [ + "INT_INTERFACE_EE4A3", + "BRAM_EE4A3_3" + ], + [ + "INT_INTERFACE_ER1BEG0", + "BRAM_ER1BEG0_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX33", + "BRAM_IMUX33_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_3" + ], + [ + "INT_INTERFACE_EE4BEG3", + "BRAM_EE4BEG3_3" + ], + [ + "INT_INTERFACE_SE4BEG2", + "BRAM_SE4BEG2_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "BRAM_LOGIC_OUTS_B14_3" + ], + [ + "INT_INTERFACE_FAN3", + "BRAM_FAN3_3" + ], + [ + "INT_INTERFACE_LH1", + "BRAM_LH1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX2", + "BRAM_IMUX2_UTURN_3" + ], + [ + "INT_INTERFACE_EE4C2", + "BRAM_EE4C2_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX41", + "BRAM_IMUX41_3" + ], + [ + "INT_INTERFACE_NW4A0", + "BRAM_NW4A0_3" + ], + [ + "INT_INTERFACE_NE4BEG0", + "BRAM_NE4BEG0_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "BRAM_LOGIC_OUTS_B17_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX43", + "BRAM_IMUX43_UTURN_3" + ], + [ + "INT_INTERFACE_LH11", + "BRAM_LH11_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX44", + "BRAM_IMUX44_3" + ], + [ + "INT_INTERFACE_WR1END2", + "BRAM_WR1END2_3" + ], + [ + "INT_INTERFACE_EL1BEG0", + "BRAM_EL1BEG0_3" + ], + [ + "INT_INTERFACE_SE4C2", + "BRAM_SE4C2_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX15", + "BRAM_IMUX15_UTURN_3" + ], + [ + "INT_INTERFACE_FAN0", + "BRAM_FAN0_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX14", + "BRAM_IMUX14_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX25", + "BRAM_IMUX25_UTURN_3" + ], + [ + "INT_INTERFACE_WW4B1", + "BRAM_WW4B1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "BRAM_LOGIC_OUTS_B6_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_3" + ], + [ + "INT_INTERFACE_EE2A1", + "BRAM_EE2A1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX35", + "BRAM_IMUX35_UTURN_3" + ], + [ + "INT_INTERFACE_FAN2", + "BRAM_FAN2_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX22", + "BRAM_IMUX22_UTURN_3" + ], + [ + "INT_INTERFACE_WL1END2", + "BRAM_WL1END2_3" + ], + [ + "INT_INTERFACE_ER1BEG3", + "BRAM_ER1BEG3_3" + ], + [ + "INT_INTERFACE_EE4BEG2", + "BRAM_EE4BEG2_3" + ], + [ + "INT_INTERFACE_NW2A0", + "BRAM_NW2A0_3" + ], + [ + "INT_INTERFACE_BYP6", + "BRAM_BYP6_3" + ], + [ + "INT_INTERFACE_EE4B2", + "BRAM_EE4B2_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX19", + "BRAM_IMUX19_UTURN_3" + ], + [ + "INT_INTERFACE_NE2A1", + "BRAM_NE2A1_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX37", + "BRAM_IMUX37_3" + ], + [ + "INT_INTERFACE_SE2A3", + "BRAM_SE2A3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX26", + "BRAM_IMUX26_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_3" + ], + [ + "INT_INTERFACE_EE4B1", + "BRAM_EE4B1_3" + ], + [ + "INT_INTERFACE_NW2A3", + "BRAM_NW2A3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "BRAM_LOGIC_OUTS_B18_3" + ], + [ + "INT_INTERFACE_WW2END2", + "BRAM_WW2END2_3" + ], + [ + "INT_INTERFACE_WR1END1", + "BRAM_WR1END1_3" + ], + [ + "INT_INTERFACE_SE4BEG0", + "BRAM_SE4BEG0_3" + ], + [ + "INT_INTERFACE_WL1END0", + "BRAM_WL1END0_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX42", + "BRAM_IMUX42_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX29", + "BRAM_IMUX29_UTURN_3" + ], + [ + "INT_INTERFACE_EE2A3", + "BRAM_EE2A3_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX13", + "BRAM_IMUX13_UTURN_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "BRAM_LOGIC_OUTS_B7_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX1", + "BRAM_IMUX1_UTURN_3" + ], + [ + "INT_INTERFACE_SE2A2", + "BRAM_SE2A2_3" + ], + [ + "INT_INTERFACE_CTRL1", + "BRAM_CTRL1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX4", + "BRAM_IMUX4_UTURN_3" + ], + [ + "INT_INTERFACE_EE4C0", + "BRAM_EE4C0_3" + ], + [ + "INT_INTERFACE_WW4END0", + "BRAM_WW4END0_3" + ], + [ + "INT_INTERFACE_SW4END0", + "BRAM_SW4END0_3" + ], + [ + "INT_INTERFACE_SW4END3", + "BRAM_SW4END3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX43", + "BRAM_IMUX43_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX22", + "BRAM_IMUX22_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX17", + "BRAM_IMUX17_UTURN_3" + ], + [ + "INT_INTERFACE_LH8", + "BRAM_LH8_3" + ], + [ + "INT_INTERFACE_NE4BEG1", + "BRAM_NE4BEG1_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_3" + ], + [ + "INT_INTERFACE_SE4C3", + "BRAM_SE4C3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX25", + "BRAM_IMUX25_3" + ], + [ + "INT_INTERFACE_BYP7", + "BRAM_BYP7_3" + ], + [ + "INT_INTERFACE_WW4A2", + "BRAM_WW4A2_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX21", + "BRAM_IMUX21_3" + ], + [ + "INT_INTERFACE_FAN1", + "BRAM_FAN1_3" + ], + [ + "INT_INTERFACE_NE4C0", + "BRAM_NE4C0_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX0", + "BRAM_IMUX0_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX31", + "BRAM_IMUX31_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_3" + ], + [ + "INT_INTERFACE_EE4B0", + "BRAM_EE4B0_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX45", + "BRAM_IMUX45_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "BRAM_LOGIC_OUTS_B15_3" + ], + [ + "INT_INTERFACE_WW4B0", + "BRAM_WW4B0_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "BRAM_LOGIC_OUTS_B1_3" + ], + [ + "INT_INTERFACE_NE4BEG3", + "BRAM_NE4BEG3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_3" + ], + [ + "INT_INTERFACE_NW4END1", + "BRAM_NW4END1_3" + ], + [ + "INT_INTERFACE_NW4A3", + "BRAM_NW4A3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX29", + "BRAM_IMUX29_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX40", + "BRAM_IMUX40_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX5", + "BRAM_IMUX5_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX6", + "BRAM_IMUX6_UTURN_3" + ], + [ + "INT_INTERFACE_WW4A0", + "BRAM_WW4A0_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "BRAM_LOGIC_OUTS_B19_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX27", + "BRAM_IMUX27_UTURN_3" + ], + [ + "INT_INTERFACE_EE2A0", + "BRAM_EE2A0_3" + ], + [ + "INT_INTERFACE_WW2A2", + "BRAM_WW2A2_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "BRAM_LOGIC_OUTS_B21_3" + ], + [ + "INT_INTERFACE_EE4B3", + "BRAM_EE4B3_3" + ], + [ + "INT_INTERFACE_NE2A3", + "BRAM_NE2A3_3" + ], + [ + "INT_INTERFACE_EE4A1", + "BRAM_EE4A1_3" + ], + [ + "INT_INTERFACE_SW4A1", + "BRAM_SW4A1_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX10", + "BRAM_IMUX10_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX3", + "BRAM_IMUX3_UTURN_3" + ], + [ + "INT_INTERFACE_EL1BEG3", + "BRAM_EL1BEG3_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX8", + "BRAM_IMUX8_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_3" + ], + [ + "INT_INTERFACE_NW2A1", + "BRAM_NW2A1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "BRAM_LOGIC_OUTS_B8_3" + ], + [ + "INT_INTERFACE_SW4A2", + "BRAM_SW4A2_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX47", + "BRAM_IMUX47_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_3" + ], + [ + "INT_INTERFACE_BYP3", + "BRAM_BYP3_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX42", + "BRAM_IMUX42_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX45", + "BRAM_IMUX45_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_3" + ], + [ + "INT_INTERFACE_FAN6", + "BRAM_FAN6_3" + ], + [ + "INT_INTERFACE_EE2BEG3", + "BRAM_EE2BEG3_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX40", + "BRAM_IMUX40_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX46", + "BRAM_IMUX46_UTURN_3" + ], + [ + "INT_INTERFACE_NE4C3", + "BRAM_NE4C3_3" + ], + [ + "INT_INTERFACE_NE4C1", + "BRAM_NE4C1_3" + ], + [ + "INT_INTERFACE_EE4BEG1", + "BRAM_EE4BEG1_3" + ], + [ + "INT_INTERFACE_SE2A1", + "BRAM_SE2A1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "BRAM_LOGIC_OUTS_B13_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX35", + "BRAM_IMUX35_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX47", + "BRAM_IMUX47_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX24", + "BRAM_IMUX24_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX9", + "BRAM_IMUX9_UTURN_3" + ], + [ + "INT_INTERFACE_WW4A3", + "BRAM_WW4A3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "BRAM_LOGIC_OUTS_B5_3" + ], + [ + "INT_INTERFACE_SW4END2", + "BRAM_SW4END2_3" + ], + [ + "INT_INTERFACE_NW4END0", + "BRAM_NW4END0_3" + ], + [ + "INT_INTERFACE_WW4A1", + "BRAM_WW4A1_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_3" + ], + [ + "INT_INTERFACE_WW4END3", + "BRAM_WW4END3_3" + ], + [ + "INT_INTERFACE_SW2A0", + "BRAM_SW2A0_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX44", + "BRAM_IMUX44_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX34", + "BRAM_IMUX34_UTURN_3" + ], + [ + "INT_INTERFACE_SE4C1", + "BRAM_SE4C1_3" + ], + [ + "INT_INTERFACE_WW2A3", + "BRAM_WW2A3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX36", + "BRAM_IMUX36_3" + ], + [ + "INT_INTERFACE_WW4C1", + "BRAM_WW4C1_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX23", + "BRAM_IMUX23_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX37", + "BRAM_IMUX37_UTURN_3" + ], + [ + "INT_INTERFACE_EE4C1", + "BRAM_EE4C1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "BRAM_LOGIC_OUTS_B4_3" + ], + [ + "INT_INTERFACE_SE4C0", + "BRAM_SE4C0_3" + ], + [ + "INT_INTERFACE_BYP2", + "BRAM_BYP2_3" + ], + [ + "INT_INTERFACE_LH4", + "BRAM_LH4_3" + ], + [ + "INT_INTERFACE_FAN7", + "BRAM_FAN7_3" + ], + [ + "INT_INTERFACE_CLK1", + "BRAM_CLK1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "BRAM_LOGIC_OUTS_B10_3" + ], + [ + "INT_INTERFACE_SE4BEG1", + "BRAM_SE4BEG1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX11", + "BRAM_IMUX11_UTURN_3" + ], + [ + "INT_INTERFACE_EE4BEG0", + "BRAM_EE4BEG0_3" + ], + [ + "INT_INTERFACE_WL1END1", + "BRAM_WL1END1_3" + ], + [ + "INT_INTERFACE_CTRL0", + "BRAM_CTRL0_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX33", + "BRAM_IMUX33_3" + ], + [ + "INT_INTERFACE_LH3", + "BRAM_LH3_3" + ], + [ + "INT_INTERFACE_WW4C3", + "BRAM_WW4C3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_3" + ], + [ + "INT_INTERFACE_NW4A2", + "BRAM_NW4A2_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX16", + "BRAM_IMUX16_UTURN_3" + ], + [ + "INT_INTERFACE_NE4BEG2", + "BRAM_NE4BEG2_3" + ], + [ + "INT_INTERFACE_MONITOR_N", + "BRAM_MONITOR_N_3" + ], + [ + "INT_INTERFACE_EL1BEG1", + "BRAM_EL1BEG1_3" + ], + [ + "INT_INTERFACE_NE2A2", + "BRAM_NE2A2_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX39", + "BRAM_IMUX39_3" + ], + [ + "INT_INTERFACE_SW2A1", + "BRAM_SW2A1_3" + ], + [ + "INT_INTERFACE_LH5", + "BRAM_LH5_3" + ], + [ + "INT_INTERFACE_SW4END1", + "BRAM_SW4END1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX24", + "BRAM_IMUX24_UTURN_3" + ], + [ + "INT_INTERFACE_EE4A0", + "BRAM_EE4A0_3" + ], + [ + "INT_INTERFACE_WW2END1", + "BRAM_WW2END1_3" + ], + [ + "INT_INTERFACE_WR1END3", + "BRAM_WR1END3_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX41", + "BRAM_IMUX41_UTURN_3" + ], + [ + "INT_INTERFACE_SW2A2", + "BRAM_SW2A2_3" + ], + [ + "INT_INTERFACE_NW4END2", + "BRAM_NW4END2_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX34", + "BRAM_IMUX34_3" + ], + [ + "INT_INTERFACE_ER1BEG1", + "BRAM_ER1BEG1_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX46", + "BRAM_IMUX46_3" + ], + [ + "INT_INTERFACE_WW4B3", + "BRAM_WW4B3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "BRAM_LOGIC_OUTS_B3_3" + ], + [ + "INT_INTERFACE_FAN4", + "BRAM_FAN4_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX30", + "BRAM_IMUX30_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX36", + "BRAM_IMUX36_UTURN_3" + ], + [ + "INT_INTERFACE_LH7", + "BRAM_LH7_3" + ], + [ + "INT_INTERFACE_BYP5", + "BRAM_BYP5_3" + ], + [ + "INT_INTERFACE_EE2BEG2", + "BRAM_EE2BEG2_3" + ], + [ + "INT_INTERFACE_EL1BEG2", + "BRAM_EL1BEG2_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX21", + "BRAM_IMUX21_UTURN_3" + ], + [ + "INT_INTERFACE_WR1END0", + "BRAM_WR1END0_3" + ], + [ + "INT_INTERFACE_MONITOR_P", + "BRAM_MONITOR_P_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "BRAM_LOGIC_OUTS_B23_3" + ], + [ + "INT_INTERFACE_WL1END3", + "BRAM_WL1END3_3" + ], + [ + "INT_INTERFACE_SW4A3", + "BRAM_SW4A3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "BRAM_LOGIC_OUTS_B2_3" + ], + [ + "INT_INTERFACE_SE4BEG3", + "BRAM_SE4BEG3_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX38", + "BRAM_IMUX38_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX23", + "BRAM_IMUX23_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_3" + ], + [ + "INT_INTERFACE_WW4END2", + "BRAM_WW4END2_3" + ], + [ + "INT_INTERFACE_CLK0", + "BRAM_CLK0_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX32", + "BRAM_IMUX32_3" + ], + [ + "INT_INTERFACE_EE2A2", + "BRAM_EE2A2_3" + ], + [ + "INT_INTERFACE_NE2A0", + "BRAM_NE2A0_3" + ], + [ + "INT_INTERFACE_WW4C2", + "BRAM_WW4C2_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "BRAM_LOGIC_OUTS_B16_3" + ], + [ + "INT_INTERFACE_SE2A0", + "BRAM_SE2A0_3" + ], + [ + "INT_INTERFACE_LH2", + "BRAM_LH2_3" + ], + [ + "INT_INTERFACE_SW4A0", + "BRAM_SW4A0_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "BRAM_LOGIC_OUTS_B12_3" + ], + [ + "INT_INTERFACE_EE2BEG0", + "BRAM_EE2BEG0_3" + ], + [ + "INT_INTERFACE_EE2BEG1", + "BRAM_EE2BEG1_3" + ], + [ + "INT_INTERFACE_EE4C3", + "BRAM_EE4C3_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX7", + "BRAM_IMUX7_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX32", + "BRAM_IMUX32_UTURN_3" + ], + [ + "INT_INTERFACE_LH9", + "BRAM_LH9_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX31", + "BRAM_IMUX31_3" + ], + [ + "INT_INTERFACE_WW2END3", + "BRAM_WW2END3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "BRAM_LOGIC_OUTS_B20_3" + ], + [ + "INT_INTERFACE_NE4C2", + "BRAM_NE4C2_3" + ], + [ + "INT_INTERFACE_LH6", + "BRAM_LH6_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_3" + ], + [ + "INT_INTERFACE_WW2A1", + "BRAM_WW2A1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX18", + "BRAM_IMUX18_UTURN_3" + ], + [ + "INT_INTERFACE_NW4END3", + "BRAM_NW4END3_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX30", + "BRAM_IMUX30_UTURN_3" + ], + [ + "INT_INTERFACE_BYP1", + "BRAM_BYP1_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX39", + "BRAM_IMUX39_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX26", + "BRAM_IMUX26_UTURN_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "BRAM_LOGIC_OUTS_B22_3" + ], + [ + "INT_INTERFACE_ER1BEG2", + "BRAM_ER1BEG2_3" + ], + [ + "INT_INTERFACE_WW2A0", + "BRAM_WW2A0_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX12", + "BRAM_IMUX12_UTURN_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_3" + ], + [ + "INT_INTERFACE_NW4A1", + "BRAM_NW4A1_3" + ], + [ + "INT_INTERFACE_WW4C0", + "BRAM_WW4C0_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_3" + ], + [ + "INT_INTERFACE_WW2END0", + "BRAM_WW2END0_3" + ], + [ + "INT_INTERFACE_FAN5", + "BRAM_FAN5_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_3" + ], + [ + "INT_INTERFACE_LH12", + "BRAM_LH12_3" + ], + [ + "INT_INTERFACE_BRAM_IMUX28", + "BRAM_IMUX28_3" + ], + [ + "INT_INTERFACE_BYP0", + "BRAM_BYP0_3" + ], + [ + "INT_INTERFACE_BYP4", + "BRAM_BYP4_3" + ], + [ + "INT_INTERFACE_NW2A2", + "BRAM_NW2A2_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "BRAM_LOGIC_OUTS_B9_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX38", + "BRAM_IMUX38_UTURN_3" + ], + [ + "INT_INTERFACE_EE4A2", + "BRAM_EE4A2_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "BRAM_LOGIC_OUTS_B0_3" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX28", + "BRAM_IMUX28_UTURN_3" + ] + ], + "tile_types": [ + "BRAM_INT_INTERFACE_L", + "BRAM_L" + ] + }, + { + "grid_deltas": [ + 0, + 5 + ], + "wire_pairs": [ + [ + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "BRAM_CASCOUT_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "BRAM_CASCOUT_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "BRAM_CASCOUT_ADDRBWRADDRU9" + ], + [ + "BRAM_FIFO36_CASCADEINA", + "BRAM_FIFO36_CASCADEOUTA_1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU3", + "BRAM_CASCOUT_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU14", + "BRAM_CASCOUT_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "BRAM_CASCOUT_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU7", + "BRAM_CASCOUT_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "BRAM_CASCOUT_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU2", + "BRAM_CASCOUT_ADDRARDADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU5", + "BRAM_CASCOUT_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "BRAM_CASCOUT_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "BRAM_CASCOUT_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "BRAM_CASCOUT_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU1", + "BRAM_CASCOUT_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU6", + "BRAM_CASCOUT_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "BRAM_CASCOUT_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "BRAM_CASCOUT_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "BRAM_CASCOUT_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "BRAM_CASCOUT_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU9", + "BRAM_CASCOUT_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU4", + "BRAM_CASCOUT_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "BRAM_CASCOUT_ADDRBWRADDRU12" + ], + [ + "BRAM_FIFO36_CASCADEINB", + "BRAM_FIFO36_CASCADEOUTB_1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU12", + "BRAM_CASCOUT_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU8", + "BRAM_CASCOUT_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU13", + "BRAM_CASCOUT_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "BRAM_CASCOUT_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU10", + "BRAM_CASCOUT_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU0", + "BRAM_CASCOUT_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "BRAM_CASCOUT_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU11", + "BRAM_CASCOUT_ADDRARDADDRU11" + ] + ], + "tile_types": [ + "BRAM_L", + "BRAM_L" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_IMUX11_9", + "CMT_TOP_IMUX11_6" + ], + [ + "CMT_FIFO_SE2A3_6", + "CMT_TOP_SE2A3_3" + ], + [ + "CMT_FIFO_SW2A2_11", + "CMT_TOP_SW2A2_8" + ], + [ + "CMT_FIFO_ER1BEG2_6", + "CMT_TOP_ER1BEG2_3" + ], + [ + "CMT_FIFO_WR1END0_6", + "CMT_TOP_WR1END0_3" + ], + [ + "CMT_FIFO_NE4BEG2_9", + "CMT_TOP_NE4BEG2_6" + ], + [ + "CMT_FIFO_SE2A3_8", + "CMT_TOP_SE2A3_5" + ], + [ + "CMT_FIFO_WR1END0_10", + "CMT_TOP_WR1END0_7" + ], + [ + "CMT_FIFO_SE4C1_9", + "CMT_TOP_SE4C1_6" + ], + [ + "CMT_FIFO_NW4A0_11", + "CMT_TOP_NW4A0_8" + ], + [ + "CMT_FIFO_NW4END2_5", + "CMT_TOP_NW4END2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_4", + "CMT_TOP_LOGIC_OUTS_L_B1_1" + ], + [ + "CMT_FIFO_EE2A1_8", + "CMT_TOP_EE2A1_5" + ], + [ + "CMT_FIFO_EE2BEG3_10", + "CMT_TOP_EE2BEG3_7" + ], + [ + "CMT_FIFO_NE4BEG2_4", + "CMT_TOP_NE4BEG2_1" + ], + [ + "CMT_FIFO_L_IMUX31_6", + "CMT_TOP_IMUX31_3" + ], + [ + "CMT_FIFO_NW4END3_11", + "CMT_TOP_NW4END3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_10", + "CMT_TOP_LOGIC_OUTS_L_B14_7" + ], + [ + "CMT_FIFO_L_IMUX2_9", + "CMT_TOP_IMUX2_6" + ], + [ + "CMT_FIFO_L_FAN2_5", + "CMT_TOP_FAN2_2" + ], + [ + "CMT_FIFO_L_BYP4_4", + "CMT_TOP_BYP4_1" + ], + [ + "CMT_FIFO_WW2END3_5", + "CMT_TOP_WW2END3_2" + ], + [ + "CMT_FIFO_LH11_5", + "CMT_TOP_LH11_2" + ], + [ + "CMT_FIFO_L_IMUX6_8", + "CMT_TOP_IMUX6_5" + ], + [ + "CMT_FIFO_SE4BEG0_4", + "CMT_TOP_SE4BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_9", + "CMT_TOP_LOGIC_OUTS_L_B22_6" + ], + [ + "CMT_FIFO_LH1_4", + "CMT_TOP_LH1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_3", + "CMT_TOP_LOGIC_OUTS_L_B18_0" + ], + [ + "CMT_FIFO_SW4A0_9", + "CMT_TOP_SW4A0_6" + ], + [ + "CMT_FIFO_L_IMUX40_11", + "CMT_TOP_IMUX40_8" + ], + [ + "CMT_FIFO_L_IMUX9_11", + "CMT_TOP_IMUX9_8" + ], + [ + "CMT_FIFO_EE2A1_9", + "CMT_TOP_EE2A1_6" + ], + [ + "CMT_FIFO_WW4END1_8", + "CMT_TOP_WW4END1_5" + ], + [ + "CMT_FIFO_NW2A3_4", + "CMT_TOP_NW2A3_1" + ], + [ + "CMT_FIFO_SW2A1_4", + "CMT_TOP_SW2A1_1" + ], + [ + "CMT_FIFO_WR1END1_10", + "CMT_TOP_WR1END1_7" + ], + [ + "CMT_FIFO_L_IMUX29_8", + "CMT_TOP_IMUX29_5" + ], + [ + "CMT_FIFO_WW4B0_4", + "CMT_TOP_WW4B0_1" + ], + [ + "CMT_FIFO_L_IMUX14_3", + "CMT_TOP_IMUX14_0" + ], + [ + "CMT_FIFO_L_FAN4_4", + "CMT_TOP_FAN4_1" + ], + [ + "CMT_FIFO_L_IMUX12_3", + "CMT_TOP_IMUX12_0" + ], + [ + "CMT_FIFO_SE4C1_7", + "CMT_TOP_SE4C1_4" + ], + [ + "CMT_FIFO_L_IMUX41_7", + "CMT_TOP_IMUX41_4" + ], + [ + "CMT_FIFO_EE4B2_3", + "CMT_TOP_EE4B2_0" + ], + [ + "CMT_FIFO_SW4A0_10", + "CMT_TOP_SW4A0_7" + ], + [ + "CMT_FIFO_NE4BEG2_7", + "CMT_TOP_NE4BEG2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_11", + "CMT_TOP_LOGIC_OUTS_L_B1_8" + ], + [ + "CMT_FIFO_LH4_10", + "CMT_TOP_LH4_7" + ], + [ + "CMT_FIFO_EE2A3_9", + "CMT_TOP_EE2A3_6" + ], + [ + "CMT_FIFO_SE4BEG3_5", + "CMT_TOP_SE4BEG3_2" + ], + [ + "CMT_FIFO_NW4A0_5", + "CMT_TOP_NW4A0_2" + ], + [ + "CMT_FIFO_WW4A2_11", + "CMT_TOP_WW4A2_8" + ], + [ + "CMT_FIFO_WW4B0_9", + "CMT_TOP_WW4B0_6" + ], + [ + "CMT_FIFO_EE4BEG0_4", + "CMT_TOP_EE4BEG0_1" + ], + [ + "CMT_FIFO_EL1BEG1_4", + "CMT_TOP_EL1BEG1_1" + ], + [ + "CMT_FIFO_MONITOR_N_6", + "CMT_TOP_MONITOR_N_3" + ], + [ + "CMT_FIFO_L_IMUX27_7", + "CMT_TOP_IMUX27_4" + ], + [ + "CMT_FIFO_SE4C2_10", + "CMT_TOP_SE4C2_7" + ], + [ + "CMT_FIFO_L_IMUX17_9", + "CMT_TOP_IMUX17_6" + ], + [ + "CMT_FIFO_EE4C2_7", + "CMT_TOP_EE4C2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_6", + "CMT_TOP_LOGIC_OUTS_L_B7_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_8", + "CMT_TOP_LOGIC_OUTS_L_B7_5" + ], + [ + "CMT_FIFO_WL1END0_10", + "CMT_TOP_WL1END0_7" + ], + [ + "CMT_FIFO_EE2BEG2_3", + "CMT_TOP_EE2BEG2_0" + ], + [ + "CMT_FIFO_WW4B0_10", + "CMT_TOP_WW4B0_7" + ], + [ + "CMT_FIFO_L_IMUX24_3", + "CMT_TOP_IMUX24_0" + ], + [ + "CMT_FIFO_NE4BEG2_8", + "CMT_TOP_NE4BEG2_5" + ], + [ + "CMT_FIFO_EE2A0_9", + "CMT_TOP_EE2A0_6" + ], + [ + "CMT_FIFO_L_IMUX22_8", + "CMT_TOP_IMUX22_5" + ], + [ + "CMT_FIFO_EE2A3_10", + "CMT_TOP_EE2A3_7" + ], + [ + "CMT_FIFO_WW4B0_8", + "CMT_TOP_WW4B0_5" + ], + [ + "CMT_FIFO_LH11_4", + "CMT_TOP_LH11_1" + ], + [ + "CMT_FIFO_SE4C0_3", + "CMT_TOP_SE4C0_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "CMT_TOP_ICLK_4" + ], + [ + "CMT_FIFO_L_BYP2_10", + "CMT_TOP_BYP2_7" + ], + [ + "CMT_FIFO_L_IMUX39_4", + "CMT_TOP_IMUX39_1" + ], + [ + "CMT_FIFO_WW4C3_10", + "CMT_TOP_WW4C3_7" + ], + [ + "CMT_FIFO_SE2A1_8", + "CMT_TOP_SE2A1_5" + ], + [ + "CMT_FIFO_L_BYP3_7", + "CMT_TOP_BYP3_4" + ], + [ + "CMT_FIFO_L_BYP7_5", + "CMT_TOP_BYP7_2" + ], + [ + "CMT_FIFO_L_IMUX14_6", + "CMT_TOP_IMUX14_3" + ], + [ + "CMT_FIFO_EE4BEG3_6", + "CMT_TOP_EE4BEG3_3" + ], + [ + "CMT_FIFO_WW2END2_6", + "CMT_TOP_WW2END2_3" + ], + [ + "CMT_FIFO_L_BYP2_8", + "CMT_TOP_BYP2_5" + ], + [ + "CMT_FIFO_WR1END3_4", + "CMT_TOP_WR1END3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_9", + "CMT_TOP_LOGIC_OUTS_L_B1_6" + ], + [ + "CMT_FIFO_NE4BEG3_6", + "CMT_TOP_NE4BEG3_3" + ], + [ + "CMT_FIFO_EE2A2_11", + "CMT_TOP_EE2A2_8" + ], + [ + "CMT_FIFO_WW2END2_9", + "CMT_TOP_WW2END2_6" + ], + [ + "CMT_FIFO_L_IMUX40_4", + "CMT_TOP_IMUX40_1" + ], + [ + "CMT_FIFO_SE4BEG0_8", + "CMT_TOP_SE4BEG0_5" + ], + [ + "CMT_FIFO_L_IMUX7_6", + "CMT_TOP_IMUX7_3" + ], + [ + "CMT_FIFO_NW4A1_10", + "CMT_TOP_NW4A1_7" + ], + [ + "CMT_FIFO_EE4B3_4", + "CMT_TOP_EE4B3_1" + ], + [ + "CMT_FIFO_MONITOR_N_8", + "CMT_TOP_MONITOR_N_5" + ], + [ + "CMT_FIFO_L_FAN3_10", + "CMT_TOP_FAN3_7" + ], + [ + "CMT_FIFO_NE4C2_5", + "CMT_TOP_NE4C2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_11", + "CMT_TOP_LOGIC_OUTS_L_B20_8" + ], + [ + "CMT_FIFO_L_IMUX34_8", + "CMT_TOP_IMUX34_5" + ], + [ + "CMT_FIFO_WL1END3_5", + "CMT_TOP_WL1END3_2" + ], + [ + "CMT_FIFO_EE4BEG3_5", + "CMT_TOP_EE4BEG3_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "CMT_TOP_ICLKDIV_2" + ], + [ + "CMT_FIFO_EE2A0_7", + "CMT_TOP_EE2A0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_9", + "CMT_TOP_LOGIC_OUTS_L_B0_6" + ], + [ + "CMT_FIFO_WW2A0_3", + "CMT_TOP_WW2A0_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "CMT_TOP_OCLKDIV_4" + ], + [ + "CMT_FIFO_WW4C3_7", + "CMT_TOP_WW4C3_4" + ], + [ + "CMT_FIFO_WW2A3_5", + "CMT_TOP_WW2A3_2" + ], + [ + "CMT_FIFO_L_IMUX16_5", + "CMT_TOP_IMUX16_2" + ], + [ + "CMT_FIFO_NW2A2_10", + "CMT_TOP_NW2A2_7" + ], + [ + "CMT_FIFO_L_IMUX47_9", + "CMT_TOP_IMUX47_6" + ], + [ + "CMT_FIFO_L_CTRL1_6", + "CMT_TOP_CTRL1_3" + ], + [ + "CMT_FIFO_EE2BEG1_5", + "CMT_TOP_EE2BEG1_2" + ], + [ + "CMT_FIFO_EE2A2_6", + "CMT_TOP_EE2A2_3" + ], + [ + "CMT_FIFO_NE4C2_3", + "CMT_TOP_NE4C2_0" + ], + [ + "CMT_FIFO_SE4C2_9", + "CMT_TOP_SE4C2_6" + ], + [ + "CMT_FIFO_NE4BEG2_3", + "CMT_TOP_NE4BEG2_0" + ], + [ + "CMT_FIFO_EE2A0_6", + "CMT_TOP_EE2A0_3" + ], + [ + "CMT_FIFO_WW2END2_5", + "CMT_TOP_WW2END2_2" + ], + [ + "CMT_FIFO_WW4B2_4", + "CMT_TOP_WW4B2_1" + ], + [ + "CMT_FIFO_LH6_9", + "CMT_TOP_LH6_6" + ], + [ + "CMT_FIFO_L_IMUX27_9", + "CMT_TOP_IMUX27_6" + ], + [ + "CMT_FIFO_ER1BEG3_9", + "CMT_TOP_ER1BEG3_6" + ], + [ + "CMT_FIFO_WL1END2_4", + "CMT_TOP_WL1END2_1" + ], + [ + "CMT_FIFO_WW4A3_8", + "CMT_TOP_WW4A3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_7" + ], + [ + "CMT_FIFO_EE2BEG3_9", + "CMT_TOP_EE2BEG3_6" + ], + [ + "CMT_FIFO_L_BYP1_7", + "CMT_TOP_BYP1_4" + ], + [ + "CMT_FIFO_L_IMUX0_5", + "CMT_TOP_IMUX0_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "CMT_TOP_OCLKDIV_6" + ], + [ + "CMT_FIFO_EE4BEG2_9", + "CMT_TOP_EE4BEG2_6" + ], + [ + "CMT_FIFO_NE4BEG3_11", + "CMT_TOP_NE4BEG3_8" + ], + [ + "CMT_FIFO_LH10_10", + "CMT_TOP_LH10_7" + ], + [ + "CMT_FIFO_L_IMUX18_6", + "CMT_TOP_IMUX18_3" + ], + [ + "CMT_FIFO_L_IMUX10_9", + "CMT_TOP_IMUX10_6" + ], + [ + "CMT_FIFO_LH11_7", + "CMT_TOP_LH11_4" + ], + [ + "CMT_FIFO_LH7_6", + "CMT_TOP_LH7_3" + ], + [ + "CMT_FIFO_WW4C2_5", + "CMT_TOP_WW4C2_2" + ], + [ + "CMT_FIFO_EE2BEG1_9", + "CMT_TOP_EE2BEG1_6" + ], + [ + "CMT_FIFO_WW4A0_8", + "CMT_TOP_WW4A0_5" + ], + [ + "CMT_FIFO_WW4C2_4", + "CMT_TOP_WW4C2_1" + ], + [ + "CMT_FIFO_L_CLK1_8", + "CMT_TOP_CLK1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_10", + "CMT_TOP_LOGIC_OUTS_L_B5_7" + ], + [ + "CMT_FIFO_L_IMUX21_3", + "CMT_TOP_IMUX21_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_9", + "CMT_TOP_LOGIC_OUTS_L_B4_6" + ], + [ + "CMT_FIFO_WL1END0_9", + "CMT_TOP_WL1END0_6" + ], + [ + "CMT_FIFO_L_BYP7_11", + "CMT_TOP_BYP7_8" + ], + [ + "CMT_FIFO_EL1BEG3_11", + "CMT_TOP_EL1BEG3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_6", + "CMT_TOP_LOGIC_OUTS_L_B4_3" + ], + [ + "CMT_FIFO_L_IMUX38_8", + "CMT_TOP_IMUX38_5" + ], + [ + "CMT_FIFO_WL1END3_3", + "CMT_TOP_WL1END3_0" + ], + [ + "CMT_FIFO_EE4C0_4", + "CMT_TOP_EE4C0_1" + ], + [ + "CMT_FIFO_L_FAN3_6", + "CMT_TOP_FAN3_3" + ], + [ + "CMT_FIFO_EL1BEG2_5", + "CMT_TOP_EL1BEG2_2" + ], + [ + "CMT_FIFO_NW2A0_5", + "CMT_TOP_NW2A0_2" + ], + [ + "CMT_FIFO_EE4BEG2_5", + "CMT_TOP_EE4BEG2_2" + ], + [ + "CMT_FIFO_EE2A1_3", + "CMT_TOP_EE2A1_0" + ], + [ + "CMT_FIFO_WW4END3_4", + "CMT_TOP_WW4END3_1" + ], + [ + "CMT_FIFO_L_IMUX6_4", + "CMT_TOP_IMUX6_1" + ], + [ + "CMT_FIFO_L_IMUX24_9", + "CMT_TOP_IMUX24_6" + ], + [ + "CMT_FIFO_NE4BEG0_9", + "CMT_TOP_NE4BEG0_6" + ], + [ + "CMT_FIFO_L_FAN5_4", + "CMT_TOP_FAN5_1" + ], + [ + "CMT_FIFO_NW4A3_6", + "CMT_TOP_NW4A3_3" + ], + [ + "CMT_FIFO_EE4BEG1_9", + "CMT_TOP_EE4BEG1_6" + ], + [ + "CMT_FIFO_L_IMUX12_9", + "CMT_TOP_IMUX12_6" + ], + [ + "CMT_FIFO_WW4B1_6", + "CMT_TOP_WW4B1_3" + ], + [ + "CMT_FIFO_NW4A3_4", + "CMT_TOP_NW4A3_1" + ], + [ + "CMT_FIFO_L_IMUX7_9", + "CMT_TOP_IMUX7_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_7", + "CMT_TOP_LOGIC_OUTS_L_B5_4" + ], + [ + "CMT_FIFO_EE4B1_5", + "CMT_TOP_EE4B1_2" + ], + [ + "CMT_FIFO_NE4BEG2_11", + "CMT_TOP_NE4BEG2_8" + ], + [ + "CMT_FIFO_WW2A3_9", + "CMT_TOP_WW2A3_6" + ], + [ + "CMT_FIFO_L_IMUX1_9", + "CMT_TOP_IMUX1_6" + ], + [ + "CMT_FIFO_WL1END0_5", + "CMT_TOP_WL1END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_5", + "CMT_TOP_LOGIC_OUTS_L_B6_2" + ], + [ + "CMT_FIFO_LH6_3", + "CMT_TOP_LH6_0" + ], + [ + "CMT_FIFO_NW2A1_8", + "CMT_TOP_NW2A1_5" + ], + [ + "CMT_FIFO_LH2_5", + "CMT_TOP_LH2_2" + ], + [ + "CMT_FIFO_WW2END1_8", + "CMT_TOP_WW2END1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_5", + "CMT_TOP_LOGIC_OUTS_L_B14_2" + ], + [ + "CMT_FIFO_L_BYP3_5", + "CMT_TOP_BYP3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_6", + "CMT_TOP_LOGIC_OUTS_L_B6_3" + ], + [ + "CMT_FIFO_EL1BEG1_6", + "CMT_TOP_EL1BEG1_3" + ], + [ + "CMT_FIFO_NW2A3_5", + "CMT_TOP_NW2A3_2" + ], + [ + "CMT_FIFO_EE4C3_3", + "CMT_TOP_EE4C3_0" + ], + [ + "CMT_FIFO_WW4C1_3", + "CMT_TOP_WW4C1_0" + ], + [ + "CMT_FIFO_L_IMUX44_11", + "CMT_TOP_IMUX44_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_7", + "CMT_TOP_LOGIC_OUTS_L_B3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_7", + "CMT_TOP_LOGIC_OUTS_L_B17_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_4", + "CMT_TOP_LOGIC_OUTS_L_B13_1" + ], + [ + "CMT_FIFO_WW4C1_5", + "CMT_TOP_WW4C1_2" + ], + [ + "CMT_FIFO_WW4C2_8", + "CMT_TOP_WW4C2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_9", + "CMT_TOP_LOGIC_OUTS_L_B19_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_0" + ], + [ + "CMT_FIFO_L_IMUX36_11", + "CMT_TOP_IMUX36_8" + ], + [ + "CMT_FIFO_L_IMUX35_6", + "CMT_TOP_IMUX35_3" + ], + [ + "CMT_FIFO_NE2A1_11", + "CMT_TOP_NE2A1_8" + ], + [ + "CMT_FIFO_WR1END0_8", + "CMT_TOP_WR1END0_5" + ], + [ + "CMT_FIFO_SE2A1_7", + "CMT_TOP_SE2A1_4" + ], + [ + "CMT_FIFO_L_IMUX8_7", + "CMT_TOP_IMUX8_4" + ], + [ + "CMT_FIFO_WR1END3_5", + "CMT_TOP_WR1END3_2" + ], + [ + "CMT_FIFO_L_FAN3_4", + "CMT_TOP_FAN3_1" + ], + [ + "CMT_FIFO_L_IMUX4_7", + "CMT_TOP_IMUX4_4" + ], + [ + "CMT_FIFO_L_IMUX6_11", + "CMT_TOP_IMUX6_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_10", + "CMT_TOP_LOGIC_OUTS_L_B11_7" + ], + [ + "CMT_FIFO_EE4BEG2_3", + "CMT_TOP_EE4BEG2_0" + ], + [ + "CMT_FIFO_L_BYP5_6", + "CMT_TOP_BYP5_3" + ], + [ + "CMT_FIFO_NE2A0_9", + "CMT_TOP_NE2A0_6" + ], + [ + "CMT_FIFO_NE2A3_7", + "CMT_TOP_NE2A3_4" + ], + [ + "CMT_FIFO_NW4A0_3", + "CMT_TOP_NW4A0_0" + ], + [ + "CMT_FIFO_SE4C0_8", + "CMT_TOP_SE4C0_5" + ], + [ + "CMT_FIFO_L_IMUX12_8", + "CMT_TOP_IMUX12_5" + ], + [ + "CMT_FIFO_NE4C2_8", + "CMT_TOP_NE4C2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_8", + "CMT_TOP_LOGIC_OUTS_L_B15_5" + ], + [ + "CMT_FIFO_NE2A0_4", + "CMT_TOP_NE2A0_1" + ], + [ + "CMT_FIFO_LH3_4", + "CMT_TOP_LH3_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "CMT_TOP_ICLK_8" + ], + [ + "CMT_FIFO_WW2END1_7", + "CMT_TOP_WW2END1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_3", + "CMT_TOP_LOGIC_OUTS_L_B5_0" + ], + [ + "CMT_FIFO_WW2A0_7", + "CMT_TOP_WW2A0_4" + ], + [ + "CMT_FIFO_L_IMUX13_9", + "CMT_TOP_IMUX13_6" + ], + [ + "CMT_FIFO_L_IMUX29_5", + "CMT_TOP_IMUX29_2" + ], + [ + "CMT_FIFO_WW4A1_5", + "CMT_TOP_WW4A1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_10", + "CMT_TOP_LOGIC_OUTS_L_B10_7" + ], + [ + "CMT_FIFO_EE4BEG1_3", + "CMT_TOP_EE4BEG1_0" + ], + [ + "CMT_FIFO_WW4B2_9", + "CMT_TOP_WW4B2_6" + ], + [ + "CMT_FIFO_SE4C1_10", + "CMT_TOP_SE4C1_7" + ], + [ + "CMT_FIFO_L_IMUX36_3", + "CMT_TOP_IMUX36_0" + ], + [ + "CMT_FIFO_SE4C3_6", + "CMT_TOP_SE4C3_3" + ], + [ + "CMT_FIFO_L_IMUX47_3", + "CMT_TOP_IMUX47_0" + ], + [ + "CMT_FIFO_NE2A3_8", + "CMT_TOP_NE2A3_5" + ], + [ + "CMT_FIFO_L_IMUX19_11", + "CMT_TOP_IMUX19_8" + ], + [ + "CMT_FIFO_NE4BEG2_10", + "CMT_TOP_NE4BEG2_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "CMT_TOP_OCLK_1" + ], + [ + "CMT_FIFO_L_IMUX7_8", + "CMT_TOP_IMUX7_5" + ], + [ + "CMT_FIFO_NW4A2_10", + "CMT_TOP_NW4A2_7" + ], + [ + "CMT_FIFO_WW4END3_9", + "CMT_TOP_WW4END3_6" + ], + [ + "CMT_FIFO_NE4C2_11", + "CMT_TOP_NE4C2_8" + ], + [ + "CMT_FIFO_EE2BEG1_8", + "CMT_TOP_EE2BEG1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_5", + "CMT_TOP_LOGIC_OUTS_L_B9_2" + ], + [ + "CMT_FIFO_NW2A3_7", + "CMT_TOP_NW2A3_4" + ], + [ + "CMT_FIFO_NW4A1_4", + "CMT_TOP_NW4A1_1" + ], + [ + "CMT_FIFO_L_IMUX7_5", + "CMT_TOP_IMUX7_2" + ], + [ + "CMT_FIFO_WW2END1_10", + "CMT_TOP_WW2END1_7" + ], + [ + "CMT_FIFO_MONITOR_P_8", + "CMT_TOP_MONITOR_P_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_9", + "CMT_TOP_LOGIC_OUTS_L_B10_6" + ], + [ + "CMT_FIFO_L_IMUX41_9", + "CMT_TOP_IMUX41_6" + ], + [ + "CMT_FIFO_WW2A3_11", + "CMT_TOP_WW2A3_8" + ], + [ + "CMT_FIFO_LH1_10", + "CMT_TOP_LH1_7" + ], + [ + "CMT_FIFO_SE4C1_8", + "CMT_TOP_SE4C1_5" + ], + [ + "CMT_FIFO_NE4C0_9", + "CMT_TOP_NE4C0_6" + ], + [ + "CMT_FIFO_L_IMUX39_8", + "CMT_TOP_IMUX39_5" + ], + [ + "CMT_FIFO_L_IMUX46_11", + "CMT_TOP_IMUX46_8" + ], + [ + "CMT_FIFO_EE4A0_10", + "CMT_TOP_EE4A0_7" + ], + [ + "CMT_FIFO_EE4C3_4", + "CMT_TOP_EE4C3_1" + ], + [ + "CMT_FIFO_WR1END3_11", + "CMT_TOP_WR1END3_8" + ], + [ + "CMT_FIFO_L_BYP2_7", + "CMT_TOP_BYP2_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "CMT_TOP_ICLK_0" + ], + [ + "CMT_FIFO_SW2A3_9", + "CMT_TOP_SW2A3_6" + ], + [ + "CMT_FIFO_NE2A0_11", + "CMT_TOP_NE2A0_8" + ], + [ + "CMT_FIFO_SW4A0_11", + "CMT_TOP_SW4A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_7", + "CMT_TOP_LOGIC_OUTS_L_B23_4" + ], + [ + "CMT_FIFO_MONITOR_P_10", + "CMT_TOP_MONITOR_P_7" + ], + [ + "CMT_FIFO_SE4C1_5", + "CMT_TOP_SE4C1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "CMT_TOP_ICLK_7" + ], + [ + "CMT_FIFO_WL1END2_5", + "CMT_TOP_WL1END2_2" + ], + [ + "CMT_FIFO_NE4C0_3", + "CMT_TOP_NE4C0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_11", + "CMT_TOP_LOGIC_OUTS_L_B5_8" + ], + [ + "CMT_FIFO_L_FAN1_7", + "CMT_TOP_FAN1_4" + ], + [ + "CMT_FIFO_SE4C1_4", + "CMT_TOP_SE4C1_1" + ], + [ + "CMT_FIFO_L_IMUX1_11", + "CMT_TOP_IMUX1_8" + ], + [ + "CMT_FIFO_NE4C0_11", + "CMT_TOP_NE4C0_8" + ], + [ + "CMT_FIFO_WW4C2_3", + "CMT_TOP_WW4C2_0" + ], + [ + "CMT_FIFO_WW4C2_7", + "CMT_TOP_WW4C2_4" + ], + [ + "CMT_FIFO_LH5_9", + "CMT_TOP_LH5_6" + ], + [ + "CMT_FIFO_WW4A0_3", + "CMT_TOP_WW4A0_0" + ], + [ + "CMT_FIFO_LH5_8", + "CMT_TOP_LH5_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_7", + "CMT_TOP_LOGIC_OUTS_L_B7_4" + ], + [ + "CMT_FIFO_ER1BEG2_3", + "CMT_TOP_ER1BEG2_0" + ], + [ + "CMT_FIFO_L_BYP5_4", + "CMT_TOP_BYP5_1" + ], + [ + "CMT_FIFO_WL1END2_9", + "CMT_TOP_WL1END2_6" + ], + [ + "CMT_FIFO_L_IMUX46_5", + "CMT_TOP_IMUX46_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_9", + "CMT_TOP_LOGIC_OUTS_L_B6_6" + ], + [ + "CMT_FIFO_L_IMUX6_10", + "CMT_TOP_IMUX6_7" + ], + [ + "CMT_FIFO_SW2A3_11", + "CMT_TOP_SW2A3_8" + ], + [ + "CMT_FIFO_WW2A2_11", + "CMT_TOP_WW2A2_8" + ], + [ + "CMT_FIFO_NE4C2_9", + "CMT_TOP_NE4C2_6" + ], + [ + "CMT_FIFO_WW2A1_10", + "CMT_TOP_WW2A1_7" + ], + [ + "CMT_FIFO_WW4C0_4", + "CMT_TOP_WW4C0_1" + ], + [ + "CMT_FIFO_EL1BEG3_6", + "CMT_TOP_EL1BEG3_3" + ], + [ + "CMT_FIFO_L_IMUX7_4", + "CMT_TOP_IMUX7_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_6", + "CMT_TOP_LOGIC_OUTS_L_B11_3" + ], + [ + "CMT_FIFO_WW4B3_4", + "CMT_TOP_WW4B3_1" + ], + [ + "CMT_FIFO_L_IMUX39_10", + "CMT_TOP_IMUX39_7" + ], + [ + "CMT_FIFO_L_IMUX32_4", + "CMT_TOP_IMUX32_1" + ], + [ + "CMT_FIFO_L_FAN7_5", + "CMT_TOP_FAN7_2" + ], + [ + "CMT_FIFO_SW2A1_6", + "CMT_TOP_SW2A1_3" + ], + [ + "CMT_FIFO_L_IMUX46_9", + "CMT_TOP_IMUX46_6" + ], + [ + "CMT_FIFO_WW4B1_11", + "CMT_TOP_WW4B1_8" + ], + [ + "CMT_FIFO_L_IMUX14_9", + "CMT_TOP_IMUX14_6" + ], + [ + "CMT_FIFO_L_BYP0_11", + "CMT_TOP_BYP0_8" + ], + [ + "CMT_FIFO_L_IMUX4_11", + "CMT_TOP_IMUX4_8" + ], + [ + "CMT_FIFO_WW4A0_6", + "CMT_TOP_WW4A0_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "CMT_TOP_OCLKDIV_0" + ], + [ + "CMT_FIFO_NW4END2_4", + "CMT_TOP_NW4END2_1" + ], + [ + "CMT_FIFO_L_BYP4_5", + "CMT_TOP_BYP4_2" + ], + [ + "CMT_FIFO_WW2A0_10", + "CMT_TOP_WW2A0_7" + ], + [ + "CMT_FIFO_L_CTRL1_8", + "CMT_TOP_CTRL1_5" + ], + [ + "CMT_FIFO_EE4A3_7", + "CMT_TOP_EE4A3_4" + ], + [ + "CMT_FIFO_EE2BEG2_7", + "CMT_TOP_EE2BEG2_4" + ], + [ + "CMT_FIFO_L_PHASER_WRCLK", + "CMT_PHASER_IN_B_WRCLK_TOFIFO" + ], + [ + "CMT_FIFO_EE4C0_5", + "CMT_TOP_EE4C0_2" + ], + [ + "CMT_FIFO_L_IMUX33_7", + "CMT_TOP_IMUX33_4" + ], + [ + "CMT_FIFO_L_IMUX42_10", + "CMT_TOP_IMUX42_7" + ], + [ + "CMT_FIFO_SE2A2_4", + "CMT_TOP_SE2A2_1" + ], + [ + "CMT_FIFO_L_CLK1_6", + "CMT_TOP_CLK1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_9", + "CMT_TOP_LOGIC_OUTS_L_B7_6" + ], + [ + "CMT_FIFO_NW4END1_8", + "CMT_TOP_NW4END1_5" + ], + [ + "CMT_FIFO_WW2END0_5", + "CMT_TOP_WW2END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_11", + "CMT_TOP_LOGIC_OUTS_L_B4_8" + ], + [ + "CMT_FIFO_L_IMUX9_6", + "CMT_TOP_IMUX9_3" + ], + [ + "CMT_FIFO_NE2A1_8", + "CMT_TOP_NE2A1_5" + ], + [ + "CMT_FIFO_L_FAN0_8", + "CMT_TOP_FAN0_5" + ], + [ + "CMT_FIFO_L_IMUX43_7", + "CMT_TOP_IMUX43_4" + ], + [ + "CMT_FIFO_NE4C3_7", + "CMT_TOP_NE4C3_4" + ], + [ + "CMT_FIFO_SE4BEG1_8", + "CMT_TOP_SE4BEG1_5" + ], + [ + "CMT_FIFO_L_BYP4_11", + "CMT_TOP_BYP4_8" + ], + [ + "CMT_FIFO_SE2A0_10", + "CMT_TOP_SE2A0_7" + ], + [ + "CMT_FIFO_SE4C1_3", + "CMT_TOP_SE4C1_0" + ], + [ + "CMT_FIFO_L_FAN2_7", + "CMT_TOP_FAN2_4" + ], + [ + "CMT_FIFO_SE4BEG0_5", + "CMT_TOP_SE4BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX3_10", + "CMT_TOP_IMUX3_7" + ], + [ + "CMT_FIFO_SW4END2_3", + "CMT_TOP_SW4END2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_10", + "CMT_TOP_LOGIC_OUTS_L_B2_7" + ], + [ + "CMT_FIFO_L_IMUX35_4", + "CMT_TOP_IMUX35_1" + ], + [ + "CMT_FIFO_L_IMUX6_9", + "CMT_TOP_IMUX6_6" + ], + [ + "CMT_FIFO_EE4B3_9", + "CMT_TOP_EE4B3_6" + ], + [ + "CMT_FIFO_WW4A2_5", + "CMT_TOP_WW4A2_2" + ], + [ + "CMT_FIFO_L_BYP6_9", + "CMT_TOP_BYP6_6" + ], + [ + "CMT_FIFO_SW4A2_9", + "CMT_TOP_SW4A2_6" + ], + [ + "CMT_FIFO_L_IMUX43_11", + "CMT_TOP_IMUX43_8" + ], + [ + "CMT_FIFO_L_IMUX38_4", + "CMT_TOP_IMUX38_1" + ], + [ + "CMT_FIFO_WW4B1_7", + "CMT_TOP_WW4B1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_8", + "CMT_TOP_LOGIC_OUTS_L_B4_5" + ], + [ + "CMT_FIFO_WW2A3_8", + "CMT_TOP_WW2A3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_6", + "CMT_TOP_LOGIC_OUTS_L_B23_3" + ], + [ + "CMT_FIFO_SW2A0_6", + "CMT_TOP_SW2A0_3" + ], + [ + "CMT_FIFO_L_BYP0_6", + "CMT_TOP_BYP0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_5", + "CMT_TOP_LOGIC_OUTS_L_B12_2" + ], + [ + "CMT_FIFO_L_IMUX13_10", + "CMT_TOP_IMUX13_7" + ], + [ + "CMT_FIFO_ER1BEG3_7", + "CMT_TOP_ER1BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_11", + "CMT_TOP_LOGIC_OUTS_L_B11_8" + ], + [ + "CMT_FIFO_L_IMUX19_7", + "CMT_TOP_IMUX19_4" + ], + [ + "CMT_FIFO_L_IMUX4_10", + "CMT_TOP_IMUX4_7" + ], + [ + "CMT_FIFO_L_IMUX40_10", + "CMT_TOP_IMUX40_7" + ], + [ + "CMT_FIFO_SW2A2_8", + "CMT_TOP_SW2A2_5" + ], + [ + "CMT_FIFO_L_IMUX25_7", + "CMT_TOP_IMUX25_4" + ], + [ + "CMT_FIFO_EE4BEG0_11", + "CMT_TOP_EE4BEG0_8" + ], + [ + "CMT_FIFO_WW4B2_6", + "CMT_TOP_WW4B2_3" + ], + [ + "CMT_FIFO_NW4END1_11", + "CMT_TOP_NW4END1_8" + ], + [ + "CMT_FIFO_EE4A3_4", + "CMT_TOP_EE4A3_1" + ], + [ + "CMT_FIFO_SW4A2_11", + "CMT_TOP_SW4A2_8" + ], + [ + "CMT_FIFO_SE4BEG2_9", + "CMT_TOP_SE4BEG2_6" + ], + [ + "CMT_FIFO_SE4C2_6", + "CMT_TOP_SE4C2_3" + ], + [ + "CMT_FIFO_SW4END1_9", + "CMT_TOP_SW4END1_6" + ], + [ + "CMT_FIFO_NE4BEG3_9", + "CMT_TOP_NE4BEG3_6" + ], + [ + "CMT_FIFO_EE4C2_3", + "CMT_TOP_EE4C2_0" + ], + [ + "CMT_FIFO_NE4BEG1_10", + "CMT_TOP_NE4BEG1_7" + ], + [ + "CMT_FIFO_L_IMUX31_5", + "CMT_TOP_IMUX31_2" + ], + [ + "CMT_FIFO_SW4END2_5", + "CMT_TOP_SW4END2_2" + ], + [ + "CMT_FIFO_EL1BEG2_10", + "CMT_TOP_EL1BEG2_7" + ], + [ + "CMT_FIFO_L_IMUX4_6", + "CMT_TOP_IMUX4_3" + ], + [ + "CMT_FIFO_L_IMUX36_4", + "CMT_TOP_IMUX36_1" + ], + [ + "CMT_FIFO_L_IMUX29_10", + "CMT_TOP_IMUX29_7" + ], + [ + "CMT_FIFO_SE4C0_6", + "CMT_TOP_SE4C0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_6", + "CMT_TOP_LOGIC_OUTS_L_B14_3" + ], + [ + "CMT_FIFO_NW2A2_4", + "CMT_TOP_NW2A2_1" + ], + [ + "CMT_FIFO_SW4END0_10", + "CMT_TOP_SW4END0_7" + ], + [ + "CMT_FIFO_L_IMUX5_11", + "CMT_TOP_IMUX5_8" + ], + [ + "CMT_FIFO_SW2A0_4", + "CMT_TOP_SW2A0_1" + ], + [ + "CMT_FIFO_L_FAN0_6", + "CMT_TOP_FAN0_3" + ], + [ + "CMT_FIFO_L_IMUX34_4", + "CMT_TOP_IMUX34_1" + ], + [ + "CMT_FIFO_L_IMUX14_11", + "CMT_TOP_IMUX14_8" + ], + [ + "CMT_FIFO_NW4A3_8", + "CMT_TOP_NW4A3_5" + ], + [ + "CMT_FIFO_WR1END1_7", + "CMT_TOP_WR1END1_4" + ], + [ + "CMT_FIFO_NE4C1_9", + "CMT_TOP_NE4C1_6" + ], + [ + "CMT_FIFO_LH6_8", + "CMT_TOP_LH6_5" + ], + [ + "CMT_FIFO_L_IMUX43_6", + "CMT_TOP_IMUX43_3" + ], + [ + "CMT_FIFO_WW4A2_7", + "CMT_TOP_WW4A2_4" + ], + [ + "CMT_FIFO_EL1BEG3_3", + "CMT_TOP_EL1BEG3_0" + ], + [ + "CMT_FIFO_L_BYP3_3", + "CMT_TOP_BYP3_0" + ], + [ + "CMT_FIFO_L_FAN6_4", + "CMT_TOP_FAN6_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_3", + "CMT_TOP_LOGIC_OUTS_L_B20_0" + ], + [ + "CMT_FIFO_SW4A2_3", + "CMT_TOP_SW4A2_0" + ], + [ + "CMT_FIFO_SE4C3_5", + "CMT_TOP_SE4C3_2" + ], + [ + "CMT_FIFO_L_IMUX45_11", + "CMT_TOP_IMUX45_8" + ], + [ + "CMT_FIFO_L_FAN5_8", + "CMT_TOP_FAN5_5" + ], + [ + "CMT_FIFO_L_IMUX32_10", + "CMT_TOP_IMUX32_7" + ], + [ + "CMT_FIFO_L_IMUX26_7", + "CMT_TOP_IMUX26_4" + ], + [ + "CMT_FIFO_NW4END0_4", + "CMT_TOP_NW4END0_1" + ], + [ + "CMT_FIFO_WW2A0_8", + "CMT_TOP_WW2A0_5" + ], + [ + "CMT_FIFO_EL1BEG0_10", + "CMT_TOP_EL1BEG0_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_6", + "CMT_TOP_LOGIC_OUTS_L_B16_3" + ], + [ + "CMT_FIFO_EE4B3_11", + "CMT_TOP_EE4B3_8" + ], + [ + "CMT_FIFO_WL1END2_3", + "CMT_TOP_WL1END2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_4" + ], + [ + "CMT_FIFO_L_IMUX36_9", + "CMT_TOP_IMUX36_6" + ], + [ + "CMT_FIFO_EE4BEG2_4", + "CMT_TOP_EE4BEG2_1" + ], + [ + "CMT_FIFO_L_IMUX16_10", + "CMT_TOP_IMUX16_7" + ], + [ + "CMT_FIFO_LH10_7", + "CMT_TOP_LH10_4" + ], + [ + "CMT_FIFO_L_BYP1_9", + "CMT_TOP_BYP1_6" + ], + [ + "CMT_FIFO_ER1BEG0_3", + "CMT_TOP_ER1BEG0_0" + ], + [ + "CMT_FIFO_WR1END3_8", + "CMT_TOP_WR1END3_5" + ], + [ + "CMT_FIFO_NW2A0_10", + "CMT_TOP_NW2A0_7" + ], + [ + "CMT_FIFO_SW2A3_5", + "CMT_TOP_SW2A3_2" + ], + [ + "CMT_FIFO_NW4A3_7", + "CMT_TOP_NW4A3_4" + ], + [ + "CMT_FIFO_L_FAN4_11", + "CMT_TOP_FAN4_8" + ], + [ + "CMT_FIFO_WL1END0_6", + "CMT_TOP_WL1END0_3" + ], + [ + "CMT_FIFO_L_BYP4_7", + "CMT_TOP_BYP4_4" + ], + [ + "CMT_FIFO_WW4C0_7", + "CMT_TOP_WW4C0_4" + ], + [ + "CMT_FIFO_SE2A3_4", + "CMT_TOP_SE2A3_1" + ], + [ + "CMT_FIFO_L_IMUX33_3", + "CMT_TOP_IMUX33_0" + ], + [ + "CMT_FIFO_L_IMUX43_9", + "CMT_TOP_IMUX43_6" + ], + [ + "CMT_FIFO_EE2A2_5", + "CMT_TOP_EE2A2_2" + ], + [ + "CMT_FIFO_EE4C2_5", + "CMT_TOP_EE4C2_2" + ], + [ + "CMT_FIFO_ER1BEG3_11", + "CMT_TOP_ER1BEG3_8" + ], + [ + "CMT_FIFO_WW4C2_10", + "CMT_TOP_WW4C2_7" + ], + [ + "CMT_FIFO_WW4A1_8", + "CMT_TOP_WW4A1_5" + ], + [ + "CMT_FIFO_L_IMUX17_8", + "CMT_TOP_IMUX17_5" + ], + [ + "CMT_FIFO_L_IMUX17_5", + "CMT_TOP_IMUX17_2" + ], + [ + "CMT_FIFO_L_IMUX32_3", + "CMT_TOP_IMUX32_0" + ], + [ + "CMT_FIFO_LH1_6", + "CMT_TOP_LH1_3" + ], + [ + "CMT_FIFO_NW4END2_11", + "CMT_TOP_NW4END2_8" + ], + [ + "CMT_FIFO_L_BYP4_3", + "CMT_TOP_BYP4_0" + ], + [ + "CMT_FIFO_L_IMUX43_10", + "CMT_TOP_IMUX43_7" + ], + [ + "CMT_FIFO_L_FAN0_7", + "CMT_TOP_FAN0_4" + ], + [ + "CMT_FIFO_EL1BEG1_5", + "CMT_TOP_EL1BEG1_2" + ], + [ + "CMT_FIFO_SW4END0_11", + "CMT_TOP_SW4END0_8" + ], + [ + "CMT_FIFO_NE4BEG3_4", + "CMT_TOP_NE4BEG3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_5", + "CMT_TOP_LOGIC_OUTS_L_B4_2" + ], + [ + "CMT_FIFO_L_BYP7_3", + "CMT_TOP_BYP7_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_3", + "CMT_TOP_LOGIC_OUTS_L_B14_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_9", + "CMT_TOP_LOGIC_OUTS_L_B15_6" + ], + [ + "CMT_FIFO_WW4B2_3", + "CMT_TOP_WW4B2_0" + ], + [ + "CMT_FIFO_WL1END0_7", + "CMT_TOP_WL1END0_4" + ], + [ + "CMT_FIFO_L_IMUX15_11", + "CMT_TOP_IMUX15_8" + ], + [ + "CMT_FIFO_SE4BEG2_10", + "CMT_TOP_SE4BEG2_7" + ], + [ + "CMT_FIFO_SE2A1_6", + "CMT_TOP_SE2A1_3" + ], + [ + "CMT_FIFO_WW2A0_5", + "CMT_TOP_WW2A0_2" + ], + [ + "CMT_FIFO_L_IMUX4_4", + "CMT_TOP_IMUX4_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_3", + "CMT_TOP_LOGIC_OUTS_L_B16_0" + ], + [ + "CMT_FIFO_NW2A3_3", + "CMT_TOP_NW2A3_0" + ], + [ + "CMT_FIFO_NW4A2_6", + "CMT_TOP_NW4A2_3" + ], + [ + "CMT_FIFO_L_FAN2_4", + "CMT_TOP_FAN2_1" + ], + [ + "CMT_FIFO_L_IMUX25_11", + "CMT_TOP_IMUX25_8" + ], + [ + "CMT_FIFO_NE2A1_5", + "CMT_TOP_NE2A1_2" + ], + [ + "CMT_FIFO_SW4END3_3", + "CMT_TOP_SW4END3_0" + ], + [ + "CMT_FIFO_ER1BEG1_5", + "CMT_TOP_ER1BEG1_2" + ], + [ + "CMT_FIFO_WW4C2_11", + "CMT_TOP_WW4C2_8" + ], + [ + "CMT_FIFO_NE4BEG1_6", + "CMT_TOP_NE4BEG1_3" + ], + [ + "CMT_FIFO_EE4A1_3", + "CMT_TOP_EE4A1_0" + ], + [ + "CMT_FIFO_NW4A0_10", + "CMT_TOP_NW4A0_7" + ], + [ + "CMT_FIFO_LH4_4", + "CMT_TOP_LH4_1" + ], + [ + "CMT_FIFO_L_IMUX28_8", + "CMT_TOP_IMUX28_5" + ], + [ + "CMT_FIFO_ER1BEG3_3", + "CMT_TOP_ER1BEG3_0" + ], + [ + "CMT_FIFO_L_IMUX5_10", + "CMT_TOP_IMUX5_7" + ], + [ + "CMT_FIFO_L_IMUX44_6", + "CMT_TOP_IMUX44_3" + ], + [ + "CMT_FIFO_L_BYP3_10", + "CMT_TOP_BYP3_7" + ], + [ + "CMT_FIFO_L_BYP5_11", + "CMT_TOP_BYP5_8" + ], + [ + "CMT_FIFO_NE4BEG1_3", + "CMT_TOP_NE4BEG1_0" + ], + [ + "CMT_FIFO_L_IMUX12_7", + "CMT_TOP_IMUX12_4" + ], + [ + "CMT_FIFO_LH7_3", + "CMT_TOP_LH7_0" + ], + [ + "CMT_FIFO_SW4A0_7", + "CMT_TOP_SW4A0_4" + ], + [ + "CMT_FIFO_L_BYP4_10", + "CMT_TOP_BYP4_7" + ], + [ + "CMT_FIFO_WR1END1_8", + "CMT_TOP_WR1END1_5" + ], + [ + "CMT_FIFO_SE2A1_3", + "CMT_TOP_SE2A1_0" + ], + [ + "CMT_FIFO_EE2BEG0_7", + "CMT_TOP_EE2BEG0_4" + ], + [ + "CMT_FIFO_L_IMUX12_11", + "CMT_TOP_IMUX12_8" + ], + [ + "CMT_FIFO_L_FAN4_3", + "CMT_TOP_FAN4_0" + ], + [ + "CMT_FIFO_L_IMUX8_11", + "CMT_TOP_IMUX8_8" + ], + [ + "CMT_FIFO_NW4END2_10", + "CMT_TOP_NW4END2_7" + ], + [ + "CMT_FIFO_ER1BEG1_11", + "CMT_TOP_ER1BEG1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_5", + "CMT_TOP_LOGIC_OUTS_L_B16_2" + ], + [ + "CMT_FIFO_WW2A3_4", + "CMT_TOP_WW2A3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_4", + "CMT_TOP_LOGIC_OUTS_L_B14_1" + ], + [ + "CMT_FIFO_L_IMUX23_5", + "CMT_TOP_IMUX23_2" + ], + [ + "CMT_FIFO_NW4END0_11", + "CMT_TOP_NW4END0_8" + ], + [ + "CMT_FIFO_ER1BEG3_10", + "CMT_TOP_ER1BEG3_7" + ], + [ + "CMT_FIFO_SE4C3_4", + "CMT_TOP_SE4C3_1" + ], + [ + "CMT_FIFO_WW2END3_4", + "CMT_TOP_WW2END3_1" + ], + [ + "CMT_FIFO_L_FAN1_11", + "CMT_TOP_FAN1_8" + ], + [ + "CMT_FIFO_SW4END1_4", + "CMT_TOP_SW4END1_1" + ], + [ + "CMT_FIFO_SW4END3_11", + "CMT_TOP_SW4END3_8" + ], + [ + "CMT_FIFO_EE4B1_8", + "CMT_TOP_EE4B1_5" + ], + [ + "CMT_FIFO_L_FAN1_10", + "CMT_TOP_FAN1_7" + ], + [ + "CMT_FIFO_L_IMUX43_3", + "CMT_TOP_IMUX43_0" + ], + [ + "CMT_FIFO_WR1END1_6", + "CMT_TOP_WR1END1_3" + ], + [ + "CMT_FIFO_WW4END0_9", + "CMT_TOP_WW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX24_4", + "CMT_TOP_IMUX24_1" + ], + [ + "CMT_FIFO_EE4C3_5", + "CMT_TOP_EE4C3_2" + ], + [ + "CMT_FIFO_SE2A3_5", + "CMT_TOP_SE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX47_6", + "CMT_TOP_IMUX47_3" + ], + [ + "CMT_FIFO_L_IMUX22_6", + "CMT_TOP_IMUX22_3" + ], + [ + "CMT_FIFO_NE4C1_8", + "CMT_TOP_NE4C1_5" + ], + [ + "CMT_FIFO_EL1BEG1_7", + "CMT_TOP_EL1BEG1_4" + ], + [ + "CMT_FIFO_L_IMUX5_8", + "CMT_TOP_IMUX5_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_4", + "CMT_TOP_LOGIC_OUTS_L_B7_1" + ], + [ + "CMT_FIFO_SE4BEG0_9", + "CMT_TOP_SE4BEG0_6" + ], + [ + "CMT_FIFO_L_BYP7_6", + "CMT_TOP_BYP7_3" + ], + [ + "CMT_FIFO_L_IMUX39_7", + "CMT_TOP_IMUX39_4" + ], + [ + "CMT_FIFO_SW2A2_10", + "CMT_TOP_SW2A2_7" + ], + [ + "CMT_FIFO_WW4A0_7", + "CMT_TOP_WW4A0_4" + ], + [ + "CMT_FIFO_NW2A1_3", + "CMT_TOP_NW2A1_0" + ], + [ + "CMT_FIFO_LH11_3", + "CMT_TOP_LH11_0" + ], + [ + "CMT_FIFO_EE4BEG3_3", + "CMT_TOP_EE4BEG3_0" + ], + [ + "CMT_FIFO_L_IMUX20_3", + "CMT_TOP_IMUX20_0" + ], + [ + "CMT_FIFO_ER1BEG1_6", + "CMT_TOP_ER1BEG1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_8", + "CMT_TOP_LOGIC_OUTS_L_B22_5" + ], + [ + "CMT_FIFO_WW4B1_5", + "CMT_TOP_WW4B1_2" + ], + [ + "CMT_FIFO_EE4B1_3", + "CMT_TOP_EE4B1_0" + ], + [ + "CMT_FIFO_L_IMUX30_5", + "CMT_TOP_IMUX30_2" + ], + [ + "CMT_FIFO_EE4A2_11", + "CMT_TOP_EE4A2_8" + ], + [ + "CMT_FIFO_WW4A2_6", + "CMT_TOP_WW4A2_3" + ], + [ + "CMT_FIFO_EE4B3_7", + "CMT_TOP_EE4B3_4" + ], + [ + "CMT_FIFO_WW4B1_9", + "CMT_TOP_WW4B1_6" + ], + [ + "CMT_FIFO_L_IMUX21_7", + "CMT_TOP_IMUX21_4" + ], + [ + "CMT_FIFO_WR1END2_8", + "CMT_TOP_WR1END2_5" + ], + [ + "CMT_FIFO_WW2END0_3", + "CMT_TOP_WW2END0_0" + ], + [ + "CMT_FIFO_WW2END0_6", + "CMT_TOP_WW2END0_3" + ], + [ + "CMT_FIFO_NW4A0_8", + "CMT_TOP_NW4A0_5" + ], + [ + "CMT_FIFO_SW4END2_7", + "CMT_TOP_SW4END2_4" + ], + [ + "CMT_FIFO_L_IMUX16_6", + "CMT_TOP_IMUX16_3" + ], + [ + "CMT_FIFO_L_IMUX3_5", + "CMT_TOP_IMUX3_2" + ], + [ + "CMT_FIFO_EL1BEG0_7", + "CMT_TOP_EL1BEG0_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "CMT_TOP_ICLK_3" + ], + [ + "CMT_FIFO_SE4C0_11", + "CMT_TOP_SE4C0_8" + ], + [ + "CMT_FIFO_L_IMUX11_7", + "CMT_TOP_IMUX11_4" + ], + [ + "CMT_FIFO_WR1END2_6", + "CMT_TOP_WR1END2_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "CMT_TOP_ICLKDIV_3" + ], + [ + "CMT_FIFO_LH11_9", + "CMT_TOP_LH11_6" + ], + [ + "CMT_FIFO_NW4A2_7", + "CMT_TOP_NW4A2_4" + ], + [ + "CMT_FIFO_SE4BEG0_6", + "CMT_TOP_SE4BEG0_3" + ], + [ + "CMT_FIFO_SW4A0_6", + "CMT_TOP_SW4A0_3" + ], + [ + "CMT_FIFO_EE4B0_10", + "CMT_TOP_EE4B0_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "CMT_TOP_OCLKDIV_2" + ], + [ + "CMT_FIFO_L_IMUX37_4", + "CMT_TOP_IMUX37_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_10", + "CMT_TOP_LOGIC_OUTS_L_B18_7" + ], + [ + "CMT_FIFO_EE4C2_8", + "CMT_TOP_EE4C2_5" + ], + [ + "CMT_FIFO_NW4END1_6", + "CMT_TOP_NW4END1_3" + ], + [ + "CMT_FIFO_LH5_5", + "CMT_TOP_LH5_2" + ], + [ + "CMT_FIFO_L_IMUX39_3", + "CMT_TOP_IMUX39_0" + ], + [ + "CMT_FIFO_LH6_4", + "CMT_TOP_LH6_1" + ], + [ + "CMT_FIFO_EE2BEG2_5", + "CMT_TOP_EE2BEG2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_8", + "CMT_TOP_LOGIC_OUTS_L_B21_5" + ], + [ + "CMT_FIFO_EL1BEG3_10", + "CMT_TOP_EL1BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX34_7", + "CMT_TOP_IMUX34_4" + ], + [ + "CMT_FIFO_L_IMUX18_4", + "CMT_TOP_IMUX18_1" + ], + [ + "CMT_FIFO_L_IMUX40_8", + "CMT_TOP_IMUX40_5" + ], + [ + "CMT_FIFO_NW4END3_6", + "CMT_TOP_NW4END3_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "CMT_TOP_ICLKDIV_7" + ], + [ + "CMT_FIFO_SW4END2_4", + "CMT_TOP_SW4END2_1" + ], + [ + "CMT_FIFO_SW2A2_5", + "CMT_TOP_SW2A2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_10", + "CMT_TOP_LOGIC_OUTS_L_B16_7" + ], + [ + "CMT_FIFO_WW4A3_10", + "CMT_TOP_WW4A3_7" + ], + [ + "CMT_FIFO_NE4C3_3", + "CMT_TOP_NE4C3_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "CMT_TOP_ICLK_5" + ], + [ + "CMT_FIFO_L_IMUX8_6", + "CMT_TOP_IMUX8_3" + ], + [ + "CMT_FIFO_L_FAN6_8", + "CMT_TOP_FAN6_5" + ], + [ + "CMT_FIFO_L_IMUX19_6", + "CMT_TOP_IMUX19_3" + ], + [ + "CMT_FIFO_L_IMUX0_11", + "CMT_TOP_IMUX0_8" + ], + [ + "CMT_FIFO_L_IMUX11_11", + "CMT_TOP_IMUX11_8" + ], + [ + "CMT_FIFO_EL1BEG3_7", + "CMT_TOP_EL1BEG3_4" + ], + [ + "CMT_FIFO_L_IMUX45_9", + "CMT_TOP_IMUX45_6" + ], + [ + "CMT_FIFO_L_CLK0_10", + "CMT_TOP_CLK0_7" + ], + [ + "CMT_FIFO_L_IMUX28_10", + "CMT_TOP_IMUX28_7" + ], + [ + "CMT_FIFO_SW4A3_8", + "CMT_TOP_SW4A3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_9", + "CMT_TOP_LOGIC_OUTS_L_B8_6" + ], + [ + "CMT_FIFO_WR1END1_5", + "CMT_TOP_WR1END1_2" + ], + [ + "CMT_FIFO_WW4END1_6", + "CMT_TOP_WW4END1_3" + ], + [ + "CMT_FIFO_LH4_8", + "CMT_TOP_LH4_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_3", + "CMT_TOP_LOGIC_OUTS_L_B13_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_9", + "CMT_TOP_LOGIC_OUTS_L_B14_6" + ], + [ + "CMT_FIFO_LH2_3", + "CMT_TOP_LH2_0" + ], + [ + "CMT_FIFO_LH3_8", + "CMT_TOP_LH3_5" + ], + [ + "CMT_FIFO_NE4C3_10", + "CMT_TOP_NE4C3_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "CMT_TOP_ICLKDIV_6" + ], + [ + "CMT_FIFO_WW4A0_5", + "CMT_TOP_WW4A0_2" + ], + [ + "CMT_FIFO_WW2END0_8", + "CMT_TOP_WW2END0_5" + ], + [ + "CMT_FIFO_L_IMUX46_3", + "CMT_TOP_IMUX46_0" + ], + [ + "CMT_FIFO_WR1END2_10", + "CMT_TOP_WR1END2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_5", + "CMT_TOP_LOGIC_OUTS_L_B7_2" + ], + [ + "CMT_FIFO_WR1END2_5", + "CMT_TOP_WR1END2_2" + ], + [ + "CMT_FIFO_L_BYP7_7", + "CMT_TOP_BYP7_4" + ], + [ + "CMT_FIFO_EE4A0_4", + "CMT_TOP_EE4A0_1" + ], + [ + "CMT_FIFO_L_IMUX25_6", + "CMT_TOP_IMUX25_3" + ], + [ + "CMT_FIFO_L_CTRL0_3", + "CMT_TOP_CTRL0_0" + ], + [ + "CMT_FIFO_L_BYP0_9", + "CMT_TOP_BYP0_6" + ], + [ + "CMT_FIFO_L_BYP1_8", + "CMT_TOP_BYP1_5" + ], + [ + "CMT_FIFO_EE4A2_7", + "CMT_TOP_EE4A2_4" + ], + [ + "CMT_FIFO_NW4END3_4", + "CMT_TOP_NW4END3_1" + ], + [ + "CMT_FIFO_ER1BEG3_6", + "CMT_TOP_ER1BEG3_3" + ], + [ + "CMT_FIFO_SW2A1_7", + "CMT_TOP_SW2A1_4" + ], + [ + "CMT_FIFO_EE4B0_4", + "CMT_TOP_EE4B0_1" + ], + [ + "CMT_FIFO_LH4_3", + "CMT_TOP_LH4_0" + ], + [ + "CMT_FIFO_L_CLK0_8", + "CMT_TOP_CLK0_5" + ], + [ + "CMT_FIFO_L_FAN0_11", + "CMT_TOP_FAN0_8" + ], + [ + "CMT_FIFO_EE4B0_6", + "CMT_TOP_EE4B0_3" + ], + [ + "CMT_FIFO_L_IMUX5_9", + "CMT_TOP_IMUX5_6" + ], + [ + "CMT_FIFO_L_IMUX34_9", + "CMT_TOP_IMUX34_6" + ], + [ + "CMT_FIFO_L_IMUX15_4", + "CMT_TOP_IMUX15_1" + ], + [ + "CMT_FIFO_L_IMUX30_6", + "CMT_TOP_IMUX30_3" + ], + [ + "CMT_FIFO_L_FAN7_9", + "CMT_TOP_FAN7_6" + ], + [ + "CMT_FIFO_ER1BEG1_7", + "CMT_TOP_ER1BEG1_4" + ], + [ + "CMT_FIFO_SE2A0_6", + "CMT_TOP_SE2A0_3" + ], + [ + "CMT_FIFO_NW4A1_7", + "CMT_TOP_NW4A1_4" + ], + [ + "CMT_FIFO_L_FAN6_11", + "CMT_TOP_FAN6_8" + ], + [ + "CMT_FIFO_SW4A1_7", + "CMT_TOP_SW4A1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_7", + "CMT_TOP_LOGIC_OUTS_L_B22_4" + ], + [ + "CMT_FIFO_WW4B2_5", + "CMT_TOP_WW4B2_2" + ], + [ + "CMT_FIFO_SW4END1_5", + "CMT_TOP_SW4END1_2" + ], + [ + "CMT_FIFO_EE4A1_10", + "CMT_TOP_EE4A1_7" + ], + [ + "CMT_FIFO_SE4BEG0_7", + "CMT_TOP_SE4BEG0_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "CMT_TOP_ICLK_2" + ], + [ + "CMT_FIFO_WW2END3_7", + "CMT_TOP_WW2END3_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "CMT_TOP_OCLKDIV_3" + ], + [ + "CMT_FIFO_L_FAN1_8", + "CMT_TOP_FAN1_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "CMT_TOP_OCLK1X_90_4" + ], + [ + "CMT_FIFO_L_IMUX29_11", + "CMT_TOP_IMUX29_8" + ], + [ + "CMT_FIFO_LH1_11", + "CMT_TOP_LH1_8" + ], + [ + "CMT_FIFO_WW4A2_3", + "CMT_TOP_WW4A2_0" + ], + [ + "CMT_FIFO_LH12_8", + "CMT_TOP_LH12_5" + ], + [ + "CMT_FIFO_NW4END0_9", + "CMT_TOP_NW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX29_3", + "CMT_TOP_IMUX29_0" + ], + [ + "CMT_FIFO_NE4BEG0_4", + "CMT_TOP_NE4BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_11", + "CMT_TOP_LOGIC_OUTS_L_B12_8" + ], + [ + "CMT_FIFO_EE4A0_7", + "CMT_TOP_EE4A0_4" + ], + [ + "CMT_FIFO_EE4B1_4", + "CMT_TOP_EE4B1_1" + ], + [ + "CMT_FIFO_SE2A2_10", + "CMT_TOP_SE2A2_7" + ], + [ + "CMT_FIFO_L_IMUX15_5", + "CMT_TOP_IMUX15_2" + ], + [ + "CMT_FIFO_EE4B2_4", + "CMT_TOP_EE4B2_1" + ], + [ + "CMT_FIFO_EE2BEG0_11", + "CMT_TOP_EE2BEG0_8" + ], + [ + "CMT_FIFO_L_IMUX30_10", + "CMT_TOP_IMUX30_7" + ], + [ + "CMT_FIFO_SW4A1_11", + "CMT_TOP_SW4A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_6", + "CMT_TOP_LOGIC_OUTS_L_B1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_7", + "CMT_TOP_LOGIC_OUTS_L_B21_4" + ], + [ + "CMT_FIFO_L_FAN0_5", + "CMT_TOP_FAN0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_3", + "CMT_TOP_LOGIC_OUTS_L_B12_0" + ], + [ + "CMT_FIFO_SW4A0_3", + "CMT_TOP_SW4A0_0" + ], + [ + "CMT_FIFO_WW2END1_5", + "CMT_TOP_WW2END1_2" + ], + [ + "CMT_FIFO_SW2A3_6", + "CMT_TOP_SW2A3_3" + ], + [ + "CMT_FIFO_LH6_11", + "CMT_TOP_LH6_8" + ], + [ + "CMT_FIFO_ER1BEG0_4", + "CMT_TOP_ER1BEG0_1" + ], + [ + "CMT_FIFO_L_IMUX0_8", + "CMT_TOP_IMUX0_5" + ], + [ + "CMT_FIFO_EE4A0_5", + "CMT_TOP_EE4A0_2" + ], + [ + "CMT_FIFO_L_IMUX41_5", + "CMT_TOP_IMUX41_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_5", + "CMT_TOP_LOGIC_OUTS_L_B17_2" + ], + [ + "CMT_FIFO_SE2A1_11", + "CMT_TOP_SE2A1_8" + ], + [ + "CMT_FIFO_EE4BEG0_10", + "CMT_TOP_EE4BEG0_7" + ], + [ + "CMT_FIFO_L_FAN5_9", + "CMT_TOP_FAN5_6" + ], + [ + "CMT_FIFO_L_FAN0_9", + "CMT_TOP_FAN0_6" + ], + [ + "CMT_FIFO_NE4C2_10", + "CMT_TOP_NE4C2_7" + ], + [ + "CMT_FIFO_WL1END1_7", + "CMT_TOP_WL1END1_4" + ], + [ + "CMT_FIFO_L_IMUX25_8", + "CMT_TOP_IMUX25_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_3", + "CMT_TOP_LOGIC_OUTS_L_B23_0" + ], + [ + "CMT_FIFO_ER1BEG0_11", + "CMT_TOP_ER1BEG0_8" + ], + [ + "CMT_FIFO_WW4END2_7", + "CMT_TOP_WW4END2_4" + ], + [ + "CMT_FIFO_WW4B3_6", + "CMT_TOP_WW4B3_3" + ], + [ + "CMT_FIFO_ER1BEG2_9", + "CMT_TOP_ER1BEG2_6" + ], + [ + "CMT_FIFO_EE4A3_6", + "CMT_TOP_EE4A3_3" + ], + [ + "CMT_FIFO_NE4C3_8", + "CMT_TOP_NE4C3_5" + ], + [ + "CMT_FIFO_EE4B0_5", + "CMT_TOP_EE4B0_2" + ], + [ + "CMT_FIFO_WW4C2_6", + "CMT_TOP_WW4C2_3" + ], + [ + "CMT_FIFO_EE4BEG2_10", + "CMT_TOP_EE4BEG2_7" + ], + [ + "CMT_FIFO_NE4C1_10", + "CMT_TOP_NE4C1_7" + ], + [ + "CMT_FIFO_L_IMUX13_5", + "CMT_TOP_IMUX13_2" + ], + [ + "CMT_FIFO_EE2BEG2_10", + "CMT_TOP_EE2BEG2_7" + ], + [ + "CMT_FIFO_WL1END2_11", + "CMT_TOP_WL1END2_8" + ], + [ + "CMT_FIFO_L_IMUX17_10", + "CMT_TOP_IMUX17_7" + ], + [ + "CMT_FIFO_WW4END2_10", + "CMT_TOP_WW4END2_7" + ], + [ + "CMT_FIFO_NW2A1_10", + "CMT_TOP_NW2A1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_7", + "CMT_TOP_LOGIC_OUTS_L_B14_4" + ], + [ + "CMT_FIFO_SW4END2_10", + "CMT_TOP_SW4END2_7" + ], + [ + "CMT_FIFO_NW4END1_5", + "CMT_TOP_NW4END1_2" + ], + [ + "CMT_FIFO_L_IMUX38_5", + "CMT_TOP_IMUX38_2" + ], + [ + "CMT_FIFO_LH7_10", + "CMT_TOP_LH7_7" + ], + [ + "CMT_FIFO_LH12_4", + "CMT_TOP_LH12_1" + ], + [ + "CMT_FIFO_WW4A1_4", + "CMT_TOP_WW4A1_1" + ], + [ + "CMT_FIFO_L_CTRL0_8", + "CMT_TOP_CTRL0_5" + ], + [ + "CMT_FIFO_EE4B1_9", + "CMT_TOP_EE4B1_6" + ], + [ + "CMT_FIFO_EE4A0_9", + "CMT_TOP_EE4A0_6" + ], + [ + "CMT_FIFO_L_IMUX15_3", + "CMT_TOP_IMUX15_0" + ], + [ + "CMT_FIFO_WW4B2_7", + "CMT_TOP_WW4B2_4" + ], + [ + "CMT_FIFO_NE2A2_9", + "CMT_TOP_NE2A2_6" + ], + [ + "CMT_FIFO_L_IMUX1_10", + "CMT_TOP_IMUX1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_4", + "CMT_TOP_LOGIC_OUTS_L_B5_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_8", + "CMT_TOP_LOGIC_OUTS_L_B6_5" + ], + [ + "CMT_FIFO_EE2A2_4", + "CMT_TOP_EE2A2_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_5", + "CMT_TOP_LOGIC_OUTS_L_B13_2" + ], + [ + "CMT_FIFO_WW2A2_7", + "CMT_TOP_WW2A2_4" + ], + [ + "CMT_FIFO_L_FAN6_3", + "CMT_TOP_FAN6_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_5", + "CMT_TOP_LOGIC_OUTS_L_B8_2" + ], + [ + "CMT_FIFO_L_IMUX32_9", + "CMT_TOP_IMUX32_6" + ], + [ + "CMT_FIFO_LH8_9", + "CMT_TOP_LH8_6" + ], + [ + "CMT_FIFO_NE4BEG0_11", + "CMT_TOP_NE4BEG0_8" + ], + [ + "CMT_FIFO_WW4END0_4", + "CMT_TOP_WW4END0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_4", + "CMT_TOP_LOGIC_OUTS_L_B18_1" + ], + [ + "CMT_FIFO_L_IMUX21_10", + "CMT_TOP_IMUX21_7" + ], + [ + "CMT_FIFO_WW4A2_8", + "CMT_TOP_WW4A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_3", + "CMT_TOP_LOGIC_OUTS_L_B19_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_5", + "CMT_TOP_LOGIC_OUTS_L_B3_2" + ], + [ + "CMT_FIFO_WW4END2_11", + "CMT_TOP_WW4END2_8" + ], + [ + "CMT_FIFO_NW4END3_3", + "CMT_TOP_NW4END3_0" + ], + [ + "CMT_FIFO_SE4BEG3_7", + "CMT_TOP_SE4BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_7", + "CMT_TOP_LOGIC_OUTS_L_B8_4" + ], + [ + "CMT_FIFO_NW4A2_8", + "CMT_TOP_NW4A2_5" + ], + [ + "CMT_FIFO_EE4BEG3_10", + "CMT_TOP_EE4BEG3_7" + ], + [ + "CMT_FIFO_NE4BEG0_6", + "CMT_TOP_NE4BEG0_3" + ], + [ + "CMT_FIFO_NE2A0_8", + "CMT_TOP_NE2A0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_8", + "CMT_TOP_LOGIC_OUTS_L_B12_5" + ], + [ + "CMT_FIFO_WR1END0_7", + "CMT_TOP_WR1END0_4" + ], + [ + "CMT_FIFO_LH8_4", + "CMT_TOP_LH8_1" + ], + [ + "CMT_FIFO_NE2A2_10", + "CMT_TOP_NE2A2_7" + ], + [ + "CMT_FIFO_WW4A3_7", + "CMT_TOP_WW4A3_4" + ], + [ + "CMT_FIFO_SW4A1_3", + "CMT_TOP_SW4A1_0" + ], + [ + "CMT_FIFO_L_FAN6_9", + "CMT_TOP_FAN6_6" + ], + [ + "CMT_FIFO_ER1BEG1_3", + "CMT_TOP_ER1BEG1_0" + ], + [ + "CMT_FIFO_L_IMUX8_5", + "CMT_TOP_IMUX8_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_3", + "CMT_TOP_LOGIC_OUTS_L_B8_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_8", + "CMT_TOP_LOGIC_OUTS_L_B10_5" + ], + [ + "CMT_FIFO_WW4C3_4", + "CMT_TOP_WW4C3_1" + ], + [ + "CMT_FIFO_L_IMUX3_7", + "CMT_TOP_IMUX3_4" + ], + [ + "CMT_FIFO_L_IMUX0_7", + "CMT_TOP_IMUX0_4" + ], + [ + "CMT_FIFO_L_IMUX10_11", + "CMT_TOP_IMUX10_8" + ], + [ + "CMT_FIFO_LH1_9", + "CMT_TOP_LH1_6" + ], + [ + "CMT_FIFO_L_FAN5_5", + "CMT_TOP_FAN5_2" + ], + [ + "CMT_FIFO_L_IMUX21_6", + "CMT_TOP_IMUX21_3" + ], + [ + "CMT_FIFO_EL1BEG3_5", + "CMT_TOP_EL1BEG3_2" + ], + [ + "CMT_FIFO_WL1END1_5", + "CMT_TOP_WL1END1_2" + ], + [ + "CMT_FIFO_L_IMUX0_4", + "CMT_TOP_IMUX0_1" + ], + [ + "CMT_FIFO_LH6_10", + "CMT_TOP_LH6_7" + ], + [ + "CMT_FIFO_SE2A0_3", + "CMT_TOP_SE2A0_0" + ], + [ + "CMT_FIFO_EE4A1_8", + "CMT_TOP_EE4A1_5" + ], + [ + "CMT_FIFO_L_IMUX30_4", + "CMT_TOP_IMUX30_1" + ], + [ + "CMT_FIFO_NW4A3_5", + "CMT_TOP_NW4A3_2" + ], + [ + "CMT_FIFO_L_IMUX37_8", + "CMT_TOP_IMUX37_5" + ], + [ + "CMT_FIFO_SE4C0_7", + "CMT_TOP_SE4C0_4" + ], + [ + "CMT_FIFO_ER1BEG0_6", + "CMT_TOP_ER1BEG0_3" + ], + [ + "CMT_FIFO_WW2A3_3", + "CMT_TOP_WW2A3_0" + ], + [ + "CMT_FIFO_WW4C1_4", + "CMT_TOP_WW4C1_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "CMT_TOP_ICLK_1" + ], + [ + "CMT_FIFO_WW4C3_8", + "CMT_TOP_WW4C3_5" + ], + [ + "CMT_FIFO_WW2END0_9", + "CMT_TOP_WW2END0_6" + ], + [ + "CMT_FIFO_SE4BEG3_8", + "CMT_TOP_SE4BEG3_5" + ], + [ + "CMT_FIFO_LH3_11", + "CMT_TOP_LH3_8" + ], + [ + "CMT_FIFO_L_CLK1_11", + "CMT_TOP_CLK1_8" + ], + [ + "CMT_FIFO_EE4BEG0_5", + "CMT_TOP_EE4BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX10_4", + "CMT_TOP_IMUX10_1" + ], + [ + "CMT_FIFO_WW2A2_3", + "CMT_TOP_WW2A2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_4", + "CMT_TOP_LOGIC_OUTS_L_B9_1" + ], + [ + "CMT_FIFO_L_IMUX7_11", + "CMT_TOP_IMUX7_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_5", + "CMT_TOP_LOGIC_OUTS_L_B20_2" + ], + [ + "CMT_FIFO_L_IMUX44_5", + "CMT_TOP_IMUX44_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "CMT_TOP_OCLK_0" + ], + [ + "CMT_FIFO_L_IMUX1_4", + "CMT_TOP_IMUX1_1" + ], + [ + "CMT_FIFO_WW2A0_11", + "CMT_TOP_WW2A0_8" + ], + [ + "CMT_FIFO_L_IMUX38_9", + "CMT_TOP_IMUX38_6" + ], + [ + "CMT_FIFO_NE4C0_6", + "CMT_TOP_NE4C0_3" + ], + [ + "CMT_FIFO_L_IMUX14_4", + "CMT_TOP_IMUX14_1" + ], + [ + "CMT_FIFO_L_BYP1_6", + "CMT_TOP_BYP1_3" + ], + [ + "CMT_FIFO_L_BYP1_4", + "CMT_TOP_BYP1_1" + ], + [ + "CMT_FIFO_L_IMUX23_7", + "CMT_TOP_IMUX23_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "CMT_TOP_OCLK_6" + ], + [ + "CMT_FIFO_L_IMUX10_3", + "CMT_TOP_IMUX10_0" + ], + [ + "CMT_FIFO_SE4C3_11", + "CMT_TOP_SE4C3_8" + ], + [ + "CMT_FIFO_WW4END1_7", + "CMT_TOP_WW4END1_4" + ], + [ + "CMT_FIFO_SW4A3_7", + "CMT_TOP_SW4A3_4" + ], + [ + "CMT_FIFO_NW4END2_6", + "CMT_TOP_NW4END2_3" + ], + [ + "CMT_FIFO_LH6_6", + "CMT_TOP_LH6_3" + ], + [ + "CMT_FIFO_L_FAN5_3", + "CMT_TOP_FAN5_0" + ], + [ + "CMT_FIFO_L_IMUX33_8", + "CMT_TOP_IMUX33_5" + ], + [ + "CMT_FIFO_NE4BEG1_7", + "CMT_TOP_NE4BEG1_4" + ], + [ + "CMT_FIFO_L_IMUX43_4", + "CMT_TOP_IMUX43_1" + ], + [ + "CMT_FIFO_L_IMUX8_9", + "CMT_TOP_IMUX8_6" + ], + [ + "CMT_FIFO_L_IMUX19_5", + "CMT_TOP_IMUX19_2" + ], + [ + "CMT_FIFO_L_IMUX41_6", + "CMT_TOP_IMUX41_3" + ], + [ + "CMT_FIFO_L_IMUX38_11", + "CMT_TOP_IMUX38_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_7", + "CMT_TOP_LOGIC_OUTS_L_B16_4" + ], + [ + "CMT_FIFO_LH1_5", + "CMT_TOP_LH1_2" + ], + [ + "CMT_FIFO_L_IMUX1_7", + "CMT_TOP_IMUX1_4" + ], + [ + "CMT_FIFO_NE4BEG2_5", + "CMT_TOP_NE4BEG2_2" + ], + [ + "CMT_FIFO_WW4C3_11", + "CMT_TOP_WW4C3_8" + ], + [ + "CMT_FIFO_L_FAN1_9", + "CMT_TOP_FAN1_6" + ], + [ + "CMT_FIFO_ER1BEG1_4", + "CMT_TOP_ER1BEG1_1" + ], + [ + "CMT_FIFO_L_IMUX29_4", + "CMT_TOP_IMUX29_1" + ], + [ + "CMT_FIFO_SW4END0_3", + "CMT_TOP_SW4END0_0" + ], + [ + "CMT_FIFO_L_BYP7_4", + "CMT_TOP_BYP7_1" + ], + [ + "CMT_FIFO_SE4C2_11", + "CMT_TOP_SE4C2_8" + ], + [ + "CMT_FIFO_NE4C3_11", + "CMT_TOP_NE4C3_8" + ], + [ + "CMT_FIFO_L_FAN3_9", + "CMT_TOP_FAN3_6" + ], + [ + "CMT_FIFO_WR1END0_9", + "CMT_TOP_WR1END0_6" + ], + [ + "CMT_FIFO_SW4A3_4", + "CMT_TOP_SW4A3_1" + ], + [ + "CMT_FIFO_WW4A1_6", + "CMT_TOP_WW4A1_3" + ], + [ + "CMT_FIFO_LH12_9", + "CMT_TOP_LH12_6" + ], + [ + "CMT_FIFO_L_CLK0_7", + "CMT_TOP_CLK0_4" + ], + [ + "CMT_FIFO_EE2BEG2_4", + "CMT_TOP_EE2BEG2_1" + ], + [ + "CMT_FIFO_ER1BEG2_7", + "CMT_TOP_ER1BEG2_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "CMT_TOP_OCLK_8" + ], + [ + "CMT_FIFO_L_IMUX11_4", + "CMT_TOP_IMUX11_1" + ], + [ + "CMT_FIFO_EE2A1_6", + "CMT_TOP_EE2A1_3" + ], + [ + "CMT_FIFO_L_FAN2_10", + "CMT_TOP_FAN2_7" + ], + [ + "CMT_FIFO_EE4BEG1_5", + "CMT_TOP_EE4BEG1_2" + ], + [ + "CMT_FIFO_L_IMUX20_10", + "CMT_TOP_IMUX20_7" + ], + [ + "CMT_FIFO_L_IMUX42_11", + "CMT_TOP_IMUX42_8" + ], + [ + "CMT_FIFO_L_IMUX47_4", + "CMT_TOP_IMUX47_1" + ], + [ + "CMT_FIFO_WW2A3_6", + "CMT_TOP_WW2A3_3" + ], + [ + "CMT_FIFO_SW2A2_6", + "CMT_TOP_SW2A2_3" + ], + [ + "CMT_FIFO_EE2BEG3_6", + "CMT_TOP_EE2BEG3_3" + ], + [ + "CMT_FIFO_L_IMUX41_3", + "CMT_TOP_IMUX41_0" + ], + [ + "CMT_FIFO_L_IMUX22_5", + "CMT_TOP_IMUX22_2" + ], + [ + "CMT_FIFO_L_IMUX13_8", + "CMT_TOP_IMUX13_5" + ], + [ + "CMT_FIFO_SE2A3_3", + "CMT_TOP_SE2A3_0" + ], + [ + "CMT_FIFO_WW4A1_9", + "CMT_TOP_WW4A1_6" + ], + [ + "CMT_FIFO_L_IMUX35_8", + "CMT_TOP_IMUX35_5" + ], + [ + "CMT_FIFO_EE2A1_4", + "CMT_TOP_EE2A1_1" + ], + [ + "CMT_FIFO_L_FAN3_8", + "CMT_TOP_FAN3_5" + ], + [ + "CMT_FIFO_L_FAN5_6", + "CMT_TOP_FAN5_3" + ], + [ + "CMT_FIFO_EL1BEG0_3", + "CMT_TOP_EL1BEG0_0" + ], + [ + "CMT_FIFO_LH10_9", + "CMT_TOP_LH10_6" + ], + [ + "CMT_FIFO_L_IMUX39_5", + "CMT_TOP_IMUX39_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_3", + "CMT_TOP_LOGIC_OUTS_L_B10_0" + ], + [ + "CMT_FIFO_WW4A2_9", + "CMT_TOP_WW4A2_6" + ], + [ + "CMT_FIFO_SW4A1_9", + "CMT_TOP_SW4A1_6" + ], + [ + "CMT_FIFO_LH8_5", + "CMT_TOP_LH8_2" + ], + [ + "CMT_FIFO_WW4B3_9", + "CMT_TOP_WW4B3_6" + ], + [ + "CMT_FIFO_SE4BEG3_3", + "CMT_TOP_SE4BEG3_0" + ], + [ + "CMT_FIFO_L_BYP5_8", + "CMT_TOP_BYP5_5" + ], + [ + "CMT_FIFO_NE4BEG2_6", + "CMT_TOP_NE4BEG2_3" + ], + [ + "CMT_FIFO_LH4_9", + "CMT_TOP_LH4_6" + ], + [ + "CMT_FIFO_L_IMUX19_4", + "CMT_TOP_IMUX19_1" + ], + [ + "CMT_FIFO_NW4END0_10", + "CMT_TOP_NW4END0_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_11", + "CMT_TOP_LOGIC_OUTS_L_B22_8" + ], + [ + "CMT_FIFO_L_BYP0_4", + "CMT_TOP_BYP0_1" + ], + [ + "CMT_FIFO_WW4C0_6", + "CMT_TOP_WW4C0_3" + ], + [ + "CMT_FIFO_L_IMUX29_7", + "CMT_TOP_IMUX29_4" + ], + [ + "CMT_FIFO_L_BYP1_11", + "CMT_TOP_BYP1_8" + ], + [ + "CMT_FIFO_LH7_11", + "CMT_TOP_LH7_8" + ], + [ + "CMT_FIFO_WR1END2_4", + "CMT_TOP_WR1END2_1" + ], + [ + "CMT_FIFO_SE2A3_9", + "CMT_TOP_SE2A3_6" + ], + [ + "CMT_FIFO_NE2A1_9", + "CMT_TOP_NE2A1_6" + ], + [ + "CMT_FIFO_L_IMUX8_4", + "CMT_TOP_IMUX8_1" + ], + [ + "CMT_FIFO_EE4B1_10", + "CMT_TOP_EE4B1_7" + ], + [ + "CMT_FIFO_L_IMUX33_9", + "CMT_TOP_IMUX33_6" + ], + [ + "CMT_FIFO_SW2A3_3", + "CMT_TOP_SW2A3_0" + ], + [ + "CMT_FIFO_NW2A3_6", + "CMT_TOP_NW2A3_3" + ], + [ + "CMT_FIFO_WW2END2_8", + "CMT_TOP_WW2END2_5" + ], + [ + "CMT_FIFO_EE2BEG0_8", + "CMT_TOP_EE2BEG0_5" + ], + [ + "CMT_FIFO_LH9_6", + "CMT_TOP_LH9_3" + ], + [ + "CMT_FIFO_L_IMUX2_4", + "CMT_TOP_IMUX2_1" + ], + [ + "CMT_FIFO_L_IMUX5_7", + "CMT_TOP_IMUX5_4" + ], + [ + "CMT_FIFO_L_FAN1_5", + "CMT_TOP_FAN1_2" + ], + [ + "CMT_FIFO_LH5_7", + "CMT_TOP_LH5_4" + ], + [ + "CMT_FIFO_L_IMUX35_10", + "CMT_TOP_IMUX35_7" + ], + [ + "CMT_FIFO_WW4C3_6", + "CMT_TOP_WW4C3_3" + ], + [ + "CMT_FIFO_LH8_6", + "CMT_TOP_LH8_3" + ], + [ + "CMT_FIFO_LH3_6", + "CMT_TOP_LH3_3" + ], + [ + "CMT_FIFO_NE4BEG1_8", + "CMT_TOP_NE4BEG1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_4", + "CMT_TOP_LOGIC_OUTS_L_B20_1" + ], + [ + "CMT_FIFO_EE2BEG3_11", + "CMT_TOP_EE2BEG3_8" + ], + [ + "CMT_FIFO_NW4END2_7", + "CMT_TOP_NW4END2_4" + ], + [ + "CMT_FIFO_WL1END1_3", + "CMT_TOP_WL1END1_0" + ], + [ + "CMT_FIFO_NE4BEG0_3", + "CMT_TOP_NE4BEG0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_3", + "CMT_TOP_LOGIC_OUTS_L_B9_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_7", + "CMT_TOP_LOGIC_OUTS_L_B18_4" + ], + [ + "CMT_FIFO_L_IMUX21_9", + "CMT_TOP_IMUX21_6" + ], + [ + "CMT_FIFO_L_IMUX0_3", + "CMT_TOP_IMUX0_0" + ], + [ + "CMT_FIFO_WW4B0_5", + "CMT_TOP_WW4B0_2" + ], + [ + "CMT_FIFO_WW4END1_3", + "CMT_TOP_WW4END1_0" + ], + [ + "CMT_FIFO_WW2END3_8", + "CMT_TOP_WW2END3_5" + ], + [ + "CMT_FIFO_EE4A0_8", + "CMT_TOP_EE4A0_5" + ], + [ + "CMT_FIFO_WW4END1_4", + "CMT_TOP_WW4END1_1" + ], + [ + "CMT_FIFO_LH2_4", + "CMT_TOP_LH2_1" + ], + [ + "CMT_FIFO_WW4C3_3", + "CMT_TOP_WW4C3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_10", + "CMT_TOP_LOGIC_OUTS_L_B15_7" + ], + [ + "CMT_FIFO_L_BYP5_10", + "CMT_TOP_BYP5_7" + ], + [ + "CMT_FIFO_EE4A3_3", + "CMT_TOP_EE4A3_0" + ], + [ + "CMT_FIFO_EE4A1_11", + "CMT_TOP_EE4A1_8" + ], + [ + "CMT_FIFO_L_IMUX46_6", + "CMT_TOP_IMUX46_3" + ], + [ + "CMT_FIFO_SW4A1_10", + "CMT_TOP_SW4A1_7" + ], + [ + "CMT_FIFO_L_IMUX20_8", + "CMT_TOP_IMUX20_5" + ], + [ + "CMT_FIFO_LH7_5", + "CMT_TOP_LH7_2" + ], + [ + "CMT_FIFO_L_IMUX31_3", + "CMT_TOP_IMUX31_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_3", + "CMT_TOP_LOGIC_OUTS_L_B11_0" + ], + [ + "CMT_FIFO_L_IMUX17_6", + "CMT_TOP_IMUX17_3" + ], + [ + "CMT_FIFO_WL1END0_8", + "CMT_TOP_WL1END0_5" + ], + [ + "CMT_FIFO_WR1END3_7", + "CMT_TOP_WR1END3_4" + ], + [ + "CMT_FIFO_SW4A3_11", + "CMT_TOP_SW4A3_8" + ], + [ + "CMT_FIFO_L_IMUX2_7", + "CMT_TOP_IMUX2_4" + ], + [ + "CMT_FIFO_SW2A3_4", + "CMT_TOP_SW2A3_1" + ], + [ + "CMT_FIFO_SE4BEG3_4", + "CMT_TOP_SE4BEG3_1" + ], + [ + "CMT_FIFO_EE2A0_3", + "CMT_TOP_EE2A0_0" + ], + [ + "CMT_FIFO_ER1BEG1_8", + "CMT_TOP_ER1BEG1_5" + ], + [ + "CMT_FIFO_L_IMUX47_11", + "CMT_TOP_IMUX47_8" + ], + [ + "CMT_FIFO_L_IMUX28_5", + "CMT_TOP_IMUX28_2" + ], + [ + "CMT_FIFO_L_FAN6_6", + "CMT_TOP_FAN6_3" + ], + [ + "CMT_FIFO_L_IMUX47_7", + "CMT_TOP_IMUX47_4" + ], + [ + "CMT_FIFO_SW4END0_7", + "CMT_TOP_SW4END0_4" + ], + [ + "CMT_FIFO_L_IMUX13_4", + "CMT_TOP_IMUX13_1" + ], + [ + "CMT_FIFO_SW4A1_4", + "CMT_TOP_SW4A1_1" + ], + [ + "CMT_FIFO_L_BYP6_10", + "CMT_TOP_BYP6_7" + ], + [ + "CMT_FIFO_NW4END0_7", + "CMT_TOP_NW4END0_4" + ], + [ + "CMT_FIFO_SE4BEG1_6", + "CMT_TOP_SE4BEG1_3" + ], + [ + "CMT_FIFO_LH5_11", + "CMT_TOP_LH5_8" + ], + [ + "CMT_FIFO_EE2BEG0_6", + "CMT_TOP_EE2BEG0_3" + ], + [ + "CMT_FIFO_L_BYP6_6", + "CMT_TOP_BYP6_3" + ], + [ + "CMT_FIFO_L_IMUX27_8", + "CMT_TOP_IMUX27_5" + ], + [ + "CMT_FIFO_NW4A2_5", + "CMT_TOP_NW4A2_2" + ], + [ + "CMT_FIFO_L_IMUX24_5", + "CMT_TOP_IMUX24_2" + ], + [ + "CMT_FIFO_L_IMUX32_7", + "CMT_TOP_IMUX32_4" + ], + [ + "CMT_FIFO_L_IMUX37_5", + "CMT_TOP_IMUX37_2" + ], + [ + "CMT_FIFO_LH2_9", + "CMT_TOP_LH2_6" + ], + [ + "CMT_FIFO_WW4END3_8", + "CMT_TOP_WW4END3_5" + ], + [ + "CMT_FIFO_EE4C2_9", + "CMT_TOP_EE4C2_6" + ], + [ + "CMT_FIFO_SW4A1_8", + "CMT_TOP_SW4A1_5" + ], + [ + "CMT_FIFO_NE4BEG0_5", + "CMT_TOP_NE4BEG0_2" + ], + [ + "CMT_FIFO_L_CLK0_6", + "CMT_TOP_CLK0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_4", + "CMT_TOP_LOGIC_OUTS_L_B17_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_5", + "CMT_TOP_LOGIC_OUTS_L_B18_2" + ], + [ + "CMT_FIFO_SW2A2_9", + "CMT_TOP_SW2A2_6" + ], + [ + "CMT_FIFO_LH4_11", + "CMT_TOP_LH4_8" + ], + [ + "CMT_FIFO_SE4C0_10", + "CMT_TOP_SE4C0_7" + ], + [ + "CMT_FIFO_EL1BEG0_11", + "CMT_TOP_EL1BEG0_8" + ], + [ + "CMT_FIFO_EE2A2_8", + "CMT_TOP_EE2A2_5" + ], + [ + "CMT_FIFO_EE4C0_7", + "CMT_TOP_EE4C0_4" + ], + [ + "CMT_FIFO_WW2END1_9", + "CMT_TOP_WW2END1_6" + ], + [ + "CMT_FIFO_WW2END2_3", + "CMT_TOP_WW2END2_0" + ], + [ + "CMT_FIFO_SE4C0_9", + "CMT_TOP_SE4C0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_7", + "CMT_TOP_LOGIC_OUTS_L_B15_4" + ], + [ + "CMT_FIFO_L_IMUX15_8", + "CMT_TOP_IMUX15_5" + ], + [ + "CMT_FIFO_L_BYP2_6", + "CMT_TOP_BYP2_3" + ], + [ + "CMT_FIFO_L_CTRL0_10", + "CMT_TOP_CTRL0_7" + ], + [ + "CMT_FIFO_SE4C3_8", + "CMT_TOP_SE4C3_5" + ], + [ + "CMT_FIFO_L_IMUX25_9", + "CMT_TOP_IMUX25_6" + ], + [ + "CMT_FIFO_L_IMUX36_10", + "CMT_TOP_IMUX36_7" + ], + [ + "CMT_FIFO_LH7_7", + "CMT_TOP_LH7_4" + ], + [ + "CMT_FIFO_SE4BEG0_10", + "CMT_TOP_SE4BEG0_7" + ], + [ + "CMT_FIFO_EE4B3_6", + "CMT_TOP_EE4B3_3" + ], + [ + "CMT_FIFO_L_IMUX1_6", + "CMT_TOP_IMUX1_3" + ], + [ + "CMT_FIFO_NE4C1_7", + "CMT_TOP_NE4C1_4" + ], + [ + "CMT_FIFO_NW4END1_9", + "CMT_TOP_NW4END1_6" + ], + [ + "CMT_FIFO_NW4A2_4", + "CMT_TOP_NW4A2_1" + ], + [ + "CMT_FIFO_EE4A2_3", + "CMT_TOP_EE4A2_0" + ], + [ + "CMT_FIFO_WR1END2_9", + "CMT_TOP_WR1END2_6" + ], + [ + "CMT_FIFO_L_CTRL0_7", + "CMT_TOP_CTRL0_4" + ], + [ + "CMT_FIFO_SE4BEG1_11", + "CMT_TOP_SE4BEG1_8" + ], + [ + "CMT_FIFO_L_BYP7_10", + "CMT_TOP_BYP7_7" + ], + [ + "CMT_FIFO_EE4C1_10", + "CMT_TOP_EE4C1_7" + ], + [ + "CMT_FIFO_EE4C1_9", + "CMT_TOP_EE4C1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_10", + "CMT_TOP_LOGIC_OUTS_L_B4_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_3", + "CMT_TOP_LOGIC_OUTS_L_B6_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_4", + "CMT_TOP_LOGIC_OUTS_L_B3_1" + ], + [ + "CMT_FIFO_L_IMUX14_5", + "CMT_TOP_IMUX14_2" + ], + [ + "CMT_FIFO_L_IMUX27_10", + "CMT_TOP_IMUX27_7" + ], + [ + "CMT_FIFO_SE4C1_11", + "CMT_TOP_SE4C1_8" + ], + [ + "CMT_FIFO_NW2A2_6", + "CMT_TOP_NW2A2_3" + ], + [ + "CMT_FIFO_LH7_4", + "CMT_TOP_LH7_1" + ], + [ + "CMT_FIFO_L_FAN6_7", + "CMT_TOP_FAN6_4" + ], + [ + "CMT_FIFO_LH6_7", + "CMT_TOP_LH6_4" + ], + [ + "CMT_FIFO_SW2A2_3", + "CMT_TOP_SW2A2_0" + ], + [ + "CMT_FIFO_EE4C1_3", + "CMT_TOP_EE4C1_0" + ], + [ + "CMT_FIFO_L_IMUX18_8", + "CMT_TOP_IMUX18_5" + ], + [ + "CMT_FIFO_EL1BEG0_6", + "CMT_TOP_EL1BEG0_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "CMT_TOP_ICLKDIV_1" + ], + [ + "CMT_FIFO_L_IMUX30_7", + "CMT_TOP_IMUX30_4" + ], + [ + "CMT_FIFO_WW2A1_9", + "CMT_TOP_WW2A1_6" + ], + [ + "CMT_FIFO_EE2BEG2_9", + "CMT_TOP_EE2BEG2_6" + ], + [ + "CMT_FIFO_WW4A3_6", + "CMT_TOP_WW4A3_3" + ], + [ + "CMT_FIFO_NE4C0_7", + "CMT_TOP_NE4C0_4" + ], + [ + "CMT_FIFO_SE4BEG2_8", + "CMT_TOP_SE4BEG2_5" + ], + [ + "CMT_FIFO_EE4A1_5", + "CMT_TOP_EE4A1_2" + ], + [ + "CMT_FIFO_LH8_8", + "CMT_TOP_LH8_5" + ], + [ + "CMT_FIFO_L_IMUX11_8", + "CMT_TOP_IMUX11_5" + ], + [ + "CMT_FIFO_WL1END2_7", + "CMT_TOP_WL1END2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_3", + "CMT_TOP_LOGIC_OUTS_L_B21_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_5", + "CMT_TOP_LOGIC_OUTS_L_B23_2" + ], + [ + "CMT_FIFO_L_IMUX27_6", + "CMT_TOP_IMUX27_3" + ], + [ + "CMT_FIFO_LH11_10", + "CMT_TOP_LH11_7" + ], + [ + "CMT_FIFO_L_IMUX38_6", + "CMT_TOP_IMUX38_3" + ], + [ + "CMT_FIFO_L_CTRL0_5", + "CMT_TOP_CTRL0_2" + ], + [ + "CMT_FIFO_WW2END3_3", + "CMT_TOP_WW2END3_0" + ], + [ + "CMT_FIFO_SE4BEG1_9", + "CMT_TOP_SE4BEG1_6" + ], + [ + "CMT_FIFO_NE2A0_6", + "CMT_TOP_NE2A0_3" + ], + [ + "CMT_FIFO_SE2A3_7", + "CMT_TOP_SE2A3_4" + ], + [ + "CMT_FIFO_ER1BEG2_5", + "CMT_TOP_ER1BEG2_2" + ], + [ + "CMT_FIFO_SE4BEG2_11", + "CMT_TOP_SE4BEG2_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "CMT_TOP_ICLKDIV_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "CMT_TOP_ICLK_6" + ], + [ + "CMT_FIFO_NE2A3_10", + "CMT_TOP_NE2A3_7" + ], + [ + "CMT_FIFO_L_BYP7_8", + "CMT_TOP_BYP7_5" + ], + [ + "CMT_FIFO_L_IMUX34_10", + "CMT_TOP_IMUX34_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_9", + "CMT_TOP_LOGIC_OUTS_L_B5_6" + ], + [ + "CMT_FIFO_L_IMUX6_3", + "CMT_TOP_IMUX6_0" + ], + [ + "CMT_FIFO_WW4A2_4", + "CMT_TOP_WW4A2_1" + ], + [ + "CMT_FIFO_SE2A1_10", + "CMT_TOP_SE2A1_7" + ], + [ + "CMT_FIFO_L_IMUX42_5", + "CMT_TOP_IMUX42_2" + ], + [ + "CMT_FIFO_WR1END3_3", + "CMT_TOP_WR1END3_0" + ], + [ + "CMT_FIFO_WR1END3_9", + "CMT_TOP_WR1END3_6" + ], + [ + "CMT_FIFO_L_CLK0_11", + "CMT_TOP_CLK0_8" + ], + [ + "CMT_FIFO_L_IMUX36_6", + "CMT_TOP_IMUX36_3" + ], + [ + "CMT_FIFO_SW4END0_5", + "CMT_TOP_SW4END0_2" + ], + [ + "CMT_FIFO_SE4BEG1_7", + "CMT_TOP_SE4BEG1_4" + ], + [ + "CMT_FIFO_NW4A0_4", + "CMT_TOP_NW4A0_1" + ], + [ + "CMT_FIFO_LH2_7", + "CMT_TOP_LH2_4" + ], + [ + "CMT_FIFO_L_IMUX42_3", + "CMT_TOP_IMUX42_0" + ], + [ + "CMT_FIFO_EE4BEG0_6", + "CMT_TOP_EE4BEG0_3" + ], + [ + "CMT_FIFO_EL1BEG0_5", + "CMT_TOP_EL1BEG0_2" + ], + [ + "CMT_FIFO_NE4BEG0_8", + "CMT_TOP_NE4BEG0_5" + ], + [ + "CMT_FIFO_WW2A1_11", + "CMT_TOP_WW2A1_8" + ], + [ + "CMT_FIFO_SW4END3_8", + "CMT_TOP_SW4END3_5" + ], + [ + "CMT_FIFO_L_BYP2_9", + "CMT_TOP_BYP2_6" + ], + [ + "CMT_FIFO_LH1_3", + "CMT_TOP_LH1_0" + ], + [ + "CMT_FIFO_L_BYP0_8", + "CMT_TOP_BYP0_5" + ], + [ + "CMT_FIFO_NE4C0_4", + "CMT_TOP_NE4C0_1" + ], + [ + "CMT_FIFO_L_IMUX45_6", + "CMT_TOP_IMUX45_3" + ], + [ + "CMT_FIFO_L_FAN3_3", + "CMT_TOP_FAN3_0" + ], + [ + "CMT_FIFO_SW4A0_4", + "CMT_TOP_SW4A0_1" + ], + [ + "CMT_FIFO_ER1BEG0_5", + "CMT_TOP_ER1BEG0_2" + ], + [ + "CMT_FIFO_NW4END3_9", + "CMT_TOP_NW4END3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_9", + "CMT_TOP_LOGIC_OUTS_L_B23_6" + ], + [ + "CMT_FIFO_SE4BEG2_4", + "CMT_TOP_SE4BEG2_1" + ], + [ + "CMT_FIFO_NW4END2_9", + "CMT_TOP_NW4END2_6" + ], + [ + "CMT_FIFO_EE4B2_7", + "CMT_TOP_EE4B2_4" + ], + [ + "CMT_FIFO_NE4BEG1_4", + "CMT_TOP_NE4BEG1_1" + ], + [ + "CMT_FIFO_WR1END1_9", + "CMT_TOP_WR1END1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_8", + "CMT_TOP_LOGIC_OUTS_L_B3_5" + ], + [ + "CMT_FIFO_WW4B1_3", + "CMT_TOP_WW4B1_0" + ], + [ + "CMT_FIFO_L_IMUX21_4", + "CMT_TOP_IMUX21_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_5", + "CMT_TOP_LOGIC_OUTS_L_B21_2" + ], + [ + "CMT_FIFO_NW2A1_5", + "CMT_TOP_NW2A1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "CMT_TOP_ICLKDIV_8" + ], + [ + "CMT_FIFO_L_CTRL0_11", + "CMT_TOP_CTRL0_8" + ], + [ + "CMT_FIFO_WW4B0_6", + "CMT_TOP_WW4B0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_7", + "CMT_TOP_LOGIC_OUTS_L_B6_4" + ], + [ + "CMT_FIFO_L_BYP0_10", + "CMT_TOP_BYP0_7" + ], + [ + "CMT_FIFO_WW4B1_10", + "CMT_TOP_WW4B1_7" + ], + [ + "CMT_FIFO_L_IMUX11_5", + "CMT_TOP_IMUX11_2" + ], + [ + "CMT_FIFO_EE4C0_3", + "CMT_TOP_EE4C0_0" + ], + [ + "CMT_FIFO_L_IMUX25_4", + "CMT_TOP_IMUX25_1" + ], + [ + "CMT_FIFO_L_FAN4_7", + "CMT_TOP_FAN4_4" + ], + [ + "CMT_FIFO_EE4C0_11", + "CMT_TOP_EE4C0_8" + ], + [ + "CMT_FIFO_NE4C3_4", + "CMT_TOP_NE4C3_1" + ], + [ + "CMT_FIFO_WR1END2_7", + "CMT_TOP_WR1END2_4" + ], + [ + "CMT_FIFO_L_IMUX22_11", + "CMT_TOP_IMUX22_8" + ], + [ + "CMT_FIFO_L_IMUX8_3", + "CMT_TOP_IMUX8_0" + ], + [ + "CMT_FIFO_LH11_6", + "CMT_TOP_LH11_3" + ], + [ + "CMT_FIFO_EE4A2_5", + "CMT_TOP_EE4A2_2" + ], + [ + "CMT_FIFO_EE4A3_11", + "CMT_TOP_EE4A3_8" + ], + [ + "CMT_FIFO_L_IMUX40_6", + "CMT_TOP_IMUX40_3" + ], + [ + "CMT_FIFO_SW4END0_8", + "CMT_TOP_SW4END0_5" + ], + [ + "CMT_FIFO_WL1END2_6", + "CMT_TOP_WL1END2_3" + ], + [ + "CMT_FIFO_SW2A2_7", + "CMT_TOP_SW2A2_4" + ], + [ + "CMT_FIFO_NE4BEG1_5", + "CMT_TOP_NE4BEG1_2" + ], + [ + "CMT_FIFO_LH9_9", + "CMT_TOP_LH9_6" + ], + [ + "CMT_FIFO_WW4END0_11", + "CMT_TOP_WW4END0_8" + ], + [ + "CMT_FIFO_EE4C2_6", + "CMT_TOP_EE4C2_3" + ], + [ + "CMT_FIFO_NW4END1_7", + "CMT_TOP_NW4END1_4" + ], + [ + "CMT_FIFO_EE2A3_6", + "CMT_TOP_EE2A3_3" + ], + [ + "CMT_FIFO_L_IMUX19_8", + "CMT_TOP_IMUX19_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_0" + ], + [ + "CMT_FIFO_WW2A1_4", + "CMT_TOP_WW2A1_1" + ], + [ + "CMT_FIFO_L_BYP5_3", + "CMT_TOP_BYP5_0" + ], + [ + "CMT_FIFO_WW4END0_7", + "CMT_TOP_WW4END0_4" + ], + [ + "CMT_FIFO_NE4C2_6", + "CMT_TOP_NE4C2_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "CMT_TOP_OCLKDIV_1" + ], + [ + "CMT_FIFO_L_FAN1_4", + "CMT_TOP_FAN1_1" + ], + [ + "CMT_FIFO_EE4B3_10", + "CMT_TOP_EE4B3_7" + ], + [ + "CMT_FIFO_LH10_6", + "CMT_TOP_LH10_3" + ], + [ + "CMT_FIFO_L_IMUX14_8", + "CMT_TOP_IMUX14_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "CMT_TOP_OCLK_4" + ], + [ + "CMT_FIFO_SE4C2_3", + "CMT_TOP_SE4C2_0" + ], + [ + "CMT_FIFO_SW4END3_9", + "CMT_TOP_SW4END3_6" + ], + [ + "CMT_FIFO_WL1END3_7", + "CMT_TOP_WL1END3_4" + ], + [ + "CMT_FIFO_EE2A3_3", + "CMT_TOP_EE2A3_0" + ], + [ + "CMT_FIFO_WW4B0_3", + "CMT_TOP_WW4B0_0" + ], + [ + "CMT_FIFO_NW4END0_5", + "CMT_TOP_NW4END0_2" + ], + [ + "CMT_FIFO_WW4B0_7", + "CMT_TOP_WW4B0_4" + ], + [ + "CMT_FIFO_L_FAN3_11", + "CMT_TOP_FAN3_8" + ], + [ + "CMT_FIFO_NW2A0_8", + "CMT_TOP_NW2A0_5" + ], + [ + "CMT_FIFO_L_IMUX20_6", + "CMT_TOP_IMUX20_3" + ], + [ + "CMT_FIFO_ER1BEG2_10", + "CMT_TOP_ER1BEG2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_9", + "CMT_TOP_LOGIC_OUTS_L_B16_6" + ], + [ + "CMT_FIFO_L_IMUX12_5", + "CMT_TOP_IMUX12_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_8", + "CMT_TOP_LOGIC_OUTS_L_B19_5" + ], + [ + "CMT_FIFO_MONITOR_N_4", + "CMT_TOP_MONITOR_N_1" + ], + [ + "CMT_FIFO_NE4BEG0_10", + "CMT_TOP_NE4BEG0_7" + ], + [ + "CMT_FIFO_L_IMUX38_3", + "CMT_TOP_IMUX38_0" + ], + [ + "CMT_FIFO_L_BYP6_3", + "CMT_TOP_BYP6_0" + ], + [ + "CMT_FIFO_WW4END3_11", + "CMT_TOP_WW4END3_8" + ], + [ + "CMT_FIFO_SW4A2_6", + "CMT_TOP_SW4A2_3" + ], + [ + "CMT_FIFO_L_FAN2_3", + "CMT_TOP_FAN2_0" + ], + [ + "CMT_FIFO_SE2A2_7", + "CMT_TOP_SE2A2_4" + ], + [ + "CMT_FIFO_L_FAN7_11", + "CMT_TOP_FAN7_8" + ], + [ + "CMT_FIFO_NW4A1_9", + "CMT_TOP_NW4A1_6" + ], + [ + "CMT_FIFO_L_IMUX15_6", + "CMT_TOP_IMUX15_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_9", + "CMT_TOP_LOGIC_OUTS_L_B2_6" + ], + [ + "CMT_FIFO_WW4A3_5", + "CMT_TOP_WW4A3_2" + ], + [ + "CMT_FIFO_L_IMUX3_4", + "CMT_TOP_IMUX3_1" + ], + [ + "CMT_FIFO_WW4END2_9", + "CMT_TOP_WW4END2_6" + ], + [ + "CMT_FIFO_EE4C1_5", + "CMT_TOP_EE4C1_2" + ], + [ + "CMT_FIFO_L_IMUX45_10", + "CMT_TOP_IMUX45_7" + ], + [ + "CMT_FIFO_EL1BEG0_4", + "CMT_TOP_EL1BEG0_1" + ], + [ + "CMT_FIFO_L_IMUX23_11", + "CMT_TOP_IMUX23_8" + ], + [ + "CMT_FIFO_WW2A3_7", + "CMT_TOP_WW2A3_4" + ], + [ + "CMT_FIFO_EE2BEG3_8", + "CMT_TOP_EE2BEG3_5" + ], + [ + "CMT_FIFO_LH3_9", + "CMT_TOP_LH3_6" + ], + [ + "CMT_FIFO_WW4END1_9", + "CMT_TOP_WW4END1_6" + ], + [ + "CMT_FIFO_L_BYP1_3", + "CMT_TOP_BYP1_0" + ], + [ + "CMT_FIFO_EE2A1_7", + "CMT_TOP_EE2A1_4" + ], + [ + "CMT_FIFO_EE2BEG0_10", + "CMT_TOP_EE2BEG0_7" + ], + [ + "CMT_FIFO_NE2A0_5", + "CMT_TOP_NE2A0_2" + ], + [ + "CMT_FIFO_EE4BEG3_4", + "CMT_TOP_EE4BEG3_1" + ], + [ + "CMT_FIFO_LH1_7", + "CMT_TOP_LH1_4" + ], + [ + "CMT_FIFO_L_IMUX9_7", + "CMT_TOP_IMUX9_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_8", + "CMT_TOP_LOGIC_OUTS_L_B8_5" + ], + [ + "CMT_FIFO_WL1END3_10", + "CMT_TOP_WL1END3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_6", + "CMT_TOP_LOGIC_OUTS_L_B0_3" + ], + [ + "CMT_FIFO_L_IMUX36_8", + "CMT_TOP_IMUX36_5" + ], + [ + "CMT_FIFO_LH9_11", + "CMT_TOP_LH9_8" + ], + [ + "CMT_FIFO_L_FAN0_3", + "CMT_TOP_FAN0_0" + ], + [ + "CMT_FIFO_SW2A0_8", + "CMT_TOP_SW2A0_5" + ], + [ + "CMT_FIFO_LH8_3", + "CMT_TOP_LH8_0" + ], + [ + "CMT_FIFO_L_BYP1_10", + "CMT_TOP_BYP1_7" + ], + [ + "CMT_FIFO_SW2A0_3", + "CMT_TOP_SW2A0_0" + ], + [ + "CMT_FIFO_EE4BEG2_11", + "CMT_TOP_EE4BEG2_8" + ], + [ + "CMT_FIFO_L_IMUX31_10", + "CMT_TOP_IMUX31_7" + ], + [ + "CMT_FIFO_L_IMUX23_8", + "CMT_TOP_IMUX23_5" + ], + [ + "CMT_FIFO_NE2A2_4", + "CMT_TOP_NE2A2_1" + ], + [ + "CMT_FIFO_WW2A2_4", + "CMT_TOP_WW2A2_1" + ], + [ + "CMT_FIFO_L_IMUX33_5", + "CMT_TOP_IMUX33_2" + ], + [ + "CMT_FIFO_L_IMUX47_5", + "CMT_TOP_IMUX47_2" + ], + [ + "CMT_FIFO_L_IMUX16_11", + "CMT_TOP_IMUX16_8" + ], + [ + "CMT_FIFO_EE4B3_8", + "CMT_TOP_EE4B3_5" + ], + [ + "CMT_FIFO_EE2BEG2_8", + "CMT_TOP_EE2BEG2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_5", + "CMT_TOP_LOGIC_OUTS_L_B5_2" + ], + [ + "CMT_FIFO_L_IMUX31_9", + "CMT_TOP_IMUX31_6" + ], + [ + "CMT_FIFO_EL1BEG1_10", + "CMT_TOP_EL1BEG1_7" + ], + [ + "CMT_FIFO_L_IMUX33_4", + "CMT_TOP_IMUX33_1" + ], + [ + "CMT_FIFO_L_FAN6_10", + "CMT_TOP_FAN6_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_10", + "CMT_TOP_LOGIC_OUTS_L_B23_7" + ], + [ + "CMT_FIFO_NE4BEG3_5", + "CMT_TOP_NE4BEG3_2" + ], + [ + "CMT_FIFO_NE2A3_4", + "CMT_TOP_NE2A3_1" + ], + [ + "CMT_FIFO_EE2BEG2_11", + "CMT_TOP_EE2BEG2_8" + ], + [ + "CMT_FIFO_EE4B2_9", + "CMT_TOP_EE4B2_6" + ], + [ + "CMT_FIFO_L_IMUX26_11", + "CMT_TOP_IMUX26_8" + ], + [ + "CMT_FIFO_WL1END0_11", + "CMT_TOP_WL1END0_8" + ], + [ + "CMT_FIFO_WL1END2_10", + "CMT_TOP_WL1END2_7" + ], + [ + "CMT_FIFO_ER1BEG3_5", + "CMT_TOP_ER1BEG3_2" + ], + [ + "CMT_FIFO_WW4C1_9", + "CMT_TOP_WW4C1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_8", + "CMT_TOP_LOGIC_OUTS_L_B17_5" + ], + [ + "CMT_FIFO_WL1END2_8", + "CMT_TOP_WL1END2_5" + ], + [ + "CMT_FIFO_L_IMUX18_3", + "CMT_TOP_IMUX18_0" + ], + [ + "CMT_FIFO_NW2A2_11", + "CMT_TOP_NW2A2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_5", + "CMT_TOP_LOGIC_OUTS_L_B2_2" + ], + [ + "CMT_FIFO_SE2A0_8", + "CMT_TOP_SE2A0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_9", + "CMT_TOP_LOGIC_OUTS_L_B11_6" + ], + [ + "CMT_FIFO_L_IMUX34_5", + "CMT_TOP_IMUX34_2" + ], + [ + "CMT_FIFO_EL1BEG1_11", + "CMT_TOP_EL1BEG1_8" + ], + [ + "CMT_FIFO_L_IMUX32_8", + "CMT_TOP_IMUX32_5" + ], + [ + "CMT_FIFO_L_IMUX19_10", + "CMT_TOP_IMUX19_7" + ], + [ + "CMT_FIFO_EE4C1_4", + "CMT_TOP_EE4C1_1" + ], + [ + "CMT_FIFO_ER1BEG2_4", + "CMT_TOP_ER1BEG2_1" + ], + [ + "CMT_FIFO_NE4C1_5", + "CMT_TOP_NE4C1_2" + ], + [ + "CMT_FIFO_WR1END1_4", + "CMT_TOP_WR1END1_1" + ], + [ + "CMT_FIFO_SW2A0_11", + "CMT_TOP_SW2A0_8" + ], + [ + "CMT_FIFO_SE4C3_10", + "CMT_TOP_SE4C3_7" + ], + [ + "CMT_FIFO_L_CTRL0_6", + "CMT_TOP_CTRL0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_10", + "CMT_TOP_LOGIC_OUTS_L_B12_7" + ], + [ + "CMT_FIFO_EE4BEG1_7", + "CMT_TOP_EE4BEG1_4" + ], + [ + "CMT_FIFO_L_CTRL0_9", + "CMT_TOP_CTRL0_6" + ], + [ + "CMT_FIFO_EE2BEG0_4", + "CMT_TOP_EE2BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_4", + "CMT_TOP_LOGIC_OUTS_L_B10_1" + ], + [ + "CMT_FIFO_NW2A2_9", + "CMT_TOP_NW2A2_6" + ], + [ + "CMT_FIFO_MONITOR_P_4", + "CMT_TOP_MONITOR_P_1" + ], + [ + "CMT_FIFO_NW2A2_8", + "CMT_TOP_NW2A2_5" + ], + [ + "CMT_FIFO_L_BYP2_11", + "CMT_TOP_BYP2_8" + ], + [ + "CMT_FIFO_L_IMUX18_10", + "CMT_TOP_IMUX18_7" + ], + [ + "CMT_FIFO_WW4A2_10", + "CMT_TOP_WW4A2_7" + ], + [ + "CMT_FIFO_L_IMUX5_6", + "CMT_TOP_IMUX5_3" + ], + [ + "CMT_FIFO_L_IMUX28_6", + "CMT_TOP_IMUX28_3" + ], + [ + "CMT_FIFO_L_BYP3_4", + "CMT_TOP_BYP3_1" + ], + [ + "CMT_FIFO_L_IMUX20_11", + "CMT_TOP_IMUX20_8" + ], + [ + "CMT_FIFO_SW2A1_11", + "CMT_TOP_SW2A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_11", + "CMT_TOP_LOGIC_OUTS_L_B13_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_8", + "CMT_TOP_LOGIC_OUTS_L_B16_5" + ], + [ + "CMT_FIFO_WL1END1_8", + "CMT_TOP_WL1END1_5" + ], + [ + "CMT_FIFO_L_IMUX37_9", + "CMT_TOP_IMUX37_6" + ], + [ + "CMT_FIFO_ER1BEG2_8", + "CMT_TOP_ER1BEG2_5" + ], + [ + "CMT_FIFO_WL1END0_4", + "CMT_TOP_WL1END0_1" + ], + [ + "CMT_FIFO_EE4BEG0_7", + "CMT_TOP_EE4BEG0_4" + ], + [ + "CMT_FIFO_LH7_9", + "CMT_TOP_LH7_6" + ], + [ + "CMT_FIFO_LH1_8", + "CMT_TOP_LH1_5" + ], + [ + "CMT_FIFO_L_CTRL1_10", + "CMT_TOP_CTRL1_7" + ], + [ + "CMT_FIFO_NE4C3_6", + "CMT_TOP_NE4C3_3" + ], + [ + "CMT_FIFO_SW4END2_11", + "CMT_TOP_SW4END2_8" + ], + [ + "CMT_FIFO_NW4A3_9", + "CMT_TOP_NW4A3_6" + ], + [ + "CMT_FIFO_L_IMUX8_8", + "CMT_TOP_IMUX8_5" + ], + [ + "CMT_FIFO_L_FAN4_9", + "CMT_TOP_FAN4_6" + ], + [ + "CMT_FIFO_EE4BEG0_8", + "CMT_TOP_EE4BEG0_5" + ], + [ + "CMT_FIFO_SE4C3_3", + "CMT_TOP_SE4C3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_7", + "CMT_TOP_LOGIC_OUTS_L_B9_4" + ], + [ + "CMT_FIFO_WW4A3_4", + "CMT_TOP_WW4A3_1" + ], + [ + "CMT_FIFO_L_BYP6_8", + "CMT_TOP_BYP6_5" + ], + [ + "CMT_FIFO_WW4B3_7", + "CMT_TOP_WW4B3_4" + ], + [ + "CMT_FIFO_L_IMUX18_11", + "CMT_TOP_IMUX18_8" + ], + [ + "CMT_FIFO_L_IMUX31_7", + "CMT_TOP_IMUX31_4" + ], + [ + "CMT_FIFO_L_IMUX3_9", + "CMT_TOP_IMUX3_6" + ], + [ + "CMT_FIFO_NW2A2_3", + "CMT_TOP_NW2A2_0" + ], + [ + "CMT_FIFO_L_IMUX25_3", + "CMT_TOP_IMUX25_0" + ], + [ + "CMT_FIFO_SW4A2_5", + "CMT_TOP_SW4A2_2" + ], + [ + "CMT_FIFO_SE4BEG3_6", + "CMT_TOP_SE4BEG3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_7", + "CMT_TOP_LOGIC_OUTS_L_B13_4" + ], + [ + "CMT_FIFO_L_IMUX11_10", + "CMT_TOP_IMUX11_7" + ], + [ + "CMT_FIFO_L_IMUX9_3", + "CMT_TOP_IMUX9_0" + ], + [ + "CMT_FIFO_WR1END0_11", + "CMT_TOP_WR1END0_8" + ], + [ + "CMT_FIFO_SW4A2_4", + "CMT_TOP_SW4A2_1" + ], + [ + "CMT_FIFO_ER1BEG0_8", + "CMT_TOP_ER1BEG0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_3", + "CMT_TOP_LOGIC_OUTS_L_B3_0" + ], + [ + "CMT_FIFO_SW4A2_10", + "CMT_TOP_SW4A2_7" + ], + [ + "CMT_FIFO_NE4C1_4", + "CMT_TOP_NE4C1_1" + ], + [ + "CMT_FIFO_EE2A3_8", + "CMT_TOP_EE2A3_5" + ], + [ + "CMT_FIFO_LH11_8", + "CMT_TOP_LH11_5" + ], + [ + "CMT_FIFO_NW4A1_5", + "CMT_TOP_NW4A1_2" + ], + [ + "CMT_FIFO_L_IMUX27_11", + "CMT_TOP_IMUX27_8" + ], + [ + "CMT_FIFO_L_FAN2_11", + "CMT_TOP_FAN2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_7", + "CMT_TOP_LOGIC_OUTS_L_B1_4" + ], + [ + "CMT_FIFO_WW4B0_11", + "CMT_TOP_WW4B0_8" + ], + [ + "CMT_FIFO_L_IMUX34_11", + "CMT_TOP_IMUX34_8" + ], + [ + "CMT_FIFO_WL1END3_6", + "CMT_TOP_WL1END3_3" + ], + [ + "CMT_FIFO_SW4A1_6", + "CMT_TOP_SW4A1_3" + ], + [ + "CMT_FIFO_WW2END3_10", + "CMT_TOP_WW2END3_7" + ], + [ + "CMT_FIFO_L_BYP3_8", + "CMT_TOP_BYP3_5" + ], + [ + "CMT_FIFO_WW4END3_7", + "CMT_TOP_WW4END3_4" + ], + [ + "CMT_FIFO_NW4A1_6", + "CMT_TOP_NW4A1_3" + ], + [ + "CMT_FIFO_LH10_11", + "CMT_TOP_LH10_8" + ], + [ + "CMT_FIFO_LH10_8", + "CMT_TOP_LH10_5" + ], + [ + "CMT_FIFO_L_CLK0_3", + "CMT_TOP_CLK0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_6", + "CMT_TOP_LOGIC_OUTS_L_B19_3" + ], + [ + "CMT_FIFO_L_IMUX4_8", + "CMT_TOP_IMUX4_5" + ], + [ + "CMT_FIFO_L_IMUX45_3", + "CMT_TOP_IMUX45_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "CMT_TOP_OCLKDIV_5" + ], + [ + "CMT_FIFO_NW4A0_9", + "CMT_TOP_NW4A0_6" + ], + [ + "CMT_FIFO_EE2BEG2_6", + "CMT_TOP_EE2BEG2_3" + ], + [ + "CMT_FIFO_L_FAN1_3", + "CMT_TOP_FAN1_0" + ], + [ + "CMT_FIFO_L_IMUX4_9", + "CMT_TOP_IMUX4_6" + ], + [ + "CMT_FIFO_WW2A1_3", + "CMT_TOP_WW2A1_0" + ], + [ + "CMT_FIFO_SE2A2_6", + "CMT_TOP_SE2A2_3" + ], + [ + "CMT_FIFO_LH12_3", + "CMT_TOP_LH12_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "CMT_TOP_OCLK_5" + ], + [ + "CMT_FIFO_SE4C1_6", + "CMT_TOP_SE4C1_3" + ], + [ + "CMT_FIFO_ER1BEG1_10", + "CMT_TOP_ER1BEG1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_4", + "CMT_TOP_LOGIC_OUTS_L_B19_1" + ], + [ + "CMT_FIFO_WR1END3_10", + "CMT_TOP_WR1END3_7" + ], + [ + "CMT_FIFO_EE4A1_4", + "CMT_TOP_EE4A1_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "CMT_TOP_OCLKDIV_8" + ], + [ + "CMT_FIFO_L_IMUX31_8", + "CMT_TOP_IMUX31_5" + ], + [ + "CMT_FIFO_EE4BEG1_10", + "CMT_TOP_EE4BEG1_7" + ], + [ + "CMT_FIFO_NE2A3_3", + "CMT_TOP_NE2A3_0" + ], + [ + "CMT_FIFO_L_IMUX15_9", + "CMT_TOP_IMUX15_6" + ], + [ + "CMT_FIFO_L_IMUX45_7", + "CMT_TOP_IMUX45_4" + ], + [ + "CMT_FIFO_WW4END3_6", + "CMT_TOP_WW4END3_3" + ], + [ + "CMT_FIFO_WW4C0_10", + "CMT_TOP_WW4C0_7" + ], + [ + "CMT_FIFO_SE2A3_11", + "CMT_TOP_SE2A3_8" + ], + [ + "CMT_FIFO_ER1BEG2_11", + "CMT_TOP_ER1BEG2_8" + ], + [ + "CMT_FIFO_SW4END2_9", + "CMT_TOP_SW4END2_6" + ], + [ + "CMT_FIFO_SW4A1_5", + "CMT_TOP_SW4A1_2" + ], + [ + "CMT_FIFO_L_IMUX23_9", + "CMT_TOP_IMUX23_6" + ], + [ + "CMT_FIFO_EE2A3_7", + "CMT_TOP_EE2A3_4" + ], + [ + "CMT_FIFO_SW2A1_3", + "CMT_TOP_SW2A1_0" + ], + [ + "CMT_FIFO_EL1BEG2_4", + "CMT_TOP_EL1BEG2_1" + ], + [ + "CMT_FIFO_WW4END2_6", + "CMT_TOP_WW4END2_3" + ], + [ + "CMT_FIFO_EE2BEG0_5", + "CMT_TOP_EE2BEG0_2" + ], + [ + "CMT_FIFO_L_BYP6_11", + "CMT_TOP_BYP6_8" + ], + [ + "CMT_FIFO_EE4A1_6", + "CMT_TOP_EE4A1_3" + ], + [ + "CMT_FIFO_SW2A1_10", + "CMT_TOP_SW2A1_7" + ], + [ + "CMT_FIFO_SW4END1_7", + "CMT_TOP_SW4END1_4" + ], + [ + "CMT_FIFO_WL1END3_11", + "CMT_TOP_WL1END3_8" + ], + [ + "CMT_FIFO_LH2_6", + "CMT_TOP_LH2_3" + ], + [ + "CMT_FIFO_NE2A2_7", + "CMT_TOP_NE2A2_4" + ], + [ + "CMT_FIFO_NE2A1_6", + "CMT_TOP_NE2A1_3" + ], + [ + "CMT_FIFO_WW4END2_4", + "CMT_TOP_WW4END2_1" + ], + [ + "CMT_FIFO_EL1BEG1_9", + "CMT_TOP_EL1BEG1_6" + ], + [ + "CMT_FIFO_L_IMUX13_6", + "CMT_TOP_IMUX13_3" + ], + [ + "CMT_FIFO_NW4A1_3", + "CMT_TOP_NW4A1_0" + ], + [ + "CMT_FIFO_WW4C0_8", + "CMT_TOP_WW4C0_5" + ], + [ + "CMT_FIFO_L_IMUX20_9", + "CMT_TOP_IMUX20_6" + ], + [ + "CMT_FIFO_L_IMUX34_6", + "CMT_TOP_IMUX34_3" + ], + [ + "CMT_FIFO_SE4BEG2_3", + "CMT_TOP_SE4BEG2_0" + ], + [ + "CMT_FIFO_NW2A1_11", + "CMT_TOP_NW2A1_8" + ], + [ + "CMT_FIFO_L_IMUX27_4", + "CMT_TOP_IMUX27_1" + ], + [ + "CMT_FIFO_EE4BEG2_7", + "CMT_TOP_EE4BEG2_4" + ], + [ + "CMT_FIFO_EE2BEG0_3", + "CMT_TOP_EE2BEG0_0" + ], + [ + "CMT_FIFO_L_IMUX1_5", + "CMT_TOP_IMUX1_2" + ], + [ + "CMT_FIFO_L_IMUX27_5", + "CMT_TOP_IMUX27_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "CMT_TOP_ICLKDIV_0" + ], + [ + "CMT_FIFO_SW4A3_5", + "CMT_TOP_SW4A3_2" + ], + [ + "CMT_FIFO_SW4END1_3", + "CMT_TOP_SW4END1_0" + ], + [ + "CMT_FIFO_L_IMUX6_5", + "CMT_TOP_IMUX6_2" + ], + [ + "CMT_FIFO_L_BYP3_11", + "CMT_TOP_BYP3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_4", + "CMT_TOP_LOGIC_OUTS_L_B11_1" + ], + [ + "CMT_FIFO_WW4END2_8", + "CMT_TOP_WW4END2_5" + ], + [ + "CMT_FIFO_SW2A0_10", + "CMT_TOP_SW2A0_7" + ], + [ + "CMT_FIFO_L_FAN3_7", + "CMT_TOP_FAN3_4" + ], + [ + "CMT_FIFO_EE2BEG1_6", + "CMT_TOP_EE2BEG1_3" + ], + [ + "CMT_FIFO_WL1END1_9", + "CMT_TOP_WL1END1_6" + ], + [ + "CMT_FIFO_NW2A0_7", + "CMT_TOP_NW2A0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_4", + "CMT_TOP_LOGIC_OUTS_L_B12_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_8", + "CMT_TOP_LOGIC_OUTS_L_B13_5" + ], + [ + "CMT_FIFO_L_IMUX46_8", + "CMT_TOP_IMUX46_5" + ], + [ + "CMT_FIFO_EE2A1_10", + "CMT_TOP_EE2A1_7" + ], + [ + "CMT_FIFO_EE4B3_5", + "CMT_TOP_EE4B3_2" + ], + [ + "CMT_FIFO_EE4C1_6", + "CMT_TOP_EE4C1_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "CMT_TOP_OCLK_2" + ], + [ + "CMT_FIFO_NW4END2_8", + "CMT_TOP_NW4END2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_8", + "CMT_TOP_LOGIC_OUTS_L_B0_5" + ], + [ + "CMT_FIFO_SE4BEG1_5", + "CMT_TOP_SE4BEG1_2" + ], + [ + "CMT_FIFO_EL1BEG2_8", + "CMT_TOP_EL1BEG2_5" + ], + [ + "CMT_FIFO_EL1BEG3_4", + "CMT_TOP_EL1BEG3_1" + ], + [ + "CMT_FIFO_NW4END1_4", + "CMT_TOP_NW4END1_1" + ], + [ + "CMT_FIFO_LH9_3", + "CMT_TOP_LH9_0" + ], + [ + "CMT_FIFO_SW4A3_3", + "CMT_TOP_SW4A3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_10", + "CMT_TOP_LOGIC_OUTS_L_B22_7" + ], + [ + "CMT_FIFO_L_CLK0_9", + "CMT_TOP_CLK0_6" + ], + [ + "CMT_FIFO_L_PHASER_RDENABLE", + "CMT_PHASER_OUT_B_RDEN_TOFIFO" + ], + [ + "CMT_FIFO_EE4BEG3_8", + "CMT_TOP_EE4BEG3_5" + ], + [ + "CMT_FIFO_NE4BEG1_9", + "CMT_TOP_NE4BEG1_6" + ], + [ + "CMT_FIFO_L_IMUX38_10", + "CMT_TOP_IMUX38_7" + ], + [ + "CMT_FIFO_NE2A1_10", + "CMT_TOP_NE2A1_7" + ], + [ + "CMT_FIFO_EE2A3_11", + "CMT_TOP_EE2A3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_8", + "CMT_TOP_LOGIC_OUTS_L_B20_5" + ], + [ + "CMT_FIFO_SW4END0_6", + "CMT_TOP_SW4END0_3" + ], + [ + "CMT_FIFO_NE4C1_11", + "CMT_TOP_NE4C1_8" + ], + [ + "CMT_FIFO_EE2BEG1_10", + "CMT_TOP_EE2BEG1_7" + ], + [ + "CMT_FIFO_SE4BEG3_10", + "CMT_TOP_SE4BEG3_7" + ], + [ + "CMT_FIFO_LH12_5", + "CMT_TOP_LH12_2" + ], + [ + "CMT_FIFO_WW2END1_4", + "CMT_TOP_WW2END1_1" + ], + [ + "CMT_FIFO_EE4B1_7", + "CMT_TOP_EE4B1_4" + ], + [ + "CMT_FIFO_L_FAN7_10", + "CMT_TOP_FAN7_7" + ], + [ + "CMT_FIFO_SE4BEG3_9", + "CMT_TOP_SE4BEG3_6" + ], + [ + "CMT_FIFO_NW2A1_4", + "CMT_TOP_NW2A1_1" + ], + [ + "CMT_FIFO_L_IMUX32_6", + "CMT_TOP_IMUX32_3" + ], + [ + "CMT_FIFO_EE4B1_6", + "CMT_TOP_EE4B1_3" + ], + [ + "CMT_FIFO_L_BYP0_7", + "CMT_TOP_BYP0_4" + ], + [ + "CMT_FIFO_WW4END1_11", + "CMT_TOP_WW4END1_8" + ], + [ + "CMT_FIFO_L_IMUX1_8", + "CMT_TOP_IMUX1_5" + ], + [ + "CMT_FIFO_SE4C2_5", + "CMT_TOP_SE4C2_2" + ], + [ + "CMT_FIFO_EE4A2_9", + "CMT_TOP_EE4A2_6" + ], + [ + "CMT_FIFO_EE4A2_6", + "CMT_TOP_EE4A2_3" + ], + [ + "CMT_FIFO_LH5_10", + "CMT_TOP_LH5_7" + ], + [ + "CMT_FIFO_MONITOR_N_10", + "CMT_TOP_MONITOR_N_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_11", + "CMT_TOP_LOGIC_OUTS_L_B23_8" + ], + [ + "CMT_FIFO_WL1END1_10", + "CMT_TOP_WL1END1_7" + ], + [ + "CMT_FIFO_WW4C1_10", + "CMT_TOP_WW4C1_7" + ], + [ + "CMT_FIFO_WW4B3_3", + "CMT_TOP_WW4B3_0" + ], + [ + "CMT_FIFO_EE4B0_11", + "CMT_TOP_EE4B0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_9", + "CMT_TOP_LOGIC_OUTS_L_B12_6" + ], + [ + "CMT_FIFO_L_IMUX37_10", + "CMT_TOP_IMUX37_7" + ], + [ + "CMT_FIFO_SW4END3_5", + "CMT_TOP_SW4END3_2" + ], + [ + "CMT_FIFO_L_IMUX35_11", + "CMT_TOP_IMUX35_8" + ], + [ + "CMT_FIFO_LH9_8", + "CMT_TOP_LH9_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_6", + "CMT_TOP_LOGIC_OUTS_L_B18_3" + ], + [ + "CMT_FIFO_EE4C0_8", + "CMT_TOP_EE4C0_5" + ], + [ + "CMT_FIFO_SW4END2_6", + "CMT_TOP_SW4END2_3" + ], + [ + "CMT_FIFO_WR1END1_3", + "CMT_TOP_WR1END1_0" + ], + [ + "CMT_FIFO_EE4C1_11", + "CMT_TOP_EE4C1_8" + ], + [ + "CMT_FIFO_NE4BEG3_10", + "CMT_TOP_NE4BEG3_7" + ], + [ + "CMT_FIFO_EE4A3_8", + "CMT_TOP_EE4A3_5" + ], + [ + "CMT_FIFO_EE4BEG0_3", + "CMT_TOP_EE4BEG0_0" + ], + [ + "CMT_FIFO_L_BYP0_3", + "CMT_TOP_BYP0_0" + ], + [ + "CMT_FIFO_SW2A3_7", + "CMT_TOP_SW2A3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_6", + "CMT_TOP_LOGIC_OUTS_L_B2_3" + ], + [ + "CMT_FIFO_EL1BEG2_11", + "CMT_TOP_EL1BEG2_8" + ], + [ + "CMT_FIFO_EE4A0_6", + "CMT_TOP_EE4A0_3" + ], + [ + "CMT_FIFO_LH5_6", + "CMT_TOP_LH5_3" + ], + [ + "CMT_FIFO_SE4BEG2_6", + "CMT_TOP_SE4BEG2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_7", + "CMT_TOP_LOGIC_OUTS_L_B2_4" + ], + [ + "CMT_FIFO_NE2A0_7", + "CMT_TOP_NE2A0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_7", + "CMT_TOP_LOGIC_OUTS_L_B20_4" + ], + [ + "CMT_FIFO_EE4A3_5", + "CMT_TOP_EE4A3_2" + ], + [ + "CMT_FIFO_LH8_10", + "CMT_TOP_LH8_7" + ], + [ + "CMT_FIFO_NE2A2_3", + "CMT_TOP_NE2A2_0" + ], + [ + "CMT_FIFO_L_IMUX22_3", + "CMT_TOP_IMUX22_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_10", + "CMT_TOP_LOGIC_OUTS_L_B6_7" + ], + [ + "CMT_FIFO_SE4C3_9", + "CMT_TOP_SE4C3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_6", + "CMT_TOP_LOGIC_OUTS_L_B22_3" + ], + [ + "CMT_FIFO_L_FAN0_10", + "CMT_TOP_FAN0_7" + ], + [ + "CMT_FIFO_EE4B2_11", + "CMT_TOP_EE4B2_8" + ], + [ + "CMT_FIFO_LH8_7", + "CMT_TOP_LH8_4" + ], + [ + "CMT_FIFO_L_IMUX10_10", + "CMT_TOP_IMUX10_7" + ], + [ + "CMT_FIFO_L_IMUX40_7", + "CMT_TOP_IMUX40_4" + ], + [ + "CMT_FIFO_WW2END2_7", + "CMT_TOP_WW2END2_4" + ], + [ + "CMT_FIFO_WW2A3_10", + "CMT_TOP_WW2A3_7" + ], + [ + "CMT_FIFO_L_CTRL1_11", + "CMT_TOP_CTRL1_8" + ], + [ + "CMT_FIFO_WW4END0_6", + "CMT_TOP_WW4END0_3" + ], + [ + "CMT_FIFO_SE2A3_10", + "CMT_TOP_SE2A3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_8", + "CMT_TOP_LOGIC_OUTS_L_B1_5" + ], + [ + "CMT_FIFO_EE4C0_9", + "CMT_TOP_EE4C0_6" + ], + [ + "CMT_FIFO_NW2A0_11", + "CMT_TOP_NW2A0_8" + ], + [ + "CMT_FIFO_L_IMUX28_7", + "CMT_TOP_IMUX28_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_9", + "CMT_TOP_LOGIC_OUTS_L_B17_6" + ], + [ + "CMT_FIFO_EL1BEG1_8", + "CMT_TOP_EL1BEG1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_6", + "CMT_TOP_LOGIC_OUTS_L_B17_3" + ], + [ + "CMT_FIFO_L_IMUX26_8", + "CMT_TOP_IMUX26_5" + ], + [ + "CMT_FIFO_L_IMUX42_4", + "CMT_TOP_IMUX42_1" + ], + [ + "CMT_FIFO_L_IMUX46_7", + "CMT_TOP_IMUX46_4" + ], + [ + "CMT_FIFO_L_IMUX10_8", + "CMT_TOP_IMUX10_5" + ], + [ + "CMT_FIFO_SE4C0_5", + "CMT_TOP_SE4C0_2" + ], + [ + "CMT_FIFO_NW4END1_3", + "CMT_TOP_NW4END1_0" + ], + [ + "CMT_FIFO_WW2A0_4", + "CMT_TOP_WW2A0_1" + ], + [ + "CMT_FIFO_L_IMUX12_6", + "CMT_TOP_IMUX12_3" + ], + [ + "CMT_FIFO_WW4B3_5", + "CMT_TOP_WW4B3_2" + ], + [ + "CMT_FIFO_L_CLK1_10", + "CMT_TOP_CLK1_7" + ], + [ + "CMT_FIFO_L_IMUX16_3", + "CMT_TOP_IMUX16_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_3", + "CMT_TOP_LOGIC_OUTS_L_B17_0" + ], + [ + "CMT_FIFO_L_IMUX9_8", + "CMT_TOP_IMUX9_5" + ], + [ + "CMT_FIFO_L_IMUX18_9", + "CMT_TOP_IMUX18_6" + ], + [ + "CMT_FIFO_L_FAN7_3", + "CMT_TOP_FAN7_0" + ], + [ + "CMT_FIFO_L_FAN5_7", + "CMT_TOP_FAN5_4" + ], + [ + "CMT_FIFO_LH5_3", + "CMT_TOP_LH5_0" + ], + [ + "CMT_FIFO_L_IMUX43_5", + "CMT_TOP_IMUX43_2" + ], + [ + "CMT_FIFO_L_IMUX42_8", + "CMT_TOP_IMUX42_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_1" + ], + [ + "CMT_FIFO_EE2BEG3_7", + "CMT_TOP_EE2BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_7", + "CMT_TOP_LOGIC_OUTS_L_B4_4" + ], + [ + "CMT_FIFO_L_IMUX30_9", + "CMT_TOP_IMUX30_6" + ], + [ + "CMT_FIFO_WW4B1_4", + "CMT_TOP_WW4B1_1" + ], + [ + "CMT_FIFO_EE4C2_4", + "CMT_TOP_EE4C2_1" + ], + [ + "CMT_FIFO_L_IMUX26_10", + "CMT_TOP_IMUX26_7" + ], + [ + "CMT_FIFO_EE2A2_10", + "CMT_TOP_EE2A2_7" + ], + [ + "CMT_FIFO_SE2A1_4", + "CMT_TOP_SE2A1_1" + ], + [ + "CMT_FIFO_L_IMUX30_11", + "CMT_TOP_IMUX30_8" + ], + [ + "CMT_FIFO_L_IMUX24_11", + "CMT_TOP_IMUX24_8" + ], + [ + "CMT_FIFO_L_FAN4_6", + "CMT_TOP_FAN4_3" + ], + [ + "CMT_FIFO_WW4B3_8", + "CMT_TOP_WW4B3_5" + ], + [ + "CMT_FIFO_NW4END3_5", + "CMT_TOP_NW4END3_2" + ], + [ + "CMT_FIFO_NW4END0_6", + "CMT_TOP_NW4END0_3" + ], + [ + "CMT_FIFO_L_CTRL0_4", + "CMT_TOP_CTRL0_1" + ], + [ + "CMT_FIFO_EE4C1_7", + "CMT_TOP_EE4C1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_7", + "CMT_TOP_LOGIC_OUTS_L_B19_4" + ], + [ + "CMT_FIFO_WW2A1_8", + "CMT_TOP_WW2A1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_8", + "CMT_TOP_LOGIC_OUTS_L_B2_5" + ], + [ + "CMT_FIFO_SW2A1_5", + "CMT_TOP_SW2A1_2" + ], + [ + "CMT_FIFO_EE4A1_7", + "CMT_TOP_EE4A1_4" + ], + [ + "CMT_FIFO_L_IMUX42_6", + "CMT_TOP_IMUX42_3" + ], + [ + "CMT_FIFO_EE4B2_6", + "CMT_TOP_EE4B2_3" + ], + [ + "CMT_FIFO_WW4C0_9", + "CMT_TOP_WW4C0_6" + ], + [ + "CMT_FIFO_L_FAN4_10", + "CMT_TOP_FAN4_7" + ], + [ + "CMT_FIFO_WW4END0_3", + "CMT_TOP_WW4END0_0" + ], + [ + "CMT_FIFO_NW2A1_6", + "CMT_TOP_NW2A1_3" + ], + [ + "CMT_FIFO_ER1BEG0_7", + "CMT_TOP_ER1BEG0_4" + ], + [ + "CMT_FIFO_EE4BEG3_7", + "CMT_TOP_EE4BEG3_4" + ], + [ + "CMT_FIFO_L_FAN6_5", + "CMT_TOP_FAN6_2" + ], + [ + "CMT_FIFO_L_IMUX6_7", + "CMT_TOP_IMUX6_4" + ], + [ + "CMT_FIFO_EE4A0_3", + "CMT_TOP_EE4A0_0" + ], + [ + "CMT_FIFO_L_IMUX23_3", + "CMT_TOP_IMUX23_0" + ], + [ + "CMT_FIFO_L_IMUX9_10", + "CMT_TOP_IMUX9_7" + ], + [ + "CMT_FIFO_EE4BEG2_8", + "CMT_TOP_EE4BEG2_5" + ], + [ + "CMT_FIFO_LH5_4", + "CMT_TOP_LH5_1" + ], + [ + "CMT_FIFO_WW4A3_9", + "CMT_TOP_WW4A3_6" + ], + [ + "CMT_FIFO_EE4C3_9", + "CMT_TOP_EE4C3_6" + ], + [ + "CMT_FIFO_NE4BEG3_7", + "CMT_TOP_NE4BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_4", + "CMT_TOP_LOGIC_OUTS_L_B22_1" + ], + [ + "CMT_FIFO_L_FAN0_4", + "CMT_TOP_FAN0_1" + ], + [ + "CMT_FIFO_EE2A0_4", + "CMT_TOP_EE2A0_1" + ], + [ + "CMT_FIFO_WW2END0_7", + "CMT_TOP_WW2END0_4" + ], + [ + "CMT_FIFO_LH4_5", + "CMT_TOP_LH4_2" + ], + [ + "CMT_FIFO_NW4A1_11", + "CMT_TOP_NW4A1_8" + ], + [ + "CMT_FIFO_SW2A1_9", + "CMT_TOP_SW2A1_6" + ], + [ + "CMT_FIFO_SW4A3_9", + "CMT_TOP_SW4A3_6" + ], + [ + "CMT_FIFO_NE2A2_8", + "CMT_TOP_NE2A2_5" + ], + [ + "CMT_FIFO_SE2A2_5", + "CMT_TOP_SE2A2_2" + ], + [ + "CMT_FIFO_LH3_5", + "CMT_TOP_LH3_2" + ], + [ + "CMT_FIFO_NW2A0_3", + "CMT_TOP_NW2A0_0" + ], + [ + "CMT_FIFO_SE2A0_4", + "CMT_TOP_SE2A0_1" + ], + [ + "CMT_FIFO_WW4B2_11", + "CMT_TOP_WW4B2_8" + ], + [ + "CMT_FIFO_NW2A1_9", + "CMT_TOP_NW2A1_6" + ], + [ + "CMT_FIFO_L_FAN7_8", + "CMT_TOP_FAN7_5" + ], + [ + "CMT_FIFO_NW4END3_10", + "CMT_TOP_NW4END3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_7" + ], + [ + "CMT_FIFO_NW2A3_10", + "CMT_TOP_NW2A3_7" + ], + [ + "CMT_FIFO_L_IMUX28_3", + "CMT_TOP_IMUX28_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_7", + "CMT_TOP_LOGIC_OUTS_L_B12_4" + ], + [ + "CMT_FIFO_NW4A3_10", + "CMT_TOP_NW4A3_7" + ], + [ + "CMT_FIFO_L_IMUX9_5", + "CMT_TOP_IMUX9_2" + ], + [ + "CMT_FIFO_WR1END2_3", + "CMT_TOP_WR1END2_0" + ], + [ + "CMT_FIFO_L_IMUX35_3", + "CMT_TOP_IMUX35_0" + ], + [ + "CMT_FIFO_WW2END2_10", + "CMT_TOP_WW2END2_7" + ], + [ + "CMT_FIFO_ER1BEG0_9", + "CMT_TOP_ER1BEG0_6" + ], + [ + "CMT_FIFO_L_PHASER_WRENABLE", + "CMT_PHASER_IN_B_WREN_TOFIFO" + ], + [ + "CMT_FIFO_L_IMUX10_5", + "CMT_TOP_IMUX10_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_5", + "CMT_TOP_LOGIC_OUTS_L_B15_2" + ], + [ + "CMT_FIFO_EE4BEG1_8", + "CMT_TOP_EE4BEG1_5" + ], + [ + "CMT_FIFO_L_IMUX17_3", + "CMT_TOP_IMUX17_0" + ], + [ + "CMT_FIFO_WW2END3_9", + "CMT_TOP_WW2END3_6" + ], + [ + "CMT_FIFO_LH9_4", + "CMT_TOP_LH9_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_4", + "CMT_TOP_LOGIC_OUTS_L_B21_1" + ], + [ + "CMT_FIFO_L_IMUX2_3", + "CMT_TOP_IMUX2_0" + ], + [ + "CMT_FIFO_SE4C0_4", + "CMT_TOP_SE4C0_1" + ], + [ + "CMT_FIFO_L_IMUX44_10", + "CMT_TOP_IMUX44_7" + ], + [ + "CMT_FIFO_WW2END0_11", + "CMT_TOP_WW2END0_8" + ], + [ + "CMT_FIFO_L_IMUX22_7", + "CMT_TOP_IMUX22_4" + ], + [ + "CMT_FIFO_L_IMUX20_5", + "CMT_TOP_IMUX20_2" + ], + [ + "CMT_FIFO_L_IMUX15_10", + "CMT_TOP_IMUX15_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_4", + "CMT_TOP_LOGIC_OUTS_L_B23_1" + ], + [ + "CMT_FIFO_L_IMUX0_10", + "CMT_TOP_IMUX0_7" + ], + [ + "CMT_FIFO_L_IMUX35_9", + "CMT_TOP_IMUX35_6" + ], + [ + "CMT_FIFO_L_CTRL1_7", + "CMT_TOP_CTRL1_4" + ], + [ + "CMT_FIFO_L_BYP4_9", + "CMT_TOP_BYP4_6" + ], + [ + "CMT_FIFO_L_BYP2_3", + "CMT_TOP_BYP2_0" + ], + [ + "CMT_FIFO_L_FAN7_4", + "CMT_TOP_FAN7_1" + ], + [ + "CMT_FIFO_WW4A0_11", + "CMT_TOP_WW4A0_8" + ], + [ + "CMT_FIFO_L_IMUX19_9", + "CMT_TOP_IMUX19_6" + ], + [ + "CMT_FIFO_L_IMUX37_3", + "CMT_TOP_IMUX37_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "CMT_TOP_OCLK_3" + ], + [ + "CMT_FIFO_L_IMUX1_3", + "CMT_TOP_IMUX1_0" + ], + [ + "CMT_FIFO_L_BYP6_4", + "CMT_TOP_BYP6_1" + ], + [ + "CMT_FIFO_L_IMUX34_3", + "CMT_TOP_IMUX34_0" + ], + [ + "CMT_FIFO_NW4A1_8", + "CMT_TOP_NW4A1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_8", + "CMT_TOP_LOGIC_OUTS_L_B9_5" + ], + [ + "CMT_FIFO_NE2A3_9", + "CMT_TOP_NE2A3_6" + ], + [ + "CMT_FIFO_EE4BEG1_11", + "CMT_TOP_EE4BEG1_8" + ], + [ + "CMT_FIFO_NW4END0_8", + "CMT_TOP_NW4END0_5" + ], + [ + "CMT_FIFO_SW2A0_5", + "CMT_TOP_SW2A0_2" + ], + [ + "CMT_FIFO_L_BYP0_5", + "CMT_TOP_BYP0_2" + ], + [ + "CMT_FIFO_WW4B2_10", + "CMT_TOP_WW4B2_7" + ], + [ + "CMT_FIFO_NE2A0_10", + "CMT_TOP_NE2A0_7" + ], + [ + "CMT_FIFO_L_IMUX23_10", + "CMT_TOP_IMUX23_7" + ], + [ + "CMT_FIFO_L_IMUX32_5", + "CMT_TOP_IMUX32_2" + ], + [ + "CMT_FIFO_L_IMUX13_3", + "CMT_TOP_IMUX13_0" + ], + [ + "CMT_FIFO_L_IMUX4_3", + "CMT_TOP_IMUX4_0" + ], + [ + "CMT_FIFO_L_IMUX41_4", + "CMT_TOP_IMUX41_1" + ], + [ + "CMT_FIFO_L_IMUX39_11", + "CMT_TOP_IMUX39_8" + ], + [ + "CMT_FIFO_NW4END3_8", + "CMT_TOP_NW4END3_5" + ], + [ + "CMT_FIFO_LH4_6", + "CMT_TOP_LH4_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_5", + "CMT_TOP_LOGIC_OUTS_L_B1_2" + ], + [ + "CMT_FIFO_WW2END1_3", + "CMT_TOP_WW2END1_0" + ], + [ + "CMT_FIFO_L_IMUX22_10", + "CMT_TOP_IMUX22_7" + ], + [ + "CMT_FIFO_NW2A3_9", + "CMT_TOP_NW2A3_6" + ], + [ + "CMT_FIFO_L_IMUX30_8", + "CMT_TOP_IMUX30_5" + ], + [ + "CMT_FIFO_EE4B0_8", + "CMT_TOP_EE4B0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_4", + "CMT_TOP_LOGIC_OUTS_L_B0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_0" + ], + [ + "CMT_FIFO_L_IMUX27_3", + "CMT_TOP_IMUX27_0" + ], + [ + "CMT_FIFO_L_IMUX16_4", + "CMT_TOP_IMUX16_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_8", + "CMT_TOP_LOGIC_OUTS_L_B11_5" + ], + [ + "CMT_FIFO_NE4BEG0_7", + "CMT_TOP_NE4BEG0_4" + ], + [ + "CMT_FIFO_L_IMUX37_7", + "CMT_TOP_IMUX37_4" + ], + [ + "CMT_FIFO_L_IMUX20_7", + "CMT_TOP_IMUX20_4" + ], + [ + "CMT_FIFO_WW4A0_4", + "CMT_TOP_WW4A0_1" + ], + [ + "CMT_FIFO_L_IMUX33_11", + "CMT_TOP_IMUX33_8" + ], + [ + "CMT_FIFO_NE4C2_7", + "CMT_TOP_NE4C2_4" + ], + [ + "CMT_FIFO_NE4C0_10", + "CMT_TOP_NE4C0_7" + ], + [ + "CMT_FIFO_LH12_7", + "CMT_TOP_LH12_4" + ], + [ + "CMT_FIFO_SW4END3_7", + "CMT_TOP_SW4END3_4" + ], + [ + "CMT_FIFO_SW4A3_10", + "CMT_TOP_SW4A3_7" + ], + [ + "CMT_FIFO_EE4A0_11", + "CMT_TOP_EE4A0_8" + ], + [ + "CMT_FIFO_L_IMUX5_5", + "CMT_TOP_IMUX5_2" + ], + [ + "CMT_FIFO_L_IMUX25_10", + "CMT_TOP_IMUX25_7" + ], + [ + "CMT_FIFO_EE2BEG3_5", + "CMT_TOP_EE2BEG3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_7", + "CMT_TOP_LOGIC_OUTS_L_B11_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_10", + "CMT_TOP_LOGIC_OUTS_L_B3_7" + ], + [ + "CMT_FIFO_EE2A2_7", + "CMT_TOP_EE2A2_4" + ], + [ + "CMT_FIFO_WL1END3_4", + "CMT_TOP_WL1END3_1" + ], + [ + "CMT_FIFO_WW4C0_3", + "CMT_TOP_WW4C0_0" + ], + [ + "CMT_FIFO_EE4BEG2_6", + "CMT_TOP_EE4BEG2_3" + ], + [ + "CMT_FIFO_L_FAN1_6", + "CMT_TOP_FAN1_3" + ], + [ + "CMT_FIFO_WW4C1_8", + "CMT_TOP_WW4C1_5" + ], + [ + "CMT_FIFO_L_FAN2_6", + "CMT_TOP_FAN2_3" + ], + [ + "CMT_FIFO_SW4END1_11", + "CMT_TOP_SW4END1_8" + ], + [ + "CMT_FIFO_WW2A0_6", + "CMT_TOP_WW2A0_3" + ], + [ + "CMT_FIFO_WW2A0_9", + "CMT_TOP_WW2A0_6" + ], + [ + "CMT_FIFO_NW2A0_9", + "CMT_TOP_NW2A0_6" + ], + [ + "CMT_FIFO_SW4END3_10", + "CMT_TOP_SW4END3_7" + ], + [ + "CMT_FIFO_WW4END3_3", + "CMT_TOP_WW4END3_0" + ], + [ + "CMT_FIFO_L_CLK1_9", + "CMT_TOP_CLK1_6" + ], + [ + "CMT_FIFO_L_IMUX42_7", + "CMT_TOP_IMUX42_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_9", + "CMT_TOP_LOGIC_OUTS_L_B9_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_11", + "CMT_TOP_LOGIC_OUTS_L_B10_8" + ], + [ + "CMT_FIFO_SW4A0_8", + "CMT_TOP_SW4A0_5" + ], + [ + "CMT_FIFO_WW2END1_6", + "CMT_TOP_WW2END1_3" + ], + [ + "CMT_FIFO_L_IMUX2_11", + "CMT_TOP_IMUX2_8" + ], + [ + "CMT_FIFO_L_IMUX2_10", + "CMT_TOP_IMUX2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_10", + "CMT_TOP_LOGIC_OUTS_L_B9_7" + ], + [ + "CMT_FIFO_WW4A3_11", + "CMT_TOP_WW4A3_8" + ], + [ + "CMT_FIFO_L_IMUX4_5", + "CMT_TOP_IMUX4_2" + ], + [ + "CMT_FIFO_EL1BEG2_3", + "CMT_TOP_EL1BEG2_0" + ], + [ + "CMT_FIFO_LH10_4", + "CMT_TOP_LH10_1" + ], + [ + "CMT_FIFO_L_IMUX21_8", + "CMT_TOP_IMUX21_5" + ], + [ + "CMT_FIFO_L_IMUX7_3", + "CMT_TOP_IMUX7_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_4", + "CMT_TOP_LOGIC_OUTS_L_B4_1" + ], + [ + "CMT_FIFO_L_FAN5_10", + "CMT_TOP_FAN5_7" + ], + [ + "CMT_FIFO_SW4END2_8", + "CMT_TOP_SW4END2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_8", + "CMT_TOP_LOGIC_OUTS_L_B18_5" + ], + [ + "CMT_FIFO_EE2BEG1_3", + "CMT_TOP_EE2BEG1_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_6", + "CMT_TOP_LOGIC_OUTS_L_B10_3" + ], + [ + "CMT_FIFO_L_PHASER_RDCLK", + "CMT_PHASER_OUT_B_RDCLK_TOFIFO" + ], + [ + "CMT_FIFO_NE4C1_6", + "CMT_TOP_NE4C1_3" + ], + [ + "CMT_FIFO_L_IMUX0_9", + "CMT_TOP_IMUX0_6" + ], + [ + "CMT_FIFO_L_IMUX31_4", + "CMT_TOP_IMUX31_1" + ], + [ + "CMT_FIFO_WW4C0_11", + "CMT_TOP_WW4C0_8" + ], + [ + "CMT_FIFO_LH2_8", + "CMT_TOP_LH2_5" + ], + [ + "CMT_FIFO_WR1END3_6", + "CMT_TOP_WR1END3_3" + ], + [ + "CMT_FIFO_MONITOR_P_6", + "CMT_TOP_MONITOR_P_3" + ], + [ + "CMT_FIFO_EE4A2_10", + "CMT_TOP_EE4A2_7" + ], + [ + "CMT_FIFO_L_IMUX2_8", + "CMT_TOP_IMUX2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_11", + "CMT_TOP_LOGIC_OUTS_L_B0_8" + ], + [ + "CMT_FIFO_L_IMUX29_6", + "CMT_TOP_IMUX29_3" + ], + [ + "CMT_FIFO_NW4A2_3", + "CMT_TOP_NW4A2_0" + ], + [ + "CMT_FIFO_L_CTRL1_4", + "CMT_TOP_CTRL1_1" + ], + [ + "CMT_FIFO_NE2A1_3", + "CMT_TOP_NE2A1_0" + ], + [ + "CMT_FIFO_EE2BEG1_7", + "CMT_TOP_EE2BEG1_4" + ], + [ + "CMT_FIFO_SE2A1_5", + "CMT_TOP_SE2A1_2" + ], + [ + "CMT_FIFO_EE4C3_8", + "CMT_TOP_EE4C3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_3", + "CMT_TOP_LOGIC_OUTS_L_B2_0" + ], + [ + "CMT_FIFO_L_IMUX47_10", + "CMT_TOP_IMUX47_7" + ], + [ + "CMT_FIFO_L_IMUX16_8", + "CMT_TOP_IMUX16_5" + ], + [ + "CMT_FIFO_WW2END1_11", + "CMT_TOP_WW2END1_8" + ], + [ + "CMT_FIFO_LH3_10", + "CMT_TOP_LH3_7" + ], + [ + "CMT_FIFO_WL1END0_3", + "CMT_TOP_WL1END0_0" + ], + [ + "CMT_FIFO_L_IMUX37_6", + "CMT_TOP_IMUX37_3" + ], + [ + "CMT_FIFO_LH2_11", + "CMT_TOP_LH2_8" + ], + [ + "CMT_FIFO_L_IMUX17_11", + "CMT_TOP_IMUX17_8" + ], + [ + "CMT_FIFO_NW4A0_7", + "CMT_TOP_NW4A0_4" + ], + [ + "CMT_FIFO_SE4BEG2_5", + "CMT_TOP_SE4BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX18_5", + "CMT_TOP_IMUX18_2" + ], + [ + "CMT_FIFO_L_BYP1_5", + "CMT_TOP_BYP1_2" + ], + [ + "CMT_FIFO_WL1END1_6", + "CMT_TOP_WL1END1_3" + ], + [ + "CMT_FIFO_SE2A0_5", + "CMT_TOP_SE2A0_2" + ], + [ + "CMT_FIFO_LH4_7", + "CMT_TOP_LH4_4" + ], + [ + "CMT_FIFO_WR1END2_11", + "CMT_TOP_WR1END2_8" + ], + [ + "CMT_FIFO_LH12_11", + "CMT_TOP_LH12_8" + ], + [ + "CMT_FIFO_L_FAN4_5", + "CMT_TOP_FAN4_2" + ], + [ + "CMT_FIFO_WW4END1_5", + "CMT_TOP_WW4END1_2" + ], + [ + "CMT_FIFO_EE2A3_4", + "CMT_TOP_EE2A3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_11", + "CMT_TOP_LOGIC_OUTS_L_B18_8" + ], + [ + "CMT_FIFO_WL1END1_11", + "CMT_TOP_WL1END1_8" + ], + [ + "CMT_FIFO_L_IMUX44_3", + "CMT_TOP_IMUX44_0" + ], + [ + "CMT_FIFO_LH10_5", + "CMT_TOP_LH10_2" + ], + [ + "CMT_FIFO_L_IMUX17_7", + "CMT_TOP_IMUX17_4" + ], + [ + "CMT_FIFO_L_IMUX5_4", + "CMT_TOP_IMUX5_1" + ], + [ + "CMT_FIFO_LH3_3", + "CMT_TOP_LH3_0" + ], + [ + "CMT_FIFO_L_FAN4_8", + "CMT_TOP_FAN4_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "CMT_TOP_OCLK_7" + ], + [ + "CMT_FIFO_SE4C2_8", + "CMT_TOP_SE4C2_5" + ], + [ + "CMT_FIFO_EE2A1_5", + "CMT_TOP_EE2A1_2" + ], + [ + "CMT_FIFO_SE2A2_11", + "CMT_TOP_SE2A2_8" + ], + [ + "CMT_FIFO_SW2A3_10", + "CMT_TOP_SW2A3_7" + ], + [ + "CMT_FIFO_WW4END0_8", + "CMT_TOP_WW4END0_5" + ], + [ + "CMT_FIFO_SW2A0_9", + "CMT_TOP_SW2A0_6" + ], + [ + "CMT_FIFO_L_IMUX28_11", + "CMT_TOP_IMUX28_8" + ], + [ + "CMT_FIFO_NE2A3_11", + "CMT_TOP_NE2A3_8" + ], + [ + "CMT_FIFO_L_IMUX40_5", + "CMT_TOP_IMUX40_2" + ], + [ + "CMT_FIFO_L_IMUX3_6", + "CMT_TOP_IMUX3_3" + ], + [ + "CMT_FIFO_L_BYP5_7", + "CMT_TOP_BYP5_4" + ], + [ + "CMT_FIFO_EE4C3_6", + "CMT_TOP_EE4C3_3" + ], + [ + "CMT_FIFO_EE4BEG0_9", + "CMT_TOP_EE4BEG0_6" + ], + [ + "CMT_FIFO_L_IMUX44_8", + "CMT_TOP_IMUX44_5" + ], + [ + "CMT_FIFO_L_BYP6_5", + "CMT_TOP_BYP6_2" + ], + [ + "CMT_FIFO_WW4C1_7", + "CMT_TOP_WW4C1_4" + ], + [ + "CMT_FIFO_NE4C2_4", + "CMT_TOP_NE4C2_1" + ], + [ + "CMT_FIFO_WW4END2_5", + "CMT_TOP_WW4END2_2" + ], + [ + "CMT_FIFO_L_IMUX24_6", + "CMT_TOP_IMUX24_3" + ], + [ + "CMT_FIFO_L_IMUX36_5", + "CMT_TOP_IMUX36_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_4", + "CMT_TOP_LOGIC_OUTS_L_B16_1" + ], + [ + "CMT_FIFO_L_IMUX29_9", + "CMT_TOP_IMUX29_6" + ], + [ + "CMT_FIFO_EL1BEG2_7", + "CMT_TOP_EL1BEG2_4" + ], + [ + "CMT_FIFO_EE2A0_10", + "CMT_TOP_EE2A0_7" + ], + [ + "CMT_FIFO_WW4C1_11", + "CMT_TOP_WW4C1_8" + ], + [ + "CMT_FIFO_L_IMUX7_10", + "CMT_TOP_IMUX7_7" + ], + [ + "CMT_FIFO_SW4END1_6", + "CMT_TOP_SW4END1_3" + ], + [ + "CMT_FIFO_SW4END3_4", + "CMT_TOP_SW4END3_1" + ], + [ + "CMT_FIFO_NW2A0_4", + "CMT_TOP_NW2A0_1" + ], + [ + "CMT_FIFO_WW4END0_10", + "CMT_TOP_WW4END0_7" + ], + [ + "CMT_FIFO_SE4BEG2_7", + "CMT_TOP_SE4BEG2_4" + ], + [ + "CMT_FIFO_EE4B2_8", + "CMT_TOP_EE4B2_5" + ], + [ + "CMT_FIFO_SE2A0_7", + "CMT_TOP_SE2A0_4" + ], + [ + "CMT_FIFO_SW4END0_4", + "CMT_TOP_SW4END0_1" + ], + [ + "CMT_FIFO_NW4END3_7", + "CMT_TOP_NW4END3_4" + ], + [ + "CMT_FIFO_WW4B3_10", + "CMT_TOP_WW4B3_7" + ], + [ + "CMT_FIFO_WW4END1_10", + "CMT_TOP_WW4END1_7" + ], + [ + "CMT_FIFO_WW4END0_5", + "CMT_TOP_WW4END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_3", + "CMT_TOP_LOGIC_OUTS_L_B4_0" + ], + [ + "CMT_FIFO_L_IMUX40_9", + "CMT_TOP_IMUX40_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_3", + "CMT_TOP_LOGIC_OUTS_L_B7_0" + ], + [ + "CMT_FIFO_EE2A0_5", + "CMT_TOP_EE2A0_2" + ], + [ + "CMT_FIFO_EL1BEG2_6", + "CMT_TOP_EL1BEG2_3" + ], + [ + "CMT_FIFO_L_IMUX13_7", + "CMT_TOP_IMUX13_4" + ], + [ + "CMT_FIFO_WW2A2_8", + "CMT_TOP_WW2A2_5" + ], + [ + "CMT_FIFO_SE2A0_9", + "CMT_TOP_SE2A0_6" + ], + [ + "CMT_FIFO_NW4A3_3", + "CMT_TOP_NW4A3_0" + ], + [ + "CMT_FIFO_L_BYP3_9", + "CMT_TOP_BYP3_6" + ], + [ + "CMT_FIFO_L_IMUX33_6", + "CMT_TOP_IMUX33_3" + ], + [ + "CMT_FIFO_EE4A2_8", + "CMT_TOP_EE4A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_8", + "CMT_TOP_LOGIC_OUTS_L_B23_5" + ], + [ + "CMT_FIFO_WW4C3_9", + "CMT_TOP_WW4C3_6" + ], + [ + "CMT_FIFO_L_IMUX22_4", + "CMT_TOP_IMUX22_1" + ], + [ + "CMT_FIFO_WW2END2_11", + "CMT_TOP_WW2END2_8" + ], + [ + "CMT_FIFO_SE2A2_8", + "CMT_TOP_SE2A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_9", + "CMT_TOP_LOGIC_OUTS_L_B20_6" + ], + [ + "CMT_FIFO_L_IMUX46_10", + "CMT_TOP_IMUX46_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_11", + "CMT_TOP_LOGIC_OUTS_L_B8_8" + ], + [ + "CMT_FIFO_WR1END0_3", + "CMT_TOP_WR1END0_0" + ], + [ + "CMT_FIFO_WW2A2_5", + "CMT_TOP_WW2A2_2" + ], + [ + "CMT_FIFO_NE2A3_5", + "CMT_TOP_NE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX26_5", + "CMT_TOP_IMUX26_2" + ], + [ + "CMT_FIFO_L_BYP7_9", + "CMT_TOP_BYP7_6" + ], + [ + "CMT_FIFO_SE2A2_9", + "CMT_TOP_SE2A2_6" + ], + [ + "CMT_FIFO_EE4BEG3_11", + "CMT_TOP_EE4BEG3_8" + ], + [ + "CMT_FIFO_LH7_8", + "CMT_TOP_LH7_5" + ], + [ + "CMT_FIFO_WW4A1_10", + "CMT_TOP_WW4A1_7" + ], + [ + "CMT_FIFO_L_IMUX38_7", + "CMT_TOP_IMUX38_4" + ], + [ + "CMT_FIFO_WW2A2_9", + "CMT_TOP_WW2A2_6" + ], + [ + "CMT_FIFO_EE4C3_7", + "CMT_TOP_EE4C3_4" + ], + [ + "CMT_FIFO_EE2BEG0_9", + "CMT_TOP_EE2BEG0_6" + ], + [ + "CMT_FIFO_L_IMUX43_8", + "CMT_TOP_IMUX43_5" + ], + [ + "CMT_FIFO_L_IMUX13_11", + "CMT_TOP_IMUX13_8" + ], + [ + "FIFO_DQS_IOTOPHASER_1", + "CMT_PHASER_DOWN_DQS_TO_PHASER_B" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_10", + "CMT_TOP_LOGIC_OUTS_L_B19_7" + ], + [ + "CMT_FIFO_LH8_11", + "CMT_TOP_LH8_8" + ], + [ + "CMT_FIFO_L_IMUX14_10", + "CMT_TOP_IMUX14_7" + ], + [ + "CMT_FIFO_EE2BEG1_4", + "CMT_TOP_EE2BEG1_1" + ], + [ + "CMT_FIFO_EL1BEG1_3", + "CMT_TOP_EL1BEG1_0" + ], + [ + "CMT_FIFO_L_IMUX2_6", + "CMT_TOP_IMUX2_3" + ], + [ + "CMT_FIFO_LH9_7", + "CMT_TOP_LH9_4" + ], + [ + "CMT_FIFO_L_IMUX35_5", + "CMT_TOP_IMUX35_2" + ], + [ + "CMT_FIFO_L_BYP2_4", + "CMT_TOP_BYP2_1" + ], + [ + "CMT_FIFO_L_CLK0_4", + "CMT_TOP_CLK0_1" + ], + [ + "CMT_FIFO_NE4C1_3", + "CMT_TOP_NE4C1_0" + ], + [ + "CMT_FIFO_L_IMUX2_5", + "CMT_TOP_IMUX2_2" + ], + [ + "CMT_FIFO_SW4END1_8", + "CMT_TOP_SW4END1_5" + ], + [ + "CMT_FIFO_WW2END2_4", + "CMT_TOP_WW2END2_1" + ], + [ + "CMT_FIFO_L_IMUX24_7", + "CMT_TOP_IMUX24_4" + ], + [ + "CMT_FIFO_SW2A0_7", + "CMT_TOP_SW2A0_4" + ], + [ + "CMT_FIFO_EE4BEG1_6", + "CMT_TOP_EE4BEG1_3" + ], + [ + "CMT_FIFO_WW4C3_5", + "CMT_TOP_WW4C3_2" + ], + [ + "CMT_FIFO_L_IMUX26_3", + "CMT_TOP_IMUX26_0" + ], + [ + "CMT_FIFO_SE2A2_3", + "CMT_TOP_SE2A2_0" + ], + [ + "CMT_FIFO_NE2A0_3", + "CMT_TOP_NE2A0_0" + ], + [ + "CMT_FIFO_SE2A1_9", + "CMT_TOP_SE2A1_6" + ], + [ + "CMT_FIFO_EE4C2_10", + "CMT_TOP_EE4C2_7" + ], + [ + "CMT_FIFO_LH12_10", + "CMT_TOP_LH12_7" + ], + [ + "CMT_FIFO_L_IMUX25_5", + "CMT_TOP_IMUX25_2" + ], + [ + "CMT_FIFO_L_IMUX18_7", + "CMT_TOP_IMUX18_4" + ], + [ + "CMT_FIFO_LH9_10", + "CMT_TOP_LH9_7" + ], + [ + "CMT_FIFO_WW4B3_11", + "CMT_TOP_WW4B3_8" + ], + [ + "CMT_FIFO_SE4BEG0_11", + "CMT_TOP_SE4BEG0_8" + ], + [ + "CMT_FIFO_L_BYP6_7", + "CMT_TOP_BYP6_4" + ], + [ + "CMT_FIFO_EE4B2_10", + "CMT_TOP_EE4B2_7" + ], + [ + "CMT_FIFO_L_IMUX9_9", + "CMT_TOP_IMUX9_6" + ], + [ + "CMT_FIFO_L_FAN7_7", + "CMT_TOP_FAN7_4" + ], + [ + "CMT_FIFO_L_IMUX45_4", + "CMT_TOP_IMUX45_1" + ], + [ + "CMT_FIFO_L_IMUX12_10", + "CMT_TOP_IMUX12_7" + ], + [ + "CMT_FIFO_WW4B2_8", + "CMT_TOP_WW4B2_5" + ], + [ + "CMT_FIFO_L_BYP4_8", + "CMT_TOP_BYP4_5" + ], + [ + "CMT_FIFO_EE4B2_5", + "CMT_TOP_EE4B2_2" + ], + [ + "CMT_FIFO_WW4A1_11", + "CMT_TOP_WW4A1_8" + ], + [ + "CMT_FIFO_NE2A2_6", + "CMT_TOP_NE2A2_3" + ], + [ + "CMT_FIFO_L_IMUX17_4", + "CMT_TOP_IMUX17_1" + ], + [ + "CMT_FIFO_L_IMUX42_9", + "CMT_TOP_IMUX42_6" + ], + [ + "CMT_FIFO_WW4C0_5", + "CMT_TOP_WW4C0_2" + ], + [ + "CMT_FIFO_SW4A3_6", + "CMT_TOP_SW4A3_3" + ], + [ + "CMT_FIFO_L_IMUX46_4", + "CMT_TOP_IMUX46_1" + ], + [ + "CMT_FIFO_SE4C2_4", + "CMT_TOP_SE4C2_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "CMT_TOP_ICLKDIV_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_9", + "CMT_TOP_LOGIC_OUTS_L_B18_6" + ], + [ + "CMT_FIFO_L_IMUX8_10", + "CMT_TOP_IMUX8_7" + ], + [ + "CMT_FIFO_WW2A1_6", + "CMT_TOP_WW2A1_3" + ], + [ + "CMT_FIFO_EE4C0_10", + "CMT_TOP_EE4C0_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_6", + "CMT_TOP_LOGIC_OUTS_L_B20_3" + ], + [ + "CMT_FIFO_EE4C0_6", + "CMT_TOP_EE4C0_3" + ], + [ + "CMT_FIFO_L_IMUX3_8", + "CMT_TOP_IMUX3_5" + ], + [ + "CMT_FIFO_NE4BEG1_11", + "CMT_TOP_NE4BEG1_8" + ], + [ + "CMT_FIFO_SE4BEG1_4", + "CMT_TOP_SE4BEG1_1" + ], + [ + "CMT_FIFO_L_CLK1_7", + "CMT_TOP_CLK1_4" + ], + [ + "CMT_FIFO_L_IMUX44_4", + "CMT_TOP_IMUX44_1" + ], + [ + "CMT_FIFO_NW4A3_11", + "CMT_TOP_NW4A3_8" + ], + [ + "CMT_FIFO_WW4A1_7", + "CMT_TOP_WW4A1_4" + ], + [ + "CMT_FIFO_WW4A3_3", + "CMT_TOP_WW4A3_0" + ], + [ + "CMT_FIFO_L_IMUX44_9", + "CMT_TOP_IMUX44_6" + ], + [ + "CMT_FIFO_L_IMUX6_6", + "CMT_TOP_IMUX6_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_10", + "CMT_TOP_LOGIC_OUTS_L_B13_7" + ], + [ + "CMT_FIFO_L_FAN2_8", + "CMT_TOP_FAN2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_6", + "CMT_TOP_LOGIC_OUTS_L_B8_3" + ], + [ + "CMT_FIFO_L_CLK0_5", + "CMT_TOP_CLK0_2" + ], + [ + "CMT_FIFO_EE2A2_3", + "CMT_TOP_EE2A2_0" + ], + [ + "CMT_FIFO_ER1BEG3_8", + "CMT_TOP_ER1BEG3_5" + ], + [ + "CMT_FIFO_L_IMUX33_10", + "CMT_TOP_IMUX33_7" + ], + [ + "CMT_FIFO_L_BYP5_5", + "CMT_TOP_BYP5_2" + ], + [ + "CMT_FIFO_EL1BEG3_8", + "CMT_TOP_EL1BEG3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_5", + "CMT_TOP_LOGIC_OUTS_L_B10_2" + ], + [ + "CMT_FIFO_EE2BEG3_4", + "CMT_TOP_EE2BEG3_1" + ], + [ + "CMT_FIFO_EE2BEG3_3", + "CMT_TOP_EE2BEG3_0" + ], + [ + "CMT_FIFO_L_BYP2_5", + "CMT_TOP_BYP2_2" + ], + [ + "CMT_FIFO_NE2A2_11", + "CMT_TOP_NE2A2_8" + ], + [ + "CMT_FIFO_EE4A3_9", + "CMT_TOP_EE4A3_6" + ], + [ + "CMT_FIFO_NW4END0_3", + "CMT_TOP_NW4END0_0" + ], + [ + "CMT_FIFO_L_IMUX28_9", + "CMT_TOP_IMUX28_6" + ], + [ + "CMT_FIFO_L_IMUX36_7", + "CMT_TOP_IMUX36_4" + ], + [ + "CMT_FIFO_SW4END3_6", + "CMT_TOP_SW4END3_3" + ], + [ + "CMT_FIFO_NE2A2_5", + "CMT_TOP_NE2A2_2" + ], + [ + "CMT_FIFO_EE4B3_3", + "CMT_TOP_EE4B3_0" + ], + [ + "CMT_FIFO_L_IMUX24_10", + "CMT_TOP_IMUX24_7" + ], + [ + "CMT_FIFO_L_IMUX41_8", + "CMT_TOP_IMUX41_5" + ], + [ + "CMT_FIFO_WL1END1_4", + "CMT_TOP_WL1END1_1" + ], + [ + "CMT_FIFO_NW2A2_5", + "CMT_TOP_NW2A2_2" + ], + [ + "CMT_FIFO_SE4BEG1_10", + "CMT_TOP_SE4BEG1_7" + ], + [ + "CMT_FIFO_EE2A2_9", + "CMT_TOP_EE2A2_6" + ], + [ + "CMT_FIFO_NE4BEG3_3", + "CMT_TOP_NE4BEG3_0" + ], + [ + "CMT_FIFO_L_CLK1_3", + "CMT_TOP_CLK1_0" + ], + [ + "CMT_FIFO_WW4C2_9", + "CMT_TOP_WW4C2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_11", + "CMT_TOP_LOGIC_OUTS_L_B9_8" + ], + [ + "CMT_FIFO_ER1BEG0_10", + "CMT_TOP_ER1BEG0_7" + ], + [ + "CMT_FIFO_LH3_7", + "CMT_TOP_LH3_4" + ], + [ + "CMT_FIFO_EE4B0_9", + "CMT_TOP_EE4B0_6" + ], + [ + "CMT_FIFO_NE4BEG3_8", + "CMT_TOP_NE4BEG3_5" + ], + [ + "CMT_FIFO_EE4A2_4", + "CMT_TOP_EE4A2_1" + ], + [ + "CMT_FIFO_EE2A0_11", + "CMT_TOP_EE2A0_8" + ], + [ + "CMT_FIFO_L_BYP5_9", + "CMT_TOP_BYP5_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_8", + "CMT_TOP_LOGIC_OUTS_L_B5_5" + ], + [ + "CMT_FIFO_L_CTRL1_5", + "CMT_TOP_CTRL1_2" + ], + [ + "CMT_FIFO_LH2_10", + "CMT_TOP_LH2_7" + ], + [ + "CMT_FIFO_L_IMUX7_7", + "CMT_TOP_IMUX7_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_2" + ], + [ + "CMT_FIFO_L_IMUX45_5", + "CMT_TOP_IMUX45_2" + ], + [ + "CMT_FIFO_L_IMUX3_11", + "CMT_TOP_IMUX3_8" + ], + [ + "CMT_FIFO_WW4C1_6", + "CMT_TOP_WW4C1_3" + ], + [ + "CMT_FIFO_WW2A1_7", + "CMT_TOP_WW2A1_4" + ], + [ + "CMT_FIFO_NE2A1_4", + "CMT_TOP_NE2A1_1" + ], + [ + "CMT_FIFO_L_IMUX19_3", + "CMT_TOP_IMUX19_0" + ], + [ + "CMT_FIFO_EE2BEG1_11", + "CMT_TOP_EE2BEG1_8" + ], + [ + "CMT_FIFO_L_IMUX41_10", + "CMT_TOP_IMUX41_7" + ], + [ + "CMT_FIFO_WW4END3_5", + "CMT_TOP_WW4END3_2" + ], + [ + "CMT_FIFO_L_IMUX35_7", + "CMT_TOP_IMUX35_4" + ], + [ + "CMT_FIFO_L_IMUX10_6", + "CMT_TOP_IMUX10_3" + ], + [ + "CMT_FIFO_L_IMUX16_7", + "CMT_TOP_IMUX16_4" + ], + [ + "CMT_FIFO_LH6_5", + "CMT_TOP_LH6_2" + ], + [ + "CMT_FIFO_L_IMUX24_8", + "CMT_TOP_IMUX24_5" + ], + [ + "CMT_FIFO_L_IMUX23_4", + "CMT_TOP_IMUX23_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_6", + "CMT_TOP_LOGIC_OUTS_L_B3_3" + ], + [ + "CMT_FIFO_L_CLK1_4", + "CMT_TOP_CLK1_1" + ], + [ + "CMT_FIFO_WW4A0_10", + "CMT_TOP_WW4A0_7" + ], + [ + "CMT_FIFO_SW4END0_9", + "CMT_TOP_SW4END0_6" + ], + [ + "CMT_FIFO_EE4B1_11", + "CMT_TOP_EE4B1_8" + ], + [ + "CMT_FIFO_EL1BEG0_9", + "CMT_TOP_EL1BEG0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_9", + "CMT_TOP_LOGIC_OUTS_L_B3_6" + ], + [ + "CMT_FIFO_L_CTRL1_3", + "CMT_TOP_CTRL1_0" + ], + [ + "CMT_FIFO_ER1BEG3_4", + "CMT_TOP_ER1BEG3_1" + ], + [ + "CMT_FIFO_WW4END2_3", + "CMT_TOP_WW4END2_0" + ], + [ + "CMT_FIFO_WW4A1_3", + "CMT_TOP_WW4A1_0" + ], + [ + "CMT_FIFO_WW2END0_10", + "CMT_TOP_WW2END0_7" + ], + [ + "CMT_FIFO_WW2A1_5", + "CMT_TOP_WW2A1_2" + ], + [ + "CMT_FIFO_NW2A3_11", + "CMT_TOP_NW2A3_8" + ], + [ + "CMT_FIFO_EE4C3_10", + "CMT_TOP_EE4C3_7" + ], + [ + "CMT_FIFO_WW2END3_6", + "CMT_TOP_WW2END3_3" + ], + [ + "CMT_FIFO_WR1END0_5", + "CMT_TOP_WR1END0_2" + ], + [ + "CMT_FIFO_L_IMUX21_11", + "CMT_TOP_IMUX21_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_7", + "CMT_TOP_LOGIC_OUTS_L_B10_4" + ], + [ + "CMT_FIFO_EE2A1_11", + "CMT_TOP_EE2A1_8" + ], + [ + "CMT_FIFO_SE4BEG1_3", + "CMT_TOP_SE4BEG1_0" + ], + [ + "CMT_FIFO_WW4END3_10", + "CMT_TOP_WW4END3_7" + ], + [ + "CMT_FIFO_L_IMUX39_6", + "CMT_TOP_IMUX39_3" + ], + [ + "CMT_FIFO_NE4C3_9", + "CMT_TOP_NE4C3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_9", + "CMT_TOP_LOGIC_OUTS_L_B13_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_4", + "CMT_TOP_LOGIC_OUTS_L_B6_1" + ], + [ + "CMT_FIFO_L_IMUX10_7", + "CMT_TOP_IMUX10_4" + ], + [ + "CMT_FIFO_L_IMUX21_5", + "CMT_TOP_IMUX21_2" + ], + [ + "CMT_FIFO_L_IMUX3_3", + "CMT_TOP_IMUX3_0" + ], + [ + "CMT_FIFO_SE4BEG0_3", + "CMT_TOP_SE4BEG0_0" + ], + [ + "CMT_FIFO_L_IMUX14_7", + "CMT_TOP_IMUX14_4" + ], + [ + "CMT_FIFO_EE2A0_8", + "CMT_TOP_EE2A0_5" + ], + [ + "CMT_FIFO_L_IMUX11_6", + "CMT_TOP_IMUX11_3" + ], + [ + "CMT_FIFO_L_IMUX12_4", + "CMT_TOP_IMUX12_1" + ], + [ + "CMT_FIFO_NW4A2_9", + "CMT_TOP_NW4A2_6" + ], + [ + "CMT_FIFO_NE4C0_8", + "CMT_TOP_NE4C0_5" + ], + [ + "CMT_FIFO_L_CLK1_5", + "CMT_TOP_CLK1_2" + ], + [ + "CMT_FIFO_EE4A1_9", + "CMT_TOP_EE4A1_6" + ], + [ + "CMT_FIFO_SE4BEG3_11", + "CMT_TOP_SE4BEG3_8" + ], + [ + "CMT_FIFO_EE4BEG3_9", + "CMT_TOP_EE4BEG3_6" + ], + [ + "CMT_FIFO_SW2A1_8", + "CMT_TOP_SW2A1_5" + ], + [ + "CMT_FIFO_NW4END2_3", + "CMT_TOP_NW4END2_0" + ], + [ + "CMT_FIFO_SW4A2_7", + "CMT_TOP_SW4A2_4" + ], + [ + "CMT_FIFO_L_FAN2_9", + "CMT_TOP_FAN2_6" + ], + [ + "CMT_FIFO_L_IMUX45_8", + "CMT_TOP_IMUX45_5" + ], + [ + "CMT_FIFO_L_IMUX23_6", + "CMT_TOP_IMUX23_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_4", + "CMT_TOP_LOGIC_OUTS_L_B8_1" + ], + [ + "CMT_FIFO_EE4BEG1_4", + "CMT_TOP_EE4BEG1_1" + ], + [ + "CMT_FIFO_L_FAN3_5", + "CMT_TOP_FAN3_2" + ], + [ + "CMT_FIFO_ER1BEG1_9", + "CMT_TOP_ER1BEG1_6" + ], + [ + "CMT_FIFO_L_IMUX47_8", + "CMT_TOP_IMUX47_5" + ], + [ + "CMT_FIFO_EE4B0_3", + "CMT_TOP_EE4B0_0" + ], + [ + "CMT_FIFO_SW4A0_5", + "CMT_TOP_SW4A0_2" + ], + [ + "CMT_FIFO_LH12_6", + "CMT_TOP_LH12_3" + ], + [ + "CMT_FIFO_NW2A3_8", + "CMT_TOP_NW2A3_5" + ], + [ + "CMT_FIFO_L_IMUX30_3", + "CMT_TOP_IMUX30_0" + ], + [ + "CMT_FIFO_L_IMUX5_3", + "CMT_TOP_IMUX5_0" + ], + [ + "CMT_FIFO_WR1END0_4", + "CMT_TOP_WR1END0_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "CMT_TOP_OCLKDIV_7" + ], + [ + "CMT_FIFO_L_CTRL1_9", + "CMT_TOP_CTRL1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_5", + "CMT_TOP_LOGIC_OUTS_L_B11_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_8", + "CMT_TOP_LOGIC_OUTS_L_B14_5" + ], + [ + "CMT_FIFO_NE4C0_5", + "CMT_TOP_NE4C0_2" + ], + [ + "CMT_FIFO_L_FAN5_11", + "CMT_TOP_FAN5_8" + ], + [ + "CMT_FIFO_SW4END1_10", + "CMT_TOP_SW4END1_7" + ], + [ + "CMT_FIFO_EE4C2_11", + "CMT_TOP_EE4C2_8" + ], + [ + "CMT_FIFO_L_IMUX40_3", + "CMT_TOP_IMUX40_0" + ], + [ + "CMT_FIFO_L_IMUX26_6", + "CMT_TOP_IMUX26_3" + ], + [ + "CMT_FIFO_L_IMUX0_6", + "CMT_TOP_IMUX0_3" + ], + [ + "CMT_FIFO_L_IMUX11_3", + "CMT_TOP_IMUX11_0" + ], + [ + "CMT_FIFO_SE2A0_11", + "CMT_TOP_SE2A0_8" + ], + [ + "CMT_FIFO_L_IMUX44_7", + "CMT_TOP_IMUX44_4" + ], + [ + "CMT_FIFO_L_IMUX26_9", + "CMT_TOP_IMUX26_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_6", + "CMT_TOP_LOGIC_OUTS_L_B5_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_10", + "CMT_TOP_LOGIC_OUTS_L_B8_7" + ], + [ + "CMT_FIFO_L_BYP4_6", + "CMT_TOP_BYP4_3" + ], + [ + "CMT_FIFO_L_IMUX39_9", + "CMT_TOP_IMUX39_6" + ], + [ + "CMT_FIFO_WL1END3_8", + "CMT_TOP_WL1END3_5" + ], + [ + "CMT_FIFO_L_IMUX41_11", + "CMT_TOP_IMUX41_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_6", + "CMT_TOP_LOGIC_OUTS_L_B12_3" + ], + [ + "CMT_FIFO_WR1END1_11", + "CMT_TOP_WR1END1_8" + ], + [ + "CMT_FIFO_NW4A0_6", + "CMT_TOP_NW4A0_3" + ], + [ + "CMT_FIFO_SW2A3_8", + "CMT_TOP_SW2A3_5" + ], + [ + "CMT_FIFO_EE4C1_8", + "CMT_TOP_EE4C1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_10", + "CMT_TOP_LOGIC_OUTS_L_B20_7" + ], + [ + "CMT_FIFO_WW2A2_10", + "CMT_TOP_WW2A2_7" + ], + [ + "CMT_FIFO_WW4B1_8", + "CMT_TOP_WW4B1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_11", + "CMT_TOP_LOGIC_OUTS_L_B6_8" + ], + [ + "CMT_FIFO_NW2A1_7", + "CMT_TOP_NW2A1_4" + ], + [ + "CMT_FIFO_L_IMUX26_4", + "CMT_TOP_IMUX26_1" + ], + [ + "CMT_FIFO_L_IMUX20_4", + "CMT_TOP_IMUX20_1" + ], + [ + "CMT_FIFO_EE4A3_10", + "CMT_TOP_EE4A3_7" + ], + [ + "CMT_FIFO_NW2A2_7", + "CMT_TOP_NW2A2_4" + ], + [ + "CMT_FIFO_L_IMUX9_4", + "CMT_TOP_IMUX9_1" + ], + [ + "CMT_FIFO_L_IMUX32_11", + "CMT_TOP_IMUX32_8" + ], + [ + "CMT_FIFO_EE4B0_7", + "CMT_TOP_EE4B0_4" + ], + [ + "CMT_FIFO_SE4C2_7", + "CMT_TOP_SE4C2_4" + ], + [ + "CMT_FIFO_EE2A3_5", + "CMT_TOP_EE2A3_2" + ], + [ + "CMT_FIFO_EL1BEG2_9", + "CMT_TOP_EL1BEG2_6" + ], + [ + "CMT_FIFO_L_IMUX37_11", + "CMT_TOP_IMUX37_8" + ], + [ + "CMT_FIFO_NW2A0_6", + "CMT_TOP_NW2A0_3" + ], + [ + "CMT_FIFO_SE4C3_7", + "CMT_TOP_SE4C3_4" + ], + [ + "CMT_FIFO_EL1BEG0_8", + "CMT_TOP_EL1BEG0_5" + ], + [ + "CMT_FIFO_SW2A2_4", + "CMT_TOP_SW2A2_1" + ], + [ + "CMT_FIFO_WW4A0_9", + "CMT_TOP_WW4A0_6" + ], + [ + "CMT_FIFO_NW4A2_11", + "CMT_TOP_NW4A2_8" + ], + [ + "CMT_FIFO_WW2END3_11", + "CMT_TOP_WW2END3_8" + ], + [ + "CMT_FIFO_WL1END3_9", + "CMT_TOP_WL1END3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_5", + "CMT_TOP_LOGIC_OUTS_L_B22_2" + ], + [ + "CMT_FIFO_L_BYP3_6", + "CMT_TOP_BYP3_3" + ], + [ + "CMT_FIFO_NW4END1_10", + "CMT_TOP_NW4END1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_5", + "CMT_TOP_LOGIC_OUTS_L_B19_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_10", + "CMT_TOP_LOGIC_OUTS_L_B21_7" + ], + [ + "CMT_FIFO_L_IMUX31_11", + "CMT_TOP_IMUX31_8" + ], + [ + "CMT_FIFO_EL1BEG3_9", + "CMT_TOP_EL1BEG3_6" + ], + [ + "CMT_FIFO_L_IMUX15_7", + "CMT_TOP_IMUX15_4" + ], + [ + "CMT_FIFO_NE2A1_7", + "CMT_TOP_NE2A1_4" + ], + [ + "CMT_FIFO_NE2A3_6", + "CMT_TOP_NE2A3_3" + ], + [ + "CMT_FIFO_EE4C3_11", + "CMT_TOP_EE4C3_8" + ], + [ + "CMT_FIFO_SW4A2_8", + "CMT_TOP_SW4A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_6", + "CMT_TOP_LOGIC_OUTS_L_B13_3" + ], + [ + "CMT_FIFO_WW2A2_6", + "CMT_TOP_WW2A2_3" + ], + [ + "CMT_FIFO_L_IMUX28_4", + "CMT_TOP_IMUX28_1" + ], + [ + "CMT_FIFO_LH10_3", + "CMT_TOP_LH10_0" + ], + [ + "CMT_FIFO_L_FAN7_6", + "CMT_TOP_FAN7_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_11", + "CMT_TOP_LOGIC_OUTS_L_B19_8" + ], + [ + "CMT_FIFO_LH9_5", + "CMT_TOP_LH9_2" + ], + [ + "CMT_FIFO_L_IMUX16_9", + "CMT_TOP_IMUX16_6" + ], + [ + "CMT_FIFO_WW2END0_4", + "CMT_TOP_WW2END0_1" + ], + [ + "CMT_FIFO_LH11_11", + "CMT_TOP_LH11_8" + ], + [ + "CMT_FIFO_L_IMUX22_9", + "CMT_TOP_IMUX22_6" + ], + [ + "CMT_FIFO_NE4C3_5", + "CMT_TOP_NE4C3_2" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "CMT_TOP_R_LOWER_T" + ] + }, + { + "grid_deltas": [ + -1, + 7 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW4A2_4", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_LH8_4", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_NW2A2_4", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_NE2A3_4", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_ER1BEG0_4", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_SE4BEG1_4", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_EL1BEG1_4", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NE4BEG3_4", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW4A1_4", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EL1BEG0_4", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE2BEG0_4", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW2A3_4", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WW4C1_4", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_EE4B3_4", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_EE2BEG1_4", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NE4BEG0_4", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_WW4A3_4", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NE4BEG1_4", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG0_4", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_LH10_4", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_NW4A0_4", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SW2A2_4", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_LH5_4", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_NW4END2_4", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4B3_4", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_EE2A3_4", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW4C3_4", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4END1_4", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_SW4A2_4", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_EE4A1_4", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NW4A3_4", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_NW4END3_4", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_NW4END1_4", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_LH7_4", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4A0_4", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE4C0_4", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WL1END1_4", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_NW2A3_4", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NW2A0_4", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WW2END3_4", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_LH3_4", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_WW4END0_4", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EL1BEG2_4", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_EE4B1_4", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_SE4C1_4", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_SW4A1_4", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NW4A2_4", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_EE4A3_4", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE4BEG2_4", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_NE4C0_4", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_WW4END2_4", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_EE4C1_4", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE2BEG2_4", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_EE4BEG1_4", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG3_4", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EE2A0_4", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_SE4BEG2_4", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WR1END0_4", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_WW2END1_4", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_WW4END3_4", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4C2_4", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_LH6_4", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_EE4BEG0_4", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NE4C1_4", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NW4END0_4", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SE2A1_4", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_EE4B2_4", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE4BEG3_4", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_SW2A0_4", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WW4B2_4", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_WW4B0_4", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_SW4END3_4", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_EE2A1_4", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_LH12_4", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_SW4END0_4", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WR1END2_4", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_NE2A1_4", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_EE4A2_4", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_NE4BEG2_4", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EE4A0_4", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_ER1BEG2_4", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_WW2END0_4", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NE2A2_4", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_ER1BEG1_4", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SE2A0_4", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SW2A1_4", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_WL1END2_4", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_EE2A2_4", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WL1END3_4", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE2BEG3_4", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_LH4_4", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SE2A3_4", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_WW4B1_4", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_EL1BEG3_4", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WL1END0_4", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_WW2A2_4", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4C3_4", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WR1END1_4", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SW4END2_4", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WW2END2_4", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SE4C2_4", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_WW2A0_4", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WW4C0_4", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_SW2A3_4", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_LH9_4", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_ER1BEG3_4", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_EE4C2_4", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW4A1_4", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SE4C0_4", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_LH1_4", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_SW4END1_4", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_SW4A3_4", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_WR1END3_4", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_NW2A1_4", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C3_4", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_NE2A0_4", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_SW4A0_4", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE4B0_4", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_SE2A2_4", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_LH11_4", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_SE4C3_4", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_LH2_4", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NE4C2_4", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW2A1_4", + "INT_FEEDTHRU_2_WW2A1" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "CLK_HROW_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_LH10_3", + "VBRK_LH10" + ], + [ + "CLK_HROW_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_LH7_3", + "VBRK_LH7" + ], + [ + "CLK_HROW_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_LH1_3", + "VBRK_LH1" + ], + [ + "CLK_HROW_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_LH4_3", + "VBRK_LH4" + ], + [ + "CLK_HROW_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_LH8_3", + "VBRK_LH8" + ], + [ + "CLK_HROW_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_LH6_3", + "VBRK_LH6" + ], + [ + "CLK_HROW_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_LH9_3", + "VBRK_LH9" + ], + [ + "CLK_HROW_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_LH3_3", + "VBRK_LH3" + ], + [ + "CLK_HROW_LH11_3", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH12_3", + "VBRK_LH12" + ], + [ + "CLK_HROW_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_EL1BEG1_3", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_LH2_3", + "VBRK_LH2" + ], + [ + "CLK_HROW_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_LH5_3", + "VBRK_LH5" + ] + ], + "tile_types": [ + "CLK_BUFG_BOT_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "DSP_LOGIC_OUTS_B2_4", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "DSP_LOGIC_OUTS_B17_4", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "DSP_EE2BEG0_4", + "INT_INTERFACE_EE2BEG0" + ], + [ + "DSP_BYP0_4", + "INT_INTERFACE_BYP0" + ], + [ + "DSP_FAN2_4", + "INT_INTERFACE_FAN2" + ], + [ + "DSP_LOGIC_OUTS_B4_4", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "DSP_NW4END2_4", + "INT_INTERFACE_NW4END2" + ], + [ + "DSP_ER1BEG3_4", + "INT_INTERFACE_ER1BEG3" + ], + [ + "DSP_LOGIC_OUTS_B8_4", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "DSP_WW4B3_4", + "INT_INTERFACE_WW4B3" + ], + [ + "DSP_SE4C3_4", + "INT_INTERFACE_SE4C3" + ], + [ + "DSP_IMUX23_4", + "INT_INTERFACE_IMUX23" + ], + [ + "DSP_EL1BEG2_4", + "INT_INTERFACE_EL1BEG2" + ], + [ + "DSP_IMUX41_4", + "INT_INTERFACE_IMUX41" + ], + [ + "DSP_BYP3_4", + "INT_INTERFACE_BYP3" + ], + [ + "DSP_NE2A3_4", + "INT_INTERFACE_NE2A3" + ], + [ + "DSP_IMUX31_4", + "INT_INTERFACE_IMUX31" + ], + [ + "DSP_EE4C3_4", + "INT_INTERFACE_EE4C3" + ], + [ + "DSP_IMUX7_4", + "INT_INTERFACE_IMUX7" + ], + [ + "DSP_WW2END3_4", + "INT_INTERFACE_WW2END3" + ], + [ + "DSP_IMUX4_4", + "INT_INTERFACE_IMUX4" + ], + [ + "DSP_SE2A1_4", + "INT_INTERFACE_SE2A1" + ], + [ + "DSP_LOGIC_OUTS_B13_4", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "DSP_WW4B0_4", + "INT_INTERFACE_WW4B0" + ], + [ + "DSP_WL1END1_4", + "INT_INTERFACE_WL1END1" + ], + [ + "DSP_LOGIC_OUTS_B10_4", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "DSP_NW4A1_4", + "INT_INTERFACE_NW4A1" + ], + [ + "DSP_LH9_4", + "INT_INTERFACE_LH9" + ], + [ + "DSP_IMUX42_4", + "INT_INTERFACE_IMUX42" + ], + [ + "DSP_LH2_4", + "INT_INTERFACE_LH2" + ], + [ + "DSP_EE4B1_4", + "INT_INTERFACE_EE4B1" + ], + [ + "DSP_EE4BEG3_4", + "INT_INTERFACE_EE4BEG3" + ], + [ + "DSP_LH8_4", + "INT_INTERFACE_LH8" + ], + [ + "DSP_EE4C1_4", + "INT_INTERFACE_EE4C1" + ], + [ + "DSP_WW4A3_4", + "INT_INTERFACE_WW4A3" + ], + [ + "DSP_WL1END3_4", + "INT_INTERFACE_WL1END3" + ], + [ + "DSP_FAN5_4", + "INT_INTERFACE_FAN5" + ], + [ + "DSP_IMUX5_4", + "INT_INTERFACE_IMUX5" + ], + [ + "DSP_FAN3_4", + "INT_INTERFACE_FAN3" + ], + [ + "DSP_IMUX35_4", + "INT_INTERFACE_IMUX35" + ], + [ + "DSP_SW4END2_4", + "INT_INTERFACE_SW4END2" + ], + [ + "DSP_IMUX44_4", + "INT_INTERFACE_IMUX44" + ], + [ + "DSP_SW2A2_4", + "INT_INTERFACE_SW2A2" + ], + [ + "DSP_EE2A2_4", + "INT_INTERFACE_EE2A2" + ], + [ + "DSP_SW4A3_4", + "INT_INTERFACE_SW4A3" + ], + [ + "DSP_WW4A0_4", + "INT_INTERFACE_WW4A0" + ], + [ + "DSP_IMUX6_4", + "INT_INTERFACE_IMUX6" + ], + [ + "DSP_IMUX22_4", + "INT_INTERFACE_IMUX22" + ], + [ + "DSP_IMUX33_4", + "INT_INTERFACE_IMUX33" + ], + [ + "DSP_ER1BEG2_4", + "INT_INTERFACE_ER1BEG2" + ], + [ + "DSP_LOGIC_OUTS_B0_4", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "DSP_IMUX36_4", + "INT_INTERFACE_IMUX36" + ], + [ + "DSP_LOGIC_OUTS_B22_4", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "DSP_EE2A0_4", + "INT_INTERFACE_EE2A0" + ], + [ + "DSP_SW4A2_4", + "INT_INTERFACE_SW4A2" + ], + [ + "DSP_EE4BEG2_4", + "INT_INTERFACE_EE4BEG2" + ], + [ + "DSP_FAN7_4", + "INT_INTERFACE_FAN7" + ], + [ + "DSP_NW4A2_4", + "INT_INTERFACE_NW4A2" + ], + [ + "DSP_LH7_4", + "INT_INTERFACE_LH7" + ], + [ + "DSP_LOGIC_OUTS_B19_4", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "DSP_IMUX29_4", + "INT_INTERFACE_IMUX29" + ], + [ + "DSP_WW2A3_4", + "INT_INTERFACE_WW2A3" + ], + [ + "DSP_EE4B0_4", + "INT_INTERFACE_EE4B0" + ], + [ + "DSP_NE4BEG2_4", + "INT_INTERFACE_NE4BEG2" + ], + [ + "DSP_EE4A0_4", + "INT_INTERFACE_EE4A0" + ], + [ + "DSP_IMUX12_4", + "INT_INTERFACE_IMUX12" + ], + [ + "DSP_EE4A3_4", + "INT_INTERFACE_EE4A3" + ], + [ + "DSP_EE2BEG1_4", + "INT_INTERFACE_EE2BEG1" + ], + [ + "DSP_MONITOR_N_4", + "INT_INTERFACE_MONITOR_N" + ], + [ + "DSP_CLK1_4", + "INT_INTERFACE_CLK1" + ], + [ + "DSP_LOGIC_OUTS_B23_4", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "DSP_IMUX40_4", + "INT_INTERFACE_IMUX40" + ], + [ + "DSP_NW2A2_4", + "INT_INTERFACE_NW2A2" + ], + [ + "DSP_LOGIC_OUTS_B15_4", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "DSP_NE4C1_4", + "INT_INTERFACE_NE4C1" + ], + [ + "DSP_IMUX2_4", + "INT_INTERFACE_IMUX2" + ], + [ + "DSP_IMUX43_4", + "INT_INTERFACE_IMUX43" + ], + [ + "DSP_IMUX9_4", + "INT_INTERFACE_IMUX9" + ], + [ + "DSP_IMUX21_4", + "INT_INTERFACE_IMUX21" + ], + [ + "DSP_NE4BEG1_4", + "INT_INTERFACE_NE4BEG1" + ], + [ + "DSP_SE2A3_4", + "INT_INTERFACE_SE2A3" + ], + [ + "DSP_LH4_4", + "INT_INTERFACE_LH4" + ], + [ + "DSP_CTRL0_4", + "INT_INTERFACE_CTRL0" + ], + [ + "DSP_LOGIC_OUTS_B1_4", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "DSP_WW4C2_4", + "INT_INTERFACE_WW4C2" + ], + [ + "DSP_WW4END3_4", + "INT_INTERFACE_WW4END3" + ], + [ + "DSP_SE4BEG2_4", + "INT_INTERFACE_SE4BEG2" + ], + [ + "DSP_IMUX25_4", + "INT_INTERFACE_IMUX25" + ], + [ + "DSP_IMUX11_4", + "INT_INTERFACE_IMUX11" + ], + [ + "DSP_EE2BEG2_4", + "INT_INTERFACE_EE2BEG2" + ], + [ + "DSP_WW2END1_4", + "INT_INTERFACE_WW2END1" + ], + [ + "DSP_WW4END2_4", + "INT_INTERFACE_WW4END2" + ], + [ + "DSP_LOGIC_OUTS_B18_4", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "DSP_EE4BEG1_4", + "INT_INTERFACE_EE4BEG1" + ], + [ + "DSP_FAN6_4", + "INT_INTERFACE_FAN6" + ], + [ + "DSP_NE2A2_4", + "INT_INTERFACE_NE2A2" + ], + [ + "DSP_IMUX34_4", + "INT_INTERFACE_IMUX34" + ], + [ + "DSP_LH1_4", + "INT_INTERFACE_LH1" + ], + [ + "DSP_WL1END0_4", + "INT_INTERFACE_WL1END0" + ], + [ + "DSP_SE4C1_4", + "INT_INTERFACE_SE4C1" + ], + [ + "DSP_IMUX19_4", + "INT_INTERFACE_IMUX19" + ], + [ + "DSP_NE2A0_4", + "INT_INTERFACE_NE2A0" + ], + [ + "DSP_BYP2_4", + "INT_INTERFACE_BYP2" + ], + [ + "DSP_SW4END0_4", + "INT_INTERFACE_SW4END0" + ], + [ + "DSP_SW4END1_4", + "INT_INTERFACE_SW4END1" + ], + [ + "DSP_NE4C3_4", + "INT_INTERFACE_NE4C3" + ], + [ + "DSP_IMUX37_4", + "INT_INTERFACE_IMUX37" + ], + [ + "DSP_WW2END0_4", + "INT_INTERFACE_WW2END0" + ], + [ + "DSP_WW2A0_4", + "INT_INTERFACE_WW2A0" + ], + [ + "DSP_SW4A0_4", + "INT_INTERFACE_SW4A0" + ], + [ + "DSP_IMUX3_4", + "INT_INTERFACE_IMUX3" + ], + [ + "DSP_IMUX39_4", + "INT_INTERFACE_IMUX39" + ], + [ + "DSP_CTRL1_4", + "INT_INTERFACE_CTRL1" + ], + [ + "DSP_NW2A1_4", + "INT_INTERFACE_NW2A1" + ], + [ + "DSP_LOGIC_OUTS_B5_4", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "DSP_IMUX24_4", + "INT_INTERFACE_IMUX24" + ], + [ + "DSP_BYP5_4", + "INT_INTERFACE_BYP5" + ], + [ + "DSP_EL1BEG3_4", + "INT_INTERFACE_EL1BEG3" + ], + [ + "DSP_WW4C0_4", + "INT_INTERFACE_WW4C0" + ], + [ + "DSP_IMUX14_4", + "INT_INTERFACE_IMUX14" + ], + [ + "DSP_WW2END2_4", + "INT_INTERFACE_WW2END2" + ], + [ + "DSP_LOGIC_OUTS_B12_4", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "DSP_LOGIC_OUTS_B3_4", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "DSP_IMUX18_4", + "INT_INTERFACE_IMUX18" + ], + [ + "DSP_NE2A1_4", + "INT_INTERFACE_NE2A1" + ], + [ + "DSP_WW4A1_4", + "INT_INTERFACE_WW4A1" + ], + [ + "DSP_FAN4_4", + "INT_INTERFACE_FAN4" + ], + [ + "DSP_IMUX32_4", + "INT_INTERFACE_IMUX32" + ], + [ + "DSP_NW4A0_4", + "INT_INTERFACE_NW4A0" + ], + [ + "DSP_LOGIC_OUTS_B21_4", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "DSP_FAN1_4", + "INT_INTERFACE_FAN1" + ], + [ + "DSP_NW4END1_4", + "INT_INTERFACE_NW4END1" + ], + [ + "DSP_IMUX28_4", + "INT_INTERFACE_IMUX28" + ], + [ + "DSP_SE4C2_4", + "INT_INTERFACE_SE4C2" + ], + [ + "DSP_WR1END3_4", + "INT_INTERFACE_WR1END3" + ], + [ + "DSP_LH12_4", + "INT_INTERFACE_LH12" + ], + [ + "DSP_SE2A2_4", + "INT_INTERFACE_SE2A2" + ], + [ + "DSP_EE2A1_4", + "INT_INTERFACE_EE2A1" + ], + [ + "DSP_WR1END2_4", + "INT_INTERFACE_WR1END2" + ], + [ + "DSP_MONITOR_P_4", + "INT_INTERFACE_MONITOR_P" + ], + [ + "DSP_IMUX13_4", + "INT_INTERFACE_IMUX13" + ], + [ + "DSP_LOGIC_OUTS_B14_4", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "DSP_LH5_4", + "INT_INTERFACE_LH5" + ], + [ + "DSP_LH3_4", + "INT_INTERFACE_LH3" + ], + [ + "DSP_IMUX30_4", + "INT_INTERFACE_IMUX30" + ], + [ + "DSP_EE4C2_4", + "INT_INTERFACE_EE4C2" + ], + [ + "DSP_WW4C1_4", + "INT_INTERFACE_WW4C1" + ], + [ + "DSP_LH11_4", + "INT_INTERFACE_LH11" + ], + [ + "DSP_LOGIC_OUTS_B7_4", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "DSP_LH10_4", + "INT_INTERFACE_LH10" + ], + [ + "DSP_ER1BEG1_4", + "INT_INTERFACE_ER1BEG1" + ], + [ + "DSP_BYP4_4", + "INT_INTERFACE_BYP4" + ], + [ + "DSP_LOGIC_OUTS_B16_4", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "DSP_SE4BEG3_4", + "INT_INTERFACE_SE4BEG3" + ], + [ + "DSP_EL1BEG1_4", + "INT_INTERFACE_EL1BEG1" + ], + [ + "DSP_SW2A0_4", + "INT_INTERFACE_SW2A0" + ], + [ + "DSP_IMUX8_4", + "INT_INTERFACE_IMUX8" + ], + [ + "DSP_SE4C0_4", + "INT_INTERFACE_SE4C0" + ], + [ + "DSP_IMUX20_4", + "INT_INTERFACE_IMUX20" + ], + [ + "DSP_NW4END3_4", + "INT_INTERFACE_NW4END3" + ], + [ + "DSP_EE4A1_4", + "INT_INTERFACE_EE4A1" + ], + [ + "DSP_IMUX15_4", + "INT_INTERFACE_IMUX15" + ], + [ + "DSP_WW2A2_4", + "INT_INTERFACE_WW2A2" + ], + [ + "DSP_CLK0_4", + "INT_INTERFACE_CLK0" + ], + [ + "DSP_SW2A1_4", + "INT_INTERFACE_SW2A1" + ], + [ + "DSP_ER1BEG0_4", + "INT_INTERFACE_ER1BEG0" + ], + [ + "DSP_LOGIC_OUTS_B6_4", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "DSP_EE4B3_4", + "INT_INTERFACE_EE4B3" + ], + [ + "DSP_WW4C3_4", + "INT_INTERFACE_WW4C3" + ], + [ + "DSP_LOGIC_OUTS_B11_4", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "DSP_FAN0_4", + "INT_INTERFACE_FAN0" + ], + [ + "DSP_IMUX26_4", + "INT_INTERFACE_IMUX26" + ], + [ + "DSP_SE2A0_4", + "INT_INTERFACE_SE2A0" + ], + [ + "DSP_IMUX0_4", + "INT_INTERFACE_IMUX0" + ], + [ + "DSP_NE4C2_4", + "INT_INTERFACE_NE4C2" + ], + [ + "DSP_NE4C0_4", + "INT_INTERFACE_NE4C0" + ], + [ + "DSP_NE4BEG3_4", + "INT_INTERFACE_NE4BEG3" + ], + [ + "DSP_EE4A2_4", + "INT_INTERFACE_EE4A2" + ], + [ + "DSP_NW2A0_4", + "INT_INTERFACE_NW2A0" + ], + [ + "DSP_IMUX17_4", + "INT_INTERFACE_IMUX17" + ], + [ + "DSP_NW2A3_4", + "INT_INTERFACE_NW2A3" + ], + [ + "DSP_EE4C0_4", + "INT_INTERFACE_EE4C0" + ], + [ + "DSP_BYP6_4", + "INT_INTERFACE_BYP6" + ], + [ + "DSP_BYP7_4", + "INT_INTERFACE_BYP7" + ], + [ + "DSP_SE4BEG1_4", + "INT_INTERFACE_SE4BEG1" + ], + [ + "DSP_EE2BEG3_4", + "INT_INTERFACE_EE2BEG3" + ], + [ + "DSP_SE4BEG0_4", + "INT_INTERFACE_SE4BEG0" + ], + [ + "DSP_WR1END0_4", + "INT_INTERFACE_WR1END0" + ], + [ + "DSP_IMUX46_4", + "INT_INTERFACE_IMUX46" + ], + [ + "DSP_EL1BEG0_4", + "INT_INTERFACE_EL1BEG0" + ], + [ + "DSP_NW4END0_4", + "INT_INTERFACE_NW4END0" + ], + [ + "DSP_IMUX1_4", + "INT_INTERFACE_IMUX1" + ], + [ + "DSP_SW4END3_4", + "INT_INTERFACE_SW4END3" + ], + [ + "DSP_BYP1_4", + "INT_INTERFACE_BYP1" + ], + [ + "DSP_IMUX38_4", + "INT_INTERFACE_IMUX38" + ], + [ + "DSP_EE4BEG0_4", + "INT_INTERFACE_EE4BEG0" + ], + [ + "DSP_IMUX10_4", + "INT_INTERFACE_IMUX10" + ], + [ + "DSP_SW4A1_4", + "INT_INTERFACE_SW4A1" + ], + [ + "DSP_WW4B2_4", + "INT_INTERFACE_WW4B2" + ], + [ + "DSP_IMUX45_4", + "INT_INTERFACE_IMUX45" + ], + [ + "DSP_WW2A1_4", + "INT_INTERFACE_WW2A1" + ], + [ + "DSP_WW4END1_4", + "INT_INTERFACE_WW4END1" + ], + [ + "DSP_EE4B2_4", + "INT_INTERFACE_EE4B2" + ], + [ + "DSP_WL1END2_4", + "INT_INTERFACE_WL1END2" + ], + [ + "DSP_LOGIC_OUTS_B9_4", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "DSP_LH6_4", + "INT_INTERFACE_LH6" + ], + [ + "DSP_WW4B1_4", + "INT_INTERFACE_WW4B1" + ], + [ + "DSP_NW4A3_4", + "INT_INTERFACE_NW4A3" + ], + [ + "DSP_EE2A3_4", + "INT_INTERFACE_EE2A3" + ], + [ + "DSP_WW4A2_4", + "INT_INTERFACE_WW4A2" + ], + [ + "DSP_WR1END1_4", + "INT_INTERFACE_WR1END1" + ], + [ + "DSP_WW4END0_4", + "INT_INTERFACE_WW4END0" + ], + [ + "DSP_NE4BEG0_4", + "INT_INTERFACE_NE4BEG0" + ], + [ + "DSP_SW2A3_4", + "INT_INTERFACE_SW2A3" + ], + [ + "DSP_IMUX47_4", + "INT_INTERFACE_IMUX47" + ], + [ + "DSP_IMUX27_4", + "INT_INTERFACE_IMUX27" + ], + [ + "DSP_LOGIC_OUTS_B20_4", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "DSP_IMUX16_4", + "INT_INTERFACE_IMUX16" + ] + ], + "tile_types": [ + "DSP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "MONITOR_WW4A2_4", + "VFRAME_WW4A2" + ], + [ + "MONITOR_NW4A0_4", + "VFRAME_NW4A0" + ], + [ + "MONITOR_LH11_4", + "VFRAME_LH11" + ], + [ + "MONITOR_FAN0_4", + "VFRAME_FAN0" + ], + [ + "MONITOR_NW4END0_4", + "VFRAME_NW4END0" + ], + [ + "MONITOR_NW4END3_4", + "VFRAME_NW4END3" + ], + [ + "MONITOR_BYP7_4", + "VFRAME_BYP7" + ], + [ + "MONITOR_EE4A2_4", + "VFRAME_EE4A2" + ], + [ + "MONITOR_ER1BEG2_4", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_CLK1_4", + "VFRAME_CLK1" + ], + [ + "MONITOR_EE2BEG0_4", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_EE2BEG2_4", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_IMUX11_4", + "VFRAME_IMUX11" + ], + [ + "MONITOR_IMUX40_4", + "VFRAME_IMUX40" + ], + [ + "MONITOR_IMUX16_4", + "VFRAME_IMUX16" + ], + [ + "MONITOR_FAN4_4", + "VFRAME_FAN4" + ], + [ + "MONITOR_BYP4_4", + "VFRAME_BYP4" + ], + [ + "MONITOR_IMUX8_4", + "VFRAME_IMUX8" + ], + [ + "MONITOR_SW4END0_4", + "VFRAME_SW4END0" + ], + [ + "MONITOR_SW4A3_4", + "VFRAME_SW4A3" + ], + [ + "MONITOR_IMUX36_4", + "VFRAME_IMUX36" + ], + [ + "MONITOR_BYP6_4", + "VFRAME_BYP6" + ], + [ + "MONITOR_IMUX4_4", + "VFRAME_IMUX4" + ], + [ + "MONITOR_NW4A3_4", + "VFRAME_NW4A3" + ], + [ + "MONITOR_NE4BEG3_4", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_IMUX27_4", + "VFRAME_IMUX27" + ], + [ + "MONITOR_NE4C3_4", + "VFRAME_NE4C3" + ], + [ + "MONITOR_LH9_4", + "VFRAME_LH9" + ], + [ + "MONITOR_IMUX2_4", + "VFRAME_IMUX2" + ], + [ + "MONITOR_SE4BEG1_4", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_LH3_4", + "VFRAME_LH3" + ], + [ + "MONITOR_EE2A0_4", + "VFRAME_EE2A0" + ], + [ + "MONITOR_EE4C1_4", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX7_4", + "VFRAME_IMUX7" + ], + [ + "MONITOR_LH10_4", + "VFRAME_LH10" + ], + [ + "MONITOR_IMUX28_4", + "VFRAME_IMUX28" + ], + [ + "MONITOR_IMUX24_4", + "VFRAME_IMUX24" + ], + [ + "MONITOR_IMUX33_4", + "VFRAME_IMUX33" + ], + [ + "MONITOR_IMUX30_4", + "VFRAME_IMUX30" + ], + [ + "MONITOR_SW2A3_4", + "VFRAME_SW2A3" + ], + [ + "MONITOR_WR1END3_4", + "VFRAME_WR1END3" + ], + [ + "MONITOR_IMUX31_4", + "VFRAME_IMUX31" + ], + [ + "MONITOR_WW4A3_4", + "VFRAME_WW4A3" + ], + [ + "MONITOR_IMUX22_4", + "VFRAME_IMUX22" + ], + [ + "MONITOR_SW4END2_4", + "VFRAME_SW4END2" + ], + [ + "MONITOR_IMUX10_4", + "VFRAME_IMUX10" + ], + [ + "MONITOR_IMUX25_4", + "VFRAME_IMUX25" + ], + [ + "MONITOR_IMUX45_4", + "VFRAME_IMUX45" + ], + [ + "MONITOR_NW4END1_4", + "VFRAME_NW4END1" + ], + [ + "MONITOR_EE4BEG0_4", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_FAN3_4", + "VFRAME_FAN3" + ], + [ + "MONITOR_BYP5_4", + "VFRAME_BYP5" + ], + [ + "MONITOR_WW4C2_4", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE4B3_4", + "VFRAME_EE4B3" + ], + [ + "MONITOR_EE4C3_4", + "VFRAME_EE4C3" + ], + [ + "MONITOR_EE4A0_4", + "VFRAME_EE4A0" + ], + [ + "MONITOR_WW4A1_4", + "VFRAME_WW4A1" + ], + [ + "MONITOR_IMUX14_4", + "VFRAME_IMUX14" + ], + [ + "MONITOR_WW4B2_4", + "VFRAME_WW4B2" + ], + [ + "MONITOR_IMUX17_4", + "VFRAME_IMUX17" + ], + [ + "MONITOR_IMUX19_4", + "VFRAME_IMUX19" + ], + [ + "MONITOR_SE2A2_4", + "VFRAME_SE2A2" + ], + [ + "MONITOR_EE4C2_4", + "VFRAME_EE4C2" + ], + [ + "MONITOR_EE4BEG3_4", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_SE4BEG2_4", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_LH7_4", + "VFRAME_LH7" + ], + [ + "MONITOR_IMUX21_4", + "VFRAME_IMUX21" + ], + [ + "MONITOR_WW4B0_4", + "VFRAME_WW4B0" + ], + [ + "MONITOR_SW4END1_4", + "VFRAME_SW4END1" + ], + [ + "MONITOR_EE4B1_4", + "VFRAME_EE4B1" + ], + [ + "MONITOR_NE2A1_4", + "VFRAME_NE2A1" + ], + [ + "MONITOR_WW2A0_4", + "VFRAME_WW2A0" + ], + [ + "MONITOR_EE4A3_4", + "VFRAME_EE4A3" + ], + [ + "MONITOR_NE4BEG0_4", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_WW4B3_4", + "VFRAME_WW4B3" + ], + [ + "MONITOR_IMUX42_4", + "VFRAME_IMUX42" + ], + [ + "MONITOR_CLK0_4", + "VFRAME_CLK0" + ], + [ + "MONITOR_IMUX26_4", + "VFRAME_IMUX26" + ], + [ + "MONITOR_SE4C1_4", + "VFRAME_SE4C1" + ], + [ + "MONITOR_WW2A3_4", + "VFRAME_WW2A3" + ], + [ + "MONITOR_LH5_4", + "VFRAME_LH5" + ], + [ + "MONITOR_SW4A1_4", + "VFRAME_SW4A1" + ], + [ + "MONITOR_FAN2_4", + "VFRAME_FAN2" + ], + [ + "MONITOR_WL1END3_4", + "VFRAME_WL1END3" + ], + [ + "MONITOR_CTRL1_4", + "VFRAME_CTRL1" + ], + [ + "MONITOR_WW4C1_4", + "VFRAME_WW4C1" + ], + [ + "MONITOR_WW4END0_4", + "VFRAME_WW4END0" + ], + [ + "MONITOR_WW4C3_4", + "VFRAME_WW4C3" + ], + [ + "MONITOR_WR1END0_4", + "VFRAME_WR1END0" + ], + [ + "MONITOR_EE4B0_4", + "VFRAME_EE4B0" + ], + [ + "MONITOR_EL1BEG0_4", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_SE4BEG3_4", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_SW2A0_4", + "VFRAME_SW2A0" + ], + [ + "MONITOR_FAN1_4", + "VFRAME_FAN1" + ], + [ + "MONITOR_EE2BEG3_4", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_WW4END2_4", + "VFRAME_WW4END2" + ], + [ + "MONITOR_BYP3_4", + "VFRAME_BYP3" + ], + [ + "MONITOR_EE2A2_4", + "VFRAME_EE2A2" + ], + [ + "MONITOR_WR1END1_4", + "VFRAME_WR1END1" + ], + [ + "MONITOR_NE2A2_4", + "VFRAME_NE2A2" + ], + [ + "MONITOR_SW2A1_4", + "VFRAME_SW2A1" + ], + [ + "MONITOR_IMUX44_4", + "VFRAME_IMUX44" + ], + [ + "MONITOR_SE4C0_4", + "VFRAME_SE4C0" + ], + [ + "MONITOR_EE4BEG2_4", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_SE2A3_4", + "VFRAME_SE2A3" + ], + [ + "MONITOR_IMUX39_4", + "VFRAME_IMUX39" + ], + [ + "MONITOR_NW2A2_4", + "VFRAME_NW2A2" + ], + [ + "MONITOR_IMUX35_4", + "VFRAME_IMUX35" + ], + [ + "MONITOR_EE4BEG1_4", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX6_4", + "VFRAME_IMUX6" + ], + [ + "MONITOR_BYP2_4", + "VFRAME_BYP2" + ], + [ + "MONITOR_NE4C1_4", + "VFRAME_NE4C1" + ], + [ + "MONITOR_LH12_4", + "VFRAME_LH12" + ], + [ + "MONITOR_NW4END2_4", + "VFRAME_NW4END2" + ], + [ + "MONITOR_SE4C2_4", + "VFRAME_SE4C2" + ], + [ + "MONITOR_NW2A3_4", + "VFRAME_NW2A3" + ], + [ + "MONITOR_IMUX34_4", + "VFRAME_IMUX34" + ], + [ + "MONITOR_LH6_4", + "VFRAME_LH6" + ], + [ + "MONITOR_WW4C0_4", + "VFRAME_WW4C0" + ], + [ + "MONITOR_ER1BEG0_4", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_NW4A1_4", + "VFRAME_NW4A1" + ], + [ + "MONITOR_IMUX47_4", + "VFRAME_IMUX47" + ], + [ + "MONITOR_LH4_4", + "VFRAME_LH4" + ], + [ + "MONITOR_WW4END1_4", + "VFRAME_WW4END1" + ], + [ + "MONITOR_ER1BEG1_4", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_IMUX32_4", + "VFRAME_IMUX32" + ], + [ + "MONITOR_FAN5_4", + "VFRAME_FAN5" + ], + [ + "MONITOR_EE4A1_4", + "VFRAME_EE4A1" + ], + [ + "MONITOR_IMUX3_4", + "VFRAME_IMUX3" + ], + [ + "MONITOR_BYP0_4", + "VFRAME_BYP0" + ], + [ + "MONITOR_WW4B1_4", + "VFRAME_WW4B1" + ], + [ + "MONITOR_IMUX43_4", + "VFRAME_IMUX43" + ], + [ + "MONITOR_WW2END3_4", + "VFRAME_WW2END3" + ], + [ + "MONITOR_WL1END2_4", + "VFRAME_WL1END2" + ], + [ + "MONITOR_SW4END3_4", + "VFRAME_SW4END3" + ], + [ + "MONITOR_FAN7_4", + "VFRAME_FAN7" + ], + [ + "MONITOR_WW2A1_4", + "VFRAME_WW2A1" + ], + [ + "MONITOR_NW4A2_4", + "VFRAME_NW4A2" + ], + [ + "MONITOR_SW2A2_4", + "VFRAME_SW2A2" + ], + [ + "MONITOR_IMUX37_4", + "VFRAME_IMUX37" + ], + [ + "MONITOR_NE4C2_4", + "VFRAME_NE4C2" + ], + [ + "MONITOR_EL1BEG1_4", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_FAN6_4", + "VFRAME_FAN6" + ], + [ + "MONITOR_WW2END1_4", + "VFRAME_WW2END1" + ], + [ + "MONITOR_NE4C0_4", + "VFRAME_NE4C0" + ], + [ + "MONITOR_IMUX0_4", + "VFRAME_IMUX0" + ], + [ + "MONITOR_SW4A2_4", + "VFRAME_SW4A2" + ], + [ + "MONITOR_IMUX46_4", + "VFRAME_IMUX46" + ], + [ + "MONITOR_IMUX13_4", + "VFRAME_IMUX13" + ], + [ + "MONITOR_WL1END1_4", + "VFRAME_WL1END1" + ], + [ + "MONITOR_NE2A0_4", + "VFRAME_NE2A0" + ], + [ + "MONITOR_LH1_4", + "VFRAME_LH1" + ], + [ + "MONITOR_EL1BEG3_4", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_EE4C0_4", + "VFRAME_EE4C0" + ], + [ + "MONITOR_NE4BEG1_4", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_WW4A0_4", + "VFRAME_WW4A0" + ], + [ + "MONITOR_SE4BEG0_4", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_WL1END0_4", + "VFRAME_WL1END0" + ], + [ + "MONITOR_IMUX12_4", + "VFRAME_IMUX12" + ], + [ + "MONITOR_EL1BEG2_4", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_SE4C3_4", + "VFRAME_SE4C3" + ], + [ + "MONITOR_IMUX41_4", + "VFRAME_IMUX41" + ], + [ + "MONITOR_WW2A2_4", + "VFRAME_WW2A2" + ], + [ + "MONITOR_WW2END2_4", + "VFRAME_WW2END2" + ], + [ + "MONITOR_LH2_4", + "VFRAME_LH2" + ], + [ + "MONITOR_IMUX23_4", + "VFRAME_IMUX23" + ], + [ + "MONITOR_LH8_4", + "VFRAME_LH8" + ], + [ + "MONITOR_IMUX20_4", + "VFRAME_IMUX20" + ], + [ + "MONITOR_IMUX5_4", + "VFRAME_IMUX5" + ], + [ + "MONITOR_WW2END0_4", + "VFRAME_WW2END0" + ], + [ + "MONITOR_BYP1_4", + "VFRAME_BYP1" + ], + [ + "MONITOR_SE2A1_4", + "VFRAME_SE2A1" + ], + [ + "MONITOR_CTRL0_4", + "VFRAME_CTRL0" + ], + [ + "MONITOR_WW4END3_4", + "VFRAME_WW4END3" + ], + [ + "MONITOR_EE4B2_4", + "VFRAME_EE4B2" + ], + [ + "MONITOR_ER1BEG3_4", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_IMUX1_4", + "VFRAME_IMUX1" + ], + [ + "MONITOR_SE2A0_4", + "VFRAME_SE2A0" + ], + [ + "MONITOR_EE2A3_4", + "VFRAME_EE2A3" + ], + [ + "MONITOR_IMUX18_4", + "VFRAME_IMUX18" + ], + [ + "MONITOR_IMUX15_4", + "VFRAME_IMUX15" + ], + [ + "MONITOR_WR1END2_4", + "VFRAME_WR1END2" + ], + [ + "MONITOR_NW2A0_4", + "VFRAME_NW2A0" + ], + [ + "MONITOR_NW2A1_4", + "VFRAME_NW2A1" + ], + [ + "MONITOR_IMUX29_4", + "VFRAME_IMUX29" + ], + [ + "MONITOR_NE2A3_4", + "VFRAME_NE2A3" + ], + [ + "MONITOR_EE2A1_4", + "VFRAME_EE2A1" + ], + [ + "MONITOR_EE2BEG1_4", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_NE4BEG2_4", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_IMUX9_4", + "VFRAME_IMUX9" + ], + [ + "MONITOR_IMUX38_4", + "VFRAME_IMUX38" + ], + [ + "MONITOR_SW4A0_4", + "VFRAME_SW4A0" + ] + ], + "tile_types": [ + "MONITOR_MID_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + -8 + ], + "wire_pairs": [ + [ + "MMCM_CLK_FREQBB_REBUFOUT0", + "HCLK_CMT_FREQ_REF_NS0" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM9", + "HCLK_CMT_MUX_CLK_MMCM9" + ], + [ + "CMT_PHASER_BOT_OBURSTPENDING0", + "HCLK_CMT_OBURSTPENDING0" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM1", + "HCLK_CMT_MUX_CLK_MMCM1" + ], + [ + "MMCM_CLK_FREQBB_REBUFOUT3", + "HCLK_CMT_FREQ_REF_NS3" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM13", + "HCLK_CMT_MUX_CLK_MMCM13" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM3", + "HCLK_CMT_MUX_CLK_MMCM3" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM6", + "HCLK_CMT_MUX_CLK_MMCM6" + ], + [ + "CMT_LR_LOWER_T_CLK_IN3_HCLK", + "HCLK_CMT_MUX_MMCM_CLKFBIN" + ], + [ + "CMT_PHASER_BOT_SYNC_BB", + "HCLK_CMT_PHY_SYNC_BB" + ], + [ + "CMT_PHASER_BOT_IRANKB0", + "HCLK_CMT_PHY_CONTROL_IRANKB0" + ], + [ + "CMT_PHASER_BOT_REFMUX_1", + "HCLK_CMT_FREQ_PHASER_REFMUX_1" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM10", + "HCLK_CMT_MUX_CLK_MMCM10" + ], + [ + "CMT_PHASER_BOT_IBURSTPENDING1", + "HCLK_CMT_IBURSTPENDING1" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM5", + "HCLK_CMT_MUX_CLK_MMCM5" + ], + [ + "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "HCLK_CMT_PHASEREF_ABOVE1" + ], + [ + "CMT_PHASER_OUT_B_OCLK", + "HCLK_CMT_PHASEROUTB_OCLK" + ], + [ + "CMT_BOT_HCLKMUX_CLKINT_1", + "HCLK_CMT_MUX_CLKINT_1" + ], + [ + "CMT_PHASER_BOT_REFMUX_2", + "HCLK_CMT_FREQ_PHASER_REFMUX_2" + ], + [ + "CMT_PHASER_BOT_OBURSTPENDING1", + "HCLK_CMT_OBURSTPENDING1" + ], + [ + "CMT_LR_LOWER_T_CLK_PERF3", + "HCLK_CMT_MUX_MMCM_MUXED3" + ], + [ + "CMT_PHASER_OUT_B_OCLK1X_90", + "HCLK_CMT_PHASEROUTB_OCLK1X_90" + ], + [ + "CMT_PHASER_IN_A_ICLKDIV", + "HCLK_CMT_PHASERINA_ICLKDIV" + ], + [ + "CMT_PHASER_IN_B_RCLK1", + "HCLK_CMT_PHASERIN_RCLK1" + ], + [ + "CMT_PHASER_BOT_IRANKA0", + "HCLK_CMT_PHY_CONTROL_IRANKA0" + ], + [ + "CMT_PHASER_IN_A_ICLK", + "HCLK_CMT_PHASERINA_ICLK" + ], + [ + "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "HCLK_CMT_PHASEREF_ABOVE0" + ], + [ + "CMT_PHASER_OUT_A_OCLK", + "HCLK_CMT_PHASEROUTA_OCLK" + ], + [ + "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "HCLK_CMT_PHASEREF_BELOW0" + ], + [ + "CMT_PHASER_OUT_B_OCLKDIV", + "HCLK_CMT_PHASEROUTB_OCLKDIV" + ], + [ + "CMT_PHASER_BOT_REFMUX_0", + "HCLK_CMT_FREQ_PHASER_REFMUX_0" + ], + [ + "MMCM_CLK_FREQBB_REBUFOUT2", + "HCLK_CMT_FREQ_REF_NS2" + ], + [ + "CMT_LR_LOWER_T_CLK_PERF2", + "HCLK_CMT_MUX_MMCM_MUXED2" + ], + [ + "MMCM_CLK_FREQBB_REBUFOUT1", + "HCLK_CMT_FREQ_REF_NS1" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM0", + "HCLK_CMT_MUX_CLK_MMCM0" + ], + [ + "CMT_LR_LOWER_T_CLK_PERF1", + "HCLK_CMT_MUX_MMCM_MUXED1" + ], + [ + "CMT_BOT_HCLKMUX_CLKINT_0", + "HCLK_CMT_MUX_CLKINT_0" + ], + [ + "CMT_PHASER_DOWN_PHASERREF0", + "HCLK_CMT_BUFMR_PHASEREF0" + ], + [ + "CMT_PHASER_DOWN_PHASERREF1", + "HCLK_CMT_BUFMR_PHASEREF1" + ], + [ + "CMT_PHASER_IN_A_RCLK0", + "HCLK_CMT_PHASERIN_RCLK0" + ], + [ + "CMT_LR_LOWER_T_CLK_PERF0", + "HCLK_CMT_MUX_MMCM_MUXED0" + ], + [ + "CMT_PHASER_BOT_ENCALIB0", + "HCLK_CMT_ECALIB0" + ], + [ + "CMT_LR_LOWER_T_CLK_IN1_HCLK", + "HCLK_CMT_MUX_MMCM_CLKIN1" + ], + [ + "CMT_PHASER_BOT_IBURSTPENDING0", + "HCLK_CMT_IBURSTPENDING0" + ], + [ + "CMT_PHASER_BOT_IRANKB1", + "HCLK_CMT_PHY_CONTROL_IRANKB1" + ], + [ + "CMT_LR_LOWER_T_CLK_IN2_HCLK", + "HCLK_CMT_MUX_MMCM_CLKIN2" + ], + [ + "CMT_PHASER_BOT_ENCALIB1", + "HCLK_CMT_ECALIB1" + ], + [ + "CMT_PHASER_IN_B_ICLK", + "HCLK_CMT_PHASERINB_ICLK" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM12", + "HCLK_CMT_MUX_CLK_MMCM12" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM7", + "HCLK_CMT_MUX_CLK_MMCM7" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM4", + "HCLK_CMT_MUX_CLK_MMCM4" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM2", + "HCLK_CMT_MUX_CLK_MMCM2" + ], + [ + "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "HCLK_CMT_PHASEREF_BELOW1" + ], + [ + "CMT_PHASER_OUT_A_OCLKDIV", + "HCLK_CMT_PHASEROUTA_OCLKDIV" + ], + [ + "CMT_PHASER_BOT_IRANKA1", + "HCLK_CMT_PHY_CONTROL_IRANKA1" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM11", + "HCLK_CMT_MUX_CLK_MMCM11" + ], + [ + "CMT_PHASER_OUT_A_OCLK1X_90", + "HCLK_CMT_PHASEROUTA_OCLK1X_90" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM8", + "HCLK_CMT_MUX_CLK_MMCM8" + ], + [ + "CMT_PHASER_IN_B_ICLKDIV", + "HCLK_CMT_PHASERINB_ICLKDIV" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_T", + "HCLK_CMT" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_2" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_2" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_2" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_2" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_2" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_2" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_2" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_2" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_2" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_2" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_2" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_2" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_2" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_2" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_2" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_2" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_2" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_2" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_2" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_2" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_2" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_2" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_2" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_2" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_2" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_2" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_2" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_2" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_2" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_2" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_2" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_2" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_2" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_2" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_2" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_2" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_2" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_2" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_2" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_2" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_2" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_2" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_2" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_2" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_2" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_2" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_2" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_2" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_2" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_2" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_2" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_2" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_2" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_2" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_2" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_2" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_2" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_2" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_2" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_2" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_2" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_2" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_2" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_2" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_2" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_2" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_2" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_2" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_2" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_2" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_2" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_2" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_2" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_2" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_2" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_2" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_2" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_2" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_2" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_2" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_2" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_2" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_2" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_2" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_2" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_2" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_2" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_2" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_2" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_2" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_2" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_2" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_2" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_2" + ], + [ + "INT_FEEDTHRU_2_MONITOR_P", + "MONITOR_HORIZ_VAUXP12_LEFT" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_2" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_2" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_2" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_2" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_2" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_2" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_2" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_2" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_2" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_2" + ], + [ + "INT_FEEDTHRU_2_MONITOR_N", + "MONITOR_HORIZ_VAUXN12_LEFT" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_2" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_2" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_2" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_2" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_2" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_2" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_2" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_2" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_2" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_2" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_2" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_2" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_2" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_2" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_2" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_2" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_BOT_FUJI2" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "DSP_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "DSP_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "DSP_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "DSP_LH4_3", + "VBRK_LH4" + ], + [ + "DSP_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "DSP_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "DSP_LH7_3", + "VBRK_LH7" + ], + [ + "DSP_LH5_3", + "VBRK_LH5" + ], + [ + "DSP_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "DSP_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "DSP_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "DSP_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "DSP_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "DSP_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "DSP_LH3_3", + "VBRK_LH3" + ], + [ + "DSP_LH1_3", + "VBRK_LH1" + ], + [ + "DSP_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "DSP_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "DSP_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "DSP_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "DSP_EL1BEG1_3", + "VBRK_EL1BEG1" + ], + [ + "DSP_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "DSP_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "DSP_LH12_3", + "VBRK_LH12" + ], + [ + "DSP_LH2_3", + "VBRK_LH2" + ], + [ + "DSP_LH9_3", + "VBRK_LH9" + ], + [ + "DSP_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "DSP_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "DSP_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "DSP_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "DSP_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "DSP_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "DSP_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "DSP_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "DSP_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "DSP_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "DSP_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "DSP_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "DSP_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "DSP_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "DSP_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "DSP_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "DSP_LH8_3", + "VBRK_LH8" + ], + [ + "DSP_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "DSP_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "DSP_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "DSP_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "DSP_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "DSP_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "DSP_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "DSP_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "DSP_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "DSP_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "DSP_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "DSP_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "DSP_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "DSP_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "DSP_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "DSP_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "DSP_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "DSP_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "DSP_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "DSP_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "DSP_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "DSP_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "DSP_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "DSP_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "DSP_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "DSP_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "DSP_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "DSP_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "DSP_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "DSP_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "DSP_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "DSP_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "DSP_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "DSP_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "DSP_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "DSP_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "DSP_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "DSP_MONITOR_N_3", + "VBRK_MONITOR_N" + ], + [ + "DSP_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "DSP_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "DSP_LH11_3", + "VBRK_LH11" + ], + [ + "DSP_LH6_3", + "VBRK_LH6" + ], + [ + "DSP_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "DSP_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "DSP_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "DSP_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "DSP_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "DSP_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "DSP_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "DSP_MONITOR_P_3", + "VBRK_MONITOR_P" + ], + [ + "DSP_LH10_3", + "VBRK_LH10" + ], + [ + "DSP_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "DSP_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "DSP_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "DSP_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "DSP_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "DSP_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "DSP_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "DSP_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "DSP_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "DSP_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "DSP_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "DSP_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "DSP_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "DSP_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "DSP_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "DSP_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "DSP_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "DSP_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "DSP_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "DSP_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "DSP_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "DSP_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "DSP_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "DSP_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "DSP_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "DSP_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "DSP_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "DSP_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "DSP_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "DSP_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "DSP_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "DSP_WR1END0_3", + "VBRK_WR1END0" + ] + ], + "tile_types": [ + "DSP_L", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 7 + ], + "wire_pairs": [ + [ + "PCIE_IMUX1_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_3", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_EE4A2_3", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_SE4BEG3_3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_WR1END0_3", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_3", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_NW4A2_3", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_NE4C0_3", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_CTRL1_R_3", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_FAN2_R_3", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_IMUX38_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_WW2A0_3", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_EE2A0_3", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_IMUX8_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_WW2END1_3", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_WW2A2_3", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_SE4C2_3", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_IMUX27_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_WW4B0_3", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_WW4END3_3", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_IMUX19_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_WW4B1_3", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_SW4A1_3", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_3", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_FAN5_R_3", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_LH9_3", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_NE4C2_3", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_WW4C2_3", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_WL1END0_3", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_SW2A2_3", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_WR1END3_3", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_NE2A3_3", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_3", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_LH11_3", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_WW4END1_3", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_EE4BEG2_3", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_NW4END3_3", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_EE2BEG0_3", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_3", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_IMUX11_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_SE2A2_3", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_EL1BEG3_3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_IMUX2_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_IMUX22_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_FAN1_R_3", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_FAN4_R_3", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_3", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_WW2A3_3", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_EE4A0_3", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_IMUX3_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_IMUX25_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_BYP4_R_3", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_NE4BEG1_3", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX7_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_IMUX36_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_IMUX9_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_SE4C3_3", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_LH4_3", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_BYP3_R_3", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_SW4A0_3", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_NE2A2_3", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_ER1BEG0_3", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_WW4A1_3", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_NW4END0_3", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_WW2END2_3", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_EE2A2_3", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_LH12_3", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_3", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_SW4END1_3", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_WW2END3_3", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_LH7_3", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_IMUX20_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_EL1BEG2_3", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_WW4B3_3", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_BYP2_R_3", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_SW2A3_3", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_NE4C1_3", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_3", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_SE2A3_3", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_IMUX12_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_IMUX28_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_NW4A1_3", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_3", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_NW2A1_3", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_3", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_IMUX10_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_BYP0_R_3", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_SE4BEG0_3", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_IMUX41_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_IMUX16_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_SE4BEG2_3", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_IMUX14_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_3", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_WW4A3_3", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_MONITOR_P_3", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_IMUX23_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_3", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_NW2A3_3", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_EE4C1_3", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_EE4B3_3", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_IMUX47_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_WW4END2_3", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_LH10_3", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_FAN7_R_3", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_CTRL0_R_3", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_IMUX46_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_EE2BEG1_3", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_NW4A0_3", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WW4A0_3", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_NW2A2_3", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_IMUX43_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_SE4C0_3", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_WL1END3_3", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_LH1_3", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_NE2A1_3", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_IMUX24_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_WW4A2_3", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_WW4B2_3", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_EE2BEG3_3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_3", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_LH3_3", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_SW4A3_3", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_3", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_WW4C1_3", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_WL1END1_3", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_SE4C1_3", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_CLK1_R_3", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_IMUX6_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_NW4END1_3", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_NE4BEG0_3", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_IMUX37_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_3", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_EE4A1_3", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_BYP7_R_3", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_EE4BEG3_3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_SE2A0_3", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_3", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_IMUX15_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_WR1END2_3", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_NE4BEG2_3", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_SW4END3_3", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_IMUX5_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_IMUX0_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_3", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_MONITOR_N_3", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_IMUX18_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_SE4BEG1_3", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_BYP1_R_3", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_EE4BEG1_3", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LH8_3", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4C3_3", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_IMUX34_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_IMUX26_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_NW4END2_3", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_FAN6_R_3", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_BYP5_R_3", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_3", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_SW2A0_3", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_EL1BEG0_3", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_NW2A0_3", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_EE4BEG0_3", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX45_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_NE4C3_3", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_NE2A0_3", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_IMUX35_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_LH2_3", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_IMUX32_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_WW4END0_3", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_EE4B0_3", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_WL1END2_3", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_IMUX33_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_IMUX13_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_3", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_SW4END0_3", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_SW2A1_3", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_LH6_3", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_NE4BEG3_3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_EE4C2_3", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_ER1BEG1_3", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_CLK0_R_3", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_IMUX29_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_SW4A2_3", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_IMUX40_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_NW4A3_3", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_EE2BEG2_3", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_ER1BEG3_3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_3", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_IMUX31_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_WW4C3_3", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_SW4END2_3", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_EE4C0_3", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_EL1BEG1_3", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_EE4B2_3", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_3", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_3", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_FAN3_R_3", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX30_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_WW4C0_3", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_LH5_3", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_EE4A3_3", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_FAN0_R_3", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_IMUX42_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_IMUX4_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_EE2A1_3", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_WW2END0_3", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_BYP6_R_3", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_WW2A1_3", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_IMUX39_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_WR1END1_3", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_IMUX21_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_3", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_ER1BEG2_3", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_3", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_SE2A1_3", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_IMUX44_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_EE4B1_3", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_EE2A3_3", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_IMUX17_R_3", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "IOB_PD_INT_EN_0", + "RIOI_PD_INT_EN_0" + ], + [ + "IOB_DIFF_TERM_INT_EN", + "RIOI_DIFF_TERM_INT_EN" + ], + [ + "IOB_KEEPER_INT_EN_0", + "RIOI_KEEPER_INT_EN_0" + ], + [ + "IOB_PU_INT_EN_1", + "RIOI_PU_INT_EN_1" + ], + [ + "IOB_O0", + "RIOI_O0" + ], + [ + "IOB_KEEPER_INT_EN_1", + "RIOI_KEEPER_INT_EN_1" + ], + [ + "IOB_DCI_T_TERM0", + "RIOI_DCI_T_TERM0" + ], + [ + "IOB_PD_INT_EN_1", + "RIOI_PD_INT_EN_1" + ], + [ + "IOB_T1", + "RIOI_T1" + ], + [ + "IOB_O1", + "RIOI_O1" + ], + [ + "IOB_IBUF_DISABLE1", + "RIOI_IBUF_DISABLE1" + ], + [ + "RIOB_MONITOR_N", + "IOI_MONITOR_N" + ], + [ + "IOB_IBUF1", + "RIOI_IBUF1" + ], + [ + "IOB_IBUF_DISABLE0", + "RIOI_IBUF_DISABLE0" + ], + [ + "IOB_DCI_T_TERM1", + "RIOI_DCI_T_TERM1" + ], + [ + "IOB_IBUF0", + "RIOI_IBUF0" + ], + [ + "IOB_PU_INT_EN_0", + "RIOI_PU_INT_EN_0" + ], + [ + "IOB_T0", + "RIOI_T0" + ], + [ + "RIOB_MONITOR_P", + "IOI_MONITOR_P" + ] + ], + "tile_types": [ + "RIOB18", + "RIOI_TBYTESRC" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_1_SW2A1", + "VFRAME_SW2A1" + ], + [ + "INT_FEEDTHRU_1_NE2A2", + "VFRAME_NE2A2" + ], + [ + "INT_FEEDTHRU_1_NE2A1", + "VFRAME_NE2A1" + ], + [ + "INT_FEEDTHRU_1_LH1", + "VFRAME_LH1" + ], + [ + "INT_FEEDTHRU_1_WW4C1", + "VFRAME_WW4C1" + ], + [ + "INT_FEEDTHRU_1_LH4", + "VFRAME_LH4" + ], + [ + "INT_FEEDTHRU_1_SW2A2", + "VFRAME_SW2A2" + ], + [ + "INT_FEEDTHRU_1_SW4A0", + "VFRAME_SW4A0" + ], + [ + "INT_FEEDTHRU_1_NE2A3", + "VFRAME_NE2A3" + ], + [ + "INT_FEEDTHRU_1_SW4A2", + "VFRAME_SW4A2" + ], + [ + "INT_FEEDTHRU_1_WW2END0", + "VFRAME_WW2END0" + ], + [ + "INT_FEEDTHRU_1_EE2A0", + "VFRAME_EE2A0" + ], + [ + "INT_FEEDTHRU_1_NW2A0", + "VFRAME_NW2A0" + ], + [ + "INT_FEEDTHRU_1_NW4END3", + "VFRAME_NW4END3" + ], + [ + "INT_FEEDTHRU_1_SW4A1", + "VFRAME_SW4A1" + ], + [ + "INT_FEEDTHRU_1_LH8", + "VFRAME_LH8" + ], + [ + "INT_FEEDTHRU_1_LH5", + "VFRAME_LH5" + ], + [ + "INT_FEEDTHRU_1_EE4A1", + "VFRAME_EE4A1" + ], + [ + "INT_FEEDTHRU_1_WW4END0", + "VFRAME_WW4END0" + ], + [ + "INT_FEEDTHRU_1_EL1BEG1", + "VFRAME_EL1BEG1" + ], + [ + "INT_FEEDTHRU_1_SE4BEG3", + "VFRAME_SE4BEG3" + ], + [ + "INT_FEEDTHRU_1_EE4B1", + "VFRAME_EE4B1" + ], + [ + "INT_FEEDTHRU_1_WW4B0", + "VFRAME_WW4B0" + ], + [ + "INT_FEEDTHRU_1_SE4C1", + "VFRAME_SE4C1" + ], + [ + "INT_FEEDTHRU_1_WL1END3", + "VFRAME_WL1END3" + ], + [ + "INT_FEEDTHRU_1_EE4C0", + "VFRAME_EE4C0" + ], + [ + "INT_FEEDTHRU_1_SW4END0", + "VFRAME_SW4END0" + ], + [ + "INT_FEEDTHRU_1_WL1END1", + "VFRAME_WL1END1" + ], + [ + "INT_FEEDTHRU_1_WW2A3", + "VFRAME_WW2A3" + ], + [ + "INT_FEEDTHRU_1_NE2A0", + "VFRAME_NE2A0" + ], + [ + "INT_FEEDTHRU_1_WW4C2", + "VFRAME_WW4C2" + ], + [ + "INT_FEEDTHRU_1_ER1BEG3", + "VFRAME_ER1BEG3" + ], + [ + "INT_FEEDTHRU_1_LH3", + "VFRAME_LH3" + ], + [ + "INT_FEEDTHRU_1_NE4C3", + "VFRAME_NE4C3" + ], + [ + "INT_FEEDTHRU_1_NE4C0", + "VFRAME_NE4C0" + ], + [ + "INT_FEEDTHRU_1_WW4C3", + "VFRAME_WW4C3" + ], + [ + "INT_FEEDTHRU_1_LH11", + "VFRAME_LH11" + ], + [ + "INT_FEEDTHRU_1_NW4END0", + "VFRAME_NW4END0" + ], + [ + "INT_FEEDTHRU_1_WL1END2", + "VFRAME_WL1END2" + ], + [ + "INT_FEEDTHRU_1_WW4A0", + "VFRAME_WW4A0" + ], + [ + "INT_FEEDTHRU_1_WW2END1", + "VFRAME_WW2END1" + ], + [ + "INT_FEEDTHRU_1_EE2BEG2", + "VFRAME_EE2BEG2" + ], + [ + "INT_FEEDTHRU_1_EE4B3", + "VFRAME_EE4B3" + ], + [ + "INT_FEEDTHRU_1_ER1BEG1", + "VFRAME_ER1BEG1" + ], + [ + "INT_FEEDTHRU_1_EE2BEG3", + "VFRAME_EE2BEG3" + ], + [ + "INT_FEEDTHRU_1_EE2BEG1", + "VFRAME_EE2BEG1" + ], + [ + "INT_FEEDTHRU_1_SE4BEG1", + "VFRAME_SE4BEG1" + ], + [ + "INT_FEEDTHRU_1_EE4A0", + "VFRAME_EE4A0" + ], + [ + "INT_FEEDTHRU_1_WW4B3", + "VFRAME_WW4B3" + ], + [ + "INT_FEEDTHRU_1_EE4C1", + "VFRAME_EE4C1" + ], + [ + "INT_FEEDTHRU_1_EL1BEG2", + "VFRAME_EL1BEG2" + ], + [ + "INT_FEEDTHRU_1_WR1END3", + "VFRAME_WR1END3" + ], + [ + "INT_FEEDTHRU_1_LH2", + "VFRAME_LH2" + ], + [ + "INT_FEEDTHRU_1_SE4BEG2", + "VFRAME_SE4BEG2" + ], + [ + "INT_FEEDTHRU_1_LH10", + "VFRAME_LH10" + ], + [ + "INT_FEEDTHRU_1_EE4BEG0", + "VFRAME_EE4BEG0" + ], + [ + "INT_FEEDTHRU_1_WL1END0", + "VFRAME_WL1END0" + ], + [ + "INT_FEEDTHRU_1_SW4END3", + "VFRAME_SW4END3" + ], + [ + "INT_FEEDTHRU_1_WW4A3", + "VFRAME_WW4A3" + ], + [ + "INT_FEEDTHRU_1_LH12", + "VFRAME_LH12" + ], + [ + "INT_FEEDTHRU_1_WW4END2", + "VFRAME_WW4END2" + ], + [ + "INT_FEEDTHRU_1_SW4A3", + "VFRAME_SW4A3" + ], + [ + "INT_FEEDTHRU_1_EE2BEG0", + "VFRAME_EE2BEG0" + ], + [ + "INT_FEEDTHRU_1_EE4B2", + "VFRAME_EE4B2" + ], + [ + "INT_FEEDTHRU_1_NE4C2", + "VFRAME_NE4C2" + ], + [ + "INT_FEEDTHRU_1_WW2A1", + "VFRAME_WW2A1" + ], + [ + "INT_FEEDTHRU_1_EE2A2", + "VFRAME_EE2A2" + ], + [ + "INT_FEEDTHRU_1_EE4BEG1", + "VFRAME_EE4BEG1" + ], + [ + "INT_FEEDTHRU_1_NE4BEG2", + "VFRAME_NE4BEG2" + ], + [ + "INT_FEEDTHRU_1_SE4C2", + "VFRAME_SE4C2" + ], + [ + "INT_FEEDTHRU_1_WW2END3", + "VFRAME_WW2END3" + ], + [ + "INT_FEEDTHRU_1_EE4BEG3", + "VFRAME_EE4BEG3" + ], + [ + "INT_FEEDTHRU_1_SE2A3", + "VFRAME_SE2A3" + ], + [ + "INT_FEEDTHRU_1_NW4A3", + "VFRAME_NW4A3" + ], + [ + "INT_FEEDTHRU_1_NE4BEG1", + "VFRAME_NE4BEG1" + ], + [ + "INT_FEEDTHRU_1_SE4C0", + "VFRAME_SE4C0" + ], + [ + "INT_FEEDTHRU_1_SW4END2", + "VFRAME_SW4END2" + ], + [ + "INT_FEEDTHRU_1_WW2A0", + "VFRAME_WW2A0" + ], + [ + "INT_FEEDTHRU_1_SE2A1", + "VFRAME_SE2A1" + ], + [ + "INT_FEEDTHRU_1_MONITOR_N", + "VFRAME_MONITOR_N" + ], + [ + "INT_FEEDTHRU_1_MONITOR_P", + "VFRAME_MONITOR_P" + ], + [ + "INT_FEEDTHRU_1_ER1BEG0", + "VFRAME_ER1BEG0" + ], + [ + "INT_FEEDTHRU_1_SW2A3", + "VFRAME_SW2A3" + ], + [ + "INT_FEEDTHRU_1_WW4B1", + "VFRAME_WW4B1" + ], + [ + "INT_FEEDTHRU_1_EE4BEG2", + "VFRAME_EE4BEG2" + ], + [ + "INT_FEEDTHRU_1_WW4END1", + "VFRAME_WW4END1" + ], + [ + "INT_FEEDTHRU_1_SE4C3", + "VFRAME_SE4C3" + ], + [ + "INT_FEEDTHRU_1_SE4BEG0", + "VFRAME_SE4BEG0" + ], + [ + "INT_FEEDTHRU_1_WW4END3", + "VFRAME_WW4END3" + ], + [ + "INT_FEEDTHRU_1_NW4A2", + "VFRAME_NW4A2" + ], + [ + "INT_FEEDTHRU_1_EE4C3", + "VFRAME_EE4C3" + ], + [ + "INT_FEEDTHRU_1_SE2A0", + "VFRAME_SE2A0" + ], + [ + "INT_FEEDTHRU_1_NE4BEG0", + "VFRAME_NE4BEG0" + ], + [ + "INT_FEEDTHRU_1_EL1BEG3", + "VFRAME_EL1BEG3" + ], + [ + "INT_FEEDTHRU_1_WR1END2", + "VFRAME_WR1END2" + ], + [ + "INT_FEEDTHRU_1_EE4A3", + "VFRAME_EE4A3" + ], + [ + "INT_FEEDTHRU_1_WR1END1", + "VFRAME_WR1END1" + ], + [ + "INT_FEEDTHRU_1_NW2A2", + "VFRAME_NW2A2" + ], + [ + "INT_FEEDTHRU_1_LH7", + "VFRAME_LH7" + ], + [ + "INT_FEEDTHRU_1_WW4A2", + "VFRAME_WW4A2" + ], + [ + "INT_FEEDTHRU_1_WW4C0", + "VFRAME_WW4C0" + ], + [ + "INT_FEEDTHRU_1_EL1BEG0", + "VFRAME_EL1BEG0" + ], + [ + "INT_FEEDTHRU_1_NW4A1", + "VFRAME_NW4A1" + ], + [ + "INT_FEEDTHRU_1_NW2A3", + "VFRAME_NW2A3" + ], + [ + "INT_FEEDTHRU_1_NW2A1", + "VFRAME_NW2A1" + ], + [ + "INT_FEEDTHRU_1_NW4END1", + "VFRAME_NW4END1" + ], + [ + "INT_FEEDTHRU_1_EE4B0", + "VFRAME_EE4B0" + ], + [ + "INT_FEEDTHRU_1_WW4A1", + "VFRAME_WW4A1" + ], + [ + "INT_FEEDTHRU_1_SW2A0", + "VFRAME_SW2A0" + ], + [ + "INT_FEEDTHRU_1_SW4END1", + "VFRAME_SW4END1" + ], + [ + "INT_FEEDTHRU_1_WW2A2", + "VFRAME_WW2A2" + ], + [ + "INT_FEEDTHRU_1_EE4C2", + "VFRAME_EE4C2" + ], + [ + "INT_FEEDTHRU_1_NE4C1", + "VFRAME_NE4C1" + ], + [ + "INT_FEEDTHRU_1_EE2A3", + "VFRAME_EE2A3" + ], + [ + "INT_FEEDTHRU_1_WW4B2", + "VFRAME_WW4B2" + ], + [ + "INT_FEEDTHRU_1_SE2A2", + "VFRAME_SE2A2" + ], + [ + "INT_FEEDTHRU_1_ER1BEG2", + "VFRAME_ER1BEG2" + ], + [ + "INT_FEEDTHRU_1_EE2A1", + "VFRAME_EE2A1" + ], + [ + "INT_FEEDTHRU_1_LH9", + "VFRAME_LH9" + ], + [ + "INT_FEEDTHRU_1_NW4END2", + "VFRAME_NW4END2" + ], + [ + "INT_FEEDTHRU_1_NE4BEG3", + "VFRAME_NE4BEG3" + ], + [ + "INT_FEEDTHRU_1_WW2END2", + "VFRAME_WW2END2" + ], + [ + "INT_FEEDTHRU_1_WR1END0", + "VFRAME_WR1END0" + ], + [ + "INT_FEEDTHRU_1_EE4A2", + "VFRAME_EE4A2" + ], + [ + "INT_FEEDTHRU_1_LH6", + "VFRAME_LH6" + ], + [ + "INT_FEEDTHRU_1_NW4A0", + "VFRAME_NW4A0" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_1", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4C1_15", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_LH12_15", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_NW4A0_15", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_NW2A1_15", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_WW4C1_15", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_EE2A3_15", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NE4C1_15", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW2END1_15", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_WW4A2_15", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE4A2_15", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_WR1END3_15", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_ER1BEG3_15", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW2A2_15", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NW2A2_15", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_EL1BEG2_15", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_LH2_15", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_SE2A0_15", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_WR1END1_15", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_NE2A0_15", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_LH9_15", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_SE2A1_15", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_EE2BEG3_15", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NW4END3_15", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_SW2A2_15", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_EL1BEG1_15", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SW2A0_15", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WW2END2_15", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_EE4C0_15", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_SW4END1_15", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_WW4B0_15", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_NW2A0_15", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WW4END3_15", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_EE4A0_15", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4BEG2_15", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_NW4END0_15", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_EE4B3_15", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SW4END3_15", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_EE4C2_15", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NE4BEG0_15", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_SE4C0_15", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_WW4C3_15", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4A1_15", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_WW4B1_15", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_EE4B2_15", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_WL1END1_15", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_LH3_15", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_LH1_15", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_SW4END0_15", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EE2A1_15", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_NW4A1_15", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SE4BEG0_15", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SW4END2_15", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_NW4A3_15", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WW4END2_15", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_SE4BEG1_15", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_WW4A3_15", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_WW4END1_15", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_NE4BEG1_15", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WR1END0_15", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH4_15", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE4A1_15", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NE2A2_15", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE4BEG1_15", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_WW4B2_15", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE2BEG1_15", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_WW4B3_15", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_EE2A2_15", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_EE2BEG2_15", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW2A1_15", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WW2END0_15", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_SE4BEG3_15", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_LH7_15", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4END0_15", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WW4A0_15", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE4C3_15", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_NE4C0_15", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_SW4A3_15", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_SE2A3_15", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_LH6_15", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_SW4A0_15", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_NE2A1_15", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_SE4C1_15", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_SE4C3_15", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_SE4BEG2_15", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW2END3_15", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_LH10_15", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WL1END3_15", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_NE4C3_15", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_SW2A1_15", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_WW2A0_15", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WL1END0_15", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_WW4C2_15", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_ER1BEG2_15", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_NE2A3_15", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_NE4BEG3_15", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG0_15", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE4B1_15", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_LH11_15", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_ER1BEG0_15", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NW4END1_15", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NE4BEG2_15", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_SW4A1_15", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_SW2A3_15", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NW4A2_15", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_EE4B0_15", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH5_15", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_LH8_15", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_SE4C2_15", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_WL1END2_15", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WW2A3_15", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_EL1BEG3_15", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_EE4BEG0_15", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE2BEG0_15", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_NW4END2_15", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WR1END2_15", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_SW4A2_15", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_WW4C0_15", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_ER1BEG1_15", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_EE4BEG3_15", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_EE2A0_15", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_SE2A2_15", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_NW2A3_15", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE4C2_15", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE4A3_15", + "INT_FEEDTHRU_2_EE4A3" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 5, + 5 + ], + "wire_pairs": [ + [ + "PCIE_CLK0_L_5", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_SE2A3_5", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_LH10_5", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_LH6_5", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_FAN7_L_5", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_EE2A2_5", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_IMUX25_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_WW4B0_5", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_LH8_5", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4A0_5", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_IMUX29_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_IMUX27_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_IMUX21_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_EE2BEG3_5", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_WW2END2_5", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_EE2A1_5", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_IMUX28_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_FAN0_L_5", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_WL1END2_5", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_NE2A2_5", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_SW2A1_5", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_IMUX6_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_LH2_5", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_WW2A2_5", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_NE2A3_5", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_WW2END1_5", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_IMUX1_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_IMUX41_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_WW4END2_5", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_IMUX30_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_IMUX20_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_WW4C1_5", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_IMUX23_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_IMUX33_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_NW2A3_5", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_EE2BEG1_5", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX26_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_WR1END0_5", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_IMUX16_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_WR1END1_5", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_FAN2_L_5", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_BYP0_L_5", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_SE2A1_5", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_NW2A1_5", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_EE2BEG0_5", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_SE2A0_5", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_SW4END3_5", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_LH11_5", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_IMUX37_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_IMUX18_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_CLK1_L_5", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_IMUX5_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_NE4BEG1_5", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX3_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_NW4A1_5", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_IMUX34_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_EE4BEG3_5", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_NE4C0_5", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_IMUX40_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_NW4END0_5", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_BYP4_L_5", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_IMUX15_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_EL1BEG3_5", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_BYP5_L_5", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_BYP6_L_5", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_NE2A0_5", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_WW4END0_5", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_WW4B1_5", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_IMUX9_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_SE4BEG2_5", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_NW4END2_5", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_EL1BEG1_5", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_IMUX17_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_WW4A3_5", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_NW4END3_5", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_ER1BEG1_5", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_IMUX46_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_NE4C3_5", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_WW2END3_5", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_LH1_5", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_NW4A0_5", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_IMUX38_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_WW4C0_5", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_WW2END0_5", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_IMUX4_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_NE4BEG0_5", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_IMUX2_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_CTRL1_L_5", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_FAN6_L_5", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_IMUX36_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_SW4A0_5", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_BYP1_L_5", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_EE4C3_5", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_EL1BEG0_5", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_IMUX7_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_IMUX0_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_IMUX32_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_LH12_5", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_IMUX13_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_NW4A3_5", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_BYP2_L_5", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_WW4A0_5", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_WL1END0_5", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_FAN4_L_5", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_IMUX43_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_LH3_5", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_EE2A0_5", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_IMUX22_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_ER1BEG3_5", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_LH4_5", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_EL1BEG2_5", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_MONITOR_P_5", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_SE4BEG0_5", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_SW4END0_5", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_LH5_5", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_SW4A3_5", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_LH7_5", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_WW2A0_5", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_IMUX39_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_EE4BEG2_5", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_WW2A3_5", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_NW4A2_5", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_WW4B2_5", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_SE4BEG1_5", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_SW4A1_5", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_SE4BEG3_5", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_SW2A0_5", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_WL1END3_5", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_WW4A1_5", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_NE4BEG2_5", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_EE4B3_5", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_EE4BEG0_5", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_NW2A0_5", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_NE4BEG3_5", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_WW4C2_5", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_SW4A2_5", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_EE4B0_5", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_NW4END1_5", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_IMUX8_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_EE4C0_5", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_BYP7_L_5", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_WW4END1_5", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_SW2A3_5", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_EE4A2_5", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_5", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_SW4END1_5", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_EE4BEG1_5", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LH9_5", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_EE4B1_5", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_EE2BEG2_5", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_ER1BEG0_5", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_SE4C2_5", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_WW4A2_5", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_IMUX31_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_EE4C2_5", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_EE2A3_5", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_EE4A1_5", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_FAN1_L_5", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_SE2A2_5", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_EE4A3_5", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_FAN5_L_5", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_FAN3_L_5", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX12_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_IMUX11_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_WR1END3_5", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_SW4END2_5", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_SE4C1_5", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_EE4C1_5", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_BYP3_L_5", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_IMUX10_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_IMUX47_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_WW4C3_5", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_SE4C3_5", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_NE2A1_5", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_SE4C0_5", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_IMUX44_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_EE4B2_5", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_NE4C2_5", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_SW2A2_5", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_NE4C1_5", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_IMUX35_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_IMUX14_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_WR1END2_5", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_WW4B3_5", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_IMUX19_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_WL1END1_5", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_ER1BEG2_5", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_WW2A1_5", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_MONITOR_N_5", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_CTRL0_L_5", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_IMUX24_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_NW2A2_5", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_IMUX42_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_IMUX45_L_5", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_WW4END3_5", + "INT_INTERFACE_WW4END3" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + -1, + 7 + ], + "wire_pairs": [ + [ + "CFG_CENTER_NE2A3_3", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_EL1BEG3_3", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_NW4A1_3", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_EE4BEG3_3", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_NE2A0_3", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EE4BEG1_3", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_LH3_3", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_WR1END3_3", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_WW4B3_3", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_ER1BEG3_3", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW4END0_3", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EL1BEG2_3", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_SW4END0_3", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_NE4BEG2_3", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_ER1BEG0_3", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_EE4C1_3", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE4A0_3", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_LH2_3", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_EE4B1_3", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EE2A0_3", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_EE4A1_3", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_SE4BEG2_3", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW4END1_3", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_LH7_3", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4A0_3", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SW2A0_3", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WL1END1_3", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_SW4A0_3", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE2BEG2_3", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NE4C0_3", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_NE4C3_3", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_EE4A2_3", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SE4C3_3", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WW4A1_3", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_LH9_3", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NE2A2_3", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE4BEG0_3", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WW2END3_3", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_NE4C1_3", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW4A2_3", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE2A3_3", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW2A2_3", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4C2_3", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW4C0_3", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_SW4A2_3", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NW4END3_3", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_LH11_3", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW2END1_3", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE4B0_3", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_SE2A0_3", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_LH6_3", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WW4C2_3", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_EE2BEG0_3", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_SW4END1_3", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EE4B2_3", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_WW4C1_3", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SE4C2_3", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_LH8_3", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_NE4BEG0_3", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NW4A3_3", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_NW2A2_3", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_NW4END1_3", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NW2A0_3", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WR1END0_3", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_SE2A1_3", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_SW2A1_3", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4C2_3", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NE2A1_3", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_ER1BEG2_3", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_EL1BEG0_3", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_ER1BEG1_3", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SE4C0_3", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_LH4_3", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE2BEG3_3", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_WW4B2_3", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_LH1_3", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_SE4BEG3_3", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_WW2END2_3", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_WW4A3_3", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_SW4END2_3", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SW2A3_3", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_EE4C0_3", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_SE4BEG0_3", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_EE2A2_3", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_SW4A1_3", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NW2A1_3", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SW4A3_3", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE4B3_3", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NE4BEG3_3", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_SE2A3_3", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_NE4BEG1_3", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_EE2BEG1_3", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_LH12_3", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW4END2_3", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_WW2A1_3", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WL1END0_3", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SE4BEG1_3", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_NW4END2_3", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_NW4END0_3", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_WW4END3_3", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_SE2A2_3", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_WR1END2_3", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_WL1END3_3", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_SE4C1_3", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_LH5_3", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_LH10_3", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_NW4A0_3", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_EE4C3_3", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_SW4END3_3", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_SW2A2_3", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WW2A0_3", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_EL1BEG1_3", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW2A3_3", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WR1END1_3", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WW4C3_3", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE4A3_3", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_NW2A3_3", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_EE4BEG2_3", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WW4B0_3", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_NW4A2_3", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WL1END2_3", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_EE2A1_3", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_WW4B1_3", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW2END0_3", + "INT_FEEDTHRU_2_WW2END0" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 0, + -5 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_HROW_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_HROW_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_HROW_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_HROW_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_HROW_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_HROW_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_HROW_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_HROW_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_HROW_R_CK_GCLK4" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_HROW_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_HROW_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_HROW_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_HROW_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_HROW_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_HROW_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_HROW_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_HROW_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + ], + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_HROW_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_HROW_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_HROW_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_HROW_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_HROW_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_HROW_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_HROW_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_HROW_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_HROW_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_HROW_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_HROW_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_HROW_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_HROW_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_HROW_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_HROW_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_HROW_TOP_R" + ] + }, + { + "grid_deltas": [ + -5, + 4 + ], + "wire_pairs": [ + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT47", + "PCIE_IMUX47_L_4" + ], + [ + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_4" + ], + [ + "INT_INTERFACE_EE4C1", + "PCIE_EE4C1_4" + ], + [ + "INT_INTERFACE_EE2A2", + "PCIE_EE2A2_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT24", + "PCIE_IMUX24_L_4" + ], + [ + "INT_INTERFACE_LH1", + "PCIE_LH1_4" + ], + [ + "INT_INTERFACE_BYP7", + "PCIE_BYP7_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT7", + "PCIE_IMUX7_L_4" + ], + [ + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_4" + ], + [ + "INT_INTERFACE_BYP2", + "PCIE_BYP2_L_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "PCIE_LOGIC_OUTS_B22_L_4" + ], + [ + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_4" + ], + [ + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_4" + ], + [ + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "PCIE_LOGIC_OUTS_B14_L_4" + ], + [ + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_4" + ], + [ + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_4" + ], + [ + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_4" + ], + [ + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_4" + ], + [ + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_4" + ], + [ + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_4" + ], + [ + "INT_INTERFACE_CTRL1", + "PCIE_CTRL1_L_4" + ], + [ + "INT_INTERFACE_FAN1", + "PCIE_FAN1_L_4" + ], + [ + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_4" + ], + [ + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_4" + ], + [ + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "PCIE_LOGIC_OUTS_B4_L_4" + ], + [ + "INT_INTERFACE_BYP4", + "PCIE_BYP4_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT33", + "PCIE_IMUX33_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT26", + "PCIE_IMUX26_L_4" + ], + [ + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_4" + ], + [ + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_4" + ], + [ + "INT_INTERFACE_EE4C0", + "PCIE_EE4C0_4" + ], + [ + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT46", + "PCIE_IMUX46_L_4" + ], + [ + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_4" + ], + [ + "INT_INTERFACE_EE2BEG3", + "PCIE_EE2BEG3_4" + ], + [ + "INT_INTERFACE_FAN6", + "PCIE_FAN6_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT4", + "PCIE_IMUX4_L_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "PCIE_LOGIC_OUTS_B6_L_4" + ], + [ + "INT_INTERFACE_LH9", + "PCIE_LH9_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT11", + "PCIE_IMUX11_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT3", + "PCIE_IMUX3_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT43", + "PCIE_IMUX43_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT29", + "PCIE_IMUX29_L_4" + ], + [ + "INT_INTERFACE_EE4B0", + "PCIE_EE4B0_4" + ], + [ + "INT_INTERFACE_LH12", + "PCIE_LH12_4" + ], + [ + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_4" + ], + [ + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT2", + "PCIE_IMUX2_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT15", + "PCIE_IMUX15_L_4" + ], + [ + "INT_INTERFACE_EE2BEG1", + "PCIE_EE2BEG1_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT10", + "PCIE_IMUX10_L_4" + ], + [ + "INT_INTERFACE_EE2A3", + "PCIE_EE2A3_4" + ], + [ + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_4" + ], + [ + "INT_INTERFACE_BYP1", + "PCIE_BYP1_L_4" + ], + [ + "INT_INTERFACE_BYP6", + "PCIE_BYP6_L_4" + ], + [ + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT5", + "PCIE_IMUX5_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT17", + "PCIE_IMUX17_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT19", + "PCIE_IMUX19_L_4" + ], + [ + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "PCIE_LOGIC_OUTS_B1_L_4" + ], + [ + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_4" + ], + [ + "INT_INTERFACE_EE2A1", + "PCIE_EE2A1_4" + ], + [ + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT12", + "PCIE_IMUX12_L_4" + ], + [ + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT42", + "PCIE_IMUX42_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT16", + "PCIE_IMUX16_L_4" + ], + [ + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_4" + ], + [ + "INT_INTERFACE_LH8", + "PCIE_LH8_4" + ], + [ + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "PCIE_LOGIC_OUTS_B5_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT28", + "PCIE_IMUX28_L_4" + ], + [ + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT20", + "PCIE_IMUX20_L_4" + ], + [ + "INT_INTERFACE_ER1BEG0", + "PCIE_ER1BEG0_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT39", + "PCIE_IMUX39_L_4" + ], + [ + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_4" + ], + [ + "INT_INTERFACE_EE4A2", + "PCIE_EE4A2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "PCIE_LOGIC_OUTS_B19_L_4" + ], + [ + "INT_INTERFACE_LH11", + "PCIE_LH11_4" + ], + [ + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_4" + ], + [ + "INT_INTERFACE_LH5", + "PCIE_LH5_4" + ], + [ + "INT_INTERFACE_EL1BEG3", + "PCIE_EL1BEG3_4" + ], + [ + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_4" + ], + [ + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_4" + ], + [ + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_4" + ], + [ + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "PCIE_LOGIC_OUTS_B18_L_4" + ], + [ + "INT_INTERFACE_FAN4", + "PCIE_FAN4_L_4" + ], + [ + "INT_INTERFACE_LH4", + "PCIE_LH4_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "PCIE_LOGIC_OUTS_B9_L_4" + ], + [ + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "PCIE_LOGIC_OUTS_B16_L_4" + ], + [ + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_4" + ], + [ + "INT_INTERFACE_LH10", + "PCIE_LH10_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT23", + "PCIE_IMUX23_L_4" + ], + [ + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_4" + ], + [ + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_4" + ], + [ + "INT_INTERFACE_FAN7", + "PCIE_FAN7_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT45", + "PCIE_IMUX45_L_4" + ], + [ + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT30", + "PCIE_IMUX30_L_4" + ], + [ + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_4" + ], + [ + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_4" + ], + [ + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_4" + ], + [ + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT37", + "PCIE_IMUX37_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT44", + "PCIE_IMUX44_L_4" + ], + [ + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_4" + ], + [ + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_4" + ], + [ + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "PCIE_LOGIC_OUTS_B8_L_4" + ], + [ + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_4" + ], + [ + "INT_INTERFACE_LH6", + "PCIE_LH6_4" + ], + [ + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_4" + ], + [ + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT35", + "PCIE_IMUX35_L_4" + ], + [ + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT18", + "PCIE_IMUX18_L_4" + ], + [ + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_4" + ], + [ + "INT_INTERFACE_EE4A0", + "PCIE_EE4A0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "PCIE_LOGIC_OUTS_B11_L_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "PCIE_LOGIC_OUTS_B0_L_4" + ], + [ + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT14", + "PCIE_IMUX14_L_4" + ], + [ + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_4" + ], + [ + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_4" + ], + [ + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT32", + "PCIE_IMUX32_L_4" + ], + [ + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_4" + ], + [ + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT27", + "PCIE_IMUX27_L_4" + ], + [ + "INT_INTERFACE_EE2BEG2", + "PCIE_EE2BEG2_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT9", + "PCIE_IMUX9_L_4" + ], + [ + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_4" + ], + [ + "INT_INTERFACE_LH7", + "PCIE_LH7_4" + ], + [ + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_4" + ], + [ + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_4" + ], + [ + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_4" + ], + [ + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_4" + ], + [ + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_4" + ], + [ + "INT_INTERFACE_EE2BEG0", + "PCIE_EE2BEG0_4" + ], + [ + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_4" + ], + [ + "INT_INTERFACE_BYP0", + "PCIE_BYP0_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT25", + "PCIE_IMUX25_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT38", + "PCIE_IMUX38_L_4" + ], + [ + "INT_INTERFACE_EE2A0", + "PCIE_EE2A0_4" + ], + [ + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT41", + "PCIE_IMUX41_L_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "PCIE_LOGIC_OUTS_B23_L_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "PCIE_LOGIC_OUTS_B21_L_4" + ], + [ + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "PCIE_LOGIC_OUTS_B15_L_4" + ], + [ + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_4" + ], + [ + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_4" + ], + [ + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_4" + ], + [ + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "PCIE_LOGIC_OUTS_B13_L_4" + ], + [ + "INT_INTERFACE_LH2", + "PCIE_LH2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "PCIE_LOGIC_OUTS_B17_L_4" + ], + [ + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT8", + "PCIE_IMUX8_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT0", + "PCIE_IMUX0_L_4" + ], + [ + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_4" + ], + [ + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_4" + ], + [ + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT34", + "PCIE_IMUX34_L_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "PCIE_LOGIC_OUTS_B2_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT1", + "PCIE_IMUX1_L_4" + ], + [ + "INT_INTERFACE_EE4A1", + "PCIE_EE4A1_4" + ], + [ + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_4" + ], + [ + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_4" + ], + [ + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_4" + ], + [ + "INT_INTERFACE_CLK1", + "PCIE_CLK1_L_4" + ], + [ + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_4" + ], + [ + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_4" + ], + [ + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_4" + ], + [ + "INT_INTERFACE_EE4A3", + "PCIE_EE4A3_4" + ], + [ + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "PCIE_LOGIC_OUTS_B12_L_4" + ], + [ + "INT_INTERFACE_FAN3", + "PCIE_FAN3_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT13", + "PCIE_IMUX13_L_4" + ], + [ + "INT_INTERFACE_CLK0", + "PCIE_CLK0_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT6", + "PCIE_IMUX6_L_4" + ], + [ + "INT_INTERFACE_EE4C2", + "PCIE_EE4C2_4" + ], + [ + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_4" + ], + [ + "INT_INTERFACE_BYP5", + "PCIE_BYP5_L_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "PCIE_LOGIC_OUTS_B3_L_4" + ], + [ + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_4" + ], + [ + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_4" + ], + [ + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_4" + ], + [ + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT22", + "PCIE_IMUX22_L_4" + ], + [ + "INT_INTERFACE_BYP3", + "PCIE_BYP3_L_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "PCIE_LOGIC_OUTS_B20_L_4" + ], + [ + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_4" + ], + [ + "INT_INTERFACE_FAN0", + "PCIE_FAN0_L_4" + ], + [ + "INT_INTERFACE_FAN5", + "PCIE_FAN5_L_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "PCIE_LOGIC_OUTS_B10_L_4" + ], + [ + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT21", + "PCIE_IMUX21_L_4" + ], + [ + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_4" + ], + [ + "INT_INTERFACE_FAN2", + "PCIE_FAN2_L_4" + ], + [ + "INT_INTERFACE_CTRL0", + "PCIE_CTRL0_L_4" + ], + [ + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_4" + ], + [ + "INT_INTERFACE_LH3", + "PCIE_LH3_4" + ], + [ + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_4" + ], + [ + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT31", + "PCIE_IMUX31_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT36", + "PCIE_IMUX36_L_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "PCIE_LOGIC_OUTS_B7_L_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT40", + "PCIE_IMUX40_L_4" + ], + [ + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_4" + ] + ], + "tile_types": [ + "PCIE_INT_INTERFACE_L", + "PCIE_TOP" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_NW2A0", + "BRAM_NW2A0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX26", + "BRAM_IMUX26_UTURN_4" + ], + [ + "INT_INTERFACE_WW2A3", + "BRAM_WW2A3_4" + ], + [ + "INT_INTERFACE_LH9", + "BRAM_LH9_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "BRAM_LOGIC_OUTS_B1_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "BRAM_LOGIC_OUTS_B16_4" + ], + [ + "INT_INTERFACE_CTRL1", + "BRAM_CTRL1_4" + ], + [ + "INT_INTERFACE_EE2A1", + "BRAM_EE2A1_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX27", + "BRAM_IMUX27_UTURN_4" + ], + [ + "INT_INTERFACE_EE4A1", + "BRAM_EE4A1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_4" + ], + [ + "INT_INTERFACE_EE4B1", + "BRAM_EE4B1_4" + ], + [ + "INT_INTERFACE_WW2A0", + "BRAM_WW2A0_4" + ], + [ + "INT_INTERFACE_EE4A2", + "BRAM_EE4A2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "BRAM_LOGIC_OUTS_B9_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX28", + "BRAM_IMUX28_UTURN_4" + ], + [ + "INT_INTERFACE_LH6", + "BRAM_LH6_4" + ], + [ + "INT_INTERFACE_WW4C1", + "BRAM_WW4C1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX32", + "BRAM_IMUX32_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX27", + "BRAM_IMUX27_4" + ], + [ + "INT_INTERFACE_CLK1", + "BRAM_CLK1_4" + ], + [ + "INT_INTERFACE_WW4B2", + "BRAM_WW4B2_4" + ], + [ + "INT_INTERFACE_NE4BEG0", + "BRAM_NE4BEG0_4" + ], + [ + "INT_INTERFACE_FAN0", + "BRAM_FAN0_4" + ], + [ + "INT_INTERFACE_EL1BEG3", + "BRAM_EL1BEG3_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX43", + "BRAM_IMUX43_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX1", + "BRAM_IMUX1_UTURN_4" + ], + [ + "INT_INTERFACE_BYP7", + "BRAM_BYP7_4" + ], + [ + "INT_INTERFACE_WW4B3", + "BRAM_WW4B3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX15", + "BRAM_IMUX15_UTURN_4" + ], + [ + "INT_INTERFACE_WW2A1", + "BRAM_WW2A1_4" + ], + [ + "INT_INTERFACE_SW4END3", + "BRAM_SW4END3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX14", + "BRAM_IMUX14_UTURN_4" + ], + [ + "INT_INTERFACE_WW4END2", + "BRAM_WW4END2_4" + ], + [ + "INT_INTERFACE_LH10", + "BRAM_LH10_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX28", + "BRAM_IMUX28_4" + ], + [ + "INT_INTERFACE_WW4C3", + "BRAM_WW4C3_4" + ], + [ + "INT_INTERFACE_LH2", + "BRAM_LH2_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_4" + ], + [ + "INT_INTERFACE_BYP6", + "BRAM_BYP6_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX4", + "BRAM_IMUX4_UTURN_4" + ], + [ + "INT_INTERFACE_MONITOR_P", + "BRAM_MONITOR_P_4" + ], + [ + "INT_INTERFACE_SE4BEG0", + "BRAM_SE4BEG0_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX32", + "BRAM_IMUX32_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "BRAM_LOGIC_OUTS_B23_4" + ], + [ + "INT_INTERFACE_NW4END1", + "BRAM_NW4END1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX43", + "BRAM_IMUX43_4" + ], + [ + "INT_INTERFACE_EE4C1", + "BRAM_EE4C1_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "BRAM_LOGIC_OUTS_B17_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX45", + "BRAM_IMUX45_UTURN_4" + ], + [ + "INT_INTERFACE_WW4B0", + "BRAM_WW4B0_4" + ], + [ + "INT_INTERFACE_SE2A3", + "BRAM_SE2A3_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "BRAM_LOGIC_OUTS_B5_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX22", + "BRAM_IMUX22_UTURN_4" + ], + [ + "INT_INTERFACE_EE4B0", + "BRAM_EE4B0_4" + ], + [ + "INT_INTERFACE_SE4BEG3", + "BRAM_SE4BEG3_4" + ], + [ + "INT_INTERFACE_EE4B3", + "BRAM_EE4B3_4" + ], + [ + "INT_INTERFACE_FAN5", + "BRAM_FAN5_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX21", + "BRAM_IMUX21_4" + ], + [ + "INT_INTERFACE_WW4END1", + "BRAM_WW4END1_4" + ], + [ + "INT_INTERFACE_NW4END2", + "BRAM_NW4END2_4" + ], + [ + "INT_INTERFACE_EL1BEG2", + "BRAM_EL1BEG2_4" + ], + [ + "INT_INTERFACE_EE4C0", + "BRAM_EE4C0_4" + ], + [ + "INT_INTERFACE_EL1BEG0", + "BRAM_EL1BEG0_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_4" + ], + [ + "INT_INTERFACE_NE4C3", + "BRAM_NE4C3_4" + ], + [ + "INT_INTERFACE_EE2BEG1", + "BRAM_EE2BEG1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "BRAM_LOGIC_OUTS_B13_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX29", + "BRAM_IMUX29_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX37", + "BRAM_IMUX37_UTURN_4" + ], + [ + "INT_INTERFACE_EE2A0", + "BRAM_EE2A0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "BRAM_LOGIC_OUTS_B21_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX22", + "BRAM_IMUX22_4" + ], + [ + "INT_INTERFACE_LH5", + "BRAM_LH5_4" + ], + [ + "INT_INTERFACE_SW2A2", + "BRAM_SW2A2_4" + ], + [ + "INT_INTERFACE_LH4", + "BRAM_LH4_4" + ], + [ + "INT_INTERFACE_ER1BEG2", + "BRAM_ER1BEG2_4" + ], + [ + "INT_INTERFACE_EE2A2", + "BRAM_EE2A2_4" + ], + [ + "INT_INTERFACE_LH12", + "BRAM_LH12_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX46", + "BRAM_IMUX46_4" + ], + [ + "INT_INTERFACE_EE4BEG2", + "BRAM_EE4BEG2_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX41", + "BRAM_IMUX41_4" + ], + [ + "INT_INTERFACE_SE4C3", + "BRAM_SE4C3_4" + ], + [ + "INT_INTERFACE_SW4END2", + "BRAM_SW4END2_4" + ], + [ + "INT_INTERFACE_WW4END0", + "BRAM_WW4END0_4" + ], + [ + "INT_INTERFACE_NE4C0", + "BRAM_NE4C0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "BRAM_LOGIC_OUTS_B20_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX7", + "BRAM_IMUX7_UTURN_4" + ], + [ + "INT_INTERFACE_SE4BEG1", + "BRAM_SE4BEG1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_4" + ], + [ + "INT_INTERFACE_FAN2", + "BRAM_FAN2_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX19", + "BRAM_IMUX19_UTURN_4" + ], + [ + "INT_INTERFACE_SW4A3", + "BRAM_SW4A3_4" + ], + [ + "INT_INTERFACE_EE4BEG3", + "BRAM_EE4BEG3_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "BRAM_LOGIC_OUTS_B12_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX44", + "BRAM_IMUX44_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX11", + "BRAM_IMUX11_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX25", + "BRAM_IMUX25_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX13", + "BRAM_IMUX13_UTURN_4" + ], + [ + "INT_INTERFACE_BYP0", + "BRAM_BYP0_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX47", + "BRAM_IMUX47_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX18", + "BRAM_IMUX18_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX6", + "BRAM_IMUX6_UTURN_4" + ], + [ + "INT_INTERFACE_SW4A0", + "BRAM_SW4A0_4" + ], + [ + "INT_INTERFACE_WW4A2", + "BRAM_WW4A2_4" + ], + [ + "INT_INTERFACE_EE2A3", + "BRAM_EE2A3_4" + ], + [ + "INT_INTERFACE_SW4A2", + "BRAM_SW4A2_4" + ], + [ + "INT_INTERFACE_NE4C1", + "BRAM_NE4C1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX26", + "BRAM_IMUX26_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "BRAM_LOGIC_OUTS_B4_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX34", + "BRAM_IMUX34_UTURN_4" + ], + [ + "INT_INTERFACE_EE4C3", + "BRAM_EE4C3_4" + ], + [ + "INT_INTERFACE_LH3", + "BRAM_LH3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX2", + "BRAM_IMUX2_UTURN_4" + ], + [ + "INT_INTERFACE_NW4END0", + "BRAM_NW4END0_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX36", + "BRAM_IMUX36_4" + ], + [ + "INT_INTERFACE_FAN7", + "BRAM_FAN7_4" + ], + [ + "INT_INTERFACE_WL1END3", + "BRAM_WL1END3_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "BRAM_LOGIC_OUTS_B2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "BRAM_LOGIC_OUTS_B8_4" + ], + [ + "INT_INTERFACE_NW4A2", + "BRAM_NW4A2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "BRAM_LOGIC_OUTS_B7_4" + ], + [ + "INT_INTERFACE_CTRL0", + "BRAM_CTRL0_4" + ], + [ + "INT_INTERFACE_LH11", + "BRAM_LH11_4" + ], + [ + "INT_INTERFACE_SW2A1", + "BRAM_SW2A1_4" + ], + [ + "INT_INTERFACE_FAN4", + "BRAM_FAN4_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX23", + "BRAM_IMUX23_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX5", + "BRAM_IMUX5_UTURN_4" + ], + [ + "INT_INTERFACE_WW4C0", + "BRAM_WW4C0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX35", + "BRAM_IMUX35_UTURN_4" + ], + [ + "INT_INTERFACE_SE2A1", + "BRAM_SE2A1_4" + ], + [ + "INT_INTERFACE_NE2A3", + "BRAM_NE2A3_4" + ], + [ + "INT_INTERFACE_SE4C0", + "BRAM_SE4C0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "BRAM_LOGIC_OUTS_B14_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX25", + "BRAM_IMUX25_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX24", + "BRAM_IMUX24_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_4" + ], + [ + "INT_INTERFACE_EE4C2", + "BRAM_EE4C2_4" + ], + [ + "INT_INTERFACE_NW2A1", + "BRAM_NW2A1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX16", + "BRAM_IMUX16_UTURN_4" + ], + [ + "INT_INTERFACE_NE4BEG1", + "BRAM_NE4BEG1_4" + ], + [ + "INT_INTERFACE_BYP5", + "BRAM_BYP5_4" + ], + [ + "INT_INTERFACE_BYP4", + "BRAM_BYP4_4" + ], + [ + "INT_INTERFACE_SE4C2", + "BRAM_SE4C2_4" + ], + [ + "INT_INTERFACE_SW4END1", + "BRAM_SW4END1_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX40", + "BRAM_IMUX40_UTURN_4" + ], + [ + "INT_INTERFACE_WW4B1", + "BRAM_WW4B1_4" + ], + [ + "INT_INTERFACE_WR1END1", + "BRAM_WR1END1_4" + ], + [ + "INT_INTERFACE_WW2END0", + "BRAM_WW2END0_4" + ], + [ + "INT_INTERFACE_NE4C2", + "BRAM_NE4C2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "BRAM_LOGIC_OUTS_B22_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX24", + "BRAM_IMUX24_4" + ], + [ + "INT_INTERFACE_NE4BEG3", + "BRAM_NE4BEG3_4" + ], + [ + "INT_INTERFACE_WL1END0", + "BRAM_WL1END0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "BRAM_LOGIC_OUTS_B19_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "BRAM_LOGIC_OUTS_B15_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "BRAM_LOGIC_OUTS_B11_4" + ], + [ + "INT_INTERFACE_SW4END0", + "BRAM_SW4END0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX41", + "BRAM_IMUX41_UTURN_4" + ], + [ + "INT_INTERFACE_EE2BEG0", + "BRAM_EE2BEG0_4" + ], + [ + "INT_INTERFACE_WL1END2", + "BRAM_WL1END2_4" + ], + [ + "INT_INTERFACE_LH7", + "BRAM_LH7_4" + ], + [ + "INT_INTERFACE_WW4C2", + "BRAM_WW4C2_4" + ], + [ + "INT_INTERFACE_WL1END1", + "BRAM_WL1END1_4" + ], + [ + "INT_INTERFACE_NW2A3", + "BRAM_NW2A3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX31", + "BRAM_IMUX31_UTURN_4" + ], + [ + "INT_INTERFACE_WW2END3", + "BRAM_WW2END3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX30", + "BRAM_IMUX30_UTURN_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "BRAM_LOGIC_OUTS_B3_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_4" + ], + [ + "INT_INTERFACE_NE2A0", + "BRAM_NE2A0_4" + ], + [ + "INT_INTERFACE_WW2END2", + "BRAM_WW2END2_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX10", + "BRAM_IMUX10_UTURN_4" + ], + [ + "INT_INTERFACE_ER1BEG3", + "BRAM_ER1BEG3_4" + ], + [ + "INT_INTERFACE_WW2END1", + "BRAM_WW2END1_4" + ], + [ + "INT_INTERFACE_WW2A2", + "BRAM_WW2A2_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX39", + "BRAM_IMUX39_4" + ], + [ + "INT_INTERFACE_NE2A2", + "BRAM_NE2A2_4" + ], + [ + "INT_INTERFACE_LH8", + "BRAM_LH8_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX45", + "BRAM_IMUX45_4" + ], + [ + "INT_INTERFACE_WR1END3", + "BRAM_WR1END3_4" + ], + [ + "INT_INTERFACE_CLK0", + "BRAM_CLK0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX3", + "BRAM_IMUX3_UTURN_4" + ], + [ + "INT_INTERFACE_NE2A1", + "BRAM_NE2A1_4" + ], + [ + "INT_INTERFACE_WW4A0", + "BRAM_WW4A0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX42", + "BRAM_IMUX42_UTURN_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "BRAM_LOGIC_OUTS_B0_4" + ], + [ + "INT_INTERFACE_EE4A0", + "BRAM_EE4A0_4" + ], + [ + "INT_INTERFACE_SW4A1", + "BRAM_SW4A1_4" + ], + [ + "INT_INTERFACE_SW2A0", + "BRAM_SW2A0_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX42", + "BRAM_IMUX42_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "BRAM_LOGIC_OUTS_B6_4" + ], + [ + "INT_INTERFACE_SW2A3", + "BRAM_SW2A3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX0", + "BRAM_IMUX0_UTURN_4" + ], + [ + "INT_INTERFACE_NW4A1", + "BRAM_NW4A1_4" + ], + [ + "INT_INTERFACE_SE2A2", + "BRAM_SE2A2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "BRAM_LOGIC_OUTS_B10_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX31", + "BRAM_IMUX31_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX33", + "BRAM_IMUX33_4" + ], + [ + "INT_INTERFACE_ER1BEG1", + "BRAM_ER1BEG1_4" + ], + [ + "INT_INTERFACE_FAN6", + "BRAM_FAN6_4" + ], + [ + "INT_INTERFACE_FAN1", + "BRAM_FAN1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX40", + "BRAM_IMUX40_4" + ], + [ + "INT_INTERFACE_BYP2", + "BRAM_BYP2_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX30", + "BRAM_IMUX30_4" + ], + [ + "INT_INTERFACE_WW4A3", + "BRAM_WW4A3_4" + ], + [ + "INT_INTERFACE_LH1", + "BRAM_LH1_4" + ], + [ + "INT_INTERFACE_NW4A3", + "BRAM_NW4A3_4" + ], + [ + "INT_INTERFACE_EE2BEG3", + "BRAM_EE2BEG3_4" + ], + [ + "INT_INTERFACE_SE2A0", + "BRAM_SE2A0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX17", + "BRAM_IMUX17_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX8", + "BRAM_IMUX8_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX46", + "BRAM_IMUX46_UTURN_4" + ], + [ + "INT_INTERFACE_WW4A1", + "BRAM_WW4A1_4" + ], + [ + "INT_INTERFACE_SE4BEG2", + "BRAM_SE4BEG2_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_4" + ], + [ + "INT_INTERFACE_EL1BEG1", + "BRAM_EL1BEG1_4" + ], + [ + "INT_INTERFACE_BYP1", + "BRAM_BYP1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX34", + "BRAM_IMUX34_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX39", + "BRAM_IMUX39_UTURN_4" + ], + [ + "INT_INTERFACE_EE4B2", + "BRAM_EE4B2_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX29", + "BRAM_IMUX29_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX38", + "BRAM_IMUX38_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_4" + ], + [ + "INT_INTERFACE_EE4A3", + "BRAM_EE4A3_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX37", + "BRAM_IMUX37_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX23", + "BRAM_IMUX23_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX20", + "BRAM_IMUX20_UTURN_4" + ], + [ + "INT_INTERFACE_EE4BEG0", + "BRAM_EE4BEG0_4" + ], + [ + "INT_INTERFACE_ER1BEG0", + "BRAM_ER1BEG0_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX38", + "BRAM_IMUX38_4" + ], + [ + "INT_INTERFACE_EE2BEG2", + "BRAM_EE2BEG2_4" + ], + [ + "INT_INTERFACE_NE4BEG2", + "BRAM_NE4BEG2_4" + ], + [ + "INT_INTERFACE_FAN3", + "BRAM_FAN3_4" + ], + [ + "INT_INTERFACE_NW2A2", + "BRAM_NW2A2_4" + ], + [ + "INT_INTERFACE_WR1END2", + "BRAM_WR1END2_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX9", + "BRAM_IMUX9_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX35", + "BRAM_IMUX35_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX44", + "BRAM_IMUX44_UTURN_4" + ], + [ + "INT_INTERFACE_MONITOR_N", + "BRAM_MONITOR_N_4" + ], + [ + "INT_INTERFACE_NW4END3", + "BRAM_NW4END3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX12", + "BRAM_IMUX12_UTURN_4" + ], + [ + "INT_INTERFACE_WR1END0", + "BRAM_WR1END0_4" + ], + [ + "INT_INTERFACE_WW4END3", + "BRAM_WW4END3_4" + ], + [ + "INT_INTERFACE_SE4C1", + "BRAM_SE4C1_4" + ], + [ + "INT_INTERFACE_EE4BEG1", + "BRAM_EE4BEG1_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX33", + "BRAM_IMUX33_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "BRAM_LOGIC_OUTS_B18_4" + ], + [ + "INT_INTERFACE_NW4A0", + "BRAM_NW4A0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX21", + "BRAM_IMUX21_UTURN_4" + ], + [ + "INT_INTERFACE_BYP3", + "BRAM_BYP3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX47", + "BRAM_IMUX47_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX36", + "BRAM_IMUX36_UTURN_4" + ] + ], + "tile_types": [ + "BRAM_INT_INTERFACE_L", + "BRAM_L" + ] + }, + { + "grid_deltas": [ + 0, + 6 + ], + "wire_pairs": [ + [ + "BRKH_GTX_REFCLK1_LOWER", + "GTXE2_CHANNEL_REFCLK1" + ], + [ + "BRKH_GTX_NORTHREFCLK1_LOWER", + "GTXE2_CHANNEL_NORTHREFCLK1" + ], + [ + "BRKH_GTX_SOUTHREFCLK1_LOWER", + "GTXE2_CHANNEL_SOUTHREFCLK1" + ], + [ + "BRKH_GTX_REFCLK0_LOWER", + "GTXE2_CHANNEL_REFCLK0" + ], + [ + "BRKH_GTX_SOUTHREFCLK0_LOWER", + "GTXE2_CHANNEL_SOUTHREFCLK0" + ], + [ + "BRKH_GTX_NORTHREFCLK0_LOWER", + "GTXE2_CHANNEL_NORTHREFCLK0" + ] + ], + "tile_types": [ + "BRKH_GTX", + "GTX_CHANNEL_3" + ] + }, + { + "grid_deltas": [ + 0, + -2 + ], + "wire_pairs": [ + [ + "IOI_RCLK_DIV_CE3_1", + "IOI_RCLK_DIV_CE3" + ], + [ + "IOI_RCLK_DIV_CE2_1", + "IOI_RCLK_DIV_CE2" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_LEAF_GCLK1" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_LEAF_GCLK0" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_LEAF_GCLK3" + ], + [ + "IOI_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1_1" + ], + [ + "IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_RCLK_FORIO0" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_LEAF_GCLK5" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_RCLK_FORIO3" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_RCLK_FORIO1" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_RCLK_FORIO2" + ], + [ + "IOI_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0_1" + ], + [ + "IOI_IMUX_RC2", + "IOI_IMUX_RC0" + ], + [ + "IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "IOI_IMUX_RC3", + "IOI_IMUX_RC1" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_LEAF_GCLK4" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_LEAF_GCLK2" + ] + ], + "tile_types": [ + "RIOI", + "RIOI_TBYTETERM" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "BRKH_CLB_COUT0_L", + "CLBLM_M_CIN" + ], + [ + "BRKH_CLB_COUT1_L", + "CLBLM_L_CIN" + ] + ], + "tile_types": [ + "BRKH_CLB", + "CLBLM_L" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_IOB_CK_BUFHCLK10", + "HCLK_IOI_CK_BUFHCLK10" + ], + [ + "HCLK_IOB_CK_BUFHCLK6", + "HCLK_IOI_CK_BUFHCLK6" + ], + [ + "HCLK_IOB_PERFCLK2", + "HCLK_IOI_IOCLK_PLL2" + ], + [ + "HCLK_IOB_CK_BUFHCLK11", + "HCLK_IOI_CK_BUFHCLK11" + ], + [ + "HCLK_IOB_PERFCLK0", + "HCLK_IOI_IOCLK_PLL0" + ], + [ + "HCLK_IOB_CK_BUFRCLK1", + "HCLK_IOI_CK_BUFRCLK1" + ], + [ + "HCLK_IOB_CK_BUFHCLK4", + "HCLK_IOI_CK_BUFHCLK4" + ], + [ + "HCLK_IOB_CK_BUFRCLK2", + "HCLK_IOI_CK_BUFRCLK2" + ], + [ + "HCLK_IOB_CK_BUFHCLK1", + "HCLK_IOI_CK_BUFHCLK1" + ], + [ + "HCLK_IOB_CK_BUFHCLK2", + "HCLK_IOI_CK_BUFHCLK2" + ], + [ + "HCLK_IOB_CK_BUFHCLK0", + "HCLK_IOI_CK_BUFHCLK0" + ], + [ + "HCLK_IOB_CK_BUFHCLK3", + "HCLK_IOI_CK_BUFHCLK3" + ], + [ + "HCLK_IOB_PERFCLK3", + "HCLK_IOI_IOCLK_PLL3" + ], + [ + "HCLK_IOB_CK_BUFHCLK5", + "HCLK_IOI_CK_BUFHCLK5" + ], + [ + "HCLK_IOB_CK_BUFHCLK8", + "HCLK_IOI_CK_BUFHCLK8" + ], + [ + "HCLK_IOB_CK_BUFRCLK0", + "HCLK_IOI_CK_BUFRCLK0" + ], + [ + "HCLK_IOB_CK_BUFHCLK7", + "HCLK_IOI_CK_BUFHCLK7" + ], + [ + "HCLK_IOB_CK_BUFHCLK9", + "HCLK_IOI_CK_BUFHCLK9" + ], + [ + "HCLK_IOB_PERFCLK1", + "HCLK_IOI_IOCLK_PLL1" + ], + [ + "HCLK_IOB_CK_BUFRCLK3", + "HCLK_IOI_CK_BUFRCLK3" + ] + ], + "tile_types": [ + "HCLK_IOB", + "HCLK_IOI" + ] + }, + { + "grid_deltas": [ + -1, + 5 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH12_0", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH9_0", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH1_0", + "VBRK_LH1" + ], + [ + "CMT_TOP_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH8_0", + "VBRK_LH8" + ], + [ + "CMT_TOP_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH5_0", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH4_0", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH3_0", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_LH10_0", + "VBRK_LH10" + ], + [ + "CMT_TOP_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH11_0", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_MONITOR_N_0", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH7_0", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH2_0", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH6_0", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_MONITOR_P_0", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SW4A1_0", + "VBRK_SW4A1" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_FEEDTHRU_1_CK_IN8", + "HCLK_FEEDTHRU_2_CK_IN8" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN3", + "HCLK_FEEDTHRU_2_CK_IN3" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK3", + "HCLK_FEEDTHRU_2_CK_BUFRCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN7", + "HCLK_FEEDTHRU_2_CK_IN7" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN13", + "HCLK_FEEDTHRU_2_CK_IN13" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK9", + "HCLK_FEEDTHRU_2_CK_BUFHCLK9" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK2", + "HCLK_FEEDTHRU_2_CK_BUFHCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK5", + "HCLK_FEEDTHRU_2_CK_BUFHCLK5" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK1", + "HCLK_FEEDTHRU_2_CK_BUFHCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN10", + "HCLK_FEEDTHRU_2_CK_IN10" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK1", + "HCLK_FEEDTHRU_2_CK_BUFRCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN5", + "HCLK_FEEDTHRU_2_CK_IN5" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN6", + "HCLK_FEEDTHRU_2_CK_IN6" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN0", + "HCLK_FEEDTHRU_2_CK_IN0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK11", + "HCLK_FEEDTHRU_2_CK_BUFHCLK11" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK7", + "HCLK_FEEDTHRU_2_CK_BUFHCLK7" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN2", + "HCLK_FEEDTHRU_2_CK_IN2" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN4", + "HCLK_FEEDTHRU_2_CK_IN4" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN1", + "HCLK_FEEDTHRU_2_CK_IN1" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN9", + "HCLK_FEEDTHRU_2_CK_IN9" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK3", + "HCLK_FEEDTHRU_2_CK_BUFHCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK8", + "HCLK_FEEDTHRU_2_CK_BUFHCLK8" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN12", + "HCLK_FEEDTHRU_2_CK_IN12" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK10", + "HCLK_FEEDTHRU_2_CK_BUFHCLK10" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK4", + "HCLK_FEEDTHRU_2_CK_BUFHCLK4" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK6", + "HCLK_FEEDTHRU_2_CK_BUFHCLK6" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK0", + "HCLK_FEEDTHRU_2_CK_BUFRCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN11", + "HCLK_FEEDTHRU_2_CK_IN11" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK0", + "HCLK_FEEDTHRU_2_CK_BUFHCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK2", + "HCLK_FEEDTHRU_2_CK_BUFRCLK2" + ] + ], + "tile_types": [ + "HCLK_FEEDTHRU_1", + "HCLK_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CLK_HROW_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_LH2_1", + "VBRK_LH2" + ], + [ + "CLK_HROW_LH4_1", + "VBRK_LH4" + ], + [ + "CLK_HROW_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_MONITOR_P_1", + "VBRK_MONITOR_P" + ], + [ + "CLK_HROW_LH10_1", + "VBRK_LH10" + ], + [ + "CLK_HROW_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_LH3_1", + "VBRK_LH3" + ], + [ + "CLK_HROW_LH9_1", + "VBRK_LH9" + ], + [ + "CLK_HROW_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_LH7_1", + "VBRK_LH7" + ], + [ + "CLK_HROW_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_MONITOR_N_1", + "VBRK_MONITOR_N" + ], + [ + "CLK_HROW_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_LH11_1", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH12_1", + "VBRK_LH12" + ], + [ + "CLK_HROW_LH8_1", + "VBRK_LH8" + ], + [ + "CLK_HROW_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_LH5_1", + "VBRK_LH5" + ], + [ + "CLK_HROW_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_LH1_1", + "VBRK_LH1" + ], + [ + "CLK_HROW_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_LH6_1", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_WW2END2_1", + "VBRK_WW2END2" + ] + ], + "tile_types": [ + "CLK_BUFG_BOT_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "IOI_IMUX11_0", + "TERM_INT_IMUX11" + ], + [ + "IOI_IMUX43_0", + "TERM_INT_IMUX43" + ], + [ + "IOI_FAN1_0", + "TERM_INT_FAN1" + ], + [ + "IOI_CTRL1_0", + "TERM_INT_CTRL1" + ], + [ + "IOI_LOGIC_OUTS18_0", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_BYP2_0", + "TERM_INT_BYP2" + ], + [ + "IOI_LOGIC_OUTS2_0", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_IMUX6_0", + "TERM_INT_IMUX6" + ], + [ + "IOI_IMUX36_0", + "TERM_INT_IMUX36" + ], + [ + "IOI_IMUX34_0", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX0_0", + "TERM_INT_IMUX0" + ], + [ + "IOI_IMUX46_0", + "TERM_INT_IMUX46" + ], + [ + "IOI_IMUX20_0", + "TERM_INT_IMUX20" + ], + [ + "IOI_LOGIC_OUTS23_0", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_LOGIC_OUTS15_0", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX19_0", + "TERM_INT_IMUX19" + ], + [ + "IOI_IMUX47_0", + "TERM_INT_IMUX47" + ], + [ + "IOI_LOGIC_OUTS17_0", + "TERM_INT_LOGIC_OUTS_L_B17" + ], + [ + "IOI_IMUX25_0", + "TERM_INT_IMUX25" + ], + [ + "IOI_LOGIC_OUTS7_0", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_FAN2_0", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX45_0", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX31_0", + "TERM_INT_IMUX31" + ], + [ + "IOI_LOGIC_OUTS19_0", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_IMUX1_0", + "TERM_INT_IMUX1" + ], + [ + "IOI_MONITOR_N", + "TERM_INT_MONITOR_N" + ], + [ + "IOI_IMUX22_0", + "TERM_INT_IMUX22" + ], + [ + "IOI_IMUX12_0", + "TERM_INT_IMUX12" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_BLOCK_OUTS2_0", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "IOI_IMUX40_0", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX10_0", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX16_0", + "TERM_INT_IMUX16" + ], + [ + "IOI_FAN0_0", + "TERM_INT_FAN0" + ], + [ + "IOI_IMUX38_0", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX26_0", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX3_0", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX24_0", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX37_0", + "TERM_INT_IMUX37" + ], + [ + "IOI_LOGIC_OUTS3_0", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_FAN4_0", + "TERM_INT_FAN4" + ], + [ + "RIOI_I2GCLK_TOP0", + "L_TERM_INT_DQS_IOTOPHASER" + ], + [ + "IOI_FAN6_0", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX7_0", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX39_0", + "TERM_INT_IMUX39" + ], + [ + "IOI_CTRL0_0", + "TERM_INT_CTRL0" + ], + [ + "IOI_CLK0_0", + "TERM_INT_CLK0" + ], + [ + "IOI_CLK1_0", + "TERM_INT_CLK1" + ], + [ + "IOI_FAN7_0", + "TERM_INT_FAN7" + ], + [ + "IOI_BYP0_0", + "TERM_INT_BYP0" + ], + [ + "IOI_LOGIC_OUTS0_0", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_LOGIC_OUTS21_0", + "TERM_INT_LOGIC_OUTS_L_B21" + ], + [ + "IOI_LOGIC_OUTS6_0", + "TERM_INT_LOGIC_OUTS_L_B6" + ], + [ + "IOI_IMUX8_0", + "TERM_INT_IMUX8" + ], + [ + "IOI_LOGIC_OUTS16_0", + "TERM_INT_LOGIC_OUTS_L_B16" + ], + [ + "IOI_LOGIC_OUTS11_0", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_BYP6_0", + "TERM_INT_BYP6" + ], + [ + "IOI_IMUX42_0", + "TERM_INT_IMUX42" + ], + [ + "IOI_IMUX30_0", + "TERM_INT_IMUX30" + ], + [ + "IOI_LOGIC_OUTS1_0", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX5_0", + "TERM_INT_IMUX5" + ], + [ + "IOI_IMUX4_0", + "TERM_INT_IMUX4" + ], + [ + "IOI_IMUX17_0", + "TERM_INT_IMUX17" + ], + [ + "IOI_IMUX23_0", + "TERM_INT_IMUX23" + ], + [ + "IOI_IMUX33_0", + "TERM_INT_IMUX33" + ], + [ + "IOI_PHASER_TO_IO_ICLK", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_FAN5_0", + "TERM_INT_FAN5" + ], + [ + "IOI_BYP1_0", + "TERM_INT_BYP1" + ], + [ + "IOI_LOGIC_OUTS9_0", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_LOGIC_OUTS14_0", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_IMUX13_0", + "TERM_INT_IMUX13" + ], + [ + "IOI_IMUX44_0", + "TERM_INT_IMUX44" + ], + [ + "IOI_LOGIC_OUTS20_0", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_LOGIC_OUTS5_0", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_IMUX27_0", + "TERM_INT_IMUX27" + ], + [ + "IOI_IMUX18_0", + "TERM_INT_IMUX18" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_IMUX9_0", + "TERM_INT_IMUX9" + ], + [ + "IOI_BLOCK_OUTS1_0", + "TERM_INT_BLOCK_OUTS_L_B1" + ], + [ + "IOI_FAN3_0", + "TERM_INT_FAN3" + ], + [ + "IOI_LOGIC_OUTS22_0", + "TERM_INT_LOGIC_OUTS_L_B22" + ], + [ + "IOI_BYP5_0", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS8_0", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_PHASER_TO_IO_OCLK", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_BYP4_0", + "TERM_INT_BYP4" + ], + [ + "IOI_LOGIC_OUTS4_0", + "TERM_INT_LOGIC_OUTS_L_B4" + ], + [ + "IOI_BYP7_0", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_0", + "TERM_INT_IMUX2" + ], + [ + "IOI_LOGIC_OUTS13_0", + "TERM_INT_LOGIC_OUTS_L_B13" + ], + [ + "IOI_IMUX35_0", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP3_0", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX15_0", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX29_0", + "TERM_INT_IMUX29" + ], + [ + "IOI_LOGIC_OUTS10_0", + "TERM_INT_LOGIC_OUTS_L_B10" + ], + [ + "IOI_LOGIC_OUTS12_0", + "TERM_INT_LOGIC_OUTS_L_B12" + ], + [ + "IOI_IMUX14_0", + "TERM_INT_IMUX14" + ], + [ + "IOI_MONITOR_P", + "TERM_INT_MONITOR_P" + ], + [ + "IOI_IMUX21_0", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX28_0", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX41_0", + "TERM_INT_IMUX41" + ], + [ + "IOI_BLOCK_OUTS0_0", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_IMUX32_0", + "TERM_INT_IMUX32" + ] + ], + "tile_types": [ + "RIOI", + "R_TERM_INT" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "IOI_CLK1_1", + "TERM_INT_CLK1" + ], + [ + "IOI_IMUX29_1", + "TERM_INT_IMUX29" + ], + [ + "IOI_BYP0_1", + "TERM_INT_BYP0" + ], + [ + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90" + ], + [ + "IOI_IMUX44_1", + "TERM_INT_IMUX44" + ], + [ + "IOI_IMUX28_1", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX5_1", + "TERM_INT_IMUX5" + ], + [ + "IOI_LOGIC_OUTS0_1", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_IMUX30_1", + "TERM_INT_IMUX30" + ], + [ + "IOI_CTRL1_1", + "TERM_INT_CTRL1" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_PHASER_TO_IO_ICLK_0", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_IMUX43_1", + "TERM_INT_IMUX43" + ], + [ + "IOI_IMUX23_1", + "TERM_INT_IMUX23" + ], + [ + "IOI_IMUX18_1", + "TERM_INT_IMUX18" + ], + [ + "IOI_IMUX37_1", + "TERM_INT_IMUX37" + ], + [ + "IOI_IMUX33_1", + "TERM_INT_IMUX33" + ], + [ + "IOI_LOGIC_OUTS7_1", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_LOGIC_OUTS18_1", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_BYP4_1", + "TERM_INT_BYP4" + ], + [ + "IOI_IMUX47_1", + "TERM_INT_IMUX47" + ], + [ + "IOI_LOGIC_OUTS1_1", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX34_1", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX39_1", + "TERM_INT_IMUX39" + ], + [ + "IOI_BYP1_1", + "TERM_INT_BYP1" + ], + [ + "IOI_FAN6_1", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX38_1", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX3_1", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX21_1", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX22_1", + "TERM_INT_IMUX22" + ], + [ + "IOI_PHASER_TO_IO_OCLK_0", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_IMUX26_1", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX11_1", + "TERM_INT_IMUX11" + ], + [ + "IOI_CLK0_1", + "TERM_INT_CLK0" + ], + [ + "IOI_LOGIC_OUTS20_1", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_BYP2_1", + "TERM_INT_BYP2" + ], + [ + "IOI_IMUX8_1", + "TERM_INT_IMUX8" + ], + [ + "IOI_IMUX19_1", + "TERM_INT_IMUX19" + ], + [ + "IOI_LOGIC_OUTS2_1", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_FAN2_1", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX14_1", + "TERM_INT_IMUX14" + ], + [ + "IOI_IMUX7_1", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX40_1", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX25_1", + "TERM_INT_IMUX25" + ], + [ + "IOI_IMUX15_1", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX24_1", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX4_1", + "TERM_INT_IMUX4" + ], + [ + "IOI_IMUX6_1", + "TERM_INT_IMUX6" + ], + [ + "IOI_LOGIC_OUTS15_1", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX41_1", + "TERM_INT_IMUX41" + ], + [ + "IOI_BYP6_1", + "TERM_INT_BYP6" + ], + [ + "IOI_FAN4_1", + "TERM_INT_FAN4" + ], + [ + "IOI_FAN1_1", + "TERM_INT_FAN1" + ], + [ + "IOI_IMUX32_1", + "TERM_INT_IMUX32" + ], + [ + "IOI_IMUX45_1", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX20_1", + "TERM_INT_IMUX20" + ], + [ + "IOI_IMUX46_1", + "TERM_INT_IMUX46" + ], + [ + "IOI_IMUX31_1", + "TERM_INT_IMUX31" + ], + [ + "IOI_FAN0_1", + "TERM_INT_FAN0" + ], + [ + "IOI_IMUX35_1", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP7_1", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_1", + "TERM_INT_IMUX2" + ], + [ + "IOI_IMUX9_1", + "TERM_INT_IMUX9" + ], + [ + "IOI_BYP5_1", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS19_1", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_FAN3_1", + "TERM_INT_FAN3" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_IMUX36_1", + "TERM_INT_IMUX36" + ], + [ + "IOI_BLOCK_OUTS2_1", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "IOI_FAN7_1", + "TERM_INT_FAN7" + ], + [ + "IOI_LOGIC_OUTS5_1", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_LOGIC_OUTS11_1", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_IMUX27_1", + "TERM_INT_IMUX27" + ], + [ + "IOI_LOGIC_OUTS8_1", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_IMUX12_1", + "TERM_INT_IMUX12" + ], + [ + "IOI_LOGIC_OUTS3_1", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_IMUX16_1", + "TERM_INT_IMUX16" + ], + [ + "IOI_LOGIC_OUTS14_1", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_LOGIC_OUTS9_1", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_FAN5_1", + "TERM_INT_FAN5" + ], + [ + "IOI_IMUX1_1", + "TERM_INT_IMUX1" + ], + [ + "IOI_IMUX13_1", + "TERM_INT_IMUX13" + ], + [ + "IOI_IMUX10_1", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX42_1", + "TERM_INT_IMUX42" + ], + [ + "IOI_BLOCK_OUTS0_1", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_CTRL0_1", + "TERM_INT_CTRL0" + ], + [ + "IOI_LOGIC_OUTS23_1", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_IMUX17_1", + "TERM_INT_IMUX17" + ], + [ + "IOI_BYP3_1", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX0_1", + "TERM_INT_IMUX0" + ], + [ + "IOI_LOGIC_OUTS10_1", + "TERM_INT_LOGIC_OUTS_L_B10" + ] + ], + "tile_types": [ + "LIOI3_TBYTESRC", + "L_TERM_INT" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "CMT_TOP_EE4C0_11", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EL1BEG1_11", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG0_11", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH7_11", + "VBRK_LH7" + ], + [ + "CMT_TOP_LH3_11", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE2A0_11", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_ER1BEG1_11", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_NE4C1_11", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH2_11", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW2A1_11", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NE2A3_11", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_MONITOR_N_11", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_ER1BEG2_11", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NW4END2_11", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE4BEG3_11", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C3_11", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE2A2_11", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_SW2A0_11", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW4A1_11", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_LH9_11", + "VBRK_LH9" + ], + [ + "CMT_TOP_SE4C3_11", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WR1END0_11", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_11", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EL1BEG2_11", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_NE4BEG2_11", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_11", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4C2_11", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4C2_11", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW4C3_11", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_LH4_11", + "VBRK_LH4" + ], + [ + "CMT_TOP_NE4C2_11", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EE4BEG0_11", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NE2A0_11", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NW4A1_11", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG1_11", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4C1_11", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_EE2A1_11", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END1_11", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SE4C2_11", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A0_11", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE4B0_11", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_11", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW4B0_11", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C0_11", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4BEG2_11", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_LH11_11", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE2BEG3_11", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_MONITOR_P_11", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WR1END2_11", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_11", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4A2_11", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EE4BEG3_11", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_NW4END3_11", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_LH1_11", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE4C0_11", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SW4END3_11", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SW4END1_11", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_11", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END1_11", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW2A3_11", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH8_11", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A0_11", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_11", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW4B3_11", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW4A2_11", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4B2_11", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE2A0_11", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WW2END3_11", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EE4A3_11", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SE4C1_11", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_ER1BEG0_11", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_NW4END1_11", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A3_11", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4A2_11", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4C3_11", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW2A0_11", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NE2A1_11", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW4A3_11", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NW2A3_11", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NE4BEG3_11", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_WW2A2_11", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG0_11", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW2END0_11", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2A3_11", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4A2_11", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG2_11", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW2A1_11", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SW4END2_11", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG0_11", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_EE4C1_11", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG1_11", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG1_11", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2BEG2_11", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SW2A1_11", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE2A2_11", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WR1END1_11", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW2A3_11", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW2A0_11", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW4B1_11", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C0_11", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4BEG1_11", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH12_11", + "VBRK_LH12" + ], + [ + "CMT_TOP_WW4END2_11", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW2A2_11", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_EE4A1_11", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH5_11", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4A0_11", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_SE2A1_11", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END2_11", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WL1END3_11", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_ER1BEG3_11", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WW4B2_11", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WL1END0_11", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW4END0_11", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_11", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A3_11", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4END3_11", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_11", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4A0_11", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A1_11", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH10_11", + "VBRK_LH10" + ], + [ + "CMT_TOP_SW4END0_11", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW4END1_11", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE2A2_11", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW2A2_11", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG0_11", + "VBRK_EL1BEG0" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CLK_HROW_SW2A3_1", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_EE2BEG1_1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_BYP3_1", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_WL1END0_1", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_WW4C0_1", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_NE2A1_1", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_BUFG_IMUX21_1", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_WW4A2_1", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_NE4C0_1", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_FAN4_1", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_BUFG_IMUX39_1", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_MONITOR_P_1", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_HROW_NE4BEG1_1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_EE2BEG0_1", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_EE2A1_1", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_EL1BEG1_1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_BUFG_IMUX36_1", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_EE4A1_1", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_BUFG_IMUX45_1", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_SW4A2_1", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_NW4A2_1", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_EE2A2_1", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_EE2A0_1", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_FAN2_1", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_SE4C3_1", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_EE4BEG3_1", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_WW4C3_1", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_SW4END0_1", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_BUFG_IMUX42_1", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_CLK0_1", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_CTRL0_1", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_EE4BEG1_1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_WW2END2_1", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_BUFG_IMUX12_1", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_WR1END0_1", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_BUFG_IMUX19_1", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_WW2END0_1", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_EE2BEG3_1", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_BYP5_1", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B1_1", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CLK_HROW_NW2A0_1", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_LH4_1", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_NE2A3_1", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_FAN7_1", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_EE4BEG2_1", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_WW2END3_1", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_NE2A2_1", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_SW4END1_1", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_SW2A1_1", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_EE4B0_1", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_BUFG_IMUX1_1", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_NW4A3_1", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WW2A3_1", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_WR1END3_1", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_NE4BEG2_1", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_BUFG_IMUX14_1", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_EE2A3_1", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_CTRL1_1", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_WW4END2_1", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_BUFG_IMUX43_1", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_EL1BEG3_1", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_LH8_1", + "INT_INTERFACE_LH8" + ], + [ + "CLK_BUFG_IMUX8_1", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_BUFG_IMUX30_1", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_NW4END0_1", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_BYP1_1", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_WW4A1_1", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_LH2_1", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_NW4END2_1", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_EE2BEG2_1", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_NE4C2_1", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_SE2A1_1", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_EE4A0_1", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_BUFG_IMUX37_1", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_CLK1_1", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_LH10_1", + "INT_INTERFACE_LH10" + ], + [ + "CLK_BUFG_IMUX34_1", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_NW2A1_1", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_LH7_1", + "INT_INTERFACE_LH7" + ], + [ + "CLK_BUFG_IMUX35_1", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_LH12_1", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_FAN0_1", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_BUFG_IMUX2_1", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_NE4C3_1", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_LH5_1", + "INT_INTERFACE_LH5" + ], + [ + "CLK_BUFG_IMUX38_1", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_SW2A0_1", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE4C0_1", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_BUFG_IMUX9_1", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_BUFG_IMUX27_1", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_WW4B0_1", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_WL1END2_1", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_FAN5_1", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_NW4A0_1", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_SW4A3_1", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_NE4BEG3_1", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_WW2END1_1", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_SW4A1_1", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_LH3_1", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_WW2A0_1", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4B1_1", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_ER1BEG1_1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_BUFG_IMUX46_1", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_NE4BEG0_1", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_WR1END1_1", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B2_1", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CLK_HROW_WW4B1_1", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_SW4END2_1", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_BUFG_IMUX7_1", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_LH9_1", + "INT_INTERFACE_LH9" + ], + [ + "CLK_BUFG_IMUX4_1", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_LH11_1", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_SW4A0_1", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_NE4C1_1", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_SE2A3_1", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_BYP6_1", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_SW2A2_1", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_SE4BEG0_1", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_NW2A2_1", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_WW4C1_1", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B7_1", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CLK_HROW_ER1BEG3_1", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_NW4END1_1", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_BUFG_IMUX44_1", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_SE4BEG3_1", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_BYP0_1", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B5_1", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CLK_HROW_WW4C2_1", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_LH6_1", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_EL1BEG0_1", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_EE4B2_1", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_FAN3_1", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_BUFG_IMUX10_1", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_LH1_1", + "INT_INTERFACE_LH1" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B3_1", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CLK_BUFG_IMUX47_1", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_NW4END3_1", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_BUFG_IMUX11_1", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_WL1END3_1", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_WW4B3_1", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_BUFG_IMUX20_1", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_BYP7_1", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_BUFG_IMUX5_1", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_BUFG_IMUX28_1", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_BUFG_IMUX29_1", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_BUFG_IMUX22_1", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_SE4C0_1", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_EE4C3_1", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_SE2A2_1", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_BUFG_IMUX18_1", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_BUFG_IMUX6_1", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_BUFG_IMUX40_1", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_WW4A0_1", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_NW4A1_1", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_FAN6_1", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_BUFG_IMUX33_1", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_EE4C1_1", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_BUFG_IMUX16_1", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_EE4B3_1", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_EE4A3_1", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_BUFG_IMUX23_1", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_BUFG_IMUX25_1", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_NE2A0_1", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_WW4B2_1", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_BUFG_IMUX17_1", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_ER1BEG2_1", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_WW4END1_1", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_WW4END0_1", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_MONITOR_N_1", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_HROW_SW4END3_1", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_EL1BEG2_1", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_FAN1_1", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_BUFG_IMUX31_1", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_BYP2_1", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_WL1END1_1", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_EE4BEG0_1", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_BUFG_IMUX15_1", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B0_1", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CLK_HROW_SE4C2_1", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_BUFG_IMUX3_1", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_BUFG_IMUX13_1", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_WW4A3_1", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_BUFG_IMUX26_1", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_BUFG_IMUX32_1", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_WR1END2_1", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B6_1", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B4_1", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CLK_HROW_EE4A2_1", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_SE4BEG2_1", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_SE4C1_1", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_NW2A3_1", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_BUFG_IMUX41_1", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_WW4END3_1", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_BUFG_IMUX0_1", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_EE4C2_1", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_BYP4_1", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_ER1BEG0_1", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_BUFG_IMUX24_1", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_SE2A0_1", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_SE4BEG1_1", + "INT_INTERFACE_SE4BEG1" + ] + ], + "tile_types": [ + "CLK_BUFG_BOT_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B5_7", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX47_7", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_LOGIC_OUTS_B14_7", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX41_7", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX20_7", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_BYP2_7", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_FAN3_7", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_BYP4_7", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_FAN2_7", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_CTRL0_7", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX7_7", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX30_7", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX29_7", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_FAN4_7", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX8_7", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_LOGIC_OUTS_B23_7", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX35_7", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_BYP3_7", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B0_7", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_LOGIC_OUTS_B1_7", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX1_7", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX9_7", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX21_7", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX10_7", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B12_7", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_LOGIC_OUTS_B15_7", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_BYP7_7", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX40_7", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX28_7", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_FAN1_7", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B6_7", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_BYP1_7", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX22_7", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B13_7", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B19_7", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B4_7", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_IMUX34_7", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX18_7", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_LOGIC_OUTS_B16_7", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B9_7", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX16_7", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX0_7", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX32_7", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_CTRL1_7", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_FAN5_7", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_FAN7_7", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX43_7", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_LOGIC_OUTS_B18_7", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX3_7", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_FAN0_7", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX23_7", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX19_7", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX25_7", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX33_7", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_CLK1_7", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX14_7", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_BYP0_7", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_LOGIC_OUTS_B3_7", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX4_7", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX2_7", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX36_7", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX15_7", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_LOGIC_OUTS_B7_7", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_IMUX12_7", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX38_7", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX11_7", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_CLK0_7", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX24_7", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX39_7", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX5_7", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX13_7", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP5_7", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B8_7", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX45_7", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_FAN6_7", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_BYP6_7", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_LOGIC_OUTS_B10_7", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX26_7", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX31_7", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B20_7", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX37_7", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX6_7", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX42_7", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_LOGIC_OUTS_B2_7", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX17_7", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_LOGIC_OUTS_B22_7", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX46_7", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX44_7", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX27_7", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B11_7", + "VBRK_EXT_LOGIC_OUTS_B11" + ] + ], + "tile_types": [ + "GTX_CHANNEL_2", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "CLBLM_NE4BEG3", + "DSP_NE4BEG3_4" + ], + [ + "CLBLM_EE4A0", + "DSP_EE4A0_4" + ], + [ + "CLBLM_ER1BEG3", + "DSP_ER1BEG3_4" + ], + [ + "CLBLM_NE4BEG0", + "DSP_NE4BEG0_4" + ], + [ + "CLBLM_SE4BEG1", + "DSP_SE4BEG1_4" + ], + [ + "CLBLM_WW4END3", + "DSP_WW4END3_4" + ], + [ + "CLBLM_WW2A1", + "DSP_WW2A1_4" + ], + [ + "CLBLM_WW4END0", + "DSP_WW4END0_4" + ], + [ + "CLBLM_SW4A3", + "DSP_SW4A3_4" + ], + [ + "CLBLM_SW2A2", + "DSP_SW2A2_4" + ], + [ + "CLBLM_NW4A3", + "DSP_NW4A3_4" + ], + [ + "CLBLM_WW4B2", + "DSP_WW4B2_4" + ], + [ + "CLBLM_SW4END0", + "DSP_SW4END0_4" + ], + [ + "CLBLM_EE4B3", + "DSP_EE4B3_4" + ], + [ + "CLBLM_LH2", + "DSP_LH2_4" + ], + [ + "CLBLM_WW2END0", + "DSP_WW2END0_4" + ], + [ + "CLBLM_NE4BEG2", + "DSP_NE4BEG2_4" + ], + [ + "CLBLM_SE2A0", + "DSP_SE2A0_4" + ], + [ + "CLBLM_WW4A2", + "DSP_WW4A2_4" + ], + [ + "CLBLM_EE4C3", + "DSP_EE4C3_4" + ], + [ + "CLBLM_NW4A0", + "DSP_NW4A0_4" + ], + [ + "CLBLM_NE2A0", + "DSP_NE2A0_4" + ], + [ + "CLBLM_NW2A2", + "DSP_NW2A2_4" + ], + [ + "CLBLM_WW4C1", + "DSP_WW4C1_4" + ], + [ + "CLBLM_NE4C3", + "DSP_NE4C3_4" + ], + [ + "CLBLM_SW4A1", + "DSP_SW4A1_4" + ], + [ + "CLBLM_EE4C1", + "DSP_EE4C1_4" + ], + [ + "CLBLM_NW4END2", + "DSP_NW4END2_4" + ], + [ + "CLBLM_EE4BEG1", + "DSP_EE4BEG1_4" + ], + [ + "CLBLM_EE2BEG1", + "DSP_EE2BEG1_4" + ], + [ + "CLBLM_ER1BEG2", + "DSP_ER1BEG2_4" + ], + [ + "CLBLM_SW4A2", + "DSP_SW4A2_4" + ], + [ + "CLBLM_EE4B1", + "DSP_EE4B1_4" + ], + [ + "CLBLM_WW4B3", + "DSP_WW4B3_4" + ], + [ + "CLBLM_EE4B0", + "DSP_EE4B0_4" + ], + [ + "CLBLM_SE2A1", + "DSP_SE2A1_4" + ], + [ + "CLBLM_WW4C0", + "DSP_WW4C0_4" + ], + [ + "CLBLM_NE4C2", + "DSP_NE4C2_4" + ], + [ + "CLBLM_SW4END3", + "DSP_SW4END3_4" + ], + [ + "CLBLM_NE2A1", + "DSP_NE2A1_4" + ], + [ + "CLBLM_WW4A3", + "DSP_WW4A3_4" + ], + [ + "CLBLM_LH3", + "DSP_LH3_4" + ], + [ + "CLBLM_SE2A2", + "DSP_SE2A2_4" + ], + [ + "CLBLM_WR1END2", + "DSP_WR1END2_4" + ], + [ + "CLBLM_LH4", + "DSP_LH4_4" + ], + [ + "CLBLM_WL1END0", + "DSP_WL1END0_4" + ], + [ + "CLBLM_EE4BEG2", + "DSP_EE4BEG2_4" + ], + [ + "CLBLM_SE4C1", + "DSP_SE4C1_4" + ], + [ + "CLBLM_WR1END3", + "DSP_WR1END3_4" + ], + [ + "CLBLM_EE4A2", + "DSP_EE4A2_4" + ], + [ + "CLBLM_LH1", + "DSP_LH1_4" + ], + [ + "CLBLM_SE4BEG0", + "DSP_SE4BEG0_4" + ], + [ + "CLBLM_SE4C2", + "DSP_SE4C2_4" + ], + [ + "CLBLM_NE2A2", + "DSP_NE2A2_4" + ], + [ + "CLBLM_SW4END1", + "DSP_SW4END1_4" + ], + [ + "CLBLM_WW4A0", + "DSP_WW4A0_4" + ], + [ + "CLBLM_WL1END2", + "DSP_WL1END2_4" + ], + [ + "CLBLM_WL1END1", + "DSP_WL1END1_4" + ], + [ + "CLBLM_WW2A2", + "DSP_WW2A2_4" + ], + [ + "CLBLM_NW4END0", + "DSP_NW4END0_4" + ], + [ + "CLBLM_WL1END3", + "DSP_WL1END3_4" + ], + [ + "CLBLM_ER1BEG1", + "DSP_ER1BEG1_4" + ], + [ + "CLBLM_NE4BEG1", + "DSP_NE4BEG1_4" + ], + [ + "CLBLM_EE2A2", + "DSP_EE2A2_4" + ], + [ + "CLBLM_LH6", + "DSP_LH6_4" + ], + [ + "CLBLM_SE4BEG3", + "DSP_SE4BEG3_4" + ], + [ + "CLBLM_LH10", + "DSP_LH10_4" + ], + [ + "CLBLM_NW2A1", + "DSP_NW2A1_4" + ], + [ + "CLBLM_NW2A0", + "DSP_NW2A0_4" + ], + [ + "CLBLM_SE4BEG2", + "DSP_SE4BEG2_4" + ], + [ + "CLBLM_WW4B1", + "DSP_WW4B1_4" + ], + [ + "CLBLM_LH5", + "DSP_LH5_4" + ], + [ + "CLBLM_SW2A0", + "DSP_SW2A0_4" + ], + [ + "CLBLM_SW4A0", + "DSP_SW4A0_4" + ], + [ + "CLBLM_WW4C2", + "DSP_WW4C2_4" + ], + [ + "CLBLM_EE2BEG2", + "DSP_EE2BEG2_4" + ], + [ + "CLBLM_EE4C0", + "DSP_EE4C0_4" + ], + [ + "CLBLM_WW4A1", + "DSP_WW4A1_4" + ], + [ + "CLBLM_SW2A1", + "DSP_SW2A1_4" + ], + [ + "CLBLM_WR1END0", + "DSP_WR1END0_4" + ], + [ + "CLBLM_LH11", + "DSP_LH11_4" + ], + [ + "CLBLM_NW4A2", + "DSP_NW4A2_4" + ], + [ + "CLBLM_NW2A3", + "DSP_NW2A3_4" + ], + [ + "CLBLM_WW2END1", + "DSP_WW2END1_4" + ], + [ + "CLBLM_SW4END2", + "DSP_SW4END2_4" + ], + [ + "CLBLM_EE2BEG3", + "DSP_EE2BEG3_4" + ], + [ + "CLBLM_EL1BEG3", + "DSP_EL1BEG3_4" + ], + [ + "CLBLM_ER1BEG0", + "DSP_ER1BEG0_4" + ], + [ + "CLBLM_EE2A1", + "DSP_EE2A1_4" + ], + [ + "CLBLM_EE4A3", + "DSP_EE4A3_4" + ], + [ + "CLBLM_EE2A3", + "DSP_EE2A3_4" + ], + [ + "CLBLM_WW4B0", + "DSP_WW4B0_4" + ], + [ + "CLBLM_WW4END2", + "DSP_WW4END2_4" + ], + [ + "CLBLM_EL1BEG2", + "DSP_EL1BEG2_4" + ], + [ + "CLBLM_NE2A3", + "DSP_NE2A3_4" + ], + [ + "CLBLM_EE4BEG0", + "DSP_EE4BEG0_4" + ], + [ + "CLBLM_EE4C2", + "DSP_EE4C2_4" + ], + [ + "CLBLM_EE4BEG3", + "DSP_EE4BEG3_4" + ], + [ + "CLBLM_NW4END3", + "DSP_NW4END3_4" + ], + [ + "CLBLM_NW4END1", + "DSP_NW4END1_4" + ], + [ + "CLBLM_LH8", + "DSP_LH8_4" + ], + [ + "CLBLM_WW2END2", + "DSP_WW2END2_4" + ], + [ + "CLBLM_WW2END3", + "DSP_WW2END3_4" + ], + [ + "CLBLM_WW4C3", + "DSP_WW4C3_4" + ], + [ + "CLBLM_MONITOR_N", + "DSP_MONITOR_N_4" + ], + [ + "CLBLM_LH7", + "DSP_LH7_4" + ], + [ + "CLBLM_EE2A0", + "DSP_EE2A0_4" + ], + [ + "CLBLM_MONITOR_P", + "DSP_MONITOR_P_4" + ], + [ + "CLBLM_LH12", + "DSP_LH12_4" + ], + [ + "CLBLM_WW2A3", + "DSP_WW2A3_4" + ], + [ + "CLBLM_NW4A1", + "DSP_NW4A1_4" + ], + [ + "CLBLM_EL1BEG1", + "DSP_EL1BEG1_4" + ], + [ + "CLBLM_SW2A3", + "DSP_SW2A3_4" + ], + [ + "CLBLM_EE4A1", + "DSP_EE4A1_4" + ], + [ + "CLBLM_SE2A3", + "DSP_SE2A3_4" + ], + [ + "CLBLM_WW2A0", + "DSP_WW2A0_4" + ], + [ + "CLBLM_LH9", + "DSP_LH9_4" + ], + [ + "CLBLM_NE4C1", + "DSP_NE4C1_4" + ], + [ + "CLBLM_EE2BEG0", + "DSP_EE2BEG0_4" + ], + [ + "CLBLM_SE4C3", + "DSP_SE4C3_4" + ], + [ + "CLBLM_SE4C0", + "DSP_SE4C0_4" + ], + [ + "CLBLM_NE4C0", + "DSP_NE4C0_4" + ], + [ + "CLBLM_EE4B2", + "DSP_EE4B2_4" + ], + [ + "CLBLM_WR1END1", + "DSP_WR1END1_4" + ], + [ + "CLBLM_WW4END1", + "DSP_WW4END1_4" + ], + [ + "CLBLM_EL1BEG0", + "DSP_EL1BEG0_4" + ] + ], + "tile_types": [ + "CLBLM_L", + "DSP_R" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "MONITOR_WW4A2_4", + "VFRAME_WW4A2" + ], + [ + "MONITOR_NW4A0_4", + "VFRAME_NW4A0" + ], + [ + "MONITOR_LH11_4", + "VFRAME_LH11" + ], + [ + "MONITOR_FAN0_4", + "VFRAME_FAN0" + ], + [ + "MONITOR_NW4END0_4", + "VFRAME_NW4END0" + ], + [ + "MONITOR_NW4END3_4", + "VFRAME_NW4END3" + ], + [ + "MONITOR_BYP7_4", + "VFRAME_BYP7" + ], + [ + "MONITOR_EE4A2_4", + "VFRAME_EE4A2" + ], + [ + "MONITOR_ER1BEG2_4", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_CLK1_4", + "VFRAME_CLK1" + ], + [ + "MONITOR_EE2BEG0_4", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_EE2BEG2_4", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_IMUX11_4", + "VFRAME_IMUX11" + ], + [ + "MONITOR_IMUX40_4", + "VFRAME_IMUX40" + ], + [ + "MONITOR_IMUX16_4", + "VFRAME_IMUX16" + ], + [ + "MONITOR_LOGIC_OUTS_B11_4", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "MONITOR_LOGIC_OUTS_B13_4", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "MONITOR_FAN4_4", + "VFRAME_FAN4" + ], + [ + "MONITOR_BYP4_4", + "VFRAME_BYP4" + ], + [ + "MONITOR_IMUX8_4", + "VFRAME_IMUX8" + ], + [ + "MONITOR_SW4END0_4", + "VFRAME_SW4END0" + ], + [ + "MONITOR_SW4A3_4", + "VFRAME_SW4A3" + ], + [ + "MONITOR_IMUX36_4", + "VFRAME_IMUX36" + ], + [ + "MONITOR_LOGIC_OUTS_B8_4", + "VFRAME_LOGIC_OUTS_B8" + ], + [ + "MONITOR_BYP6_4", + "VFRAME_BYP6" + ], + [ + "MONITOR_IMUX4_4", + "VFRAME_IMUX4" + ], + [ + "MONITOR_LOGIC_OUTS_B22_4", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "MONITOR_NW4A3_4", + "VFRAME_NW4A3" + ], + [ + "MONITOR_NE4BEG3_4", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_IMUX27_4", + "VFRAME_IMUX27" + ], + [ + "MONITOR_NE4C3_4", + "VFRAME_NE4C3" + ], + [ + "MONITOR_LH9_4", + "VFRAME_LH9" + ], + [ + "MONITOR_IMUX2_4", + "VFRAME_IMUX2" + ], + [ + "MONITOR_SE4BEG1_4", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_LH3_4", + "VFRAME_LH3" + ], + [ + "MONITOR_EE2A0_4", + "VFRAME_EE2A0" + ], + [ + "MONITOR_EE4C1_4", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX7_4", + "VFRAME_IMUX7" + ], + [ + "MONITOR_LH10_4", + "VFRAME_LH10" + ], + [ + "MONITOR_IMUX28_4", + "VFRAME_IMUX28" + ], + [ + "MONITOR_IMUX24_4", + "VFRAME_IMUX24" + ], + [ + "MONITOR_IMUX33_4", + "VFRAME_IMUX33" + ], + [ + "MONITOR_IMUX30_4", + "VFRAME_IMUX30" + ], + [ + "MONITOR_SW2A3_4", + "VFRAME_SW2A3" + ], + [ + "MONITOR_WR1END3_4", + "VFRAME_WR1END3" + ], + [ + "MONITOR_IMUX31_4", + "VFRAME_IMUX31" + ], + [ + "MONITOR_WW4A3_4", + "VFRAME_WW4A3" + ], + [ + "MONITOR_IMUX22_4", + "VFRAME_IMUX22" + ], + [ + "MONITOR_SW4END2_4", + "VFRAME_SW4END2" + ], + [ + "MONITOR_IMUX10_4", + "VFRAME_IMUX10" + ], + [ + "MONITOR_LOGIC_OUTS_B14_4", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "MONITOR_IMUX25_4", + "VFRAME_IMUX25" + ], + [ + "MONITOR_IMUX45_4", + "VFRAME_IMUX45" + ], + [ + "MONITOR_NW4END1_4", + "VFRAME_NW4END1" + ], + [ + "MONITOR_EE4BEG0_4", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_FAN3_4", + "VFRAME_FAN3" + ], + [ + "MONITOR_BYP5_4", + "VFRAME_BYP5" + ], + [ + "MONITOR_WW4C2_4", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE4B3_4", + "VFRAME_EE4B3" + ], + [ + "MONITOR_EE4C3_4", + "VFRAME_EE4C3" + ], + [ + "MONITOR_EE4A0_4", + "VFRAME_EE4A0" + ], + [ + "MONITOR_WW4A1_4", + "VFRAME_WW4A1" + ], + [ + "MONITOR_IMUX14_4", + "VFRAME_IMUX14" + ], + [ + "MONITOR_WW4B2_4", + "VFRAME_WW4B2" + ], + [ + "MONITOR_LOGIC_OUTS_B19_4", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "MONITOR_IMUX17_4", + "VFRAME_IMUX17" + ], + [ + "MONITOR_IMUX19_4", + "VFRAME_IMUX19" + ], + [ + "MONITOR_SE2A2_4", + "VFRAME_SE2A2" + ], + [ + "MONITOR_EE4C2_4", + "VFRAME_EE4C2" + ], + [ + "MONITOR_EE4BEG3_4", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_SE4BEG2_4", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_LOGIC_OUTS_B20_4", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "MONITOR_LH7_4", + "VFRAME_LH7" + ], + [ + "MONITOR_IMUX21_4", + "VFRAME_IMUX21" + ], + [ + "MONITOR_WW4B0_4", + "VFRAME_WW4B0" + ], + [ + "MONITOR_SW4END1_4", + "VFRAME_SW4END1" + ], + [ + "MONITOR_EE4B1_4", + "VFRAME_EE4B1" + ], + [ + "MONITOR_LOGIC_OUTS_B17_4", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "MONITOR_NE2A1_4", + "VFRAME_NE2A1" + ], + [ + "MONITOR_WW2A0_4", + "VFRAME_WW2A0" + ], + [ + "MONITOR_EE4A3_4", + "VFRAME_EE4A3" + ], + [ + "MONITOR_NE4BEG0_4", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_WW4B3_4", + "VFRAME_WW4B3" + ], + [ + "MONITOR_IMUX42_4", + "VFRAME_IMUX42" + ], + [ + "MONITOR_CLK0_4", + "VFRAME_CLK0" + ], + [ + "MONITOR_IMUX26_4", + "VFRAME_IMUX26" + ], + [ + "MONITOR_SE4C1_4", + "VFRAME_SE4C1" + ], + [ + "MONITOR_WW2A3_4", + "VFRAME_WW2A3" + ], + [ + "MONITOR_LH5_4", + "VFRAME_LH5" + ], + [ + "MONITOR_SW4A1_4", + "VFRAME_SW4A1" + ], + [ + "MONITOR_FAN2_4", + "VFRAME_FAN2" + ], + [ + "MONITOR_LOGIC_OUTS_B23_4", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "MONITOR_WL1END3_4", + "VFRAME_WL1END3" + ], + [ + "MONITOR_CTRL1_4", + "VFRAME_CTRL1" + ], + [ + "MONITOR_WW4C1_4", + "VFRAME_WW4C1" + ], + [ + "MONITOR_WW4END0_4", + "VFRAME_WW4END0" + ], + [ + "MONITOR_WW4C3_4", + "VFRAME_WW4C3" + ], + [ + "MONITOR_WR1END0_4", + "VFRAME_WR1END0" + ], + [ + "MONITOR_EE4B0_4", + "VFRAME_EE4B0" + ], + [ + "MONITOR_EL1BEG0_4", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_SE4BEG3_4", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_SW2A0_4", + "VFRAME_SW2A0" + ], + [ + "MONITOR_FAN1_4", + "VFRAME_FAN1" + ], + [ + "MONITOR_EE2BEG3_4", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_WW4END2_4", + "VFRAME_WW4END2" + ], + [ + "MONITOR_BYP3_4", + "VFRAME_BYP3" + ], + [ + "MONITOR_EE2A2_4", + "VFRAME_EE2A2" + ], + [ + "MONITOR_WR1END1_4", + "VFRAME_WR1END1" + ], + [ + "MONITOR_NE2A2_4", + "VFRAME_NE2A2" + ], + [ + "MONITOR_SW2A1_4", + "VFRAME_SW2A1" + ], + [ + "MONITOR_IMUX44_4", + "VFRAME_IMUX44" + ], + [ + "MONITOR_SE4C0_4", + "VFRAME_SE4C0" + ], + [ + "MONITOR_EE4BEG2_4", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_SE2A3_4", + "VFRAME_SE2A3" + ], + [ + "MONITOR_LOGIC_OUTS_B10_4", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "MONITOR_IMUX39_4", + "VFRAME_IMUX39" + ], + [ + "MONITOR_NW2A2_4", + "VFRAME_NW2A2" + ], + [ + "MONITOR_IMUX35_4", + "VFRAME_IMUX35" + ], + [ + "MONITOR_EE4BEG1_4", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX6_4", + "VFRAME_IMUX6" + ], + [ + "MONITOR_BYP2_4", + "VFRAME_BYP2" + ], + [ + "MONITOR_NE4C1_4", + "VFRAME_NE4C1" + ], + [ + "MONITOR_LH12_4", + "VFRAME_LH12" + ], + [ + "MONITOR_LOGIC_OUTS_B21_4", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "MONITOR_NW4END2_4", + "VFRAME_NW4END2" + ], + [ + "MONITOR_SE4C2_4", + "VFRAME_SE4C2" + ], + [ + "MONITOR_NW2A3_4", + "VFRAME_NW2A3" + ], + [ + "MONITOR_IMUX34_4", + "VFRAME_IMUX34" + ], + [ + "MONITOR_LH6_4", + "VFRAME_LH6" + ], + [ + "MONITOR_WW4C0_4", + "VFRAME_WW4C0" + ], + [ + "MONITOR_ER1BEG0_4", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_NW4A1_4", + "VFRAME_NW4A1" + ], + [ + "MONITOR_IMUX47_4", + "VFRAME_IMUX47" + ], + [ + "MONITOR_LH4_4", + "VFRAME_LH4" + ], + [ + "MONITOR_WW4END1_4", + "VFRAME_WW4END1" + ], + [ + "MONITOR_ER1BEG1_4", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_IMUX32_4", + "VFRAME_IMUX32" + ], + [ + "MONITOR_FAN5_4", + "VFRAME_FAN5" + ], + [ + "MONITOR_EE4A1_4", + "VFRAME_EE4A1" + ], + [ + "MONITOR_IMUX3_4", + "VFRAME_IMUX3" + ], + [ + "MONITOR_BYP0_4", + "VFRAME_BYP0" + ], + [ + "MONITOR_WW4B1_4", + "VFRAME_WW4B1" + ], + [ + "MONITOR_LOGIC_OUTS_B9_4", + "VFRAME_LOGIC_OUTS_B9" + ], + [ + "MONITOR_IMUX43_4", + "VFRAME_IMUX43" + ], + [ + "MONITOR_LOGIC_OUTS_B18_4", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "MONITOR_WW2END3_4", + "VFRAME_WW2END3" + ], + [ + "MONITOR_WL1END2_4", + "VFRAME_WL1END2" + ], + [ + "MONITOR_SW4END3_4", + "VFRAME_SW4END3" + ], + [ + "MONITOR_FAN7_4", + "VFRAME_FAN7" + ], + [ + "MONITOR_WW2A1_4", + "VFRAME_WW2A1" + ], + [ + "MONITOR_NW4A2_4", + "VFRAME_NW4A2" + ], + [ + "MONITOR_SW2A2_4", + "VFRAME_SW2A2" + ], + [ + "MONITOR_IMUX37_4", + "VFRAME_IMUX37" + ], + [ + "MONITOR_LOGIC_OUTS_B12_4", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "MONITOR_NE4C2_4", + "VFRAME_NE4C2" + ], + [ + "MONITOR_EL1BEG1_4", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_FAN6_4", + "VFRAME_FAN6" + ], + [ + "MONITOR_WW2END1_4", + "VFRAME_WW2END1" + ], + [ + "MONITOR_NE4C0_4", + "VFRAME_NE4C0" + ], + [ + "MONITOR_LOGIC_OUTS_B15_4", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "MONITOR_IMUX0_4", + "VFRAME_IMUX0" + ], + [ + "MONITOR_SW4A2_4", + "VFRAME_SW4A2" + ], + [ + "MONITOR_IMUX46_4", + "VFRAME_IMUX46" + ], + [ + "MONITOR_IMUX13_4", + "VFRAME_IMUX13" + ], + [ + "MONITOR_WL1END1_4", + "VFRAME_WL1END1" + ], + [ + "MONITOR_NE2A0_4", + "VFRAME_NE2A0" + ], + [ + "MONITOR_LH1_4", + "VFRAME_LH1" + ], + [ + "MONITOR_EL1BEG3_4", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_EE4C0_4", + "VFRAME_EE4C0" + ], + [ + "MONITOR_NE4BEG1_4", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_WW4A0_4", + "VFRAME_WW4A0" + ], + [ + "MONITOR_SE4BEG0_4", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_WL1END0_4", + "VFRAME_WL1END0" + ], + [ + "MONITOR_IMUX12_4", + "VFRAME_IMUX12" + ], + [ + "MONITOR_EL1BEG2_4", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_SE4C3_4", + "VFRAME_SE4C3" + ], + [ + "MONITOR_IMUX41_4", + "VFRAME_IMUX41" + ], + [ + "MONITOR_WW2A2_4", + "VFRAME_WW2A2" + ], + [ + "MONITOR_WW2END2_4", + "VFRAME_WW2END2" + ], + [ + "MONITOR_LH2_4", + "VFRAME_LH2" + ], + [ + "MONITOR_IMUX23_4", + "VFRAME_IMUX23" + ], + [ + "MONITOR_LH8_4", + "VFRAME_LH8" + ], + [ + "MONITOR_IMUX20_4", + "VFRAME_IMUX20" + ], + [ + "MONITOR_IMUX5_4", + "VFRAME_IMUX5" + ], + [ + "MONITOR_WW2END0_4", + "VFRAME_WW2END0" + ], + [ + "MONITOR_BYP1_4", + "VFRAME_BYP1" + ], + [ + "MONITOR_SE2A1_4", + "VFRAME_SE2A1" + ], + [ + "MONITOR_CTRL0_4", + "VFRAME_CTRL0" + ], + [ + "MONITOR_WW4END3_4", + "VFRAME_WW4END3" + ], + [ + "MONITOR_LOGIC_OUTS_B16_4", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "MONITOR_EE4B2_4", + "VFRAME_EE4B2" + ], + [ + "MONITOR_ER1BEG3_4", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_IMUX1_4", + "VFRAME_IMUX1" + ], + [ + "MONITOR_SE2A0_4", + "VFRAME_SE2A0" + ], + [ + "MONITOR_EE2A3_4", + "VFRAME_EE2A3" + ], + [ + "MONITOR_IMUX18_4", + "VFRAME_IMUX18" + ], + [ + "MONITOR_IMUX15_4", + "VFRAME_IMUX15" + ], + [ + "MONITOR_WR1END2_4", + "VFRAME_WR1END2" + ], + [ + "MONITOR_NW2A0_4", + "VFRAME_NW2A0" + ], + [ + "MONITOR_NW2A1_4", + "VFRAME_NW2A1" + ], + [ + "MONITOR_IMUX29_4", + "VFRAME_IMUX29" + ], + [ + "MONITOR_NE2A3_4", + "VFRAME_NE2A3" + ], + [ + "MONITOR_EE2A1_4", + "VFRAME_EE2A1" + ], + [ + "MONITOR_EE2BEG1_4", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_NE4BEG2_4", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_IMUX9_4", + "VFRAME_IMUX9" + ], + [ + "MONITOR_IMUX38_4", + "VFRAME_IMUX38" + ], + [ + "MONITOR_SW4A0_4", + "VFRAME_SW4A0" + ] + ], + "tile_types": [ + "MONITOR_BOT_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_EL1BEG0", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "INT_FEEDTHRU_2_LH10", + "INT_FEEDTHRU_2_LH10" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "INT_FEEDTHRU_2_LH2", + "INT_FEEDTHRU_2_LH2" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "INT_FEEDTHRU_2_LH7", + "INT_FEEDTHRU_2_LH7" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "INT_FEEDTHRU_2_LH4", + "INT_FEEDTHRU_2_LH4" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "INT_FEEDTHRU_2_LH8", + "INT_FEEDTHRU_2_LH8" + ], + [ + "INT_FEEDTHRU_2_LH11", + "INT_FEEDTHRU_2_LH11" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "INT_FEEDTHRU_2_LH6", + "INT_FEEDTHRU_2_LH6" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "INT_FEEDTHRU_2_LH3", + "INT_FEEDTHRU_2_LH3" + ], + [ + "INT_FEEDTHRU_2_LH12", + "INT_FEEDTHRU_2_LH12" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "INT_FEEDTHRU_2_MONITOR_P", + "INT_FEEDTHRU_2_MONITOR_P" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "INT_FEEDTHRU_2_LH1", + "INT_FEEDTHRU_2_LH1" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "INT_FEEDTHRU_2_LH5", + "INT_FEEDTHRU_2_LH5" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "INT_FEEDTHRU_2_LH9", + "INT_FEEDTHRU_2_LH9" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "INT_FEEDTHRU_2_MONITOR_N", + "INT_FEEDTHRU_2_MONITOR_N" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "INT_FEEDTHRU_2_ER1BEG0" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -7 + ], + "wire_pairs": [ + [ + "CMT_TOP_EE2A1_15", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW4B1_15", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_NW4END0_15", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_EE4B0_15", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WL1END0_15", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SW4A3_15", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WL1END3_15", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NE2A2_15", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_SW2A3_15", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH5_15", + "VBRK_LH5" + ], + [ + "CMT_TOP_NW4END1_15", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A1_15", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EE2A0_15", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_WR1END3_15", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW4B2_15", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4A2_15", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE2A0_15", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NE4C0_15", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_NW2A0_15", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG2_15", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_NW4A0_15", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_SW2A0_15", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NW4A1_15", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE4C2_15", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2BEG3_15", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4C3_15", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW2A3_15", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WR1END0_15", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_NW4END2_15", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4C2_15", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SW4END0_15", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_LH1_15", + "VBRK_LH1" + ], + [ + "CMT_TOP_MONITOR_N_15", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WW4END3_15", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE2A3_15", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4BEG1_15", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WL1END2_15", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_SE4BEG2_15", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4C3_15", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE4BEG1_15", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_WW4C0_15", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4A3_15", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_WW2A1_15", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW2A3_15", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4BEG3_15", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NW4A2_15", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_WW4END0_15", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EE4A0_15", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_SE4BEG1_15", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2A2_15", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4C2_15", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW2A2_15", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SE4C3_15", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_SE2A1_15", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_LH8_15", + "VBRK_LH8" + ], + [ + "CMT_TOP_LH7_15", + "VBRK_LH7" + ], + [ + "CMT_TOP_SW2A2_15", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4B1_15", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_LH12_15", + "VBRK_LH12" + ], + [ + "CMT_TOP_NE4BEG0_15", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_15", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EL1BEG2_15", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_NE2A1_15", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_WW2END2_15", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW4B0_15", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_LH9_15", + "VBRK_LH9" + ], + [ + "CMT_TOP_SE4C1_15", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE4C1_15", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG0_15", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4A3_15", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_LH4_15", + "VBRK_LH4" + ], + [ + "CMT_TOP_SE4C0_15", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_WW4END2_15", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_WW4A2_15", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG0_15", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_SW4A2_15", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EE4BEG3_15", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW2A2_15", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4A0_15", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_SW4END3_15", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SW4END1_15", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_WW2A0_15", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WR1END1_15", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH6_15", + "VBRK_LH6" + ], + [ + "CMT_TOP_NW2A1_15", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_LH3_15", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C1_15", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE2BEG1_15", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SW4A1_15", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE4BEG2_15", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW4END3_15", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EL1BEG3_15", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW2END3_15", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_ER1BEG0_15", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SE4BEG3_15", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH10_15", + "VBRK_LH10" + ], + [ + "CMT_TOP_LH11_15", + "VBRK_LH11" + ], + [ + "CMT_TOP_NE2A3_15", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WL1END1_15", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW4C1_15", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_EE4C0_15", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WW2END0_15", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2END1_15", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4B3_15", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW4END2_15", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_WW4END1_15", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_WW4A1_15", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE2BEG0_15", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_ER1BEG2_15", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NW4A3_15", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SE2A2_15", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4A0_15", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_SW2A1_15", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_SE4C2_15", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE2A0_15", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_MONITOR_P_15", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW4B3_15", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4B2_15", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_WW4C3_15", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_EE2A3_15", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4BEG0_15", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH2_15", + "VBRK_LH2" + ], + [ + "CMT_TOP_WR1END2_15", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_ER1BEG3_15", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE2BEG2_15", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EL1BEG1_15", + "VBRK_EL1BEG1" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -6 + ], + "wire_pairs": [ + [ + "BRKH_GTX_REFCLK0_UPPER", + "GTXE2_CHANNEL_REFCLK0" + ], + [ + "BRKH_GTX_SOUTHREFCLK0_UPPER", + "GTXE2_CHANNEL_SOUTHREFCLK0" + ], + [ + "BRKH_GTX_REFCLK1_UPPER", + "GTXE2_CHANNEL_REFCLK1" + ], + [ + "BRKH_GTX_NORTHREFCLK0_UPPER", + "GTXE2_CHANNEL_NORTHREFCLK0" + ], + [ + "BRKH_GTX_NORTHREFCLK1_UPPER", + "GTXE2_CHANNEL_NORTHREFCLK1" + ], + [ + "BRKH_GTX_SOUTHREFCLK1_UPPER", + "GTXE2_CHANNEL_SOUTHREFCLK1" + ] + ], + "tile_types": [ + "BRKH_GTX", + "GTX_CHANNEL_0" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "CFG_CENTER_LH7_14", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_SE4BEG1_14", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SW2A1_14", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4B2_14", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_NE2A3_14", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_EE4B0_14", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_ER1BEG3_14", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_SE4BEG3_14", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_NE4BEG1_14", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WW4B2_14", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE4A3_14", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE4BEG1_14", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_NE4C3_14", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_EE4BEG3_14", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_EE4C3_14", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW2END0_14", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WW4B0_14", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_SW4END0_14", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_ER1BEG1_14", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SE4C3_14", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_NE2A0_14", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EE2BEG0_14", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4C1_14", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SW4END3_14", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_SW2A2_14", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_SW4A3_14", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_SE2A1_14", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_EE4C2_14", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW4A0_14", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_EL1BEG2_14", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_ER1BEG0_14", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NE4BEG2_14", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_LH6_14", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_SE4BEG0_14", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_NE4C1_14", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_SE4C1_14", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_EE4B1_14", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EL1BEG0_14", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_WW4A0_14", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EL1BEG3_14", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_ER1BEG2_14", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_NW4A3_14", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WR1END1_14", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SW4A1_14", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_EE2BEG1_14", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_EL1BEG1_14", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SE4BEG2_14", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_SE2A2_14", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_NW2A2_14", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_WW4END1_14", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_SW4END2_14", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WW4A3_14", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NW4END3_14", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_EE2A2_14", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_NW2A1_14", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4A0_14", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_SW2A3_14", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_WW2A2_14", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_SE4C2_14", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_WW2END1_14", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE2A3_14", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_SE2A3_14", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_WR1END2_14", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_WL1END3_14", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_SW2A0_14", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WL1END0_14", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_NW4A2_14", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WW4A1_14", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_SW4END1_14", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_LH5_14", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_LH10_14", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_EE4BEG0_14", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WR1END3_14", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE4C0_14", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_NE2A2_14", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_LH3_14", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_EE4BEG2_14", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WW4B3_14", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_NE4BEG3_14", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW2A3_14", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_SE2A0_14", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_NW2A0_14", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_SW4A2_14", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NW4END2_14", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_EE2A1_14", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_WW4C0_14", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NW2A3_14", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NW4END1_14", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_WL1END1_14", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_WW4C2_14", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_EE4B3_14", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_LH1_14", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_LH2_14", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_WR1END0_14", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH9_14", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_WW4A2_14", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WW2END2_14", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_WW4END3_14", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4END0_14", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EE2BEG3_14", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_WW4END2_14", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_EE4C1_14", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_NE4C0_14", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_NW4END0_14", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SE4C0_14", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_EE2BEG2_14", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WL1END2_14", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_LH11_14", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW2END3_14", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_WW4B1_14", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_SW4A0_14", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE4A2_14", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_NE4BEG0_14", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_LH4_14", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE4A1_14", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_WW2A0_14", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_NW4A1_14", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_LH12_14", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_NE4C2_14", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW4C3_14", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_LH8_14", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_EE2A0_14", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW2A1_14", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_NE2A1_14", + "INT_FEEDTHRU_2_NE2A1" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH3_4", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH4_4", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH12_4", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH11_4", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH9_4", + "VBRK_LH9" + ], + [ + "CMT_TOP_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH1_4", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_MONITOR_N_4", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_LH10_4", + "VBRK_LH10" + ], + [ + "CMT_TOP_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH2_4", + "VBRK_LH2" + ], + [ + "CMT_TOP_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_MONITOR_P_4", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_LH8_4", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH7_4", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_4", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH6_4", + "VBRK_LH6" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "BRKH_INT_SW6D0", + "SW6D0" + ], + [ + "BRKH_INT_NN6B3", + "NN6B3" + ], + [ + "BRKH_INT_NW6A1", + "NW6A1" + ], + [ + "BRKH_INT_SW2A3", + "SW2A3" + ], + [ + "BRKH_INT_SE6D0", + "SE6D0" + ], + [ + "BRKH_INT_WW4END_S0_0", + "WW4END_S0_0" + ], + [ + "BRKH_INT_NN6E1", + "NN6E1" + ], + [ + "BRKH_INT_LVB_L6", + "LVB_L5" + ], + [ + "BRKH_INT_NR1BEG1", + "NR1BEG1" + ], + [ + "BRKH_INT_L_LV7", + "LV_L7" + ], + [ + "BRKH_INT_NL1BEG1", + "NL1BEG1" + ], + [ + "BRKH_INT_SS2END_N0_3", + "SS2END3" + ], + [ + "BRKH_INT_BYP_BOUNCE7", + "BYP_BOUNCE7" + ], + [ + "BRKH_INT_SS2A3", + "SS2A3" + ], + [ + "BRKH_INT_SR1END_N3_3", + "SR1END3" + ], + [ + "BRKH_INT_SS6C1", + "SS6C1" + ], + [ + "BRKH_INT_LVB_L8", + "LVB_L7" + ], + [ + "BRKH_INT_WR1END_S1_0", + "WR1END_S1_0" + ], + [ + "BRKH_INT_SW6B0", + "SW6B0" + ], + [ + "BRKH_INT_SS6D0", + "SS6D0" + ], + [ + "BRKH_INT_NE6C0", + "NE6C0" + ], + [ + "BRKH_INT_NL1BEG0", + "NL1BEG0" + ], + [ + "BRKH_INT_SL1END1", + "SL1END1" + ], + [ + "BRKH_INT_NW6C2", + "NW6C2" + ], + [ + "BRKH_INT_NN2BEG2", + "NN2BEG2" + ], + [ + "BRKH_INT_NE6A0", + "NE6A0" + ], + [ + "BRKH_INT_NW6D3", + "NW6D3" + ], + [ + "BRKH_INT_NE6D3", + "NE6D3" + ], + [ + "BRKH_INT_NN6D0", + "NN6D0" + ], + [ + "BRKH_INT_SE6D2", + "SE6D2" + ], + [ + "BRKH_INT_NN6BEG3", + "NN6BEG3" + ], + [ + "BRKH_INT_SE6E1", + "SE6E1" + ], + [ + "BRKH_INT_SE6B0", + "SE6B0" + ], + [ + "BRKH_INT_NN6C1", + "NN6C1" + ], + [ + "BRKH_INT_L_LV1", + "LV_L1" + ], + [ + "BRKH_INT_NN6A1", + "NN6A1" + ], + [ + "BRKH_INT_SW6B1", + "SW6B1" + ], + [ + "BRKH_INT_L_LV5", + "LV_L5" + ], + [ + "BRKH_INT_SS6A3", + "SS6A3" + ], + [ + "BRKH_INT_SE6E3", + "SE6E3" + ], + [ + "BRKH_INT_SE6B1", + "SE6B1" + ], + [ + "BRKH_INT_L_LV14", + "LV_L14" + ], + [ + "BRKH_INT_LVB_L7", + "LVB_L6" + ], + [ + "BRKH_INT_NW6B3", + "NW6B3" + ], + [ + "BRKH_INT_NN6E3", + "NN6E3" + ], + [ + "BRKH_INT_SE6C1", + "SE6C1" + ], + [ + "BRKH_INT_NW6C1", + "NW6C1" + ], + [ + "BRKH_INT_SL1END3", + "SL1END3" + ], + [ + "BRKH_INT_NW6C3", + "NW6C3" + ], + [ + "BRKH_INT_SS6A0", + "SS6A0" + ], + [ + "BRKH_INT_SS2A2", + "SS2A2" + ], + [ + "BRKH_INT_SE6B2", + "SE6B2" + ], + [ + "BRKH_INT_NE6D0", + "NE6D0" + ], + [ + "BRKH_INT_NN6END_S1_0", + "NN6END_S1_0" + ], + [ + "BRKH_INT_NN6A3", + "NN6A3" + ], + [ + "BRKH_INT_NE6B3", + "NE6B3" + ], + [ + "BRKH_INT_SR1END1", + "SR1END1" + ], + [ + "BRKH_INT_NN6BEG0", + "NN6BEG0" + ], + [ + "BRKH_INT_SW6C1", + "SW6C1" + ], + [ + "BRKH_INT_SE6D1", + "SE6D1" + ], + [ + "BRKH_INT_SS6D1", + "SS6D1" + ], + [ + "BRKH_INT_NW6A2", + "NW6A2" + ], + [ + "BRKH_INT_SW6B2", + "SW6B2" + ], + [ + "BRKH_INT_NW2BEG3", + "NW2BEG3" + ], + [ + "BRKH_INT_L_LV11", + "LV_L11" + ], + [ + "BRKH_INT_L_LV4", + "LV_L4" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_6", + "FAN_BOUNCE_S3_6" + ], + [ + "BRKH_INT_LVB_L2", + "LVB_L1" + ], + [ + "BRKH_INT_L_LV15", + "LV_L15" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_4", + "FAN_BOUNCE_S3_4" + ], + [ + "BRKH_INT_SS6END_N0_3", + "SS6END3" + ], + [ + "BRKH_INT_SE6C3", + "SE6C3" + ], + [ + "BRKH_INT_SE6C2", + "SE6C2" + ], + [ + "BRKH_INT_WR1BEG_S0", + "WR1BEG_S0" + ], + [ + "BRKH_INT_SW6D2", + "SW6D2" + ], + [ + "BRKH_INT_SS6END3", + "SS6END3" + ], + [ + "BRKH_INT_NN6B0", + "NN6B0" + ], + [ + "BRKH_INT_NW6D2", + "NW6D2" + ], + [ + "BRKH_INT_ER1BEG_S0", + "ER1BEG_S0" + ], + [ + "BRKH_INT_SW6E3", + "SW6E3" + ], + [ + "BRKH_INT_SS6B1", + "SS6B1" + ], + [ + "BRKH_INT_L_LV6", + "LV_L6" + ], + [ + "BRKH_INT_LVB_L12", + "LVB_L11" + ], + [ + "BRKH_INT_NE2BEG0", + "NE2BEG0" + ], + [ + "BRKH_INT_NW6A3", + "NW6A3" + ], + [ + "BRKH_INT_LVB_L11", + "LVB_L10" + ], + [ + "BRKH_INT_L_LV3", + "LV_L3" + ], + [ + "BRKH_INT_SS2A1", + "SS2A1" + ], + [ + "BRKH_INT_SW6C0", + "SW6C0" + ], + [ + "BRKH_INT_SE2A3", + "SE2A3" + ], + [ + "BRKH_INT_NN2A2", + "NN2A2" + ], + [ + "BRKH_INT_NN6A0", + "NN6A0" + ], + [ + "BRKH_INT_SW6D3", + "SW6D3" + ], + [ + "BRKH_INT_NE6A3", + "NE6A3" + ], + [ + "BRKH_INT_NE2BEG3", + "NE2BEG3" + ], + [ + "BRKH_INT_NE6B2", + "NE6B2" + ], + [ + "BRKH_INT_NN6E2", + "NN6E2" + ], + [ + "BRKH_INT_BYP_BOUNCE3", + "BYP_BOUNCE3" + ], + [ + "BRKH_INT_LVB_L9", + "LVB_L8" + ], + [ + "BRKH_INT_NE6B1", + "NE6B1" + ], + [ + "BRKH_INT_SS6END1", + "SS6END1" + ], + [ + "BRKH_INT_L_LV12", + "LV_L12" + ], + [ + "BRKH_INT_NN2BEG1", + "NN2BEG1" + ], + [ + "BRKH_INT_NW6B0", + "NW6B0" + ], + [ + "BRKH_INT_SE6C0", + "SE6C0" + ], + [ + "BRKH_INT_NW6B2", + "NW6B2" + ], + [ + "BRKH_INT_SS6E1", + "SS6E1" + ], + [ + "BRKH_INT_NW2END_S0_0", + "NW2END_S0_0" + ], + [ + "BRKH_INT_NW6A0", + "NW6A0" + ], + [ + "BRKH_INT_NN6D1", + "NN6D1" + ], + [ + "BRKH_INT_NN6BEG1", + "NN6BEG1" + ], + [ + "BRKH_INT_SE2A2", + "SE2A2" + ], + [ + "BRKH_INT_L_LV2", + "LV_L2" + ], + [ + "BRKH_INT_SL1END2", + "SL1END2" + ], + [ + "BRKH_INT_SR1END2", + "SR1END2" + ], + [ + "BRKH_INT_NW2BEG1", + "NW2BEG1" + ], + [ + "BRKH_INT_NE6C2", + "NE6C2" + ], + [ + "BRKH_INT_L_LV16", + "LV_L16" + ], + [ + "BRKH_INT_WL1BEG3", + "WL1BEG3" + ], + [ + "BRKH_INT_NW6D1", + "NW6D1" + ], + [ + "BRKH_INT_L_LV0", + "LV_L0" + ], + [ + "BRKH_INT_NL1BEG2", + "NL1BEG2" + ], + [ + "BRKH_INT_SE6E0", + "SE6E0" + ], + [ + "BRKH_INT_SS6B0", + "SS6B0" + ], + [ + "BRKH_INT_NN2A1", + "NN2A1" + ], + [ + "BRKH_INT_SW6E0", + "SW6E0" + ], + [ + "BRKH_INT_SW2END3", + "SW2END3" + ], + [ + "BRKH_INT_SW6C2", + "SW6C2" + ], + [ + "BRKH_INT_SS6A1", + "SS6A1" + ], + [ + "BRKH_INT_NN2END_S2_0", + "NN2END_S2_0" + ], + [ + "BRKH_INT_SS6E3", + "SS6E3" + ], + [ + "BRKH_INT_SR1END3", + "SR1END3" + ], + [ + "BRKH_INT_SW6E1", + "SW6E1" + ], + [ + "BRKH_INT_SE6B3", + "SE6B3" + ], + [ + "BRKH_INT_L_LV17", + "LV_L17" + ], + [ + "BRKH_INT_SW6C3", + "SW6C3" + ], + [ + "BRKH_INT_NN6BEG2", + "NN6BEG2" + ], + [ + "BRKH_INT_NE6A2", + "NE6A2" + ], + [ + "BRKH_INT_NN2A3", + "NN2A3" + ], + [ + "BRKH_INT_NR1BEG0", + "NR1BEG0" + ], + [ + "BRKH_INT_NL1END_S3_0", + "NL1END_S3_0" + ], + [ + "BRKH_INT_SW6E2", + "SW6E2" + ], + [ + "BRKH_INT_SS2END2", + "SS2END2" + ], + [ + "BRKH_INT_LVB_L1", + "LVB_L0" + ], + [ + "BRKH_INT_SW2A1", + "SW2A1" + ], + [ + "BRKH_INT_SW2A0", + "SW2A0" + ], + [ + "BRKH_INT_NE2BEG1", + "NE2BEG1" + ], + [ + "BRKH_INT_NN6C3", + "NN6C3" + ], + [ + "BRKH_INT_NN6B1", + "NN6B1" + ], + [ + "BRKH_INT_NR1BEG2", + "NR1BEG2" + ], + [ + "BRKH_INT_SS6C2", + "SS6C2" + ], + [ + "BRKH_INT_NW2BEG2", + "NW2BEG2" + ], + [ + "BRKH_INT_SW2A2", + "SW2A2" + ], + [ + "BRKH_INT_NN2A0", + "NN2A0" + ], + [ + "BRKH_INT_EL1END_S3_0", + "EL1END_S3_0" + ], + [ + "BRKH_INT_NN6D2", + "NN6D2" + ], + [ + "BRKH_INT_SS6C0", + "SS6C0" + ], + [ + "BRKH_INT_NW6D0", + "NW6D0" + ], + [ + "BRKH_INT_L_LV8", + "LV_L8" + ], + [ + "BRKH_INT_LVB_L5", + "LVB_L4" + ], + [ + "BRKH_INT_SS6B3", + "SS6B3" + ], + [ + "BRKH_INT_NN6D3", + "NN6D3" + ], + [ + "BRKH_INT_NE6C1", + "NE6C1" + ], + [ + "BRKH_INT_SS2END1", + "SS2END1" + ], + [ + "BRKH_INT_SW6B3", + "SW6B3" + ], + [ + "BRKH_INT_SS6D2", + "SS6D2" + ], + [ + "BRKH_INT_SS6E2", + "SS6E2" + ], + [ + "BRKH_INT_NN6A2", + "NN6A2" + ], + [ + "BRKH_INT_LVB_L10", + "LVB_L9" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_2", + "FAN_BOUNCE_S3_2" + ], + [ + "BRKH_INT_ER1END3", + "ER1END3" + ], + [ + "BRKH_INT_WL1END3", + "WL1END3" + ], + [ + "BRKH_INT_NE6D1", + "NE6D1" + ], + [ + "BRKH_INT_SW6D1", + "SW6D1" + ], + [ + "BRKH_INT_NN2BEG0", + "NN2BEG0" + ], + [ + "BRKH_INT_SS6D3", + "SS6D3" + ], + [ + "BRKH_INT_WW2END3", + "WW2END3" + ], + [ + "BRKH_INT_NE2BEG2", + "NE2BEG2" + ], + [ + "BRKH_INT_SE2A1", + "SE2A1" + ], + [ + "BRKH_INT_SW6END3", + "SW6END3" + ], + [ + "BRKH_INT_NE6B0", + "NE6B0" + ], + [ + "BRKH_INT_NW2BEG0", + "NW2BEG0" + ], + [ + "BRKH_INT_NW6END_S0_0", + "NW6END_S0_0" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_0", + "FAN_BOUNCE_S3_0" + ], + [ + "BRKH_INT_SS6A2", + "SS6A2" + ], + [ + "BRKH_INT_SE2A0", + "SE2A0" + ], + [ + "BRKH_INT_SS2END0", + "SS2END0" + ], + [ + "BRKH_INT_NE6A1", + "NE6A1" + ], + [ + "BRKH_INT_LVB_L3", + "LVB_L2" + ], + [ + "BRKH_INT_NN2BEG3", + "NN2BEG3" + ], + [ + "BRKH_INT_NE6C3", + "NE6C3" + ], + [ + "BRKH_INT_SS2A0", + "SS2A0" + ], + [ + "BRKH_INT_L_LV10", + "LV_L10" + ], + [ + "BRKH_INT_NN6C0", + "NN6C0" + ], + [ + "BRKH_INT_NN6C2", + "NN6C2" + ], + [ + "BRKH_INT_NN6E0", + "NN6E0" + ], + [ + "BRKH_INT_NR1BEG3", + "NR1BEG3" + ], + [ + "BRKH_INT_SE6E2", + "SE6E2" + ], + [ + "BRKH_INT_BYP_BOUNCE2", + "BYP_BOUNCE2" + ], + [ + "BRKH_INT_NW6C0", + "NW6C0" + ], + [ + "BRKH_INT_SS2END3", + "SS2END3" + ], + [ + "BRKH_INT_NE6D2", + "NE6D2" + ], + [ + "BRKH_INT_SS6END0", + "SS6END0" + ], + [ + "BRKH_INT_EL1BEG3", + "EL1BEG3" + ], + [ + "BRKH_INT_SS6C3", + "SS6C3" + ], + [ + "BRKH_INT_NN6B2", + "NN6B2" + ], + [ + "BRKH_INT_NW6B1", + "NW6B1" + ], + [ + "BRKH_INT_SS6END2", + "SS6END2" + ], + [ + "BRKH_INT_L_LV13", + "LV_L13" + ], + [ + "BRKH_INT_SS6E0", + "SS6E0" + ], + [ + "BRKH_INT_NE2END_S3_0", + "NE2END_S3_0" + ], + [ + "BRKH_INT_LVB_L4", + "LVB_L3" + ], + [ + "BRKH_INT_BYP_BOUNCE6", + "BYP_BOUNCE6" + ], + [ + "BRKH_INT_SS6B2", + "SS6B2" + ], + [ + "BRKH_INT_SL1END0", + "SL1END0" + ], + [ + "BRKH_INT_SE6D3", + "SE6D3" + ], + [ + "BRKH_INT_L_LV9", + "LV_L9" + ] + ], + "tile_types": [ + "BRKH_INT", + "INT_L" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_IN2", + "HCLK_VFRAME_CK_IN2" + ], + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VFRAME_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VFRAME_CK_IN10" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VFRAME_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VFRAME_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VFRAME_CK_IN7" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VFRAME_CK_IN5" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VFRAME_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VFRAME_CK_IN11" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_VFRAME_CK_IN13" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VFRAME_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VFRAME_CK_IN4" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VFRAME_CK_IN9" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VFRAME_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VFRAME_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VFRAME_CK_IN0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VFRAME_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VFRAME_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VFRAME_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VFRAME_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VFRAME_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VFRAME_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VFRAME_CK_IN12" + ] + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + -5 + ], + "wire_pairs": [ + [ + "MONITOR_IMUX46_5", + "VFRAME_IMUX46" + ], + [ + "MONITOR_FAN5_5", + "VFRAME_FAN5" + ], + [ + "MONITOR_SW4A1_5", + "VFRAME_SW4A1" + ], + [ + "MONITOR_WW4C2_5", + "VFRAME_WW4C2" + ], + [ + "MONITOR_IMUX31_5", + "VFRAME_IMUX31" + ], + [ + "MONITOR_IMUX26_5", + "VFRAME_IMUX26" + ], + [ + "MONITOR_EE4BEG1_5", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_ER1BEG3_5", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_WR1END1_5", + "VFRAME_WR1END1" + ], + [ + "MONITOR_NW2A2_5", + "VFRAME_NW2A2" + ], + [ + "MONITOR_EE4A1_5", + "VFRAME_EE4A1" + ], + [ + "MONITOR_SE2A3_5", + "VFRAME_SE2A3" + ], + [ + "MONITOR_EL1BEG3_5", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_CLK1_5", + "VFRAME_CLK1" + ], + [ + "MONITOR_WW4C0_5", + "VFRAME_WW4C0" + ], + [ + "MONITOR_BYP3_5", + "VFRAME_BYP3" + ], + [ + "MONITOR_EE4B3_5", + "VFRAME_EE4B3" + ], + [ + "MONITOR_NW4A1_5", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WW2END2_5", + "VFRAME_WW2END2" + ], + [ + "MONITOR_IMUX15_5", + "VFRAME_IMUX15" + ], + [ + "MONITOR_NW4A3_5", + "VFRAME_NW4A3" + ], + [ + "MONITOR_EE4B2_5", + "VFRAME_EE4B2" + ], + [ + "MONITOR_IMUX30_5", + "VFRAME_IMUX30" + ], + [ + "MONITOR_WW2A1_5", + "VFRAME_WW2A1" + ], + [ + "MONITOR_SE2A0_5", + "VFRAME_SE2A0" + ], + [ + "MONITOR_IMUX38_5", + "VFRAME_IMUX38" + ], + [ + "MONITOR_BYP1_5", + "VFRAME_BYP1" + ], + [ + "MONITOR_FAN6_5", + "VFRAME_FAN6" + ], + [ + "MONITOR_IMUX24_5", + "VFRAME_IMUX24" + ], + [ + "MONITOR_SW4A0_5", + "VFRAME_SW4A0" + ], + [ + "MONITOR_CLK0_5", + "VFRAME_CLK0" + ], + [ + "MONITOR_IMUX8_5", + "VFRAME_IMUX8" + ], + [ + "MONITOR_SW4END2_5", + "VFRAME_SW4END2" + ], + [ + "MONITOR_LH8_5", + "VFRAME_LH8" + ], + [ + "MONITOR_SE4C3_5", + "VFRAME_SE4C3" + ], + [ + "MONITOR_LH11_5", + "VFRAME_LH11" + ], + [ + "MONITOR_EE4A3_5", + "VFRAME_EE4A3" + ], + [ + "MONITOR_NW4END3_5", + "VFRAME_NW4END3" + ], + [ + "MONITOR_IMUX18_5", + "VFRAME_IMUX18" + ], + [ + "MONITOR_NE4BEG3_5", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_NE4C2_5", + "VFRAME_NE4C2" + ], + [ + "MONITOR_IMUX7_5", + "VFRAME_IMUX7" + ], + [ + "MONITOR_BYP6_5", + "VFRAME_BYP6" + ], + [ + "MONITOR_SE4C2_5", + "VFRAME_SE4C2" + ], + [ + "MONITOR_IMUX16_5", + "VFRAME_IMUX16" + ], + [ + "MONITOR_IMUX41_5", + "VFRAME_IMUX41" + ], + [ + "MONITOR_SW4END1_5", + "VFRAME_SW4END1" + ], + [ + "MONITOR_EE2BEG2_5", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_EE4C0_5", + "VFRAME_EE4C0" + ], + [ + "MONITOR_NE2A0_5", + "VFRAME_NE2A0" + ], + [ + "MONITOR_EL1BEG0_5", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_LH9_5", + "VFRAME_LH9" + ], + [ + "MONITOR_NE2A2_5", + "VFRAME_NE2A2" + ], + [ + "MONITOR_WW4B0_5", + "VFRAME_WW4B0" + ], + [ + "MONITOR_WR1END3_5", + "VFRAME_WR1END3" + ], + [ + "MONITOR_WW4END1_5", + "VFRAME_WW4END1" + ], + [ + "MONITOR_NW4END0_5", + "VFRAME_NW4END0" + ], + [ + "MONITOR_SE2A1_5", + "VFRAME_SE2A1" + ], + [ + "MONITOR_WW4B2_5", + "VFRAME_WW4B2" + ], + [ + "MONITOR_WW4A1_5", + "VFRAME_WW4A1" + ], + [ + "MONITOR_NW4END1_5", + "VFRAME_NW4END1" + ], + [ + "MONITOR_LH3_5", + "VFRAME_LH3" + ], + [ + "MONITOR_BYP2_5", + "VFRAME_BYP2" + ], + [ + "MONITOR_FAN0_5", + "VFRAME_FAN0" + ], + [ + "MONITOR_WR1END0_5", + "VFRAME_WR1END0" + ], + [ + "MONITOR_IMUX39_5", + "VFRAME_IMUX39" + ], + [ + "MONITOR_FAN3_5", + "VFRAME_FAN3" + ], + [ + "MONITOR_IMUX22_5", + "VFRAME_IMUX22" + ], + [ + "MONITOR_EE2BEG0_5", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_SW4A2_5", + "VFRAME_SW4A2" + ], + [ + "MONITOR_NW4A0_5", + "VFRAME_NW4A0" + ], + [ + "MONITOR_WW4B1_5", + "VFRAME_WW4B1" + ], + [ + "MONITOR_NE4C3_5", + "VFRAME_NE4C3" + ], + [ + "MONITOR_IMUX32_5", + "VFRAME_IMUX32" + ], + [ + "MONITOR_WW4A2_5", + "VFRAME_WW4A2" + ], + [ + "MONITOR_LH4_5", + "VFRAME_LH4" + ], + [ + "MONITOR_ER1BEG1_5", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_EE4C2_5", + "VFRAME_EE4C2" + ], + [ + "MONITOR_BYP0_5", + "VFRAME_BYP0" + ], + [ + "MONITOR_NE4C0_5", + "VFRAME_NE4C0" + ], + [ + "MONITOR_NE2A1_5", + "VFRAME_NE2A1" + ], + [ + "MONITOR_SW4END3_5", + "VFRAME_SW4END3" + ], + [ + "MONITOR_SE4BEG3_5", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_LH5_5", + "VFRAME_LH5" + ], + [ + "MONITOR_FAN7_5", + "VFRAME_FAN7" + ], + [ + "MONITOR_WW4END0_5", + "VFRAME_WW4END0" + ], + [ + "MONITOR_NW2A1_5", + "VFRAME_NW2A1" + ], + [ + "MONITOR_ER1BEG0_5", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_IMUX5_5", + "VFRAME_IMUX5" + ], + [ + "MONITOR_IMUX10_5", + "VFRAME_IMUX10" + ], + [ + "MONITOR_EE2A2_5", + "VFRAME_EE2A2" + ], + [ + "MONITOR_IMUX11_5", + "VFRAME_IMUX11" + ], + [ + "MONITOR_WL1END0_5", + "VFRAME_WL1END0" + ], + [ + "MONITOR_EE4BEG3_5", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_WW2END3_5", + "VFRAME_WW2END3" + ], + [ + "MONITOR_SE2A2_5", + "VFRAME_SE2A2" + ], + [ + "MONITOR_IMUX13_5", + "VFRAME_IMUX13" + ], + [ + "MONITOR_IMUX27_5", + "VFRAME_IMUX27" + ], + [ + "MONITOR_SE4BEG0_5", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_SW2A0_5", + "VFRAME_SW2A0" + ], + [ + "MONITOR_ER1BEG2_5", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_NW4END2_5", + "VFRAME_NW4END2" + ], + [ + "MONITOR_EE2BEG1_5", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_EE2A3_5", + "VFRAME_EE2A3" + ], + [ + "MONITOR_IMUX19_5", + "VFRAME_IMUX19" + ], + [ + "MONITOR_IMUX12_5", + "VFRAME_IMUX12" + ], + [ + "MONITOR_WL1END2_5", + "VFRAME_WL1END2" + ], + [ + "MONITOR_EE4B1_5", + "VFRAME_EE4B1" + ], + [ + "MONITOR_NE4BEG2_5", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_SW2A1_5", + "VFRAME_SW2A1" + ], + [ + "MONITOR_IMUX36_5", + "VFRAME_IMUX36" + ], + [ + "MONITOR_SE4BEG1_5", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_EE4BEG2_5", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_WW2END1_5", + "VFRAME_WW2END1" + ], + [ + "MONITOR_NE4C1_5", + "VFRAME_NE4C1" + ], + [ + "MONITOR_EE4C3_5", + "VFRAME_EE4C3" + ], + [ + "MONITOR_EE4B0_5", + "VFRAME_EE4B0" + ], + [ + "MONITOR_EE4C1_5", + "VFRAME_EE4C1" + ], + [ + "MONITOR_WL1END1_5", + "VFRAME_WL1END1" + ], + [ + "MONITOR_IMUX33_5", + "VFRAME_IMUX33" + ], + [ + "MONITOR_LH12_5", + "VFRAME_LH12" + ], + [ + "MONITOR_WW2A0_5", + "VFRAME_WW2A0" + ], + [ + "MONITOR_SE4C0_5", + "VFRAME_SE4C0" + ], + [ + "MONITOR_WW4END3_5", + "VFRAME_WW4END3" + ], + [ + "MONITOR_WW4C3_5", + "VFRAME_WW4C3" + ], + [ + "MONITOR_EE4A2_5", + "VFRAME_EE4A2" + ], + [ + "MONITOR_NW2A0_5", + "VFRAME_NW2A0" + ], + [ + "MONITOR_IMUX23_5", + "VFRAME_IMUX23" + ], + [ + "MONITOR_FAN2_5", + "VFRAME_FAN2" + ], + [ + "MONITOR_WW2A3_5", + "VFRAME_WW2A3" + ], + [ + "MONITOR_IMUX21_5", + "VFRAME_IMUX21" + ], + [ + "MONITOR_IMUX3_5", + "VFRAME_IMUX3" + ], + [ + "MONITOR_LH6_5", + "VFRAME_LH6" + ], + [ + "MONITOR_LH7_5", + "VFRAME_LH7" + ], + [ + "MONITOR_LH10_5", + "VFRAME_LH10" + ], + [ + "MONITOR_IMUX2_5", + "VFRAME_IMUX2" + ], + [ + "MONITOR_IMUX4_5", + "VFRAME_IMUX4" + ], + [ + "MONITOR_NW4A2_5", + "VFRAME_NW4A2" + ], + [ + "MONITOR_IMUX25_5", + "VFRAME_IMUX25" + ], + [ + "MONITOR_NE4BEG1_5", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_EE4A0_5", + "VFRAME_EE4A0" + ], + [ + "MONITOR_EE2A0_5", + "VFRAME_EE2A0" + ], + [ + "MONITOR_SE4BEG2_5", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_EE4BEG0_5", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_CTRL0_5", + "VFRAME_CTRL0" + ], + [ + "MONITOR_IMUX0_5", + "VFRAME_IMUX0" + ], + [ + "MONITOR_WW2END0_5", + "VFRAME_WW2END0" + ], + [ + "MONITOR_WR1END2_5", + "VFRAME_WR1END2" + ], + [ + "MONITOR_IMUX17_5", + "VFRAME_IMUX17" + ], + [ + "MONITOR_NW2A3_5", + "VFRAME_NW2A3" + ], + [ + "MONITOR_IMUX29_5", + "VFRAME_IMUX29" + ], + [ + "MONITOR_FAN1_5", + "VFRAME_FAN1" + ], + [ + "MONITOR_IMUX47_5", + "VFRAME_IMUX47" + ], + [ + "MONITOR_IMUX20_5", + "VFRAME_IMUX20" + ], + [ + "MONITOR_BYP7_5", + "VFRAME_BYP7" + ], + [ + "MONITOR_BYP5_5", + "VFRAME_BYP5" + ], + [ + "MONITOR_IMUX35_5", + "VFRAME_IMUX35" + ], + [ + "MONITOR_SE4C1_5", + "VFRAME_SE4C1" + ], + [ + "MONITOR_SW4A3_5", + "VFRAME_SW4A3" + ], + [ + "MONITOR_IMUX40_5", + "VFRAME_IMUX40" + ], + [ + "MONITOR_WW4END2_5", + "VFRAME_WW4END2" + ], + [ + "MONITOR_SW2A2_5", + "VFRAME_SW2A2" + ], + [ + "MONITOR_IMUX28_5", + "VFRAME_IMUX28" + ], + [ + "MONITOR_EL1BEG2_5", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_SW2A3_5", + "VFRAME_SW2A3" + ], + [ + "MONITOR_WW4A0_5", + "VFRAME_WW4A0" + ], + [ + "MONITOR_LH2_5", + "VFRAME_LH2" + ], + [ + "MONITOR_IMUX9_5", + "VFRAME_IMUX9" + ], + [ + "MONITOR_WL1END3_5", + "VFRAME_WL1END3" + ], + [ + "MONITOR_WW2A2_5", + "VFRAME_WW2A2" + ], + [ + "MONITOR_IMUX37_5", + "VFRAME_IMUX37" + ], + [ + "MONITOR_IMUX42_5", + "VFRAME_IMUX42" + ], + [ + "MONITOR_EL1BEG1_5", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_IMUX45_5", + "VFRAME_IMUX45" + ], + [ + "MONITOR_IMUX1_5", + "VFRAME_IMUX1" + ], + [ + "MONITOR_IMUX44_5", + "VFRAME_IMUX44" + ], + [ + "MONITOR_LH1_5", + "VFRAME_LH1" + ], + [ + "MONITOR_EE2A1_5", + "VFRAME_EE2A1" + ], + [ + "MONITOR_SW4END0_5", + "VFRAME_SW4END0" + ], + [ + "MONITOR_IMUX43_5", + "VFRAME_IMUX43" + ], + [ + "MONITOR_CTRL1_5", + "VFRAME_CTRL1" + ], + [ + "MONITOR_WW4C1_5", + "VFRAME_WW4C1" + ], + [ + "MONITOR_FAN4_5", + "VFRAME_FAN4" + ], + [ + "MONITOR_WW4B3_5", + "VFRAME_WW4B3" + ], + [ + "MONITOR_IMUX6_5", + "VFRAME_IMUX6" + ], + [ + "MONITOR_NE2A3_5", + "VFRAME_NE2A3" + ], + [ + "MONITOR_NE4BEG0_5", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_IMUX14_5", + "VFRAME_IMUX14" + ], + [ + "MONITOR_IMUX34_5", + "VFRAME_IMUX34" + ], + [ + "MONITOR_BYP4_5", + "VFRAME_BYP4" + ], + [ + "MONITOR_WW4A3_5", + "VFRAME_WW4A3" + ], + [ + "MONITOR_EE2BEG3_5", + "VFRAME_EE2BEG3" + ] + ], + "tile_types": [ + "MONITOR_MID_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_1_EE4BEG2", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "INT_FEEDTHRU_1_WW2END3", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "INT_FEEDTHRU_1_WW4C3", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "INT_FEEDTHRU_1_EE4BEG0", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "INT_FEEDTHRU_1_NE4BEG1", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "INT_FEEDTHRU_1_LH3", + "INT_FEEDTHRU_2_LH3" + ], + [ + "INT_FEEDTHRU_1_LH10", + "INT_FEEDTHRU_2_LH10" + ], + [ + "INT_FEEDTHRU_1_ER1BEG1", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "INT_FEEDTHRU_1_NE4BEG3", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "INT_FEEDTHRU_1_NW4END0", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "INT_FEEDTHRU_1_EL1BEG0", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "INT_FEEDTHRU_1_WW4END3", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "INT_FEEDTHRU_1_NE2A2", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "INT_FEEDTHRU_1_EL1BEG3", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "INT_FEEDTHRU_1_SE4BEG1", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "INT_FEEDTHRU_1_SE4C3", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "INT_FEEDTHRU_1_MONITOR_P", + "INT_FEEDTHRU_2_MONITOR_P" + ], + [ + "INT_FEEDTHRU_1_EE4B2", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "INT_FEEDTHRU_1_WW4A3", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "INT_FEEDTHRU_1_WR1END1", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "INT_FEEDTHRU_1_EE4A2", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "INT_FEEDTHRU_1_NE2A0", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "INT_FEEDTHRU_1_EE4A1", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "INT_FEEDTHRU_1_WL1END3", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "INT_FEEDTHRU_1_EE2BEG3", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "INT_FEEDTHRU_1_WW2END1", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "INT_FEEDTHRU_1_ER1BEG2", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "INT_FEEDTHRU_1_WW2A2", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "INT_FEEDTHRU_1_LH8", + "INT_FEEDTHRU_2_LH8" + ], + [ + "INT_FEEDTHRU_1_WR1END2", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "INT_FEEDTHRU_1_EE4C1", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "INT_FEEDTHRU_1_WW4C0", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "INT_FEEDTHRU_1_LH11", + "INT_FEEDTHRU_2_LH11" + ], + [ + "INT_FEEDTHRU_1_LH4", + "INT_FEEDTHRU_2_LH4" + ], + [ + "INT_FEEDTHRU_1_LH9", + "INT_FEEDTHRU_2_LH9" + ], + [ + "INT_FEEDTHRU_1_NE4C1", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "INT_FEEDTHRU_1_NW2A0", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "INT_FEEDTHRU_1_SW4A0", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "INT_FEEDTHRU_1_WL1END2", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "INT_FEEDTHRU_1_EE4BEG3", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "INT_FEEDTHRU_1_SE4C2", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "INT_FEEDTHRU_1_NW2A2", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "INT_FEEDTHRU_1_WW4A1", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "INT_FEEDTHRU_1_NE4BEG0", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "INT_FEEDTHRU_1_EE4C2", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "INT_FEEDTHRU_1_WW4B1", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "INT_FEEDTHRU_1_MONITOR_N", + "INT_FEEDTHRU_2_MONITOR_N" + ], + [ + "INT_FEEDTHRU_1_WW4C1", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "INT_FEEDTHRU_1_LH12", + "INT_FEEDTHRU_2_LH12" + ], + [ + "INT_FEEDTHRU_1_EE2A0", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "INT_FEEDTHRU_1_SE4C1", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "INT_FEEDTHRU_1_EE4A0", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "INT_FEEDTHRU_1_SE2A3", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "INT_FEEDTHRU_1_WW4END2", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "INT_FEEDTHRU_1_SW4A2", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "INT_FEEDTHRU_1_SW2A3", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "INT_FEEDTHRU_1_SW4END1", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "INT_FEEDTHRU_1_SE2A1", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "INT_FEEDTHRU_1_NW4A3", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "INT_FEEDTHRU_1_EE2A2", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "INT_FEEDTHRU_1_WW4B3", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "INT_FEEDTHRU_1_SW4END2", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "INT_FEEDTHRU_1_ER1BEG0", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "INT_FEEDTHRU_1_ER1BEG3", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "INT_FEEDTHRU_1_WW4END0", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "INT_FEEDTHRU_1_EE4C3", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "INT_FEEDTHRU_1_NE2A1", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "INT_FEEDTHRU_1_EE4B1", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "INT_FEEDTHRU_1_WW4A2", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "INT_FEEDTHRU_1_NW4A1", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "INT_FEEDTHRU_1_NW4A0", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "INT_FEEDTHRU_1_EE4B3", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "INT_FEEDTHRU_1_SW4END3", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "INT_FEEDTHRU_1_WW2END2", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "INT_FEEDTHRU_1_WL1END1", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "INT_FEEDTHRU_1_LH7", + "INT_FEEDTHRU_2_LH7" + ], + [ + "INT_FEEDTHRU_1_WW2END0", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "INT_FEEDTHRU_1_SE4BEG2", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "INT_FEEDTHRU_1_SW2A1", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "INT_FEEDTHRU_1_EE2BEG2", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "INT_FEEDTHRU_1_LH6", + "INT_FEEDTHRU_2_LH6" + ], + [ + "INT_FEEDTHRU_1_NW2A1", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "INT_FEEDTHRU_1_SE4BEG3", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "INT_FEEDTHRU_1_WW2A1", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "INT_FEEDTHRU_1_NW4A2", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "INT_FEEDTHRU_1_EE4C0", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "INT_FEEDTHRU_1_NE4C3", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "INT_FEEDTHRU_1_SE2A0", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "INT_FEEDTHRU_1_EE2BEG0", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "INT_FEEDTHRU_1_SE2A2", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "INT_FEEDTHRU_1_SW4A1", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "INT_FEEDTHRU_1_WW4C2", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "INT_FEEDTHRU_1_WW2A0", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "INT_FEEDTHRU_1_WW4B0", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "INT_FEEDTHRU_1_LH1", + "INT_FEEDTHRU_2_LH1" + ], + [ + "INT_FEEDTHRU_1_NW4END3", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "INT_FEEDTHRU_1_WW4A0", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "INT_FEEDTHRU_1_NE4C2", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "INT_FEEDTHRU_1_WW4B2", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "INT_FEEDTHRU_1_NW4END1", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "INT_FEEDTHRU_1_NW2A3", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "INT_FEEDTHRU_1_SE4C0", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "INT_FEEDTHRU_1_EE2A1", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "INT_FEEDTHRU_1_WR1END0", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "INT_FEEDTHRU_1_EL1BEG1", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "INT_FEEDTHRU_1_SE4BEG0", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "INT_FEEDTHRU_1_NE4BEG2", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "INT_FEEDTHRU_1_NW4END2", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "INT_FEEDTHRU_1_EE2A3", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "INT_FEEDTHRU_1_EE4A3", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "INT_FEEDTHRU_1_WR1END3", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "INT_FEEDTHRU_1_EE4B0", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "INT_FEEDTHRU_1_SW4A3", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "INT_FEEDTHRU_1_WW4END1", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "INT_FEEDTHRU_1_WL1END0", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "INT_FEEDTHRU_1_SW2A0", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "INT_FEEDTHRU_1_LH2", + "INT_FEEDTHRU_2_LH2" + ], + [ + "INT_FEEDTHRU_1_LH5", + "INT_FEEDTHRU_2_LH5" + ], + [ + "INT_FEEDTHRU_1_EL1BEG2", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "INT_FEEDTHRU_1_WW2A3", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "INT_FEEDTHRU_1_EE4BEG1", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "INT_FEEDTHRU_1_NE2A3", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "INT_FEEDTHRU_1_SW4END0", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "INT_FEEDTHRU_1_SW2A2", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "INT_FEEDTHRU_1_NE4C0", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "INT_FEEDTHRU_1_EE2BEG1", + "INT_FEEDTHRU_2_EE2BEG1" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_1", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CMT_FIFO_WW4B0_3", + "CMT_TOP_WW4B0_4" + ], + [ + "CMT_FIFO_ER1BEG2_7", + "CMT_TOP_ER1BEG2_8" + ], + [ + "CMT_FIFO_L_IMUX36_7", + "CMT_TOP_IMUX36_8" + ], + [ + "CMT_FIFO_EL1BEG0_0", + "CMT_TOP_EL1BEG0_1" + ], + [ + "CMT_FIFO_SE4BEG2_0", + "CMT_TOP_SE4BEG2_1" + ], + [ + "CMT_FIFO_L_CTRL1_3", + "CMT_TOP_CTRL1_4" + ], + [ + "CMT_FIFO_EE2A0_7", + "CMT_TOP_EE2A0_8" + ], + [ + "CMT_FIFO_L_IMUX3_4", + "CMT_TOP_IMUX3_5" + ], + [ + "CMT_FIFO_L_FAN1_10", + "CMT_TOP_FAN1_11" + ], + [ + "CMT_FIFO_NW4END3_5", + "CMT_TOP_NW4END3_6" + ], + [ + "CMT_FIFO_LH2_0", + "CMT_TOP_LH2_1" + ], + [ + "CMT_FIFO_L_IMUX22_0", + "CMT_TOP_IMUX22_1" + ], + [ + "CMT_FIFO_L_IMUX44_8", + "CMT_TOP_IMUX44_9" + ], + [ + "CMT_FIFO_L_IMUX42_11", + "CMT_TOP_IMUX42_12" + ], + [ + "CMT_FIFO_EE2A0_0", + "CMT_TOP_EE2A0_1" + ], + [ + "CMT_FIFO_LH7_11", + "CMT_TOP_LH7_12" + ], + [ + "CMT_FIFO_SW4A3_10", + "CMT_TOP_SW4A3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_1", + "CMT_TOP_LOGIC_OUTS_L_B5_2" + ], + [ + "CMT_FIFO_WW4A3_1", + "CMT_TOP_WW4A3_2" + ], + [ + "CMT_FIFO_WR1END2_0", + "CMT_TOP_WR1END2_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "CMT_TOP_ICLKDIV_3" + ], + [ + "CMT_FIFO_EE2BEG2_4", + "CMT_TOP_EE2BEG2_5" + ], + [ + "CMT_FIFO_WW2END0_6", + "CMT_TOP_WW2END0_7" + ], + [ + "CMT_FIFO_SE2A3_3", + "CMT_TOP_SE2A3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_1", + "CMT_TOP_LOGIC_OUTS_L_B0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_2", + "CMT_TOP_LOGIC_OUTS_L_B22_3" + ], + [ + "CMT_FIFO_SW4END2_7", + "CMT_TOP_SW4END2_8" + ], + [ + "CMT_FIFO_MONITOR_N_4", + "CMT_TOP_MONITOR_N_5" + ], + [ + "CMT_FIFO_SE2A3_7", + "CMT_TOP_SE2A3_8" + ], + [ + "CMT_FIFO_NW2A0_7", + "CMT_TOP_NW2A0_8" + ], + [ + "CMT_FIFO_L_IMUX6_4", + "CMT_TOP_IMUX6_5" + ], + [ + "CMT_FIFO_LH3_5", + "CMT_TOP_LH3_6" + ], + [ + "CMT_FIFO_L_CTRL0_10", + "CMT_TOP_CTRL0_11" + ], + [ + "CMT_FIFO_SW4END1_1", + "CMT_TOP_SW4END1_2" + ], + [ + "CMT_FIFO_L_CTRL0_5", + "CMT_TOP_CTRL0_6" + ], + [ + "CMT_FIFO_WW2A3_4", + "CMT_TOP_WW2A3_5" + ], + [ + "CMT_FIFO_L_IMUX37_5", + "CMT_TOP_IMUX37_6" + ], + [ + "CMT_FIFO_NW2A2_4", + "CMT_TOP_NW2A2_5" + ], + [ + "CMT_FIFO_L_IMUX45_4", + "CMT_TOP_IMUX45_5" + ], + [ + "CMT_FIFO_LH7_0", + "CMT_TOP_LH7_1" + ], + [ + "CMT_FIFO_LH9_1", + "CMT_TOP_LH9_2" + ], + [ + "CMT_FIFO_SW4END1_3", + "CMT_TOP_SW4END1_4" + ], + [ + "CMT_FIFO_EL1BEG1_2", + "CMT_TOP_EL1BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX38_11", + "CMT_TOP_IMUX38_12" + ], + [ + "CMT_FIFO_SE2A0_9", + "CMT_TOP_SE2A0_10" + ], + [ + "CMT_FIFO_EE4C0_5", + "CMT_TOP_EE4C0_6" + ], + [ + "CMT_FIFO_WW4A2_8", + "CMT_TOP_WW4A2_9" + ], + [ + "CMT_FIFO_WW4C3_0", + "CMT_TOP_WW4C3_1" + ], + [ + "CMT_FIFO_LH12_10", + "CMT_TOP_LH12_11" + ], + [ + "CMT_FIFO_L_IMUX15_1", + "CMT_TOP_IMUX15_2" + ], + [ + "CMT_FIFO_EL1BEG1_11", + "CMT_TOP_EL1BEG1_12" + ], + [ + "CMT_FIFO_L_IMUX46_4", + "CMT_TOP_IMUX46_5" + ], + [ + "CMT_FIFO_NW4A1_11", + "CMT_TOP_NW4A1_12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "CMT_TOP_OCLK_6" + ], + [ + "CMT_FIFO_LH11_7", + "CMT_TOP_LH11_8" + ], + [ + "CMT_FIFO_L_FAN6_3", + "CMT_TOP_FAN6_4" + ], + [ + "CMT_FIFO_EE4BEG0_7", + "CMT_TOP_EE4BEG0_8" + ], + [ + "CMT_FIFO_SE4C2_2", + "CMT_TOP_SE4C2_3" + ], + [ + "CMT_FIFO_EE4BEG0_9", + "CMT_TOP_EE4BEG0_10" + ], + [ + "CMT_FIFO_NE2A0_8", + "CMT_TOP_NE2A0_9" + ], + [ + "CMT_FIFO_L_IMUX5_6", + "CMT_TOP_IMUX5_7" + ], + [ + "CMT_FIFO_L_IMUX9_10", + "CMT_TOP_IMUX9_11" + ], + [ + "CMT_FIFO_L_IMUX2_3", + "CMT_TOP_IMUX2_4" + ], + [ + "CMT_FIFO_L_IMUX42_1", + "CMT_TOP_IMUX42_2" + ], + [ + "CMT_FIFO_WW2A0_9", + "CMT_TOP_WW2A0_10" + ], + [ + "CMT_FIFO_SE2A1_1", + "CMT_TOP_SE2A1_2" + ], + [ + "CMT_FIFO_WL1END2_4", + "CMT_TOP_WL1END2_5" + ], + [ + "CMT_FIFO_MONITOR_P_10", + "CMT_TOP_MONITOR_P_11" + ], + [ + "CMT_FIFO_WW4A3_0", + "CMT_TOP_WW4A3_1" + ], + [ + "CMT_FIFO_WL1END2_5", + "CMT_TOP_WL1END2_6" + ], + [ + "CMT_FIFO_L_IMUX3_0", + "CMT_TOP_IMUX3_1" + ], + [ + "CMT_FIFO_EE2A3_6", + "CMT_TOP_EE2A3_7" + ], + [ + "CMT_FIFO_L_FAN0_2", + "CMT_TOP_FAN0_3" + ], + [ + "CMT_FIFO_WW4C2_11", + "CMT_TOP_WW4C2_12" + ], + [ + "CMT_FIFO_NE4BEG1_9", + "CMT_TOP_NE4BEG1_10" + ], + [ + "CMT_FIFO_WW4A1_11", + "CMT_TOP_WW4A1_12" + ], + [ + "CMT_FIFO_EE4BEG1_6", + "CMT_TOP_EE4BEG1_7" + ], + [ + "CMT_FIFO_SE4C0_3", + "CMT_TOP_SE4C0_4" + ], + [ + "CMT_FIFO_L_IMUX31_4", + "CMT_TOP_IMUX31_5" + ], + [ + "CMT_FIFO_EE4BEG3_11", + "CMT_TOP_EE4BEG3_12" + ], + [ + "CMT_FIFO_NE4C2_2", + "CMT_TOP_NE4C2_3" + ], + [ + "CMT_FIFO_EE2A0_2", + "CMT_TOP_EE2A0_3" + ], + [ + "CMT_FIFO_L_IMUX8_1", + "CMT_TOP_IMUX8_2" + ], + [ + "CMT_FIFO_L_IMUX47_8", + "CMT_TOP_IMUX47_9" + ], + [ + "CMT_FIFO_WW2A0_3", + "CMT_TOP_WW2A0_4" + ], + [ + "CMT_FIFO_WW4C1_11", + "CMT_TOP_WW4C1_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_4", + "CMT_TOP_LOGIC_OUTS_L_B21_5" + ], + [ + "CMT_FIFO_L_IMUX14_6", + "CMT_TOP_IMUX14_7" + ], + [ + "CMT_FIFO_WR1END3_4", + "CMT_TOP_WR1END3_5" + ], + [ + "CMT_FIFO_SW2A3_4", + "CMT_TOP_SW2A3_5" + ], + [ + "CMT_FIFO_EE2A3_11", + "CMT_TOP_EE2A3_12" + ], + [ + "CMT_FIFO_SW4END2_2", + "CMT_TOP_SW4END2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_11", + "CMT_TOP_LOGIC_OUTS_L_B20_12" + ], + [ + "CMT_FIFO_L_FAN1_11", + "CMT_TOP_FAN1_12" + ], + [ + "CMT_FIFO_L_IMUX36_9", + "CMT_TOP_IMUX36_10" + ], + [ + "CMT_FIFO_WW4C3_3", + "CMT_TOP_WW4C3_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "CMT_TOP_ICLKDIV_10" + ], + [ + "CMT_FIFO_L_IMUX30_7", + "CMT_TOP_IMUX30_8" + ], + [ + "CMT_FIFO_EE4A3_9", + "CMT_TOP_EE4A3_10" + ], + [ + "CMT_FIFO_L_CLK0_10", + "CMT_TOP_CLK0_11" + ], + [ + "CMT_FIFO_L_IMUX20_1", + "CMT_TOP_IMUX20_2" + ], + [ + "CMT_FIFO_L_IMUX24_11", + "CMT_TOP_IMUX24_12" + ], + [ + "CMT_FIFO_NW4END2_8", + "CMT_TOP_NW4END2_9" + ], + [ + "CMT_FIFO_SW4A2_6", + "CMT_TOP_SW4A2_7" + ], + [ + "CMT_FIFO_WW2END3_3", + "CMT_TOP_WW2END3_4" + ], + [ + "CMT_FIFO_L_IMUX20_4", + "CMT_TOP_IMUX20_5" + ], + [ + "CMT_FIFO_WW4C1_3", + "CMT_TOP_WW4C1_4" + ], + [ + "CMT_FIFO_WW4B0_5", + "CMT_TOP_WW4B0_6" + ], + [ + "CMT_FIFO_L_IMUX28_10", + "CMT_TOP_IMUX28_11" + ], + [ + "CMT_FIFO_WR1END3_7", + "CMT_TOP_WR1END3_8" + ], + [ + "CMT_FIFO_WW4A1_6", + "CMT_TOP_WW4A1_7" + ], + [ + "CMT_FIFO_LH10_7", + "CMT_TOP_LH10_8" + ], + [ + "CMT_FIFO_EE2A2_5", + "CMT_TOP_EE2A2_6" + ], + [ + "CMT_FIFO_L_IMUX19_11", + "CMT_TOP_IMUX19_12" + ], + [ + "CMT_FIFO_L_IMUX3_6", + "CMT_TOP_IMUX3_7" + ], + [ + "CMT_FIFO_NW2A0_1", + "CMT_TOP_NW2A0_2" + ], + [ + "CMT_FIFO_WW4B3_6", + "CMT_TOP_WW4B3_7" + ], + [ + "CMT_FIFO_SW4A2_3", + "CMT_TOP_SW4A2_4" + ], + [ + "CMT_FIFO_NE4C0_5", + "CMT_TOP_NE4C0_6" + ], + [ + "CMT_FIFO_SE2A3_10", + "CMT_TOP_SE2A3_11" + ], + [ + "CMT_FIFO_WL1END3_8", + "CMT_TOP_WL1END3_9" + ], + [ + "CMT_FIFO_EE4BEG3_5", + "CMT_TOP_EE4BEG3_6" + ], + [ + "CMT_FIFO_WL1END0_4", + "CMT_TOP_WL1END0_5" + ], + [ + "CMT_FIFO_L_CLK1_8", + "CMT_TOP_CLK1_9" + ], + [ + "CMT_FIFO_LH6_0", + "CMT_TOP_LH6_1" + ], + [ + "CMT_FIFO_L_IMUX35_2", + "CMT_TOP_IMUX35_3" + ], + [ + "CMT_FIFO_SW4END0_8", + "CMT_TOP_SW4END0_9" + ], + [ + "CMT_FIFO_SE2A0_6", + "CMT_TOP_SE2A0_7" + ], + [ + "CMT_FIFO_L_IMUX33_0", + "CMT_TOP_IMUX33_1" + ], + [ + "CMT_FIFO_LH12_11", + "CMT_TOP_LH12_12" + ], + [ + "CMT_FIFO_WW2END2_10", + "CMT_TOP_WW2END2_11" + ], + [ + "CMT_FIFO_WW4END2_1", + "CMT_TOP_WW4END2_2" + ], + [ + "CMT_FIFO_WR1END1_1", + "CMT_TOP_WR1END1_2" + ], + [ + "CMT_FIFO_L_BYP3_8", + "CMT_TOP_BYP3_9" + ], + [ + "CMT_FIFO_L_IMUX15_11", + "CMT_TOP_IMUX15_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_2", + "CMT_TOP_LOGIC_OUTS_L_B2_3" + ], + [ + "CMT_FIFO_L_CLK0_1", + "CMT_TOP_CLK0_2" + ], + [ + "CMT_FIFO_WW2END0_3", + "CMT_TOP_WW2END0_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "CMT_TOP_OCLKDIV_2" + ], + [ + "CMT_FIFO_L_IMUX6_9", + "CMT_TOP_IMUX6_10" + ], + [ + "CMT_FIFO_L_IMUX36_2", + "CMT_TOP_IMUX36_3" + ], + [ + "CMT_FIFO_NE4C3_11", + "CMT_TOP_NE4C3_12" + ], + [ + "CMT_FIFO_WW4C2_9", + "CMT_TOP_WW4C2_10" + ], + [ + "CMT_FIFO_SW4END3_2", + "CMT_TOP_SW4END3_3" + ], + [ + "CMT_FIFO_LH7_7", + "CMT_TOP_LH7_8" + ], + [ + "CMT_FIFO_L_IMUX25_8", + "CMT_TOP_IMUX25_9" + ], + [ + "CMT_FIFO_EE2A2_2", + "CMT_TOP_EE2A2_3" + ], + [ + "CMT_FIFO_L_BYP4_6", + "CMT_TOP_BYP4_7" + ], + [ + "CMT_FIFO_SW4END1_10", + "CMT_TOP_SW4END1_11" + ], + [ + "CMT_FIFO_SE2A2_7", + "CMT_TOP_SE2A2_8" + ], + [ + "CMT_FIFO_WW4B2_4", + "CMT_TOP_WW4B2_5" + ], + [ + "CMT_FIFO_L_IMUX27_2", + "CMT_TOP_IMUX27_3" + ], + [ + "CMT_FIFO_NE4C1_5", + "CMT_TOP_NE4C1_6" + ], + [ + "CMT_FIFO_L_IMUX43_1", + "CMT_TOP_IMUX43_2" + ], + [ + "CMT_FIFO_LH4_4", + "CMT_TOP_LH4_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "CMT_TOP_ICLKDIV_11" + ], + [ + "CMT_FIFO_EE4BEG2_7", + "CMT_TOP_EE4BEG2_8" + ], + [ + "CMT_FIFO_L_CTRL0_7", + "CMT_TOP_CTRL0_8" + ], + [ + "CMT_FIFO_NW2A3_0", + "CMT_TOP_NW2A3_1" + ], + [ + "CMT_FIFO_EE4BEG1_8", + "CMT_TOP_EE4BEG1_9" + ], + [ + "CMT_FIFO_NW4A0_0", + "CMT_TOP_NW4A0_1" + ], + [ + "CMT_FIFO_EE2A1_6", + "CMT_TOP_EE2A1_7" + ], + [ + "CMT_FIFO_EE2BEG1_5", + "CMT_TOP_EE2BEG1_6" + ], + [ + "CMT_FIFO_L_IMUX33_7", + "CMT_TOP_IMUX33_8" + ], + [ + "CMT_FIFO_WW2END3_2", + "CMT_TOP_WW2END3_3" + ], + [ + "CMT_FIFO_LH5_7", + "CMT_TOP_LH5_8" + ], + [ + "CMT_FIFO_L_FAN2_9", + "CMT_TOP_FAN2_10" + ], + [ + "CMT_FIFO_NE4BEG2_5", + "CMT_TOP_NE4BEG2_6" + ], + [ + "CMT_FIFO_L_IMUX1_4", + "CMT_TOP_IMUX1_5" + ], + [ + "CMT_FIFO_SE4BEG3_2", + "CMT_TOP_SE4BEG3_3" + ], + [ + "CMT_FIFO_NW4END2_11", + "CMT_TOP_NW4END2_12" + ], + [ + "CMT_FIFO_SW4END0_11", + "CMT_TOP_SW4END0_12" + ], + [ + "CMT_FIFO_L_IMUX38_7", + "CMT_TOP_IMUX38_8" + ], + [ + "CMT_FIFO_WW2END3_8", + "CMT_TOP_WW2END3_9" + ], + [ + "CMT_FIFO_SW4END1_8", + "CMT_TOP_SW4END1_9" + ], + [ + "CMT_FIFO_SW4A1_0", + "CMT_TOP_SW4A1_1" + ], + [ + "CMT_FIFO_NW4END2_9", + "CMT_TOP_NW4END2_10" + ], + [ + "CMT_FIFO_EE2BEG1_11", + "CMT_TOP_EE2BEG1_12" + ], + [ + "CMT_FIFO_L_IMUX37_1", + "CMT_TOP_IMUX37_2" + ], + [ + "CMT_FIFO_SW2A1_9", + "CMT_TOP_SW2A1_10" + ], + [ + "CMT_FIFO_L_IMUX17_9", + "CMT_TOP_IMUX17_10" + ], + [ + "CMT_FIFO_L_IMUX23_8", + "CMT_TOP_IMUX23_9" + ], + [ + "CMT_FIFO_SW4END3_8", + "CMT_TOP_SW4END3_9" + ], + [ + "CMT_FIFO_L_IMUX30_3", + "CMT_TOP_IMUX30_4" + ], + [ + "CMT_FIFO_WW2END2_4", + "CMT_TOP_WW2END2_5" + ], + [ + "CMT_FIFO_LH10_4", + "CMT_TOP_LH10_5" + ], + [ + "CMT_FIFO_L_IMUX23_7", + "CMT_TOP_IMUX23_8" + ], + [ + "CMT_FIFO_L_IMUX9_9", + "CMT_TOP_IMUX9_10" + ], + [ + "CMT_FIFO_SE2A1_3", + "CMT_TOP_SE2A1_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "CMT_TOP_ICLKDIV_8" + ], + [ + "CMT_FIFO_NW2A3_2", + "CMT_TOP_NW2A3_3" + ], + [ + "CMT_FIFO_L_IMUX43_6", + "CMT_TOP_IMUX43_7" + ], + [ + "CMT_FIFO_L_CTRL1_4", + "CMT_TOP_CTRL1_5" + ], + [ + "CMT_FIFO_WW2END2_0", + "CMT_TOP_WW2END2_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_2", + "CMT_TOP_LOGIC_OUTS_L_B8_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_6", + "CMT_TOP_LOGIC_OUTS_L_B23_7" + ], + [ + "CMT_FIFO_NE4BEG1_4", + "CMT_TOP_NE4BEG1_5" + ], + [ + "CMT_FIFO_WL1END1_1", + "CMT_TOP_WL1END1_2" + ], + [ + "CMT_FIFO_L_IMUX38_1", + "CMT_TOP_IMUX38_2" + ], + [ + "CMT_FIFO_EE4B1_10", + "CMT_TOP_EE4B1_11" + ], + [ + "CMT_FIFO_L_IMUX46_11", + "CMT_TOP_IMUX46_12" + ], + [ + "CMT_FIFO_L_BYP2_10", + "CMT_TOP_BYP2_11" + ], + [ + "CMT_FIFO_NE4C3_10", + "CMT_TOP_NE4C3_11" + ], + [ + "CMT_FIFO_WW2END3_1", + "CMT_TOP_WW2END3_2" + ], + [ + "CMT_FIFO_L_IMUX30_0", + "CMT_TOP_IMUX30_1" + ], + [ + "CMT_FIFO_WR1END0_6", + "CMT_TOP_WR1END0_7" + ], + [ + "CMT_FIFO_L_IMUX27_9", + "CMT_TOP_IMUX27_10" + ], + [ + "CMT_FIFO_EL1BEG3_8", + "CMT_TOP_EL1BEG3_9" + ], + [ + "CMT_FIFO_WW4END0_5", + "CMT_TOP_WW4END0_6" + ], + [ + "CMT_FIFO_L_FAN3_8", + "CMT_TOP_FAN3_9" + ], + [ + "CMT_FIFO_WW4END1_0", + "CMT_TOP_WW4END1_1" + ], + [ + "CMT_FIFO_L_IMUX37_10", + "CMT_TOP_IMUX37_11" + ], + [ + "CMT_FIFO_SE4BEG2_1", + "CMT_TOP_SE4BEG2_2" + ], + [ + "CMT_FIFO_L_BYP3_10", + "CMT_TOP_BYP3_11" + ], + [ + "CMT_FIFO_LH4_7", + "CMT_TOP_LH4_8" + ], + [ + "CMT_FIFO_L_IMUX35_9", + "CMT_TOP_IMUX35_10" + ], + [ + "CMT_FIFO_L_CLK0_2", + "CMT_TOP_CLK0_3" + ], + [ + "CMT_FIFO_L_IMUX8_6", + "CMT_TOP_IMUX8_7" + ], + [ + "CMT_FIFO_SE4C2_9", + "CMT_TOP_SE4C2_10" + ], + [ + "CMT_FIFO_NW4A1_5", + "CMT_TOP_NW4A1_6" + ], + [ + "CMT_FIFO_L_IMUX33_5", + "CMT_TOP_IMUX33_6" + ], + [ + "CMT_FIFO_SW2A0_0", + "CMT_TOP_SW2A0_1" + ], + [ + "CMT_FIFO_WW2END0_11", + "CMT_TOP_WW2END0_12" + ], + [ + "CMT_FIFO_L_BYP4_3", + "CMT_TOP_BYP4_4" + ], + [ + "CMT_FIFO_LH6_3", + "CMT_TOP_LH6_4" + ], + [ + "CMT_FIFO_WW4C0_8", + "CMT_TOP_WW4C0_9" + ], + [ + "CMT_FIFO_WW2A3_8", + "CMT_TOP_WW2A3_9" + ], + [ + "CMT_FIFO_NE4C0_2", + "CMT_TOP_NE4C0_3" + ], + [ + "CMT_FIFO_SE4C1_8", + "CMT_TOP_SE4C1_9" + ], + [ + "CMT_FIFO_SE4BEG0_10", + "CMT_TOP_SE4BEG0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_9", + "CMT_TOP_LOGIC_OUTS_L_B17_10" + ], + [ + "CMT_FIFO_L_FAN5_5", + "CMT_TOP_FAN5_6" + ], + [ + "CMT_FIFO_L_IMUX0_4", + "CMT_TOP_IMUX0_5" + ], + [ + "CMT_FIFO_L_IMUX10_2", + "CMT_TOP_IMUX10_3" + ], + [ + "CMT_FIFO_MONITOR_P_8", + "CMT_TOP_MONITOR_P_9" + ], + [ + "CMT_FIFO_L_FAN7_7", + "CMT_TOP_FAN7_8" + ], + [ + "CMT_FIFO_SE2A1_0", + "CMT_TOP_SE2A1_1" + ], + [ + "CMT_FIFO_SW4END2_10", + "CMT_TOP_SW4END2_11" + ], + [ + "CMT_FIFO_WW4END2_9", + "CMT_TOP_WW4END2_10" + ], + [ + "CMT_FIFO_WW4END1_9", + "CMT_TOP_WW4END1_10" + ], + [ + "CMT_FIFO_EE4BEG2_1", + "CMT_TOP_EE4BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX44_3", + "CMT_TOP_IMUX44_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_10", + "CMT_TOP_LOGIC_OUTS_L_B8_11" + ], + [ + "CMT_FIFO_L_FAN7_0", + "CMT_TOP_FAN7_1" + ], + [ + "CMT_FIFO_EE4B0_6", + "CMT_TOP_EE4B0_7" + ], + [ + "CMT_FIFO_L_IMUX43_3", + "CMT_TOP_IMUX43_4" + ], + [ + "CMT_FIFO_LH6_10", + "CMT_TOP_LH6_11" + ], + [ + "CMT_FIFO_WR1END3_5", + "CMT_TOP_WR1END3_6" + ], + [ + "CMT_FIFO_NE4C0_0", + "CMT_TOP_NE4C0_1" + ], + [ + "CMT_FIFO_L_FAN6_7", + "CMT_TOP_FAN6_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_9", + "CMT_TOP_LOGIC_OUTS_L_B0_10" + ], + [ + "CMT_FIFO_L_IMUX37_8", + "CMT_TOP_IMUX37_9" + ], + [ + "CMT_FIFO_L_IMUX29_4", + "CMT_TOP_IMUX29_5" + ], + [ + "CMT_FIFO_SW2A1_5", + "CMT_TOP_SW2A1_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "CMT_TOP_OCLK_8" + ], + [ + "CMT_FIFO_ER1BEG0_5", + "CMT_TOP_ER1BEG0_6" + ], + [ + "CMT_FIFO_L_IMUX30_9", + "CMT_TOP_IMUX30_10" + ], + [ + "CMT_FIFO_SE2A2_8", + "CMT_TOP_SE2A2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_10", + "CMT_TOP_LOGIC_OUTS_L_B13_11" + ], + [ + "CMT_FIFO_L_IMUX40_1", + "CMT_TOP_IMUX40_2" + ], + [ + "CMT_FIFO_WW2END0_0", + "CMT_TOP_WW2END0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_4", + "CMT_TOP_LOGIC_OUTS_L_B22_5" + ], + [ + "CMT_FIFO_L_BYP0_0", + "CMT_TOP_BYP0_1" + ], + [ + "CMT_FIFO_EL1BEG2_9", + "CMT_TOP_EL1BEG2_10" + ], + [ + "CMT_FIFO_NE4BEG2_0", + "CMT_TOP_NE4BEG2_1" + ], + [ + "CMT_FIFO_L_CLK0_6", + "CMT_TOP_CLK0_7" + ], + [ + "CMT_FIFO_WW2A3_7", + "CMT_TOP_WW2A3_8" + ], + [ + "CMT_FIFO_ER1BEG2_4", + "CMT_TOP_ER1BEG2_5" + ], + [ + "CMT_FIFO_EE2A1_0", + "CMT_TOP_EE2A1_1" + ], + [ + "CMT_FIFO_L_IMUX11_0", + "CMT_TOP_IMUX11_1" + ], + [ + "CMT_FIFO_L_IMUX22_7", + "CMT_TOP_IMUX22_8" + ], + [ + "CMT_FIFO_WW4A1_9", + "CMT_TOP_WW4A1_10" + ], + [ + "CMT_FIFO_ER1BEG2_2", + "CMT_TOP_ER1BEG2_3" + ], + [ + "CMT_FIFO_NE2A2_5", + "CMT_TOP_NE2A2_6" + ], + [ + "CMT_FIFO_L_CLK1_0", + "CMT_TOP_CLK1_1" + ], + [ + "CMT_FIFO_WR1END3_8", + "CMT_TOP_WR1END3_9" + ], + [ + "CMT_FIFO_SE2A1_11", + "CMT_TOP_SE2A1_12" + ], + [ + "CMT_FIFO_WW2A3_2", + "CMT_TOP_WW2A3_3" + ], + [ + "CMT_FIFO_WW4END2_10", + "CMT_TOP_WW4END2_11" + ], + [ + "CMT_FIFO_L_FAN1_0", + "CMT_TOP_FAN1_1" + ], + [ + "CMT_FIFO_L_IMUX4_9", + "CMT_TOP_IMUX4_10" + ], + [ + "CMT_FIFO_LH6_2", + "CMT_TOP_LH6_3" + ], + [ + "CMT_FIFO_LH5_5", + "CMT_TOP_LH5_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_2", + "CMT_TOP_LOGIC_OUTS_L_B20_3" + ], + [ + "CMT_FIFO_WW4B3_0", + "CMT_TOP_WW4B3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_1", + "CMT_TOP_LOGIC_OUTS_L_B16_2" + ], + [ + "CMT_FIFO_WW4C0_4", + "CMT_TOP_WW4C0_5" + ], + [ + "CMT_FIFO_NE4BEG3_6", + "CMT_TOP_NE4BEG3_7" + ], + [ + "CMT_FIFO_WW2A0_1", + "CMT_TOP_WW2A0_2" + ], + [ + "CMT_FIFO_NW4A2_4", + "CMT_TOP_NW4A2_5" + ], + [ + "CMT_FIFO_L_IMUX11_5", + "CMT_TOP_IMUX11_6" + ], + [ + "CMT_FIFO_NW4END1_3", + "CMT_TOP_NW4END1_4" + ], + [ + "CMT_FIFO_SW2A2_9", + "CMT_TOP_SW2A2_10" + ], + [ + "CMT_FIFO_EL1BEG3_4", + "CMT_TOP_EL1BEG3_5" + ], + [ + "CMT_FIFO_WW2A0_8", + "CMT_TOP_WW2A0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_8", + "CMT_TOP_LOGIC_OUTS_L_B17_9" + ], + [ + "CMT_FIFO_WW4A3_2", + "CMT_TOP_WW4A3_3" + ], + [ + "CMT_FIFO_NW4END2_4", + "CMT_TOP_NW4END2_5" + ], + [ + "CMT_FIFO_WW4C3_11", + "CMT_TOP_WW4C3_12" + ], + [ + "CMT_FIFO_NE4BEG2_8", + "CMT_TOP_NE4BEG2_9" + ], + [ + "CMT_FIFO_L_IMUX1_5", + "CMT_TOP_IMUX1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_0", + "CMT_TOP_LOGIC_OUTS_L_B16_1" + ], + [ + "CMT_FIFO_ER1BEG3_10", + "CMT_TOP_ER1BEG3_11" + ], + [ + "CMT_FIFO_EE2BEG1_8", + "CMT_TOP_EE2BEG1_9" + ], + [ + "CMT_FIFO_L_IMUX23_4", + "CMT_TOP_IMUX23_5" + ], + [ + "CMT_FIFO_L_IMUX6_3", + "CMT_TOP_IMUX6_4" + ], + [ + "CMT_FIFO_SE2A0_10", + "CMT_TOP_SE2A0_11" + ], + [ + "CMT_FIFO_WW2A3_1", + "CMT_TOP_WW2A3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_7", + "CMT_TOP_LOGIC_OUTS_L_B19_8" + ], + [ + "CMT_FIFO_L_IMUX19_6", + "CMT_TOP_IMUX19_7" + ], + [ + "CMT_FIFO_L_IMUX2_1", + "CMT_TOP_IMUX2_2" + ], + [ + "CMT_FIFO_LH10_6", + "CMT_TOP_LH10_7" + ], + [ + "CMT_FIFO_L_IMUX29_11", + "CMT_TOP_IMUX29_12" + ], + [ + "CMT_FIFO_NW2A1_8", + "CMT_TOP_NW2A1_9" + ], + [ + "CMT_FIFO_L_CLK0_4", + "CMT_TOP_CLK0_5" + ], + [ + "CMT_FIFO_NW4END0_6", + "CMT_TOP_NW4END0_7" + ], + [ + "CMT_FIFO_EE4A3_1", + "CMT_TOP_EE4A3_2" + ], + [ + "CMT_FIFO_L_IMUX30_11", + "CMT_TOP_IMUX30_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_6", + "CMT_TOP_LOGIC_OUTS_L_B9_7" + ], + [ + "CMT_FIFO_WW4B1_6", + "CMT_TOP_WW4B1_7" + ], + [ + "CMT_FIFO_L_IMUX16_7", + "CMT_TOP_IMUX16_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_7", + "CMT_TOP_LOGIC_OUTS_L_B11_8" + ], + [ + "CMT_FIFO_LH11_11", + "CMT_TOP_LH11_12" + ], + [ + "CMT_FIFO_EE4A1_6", + "CMT_TOP_EE4A1_7" + ], + [ + "CMT_FIFO_WW4A0_1", + "CMT_TOP_WW4A0_2" + ], + [ + "CMT_FIFO_SE2A0_0", + "CMT_TOP_SE2A0_1" + ], + [ + "CMT_FIFO_SE4C0_4", + "CMT_TOP_SE4C0_5" + ], + [ + "CMT_FIFO_ER1BEG2_10", + "CMT_TOP_ER1BEG2_11" + ], + [ + "CMT_FIFO_L_IMUX39_10", + "CMT_TOP_IMUX39_11" + ], + [ + "CMT_FIFO_L_FAN3_6", + "CMT_TOP_FAN3_7" + ], + [ + "CMT_FIFO_L_IMUX45_6", + "CMT_TOP_IMUX45_7" + ], + [ + "CMT_FIFO_WR1END0_7", + "CMT_TOP_WR1END0_8" + ], + [ + "CMT_FIFO_L_IMUX26_1", + "CMT_TOP_IMUX26_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "CMT_TOP_OCLKDIV_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_7", + "CMT_TOP_LOGIC_OUTS_L_B13_8" + ], + [ + "CMT_FIFO_L_BYP4_1", + "CMT_TOP_BYP4_2" + ], + [ + "CMT_FIFO_WW4END3_1", + "CMT_TOP_WW4END3_2" + ], + [ + "CMT_FIFO_L_FAN3_3", + "CMT_TOP_FAN3_4" + ], + [ + "CMT_FIFO_L_IMUX36_8", + "CMT_TOP_IMUX36_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_6", + "CMT_TOP_LOGIC_OUTS_L_B8_7" + ], + [ + "CMT_FIFO_LH12_2", + "CMT_TOP_LH12_3" + ], + [ + "CMT_FIFO_EE4B1_5", + "CMT_TOP_EE4B1_6" + ], + [ + "CMT_FIFO_SE4BEG0_5", + "CMT_TOP_SE4BEG0_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "CMT_TOP_OCLK_4" + ], + [ + "CMT_FIFO_L_IMUX16_0", + "CMT_TOP_IMUX16_1" + ], + [ + "CMT_FIFO_EE4BEG3_0", + "CMT_TOP_EE4BEG3_1" + ], + [ + "CMT_FIFO_L_IMUX36_4", + "CMT_TOP_IMUX36_5" + ], + [ + "CMT_FIFO_L_IMUX1_3", + "CMT_TOP_IMUX1_4" + ], + [ + "CMT_FIFO_EL1BEG1_9", + "CMT_TOP_EL1BEG1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_6", + "CMT_TOP_LOGIC_OUTS_L_B16_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_4", + "CMT_TOP_LOGIC_OUTS_L_B19_5" + ], + [ + "CMT_FIFO_NW4END3_4", + "CMT_TOP_NW4END3_5" + ], + [ + "CMT_FIFO_SW4A2_4", + "CMT_TOP_SW4A2_5" + ], + [ + "CMT_FIFO_LH2_1", + "CMT_TOP_LH2_2" + ], + [ + "CMT_FIFO_L_IMUX30_5", + "CMT_TOP_IMUX30_6" + ], + [ + "CMT_FIFO_L_IMUX42_5", + "CMT_TOP_IMUX42_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_6", + "CMT_TOP_LOGIC_OUTS_L_B19_7" + ], + [ + "CMT_FIFO_L_IMUX40_6", + "CMT_TOP_IMUX40_7" + ], + [ + "CMT_FIFO_WW4B2_8", + "CMT_TOP_WW4B2_9" + ], + [ + "CMT_FIFO_L_IMUX9_5", + "CMT_TOP_IMUX9_6" + ], + [ + "CMT_FIFO_L_IMUX41_4", + "CMT_TOP_IMUX41_5" + ], + [ + "CMT_FIFO_EE4B2_11", + "CMT_TOP_EE4B2_12" + ], + [ + "CMT_FIFO_EL1BEG0_6", + "CMT_TOP_EL1BEG0_7" + ], + [ + "CMT_FIFO_SW4A3_3", + "CMT_TOP_SW4A3_4" + ], + [ + "CMT_FIFO_SE4C3_10", + "CMT_TOP_SE4C3_11" + ], + [ + "CMT_FIFO_L_IMUX41_7", + "CMT_TOP_IMUX41_8" + ], + [ + "CMT_FIFO_L_IMUX14_11", + "CMT_TOP_IMUX14_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_4", + "CMT_TOP_LOGIC_OUTS_L_B11_5" + ], + [ + "CMT_FIFO_NE2A1_2", + "CMT_TOP_NE2A1_3" + ], + [ + "CMT_FIFO_NW4END2_2", + "CMT_TOP_NW4END2_3" + ], + [ + "CMT_FIFO_NE2A0_7", + "CMT_TOP_NE2A0_8" + ], + [ + "CMT_FIFO_WW2END1_1", + "CMT_TOP_WW2END1_2" + ], + [ + "CMT_FIFO_SW2A2_6", + "CMT_TOP_SW2A2_7" + ], + [ + "CMT_FIFO_EE4B0_2", + "CMT_TOP_EE4B0_3" + ], + [ + "CMT_FIFO_L_IMUX26_8", + "CMT_TOP_IMUX26_9" + ], + [ + "CMT_FIFO_SW2A0_9", + "CMT_TOP_SW2A0_10" + ], + [ + "CMT_FIFO_L_IMUX8_10", + "CMT_TOP_IMUX8_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "CMT_TOP_ICLKDIV_2" + ], + [ + "CMT_FIFO_SW4A2_0", + "CMT_TOP_SW4A2_1" + ], + [ + "CMT_FIFO_L_FAN2_11", + "CMT_TOP_FAN2_12" + ], + [ + "CMT_FIFO_L_IMUX30_4", + "CMT_TOP_IMUX30_5" + ], + [ + "CMT_FIFO_NE2A3_5", + "CMT_TOP_NE2A3_6" + ], + [ + "CMT_FIFO_WW2A1_9", + "CMT_TOP_WW2A1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_8" + ], + [ + "CMT_FIFO_L_IMUX41_0", + "CMT_TOP_IMUX41_1" + ], + [ + "CMT_FIFO_L_FAN5_1", + "CMT_TOP_FAN5_2" + ], + [ + "CMT_FIFO_EE2A1_11", + "CMT_TOP_EE2A1_12" + ], + [ + "CMT_FIFO_L_CLK1_7", + "CMT_TOP_CLK1_8" + ], + [ + "CMT_FIFO_EE4B0_8", + "CMT_TOP_EE4B0_9" + ], + [ + "CMT_FIFO_L_BYP5_8", + "CMT_TOP_BYP5_9" + ], + [ + "CMT_FIFO_LH9_2", + "CMT_TOP_LH9_3" + ], + [ + "CMT_FIFO_SE4BEG1_1", + "CMT_TOP_SE4BEG1_2" + ], + [ + "CMT_FIFO_L_IMUX29_0", + "CMT_TOP_IMUX29_1" + ], + [ + "CMT_FIFO_L_FAN0_8", + "CMT_TOP_FAN0_9" + ], + [ + "CMT_FIFO_SE4C3_1", + "CMT_TOP_SE4C3_2" + ], + [ + "CMT_FIFO_LH6_4", + "CMT_TOP_LH6_5" + ], + [ + "CMT_FIFO_SW4END3_11", + "CMT_TOP_SW4END3_12" + ], + [ + "CMT_FIFO_SE4BEG1_4", + "CMT_TOP_SE4BEG1_5" + ], + [ + "CMT_FIFO_SE2A0_2", + "CMT_TOP_SE2A0_3" + ], + [ + "CMT_FIFO_WW4A1_0", + "CMT_TOP_WW4A1_1" + ], + [ + "CMT_FIFO_EE4C1_10", + "CMT_TOP_EE4C1_11" + ], + [ + "CMT_FIFO_WW2A1_8", + "CMT_TOP_WW2A1_9" + ], + [ + "CMT_FIFO_L_CTRL1_8", + "CMT_TOP_CTRL1_9" + ], + [ + "CMT_FIFO_L_FAN5_0", + "CMT_TOP_FAN5_1" + ], + [ + "CMT_FIFO_SE4C3_0", + "CMT_TOP_SE4C3_1" + ], + [ + "CMT_FIFO_WR1END3_10", + "CMT_TOP_WR1END3_11" + ], + [ + "CMT_FIFO_L_FAN7_11", + "CMT_TOP_FAN7_12" + ], + [ + "CMT_FIFO_L_IMUX39_11", + "CMT_TOP_IMUX39_12" + ], + [ + "CMT_FIFO_SW2A3_2", + "CMT_TOP_SW2A3_3" + ], + [ + "CMT_FIFO_WW4A2_11", + "CMT_TOP_WW4A2_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_8", + "CMT_TOP_LOGIC_OUTS_L_B0_9" + ], + [ + "CMT_FIFO_WW4END2_4", + "CMT_TOP_WW4END2_5" + ], + [ + "CMT_FIFO_NE2A1_0", + "CMT_TOP_NE2A1_1" + ], + [ + "CMT_FIFO_SE4C2_10", + "CMT_TOP_SE4C2_11" + ], + [ + "CMT_FIFO_ER1BEG0_0", + "CMT_TOP_ER1BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_5", + "CMT_TOP_LOGIC_OUTS_L_B15_6" + ], + [ + "CMT_FIFO_L_IMUX9_7", + "CMT_TOP_IMUX9_8" + ], + [ + "CMT_FIFO_L_IMUX7_1", + "CMT_TOP_IMUX7_2" + ], + [ + "CMT_FIFO_NE2A3_6", + "CMT_TOP_NE2A3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_2", + "CMT_TOP_LOGIC_OUTS_L_B18_3" + ], + [ + "CMT_FIFO_NE4C0_3", + "CMT_TOP_NE4C0_4" + ], + [ + "CMT_FIFO_SE4C1_11", + "CMT_TOP_SE4C1_12" + ], + [ + "CMT_FIFO_SW2A2_10", + "CMT_TOP_SW2A2_11" + ], + [ + "CMT_FIFO_SW2A1_7", + "CMT_TOP_SW2A1_8" + ], + [ + "CMT_FIFO_EE4B1_7", + "CMT_TOP_EE4B1_8" + ], + [ + "CMT_FIFO_NW2A1_7", + "CMT_TOP_NW2A1_8" + ], + [ + "CMT_FIFO_SE4C3_3", + "CMT_TOP_SE4C3_4" + ], + [ + "CMT_FIFO_L_IMUX6_0", + "CMT_TOP_IMUX6_1" + ], + [ + "CMT_FIFO_L_CTRL1_6", + "CMT_TOP_CTRL1_7" + ], + [ + "CMT_FIFO_LH5_6", + "CMT_TOP_LH5_7" + ], + [ + "CMT_FIFO_SW2A3_6", + "CMT_TOP_SW2A3_7" + ], + [ + "CMT_FIFO_EE4BEG3_2", + "CMT_TOP_EE4BEG3_3" + ], + [ + "CMT_FIFO_NW2A0_5", + "CMT_TOP_NW2A0_6" + ], + [ + "CMT_FIFO_WL1END3_10", + "CMT_TOP_WL1END3_11" + ], + [ + "CMT_FIFO_EE2A0_10", + "CMT_TOP_EE2A0_11" + ], + [ + "CMT_FIFO_L_CLK1_11", + "CMT_TOP_CLK1_12" + ], + [ + "CMT_FIFO_L_FAN0_1", + "CMT_TOP_FAN0_2" + ], + [ + "CMT_FIFO_NE4C0_8", + "CMT_TOP_NE4C0_9" + ], + [ + "CMT_FIFO_LH7_4", + "CMT_TOP_LH7_5" + ], + [ + "CMT_FIFO_NW4END3_1", + "CMT_TOP_NW4END3_2" + ], + [ + "CMT_FIFO_NW2A1_9", + "CMT_TOP_NW2A1_10" + ], + [ + "CMT_FIFO_LH5_8", + "CMT_TOP_LH5_9" + ], + [ + "CMT_FIFO_SW4A1_6", + "CMT_TOP_SW4A1_7" + ], + [ + "CMT_FIFO_SE4BEG0_11", + "CMT_TOP_SE4BEG0_12" + ], + [ + "CMT_FIFO_EE4A0_3", + "CMT_TOP_EE4A0_4" + ], + [ + "CMT_FIFO_L_FAN5_10", + "CMT_TOP_FAN5_11" + ], + [ + "CMT_FIFO_WW4END3_9", + "CMT_TOP_WW4END3_10" + ], + [ + "CMT_FIFO_SW4END0_4", + "CMT_TOP_SW4END0_5" + ], + [ + "CMT_FIFO_EE4C3_11", + "CMT_TOP_EE4C3_12" + ], + [ + "CMT_FIFO_L_FAN3_0", + "CMT_TOP_FAN3_1" + ], + [ + "CMT_FIFO_WW2END0_2", + "CMT_TOP_WW2END0_3" + ], + [ + "CMT_FIFO_EE4B3_7", + "CMT_TOP_EE4B3_8" + ], + [ + "CMT_FIFO_L_CTRL0_11", + "CMT_TOP_CTRL0_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_11", + "CMT_TOP_LOGIC_OUTS_L_B19_12" + ], + [ + "CMT_FIFO_SW4A2_1", + "CMT_TOP_SW4A2_2" + ], + [ + "CMT_FIFO_WW2A0_4", + "CMT_TOP_WW2A0_5" + ], + [ + "CMT_FIFO_EE2A1_4", + "CMT_TOP_EE2A1_5" + ], + [ + "CMT_FIFO_WW4B2_7", + "CMT_TOP_WW4B2_8" + ], + [ + "CMT_FIFO_L_CTRL1_1", + "CMT_TOP_CTRL1_2" + ], + [ + "CMT_FIFO_ER1BEG1_8", + "CMT_TOP_ER1BEG1_9" + ], + [ + "CMT_FIFO_EL1BEG2_4", + "CMT_TOP_EL1BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX12_0", + "CMT_TOP_IMUX12_1" + ], + [ + "CMT_FIFO_L_IMUX28_8", + "CMT_TOP_IMUX28_9" + ], + [ + "CMT_FIFO_NE2A0_6", + "CMT_TOP_NE2A0_7" + ], + [ + "CMT_FIFO_L_IMUX32_5", + "CMT_TOP_IMUX32_6" + ], + [ + "CMT_FIFO_L_IMUX42_6", + "CMT_TOP_IMUX42_7" + ], + [ + "CMT_FIFO_L_BYP3_9", + "CMT_TOP_BYP3_10" + ], + [ + "CMT_FIFO_L_IMUX5_1", + "CMT_TOP_IMUX5_2" + ], + [ + "CMT_FIFO_LH9_11", + "CMT_TOP_LH9_12" + ], + [ + "CMT_FIFO_WW2A3_10", + "CMT_TOP_WW2A3_11" + ], + [ + "CMT_FIFO_NW4END1_1", + "CMT_TOP_NW4END1_2" + ], + [ + "CMT_FIFO_WL1END3_1", + "CMT_TOP_WL1END3_2" + ], + [ + "CMT_FIFO_NW2A2_7", + "CMT_TOP_NW2A2_8" + ], + [ + "CMT_FIFO_L_IMUX28_0", + "CMT_TOP_IMUX28_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_7", + "CMT_TOP_LOGIC_OUTS_L_B23_8" + ], + [ + "CMT_FIFO_NE4C2_5", + "CMT_TOP_NE4C2_6" + ], + [ + "CMT_FIFO_L_IMUX8_11", + "CMT_TOP_IMUX8_12" + ], + [ + "CMT_FIFO_L_FAN4_11", + "CMT_TOP_FAN4_12" + ], + [ + "CMT_FIFO_L_IMUX40_4", + "CMT_TOP_IMUX40_5" + ], + [ + "CMT_FIFO_L_IMUX11_8", + "CMT_TOP_IMUX11_9" + ], + [ + "CMT_FIFO_L_IMUX27_0", + "CMT_TOP_IMUX27_1" + ], + [ + "CMT_FIFO_L_IMUX3_10", + "CMT_TOP_IMUX3_11" + ], + [ + "CMT_FIFO_L_IMUX12_7", + "CMT_TOP_IMUX12_8" + ], + [ + "CMT_FIFO_L_IMUX35_3", + "CMT_TOP_IMUX35_4" + ], + [ + "CMT_FIFO_L_IMUX23_0", + "CMT_TOP_IMUX23_1" + ], + [ + "CMT_FIFO_L_IMUX20_7", + "CMT_TOP_IMUX20_8" + ], + [ + "CMT_FIFO_SE4C3_9", + "CMT_TOP_SE4C3_10" + ], + [ + "CMT_FIFO_L_IMUX42_9", + "CMT_TOP_IMUX42_10" + ], + [ + "CMT_FIFO_WW2A1_3", + "CMT_TOP_WW2A1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_2", + "CMT_TOP_LOGIC_OUTS_L_B9_3" + ], + [ + "CMT_FIFO_NE4BEG1_8", + "CMT_TOP_NE4BEG1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_3", + "CMT_TOP_LOGIC_OUTS_L_B19_4" + ], + [ + "CMT_FIFO_L_IMUX22_3", + "CMT_TOP_IMUX22_4" + ], + [ + "CMT_FIFO_L_IMUX46_1", + "CMT_TOP_IMUX46_2" + ], + [ + "CMT_FIFO_L_IMUX25_9", + "CMT_TOP_IMUX25_10" + ], + [ + "CMT_FIFO_SE2A0_7", + "CMT_TOP_SE2A0_8" + ], + [ + "CMT_FIFO_L_BYP3_4", + "CMT_TOP_BYP3_5" + ], + [ + "CMT_FIFO_WW2END1_2", + "CMT_TOP_WW2END1_3" + ], + [ + "CMT_FIFO_WW4C1_9", + "CMT_TOP_WW4C1_10" + ], + [ + "CMT_FIFO_NW4END1_4", + "CMT_TOP_NW4END1_5" + ], + [ + "CMT_FIFO_WW4END3_5", + "CMT_TOP_WW4END3_6" + ], + [ + "CMT_FIFO_EL1BEG2_3", + "CMT_TOP_EL1BEG2_4" + ], + [ + "CMT_FIFO_L_IMUX7_5", + "CMT_TOP_IMUX7_6" + ], + [ + "CMT_FIFO_L_FAN0_5", + "CMT_TOP_FAN0_6" + ], + [ + "CMT_FIFO_L_IMUX31_2", + "CMT_TOP_IMUX31_3" + ], + [ + "CMT_FIFO_WW4A2_5", + "CMT_TOP_WW4A2_6" + ], + [ + "CMT_FIFO_L_BYP4_10", + "CMT_TOP_BYP4_11" + ], + [ + "CMT_FIFO_EE2BEG3_7", + "CMT_TOP_EE2BEG3_8" + ], + [ + "CMT_FIFO_WW4END3_4", + "CMT_TOP_WW4END3_5" + ], + [ + "CMT_FIFO_WR1END0_3", + "CMT_TOP_WR1END0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_6", + "CMT_TOP_LOGIC_OUTS_L_B11_7" + ], + [ + "CMT_FIFO_EE4B3_8", + "CMT_TOP_EE4B3_9" + ], + [ + "CMT_FIFO_NE4BEG0_11", + "CMT_TOP_NE4BEG0_12" + ], + [ + "CMT_FIFO_L_FAN2_5", + "CMT_TOP_FAN2_6" + ], + [ + "CMT_FIFO_L_BYP4_9", + "CMT_TOP_BYP4_10" + ], + [ + "CMT_FIFO_SE4BEG3_10", + "CMT_TOP_SE4BEG3_11" + ], + [ + "CMT_FIFO_L_BYP6_3", + "CMT_TOP_BYP6_4" + ], + [ + "CMT_FIFO_WW4B0_9", + "CMT_TOP_WW4B0_10" + ], + [ + "CMT_FIFO_SE4BEG2_10", + "CMT_TOP_SE4BEG2_11" + ], + [ + "CMT_FIFO_WW2A1_0", + "CMT_TOP_WW2A1_1" + ], + [ + "CMT_FIFO_EE4BEG3_4", + "CMT_TOP_EE4BEG3_5" + ], + [ + "CMT_FIFO_WW4A0_5", + "CMT_TOP_WW4A0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_5", + "CMT_TOP_LOGIC_OUTS_L_B23_6" + ], + [ + "CMT_FIFO_EE4B0_7", + "CMT_TOP_EE4B0_8" + ], + [ + "CMT_FIFO_LH11_8", + "CMT_TOP_LH11_9" + ], + [ + "CMT_FIFO_NW4END2_0", + "CMT_TOP_NW4END2_1" + ], + [ + "CMT_FIFO_WW4A2_0", + "CMT_TOP_WW4A2_1" + ], + [ + "CMT_FIFO_SW4END2_9", + "CMT_TOP_SW4END2_10" + ], + [ + "CMT_FIFO_EE2BEG2_11", + "CMT_TOP_EE2BEG2_12" + ], + [ + "CMT_FIFO_NE4BEG3_7", + "CMT_TOP_NE4BEG3_8" + ], + [ + "CMT_FIFO_WW4C0_6", + "CMT_TOP_WW4C0_7" + ], + [ + "CMT_FIFO_LH9_4", + "CMT_TOP_LH9_5" + ], + [ + "CMT_FIFO_SE2A1_6", + "CMT_TOP_SE2A1_7" + ], + [ + "CMT_FIFO_NE4C3_8", + "CMT_TOP_NE4C3_9" + ], + [ + "CMT_FIFO_L_IMUX6_2", + "CMT_TOP_IMUX6_3" + ], + [ + "CMT_FIFO_L_IMUX28_6", + "CMT_TOP_IMUX28_7" + ], + [ + "CMT_FIFO_NW4END1_6", + "CMT_TOP_NW4END1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_0", + "CMT_TOP_LOGIC_OUTS_L_B22_1" + ], + [ + "CMT_FIFO_L_IMUX33_9", + "CMT_TOP_IMUX33_10" + ], + [ + "CMT_FIFO_WW4A0_11", + "CMT_TOP_WW4A0_12" + ], + [ + "CMT_FIFO_NW4A0_8", + "CMT_TOP_NW4A0_9" + ], + [ + "CMT_FIFO_WW2A3_3", + "CMT_TOP_WW2A3_4" + ], + [ + "CMT_FIFO_WW2END1_11", + "CMT_TOP_WW2END1_12" + ], + [ + "CMT_FIFO_WW2A2_5", + "CMT_TOP_WW2A2_6" + ], + [ + "CMT_FIFO_L_IMUX47_9", + "CMT_TOP_IMUX47_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_5", + "CMT_TOP_LOGIC_OUTS_L_B10_6" + ], + [ + "CMT_FIFO_NE2A1_9", + "CMT_TOP_NE2A1_10" + ], + [ + "CMT_FIFO_NE4BEG3_10", + "CMT_TOP_NE4BEG3_11" + ], + [ + "CMT_FIFO_NE4BEG0_6", + "CMT_TOP_NE4BEG0_7" + ], + [ + "CMT_FIFO_WL1END0_6", + "CMT_TOP_WL1END0_7" + ], + [ + "CMT_FIFO_SW2A0_8", + "CMT_TOP_SW2A0_9" + ], + [ + "CMT_FIFO_WW4C3_8", + "CMT_TOP_WW4C3_9" + ], + [ + "CMT_FIFO_SE4BEG2_9", + "CMT_TOP_SE4BEG2_10" + ], + [ + "CMT_FIFO_EL1BEG3_7", + "CMT_TOP_EL1BEG3_8" + ], + [ + "CMT_FIFO_SE2A2_11", + "CMT_TOP_SE2A2_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_6", + "CMT_TOP_LOGIC_OUTS_L_B17_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_1" + ], + [ + "CMT_FIFO_EE4BEG0_4", + "CMT_TOP_EE4BEG0_5" + ], + [ + "CMT_FIFO_L_IMUX24_0", + "CMT_TOP_IMUX24_1" + ], + [ + "CMT_FIFO_EE4A1_4", + "CMT_TOP_EE4A1_5" + ], + [ + "CMT_FIFO_SE4BEG3_7", + "CMT_TOP_SE4BEG3_8" + ], + [ + "CMT_FIFO_SW4A1_7", + "CMT_TOP_SW4A1_8" + ], + [ + "CMT_FIFO_L_IMUX6_10", + "CMT_TOP_IMUX6_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_4", + "CMT_TOP_LOGIC_OUTS_L_B12_5" + ], + [ + "CMT_FIFO_EE2BEG2_8", + "CMT_TOP_EE2BEG2_9" + ], + [ + "CMT_FIFO_L_IMUX39_5", + "CMT_TOP_IMUX39_6" + ], + [ + "CMT_FIFO_SW4A3_6", + "CMT_TOP_SW4A3_7" + ], + [ + "CMT_FIFO_NE4BEG2_10", + "CMT_TOP_NE4BEG2_11" + ], + [ + "CMT_FIFO_SE2A1_10", + "CMT_TOP_SE2A1_11" + ], + [ + "CMT_FIFO_SW4END1_2", + "CMT_TOP_SW4END1_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "CMT_TOP_OCLKDIV_8" + ], + [ + "CMT_FIFO_WW2END2_7", + "CMT_TOP_WW2END2_8" + ], + [ + "CMT_FIFO_L_BYP4_4", + "CMT_TOP_BYP4_5" + ], + [ + "CMT_FIFO_NW2A2_6", + "CMT_TOP_NW2A2_7" + ], + [ + "CMT_FIFO_NE2A3_9", + "CMT_TOP_NE2A3_10" + ], + [ + "CMT_FIFO_EE2A0_4", + "CMT_TOP_EE2A0_5" + ], + [ + "CMT_FIFO_NW4END1_0", + "CMT_TOP_NW4END1_1" + ], + [ + "CMT_FIFO_L_IMUX42_4", + "CMT_TOP_IMUX42_5" + ], + [ + "CMT_FIFO_L_IMUX0_8", + "CMT_TOP_IMUX0_9" + ], + [ + "CMT_FIFO_L_IMUX19_3", + "CMT_TOP_IMUX19_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "CMT_TOP_OCLKDIV_12" + ], + [ + "CMT_FIFO_LH11_6", + "CMT_TOP_LH11_7" + ], + [ + "CMT_FIFO_WW4B0_11", + "CMT_TOP_WW4B0_12" + ], + [ + "CMT_FIFO_L_CTRL1_7", + "CMT_TOP_CTRL1_8" + ], + [ + "CMT_FIFO_SW4A0_9", + "CMT_TOP_SW4A0_10" + ], + [ + "CMT_FIFO_L_FAN3_1", + "CMT_TOP_FAN3_2" + ], + [ + "CMT_FIFO_L_IMUX24_5", + "CMT_TOP_IMUX24_6" + ], + [ + "CMT_FIFO_WW2A0_11", + "CMT_TOP_WW2A0_12" + ], + [ + "CMT_FIFO_NW4END2_1", + "CMT_TOP_NW4END2_2" + ], + [ + "CMT_FIFO_SE4BEG0_7", + "CMT_TOP_SE4BEG0_8" + ], + [ + "CMT_FIFO_LH2_2", + "CMT_TOP_LH2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_9", + "CMT_TOP_LOGIC_OUTS_L_B21_10" + ], + [ + "CMT_FIFO_LH8_10", + "CMT_TOP_LH8_11" + ], + [ + "CMT_FIFO_L_IMUX16_5", + "CMT_TOP_IMUX16_6" + ], + [ + "CMT_FIFO_NW4END0_2", + "CMT_TOP_NW4END0_3" + ], + [ + "CMT_FIFO_WL1END0_10", + "CMT_TOP_WL1END0_11" + ], + [ + "CMT_FIFO_L_CTRL1_9", + "CMT_TOP_CTRL1_10" + ], + [ + "CMT_FIFO_LH9_6", + "CMT_TOP_LH9_7" + ], + [ + "CMT_FIFO_WW2A2_2", + "CMT_TOP_WW2A2_3" + ], + [ + "CMT_FIFO_L_IMUX9_6", + "CMT_TOP_IMUX9_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_11" + ], + [ + "CMT_FIFO_NE2A1_10", + "CMT_TOP_NE2A1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_2", + "CMT_TOP_LOGIC_OUTS_L_B15_3" + ], + [ + "CMT_FIFO_WW4A1_4", + "CMT_TOP_WW4A1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8" + ], + [ + "CMT_FIFO_WL1END2_2", + "CMT_TOP_WL1END2_3" + ], + [ + "CMT_FIFO_ER1BEG2_0", + "CMT_TOP_ER1BEG2_1" + ], + [ + "CMT_FIFO_WW4A2_9", + "CMT_TOP_WW4A2_10" + ], + [ + "CMT_FIFO_L_CLK0_8", + "CMT_TOP_CLK0_9" + ], + [ + "CMT_FIFO_L_IMUX0_11", + "CMT_TOP_IMUX0_12" + ], + [ + "CMT_FIFO_WW4END3_11", + "CMT_TOP_WW4END3_12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "CMT_TOP_OCLKDIV_1" + ], + [ + "CMT_FIFO_L_BYP2_11", + "CMT_TOP_BYP2_12" + ], + [ + "CMT_FIFO_EE4A0_2", + "CMT_TOP_EE4A0_3" + ], + [ + "CMT_FIFO_L_IMUX20_2", + "CMT_TOP_IMUX20_3" + ], + [ + "CMT_FIFO_SE4BEG1_3", + "CMT_TOP_SE4BEG1_4" + ], + [ + "CMT_FIFO_L_FAN5_4", + "CMT_TOP_FAN5_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_9", + "CMT_TOP_LOGIC_OUTS_L_B1_10" + ], + [ + "CMT_FIFO_WW4END0_7", + "CMT_TOP_WW4END0_8" + ], + [ + "CMT_FIFO_L_IMUX10_1", + "CMT_TOP_IMUX10_2" + ], + [ + "CMT_FIFO_EE4B1_8", + "CMT_TOP_EE4B1_9" + ], + [ + "CMT_FIFO_WW4A0_8", + "CMT_TOP_WW4A0_9" + ], + [ + "CMT_FIFO_L_IMUX47_3", + "CMT_TOP_IMUX47_4" + ], + [ + "CMT_FIFO_EE2A3_8", + "CMT_TOP_EE2A3_9" + ], + [ + "CMT_FIFO_ER1BEG3_2", + "CMT_TOP_ER1BEG3_3" + ], + [ + "CMT_FIFO_L_FAN0_7", + "CMT_TOP_FAN0_8" + ], + [ + "CMT_FIFO_L_FAN6_6", + "CMT_TOP_FAN6_7" + ], + [ + "CMT_FIFO_L_IMUX3_2", + "CMT_TOP_IMUX3_3" + ], + [ + "CMT_FIFO_L_IMUX42_0", + "CMT_TOP_IMUX42_1" + ], + [ + "CMT_FIFO_L_FAN4_6", + "CMT_TOP_FAN4_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_11", + "CMT_TOP_LOGIC_OUTS_L_B12_12" + ], + [ + "CMT_FIFO_ER1BEG0_1", + "CMT_TOP_ER1BEG0_2" + ], + [ + "CMT_FIFO_WW2END3_10", + "CMT_TOP_WW2END3_11" + ], + [ + "CMT_FIFO_L_IMUX8_3", + "CMT_TOP_IMUX8_4" + ], + [ + "CMT_FIFO_SE2A2_3", + "CMT_TOP_SE2A2_4" + ], + [ + "CMT_FIFO_SE2A1_2", + "CMT_TOP_SE2A1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_3", + "CMT_TOP_LOGIC_OUTS_L_B15_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_10", + "CMT_TOP_LOGIC_OUTS_L_B4_11" + ], + [ + "CMT_FIFO_SE4BEG0_1", + "CMT_TOP_SE4BEG0_2" + ], + [ + "CMT_FIFO_SW4END0_6", + "CMT_TOP_SW4END0_7" + ], + [ + "CMT_FIFO_NE4C2_7", + "CMT_TOP_NE4C2_8" + ], + [ + "CMT_FIFO_WL1END1_3", + "CMT_TOP_WL1END1_4" + ], + [ + "CMT_FIFO_EL1BEG3_10", + "CMT_TOP_EL1BEG3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_8", + "CMT_TOP_LOGIC_OUTS_L_B23_9" + ], + [ + "CMT_FIFO_L_IMUX23_1", + "CMT_TOP_IMUX23_2" + ], + [ + "CMT_FIFO_SW2A2_4", + "CMT_TOP_SW2A2_5" + ], + [ + "CMT_FIFO_L_IMUX1_9", + "CMT_TOP_IMUX1_10" + ], + [ + "CMT_FIFO_L_IMUX22_5", + "CMT_TOP_IMUX22_6" + ], + [ + "CMT_FIFO_L_FAN5_9", + "CMT_TOP_FAN5_10" + ], + [ + "CMT_FIFO_L_IMUX45_8", + "CMT_TOP_IMUX45_9" + ], + [ + "CMT_FIFO_L_BYP1_7", + "CMT_TOP_BYP1_8" + ], + [ + "CMT_FIFO_WR1END0_1", + "CMT_TOP_WR1END0_2" + ], + [ + "CMT_FIFO_NE4C0_6", + "CMT_TOP_NE4C0_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_9", + "CMT_TOP_LOGIC_OUTS_L_B8_10" + ], + [ + "CMT_FIFO_L_IMUX14_7", + "CMT_TOP_IMUX14_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_3", + "CMT_TOP_LOGIC_OUTS_L_B11_4" + ], + [ + "CMT_FIFO_L_IMUX33_8", + "CMT_TOP_IMUX33_9" + ], + [ + "CMT_FIFO_L_BYP7_2", + "CMT_TOP_BYP7_3" + ], + [ + "CMT_FIFO_NW4END3_6", + "CMT_TOP_NW4END3_7" + ], + [ + "CMT_FIFO_L_IMUX20_0", + "CMT_TOP_IMUX20_1" + ], + [ + "CMT_FIFO_WW2END3_4", + "CMT_TOP_WW2END3_5" + ], + [ + "CMT_FIFO_L_BYP0_5", + "CMT_TOP_BYP0_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "CMT_TOP_ICLK_3" + ], + [ + "CMT_FIFO_EE2BEG0_2", + "CMT_TOP_EE2BEG0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_4", + "CMT_TOP_LOGIC_OUTS_L_B10_5" + ], + [ + "CMT_FIFO_ER1BEG3_4", + "CMT_TOP_ER1BEG3_5" + ], + [ + "CMT_FIFO_NW2A2_5", + "CMT_TOP_NW2A2_6" + ], + [ + "CMT_FIFO_NE4C3_4", + "CMT_TOP_NE4C3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_10", + "CMT_TOP_LOGIC_OUTS_L_B20_11" + ], + [ + "CMT_FIFO_EE4B3_3", + "CMT_TOP_EE4B3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_3", + "CMT_TOP_LOGIC_OUTS_L_B8_4" + ], + [ + "CMT_FIFO_NW2A0_3", + "CMT_TOP_NW2A0_4" + ], + [ + "CMT_FIFO_L_BYP2_2", + "CMT_TOP_BYP2_3" + ], + [ + "CMT_FIFO_WW2END2_9", + "CMT_TOP_WW2END2_10" + ], + [ + "CMT_FIFO_NW4END0_8", + "CMT_TOP_NW4END0_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "CMT_TOP_ICLKDIV_7" + ], + [ + "CMT_FIFO_SE4C3_6", + "CMT_TOP_SE4C3_7" + ], + [ + "CMT_FIFO_SW4A1_5", + "CMT_TOP_SW4A1_6" + ], + [ + "CMT_FIFO_WW2END0_7", + "CMT_TOP_WW2END0_8" + ], + [ + "CMT_FIFO_SE4C2_5", + "CMT_TOP_SE4C2_6" + ], + [ + "CMT_FIFO_SE4BEG1_10", + "CMT_TOP_SE4BEG1_11" + ], + [ + "CMT_FIFO_NW4A2_6", + "CMT_TOP_NW4A2_7" + ], + [ + "CMT_FIFO_EE4A1_5", + "CMT_TOP_EE4A1_6" + ], + [ + "CMT_FIFO_NW4A3_6", + "CMT_TOP_NW4A3_7" + ], + [ + "CMT_FIFO_SW4END1_0", + "CMT_TOP_SW4END1_1" + ], + [ + "CMT_FIFO_L_IMUX4_10", + "CMT_TOP_IMUX4_11" + ], + [ + "CMT_FIFO_WR1END2_2", + "CMT_TOP_WR1END2_3" + ], + [ + "CMT_FIFO_NE4C1_1", + "CMT_TOP_NE4C1_2" + ], + [ + "CMT_FIFO_WW4B2_6", + "CMT_TOP_WW4B2_7" + ], + [ + "CMT_FIFO_L_BYP0_4", + "CMT_TOP_BYP0_5" + ], + [ + "CMT_FIFO_NW4END3_11", + "CMT_TOP_NW4END3_12" + ], + [ + "CMT_FIFO_EE4C2_4", + "CMT_TOP_EE4C2_5" + ], + [ + "CMT_FIFO_L_IMUX8_4", + "CMT_TOP_IMUX8_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "CMT_TOP_ICLK_9" + ], + [ + "CMT_FIFO_SE4C0_8", + "CMT_TOP_SE4C0_9" + ], + [ + "CMT_FIFO_NW2A2_10", + "CMT_TOP_NW2A2_11" + ], + [ + "CMT_FIFO_EE4A0_4", + "CMT_TOP_EE4A0_5" + ], + [ + "CMT_FIFO_L_BYP4_0", + "CMT_TOP_BYP4_1" + ], + [ + "CMT_FIFO_NW2A3_8", + "CMT_TOP_NW2A3_9" + ], + [ + "CMT_FIFO_EE2BEG3_9", + "CMT_TOP_EE2BEG3_10" + ], + [ + "CMT_FIFO_SE4C3_11", + "CMT_TOP_SE4C3_12" + ], + [ + "CMT_FIFO_WW4END3_10", + "CMT_TOP_WW4END3_11" + ], + [ + "CMT_FIFO_ER1BEG2_1", + "CMT_TOP_ER1BEG2_2" + ], + [ + "CMT_FIFO_NW4A2_10", + "CMT_TOP_NW4A2_11" + ], + [ + "CMT_FIFO_EE4BEG0_6", + "CMT_TOP_EE4BEG0_7" + ], + [ + "CMT_FIFO_L_IMUX30_10", + "CMT_TOP_IMUX30_11" + ], + [ + "CMT_FIFO_EE4B2_9", + "CMT_TOP_EE4B2_10" + ], + [ + "CMT_FIFO_SW4A2_8", + "CMT_TOP_SW4A2_9" + ], + [ + "CMT_FIFO_WW4A3_10", + "CMT_TOP_WW4A3_11" + ], + [ + "CMT_FIFO_NE4BEG1_6", + "CMT_TOP_NE4BEG1_7" + ], + [ + "CMT_FIFO_WR1END1_7", + "CMT_TOP_WR1END1_8" + ], + [ + "CMT_FIFO_L_BYP2_5", + "CMT_TOP_BYP2_6" + ], + [ + "CMT_FIFO_L_IMUX0_5", + "CMT_TOP_IMUX0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_6" + ], + [ + "CMT_FIFO_EE4C2_1", + "CMT_TOP_EE4C2_2" + ], + [ + "CMT_FIFO_EE4B1_1", + "CMT_TOP_EE4B1_2" + ], + [ + "CMT_FIFO_NW4A3_9", + "CMT_TOP_NW4A3_10" + ], + [ + "CMT_FIFO_SW4END3_6", + "CMT_TOP_SW4END3_7" + ], + [ + "CMT_FIFO_EE4A1_1", + "CMT_TOP_EE4A1_2" + ], + [ + "CMT_FIFO_EL1BEG0_1", + "CMT_TOP_EL1BEG0_2" + ], + [ + "CMT_FIFO_EE4A2_4", + "CMT_TOP_EE4A2_5" + ], + [ + "CMT_FIFO_L_IMUX32_0", + "CMT_TOP_IMUX32_1" + ], + [ + "CMT_FIFO_SE2A2_2", + "CMT_TOP_SE2A2_3" + ], + [ + "CMT_FIFO_L_IMUX14_2", + "CMT_TOP_IMUX14_3" + ], + [ + "CMT_FIFO_NE2A2_9", + "CMT_TOP_NE2A2_10" + ], + [ + "CMT_FIFO_EE4C0_8", + "CMT_TOP_EE4C0_9" + ], + [ + "CMT_FIFO_L_IMUX22_4", + "CMT_TOP_IMUX22_5" + ], + [ + "CMT_FIFO_WW4B1_9", + "CMT_TOP_WW4B1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_6", + "CMT_TOP_LOGIC_OUTS_L_B20_7" + ], + [ + "CMT_FIFO_NE4C3_1", + "CMT_TOP_NE4C3_2" + ], + [ + "CMT_FIFO_L_IMUX47_6", + "CMT_TOP_IMUX47_7" + ], + [ + "CMT_FIFO_L_IMUX45_7", + "CMT_TOP_IMUX45_8" + ], + [ + "CMT_FIFO_LH12_7", + "CMT_TOP_LH12_8" + ], + [ + "CMT_FIFO_EE2A2_11", + "CMT_TOP_EE2A2_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_4", + "CMT_TOP_LOGIC_OUTS_L_B4_5" + ], + [ + "CMT_FIFO_WW2A0_5", + "CMT_TOP_WW2A0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_0", + "CMT_TOP_LOGIC_OUTS_L_B9_1" + ], + [ + "CMT_FIFO_L_PHASER_RDENABLE", + "CMT_MMCM_A_RDEN_TOFIFO" + ], + [ + "CMT_FIFO_WW2END3_5", + "CMT_TOP_WW2END3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_7", + "CMT_TOP_LOGIC_OUTS_L_B5_8" + ], + [ + "CMT_FIFO_L_IMUX4_7", + "CMT_TOP_IMUX4_8" + ], + [ + "CMT_FIFO_L_FAN0_11", + "CMT_TOP_FAN0_12" + ], + [ + "CMT_FIFO_EE4A0_5", + "CMT_TOP_EE4A0_6" + ], + [ + "CMT_FIFO_L_IMUX23_5", + "CMT_TOP_IMUX23_6" + ], + [ + "CMT_FIFO_NW2A0_2", + "CMT_TOP_NW2A0_3" + ], + [ + "CMT_FIFO_EE2BEG0_1", + "CMT_TOP_EE2BEG0_2" + ], + [ + "CMT_FIFO_NE4BEG0_8", + "CMT_TOP_NE4BEG0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_7", + "CMT_TOP_LOGIC_OUTS_L_B20_8" + ], + [ + "CMT_FIFO_NW4A3_5", + "CMT_TOP_NW4A3_6" + ], + [ + "CMT_FIFO_NE4C3_7", + "CMT_TOP_NE4C3_8" + ], + [ + "CMT_FIFO_L_BYP6_10", + "CMT_TOP_BYP6_11" + ], + [ + "CMT_FIFO_L_IMUX46_5", + "CMT_TOP_IMUX46_6" + ], + [ + "CMT_FIFO_WW4END3_8", + "CMT_TOP_WW4END3_9" + ], + [ + "CMT_FIFO_NW4END3_2", + "CMT_TOP_NW4END3_3" + ], + [ + "CMT_FIFO_WW2END1_10", + "CMT_TOP_WW2END1_11" + ], + [ + "CMT_FIFO_ER1BEG2_8", + "CMT_TOP_ER1BEG2_9" + ], + [ + "CMT_FIFO_L_IMUX0_7", + "CMT_TOP_IMUX0_8" + ], + [ + "CMT_FIFO_L_IMUX40_10", + "CMT_TOP_IMUX40_11" + ], + [ + "CMT_FIFO_L_IMUX5_2", + "CMT_TOP_IMUX5_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "CMT_TOP_OCLKDIV_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_6", + "CMT_TOP_LOGIC_OUTS_L_B21_7" + ], + [ + "CMT_FIFO_EE4A3_6", + "CMT_TOP_EE4A3_7" + ], + [ + "CMT_FIFO_SE4BEG2_2", + "CMT_TOP_SE4BEG2_3" + ], + [ + "CMT_FIFO_L_IMUX38_9", + "CMT_TOP_IMUX38_10" + ], + [ + "CMT_FIFO_SW4A3_5", + "CMT_TOP_SW4A3_6" + ], + [ + "CMT_FIFO_SE4C3_7", + "CMT_TOP_SE4C3_8" + ], + [ + "CMT_FIFO_L_FAN4_9", + "CMT_TOP_FAN4_10" + ], + [ + "CMT_FIFO_WW2END0_4", + "CMT_TOP_WW2END0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_7", + "CMT_TOP_LOGIC_OUTS_L_B7_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_9", + "CMT_TOP_LOGIC_OUTS_L_B12_10" + ], + [ + "CMT_FIFO_L_IMUX18_11", + "CMT_TOP_IMUX18_12" + ], + [ + "CMT_FIFO_L_IMUX31_6", + "CMT_TOP_IMUX31_7" + ], + [ + "CMT_FIFO_LH1_0", + "CMT_TOP_LH1_1" + ], + [ + "CMT_FIFO_WW4END2_2", + "CMT_TOP_WW4END2_3" + ], + [ + "CMT_FIFO_L_IMUX45_9", + "CMT_TOP_IMUX45_10" + ], + [ + "CMT_FIFO_L_IMUX34_1", + "CMT_TOP_IMUX34_2" + ], + [ + "CMT_FIFO_L_FAN0_6", + "CMT_TOP_FAN0_7" + ], + [ + "CMT_FIFO_L_BYP3_11", + "CMT_TOP_BYP3_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_3", + "CMT_TOP_LOGIC_OUTS_L_B13_4" + ], + [ + "CMT_FIFO_WR1END1_6", + "CMT_TOP_WR1END1_7" + ], + [ + "CMT_FIFO_SE4BEG1_2", + "CMT_TOP_SE4BEG1_3" + ], + [ + "CMT_FIFO_WW4A0_7", + "CMT_TOP_WW4A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_5", + "CMT_TOP_LOGIC_OUTS_L_B20_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "CMT_TOP_OCLK_9" + ], + [ + "CMT_FIFO_L_IMUX19_8", + "CMT_TOP_IMUX19_9" + ], + [ + "CMT_FIFO_NE2A3_0", + "CMT_TOP_NE2A3_1" + ], + [ + "CMT_FIFO_SW4END2_4", + "CMT_TOP_SW4END2_5" + ], + [ + "CMT_FIFO_NW4END1_8", + "CMT_TOP_NW4END1_9" + ], + [ + "CMT_FIFO_SE2A1_9", + "CMT_TOP_SE2A1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_9", + "CMT_TOP_LOGIC_OUTS_L_B9_10" + ], + [ + "CMT_FIFO_WW2A1_11", + "CMT_TOP_WW2A1_12" + ], + [ + "CMT_FIFO_LH12_9", + "CMT_TOP_LH12_10" + ], + [ + "CMT_FIFO_LH8_2", + "CMT_TOP_LH8_3" + ], + [ + "CMT_FIFO_L_IMUX31_5", + "CMT_TOP_IMUX31_6" + ], + [ + "CMT_FIFO_L_BYP3_2", + "CMT_TOP_BYP3_3" + ], + [ + "CMT_FIFO_NE4C2_6", + "CMT_TOP_NE4C2_7" + ], + [ + "CMT_FIFO_LH9_0", + "CMT_TOP_LH9_1" + ], + [ + "CMT_FIFO_SW2A3_5", + "CMT_TOP_SW2A3_6" + ], + [ + "CMT_FIFO_L_IMUX11_11", + "CMT_TOP_IMUX11_12" + ], + [ + "CMT_FIFO_WW4C3_4", + "CMT_TOP_WW4C3_5" + ], + [ + "CMT_FIFO_WW4C3_10", + "CMT_TOP_WW4C3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_5", + "CMT_TOP_LOGIC_OUTS_L_B4_6" + ], + [ + "CMT_FIFO_LH6_9", + "CMT_TOP_LH6_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_4", + "CMT_TOP_LOGIC_OUTS_L_B23_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_2", + "CMT_TOP_LOGIC_OUTS_L_B5_3" + ], + [ + "CMT_FIFO_NE2A0_2", + "CMT_TOP_NE2A0_3" + ], + [ + "CMT_FIFO_NE4C0_9", + "CMT_TOP_NE4C0_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_8", + "CMT_TOP_LOGIC_OUTS_L_B10_9" + ], + [ + "CMT_FIFO_L_IMUX10_10", + "CMT_TOP_IMUX10_11" + ], + [ + "CMT_FIFO_SW4END1_9", + "CMT_TOP_SW4END1_10" + ], + [ + "CMT_FIFO_L_IMUX7_10", + "CMT_TOP_IMUX7_11" + ], + [ + "CMT_FIFO_L_IMUX20_3", + "CMT_TOP_IMUX20_4" + ], + [ + "CMT_FIFO_EE4BEG1_5", + "CMT_TOP_EE4BEG1_6" + ], + [ + "CMT_FIFO_NW2A1_2", + "CMT_TOP_NW2A1_3" + ], + [ + "CMT_FIFO_WW4B3_9", + "CMT_TOP_WW4B3_10" + ], + [ + "CMT_FIFO_LH10_3", + "CMT_TOP_LH10_4" + ], + [ + "CMT_FIFO_NE4C3_9", + "CMT_TOP_NE4C3_10" + ], + [ + "CMT_FIFO_EL1BEG0_5", + "CMT_TOP_EL1BEG0_6" + ], + [ + "CMT_FIFO_SW2A1_4", + "CMT_TOP_SW2A1_5" + ], + [ + "CMT_FIFO_L_IMUX43_7", + "CMT_TOP_IMUX43_8" + ], + [ + "CMT_FIFO_L_BYP6_2", + "CMT_TOP_BYP6_3" + ], + [ + "CMT_FIFO_WR1END3_0", + "CMT_TOP_WR1END3_1" + ], + [ + "CMT_FIFO_EE4C1_0", + "CMT_TOP_EE4C1_1" + ], + [ + "CMT_FIFO_LH6_11", + "CMT_TOP_LH6_12" + ], + [ + "CMT_FIFO_SE2A2_9", + "CMT_TOP_SE2A2_10" + ], + [ + "FIFO_DQS_IOTOPHASER_1", + "CMT_MMCM_DQS_TO_PHASERA" + ], + [ + "CMT_FIFO_L_IMUX0_3", + "CMT_TOP_IMUX0_4" + ], + [ + "CMT_FIFO_LH11_3", + "CMT_TOP_LH11_4" + ], + [ + "CMT_FIFO_LH2_10", + "CMT_TOP_LH2_11" + ], + [ + "CMT_FIFO_L_IMUX10_8", + "CMT_TOP_IMUX10_9" + ], + [ + "CMT_FIFO_WL1END1_9", + "CMT_TOP_WL1END1_10" + ], + [ + "CMT_FIFO_WW4C3_2", + "CMT_TOP_WW4C3_3" + ], + [ + "CMT_FIFO_L_IMUX37_6", + "CMT_TOP_IMUX37_7" + ], + [ + "CMT_FIFO_L_IMUX44_1", + "CMT_TOP_IMUX44_2" + ], + [ + "CMT_FIFO_EE2BEG2_7", + "CMT_TOP_EE2BEG2_8" + ], + [ + "CMT_FIFO_NE2A0_11", + "CMT_TOP_NE2A0_12" + ], + [ + "CMT_FIFO_L_IMUX41_6", + "CMT_TOP_IMUX41_7" + ], + [ + "CMT_FIFO_SE4BEG3_4", + "CMT_TOP_SE4BEG3_5" + ], + [ + "CMT_FIFO_L_IMUX26_7", + "CMT_TOP_IMUX26_8" + ], + [ + "CMT_FIFO_NE4BEG3_11", + "CMT_TOP_NE4BEG3_12" + ], + [ + "CMT_FIFO_L_IMUX12_11", + "CMT_TOP_IMUX12_12" + ], + [ + "CMT_FIFO_SW2A0_6", + "CMT_TOP_SW2A0_7" + ], + [ + "CMT_FIFO_EE4B3_5", + "CMT_TOP_EE4B3_6" + ], + [ + "CMT_FIFO_L_IMUX33_3", + "CMT_TOP_IMUX33_4" + ], + [ + "CMT_FIFO_EE2A2_4", + "CMT_TOP_EE2A2_5" + ], + [ + "CMT_FIFO_L_IMUX32_1", + "CMT_TOP_IMUX32_2" + ], + [ + "CMT_FIFO_WW4B3_1", + "CMT_TOP_WW4B3_2" + ], + [ + "CMT_FIFO_L_IMUX9_1", + "CMT_TOP_IMUX9_2" + ], + [ + "CMT_FIFO_SW4END2_8", + "CMT_TOP_SW4END2_9" + ], + [ + "CMT_FIFO_NW2A3_9", + "CMT_TOP_NW2A3_10" + ], + [ + "CMT_FIFO_WW4C2_4", + "CMT_TOP_WW4C2_5" + ], + [ + "CMT_FIFO_WW2END1_4", + "CMT_TOP_WW2END1_5" + ], + [ + "CMT_FIFO_SE4C0_6", + "CMT_TOP_SE4C0_7" + ], + [ + "CMT_FIFO_LH4_8", + "CMT_TOP_LH4_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_10", + "CMT_TOP_LOGIC_OUTS_L_B19_11" + ], + [ + "CMT_FIFO_EE4BEG2_5", + "CMT_TOP_EE4BEG2_6" + ], + [ + "CMT_FIFO_L_IMUX17_3", + "CMT_TOP_IMUX17_4" + ], + [ + "CMT_FIFO_WW4END3_7", + "CMT_TOP_WW4END3_8" + ], + [ + "CMT_FIFO_SE4C2_6", + "CMT_TOP_SE4C2_7" + ], + [ + "CMT_FIFO_L_IMUX47_10", + "CMT_TOP_IMUX47_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_6", + "CMT_TOP_LOGIC_OUTS_L_B10_7" + ], + [ + "CMT_FIFO_L_IMUX13_7", + "CMT_TOP_IMUX13_8" + ], + [ + "CMT_FIFO_ER1BEG0_10", + "CMT_TOP_ER1BEG0_11" + ], + [ + "CMT_FIFO_LH9_3", + "CMT_TOP_LH9_4" + ], + [ + "CMT_FIFO_L_IMUX45_11", + "CMT_TOP_IMUX45_12" + ], + [ + "CMT_FIFO_L_BYP6_8", + "CMT_TOP_BYP6_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_8", + "CMT_TOP_LOGIC_OUTS_L_B9_9" + ], + [ + "CMT_FIFO_WW4B3_8", + "CMT_TOP_WW4B3_9" + ], + [ + "CMT_FIFO_L_IMUX29_7", + "CMT_TOP_IMUX29_8" + ], + [ + "CMT_FIFO_ER1BEG3_5", + "CMT_TOP_ER1BEG3_6" + ], + [ + "CMT_FIFO_NW2A1_4", + "CMT_TOP_NW2A1_5" + ], + [ + "CMT_FIFO_L_IMUX35_7", + "CMT_TOP_IMUX35_8" + ], + [ + "CMT_FIFO_WW4A2_2", + "CMT_TOP_WW4A2_3" + ], + [ + "CMT_FIFO_L_IMUX10_9", + "CMT_TOP_IMUX10_10" + ], + [ + "CMT_FIFO_WL1END2_3", + "CMT_TOP_WL1END2_4" + ], + [ + "CMT_FIFO_WR1END1_0", + "CMT_TOP_WR1END1_1" + ], + [ + "CMT_FIFO_NE4C0_11", + "CMT_TOP_NE4C0_12" + ], + [ + "CMT_FIFO_ER1BEG0_8", + "CMT_TOP_ER1BEG0_9" + ], + [ + "CMT_FIFO_NW2A1_0", + "CMT_TOP_NW2A1_1" + ], + [ + "CMT_FIFO_L_IMUX19_2", + "CMT_TOP_IMUX19_3" + ], + [ + "CMT_FIFO_LH12_1", + "CMT_TOP_LH12_2" + ], + [ + "CMT_FIFO_WW2END2_1", + "CMT_TOP_WW2END2_2" + ], + [ + "CMT_FIFO_L_CLK0_0", + "CMT_TOP_CLK0_1" + ], + [ + "CMT_FIFO_L_IMUX21_11", + "CMT_TOP_IMUX21_12" + ], + [ + "CMT_FIFO_LH8_11", + "CMT_TOP_LH8_12" + ], + [ + "CMT_FIFO_L_IMUX32_9", + "CMT_TOP_IMUX32_10" + ], + [ + "CMT_FIFO_WW4B1_8", + "CMT_TOP_WW4B1_9" + ], + [ + "CMT_FIFO_NE2A2_10", + "CMT_TOP_NE2A2_11" + ], + [ + "CMT_FIFO_EE4BEG3_1", + "CMT_TOP_EE4BEG3_2" + ], + [ + "CMT_FIFO_L_BYP2_9", + "CMT_TOP_BYP2_10" + ], + [ + "CMT_FIFO_L_IMUX41_8", + "CMT_TOP_IMUX41_9" + ], + [ + "CMT_FIFO_L_IMUX24_7", + "CMT_TOP_IMUX24_8" + ], + [ + "CMT_FIFO_ER1BEG1_3", + "CMT_TOP_ER1BEG1_4" + ], + [ + "CMT_FIFO_L_FAN7_2", + "CMT_TOP_FAN7_3" + ], + [ + "CMT_FIFO_SW4A3_7", + "CMT_TOP_SW4A3_8" + ], + [ + "CMT_FIFO_L_IMUX5_0", + "CMT_TOP_IMUX5_1" + ], + [ + "CMT_FIFO_WW4END1_5", + "CMT_TOP_WW4END1_6" + ], + [ + "CMT_FIFO_SE4BEG2_11", + "CMT_TOP_SE4BEG2_12" + ], + [ + "CMT_FIFO_WW2END2_8", + "CMT_TOP_WW2END2_9" + ], + [ + "CMT_FIFO_WW4B0_1", + "CMT_TOP_WW4B0_2" + ], + [ + "CMT_FIFO_EE2A2_3", + "CMT_TOP_EE2A2_4" + ], + [ + "CMT_FIFO_EE4A2_0", + "CMT_TOP_EE4A2_1" + ], + [ + "CMT_FIFO_SW4END2_0", + "CMT_TOP_SW4END2_1" + ], + [ + "CMT_FIFO_SE4C0_11", + "CMT_TOP_SE4C0_12" + ], + [ + "CMT_FIFO_EE4A0_10", + "CMT_TOP_EE4A0_11" + ], + [ + "CMT_FIFO_L_IMUX3_5", + "CMT_TOP_IMUX3_6" + ], + [ + "CMT_FIFO_NW4A1_2", + "CMT_TOP_NW4A1_3" + ], + [ + "CMT_FIFO_WR1END2_9", + "CMT_TOP_WR1END2_10" + ], + [ + "CMT_FIFO_SE4C1_1", + "CMT_TOP_SE4C1_2" + ], + [ + "CMT_FIFO_L_IMUX23_2", + "CMT_TOP_IMUX23_3" + ], + [ + "CMT_FIFO_WW2A0_10", + "CMT_TOP_WW2A0_11" + ], + [ + "CMT_FIFO_ER1BEG2_11", + "CMT_TOP_ER1BEG2_12" + ], + [ + "CMT_FIFO_EE4BEG3_7", + "CMT_TOP_EE4BEG3_8" + ], + [ + "CMT_FIFO_WW4B0_10", + "CMT_TOP_WW4B0_11" + ], + [ + "CMT_FIFO_SE4BEG3_5", + "CMT_TOP_SE4BEG3_6" + ], + [ + "CMT_FIFO_EE2A1_5", + "CMT_TOP_EE2A1_6" + ], + [ + "CMT_FIFO_EE4A0_7", + "CMT_TOP_EE4A0_8" + ], + [ + "CMT_FIFO_L_IMUX14_0", + "CMT_TOP_IMUX14_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "CMT_TOP_ICLK_10" + ], + [ + "CMT_FIFO_L_IMUX46_3", + "CMT_TOP_IMUX46_4" + ], + [ + "CMT_FIFO_ER1BEG1_10", + "CMT_TOP_ER1BEG1_11" + ], + [ + "CMT_FIFO_EL1BEG2_1", + "CMT_TOP_EL1BEG2_2" + ], + [ + "CMT_FIFO_LH2_4", + "CMT_TOP_LH2_5" + ], + [ + "CMT_FIFO_L_BYP3_7", + "CMT_TOP_BYP3_8" + ], + [ + "CMT_FIFO_L_BYP7_0", + "CMT_TOP_BYP7_1" + ], + [ + "CMT_FIFO_WR1END2_1", + "CMT_TOP_WR1END2_2" + ], + [ + "CMT_FIFO_SE2A3_4", + "CMT_TOP_SE2A3_5" + ], + [ + "CMT_FIFO_EE2BEG0_4", + "CMT_TOP_EE2BEG0_5" + ], + [ + "CMT_FIFO_L_FAN1_2", + "CMT_TOP_FAN1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_3", + "CMT_TOP_LOGIC_OUTS_L_B20_4" + ], + [ + "CMT_FIFO_L_IMUX16_2", + "CMT_TOP_IMUX16_3" + ], + [ + "CMT_FIFO_EE4BEG3_10", + "CMT_TOP_EE4BEG3_11" + ], + [ + "CMT_FIFO_NW2A1_3", + "CMT_TOP_NW2A1_4" + ], + [ + "CMT_FIFO_L_IMUX2_4", + "CMT_TOP_IMUX2_5" + ], + [ + "CMT_FIFO_L_IMUX12_9", + "CMT_TOP_IMUX12_10" + ], + [ + "CMT_FIFO_ER1BEG0_4", + "CMT_TOP_ER1BEG0_5" + ], + [ + "CMT_FIFO_L_BYP0_8", + "CMT_TOP_BYP0_9" + ], + [ + "CMT_FIFO_L_CTRL0_1", + "CMT_TOP_CTRL0_2" + ], + [ + "CMT_FIFO_L_FAN0_9", + "CMT_TOP_FAN0_10" + ], + [ + "CMT_FIFO_EE4B1_11", + "CMT_TOP_EE4B1_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_9", + "CMT_TOP_LOGIC_OUTS_L_B19_10" + ], + [ + "CMT_FIFO_L_IMUX34_5", + "CMT_TOP_IMUX34_6" + ], + [ + "CMT_FIFO_L_IMUX41_10", + "CMT_TOP_IMUX41_11" + ], + [ + "CMT_FIFO_LH5_10", + "CMT_TOP_LH5_11" + ], + [ + "CMT_FIFO_ER1BEG2_6", + "CMT_TOP_ER1BEG2_7" + ], + [ + "CMT_FIFO_L_IMUX27_8", + "CMT_TOP_IMUX27_9" + ], + [ + "CMT_FIFO_WW2A1_2", + "CMT_TOP_WW2A1_3" + ], + [ + "CMT_FIFO_NE4BEG1_11", + "CMT_TOP_NE4BEG1_12" + ], + [ + "CMT_FIFO_MONITOR_N_10", + "CMT_TOP_MONITOR_N_11" + ], + [ + "CMT_FIFO_L_CLK1_10", + "CMT_TOP_CLK1_11" + ], + [ + "CMT_FIFO_L_IMUX15_2", + "CMT_TOP_IMUX15_3" + ], + [ + "CMT_FIFO_EL1BEG0_7", + "CMT_TOP_EL1BEG0_8" + ], + [ + "CMT_FIFO_EE4BEG0_0", + "CMT_TOP_EE4BEG0_1" + ], + [ + "CMT_FIFO_L_BYP1_3", + "CMT_TOP_BYP1_4" + ], + [ + "CMT_FIFO_WW2A1_5", + "CMT_TOP_WW2A1_6" + ], + [ + "CMT_FIFO_EE4A2_10", + "CMT_TOP_EE4A2_11" + ], + [ + "CMT_FIFO_SE4BEG1_0", + "CMT_TOP_SE4BEG1_1" + ], + [ + "CMT_FIFO_L_FAN4_4", + "CMT_TOP_FAN4_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_5", + "CMT_TOP_LOGIC_OUTS_L_B8_6" + ], + [ + "CMT_FIFO_EE4A3_4", + "CMT_TOP_EE4A3_5" + ], + [ + "CMT_FIFO_L_FAN5_3", + "CMT_TOP_FAN5_4" + ], + [ + "CMT_FIFO_LH11_0", + "CMT_TOP_LH11_1" + ], + [ + "CMT_FIFO_L_IMUX3_9", + "CMT_TOP_IMUX3_10" + ], + [ + "CMT_FIFO_EE4BEG3_8", + "CMT_TOP_EE4BEG3_9" + ], + [ + "CMT_FIFO_L_IMUX22_8", + "CMT_TOP_IMUX22_9" + ], + [ + "CMT_FIFO_LH6_7", + "CMT_TOP_LH6_8" + ], + [ + "CMT_FIFO_L_FAN6_11", + "CMT_TOP_FAN6_12" + ], + [ + "CMT_FIFO_WW4B0_4", + "CMT_TOP_WW4B0_5" + ], + [ + "CMT_FIFO_L_IMUX10_0", + "CMT_TOP_IMUX10_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_9", + "CMT_TOP_LOGIC_OUTS_L_B5_10" + ], + [ + "CMT_FIFO_EE4A3_5", + "CMT_TOP_EE4A3_6" + ], + [ + "CMT_FIFO_ER1BEG1_0", + "CMT_TOP_ER1BEG1_1" + ], + [ + "CMT_FIFO_WW4C0_5", + "CMT_TOP_WW4C0_6" + ], + [ + "CMT_FIFO_L_IMUX14_1", + "CMT_TOP_IMUX14_2" + ], + [ + "CMT_FIFO_NE4C3_6", + "CMT_TOP_NE4C3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_8", + "CMT_TOP_LOGIC_OUTS_L_B15_9" + ], + [ + "CMT_FIFO_WW2END2_2", + "CMT_TOP_WW2END2_3" + ], + [ + "CMT_FIFO_EE2BEG3_1", + "CMT_TOP_EE2BEG3_2" + ], + [ + "CMT_FIFO_NE4C0_4", + "CMT_TOP_NE4C0_5" + ], + [ + "CMT_FIFO_NW4A0_10", + "CMT_TOP_NW4A0_11" + ], + [ + "CMT_FIFO_L_IMUX27_11", + "CMT_TOP_IMUX27_12" + ], + [ + "CMT_FIFO_NW4END0_7", + "CMT_TOP_NW4END0_8" + ], + [ + "CMT_FIFO_SE4BEG0_9", + "CMT_TOP_SE4BEG0_10" + ], + [ + "CMT_FIFO_WW2A2_11", + "CMT_TOP_WW2A2_12" + ], + [ + "CMT_FIFO_L_BYP3_0", + "CMT_TOP_BYP3_1" + ], + [ + "CMT_FIFO_L_IMUX17_4", + "CMT_TOP_IMUX17_5" + ], + [ + "CMT_FIFO_LH8_3", + "CMT_TOP_LH8_4" + ], + [ + "CMT_FIFO_SW4END0_3", + "CMT_TOP_SW4END0_4" + ], + [ + "CMT_FIFO_NW2A3_1", + "CMT_TOP_NW2A3_2" + ], + [ + "CMT_FIFO_L_IMUX27_7", + "CMT_TOP_IMUX27_8" + ], + [ + "CMT_FIFO_EE4A1_0", + "CMT_TOP_EE4A1_1" + ], + [ + "CMT_FIFO_WW4A2_3", + "CMT_TOP_WW4A2_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "CMT_TOP_ICLK_7" + ], + [ + "CMT_FIFO_L_IMUX0_2", + "CMT_TOP_IMUX0_3" + ], + [ + "CMT_FIFO_WW4C1_2", + "CMT_TOP_WW4C1_3" + ], + [ + "CMT_FIFO_EE4B1_4", + "CMT_TOP_EE4B1_5" + ], + [ + "CMT_FIFO_WW2A1_10", + "CMT_TOP_WW2A1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_4", + "CMT_TOP_LOGIC_OUTS_L_B13_5" + ], + [ + "CMT_FIFO_SE2A1_5", + "CMT_TOP_SE2A1_6" + ], + [ + "CMT_FIFO_NE4BEG0_10", + "CMT_TOP_NE4BEG0_11" + ], + [ + "CMT_FIFO_EE4C1_9", + "CMT_TOP_EE4C1_10" + ], + [ + "CMT_FIFO_LH11_4", + "CMT_TOP_LH11_5" + ], + [ + "CMT_FIFO_WW4END0_1", + "CMT_TOP_WW4END0_2" + ], + [ + "CMT_FIFO_EL1BEG0_10", + "CMT_TOP_EL1BEG0_11" + ], + [ + "CMT_FIFO_EE4C2_2", + "CMT_TOP_EE4C2_3" + ], + [ + "CMT_FIFO_L_FAN3_11", + "CMT_TOP_FAN3_12" + ], + [ + "CMT_FIFO_L_BYP0_11", + "CMT_TOP_BYP0_12" + ], + [ + "CMT_FIFO_L_IMUX38_4", + "CMT_TOP_IMUX38_5" + ], + [ + "CMT_FIFO_NE2A0_3", + "CMT_TOP_NE2A0_4" + ], + [ + "CMT_FIFO_LH5_3", + "CMT_TOP_LH5_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_4" + ], + [ + "CMT_FIFO_NE2A2_1", + "CMT_TOP_NE2A2_2" + ], + [ + "CMT_FIFO_LH2_11", + "CMT_TOP_LH2_12" + ], + [ + "CMT_FIFO_L_FAN6_4", + "CMT_TOP_FAN6_5" + ], + [ + "CMT_FIFO_EE4B3_4", + "CMT_TOP_EE4B3_5" + ], + [ + "CMT_FIFO_SW4END2_3", + "CMT_TOP_SW4END2_4" + ], + [ + "CMT_FIFO_L_CLK0_11", + "CMT_TOP_CLK0_12" + ], + [ + "CMT_FIFO_EE4B1_3", + "CMT_TOP_EE4B1_4" + ], + [ + "CMT_FIFO_L_FAN3_2", + "CMT_TOP_FAN3_3" + ], + [ + "CMT_FIFO_SW4A1_8", + "CMT_TOP_SW4A1_9" + ], + [ + "CMT_FIFO_LH8_9", + "CMT_TOP_LH8_10" + ], + [ + "CMT_FIFO_L_BYP4_11", + "CMT_TOP_BYP4_12" + ], + [ + "CMT_FIFO_NE2A1_1", + "CMT_TOP_NE2A1_2" + ], + [ + "CMT_FIFO_EE2BEG2_6", + "CMT_TOP_EE2BEG2_7" + ], + [ + "CMT_FIFO_WW2A2_4", + "CMT_TOP_WW2A2_5" + ], + [ + "CMT_FIFO_WW2END1_7", + "CMT_TOP_WW2END1_8" + ], + [ + "CMT_FIFO_L_BYP0_7", + "CMT_TOP_BYP0_8" + ], + [ + "CMT_FIFO_SW4END2_11", + "CMT_TOP_SW4END2_12" + ], + [ + "CMT_FIFO_NE4C2_10", + "CMT_TOP_NE4C2_11" + ], + [ + "CMT_FIFO_L_FAN5_11", + "CMT_TOP_FAN5_12" + ], + [ + "CMT_FIFO_SW2A1_1", + "CMT_TOP_SW2A1_2" + ], + [ + "CMT_FIFO_WW4END0_11", + "CMT_TOP_WW4END0_12" + ], + [ + "CMT_FIFO_SE4C1_3", + "CMT_TOP_SE4C1_4" + ], + [ + "CMT_FIFO_NE4BEG1_7", + "CMT_TOP_NE4BEG1_8" + ], + [ + "CMT_FIFO_NE2A0_4", + "CMT_TOP_NE2A0_5" + ], + [ + "CMT_FIFO_NE2A1_6", + "CMT_TOP_NE2A1_7" + ], + [ + "CMT_FIFO_WW2A2_3", + "CMT_TOP_WW2A2_4" + ], + [ + "CMT_FIFO_WL1END3_9", + "CMT_TOP_WL1END3_10" + ], + [ + "CMT_FIFO_L_IMUX27_5", + "CMT_TOP_IMUX27_6" + ], + [ + "CMT_FIFO_L_IMUX38_8", + "CMT_TOP_IMUX38_9" + ], + [ + "CMT_FIFO_WW4C3_9", + "CMT_TOP_WW4C3_10" + ], + [ + "CMT_FIFO_EL1BEG2_2", + "CMT_TOP_EL1BEG2_3" + ], + [ + "CMT_FIFO_SE4C0_7", + "CMT_TOP_SE4C0_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "CMT_TOP_ICLK_12" + ], + [ + "CMT_FIFO_EE4BEG2_3", + "CMT_TOP_EE4BEG2_4" + ], + [ + "CMT_FIFO_L_IMUX39_8", + "CMT_TOP_IMUX39_9" + ], + [ + "CMT_FIFO_WW4A1_10", + "CMT_TOP_WW4A1_11" + ], + [ + "CMT_FIFO_L_IMUX1_7", + "CMT_TOP_IMUX1_8" + ], + [ + "CMT_FIFO_WW4C2_0", + "CMT_TOP_WW4C2_1" + ], + [ + "CMT_FIFO_EE2A2_6", + "CMT_TOP_EE2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_0", + "CMT_TOP_LOGIC_OUTS_L_B20_1" + ], + [ + "CMT_FIFO_L_IMUX11_4", + "CMT_TOP_IMUX11_5" + ], + [ + "CMT_FIFO_L_IMUX29_8", + "CMT_TOP_IMUX29_9" + ], + [ + "CMT_FIFO_L_BYP5_1", + "CMT_TOP_BYP5_2" + ], + [ + "CMT_FIFO_L_IMUX23_11", + "CMT_TOP_IMUX23_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_5", + "CMT_TOP_LOGIC_OUTS_L_B12_6" + ], + [ + "CMT_FIFO_LH4_1", + "CMT_TOP_LH4_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_0", + "CMT_TOP_LOGIC_OUTS_L_B21_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_7", + "CMT_TOP_LOGIC_OUTS_L_B16_8" + ], + [ + "CMT_FIFO_EE4A0_8", + "CMT_TOP_EE4A0_9" + ], + [ + "CMT_FIFO_L_IMUX17_0", + "CMT_TOP_IMUX17_1" + ], + [ + "CMT_FIFO_NE4BEG3_2", + "CMT_TOP_NE4BEG3_3" + ], + [ + "CMT_FIFO_WW2A0_2", + "CMT_TOP_WW2A0_3" + ], + [ + "CMT_FIFO_WW4B1_10", + "CMT_TOP_WW4B1_11" + ], + [ + "CMT_FIFO_LH12_4", + "CMT_TOP_LH12_5" + ], + [ + "CMT_FIFO_EE4B0_5", + "CMT_TOP_EE4B0_6" + ], + [ + "CMT_FIFO_L_IMUX25_11", + "CMT_TOP_IMUX25_12" + ], + [ + "CMT_FIFO_NE2A2_6", + "CMT_TOP_NE2A2_7" + ], + [ + "CMT_FIFO_WW4C2_1", + "CMT_TOP_WW4C2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_3", + "CMT_TOP_LOGIC_OUTS_L_B17_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_6", + "CMT_TOP_LOGIC_OUTS_L_B3_7" + ], + [ + "CMT_FIFO_WW4B0_0", + "CMT_TOP_WW4B0_1" + ], + [ + "CMT_FIFO_EE4C1_7", + "CMT_TOP_EE4C1_8" + ], + [ + "CMT_FIFO_L_IMUX5_3", + "CMT_TOP_IMUX5_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_8", + "CMT_TOP_LOGIC_OUTS_L_B18_9" + ], + [ + "CMT_FIFO_ER1BEG2_3", + "CMT_TOP_ER1BEG2_4" + ], + [ + "CMT_FIFO_EL1BEG0_8", + "CMT_TOP_EL1BEG0_9" + ], + [ + "CMT_FIFO_WR1END0_9", + "CMT_TOP_WR1END0_10" + ], + [ + "CMT_FIFO_WW2A0_7", + "CMT_TOP_WW2A0_8" + ], + [ + "CMT_FIFO_ER1BEG0_6", + "CMT_TOP_ER1BEG0_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "CMT_TOP_OCLKDIV_5" + ], + [ + "CMT_FIFO_L_BYP1_5", + "CMT_TOP_BYP1_6" + ], + [ + "CMT_FIFO_L_IMUX14_5", + "CMT_TOP_IMUX14_6" + ], + [ + "CMT_FIFO_WR1END0_4", + "CMT_TOP_WR1END0_5" + ], + [ + "CMT_FIFO_L_IMUX16_4", + "CMT_TOP_IMUX16_5" + ], + [ + "CMT_FIFO_LH9_9", + "CMT_TOP_LH9_10" + ], + [ + "CMT_FIFO_L_IMUX19_10", + "CMT_TOP_IMUX19_11" + ], + [ + "CMT_FIFO_EE4A3_7", + "CMT_TOP_EE4A3_8" + ], + [ + "CMT_FIFO_L_FAN7_8", + "CMT_TOP_FAN7_9" + ], + [ + "CMT_FIFO_L_IMUX7_9", + "CMT_TOP_IMUX7_10" + ], + [ + "CMT_FIFO_L_IMUX15_4", + "CMT_TOP_IMUX15_5" + ], + [ + "CMT_FIFO_WW4B1_3", + "CMT_TOP_WW4B1_4" + ], + [ + "CMT_FIFO_EE2A0_9", + "CMT_TOP_EE2A0_10" + ], + [ + "CMT_FIFO_L_FAN7_10", + "CMT_TOP_FAN7_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_2", + "CMT_TOP_LOGIC_OUTS_L_B0_3" + ], + [ + "CMT_FIFO_WW2END0_9", + "CMT_TOP_WW2END0_10" + ], + [ + "CMT_FIFO_WW4C0_0", + "CMT_TOP_WW4C0_1" + ], + [ + "CMT_FIFO_L_IMUX9_0", + "CMT_TOP_IMUX9_1" + ], + [ + "CMT_FIFO_NE4C1_11", + "CMT_TOP_NE4C1_12" + ], + [ + "CMT_FIFO_L_FAN0_10", + "CMT_TOP_FAN0_11" + ], + [ + "CMT_FIFO_L_BYP1_11", + "CMT_TOP_BYP1_12" + ], + [ + "CMT_FIFO_NE4BEG1_1", + "CMT_TOP_NE4BEG1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_0", + "CMT_TOP_LOGIC_OUTS_L_B18_1" + ], + [ + "CMT_FIFO_NW2A1_10", + "CMT_TOP_NW2A1_11" + ], + [ + "CMT_FIFO_EE2A1_8", + "CMT_TOP_EE2A1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_6", + "CMT_TOP_LOGIC_OUTS_L_B15_7" + ], + [ + "CMT_FIFO_L_FAN4_3", + "CMT_TOP_FAN4_4" + ], + [ + "CMT_FIFO_WL1END0_0", + "CMT_TOP_WL1END0_1" + ], + [ + "CMT_FIFO_ER1BEG1_9", + "CMT_TOP_ER1BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX44_6", + "CMT_TOP_IMUX44_7" + ], + [ + "CMT_FIFO_EE2BEG3_2", + "CMT_TOP_EE2BEG3_3" + ], + [ + "CMT_FIFO_L_BYP1_8", + "CMT_TOP_BYP1_9" + ], + [ + "CMT_FIFO_NW4END1_10", + "CMT_TOP_NW4END1_11" + ], + [ + "CMT_FIFO_WR1END0_10", + "CMT_TOP_WR1END0_11" + ], + [ + "CMT_FIFO_L_IMUX2_5", + "CMT_TOP_IMUX2_6" + ], + [ + "CMT_FIFO_L_CTRL1_0", + "CMT_TOP_CTRL1_1" + ], + [ + "CMT_FIFO_WW4B1_7", + "CMT_TOP_WW4B1_8" + ], + [ + "CMT_FIFO_L_BYP7_5", + "CMT_TOP_BYP7_6" + ], + [ + "CMT_FIFO_SE2A3_0", + "CMT_TOP_SE2A3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_1", + "CMT_TOP_LOGIC_OUTS_L_B20_2" + ], + [ + "CMT_FIFO_EE2BEG3_0", + "CMT_TOP_EE2BEG3_1" + ], + [ + "CMT_FIFO_WR1END3_3", + "CMT_TOP_WR1END3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_0", + "CMT_TOP_LOGIC_OUTS_L_B12_1" + ], + [ + "CMT_FIFO_L_IMUX16_6", + "CMT_TOP_IMUX16_7" + ], + [ + "CMT_FIFO_L_FAN4_8", + "CMT_TOP_FAN4_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_0", + "CMT_TOP_LOGIC_OUTS_L_B8_1" + ], + [ + "CMT_FIFO_EE4C1_3", + "CMT_TOP_EE4C1_4" + ], + [ + "CMT_FIFO_WL1END3_11", + "CMT_TOP_WL1END3_12" + ], + [ + "CMT_FIFO_LH2_5", + "CMT_TOP_LH2_6" + ], + [ + "CMT_FIFO_NE4BEG0_5", + "CMT_TOP_NE4BEG0_6" + ], + [ + "CMT_FIFO_EE2BEG2_2", + "CMT_TOP_EE2BEG2_3" + ], + [ + "CMT_FIFO_WL1END1_2", + "CMT_TOP_WL1END1_3" + ], + [ + "CMT_FIFO_EL1BEG3_9", + "CMT_TOP_EL1BEG3_10" + ], + [ + "CMT_FIFO_NW4A1_4", + "CMT_TOP_NW4A1_5" + ], + [ + "CMT_FIFO_L_CLK0_5", + "CMT_TOP_CLK0_6" + ], + [ + "CMT_FIFO_EE2BEG1_3", + "CMT_TOP_EE2BEG1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_2", + "CMT_TOP_LOGIC_OUTS_L_B11_3" + ], + [ + "CMT_FIFO_L_FAN3_9", + "CMT_TOP_FAN3_10" + ], + [ + "CMT_FIFO_L_CLK1_1", + "CMT_TOP_CLK1_2" + ], + [ + "CMT_FIFO_EE4C1_8", + "CMT_TOP_EE4C1_9" + ], + [ + "CMT_FIFO_L_IMUX7_2", + "CMT_TOP_IMUX7_3" + ], + [ + "CMT_FIFO_L_IMUX10_7", + "CMT_TOP_IMUX10_8" + ], + [ + "CMT_FIFO_WW4END3_6", + "CMT_TOP_WW4END3_7" + ], + [ + "CMT_FIFO_L_IMUX24_2", + "CMT_TOP_IMUX24_3" + ], + [ + "CMT_FIFO_NE4C1_7", + "CMT_TOP_NE4C1_8" + ], + [ + "CMT_FIFO_L_IMUX12_6", + "CMT_TOP_IMUX12_7" + ], + [ + "CMT_FIFO_L_IMUX26_6", + "CMT_TOP_IMUX26_7" + ], + [ + "CMT_FIFO_L_IMUX21_1", + "CMT_TOP_IMUX21_2" + ], + [ + "CMT_FIFO_L_IMUX12_10", + "CMT_TOP_IMUX12_11" + ], + [ + "CMT_FIFO_EE4BEG2_9", + "CMT_TOP_EE4BEG2_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_0", + "CMT_TOP_LOGIC_OUTS_L_B19_1" + ], + [ + "CMT_FIFO_NW4A0_2", + "CMT_TOP_NW4A0_3" + ], + [ + "CMT_FIFO_NE4C1_4", + "CMT_TOP_NE4C1_5" + ], + [ + "CMT_FIFO_EE4B2_1", + "CMT_TOP_EE4B2_2" + ], + [ + "CMT_FIFO_EE4B3_2", + "CMT_TOP_EE4B3_3" + ], + [ + "CMT_FIFO_L_BYP7_3", + "CMT_TOP_BYP7_4" + ], + [ + "CMT_FIFO_L_IMUX31_11", + "CMT_TOP_IMUX31_12" + ], + [ + "CMT_FIFO_EL1BEG1_0", + "CMT_TOP_EL1BEG1_1" + ], + [ + "CMT_FIFO_SW2A0_5", + "CMT_TOP_SW2A0_6" + ], + [ + "CMT_FIFO_NW4END0_1", + "CMT_TOP_NW4END0_2" + ], + [ + "CMT_FIFO_NE2A3_1", + "CMT_TOP_NE2A3_2" + ], + [ + "CMT_FIFO_WW4A2_1", + "CMT_TOP_WW4A2_2" + ], + [ + "CMT_FIFO_LH9_7", + "CMT_TOP_LH9_8" + ], + [ + "CMT_FIFO_NE4BEG0_3", + "CMT_TOP_NE4BEG0_4" + ], + [ + "CMT_FIFO_WR1END3_11", + "CMT_TOP_WR1END3_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_4", + "CMT_TOP_LOGIC_OUTS_L_B0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_7", + "CMT_TOP_LOGIC_OUTS_L_B1_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "CMT_TOP_OCLKDIV_4" + ], + [ + "CMT_FIFO_L_IMUX20_5", + "CMT_TOP_IMUX20_6" + ], + [ + "CMT_FIFO_WW4B1_1", + "CMT_TOP_WW4B1_2" + ], + [ + "CMT_FIFO_L_IMUX25_3", + "CMT_TOP_IMUX25_4" + ], + [ + "CMT_FIFO_L_BYP1_2", + "CMT_TOP_BYP1_3" + ], + [ + "CMT_FIFO_SW4END0_9", + "CMT_TOP_SW4END0_10" + ], + [ + "CMT_FIFO_WW4C1_4", + "CMT_TOP_WW4C1_5" + ], + [ + "CMT_FIFO_NW4A0_11", + "CMT_TOP_NW4A0_12" + ], + [ + "CMT_FIFO_L_IMUX10_6", + "CMT_TOP_IMUX10_7" + ], + [ + "CMT_FIFO_LH11_2", + "CMT_TOP_LH11_3" + ], + [ + "CMT_FIFO_LH4_0", + "CMT_TOP_LH4_1" + ], + [ + "CMT_FIFO_L_BYP2_7", + "CMT_TOP_BYP2_8" + ], + [ + "CMT_FIFO_SE4BEG0_0", + "CMT_TOP_SE4BEG0_1" + ], + [ + "CMT_FIFO_L_FAN2_3", + "CMT_TOP_FAN2_4" + ], + [ + "CMT_FIFO_L_IMUX3_11", + "CMT_TOP_IMUX3_12" + ], + [ + "CMT_FIFO_L_IMUX14_4", + "CMT_TOP_IMUX14_5" + ], + [ + "CMT_FIFO_L_IMUX35_11", + "CMT_TOP_IMUX35_12" + ], + [ + "CMT_FIFO_L_IMUX2_0", + "CMT_TOP_IMUX2_1" + ], + [ + "CMT_FIFO_NE4BEG2_6", + "CMT_TOP_NE4BEG2_7" + ], + [ + "CMT_FIFO_EE2BEG3_3", + "CMT_TOP_EE2BEG3_4" + ], + [ + "CMT_FIFO_WR1END1_3", + "CMT_TOP_WR1END1_4" + ], + [ + "CMT_FIFO_WR1END1_11", + "CMT_TOP_WR1END1_12" + ], + [ + "CMT_FIFO_L_FAN2_7", + "CMT_TOP_FAN2_8" + ], + [ + "CMT_FIFO_WR1END2_10", + "CMT_TOP_WR1END2_11" + ], + [ + "CMT_FIFO_L_IMUX28_4", + "CMT_TOP_IMUX28_5" + ], + [ + "CMT_FIFO_LH3_7", + "CMT_TOP_LH3_8" + ], + [ + "CMT_FIFO_L_IMUX4_4", + "CMT_TOP_IMUX4_5" + ], + [ + "CMT_FIFO_EE4BEG0_3", + "CMT_TOP_EE4BEG0_4" + ], + [ + "CMT_FIFO_L_IMUX28_9", + "CMT_TOP_IMUX28_10" + ], + [ + "CMT_FIFO_L_BYP7_1", + "CMT_TOP_BYP7_2" + ], + [ + "CMT_FIFO_WW2END3_0", + "CMT_TOP_WW2END3_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "CMT_TOP_ICLK_1" + ], + [ + "CMT_FIFO_L_BYP6_7", + "CMT_TOP_BYP6_8" + ], + [ + "CMT_FIFO_L_IMUX38_0", + "CMT_TOP_IMUX38_1" + ], + [ + "CMT_FIFO_LH10_8", + "CMT_TOP_LH10_9" + ], + [ + "CMT_FIFO_NW4A1_6", + "CMT_TOP_NW4A1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_3", + "CMT_TOP_LOGIC_OUTS_L_B21_4" + ], + [ + "CMT_FIFO_L_FAN7_5", + "CMT_TOP_FAN7_6" + ], + [ + "CMT_FIFO_SW2A3_9", + "CMT_TOP_SW2A3_10" + ], + [ + "CMT_FIFO_WW4B0_2", + "CMT_TOP_WW4B0_3" + ], + [ + "CMT_FIFO_L_IMUX15_7", + "CMT_TOP_IMUX15_8" + ], + [ + "CMT_FIFO_LH12_5", + "CMT_TOP_LH12_6" + ], + [ + "CMT_FIFO_WW4A0_3", + "CMT_TOP_WW4A0_4" + ], + [ + "CMT_FIFO_EE4C1_2", + "CMT_TOP_EE4C1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_5", + "CMT_TOP_LOGIC_OUTS_L_B17_6" + ], + [ + "CMT_FIFO_WW4B0_7", + "CMT_TOP_WW4B0_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "CMT_TOP_OCLKDIV_7" + ], + [ + "CMT_FIFO_NE4BEG3_4", + "CMT_TOP_NE4BEG3_5" + ], + [ + "CMT_FIFO_WW4B1_2", + "CMT_TOP_WW4B1_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "CMT_TOP_OCLK_2" + ], + [ + "CMT_FIFO_EE4A2_1", + "CMT_TOP_EE4A2_2" + ], + [ + "CMT_FIFO_EE2BEG3_8", + "CMT_TOP_EE2BEG3_9" + ], + [ + "CMT_FIFO_EE2A0_11", + "CMT_TOP_EE2A0_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_10", + "CMT_TOP_LOGIC_OUTS_L_B5_11" + ], + [ + "CMT_FIFO_SE4C1_6", + "CMT_TOP_SE4C1_7" + ], + [ + "CMT_FIFO_EE2A2_8", + "CMT_TOP_EE2A2_9" + ], + [ + "CMT_FIFO_WW4A3_4", + "CMT_TOP_WW4A3_5" + ], + [ + "CMT_FIFO_WW4C1_1", + "CMT_TOP_WW4C1_2" + ], + [ + "CMT_FIFO_L_CTRL0_2", + "CMT_TOP_CTRL0_3" + ], + [ + "CMT_FIFO_EE4B2_7", + "CMT_TOP_EE4B2_8" + ], + [ + "CMT_FIFO_WW4A3_7", + "CMT_TOP_WW4A3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_4", + "CMT_TOP_LOGIC_OUTS_L_B20_5" + ], + [ + "CMT_FIFO_SE4C3_2", + "CMT_TOP_SE4C3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_2", + "CMT_TOP_LOGIC_OUTS_L_B10_3" + ], + [ + "CMT_FIFO_WW4END1_2", + "CMT_TOP_WW4END1_3" + ], + [ + "CMT_FIFO_L_BYP3_1", + "CMT_TOP_BYP3_2" + ], + [ + "CMT_FIFO_WW4A1_7", + "CMT_TOP_WW4A1_8" + ], + [ + "CMT_FIFO_L_IMUX17_5", + "CMT_TOP_IMUX17_6" + ], + [ + "CMT_FIFO_WW4B3_5", + "CMT_TOP_WW4B3_6" + ], + [ + "CMT_FIFO_L_IMUX20_6", + "CMT_TOP_IMUX20_7" + ], + [ + "CMT_FIFO_EE4C0_9", + "CMT_TOP_EE4C0_10" + ], + [ + "CMT_FIFO_NE4BEG0_7", + "CMT_TOP_NE4BEG0_8" + ], + [ + "CMT_FIFO_WW4A1_3", + "CMT_TOP_WW4A1_4" + ], + [ + "CMT_FIFO_L_BYP6_11", + "CMT_TOP_BYP6_12" + ], + [ + "CMT_FIFO_NE2A2_2", + "CMT_TOP_NE2A2_3" + ], + [ + "CMT_FIFO_L_FAN2_6", + "CMT_TOP_FAN2_7" + ], + [ + "CMT_FIFO_L_IMUX4_5", + "CMT_TOP_IMUX4_6" + ], + [ + "CMT_FIFO_NE4C2_9", + "CMT_TOP_NE4C2_10" + ], + [ + "CMT_FIFO_LH4_5", + "CMT_TOP_LH4_6" + ], + [ + "CMT_FIFO_WW4B2_11", + "CMT_TOP_WW4B2_12" + ], + [ + "CMT_FIFO_SW4A0_4", + "CMT_TOP_SW4A0_5" + ], + [ + "CMT_FIFO_L_BYP1_0", + "CMT_TOP_BYP1_1" + ], + [ + "CMT_FIFO_NW4A1_0", + "CMT_TOP_NW4A1_1" + ], + [ + "CMT_FIFO_WL1END1_8", + "CMT_TOP_WL1END1_9" + ], + [ + "CMT_FIFO_L_IMUX2_10", + "CMT_TOP_IMUX2_11" + ], + [ + "CMT_FIFO_L_BYP0_2", + "CMT_TOP_BYP0_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "CMT_TOP_ICLK_5" + ], + [ + "CMT_FIFO_L_IMUX23_3", + "CMT_TOP_IMUX23_4" + ], + [ + "CMT_FIFO_NE2A1_11", + "CMT_TOP_NE2A1_12" + ], + [ + "CMT_FIFO_EE4B1_9", + "CMT_TOP_EE4B1_10" + ], + [ + "CMT_FIFO_L_CLK1_6", + "CMT_TOP_CLK1_7" + ], + [ + "CMT_FIFO_WR1END3_6", + "CMT_TOP_WR1END3_7" + ], + [ + "CMT_FIFO_ER1BEG3_8", + "CMT_TOP_ER1BEG3_9" + ], + [ + "CMT_FIFO_EE2A3_1", + "CMT_TOP_EE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX2_8", + "CMT_TOP_IMUX2_9" + ], + [ + "CMT_FIFO_NE2A2_8", + "CMT_TOP_NE2A2_9" + ], + [ + "CMT_FIFO_L_IMUX44_9", + "CMT_TOP_IMUX44_10" + ], + [ + "CMT_FIFO_EE4C1_6", + "CMT_TOP_EE4C1_7" + ], + [ + "CMT_FIFO_L_IMUX44_0", + "CMT_TOP_IMUX44_1" + ], + [ + "CMT_FIFO_L_CTRL1_11", + "CMT_TOP_CTRL1_12" + ], + [ + "CMT_FIFO_SW2A1_3", + "CMT_TOP_SW2A1_4" + ], + [ + "CMT_FIFO_L_IMUX28_1", + "CMT_TOP_IMUX28_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_5", + "CMT_TOP_LOGIC_OUTS_L_B18_6" + ], + [ + "CMT_FIFO_L_BYP0_3", + "CMT_TOP_BYP0_4" + ], + [ + "CMT_FIFO_NE2A3_2", + "CMT_TOP_NE2A3_3" + ], + [ + "CMT_FIFO_SE4C1_5", + "CMT_TOP_SE4C1_6" + ], + [ + "CMT_FIFO_NW4A3_8", + "CMT_TOP_NW4A3_9" + ], + [ + "CMT_FIFO_SW4END2_1", + "CMT_TOP_SW4END2_2" + ], + [ + "CMT_FIFO_WW4END1_7", + "CMT_TOP_WW4END1_8" + ], + [ + "CMT_FIFO_L_IMUX5_11", + "CMT_TOP_IMUX5_12" + ], + [ + "CMT_FIFO_LH4_10", + "CMT_TOP_LH4_11" + ], + [ + "CMT_FIFO_L_IMUX35_8", + "CMT_TOP_IMUX35_9" + ], + [ + "CMT_FIFO_EE2BEG1_2", + "CMT_TOP_EE2BEG1_3" + ], + [ + "CMT_FIFO_EL1BEG1_6", + "CMT_TOP_EL1BEG1_7" + ], + [ + "CMT_FIFO_SW4END2_6", + "CMT_TOP_SW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX39_2", + "CMT_TOP_IMUX39_3" + ], + [ + "CMT_FIFO_EE2A0_6", + "CMT_TOP_EE2A0_7" + ], + [ + "CMT_FIFO_L_IMUX7_0", + "CMT_TOP_IMUX7_1" + ], + [ + "CMT_FIFO_EL1BEG1_10", + "CMT_TOP_EL1BEG1_11" + ], + [ + "CMT_FIFO_EE4A3_2", + "CMT_TOP_EE4A3_3" + ], + [ + "CMT_FIFO_NW4A0_1", + "CMT_TOP_NW4A0_2" + ], + [ + "CMT_FIFO_L_IMUX7_6", + "CMT_TOP_IMUX7_7" + ], + [ + "CMT_FIFO_SW4A0_5", + "CMT_TOP_SW4A0_6" + ], + [ + "CMT_FIFO_L_IMUX31_1", + "CMT_TOP_IMUX31_2" + ], + [ + "CMT_FIFO_L_IMUX13_11", + "CMT_TOP_IMUX13_12" + ], + [ + "CMT_FIFO_SW4A0_11", + "CMT_TOP_SW4A0_12" + ], + [ + "CMT_FIFO_EE4C2_6", + "CMT_TOP_EE4C2_7" + ], + [ + "CMT_FIFO_SE4C2_3", + "CMT_TOP_SE4C2_4" + ], + [ + "CMT_FIFO_L_IMUX36_5", + "CMT_TOP_IMUX36_6" + ], + [ + "CMT_FIFO_L_IMUX47_7", + "CMT_TOP_IMUX47_8" + ], + [ + "CMT_FIFO_EE2BEG1_10", + "CMT_TOP_EE2BEG1_11" + ], + [ + "CMT_FIFO_L_IMUX2_11", + "CMT_TOP_IMUX2_12" + ], + [ + "CMT_FIFO_NW4END3_8", + "CMT_TOP_NW4END3_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "CMT_TOP_ICLKDIV_4" + ], + [ + "CMT_FIFO_L_IMUX11_1", + "CMT_TOP_IMUX11_2" + ], + [ + "CMT_FIFO_SW4END3_3", + "CMT_TOP_SW4END3_4" + ], + [ + "CMT_FIFO_L_IMUX44_4", + "CMT_TOP_IMUX44_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_4", + "CMT_TOP_LOGIC_OUTS_L_B8_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_3", + "CMT_TOP_LOGIC_OUTS_L_B18_4" + ], + [ + "CMT_FIFO_NW4END0_0", + "CMT_TOP_NW4END0_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "CMT_TOP_ICLKDIV_6" + ], + [ + "CMT_FIFO_WW2END1_8", + "CMT_TOP_WW2END1_9" + ], + [ + "CMT_FIFO_NW4END0_10", + "CMT_TOP_NW4END0_11" + ], + [ + "CMT_FIFO_L_IMUX18_2", + "CMT_TOP_IMUX18_3" + ], + [ + "CMT_FIFO_WL1END0_9", + "CMT_TOP_WL1END0_10" + ], + [ + "CMT_FIFO_NW4END2_6", + "CMT_TOP_NW4END2_7" + ], + [ + "CMT_FIFO_NW2A2_3", + "CMT_TOP_NW2A2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_11", + "CMT_TOP_LOGIC_OUTS_L_B5_12" + ], + [ + "CMT_FIFO_L_IMUX5_4", + "CMT_TOP_IMUX5_5" + ], + [ + "CMT_FIFO_L_IMUX21_5", + "CMT_TOP_IMUX21_6" + ], + [ + "CMT_FIFO_WW4B2_2", + "CMT_TOP_WW4B2_3" + ], + [ + "CMT_FIFO_WW4A3_11", + "CMT_TOP_WW4A3_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_6", + "CMT_TOP_LOGIC_OUTS_L_B18_7" + ], + [ + "CMT_FIFO_L_IMUX39_6", + "CMT_TOP_IMUX39_7" + ], + [ + "CMT_FIFO_L_IMUX37_3", + "CMT_TOP_IMUX37_4" + ], + [ + "CMT_FIFO_SW2A2_1", + "CMT_TOP_SW2A2_2" + ], + [ + "CMT_FIFO_WW4B2_5", + "CMT_TOP_WW4B2_6" + ], + [ + "CMT_FIFO_EE4BEG3_6", + "CMT_TOP_EE4BEG3_7" + ], + [ + "CMT_FIFO_EE4BEG0_2", + "CMT_TOP_EE4BEG0_3" + ], + [ + "CMT_FIFO_EL1BEG0_11", + "CMT_TOP_EL1BEG0_12" + ], + [ + "CMT_FIFO_L_IMUX6_7", + "CMT_TOP_IMUX6_8" + ], + [ + "CMT_FIFO_EE4C2_7", + "CMT_TOP_EE4C2_8" + ], + [ + "CMT_FIFO_L_IMUX41_3", + "CMT_TOP_IMUX41_4" + ], + [ + "CMT_FIFO_WW2A1_7", + "CMT_TOP_WW2A1_8" + ], + [ + "CMT_FIFO_ER1BEG2_5", + "CMT_TOP_ER1BEG2_6" + ], + [ + "CMT_FIFO_SE4C3_5", + "CMT_TOP_SE4C3_6" + ], + [ + "CMT_FIFO_SW4A0_3", + "CMT_TOP_SW4A0_4" + ], + [ + "CMT_FIFO_L_IMUX46_9", + "CMT_TOP_IMUX46_10" + ], + [ + "CMT_FIFO_ER1BEG0_2", + "CMT_TOP_ER1BEG0_3" + ], + [ + "CMT_FIFO_L_IMUX31_8", + "CMT_TOP_IMUX31_9" + ], + [ + "CMT_FIFO_SW2A1_8", + "CMT_TOP_SW2A1_9" + ], + [ + "CMT_FIFO_L_IMUX34_4", + "CMT_TOP_IMUX34_5" + ], + [ + "CMT_FIFO_EE2A2_7", + "CMT_TOP_EE2A2_8" + ], + [ + "CMT_FIFO_NE4C0_1", + "CMT_TOP_NE4C0_2" + ], + [ + "CMT_FIFO_NE4C2_8", + "CMT_TOP_NE4C2_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "CMT_TOP_ICLK_6" + ], + [ + "CMT_FIFO_L_BYP1_4", + "CMT_TOP_BYP1_5" + ], + [ + "CMT_FIFO_EE4C2_5", + "CMT_TOP_EE4C2_6" + ], + [ + "CMT_FIFO_L_IMUX11_9", + "CMT_TOP_IMUX11_10" + ], + [ + "CMT_FIFO_L_IMUX28_11", + "CMT_TOP_IMUX28_12" + ], + [ + "CMT_FIFO_MONITOR_P_6", + "CMT_TOP_MONITOR_P_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_9", + "CMT_TOP_LOGIC_OUTS_L_B10_10" + ], + [ + "CMT_FIFO_WW4B3_4", + "CMT_TOP_WW4B3_5" + ], + [ + "CMT_FIFO_SE4BEG2_7", + "CMT_TOP_SE4BEG2_8" + ], + [ + "CMT_FIFO_SW2A0_10", + "CMT_TOP_SW2A0_11" + ], + [ + "CMT_FIFO_NW4A2_9", + "CMT_TOP_NW4A2_10" + ], + [ + "CMT_FIFO_EL1BEG2_5", + "CMT_TOP_EL1BEG2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_7", + "CMT_TOP_LOGIC_OUTS_L_B15_8" + ], + [ + "CMT_FIFO_L_IMUX32_11", + "CMT_TOP_IMUX32_12" + ], + [ + "CMT_FIFO_EE4BEG2_11", + "CMT_TOP_EE4BEG2_12" + ], + [ + "CMT_FIFO_NW4A3_1", + "CMT_TOP_NW4A3_2" + ], + [ + "CMT_FIFO_WW4B3_11", + "CMT_TOP_WW4B3_12" + ], + [ + "CMT_FIFO_NW2A3_10", + "CMT_TOP_NW2A3_11" + ], + [ + "CMT_FIFO_L_IMUX8_9", + "CMT_TOP_IMUX8_10" + ], + [ + "CMT_FIFO_LH2_9", + "CMT_TOP_LH2_10" + ], + [ + "CMT_FIFO_SE2A0_5", + "CMT_TOP_SE2A0_6" + ], + [ + "CMT_FIFO_WL1END0_1", + "CMT_TOP_WL1END0_2" + ], + [ + "CMT_FIFO_WW4A1_5", + "CMT_TOP_WW4A1_6" + ], + [ + "CMT_FIFO_LH1_3", + "CMT_TOP_LH1_4" + ], + [ + "CMT_FIFO_EE2A3_2", + "CMT_TOP_EE2A3_3" + ], + [ + "CMT_FIFO_L_IMUX40_0", + "CMT_TOP_IMUX40_1" + ], + [ + "CMT_FIFO_SE4C3_8", + "CMT_TOP_SE4C3_9" + ], + [ + "CMT_FIFO_WL1END0_5", + "CMT_TOP_WL1END0_6" + ], + [ + "CMT_FIFO_NW2A0_4", + "CMT_TOP_NW2A0_5" + ], + [ + "CMT_FIFO_L_BYP5_2", + "CMT_TOP_BYP5_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_4", + "CMT_TOP_LOGIC_OUTS_L_B9_5" + ], + [ + "CMT_FIFO_LH3_9", + "CMT_TOP_LH3_10" + ], + [ + "CMT_FIFO_L_IMUX4_2", + "CMT_TOP_IMUX4_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_11", + "CMT_TOP_LOGIC_OUTS_L_B11_12" + ], + [ + "CMT_FIFO_EE2A1_3", + "CMT_TOP_EE2A1_4" + ], + [ + "CMT_FIFO_NE4BEG0_2", + "CMT_TOP_NE4BEG0_3" + ], + [ + "CMT_FIFO_WW2A2_9", + "CMT_TOP_WW2A2_10" + ], + [ + "CMT_FIFO_WW4C2_5", + "CMT_TOP_WW4C2_6" + ], + [ + "CMT_FIFO_WW4A0_0", + "CMT_TOP_WW4A0_1" + ], + [ + "CMT_FIFO_EL1BEG3_2", + "CMT_TOP_EL1BEG3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_11", + "CMT_TOP_LOGIC_OUTS_L_B4_12" + ], + [ + "CMT_FIFO_L_CTRL1_10", + "CMT_TOP_CTRL1_11" + ], + [ + "CMT_FIFO_NW4A1_7", + "CMT_TOP_NW4A1_8" + ], + [ + "CMT_FIFO_EE4B2_5", + "CMT_TOP_EE4B2_6" + ], + [ + "CMT_FIFO_L_FAN3_7", + "CMT_TOP_FAN3_8" + ], + [ + "CMT_FIFO_WW2A2_10", + "CMT_TOP_WW2A2_11" + ], + [ + "CMT_FIFO_L_IMUX26_2", + "CMT_TOP_IMUX26_3" + ], + [ + "CMT_FIFO_L_IMUX42_7", + "CMT_TOP_IMUX42_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_8", + "CMT_TOP_LOGIC_OUTS_L_B11_9" + ], + [ + "CMT_FIFO_WW2A2_0", + "CMT_TOP_WW2A2_1" + ], + [ + "CMT_FIFO_SE4C2_1", + "CMT_TOP_SE4C2_2" + ], + [ + "CMT_FIFO_WL1END3_2", + "CMT_TOP_WL1END3_3" + ], + [ + "CMT_FIFO_ER1BEG1_5", + "CMT_TOP_ER1BEG1_6" + ], + [ + "CMT_FIFO_LH5_9", + "CMT_TOP_LH5_10" + ], + [ + "CMT_FIFO_NW2A0_11", + "CMT_TOP_NW2A0_12" + ], + [ + "CMT_FIFO_EE4BEG0_1", + "CMT_TOP_EE4BEG0_2" + ], + [ + "CMT_FIFO_NW4A2_11", + "CMT_TOP_NW4A2_12" + ], + [ + "CMT_FIFO_EE4BEG1_10", + "CMT_TOP_EE4BEG1_11" + ], + [ + "CMT_FIFO_WW4B2_3", + "CMT_TOP_WW4B2_4" + ], + [ + "CMT_FIFO_WW4C2_2", + "CMT_TOP_WW4C2_3" + ], + [ + "CMT_FIFO_L_BYP6_9", + "CMT_TOP_BYP6_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "CMT_TOP_OCLKDIV_3" + ], + [ + "CMT_FIFO_L_IMUX18_7", + "CMT_TOP_IMUX18_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_7", + "CMT_TOP_LOGIC_OUTS_L_B17_8" + ], + [ + "CMT_FIFO_NW2A3_3", + "CMT_TOP_NW2A3_4" + ], + [ + "CMT_FIFO_EE4BEG1_7", + "CMT_TOP_EE4BEG1_8" + ], + [ + "CMT_FIFO_NW4A0_7", + "CMT_TOP_NW4A0_8" + ], + [ + "CMT_FIFO_MONITOR_N_2", + "CMT_TOP_MONITOR_N_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_9", + "CMT_TOP_LOGIC_OUTS_L_B7_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_1", + "CMT_TOP_LOGIC_OUTS_L_B12_2" + ], + [ + "CMT_FIFO_L_BYP3_3", + "CMT_TOP_BYP3_4" + ], + [ + "CMT_FIFO_L_IMUX16_9", + "CMT_TOP_IMUX16_10" + ], + [ + "CMT_FIFO_EE4A3_3", + "CMT_TOP_EE4A3_4" + ], + [ + "CMT_FIFO_L_IMUX34_8", + "CMT_TOP_IMUX34_9" + ], + [ + "CMT_FIFO_L_CTRL0_8", + "CMT_TOP_CTRL0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_7", + "CMT_TOP_LOGIC_OUTS_L_B22_8" + ], + [ + "CMT_FIFO_NE4C1_2", + "CMT_TOP_NE4C1_3" + ], + [ + "CMT_FIFO_WW2END1_9", + "CMT_TOP_WW2END1_10" + ], + [ + "CMT_FIFO_L_BYP0_9", + "CMT_TOP_BYP0_10" + ], + [ + "CMT_FIFO_L_IMUX20_11", + "CMT_TOP_IMUX20_12" + ], + [ + "CMT_FIFO_SW2A0_4", + "CMT_TOP_SW2A0_5" + ], + [ + "CMT_FIFO_SE4BEG1_11", + "CMT_TOP_SE4BEG1_12" + ], + [ + "CMT_FIFO_NE2A1_3", + "CMT_TOP_NE2A1_4" + ], + [ + "CMT_FIFO_LH3_10", + "CMT_TOP_LH3_11" + ], + [ + "CMT_FIFO_NE2A3_4", + "CMT_TOP_NE2A3_5" + ], + [ + "CMT_FIFO_WR1END1_2", + "CMT_TOP_WR1END1_3" + ], + [ + "CMT_FIFO_LH10_9", + "CMT_TOP_LH10_10" + ], + [ + "CMT_FIFO_L_FAN0_0", + "CMT_TOP_FAN0_1" + ], + [ + "CMT_FIFO_EE2A2_9", + "CMT_TOP_EE2A2_10" + ], + [ + "CMT_FIFO_L_IMUX15_3", + "CMT_TOP_IMUX15_4" + ], + [ + "CMT_FIFO_L_IMUX10_3", + "CMT_TOP_IMUX10_4" + ], + [ + "CMT_FIFO_LH12_8", + "CMT_TOP_LH12_9" + ], + [ + "CMT_FIFO_L_IMUX6_8", + "CMT_TOP_IMUX6_9" + ], + [ + "CMT_FIFO_WW4A0_4", + "CMT_TOP_WW4A0_5" + ], + [ + "CMT_FIFO_EE4C0_3", + "CMT_TOP_EE4C0_4" + ], + [ + "CMT_FIFO_EE2BEG1_9", + "CMT_TOP_EE2BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX42_2", + "CMT_TOP_IMUX42_3" + ], + [ + "CMT_FIFO_L_CLK1_4", + "CMT_TOP_CLK1_5" + ], + [ + "CMT_FIFO_EE4C1_4", + "CMT_TOP_EE4C1_5" + ], + [ + "CMT_FIFO_EE4C2_3", + "CMT_TOP_EE4C2_4" + ], + [ + "CMT_FIFO_L_BYP6_4", + "CMT_TOP_BYP6_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_5", + "CMT_TOP_LOGIC_OUTS_L_B11_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_4", + "CMT_TOP_LOGIC_OUTS_L_B5_5" + ], + [ + "CMT_FIFO_L_IMUX26_10", + "CMT_TOP_IMUX26_11" + ], + [ + "CMT_FIFO_WW4B3_7", + "CMT_TOP_WW4B3_8" + ], + [ + "CMT_FIFO_NW4END3_3", + "CMT_TOP_NW4END3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_6", + "CMT_TOP_LOGIC_OUTS_L_B13_7" + ], + [ + "CMT_FIFO_NW4END0_3", + "CMT_TOP_NW4END0_4" + ], + [ + "CMT_FIFO_LH12_0", + "CMT_TOP_LH12_1" + ], + [ + "CMT_FIFO_L_IMUX17_6", + "CMT_TOP_IMUX17_7" + ], + [ + "CMT_FIFO_LH2_6", + "CMT_TOP_LH2_7" + ], + [ + "CMT_FIFO_L_IMUX46_8", + "CMT_TOP_IMUX46_9" + ], + [ + "CMT_FIFO_L_IMUX28_7", + "CMT_TOP_IMUX28_8" + ], + [ + "CMT_FIFO_LH9_8", + "CMT_TOP_LH9_9" + ], + [ + "CMT_FIFO_NE4BEG2_3", + "CMT_TOP_NE4BEG2_4" + ], + [ + "CMT_FIFO_L_IMUX6_6", + "CMT_TOP_IMUX6_7" + ], + [ + "CMT_FIFO_NE4C3_2", + "CMT_TOP_NE4C3_3" + ], + [ + "CMT_FIFO_L_IMUX5_5", + "CMT_TOP_IMUX5_6" + ], + [ + "CMT_FIFO_NE4BEG3_0", + "CMT_TOP_NE4BEG3_1" + ], + [ + "CMT_FIFO_NW4END1_5", + "CMT_TOP_NW4END1_6" + ], + [ + "CMT_FIFO_L_IMUX25_1", + "CMT_TOP_IMUX25_2" + ], + [ + "CMT_FIFO_NW2A2_2", + "CMT_TOP_NW2A2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_3", + "CMT_TOP_LOGIC_OUTS_L_B9_4" + ], + [ + "CMT_FIFO_L_IMUX13_9", + "CMT_TOP_IMUX13_10" + ], + [ + "CMT_FIFO_LH1_4", + "CMT_TOP_LH1_5" + ], + [ + "CMT_FIFO_L_IMUX44_5", + "CMT_TOP_IMUX44_6" + ], + [ + "CMT_FIFO_MONITOR_P_2", + "CMT_TOP_MONITOR_P_3" + ], + [ + "CMT_FIFO_EE2BEG2_3", + "CMT_TOP_EE2BEG2_4" + ], + [ + "CMT_FIFO_WL1END1_6", + "CMT_TOP_WL1END1_7" + ], + [ + "CMT_FIFO_L_BYP3_5", + "CMT_TOP_BYP3_6" + ], + [ + "CMT_FIFO_L_IMUX21_6", + "CMT_TOP_IMUX21_7" + ], + [ + "CMT_FIFO_L_FAN2_4", + "CMT_TOP_FAN2_5" + ], + [ + "CMT_FIFO_NW4A1_1", + "CMT_TOP_NW4A1_2" + ], + [ + "CMT_FIFO_NW4END0_4", + "CMT_TOP_NW4END0_5" + ], + [ + "CMT_FIFO_NE2A3_3", + "CMT_TOP_NE2A3_4" + ], + [ + "CMT_FIFO_L_BYP4_2", + "CMT_TOP_BYP4_3" + ], + [ + "CMT_FIFO_L_BYP6_5", + "CMT_TOP_BYP6_6" + ], + [ + "CMT_FIFO_NE4C3_3", + "CMT_TOP_NE4C3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_11", + "CMT_TOP_LOGIC_OUTS_L_B22_12" + ], + [ + "CMT_FIFO_LH1_10", + "CMT_TOP_LH1_11" + ], + [ + "CMT_FIFO_L_IMUX4_6", + "CMT_TOP_IMUX4_7" + ], + [ + "CMT_FIFO_WW4A3_5", + "CMT_TOP_WW4A3_6" + ], + [ + "CMT_FIFO_LH10_1", + "CMT_TOP_LH10_2" + ], + [ + "CMT_FIFO_WW4END3_2", + "CMT_TOP_WW4END3_3" + ], + [ + "CMT_FIFO_SW2A2_0", + "CMT_TOP_SW2A2_1" + ], + [ + "CMT_FIFO_NW2A0_10", + "CMT_TOP_NW2A0_11" + ], + [ + "CMT_FIFO_EE4C3_10", + "CMT_TOP_EE4C3_11" + ], + [ + "CMT_FIFO_SE4C1_7", + "CMT_TOP_SE4C1_8" + ], + [ + "CMT_FIFO_EE4C0_11", + "CMT_TOP_EE4C0_12" + ], + [ + "CMT_FIFO_L_IMUX25_2", + "CMT_TOP_IMUX25_3" + ], + [ + "CMT_FIFO_L_FAN2_2", + "CMT_TOP_FAN2_3" + ], + [ + "CMT_FIFO_L_IMUX44_7", + "CMT_TOP_IMUX44_8" + ], + [ + "CMT_FIFO_SW4A3_8", + "CMT_TOP_SW4A3_9" + ], + [ + "CMT_FIFO_SE2A2_4", + "CMT_TOP_SE2A2_5" + ], + [ + "CMT_FIFO_WW4A0_9", + "CMT_TOP_WW4A0_10" + ], + [ + "CMT_FIFO_L_IMUX47_2", + "CMT_TOP_IMUX47_3" + ], + [ + "CMT_FIFO_SW4A0_0", + "CMT_TOP_SW4A0_1" + ], + [ + "CMT_FIFO_L_IMUX26_11", + "CMT_TOP_IMUX26_12" + ], + [ + "CMT_FIFO_L_IMUX23_6", + "CMT_TOP_IMUX23_7" + ], + [ + "CMT_FIFO_SW2A1_0", + "CMT_TOP_SW2A1_1" + ], + [ + "CMT_FIFO_WW4B2_1", + "CMT_TOP_WW4B2_2" + ], + [ + "CMT_FIFO_L_IMUX40_2", + "CMT_TOP_IMUX40_3" + ], + [ + "CMT_FIFO_WW2END1_0", + "CMT_TOP_WW2END1_1" + ], + [ + "CMT_FIFO_EE4C0_0", + "CMT_TOP_EE4C0_1" + ], + [ + "CMT_FIFO_EE4C3_5", + "CMT_TOP_EE4C3_6" + ], + [ + "CMT_FIFO_WW4A1_1", + "CMT_TOP_WW4A1_2" + ], + [ + "CMT_FIFO_L_BYP5_10", + "CMT_TOP_BYP5_11" + ], + [ + "CMT_FIFO_NE2A0_5", + "CMT_TOP_NE2A0_6" + ], + [ + "CMT_FIFO_L_FAN6_10", + "CMT_TOP_FAN6_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_11", + "CMT_TOP_LOGIC_OUTS_L_B1_12" + ], + [ + "CMT_FIFO_LH3_3", + "CMT_TOP_LH3_4" + ], + [ + "CMT_FIFO_NW4A2_0", + "CMT_TOP_NW4A2_1" + ], + [ + "CMT_FIFO_NW2A0_9", + "CMT_TOP_NW2A0_10" + ], + [ + "CMT_FIFO_L_IMUX17_7", + "CMT_TOP_IMUX17_8" + ], + [ + "CMT_FIFO_L_IMUX47_0", + "CMT_TOP_IMUX47_1" + ], + [ + "CMT_FIFO_EL1BEG3_0", + "CMT_TOP_EL1BEG3_1" + ], + [ + "CMT_FIFO_EE2BEG0_0", + "CMT_TOP_EE2BEG0_1" + ], + [ + "CMT_FIFO_EE4BEG1_3", + "CMT_TOP_EE4BEG1_4" + ], + [ + "CMT_FIFO_SW2A1_2", + "CMT_TOP_SW2A1_3" + ], + [ + "CMT_FIFO_LH8_8", + "CMT_TOP_LH8_9" + ], + [ + "CMT_FIFO_NE4BEG2_7", + "CMT_TOP_NE4BEG2_8" + ], + [ + "CMT_FIFO_L_IMUX29_9", + "CMT_TOP_IMUX29_10" + ], + [ + "CMT_FIFO_SW4A2_5", + "CMT_TOP_SW4A2_6" + ], + [ + "CMT_FIFO_L_IMUX40_9", + "CMT_TOP_IMUX40_10" + ], + [ + "CMT_FIFO_L_FAN4_0", + "CMT_TOP_FAN4_1" + ], + [ + "CMT_FIFO_L_IMUX21_7", + "CMT_TOP_IMUX21_8" + ], + [ + "CMT_FIFO_NW2A1_11", + "CMT_TOP_NW2A1_12" + ], + [ + "CMT_FIFO_EE2BEG0_8", + "CMT_TOP_EE2BEG0_9" + ], + [ + "CMT_FIFO_WW4B1_11", + "CMT_TOP_WW4B1_12" + ], + [ + "CMT_FIFO_WR1END2_8", + "CMT_TOP_WR1END2_9" + ], + [ + "CMT_FIFO_WW4END1_6", + "CMT_TOP_WW4END1_7" + ], + [ + "CMT_FIFO_L_IMUX14_3", + "CMT_TOP_IMUX14_4" + ], + [ + "CMT_FIFO_WW2END1_3", + "CMT_TOP_WW2END1_4" + ], + [ + "CMT_FIFO_WW4END0_6", + "CMT_TOP_WW4END0_7" + ], + [ + "CMT_FIFO_EE4C1_1", + "CMT_TOP_EE4C1_2" + ], + [ + "CMT_FIFO_SW4A0_10", + "CMT_TOP_SW4A0_11" + ], + [ + "CMT_FIFO_EE4A1_3", + "CMT_TOP_EE4A1_4" + ], + [ + "CMT_FIFO_L_IMUX41_2", + "CMT_TOP_IMUX41_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_2", + "CMT_TOP_LOGIC_OUTS_L_B1_3" + ], + [ + "CMT_FIFO_LH11_10", + "CMT_TOP_LH11_11" + ], + [ + "CMT_FIFO_L_IMUX0_0", + "CMT_TOP_IMUX0_1" + ], + [ + "CMT_FIFO_WW4C3_1", + "CMT_TOP_WW4C3_2" + ], + [ + "CMT_FIFO_EE4BEG3_9", + "CMT_TOP_EE4BEG3_10" + ], + [ + "CMT_FIFO_L_IMUX26_4", + "CMT_TOP_IMUX26_5" + ], + [ + "CMT_FIFO_L_BYP2_1", + "CMT_TOP_BYP2_2" + ], + [ + "CMT_FIFO_NW4END1_11", + "CMT_TOP_NW4END1_12" + ], + [ + "CMT_FIFO_L_BYP2_0", + "CMT_TOP_BYP2_1" + ], + [ + "CMT_FIFO_L_IMUX27_3", + "CMT_TOP_IMUX27_4" + ], + [ + "CMT_FIFO_L_IMUX32_8", + "CMT_TOP_IMUX32_9" + ], + [ + "CMT_FIFO_LH4_9", + "CMT_TOP_LH4_10" + ], + [ + "CMT_FIFO_L_IMUX33_1", + "CMT_TOP_IMUX33_2" + ], + [ + "CMT_FIFO_WL1END3_0", + "CMT_TOP_WL1END3_1" + ], + [ + "CMT_FIFO_SW4END1_5", + "CMT_TOP_SW4END1_6" + ], + [ + "CMT_FIFO_LH9_5", + "CMT_TOP_LH9_6" + ], + [ + "CMT_FIFO_L_IMUX34_7", + "CMT_TOP_IMUX34_8" + ], + [ + "CMT_FIFO_WW4C3_6", + "CMT_TOP_WW4C3_7" + ], + [ + "CMT_FIFO_L_IMUX31_7", + "CMT_TOP_IMUX31_8" + ], + [ + "CMT_FIFO_SE4C2_0", + "CMT_TOP_SE4C2_1" + ], + [ + "CMT_FIFO_L_IMUX9_4", + "CMT_TOP_IMUX9_5" + ], + [ + "CMT_FIFO_LH7_8", + "CMT_TOP_LH7_9" + ], + [ + "CMT_FIFO_WR1END3_9", + "CMT_TOP_WR1END3_10" + ], + [ + "CMT_FIFO_L_IMUX13_8", + "CMT_TOP_IMUX13_9" + ], + [ + "CMT_FIFO_L_IMUX23_9", + "CMT_TOP_IMUX23_10" + ], + [ + "CMT_FIFO_NW4A3_3", + "CMT_TOP_NW4A3_4" + ], + [ + "CMT_FIFO_L_IMUX4_1", + "CMT_TOP_IMUX4_2" + ], + [ + "CMT_FIFO_L_BYP5_0", + "CMT_TOP_BYP5_1" + ], + [ + "CMT_FIFO_L_IMUX32_10", + "CMT_TOP_IMUX32_11" + ], + [ + "CMT_FIFO_LH4_2", + "CMT_TOP_LH4_3" + ], + [ + "CMT_FIFO_LH9_10", + "CMT_TOP_LH9_11" + ], + [ + "CMT_FIFO_NE2A3_10", + "CMT_TOP_NE2A3_11" + ], + [ + "CMT_FIFO_L_IMUX44_10", + "CMT_TOP_IMUX44_11" + ], + [ + "CMT_FIFO_L_IMUX25_4", + "CMT_TOP_IMUX25_5" + ], + [ + "CMT_FIFO_L_IMUX7_3", + "CMT_TOP_IMUX7_4" + ], + [ + "CMT_FIFO_EE4C3_1", + "CMT_TOP_EE4C3_2" + ], + [ + "CMT_FIFO_EE2BEG2_0", + "CMT_TOP_EE2BEG2_1" + ], + [ + "CMT_FIFO_L_IMUX33_6", + "CMT_TOP_IMUX33_7" + ], + [ + "CMT_FIFO_WR1END3_2", + "CMT_TOP_WR1END3_3" + ], + [ + "CMT_FIFO_L_BYP1_10", + "CMT_TOP_BYP1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_7", + "CMT_TOP_LOGIC_OUTS_L_B6_8" + ], + [ + "CMT_FIFO_L_IMUX27_1", + "CMT_TOP_IMUX27_2" + ], + [ + "CMT_FIFO_NW4A1_9", + "CMT_TOP_NW4A1_10" + ], + [ + "CMT_FIFO_L_IMUX18_6", + "CMT_TOP_IMUX18_7" + ], + [ + "CMT_FIFO_EE4B0_3", + "CMT_TOP_EE4B0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_2", + "CMT_TOP_LOGIC_OUTS_L_B7_3" + ], + [ + "CMT_FIFO_SW4END1_7", + "CMT_TOP_SW4END1_8" + ], + [ + "CMT_FIFO_L_FAN6_9", + "CMT_TOP_FAN6_10" + ], + [ + "CMT_FIFO_L_IMUX13_5", + "CMT_TOP_IMUX13_6" + ], + [ + "CMT_FIFO_L_IMUX26_5", + "CMT_TOP_IMUX26_6" + ], + [ + "CMT_FIFO_L_IMUX9_11", + "CMT_TOP_IMUX9_12" + ], + [ + "CMT_FIFO_NW4A0_4", + "CMT_TOP_NW4A0_5" + ], + [ + "CMT_FIFO_NW4A2_7", + "CMT_TOP_NW4A2_8" + ], + [ + "CMT_FIFO_L_FAN2_8", + "CMT_TOP_FAN2_9" + ], + [ + "CMT_FIFO_NE2A3_8", + "CMT_TOP_NE2A3_9" + ], + [ + "CMT_FIFO_L_IMUX37_7", + "CMT_TOP_IMUX37_8" + ], + [ + "CMT_FIFO_WW2A1_4", + "CMT_TOP_WW2A1_5" + ], + [ + "CMT_FIFO_WW4C2_8", + "CMT_TOP_WW4C2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_10", + "CMT_TOP_LOGIC_OUTS_L_B9_11" + ], + [ + "CMT_FIFO_EE4C2_9", + "CMT_TOP_EE4C2_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "CMT_TOP_ICLK_2" + ], + [ + "CMT_FIFO_WL1END1_7", + "CMT_TOP_WL1END1_8" + ], + [ + "CMT_FIFO_EE4C3_0", + "CMT_TOP_EE4C3_1" + ], + [ + "CMT_FIFO_L_BYP6_0", + "CMT_TOP_BYP6_1" + ], + [ + "CMT_FIFO_L_FAN6_8", + "CMT_TOP_FAN6_9" + ], + [ + "CMT_FIFO_LH6_8", + "CMT_TOP_LH6_9" + ], + [ + "CMT_FIFO_LH3_1", + "CMT_TOP_LH3_2" + ], + [ + "CMT_FIFO_WW2A1_1", + "CMT_TOP_WW2A1_2" + ], + [ + "CMT_FIFO_SE2A3_6", + "CMT_TOP_SE2A3_7" + ], + [ + "CMT_FIFO_NE4C0_10", + "CMT_TOP_NE4C0_11" + ], + [ + "CMT_FIFO_L_IMUX38_5", + "CMT_TOP_IMUX38_6" + ], + [ + "CMT_FIFO_LH8_5", + "CMT_TOP_LH8_6" + ], + [ + "CMT_FIFO_WR1END2_5", + "CMT_TOP_WR1END2_6" + ], + [ + "CMT_FIFO_L_IMUX47_1", + "CMT_TOP_IMUX47_2" + ], + [ + "CMT_FIFO_NE2A0_0", + "CMT_TOP_NE2A0_1" + ], + [ + "CMT_FIFO_L_BYP1_9", + "CMT_TOP_BYP1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_7", + "CMT_TOP_LOGIC_OUTS_L_B2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_3", + "CMT_TOP_LOGIC_OUTS_L_B10_4" + ], + [ + "CMT_FIFO_NW2A1_6", + "CMT_TOP_NW2A1_7" + ], + [ + "CMT_FIFO_L_IMUX19_4", + "CMT_TOP_IMUX19_5" + ], + [ + "CMT_FIFO_L_IMUX14_9", + "CMT_TOP_IMUX14_10" + ], + [ + "CMT_FIFO_LH10_11", + "CMT_TOP_LH10_12" + ], + [ + "CMT_FIFO_WW4A3_3", + "CMT_TOP_WW4A3_4" + ], + [ + "CMT_FIFO_L_IMUX21_0", + "CMT_TOP_IMUX21_1" + ], + [ + "CMT_FIFO_L_IMUX42_3", + "CMT_TOP_IMUX42_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_8", + "CMT_TOP_LOGIC_OUTS_L_B5_9" + ], + [ + "CMT_FIFO_L_IMUX20_9", + "CMT_TOP_IMUX20_10" + ], + [ + "CMT_FIFO_L_IMUX1_6", + "CMT_TOP_IMUX1_7" + ], + [ + "CMT_FIFO_WW4END3_3", + "CMT_TOP_WW4END3_4" + ], + [ + "CMT_FIFO_WL1END2_11", + "CMT_TOP_WL1END2_12" + ], + [ + "CMT_FIFO_WW4END2_11", + "CMT_TOP_WW4END2_12" + ], + [ + "CMT_FIFO_L_IMUX22_6", + "CMT_TOP_IMUX22_7" + ], + [ + "CMT_FIFO_LH5_4", + "CMT_TOP_LH5_5" + ], + [ + "CMT_FIFO_NE2A2_0", + "CMT_TOP_NE2A2_1" + ], + [ + "CMT_FIFO_L_IMUX26_0", + "CMT_TOP_IMUX26_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_1", + "CMT_TOP_LOGIC_OUTS_L_B22_2" + ], + [ + "CMT_FIFO_L_IMUX37_0", + "CMT_TOP_IMUX37_1" + ], + [ + "CMT_FIFO_NE4C1_6", + "CMT_TOP_NE4C1_7" + ], + [ + "CMT_FIFO_EE2A2_10", + "CMT_TOP_EE2A2_11" + ], + [ + "CMT_FIFO_WW4A2_7", + "CMT_TOP_WW4A2_8" + ], + [ + "CMT_FIFO_ER1BEG1_2", + "CMT_TOP_ER1BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX17_10", + "CMT_TOP_IMUX17_11" + ], + [ + "CMT_FIFO_L_IMUX13_10", + "CMT_TOP_IMUX13_11" + ], + [ + "CMT_FIFO_WW4END0_3", + "CMT_TOP_WW4END0_4" + ], + [ + "CMT_FIFO_L_IMUX5_8", + "CMT_TOP_IMUX5_9" + ], + [ + "CMT_FIFO_WW4C1_0", + "CMT_TOP_WW4C1_1" + ], + [ + "CMT_FIFO_SW2A0_1", + "CMT_TOP_SW2A0_2" + ], + [ + "CMT_FIFO_NW4A3_11", + "CMT_TOP_NW4A3_12" + ], + [ + "CMT_FIFO_LH12_3", + "CMT_TOP_LH12_4" + ], + [ + "CMT_FIFO_L_IMUX22_11", + "CMT_TOP_IMUX22_12" + ], + [ + "CMT_FIFO_EE4B1_2", + "CMT_TOP_EE4B1_3" + ], + [ + "CMT_FIFO_SE4BEG0_8", + "CMT_TOP_SE4BEG0_9" + ], + [ + "CMT_FIFO_WW4B2_9", + "CMT_TOP_WW4B2_10" + ], + [ + "CMT_FIFO_LH5_1", + "CMT_TOP_LH5_2" + ], + [ + "CMT_FIFO_WW4C0_3", + "CMT_TOP_WW4C0_4" + ], + [ + "CMT_FIFO_WW4END1_4", + "CMT_TOP_WW4END1_5" + ], + [ + "CMT_FIFO_WW4A3_6", + "CMT_TOP_WW4A3_7" + ], + [ + "CMT_FIFO_L_IMUX36_6", + "CMT_TOP_IMUX36_7" + ], + [ + "CMT_FIFO_EE4BEG0_5", + "CMT_TOP_EE4BEG0_6" + ], + [ + "CMT_FIFO_EE2A0_3", + "CMT_TOP_EE2A0_4" + ], + [ + "CMT_FIFO_SE4BEG3_9", + "CMT_TOP_SE4BEG3_10" + ], + [ + "CMT_FIFO_L_IMUX18_9", + "CMT_TOP_IMUX18_10" + ], + [ + "CMT_FIFO_L_CTRL0_4", + "CMT_TOP_CTRL0_5" + ], + [ + "CMT_FIFO_NW2A3_7", + "CMT_TOP_NW2A3_8" + ], + [ + "CMT_FIFO_SE4BEG0_4", + "CMT_TOP_SE4BEG0_5" + ], + [ + "CMT_FIFO_EE4A2_6", + "CMT_TOP_EE4A2_7" + ], + [ + "CMT_FIFO_EE4B0_11", + "CMT_TOP_EE4B0_12" + ], + [ + "CMT_FIFO_L_FAN1_1", + "CMT_TOP_FAN1_2" + ], + [ + "CMT_FIFO_EE4B2_2", + "CMT_TOP_EE4B2_3" + ], + [ + "CMT_FIFO_EE2BEG3_4", + "CMT_TOP_EE2BEG3_5" + ], + [ + "CMT_FIFO_WW2A2_6", + "CMT_TOP_WW2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_1", + "CMT_TOP_LOGIC_OUTS_L_B19_2" + ], + [ + "CMT_FIFO_L_IMUX0_1", + "CMT_TOP_IMUX0_2" + ], + [ + "CMT_FIFO_SW4A3_0", + "CMT_TOP_SW4A3_1" + ], + [ + "CMT_FIFO_SE2A0_8", + "CMT_TOP_SE2A0_9" + ], + [ + "CMT_FIFO_L_CLK0_7", + "CMT_TOP_CLK0_8" + ], + [ + "CMT_FIFO_SE4C3_4", + "CMT_TOP_SE4C3_5" + ], + [ + "CMT_FIFO_EE2BEG0_7", + "CMT_TOP_EE2BEG0_8" + ], + [ + "CMT_FIFO_WW4B3_10", + "CMT_TOP_WW4B3_11" + ], + [ + "CMT_FIFO_L_BYP5_7", + "CMT_TOP_BYP5_8" + ], + [ + "CMT_FIFO_L_IMUX1_0", + "CMT_TOP_IMUX1_1" + ], + [ + "CMT_FIFO_EE4B0_4", + "CMT_TOP_EE4B0_5" + ], + [ + "CMT_FIFO_NW4END0_11", + "CMT_TOP_NW4END0_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_6", + "CMT_TOP_LOGIC_OUTS_L_B2_7" + ], + [ + "CMT_FIFO_NE2A2_3", + "CMT_TOP_NE2A2_4" + ], + [ + "CMT_FIFO_EL1BEG2_8", + "CMT_TOP_EL1BEG2_9" + ], + [ + "CMT_FIFO_L_IMUX0_9", + "CMT_TOP_IMUX0_10" + ], + [ + "CMT_FIFO_SW4END1_11", + "CMT_TOP_SW4END1_12" + ], + [ + "CMT_FIFO_L_IMUX3_1", + "CMT_TOP_IMUX3_2" + ], + [ + "CMT_FIFO_L_IMUX12_1", + "CMT_TOP_IMUX12_2" + ], + [ + "CMT_FIFO_ER1BEG3_9", + "CMT_TOP_ER1BEG3_10" + ], + [ + "CMT_FIFO_SE4BEG2_5", + "CMT_TOP_SE4BEG2_6" + ], + [ + "CMT_FIFO_SE4C2_8", + "CMT_TOP_SE4C2_9" + ], + [ + "CMT_FIFO_ER1BEG3_1", + "CMT_TOP_ER1BEG3_2" + ], + [ + "CMT_FIFO_EE4B1_6", + "CMT_TOP_EE4B1_7" + ], + [ + "CMT_FIFO_WW4END2_6", + "CMT_TOP_WW4END2_7" + ], + [ + "CMT_FIFO_L_FAN1_6", + "CMT_TOP_FAN1_7" + ], + [ + "CMT_FIFO_L_IMUX47_5", + "CMT_TOP_IMUX47_6" + ], + [ + "CMT_FIFO_NW2A3_5", + "CMT_TOP_NW2A3_6" + ], + [ + "CMT_FIFO_EE2BEG3_6", + "CMT_TOP_EE2BEG3_7" + ], + [ + "CMT_FIFO_WW2A2_7", + "CMT_TOP_WW2A2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_11" + ], + [ + "CMT_FIFO_L_IMUX1_8", + "CMT_TOP_IMUX1_9" + ], + [ + "CMT_FIFO_SW4END0_10", + "CMT_TOP_SW4END0_11" + ], + [ + "CMT_FIFO_WW4B0_8", + "CMT_TOP_WW4B0_9" + ], + [ + "CMT_FIFO_SW4A0_2", + "CMT_TOP_SW4A0_3" + ], + [ + "CMT_FIFO_SE4BEG1_6", + "CMT_TOP_SE4BEG1_7" + ], + [ + "CMT_FIFO_L_IMUX45_0", + "CMT_TOP_IMUX45_1" + ], + [ + "CMT_FIFO_L_BYP4_5", + "CMT_TOP_BYP4_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_9", + "CMT_TOP_LOGIC_OUTS_L_B18_10" + ], + [ + "CMT_FIFO_EL1BEG1_4", + "CMT_TOP_EL1BEG1_5" + ], + [ + "CMT_FIFO_SE4BEG2_3", + "CMT_TOP_SE4BEG2_4" + ], + [ + "CMT_FIFO_L_CLK1_3", + "CMT_TOP_CLK1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_7", + "CMT_TOP_LOGIC_OUTS_L_B8_8" + ], + [ + "CMT_FIFO_L_IMUX46_10", + "CMT_TOP_IMUX46_11" + ], + [ + "CMT_FIFO_SE2A2_10", + "CMT_TOP_SE2A2_11" + ], + [ + "CMT_FIFO_SE4C1_0", + "CMT_TOP_SE4C1_1" + ], + [ + "CMT_FIFO_SW4A1_2", + "CMT_TOP_SW4A1_3" + ], + [ + "CMT_FIFO_WW2END0_10", + "CMT_TOP_WW2END0_11" + ], + [ + "CMT_FIFO_L_IMUX10_11", + "CMT_TOP_IMUX10_12" + ], + [ + "CMT_FIFO_L_IMUX15_10", + "CMT_TOP_IMUX15_11" + ], + [ + "CMT_FIFO_ER1BEG3_6", + "CMT_TOP_ER1BEG3_7" + ], + [ + "CMT_FIFO_L_FAN1_4", + "CMT_TOP_FAN1_5" + ], + [ + "CMT_FIFO_LH1_6", + "CMT_TOP_LH1_7" + ], + [ + "CMT_FIFO_NW4A2_2", + "CMT_TOP_NW4A2_3" + ], + [ + "CMT_FIFO_NW2A3_4", + "CMT_TOP_NW2A3_5" + ], + [ + "CMT_FIFO_L_IMUX19_0", + "CMT_TOP_IMUX19_1" + ], + [ + "CMT_FIFO_SE4BEG0_6", + "CMT_TOP_SE4BEG0_7" + ], + [ + "CMT_FIFO_NE4BEG1_3", + "CMT_TOP_NE4BEG1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_5", + "CMT_TOP_LOGIC_OUTS_L_B5_6" + ], + [ + "CMT_FIFO_NE4C1_8", + "CMT_TOP_NE4C1_9" + ], + [ + "CMT_FIFO_L_FAN7_3", + "CMT_TOP_FAN7_4" + ], + [ + "CMT_FIFO_L_IMUX4_8", + "CMT_TOP_IMUX4_9" + ], + [ + "CMT_FIFO_NE4BEG2_1", + "CMT_TOP_NE4BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX28_2", + "CMT_TOP_IMUX28_3" + ], + [ + "CMT_FIFO_WR1END0_0", + "CMT_TOP_WR1END0_1" + ], + [ + "CMT_FIFO_L_IMUX36_1", + "CMT_TOP_IMUX36_2" + ], + [ + "CMT_FIFO_SW4A1_1", + "CMT_TOP_SW4A1_2" + ], + [ + "CMT_FIFO_WW4END1_3", + "CMT_TOP_WW4END1_4" + ], + [ + "CMT_FIFO_L_FAN1_9", + "CMT_TOP_FAN1_10" + ], + [ + "CMT_FIFO_WR1END2_6", + "CMT_TOP_WR1END2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_8", + "CMT_TOP_LOGIC_OUTS_L_B2_9" + ], + [ + "CMT_FIFO_SE4C1_9", + "CMT_TOP_SE4C1_10" + ], + [ + "CMT_FIFO_L_IMUX7_4", + "CMT_TOP_IMUX7_5" + ], + [ + "CMT_FIFO_EE4C3_2", + "CMT_TOP_EE4C3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_8", + "CMT_TOP_LOGIC_OUTS_L_B7_9" + ], + [ + "CMT_FIFO_LH10_0", + "CMT_TOP_LH10_1" + ], + [ + "CMT_FIFO_EE4C3_4", + "CMT_TOP_EE4C3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_7", + "CMT_TOP_LOGIC_OUTS_L_B10_8" + ], + [ + "CMT_FIFO_WL1END3_4", + "CMT_TOP_WL1END3_5" + ], + [ + "CMT_FIFO_L_IMUX33_2", + "CMT_TOP_IMUX33_3" + ], + [ + "CMT_FIFO_L_IMUX18_8", + "CMT_TOP_IMUX18_9" + ], + [ + "CMT_FIFO_WW4C0_9", + "CMT_TOP_WW4C0_10" + ], + [ + "CMT_FIFO_L_IMUX32_3", + "CMT_TOP_IMUX32_4" + ], + [ + "CMT_FIFO_LH12_6", + "CMT_TOP_LH12_7" + ], + [ + "CMT_FIFO_WW4C1_8", + "CMT_TOP_WW4C1_9" + ], + [ + "CMT_FIFO_L_FAN6_0", + "CMT_TOP_FAN6_1" + ], + [ + "CMT_FIFO_L_IMUX10_5", + "CMT_TOP_IMUX10_6" + ], + [ + "CMT_FIFO_WL1END2_1", + "CMT_TOP_WL1END2_2" + ], + [ + "CMT_FIFO_L_IMUX21_8", + "CMT_TOP_IMUX21_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_0", + "CMT_TOP_LOGIC_OUTS_L_B5_1" + ], + [ + "CMT_FIFO_SE2A2_1", + "CMT_TOP_SE2A2_2" + ], + [ + "CMT_FIFO_LH3_11", + "CMT_TOP_LH3_12" + ], + [ + "CMT_FIFO_SW4A3_11", + "CMT_TOP_SW4A3_12" + ], + [ + "CMT_FIFO_NE2A1_7", + "CMT_TOP_NE2A1_8" + ], + [ + "CMT_FIFO_LH1_1", + "CMT_TOP_LH1_2" + ], + [ + "CMT_FIFO_L_IMUX29_1", + "CMT_TOP_IMUX29_2" + ], + [ + "CMT_FIFO_L_FAN6_1", + "CMT_TOP_FAN6_2" + ], + [ + "CMT_FIFO_EE2BEG2_10", + "CMT_TOP_EE2BEG2_11" + ], + [ + "CMT_FIFO_NW4END2_7", + "CMT_TOP_NW4END2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_11", + "CMT_TOP_LOGIC_OUTS_L_B13_12" + ], + [ + "CMT_FIFO_L_BYP0_1", + "CMT_TOP_BYP0_2" + ], + [ + "CMT_FIFO_EE4A1_11", + "CMT_TOP_EE4A1_12" + ], + [ + "CMT_FIFO_L_IMUX30_8", + "CMT_TOP_IMUX30_9" + ], + [ + "CMT_FIFO_WL1END3_5", + "CMT_TOP_WL1END3_6" + ], + [ + "CMT_FIFO_L_IMUX45_2", + "CMT_TOP_IMUX45_3" + ], + [ + "CMT_FIFO_L_FAN6_5", + "CMT_TOP_FAN6_6" + ], + [ + "CMT_FIFO_WL1END2_8", + "CMT_TOP_WL1END2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_1", + "CMT_TOP_LOGIC_OUTS_L_B4_2" + ], + [ + "CMT_FIFO_EE4A2_5", + "CMT_TOP_EE4A2_6" + ], + [ + "CMT_FIFO_WL1END2_10", + "CMT_TOP_WL1END2_11" + ], + [ + "CMT_FIFO_L_IMUX24_8", + "CMT_TOP_IMUX24_9" + ], + [ + "CMT_FIFO_LH11_5", + "CMT_TOP_LH11_6" + ], + [ + "CMT_FIFO_NW2A2_1", + "CMT_TOP_NW2A2_2" + ], + [ + "CMT_FIFO_L_BYP6_1", + "CMT_TOP_BYP6_2" + ], + [ + "CMT_FIFO_SE2A0_1", + "CMT_TOP_SE2A0_2" + ], + [ + "CMT_FIFO_SE2A3_9", + "CMT_TOP_SE2A3_10" + ], + [ + "CMT_FIFO_L_IMUX47_11", + "CMT_TOP_IMUX47_12" + ], + [ + "CMT_FIFO_EE4A2_8", + "CMT_TOP_EE4A2_9" + ], + [ + "CMT_FIFO_L_BYP2_4", + "CMT_TOP_BYP2_5" + ], + [ + "CMT_FIFO_L_BYP2_8", + "CMT_TOP_BYP2_9" + ], + [ + "CMT_FIFO_L_IMUX41_11", + "CMT_TOP_IMUX41_12" + ], + [ + "CMT_FIFO_SE2A2_5", + "CMT_TOP_SE2A2_6" + ], + [ + "CMT_FIFO_L_IMUX35_6", + "CMT_TOP_IMUX35_7" + ], + [ + "CMT_FIFO_L_FAN7_6", + "CMT_TOP_FAN7_7" + ], + [ + "CMT_FIFO_L_BYP7_8", + "CMT_TOP_BYP7_9" + ], + [ + "CMT_FIFO_SE4C0_9", + "CMT_TOP_SE4C0_10" + ], + [ + "CMT_FIFO_EE4C3_6", + "CMT_TOP_EE4C3_7" + ], + [ + "CMT_FIFO_EL1BEG1_3", + "CMT_TOP_EL1BEG1_4" + ], + [ + "CMT_FIFO_SE4BEG2_4", + "CMT_TOP_SE4BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX25_0", + "CMT_TOP_IMUX25_1" + ], + [ + "CMT_FIFO_L_IMUX29_6", + "CMT_TOP_IMUX29_7" + ], + [ + "CMT_FIFO_L_BYP6_6", + "CMT_TOP_BYP6_7" + ], + [ + "CMT_FIFO_L_IMUX1_10", + "CMT_TOP_IMUX1_11" + ], + [ + "CMT_FIFO_L_IMUX35_4", + "CMT_TOP_IMUX35_5" + ], + [ + "CMT_FIFO_EL1BEG1_5", + "CMT_TOP_EL1BEG1_6" + ], + [ + "CMT_FIFO_L_CLK1_5", + "CMT_TOP_CLK1_6" + ], + [ + "CMT_FIFO_L_BYP5_5", + "CMT_TOP_BYP5_6" + ], + [ + "CMT_FIFO_EE2BEG1_6", + "CMT_TOP_EE2BEG1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_9", + "CMT_TOP_LOGIC_OUTS_L_B4_10" + ], + [ + "CMT_FIFO_WW4B2_0", + "CMT_TOP_WW4B2_1" + ], + [ + "CMT_FIFO_SW4A3_1", + "CMT_TOP_SW4A3_2" + ], + [ + "CMT_FIFO_L_PHASER_WRENABLE", + "CMT_MMCM_A_WREN_TOFIFO" + ], + [ + "CMT_FIFO_NE4BEG2_9", + "CMT_TOP_NE4BEG2_10" + ], + [ + "CMT_FIFO_WW4A2_4", + "CMT_TOP_WW4A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_0", + "CMT_TOP_LOGIC_OUTS_L_B13_1" + ], + [ + "CMT_FIFO_SW4A2_11", + "CMT_TOP_SW4A2_12" + ], + [ + "CMT_FIFO_EE4BEG2_8", + "CMT_TOP_EE4BEG2_9" + ], + [ + "CMT_FIFO_L_FAN4_10", + "CMT_TOP_FAN4_11" + ], + [ + "CMT_FIFO_EE4C0_2", + "CMT_TOP_EE4C0_3" + ], + [ + "CMT_FIFO_L_IMUX39_0", + "CMT_TOP_IMUX39_1" + ], + [ + "CMT_FIFO_EE4BEG1_11", + "CMT_TOP_EE4BEG1_12" + ], + [ + "CMT_FIFO_SE2A3_8", + "CMT_TOP_SE2A3_9" + ], + [ + "CMT_FIFO_WW4C1_6", + "CMT_TOP_WW4C1_7" + ], + [ + "CMT_FIFO_EE4C2_0", + "CMT_TOP_EE4C2_1" + ], + [ + "CMT_FIFO_SW2A2_8", + "CMT_TOP_SW2A2_9" + ], + [ + "CMT_FIFO_EE2A3_9", + "CMT_TOP_EE2A3_10" + ], + [ + "CMT_FIFO_LH1_2", + "CMT_TOP_LH1_3" + ], + [ + "CMT_FIFO_L_IMUX41_9", + "CMT_TOP_IMUX41_10" + ], + [ + "CMT_FIFO_L_IMUX29_2", + "CMT_TOP_IMUX29_3" + ], + [ + "CMT_FIFO_NW4END3_10", + "CMT_TOP_NW4END3_11" + ], + [ + "CMT_FIFO_L_IMUX13_0", + "CMT_TOP_IMUX13_1" + ], + [ + "CMT_FIFO_SW2A2_2", + "CMT_TOP_SW2A2_3" + ], + [ + "CMT_FIFO_L_IMUX33_10", + "CMT_TOP_IMUX33_11" + ], + [ + "CMT_FIFO_SE4C0_5", + "CMT_TOP_SE4C0_6" + ], + [ + "CMT_FIFO_SW4END0_7", + "CMT_TOP_SW4END0_8" + ], + [ + "CMT_FIFO_L_IMUX16_3", + "CMT_TOP_IMUX16_4" + ], + [ + "CMT_FIFO_WW2A0_0", + "CMT_TOP_WW2A0_1" + ], + [ + "CMT_FIFO_L_IMUX21_2", + "CMT_TOP_IMUX21_3" + ], + [ + "CMT_FIFO_EL1BEG1_8", + "CMT_TOP_EL1BEG1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_4", + "CMT_TOP_LOGIC_OUTS_L_B1_5" + ], + [ + "CMT_FIFO_L_IMUX1_11", + "CMT_TOP_IMUX1_12" + ], + [ + "CMT_FIFO_L_IMUX41_1", + "CMT_TOP_IMUX41_2" + ], + [ + "CMT_FIFO_SW2A3_0", + "CMT_TOP_SW2A3_1" + ], + [ + "CMT_FIFO_L_PHASER_RDCLK", + "CMT_MMCM_A_RDCLK_TOFIFO" + ], + [ + "CMT_FIFO_SE4BEG0_2", + "CMT_TOP_SE4BEG0_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "CMT_TOP_OCLKDIV_9" + ], + [ + "CMT_FIFO_L_BYP7_11", + "CMT_TOP_BYP7_12" + ], + [ + "CMT_FIFO_WL1END0_7", + "CMT_TOP_WL1END0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_0", + "CMT_TOP_LOGIC_OUTS_L_B1_1" + ], + [ + "CMT_FIFO_L_IMUX33_4", + "CMT_TOP_IMUX33_5" + ], + [ + "CMT_FIFO_WL1END2_9", + "CMT_TOP_WL1END2_10" + ], + [ + "CMT_FIFO_WW2END0_8", + "CMT_TOP_WW2END0_9" + ], + [ + "CMT_FIFO_WW4A0_6", + "CMT_TOP_WW4A0_7" + ], + [ + "CMT_FIFO_L_CTRL0_3", + "CMT_TOP_CTRL0_4" + ], + [ + "CMT_FIFO_L_IMUX6_11", + "CMT_TOP_IMUX6_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_8", + "CMT_TOP_LOGIC_OUTS_L_B19_9" + ], + [ + "CMT_FIFO_NE4C1_9", + "CMT_TOP_NE4C1_10" + ], + [ + "CMT_FIFO_EE4A2_2", + "CMT_TOP_EE4A2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_5", + "CMT_TOP_LOGIC_OUTS_L_B7_6" + ], + [ + "CMT_FIFO_L_FAN2_0", + "CMT_TOP_FAN2_1" + ], + [ + "CMT_FIFO_SW4A1_4", + "CMT_TOP_SW4A1_5" + ], + [ + "CMT_FIFO_L_IMUX43_9", + "CMT_TOP_IMUX43_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_8", + "CMT_TOP_LOGIC_OUTS_L_B20_9" + ], + [ + "CMT_FIFO_L_IMUX34_6", + "CMT_TOP_IMUX34_7" + ], + [ + "CMT_FIFO_L_IMUX46_2", + "CMT_TOP_IMUX46_3" + ], + [ + "CMT_FIFO_L_IMUX47_4", + "CMT_TOP_IMUX47_5" + ], + [ + "CMT_FIFO_LH3_8", + "CMT_TOP_LH3_9" + ], + [ + "CMT_FIFO_L_IMUX2_6", + "CMT_TOP_IMUX2_7" + ], + [ + "CMT_FIFO_L_FAN2_10", + "CMT_TOP_FAN2_11" + ], + [ + "CMT_FIFO_WW4END0_10", + "CMT_TOP_WW4END0_11" + ], + [ + "CMT_FIFO_SE4C1_2", + "CMT_TOP_SE4C1_3" + ], + [ + "CMT_FIFO_L_IMUX42_10", + "CMT_TOP_IMUX42_11" + ], + [ + "CMT_FIFO_SW4END1_6", + "CMT_TOP_SW4END1_7" + ], + [ + "CMT_FIFO_L_BYP7_6", + "CMT_TOP_BYP7_7" + ], + [ + "CMT_FIFO_NE4C3_0", + "CMT_TOP_NE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX45_5", + "CMT_TOP_IMUX45_6" + ], + [ + "CMT_FIFO_L_IMUX39_3", + "CMT_TOP_IMUX39_4" + ], + [ + "CMT_FIFO_L_IMUX30_1", + "CMT_TOP_IMUX30_2" + ], + [ + "CMT_FIFO_EL1BEG2_11", + "CMT_TOP_EL1BEG2_12" + ], + [ + "CMT_FIFO_L_IMUX31_10", + "CMT_TOP_IMUX31_11" + ], + [ + "CMT_FIFO_L_IMUX31_9", + "CMT_TOP_IMUX31_10" + ], + [ + "CMT_FIFO_L_IMUX6_1", + "CMT_TOP_IMUX6_2" + ], + [ + "CMT_FIFO_SW2A2_11", + "CMT_TOP_SW2A2_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_1", + "CMT_TOP_LOGIC_OUTS_L_B11_2" + ], + [ + "CMT_FIFO_L_IMUX11_7", + "CMT_TOP_IMUX11_8" + ], + [ + "CMT_FIFO_L_IMUX37_4", + "CMT_TOP_IMUX37_5" + ], + [ + "CMT_FIFO_EL1BEG1_1", + "CMT_TOP_EL1BEG1_2" + ], + [ + "CMT_FIFO_LH7_10", + "CMT_TOP_LH7_11" + ], + [ + "CMT_FIFO_EE2A1_7", + "CMT_TOP_EE2A1_8" + ], + [ + "CMT_FIFO_EE4BEG2_0", + "CMT_TOP_EE4BEG2_1" + ], + [ + "CMT_FIFO_EE2BEG1_1", + "CMT_TOP_EE2BEG1_2" + ], + [ + "CMT_FIFO_L_IMUX24_6", + "CMT_TOP_IMUX24_7" + ], + [ + "CMT_FIFO_EE4BEG0_10", + "CMT_TOP_EE4BEG0_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "CMT_TOP_OCLKDIV_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "CMT_TOP_ICLKDIV_5" + ], + [ + "CMT_FIFO_L_IMUX20_8", + "CMT_TOP_IMUX20_9" + ], + [ + "CMT_FIFO_LH3_0", + "CMT_TOP_LH3_1" + ], + [ + "CMT_FIFO_SW2A0_2", + "CMT_TOP_SW2A0_3" + ], + [ + "CMT_FIFO_WW2A3_6", + "CMT_TOP_WW2A3_7" + ], + [ + "CMT_FIFO_L_IMUX22_1", + "CMT_TOP_IMUX22_2" + ], + [ + "CMT_FIFO_LH8_7", + "CMT_TOP_LH8_8" + ], + [ + "CMT_FIFO_L_IMUX45_1", + "CMT_TOP_IMUX45_2" + ], + [ + "CMT_FIFO_EE4A0_1", + "CMT_TOP_EE4A0_2" + ], + [ + "CMT_FIFO_WW2END1_5", + "CMT_TOP_WW2END1_6" + ], + [ + "CMT_FIFO_L_BYP1_6", + "CMT_TOP_BYP1_7" + ], + [ + "CMT_FIFO_SW4A3_4", + "CMT_TOP_SW4A3_5" + ], + [ + "CMT_FIFO_L_CLK0_3", + "CMT_TOP_CLK0_4" + ], + [ + "CMT_FIFO_ER1BEG2_9", + "CMT_TOP_ER1BEG2_10" + ], + [ + "CMT_FIFO_NE4BEG2_4", + "CMT_TOP_NE4BEG2_5" + ], + [ + "CMT_FIFO_SW4END0_5", + "CMT_TOP_SW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX0_10", + "CMT_TOP_IMUX0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_3", + "CMT_TOP_LOGIC_OUTS_L_B23_4" + ], + [ + "CMT_FIFO_L_IMUX26_9", + "CMT_TOP_IMUX26_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_10", + "CMT_TOP_LOGIC_OUTS_L_B11_11" + ], + [ + "CMT_FIFO_EE4B0_1", + "CMT_TOP_EE4B0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_8", + "CMT_TOP_LOGIC_OUTS_L_B13_9" + ], + [ + "CMT_FIFO_EE4B2_10", + "CMT_TOP_EE4B2_11" + ], + [ + "CMT_FIFO_L_IMUX4_11", + "CMT_TOP_IMUX4_12" + ], + [ + "CMT_FIFO_NW2A1_5", + "CMT_TOP_NW2A1_6" + ], + [ + "CMT_FIFO_L_IMUX17_8", + "CMT_TOP_IMUX17_9" + ], + [ + "CMT_FIFO_EL1BEG3_1", + "CMT_TOP_EL1BEG3_2" + ], + [ + "CMT_FIFO_L_BYP1_1", + "CMT_TOP_BYP1_2" + ], + [ + "CMT_FIFO_L_IMUX38_3", + "CMT_TOP_IMUX38_4" + ], + [ + "CMT_FIFO_WW4END1_10", + "CMT_TOP_WW4END1_11" + ], + [ + "CMT_FIFO_SW4A0_8", + "CMT_TOP_SW4A0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_6", + "CMT_TOP_LOGIC_OUTS_L_B6_7" + ], + [ + "CMT_FIFO_L_IMUX40_5", + "CMT_TOP_IMUX40_6" + ], + [ + "CMT_FIFO_WW2A0_6", + "CMT_TOP_WW2A0_7" + ], + [ + "CMT_FIFO_LH1_7", + "CMT_TOP_LH1_8" + ], + [ + "CMT_FIFO_L_IMUX17_1", + "CMT_TOP_IMUX17_2" + ], + [ + "CMT_FIFO_L_IMUX43_2", + "CMT_TOP_IMUX43_3" + ], + [ + "CMT_FIFO_L_BYP2_6", + "CMT_TOP_BYP2_7" + ], + [ + "CMT_FIFO_SW2A0_3", + "CMT_TOP_SW2A0_4" + ], + [ + "CMT_FIFO_L_IMUX16_8", + "CMT_TOP_IMUX16_9" + ], + [ + "CMT_FIFO_EE4C3_7", + "CMT_TOP_EE4C3_8" + ], + [ + "CMT_FIFO_SE4C1_4", + "CMT_TOP_SE4C1_5" + ], + [ + "CMT_FIFO_EE2A1_1", + "CMT_TOP_EE2A1_2" + ], + [ + "CMT_FIFO_L_IMUX17_11", + "CMT_TOP_IMUX17_12" + ], + [ + "CMT_FIFO_NW2A3_11", + "CMT_TOP_NW2A3_12" + ], + [ + "CMT_FIFO_L_IMUX44_11", + "CMT_TOP_IMUX44_12" + ], + [ + "CMT_FIFO_WW2END3_7", + "CMT_TOP_WW2END3_8" + ], + [ + "CMT_FIFO_NW2A2_9", + "CMT_TOP_NW2A2_10" + ], + [ + "CMT_FIFO_WR1END2_3", + "CMT_TOP_WR1END2_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "CMT_TOP_ICLK_4" + ], + [ + "CMT_FIFO_WW4A2_10", + "CMT_TOP_WW4A2_11" + ], + [ + "CMT_FIFO_EL1BEG0_4", + "CMT_TOP_EL1BEG0_5" + ], + [ + "CMT_FIFO_WR1END3_1", + "CMT_TOP_WR1END3_2" + ], + [ + "CMT_FIFO_WW4C1_10", + "CMT_TOP_WW4C1_11" + ], + [ + "CMT_FIFO_LH8_0", + "CMT_TOP_LH8_1" + ], + [ + "CMT_FIFO_ER1BEG1_4", + "CMT_TOP_ER1BEG1_5" + ], + [ + "CMT_FIFO_WR1END0_2", + "CMT_TOP_WR1END0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_2", + "CMT_TOP_LOGIC_OUTS_L_B23_3" + ], + [ + "CMT_FIFO_SW4A2_9", + "CMT_TOP_SW4A2_10" + ], + [ + "CMT_FIFO_L_FAN0_3", + "CMT_TOP_FAN0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_2", + "CMT_TOP_LOGIC_OUTS_L_B12_3" + ], + [ + "CMT_FIFO_SW4A2_10", + "CMT_TOP_SW4A2_11" + ], + [ + "CMT_FIFO_L_IMUX37_9", + "CMT_TOP_IMUX37_10" + ], + [ + "CMT_FIFO_L_IMUX5_10", + "CMT_TOP_IMUX5_11" + ], + [ + "CMT_FIFO_L_IMUX6_5", + "CMT_TOP_IMUX6_6" + ], + [ + "CMT_FIFO_SE4C2_4", + "CMT_TOP_SE4C2_5" + ], + [ + "CMT_FIFO_WR1END1_5", + "CMT_TOP_WR1END1_6" + ], + [ + "CMT_FIFO_NE4BEG0_9", + "CMT_TOP_NE4BEG0_10" + ], + [ + "CMT_FIFO_L_IMUX35_0", + "CMT_TOP_IMUX35_1" + ], + [ + "CMT_FIFO_L_CTRL0_6", + "CMT_TOP_CTRL0_7" + ], + [ + "CMT_FIFO_WW4END3_0", + "CMT_TOP_WW4END3_1" + ], + [ + "CMT_FIFO_WW2END2_5", + "CMT_TOP_WW2END2_6" + ], + [ + "CMT_FIFO_LH10_5", + "CMT_TOP_LH10_6" + ], + [ + "CMT_FIFO_L_CTRL0_9", + "CMT_TOP_CTRL0_10" + ], + [ + "CMT_FIFO_L_IMUX23_10", + "CMT_TOP_IMUX23_11" + ], + [ + "CMT_FIFO_L_IMUX15_9", + "CMT_TOP_IMUX15_10" + ], + [ + "CMT_FIFO_NE2A1_8", + "CMT_TOP_NE2A1_9" + ], + [ + "CMT_FIFO_SE2A1_8", + "CMT_TOP_SE2A1_9" + ], + [ + "CMT_FIFO_L_FAN7_4", + "CMT_TOP_FAN7_5" + ], + [ + "CMT_FIFO_L_IMUX7_8", + "CMT_TOP_IMUX7_9" + ], + [ + "CMT_FIFO_L_BYP7_7", + "CMT_TOP_BYP7_8" + ], + [ + "CMT_FIFO_WW4C3_5", + "CMT_TOP_WW4C3_6" + ], + [ + "CMT_FIFO_L_IMUX13_3", + "CMT_TOP_IMUX13_4" + ], + [ + "CMT_FIFO_L_IMUX18_0", + "CMT_TOP_IMUX18_1" + ], + [ + "CMT_FIFO_SE4C0_0", + "CMT_TOP_SE4C0_1" + ], + [ + "CMT_FIFO_WW2END2_11", + "CMT_TOP_WW2END2_12" + ], + [ + "CMT_FIFO_L_IMUX24_9", + "CMT_TOP_IMUX24_10" + ], + [ + "CMT_FIFO_NW4A0_9", + "CMT_TOP_NW4A0_10" + ], + [ + "CMT_FIFO_LH6_6", + "CMT_TOP_LH6_7" + ], + [ + "CMT_FIFO_EL1BEG1_7", + "CMT_TOP_EL1BEG1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_4", + "CMT_TOP_LOGIC_OUTS_L_B7_5" + ], + [ + "CMT_FIFO_NE4BEG0_4", + "CMT_TOP_NE4BEG0_5" + ], + [ + "CMT_FIFO_LH1_8", + "CMT_TOP_LH1_9" + ], + [ + "CMT_FIFO_WW4A3_8", + "CMT_TOP_WW4A3_9" + ], + [ + "CMT_FIFO_L_CTRL1_2", + "CMT_TOP_CTRL1_3" + ], + [ + "CMT_FIFO_L_FAN5_2", + "CMT_TOP_FAN5_3" + ], + [ + "CMT_FIFO_EE4A1_7", + "CMT_TOP_EE4A1_8" + ], + [ + "CMT_FIFO_NE4BEG1_10", + "CMT_TOP_NE4BEG1_11" + ], + [ + "CMT_FIFO_SE4C0_10", + "CMT_TOP_SE4C0_11" + ], + [ + "CMT_FIFO_LH7_3", + "CMT_TOP_LH7_4" + ], + [ + "CMT_FIFO_WL1END0_8", + "CMT_TOP_WL1END0_9" + ], + [ + "CMT_FIFO_SW4A3_2", + "CMT_TOP_SW4A3_3" + ], + [ + "CMT_FIFO_L_BYP5_6", + "CMT_TOP_BYP5_7" + ], + [ + "CMT_FIFO_L_BYP5_9", + "CMT_TOP_BYP5_10" + ], + [ + "CMT_FIFO_L_IMUX5_9", + "CMT_TOP_IMUX5_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_3", + "CMT_TOP_LOGIC_OUTS_L_B4_4" + ], + [ + "CMT_FIFO_NW4END3_7", + "CMT_TOP_NW4END3_8" + ], + [ + "CMT_FIFO_NE4BEG3_5", + "CMT_TOP_NE4BEG3_6" + ], + [ + "CMT_FIFO_MONITOR_N_8", + "CMT_TOP_MONITOR_N_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_0", + "CMT_TOP_LOGIC_OUTS_L_B11_1" + ], + [ + "CMT_FIFO_LH6_5", + "CMT_TOP_LH6_6" + ], + [ + "CMT_FIFO_WL1END0_11", + "CMT_TOP_WL1END0_12" + ], + [ + "CMT_FIFO_L_IMUX18_3", + "CMT_TOP_IMUX18_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_4" + ], + [ + "CMT_FIFO_LH2_3", + "CMT_TOP_LH2_4" + ], + [ + "CMT_FIFO_EE4B3_1", + "CMT_TOP_EE4B3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_9", + "CMT_TOP_LOGIC_OUTS_L_B11_10" + ], + [ + "CMT_FIFO_NE4C2_1", + "CMT_TOP_NE4C2_2" + ], + [ + "CMT_FIFO_L_IMUX8_7", + "CMT_TOP_IMUX8_8" + ], + [ + "CMT_FIFO_WR1END1_8", + "CMT_TOP_WR1END1_9" + ], + [ + "CMT_FIFO_WW4A1_8", + "CMT_TOP_WW4A1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_3", + "CMT_TOP_LOGIC_OUTS_L_B12_4" + ], + [ + "CMT_FIFO_EE2BEG3_5", + "CMT_TOP_EE2BEG3_6" + ], + [ + "CMT_FIFO_EE4C0_6", + "CMT_TOP_EE4C0_7" + ], + [ + "CMT_FIFO_ER1BEG3_3", + "CMT_TOP_ER1BEG3_4" + ], + [ + "CMT_FIFO_L_IMUX31_0", + "CMT_TOP_IMUX31_1" + ], + [ + "CMT_FIFO_WW4B0_6", + "CMT_TOP_WW4B0_7" + ], + [ + "CMT_FIFO_NE4BEG3_1", + "CMT_TOP_NE4BEG3_2" + ], + [ + "CMT_FIFO_LH8_1", + "CMT_TOP_LH8_2" + ], + [ + "CMT_FIFO_EE4B3_9", + "CMT_TOP_EE4B3_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "CMT_TOP_OCLK_1" + ], + [ + "CMT_FIFO_L_IMUX45_3", + "CMT_TOP_IMUX45_4" + ], + [ + "CMT_FIFO_L_IMUX37_11", + "CMT_TOP_IMUX37_12" + ], + [ + "CMT_FIFO_ER1BEG0_11", + "CMT_TOP_ER1BEG0_12" + ], + [ + "CMT_FIFO_WW2END3_9", + "CMT_TOP_WW2END3_10" + ], + [ + "CMT_FIFO_EE4B3_11", + "CMT_TOP_EE4B3_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_3", + "CMT_TOP_LOGIC_OUTS_L_B2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_9", + "CMT_TOP_LOGIC_OUTS_L_B15_10" + ], + [ + "CMT_FIFO_L_CLK0_9", + "CMT_TOP_CLK0_10" + ], + [ + "CMT_FIFO_NW4END1_2", + "CMT_TOP_NW4END1_3" + ], + [ + "CMT_FIFO_WW4A3_9", + "CMT_TOP_WW4A3_10" + ], + [ + "CMT_FIFO_NE4BEG0_0", + "CMT_TOP_NE4BEG0_1" + ], + [ + "CMT_FIFO_L_IMUX20_10", + "CMT_TOP_IMUX20_11" + ], + [ + "CMT_FIFO_L_IMUX34_3", + "CMT_TOP_IMUX34_4" + ], + [ + "CMT_FIFO_L_IMUX27_6", + "CMT_TOP_IMUX27_7" + ], + [ + "CMT_FIFO_WL1END1_4", + "CMT_TOP_WL1END1_5" + ], + [ + "CMT_FIFO_EE4C3_9", + "CMT_TOP_EE4C3_10" + ], + [ + "CMT_FIFO_NE4C2_11", + "CMT_TOP_NE4C2_12" + ], + [ + "CMT_FIFO_WL1END2_6", + "CMT_TOP_WL1END2_7" + ], + [ + "CMT_FIFO_EE4C0_7", + "CMT_TOP_EE4C0_8" + ], + [ + "CMT_FIFO_WR1END2_7", + "CMT_TOP_WR1END2_8" + ], + [ + "CMT_FIFO_L_IMUX40_8", + "CMT_TOP_IMUX40_9" + ], + [ + "CMT_FIFO_EE4C1_5", + "CMT_TOP_EE4C1_6" + ], + [ + "CMT_FIFO_L_IMUX34_11", + "CMT_TOP_IMUX34_12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "CMT_TOP_OCLK_11" + ], + [ + "CMT_FIFO_EE4B3_0", + "CMT_TOP_EE4B3_1" + ], + [ + "CMT_FIFO_L_IMUX7_11", + "CMT_TOP_IMUX7_12" + ], + [ + "CMT_FIFO_L_CLK1_2", + "CMT_TOP_CLK1_3" + ], + [ + "CMT_FIFO_L_IMUX34_0", + "CMT_TOP_IMUX34_1" + ], + [ + "CMT_FIFO_LH11_1", + "CMT_TOP_LH11_2" + ], + [ + "CMT_FIFO_NW4A3_10", + "CMT_TOP_NW4A3_11" + ], + [ + "CMT_FIFO_WL1END2_7", + "CMT_TOP_WL1END2_8" + ], + [ + "CMT_FIFO_SE2A2_6", + "CMT_TOP_SE2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_2", + "CMT_TOP_LOGIC_OUTS_L_B17_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_5", + "CMT_TOP_LOGIC_OUTS_L_B19_6" + ], + [ + "CMT_FIFO_L_IMUX25_6", + "CMT_TOP_IMUX25_7" + ], + [ + "CMT_FIFO_EE4B0_10", + "CMT_TOP_EE4B0_11" + ], + [ + "CMT_FIFO_NE4C1_10", + "CMT_TOP_NE4C1_11" + ], + [ + "CMT_FIFO_L_FAN1_7", + "CMT_TOP_FAN1_8" + ], + [ + "CMT_FIFO_WW4END2_5", + "CMT_TOP_WW4END2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_10", + "CMT_TOP_LOGIC_OUTS_L_B22_11" + ], + [ + "CMT_FIFO_L_IMUX25_5", + "CMT_TOP_IMUX25_6" + ], + [ + "CMT_FIFO_NW4A2_8", + "CMT_TOP_NW4A2_9" + ], + [ + "CMT_FIFO_L_BYP5_4", + "CMT_TOP_BYP5_5" + ], + [ + "CMT_FIFO_L_FAN7_1", + "CMT_TOP_FAN7_2" + ], + [ + "CMT_FIFO_NW4END0_9", + "CMT_TOP_NW4END0_10" + ], + [ + "CMT_FIFO_NW2A0_0", + "CMT_TOP_NW2A0_1" + ], + [ + "CMT_FIFO_WL1END2_0", + "CMT_TOP_WL1END2_1" + ], + [ + "CMT_FIFO_SE4BEG1_7", + "CMT_TOP_SE4BEG1_8" + ], + [ + "CMT_FIFO_L_BYP2_3", + "CMT_TOP_BYP2_4" + ], + [ + "CMT_FIFO_NW4A0_5", + "CMT_TOP_NW4A0_6" + ], + [ + "CMT_FIFO_L_IMUX18_4", + "CMT_TOP_IMUX18_5" + ], + [ + "CMT_FIFO_L_IMUX22_9", + "CMT_TOP_IMUX22_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "CMT_TOP_ICLKDIV_9" + ], + [ + "CMT_FIFO_SE4C0_2", + "CMT_TOP_SE4C0_3" + ], + [ + "CMT_FIFO_EE4A3_0", + "CMT_TOP_EE4A3_1" + ], + [ + "CMT_FIFO_LH3_6", + "CMT_TOP_LH3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_3", + "CMT_TOP_LOGIC_OUTS_L_B5_4" + ], + [ + "CMT_FIFO_LH5_11", + "CMT_TOP_LH5_12" + ], + [ + "CMT_FIFO_L_IMUX7_7", + "CMT_TOP_IMUX7_8" + ], + [ + "CMT_FIFO_L_IMUX38_6", + "CMT_TOP_IMUX38_7" + ], + [ + "CMT_FIFO_L_IMUX18_5", + "CMT_TOP_IMUX18_6" + ], + [ + "CMT_FIFO_L_BYP7_4", + "CMT_TOP_BYP7_5" + ], + [ + "CMT_FIFO_LH3_4", + "CMT_TOP_LH3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_7", + "CMT_TOP_LOGIC_OUTS_L_B3_8" + ], + [ + "CMT_FIFO_EE4B2_8", + "CMT_TOP_EE4B2_9" + ], + [ + "CMT_FIFO_WL1END1_5", + "CMT_TOP_WL1END1_6" + ], + [ + "CMT_FIFO_WW4END2_0", + "CMT_TOP_WW4END2_1" + ], + [ + "CMT_FIFO_WW4END0_8", + "CMT_TOP_WW4END0_9" + ], + [ + "CMT_FIFO_L_IMUX35_1", + "CMT_TOP_IMUX35_2" + ], + [ + "CMT_FIFO_L_IMUX15_6", + "CMT_TOP_IMUX15_7" + ], + [ + "CMT_FIFO_EE4A1_10", + "CMT_TOP_EE4A1_11" + ], + [ + "CMT_FIFO_SW4A2_7", + "CMT_TOP_SW4A2_8" + ], + [ + "CMT_FIFO_L_IMUX12_2", + "CMT_TOP_IMUX12_3" + ], + [ + "CMT_FIFO_WL1END3_7", + "CMT_TOP_WL1END3_8" + ], + [ + "CMT_FIFO_EE2BEG0_3", + "CMT_TOP_EE2BEG0_4" + ], + [ + "CMT_FIFO_EE4B0_0", + "CMT_TOP_EE4B0_1" + ], + [ + "CMT_FIFO_EL1BEG3_5", + "CMT_TOP_EL1BEG3_6" + ], + [ + "CMT_FIFO_L_IMUX29_10", + "CMT_TOP_IMUX29_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_5", + "CMT_TOP_LOGIC_OUTS_L_B13_6" + ], + [ + "CMT_FIFO_NW2A2_0", + "CMT_TOP_NW2A2_1" + ], + [ + "CMT_FIFO_LH6_1", + "CMT_TOP_LH6_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_8", + "CMT_TOP_LOGIC_OUTS_L_B1_9" + ], + [ + "CMT_FIFO_NE4BEG3_9", + "CMT_TOP_NE4BEG3_10" + ], + [ + "CMT_FIFO_NW4END1_9", + "CMT_TOP_NW4END1_10" + ], + [ + "CMT_FIFO_L_IMUX40_3", + "CMT_TOP_IMUX40_4" + ], + [ + "CMT_FIFO_EE2A0_5", + "CMT_TOP_EE2A0_6" + ], + [ + "CMT_FIFO_SW2A3_8", + "CMT_TOP_SW2A3_9" + ], + [ + "CMT_FIFO_LH7_2", + "CMT_TOP_LH7_3" + ], + [ + "CMT_FIFO_SE4BEG1_9", + "CMT_TOP_SE4BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX3_7", + "CMT_TOP_IMUX3_8" + ], + [ + "CMT_FIFO_L_IMUX32_4", + "CMT_TOP_IMUX32_5" + ], + [ + "CMT_FIFO_ER1BEG0_7", + "CMT_TOP_ER1BEG0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_4", + "CMT_TOP_LOGIC_OUTS_L_B15_5" + ], + [ + "CMT_FIFO_SE4BEG2_8", + "CMT_TOP_SE4BEG2_9" + ], + [ + "CMT_FIFO_L_IMUX8_5", + "CMT_TOP_IMUX8_6" + ], + [ + "CMT_FIFO_EL1BEG3_11", + "CMT_TOP_EL1BEG3_12" + ], + [ + "CMT_FIFO_SW2A3_7", + "CMT_TOP_SW2A3_8" + ], + [ + "CMT_FIFO_L_IMUX44_2", + "CMT_TOP_IMUX44_3" + ], + [ + "CMT_FIFO_SW4END0_1", + "CMT_TOP_SW4END0_2" + ], + [ + "CMT_FIFO_L_IMUX38_2", + "CMT_TOP_IMUX38_3" + ], + [ + "CMT_FIFO_EE2BEG0_9", + "CMT_TOP_EE2BEG0_10" + ], + [ + "CMT_FIFO_EL1BEG2_6", + "CMT_TOP_EL1BEG2_7" + ], + [ + "CMT_FIFO_WW4A0_2", + "CMT_TOP_WW4A0_3" + ], + [ + "CMT_FIFO_LH5_0", + "CMT_TOP_LH5_1" + ], + [ + "CMT_FIFO_NE4BEG1_2", + "CMT_TOP_NE4BEG1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_1", + "CMT_TOP_LOGIC_OUTS_L_B13_2" + ], + [ + "CMT_FIFO_L_IMUX21_4", + "CMT_TOP_IMUX21_5" + ], + [ + "CMT_FIFO_SW4A3_9", + "CMT_TOP_SW4A3_10" + ], + [ + "CMT_FIFO_L_FAN2_1", + "CMT_TOP_FAN2_2" + ], + [ + "CMT_FIFO_LH11_9", + "CMT_TOP_LH11_10" + ], + [ + "CMT_FIFO_SE4BEG3_8", + "CMT_TOP_SE4BEG3_9" + ], + [ + "CMT_FIFO_L_FAN6_2", + "CMT_TOP_FAN6_3" + ], + [ + "CMT_FIFO_WW4END0_9", + "CMT_TOP_WW4END0_10" + ], + [ + "CMT_FIFO_L_IMUX43_10", + "CMT_TOP_IMUX43_11" + ], + [ + "CMT_FIFO_EE4BEG1_9", + "CMT_TOP_EE4BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX18_1", + "CMT_TOP_IMUX18_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_5" + ], + [ + "CMT_FIFO_SE4BEG3_11", + "CMT_TOP_SE4BEG3_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_9", + "CMT_TOP_LOGIC_OUTS_L_B20_10" + ], + [ + "CMT_FIFO_NE2A3_11", + "CMT_TOP_NE2A3_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_8", + "CMT_TOP_LOGIC_OUTS_L_B4_9" + ], + [ + "CMT_FIFO_MONITOR_N_6", + "CMT_TOP_MONITOR_N_7" + ], + [ + "CMT_FIFO_ER1BEG1_1", + "CMT_TOP_ER1BEG1_2" + ], + [ + "CMT_FIFO_L_IMUX13_4", + "CMT_TOP_IMUX13_5" + ], + [ + "CMT_FIFO_SW4END3_10", + "CMT_TOP_SW4END3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_5", + "CMT_TOP_LOGIC_OUTS_L_B1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_8", + "CMT_TOP_LOGIC_OUTS_L_B8_9" + ], + [ + "CMT_FIFO_SE4BEG3_6", + "CMT_TOP_SE4BEG3_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "CMT_TOP_OCLK_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_8", + "CMT_TOP_LOGIC_OUTS_L_B21_9" + ], + [ + "CMT_FIFO_EE4B0_9", + "CMT_TOP_EE4B0_10" + ], + [ + "CMT_FIFO_L_IMUX45_10", + "CMT_TOP_IMUX45_11" + ], + [ + "CMT_FIFO_SW4END3_9", + "CMT_TOP_SW4END3_10" + ], + [ + "CMT_FIFO_L_IMUX35_10", + "CMT_TOP_IMUX35_11" + ], + [ + "CMT_FIFO_SW4A0_7", + "CMT_TOP_SW4A0_8" + ], + [ + "CMT_FIFO_SW2A3_1", + "CMT_TOP_SW2A3_2" + ], + [ + "CMT_FIFO_SE2A0_11", + "CMT_TOP_SE2A0_12" + ], + [ + "CMT_FIFO_EE4BEG2_2", + "CMT_TOP_EE4BEG2_3" + ], + [ + "CMT_FIFO_SW4A1_3", + "CMT_TOP_SW4A1_4" + ], + [ + "CMT_FIFO_WW4C1_5", + "CMT_TOP_WW4C1_6" + ], + [ + "CMT_FIFO_WW2END1_6", + "CMT_TOP_WW2END1_7" + ], + [ + "CMT_FIFO_ER1BEG3_7", + "CMT_TOP_ER1BEG3_8" + ], + [ + "CMT_FIFO_WW4A0_10", + "CMT_TOP_WW4A0_11" + ], + [ + "CMT_FIFO_EE4B2_3", + "CMT_TOP_EE4B2_4" + ], + [ + "CMT_FIFO_L_FAN1_5", + "CMT_TOP_FAN1_6" + ], + [ + "CMT_FIFO_MONITOR_P_4", + "CMT_TOP_MONITOR_P_5" + ], + [ + "CMT_FIFO_NW4A0_3", + "CMT_TOP_NW4A0_4" + ], + [ + "CMT_FIFO_EE4A2_11", + "CMT_TOP_EE4A2_12" + ], + [ + "CMT_FIFO_LH1_11", + "CMT_TOP_LH1_12" + ], + [ + "CMT_FIFO_WR1END1_4", + "CMT_TOP_WR1END1_5" + ], + [ + "CMT_FIFO_SW4A0_6", + "CMT_TOP_SW4A0_7" + ], + [ + "CMT_FIFO_WW2END3_6", + "CMT_TOP_WW2END3_7" + ], + [ + "CMT_FIFO_MONITOR_N_0", + "CMT_TOP_MONITOR_N_1" + ], + [ + "CMT_FIFO_LH4_3", + "CMT_TOP_LH4_4" + ], + [ + "CMT_FIFO_EE2BEG2_1", + "CMT_TOP_EE2BEG2_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "CMT_TOP_ICLK_8" + ], + [ + "CMT_FIFO_NW4END2_5", + "CMT_TOP_NW4END2_6" + ], + [ + "CMT_FIFO_LH7_5", + "CMT_TOP_LH7_6" + ], + [ + "CMT_FIFO_WW2A3_0", + "CMT_TOP_WW2A3_1" + ], + [ + "CMT_FIFO_EE4C1_11", + "CMT_TOP_EE4C1_12" + ], + [ + "CMT_FIFO_L_IMUX30_2", + "CMT_TOP_IMUX30_3" + ], + [ + "CMT_FIFO_L_FAN4_5", + "CMT_TOP_FAN4_6" + ], + [ + "CMT_FIFO_WR1END2_4", + "CMT_TOP_WR1END2_5" + ], + [ + "CMT_FIFO_SE2A3_5", + "CMT_TOP_SE2A3_6" + ], + [ + "CMT_FIFO_L_IMUX26_3", + "CMT_TOP_IMUX26_4" + ], + [ + "CMT_FIFO_L_IMUX34_9", + "CMT_TOP_IMUX34_10" + ], + [ + "CMT_FIFO_EE4A1_9", + "CMT_TOP_EE4A1_10" + ], + [ + "CMT_FIFO_ER1BEG3_11", + "CMT_TOP_ER1BEG3_12" + ], + [ + "CMT_FIFO_WW4C1_7", + "CMT_TOP_WW4C1_8" + ], + [ + "CMT_FIFO_NE4C2_3", + "CMT_TOP_NE4C2_4" + ], + [ + "CMT_FIFO_SW4A1_11", + "CMT_TOP_SW4A1_12" + ], + [ + "CMT_FIFO_EE4BEG1_4", + "CMT_TOP_EE4BEG1_5" + ], + [ + "CMT_FIFO_L_IMUX16_11", + "CMT_TOP_IMUX16_12" + ], + [ + "CMT_FIFO_L_IMUX8_8", + "CMT_TOP_IMUX8_9" + ], + [ + "CMT_FIFO_LH7_9", + "CMT_TOP_LH7_10" + ], + [ + "CMT_FIFO_L_IMUX39_7", + "CMT_TOP_IMUX39_8" + ], + [ + "CMT_FIFO_SE2A1_7", + "CMT_TOP_SE2A1_8" + ], + [ + "CMT_FIFO_LH1_5", + "CMT_TOP_LH1_6" + ], + [ + "CMT_FIFO_L_IMUX43_0", + "CMT_TOP_IMUX43_1" + ], + [ + "CMT_FIFO_EE2BEG3_10", + "CMT_TOP_EE2BEG3_11" + ], + [ + "CMT_FIFO_L_IMUX8_2", + "CMT_TOP_IMUX8_3" + ], + [ + "CMT_FIFO_EE4C0_4", + "CMT_TOP_EE4C0_5" + ], + [ + "CMT_FIFO_L_FAN5_7", + "CMT_TOP_FAN5_8" + ], + [ + "CMT_FIFO_L_IMUX11_6", + "CMT_TOP_IMUX11_7" + ], + [ + "CMT_FIFO_NW4A2_1", + "CMT_TOP_NW4A2_2" + ], + [ + "CMT_FIFO_WW4C2_6", + "CMT_TOP_WW4C2_7" + ], + [ + "CMT_FIFO_L_FAN3_5", + "CMT_TOP_FAN3_6" + ], + [ + "CMT_FIFO_EE4BEG2_10", + "CMT_TOP_EE4BEG2_11" + ], + [ + "CMT_FIFO_L_BYP0_10", + "CMT_TOP_BYP0_11" + ], + [ + "CMT_FIFO_NE4C2_0", + "CMT_TOP_NE4C2_1" + ], + [ + "CMT_FIFO_NW4A3_0", + "CMT_TOP_NW4A3_1" + ], + [ + "CMT_FIFO_EL1BEG0_2", + "CMT_TOP_EL1BEG0_3" + ], + [ + "CMT_FIFO_NE4BEG3_8", + "CMT_TOP_NE4BEG3_9" + ], + [ + "CMT_FIFO_WW4A2_6", + "CMT_TOP_WW4A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_6", + "CMT_TOP_LOGIC_OUTS_L_B7_7" + ], + [ + "CMT_FIFO_EE2A0_1", + "CMT_TOP_EE2A0_2" + ], + [ + "CMT_FIFO_WW4C0_1", + "CMT_TOP_WW4C0_2" + ], + [ + "CMT_FIFO_WW4END2_3", + "CMT_TOP_WW4END2_4" + ], + [ + "CMT_FIFO_WW2A2_8", + "CMT_TOP_WW2A2_9" + ], + [ + "CMT_FIFO_LH2_8", + "CMT_TOP_LH2_9" + ], + [ + "CMT_FIFO_SW4A2_2", + "CMT_TOP_SW4A2_3" + ], + [ + "CMT_FIFO_L_IMUX11_10", + "CMT_TOP_IMUX11_11" + ], + [ + "CMT_FIFO_EE4A2_7", + "CMT_TOP_EE4A2_8" + ], + [ + "CMT_FIFO_WW4B3_3", + "CMT_TOP_WW4B3_4" + ], + [ + "CMT_FIFO_L_IMUX4_3", + "CMT_TOP_IMUX4_4" + ], + [ + "CMT_FIFO_WW2A3_11", + "CMT_TOP_WW2A3_12" + ], + [ + "CMT_FIFO_NW2A0_6", + "CMT_TOP_NW2A0_7" + ], + [ + "CMT_FIFO_WW4B3_2", + "CMT_TOP_WW4B3_3" + ], + [ + "CMT_FIFO_L_IMUX28_5", + "CMT_TOP_IMUX28_6" + ], + [ + "CMT_FIFO_L_IMUX42_8", + "CMT_TOP_IMUX42_9" + ], + [ + "CMT_FIFO_SW4END3_0", + "CMT_TOP_SW4END3_1" + ], + [ + "CMT_FIFO_SW2A1_10", + "CMT_TOP_SW2A1_11" + ], + [ + "CMT_FIFO_EE4A0_6", + "CMT_TOP_EE4A0_7" + ], + [ + "CMT_FIFO_SW4END1_4", + "CMT_TOP_SW4END1_5" + ], + [ + "CMT_FIFO_WW2END0_5", + "CMT_TOP_WW2END0_6" + ], + [ + "CMT_FIFO_WW2END3_11", + "CMT_TOP_WW2END3_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_5", + "CMT_TOP_LOGIC_OUTS_L_B22_6" + ], + [ + "CMT_FIFO_L_IMUX12_5", + "CMT_TOP_IMUX12_6" + ], + [ + "CMT_FIFO_EE4BEG2_4", + "CMT_TOP_EE4BEG2_5" + ], + [ + "CMT_FIFO_EE2BEG0_10", + "CMT_TOP_EE2BEG0_11" + ], + [ + "CMT_FIFO_EE2BEG1_7", + "CMT_TOP_EE2BEG1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_4", + "CMT_TOP_LOGIC_OUTS_L_B17_5" + ], + [ + "CMT_FIFO_NW4END3_9", + "CMT_TOP_NW4END3_10" + ], + [ + "CMT_FIFO_EE4BEG1_2", + "CMT_TOP_EE4BEG1_3" + ], + [ + "CMT_FIFO_LH7_1", + "CMT_TOP_LH7_2" + ], + [ + "CMT_FIFO_EE4A1_8", + "CMT_TOP_EE4A1_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "CMT_TOP_ICLKDIV_12" + ], + [ + "CMT_FIFO_ER1BEG3_0", + "CMT_TOP_ER1BEG3_1" + ], + [ + "CMT_FIFO_L_IMUX37_2", + "CMT_TOP_IMUX37_3" + ], + [ + "CMT_FIFO_L_IMUX24_4", + "CMT_TOP_IMUX24_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_9", + "CMT_TOP_LOGIC_OUTS_L_B22_10" + ], + [ + "CMT_FIFO_L_IMUX24_3", + "CMT_TOP_IMUX24_4" + ], + [ + "CMT_FIFO_EE2BEG0_11", + "CMT_TOP_EE2BEG0_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_2", + "CMT_TOP_LOGIC_OUTS_L_B21_3" + ], + [ + "CMT_FIFO_WW4C3_7", + "CMT_TOP_WW4C3_8" + ], + [ + "CMT_FIFO_NW4A0_6", + "CMT_TOP_NW4A0_7" + ], + [ + "CMT_FIFO_SW4A1_9", + "CMT_TOP_SW4A1_10" + ], + [ + "CMT_FIFO_NE2A0_1", + "CMT_TOP_NE2A0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_1", + "CMT_TOP_LOGIC_OUTS_L_B18_2" + ], + [ + "CMT_FIFO_NE2A1_5", + "CMT_TOP_NE2A1_6" + ], + [ + "CMT_FIFO_L_IMUX3_8", + "CMT_TOP_IMUX3_9" + ], + [ + "CMT_FIFO_SW4END2_5", + "CMT_TOP_SW4END2_6" + ], + [ + "CMT_FIFO_L_FAN4_7", + "CMT_TOP_FAN4_8" + ], + [ + "CMT_FIFO_EL1BEG3_6", + "CMT_TOP_EL1BEG3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_0", + "CMT_TOP_LOGIC_OUTS_L_B4_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_7", + "CMT_TOP_LOGIC_OUTS_L_B9_8" + ], + [ + "CMT_FIFO_NW4A2_3", + "CMT_TOP_NW4A2_4" + ], + [ + "CMT_FIFO_L_IMUX32_6", + "CMT_TOP_IMUX32_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_7", + "CMT_TOP_LOGIC_OUTS_L_B4_8" + ], + [ + "CMT_FIFO_NE4BEG1_5", + "CMT_TOP_NE4BEG1_6" + ], + [ + "CMT_FIFO_SE4C0_1", + "CMT_TOP_SE4C0_2" + ], + [ + "CMT_FIFO_EE4C3_3", + "CMT_TOP_EE4C3_4" + ], + [ + "CMT_FIFO_L_IMUX28_3", + "CMT_TOP_IMUX28_4" + ], + [ + "CMT_FIFO_SE4C2_11", + "CMT_TOP_SE4C2_12" + ], + [ + "CMT_FIFO_NE4BEG2_11", + "CMT_TOP_NE4BEG2_12" + ], + [ + "CMT_FIFO_NE2A2_4", + "CMT_TOP_NE2A2_5" + ], + [ + "CMT_FIFO_NW4END3_0", + "CMT_TOP_NW4END3_1" + ], + [ + "CMT_FIFO_EE2A3_5", + "CMT_TOP_EE2A3_6" + ], + [ + "CMT_FIFO_SW4END3_1", + "CMT_TOP_SW4END3_2" + ], + [ + "CMT_FIFO_L_IMUX4_0", + "CMT_TOP_IMUX4_1" + ], + [ + "CMT_FIFO_SW4END3_4", + "CMT_TOP_SW4END3_5" + ], + [ + "CMT_FIFO_L_IMUX15_5", + "CMT_TOP_IMUX15_6" + ], + [ + "CMT_FIFO_L_IMUX22_10", + "CMT_TOP_IMUX22_11" + ], + [ + "CMT_FIFO_SW2A1_6", + "CMT_TOP_SW2A1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_1", + "CMT_TOP_LOGIC_OUTS_L_B1_2" + ], + [ + "CMT_FIFO_WL1END1_11", + "CMT_TOP_WL1END1_12" + ], + [ + "CMT_FIFO_SW2A2_7", + "CMT_TOP_SW2A2_8" + ], + [ + "CMT_FIFO_NE2A0_10", + "CMT_TOP_NE2A0_11" + ], + [ + "CMT_FIFO_EE2A3_7", + "CMT_TOP_EE2A3_8" + ], + [ + "CMT_FIFO_L_BYP5_3", + "CMT_TOP_BYP5_4" + ], + [ + "CMT_FIFO_L_IMUX25_7", + "CMT_TOP_IMUX25_8" + ], + [ + "CMT_FIFO_L_IMUX35_5", + "CMT_TOP_IMUX35_6" + ], + [ + "CMT_FIFO_L_BYP4_8", + "CMT_TOP_BYP4_9" + ], + [ + "CMT_FIFO_EE4B1_0", + "CMT_TOP_EE4B1_1" + ], + [ + "CMT_FIFO_WW2A3_9", + "CMT_TOP_WW2A3_10" + ], + [ + "CMT_FIFO_L_IMUX2_2", + "CMT_TOP_IMUX2_3" + ], + [ + "CMT_FIFO_L_BYP7_10", + "CMT_TOP_BYP7_11" + ], + [ + "CMT_FIFO_L_IMUX46_7", + "CMT_TOP_IMUX46_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_7", + "CMT_TOP_LOGIC_OUTS_L_B18_8" + ], + [ + "CMT_FIFO_EL1BEG2_7", + "CMT_TOP_EL1BEG2_8" + ], + [ + "CMT_FIFO_EE2A2_0", + "CMT_TOP_EE2A2_1" + ], + [ + "CMT_FIFO_L_IMUX29_3", + "CMT_TOP_IMUX29_4" + ], + [ + "CMT_FIFO_EE2BEG0_5", + "CMT_TOP_EE2BEG0_6" + ], + [ + "CMT_FIFO_L_IMUX22_2", + "CMT_TOP_IMUX22_3" + ], + [ + "CMT_FIFO_L_IMUX15_0", + "CMT_TOP_IMUX15_1" + ], + [ + "CMT_FIFO_WW4B1_4", + "CMT_TOP_WW4B1_5" + ], + [ + "CMT_FIFO_WR1END1_9", + "CMT_TOP_WR1END1_10" + ], + [ + "CMT_FIFO_WW4C0_2", + "CMT_TOP_WW4C0_3" + ], + [ + "CMT_FIFO_NW4A1_10", + "CMT_TOP_NW4A1_11" + ], + [ + "CMT_FIFO_NW4A3_7", + "CMT_TOP_NW4A3_8" + ], + [ + "CMT_FIFO_WR1END0_5", + "CMT_TOP_WR1END0_6" + ], + [ + "CMT_FIFO_EE4A0_0", + "CMT_TOP_EE4A0_1" + ], + [ + "CMT_FIFO_WW4C2_7", + "CMT_TOP_WW4C2_8" + ], + [ + "CMT_FIFO_EE4BEG2_6", + "CMT_TOP_EE4BEG2_7" + ], + [ + "CMT_FIFO_L_IMUX29_5", + "CMT_TOP_IMUX29_6" + ], + [ + "CMT_FIFO_L_IMUX3_3", + "CMT_TOP_IMUX3_4" + ], + [ + "CMT_FIFO_L_IMUX13_2", + "CMT_TOP_IMUX13_3" + ], + [ + "CMT_FIFO_L_IMUX43_8", + "CMT_TOP_IMUX43_9" + ], + [ + "CMT_FIFO_NW4END2_10", + "CMT_TOP_NW4END2_11" + ], + [ + "CMT_FIFO_L_IMUX36_10", + "CMT_TOP_IMUX36_11" + ], + [ + "CMT_FIFO_SW4END0_2", + "CMT_TOP_SW4END0_3" + ], + [ + "CMT_FIFO_L_IMUX27_4", + "CMT_TOP_IMUX27_5" + ], + [ + "CMT_FIFO_WW4B2_10", + "CMT_TOP_WW4B2_11" + ], + [ + "CMT_FIFO_EE2A3_0", + "CMT_TOP_EE2A3_1" + ], + [ + "CMT_FIFO_L_FAN7_9", + "CMT_TOP_FAN7_10" + ], + [ + "CMT_FIFO_ER1BEG1_7", + "CMT_TOP_ER1BEG1_8" + ], + [ + "CMT_FIFO_NW4A3_4", + "CMT_TOP_NW4A3_5" + ], + [ + "CMT_FIFO_L_IMUX12_4", + "CMT_TOP_IMUX12_5" + ], + [ + "CMT_FIFO_ER1BEG1_11", + "CMT_TOP_ER1BEG1_12" + ], + [ + "CMT_FIFO_EE4A2_9", + "CMT_TOP_EE4A2_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_7", + "CMT_TOP_LOGIC_OUTS_L_B12_8" + ], + [ + "CMT_FIFO_EE2BEG2_5", + "CMT_TOP_EE2BEG2_6" + ], + [ + "CMT_FIFO_L_IMUX39_4", + "CMT_TOP_IMUX39_5" + ], + [ + "CMT_FIFO_MONITOR_P_0", + "CMT_TOP_MONITOR_P_1" + ], + [ + "CMT_FIFO_SE2A3_11", + "CMT_TOP_SE2A3_12" + ], + [ + "CMT_FIFO_EE2A3_10", + "CMT_TOP_EE2A3_11" + ], + [ + "CMT_FIFO_L_IMUX32_2", + "CMT_TOP_IMUX32_3" + ], + [ + "CMT_FIFO_L_IMUX9_8", + "CMT_TOP_IMUX9_9" + ], + [ + "CMT_FIFO_SE4C1_10", + "CMT_TOP_SE4C1_11" + ], + [ + "CMT_FIFO_L_CTRL1_5", + "CMT_TOP_CTRL1_6" + ], + [ + "CMT_FIFO_SE4BEG0_3", + "CMT_TOP_SE4BEG0_4" + ], + [ + "CMT_FIFO_WW4END1_8", + "CMT_TOP_WW4END1_9" + ], + [ + "CMT_FIFO_EE4A0_9", + "CMT_TOP_EE4A0_10" + ], + [ + "CMT_FIFO_NW2A2_8", + "CMT_TOP_NW2A2_9" + ], + [ + "CMT_FIFO_L_IMUX19_5", + "CMT_TOP_IMUX19_6" + ], + [ + "CMT_FIFO_EE4A0_11", + "CMT_TOP_EE4A0_12" + ], + [ + "CMT_FIFO_SE2A2_0", + "CMT_TOP_SE2A2_1" + ], + [ + "CMT_FIFO_L_IMUX17_2", + "CMT_TOP_IMUX17_3" + ], + [ + "CMT_FIFO_L_IMUX33_11", + "CMT_TOP_IMUX33_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_1", + "CMT_TOP_LOGIC_OUTS_L_B8_2" + ], + [ + "CMT_FIFO_SW4END3_7", + "CMT_TOP_SW4END3_8" + ], + [ + "CMT_FIFO_WW4END2_7", + "CMT_TOP_WW4END2_8" + ], + [ + "CMT_FIFO_LH2_7", + "CMT_TOP_LH2_8" + ], + [ + "CMT_FIFO_WW4C0_7", + "CMT_TOP_WW4C0_8" + ], + [ + "CMT_FIFO_EL1BEG2_0", + "CMT_TOP_EL1BEG2_1" + ], + [ + "CMT_FIFO_EE2BEG1_0", + "CMT_TOP_EE2BEG1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_1", + "CMT_TOP_LOGIC_OUTS_L_B9_2" + ], + [ + "CMT_FIFO_EE4A1_2", + "CMT_TOP_EE4A1_3" + ], + [ + "CMT_FIFO_NE4BEG0_1", + "CMT_TOP_NE4BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX46_0", + "CMT_TOP_IMUX46_1" + ], + [ + "CMT_FIFO_EE2A1_9", + "CMT_TOP_EE2A1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_2", + "CMT_TOP_LOGIC_OUTS_L_B13_3" + ], + [ + "CMT_FIFO_L_IMUX36_0", + "CMT_TOP_IMUX36_1" + ], + [ + "CMT_FIFO_SW4END0_0", + "CMT_TOP_SW4END0_1" + ], + [ + "CMT_FIFO_NE4C1_3", + "CMT_TOP_NE4C1_4" + ], + [ + "CMT_FIFO_WL1END3_3", + "CMT_TOP_WL1END3_4" + ], + [ + "CMT_FIFO_WW4B1_5", + "CMT_TOP_WW4B1_6" + ], + [ + "CMT_FIFO_L_IMUX38_10", + "CMT_TOP_IMUX38_11" + ], + [ + "CMT_FIFO_L_IMUX27_10", + "CMT_TOP_IMUX27_11" + ], + [ + "CMT_FIFO_L_IMUX40_11", + "CMT_TOP_IMUX40_12" + ], + [ + "CMT_FIFO_L_IMUX36_3", + "CMT_TOP_IMUX36_4" + ], + [ + "CMT_FIFO_SE4C2_7", + "CMT_TOP_SE4C2_8" + ], + [ + "CMT_FIFO_EE4A2_3", + "CMT_TOP_EE4A2_4" + ], + [ + "CMT_FIFO_L_IMUX14_8", + "CMT_TOP_IMUX14_9" + ], + [ + "CMT_FIFO_EE4A3_10", + "CMT_TOP_EE4A3_11" + ], + [ + "CMT_FIFO_WL1END1_0", + "CMT_TOP_WL1END1_1" + ], + [ + "CMT_FIFO_EE4B3_6", + "CMT_TOP_EE4B3_7" + ], + [ + "CMT_FIFO_WW2END2_6", + "CMT_TOP_WW2END2_7" + ], + [ + "CMT_FIFO_EE4B2_0", + "CMT_TOP_EE4B2_1" + ], + [ + "CMT_FIFO_NE4C2_4", + "CMT_TOP_NE4C2_5" + ], + [ + "CMT_FIFO_LH1_9", + "CMT_TOP_LH1_10" + ], + [ + "CMT_FIFO_L_IMUX19_9", + "CMT_TOP_IMUX19_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_5", + "CMT_TOP_LOGIC_OUTS_L_B9_6" + ], + [ + "CMT_FIFO_WW4END1_11", + "CMT_TOP_WW4END1_12" + ], + [ + "CMT_FIFO_L_CLK1_9", + "CMT_TOP_CLK1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_9", + "CMT_TOP_LOGIC_OUTS_L_B13_10" + ], + [ + "CMT_FIFO_EE2A1_2", + "CMT_TOP_EE2A1_3" + ], + [ + "CMT_FIFO_L_IMUX25_10", + "CMT_TOP_IMUX25_11" + ], + [ + "CMT_FIFO_WW2A3_5", + "CMT_TOP_WW2A3_6" + ], + [ + "CMT_FIFO_WW4C0_11", + "CMT_TOP_WW4C0_12" + ], + [ + "CMT_FIFO_L_IMUX40_7", + "CMT_TOP_IMUX40_8" + ], + [ + "CMT_FIFO_L_BYP3_6", + "CMT_TOP_BYP3_7" + ], + [ + "CMT_FIFO_WW4B1_0", + "CMT_TOP_WW4B1_1" + ], + [ + "CMT_FIFO_ER1BEG0_3", + "CMT_TOP_ER1BEG0_4" + ], + [ + "CMT_FIFO_WW4C2_3", + "CMT_TOP_WW4C2_4" + ], + [ + "CMT_FIFO_SW2A0_7", + "CMT_TOP_SW2A0_8" + ], + [ + "CMT_FIFO_L_IMUX12_3", + "CMT_TOP_IMUX12_4" + ], + [ + "CMT_FIFO_EE4B2_4", + "CMT_TOP_EE4B2_5" + ], + [ + "CMT_FIFO_L_IMUX10_4", + "CMT_TOP_IMUX10_5" + ], + [ + "CMT_FIFO_NW4A3_2", + "CMT_TOP_NW4A3_3" + ], + [ + "CMT_FIFO_EE4C2_8", + "CMT_TOP_EE4C2_9" + ], + [ + "CMT_FIFO_NW2A1_1", + "CMT_TOP_NW2A1_2" + ], + [ + "CMT_FIFO_EL1BEG0_9", + "CMT_TOP_EL1BEG0_10" + ], + [ + "CMT_FIFO_WW4END2_8", + "CMT_TOP_WW4END2_9" + ], + [ + "CMT_FIFO_L_FAN3_10", + "CMT_TOP_FAN3_11" + ], + [ + "CMT_FIFO_ER1BEG0_9", + "CMT_TOP_ER1BEG0_10" + ], + [ + "CMT_FIFO_EE2BEG2_9", + "CMT_TOP_EE2BEG2_10" + ], + [ + "CMT_FIFO_NW4END1_7", + "CMT_TOP_NW4END1_8" + ], + [ + "CMT_FIFO_L_IMUX43_4", + "CMT_TOP_IMUX43_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_9", + "CMT_TOP_LOGIC_OUTS_L_B23_10" + ], + [ + "CMT_FIFO_EE4BEG3_3", + "CMT_TOP_EE4BEG3_4" + ], + [ + "CMT_FIFO_NW4END2_3", + "CMT_TOP_NW4END2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_4", + "CMT_TOP_LOGIC_OUTS_L_B18_5" + ], + [ + "CMT_FIFO_SE2A1_4", + "CMT_TOP_SE2A1_5" + ], + [ + "CMT_FIFO_EE4B3_10", + "CMT_TOP_EE4B3_11" + ], + [ + "CMT_FIFO_WL1END3_6", + "CMT_TOP_WL1END3_7" + ], + [ + "CMT_FIFO_NW4A1_3", + "CMT_TOP_NW4A1_4" + ], + [ + "CMT_FIFO_L_IMUX46_6", + "CMT_TOP_IMUX46_7" + ], + [ + "CMT_FIFO_EE4B2_6", + "CMT_TOP_EE4B2_7" + ], + [ + "CMT_FIFO_EE4BEG0_8", + "CMT_TOP_EE4BEG0_9" + ], + [ + "CMT_FIFO_NE2A2_11", + "CMT_TOP_NE2A2_12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "CMT_TOP_ICLKDIV_1" + ], + [ + "CMT_FIFO_EL1BEG3_3", + "CMT_TOP_EL1BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_6", + "CMT_TOP_LOGIC_OUTS_L_B14_7" + ], + [ + "CMT_FIFO_SE2A3_1", + "CMT_TOP_SE2A3_2" + ], + [ + "CMT_FIFO_SW4A0_1", + "CMT_TOP_SW4A0_2" + ], + [ + "CMT_FIFO_L_FAN4_1", + "CMT_TOP_FAN4_2" + ], + [ + "CMT_FIFO_SW2A3_11", + "CMT_TOP_SW2A3_12" + ], + [ + "CMT_FIFO_SE4BEG3_0", + "CMT_TOP_SE4BEG3_1" + ], + [ + "CMT_FIFO_NW2A2_11", + "CMT_TOP_NW2A2_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_11", + "CMT_TOP_LOGIC_OUTS_L_B0_12" + ], + [ + "CMT_FIFO_SW2A3_3", + "CMT_TOP_SW2A3_4" + ], + [ + "CMT_FIFO_WW4C0_10", + "CMT_TOP_WW4C0_11" + ], + [ + "CMT_FIFO_EE4C2_10", + "CMT_TOP_EE4C2_11" + ], + [ + "CMT_FIFO_LH10_2", + "CMT_TOP_LH10_3" + ], + [ + "CMT_FIFO_WR1END2_11", + "CMT_TOP_WR1END2_12" + ], + [ + "CMT_FIFO_L_IMUX0_6", + "CMT_TOP_IMUX0_7" + ], + [ + "CMT_FIFO_L_FAN3_4", + "CMT_TOP_FAN3_5" + ], + [ + "CMT_FIFO_NE4BEG1_0", + "CMT_TOP_NE4BEG1_1" + ], + [ + "CMT_FIFO_L_IMUX43_11", + "CMT_TOP_IMUX43_12" + ], + [ + "CMT_FIFO_EE4C3_8", + "CMT_TOP_EE4C3_9" + ], + [ + "CMT_FIFO_LH7_6", + "CMT_TOP_LH7_7" + ], + [ + "CMT_FIFO_EE2A1_10", + "CMT_TOP_EE2A1_11" + ], + [ + "CMT_FIFO_L_IMUX14_10", + "CMT_TOP_IMUX14_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_5", + "CMT_TOP_LOGIC_OUTS_L_B2_6" + ], + [ + "CMT_FIFO_SE2A0_4", + "CMT_TOP_SE2A0_5" + ], + [ + "CMT_FIFO_L_IMUX19_7", + "CMT_TOP_IMUX19_8" + ], + [ + "CMT_FIFO_NE2A0_9", + "CMT_TOP_NE2A0_10" + ], + [ + "CMT_FIFO_WW4END0_4", + "CMT_TOP_WW4END0_5" + ], + [ + "CMT_FIFO_EE4BEG0_11", + "CMT_TOP_EE4BEG0_12" + ], + [ + "CMT_FIFO_SW2A3_10", + "CMT_TOP_SW2A3_11" + ], + [ + "CMT_FIFO_L_IMUX18_10", + "CMT_TOP_IMUX18_11" + ], + [ + "CMT_FIFO_L_IMUX13_1", + "CMT_TOP_IMUX13_2" + ], + [ + "CMT_FIFO_NE4C1_0", + "CMT_TOP_NE4C1_1" + ], + [ + "CMT_FIFO_L_IMUX1_1", + "CMT_TOP_IMUX1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_7", + "CMT_TOP_LOGIC_OUTS_L_B21_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_3", + "CMT_TOP_LOGIC_OUTS_L_B7_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_6", + "CMT_TOP_LOGIC_OUTS_L_B22_7" + ], + [ + "CMT_FIFO_EE2A3_3", + "CMT_TOP_EE2A3_4" + ], + [ + "CMT_FIFO_L_IMUX16_10", + "CMT_TOP_IMUX16_11" + ], + [ + "CMT_FIFO_SE2A3_2", + "CMT_TOP_SE2A3_3" + ], + [ + "CMT_FIFO_L_IMUX31_3", + "CMT_TOP_IMUX31_4" + ], + [ + "CMT_FIFO_WL1END0_3", + "CMT_TOP_WL1END0_4" + ], + [ + "CMT_FIFO_L_IMUX11_2", + "CMT_TOP_IMUX11_3" + ], + [ + "CMT_FIFO_EE4BEG1_0", + "CMT_TOP_EE4BEG1_1" + ], + [ + "CMT_FIFO_NE4C0_7", + "CMT_TOP_NE4C0_8" + ], + [ + "CMT_FIFO_NW2A0_8", + "CMT_TOP_NW2A0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_5", + "CMT_TOP_LOGIC_OUTS_L_B21_6" + ], + [ + "CMT_FIFO_NE4BEG3_3", + "CMT_TOP_NE4BEG3_4" + ], + [ + "CMT_FIFO_EE2BEG3_11", + "CMT_TOP_EE2BEG3_12" + ], + [ + "CMT_FIFO_L_BYP7_9", + "CMT_TOP_BYP7_10" + ], + [ + "CMT_FIFO_SE4BEG3_1", + "CMT_TOP_SE4BEG3_2" + ], + [ + "CMT_FIFO_NE2A3_7", + "CMT_TOP_NE2A3_8" + ], + [ + "CMT_FIFO_LH4_11", + "CMT_TOP_LH4_12" + ], + [ + "CMT_FIFO_EE4BEG1_1", + "CMT_TOP_EE4BEG1_2" + ], + [ + "CMT_FIFO_WR1END1_10", + "CMT_TOP_WR1END1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_11", + "CMT_TOP_LOGIC_OUTS_L_B8_12" + ], + [ + "CMT_FIFO_WW2END0_1", + "CMT_TOP_WW2END0_2" + ], + [ + "CMT_FIFO_EL1BEG2_10", + "CMT_TOP_EL1BEG2_11" + ], + [ + "CMT_FIFO_L_IMUX24_10", + "CMT_TOP_IMUX24_11" + ], + [ + "CMT_FIFO_EE4C0_10", + "CMT_TOP_EE4C0_11" + ], + [ + "CMT_FIFO_NE2A2_7", + "CMT_TOP_NE2A2_8" + ], + [ + "CMT_FIFO_WW2A1_6", + "CMT_TOP_WW2A1_7" + ], + [ + "CMT_FIFO_NW4A2_5", + "CMT_TOP_NW4A2_6" + ], + [ + "CMT_FIFO_SW2A2_5", + "CMT_TOP_SW2A2_6" + ], + [ + "CMT_FIFO_L_IMUX11_3", + "CMT_TOP_IMUX11_4" + ], + [ + "CMT_FIFO_L_IMUX36_11", + "CMT_TOP_IMUX36_12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "CMT_TOP_OCLK_12" + ], + [ + "CMT_FIFO_LH8_6", + "CMT_TOP_LH8_7" + ], + [ + "CMT_FIFO_WW4END0_0", + "CMT_TOP_WW4END0_1" + ], + [ + "CMT_FIFO_L_FAN1_8", + "CMT_TOP_FAN1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_11", + "CMT_TOP_LOGIC_OUTS_L_B9_12" + ], + [ + "CMT_FIFO_NE2A1_4", + "CMT_TOP_NE2A1_5" + ], + [ + "CMT_FIFO_EE2A2_1", + "CMT_TOP_EE2A2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_10", + "CMT_TOP_LOGIC_OUTS_L_B12_11" + ], + [ + "CMT_FIFO_L_BYP4_7", + "CMT_TOP_BYP4_8" + ], + [ + "CMT_FIFO_L_IMUX8_0", + "CMT_TOP_IMUX8_1" + ], + [ + "CMT_FIFO_L_BYP0_6", + "CMT_TOP_BYP0_7" + ], + [ + "CMT_FIFO_L_IMUX15_8", + "CMT_TOP_IMUX15_9" + ], + [ + "CMT_FIFO_L_IMUX2_7", + "CMT_TOP_IMUX2_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "CMT_TOP_OCLK_10" + ], + [ + "CMT_FIFO_EE2A0_8", + "CMT_TOP_EE2A0_9" + ], + [ + "CMT_FIFO_SW4A1_10", + "CMT_TOP_SW4A1_11" + ], + [ + "CMT_FIFO_LH3_2", + "CMT_TOP_LH3_3" + ], + [ + "CMT_FIFO_NW2A3_6", + "CMT_TOP_NW2A3_7" + ], + [ + "CMT_FIFO_WR1END0_8", + "CMT_TOP_WR1END0_9" + ], + [ + "CMT_FIFO_LH10_10", + "CMT_TOP_LH10_11" + ], + [ + "CMT_FIFO_NE4C3_5", + "CMT_TOP_NE4C3_6" + ], + [ + "CMT_FIFO_L_BYP5_11", + "CMT_TOP_BYP5_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_6", + "CMT_TOP_LOGIC_OUTS_L_B1_7" + ], + [ + "CMT_FIFO_NE4BEG2_2", + "CMT_TOP_NE4BEG2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_6", + "CMT_TOP_LOGIC_OUTS_L_B12_7" + ], + [ + "CMT_FIFO_L_IMUX21_10", + "CMT_TOP_IMUX21_11" + ], + [ + "CMT_FIFO_WL1END1_10", + "CMT_TOP_WL1END1_11" + ], + [ + "CMT_FIFO_L_IMUX2_9", + "CMT_TOP_IMUX2_10" + ], + [ + "CMT_FIFO_L_FAN4_2", + "CMT_TOP_FAN4_3" + ], + [ + "CMT_FIFO_L_IMUX43_5", + "CMT_TOP_IMUX43_6" + ], + [ + "CMT_FIFO_WW4END1_1", + "CMT_TOP_WW4END1_2" + ], + [ + "CMT_FIFO_L_FAN0_4", + "CMT_TOP_FAN0_5" + ], + [ + "CMT_FIFO_L_IMUX13_6", + "CMT_TOP_IMUX13_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "CMT_TOP_ICLK_11" + ], + [ + "CMT_FIFO_SE4BEG1_8", + "CMT_TOP_SE4BEG1_9" + ], + [ + "CMT_FIFO_EE2BEG0_6", + "CMT_TOP_EE2BEG0_7" + ], + [ + "CMT_FIFO_SE4BEG3_3", + "CMT_TOP_SE4BEG3_4" + ], + [ + "CMT_FIFO_WL1END0_2", + "CMT_TOP_WL1END0_3" + ], + [ + "CMT_FIFO_L_IMUX9_2", + "CMT_TOP_IMUX9_3" + ], + [ + "CMT_FIFO_SW2A2_3", + "CMT_TOP_SW2A2_4" + ], + [ + "CMT_FIFO_EE4C2_11", + "CMT_TOP_EE4C2_12" + ], + [ + "CMT_FIFO_ER1BEG1_6", + "CMT_TOP_ER1BEG1_7" + ], + [ + "CMT_FIFO_SW4END3_5", + "CMT_TOP_SW4END3_6" + ], + [ + "CMT_FIFO_L_IMUX9_3", + "CMT_TOP_IMUX9_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_9", + "CMT_TOP_LOGIC_OUTS_L_B2_10" + ], + [ + "CMT_FIFO_WW4END0_2", + "CMT_TOP_WW4END0_3" + ], + [ + "CMT_FIFO_L_PHASER_WRCLK", + "CMT_MMCM_A_WRCLK_TOFIFO" + ], + [ + "CMT_FIFO_WW4C2_10", + "CMT_TOP_WW4C2_11" + ], + [ + "CMT_FIFO_L_IMUX5_7", + "CMT_TOP_IMUX5_8" + ], + [ + "CMT_FIFO_L_FAN5_8", + "CMT_TOP_FAN5_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_8", + "CMT_TOP_LOGIC_OUTS_L_B12_9" + ], + [ + "CMT_FIFO_L_FAN1_3", + "CMT_TOP_FAN1_4" + ], + [ + "CMT_FIFO_L_IMUX30_6", + "CMT_TOP_IMUX30_7" + ], + [ + "CMT_FIFO_EE4A3_8", + "CMT_TOP_EE4A3_9" + ], + [ + "CMT_FIFO_L_IMUX41_5", + "CMT_TOP_IMUX41_6" + ], + [ + "CMT_FIFO_SE4BEG2_6", + "CMT_TOP_SE4BEG2_7" + ], + [ + "CMT_FIFO_L_FAN5_6", + "CMT_TOP_FAN5_7" + ], + [ + "CMT_FIFO_NW4END0_5", + "CMT_TOP_NW4END0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_2", + "CMT_TOP_LOGIC_OUTS_L_B19_3" + ], + [ + "CMT_FIFO_WW2END2_3", + "CMT_TOP_WW2END2_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "CMT_TOP_OCLK_7" + ], + [ + "CMT_FIFO_L_IMUX34_2", + "CMT_TOP_IMUX34_3" + ], + [ + "CMT_FIFO_EE4C0_1", + "CMT_TOP_EE4C0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_6", + "CMT_TOP_LOGIC_OUTS_L_B5_7" + ], + [ + "CMT_FIFO_LH5_2", + "CMT_TOP_LH5_3" + ], + [ + "CMT_FIFO_SW2A1_11", + "CMT_TOP_SW2A1_12" + ], + [ + "CMT_FIFO_L_IMUX16_1", + "CMT_TOP_IMUX16_2" + ], + [ + "CMT_FIFO_NW4A1_8", + "CMT_TOP_NW4A1_9" + ], + [ + "CMT_FIFO_SE2A0_3", + "CMT_TOP_SE2A0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_8", + "CMT_TOP_LOGIC_OUTS_L_B22_9" + ], + [ + "CMT_FIFO_L_IMUX39_1", + "CMT_TOP_IMUX39_2" + ], + [ + "CMT_FIFO_L_IMUX12_8", + "CMT_TOP_IMUX12_9" + ], + [ + "CMT_FIFO_EE2A3_4", + "CMT_TOP_EE2A3_5" + ], + [ + "CMT_FIFO_EE4A3_11", + "CMT_TOP_EE4A3_12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "CMT_TOP_OCLK_5" + ], + [ + "CMT_FIFO_WW2A2_1", + "CMT_TOP_WW2A2_2" + ], + [ + "CMT_FIFO_L_IMUX32_7", + "CMT_TOP_IMUX32_8" + ], + [ + "CMT_FIFO_LH4_6", + "CMT_TOP_LH4_7" + ], + [ + "CMT_FIFO_L_IMUX1_2", + "CMT_TOP_IMUX1_3" + ], + [ + "CMT_FIFO_SW2A0_11", + "CMT_TOP_SW2A0_12" + ], + [ + "CMT_FIFO_L_IMUX24_1", + "CMT_TOP_IMUX24_2" + ], + [ + "CMT_FIFO_L_IMUX21_9", + "CMT_TOP_IMUX21_10" + ], + [ + "CMT_FIFO_EL1BEG0_3", + "CMT_TOP_EL1BEG0_4" + ], + [ + "CMT_FIFO_WR1END0_11", + "CMT_TOP_WR1END0_12" + ], + [ + "CMT_FIFO_LH8_4", + "CMT_TOP_LH8_5" + ], + [ + "CMT_FIFO_L_CTRL0_0", + "CMT_TOP_CTRL0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "CMT_TOP_OCLK1X_90_8" + ], + [ + "CMT_FIFO_EE2BEG1_4", + "CMT_TOP_EE2BEG1_5" + ], + [ + "CMT_FIFO_L_IMUX21_3", + "CMT_TOP_IMUX21_4" + ], + [ + "CMT_FIFO_L_IMUX34_10", + "CMT_TOP_IMUX34_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_3" + ], + [ + "CMT_FIFO_L_IMUX19_1", + "CMT_TOP_IMUX19_2" + ], + [ + "CMT_FIFO_WW4A1_2", + "CMT_TOP_WW4A1_3" + ], + [ + "CMT_FIFO_SE4BEG1_5", + "CMT_TOP_SE4BEG1_6" + ], + [ + "CMT_FIFO_L_IMUX39_9", + "CMT_TOP_IMUX39_10" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "CMT_TOP_L_LOWER_B" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "BRAM_CASCOUT_ADDRARDADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13" + ], + [ + "BRAM_FIFO36_CASCADEINB", + "BRKH_BRAM_CASCADEB_R" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" + ], + [ + "BRAM_FIFO36_CASCADEINA", + "BRKH_BRAM_CASCADEA_R" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9" + ] + ], + "tile_types": [ + "BRAM_R", + "BRKH_BRAM" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "BRAM_SW4END2_4", + "CLBLM_SW4END2" + ], + [ + "BRAM_SE4BEG0_4", + "CLBLM_SE4BEG0" + ], + [ + "BRAM_SW4A2_4", + "CLBLM_SW4A2" + ], + [ + "BRAM_NW2A0_4", + "CLBLM_NW2A0" + ], + [ + "BRAM_NW2A3_4", + "CLBLM_NW2A3" + ], + [ + "BRAM_WW4END3_4", + "CLBLM_WW4END3" + ], + [ + "BRAM_NW4END1_4", + "CLBLM_NW4END1" + ], + [ + "BRAM_NE2A0_4", + "CLBLM_NE2A0" + ], + [ + "BRAM_LH10_4", + "CLBLM_LH10" + ], + [ + "BRAM_LH11_4", + "CLBLM_LH11" + ], + [ + "BRAM_WR1END3_4", + "CLBLM_WR1END3" + ], + [ + "BRAM_WW4B0_4", + "CLBLM_WW4B0" + ], + [ + "BRAM_SW4END3_4", + "CLBLM_SW4END3" + ], + [ + "BRAM_EE4B1_4", + "CLBLM_EE4B1" + ], + [ + "BRAM_WL1END1_4", + "CLBLM_WL1END1" + ], + [ + "BRAM_WL1END2_4", + "CLBLM_WL1END2" + ], + [ + "BRAM_WW2END2_4", + "CLBLM_WW2END2" + ], + [ + "BRAM_WW4C3_4", + "CLBLM_WW4C3" + ], + [ + "BRAM_SE4C0_4", + "CLBLM_SE4C0" + ], + [ + "BRAM_LH3_4", + "CLBLM_LH3" + ], + [ + "BRAM_WW4C0_4", + "CLBLM_WW4C0" + ], + [ + "BRAM_EE2BEG1_4", + "CLBLM_EE2BEG1" + ], + [ + "BRAM_WW4B3_4", + "CLBLM_WW4B3" + ], + [ + "BRAM_EE4BEG1_4", + "CLBLM_EE4BEG1" + ], + [ + "BRAM_SW2A0_4", + "CLBLM_SW2A0" + ], + [ + "BRAM_NW4A0_4", + "CLBLM_NW4A0" + ], + [ + "BRAM_EL1BEG1_4", + "CLBLM_EL1BEG1" + ], + [ + "BRAM_WW4A0_4", + "CLBLM_WW4A0" + ], + [ + "BRAM_EE4B3_4", + "CLBLM_EE4B3" + ], + [ + "BRAM_EE4BEG2_4", + "CLBLM_EE4BEG2" + ], + [ + "BRAM_WW2END3_4", + "CLBLM_WW2END3" + ], + [ + "BRAM_NE4C2_4", + "CLBLM_NE4C2" + ], + [ + "BRAM_SE4BEG3_4", + "CLBLM_SE4BEG3" + ], + [ + "BRAM_EL1BEG2_4", + "CLBLM_EL1BEG2" + ], + [ + "BRAM_EE4BEG3_4", + "CLBLM_EE4BEG3" + ], + [ + "BRAM_NW4END2_4", + "CLBLM_NW4END2" + ], + [ + "BRAM_LH1_4", + "CLBLM_LH1" + ], + [ + "BRAM_WW4C1_4", + "CLBLM_WW4C1" + ], + [ + "BRAM_SW2A1_4", + "CLBLM_SW2A1" + ], + [ + "BRAM_EE2A3_4", + "CLBLM_EE2A3" + ], + [ + "BRAM_ER1BEG3_4", + "CLBLM_ER1BEG3" + ], + [ + "BRAM_LH12_4", + "CLBLM_LH12" + ], + [ + "BRAM_SW4END1_4", + "CLBLM_SW4END1" + ], + [ + "BRAM_SE2A1_4", + "CLBLM_SE2A1" + ], + [ + "BRAM_WW4B2_4", + "CLBLM_WW4B2" + ], + [ + "BRAM_EE2BEG3_4", + "CLBLM_EE2BEG3" + ], + [ + "BRAM_SW4A3_4", + "CLBLM_SW4A3" + ], + [ + "BRAM_NE4BEG1_4", + "CLBLM_NE4BEG1" + ], + [ + "BRAM_NE4BEG2_4", + "CLBLM_NE4BEG2" + ], + [ + "BRAM_EE2A2_4", + "CLBLM_EE2A2" + ], + [ + "BRAM_WL1END3_4", + "CLBLM_WL1END3" + ], + [ + "BRAM_NW4A2_4", + "CLBLM_NW4A2" + ], + [ + "BRAM_NW2A1_4", + "CLBLM_NW2A1" + ], + [ + "BRAM_NE2A1_4", + "CLBLM_NE2A1" + ], + [ + "BRAM_WW2A1_4", + "CLBLM_WW2A1" + ], + [ + "BRAM_SE2A2_4", + "CLBLM_SE2A2" + ], + [ + "BRAM_EE4B2_4", + "CLBLM_EE4B2" + ], + [ + "BRAM_WW4C2_4", + "CLBLM_WW4C2" + ], + [ + "BRAM_LH9_4", + "CLBLM_LH9" + ], + [ + "BRAM_EE2A1_4", + "CLBLM_EE2A1" + ], + [ + "BRAM_EE4A3_4", + "CLBLM_EE4A3" + ], + [ + "BRAM_NE2A3_4", + "CLBLM_NE2A3" + ], + [ + "BRAM_WW4END2_4", + "CLBLM_WW4END2" + ], + [ + "BRAM_LH6_4", + "CLBLM_LH6" + ], + [ + "BRAM_NE4BEG3_4", + "CLBLM_NE4BEG3" + ], + [ + "BRAM_WW2A3_4", + "CLBLM_WW2A3" + ], + [ + "BRAM_LH7_4", + "CLBLM_LH7" + ], + [ + "BRAM_SE4BEG2_4", + "CLBLM_SE4BEG2" + ], + [ + "BRAM_SE4BEG1_4", + "CLBLM_SE4BEG1" + ], + [ + "BRAM_EE4A1_4", + "CLBLM_EE4A1" + ], + [ + "BRAM_NE4C1_4", + "CLBLM_NE4C1" + ], + [ + "BRAM_MONITOR_N_4", + "CLBLM_MONITOR_N" + ], + [ + "BRAM_WW2END1_4", + "CLBLM_WW2END1" + ], + [ + "BRAM_MONITOR_P_4", + "CLBLM_MONITOR_P" + ], + [ + "BRAM_NW4A3_4", + "CLBLM_NW4A3" + ], + [ + "BRAM_EL1BEG0_4", + "CLBLM_EL1BEG0" + ], + [ + "BRAM_EE2BEG2_4", + "CLBLM_EE2BEG2" + ], + [ + "BRAM_SE2A3_4", + "CLBLM_SE2A3" + ], + [ + "BRAM_SE4C3_4", + "CLBLM_SE4C3" + ], + [ + "BRAM_SW4END0_4", + "CLBLM_SW4END0" + ], + [ + "BRAM_SE4C2_4", + "CLBLM_SE4C2" + ], + [ + "BRAM_ER1BEG2_4", + "CLBLM_ER1BEG2" + ], + [ + "BRAM_SE2A0_4", + "CLBLM_SE2A0" + ], + [ + "BRAM_EE4C1_4", + "CLBLM_EE4C1" + ], + [ + "BRAM_EE4A2_4", + "CLBLM_EE4A2" + ], + [ + "BRAM_NW4END0_4", + "CLBLM_NW4END0" + ], + [ + "BRAM_NW4A1_4", + "CLBLM_NW4A1" + ], + [ + "BRAM_WW4END0_4", + "CLBLM_WW4END0" + ], + [ + "BRAM_ER1BEG1_4", + "CLBLM_ER1BEG1" + ], + [ + "BRAM_WR1END1_4", + "CLBLM_WR1END1" + ], + [ + "BRAM_EE2BEG0_4", + "CLBLM_EE2BEG0" + ], + [ + "BRAM_LH5_4", + "CLBLM_LH5" + ], + [ + "BRAM_WW4A3_4", + "CLBLM_WW4A3" + ], + [ + "BRAM_EE4C2_4", + "CLBLM_EE4C2" + ], + [ + "BRAM_NW2A2_4", + "CLBLM_NW2A2" + ], + [ + "BRAM_EE4C0_4", + "CLBLM_EE4C0" + ], + [ + "BRAM_NW4END3_4", + "CLBLM_NW4END3" + ], + [ + "BRAM_SW2A2_4", + "CLBLM_SW2A2" + ], + [ + "BRAM_WW2A2_4", + "CLBLM_WW2A2" + ], + [ + "BRAM_SW4A0_4", + "CLBLM_SW4A0" + ], + [ + "BRAM_WW4B1_4", + "CLBLM_WW4B1" + ], + [ + "BRAM_WW4END1_4", + "CLBLM_WW4END1" + ], + [ + "BRAM_NE4C3_4", + "CLBLM_NE4C3" + ], + [ + "BRAM_WR1END2_4", + "CLBLM_WR1END2" + ], + [ + "BRAM_LH2_4", + "CLBLM_LH2" + ], + [ + "BRAM_ER1BEG0_4", + "CLBLM_ER1BEG0" + ], + [ + "BRAM_SW4A1_4", + "CLBLM_SW4A1" + ], + [ + "BRAM_NE4BEG0_4", + "CLBLM_NE4BEG0" + ], + [ + "BRAM_EE4BEG0_4", + "CLBLM_EE4BEG0" + ], + [ + "BRAM_SW2A3_4", + "CLBLM_SW2A3" + ], + [ + "BRAM_WW2END0_4", + "CLBLM_WW2END0" + ], + [ + "BRAM_WL1END0_4", + "CLBLM_WL1END0" + ], + [ + "BRAM_LH8_4", + "CLBLM_LH8" + ], + [ + "BRAM_WW2A0_4", + "CLBLM_WW2A0" + ], + [ + "BRAM_WR1END0_4", + "CLBLM_WR1END0" + ], + [ + "BRAM_EL1BEG3_4", + "CLBLM_EL1BEG3" + ], + [ + "BRAM_EE2A0_4", + "CLBLM_EE2A0" + ], + [ + "BRAM_NE2A2_4", + "CLBLM_NE2A2" + ], + [ + "BRAM_NE4C0_4", + "CLBLM_NE4C0" + ], + [ + "BRAM_SE4C1_4", + "CLBLM_SE4C1" + ], + [ + "BRAM_EE4A0_4", + "CLBLM_EE4A0" + ], + [ + "BRAM_EE4B0_4", + "CLBLM_EE4B0" + ], + [ + "BRAM_WW4A2_4", + "CLBLM_WW4A2" + ], + [ + "BRAM_LH4_4", + "CLBLM_LH4" + ], + [ + "BRAM_EE4C3_4", + "CLBLM_EE4C3" + ], + [ + "BRAM_WW4A1_4", + "CLBLM_WW4A1" + ] + ], + "tile_types": [ + "BRAM_L", + "CLBLM_R" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE2A2_14", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_ER1BEG2_14", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_LH9_14", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_ER1BEG1_14", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_WW2END0_14", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WW4END1_14", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX41_14", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX18_14", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_FAN4_14", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_LH8_14", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_EE4A2_14", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_FAN0_14", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_LH3_14", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_EE4BEG2_14", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_WW2END1_14", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_IMUX26_14", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_NW4A1_14", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SW2A2_14", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_IMUX5_14", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX0_14", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_LH10_14", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_NW4A3_14", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SW4A1_14", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_LH1_14", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_EE2A3_14", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EL1BEG3_14", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_IMUX46_14", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW2END3_14", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW4C2_14", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WW4END2_14", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX42_14", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_WW2END2_14", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_EE2A0_14", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WW4C1_14", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_NW4END2_14", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_LH4_14", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_IMUX29_14", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_NE2A0_14", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX34_14", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_IMUX20_14", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SE2A3_14", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SE4BEG1_14", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_IMUX23_14", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NE4C2_14", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_SW4END2_14", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_NE4C0_14", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_NE4BEG0_14", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_NW4A2_14", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_WW4A0_14", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX43_14", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_EE2BEG2_14", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_EL1BEG2_14", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_WW4END0_14", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_SW4END0_14", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_ER1BEG0_14", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_WW2A2_14", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_NW4END1_14", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_WR1END3_14", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX25_14", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_BYP7_14", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_NW4A0_14", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_BYP2_14", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_IMUX8_14", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_CLK1_14", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX30_14", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_WW4A1_14", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_WW4A3_14", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WL1END2_14", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WR1END2_14", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_WW4C0_14", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_SW4END3_14", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_EE2BEG0_14", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_EE4B3_14", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_LH6_14", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX2_14", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_EE4A3_14", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX19_14", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_WL1END3_14", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_EE4C1_14", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_BYP6_14", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX36_14", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW2A0_14", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_NE4C3_14", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_EE2A1_14", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX7_14", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_IMUX38_14", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_EE2BEG3_14", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_SW4A0_14", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_WW4B1_14", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_WW2A3_14", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX10_14", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_NE2A1_14", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_SE4C1_14", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_LH2_14", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_NE2A3_14", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX16_14", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX33_14", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_SE2A0_14", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_FAN3_14", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_WW4A2_14", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_EE4C3_14", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_WW4B3_14", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_LH12_14", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX31_14", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_ER1BEG3_14", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_EE4B2_14", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_EL1BEG1_14", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_EE4A0_14", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_IMUX11_14", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_SE4BEG3_14", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_EE4BEG0_14", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_IMUX13_14", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_IMUX39_14", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_SE4C3_14", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX37_14", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_FAN2_14", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_FAN1_14", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_WW4B2_14", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_NW2A3_14", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_SE4C2_14", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_SW2A1_14", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_SE4C0_14", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_IMUX12_14", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX4_14", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX44_14", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WR1END1_14", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_EE4B0_14", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_EE2BEG1_14", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_SE4BEG0_14", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_CTRL1_14", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_NE4BEG1_14", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX15_14", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_SW4A3_14", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EE4BEG1_14", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_FAN5_14", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SE2A1_14", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NE4BEG3_14", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX32_14", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_WW4C3_14", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_BYP4_14", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WR1END0_14", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_IMUX28_14", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX22_14", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_LH5_14", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_FAN7_14", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_LH11_14", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_IMUX35_14", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_IMUX9_14", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_NW2A0_14", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_IMUX47_14", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_SE2A2_14", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_WW4B0_14", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_WW2A0_14", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_SW2A3_14", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_IMUX14_14", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_NW4END0_14", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_BYP3_14", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_NW4END3_14", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_IMUX40_14", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_IMUX6_14", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX21_14", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_WW4END3_14", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_BYP0_14", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_EL1BEG0_14", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_CLK0_14", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_SW4A2_14", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_EE4C0_14", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_IMUX45_14", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_NE4C1_14", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_WL1END0_14", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_SW4END1_14", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_IMUX27_14", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX3_14", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_EE4BEG3_14", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX24_14", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_WL1END1_14", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_NE2A2_14", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE4A1_14", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_SE4BEG2_14", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE4C2_14", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX17_14", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_NE4BEG2_14", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_CTRL0_14", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_BYP5_14", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_FAN6_14", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_EE4B1_14", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_NW2A2_14", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW2A1_14", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_LH7_14", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_IMUX1_14", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_BYP1_14", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_NW2A1_14", + "VFRAME_NW2A1" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "BRKH_CLB_COUT0_L", + "CLBLL_LL_COUT_N" + ], + [ + "BRKH_CLB_COUT1_L", + "CLBLL_L_COUT_N" + ] + ], + "tile_types": [ + "BRKH_CLB", + "CLBLL_L" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "IOI_IMUX11_0", + "TERM_INT_IMUX11" + ], + [ + "IOI_IMUX43_0", + "TERM_INT_IMUX43" + ], + [ + "IOI_FAN1_0", + "TERM_INT_FAN1" + ], + [ + "IOI_CTRL1_0", + "TERM_INT_CTRL1" + ], + [ + "IOI_LOGIC_OUTS18_0", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_BYP2_0", + "TERM_INT_BYP2" + ], + [ + "IOI_LOGIC_OUTS2_0", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_IMUX6_0", + "TERM_INT_IMUX6" + ], + [ + "IOI_IMUX36_0", + "TERM_INT_IMUX36" + ], + [ + "IOI_IMUX34_0", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX46_0", + "TERM_INT_IMUX46" + ], + [ + "IOI_IMUX0_0", + "TERM_INT_IMUX0" + ], + [ + "IOI_IMUX20_0", + "TERM_INT_IMUX20" + ], + [ + "IOI_LOGIC_OUTS23_0", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_LOGIC_OUTS15_0", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX19_0", + "TERM_INT_IMUX19" + ], + [ + "IOI_IMUX47_0", + "TERM_INT_IMUX47" + ], + [ + "IOI_LOGIC_OUTS17_0", + "TERM_INT_LOGIC_OUTS_L_B17" + ], + [ + "IOI_IMUX25_0", + "TERM_INT_IMUX25" + ], + [ + "IOI_LOGIC_OUTS7_0", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_FAN2_0", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX45_0", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX31_0", + "TERM_INT_IMUX31" + ], + [ + "IOI_LOGIC_OUTS19_0", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_IMUX1_0", + "TERM_INT_IMUX1" + ], + [ + "IOI_MONITOR_N", + "TERM_INT_MONITOR_N" + ], + [ + "IOI_IMUX22_0", + "TERM_INT_IMUX22" + ], + [ + "IOI_IMUX12_0", + "TERM_INT_IMUX12" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_BLOCK_OUTS2_0", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "IOI_IMUX40_0", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX10_0", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX16_0", + "TERM_INT_IMUX16" + ], + [ + "IOI_FAN0_0", + "TERM_INT_FAN0" + ], + [ + "IOI_IMUX38_0", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX26_0", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX3_0", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX24_0", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX37_0", + "TERM_INT_IMUX37" + ], + [ + "IOI_LOGIC_OUTS3_0", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_FAN4_0", + "TERM_INT_FAN4" + ], + [ + "RIOI_I2GCLK_TOP0", + "L_TERM_INT_DQS_IOTOPHASER" + ], + [ + "IOI_FAN6_0", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX7_0", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX39_0", + "TERM_INT_IMUX39" + ], + [ + "IOI_CTRL0_0", + "TERM_INT_CTRL0" + ], + [ + "IOI_CLK0_0", + "TERM_INT_CLK0" + ], + [ + "IOI_CLK1_0", + "TERM_INT_CLK1" + ], + [ + "IOI_FAN7_0", + "TERM_INT_FAN7" + ], + [ + "IOI_BYP0_0", + "TERM_INT_BYP0" + ], + [ + "IOI_LOGIC_OUTS0_0", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_LOGIC_OUTS21_0", + "TERM_INT_LOGIC_OUTS_L_B21" + ], + [ + "IOI_LOGIC_OUTS6_0", + "TERM_INT_LOGIC_OUTS_L_B6" + ], + [ + "IOI_IMUX8_0", + "TERM_INT_IMUX8" + ], + [ + "IOI_LOGIC_OUTS11_0", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_BYP6_0", + "TERM_INT_BYP6" + ], + [ + "IOI_IMUX42_0", + "TERM_INT_IMUX42" + ], + [ + "IOI_IMUX30_0", + "TERM_INT_IMUX30" + ], + [ + "IOI_LOGIC_OUTS1_0", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX5_0", + "TERM_INT_IMUX5" + ], + [ + "IOI_IMUX4_0", + "TERM_INT_IMUX4" + ], + [ + "IOI_IMUX17_0", + "TERM_INT_IMUX17" + ], + [ + "IOI_IMUX23_0", + "TERM_INT_IMUX23" + ], + [ + "IOI_IMUX33_0", + "TERM_INT_IMUX33" + ], + [ + "IOI_PHASER_TO_IO_ICLK", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_FAN5_0", + "TERM_INT_FAN5" + ], + [ + "IOI_BYP1_0", + "TERM_INT_BYP1" + ], + [ + "IOI_LOGIC_OUTS9_0", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_LOGIC_OUTS14_0", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_IMUX13_0", + "TERM_INT_IMUX13" + ], + [ + "IOI_IMUX44_0", + "TERM_INT_IMUX44" + ], + [ + "IOI_LOGIC_OUTS20_0", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_LOGIC_OUTS5_0", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_IMUX27_0", + "TERM_INT_IMUX27" + ], + [ + "IOI_IMUX18_0", + "TERM_INT_IMUX18" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_IMUX9_0", + "TERM_INT_IMUX9" + ], + [ + "IOI_BLOCK_OUTS1_0", + "TERM_INT_BLOCK_OUTS_L_B1" + ], + [ + "IOI_FAN3_0", + "TERM_INT_FAN3" + ], + [ + "IOI_BYP5_0", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS8_0", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_PHASER_TO_IO_OCLK", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_LOGIC_OUTS4_0", + "TERM_INT_LOGIC_OUTS_L_B4" + ], + [ + "IOI_BYP4_0", + "TERM_INT_BYP4" + ], + [ + "IOI_BYP7_0", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_0", + "TERM_INT_IMUX2" + ], + [ + "IOI_IMUX35_0", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP3_0", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX15_0", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX29_0", + "TERM_INT_IMUX29" + ], + [ + "IOI_LOGIC_OUTS10_0", + "TERM_INT_LOGIC_OUTS_L_B10" + ], + [ + "IOI_LOGIC_OUTS12_0", + "TERM_INT_LOGIC_OUTS_L_B12" + ], + [ + "IOI_IMUX14_0", + "TERM_INT_IMUX14" + ], + [ + "IOI_MONITOR_P", + "TERM_INT_MONITOR_P" + ], + [ + "IOI_IMUX21_0", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX28_0", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX41_0", + "TERM_INT_IMUX41" + ], + [ + "IOI_BLOCK_OUTS0_0", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_IMUX32_0", + "TERM_INT_IMUX32" + ] + ], + "tile_types": [ + "RIOI_TBYTESRC", + "R_TERM_INT" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "CMT_TOP_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_LH2_1", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH11_1", + "VBRK_LH11" + ], + [ + "CMT_TOP_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH10_1", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_LH8_1", + "VBRK_LH8" + ], + [ + "CMT_TOP_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH3_1", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH4_1", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH5_1", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_1", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_LH6_1", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH1_1", + "VBRK_LH1" + ], + [ + "CMT_TOP_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_LH7_1", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_LH9_1", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2BEG2_1", + "VBRK_EE2BEG2" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "DSP_LH2_1", + "VBRK_LH2" + ], + [ + "DSP_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "DSP_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "DSP_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "DSP_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "DSP_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "DSP_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "DSP_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "DSP_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "DSP_LH9_1", + "VBRK_LH9" + ], + [ + "DSP_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "DSP_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "DSP_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "DSP_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "DSP_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "DSP_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "DSP_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "DSP_LH3_1", + "VBRK_LH3" + ], + [ + "DSP_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "DSP_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "DSP_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "DSP_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "DSP_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "DSP_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "DSP_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "DSP_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "DSP_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "DSP_LH8_1", + "VBRK_LH8" + ], + [ + "DSP_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "DSP_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "DSP_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "DSP_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "DSP_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "DSP_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "DSP_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "DSP_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "DSP_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "DSP_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "DSP_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "DSP_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "DSP_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "DSP_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "DSP_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "DSP_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "DSP_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "DSP_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "DSP_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "DSP_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "DSP_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "DSP_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "DSP_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "DSP_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "DSP_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "DSP_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "DSP_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "DSP_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "DSP_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "DSP_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "DSP_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "DSP_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "DSP_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "DSP_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "DSP_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "DSP_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "DSP_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "DSP_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "DSP_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "DSP_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "DSP_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "DSP_LH12_1", + "VBRK_LH12" + ], + [ + "DSP_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "DSP_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "DSP_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "DSP_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "DSP_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "DSP_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "DSP_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "DSP_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "DSP_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "DSP_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "DSP_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "DSP_MONITOR_N_1", + "VBRK_MONITOR_N" + ], + [ + "DSP_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "DSP_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "DSP_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "DSP_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "DSP_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "DSP_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "DSP_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "DSP_LH11_1", + "VBRK_LH11" + ], + [ + "DSP_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "DSP_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "DSP_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "DSP_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "DSP_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "DSP_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "DSP_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "DSP_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "DSP_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "DSP_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "DSP_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "DSP_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "DSP_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "DSP_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "DSP_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "DSP_LH7_1", + "VBRK_LH7" + ], + [ + "DSP_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "DSP_LH6_1", + "VBRK_LH6" + ], + [ + "DSP_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "DSP_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "DSP_LH4_1", + "VBRK_LH4" + ], + [ + "DSP_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "DSP_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "DSP_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "DSP_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "DSP_MONITOR_P_1", + "VBRK_MONITOR_P" + ], + [ + "DSP_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "DSP_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "DSP_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "DSP_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "DSP_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "DSP_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "DSP_LH5_1", + "VBRK_LH5" + ], + [ + "DSP_LH10_1", + "VBRK_LH10" + ], + [ + "DSP_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "DSP_LH1_1", + "VBRK_LH1" + ] + ], + "tile_types": [ + "DSP_L", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -9 + ], + "wire_pairs": [ + [ + "MONITOR_WW2END3_9", + "VFRAME_WW2END3" + ], + [ + "MONITOR_NE4C1_9", + "VFRAME_NE4C1" + ], + [ + "MONITOR_SW2A3_9", + "VFRAME_SW2A3" + ], + [ + "MONITOR_NE4BEG3_9", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_LH10_9", + "VFRAME_LH10" + ], + [ + "MONITOR_IMUX2_9", + "VFRAME_IMUX2" + ], + [ + "MONITOR_WW4C3_9", + "VFRAME_WW4C3" + ], + [ + "MONITOR_IMUX30_9", + "VFRAME_IMUX30" + ], + [ + "MONITOR_SW4A0_9", + "VFRAME_SW4A0" + ], + [ + "MONITOR_IMUX27_9", + "VFRAME_IMUX27" + ], + [ + "MONITOR_NW2A3_9", + "VFRAME_NW2A3" + ], + [ + "MONITOR_SW4END2_9", + "VFRAME_SW4END2" + ], + [ + "MONITOR_WL1END0_9", + "VFRAME_WL1END0" + ], + [ + "MONITOR_IMUX41_9", + "VFRAME_IMUX41" + ], + [ + "MONITOR_SE4BEG3_9", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_FAN4_9", + "VFRAME_FAN4" + ], + [ + "MONITOR_FAN0_9", + "VFRAME_FAN0" + ], + [ + "MONITOR_LH4_9", + "VFRAME_LH4" + ], + [ + "MONITOR_IMUX21_9", + "VFRAME_IMUX21" + ], + [ + "MONITOR_IMUX6_9", + "VFRAME_IMUX6" + ], + [ + "MONITOR_ER1BEG3_9", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_IMUX5_9", + "VFRAME_IMUX5" + ], + [ + "MONITOR_SW2A2_9", + "VFRAME_SW2A2" + ], + [ + "MONITOR_BYP3_9", + "VFRAME_BYP3" + ], + [ + "MONITOR_LH9_9", + "VFRAME_LH9" + ], + [ + "MONITOR_SE4C0_9", + "VFRAME_SE4C0" + ], + [ + "MONITOR_IMUX25_9", + "VFRAME_IMUX25" + ], + [ + "MONITOR_IMUX20_9", + "VFRAME_IMUX20" + ], + [ + "MONITOR_EE2BEG1_9", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_NE4BEG2_9", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_IMUX44_9", + "VFRAME_IMUX44" + ], + [ + "MONITOR_NW4END2_9", + "VFRAME_NW4END2" + ], + [ + "MONITOR_ER1BEG2_9", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_LH12_9", + "VFRAME_LH12" + ], + [ + "MONITOR_IMUX14_9", + "VFRAME_IMUX14" + ], + [ + "MONITOR_IMUX35_9", + "VFRAME_IMUX35" + ], + [ + "MONITOR_BYP1_9", + "VFRAME_BYP1" + ], + [ + "MONITOR_WW2A3_9", + "VFRAME_WW2A3" + ], + [ + "MONITOR_NW2A1_9", + "VFRAME_NW2A1" + ], + [ + "MONITOR_SE4C1_9", + "VFRAME_SE4C1" + ], + [ + "MONITOR_EE4A2_9", + "VFRAME_EE4A2" + ], + [ + "MONITOR_IMUX38_9", + "VFRAME_IMUX38" + ], + [ + "MONITOR_EE2BEG0_9", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_IMUX46_9", + "VFRAME_IMUX46" + ], + [ + "MONITOR_EE4C2_9", + "VFRAME_EE4C2" + ], + [ + "MONITOR_LH3_9", + "VFRAME_LH3" + ], + [ + "MONITOR_CLK1_9", + "VFRAME_CLK1" + ], + [ + "MONITOR_SW2A0_9", + "VFRAME_SW2A0" + ], + [ + "MONITOR_IMUX32_9", + "VFRAME_IMUX32" + ], + [ + "MONITOR_NW4A0_9", + "VFRAME_NW4A0" + ], + [ + "MONITOR_IMUX26_9", + "VFRAME_IMUX26" + ], + [ + "MONITOR_NE4C0_9", + "VFRAME_NE4C0" + ], + [ + "MONITOR_IMUX10_9", + "VFRAME_IMUX10" + ], + [ + "MONITOR_WW2END0_9", + "VFRAME_WW2END0" + ], + [ + "MONITOR_WW4B3_9", + "VFRAME_WW4B3" + ], + [ + "MONITOR_EE2A2_9", + "VFRAME_EE2A2" + ], + [ + "MONITOR_IMUX37_9", + "VFRAME_IMUX37" + ], + [ + "MONITOR_IMUX24_9", + "VFRAME_IMUX24" + ], + [ + "MONITOR_IMUX23_9", + "VFRAME_IMUX23" + ], + [ + "MONITOR_IMUX22_9", + "VFRAME_IMUX22" + ], + [ + "MONITOR_IMUX11_9", + "VFRAME_IMUX11" + ], + [ + "MONITOR_NW4END1_9", + "VFRAME_NW4END1" + ], + [ + "MONITOR_WR1END2_9", + "VFRAME_WR1END2" + ], + [ + "MONITOR_WW4A1_9", + "VFRAME_WW4A1" + ], + [ + "MONITOR_WW4B2_9", + "VFRAME_WW4B2" + ], + [ + "MONITOR_EE4B2_9", + "VFRAME_EE4B2" + ], + [ + "MONITOR_LH11_9", + "VFRAME_LH11" + ], + [ + "MONITOR_IMUX40_9", + "VFRAME_IMUX40" + ], + [ + "MONITOR_WL1END1_9", + "VFRAME_WL1END1" + ], + [ + "MONITOR_IMUX39_9", + "VFRAME_IMUX39" + ], + [ + "MONITOR_LH2_9", + "VFRAME_LH2" + ], + [ + "MONITOR_BYP2_9", + "VFRAME_BYP2" + ], + [ + "MONITOR_NE2A2_9", + "VFRAME_NE2A2" + ], + [ + "MONITOR_SE2A3_9", + "VFRAME_SE2A3" + ], + [ + "MONITOR_SE4BEG1_9", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_IMUX19_9", + "VFRAME_IMUX19" + ], + [ + "MONITOR_IMUX3_9", + "VFRAME_IMUX3" + ], + [ + "MONITOR_EE2BEG2_9", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_SE2A1_9", + "VFRAME_SE2A1" + ], + [ + "MONITOR_BYP5_9", + "VFRAME_BYP5" + ], + [ + "MONITOR_IMUX43_9", + "VFRAME_IMUX43" + ], + [ + "MONITOR_IMUX31_9", + "VFRAME_IMUX31" + ], + [ + "MONITOR_FAN2_9", + "VFRAME_FAN2" + ], + [ + "MONITOR_SW4END1_9", + "VFRAME_SW4END1" + ], + [ + "MONITOR_SW4A3_9", + "VFRAME_SW4A3" + ], + [ + "MONITOR_EE4B1_9", + "VFRAME_EE4B1" + ], + [ + "MONITOR_CTRL0_9", + "VFRAME_CTRL0" + ], + [ + "MONITOR_IMUX9_9", + "VFRAME_IMUX9" + ], + [ + "MONITOR_IMUX42_9", + "VFRAME_IMUX42" + ], + [ + "MONITOR_BYP7_9", + "VFRAME_BYP7" + ], + [ + "MONITOR_IMUX13_9", + "VFRAME_IMUX13" + ], + [ + "MONITOR_NE4C3_9", + "VFRAME_NE4C3" + ], + [ + "MONITOR_EL1BEG3_9", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_NW4A3_9", + "VFRAME_NW4A3" + ], + [ + "MONITOR_WW2A2_9", + "VFRAME_WW2A2" + ], + [ + "MONITOR_SE4C2_9", + "VFRAME_SE4C2" + ], + [ + "MONITOR_SE4BEG0_9", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_SW4END0_9", + "VFRAME_SW4END0" + ], + [ + "MONITOR_EE2BEG3_9", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_LH1_9", + "VFRAME_LH1" + ], + [ + "MONITOR_WW4C0_9", + "VFRAME_WW4C0" + ], + [ + "MONITOR_NW2A0_9", + "VFRAME_NW2A0" + ], + [ + "MONITOR_IMUX1_9", + "VFRAME_IMUX1" + ], + [ + "MONITOR_IMUX28_9", + "VFRAME_IMUX28" + ], + [ + "MONITOR_EE4A0_9", + "VFRAME_EE4A0" + ], + [ + "MONITOR_NE2A3_9", + "VFRAME_NE2A3" + ], + [ + "MONITOR_SE2A0_9", + "VFRAME_SE2A0" + ], + [ + "MONITOR_NW4END3_9", + "VFRAME_NW4END3" + ], + [ + "MONITOR_SW4END3_9", + "VFRAME_SW4END3" + ], + [ + "MONITOR_EE4BEG1_9", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_NE4C2_9", + "VFRAME_NE4C2" + ], + [ + "MONITOR_NE2A0_9", + "VFRAME_NE2A0" + ], + [ + "MONITOR_EE4B0_9", + "VFRAME_EE4B0" + ], + [ + "MONITOR_EE2A3_9", + "VFRAME_EE2A3" + ], + [ + "MONITOR_NE2A1_9", + "VFRAME_NE2A1" + ], + [ + "MONITOR_LH8_9", + "VFRAME_LH8" + ], + [ + "MONITOR_ER1BEG1_9", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_LH7_9", + "VFRAME_LH7" + ], + [ + "MONITOR_IMUX0_9", + "VFRAME_IMUX0" + ], + [ + "MONITOR_NW4A1_9", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WW4A2_9", + "VFRAME_WW4A2" + ], + [ + "MONITOR_EE4BEG2_9", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_ER1BEG0_9", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_EE4BEG3_9", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_WW4END2_9", + "VFRAME_WW4END2" + ], + [ + "MONITOR_NW2A2_9", + "VFRAME_NW2A2" + ], + [ + "MONITOR_BYP4_9", + "VFRAME_BYP4" + ], + [ + "MONITOR_LH6_9", + "VFRAME_LH6" + ], + [ + "MONITOR_SW2A1_9", + "VFRAME_SW2A1" + ], + [ + "MONITOR_IMUX29_9", + "VFRAME_IMUX29" + ], + [ + "MONITOR_EE4B3_9", + "VFRAME_EE4B3" + ], + [ + "MONITOR_IMUX7_9", + "VFRAME_IMUX7" + ], + [ + "MONITOR_WW2A0_9", + "VFRAME_WW2A0" + ], + [ + "MONITOR_IMUX4_9", + "VFRAME_IMUX4" + ], + [ + "MONITOR_EE4C3_9", + "VFRAME_EE4C3" + ], + [ + "MONITOR_WW4END1_9", + "VFRAME_WW4END1" + ], + [ + "MONITOR_WR1END0_9", + "VFRAME_WR1END0" + ], + [ + "MONITOR_EE4A3_9", + "VFRAME_EE4A3" + ], + [ + "MONITOR_WW4END0_9", + "VFRAME_WW4END0" + ], + [ + "MONITOR_SE2A2_9", + "VFRAME_SE2A2" + ], + [ + "MONITOR_WW4C2_9", + "VFRAME_WW4C2" + ], + [ + "MONITOR_NW4A2_9", + "VFRAME_NW4A2" + ], + [ + "MONITOR_FAN3_9", + "VFRAME_FAN3" + ], + [ + "MONITOR_SE4BEG2_9", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_FAN5_9", + "VFRAME_FAN5" + ], + [ + "MONITOR_NW4END0_9", + "VFRAME_NW4END0" + ], + [ + "MONITOR_WR1END1_9", + "VFRAME_WR1END1" + ], + [ + "MONITOR_IMUX34_9", + "VFRAME_IMUX34" + ], + [ + "MONITOR_LH5_9", + "VFRAME_LH5" + ], + [ + "MONITOR_WW4A0_9", + "VFRAME_WW4A0" + ], + [ + "MONITOR_FAN1_9", + "VFRAME_FAN1" + ], + [ + "MONITOR_SE4C3_9", + "VFRAME_SE4C3" + ], + [ + "MONITOR_IMUX47_9", + "VFRAME_IMUX47" + ], + [ + "MONITOR_IMUX36_9", + "VFRAME_IMUX36" + ], + [ + "MONITOR_WW2A1_9", + "VFRAME_WW2A1" + ], + [ + "MONITOR_NE4BEG0_9", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_IMUX45_9", + "VFRAME_IMUX45" + ], + [ + "MONITOR_WR1END3_9", + "VFRAME_WR1END3" + ], + [ + "MONITOR_SW4A1_9", + "VFRAME_SW4A1" + ], + [ + "MONITOR_IMUX16_9", + "VFRAME_IMUX16" + ], + [ + "MONITOR_EE4A1_9", + "VFRAME_EE4A1" + ], + [ + "MONITOR_IMUX12_9", + "VFRAME_IMUX12" + ], + [ + "MONITOR_NE4BEG1_9", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_WW4B1_9", + "VFRAME_WW4B1" + ], + [ + "MONITOR_EE2A1_9", + "VFRAME_EE2A1" + ], + [ + "MONITOR_EL1BEG2_9", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_IMUX15_9", + "VFRAME_IMUX15" + ], + [ + "MONITOR_IMUX17_9", + "VFRAME_IMUX17" + ], + [ + "MONITOR_WW4A3_9", + "VFRAME_WW4A3" + ], + [ + "MONITOR_WW4C1_9", + "VFRAME_WW4C1" + ], + [ + "MONITOR_EL1BEG0_9", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_IMUX33_9", + "VFRAME_IMUX33" + ], + [ + "MONITOR_WW4END3_9", + "VFRAME_WW4END3" + ], + [ + "MONITOR_BYP0_9", + "VFRAME_BYP0" + ], + [ + "MONITOR_FAN6_9", + "VFRAME_FAN6" + ], + [ + "MONITOR_EE4BEG0_9", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_CTRL1_9", + "VFRAME_CTRL1" + ], + [ + "MONITOR_IMUX18_9", + "VFRAME_IMUX18" + ], + [ + "MONITOR_WL1END3_9", + "VFRAME_WL1END3" + ], + [ + "MONITOR_WW4B0_9", + "VFRAME_WW4B0" + ], + [ + "MONITOR_EE2A0_9", + "VFRAME_EE2A0" + ], + [ + "MONITOR_WL1END2_9", + "VFRAME_WL1END2" + ], + [ + "MONITOR_WW2END2_9", + "VFRAME_WW2END2" + ], + [ + "MONITOR_BYP6_9", + "VFRAME_BYP6" + ], + [ + "MONITOR_CLK0_9", + "VFRAME_CLK0" + ], + [ + "MONITOR_SW4A2_9", + "VFRAME_SW4A2" + ], + [ + "MONITOR_EE4C1_9", + "VFRAME_EE4C1" + ], + [ + "MONITOR_EE4C0_9", + "VFRAME_EE4C0" + ], + [ + "MONITOR_IMUX8_9", + "VFRAME_IMUX8" + ], + [ + "MONITOR_FAN7_9", + "VFRAME_FAN7" + ], + [ + "MONITOR_EL1BEG1_9", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_WW2END1_9", + "VFRAME_WW2END1" + ] + ], + "tile_types": [ + "MONITOR_BOT_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLBLL_LH3", + "CLBLL_LH3" + ], + [ + "CLBLL_WW4A2", + "CLBLL_WW4A2" + ], + [ + "CLBLL_WL1END0", + "CLBLL_WL1END0" + ], + [ + "CLBLL_SW4END2", + "CLBLL_SW4END2" + ], + [ + "CLBLL_WW4B2", + "CLBLL_WW4B2" + ], + [ + "CLBLL_WW4B0", + "CLBLL_WW4B0" + ], + [ + "CLBLL_EE2A0", + "CLBLL_EE2A0" + ], + [ + "CLBLL_WW4A0", + "CLBLL_WW4A0" + ], + [ + "CLBLL_WR1END3", + "CLBLL_WR1END3" + ], + [ + "CLBLL_WW2END1", + "CLBLL_WW2END1" + ], + [ + "CLBLL_EE4C3", + "CLBLL_EE4C3" + ], + [ + "CLBLL_NE4BEG1", + "CLBLL_NE4BEG1" + ], + [ + "CLBLL_NE4C0", + "CLBLL_NE4C0" + ], + [ + "CLBLL_SE4BEG0", + "CLBLL_SE4BEG0" + ], + [ + "CLBLL_NW2A1", + "CLBLL_NW2A1" + ], + [ + "CLBLL_SE4C1", + "CLBLL_SE4C1" + ], + [ + "CLBLL_EE4A0", + "CLBLL_EE4A0" + ], + [ + "CLBLL_EL1BEG0", + "CLBLL_EL1BEG0" + ], + [ + "CLBLL_SW2A1", + "CLBLL_SW2A1" + ], + [ + "CLBLL_WW4B3", + "CLBLL_WW4B3" + ], + [ + "CLBLL_EL1BEG2", + "CLBLL_EL1BEG2" + ], + [ + "CLBLL_SW4A3", + "CLBLL_SW4A3" + ], + [ + "CLBLL_WR1END1", + "CLBLL_WR1END1" + ], + [ + "CLBLL_WW4C2", + "CLBLL_WW4C2" + ], + [ + "CLBLL_EE4B2", + "CLBLL_EE4B2" + ], + [ + "CLBLL_LH10", + "CLBLL_LH10" + ], + [ + "CLBLL_LH1", + "CLBLL_LH1" + ], + [ + "CLBLL_EE4B0", + "CLBLL_EE4B0" + ], + [ + "CLBLL_EE2BEG2", + "CLBLL_EE2BEG2" + ], + [ + "CLBLL_SW4END1", + "CLBLL_SW4END1" + ], + [ + "CLBLL_NE2A3", + "CLBLL_NE2A3" + ], + [ + "CLBLL_NE4C1", + "CLBLL_NE4C1" + ], + [ + "CLBLL_NE4C3", + "CLBLL_NE4C3" + ], + [ + "CLBLL_NW4END0", + "CLBLL_NW4END0" + ], + [ + "CLBLL_NW4END2", + "CLBLL_NW4END2" + ], + [ + "CLBLL_EE2BEG1", + "CLBLL_EE2BEG1" + ], + [ + "CLBLL_LH7", + "CLBLL_LH7" + ], + [ + "CLBLL_EE2A3", + "CLBLL_EE2A3" + ], + [ + "CLBLL_LH5", + "CLBLL_LH5" + ], + [ + "CLBLL_NE2A0", + "CLBLL_NE2A0" + ], + [ + "CLBLL_LH9", + "CLBLL_LH9" + ], + [ + "CLBLL_EE4B3", + "CLBLL_EE4B3" + ], + [ + "CLBLL_SE4C2", + "CLBLL_SE4C2" + ], + [ + "CLBLL_WW4B1", + "CLBLL_WW4B1" + ], + [ + "CLBLL_WW2END0", + "CLBLL_WW2END0" + ], + [ + "CLBLL_WW2A3", + "CLBLL_WW2A3" + ], + [ + "CLBLL_SE4BEG1", + "CLBLL_SE4BEG1" + ], + [ + "CLBLL_EE4BEG1", + "CLBLL_EE4BEG1" + ], + [ + "CLBLL_EE4BEG3", + "CLBLL_EE4BEG3" + ], + [ + "CLBLL_LH12", + "CLBLL_LH12" + ], + [ + "CLBLL_NW4A2", + "CLBLL_NW4A2" + ], + [ + "CLBLL_NE4BEG2", + "CLBLL_NE4BEG2" + ], + [ + "CLBLL_EE4BEG2", + "CLBLL_EE4BEG2" + ], + [ + "CLBLL_WL1END1", + "CLBLL_WL1END1" + ], + [ + "CLBLL_WL1END2", + "CLBLL_WL1END2" + ], + [ + "CLBLL_LH11", + "CLBLL_LH11" + ], + [ + "CLBLL_WW4C3", + "CLBLL_WW4C3" + ], + [ + "CLBLL_WL1END3", + "CLBLL_WL1END3" + ], + [ + "CLBLL_NW2A3", + "CLBLL_NW2A3" + ], + [ + "CLBLL_NW4A0", + "CLBLL_NW4A0" + ], + [ + "CLBLL_SE4BEG3", + "CLBLL_SE4BEG3" + ], + [ + "CLBLL_SE2A1", + "CLBLL_SE2A1" + ], + [ + "CLBLL_SW4A0", + "CLBLL_SW4A0" + ], + [ + "CLBLL_EE4B1", + "CLBLL_EE4B1" + ], + [ + "CLBLL_SE2A3", + "CLBLL_SE2A3" + ], + [ + "CLBLL_ER1BEG2", + "CLBLL_ER1BEG2" + ], + [ + "CLBLL_NE2A1", + "CLBLL_NE2A1" + ], + [ + "CLBLL_NW4END1", + "CLBLL_NW4END1" + ], + [ + "CLBLL_LH8", + "CLBLL_LH8" + ], + [ + "CLBLL_NW2A2", + "CLBLL_NW2A2" + ], + [ + "CLBLL_SE2A0", + "CLBLL_SE2A0" + ], + [ + "CLBLL_NW4END3", + "CLBLL_NW4END3" + ], + [ + "CLBLL_EE4A1", + "CLBLL_EE4A1" + ], + [ + "CLBLL_SE4BEG2", + "CLBLL_SE4BEG2" + ], + [ + "CLBLL_WW2A2", + "CLBLL_WW2A2" + ], + [ + "CLBLL_WW2END3", + "CLBLL_WW2END3" + ], + [ + "CLBLL_LH4", + "CLBLL_LH4" + ], + [ + "CLBLL_EE2A1", + "CLBLL_EE2A1" + ], + [ + "CLBLL_EE2BEG0", + "CLBLL_EE2BEG0" + ], + [ + "CLBLL_LH2", + "CLBLL_LH2" + ], + [ + "CLBLL_EL1BEG3", + "CLBLL_EL1BEG3" + ], + [ + "CLBLL_WW4END1", + "CLBLL_WW4END1" + ], + [ + "CLBLL_NE4BEG0", + "CLBLL_NE4BEG0" + ], + [ + "CLBLL_EE4C0", + "CLBLL_EE4C0" + ], + [ + "CLBLL_EE2A2", + "CLBLL_EE2A2" + ], + [ + "CLBLL_WW2END2", + "CLBLL_WW2END2" + ], + [ + "CLBLL_SE4C3", + "CLBLL_SE4C3" + ], + [ + "CLBLL_WW2A0", + "CLBLL_WW2A0" + ], + [ + "CLBLL_NW2A0", + "CLBLL_NW2A0" + ], + [ + "CLBLL_NW4A1", + "CLBLL_NW4A1" + ], + [ + "CLBLL_SW4END0", + "CLBLL_SW4END0" + ], + [ + "CLBLL_WW4C1", + "CLBLL_WW4C1" + ], + [ + "CLBLL_SW2A2", + "CLBLL_SW2A2" + ], + [ + "CLBLL_SW4A1", + "CLBLL_SW4A1" + ], + [ + "CLBLL_EL1BEG1", + "CLBLL_EL1BEG1" + ], + [ + "CLBLL_NE2A2", + "CLBLL_NE2A2" + ], + [ + "CLBLL_MONITOR_P", + "CLBLL_MONITOR_P" + ], + [ + "CLBLL_EE4A2", + "CLBLL_EE4A2" + ], + [ + "CLBLL_SW2A3", + "CLBLL_SW2A3" + ], + [ + "CLBLL_EE4BEG0", + "CLBLL_EE4BEG0" + ], + [ + "CLBLL_EE4C2", + "CLBLL_EE4C2" + ], + [ + "CLBLL_EE4A3", + "CLBLL_EE4A3" + ], + [ + "CLBLL_ER1BEG1", + "CLBLL_ER1BEG1" + ], + [ + "CLBLL_NW4A3", + "CLBLL_NW4A3" + ], + [ + "CLBLL_ER1BEG0", + "CLBLL_ER1BEG0" + ], + [ + "CLBLL_WR1END0", + "CLBLL_WR1END0" + ], + [ + "CLBLL_LH6", + "CLBLL_LH6" + ], + [ + "CLBLL_SE2A2", + "CLBLL_SE2A2" + ], + [ + "CLBLL_WW4A3", + "CLBLL_WW4A3" + ], + [ + "CLBLL_SW2A0", + "CLBLL_SW2A0" + ], + [ + "CLBLL_WW4END3", + "CLBLL_WW4END3" + ], + [ + "CLBLL_NE4C2", + "CLBLL_NE4C2" + ], + [ + "CLBLL_EE4C1", + "CLBLL_EE4C1" + ], + [ + "CLBLL_SW4END3", + "CLBLL_SW4END3" + ], + [ + "CLBLL_SE4C0", + "CLBLL_SE4C0" + ], + [ + "CLBLL_WW4C0", + "CLBLL_WW4C0" + ], + [ + "CLBLL_WW4END2", + "CLBLL_WW4END2" + ], + [ + "CLBLL_MONITOR_N", + "CLBLL_MONITOR_N" + ], + [ + "CLBLL_WW2A1", + "CLBLL_WW2A1" + ], + [ + "CLBLL_WW4A1", + "CLBLL_WW4A1" + ], + [ + "CLBLL_WR1END2", + "CLBLL_WR1END2" + ], + [ + "CLBLL_WW4END0", + "CLBLL_WW4END0" + ], + [ + "CLBLL_EE2BEG3", + "CLBLL_EE2BEG3" + ], + [ + "CLBLL_NE4BEG3", + "CLBLL_NE4BEG3" + ], + [ + "CLBLL_SW4A2", + "CLBLL_SW4A2" + ], + [ + "CLBLL_ER1BEG3", + "CLBLL_ER1BEG3" + ] + ], + "tile_types": [ + "CLBLL_L", + "CLBLL_R" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "CLK_PMV_NW4END0_3", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_PMV_EE4B3_3", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_PMV_NE2A3_3", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_PMV_WW4A0_3", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_PMV_NE4C2_3", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_PMV_IMUX41_3", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_PMV_BYP1_3", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_PMV_WW4C3_3", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_PMV_IMUX26_3", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_PMV_IMUX37_3", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_PMV_WL1END3_3", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_PMV_WW2A2_3", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_PMV_IMUX42_3", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_PMV_BYP0_3", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_PMV_EE4A3_3", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_PMV_WW4C0_3", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_PMV_NE4BEG0_3", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_PMV_WW4END2_3", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_PMV_WW2A0_3", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_PMV_IMUX0_3", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_PMV_WW2A1_3", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_PMV_WW4END3_3", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_PMV_IMUX44_3", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_PMV_LH12_3", + "INT_INTERFACE_LH12" + ], + [ + "CLK_PMV_EE4C3_3", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_PMV_WW4B2_3", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_PMV_BYP2_3", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_PMV_IMUX27_3", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_PMV_FAN1_3", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_PMV_SE4BEG2_3", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_PMV_LH11_3", + "INT_INTERFACE_LH11" + ], + [ + "CLK_PMV_LH1_3", + "INT_INTERFACE_LH1" + ], + [ + "CLK_PMV_IMUX40_3", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_PMV_NW4END2_3", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_PMV_IMUX33_3", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_PMV_LH7_3", + "INT_INTERFACE_LH7" + ], + [ + "CLK_PMV_IMUX10_3", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_PMV_IMUX20_3", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_PMV_LH4_3", + "INT_INTERFACE_LH4" + ], + [ + "CLK_PMV_IMUX14_3", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_PMV_EE4B0_3", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_PMV_WW2END3_3", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_PMV_NW2A2_3", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_PMV_IMUX11_3", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_PMV_SW4END3_3", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_PMV_NE4BEG2_3", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_PMV_IMUX28_3", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_PMV_WL1END1_3", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_PMV_IMUX3_3", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_PMV_FAN3_3", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_PMV_SE4BEG1_3", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_PMV_SW4END2_3", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_PMV_SE4C1_3", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_PMV_SE2A1_3", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_PMV_IMUX34_3", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_PMV_IMUX45_3", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_PMV_ER1BEG0_3", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_PMV_IMUX24_3", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_PMV_CLK0_3", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_PMV_IMUX30_3", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_PMV_EE4A1_3", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_PMV_FAN0_3", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_PMV_IMUX36_3", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_PMV_LOGIC_OUTS1_3", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CLK_PMV_ER1BEG1_3", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_PMV_IMUX38_3", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_PMV_NE2A0_3", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_PMV_LH10_3", + "INT_INTERFACE_LH10" + ], + [ + "CLK_PMV_SE2A3_3", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_PMV_IMUX7_3", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_PMV_FAN4_3", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_PMV_WW2END0_3", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_PMV_FAN5_3", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_PMV_EL1BEG1_3", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_PMV_CTRL1_3", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_PMV_EE4C1_3", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_PMV_WW4A3_3", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_PMV_IMUX5_3", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_PMV_IMUX32_3", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_PMV_EL1BEG0_3", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_PMV_BYP7_3", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_PMV_IMUX21_3", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_PMV_WW4C1_3", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_PMV_NW4A3_3", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_PMV_IMUX9_3", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_PMV_SW2A1_3", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_PMV_EE4B2_3", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_PMV_SW4A3_3", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_PMV_WW4B0_3", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_PMV_WW4B1_3", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_PMV_SW4A0_3", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_PMV_WR1END2_3", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_PMV_NE4C0_3", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_PMV_NE2A1_3", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_PMV_IMUX23_3", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_PMV_LH5_3", + "INT_INTERFACE_LH5" + ], + [ + "CLK_PMV_NE4BEG1_3", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_PMV_IMUX13_3", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_PMV_NW2A0_3", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_PMV_EE2BEG2_3", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_PMV_NW4END1_3", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_PMV_FAN2_3", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_PMV_SW2A0_3", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_PMV_EE4A2_3", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_PMV_EE4BEG0_3", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_PMV_IMUX15_3", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_PMV_SE4C2_3", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_PMV_EE2A0_3", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_PMV_IMUX1_3", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_PMV_WR1END1_3", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_PMV_IMUX17_3", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_PMV_NW4A0_3", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_PMV_NW4END3_3", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_PMV_SE4BEG3_3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_PMV_WL1END2_3", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_PMV_IMUX35_3", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_PMV_LH8_3", + "INT_INTERFACE_LH8" + ], + [ + "CLK_PMV_LH6_3", + "INT_INTERFACE_LH6" + ], + [ + "CLK_PMV_EE4B1_3", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_PMV_BYP3_3", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_PMV_EE4BEG1_3", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_PMV_SW4END0_3", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_PMV_BYP4_3", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_PMV_WW4A1_3", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_PMV_WR1END0_3", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_PMV_WW4END1_3", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_PMV_IMUX6_3", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_PMV_LOGIC_OUTS13_3", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "CLK_PMV_CTRL0_3", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_PMV_ER1BEG3_3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_PMV_WR1END3_3", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_PMV_NE4C1_3", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_PMV_WW4B3_3", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_PMV_SE4C3_3", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_PMV_WL1END0_3", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_PMV_EL1BEG2_3", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_PMV_IMUX19_3", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_PMV_IMUX12_3", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_PMV_EE2A1_3", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_PMV_WW2END2_3", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_PMV_EE4C0_3", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_PMV_WW4END0_3", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_PMV_WW4A2_3", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_PMV_IMUX29_3", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_PMV_FAN7_3", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_PMV_SE2A2_3", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_PMV_IMUX43_3", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_PMV_LOGIC_OUTS9_3", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CLK_PMV_LH3_3", + "INT_INTERFACE_LH3" + ], + [ + "CLK_PMV_WW2END1_3", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_PMV_SW4END1_3", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_PMV_IMUX25_3", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_PMV_EE2A3_3", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_PMV_EE4BEG3_3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_PMV_NE4BEG3_3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_PMV_IMUX39_3", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_PMV_LH9_3", + "INT_INTERFACE_LH9" + ], + [ + "CLK_PMV_NE4C3_3", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_PMV_SE2A0_3", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_PMV_IMUX4_3", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_PMV_SW2A3_3", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_PMV_EE4A0_3", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_PMV_WW4C2_3", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_PMV_NW2A1_3", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_PMV_IMUX8_3", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_PMV_FAN6_3", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_PMV_EE2BEG1_3", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_PMV_EE2A2_3", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_PMV_IMUX46_3", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_PMV_IMUX18_3", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_PMV_NW4A2_3", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_PMV_IMUX31_3", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_PMV_CLK1_3", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_PMV_IMUX2_3", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_PMV_BYP5_3", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_PMV_LH2_3", + "INT_INTERFACE_LH2" + ], + [ + "CLK_PMV_NW2A3_3", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_PMV_SW2A2_3", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_PMV_EE4BEG2_3", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_PMV_SW4A1_3", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_PMV_WW2A3_3", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_PMV_IMUX22_3", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_PMV_SE4C0_3", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_PMV_EE4C2_3", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_PMV_EE2BEG3_3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_PMV_EL1BEG3_3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_PMV_SW4A2_3", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_PMV_NE2A2_3", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_PMV_ER1BEG2_3", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_PMV_EE2BEG0_3", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_PMV_NW4A1_3", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_PMV_SE4BEG0_3", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_PMV_BYP6_3", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_PMV_IMUX47_3", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_PMV_IMUX16_3", + "INT_INTERFACE_IMUX16" + ] + ], + "tile_types": [ + "CLK_PMV", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLK_HROW_CK_IN_L12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "CLK_HROW_CK_BUFRCLK_L2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "CLK_HROW_CK_IN_L2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "CLK_HROW_CK_IN_L6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "CLK_HROW_CK_BUFHCLK_L11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "CLK_HROW_CK_BUFHCLK_L3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "CLK_HROW_CK_IN_L11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "CLK_HROW_CK_BUFHCLK_L8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "CLK_HROW_CK_BUFHCLK_L0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "CLK_HROW_CK_IN_L5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "CLK_HROW_CK_BUFHCLK_L1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "CLK_HROW_CK_BUFHCLK_L7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "CLK_HROW_CK_BUFHCLK_L10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "CLK_HROW_CK_IN_L9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "CLK_HROW_CK_IN_L7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "CLK_HROW_CK_IN_L0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "CLK_HROW_CK_BUFHCLK_L9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "CLK_HROW_CK_BUFRCLK_L0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "CLK_HROW_CK_IN_L4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "CLK_HROW_CK_IN_L3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "CLK_HROW_CK_IN_L13", + "HCLK_INT_INTERFACE_CK_IN13" + ], + [ + "CLK_HROW_CK_IN_L1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "CLK_HROW_CK_BUFHCLK_L4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "CLK_HROW_CK_BUFRCLK_L1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "CLK_HROW_CK_IN_L8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "CLK_HROW_CK_BUFRCLK_L3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "CLK_HROW_CK_BUFHCLK_L2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "CLK_HROW_CK_BUFHCLK_L6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "CLK_HROW_CK_IN_L10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "CLK_HROW_CK_BUFHCLK_L5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "HCLK_INT_INTERFACE" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_1_SW2A1", + "VBRK_SW2A1" + ], + [ + "INT_FEEDTHRU_1_SW2A3", + "VBRK_SW2A3" + ], + [ + "INT_FEEDTHRU_1_LH6", + "VBRK_LH6" + ], + [ + "INT_FEEDTHRU_1_EE4C1", + "VBRK_EE4C1" + ], + [ + "INT_FEEDTHRU_1_WW4END2", + "VBRK_WW4END2" + ], + [ + "INT_FEEDTHRU_1_WW4END1", + "VBRK_WW4END1" + ], + [ + "INT_FEEDTHRU_1_NW2A3", + "VBRK_NW2A3" + ], + [ + "INT_FEEDTHRU_1_WR1END0", + "VBRK_WR1END0" + ], + [ + "INT_FEEDTHRU_1_EE2BEG3", + "VBRK_EE2BEG3" + ], + [ + "INT_FEEDTHRU_1_LH11", + "VBRK_LH11" + ], + [ + "INT_FEEDTHRU_1_EE2A2", + "VBRK_EE2A2" + ], + [ + "INT_FEEDTHRU_1_LH8", + "VBRK_LH8" + ], + [ + "INT_FEEDTHRU_1_NE4C0", + "VBRK_NE4C0" + ], + [ + "INT_FEEDTHRU_1_ER1BEG2", + "VBRK_ER1BEG2" + ], + [ + "INT_FEEDTHRU_1_WW2A2", + "VBRK_WW2A2" + ], + [ + "INT_FEEDTHRU_1_SW4A0", + "VBRK_SW4A0" + ], + [ + "INT_FEEDTHRU_1_NW4A2", + "VBRK_NW4A2" + ], + [ + "INT_FEEDTHRU_1_EE4C2", + "VBRK_EE4C2" + ], + [ + "INT_FEEDTHRU_1_EL1BEG1", + "VBRK_EL1BEG1" + ], + [ + "INT_FEEDTHRU_1_EE4B0", + "VBRK_EE4B0" + ], + [ + "INT_FEEDTHRU_1_EE2A1", + "VBRK_EE2A1" + ], + [ + "INT_FEEDTHRU_1_EE4A2", + "VBRK_EE4A2" + ], + [ + "INT_FEEDTHRU_1_WW2END1", + "VBRK_WW2END1" + ], + [ + "INT_FEEDTHRU_1_LH2", + "VBRK_LH2" + ], + [ + "INT_FEEDTHRU_1_NE2A1", + "VBRK_NE2A1" + ], + [ + "INT_FEEDTHRU_1_LH10", + "VBRK_LH10" + ], + [ + "INT_FEEDTHRU_1_EE4BEG2", + "VBRK_EE4BEG2" + ], + [ + "INT_FEEDTHRU_1_NW4A3", + "VBRK_NW4A3" + ], + [ + "INT_FEEDTHRU_1_SE4C1", + "VBRK_SE4C1" + ], + [ + "INT_FEEDTHRU_1_SW4A2", + "VBRK_SW4A2" + ], + [ + "INT_FEEDTHRU_1_WW4B1", + "VBRK_WW4B1" + ], + [ + "INT_FEEDTHRU_1_LH5", + "VBRK_LH5" + ], + [ + "INT_FEEDTHRU_1_MONITOR_P", + "VBRK_MONITOR_P" + ], + [ + "INT_FEEDTHRU_1_NE2A3", + "VBRK_NE2A3" + ], + [ + "INT_FEEDTHRU_1_WW4C0", + "VBRK_WW4C0" + ], + [ + "INT_FEEDTHRU_1_SE4BEG2", + "VBRK_SE4BEG2" + ], + [ + "INT_FEEDTHRU_1_WR1END1", + "VBRK_WR1END1" + ], + [ + "INT_FEEDTHRU_1_NW4A1", + "VBRK_NW4A1" + ], + [ + "INT_FEEDTHRU_1_NW4A0", + "VBRK_NW4A0" + ], + [ + "INT_FEEDTHRU_1_SE4BEG3", + "VBRK_SE4BEG3" + ], + [ + "INT_FEEDTHRU_1_MONITOR_N", + "VBRK_MONITOR_N" + ], + [ + "INT_FEEDTHRU_1_EE4B3", + "VBRK_EE4B3" + ], + [ + "INT_FEEDTHRU_1_NE4BEG1", + "VBRK_NE4BEG1" + ], + [ + "INT_FEEDTHRU_1_LH7", + "VBRK_LH7" + ], + [ + "INT_FEEDTHRU_1_WW4END3", + "VBRK_WW4END3" + ], + [ + "INT_FEEDTHRU_1_NE4BEG3", + "VBRK_NE4BEG3" + ], + [ + "INT_FEEDTHRU_1_WL1END1", + "VBRK_WL1END1" + ], + [ + "INT_FEEDTHRU_1_WW4A3", + "VBRK_WW4A3" + ], + [ + "INT_FEEDTHRU_1_WW4B2", + "VBRK_WW4B2" + ], + [ + "INT_FEEDTHRU_1_EE4C0", + "VBRK_EE4C0" + ], + [ + "INT_FEEDTHRU_1_NW2A1", + "VBRK_NW2A1" + ], + [ + "INT_FEEDTHRU_1_NW4END1", + "VBRK_NW4END1" + ], + [ + "INT_FEEDTHRU_1_EE2A3", + "VBRK_EE2A3" + ], + [ + "INT_FEEDTHRU_1_WW4END0", + "VBRK_WW4END0" + ], + [ + "INT_FEEDTHRU_1_NE4BEG2", + "VBRK_NE4BEG2" + ], + [ + "INT_FEEDTHRU_1_SW2A2", + "VBRK_SW2A2" + ], + [ + "INT_FEEDTHRU_1_WW2A1", + "VBRK_WW2A1" + ], + [ + "INT_FEEDTHRU_1_SE2A1", + "VBRK_SE2A1" + ], + [ + "INT_FEEDTHRU_1_WW4B3", + "VBRK_WW4B3" + ], + [ + "INT_FEEDTHRU_1_EE2BEG1", + "VBRK_EE2BEG1" + ], + [ + "INT_FEEDTHRU_1_WW4C3", + "VBRK_WW4C3" + ], + [ + "INT_FEEDTHRU_1_SW4A1", + "VBRK_SW4A1" + ], + [ + "INT_FEEDTHRU_1_EE4C3", + "VBRK_EE4C3" + ], + [ + "INT_FEEDTHRU_1_NW4END2", + "VBRK_NW4END2" + ], + [ + "INT_FEEDTHRU_1_SW4A3", + "VBRK_SW4A3" + ], + [ + "INT_FEEDTHRU_1_LH9", + "VBRK_LH9" + ], + [ + "INT_FEEDTHRU_1_LH1", + "VBRK_LH1" + ], + [ + "INT_FEEDTHRU_1_SE2A0", + "VBRK_SE2A0" + ], + [ + "INT_FEEDTHRU_1_SE2A2", + "VBRK_SE2A2" + ], + [ + "INT_FEEDTHRU_1_EE4BEG0", + "VBRK_EE4BEG0" + ], + [ + "INT_FEEDTHRU_1_SE4BEG0", + "VBRK_SE4BEG0" + ], + [ + "INT_FEEDTHRU_1_WL1END2", + "VBRK_WL1END2" + ], + [ + "INT_FEEDTHRU_1_EE4A3", + "VBRK_EE4A3" + ], + [ + "INT_FEEDTHRU_1_LH12", + "VBRK_LH12" + ], + [ + "INT_FEEDTHRU_1_SE4C2", + "VBRK_SE4C2" + ], + [ + "INT_FEEDTHRU_1_WW2A3", + "VBRK_WW2A3" + ], + [ + "INT_FEEDTHRU_1_WW4C1", + "VBRK_WW4C1" + ], + [ + "INT_FEEDTHRU_1_EE4A0", + "VBRK_EE4A0" + ], + [ + "INT_FEEDTHRU_1_EE4B1", + "VBRK_EE4B1" + ], + [ + "INT_FEEDTHRU_1_WR1END2", + "VBRK_WR1END2" + ], + [ + "INT_FEEDTHRU_1_WW4C2", + "VBRK_WW4C2" + ], + [ + "INT_FEEDTHRU_1_NE2A0", + "VBRK_NE2A0" + ], + [ + "INT_FEEDTHRU_1_NE4C1", + "VBRK_NE4C1" + ], + [ + "INT_FEEDTHRU_1_EE4A1", + "VBRK_EE4A1" + ], + [ + "INT_FEEDTHRU_1_WW4A2", + "VBRK_WW4A2" + ], + [ + "INT_FEEDTHRU_1_ER1BEG0", + "VBRK_ER1BEG0" + ], + [ + "INT_FEEDTHRU_1_SE4BEG1", + "VBRK_SE4BEG1" + ], + [ + "INT_FEEDTHRU_1_NE4BEG0", + "VBRK_NE4BEG0" + ], + [ + "INT_FEEDTHRU_1_NE2A2", + "VBRK_NE2A2" + ], + [ + "INT_FEEDTHRU_1_WW4A1", + "VBRK_WW4A1" + ], + [ + "INT_FEEDTHRU_1_NW2A2", + "VBRK_NW2A2" + ], + [ + "INT_FEEDTHRU_1_EE2A0", + "VBRK_EE2A0" + ], + [ + "INT_FEEDTHRU_1_SW4END0", + "VBRK_SW4END0" + ], + [ + "INT_FEEDTHRU_1_EE4B2", + "VBRK_EE4B2" + ], + [ + "INT_FEEDTHRU_1_SW4END1", + "VBRK_SW4END1" + ], + [ + "INT_FEEDTHRU_1_EL1BEG0", + "VBRK_EL1BEG0" + ], + [ + "INT_FEEDTHRU_1_EE2BEG2", + "VBRK_EE2BEG2" + ], + [ + "INT_FEEDTHRU_1_WW2END3", + "VBRK_WW2END3" + ], + [ + "INT_FEEDTHRU_1_WW2END0", + "VBRK_WW2END0" + ], + [ + "INT_FEEDTHRU_1_SE2A3", + "VBRK_SE2A3" + ], + [ + "INT_FEEDTHRU_1_LH4", + "VBRK_LH4" + ], + [ + "INT_FEEDTHRU_1_SW4END2", + "VBRK_SW4END2" + ], + [ + "INT_FEEDTHRU_1_WL1END0", + "VBRK_WL1END0" + ], + [ + "INT_FEEDTHRU_1_EL1BEG2", + "VBRK_EL1BEG2" + ], + [ + "INT_FEEDTHRU_1_WW4B0", + "VBRK_WW4B0" + ], + [ + "INT_FEEDTHRU_1_WR1END3", + "VBRK_WR1END3" + ], + [ + "INT_FEEDTHRU_1_NW2A0", + "VBRK_NW2A0" + ], + [ + "INT_FEEDTHRU_1_WW2A0", + "VBRK_WW2A0" + ], + [ + "INT_FEEDTHRU_1_EE4BEG3", + "VBRK_EE4BEG3" + ], + [ + "INT_FEEDTHRU_1_NW4END0", + "VBRK_NW4END0" + ], + [ + "INT_FEEDTHRU_1_NE4C3", + "VBRK_NE4C3" + ], + [ + "INT_FEEDTHRU_1_WW4A0", + "VBRK_WW4A0" + ], + [ + "INT_FEEDTHRU_1_WW2END2", + "VBRK_WW2END2" + ], + [ + "INT_FEEDTHRU_1_ER1BEG1", + "VBRK_ER1BEG1" + ], + [ + "INT_FEEDTHRU_1_WL1END3", + "VBRK_WL1END3" + ], + [ + "INT_FEEDTHRU_1_EE2BEG0", + "VBRK_EE2BEG0" + ], + [ + "INT_FEEDTHRU_1_NW4END3", + "VBRK_NW4END3" + ], + [ + "INT_FEEDTHRU_1_LH3", + "VBRK_LH3" + ], + [ + "INT_FEEDTHRU_1_SW4END3", + "VBRK_SW4END3" + ], + [ + "INT_FEEDTHRU_1_SE4C0", + "VBRK_SE4C0" + ], + [ + "INT_FEEDTHRU_1_EL1BEG3", + "VBRK_EL1BEG3" + ], + [ + "INT_FEEDTHRU_1_SW2A0", + "VBRK_SW2A0" + ], + [ + "INT_FEEDTHRU_1_SE4C3", + "VBRK_SE4C3" + ], + [ + "INT_FEEDTHRU_1_EE4BEG1", + "VBRK_EE4BEG1" + ], + [ + "INT_FEEDTHRU_1_ER1BEG3", + "VBRK_ER1BEG3" + ], + [ + "INT_FEEDTHRU_1_NE4C2", + "VBRK_NE4C2" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_1", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "IOB_IBUF0", + "LIOI_IBUF0" + ], + [ + "IOB_KEEPER_INT_EN_1", + "LIOI_KEEPER_INT_EN_1" + ], + [ + "IOB_PU_INT_EN_1", + "LIOI_PU_INT_EN_1" + ], + [ + "IOB_PD_INT_EN_1", + "LIOI_PD_INT_EN_1" + ], + [ + "LIOB_IN_TERM0", + "LIOI_DCI_T_TERM0" + ], + [ + "IOB_T0", + "LIOI_T0" + ], + [ + "IOB_IBUF_DISABLE0", + "LIOI_IBUF_DISABLE0" + ], + [ + "IOB_O0", + "LIOI_O0" + ] + ], + "tile_types": [ + "LIOB33_SING", + "LIOI3_SING" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH3_4", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH4_4", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH12_4", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH11_4", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH9_4", + "VBRK_LH9" + ], + [ + "CMT_TOP_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH1_4", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_LH10_4", + "VBRK_LH10" + ], + [ + "CMT_TOP_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH2_4", + "VBRK_LH2" + ], + [ + "CMT_TOP_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_LH8_4", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH7_4", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_4", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH6_4", + "VBRK_LH6" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 3 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_3" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_3" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_3" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_3" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_3" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_3" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_3" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_3" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_3" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_3" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_3" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_3" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_3" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_3" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_3" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_3" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_3" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_3" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_3" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_3" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_3" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_3" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_3" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_3" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_3" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_3" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_3" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_3" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_3" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_3" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_3" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_3" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_3" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_3" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_3" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_3" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_3" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_3" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_3" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_3" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_3" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_3" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_3" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_3" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_3" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_3" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_3" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_3" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_3" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_3" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_3" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_3" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_3" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_3" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_3" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_3" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_3" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_3" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_3" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_3" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_3" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_3" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_3" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_3" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_3" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_3" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_3" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_3" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_3" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_3" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_3" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_3" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_3" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_3" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_3" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_3" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_3" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_3" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_3" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_3" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_3" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_3" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_3" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_3" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_3" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_3" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_3" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_3" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_3" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_3" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_3" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_3" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_3" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_3" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_3" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_3" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_3" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_3" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_3" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_3" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_3" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_3" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_3" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_3" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_3" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_3" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_3" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_3" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_3" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_3" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_3" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_3" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_3" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_3" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_3" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_3" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_3" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_3" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_3" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_3" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_MID_FUJI2" + ] + }, + { + "grid_deltas": [ + 0, + 8 + ], + "wire_pairs": [ + [ + "BRKH_CMT_PHASEREF1", + "CMT_PLL_PHASERREF_ABOVE1" + ], + [ + "BRKH_CMT_PHASEREF_BELOW1", + "CMT_PLL_PHASERREF1" + ], + [ + "BRKH_CMT_PHYCTRL_SYNC_BB", + "CMT_PLL_PHYCTRL_SYNC_BB_UP" + ], + [ + "BRKH_CMT_FREQ_REF_NS0", + "PLL_CLK_FREQ_BB_BUFOUT_NS0" + ], + [ + "BRKH_CMT_FREQ_REF_NS3", + "PLL_CLK_FREQ_BB_BUFOUT_NS3" + ], + [ + "BRKH_CMT_PHASEREF0", + "CMT_PLL_PHASERREF_ABOVE0" + ], + [ + "BRKH_CMT_FREQ_REF_NS2", + "PLL_CLK_FREQ_BB_BUFOUT_NS2" + ], + [ + "BRKH_CMT_PHASEREF_BELOW0", + "CMT_PLL_PHASERREF0" + ], + [ + "BRKH_CMT_FREQ_REF_NS1", + "PLL_CLK_FREQ_BB_BUFOUT_NS1" + ] + ], + "tile_types": [ + "BRKH_CMT", + "CMT_TOP_R_UPPER_T" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CFG_CENTER_IMUX7_10", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_WR1END1_10", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_BYP0_10", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_FAN7_10", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX37_10", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_LH5_10", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX5_10", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX24_10", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_WW4A1_10", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_LH10_10", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_IMUX21_10", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_EL1BEG0_10", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_IMUX36_10", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_CTRL0_10", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_SE2A2_10", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX31_10", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_EE2A3_10", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NE4C3_10", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_EE4B3_10", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_EE2BEG1_10", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX34_10", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_SE4BEG2_10", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_NW2A0_10", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_WW2A1_10", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_EL1BEG1_10", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_EE4A1_10", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX23_10", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_IMUX46_10", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW4A2_10", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_LH4_10", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_WW2A0_10", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_BYP7_10", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_EL1BEG3_10", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW4B2_10", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_WW4END3_10", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX15_10", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_FAN0_10", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_WW4A0_10", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_BYP1_10", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SW4A3_10", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_IMUX27_10", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX8_10", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_IMUX3_10", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_BYP5_10", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_WW4C1_10", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_NE2A1_10", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX30_10", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_CLK0_10", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_WW2END1_10", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_ER1BEG2_10", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX14_10", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_WW2END3_10", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_10", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_IMUX13_10", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_IMUX6_10", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX0_10", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_NW2A3_10", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_WL1END0_10", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_IMUX45_10", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX38_10", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_SW4END0_10", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_LH3_10", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX4_10", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_SW4A1_10", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_NE2A3_10", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_SE4BEG1_10", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_IMUX42_10", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_SW2A0_10", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_WL1END3_10", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_WW2A2_10", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_NW4END1_10", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_EL1BEG2_10", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX16_10", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_SW2A3_10", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_NW2A2_10", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_ER1BEG1_10", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_EE4B2_10", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_EE2A2_10", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_EE4A3_10", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_SW2A2_10", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_NW4A0_10", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_SW4END1_10", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_ER1BEG3_10", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_IMUX47_10", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_EE4A0_10", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_SE4C1_10", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX18_10", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX1_10", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_BYP2_10", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_NE4BEG2_10", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_IMUX40_10", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_FAN6_10", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_EE4A2_10", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_EE4BEG2_10", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_10", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_SW4END3_10", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_SW4A2_10", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_10", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_IMUX32_10", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_SW4END2_10", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_SE4C3_10", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_NW4A2_10", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_IMUX25_10", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_IMUX12_10", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX35_10", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_LH2_10", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_FAN2_10", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_EE4B1_10", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_NW4END3_10", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_NW4END2_10", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_EE2BEG2_10", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_SW4A0_10", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_IMUX22_10", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_NW4A1_10", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_IMUX41_10", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_WW2END2_10", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_NW4A3_10", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_WW4A3_10", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_BYP6_10", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_WL1END1_10", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_EE4C0_10", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_NW2A1_10", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_WW4B0_10", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_WW4B1_10", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_NE2A2_10", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_NE4C0_10", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE4C3_10", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_FAN3_10", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_FAN1_10", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_EE4B0_10", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_IMUX19_10", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_WL1END2_10", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_EE2BEG3_10", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX28_10", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_SE4BEG0_10", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_WR1END2_10", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_FAN5_10", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_NE2A0_10", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_WW4C3_10", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX9_10", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_WW2A3_10", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_WW4C2_10", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_BYP4_10", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WW4END2_10", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_ER1BEG0_10", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_SE4C0_10", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_WR1END3_10", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_LH1_10", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_WW4END1_10", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX10_10", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_WW4B3_10", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_10", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_WW4C0_10", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_10", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_EE4C2_10", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_SW2A1_10", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_CLK1_10", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_EE4BEG0_10", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_EE4BEG1_10", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_IMUX11_10", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX2_10", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_SE2A3_10", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_IMUX29_10", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_10", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_IMUX44_10", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_CTRL1_10", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_NE4C1_10", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_LH12_10", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_EE2A0_10", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WR1END0_10", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EE2A1_10", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_10", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_EE4C1_10", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX33_10", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_WW2END0_10", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_NE4BEG0_10", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_10", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_BYP3_10", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_SE2A0_10", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_NE4C2_10", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_LH7_10", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_LH11_10", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_SE4C2_10", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_LH6_10", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_FAN4_10", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_10", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_10", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_NE4BEG3_10", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX43_10", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX26_10", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_LH8_10", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_IMUX17_10", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX20_10", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_EE4BEG3_10", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_NW4END0_10", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX39_10", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_SE4BEG3_10", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_WW4END0_10", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_EE2BEG0_10", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_LH9_10", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_SE2A1_10", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NE4BEG1_10", + "VFRAME_NE4BEG1" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + -5 + ], + "wire_pairs": [ + [ + "CMT_TOP_EE2BEG2_9", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NE4C0_9", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EE2A0_9", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_9", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SE4BEG2_9", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_NE2A2_9", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW2A2_9", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_LH6_9", + "VBRK_LH6" + ], + [ + "CMT_TOP_EE4B1_9", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW4A1_9", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SW4A2_9", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WR1END2_9", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH8_9", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A3_9", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4BEG3_9", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WW2END2_9", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2A1_9", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4A0_9", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4C1_9", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NE4C3_9", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW2A0_9", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_9", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2END0_9", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4C2_9", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A3_9", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_ER1BEG0_9", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EL1BEG1_9", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG0_9", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH3_9", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END2_9", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH2_9", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW4A3_9", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW2A2_9", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4A2_9", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END3_9", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE2A3_9", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4BEG2_9", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4END0_9", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SW4A0_9", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4C1_9", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A1_9", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4END2_9", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EL1BEG3_9", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_9", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW2A0_9", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4B0_9", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE4C0_9", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE4B3_9", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW4A1_9", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4C1_9", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_LH4_9", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2BEG1_9", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4A0_9", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4BEG0_9", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_9", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2A2_9", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EE4A1_9", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4END0_9", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW4B1_9", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4A3_9", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END3_9", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH11_9", + "VBRK_LH11" + ], + [ + "CMT_TOP_SW4END3_9", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_9", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END1_9", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_LH12_9", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C1_9", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE4C3_9", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_SE2A1_9", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE4A0_9", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_EE2BEG3_9", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END1_9", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A1_9", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE2BEG0_9", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE2A2_9", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END3_9", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_ER1BEG3_9", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NE2A3_9", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW2A3_9", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_9", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH9_9", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4B0_9", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A0_9", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NE4BEG2_9", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A2_9", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_WW4C0_9", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SW2A1_9", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH5_9", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END0_9", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NE4BEG1_9", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_9", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A2_9", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4BEG1_9", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C0_9", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_WW4END2_9", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_WW4END1_9", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NW2A0_9", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4C2_9", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_WW4B3_9", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WR1END0_9", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW2A3_9", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW2A2_9", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_EE4BEG3_9", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C2_9", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_SE4BEG1_9", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_9", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_NE2A0_9", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4B2_9", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WL1END2_9", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG0_9", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG2_9", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4C3_9", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4A1_9", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH1_9", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW4END0_9", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_EE4A3_9", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_LH10_9", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW2END1_9", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WL1END3_9", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_EE2A1_9", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4C3_9", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WR1END3_9", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SW2A3_9", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH7_9", + "VBRK_LH7" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B11_6", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_LOGIC_OUTS_B2_6", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX5_6", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_CLK1_6", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX6_6", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX3_6", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_LOGIC_OUTS_B20_6", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX22_6", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B0_6", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX21_6", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_CLK0_6", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_LOGIC_OUTS_B14_6", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX24_6", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX39_6", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B9_6", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_LOGIC_OUTS_B5_6", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX46_6", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP3_6", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_FAN1_6", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B3_6", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX30_6", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_FAN4_6", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_LOGIC_OUTS_B10_6", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX42_6", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_LOGIC_OUTS_B6_6", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX28_6", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX8_6", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX45_6", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX10_6", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B16_6", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX36_6", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX44_6", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX33_6", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_BYP7_6", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX15_6", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX41_6", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX25_6", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_CTRL1_6", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_6", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX12_6", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B22_6", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX19_6", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_BYP6_6", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX40_6", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX32_6", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN0_6", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX27_6", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX37_6", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX0_6", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX35_6", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_BYP2_6", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_BYP0_6", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX31_6", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX13_6", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_FAN2_6", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX2_6", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_LOGIC_OUTS_B12_6", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_BYP5_6", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_CTRL0_6", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_LOGIC_OUTS_B17_6", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX9_6", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX29_6", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX16_6", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_LOGIC_OUTS_B1_6", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_FAN5_6", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX18_6", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX43_6", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX4_6", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_LOGIC_OUTS_B8_6", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_LOGIC_OUTS_B15_6", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_LOGIC_OUTS_B13_6", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_IMUX38_6", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX7_6", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_BYP1_6", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B23_6", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX23_6", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_FAN7_6", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B7_6", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B4_6", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_IMUX26_6", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX20_6", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN3_6", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX34_6", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX47_6", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_BYP4_6", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX11_6", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_FAN6_6", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX14_6", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX1_6", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX17_6", + "VBRK_EXT_IMUX17" + ] + ], + "tile_types": [ + "GTX_CHANNEL_1", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + -5 + ], + "wire_pairs": [ + [ + "CLK_PMV_WW4END0_5", + "VBRK_WW4END0" + ], + [ + "CLK_PMV_WR1END0_5", + "VBRK_WR1END0" + ], + [ + "CLK_PMV_EE4A0_5", + "VBRK_EE4A0" + ], + [ + "CLK_PMV_SW2A1_5", + "VBRK_SW2A1" + ], + [ + "CLK_PMV_WL1END0_5", + "VBRK_WL1END0" + ], + [ + "CLK_PMV_WW4A1_5", + "VBRK_WW4A1" + ], + [ + "CLK_PMV_SW4END1_5", + "VBRK_SW4END1" + ], + [ + "CLK_PMV_WW2END0_5", + "VBRK_WW2END0" + ], + [ + "CLK_PMV_NW2A0_5", + "VBRK_NW2A0" + ], + [ + "CLK_PMV_WR1END3_5", + "VBRK_WR1END3" + ], + [ + "CLK_PMV_EL1BEG0_5", + "VBRK_EL1BEG0" + ], + [ + "CLK_PMV_SW4END0_5", + "VBRK_SW4END0" + ], + [ + "CLK_PMV_WW4END2_5", + "VBRK_WW4END2" + ], + [ + "CLK_PMV_NW4A2_5", + "VBRK_NW4A2" + ], + [ + "CLK_PMV_WW4C3_5", + "VBRK_WW4C3" + ], + [ + "CLK_PMV_LH8_5", + "VBRK_LH8" + ], + [ + "CLK_PMV_NE2A1_5", + "VBRK_NE2A1" + ], + [ + "CLK_PMV_NE4BEG3_5", + "VBRK_NE4BEG3" + ], + [ + "CLK_PMV_SW2A2_5", + "VBRK_SW2A2" + ], + [ + "CLK_PMV_NE2A3_5", + "VBRK_NE2A3" + ], + [ + "CLK_PMV_EE2BEG1_5", + "VBRK_EE2BEG1" + ], + [ + "CLK_PMV_NE4C3_5", + "VBRK_NE4C3" + ], + [ + "CLK_PMV_WW4A3_5", + "VBRK_WW4A3" + ], + [ + "CLK_PMV_EL1BEG2_5", + "VBRK_EL1BEG2" + ], + [ + "CLK_PMV_WW2A1_5", + "VBRK_WW2A1" + ], + [ + "CLK_PMV_NW2A1_5", + "VBRK_NW2A1" + ], + [ + "CLK_PMV_EE2A2_5", + "VBRK_EE2A2" + ], + [ + "CLK_PMV_SW4A3_5", + "VBRK_SW4A3" + ], + [ + "CLK_PMV_ER1BEG0_5", + "VBRK_ER1BEG0" + ], + [ + "CLK_PMV_SE2A3_5", + "VBRK_SE2A3" + ], + [ + "CLK_PMV_SE4BEG3_5", + "VBRK_SE4BEG3" + ], + [ + "CLK_PMV_EE4C2_5", + "VBRK_EE4C2" + ], + [ + "CLK_PMV_NW4END1_5", + "VBRK_NW4END1" + ], + [ + "CLK_PMV_NW4END2_5", + "VBRK_NW4END2" + ], + [ + "CLK_PMV_NW4A0_5", + "VBRK_NW4A0" + ], + [ + "CLK_PMV_SE2A1_5", + "VBRK_SE2A1" + ], + [ + "CLK_PMV_EE4BEG0_5", + "VBRK_EE4BEG0" + ], + [ + "CLK_PMV_NW4A3_5", + "VBRK_NW4A3" + ], + [ + "CLK_PMV_WW4END1_5", + "VBRK_WW4END1" + ], + [ + "CLK_PMV_WR1END2_5", + "VBRK_WR1END2" + ], + [ + "CLK_PMV_EE4A2_5", + "VBRK_EE4A2" + ], + [ + "CLK_PMV_NE2A0_5", + "VBRK_NE2A0" + ], + [ + "CLK_PMV_ER1BEG1_5", + "VBRK_ER1BEG1" + ], + [ + "CLK_PMV_SW4A2_5", + "VBRK_SW4A2" + ], + [ + "CLK_PMV_SW4END2_5", + "VBRK_SW4END2" + ], + [ + "CLK_PMV_WW2A2_5", + "VBRK_WW2A2" + ], + [ + "CLK_PMV_NW2A3_5", + "VBRK_NW2A3" + ], + [ + "CLK_PMV_WL1END1_5", + "VBRK_WL1END1" + ], + [ + "CLK_PMV_EE2A3_5", + "VBRK_EE2A3" + ], + [ + "CLK_PMV_WW4C2_5", + "VBRK_WW4C2" + ], + [ + "CLK_PMV_NE4BEG0_5", + "VBRK_NE4BEG0" + ], + [ + "CLK_PMV_NE4C0_5", + "VBRK_NE4C0" + ], + [ + "CLK_PMV_EE4C1_5", + "VBRK_EE4C1" + ], + [ + "CLK_PMV_EE4C3_5", + "VBRK_EE4C3" + ], + [ + "CLK_PMV_EE4B0_5", + "VBRK_EE4B0" + ], + [ + "CLK_PMV_LH5_5", + "VBRK_LH5" + ], + [ + "CLK_PMV_ER1BEG3_5", + "VBRK_ER1BEG3" + ], + [ + "CLK_PMV_WW2A3_5", + "VBRK_WW2A3" + ], + [ + "CLK_PMV_SE4C2_5", + "VBRK_SE4C2" + ], + [ + "CLK_PMV_SW4END3_5", + "VBRK_SW4END3" + ], + [ + "CLK_PMV_LH9_5", + "VBRK_LH9" + ], + [ + "CLK_PMV_WW4END3_5", + "VBRK_WW4END3" + ], + [ + "CLK_PMV_EE4A1_5", + "VBRK_EE4A1" + ], + [ + "CLK_PMV_NE4BEG1_5", + "VBRK_NE4BEG1" + ], + [ + "CLK_PMV_LH2_5", + "VBRK_LH2" + ], + [ + "CLK_PMV_WL1END3_5", + "VBRK_WL1END3" + ], + [ + "CLK_PMV_WW4C1_5", + "VBRK_WW4C1" + ], + [ + "CLK_PMV_SW4A0_5", + "VBRK_SW4A0" + ], + [ + "CLK_PMV_SE4BEG0_5", + "VBRK_SE4BEG0" + ], + [ + "CLK_PMV_EL1BEG1_5", + "VBRK_EL1BEG1" + ], + [ + "CLK_PMV_EE2A0_5", + "VBRK_EE2A0" + ], + [ + "CLK_PMV_SE4C3_5", + "VBRK_SE4C3" + ], + [ + "CLK_PMV_LH10_5", + "VBRK_LH10" + ], + [ + "CLK_PMV_EE2BEG0_5", + "VBRK_EE2BEG0" + ], + [ + "CLK_PMV_SE2A2_5", + "VBRK_SE2A2" + ], + [ + "CLK_PMV_WW4B2_5", + "VBRK_WW4B2" + ], + [ + "CLK_PMV_LH6_5", + "VBRK_LH6" + ], + [ + "CLK_PMV_EE4BEG2_5", + "VBRK_EE4BEG2" + ], + [ + "CLK_PMV_LH4_5", + "VBRK_LH4" + ], + [ + "CLK_PMV_WW4B3_5", + "VBRK_WW4B3" + ], + [ + "CLK_PMV_WW4C0_5", + "VBRK_WW4C0" + ], + [ + "CLK_PMV_LH7_5", + "VBRK_LH7" + ], + [ + "CLK_PMV_LH1_5", + "VBRK_LH1" + ], + [ + "CLK_PMV_EE4B3_5", + "VBRK_EE4B3" + ], + [ + "CLK_PMV_LH3_5", + "VBRK_LH3" + ], + [ + "CLK_PMV_EE2BEG3_5", + "VBRK_EE2BEG3" + ], + [ + "CLK_PMV_NW4A1_5", + "VBRK_NW4A1" + ], + [ + "CLK_PMV_WL1END2_5", + "VBRK_WL1END2" + ], + [ + "CLK_PMV_WW2END3_5", + "VBRK_WW2END3" + ], + [ + "CLK_PMV_LH11_5", + "VBRK_LH11" + ], + [ + "CLK_PMV_EE4B1_5", + "VBRK_EE4B1" + ], + [ + "CLK_PMV_EE4BEG1_5", + "VBRK_EE4BEG1" + ], + [ + "CLK_PMV_WW4A2_5", + "VBRK_WW4A2" + ], + [ + "CLK_PMV_SW2A0_5", + "VBRK_SW2A0" + ], + [ + "CLK_PMV_EE2BEG2_5", + "VBRK_EE2BEG2" + ], + [ + "CLK_PMV_WR1END1_5", + "VBRK_WR1END1" + ], + [ + "CLK_PMV_NW4END0_5", + "VBRK_NW4END0" + ], + [ + "CLK_PMV_NE4C1_5", + "VBRK_NE4C1" + ], + [ + "CLK_PMV_WW2END2_5", + "VBRK_WW2END2" + ], + [ + "CLK_PMV_SW2A3_5", + "VBRK_SW2A3" + ], + [ + "CLK_PMV_SW4A1_5", + "VBRK_SW4A1" + ], + [ + "CLK_PMV_NE4C2_5", + "VBRK_NE4C2" + ], + [ + "CLK_PMV_SE4BEG2_5", + "VBRK_SE4BEG2" + ], + [ + "CLK_PMV_EE4BEG3_5", + "VBRK_EE4BEG3" + ], + [ + "CLK_PMV_EL1BEG3_5", + "VBRK_EL1BEG3" + ], + [ + "CLK_PMV_NE4BEG2_5", + "VBRK_NE4BEG2" + ], + [ + "CLK_PMV_WW4B0_5", + "VBRK_WW4B0" + ], + [ + "CLK_PMV_NW4END3_5", + "VBRK_NW4END3" + ], + [ + "CLK_PMV_WW2END1_5", + "VBRK_WW2END1" + ], + [ + "CLK_PMV_EE4B2_5", + "VBRK_EE4B2" + ], + [ + "CLK_PMV_EE2A1_5", + "VBRK_EE2A1" + ], + [ + "CLK_PMV_WW4B1_5", + "VBRK_WW4B1" + ], + [ + "CLK_PMV_EE4C0_5", + "VBRK_EE4C0" + ], + [ + "CLK_PMV_SE4C0_5", + "VBRK_SE4C0" + ], + [ + "CLK_PMV_EE4A3_5", + "VBRK_EE4A3" + ], + [ + "CLK_PMV_WW2A0_5", + "VBRK_WW2A0" + ], + [ + "CLK_PMV_SE4C1_5", + "VBRK_SE4C1" + ], + [ + "CLK_PMV_SE2A0_5", + "VBRK_SE2A0" + ], + [ + "CLK_PMV_LH12_5", + "VBRK_LH12" + ], + [ + "CLK_PMV_NW2A2_5", + "VBRK_NW2A2" + ], + [ + "CLK_PMV_NE2A2_5", + "VBRK_NE2A2" + ], + [ + "CLK_PMV_SE4BEG1_5", + "VBRK_SE4BEG1" + ], + [ + "CLK_PMV_WW4A0_5", + "VBRK_WW4A0" + ], + [ + "CLK_PMV_ER1BEG2_5", + "VBRK_ER1BEG2" + ] + ], + "tile_types": [ + "CLK_PMV", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CMT_FIFO_LH7_6", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_NW4END3_6", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_NW4A2_6", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_LH6_6", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_SW4A2_6", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_L_FAN1_6", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_WW4C1_6", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_SW4A3_6", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_L_CTRL0_6", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_SE2A3_6", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_6", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "CMT_FIFO_WL1END1_6", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_EE4B3_6", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_EE4A2_6", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_IMUX28_6", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_L_IMUX0_6", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_EE4C0_6", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_L_CTRL1_6", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_L_FAN5_6", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_WW4A3_6", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_ER1BEG3_6", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_L_IMUX9_6", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX46_6", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_6", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "CMT_FIFO_WW2A3_6", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_EE4C3_6", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_NW4A3_6", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_EE4A3_6", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_BYP6_6", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_WW4A2_6", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_WW2END1_6", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_6", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "CMT_FIFO_NE4C1_6", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_NE4C0_6", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_L_IMUX39_6", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_L_IMUX4_6", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_SE4BEG3_6", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_WR1END3_6", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_NE4BEG2_6", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX18_6", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_6", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "CMT_FIFO_NE2A1_6", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_6", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "CMT_FIFO_SW4A0_6", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_L_IMUX8_6", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_EE2A1_6", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_SW4END3_6", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_EE2A3_6", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_L_IMUX25_6", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_L_FAN7_6", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_SW4END1_6", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_L_FAN2_6", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_L_BYP5_6", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_L_IMUX40_6", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_EE2A2_6", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_EL1BEG3_6", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_NW4END0_6", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_MONITOR_N_6", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CMT_FIFO_SE4C1_6", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_L_IMUX33_6", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_L_BYP4_6", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_NE2A0_6", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_IMUX29_6", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_NW2A2_6", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_EL1BEG0_6", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_WR1END0_6", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_L_BYP1_6", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_NE4BEG3_6", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_EL1BEG2_6", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_WW2END0_6", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_6", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "CMT_FIFO_L_IMUX13_6", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_WW2A2_6", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_WL1END3_6", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_WW4B2_6", + "INT_INTERFACE_WW4B2" + ], + [ + "FIFO_DQS_IOTOPHASER_1", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "CMT_FIFO_L_IMUX15_6", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_CLK1_6", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_EE4B1_6", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_6", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "CMT_FIFO_NE4BEG0_6", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_6", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "CMT_FIFO_WW4END3_6", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_SE4BEG0_6", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_EL1BEG1_6", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_ER1BEG2_6", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_IMUX35_6", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_NE4C2_6", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_LH3_6", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_L_IMUX2_6", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_L_IMUX36_6", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_L_IMUX31_6", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_WW4B3_6", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_WW2END2_6", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_6", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "CMT_FIFO_L_IMUX38_6", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_L_BYP0_6", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_NW2A3_6", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_L_IMUX30_6", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_SE2A2_6", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_SW2A0_6", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_L_IMUX3_6", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_L_FAN3_6", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_SW4END2_6", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_EE2BEG1_6", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_L_BYP2_6", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_L_IMUX17_6", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_NE4BEG1_6", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_WW4C0_6", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_EE4B0_6", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_L_IMUX7_6", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_EE4BEG3_6", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_MONITOR_P_6", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CMT_FIFO_L_IMUX22_6", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_SE4C3_6", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_BYP7_6", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_L_IMUX47_6", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_LH1_6", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_L_IMUX37_6", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_NW4A1_6", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_WW4END0_6", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_6", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_6", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "CMT_FIFO_LH2_6", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_LH8_6", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_6", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_NW2A1_6", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_L_IMUX24_6", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_L_IMUX44_6", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_IMUX21_6", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_L_FAN4_6", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_6", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "CMT_FIFO_L_FAN0_6", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_L_IMUX27_6", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_SW2A3_6", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_NW4A0_6", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_ER1BEG0_6", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_EE4A0_6", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_WW4END2_6", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_NW4END2_6", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_SW4A1_6", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_L_IMUX19_6", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_WW2A1_6", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_SW2A1_6", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_SE4C2_6", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_EE2BEG0_6", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_IMUX11_6", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_6", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "CMT_FIFO_NE4C3_6", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_6", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_EE4C2_6", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_SE4C0_6", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_6", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "CMT_FIFO_EE2BEG3_6", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_WW4B0_6", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_LH12_6", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_LH11_6", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_L_IMUX5_6", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_WL1END0_6", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_6", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "CMT_FIFO_SE2A1_6", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_SW2A2_6", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_WW4C3_6", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_WW4C2_6", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_IMUX34_6", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_WW2END3_6", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_SW4END0_6", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_WL1END2_6", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_L_IMUX10_6", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_EE4BEG1_6", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_6", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "CMT_FIFO_LH4_6", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_EE2BEG2_6", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_L_IMUX23_6", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_6", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "CMT_FIFO_WR1END1_6", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_L_IMUX45_6", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_SE2A0_6", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_EE4A1_6", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_L_IMUX41_6", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_FAN6_6", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_WW4END1_6", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_NW4END1_6", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_LH10_6", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_L_BYP3_6", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_SE4BEG2_6", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_ER1BEG1_6", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_IMUX20_6", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_6", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "CMT_FIFO_NW2A0_6", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_6", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "CMT_FIFO_L_IMUX14_6", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_WW4A0_6", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_L_IMUX12_6", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_LH5_6", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_L_IMUX42_6", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_IMUX26_6", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_IMUX1_6", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_NE2A2_6", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_L_IMUX43_6", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_EE4C1_6", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_EE4BEG0_6", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_EE2A0_6", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_WW4B1_6", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_EE4B2_6", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_L_IMUX6_6", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_WW2A0_6", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_L_CLK0_6", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_SE4BEG1_6", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_6", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_6", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "CMT_FIFO_WW4A1_6", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_WR1END2_6", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_LH9_6", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_NE2A3_6", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_L_IMUX32_6", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_6", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "CMT_FIFO_EE4BEG2_6", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX16_6", + "INT_INTERFACE_IMUX16" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLK_HROW_FAN1_0", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_WW4A2_0", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_BUFG_IMUX10_0", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_BUFG_IMUX38_0", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_EE2BEG2_0", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_SE4BEG2_0", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_BUFG_IMUX5_0", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_BYP5_0", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_NW2A2_0", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_FAN3_0", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_EE4A2_0", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_ER1BEG3_0", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_WR1END0_0", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_BUFG_IMUX3_0", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_BUFG_IMUX2_0", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_BUFG_IMUX46_0", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_BUFG_IMUX9_0", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_WW2A0_0", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4BEG2_0", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_CLK1_0", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_SW4A2_0", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_LH2_0", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_WW4A3_0", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_BUFG_IMUX14_0", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_NE2A0_0", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_EE4BEG1_0", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_SW2A2_0", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B3_0", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CLK_HROW_BYP4_0", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B0_0", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CLK_HROW_EE4B3_0", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_EE2BEG0_0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_SE4C2_0", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_BYP7_0", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_SW4END0_0", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_EE4A0_0", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_SE4C3_0", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_BUFG_IMUX25_0", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_SE4BEG1_0", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_BYP2_0", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_SW4A0_0", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_EE2BEG1_0", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_BYP6_0", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_BUFG_IMUX30_0", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B1_0", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CLK_HROW_FAN4_0", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_WL1END1_0", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_BUFG_IMUX39_0", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_WW2END3_0", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_EL1BEG3_0", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_EE2BEG3_0", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_WW4END3_0", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_BYP3_0", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_NE4BEG3_0", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_BUFG_IMUX17_0", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_EE2A0_0", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_SE4BEG0_0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_BUFG_IMUX31_0", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_WW4C2_0", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_BUFG_IMUX26_0", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_LH5_0", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_EL1BEG2_0", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_BUFG_IMUX1_0", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_NW2A3_0", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_NE4C1_0", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_EE4C1_0", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_BUFG_IMUX18_0", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_WW4END2_0", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_EE4BEG3_0", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_NE2A3_0", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_NW4END1_0", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_BUFG_IMUX12_0", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_SW4END1_0", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_WW2A1_0", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_SW4END2_0", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_EE4C3_0", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_BUFG_IMUX45_0", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_NW4END0_0", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_SW2A0_0", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_SW4A1_0", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_BUFG_IMUX33_0", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_WW2A2_0", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B4_0", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CLK_HROW_NE4C2_0", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_BUFG_IMUX43_0", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_NW4A1_0", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_BUFG_IMUX19_0", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_BUFG_IMUX21_0", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_WW4END0_0", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_WW4C0_0", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_BUFG_IMUX20_0", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_WW4A1_0", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_LH6_0", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_SW4END3_0", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_BUFG_IMUX32_0", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_SE4C0_0", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_BUFG_IMUX13_0", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_SE2A3_0", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_EE4A3_0", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_BUFG_IMUX24_0", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_EE4B0_0", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_WW2A3_0", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_BUFG_IMUX15_0", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_WW4A0_0", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_EE4A1_0", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_ER1BEG2_0", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_BUFG_IMUX28_0", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_BUFG_IMUX7_0", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_WW4C1_0", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_WL1END3_0", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_BUFG_IMUX23_0", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_LH11_0", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_LH12_0", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_EE4BEG0_0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_NW4A0_0", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_BUFG_IMUX6_0", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_WW4B1_0", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_WL1END2_0", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_BUFG_IMUX47_0", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_EL1BEG0_0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_EE2A3_0", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_LH3_0", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_NE4BEG1_0", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_SE4C1_0", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_BUFG_IMUX42_0", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_BYP1_0", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_WW2END0_0", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_BUFG_IMUX27_0", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_NE4BEG2_0", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_NE4C3_0", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_SW2A1_0", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_BUFG_IMUX11_0", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B2_0", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CLK_BUFG_IMUX8_0", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_WL1END0_0", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_NW4END3_0", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_CTRL0_0", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_CTRL1_0", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_WR1END2_0", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_BUFG_IMUX4_0", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_WW4C3_0", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_EE2A2_0", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_LH9_0", + "INT_INTERFACE_LH9" + ], + [ + "CLK_BUFG_IMUX36_0", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_EL1BEG1_0", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_BUFG_IMUX41_0", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_BYP0_0", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_WR1END1_0", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_ER1BEG0_0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_FAN6_0", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_WW4END1_0", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_NE2A1_0", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_NW2A0_0", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_WW2END1_0", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_LH4_0", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_ER1BEG1_0", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_SE4BEG3_0", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_FAN7_0", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_FAN0_0", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_NE4C0_0", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_EE2A1_0", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_WW4B2_0", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_LH1_0", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_WW2END2_0", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_WW4B3_0", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_FAN2_0", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_BUFG_IMUX0_0", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_SE2A2_0", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_LH10_0", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_NW2A1_0", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_NE2A2_0", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B7_0", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CLK_HROW_EE4B2_0", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_FAN5_0", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_NE4BEG0_0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_BUFG_IMUX22_0", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_SW2A3_0", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_SE2A0_0", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_SW4A3_0", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_NW4A2_0", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_EE4B1_0", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_LH7_0", + "INT_INTERFACE_LH7" + ], + [ + "CLK_BUFG_IMUX44_0", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B5_0", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CLK_BUFG_IMUX35_0", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_BUFG_IMUX37_0", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_NW4A3_0", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WR1END3_0", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_CLK0_0", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_NW4END2_0", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_WW4B0_0", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_LH8_0", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_SE2A1_0", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_BUFG_IMUX16_0", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_EE4C2_0", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_BUFG_IMUX34_0", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_BUFG_IMUX40_0", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_BUFG_IMUX29_0", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B6_0", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CLK_HROW_EE4C0_0", + "INT_INTERFACE_EE4C0" + ] + ], + "tile_types": [ + "CLK_BUFG_TOP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "DSP_EE2BEG0_4", + "INT_INTERFACE_EE2BEG0" + ], + [ + "DSP_BYP0_4", + "INT_INTERFACE_BYP0" + ], + [ + "DSP_FAN2_4", + "INT_INTERFACE_FAN2" + ], + [ + "DSP_NW4END2_4", + "INT_INTERFACE_NW4END2" + ], + [ + "DSP_LOGIC_OUTS_B20_4", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "DSP_ER1BEG3_4", + "INT_INTERFACE_ER1BEG3" + ], + [ + "DSP_WW4B3_4", + "INT_INTERFACE_WW4B3" + ], + [ + "DSP_SE4C3_4", + "INT_INTERFACE_SE4C3" + ], + [ + "DSP_EL1BEG2_4", + "INT_INTERFACE_EL1BEG2" + ], + [ + "DSP_IMUX23_4", + "INT_INTERFACE_IMUX23" + ], + [ + "DSP_IMUX41_4", + "INT_INTERFACE_IMUX41" + ], + [ + "DSP_BYP3_4", + "INT_INTERFACE_BYP3" + ], + [ + "DSP_NE2A3_4", + "INT_INTERFACE_NE2A3" + ], + [ + "DSP_IMUX31_4", + "INT_INTERFACE_IMUX31" + ], + [ + "DSP_EE4C3_4", + "INT_INTERFACE_EE4C3" + ], + [ + "DSP_IMUX7_4", + "INT_INTERFACE_IMUX7" + ], + [ + "DSP_WW2END3_4", + "INT_INTERFACE_WW2END3" + ], + [ + "DSP_IMUX4_4", + "INT_INTERFACE_IMUX4" + ], + [ + "DSP_SE2A1_4", + "INT_INTERFACE_SE2A1" + ], + [ + "DSP_WW4B0_4", + "INT_INTERFACE_WW4B0" + ], + [ + "DSP_WL1END1_4", + "INT_INTERFACE_WL1END1" + ], + [ + "DSP_LOGIC_OUTS_B22_4", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "DSP_NW4A1_4", + "INT_INTERFACE_NW4A1" + ], + [ + "DSP_LH9_4", + "INT_INTERFACE_LH9" + ], + [ + "DSP_IMUX42_4", + "INT_INTERFACE_IMUX42" + ], + [ + "DSP_LH2_4", + "INT_INTERFACE_LH2" + ], + [ + "DSP_EE4B1_4", + "INT_INTERFACE_EE4B1" + ], + [ + "DSP_EE4BEG3_4", + "INT_INTERFACE_EE4BEG3" + ], + [ + "DSP_LOGIC_OUTS_B4_4", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "DSP_LH8_4", + "INT_INTERFACE_LH8" + ], + [ + "DSP_EE4C1_4", + "INT_INTERFACE_EE4C1" + ], + [ + "DSP_WW4A3_4", + "INT_INTERFACE_WW4A3" + ], + [ + "DSP_WL1END3_4", + "INT_INTERFACE_WL1END3" + ], + [ + "DSP_LOGIC_OUTS_B11_4", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "DSP_FAN5_4", + "INT_INTERFACE_FAN5" + ], + [ + "DSP_IMUX5_4", + "INT_INTERFACE_IMUX5" + ], + [ + "DSP_FAN3_4", + "INT_INTERFACE_FAN3" + ], + [ + "DSP_IMUX35_4", + "INT_INTERFACE_IMUX35" + ], + [ + "DSP_SW4END2_4", + "INT_INTERFACE_SW4END2" + ], + [ + "DSP_IMUX44_4", + "INT_INTERFACE_IMUX44" + ], + [ + "DSP_SW2A2_4", + "INT_INTERFACE_SW2A2" + ], + [ + "DSP_EE2A2_4", + "INT_INTERFACE_EE2A2" + ], + [ + "DSP_LOGIC_OUTS_B5_4", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "DSP_SW4A3_4", + "INT_INTERFACE_SW4A3" + ], + [ + "DSP_WW4A0_4", + "INT_INTERFACE_WW4A0" + ], + [ + "DSP_IMUX6_4", + "INT_INTERFACE_IMUX6" + ], + [ + "DSP_IMUX22_4", + "INT_INTERFACE_IMUX22" + ], + [ + "DSP_IMUX33_4", + "INT_INTERFACE_IMUX33" + ], + [ + "DSP_ER1BEG2_4", + "INT_INTERFACE_ER1BEG2" + ], + [ + "DSP_IMUX36_4", + "INT_INTERFACE_IMUX36" + ], + [ + "DSP_EE2A0_4", + "INT_INTERFACE_EE2A0" + ], + [ + "DSP_SW4A2_4", + "INT_INTERFACE_SW4A2" + ], + [ + "DSP_EE4BEG2_4", + "INT_INTERFACE_EE4BEG2" + ], + [ + "DSP_NW4A2_4", + "INT_INTERFACE_NW4A2" + ], + [ + "DSP_FAN7_4", + "INT_INTERFACE_FAN7" + ], + [ + "DSP_LOGIC_OUTS_B18_4", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "DSP_LOGIC_OUTS_B8_4", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "DSP_LOGIC_OUTS_B21_4", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "DSP_LH7_4", + "INT_INTERFACE_LH7" + ], + [ + "DSP_IMUX29_4", + "INT_INTERFACE_IMUX29" + ], + [ + "DSP_LOGIC_OUTS_B6_4", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "DSP_WW2A3_4", + "INT_INTERFACE_WW2A3" + ], + [ + "DSP_LOGIC_OUTS_B1_4", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "DSP_EE4B0_4", + "INT_INTERFACE_EE4B0" + ], + [ + "DSP_NE4BEG2_4", + "INT_INTERFACE_NE4BEG2" + ], + [ + "DSP_EE4A0_4", + "INT_INTERFACE_EE4A0" + ], + [ + "DSP_IMUX12_4", + "INT_INTERFACE_IMUX12" + ], + [ + "DSP_EE4A3_4", + "INT_INTERFACE_EE4A3" + ], + [ + "DSP_EE2BEG1_4", + "INT_INTERFACE_EE2BEG1" + ], + [ + "DSP_MONITOR_N_4", + "INT_INTERFACE_MONITOR_N" + ], + [ + "DSP_CLK1_4", + "INT_INTERFACE_CLK1" + ], + [ + "DSP_IMUX40_4", + "INT_INTERFACE_IMUX40" + ], + [ + "DSP_NW2A2_4", + "INT_INTERFACE_NW2A2" + ], + [ + "DSP_LOGIC_OUTS_B19_4", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "DSP_NE4C1_4", + "INT_INTERFACE_NE4C1" + ], + [ + "DSP_LOGIC_OUTS_B17_4", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "DSP_IMUX43_4", + "INT_INTERFACE_IMUX43" + ], + [ + "DSP_IMUX9_4", + "INT_INTERFACE_IMUX9" + ], + [ + "DSP_SE2A3_4", + "INT_INTERFACE_SE2A3" + ], + [ + "DSP_NE4BEG1_4", + "INT_INTERFACE_NE4BEG1" + ], + [ + "DSP_IMUX2_4", + "INT_INTERFACE_IMUX2" + ], + [ + "DSP_IMUX21_4", + "INT_INTERFACE_IMUX21" + ], + [ + "DSP_LOGIC_OUTS_B13_4", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "DSP_LH4_4", + "INT_INTERFACE_LH4" + ], + [ + "DSP_LOGIC_OUTS_B2_4", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "DSP_CTRL0_4", + "INT_INTERFACE_CTRL0" + ], + [ + "DSP_WW4C2_4", + "INT_INTERFACE_WW4C2" + ], + [ + "DSP_WW4END3_4", + "INT_INTERFACE_WW4END3" + ], + [ + "DSP_SE4BEG2_4", + "INT_INTERFACE_SE4BEG2" + ], + [ + "DSP_EE2BEG2_4", + "INT_INTERFACE_EE2BEG2" + ], + [ + "DSP_IMUX11_4", + "INT_INTERFACE_IMUX11" + ], + [ + "DSP_IMUX25_4", + "INT_INTERFACE_IMUX25" + ], + [ + "DSP_WW2END1_4", + "INT_INTERFACE_WW2END1" + ], + [ + "DSP_WW4END2_4", + "INT_INTERFACE_WW4END2" + ], + [ + "DSP_LOGIC_OUTS_B14_4", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "DSP_EE4BEG1_4", + "INT_INTERFACE_EE4BEG1" + ], + [ + "DSP_FAN6_4", + "INT_INTERFACE_FAN6" + ], + [ + "DSP_NE2A2_4", + "INT_INTERFACE_NE2A2" + ], + [ + "DSP_IMUX34_4", + "INT_INTERFACE_IMUX34" + ], + [ + "DSP_LH1_4", + "INT_INTERFACE_LH1" + ], + [ + "DSP_WL1END0_4", + "INT_INTERFACE_WL1END0" + ], + [ + "DSP_SE4C1_4", + "INT_INTERFACE_SE4C1" + ], + [ + "DSP_IMUX19_4", + "INT_INTERFACE_IMUX19" + ], + [ + "DSP_NE2A0_4", + "INT_INTERFACE_NE2A0" + ], + [ + "DSP_BYP2_4", + "INT_INTERFACE_BYP2" + ], + [ + "DSP_SW4END0_4", + "INT_INTERFACE_SW4END0" + ], + [ + "DSP_SW4END1_4", + "INT_INTERFACE_SW4END1" + ], + [ + "DSP_NE4C3_4", + "INT_INTERFACE_NE4C3" + ], + [ + "DSP_IMUX37_4", + "INT_INTERFACE_IMUX37" + ], + [ + "DSP_WW2END0_4", + "INT_INTERFACE_WW2END0" + ], + [ + "DSP_WW2A0_4", + "INT_INTERFACE_WW2A0" + ], + [ + "DSP_SW4A0_4", + "INT_INTERFACE_SW4A0" + ], + [ + "DSP_IMUX3_4", + "INT_INTERFACE_IMUX3" + ], + [ + "DSP_IMUX39_4", + "INT_INTERFACE_IMUX39" + ], + [ + "DSP_CTRL1_4", + "INT_INTERFACE_CTRL1" + ], + [ + "DSP_NW2A1_4", + "INT_INTERFACE_NW2A1" + ], + [ + "DSP_IMUX24_4", + "INT_INTERFACE_IMUX24" + ], + [ + "DSP_BYP5_4", + "INT_INTERFACE_BYP5" + ], + [ + "DSP_EL1BEG3_4", + "INT_INTERFACE_EL1BEG3" + ], + [ + "DSP_WW4C0_4", + "INT_INTERFACE_WW4C0" + ], + [ + "DSP_IMUX14_4", + "INT_INTERFACE_IMUX14" + ], + [ + "DSP_WW2END2_4", + "INT_INTERFACE_WW2END2" + ], + [ + "DSP_IMUX18_4", + "INT_INTERFACE_IMUX18" + ], + [ + "DSP_NE2A1_4", + "INT_INTERFACE_NE2A1" + ], + [ + "DSP_WW4A1_4", + "INT_INTERFACE_WW4A1" + ], + [ + "DSP_FAN4_4", + "INT_INTERFACE_FAN4" + ], + [ + "DSP_IMUX32_4", + "INT_INTERFACE_IMUX32" + ], + [ + "DSP_LOGIC_OUTS_B10_4", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "DSP_NW4A0_4", + "INT_INTERFACE_NW4A0" + ], + [ + "DSP_FAN1_4", + "INT_INTERFACE_FAN1" + ], + [ + "DSP_NW4END1_4", + "INT_INTERFACE_NW4END1" + ], + [ + "DSP_IMUX28_4", + "INT_INTERFACE_IMUX28" + ], + [ + "DSP_SE4C2_4", + "INT_INTERFACE_SE4C2" + ], + [ + "DSP_WR1END3_4", + "INT_INTERFACE_WR1END3" + ], + [ + "DSP_LH12_4", + "INT_INTERFACE_LH12" + ], + [ + "DSP_SE2A2_4", + "INT_INTERFACE_SE2A2" + ], + [ + "DSP_EE2A1_4", + "INT_INTERFACE_EE2A1" + ], + [ + "DSP_WR1END2_4", + "INT_INTERFACE_WR1END2" + ], + [ + "DSP_MONITOR_P_4", + "INT_INTERFACE_MONITOR_P" + ], + [ + "DSP_IMUX13_4", + "INT_INTERFACE_IMUX13" + ], + [ + "DSP_LH5_4", + "INT_INTERFACE_LH5" + ], + [ + "DSP_LH3_4", + "INT_INTERFACE_LH3" + ], + [ + "DSP_IMUX30_4", + "INT_INTERFACE_IMUX30" + ], + [ + "DSP_EE4C2_4", + "INT_INTERFACE_EE4C2" + ], + [ + "DSP_WW4C1_4", + "INT_INTERFACE_WW4C1" + ], + [ + "DSP_LH11_4", + "INT_INTERFACE_LH11" + ], + [ + "DSP_LH10_4", + "INT_INTERFACE_LH10" + ], + [ + "DSP_ER1BEG1_4", + "INT_INTERFACE_ER1BEG1" + ], + [ + "DSP_BYP4_4", + "INT_INTERFACE_BYP4" + ], + [ + "DSP_SE4BEG3_4", + "INT_INTERFACE_SE4BEG3" + ], + [ + "DSP_EL1BEG1_4", + "INT_INTERFACE_EL1BEG1" + ], + [ + "DSP_SW2A0_4", + "INT_INTERFACE_SW2A0" + ], + [ + "DSP_IMUX8_4", + "INT_INTERFACE_IMUX8" + ], + [ + "DSP_LOGIC_OUTS_B0_4", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "DSP_LOGIC_OUTS_B7_4", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "DSP_SE4C0_4", + "INT_INTERFACE_SE4C0" + ], + [ + "DSP_IMUX20_4", + "INT_INTERFACE_IMUX20" + ], + [ + "DSP_NW4END3_4", + "INT_INTERFACE_NW4END3" + ], + [ + "DSP_EE4A1_4", + "INT_INTERFACE_EE4A1" + ], + [ + "DSP_IMUX15_4", + "INT_INTERFACE_IMUX15" + ], + [ + "DSP_WW2A2_4", + "INT_INTERFACE_WW2A2" + ], + [ + "DSP_CLK0_4", + "INT_INTERFACE_CLK0" + ], + [ + "DSP_SW2A1_4", + "INT_INTERFACE_SW2A1" + ], + [ + "DSP_ER1BEG0_4", + "INT_INTERFACE_ER1BEG0" + ], + [ + "DSP_EE4B3_4", + "INT_INTERFACE_EE4B3" + ], + [ + "DSP_WW4C3_4", + "INT_INTERFACE_WW4C3" + ], + [ + "DSP_FAN0_4", + "INT_INTERFACE_FAN0" + ], + [ + "DSP_SE2A0_4", + "INT_INTERFACE_SE2A0" + ], + [ + "DSP_IMUX26_4", + "INT_INTERFACE_IMUX26" + ], + [ + "DSP_IMUX0_4", + "INT_INTERFACE_IMUX0" + ], + [ + "DSP_NE4C2_4", + "INT_INTERFACE_NE4C2" + ], + [ + "DSP_NE4C0_4", + "INT_INTERFACE_NE4C0" + ], + [ + "DSP_NE4BEG3_4", + "INT_INTERFACE_NE4BEG3" + ], + [ + "DSP_EE4A2_4", + "INT_INTERFACE_EE4A2" + ], + [ + "DSP_NW2A0_4", + "INT_INTERFACE_NW2A0" + ], + [ + "DSP_IMUX17_4", + "INT_INTERFACE_IMUX17" + ], + [ + "DSP_LOGIC_OUTS_B3_4", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "DSP_NW2A3_4", + "INT_INTERFACE_NW2A3" + ], + [ + "DSP_EE4C0_4", + "INT_INTERFACE_EE4C0" + ], + [ + "DSP_SE4BEG1_4", + "INT_INTERFACE_SE4BEG1" + ], + [ + "DSP_BYP6_4", + "INT_INTERFACE_BYP6" + ], + [ + "DSP_BYP7_4", + "INT_INTERFACE_BYP7" + ], + [ + "DSP_LOGIC_OUTS_B15_4", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "DSP_EE2BEG3_4", + "INT_INTERFACE_EE2BEG3" + ], + [ + "DSP_LOGIC_OUTS_B9_4", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "DSP_SE4BEG0_4", + "INT_INTERFACE_SE4BEG0" + ], + [ + "DSP_WR1END0_4", + "INT_INTERFACE_WR1END0" + ], + [ + "DSP_EL1BEG0_4", + "INT_INTERFACE_EL1BEG0" + ], + [ + "DSP_IMUX46_4", + "INT_INTERFACE_IMUX46" + ], + [ + "DSP_NW4END0_4", + "INT_INTERFACE_NW4END0" + ], + [ + "DSP_IMUX1_4", + "INT_INTERFACE_IMUX1" + ], + [ + "DSP_SW4END3_4", + "INT_INTERFACE_SW4END3" + ], + [ + "DSP_BYP1_4", + "INT_INTERFACE_BYP1" + ], + [ + "DSP_EE4BEG0_4", + "INT_INTERFACE_EE4BEG0" + ], + [ + "DSP_IMUX38_4", + "INT_INTERFACE_IMUX38" + ], + [ + "DSP_LOGIC_OUTS_B16_4", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "DSP_IMUX10_4", + "INT_INTERFACE_IMUX10" + ], + [ + "DSP_SW4A1_4", + "INT_INTERFACE_SW4A1" + ], + [ + "DSP_WW4B2_4", + "INT_INTERFACE_WW4B2" + ], + [ + "DSP_IMUX45_4", + "INT_INTERFACE_IMUX45" + ], + [ + "DSP_WW2A1_4", + "INT_INTERFACE_WW2A1" + ], + [ + "DSP_WW4END1_4", + "INT_INTERFACE_WW4END1" + ], + [ + "DSP_EE4B2_4", + "INT_INTERFACE_EE4B2" + ], + [ + "DSP_WL1END2_4", + "INT_INTERFACE_WL1END2" + ], + [ + "DSP_LH6_4", + "INT_INTERFACE_LH6" + ], + [ + "DSP_WW4B1_4", + "INT_INTERFACE_WW4B1" + ], + [ + "DSP_NW4A3_4", + "INT_INTERFACE_NW4A3" + ], + [ + "DSP_EE2A3_4", + "INT_INTERFACE_EE2A3" + ], + [ + "DSP_WW4A2_4", + "INT_INTERFACE_WW4A2" + ], + [ + "DSP_WR1END1_4", + "INT_INTERFACE_WR1END1" + ], + [ + "DSP_WW4END0_4", + "INT_INTERFACE_WW4END0" + ], + [ + "DSP_NE4BEG0_4", + "INT_INTERFACE_NE4BEG0" + ], + [ + "DSP_SW2A3_4", + "INT_INTERFACE_SW2A3" + ], + [ + "DSP_LOGIC_OUTS_B12_4", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "DSP_IMUX47_4", + "INT_INTERFACE_IMUX47" + ], + [ + "DSP_IMUX27_4", + "INT_INTERFACE_IMUX27" + ], + [ + "DSP_LOGIC_OUTS_B23_4", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "DSP_IMUX16_4", + "INT_INTERFACE_IMUX16" + ] + ], + "tile_types": [ + "DSP_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFRCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN6", + "HCLK_VFRAME_CK_IN6" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN12", + "HCLK_VFRAME_CK_IN12" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN4", + "HCLK_VFRAME_CK_IN4" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK7" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN3", + "HCLK_VFRAME_CK_IN3" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN0", + "HCLK_VFRAME_CK_IN0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK2", + "HCLK_VFRAME_CK_BUFHCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN2", + "HCLK_VFRAME_CK_IN2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFRCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN10", + "HCLK_VFRAME_CK_IN10" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK11", + "HCLK_VFRAME_CK_BUFHCLK11" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK0", + "HCLK_VFRAME_CK_BUFHCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK6", + "HCLK_VFRAME_CK_BUFHCLK6" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK2", + "HCLK_VFRAME_CK_BUFRCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN9", + "HCLK_VFRAME_CK_IN9" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK1", + "HCLK_VFRAME_CK_BUFHCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN13", + "HCLK_VFRAME_CK_IN13" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK3", + "HCLK_VFRAME_CK_BUFHCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK9" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK4", + "HCLK_VFRAME_CK_BUFHCLK4" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN11", + "HCLK_VFRAME_CK_IN11" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN8", + "HCLK_VFRAME_CK_IN8" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK8", + "HCLK_VFRAME_CK_BUFHCLK8" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN7", + "HCLK_VFRAME_CK_IN7" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK5" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN5", + "HCLK_VFRAME_CK_IN5" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN1", + "HCLK_VFRAME_CK_IN1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK10" + ] + ], + "tile_types": [ + "HCLK_FEEDTHRU_1", + "HCLK_VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "CLK_HROW_EE4A1_5", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_WW2A1_5", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_IMUX17_5", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_NE2A2_5", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_SW4END3_5", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_EE2BEG1_5", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_WW4END3_5", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_IMUX26_5", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_EE4B3_5", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_IMUX19_5", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_NE2A0_5", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_SE2A2_5", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_NE4BEG0_5", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_EE4C0_5", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_WW2A3_5", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_BYP4_5", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_CTRL1_5", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_BYP1_5", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_IMUX44_5", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_SE2A0_5", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_IMUX11_5", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_NW4END3_5", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_FAN0_5", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_FAN7_5", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_IMUX1_5", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_ER1BEG2_5", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_IMUX20_5", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_WW2A2_5", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_WW2END2_5", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_WW4A1_5", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_WW2END1_5", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_SE4C0_5", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_EE4B2_5", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_NW2A1_5", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_SW4END1_5", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_IMUX6_5", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_SW4END2_5", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_IMUX45_5", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_IMUX9_5", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_IMUX3_5", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_EE2A0_5", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_BYP0_5", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_NW2A0_5", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_BYP2_5", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_NE4BEG3_5", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_WW4C1_5", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_FAN6_5", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_WW4A2_5", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_NW4A2_5", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_SW2A3_5", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_EE4C1_5", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_SW2A1_5", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_EL1BEG3_5", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_IMUX23_5", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_IMUX18_5", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_WL1END0_5", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_NE2A3_5", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_IMUX7_5", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_EE4B0_5", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_ER1BEG1_5", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_ER1BEG3_5", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_IMUX34_5", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_WW4A0_5", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_EL1BEG1_5", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_NE4C2_5", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_CTRL0_5", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_NW4A3_5", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WW4C2_5", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_IMUX24_5", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_WR1END0_5", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_IMUX28_5", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_SW4A3_5", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_NE4C0_5", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_EE2BEG3_5", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_EE4A0_5", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_NW4END1_5", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_SW4A1_5", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_IMUX46_5", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_LH1_5", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_LH12_5", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_IMUX32_5", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_SE4BEG0_5", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_LH6_5", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_BYP5_5", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_SW4A2_5", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_SW4A0_5", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_EE2A3_5", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_LH10_5", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_SE2A3_5", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_EE4C2_5", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_IMUX22_5", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_SE4C3_5", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_IMUX13_5", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_EE4BEG2_5", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_NE4C1_5", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_WW4END0_5", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_IMUX4_5", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_WW4END2_5", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_NW4END2_5", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_FAN3_5", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_WW4C3_5", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_SW4END0_5", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_WL1END2_5", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_SE4C2_5", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_NE2A1_5", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_CLK0_5", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_LH9_5", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_IMUX15_5", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_EE4BEG3_5", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_WR1END2_5", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_LH5_5", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_NW4END0_5", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_IMUX37_5", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_IMUX8_5", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_EE2BEG0_5", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_IMUX31_5", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_LH11_5", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_WR1END3_5", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_IMUX25_5", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_IMUX42_5", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_EE4B1_5", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_WW4B3_5", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_LH2_5", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_SE4BEG1_5", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_NW4A1_5", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_EE4A2_5", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_LH8_5", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_IMUX0_5", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_IMUX21_5", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_IMUX5_5", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_FAN1_5", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_IMUX43_5", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_WW4B1_5", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_IMUX38_5", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_FAN4_5", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_IMUX14_5", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_LH4_5", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_EL1BEG2_5", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_LH3_5", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_IMUX35_5", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_SE4C1_5", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_IMUX47_5", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_IMUX16_5", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_FAN5_5", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_WR1END1_5", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_WW4END1_5", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_IMUX27_5", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_BYP7_5", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_SE4BEG2_5", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_LH7_5", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_WW2END3_5", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_NW4A0_5", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_WW2END0_5", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_EE4A3_5", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_IMUX29_5", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_IMUX39_5", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_EL1BEG0_5", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_SE4BEG3_5", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_NW2A3_5", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_EE4BEG1_5", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_NE4BEG2_5", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_WL1END1_5", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_IMUX12_5", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_EE2A2_5", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_WL1END3_5", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_IMUX2_5", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_NE4BEG1_5", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_IMUX41_5", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_IMUX40_5", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_WW4A3_5", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_CLK1_5", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_IMUX36_5", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_EE4BEG0_5", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_EE4C3_5", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_IMUX10_5", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_WW2A0_5", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE2BEG2_5", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_SE2A1_5", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_FAN2_5", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_BYP3_5", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_WW4B0_5", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_NW2A2_5", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_IMUX30_5", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_SW2A2_5", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_ER1BEG0_5", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_EE2A1_5", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_NE4C3_5", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_IMUX33_5", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_SW2A0_5", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_BYP6_5", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_WW4C0_5", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_WW4B2_5", + "INT_INTERFACE_WW4B2" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "CLK_PMV_LH5_3", + "VBRK_LH5" + ], + [ + "CLK_PMV_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "CLK_PMV_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "CLK_PMV_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "CLK_PMV_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "CLK_PMV_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "CLK_PMV_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "CLK_PMV_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "CLK_PMV_LH8_3", + "VBRK_LH8" + ], + [ + "CLK_PMV_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "CLK_PMV_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "CLK_PMV_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "CLK_PMV_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "CLK_PMV_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "CLK_PMV_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "CLK_PMV_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "CLK_PMV_LH7_3", + "VBRK_LH7" + ], + [ + "CLK_PMV_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "CLK_PMV_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "CLK_PMV_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "CLK_PMV_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "CLK_PMV_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "CLK_PMV_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "CLK_PMV_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "CLK_PMV_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "CLK_PMV_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "CLK_PMV_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "CLK_PMV_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "CLK_PMV_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "CLK_PMV_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "CLK_PMV_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "CLK_PMV_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "CLK_PMV_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "CLK_PMV_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "CLK_PMV_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "CLK_PMV_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "CLK_PMV_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "CLK_PMV_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "CLK_PMV_LH11_3", + "VBRK_LH11" + ], + [ + "CLK_PMV_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "CLK_PMV_LH10_3", + "VBRK_LH10" + ], + [ + "CLK_PMV_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "CLK_PMV_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "CLK_PMV_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "CLK_PMV_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "CLK_PMV_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "CLK_PMV_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "CLK_PMV_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "CLK_PMV_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "CLK_PMV_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "CLK_PMV_LH12_3", + "VBRK_LH12" + ], + [ + "CLK_PMV_EL1BEG1_3", + "VBRK_EL1BEG1" + ], + [ + "CLK_PMV_LH3_3", + "VBRK_LH3" + ], + [ + "CLK_PMV_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "CLK_PMV_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "CLK_PMV_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "CLK_PMV_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "CLK_PMV_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "CLK_PMV_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "CLK_PMV_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "CLK_PMV_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "CLK_PMV_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "CLK_PMV_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "CLK_PMV_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "CLK_PMV_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "CLK_PMV_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "CLK_PMV_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "CLK_PMV_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "CLK_PMV_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "CLK_PMV_LH9_3", + "VBRK_LH9" + ], + [ + "CLK_PMV_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "CLK_PMV_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "CLK_PMV_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "CLK_PMV_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "CLK_PMV_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "CLK_PMV_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "CLK_PMV_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "CLK_PMV_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "CLK_PMV_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "CLK_PMV_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "CLK_PMV_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "CLK_PMV_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "CLK_PMV_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "CLK_PMV_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "CLK_PMV_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "CLK_PMV_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "CLK_PMV_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "CLK_PMV_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "CLK_PMV_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "CLK_PMV_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "CLK_PMV_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "CLK_PMV_LH6_3", + "VBRK_LH6" + ], + [ + "CLK_PMV_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "CLK_PMV_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "CLK_PMV_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "CLK_PMV_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "CLK_PMV_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "CLK_PMV_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "CLK_PMV_LH1_3", + "VBRK_LH1" + ], + [ + "CLK_PMV_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "CLK_PMV_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "CLK_PMV_LH4_3", + "VBRK_LH4" + ], + [ + "CLK_PMV_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "CLK_PMV_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "CLK_PMV_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "CLK_PMV_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "CLK_PMV_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "CLK_PMV_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "CLK_PMV_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "CLK_PMV_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "CLK_PMV_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "CLK_PMV_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "CLK_PMV_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "CLK_PMV_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "CLK_PMV_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "CLK_PMV_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "CLK_PMV_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "CLK_PMV_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "CLK_PMV_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "CLK_PMV_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "CLK_PMV_LH2_3", + "VBRK_LH2" + ], + [ + "CLK_PMV_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "CLK_PMV_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "CLK_PMV_SE4C0_3", + "VBRK_SE4C0" + ] + ], + "tile_types": [ + "CLK_PMV", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_0" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_0" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_0" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_0" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_0" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_0" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_0" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_0" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_0" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_0" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_0" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_0" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_0" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_0" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_0" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_0" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_0" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_0" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_0" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_0" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_0" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_0" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_0" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_0" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_0" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_0" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_0" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_0" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_0" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_0" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_0" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_0" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_0" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_0" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_0" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_0" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_0" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_0" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_0" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_0" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_0" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_0" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_0" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_0" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_0" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_0" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_0" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_0" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_0" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_0" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_0" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_0" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_0" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_0" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_0" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_0" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_0" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_0" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_0" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_0" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_0" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_0" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_0" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_0" + ], + [ + "INT_FEEDTHRU_2_MONITOR_N", + "MONITOR_HORIZ_VAUXN10" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_0" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_0" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_0" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_0" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_0" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_0" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_0" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_0" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_0" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_0" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_0" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_0" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_0" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_0" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_0" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_0" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_0" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_0" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_0" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_0" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_0" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_0" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_0" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_0" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_0" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_0" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_0" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_0" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_0" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_0" + ], + [ + "INT_FEEDTHRU_2_MONITOR_P", + "MONITOR_HORIZ_VAUXP10" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_0" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_0" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_0" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_0" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_0" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_0" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_0" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_0" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_0" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_0" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_0" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_0" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_0" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_0" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_0" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_0" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_0" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_0" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_0" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_0" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_0" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_0" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_0" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_0" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_0" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_0" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_0" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_0" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_0" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_0" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_MID_FUJI2" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B11_6", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_LOGIC_OUTS_B2_6", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX5_6", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_CLK1_6", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX6_6", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX3_6", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_LOGIC_OUTS_B20_6", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX22_6", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B0_6", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX21_6", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_CLK0_6", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_LOGIC_OUTS_B14_6", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX24_6", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX39_6", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B9_6", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_LOGIC_OUTS_B5_6", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX46_6", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP3_6", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_FAN1_6", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B3_6", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX30_6", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_FAN4_6", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_LOGIC_OUTS_B10_6", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX42_6", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_LOGIC_OUTS_B6_6", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX28_6", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX45_6", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX8_6", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX10_6", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B16_6", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX36_6", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX44_6", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX33_6", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_BYP7_6", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX15_6", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX41_6", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX25_6", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_CTRL1_6", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_6", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX12_6", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B22_6", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX19_6", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX40_6", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_BYP6_6", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX32_6", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN0_6", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX27_6", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX37_6", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX0_6", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX35_6", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_BYP2_6", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_BYP0_6", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX31_6", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX13_6", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_FAN2_6", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX2_6", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_LOGIC_OUTS_B12_6", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_CTRL0_6", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_BYP5_6", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B17_6", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX9_6", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX29_6", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX16_6", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_LOGIC_OUTS_B1_6", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_FAN5_6", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX18_6", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX43_6", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX4_6", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_LOGIC_OUTS_B8_6", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_LOGIC_OUTS_B15_6", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_LOGIC_OUTS_B13_6", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_IMUX38_6", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX7_6", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_BYP1_6", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B23_6", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX23_6", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_FAN7_6", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B7_6", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B4_6", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_IMUX26_6", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX20_6", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN3_6", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX34_6", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX47_6", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_BYP4_6", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX11_6", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_FAN6_6", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX14_6", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX1_6", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX17_6", + "VBRK_EXT_IMUX17" + ] + ], + "tile_types": [ + "GTX_CHANNEL_3", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 5, + 3 + ], + "wire_pairs": [ + [ + "PCIE_LH4_7", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_EE4C1_7", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_MONITOR_N_7", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_IMUX21_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_EE2A2_7", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_IMUX37_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_SE2A3_7", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_EE2BEG2_7", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_WL1END2_7", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_SW4A3_7", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_SW4END0_7", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_WL1END3_7", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_FAN0_L_7", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_IMUX2_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_NW4END3_7", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_SW4END2_7", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_WW2END3_7", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_EE4C0_7", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX34_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_ER1BEG3_7", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_IMUX4_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_EE4B0_7", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_WW4END0_7", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_WW4A0_7", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_CTRL0_L_7", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_FAN7_L_7", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_IMUX29_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_WW4B0_7", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_IMUX45_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_WW4A2_7", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_SE4BEG0_7", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_NW4A2_7", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_WR1END1_7", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_IMUX3_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_NE4BEG2_7", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_IMUX23_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_BYP4_L_7", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_WW4B2_7", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_LH9_7", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_EE2A3_7", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_IMUX36_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_EE2A1_7", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_SE2A2_7", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_EE4C3_7", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_IMUX42_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_FAN3_L_7", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_WW4B1_7", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_EE4A3_7", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_NE4BEG1_7", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_SE4BEG2_7", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_CLK1_L_7", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_WW4C3_7", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_LH3_7", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_SE2A1_7", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_BYP7_L_7", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_SE4C1_7", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_NW4END1_7", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_WL1END1_7", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_IMUX27_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_NE2A3_7", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_SE2A0_7", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_ER1BEG2_7", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_WW2END1_7", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_SE4C0_7", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_CTRL1_L_7", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_EE4A1_7", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_WW2END0_7", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_EE2BEG3_7", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_NW2A0_7", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_BYP0_L_7", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_NE4BEG3_7", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_WW4A3_7", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_ER1BEG1_7", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_WW4C0_7", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_WR1END0_7", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_NW4END0_7", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_IMUX46_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_NW4A3_7", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_EE4BEG3_7", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_WW4END2_7", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_NE2A0_7", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_ER1BEG0_7", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_NW4A0_7", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WR1END2_7", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_SW4A1_7", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_NE4C1_7", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_SW2A3_7", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX18_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_LH7_7", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_SW4END1_7", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_EL1BEG3_7", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_EL1BEG0_7", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_MONITOR_P_7", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_EE4A2_7", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_EE4BEG2_7", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX47_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_IMUX35_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_LH6_7", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_WW2END2_7", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_IMUX13_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_WW4B3_7", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_NE2A1_7", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_LH10_7", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_WW2A3_7", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_IMUX22_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_IMUX44_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_NW4END2_7", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_BYP5_L_7", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_FAN1_L_7", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_IMUX12_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_EE4B3_7", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_IMUX38_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_SW2A2_7", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_EE4B2_7", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_SW2A0_7", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_SE4BEG1_7", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_WW4C2_7", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_IMUX43_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_IMUX14_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_SE4C2_7", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_IMUX32_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_FAN6_L_7", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_BYP3_L_7", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_EL1BEG2_7", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_WW4END3_7", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_NW2A1_7", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_EE2BEG1_7", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_WW4END1_7", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_BYP6_L_7", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_NW4A1_7", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_IMUX40_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_NE4BEG0_7", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_WL1END0_7", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_IMUX0_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_EE2A0_7", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_CLK0_L_7", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_IMUX31_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_SW4END3_7", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_IMUX15_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_LH11_7", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_IMUX16_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_WW2A0_7", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_LH1_7", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_NW2A3_7", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_IMUX7_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_IMUX30_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_IMUX1_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_SE4BEG3_7", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_LH12_7", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_WW2A2_7", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_IMUX41_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_EE2BEG0_7", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_BYP2_L_7", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_NE4C3_7", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_SW2A1_7", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_LH2_7", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_EE4C2_7", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_NW2A2_7", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_IMUX8_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_NE4C2_7", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_EE4BEG0_7", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_SE4C3_7", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_FAN2_L_7", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_IMUX20_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_WW2A1_7", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_NE2A2_7", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_NE4C0_7", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_WW4A1_7", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_IMUX17_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_IMUX24_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_WR1END3_7", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_IMUX19_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_IMUX10_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_FAN5_L_7", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_LH5_7", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_IMUX9_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_EE4A0_7", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_BYP1_L_7", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_IMUX11_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_IMUX33_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_IMUX5_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_LH8_7", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_IMUX26_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_FAN4_L_7", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_SW4A0_7", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_IMUX25_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_EE4B1_7", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_IMUX6_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_IMUX39_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_IMUX28_L_7", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_SW4A2_7", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_WW4C1_7", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_EE4BEG1_7", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_7", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_EL1BEG1_7", + "INT_INTERFACE_EL1BEG1" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 0, + -8 + ], + "wire_pairs": [ + [ + "MMCM_CLK_FREQBB_REBUFOUT0", + "HCLK_CMT_FREQ_REF_NS0" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM9", + "HCLK_CMT_MUX_CLK_MMCM9" + ], + [ + "CMT_PHASER_BOT_OBURSTPENDING0", + "HCLK_CMT_OBURSTPENDING0" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM1", + "HCLK_CMT_MUX_CLK_MMCM1" + ], + [ + "MMCM_CLK_FREQBB_REBUFOUT3", + "HCLK_CMT_FREQ_REF_NS3" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM3", + "HCLK_CMT_MUX_CLK_MMCM3" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM13", + "HCLK_CMT_MUX_CLK_MMCM13" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM6", + "HCLK_CMT_MUX_CLK_MMCM6" + ], + [ + "CMT_LR_LOWER_T_CLK_IN3_HCLK", + "HCLK_CMT_MUX_MMCM_CLKFBIN" + ], + [ + "CMT_PHASER_BOT_SYNC_BB", + "HCLK_CMT_PHY_SYNC_BB" + ], + [ + "CMT_PHASER_BOT_IRANKB0", + "HCLK_CMT_PHY_CONTROL_IRANKB0" + ], + [ + "CMT_PHASER_BOT_REFMUX_1", + "HCLK_CMT_FREQ_PHASER_REFMUX_1" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM10", + "HCLK_CMT_MUX_CLK_MMCM10" + ], + [ + "CMT_PHASER_BOT_IBURSTPENDING1", + "HCLK_CMT_IBURSTPENDING1" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM5", + "HCLK_CMT_MUX_CLK_MMCM5" + ], + [ + "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "HCLK_CMT_PHASEREF_ABOVE1" + ], + [ + "CMT_BOT_HCLKMUX_CLKINT_1", + "HCLK_CMT_MUX_CLKINT_1" + ], + [ + "CMT_PHASER_BOT_REFMUX_2", + "HCLK_CMT_FREQ_PHASER_REFMUX_2" + ], + [ + "CMT_PHASER_BOT_OBURSTPENDING1", + "HCLK_CMT_OBURSTPENDING1" + ], + [ + "CMT_LR_LOWER_T_CLK_PERF3", + "HCLK_CMT_MUX_MMCM_MUXED3" + ], + [ + "CMT_PHASER_IN_B_RCLK1", + "HCLK_CMT_PHASERIN_RCLK1" + ], + [ + "CMT_PHASER_BOT_IRANKA0", + "HCLK_CMT_PHY_CONTROL_IRANKA0" + ], + [ + "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "HCLK_CMT_PHASEREF_ABOVE0" + ], + [ + "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "HCLK_CMT_PHASEREF_BELOW0" + ], + [ + "CMT_PHASER_BOT_REFMUX_0", + "HCLK_CMT_FREQ_PHASER_REFMUX_0" + ], + [ + "MMCM_CLK_FREQBB_REBUFOUT2", + "HCLK_CMT_FREQ_REF_NS2" + ], + [ + "CMT_LR_LOWER_T_CLK_PERF2", + "HCLK_CMT_MUX_MMCM_MUXED2" + ], + [ + "MMCM_CLK_FREQBB_REBUFOUT1", + "HCLK_CMT_FREQ_REF_NS1" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM0", + "HCLK_CMT_MUX_CLK_MMCM0" + ], + [ + "CMT_LR_LOWER_T_CLK_PERF1", + "HCLK_CMT_MUX_MMCM_MUXED1" + ], + [ + "CMT_BOT_HCLKMUX_CLKINT_0", + "HCLK_CMT_MUX_CLKINT_0" + ], + [ + "CMT_PHASER_DOWN_PHASERREF0", + "HCLK_CMT_BUFMR_PHASEREF0" + ], + [ + "CMT_PHASER_DOWN_PHASERREF1", + "HCLK_CMT_BUFMR_PHASEREF1" + ], + [ + "CMT_PHASER_IN_A_RCLK0", + "HCLK_CMT_PHASERIN_RCLK0" + ], + [ + "CMT_LR_LOWER_T_CLK_PERF0", + "HCLK_CMT_MUX_MMCM_MUXED0" + ], + [ + "CMT_PHASER_BOT_ENCALIB0", + "HCLK_CMT_ECALIB0" + ], + [ + "CMT_LR_LOWER_T_CLK_IN1_HCLK", + "HCLK_CMT_MUX_MMCM_CLKIN1" + ], + [ + "CMT_PHASER_BOT_IBURSTPENDING0", + "HCLK_CMT_IBURSTPENDING0" + ], + [ + "CMT_PHASER_BOT_IRANKB1", + "HCLK_CMT_PHY_CONTROL_IRANKB1" + ], + [ + "CMT_LR_LOWER_T_CLK_IN2_HCLK", + "HCLK_CMT_MUX_MMCM_CLKIN2" + ], + [ + "CMT_PHASER_BOT_ENCALIB1", + "HCLK_CMT_ECALIB1" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM4", + "HCLK_CMT_MUX_CLK_MMCM4" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM7", + "HCLK_CMT_MUX_CLK_MMCM7" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM2", + "HCLK_CMT_MUX_CLK_MMCM2" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM12", + "HCLK_CMT_MUX_CLK_MMCM12" + ], + [ + "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "HCLK_CMT_PHASEREF_BELOW1" + ], + [ + "CMT_PHASER_BOT_IRANKA1", + "HCLK_CMT_PHY_CONTROL_IRANKA1" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM11", + "HCLK_CMT_MUX_CLK_MMCM11" + ], + [ + "CMT_LR_LOWER_T_CLK_MMCM8", + "HCLK_CMT_MUX_CLK_MMCM8" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_T", + "HCLK_CMT_L" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_GTX_CK_IN12", + "HCLK_TERM_GTX_CK_IN12" + ], + [ + "HCLK_GTX_CK_IN6", + "HCLK_TERM_GTX_CK_IN6" + ], + [ + "HCLK_GTX_CK_IN8", + "HCLK_TERM_GTX_CK_IN8" + ], + [ + "HCLK_GTX_CK_IN11", + "HCLK_TERM_GTX_CK_IN11" + ], + [ + "HCLK_GTX_CK_IN4", + "HCLK_TERM_GTX_CK_IN4" + ], + [ + "HCLK_GTX_CK_IN13", + "HCLK_TERM_GTX_CK_IN13" + ], + [ + "HCLK_GTX_CK_IN9", + "HCLK_TERM_GTX_CK_IN9" + ], + [ + "HCLK_GTX_CK_IN7", + "HCLK_TERM_GTX_CK_IN7" + ], + [ + "HCLK_GTX_CK_IN5", + "HCLK_TERM_GTX_CK_IN5" + ], + [ + "HCLK_GTX_CK_IN10", + "HCLK_TERM_GTX_CK_IN10" + ] + ], + "tile_types": [ + "HCLK_GTX", + "HCLK_TERM_GTX" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "MONITOR_NE2A0_1", + "VFRAME_NE2A0" + ], + [ + "MONITOR_EE4A0_1", + "VFRAME_EE4A0" + ], + [ + "MONITOR_ER1BEG3_1", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_BYP3_1", + "VFRAME_BYP3" + ], + [ + "MONITOR_IMUX7_1", + "VFRAME_IMUX7" + ], + [ + "MONITOR_NW4A0_1", + "VFRAME_NW4A0" + ], + [ + "MONITOR_WW4B0_1", + "VFRAME_WW4B0" + ], + [ + "MONITOR_IMUX4_1", + "VFRAME_IMUX4" + ], + [ + "MONITOR_FAN1_1", + "VFRAME_FAN1" + ], + [ + "MONITOR_EE2A1_1", + "VFRAME_EE2A1" + ], + [ + "MONITOR_IMUX31_1", + "VFRAME_IMUX31" + ], + [ + "MONITOR_WW4B1_1", + "VFRAME_WW4B1" + ], + [ + "MONITOR_EE4C3_1", + "VFRAME_EE4C3" + ], + [ + "MONITOR_WW4END1_1", + "VFRAME_WW4END1" + ], + [ + "MONITOR_NW4A2_1", + "VFRAME_NW4A2" + ], + [ + "MONITOR_SE4C0_1", + "VFRAME_SE4C0" + ], + [ + "MONITOR_NW2A3_1", + "VFRAME_NW2A3" + ], + [ + "MONITOR_SW4END1_1", + "VFRAME_SW4END1" + ], + [ + "MONITOR_NE4BEG3_1", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_IMUX46_1", + "VFRAME_IMUX46" + ], + [ + "MONITOR_FAN5_1", + "VFRAME_FAN5" + ], + [ + "MONITOR_LH5_1", + "VFRAME_LH5" + ], + [ + "MONITOR_EL1BEG0_1", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_SE4C3_1", + "VFRAME_SE4C3" + ], + [ + "MONITOR_SW4A2_1", + "VFRAME_SW4A2" + ], + [ + "MONITOR_NE4BEG2_1", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_IMUX16_1", + "VFRAME_IMUX16" + ], + [ + "MONITOR_EL1BEG1_1", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_NE2A1_1", + "VFRAME_NE2A1" + ], + [ + "MONITOR_WR1END0_1", + "VFRAME_WR1END0" + ], + [ + "MONITOR_FAN7_1", + "VFRAME_FAN7" + ], + [ + "MONITOR_NE4BEG1_1", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_NE4BEG0_1", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_IMUX38_1", + "VFRAME_IMUX38" + ], + [ + "MONITOR_EE4A1_1", + "VFRAME_EE4A1" + ], + [ + "MONITOR_FAN3_1", + "VFRAME_FAN3" + ], + [ + "MONITOR_SE4BEG0_1", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_IMUX42_1", + "VFRAME_IMUX42" + ], + [ + "MONITOR_IMUX29_1", + "VFRAME_IMUX29" + ], + [ + "MONITOR_EE4B3_1", + "VFRAME_EE4B3" + ], + [ + "MONITOR_LH8_1", + "VFRAME_LH8" + ], + [ + "MONITOR_IMUX43_1", + "VFRAME_IMUX43" + ], + [ + "MONITOR_WW2END0_1", + "VFRAME_WW2END0" + ], + [ + "MONITOR_NE2A3_1", + "VFRAME_NE2A3" + ], + [ + "MONITOR_WW4C0_1", + "VFRAME_WW4C0" + ], + [ + "MONITOR_LH11_1", + "VFRAME_LH11" + ], + [ + "MONITOR_BYP1_1", + "VFRAME_BYP1" + ], + [ + "MONITOR_WW2END3_1", + "VFRAME_WW2END3" + ], + [ + "MONITOR_EE4BEG2_1", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_IMUX3_1", + "VFRAME_IMUX3" + ], + [ + "MONITOR_CLK0_1", + "VFRAME_CLK0" + ], + [ + "MONITOR_WR1END3_1", + "VFRAME_WR1END3" + ], + [ + "MONITOR_SW2A1_1", + "VFRAME_SW2A1" + ], + [ + "MONITOR_EE4A2_1", + "VFRAME_EE4A2" + ], + [ + "MONITOR_EE4BEG3_1", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_NW4A1_1", + "VFRAME_NW4A1" + ], + [ + "MONITOR_EL1BEG2_1", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_WW2A2_1", + "VFRAME_WW2A2" + ], + [ + "MONITOR_NE4C2_1", + "VFRAME_NE4C2" + ], + [ + "MONITOR_SE4BEG3_1", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_LH9_1", + "VFRAME_LH9" + ], + [ + "MONITOR_IMUX0_1", + "VFRAME_IMUX0" + ], + [ + "MONITOR_IMUX12_1", + "VFRAME_IMUX12" + ], + [ + "MONITOR_WL1END1_1", + "VFRAME_WL1END1" + ], + [ + "MONITOR_LH10_1", + "VFRAME_LH10" + ], + [ + "MONITOR_ER1BEG2_1", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_EE2A2_1", + "VFRAME_EE2A2" + ], + [ + "MONITOR_EE2BEG0_1", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_EE4BEG1_1", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX30_1", + "VFRAME_IMUX30" + ], + [ + "MONITOR_FAN6_1", + "VFRAME_FAN6" + ], + [ + "MONITOR_IMUX41_1", + "VFRAME_IMUX41" + ], + [ + "MONITOR_EE2BEG2_1", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_IMUX10_1", + "VFRAME_IMUX10" + ], + [ + "MONITOR_IMUX40_1", + "VFRAME_IMUX40" + ], + [ + "MONITOR_SW4A0_1", + "VFRAME_SW4A0" + ], + [ + "MONITOR_EE4B1_1", + "VFRAME_EE4B1" + ], + [ + "MONITOR_IMUX33_1", + "VFRAME_IMUX33" + ], + [ + "MONITOR_FAN0_1", + "VFRAME_FAN0" + ], + [ + "MONITOR_BYP2_1", + "VFRAME_BYP2" + ], + [ + "MONITOR_ER1BEG0_1", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_WW2A0_1", + "VFRAME_WW2A0" + ], + [ + "MONITOR_SE4C2_1", + "VFRAME_SE4C2" + ], + [ + "MONITOR_WW2A1_1", + "VFRAME_WW2A1" + ], + [ + "MONITOR_EE4B2_1", + "VFRAME_EE4B2" + ], + [ + "MONITOR_EE4B0_1", + "VFRAME_EE4B0" + ], + [ + "MONITOR_IMUX44_1", + "VFRAME_IMUX44" + ], + [ + "MONITOR_WL1END0_1", + "VFRAME_WL1END0" + ], + [ + "MONITOR_IMUX45_1", + "VFRAME_IMUX45" + ], + [ + "MONITOR_WW4B3_1", + "VFRAME_WW4B3" + ], + [ + "MONITOR_SW4END0_1", + "VFRAME_SW4END0" + ], + [ + "MONITOR_WW2A3_1", + "VFRAME_WW2A3" + ], + [ + "MONITOR_IMUX5_1", + "VFRAME_IMUX5" + ], + [ + "MONITOR_WW4A0_1", + "VFRAME_WW4A0" + ], + [ + "MONITOR_NW4END1_1", + "VFRAME_NW4END1" + ], + [ + "MONITOR_EE2BEG1_1", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_EE2BEG3_1", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_NW4END0_1", + "VFRAME_NW4END0" + ], + [ + "MONITOR_IMUX27_1", + "VFRAME_IMUX27" + ], + [ + "MONITOR_IMUX2_1", + "VFRAME_IMUX2" + ], + [ + "MONITOR_CLK1_1", + "VFRAME_CLK1" + ], + [ + "MONITOR_EE4C1_1", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX37_1", + "VFRAME_IMUX37" + ], + [ + "MONITOR_WW4A1_1", + "VFRAME_WW4A1" + ], + [ + "MONITOR_SE2A3_1", + "VFRAME_SE2A3" + ], + [ + "MONITOR_IMUX21_1", + "VFRAME_IMUX21" + ], + [ + "MONITOR_LH1_1", + "VFRAME_LH1" + ], + [ + "MONITOR_WW4C3_1", + "VFRAME_WW4C3" + ], + [ + "MONITOR_IMUX20_1", + "VFRAME_IMUX20" + ], + [ + "MONITOR_LH3_1", + "VFRAME_LH3" + ], + [ + "MONITOR_IMUX34_1", + "VFRAME_IMUX34" + ], + [ + "MONITOR_NW2A1_1", + "VFRAME_NW2A1" + ], + [ + "MONITOR_WW4END0_1", + "VFRAME_WW4END0" + ], + [ + "MONITOR_NE4C3_1", + "VFRAME_NE4C3" + ], + [ + "MONITOR_IMUX15_1", + "VFRAME_IMUX15" + ], + [ + "MONITOR_WW2END2_1", + "VFRAME_WW2END2" + ], + [ + "MONITOR_FAN2_1", + "VFRAME_FAN2" + ], + [ + "MONITOR_NW2A0_1", + "VFRAME_NW2A0" + ], + [ + "MONITOR_IMUX18_1", + "VFRAME_IMUX18" + ], + [ + "MONITOR_IMUX6_1", + "VFRAME_IMUX6" + ], + [ + "MONITOR_IMUX35_1", + "VFRAME_IMUX35" + ], + [ + "MONITOR_WW4B2_1", + "VFRAME_WW4B2" + ], + [ + "MONITOR_SE4BEG2_1", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_LH12_1", + "VFRAME_LH12" + ], + [ + "MONITOR_WW4A2_1", + "VFRAME_WW4A2" + ], + [ + "MONITOR_NW4END3_1", + "VFRAME_NW4END3" + ], + [ + "MONITOR_WW4END3_1", + "VFRAME_WW4END3" + ], + [ + "MONITOR_IMUX28_1", + "VFRAME_IMUX28" + ], + [ + "MONITOR_EE4BEG0_1", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_WW2END1_1", + "VFRAME_WW2END1" + ], + [ + "MONITOR_IMUX26_1", + "VFRAME_IMUX26" + ], + [ + "MONITOR_EE4C2_1", + "VFRAME_EE4C2" + ], + [ + "MONITOR_SE2A0_1", + "VFRAME_SE2A0" + ], + [ + "MONITOR_NW2A2_1", + "VFRAME_NW2A2" + ], + [ + "MONITOR_WW4END2_1", + "VFRAME_WW4END2" + ], + [ + "MONITOR_ER1BEG1_1", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_WR1END1_1", + "VFRAME_WR1END1" + ], + [ + "MONITOR_BYP6_1", + "VFRAME_BYP6" + ], + [ + "MONITOR_BYP7_1", + "VFRAME_BYP7" + ], + [ + "MONITOR_IMUX24_1", + "VFRAME_IMUX24" + ], + [ + "MONITOR_SW4A1_1", + "VFRAME_SW4A1" + ], + [ + "MONITOR_WR1END2_1", + "VFRAME_WR1END2" + ], + [ + "MONITOR_IMUX8_1", + "VFRAME_IMUX8" + ], + [ + "MONITOR_SW4A3_1", + "VFRAME_SW4A3" + ], + [ + "MONITOR_SW4END2_1", + "VFRAME_SW4END2" + ], + [ + "MONITOR_IMUX47_1", + "VFRAME_IMUX47" + ], + [ + "MONITOR_IMUX36_1", + "VFRAME_IMUX36" + ], + [ + "MONITOR_SW2A2_1", + "VFRAME_SW2A2" + ], + [ + "MONITOR_SE4C1_1", + "VFRAME_SE4C1" + ], + [ + "MONITOR_FAN4_1", + "VFRAME_FAN4" + ], + [ + "MONITOR_CTRL0_1", + "VFRAME_CTRL0" + ], + [ + "MONITOR_SE2A1_1", + "VFRAME_SE2A1" + ], + [ + "MONITOR_IMUX22_1", + "VFRAME_IMUX22" + ], + [ + "MONITOR_LH2_1", + "VFRAME_LH2" + ], + [ + "MONITOR_EL1BEG3_1", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_CTRL1_1", + "VFRAME_CTRL1" + ], + [ + "MONITOR_NW4A3_1", + "VFRAME_NW4A3" + ], + [ + "MONITOR_SW2A3_1", + "VFRAME_SW2A3" + ], + [ + "MONITOR_WL1END2_1", + "VFRAME_WL1END2" + ], + [ + "MONITOR_LH4_1", + "VFRAME_LH4" + ], + [ + "MONITOR_IMUX25_1", + "VFRAME_IMUX25" + ], + [ + "MONITOR_BYP0_1", + "VFRAME_BYP0" + ], + [ + "MONITOR_WW4C1_1", + "VFRAME_WW4C1" + ], + [ + "MONITOR_EE2A3_1", + "VFRAME_EE2A3" + ], + [ + "MONITOR_EE4A3_1", + "VFRAME_EE4A3" + ], + [ + "MONITOR_IMUX23_1", + "VFRAME_IMUX23" + ], + [ + "MONITOR_SE2A2_1", + "VFRAME_SE2A2" + ], + [ + "MONITOR_EE4C0_1", + "VFRAME_EE4C0" + ], + [ + "MONITOR_NE4C1_1", + "VFRAME_NE4C1" + ], + [ + "MONITOR_WL1END3_1", + "VFRAME_WL1END3" + ], + [ + "MONITOR_IMUX1_1", + "VFRAME_IMUX1" + ], + [ + "MONITOR_NE4C0_1", + "VFRAME_NE4C0" + ], + [ + "MONITOR_IMUX11_1", + "VFRAME_IMUX11" + ], + [ + "MONITOR_BYP4_1", + "VFRAME_BYP4" + ], + [ + "MONITOR_SW2A0_1", + "VFRAME_SW2A0" + ], + [ + "MONITOR_LH6_1", + "VFRAME_LH6" + ], + [ + "MONITOR_SE4BEG1_1", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_LH7_1", + "VFRAME_LH7" + ], + [ + "MONITOR_NW4END2_1", + "VFRAME_NW4END2" + ], + [ + "MONITOR_BYP5_1", + "VFRAME_BYP5" + ], + [ + "MONITOR_IMUX14_1", + "VFRAME_IMUX14" + ], + [ + "MONITOR_WW4A3_1", + "VFRAME_WW4A3" + ], + [ + "MONITOR_NE2A2_1", + "VFRAME_NE2A2" + ], + [ + "MONITOR_IMUX32_1", + "VFRAME_IMUX32" + ], + [ + "MONITOR_IMUX13_1", + "VFRAME_IMUX13" + ], + [ + "MONITOR_IMUX17_1", + "VFRAME_IMUX17" + ], + [ + "MONITOR_WW4C2_1", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE2A0_1", + "VFRAME_EE2A0" + ], + [ + "MONITOR_IMUX9_1", + "VFRAME_IMUX9" + ], + [ + "MONITOR_IMUX39_1", + "VFRAME_IMUX39" + ], + [ + "MONITOR_SW4END3_1", + "VFRAME_SW4END3" + ], + [ + "MONITOR_IMUX19_1", + "VFRAME_IMUX19" + ] + ], + "tile_types": [ + "MONITOR_TOP_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "IOI_IMUX11_0", + "TERM_INT_IMUX11" + ], + [ + "IOI_IMUX43_0", + "TERM_INT_IMUX43" + ], + [ + "IOI_FAN1_0", + "TERM_INT_FAN1" + ], + [ + "IOI_LOGIC_OUTS18_0", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_CTRL1_0", + "TERM_INT_CTRL1" + ], + [ + "IOI_BYP2_0", + "TERM_INT_BYP2" + ], + [ + "IOI_LOGIC_OUTS2_0", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_IMUX6_0", + "TERM_INT_IMUX6" + ], + [ + "IOI_IMUX36_0", + "TERM_INT_IMUX36" + ], + [ + "IOI_IMUX34_0", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX0_0", + "TERM_INT_IMUX0" + ], + [ + "IOI_IMUX46_0", + "TERM_INT_IMUX46" + ], + [ + "IOI_LOGIC_OUTS23_0", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_IMUX20_0", + "TERM_INT_IMUX20" + ], + [ + "IOI_LOGIC_OUTS15_0", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX19_0", + "TERM_INT_IMUX19" + ], + [ + "IOI_IMUX47_0", + "TERM_INT_IMUX47" + ], + [ + "IOI_IMUX25_0", + "TERM_INT_IMUX25" + ], + [ + "IOI_LOGIC_OUTS7_0", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_FAN2_0", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX45_0", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX31_0", + "TERM_INT_IMUX31" + ], + [ + "IOI_LOGIC_OUTS19_0", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_IMUX1_0", + "TERM_INT_IMUX1" + ], + [ + "IOI_MONITOR_N", + "TERM_INT_MONITOR_N" + ], + [ + "IOI_IMUX22_0", + "TERM_INT_IMUX22" + ], + [ + "IOI_IMUX12_0", + "TERM_INT_IMUX12" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_BLOCK_OUTS2_0", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "LIOI_I2GCLK_TOP0", + "L_TERM_INT_DQS_IOTOPHASER" + ], + [ + "IOI_IMUX40_0", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX10_0", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX16_0", + "TERM_INT_IMUX16" + ], + [ + "IOI_FAN0_0", + "TERM_INT_FAN0" + ], + [ + "IOI_IMUX38_0", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX26_0", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX3_0", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX24_0", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX37_0", + "TERM_INT_IMUX37" + ], + [ + "IOI_LOGIC_OUTS3_0", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_FAN4_0", + "TERM_INT_FAN4" + ], + [ + "IOI_FAN6_0", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX7_0", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX39_0", + "TERM_INT_IMUX39" + ], + [ + "IOI_CTRL0_0", + "TERM_INT_CTRL0" + ], + [ + "IOI_CLK0_0", + "TERM_INT_CLK0" + ], + [ + "IOI_FAN7_0", + "TERM_INT_FAN7" + ], + [ + "IOI_CLK1_0", + "TERM_INT_CLK1" + ], + [ + "IOI_BYP0_0", + "TERM_INT_BYP0" + ], + [ + "IOI_LOGIC_OUTS0_0", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_IMUX8_0", + "TERM_INT_IMUX8" + ], + [ + "IOI_LOGIC_OUTS16_0", + "TERM_INT_LOGIC_OUTS_L_B16" + ], + [ + "IOI_LOGIC_OUTS11_0", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_BYP6_0", + "TERM_INT_BYP6" + ], + [ + "IOI_IMUX42_0", + "TERM_INT_IMUX42" + ], + [ + "IOI_IMUX30_0", + "TERM_INT_IMUX30" + ], + [ + "IOI_LOGIC_OUTS1_0", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX5_0", + "TERM_INT_IMUX5" + ], + [ + "IOI_IMUX4_0", + "TERM_INT_IMUX4" + ], + [ + "IOI_IMUX17_0", + "TERM_INT_IMUX17" + ], + [ + "IOI_IMUX23_0", + "TERM_INT_IMUX23" + ], + [ + "IOI_IMUX33_0", + "TERM_INT_IMUX33" + ], + [ + "IOI_PHASER_TO_IO_ICLK", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_FAN5_0", + "TERM_INT_FAN5" + ], + [ + "IOI_LOGIC_OUTS9_0", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_BYP1_0", + "TERM_INT_BYP1" + ], + [ + "IOI_LOGIC_OUTS14_0", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_IMUX13_0", + "TERM_INT_IMUX13" + ], + [ + "IOI_IMUX44_0", + "TERM_INT_IMUX44" + ], + [ + "IOI_LOGIC_OUTS20_0", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_LOGIC_OUTS5_0", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_IMUX27_0", + "TERM_INT_IMUX27" + ], + [ + "IOI_IMUX18_0", + "TERM_INT_IMUX18" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_IMUX9_0", + "TERM_INT_IMUX9" + ], + [ + "IOI_FAN3_0", + "TERM_INT_FAN3" + ], + [ + "IOI_BYP5_0", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS8_0", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_PHASER_TO_IO_OCLK", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_BYP4_0", + "TERM_INT_BYP4" + ], + [ + "IOI_BYP7_0", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_0", + "TERM_INT_IMUX2" + ], + [ + "IOI_LOGIC_OUTS13_0", + "TERM_INT_LOGIC_OUTS_L_B13" + ], + [ + "IOI_IMUX35_0", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP3_0", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX15_0", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX29_0", + "TERM_INT_IMUX29" + ], + [ + "IOI_LOGIC_OUTS10_0", + "TERM_INT_LOGIC_OUTS_L_B10" + ], + [ + "IOI_IMUX14_0", + "TERM_INT_IMUX14" + ], + [ + "IOI_MONITOR_P", + "TERM_INT_MONITOR_P" + ], + [ + "IOI_IMUX21_0", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX28_0", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX41_0", + "TERM_INT_IMUX41" + ], + [ + "IOI_BLOCK_OUTS0_0", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_IMUX32_0", + "TERM_INT_IMUX32" + ] + ], + "tile_types": [ + "LIOI3", + "L_TERM_INT" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "GTXE2_BYP3_1", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX31_1", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX35_1", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX17_1", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX28_1", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_FAN7_1", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX21_1", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_FAN6_1", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX12_1", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B18_1", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX40_1", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B14_1", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX8_1", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX0_1", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX6_1", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX44_1", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_FAN3_1", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX7_1", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX37_1", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_BYP6_1", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX10_1", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX20_1", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN1_1", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_1", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B6_1", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_FAN2_1", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX41_1", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B13_1", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_CLK0_1", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX5_1", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX24_1", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_CLK1_1", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_CTRL0_1", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_CTRL1_1", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX9_1", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_LOGIC_OUTS_B16_1", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX34_1", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_LOGIC_OUTS_B3_1", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX45_1", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX43_1", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX19_1", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_LOGIC_OUTS_B4_1", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B1_1", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX29_1", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_BYP1_1", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX15_1", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_LOGIC_OUTS_B15_1", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX39_1", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B17_1", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX27_1", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B10_1", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX47_1", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX46_1", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX36_1", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_LOGIC_OUTS_B2_1", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_FAN5_1", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_BYP0_1", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_FAN4_1", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_BYP5_1", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX3_1", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX22_1", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX38_1", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_LOGIC_OUTS_B0_1", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_LOGIC_OUTS_B5_1", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX30_1", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_BYP4_1", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX42_1", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX13_1", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP7_1", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX25_1", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B9_1", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX18_1", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_LOGIC_OUTS_B7_1", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_IMUX32_1", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN0_1", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_LOGIC_OUTS_B22_1", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B20_1", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_LOGIC_OUTS_B11_1", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_LOGIC_OUTS_B8_1", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_BYP2_1", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX26_1", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX33_1", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX2_1", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX11_1", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX16_1", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX4_1", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX23_1", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX14_1", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX1_1", + "VBRK_EXT_IMUX1" + ] + ], + "tile_types": [ + "GTX_CHANNEL_0", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_CLK_2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_MUX_CLK_13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_CLK_9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_MUX_CLK_12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_MUX_CLK_1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ], + [ + "HCLK_CMT_MUX_CLK_8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CMT_MUX_CLK_5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CMT_MUX_CLK_0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CMT_MUX_CLK_3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CMT_MUX_CLK_10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_MUX_CLK_7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CMT_MUX_CLK_11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CMT_MUX_CLK_4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CMT_MUX_CLK_6", + "HCLK_VBRK_MUX_CLK6" + ] + ], + "tile_types": [ + "HCLK_CMT", + "HCLK_VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 6 + ], + "wire_pairs": [ + [ + "PCIE_EE4A3_4", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_NW4END1_4", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_SW4END0_4", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_EE2A2_4", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_WL1END3_4", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_EE2BEG1_4", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX10_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_SE4BEG0_4", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_NE2A0_4", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_EE2A1_4", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_LH6_4", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_WL1END2_4", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_4", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_NE4C2_4", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_4", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_CLK1_R_4", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_CTRL0_R_4", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_EE2BEG3_4", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_LH5_4", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_WR1END2_4", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_WW4B1_4", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_ER1BEG2_4", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_WL1END0_4", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_WW4C0_4", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_NW4A2_4", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_IMUX11_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_4", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_IMUX18_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_SW4END2_4", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_SW4A2_4", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_IMUX35_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_NW2A1_4", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_FAN6_R_4", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_IMUX12_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_NW2A2_4", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_IMUX14_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_4", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_EE2BEG0_4", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_4", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_NW2A3_4", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_IMUX45_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_IMUX27_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_4", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_IMUX7_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_IMUX13_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_EL1BEG1_4", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_IMUX43_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_IMUX34_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_EE4B1_4", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_BYP3_R_4", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_4", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_NE2A2_4", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_4", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_BYP5_R_4", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_IMUX32_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_NE4BEG3_4", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_BYP1_R_4", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_4", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_FAN3_R_4", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_4", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_EE4C1_4", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_NE4C0_4", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_IMUX42_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_SE4C0_4", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_EE4A1_4", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_EE2A3_4", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_SE4BEG2_4", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_BYP2_R_4", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_SW2A3_4", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_SE4C3_4", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_NE4BEG1_4", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_SE4BEG3_4", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_EE4A2_4", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_IMUX33_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_LH3_4", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_WW4A0_4", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_IMUX8_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_SW4END3_4", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_4", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_IMUX4_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_NE4C3_4", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_EE4C0_4", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_FAN0_R_4", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_IMUX40_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_IMUX25_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_WW2A1_4", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_WR1END3_4", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_WW2END3_4", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_IMUX16_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_LH2_4", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_IMUX0_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_4", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_4", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_NE4BEG2_4", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_CTRL1_R_4", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_FAN2_R_4", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_EE4BEG1_4", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_IMUX36_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_IMUX30_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_EE2A0_4", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_EE4B0_4", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_4", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_ER1BEG0_4", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_IMUX37_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_EE4C3_4", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_IMUX2_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_WW2END0_4", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_IMUX6_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_BYP7_R_4", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_NE4BEG0_4", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_CLK0_R_4", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_LH9_4", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_NW4A1_4", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_NW4A0_4", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WW4END1_4", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_SE2A2_4", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_EE4C2_4", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_BYP0_R_4", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_FAN4_R_4", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_EL1BEG2_4", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_NW4END0_4", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_NW4END2_4", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_IMUX21_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_WW4END2_4", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_WW4END3_4", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_4", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_SE2A0_4", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_LH12_4", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_IMUX1_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_BYP4_R_4", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_EE4B3_4", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_IMUX29_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_IMUX20_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_IMUX15_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_ER1BEG3_4", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_SE4BEG1_4", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_IMUX24_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_IMUX28_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_SW4A1_4", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_4", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_WR1END0_4", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_WL1END1_4", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_SW2A0_4", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_FAN1_R_4", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_IMUX23_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_4", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_EL1BEG3_4", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_SW2A2_4", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_4", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_NE4C1_4", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_IMUX26_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_EL1BEG0_4", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_IMUX46_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_IMUX38_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_WW2END2_4", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_ER1BEG1_4", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_WW4END0_4", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_IMUX22_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_IMUX17_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_WW4A2_4", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_WW4A1_4", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_LH11_4", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_SW4A3_4", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_SE2A3_4", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_4", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_IMUX9_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_NE2A3_4", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_LH8_4", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4BEG3_4", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_WW2A0_4", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_NW2A0_4", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_WW4C1_4", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_WW4C3_4", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_NE2A1_4", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_IMUX3_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_LH1_4", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_LH4_4", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_4", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_SE2A1_4", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_WW4A3_4", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_WR1END1_4", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_SE4C2_4", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_SW2A1_4", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_FAN5_R_4", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_WW4C2_4", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_4", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_WW2A2_4", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_4", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_EE2BEG2_4", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_FAN7_R_4", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_4", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_IMUX31_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_WW4B2_4", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_4", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_EE4BEG2_4", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_NW4END3_4", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_IMUX5_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_SW4A0_4", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_EE4B2_4", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_IMUX41_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_NW4A3_4", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_WW4B0_4", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_WW2END1_4", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_EE4BEG0_4", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX47_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_IMUX44_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_BYP6_R_4", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_IMUX19_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_LH10_4", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_WW4B3_4", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_SE4C1_4", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_WW2A3_4", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_SW4END1_4", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_IMUX39_R_4", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_LH7_4", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_EE4A0_4", + "INT_INTERFACE_EE4A0" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "CMT_TOP_EL1BEG1_8", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG1_8", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NW4A0_8", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4B0_8", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_8", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW2A0_8", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW2A0_8", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4BEG2_8", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_MONITOR_P_8", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_NE4C0_8", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_ER1BEG2_8", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_8", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_LH12_8", + "VBRK_LH12" + ], + [ + "CMT_TOP_EL1BEG2_8", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_LH1_8", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH10_8", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW4B1_8", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG2_8", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW4A3_8", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4C3_8", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_MONITOR_N_8", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW2A0_8", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NW4END0_8", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE2A2_8", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4C1_8", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW4C2_8", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW4A1_8", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NW2A1_8", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SE4BEG0_8", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_8", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_LH3_8", + "VBRK_LH3" + ], + [ + "CMT_TOP_WR1END2_8", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A0_8", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4A2_8", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END1_8", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A0_8", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A1_8", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EL1BEG0_8", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_EE4A3_8", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C3_8", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE4A0_8", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END1_8", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH4_8", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2A0_8", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH2_8", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4C1_8", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NE2A2_8", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2A3_8", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_NW4A3_8", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4END2_8", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE2A1_8", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END2_8", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2END0_8", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2BEG0_8", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4C0_8", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG0_8", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_WR1END0_8", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_SE4C2_8", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4END1_8", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NE2A1_8", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4B3_8", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_8", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C2_8", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4B1_8", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW2A3_8", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SE4C1_8", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WR1END3_8", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW2A2_8", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C0_8", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4C1_8", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH11_8", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4B2_8", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW2A3_8", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NW4END2_8", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A0_8", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WR1END1_8", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH5_8", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END3_8", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH6_8", + "VBRK_LH6" + ], + [ + "CMT_TOP_NE4BEG3_8", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_LH8_8", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A1_8", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE2BEG2_8", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4C3_8", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NW2A2_8", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END3_8", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE2A3_8", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_ER1BEG1_8", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_8", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_NE4BEG1_8", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_WW4A2_8", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG0_8", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NE4C2_8", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SE4BEG3_8", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C0_8", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_8", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2BEG3_8", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH9_8", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE4B2_8", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_WL1END0_8", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_WW2END3_8", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EL1BEG3_8", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG3_8", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4BEG3_8", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WL1END1_8", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2A1_8", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SE4BEG2_8", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW2A3_8", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SE4C3_8", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE2A2_8", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_8", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4A1_8", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW4A2_8", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SW2A2_8", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_NW4END3_8", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SW4END1_8", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END3_8", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4BEG1_8", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4END2_8", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH7_8", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4BEG0_8", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2BEG1_8", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_8", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A3_8", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WL1END2_8", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A0_8", + "VBRK_WW4A0" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "CLK_HROW_EE4A1_5", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_WW2A1_5", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_IMUX17_5", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_NE2A2_5", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_SW4END3_5", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_EE2BEG1_5", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_WW4END3_5", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_IMUX26_5", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_EE4B3_5", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_IMUX19_5", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_NE2A0_5", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_SE2A2_5", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_NE4BEG0_5", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_EE4C0_5", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_WW2A3_5", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_BYP4_5", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_CTRL1_5", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_BYP1_5", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_IMUX44_5", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_SE2A0_5", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_IMUX11_5", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_NW4END3_5", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_FAN0_5", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_FAN7_5", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_IMUX1_5", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_ER1BEG2_5", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_IMUX20_5", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_WW2A2_5", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_WW2END2_5", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_WW4A1_5", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_WW2END1_5", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_SE4C0_5", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_EE4B2_5", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_NW2A1_5", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_SW4END1_5", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_IMUX6_5", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_SW4END2_5", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_IMUX45_5", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_IMUX9_5", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_IMUX3_5", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_EE2A0_5", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_BYP0_5", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_NW2A0_5", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_BYP2_5", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_NE4BEG3_5", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_WW4C1_5", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_FAN6_5", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_WW4A2_5", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_NW4A2_5", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_SW2A3_5", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_EE4C1_5", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_SW2A1_5", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_EL1BEG3_5", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_IMUX23_5", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_IMUX18_5", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_WL1END0_5", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_NE2A3_5", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_IMUX7_5", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_EE4B0_5", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_ER1BEG1_5", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_ER1BEG3_5", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_IMUX34_5", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_WW4A0_5", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_EL1BEG1_5", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_NE4C2_5", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_CTRL0_5", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_NW4A3_5", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WW4C2_5", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_IMUX24_5", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_WR1END0_5", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_IMUX28_5", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_SW4A3_5", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_NE4C0_5", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_EE2BEG3_5", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_EE4A0_5", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_NW4END1_5", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_SW4A1_5", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_IMUX46_5", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_LH1_5", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_LH12_5", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_IMUX32_5", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_SE4BEG0_5", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_LH6_5", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_BYP5_5", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_SW4A2_5", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_SW4A0_5", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_EE2A3_5", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_LH10_5", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_SE2A3_5", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_EE4C2_5", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_IMUX22_5", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_SE4C3_5", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_IMUX13_5", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_EE4BEG2_5", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_NE4C1_5", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_WW4END0_5", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_IMUX4_5", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_WW4END2_5", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_NW4END2_5", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_FAN3_5", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_WW4C3_5", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_SW4END0_5", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_WL1END2_5", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_SE4C2_5", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_NE2A1_5", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_CLK0_5", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_LH9_5", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_IMUX15_5", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_EE4BEG3_5", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_WR1END2_5", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_LH5_5", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_NW4END0_5", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_IMUX37_5", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_IMUX8_5", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_EE2BEG0_5", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_IMUX31_5", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_LH11_5", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_WR1END3_5", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_IMUX25_5", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_IMUX42_5", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_EE4B1_5", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_WW4B3_5", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_LH2_5", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_SE4BEG1_5", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_NW4A1_5", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_EE4A2_5", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_LH8_5", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_IMUX0_5", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_IMUX21_5", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_IMUX5_5", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_FAN1_5", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_IMUX43_5", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_WW4B1_5", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_IMUX38_5", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_FAN4_5", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_IMUX14_5", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_LH4_5", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_EL1BEG2_5", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_LH3_5", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_IMUX35_5", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_SE4C1_5", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_IMUX47_5", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_IMUX16_5", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_FAN5_5", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_WR1END1_5", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_WW4END1_5", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_IMUX27_5", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_BYP7_5", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_SE4BEG2_5", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_LH7_5", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_WW2END3_5", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_NW4A0_5", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_WW2END0_5", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_EE4A3_5", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_IMUX29_5", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_IMUX39_5", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_EL1BEG0_5", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_SE4BEG3_5", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_NW2A3_5", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_EE4BEG1_5", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_NE4BEG2_5", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_WL1END1_5", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_IMUX12_5", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_EE2A2_5", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_WL1END3_5", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_IMUX2_5", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_NE4BEG1_5", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_IMUX41_5", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_IMUX40_5", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_WW4A3_5", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_CLK1_5", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_IMUX36_5", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_EE4BEG0_5", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_EE4C3_5", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_IMUX10_5", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_WW2A0_5", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE2BEG2_5", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_SE2A1_5", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_FAN2_5", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_BYP3_5", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_WW4B0_5", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_NW2A2_5", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_IMUX30_5", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_SW2A2_5", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_ER1BEG0_5", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_EE2A1_5", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_NE4C3_5", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_IMUX33_5", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_SW2A0_5", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_BYP6_5", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_WW4C0_5", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_WW4B2_5", + "INT_INTERFACE_WW4B2" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 7 + ], + "wire_pairs": [ + [ + "CMT_PMV_LOGIC_OUTS8", + "CMT_TOP_LOGIC_OUTS_L_B8_12" + ], + [ + "CMT_PMV_IMUX25", + "CMT_TOP_IMUX25_12" + ], + [ + "CMT_PMV_IMUX3", + "CMT_TOP_IMUX3_12" + ], + [ + "CMT_PMV_IMUX24", + "CMT_TOP_IMUX24_12" + ], + [ + "CMT_PMV_IMUX29", + "CMT_TOP_IMUX29_12" + ], + [ + "CMT_PMV_WW2A2", + "CMT_TOP_WW2A2_12" + ], + [ + "CMT_PMV_EE4B2", + "CMT_TOP_EE4B2_12" + ], + [ + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "CMT_TOP_ICLKDIV_12" + ], + [ + "CMT_PMV_IMUX30", + "CMT_TOP_IMUX30_12" + ], + [ + "CMT_PMV_WW4C1", + "CMT_TOP_WW4C1_12" + ], + [ + "CMT_PMV_LOGIC_OUTS5", + "CMT_TOP_LOGIC_OUTS_L_B5_12" + ], + [ + "CMT_PMV_WW4END1", + "CMT_TOP_WW4END1_12" + ], + [ + "CMT_PMV_IMUX46", + "CMT_TOP_IMUX46_12" + ], + [ + "CMT_PMV_SE4BEG3", + "CMT_TOP_SE4BEG3_12" + ], + [ + "CMT_PMV_EE2BEG0", + "CMT_TOP_EE2BEG0_12" + ], + [ + "CMT_PMV_IMUX7", + "CMT_TOP_IMUX7_12" + ], + [ + "CMT_PMV_WW4A1", + "CMT_TOP_WW4A1_12" + ], + [ + "CMT_PMV_SE2A3", + "CMT_TOP_SE2A3_12" + ], + [ + "CMT_PMV_EE4C3", + "CMT_TOP_EE4C3_12" + ], + [ + "CMT_PMV_IMUX40", + "CMT_TOP_IMUX40_12" + ], + [ + "CMT_PMV_FAN3", + "CMT_TOP_FAN3_12" + ], + [ + "CMT_PMV_NW4END3", + "CMT_TOP_NW4END3_12" + ], + [ + "CMT_PMV_EE2A1", + "CMT_TOP_EE2A1_12" + ], + [ + "CMT_PMV_WW2A3", + "CMT_TOP_WW2A3_12" + ], + [ + "CMT_PMV_EE4BEG2", + "CMT_TOP_EE4BEG2_12" + ], + [ + "CMT_PMV_BYP0", + "CMT_TOP_BYP0_12" + ], + [ + "CMT_PMV_IMUX5", + "CMT_TOP_IMUX5_12" + ], + [ + "CMT_PMV_WW2A1", + "CMT_TOP_WW2A1_12" + ], + [ + "CMT_PMV_EE4BEG3", + "CMT_TOP_EE4BEG3_12" + ], + [ + "CMT_PMV_EE4B1", + "CMT_TOP_EE4B1_12" + ], + [ + "CMT_PMV_SW4A0", + "CMT_TOP_SW4A0_12" + ], + [ + "CMT_PMV_LOGIC_OUTS0", + "CMT_TOP_LOGIC_OUTS_L_B0_12" + ], + [ + "CMT_PMV_IMUX12", + "CMT_TOP_IMUX12_12" + ], + [ + "CMT_PMV_IMUX39", + "CMT_TOP_IMUX39_12" + ], + [ + "CMT_PMV_SE4BEG0", + "CMT_TOP_SE4BEG0_12" + ], + [ + "CMT_PMV_IMUX23", + "CMT_TOP_IMUX23_12" + ], + [ + "CMT_PMV_NE2A3", + "CMT_TOP_NE2A3_12" + ], + [ + "CMT_PMV_NW4A0", + "CMT_TOP_NW4A0_12" + ], + [ + "CMT_PMV_NE4C1", + "CMT_TOP_NE4C1_12" + ], + [ + "CMT_PMV_LOGIC_OUTS22", + "CMT_TOP_LOGIC_OUTS_L_B22_12" + ], + [ + "CMT_PMV_LH7", + "CMT_TOP_LH7_12" + ], + [ + "CMT_PMV_NW2A1", + "CMT_TOP_NW2A1_12" + ], + [ + "CMT_PMV_SE2A1", + "CMT_TOP_SE2A1_12" + ], + [ + "CMT_PMV_IMUX17", + "CMT_TOP_IMUX17_12" + ], + [ + "CMT_PMV_IMUX28", + "CMT_TOP_IMUX28_12" + ], + [ + "CMT_PMV_FAN0", + "CMT_TOP_FAN0_12" + ], + [ + "CMT_PMV_LOGIC_OUTS23", + "CMT_TOP_LOGIC_OUTS_L_B23_12" + ], + [ + "CMT_PMV_NE4C2", + "CMT_TOP_NE4C2_12" + ], + [ + "CMT_PMV_IMUX47", + "CMT_TOP_IMUX47_12" + ], + [ + "CMT_PMV_IMUX21", + "CMT_TOP_IMUX21_12" + ], + [ + "CMT_PMV_IMUX0", + "CMT_TOP_IMUX0_12" + ], + [ + "CMT_PMV_SE4BEG2", + "CMT_TOP_SE4BEG2_12" + ], + [ + "CMT_PMV_NW4A2", + "CMT_TOP_NW4A2_12" + ], + [ + "CMT_PMV_NE2A0", + "CMT_TOP_NE2A0_12" + ], + [ + "CMT_PMV_WW4END2", + "CMT_TOP_WW4END2_12" + ], + [ + "CMT_PMV_WW4B0", + "CMT_TOP_WW4B0_12" + ], + [ + "CMT_PMV_LH8", + "CMT_TOP_LH8_12" + ], + [ + "CMT_PMV_IMUX20", + "CMT_TOP_IMUX20_12" + ], + [ + "CMT_PMV_SW2A0", + "CMT_TOP_SW2A0_12" + ], + [ + "CMT_PMV_NE2A1", + "CMT_TOP_NE2A1_12" + ], + [ + "CMT_PMV_NW2A0", + "CMT_TOP_NW2A0_12" + ], + [ + "CMT_PMV_EE4A3", + "CMT_TOP_EE4A3_12" + ], + [ + "CMT_PMV_LH1", + "CMT_TOP_LH1_12" + ], + [ + "CMT_PMV_SW2A3", + "CMT_TOP_SW2A3_12" + ], + [ + "CMT_PMV_EE2BEG1", + "CMT_TOP_EE2BEG1_12" + ], + [ + "CMT_PMV_IMUX44", + "CMT_TOP_IMUX44_12" + ], + [ + "CMT_PMV_WL1END1", + "CMT_TOP_WL1END1_12" + ], + [ + "CMT_PMV_LOGIC_OUTS13", + "CMT_TOP_LOGIC_OUTS_L_B13_12" + ], + [ + "CMT_PMV_BYP3", + "CMT_TOP_BYP3_12" + ], + [ + "CMT_PMV_WW4B2", + "CMT_TOP_WW4B2_12" + ], + [ + "CMT_PMV_IMUX33", + "CMT_TOP_IMUX33_12" + ], + [ + "CMT_PMV_EE4B3", + "CMT_TOP_EE4B3_12" + ], + [ + "CMT_PMV_LH5", + "CMT_TOP_LH5_12" + ], + [ + "CMT_PMV_BYP2", + "CMT_TOP_BYP2_12" + ], + [ + "CMT_PMV_ER1BEG1", + "CMT_TOP_ER1BEG1_12" + ], + [ + "CMT_PMV_SE2A0", + "CMT_TOP_SE2A0_12" + ], + [ + "CMT_PMV_WW2END3", + "CMT_TOP_WW2END3_12" + ], + [ + "CMT_PMV_IMUX38", + "CMT_TOP_IMUX38_12" + ], + [ + "CMT_PMV_BYP5", + "CMT_TOP_BYP5_12" + ], + [ + "CMT_PMV_SW4END3", + "CMT_TOP_SW4END3_12" + ], + [ + "CMT_PMV_NE4BEG3", + "CMT_TOP_NE4BEG3_12" + ], + [ + "CMT_PMV_NE4BEG1", + "CMT_TOP_NE4BEG1_12" + ], + [ + "CMT_PMV_EE2A0", + "CMT_TOP_EE2A0_12" + ], + [ + "CMT_PMV_LOGIC_OUTS7", + "CMT_TOP_LOGIC_OUTS_L_B7_12" + ], + [ + "CMT_PMV_WW4B1", + "CMT_TOP_WW4B1_12" + ], + [ + "CMT_PMV_LH10", + "CMT_TOP_LH10_12" + ], + [ + "CMT_PMV_WW4C0", + "CMT_TOP_WW4C0_12" + ], + [ + "CMT_PMV_IMUX19", + "CMT_TOP_IMUX19_12" + ], + [ + "CMT_PMV_IMUX6", + "CMT_TOP_IMUX6_12" + ], + [ + "CMT_PMV_IMUX11", + "CMT_TOP_IMUX11_12" + ], + [ + "CMT_PMV_NW4A3", + "CMT_TOP_NW4A3_12" + ], + [ + "CMT_PMV_LOGIC_OUTS21", + "CMT_TOP_LOGIC_OUTS_L_B21_12" + ], + [ + "CMT_PMV_LOGIC_OUTS19", + "CMT_TOP_LOGIC_OUTS_L_B19_12" + ], + [ + "CMT_PMV_IMUX43", + "CMT_TOP_IMUX43_12" + ], + [ + "CMT_PMV_WW2A0", + "CMT_TOP_WW2A0_12" + ], + [ + "CMT_PMV_BYP4", + "CMT_TOP_BYP4_12" + ], + [ + "CMT_PMV_WR1END0", + "CMT_TOP_WR1END0_12" + ], + [ + "CMT_PMV_SE2A2", + "CMT_TOP_SE2A2_12" + ], + [ + "CMT_PMV_EE2BEG2", + "CMT_TOP_EE2BEG2_12" + ], + [ + "CMT_PMV_WR1END3", + "CMT_TOP_WR1END3_12" + ], + [ + "CMT_PMV_LOGIC_OUTS16", + "CMT_TOP_LOGIC_OUTS_L_B16_12" + ], + [ + "L_TERM_INT_PHASER_TO_IO_OCLK", + "CMT_TOP_OCLK_12" + ], + [ + "CMT_PMV_NE4BEG2", + "CMT_TOP_NE4BEG2_12" + ], + [ + "CMT_PMV_WR1END1", + "CMT_TOP_WR1END1_12" + ], + [ + "CMT_PMV_WW2END0", + "CMT_TOP_WW2END0_12" + ], + [ + "CMT_PMV_NW4END1", + "CMT_TOP_NW4END1_12" + ], + [ + "CMT_PMV_LOGIC_OUTS20", + "CMT_TOP_LOGIC_OUTS_L_B20_12" + ], + [ + "CMT_PMV_IMUX14", + "CMT_TOP_IMUX14_12" + ], + [ + "CMT_PMV_WW4C3", + "CMT_TOP_WW4C3_12" + ], + [ + "CMT_PMV_WW4END0", + "CMT_TOP_WW4END0_12" + ], + [ + "CMT_PMV_WW4B3", + "CMT_TOP_WW4B3_12" + ], + [ + "CMT_PMV_NW2A3", + "CMT_TOP_NW2A3_12" + ], + [ + "CMT_PMV_NW4END2", + "CMT_TOP_NW4END2_12" + ], + [ + "CMT_PMV_FAN1", + "CMT_TOP_FAN1_12" + ], + [ + "CMT_PMV_SW4A3", + "CMT_TOP_SW4A3_12" + ], + [ + "CMT_PMV_SE4C3", + "CMT_TOP_SE4C3_12" + ], + [ + "CMT_PMV_IMUX4", + "CMT_TOP_IMUX4_12" + ], + [ + "CMT_PMV_NE4C0", + "CMT_TOP_NE4C0_12" + ], + [ + "CMT_PMV_LH3", + "CMT_TOP_LH3_12" + ], + [ + "CMT_PMV_IMUX16", + "CMT_TOP_IMUX16_12" + ], + [ + "CMT_PMV_EL1BEG1", + "CMT_TOP_EL1BEG1_12" + ], + [ + "CMT_PMV_IMUX35", + "CMT_TOP_IMUX35_12" + ], + [ + "CMT_PMV_IMUX26", + "CMT_TOP_IMUX26_12" + ], + [ + "CMT_PMV_EE2A3", + "CMT_TOP_EE2A3_12" + ], + [ + "CMT_PMV_WW4C2", + "CMT_TOP_WW4C2_12" + ], + [ + "CMT_PMV_NW2A2", + "CMT_TOP_NW2A2_12" + ], + [ + "CMT_PMV_IMUX37", + "CMT_TOP_IMUX37_12" + ], + [ + "CMT_PMV_IMUX41", + "CMT_TOP_IMUX41_12" + ], + [ + "CMT_PMV_CTRL1", + "CMT_TOP_CTRL1_12" + ], + [ + "CMT_PMV_NE4BEG0", + "CMT_TOP_NE4BEG0_12" + ], + [ + "CMT_PMV_EE4A1", + "CMT_TOP_EE4A1_12" + ], + [ + "CMT_PMV_BYP1", + "CMT_TOP_BYP1_12" + ], + [ + "CMT_PMV_WW2END1", + "CMT_TOP_WW2END1_12" + ], + [ + "CMT_PMV_SE4C0", + "CMT_TOP_SE4C0_12" + ], + [ + "CMT_PMV_FAN5", + "CMT_TOP_FAN5_12" + ], + [ + "CMT_PMV_IMUX31", + "CMT_TOP_IMUX31_12" + ], + [ + "CMT_PMV_SW2A1", + "CMT_TOP_SW2A1_12" + ], + [ + "CMT_PMV_EE4B0", + "CMT_TOP_EE4B0_12" + ], + [ + "CMT_PMV_WW4A0", + "CMT_TOP_WW4A0_12" + ], + [ + "L_TERM_INT_PHASER_TO_IO_ICLK", + "CMT_TOP_ICLK_12" + ], + [ + "CMT_PMV_IMUX32", + "CMT_TOP_IMUX32_12" + ], + [ + "CMT_PMV_ER1BEG0", + "CMT_TOP_ER1BEG0_12" + ], + [ + "CMT_PMV_WL1END2", + "CMT_TOP_WL1END2_12" + ], + [ + "CMT_PMV_WW4A3", + "CMT_TOP_WW4A3_12" + ], + [ + "CMT_PMV_SW4END0", + "CMT_TOP_SW4END0_12" + ], + [ + "CMT_PMV_FAN7", + "CMT_TOP_FAN7_12" + ], + [ + "CMT_PMV_SW4END1", + "CMT_TOP_SW4END1_12" + ], + [ + "CMT_PMV_LH11", + "CMT_TOP_LH11_12" + ], + [ + "CMT_PMV_LH12", + "CMT_TOP_LH12_12" + ], + [ + "CMT_PMV_WW2END2", + "CMT_TOP_WW2END2_12" + ], + [ + "CMT_PMV_EE4A2", + "CMT_TOP_EE4A2_12" + ], + [ + "CMT_PMV_NW4A1", + "CMT_TOP_NW4A1_12" + ], + [ + "CMT_PMV_IMUX18", + "CMT_TOP_IMUX18_12" + ], + [ + "CMT_PMV_SE4C2", + "CMT_TOP_SE4C2_12" + ], + [ + "CMT_PMV_BYP6", + "CMT_TOP_BYP6_12" + ], + [ + "CMT_PMV_EL1BEG0", + "CMT_TOP_EL1BEG0_12" + ], + [ + "CMT_PMV_WW4END3", + "CMT_TOP_WW4END3_12" + ], + [ + "CMT_PMV_EE4C0", + "CMT_TOP_EE4C0_12" + ], + [ + "CMT_PMV_FAN4", + "CMT_TOP_FAN4_12" + ], + [ + "CMT_PMV_LOGIC_OUTS18", + "CMT_TOP_LOGIC_OUTS_L_B18_12" + ], + [ + "CMT_PMV_NW4END0", + "CMT_TOP_NW4END0_12" + ], + [ + "CMT_PMV_FAN2", + "CMT_TOP_FAN2_12" + ], + [ + "CMT_PMV_BYP7", + "CMT_TOP_BYP7_12" + ], + [ + "CMT_PMV_LH9", + "CMT_TOP_LH9_12" + ], + [ + "CMT_PMV_LH6", + "CMT_TOP_LH6_12" + ], + [ + "CMT_PMV_IMUX22", + "CMT_TOP_IMUX22_12" + ], + [ + "CMT_PMV_CLK0", + "CMT_TOP_CLK0_12" + ], + [ + "CMT_PMV_WW4A2", + "CMT_TOP_WW4A2_12" + ], + [ + "CMT_PMV_EE2A2", + "CMT_TOP_EE2A2_12" + ], + [ + "CMT_PMV_CLK1", + "CMT_TOP_CLK1_12" + ], + [ + "CMT_PMV_LH4", + "CMT_TOP_LH4_12" + ], + [ + "CMT_PMV_NE2A2", + "CMT_TOP_NE2A2_12" + ], + [ + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "CMT_TOP_OCLKDIV_12" + ], + [ + "CMT_PMV_EL1BEG2", + "CMT_TOP_EL1BEG2_12" + ], + [ + "CMT_PMV_WL1END0", + "CMT_TOP_WL1END0_12" + ], + [ + "CMT_PMV_LOGIC_OUTS17", + "CMT_TOP_LOGIC_OUTS_L_B17_12" + ], + [ + "CMT_PMV_SW4A1", + "CMT_TOP_SW4A1_12" + ], + [ + "CMT_PMV_IMUX2", + "CMT_TOP_IMUX2_12" + ], + [ + "CMT_PMV_EL1BEG3", + "CMT_TOP_EL1BEG3_12" + ], + [ + "CMT_PMV_EE4A0", + "CMT_TOP_EE4A0_12" + ], + [ + "CMT_PMV_IMUX34", + "CMT_TOP_IMUX34_12" + ], + [ + "CMT_PMV_IMUX42", + "CMT_TOP_IMUX42_12" + ], + [ + "CMT_PMV_IMUX9", + "CMT_TOP_IMUX9_12" + ], + [ + "CMT_PMV_IMUX27", + "CMT_TOP_IMUX27_12" + ], + [ + "CMT_PMV_ER1BEG3", + "CMT_TOP_ER1BEG3_12" + ], + [ + "CMT_PMV_SE4BEG1", + "CMT_TOP_SE4BEG1_12" + ], + [ + "CMT_PMV_IMUX45", + "CMT_TOP_IMUX45_12" + ], + [ + "CMT_PMV_IMUX10", + "CMT_TOP_IMUX10_12" + ], + [ + "CMT_PMV_WR1END2", + "CMT_TOP_WR1END2_12" + ], + [ + "CMT_PMV_EE4C2", + "CMT_TOP_EE4C2_12" + ], + [ + "CMT_PMV_SW2A2", + "CMT_TOP_SW2A2_12" + ], + [ + "CMT_PMV_EE4BEG0", + "CMT_TOP_EE4BEG0_12" + ], + [ + "CMT_PMV_EE4BEG1", + "CMT_TOP_EE4BEG1_12" + ], + [ + "CMT_PMV_EE2BEG3", + "CMT_TOP_EE2BEG3_12" + ], + [ + "CMT_PMV_IMUX13", + "CMT_TOP_IMUX13_12" + ], + [ + "CMT_PMV_ER1BEG2", + "CMT_TOP_ER1BEG2_12" + ], + [ + "CMT_PMV_IMUX8", + "CMT_TOP_IMUX8_12" + ], + [ + "CMT_PMV_IMUX1", + "CMT_TOP_IMUX1_12" + ], + [ + "CMT_PMV_EE4C1", + "CMT_TOP_EE4C1_12" + ], + [ + "CMT_PMV_SE4C1", + "CMT_TOP_SE4C1_12" + ], + [ + "CMT_PMV_FAN6", + "CMT_TOP_FAN6_12" + ], + [ + "CMT_PMV_CTRL0", + "CMT_TOP_CTRL0_12" + ], + [ + "CMT_PMV_SW4END2", + "CMT_TOP_SW4END2_12" + ], + [ + "CMT_PMV_WL1END3", + "CMT_TOP_WL1END3_12" + ], + [ + "CMT_PMV_NE4C3", + "CMT_TOP_NE4C3_12" + ], + [ + "CMT_PMV_LOGIC_OUTS15", + "CMT_TOP_LOGIC_OUTS_L_B15_12" + ], + [ + "CMT_PMV_LOGIC_OUTS10", + "CMT_TOP_LOGIC_OUTS_L_B10_12" + ], + [ + "CMT_PMV_IMUX15", + "CMT_TOP_IMUX15_12" + ], + [ + "CMT_PMV_SW4A2", + "CMT_TOP_SW4A2_12" + ], + [ + "CMT_PMV_LOGIC_OUTS2", + "CMT_TOP_LOGIC_OUTS_L_B2_12" + ], + [ + "CMT_PMV_IMUX36", + "CMT_TOP_IMUX36_12" + ], + [ + "CMT_PMV_LH2", + "CMT_TOP_LH2_12" + ] + ], + "tile_types": [ + "CMT_PMV", + "CMT_TOP_R_UPPER_T" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "CMT_TOP_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH6_3", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_LH1_3", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_LH12_3", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_LH7_3", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_3", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH3_3", + "VBRK_LH3" + ], + [ + "CMT_TOP_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_LH2_3", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_LH9_3", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH5_3", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH11_3", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_LH10_3", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH8_3", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EL1BEG1_3", + "VBRK_EL1BEG1" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CMT_PMV_NE4C0", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_PMV_BYP3", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_PMV_NW2A3", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_PMV_EE4B3", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_PMV_LH2", + "INT_INTERFACE_LH2" + ], + [ + "CMT_PMV_WW4B2", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_PMV_WW4C3", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_PMV_SE2A0", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_PMV_NE2A1", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_PMV_IMUX30", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_PMV_IMUX24", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_PMV_SW4A3", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_PMV_EE4BEG0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "L_TERM_INT_PHASER_TO_IO_OCLK", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_PMV_IMUX15", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_PMV_LOGIC_OUTS0", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "CMT_PMV_SW4END3", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_PMV_SW4A0", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_PMV_SE4C2", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_PMV_FAN5", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_PMV_FAN4", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_PMV_EE4B2", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_PMV_NW4END2", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_PMV_IMUX2", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_PMV_LOGIC_OUTS10", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "CMT_PMV_EE2A1", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_PMV_EE4BEG3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_PMV_SW4A2", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_PMV_LOGIC_OUTS17", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "CMT_PMV_WW2END2", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_PMV_SE2A1", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_PMV_WR1END0", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_PMV_EE4A1", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_PMV_NE4BEG1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "L_TERM_INT_PHASER_TO_IO_ICLK", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_PMV_IMUX28", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_PMV_IMUX27", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_PMV_EL1BEG1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_PMV_FAN3", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_PMV_SW2A3", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_PMV_IMUX44", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_PMV_IMUX0", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_PMV_IMUX8", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_PMV_SW4A1", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_PMV_FAN1", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_PMV_IMUX34", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_PMV_SW2A1", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_PMV_WW2END1", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_PMV_NE4BEG2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_PMV_WW2A0", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_PMV_EE4BEG2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_PMV_NE2A3", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_PMV_WW4B3", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_PMV_NE2A0", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_PMV_WW4B0", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_PMV_SE4C1", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_PMV_EE2A0", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_PMV_IMUX22", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_PMV_CLK0", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_PMV_FAN6", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_PMV_IMUX16", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_PMV_IMUX20", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_PMV_BYP6", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_PMV_IMUX36", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_PMV_EE4B1", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_PMV_NW2A1", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_PMV_WW2A3", + "INT_INTERFACE_WW2A3" + ], + [ + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_PMV_WW4C2", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_PMV_WR1END2", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_PMV_IMUX43", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_PMV_NW4A1", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_PMV_WR1END3", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_PMV_IMUX35", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_PMV_WL1END2", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_PMV_BYP0", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_PMV_EE4C2", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_PMV_IMUX23", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_PMV_EE2A2", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_PMV_SW2A0", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_PMV_BYP2", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_PMV_BYP4", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_PMV_SW4END0", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_PMV_IMUX18", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_PMV_WW2A2", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_PMV_IMUX41", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_PMV_LH3", + "INT_INTERFACE_LH3" + ], + [ + "CMT_PMV_SE2A2", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_PMV_IMUX13", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_PMV_SE4C3", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_PMV_BYP5", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_PMV_IMUX5", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_PMV_EE2A3", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_PMV_WW4A1", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_PMV_WW4A3", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_PMV_EE4C3", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_PMV_CTRL1", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_PMV_ER1BEG3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_PMV_LH11", + "INT_INTERFACE_LH11" + ], + [ + "CMT_PMV_IMUX1", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_PMV_IMUX10", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_PMV_LOGIC_OUTS19", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "CMT_PMV_IMUX14", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_PMV_LOGIC_OUTS8", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "CMT_PMV_SE4BEG1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_PMV_IMUX37", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_PMV_SE4BEG3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_PMV_IMUX31", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_PMV_LH12", + "INT_INTERFACE_LH12" + ], + [ + "CMT_PMV_NW4END1", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_PMV_EL1BEG2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_PMV_NW4A2", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_PMV_IMUX40", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_PMV_EE2BEG2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_PMV_WW2A1", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_PMV_SW4END1", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_PMV_LOGIC_OUTS23", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "CMT_PMV_WW4END0", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_PMV_EE4C0", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_PMV_SE2A3", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_PMV_IMUX32", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_PMV_LH9", + "INT_INTERFACE_LH9" + ], + [ + "CMT_PMV_WL1END0", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_PMV_WW4END3", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_PMV_IMUX29", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_PMV_WW4B1", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_PMV_EE4B0", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_PMV_IMUX39", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_PMV_SW4END2", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_PMV_IMUX17", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_PMV_LOGIC_OUTS7", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "CMT_PMV_WW2END3", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_PMV_EE4C1", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_PMV_BYP7", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_PMV_IMUX47", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_PMV_WL1END3", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_PMV_FAN2", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_PMV_ER1BEG1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_PMV_LOGIC_OUTS22", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "CMT_PMV_NW2A0", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_PMV_NW4A3", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_PMV_WW4A2", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_PMV_IMUX46", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_PMV_IMUX45", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_PMV_FAN0", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_PMV_LH10", + "INT_INTERFACE_LH10" + ], + [ + "CMT_PMV_WR1END1", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_PMV_WW2END0", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_PMV_LH7", + "INT_INTERFACE_LH7" + ], + [ + "CMT_PMV_EE2BEG1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_PMV_CTRL0", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_PMV_CLK1", + "INT_INTERFACE_CLK1" + ], + [ + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_PMV_IMUX19", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_PMV_SE4BEG0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_PMV_WW4C1", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_PMV_LOGIC_OUTS18", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "CMT_PMV_EE2BEG0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_PMV_WW4A0", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_PMV_NW2A2", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_PMV_LOGIC_OUTS21", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "CMT_PMV_NE2A2", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_PMV_EE4A3", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_PMV_NW4END3", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_PMV_IMUX6", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_PMV_EE4A2", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_PMV_NW4END0", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_PMV_NE4C1", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_PMV_NE4C3", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_PMV_IMUX21", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_PMV_IMUX7", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_PMV_LH6", + "INT_INTERFACE_LH6" + ], + [ + "CMT_PMV_EE2BEG3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_PMV_IMUX25", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_PMV_ER1BEG0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_PMV_LOGIC_OUTS20", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "CMT_PMV_LOGIC_OUTS13", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "CMT_PMV_LH8", + "INT_INTERFACE_LH8" + ], + [ + "CMT_PMV_LH4", + "INT_INTERFACE_LH4" + ], + [ + "CMT_PMV_EE4A0", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_PMV_IMUX3", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_PMV_ER1BEG2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_PMV_NE4BEG0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_PMV_EL1BEG3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_PMV_IMUX38", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_PMV_IMUX11", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_PMV_LOGIC_OUTS5", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "CMT_PMV_SE4BEG2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_PMV_LOGIC_OUTS15", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "CMT_PMV_WL1END1", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_PMV_IMUX26", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_PMV_WW4END2", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_PMV_IMUX33", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_PMV_LH1", + "INT_INTERFACE_LH1" + ], + [ + "CMT_PMV_FAN7", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_PMV_IMUX12", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_PMV_NE4C2", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_PMV_NE4BEG3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_PMV_SW2A2", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_PMV_IMUX42", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_PMV_LH5", + "INT_INTERFACE_LH5" + ], + [ + "CMT_PMV_EE4BEG1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_PMV_SE4C0", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_PMV_WW4C0", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_PMV_WW4END1", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_PMV_EL1BEG0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_PMV_IMUX9", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_PMV_LOGIC_OUTS16", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "CMT_PMV_LOGIC_OUTS2", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "CMT_PMV_IMUX4", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_PMV_NW4A0", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_PMV_BYP1", + "INT_INTERFACE_BYP1" + ] + ], + "tile_types": [ + "CMT_PMV_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLBLM_WW4A0", + "WW4A0" + ], + [ + "CLBLM_ER1BEG3", + "ER1BEG3" + ], + [ + "CLBLM_BYP3", + "BYP3" + ], + [ + "CLBLM_NE4BEG3", + "NE6BEG3" + ], + [ + "CLBLM_IMUX13", + "IMUX13" + ], + [ + "CLBLM_SE2A0", + "SE2A0" + ], + [ + "CLBLM_FAN7", + "FAN7" + ], + [ + "CLBLM_WW2END3", + "WW2END3" + ], + [ + "CLBLM_IMUX4", + "IMUX4" + ], + [ + "CLBLM_NW4A3", + "NW6A3" + ], + [ + "CLBLM_EE4BEG1", + "EE4BEG1" + ], + [ + "CLBLM_IMUX15", + "IMUX15" + ], + [ + "CLBLM_LH2", + "LH2" + ], + [ + "CLBLM_WW2END2", + "WW2END2" + ], + [ + "CLBLM_LOGIC_OUTS1", + "LOGIC_OUTS1" + ], + [ + "CLBLM_FAN1", + "FAN1" + ], + [ + "CLBLM_EL1BEG1", + "EL1BEG1" + ], + [ + "CLBLM_LH6", + "LH6" + ], + [ + "CLBLM_NE2A2", + "NE2A2" + ], + [ + "CLBLM_LOGIC_OUTS12", + "LOGIC_OUTS12" + ], + [ + "CLBLM_IMUX42", + "IMUX42" + ], + [ + "CLBLM_IMUX24", + "IMUX24" + ], + [ + "CLBLM_LOGIC_OUTS16", + "LOGIC_OUTS16" + ], + [ + "CLBLM_EE4C0", + "EE4C0" + ], + [ + "CLBLM_CTRL1", + "CTRL1" + ], + [ + "CLBLM_WL1END0", + "WL1END0" + ], + [ + "CLBLM_NE4C1", + "NE6E1" + ], + [ + "CLBLM_LOGIC_OUTS19", + "LOGIC_OUTS19" + ], + [ + "CLBLM_LOGIC_OUTS13", + "LOGIC_OUTS13" + ], + [ + "CLBLM_BYP2", + "BYP2" + ], + [ + "CLBLM_WW4END2", + "WW4END2" + ], + [ + "CLBLM_IMUX32", + "IMUX32" + ], + [ + "CLBLM_LOGIC_OUTS15", + "LOGIC_OUTS15" + ], + [ + "CLBLM_BYP6", + "BYP6" + ], + [ + "CLBLM_IMUX1", + "IMUX1" + ], + [ + "CLBLM_LOGIC_OUTS4", + "LOGIC_OUTS4" + ], + [ + "CLBLM_CTRL0", + "CTRL0" + ], + [ + "CLBLM_LOGIC_OUTS0", + "LOGIC_OUTS0" + ], + [ + "CLBLM_IMUX17", + "IMUX17" + ], + [ + "CLBLM_SE2A1", + "SE2A1" + ], + [ + "CLBLM_SE4BEG2", + "SE6BEG2" + ], + [ + "CLBLM_EE2A3", + "EE2A3" + ], + [ + "CLBLM_NE4C3", + "NE6E3" + ], + [ + "CLBLM_SW2A2", + "SW2END2" + ], + [ + "CLBLM_EE4A1", + "EE4A1" + ], + [ + "CLBLM_LOGIC_OUTS14", + "LOGIC_OUTS14" + ], + [ + "CLBLM_SW4A1", + "SW6A1" + ], + [ + "CLBLM_EE2BEG3", + "EE2BEG3" + ], + [ + "CLBLM_WW2END0", + "WW2END0" + ], + [ + "CLBLM_LOGIC_OUTS9", + "LOGIC_OUTS9" + ], + [ + "CLBLM_BYP4", + "BYP4" + ], + [ + "CLBLM_WW2A1", + "WW2A1" + ], + [ + "CLBLM_WW2A3", + "WW2A3" + ], + [ + "CLBLM_LOGIC_OUTS18", + "LOGIC_OUTS18" + ], + [ + "CLBLM_NW4END3", + "NW6END3" + ], + [ + "CLBLM_IMUX46", + "IMUX46" + ], + [ + "CLBLM_MONITOR_N", + "MONITOR_N" + ], + [ + "CLBLM_IMUX3", + "IMUX3" + ], + [ + "CLBLM_LOGIC_OUTS3", + "LOGIC_OUTS3" + ], + [ + "CLBLM_WL1END1", + "WL1END1" + ], + [ + "CLBLM_NW2A1", + "NW2END1" + ], + [ + "CLBLM_WR1END0", + "WR1END0" + ], + [ + "CLBLM_IMUX5", + "IMUX5" + ], + [ + "CLBLM_IMUX43", + "IMUX43" + ], + [ + "CLBLM_EE4C2", + "EE4C2" + ], + [ + "CLBLM_EE4B1", + "EE4B1" + ], + [ + "CLBLM_IMUX11", + "IMUX11" + ], + [ + "CLBLM_WW4B1", + "WW4B1" + ], + [ + "CLBLM_IMUX16", + "IMUX16" + ], + [ + "CLBLM_WR1END1", + "WR1END1" + ], + [ + "CLBLM_IMUX20", + "IMUX20" + ], + [ + "CLBLM_IMUX29", + "IMUX29" + ], + [ + "CLBLM_IMUX7", + "IMUX7" + ], + [ + "CLBLM_EL1BEG3", + "EL1BEG3" + ], + [ + "CLBLM_LOGIC_OUTS7", + "LOGIC_OUTS7" + ], + [ + "CLBLM_SE4C3", + "SE6E3" + ], + [ + "CLBLM_WL1END2", + "WL1END2" + ], + [ + "CLBLM_WW4B3", + "WW4B3" + ], + [ + "CLBLM_WW4END3", + "WW4END3" + ], + [ + "CLBLM_IMUX44", + "IMUX44" + ], + [ + "CLBLM_WW4END0", + "WW4END0" + ], + [ + "CLBLM_EE2A0", + "EE2A0" + ], + [ + "CLBLM_EE4B2", + "EE4B2" + ], + [ + "CLBLM_IMUX10", + "IMUX10" + ], + [ + "CLBLM_WW4A3", + "WW4A3" + ], + [ + "CLBLM_IMUX26", + "IMUX26" + ], + [ + "CLBLM_IMUX19", + "IMUX19" + ], + [ + "CLBLM_FAN0", + "FAN0" + ], + [ + "CLBLM_WW4C0", + "WW4C0" + ], + [ + "CLBLM_SW2A1", + "SW2END1" + ], + [ + "CLBLM_IMUX9", + "IMUX9" + ], + [ + "CLBLM_NE4BEG2", + "NE6BEG2" + ], + [ + "CLBLM_LOGIC_OUTS11", + "LOGIC_OUTS11" + ], + [ + "CLBLM_EL1BEG2", + "EL1BEG2" + ], + [ + "CLBLM_SW4END0", + "SW6END0" + ], + [ + "CLBLM_IMUX27", + "IMUX27" + ], + [ + "CLBLM_IMUX25", + "IMUX25" + ], + [ + "CLBLM_IMUX0", + "IMUX0" + ], + [ + "CLBLM_EE2BEG2", + "EE2BEG2" + ], + [ + "CLBLM_LH4", + "LH4" + ], + [ + "CLBLM_FAN3", + "FAN3" + ], + [ + "CLBLM_NW2A0", + "NW2END0" + ], + [ + "CLBLM_LOGIC_OUTS5", + "LOGIC_OUTS5" + ], + [ + "CLBLM_IMUX28", + "IMUX28" + ], + [ + "CLBLM_IMUX35", + "IMUX35" + ], + [ + "CLBLM_EL1BEG0", + "EL1BEG0" + ], + [ + "CLBLM_IMUX18", + "IMUX18" + ], + [ + "CLBLM_LH7", + "LH7" + ], + [ + "CLBLM_WW4END1", + "WW4END1" + ], + [ + "CLBLM_NW4A2", + "NW6A2" + ], + [ + "CLBLM_LOGIC_OUTS10", + "LOGIC_OUTS10" + ], + [ + "CLBLM_LOGIC_OUTS8", + "LOGIC_OUTS8" + ], + [ + "CLBLM_IMUX22", + "IMUX22" + ], + [ + "CLBLM_LH10", + "LH10" + ], + [ + "CLBLM_SE4BEG3", + "SE6BEG3" + ], + [ + "CLBLM_WR1END3", + "WR1END3" + ], + [ + "CLBLM_LOGIC_OUTS2", + "LOGIC_OUTS2" + ], + [ + "CLBLM_NW4A0", + "NW6A0" + ], + [ + "CLBLM_CLK1", + "CLK1" + ], + [ + "CLBLM_SW4END2", + "SW6END2" + ], + [ + "CLBLM_NW4A1", + "NW6A1" + ], + [ + "CLBLM_FAN5", + "FAN5" + ], + [ + "CLBLM_MONITOR_P", + "MONITOR_P" + ], + [ + "CLBLM_FAN4", + "FAN4" + ], + [ + "CLBLM_LOGIC_OUTS21", + "LOGIC_OUTS21" + ], + [ + "CLBLM_SW4A3", + "SW6A3" + ], + [ + "CLBLM_EE2BEG0", + "EE2BEG0" + ], + [ + "CLBLM_SE2A3", + "SE2A3" + ], + [ + "CLBLM_ER1BEG2", + "ER1BEG2" + ], + [ + "CLBLM_NE2A0", + "NE2A0" + ], + [ + "CLBLM_LOGIC_OUTS23", + "LOGIC_OUTS23" + ], + [ + "CLBLM_IMUX23", + "IMUX23" + ], + [ + "CLBLM_EE4C1", + "EE4C1" + ], + [ + "CLBLM_EE2A1", + "EE2A1" + ], + [ + "CLBLM_NW4END0", + "NW6END0" + ], + [ + "CLBLM_NE2A3", + "NE2A3" + ], + [ + "CLBLM_NE4C2", + "NE6E2" + ], + [ + "CLBLM_EE2BEG1", + "EE2BEG1" + ], + [ + "CLBLM_SE2A2", + "SE2A2" + ], + [ + "CLBLM_EE4A2", + "EE4A2" + ], + [ + "CLBLM_LH1", + "LH1" + ], + [ + "CLBLM_WW2A0", + "WW2A0" + ], + [ + "CLBLM_NW2A3", + "NW2END3" + ], + [ + "CLBLM_SW2A0", + "SW2END0" + ], + [ + "CLBLM_IMUX36", + "IMUX36" + ], + [ + "CLBLM_WW4B0", + "WW4B0" + ], + [ + "CLBLM_ER1BEG0", + "ER1BEG0" + ], + [ + "CLBLM_LH8", + "LH8" + ], + [ + "CLBLM_IMUX38", + "IMUX38" + ], + [ + "CLBLM_WW4C2", + "WW4C2" + ], + [ + "CLBLM_NW2A2", + "NW2END2" + ], + [ + "CLBLM_EE4B0", + "EE4B0" + ], + [ + "CLBLM_NE4C0", + "NE6E0" + ], + [ + "CLBLM_LOGIC_OUTS20", + "LOGIC_OUTS20" + ], + [ + "CLBLM_LH12", + "LH12" + ], + [ + "CLBLM_LH5", + "LH5" + ], + [ + "CLBLM_IMUX14", + "IMUX14" + ], + [ + "CLBLM_SW4END1", + "SW6END1" + ], + [ + "CLBLM_WL1END3", + "WL1END3" + ], + [ + "CLBLM_EE4BEG0", + "EE4BEG0" + ], + [ + "CLBLM_EE4C3", + "EE4C3" + ], + [ + "CLBLM_LOGIC_OUTS17", + "LOGIC_OUTS17" + ], + [ + "CLBLM_BYP0", + "BYP0" + ], + [ + "CLBLM_IMUX21", + "IMUX21" + ], + [ + "CLBLM_NE2A1", + "NE2A1" + ], + [ + "CLBLM_IMUX34", + "IMUX34" + ], + [ + "CLBLM_EE4A0", + "EE4A0" + ], + [ + "CLBLM_IMUX31", + "IMUX31" + ], + [ + "CLBLM_SW4END3", + "SW6END3" + ], + [ + "CLBLM_IMUX2", + "IMUX2" + ], + [ + "CLBLM_IMUX45", + "IMUX45" + ], + [ + "CLBLM_ER1BEG1", + "ER1BEG1" + ], + [ + "CLBLM_WW4C1", + "WW4C1" + ], + [ + "CLBLM_EE2A2", + "EE2A2" + ], + [ + "CLBLM_LH3", + "LH3" + ], + [ + "CLBLM_SE4C2", + "SE6E2" + ], + [ + "CLBLM_SW4A2", + "SW6A2" + ], + [ + "CLBLM_EE4B3", + "EE4B3" + ], + [ + "CLBLM_SE4BEG0", + "SE6BEG0" + ], + [ + "CLBLM_BYP1", + "BYP1" + ], + [ + "CLBLM_LOGIC_OUTS6", + "LOGIC_OUTS6" + ], + [ + "CLBLM_WW2END1", + "WW2END1" + ], + [ + "CLBLM_SE4C0", + "SE6E0" + ], + [ + "CLBLM_EE4BEG2", + "EE4BEG2" + ], + [ + "CLBLM_IMUX8", + "IMUX8" + ], + [ + "CLBLM_IMUX41", + "IMUX41" + ], + [ + "CLBLM_FAN6", + "FAN6" + ], + [ + "CLBLM_LH11", + "LH11" + ], + [ + "CLBLM_IMUX12", + "IMUX12" + ], + [ + "CLBLM_IMUX47", + "IMUX47" + ], + [ + "CLBLM_BYP7", + "BYP7" + ], + [ + "CLBLM_IMUX30", + "IMUX30" + ], + [ + "CLBLM_IMUX40", + "IMUX40" + ], + [ + "CLBLM_WW4A2", + "WW4A2" + ], + [ + "CLBLM_CLK0", + "CLK0" + ], + [ + "CLBLM_IMUX6", + "IMUX6" + ], + [ + "CLBLM_IMUX39", + "IMUX39" + ], + [ + "CLBLM_EE4BEG3", + "EE4BEG3" + ], + [ + "CLBLM_NE4BEG1", + "NE6BEG1" + ], + [ + "CLBLM_LOGIC_OUTS22", + "LOGIC_OUTS22" + ], + [ + "CLBLM_SW4A0", + "SW6A0" + ], + [ + "CLBLM_LH9", + "LH9" + ], + [ + "CLBLM_IMUX33", + "IMUX33" + ], + [ + "CLBLM_BYP5", + "BYP5" + ], + [ + "CLBLM_IMUX37", + "IMUX37" + ], + [ + "CLBLM_EE4A3", + "EE4A3" + ], + [ + "CLBLM_SE4BEG1", + "SE6BEG1" + ], + [ + "CLBLM_WR1END2", + "WR1END2" + ], + [ + "CLBLM_SE4C1", + "SE6E1" + ], + [ + "CLBLM_WW4B2", + "WW4B2" + ], + [ + "CLBLM_SW2A3", + "SW2END3" + ], + [ + "CLBLM_NE4BEG0", + "NE6BEG0" + ], + [ + "CLBLM_WW4C3", + "WW4C3" + ], + [ + "CLBLM_WW2A2", + "WW2A2" + ], + [ + "CLBLM_NW4END2", + "NW6END2" + ], + [ + "CLBLM_WW4A1", + "WW4A1" + ], + [ + "CLBLM_FAN2", + "FAN2" + ], + [ + "CLBLM_NW4END1", + "NW6END1" + ] + ], + "tile_types": [ + "CLBLM_R", + "INT_R" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW2A2_5", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A0_5", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END2_5", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SE4C1_5", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SW4END3_5", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NW4END0_5", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW2A0_5", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WL1END3_5", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SE2A2_5", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4B3_5", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_LH3_5", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE2A2_5", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_5", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4C2_5", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2A0_5", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG1_5", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A1_5", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4A2_5", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END1_5", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW4C0_5", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_5", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4END3_5", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4BEG0_5", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH6_5", + "VBRK_LH6" + ], + [ + "CMT_TOP_EL1BEG1_5", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_EE4A1_5", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NW4A2_5", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4A3_5", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NE4BEG0_5", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW2A2_5", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C3_5", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH7_5", + "VBRK_LH7" + ], + [ + "CMT_TOP_WW4B2_5", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH5_5", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4A1_5", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4A0_5", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C1_5", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW2A0_5", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WL1END2_5", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_SE4C0_5", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SW4END2_5", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END1_5", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG0_5", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_WR1END1_5", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EE4C1_5", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG0_5", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NW4END2_5", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_EE2BEG2_5", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4B1_5", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_ER1BEG3_5", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NW2A1_5", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B0_5", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END2_5", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A1_5", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE2A3_5", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_LH11_5", + "VBRK_LH11" + ], + [ + "CMT_TOP_WL1END0_5", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SW4END0_5", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4BEG3_5", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C3_5", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_SE4BEG1_5", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NE2A2_5", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B0_5", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_ER1BEG2_5", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_5", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NE2A0_5", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4BEG1_5", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE2A3_5", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG2_5", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_LH9_5", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4END2_5", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4BEG2_5", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2END0_5", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_ER1BEG0_5", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH4_5", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2A1_5", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE2BEG1_5", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_NE4BEG3_5", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C0_5", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH8_5", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4A3_5", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2BEG0_5", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_NE2A1_5", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C3_5", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WL1END1_5", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW4A1_5", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_5", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4A0_5", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4END1_5", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH2_5", + "VBRK_LH2" + ], + [ + "CMT_TOP_NE2A3_5", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW4A0_5", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4A3_5", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4C0_5", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_LH12_5", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH1_5", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_5", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_ER1BEG1_5", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2BEG3_5", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH10_5", + "VBRK_LH10" + ], + [ + "CMT_TOP_SW2A2_5", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WR1END3_5", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NW4END1_5", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NW4A1_5", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WW4C2_5", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WR1END0_5", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4END3_5", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW4A3_5", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4END0_5", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW2A3_5", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4C2_5", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG3_5", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW2A3_5", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4A2_5", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4BEG3_5", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE4B2_5", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW2A0_5", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SE2A0_5", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SE4BEG2_5", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B1_5", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4C1_5", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C2_5", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4C3_5", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_EL1BEG2_5", + "VBRK_EL1BEG2" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX21_2", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX33_2", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX34_2", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX35_2", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX26_2", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX16_2", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX36_2", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_CTRL0_2", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX4_2", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX37_2", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX41_2", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX11_2", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP0_2", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_BYP5_2", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_CTRL1_2", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX32_2", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX39_2", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX8_2", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_BYP4_2", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX20_2", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN4_2", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_BYP3_2", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX22_2", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX30_2", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX14_2", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX5_2", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX17_2", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_LOGIC_OUTS_B9_2", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX31_2", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_FAN2_2", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_LOGIC_OUTS_B10_2", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX43_2", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_FAN7_2", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX2_2", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_FAN1_2", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_FAN0_2", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_CLK1_2", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_BYP1_2", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_BYP2_2", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX44_2", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX42_2", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX40_2", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX38_2", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX0_2", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX6_2", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX15_2", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_CLK0_2", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX19_2", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX45_2", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX3_2", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX29_2", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_FAN5_2", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX12_2", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX10_2", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX13_2", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX9_2", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX1_2", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX23_2", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_FAN3_2", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX25_2", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B14_2", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX7_2", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX24_2", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_FAN6_2", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX18_2", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX27_2", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_BYP6_2", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX47_2", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_LOGIC_OUTS_B19_2", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX28_2", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX46_2", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP7_2", + "VBRK_EXT_BYP7" + ] + ], + "tile_types": [ + "GTX_COMMON", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + 9 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_9" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_9" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_9" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_9" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_9" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_9" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_9" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_9" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_9" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_9" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_9" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_9" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_9" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_9" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_9" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_9" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_9" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_9" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_9" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_9" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_9" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_9" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_9" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_9" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_9" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_9" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_9" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_9" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_9" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_9" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_9" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_9" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_9" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_9" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_9" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_9" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_9" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_9" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_9" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_9" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_9" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_9" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_9" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_9" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_9" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_9" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_9" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_9" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_9" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_9" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_9" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_9" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_9" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_9" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_9" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_9" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_9" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_9" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_9" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_9" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_9" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_9" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_9" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_9" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_9" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_9" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_9" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_9" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_9" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_9" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_9" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_9" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_9" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_9" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_9" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_9" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_9" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_9" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_9" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_9" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_9" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_9" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_9" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_9" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_9" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_9" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_9" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_9" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_9" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_9" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_9" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_9" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_9" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_9" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_9" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_9" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_9" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_9" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_9" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_9" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_9" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_9" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_9" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_9" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_9" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_9" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_9" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_9" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_9" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_9" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_9" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_9" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_9" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_9" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_9" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_9" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_9" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_9" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_9" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_9" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_9" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_9" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_9" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_9" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_MID_FUJI2" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "CLK_HROW_SE2A0_2", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_WW2A0_2", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4C1_2", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_EE4BEG0_2", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_NE4BEG3_2", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_SE2A1_2", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_WW4END3_2", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_SW2A1_2", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_BUFG_IMUX44_2", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_EE4A2_2", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_WW4B0_2", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_EE4C2_2", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_BUFG_IMUX15_2", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_NW2A2_2", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_LH8_2", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_EE4B1_2", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_WL1END2_2", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_SE4BEG1_2", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_BUFG_IMUX16_2", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_NW4A3_2", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WW2END2_2", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_BUFG_IMUX10_2", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_BUFG_IMUX37_2", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_BUFG_IMUX14_2", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_BUFG_IMUX28_2", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_WW4END1_2", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_LH12_2", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_EE2BEG3_2", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_BUFG_IMUX3_2", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_BUFG_IMUX25_2", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_NE4C0_2", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_WW4B2_2", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_SE4C2_2", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_SW4END3_2", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_FAN7_2", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_BUFG_IMUX17_2", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_BUFG_IMUX20_2", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_NW4END3_2", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_BUFG_IMUX19_2", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_BUFG_IMUX30_2", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_LH10_2", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_SW4END1_2", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_WW2A3_2", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_BYP4_2", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_FAN2_2", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_BUFG_IMUX2_2", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_LH1_2", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_NE2A3_2", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_EE4BEG2_2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_BYP0_2", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_WW4B3_2", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B7_2", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CLK_HROW_WR1END2_2", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_BUFG_IMUX36_2", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_ER1BEG3_2", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_BYP5_2", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_SW4END0_2", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_SE4C0_2", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_NE4BEG2_2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_LH2_2", + "INT_INTERFACE_LH2" + ], + [ + "CLK_BUFG_IMUX42_2", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_WW4END2_2", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_NW4END0_2", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_NW4A1_2", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B0_2", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CLK_HROW_WW4C3_2", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_BYP1_2", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_NE2A1_2", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_ER1BEG1_2", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B3_2", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CLK_HROW_SE2A2_2", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_BUFG_IMUX13_2", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_EL1BEG1_2", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_NW2A0_2", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_SW2A2_2", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_EE4A1_2", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_NE4BEG1_2", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_BUFG_IMUX18_2", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B1_2", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CLK_HROW_WW4B1_2", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_NE2A2_2", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_SE4BEG2_2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_BUFG_IMUX39_2", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_BUFG_IMUX1_2", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_WW4A0_2", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_BYP7_2", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_WW2END3_2", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_WW4A3_2", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_SW4END2_2", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_WW2END0_2", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_BUFG_IMUX23_2", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_EE2BEG2_2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_WW4A1_2", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_NW4A2_2", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_BYP3_2", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_LH6_2", + "INT_INTERFACE_LH6" + ], + [ + "CLK_BUFG_IMUX33_2", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_BUFG_IMUX43_2", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_NW2A3_2", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_EE2A1_2", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_LH9_2", + "INT_INTERFACE_LH9" + ], + [ + "CLK_BUFG_IMUX45_2", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_BUFG_IMUX31_2", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_EE4BEG1_2", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_WR1END3_2", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_WL1END0_2", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_CLK0_2", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_WR1END1_2", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_FAN5_2", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_WW4C0_2", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_BUFG_IMUX46_2", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_SE4C3_2", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_NW4END1_2", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_LH3_2", + "INT_INTERFACE_LH3" + ], + [ + "CLK_BUFG_IMUX47_2", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_WW2A1_2", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_SE4C1_2", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_CTRL0_2", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_FAN1_2", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_EL1BEG0_2", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_NE4C1_2", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_BUFG_IMUX5_2", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_BYP6_2", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_NE4BEG0_2", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_FAN6_2", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_SW2A3_2", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_BUFG_IMUX40_2", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_EL1BEG3_2", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_NE4C3_2", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_BYP2_2", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_SW4A1_2", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_WW4C1_2", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_NW2A1_2", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_LH11_2", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_SW4A3_2", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_BUFG_IMUX32_2", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_EE2A2_2", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_BUFG_IMUX24_2", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_FAN3_2", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_SW2A0_2", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE2A0_2", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_SW4A0_2", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_BUFG_IMUX29_2", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_WW4END0_2", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_LH7_2", + "INT_INTERFACE_LH7" + ], + [ + "CLK_BUFG_IMUX12_2", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_SE4BEG0_2", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_EE2A3_2", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B2_2", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CLK_HROW_SE4BEG3_2", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_WW2END1_2", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_BUFG_IMUX9_2", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_BUFG_IMUX27_2", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_EE4B3_2", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_BUFG_IMUX11_2", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_EE2BEG0_2", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_CTRL1_2", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_EE4A0_2", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_BUFG_IMUX4_2", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_NW4END2_2", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_SE2A3_2", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_FAN4_2", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_EE2BEG1_2", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_BUFG_IMUX22_2", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_NE2A0_2", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_EE4BEG3_2", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_WR1END0_2", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_ER1BEG0_2", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B5_2", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CLK_BUFG_IMUX7_2", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_WW4A2_2", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_BUFG_IMUX35_2", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_SW4A2_2", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_BUFG_IMUX34_2", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_WW2A2_2", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_EE4C0_2", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_BUFG_IMUX8_2", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_BUFG_IMUX26_2", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_BUFG_IMUX21_2", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_BUFG_IMUX0_2", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_EE4B2_2", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_CLK1_2", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_EL1BEG2_2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_WW4C2_2", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_EE4A3_2", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_EE4B0_2", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_FAN0_2", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B4_2", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CLK_HROW_ER1BEG2_2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_WL1END3_2", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_WL1END1_2", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_BUFG_IMUX41_2", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_NE4C2_2", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_LH4_2", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_NW4A0_2", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_BUFG_IMUX38_2", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_LH5_2", + "INT_INTERFACE_LH5" + ], + [ + "CLK_BUFG_IMUX6_2", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B6_2", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CLK_HROW_EE4C3_2", + "INT_INTERFACE_EE4C3" + ] + ], + "tile_types": [ + "CLK_BUFG_BOT_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 8 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SW4A3_2", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_CLK0_2", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_EE4BEG2_2", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX32_2", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_EL1BEG2_2", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_FAN7_2", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_EE4BEG0_2", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_IMUX14_2", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_EE2BEG0_2", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_LH12_2", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX43_2", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_SW2A0_2", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_EE4C0_2", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_FAN6_2", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_WR1END1_2", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_LH9_2", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_WW4END0_2", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX10_2", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_EL1BEG0_2", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_IMUX31_2", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_EE2A2_2", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_SE2A2_2", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX18_2", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_EE2BEG3_2", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_EE2A3_2", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_IMUX45_2", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX26_2", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX21_2", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_SE4C2_2", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WW4B2_2", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_WL1END3_2", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_IMUX35_2", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_IMUX0_2", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_IMUX25_2", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_WW4B1_2", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_WW2END2_2", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_IMUX37_2", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_EE4B1_2", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_EE2A0_2", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_IMUX3_2", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_LH2_2", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EE4A3_2", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_BYP5_2", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_IMUX36_2", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW2A1_2", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_SW4END1_2", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_SE2A3_2", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_WW4END2_2", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX33_2", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_WR1END2_2", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SE4BEG0_2", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_CTRL0_2", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_LH8_2", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_SW2A2_2", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_WW2A3_2", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_BYP3_2", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_EE4A2_2", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_FAN4_2", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_NE4C2_2", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_NW4END3_2", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_IMUX8_2", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_NE4BEG3_2", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NE2A0_2", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX44_2", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_BYP4_2", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_NE4BEG0_2", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX27_2", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX38_2", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_NW4END1_2", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SE2A0_2", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_BYP0_2", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX29_2", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_WW4A2_2", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_LH6_2", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_NW4A1_2", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_FAN0_2", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_WL1END2_2", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_SE2A1_2", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_IMUX30_2", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_WW4A0_2", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_WW4END1_2", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_SW4A1_2", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_NE4BEG2_2", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_IMUX15_2", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_EE4BEG3_2", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_WW2A1_2", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_FAN5_2", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_IMUX41_2", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_EE4A1_2", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_LH3_2", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX47_2", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_SE4C1_2", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_WW4A3_2", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW4B3_2", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_EL1BEG1_2", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_FAN1_2", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_BYP6_2", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX20_2", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_LH11_2", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_WR1END0_2", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_NW2A3_2", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_BYP2_2", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_WW4C2_2", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_EL1BEG3_2", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_BYP1_2", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SW4A2_2", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_IMUX7_2", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_NW4END0_2", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX6_2", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX28_2", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX19_2", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_EE4C2_2", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_LH1_2", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NE2A1_2", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_NW4A3_2", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_LH7_2", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_NE4C1_2", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_WW2END3_2", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_EE2BEG2_2", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_NE4C0_2", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_NW2A0_2", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_WW2END1_2", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_WW2A0_2", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_IMUX4_2", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_EE4C1_2", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX22_2", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX12_2", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_NE4C3_2", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_WW4END3_2", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX17_2", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX13_2", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_EE4BEG1_2", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_WW4C0_2", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX9_2", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX40_2", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_SE4BEG1_2", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE4B0_2", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WW4B0_2", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_WL1END0_2", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_SE4C0_2", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_SE4BEG3_2", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_SE4BEG2_2", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_SW4END3_2", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_ER1BEG1_2", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_IMUX24_2", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_EE4A0_2", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_NW4A0_2", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_CTRL1_2", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_WW4C1_2", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_IMUX34_2", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_FAN3_2", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_NE2A3_2", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX2_2", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_IMUX39_2", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_LH10_2", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_ER1BEG0_2", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_IMUX5_2", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WL1END1_2", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_IMUX1_2", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX16_2", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WR1END3_2", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_EE4B3_2", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_EE4C3_2", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE2A1_2", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_SW4A0_2", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_NW2A2_2", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_NE2A2_2", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_SW2A3_2", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_ER1BEG2_2", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_ER1BEG3_2", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_FAN2_2", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_SE4C3_2", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_LH4_2", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_NW4END2_2", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_NE4BEG1_2", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_WW2END0_2", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_EE4B2_2", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_WW4C3_2", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX46_2", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_SW4END0_2", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX23_2", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW2A2_2", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_IMUX42_2", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_NW4A2_2", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_BYP7_2", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_CLK1_2", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_SW4END2_2", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_LH5_2", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_WW4A1_2", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_EE2BEG1_2", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_NW2A1_2", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_IMUX11_2", + "VFRAME_IMUX11" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "PCIE_BYP3_R_13", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_WW4C3_13", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_WL1END2_13", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_13", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_BYP1_R_13", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_NE2A3_13", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_IMUX31_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_WL1END1_13", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_SE4BEG2_13", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_EL1BEG2_13", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_WW4C0_13", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_13", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_13", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_13", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_FAN5_R_13", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_MONITOR_N_13", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_IMUX22_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_EE4A2_13", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_LH5_13", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_LH1_13", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_EE4B0_13", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_SW4A2_13", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_WW4B0_13", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_13", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_WW4B1_13", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_LH2_13", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_EE2A3_13", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_IMUX9_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_FAN7_R_13", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_WW4END1_13", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_FAN0_R_13", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_LH6_13", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_CTRL1_R_13", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_IMUX47_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_IMUX39_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_13", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_NW4A3_13", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_EE4BEG0_13", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX14_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_13", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_BYP0_R_13", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_13", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_SW2A1_13", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_SE2A1_13", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_WW2END2_13", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_FAN1_R_13", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_LH4_13", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_IMUX34_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_EE4A3_13", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_EE2A0_13", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_WW4END3_13", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_IMUX38_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_WW2A1_13", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_IMUX12_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_SE2A2_13", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_NW4END0_13", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_IMUX25_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_EE4B3_13", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_EE2A2_13", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_EE4BEG3_13", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_EE4C0_13", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX24_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_IMUX10_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_BYP4_R_13", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_NW2A2_13", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_WW2A2_13", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_IMUX44_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_NW2A1_13", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_EE4A1_13", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_13", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_13", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_WW2A0_13", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_WW4A0_13", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_FAN4_R_13", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_13", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_13", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_NW2A3_13", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_NW4END2_13", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_IMUX37_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_SE4BEG3_13", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_EE4BEG1_13", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_NE2A0_13", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_NE4C0_13", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_IMUX26_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_CTRL0_R_13", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_IMUX29_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_IMUX30_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_WR1END2_13", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_LH8_13", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4C3_13", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_SE4C3_13", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_IMUX33_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_13", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_SW4A0_13", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_EL1BEG3_13", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_NW4END3_13", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_LH11_13", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_ER1BEG3_13", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_EE2BEG2_13", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_NW4A1_13", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_IMUX0_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_IMUX1_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_IMUX4_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_EE4B2_13", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_LH10_13", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_IMUX21_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_EE4C2_13", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_NE4C1_13", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_IMUX17_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_BYP5_R_13", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_NW4END1_13", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_SW4END1_13", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_EL1BEG1_13", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_FAN2_R_13", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_SE4C1_13", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_IMUX2_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_EE4C1_13", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_13", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_WW4B3_13", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_WW4C2_13", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_EE4BEG2_13", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_ER1BEG1_13", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_NE4BEG1_13", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_SE4C0_13", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_ER1BEG2_13", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_IMUX11_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_WW4A1_13", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_WR1END1_13", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_13", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_IMUX45_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_13", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_13", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_WW2END1_13", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_LH9_13", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_MONITOR_P_13", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_13", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_IMUX20_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_NE2A1_13", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_IMUX3_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_IMUX16_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_SE4BEG0_13", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_WR1END0_13", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_NW2A0_13", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_SW4END0_13", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_SE2A0_13", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_SE4BEG1_13", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_13", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_IMUX35_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_WR1END3_13", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_FAN6_R_13", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_BYP6_R_13", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_IMUX28_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_WW4B2_13", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_SW2A3_13", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_13", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_BYP2_R_13", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_SW2A0_13", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX8_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_IMUX23_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_SE2A3_13", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_SW4A3_13", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_CLK1_R_13", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_SE4C2_13", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_NW4A0_13", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_IMUX7_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_IMUX42_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_WL1END3_13", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_SW4A1_13", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_IMUX5_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_IMUX40_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_SW4END3_13", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_WW4C1_13", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_EE4B1_13", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_IMUX19_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_IMUX6_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_IMUX13_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_SW4END2_13", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_IMUX32_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_FAN3_R_13", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_EE2BEG0_13", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_13", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_IMUX43_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_EE2A1_13", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_IMUX41_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_SW2A2_13", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_NE4C3_13", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_EE2BEG1_13", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX46_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_IMUX36_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_NW4A2_13", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_EE4A0_13", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_NE2A2_13", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_WW4A3_13", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_LH12_13", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_WW2END0_13", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_IMUX15_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_IMUX18_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_NE4BEG3_13", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_WW4A2_13", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_WW2A3_13", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_13", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_EE2BEG3_13", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_NE4BEG0_13", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_13", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_EL1BEG0_13", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_BYP7_R_13", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_WW2END3_13", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_LH3_13", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_LH7_13", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_CLK0_R_13", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_WL1END0_13", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_WW4END2_13", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_ER1BEG0_13", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_NE4C2_13", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_IMUX27_R_13", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_WW4END0_13", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_13", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_NE4BEG2_13", + "INT_INTERFACE_NE4BEG2" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_LOGIC_OUTS4", + "LOGIC_OUTS4" + ], + [ + "INT_INTERFACE_FAN4", + "FAN4" + ], + [ + "INT_INTERFACE_NW4END3", + "NW6END3" + ], + [ + "INT_INTERFACE_WW2A2", + "WW2A2" + ], + [ + "INT_INTERFACE_SE4BEG3", + "SE6BEG3" + ], + [ + "INT_INTERFACE_NW4A0", + "NW6A0" + ], + [ + "INT_INTERFACE_SE4C0", + "SE6E0" + ], + [ + "INT_INTERFACE_SW4A0", + "SW6A0" + ], + [ + "INT_INTERFACE_EE4BEG3", + "EE4BEG3" + ], + [ + "INT_INTERFACE_BRAM_IMUX4", + "IMUX4" + ], + [ + "INT_INTERFACE_CLK1", + "CLK1" + ], + [ + "INT_INTERFACE_BRAM_IMUX22", + "IMUX22" + ], + [ + "INT_INTERFACE_WW2END1", + "WW2END1" + ], + [ + "INT_INTERFACE_WW4END3", + "WW4END3" + ], + [ + "INT_INTERFACE_FAN7", + "FAN7" + ], + [ + "INT_INTERFACE_LH5", + "LH5" + ], + [ + "INT_INTERFACE_WR1END0", + "WR1END0" + ], + [ + "INT_INTERFACE_SE4C2", + "SE6E2" + ], + [ + "INT_INTERFACE_EE2BEG0", + "EE2BEG0" + ], + [ + "INT_INTERFACE_SE2A2", + "SE2A2" + ], + [ + "INT_INTERFACE_BYP0", + "BYP0" + ], + [ + "INT_INTERFACE_BRAM_IMUX16", + "IMUX16" + ], + [ + "INT_INTERFACE_BYP5", + "BYP5" + ], + [ + "INT_INTERFACE_WL1END0", + "WL1END0" + ], + [ + "INT_INTERFACE_WW4A3", + "WW4A3" + ], + [ + "INT_INTERFACE_LH4", + "LH4" + ], + [ + "INT_INTERFACE_WW4C3", + "WW4C3" + ], + [ + "INT_INTERFACE_BRAM_IMUX19", + "IMUX19" + ], + [ + "INT_INTERFACE_SW2A2", + "SW2END2" + ], + [ + "INT_INTERFACE_EE2BEG3", + "EE2BEG3" + ], + [ + "INT_INTERFACE_BRAM_IMUX33", + "IMUX33" + ], + [ + "INT_INTERFACE_LH11", + "LH11" + ], + [ + "INT_INTERFACE_LOGIC_OUTS12", + "LOGIC_OUTS12" + ], + [ + "INT_INTERFACE_BRAM_IMUX9", + "IMUX9" + ], + [ + "INT_INTERFACE_WW2A3", + "WW2A3" + ], + [ + "INT_INTERFACE_NE2A0", + "NE2A0" + ], + [ + "INT_INTERFACE_NE4BEG3", + "NE6BEG3" + ], + [ + "INT_INTERFACE_SE4C3", + "SE6E3" + ], + [ + "INT_INTERFACE_BRAM_IMUX42", + "IMUX42" + ], + [ + "INT_INTERFACE_SE2A3", + "SE2A3" + ], + [ + "INT_INTERFACE_ER1BEG3", + "ER1BEG3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS2", + "LOGIC_OUTS2" + ], + [ + "INT_INTERFACE_WW4END0", + "WW4END0" + ], + [ + "INT_INTERFACE_BRAM_IMUX43", + "IMUX43" + ], + [ + "INT_INTERFACE_EE4A2", + "EE4A2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS14", + "LOGIC_OUTS14" + ], + [ + "INT_INTERFACE_WW2END2", + "WW2END2" + ], + [ + "INT_INTERFACE_WW4END2", + "WW4END2" + ], + [ + "INT_INTERFACE_NW4END2", + "NW6END2" + ], + [ + "INT_INTERFACE_BRAM_IMUX32", + "IMUX32" + ], + [ + "INT_INTERFACE_SW2A0", + "SW2END0" + ], + [ + "INT_INTERFACE_BRAM_IMUX25", + "IMUX25" + ], + [ + "INT_INTERFACE_EE4C1", + "EE4C1" + ], + [ + "INT_INTERFACE_EE2BEG2", + "EE2BEG2" + ], + [ + "INT_INTERFACE_NE4BEG2", + "NE6BEG2" + ], + [ + "INT_INTERFACE_WL1END2", + "WL1END2" + ], + [ + "INT_INTERFACE_NW2A1", + "NW2END1" + ], + [ + "INT_INTERFACE_WW4A2", + "WW4A2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS6", + "LOGIC_OUTS6" + ], + [ + "INT_INTERFACE_SW4END3", + "SW6END3" + ], + [ + "INT_INTERFACE_NW2A0", + "NW2END0" + ], + [ + "INT_INTERFACE_EE4B2", + "EE4B2" + ], + [ + "INT_INTERFACE_BRAM_IMUX13", + "IMUX13" + ], + [ + "INT_INTERFACE_EE4C2", + "EE4C2" + ], + [ + "INT_INTERFACE_BRAM_IMUX28", + "IMUX28" + ], + [ + "INT_INTERFACE_ER1BEG0", + "ER1BEG0" + ], + [ + "INT_INTERFACE_BRAM_IMUX10", + "IMUX10" + ], + [ + "INT_INTERFACE_EE2A1", + "EE2A1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS15", + "LOGIC_OUTS15" + ], + [ + "INT_INTERFACE_WW2END0", + "WW2END0" + ], + [ + "INT_INTERFACE_WW4C0", + "WW4C0" + ], + [ + "INT_INTERFACE_NE2A2", + "NE2A2" + ], + [ + "INT_INTERFACE_EE4B1", + "EE4B1" + ], + [ + "INT_INTERFACE_LH3", + "LH3" + ], + [ + "INT_INTERFACE_BYP4", + "BYP4" + ], + [ + "INT_INTERFACE_NW2A3", + "NW2END3" + ], + [ + "INT_INTERFACE_SE4BEG0", + "SE6BEG0" + ], + [ + "INT_INTERFACE_BRAM_IMUX2", + "IMUX2" + ], + [ + "INT_INTERFACE_CTRL0", + "CTRL0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS23", + "LOGIC_OUTS23" + ], + [ + "INT_INTERFACE_LH8", + "LH8" + ], + [ + "INT_INTERFACE_BRAM_IMUX31", + "IMUX31" + ], + [ + "INT_INTERFACE_LOGIC_OUTS21", + "LOGIC_OUTS21" + ], + [ + "INT_INTERFACE_BRAM_IMUX3", + "IMUX3" + ], + [ + "INT_INTERFACE_ER1BEG2", + "ER1BEG2" + ], + [ + "INT_INTERFACE_BRAM_IMUX6", + "IMUX6" + ], + [ + "INT_INTERFACE_FAN5", + "FAN5" + ], + [ + "INT_INTERFACE_LH6", + "LH6" + ], + [ + "INT_INTERFACE_CTRL1", + "CTRL1" + ], + [ + "INT_INTERFACE_BYP7", + "BYP7" + ], + [ + "INT_INTERFACE_SW4END2", + "SW6END2" + ], + [ + "INT_INTERFACE_WW4B3", + "WW4B3" + ], + [ + "INT_INTERFACE_BRAM_IMUX35", + "IMUX35" + ], + [ + "INT_INTERFACE_BRAM_IMUX0", + "IMUX0" + ], + [ + "INT_INTERFACE_BRAM_IMUX12", + "IMUX12" + ], + [ + "INT_INTERFACE_WR1END3", + "WR1END3" + ], + [ + "INT_INTERFACE_BRAM_IMUX29", + "IMUX29" + ], + [ + "INT_INTERFACE_SE2A1", + "SE2A1" + ], + [ + "INT_INTERFACE_SW4A2", + "SW6A2" + ], + [ + "INT_INTERFACE_SW2A3", + "SW2END3" + ], + [ + "INT_INTERFACE_WW2A1", + "WW2A1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS10", + "LOGIC_OUTS10" + ], + [ + "INT_INTERFACE_EE4C3", + "EE4C3" + ], + [ + "INT_INTERFACE_SE4C1", + "SE6E1" + ], + [ + "INT_INTERFACE_EE4A1", + "EE4A1" + ], + [ + "INT_INTERFACE_EE4B3", + "EE4B3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS18", + "LOGIC_OUTS18" + ], + [ + "INT_INTERFACE_EL1BEG0", + "EL1BEG0" + ], + [ + "INT_INTERFACE_FAN2", + "FAN2" + ], + [ + "INT_INTERFACE_BYP1", + "BYP1" + ], + [ + "INT_INTERFACE_WL1END3", + "WL1END3" + ], + [ + "INT_INTERFACE_WR1END2", + "WR1END2" + ], + [ + "INT_INTERFACE_WW4B1", + "WW4B1" + ], + [ + "INT_INTERFACE_BRAM_IMUX30", + "IMUX30" + ], + [ + "INT_INTERFACE_EE2A3", + "EE2A3" + ], + [ + "INT_INTERFACE_WW4A1", + "WW4A1" + ], + [ + "INT_INTERFACE_EE4B0", + "EE4B0" + ], + [ + "INT_INTERFACE_BRAM_IMUX34", + "IMUX34" + ], + [ + "INT_INTERFACE_LOGIC_OUTS5", + "LOGIC_OUTS5" + ], + [ + "INT_INTERFACE_LOGIC_OUTS3", + "LOGIC_OUTS3" + ], + [ + "INT_INTERFACE_NW4A2", + "NW6A2" + ], + [ + "INT_INTERFACE_EL1BEG3", + "EL1BEG3" + ], + [ + "INT_INTERFACE_FAN6", + "FAN6" + ], + [ + "INT_INTERFACE_NE4C2", + "NE6E2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS8", + "LOGIC_OUTS8" + ], + [ + "INT_INTERFACE_BRAM_IMUX5", + "IMUX5" + ], + [ + "INT_INTERFACE_BRAM_IMUX18", + "IMUX18" + ], + [ + "INT_INTERFACE_NW2A2", + "NW2END2" + ], + [ + "INT_INTERFACE_SE4BEG1", + "SE6BEG1" + ], + [ + "INT_INTERFACE_BRAM_IMUX27", + "IMUX27" + ], + [ + "INT_INTERFACE_BRAM_IMUX24", + "IMUX24" + ], + [ + "INT_INTERFACE_SW4A1", + "SW6A1" + ], + [ + "INT_INTERFACE_SW2A1", + "SW2END1" + ], + [ + "INT_INTERFACE_BRAM_IMUX26", + "IMUX26" + ], + [ + "INT_INTERFACE_SE4BEG2", + "SE6BEG2" + ], + [ + "INT_INTERFACE_FAN3", + "FAN3" + ], + [ + "INT_INTERFACE_BRAM_IMUX39", + "IMUX39" + ], + [ + "INT_INTERFACE_BRAM_IMUX46", + "IMUX46" + ], + [ + "INT_INTERFACE_ER1BEG1", + "ER1BEG1" + ], + [ + "INT_INTERFACE_BRAM_IMUX7", + "IMUX7" + ], + [ + "INT_INTERFACE_EE4A0", + "EE4A0" + ], + [ + "INT_INTERFACE_WW4A0", + "WW4A0" + ], + [ + "INT_INTERFACE_NW4A1", + "NW6A1" + ], + [ + "INT_INTERFACE_WW4B0", + "WW4B0" + ], + [ + "INT_INTERFACE_SW4END1", + "SW6END1" + ], + [ + "INT_INTERFACE_WW4C1", + "WW4C1" + ], + [ + "INT_INTERFACE_NE4C3", + "NE6E3" + ], + [ + "INT_INTERFACE_BYP3", + "BYP3" + ], + [ + "INT_INTERFACE_EE4BEG0", + "EE4BEG0" + ], + [ + "INT_INTERFACE_MONITOR_P", + "MONITOR_P" + ], + [ + "INT_INTERFACE_WW4END1", + "WW4END1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS17", + "LOGIC_OUTS17" + ], + [ + "INT_INTERFACE_NE4C1", + "NE6E1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS13", + "LOGIC_OUTS13" + ], + [ + "INT_INTERFACE_WW2END3", + "WW2END3" + ], + [ + "INT_INTERFACE_EL1BEG1", + "EL1BEG1" + ], + [ + "INT_INTERFACE_NW4A3", + "NW6A3" + ], + [ + "INT_INTERFACE_BRAM_IMUX44", + "IMUX44" + ], + [ + "INT_INTERFACE_SW4A3", + "SW6A3" + ], + [ + "INT_INTERFACE_NE4BEG0", + "NE6BEG0" + ], + [ + "INT_INTERFACE_CLK0", + "CLK0" + ], + [ + "INT_INTERFACE_BRAM_IMUX15", + "IMUX15" + ], + [ + "INT_INTERFACE_EE2A0", + "EE2A0" + ], + [ + "INT_INTERFACE_BRAM_IMUX38", + "IMUX38" + ], + [ + "INT_INTERFACE_BRAM_IMUX21", + "IMUX21" + ], + [ + "INT_INTERFACE_NE4BEG1", + "NE6BEG1" + ], + [ + "INT_INTERFACE_LH2", + "LH2" + ], + [ + "INT_INTERFACE_BRAM_IMUX41", + "IMUX41" + ], + [ + "INT_INTERFACE_SW4END0", + "SW6END0" + ], + [ + "INT_INTERFACE_BRAM_IMUX47", + "IMUX47" + ], + [ + "INT_INTERFACE_BRAM_IMUX45", + "IMUX45" + ], + [ + "INT_INTERFACE_NE2A3", + "NE2A3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS9", + "LOGIC_OUTS9" + ], + [ + "INT_INTERFACE_NE2A1", + "NE2A1" + ], + [ + "INT_INTERFACE_BRAM_IMUX36", + "IMUX36" + ], + [ + "INT_INTERFACE_BYP2", + "BYP2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS11", + "LOGIC_OUTS11" + ], + [ + "INT_INTERFACE_BRAM_IMUX14", + "IMUX14" + ], + [ + "INT_INTERFACE_WL1END1", + "WL1END1" + ], + [ + "INT_INTERFACE_EE4BEG1", + "EE4BEG1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS19", + "LOGIC_OUTS19" + ], + [ + "INT_INTERFACE_WW2A0", + "WW2A0" + ], + [ + "INT_INTERFACE_EL1BEG2", + "EL1BEG2" + ], + [ + "INT_INTERFACE_WR1END1", + "WR1END1" + ], + [ + "INT_INTERFACE_WW4B2", + "WW4B2" + ], + [ + "INT_INTERFACE_EE2BEG1", + "EE2BEG1" + ], + [ + "INT_INTERFACE_BRAM_IMUX11", + "IMUX11" + ], + [ + "INT_INTERFACE_FAN0", + "FAN0" + ], + [ + "INT_INTERFACE_BRAM_IMUX17", + "IMUX17" + ], + [ + "INT_INTERFACE_BRAM_IMUX23", + "IMUX23" + ], + [ + "INT_INTERFACE_LH10", + "LH10" + ], + [ + "INT_INTERFACE_BRAM_IMUX1", + "IMUX1" + ], + [ + "INT_INTERFACE_BRAM_IMUX8", + "IMUX8" + ], + [ + "INT_INTERFACE_BRAM_IMUX40", + "IMUX40" + ], + [ + "INT_INTERFACE_LH7", + "LH7" + ], + [ + "INT_INTERFACE_LH9", + "LH9" + ], + [ + "INT_INTERFACE_EE4A3", + "EE4A3" + ], + [ + "INT_INTERFACE_BRAM_IMUX20", + "IMUX20" + ], + [ + "INT_INTERFACE_EE4BEG2", + "EE4BEG2" + ], + [ + "INT_INTERFACE_MONITOR_N", + "MONITOR_N" + ], + [ + "INT_INTERFACE_LOGIC_OUTS22", + "LOGIC_OUTS22" + ], + [ + "INT_INTERFACE_LOGIC_OUTS16", + "LOGIC_OUTS16" + ], + [ + "INT_INTERFACE_LOGIC_OUTS20", + "LOGIC_OUTS20" + ], + [ + "INT_INTERFACE_WW4C2", + "WW4C2" + ], + [ + "INT_INTERFACE_NW4END0", + "NW6END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS0", + "LOGIC_OUTS0" + ], + [ + "INT_INTERFACE_EE2A2", + "EE2A2" + ], + [ + "INT_INTERFACE_BYP6", + "BYP6" + ], + [ + "INT_INTERFACE_EE4C0", + "EE4C0" + ], + [ + "INT_INTERFACE_BRAM_IMUX37", + "IMUX37" + ], + [ + "INT_INTERFACE_LH12", + "LH12" + ], + [ + "INT_INTERFACE_LH1", + "LH1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS7", + "LOGIC_OUTS7" + ], + [ + "INT_INTERFACE_LOGIC_OUTS1", + "LOGIC_OUTS1" + ], + [ + "INT_INTERFACE_SE2A0", + "SE2A0" + ], + [ + "INT_INTERFACE_NW4END1", + "NW6END1" + ], + [ + "INT_INTERFACE_NE4C0", + "NE6E0" + ], + [ + "INT_INTERFACE_FAN1", + "FAN1" + ] + ], + "tile_types": [ + "BRAM_INT_INTERFACE_R", + "INT_R" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX44_4", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX34_4", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX28_4", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_LOGIC_OUTS_B11_4", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_IMUX6_4", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B22_4", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX36_4", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX4_4", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_CTRL1_4", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX29_4", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX30_4", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX35_4", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX12_4", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX45_4", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_LOGIC_OUTS_B14_4", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX7_4", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX10_4", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX39_4", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX23_4", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX33_4", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_LOGIC_OUTS_B15_4", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_FAN4_4", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_LOGIC_OUTS_B0_4", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_LOGIC_OUTS_B23_4", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_BYP6_4", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX27_4", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B8_4", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX15_4", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_FAN0_4", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_BYP3_4", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B13_4", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_IMUX5_4", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B12_4", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_LOGIC_OUTS_B16_4", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_CTRL0_4", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX9_4", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX11_4", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX19_4", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX21_4", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX17_4", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX16_4", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_LOGIC_OUTS_B9_4", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_FAN7_4", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX37_4", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_LOGIC_OUTS_B19_4", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B17_4", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B5_4", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_BYP0_4", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX26_4", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX22_4", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B6_4", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX2_4", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_BYP1_4", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B7_4", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_BYP2_4", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX8_4", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_FAN5_4", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX38_4", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX43_4", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_CLK1_4", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX41_4", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B18_4", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX1_4", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_FAN3_4", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN1_4", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B4_4", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B10_4", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_LOGIC_OUTS_B3_4", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_LOGIC_OUTS_B20_4", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX20_4", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX24_4", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_FAN2_4", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX46_4", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX13_4", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX3_4", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX42_4", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX18_4", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX0_4", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_BYP4_4", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX32_4", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN6_4", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX14_4", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_BYP7_4", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B1_4", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX31_4", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX40_4", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B2_4", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX25_4", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_BYP5_4", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX47_4", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_CLK0_4", + "VBRK_EXT_CLK0" + ] + ], + "tile_types": [ + "GTX_CHANNEL_1", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "PCIE_EE2A2_14", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_IMUX44_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_IMUX27_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_EE4BEG3_14", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_NE2A0_14", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_EL1BEG2_14", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_WL1END1_14", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_WR1END3_14", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_14", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_14", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_IMUX5_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_NE2A2_14", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_SE4C0_14", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_IMUX33_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_IMUX37_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_14", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_NW4END1_14", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_14", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_LH4_14", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_EE4B2_14", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_EE4BEG0_14", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_FAN3_R_14", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX18_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_SE2A3_14", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_NW4A0_14", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_14", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_14", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_WW4C3_14", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_FAN5_R_14", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_IMUX1_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_WW2END2_14", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_WL1END2_14", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_IMUX3_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_SW4END3_14", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_BYP1_R_14", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_IMUX26_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_LH8_14", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_WW4B0_14", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_SW4END1_14", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_ER1BEG1_14", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_LH12_14", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_EE4A1_14", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_EE2A3_14", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_ER1BEG3_14", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_IMUX30_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_IMUX23_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_14", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_14", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_NE2A1_14", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_SW4END2_14", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_WR1END2_14", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_WW2END0_14", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_IMUX13_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_WW4C0_14", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_NW2A3_14", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_IMUX20_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_EE4C1_14", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_NE4C2_14", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_14", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_EE4C2_14", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_ER1BEG2_14", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_SW2A0_14", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX17_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_SE2A1_14", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_SW2A3_14", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX22_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_IMUX12_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_SE2A0_14", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_BYP3_R_14", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_BYP4_R_14", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_14", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_14", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_BYP5_R_14", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_IMUX0_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_WW4A1_14", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_NE2A3_14", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_EE4B0_14", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX19_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_WW4B2_14", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_LH7_14", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_SE4BEG2_14", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_IMUX47_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_WW4END1_14", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_CTRL1_R_14", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_NE4BEG2_14", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_FAN1_R_14", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_EL1BEG3_14", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_IMUX34_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_14", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_EE2BEG2_14", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_SE4C1_14", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_BYP2_R_14", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_CTRL0_R_14", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_WL1END3_14", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_14", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_NW4END3_14", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_FAN6_R_14", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_SE2A2_14", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_EE4BEG1_14", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_NW4A3_14", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_FAN0_R_14", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_IMUX15_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_WW2END3_14", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_EE4C3_14", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_SW4A3_14", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_NW4A2_14", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_NW2A0_14", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_SE4BEG1_14", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_EE4A3_14", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_EE4C0_14", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_EL1BEG1_14", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_EE4B3_14", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_LH6_14", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_FAN7_R_14", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_WW4END3_14", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_SE4BEG0_14", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_SW2A2_14", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_IMUX10_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_WW4B1_14", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_WW4END0_14", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_IMUX41_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_EE2BEG1_14", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX42_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_LH3_14", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_NE4BEG3_14", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_SW4A1_14", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_NE4BEG0_14", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_LH9_14", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_NW2A2_14", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_IMUX24_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_NE4C1_14", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_IMUX31_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_LH10_14", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_IMUX29_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_IMUX14_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_WL1END0_14", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_14", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_IMUX36_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_IMUX7_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_IMUX43_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_WW2A0_14", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_IMUX45_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_14", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_FAN4_R_14", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_FAN2_R_14", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_NW4END0_14", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_WW4A2_14", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_IMUX4_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_WW4B3_14", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_WW2A2_14", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_WW2A1_14", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_NE4C3_14", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_SE4C3_14", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_14", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_IMUX9_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_IMUX8_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_14", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_WW4A3_14", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_EE2A1_14", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_IMUX32_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_EE4BEG2_14", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_EE4B1_14", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_SW4A0_14", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_LH1_14", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_IMUX16_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_NW4A1_14", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_SW4END0_14", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_14", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_EE4A0_14", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_WR1END0_14", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_14", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_BYP0_R_14", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_EL1BEG0_14", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_BYP6_R_14", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_BYP7_R_14", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_IMUX21_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_WW4A0_14", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_IMUX38_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_LH5_14", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_IMUX11_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_WW4C2_14", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_IMUX28_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_WW2A3_14", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_LH11_14", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_EE4A2_14", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_WW4C1_14", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_14", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_IMUX40_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_14", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_EE2BEG3_14", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_EE2A0_14", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_NE4BEG1_14", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_SE4BEG3_14", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_EE2BEG0_14", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_CLK0_R_14", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_IMUX2_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_IMUX25_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_14", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_NW4END2_14", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_CLK1_R_14", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_IMUX6_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_NE4C0_14", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_WR1END1_14", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_14", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_LH2_14", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_IMUX46_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_SW4A2_14", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_SE4C2_14", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_14", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_SW2A1_14", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_WW2END1_14", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_IMUX39_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_WW4END2_14", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_NW2A1_14", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_ER1BEG0_14", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_IMUX35_R_14", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "CFG_CENTER_NW4A1_13", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WW4B2_13", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_WW2END1_13", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_NE4C3_13", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_NE2A0_13", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_NW4END3_13", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW4END1_13", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_SW2A1_13", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_NE2A1_13", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_EL1BEG3_13", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_LH7_13", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WL1END2_13", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_EE4BEG3_13", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG1_13", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW4B0_13", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_SW4A1_13", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_WW4B3_13", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_WW4A0_13", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_WW4A3_13", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_ER1BEG2_13", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_EL1BEG0_13", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_NW4A3_13", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_EL1BEG2_13", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_NW4END1_13", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_EE2BEG2_13", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW4C1_13", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SE4BEG1_13", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_NW4A2_13", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NW2A0_13", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_SW4END0_13", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_SW2A2_13", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WR1END3_13", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_WW4END2_13", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_LH4_13", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_WL1END0_13", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SE4C1_13", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_LH9_13", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NE4C0_13", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_NW4A0_13", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_WR1END1_13", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SE2A0_13", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE4A0_13", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4B1_13", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EE4C3_13", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_SW2A0_13", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_EE2A2_13", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WW2END2_13", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_LH10_13", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_EE4B2_13", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_ER1BEG0_13", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NW2A2_13", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_WW4END3_13", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_ER1BEG1_13", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_EE4A1_13", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_SE4BEG3_13", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_WL1END1_13", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_SE4BEG0_13", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SW4END3_13", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_WW2A3_13", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_LH12_13", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_LH8_13", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_SE4C2_13", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_NE4BEG1_13", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_EE4A3_13", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_NE2A2_13", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE4C1_13", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_LH2_13", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_EE4BEG2_13", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SW4A3_13", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_WW2A2_13", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_EE2A0_13", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW4C3_13", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4C0_13", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NW2A3_13", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE4C1_13", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WR1END0_13", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH6_13", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_EE2BEG1_13", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NW4END0_13", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_NE4BEG0_13", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_SE2A2_13", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_NW4END2_13", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WL1END3_13", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_LH3_13", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_NE4BEG2_13", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_WW2A0_13", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WW2END3_13", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_EE4B0_13", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH11_13", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EE4C2_13", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_SE4BEG2_13", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW4C2_13", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_SW4END1_13", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_SW4END2_13", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SE2A1_13", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW4B1_13", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_NE4BEG3_13", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW2A1_13", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WW2END0_13", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_SW2A3_13", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_WW4END0_13", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EE2BEG3_13", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_LH5_13", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE4BEG0_13", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NE2A3_13", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_SW4A0_13", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE2A1_13", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_SE4C0_13", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_NE4C2_13", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE2BEG0_13", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4A2_13", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WR1END2_13", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_EE2A3_13", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NW2A1_13", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C0_13", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EE4A2_13", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SE4C3_13", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_EE4B3_13", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SE2A3_13", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_ER1BEG3_13", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_SW4A2_13", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_LH1_13", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_WW4A1_13", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EE4BEG1_13", + "INT_FEEDTHRU_2_EE4BEG1" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_1_LH3", + "INT_FEEDTHRU_1_LH3" + ], + [ + "INT_FEEDTHRU_1_ER1BEG1", + "INT_FEEDTHRU_1_ER1BEG1" + ], + [ + "INT_FEEDTHRU_1_SW2A1", + "INT_FEEDTHRU_1_SW2A1" + ], + [ + "INT_FEEDTHRU_1_NE2A2", + "INT_FEEDTHRU_1_NE2A2" + ], + [ + "INT_FEEDTHRU_1_NE2A1", + "INT_FEEDTHRU_1_NE2A1" + ], + [ + "INT_FEEDTHRU_1_NW4END0", + "INT_FEEDTHRU_1_NW4END0" + ], + [ + "INT_FEEDTHRU_1_SE2A1", + "INT_FEEDTHRU_1_SE2A1" + ], + [ + "INT_FEEDTHRU_1_LH9", + "INT_FEEDTHRU_1_LH9" + ], + [ + "INT_FEEDTHRU_1_SE4BEG1", + "INT_FEEDTHRU_1_SE4BEG1" + ], + [ + "INT_FEEDTHRU_1_NE4C2", + "INT_FEEDTHRU_1_NE4C2" + ], + [ + "INT_FEEDTHRU_1_WL1END1", + "INT_FEEDTHRU_1_WL1END1" + ], + [ + "INT_FEEDTHRU_1_LH2", + "INT_FEEDTHRU_1_LH2" + ], + [ + "INT_FEEDTHRU_1_SE2A0", + "INT_FEEDTHRU_1_SE2A0" + ], + [ + "INT_FEEDTHRU_1_NE4BEG2", + "INT_FEEDTHRU_1_NE4BEG2" + ], + [ + "INT_FEEDTHRU_1_WW2END2", + "INT_FEEDTHRU_1_WW2END2" + ], + [ + "INT_FEEDTHRU_1_NW4END1", + "INT_FEEDTHRU_1_NW4END1" + ], + [ + "INT_FEEDTHRU_1_SW2A0", + "INT_FEEDTHRU_1_SW2A0" + ], + [ + "INT_FEEDTHRU_1_LH7", + "INT_FEEDTHRU_1_LH7" + ], + [ + "INT_FEEDTHRU_1_WW4B2", + "INT_FEEDTHRU_1_WW4B2" + ], + [ + "INT_FEEDTHRU_1_NE4C3", + "INT_FEEDTHRU_1_NE4C3" + ], + [ + "INT_FEEDTHRU_1_ER1BEG3", + "INT_FEEDTHRU_1_ER1BEG3" + ], + [ + "INT_FEEDTHRU_1_SW4END3", + "INT_FEEDTHRU_1_SW4END3" + ], + [ + "INT_FEEDTHRU_1_LH5", + "INT_FEEDTHRU_1_LH5" + ], + [ + "INT_FEEDTHRU_1_EE4C1", + "INT_FEEDTHRU_1_EE4C1" + ], + [ + "INT_FEEDTHRU_1_EE2A1", + "INT_FEEDTHRU_1_EE2A1" + ], + [ + "INT_FEEDTHRU_1_NW4A0", + "INT_FEEDTHRU_1_NW4A0" + ], + [ + "INT_FEEDTHRU_1_WW2END1", + "INT_FEEDTHRU_1_WW2END1" + ], + [ + "INT_FEEDTHRU_1_NE2A0", + "INT_FEEDTHRU_1_NE2A0" + ], + [ + "INT_FEEDTHRU_1_NW2A1", + "INT_FEEDTHRU_1_NW2A1" + ], + [ + "INT_FEEDTHRU_1_WW4A0", + "INT_FEEDTHRU_1_WW4A0" + ], + [ + "INT_FEEDTHRU_1_EE4BEG1", + "INT_FEEDTHRU_1_EE4BEG1" + ], + [ + "INT_FEEDTHRU_1_WW4B0", + "INT_FEEDTHRU_1_WW4B0" + ], + [ + "INT_FEEDTHRU_1_WW4C2", + "INT_FEEDTHRU_1_WW4C2" + ], + [ + "INT_FEEDTHRU_1_WW4END2", + "INT_FEEDTHRU_1_WW4END2" + ], + [ + "INT_FEEDTHRU_1_SE2A3", + "INT_FEEDTHRU_1_SE2A3" + ], + [ + "INT_FEEDTHRU_1_EE2A0", + "INT_FEEDTHRU_1_EE2A0" + ], + [ + "INT_FEEDTHRU_1_WL1END0", + "INT_FEEDTHRU_1_WL1END0" + ], + [ + "INT_FEEDTHRU_1_SE2A2", + "INT_FEEDTHRU_1_SE2A2" + ], + [ + "INT_FEEDTHRU_1_EE2BEG3", + "INT_FEEDTHRU_1_EE2BEG3" + ], + [ + "INT_FEEDTHRU_1_SE4BEG2", + "INT_FEEDTHRU_1_SE4BEG2" + ], + [ + "INT_FEEDTHRU_1_WR1END1", + "INT_FEEDTHRU_1_WR1END1" + ], + [ + "INT_FEEDTHRU_1_WW4END3", + "INT_FEEDTHRU_1_WW4END3" + ], + [ + "INT_FEEDTHRU_1_ER1BEG0", + "INT_FEEDTHRU_1_ER1BEG0" + ], + [ + "INT_FEEDTHRU_1_SW4END2", + "INT_FEEDTHRU_1_SW4END2" + ], + [ + "INT_FEEDTHRU_1_MONITOR_N", + "INT_FEEDTHRU_1_MONITOR_N" + ], + [ + "INT_FEEDTHRU_1_LH6", + "INT_FEEDTHRU_1_LH6" + ], + [ + "INT_FEEDTHRU_1_WW4C0", + "INT_FEEDTHRU_1_WW4C0" + ], + [ + "INT_FEEDTHRU_1_WW4END0", + "INT_FEEDTHRU_1_WW4END0" + ], + [ + "INT_FEEDTHRU_1_NW2A0", + "INT_FEEDTHRU_1_NW2A0" + ], + [ + "INT_FEEDTHRU_1_SW4A0", + "INT_FEEDTHRU_1_SW4A0" + ], + [ + "INT_FEEDTHRU_1_SE4BEG0", + "INT_FEEDTHRU_1_SE4BEG0" + ], + [ + "INT_FEEDTHRU_1_SW4END0", + "INT_FEEDTHRU_1_SW4END0" + ], + [ + "INT_FEEDTHRU_1_EE4C0", + "INT_FEEDTHRU_1_EE4C0" + ], + [ + "INT_FEEDTHRU_1_EE2BEG0", + "INT_FEEDTHRU_1_EE2BEG0" + ], + [ + "INT_FEEDTHRU_1_MONITOR_P", + "INT_FEEDTHRU_1_MONITOR_P" + ], + [ + "INT_FEEDTHRU_1_WW2A0", + "INT_FEEDTHRU_1_WW2A0" + ], + [ + "INT_FEEDTHRU_1_EE4B3", + "INT_FEEDTHRU_1_EE4B3" + ], + [ + "INT_FEEDTHRU_1_SW4A1", + "INT_FEEDTHRU_1_SW4A1" + ], + [ + "INT_FEEDTHRU_1_EE4A1", + "INT_FEEDTHRU_1_EE4A1" + ], + [ + "INT_FEEDTHRU_1_EE2BEG1", + "INT_FEEDTHRU_1_EE2BEG1" + ], + [ + "INT_FEEDTHRU_1_WW2END3", + "INT_FEEDTHRU_1_WW2END3" + ], + [ + "INT_FEEDTHRU_1_NE4C0", + "INT_FEEDTHRU_1_NE4C0" + ], + [ + "INT_FEEDTHRU_1_WW4A3", + "INT_FEEDTHRU_1_WW4A3" + ], + [ + "INT_FEEDTHRU_1_EE4C2", + "INT_FEEDTHRU_1_EE4C2" + ], + [ + "INT_FEEDTHRU_1_EE2A3", + "INT_FEEDTHRU_1_EE2A3" + ], + [ + "INT_FEEDTHRU_1_EL1BEG3", + "INT_FEEDTHRU_1_EL1BEG3" + ], + [ + "INT_FEEDTHRU_1_LH1", + "INT_FEEDTHRU_1_LH1" + ], + [ + "INT_FEEDTHRU_1_EE4B2", + "INT_FEEDTHRU_1_EE4B2" + ], + [ + "INT_FEEDTHRU_1_SE4C2", + "INT_FEEDTHRU_1_SE4C2" + ], + [ + "INT_FEEDTHRU_1_EE4A3", + "INT_FEEDTHRU_1_EE4A3" + ], + [ + "INT_FEEDTHRU_1_WW4END1", + "INT_FEEDTHRU_1_WW4END1" + ], + [ + "INT_FEEDTHRU_1_LH4", + "INT_FEEDTHRU_1_LH4" + ], + [ + "INT_FEEDTHRU_1_EL1BEG2", + "INT_FEEDTHRU_1_EL1BEG2" + ], + [ + "INT_FEEDTHRU_1_NW4A1", + "INT_FEEDTHRU_1_NW4A1" + ], + [ + "INT_FEEDTHRU_1_WW4B3", + "INT_FEEDTHRU_1_WW4B3" + ], + [ + "INT_FEEDTHRU_1_EE4B1", + "INT_FEEDTHRU_1_EE4B1" + ], + [ + "INT_FEEDTHRU_1_WW4C1", + "INT_FEEDTHRU_1_WW4C1" + ], + [ + "INT_FEEDTHRU_1_NW2A2", + "INT_FEEDTHRU_1_NW2A2" + ], + [ + "INT_FEEDTHRU_1_SW4A3", + "INT_FEEDTHRU_1_SW4A3" + ], + [ + "INT_FEEDTHRU_1_EE4BEG3", + "INT_FEEDTHRU_1_EE4BEG3" + ], + [ + "INT_FEEDTHRU_1_EE2A2", + "INT_FEEDTHRU_1_EE2A2" + ], + [ + "INT_FEEDTHRU_1_LH12", + "INT_FEEDTHRU_1_LH12" + ], + [ + "INT_FEEDTHRU_1_LH11", + "INT_FEEDTHRU_1_LH11" + ], + [ + "INT_FEEDTHRU_1_WR1END3", + "INT_FEEDTHRU_1_WR1END3" + ], + [ + "INT_FEEDTHRU_1_WW4C3", + "INT_FEEDTHRU_1_WW4C3" + ], + [ + "INT_FEEDTHRU_1_LH10", + "INT_FEEDTHRU_1_LH10" + ], + [ + "INT_FEEDTHRU_1_EE2BEG2", + "INT_FEEDTHRU_1_EE2BEG2" + ], + [ + "INT_FEEDTHRU_1_WL1END2", + "INT_FEEDTHRU_1_WL1END2" + ], + [ + "INT_FEEDTHRU_1_SW2A3", + "INT_FEEDTHRU_1_SW2A3" + ], + [ + "INT_FEEDTHRU_1_WR1END2", + "INT_FEEDTHRU_1_WR1END2" + ], + [ + "INT_FEEDTHRU_1_WW4B1", + "INT_FEEDTHRU_1_WW4B1" + ], + [ + "INT_FEEDTHRU_1_WW2END0", + "INT_FEEDTHRU_1_WW2END0" + ], + [ + "INT_FEEDTHRU_1_EL1BEG1", + "INT_FEEDTHRU_1_EL1BEG1" + ], + [ + "INT_FEEDTHRU_1_EE4B0", + "INT_FEEDTHRU_1_EE4B0" + ], + [ + "INT_FEEDTHRU_1_LH8", + "INT_FEEDTHRU_1_LH8" + ], + [ + "INT_FEEDTHRU_1_NW4END2", + "INT_FEEDTHRU_1_NW4END2" + ], + [ + "INT_FEEDTHRU_1_EE4BEG0", + "INT_FEEDTHRU_1_EE4BEG0" + ], + [ + "INT_FEEDTHRU_1_EE4C3", + "INT_FEEDTHRU_1_EE4C3" + ], + [ + "INT_FEEDTHRU_1_NE4BEG3", + "INT_FEEDTHRU_1_NE4BEG3" + ], + [ + "INT_FEEDTHRU_1_ER1BEG2", + "INT_FEEDTHRU_1_ER1BEG2" + ], + [ + "INT_FEEDTHRU_1_NE4BEG0", + "INT_FEEDTHRU_1_NE4BEG0" + ], + [ + "INT_FEEDTHRU_1_WW2A2", + "INT_FEEDTHRU_1_WW2A2" + ], + [ + "INT_FEEDTHRU_1_NW4A2", + "INT_FEEDTHRU_1_NW4A2" + ], + [ + "INT_FEEDTHRU_1_EE4A0", + "INT_FEEDTHRU_1_EE4A0" + ], + [ + "INT_FEEDTHRU_1_WW4A2", + "INT_FEEDTHRU_1_WW4A2" + ], + [ + "INT_FEEDTHRU_1_SE4C3", + "INT_FEEDTHRU_1_SE4C3" + ], + [ + "INT_FEEDTHRU_1_WW2A1", + "INT_FEEDTHRU_1_WW2A1" + ], + [ + "INT_FEEDTHRU_1_NW4A3", + "INT_FEEDTHRU_1_NW4A3" + ], + [ + "INT_FEEDTHRU_1_NE2A3", + "INT_FEEDTHRU_1_NE2A3" + ], + [ + "INT_FEEDTHRU_1_WR1END0", + "INT_FEEDTHRU_1_WR1END0" + ], + [ + "INT_FEEDTHRU_1_NW2A3", + "INT_FEEDTHRU_1_NW2A3" + ], + [ + "INT_FEEDTHRU_1_NE4BEG1", + "INT_FEEDTHRU_1_NE4BEG1" + ], + [ + "INT_FEEDTHRU_1_SW4A2", + "INT_FEEDTHRU_1_SW4A2" + ], + [ + "INT_FEEDTHRU_1_SW4END1", + "INT_FEEDTHRU_1_SW4END1" + ], + [ + "INT_FEEDTHRU_1_NW4END3", + "INT_FEEDTHRU_1_NW4END3" + ], + [ + "INT_FEEDTHRU_1_WL1END3", + "INT_FEEDTHRU_1_WL1END3" + ], + [ + "INT_FEEDTHRU_1_EE4BEG2", + "INT_FEEDTHRU_1_EE4BEG2" + ], + [ + "INT_FEEDTHRU_1_SE4BEG3", + "INT_FEEDTHRU_1_SE4BEG3" + ], + [ + "INT_FEEDTHRU_1_NE4C1", + "INT_FEEDTHRU_1_NE4C1" + ], + [ + "INT_FEEDTHRU_1_WW2A3", + "INT_FEEDTHRU_1_WW2A3" + ], + [ + "INT_FEEDTHRU_1_EL1BEG0", + "INT_FEEDTHRU_1_EL1BEG0" + ], + [ + "INT_FEEDTHRU_1_SE4C1", + "INT_FEEDTHRU_1_SE4C1" + ], + [ + "INT_FEEDTHRU_1_SW2A2", + "INT_FEEDTHRU_1_SW2A2" + ], + [ + "INT_FEEDTHRU_1_EE4A2", + "INT_FEEDTHRU_1_EE4A2" + ], + [ + "INT_FEEDTHRU_1_WW4A1", + "INT_FEEDTHRU_1_WW4A1" + ], + [ + "INT_FEEDTHRU_1_SE4C0", + "INT_FEEDTHRU_1_SE4C0" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_1", + "INT_FEEDTHRU_1" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE2A0_10", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WL1END0_10", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_EE4BEG1_10", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_WL1END3_10", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4C0_10", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_ER1BEG1_10", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SE2A2_10", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4C2_10", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_EE4B3_10", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NW2A3_10", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_EE2A3_10", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_EE4BEG3_10", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WW2A0_10", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_NE2A2_10", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE4B0_10", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WW2END2_10", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_WW2A1_10", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_NE4C1_10", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_LH4_10", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SW4A1_10", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_EE4A3_10", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE2BEG0_10", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_SE2A1_10", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW2A3_10", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_NW4A0_10", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_WR1END0_10", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_SE4C0_10", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_LH5_10", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_WW4B0_10", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_WW4END3_10", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WL1END1_10", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_EE4A0_10", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_WW4A3_10", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NE4C3_10", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_SW2A3_10", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NW4A3_10", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_LH11_10", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW2END0_10", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NE4BEG2_10", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_SE4BEG0_10", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SW4A0_10", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE4B1_10", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_SE4BEG1_10", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_EE4C1_10", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_NE4BEG1_10", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_NW4END0_10", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_WW4END1_10", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_WW4END0_10", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WW4A2_10", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_NW4END3_10", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW4A1_10", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_LH8_10", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_LH12_10", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_EE4B2_10", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE2BEG1_10", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NW4END2_10", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_ER1BEG3_10", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_SE4C1_10", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_SW4A2_10", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_LH7_10", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4C0_10", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_SW2A2_10", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_LH1_10", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_LH2_10", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_WW2A2_10", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4BEG3_10", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_ER1BEG0_10", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NW2A0_10", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_SE4C2_10", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_SE4BEG3_10", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_SW2A0_10", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_ER1BEG2_10", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_EE2BEG2_10", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_LH9_10", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_EE4BEG2_10", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SW4A3_10", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_NW4A1_10", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_NW4END1_10", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NE4C2_10", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE4A2_10", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4C3_10", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW2END1_10", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE4A1_10", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_WW2END3_10", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_SW4END3_10", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_WW4C2_10", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_WW4A0_10", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_NE2A0_10", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_LH10_10", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_NW4A2_10", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_LH6_10", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_EL1BEG3_10", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_EL1BEG0_10", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_SW4END0_10", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EE2A1_10", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_EL1BEG2_10", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_SW2A1_10", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_WW4C1_10", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_WR1END2_10", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_NE2A1_10", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NE2A3_10", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_EE4BEG0_10", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NW2A2_10", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_SW4END2_10", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_EL1BEG1_10", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW4END2_10", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_SE4BEG2_10", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW4B3_10", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_WW4B2_10", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_SE4C3_10", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WW4B1_10", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_NW2A1_10", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SE2A0_10", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_WR1END1_10", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WW4C3_10", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_LH3_10", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SE2A3_10", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_WR1END3_10", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_NE4C0_10", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_EE2A2_10", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WL1END2_10", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SW4END1_10", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EE2BEG3_10", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NE4BEG0_10", + "INT_FEEDTHRU_2_NE4BEG0" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "CLK_HROW_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_LH10_3", + "VBRK_LH10" + ], + [ + "CLK_HROW_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_LH7_3", + "VBRK_LH7" + ], + [ + "CLK_HROW_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_LH1_3", + "VBRK_LH1" + ], + [ + "CLK_HROW_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_LH4_3", + "VBRK_LH4" + ], + [ + "CLK_HROW_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_LH8_3", + "VBRK_LH8" + ], + [ + "CLK_HROW_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_MONITOR_N_3", + "VBRK_MONITOR_N" + ], + [ + "CLK_HROW_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_LH6_3", + "VBRK_LH6" + ], + [ + "CLK_HROW_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_LH9_3", + "VBRK_LH9" + ], + [ + "CLK_HROW_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_LH3_3", + "VBRK_LH3" + ], + [ + "CLK_HROW_LH11_3", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH12_3", + "VBRK_LH12" + ], + [ + "CLK_HROW_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_EL1BEG1_3", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_LH2_3", + "VBRK_LH2" + ], + [ + "CLK_HROW_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_MONITOR_P_3", + "VBRK_MONITOR_P" + ], + [ + "CLK_HROW_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_LH5_3", + "VBRK_LH5" + ] + ], + "tile_types": [ + "CLK_BUFG_TOP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 10 + ], + "wire_pairs": [ + [ + "CFG_CENTER_NW4A1_1", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_WW4A1_1", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_IMUX3_1", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_SW4END0_1", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_WW2A3_1", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_1", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B11_1", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "CFG_CENTER_BYP1_1", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SE2A2_1", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_WW2END3_1", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_LH4_1", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_CTRL0_1", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX10_1", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_FAN2_1", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_EE4B2_1", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX31_1", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_EE4C3_1", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_WW4B2_1", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_LH3_1", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX46_1", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW2A2_1", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_EE4A1_1", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_WW2END0_1", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_1", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_NW4END3_1", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_EE2BEG3_1", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX33_1", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_WW2END1_1", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_ER1BEG2_1", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX5_1", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WR1END3_1", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX32_1", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_IMUX17_1", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_NW4END2_1", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_IMUX22_1", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX24_1", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_BYP2_1", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_IMUX38_1", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX21_1", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_WL1END3_1", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_NE2A1_1", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_BYP6_1", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_LH7_1", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_SE2A3_1", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_FAN5_1", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_IMUX37_1", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_IMUX42_1", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX13_1", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_FAN7_1", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_ER1BEG1_1", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SW2A1_1", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_LH2_1", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_SW4A0_1", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_EE4BEG1_1", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG0_1", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_SW4END1_1", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_IMUX23_1", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WR1END0_1", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_WR1END1_1", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NE4BEG0_1", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_SW2A2_1", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_WW4B0_1", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_LH9_1", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_NE4C0_1", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_SE2A0_1", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_SE4BEG2_1", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE2A3_1", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NW2A0_1", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_NE4C1_1", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_BYP4_1", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WW4END2_1", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_WW4C1_1", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_SW4A1_1", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_IMUX41_1", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_NW4A2_1", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_EE2A2_1", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_IMUX35_1", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_NE2A2_1", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE4BEG0_1", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_NW2A3_1", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NE2A0_1", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_BYP0_1", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX34_1", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_WW4C2_1", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX18_1", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_EL1BEG0_1", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_1", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_LH11_1", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_WW4END1_1", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_EE4A0_1", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_IMUX47_1", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX43_1", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_WL1END1_1", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_SW4A2_1", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NW4A0_1", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX20_1", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SE4BEG1_1", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_BYP5_1", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_SE4BEG3_1", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_1", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_WW4A0_1", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX12_1", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX4_1", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_EE4B0_1", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_CLK1_1", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_1", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_IMUX7_1", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_IMUX6_1", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_NE4BEG2_1", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW4END3_1", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX2_1", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_WW4C3_1", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_WR1END2_1", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_1", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_EE4C0_1", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B10_1", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "CFG_CENTER_WW4END0_1", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_FAN1_1", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX1_1", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX36_1", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW4A3_1", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EE4A2_1", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_SE4C0_1", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_NW2A1_1", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_ER1BEG3_1", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_SW4END2_1", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_WL1END0_1", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_SW2A3_1", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_EE2BEG2_1", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_EE2BEG0_1", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX9_1", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_1", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_1", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_EL1BEG3_1", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW4A3_1", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_IMUX11_1", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_NE4BEG1_1", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX29_1", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_FAN6_1", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_EE4A3_1", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_NE4C2_1", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_BYP3_1", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_IMUX14_1", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_IMUX0_1", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_EE4BEG3_1", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_1", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_SW4END3_1", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_NE4BEG3_1", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX25_1", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_FAN3_1", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_EE2A0_1", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_ER1BEG0_1", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_1", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_WL1END2_1", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WW2A1_1", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_SE4C2_1", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_LH10_1", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_FAN0_1", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_EE4C1_1", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX16_1", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WW4A2_1", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_NW4END1_1", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SE4C1_1", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX39_1", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_CTRL1_1", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_LH6_1", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_EL1BEG1_1", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_IMUX28_1", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX44_1", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_EE4B1_1", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_WW2END2_1", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_WW4C0_1", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_EE2A1_1", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX15_1", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_NW4A3_1", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SE2A1_1", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_SW2A0_1", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_LH5_1", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX45_1", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX27_1", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_NW4END0_1", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_BYP7_1", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_IMUX26_1", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_CLK0_1", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_WW4B3_1", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_IMUX30_1", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_IMUX40_1", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_EE2BEG1_1", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_NE4C3_1", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_LH12_1", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_LH8_1", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_NE2A3_1", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_1", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_WW4B1_1", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_NW2A2_1", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_LH1_1", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_EE4C2_1", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_EL1BEG2_1", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_1", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_FAN4_1", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW2A0_1", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_IMUX8_1", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_SE4C3_1", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX19_1", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_EE4BEG2_1", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE4B3_1", + "VFRAME_EE4B3" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + 5 + ], + "wire_pairs": [ + [ + "CMT_R_TOP_UPPER_B_CLKPLL3", + "HCLK_CMT_MUX_CLK_PLL3" + ], + [ + "CMT_PHASER_IN_C_ICLK", + "HCLK_CMT_PHASERINC_ICLK" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT2", + "HCLK_CMT_FREQ_REF_NS2" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL7", + "HCLK_CMT_MUX_CLK_PLL7" + ], + [ + "CMT_PHASER_IN_C_ICLKDIV", + "HCLK_CMT_PHASERINC_ICLKDIV" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT0", + "HCLK_CMT_FREQ_REF_NS0" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL1", + "HCLK_CMT_MUX_CLK_PLL1" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT3", + "HCLK_CMT_FREQ_REF_NS3" + ], + [ + "CMT_FREQ_PHASER_REFMUX_0", + "HCLK_CMT_FREQ_PHASER_REFMUX_0" + ], + [ + "CMT_FREQ_PHASER_REFMUX_2", + "HCLK_CMT_FREQ_PHASER_REFMUX_2" + ], + [ + "CMT_PHY_CONTROL_IBURSTPENDING0", + "HCLK_CMT_IBURSTPENDING0" + ], + [ + "CMT_PHASER_OUT_D_OCLK", + "HCLK_CMT_PHASEROUTD_OCLK" + ], + [ + "CMT_PHASER_IN_D_ICLKDIV", + "HCLK_CMT_PHASERIND_ICLKDIV" + ], + [ + "CMT_PHASER_IN_D_RCLK3", + "HCLK_CMT_PHASERIN_RCLK3" + ], + [ + "CMT_PHY_CONTROL_IRANKB0", + "HCLK_CMT_PHY_CONTROL_IRANKB0" + ], + [ + "CMT_R_TOP_UPPER_B_CLKIN2", + "HCLK_CMT_MUX_PLLE2_CLKIN2" + ], + [ + "CMT_FREQ_PHASER_REFMUX_1", + "HCLK_CMT_FREQ_PHASER_REFMUX_1" + ], + [ + "CMT_R_TOP_UPPER_B_CLKIN1", + "HCLK_CMT_MUX_PLLE2_CLKIN1" + ], + [ + "CMT_PHY_CONTROL_OBURSTPENDING0", + "HCLK_CMT_OBURSTPENDING0" + ], + [ + "CMT_PHASER_REF_TMUXOUT_TOHCLK", + "HCLK_CMT_PREF_TMUXOUT" + ], + [ + "CMT_PHASER_REF_CLKOUT_TOHCLK", + "HCLK_CMT_PREF_CLKOUT" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL0", + "HCLK_CMT_MUX_CLK_PLL0" + ], + [ + "CMT_PHY_CONTROL_IRANKA1", + "HCLK_CMT_PHY_CONTROL_IRANKA1" + ], + [ + "CMT_PHASER_OUT_C_OCLK1X_90", + "HCLK_CMT_PHASEROUTC_OCLK1X_90" + ], + [ + "CMT_R_TOP_UPPER_B_CLKINT_3", + "HCLK_CMT_MUX_CLKINT_3" + ], + [ + "CMT_PHASER_UP_PHASERREF_ABOVE1", + "HCLK_CMT_PHASEREF_ABOVE1" + ], + [ + "CMT_PHASER_UP_PHASERREF0", + "HCLK_CMT_BUFMR_PHASEREF0" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL2", + "HCLK_CMT_MUX_CLK_PLL2" + ], + [ + "CMT_PHASER_UP_BUFMRCE_CE0", + "HCLK_CMT_BUFMR_CE0" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL6", + "HCLK_CMT_MUX_CLK_PLL6" + ], + [ + "CMT_PHASER_TOP_SYNC_BB", + "HCLK_CMT_PHY_SYNC_BB" + ], + [ + "CMT_PHY_CONTROL_IBURSTPENDING1", + "HCLK_CMT_IBURSTPENDING1" + ], + [ + "CMT_PHASER_OUT_D_OCLK1X_90", + "HCLK_CMT_PHASEROUTD_OCLK1X_90" + ], + [ + "CMT_PHY_CONTROL_OBURSTPENDING1", + "HCLK_CMT_OBURSTPENDING1" + ], + [ + "CMT_PHASER_UP_BUFMRCE_CE1", + "HCLK_CMT_BUFMR_CE1" + ], + [ + "CMT_PHY_CONTROL_IRANKB1", + "HCLK_CMT_PHY_CONTROL_IRANKB1" + ], + [ + "CMT_R_TOP_UPPER_B_CLKINT_2", + "HCLK_CMT_MUX_CLKINT_2" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL4", + "HCLK_CMT_MUX_CLK_PLL4" + ], + [ + "CMT_PHASER_OUT_C_OCLKDIV", + "HCLK_CMT_PHASEROUTC_OCLKDIV" + ], + [ + "CMT_PHASER_IN_C_RCLK2", + "HCLK_CMT_PHASERIN_RCLK2" + ], + [ + "CMT_PHASER_UP_PHASERREF_BELOW1", + "HCLK_CMT_PHASEREF_BELOW1" + ], + [ + "CMT_PHASER_IN_D_ICLK", + "HCLK_CMT_PHASERIND_ICLK" + ], + [ + "CMT_PHASER_OUT_D_OCLKDIV", + "HCLK_CMT_PHASEROUTD_OCLKDIV" + ], + [ + "CMT_PHASER_OUT_C_OCLK", + "HCLK_CMT_PHASEROUTC_OCLK" + ], + [ + "CMT_PHASER_UP_PHASERREF_BELOW0", + "HCLK_CMT_PHASEREF_BELOW0" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL5", + "HCLK_CMT_MUX_CLK_PLL5" + ], + [ + "CMT_PHY_CONTROL_ECALIB0", + "HCLK_CMT_ECALIB0" + ], + [ + "CMT_PHY_CONTROL_IRANKA0", + "HCLK_CMT_PHY_CONTROL_IRANKA0" + ], + [ + "CMT_PHY_CONTROL_ECALIB1", + "HCLK_CMT_ECALIB1" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT1", + "HCLK_CMT_FREQ_REF_NS1" + ], + [ + "CMT_PHASER_UP_PHASERREF_ABOVE0", + "HCLK_CMT_PHASEREF_ABOVE0" + ], + [ + "CMT_R_TOP_UPPER_B_CLKFBIN", + "HCLK_CMT_MUX_PLLE2_CLKFBIN" + ], + [ + "CMT_PHASER_UP_PHASERREF1", + "HCLK_CMT_BUFMR_PHASEREF1" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "HCLK_CMT" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "MONITOR_IMUX46_2", + "VFRAME_IMUX46" + ], + [ + "MONITOR_IMUX44_2", + "VFRAME_IMUX44" + ], + [ + "MONITOR_IMUX7_2", + "VFRAME_IMUX7" + ], + [ + "MONITOR_IMUX23_2", + "VFRAME_IMUX23" + ], + [ + "MONITOR_NE4BEG1_2", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_SW4END3_2", + "VFRAME_SW4END3" + ], + [ + "MONITOR_BYP4_2", + "VFRAME_BYP4" + ], + [ + "MONITOR_IMUX34_2", + "VFRAME_IMUX34" + ], + [ + "MONITOR_SE4C0_2", + "VFRAME_SE4C0" + ], + [ + "MONITOR_IMUX13_2", + "VFRAME_IMUX13" + ], + [ + "MONITOR_IMUX6_2", + "VFRAME_IMUX6" + ], + [ + "MONITOR_EE4BEG2_2", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_IMUX19_2", + "VFRAME_IMUX19" + ], + [ + "MONITOR_NW4A2_2", + "VFRAME_NW4A2" + ], + [ + "MONITOR_IMUX9_2", + "VFRAME_IMUX9" + ], + [ + "MONITOR_NE4C2_2", + "VFRAME_NE4C2" + ], + [ + "MONITOR_EE4C1_2", + "VFRAME_EE4C1" + ], + [ + "MONITOR_SE2A2_2", + "VFRAME_SE2A2" + ], + [ + "MONITOR_LH3_2", + "VFRAME_LH3" + ], + [ + "MONITOR_IMUX42_2", + "VFRAME_IMUX42" + ], + [ + "MONITOR_IMUX17_2", + "VFRAME_IMUX17" + ], + [ + "MONITOR_SE2A0_2", + "VFRAME_SE2A0" + ], + [ + "MONITOR_BYP2_2", + "VFRAME_BYP2" + ], + [ + "MONITOR_LH2_2", + "VFRAME_LH2" + ], + [ + "MONITOR_NE2A2_2", + "VFRAME_NE2A2" + ], + [ + "MONITOR_WW4B1_2", + "VFRAME_WW4B1" + ], + [ + "MONITOR_EE4BEG0_2", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_FAN2_2", + "VFRAME_FAN2" + ], + [ + "MONITOR_EE4B0_2", + "VFRAME_EE4B0" + ], + [ + "MONITOR_WW2END0_2", + "VFRAME_WW2END0" + ], + [ + "MONITOR_SE4BEG0_2", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_FAN3_2", + "VFRAME_FAN3" + ], + [ + "MONITOR_BYP5_2", + "VFRAME_BYP5" + ], + [ + "MONITOR_BYP0_2", + "VFRAME_BYP0" + ], + [ + "MONITOR_WW4C1_2", + "VFRAME_WW4C1" + ], + [ + "MONITOR_SE4C3_2", + "VFRAME_SE4C3" + ], + [ + "MONITOR_EE4B1_2", + "VFRAME_EE4B1" + ], + [ + "MONITOR_IMUX33_2", + "VFRAME_IMUX33" + ], + [ + "MONITOR_IMUX14_2", + "VFRAME_IMUX14" + ], + [ + "MONITOR_NE4BEG2_2", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_IMUX16_2", + "VFRAME_IMUX16" + ], + [ + "MONITOR_WW4A1_2", + "VFRAME_WW4A1" + ], + [ + "MONITOR_WR1END1_2", + "VFRAME_WR1END1" + ], + [ + "MONITOR_WW4C0_2", + "VFRAME_WW4C0" + ], + [ + "MONITOR_LH11_2", + "VFRAME_LH11" + ], + [ + "MONITOR_NW2A1_2", + "VFRAME_NW2A1" + ], + [ + "MONITOR_SW2A0_2", + "VFRAME_SW2A0" + ], + [ + "MONITOR_WW4C2_2", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE4C3_2", + "VFRAME_EE4C3" + ], + [ + "MONITOR_WW4A3_2", + "VFRAME_WW4A3" + ], + [ + "MONITOR_EE4B3_2", + "VFRAME_EE4B3" + ], + [ + "MONITOR_EE4BEG1_2", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_EE2BEG0_2", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_IMUX8_2", + "VFRAME_IMUX8" + ], + [ + "MONITOR_LH10_2", + "VFRAME_LH10" + ], + [ + "MONITOR_WW4END3_2", + "VFRAME_WW4END3" + ], + [ + "MONITOR_LH4_2", + "VFRAME_LH4" + ], + [ + "MONITOR_LH6_2", + "VFRAME_LH6" + ], + [ + "MONITOR_IMUX47_2", + "VFRAME_IMUX47" + ], + [ + "MONITOR_SW4A2_2", + "VFRAME_SW4A2" + ], + [ + "MONITOR_BYP1_2", + "VFRAME_BYP1" + ], + [ + "MONITOR_NW4END1_2", + "VFRAME_NW4END1" + ], + [ + "MONITOR_SE2A3_2", + "VFRAME_SE2A3" + ], + [ + "MONITOR_IMUX21_2", + "VFRAME_IMUX21" + ], + [ + "MONITOR_SE4C1_2", + "VFRAME_SE4C1" + ], + [ + "MONITOR_BYP6_2", + "VFRAME_BYP6" + ], + [ + "MONITOR_WW4B3_2", + "VFRAME_WW4B3" + ], + [ + "MONITOR_EE2A2_2", + "VFRAME_EE2A2" + ], + [ + "MONITOR_ER1BEG0_2", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_IMUX45_2", + "VFRAME_IMUX45" + ], + [ + "MONITOR_WR1END2_2", + "VFRAME_WR1END2" + ], + [ + "MONITOR_EE2A3_2", + "VFRAME_EE2A3" + ], + [ + "MONITOR_SW4END2_2", + "VFRAME_SW4END2" + ], + [ + "MONITOR_WL1END2_2", + "VFRAME_WL1END2" + ], + [ + "MONITOR_WR1END3_2", + "VFRAME_WR1END3" + ], + [ + "MONITOR_IMUX24_2", + "VFRAME_IMUX24" + ], + [ + "MONITOR_IMUX37_2", + "VFRAME_IMUX37" + ], + [ + "MONITOR_WW2A0_2", + "VFRAME_WW2A0" + ], + [ + "MONITOR_WR1END0_2", + "VFRAME_WR1END0" + ], + [ + "MONITOR_CLK1_2", + "VFRAME_CLK1" + ], + [ + "MONITOR_NW4A0_2", + "VFRAME_NW4A0" + ], + [ + "MONITOR_SW2A3_2", + "VFRAME_SW2A3" + ], + [ + "MONITOR_SE4BEG3_2", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_IMUX31_2", + "VFRAME_IMUX31" + ], + [ + "MONITOR_WW2END1_2", + "VFRAME_WW2END1" + ], + [ + "MONITOR_BYP3_2", + "VFRAME_BYP3" + ], + [ + "MONITOR_NE2A0_2", + "VFRAME_NE2A0" + ], + [ + "MONITOR_IMUX38_2", + "VFRAME_IMUX38" + ], + [ + "MONITOR_IMUX29_2", + "VFRAME_IMUX29" + ], + [ + "MONITOR_SE4C2_2", + "VFRAME_SE4C2" + ], + [ + "MONITOR_WW4A2_2", + "VFRAME_WW4A2" + ], + [ + "MONITOR_NW4END2_2", + "VFRAME_NW4END2" + ], + [ + "MONITOR_EE2BEG3_2", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_BYP7_2", + "VFRAME_BYP7" + ], + [ + "MONITOR_EE2A1_2", + "VFRAME_EE2A1" + ], + [ + "MONITOR_FAN4_2", + "VFRAME_FAN4" + ], + [ + "MONITOR_EE2BEG2_2", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_ER1BEG3_2", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_SE4BEG2_2", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_WW2A2_2", + "VFRAME_WW2A2" + ], + [ + "MONITOR_LH1_2", + "VFRAME_LH1" + ], + [ + "MONITOR_IMUX12_2", + "VFRAME_IMUX12" + ], + [ + "MONITOR_IMUX2_2", + "VFRAME_IMUX2" + ], + [ + "MONITOR_IMUX30_2", + "VFRAME_IMUX30" + ], + [ + "MONITOR_CTRL0_2", + "VFRAME_CTRL0" + ], + [ + "MONITOR_EE4BEG3_2", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_FAN5_2", + "VFRAME_FAN5" + ], + [ + "MONITOR_IMUX1_2", + "VFRAME_IMUX1" + ], + [ + "MONITOR_EL1BEG0_2", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_SW4A1_2", + "VFRAME_SW4A1" + ], + [ + "MONITOR_LH9_2", + "VFRAME_LH9" + ], + [ + "MONITOR_SW2A1_2", + "VFRAME_SW2A1" + ], + [ + "MONITOR_EE4B2_2", + "VFRAME_EE4B2" + ], + [ + "MONITOR_IMUX3_2", + "VFRAME_IMUX3" + ], + [ + "MONITOR_IMUX27_2", + "VFRAME_IMUX27" + ], + [ + "MONITOR_SE2A1_2", + "VFRAME_SE2A1" + ], + [ + "MONITOR_IMUX36_2", + "VFRAME_IMUX36" + ], + [ + "MONITOR_WW2A1_2", + "VFRAME_WW2A1" + ], + [ + "MONITOR_EL1BEG2_2", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_IMUX35_2", + "VFRAME_IMUX35" + ], + [ + "MONITOR_IMUX26_2", + "VFRAME_IMUX26" + ], + [ + "MONITOR_SW2A2_2", + "VFRAME_SW2A2" + ], + [ + "MONITOR_LH8_2", + "VFRAME_LH8" + ], + [ + "MONITOR_IMUX40_2", + "VFRAME_IMUX40" + ], + [ + "MONITOR_NE2A3_2", + "VFRAME_NE2A3" + ], + [ + "MONITOR_WL1END0_2", + "VFRAME_WL1END0" + ], + [ + "MONITOR_NW2A3_2", + "VFRAME_NW2A3" + ], + [ + "MONITOR_WL1END1_2", + "VFRAME_WL1END1" + ], + [ + "MONITOR_NE4C3_2", + "VFRAME_NE4C3" + ], + [ + "MONITOR_LH12_2", + "VFRAME_LH12" + ], + [ + "MONITOR_NW2A2_2", + "VFRAME_NW2A2" + ], + [ + "MONITOR_EE4A2_2", + "VFRAME_EE4A2" + ], + [ + "MONITOR_WL1END3_2", + "VFRAME_WL1END3" + ], + [ + "MONITOR_WW2END3_2", + "VFRAME_WW2END3" + ], + [ + "MONITOR_IMUX20_2", + "VFRAME_IMUX20" + ], + [ + "MONITOR_LH7_2", + "VFRAME_LH7" + ], + [ + "MONITOR_EL1BEG1_2", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_IMUX15_2", + "VFRAME_IMUX15" + ], + [ + "MONITOR_IMUX39_2", + "VFRAME_IMUX39" + ], + [ + "MONITOR_NW2A0_2", + "VFRAME_NW2A0" + ], + [ + "MONITOR_IMUX11_2", + "VFRAME_IMUX11" + ], + [ + "MONITOR_NE2A1_2", + "VFRAME_NE2A1" + ], + [ + "MONITOR_ER1BEG1_2", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_WW4END2_2", + "VFRAME_WW4END2" + ], + [ + "MONITOR_WW4END1_2", + "VFRAME_WW4END1" + ], + [ + "MONITOR_NW4END3_2", + "VFRAME_NW4END3" + ], + [ + "MONITOR_SW4END1_2", + "VFRAME_SW4END1" + ], + [ + "MONITOR_SW4END0_2", + "VFRAME_SW4END0" + ], + [ + "MONITOR_NE4C1_2", + "VFRAME_NE4C1" + ], + [ + "MONITOR_IMUX5_2", + "VFRAME_IMUX5" + ], + [ + "MONITOR_EE4C0_2", + "VFRAME_EE4C0" + ], + [ + "MONITOR_SW4A3_2", + "VFRAME_SW4A3" + ], + [ + "MONITOR_IMUX41_2", + "VFRAME_IMUX41" + ], + [ + "MONITOR_IMUX10_2", + "VFRAME_IMUX10" + ], + [ + "MONITOR_LH5_2", + "VFRAME_LH5" + ], + [ + "MONITOR_IMUX4_2", + "VFRAME_IMUX4" + ], + [ + "MONITOR_EL1BEG3_2", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_EE4A1_2", + "VFRAME_EE4A1" + ], + [ + "MONITOR_FAN6_2", + "VFRAME_FAN6" + ], + [ + "MONITOR_EE2BEG1_2", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_IMUX22_2", + "VFRAME_IMUX22" + ], + [ + "MONITOR_ER1BEG2_2", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_EE4C2_2", + "VFRAME_EE4C2" + ], + [ + "MONITOR_WW4B2_2", + "VFRAME_WW4B2" + ], + [ + "MONITOR_IMUX32_2", + "VFRAME_IMUX32" + ], + [ + "MONITOR_FAN7_2", + "VFRAME_FAN7" + ], + [ + "MONITOR_CLK0_2", + "VFRAME_CLK0" + ], + [ + "MONITOR_NE4C0_2", + "VFRAME_NE4C0" + ], + [ + "MONITOR_WW4END0_2", + "VFRAME_WW4END0" + ], + [ + "MONITOR_IMUX25_2", + "VFRAME_IMUX25" + ], + [ + "MONITOR_NW4A3_2", + "VFRAME_NW4A3" + ], + [ + "MONITOR_WW4B0_2", + "VFRAME_WW4B0" + ], + [ + "MONITOR_SE4BEG1_2", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_EE4A3_2", + "VFRAME_EE4A3" + ], + [ + "MONITOR_NE4BEG3_2", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_FAN1_2", + "VFRAME_FAN1" + ], + [ + "MONITOR_NW4END0_2", + "VFRAME_NW4END0" + ], + [ + "MONITOR_IMUX28_2", + "VFRAME_IMUX28" + ], + [ + "MONITOR_IMUX43_2", + "VFRAME_IMUX43" + ], + [ + "MONITOR_EE2A0_2", + "VFRAME_EE2A0" + ], + [ + "MONITOR_SW4A0_2", + "VFRAME_SW4A0" + ], + [ + "MONITOR_IMUX18_2", + "VFRAME_IMUX18" + ], + [ + "MONITOR_WW4A0_2", + "VFRAME_WW4A0" + ], + [ + "MONITOR_WW2A3_2", + "VFRAME_WW2A3" + ], + [ + "MONITOR_WW2END2_2", + "VFRAME_WW2END2" + ], + [ + "MONITOR_NE4BEG0_2", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_IMUX0_2", + "VFRAME_IMUX0" + ], + [ + "MONITOR_FAN0_2", + "VFRAME_FAN0" + ], + [ + "MONITOR_WW4C3_2", + "VFRAME_WW4C3" + ], + [ + "MONITOR_NW4A1_2", + "VFRAME_NW4A1" + ], + [ + "MONITOR_EE4A0_2", + "VFRAME_EE4A0" + ], + [ + "MONITOR_CTRL1_2", + "VFRAME_CTRL1" + ] + ], + "tile_types": [ + "MONITOR_TOP_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE2A3_6", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NE4C2_6", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_LH4_6", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_WW2END3_6", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_LH8_6", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW2A0_6", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_EE4A1_6", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NW4A1_6", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SE2A1_6", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WL1END3_6", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4A2_6", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_WW4B3_6", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_LH3_6", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_EE2A1_6", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_SW2A2_6", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WR1END2_6", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_SW2A3_6", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NE4BEG3_6", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW2END2_6", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SE4BEG2_6", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW2END1_6", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_NW4END3_6", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_ER1BEG1_6", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SW4END1_6", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EL1BEG2_6", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_EL1BEG3_6", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WW4A2_6", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE4BEG1_6", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_NW4END0_6", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_EE2BEG0_6", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WL1END2_6", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SW4END3_6", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NE2A3_6", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_EE4BEG0_6", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NE4BEG0_6", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NW4END2_6", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4C1_6", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_WR1END1_6", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SW4A3_6", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE4A0_6", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EL1BEG0_6", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE4BEG3_6", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_NW2A1_6", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SE4C3_6", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_LH6_6", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_LH12_6", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WR1END3_6", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_WW4B0_6", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_EE4C0_6", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EL1BEG1_6", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW4A0_6", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_LH7_6", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_EE4C2_6", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_WW2A2_6", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WW4C0_6", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NW4A2_6", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_LH5_6", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_SW2A1_6", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_NW4A0_6", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_ER1BEG0_6", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_WW2END0_6", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_SW4END2_6", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_LH9_6", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NE4C1_6", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE2A2_6", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_SE4C2_6", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_NE2A1_6", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NW2A2_6", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_SW4A1_6", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_EE4B0_6", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WW4A3_6", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_WW4A1_6", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_ER1BEG3_6", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_EE4BEG2_6", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_NW2A0_6", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WW4END2_6", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_EE4C3_6", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW4C3_6", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WR1END0_6", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_WW4B1_6", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_LH10_6", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WL1END1_6", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_EE4B3_6", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NE2A0_6", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_NW4A3_6", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WW4END0_6", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WL1END0_6", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_NE4C0_6", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_SW2A0_6", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_SE4BEG1_6", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG3_6", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_NW4END1_6", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_EE2A2_6", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_SE4C1_6", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_ER1BEG2_6", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_NE4C3_6", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_LH11_6", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_SE4BEG0_6", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_WW4END1_6", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE4B2_6", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE2BEG3_6", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_WW4B2_6", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_SE2A3_6", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SW4A2_6", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_EE4A3_6", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_NE4BEG2_6", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_LH1_6", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_EE2BEG2_6", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_SE2A0_6", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE4C1_6", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE2A0_6", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW2A3_6", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_SE2A2_6", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4B1_6", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NE4BEG1_6", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WW4C2_6", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_SE4C0_6", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_EE2BEG1_6", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NW2A3_6", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_LH2_6", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_SW4END0_6", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WW4END3_6", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW2A1_6", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_SW4A0_6", + "INT_FEEDTHRU_2_SW4A0" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_SW4END3", + "R_TERM_INT_SW4END3" + ], + [ + "INT_INTERFACE_IMUX19", + "TERM_INT_IMUX19" + ], + [ + "INT_INTERFACE_FAN3", + "TERM_INT_FAN3" + ], + [ + "INT_INTERFACE_NW4END1", + "R_TERM_INT_NW4END1" + ], + [ + "INT_INTERFACE_WW4A0", + "R_TERM_INT_WW4A0" + ], + [ + "INT_INTERFACE_EE4BEG3", + "R_TERM_INT_WW4A3" + ], + [ + "INT_INTERFACE_NW2A1", + "R_TERM_INT_NW2A1" + ], + [ + "INT_INTERFACE_CLK0", + "TERM_INT_CLK0" + ], + [ + "INT_INTERFACE_WW4END1", + "R_TERM_INT_WW4END1" + ], + [ + "INT_INTERFACE_IMUX38", + "TERM_INT_IMUX38" + ], + [ + "INT_INTERFACE_WW2END3", + "R_TERM_INT_WW2END3" + ], + [ + "INT_INTERFACE_FAN1", + "TERM_INT_FAN1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B15", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "INT_INTERFACE_WW4B2", + "R_TERM_INT_WW4B2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B11", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "INT_INTERFACE_SE4C1", + "R_TERM_INT_SW4END1" + ], + [ + "INT_INTERFACE_IMUX12", + "TERM_INT_IMUX12" + ], + [ + "INT_INTERFACE_EE4A2", + "R_TERM_INT_WW4B2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B16", + "TERM_INT_LOGIC_OUTS_L_B16" + ], + [ + "INT_INTERFACE_EE4C2", + "R_TERM_INT_WW4END2" + ], + [ + "INT_INTERFACE_IMUX3", + "TERM_INT_IMUX3" + ], + [ + "INT_INTERFACE_WW4B1", + "R_TERM_INT_WW4B1" + ], + [ + "INT_INTERFACE_NW4A3", + "R_TERM_INT_NW4A3" + ], + [ + "INT_INTERFACE_LH11", + "R_TERM_INT_LH1" + ], + [ + "INT_INTERFACE_SW2A1", + "R_TERM_INT_SW2A1" + ], + [ + "INT_INTERFACE_LH3", + "R_TERM_INT_LH2" + ], + [ + "INT_INTERFACE_BYP7", + "TERM_INT_BYP7" + ], + [ + "INT_INTERFACE_IMUX28", + "TERM_INT_IMUX28" + ], + [ + "INT_INTERFACE_BLOCK_OUTS_B1", + "TERM_INT_BLOCK_OUTS_L_B1" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B2", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "INT_INTERFACE_WW4C2", + "R_TERM_INT_WW4C2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B8", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "INT_INTERFACE_NE4C1", + "R_TERM_INT_NW4END1" + ], + [ + "INT_INTERFACE_SW4END1", + "R_TERM_INT_SW4END1" + ], + [ + "INT_INTERFACE_IMUX23", + "TERM_INT_IMUX23" + ], + [ + "INT_INTERFACE_SE4BEG1", + "R_TERM_INT_SW4A1" + ], + [ + "INT_INTERFACE_IMUX7", + "TERM_INT_IMUX7" + ], + [ + "INT_INTERFACE_WW4A2", + "R_TERM_INT_WW4A2" + ], + [ + "INT_INTERFACE_SW4A2", + "R_TERM_INT_SW4A2" + ], + [ + "INT_INTERFACE_SE2A2", + "R_TERM_INT_SW2A2" + ], + [ + "INT_INTERFACE_SE4BEG3", + "R_TERM_INT_SW4A3" + ], + [ + "INT_INTERFACE_IMUX13", + "TERM_INT_IMUX13" + ], + [ + "INT_INTERFACE_WR1END1", + "R_TERM_INT_WR1END1" + ], + [ + "INT_INTERFACE_IMUX5", + "TERM_INT_IMUX5" + ], + [ + "INT_INTERFACE_EE4A0", + "R_TERM_INT_WW4B0" + ], + [ + "INT_INTERFACE_IMUX21", + "TERM_INT_IMUX21" + ], + [ + "INT_INTERFACE_EE2BEG0", + "R_TERM_INT_WW2A0" + ], + [ + "INT_INTERFACE_ER1BEG0", + "R_TERM_INT_WR1END0" + ], + [ + "INT_INTERFACE_WW2A1", + "R_TERM_INT_WW2A1" + ], + [ + "INT_INTERFACE_BYP2", + "TERM_INT_BYP2" + ], + [ + "INT_INTERFACE_BYP6", + "TERM_INT_BYP6" + ], + [ + "INT_INTERFACE_EE2A3", + "R_TERM_INT_WW2END3" + ], + [ + "INT_INTERFACE_WW4END2", + "R_TERM_INT_WW4END2" + ], + [ + "INT_INTERFACE_SE4BEG2", + "R_TERM_INT_SW4A2" + ], + [ + "INT_INTERFACE_BYP3", + "TERM_INT_BYP3" + ], + [ + "INT_INTERFACE_EL1BEG3", + "R_TERM_INT_WL1END3" + ], + [ + "INT_INTERFACE_WL1END2", + "R_TERM_INT_WL1END2" + ], + [ + "INT_INTERFACE_IMUX37", + "TERM_INT_IMUX37" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B13", + "TERM_INT_LOGIC_OUTS_L_B13" + ], + [ + "INT_INTERFACE_IMUX25", + "TERM_INT_IMUX25" + ], + [ + "INT_INTERFACE_NW2A3", + "R_TERM_INT_NW2A3" + ], + [ + "INT_INTERFACE_EE4B0", + "R_TERM_INT_WW4C0" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "INT_INTERFACE_SW2A2", + "R_TERM_INT_SW2A2" + ], + [ + "INT_INTERFACE_IMUX20", + "TERM_INT_IMUX20" + ], + [ + "INT_INTERFACE_EE4BEG1", + "R_TERM_INT_WW4A1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B4", + "TERM_INT_LOGIC_OUTS_L_B4" + ], + [ + "INT_INTERFACE_NE4BEG1", + "R_TERM_INT_NW4A1" + ], + [ + "INT_INTERFACE_EE4B1", + "R_TERM_INT_WW4C1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B14", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B5", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "INT_INTERFACE_ER1BEG1", + "R_TERM_INT_WR1END1" + ], + [ + "INT_INTERFACE_IMUX0", + "TERM_INT_IMUX0" + ], + [ + "INT_INTERFACE_NE4C2", + "R_TERM_INT_NW4END2" + ], + [ + "INT_INTERFACE_IMUX8", + "TERM_INT_IMUX8" + ], + [ + "INT_INTERFACE_IMUX4", + "TERM_INT_IMUX4" + ], + [ + "INT_INTERFACE_WR1END3", + "R_TERM_INT_WR1END3" + ], + [ + "INT_INTERFACE_SW2A0", + "R_TERM_INT_SW2A0" + ], + [ + "INT_INTERFACE_BYP5", + "TERM_INT_BYP5" + ], + [ + "INT_INTERFACE_NE4BEG0", + "R_TERM_INT_NW4A0" + ], + [ + "INT_INTERFACE_WW4END0", + "R_TERM_INT_WW4END0" + ], + [ + "INT_INTERFACE_SE4BEG0", + "R_TERM_INT_SW4A0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B1", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "INT_INTERFACE_IMUX45", + "TERM_INT_IMUX45" + ], + [ + "INT_INTERFACE_IMUX32", + "TERM_INT_IMUX32" + ], + [ + "INT_INTERFACE_EE4BEG2", + "R_TERM_INT_WW4A2" + ], + [ + "INT_INTERFACE_WW4A1", + "R_TERM_INT_WW4A1" + ], + [ + "INT_INTERFACE_FAN2", + "TERM_INT_FAN2" + ], + [ + "INT_INTERFACE_IMUX36", + "TERM_INT_IMUX36" + ], + [ + "INT_INTERFACE_NW4END0", + "R_TERM_INT_NW4END0" + ], + [ + "INT_INTERFACE_NE4BEG3", + "R_TERM_INT_NW4A3" + ], + [ + "INT_INTERFACE_EE2BEG3", + "R_TERM_INT_WW2A3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B6", + "TERM_INT_LOGIC_OUTS_L_B6" + ], + [ + "INT_INTERFACE_NW4A0", + "R_TERM_INT_NW4A0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B21", + "TERM_INT_LOGIC_OUTS_L_B21" + ], + [ + "INT_INTERFACE_SW4END0", + "R_TERM_INT_SW4END0" + ], + [ + "INT_INTERFACE_WW4C0", + "R_TERM_INT_WW4C0" + ], + [ + "INT_INTERFACE_IMUX31", + "TERM_INT_IMUX31" + ], + [ + "INT_INTERFACE_WR1END2", + "R_TERM_INT_WR1END2" + ], + [ + "INT_INTERFACE_SW4A0", + "R_TERM_INT_SW4A0" + ], + [ + "INT_INTERFACE_IMUX14", + "TERM_INT_IMUX14" + ], + [ + "INT_INTERFACE_SW4A3", + "R_TERM_INT_SW4A3" + ], + [ + "INT_INTERFACE_WW2END1", + "R_TERM_INT_WW2END1" + ], + [ + "INT_INTERFACE_NW4END3", + "R_TERM_INT_NW4END3" + ], + [ + "INT_INTERFACE_NE2A3", + "R_TERM_INT_NW2A3" + ], + [ + "INT_INTERFACE_IMUX10", + "TERM_INT_IMUX10" + ], + [ + "INT_INTERFACE_FAN0", + "TERM_INT_FAN0" + ], + [ + "INT_INTERFACE_IMUX16", + "TERM_INT_IMUX16" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B23", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B20", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "INT_INTERFACE_NE2A1", + "R_TERM_INT_NW2A1" + ], + [ + "INT_INTERFACE_IMUX2", + "TERM_INT_IMUX2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B19", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "INT_INTERFACE_SW2A3", + "R_TERM_INT_SW2A3" + ], + [ + "INT_INTERFACE_IMUX9", + "TERM_INT_IMUX9" + ], + [ + "INT_INTERFACE_EE2A2", + "R_TERM_INT_WW2END2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B3", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "INT_INTERFACE_IMUX29", + "TERM_INT_IMUX29" + ], + [ + "INT_INTERFACE_CTRL1", + "TERM_INT_CTRL1" + ], + [ + "INT_INTERFACE_WW4C1", + "R_TERM_INT_WW4C1" + ], + [ + "INT_INTERFACE_LH10", + "R_TERM_INT_LH2" + ], + [ + "INT_INTERFACE_EE4C3", + "R_TERM_INT_WW4END3" + ], + [ + "INT_INTERFACE_IMUX35", + "TERM_INT_IMUX35" + ], + [ + "INT_INTERFACE_BYP0", + "TERM_INT_BYP0" + ], + [ + "INT_INTERFACE_WW2A3", + "R_TERM_INT_WW2A3" + ], + [ + "INT_INTERFACE_WL1END1", + "R_TERM_INT_WL1END1" + ], + [ + "INT_INTERFACE_BYP4", + "TERM_INT_BYP4" + ], + [ + "INT_INTERFACE_EE2A0", + "R_TERM_INT_WW2END0" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90" + ], + [ + "INT_INTERFACE_WL1END3", + "R_TERM_INT_WL1END3" + ], + [ + "INT_INTERFACE_SW4END2", + "R_TERM_INT_SW4END2" + ], + [ + "INT_INTERFACE_CTRL0", + "TERM_INT_CTRL0" + ], + [ + "INT_INTERFACE_WW2END2", + "R_TERM_INT_WW2END2" + ], + [ + "INT_INTERFACE_NE4BEG2", + "R_TERM_INT_NW4A2" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "INT_INTERFACE_WW2A0", + "R_TERM_INT_WW2A0" + ], + [ + "INT_INTERFACE_NE4C0", + "R_TERM_INT_NW4END0" + ], + [ + "INT_INTERFACE_NW4A1", + "R_TERM_INT_NW4A1" + ], + [ + "INT_INTERFACE_BYP1", + "TERM_INT_BYP1" + ], + [ + "INT_INTERFACE_NE4C3", + "R_TERM_INT_NW4END3" + ], + [ + "INT_INTERFACE_IMUX17", + "TERM_INT_IMUX17" + ], + [ + "INT_INTERFACE_EE4C0", + "R_TERM_INT_WW4END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B17", + "TERM_INT_LOGIC_OUTS_L_B17" + ], + [ + "INT_INTERFACE_IMUX43", + "TERM_INT_IMUX43" + ], + [ + "INT_INTERFACE_EE4C1", + "R_TERM_INT_WW4END1" + ], + [ + "INT_INTERFACE_EL1BEG0", + "R_TERM_INT_WL1END0" + ], + [ + "INT_INTERFACE_IMUX34", + "TERM_INT_IMUX34" + ], + [ + "INT_INTERFACE_IMUX1", + "TERM_INT_IMUX1" + ], + [ + "INT_INTERFACE_IMUX27", + "TERM_INT_IMUX27" + ], + [ + "INT_INTERFACE_WW2A2", + "R_TERM_INT_WW2A2" + ], + [ + "INT_INTERFACE_BLOCK_OUTS_B0", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "INT_INTERFACE_NE2A2", + "R_TERM_INT_NW2A2" + ], + [ + "INT_INTERFACE_EE4A3", + "R_TERM_INT_WW4B3" + ], + [ + "INT_INTERFACE_IMUX11", + "TERM_INT_IMUX11" + ], + [ + "INT_INTERFACE_EE4A1", + "R_TERM_INT_WW4B1" + ], + [ + "INT_INTERFACE_WR1END0", + "R_TERM_INT_WR1END0" + ], + [ + "INT_INTERFACE_LH4", + "R_TERM_INT_LH3" + ], + [ + "INT_INTERFACE_ER1BEG2", + "R_TERM_INT_WR1END2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B18", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "INT_INTERFACE_WL1END0", + "R_TERM_INT_WL1END0" + ], + [ + "INT_INTERFACE_IMUX22", + "TERM_INT_IMUX22" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B9", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "INT_INTERFACE_EE4BEG0", + "R_TERM_INT_WW4A0" + ], + [ + "INT_INTERFACE_NW4END2", + "R_TERM_INT_NW4END2" + ], + [ + "INT_INTERFACE_IMUX30", + "TERM_INT_IMUX30" + ], + [ + "INT_INTERFACE_WW4B3", + "R_TERM_INT_WW4B3" + ], + [ + "INT_INTERFACE_EE2A1", + "R_TERM_INT_WW2END1" + ], + [ + "INT_INTERFACE_MONITOR_P", + "TERM_INT_MONITOR_P" + ], + [ + "INT_INTERFACE_WW4C3", + "R_TERM_INT_WW4C3" + ], + [ + "INT_INTERFACE_EE2BEG1", + "R_TERM_INT_WW2A1" + ], + [ + "INT_INTERFACE_IMUX18", + "TERM_INT_IMUX18" + ], + [ + "INT_INTERFACE_NW4A2", + "R_TERM_INT_NW4A2" + ], + [ + "INT_INTERFACE_FAN6", + "TERM_INT_FAN6" + ], + [ + "INT_INTERFACE_SE4C0", + "R_TERM_INT_SW4END0" + ], + [ + "INT_INTERFACE_WW2END0", + "R_TERM_INT_WW2END0" + ], + [ + "INT_INTERFACE_IMUX42", + "TERM_INT_IMUX42" + ], + [ + "INT_INTERFACE_IMUX46", + "TERM_INT_IMUX46" + ], + [ + "INT_INTERFACE_SE2A1", + "R_TERM_INT_SW2A1" + ], + [ + "INT_INTERFACE_EE2BEG2", + "R_TERM_INT_WW2A2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B12", + "TERM_INT_LOGIC_OUTS_L_B12" + ], + [ + "INT_INTERFACE_FAN5", + "TERM_INT_FAN5" + ], + [ + "INT_INTERFACE_IMUX24", + "TERM_INT_IMUX24" + ], + [ + "L_INT_INTER_DQS_IOTOPHASER", + "L_TERM_INT_DQS_IOTOPHASER" + ], + [ + "INT_INTERFACE_LH8", + "R_TERM_INT_LH4" + ], + [ + "INT_INTERFACE_IMUX6", + "TERM_INT_IMUX6" + ], + [ + "INT_INTERFACE_IMUX44", + "TERM_INT_IMUX44" + ], + [ + "INT_INTERFACE_IMUX41", + "TERM_INT_IMUX41" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B0", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B22", + "TERM_INT_LOGIC_OUTS_L_B22" + ], + [ + "INT_INTERFACE_LH6", + "R_TERM_INT_LH5" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B10", + "TERM_INT_LOGIC_OUTS_L_B10" + ], + [ + "INT_INTERFACE_LH2", + "R_TERM_INT_LH1" + ], + [ + "INT_INTERFACE_NW2A0", + "R_TERM_INT_NW2A0" + ], + [ + "INT_INTERFACE_WW4END3", + "R_TERM_INT_WW4END3" + ], + [ + "INT_INTERFACE_EL1BEG2", + "R_TERM_INT_WL1END2" + ], + [ + "INT_INTERFACE_EE4B3", + "R_TERM_INT_WW4C3" + ], + [ + "INT_INTERFACE_WW4B0", + "R_TERM_INT_WW4B0" + ], + [ + "INT_INTERFACE_IMUX26", + "TERM_INT_IMUX26" + ], + [ + "INT_INTERFACE_FAN4", + "TERM_INT_FAN4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B7", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "INT_INTERFACE_IMUX40", + "TERM_INT_IMUX40" + ], + [ + "INT_INTERFACE_IMUX33", + "TERM_INT_IMUX33" + ], + [ + "INT_INTERFACE_SE2A3", + "R_TERM_INT_SW2A3" + ], + [ + "INT_INTERFACE_EL1BEG1", + "R_TERM_INT_WL1END1" + ], + [ + "INT_INTERFACE_SW4A1", + "R_TERM_INT_SW4A1" + ], + [ + "INT_INTERFACE_SE4C2", + "R_TERM_INT_SW4END2" + ], + [ + "INT_INTERFACE_SE4C3", + "R_TERM_INT_SW4END3" + ], + [ + "INT_INTERFACE_IMUX15", + "TERM_INT_IMUX15" + ], + [ + "INT_INTERFACE_FAN7", + "TERM_INT_FAN7" + ], + [ + "INT_INTERFACE_LH9", + "R_TERM_INT_LH3" + ], + [ + "INT_INTERFACE_CLK1", + "TERM_INT_CLK1" + ], + [ + "INT_INTERFACE_LH1", + "R_TERM_INT_LH0" + ], + [ + "INT_INTERFACE_LH7", + "R_TERM_INT_LH5" + ], + [ + "INT_INTERFACE_BLOCK_OUTS_B2", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "INT_INTERFACE_MONITOR_N", + "TERM_INT_MONITOR_N" + ], + [ + "INT_INTERFACE_EE4B2", + "R_TERM_INT_WW4C2" + ], + [ + "INT_INTERFACE_IMUX47", + "TERM_INT_IMUX47" + ], + [ + "INT_INTERFACE_NE2A0", + "R_TERM_INT_NW2A0" + ], + [ + "INT_INTERFACE_SE2A0", + "R_TERM_INT_SW2A0" + ], + [ + "INT_INTERFACE_NW2A2", + "R_TERM_INT_NW2A2" + ], + [ + "INT_INTERFACE_WW4A3", + "R_TERM_INT_WW4A3" + ], + [ + "INT_INTERFACE_LH12", + "R_TERM_INT_LH0" + ], + [ + "INT_INTERFACE_IMUX39", + "TERM_INT_IMUX39" + ], + [ + "INT_INTERFACE_ER1BEG3", + "R_TERM_INT_WR1END3" + ], + [ + "INT_INTERFACE_LH5", + "R_TERM_INT_LH4" + ] + ], + "tile_types": [ + "IO_INT_INTERFACE_R", + "R_TERM_INT" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "CMT_TOP_EE2BEG2_9", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NE4C0_9", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EE2A0_9", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_9", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SE4BEG2_9", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_NE2A2_9", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW2A2_9", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_LH6_9", + "VBRK_LH6" + ], + [ + "CMT_TOP_EE4B1_9", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW4A1_9", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SW4A2_9", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WR1END2_9", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH8_9", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A3_9", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4BEG3_9", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WW2END2_9", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2A1_9", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4A0_9", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4C1_9", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NE4C3_9", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW2A0_9", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_9", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2END0_9", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4C2_9", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A3_9", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_ER1BEG0_9", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EL1BEG1_9", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG0_9", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH3_9", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END2_9", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH2_9", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW4A3_9", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW2A2_9", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4A2_9", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END3_9", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE2A3_9", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4BEG2_9", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4END0_9", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SW4A0_9", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4C1_9", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A1_9", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4END2_9", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EL1BEG3_9", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_9", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW2A0_9", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4B0_9", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE4C0_9", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE4B3_9", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW4A1_9", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_LH4_9", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW4C1_9", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_EE2BEG1_9", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4A0_9", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4BEG0_9", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_9", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2A2_9", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EE4A1_9", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4END0_9", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW4B1_9", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4A3_9", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END3_9", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH11_9", + "VBRK_LH11" + ], + [ + "CMT_TOP_SW4END3_9", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_9", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END1_9", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_LH12_9", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C1_9", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE4C3_9", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_SE2A1_9", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE4A0_9", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_EE2BEG3_9", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END1_9", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A1_9", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE2BEG0_9", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE2A2_9", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END3_9", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_ER1BEG3_9", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NE2A3_9", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW2A3_9", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_9", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH9_9", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4B0_9", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A0_9", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NE4BEG2_9", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A2_9", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_WW4C0_9", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SW2A1_9", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH5_9", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END0_9", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NE4BEG1_9", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_9", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A2_9", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4BEG1_9", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C0_9", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_WW4END2_9", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_WW4END1_9", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NW2A0_9", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4C2_9", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_WW4B3_9", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WR1END0_9", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW2A3_9", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW2A2_9", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_EE4BEG3_9", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C2_9", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_SE4BEG1_9", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_9", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_NE2A0_9", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4B2_9", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WL1END2_9", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG0_9", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG2_9", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4C3_9", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4A1_9", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH1_9", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW4END0_9", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_EE4A3_9", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_LH10_9", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW2END1_9", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WL1END3_9", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_EE2A1_9", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4C3_9", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WR1END3_9", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SW2A3_9", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH7_9", + "VBRK_LH7" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -7 + ], + "wire_pairs": [ + [ + "CFG_CENTER_LH5_17", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_NE4BEG0_17", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_LH2_17", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_EE4A3_17", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_ER1BEG2_17", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_SE4C2_17", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_SE2A2_17", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_NE4C0_17", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_WW4B0_17", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_EE4BEG1_17", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_SW2A2_17", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_LH8_17", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_SW4END3_17", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_EE4B2_17", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_NW4A2_17", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WW4B1_17", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_NW2A2_17", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_ER1BEG3_17", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_EL1BEG0_17", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_NE4C3_17", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_ER1BEG0_17", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_LH1_17", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_EE4A2_17", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4B1_17", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_WW4A0_17", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SW2A0_17", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_LH3_17", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SW4A3_17", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_LH6_17", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_NE4BEG2_17", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_WW4END1_17", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE4C0_17", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_SE4C1_17", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_SW4END2_17", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SE2A0_17", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_WW4END0_17", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EE4BEG2_17", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SE4BEG2_17", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_SW2A1_17", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE2BEG3_17", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_EE2A3_17", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_EE2A2_17", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_NW4END3_17", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_EE4C1_17", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_WR1END2_17", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_SW2A3_17", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_LH4_17", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SE4C3_17", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WW2END3_17", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_EE4A0_17", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_WW4C2_17", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NW2A0_17", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_NW4END0_17", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_WL1END1_17", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_LH7_17", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_EE4B0_17", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH12_17", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_NW2A3_17", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_WL1END3_17", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_WW2END1_17", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_SW4A2_17", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NW4END2_17", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_LH9_17", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_EE2A0_17", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW2END0_17", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_EE2BEG0_17", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4C1_17", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_WW4A1_17", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_SW4A1_17", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NE2A2_17", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_NE4BEG1_17", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WW4END3_17", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW2A1_17", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_ER1BEG1_17", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_NE4BEG3_17", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG2_17", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_WL1END0_17", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SW4END0_17", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EL1BEG3_17", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_NW4A3_17", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WR1END1_17", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WR1END3_17", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE2A1_17", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_NW4A1_17", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WW2A2_17", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WW4END2_17", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_WW4A2_17", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE4A1_17", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EE4BEG0_17", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WW2END2_17", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SE2A3_17", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_NW2A1_17", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SW4A0_17", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WW4C3_17", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_SE2A1_17", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW2A0_17", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_EE2BEG2_17", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW2A3_17", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WL1END2_17", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_NE2A1_17", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_LH10_17", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_SW4END1_17", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_NW4A0_17", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SE4C0_17", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_SE4BEG0_17", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_WW4C0_17", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_EE4C3_17", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_NW4END1_17", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_EE4B3_17", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NE4C1_17", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE2A0_17", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_SE4BEG1_17", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_LH11_17", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EL1BEG1_17", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NE2A3_17", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_WR1END0_17", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_NE4C2_17", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW4A3_17", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_SE4BEG3_17", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_WW4B3_17", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_EE2BEG1_17", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_EE4BEG3_17", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WW4B2_17", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE4C2_17", + "INT_FEEDTHRU_2_EE4C2" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW4C0_6", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4END2_6", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW2A3_6", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4BEG0_6", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_6", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_6", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A3_6", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4A1_6", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4B0_6", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SW4A3_6", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_NE4BEG2_6", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE4B0_6", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE4C1_6", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A1_6", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END1_6", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_6", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_6", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_6", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C1_6", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW4A1_6", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_ER1BEG0_6", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_6", + "VBRK_LH1" + ], + [ + "CMT_TOP_EE4BEG2_6", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG2_6", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SE2A0_6", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WL1END2_6", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A1_6", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WR1END3_6", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NE2A2_6", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_LH4_6", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END1_6", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH8_6", + "VBRK_LH8" + ], + [ + "CMT_TOP_SE4BEG2_6", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4END2_6", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH6_6", + "VBRK_LH6" + ], + [ + "CMT_TOP_LH3_6", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C2_6", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NE2A3_6", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE4C3_6", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4A0_6", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C3_6", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_ER1BEG3_6", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_6", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WR1END2_6", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END0_6", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4C0_6", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SE4C0_6", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SE2A3_6", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_LH2_6", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW2END1_6", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW2END3_6", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE2A0_6", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NE4C0_6", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WW4C3_6", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END1_6", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4BEG3_6", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A1_6", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4B3_6", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4B1_6", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A1_6", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WL1END3_6", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH7_6", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW2A0_6", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A0_6", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NW2A1_6", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2BEG0_6", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_6", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE2BEG1_6", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4END3_6", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NW4END3_6", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4BEG1_6", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_6", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_SW4END2_6", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NW4A3_6", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4BEG0_6", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SW4A2_6", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4C1_6", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2A0_6", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4END0_6", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_ER1BEG2_6", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2A3_6", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW2A0_6", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_LH11_6", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH9_6", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2BEG3_6", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WW4A3_6", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4A0_6", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE2A0_6", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NW2A2_6", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_6", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C3_6", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4A1_6", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WR1END0_6", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4C2_6", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE4C1_6", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG3_6", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW4B3_6", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END2_6", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A2_6", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4B2_6", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW4A0_6", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW2A1_6", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH5_6", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4B1_6", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_NE4BEG1_6", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH10_6", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_6", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4A2_6", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG1_6", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE2A1_6", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C2_6", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END0_6", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SE4BEG0_6", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_6", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE4A2_6", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4END0_6", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4BEG3_6", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A3_6", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_6", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_6", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A2_6", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NW2A3_6", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_6", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE4C2_6", + "VBRK_SE4C2" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "B_TERM_UTURN_INT_LVB_L1", + "LVB_L11" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "FAN_BOUNCE4" + ], + [ + "B_TERM_UTURN_INT_SW6B0", + "NW6C3" + ], + [ + "B_TERM_UTURN_INT_SS6B1", + "NN6C2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG0", + "SL1BEG0" + ], + [ + "B_TERM_UTURN_INT_LV_L2", + "LV_L2" + ], + [ + "B_TERM_UTURN_INT_SS6C2", + "SS6C2" + ], + [ + "B_TERM_UTURN_INT_SS6E0", + "SS6E0" + ], + [ + "B_TERM_UTURN_INT_SW6A3", + "NW6B0" + ], + [ + "B_TERM_UTURN_INT_SW6B0", + "SW6B0" + ], + [ + "B_TERM_UTURN_INT_SS6BEG0", + "NN6A3" + ], + [ + "B_TERM_UTURN_INT_SS6A2", + "NN6B1" + ], + [ + "B_TERM_UTURN_INT_SS6C2", + "NN6D1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG0", + "SS2BEG0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG1", + "NL1END2" + ], + [ + "B_TERM_UTURN_INT_SW6B1", + "NW6C2" + ], + [ + "B_TERM_UTURN_INT_SS6C3", + "SS6C3" + ], + [ + "B_TERM_UTURN_INT_ER1END_N3_3", + "ER1END_N3_3" + ], + [ + "B_TERM_UTURN_INT_LV_L3", + "LV_L3" + ], + [ + "B_TERM_UTURN_INT_LV_L6", + "LV_L13" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "FAN_BOUNCE0" + ], + [ + "B_TERM_UTURN_INT_SS6A3", + "NN6B0" + ], + [ + "B_TERM_UTURN_INT_SE6D1", + "NE6E2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG1", + "NR1END2" + ], + [ + "B_TERM_UTURN_INT_SW6C0", + "SW6C0" + ], + [ + "B_TERM_UTURN_INT_SE6A0", + "SE6A0" + ], + [ + "B_TERM_UTURN_INT_LVB_L0", + "LVB_L1" + ], + [ + "B_TERM_UTURN_INT_LV_L18", + "LV_L18" + ], + [ + "B_TERM_UTURN_INT_SW6A0", + "NW6B3" + ], + [ + "B_TERM_UTURN_INT_SS6E0", + "NN6END3" + ], + [ + "B_TERM_UTURN_INT_WR1END0", + "WR1END0" + ], + [ + "B_TERM_UTURN_INT_SE6A2", + "SE6A2" + ], + [ + "B_TERM_UTURN_INT_SS6D1", + "SS6D1" + ], + [ + "B_TERM_UTURN_INT_LVB_L2", + "LVB_L10" + ], + [ + "B_TERM_UTURN_INT_LV_L6", + "LV_L6" + ], + [ + "B_TERM_UTURN_INT_SE6B0", + "SE6B0" + ], + [ + "B_TERM_UTURN_INT_LV_L5", + "LV_L5" + ], + [ + "B_TERM_UTURN_INT_SS6A3", + "SS6A3" + ], + [ + "B_TERM_UTURN_INT_ER1BEG0", + "EL1BEG_N3" + ], + [ + "B_TERM_UTURN_INT_SW6B3", + "NW6C0" + ], + [ + "B_TERM_UTURN_INT_LV_L9", + "LV_L10" + ], + [ + "B_TERM_UTURN_INT_LV_L7", + "LV_L7" + ], + [ + "B_TERM_UTURN_INT_SE6C2", + "SE6C2" + ], + [ + "B_TERM_UTURN_INT_SE6B2", + "SE6B2" + ], + [ + "B_TERM_UTURN_INT_SE6B0", + "NE6C3" + ], + [ + "B_TERM_UTURN_INT_SE6D0", + "NE6E3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG3", + "NN6A0" + ], + [ + "B_TERM_UTURN_INT_SW6D3", + "NW6E0" + ], + [ + "B_TERM_UTURN_INT_SS6BEG0", + "SS6BEG0" + ], + [ + "B_TERM_UTURN_INT_SE6D2", + "NE6E1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG1", + "NN2A2" + ], + [ + "B_TERM_UTURN_INT_SS6D1", + "NN6E2" + ], + [ + "B_TERM_UTURN_INT_SE6C3", + "SE6C3" + ], + [ + "B_TERM_UTURN_INT_SS2A2", + "NN2END1" + ], + [ + "B_TERM_UTURN_INT_SE6D1", + "SE6D1" + ], + [ + "B_TERM_UTURN_INT_SS6D0", + "NN6E3" + ], + [ + "B_TERM_UTURN_INT_SS6B3", + "NN6C0" + ], + [ + "B_TERM_UTURN_INT_SE6A1", + "NE6B2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG2", + "SL1BEG2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "FAN_BOUNCE6" + ], + [ + "B_TERM_UTURN_INT_SE6C3", + "NE6D0" + ], + [ + "B_TERM_UTURN_INT_SE6A0", + "NE6B3" + ], + [ + "B_TERM_UTURN_INT_SE6A2", + "NE6B1" + ], + [ + "B_TERM_UTURN_INT_SS6E3", + "SS6E3" + ], + [ + "B_TERM_UTURN_INT_SS2A0", + "SS2A0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG2", + "SS2BEG2" + ], + [ + "B_TERM_UTURN_INT_ER1BEG0", + "ER1BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG3", + "NR1END0" + ], + [ + "B_TERM_UTURN_INT_SW6A3", + "SW6A3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG3", + "NW2A0" + ], + [ + "B_TERM_UTURN_INT_SS6C1", + "NN6D2" + ], + [ + "B_TERM_UTURN_INT_SE6C0", + "NE6D3" + ], + [ + "B_TERM_UTURN_INT_SW6C0", + "NW6D3" + ], + [ + "B_TERM_UTURN_INT_SW6B2", + "SW6B2" + ], + [ + "B_TERM_UTURN_INT_SS6C1", + "SS6C1" + ], + [ + "B_TERM_UTURN_INT_SS6D3", + "SS6D3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG1", + "SE2BEG1" + ], + [ + "B_TERM_UTURN_INT_SS6B1", + "SS6B1" + ], + [ + "B_TERM_UTURN_INT_SW6D0", + "NW6E3" + ], + [ + "B_TERM_UTURN_INT_SS6B0", + "SS6B0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG1", + "NE2A2" + ], + [ + "B_TERM_UTURN_INT_LV_L2", + "LV_L17" + ], + [ + "B_TERM_UTURN_INT_LV_L18", + "LV_L1" + ], + [ + "B_TERM_UTURN_INT_SW6D2", + "NW6E1" + ], + [ + "B_TERM_UTURN_INT_SS6BEG3", + "SS6BEG3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG0", + "SE2BEG0" + ], + [ + "B_TERM_UTURN_INT_SW6B3", + "SW6B3" + ], + [ + "B_TERM_UTURN_INT_SW6C1", + "SW6C1" + ], + [ + "B_TERM_UTURN_INT_SE6C1", + "NE6D2" + ], + [ + "B_TERM_UTURN_INT_SW6A2", + "NW6B1" + ], + [ + "B_TERM_UTURN_INT_SE6D3", + "SE6D3" + ], + [ + "B_TERM_UTURN_INT_LVB_L4", + "LVB_L8" + ], + [ + "B_TERM_UTURN_INT_SW6D2", + "SW6D2" + ], + [ + "B_TERM_UTURN_INT_LVB_L5", + "LVB_L7" + ], + [ + "B_TERM_UTURN_INT_LV_L4", + "LV_L4" + ], + [ + "B_TERM_UTURN_INT_SR1BEG2", + "NL1END1" + ], + [ + "B_TERM_UTURN_INT_SS2A3", + "SS2A3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG2", + "SS6BEG2" + ], + [ + "B_TERM_UTURN_INT_SS6E2", + "SS6E2" + ], + [ + "B_TERM_UTURN_INT_SW6C1", + "NW6D2" + ], + [ + "B_TERM_UTURN_INT_SS6E3", + "NN6END0" + ], + [ + "B_TERM_UTURN_INT_SS6E1", + "SS6E1" + ], + [ + "B_TERM_UTURN_INT_SE6D0", + "SE6D0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG2", + "SR1BEG2" + ], + [ + "B_TERM_UTURN_INT_LVB_L2", + "LVB_L3" + ], + [ + "B_TERM_UTURN_INT_SS6B2", + "SS6B2" + ], + [ + "B_TERM_UTURN_INT_SS6A1", + "SS6A1" + ], + [ + "B_TERM_UTURN_INT_WR1BEG0", + "WL1BEG_N3" + ], + [ + "B_TERM_UTURN_INT_SW6D1", + "SW6D1" + ], + [ + "B_TERM_UTURN_INT_SS6B0", + "NN6C3" + ], + [ + "B_TERM_UTURN_INT_SS6C0", + "SS6C0" + ], + [ + "B_TERM_UTURN_INT_LV_L3", + "LV_L16" + ], + [ + "B_TERM_UTURN_INT_SS2BEG3", + "SS2BEG3" + ], + [ + "B_TERM_UTURN_INT_SS2BEG1", + "SS2BEG1" + ], + [ + "B_TERM_UTURN_INT_SW6C2", + "SW6C2" + ], + [ + "B_TERM_UTURN_INT_LV_L8", + "LV_L11" + ], + [ + "B_TERM_UTURN_INT_SW2BEG0", + "SW2BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG1", + "SL1BEG1" + ], + [ + "B_TERM_UTURN_INT_SS6D3", + "NN6E0" + ], + [ + "B_TERM_UTURN_INT_LVB_L4", + "LVB_L5" + ], + [ + "B_TERM_UTURN_INT_SS6A0", + "NN6B3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG1", + "SW2BEG1" + ], + [ + "B_TERM_UTURN_INT_SW6A1", + "NW6B2" + ], + [ + "B_TERM_UTURN_INT_SS6C3", + "NN6D0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG1", + "SR1BEG1" + ], + [ + "B_TERM_UTURN_INT_LVB_L0", + "LVB_L12" + ], + [ + "B_TERM_UTURN_INT_SS6A0", + "SS6A0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG2", + "NE2A1" + ], + [ + "B_TERM_UTURN_INT_SW6C2", + "NW6D1" + ], + [ + "B_TERM_UTURN_INT_SW6C3", + "SW6C3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG1", + "SS6BEG1" + ], + [ + "B_TERM_UTURN_INT_SR1BEG3", + "SR1BEG3" + ], + [ + "B_TERM_UTURN_INT_LV_L9", + "LV_L9" + ], + [ + "B_TERM_UTURN_INT_SE6D3", + "NE6E0" + ], + [ + "B_TERM_UTURN_INT_SE6B3", + "SE6B3" + ], + [ + "B_TERM_UTURN_INT_WR1END0", + "WL1END_N1_3" + ], + [ + "B_TERM_UTURN_INT_SW6D0", + "SW6D0" + ], + [ + "B_TERM_UTURN_INT_SW6A2", + "SW6A2" + ], + [ + "B_TERM_UTURN_INT_SW2BEG0", + "NW2A3" + ], + [ + "B_TERM_UTURN_INT_LV_L4", + "LV_L15" + ], + [ + "B_TERM_UTURN_INT_SR1BEG3", + "NL1END0" + ], + [ + "B_TERM_UTURN_INT_SS6E1", + "NN6END2" + ], + [ + "B_TERM_UTURN_INT_SS2A0", + "NN2END3" + ], + [ + "B_TERM_UTURN_INT_SW6C3", + "NW6D0" + ], + [ + "B_TERM_UTURN_INT_SE6B2", + "NE6C1" + ], + [ + "B_TERM_UTURN_INT_SW2BEG1", + "NW2A2" + ], + [ + "B_TERM_UTURN_INT_SS6C0", + "NN6D3" + ], + [ + "B_TERM_UTURN_INT_SS6A1", + "NN6B2" + ], + [ + "B_TERM_UTURN_INT_SS6A2", + "SS6A2" + ], + [ + "B_TERM_UTURN_INT_SS6E2", + "NN6END1" + ], + [ + "B_TERM_UTURN_INT_SS6D2", + "SS6D2" + ], + [ + "B_TERM_UTURN_INT_SS6B2", + "NN6C1" + ], + [ + "B_TERM_UTURN_INT_LVB_L5", + "LVB_L6" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "BYP_BOUNCE_N3_7" + ], + [ + "B_TERM_UTURN_INT_SW6D1", + "NW6E2" + ], + [ + "B_TERM_UTURN_INT_ER1END_N3_3", + "EL1END0" + ], + [ + "B_TERM_UTURN_INT_SS2A3", + "NN2END0" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "BYP_BOUNCE_N3_6" + ], + [ + "B_TERM_UTURN_INT_SS6D2", + "NN6E1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG2", + "NN2A1" + ], + [ + "B_TERM_UTURN_INT_LV_L5", + "LV_L14" + ], + [ + "B_TERM_UTURN_INT_SE6B1", + "SE6B1" + ], + [ + "B_TERM_UTURN_INT_SW2BEG3", + "SW2BEG3" + ], + [ + "B_TERM_UTURN_INT_SE6C1", + "SE6C1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "BYP_BOUNCE_N3_2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "BYP_BOUNCE_N3_3" + ], + [ + "B_TERM_UTURN_INT_SS6D0", + "SS6D0" + ], + [ + "B_TERM_UTURN_INT_SW2BEG2", + "NW2A1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "FAN_BOUNCE2" + ], + [ + "B_TERM_UTURN_INT_SS6BEG2", + "NN6A1" + ], + [ + "B_TERM_UTURN_INT_SS2A1", + "NN2END2" + ], + [ + "B_TERM_UTURN_INT_SE6B3", + "NE6C0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG3", + "NE2A0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG3", + "NN2A0" + ], + [ + "B_TERM_UTURN_INT_SW6B2", + "NW6C1" + ], + [ + "B_TERM_UTURN_INT_SW6A0", + "SW6A0" + ], + [ + "B_TERM_UTURN_INT_LV_L8", + "LV_L8" + ], + [ + "B_TERM_UTURN_INT_SL1BEG2", + "NR1END1" + ], + [ + "B_TERM_UTURN_INT_SE2BEG0", + "NE2A3" + ], + [ + "B_TERM_UTURN_INT_SW6B1", + "SW6B1" + ], + [ + "B_TERM_UTURN_INT_SS2A2", + "SS2A2" + ], + [ + "B_TERM_UTURN_INT_LVB_L1", + "LVB_L2" + ], + [ + "B_TERM_UTURN_INT_SS6B3", + "SS6B3" + ], + [ + "B_TERM_UTURN_INT_SE6D2", + "SE6D2" + ], + [ + "B_TERM_UTURN_INT_SW6END_N0_3", + "SW6END_N0_3" + ], + [ + "B_TERM_UTURN_INT_SE6A3", + "SE6A3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG2", + "SW2BEG2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG0", + "NR1END3" + ], + [ + "B_TERM_UTURN_INT_LVB_L3", + "LVB_L4" + ], + [ + "B_TERM_UTURN_INT_SE6C2", + "NE6D1" + ], + [ + "B_TERM_UTURN_INT_WR1BEG0", + "WR1BEG0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG0", + "NN2A3" + ], + [ + "B_TERM_UTURN_INT_SE6C0", + "SE6C0" + ], + [ + "B_TERM_UTURN_INT_LV_L7", + "LV_L12" + ], + [ + "B_TERM_UTURN_INT_SW6END_N0_3", + "NW6END0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG3", + "SL1BEG3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG3", + "SE2BEG3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG1", + "NN6A2" + ], + [ + "B_TERM_UTURN_INT_SE2BEG2", + "SE2BEG2" + ], + [ + "B_TERM_UTURN_INT_SE6A1", + "SE6A1" + ], + [ + "B_TERM_UTURN_INT_SE6B1", + "NE6C2" + ], + [ + "B_TERM_UTURN_INT_SW6D3", + "SW6D3" + ], + [ + "B_TERM_UTURN_INT_SE6A3", + "NE6B0" + ], + [ + "B_TERM_UTURN_INT_SW6A1", + "SW6A1" + ], + [ + "B_TERM_UTURN_INT_SS2A1", + "SS2A1" + ], + [ + "B_TERM_UTURN_INT_LVB_L3", + "LVB_L9" + ] + ], + "tile_types": [ + "BRKH_B_TERM_INT", + "INT_L" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "BRKH_INT_SW6D0", + "SW6D0" + ], + [ + "BRKH_INT_NN6B3", + "NN6B3" + ], + [ + "BRKH_INT_NW6A1", + "NW6A1" + ], + [ + "BRKH_INT_SW2A3", + "SW2A3" + ], + [ + "BRKH_INT_SE6D0", + "SE6D0" + ], + [ + "BRKH_INT_WW4END_S0_0", + "WW4END_S0_0" + ], + [ + "BRKH_INT_LV10", + "LV10" + ], + [ + "BRKH_INT_LVB11", + "LVB10" + ], + [ + "BRKH_INT_NN6E1", + "NN6E1" + ], + [ + "BRKH_INT_NR1BEG1", + "NR1BEG1" + ], + [ + "BRKH_INT_LV17", + "LV17" + ], + [ + "BRKH_INT_NL1BEG1", + "NL1BEG1" + ], + [ + "BRKH_INT_SS2END_N0_3", + "SS2END3" + ], + [ + "BRKH_INT_BYP_BOUNCE7", + "BYP_BOUNCE7" + ], + [ + "BRKH_INT_SS2A3", + "SS2A3" + ], + [ + "BRKH_INT_SR1END_N3_3", + "SR1END3" + ], + [ + "BRKH_INT_SS6C1", + "SS6C1" + ], + [ + "BRKH_INT_WR1END_S1_0", + "WR1END_S1_0" + ], + [ + "BRKH_INT_SW6B0", + "SW6B0" + ], + [ + "BRKH_INT_SS6D0", + "SS6D0" + ], + [ + "BRKH_INT_NE6C0", + "NE6C0" + ], + [ + "BRKH_INT_NL1BEG0", + "NL1BEG0" + ], + [ + "BRKH_INT_LVB10", + "LVB9" + ], + [ + "BRKH_INT_SL1END1", + "SL1END1" + ], + [ + "BRKH_INT_NW6C2", + "NW6C2" + ], + [ + "BRKH_INT_NN2BEG2", + "NN2BEG2" + ], + [ + "BRKH_INT_NE6A0", + "NE6A0" + ], + [ + "BRKH_INT_NW6D3", + "NW6D3" + ], + [ + "BRKH_INT_NE6D3", + "NE6D3" + ], + [ + "BRKH_INT_LVB2", + "LVB1" + ], + [ + "BRKH_INT_NN6D0", + "NN6D0" + ], + [ + "BRKH_INT_SE6D2", + "SE6D2" + ], + [ + "BRKH_INT_NN6BEG3", + "NN6BEG3" + ], + [ + "BRKH_INT_SE6E1", + "SE6E1" + ], + [ + "BRKH_INT_LV9", + "LV9" + ], + [ + "BRKH_INT_SE6B0", + "SE6B0" + ], + [ + "BRKH_INT_NN6C1", + "NN6C1" + ], + [ + "BRKH_INT_NN6A1", + "NN6A1" + ], + [ + "BRKH_INT_SW6B1", + "SW6B1" + ], + [ + "BRKH_INT_SS6A3", + "SS6A3" + ], + [ + "BRKH_INT_SE6E3", + "SE6E3" + ], + [ + "BRKH_INT_SE6B1", + "SE6B1" + ], + [ + "BRKH_INT_LV1", + "LV1" + ], + [ + "BRKH_INT_NW6B3", + "NW6B3" + ], + [ + "BRKH_INT_NN6E3", + "NN6E3" + ], + [ + "BRKH_INT_SE6C1", + "SE6C1" + ], + [ + "BRKH_INT_NW6C1", + "NW6C1" + ], + [ + "BRKH_INT_SL1END3", + "SL1END3" + ], + [ + "BRKH_INT_NW6C3", + "NW6C3" + ], + [ + "BRKH_INT_SS6A0", + "SS6A0" + ], + [ + "BRKH_INT_SS2A2", + "SS2A2" + ], + [ + "BRKH_INT_LV12", + "LV12" + ], + [ + "BRKH_INT_SE6B2", + "SE6B2" + ], + [ + "BRKH_INT_NE6D0", + "NE6D0" + ], + [ + "BRKH_INT_NN6END_S1_0", + "NN6END_S1_0" + ], + [ + "BRKH_INT_NN6A3", + "NN6A3" + ], + [ + "BRKH_INT_NE6B3", + "NE6B3" + ], + [ + "BRKH_INT_SR1END1", + "SR1END1" + ], + [ + "BRKH_INT_NN6BEG0", + "NN6BEG0" + ], + [ + "BRKH_INT_LV8", + "LV8" + ], + [ + "BRKH_INT_SW6C1", + "SW6C1" + ], + [ + "BRKH_INT_SE6D1", + "SE6D1" + ], + [ + "BRKH_INT_SS6D1", + "SS6D1" + ], + [ + "BRKH_INT_NW6A2", + "NW6A2" + ], + [ + "BRKH_INT_SW6B2", + "SW6B2" + ], + [ + "BRKH_INT_NW2BEG3", + "NW2BEG3" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_6", + "FAN_BOUNCE_S3_6" + ], + [ + "BRKH_INT_NN6B0", + "NN6B0" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_4", + "FAN_BOUNCE_S3_4" + ], + [ + "BRKH_INT_SS6END_N0_3", + "SS6END3" + ], + [ + "BRKH_INT_SE6C2", + "SE6C2" + ], + [ + "BRKH_INT_SE6C3", + "SE6C3" + ], + [ + "BRKH_INT_WR1BEG_S0", + "WR1BEG_S0" + ], + [ + "BRKH_INT_SW6D2", + "SW6D2" + ], + [ + "BRKH_INT_SS6END3", + "SS6END3" + ], + [ + "BRKH_INT_LV15", + "LV15" + ], + [ + "BRKH_INT_LV5", + "LV5" + ], + [ + "BRKH_INT_NW6D2", + "NW6D2" + ], + [ + "BRKH_INT_ER1BEG_S0", + "ER1BEG_S0" + ], + [ + "BRKH_INT_SW6E3", + "SW6E3" + ], + [ + "BRKH_INT_SS6B1", + "SS6B1" + ], + [ + "BRKH_INT_LVB5", + "LVB4" + ], + [ + "BRKH_INT_NE2BEG0", + "NE2BEG0" + ], + [ + "BRKH_INT_NW6A3", + "NW6A3" + ], + [ + "BRKH_INT_LV4", + "LV4" + ], + [ + "BRKH_INT_SS2A1", + "SS2A1" + ], + [ + "BRKH_INT_SW6C0", + "SW6C0" + ], + [ + "BRKH_INT_SE2A3", + "SE2A3" + ], + [ + "BRKH_INT_NN6A0", + "NN6A0" + ], + [ + "BRKH_INT_NN2A2", + "NN2A2" + ], + [ + "BRKH_INT_SW6D3", + "SW6D3" + ], + [ + "BRKH_INT_NE6A3", + "NE6A3" + ], + [ + "BRKH_INT_NE2BEG3", + "NE2BEG3" + ], + [ + "BRKH_INT_NE6B2", + "NE6B2" + ], + [ + "BRKH_INT_NN6E2", + "NN6E2" + ], + [ + "BRKH_INT_BYP_BOUNCE3", + "BYP_BOUNCE3" + ], + [ + "BRKH_INT_NE6B1", + "NE6B1" + ], + [ + "BRKH_INT_SS6END1", + "SS6END1" + ], + [ + "BRKH_INT_LVB9", + "LVB8" + ], + [ + "BRKH_INT_NN2BEG1", + "NN2BEG1" + ], + [ + "BRKH_INT_NW6B0", + "NW6B0" + ], + [ + "BRKH_INT_SE6C0", + "SE6C0" + ], + [ + "BRKH_INT_NW6B2", + "NW6B2" + ], + [ + "BRKH_INT_SS6E1", + "SS6E1" + ], + [ + "BRKH_INT_LV16", + "LV16" + ], + [ + "BRKH_INT_NW2END_S0_0", + "NW2END_S0_0" + ], + [ + "BRKH_INT_NW6A0", + "NW6A0" + ], + [ + "BRKH_INT_NN6D1", + "NN6D1" + ], + [ + "BRKH_INT_NN6BEG1", + "NN6BEG1" + ], + [ + "BRKH_INT_SE2A2", + "SE2A2" + ], + [ + "BRKH_INT_SL1END2", + "SL1END2" + ], + [ + "BRKH_INT_SR1END2", + "SR1END2" + ], + [ + "BRKH_INT_NW2BEG1", + "NW2BEG1" + ], + [ + "BRKH_INT_NE6C2", + "NE6C2" + ], + [ + "BRKH_INT_WL1BEG3", + "WL1BEG3" + ], + [ + "BRKH_INT_NW6D1", + "NW6D1" + ], + [ + "BRKH_INT_NL1BEG2", + "NL1BEG2" + ], + [ + "BRKH_INT_SE6E0", + "SE6E0" + ], + [ + "BRKH_INT_SS6B0", + "SS6B0" + ], + [ + "BRKH_INT_NN2A1", + "NN2A1" + ], + [ + "BRKH_INT_SW6E0", + "SW6E0" + ], + [ + "BRKH_INT_SW2END3", + "SW2END3" + ], + [ + "BRKH_INT_SW6C2", + "SW6C2" + ], + [ + "BRKH_INT_SS6A1", + "SS6A1" + ], + [ + "BRKH_INT_NN2END_S2_0", + "NN2END_S2_0" + ], + [ + "BRKH_INT_SS6E3", + "SS6E3" + ], + [ + "BRKH_INT_SR1END3", + "SR1END3" + ], + [ + "BRKH_INT_SW6E1", + "SW6E1" + ], + [ + "BRKH_INT_LVB4", + "LVB3" + ], + [ + "BRKH_INT_SE6B3", + "SE6B3" + ], + [ + "BRKH_INT_SW6C3", + "SW6C3" + ], + [ + "BRKH_INT_NE6A2", + "NE6A2" + ], + [ + "BRKH_INT_NN6BEG2", + "NN6BEG2" + ], + [ + "BRKH_INT_NN2A3", + "NN2A3" + ], + [ + "BRKH_INT_NR1BEG0", + "NR1BEG0" + ], + [ + "BRKH_INT_LVB3", + "LVB2" + ], + [ + "BRKH_INT_NL1END_S3_0", + "NL1END_S3_0" + ], + [ + "BRKH_INT_SW6E2", + "SW6E2" + ], + [ + "BRKH_INT_SS2END2", + "SS2END2" + ], + [ + "BRKH_INT_SW2A1", + "SW2A1" + ], + [ + "BRKH_INT_NN6C3", + "NN6C3" + ], + [ + "BRKH_INT_SW2A0", + "SW2A0" + ], + [ + "BRKH_INT_NE2BEG1", + "NE2BEG1" + ], + [ + "BRKH_INT_NN6B1", + "NN6B1" + ], + [ + "BRKH_INT_NR1BEG2", + "NR1BEG2" + ], + [ + "BRKH_INT_SS6C2", + "SS6C2" + ], + [ + "BRKH_INT_NW2BEG2", + "NW2BEG2" + ], + [ + "BRKH_INT_LV7", + "LV7" + ], + [ + "BRKH_INT_SW2A2", + "SW2A2" + ], + [ + "BRKH_INT_NN2A0", + "NN2A0" + ], + [ + "BRKH_INT_EL1END_S3_0", + "EL1END_S3_0" + ], + [ + "BRKH_INT_NN6D2", + "NN6D2" + ], + [ + "BRKH_INT_SS6C0", + "SS6C0" + ], + [ + "BRKH_INT_NW6D0", + "NW6D0" + ], + [ + "BRKH_INT_SS6B3", + "SS6B3" + ], + [ + "BRKH_INT_NN6D3", + "NN6D3" + ], + [ + "BRKH_INT_NE6C1", + "NE6C1" + ], + [ + "BRKH_INT_SS2END1", + "SS2END1" + ], + [ + "BRKH_INT_SW6B3", + "SW6B3" + ], + [ + "BRKH_INT_SS6D2", + "SS6D2" + ], + [ + "BRKH_INT_SS6E2", + "SS6E2" + ], + [ + "BRKH_INT_NN6A2", + "NN6A2" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_2", + "FAN_BOUNCE_S3_2" + ], + [ + "BRKH_INT_LV3", + "LV3" + ], + [ + "BRKH_INT_LVB1", + "LVB0" + ], + [ + "BRKH_INT_ER1END3", + "ER1END3" + ], + [ + "BRKH_INT_WL1END3", + "WL1END3" + ], + [ + "BRKH_INT_NE6D1", + "NE6D1" + ], + [ + "BRKH_INT_SW6D1", + "SW6D1" + ], + [ + "BRKH_INT_NN2BEG0", + "NN2BEG0" + ], + [ + "BRKH_INT_SS6D3", + "SS6D3" + ], + [ + "BRKH_INT_WW2END3", + "WW2END3" + ], + [ + "BRKH_INT_NE2BEG2", + "NE2BEG2" + ], + [ + "BRKH_INT_SE2A1", + "SE2A1" + ], + [ + "BRKH_INT_SW6END3", + "SW6END3" + ], + [ + "BRKH_INT_NE6B0", + "NE6B0" + ], + [ + "BRKH_INT_LV11", + "LV11" + ], + [ + "BRKH_INT_NW6END_S0_0", + "NW6END_S0_0" + ], + [ + "BRKH_INT_NW2BEG0", + "NW2BEG0" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_0", + "FAN_BOUNCE_S3_0" + ], + [ + "BRKH_INT_LV14", + "LV14" + ], + [ + "BRKH_INT_SS6A2", + "SS6A2" + ], + [ + "BRKH_INT_SE2A0", + "SE2A0" + ], + [ + "BRKH_INT_LVB12", + "LVB11" + ], + [ + "BRKH_INT_SS2END0", + "SS2END0" + ], + [ + "BRKH_INT_NE6A1", + "NE6A1" + ], + [ + "BRKH_INT_NN2BEG3", + "NN2BEG3" + ], + [ + "BRKH_INT_NE6C3", + "NE6C3" + ], + [ + "BRKH_INT_LVB6", + "LVB5" + ], + [ + "BRKH_INT_SS2A0", + "SS2A0" + ], + [ + "BRKH_INT_NN6C0", + "NN6C0" + ], + [ + "BRKH_INT_NN6C2", + "NN6C2" + ], + [ + "BRKH_INT_NN6E0", + "NN6E0" + ], + [ + "BRKH_INT_NR1BEG3", + "NR1BEG3" + ], + [ + "BRKH_INT_SE6E2", + "SE6E2" + ], + [ + "BRKH_INT_BYP_BOUNCE2", + "BYP_BOUNCE2" + ], + [ + "BRKH_INT_NW6C0", + "NW6C0" + ], + [ + "BRKH_INT_LV2", + "LV2" + ], + [ + "BRKH_INT_SS2END3", + "SS2END3" + ], + [ + "BRKH_INT_LV6", + "LV6" + ], + [ + "BRKH_INT_SS6END0", + "SS6END0" + ], + [ + "BRKH_INT_NE6D2", + "NE6D2" + ], + [ + "BRKH_INT_LVB7", + "LVB6" + ], + [ + "BRKH_INT_LV13", + "LV13" + ], + [ + "BRKH_INT_EL1BEG3", + "EL1BEG3" + ], + [ + "BRKH_INT_LVB8", + "LVB7" + ], + [ + "BRKH_INT_SS6C3", + "SS6C3" + ], + [ + "BRKH_INT_NN6B2", + "NN6B2" + ], + [ + "BRKH_INT_NW6B1", + "NW6B1" + ], + [ + "BRKH_INT_SS6END2", + "SS6END2" + ], + [ + "BRKH_INT_NE2END_S3_0", + "NE2END_S3_0" + ], + [ + "BRKH_INT_SS6E0", + "SS6E0" + ], + [ + "BRKH_INT_BYP_BOUNCE6", + "BYP_BOUNCE6" + ], + [ + "BRKH_INT_LV0", + "LV0" + ], + [ + "BRKH_INT_SS6B2", + "SS6B2" + ], + [ + "BRKH_INT_SL1END0", + "SL1END0" + ], + [ + "BRKH_INT_SE6D3", + "SE6D3" + ] + ], + "tile_types": [ + "BRKH_INT", + "INT_R" + ] + }, + { + "grid_deltas": [ + 5, + 6 + ], + "wire_pairs": [ + [ + "PCIE_EE4A3_4", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_NW4END1_4", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_SW4END0_4", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_IMUX2_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_EE2A2_4", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_WL1END3_4", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_EE2BEG1_4", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX29_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_SE4BEG0_4", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_NE2A0_4", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_IMUX35_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_EE2A1_4", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_LH6_4", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_WL1END2_4", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_IMUX31_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_FAN6_L_4", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_FAN1_L_4", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_NE4C2_4", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_FAN3_L_4", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX9_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_IMUX21_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_LH5_4", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_EE2BEG3_4", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_WR1END2_4", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_WW4B1_4", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_ER1BEG2_4", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_BYP7_L_4", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_IMUX8_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_IMUX26_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_WL1END0_4", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_IMUX45_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_WW4C0_4", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_IMUX33_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_NW4A2_4", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_SW4END2_4", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_SW4A2_4", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_IMUX43_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_NW2A1_4", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_BYP0_L_4", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_CLK1_L_4", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_NW2A2_4", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_IMUX18_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_EE2BEG0_4", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_NW2A3_4", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_IMUX41_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_EL1BEG1_4", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_IMUX30_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_EE4B1_4", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_NE2A2_4", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_BYP3_L_4", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_NE4BEG3_4", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_FAN7_L_4", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_EE4C1_4", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_IMUX44_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_NE4C0_4", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_SE4C0_4", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_EE4A1_4", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_EE2A3_4", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_IMUX14_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_SE4BEG2_4", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_SW2A3_4", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_SE4C3_4", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_NE4BEG1_4", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_SE4BEG3_4", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_IMUX46_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_EE4A2_4", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_IMUX36_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_LH3_4", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_WW4A0_4", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_SW4END3_4", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_IMUX32_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_IMUX3_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_EE4C0_4", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX28_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_IMUX1_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_WW2A1_4", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_NE4C3_4", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_IMUX12_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_WR1END3_4", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_WW2END3_4", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_LH2_4", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_CTRL1_L_4", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_NE4BEG2_4", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_EE4BEG1_4", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_CLK0_L_4", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_EE2A0_4", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_EE4B0_4", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX47_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_IMUX40_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_IMUX4_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_ER1BEG0_4", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_EE4C3_4", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_WW2END0_4", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_NE4BEG0_4", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_IMUX10_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_IMUX19_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_LH9_4", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_IMUX42_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_NW4A1_4", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_NW4A0_4", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_SE2A2_4", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_EE4C2_4", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_EL1BEG2_4", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_BYP1_L_4", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_FAN4_L_4", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_WW4END1_4", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_NW4END0_4", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_NW4END2_4", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_WW4END2_4", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_WW4END3_4", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_SE2A0_4", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_IMUX20_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_LH12_4", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_EE4B3_4", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_IMUX6_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_ER1BEG3_4", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_FAN5_L_4", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_SE4BEG1_4", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_SW4A1_4", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_WR1END0_4", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_BYP2_L_4", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_WL1END1_4", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_FAN0_L_4", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_SW2A0_4", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX37_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_BYP5_L_4", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_EL1BEG3_4", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_BYP6_L_4", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_SW2A2_4", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_CTRL0_L_4", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_NE4C1_4", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_IMUX23_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_EL1BEG0_4", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_WW2END2_4", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_ER1BEG1_4", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_IMUX38_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_WW4END0_4", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_IMUX24_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_IMUX27_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_WW4A2_4", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_WW4A1_4", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_LH11_4", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_IMUX7_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_SW4A3_4", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_SE2A3_4", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_IMUX17_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_NE2A3_4", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_LH8_4", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_IMUX34_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_EE4BEG3_4", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_WW2A0_4", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_WW4C1_4", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_WW4C3_4", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_NE2A1_4", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_NW2A0_4", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_LH1_4", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_LH4_4", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_SE2A1_4", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_WW4A3_4", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_WR1END1_4", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_FAN2_L_4", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_SE4C2_4", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_SW2A1_4", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_WW4C2_4", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_WW2A2_4", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_IMUX25_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_EE2BEG2_4", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_BYP4_L_4", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_WW4B2_4", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_EE4BEG2_4", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX39_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_NW4END3_4", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_IMUX15_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_SW4A0_4", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_EE4B2_4", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_NW4A3_4", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_WW4B0_4", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_WW2END1_4", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_EE4BEG0_4", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX0_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_IMUX16_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_4", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_LH10_4", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_IMUX11_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_SE4C1_4", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_WW4B3_4", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_WW2A3_4", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_SW4END1_4", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_IMUX22_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_IMUX5_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_LH7_4", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_EE4A0_4", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_IMUX13_L_4", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4A3_10", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SE2A3_10", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG0_10", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END2_10", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW4C2_10", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_LH8_10", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4B2_10", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A1_10", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW4C0_10", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WL1END3_10", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WL1END0_10", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW2A0_10", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2END0_10", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE4C3_10", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE2BEG1_10", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_LH7_10", + "VBRK_LH7" + ], + [ + "CMT_TOP_EL1BEG1_10", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE4C2_10", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH10_10", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4B1_10", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4C0_10", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH12_10", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_10", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4BEG3_10", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW2END2_10", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW4A2_10", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG3_10", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE4A1_10", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_SW2A0_10", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE2BEG0_10", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE2A0_10", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH5_10", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW2A3_10", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW2A1_10", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WR1END2_10", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SW4END1_10", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW2A3_10", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SW4END2_10", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EL1BEG0_10", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH3_10", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END0_10", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A1_10", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SE4BEG2_10", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4C2_10", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WR1END3_10", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WR1END1_10", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NW4A0_10", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_10", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW4B1_10", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C2_10", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE4BEG3_10", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4BEG1_10", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EE4C1_10", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG2_10", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG3_10", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE4BEG3_10", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE2A1_10", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4A3_10", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_LH11_10", + "VBRK_LH11" + ], + [ + "CMT_TOP_SE4C1_10", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WL1END1_10", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW4B0_10", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2A2_10", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4BEG1_10", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW4A0_10", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END1_10", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_ER1BEG3_10", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WW4END2_10", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_ER1BEG0_10", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_10", + "VBRK_LH1" + ], + [ + "CMT_TOP_WW4C3_10", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END0_10", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW4END3_10", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_LH9_10", + "VBRK_LH9" + ], + [ + "CMT_TOP_NW2A2_10", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_10", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_LH6_10", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A0_10", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE2A2_10", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2BEG2_10", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW2END1_10", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4B0_10", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C1_10", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SW2A2_10", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG2_10", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_NE2A0_10", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE2A1_10", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_10", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW2A0_10", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4A2_10", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW4A1_10", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WR1END0_10", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4B2_10", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END0_10", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4C0_10", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_10", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4B3_10", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4A0_10", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END3_10", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WL1END2_10", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4A2_10", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4B3_10", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NE4C1_10", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A1_10", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2A2_10", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EE4C3_10", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NW4A2_10", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NE4BEG2_10", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_SW2A1_10", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4BEG0_10", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SE2A0_10", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4BEG1_10", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_10", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_10", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_SE2A2_10", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4END3_10", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE4C3_10", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4A3_10", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_ER1BEG2_10", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_LH2_10", + "VBRK_LH2" + ], + [ + "CMT_TOP_NE2A3_10", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2A3_10", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C0_10", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_ER1BEG1_10", + "VBRK_ER1BEG1" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -5, + 2 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_2" + ], + [ + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "PCIE_LOGIC_OUTS_B2_L_2" + ], + [ + "INT_INTERFACE_LH2", + "PCIE_LH2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "PCIE_LOGIC_OUTS_B18_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT21", + "PCIE_IMUX21_L_2" + ], + [ + "INT_INTERFACE_EE4C2", + "PCIE_EE4C2_2" + ], + [ + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "PCIE_LOGIC_OUTS_B23_L_2" + ], + [ + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT9", + "PCIE_IMUX9_L_2" + ], + [ + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_2" + ], + [ + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT3", + "PCIE_IMUX3_L_2" + ], + [ + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_2" + ], + [ + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT19", + "PCIE_IMUX19_L_2" + ], + [ + "INT_INTERFACE_LH3", + "PCIE_LH3_2" + ], + [ + "INT_INTERFACE_EE4A1", + "PCIE_EE4A1_2" + ], + [ + "INT_INTERFACE_EE4A2", + "PCIE_EE4A2_2" + ], + [ + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT13", + "PCIE_IMUX13_L_2" + ], + [ + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_2" + ], + [ + "INT_INTERFACE_FAN6", + "PCIE_FAN6_L_2" + ], + [ + "INT_INTERFACE_FAN1", + "PCIE_FAN1_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT42", + "PCIE_IMUX42_L_2" + ], + [ + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_2" + ], + [ + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_2" + ], + [ + "INT_INTERFACE_EE2A3", + "PCIE_EE2A3_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT23", + "PCIE_IMUX23_L_2" + ], + [ + "INT_INTERFACE_EE4A3", + "PCIE_EE4A3_2" + ], + [ + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT5", + "PCIE_IMUX5_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT37", + "PCIE_IMUX37_L_2" + ], + [ + "INT_INTERFACE_BYP0", + "PCIE_BYP0_L_2" + ], + [ + "INT_INTERFACE_LH8", + "PCIE_LH8_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "PCIE_LOGIC_OUTS_B11_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT46", + "PCIE_IMUX46_L_2" + ], + [ + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_2" + ], + [ + "INT_INTERFACE_CTRL1", + "PCIE_CTRL1_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT17", + "PCIE_IMUX17_L_2" + ], + [ + "INT_INTERFACE_EE2BEG1", + "PCIE_EE2BEG1_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "PCIE_LOGIC_OUTS_B20_L_2" + ], + [ + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "PCIE_LOGIC_OUTS_B8_L_2" + ], + [ + "INT_INTERFACE_BYP4", + "PCIE_BYP4_L_2" + ], + [ + "INT_INTERFACE_FAN3", + "PCIE_FAN3_L_2" + ], + [ + "INT_INTERFACE_CTRL0", + "PCIE_CTRL0_L_2" + ], + [ + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT36", + "PCIE_IMUX36_L_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "PCIE_LOGIC_OUTS_B7_L_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "PCIE_LOGIC_OUTS_B0_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT16", + "PCIE_IMUX16_L_2" + ], + [ + "INT_INTERFACE_CLK1", + "PCIE_CLK1_L_2" + ], + [ + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_2" + ], + [ + "INT_INTERFACE_EE2BEG3", + "PCIE_EE2BEG3_2" + ], + [ + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT14", + "PCIE_IMUX14_L_2" + ], + [ + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_2" + ], + [ + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_2" + ], + [ + "INT_INTERFACE_EE4B0", + "PCIE_EE4B0_2" + ], + [ + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_2" + ], + [ + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT20", + "PCIE_IMUX20_L_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "PCIE_LOGIC_OUTS_B6_L_2" + ], + [ + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_2" + ], + [ + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_2" + ], + [ + "INT_INTERFACE_ER1BEG0", + "PCIE_ER1BEG0_2" + ], + [ + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_2" + ], + [ + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT1", + "PCIE_IMUX1_L_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "PCIE_LOGIC_OUTS_B5_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT33", + "PCIE_IMUX33_L_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "PCIE_LOGIC_OUTS_B13_L_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "PCIE_LOGIC_OUTS_B16_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT34", + "PCIE_IMUX34_L_2" + ], + [ + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT44", + "PCIE_IMUX44_L_2" + ], + [ + "INT_INTERFACE_LH1", + "PCIE_LH1_2" + ], + [ + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT47", + "PCIE_IMUX47_L_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "PCIE_LOGIC_OUTS_B3_L_2" + ], + [ + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_2" + ], + [ + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "PCIE_LOGIC_OUTS_B1_L_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "PCIE_LOGIC_OUTS_B21_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT4", + "PCIE_IMUX4_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT22", + "PCIE_IMUX22_L_2" + ], + [ + "INT_INTERFACE_EE4A0", + "PCIE_EE4A0_2" + ], + [ + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT45", + "PCIE_IMUX45_L_2" + ], + [ + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_2" + ], + [ + "INT_INTERFACE_FAN2", + "PCIE_FAN2_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT10", + "PCIE_IMUX10_L_2" + ], + [ + "INT_INTERFACE_EE4C1", + "PCIE_EE4C1_2" + ], + [ + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_2" + ], + [ + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_2" + ], + [ + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "PCIE_LOGIC_OUTS_B9_L_2" + ], + [ + "INT_INTERFACE_LH10", + "PCIE_LH10_2" + ], + [ + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_2" + ], + [ + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_2" + ], + [ + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "PCIE_LOGIC_OUTS_B4_L_2" + ], + [ + "INT_INTERFACE_EL1BEG3", + "PCIE_EL1BEG3_2" + ], + [ + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_2" + ], + [ + "INT_INTERFACE_LH6", + "PCIE_LH6_2" + ], + [ + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_2" + ], + [ + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_2" + ], + [ + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "PCIE_LOGIC_OUTS_B19_L_2" + ], + [ + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT6", + "PCIE_IMUX6_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT32", + "PCIE_IMUX32_L_2" + ], + [ + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT27", + "PCIE_IMUX27_L_2" + ], + [ + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_2" + ], + [ + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT31", + "PCIE_IMUX31_L_2" + ], + [ + "INT_INTERFACE_CLK0", + "PCIE_CLK0_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT29", + "PCIE_IMUX29_L_2" + ], + [ + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_2" + ], + [ + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_2" + ], + [ + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_2" + ], + [ + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_2" + ], + [ + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT26", + "PCIE_IMUX26_L_2" + ], + [ + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_2" + ], + [ + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_2" + ], + [ + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_2" + ], + [ + "INT_INTERFACE_BYP2", + "PCIE_BYP2_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT38", + "PCIE_IMUX38_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT30", + "PCIE_IMUX30_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT40", + "PCIE_IMUX40_L_2" + ], + [ + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_2" + ], + [ + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_2" + ], + [ + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_2" + ], + [ + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_2" + ], + [ + "INT_INTERFACE_FAN4", + "PCIE_FAN4_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT24", + "PCIE_IMUX24_L_2" + ], + [ + "INT_INTERFACE_BYP6", + "PCIE_BYP6_L_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "PCIE_LOGIC_OUTS_B10_L_2" + ], + [ + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_2" + ], + [ + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT11", + "PCIE_IMUX11_L_2" + ], + [ + "INT_INTERFACE_BYP3", + "PCIE_BYP3_L_2" + ], + [ + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_2" + ], + [ + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_2" + ], + [ + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_2" + ], + [ + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_2" + ], + [ + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_2" + ], + [ + "INT_INTERFACE_LH12", + "PCIE_LH12_2" + ], + [ + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "PCIE_LOGIC_OUTS_B17_L_2" + ], + [ + "INT_INTERFACE_BYP7", + "PCIE_BYP7_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT39", + "PCIE_IMUX39_L_2" + ], + [ + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_2" + ], + [ + "INT_INTERFACE_FAN0", + "PCIE_FAN0_L_2" + ], + [ + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT43", + "PCIE_IMUX43_L_2" + ], + [ + "INT_INTERFACE_LH7", + "PCIE_LH7_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT28", + "PCIE_IMUX28_L_2" + ], + [ + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_2" + ], + [ + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "PCIE_LOGIC_OUTS_B12_L_2" + ], + [ + "INT_INTERFACE_EE2A2", + "PCIE_EE2A2_2" + ], + [ + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT25", + "PCIE_IMUX25_L_2" + ], + [ + "INT_INTERFACE_LH9", + "PCIE_LH9_2" + ], + [ + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_2" + ], + [ + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_2" + ], + [ + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT2", + "PCIE_IMUX2_L_2" + ], + [ + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_2" + ], + [ + "INT_INTERFACE_LH11", + "PCIE_LH11_2" + ], + [ + "INT_INTERFACE_EE2A1", + "PCIE_EE2A1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT35", + "PCIE_IMUX35_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT41", + "PCIE_IMUX41_L_2" + ], + [ + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT7", + "PCIE_IMUX7_L_2" + ], + [ + "INT_INTERFACE_BYP5", + "PCIE_BYP5_L_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "PCIE_LOGIC_OUTS_B14_L_2" + ], + [ + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT18", + "PCIE_IMUX18_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT0", + "PCIE_IMUX0_L_2" + ], + [ + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_2" + ], + [ + "INT_INTERFACE_FAN7", + "PCIE_FAN7_L_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "PCIE_LOGIC_OUTS_B22_L_2" + ], + [ + "INT_INTERFACE_BYP1", + "PCIE_BYP1_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT15", + "PCIE_IMUX15_L_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT8", + "PCIE_IMUX8_L_2" + ], + [ + "INT_INTERFACE_LH4", + "PCIE_LH4_2" + ], + [ + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_2" + ], + [ + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_2" + ], + [ + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT12", + "PCIE_IMUX12_L_2" + ], + [ + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "PCIE_LOGIC_OUTS_B15_L_2" + ], + [ + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_2" + ], + [ + "INT_INTERFACE_EE2BEG0", + "PCIE_EE2BEG0_2" + ], + [ + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_2" + ], + [ + "INT_INTERFACE_FAN5", + "PCIE_FAN5_L_2" + ], + [ + "INT_INTERFACE_EE4C0", + "PCIE_EE4C0_2" + ], + [ + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_2" + ], + [ + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_2" + ], + [ + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_2" + ], + [ + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_2" + ], + [ + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_2" + ], + [ + "INT_INTERFACE_LH5", + "PCIE_LH5_2" + ], + [ + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_2" + ], + [ + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_2" + ], + [ + "INT_INTERFACE_EE2A0", + "PCIE_EE2A0_2" + ], + [ + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_2" + ], + [ + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_2" + ], + [ + "INT_INTERFACE_EE2BEG2", + "PCIE_EE2BEG2_2" + ], + [ + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_2" + ] + ], + "tile_types": [ + "PCIE_INT_INTERFACE_L", + "PCIE_TOP" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ] + ], + "tile_types": [ + "HCLK_DSP_R", + "HCLK_INT_INTERFACE" + ] + }, + { + "grid_deltas": [ + -1, + -7 + ], + "wire_pairs": [ + [ + "CMT_TOP_EE4C0_11", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EL1BEG1_11", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG0_11", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH7_11", + "VBRK_LH7" + ], + [ + "CMT_TOP_LH3_11", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE2A0_11", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_ER1BEG1_11", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_NE4C1_11", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH2_11", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW2A1_11", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NE2A3_11", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_ER1BEG2_11", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NW4END2_11", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE4BEG3_11", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C3_11", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE2A2_11", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_SW2A0_11", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW4A1_11", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_LH9_11", + "VBRK_LH9" + ], + [ + "CMT_TOP_SE4C3_11", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WR1END0_11", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_11", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EL1BEG2_11", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_NE4BEG2_11", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_11", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4C2_11", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4C2_11", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW4C3_11", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_LH4_11", + "VBRK_LH4" + ], + [ + "CMT_TOP_NE4C2_11", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EE4BEG0_11", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NE2A0_11", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NW4A1_11", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG1_11", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4C1_11", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_EE2A1_11", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END1_11", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SE4C2_11", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A0_11", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE4B0_11", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_11", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW4B0_11", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C0_11", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4BEG2_11", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_LH11_11", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE2BEG3_11", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END2_11", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_11", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4A2_11", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EE4BEG3_11", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_NW4END3_11", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_LH1_11", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE4C0_11", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SW4END3_11", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SW4END1_11", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_11", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END1_11", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW2A3_11", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH8_11", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A0_11", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_11", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW4B3_11", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW4A2_11", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4B2_11", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE2A0_11", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WW2END3_11", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EE4A3_11", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SE4C1_11", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_ER1BEG0_11", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_NW4END1_11", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A3_11", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4A2_11", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4C3_11", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW2A0_11", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NE2A1_11", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW4A3_11", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NW2A3_11", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NE4BEG3_11", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_WW2A2_11", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG0_11", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW2END0_11", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2A3_11", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4A2_11", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG2_11", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW2A1_11", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SW4END2_11", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG0_11", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_EE4C1_11", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG1_11", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG1_11", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2BEG2_11", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SW2A1_11", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE2A2_11", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WR1END1_11", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW2A3_11", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW2A0_11", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW4B1_11", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C0_11", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4BEG1_11", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH12_11", + "VBRK_LH12" + ], + [ + "CMT_TOP_WW4END2_11", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW2A2_11", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_EE4A1_11", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH5_11", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4A0_11", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_SE2A1_11", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END2_11", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WL1END3_11", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_ER1BEG3_11", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WW4B2_11", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WL1END0_11", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW4END0_11", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_11", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A3_11", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4END3_11", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_11", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4A0_11", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A1_11", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH10_11", + "VBRK_LH10" + ], + [ + "CMT_TOP_SW4END0_11", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW4END1_11", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE2A2_11", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW2A2_11", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG0_11", + "VBRK_EL1BEG0" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 9 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_9" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_9" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_9" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_9" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_9" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_9" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_9" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_9" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_9" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_9" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_9" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_9" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_9" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_9" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_9" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_9" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_9" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_9" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_9" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_9" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_9" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_9" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_9" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_9" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_9" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_9" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_9" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_9" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_9" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_9" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_9" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_9" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_9" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_9" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_9" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_9" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_9" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_9" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_9" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_9" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_9" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_9" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_9" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_9" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_9" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_9" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_9" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_9" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_9" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_9" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_9" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_9" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_9" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_9" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_9" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_9" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_9" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_9" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_9" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_9" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_9" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_9" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_9" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_9" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_9" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_9" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_9" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_9" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_9" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_9" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_9" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_9" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_9" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_9" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_9" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_9" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_9" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_9" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_9" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_9" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_9" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_9" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_9" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_9" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_9" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_9" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_9" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_9" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_9" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_9" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_9" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_9" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_9" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_9" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_9" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_9" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_9" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_9" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_9" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_9" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_9" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_9" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_9" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_9" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_9" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_9" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_9" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_9" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_9" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_9" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_9" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_9" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_9" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_9" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_9" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_9" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_9" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_9" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_9" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_9" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_9" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_9" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_9" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_9" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_BOT_FUJI2" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "CMT_TOP_LH12_7", + "VBRK_LH12" + ], + [ + "CMT_TOP_SW4END1_7", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_7", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE4C2_7", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_ER1BEG3_7", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END1_7", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WL1END2_7", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_NW4A0_7", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WR1END2_7", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW4A2_7", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG3_7", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EL1BEG0_7", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH11_7", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW2END2_7", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4A1_7", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NE2A1_7", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SW2A2_7", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_ER1BEG0_7", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_7", + "VBRK_LH1" + ], + [ + "CMT_TOP_SW4A3_7", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH10_7", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4BEG3_7", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C3_7", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4END3_7", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_ER1BEG1_7", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_7", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW2END0_7", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END2_7", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NE4C0_7", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EL1BEG1_7", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4END0_7", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EE2BEG3_7", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4C1_7", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A2_7", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_7", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE2A3_7", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4A1_7", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_LH2_7", + "VBRK_LH2" + ], + [ + "CMT_TOP_EL1BEG2_7", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WL1END0_7", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4C1_7", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW2END1_7", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2BEG0_7", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4B0_7", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C2_7", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A0_7", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_7", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_EE4B2_7", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG2_7", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A0_7", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG0_7", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW4A1_7", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_SE2A1_7", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4END2_7", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE2A3_7", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW4C0_7", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_7", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_ER1BEG2_7", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SE4C0_7", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4BEG2_7", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_NE2A0_7", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4A3_7", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4BEG2_7", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_7", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4B3_7", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END3_7", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WW4C1_7", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WL1END3_7", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH9_7", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2A0_7", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG1_7", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_7", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_LH3_7", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_7", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE4BEG1_7", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EE4A2_7", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG0_7", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE4BEG2_7", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW4END3_7", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NE4BEG1_7", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A2_7", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NW4END0_7", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_7", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4A0_7", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END0_7", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_7", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW4END1_7", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH7_7", + "VBRK_LH7" + ], + [ + "CMT_TOP_SE4BEG1_7", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE4A3_7", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C2_7", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A3_7", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW2A1_7", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C3_7", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE2A2_7", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NE4C3_7", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE4C0_7", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WR1END1_7", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NW4END3_7", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_WW4B1_7", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C1_7", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_7", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE2A1_7", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_7", + "VBRK_LH5" + ], + [ + "CMT_TOP_SE4C2_7", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B0_7", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE2A0_7", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW4A1_7", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SW2A0_7", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW2A3_7", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW2A0_7", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_7", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EL1BEG3_7", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_NW4A2_7", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG3_7", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NW2A3_7", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW4C3_7", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_7", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_LH4_7", + "VBRK_LH4" + ], + [ + "CMT_TOP_LH8_7", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B3_7", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NE2A2_7", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4BEG0_7", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2A3_7", + "VBRK_EE2A3" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLBLL_LH7", + "CLBLM_LH7" + ], + [ + "CLBLL_NE4C3", + "CLBLM_NE4C3" + ], + [ + "CLBLL_EE2BEG2", + "CLBLM_EE2BEG2" + ], + [ + "CLBLL_LH2", + "CLBLM_LH2" + ], + [ + "CLBLL_NW4END1", + "CLBLM_NW4END1" + ], + [ + "CLBLL_WL1END3", + "CLBLM_WL1END3" + ], + [ + "CLBLL_LH8", + "CLBLM_LH8" + ], + [ + "CLBLL_WW4END1", + "CLBLM_WW4END1" + ], + [ + "CLBLL_SE4BEG2", + "CLBLM_SE4BEG2" + ], + [ + "CLBLL_EL1BEG1", + "CLBLM_EL1BEG1" + ], + [ + "CLBLL_LH12", + "CLBLM_LH12" + ], + [ + "CLBLL_SW2A1", + "CLBLM_SW2A1" + ], + [ + "CLBLL_WW4B3", + "CLBLM_WW4B3" + ], + [ + "CLBLL_NE2A0", + "CLBLM_NE2A0" + ], + [ + "CLBLL_MONITOR_P", + "CLBLM_MONITOR_P" + ], + [ + "CLBLL_WL1END0", + "CLBLM_WL1END0" + ], + [ + "CLBLL_SE4C3", + "CLBLM_SE4C3" + ], + [ + "CLBLL_WW4C0", + "CLBLM_WW4C0" + ], + [ + "CLBLL_WW2A1", + "CLBLM_WW2A1" + ], + [ + "CLBLL_WW4A3", + "CLBLM_WW4A3" + ], + [ + "CLBLL_WW2A0", + "CLBLM_WW2A0" + ], + [ + "CLBLL_NE4C2", + "CLBLM_NE4C2" + ], + [ + "CLBLL_EE4B1", + "CLBLM_EE4B1" + ], + [ + "CLBLL_MONITOR_N", + "CLBLM_MONITOR_N" + ], + [ + "CLBLL_EE4A0", + "CLBLM_EE4A0" + ], + [ + "CLBLL_WW4B2", + "CLBLM_WW4B2" + ], + [ + "CLBLL_WR1END1", + "CLBLM_WR1END1" + ], + [ + "CLBLL_NE4BEG2", + "CLBLM_NE4BEG2" + ], + [ + "CLBLL_EE2BEG0", + "CLBLM_EE2BEG0" + ], + [ + "CLBLL_EE2A3", + "CLBLM_EE2A3" + ], + [ + "CLBLL_WW4B1", + "CLBLM_WW4B1" + ], + [ + "CLBLL_SW4END1", + "CLBLM_SW4END1" + ], + [ + "CLBLL_LH5", + "CLBLM_LH5" + ], + [ + "CLBLL_NW2A2", + "CLBLM_NW2A2" + ], + [ + "CLBLL_LH9", + "CLBLM_LH9" + ], + [ + "CLBLL_SE4BEG1", + "CLBLM_SE4BEG1" + ], + [ + "CLBLL_NW4A2", + "CLBLM_NW4A2" + ], + [ + "CLBLL_LH4", + "CLBLM_LH4" + ], + [ + "CLBLL_EE4BEG3", + "CLBLM_EE4BEG3" + ], + [ + "CLBLL_NW2A1", + "CLBLM_NW2A1" + ], + [ + "CLBLL_WR1END0", + "CLBLM_WR1END0" + ], + [ + "CLBLL_WL1END2", + "CLBLM_WL1END2" + ], + [ + "CLBLL_SE2A0", + "CLBLM_SE2A0" + ], + [ + "CLBLL_EE4C1", + "CLBLM_EE4C1" + ], + [ + "CLBLL_EE4A3", + "CLBLM_EE4A3" + ], + [ + "CLBLL_EE4BEG0", + "CLBLM_EE4BEG0" + ], + [ + "CLBLL_NW4END0", + "CLBLM_NW4END0" + ], + [ + "CLBLL_EL1BEG3", + "CLBLM_EL1BEG3" + ], + [ + "CLBLL_NW2A0", + "CLBLM_NW2A0" + ], + [ + "CLBLL_EE2BEG1", + "CLBLM_EE2BEG1" + ], + [ + "CLBLL_EE2BEG3", + "CLBLM_EE2BEG3" + ], + [ + "CLBLL_EE4C2", + "CLBLM_EE4C2" + ], + [ + "CLBLL_WW2END3", + "CLBLM_WW2END3" + ], + [ + "CLBLL_EL1BEG0", + "CLBLM_EL1BEG0" + ], + [ + "CLBLL_NW4A3", + "CLBLM_NW4A3" + ], + [ + "CLBLL_EE4A1", + "CLBLM_EE4A1" + ], + [ + "CLBLL_WW2END1", + "CLBLM_WW2END1" + ], + [ + "CLBLL_SW2A0", + "CLBLM_SW2A0" + ], + [ + "CLBLL_SW2A2", + "CLBLM_SW2A2" + ], + [ + "CLBLL_WR1END2", + "CLBLM_WR1END2" + ], + [ + "CLBLL_EE4C3", + "CLBLM_EE4C3" + ], + [ + "CLBLL_SW4END3", + "CLBLM_SW4END3" + ], + [ + "CLBLL_NW2A3", + "CLBLM_NW2A3" + ], + [ + "CLBLL_WW4C3", + "CLBLM_WW4C3" + ], + [ + "CLBLL_SW4A3", + "CLBLM_SW4A3" + ], + [ + "CLBLL_ER1BEG3", + "CLBLM_ER1BEG3" + ], + [ + "CLBLL_ER1BEG0", + "CLBLM_ER1BEG0" + ], + [ + "CLBLL_EE4A2", + "CLBLM_EE4A2" + ], + [ + "CLBLL_WL1END1", + "CLBLM_WL1END1" + ], + [ + "CLBLL_EL1BEG2", + "CLBLM_EL1BEG2" + ], + [ + "CLBLL_SE4C1", + "CLBLM_SE4C1" + ], + [ + "CLBLL_EE2A1", + "CLBLM_EE2A1" + ], + [ + "CLBLL_SW4A0", + "CLBLM_SW4A0" + ], + [ + "CLBLL_NE4C0", + "CLBLM_NE4C0" + ], + [ + "CLBLL_SE4C0", + "CLBLM_SE4C0" + ], + [ + "CLBLL_WW4C2", + "CLBLM_WW4C2" + ], + [ + "CLBLL_WW2END2", + "CLBLM_WW2END2" + ], + [ + "CLBLL_NW4A0", + "CLBLM_NW4A0" + ], + [ + "CLBLL_WW4A1", + "CLBLM_WW4A1" + ], + [ + "CLBLL_SW4A2", + "CLBLM_SW4A2" + ], + [ + "CLBLL_SE2A2", + "CLBLM_SE2A2" + ], + [ + "CLBLL_SW4END2", + "CLBLM_SW4END2" + ], + [ + "CLBLL_LH10", + "CLBLM_LH10" + ], + [ + "CLBLL_NW4END3", + "CLBLM_NW4END3" + ], + [ + "CLBLL_EE4B2", + "CLBLM_EE4B2" + ], + [ + "CLBLL_WW2A3", + "CLBLM_WW2A3" + ], + [ + "CLBLL_WW4END2", + "CLBLM_WW4END2" + ], + [ + "CLBLL_EE4B0", + "CLBLM_EE4B0" + ], + [ + "CLBLL_SE4BEG0", + "CLBLM_SE4BEG0" + ], + [ + "CLBLL_WW2END0", + "CLBLM_WW2END0" + ], + [ + "CLBLL_NE4BEG0", + "CLBLM_NE4BEG0" + ], + [ + "CLBLL_WW4A0", + "CLBLM_WW4A0" + ], + [ + "CLBLL_LH3", + "CLBLM_LH3" + ], + [ + "CLBLL_WW4END0", + "CLBLM_WW4END0" + ], + [ + "CLBLL_EE4B3", + "CLBLM_EE4B3" + ], + [ + "CLBLL_NE2A3", + "CLBLM_NE2A3" + ], + [ + "CLBLL_WW4END3", + "CLBLM_WW4END3" + ], + [ + "CLBLL_EE2A2", + "CLBLM_EE2A2" + ], + [ + "CLBLL_LH11", + "CLBLM_LH11" + ], + [ + "CLBLL_WW4B0", + "CLBLM_WW4B0" + ], + [ + "CLBLL_SE2A3", + "CLBLM_SE2A3" + ], + [ + "CLBLL_NE2A2", + "CLBLM_NE2A2" + ], + [ + "CLBLL_NE4BEG1", + "CLBLM_NE4BEG1" + ], + [ + "CLBLL_NE4C1", + "CLBLM_NE4C1" + ], + [ + "CLBLL_EE4C0", + "CLBLM_EE4C0" + ], + [ + "CLBLL_EE4BEG2", + "CLBLM_EE4BEG2" + ], + [ + "CLBLL_NW4END2", + "CLBLM_NW4END2" + ], + [ + "CLBLL_ER1BEG1", + "CLBLM_ER1BEG1" + ], + [ + "CLBLL_WW2A2", + "CLBLM_WW2A2" + ], + [ + "CLBLL_SW2A3", + "CLBLM_SW2A3" + ], + [ + "CLBLL_LH6", + "CLBLM_LH6" + ], + [ + "CLBLL_NW4A1", + "CLBLM_NW4A1" + ], + [ + "CLBLL_NE2A1", + "CLBLM_NE2A1" + ], + [ + "CLBLL_EE4BEG1", + "CLBLM_EE4BEG1" + ], + [ + "CLBLL_SW4A1", + "CLBLM_SW4A1" + ], + [ + "CLBLL_SE2A1", + "CLBLM_SE2A1" + ], + [ + "CLBLL_SE4C2", + "CLBLM_SE4C2" + ], + [ + "CLBLL_LH1", + "CLBLM_LH1" + ], + [ + "CLBLL_WW4A2", + "CLBLM_WW4A2" + ], + [ + "CLBLL_SW4END0", + "CLBLM_SW4END0" + ], + [ + "CLBLL_ER1BEG2", + "CLBLM_ER1BEG2" + ], + [ + "CLBLL_WW4C1", + "CLBLM_WW4C1" + ], + [ + "CLBLL_NE4BEG3", + "CLBLM_NE4BEG3" + ], + [ + "CLBLL_SE4BEG3", + "CLBLM_SE4BEG3" + ], + [ + "CLBLL_EE2A0", + "CLBLM_EE2A0" + ], + [ + "CLBLL_WR1END3", + "CLBLM_WR1END3" + ] + ], + "tile_types": [ + "CLBLL_L", + "CLBLM_R" + ] + }, + { + "grid_deltas": [ + 5, + 8 + ], + "wire_pairs": [ + [ + "PCIE_WR1END0_2", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_SW4A3_2", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_NW4END0_2", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_BYP0_L_2", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_WW4A0_2", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_IMUX34_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_IMUX30_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_IMUX45_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_EE2BEG0_2", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_NE4BEG1_2", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_FAN5_L_2", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_BYP2_L_2", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_NE4C0_2", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_SW4END0_2", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_WW4END2_2", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_WW4C2_2", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_LH7_2", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_ER1BEG3_2", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_LH9_2", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_WW4C3_2", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_NE4BEG0_2", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_IMUX42_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_IMUX18_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_EE2A3_2", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_IMUX21_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_BYP6_L_2", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_NE2A1_2", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_IMUX0_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_WL1END3_2", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_EE4A0_2", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_IMUX47_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_BYP7_L_2", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_SW2A1_2", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_ER1BEG0_2", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_NW2A1_2", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_NE2A0_2", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_WW2A0_2", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_WL1END1_2", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_WW4A1_2", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_EE4B2_2", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_EE2BEG3_2", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_NE4BEG2_2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_WW2A1_2", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_IMUX36_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_CTRL0_L_2", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_WW4B3_2", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_SW2A0_2", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_LH11_2", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_SW2A2_2", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_IMUX10_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_BYP3_L_2", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_EE2BEG1_2", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_WR1END3_2", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_WR1END1_2", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_IMUX26_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_EE4BEG1_2", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_IMUX12_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_FAN2_L_2", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_SE4BEG1_2", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_WW2END2_2", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_EE4BEG3_2", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_IMUX16_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_LH3_2", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_WW2A2_2", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_NW4END3_2", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_LH8_2", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_ER1BEG2_2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_NW4END2_2", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_IMUX2_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_IMUX40_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_IMUX13_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_NW2A2_2", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_LH6_2", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_EL1BEG3_2", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_LH2_2", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_LH4_2", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_EE4A1_2", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_IMUX28_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_FAN7_L_2", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_BYP1_L_2", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_SW4END2_2", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_IMUX15_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_EE4A3_2", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_EL1BEG1_2", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_IMUX44_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_WR1END2_2", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_SE4C2_2", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_LH10_2", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_SE4BEG0_2", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_LH1_2", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_SW4END1_2", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_IMUX31_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_FAN0_L_2", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_FAN4_L_2", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_WW4C1_2", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_NE2A2_2", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_LH5_2", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_SW4A2_2", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_NE4C1_2", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_CLK0_L_2", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_EE4B0_2", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX1_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_IMUX9_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_IMUX39_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_IMUX11_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_FAN1_L_2", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_IMUX4_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_SE2A2_2", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_EE4B3_2", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_IMUX23_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_IMUX27_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_SE4BEG3_2", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_IMUX43_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_IMUX22_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_ER1BEG1_2", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_WW4A3_2", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_LH12_2", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_WW4B0_2", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_IMUX6_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_WW4A2_2", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_WW2END1_2", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_FAN6_L_2", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_WW4END1_2", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_SE4C0_2", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_IMUX41_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_IMUX46_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_IMUX19_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_EE4A2_2", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_EE2A2_2", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_WW2END0_2", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_FAN3_L_2", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_EE4C3_2", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_CLK1_L_2", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_WL1END0_2", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_IMUX5_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_SW4END3_2", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_SE2A3_2", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_EE2A1_2", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_SE2A0_2", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_WW4END3_2", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_EL1BEG0_2", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_IMUX8_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_IMUX32_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_WW2A3_2", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_IMUX33_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_EE4C2_2", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_NW4END1_2", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_IMUX25_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_WW2END3_2", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_WW4END0_2", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_EE2A0_2", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_IMUX38_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_EE4BEG0_2", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX7_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_EE4BEG2_2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_NW2A3_2", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_WW4B2_2", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_IMUX24_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_CTRL1_L_2", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_WW4B1_2", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_BYP5_L_2", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_EL1BEG2_2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_NE4C2_2", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_EE2BEG2_2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_SW4A1_2", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_WL1END2_2", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_NW4A0_2", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_NE4BEG3_2", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_IMUX37_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_IMUX3_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_SE4C1_2", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_EE4C0_2", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX17_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_IMUX14_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_NW2A0_2", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_IMUX29_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_BYP4_L_2", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_EE4C1_2", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_SE4C3_2", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_NW4A2_2", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_NW4A3_2", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_IMUX35_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_IMUX20_L_2", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_SW4A0_2", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_NW4A1_2", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_WW4C0_2", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_SW2A3_2", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_NE4C3_2", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_2", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_SE2A1_2", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_SE4BEG2_2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_NE2A3_2", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_EE4B1_2", + "INT_INTERFACE_EE4B1" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + -1, + -8 + ], + "wire_pairs": [ + [ + "CMT_PMV_BYP2", + "CMT_TOP_BYP2_0" + ], + [ + "CMT_PMV_IMUX4", + "CMT_TOP_IMUX4_0" + ], + [ + "CMT_PMV_EE4B0", + "CMT_TOP_EE4B0_0" + ], + [ + "CMT_PMV_SW2A1", + "CMT_TOP_SW2A1_0" + ], + [ + "CMT_PMV_FAN2", + "CMT_TOP_FAN2_0" + ], + [ + "CMT_PMV_IMUX7", + "CMT_TOP_IMUX7_0" + ], + [ + "CMT_PMV_EE4B2", + "CMT_TOP_EE4B2_0" + ], + [ + "CMT_PMV_LOGIC_OUTS10", + "CMT_TOP_LOGIC_OUTS_L_B10_0" + ], + [ + "CMT_PMV_ER1BEG1", + "CMT_TOP_ER1BEG1_0" + ], + [ + "CMT_PMV_IMUX46", + "CMT_TOP_IMUX46_0" + ], + [ + "CMT_PMV_EE2BEG0", + "CMT_TOP_EE2BEG0_0" + ], + [ + "CMT_PMV_NW4A0", + "CMT_TOP_NW4A0_0" + ], + [ + "CMT_PMV_LOGIC_OUTS15", + "CMT_TOP_LOGIC_OUTS_L_B15_0" + ], + [ + "CMT_PMV_FAN5", + "CMT_TOP_FAN5_0" + ], + [ + "CMT_PMV_LOGIC_OUTS13", + "CMT_TOP_LOGIC_OUTS_L_B13_0" + ], + [ + "CMT_PMV_IMUX3", + "CMT_TOP_IMUX3_0" + ], + [ + "CMT_PMV_NW2A1", + "CMT_TOP_NW2A1_0" + ], + [ + "CMT_PMV_FAN1", + "CMT_TOP_FAN1_0" + ], + [ + "CMT_PMV_WW4B0", + "CMT_TOP_WW4B0_0" + ], + [ + "CMT_PMV_NE4C3", + "CMT_TOP_NE4C3_0" + ], + [ + "CMT_PMV_EE2BEG1", + "CMT_TOP_EE2BEG1_0" + ], + [ + "CMT_PMV_IMUX34", + "CMT_TOP_IMUX34_0" + ], + [ + "CMT_PMV_SW4A3", + "CMT_TOP_SW4A3_0" + ], + [ + "CMT_PMV_IMUX25", + "CMT_TOP_IMUX25_0" + ], + [ + "CMT_PMV_FAN3", + "CMT_TOP_FAN3_0" + ], + [ + "CMT_PMV_EL1BEG0", + "CMT_TOP_EL1BEG0_0" + ], + [ + "CMT_PMV_EE4C2", + "CMT_TOP_EE4C2_0" + ], + [ + "CMT_PMV_WW2A2", + "CMT_TOP_WW2A2_0" + ], + [ + "CMT_PMV_IMUX1", + "CMT_TOP_IMUX1_0" + ], + [ + "CMT_PMV_IMUX36", + "CMT_TOP_IMUX36_0" + ], + [ + "CMT_PMV_EE4BEG1", + "CMT_TOP_EE4BEG1_0" + ], + [ + "CMT_PMV_IMUX21", + "CMT_TOP_IMUX21_0" + ], + [ + "CMT_PMV_WW4A0", + "CMT_TOP_WW4A0_0" + ], + [ + "CMT_PMV_ER1BEG2", + "CMT_TOP_ER1BEG2_0" + ], + [ + "CMT_PMV_BYP1", + "CMT_TOP_BYP1_0" + ], + [ + "CMT_PMV_IMUX6", + "CMT_TOP_IMUX6_0" + ], + [ + "CMT_PMV_IMUX5", + "CMT_TOP_IMUX5_0" + ], + [ + "CMT_PMV_IMUX45", + "CMT_TOP_IMUX45_0" + ], + [ + "CMT_PMV_WW4END1", + "CMT_TOP_WW4END1_0" + ], + [ + "CMT_PMV_NW2A2", + "CMT_TOP_NW2A2_0" + ], + [ + "CMT_PMV_WW4C3", + "CMT_TOP_WW4C3_0" + ], + [ + "CMT_PMV_SW4A2", + "CMT_TOP_SW4A2_0" + ], + [ + "CMT_PMV_WW4B1", + "CMT_TOP_WW4B1_0" + ], + [ + "CMT_PMV_SE4C2", + "CMT_TOP_SE4C2_0" + ], + [ + "CMT_PMV_IMUX32", + "CMT_TOP_IMUX32_0" + ], + [ + "CMT_PMV_IMUX42", + "CMT_TOP_IMUX42_0" + ], + [ + "CMT_PMV_LOGIC_OUTS16", + "CMT_TOP_LOGIC_OUTS_L_B16_0" + ], + [ + "CMT_PMV_EE4A0", + "CMT_TOP_EE4A0_0" + ], + [ + "CMT_PMV_LH2", + "CMT_TOP_LH2_0" + ], + [ + "CMT_PMV_IMUX31", + "CMT_TOP_IMUX31_0" + ], + [ + "CMT_PMV_WL1END0", + "CMT_TOP_WL1END0_0" + ], + [ + "CMT_PMV_EE2A3", + "CMT_TOP_EE2A3_0" + ], + [ + "CMT_PMV_BYP4", + "CMT_TOP_BYP4_0" + ], + [ + "CMT_PMV_SW4END2", + "CMT_TOP_SW4END2_0" + ], + [ + "CMT_PMV_IMUX35", + "CMT_TOP_IMUX35_0" + ], + [ + "CMT_PMV_NW4A2", + "CMT_TOP_NW4A2_0" + ], + [ + "CMT_PMV_NE4C0", + "CMT_TOP_NE4C0_0" + ], + [ + "CMT_PMV_LOGIC_OUTS2", + "CMT_TOP_LOGIC_OUTS_L_B2_0" + ], + [ + "CMT_PMV_SE4C1", + "CMT_TOP_SE4C1_0" + ], + [ + "CMT_PMV_IMUX19", + "CMT_TOP_IMUX19_0" + ], + [ + "CMT_PMV_NW4END0", + "CMT_TOP_NW4END0_0" + ], + [ + "CMT_PMV_NE4BEG1", + "CMT_TOP_NE4BEG1_0" + ], + [ + "CMT_PMV_IMUX0", + "CMT_TOP_IMUX0_0" + ], + [ + "CMT_PMV_IMUX8", + "CMT_TOP_IMUX8_0" + ], + [ + "CMT_PMV_IMUX40", + "CMT_TOP_IMUX40_0" + ], + [ + "CMT_PMV_LOGIC_OUTS5", + "CMT_TOP_LOGIC_OUTS_L_B5_0" + ], + [ + "CMT_PMV_WL1END1", + "CMT_TOP_WL1END1_0" + ], + [ + "CMT_PMV_EE4B3", + "CMT_TOP_EE4B3_0" + ], + [ + "CMT_PMV_LH1", + "CMT_TOP_LH1_0" + ], + [ + "CMT_PMV_CLK1", + "CMT_TOP_CLK1_0" + ], + [ + "CMT_PMV_LH4", + "CMT_TOP_LH4_0" + ], + [ + "CMT_PMV_SE4C0", + "CMT_TOP_SE4C0_0" + ], + [ + "CMT_PMV_IMUX37", + "CMT_TOP_IMUX37_0" + ], + [ + "CMT_PMV_IMUX47", + "CMT_TOP_IMUX47_0" + ], + [ + "L_TERM_INT_PHASER_TO_IO_OCLK", + "CMT_TOP_OCLK_0" + ], + [ + "CMT_PMV_NE2A3", + "CMT_TOP_NE2A3_0" + ], + [ + "CMT_PMV_WR1END1", + "CMT_TOP_WR1END1_0" + ], + [ + "CMT_PMV_SW4A0", + "CMT_TOP_SW4A0_0" + ], + [ + "CMT_PMV_LH7", + "CMT_TOP_LH7_0" + ], + [ + "CMT_PMV_WW4A3", + "CMT_TOP_WW4A3_0" + ], + [ + "CMT_PMV_IMUX44", + "CMT_TOP_IMUX44_0" + ], + [ + "CMT_PMV_NE2A0", + "CMT_TOP_NE2A0_0" + ], + [ + "CMT_PMV_EE4C3", + "CMT_TOP_EE4C3_0" + ], + [ + "CMT_PMV_IMUX30", + "CMT_TOP_IMUX30_0" + ], + [ + "CMT_PMV_EE4BEG3", + "CMT_TOP_EE4BEG3_0" + ], + [ + "CMT_PMV_IMUX43", + "CMT_TOP_IMUX43_0" + ], + [ + "CMT_PMV_CLK0", + "CMT_TOP_CLK0_0" + ], + [ + "CMT_PMV_WR1END0", + "CMT_TOP_WR1END0_0" + ], + [ + "CMT_PMV_SE2A0", + "CMT_TOP_SE2A0_0" + ], + [ + "CMT_PMV_IMUX17", + "CMT_TOP_IMUX17_0" + ], + [ + "CMT_PMV_LOGIC_OUTS18", + "CMT_TOP_LOGIC_OUTS_L_B18_0" + ], + [ + "CMT_PMV_SW2A0", + "CMT_TOP_SW2A0_0" + ], + [ + "CMT_PMV_SE2A3", + "CMT_TOP_SE2A3_0" + ], + [ + "CMT_PMV_WW4B2", + "CMT_TOP_WW4B2_0" + ], + [ + "CMT_PMV_EL1BEG2", + "CMT_TOP_EL1BEG2_0" + ], + [ + "CMT_PMV_SE4C3", + "CMT_TOP_SE4C3_0" + ], + [ + "CMT_PMV_LOGIC_OUTS17", + "CMT_TOP_LOGIC_OUTS_L_B17_0" + ], + [ + "L_TERM_INT_PHASER_TO_IO_ICLK", + "CMT_TOP_ICLK_0" + ], + [ + "CMT_PMV_NE4BEG2", + "CMT_TOP_NE4BEG2_0" + ], + [ + "CMT_PMV_EE2A1", + "CMT_TOP_EE2A1_0" + ], + [ + "CMT_PMV_LOGIC_OUTS22", + "CMT_TOP_LOGIC_OUTS_L_B22_0" + ], + [ + "CMT_PMV_IMUX11", + "CMT_TOP_IMUX11_0" + ], + [ + "CMT_PMV_IMUX39", + "CMT_TOP_IMUX39_0" + ], + [ + "CMT_PMV_EE4BEG2", + "CMT_TOP_EE4BEG2_0" + ], + [ + "CMT_PMV_WW4B3", + "CMT_TOP_WW4B3_0" + ], + [ + "CMT_PMV_EE2A0", + "CMT_TOP_EE2A0_0" + ], + [ + "CMT_PMV_LH6", + "CMT_TOP_LH6_0" + ], + [ + "CMT_PMV_FAN0", + "CMT_TOP_FAN0_0" + ], + [ + "CMT_PMV_SW4END1", + "CMT_TOP_SW4END1_0" + ], + [ + "CMT_PMV_SE4BEG1", + "CMT_TOP_SE4BEG1_0" + ], + [ + "CMT_PMV_BYP0", + "CMT_TOP_BYP0_0" + ], + [ + "CMT_PMV_NE4C1", + "CMT_TOP_NE4C1_0" + ], + [ + "CMT_PMV_SE4BEG3", + "CMT_TOP_SE4BEG3_0" + ], + [ + "CMT_PMV_EE4A3", + "CMT_TOP_EE4A3_0" + ], + [ + "CMT_PMV_EE4BEG0", + "CMT_TOP_EE4BEG0_0" + ], + [ + "CMT_PMV_IMUX41", + "CMT_TOP_IMUX41_0" + ], + [ + "CMT_PMV_WW4A2", + "CMT_TOP_WW4A2_0" + ], + [ + "CMT_PMV_IMUX10", + "CMT_TOP_IMUX10_0" + ], + [ + "CMT_PMV_IMUX38", + "CMT_TOP_IMUX38_0" + ], + [ + "CMT_PMV_BYP5", + "CMT_TOP_BYP5_0" + ], + [ + "CMT_PMV_NW2A3", + "CMT_TOP_NW2A3_0" + ], + [ + "CMT_PMV_LOGIC_OUTS19", + "CMT_TOP_LOGIC_OUTS_L_B19_0" + ], + [ + "CMT_PMV_EE4A2", + "CMT_TOP_EE4A2_0" + ], + [ + "CMT_PMV_ER1BEG3", + "CMT_TOP_ER1BEG3_0" + ], + [ + "CMT_PMV_IMUX16", + "CMT_TOP_IMUX16_0" + ], + [ + "CMT_PMV_LOGIC_OUTS23", + "CMT_TOP_LOGIC_OUTS_L_B23_0" + ], + [ + "CMT_PMV_NW2A0", + "CMT_TOP_NW2A0_0" + ], + [ + "CMT_PMV_SW2A3", + "CMT_TOP_SW2A3_0" + ], + [ + "CMT_PMV_CTRL1", + "CMT_TOP_CTRL1_0" + ], + [ + "CMT_PMV_SE2A1", + "CMT_TOP_SE2A1_0" + ], + [ + "CMT_PMV_IMUX20", + "CMT_TOP_IMUX20_0" + ], + [ + "CMT_PMV_EE4B1", + "CMT_TOP_EE4B1_0" + ], + [ + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "CMT_TOP_OCLKDIV_0" + ], + [ + "CMT_PMV_WW2END1", + "CMT_TOP_WW2END1_0" + ], + [ + "CMT_PMV_ER1BEG0", + "CMT_TOP_ER1BEG0_0" + ], + [ + "CMT_PMV_NE2A2", + "CMT_TOP_NE2A2_0" + ], + [ + "CMT_PMV_WW2END3", + "CMT_TOP_WW2END3_0" + ], + [ + "CMT_PMV_SW2A2", + "CMT_TOP_SW2A2_0" + ], + [ + "CMT_PMV_LOGIC_OUTS7", + "CMT_TOP_LOGIC_OUTS_L_B7_0" + ], + [ + "CMT_PMV_IMUX29", + "CMT_TOP_IMUX29_0" + ], + [ + "CMT_PMV_IMUX27", + "CMT_TOP_IMUX27_0" + ], + [ + "CMT_PMV_WL1END3", + "CMT_TOP_WL1END3_0" + ], + [ + "CMT_PMV_IMUX2", + "CMT_TOP_IMUX2_0" + ], + [ + "CMT_PMV_SW4END3", + "CMT_TOP_SW4END3_0" + ], + [ + "CMT_PMV_BYP6", + "CMT_TOP_BYP6_0" + ], + [ + "CMT_PMV_IMUX23", + "CMT_TOP_IMUX23_0" + ], + [ + "CMT_PMV_NW4END2", + "CMT_TOP_NW4END2_0" + ], + [ + "CMT_PMV_WW4END3", + "CMT_TOP_WW4END3_0" + ], + [ + "CMT_PMV_LH8", + "CMT_TOP_LH8_0" + ], + [ + "CMT_PMV_NE4BEG0", + "CMT_TOP_NE4BEG0_0" + ], + [ + "CMT_PMV_FAN4", + "CMT_TOP_FAN4_0" + ], + [ + "CMT_PMV_LOGIC_OUTS0", + "CMT_TOP_LOGIC_OUTS_L_B0_0" + ], + [ + "CMT_PMV_WR1END3", + "CMT_TOP_WR1END3_0" + ], + [ + "CMT_PMV_LH10", + "CMT_TOP_LH10_0" + ], + [ + "CMT_PMV_LH5", + "CMT_TOP_LH5_0" + ], + [ + "CMT_PMV_EE4A1", + "CMT_TOP_EE4A1_0" + ], + [ + "CMT_PMV_IMUX18", + "CMT_TOP_IMUX18_0" + ], + [ + "CMT_PMV_FAN6", + "CMT_TOP_FAN6_0" + ], + [ + "CMT_PMV_SE4BEG0", + "CMT_TOP_SE4BEG0_0" + ], + [ + "CMT_PMV_WW4END2", + "CMT_TOP_WW4END2_0" + ], + [ + "CMT_PMV_NE2A1", + "CMT_TOP_NE2A1_0" + ], + [ + "CMT_PMV_IMUX33", + "CMT_TOP_IMUX33_0" + ], + [ + "CMT_PMV_WW4C2", + "CMT_TOP_WW4C2_0" + ], + [ + "CMT_PMV_WW2A0", + "CMT_TOP_WW2A0_0" + ], + [ + "CMT_PMV_CTRL0", + "CMT_TOP_CTRL0_0" + ], + [ + "CMT_PMV_WW2END0", + "CMT_TOP_WW2END0_0" + ], + [ + "CMT_PMV_EE2A2", + "CMT_TOP_EE2A2_0" + ], + [ + "CMT_PMV_EL1BEG1", + "CMT_TOP_EL1BEG1_0" + ], + [ + "CMT_PMV_EE2BEG2", + "CMT_TOP_EE2BEG2_0" + ], + [ + "CMT_PMV_EE2BEG3", + "CMT_TOP_EE2BEG3_0" + ], + [ + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "CMT_TOP_ICLKDIV_0" + ], + [ + "CMT_PMV_BYP7", + "CMT_TOP_BYP7_0" + ], + [ + "CMT_PMV_WW4END0", + "CMT_TOP_WW4END0_0" + ], + [ + "CMT_PMV_EE4C1", + "CMT_TOP_EE4C1_0" + ], + [ + "CMT_PMV_IMUX12", + "CMT_TOP_IMUX12_0" + ], + [ + "CMT_PMV_WW2END2", + "CMT_TOP_WW2END2_0" + ], + [ + "CMT_PMV_NW4END1", + "CMT_TOP_NW4END1_0" + ], + [ + "CMT_PMV_IMUX26", + "CMT_TOP_IMUX26_0" + ], + [ + "CMT_PMV_SW4A1", + "CMT_TOP_SW4A1_0" + ], + [ + "CMT_PMV_IMUX14", + "CMT_TOP_IMUX14_0" + ], + [ + "CMT_PMV_LH9", + "CMT_TOP_LH9_0" + ], + [ + "CMT_PMV_NW4A1", + "CMT_TOP_NW4A1_0" + ], + [ + "CMT_PMV_IMUX22", + "CMT_TOP_IMUX22_0" + ], + [ + "CMT_PMV_LOGIC_OUTS8", + "CMT_TOP_LOGIC_OUTS_L_B8_0" + ], + [ + "CMT_PMV_IMUX24", + "CMT_TOP_IMUX24_0" + ], + [ + "CMT_PMV_SE2A2", + "CMT_TOP_SE2A2_0" + ], + [ + "CMT_PMV_NW4END3", + "CMT_TOP_NW4END3_0" + ], + [ + "CMT_PMV_NW4A3", + "CMT_TOP_NW4A3_0" + ], + [ + "CMT_PMV_NE4BEG3", + "CMT_TOP_NE4BEG3_0" + ], + [ + "CMT_PMV_SE4BEG2", + "CMT_TOP_SE4BEG2_0" + ], + [ + "CMT_PMV_LH11", + "CMT_TOP_LH11_0" + ], + [ + "CMT_PMV_LH12", + "CMT_TOP_LH12_0" + ], + [ + "CMT_PMV_WR1END2", + "CMT_TOP_WR1END2_0" + ], + [ + "CMT_PMV_FAN7", + "CMT_TOP_FAN7_0" + ], + [ + "CMT_PMV_BYP3", + "CMT_TOP_BYP3_0" + ], + [ + "CMT_PMV_IMUX15", + "CMT_TOP_IMUX15_0" + ], + [ + "CMT_PMV_IMUX13", + "CMT_TOP_IMUX13_0" + ], + [ + "CMT_PMV_LOGIC_OUTS20", + "CMT_TOP_LOGIC_OUTS_L_B20_0" + ], + [ + "CMT_PMV_NE4C2", + "CMT_TOP_NE4C2_0" + ], + [ + "CMT_PMV_WW4C1", + "CMT_TOP_WW4C1_0" + ], + [ + "CMT_PMV_LOGIC_OUTS21", + "CMT_TOP_LOGIC_OUTS_L_B21_0" + ], + [ + "CMT_PMV_EE4C0", + "CMT_TOP_EE4C0_0" + ], + [ + "CMT_PMV_WW2A1", + "CMT_TOP_WW2A1_0" + ], + [ + "CMT_PMV_SW4END0", + "CMT_TOP_SW4END0_0" + ], + [ + "CMT_PMV_IMUX28", + "CMT_TOP_IMUX28_0" + ], + [ + "CMT_PMV_WW4A1", + "CMT_TOP_WW4A1_0" + ], + [ + "CMT_PMV_WW4C0", + "CMT_TOP_WW4C0_0" + ], + [ + "CMT_PMV_WL1END2", + "CMT_TOP_WL1END2_0" + ], + [ + "CMT_PMV_EL1BEG3", + "CMT_TOP_EL1BEG3_0" + ], + [ + "CMT_PMV_LH3", + "CMT_TOP_LH3_0" + ], + [ + "CMT_PMV_IMUX9", + "CMT_TOP_IMUX9_0" + ], + [ + "CMT_PMV_WW2A3", + "CMT_TOP_WW2A3_0" + ] + ], + "tile_types": [ + "CMT_PMV_L", + "CMT_TOP_L_LOWER_B" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CLK_HROW_SW2A3_1", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_EE2BEG1_1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_BYP3_1", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_WL1END0_1", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_WW4C0_1", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_NE2A1_1", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_BUFG_IMUX21_1", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_WW4A2_1", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_NE4C0_1", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_FAN4_1", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_MONITOR_P_1", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_BUFG_IMUX39_1", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_NE4BEG1_1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_EE2BEG0_1", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_EE2A1_1", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_EL1BEG1_1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_BUFG_IMUX36_1", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_EE4A1_1", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_BUFG_IMUX45_1", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_SW4A2_1", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_NW4A2_1", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_EE2A2_1", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_EE2A0_1", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_FAN2_1", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_SE4C3_1", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_EE4BEG3_1", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_WW4C3_1", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_SW4END0_1", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_BUFG_IMUX42_1", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_CLK0_1", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_CTRL0_1", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_EE4BEG1_1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_WW2END2_1", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_BUFG_IMUX12_1", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_WR1END0_1", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_BUFG_IMUX19_1", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_WW2END0_1", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_EE2BEG3_1", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_BYP5_1", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B1_1", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CLK_HROW_NW2A0_1", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_LH4_1", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_NE2A3_1", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_FAN7_1", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_EE4BEG2_1", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_WW2END3_1", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_NE2A2_1", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_SW4END1_1", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_SW2A1_1", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_EE4B0_1", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_BUFG_IMUX1_1", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_NW4A3_1", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WW2A3_1", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_WR1END3_1", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_NE4BEG2_1", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_BUFG_IMUX14_1", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_EE2A3_1", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_CTRL1_1", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_WW4END2_1", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_BUFG_IMUX43_1", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_EL1BEG3_1", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_LH8_1", + "INT_INTERFACE_LH8" + ], + [ + "CLK_BUFG_IMUX8_1", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_BUFG_IMUX30_1", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_NW4END0_1", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_BYP1_1", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_WW4A1_1", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_LH2_1", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_NW4END2_1", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_EE2BEG2_1", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_NE4C2_1", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_SE2A1_1", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_EE4A0_1", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_BUFG_IMUX37_1", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_CLK1_1", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_LH10_1", + "INT_INTERFACE_LH10" + ], + [ + "CLK_BUFG_IMUX34_1", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_NW2A1_1", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_LH7_1", + "INT_INTERFACE_LH7" + ], + [ + "CLK_BUFG_IMUX35_1", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_LH12_1", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_FAN0_1", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_BUFG_IMUX2_1", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_NE4C3_1", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_LH5_1", + "INT_INTERFACE_LH5" + ], + [ + "CLK_BUFG_IMUX38_1", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_SW2A0_1", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE4C0_1", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_BUFG_IMUX9_1", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_BUFG_IMUX27_1", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_WW4B0_1", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_WL1END2_1", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_FAN5_1", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_NW4A0_1", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_SW4A3_1", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_NE4BEG3_1", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_WW2END1_1", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_SW4A1_1", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_LH3_1", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_WW2A0_1", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4B1_1", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_ER1BEG1_1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_BUFG_IMUX46_1", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_NE4BEG0_1", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_WR1END1_1", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B2_1", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CLK_HROW_WW4B1_1", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_SW4END2_1", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_BUFG_IMUX7_1", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_LH9_1", + "INT_INTERFACE_LH9" + ], + [ + "CLK_BUFG_IMUX4_1", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_LH11_1", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_SW4A0_1", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_NE4C1_1", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_SE2A3_1", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_BYP6_1", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_SW2A2_1", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_SE4BEG0_1", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_NW2A2_1", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_WW4C1_1", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B7_1", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CLK_HROW_ER1BEG3_1", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_NW4END1_1", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_BUFG_IMUX44_1", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_SE4BEG3_1", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_BYP0_1", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B5_1", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CLK_HROW_WW4C2_1", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_LH6_1", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_EL1BEG0_1", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_EE4B2_1", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_FAN3_1", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_BUFG_IMUX10_1", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_LH1_1", + "INT_INTERFACE_LH1" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B3_1", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CLK_BUFG_IMUX47_1", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_NW4END3_1", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_BUFG_IMUX11_1", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_WL1END3_1", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_WW4B3_1", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_BUFG_IMUX20_1", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_BYP7_1", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_BUFG_IMUX5_1", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_BUFG_IMUX28_1", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_BUFG_IMUX29_1", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_BUFG_IMUX22_1", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_SE4C0_1", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_EE4C3_1", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_SE2A2_1", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_BUFG_IMUX18_1", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_BUFG_IMUX6_1", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_BUFG_IMUX40_1", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_WW4A0_1", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_NW4A1_1", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_FAN6_1", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_BUFG_IMUX33_1", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_EE4C1_1", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_BUFG_IMUX16_1", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_EE4B3_1", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_EE4A3_1", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_BUFG_IMUX23_1", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_BUFG_IMUX25_1", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_NE2A0_1", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_WW4B2_1", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_BUFG_IMUX17_1", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_ER1BEG2_1", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_WW4END1_1", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_WW4END0_1", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_MONITOR_N_1", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_HROW_SW4END3_1", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_EL1BEG2_1", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_FAN1_1", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_BUFG_IMUX31_1", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_BYP2_1", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_WL1END1_1", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_EE4BEG0_1", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_BUFG_IMUX15_1", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B0_1", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CLK_HROW_SE4C2_1", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_BUFG_IMUX3_1", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_BUFG_IMUX13_1", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_WW4A3_1", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_BUFG_IMUX26_1", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_BUFG_IMUX32_1", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_WR1END2_1", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B4_1", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B6_1", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CLK_HROW_EE4A2_1", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_SE4BEG2_1", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_SE4C1_1", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_NW2A3_1", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_BUFG_IMUX41_1", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_WW4END3_1", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_BUFG_IMUX0_1", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_EE4C2_1", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_BYP4_1", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_ER1BEG0_1", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_BUFG_IMUX24_1", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_SE2A0_1", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_SE4BEG1_1", + "INT_INTERFACE_SE4BEG1" + ] + ], + "tile_types": [ + "CLK_BUFG_TOP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -5 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW4C0_6", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4END2_6", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW2A3_6", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4BEG0_6", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_6", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_6", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A3_6", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4A1_6", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4B0_6", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SW4A3_6", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_NE4BEG2_6", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE4B0_6", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE4C1_6", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A1_6", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END1_6", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_6", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_6", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_6", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C1_6", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW4A1_6", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_ER1BEG0_6", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_6", + "VBRK_LH1" + ], + [ + "CMT_TOP_EE4BEG2_6", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG2_6", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SE2A0_6", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WL1END2_6", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A1_6", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WR1END3_6", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NE2A2_6", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_LH4_6", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END1_6", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH8_6", + "VBRK_LH8" + ], + [ + "CMT_TOP_SE4BEG2_6", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4END2_6", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH6_6", + "VBRK_LH6" + ], + [ + "CMT_TOP_LH3_6", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C2_6", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NE2A3_6", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE4C3_6", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4A0_6", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C3_6", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_ER1BEG3_6", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_6", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WR1END2_6", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END0_6", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4C0_6", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SE4C0_6", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SE2A3_6", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW2END1_6", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH2_6", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW2END3_6", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE2A0_6", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NE4C0_6", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WW4C3_6", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END1_6", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4BEG3_6", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A1_6", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4B3_6", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4B1_6", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A1_6", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WL1END3_6", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH7_6", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW2A0_6", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A0_6", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NW2A1_6", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2BEG0_6", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_6", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE2BEG1_6", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4END3_6", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NW4END3_6", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4BEG1_6", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_6", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_SW4END2_6", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NW4A3_6", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4BEG0_6", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SW4A2_6", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4C1_6", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2A0_6", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4END0_6", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_ER1BEG2_6", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2A3_6", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW2A0_6", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_LH11_6", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE2BEG3_6", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH9_6", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4A3_6", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4A0_6", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE2A0_6", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NW2A2_6", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_6", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C3_6", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4A1_6", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WR1END0_6", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4C2_6", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE4C1_6", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG3_6", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW4B3_6", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END2_6", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A2_6", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4B2_6", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW4A0_6", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW2A1_6", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH5_6", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4B1_6", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_NE4BEG1_6", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH10_6", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_6", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4A2_6", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG1_6", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE2A1_6", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C2_6", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END0_6", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SE4BEG0_6", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_6", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE4A2_6", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4END0_6", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4BEG3_6", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A3_6", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_6", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_6", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A2_6", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NW2A3_6", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_6", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE4C2_6", + "VBRK_SE4C2" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -6 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX1_5", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX3_5", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX10_5", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_FAN0_5", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX13_5", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_FAN5_5", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX41_5", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX26_5", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX27_5", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX34_5", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX30_5", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX20_5", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN4_5", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX12_5", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX8_5", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_CLK0_5", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX14_5", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX22_5", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX24_5", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_BYP3_5", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX0_5", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_BYP4_5", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX18_5", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX43_5", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX37_5", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX4_5", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX9_5", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX29_5", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_BYP1_5", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_CTRL1_5", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_BYP7_5", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX39_5", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_CLK1_5", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX31_5", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX35_5", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_CTRL0_5", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_FAN1_5", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX28_5", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_FAN2_5", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX32_5", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX16_5", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX42_5", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX19_5", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX46_5", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX5_5", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX17_5", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_FAN7_5", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX11_5", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX6_5", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_BYP6_5", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_LOGIC_OUTS_B9_5", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_FAN6_5", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX7_5", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX15_5", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX47_5", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_BYP0_5", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX25_5", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX45_5", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX38_5", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX33_5", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX21_5", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX44_5", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX36_5", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_BYP2_5", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX2_5", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_BYP5_5", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX23_5", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX40_5", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_FAN3_5", + "VBRK_EXT_FAN3" + ] + ], + "tile_types": [ + "GTX_COMMON", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "CLK_HROW_IMUX18_0", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_IMUX39_0", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_IMUX5_0", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_FAN1_0", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_WW4A2_0", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_EE2BEG2_0", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_SE4BEG2_0", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_MONITOR_P_0", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_HROW_BYP5_0", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_IMUX19_0", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_NW2A2_0", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_FAN3_0", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_EE4A2_0", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_ER1BEG3_0", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_WR1END0_0", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_WW2A0_0", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4BEG2_0", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_CLK1_0", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_IMUX30_0", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_SW4A2_0", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_LH2_0", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_WW4A3_0", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_IMUX6_0", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_NE2A0_0", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_IMUX22_0", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_EE4BEG1_0", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_SW2A2_0", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_IMUX40_0", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_BYP4_0", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_EE4B3_0", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_IMUX14_0", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_EE2BEG0_0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_SE4C2_0", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_BYP7_0", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_SW4END0_0", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_EE4A0_0", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_SE4C3_0", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_IMUX16_0", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_BYP2_0", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_SE4BEG1_0", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_SW4A0_0", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_EE2BEG1_0", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_BYP6_0", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_IMUX1_0", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_IMUX37_0", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_FAN4_0", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_IMUX7_0", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_IMUX34_0", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_IMUX12_0", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_WL1END1_0", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_WW2END3_0", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_EL1BEG3_0", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_IMUX46_0", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_IMUX24_0", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_IMUX26_0", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_EE2BEG3_0", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_BYP3_0", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_WW4END3_0", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_NE4BEG3_0", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_EE2A0_0", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_IMUX8_0", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_IMUX35_0", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_IMUX28_0", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_IMUX32_0", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_SE4BEG0_0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_WW4C2_0", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_LH5_0", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_EL1BEG2_0", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_IMUX21_0", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_NW2A3_0", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_IMUX27_0", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_NE4C1_0", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_EE4C1_0", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_WW4END2_0", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_EE4BEG3_0", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_NE2A3_0", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_NW4END1_0", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_IMUX20_0", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_SW4END1_0", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_WW2A1_0", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_SW4END2_0", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_EE4C3_0", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_IMUX17_0", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_IMUX42_0", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_NW4END0_0", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_SW2A0_0", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_SW4A1_0", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_IMUX15_0", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_WW2A2_0", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_NE4C2_0", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_IMUX0_0", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_IMUX38_0", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_NW4A1_0", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_IMUX41_0", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_WW4END0_0", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_IMUX10_0", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_WW4C0_0", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_IMUX43_0", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_WW4A1_0", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_IMUX4_0", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_LH6_0", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_SW4END3_0", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_IMUX45_0", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_SE4C0_0", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_SE2A3_0", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_EE4A3_0", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_EE4B0_0", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_WW2A3_0", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_WW4A0_0", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_IMUX11_0", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_IMUX31_0", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_EE4A1_0", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_ER1BEG2_0", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_IMUX2_0", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_WW4C1_0", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_WL1END3_0", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_LH11_0", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_LH12_0", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_EE4BEG0_0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_MONITOR_N_0", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_HROW_IMUX47_0", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_IMUX13_0", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_NW4A0_0", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_WW4B1_0", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_WL1END2_0", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_EL1BEG0_0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_EE2A3_0", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_LH3_0", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_NE4BEG1_0", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_SE4C1_0", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_BYP1_0", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_WW2END0_0", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_NE4BEG2_0", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_NE4C3_0", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_SW2A1_0", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_WL1END0_0", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_NW4END3_0", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_CTRL0_0", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_CTRL1_0", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_WR1END2_0", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_WW4C3_0", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_EE2A2_0", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_LH9_0", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_EL1BEG1_0", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_IMUX33_0", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_IMUX44_0", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_BYP0_0", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_WR1END1_0", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_ER1BEG0_0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_FAN6_0", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_WW4END1_0", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_NE2A1_0", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_IMUX3_0", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_NW2A0_0", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_WW2END1_0", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_LH4_0", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_ER1BEG1_0", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_SE4BEG3_0", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_FAN7_0", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_FAN0_0", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_NE4C0_0", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_EE2A1_0", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_WW4B2_0", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_LH1_0", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_WW2END2_0", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_WW4B3_0", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_FAN2_0", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_SE2A2_0", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_LH10_0", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_IMUX9_0", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_NW2A1_0", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_IMUX36_0", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_NE2A2_0", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_EE4B2_0", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_FAN5_0", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_NE4BEG0_0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_IMUX23_0", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_SW2A3_0", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_SE2A0_0", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_SW4A3_0", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_NW4A2_0", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_EE4B1_0", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_LH7_0", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_IMUX29_0", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_NW4END2_0", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_NW4A3_0", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WR1END3_0", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_CLK0_0", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_WW4B0_0", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_LH8_0", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_SE2A1_0", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_EE4C2_0", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_IMUX25_0", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_EE4C0_0", + "INT_INTERFACE_EE4C0" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_GTX_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ], + [ + "HCLK_GTX_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_GTX_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_GTX_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_GTX_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_GTX_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_GTX_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_GTX_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_GTX_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_GTX_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ] + ], + "tile_types": [ + "HCLK_GTX", + "HCLK_INT_INTERFACE" + ] + }, + { + "grid_deltas": [ + 1, + 5 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4BEG2_5", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE2A2_5", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_IMUX6_5", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_EL1BEG1_5", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_WW4B1_5", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_BYP2_5", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_FAN4_5", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_SW4END2_5", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_EE2A3_5", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EE2BEG0_5", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX0_5", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_EE2BEG1_5", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX47_5", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX28_5", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_NW4END2_5", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_WW4B2_5", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_LH4_5", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_LH8_5", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_EE2BEG2_5", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_EE4B0_5", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_NW2A1_5", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_WL1END3_5", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_BYP6_5", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX44_5", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_NE4BEG1_5", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_NE2A0_5", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_EE4A2_5", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX2_5", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_SW2A1_5", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_SW4END0_5", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX26_5", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_WW4B3_5", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_FAN1_5", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_WR1END2_5", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_WR1END3_5", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX32_5", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_NE2A1_5", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_WW2END3_5", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW2END2_5", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_FAN6_5", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_FAN0_5", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_NE2A3_5", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_EE4BEG3_5", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_SE4BEG3_5", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_ER1BEG1_5", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_WR1END0_5", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EE4C0_5", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_IMUX41_5", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX19_5", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_IMUX24_5", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_WW4END1_5", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_WW4A3_5", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_SW4A3_5", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EL1BEG2_5", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NW4A3_5", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SE4C2_5", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_LH5_5", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_ER1BEG0_5", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_IMUX45_5", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_LH3_5", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX36_5", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_NE4BEG0_5", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX3_5", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_SW2A0_5", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_LH2_5", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EL1BEG0_5", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_WL1END2_5", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WW4END0_5", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_SE2A1_5", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NW4A0_5", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NW4END3_5", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_NW2A3_5", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_SW4A2_5", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_IMUX4_5", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX5_5", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_NW4A1_5", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_EE4B3_5", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_IMUX33_5", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_EE4C1_5", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_WW4B0_5", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_SW4END3_5", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX7_5", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_WW4C2_5", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX22_5", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW2A1_5", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_IMUX9_5", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_WL1END0_5", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_IMUX14_5", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_SE4C1_5", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX30_5", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_ER1BEG2_5", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX38_5", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX1_5", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX43_5", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_SW4A1_5", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_BYP4_5", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_EE4A0_5", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_NE4C0_5", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_BYP1_5", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW4END2_5", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_BYP0_5", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_NW4A2_5", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_EE4BEG0_5", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_IMUX18_5", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX8_5", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_LH1_5", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NE4BEG3_5", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX25_5", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_CLK1_5", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_SW4A0_5", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_NW2A2_5", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW4A2_5", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_WW4C1_5", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_CTRL1_5", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_EE4B2_5", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX37_5", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_FAN2_5", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_SE4C0_5", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_WW4C0_5", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX11_5", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_LH7_5", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_IMUX16_5", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_NE4C1_5", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_LH12_5", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_SE2A3_5", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SE4BEG0_5", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_IMUX39_5", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_WL1END1_5", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_SW2A2_5", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_SE4BEG1_5", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_IMUX17_5", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_EE4C2_5", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_WW2A0_5", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_WW2END0_5", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_NE2A2_5", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_IMUX34_5", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_EE4BEG1_5", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_IMUX10_5", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SW2A3_5", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_SE4C3_5", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_BYP7_5", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_EE4C3_5", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE4A3_5", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_WW2A3_5", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_NW4END0_5", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX35_5", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_IMUX31_5", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_BYP5_5", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_EE2A1_5", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX13_5", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_IMUX12_5", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX42_5", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_BYP3_5", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_NE4C2_5", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_WW4A1_5", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_WR1END1_5", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_FAN5_5", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SE2A2_5", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_SW4END1_5", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_FAN3_5", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_NE4C3_5", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_IMUX20_5", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_WW4END3_5", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_EE2A0_5", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_EE4A1_5", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX23_5", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_SE4BEG2_5", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE4B1_5", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_IMUX40_5", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_FAN7_5", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_LH6_5", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_WW2END1_5", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_NW4END1_5", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SE2A0_5", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_LH11_5", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_IMUX27_5", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX21_5", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_LH9_5", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EL1BEG3_5", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_NE4BEG2_5", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW4C3_5", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NW2A0_5", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_IMUX46_5", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_CTRL0_5", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_EE2BEG3_5", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_CLK0_5", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX29_5", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX15_5", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_WW2A2_5", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_LH10_5", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_ER1BEG3_5", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_WW4A0_5", + "VFRAME_WW4A0" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLK_PMV_IMUX25_0", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_PMV_IMUX14_0", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_PMV_IMUX6_0", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_PMV_IMUX46_0", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_PMV_IMUX34_0", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_FEED_WW4B1", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_PMV_IMUX7_0", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_PMV_IMUX28_0", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_PMV_IMUX11_0", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_FEED_WL1END2", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_FEED_EE4BEG2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_FEED_LH8", + "INT_INTERFACE_LH8" + ], + [ + "CLK_PMV_IMUX8_0", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_FEED_WW4C1", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_PMV_IMUX37_0", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_PMV_IMUX19_0", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_FEED_WR1END3", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_FEED_EE4B3", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_PMV_IMUX3_0", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_PMV_FAN0_0", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_FEED_NE2A2", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_PMV_IMUX10_0", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_FEED_WL1END0", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_FEED_NE2A1", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_FEED_WW4C2", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_PMV_IMUX45_0", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_FEED_NW2A2", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_FEED_WW2A0", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_FEED_WR1END1", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_PMV_IMUX18_0", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_FEED_SE4BEG2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_PMV_BYP1_0", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_PMV_IMUX39_0", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_FEED_NW2A1", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_FEED_EE4A2", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_PMV_FAN7_0", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_PMV_IMUX17_0", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_FEED_NW2A0", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_PMV_IMUX29_0", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_FEED_WW4B2", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_FEED_WL1END1", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_PMV_IMUX35_0", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_FEED_NE2A0", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_FEED_WW4C0", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_FEED_WW4END0", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_FEED_EE4C1", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_FEED_EE4C0", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_FEED_EE4BEG0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_FEED_LH11", + "INT_INTERFACE_LH11" + ], + [ + "CLK_PMV_IMUX27_0", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_PMV_IMUX22_0", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_PMV_BYP4_0", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_FEED_WW4END2", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_FEED_SE4BEG1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_FEED_NW4A3", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_PMV_IMUX1_0", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_FEED_EE2BEG3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_FEED_SE2A2", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_FEED_EE2BEG2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_FEED_NW4A0", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_PMV_FAN5_0", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_FEED_LH5", + "INT_INTERFACE_LH5" + ], + [ + "CLK_FEED_WW2A1", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_PMV_IMUX40_0", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_FEED_WW4C3", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_PMV_LOGIC_OUTS1_0", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CLK_FEED_SW4END1", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_FEED_EE2A2", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_FEED_WW4A2", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_PMV_BYP2_0", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_FEED_NW4END2", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_PMV_IMUX38_0", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_FEED_SW4END2", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_PMV_BYP7_0", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_PMV_BYP5_0", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_FEED_ER1BEG1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_FEED_EE4BEG3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_FEED_WW4A0", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_FEED_NE4C2", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_PMV_IMUX21_0", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_FEED_EE2A0", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_PMV_IMUX26_0", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_FEED_NE4C1", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_PMV_BYP6_0", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_FEED_SE4C2", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_FEED_SE2A1", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_PMV_IMUX43_0", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_FEED_SE4C0", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_FEED_LH1", + "INT_INTERFACE_LH1" + ], + [ + "CLK_FEED_NE4BEG3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_PMV_CTRL0_0", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_FEED_WW2END2", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_FEED_EE4B2", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_FEED_MONITOR_P", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_FEED_WW2END0", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_PMV_FAN1_0", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_FEED_EE4B1", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_FEED_NE2A3", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_PMV_IMUX0_0", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_PMV_IMUX9_0", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_FEED_MONITOR_N", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_PMV_BYP3_0", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_FEED_WW4B0", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_FEED_SW4A1", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_FEED_SE2A3", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_FEED_WW4END1", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_PMV_IMUX30_0", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_FEED_ER1BEG2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_FEED_WR1END2", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_FEED_WR1END0", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_FEED_EE2A3", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_FEED_NE4C0", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_FEED_SE4C3", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_FEED_LH9", + "INT_INTERFACE_LH9" + ], + [ + "CLK_FEED_WW4A1", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_FEED_LH3", + "INT_INTERFACE_LH3" + ], + [ + "CLK_FEED_EL1BEG3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_FEED_EE4A0", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_PMV_IMUX23_0", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_PMV_IMUX31_0", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_FEED_SW4A3", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_FEED_NW2A3", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_PMV_IMUX20_0", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_FEED_SW4END3", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_FEED_WL1END3", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_PMV_IMUX47_0", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_FEED_SE2A0", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_PMV_IMUX24_0", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_PMV_FAN3_0", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_PMV_LOGIC_OUTS0_0", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CLK_FEED_NW4END3", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_FEED_EE2A1", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_FEED_SW4END0", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_FEED_EL1BEG2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_FEED_LH2", + "INT_INTERFACE_LH2" + ], + [ + "CLK_FEED_EE2BEG1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_PMV_IMUX15_0", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_FEED_SW2A2", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_FEED_EE4B0", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_FEED_LH6", + "INT_INTERFACE_LH6" + ], + [ + "CLK_FEED_SW2A1", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_PMV_IMUX41_0", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_FEED_SW2A0", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_FEED_EE4A3", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_FEED_EE4A1", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_FEED_EE4BEG1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_FEED_ER1BEG0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_FEED_NE4BEG1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_PMV_CLK0_0", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_PMV_FAN2_0", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_PMV_FAN4_0", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_FEED_EL1BEG0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_PMV_IMUX13_0", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_FEED_WW2END1", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_FEED_NE4BEG2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_FEED_WW4A3", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_FEED_EE2BEG0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_PMV_CLK1_0", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_FEED_WW4END3", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_PMV_IMUX2_0", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_PMV_FAN6_0", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_FEED_NE4BEG0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_FEED_SW4A2", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_PMV_IMUX12_0", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_FEED_WW4B3", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_FEED_NE4C3", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_PMV_IMUX5_0", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_PMV_IMUX32_0", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_PMV_IMUX42_0", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_FEED_SE4BEG0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_FEED_LH12", + "INT_INTERFACE_LH12" + ], + [ + "CLK_FEED_ER1BEG3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_PMV_CTRL1_0", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_PMV_IMUX36_0", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_PMV_IMUX16_0", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_PMV_BYP0_0", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_FEED_NW4END0", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_PMV_LOGIC_OUTS2_0", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CLK_FEED_LH4", + "INT_INTERFACE_LH4" + ], + [ + "CLK_FEED_EE4C3", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_FEED_SW2A3", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_FEED_EL1BEG1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_FEED_SW4A0", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_FEED_LH10", + "INT_INTERFACE_LH10" + ], + [ + "CLK_FEED_NW4END1", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_PMV_IMUX33_0", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_FEED_WW2A3", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_PMV_IMUX44_0", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_FEED_NW4A2", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_FEED_WW2END3", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_FEED_LH7", + "INT_INTERFACE_LH7" + ], + [ + "CLK_FEED_EE4C2", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_FEED_SE4C1", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_FEED_NW4A1", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_FEED_WW2A2", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_PMV_IMUX4_0", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_FEED_SE4BEG3", + "INT_INTERFACE_SE4BEG3" + ] + ], + "tile_types": [ + "CLK_PMVIOB", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "HCLK_NW6A0", + "NW6B0" + ], + [ + "HCLK_NW6END_S0_0", + "NW6END0" + ], + [ + "HCLK_SS2END2", + "SS2A2" + ], + [ + "HCLK_LEAF_CLK_B_TOPL4", + "GCLK_L_B10" + ], + [ + "HCLK_SW6B1", + "SW6A1" + ], + [ + "HCLK_NE6D2", + "NE6E2" + ], + [ + "HCLK_NE6B0", + "NE6C0" + ], + [ + "HCLK_LV4", + "LV_L5" + ], + [ + "HCLK_LV11", + "LV_L12" + ], + [ + "HCLK_SW6B0", + "SW6A0" + ], + [ + "HCLK_NW2END_S0_0", + "NW2END0" + ], + [ + "HCLK_NL1BEG1", + "NL1END1" + ], + [ + "HCLK_NW6D2", + "NW6E2" + ], + [ + "HCLK_SE6B0", + "SE6A0" + ], + [ + "HCLK_LEAF_CLK_B_TOPL0", + "GCLK_L_B6" + ], + [ + "HCLK_SE6D2", + "SE6C2" + ], + [ + "HCLK_SS6C1", + "SS6B1" + ], + [ + "HCLK_NE6C3", + "NE6D3" + ], + [ + "HCLK_SW6D0", + "SW6C0" + ], + [ + "HCLK_SS6C3", + "SS6B3" + ], + [ + "HCLK_NN6D3", + "NN6E3" + ], + [ + "HCLK_WW4END_S0_0", + "WW4END0" + ], + [ + "HCLK_NN6END_S1_0", + "NN6END0" + ], + [ + "HCLK_SS6B1", + "SS6A1" + ], + [ + "HCLK_NE6A3", + "NE6B3" + ], + [ + "HCLK_WR1END_S1_0", + "WR1END0" + ], + [ + "HCLK_NN6C0", + "NN6D0" + ], + [ + "HCLK_SS2END1", + "SS2A1" + ], + [ + "HCLK_SR1BEG3", + "SR1BEG3" + ], + [ + "HCLK_SR1END_N3_3", + "SR1END_N3_3" + ], + [ + "HCLK_LV9", + "LV_L10" + ], + [ + "HCLK_LVB6", + "LVB_L6" + ], + [ + "HCLK_SW6E2", + "SW6D2" + ], + [ + "HCLK_SE6E1", + "SE6D1" + ], + [ + "HCLK_NW6B1", + "NW6C1" + ], + [ + "HCLK_LV1", + "LV_L2" + ], + [ + "HCLK_SL1END2", + "SL1BEG2" + ], + [ + "HCLK_BYP_BOUNCE3", + "BYP_BOUNCE_N3_3" + ], + [ + "HCLK_FAN_BOUNCE_S3_6", + "FAN_BOUNCE6" + ], + [ + "HCLK_NL1BEG2", + "NL1END2" + ], + [ + "HCLK_NW6A3", + "NW6B3" + ], + [ + "HCLK_LVB3", + "LVB_L3" + ], + [ + "HCLK_SW6C1", + "SW6B1" + ], + [ + "HCLK_SS6C0", + "SS6B0" + ], + [ + "HCLK_SW6E1", + "SW6D1" + ], + [ + "HCLK_LVB7", + "LVB_L7" + ], + [ + "HCLK_SS6D2", + "SS6C2" + ], + [ + "HCLK_FAN_BOUNCE_S3_2", + "FAN_BOUNCE2" + ], + [ + "HCLK_NE6B3", + "NE6C3" + ], + [ + "HCLK_SS6A1", + "SS6BEG1" + ], + [ + "HCLK_EL1BEG3", + "EL1BEG_N3" + ], + [ + "HCLK_LVB10", + "LVB_L10" + ], + [ + "HCLK_SW6C0", + "SW6B0" + ], + [ + "HCLK_SE6B3", + "SE6A3" + ], + [ + "HCLK_NW2A1", + "NW2A1" + ], + [ + "HCLK_LVB11", + "LVB_L11" + ], + [ + "HCLK_SS6C2", + "SS6B2" + ], + [ + "HCLK_NW2A3", + "NW2A3" + ], + [ + "HCLK_NN6BEG0", + "NN6A0" + ], + [ + "HCLK_NE6D1", + "NE6E1" + ], + [ + "HCLK_SS6END1", + "SS6E1" + ], + [ + "HCLK_SS2A0", + "SS2BEG0" + ], + [ + "HCLK_SR1END1", + "SR1BEG1" + ], + [ + "HCLK_WL1END3", + "WL1END_N1_3" + ], + [ + "HCLK_EL1END_S3_0", + "EL1END0" + ], + [ + "HCLK_NE6A0", + "NE6B0" + ], + [ + "HCLK_NN2A3", + "NN2END3" + ], + [ + "HCLK_SS6END3", + "SS6E3" + ], + [ + "HCLK_SW6D3", + "SW6C3" + ], + [ + "HCLK_SE6E3", + "SE6D3" + ], + [ + "HCLK_NN6D1", + "NN6E1" + ], + [ + "HCLK_NN2A2", + "NN2END2" + ], + [ + "HCLK_NN6E0", + "NN6END0" + ], + [ + "HCLK_WW2END3", + "WW2END_N0_3" + ], + [ + "HCLK_SW6E3", + "SW6D3" + ], + [ + "HCLK_LV17", + "LV_L18" + ], + [ + "HCLK_LVB2", + "LVB_L2" + ], + [ + "HCLK_SW6D1", + "SW6C1" + ], + [ + "HCLK_NE2BEG2", + "NE2A2" + ], + [ + "HCLK_NE6A2", + "NE6B2" + ], + [ + "HCLK_SE6B1", + "SE6A1" + ], + [ + "HCLK_LV2", + "LV_L3" + ], + [ + "HCLK_NW6C3", + "NW6D3" + ], + [ + "HCLK_SS2BEG3", + "SS2BEG3" + ], + [ + "HCLK_NE6C2", + "NE6D2" + ], + [ + "HCLK_NW6D1", + "NW6E1" + ], + [ + "HCLK_NN6BEG1", + "NN6A1" + ], + [ + "HCLK_WL1BEG3", + "WL1BEG_N3" + ], + [ + "HCLK_SW2END2", + "SW2BEG2" + ], + [ + "HCLK_NN6C2", + "NN6D2" + ], + [ + "HCLK_SS6D3", + "SS6C3" + ], + [ + "HCLK_NN6B3", + "NN6C3" + ], + [ + "HCLK_NR1BEG3", + "NR1END3" + ], + [ + "HCLK_NW6B2", + "NW6C2" + ], + [ + "HCLK_LV0", + "LV_L1" + ], + [ + "HCLK_SW2END_N0_3", + "SW2END_N0_3" + ], + [ + "HCLK_NN6BEG3", + "NN6A3" + ], + [ + "HCLK_SS6A0", + "SS6BEG0" + ], + [ + "HCLK_NW6A1", + "NW6B1" + ], + [ + "HCLK_NN6A1", + "NN6B1" + ], + [ + "HCLK_SW6END3", + "SW6END_N0_3" + ], + [ + "HCLK_WR1BEG_S0", + "WR1BEG0" + ], + [ + "HCLK_NN6BEG2", + "NN6A2" + ], + [ + "HCLK_NN6B1", + "NN6C1" + ], + [ + "HCLK_LVB1", + "LVB_L1" + ], + [ + "HCLK_NN2BEG1", + "NN2A1" + ], + [ + "HCLK_NE6C0", + "NE6D0" + ], + [ + "HCLK_NN2A1", + "NN2END1" + ], + [ + "HCLK_SS6E1", + "SS6D1" + ], + [ + "HCLK_LVB9", + "LVB_L9" + ], + [ + "HCLK_NN2END_S2_0", + "NN2END0" + ], + [ + "HCLK_LV14", + "LV_L15" + ], + [ + "HCLK_SW2END0", + "SW2BEG0" + ], + [ + "HCLK_ER1BEG_S0", + "ER1BEG0" + ], + [ + "HCLK_SS2END0", + "SS2A0" + ], + [ + "HCLK_SW2END1", + "SW2BEG1" + ], + [ + "HCLK_NN6C3", + "NN6D3" + ], + [ + "HCLK_NE6D0", + "NE6E0" + ], + [ + "HCLK_BYP_BOUNCE7", + "BYP_BOUNCE_N3_7" + ], + [ + "HCLK_NN6B0", + "NN6C0" + ], + [ + "HCLK_SW6C2", + "SW6B2" + ], + [ + "HCLK_SS6E2", + "SS6D2" + ], + [ + "HCLK_LVB8", + "LVB_L8" + ], + [ + "HCLK_SE6D0", + "SE6C0" + ], + [ + "HCLK_NW2A0", + "NW2A0" + ], + [ + "HCLK_NW6C0", + "NW6D0" + ], + [ + "HCLK_SE6C1", + "SE6B1" + ], + [ + "HCLK_SS2A1", + "SS2BEG1" + ], + [ + "HCLK_SE2A1", + "SE2BEG1" + ], + [ + "HCLK_NW6B0", + "NW6C0" + ], + [ + "HCLK_NE6D3", + "NE6E3" + ], + [ + "HCLK_LV15", + "LV_L16" + ], + [ + "HCLK_LEAF_CLK_B_TOPL1", + "GCLK_L_B7" + ], + [ + "HCLK_SE6D3", + "SE6C3" + ], + [ + "HCLK_NN6E2", + "NN6END2" + ], + [ + "HCLK_NN2BEG2", + "NN2A2" + ], + [ + "HCLK_SS6B3", + "SS6A3" + ], + [ + "HCLK_NR1BEG2", + "NR1END2" + ], + [ + "HCLK_NN6A3", + "NN6B3" + ], + [ + "HCLK_BYP_BOUNCE6", + "BYP_BOUNCE_N3_6" + ], + [ + "HCLK_LV8", + "LV_L9" + ], + [ + "HCLK_SS6A2", + "SS6BEG2" + ], + [ + "HCLK_SW6D2", + "SW6C2" + ], + [ + "HCLK_SW6C3", + "SW6B3" + ], + [ + "HCLK_SS2END_N0_3", + "SS2END_N0_3" + ], + [ + "HCLK_SS6END0", + "SS6E0" + ], + [ + "HCLK_SW6B3", + "SW6A3" + ], + [ + "HCLK_LEAF_CLK_B_TOPL5", + "GCLK_L_B11" + ], + [ + "HCLK_SE6C2", + "SE6B2" + ], + [ + "HCLK_NE2END_S3_0", + "NE2END0" + ], + [ + "HCLK_NE2BEG0", + "NE2A0" + ], + [ + "HCLK_SS6B0", + "SS6A0" + ], + [ + "HCLK_NN6A2", + "NN6B2" + ], + [ + "HCLK_NW6D0", + "NW6E0" + ], + [ + "HCLK_SE6E2", + "SE6D2" + ], + [ + "HCLK_NN2A0", + "NN2END0" + ], + [ + "HCLK_LV13", + "LV_L14" + ], + [ + "HCLK_NN2BEG3", + "NN2A3" + ], + [ + "HCLK_SR1END2", + "SR1BEG2" + ], + [ + "HCLK_NN2BEG0", + "NN2A0" + ], + [ + "HCLK_NW6B3", + "NW6C3" + ], + [ + "HCLK_NW6C1", + "NW6D1" + ], + [ + "HCLK_SS6D1", + "SS6C1" + ], + [ + "HCLK_LEAF_CLK_B_TOPL3", + "GCLK_L_B9" + ], + [ + "HCLK_FAN_BOUNCE_S3_4", + "FAN_BOUNCE4" + ], + [ + "HCLK_NN6C1", + "NN6D1" + ], + [ + "HCLK_LV5", + "LV_L6" + ], + [ + "HCLK_BYP_BOUNCE2", + "BYP_BOUNCE_N3_2" + ], + [ + "HCLK_SE6B2", + "SE6A2" + ], + [ + "HCLK_NE6A1", + "NE6B1" + ], + [ + "HCLK_LVB4", + "LVB_L4" + ], + [ + "HCLK_SW6B2", + "SW6A2" + ], + [ + "HCLK_SS6B2", + "SS6A2" + ], + [ + "HCLK_SE6C3", + "SE6B3" + ], + [ + "HCLK_NW6A2", + "NW6B2" + ], + [ + "HCLK_FAN_BOUNCE_S3_0", + "FAN_BOUNCE0" + ], + [ + "HCLK_NN6E3", + "NN6END3" + ], + [ + "HCLK_SW6E0", + "SW6D0" + ], + [ + "HCLK_SS6END_N0_3", + "SS6END_N0_3" + ], + [ + "HCLK_NR1BEG1", + "NR1END1" + ], + [ + "HCLK_NR1BEG0", + "NR1END0" + ], + [ + "HCLK_LV6", + "LV_L7" + ], + [ + "HCLK_SL1END3", + "SL1BEG3" + ], + [ + "HCLK_NN6B2", + "NN6C2" + ], + [ + "HCLK_SS6E0", + "SS6D0" + ], + [ + "HCLK_LV12", + "LV_L13" + ], + [ + "HCLK_SS6D0", + "SS6C0" + ], + [ + "HCLK_SS2A3", + "SS2A3" + ], + [ + "HCLK_LV16", + "LV_L17" + ], + [ + "HCLK_SS6A3", + "SS6BEG3" + ], + [ + "HCLK_SS6END2", + "SS6E2" + ], + [ + "HCLK_SE6E0", + "SE6D0" + ], + [ + "HCLK_NW2A2", + "NW2A2" + ], + [ + "HCLK_NE6B1", + "NE6C1" + ], + [ + "HCLK_LVB5", + "LVB_L5" + ], + [ + "HCLK_NW6C2", + "NW6D2" + ], + [ + "HCLK_NE6B2", + "NE6C2" + ], + [ + "HCLK_NL1END_S3_0", + "NL1END0" + ], + [ + "HCLK_SS6E3", + "SS6D3" + ], + [ + "HCLK_NE2BEG3", + "NE2A3" + ], + [ + "HCLK_NN6E1", + "NN6END1" + ], + [ + "HCLK_SL1END0", + "SL1BEG0" + ], + [ + "HCLK_SE6D1", + "SE6C1" + ], + [ + "HCLK_SE2A3", + "SE2BEG3" + ], + [ + "HCLK_ER1END3", + "ER1END_N3_3" + ], + [ + "HCLK_SL1END1", + "SL1BEG1" + ], + [ + "HCLK_NL1BEG0", + "NL1END0" + ], + [ + "HCLK_LV10", + "LV_L11" + ], + [ + "HCLK_SS2A2", + "SS2BEG2" + ], + [ + "HCLK_NN6D0", + "NN6E0" + ], + [ + "HCLK_NE2BEG1", + "NE2A1" + ], + [ + "HCLK_NN6A0", + "NN6B0" + ], + [ + "HCLK_SW2A3", + "SW2BEG3" + ], + [ + "HCLK_SE2A2", + "SE2BEG2" + ], + [ + "HCLK_NW6D3", + "NW6E3" + ], + [ + "HCLK_NN6D2", + "NN6E2" + ], + [ + "HCLK_LV3", + "LV_L4" + ], + [ + "HCLK_SE2A0", + "SE2BEG0" + ], + [ + "HCLK_SE6C0", + "SE6B0" + ], + [ + "HCLK_LVB12", + "LVB_L12" + ], + [ + "HCLK_LV7", + "LV_L8" + ], + [ + "HCLK_NE6C1", + "NE6D1" + ], + [ + "HCLK_LEAF_CLK_B_TOPL2", + "GCLK_L_B8" + ] + ], + "tile_types": [ + "HCLK_L", + "INT_L" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "CLK_HROW_EL1BEG3_7", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_WW2A1_7", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_SE4C3_7", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_WW4END3_7", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_EE4C0_7", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_SW4A2_7", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_NE2A3_7", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_CLK1_7", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_BYP6_7", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_WW4B0_7", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_IMUX38_7", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_ER1BEG0_7", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_IMUX4_7", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_WL1END2_7", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_WW2A0_7", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_IMUX1_7", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_WW4A2_7", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_SE2A1_7", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_NW4END1_7", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_EE4C2_7", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_CTRL1_7", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_SE4BEG0_7", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_WW2END0_7", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_IMUX13_7", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_SE2A3_7", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_IMUX22_7", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_NE4BEG1_7", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_SW4A1_7", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_SW2A0_7", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE2A0_7", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_IMUX24_7", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_WW4END2_7", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_IMUX36_7", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_WW4C3_7", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_EL1BEG1_7", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_WW4B1_7", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_EE4B3_7", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_IMUX44_7", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_CTRL0_7", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_LH10_7", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_IMUX7_7", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_EE2BEG1_7", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_NW4A1_7", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_IMUX2_7", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_ER1BEG3_7", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_FAN3_7", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_WW2END2_7", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_WW4C2_7", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_EE2A3_7", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_IMUX5_7", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_IMUX15_7", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_IMUX34_7", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_EL1BEG0_7", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_EE2BEG3_7", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_SW4A0_7", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_IMUX18_7", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_NW4A3_7", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_IMUX6_7", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_WR1END2_7", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_IMUX40_7", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_SW2A1_7", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_EE2A2_7", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_WW4C0_7", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_EE4A3_7", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_IMUX30_7", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_IMUX47_7", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_SW4END2_7", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_IMUX42_7", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_IMUX29_7", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_BYP7_7", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_FAN7_7", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_IMUX28_7", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_NW2A2_7", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_WW2END1_7", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_BYP2_7", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_IMUX9_7", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_LH9_7", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_IMUX3_7", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_IMUX21_7", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_NW4A0_7", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_IMUX23_7", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_WW4C1_7", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_IMUX32_7", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_FAN2_7", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_SE4BEG3_7", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_SE4BEG1_7", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_LH4_7", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_NE4BEG0_7", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_NE4BEG2_7", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_NE2A2_7", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_WW2END3_7", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_IMUX35_7", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_FAN0_7", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_WW4A1_7", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_IMUX8_7", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_NE2A0_7", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_LH3_7", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_IMUX31_7", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_NW4END2_7", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_NW4END3_7", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_EE4BEG3_7", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_SW2A2_7", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_IMUX20_7", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_SW4END1_7", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_ER1BEG1_7", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_WW4END1_7", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_FAN6_7", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_SE4C0_7", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_LH6_7", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_EE4B0_7", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_NW4END0_7", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_SE2A2_7", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_EE4C1_7", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_IMUX43_7", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_BYP5_7", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_IMUX37_7", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_FAN4_7", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_NE4C0_7", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_CLK0_7", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_WW4B2_7", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_SW4END3_7", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_WW4A0_7", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_WW4END0_7", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_IMUX25_7", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_NE4C2_7", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_IMUX33_7", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_WR1END0_7", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_SW2A3_7", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_SE2A0_7", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_SE4C1_7", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_IMUX0_7", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_FAN5_7", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_SE4C2_7", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_IMUX11_7", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_SW4A3_7", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_EE4A0_7", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_LH1_7", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_BYP3_7", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_IMUX19_7", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_EE4C3_7", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_LH7_7", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_IMUX39_7", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_NE4C3_7", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_EE2BEG0_7", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_WL1END1_7", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_EE2A1_7", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_WL1END3_7", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_SE4BEG2_7", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_IMUX16_7", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_WR1END3_7", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_IMUX45_7", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_NW4A2_7", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_EE4BEG1_7", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_EE4B2_7", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_EE4BEG2_7", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_EE4A2_7", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_NW2A3_7", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_WW4B3_7", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_IMUX17_7", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_IMUX26_7", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_WW2A3_7", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_WW2A2_7", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_BYP4_7", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_EE4BEG0_7", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_NE2A1_7", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_EE2BEG2_7", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_EE4B1_7", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_LH11_7", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_IMUX27_7", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_NE4C1_7", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_LH8_7", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_BYP1_7", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_EL1BEG2_7", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_ER1BEG2_7", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_LH5_7", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_WR1END1_7", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_NW2A1_7", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_IMUX14_7", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_IMUX10_7", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_BYP0_7", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_IMUX12_7", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_FAN1_7", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_WW4A3_7", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_IMUX46_7", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_NE4BEG3_7", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_NW2A0_7", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_IMUX41_7", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_EE4A1_7", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_LH12_7", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_WL1END0_7", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_SW4END0_7", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_LH2_7", + "INT_INTERFACE_LH2" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_1_EE4BEG2", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "INT_FEEDTHRU_1_WW2END3", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "INT_FEEDTHRU_1_WW4C3", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "INT_FEEDTHRU_1_EE4BEG0", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "INT_FEEDTHRU_1_NE4BEG1", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "INT_FEEDTHRU_1_LH3", + "INT_FEEDTHRU_2_LH3" + ], + [ + "INT_FEEDTHRU_1_LH10", + "INT_FEEDTHRU_2_LH10" + ], + [ + "INT_FEEDTHRU_1_ER1BEG1", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "INT_FEEDTHRU_1_NE4BEG3", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "INT_FEEDTHRU_1_NW4END0", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "INT_FEEDTHRU_1_EL1BEG0", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "INT_FEEDTHRU_1_WW4END3", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "INT_FEEDTHRU_1_NE2A2", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "INT_FEEDTHRU_1_EL1BEG3", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "INT_FEEDTHRU_1_SE4BEG1", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "INT_FEEDTHRU_1_SE4C3", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "INT_FEEDTHRU_1_MONITOR_P", + "INT_FEEDTHRU_2_MONITOR_P" + ], + [ + "INT_FEEDTHRU_1_EE4B2", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "INT_FEEDTHRU_1_WW4A3", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "INT_FEEDTHRU_1_WR1END1", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "INT_FEEDTHRU_1_EE4A2", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "INT_FEEDTHRU_1_NE2A0", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "INT_FEEDTHRU_1_EE4A1", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "INT_FEEDTHRU_1_WL1END3", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "INT_FEEDTHRU_1_EE2BEG3", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "INT_FEEDTHRU_1_WW2END1", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "INT_FEEDTHRU_1_ER1BEG2", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "INT_FEEDTHRU_1_WW2A2", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "INT_FEEDTHRU_1_LH8", + "INT_FEEDTHRU_2_LH8" + ], + [ + "INT_FEEDTHRU_1_WR1END2", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "INT_FEEDTHRU_1_EE4C1", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "INT_FEEDTHRU_1_WW4C0", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "INT_FEEDTHRU_1_LH11", + "INT_FEEDTHRU_2_LH11" + ], + [ + "INT_FEEDTHRU_1_LH4", + "INT_FEEDTHRU_2_LH4" + ], + [ + "INT_FEEDTHRU_1_LH9", + "INT_FEEDTHRU_2_LH9" + ], + [ + "INT_FEEDTHRU_1_NE4C1", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "INT_FEEDTHRU_1_NW2A0", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "INT_FEEDTHRU_1_SW4A0", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "INT_FEEDTHRU_1_WL1END2", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "INT_FEEDTHRU_1_EE4BEG3", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "INT_FEEDTHRU_1_SE4C2", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "INT_FEEDTHRU_1_NW2A2", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "INT_FEEDTHRU_1_WW4A1", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "INT_FEEDTHRU_1_NE4BEG0", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "INT_FEEDTHRU_1_EE4C2", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "INT_FEEDTHRU_1_WW4B1", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "INT_FEEDTHRU_1_MONITOR_N", + "INT_FEEDTHRU_2_MONITOR_N" + ], + [ + "INT_FEEDTHRU_1_WW4C1", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "INT_FEEDTHRU_1_LH12", + "INT_FEEDTHRU_2_LH12" + ], + [ + "INT_FEEDTHRU_1_EE2A0", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "INT_FEEDTHRU_1_SE4C1", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "INT_FEEDTHRU_1_EE4A0", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "INT_FEEDTHRU_1_SE2A3", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "INT_FEEDTHRU_1_WW4END2", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "INT_FEEDTHRU_1_SW4A2", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "INT_FEEDTHRU_1_SW2A3", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "INT_FEEDTHRU_1_SW4END1", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "INT_FEEDTHRU_1_SE2A1", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "INT_FEEDTHRU_1_NW4A3", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "INT_FEEDTHRU_1_EE2A2", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "INT_FEEDTHRU_1_WW4B3", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "INT_FEEDTHRU_1_SW4END2", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "INT_FEEDTHRU_1_ER1BEG0", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "INT_FEEDTHRU_1_ER1BEG3", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "INT_FEEDTHRU_1_WW4END0", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "INT_FEEDTHRU_1_EE4C3", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "INT_FEEDTHRU_1_NE2A1", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "INT_FEEDTHRU_1_EE4B1", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "INT_FEEDTHRU_1_WW4A2", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "INT_FEEDTHRU_1_NW4A1", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "INT_FEEDTHRU_1_NW4A0", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "INT_FEEDTHRU_1_EE4B3", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "INT_FEEDTHRU_1_SW4END3", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "INT_FEEDTHRU_1_WW2END2", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "INT_FEEDTHRU_1_WL1END1", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "INT_FEEDTHRU_1_LH7", + "INT_FEEDTHRU_2_LH7" + ], + [ + "INT_FEEDTHRU_1_WW2END0", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "INT_FEEDTHRU_1_SE4BEG2", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "INT_FEEDTHRU_1_SW2A1", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "INT_FEEDTHRU_1_EE2BEG2", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "INT_FEEDTHRU_1_LH6", + "INT_FEEDTHRU_2_LH6" + ], + [ + "INT_FEEDTHRU_1_NW2A1", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "INT_FEEDTHRU_1_SE4BEG3", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "INT_FEEDTHRU_1_WW2A1", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "INT_FEEDTHRU_1_NW4A2", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "INT_FEEDTHRU_1_EE4C0", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "INT_FEEDTHRU_1_NE4C3", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "INT_FEEDTHRU_1_SE2A0", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "INT_FEEDTHRU_1_EE2BEG0", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "INT_FEEDTHRU_1_SE2A2", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "INT_FEEDTHRU_1_SW4A1", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "INT_FEEDTHRU_1_WW4C2", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "INT_FEEDTHRU_1_WW2A0", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "INT_FEEDTHRU_1_WW4B0", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "INT_FEEDTHRU_1_LH1", + "INT_FEEDTHRU_2_LH1" + ], + [ + "INT_FEEDTHRU_1_NW4END3", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "INT_FEEDTHRU_1_WW4A0", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "INT_FEEDTHRU_1_NE4C2", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "INT_FEEDTHRU_1_WW4B2", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "INT_FEEDTHRU_1_NW4END1", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "INT_FEEDTHRU_1_NW2A3", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "INT_FEEDTHRU_1_SE4C0", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "INT_FEEDTHRU_1_EE2A1", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "INT_FEEDTHRU_1_WR1END0", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "INT_FEEDTHRU_1_EL1BEG1", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "INT_FEEDTHRU_1_SE4BEG0", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "INT_FEEDTHRU_1_NE4BEG2", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "INT_FEEDTHRU_1_NW4END2", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "INT_FEEDTHRU_1_EE2A3", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "INT_FEEDTHRU_1_EE4A3", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "INT_FEEDTHRU_1_WR1END3", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "INT_FEEDTHRU_1_EE4B0", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "INT_FEEDTHRU_1_SW4A3", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "INT_FEEDTHRU_1_WW4END1", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "INT_FEEDTHRU_1_WL1END0", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "INT_FEEDTHRU_1_SW2A0", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "INT_FEEDTHRU_1_LH2", + "INT_FEEDTHRU_2_LH2" + ], + [ + "INT_FEEDTHRU_1_LH5", + "INT_FEEDTHRU_2_LH5" + ], + [ + "INT_FEEDTHRU_1_EL1BEG2", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "INT_FEEDTHRU_1_WW2A3", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "INT_FEEDTHRU_1_EE4BEG1", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "INT_FEEDTHRU_1_NE2A3", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "INT_FEEDTHRU_1_SW4END0", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "INT_FEEDTHRU_1_SW2A2", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "INT_FEEDTHRU_1_NE4C0", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "INT_FEEDTHRU_1_EE2BEG1", + "INT_FEEDTHRU_2_EE2BEG1" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_1", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "NW6D0", + "NW6E0" + ], + [ + "NW6D2", + "NW6E2" + ], + [ + "SW2A2", + "SW2BEG2" + ], + [ + "NN6E2", + "NN6END2" + ], + [ + "LV17", + "LV18" + ], + [ + "NW6A1", + "NW6B1" + ], + [ + "LV16", + "LV17" + ], + [ + "NW6B3", + "NW6C3" + ], + [ + "NE6C0", + "NE6D0" + ], + [ + "NE6A1", + "NE6B1" + ], + [ + "NN6A1", + "NN6B1" + ], + [ + "NN6E1", + "NN6END1" + ], + [ + "NN2A2", + "NN2END2" + ], + [ + "SE2A3", + "SE2BEG3" + ], + [ + "NE6B2", + "NE6C2" + ], + [ + "NL1BEG1", + "NL1END1" + ], + [ + "NE6D0", + "NE6E0" + ], + [ + "NN6C1", + "NN6D1" + ], + [ + "LVB5", + "LVB6" + ], + [ + "SS6A3", + "SS6BEG3" + ], + [ + "LVB10", + "LVB11" + ], + [ + "LV1", + "LV2" + ], + [ + "NL1BEG0", + "NL1END0" + ], + [ + "NN6D2", + "NN6E2" + ], + [ + "SE2A1", + "SE2BEG1" + ], + [ + "NE6B3", + "NE6C3" + ], + [ + "NL1BEG2", + "NL1END2" + ], + [ + "LVB1", + "LVB2" + ], + [ + "LV5", + "LV6" + ], + [ + "SE2A2", + "SE2BEG2" + ], + [ + "NN6D1", + "NN6E1" + ], + [ + "LV15", + "LV16" + ], + [ + "NW6A3", + "NW6B3" + ], + [ + "NE6C2", + "NE6D2" + ], + [ + "NN6B3", + "NN6C3" + ], + [ + "NW6A2", + "NW6B2" + ], + [ + "SS2A0", + "SS2BEG0" + ], + [ + "SW2A1", + "SW2BEG1" + ], + [ + "NW6C1", + "NW6D1" + ], + [ + "LV8", + "LV9" + ], + [ + "BYP_BOUNCE2", + "BYP_BOUNCE_N3_2" + ], + [ + "LV2", + "LV3" + ], + [ + "NN6A0", + "NN6B0" + ], + [ + "NE6A0", + "NE6B0" + ], + [ + "NN6E3", + "NN6END3" + ], + [ + "NN2A0", + "NN2END0" + ], + [ + "NE6A2", + "NE6B2" + ], + [ + "LV12", + "LV13" + ], + [ + "SS2A1", + "SS2BEG1" + ], + [ + "SS2A2", + "SS2BEG2" + ], + [ + "BYP_BOUNCE3", + "BYP_BOUNCE_N3_3" + ], + [ + "NE6D2", + "NE6E2" + ], + [ + "NR1BEG2", + "NR1END2" + ], + [ + "NN6E0", + "NN6END0" + ], + [ + "NN6B0", + "NN6C0" + ], + [ + "NW6A0", + "NW6B0" + ], + [ + "NE6B1", + "NE6C1" + ], + [ + "LVB0", + "LVB1" + ], + [ + "NN2A3", + "NN2END3" + ], + [ + "LV7", + "LV8" + ], + [ + "BYP_BOUNCE7", + "BYP_BOUNCE_N3_7" + ], + [ + "NW6C3", + "NW6D3" + ], + [ + "LV13", + "LV14" + ], + [ + "SS2A3", + "SS2BEG3" + ], + [ + "ER1END3", + "ER1END_N3_3" + ], + [ + "LVB3", + "LVB4" + ], + [ + "WW2END3", + "WW2END_N0_3" + ], + [ + "NW6D1", + "NW6E1" + ], + [ + "LV0", + "LV1" + ], + [ + "SW2A3", + "SW2BEG3" + ], + [ + "SR1END3", + "SR1END_N3_3" + ], + [ + "NN6D0", + "NN6E0" + ], + [ + "WL1BEG3", + "WL1BEG_N3" + ], + [ + "NE6D3", + "NE6E3" + ], + [ + "SW2A0", + "SW2BEG0" + ], + [ + "LVB2", + "LVB3" + ], + [ + "NN2A1", + "NN2END1" + ], + [ + "NN6A2", + "NN6B2" + ], + [ + "SS6END3", + "SS6END_N0_3" + ], + [ + "NN6A3", + "NN6B3" + ], + [ + "LVB11", + "LVB12" + ], + [ + "NN6C2", + "NN6D2" + ], + [ + "WL1END3", + "WL1END_N1_3" + ], + [ + "NW6D3", + "NW6E3" + ], + [ + "NW6B0", + "NW6C0" + ], + [ + "SE2A0", + "SE2BEG0" + ], + [ + "LVB7", + "LVB8" + ], + [ + "NN6B1", + "NN6C1" + ], + [ + "NR1BEG1", + "NR1END1" + ], + [ + "LV4", + "LV5" + ], + [ + "LV10", + "LV11" + ], + [ + "NE6A3", + "NE6B3" + ], + [ + "LV3", + "LV4" + ], + [ + "NW6C2", + "NW6D2" + ], + [ + "LVB4", + "LVB5" + ], + [ + "EL1BEG3", + "EL1BEG_N3" + ], + [ + "SS6A2", + "SS6BEG2" + ], + [ + "LV11", + "LV12" + ], + [ + "NW6B2", + "NW6C2" + ], + [ + "LV14", + "LV15" + ], + [ + "NR1BEG3", + "NR1END3" + ], + [ + "LV6", + "LV7" + ], + [ + "NE6C3", + "NE6D3" + ], + [ + "BYP_BOUNCE6", + "BYP_BOUNCE_N3_6" + ], + [ + "NE6C1", + "NE6D1" + ], + [ + "LVB6", + "LVB7" + ], + [ + "NN6C0", + "NN6D0" + ], + [ + "NN6B2", + "NN6C2" + ], + [ + "NE6D1", + "NE6E1" + ], + [ + "NW6B1", + "NW6C1" + ], + [ + "NR1BEG0", + "NR1END0" + ], + [ + "SS6A1", + "SS6BEG1" + ], + [ + "SS2END3", + "SS2END_N0_3" + ], + [ + "SW2END3", + "SW2END_N0_3" + ], + [ + "NW6C0", + "NW6D0" + ], + [ + "NN6D3", + "NN6E3" + ], + [ + "NN6C3", + "NN6D3" + ], + [ + "SS6A0", + "SS6BEG0" + ], + [ + "SW6END3", + "SW6END_N0_3" + ], + [ + "LVB8", + "LVB9" + ], + [ + "NE6B0", + "NE6C0" + ] + ], + "tile_types": [ + "INT_R", + "INT_R" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "DSP_IMUX39_0", + "INT_INTERFACE_IMUX39" + ], + [ + "DSP_ER1BEG2_0", + "INT_INTERFACE_ER1BEG2" + ], + [ + "DSP_ER1BEG3_0", + "INT_INTERFACE_ER1BEG3" + ], + [ + "DSP_EL1BEG2_0", + "INT_INTERFACE_EL1BEG2" + ], + [ + "DSP_LOGIC_OUTS_B3_0", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "DSP_WW4B2_0", + "INT_INTERFACE_WW4B2" + ], + [ + "DSP_IMUX26_0", + "INT_INTERFACE_IMUX26" + ], + [ + "DSP_EE4C1_0", + "INT_INTERFACE_EE4C1" + ], + [ + "DSP_WW2A2_0", + "INT_INTERFACE_WW2A2" + ], + [ + "DSP_EE4A0_0", + "INT_INTERFACE_EE4A0" + ], + [ + "DSP_EE4BEG3_0", + "INT_INTERFACE_EE4BEG3" + ], + [ + "DSP_IMUX20_0", + "INT_INTERFACE_IMUX20" + ], + [ + "DSP_WL1END0_0", + "INT_INTERFACE_WL1END0" + ], + [ + "DSP_EE4C2_0", + "INT_INTERFACE_EE4C2" + ], + [ + "DSP_IMUX44_0", + "INT_INTERFACE_IMUX44" + ], + [ + "DSP_NW4END3_0", + "INT_INTERFACE_NW4END3" + ], + [ + "DSP_IMUX35_0", + "INT_INTERFACE_IMUX35" + ], + [ + "DSP_IMUX30_0", + "INT_INTERFACE_IMUX30" + ], + [ + "DSP_NE4C1_0", + "INT_INTERFACE_NE4C1" + ], + [ + "DSP_LH3_0", + "INT_INTERFACE_LH3" + ], + [ + "DSP_EE4B0_0", + "INT_INTERFACE_EE4B0" + ], + [ + "DSP_SE4BEG1_0", + "INT_INTERFACE_SE4BEG1" + ], + [ + "DSP_WW2A1_0", + "INT_INTERFACE_WW2A1" + ], + [ + "DSP_WL1END2_0", + "INT_INTERFACE_WL1END2" + ], + [ + "DSP_IMUX19_0", + "INT_INTERFACE_IMUX19" + ], + [ + "DSP_EE2A2_0", + "INT_INTERFACE_EE2A2" + ], + [ + "DSP_WW4A2_0", + "INT_INTERFACE_WW4A2" + ], + [ + "DSP_WW4B3_0", + "INT_INTERFACE_WW4B3" + ], + [ + "DSP_IMUX43_0", + "INT_INTERFACE_IMUX43" + ], + [ + "DSP_WW4END2_0", + "INT_INTERFACE_WW4END2" + ], + [ + "DSP_LH8_0", + "INT_INTERFACE_LH8" + ], + [ + "DSP_EE4BEG1_0", + "INT_INTERFACE_EE4BEG1" + ], + [ + "DSP_LOGIC_OUTS_B7_0", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "DSP_WW2END1_0", + "INT_INTERFACE_WW2END1" + ], + [ + "DSP_BYP2_0", + "INT_INTERFACE_BYP2" + ], + [ + "DSP_NE2A2_0", + "INT_INTERFACE_NE2A2" + ], + [ + "DSP_LH4_0", + "INT_INTERFACE_LH4" + ], + [ + "DSP_EE4C0_0", + "INT_INTERFACE_EE4C0" + ], + [ + "DSP_CLK0_0", + "INT_INTERFACE_CLK0" + ], + [ + "DSP_LOGIC_OUTS_B21_0", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "DSP_BYP3_0", + "INT_INTERFACE_BYP3" + ], + [ + "DSP_NW2A1_0", + "INT_INTERFACE_NW2A1" + ], + [ + "DSP_FAN0_0", + "INT_INTERFACE_FAN0" + ], + [ + "DSP_MONITOR_N_0", + "INT_INTERFACE_MONITOR_N" + ], + [ + "DSP_EE2BEG0_0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "DSP_IMUX23_0", + "INT_INTERFACE_IMUX23" + ], + [ + "DSP_SE4C1_0", + "INT_INTERFACE_SE4C1" + ], + [ + "DSP_LOGIC_OUTS_B5_0", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "DSP_WW4A3_0", + "INT_INTERFACE_WW4A3" + ], + [ + "DSP_EL1BEG3_0", + "INT_INTERFACE_EL1BEG3" + ], + [ + "DSP_NE4BEG3_0", + "INT_INTERFACE_NE4BEG3" + ], + [ + "DSP_LOGIC_OUTS_B0_0", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "DSP_LOGIC_OUTS_B23_0", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "DSP_IMUX29_0", + "INT_INTERFACE_IMUX29" + ], + [ + "DSP_IMUX28_0", + "INT_INTERFACE_IMUX28" + ], + [ + "DSP_FAN1_0", + "INT_INTERFACE_FAN1" + ], + [ + "DSP_IMUX0_0", + "INT_INTERFACE_IMUX0" + ], + [ + "DSP_WL1END1_0", + "INT_INTERFACE_WL1END1" + ], + [ + "DSP_IMUX15_0", + "INT_INTERFACE_IMUX15" + ], + [ + "DSP_IMUX33_0", + "INT_INTERFACE_IMUX33" + ], + [ + "DSP_EL1BEG0_0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "DSP_IMUX36_0", + "INT_INTERFACE_IMUX36" + ], + [ + "DSP_SE4C2_0", + "INT_INTERFACE_SE4C2" + ], + [ + "DSP_WW4C3_0", + "INT_INTERFACE_WW4C3" + ], + [ + "DSP_LH11_0", + "INT_INTERFACE_LH11" + ], + [ + "DSP_WR1END2_0", + "INT_INTERFACE_WR1END2" + ], + [ + "DSP_LH12_0", + "INT_INTERFACE_LH12" + ], + [ + "DSP_IMUX34_0", + "INT_INTERFACE_IMUX34" + ], + [ + "DSP_NW2A0_0", + "INT_INTERFACE_NW2A0" + ], + [ + "DSP_SE2A1_0", + "INT_INTERFACE_SE2A1" + ], + [ + "DSP_EE4BEG2_0", + "INT_INTERFACE_EE4BEG2" + ], + [ + "DSP_LOGIC_OUTS_B6_0", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "DSP_FAN2_0", + "INT_INTERFACE_FAN2" + ], + [ + "DSP_IMUX1_0", + "INT_INTERFACE_IMUX1" + ], + [ + "DSP_FAN3_0", + "INT_INTERFACE_FAN3" + ], + [ + "DSP_MONITOR_P_0", + "INT_INTERFACE_MONITOR_P" + ], + [ + "DSP_NE4BEG1_0", + "INT_INTERFACE_NE4BEG1" + ], + [ + "DSP_IMUX3_0", + "INT_INTERFACE_IMUX3" + ], + [ + "DSP_WW4END1_0", + "INT_INTERFACE_WW4END1" + ], + [ + "DSP_LOGIC_OUTS_B12_0", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "DSP_EL1BEG1_0", + "INT_INTERFACE_EL1BEG1" + ], + [ + "DSP_IMUX17_0", + "INT_INTERFACE_IMUX17" + ], + [ + "DSP_IMUX22_0", + "INT_INTERFACE_IMUX22" + ], + [ + "DSP_SE4C3_0", + "INT_INTERFACE_SE4C3" + ], + [ + "DSP_LOGIC_OUTS_B4_0", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "DSP_NE4C2_0", + "INT_INTERFACE_NE4C2" + ], + [ + "DSP_LH1_0", + "INT_INTERFACE_LH1" + ], + [ + "DSP_SW4END3_0", + "INT_INTERFACE_SW4END3" + ], + [ + "DSP_FAN5_0", + "INT_INTERFACE_FAN5" + ], + [ + "DSP_BYP5_0", + "INT_INTERFACE_BYP5" + ], + [ + "DSP_LOGIC_OUTS_B8_0", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "DSP_LH2_0", + "INT_INTERFACE_LH2" + ], + [ + "DSP_SW4END2_0", + "INT_INTERFACE_SW4END2" + ], + [ + "DSP_LOGIC_OUTS_B22_0", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "DSP_SW4A2_0", + "INT_INTERFACE_SW4A2" + ], + [ + "DSP_LOGIC_OUTS_B18_0", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "DSP_LH6_0", + "INT_INTERFACE_LH6" + ], + [ + "DSP_IMUX10_0", + "INT_INTERFACE_IMUX10" + ], + [ + "DSP_SE4BEG3_0", + "INT_INTERFACE_SE4BEG3" + ], + [ + "DSP_BYP1_0", + "INT_INTERFACE_BYP1" + ], + [ + "DSP_WR1END3_0", + "INT_INTERFACE_WR1END3" + ], + [ + "DSP_WL1END3_0", + "INT_INTERFACE_WL1END3" + ], + [ + "DSP_SE2A3_0", + "INT_INTERFACE_SE2A3" + ], + [ + "DSP_NW4A2_0", + "INT_INTERFACE_NW4A2" + ], + [ + "DSP_WW4C0_0", + "INT_INTERFACE_WW4C0" + ], + [ + "DSP_IMUX4_0", + "INT_INTERFACE_IMUX4" + ], + [ + "DSP_SW4A1_0", + "INT_INTERFACE_SW4A1" + ], + [ + "DSP_IMUX12_0", + "INT_INTERFACE_IMUX12" + ], + [ + "DSP_LOGIC_OUTS_B11_0", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "DSP_SW4END1_0", + "INT_INTERFACE_SW4END1" + ], + [ + "DSP_NE4BEG2_0", + "INT_INTERFACE_NE4BEG2" + ], + [ + "DSP_NW4A3_0", + "INT_INTERFACE_NW4A3" + ], + [ + "DSP_WW2END0_0", + "INT_INTERFACE_WW2END0" + ], + [ + "DSP_EE4A2_0", + "INT_INTERFACE_EE4A2" + ], + [ + "DSP_SE4BEG0_0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "DSP_EE2A1_0", + "INT_INTERFACE_EE2A1" + ], + [ + "DSP_WR1END1_0", + "INT_INTERFACE_WR1END1" + ], + [ + "DSP_SW2A3_0", + "INT_INTERFACE_SW2A3" + ], + [ + "DSP_SW2A1_0", + "INT_INTERFACE_SW2A1" + ], + [ + "DSP_EE2BEG3_0", + "INT_INTERFACE_EE2BEG3" + ], + [ + "DSP_IMUX47_0", + "INT_INTERFACE_IMUX47" + ], + [ + "DSP_IMUX38_0", + "INT_INTERFACE_IMUX38" + ], + [ + "DSP_WW4A1_0", + "INT_INTERFACE_WW4A1" + ], + [ + "DSP_BYP7_0", + "INT_INTERFACE_BYP7" + ], + [ + "DSP_FAN7_0", + "INT_INTERFACE_FAN7" + ], + [ + "DSP_IMUX2_0", + "INT_INTERFACE_IMUX2" + ], + [ + "DSP_IMUX8_0", + "INT_INTERFACE_IMUX8" + ], + [ + "DSP_NE2A3_0", + "INT_INTERFACE_NE2A3" + ], + [ + "DSP_LOGIC_OUTS_B9_0", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "DSP_IMUX18_0", + "INT_INTERFACE_IMUX18" + ], + [ + "DSP_BYP4_0", + "INT_INTERFACE_BYP4" + ], + [ + "DSP_FAN4_0", + "INT_INTERFACE_FAN4" + ], + [ + "DSP_LH7_0", + "INT_INTERFACE_LH7" + ], + [ + "DSP_SE4C0_0", + "INT_INTERFACE_SE4C0" + ], + [ + "DSP_IMUX13_0", + "INT_INTERFACE_IMUX13" + ], + [ + "DSP_FAN6_0", + "INT_INTERFACE_FAN6" + ], + [ + "DSP_EE2A3_0", + "INT_INTERFACE_EE2A3" + ], + [ + "DSP_WW2A3_0", + "INT_INTERFACE_WW2A3" + ], + [ + "DSP_NW4A1_0", + "INT_INTERFACE_NW4A1" + ], + [ + "DSP_IMUX9_0", + "INT_INTERFACE_IMUX9" + ], + [ + "DSP_IMUX27_0", + "INT_INTERFACE_IMUX27" + ], + [ + "DSP_EE4C3_0", + "INT_INTERFACE_EE4C3" + ], + [ + "DSP_WW2END2_0", + "INT_INTERFACE_WW2END2" + ], + [ + "DSP_WW4C1_0", + "INT_INTERFACE_WW4C1" + ], + [ + "DSP_EE4A1_0", + "INT_INTERFACE_EE4A1" + ], + [ + "DSP_NE4BEG0_0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "DSP_CTRL0_0", + "INT_INTERFACE_CTRL0" + ], + [ + "DSP_LOGIC_OUTS_B17_0", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "DSP_WW2A0_0", + "INT_INTERFACE_WW2A0" + ], + [ + "DSP_WW4END0_0", + "INT_INTERFACE_WW4END0" + ], + [ + "DSP_SE2A0_0", + "INT_INTERFACE_SE2A0" + ], + [ + "DSP_EE4B1_0", + "INT_INTERFACE_EE4B1" + ], + [ + "DSP_SW4A0_0", + "INT_INTERFACE_SW4A0" + ], + [ + "DSP_LH5_0", + "INT_INTERFACE_LH5" + ], + [ + "DSP_WW4C2_0", + "INT_INTERFACE_WW4C2" + ], + [ + "DSP_EE4B3_0", + "INT_INTERFACE_EE4B3" + ], + [ + "DSP_WW4END3_0", + "INT_INTERFACE_WW4END3" + ], + [ + "DSP_IMUX37_0", + "INT_INTERFACE_IMUX37" + ], + [ + "DSP_NE2A0_0", + "INT_INTERFACE_NE2A0" + ], + [ + "DSP_SE2A2_0", + "INT_INTERFACE_SE2A2" + ], + [ + "DSP_LOGIC_OUTS_B19_0", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "DSP_BYP0_0", + "INT_INTERFACE_BYP0" + ], + [ + "DSP_SW2A0_0", + "INT_INTERFACE_SW2A0" + ], + [ + "DSP_LOGIC_OUTS_B1_0", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "DSP_IMUX46_0", + "INT_INTERFACE_IMUX46" + ], + [ + "DSP_IMUX32_0", + "INT_INTERFACE_IMUX32" + ], + [ + "DSP_NW4A0_0", + "INT_INTERFACE_NW4A0" + ], + [ + "DSP_LOGIC_OUTS_B15_0", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "DSP_EE2A0_0", + "INT_INTERFACE_EE2A0" + ], + [ + "DSP_EE4BEG0_0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "DSP_EE4A3_0", + "INT_INTERFACE_EE4A3" + ], + [ + "DSP_EE4B2_0", + "INT_INTERFACE_EE4B2" + ], + [ + "DSP_BYP6_0", + "INT_INTERFACE_BYP6" + ], + [ + "DSP_NE4C0_0", + "INT_INTERFACE_NE4C0" + ], + [ + "DSP_SE4BEG2_0", + "INT_INTERFACE_SE4BEG2" + ], + [ + "DSP_WW4B0_0", + "INT_INTERFACE_WW4B0" + ], + [ + "DSP_SW2A2_0", + "INT_INTERFACE_SW2A2" + ], + [ + "DSP_IMUX21_0", + "INT_INTERFACE_IMUX21" + ], + [ + "DSP_NW4END0_0", + "INT_INTERFACE_NW4END0" + ], + [ + "DSP_IMUX11_0", + "INT_INTERFACE_IMUX11" + ], + [ + "DSP_IMUX6_0", + "INT_INTERFACE_IMUX6" + ], + [ + "DSP_IMUX40_0", + "INT_INTERFACE_IMUX40" + ], + [ + "DSP_CTRL1_0", + "INT_INTERFACE_CTRL1" + ], + [ + "DSP_NW4END1_0", + "INT_INTERFACE_NW4END1" + ], + [ + "DSP_IMUX14_0", + "INT_INTERFACE_IMUX14" + ], + [ + "DSP_NW2A2_0", + "INT_INTERFACE_NW2A2" + ], + [ + "DSP_LOGIC_OUTS_B20_0", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "DSP_ER1BEG0_0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "DSP_IMUX7_0", + "INT_INTERFACE_IMUX7" + ], + [ + "DSP_SW4A3_0", + "INT_INTERFACE_SW4A3" + ], + [ + "DSP_LOGIC_OUTS_B16_0", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "DSP_WW4A0_0", + "INT_INTERFACE_WW4A0" + ], + [ + "DSP_NW4END2_0", + "INT_INTERFACE_NW4END2" + ], + [ + "DSP_NE2A1_0", + "INT_INTERFACE_NE2A1" + ], + [ + "DSP_NW2A3_0", + "INT_INTERFACE_NW2A3" + ], + [ + "DSP_IMUX45_0", + "INT_INTERFACE_IMUX45" + ], + [ + "DSP_IMUX24_0", + "INT_INTERFACE_IMUX24" + ], + [ + "DSP_IMUX25_0", + "INT_INTERFACE_IMUX25" + ], + [ + "DSP_SW4END0_0", + "INT_INTERFACE_SW4END0" + ], + [ + "DSP_LOGIC_OUTS_B13_0", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "DSP_EE2BEG2_0", + "INT_INTERFACE_EE2BEG2" + ], + [ + "DSP_CLK1_0", + "INT_INTERFACE_CLK1" + ], + [ + "DSP_WR1END0_0", + "INT_INTERFACE_WR1END0" + ], + [ + "DSP_LOGIC_OUTS_B14_0", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "DSP_LOGIC_OUTS_B2_0", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "DSP_IMUX31_0", + "INT_INTERFACE_IMUX31" + ], + [ + "DSP_WW2END3_0", + "INT_INTERFACE_WW2END3" + ], + [ + "DSP_IMUX16_0", + "INT_INTERFACE_IMUX16" + ], + [ + "DSP_ER1BEG1_0", + "INT_INTERFACE_ER1BEG1" + ], + [ + "DSP_IMUX42_0", + "INT_INTERFACE_IMUX42" + ], + [ + "DSP_LOGIC_OUTS_B10_0", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "DSP_LH10_0", + "INT_INTERFACE_LH10" + ], + [ + "DSP_EE2BEG1_0", + "INT_INTERFACE_EE2BEG1" + ], + [ + "DSP_NE4C3_0", + "INT_INTERFACE_NE4C3" + ], + [ + "DSP_WW4B1_0", + "INT_INTERFACE_WW4B1" + ], + [ + "DSP_IMUX5_0", + "INT_INTERFACE_IMUX5" + ], + [ + "DSP_IMUX41_0", + "INT_INTERFACE_IMUX41" + ], + [ + "DSP_LH9_0", + "INT_INTERFACE_LH9" + ] + ], + "tile_types": [ + "DSP_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 5, + -1 + ], + "wire_pairs": [ + [ + "PCIE_LOGIC_OUTS_B1_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_WW2A3_11", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_NW2A2_11", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_CLK0_L_11", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_IMUX6_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_SE4BEG2_11", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_SE4C1_11", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_SW4END0_11", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_FAN1_L_11", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_NW4A1_11", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_NE4BEG2_11", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_SW4A2_11", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_EE4B0_11", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_WW2END2_11", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_WW4END2_11", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_LH5_11", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_WW4A0_11", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_EE2BEG1_11", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_BYP1_L_11", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_WW2END3_11", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_NE4C2_11", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_WW4A3_11", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_IMUX30_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_EE4B3_11", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_IMUX44_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_IMUX29_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_FAN7_L_11", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_SE4BEG3_11", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_WW4END1_11", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_EE4BEG2_11", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_NW4END0_11", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_IMUX13_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_SE2A0_11", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_WR1END1_11", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_SW4END2_11", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_BYP5_L_11", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_IMUX46_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_LH2_11", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_NW2A1_11", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_SW2A3_11", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_SW2A1_11", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_EE2A0_11", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_IMUX31_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_IMUX16_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_WW2A1_11", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_EE2BEG3_11", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_SE4C2_11", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_SE2A1_11", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_IMUX12_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_EL1BEG0_11", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_IMUX8_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_WR1END3_11", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_LH8_11", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_IMUX41_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_WW4A2_11", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_NE2A2_11", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_WW4C0_11", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_EE4A0_11", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_IMUX19_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_IMUX18_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_WW4C2_11", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_EE4BEG0_11", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX23_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_NE4C1_11", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_IMUX32_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_EE4A2_11", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_EE2A1_11", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_LH9_11", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_EE4C3_11", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_FAN4_L_11", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_LH12_11", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_IMUX25_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_EE4BEG3_11", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_IMUX5_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_WR1END2_11", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_SW4A0_11", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_IMUX14_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_IMUX36_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_IMUX26_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_BYP7_L_11", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_SE2A2_11", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_WR1END0_11", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_CTRL0_L_11", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_IMUX7_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_IMUX9_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_EE4BEG1_11", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_EL1BEG1_11", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_LH7_11", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_NE4BEG0_11", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_BYP6_L_11", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_WW4B2_11", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_IMUX10_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_IMUX43_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_FAN5_L_11", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_FAN0_L_11", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_SW4A3_11", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_WL1END3_11", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_FAN2_L_11", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_EE2A3_11", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_IMUX20_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_NW4A3_11", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_BYP3_L_11", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_EE4A3_11", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_FAN3_L_11", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_WW2END1_11", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_WL1END1_11", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_WW2A2_11", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_SE4C0_11", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_CTRL1_L_11", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_IMUX40_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_WW4END0_11", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_NW2A3_11", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_BYP0_L_11", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_SE4BEG1_11", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_WW4B0_11", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_WW4END3_11", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_LH3_11", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_SW4A1_11", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_NW4A2_11", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_WW2A0_11", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_EE2A2_11", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_LH11_11", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_IMUX47_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_IMUX0_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_EE4C0_11", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX35_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_WW4B3_11", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_IMUX34_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_WL1END2_11", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_MONITOR_P_11", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_WW2END0_11", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_IMUX24_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_LH4_11", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_SE2A3_11", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_IMUX2_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_BYP2_L_11", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_IMUX22_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_IMUX38_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_NE4BEG3_11", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_SW4END3_11", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_ER1BEG3_11", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_IMUX39_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_ER1BEG0_11", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_NE2A1_11", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_NE2A3_11", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_WW4C3_11", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_WW4A1_11", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_EE4B1_11", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_SW4END1_11", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_EE4B2_11", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_CLK1_L_11", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_WW4B1_11", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_NE4C3_11", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_NW2A0_11", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_SE4BEG0_11", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_EL1BEG2_11", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_IMUX37_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_EE2BEG2_11", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_EE4C2_11", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_IMUX33_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_IMUX15_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_IMUX28_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_NE4C0_11", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_EE4C1_11", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_EE2BEG0_11", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_ER1BEG2_11", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_IMUX45_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_LH6_11", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_NW4A0_11", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_SW2A2_11", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_BYP4_L_11", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_IMUX4_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_WW4C1_11", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_MONITOR_N_11", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_SW2A0_11", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX11_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_IMUX27_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_IMUX3_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_FAN6_L_11", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_NW4END1_11", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_NW4END3_11", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_ER1BEG1_11", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_EE4A1_11", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_IMUX21_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_IMUX17_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_NW4END2_11", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_EL1BEG3_11", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_LH10_11", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_LH1_11", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_IMUX42_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_SE4C3_11", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_WL1END0_11", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_IMUX1_L_11", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_NE2A0_11", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_NE4BEG1_11", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_11", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 5, + 1 + ], + "wire_pairs": [ + [ + "PCIE_LH10_9", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_IMUX38_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_NW4A3_9", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_WW4END0_9", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_SE4C3_9", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_SW4A2_9", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_NW4A0_9", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WR1END2_9", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_WW2END2_9", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_BYP3_L_9", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_IMUX4_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_SW2A1_9", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_LH4_9", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_WL1END3_9", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_NE2A3_9", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_IMUX35_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_LH8_9", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4BEG1_9", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LH12_9", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_WL1END2_9", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_LH5_9", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_IMUX7_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_IMUX22_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_WW4C0_9", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_NW2A0_9", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_IMUX13_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_IMUX2_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_IMUX41_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_WW4END3_9", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_CLK0_L_9", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_EL1BEG2_9", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_FAN1_L_9", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_WR1END1_9", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_EE4BEG2_9", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_WW4A3_9", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_IMUX30_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_NE4BEG2_9", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_ER1BEG2_9", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_NW4END1_9", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_EE4C3_9", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_SW2A2_9", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_EE2A1_9", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_EE4C0_9", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_EE4B0_9", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX21_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_WW4A0_9", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_LH11_9", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_NE4C2_9", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_IMUX16_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_IMUX12_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_CTRL0_L_9", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_BYP4_L_9", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_IMUX15_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_SW2A0_9", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX31_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_LH1_9", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_IMUX29_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_IMUX45_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_BYP0_L_9", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_IMUX20_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_FAN0_L_9", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_WW4A1_9", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_LH3_9", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_IMUX9_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_WR1END3_9", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_WW4B0_9", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_IMUX27_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_SE2A2_9", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_EL1BEG0_9", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_BYP7_L_9", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_SW4END3_9", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_IMUX26_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_FAN2_L_9", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_ER1BEG0_9", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_IMUX0_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_NW4END3_9", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_EE2BEG0_9", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_NE2A0_9", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_ER1BEG1_9", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_EE4A2_9", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_SE4BEG1_9", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_LH7_9", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_WW2END1_9", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_SE4C0_9", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_NE4BEG1_9", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX8_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_BYP1_L_9", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_IMUX34_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_NW4A2_9", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_NW2A1_9", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_IMUX6_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_SE4C2_9", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_EE2A3_9", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_WR1END0_9", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_SE4BEG0_9", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_EL1BEG3_9", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_FAN3_L_9", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_BYP5_L_9", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_EE2A0_9", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_NE4C1_9", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_BYP2_L_9", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_IMUX18_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_CLK1_L_9", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_NW4END0_9", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_SE4BEG2_9", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_WW4B2_9", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_IMUX39_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_EE4BEG0_9", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_WW2A3_9", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_IMUX33_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_EE4A0_9", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_SW4A3_9", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_BYP6_L_9", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_EE2BEG3_9", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_MONITOR_N_9", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_NE4C0_9", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_LH2_9", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_SW4A1_9", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_WL1END1_9", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_IMUX14_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_FAN5_L_9", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_IMUX46_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_NW2A3_9", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_SE2A3_9", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_IMUX10_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_EE2BEG2_9", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_SW4A0_9", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_IMUX43_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_SW4END1_9", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_EE2BEG1_9", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_IMUX23_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_NW2A2_9", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_EE4C1_9", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_IMUX36_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_WW4END2_9", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_NW4A1_9", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_NW4END2_9", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_LH9_9", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_NE2A1_9", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_SE2A0_9", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_EE4BEG3_9", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_FAN7_L_9", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_IMUX25_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_WW2END3_9", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_IMUX3_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_IMUX40_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_IMUX5_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_WW4A2_9", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_NE2A2_9", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_SW2A3_9", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_CTRL1_L_9", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_IMUX1_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_SW4END2_9", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_IMUX32_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_SE2A1_9", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_MONITOR_P_9", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_EL1BEG1_9", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_EE4A1_9", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_IMUX42_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_WW2END0_9", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_WW4C3_9", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_SE4C1_9", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_SW4END0_9", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_EE4B1_9", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_IMUX19_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_FAN6_L_9", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_EE4B2_9", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_IMUX37_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_IMUX17_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_FAN4_L_9", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_EE4C2_9", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_NE4BEG0_9", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_LH6_9", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_IMUX11_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_IMUX44_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_WW4C2_9", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_WW4B1_9", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_ER1BEG3_9", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_IMUX28_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_NE4C3_9", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_NE4BEG3_9", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_EE4B3_9", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_EE4A3_9", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_WW2A0_9", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_WW4B3_9", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_WW4END1_9", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_WW2A2_9", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_IMUX24_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_EE2A2_9", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_WL1END0_9", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_WW4C1_9", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_9", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_WW2A1_9", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_IMUX47_L_9", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_SE4BEG3_9", + "INT_INTERFACE_SE4BEG3" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 0, + -5 + ], + "wire_pairs": [ + [ + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "BRAM_CASCOUT_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "BRAM_CASCOUT_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "BRAM_CASCOUT_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "BRAM_CASCOUT_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU8", + "BRAM_CASCOUT_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU10", + "BRAM_CASCOUT_ADDRARDADDRU10" + ], + [ + "BRAM_PMVBRAM_O_1", + "BRAM_PMVBRAM_O_2" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "BRAM_CASCOUT_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "BRAM_CASCOUT_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "BRAM_CASCOUT_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRAM_CASCOUT_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRAM_CASCOUT_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "BRAM_CASCOUT_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU13", + "BRAM_CASCOUT_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "BRAM_CASCOUT_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRAM_CASCOUT_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "BRAM_CASCOUT_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU2", + "BRAM_CASCOUT_ADDRARDADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRAM_CASCOUT_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "BRAM_CASCOUT_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "BRAM_CASCOUT_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "BRAM_CASCOUT_ADDRBWRADDRU8" + ], + [ + "BRAM_PMVBRAM_ODIV2", + "BRAM_PMVBRAM_ODIV2_1" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU5", + "BRAM_CASCOUT_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU12", + "BRAM_CASCOUT_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU0", + "BRAM_CASCOUT_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU6", + "BRAM_CASCOUT_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU11", + "BRAM_CASCOUT_ADDRARDADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU3", + "BRAM_CASCOUT_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "BRAM_CASCOUT_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "BRAM_CASCOUT_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU9", + "BRAM_CASCOUT_ADDRARDADDRU9" + ], + [ + "BRAM_PMVBRAM_O", + "BRAM_PMVBRAM_O_1" + ] + ], + "tile_types": [ + "BRAM_R", + "BRAM_R" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "CLK_PMV_FAN2_4", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_PMV_MONITOR_P_4", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_PMV_SE4C3_4", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_PMV_EE2A2_4", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_PMV_NE4BEG1_4", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_PMV_IMUX33_4", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_PMV_IMUX2_4", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_PMV_WR1END0_4", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_PMV_IMUX21_4", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_PMV_BYP0_4", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_PMV_SW4A1_4", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_PMV_EE4B3_4", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_PMV_IMUX29_4", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_PMV_SE4C0_4", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_PMV_WW4END0_4", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_PMV_IMUX0_4", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_PMV_SW4END3_4", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_PMV_EE4BEG0_4", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_PMV_EE2A3_4", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_PMV_NW4END0_4", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_PMV_IMUX43_4", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_PMV_EE4A1_4", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_PMV_NE2A3_4", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_PMV_EE4BEG2_4", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_PMV_WW4C3_4", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_PMV_ER1BEG2_4", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_PMV_ER1BEG0_4", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_PMV_WR1END3_4", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_PMV_SE2A3_4", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_PMV_EE4C2_4", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_PMV_EL1BEG3_4", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_PMV_FAN7_4", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_PMV_SW2A2_4", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_PMV_CLK0_4", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_PMV_NE4C0_4", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_PMV_NE4C1_4", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_PMV_LH4_4", + "INT_INTERFACE_LH4" + ], + [ + "CLK_PMV_EE4A3_4", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_PMV_EL1BEG1_4", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_PMV_LH5_4", + "INT_INTERFACE_LH5" + ], + [ + "CLK_PMV_IMUX8_4", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_PMV_NW4END3_4", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_PMV_IMUX32_4", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_PMV_IMUX13_4", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_PMV_IMUX44_4", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_PMV_IMUX45_4", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_PMV_SE4C2_4", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_PMV_EE4BEG1_4", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_PMV_BYP1_4", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_PMV_WL1END1_4", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_PMV_SW2A1_4", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_PMV_CLK1_4", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_PMV_SW2A0_4", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_PMV_WW2A1_4", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_PMV_IMUX25_4", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_PMV_IMUX3_4", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_PMV_IMUX26_4", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_PMV_ER1BEG3_4", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_PMV_NW2A2_4", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_PMV_NW4A1_4", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_PMV_IMUX39_4", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_PMV_WW2END0_4", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_PMV_EE2BEG3_4", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_PMV_FAN0_4", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_PMV_LH1_4", + "INT_INTERFACE_LH1" + ], + [ + "CLK_PMV_WW4C0_4", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_PMV_SE2A1_4", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_PMV_LH9_4", + "INT_INTERFACE_LH9" + ], + [ + "CLK_PMV_IMUX38_4", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_PMV_SE4C1_4", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_PMV_EE2A0_4", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_PMV_LH10_4", + "INT_INTERFACE_LH10" + ], + [ + "CLK_PMV_WW4END3_4", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_PMV_IMUX37_4", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_PMV_FAN6_4", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_PMV_BYP5_4", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_PMV_MONITOR_N_4", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_PMV_WL1END2_4", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_PMV_IMUX46_4", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_PMV_BYP2_4", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_PMV_IMUX10_4", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_PMV_IMUX19_4", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_PMV_EE2BEG0_4", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_PMV_EE4A2_4", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_PMV_NE4C2_4", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_PMV_FAN4_4", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_PMV_IMUX47_4", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_PMV_NW2A1_4", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_PMV_LH6_4", + "INT_INTERFACE_LH6" + ], + [ + "CLK_PMV_IMUX6_4", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_PMV_IMUX35_4", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_PMV_NW4A2_4", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_PMV_IMUX34_4", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_PMV_WW4A1_4", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_PMV_IMUX20_4", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_PMV_NE2A0_4", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_PMV_IMUX18_4", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_PMV_BYP4_4", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_PMV_WW4B3_4", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_PMV_WW2A2_4", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_PMV_LH11_4", + "INT_INTERFACE_LH11" + ], + [ + "CLK_PMV_SW4A0_4", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_PMV_IMUX24_4", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_PMV_SW2A3_4", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_PMV_WW2END1_4", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_PMV_IMUX31_4", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_PMV_EE4C0_4", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_PMV_WW2A3_4", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_PMV_WL1END3_4", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_PMV_NW2A0_4", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_PMV_IMUX11_4", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_PMV_WW4END1_4", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_PMV_IMUX12_4", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_PMV_IMUX14_4", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_PMV_EE4B0_4", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_PMV_IMUX30_4", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_PMV_SW4END1_4", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_PMV_EE4C3_4", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_PMV_NE4BEG0_4", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_PMV_FAN3_4", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_PMV_NW4A0_4", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_PMV_ER1BEG1_4", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_PMV_IMUX7_4", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_PMV_CTRL1_4", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_PMV_WL1END0_4", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_PMV_EE2BEG1_4", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_PMV_LH2_4", + "INT_INTERFACE_LH2" + ], + [ + "CLK_PMV_EE4B1_4", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_PMV_SW4A2_4", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_PMV_NW4A3_4", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_PMV_IMUX22_4", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_PMV_WW4C1_4", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_PMV_IMUX17_4", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_PMV_NE4BEG2_4", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_PMV_EL1BEG2_4", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_PMV_IMUX15_4", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_PMV_SW4END2_4", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_PMV_FAN5_4", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_PMV_NE2A1_4", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_PMV_SE4BEG1_4", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_PMV_WR1END1_4", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_PMV_NW4END2_4", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_PMV_IMUX1_4", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_PMV_LH7_4", + "INT_INTERFACE_LH7" + ], + [ + "CLK_PMV_WW2END3_4", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_PMV_IMUX27_4", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_PMV_NW4END1_4", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_PMV_LH8_4", + "INT_INTERFACE_LH8" + ], + [ + "CLK_PMV_WW4C2_4", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_PMV_EL1BEG0_4", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_PMV_IMUX40_4", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_PMV_NW2A3_4", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_PMV_SW4END0_4", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_PMV_SE4BEG2_4", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_PMV_EE2BEG2_4", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_PMV_IMUX36_4", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_PMV_IMUX16_4", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_PMV_BYP7_4", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_PMV_SE4BEG3_4", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_PMV_WW4B2_4", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_PMV_IMUX4_4", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_PMV_FAN1_4", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_PMV_WR1END2_4", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_PMV_EE4C1_4", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_PMV_IMUX9_4", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_PMV_LH12_4", + "INT_INTERFACE_LH12" + ], + [ + "CLK_PMV_WW4A3_4", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_PMV_BYP6_4", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_PMV_EE2A1_4", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_PMV_BYP3_4", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_PMV_SE4BEG0_4", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_PMV_IMUX5_4", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_PMV_WW4END2_4", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_PMV_WW2END2_4", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_PMV_SW4A3_4", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_PMV_SE2A2_4", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_PMV_IMUX23_4", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_PMV_WW2A0_4", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_PMV_IMUX28_4", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_PMV_EE4B2_4", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_PMV_SE2A0_4", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_PMV_LH3_4", + "INT_INTERFACE_LH3" + ], + [ + "CLK_PMV_WW4A2_4", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_PMV_WW4A0_4", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_PMV_EE4BEG3_4", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_PMV_WW4B0_4", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_PMV_NE4BEG3_4", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_PMV_WW4B1_4", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_PMV_IMUX42_4", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_PMV_CTRL0_4", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_PMV_NE2A2_4", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_PMV_NE4C3_4", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_PMV_EE4A0_4", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_PMV_IMUX41_4", + "INT_INTERFACE_IMUX41" + ] + ], + "tile_types": [ + "CLK_PMV", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "T_TERM_UTURN_INT_SL1END3_SLOW", + "NR1BEG0" + ], + [ + "T_TERM_UTURN_INT_SS6END1", + "NN6E2" + ], + [ + "T_TERM_UTURN_INT_LV_L16", + "LV_L1" + ], + [ + "T_TERM_UTURN_INT_WR1END_S1_0", + "WL1END3" + ], + [ + "T_TERM_UTURN_INT_SS6D0", + "SS6D0" + ], + [ + "T_TERM_UTURN_INT_LVB_L4", + "LVB_L4" + ], + [ + "T_TERM_UTURN_INT_SS6B1", + "NN6A2" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", + "BYP_BOUNCE7" + ], + [ + "T_TERM_UTURN_INT_SS2A2", + "NN2BEG1" + ], + [ + "T_TERM_UTURN_INT_SW6B0", + "NW6A3" + ], + [ + "T_TERM_UTURN_INT_SS6B2", + "NN6A1" + ], + [ + "T_TERM_UTURN_INT_SE6E0", + "NE6D3" + ], + [ + "T_TERM_UTURN_INT_SS2END0", + "NN2A3" + ], + [ + "T_TERM_UTURN_INT_SS6A2", + "SS6A2" + ], + [ + "T_TERM_UTURN_INT_SS6C0", + "SS6C0" + ], + [ + "T_TERM_UTURN_INT_SR1END1_SLOW", + "SR1END1" + ], + [ + "T_TERM_UTURN_INT_SS6B2", + "SS6B2" + ], + [ + "T_TERM_UTURN_INT_SS2END3", + "SS2END3" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", + "FAN_BOUNCE_S3_0" + ], + [ + "T_TERM_UTURN_INT_LV_L7", + "LV_L10" + ], + [ + "T_TERM_UTURN_INT_SW6C0", + "SW6C0" + ], + [ + "T_TERM_UTURN_INT_SE6B3", + "SE6B3" + ], + [ + "T_TERM_UTURN_INT_SS6A3", + "NN6BEG0" + ], + [ + "T_TERM_UTURN_INT_ER1BEG_S0", + "ER1BEG_S0" + ], + [ + "T_TERM_UTURN_INT_SE6C1", + "NE6B2" + ], + [ + "T_TERM_UTURN_INT_SS6A1", + "NN6BEG2" + ], + [ + "T_TERM_UTURN_INT_SS6C0", + "NN6B3" + ], + [ + "T_TERM_UTURN_INT_SW6B1", + "SW6B1" + ], + [ + "T_TERM_UTURN_INT_SE2A2", + "NE2BEG1" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", + "BYP_BOUNCE2" + ], + [ + "T_TERM_UTURN_INT_SW6E3", + "NW6D0" + ], + [ + "T_TERM_UTURN_INT_SW6C0", + "NW6B3" + ], + [ + "T_TERM_UTURN_INT_LVB_L2", + "LVB_L2" + ], + [ + "T_TERM_UTURN_INT_SW6E2", + "SW6E2" + ], + [ + "T_TERM_UTURN_INT_SS6D3", + "NN6C0" + ], + [ + "T_TERM_UTURN_INT_SS6B0", + "NN6A3" + ], + [ + "T_TERM_UTURN_INT_SW6C1", + "NW6B2" + ], + [ + "T_TERM_UTURN_INT_SS6E3", + "NN6D0" + ], + [ + "T_TERM_UTURN_INT_SE6D2", + "NE6C1" + ], + [ + "T_TERM_UTURN_INT_SW6B1", + "NW6A2" + ], + [ + "T_TERM_UTURN_INT_SW2A2", + "SW2A2" + ], + [ + "T_TERM_UTURN_INT_LVB_L3", + "LVB_L3" + ], + [ + "T_TERM_UTURN_INT_SE6D1", + "SE6D1" + ], + [ + "T_TERM_UTURN_INT_SW6C3", + "SW6C3" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", + "FAN_BOUNCE_S3_4" + ], + [ + "T_TERM_UTURN_INT_SS6B1", + "SS6B1" + ], + [ + "T_TERM_UTURN_INT_LVB_L1", + "LVB_L10" + ], + [ + "T_TERM_UTURN_INT_SS6B0", + "SS6B0" + ], + [ + "T_TERM_UTURN_INT_SW6D0", + "NW6C3" + ], + [ + "T_TERM_UTURN_INT_SS6E3", + "SS6E3" + ], + [ + "T_TERM_UTURN_INT_SW6E3", + "SW6E3" + ], + [ + "T_TERM_UTURN_INT_SS6END3", + "NN6E0" + ], + [ + "T_TERM_UTURN_INT_SR1END3_SLOW", + "NL1BEG0" + ], + [ + "T_TERM_UTURN_INT_SW6E2", + "NW6D1" + ], + [ + "T_TERM_UTURN_INT_SL1END1_SLOW", + "NR1BEG2" + ], + [ + "T_TERM_UTURN_INT_SE2A1", + "NE2BEG2" + ], + [ + "T_TERM_UTURN_INT_LVB_L5", + "LVB_L6" + ], + [ + "T_TERM_UTURN_INT_LV_L9", + "LV_L9" + ], + [ + "T_TERM_UTURN_INT_SE6B1", + "NE6A2" + ], + [ + "T_TERM_UTURN_INT_LV_L2", + "LV_L2" + ], + [ + "T_TERM_UTURN_INT_SE6C3", + "SE6C3" + ], + [ + "T_TERM_UTURN_INT_SE6D0", + "NE6C3" + ], + [ + "T_TERM_UTURN_INT_LV_L3", + "LV_L14" + ], + [ + "T_TERM_UTURN_INT_SW6E0", + "SW6E0" + ], + [ + "T_TERM_UTURN_INT_SW6D2", + "SW6D2" + ], + [ + "T_TERM_UTURN_INT_LV_L4", + "LV_L4" + ], + [ + "T_TERM_UTURN_INT_LV_L6", + "LV_L11" + ], + [ + "T_TERM_UTURN_INT_SS6A0", + "NN6BEG3" + ], + [ + "T_TERM_UTURN_INT_SS6C3", + "SS6C3" + ], + [ + "T_TERM_UTURN_INT_SW6B2", + "NW6A1" + ], + [ + "T_TERM_UTURN_INT_SL1END1_SLOW", + "SL1END1" + ], + [ + "T_TERM_UTURN_INT_LVB_L2", + "LVB_L9" + ], + [ + "T_TERM_UTURN_INT_SW6D3", + "SW6D3" + ], + [ + "T_TERM_UTURN_INT_SE6B0", + "NE6A3" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", + "FAN_BOUNCE_S3_2" + ], + [ + "T_TERM_UTURN_INT_SW6E0", + "NW6D3" + ], + [ + "T_TERM_UTURN_INT_SS6C2", + "NN6B1" + ], + [ + "T_TERM_UTURN_INT_SW2A3", + "NW2BEG0" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", + "FAN_BOUNCE_S3_6" + ], + [ + "T_TERM_UTURN_INT_LV_L17", + "LV_L0" + ], + [ + "T_TERM_UTURN_INT_SS6E0", + "NN6D3" + ], + [ + "T_TERM_UTURN_INT_SW6D1", + "NW6C2" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", + "BYP_BOUNCE6" + ], + [ + "T_TERM_UTURN_INT_LV_L4", + "LV_L13" + ], + [ + "T_TERM_UTURN_INT_SW6D1", + "SW6D1" + ], + [ + "T_TERM_UTURN_INT_SS2A0", + "NN2BEG3" + ], + [ + "T_TERM_UTURN_INT_SE2A2", + "SE2A2" + ], + [ + "T_TERM_UTURN_INT_SE6E0", + "SE6E0" + ], + [ + "T_TERM_UTURN_INT_SW6C2", + "SW6C2" + ], + [ + "T_TERM_UTURN_INT_LV_L5", + "LV_L12" + ], + [ + "T_TERM_UTURN_INT_SW2A1", + "SW2A1" + ], + [ + "T_TERM_UTURN_INT_SS6END0", + "NN6E3" + ], + [ + "T_TERM_UTURN_INT_SE6B2", + "NE6A1" + ], + [ + "T_TERM_UTURN_INT_LVB_L4", + "LVB_L7" + ], + [ + "T_TERM_UTURN_INT_SS6D2", + "NN6C1" + ], + [ + "T_TERM_UTURN_INT_SL1END0_SLOW", + "SL1END0" + ], + [ + "T_TERM_UTURN_INT_SL1END0_SLOW", + "NR1BEG3" + ], + [ + "T_TERM_UTURN_INT_SS6D3", + "SS6D3" + ], + [ + "T_TERM_UTURN_INT_LV_L5", + "LV_L5" + ], + [ + "T_TERM_UTURN_INT_SW2A3", + "SW2A3" + ], + [ + "T_TERM_UTURN_INT_SW2A0", + "NW2BEG3" + ], + [ + "T_TERM_UTURN_INT_SS6A0", + "SS6A0" + ], + [ + "T_TERM_UTURN_INT_SS2END0", + "SS2END0" + ], + [ + "T_TERM_UTURN_INT_SS6E0", + "SS6E0" + ], + [ + "T_TERM_UTURN_INT_SS2END3", + "NN2A0" + ], + [ + "T_TERM_UTURN_INT_LVB_L5", + "LVB_L5" + ], + [ + "T_TERM_UTURN_INT_LVB_L0", + "LVB_L0" + ], + [ + "T_TERM_UTURN_INT_LV_L7", + "LV_L7" + ], + [ + "T_TERM_UTURN_INT_SS2A3", + "NN2BEG0" + ], + [ + "T_TERM_UTURN_INT_SE6D1", + "NE6C2" + ], + [ + "T_TERM_UTURN_INT_SS6END2", + "SS6END2" + ], + [ + "T_TERM_UTURN_INT_SS6END3", + "SS6END3" + ], + [ + "T_TERM_UTURN_INT_SS6A1", + "SS6A1" + ], + [ + "T_TERM_UTURN_INT_SS6A2", + "NN6BEG1" + ], + [ + "T_TERM_UTURN_INT_SE2A0", + "SE2A0" + ], + [ + "T_TERM_UTURN_INT_SW2A2", + "NW2BEG1" + ], + [ + "T_TERM_UTURN_INT_SE6C2", + "NE6B1" + ], + [ + "T_TERM_UTURN_INT_SS2END2", + "SS2END2" + ], + [ + "T_TERM_UTURN_INT_WR1BEG_S0", + "WL1BEG3" + ], + [ + "T_TERM_UTURN_INT_SS6B3", + "NN6A0" + ], + [ + "T_TERM_UTURN_INT_LV_L16", + "LV_L16" + ], + [ + "T_TERM_UTURN_INT_SS6D1", + "SS6D1" + ], + [ + "T_TERM_UTURN_INT_SR1END1_SLOW", + "NL1BEG2" + ], + [ + "T_TERM_UTURN_INT_ER1END3", + "EL1END_S3_0" + ], + [ + "T_TERM_UTURN_INT_SE6C3", + "NE6B0" + ], + [ + "T_TERM_UTURN_INT_SE6B0", + "SE6B0" + ], + [ + "T_TERM_UTURN_INT_LVB_L1", + "LVB_L1" + ], + [ + "T_TERM_UTURN_INT_ER1END3", + "ER1END3" + ], + [ + "T_TERM_UTURN_INT_SS2A3", + "SS2A3" + ], + [ + "T_TERM_UTURN_INT_LVB_L3", + "LVB_L8" + ], + [ + "T_TERM_UTURN_INT_SE6E3", + "NE6D0" + ], + [ + "T_TERM_UTURN_INT_SW6D3", + "NW6C0" + ], + [ + "T_TERM_UTURN_INT_SS6C2", + "SS6C2" + ], + [ + "T_TERM_UTURN_INT_SS6B3", + "SS6B3" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", + "BYP_BOUNCE3" + ], + [ + "T_TERM_UTURN_INT_SS6C1", + "SS6C1" + ], + [ + "T_TERM_UTURN_INT_SE6B2", + "SE6B2" + ], + [ + "T_TERM_UTURN_INT_SE2A0", + "NE2BEG3" + ], + [ + "T_TERM_UTURN_INT_LV_L2", + "LV_L15" + ], + [ + "T_TERM_UTURN_INT_SS6E1", + "NN6D2" + ], + [ + "T_TERM_UTURN_INT_SE2A3", + "NE2BEG0" + ], + [ + "T_TERM_UTURN_INT_SE6B3", + "NE6A0" + ], + [ + "T_TERM_UTURN_INT_SS6END1", + "SS6END1" + ], + [ + "T_TERM_UTURN_INT_SE2A3", + "SE2A3" + ], + [ + "T_TERM_UTURN_INT_SS2A1", + "NN2BEG2" + ], + [ + "T_TERM_UTURN_INT_LVB_L0", + "LVB_L11" + ], + [ + "T_TERM_UTURN_INT_SW6C3", + "NW6B0" + ], + [ + "T_TERM_UTURN_INT_SS6E2", + "NN6D1" + ], + [ + "T_TERM_UTURN_INT_SW6E1", + "NW6D2" + ], + [ + "T_TERM_UTURN_INT_ER1BEG_S0", + "EL1BEG3" + ], + [ + "T_TERM_UTURN_INT_SW6E1", + "SW6E1" + ], + [ + "T_TERM_UTURN_INT_SS6C1", + "NN6B2" + ], + [ + "T_TERM_UTURN_INT_SS6C3", + "NN6B0" + ], + [ + "T_TERM_UTURN_INT_SS2END1", + "NN2A2" + ], + [ + "T_TERM_UTURN_INT_SW6B3", + "NW6A0" + ], + [ + "T_TERM_UTURN_INT_SE6D2", + "SE6D2" + ], + [ + "T_TERM_UTURN_INT_LV_L9", + "LV_L8" + ], + [ + "T_TERM_UTURN_INT_SL1END2_SLOW", + "NR1BEG1" + ], + [ + "T_TERM_UTURN_INT_SE6C0", + "SE6C0" + ], + [ + "T_TERM_UTURN_INT_SE2A1", + "SE2A1" + ], + [ + "T_TERM_UTURN_INT_SE6D3", + "NE6C0" + ], + [ + "T_TERM_UTURN_INT_SS6E1", + "SS6E1" + ], + [ + "T_TERM_UTURN_INT_SE6B1", + "SE6B1" + ], + [ + "T_TERM_UTURN_INT_SE6E2", + "SE6E2" + ], + [ + "T_TERM_UTURN_INT_SW6B0", + "SW6B0" + ], + [ + "T_TERM_UTURN_INT_SS2A2", + "SS2A2" + ], + [ + "T_TERM_UTURN_INT_SS2END2", + "NN2A1" + ], + [ + "T_TERM_UTURN_INT_SS6D2", + "SS6D2" + ], + [ + "T_TERM_UTURN_INT_SR1END2_SLOW", + "SR1END2" + ], + [ + "T_TERM_UTURN_INT_SE6C2", + "SE6C2" + ], + [ + "T_TERM_UTURN_INT_WR1END_S1_0", + "WR1END_S1_0" + ], + [ + "T_TERM_UTURN_INT_SS6D1", + "NN6C2" + ], + [ + "T_TERM_UTURN_INT_SE6C0", + "NE6B3" + ], + [ + "T_TERM_UTURN_INT_LV_L17", + "LV_L17" + ], + [ + "T_TERM_UTURN_INT_SE6C1", + "SE6C1" + ], + [ + "T_TERM_UTURN_INT_SW6D2", + "NW6C1" + ], + [ + "T_TERM_UTURN_INT_SE6E2", + "NE6D1" + ], + [ + "T_TERM_UTURN_INT_WR1BEG_S0", + "WR1BEG_S0" + ], + [ + "T_TERM_UTURN_INT_SS6A3", + "SS6A3" + ], + [ + "T_TERM_UTURN_INT_SS2A0", + "SS2A0" + ], + [ + "T_TERM_UTURN_INT_SR1END3_SLOW", + "SR1END3" + ], + [ + "T_TERM_UTURN_INT_LV_L3", + "LV_L3" + ], + [ + "T_TERM_UTURN_INT_SW6D0", + "SW6D0" + ], + [ + "T_TERM_UTURN_INT_SR1END2_SLOW", + "NL1BEG1" + ], + [ + "T_TERM_UTURN_INT_SL1END2_SLOW", + "SL1END2" + ], + [ + "T_TERM_UTURN_INT_SE6E1", + "NE6D2" + ], + [ + "T_TERM_UTURN_INT_SS6END2", + "NN6E1" + ], + [ + "T_TERM_UTURN_INT_SE6E3", + "SE6E3" + ], + [ + "T_TERM_UTURN_INT_SS6D0", + "NN6C3" + ], + [ + "T_TERM_UTURN_INT_SS2END1", + "SS2END1" + ], + [ + "T_TERM_UTURN_INT_SS6END0", + "SS6END0" + ], + [ + "T_TERM_UTURN_INT_SW6C1", + "SW6C1" + ], + [ + "T_TERM_UTURN_INT_SW6B3", + "SW6B3" + ], + [ + "T_TERM_UTURN_INT_SE6D0", + "SE6D0" + ], + [ + "T_TERM_UTURN_INT_SW2A0", + "SW2A0" + ], + [ + "T_TERM_UTURN_INT_SW2A1", + "NW2BEG2" + ], + [ + "T_TERM_UTURN_INT_SS6E2", + "SS6E2" + ], + [ + "T_TERM_UTURN_INT_SW6C2", + "NW6B1" + ], + [ + "T_TERM_UTURN_INT_SL1END3_SLOW", + "SL1END3" + ], + [ + "T_TERM_UTURN_INT_SW6B2", + "SW6B2" + ], + [ + "T_TERM_UTURN_INT_SE6D3", + "SE6D3" + ], + [ + "T_TERM_UTURN_INT_SE6E1", + "SE6E1" + ], + [ + "T_TERM_UTURN_INT_SS2A1", + "SS2A1" + ], + [ + "T_TERM_UTURN_INT_LV_L6", + "LV_L6" + ] + ], + "tile_types": [ + "BRKH_TERM_INT", + "INT_L" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE2A0_10", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WL1END0_10", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_EE4BEG1_10", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_WL1END3_10", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4C0_10", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_ER1BEG1_10", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SE2A2_10", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4C2_10", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_EE4B3_10", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NW2A3_10", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_EE2A3_10", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_EE4BEG3_10", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WW2A0_10", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_NE2A2_10", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE4B0_10", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WW2END2_10", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_WW2A1_10", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_NE4C1_10", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_LH4_10", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SW4A1_10", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_EE4A3_10", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE2BEG0_10", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_SE2A1_10", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW2A3_10", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_NW4A0_10", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_WR1END0_10", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_SE4C0_10", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_LH5_10", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_WW4B0_10", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_WW4END3_10", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WL1END1_10", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_EE4A0_10", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_WW4A3_10", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NE4C3_10", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_SW2A3_10", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NW4A3_10", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_LH11_10", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW2END0_10", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NE4BEG2_10", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_SE4BEG0_10", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SW4A0_10", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE4B1_10", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_SE4BEG1_10", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_EE4C1_10", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_NE4BEG1_10", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_NW4END0_10", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_WW4END1_10", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_WW4END0_10", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WW4A2_10", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_NW4END3_10", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW4A1_10", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_LH12_10", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_LH8_10", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_EE4B2_10", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE2BEG1_10", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NW4END2_10", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_ER1BEG3_10", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_SE4C1_10", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_SW4A2_10", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_LH7_10", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4C0_10", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_SW2A2_10", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_LH1_10", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_LH2_10", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_WW2A2_10", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4BEG3_10", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_ER1BEG0_10", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NW2A0_10", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_SE4C2_10", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_SE4BEG3_10", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_SW2A0_10", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_ER1BEG2_10", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_EE2BEG2_10", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_LH9_10", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_EE4BEG2_10", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SW4A3_10", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_NW4A1_10", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_NW4END1_10", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NE4C2_10", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE4A2_10", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4C3_10", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW2END1_10", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE4A1_10", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_WW2END3_10", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_SW4END3_10", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_WW4C2_10", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_WW4A0_10", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_NE2A0_10", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_LH10_10", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_NW4A2_10", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_LH6_10", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_EL1BEG3_10", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_EL1BEG0_10", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_SW4END0_10", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EE2A1_10", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_EL1BEG2_10", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_SW2A1_10", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_WW4C1_10", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_WR1END2_10", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_NE2A1_10", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NE2A3_10", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_EE4BEG0_10", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NW2A2_10", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_SW4END2_10", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_EL1BEG1_10", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW4END2_10", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_SE4BEG2_10", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW4B3_10", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_WW4B2_10", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_SE4C3_10", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WW4B1_10", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_NW2A1_10", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SE2A0_10", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_WR1END1_10", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WW4C3_10", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_LH3_10", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SE2A3_10", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_WR1END3_10", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_NE4C0_10", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_EE2A2_10", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WL1END2_10", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SW4END1_10", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EE2BEG3_10", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NE4BEG0_10", + "INT_FEEDTHRU_2_NE4BEG0" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX23_10", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_BYP6_10", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_CLK0_10", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_LOGIC_OUTS_B19_10", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX7_10", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX12_10", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX28_10", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX18_10", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_FAN0_10", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_FAN6_10", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX31_10", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B8_10", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_BYP2_10", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX36_10", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX42_10", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX45_10", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX22_10", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B2_10", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_LOGIC_OUTS_B0_10", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX21_10", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX14_10", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX9_10", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX3_10", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_LOGIC_OUTS_B17_10", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX33_10", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_LOGIC_OUTS_B10_10", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX17_10", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_LOGIC_OUTS_B12_10", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX15_10", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX24_10", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B7_10", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_IMUX44_10", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_FAN3_10", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_BYP3_10", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX8_10", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_BYP7_10", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B23_10", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX38_10", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX19_10", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_BYP1_10", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX29_10", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX10_10", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_FAN7_10", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B16_10", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX46_10", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_LOGIC_OUTS_B15_10", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX0_10", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX11_10", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX4_10", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_BYP0_10", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX26_10", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX40_10", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_FAN2_10", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX43_10", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_CTRL0_10", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX5_10", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX41_10", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX13_10", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_FAN5_10", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_FAN4_10", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_LOGIC_OUTS_B18_10", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX27_10", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_BYP4_10", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_CTRL1_10", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX1_10", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX30_10", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_LOGIC_OUTS_B4_10", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B20_10", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX20_10", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX47_10", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX2_10", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_LOGIC_OUTS_B9_10", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_LOGIC_OUTS_B5_10", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_FAN1_10", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX35_10", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_CLK1_10", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX16_10", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_LOGIC_OUTS_B14_10", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_LOGIC_OUTS_B1_10", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX37_10", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_LOGIC_OUTS_B13_10", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B22_10", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX32_10", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX25_10", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_BYP5_10", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B3_10", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX34_10", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_LOGIC_OUTS_B6_10", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX6_10", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX39_10", + "VBRK_EXT_IMUX39" + ] + ], + "tile_types": [ + "GTX_CHANNEL_3", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_INT_PERFCLK3" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CK_IN2" + ] + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_L" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_NE4BEG1_10", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_SW4END1_10", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_EE4C3_10", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_SW4END3_10", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_L_IMUX22_10", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_SE4BEG1_10", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_SW4END2_10", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_LH12_10", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_WW4C0_10", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_10", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "CMT_FIFO_NW4A3_10", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_L_IMUX21_10", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_SW4END0_10", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_WW4B0_10", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_EE4BEG1_10", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX16_10", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_WR1END2_10", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_NW2A1_10", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_WW2A1_10", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_NE4C0_10", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_SE2A2_10", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_L_BYP6_10", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_NW2A3_10", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_10", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_10", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "CMT_FIFO_L_IMUX38_10", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_LH7_10", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_NE4BEG0_10", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_WW4END0_10", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_IMUX7_10", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_NW4A2_10", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_WW4C1_10", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_L_IMUX18_10", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_ER1BEG0_10", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_10", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "CMT_FIFO_NW4A0_10", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_10", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CMT_FIFO_EE4BEG3_10", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_SW4A2_10", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_WR1END1_10", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_WW4END1_10", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_WL1END3_10", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_NE4BEG2_10", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_EL1BEG0_10", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_EE2BEG1_10", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_WW4C3_10", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_WW2END2_10", + "INT_INTERFACE_WW2END2" + ], + [ + "FIFO_DQS_IOTOPHASER_5", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "CMT_FIFO_L_BYP4_10", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_L_IMUX13_10", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_10", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CMT_FIFO_EE2A0_10", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_FAN1_10", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_L_IMUX33_10", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_WW4A2_10", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_SE2A0_10", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_NW4END2_10", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_10", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "CMT_FIFO_EE4C2_10", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_NE2A1_10", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_10", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CMT_FIFO_LH6_10", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_L_FAN5_10", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_SW2A0_10", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_L_IMUX8_10", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_IMUX30_10", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_NE2A3_10", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_NE2A2_10", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_NE4C3_10", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_NE2A0_10", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_EL1BEG2_10", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_WW4B1_10", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_WW4B3_10", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_EE2A1_10", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_L_FAN4_10", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_ER1BEG1_10", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_LH2_10", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_L_IMUX34_10", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_SW4A3_10", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_WW4C2_10", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_IMUX41_10", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_FAN3_10", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_SE4C1_10", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_EL1BEG3_10", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_EE4B3_10", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_EE2A2_10", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_L_CTRL0_10", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_10", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CMT_FIFO_WW4END2_10", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_L_IMUX19_10", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_EL1BEG1_10", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_WW4B2_10", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_L_IMUX44_10", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_CLK0_10", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_WW4END3_10", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_L_IMUX37_10", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_SW2A1_10", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_L_IMUX43_10", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_WW4A3_10", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_EE2BEG3_10", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_NW4A1_10", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_WR1END3_10", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_L_IMUX39_10", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_WW2END3_10", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_L_BYP5_10", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_10", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "CMT_FIFO_L_IMUX3_10", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_10", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "CMT_FIFO_LH9_10", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_L_IMUX32_10", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_NW2A0_10", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_WW2END0_10", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_L_IMUX17_10", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_L_IMUX25_10", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_10", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CMT_FIFO_L_IMUX5_10", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_SE4C0_10", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_L_IMUX4_10", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_L_IMUX46_10", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_L_IMUX15_10", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_IMUX14_10", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_SE4BEG0_10", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_L_FAN7_10", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_WL1END2_10", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_EE4C0_10", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_NW4END0_10", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_SE4C2_10", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_L_BYP7_10", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_EE4B2_10", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_EE4BEG2_10", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_L_BYP0_10", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_WW4A0_10", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_L_IMUX47_10", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_L_IMUX11_10", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_EE2BEG2_10", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_ER1BEG2_10", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_IMUX45_10", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_L_IMUX36_10", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_ER1BEG3_10", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_WW2A0_10", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_NE4BEG3_10", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_WW2A2_10", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_NW2A2_10", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_WL1END0_10", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_10", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_10", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_10", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "CMT_FIFO_L_FAN0_10", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_L_IMUX10_10", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_L_IMUX12_10", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_SE4BEG2_10", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_10", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CMT_FIFO_EE4BEG0_10", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_10", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CMT_FIFO_EE4A0_10", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_L_IMUX2_10", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_L_IMUX42_10", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_EE4C1_10", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_L_IMUX31_10", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_WR1END0_10", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_SE2A1_10", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_SE4C3_10", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_FAN6_10", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_LH10_10", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_SW4A1_10", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_NW4END3_10", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_NE4C2_10", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_L_CTRL1_10", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_EE4A1_10", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_WW2A3_10", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_LH3_10", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_L_IMUX28_10", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_L_IMUX24_10", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_L_BYP3_10", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_SW4A0_10", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_L_BYP2_10", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_MONITOR_P_10", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CMT_FIFO_L_IMUX26_10", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_CLK1_10", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_SW2A2_10", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_MONITOR_N_10", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CMT_FIFO_L_IMUX35_10", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_NE4C1_10", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_L_FAN2_10", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_WW2END1_10", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_EE4A2_10", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_EE4A3_10", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_10", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "CMT_FIFO_L_IMUX40_10", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_NW4END1_10", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_10", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_10", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CMT_FIFO_L_IMUX29_10", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_LH1_10", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_EE2A3_10", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_10", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "CMT_FIFO_L_IMUX1_10", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_IMUX27_10", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_L_IMUX9_10", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_WL1END1_10", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_L_IMUX6_10", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_LH4_10", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_SW2A3_10", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_10", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "CMT_FIFO_SE4BEG3_10", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_LH11_10", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_LH8_10", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_10", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CMT_FIFO_L_IMUX23_10", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_10", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CMT_FIFO_EE2BEG0_10", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_EE4B1_10", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_LH5_10", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_L_IMUX0_10", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_SE2A3_10", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_L_IMUX20_10", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_L_BYP1_10", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_EE4B0_10", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_WW4A1_10", + "INT_INTERFACE_WW4A1" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4C1_15", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_LH12_15", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_NW4A0_15", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_NW2A1_15", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_WW4C1_15", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_EE2A3_15", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NE4C1_15", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW2END1_15", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_WW4A2_15", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE4A2_15", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_WR1END3_15", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_ER1BEG3_15", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW2A2_15", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NW2A2_15", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_EL1BEG2_15", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_LH2_15", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_SE2A0_15", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_WR1END1_15", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_NE2A0_15", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_LH9_15", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_SE2A1_15", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_EE2BEG3_15", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NW4END3_15", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_SW2A2_15", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_EL1BEG1_15", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SW2A0_15", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WW2END2_15", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_EE4C0_15", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_SW4END1_15", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_WW4B0_15", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_NW2A0_15", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WW4END3_15", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_EE4A0_15", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4BEG2_15", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_NW4END0_15", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_EE4B3_15", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SW4END3_15", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_EE4C2_15", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NE4BEG0_15", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_SE4C0_15", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_WW4C3_15", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4A1_15", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_WW4B1_15", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_EE4B2_15", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_WL1END1_15", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_LH3_15", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_LH1_15", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_SW4END0_15", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EE2A1_15", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_NW4A1_15", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SE4BEG0_15", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SW4END2_15", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_NW4A3_15", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WW4END2_15", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_SE4BEG1_15", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_WW4A3_15", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_WW4END1_15", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_NE4BEG1_15", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WR1END0_15", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH4_15", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE4A1_15", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NE2A2_15", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE4BEG1_15", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_WW4B2_15", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE2BEG1_15", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_WW4B3_15", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_EE2A2_15", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_EE2BEG2_15", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW2A1_15", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WW2END0_15", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_SE4BEG3_15", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_LH7_15", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4END0_15", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WW4A0_15", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE4C3_15", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_NE4C0_15", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_SW4A3_15", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_SE2A3_15", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_LH6_15", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_SW4A0_15", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_NE2A1_15", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_SE4C1_15", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_SE4C3_15", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_SE4BEG2_15", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW2END3_15", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_LH10_15", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WL1END3_15", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_NE4C3_15", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_SW2A1_15", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_WW2A0_15", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WL1END0_15", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_WW4C2_15", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_ER1BEG2_15", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_NE2A3_15", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_NE4BEG3_15", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG0_15", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE4B1_15", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_LH11_15", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_ER1BEG0_15", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NW4END1_15", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NE4BEG2_15", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_SW4A1_15", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_SW2A3_15", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NW4A2_15", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_EE4B0_15", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH5_15", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_LH8_15", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_SE4C2_15", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_WL1END2_15", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WW2A3_15", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_EL1BEG3_15", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_EE4BEG0_15", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE2BEG0_15", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_NW4END2_15", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WR1END2_15", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_SW4A2_15", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_WW4C0_15", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_ER1BEG1_15", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_EE4BEG3_15", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_EE2A0_15", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_SE2A2_15", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_NW2A3_15", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE4C2_15", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE4A3_15", + "INT_FEEDTHRU_2_EE4A3" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + 9 + ], + "wire_pairs": [ + [ + "PCIE_SW2A1_1", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_1", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_WW4A1_1", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_SE4BEG2_1", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_IMUX31_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_BYP5_R_1", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_LH10_1", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_SE2A3_1", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_WW4A2_1", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_1", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_IMUX13_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_NE4BEG3_1", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_EE2A1_1", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_WW2END0_1", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_LH2_1", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_WL1END0_1", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_LH1_1", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_NW4A0_1", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_NE2A0_1", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_WW4A0_1", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_NE2A1_1", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_EE4A3_1", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_SW4A3_1", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_WW4C1_1", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_IMUX15_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_EE4BEG3_1", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_1", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_NE4BEG2_1", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_SW4END2_1", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_EE2BEG0_1", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_1", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_1", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_LH3_1", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_BYP2_R_1", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_SW4A1_1", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_WW4END2_1", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_SW2A3_1", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_1", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_IMUX43_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_IMUX3_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_NW4END1_1", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_EE2BEG3_1", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_CTRL1_R_1", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_EE4B0_1", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_NW4A2_1", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_IMUX1_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_IMUX0_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_SE4C3_1", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_ER1BEG0_1", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_IMUX26_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_EL1BEG3_1", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_IMUX2_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_IMUX46_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_WW4END1_1", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_IMUX17_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_WW2END2_1", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_EE4C2_1", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_EE4B2_1", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_ER1BEG2_1", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_NW2A1_1", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_IMUX42_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_IMUX23_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_SW4END3_1", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_WR1END0_1", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_IMUX40_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_1", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_NW4END2_1", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_BYP4_R_1", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_FAN2_R_1", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_LH11_1", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_CTRL0_R_1", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_LH7_1", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_SW4A2_1", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_WW4C2_1", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_SW4END1_1", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_BYP1_R_1", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_1", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_FAN4_R_1", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_ER1BEG1_1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_IMUX33_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_IMUX32_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_WR1END1_1", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_1", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_1", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_NW2A3_1", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_IMUX30_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_EE4BEG2_1", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_EE4A0_1", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_NE4BEG0_1", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_WW4B2_1", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_FAN7_R_1", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_1", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_1", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_NW4A3_1", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_1", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_IMUX10_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_IMUX44_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_NW2A2_1", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_IMUX5_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_EE4C3_1", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_WW4B1_1", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_IMUX4_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_1", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_LH8_1", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_IMUX11_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_1", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_WW4C3_1", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_EE2BEG2_1", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_IMUX29_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_SE2A0_1", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_WW4END0_1", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_1", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_NW4END3_1", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_IMUX27_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_SE4BEG3_1", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_WW4B0_1", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_NE4C3_1", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_1", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_ER1BEG3_1", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_1", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_WW2END3_1", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_LH9_1", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_EE4BEG1_1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_IMUX8_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_EE4A1_1", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_SE4C1_1", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_SW4END0_1", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_WR1END2_1", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_FAN3_R_1", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX18_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_SE2A2_1", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_WW4END3_1", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_IMUX37_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_EL1BEG1_1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_FAN1_R_1", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_IMUX21_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_IMUX35_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_SW4A0_1", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_SW2A0_1", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_EL1BEG2_1", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_1", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_LH12_1", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_MONITOR_N_1", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_NE2A2_1", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_EE2BEG1_1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX34_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_1", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_IMUX9_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_NE4C1_1", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_1", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_WL1END2_1", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_SW2A2_1", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_EE4A2_1", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_EE4BEG0_1", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_IMUX22_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_NW2A0_1", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_WW4C0_1", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_SE4C2_1", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_EE2A3_1", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_IMUX41_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_WW2A0_1", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_BYP3_R_1", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_IMUX36_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_EE4B3_1", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_MONITOR_P_1", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_WW2END1_1", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_SE2A1_1", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_IMUX38_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_CLK0_R_1", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_WW4A3_1", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_IMUX39_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_LH6_1", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_IMUX45_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_WL1END3_1", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_FAN5_R_1", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_IMUX14_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_BYP6_R_1", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_FAN0_R_1", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_1", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_LH5_1", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_IMUX16_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_IMUX20_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_SE4C0_1", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_BYP7_R_1", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_EL1BEG0_1", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_NW4A1_1", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_WW4B3_1", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_NE4C0_1", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_BYP0_R_1", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_IMUX19_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_EE2A0_1", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_WL1END1_1", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_NE2A3_1", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_EE4B1_1", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_LH4_1", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_IMUX6_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_FAN6_R_1", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_IMUX7_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_EE4C1_1", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_IMUX28_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_NE4BEG1_1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX47_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_1", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_EE4C0_1", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_EE2A2_1", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_SE4BEG0_1", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_WR1END3_1", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_NE4C2_1", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_NW4END0_1", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_IMUX25_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_WW2A3_1", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_IMUX24_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_1", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_SE4BEG1_1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_CLK1_R_1", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_IMUX12_R_1", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_PMVIOB" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_FEEDTHRU_1_CK_IN8", + "HCLK_FEEDTHRU_2_CK_IN8" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN3", + "HCLK_FEEDTHRU_2_CK_IN3" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK3", + "HCLK_FEEDTHRU_2_CK_BUFRCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN7", + "HCLK_FEEDTHRU_2_CK_IN7" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN13", + "HCLK_FEEDTHRU_2_CK_IN13" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK9", + "HCLK_FEEDTHRU_2_CK_BUFHCLK9" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK2", + "HCLK_FEEDTHRU_2_CK_BUFHCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK5", + "HCLK_FEEDTHRU_2_CK_BUFHCLK5" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK1", + "HCLK_FEEDTHRU_2_CK_BUFHCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN10", + "HCLK_FEEDTHRU_2_CK_IN10" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK1", + "HCLK_FEEDTHRU_2_CK_BUFRCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN5", + "HCLK_FEEDTHRU_2_CK_IN5" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN6", + "HCLK_FEEDTHRU_2_CK_IN6" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN0", + "HCLK_FEEDTHRU_2_CK_IN0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK11", + "HCLK_FEEDTHRU_2_CK_BUFHCLK11" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK7", + "HCLK_FEEDTHRU_2_CK_BUFHCLK7" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN2", + "HCLK_FEEDTHRU_2_CK_IN2" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN4", + "HCLK_FEEDTHRU_2_CK_IN4" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN1", + "HCLK_FEEDTHRU_2_CK_IN1" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN9", + "HCLK_FEEDTHRU_2_CK_IN9" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK3", + "HCLK_FEEDTHRU_2_CK_BUFHCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK8", + "HCLK_FEEDTHRU_2_CK_BUFHCLK8" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN12", + "HCLK_FEEDTHRU_2_CK_IN12" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK10", + "HCLK_FEEDTHRU_2_CK_BUFHCLK10" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK4", + "HCLK_FEEDTHRU_2_CK_BUFHCLK4" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK6", + "HCLK_FEEDTHRU_2_CK_BUFHCLK6" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK0", + "HCLK_FEEDTHRU_2_CK_BUFRCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN11", + "HCLK_FEEDTHRU_2_CK_IN11" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK0", + "HCLK_FEEDTHRU_2_CK_BUFHCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK2", + "HCLK_FEEDTHRU_2_CK_BUFRCLK2" + ] + ], + "tile_types": [ + "HCLK_FEEDTHRU_1", + "HCLK_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + -6 + ], + "wire_pairs": [ + [ + "CMT_TOP_LH12_7", + "VBRK_LH12" + ], + [ + "CMT_TOP_SW4END1_7", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_7", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE4C2_7", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_ER1BEG3_7", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END1_7", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WL1END2_7", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_NW4A0_7", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WR1END2_7", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW4A2_7", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG3_7", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EL1BEG0_7", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH11_7", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW2END2_7", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4A1_7", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NE2A1_7", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SW2A2_7", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_ER1BEG0_7", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_7", + "VBRK_LH1" + ], + [ + "CMT_TOP_SW4A3_7", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH10_7", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4BEG3_7", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C3_7", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4END3_7", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_ER1BEG1_7", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_7", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW2END0_7", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END2_7", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NE4C0_7", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EL1BEG1_7", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4END0_7", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EE2BEG3_7", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4C1_7", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A2_7", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_7", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE2A3_7", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4A1_7", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_LH2_7", + "VBRK_LH2" + ], + [ + "CMT_TOP_EL1BEG2_7", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WL1END0_7", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4C1_7", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW2END1_7", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2BEG0_7", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4B0_7", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C2_7", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A0_7", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_7", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_MONITOR_P_7", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_EE4B2_7", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG2_7", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A0_7", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG0_7", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW4A1_7", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_SE2A1_7", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4END2_7", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE2A3_7", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW4C0_7", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_7", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE4BEG2_7", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_SE4C0_7", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_ER1BEG2_7", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NE2A0_7", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4A3_7", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4BEG2_7", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_7", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4B3_7", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END3_7", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WW4C1_7", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WL1END3_7", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH9_7", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2A0_7", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG1_7", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_7", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_LH3_7", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_7", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE4BEG1_7", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EE4A2_7", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG0_7", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE4BEG2_7", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW4END3_7", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NE4BEG1_7", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A2_7", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NW4END0_7", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_7", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4A0_7", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END0_7", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_7", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW4END1_7", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH7_7", + "VBRK_LH7" + ], + [ + "CMT_TOP_SE4BEG1_7", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE4A3_7", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C2_7", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A3_7", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW2A1_7", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C3_7", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE2A2_7", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NE4C3_7", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE4C0_7", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WR1END1_7", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A2_7", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_NW4END3_7", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_WW4B1_7", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C1_7", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_7", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE2A1_7", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_7", + "VBRK_LH5" + ], + [ + "CMT_TOP_SE4C2_7", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B0_7", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE2A0_7", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW4A1_7", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SW2A0_7", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW2A3_7", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW2A0_7", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_7", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EL1BEG3_7", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_NW4A2_7", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG3_7", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NW2A3_7", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW4C3_7", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_7", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_LH4_7", + "VBRK_LH4" + ], + [ + "CMT_TOP_LH8_7", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B3_7", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_MONITOR_N_7", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_EE4BEG0_7", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2A3_7", + "VBRK_EE2A3" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -6 + ], + "wire_pairs": [ + [ + "CMT_TOP_LH12_7", + "VBRK_LH12" + ], + [ + "CMT_TOP_SW4END1_7", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_7", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE4C2_7", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_ER1BEG3_7", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END1_7", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_NW4A0_7", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WL1END2_7", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WR1END2_7", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW4A2_7", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG3_7", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EL1BEG0_7", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH11_7", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW2END2_7", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4A1_7", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NE2A1_7", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SW2A2_7", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_ER1BEG0_7", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_7", + "VBRK_LH1" + ], + [ + "CMT_TOP_SW4A3_7", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH10_7", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4BEG3_7", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C3_7", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4END3_7", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_ER1BEG1_7", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_7", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW2END0_7", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END2_7", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NE4C0_7", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EL1BEG1_7", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_EE2BEG3_7", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WW4END0_7", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4C1_7", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A2_7", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_7", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE2A3_7", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4A1_7", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_LH2_7", + "VBRK_LH2" + ], + [ + "CMT_TOP_EL1BEG2_7", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WL1END0_7", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4C1_7", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW2END1_7", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2BEG0_7", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4B0_7", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C2_7", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A0_7", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_7", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_MONITOR_P_7", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_EE4B2_7", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG2_7", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A0_7", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG0_7", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW4A1_7", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_SE2A1_7", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4END2_7", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE2A3_7", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW4C0_7", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_7", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE4BEG2_7", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_SE4C0_7", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_ER1BEG2_7", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NE2A0_7", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4A3_7", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4BEG2_7", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_7", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4B3_7", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END3_7", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WW4C1_7", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WL1END3_7", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH9_7", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2A0_7", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG1_7", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_7", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_LH3_7", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_7", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE4BEG1_7", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EE4A2_7", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG2_7", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SE4BEG0_7", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SW4END3_7", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NE4BEG1_7", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A2_7", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NW4END0_7", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_7", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4A0_7", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END0_7", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_7", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW4END1_7", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE4BEG1_7", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH7_7", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4A3_7", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C2_7", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A3_7", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW2A1_7", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C3_7", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE2A2_7", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NE4C3_7", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE4C0_7", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WR1END1_7", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A2_7", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_NW4END3_7", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_WW4B1_7", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C1_7", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_7", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE2A1_7", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_7", + "VBRK_LH5" + ], + [ + "CMT_TOP_SE4C2_7", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B0_7", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE2A0_7", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW4A1_7", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SW2A0_7", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW2A3_7", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW2A0_7", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_7", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EL1BEG3_7", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_NW4A2_7", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG3_7", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NW2A3_7", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW4C3_7", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_7", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_LH4_7", + "VBRK_LH4" + ], + [ + "CMT_TOP_LH8_7", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B3_7", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_MONITOR_N_7", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_EE4BEG0_7", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2A3_7", + "VBRK_EE2A3" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 11 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_IMUX23_2", + "CMT_TOP_IMUX23_15" + ], + [ + "CMT_FIFO_L_IMUX8_1", + "CMT_TOP_IMUX8_14" + ], + [ + "CMT_FIFO_EE4BEG3_2", + "CMT_TOP_EE4BEG3_15" + ], + [ + "CMT_FIFO_L_FAN6_2", + "CMT_TOP_FAN6_15" + ], + [ + "CMT_FIFO_WW4C2_2", + "CMT_TOP_WW4C2_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_0", + "CMT_TOP_LOGIC_OUTS_L_B12_13" + ], + [ + "CMT_FIFO_WW4B0_2", + "CMT_TOP_WW4B0_15" + ], + [ + "CMT_FIFO_EE2A2_2", + "CMT_TOP_EE2A2_15" + ], + [ + "CMT_FIFO_L_IMUX20_0", + "CMT_TOP_IMUX20_13" + ], + [ + "CMT_FIFO_L_BYP1_2", + "CMT_TOP_BYP1_15" + ], + [ + "CMT_FIFO_L_FAN0_1", + "CMT_TOP_FAN0_14" + ], + [ + "CMT_FIFO_L_IMUX36_0", + "CMT_TOP_IMUX36_13" + ], + [ + "CMT_FIFO_SW2A2_2", + "CMT_TOP_SW2A2_15" + ], + [ + "CMT_FIFO_L_IMUX28_1", + "CMT_TOP_IMUX28_14" + ], + [ + "CMT_FIFO_EE2BEG3_1", + "CMT_TOP_EE2BEG3_14" + ], + [ + "CMT_FIFO_WW4B2_2", + "CMT_TOP_WW4B2_15" + ], + [ + "CMT_FIFO_NW4A1_2", + "CMT_TOP_NW4A1_15" + ], + [ + "CMT_FIFO_NW4A2_1", + "CMT_TOP_NW4A2_14" + ], + [ + "CMT_FIFO_L_IMUX9_1", + "CMT_TOP_IMUX9_14" + ], + [ + "CMT_FIFO_NE2A1_1", + "CMT_TOP_NE2A1_14" + ], + [ + "CMT_FIFO_EE2BEG0_0", + "CMT_TOP_EE2BEG0_13" + ], + [ + "CMT_FIFO_L_FAN0_2", + "CMT_TOP_FAN0_15" + ], + [ + "CMT_FIFO_L_IMUX38_1", + "CMT_TOP_IMUX38_14" + ], + [ + "CMT_FIFO_L_IMUX36_1", + "CMT_TOP_IMUX36_14" + ], + [ + "CMT_FIFO_EE2A1_2", + "CMT_TOP_EE2A1_15" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "CMT_TOP_OCLKDIV_14" + ], + [ + "CMT_FIFO_EE4A2_1", + "CMT_TOP_EE4A2_14" + ], + [ + "CMT_FIFO_WW2END0_1", + "CMT_TOP_WW2END0_14" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "CMT_TOP_OCLKDIV_13" + ], + [ + "CMT_FIFO_EE2A0_2", + "CMT_TOP_EE2A0_15" + ], + [ + "CMT_FIFO_SE4BEG2_1", + "CMT_TOP_SE4BEG2_14" + ], + [ + "CMT_FIFO_EE4BEG1_2", + "CMT_TOP_EE4BEG1_15" + ], + [ + "CMT_FIFO_EE4A0_2", + "CMT_TOP_EE4A0_15" + ], + [ + "CMT_FIFO_L_IMUX31_1", + "CMT_TOP_IMUX31_14" + ], + [ + "CMT_FIFO_EE4B3_2", + "CMT_TOP_EE4B3_15" + ], + [ + "CMT_FIFO_EE4BEG3_0", + "CMT_TOP_EE4BEG3_13" + ], + [ + "CMT_FIFO_L_IMUX33_2", + "CMT_TOP_IMUX33_15" + ], + [ + "CMT_FIFO_NW4A1_0", + "CMT_TOP_NW4A1_13" + ], + [ + "CMT_FIFO_SE4C3_0", + "CMT_TOP_SE4C3_13" + ], + [ + "CMT_FIFO_WW4B3_0", + "CMT_TOP_WW4B3_13" + ], + [ + "CMT_FIFO_WW4A2_1", + "CMT_TOP_WW4A2_14" + ], + [ + "CMT_FIFO_L_BYP2_0", + "CMT_TOP_BYP2_13" + ], + [ + "CMT_FIFO_L_IMUX26_1", + "CMT_TOP_IMUX26_14" + ], + [ + "CMT_FIFO_WR1END1_1", + "CMT_TOP_WR1END1_14" + ], + [ + "CMT_FIFO_EE4C1_2", + "CMT_TOP_EE4C1_15" + ], + [ + "CMT_FIFO_ER1BEG1_1", + "CMT_TOP_ER1BEG1_14" + ], + [ + "CMT_FIFO_LH2_0", + "CMT_TOP_LH2_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_0", + "CMT_TOP_LOGIC_OUTS_L_B5_13" + ], + [ + "CMT_FIFO_LH10_1", + "CMT_TOP_LH10_14" + ], + [ + "CMT_FIFO_L_IMUX42_2", + "CMT_TOP_IMUX42_15" + ], + [ + "CMT_FIFO_L_IMUX6_0", + "CMT_TOP_IMUX6_13" + ], + [ + "CMT_FIFO_SE2A1_1", + "CMT_TOP_SE2A1_14" + ], + [ + "CMT_FIFO_SE2A0_1", + "CMT_TOP_SE2A0_14" + ], + [ + "CMT_FIFO_SW2A1_1", + "CMT_TOP_SW2A1_14" + ], + [ + "CMT_FIFO_SE4C2_0", + "CMT_TOP_SE4C2_13" + ], + [ + "CMT_FIFO_WW2A3_1", + "CMT_TOP_WW2A3_14" + ], + [ + "CMT_FIFO_L_IMUX3_1", + "CMT_TOP_IMUX3_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_15" + ], + [ + "CMT_FIFO_L_IMUX12_0", + "CMT_TOP_IMUX12_13" + ], + [ + "CMT_FIFO_NE4C0_0", + "CMT_TOP_NE4C0_13" + ], + [ + "CMT_FIFO_L_BYP7_0", + "CMT_TOP_BYP7_13" + ], + [ + "CMT_FIFO_WR1END1_2", + "CMT_TOP_WR1END1_15" + ], + [ + "CMT_FIFO_SE4C3_2", + "CMT_TOP_SE4C3_15" + ], + [ + "CMT_FIFO_NE4BEG1_0", + "CMT_TOP_NE4BEG1_13" + ], + [ + "CMT_FIFO_EL1BEG0_1", + "CMT_TOP_EL1BEG0_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_1", + "CMT_TOP_LOGIC_OUTS_L_B9_14" + ], + [ + "CMT_FIFO_WW4C0_0", + "CMT_TOP_WW4C0_13" + ], + [ + "CMT_FIFO_L_IMUX0_0", + "CMT_TOP_IMUX0_13" + ], + [ + "CMT_FIFO_WW2END2_0", + "CMT_TOP_WW2END2_13" + ], + [ + "CMT_FIFO_L_IMUX15_0", + "CMT_TOP_IMUX15_13" + ], + [ + "CMT_FIFO_NE4BEG1_1", + "CMT_TOP_NE4BEG1_14" + ], + [ + "CMT_FIFO_WL1END0_2", + "CMT_TOP_WL1END0_15" + ], + [ + "CMT_FIFO_EE4A0_0", + "CMT_TOP_EE4A0_13" + ], + [ + "CMT_FIFO_L_FAN1_2", + "CMT_TOP_FAN1_15" + ], + [ + "CMT_FIFO_L_IMUX2_2", + "CMT_TOP_IMUX2_15" + ], + [ + "CMT_FIFO_SW4END2_2", + "CMT_TOP_SW4END2_15" + ], + [ + "CMT_FIFO_L_IMUX33_0", + "CMT_TOP_IMUX33_13" + ], + [ + "CMT_FIFO_L_FAN2_1", + "CMT_TOP_FAN2_14" + ], + [ + "CMT_FIFO_EE2BEG0_1", + "CMT_TOP_EE2BEG0_14" + ], + [ + "CMT_FIFO_NW4END3_2", + "CMT_TOP_NW4END3_15" + ], + [ + "CMT_FIFO_SE4C0_2", + "CMT_TOP_SE4C0_15" + ], + [ + "CMT_FIFO_L_BYP7_2", + "CMT_TOP_BYP7_15" + ], + [ + "CMT_FIFO_L_IMUX21_0", + "CMT_TOP_IMUX21_13" + ], + [ + "CMT_FIFO_L_IMUX27_0", + "CMT_TOP_IMUX27_13" + ], + [ + "CMT_FIFO_NW2A0_2", + "CMT_TOP_NW2A0_15" + ], + [ + "CMT_FIFO_WL1END3_0", + "CMT_TOP_WL1END3_13" + ], + [ + "CMT_FIFO_SW4A2_2", + "CMT_TOP_SW4A2_15" + ], + [ + "CMT_FIFO_L_IMUX7_2", + "CMT_TOP_IMUX7_15" + ], + [ + "CMT_FIFO_SW4END1_1", + "CMT_TOP_SW4END1_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_2", + "CMT_TOP_LOGIC_OUTS_L_B11_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_1", + "CMT_TOP_LOGIC_OUTS_L_B1_14" + ], + [ + "CMT_FIFO_EE4A1_2", + "CMT_TOP_EE4A1_15" + ], + [ + "CMT_FIFO_L_IMUX47_0", + "CMT_TOP_IMUX47_13" + ], + [ + "CMT_FIFO_L_IMUX29_1", + "CMT_TOP_IMUX29_14" + ], + [ + "CMT_FIFO_SW4A1_1", + "CMT_TOP_SW4A1_14" + ], + [ + "CMT_FIFO_L_IMUX10_2", + "CMT_TOP_IMUX10_15" + ], + [ + "CMT_FIFO_L_IMUX7_1", + "CMT_TOP_IMUX7_14" + ], + [ + "CMT_FIFO_NE2A0_2", + "CMT_TOP_NE2A0_15" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "CMT_TOP_OCLKDIV_15" + ], + [ + "CMT_FIFO_L_IMUX12_2", + "CMT_TOP_IMUX12_15" + ], + [ + "CMT_FIFO_EE4B2_1", + "CMT_TOP_EE4B2_14" + ], + [ + "CMT_FIFO_L_IMUX39_2", + "CMT_TOP_IMUX39_15" + ], + [ + "CMT_FIFO_L_BYP2_1", + "CMT_TOP_BYP2_14" + ], + [ + "CMT_FIFO_EE4B0_2", + "CMT_TOP_EE4B0_15" + ], + [ + "CMT_FIFO_L_IMUX44_2", + "CMT_TOP_IMUX44_15" + ], + [ + "CMT_FIFO_EE4C1_0", + "CMT_TOP_EE4C1_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_0", + "CMT_TOP_LOGIC_OUTS_L_B20_13" + ], + [ + "CMT_FIFO_SE4BEG0_1", + "CMT_TOP_SE4BEG0_14" + ], + [ + "CMT_FIFO_L_IMUX22_0", + "CMT_TOP_IMUX22_13" + ], + [ + "CMT_FIFO_WL1END0_1", + "CMT_TOP_WL1END0_14" + ], + [ + "CMT_FIFO_SE4BEG3_0", + "CMT_TOP_SE4BEG3_13" + ], + [ + "CMT_FIFO_NE2A0_0", + "CMT_TOP_NE2A0_13" + ], + [ + "CMT_FIFO_WW2A0_2", + "CMT_TOP_WW2A0_15" + ], + [ + "CMT_FIFO_WW4END1_1", + "CMT_TOP_WW4END1_14" + ], + [ + "CMT_FIFO_EE4B2_2", + "CMT_TOP_EE4B2_15" + ], + [ + "CMT_FIFO_L_FAN6_0", + "CMT_TOP_FAN6_13" + ], + [ + "CMT_FIFO_L_FAN4_2", + "CMT_TOP_FAN4_15" + ], + [ + "CMT_FIFO_ER1BEG0_0", + "CMT_TOP_ER1BEG0_13" + ], + [ + "CMT_FIFO_L_IMUX24_2", + "CMT_TOP_IMUX24_15" + ], + [ + "CMT_FIFO_L_BYP0_1", + "CMT_TOP_BYP0_14" + ], + [ + "CMT_FIFO_L_CTRL1_2", + "CMT_TOP_CTRL1_15" + ], + [ + "CMT_FIFO_NW4A3_2", + "CMT_TOP_NW4A3_15" + ], + [ + "CMT_FIFO_EE4C3_2", + "CMT_TOP_EE4C3_15" + ], + [ + "CMT_FIFO_NW2A2_0", + "CMT_TOP_NW2A2_13" + ], + [ + "CMT_FIFO_L_IMUX25_0", + "CMT_TOP_IMUX25_13" + ], + [ + "CMT_FIFO_WR1END2_1", + "CMT_TOP_WR1END2_14" + ], + [ + "CMT_FIFO_EE4A2_2", + "CMT_TOP_EE4A2_15" + ], + [ + "CMT_FIFO_LH8_0", + "CMT_TOP_LH8_13" + ], + [ + "CMT_FIFO_NW2A0_1", + "CMT_TOP_NW2A0_14" + ], + [ + "CMT_FIFO_WL1END3_2", + "CMT_TOP_WL1END3_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_0", + "CMT_TOP_LOGIC_OUTS_L_B13_13" + ], + [ + "CMT_FIFO_EE4BEG2_2", + "CMT_TOP_EE4BEG2_15" + ], + [ + "CMT_FIFO_L_IMUX1_1", + "CMT_TOP_IMUX1_14" + ], + [ + "CMT_FIFO_L_BYP3_0", + "CMT_TOP_BYP3_13" + ], + [ + "CMT_FIFO_L_CTRL0_1", + "CMT_TOP_CTRL0_14" + ], + [ + "CMT_FIFO_WW2A2_0", + "CMT_TOP_WW2A2_13" + ], + [ + "CMT_FIFO_L_FAN7_2", + "CMT_TOP_FAN7_15" + ], + [ + "CMT_FIFO_EE4A0_1", + "CMT_TOP_EE4A0_14" + ], + [ + "CMT_FIFO_L_IMUX11_1", + "CMT_TOP_IMUX11_14" + ], + [ + "CMT_FIFO_NE4BEG2_0", + "CMT_TOP_NE4BEG2_13" + ], + [ + "CMT_FIFO_NW4END3_1", + "CMT_TOP_NW4END3_14" + ], + [ + "CMT_FIFO_SW4END0_1", + "CMT_TOP_SW4END0_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_1", + "CMT_TOP_LOGIC_OUTS_L_B5_14" + ], + [ + "CMT_FIFO_SW2A3_1", + "CMT_TOP_SW2A3_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_1", + "CMT_TOP_LOGIC_OUTS_L_B13_14" + ], + [ + "CMT_FIFO_EE4B1_1", + "CMT_TOP_EE4B1_14" + ], + [ + "CMT_FIFO_L_IMUX3_2", + "CMT_TOP_IMUX3_15" + ], + [ + "CMT_FIFO_SW4A2_0", + "CMT_TOP_SW4A2_13" + ], + [ + "CMT_FIFO_EE2A0_0", + "CMT_TOP_EE2A0_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_2", + "CMT_TOP_LOGIC_OUTS_L_B22_15" + ], + [ + "CMT_FIFO_NW4A3_1", + "CMT_TOP_NW4A3_14" + ], + [ + "CMT_FIFO_L_IMUX18_1", + "CMT_TOP_IMUX18_14" + ], + [ + "CMT_FIFO_EE4A2_0", + "CMT_TOP_EE4A2_13" + ], + [ + "CMT_FIFO_L_IMUX47_1", + "CMT_TOP_IMUX47_14" + ], + [ + "CMT_FIFO_L_IMUX43_2", + "CMT_TOP_IMUX43_15" + ], + [ + "CMT_FIFO_ER1BEG3_0", + "CMT_TOP_ER1BEG3_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_0", + "CMT_TOP_LOGIC_OUTS_L_B9_13" + ], + [ + "CMT_FIFO_WW4C1_1", + "CMT_TOP_WW4C1_14" + ], + [ + "CMT_FIFO_WW2END1_1", + "CMT_TOP_WW2END1_14" + ], + [ + "CMT_FIFO_WL1END2_0", + "CMT_TOP_WL1END2_13" + ], + [ + "CMT_FIFO_EE4B3_1", + "CMT_TOP_EE4B3_14" + ], + [ + "CMT_FIFO_EL1BEG0_2", + "CMT_TOP_EL1BEG0_15" + ], + [ + "CMT_FIFO_NW4A3_0", + "CMT_TOP_NW4A3_13" + ], + [ + "CMT_FIFO_LH12_0", + "CMT_TOP_LH12_13" + ], + [ + "CMT_FIFO_NW4A0_0", + "CMT_TOP_NW4A0_13" + ], + [ + "CMT_FIFO_SW4END1_2", + "CMT_TOP_SW4END1_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_0", + "CMT_TOP_LOGIC_OUTS_L_B19_13" + ], + [ + "CMT_FIFO_SW4END3_2", + "CMT_TOP_SW4END3_15" + ], + [ + "CMT_FIFO_SW2A3_2", + "CMT_TOP_SW2A3_15" + ], + [ + "CMT_FIFO_LH5_2", + "CMT_TOP_LH5_15" + ], + [ + "CMT_FIFO_L_CLK1_1", + "CMT_TOP_CLK1_14" + ], + [ + "CMT_FIFO_L_IMUX8_2", + "CMT_TOP_IMUX8_15" + ], + [ + "CMT_FIFO_L_IMUX32_2", + "CMT_TOP_IMUX32_15" + ], + [ + "CMT_FIFO_L_BYP1_0", + "CMT_TOP_BYP1_13" + ], + [ + "CMT_FIFO_WW4B3_2", + "CMT_TOP_WW4B3_15" + ], + [ + "CMT_FIFO_L_FAN3_2", + "CMT_TOP_FAN3_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_2", + "CMT_TOP_LOGIC_OUTS_L_B13_15" + ], + [ + "CMT_FIFO_EE4BEG0_2", + "CMT_TOP_EE4BEG0_15" + ], + [ + "CMT_FIFO_L_IMUX39_0", + "CMT_TOP_IMUX39_13" + ], + [ + "CMT_FIFO_L_IMUX40_0", + "CMT_TOP_IMUX40_13" + ], + [ + "CMT_FIFO_WR1END0_1", + "CMT_TOP_WR1END0_14" + ], + [ + "CMT_FIFO_L_IMUX21_1", + "CMT_TOP_IMUX21_14" + ], + [ + "CMT_FIFO_LH6_0", + "CMT_TOP_LH6_13" + ], + [ + "CMT_FIFO_L_IMUX24_1", + "CMT_TOP_IMUX24_14" + ], + [ + "CMT_FIFO_WW4END0_2", + "CMT_TOP_WW4END0_15" + ], + [ + "CMT_FIFO_WR1END0_2", + "CMT_TOP_WR1END0_15" + ], + [ + "CMT_FIFO_EL1BEG1_0", + "CMT_TOP_EL1BEG1_13" + ], + [ + "CMT_FIFO_WW4B0_1", + "CMT_TOP_WW4B0_14" + ], + [ + "CMT_FIFO_EE4BEG1_0", + "CMT_TOP_EE4BEG1_13" + ], + [ + "CMT_FIFO_NE4C0_1", + "CMT_TOP_NE4C0_14" + ], + [ + "CMT_FIFO_WL1END2_1", + "CMT_TOP_WL1END2_14" + ], + [ + "CMT_FIFO_NW4END3_0", + "CMT_TOP_NW4END3_13" + ], + [ + "CMT_FIFO_LH11_2", + "CMT_TOP_LH11_15" + ], + [ + "CMT_FIFO_WW2END3_2", + "CMT_TOP_WW2END3_15" + ], + [ + "CMT_FIFO_EL1BEG0_0", + "CMT_TOP_EL1BEG0_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_1", + "CMT_TOP_LOGIC_OUTS_L_B20_14" + ], + [ + "CMT_FIFO_L_FAN4_1", + "CMT_TOP_FAN4_14" + ], + [ + "CMT_FIFO_NE4BEG3_0", + "CMT_TOP_NE4BEG3_13" + ], + [ + "CMT_FIFO_SW4A1_0", + "CMT_TOP_SW4A1_13" + ], + [ + "CMT_FIFO_EE4C1_1", + "CMT_TOP_EE4C1_14" + ], + [ + "CMT_FIFO_NW2A1_1", + "CMT_TOP_NW2A1_14" + ], + [ + "CMT_FIFO_L_FAN1_1", + "CMT_TOP_FAN1_14" + ], + [ + "CMT_FIFO_L_CTRL0_2", + "CMT_TOP_CTRL0_15" + ], + [ + "CMT_FIFO_L_FAN6_1", + "CMT_TOP_FAN6_14" + ], + [ + "CMT_FIFO_EE4B2_0", + "CMT_TOP_EE4B2_13" + ], + [ + "CMT_FIFO_L_IMUX32_1", + "CMT_TOP_IMUX32_14" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "CMT_TOP_ICLK_14" + ], + [ + "CMT_FIFO_WW4A0_0", + "CMT_TOP_WW4A0_13" + ], + [ + "CMT_FIFO_WW4B1_1", + "CMT_TOP_WW4B1_14" + ], + [ + "CMT_FIFO_L_IMUX17_0", + "CMT_TOP_IMUX17_13" + ], + [ + "CMT_FIFO_WW2A3_0", + "CMT_TOP_WW2A3_13" + ], + [ + "CMT_FIFO_NE4C0_2", + "CMT_TOP_NE4C0_15" + ], + [ + "CMT_FIFO_L_IMUX38_0", + "CMT_TOP_IMUX38_13" + ], + [ + "CMT_FIFO_SE4BEG1_0", + "CMT_TOP_SE4BEG1_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_2", + "CMT_TOP_LOGIC_OUTS_L_B8_15" + ], + [ + "CMT_FIFO_L_IMUX11_0", + "CMT_TOP_IMUX11_13" + ], + [ + "CMT_FIFO_NW2A1_2", + "CMT_TOP_NW2A1_15" + ], + [ + "CMT_FIFO_WR1END0_0", + "CMT_TOP_WR1END0_13" + ], + [ + "CMT_FIFO_WW4B2_0", + "CMT_TOP_WW4B2_13" + ], + [ + "CMT_FIFO_WW4A3_0", + "CMT_TOP_WW4A3_13" + ], + [ + "CMT_FIFO_L_IMUX20_1", + "CMT_TOP_IMUX20_14" + ], + [ + "CMT_FIFO_SE4BEG2_0", + "CMT_TOP_SE4BEG2_13" + ], + [ + "CMT_FIFO_WW2END3_1", + "CMT_TOP_WW2END3_14" + ], + [ + "CMT_FIFO_L_BYP6_1", + "CMT_TOP_BYP6_14" + ], + [ + "CMT_FIFO_SE4BEG3_2", + "CMT_TOP_SE4BEG3_15" + ], + [ + "CMT_FIFO_LH11_0", + "CMT_TOP_LH11_13" + ], + [ + "CMT_FIFO_L_IMUX27_1", + "CMT_TOP_IMUX27_14" + ], + [ + "CMT_FIFO_L_IMUX16_0", + "CMT_TOP_IMUX16_13" + ], + [ + "CMT_FIFO_L_IMUX19_1", + "CMT_TOP_IMUX19_14" + ], + [ + "CMT_FIFO_LH7_1", + "CMT_TOP_LH7_14" + ], + [ + "CMT_FIFO_L_CLK1_2", + "CMT_TOP_CLK1_15" + ], + [ + "CMT_FIFO_SW2A0_2", + "CMT_TOP_SW2A0_15" + ], + [ + "CMT_FIFO_WW4B3_1", + "CMT_TOP_WW4B3_14" + ], + [ + "CMT_FIFO_L_IMUX29_2", + "CMT_TOP_IMUX29_15" + ], + [ + "CMT_FIFO_LH1_0", + "CMT_TOP_LH1_13" + ], + [ + "CMT_FIFO_WW2A2_1", + "CMT_TOP_WW2A2_14" + ], + [ + "CMT_FIFO_WW2A1_2", + "CMT_TOP_WW2A1_15" + ], + [ + "CMT_FIFO_EL1BEG1_1", + "CMT_TOP_EL1BEG1_14" + ], + [ + "CMT_FIFO_SW2A2_1", + "CMT_TOP_SW2A2_14" + ], + [ + "CMT_FIFO_WR1END3_0", + "CMT_TOP_WR1END3_13" + ], + [ + "CMT_FIFO_EE2A3_0", + "CMT_TOP_EE2A3_13" + ], + [ + "CMT_FIFO_SE4BEG2_2", + "CMT_TOP_SE4BEG2_15" + ], + [ + "CMT_FIFO_L_CTRL1_1", + "CMT_TOP_CTRL1_14" + ], + [ + "CMT_FIFO_L_IMUX0_2", + "CMT_TOP_IMUX0_15" + ], + [ + "CMT_FIFO_WW4A2_2", + "CMT_TOP_WW4A2_15" + ], + [ + "CMT_FIFO_LH11_1", + "CMT_TOP_LH11_14" + ], + [ + "CMT_FIFO_EE4A3_1", + "CMT_TOP_EE4A3_14" + ], + [ + "CMT_FIFO_L_IMUX18_2", + "CMT_TOP_IMUX18_15" + ], + [ + "CMT_FIFO_LH6_1", + "CMT_TOP_LH6_14" + ], + [ + "CMT_FIFO_L_IMUX23_0", + "CMT_TOP_IMUX23_13" + ], + [ + "CMT_FIFO_LH4_2", + "CMT_TOP_LH4_15" + ], + [ + "CMT_FIFO_WW4END2_2", + "CMT_TOP_WW4END2_15" + ], + [ + "CMT_FIFO_NW4END2_0", + "CMT_TOP_NW4END2_13" + ], + [ + "CMT_FIFO_EE4C0_0", + "CMT_TOP_EE4C0_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_2", + "CMT_TOP_LOGIC_OUTS_L_B5_15" + ], + [ + "CMT_FIFO_EE2A1_0", + "CMT_TOP_EE2A1_13" + ], + [ + "CMT_FIFO_ER1BEG1_0", + "CMT_TOP_ER1BEG1_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_2", + "CMT_TOP_LOGIC_OUTS_L_B20_15" + ], + [ + "CMT_FIFO_WL1END1_1", + "CMT_TOP_WL1END1_14" + ], + [ + "CMT_FIFO_WW2END2_2", + "CMT_TOP_WW2END2_15" + ], + [ + "CMT_FIFO_SE4BEG0_0", + "CMT_TOP_SE4BEG0_13" + ], + [ + "CMT_FIFO_L_IMUX40_2", + "CMT_TOP_IMUX40_15" + ], + [ + "CMT_FIFO_NE4BEG0_2", + "CMT_TOP_NE4BEG0_15" + ], + [ + "CMT_FIFO_SW4A1_2", + "CMT_TOP_SW4A1_15" + ], + [ + "CMT_FIFO_L_IMUX9_0", + "CMT_TOP_IMUX9_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_2", + "CMT_TOP_LOGIC_OUTS_L_B12_15" + ], + [ + "CMT_FIFO_WW4B1_2", + "CMT_TOP_WW4B1_15" + ], + [ + "CMT_FIFO_SW2A2_0", + "CMT_TOP_SW2A2_13" + ], + [ + "CMT_FIFO_WW2END1_0", + "CMT_TOP_WW2END1_13" + ], + [ + "CMT_FIFO_L_FAN3_0", + "CMT_TOP_FAN3_13" + ], + [ + "CMT_FIFO_WW4C2_1", + "CMT_TOP_WW4C2_14" + ], + [ + "CMT_FIFO_L_IMUX2_0", + "CMT_TOP_IMUX2_13" + ], + [ + "CMT_FIFO_L_IMUX28_2", + "CMT_TOP_IMUX28_15" + ], + [ + "CMT_FIFO_NE4C3_0", + "CMT_TOP_NE4C3_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_1", + "CMT_TOP_LOGIC_OUTS_L_B0_14" + ], + [ + "CMT_FIFO_L_BYP1_1", + "CMT_TOP_BYP1_14" + ], + [ + "CMT_FIFO_WL1END1_2", + "CMT_TOP_WL1END1_15" + ], + [ + "CMT_FIFO_SE2A1_0", + "CMT_TOP_SE2A1_13" + ], + [ + "CMT_FIFO_L_IMUX41_2", + "CMT_TOP_IMUX41_15" + ], + [ + "CMT_FIFO_NE4C3_2", + "CMT_TOP_NE4C3_15" + ], + [ + "CMT_FIFO_NW4END2_2", + "CMT_TOP_NW4END2_15" + ], + [ + "CMT_FIFO_SW4END0_0", + "CMT_TOP_SW4END0_13" + ], + [ + "CMT_FIFO_SE4C0_0", + "CMT_TOP_SE4C0_13" + ], + [ + "CMT_FIFO_NW4END1_1", + "CMT_TOP_NW4END1_14" + ], + [ + "CMT_FIFO_SE4BEG1_2", + "CMT_TOP_SE4BEG1_15" + ], + [ + "CMT_FIFO_EE4C0_1", + "CMT_TOP_EE4C0_14" + ], + [ + "CMT_FIFO_NE2A2_0", + "CMT_TOP_NE2A2_13" + ], + [ + "CMT_FIFO_L_BYP5_0", + "CMT_TOP_BYP5_13" + ], + [ + "CMT_FIFO_LH7_2", + "CMT_TOP_LH7_15" + ], + [ + "CMT_FIFO_EE4BEG2_1", + "CMT_TOP_EE4BEG2_14" + ], + [ + "CMT_FIFO_EE4BEG2_0", + "CMT_TOP_EE4BEG2_13" + ], + [ + "CMT_FIFO_L_CTRL1_0", + "CMT_TOP_CTRL1_13" + ], + [ + "CMT_FIFO_NW4A0_1", + "CMT_TOP_NW4A0_14" + ], + [ + "CMT_FIFO_NW2A2_2", + "CMT_TOP_NW2A2_15" + ], + [ + "CMT_FIFO_NE2A2_1", + "CMT_TOP_NE2A2_14" + ], + [ + "CMT_FIFO_NE4C2_0", + "CMT_TOP_NE4C2_13" + ], + [ + "CMT_FIFO_SE4BEG0_2", + "CMT_TOP_SE4BEG0_15" + ], + [ + "CMT_FIFO_L_IMUX14_2", + "CMT_TOP_IMUX14_15" + ], + [ + "CMT_FIFO_L_BYP6_2", + "CMT_TOP_BYP6_15" + ], + [ + "CMT_FIFO_WW2A1_0", + "CMT_TOP_WW2A1_13" + ], + [ + "CMT_FIFO_NW4END0_1", + "CMT_TOP_NW4END0_14" + ], + [ + "CMT_FIFO_EE4C2_2", + "CMT_TOP_EE4C2_15" + ], + [ + "CMT_FIFO_WR1END3_2", + "CMT_TOP_WR1END3_15" + ], + [ + "CMT_FIFO_WW4A0_1", + "CMT_TOP_WW4A0_14" + ], + [ + "CMT_FIFO_EE2BEG1_2", + "CMT_TOP_EE2BEG1_15" + ], + [ + "CMT_FIFO_NW2A3_0", + "CMT_TOP_NW2A3_13" + ], + [ + "CMT_FIFO_WL1END1_0", + "CMT_TOP_WL1END1_13" + ], + [ + "CMT_FIFO_EE2A2_0", + "CMT_TOP_EE2A2_13" + ], + [ + "CMT_FIFO_SE2A2_2", + "CMT_TOP_SE2A2_15" + ], + [ + "CMT_FIFO_L_IMUX46_1", + "CMT_TOP_IMUX46_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_2", + "CMT_TOP_LOGIC_OUTS_L_B9_15" + ], + [ + "CMT_FIFO_EE4B0_0", + "CMT_TOP_EE4B0_13" + ], + [ + "CMT_FIFO_NE2A3_0", + "CMT_TOP_NE2A3_13" + ], + [ + "CMT_FIFO_SW4END1_0", + "CMT_TOP_SW4END1_13" + ], + [ + "CMT_FIFO_NE4C2_1", + "CMT_TOP_NE4C2_14" + ], + [ + "CMT_FIFO_WW4END2_1", + "CMT_TOP_WW4END2_14" + ], + [ + "CMT_FIFO_SE4C1_0", + "CMT_TOP_SE4C1_13" + ], + [ + "CMT_FIFO_SW4END0_2", + "CMT_TOP_SW4END0_15" + ], + [ + "CMT_FIFO_NE4C2_2", + "CMT_TOP_NE4C2_15" + ], + [ + "CMT_FIFO_NW4END0_2", + "CMT_TOP_NW4END0_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_0", + "CMT_TOP_LOGIC_OUTS_L_B4_13" + ], + [ + "CMT_FIFO_MONITOR_N_0", + "CMT_TOP_MONITOR_N_13" + ], + [ + "CMT_FIFO_EL1BEG3_2", + "CMT_TOP_EL1BEG3_15" + ], + [ + "CMT_FIFO_LH8_2", + "CMT_TOP_LH8_15" + ], + [ + "CMT_FIFO_L_IMUX15_1", + "CMT_TOP_IMUX15_14" + ], + [ + "CMT_FIFO_L_IMUX33_1", + "CMT_TOP_IMUX33_14" + ], + [ + "CMT_FIFO_EE2BEG2_1", + "CMT_TOP_EE2BEG2_14" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "CMT_TOP_ICLKDIV_13" + ], + [ + "CMT_FIFO_L_IMUX16_1", + "CMT_TOP_IMUX16_14" + ], + [ + "CMT_FIFO_L_CLK0_2", + "CMT_TOP_CLK0_15" + ], + [ + "CMT_FIFO_NE2A2_2", + "CMT_TOP_NE2A2_15" + ], + [ + "CMT_FIFO_ER1BEG0_2", + "CMT_TOP_ER1BEG0_15" + ], + [ + "CMT_FIFO_EE4BEG0_1", + "CMT_TOP_EE4BEG0_14" + ], + [ + "CMT_FIFO_L_IMUX34_0", + "CMT_TOP_IMUX34_13" + ], + [ + "CMT_FIFO_WW4A3_2", + "CMT_TOP_WW4A3_15" + ], + [ + "CMT_FIFO_L_IMUX8_0", + "CMT_TOP_IMUX8_13" + ], + [ + "CMT_FIFO_NW2A2_1", + "CMT_TOP_NW2A2_14" + ], + [ + "CMT_FIFO_EE2A2_1", + "CMT_TOP_EE2A2_14" + ], + [ + "CMT_FIFO_SW4A0_1", + "CMT_TOP_SW4A0_14" + ], + [ + "CMT_FIFO_EE4A1_0", + "CMT_TOP_EE4A1_13" + ], + [ + "CMT_FIFO_L_IMUX3_0", + "CMT_TOP_IMUX3_13" + ], + [ + "CMT_FIFO_EE2BEG2_0", + "CMT_TOP_EE2BEG2_13" + ], + [ + "CMT_FIFO_LH2_1", + "CMT_TOP_LH2_14" + ], + [ + "CMT_FIFO_EE4A3_2", + "CMT_TOP_EE4A3_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_1", + "CMT_TOP_LOGIC_OUTS_L_B11_14" + ], + [ + "CMT_FIFO_LH1_2", + "CMT_TOP_LH1_15" + ], + [ + "CMT_FIFO_EE4A1_1", + "CMT_TOP_EE4A1_14" + ], + [ + "CMT_FIFO_L_IMUX47_2", + "CMT_TOP_IMUX47_15" + ], + [ + "CMT_FIFO_L_IMUX17_2", + "CMT_TOP_IMUX17_15" + ], + [ + "CMT_FIFO_NE4BEG2_2", + "CMT_TOP_NE4BEG2_15" + ], + [ + "CMT_FIFO_WW4C0_2", + "CMT_TOP_WW4C0_15" + ], + [ + "CMT_FIFO_EL1BEG2_0", + "CMT_TOP_EL1BEG2_13" + ], + [ + "CMT_FIFO_SE2A2_1", + "CMT_TOP_SE2A2_14" + ], + [ + "CMT_FIFO_L_IMUX13_0", + "CMT_TOP_IMUX13_13" + ], + [ + "CMT_FIFO_L_IMUX30_1", + "CMT_TOP_IMUX30_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_13" + ], + [ + "CMT_FIFO_LH12_2", + "CMT_TOP_LH12_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_1", + "CMT_TOP_LOGIC_OUTS_L_B4_14" + ], + [ + "CMT_FIFO_WW4A3_1", + "CMT_TOP_WW4A3_14" + ], + [ + "CMT_FIFO_WW4C2_0", + "CMT_TOP_WW4C2_13" + ], + [ + "CMT_FIFO_L_BYP3_1", + "CMT_TOP_BYP3_14" + ], + [ + "CMT_FIFO_L_IMUX5_2", + "CMT_TOP_IMUX5_15" + ], + [ + "CMT_FIFO_MONITOR_N_2", + "CMT_TOP_MONITOR_N_15" + ], + [ + "CMT_FIFO_SE4C3_1", + "CMT_TOP_SE4C3_14" + ], + [ + "CMT_FIFO_SE2A3_1", + "CMT_TOP_SE2A3_14" + ], + [ + "CMT_FIFO_NE4BEG3_1", + "CMT_TOP_NE4BEG3_14" + ], + [ + "CMT_FIFO_WW4END1_2", + "CMT_TOP_WW4END1_15" + ], + [ + "CMT_FIFO_EE2A0_1", + "CMT_TOP_EE2A0_14" + ], + [ + "CMT_FIFO_WR1END1_0", + "CMT_TOP_WR1END1_13" + ], + [ + "CMT_FIFO_L_IMUX26_0", + "CMT_TOP_IMUX26_13" + ], + [ + "CMT_FIFO_L_IMUX41_1", + "CMT_TOP_IMUX41_14" + ], + [ + "CMT_FIFO_WW4A1_0", + "CMT_TOP_WW4A1_13" + ], + [ + "CMT_FIFO_WW4C3_0", + "CMT_TOP_WW4C3_13" + ], + [ + "CMT_FIFO_SW4END3_0", + "CMT_TOP_SW4END3_13" + ], + [ + "CMT_FIFO_L_IMUX0_1", + "CMT_TOP_IMUX0_14" + ], + [ + "CMT_FIFO_L_IMUX25_2", + "CMT_TOP_IMUX25_15" + ], + [ + "CMT_FIFO_MONITOR_P_0", + "CMT_TOP_MONITOR_P_13" + ], + [ + "CMT_FIFO_SE4C1_2", + "CMT_TOP_SE4C1_15" + ], + [ + "CMT_FIFO_L_IMUX45_2", + "CMT_TOP_IMUX45_15" + ], + [ + "CMT_FIFO_WW2END2_1", + "CMT_TOP_WW2END2_14" + ], + [ + "CMT_FIFO_L_IMUX45_0", + "CMT_TOP_IMUX45_13" + ], + [ + "CMT_FIFO_WR1END2_0", + "CMT_TOP_WR1END2_13" + ], + [ + "CMT_FIFO_WW4A2_0", + "CMT_TOP_WW4A2_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_1", + "CMT_TOP_LOGIC_OUTS_L_B19_14" + ], + [ + "CMT_FIFO_NE4BEG0_0", + "CMT_TOP_NE4BEG0_13" + ], + [ + "CMT_FIFO_SW4END2_0", + "CMT_TOP_SW4END2_13" + ], + [ + "CMT_FIFO_L_IMUX27_2", + "CMT_TOP_IMUX27_15" + ], + [ + "CMT_FIFO_NE4C1_0", + "CMT_TOP_NE4C1_13" + ], + [ + "CMT_FIFO_SE4BEG3_1", + "CMT_TOP_SE4BEG3_14" + ], + [ + "CMT_FIFO_LH9_2", + "CMT_TOP_LH9_15" + ], + [ + "CMT_FIFO_LH2_2", + "CMT_TOP_LH2_15" + ], + [ + "CMT_FIFO_WW4C1_0", + "CMT_TOP_WW4C1_13" + ], + [ + "CMT_FIFO_SE4BEG1_1", + "CMT_TOP_SE4BEG1_14" + ], + [ + "CMT_FIFO_SW4A0_2", + "CMT_TOP_SW4A0_15" + ], + [ + "CMT_FIFO_L_IMUX1_2", + "CMT_TOP_IMUX1_15" + ], + [ + "CMT_FIFO_NE4BEG1_2", + "CMT_TOP_NE4BEG1_15" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "CMT_TOP_OCLK_15" + ], + [ + "CMT_FIFO_EE4BEG1_1", + "CMT_TOP_EE4BEG1_14" + ], + [ + "CMT_FIFO_LH7_0", + "CMT_TOP_LH7_13" + ], + [ + "CMT_FIFO_L_IMUX19_2", + "CMT_TOP_IMUX19_15" + ], + [ + "CMT_FIFO_WW2END0_2", + "CMT_TOP_WW2END0_15" + ], + [ + "CMT_FIFO_EE4B1_2", + "CMT_TOP_EE4B1_15" + ], + [ + "CMT_FIFO_L_IMUX35_2", + "CMT_TOP_IMUX35_15" + ], + [ + "CMT_FIFO_MONITOR_P_2", + "CMT_TOP_MONITOR_P_15" + ], + [ + "CMT_FIFO_WW4A1_1", + "CMT_TOP_WW4A1_14" + ], + [ + "CMT_FIFO_L_IMUX6_2", + "CMT_TOP_IMUX6_15" + ], + [ + "CMT_FIFO_ER1BEG1_2", + "CMT_TOP_ER1BEG1_15" + ], + [ + "CMT_FIFO_L_FAN5_1", + "CMT_TOP_FAN5_14" + ], + [ + "CMT_FIFO_L_IMUX37_1", + "CMT_TOP_IMUX37_14" + ], + [ + "CMT_FIFO_NW4END0_0", + "CMT_TOP_NW4END0_13" + ], + [ + "CMT_FIFO_L_IMUX31_0", + "CMT_TOP_IMUX31_13" + ], + [ + "CMT_FIFO_L_IMUX45_1", + "CMT_TOP_IMUX45_14" + ], + [ + "CMT_FIFO_SE2A0_2", + "CMT_TOP_SE2A0_15" + ], + [ + "CMT_FIFO_L_IMUX1_0", + "CMT_TOP_IMUX1_13" + ], + [ + "CMT_FIFO_LH3_1", + "CMT_TOP_LH3_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_2", + "CMT_TOP_LOGIC_OUTS_L_B1_15" + ], + [ + "CMT_FIFO_NE2A3_1", + "CMT_TOP_NE2A3_14" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "CMT_TOP_OCLK_14" + ], + [ + "CMT_FIFO_L_IMUX43_0", + "CMT_TOP_IMUX43_13" + ], + [ + "CMT_FIFO_WW2A1_1", + "CMT_TOP_WW2A1_14" + ], + [ + "CMT_FIFO_EL1BEG2_1", + "CMT_TOP_EL1BEG2_14" + ], + [ + "CMT_FIFO_NE4C1_1", + "CMT_TOP_NE4C1_14" + ], + [ + "CMT_FIFO_L_IMUX13_2", + "CMT_TOP_IMUX13_15" + ], + [ + "CMT_FIFO_L_IMUX6_1", + "CMT_TOP_IMUX6_14" + ], + [ + "CMT_FIFO_L_IMUX32_0", + "CMT_TOP_IMUX32_13" + ], + [ + "CMT_FIFO_SE4C0_1", + "CMT_TOP_SE4C0_14" + ], + [ + "CMT_FIFO_LH5_0", + "CMT_TOP_LH5_13" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "CMT_TOP_ICLK_15" + ], + [ + "CMT_FIFO_L_IMUX16_2", + "CMT_TOP_IMUX16_15" + ], + [ + "CMT_FIFO_SE4C2_1", + "CMT_TOP_SE4C2_14" + ], + [ + "CMT_FIFO_L_IMUX34_2", + "CMT_TOP_IMUX34_15" + ], + [ + "CMT_FIFO_L_BYP2_2", + "CMT_TOP_BYP2_15" + ], + [ + "CMT_FIFO_L_IMUX2_1", + "CMT_TOP_IMUX2_14" + ], + [ + "CMT_FIFO_NW4END1_0", + "CMT_TOP_NW4END1_13" + ], + [ + "CMT_FIFO_L_BYP0_0", + "CMT_TOP_BYP0_13" + ], + [ + "CMT_FIFO_L_IMUX11_2", + "CMT_TOP_IMUX11_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_0", + "CMT_TOP_LOGIC_OUTS_L_B8_13" + ], + [ + "CMT_FIFO_SW4A3_1", + "CMT_TOP_SW4A3_14" + ], + [ + "CMT_FIFO_L_IMUX46_2", + "CMT_TOP_IMUX46_15" + ], + [ + "CMT_FIFO_LH1_1", + "CMT_TOP_LH1_14" + ], + [ + "CMT_FIFO_NE4BEG0_1", + "CMT_TOP_NE4BEG0_14" + ], + [ + "CMT_FIFO_NE4C1_2", + "CMT_TOP_NE4C1_15" + ], + [ + "CMT_FIFO_L_IMUX42_1", + "CMT_TOP_IMUX42_14" + ], + [ + "CMT_FIFO_L_IMUX24_0", + "CMT_TOP_IMUX24_13" + ], + [ + "CMT_FIFO_LH4_1", + "CMT_TOP_LH4_14" + ], + [ + "CMT_FIFO_SW2A0_0", + "CMT_TOP_SW2A0_13" + ], + [ + "CMT_FIFO_NE2A1_0", + "CMT_TOP_NE2A1_13" + ], + [ + "CMT_FIFO_L_IMUX44_1", + "CMT_TOP_IMUX44_14" + ], + [ + "CMT_FIFO_L_IMUX31_2", + "CMT_TOP_IMUX31_15" + ], + [ + "CMT_FIFO_WW2A3_2", + "CMT_TOP_WW2A3_15" + ], + [ + "CMT_FIFO_L_IMUX7_0", + "CMT_TOP_IMUX7_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_1", + "CMT_TOP_LOGIC_OUTS_L_B22_14" + ], + [ + "CMT_FIFO_LH12_1", + "CMT_TOP_LH12_14" + ], + [ + "CMT_FIFO_LH10_2", + "CMT_TOP_LH10_15" + ], + [ + "CMT_FIFO_EE4C2_0", + "CMT_TOP_EE4C2_13" + ], + [ + "CMT_FIFO_WW2A2_2", + "CMT_TOP_WW2A2_15" + ], + [ + "CMT_FIFO_WW2END1_2", + "CMT_TOP_WW2END1_15" + ], + [ + "CMT_FIFO_WW4C3_1", + "CMT_TOP_WW4C3_14" + ], + [ + "CMT_FIFO_NW2A3_1", + "CMT_TOP_NW2A3_14" + ], + [ + "CMT_FIFO_SE2A2_0", + "CMT_TOP_SE2A2_13" + ], + [ + "CMT_FIFO_L_FAN7_1", + "CMT_TOP_FAN7_14" + ], + [ + "CMT_FIFO_L_BYP5_2", + "CMT_TOP_BYP5_15" + ], + [ + "CMT_FIFO_NW4END2_1", + "CMT_TOP_NW4END2_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_0", + "CMT_TOP_LOGIC_OUTS_L_B1_13" + ], + [ + "CMT_FIFO_EE2BEG2_2", + "CMT_TOP_EE2BEG2_15" + ], + [ + "CMT_FIFO_L_IMUX22_1", + "CMT_TOP_IMUX22_14" + ], + [ + "CMT_FIFO_SE4C1_1", + "CMT_TOP_SE4C1_14" + ], + [ + "CMT_FIFO_SE2A3_2", + "CMT_TOP_SE2A3_15" + ], + [ + "CMT_FIFO_L_BYP4_2", + "CMT_TOP_BYP4_15" + ], + [ + "CMT_FIFO_WW4C0_1", + "CMT_TOP_WW4C0_14" + ], + [ + "CMT_FIFO_WL1END0_0", + "CMT_TOP_WL1END0_13" + ], + [ + "CMT_FIFO_WW4END3_1", + "CMT_TOP_WW4END3_14" + ], + [ + "CMT_FIFO_LH9_1", + "CMT_TOP_LH9_14" + ], + [ + "CMT_FIFO_WR1END3_1", + "CMT_TOP_WR1END3_14" + ], + [ + "CMT_FIFO_L_IMUX35_0", + "CMT_TOP_IMUX35_13" + ], + [ + "CMT_FIFO_L_IMUX35_1", + "CMT_TOP_IMUX35_14" + ], + [ + "CMT_FIFO_L_IMUX22_2", + "CMT_TOP_IMUX22_15" + ], + [ + "CMT_FIFO_NE4BEG3_2", + "CMT_TOP_NE4BEG3_15" + ], + [ + "CMT_FIFO_NE2A3_2", + "CMT_TOP_NE2A3_15" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "CMT_TOP_ICLK_13" + ], + [ + "CMT_FIFO_WW4C1_2", + "CMT_TOP_WW4C1_15" + ], + [ + "CMT_FIFO_L_IMUX29_0", + "CMT_TOP_IMUX29_13" + ], + [ + "CMT_FIFO_NW4A0_2", + "CMT_TOP_NW4A0_15" + ], + [ + "CMT_FIFO_EL1BEG1_2", + "CMT_TOP_EL1BEG1_15" + ], + [ + "CMT_FIFO_SW4END3_1", + "CMT_TOP_SW4END3_14" + ], + [ + "CMT_FIFO_SW4A0_0", + "CMT_TOP_SW4A0_13" + ], + [ + "CMT_FIFO_L_FAN3_1", + "CMT_TOP_FAN3_14" + ], + [ + "CMT_FIFO_WW4A1_2", + "CMT_TOP_WW4A1_15" + ], + [ + "CMT_FIFO_LH5_1", + "CMT_TOP_LH5_14" + ], + [ + "CMT_FIFO_L_FAN5_2", + "CMT_TOP_FAN5_15" + ], + [ + "CMT_FIFO_L_CTRL0_0", + "CMT_TOP_CTRL0_13" + ], + [ + "CMT_FIFO_L_IMUX40_1", + "CMT_TOP_IMUX40_14" + ], + [ + "CMT_FIFO_L_BYP4_0", + "CMT_TOP_BYP4_13" + ], + [ + "CMT_FIFO_L_IMUX25_1", + "CMT_TOP_IMUX25_14" + ], + [ + "CMT_FIFO_SE4C2_2", + "CMT_TOP_SE4C2_15" + ], + [ + "CMT_FIFO_L_BYP5_1", + "CMT_TOP_BYP5_14" + ], + [ + "CMT_FIFO_EE2BEG3_2", + "CMT_TOP_EE2BEG3_15" + ], + [ + "CMT_FIFO_ER1BEG3_2", + "CMT_TOP_ER1BEG3_15" + ], + [ + "CMT_FIFO_SW4A3_0", + "CMT_TOP_SW4A3_13" + ], + [ + "CMT_FIFO_L_IMUX20_2", + "CMT_TOP_IMUX20_15" + ], + [ + "CMT_FIFO_L_IMUX39_1", + "CMT_TOP_IMUX39_14" + ], + [ + "CMT_FIFO_L_IMUX30_2", + "CMT_TOP_IMUX30_15" + ], + [ + "CMT_FIFO_SW4A2_1", + "CMT_TOP_SW4A2_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_2", + "CMT_TOP_LOGIC_OUTS_L_B19_15" + ], + [ + "CMT_FIFO_EE4C0_2", + "CMT_TOP_EE4C0_15" + ], + [ + "CMT_FIFO_WW2A0_1", + "CMT_TOP_WW2A0_14" + ], + [ + "CMT_FIFO_L_FAN7_0", + "CMT_TOP_FAN7_13" + ], + [ + "CMT_FIFO_EE4A3_0", + "CMT_TOP_EE4A3_13" + ], + [ + "CMT_FIFO_EE4B1_0", + "CMT_TOP_EE4B1_13" + ], + [ + "CMT_FIFO_EE4B0_1", + "CMT_TOP_EE4B0_14" + ], + [ + "CMT_FIFO_WW4END1_0", + "CMT_TOP_WW4END1_13" + ], + [ + "CMT_FIFO_L_IMUX4_1", + "CMT_TOP_IMUX4_14" + ], + [ + "CMT_FIFO_SW4A3_2", + "CMT_TOP_SW4A3_15" + ], + [ + "CMT_FIFO_SW2A1_2", + "CMT_TOP_SW2A1_15" + ], + [ + "CMT_FIFO_EE4BEG0_0", + "CMT_TOP_EE4BEG0_13" + ], + [ + "CMT_FIFO_LH3_0", + "CMT_TOP_LH3_13" + ], + [ + "CMT_FIFO_NW4A2_2", + "CMT_TOP_NW4A2_15" + ], + [ + "CMT_FIFO_L_IMUX10_0", + "CMT_TOP_IMUX10_13" + ], + [ + "CMT_FIFO_SE2A3_0", + "CMT_TOP_SE2A3_13" + ], + [ + "CMT_FIFO_WW4END3_0", + "CMT_TOP_WW4END3_13" + ], + [ + "CMT_FIFO_EE2A3_2", + "CMT_TOP_EE2A3_15" + ], + [ + "CMT_FIFO_NE2A1_2", + "CMT_TOP_NE2A1_15" + ], + [ + "CMT_FIFO_WW4C3_2", + "CMT_TOP_WW4C3_15" + ], + [ + "CMT_FIFO_EE2A3_1", + "CMT_TOP_EE2A3_14" + ], + [ + "CMT_FIFO_SW2A0_1", + "CMT_TOP_SW2A0_14" + ], + [ + "CMT_FIFO_WL1END3_1", + "CMT_TOP_WL1END3_14" + ], + [ + "CMT_FIFO_WW2END0_0", + "CMT_TOP_WW2END0_13" + ], + [ + "CMT_FIFO_NE4C3_1", + "CMT_TOP_NE4C3_14" + ], + [ + "CMT_FIFO_WW4END2_0", + "CMT_TOP_WW4END2_13" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "CMT_TOP_ICLKDIV_14" + ], + [ + "CMT_FIFO_L_IMUX38_2", + "CMT_TOP_IMUX38_15" + ], + [ + "CMT_FIFO_L_IMUX15_2", + "CMT_TOP_IMUX15_15" + ], + [ + "CMT_FIFO_L_BYP0_2", + "CMT_TOP_BYP0_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_0", + "CMT_TOP_LOGIC_OUTS_L_B11_13" + ], + [ + "CMT_FIFO_NE4BEG2_1", + "CMT_TOP_NE4BEG2_14" + ], + [ + "CMT_FIFO_EE4BEG3_1", + "CMT_TOP_EE4BEG3_14" + ], + [ + "CMT_FIFO_EE4B3_0", + "CMT_TOP_EE4B3_13" + ], + [ + "CMT_FIFO_L_CLK1_0", + "CMT_TOP_CLK1_13" + ], + [ + "CMT_FIFO_WW4B0_0", + "CMT_TOP_WW4B0_13" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "CMT_TOP_ICLKDIV_15" + ], + [ + "CMT_FIFO_ER1BEG2_2", + "CMT_TOP_ER1BEG2_15" + ], + [ + "CMT_FIFO_L_IMUX43_1", + "CMT_TOP_IMUX43_14" + ], + [ + "CMT_FIFO_L_BYP3_2", + "CMT_TOP_BYP3_15" + ], + [ + "CMT_FIFO_WR1END2_2", + "CMT_TOP_WR1END2_15" + ], + [ + "CMT_FIFO_EE2BEG1_1", + "CMT_TOP_EE2BEG1_14" + ], + [ + "CMT_FIFO_L_FAN1_0", + "CMT_TOP_FAN1_13" + ], + [ + "CMT_FIFO_L_IMUX19_0", + "CMT_TOP_IMUX19_13" + ], + [ + "CMT_FIFO_L_IMUX30_0", + "CMT_TOP_IMUX30_13" + ], + [ + "CMT_FIFO_WW4END0_1", + "CMT_TOP_WW4END0_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_1", + "CMT_TOP_LOGIC_OUTS_L_B8_14" + ], + [ + "CMT_FIFO_L_IMUX41_0", + "CMT_TOP_IMUX41_13" + ], + [ + "CMT_FIFO_L_IMUX37_0", + "CMT_TOP_IMUX37_13" + ], + [ + "CMT_FIFO_LH4_0", + "CMT_TOP_LH4_13" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "CMT_TOP_OCLK_13" + ], + [ + "CMT_FIFO_ER1BEG3_1", + "CMT_TOP_ER1BEG3_14" + ], + [ + "CMT_FIFO_L_IMUX34_1", + "CMT_TOP_IMUX34_14" + ], + [ + "CMT_FIFO_L_IMUX5_0", + "CMT_TOP_IMUX5_13" + ], + [ + "CMT_FIFO_SW2A3_0", + "CMT_TOP_SW2A3_13" + ], + [ + "CMT_FIFO_L_IMUX13_1", + "CMT_TOP_IMUX13_14" + ], + [ + "CMT_FIFO_SW2A1_0", + "CMT_TOP_SW2A1_13" + ], + [ + "CMT_FIFO_L_IMUX46_0", + "CMT_TOP_IMUX46_13" + ], + [ + "CMT_FIFO_EE2BEG1_0", + "CMT_TOP_EE2BEG1_13" + ], + [ + "CMT_FIFO_LH9_0", + "CMT_TOP_LH9_13" + ], + [ + "CMT_FIFO_WW4B1_0", + "CMT_TOP_WW4B1_13" + ], + [ + "CMT_FIFO_SE2A1_2", + "CMT_TOP_SE2A1_15" + ], + [ + "CMT_FIFO_L_IMUX9_2", + "CMT_TOP_IMUX9_15" + ], + [ + "CMT_FIFO_LH3_2", + "CMT_TOP_LH3_15" + ], + [ + "CMT_FIFO_L_IMUX12_1", + "CMT_TOP_IMUX12_14" + ], + [ + "CMT_FIFO_NE2A0_1", + "CMT_TOP_NE2A0_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_1", + "CMT_TOP_LOGIC_OUTS_L_B12_14" + ], + [ + "CMT_FIFO_WW4A0_2", + "CMT_TOP_WW4A0_15" + ], + [ + "CMT_FIFO_NW4A1_1", + "CMT_TOP_NW4A1_14" + ], + [ + "CMT_FIFO_SE2A0_0", + "CMT_TOP_SE2A0_13" + ], + [ + "CMT_FIFO_LH10_0", + "CMT_TOP_LH10_13" + ], + [ + "CMT_FIFO_L_IMUX14_0", + "CMT_TOP_IMUX14_13" + ], + [ + "CMT_FIFO_LH8_1", + "CMT_TOP_LH8_14" + ], + [ + "CMT_FIFO_NW2A3_2", + "CMT_TOP_NW2A3_15" + ], + [ + "CMT_FIFO_ER1BEG2_0", + "CMT_TOP_ER1BEG2_13" + ], + [ + "CMT_FIFO_WW4END0_0", + "CMT_TOP_WW4END0_13" + ], + [ + "CMT_FIFO_L_FAN5_0", + "CMT_TOP_FAN5_13" + ], + [ + "CMT_FIFO_L_FAN0_0", + "CMT_TOP_FAN0_13" + ], + [ + "CMT_FIFO_EL1BEG3_0", + "CMT_TOP_EL1BEG3_13" + ], + [ + "CMT_FIFO_L_IMUX44_0", + "CMT_TOP_IMUX44_13" + ], + [ + "CMT_FIFO_L_FAN2_2", + "CMT_TOP_FAN2_15" + ], + [ + "CMT_FIFO_WW4END3_2", + "CMT_TOP_WW4END3_15" + ], + [ + "CMT_FIFO_LH6_2", + "CMT_TOP_LH6_15" + ], + [ + "CMT_FIFO_L_BYP7_1", + "CMT_TOP_BYP7_14" + ], + [ + "CMT_FIFO_L_CLK0_0", + "CMT_TOP_CLK0_13" + ], + [ + "CMT_FIFO_L_IMUX36_2", + "CMT_TOP_IMUX36_15" + ], + [ + "CMT_FIFO_L_IMUX4_0", + "CMT_TOP_IMUX4_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_0", + "CMT_TOP_LOGIC_OUTS_L_B22_13" + ], + [ + "CMT_FIFO_L_IMUX14_1", + "CMT_TOP_IMUX14_14" + ], + [ + "CMT_FIFO_L_IMUX5_1", + "CMT_TOP_IMUX5_14" + ], + [ + "CMT_FIFO_EE4C3_1", + "CMT_TOP_EE4C3_14" + ], + [ + "CMT_FIFO_L_IMUX21_2", + "CMT_TOP_IMUX21_15" + ], + [ + "CMT_FIFO_L_IMUX23_1", + "CMT_TOP_IMUX23_14" + ], + [ + "CMT_FIFO_L_IMUX10_1", + "CMT_TOP_IMUX10_14" + ], + [ + "CMT_FIFO_L_IMUX17_1", + "CMT_TOP_IMUX17_14" + ], + [ + "CMT_FIFO_NW2A0_0", + "CMT_TOP_NW2A0_13" + ], + [ + "CMT_FIFO_EE2BEG3_0", + "CMT_TOP_EE2BEG3_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_2", + "CMT_TOP_LOGIC_OUTS_L_B0_15" + ], + [ + "CMT_FIFO_EL1BEG3_1", + "CMT_TOP_EL1BEG3_14" + ], + [ + "CMT_FIFO_EE4C3_0", + "CMT_TOP_EE4C3_13" + ], + [ + "CMT_FIFO_WW4B2_1", + "CMT_TOP_WW4B2_14" + ], + [ + "CMT_FIFO_L_FAN2_0", + "CMT_TOP_FAN2_13" + ], + [ + "CMT_FIFO_L_IMUX37_2", + "CMT_TOP_IMUX37_15" + ], + [ + "CMT_FIFO_L_IMUX42_0", + "CMT_TOP_IMUX42_13" + ], + [ + "CMT_FIFO_EL1BEG2_2", + "CMT_TOP_EL1BEG2_15" + ], + [ + "CMT_FIFO_L_IMUX18_0", + "CMT_TOP_IMUX18_13" + ], + [ + "CMT_FIFO_ER1BEG2_1", + "CMT_TOP_ER1BEG2_14" + ], + [ + "CMT_FIFO_EE4C2_1", + "CMT_TOP_EE4C2_14" + ], + [ + "CMT_FIFO_L_IMUX28_0", + "CMT_TOP_IMUX28_13" + ], + [ + "CMT_FIFO_EE2A1_1", + "CMT_TOP_EE2A1_14" + ], + [ + "CMT_FIFO_L_BYP4_1", + "CMT_TOP_BYP4_14" + ], + [ + "CMT_FIFO_ER1BEG0_1", + "CMT_TOP_ER1BEG0_14" + ], + [ + "CMT_FIFO_L_FAN4_0", + "CMT_TOP_FAN4_13" + ], + [ + "CMT_FIFO_NW4END1_2", + "CMT_TOP_NW4END1_15" + ], + [ + "CMT_FIFO_WL1END2_2", + "CMT_TOP_WL1END2_15" + ], + [ + "CMT_FIFO_NW4A2_0", + "CMT_TOP_NW4A2_13" + ], + [ + "CMT_FIFO_L_BYP6_0", + "CMT_TOP_BYP6_13" + ], + [ + "CMT_FIFO_L_IMUX4_2", + "CMT_TOP_IMUX4_15" + ], + [ + "CMT_FIFO_L_IMUX26_2", + "CMT_TOP_IMUX26_15" + ], + [ + "CMT_FIFO_NW2A1_0", + "CMT_TOP_NW2A1_13" + ], + [ + "CMT_FIFO_EE2BEG0_2", + "CMT_TOP_EE2BEG0_15" + ], + [ + "CMT_FIFO_L_CLK0_1", + "CMT_TOP_CLK0_14" + ], + [ + "CMT_FIFO_WW2END3_0", + "CMT_TOP_WW2END3_13" + ], + [ + "CMT_FIFO_WW2A0_0", + "CMT_TOP_WW2A0_13" + ], + [ + "CMT_FIFO_SW4END2_1", + "CMT_TOP_SW4END2_14" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "CMT_TOP_R_LOWER_B" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_IOI_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_IOI_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_IOI_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_IOI_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_IOI_IOCLK_PLL3", + "HCLK_TERM_PERFCLK3" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_IOI_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_IOI_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_IOI_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_IOI_IOCLK_PLL1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_IOI_I2IOCLK_TOP0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_IOI_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_IOI_IOCLK_PLL0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_IOI_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_IOI_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_IOI_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_IOI_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_IOI_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_IOI_I2IOCLK_BOT0", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_IOI_IOCLK_PLL2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_IOI_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_IOI_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_IOI_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ] + ], + "tile_types": [ + "HCLK_IOI", + "HCLK_TERM" + ] + }, + { + "grid_deltas": [ + 5, + -3 + ], + "wire_pairs": [ + [ + "PCIE_WW4C3_13", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_WL1END2_13", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_BYP0_L_13", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_NE2A3_13", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_WL1END1_13", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_WW4C0_13", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_SE4BEG2_13", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_EL1BEG2_13", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_IMUX26_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_MONITOR_N_13", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_BYP7_L_13", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_EE4A2_13", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_LH5_13", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_LH1_13", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_EE4B0_13", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX24_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_SW4A2_13", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_WW4B0_13", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_WW4B1_13", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_FAN2_L_13", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_IMUX0_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_LH2_13", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_EE2A3_13", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_IMUX1_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_IMUX29_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_WW4END1_13", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_IMUX6_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_LH6_13", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_IMUX20_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_CTRL1_L_13", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_NW4A3_13", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_EE4BEG0_13", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX8_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_IMUX36_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_IMUX23_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_IMUX9_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_SW2A1_13", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_SE2A1_13", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_WW2END2_13", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_CTRL0_L_13", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_LH4_13", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_IMUX13_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_IMUX43_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_EE4A3_13", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_EE2A0_13", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_IMUX46_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_WW4END3_13", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_WW2A1_13", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_SE2A2_13", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_IMUX3_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_IMUX39_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_FAN1_L_13", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_FAN3_L_13", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX28_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_NW4END0_13", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_EE4B3_13", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_EE2A2_13", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_EE4BEG3_13", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_EE4C0_13", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX15_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_NW2A2_13", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_IMUX38_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_NW2A1_13", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_WW2A2_13", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_EE4A1_13", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_WW2A0_13", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_IMUX18_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_WW4A0_13", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_NW2A3_13", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_NW4END2_13", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_IMUX2_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_SE4BEG3_13", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_EE4BEG1_13", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_NE2A0_13", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_IMUX31_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_NE4C0_13", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_IMUX11_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_BYP4_L_13", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_WR1END2_13", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_IMUX5_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_LH8_13", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4C3_13", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_SE4C3_13", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_CLK0_L_13", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_FAN5_L_13", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_FAN0_L_13", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_SW4A0_13", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_EL1BEG3_13", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_NW4END3_13", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_LH11_13", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_ER1BEG3_13", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_EE2BEG2_13", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_BYP1_L_13", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_FAN6_L_13", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_NW4A1_13", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_IMUX10_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_IMUX30_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_EE4B2_13", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_IMUX37_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_LH10_13", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_IMUX44_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_IMUX33_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_EE4C2_13", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_NE4C1_13", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_NW4END1_13", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_SW4END1_13", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_EL1BEG1_13", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_BYP2_L_13", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_SE4C1_13", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_EE4C1_13", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_WW4B3_13", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_WW4C2_13", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_EE4BEG2_13", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_ER1BEG1_13", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_NE4BEG1_13", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_SE4C0_13", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_ER1BEG2_13", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_IMUX25_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_WW4A1_13", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_WR1END1_13", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_BYP3_L_13", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_BYP5_L_13", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_BYP6_L_13", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_WW2END1_13", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_LH9_13", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_MONITOR_P_13", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_IMUX12_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_NE2A1_13", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_SE4BEG0_13", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_WR1END0_13", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_IMUX35_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_NW2A0_13", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_SW4END0_13", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_SE2A0_13", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_FAN4_L_13", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_SE4BEG1_13", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_IMUX22_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_IMUX21_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_IMUX32_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_WR1END3_13", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_WW4B2_13", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_IMUX19_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_SW2A3_13", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_SW2A0_13", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_SW4A3_13", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_SE2A3_13", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_SE4C2_13", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_NW4A0_13", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WL1END3_13", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_IMUX41_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_SW4A1_13", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_SW4END3_13", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_WW4C1_13", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_EE4B1_13", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_IMUX17_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_SW4END2_13", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_IMUX47_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_EE2BEG0_13", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_IMUX7_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_EE2A1_13", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_CLK1_L_13", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_NE4C3_13", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_SW2A2_13", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_IMUX42_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_EE2BEG1_13", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_IMUX16_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_IMUX40_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_NW4A2_13", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_EE4A0_13", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_NE2A2_13", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_WW4A3_13", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_LH12_13", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_WW2END0_13", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_NE4BEG3_13", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_WW4A2_13", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_FAN7_L_13", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_WW2A3_13", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_EE2BEG3_13", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_NE4BEG0_13", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_IMUX27_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_EL1BEG0_13", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_WW2END3_13", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_IMUX14_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_LH3_13", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_LH7_13", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_WL1END0_13", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_WW4END2_13", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_ER1BEG0_13", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_13", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_NE4C2_13", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_WW4END0_13", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_IMUX45_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_IMUX4_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_NE4BEG2_13", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_IMUX34_L_13", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + -6 + ], + "wire_pairs": [ + [ + "CLK_PMV_EL1BEG0_6", + "VBRK_EL1BEG0" + ], + [ + "CLK_PMV_EE2A1_6", + "VBRK_EE2A1" + ], + [ + "CLK_PMV_EE2BEG3_6", + "VBRK_EE2BEG3" + ], + [ + "CLK_PMV_MONITOR_P_6", + "VBRK_MONITOR_P" + ], + [ + "CLK_PMV_WR1END2_6", + "VBRK_WR1END2" + ], + [ + "CLK_PMV_MONITOR_N_6", + "VBRK_MONITOR_N" + ], + [ + "CLK_PMV_LH10_6", + "VBRK_LH10" + ], + [ + "CLK_PMV_SW4END1_6", + "VBRK_SW4END1" + ], + [ + "CLK_PMV_WW2A2_6", + "VBRK_WW2A2" + ], + [ + "CLK_PMV_NE4C3_6", + "VBRK_NE4C3" + ], + [ + "CLK_PMV_EE2BEG0_6", + "VBRK_EE2BEG0" + ], + [ + "CLK_PMV_NE4C2_6", + "VBRK_NE4C2" + ], + [ + "CLK_PMV_EE4A3_6", + "VBRK_EE4A3" + ], + [ + "CLK_PMV_SE4C0_6", + "VBRK_SE4C0" + ], + [ + "CLK_PMV_EE4A0_6", + "VBRK_EE4A0" + ], + [ + "CLK_PMV_SE4C2_6", + "VBRK_SE4C2" + ], + [ + "CLK_PMV_SE2A1_6", + "VBRK_SE2A1" + ], + [ + "CLK_PMV_NW4A0_6", + "VBRK_NW4A0" + ], + [ + "CLK_PMV_WW2A3_6", + "VBRK_WW2A3" + ], + [ + "CLK_PMV_SW2A1_6", + "VBRK_SW2A1" + ], + [ + "CLK_PMV_NW4A1_6", + "VBRK_NW4A1" + ], + [ + "CLK_PMV_EE4B3_6", + "VBRK_EE4B3" + ], + [ + "CLK_PMV_EE4B2_6", + "VBRK_EE4B2" + ], + [ + "CLK_PMV_EE4B0_6", + "VBRK_EE4B0" + ], + [ + "CLK_PMV_EE4A1_6", + "VBRK_EE4A1" + ], + [ + "CLK_PMV_EE4BEG0_6", + "VBRK_EE4BEG0" + ], + [ + "CLK_PMV_ER1BEG1_6", + "VBRK_ER1BEG1" + ], + [ + "CLK_PMV_WW4END2_6", + "VBRK_WW4END2" + ], + [ + "CLK_PMV_SW4END2_6", + "VBRK_SW4END2" + ], + [ + "CLK_PMV_SE2A3_6", + "VBRK_SE2A3" + ], + [ + "CLK_PMV_LH7_6", + "VBRK_LH7" + ], + [ + "CLK_PMV_EE2BEG2_6", + "VBRK_EE2BEG2" + ], + [ + "CLK_PMV_EE4C2_6", + "VBRK_EE4C2" + ], + [ + "CLK_PMV_SE4BEG0_6", + "VBRK_SE4BEG0" + ], + [ + "CLK_PMV_SE2A0_6", + "VBRK_SE2A0" + ], + [ + "CLK_PMV_NW4END3_6", + "VBRK_NW4END3" + ], + [ + "CLK_PMV_NW2A1_6", + "VBRK_NW2A1" + ], + [ + "CLK_PMV_SW4A0_6", + "VBRK_SW4A0" + ], + [ + "CLK_PMV_WW4END1_6", + "VBRK_WW4END1" + ], + [ + "CLK_PMV_NE2A1_6", + "VBRK_NE2A1" + ], + [ + "CLK_PMV_WW4B3_6", + "VBRK_WW4B3" + ], + [ + "CLK_PMV_NW2A0_6", + "VBRK_NW2A0" + ], + [ + "CLK_PMV_WL1END0_6", + "VBRK_WL1END0" + ], + [ + "CLK_PMV_SE4C3_6", + "VBRK_SE4C3" + ], + [ + "CLK_PMV_WW4END3_6", + "VBRK_WW4END3" + ], + [ + "CLK_PMV_LH9_6", + "VBRK_LH9" + ], + [ + "CLK_PMV_NE2A3_6", + "VBRK_NE2A3" + ], + [ + "CLK_PMV_NE4C1_6", + "VBRK_NE4C1" + ], + [ + "CLK_PMV_SW4A1_6", + "VBRK_SW4A1" + ], + [ + "CLK_PMV_WW4C0_6", + "VBRK_WW4C0" + ], + [ + "CLK_PMV_NE4BEG3_6", + "VBRK_NE4BEG3" + ], + [ + "CLK_PMV_WW4A2_6", + "VBRK_WW4A2" + ], + [ + "CLK_PMV_SW2A3_6", + "VBRK_SW2A3" + ], + [ + "CLK_PMV_WW2END3_6", + "VBRK_WW2END3" + ], + [ + "CLK_PMV_WW4END0_6", + "VBRK_WW4END0" + ], + [ + "CLK_PMV_NW2A3_6", + "VBRK_NW2A3" + ], + [ + "CLK_PMV_EE4BEG1_6", + "VBRK_EE4BEG1" + ], + [ + "CLK_PMV_SE4BEG1_6", + "VBRK_SE4BEG1" + ], + [ + "CLK_PMV_WL1END1_6", + "VBRK_WL1END1" + ], + [ + "CLK_PMV_SW4A3_6", + "VBRK_SW4A3" + ], + [ + "CLK_PMV_WW2END1_6", + "VBRK_WW2END1" + ], + [ + "CLK_PMV_EE4BEG2_6", + "VBRK_EE4BEG2" + ], + [ + "CLK_PMV_WW2A1_6", + "VBRK_WW2A1" + ], + [ + "CLK_PMV_EE2A3_6", + "VBRK_EE2A3" + ], + [ + "CLK_PMV_NW4A2_6", + "VBRK_NW4A2" + ], + [ + "CLK_PMV_EE2BEG1_6", + "VBRK_EE2BEG1" + ], + [ + "CLK_PMV_NE4BEG2_6", + "VBRK_NE4BEG2" + ], + [ + "CLK_PMV_WW2END0_6", + "VBRK_WW2END0" + ], + [ + "CLK_PMV_WW2A0_6", + "VBRK_WW2A0" + ], + [ + "CLK_PMV_LH6_6", + "VBRK_LH6" + ], + [ + "CLK_PMV_SW4END0_6", + "VBRK_SW4END0" + ], + [ + "CLK_PMV_NW4END0_6", + "VBRK_NW4END0" + ], + [ + "CLK_PMV_LH2_6", + "VBRK_LH2" + ], + [ + "CLK_PMV_WR1END3_6", + "VBRK_WR1END3" + ], + [ + "CLK_PMV_LH11_6", + "VBRK_LH11" + ], + [ + "CLK_PMV_EL1BEG1_6", + "VBRK_EL1BEG1" + ], + [ + "CLK_PMV_NW4END2_6", + "VBRK_NW4END2" + ], + [ + "CLK_PMV_WW4C3_6", + "VBRK_WW4C3" + ], + [ + "CLK_PMV_EE2A0_6", + "VBRK_EE2A0" + ], + [ + "CLK_PMV_SW2A2_6", + "VBRK_SW2A2" + ], + [ + "CLK_PMV_NW4END1_6", + "VBRK_NW4END1" + ], + [ + "CLK_PMV_EE4BEG3_6", + "VBRK_EE4BEG3" + ], + [ + "CLK_PMV_NE4BEG1_6", + "VBRK_NE4BEG1" + ], + [ + "CLK_PMV_EL1BEG3_6", + "VBRK_EL1BEG3" + ], + [ + "CLK_PMV_WW2END2_6", + "VBRK_WW2END2" + ], + [ + "CLK_PMV_SW2A0_6", + "VBRK_SW2A0" + ], + [ + "CLK_PMV_EE4B1_6", + "VBRK_EE4B1" + ], + [ + "CLK_PMV_EE4A2_6", + "VBRK_EE4A2" + ], + [ + "CLK_PMV_WW4C2_6", + "VBRK_WW4C2" + ], + [ + "CLK_PMV_WR1END0_6", + "VBRK_WR1END0" + ], + [ + "CLK_PMV_ER1BEG0_6", + "VBRK_ER1BEG0" + ], + [ + "CLK_PMV_EE4C1_6", + "VBRK_EE4C1" + ], + [ + "CLK_PMV_LH1_6", + "VBRK_LH1" + ], + [ + "CLK_PMV_WL1END2_6", + "VBRK_WL1END2" + ], + [ + "CLK_PMV_SE2A2_6", + "VBRK_SE2A2" + ], + [ + "CLK_PMV_WW4A3_6", + "VBRK_WW4A3" + ], + [ + "CLK_PMV_NE4C0_6", + "VBRK_NE4C0" + ], + [ + "CLK_PMV_NW4A3_6", + "VBRK_NW4A3" + ], + [ + "CLK_PMV_WR1END1_6", + "VBRK_WR1END1" + ], + [ + "CLK_PMV_LH3_6", + "VBRK_LH3" + ], + [ + "CLK_PMV_SE4BEG3_6", + "VBRK_SE4BEG3" + ], + [ + "CLK_PMV_LH8_6", + "VBRK_LH8" + ], + [ + "CLK_PMV_NW2A2_6", + "VBRK_NW2A2" + ], + [ + "CLK_PMV_SW4A2_6", + "VBRK_SW4A2" + ], + [ + "CLK_PMV_ER1BEG2_6", + "VBRK_ER1BEG2" + ], + [ + "CLK_PMV_WW4A1_6", + "VBRK_WW4A1" + ], + [ + "CLK_PMV_LH4_6", + "VBRK_LH4" + ], + [ + "CLK_PMV_SW4END3_6", + "VBRK_SW4END3" + ], + [ + "CLK_PMV_EE2A2_6", + "VBRK_EE2A2" + ], + [ + "CLK_PMV_WW4A0_6", + "VBRK_WW4A0" + ], + [ + "CLK_PMV_WW4B1_6", + "VBRK_WW4B1" + ], + [ + "CLK_PMV_ER1BEG3_6", + "VBRK_ER1BEG3" + ], + [ + "CLK_PMV_SE4BEG2_6", + "VBRK_SE4BEG2" + ], + [ + "CLK_PMV_LH12_6", + "VBRK_LH12" + ], + [ + "CLK_PMV_NE2A0_6", + "VBRK_NE2A0" + ], + [ + "CLK_PMV_NE2A2_6", + "VBRK_NE2A2" + ], + [ + "CLK_PMV_WW4B0_6", + "VBRK_WW4B0" + ], + [ + "CLK_PMV_LH5_6", + "VBRK_LH5" + ], + [ + "CLK_PMV_WW4C1_6", + "VBRK_WW4C1" + ], + [ + "CLK_PMV_NE4BEG0_6", + "VBRK_NE4BEG0" + ], + [ + "CLK_PMV_SE4C1_6", + "VBRK_SE4C1" + ], + [ + "CLK_PMV_EE4C3_6", + "VBRK_EE4C3" + ], + [ + "CLK_PMV_EL1BEG2_6", + "VBRK_EL1BEG2" + ], + [ + "CLK_PMV_WW4B2_6", + "VBRK_WW4B2" + ], + [ + "CLK_PMV_EE4C0_6", + "VBRK_EE4C0" + ], + [ + "CLK_PMV_WL1END3_6", + "VBRK_WL1END3" + ] + ], + "tile_types": [ + "CLK_PMV", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 7 + ], + "wire_pairs": [ + [ + "CFG_CENTER_IMUX2_4", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_SE4BEG2_4", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_WW2A2_4", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_CTRL0_4", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX28_4", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_EL1BEG3_4", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_EE4A0_4", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B11_4", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "CFG_CENTER_LH4_4", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_IMUX26_4", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_BYP5_4", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_WW4C2_4", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX21_4", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_SW2A2_4", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_IMUX17_4", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX1_4", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_SE4BEG3_4", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_SW4A0_4", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_EE4A1_4", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_EE4BEG2_4", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX39_4", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_IMUX4_4", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX40_4", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_EE2BEG2_4", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_SW4A1_4", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_LH9_4", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EE2A3_4", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B9_4", + "VFRAME_LOGIC_OUTS_B9" + ], + [ + "CFG_CENTER_IMUX6_4", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_NW4A3_4", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_NE4C2_4", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_SE4BEG1_4", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE4B0_4", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_NE2A1_4", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_EE4C3_4", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_NE2A0_4", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_SW2A3_4", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_IMUX35_4", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_FAN1_4", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_NE4C3_4", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_EE4A3_4", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_CLK0_4", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_EE2BEG1_4", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_SE4C2_4", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WW2A1_4", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_BYP6_4", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_NW4A0_4", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NE2A2_4", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_SE2A1_4", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NW4A1_4", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_BYP2_4", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_4", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_FAN3_4", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_IMUX19_4", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_WL1END1_4", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_WW4B1_4", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_ER1BEG1_4", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_IMUX9_4", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_EE4BEG0_4", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_WL1END3_4", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_BYP1_4", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WR1END2_4", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_WW4B2_4", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_BYP7_4", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_SE2A2_4", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX14_4", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_NW4END2_4", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_EE4C2_4", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_WW4B3_4", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_NW2A3_4", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_IMUX0_4", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_IMUX43_4", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX5_4", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX32_4", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_LH5_4", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX46_4", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B8_4", + "VFRAME_LOGIC_OUTS_B8" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_4", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_SE4C1_4", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_EE4B3_4", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_IMUX44_4", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WL1END0_4", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_IMUX31_4", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_IMUX41_4", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_WW2A3_4", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_WW4A1_4", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_SW4A3_4", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EL1BEG2_4", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX12_4", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_WR1END1_4", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_FAN7_4", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX10_4", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_WW4A3_4", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_NE4C1_4", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_ER1BEG0_4", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_NE4BEG0_4", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_ER1BEG2_4", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_WR1END3_4", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_WW2END3_4", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_EL1BEG0_4", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_SE4BEG0_4", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_IMUX24_4", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_SW2A0_4", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_WW2END1_4", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_FAN4_4", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_EE2A1_4", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_LH10_4", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_4", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_CTRL1_4", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_BYP0_4", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_4", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_SE2A0_4", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_4", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_WW4A2_4", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_EE4C1_4", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_EE4B1_4", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_IMUX15_4", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_LH3_4", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_WW4A0_4", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_LH11_4", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_LH7_4", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_NE2A3_4", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_WW4C0_4", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_NW2A2_4", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_SW4END1_4", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_NE4BEG3_4", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX7_4", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_WW2END2_4", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_IMUX3_4", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_FAN5_4", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_ER1BEG3_4", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_BYP4_4", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_IMUX37_4", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SE4C0_4", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_SE4C3_4", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_LH1_4", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NW2A0_4", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_4", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_FAN0_4", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX11_4", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_LH6_4", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX8_4", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_IMUX36_4", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_EE4BEG1_4", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_LH2_4", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EE4B2_4", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX45_4", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX27_4", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_EE4A2_4", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_EE2BEG3_4", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX13_4", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_SW4END2_4", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_IMUX42_4", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX38_4", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_FAN6_4", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_EE2BEG0_4", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_EE2A0_4", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_SW4END3_4", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_CLK1_4", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_EE2A2_4", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_EE4C0_4", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_NW2A1_4", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_NE4C0_4", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE4BEG3_4", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_WW2A0_4", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_NW4END0_4", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_SW4END0_4", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_NW4A2_4", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_IMUX18_4", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX25_4", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_4", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_NW4END1_4", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_WW4END2_4", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_SW2A1_4", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WR1END0_4", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_WL1END2_4", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_FAN2_4", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_WW4B0_4", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_4", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_LH8_4", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_IMUX29_4", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_BYP3_4", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_4", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_NE4BEG1_4", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_WW4END0_4", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX22_4", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW4C1_4", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_WW4END3_4", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B10_4", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "CFG_CENTER_NE4BEG2_4", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_4", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_4", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_EL1BEG1_4", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_SE2A3_4", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_IMUX16_4", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX30_4", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_WW4END1_4", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX23_4", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW4C3_4", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_4", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_IMUX33_4", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_IMUX20_4", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_IMUX34_4", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_IMUX47_4", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_LH12_4", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_SW4A2_4", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_WW2END0_4", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_NW4END3_4", + "VFRAME_NW4END3" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_IMUX47_6", + "CMT_TOP_IMUX47_6" + ], + [ + "CMT_FIFO_L_IMUX45_6", + "CMT_TOP_IMUX45_6" + ], + [ + "CMT_FIFO_WW4B2_7", + "CMT_TOP_WW4B2_7" + ], + [ + "CMT_FIFO_SE4BEG3_3", + "CMT_TOP_SE4BEG3_3" + ], + [ + "CMT_FIFO_SW4END2_3", + "CMT_TOP_SW4END2_3" + ], + [ + "CMT_FIFO_L_BYP4_6", + "CMT_TOP_BYP4_6" + ], + [ + "CMT_FIFO_LH11_10", + "CMT_TOP_LH11_10" + ], + [ + "CMT_FIFO_L_IMUX22_4", + "CMT_TOP_IMUX22_4" + ], + [ + "CMT_FIFO_L_IMUX12_3", + "CMT_TOP_IMUX12_3" + ], + [ + "CMT_FIFO_SE2A3_1", + "CMT_TOP_SE2A3_1" + ], + [ + "CMT_FIFO_SW4A0_2", + "CMT_TOP_SW4A0_2" + ], + [ + "CMT_FIFO_LH3_2", + "CMT_TOP_LH3_2" + ], + [ + "CMT_FIFO_SW4END1_9", + "CMT_TOP_SW4END1_9" + ], + [ + "CMT_FIFO_L_IMUX8_9", + "CMT_TOP_IMUX8_9" + ], + [ + "CMT_FIFO_EE4A3_7", + "CMT_TOP_EE4A3_7" + ], + [ + "CMT_FIFO_SW4END3_11", + "CMT_TOP_SW4END3_11" + ], + [ + "CMT_FIFO_SE4C3_9", + "CMT_TOP_SE4C3_9" + ], + [ + "CMT_FIFO_NE4C0_10", + "CMT_TOP_NE4C0_10" + ], + [ + "CMT_FIFO_NE2A1_6", + "CMT_TOP_NE2A1_6" + ], + [ + "CMT_FIFO_WW2A0_8", + "CMT_TOP_WW2A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_1", + "CMT_TOP_LOGIC_OUTS_L_B23_1" + ], + [ + "CMT_FIFO_L_FAN3_4", + "CMT_TOP_FAN3_4" + ], + [ + "CMT_FIFO_NW4END3_6", + "CMT_TOP_NW4END3_6" + ], + [ + "CMT_FIFO_NW2A2_6", + "CMT_TOP_NW2A2_6" + ], + [ + "CMT_FIFO_SW4END1_8", + "CMT_TOP_SW4END1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_2", + "CMT_TOP_LOGIC_OUTS_L_B21_2" + ], + [ + "CMT_FIFO_WW2END1_5", + "CMT_TOP_WW2END1_5" + ], + [ + "CMT_FIFO_L_BYP6_2", + "CMT_TOP_BYP6_2" + ], + [ + "CMT_FIFO_NE4C0_8", + "CMT_TOP_NE4C0_8" + ], + [ + "CMT_FIFO_EE4A2_1", + "CMT_TOP_EE4A2_1" + ], + [ + "CMT_FIFO_EL1BEG0_9", + "CMT_TOP_EL1BEG0_9" + ], + [ + "CMT_FIFO_LH1_9", + "CMT_TOP_LH1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_10", + "CMT_TOP_LOGIC_OUTS_L_B21_10" + ], + [ + "CMT_FIFO_WL1END1_11", + "CMT_TOP_WL1END1_11" + ], + [ + "CMT_FIFO_WW4C0_9", + "CMT_TOP_WW4C0_9" + ], + [ + "CMT_FIFO_WW2A2_7", + "CMT_TOP_WW2A2_7" + ], + [ + "CMT_FIFO_NW2A0_6", + "CMT_TOP_NW2A0_6" + ], + [ + "CMT_FIFO_NW4END3_7", + "CMT_TOP_NW4END3_7" + ], + [ + "CMT_FIFO_NE2A3_10", + "CMT_TOP_NE2A3_10" + ], + [ + "CMT_FIFO_EE2A0_9", + "CMT_TOP_EE2A0_9" + ], + [ + "CMT_FIFO_ER1BEG0_11", + "CMT_TOP_ER1BEG0_11" + ], + [ + "CMT_FIFO_ER1BEG2_7", + "CMT_TOP_ER1BEG2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_4", + "CMT_TOP_LOGIC_OUTS_L_B17_4" + ], + [ + "CMT_FIFO_LH3_8", + "CMT_TOP_LH3_8" + ], + [ + "CMT_FIFO_L_FAN5_2", + "CMT_TOP_FAN5_2" + ], + [ + "CMT_FIFO_L_BYP7_0", + "CMT_TOP_BYP7_0" + ], + [ + "CMT_FIFO_L_IMUX43_10", + "CMT_TOP_IMUX43_10" + ], + [ + "CMT_FIFO_L_IMUX5_9", + "CMT_TOP_IMUX5_9" + ], + [ + "CMT_FIFO_WW4C3_8", + "CMT_TOP_WW4C3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_8", + "CMT_TOP_LOGIC_OUTS_L_B15_8" + ], + [ + "CMT_FIFO_WW2A3_11", + "CMT_TOP_WW2A3_11" + ], + [ + "CMT_FIFO_WW4A0_8", + "CMT_TOP_WW4A0_8" + ], + [ + "CMT_FIFO_WW4END1_0", + "CMT_TOP_WW4END1_0" + ], + [ + "CMT_FIFO_WW4END2_2", + "CMT_TOP_WW4END2_2" + ], + [ + "CMT_FIFO_WW4END3_4", + "CMT_TOP_WW4END3_4" + ], + [ + "CMT_FIFO_EE4BEG3_9", + "CMT_TOP_EE4BEG3_9" + ], + [ + "CMT_FIFO_SW4A1_3", + "CMT_TOP_SW4A1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_4", + "CMT_TOP_LOGIC_OUTS_L_B9_4" + ], + [ + "CMT_FIFO_L_FAN6_1", + "CMT_TOP_FAN6_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_11", + "CMT_TOP_LOGIC_OUTS_L_B1_11" + ], + [ + "CMT_FIFO_L_IMUX14_1", + "CMT_TOP_IMUX14_1" + ], + [ + "CMT_FIFO_EL1BEG2_8", + "CMT_TOP_EL1BEG2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0" + ], + [ + "CMT_FIFO_SW4A2_5", + "CMT_TOP_SW4A2_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "CMT_TOP_ICLK_1" + ], + [ + "CMT_FIFO_L_BYP6_8", + "CMT_TOP_BYP6_8" + ], + [ + "CMT_FIFO_EE4BEG3_0", + "CMT_TOP_EE4BEG3_0" + ], + [ + "CMT_FIFO_L_CTRL0_2", + "CMT_TOP_CTRL0_2" + ], + [ + "CMT_FIFO_WL1END3_4", + "CMT_TOP_WL1END3_4" + ], + [ + "CMT_FIFO_L_IMUX9_7", + "CMT_TOP_IMUX9_7" + ], + [ + "CMT_FIFO_L_BYP6_1", + "CMT_TOP_BYP6_1" + ], + [ + "CMT_FIFO_L_IMUX18_2", + "CMT_TOP_IMUX18_2" + ], + [ + "CMT_FIFO_EL1BEG2_7", + "CMT_TOP_EL1BEG2_7" + ], + [ + "CMT_FIFO_L_IMUX16_5", + "CMT_TOP_IMUX16_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_1", + "CMT_TOP_LOGIC_OUTS_L_B11_1" + ], + [ + "CMT_FIFO_LH2_6", + "CMT_TOP_LH2_6" + ], + [ + "CMT_FIFO_NE4C1_2", + "CMT_TOP_NE4C1_2" + ], + [ + "CMT_FIFO_NE2A0_2", + "CMT_TOP_NE2A0_2" + ], + [ + "CMT_FIFO_SW4END3_9", + "CMT_TOP_SW4END3_9" + ], + [ + "CMT_FIFO_SW4A0_7", + "CMT_TOP_SW4A0_7" + ], + [ + "CMT_FIFO_EL1BEG0_10", + "CMT_TOP_EL1BEG0_10" + ], + [ + "CMT_FIFO_ER1BEG2_10", + "CMT_TOP_ER1BEG2_10" + ], + [ + "CMT_FIFO_WW4C1_9", + "CMT_TOP_WW4C1_9" + ], + [ + "CMT_FIFO_LH7_0", + "CMT_TOP_LH7_0" + ], + [ + "CMT_FIFO_WW2A0_9", + "CMT_TOP_WW2A0_9" + ], + [ + "CMT_FIFO_NE2A2_0", + "CMT_TOP_NE2A2_0" + ], + [ + "CMT_FIFO_L_IMUX0_5", + "CMT_TOP_IMUX0_5" + ], + [ + "CMT_FIFO_L_IMUX24_10", + "CMT_TOP_IMUX24_10" + ], + [ + "CMT_FIFO_ER1BEG3_3", + "CMT_TOP_ER1BEG3_3" + ], + [ + "CMT_FIFO_L_FAN4_4", + "CMT_TOP_FAN4_4" + ], + [ + "CMT_FIFO_LH12_6", + "CMT_TOP_LH12_6" + ], + [ + "CMT_FIFO_SW2A0_10", + "CMT_TOP_SW2A0_10" + ], + [ + "CMT_FIFO_L_IMUX24_1", + "CMT_TOP_IMUX24_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "CMT_TOP_ICLKDIV_2" + ], + [ + "CMT_FIFO_L_IMUX47_8", + "CMT_TOP_IMUX47_8" + ], + [ + "CMT_FIFO_SW2A3_2", + "CMT_TOP_SW2A3_2" + ], + [ + "CMT_FIFO_L_IMUX26_6", + "CMT_TOP_IMUX26_6" + ], + [ + "CMT_FIFO_WW4C0_11", + "CMT_TOP_WW4C0_11" + ], + [ + "CMT_FIFO_L_FAN3_8", + "CMT_TOP_FAN3_8" + ], + [ + "CMT_FIFO_SW2A3_9", + "CMT_TOP_SW2A3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_10", + "CMT_TOP_LOGIC_OUTS_L_B20_10" + ], + [ + "CMT_FIFO_L_BYP5_1", + "CMT_TOP_BYP5_1" + ], + [ + "CMT_FIFO_SE4C3_8", + "CMT_TOP_SE4C3_8" + ], + [ + "CMT_FIFO_WW4B1_10", + "CMT_TOP_WW4B1_10" + ], + [ + "CMT_FIFO_WW2A3_7", + "CMT_TOP_WW2A3_7" + ], + [ + "CMT_FIFO_L_BYP0_0", + "CMT_TOP_BYP0_0" + ], + [ + "CMT_FIFO_L_IMUX36_5", + "CMT_TOP_IMUX36_5" + ], + [ + "CMT_FIFO_L_FAN6_6", + "CMT_TOP_FAN6_6" + ], + [ + "CMT_FIFO_WW4A3_3", + "CMT_TOP_WW4A3_3" + ], + [ + "CMT_FIFO_L_IMUX31_5", + "CMT_TOP_IMUX31_5" + ], + [ + "CMT_FIFO_L_FAN1_4", + "CMT_TOP_FAN1_4" + ], + [ + "CMT_FIFO_WW2END3_11", + "CMT_TOP_WW2END3_11" + ], + [ + "CMT_FIFO_L_CLK1_10", + "CMT_TOP_CLK1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_3", + "CMT_TOP_LOGIC_OUTS_L_B15_3" + ], + [ + "CMT_FIFO_ER1BEG3_6", + "CMT_TOP_ER1BEG3_6" + ], + [ + "CMT_FIFO_NW4END3_3", + "CMT_TOP_NW4END3_3" + ], + [ + "CMT_FIFO_WR1END1_8", + "CMT_TOP_WR1END1_8" + ], + [ + "CMT_FIFO_WW4B2_6", + "CMT_TOP_WW4B2_6" + ], + [ + "CMT_FIFO_L_FAN5_6", + "CMT_TOP_FAN5_6" + ], + [ + "CMT_FIFO_NW4END2_9", + "CMT_TOP_NW4END2_9" + ], + [ + "CMT_FIFO_WW2A2_8", + "CMT_TOP_WW2A2_8" + ], + [ + "CMT_FIFO_NE2A0_8", + "CMT_TOP_NE2A0_8" + ], + [ + "CMT_FIFO_EE4C0_4", + "CMT_TOP_EE4C0_4" + ], + [ + "CMT_FIFO_LH9_2", + "CMT_TOP_LH9_2" + ], + [ + "CMT_FIFO_EL1BEG1_11", + "CMT_TOP_EL1BEG1_11" + ], + [ + "CMT_FIFO_L_IMUX5_7", + "CMT_TOP_IMUX5_7" + ], + [ + "CMT_FIFO_L_IMUX5_3", + "CMT_TOP_IMUX5_3" + ], + [ + "CMT_FIFO_LH2_3", + "CMT_TOP_LH2_3" + ], + [ + "CMT_FIFO_EE2A3_4", + "CMT_TOP_EE2A3_4" + ], + [ + "CMT_FIFO_EL1BEG3_6", + "CMT_TOP_EL1BEG3_6" + ], + [ + "CMT_FIFO_L_BYP5_3", + "CMT_TOP_BYP5_3" + ], + [ + "CMT_FIFO_L_IMUX7_8", + "CMT_TOP_IMUX7_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_7", + "CMT_TOP_LOGIC_OUTS_L_B2_7" + ], + [ + "CMT_FIFO_EE4A0_7", + "CMT_TOP_EE4A0_7" + ], + [ + "CMT_FIFO_L_IMUX30_10", + "CMT_TOP_IMUX30_10" + ], + [ + "CMT_FIFO_WW2END1_4", + "CMT_TOP_WW2END1_4" + ], + [ + "CMT_FIFO_WW4END2_4", + "CMT_TOP_WW4END2_4" + ], + [ + "CMT_FIFO_L_FAN5_10", + "CMT_TOP_FAN5_10" + ], + [ + "CMT_FIFO_L_IMUX9_0", + "CMT_TOP_IMUX9_0" + ], + [ + "CMT_FIFO_WL1END1_2", + "CMT_TOP_WL1END1_2" + ], + [ + "CMT_FIFO_NE2A2_1", + "CMT_TOP_NE2A2_1" + ], + [ + "CMT_FIFO_L_FAN6_8", + "CMT_TOP_FAN6_8" + ], + [ + "CMT_FIFO_L_IMUX21_3", + "CMT_TOP_IMUX21_3" + ], + [ + "CMT_FIFO_WW2END0_1", + "CMT_TOP_WW2END0_1" + ], + [ + "CMT_FIFO_LH2_8", + "CMT_TOP_LH2_8" + ], + [ + "CMT_FIFO_L_IMUX27_9", + "CMT_TOP_IMUX27_9" + ], + [ + "CMT_FIFO_SW4END1_1", + "CMT_TOP_SW4END1_1" + ], + [ + "CMT_FIFO_EE2A0_4", + "CMT_TOP_EE2A0_4" + ], + [ + "CMT_FIFO_WW4END0_10", + "CMT_TOP_WW4END0_10" + ], + [ + "CMT_FIFO_L_IMUX7_2", + "CMT_TOP_IMUX7_2" + ], + [ + "CMT_FIFO_NW4A0_6", + "CMT_TOP_NW4A0_6" + ], + [ + "CMT_FIFO_L_IMUX42_0", + "CMT_TOP_IMUX42_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_10" + ], + [ + "CMT_FIFO_L_BYP4_4", + "CMT_TOP_BYP4_4" + ], + [ + "CMT_FIFO_SE2A2_3", + "CMT_TOP_SE2A2_3" + ], + [ + "CMT_FIFO_NE2A1_9", + "CMT_TOP_NE2A1_9" + ], + [ + "CMT_FIFO_WW2A0_3", + "CMT_TOP_WW2A0_3" + ], + [ + "CMT_FIFO_L_IMUX9_5", + "CMT_TOP_IMUX9_5" + ], + [ + "CMT_FIFO_NE4C1_8", + "CMT_TOP_NE4C1_8" + ], + [ + "CMT_FIFO_WL1END0_2", + "CMT_TOP_WL1END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_3", + "CMT_TOP_LOGIC_OUTS_L_B4_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_2", + "CMT_TOP_LOGIC_OUTS_L_B8_2" + ], + [ + "CMT_FIFO_L_FAN4_6", + "CMT_TOP_FAN4_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_3", + "CMT_TOP_LOGIC_OUTS_L_B23_3" + ], + [ + "CMT_FIFO_L_IMUX16_9", + "CMT_TOP_IMUX16_9" + ], + [ + "CMT_FIFO_SE2A1_9", + "CMT_TOP_SE2A1_9" + ], + [ + "CMT_FIFO_NW4END1_7", + "CMT_TOP_NW4END1_7" + ], + [ + "CMT_FIFO_SE2A2_10", + "CMT_TOP_SE2A2_10" + ], + [ + "CMT_FIFO_L_IMUX25_10", + "CMT_TOP_IMUX25_10" + ], + [ + "CMT_FIFO_L_BYP4_9", + "CMT_TOP_BYP4_9" + ], + [ + "CMT_FIFO_EE2BEG2_11", + "CMT_TOP_EE2BEG2_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_6", + "CMT_TOP_LOGIC_OUTS_L_B6_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_8", + "CMT_TOP_LOGIC_OUTS_L_B14_8" + ], + [ + "CMT_FIFO_WW2END1_1", + "CMT_TOP_WW2END1_1" + ], + [ + "CMT_FIFO_WW2END3_6", + "CMT_TOP_WW2END3_6" + ], + [ + "CMT_FIFO_L_CLK1_7", + "CMT_TOP_CLK1_7" + ], + [ + "CMT_FIFO_SE4BEG3_10", + "CMT_TOP_SE4BEG3_10" + ], + [ + "CMT_FIFO_SW4A1_1", + "CMT_TOP_SW4A1_1" + ], + [ + "CMT_FIFO_LH8_3", + "CMT_TOP_LH8_3" + ], + [ + "CMT_FIFO_WW4A1_9", + "CMT_TOP_WW4A1_9" + ], + [ + "CMT_FIFO_L_IMUX45_1", + "CMT_TOP_IMUX45_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_2", + "CMT_TOP_LOGIC_OUTS_L_B18_2" + ], + [ + "CMT_FIFO_L_IMUX28_10", + "CMT_TOP_IMUX28_10" + ], + [ + "CMT_FIFO_SE4C0_0", + "CMT_TOP_SE4C0_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "CMT_TOP_OCLK_2" + ], + [ + "CMT_FIFO_L_IMUX21_11", + "CMT_TOP_IMUX21_11" + ], + [ + "CMT_FIFO_NE4BEG1_0", + "CMT_TOP_NE4BEG1_0" + ], + [ + "CMT_FIFO_SW4END1_11", + "CMT_TOP_SW4END1_11" + ], + [ + "CMT_FIFO_NE4C2_7", + "CMT_TOP_NE4C2_7" + ], + [ + "CMT_FIFO_SE4C2_4", + "CMT_TOP_SE4C2_4" + ], + [ + "CMT_FIFO_SW4A3_4", + "CMT_TOP_SW4A3_4" + ], + [ + "CMT_FIFO_ER1BEG1_0", + "CMT_TOP_ER1BEG1_0" + ], + [ + "CMT_FIFO_NW4A2_3", + "CMT_TOP_NW4A2_3" + ], + [ + "CMT_FIFO_WW4A1_0", + "CMT_TOP_WW4A1_0" + ], + [ + "CMT_FIFO_EL1BEG1_9", + "CMT_TOP_EL1BEG1_9" + ], + [ + "CMT_FIFO_L_IMUX34_11", + "CMT_TOP_IMUX34_11" + ], + [ + "CMT_FIFO_SW2A0_0", + "CMT_TOP_SW2A0_0" + ], + [ + "CMT_FIFO_SE4BEG1_5", + "CMT_TOP_SE4BEG1_5" + ], + [ + "CMT_FIFO_NW4END0_6", + "CMT_TOP_NW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX23_2", + "CMT_TOP_IMUX23_2" + ], + [ + "CMT_FIFO_L_IMUX1_11", + "CMT_TOP_IMUX1_11" + ], + [ + "CMT_FIFO_WW4END1_1", + "CMT_TOP_WW4END1_1" + ], + [ + "CMT_FIFO_EE2BEG3_7", + "CMT_TOP_EE2BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX33_5", + "CMT_TOP_IMUX33_5" + ], + [ + "CMT_FIFO_WW4B3_3", + "CMT_TOP_WW4B3_3" + ], + [ + "CMT_FIFO_L_FAN5_0", + "CMT_TOP_FAN5_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_6", + "CMT_TOP_LOGIC_OUTS_L_B17_6" + ], + [ + "CMT_FIFO_WW4END2_8", + "CMT_TOP_WW4END2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_0", + "CMT_TOP_LOGIC_OUTS_L_B21_0" + ], + [ + "CMT_FIFO_L_BYP0_1", + "CMT_TOP_BYP0_1" + ], + [ + "CMT_FIFO_WL1END3_7", + "CMT_TOP_WL1END3_7" + ], + [ + "CMT_FIFO_L_IMUX39_9", + "CMT_TOP_IMUX39_9" + ], + [ + "CMT_FIFO_WR1END3_6", + "CMT_TOP_WR1END3_6" + ], + [ + "CMT_FIFO_SE4C3_1", + "CMT_TOP_SE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX33_7", + "CMT_TOP_IMUX33_7" + ], + [ + "CMT_FIFO_L_BYP4_11", + "CMT_TOP_BYP4_11" + ], + [ + "CMT_FIFO_L_IMUX32_6", + "CMT_TOP_IMUX32_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "CMT_TOP_OCLKDIV_2" + ], + [ + "CMT_FIFO_L_IMUX33_11", + "CMT_TOP_IMUX33_11" + ], + [ + "CMT_FIFO_SE2A3_4", + "CMT_TOP_SE2A3_4" + ], + [ + "CMT_FIFO_L_IMUX44_2", + "CMT_TOP_IMUX44_2" + ], + [ + "CMT_FIFO_NE4C3_5", + "CMT_TOP_NE4C3_5" + ], + [ + "CMT_FIFO_EE4B1_4", + "CMT_TOP_EE4B1_4" + ], + [ + "CMT_FIFO_SW2A2_11", + "CMT_TOP_SW2A2_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_0", + "CMT_TOP_LOGIC_OUTS_L_B22_0" + ], + [ + "CMT_FIFO_WW4C3_9", + "CMT_TOP_WW4C3_9" + ], + [ + "CMT_FIFO_EE2BEG0_11", + "CMT_TOP_EE2BEG0_11" + ], + [ + "CMT_FIFO_ER1BEG0_0", + "CMT_TOP_ER1BEG0_0" + ], + [ + "CMT_FIFO_NW4END2_8", + "CMT_TOP_NW4END2_8" + ], + [ + "CMT_FIFO_L_IMUX25_3", + "CMT_TOP_IMUX25_3" + ], + [ + "CMT_FIFO_NW4A0_2", + "CMT_TOP_NW4A0_2" + ], + [ + "CMT_FIFO_SE4C1_0", + "CMT_TOP_SE4C1_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_8", + "CMT_TOP_LOGIC_OUTS_L_B1_8" + ], + [ + "CMT_FIFO_WW4A1_7", + "CMT_TOP_WW4A1_7" + ], + [ + "CMT_FIFO_L_IMUX21_1", + "CMT_TOP_IMUX21_1" + ], + [ + "CMT_FIFO_LH11_2", + "CMT_TOP_LH11_2" + ], + [ + "CMT_FIFO_SE2A1_8", + "CMT_TOP_SE2A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_4", + "CMT_TOP_LOGIC_OUTS_L_B13_4" + ], + [ + "CMT_FIFO_WW4END3_1", + "CMT_TOP_WW4END3_1" + ], + [ + "CMT_FIFO_L_BYP1_6", + "CMT_TOP_BYP1_6" + ], + [ + "CMT_FIFO_LH7_7", + "CMT_TOP_LH7_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_3", + "CMT_TOP_LOGIC_OUTS_L_B6_3" + ], + [ + "CMT_FIFO_EE4BEG0_0", + "CMT_TOP_EE4BEG0_0" + ], + [ + "CMT_FIFO_NE4BEG2_11", + "CMT_TOP_NE4BEG2_11" + ], + [ + "CMT_FIFO_WW4A2_9", + "CMT_TOP_WW4A2_9" + ], + [ + "CMT_FIFO_L_IMUX29_6", + "CMT_TOP_IMUX29_6" + ], + [ + "CMT_FIFO_WW2A2_2", + "CMT_TOP_WW2A2_2" + ], + [ + "CMT_FIFO_L_BYP0_2", + "CMT_TOP_BYP0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_10", + "CMT_TOP_LOGIC_OUTS_L_B6_10" + ], + [ + "CMT_FIFO_NE4BEG1_6", + "CMT_TOP_NE4BEG1_6" + ], + [ + "CMT_FIFO_NW2A1_4", + "CMT_TOP_NW2A1_4" + ], + [ + "CMT_FIFO_L_IMUX2_11", + "CMT_TOP_IMUX2_11" + ], + [ + "CMT_FIFO_WW4A3_9", + "CMT_TOP_WW4A3_9" + ], + [ + "CMT_FIFO_SW2A0_7", + "CMT_TOP_SW2A0_7" + ], + [ + "CMT_FIFO_L_FAN0_8", + "CMT_TOP_FAN0_8" + ], + [ + "CMT_FIFO_NE4BEG3_5", + "CMT_TOP_NE4BEG3_5" + ], + [ + "CMT_FIFO_LH5_1", + "CMT_TOP_LH5_1" + ], + [ + "CMT_FIFO_SE4BEG0_4", + "CMT_TOP_SE4BEG0_4" + ], + [ + "CMT_FIFO_WW4END1_3", + "CMT_TOP_WW4END1_3" + ], + [ + "CMT_FIFO_NE2A1_8", + "CMT_TOP_NE2A1_8" + ], + [ + "CMT_FIFO_L_IMUX8_2", + "CMT_TOP_IMUX8_2" + ], + [ + "CMT_FIFO_SE2A0_8", + "CMT_TOP_SE2A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_6", + "CMT_TOP_LOGIC_OUTS_L_B8_6" + ], + [ + "CMT_FIFO_L_BYP3_0", + "CMT_TOP_BYP3_0" + ], + [ + "CMT_FIFO_EE2BEG0_6", + "CMT_TOP_EE2BEG0_6" + ], + [ + "CMT_FIFO_EL1BEG2_9", + "CMT_TOP_EL1BEG2_9" + ], + [ + "CMT_FIFO_EE4B2_9", + "CMT_TOP_EE4B2_9" + ], + [ + "CMT_FIFO_SE4C3_4", + "CMT_TOP_SE4C3_4" + ], + [ + "CMT_FIFO_L_IMUX30_1", + "CMT_TOP_IMUX30_1" + ], + [ + "CMT_FIFO_L_BYP4_0", + "CMT_TOP_BYP4_0" + ], + [ + "CMT_FIFO_L_IMUX34_10", + "CMT_TOP_IMUX34_10" + ], + [ + "CMT_FIFO_SW2A0_6", + "CMT_TOP_SW2A0_6" + ], + [ + "CMT_FIFO_NW4A3_4", + "CMT_TOP_NW4A3_4" + ], + [ + "CMT_FIFO_L_IMUX17_3", + "CMT_TOP_IMUX17_3" + ], + [ + "CMT_FIFO_WW2END0_5", + "CMT_TOP_WW2END0_5" + ], + [ + "CMT_FIFO_EE2BEG2_0", + "CMT_TOP_EE2BEG2_0" + ], + [ + "CMT_FIFO_WR1END3_10", + "CMT_TOP_WR1END3_10" + ], + [ + "CMT_FIFO_L_IMUX41_1", + "CMT_TOP_IMUX41_1" + ], + [ + "CMT_FIFO_EE4A0_10", + "CMT_TOP_EE4A0_10" + ], + [ + "CMT_FIFO_EE4B1_9", + "CMT_TOP_EE4B1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_3", + "CMT_TOP_LOGIC_OUTS_L_B11_3" + ], + [ + "CMT_FIFO_NW2A0_0", + "CMT_TOP_NW2A0_0" + ], + [ + "CMT_FIFO_L_IMUX26_11", + "CMT_TOP_IMUX26_11" + ], + [ + "CMT_FIFO_L_IMUX2_10", + "CMT_TOP_IMUX2_10" + ], + [ + "CMT_FIFO_L_IMUX5_4", + "CMT_TOP_IMUX5_4" + ], + [ + "CMT_FIFO_SW4END3_10", + "CMT_TOP_SW4END3_10" + ], + [ + "CMT_FIFO_WW4C2_2", + "CMT_TOP_WW4C2_2" + ], + [ + "CMT_FIFO_SE4BEG1_7", + "CMT_TOP_SE4BEG1_7" + ], + [ + "CMT_FIFO_SW4A1_5", + "CMT_TOP_SW4A1_5" + ], + [ + "CMT_FIFO_SW2A0_11", + "CMT_TOP_SW2A0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_3", + "CMT_TOP_LOGIC_OUTS_L_B13_3" + ], + [ + "CMT_FIFO_L_IMUX29_5", + "CMT_TOP_IMUX29_5" + ], + [ + "CMT_FIFO_L_FAN6_3", + "CMT_TOP_FAN6_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_4", + "CMT_TOP_LOGIC_OUTS_L_B23_4" + ], + [ + "CMT_FIFO_L_IMUX25_5", + "CMT_TOP_IMUX25_5" + ], + [ + "CMT_FIFO_SE4C0_2", + "CMT_TOP_SE4C0_2" + ], + [ + "CMT_FIFO_WW2A2_10", + "CMT_TOP_WW2A2_10" + ], + [ + "CMT_FIFO_L_CLK1_1", + "CMT_TOP_CLK1_1" + ], + [ + "CMT_FIFO_L_IMUX0_0", + "CMT_TOP_IMUX0_0" + ], + [ + "CMT_FIFO_L_IMUX29_11", + "CMT_TOP_IMUX29_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "CMT_TOP_ICLKDIV_7" + ], + [ + "CMT_FIFO_L_FAN6_4", + "CMT_TOP_FAN6_4" + ], + [ + "CMT_FIFO_NE4BEG1_10", + "CMT_TOP_NE4BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX0_8", + "CMT_TOP_IMUX0_8" + ], + [ + "CMT_FIFO_L_IMUX34_1", + "CMT_TOP_IMUX34_1" + ], + [ + "CMT_FIFO_EL1BEG2_3", + "CMT_TOP_EL1BEG2_3" + ], + [ + "CMT_FIFO_SW2A0_9", + "CMT_TOP_SW2A0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_1", + "CMT_TOP_LOGIC_OUTS_L_B0_1" + ], + [ + "CMT_FIFO_WW4A2_11", + "CMT_TOP_WW4A2_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "CMT_TOP_OCLKDIV_0" + ], + [ + "CMT_FIFO_NW4A1_10", + "CMT_TOP_NW4A1_10" + ], + [ + "CMT_FIFO_LH11_7", + "CMT_TOP_LH11_7" + ], + [ + "CMT_FIFO_NE4C3_11", + "CMT_TOP_NE4C3_11" + ], + [ + "CMT_FIFO_L_IMUX23_0", + "CMT_TOP_IMUX23_0" + ], + [ + "CMT_FIFO_NW4A3_6", + "CMT_TOP_NW4A3_6" + ], + [ + "CMT_FIFO_SW2A2_9", + "CMT_TOP_SW2A2_9" + ], + [ + "CMT_FIFO_L_FAN3_2", + "CMT_TOP_FAN3_2" + ], + [ + "CMT_FIFO_WL1END1_3", + "CMT_TOP_WL1END1_3" + ], + [ + "CMT_FIFO_L_IMUX12_0", + "CMT_TOP_IMUX12_0" + ], + [ + "CMT_FIFO_WW4C0_2", + "CMT_TOP_WW4C0_2" + ], + [ + "CMT_FIFO_NW4A2_7", + "CMT_TOP_NW4A2_7" + ], + [ + "CMT_FIFO_ER1BEG1_3", + "CMT_TOP_ER1BEG1_3" + ], + [ + "CMT_FIFO_WW4C1_4", + "CMT_TOP_WW4C1_4" + ], + [ + "CMT_FIFO_WW4END3_3", + "CMT_TOP_WW4END3_3" + ], + [ + "CMT_FIFO_EE4A1_5", + "CMT_TOP_EE4A1_5" + ], + [ + "CMT_FIFO_SE2A2_7", + "CMT_TOP_SE2A2_7" + ], + [ + "CMT_FIFO_NW2A1_0", + "CMT_TOP_NW2A1_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "CMT_TOP_OCLK1X_90_7" + ], + [ + "CMT_FIFO_L_CTRL1_5", + "CMT_TOP_CTRL1_5" + ], + [ + "CMT_FIFO_WW4B0_11", + "CMT_TOP_WW4B0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_6", + "CMT_TOP_LOGIC_OUTS_L_B7_6" + ], + [ + "CMT_FIFO_L_IMUX34_3", + "CMT_TOP_IMUX34_3" + ], + [ + "CMT_FIFO_WW2A1_3", + "CMT_TOP_WW2A1_3" + ], + [ + "CMT_FIFO_EL1BEG3_7", + "CMT_TOP_EL1BEG3_7" + ], + [ + "CMT_FIFO_EE2BEG2_4", + "CMT_TOP_EE2BEG2_4" + ], + [ + "CMT_FIFO_LH10_11", + "CMT_TOP_LH10_11" + ], + [ + "CMT_FIFO_SW2A1_0", + "CMT_TOP_SW2A1_0" + ], + [ + "CMT_FIFO_L_IMUX15_9", + "CMT_TOP_IMUX15_9" + ], + [ + "CMT_FIFO_L_IMUX1_4", + "CMT_TOP_IMUX1_4" + ], + [ + "CMT_FIFO_L_IMUX22_7", + "CMT_TOP_IMUX22_7" + ], + [ + "CMT_FIFO_EE4A0_11", + "CMT_TOP_EE4A0_11" + ], + [ + "CMT_FIFO_WL1END2_3", + "CMT_TOP_WL1END2_3" + ], + [ + "CMT_FIFO_EE2BEG3_1", + "CMT_TOP_EE2BEG3_1" + ], + [ + "CMT_FIFO_EE2A2_1", + "CMT_TOP_EE2A2_1" + ], + [ + "CMT_FIFO_NW4END2_1", + "CMT_TOP_NW4END2_1" + ], + [ + "CMT_FIFO_L_IMUX16_7", + "CMT_TOP_IMUX16_7" + ], + [ + "CMT_FIFO_SW4A2_2", + "CMT_TOP_SW4A2_2" + ], + [ + "CMT_FIFO_LH11_9", + "CMT_TOP_LH11_9" + ], + [ + "CMT_FIFO_ER1BEG2_9", + "CMT_TOP_ER1BEG2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_5", + "CMT_TOP_LOGIC_OUTS_L_B14_5" + ], + [ + "CMT_FIFO_LH6_2", + "CMT_TOP_LH6_2" + ], + [ + "CMT_FIFO_SE4C1_5", + "CMT_TOP_SE4C1_5" + ], + [ + "CMT_FIFO_L_IMUX2_2", + "CMT_TOP_IMUX2_2" + ], + [ + "CMT_FIFO_NE4C3_8", + "CMT_TOP_NE4C3_8" + ], + [ + "CMT_FIFO_WR1END0_11", + "CMT_TOP_WR1END0_11" + ], + [ + "CMT_FIFO_L_IMUX25_2", + "CMT_TOP_IMUX25_2" + ], + [ + "CMT_FIFO_SW4END0_2", + "CMT_TOP_SW4END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_7", + "CMT_TOP_LOGIC_OUTS_L_B5_7" + ], + [ + "CMT_FIFO_L_IMUX32_1", + "CMT_TOP_IMUX32_1" + ], + [ + "CMT_FIFO_L_IMUX41_5", + "CMT_TOP_IMUX41_5" + ], + [ + "CMT_FIFO_EE4C1_0", + "CMT_TOP_EE4C1_0" + ], + [ + "CMT_FIFO_EE4C0_6", + "CMT_TOP_EE4C0_6" + ], + [ + "CMT_FIFO_WW2A3_1", + "CMT_TOP_WW2A3_1" + ], + [ + "CMT_FIFO_NE4C2_1", + "CMT_TOP_NE4C2_1" + ], + [ + "CMT_FIFO_NW2A3_0", + "CMT_TOP_NW2A3_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "CMT_TOP_OCLK_7" + ], + [ + "CMT_FIFO_L_IMUX15_6", + "CMT_TOP_IMUX15_6" + ], + [ + "CMT_FIFO_EE2A0_3", + "CMT_TOP_EE2A0_3" + ], + [ + "CMT_FIFO_EE4BEG1_11", + "CMT_TOP_EE4BEG1_11" + ], + [ + "CMT_FIFO_LH7_5", + "CMT_TOP_LH7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_7", + "CMT_TOP_LOGIC_OUTS_L_B20_7" + ], + [ + "CMT_FIFO_SE4BEG0_8", + "CMT_TOP_SE4BEG0_8" + ], + [ + "CMT_FIFO_EE4C1_4", + "CMT_TOP_EE4C1_4" + ], + [ + "CMT_FIFO_NW2A2_1", + "CMT_TOP_NW2A2_1" + ], + [ + "CMT_FIFO_ER1BEG3_9", + "CMT_TOP_ER1BEG3_9" + ], + [ + "CMT_FIFO_EE4A3_0", + "CMT_TOP_EE4A3_0" + ], + [ + "CMT_FIFO_L_IMUX3_9", + "CMT_TOP_IMUX3_9" + ], + [ + "CMT_FIFO_EE4C0_7", + "CMT_TOP_EE4C0_7" + ], + [ + "CMT_FIFO_L_BYP1_1", + "CMT_TOP_BYP1_1" + ], + [ + "CMT_FIFO_SE4BEG3_0", + "CMT_TOP_SE4BEG3_0" + ], + [ + "CMT_FIFO_L_IMUX31_2", + "CMT_TOP_IMUX31_2" + ], + [ + "CMT_FIFO_WW2END3_5", + "CMT_TOP_WW2END3_5" + ], + [ + "CMT_FIFO_L_IMUX1_10", + "CMT_TOP_IMUX1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_1", + "CMT_TOP_LOGIC_OUTS_L_B20_1" + ], + [ + "CMT_FIFO_EE4BEG2_3", + "CMT_TOP_EE4BEG2_3" + ], + [ + "CMT_FIFO_L_FAN1_5", + "CMT_TOP_FAN1_5" + ], + [ + "CMT_FIFO_L_IMUX34_0", + "CMT_TOP_IMUX34_0" + ], + [ + "CMT_FIFO_L_IMUX23_3", + "CMT_TOP_IMUX23_3" + ], + [ + "CMT_FIFO_L_IMUX27_8", + "CMT_TOP_IMUX27_8" + ], + [ + "CMT_FIFO_WW4C1_1", + "CMT_TOP_WW4C1_1" + ], + [ + "CMT_FIFO_NE4BEG1_5", + "CMT_TOP_NE4BEG1_5" + ], + [ + "CMT_FIFO_NE4BEG2_4", + "CMT_TOP_NE4BEG2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_5", + "CMT_TOP_LOGIC_OUTS_L_B5_5" + ], + [ + "CMT_FIFO_WW4A0_1", + "CMT_TOP_WW4A0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_1", + "CMT_TOP_LOGIC_OUTS_L_B4_1" + ], + [ + "CMT_FIFO_WW2A3_5", + "CMT_TOP_WW2A3_5" + ], + [ + "CMT_FIFO_WW4A0_6", + "CMT_TOP_WW4A0_6" + ], + [ + "CMT_FIFO_WW4C0_6", + "CMT_TOP_WW4C0_6" + ], + [ + "CMT_FIFO_SW4END1_4", + "CMT_TOP_SW4END1_4" + ], + [ + "CMT_FIFO_EE4A1_1", + "CMT_TOP_EE4A1_1" + ], + [ + "CMT_FIFO_LH4_7", + "CMT_TOP_LH4_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_7", + "CMT_TOP_LOGIC_OUTS_L_B7_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_9", + "CMT_TOP_LOGIC_OUTS_L_B23_9" + ], + [ + "CMT_FIFO_SE4C2_3", + "CMT_TOP_SE4C2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_1", + "CMT_TOP_LOGIC_OUTS_L_B14_1" + ], + [ + "CMT_FIFO_NW4END1_1", + "CMT_TOP_NW4END1_1" + ], + [ + "CMT_FIFO_WW2END3_8", + "CMT_TOP_WW2END3_8" + ], + [ + "CMT_FIFO_NW2A2_4", + "CMT_TOP_NW2A2_4" + ], + [ + "CMT_FIFO_EE4BEG2_8", + "CMT_TOP_EE4BEG2_8" + ], + [ + "CMT_FIFO_NW2A3_5", + "CMT_TOP_NW2A3_5" + ], + [ + "CMT_FIFO_L_IMUX11_3", + "CMT_TOP_IMUX11_3" + ], + [ + "CMT_FIFO_WW4A0_0", + "CMT_TOP_WW4A0_0" + ], + [ + "CMT_FIFO_WW4END0_4", + "CMT_TOP_WW4END0_4" + ], + [ + "CMT_FIFO_L_IMUX39_4", + "CMT_TOP_IMUX39_4" + ], + [ + "CMT_FIFO_SE4C3_10", + "CMT_TOP_SE4C3_10" + ], + [ + "CMT_FIFO_L_IMUX22_8", + "CMT_TOP_IMUX22_8" + ], + [ + "CMT_FIFO_L_IMUX42_11", + "CMT_TOP_IMUX42_11" + ], + [ + "CMT_FIFO_WW2END3_1", + "CMT_TOP_WW2END3_1" + ], + [ + "CMT_FIFO_L_IMUX2_4", + "CMT_TOP_IMUX2_4" + ], + [ + "CMT_FIFO_L_BYP6_3", + "CMT_TOP_BYP6_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_4", + "CMT_TOP_LOGIC_OUTS_L_B7_4" + ], + [ + "CMT_FIFO_WW4A3_4", + "CMT_TOP_WW4A3_4" + ], + [ + "CMT_FIFO_L_IMUX7_3", + "CMT_TOP_IMUX7_3" + ], + [ + "CMT_FIFO_SW2A1_9", + "CMT_TOP_SW2A1_9" + ], + [ + "CMT_FIFO_L_IMUX18_6", + "CMT_TOP_IMUX18_6" + ], + [ + "CMT_FIFO_L_IMUX12_2", + "CMT_TOP_IMUX12_2" + ], + [ + "CMT_FIFO_LH12_2", + "CMT_TOP_LH12_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_3", + "CMT_TOP_LOGIC_OUTS_L_B8_3" + ], + [ + "CMT_FIFO_WW2END0_4", + "CMT_TOP_WW2END0_4" + ], + [ + "CMT_FIFO_L_IMUX22_3", + "CMT_TOP_IMUX22_3" + ], + [ + "CMT_FIFO_NE4BEG3_10", + "CMT_TOP_NE4BEG3_10" + ], + [ + "CMT_FIFO_LH11_5", + "CMT_TOP_LH11_5" + ], + [ + "CMT_FIFO_L_IMUX10_3", + "CMT_TOP_IMUX10_3" + ], + [ + "CMT_FIFO_LH3_10", + "CMT_TOP_LH3_10" + ], + [ + "CMT_FIFO_LH9_8", + "CMT_TOP_LH9_8" + ], + [ + "CMT_FIFO_NW4END2_11", + "CMT_TOP_NW4END2_11" + ], + [ + "CMT_FIFO_L_IMUX15_3", + "CMT_TOP_IMUX15_3" + ], + [ + "CMT_FIFO_L_IMUX47_11", + "CMT_TOP_IMUX47_11" + ], + [ + "CMT_FIFO_SE2A2_11", + "CMT_TOP_SE2A2_11" + ], + [ + "CMT_FIFO_EE4B1_5", + "CMT_TOP_EE4B1_5" + ], + [ + "CMT_FIFO_SE4BEG1_6", + "CMT_TOP_SE4BEG1_6" + ], + [ + "CMT_FIFO_LH6_6", + "CMT_TOP_LH6_6" + ], + [ + "CMT_FIFO_NE2A3_0", + "CMT_TOP_NE2A3_0" + ], + [ + "CMT_FIFO_L_BYP0_4", + "CMT_TOP_BYP0_4" + ], + [ + "CMT_FIFO_WW2END2_5", + "CMT_TOP_WW2END2_5" + ], + [ + "CMT_FIFO_EE4B3_6", + "CMT_TOP_EE4B3_6" + ], + [ + "CMT_FIFO_L_IMUX39_3", + "CMT_TOP_IMUX39_3" + ], + [ + "CMT_FIFO_L_FAN7_5", + "CMT_TOP_FAN7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_6", + "CMT_TOP_LOGIC_OUTS_L_B2_6" + ], + [ + "CMT_FIFO_WW2END0_2", + "CMT_TOP_WW2END0_2" + ], + [ + "CMT_FIFO_SE4C3_3", + "CMT_TOP_SE4C3_3" + ], + [ + "CMT_FIFO_NE4C3_1", + "CMT_TOP_NE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX40_3", + "CMT_TOP_IMUX40_3" + ], + [ + "CMT_FIFO_WW4A3_0", + "CMT_TOP_WW4A3_0" + ], + [ + "CMT_FIFO_L_IMUX37_10", + "CMT_TOP_IMUX37_10" + ], + [ + "CMT_FIFO_L_IMUX21_4", + "CMT_TOP_IMUX21_4" + ], + [ + "CMT_FIFO_SE4BEG0_11", + "CMT_TOP_SE4BEG0_11" + ], + [ + "CMT_FIFO_WW4B2_10", + "CMT_TOP_WW4B2_10" + ], + [ + "CMT_FIFO_EE4B1_11", + "CMT_TOP_EE4B1_11" + ], + [ + "CMT_FIFO_WW2A1_6", + "CMT_TOP_WW2A1_6" + ], + [ + "CMT_FIFO_NE2A0_10", + "CMT_TOP_NE2A0_10" + ], + [ + "CMT_FIFO_EE4B2_7", + "CMT_TOP_EE4B2_7" + ], + [ + "CMT_FIFO_SE4C0_10", + "CMT_TOP_SE4C0_10" + ], + [ + "CMT_FIFO_SE2A0_2", + "CMT_TOP_SE2A0_2" + ], + [ + "CMT_FIFO_NE4C1_4", + "CMT_TOP_NE4C1_4" + ], + [ + "CMT_FIFO_L_IMUX4_5", + "CMT_TOP_IMUX4_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_10" + ], + [ + "CMT_FIFO_L_IMUX26_5", + "CMT_TOP_IMUX26_5" + ], + [ + "CMT_FIFO_EE4A3_8", + "CMT_TOP_EE4A3_8" + ], + [ + "CMT_FIFO_L_IMUX38_7", + "CMT_TOP_IMUX38_7" + ], + [ + "CMT_FIFO_EL1BEG0_1", + "CMT_TOP_EL1BEG0_1" + ], + [ + "CMT_FIFO_L_IMUX33_10", + "CMT_TOP_IMUX33_10" + ], + [ + "CMT_FIFO_LH4_11", + "CMT_TOP_LH4_11" + ], + [ + "CMT_FIFO_L_IMUX37_6", + "CMT_TOP_IMUX37_6" + ], + [ + "CMT_FIFO_L_IMUX15_10", + "CMT_TOP_IMUX15_10" + ], + [ + "CMT_FIFO_EL1BEG1_8", + "CMT_TOP_EL1BEG1_8" + ], + [ + "CMT_FIFO_NE2A2_5", + "CMT_TOP_NE2A2_5" + ], + [ + "CMT_FIFO_SW2A2_4", + "CMT_TOP_SW2A2_4" + ], + [ + "CMT_FIFO_SW4END3_2", + "CMT_TOP_SW4END3_2" + ], + [ + "CMT_FIFO_L_IMUX31_9", + "CMT_TOP_IMUX31_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "CMT_TOP_OCLKDIV_7" + ], + [ + "CMT_FIFO_L_IMUX23_8", + "CMT_TOP_IMUX23_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_10", + "CMT_TOP_LOGIC_OUTS_L_B7_10" + ], + [ + "CMT_FIFO_EE4A2_3", + "CMT_TOP_EE4A2_3" + ], + [ + "CMT_FIFO_L_IMUX46_10", + "CMT_TOP_IMUX46_10" + ], + [ + "CMT_FIFO_MONITOR_N_4", + "CMT_TOP_MONITOR_N_4" + ], + [ + "CMT_FIFO_WW4A3_10", + "CMT_TOP_WW4A3_10" + ], + [ + "CMT_FIFO_SW4A2_11", + "CMT_TOP_SW4A2_11" + ], + [ + "CMT_FIFO_LH3_11", + "CMT_TOP_LH3_11" + ], + [ + "CMT_FIFO_L_IMUX33_3", + "CMT_TOP_IMUX33_3" + ], + [ + "CMT_FIFO_WR1END3_3", + "CMT_TOP_WR1END3_3" + ], + [ + "CMT_FIFO_WR1END2_4", + "CMT_TOP_WR1END2_4" + ], + [ + "CMT_FIFO_WW4B2_5", + "CMT_TOP_WW4B2_5" + ], + [ + "CMT_FIFO_L_FAN7_2", + "CMT_TOP_FAN7_2" + ], + [ + "CMT_FIFO_NW2A1_1", + "CMT_TOP_NW2A1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_1", + "CMT_TOP_LOGIC_OUTS_L_B12_1" + ], + [ + "CMT_FIFO_NW4A2_10", + "CMT_TOP_NW4A2_10" + ], + [ + "CMT_FIFO_WL1END2_5", + "CMT_TOP_WL1END2_5" + ], + [ + "CMT_FIFO_L_CLK0_7", + "CMT_TOP_CLK0_7" + ], + [ + "CMT_FIFO_L_IMUX28_2", + "CMT_TOP_IMUX28_2" + ], + [ + "CMT_FIFO_EL1BEG2_11", + "CMT_TOP_EL1BEG2_11" + ], + [ + "CMT_FIFO_WW4END3_10", + "CMT_TOP_WW4END3_10" + ], + [ + "CMT_FIFO_EE2BEG3_10", + "CMT_TOP_EE2BEG3_10" + ], + [ + "CMT_FIFO_ER1BEG2_4", + "CMT_TOP_ER1BEG2_4" + ], + [ + "CMT_FIFO_WW4END1_2", + "CMT_TOP_WW4END1_2" + ], + [ + "CMT_FIFO_L_FAN1_3", + "CMT_TOP_FAN1_3" + ], + [ + "CMT_FIFO_L_BYP6_9", + "CMT_TOP_BYP6_9" + ], + [ + "CMT_FIFO_L_BYP7_9", + "CMT_TOP_BYP7_9" + ], + [ + "CMT_FIFO_SW4A0_6", + "CMT_TOP_SW4A0_6" + ], + [ + "CMT_FIFO_L_FAN0_4", + "CMT_TOP_FAN0_4" + ], + [ + "CMT_FIFO_SW4A1_7", + "CMT_TOP_SW4A1_7" + ], + [ + "CMT_FIFO_L_IMUX11_2", + "CMT_TOP_IMUX11_2" + ], + [ + "CMT_FIFO_EE2A1_0", + "CMT_TOP_EE2A1_0" + ], + [ + "CMT_FIFO_LH12_9", + "CMT_TOP_LH12_9" + ], + [ + "CMT_FIFO_LH10_10", + "CMT_TOP_LH10_10" + ], + [ + "CMT_FIFO_L_IMUX39_7", + "CMT_TOP_IMUX39_7" + ], + [ + "CMT_FIFO_L_IMUX9_9", + "CMT_TOP_IMUX9_9" + ], + [ + "CMT_FIFO_NW2A0_10", + "CMT_TOP_NW2A0_10" + ], + [ + "CMT_FIFO_WW2A1_2", + "CMT_TOP_WW2A1_2" + ], + [ + "CMT_FIFO_SE4C1_8", + "CMT_TOP_SE4C1_8" + ], + [ + "CMT_FIFO_L_IMUX45_2", + "CMT_TOP_IMUX45_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_5", + "CMT_TOP_LOGIC_OUTS_L_B18_5" + ], + [ + "CMT_FIFO_SW4END2_7", + "CMT_TOP_SW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX31_8", + "CMT_TOP_IMUX31_8" + ], + [ + "CMT_FIFO_L_FAN2_11", + "CMT_TOP_FAN2_11" + ], + [ + "CMT_FIFO_NW4END1_8", + "CMT_TOP_NW4END1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_3" + ], + [ + "CMT_FIFO_L_IMUX0_3", + "CMT_TOP_IMUX0_3" + ], + [ + "CMT_FIFO_SE4BEG3_9", + "CMT_TOP_SE4BEG3_9" + ], + [ + "CMT_FIFO_ER1BEG0_1", + "CMT_TOP_ER1BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_9", + "CMT_TOP_LOGIC_OUTS_L_B2_9" + ], + [ + "CMT_FIFO_NE4C2_3", + "CMT_TOP_NE4C2_3" + ], + [ + "CMT_FIFO_LH1_6", + "CMT_TOP_LH1_6" + ], + [ + "CMT_FIFO_L_IMUX21_7", + "CMT_TOP_IMUX21_7" + ], + [ + "CMT_FIFO_SE2A2_8", + "CMT_TOP_SE2A2_8" + ], + [ + "CMT_FIFO_WW4A2_3", + "CMT_TOP_WW4A2_3" + ], + [ + "CMT_FIFO_SE4BEG1_0", + "CMT_TOP_SE4BEG1_0" + ], + [ + "CMT_FIFO_WR1END1_5", + "CMT_TOP_WR1END1_5" + ], + [ + "CMT_FIFO_WW2END2_7", + "CMT_TOP_WW2END2_7" + ], + [ + "CMT_FIFO_L_IMUX38_8", + "CMT_TOP_IMUX38_8" + ], + [ + "CMT_FIFO_LH5_9", + "CMT_TOP_LH5_9" + ], + [ + "CMT_FIFO_L_FAN4_10", + "CMT_TOP_FAN4_10" + ], + [ + "CMT_FIFO_NW4END1_5", + "CMT_TOP_NW4END1_5" + ], + [ + "CMT_FIFO_EE2A2_11", + "CMT_TOP_EE2A2_11" + ], + [ + "CMT_FIFO_SE2A0_9", + "CMT_TOP_SE2A0_9" + ], + [ + "CMT_FIFO_WW4B3_7", + "CMT_TOP_WW4B3_7" + ], + [ + "CMT_FIFO_L_FAN3_11", + "CMT_TOP_FAN3_11" + ], + [ + "CMT_FIFO_LH5_2", + "CMT_TOP_LH5_2" + ], + [ + "CMT_FIFO_SE4BEG1_1", + "CMT_TOP_SE4BEG1_1" + ], + [ + "CMT_FIFO_LH1_4", + "CMT_TOP_LH1_4" + ], + [ + "CMT_FIFO_EL1BEG0_4", + "CMT_TOP_EL1BEG0_4" + ], + [ + "CMT_FIFO_WW4B1_5", + "CMT_TOP_WW4B1_5" + ], + [ + "CMT_FIFO_LH7_2", + "CMT_TOP_LH7_2" + ], + [ + "CMT_FIFO_L_IMUX5_11", + "CMT_TOP_IMUX5_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_5", + "CMT_TOP_LOGIC_OUTS_L_B12_5" + ], + [ + "CMT_FIFO_EE4B0_4", + "CMT_TOP_EE4B0_4" + ], + [ + "CMT_FIFO_EE2BEG0_2", + "CMT_TOP_EE2BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX44_1", + "CMT_TOP_IMUX44_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_8", + "CMT_TOP_LOGIC_OUTS_L_B0_8" + ], + [ + "CMT_FIFO_L_IMUX13_10", + "CMT_TOP_IMUX13_10" + ], + [ + "CMT_FIFO_NE2A3_4", + "CMT_TOP_NE2A3_4" + ], + [ + "CMT_FIFO_ER1BEG2_5", + "CMT_TOP_ER1BEG2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_3" + ], + [ + "CMT_FIFO_EE4A3_6", + "CMT_TOP_EE4A3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_2", + "CMT_TOP_LOGIC_OUTS_L_B3_2" + ], + [ + "CMT_FIFO_L_FAN1_2", + "CMT_TOP_FAN1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "CMT_TOP_OCLKDIV_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_8", + "CMT_TOP_LOGIC_OUTS_L_B10_8" + ], + [ + "CMT_FIFO_WW2END2_0", + "CMT_TOP_WW2END2_0" + ], + [ + "CMT_FIFO_NE4C2_8", + "CMT_TOP_NE4C2_8" + ], + [ + "CMT_FIFO_LH1_5", + "CMT_TOP_LH1_5" + ], + [ + "CMT_FIFO_NW2A3_9", + "CMT_TOP_NW2A3_9" + ], + [ + "CMT_FIFO_SE4BEG0_0", + "CMT_TOP_SE4BEG0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_9", + "CMT_TOP_LOGIC_OUTS_L_B9_9" + ], + [ + "CMT_FIFO_L_BYP0_5", + "CMT_TOP_BYP0_5" + ], + [ + "CMT_FIFO_L_IMUX27_3", + "CMT_TOP_IMUX27_3" + ], + [ + "CMT_FIFO_L_IMUX16_0", + "CMT_TOP_IMUX16_0" + ], + [ + "CMT_FIFO_NW4END2_2", + "CMT_TOP_NW4END2_2" + ], + [ + "CMT_FIFO_SW4A1_4", + "CMT_TOP_SW4A1_4" + ], + [ + "CMT_FIFO_WW4B3_11", + "CMT_TOP_WW4B3_11" + ], + [ + "CMT_FIFO_L_IMUX15_4", + "CMT_TOP_IMUX15_4" + ], + [ + "CMT_FIFO_WR1END2_3", + "CMT_TOP_WR1END2_3" + ], + [ + "CMT_FIFO_NW4END2_10", + "CMT_TOP_NW4END2_10" + ], + [ + "CMT_FIFO_WW4END3_9", + "CMT_TOP_WW4END3_9" + ], + [ + "CMT_FIFO_L_IMUX18_8", + "CMT_TOP_IMUX18_8" + ], + [ + "CMT_FIFO_L_FAN4_8", + "CMT_TOP_FAN4_8" + ], + [ + "CMT_FIFO_WW4A2_8", + "CMT_TOP_WW4A2_8" + ], + [ + "CMT_FIFO_L_IMUX35_4", + "CMT_TOP_IMUX35_4" + ], + [ + "CMT_FIFO_L_IMUX19_10", + "CMT_TOP_IMUX19_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_1", + "CMT_TOP_LOGIC_OUTS_L_B7_1" + ], + [ + "CMT_FIFO_L_IMUX22_0", + "CMT_TOP_IMUX22_0" + ], + [ + "CMT_FIFO_EE4B1_3", + "CMT_TOP_EE4B1_3" + ], + [ + "CMT_FIFO_NW2A1_10", + "CMT_TOP_NW2A1_10" + ], + [ + "CMT_FIFO_SE2A3_0", + "CMT_TOP_SE2A3_0" + ], + [ + "CMT_FIFO_SW4A0_9", + "CMT_TOP_SW4A0_9" + ], + [ + "CMT_FIFO_EE4A2_4", + "CMT_TOP_EE4A2_4" + ], + [ + "CMT_FIFO_EE2BEG0_7", + "CMT_TOP_EE2BEG0_7" + ], + [ + "CMT_FIFO_LH4_1", + "CMT_TOP_LH4_1" + ], + [ + "CMT_FIFO_L_IMUX8_6", + "CMT_TOP_IMUX8_6" + ], + [ + "CMT_FIFO_L_BYP1_3", + "CMT_TOP_BYP1_3" + ], + [ + "CMT_FIFO_L_FAN0_5", + "CMT_TOP_FAN0_5" + ], + [ + "CMT_FIFO_L_IMUX23_9", + "CMT_TOP_IMUX23_9" + ], + [ + "CMT_FIFO_EE4C2_6", + "CMT_TOP_EE4C2_6" + ], + [ + "CMT_FIFO_NW4END2_7", + "CMT_TOP_NW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX22_5", + "CMT_TOP_IMUX22_5" + ], + [ + "CMT_FIFO_EE2BEG0_9", + "CMT_TOP_EE2BEG0_9" + ], + [ + "CMT_FIFO_EE4B3_0", + "CMT_TOP_EE4B3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_5", + "CMT_TOP_LOGIC_OUTS_L_B7_5" + ], + [ + "CMT_FIFO_L_IMUX15_8", + "CMT_TOP_IMUX15_8" + ], + [ + "CMT_FIFO_NE4C1_3", + "CMT_TOP_NE4C1_3" + ], + [ + "CMT_FIFO_NE4BEG1_2", + "CMT_TOP_NE4BEG1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_7", + "CMT_TOP_LOGIC_OUTS_L_B19_7" + ], + [ + "CMT_FIFO_NW2A2_9", + "CMT_TOP_NW2A2_9" + ], + [ + "CMT_FIFO_L_PHASER_WRENABLE", + "CMT_PHASER_IN_C_WRENABLE_FIFO" + ], + [ + "CMT_FIFO_SW2A1_7", + "CMT_TOP_SW2A1_7" + ], + [ + "CMT_FIFO_L_IMUX1_8", + "CMT_TOP_IMUX1_8" + ], + [ + "CMT_FIFO_L_IMUX30_5", + "CMT_TOP_IMUX30_5" + ], + [ + "CMT_FIFO_L_IMUX39_11", + "CMT_TOP_IMUX39_11" + ], + [ + "CMT_FIFO_SE4BEG2_6", + "CMT_TOP_SE4BEG2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_2", + "CMT_TOP_LOGIC_OUTS_L_B1_2" + ], + [ + "CMT_FIFO_LH7_9", + "CMT_TOP_LH7_9" + ], + [ + "CMT_FIFO_EE4C0_2", + "CMT_TOP_EE4C0_2" + ], + [ + "CMT_FIFO_L_IMUX46_1", + "CMT_TOP_IMUX46_1" + ], + [ + "CMT_FIFO_SW2A3_6", + "CMT_TOP_SW2A3_6" + ], + [ + "CMT_FIFO_NW4END3_4", + "CMT_TOP_NW4END3_4" + ], + [ + "CMT_FIFO_L_BYP2_6", + "CMT_TOP_BYP2_6" + ], + [ + "CMT_FIFO_L_CLK1_3", + "CMT_TOP_CLK1_3" + ], + [ + "CMT_FIFO_L_CLK0_8", + "CMT_TOP_CLK0_8" + ], + [ + "CMT_FIFO_SW2A1_8", + "CMT_TOP_SW2A1_8" + ], + [ + "CMT_FIFO_WW2END1_3", + "CMT_TOP_WW2END1_3" + ], + [ + "CMT_FIFO_EE4BEG1_10", + "CMT_TOP_EE4BEG1_10" + ], + [ + "CMT_FIFO_WW2END1_10", + "CMT_TOP_WW2END1_10" + ], + [ + "CMT_FIFO_SE2A0_7", + "CMT_TOP_SE2A0_7" + ], + [ + "CMT_FIFO_NE4C3_4", + "CMT_TOP_NE4C3_4" + ], + [ + "CMT_FIFO_SW4END1_6", + "CMT_TOP_SW4END1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_0", + "CMT_TOP_LOGIC_OUTS_L_B18_0" + ], + [ + "CMT_FIFO_WW2END3_2", + "CMT_TOP_WW2END3_2" + ], + [ + "CMT_FIFO_EE2A1_1", + "CMT_TOP_EE2A1_1" + ], + [ + "CMT_FIFO_L_FAN1_1", + "CMT_TOP_FAN1_1" + ], + [ + "CMT_FIFO_LH9_10", + "CMT_TOP_LH9_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_7", + "CMT_TOP_LOGIC_OUTS_L_B13_7" + ], + [ + "CMT_FIFO_L_IMUX18_10", + "CMT_TOP_IMUX18_10" + ], + [ + "CMT_FIFO_L_IMUX10_9", + "CMT_TOP_IMUX10_9" + ], + [ + "CMT_FIFO_WW4B2_9", + "CMT_TOP_WW4B2_9" + ], + [ + "CMT_FIFO_L_BYP7_6", + "CMT_TOP_BYP7_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_8", + "CMT_TOP_LOGIC_OUTS_L_B22_8" + ], + [ + "CMT_FIFO_SE4BEG0_3", + "CMT_TOP_SE4BEG0_3" + ], + [ + "CMT_FIFO_LH7_1", + "CMT_TOP_LH7_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_8", + "CMT_TOP_LOGIC_OUTS_L_B4_8" + ], + [ + "CMT_FIFO_L_IMUX29_2", + "CMT_TOP_IMUX29_2" + ], + [ + "CMT_FIFO_NE4BEG1_4", + "CMT_TOP_NE4BEG1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_1", + "CMT_TOP_LOGIC_OUTS_L_B16_1" + ], + [ + "CMT_FIFO_WW4END0_0", + "CMT_TOP_WW4END0_0" + ], + [ + "CMT_FIFO_NW4END1_6", + "CMT_TOP_NW4END1_6" + ], + [ + "CMT_FIFO_NW4A1_2", + "CMT_TOP_NW4A1_2" + ], + [ + "CMT_FIFO_LH8_2", + "CMT_TOP_LH8_2" + ], + [ + "CMT_FIFO_WL1END0_5", + "CMT_TOP_WL1END0_5" + ], + [ + "CMT_FIFO_SE2A2_1", + "CMT_TOP_SE2A2_1" + ], + [ + "CMT_FIFO_NE2A0_4", + "CMT_TOP_NE2A0_4" + ], + [ + "CMT_FIFO_L_IMUX18_11", + "CMT_TOP_IMUX18_11" + ], + [ + "CMT_FIFO_L_IMUX25_7", + "CMT_TOP_IMUX25_7" + ], + [ + "CMT_FIFO_NW4END0_4", + "CMT_TOP_NW4END0_4" + ], + [ + "CMT_FIFO_WL1END1_8", + "CMT_TOP_WL1END1_8" + ], + [ + "CMT_FIFO_EE4B2_5", + "CMT_TOP_EE4B2_5" + ], + [ + "CMT_FIFO_NE4BEG0_0", + "CMT_TOP_NE4BEG0_0" + ], + [ + "CMT_FIFO_SW4END1_7", + "CMT_TOP_SW4END1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_6", + "CMT_TOP_LOGIC_OUTS_L_B10_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_6", + "CMT_TOP_LOGIC_OUTS_L_B14_6" + ], + [ + "CMT_FIFO_NE4BEG1_3", + "CMT_TOP_NE4BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX20_2", + "CMT_TOP_IMUX20_2" + ], + [ + "CMT_FIFO_SE4BEG0_5", + "CMT_TOP_SE4BEG0_5" + ], + [ + "CMT_FIFO_NW4END0_2", + "CMT_TOP_NW4END0_2" + ], + [ + "CMT_FIFO_NW4A2_6", + "CMT_TOP_NW4A2_6" + ], + [ + "CMT_FIFO_WW2A3_10", + "CMT_TOP_WW2A3_10" + ], + [ + "CMT_FIFO_L_IMUX40_7", + "CMT_TOP_IMUX40_7" + ], + [ + "CMT_FIFO_LH8_11", + "CMT_TOP_LH8_11" + ], + [ + "CMT_FIFO_L_IMUX19_2", + "CMT_TOP_IMUX19_2" + ], + [ + "CMT_FIFO_WL1END3_6", + "CMT_TOP_WL1END3_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "CMT_TOP_OCLK_5" + ], + [ + "CMT_FIFO_L_IMUX16_8", + "CMT_TOP_IMUX16_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_8", + "CMT_TOP_LOGIC_OUTS_L_B12_8" + ], + [ + "CMT_FIFO_EE4BEG0_1", + "CMT_TOP_EE4BEG0_1" + ], + [ + "CMT_FIFO_WR1END1_6", + "CMT_TOP_WR1END1_6" + ], + [ + "CMT_FIFO_NE2A2_3", + "CMT_TOP_NE2A2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_6", + "CMT_TOP_LOGIC_OUTS_L_B4_6" + ], + [ + "CMT_FIFO_WW4END1_5", + "CMT_TOP_WW4END1_5" + ], + [ + "CMT_FIFO_L_IMUX2_8", + "CMT_TOP_IMUX2_8" + ], + [ + "CMT_FIFO_NW4A2_9", + "CMT_TOP_NW4A2_9" + ], + [ + "CMT_FIFO_EL1BEG2_2", + "CMT_TOP_EL1BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX4_0", + "CMT_TOP_IMUX4_0" + ], + [ + "CMT_FIFO_EE4A1_7", + "CMT_TOP_EE4A1_7" + ], + [ + "CMT_FIFO_L_IMUX35_1", + "CMT_TOP_IMUX35_1" + ], + [ + "CMT_FIFO_WL1END2_7", + "CMT_TOP_WL1END2_7" + ], + [ + "CMT_FIFO_L_FAN5_3", + "CMT_TOP_FAN5_3" + ], + [ + "CMT_FIFO_LH1_3", + "CMT_TOP_LH1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_1", + "CMT_TOP_LOGIC_OUTS_L_B2_1" + ], + [ + "CMT_FIFO_L_IMUX11_8", + "CMT_TOP_IMUX11_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "CMT_TOP_ICLKDIV_4" + ], + [ + "CMT_FIFO_EE4B0_7", + "CMT_TOP_EE4B0_7" + ], + [ + "CMT_FIFO_WW4A0_9", + "CMT_TOP_WW4A0_9" + ], + [ + "CMT_FIFO_L_IMUX40_0", + "CMT_TOP_IMUX40_0" + ], + [ + "CMT_FIFO_L_CTRL0_5", + "CMT_TOP_CTRL0_5" + ], + [ + "CMT_FIFO_L_BYP2_2", + "CMT_TOP_BYP2_2" + ], + [ + "CMT_FIFO_L_IMUX19_0", + "CMT_TOP_IMUX19_0" + ], + [ + "CMT_FIFO_WR1END3_0", + "CMT_TOP_WR1END3_0" + ], + [ + "CMT_FIFO_EL1BEG0_5", + "CMT_TOP_EL1BEG0_5" + ], + [ + "CMT_FIFO_EE4B1_10", + "CMT_TOP_EE4B1_10" + ], + [ + "CMT_FIFO_EE4A1_3", + "CMT_TOP_EE4A1_3" + ], + [ + "CMT_FIFO_EE4BEG3_10", + "CMT_TOP_EE4BEG3_10" + ], + [ + "CMT_FIFO_EE2A1_3", + "CMT_TOP_EE2A1_3" + ], + [ + "CMT_FIFO_L_BYP6_0", + "CMT_TOP_BYP6_0" + ], + [ + "CMT_FIFO_NE4BEG2_9", + "CMT_TOP_NE4BEG2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_11", + "CMT_TOP_LOGIC_OUTS_L_B0_11" + ], + [ + "CMT_FIFO_SW4END2_0", + "CMT_TOP_SW4END2_0" + ], + [ + "CMT_FIFO_L_IMUX33_8", + "CMT_TOP_IMUX33_8" + ], + [ + "CMT_FIFO_SW4END3_5", + "CMT_TOP_SW4END3_5" + ], + [ + "CMT_FIFO_L_IMUX24_9", + "CMT_TOP_IMUX24_9" + ], + [ + "CMT_FIFO_SW2A3_11", + "CMT_TOP_SW2A3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_10", + "CMT_TOP_LOGIC_OUTS_L_B3_10" + ], + [ + "CMT_FIFO_L_IMUX37_4", + "CMT_TOP_IMUX37_4" + ], + [ + "CMT_FIFO_NW4A0_0", + "CMT_TOP_NW4A0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_8", + "CMT_TOP_LOGIC_OUTS_L_B9_8" + ], + [ + "CMT_FIFO_LH8_10", + "CMT_TOP_LH8_10" + ], + [ + "CMT_FIFO_NE4C2_11", + "CMT_TOP_NE4C2_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "CMT_TOP_ICLKDIV_8" + ], + [ + "CMT_FIFO_WW4B1_3", + "CMT_TOP_WW4B1_3" + ], + [ + "CMT_FIFO_WW4B0_1", + "CMT_TOP_WW4B0_1" + ], + [ + "CMT_FIFO_L_IMUX6_1", + "CMT_TOP_IMUX6_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_11", + "CMT_TOP_LOGIC_OUTS_L_B8_11" + ], + [ + "CMT_FIFO_WL1END1_9", + "CMT_TOP_WL1END1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_5", + "CMT_TOP_LOGIC_OUTS_L_B6_5" + ], + [ + "CMT_FIFO_L_IMUX20_1", + "CMT_TOP_IMUX20_1" + ], + [ + "CMT_FIFO_L_IMUX43_3", + "CMT_TOP_IMUX43_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_3", + "CMT_TOP_LOGIC_OUTS_L_B2_3" + ], + [ + "CMT_FIFO_L_FAN7_0", + "CMT_TOP_FAN7_0" + ], + [ + "CMT_FIFO_L_BYP6_10", + "CMT_TOP_BYP6_10" + ], + [ + "CMT_FIFO_EE4B0_6", + "CMT_TOP_EE4B0_6" + ], + [ + "CMT_FIFO_EE4BEG1_6", + "CMT_TOP_EE4BEG1_6" + ], + [ + "CMT_FIFO_EE2A2_10", + "CMT_TOP_EE2A2_10" + ], + [ + "CMT_FIFO_L_IMUX28_5", + "CMT_TOP_IMUX28_5" + ], + [ + "CMT_FIFO_L_IMUX20_3", + "CMT_TOP_IMUX20_3" + ], + [ + "CMT_FIFO_SE4BEG2_3", + "CMT_TOP_SE4BEG2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_1", + "CMT_TOP_LOGIC_OUTS_L_B6_1" + ], + [ + "CMT_FIFO_L_CLK0_2", + "CMT_TOP_CLK0_2" + ], + [ + "CMT_FIFO_SW4END2_1", + "CMT_TOP_SW4END2_1" + ], + [ + "CMT_FIFO_EE4A3_11", + "CMT_TOP_EE4A3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_7", + "CMT_TOP_LOGIC_OUTS_L_B6_7" + ], + [ + "CMT_FIFO_WL1END1_10", + "CMT_TOP_WL1END1_10" + ], + [ + "CMT_FIFO_LH2_11", + "CMT_TOP_LH2_11" + ], + [ + "CMT_FIFO_EL1BEG1_6", + "CMT_TOP_EL1BEG1_6" + ], + [ + "CMT_FIFO_NE4C1_10", + "CMT_TOP_NE4C1_10" + ], + [ + "CMT_FIFO_NE4C2_4", + "CMT_TOP_NE4C2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_4", + "CMT_TOP_LOGIC_OUTS_L_B3_4" + ], + [ + "CMT_FIFO_L_IMUX24_11", + "CMT_TOP_IMUX24_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_0", + "CMT_TOP_LOGIC_OUTS_L_B23_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_3", + "CMT_TOP_LOGIC_OUTS_L_B14_3" + ], + [ + "CMT_FIFO_L_IMUX27_10", + "CMT_TOP_IMUX27_10" + ], + [ + "CMT_FIFO_EE4A2_7", + "CMT_TOP_EE4A2_7" + ], + [ + "CMT_FIFO_EE4BEG2_9", + "CMT_TOP_EE4BEG2_9" + ], + [ + "CMT_FIFO_LH9_9", + "CMT_TOP_LH9_9" + ], + [ + "CMT_FIFO_WR1END0_2", + "CMT_TOP_WR1END0_2" + ], + [ + "CMT_FIFO_L_IMUX9_11", + "CMT_TOP_IMUX9_11" + ], + [ + "CMT_FIFO_WW4B1_7", + "CMT_TOP_WW4B1_7" + ], + [ + "CMT_FIFO_L_CLK0_1", + "CMT_TOP_CLK0_1" + ], + [ + "CMT_FIFO_WW2END2_9", + "CMT_TOP_WW2END2_9" + ], + [ + "CMT_FIFO_NE4BEG3_8", + "CMT_TOP_NE4BEG3_8" + ], + [ + "CMT_FIFO_WW4A2_0", + "CMT_TOP_WW4A2_0" + ], + [ + "CMT_FIFO_WL1END2_0", + "CMT_TOP_WL1END2_0" + ], + [ + "CMT_FIFO_EE2BEG2_7", + "CMT_TOP_EE2BEG2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_9", + "CMT_TOP_LOGIC_OUTS_L_B18_9" + ], + [ + "CMT_FIFO_WW2END1_9", + "CMT_TOP_WW2END1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_10", + "CMT_TOP_LOGIC_OUTS_L_B12_10" + ], + [ + "CMT_FIFO_WW4C2_11", + "CMT_TOP_WW4C2_11" + ], + [ + "CMT_FIFO_SE4C1_9", + "CMT_TOP_SE4C1_9" + ], + [ + "CMT_FIFO_WL1END2_9", + "CMT_TOP_WL1END2_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "CMT_TOP_OCLKDIV_10" + ], + [ + "CMT_FIFO_EE2BEG1_3", + "CMT_TOP_EE2BEG1_3" + ], + [ + "CMT_FIFO_WW2END2_1", + "CMT_TOP_WW2END2_1" + ], + [ + "CMT_FIFO_L_BYP5_0", + "CMT_TOP_BYP5_0" + ], + [ + "CMT_FIFO_NE4C2_10", + "CMT_TOP_NE4C2_10" + ], + [ + "CMT_FIFO_NE4BEG0_11", + "CMT_TOP_NE4BEG0_11" + ], + [ + "CMT_FIFO_NE4C2_0", + "CMT_TOP_NE4C2_0" + ], + [ + "CMT_FIFO_SW4A2_7", + "CMT_TOP_SW4A2_7" + ], + [ + "CMT_FIFO_SW4END1_3", + "CMT_TOP_SW4END1_3" + ], + [ + "CMT_FIFO_L_IMUX9_3", + "CMT_TOP_IMUX9_3" + ], + [ + "CMT_FIFO_LH2_0", + "CMT_TOP_LH2_0" + ], + [ + "CMT_FIFO_EL1BEG2_1", + "CMT_TOP_EL1BEG2_1" + ], + [ + "CMT_FIFO_WL1END2_1", + "CMT_TOP_WL1END2_1" + ], + [ + "CMT_FIFO_EE4C3_3", + "CMT_TOP_EE4C3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_6", + "CMT_TOP_LOGIC_OUTS_L_B15_6" + ], + [ + "CMT_FIFO_L_IMUX22_1", + "CMT_TOP_IMUX22_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_5", + "CMT_TOP_LOGIC_OUTS_L_B21_5" + ], + [ + "CMT_FIFO_SW4END1_0", + "CMT_TOP_SW4END1_0" + ], + [ + "CMT_FIFO_SE4C3_5", + "CMT_TOP_SE4C3_5" + ], + [ + "CMT_FIFO_EE4BEG0_8", + "CMT_TOP_EE4BEG0_8" + ], + [ + "CMT_FIFO_L_IMUX27_7", + "CMT_TOP_IMUX27_7" + ], + [ + "CMT_FIFO_NW4END0_8", + "CMT_TOP_NW4END0_8" + ], + [ + "CMT_FIFO_L_IMUX33_1", + "CMT_TOP_IMUX33_1" + ], + [ + "CMT_FIFO_L_IMUX11_0", + "CMT_TOP_IMUX11_0" + ], + [ + "CMT_FIFO_L_FAN0_0", + "CMT_TOP_FAN0_0" + ], + [ + "CMT_FIFO_SW4END2_9", + "CMT_TOP_SW4END2_9" + ], + [ + "CMT_FIFO_L_IMUX35_10", + "CMT_TOP_IMUX35_10" + ], + [ + "CMT_FIFO_WW2END3_7", + "CMT_TOP_WW2END3_7" + ], + [ + "CMT_FIFO_EE4BEG1_3", + "CMT_TOP_EE4BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX19_3", + "CMT_TOP_IMUX19_3" + ], + [ + "CMT_FIFO_EE4B3_9", + "CMT_TOP_EE4B3_9" + ], + [ + "CMT_FIFO_LH3_3", + "CMT_TOP_LH3_3" + ], + [ + "CMT_FIFO_EE2A1_5", + "CMT_TOP_EE2A1_5" + ], + [ + "CMT_FIFO_NW2A1_5", + "CMT_TOP_NW2A1_5" + ], + [ + "CMT_FIFO_EE2A0_2", + "CMT_TOP_EE2A0_2" + ], + [ + "CMT_FIFO_SW4A2_10", + "CMT_TOP_SW4A2_10" + ], + [ + "CMT_FIFO_EE4C2_2", + "CMT_TOP_EE4C2_2" + ], + [ + "CMT_FIFO_LH2_7", + "CMT_TOP_LH2_7" + ], + [ + "CMT_FIFO_EE4BEG3_6", + "CMT_TOP_EE4BEG3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_0", + "CMT_TOP_LOGIC_OUTS_L_B17_0" + ], + [ + "CMT_FIFO_L_IMUX44_8", + "CMT_TOP_IMUX44_8" + ], + [ + "CMT_FIFO_L_IMUX23_4", + "CMT_TOP_IMUX23_4" + ], + [ + "CMT_FIFO_SE4BEG2_10", + "CMT_TOP_SE4BEG2_10" + ], + [ + "CMT_FIFO_L_IMUX30_6", + "CMT_TOP_IMUX30_6" + ], + [ + "CMT_FIFO_L_CTRL0_3", + "CMT_TOP_CTRL0_3" + ], + [ + "CMT_FIFO_WR1END3_2", + "CMT_TOP_WR1END3_2" + ], + [ + "CMT_FIFO_SW4A0_3", + "CMT_TOP_SW4A0_3" + ], + [ + "CMT_FIFO_L_IMUX22_11", + "CMT_TOP_IMUX22_11" + ], + [ + "CMT_FIFO_LH9_3", + "CMT_TOP_LH9_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_11", + "CMT_TOP_LOGIC_OUTS_L_B11_11" + ], + [ + "CMT_FIFO_L_IMUX24_5", + "CMT_TOP_IMUX24_5" + ], + [ + "CMT_FIFO_WR1END1_11", + "CMT_TOP_WR1END1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_4", + "CMT_TOP_LOGIC_OUTS_L_B10_4" + ], + [ + "CMT_FIFO_SE4C0_6", + "CMT_TOP_SE4C0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_10", + "CMT_TOP_LOGIC_OUTS_L_B9_10" + ], + [ + "CMT_FIFO_LH4_10", + "CMT_TOP_LH4_10" + ], + [ + "CMT_FIFO_L_IMUX2_1", + "CMT_TOP_IMUX2_1" + ], + [ + "CMT_FIFO_LH7_6", + "CMT_TOP_LH7_6" + ], + [ + "CMT_FIFO_L_BYP5_7", + "CMT_TOP_BYP5_7" + ], + [ + "CMT_FIFO_L_IMUX4_11", + "CMT_TOP_IMUX4_11" + ], + [ + "CMT_FIFO_L_IMUX43_5", + "CMT_TOP_IMUX43_5" + ], + [ + "CMT_FIFO_L_IMUX18_5", + "CMT_TOP_IMUX18_5" + ], + [ + "CMT_FIFO_WW4END1_9", + "CMT_TOP_WW4END1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_1", + "CMT_TOP_LOGIC_OUTS_L_B9_1" + ], + [ + "CMT_FIFO_NE4BEG2_2", + "CMT_TOP_NE4BEG2_2" + ], + [ + "CMT_FIFO_WW2A3_8", + "CMT_TOP_WW2A3_8" + ], + [ + "CMT_FIFO_EL1BEG1_4", + "CMT_TOP_EL1BEG1_4" + ], + [ + "CMT_FIFO_SE2A1_7", + "CMT_TOP_SE2A1_7" + ], + [ + "CMT_FIFO_WW2A0_1", + "CMT_TOP_WW2A0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_6", + "CMT_TOP_LOGIC_OUTS_L_B0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_10", + "CMT_TOP_LOGIC_OUTS_L_B19_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "CMT_TOP_ICLK_7" + ], + [ + "CMT_FIFO_NW4END1_3", + "CMT_TOP_NW4END1_3" + ], + [ + "CMT_FIFO_WW4C2_8", + "CMT_TOP_WW4C2_8" + ], + [ + "CMT_FIFO_NE4BEG1_11", + "CMT_TOP_NE4BEG1_11" + ], + [ + "CMT_FIFO_NE2A1_4", + "CMT_TOP_NE2A1_4" + ], + [ + "CMT_FIFO_NE4BEG0_10", + "CMT_TOP_NE4BEG0_10" + ], + [ + "CMT_FIFO_L_BYP1_4", + "CMT_TOP_BYP1_4" + ], + [ + "CMT_FIFO_EL1BEG3_3", + "CMT_TOP_EL1BEG3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_7" + ], + [ + "CMT_FIFO_NW2A2_10", + "CMT_TOP_NW2A2_10" + ], + [ + "CMT_FIFO_L_IMUX32_0", + "CMT_TOP_IMUX32_0" + ], + [ + "CMT_FIFO_SE4C0_4", + "CMT_TOP_SE4C0_4" + ], + [ + "CMT_FIFO_L_IMUX1_1", + "CMT_TOP_IMUX1_1" + ], + [ + "CMT_FIFO_L_IMUX39_10", + "CMT_TOP_IMUX39_10" + ], + [ + "CMT_FIFO_EE4C1_10", + "CMT_TOP_EE4C1_10" + ], + [ + "CMT_FIFO_L_BYP1_10", + "CMT_TOP_BYP1_10" + ], + [ + "CMT_FIFO_SE4BEG3_11", + "CMT_TOP_SE4BEG3_11" + ], + [ + "CMT_FIFO_L_IMUX47_9", + "CMT_TOP_IMUX47_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_4", + "CMT_TOP_LOGIC_OUTS_L_B4_4" + ], + [ + "CMT_FIFO_WL1END3_8", + "CMT_TOP_WL1END3_8" + ], + [ + "CMT_FIFO_L_IMUX13_11", + "CMT_TOP_IMUX13_11" + ], + [ + "CMT_FIFO_L_BYP5_8", + "CMT_TOP_BYP5_8" + ], + [ + "CMT_FIFO_NE4C3_9", + "CMT_TOP_NE4C3_9" + ], + [ + "CMT_FIFO_NE4C3_10", + "CMT_TOP_NE4C3_10" + ], + [ + "CMT_FIFO_L_IMUX26_10", + "CMT_TOP_IMUX26_10" + ], + [ + "CMT_FIFO_L_IMUX17_0", + "CMT_TOP_IMUX17_0" + ], + [ + "CMT_FIFO_L_IMUX25_9", + "CMT_TOP_IMUX25_9" + ], + [ + "CMT_FIFO_NW2A1_2", + "CMT_TOP_NW2A1_2" + ], + [ + "CMT_FIFO_L_IMUX45_11", + "CMT_TOP_IMUX45_11" + ], + [ + "CMT_FIFO_WW4C3_5", + "CMT_TOP_WW4C3_5" + ], + [ + "CMT_FIFO_WW4END2_10", + "CMT_TOP_WW4END2_10" + ], + [ + "CMT_FIFO_EE2A0_10", + "CMT_TOP_EE2A0_10" + ], + [ + "CMT_FIFO_ER1BEG0_7", + "CMT_TOP_ER1BEG0_7" + ], + [ + "CMT_FIFO_EE4BEG3_3", + "CMT_TOP_EE4BEG3_3" + ], + [ + "CMT_FIFO_L_IMUX42_1", + "CMT_TOP_IMUX42_1" + ], + [ + "CMT_FIFO_NE2A1_5", + "CMT_TOP_NE2A1_5" + ], + [ + "CMT_FIFO_L_IMUX22_2", + "CMT_TOP_IMUX22_2" + ], + [ + "CMT_FIFO_WR1END1_1", + "CMT_TOP_WR1END1_1" + ], + [ + "CMT_FIFO_EE2BEG1_8", + "CMT_TOP_EE2BEG1_8" + ], + [ + "CMT_FIFO_EL1BEG3_8", + "CMT_TOP_EL1BEG3_8" + ], + [ + "CMT_FIFO_L_IMUX19_9", + "CMT_TOP_IMUX19_9" + ], + [ + "CMT_FIFO_ER1BEG1_6", + "CMT_TOP_ER1BEG1_6" + ], + [ + "CMT_FIFO_L_BYP3_6", + "CMT_TOP_BYP3_6" + ], + [ + "CMT_FIFO_SW2A3_5", + "CMT_TOP_SW2A3_5" + ], + [ + "CMT_FIFO_ER1BEG3_1", + "CMT_TOP_ER1BEG3_1" + ], + [ + "CMT_FIFO_L_BYP4_10", + "CMT_TOP_BYP4_10" + ], + [ + "CMT_FIFO_SW4A3_9", + "CMT_TOP_SW4A3_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "CMT_TOP_OCLK_3" + ], + [ + "CMT_FIFO_L_IMUX20_10", + "CMT_TOP_IMUX20_10" + ], + [ + "CMT_FIFO_NW2A2_11", + "CMT_TOP_NW2A2_11" + ], + [ + "CMT_FIFO_L_FAN2_8", + "CMT_TOP_FAN2_8" + ], + [ + "CMT_FIFO_L_FAN0_6", + "CMT_TOP_FAN0_6" + ], + [ + "CMT_FIFO_WW2A0_11", + "CMT_TOP_WW2A0_11" + ], + [ + "CMT_FIFO_WW4A1_3", + "CMT_TOP_WW4A1_3" + ], + [ + "CMT_FIFO_L_IMUX40_4", + "CMT_TOP_IMUX40_4" + ], + [ + "CMT_FIFO_L_IMUX46_2", + "CMT_TOP_IMUX46_2" + ], + [ + "CMT_FIFO_NW4END3_9", + "CMT_TOP_NW4END3_9" + ], + [ + "CMT_FIFO_ER1BEG2_6", + "CMT_TOP_ER1BEG2_6" + ], + [ + "CMT_FIFO_EE4A3_4", + "CMT_TOP_EE4A3_4" + ], + [ + "CMT_FIFO_EE4BEG2_1", + "CMT_TOP_EE4BEG2_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_11", + "CMT_TOP_LOGIC_OUTS_L_B17_11" + ], + [ + "CMT_FIFO_WW2A3_6", + "CMT_TOP_WW2A3_6" + ], + [ + "CMT_FIFO_WW4B0_9", + "CMT_TOP_WW4B0_9" + ], + [ + "CMT_FIFO_L_IMUX43_1", + "CMT_TOP_IMUX43_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_9", + "CMT_TOP_LOGIC_OUTS_L_B11_9" + ], + [ + "CMT_FIFO_L_IMUX16_6", + "CMT_TOP_IMUX16_6" + ], + [ + "CMT_FIFO_L_IMUX44_10", + "CMT_TOP_IMUX44_10" + ], + [ + "CMT_FIFO_L_IMUX4_8", + "CMT_TOP_IMUX4_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_5" + ], + [ + "CMT_FIFO_EE4BEG1_8", + "CMT_TOP_EE4BEG1_8" + ], + [ + "CMT_FIFO_WW4A0_3", + "CMT_TOP_WW4A0_3" + ], + [ + "CMT_FIFO_ER1BEG2_11", + "CMT_TOP_ER1BEG2_11" + ], + [ + "CMT_FIFO_EE2A0_6", + "CMT_TOP_EE2A0_6" + ], + [ + "CMT_FIFO_EE4BEG2_4", + "CMT_TOP_EE4BEG2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_10", + "CMT_TOP_LOGIC_OUTS_L_B16_10" + ], + [ + "CMT_FIFO_L_IMUX37_1", + "CMT_TOP_IMUX37_1" + ], + [ + "CMT_FIFO_LH2_1", + "CMT_TOP_LH2_1" + ], + [ + "CMT_FIFO_WW4B1_1", + "CMT_TOP_WW4B1_1" + ], + [ + "CMT_FIFO_WW4B1_0", + "CMT_TOP_WW4B1_0" + ], + [ + "CMT_FIFO_NW2A3_8", + "CMT_TOP_NW2A3_8" + ], + [ + "CMT_FIFO_NW4A1_11", + "CMT_TOP_NW4A1_11" + ], + [ + "CMT_FIFO_EE4A1_10", + "CMT_TOP_EE4A1_10" + ], + [ + "CMT_FIFO_WR1END1_2", + "CMT_TOP_WR1END1_2" + ], + [ + "CMT_FIFO_WW4B0_0", + "CMT_TOP_WW4B0_0" + ], + [ + "CMT_FIFO_L_IMUX29_10", + "CMT_TOP_IMUX29_10" + ], + [ + "CMT_FIFO_WW2END1_11", + "CMT_TOP_WW2END1_11" + ], + [ + "CMT_FIFO_L_BYP2_4", + "CMT_TOP_BYP2_4" + ], + [ + "CMT_FIFO_WW4C2_6", + "CMT_TOP_WW4C2_6" + ], + [ + "CMT_FIFO_L_BYP7_2", + "CMT_TOP_BYP7_2" + ], + [ + "CMT_FIFO_L_IMUX45_0", + "CMT_TOP_IMUX45_0" + ], + [ + "CMT_FIFO_L_IMUX42_10", + "CMT_TOP_IMUX42_10" + ], + [ + "CMT_FIFO_L_CLK0_6", + "CMT_TOP_CLK0_6" + ], + [ + "CMT_FIFO_SW2A3_8", + "CMT_TOP_SW2A3_8" + ], + [ + "CMT_FIFO_NW4END1_4", + "CMT_TOP_NW4END1_4" + ], + [ + "CMT_FIFO_L_CLK1_2", + "CMT_TOP_CLK1_2" + ], + [ + "CMT_FIFO_EE2BEG3_2", + "CMT_TOP_EE2BEG3_2" + ], + [ + "CMT_FIFO_L_IMUX3_3", + "CMT_TOP_IMUX3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_9", + "CMT_TOP_LOGIC_OUTS_L_B3_9" + ], + [ + "CMT_FIFO_WW4C0_1", + "CMT_TOP_WW4C0_1" + ], + [ + "CMT_FIFO_NE2A1_1", + "CMT_TOP_NE2A1_1" + ], + [ + "CMT_FIFO_L_BYP2_9", + "CMT_TOP_BYP2_9" + ], + [ + "CMT_FIFO_WW2A1_1", + "CMT_TOP_WW2A1_1" + ], + [ + "CMT_FIFO_L_FAN0_2", + "CMT_TOP_FAN0_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "CMT_TOP_OCLK_9" + ], + [ + "CMT_FIFO_SW2A2_6", + "CMT_TOP_SW2A2_6" + ], + [ + "CMT_FIFO_L_IMUX1_7", + "CMT_TOP_IMUX1_7" + ], + [ + "CMT_FIFO_SE4BEG2_4", + "CMT_TOP_SE4BEG2_4" + ], + [ + "CMT_FIFO_NW4A2_11", + "CMT_TOP_NW4A2_11" + ], + [ + "CMT_FIFO_EE4B0_11", + "CMT_TOP_EE4B0_11" + ], + [ + "CMT_FIFO_SW4A2_8", + "CMT_TOP_SW4A2_8" + ], + [ + "CMT_FIFO_WR1END3_1", + "CMT_TOP_WR1END3_1" + ], + [ + "CMT_FIFO_L_IMUX34_8", + "CMT_TOP_IMUX34_8" + ], + [ + "CMT_FIFO_L_IMUX47_3", + "CMT_TOP_IMUX47_3" + ], + [ + "CMT_FIFO_EE4A3_5", + "CMT_TOP_EE4A3_5" + ], + [ + "CMT_FIFO_EE4A0_0", + "CMT_TOP_EE4A0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_8", + "CMT_TOP_LOGIC_OUTS_L_B6_8" + ], + [ + "CMT_FIFO_SE4BEG1_10", + "CMT_TOP_SE4BEG1_10" + ], + [ + "CMT_FIFO_LH2_10", + "CMT_TOP_LH2_10" + ], + [ + "CMT_FIFO_SE4C2_7", + "CMT_TOP_SE4C2_7" + ], + [ + "CMT_FIFO_L_IMUX15_5", + "CMT_TOP_IMUX15_5" + ], + [ + "CMT_FIFO_EE4C3_6", + "CMT_TOP_EE4C3_6" + ], + [ + "CMT_FIFO_L_IMUX44_5", + "CMT_TOP_IMUX44_5" + ], + [ + "CMT_FIFO_WW4C0_5", + "CMT_TOP_WW4C0_5" + ], + [ + "CMT_FIFO_L_IMUX31_10", + "CMT_TOP_IMUX31_10" + ], + [ + "CMT_FIFO_EL1BEG2_0", + "CMT_TOP_EL1BEG2_0" + ], + [ + "CMT_FIFO_SE4BEG0_7", + "CMT_TOP_SE4BEG0_7" + ], + [ + "CMT_FIFO_WW4END0_3", + "CMT_TOP_WW4END0_3" + ], + [ + "CMT_FIFO_WL1END1_7", + "CMT_TOP_WL1END1_7" + ], + [ + "CMT_FIFO_MONITOR_N_2", + "CMT_TOP_MONITOR_N_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_10", + "CMT_TOP_LOGIC_OUTS_L_B14_10" + ], + [ + "CMT_FIFO_NE4BEG0_4", + "CMT_TOP_NE4BEG0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_11", + "CMT_TOP_LOGIC_OUTS_L_B12_11" + ], + [ + "CMT_FIFO_SE4BEG2_5", + "CMT_TOP_SE4BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX17_2", + "CMT_TOP_IMUX17_2" + ], + [ + "CMT_FIFO_L_IMUX16_2", + "CMT_TOP_IMUX16_2" + ], + [ + "CMT_FIFO_WW4END1_8", + "CMT_TOP_WW4END1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_0", + "CMT_TOP_LOGIC_OUTS_L_B10_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_7", + "CMT_TOP_LOGIC_OUTS_L_B1_7" + ], + [ + "CMT_FIFO_L_IMUX20_0", + "CMT_TOP_IMUX20_0" + ], + [ + "CMT_FIFO_SE2A3_9", + "CMT_TOP_SE2A3_9" + ], + [ + "CMT_FIFO_EE4C2_0", + "CMT_TOP_EE4C2_0" + ], + [ + "CMT_FIFO_L_FAN3_5", + "CMT_TOP_FAN3_5" + ], + [ + "CMT_FIFO_WW4B0_2", + "CMT_TOP_WW4B0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_2", + "CMT_TOP_LOGIC_OUTS_L_B9_2" + ], + [ + "CMT_FIFO_L_IMUX26_1", + "CMT_TOP_IMUX26_1" + ], + [ + "CMT_FIFO_EE4C3_1", + "CMT_TOP_EE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX38_3", + "CMT_TOP_IMUX38_3" + ], + [ + "CMT_FIFO_L_IMUX36_9", + "CMT_TOP_IMUX36_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_5", + "CMT_TOP_LOGIC_OUTS_L_B1_5" + ], + [ + "CMT_FIFO_EE4C0_1", + "CMT_TOP_EE4C0_1" + ], + [ + "CMT_FIFO_L_IMUX2_7", + "CMT_TOP_IMUX2_7" + ], + [ + "CMT_FIFO_NE4BEG1_8", + "CMT_TOP_NE4BEG1_8" + ], + [ + "CMT_FIFO_WW2A1_11", + "CMT_TOP_WW2A1_11" + ], + [ + "CMT_FIFO_L_CLK1_5", + "CMT_TOP_CLK1_5" + ], + [ + "CMT_FIFO_L_FAN0_3", + "CMT_TOP_FAN0_3" + ], + [ + "CMT_FIFO_WW4C3_7", + "CMT_TOP_WW4C3_7" + ], + [ + "CMT_FIFO_EE2BEG2_10", + "CMT_TOP_EE2BEG2_10" + ], + [ + "CMT_FIFO_SE4C2_5", + "CMT_TOP_SE4C2_5" + ], + [ + "CMT_FIFO_SW2A0_4", + "CMT_TOP_SW2A0_4" + ], + [ + "CMT_FIFO_L_IMUX2_3", + "CMT_TOP_IMUX2_3" + ], + [ + "CMT_FIFO_WR1END2_8", + "CMT_TOP_WR1END2_8" + ], + [ + "CMT_FIFO_L_IMUX8_0", + "CMT_TOP_IMUX8_0" + ], + [ + "CMT_FIFO_EE2BEG1_2", + "CMT_TOP_EE2BEG1_2" + ], + [ + "CMT_FIFO_WW2END0_3", + "CMT_TOP_WW2END0_3" + ], + [ + "CMT_FIFO_EE4A0_2", + "CMT_TOP_EE4A0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_2", + "CMT_TOP_LOGIC_OUTS_L_B10_2" + ], + [ + "CMT_FIFO_WW2END0_8", + "CMT_TOP_WW2END0_8" + ], + [ + "CMT_FIFO_L_FAN1_8", + "CMT_TOP_FAN1_8" + ], + [ + "CMT_FIFO_L_IMUX40_9", + "CMT_TOP_IMUX40_9" + ], + [ + "CMT_FIFO_WW2END3_9", + "CMT_TOP_WW2END3_9" + ], + [ + "CMT_FIFO_EE4C1_6", + "CMT_TOP_EE4C1_6" + ], + [ + "CMT_FIFO_L_BYP5_5", + "CMT_TOP_BYP5_5" + ], + [ + "CMT_FIFO_LH5_8", + "CMT_TOP_LH5_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_9", + "CMT_TOP_LOGIC_OUTS_L_B14_9" + ], + [ + "CMT_FIFO_L_FAN6_11", + "CMT_TOP_FAN6_11" + ], + [ + "CMT_FIFO_WW2A2_3", + "CMT_TOP_WW2A2_3" + ], + [ + "CMT_FIFO_WW2A3_3", + "CMT_TOP_WW2A3_3" + ], + [ + "CMT_FIFO_L_IMUX4_2", + "CMT_TOP_IMUX4_2" + ], + [ + "CMT_FIFO_L_IMUX36_4", + "CMT_TOP_IMUX36_4" + ], + [ + "CMT_FIFO_LH1_11", + "CMT_TOP_LH1_11" + ], + [ + "CMT_FIFO_WW4B3_0", + "CMT_TOP_WW4B3_0" + ], + [ + "CMT_FIFO_EE4B3_7", + "CMT_TOP_EE4B3_7" + ], + [ + "CMT_FIFO_LH5_11", + "CMT_TOP_LH5_11" + ], + [ + "CMT_FIFO_NW2A1_11", + "CMT_TOP_NW2A1_11" + ], + [ + "CMT_FIFO_SE4C2_9", + "CMT_TOP_SE4C2_9" + ], + [ + "CMT_FIFO_L_CTRL1_11", + "CMT_TOP_CTRL1_11" + ], + [ + "CMT_FIFO_SW2A0_5", + "CMT_TOP_SW2A0_5" + ], + [ + "CMT_FIFO_LH7_10", + "CMT_TOP_LH7_10" + ], + [ + "CMT_FIFO_L_IMUX25_0", + "CMT_TOP_IMUX25_0" + ], + [ + "CMT_FIFO_L_FAN2_5", + "CMT_TOP_FAN2_5" + ], + [ + "CMT_FIFO_NE4BEG3_2", + "CMT_TOP_NE4BEG3_2" + ], + [ + "CMT_FIFO_EE4B2_4", + "CMT_TOP_EE4B2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_4", + "CMT_TOP_LOGIC_OUTS_L_B19_4" + ], + [ + "CMT_FIFO_NE2A1_0", + "CMT_TOP_NE2A1_0" + ], + [ + "CMT_FIFO_WW2A0_6", + "CMT_TOP_WW2A0_6" + ], + [ + "CMT_FIFO_L_IMUX19_11", + "CMT_TOP_IMUX19_11" + ], + [ + "CMT_FIFO_L_IMUX3_5", + "CMT_TOP_IMUX3_5" + ], + [ + "CMT_FIFO_L_BYP7_1", + "CMT_TOP_BYP7_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_8", + "CMT_TOP_LOGIC_OUTS_L_B7_8" + ], + [ + "CMT_FIFO_WW4C3_2", + "CMT_TOP_WW4C3_2" + ], + [ + "CMT_FIFO_L_IMUX18_0", + "CMT_TOP_IMUX18_0" + ], + [ + "CMT_FIFO_LH2_9", + "CMT_TOP_LH2_9" + ], + [ + "CMT_FIFO_L_IMUX46_6", + "CMT_TOP_IMUX46_6" + ], + [ + "CMT_FIFO_L_IMUX29_9", + "CMT_TOP_IMUX29_9" + ], + [ + "CMT_FIFO_SE4C1_2", + "CMT_TOP_SE4C1_2" + ], + [ + "CMT_FIFO_L_IMUX24_6", + "CMT_TOP_IMUX24_6" + ], + [ + "CMT_FIFO_EE4A0_9", + "CMT_TOP_EE4A0_9" + ], + [ + "CMT_FIFO_SE2A3_3", + "CMT_TOP_SE2A3_3" + ], + [ + "CMT_FIFO_L_IMUX46_9", + "CMT_TOP_IMUX46_9" + ], + [ + "CMT_FIFO_NE4C0_5", + "CMT_TOP_NE4C0_5" + ], + [ + "CMT_FIFO_WW2A0_4", + "CMT_TOP_WW2A0_4" + ], + [ + "CMT_FIFO_L_FAN7_6", + "CMT_TOP_FAN7_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_8", + "CMT_TOP_LOGIC_OUTS_L_B13_8" + ], + [ + "CMT_FIFO_L_IMUX6_10", + "CMT_TOP_IMUX6_10" + ], + [ + "CMT_FIFO_SW2A1_4", + "CMT_TOP_SW2A1_4" + ], + [ + "CMT_FIFO_NE4BEG2_1", + "CMT_TOP_NE4BEG2_1" + ], + [ + "CMT_FIFO_ER1BEG0_8", + "CMT_TOP_ER1BEG0_8" + ], + [ + "CMT_FIFO_L_BYP1_9", + "CMT_TOP_BYP1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_2", + "CMT_TOP_LOGIC_OUTS_L_B22_2" + ], + [ + "CMT_FIFO_L_IMUX26_9", + "CMT_TOP_IMUX26_9" + ], + [ + "CMT_FIFO_WW4B1_8", + "CMT_TOP_WW4B1_8" + ], + [ + "CMT_FIFO_L_FAN6_0", + "CMT_TOP_FAN6_0" + ], + [ + "CMT_FIFO_L_IMUX20_4", + "CMT_TOP_IMUX20_4" + ], + [ + "CMT_FIFO_NW2A3_2", + "CMT_TOP_NW2A3_2" + ], + [ + "CMT_FIFO_NE4C1_11", + "CMT_TOP_NE4C1_11" + ], + [ + "CMT_FIFO_L_FAN1_11", + "CMT_TOP_FAN1_11" + ], + [ + "CMT_FIFO_LH10_3", + "CMT_TOP_LH10_3" + ], + [ + "CMT_FIFO_SE4C0_11", + "CMT_TOP_SE4C0_11" + ], + [ + "CMT_FIFO_L_FAN4_7", + "CMT_TOP_FAN4_7" + ], + [ + "CMT_FIFO_L_FAN2_3", + "CMT_TOP_FAN2_3" + ], + [ + "CMT_FIFO_NW4END3_2", + "CMT_TOP_NW4END3_2" + ], + [ + "CMT_FIFO_WW4A3_11", + "CMT_TOP_WW4A3_11" + ], + [ + "CMT_FIFO_L_IMUX25_8", + "CMT_TOP_IMUX25_8" + ], + [ + "CMT_FIFO_L_BYP5_2", + "CMT_TOP_BYP5_2" + ], + [ + "CMT_FIFO_EE4A1_9", + "CMT_TOP_EE4A1_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "CMT_TOP_OCLKDIV_3" + ], + [ + "CMT_FIFO_SE2A0_0", + "CMT_TOP_SE2A0_0" + ], + [ + "CMT_FIFO_L_CLK0_4", + "CMT_TOP_CLK0_4" + ], + [ + "CMT_FIFO_L_IMUX19_8", + "CMT_TOP_IMUX19_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_9", + "CMT_TOP_LOGIC_OUTS_L_B1_9" + ], + [ + "CMT_FIFO_NW2A0_4", + "CMT_TOP_NW2A0_4" + ], + [ + "CMT_FIFO_SE4C3_2", + "CMT_TOP_SE4C3_2" + ], + [ + "CMT_FIFO_SE2A1_5", + "CMT_TOP_SE2A1_5" + ], + [ + "CMT_FIFO_EE4BEG1_0", + "CMT_TOP_EE4BEG1_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_8", + "CMT_TOP_LOGIC_OUTS_L_B20_8" + ], + [ + "CMT_FIFO_L_IMUX45_5", + "CMT_TOP_IMUX45_5" + ], + [ + "CMT_FIFO_EL1BEG1_2", + "CMT_TOP_EL1BEG1_2" + ], + [ + "CMT_FIFO_L_FAN0_7", + "CMT_TOP_FAN0_7" + ], + [ + "CMT_FIFO_EE4B1_1", + "CMT_TOP_EE4B1_1" + ], + [ + "CMT_FIFO_L_IMUX21_5", + "CMT_TOP_IMUX21_5" + ], + [ + "CMT_FIFO_EL1BEG3_5", + "CMT_TOP_EL1BEG3_5" + ], + [ + "CMT_FIFO_EE4BEG1_2", + "CMT_TOP_EE4BEG1_2" + ], + [ + "CMT_FIFO_EE4BEG2_2", + "CMT_TOP_EE4BEG2_2" + ], + [ + "CMT_FIFO_LH8_6", + "CMT_TOP_LH8_6" + ], + [ + "CMT_FIFO_L_IMUX24_2", + "CMT_TOP_IMUX24_2" + ], + [ + "CMT_FIFO_L_IMUX32_4", + "CMT_TOP_IMUX32_4" + ], + [ + "CMT_FIFO_ER1BEG0_2", + "CMT_TOP_ER1BEG0_2" + ], + [ + "CMT_FIFO_EE4C3_5", + "CMT_TOP_EE4C3_5" + ], + [ + "CMT_FIFO_L_IMUX41_11", + "CMT_TOP_IMUX41_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_10", + "CMT_TOP_LOGIC_OUTS_L_B8_10" + ], + [ + "CMT_FIFO_WW4B3_6", + "CMT_TOP_WW4B3_6" + ], + [ + "CMT_FIFO_NW2A1_6", + "CMT_TOP_NW2A1_6" + ], + [ + "CMT_FIFO_L_BYP1_11", + "CMT_TOP_BYP1_11" + ], + [ + "CMT_FIFO_WW2A3_2", + "CMT_TOP_WW2A3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_2", + "CMT_TOP_LOGIC_OUTS_L_B11_2" + ], + [ + "CMT_FIFO_L_IMUX45_8", + "CMT_TOP_IMUX45_8" + ], + [ + "CMT_FIFO_WW2A1_10", + "CMT_TOP_WW2A1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_9", + "CMT_TOP_LOGIC_OUTS_L_B10_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_7", + "CMT_TOP_LOGIC_OUTS_L_B4_7" + ], + [ + "CMT_FIFO_L_IMUX6_6", + "CMT_TOP_IMUX6_6" + ], + [ + "CMT_FIFO_L_IMUX12_10", + "CMT_TOP_IMUX12_10" + ], + [ + "CMT_FIFO_L_CTRL0_0", + "CMT_TOP_CTRL0_0" + ], + [ + "CMT_FIFO_SW4A0_11", + "CMT_TOP_SW4A0_11" + ], + [ + "CMT_FIFO_L_FAN5_4", + "CMT_TOP_FAN5_4" + ], + [ + "CMT_FIFO_WW2END1_7", + "CMT_TOP_WW2END1_7" + ], + [ + "CMT_FIFO_WW2END0_0", + "CMT_TOP_WW2END0_0" + ], + [ + "CMT_FIFO_EE4B0_0", + "CMT_TOP_EE4B0_0" + ], + [ + "CMT_FIFO_NW4A1_6", + "CMT_TOP_NW4A1_6" + ], + [ + "CMT_FIFO_SE4BEG2_7", + "CMT_TOP_SE4BEG2_7" + ], + [ + "CMT_FIFO_SW4END0_5", + "CMT_TOP_SW4END0_5" + ], + [ + "CMT_FIFO_EE2BEG0_5", + "CMT_TOP_EE2BEG0_5" + ], + [ + "CMT_FIFO_L_CTRL1_7", + "CMT_TOP_CTRL1_7" + ], + [ + "CMT_FIFO_SW4END3_0", + "CMT_TOP_SW4END3_0" + ], + [ + "CMT_FIFO_SW4A2_1", + "CMT_TOP_SW4A2_1" + ], + [ + "CMT_FIFO_EL1BEG3_2", + "CMT_TOP_EL1BEG3_2" + ], + [ + "CMT_FIFO_SE4BEG1_11", + "CMT_TOP_SE4BEG1_11" + ], + [ + "CMT_FIFO_NW4END3_5", + "CMT_TOP_NW4END3_5" + ], + [ + "CMT_FIFO_L_IMUX16_1", + "CMT_TOP_IMUX16_1" + ], + [ + "CMT_FIFO_WW4C3_4", + "CMT_TOP_WW4C3_4" + ], + [ + "CMT_FIFO_L_FAN0_10", + "CMT_TOP_FAN0_10" + ], + [ + "CMT_FIFO_L_FAN2_1", + "CMT_TOP_FAN2_1" + ], + [ + "CMT_FIFO_L_BYP3_8", + "CMT_TOP_BYP3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_11", + "CMT_TOP_LOGIC_OUTS_L_B20_11" + ], + [ + "CMT_FIFO_L_CLK0_3", + "CMT_TOP_CLK0_3" + ], + [ + "CMT_FIFO_WW4C0_8", + "CMT_TOP_WW4C0_8" + ], + [ + "CMT_FIFO_L_IMUX31_4", + "CMT_TOP_IMUX31_4" + ], + [ + "CMT_FIFO_L_IMUX43_7", + "CMT_TOP_IMUX43_7" + ], + [ + "CMT_FIFO_SE4C0_1", + "CMT_TOP_SE4C0_1" + ], + [ + "CMT_FIFO_EE4C3_8", + "CMT_TOP_EE4C3_8" + ], + [ + "CMT_FIFO_L_IMUX31_11", + "CMT_TOP_IMUX31_11" + ], + [ + "CMT_FIFO_NW4END0_0", + "CMT_TOP_NW4END0_0" + ], + [ + "CMT_FIFO_EE4C3_10", + "CMT_TOP_EE4C3_10" + ], + [ + "CMT_FIFO_NW4A1_1", + "CMT_TOP_NW4A1_1" + ], + [ + "CMT_FIFO_LH1_8", + "CMT_TOP_LH1_8" + ], + [ + "CMT_FIFO_L_IMUX3_11", + "CMT_TOP_IMUX3_11" + ], + [ + "CMT_FIFO_WW2A0_10", + "CMT_TOP_WW2A0_10" + ], + [ + "CMT_FIFO_L_FAN4_0", + "CMT_TOP_FAN4_0" + ], + [ + "CMT_FIFO_WW2A2_6", + "CMT_TOP_WW2A2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_0", + "CMT_TOP_LOGIC_OUTS_L_B16_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_1", + "CMT_TOP_LOGIC_OUTS_L_B18_1" + ], + [ + "CMT_FIFO_L_IMUX42_6", + "CMT_TOP_IMUX42_6" + ], + [ + "CMT_FIFO_L_IMUX37_2", + "CMT_TOP_IMUX37_2" + ], + [ + "CMT_FIFO_EE4C2_11", + "CMT_TOP_EE4C2_11" + ], + [ + "CMT_FIFO_LH5_4", + "CMT_TOP_LH5_4" + ], + [ + "CMT_FIFO_EE2BEG1_0", + "CMT_TOP_EE2BEG1_0" + ], + [ + "CMT_FIFO_L_IMUX38_6", + "CMT_TOP_IMUX38_6" + ], + [ + "CMT_FIFO_EE4C2_8", + "CMT_TOP_EE4C2_8" + ], + [ + "CMT_FIFO_EE4BEG2_5", + "CMT_TOP_EE4BEG2_5" + ], + [ + "CMT_FIFO_WW4C1_7", + "CMT_TOP_WW4C1_7" + ], + [ + "CMT_FIFO_WW4C2_7", + "CMT_TOP_WW4C2_7" + ], + [ + "CMT_FIFO_L_BYP3_9", + "CMT_TOP_BYP3_9" + ], + [ + "CMT_FIFO_L_FAN4_11", + "CMT_TOP_FAN4_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_0", + "CMT_TOP_LOGIC_OUTS_L_B19_0" + ], + [ + "CMT_FIFO_SW4END0_4", + "CMT_TOP_SW4END0_4" + ], + [ + "CMT_FIFO_L_IMUX35_2", + "CMT_TOP_IMUX35_2" + ], + [ + "CMT_FIFO_WW4C1_10", + "CMT_TOP_WW4C1_10" + ], + [ + "CMT_FIFO_EE2A2_6", + "CMT_TOP_EE2A2_6" + ], + [ + "CMT_FIFO_EE4C3_11", + "CMT_TOP_EE4C3_11" + ], + [ + "CMT_FIFO_L_BYP7_10", + "CMT_TOP_BYP7_10" + ], + [ + "CMT_FIFO_L_IMUX29_8", + "CMT_TOP_IMUX29_8" + ], + [ + "CMT_FIFO_NE2A0_0", + "CMT_TOP_NE2A0_0" + ], + [ + "CMT_FIFO_NE2A0_9", + "CMT_TOP_NE2A0_9" + ], + [ + "CMT_FIFO_L_IMUX9_10", + "CMT_TOP_IMUX9_10" + ], + [ + "CMT_FIFO_WW2END1_0", + "CMT_TOP_WW2END1_0" + ], + [ + "CMT_FIFO_SE2A1_10", + "CMT_TOP_SE2A1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_5", + "CMT_TOP_LOGIC_OUTS_L_B16_5" + ], + [ + "CMT_FIFO_L_IMUX34_6", + "CMT_TOP_IMUX34_6" + ], + [ + "CMT_FIFO_L_IMUX43_11", + "CMT_TOP_IMUX43_11" + ], + [ + "CMT_FIFO_EL1BEG2_10", + "CMT_TOP_EL1BEG2_10" + ], + [ + "CMT_FIFO_WW2END3_3", + "CMT_TOP_WW2END3_3" + ], + [ + "CMT_FIFO_L_IMUX15_2", + "CMT_TOP_IMUX15_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "CMT_TOP_OCLK_4" + ], + [ + "CMT_FIFO_EE4A3_1", + "CMT_TOP_EE4A3_1" + ], + [ + "CMT_FIFO_L_IMUX33_6", + "CMT_TOP_IMUX33_6" + ], + [ + "CMT_FIFO_WL1END3_5", + "CMT_TOP_WL1END3_5" + ], + [ + "CMT_FIFO_NE4C1_1", + "CMT_TOP_NE4C1_1" + ], + [ + "CMT_FIFO_ER1BEG0_3", + "CMT_TOP_ER1BEG0_3" + ], + [ + "CMT_FIFO_LH4_5", + "CMT_TOP_LH4_5" + ], + [ + "CMT_FIFO_L_IMUX16_3", + "CMT_TOP_IMUX16_3" + ], + [ + "CMT_FIFO_NE2A3_9", + "CMT_TOP_NE2A3_9" + ], + [ + "CMT_FIFO_NE4BEG2_10", + "CMT_TOP_NE4BEG2_10" + ], + [ + "CMT_FIFO_L_BYP3_1", + "CMT_TOP_BYP3_1" + ], + [ + "CMT_FIFO_WW4C3_11", + "CMT_TOP_WW4C3_11" + ], + [ + "CMT_FIFO_EL1BEG1_0", + "CMT_TOP_EL1BEG1_0" + ], + [ + "CMT_FIFO_L_CTRL0_11", + "CMT_TOP_CTRL0_11" + ], + [ + "CMT_FIFO_L_IMUX18_1", + "CMT_TOP_IMUX18_1" + ], + [ + "CMT_FIFO_SE4BEG0_2", + "CMT_TOP_SE4BEG0_2" + ], + [ + "CMT_FIFO_EE2BEG1_7", + "CMT_TOP_EE2BEG1_7" + ], + [ + "CMT_FIFO_EL1BEG1_7", + "CMT_TOP_EL1BEG1_7" + ], + [ + "CMT_FIFO_LH12_10", + "CMT_TOP_LH12_10" + ], + [ + "CMT_FIFO_ER1BEG0_6", + "CMT_TOP_ER1BEG0_6" + ], + [ + "CMT_FIFO_LH11_11", + "CMT_TOP_LH11_11" + ], + [ + "CMT_FIFO_L_IMUX5_6", + "CMT_TOP_IMUX5_6" + ], + [ + "CMT_FIFO_WW2END1_6", + "CMT_TOP_WW2END1_6" + ], + [ + "CMT_FIFO_WW4A2_6", + "CMT_TOP_WW4A2_6" + ], + [ + "CMT_FIFO_L_FAN4_2", + "CMT_TOP_FAN4_2" + ], + [ + "CMT_FIFO_WL1END0_6", + "CMT_TOP_WL1END0_6" + ], + [ + "CMT_FIFO_WW4END0_9", + "CMT_TOP_WW4END0_9" + ], + [ + "CMT_FIFO_WW4A0_11", + "CMT_TOP_WW4A0_11" + ], + [ + "CMT_FIFO_EE4B3_1", + "CMT_TOP_EE4B3_1" + ], + [ + "CMT_FIFO_L_IMUX19_1", + "CMT_TOP_IMUX19_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_3", + "CMT_TOP_LOGIC_OUTS_L_B3_3" + ], + [ + "CMT_FIFO_NW4A2_2", + "CMT_TOP_NW4A2_2" + ], + [ + "CMT_FIFO_L_IMUX3_10", + "CMT_TOP_IMUX3_10" + ], + [ + "CMT_FIFO_EE4C3_9", + "CMT_TOP_EE4C3_9" + ], + [ + "CMT_FIFO_SW4END2_8", + "CMT_TOP_SW4END2_8" + ], + [ + "CMT_FIFO_SE4C2_2", + "CMT_TOP_SE4C2_2" + ], + [ + "CMT_FIFO_NE2A2_11", + "CMT_TOP_NE2A2_11" + ], + [ + "CMT_FIFO_L_IMUX36_8", + "CMT_TOP_IMUX36_8" + ], + [ + "CMT_FIFO_L_IMUX44_11", + "CMT_TOP_IMUX44_11" + ], + [ + "CMT_FIFO_LH11_4", + "CMT_TOP_LH11_4" + ], + [ + "CMT_FIFO_L_BYP7_11", + "CMT_TOP_BYP7_11" + ], + [ + "CMT_FIFO_LH1_1", + "CMT_TOP_LH1_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "CMT_TOP_OCLKDIV_5" + ], + [ + "CMT_FIFO_LH6_3", + "CMT_TOP_LH6_3" + ], + [ + "CMT_FIFO_WW4C2_3", + "CMT_TOP_WW4C2_3" + ], + [ + "CMT_FIFO_NE4BEG3_9", + "CMT_TOP_NE4BEG3_9" + ], + [ + "CMT_FIFO_LH7_3", + "CMT_TOP_LH7_3" + ], + [ + "CMT_FIFO_L_IMUX1_5", + "CMT_TOP_IMUX1_5" + ], + [ + "CMT_FIFO_SW4A1_10", + "CMT_TOP_SW4A1_10" + ], + [ + "CMT_FIFO_L_FAN0_11", + "CMT_TOP_FAN0_11" + ], + [ + "CMT_FIFO_EE2BEG1_10", + "CMT_TOP_EE2BEG1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_5", + "CMT_TOP_LOGIC_OUTS_L_B3_5" + ], + [ + "FIFO_DQS_IOTOPHASER_1", + "CMT_PHASER_UP_DQS_TO_PHASER_C" + ], + [ + "CMT_FIFO_L_IMUX45_10", + "CMT_TOP_IMUX45_10" + ], + [ + "CMT_FIFO_NW4END0_7", + "CMT_TOP_NW4END0_7" + ], + [ + "CMT_FIFO_L_IMUX41_2", + "CMT_TOP_IMUX41_2" + ], + [ + "CMT_FIFO_EE4A1_4", + "CMT_TOP_EE4A1_4" + ], + [ + "CMT_FIFO_NE2A3_7", + "CMT_TOP_NE2A3_7" + ], + [ + "CMT_FIFO_L_IMUX19_5", + "CMT_TOP_IMUX19_5" + ], + [ + "CMT_FIFO_NE4C2_6", + "CMT_TOP_NE4C2_6" + ], + [ + "CMT_FIFO_L_IMUX0_6", + "CMT_TOP_IMUX0_6" + ], + [ + "CMT_FIFO_SE4C3_6", + "CMT_TOP_SE4C3_6" + ], + [ + "CMT_FIFO_L_IMUX12_6", + "CMT_TOP_IMUX12_6" + ], + [ + "CMT_FIFO_SE4C0_8", + "CMT_TOP_SE4C0_8" + ], + [ + "CMT_FIFO_L_IMUX38_4", + "CMT_TOP_IMUX38_4" + ], + [ + "CMT_FIFO_EE4C2_9", + "CMT_TOP_EE4C2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_9", + "CMT_TOP_LOGIC_OUTS_L_B13_9" + ], + [ + "CMT_FIFO_L_IMUX16_11", + "CMT_TOP_IMUX16_11" + ], + [ + "CMT_FIFO_L_IMUX28_7", + "CMT_TOP_IMUX28_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_1", + "CMT_TOP_LOGIC_OUTS_L_B21_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_5", + "CMT_TOP_LOGIC_OUTS_L_B11_5" + ], + [ + "CMT_FIFO_L_IMUX7_1", + "CMT_TOP_IMUX7_1" + ], + [ + "CMT_FIFO_MONITOR_N_8", + "CMT_TOP_MONITOR_N_8" + ], + [ + "CMT_FIFO_L_IMUX47_1", + "CMT_TOP_IMUX47_1" + ], + [ + "CMT_FIFO_L_FAN2_9", + "CMT_TOP_FAN2_9" + ], + [ + "CMT_FIFO_SE2A2_4", + "CMT_TOP_SE2A2_4" + ], + [ + "CMT_FIFO_LH4_3", + "CMT_TOP_LH4_3" + ], + [ + "CMT_FIFO_EE4A0_5", + "CMT_TOP_EE4A0_5" + ], + [ + "CMT_FIFO_L_CLK1_4", + "CMT_TOP_CLK1_4" + ], + [ + "CMT_FIFO_LH5_3", + "CMT_TOP_LH5_3" + ], + [ + "CMT_FIFO_LH10_0", + "CMT_TOP_LH10_0" + ], + [ + "CMT_FIFO_L_IMUX21_6", + "CMT_TOP_IMUX21_6" + ], + [ + "CMT_FIFO_NW4A3_10", + "CMT_TOP_NW4A3_10" + ], + [ + "CMT_FIFO_L_IMUX18_4", + "CMT_TOP_IMUX18_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_6", + "CMT_TOP_LOGIC_OUTS_L_B23_6" + ], + [ + "CMT_FIFO_NW2A0_8", + "CMT_TOP_NW2A0_8" + ], + [ + "CMT_FIFO_EE4A1_0", + "CMT_TOP_EE4A1_0" + ], + [ + "CMT_FIFO_SE4C2_10", + "CMT_TOP_SE4C2_10" + ], + [ + "CMT_FIFO_WW4END0_5", + "CMT_TOP_WW4END0_5" + ], + [ + "CMT_FIFO_SW4END3_4", + "CMT_TOP_SW4END3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_10", + "CMT_TOP_LOGIC_OUTS_L_B13_10" + ], + [ + "CMT_FIFO_WW4A1_1", + "CMT_TOP_WW4A1_1" + ], + [ + "CMT_FIFO_WW4END1_6", + "CMT_TOP_WW4END1_6" + ], + [ + "CMT_FIFO_SW2A1_1", + "CMT_TOP_SW2A1_1" + ], + [ + "CMT_FIFO_NW4A3_3", + "CMT_TOP_NW4A3_3" + ], + [ + "CMT_FIFO_L_FAN7_7", + "CMT_TOP_FAN7_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "CMT_TOP_ICLKDIV_6" + ], + [ + "CMT_FIFO_L_IMUX32_10", + "CMT_TOP_IMUX32_10" + ], + [ + "CMT_FIFO_L_IMUX0_7", + "CMT_TOP_IMUX0_7" + ], + [ + "CMT_FIFO_L_BYP3_5", + "CMT_TOP_BYP3_5" + ], + [ + "CMT_FIFO_EE4C0_5", + "CMT_TOP_EE4C0_5" + ], + [ + "CMT_FIFO_WR1END0_6", + "CMT_TOP_WR1END0_6" + ], + [ + "CMT_FIFO_SE4BEG1_2", + "CMT_TOP_SE4BEG1_2" + ], + [ + "CMT_FIFO_NW2A1_3", + "CMT_TOP_NW2A1_3" + ], + [ + "CMT_FIFO_L_IMUX10_5", + "CMT_TOP_IMUX10_5" + ], + [ + "CMT_FIFO_L_IMUX45_4", + "CMT_TOP_IMUX45_4" + ], + [ + "CMT_FIFO_EE4C3_2", + "CMT_TOP_EE4C3_2" + ], + [ + "CMT_FIFO_SE4BEG3_4", + "CMT_TOP_SE4BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_2", + "CMT_TOP_LOGIC_OUTS_L_B23_2" + ], + [ + "CMT_FIFO_ER1BEG0_10", + "CMT_TOP_ER1BEG0_10" + ], + [ + "CMT_FIFO_NW4A3_5", + "CMT_TOP_NW4A3_5" + ], + [ + "CMT_FIFO_LH9_0", + "CMT_TOP_LH9_0" + ], + [ + "CMT_FIFO_SW4A3_5", + "CMT_TOP_SW4A3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_8", + "CMT_TOP_LOGIC_OUTS_L_B21_8" + ], + [ + "CMT_FIFO_WW4A3_6", + "CMT_TOP_WW4A3_6" + ], + [ + "CMT_FIFO_SE2A1_1", + "CMT_TOP_SE2A1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_1", + "CMT_TOP_LOGIC_OUTS_L_B19_1" + ], + [ + "CMT_FIFO_L_FAN5_9", + "CMT_TOP_FAN5_9" + ], + [ + "CMT_FIFO_NE4C3_7", + "CMT_TOP_NE4C3_7" + ], + [ + "CMT_FIFO_NW2A3_11", + "CMT_TOP_NW2A3_11" + ], + [ + "CMT_FIFO_WW4END2_3", + "CMT_TOP_WW4END2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_1", + "CMT_TOP_LOGIC_OUTS_L_B3_1" + ], + [ + "CMT_FIFO_LH1_2", + "CMT_TOP_LH1_2" + ], + [ + "CMT_FIFO_SW4END2_2", + "CMT_TOP_SW4END2_2" + ], + [ + "CMT_FIFO_L_IMUX23_10", + "CMT_TOP_IMUX23_10" + ], + [ + "CMT_FIFO_WR1END3_9", + "CMT_TOP_WR1END3_9" + ], + [ + "CMT_FIFO_L_IMUX42_5", + "CMT_TOP_IMUX42_5" + ], + [ + "CMT_FIFO_NE4C1_7", + "CMT_TOP_NE4C1_7" + ], + [ + "CMT_FIFO_LH7_11", + "CMT_TOP_LH7_11" + ], + [ + "CMT_FIFO_L_BYP5_11", + "CMT_TOP_BYP5_11" + ], + [ + "CMT_FIFO_MONITOR_P_8", + "CMT_TOP_MONITOR_P_8" + ], + [ + "CMT_FIFO_SE4C0_9", + "CMT_TOP_SE4C0_9" + ], + [ + "CMT_FIFO_L_IMUX46_8", + "CMT_TOP_IMUX46_8" + ], + [ + "CMT_FIFO_MONITOR_P_10", + "CMT_TOP_MONITOR_P_10" + ], + [ + "CMT_FIFO_L_IMUX10_10", + "CMT_TOP_IMUX10_10" + ], + [ + "CMT_FIFO_L_IMUX4_9", + "CMT_TOP_IMUX4_9" + ], + [ + "CMT_FIFO_SW2A2_3", + "CMT_TOP_SW2A2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_5", + "CMT_TOP_LOGIC_OUTS_L_B15_5" + ], + [ + "CMT_FIFO_EE4B2_8", + "CMT_TOP_EE4B2_8" + ], + [ + "CMT_FIFO_L_IMUX17_6", + "CMT_TOP_IMUX17_6" + ], + [ + "CMT_FIFO_EL1BEG3_1", + "CMT_TOP_EL1BEG3_1" + ], + [ + "CMT_FIFO_L_IMUX34_9", + "CMT_TOP_IMUX34_9" + ], + [ + "CMT_FIFO_EL1BEG2_6", + "CMT_TOP_EL1BEG2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_10", + "CMT_TOP_LOGIC_OUTS_L_B4_10" + ], + [ + "CMT_FIFO_L_IMUX44_7", + "CMT_TOP_IMUX44_7" + ], + [ + "CMT_FIFO_SW4A3_11", + "CMT_TOP_SW4A3_11" + ], + [ + "CMT_FIFO_NW4A2_0", + "CMT_TOP_NW4A2_0" + ], + [ + "CMT_FIFO_LH7_8", + "CMT_TOP_LH7_8" + ], + [ + "CMT_FIFO_EE2BEG2_6", + "CMT_TOP_EE2BEG2_6" + ], + [ + "CMT_FIFO_SE4BEG0_1", + "CMT_TOP_SE4BEG0_1" + ], + [ + "CMT_FIFO_WW4B1_4", + "CMT_TOP_WW4B1_4" + ], + [ + "CMT_FIFO_L_CTRL0_9", + "CMT_TOP_CTRL0_9" + ], + [ + "CMT_FIFO_SE4C1_3", + "CMT_TOP_SE4C1_3" + ], + [ + "CMT_FIFO_WW2END2_11", + "CMT_TOP_WW2END2_11" + ], + [ + "CMT_FIFO_WR1END3_7", + "CMT_TOP_WR1END3_7" + ], + [ + "CMT_FIFO_WW4B2_2", + "CMT_TOP_WW4B2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_6", + "CMT_TOP_LOGIC_OUTS_L_B18_6" + ], + [ + "CMT_FIFO_LH3_6", + "CMT_TOP_LH3_6" + ], + [ + "CMT_FIFO_LH7_4", + "CMT_TOP_LH7_4" + ], + [ + "CMT_FIFO_LH12_1", + "CMT_TOP_LH12_1" + ], + [ + "CMT_FIFO_WW2A2_4", + "CMT_TOP_WW2A2_4" + ], + [ + "CMT_FIFO_ER1BEG2_1", + "CMT_TOP_ER1BEG2_1" + ], + [ + "CMT_FIFO_WW4A3_1", + "CMT_TOP_WW4A3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_10", + "CMT_TOP_LOGIC_OUTS_L_B22_10" + ], + [ + "CMT_FIFO_SW4END1_10", + "CMT_TOP_SW4END1_10" + ], + [ + "CMT_FIFO_L_IMUX30_9", + "CMT_TOP_IMUX30_9" + ], + [ + "CMT_FIFO_EE4C1_1", + "CMT_TOP_EE4C1_1" + ], + [ + "CMT_FIFO_NW2A2_7", + "CMT_TOP_NW2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_4", + "CMT_TOP_LOGIC_OUTS_L_B1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_6", + "CMT_TOP_LOGIC_OUTS_L_B9_6" + ], + [ + "CMT_FIFO_NE2A3_6", + "CMT_TOP_NE2A3_6" + ], + [ + "CMT_FIFO_L_IMUX30_8", + "CMT_TOP_IMUX30_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "CMT_TOP_ICLKDIV_10" + ], + [ + "CMT_FIFO_NW4END3_8", + "CMT_TOP_NW4END3_8" + ], + [ + "CMT_FIFO_EE2BEG3_8", + "CMT_TOP_EE2BEG3_8" + ], + [ + "CMT_FIFO_NW2A0_3", + "CMT_TOP_NW2A0_3" + ], + [ + "CMT_FIFO_L_PHASER_WRCLK", + "CMT_PHASER_IN_C_WRCLK_TOFIFO" + ], + [ + "CMT_FIFO_WR1END0_10", + "CMT_TOP_WR1END0_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "CMT_TOP_ICLKDIV_11" + ], + [ + "CMT_FIFO_L_BYP2_0", + "CMT_TOP_BYP2_0" + ], + [ + "CMT_FIFO_L_IMUX2_5", + "CMT_TOP_IMUX2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_11", + "CMT_TOP_LOGIC_OUTS_L_B9_11" + ], + [ + "CMT_FIFO_NW2A2_5", + "CMT_TOP_NW2A2_5" + ], + [ + "CMT_FIFO_NW2A2_3", + "CMT_TOP_NW2A2_3" + ], + [ + "CMT_FIFO_NW4A0_9", + "CMT_TOP_NW4A0_9" + ], + [ + "CMT_FIFO_SW2A1_5", + "CMT_TOP_SW2A1_5" + ], + [ + "CMT_FIFO_SE2A3_10", + "CMT_TOP_SE2A3_10" + ], + [ + "CMT_FIFO_EE2BEG2_1", + "CMT_TOP_EE2BEG2_1" + ], + [ + "CMT_FIFO_L_CTRL1_1", + "CMT_TOP_CTRL1_1" + ], + [ + "CMT_FIFO_NE2A3_8", + "CMT_TOP_NE2A3_8" + ], + [ + "CMT_FIFO_L_IMUX30_4", + "CMT_TOP_IMUX30_4" + ], + [ + "CMT_FIFO_L_BYP3_4", + "CMT_TOP_BYP3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_5", + "CMT_TOP_LOGIC_OUTS_L_B17_5" + ], + [ + "CMT_FIFO_WW4B3_5", + "CMT_TOP_WW4B3_5" + ], + [ + "CMT_FIFO_EE4B1_7", + "CMT_TOP_EE4B1_7" + ], + [ + "CMT_FIFO_EE4C0_9", + "CMT_TOP_EE4C0_9" + ], + [ + "CMT_FIFO_EE2BEG0_0", + "CMT_TOP_EE2BEG0_0" + ], + [ + "CMT_FIFO_LH8_0", + "CMT_TOP_LH8_0" + ], + [ + "CMT_FIFO_WR1END1_9", + "CMT_TOP_WR1END1_9" + ], + [ + "CMT_FIFO_EE2BEG3_5", + "CMT_TOP_EE2BEG3_5" + ], + [ + "CMT_FIFO_SE2A1_4", + "CMT_TOP_SE2A1_4" + ], + [ + "CMT_FIFO_L_IMUX32_3", + "CMT_TOP_IMUX32_3" + ], + [ + "CMT_FIFO_L_BYP5_10", + "CMT_TOP_BYP5_10" + ], + [ + "CMT_FIFO_EE4B3_11", + "CMT_TOP_EE4B3_11" + ], + [ + "CMT_FIFO_NW2A3_1", + "CMT_TOP_NW2A3_1" + ], + [ + "CMT_FIFO_SE4C1_1", + "CMT_TOP_SE4C1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_9", + "CMT_TOP_LOGIC_OUTS_L_B6_9" + ], + [ + "CMT_FIFO_L_IMUX46_4", + "CMT_TOP_IMUX46_4" + ], + [ + "CMT_FIFO_EE4B2_2", + "CMT_TOP_EE4B2_2" + ], + [ + "CMT_FIFO_SW4END3_1", + "CMT_TOP_SW4END3_1" + ], + [ + "CMT_FIFO_WW2A1_7", + "CMT_TOP_WW2A1_7" + ], + [ + "CMT_FIFO_EL1BEG0_6", + "CMT_TOP_EL1BEG0_6" + ], + [ + "CMT_FIFO_EE2A2_2", + "CMT_TOP_EE2A2_2" + ], + [ + "CMT_FIFO_WR1END3_5", + "CMT_TOP_WR1END3_5" + ], + [ + "CMT_FIFO_L_BYP5_6", + "CMT_TOP_BYP5_6" + ], + [ + "CMT_FIFO_L_IMUX30_11", + "CMT_TOP_IMUX30_11" + ], + [ + "CMT_FIFO_L_IMUX4_4", + "CMT_TOP_IMUX4_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_6", + "CMT_TOP_LOGIC_OUTS_L_B3_6" + ], + [ + "CMT_FIFO_L_IMUX44_9", + "CMT_TOP_IMUX44_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_6", + "CMT_TOP_LOGIC_OUTS_L_B20_6" + ], + [ + "CMT_FIFO_EE4B1_0", + "CMT_TOP_EE4B1_0" + ], + [ + "CMT_FIFO_L_IMUX26_4", + "CMT_TOP_IMUX26_4" + ], + [ + "CMT_FIFO_L_IMUX39_0", + "CMT_TOP_IMUX39_0" + ], + [ + "CMT_FIFO_NW4A0_11", + "CMT_TOP_NW4A0_11" + ], + [ + "CMT_FIFO_WW4C0_10", + "CMT_TOP_WW4C0_10" + ], + [ + "CMT_FIFO_L_IMUX45_9", + "CMT_TOP_IMUX45_9" + ], + [ + "CMT_FIFO_NE4C1_0", + "CMT_TOP_NE4C1_0" + ], + [ + "CMT_FIFO_EE4A2_9", + "CMT_TOP_EE4A2_9" + ], + [ + "CMT_FIFO_L_FAN1_10", + "CMT_TOP_FAN1_10" + ], + [ + "CMT_FIFO_ER1BEG3_11", + "CMT_TOP_ER1BEG3_11" + ], + [ + "CMT_FIFO_NW4END3_10", + "CMT_TOP_NW4END3_10" + ], + [ + "CMT_FIFO_L_IMUX28_8", + "CMT_TOP_IMUX28_8" + ], + [ + "CMT_FIFO_L_IMUX38_5", + "CMT_TOP_IMUX38_5" + ], + [ + "CMT_FIFO_L_IMUX38_2", + "CMT_TOP_IMUX38_2" + ], + [ + "CMT_FIFO_ER1BEG0_4", + "CMT_TOP_ER1BEG0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_3", + "CMT_TOP_LOGIC_OUTS_L_B5_3" + ], + [ + "CMT_FIFO_L_BYP2_8", + "CMT_TOP_BYP2_8" + ], + [ + "CMT_FIFO_SW2A3_0", + "CMT_TOP_SW2A3_0" + ], + [ + "CMT_FIFO_WW4C1_11", + "CMT_TOP_WW4C1_11" + ], + [ + "CMT_FIFO_NE2A2_2", + "CMT_TOP_NE2A2_2" + ], + [ + "CMT_FIFO_L_IMUX25_6", + "CMT_TOP_IMUX25_6" + ], + [ + "CMT_FIFO_L_IMUX15_11", + "CMT_TOP_IMUX15_11" + ], + [ + "CMT_FIFO_L_IMUX10_8", + "CMT_TOP_IMUX10_8" + ], + [ + "CMT_FIFO_L_IMUX38_11", + "CMT_TOP_IMUX38_11" + ], + [ + "CMT_FIFO_EE4B0_10", + "CMT_TOP_EE4B0_10" + ], + [ + "CMT_FIFO_WW4END2_9", + "CMT_TOP_WW4END2_9" + ], + [ + "CMT_FIFO_L_IMUX31_6", + "CMT_TOP_IMUX31_6" + ], + [ + "CMT_FIFO_L_IMUX35_3", + "CMT_TOP_IMUX35_3" + ], + [ + "CMT_FIFO_SW2A2_0", + "CMT_TOP_SW2A2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_0", + "CMT_TOP_LOGIC_OUTS_L_B11_0" + ], + [ + "CMT_FIFO_NW4A0_5", + "CMT_TOP_NW4A0_5" + ], + [ + "CMT_FIFO_L_IMUX14_10", + "CMT_TOP_IMUX14_10" + ], + [ + "CMT_FIFO_NE4C3_6", + "CMT_TOP_NE4C3_6" + ], + [ + "CMT_FIFO_L_IMUX31_3", + "CMT_TOP_IMUX31_3" + ], + [ + "CMT_FIFO_WW4B0_10", + "CMT_TOP_WW4B0_10" + ], + [ + "CMT_FIFO_L_CLK1_8", + "CMT_TOP_CLK1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_8", + "CMT_TOP_LOGIC_OUTS_L_B17_8" + ], + [ + "CMT_FIFO_L_FAN6_7", + "CMT_TOP_FAN6_7" + ], + [ + "CMT_FIFO_LH6_1", + "CMT_TOP_LH6_1" + ], + [ + "CMT_FIFO_L_FAN3_0", + "CMT_TOP_FAN3_0" + ], + [ + "CMT_FIFO_WW4C3_10", + "CMT_TOP_WW4C3_10" + ], + [ + "CMT_FIFO_EE2A3_6", + "CMT_TOP_EE2A3_6" + ], + [ + "CMT_FIFO_EL1BEG0_0", + "CMT_TOP_EL1BEG0_0" + ], + [ + "CMT_FIFO_EE4BEG2_11", + "CMT_TOP_EE4BEG2_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "CMT_TOP_ICLK_11" + ], + [ + "CMT_FIFO_SE2A2_9", + "CMT_TOP_SE2A2_9" + ], + [ + "CMT_FIFO_L_IMUX43_8", + "CMT_TOP_IMUX43_8" + ], + [ + "CMT_FIFO_EE4C2_7", + "CMT_TOP_EE4C2_7" + ], + [ + "CMT_FIFO_EE2BEG3_6", + "CMT_TOP_EE2BEG3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_7", + "CMT_TOP_LOGIC_OUTS_L_B23_7" + ], + [ + "CMT_FIFO_NE4BEG0_1", + "CMT_TOP_NE4BEG0_1" + ], + [ + "CMT_FIFO_NW4A0_8", + "CMT_TOP_NW4A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_7", + "CMT_TOP_LOGIC_OUTS_L_B21_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_3", + "CMT_TOP_LOGIC_OUTS_L_B19_3" + ], + [ + "CMT_FIFO_L_FAN7_4", + "CMT_TOP_FAN7_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_8", + "CMT_TOP_LOGIC_OUTS_L_B23_8" + ], + [ + "CMT_FIFO_WW4A2_2", + "CMT_TOP_WW4A2_2" + ], + [ + "CMT_FIFO_SE4C2_11", + "CMT_TOP_SE4C2_11" + ], + [ + "CMT_FIFO_L_IMUX27_1", + "CMT_TOP_IMUX27_1" + ], + [ + "CMT_FIFO_ER1BEG1_4", + "CMT_TOP_ER1BEG1_4" + ], + [ + "CMT_FIFO_L_FAN2_10", + "CMT_TOP_FAN2_10" + ], + [ + "CMT_FIFO_WW2END2_8", + "CMT_TOP_WW2END2_8" + ], + [ + "CMT_FIFO_L_IMUX23_11", + "CMT_TOP_IMUX23_11" + ], + [ + "CMT_FIFO_EE4C3_4", + "CMT_TOP_EE4C3_4" + ], + [ + "CMT_FIFO_L_IMUX41_0", + "CMT_TOP_IMUX41_0" + ], + [ + "CMT_FIFO_ER1BEG1_11", + "CMT_TOP_ER1BEG1_11" + ], + [ + "CMT_FIFO_SE4C3_7", + "CMT_TOP_SE4C3_7" + ], + [ + "CMT_FIFO_L_IMUX7_10", + "CMT_TOP_IMUX7_10" + ], + [ + "CMT_FIFO_L_FAN4_3", + "CMT_TOP_FAN4_3" + ], + [ + "CMT_FIFO_L_IMUX35_5", + "CMT_TOP_IMUX35_5" + ], + [ + "CMT_FIFO_WW4A0_5", + "CMT_TOP_WW4A0_5" + ], + [ + "CMT_FIFO_L_IMUX47_0", + "CMT_TOP_IMUX47_0" + ], + [ + "CMT_FIFO_WW4B3_2", + "CMT_TOP_WW4B3_2" + ], + [ + "CMT_FIFO_L_IMUX6_7", + "CMT_TOP_IMUX6_7" + ], + [ + "CMT_FIFO_L_IMUX28_0", + "CMT_TOP_IMUX28_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_5", + "CMT_TOP_LOGIC_OUTS_L_B23_5" + ], + [ + "CMT_FIFO_LH2_2", + "CMT_TOP_LH2_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "CMT_TOP_OCLKDIV_11" + ], + [ + "CMT_FIFO_WW4B1_11", + "CMT_TOP_WW4B1_11" + ], + [ + "CMT_FIFO_MONITOR_N_0", + "CMT_TOP_MONITOR_N_0" + ], + [ + "CMT_FIFO_WW4A2_5", + "CMT_TOP_WW4A2_5" + ], + [ + "CMT_FIFO_SE4BEG2_9", + "CMT_TOP_SE4BEG2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_0", + "CMT_TOP_LOGIC_OUTS_L_B5_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_5", + "CMT_TOP_LOGIC_OUTS_L_B20_5" + ], + [ + "CMT_FIFO_SE4C1_11", + "CMT_TOP_SE4C1_11" + ], + [ + "CMT_FIFO_EE4C2_1", + "CMT_TOP_EE4C2_1" + ], + [ + "CMT_FIFO_EE4B3_8", + "CMT_TOP_EE4B3_8" + ], + [ + "CMT_FIFO_L_IMUX37_8", + "CMT_TOP_IMUX37_8" + ], + [ + "CMT_FIFO_LH3_7", + "CMT_TOP_LH3_7" + ], + [ + "CMT_FIFO_L_IMUX22_6", + "CMT_TOP_IMUX22_6" + ], + [ + "CMT_FIFO_SE2A0_5", + "CMT_TOP_SE2A0_5" + ], + [ + "CMT_FIFO_L_BYP4_2", + "CMT_TOP_BYP4_2" + ], + [ + "CMT_FIFO_MONITOR_P_6", + "CMT_TOP_MONITOR_P_6" + ], + [ + "CMT_FIFO_WW4END2_11", + "CMT_TOP_WW4END2_11" + ], + [ + "CMT_FIFO_SE4BEG3_8", + "CMT_TOP_SE4BEG3_8" + ], + [ + "CMT_FIFO_L_PHASER_RDCLK", + "CMT_PHASER_OUT_C_RDCLK_TOFIFO" + ], + [ + "CMT_FIFO_NW2A3_10", + "CMT_TOP_NW2A3_10" + ], + [ + "CMT_FIFO_L_IMUX32_5", + "CMT_TOP_IMUX32_5" + ], + [ + "CMT_FIFO_L_IMUX17_7", + "CMT_TOP_IMUX17_7" + ], + [ + "CMT_FIFO_SE2A3_2", + "CMT_TOP_SE2A3_2" + ], + [ + "CMT_FIFO_WW4END3_11", + "CMT_TOP_WW4END3_11" + ], + [ + "CMT_FIFO_L_IMUX42_7", + "CMT_TOP_IMUX42_7" + ], + [ + "CMT_FIFO_L_IMUX32_7", + "CMT_TOP_IMUX32_7" + ], + [ + "CMT_FIFO_L_IMUX0_2", + "CMT_TOP_IMUX0_2" + ], + [ + "CMT_FIFO_L_IMUX46_7", + "CMT_TOP_IMUX46_7" + ], + [ + "CMT_FIFO_L_IMUX31_7", + "CMT_TOP_IMUX31_7" + ], + [ + "CMT_FIFO_WL1END3_1", + "CMT_TOP_WL1END3_1" + ], + [ + "CMT_FIFO_WW4B1_2", + "CMT_TOP_WW4B1_2" + ], + [ + "CMT_FIFO_LH5_5", + "CMT_TOP_LH5_5" + ], + [ + "CMT_FIFO_LH10_1", + "CMT_TOP_LH10_1" + ], + [ + "CMT_FIFO_NE2A1_7", + "CMT_TOP_NE2A1_7" + ], + [ + "CMT_FIFO_L_IMUX0_10", + "CMT_TOP_IMUX0_10" + ], + [ + "CMT_FIFO_L_BYP2_10", + "CMT_TOP_BYP2_10" + ], + [ + "CMT_FIFO_L_CTRL1_6", + "CMT_TOP_CTRL1_6" + ], + [ + "CMT_FIFO_WR1END0_9", + "CMT_TOP_WR1END0_9" + ], + [ + "CMT_FIFO_L_BYP1_7", + "CMT_TOP_BYP1_7" + ], + [ + "CMT_FIFO_L_FAN1_9", + "CMT_TOP_FAN1_9" + ], + [ + "CMT_FIFO_WW4C2_5", + "CMT_TOP_WW4C2_5" + ], + [ + "CMT_FIFO_WL1END2_11", + "CMT_TOP_WL1END2_11" + ], + [ + "CMT_FIFO_NW4A3_11", + "CMT_TOP_NW4A3_11" + ], + [ + "CMT_FIFO_L_BYP6_5", + "CMT_TOP_BYP6_5" + ], + [ + "CMT_FIFO_EE4BEG3_1", + "CMT_TOP_EE4BEG3_1" + ], + [ + "CMT_FIFO_L_IMUX17_8", + "CMT_TOP_IMUX17_8" + ], + [ + "CMT_FIFO_WW2END3_0", + "CMT_TOP_WW2END3_0" + ], + [ + "CMT_FIFO_L_IMUX42_4", + "CMT_TOP_IMUX42_4" + ], + [ + "CMT_FIFO_NE4BEG3_3", + "CMT_TOP_NE4BEG3_3" + ], + [ + "CMT_FIFO_SE4C2_0", + "CMT_TOP_SE4C2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_6", + "CMT_TOP_LOGIC_OUTS_L_B5_6" + ], + [ + "CMT_FIFO_WW4C2_9", + "CMT_TOP_WW4C2_9" + ], + [ + "CMT_FIFO_WW2END2_4", + "CMT_TOP_WW2END2_4" + ], + [ + "CMT_FIFO_SW2A0_2", + "CMT_TOP_SW2A0_2" + ], + [ + "CMT_FIFO_EE4BEG2_6", + "CMT_TOP_EE4BEG2_6" + ], + [ + "CMT_FIFO_EE2BEG0_3", + "CMT_TOP_EE2BEG0_3" + ], + [ + "CMT_FIFO_L_IMUX47_4", + "CMT_TOP_IMUX47_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_6", + "CMT_TOP_LOGIC_OUTS_L_B11_6" + ], + [ + "CMT_FIFO_L_FAN6_5", + "CMT_TOP_FAN6_5" + ], + [ + "CMT_FIFO_EE2BEG3_3", + "CMT_TOP_EE2BEG3_3" + ], + [ + "CMT_FIFO_L_IMUX31_0", + "CMT_TOP_IMUX31_0" + ], + [ + "CMT_FIFO_WR1END1_3", + "CMT_TOP_WR1END1_3" + ], + [ + "CMT_FIFO_NW2A1_8", + "CMT_TOP_NW2A1_8" + ], + [ + "CMT_FIFO_L_IMUX42_3", + "CMT_TOP_IMUX42_3" + ], + [ + "CMT_FIFO_NW2A2_0", + "CMT_TOP_NW2A2_0" + ], + [ + "CMT_FIFO_L_BYP1_0", + "CMT_TOP_BYP1_0" + ], + [ + "CMT_FIFO_EE2BEG3_11", + "CMT_TOP_EE2BEG3_11" + ], + [ + "CMT_FIFO_L_FAN5_1", + "CMT_TOP_FAN5_1" + ], + [ + "CMT_FIFO_SW2A1_6", + "CMT_TOP_SW2A1_6" + ], + [ + "CMT_FIFO_NW2A3_7", + "CMT_TOP_NW2A3_7" + ], + [ + "CMT_FIFO_EE4C1_9", + "CMT_TOP_EE4C1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_11", + "CMT_TOP_LOGIC_OUTS_L_B22_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_2", + "CMT_TOP_LOGIC_OUTS_L_B5_2" + ], + [ + "CMT_FIFO_WW4B2_8", + "CMT_TOP_WW4B2_8" + ], + [ + "CMT_FIFO_EE4A0_1", + "CMT_TOP_EE4A0_1" + ], + [ + "CMT_FIFO_WW4END2_1", + "CMT_TOP_WW4END2_1" + ], + [ + "CMT_FIFO_WL1END2_10", + "CMT_TOP_WL1END2_10" + ], + [ + "CMT_FIFO_L_IMUX12_7", + "CMT_TOP_IMUX12_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_0", + "CMT_TOP_LOGIC_OUTS_L_B13_0" + ], + [ + "CMT_FIFO_SW4A2_3", + "CMT_TOP_SW4A2_3" + ], + [ + "CMT_FIFO_WL1END3_0", + "CMT_TOP_WL1END3_0" + ], + [ + "CMT_FIFO_SW4END2_6", + "CMT_TOP_SW4END2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_0", + "CMT_TOP_LOGIC_OUTS_L_B8_0" + ], + [ + "CMT_FIFO_SW4A0_1", + "CMT_TOP_SW4A0_1" + ], + [ + "CMT_FIFO_WW4END3_7", + "CMT_TOP_WW4END3_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "CMT_TOP_OCLKDIV_1" + ], + [ + "CMT_FIFO_EE4BEG0_9", + "CMT_TOP_EE4BEG0_9" + ], + [ + "CMT_FIFO_SE4BEG3_2", + "CMT_TOP_SE4BEG3_2" + ], + [ + "CMT_FIFO_NW4A0_10", + "CMT_TOP_NW4A0_10" + ], + [ + "CMT_FIFO_ER1BEG3_8", + "CMT_TOP_ER1BEG3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_5", + "CMT_TOP_LOGIC_OUTS_L_B10_5" + ], + [ + "CMT_FIFO_SW2A2_10", + "CMT_TOP_SW2A2_10" + ], + [ + "CMT_FIFO_L_BYP2_3", + "CMT_TOP_BYP2_3" + ], + [ + "CMT_FIFO_WW4C0_7", + "CMT_TOP_WW4C0_7" + ], + [ + "CMT_FIFO_L_IMUX9_8", + "CMT_TOP_IMUX9_8" + ], + [ + "CMT_FIFO_NW4END2_5", + "CMT_TOP_NW4END2_5" + ], + [ + "CMT_FIFO_L_IMUX30_2", + "CMT_TOP_IMUX30_2" + ], + [ + "CMT_FIFO_L_BYP7_8", + "CMT_TOP_BYP7_8" + ], + [ + "CMT_FIFO_WL1END3_10", + "CMT_TOP_WL1END3_10" + ], + [ + "CMT_FIFO_L_IMUX11_10", + "CMT_TOP_IMUX11_10" + ], + [ + "CMT_FIFO_L_FAN5_11", + "CMT_TOP_FAN5_11" + ], + [ + "CMT_FIFO_NE4BEG3_0", + "CMT_TOP_NE4BEG3_0" + ], + [ + "CMT_FIFO_EE2A2_7", + "CMT_TOP_EE2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_5", + "CMT_TOP_LOGIC_OUTS_L_B8_5" + ], + [ + "CMT_FIFO_WW4A2_10", + "CMT_TOP_WW4A2_10" + ], + [ + "CMT_FIFO_EE4C2_10", + "CMT_TOP_EE4C2_10" + ], + [ + "CMT_FIFO_L_IMUX8_10", + "CMT_TOP_IMUX8_10" + ], + [ + "CMT_FIFO_SW4A1_8", + "CMT_TOP_SW4A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_9", + "CMT_TOP_LOGIC_OUTS_L_B15_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_3", + "CMT_TOP_LOGIC_OUTS_L_B10_3" + ], + [ + "CMT_FIFO_EL1BEG1_3", + "CMT_TOP_EL1BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX7_0", + "CMT_TOP_IMUX7_0" + ], + [ + "CMT_FIFO_L_IMUX29_0", + "CMT_TOP_IMUX29_0" + ], + [ + "CMT_FIFO_WW4B0_8", + "CMT_TOP_WW4B0_8" + ], + [ + "CMT_FIFO_NE4BEG2_6", + "CMT_TOP_NE4BEG2_6" + ], + [ + "CMT_FIFO_L_FAN1_0", + "CMT_TOP_FAN1_0" + ], + [ + "CMT_FIFO_WW2END0_11", + "CMT_TOP_WW2END0_11" + ], + [ + "CMT_FIFO_L_FAN3_1", + "CMT_TOP_FAN3_1" + ], + [ + "CMT_FIFO_LH12_7", + "CMT_TOP_LH12_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_3", + "CMT_TOP_LOGIC_OUTS_L_B18_3" + ], + [ + "CMT_FIFO_ER1BEG0_9", + "CMT_TOP_ER1BEG0_9" + ], + [ + "CMT_FIFO_SW4END1_5", + "CMT_TOP_SW4END1_5" + ], + [ + "CMT_FIFO_EE2BEG1_5", + "CMT_TOP_EE2BEG1_5" + ], + [ + "CMT_FIFO_EE2BEG2_5", + "CMT_TOP_EE2BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX14_5", + "CMT_TOP_IMUX14_5" + ], + [ + "CMT_FIFO_WW4A0_7", + "CMT_TOP_WW4A0_7" + ], + [ + "CMT_FIFO_L_IMUX23_6", + "CMT_TOP_IMUX23_6" + ], + [ + "CMT_FIFO_SW4END3_7", + "CMT_TOP_SW4END3_7" + ], + [ + "CMT_FIFO_L_IMUX46_3", + "CMT_TOP_IMUX46_3" + ], + [ + "CMT_FIFO_WR1END0_1", + "CMT_TOP_WR1END0_1" + ], + [ + "CMT_FIFO_SE4BEG2_2", + "CMT_TOP_SE4BEG2_2" + ], + [ + "CMT_FIFO_WW4END3_6", + "CMT_TOP_WW4END3_6" + ], + [ + "CMT_FIFO_SW4END2_4", + "CMT_TOP_SW4END2_4" + ], + [ + "CMT_FIFO_WW2A2_11", + "CMT_TOP_WW2A2_11" + ], + [ + "CMT_FIFO_WW2A2_0", + "CMT_TOP_WW2A2_0" + ], + [ + "CMT_FIFO_SE4C2_6", + "CMT_TOP_SE4C2_6" + ], + [ + "CMT_FIFO_SW2A3_1", + "CMT_TOP_SW2A3_1" + ], + [ + "CMT_FIFO_EE4C3_7", + "CMT_TOP_EE4C3_7" + ], + [ + "CMT_FIFO_EE4A2_8", + "CMT_TOP_EE4A2_8" + ], + [ + "CMT_FIFO_NE4BEG2_0", + "CMT_TOP_NE4BEG2_0" + ], + [ + "CMT_FIFO_NE4C1_6", + "CMT_TOP_NE4C1_6" + ], + [ + "CMT_FIFO_NE4C0_4", + "CMT_TOP_NE4C0_4" + ], + [ + "CMT_FIFO_L_IMUX13_6", + "CMT_TOP_IMUX13_6" + ], + [ + "CMT_FIFO_LH2_4", + "CMT_TOP_LH2_4" + ], + [ + "CMT_FIFO_LH1_10", + "CMT_TOP_LH1_10" + ], + [ + "CMT_FIFO_WW2END0_10", + "CMT_TOP_WW2END0_10" + ], + [ + "CMT_FIFO_L_IMUX7_9", + "CMT_TOP_IMUX7_9" + ], + [ + "CMT_FIFO_L_IMUX20_7", + "CMT_TOP_IMUX20_7" + ], + [ + "CMT_FIFO_NW2A3_6", + "CMT_TOP_NW2A3_6" + ], + [ + "CMT_FIFO_ER1BEG1_8", + "CMT_TOP_ER1BEG1_8" + ], + [ + "CMT_FIFO_SE2A0_6", + "CMT_TOP_SE2A0_6" + ], + [ + "CMT_FIFO_NW4A1_7", + "CMT_TOP_NW4A1_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "CMT_TOP_ICLK_2" + ], + [ + "CMT_FIFO_L_IMUX10_7", + "CMT_TOP_IMUX10_7" + ], + [ + "CMT_FIFO_EE4B0_3", + "CMT_TOP_EE4B0_3" + ], + [ + "CMT_FIFO_NE4C2_2", + "CMT_TOP_NE4C2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_8", + "CMT_TOP_LOGIC_OUTS_L_B19_8" + ], + [ + "CMT_FIFO_L_IMUX47_2", + "CMT_TOP_IMUX47_2" + ], + [ + "CMT_FIFO_EE4B0_9", + "CMT_TOP_EE4B0_9" + ], + [ + "CMT_FIFO_NW4A3_0", + "CMT_TOP_NW4A3_0" + ], + [ + "CMT_FIFO_NW4A0_7", + "CMT_TOP_NW4A0_7" + ], + [ + "CMT_FIFO_NE4C0_2", + "CMT_TOP_NE4C0_2" + ], + [ + "CMT_FIFO_WW2A2_5", + "CMT_TOP_WW2A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_5", + "CMT_TOP_LOGIC_OUTS_L_B2_5" + ], + [ + "CMT_FIFO_WW4B2_1", + "CMT_TOP_WW4B2_1" + ], + [ + "CMT_FIFO_WW2END1_8", + "CMT_TOP_WW2END1_8" + ], + [ + "CMT_FIFO_L_IMUX38_0", + "CMT_TOP_IMUX38_0" + ], + [ + "CMT_FIFO_L_IMUX14_11", + "CMT_TOP_IMUX14_11" + ], + [ + "CMT_FIFO_SE4BEG2_1", + "CMT_TOP_SE4BEG2_1" + ], + [ + "CMT_FIFO_L_IMUX36_6", + "CMT_TOP_IMUX36_6" + ], + [ + "CMT_FIFO_L_IMUX37_11", + "CMT_TOP_IMUX37_11" + ], + [ + "CMT_FIFO_EE4BEG3_11", + "CMT_TOP_EE4BEG3_11" + ], + [ + "CMT_FIFO_WW4A0_4", + "CMT_TOP_WW4A0_4" + ], + [ + "CMT_FIFO_EE4BEG1_5", + "CMT_TOP_EE4BEG1_5" + ], + [ + "CMT_FIFO_EE4BEG2_10", + "CMT_TOP_EE4BEG2_10" + ], + [ + "CMT_FIFO_NE2A0_3", + "CMT_TOP_NE2A0_3" + ], + [ + "CMT_FIFO_NE2A0_1", + "CMT_TOP_NE2A0_1" + ], + [ + "CMT_FIFO_EE4A1_6", + "CMT_TOP_EE4A1_6" + ], + [ + "CMT_FIFO_L_FAN7_10", + "CMT_TOP_FAN7_10" + ], + [ + "CMT_FIFO_L_IMUX37_0", + "CMT_TOP_IMUX37_0" + ], + [ + "CMT_FIFO_SW4A3_7", + "CMT_TOP_SW4A3_7" + ], + [ + "CMT_FIFO_LH11_8", + "CMT_TOP_LH11_8" + ], + [ + "CMT_FIFO_L_BYP5_4", + "CMT_TOP_BYP5_4" + ], + [ + "CMT_FIFO_WL1END0_4", + "CMT_TOP_WL1END0_4" + ], + [ + "CMT_FIFO_L_PHASER_RDENABLE", + "CMT_PHASER_OUT_C_RDENABLE_TOFIFO" + ], + [ + "CMT_FIFO_L_IMUX40_8", + "CMT_TOP_IMUX40_8" + ], + [ + "CMT_FIFO_LH8_4", + "CMT_TOP_LH8_4" + ], + [ + "CMT_FIFO_EL1BEG2_4", + "CMT_TOP_EL1BEG2_4" + ], + [ + "CMT_FIFO_NE4C0_11", + "CMT_TOP_NE4C0_11" + ], + [ + "CMT_FIFO_EE2A3_7", + "CMT_TOP_EE2A3_7" + ], + [ + "CMT_FIFO_WW2A0_2", + "CMT_TOP_WW2A0_2" + ], + [ + "CMT_FIFO_WW2A3_0", + "CMT_TOP_WW2A3_0" + ], + [ + "CMT_FIFO_WW4A3_7", + "CMT_TOP_WW4A3_7" + ], + [ + "CMT_FIFO_SE2A0_1", + "CMT_TOP_SE2A0_1" + ], + [ + "CMT_FIFO_WW4C1_8", + "CMT_TOP_WW4C1_8" + ], + [ + "CMT_FIFO_NW4END3_1", + "CMT_TOP_NW4END3_1" + ], + [ + "CMT_FIFO_L_IMUX11_7", + "CMT_TOP_IMUX11_7" + ], + [ + "CMT_FIFO_NE4C1_5", + "CMT_TOP_NE4C1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_7", + "CMT_TOP_LOGIC_OUTS_L_B8_7" + ], + [ + "CMT_FIFO_L_IMUX41_6", + "CMT_TOP_IMUX41_6" + ], + [ + "CMT_FIFO_SE4BEG3_5", + "CMT_TOP_SE4BEG3_5" + ], + [ + "CMT_FIFO_L_IMUX6_2", + "CMT_TOP_IMUX6_2" + ], + [ + "CMT_FIFO_L_IMUX12_8", + "CMT_TOP_IMUX12_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_4", + "CMT_TOP_LOGIC_OUTS_L_B22_4" + ], + [ + "CMT_FIFO_SW4A1_11", + "CMT_TOP_SW4A1_11" + ], + [ + "CMT_FIFO_L_FAN5_7", + "CMT_TOP_FAN5_7" + ], + [ + "CMT_FIFO_L_CLK0_0", + "CMT_TOP_CLK0_0" + ], + [ + "CMT_FIFO_L_IMUX20_9", + "CMT_TOP_IMUX20_9" + ], + [ + "CMT_FIFO_L_BYP6_11", + "CMT_TOP_BYP6_11" + ], + [ + "CMT_FIFO_SW4A0_4", + "CMT_TOP_SW4A0_4" + ], + [ + "CMT_FIFO_EE2BEG0_8", + "CMT_TOP_EE2BEG0_8" + ], + [ + "CMT_FIFO_NE4BEG0_8", + "CMT_TOP_NE4BEG0_8" + ], + [ + "CMT_FIFO_LH4_4", + "CMT_TOP_LH4_4" + ], + [ + "CMT_FIFO_L_IMUX34_2", + "CMT_TOP_IMUX34_2" + ], + [ + "CMT_FIFO_L_IMUX0_1", + "CMT_TOP_IMUX0_1" + ], + [ + "CMT_FIFO_NW2A2_8", + "CMT_TOP_NW2A2_8" + ], + [ + "CMT_FIFO_L_IMUX10_2", + "CMT_TOP_IMUX10_2" + ], + [ + "CMT_FIFO_L_FAN0_1", + "CMT_TOP_FAN0_1" + ], + [ + "CMT_FIFO_LH12_4", + "CMT_TOP_LH12_4" + ], + [ + "CMT_FIFO_EL1BEG3_4", + "CMT_TOP_EL1BEG3_4" + ], + [ + "CMT_FIFO_WW4END0_11", + "CMT_TOP_WW4END0_11" + ], + [ + "CMT_FIFO_EE2A3_0", + "CMT_TOP_EE2A3_0" + ], + [ + "CMT_FIFO_L_IMUX12_9", + "CMT_TOP_IMUX12_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_4", + "CMT_TOP_LOGIC_OUTS_L_B18_4" + ], + [ + "CMT_FIFO_EE4C3_0", + "CMT_TOP_EE4C3_0" + ], + [ + "CMT_FIFO_NW4END1_0", + "CMT_TOP_NW4END1_0" + ], + [ + "CMT_FIFO_SE4C0_3", + "CMT_TOP_SE4C0_3" + ], + [ + "CMT_FIFO_L_IMUX2_6", + "CMT_TOP_IMUX2_6" + ], + [ + "CMT_FIFO_WW4END0_6", + "CMT_TOP_WW4END0_6" + ], + [ + "CMT_FIFO_L_FAN6_10", + "CMT_TOP_FAN6_10" + ], + [ + "CMT_FIFO_L_IMUX9_4", + "CMT_TOP_IMUX9_4" + ], + [ + "CMT_FIFO_EE4BEG1_1", + "CMT_TOP_EE4BEG1_1" + ], + [ + "CMT_FIFO_L_IMUX32_9", + "CMT_TOP_IMUX32_9" + ], + [ + "CMT_FIFO_EE2A1_4", + "CMT_TOP_EE2A1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_8", + "CMT_TOP_LOGIC_OUTS_L_B11_8" + ], + [ + "CMT_FIFO_L_IMUX43_4", + "CMT_TOP_IMUX43_4" + ], + [ + "CMT_FIFO_NW4A0_3", + "CMT_TOP_NW4A0_3" + ], + [ + "CMT_FIFO_WW4END3_2", + "CMT_TOP_WW4END3_2" + ], + [ + "CMT_FIFO_NW4END1_2", + "CMT_TOP_NW4END1_2" + ], + [ + "CMT_FIFO_EL1BEG3_9", + "CMT_TOP_EL1BEG3_9" + ], + [ + "CMT_FIFO_L_FAN3_9", + "CMT_TOP_FAN3_9" + ], + [ + "CMT_FIFO_EE4B2_3", + "CMT_TOP_EE4B2_3" + ], + [ + "CMT_FIFO_WW4A1_2", + "CMT_TOP_WW4A1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_11", + "CMT_TOP_LOGIC_OUTS_L_B13_11" + ], + [ + "CMT_FIFO_LH5_10", + "CMT_TOP_LH5_10" + ], + [ + "CMT_FIFO_EE4BEG0_11", + "CMT_TOP_EE4BEG0_11" + ], + [ + "CMT_FIFO_EE4A0_6", + "CMT_TOP_EE4A0_6" + ], + [ + "CMT_FIFO_LH10_5", + "CMT_TOP_LH10_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_6", + "CMT_TOP_LOGIC_OUTS_L_B13_6" + ], + [ + "CMT_FIFO_EE4BEG3_8", + "CMT_TOP_EE4BEG3_8" + ], + [ + "CMT_FIFO_L_IMUX17_4", + "CMT_TOP_IMUX17_4" + ], + [ + "CMT_FIFO_L_IMUX6_4", + "CMT_TOP_IMUX6_4" + ], + [ + "CMT_FIFO_LH11_0", + "CMT_TOP_LH11_0" + ], + [ + "CMT_FIFO_L_IMUX30_0", + "CMT_TOP_IMUX30_0" + ], + [ + "CMT_FIFO_L_FAN6_9", + "CMT_TOP_FAN6_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "CMT_TOP_ICLK_5" + ], + [ + "CMT_FIFO_L_IMUX36_1", + "CMT_TOP_IMUX36_1" + ], + [ + "CMT_FIFO_L_IMUX3_0", + "CMT_TOP_IMUX3_0" + ], + [ + "CMT_FIFO_L_IMUX41_7", + "CMT_TOP_IMUX41_7" + ], + [ + "CMT_FIFO_L_IMUX6_3", + "CMT_TOP_IMUX6_3" + ], + [ + "CMT_FIFO_NE2A3_1", + "CMT_TOP_NE2A3_1" + ], + [ + "CMT_FIFO_ER1BEG3_4", + "CMT_TOP_ER1BEG3_4" + ], + [ + "CMT_FIFO_L_IMUX8_1", + "CMT_TOP_IMUX8_1" + ], + [ + "CMT_FIFO_SE2A0_3", + "CMT_TOP_SE2A0_3" + ], + [ + "CMT_FIFO_EE4B3_2", + "CMT_TOP_EE4B3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_8", + "CMT_TOP_LOGIC_OUTS_L_B5_8" + ], + [ + "CMT_FIFO_NW4END0_1", + "CMT_TOP_NW4END0_1" + ], + [ + "CMT_FIFO_EL1BEG1_10", + "CMT_TOP_EL1BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX5_5", + "CMT_TOP_IMUX5_5" + ], + [ + "CMT_FIFO_L_FAN2_0", + "CMT_TOP_FAN2_0" + ], + [ + "CMT_FIFO_EE4B0_5", + "CMT_TOP_EE4B0_5" + ], + [ + "CMT_FIFO_NW4A2_4", + "CMT_TOP_NW4A2_4" + ], + [ + "CMT_FIFO_NW4END2_0", + "CMT_TOP_NW4END2_0" + ], + [ + "CMT_FIFO_WW4END3_8", + "CMT_TOP_WW4END3_8" + ], + [ + "CMT_FIFO_LH9_4", + "CMT_TOP_LH9_4" + ], + [ + "CMT_FIFO_NE4BEG1_7", + "CMT_TOP_NE4BEG1_7" + ], + [ + "CMT_FIFO_SW4A1_9", + "CMT_TOP_SW4A1_9" + ], + [ + "CMT_FIFO_SE4BEG1_4", + "CMT_TOP_SE4BEG1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_2", + "CMT_TOP_LOGIC_OUTS_L_B7_2" + ], + [ + "CMT_FIFO_L_CTRL1_9", + "CMT_TOP_CTRL1_9" + ], + [ + "CMT_FIFO_L_IMUX13_2", + "CMT_TOP_IMUX13_2" + ], + [ + "CMT_FIFO_WW4A1_11", + "CMT_TOP_WW4A1_11" + ], + [ + "CMT_FIFO_L_IMUX25_1", + "CMT_TOP_IMUX25_1" + ], + [ + "CMT_FIFO_L_FAN4_9", + "CMT_TOP_FAN4_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_0", + "CMT_TOP_LOGIC_OUTS_L_B15_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "CMT_TOP_ICLK_4" + ], + [ + "CMT_FIFO_SW2A1_11", + "CMT_TOP_SW2A1_11" + ], + [ + "CMT_FIFO_EE4BEG3_7", + "CMT_TOP_EE4BEG3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_2", + "CMT_TOP_LOGIC_OUTS_L_B6_2" + ], + [ + "CMT_FIFO_SE4BEG1_9", + "CMT_TOP_SE4BEG1_9" + ], + [ + "CMT_FIFO_WW4C0_3", + "CMT_TOP_WW4C0_3" + ], + [ + "CMT_FIFO_SW2A1_3", + "CMT_TOP_SW2A1_3" + ], + [ + "CMT_FIFO_SE4C0_5", + "CMT_TOP_SE4C0_5" + ], + [ + "CMT_FIFO_EE2A0_5", + "CMT_TOP_EE2A0_5" + ], + [ + "CMT_FIFO_SE4C1_4", + "CMT_TOP_SE4C1_4" + ], + [ + "CMT_FIFO_EL1BEG0_8", + "CMT_TOP_EL1BEG0_8" + ], + [ + "CMT_FIFO_WW4A1_8", + "CMT_TOP_WW4A1_8" + ], + [ + "CMT_FIFO_NW2A1_7", + "CMT_TOP_NW2A1_7" + ], + [ + "CMT_FIFO_NE2A1_2", + "CMT_TOP_NE2A1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_8", + "CMT_TOP_LOGIC_OUTS_L_B8_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_0", + "CMT_TOP_LOGIC_OUTS_L_B12_0" + ], + [ + "CMT_FIFO_SW4A3_2", + "CMT_TOP_SW4A3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_9", + "CMT_TOP_LOGIC_OUTS_L_B5_9" + ], + [ + "CMT_FIFO_L_CTRL1_3", + "CMT_TOP_CTRL1_3" + ], + [ + "CMT_FIFO_L_IMUX20_11", + "CMT_TOP_IMUX20_11" + ], + [ + "CMT_FIFO_ER1BEG3_0", + "CMT_TOP_ER1BEG3_0" + ], + [ + "CMT_FIFO_NW4A2_8", + "CMT_TOP_NW4A2_8" + ], + [ + "CMT_FIFO_NE4BEG0_2", + "CMT_TOP_NE4BEG0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_7", + "CMT_TOP_LOGIC_OUTS_L_B22_7" + ], + [ + "CMT_FIFO_SW4END0_10", + "CMT_TOP_SW4END0_10" + ], + [ + "CMT_FIFO_EE2A1_7", + "CMT_TOP_EE2A1_7" + ], + [ + "CMT_FIFO_NE4BEG0_6", + "CMT_TOP_NE4BEG0_6" + ], + [ + "CMT_FIFO_LH9_5", + "CMT_TOP_LH9_5" + ], + [ + "CMT_FIFO_EE2BEG2_3", + "CMT_TOP_EE2BEG2_3" + ], + [ + "CMT_FIFO_L_IMUX40_6", + "CMT_TOP_IMUX40_6" + ], + [ + "CMT_FIFO_WW4END1_4", + "CMT_TOP_WW4END1_4" + ], + [ + "CMT_FIFO_NE2A2_9", + "CMT_TOP_NE2A2_9" + ], + [ + "CMT_FIFO_SW2A1_2", + "CMT_TOP_SW2A1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "CMT_TOP_OCLK_8" + ], + [ + "CMT_FIFO_EE2A0_7", + "CMT_TOP_EE2A0_7" + ], + [ + "CMT_FIFO_WW4B0_7", + "CMT_TOP_WW4B0_7" + ], + [ + "CMT_FIFO_L_CTRL1_4", + "CMT_TOP_CTRL1_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "CMT_TOP_OCLKDIV_9" + ], + [ + "CMT_FIFO_L_IMUX37_7", + "CMT_TOP_IMUX37_7" + ], + [ + "CMT_FIFO_WW4A2_4", + "CMT_TOP_WW4A2_4" + ], + [ + "CMT_FIFO_MONITOR_N_6", + "CMT_TOP_MONITOR_N_6" + ], + [ + "CMT_FIFO_WR1END0_8", + "CMT_TOP_WR1END0_8" + ], + [ + "CMT_FIFO_WW2END3_4", + "CMT_TOP_WW2END3_4" + ], + [ + "CMT_FIFO_L_BYP1_2", + "CMT_TOP_BYP1_2" + ], + [ + "CMT_FIFO_L_IMUX46_11", + "CMT_TOP_IMUX46_11" + ], + [ + "CMT_FIFO_EE4BEG0_3", + "CMT_TOP_EE4BEG0_3" + ], + [ + "CMT_FIFO_L_BYP0_9", + "CMT_TOP_BYP0_9" + ], + [ + "CMT_FIFO_EE4BEG0_7", + "CMT_TOP_EE4BEG0_7" + ], + [ + "CMT_FIFO_SE4BEG0_6", + "CMT_TOP_SE4BEG0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_8", + "CMT_TOP_LOGIC_OUTS_L_B18_8" + ], + [ + "CMT_FIFO_L_IMUX27_11", + "CMT_TOP_IMUX27_11" + ], + [ + "CMT_FIFO_SE2A1_6", + "CMT_TOP_SE2A1_6" + ], + [ + "CMT_FIFO_NW4A0_4", + "CMT_TOP_NW4A0_4" + ], + [ + "CMT_FIFO_L_IMUX39_1", + "CMT_TOP_IMUX39_1" + ], + [ + "CMT_FIFO_EE4C2_4", + "CMT_TOP_EE4C2_4" + ], + [ + "CMT_FIFO_NE2A0_5", + "CMT_TOP_NE2A0_5" + ], + [ + "CMT_FIFO_L_CLK0_5", + "CMT_TOP_CLK0_5" + ], + [ + "CMT_FIFO_L_IMUX24_0", + "CMT_TOP_IMUX24_0" + ], + [ + "CMT_FIFO_EE4A2_5", + "CMT_TOP_EE4A2_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "CMT_TOP_OCLK_6" + ], + [ + "CMT_FIFO_L_IMUX8_7", + "CMT_TOP_IMUX8_7" + ], + [ + "CMT_FIFO_L_IMUX36_0", + "CMT_TOP_IMUX36_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_10", + "CMT_TOP_LOGIC_OUTS_L_B11_10" + ], + [ + "CMT_FIFO_L_IMUX39_2", + "CMT_TOP_IMUX39_2" + ], + [ + "CMT_FIFO_L_IMUX9_6", + "CMT_TOP_IMUX9_6" + ], + [ + "CMT_FIFO_NW4A1_4", + "CMT_TOP_NW4A1_4" + ], + [ + "CMT_FIFO_EE4C1_2", + "CMT_TOP_EE4C1_2" + ], + [ + "CMT_FIFO_L_IMUX44_0", + "CMT_TOP_IMUX44_0" + ], + [ + "CMT_FIFO_L_IMUX14_6", + "CMT_TOP_IMUX14_6" + ], + [ + "CMT_FIFO_L_IMUX16_10", + "CMT_TOP_IMUX16_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_5", + "CMT_TOP_LOGIC_OUTS_L_B19_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_4", + "CMT_TOP_LOGIC_OUTS_L_B15_4" + ], + [ + "CMT_FIFO_EE4A0_3", + "CMT_TOP_EE4A0_3" + ], + [ + "CMT_FIFO_L_FAN6_2", + "CMT_TOP_FAN6_2" + ], + [ + "CMT_FIFO_WW4B2_11", + "CMT_TOP_WW4B2_11" + ], + [ + "CMT_FIFO_L_BYP0_11", + "CMT_TOP_BYP0_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "CMT_TOP_ICLKDIV_0" + ], + [ + "CMT_FIFO_WW4C2_0", + "CMT_TOP_WW4C2_0" + ], + [ + "CMT_FIFO_L_IMUX28_1", + "CMT_TOP_IMUX28_1" + ], + [ + "CMT_FIFO_WW4B1_6", + "CMT_TOP_WW4B1_6" + ], + [ + "CMT_FIFO_EE4BEG0_4", + "CMT_TOP_EE4BEG0_4" + ], + [ + "CMT_FIFO_EE2A2_3", + "CMT_TOP_EE2A2_3" + ], + [ + "CMT_FIFO_EE4BEG1_9", + "CMT_TOP_EE4BEG1_9" + ], + [ + "CMT_FIFO_SE2A1_2", + "CMT_TOP_SE2A1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "CMT_TOP_ICLK_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_1", + "CMT_TOP_LOGIC_OUTS_L_B1_1" + ], + [ + "CMT_FIFO_WR1END2_6", + "CMT_TOP_WR1END2_6" + ], + [ + "CMT_FIFO_NW4END0_9", + "CMT_TOP_NW4END0_9" + ], + [ + "CMT_FIFO_EE4C2_3", + "CMT_TOP_EE4C2_3" + ], + [ + "CMT_FIFO_SE4C0_7", + "CMT_TOP_SE4C0_7" + ], + [ + "CMT_FIFO_L_IMUX15_7", + "CMT_TOP_IMUX15_7" + ], + [ + "CMT_FIFO_L_FAN0_9", + "CMT_TOP_FAN0_9" + ], + [ + "CMT_FIFO_SW4A3_6", + "CMT_TOP_SW4A3_6" + ], + [ + "CMT_FIFO_L_IMUX35_7", + "CMT_TOP_IMUX35_7" + ], + [ + "CMT_FIFO_ER1BEG0_5", + "CMT_TOP_ER1BEG0_5" + ], + [ + "CMT_FIFO_L_IMUX6_0", + "CMT_TOP_IMUX6_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_4", + "CMT_TOP_LOGIC_OUTS_L_B0_4" + ], + [ + "CMT_FIFO_NE4C0_6", + "CMT_TOP_NE4C0_6" + ], + [ + "CMT_FIFO_EE2A0_8", + "CMT_TOP_EE2A0_8" + ], + [ + "CMT_FIFO_EE4BEG3_4", + "CMT_TOP_EE4BEG3_4" + ], + [ + "CMT_FIFO_NE2A3_3", + "CMT_TOP_NE2A3_3" + ], + [ + "CMT_FIFO_SW2A3_4", + "CMT_TOP_SW2A3_4" + ], + [ + "CMT_FIFO_LH6_0", + "CMT_TOP_LH6_0" + ], + [ + "CMT_FIFO_EE2BEG3_0", + "CMT_TOP_EE2BEG3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_0", + "CMT_TOP_LOGIC_OUTS_L_B1_0" + ], + [ + "CMT_FIFO_SW2A2_7", + "CMT_TOP_SW2A2_7" + ], + [ + "CMT_FIFO_EE4B2_11", + "CMT_TOP_EE4B2_11" + ], + [ + "CMT_FIFO_WW4END2_6", + "CMT_TOP_WW4END2_6" + ], + [ + "CMT_FIFO_WW4B3_10", + "CMT_TOP_WW4B3_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_1", + "CMT_TOP_LOGIC_OUTS_L_B5_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_5", + "CMT_TOP_LOGIC_OUTS_L_B9_5" + ], + [ + "CMT_FIFO_SW2A2_1", + "CMT_TOP_SW2A2_1" + ], + [ + "CMT_FIFO_EE2A1_11", + "CMT_TOP_EE2A1_11" + ], + [ + "CMT_FIFO_L_IMUX3_6", + "CMT_TOP_IMUX3_6" + ], + [ + "CMT_FIFO_NE4BEG2_5", + "CMT_TOP_NE4BEG2_5" + ], + [ + "CMT_FIFO_L_FAN5_5", + "CMT_TOP_FAN5_5" + ], + [ + "CMT_FIFO_NE4BEG0_7", + "CMT_TOP_NE4BEG0_7" + ], + [ + "CMT_FIFO_L_IMUX14_3", + "CMT_TOP_IMUX14_3" + ], + [ + "CMT_FIFO_EE2BEG0_10", + "CMT_TOP_EE2BEG0_10" + ], + [ + "CMT_FIFO_L_BYP1_8", + "CMT_TOP_BYP1_8" + ], + [ + "CMT_FIFO_L_IMUX19_4", + "CMT_TOP_IMUX19_4" + ], + [ + "CMT_FIFO_LH4_2", + "CMT_TOP_LH4_2" + ], + [ + "CMT_FIFO_WW2A1_8", + "CMT_TOP_WW2A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6" + ], + [ + "CMT_FIFO_WL1END3_2", + "CMT_TOP_WL1END3_2" + ], + [ + "CMT_FIFO_L_IMUX29_1", + "CMT_TOP_IMUX29_1" + ], + [ + "CMT_FIFO_SW4A1_0", + "CMT_TOP_SW4A1_0" + ], + [ + "CMT_FIFO_EE2A3_8", + "CMT_TOP_EE2A3_8" + ], + [ + "CMT_FIFO_L_CLK1_0", + "CMT_TOP_CLK1_0" + ], + [ + "CMT_FIFO_L_IMUX26_7", + "CMT_TOP_IMUX26_7" + ], + [ + "CMT_FIFO_EE4C1_11", + "CMT_TOP_EE4C1_11" + ], + [ + "CMT_FIFO_NE2A0_7", + "CMT_TOP_NE2A0_7" + ], + [ + "CMT_FIFO_LH6_9", + "CMT_TOP_LH6_9" + ], + [ + "CMT_FIFO_NW2A3_4", + "CMT_TOP_NW2A3_4" + ], + [ + "CMT_FIFO_EE2A3_11", + "CMT_TOP_EE2A3_11" + ], + [ + "CMT_FIFO_L_IMUX3_8", + "CMT_TOP_IMUX3_8" + ], + [ + "CMT_FIFO_NE4C2_5", + "CMT_TOP_NE4C2_5" + ], + [ + "CMT_FIFO_L_BYP2_1", + "CMT_TOP_BYP2_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "CMT_TOP_OCLK_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_2", + "CMT_TOP_LOGIC_OUTS_L_B0_2" + ], + [ + "CMT_FIFO_L_IMUX28_9", + "CMT_TOP_IMUX28_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_2", + "CMT_TOP_LOGIC_OUTS_L_B14_2" + ], + [ + "CMT_FIFO_L_IMUX27_4", + "CMT_TOP_IMUX27_4" + ], + [ + "CMT_FIFO_SE4BEG3_1", + "CMT_TOP_SE4BEG3_1" + ], + [ + "CMT_FIFO_NE4C2_9", + "CMT_TOP_NE4C2_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "CMT_TOP_OCLK_1" + ], + [ + "CMT_FIFO_NE4BEG3_11", + "CMT_TOP_NE4BEG3_11" + ], + [ + "CMT_FIFO_ER1BEG1_9", + "CMT_TOP_ER1BEG1_9" + ], + [ + "CMT_FIFO_LH3_4", + "CMT_TOP_LH3_4" + ], + [ + "CMT_FIFO_LH5_7", + "CMT_TOP_LH5_7" + ], + [ + "CMT_FIFO_L_FAN2_7", + "CMT_TOP_FAN2_7" + ], + [ + "CMT_FIFO_WW2END2_3", + "CMT_TOP_WW2END2_3" + ], + [ + "CMT_FIFO_L_IMUX25_4", + "CMT_TOP_IMUX25_4" + ], + [ + "CMT_FIFO_L_IMUX40_1", + "CMT_TOP_IMUX40_1" + ], + [ + "CMT_FIFO_WL1END0_0", + "CMT_TOP_WL1END0_0" + ], + [ + "CMT_FIFO_L_BYP2_7", + "CMT_TOP_BYP2_7" + ], + [ + "CMT_FIFO_L_CTRL1_8", + "CMT_TOP_CTRL1_8" + ], + [ + "CMT_FIFO_EE4B3_3", + "CMT_TOP_EE4B3_3" + ], + [ + "CMT_FIFO_L_IMUX0_11", + "CMT_TOP_IMUX0_11" + ], + [ + "CMT_FIFO_WW2A1_5", + "CMT_TOP_WW2A1_5" + ], + [ + "CMT_FIFO_WL1END0_1", + "CMT_TOP_WL1END0_1" + ], + [ + "CMT_FIFO_L_BYP4_8", + "CMT_TOP_BYP4_8" + ], + [ + "CMT_FIFO_NW4A1_9", + "CMT_TOP_NW4A1_9" + ], + [ + "CMT_FIFO_NW4END1_9", + "CMT_TOP_NW4END1_9" + ], + [ + "CMT_FIFO_WR1END2_1", + "CMT_TOP_WR1END2_1" + ], + [ + "CMT_FIFO_EE4A3_3", + "CMT_TOP_EE4A3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_0", + "CMT_TOP_LOGIC_OUTS_L_B20_0" + ], + [ + "CMT_FIFO_SE2A2_6", + "CMT_TOP_SE2A2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_1", + "CMT_TOP_LOGIC_OUTS_L_B13_1" + ], + [ + "CMT_FIFO_L_IMUX6_5", + "CMT_TOP_IMUX6_5" + ], + [ + "CMT_FIFO_WR1END2_10", + "CMT_TOP_WR1END2_10" + ], + [ + "CMT_FIFO_LH9_1", + "CMT_TOP_LH9_1" + ], + [ + "CMT_FIFO_NW4A3_9", + "CMT_TOP_NW4A3_9" + ], + [ + "CMT_FIFO_SE2A3_6", + "CMT_TOP_SE2A3_6" + ], + [ + "CMT_FIFO_L_IMUX44_4", + "CMT_TOP_IMUX44_4" + ], + [ + "CMT_FIFO_L_IMUX35_6", + "CMT_TOP_IMUX35_6" + ], + [ + "CMT_FIFO_WR1END3_8", + "CMT_TOP_WR1END3_8" + ], + [ + "CMT_FIFO_NW2A0_11", + "CMT_TOP_NW2A0_11" + ], + [ + "CMT_FIFO_L_IMUX33_9", + "CMT_TOP_IMUX33_9" + ], + [ + "CMT_FIFO_EE2BEG1_9", + "CMT_TOP_EE2BEG1_9" + ], + [ + "CMT_FIFO_SE2A3_7", + "CMT_TOP_SE2A3_7" + ], + [ + "CMT_FIFO_EE4B3_4", + "CMT_TOP_EE4B3_4" + ], + [ + "CMT_FIFO_L_IMUX19_7", + "CMT_TOP_IMUX19_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "CMT_TOP_OCLK_0" + ], + [ + "CMT_FIFO_L_IMUX6_8", + "CMT_TOP_IMUX6_8" + ], + [ + "CMT_FIFO_L_CTRL0_4", + "CMT_TOP_CTRL0_4" + ], + [ + "CMT_FIFO_L_IMUX29_4", + "CMT_TOP_IMUX29_4" + ], + [ + "CMT_FIFO_WW4A1_10", + "CMT_TOP_WW4A1_10" + ], + [ + "CMT_FIFO_NE2A1_3", + "CMT_TOP_NE2A1_3" + ], + [ + "CMT_FIFO_L_IMUX46_0", + "CMT_TOP_IMUX46_0" + ], + [ + "CMT_FIFO_WW4B3_8", + "CMT_TOP_WW4B3_8" + ], + [ + "CMT_FIFO_L_IMUX35_8", + "CMT_TOP_IMUX35_8" + ], + [ + "CMT_FIFO_SW4END0_0", + "CMT_TOP_SW4END0_0" + ], + [ + "CMT_FIFO_EE4BEG2_0", + "CMT_TOP_EE4BEG2_0" + ], + [ + "CMT_FIFO_MONITOR_N_10", + "CMT_TOP_MONITOR_N_10" + ], + [ + "CMT_FIFO_L_FAN3_7", + "CMT_TOP_FAN3_7" + ], + [ + "CMT_FIFO_WW2END2_2", + "CMT_TOP_WW2END2_2" + ], + [ + "CMT_FIFO_EE4A1_8", + "CMT_TOP_EE4A1_8" + ], + [ + "CMT_FIFO_NW4END2_6", + "CMT_TOP_NW4END2_6" + ], + [ + "CMT_FIFO_EE2A0_11", + "CMT_TOP_EE2A0_11" + ], + [ + "CMT_FIFO_EE4B1_8", + "CMT_TOP_EE4B1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_1", + "CMT_TOP_LOGIC_OUTS_L_B22_1" + ], + [ + "CMT_FIFO_L_IMUX39_5", + "CMT_TOP_IMUX39_5" + ], + [ + "CMT_FIFO_LH2_5", + "CMT_TOP_LH2_5" + ], + [ + "CMT_FIFO_SW2A3_10", + "CMT_TOP_SW2A3_10" + ], + [ + "CMT_FIFO_WW4END0_8", + "CMT_TOP_WW4END0_8" + ], + [ + "CMT_FIFO_SE2A3_8", + "CMT_TOP_SE2A3_8" + ], + [ + "CMT_FIFO_L_IMUX29_7", + "CMT_TOP_IMUX29_7" + ], + [ + "CMT_FIFO_L_CTRL0_7", + "CMT_TOP_CTRL0_7" + ], + [ + "CMT_FIFO_L_BYP1_5", + "CMT_TOP_BYP1_5" + ], + [ + "CMT_FIFO_NE2A0_11", + "CMT_TOP_NE2A0_11" + ], + [ + "CMT_FIFO_L_IMUX20_8", + "CMT_TOP_IMUX20_8" + ], + [ + "CMT_FIFO_WR1END1_0", + "CMT_TOP_WR1END1_0" + ], + [ + "CMT_FIFO_EE4BEG1_4", + "CMT_TOP_EE4BEG1_4" + ], + [ + "CMT_FIFO_WW2END2_10", + "CMT_TOP_WW2END2_10" + ], + [ + "CMT_FIFO_L_CTRL0_6", + "CMT_TOP_CTRL0_6" + ], + [ + "CMT_FIFO_WW4C0_4", + "CMT_TOP_WW4C0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_0", + "CMT_TOP_LOGIC_OUTS_L_B2_0" + ], + [ + "CMT_FIFO_NE2A2_8", + "CMT_TOP_NE2A2_8" + ], + [ + "CMT_FIFO_L_IMUX4_6", + "CMT_TOP_IMUX4_6" + ], + [ + "CMT_FIFO_SW4END0_3", + "CMT_TOP_SW4END0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_0", + "CMT_TOP_LOGIC_OUTS_L_B4_0" + ], + [ + "CMT_FIFO_SW4END0_11", + "CMT_TOP_SW4END0_11" + ], + [ + "CMT_FIFO_EE2A0_1", + "CMT_TOP_EE2A0_1" + ], + [ + "CMT_FIFO_EE4B1_2", + "CMT_TOP_EE4B1_2" + ], + [ + "CMT_FIFO_NE4C3_0", + "CMT_TOP_NE4C3_0" + ], + [ + "CMT_FIFO_L_IMUX40_5", + "CMT_TOP_IMUX40_5" + ], + [ + "CMT_FIFO_WW2END1_2", + "CMT_TOP_WW2END1_2" + ], + [ + "CMT_FIFO_WW2A0_0", + "CMT_TOP_WW2A0_0" + ], + [ + "CMT_FIFO_EE2BEG1_11", + "CMT_TOP_EE2BEG1_11" + ], + [ + "CMT_FIFO_EE4A1_2", + "CMT_TOP_EE4A1_2" + ], + [ + "CMT_FIFO_ER1BEG2_3", + "CMT_TOP_ER1BEG2_3" + ], + [ + "CMT_FIFO_L_IMUX33_2", + "CMT_TOP_IMUX33_2" + ], + [ + "CMT_FIFO_SW2A2_8", + "CMT_TOP_SW2A2_8" + ], + [ + "CMT_FIFO_L_IMUX13_0", + "CMT_TOP_IMUX13_0" + ], + [ + "CMT_FIFO_EE2BEG1_1", + "CMT_TOP_EE2BEG1_1" + ], + [ + "CMT_FIFO_WW4C3_0", + "CMT_TOP_WW4C3_0" + ], + [ + "CMT_FIFO_WL1END1_1", + "CMT_TOP_WL1END1_1" + ], + [ + "CMT_FIFO_L_IMUX18_3", + "CMT_TOP_IMUX18_3" + ], + [ + "CMT_FIFO_WL1END0_9", + "CMT_TOP_WL1END0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_11", + "CMT_TOP_LOGIC_OUTS_L_B4_11" + ], + [ + "CMT_FIFO_L_IMUX44_3", + "CMT_TOP_IMUX44_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_2", + "CMT_TOP_LOGIC_OUTS_L_B19_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5" + ], + [ + "CMT_FIFO_L_IMUX23_7", + "CMT_TOP_IMUX23_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_6", + "CMT_TOP_LOGIC_OUTS_L_B19_6" + ], + [ + "CMT_FIFO_L_IMUX2_0", + "CMT_TOP_IMUX2_0" + ], + [ + "CMT_FIFO_L_IMUX35_9", + "CMT_TOP_IMUX35_9" + ], + [ + "CMT_FIFO_WR1END1_7", + "CMT_TOP_WR1END1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_4", + "CMT_TOP_LOGIC_OUTS_L_B6_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_9", + "CMT_TOP_LOGIC_OUTS_L_B17_9" + ], + [ + "CMT_FIFO_L_IMUX39_8", + "CMT_TOP_IMUX39_8" + ], + [ + "CMT_FIFO_WR1END3_4", + "CMT_TOP_WR1END3_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "CMT_TOP_ICLKDIV_9" + ], + [ + "CMT_FIFO_NE4BEG3_1", + "CMT_TOP_NE4BEG3_1" + ], + [ + "CMT_FIFO_WL1END2_6", + "CMT_TOP_WL1END2_6" + ], + [ + "CMT_FIFO_SE2A3_11", + "CMT_TOP_SE2A3_11" + ], + [ + "CMT_FIFO_NW4A3_7", + "CMT_TOP_NW4A3_7" + ], + [ + "CMT_FIFO_L_BYP0_7", + "CMT_TOP_BYP0_7" + ], + [ + "CMT_FIFO_SW2A0_3", + "CMT_TOP_SW2A0_3" + ], + [ + "CMT_FIFO_EE2BEG2_8", + "CMT_TOP_EE2BEG2_8" + ], + [ + "CMT_FIFO_EE2A1_6", + "CMT_TOP_EE2A1_6" + ], + [ + "CMT_FIFO_EE4C1_7", + "CMT_TOP_EE4C1_7" + ], + [ + "CMT_FIFO_WW4A0_10", + "CMT_TOP_WW4A0_10" + ], + [ + "CMT_FIFO_WR1END2_9", + "CMT_TOP_WR1END2_9" + ], + [ + "CMT_FIFO_WW4C3_6", + "CMT_TOP_WW4C3_6" + ], + [ + "CMT_FIFO_WW4END2_7", + "CMT_TOP_WW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX6_11", + "CMT_TOP_IMUX6_11" + ], + [ + "CMT_FIFO_L_IMUX10_6", + "CMT_TOP_IMUX10_6" + ], + [ + "CMT_FIFO_LH9_7", + "CMT_TOP_LH9_7" + ], + [ + "CMT_FIFO_L_CTRL1_0", + "CMT_TOP_CTRL1_0" + ], + [ + "CMT_FIFO_L_IMUX1_3", + "CMT_TOP_IMUX1_3" + ], + [ + "CMT_FIFO_WW2END3_10", + "CMT_TOP_WW2END3_10" + ], + [ + "CMT_FIFO_WW2A2_1", + "CMT_TOP_WW2A2_1" + ], + [ + "CMT_FIFO_L_CLK1_6", + "CMT_TOP_CLK1_6" + ], + [ + "CMT_FIFO_LH8_9", + "CMT_TOP_LH8_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_8", + "CMT_TOP_LOGIC_OUTS_L_B3_8" + ], + [ + "CMT_FIFO_L_IMUX46_5", + "CMT_TOP_IMUX46_5" + ], + [ + "CMT_FIFO_WW4A1_4", + "CMT_TOP_WW4A1_4" + ], + [ + "CMT_FIFO_L_IMUX25_11", + "CMT_TOP_IMUX25_11" + ], + [ + "CMT_FIFO_L_IMUX2_9", + "CMT_TOP_IMUX2_9" + ], + [ + "CMT_FIFO_SE4C3_0", + "CMT_TOP_SE4C3_0" + ], + [ + "CMT_FIFO_WW4C2_4", + "CMT_TOP_WW4C2_4" + ], + [ + "CMT_FIFO_WW4C1_6", + "CMT_TOP_WW4C1_6" + ], + [ + "CMT_FIFO_L_IMUX38_1", + "CMT_TOP_IMUX38_1" + ], + [ + "CMT_FIFO_MONITOR_P_0", + "CMT_TOP_MONITOR_P_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_0" + ], + [ + "CMT_FIFO_WL1END1_4", + "CMT_TOP_WL1END1_4" + ], + [ + "CMT_FIFO_EE4A2_0", + "CMT_TOP_EE4A2_0" + ], + [ + "CMT_FIFO_EL1BEG3_10", + "CMT_TOP_EL1BEG3_10" + ], + [ + "CMT_FIFO_L_IMUX27_0", + "CMT_TOP_IMUX27_0" + ], + [ + "CMT_FIFO_NE4C0_7", + "CMT_TOP_NE4C0_7" + ], + [ + "CMT_FIFO_ER1BEG1_2", + "CMT_TOP_ER1BEG1_2" + ], + [ + "CMT_FIFO_NE2A1_10", + "CMT_TOP_NE2A1_10" + ], + [ + "CMT_FIFO_SE4BEG3_6", + "CMT_TOP_SE4BEG3_6" + ], + [ + "CMT_FIFO_WL1END3_11", + "CMT_TOP_WL1END3_11" + ], + [ + "CMT_FIFO_SW4A1_6", + "CMT_TOP_SW4A1_6" + ], + [ + "CMT_FIFO_EE4A3_9", + "CMT_TOP_EE4A3_9" + ], + [ + "CMT_FIFO_EL1BEG0_2", + "CMT_TOP_EL1BEG0_2" + ], + [ + "CMT_FIFO_WW4C3_3", + "CMT_TOP_WW4C3_3" + ], + [ + "CMT_FIFO_SW4END0_6", + "CMT_TOP_SW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX41_4", + "CMT_TOP_IMUX41_4" + ], + [ + "CMT_FIFO_L_FAN3_3", + "CMT_TOP_FAN3_3" + ], + [ + "CMT_FIFO_WW4C2_1", + "CMT_TOP_WW4C2_1" + ], + [ + "CMT_FIFO_L_BYP3_2", + "CMT_TOP_BYP3_2" + ], + [ + "CMT_FIFO_L_IMUX8_3", + "CMT_TOP_IMUX8_3" + ], + [ + "CMT_FIFO_LH6_11", + "CMT_TOP_LH6_11" + ], + [ + "CMT_FIFO_EE2A2_9", + "CMT_TOP_EE2A2_9" + ], + [ + "CMT_FIFO_WW2A0_7", + "CMT_TOP_WW2A0_7" + ], + [ + "CMT_FIFO_WW4END2_5", + "CMT_TOP_WW4END2_5" + ], + [ + "CMT_FIFO_WW2END0_7", + "CMT_TOP_WW2END0_7" + ], + [ + "CMT_FIFO_EE4B0_1", + "CMT_TOP_EE4B0_1" + ], + [ + "CMT_FIFO_L_IMUX38_10", + "CMT_TOP_IMUX38_10" + ], + [ + "CMT_FIFO_NE2A2_10", + "CMT_TOP_NE2A2_10" + ], + [ + "CMT_FIFO_EE2A3_2", + "CMT_TOP_EE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX4_3", + "CMT_TOP_IMUX4_3" + ], + [ + "CMT_FIFO_L_FAN2_6", + "CMT_TOP_FAN2_6" + ], + [ + "CMT_FIFO_WW4END0_2", + "CMT_TOP_WW4END0_2" + ], + [ + "CMT_FIFO_NE4BEG0_3", + "CMT_TOP_NE4BEG0_3" + ], + [ + "CMT_FIFO_SW4END3_8", + "CMT_TOP_SW4END3_8" + ], + [ + "CMT_FIFO_LH6_7", + "CMT_TOP_LH6_7" + ], + [ + "CMT_FIFO_WW2END0_6", + "CMT_TOP_WW2END0_6" + ], + [ + "CMT_FIFO_NW4A2_1", + "CMT_TOP_NW4A2_1" + ], + [ + "CMT_FIFO_WW2A3_4", + "CMT_TOP_WW2A3_4" + ], + [ + "CMT_FIFO_SW4A0_8", + "CMT_TOP_SW4A0_8" + ], + [ + "CMT_FIFO_L_IMUX19_6", + "CMT_TOP_IMUX19_6" + ], + [ + "CMT_FIFO_EL1BEG3_0", + "CMT_TOP_EL1BEG3_0" + ], + [ + "CMT_FIFO_LH3_1", + "CMT_TOP_LH3_1" + ], + [ + "CMT_FIFO_L_IMUX10_1", + "CMT_TOP_IMUX10_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_3", + "CMT_TOP_LOGIC_OUTS_L_B16_3" + ], + [ + "CMT_FIFO_WW4END1_10", + "CMT_TOP_WW4END1_10" + ], + [ + "CMT_FIFO_L_IMUX43_6", + "CMT_TOP_IMUX43_6" + ], + [ + "CMT_FIFO_L_FAN2_4", + "CMT_TOP_FAN2_4" + ], + [ + "CMT_FIFO_WR1END2_11", + "CMT_TOP_WR1END2_11" + ], + [ + "CMT_FIFO_NW4END0_11", + "CMT_TOP_NW4END0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_2", + "CMT_TOP_LOGIC_OUTS_L_B2_2" + ], + [ + "CMT_FIFO_SE4BEG2_11", + "CMT_TOP_SE4BEG2_11" + ], + [ + "CMT_FIFO_EE2A3_3", + "CMT_TOP_EE2A3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_5", + "CMT_TOP_LOGIC_OUTS_L_B22_5" + ], + [ + "CMT_FIFO_SW4A0_0", + "CMT_TOP_SW4A0_0" + ], + [ + "CMT_FIFO_NE4BEG3_7", + "CMT_TOP_NE4BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX9_1", + "CMT_TOP_IMUX9_1" + ], + [ + "CMT_FIFO_NW4A3_2", + "CMT_TOP_NW4A3_2" + ], + [ + "CMT_FIFO_NW4A0_1", + "CMT_TOP_NW4A0_1" + ], + [ + "CMT_FIFO_WW4END0_1", + "CMT_TOP_WW4END0_1" + ], + [ + "CMT_FIFO_L_IMUX37_9", + "CMT_TOP_IMUX37_9" + ], + [ + "CMT_FIFO_L_IMUX7_7", + "CMT_TOP_IMUX7_7" + ], + [ + "CMT_FIFO_NE2A2_6", + "CMT_TOP_NE2A2_6" + ], + [ + "CMT_FIFO_EE2A1_10", + "CMT_TOP_EE2A1_10" + ], + [ + "CMT_FIFO_NE4BEG2_3", + "CMT_TOP_NE4BEG2_3" + ], + [ + "CMT_FIFO_WW2END2_6", + "CMT_TOP_WW2END2_6" + ], + [ + "CMT_FIFO_SW4A2_9", + "CMT_TOP_SW4A2_9" + ], + [ + "CMT_FIFO_L_IMUX1_6", + "CMT_TOP_IMUX1_6" + ], + [ + "CMT_FIFO_L_IMUX18_7", + "CMT_TOP_IMUX18_7" + ], + [ + "CMT_FIFO_WR1END2_2", + "CMT_TOP_WR1END2_2" + ], + [ + "CMT_FIFO_L_IMUX41_3", + "CMT_TOP_IMUX41_3" + ], + [ + "CMT_FIFO_L_IMUX17_9", + "CMT_TOP_IMUX17_9" + ], + [ + "CMT_FIFO_EE4BEG3_5", + "CMT_TOP_EE4BEG3_5" + ], + [ + "CMT_FIFO_NW2A0_1", + "CMT_TOP_NW2A0_1" + ], + [ + "CMT_FIFO_EE4A1_11", + "CMT_TOP_EE4A1_11" + ], + [ + "CMT_FIFO_SE2A0_11", + "CMT_TOP_SE2A0_11" + ], + [ + "CMT_FIFO_L_IMUX10_11", + "CMT_TOP_IMUX10_11" + ], + [ + "CMT_FIFO_L_IMUX47_5", + "CMT_TOP_IMUX47_5" + ], + [ + "CMT_FIFO_L_IMUX42_2", + "CMT_TOP_IMUX42_2" + ], + [ + "CMT_FIFO_L_IMUX36_11", + "CMT_TOP_IMUX36_11" + ], + [ + "CMT_FIFO_L_IMUX5_0", + "CMT_TOP_IMUX5_0" + ], + [ + "CMT_FIFO_LH1_0", + "CMT_TOP_LH1_0" + ], + [ + "CMT_FIFO_L_IMUX17_10", + "CMT_TOP_IMUX17_10" + ], + [ + "CMT_FIFO_WW4C1_2", + "CMT_TOP_WW4C1_2" + ], + [ + "CMT_FIFO_WR1END1_4", + "CMT_TOP_WR1END1_4" + ], + [ + "CMT_FIFO_WW4C3_1", + "CMT_TOP_WW4C3_1" + ], + [ + "CMT_FIFO_EE4C1_5", + "CMT_TOP_EE4C1_5" + ], + [ + "CMT_FIFO_LH5_6", + "CMT_TOP_LH5_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_9", + "CMT_TOP_LOGIC_OUTS_L_B16_9" + ], + [ + "CMT_FIFO_EL1BEG2_5", + "CMT_TOP_EL1BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX3_4", + "CMT_TOP_IMUX3_4" + ], + [ + "CMT_FIFO_L_IMUX21_8", + "CMT_TOP_IMUX21_8" + ], + [ + "CMT_FIFO_L_FAN2_2", + "CMT_TOP_FAN2_2" + ], + [ + "CMT_FIFO_L_IMUX44_6", + "CMT_TOP_IMUX44_6" + ], + [ + "CMT_FIFO_L_BYP3_10", + "CMT_TOP_BYP3_10" + ], + [ + "CMT_FIFO_LH11_6", + "CMT_TOP_LH11_6" + ], + [ + "CMT_FIFO_NE4BEG0_9", + "CMT_TOP_NE4BEG0_9" + ], + [ + "CMT_FIFO_L_IMUX7_6", + "CMT_TOP_IMUX7_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_9", + "CMT_TOP_LOGIC_OUTS_L_B12_9" + ], + [ + "CMT_FIFO_EE2A2_5", + "CMT_TOP_EE2A2_5" + ], + [ + "CMT_FIFO_LH11_1", + "CMT_TOP_LH11_1" + ], + [ + "CMT_FIFO_NW2A2_2", + "CMT_TOP_NW2A2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_0" + ], + [ + "CMT_FIFO_SW4A1_2", + "CMT_TOP_SW4A1_2" + ], + [ + "CMT_FIFO_EE4C0_0", + "CMT_TOP_EE4C0_0" + ], + [ + "CMT_FIFO_L_IMUX35_0", + "CMT_TOP_IMUX35_0" + ], + [ + "CMT_FIFO_EE2A3_9", + "CMT_TOP_EE2A3_9" + ], + [ + "CMT_FIFO_L_FAN3_10", + "CMT_TOP_FAN3_10" + ], + [ + "CMT_FIFO_L_BYP4_7", + "CMT_TOP_BYP4_7" + ], + [ + "CMT_FIFO_L_IMUX28_3", + "CMT_TOP_IMUX28_3" + ], + [ + "CMT_FIFO_EE2A0_0", + "CMT_TOP_EE2A0_0" + ], + [ + "CMT_FIFO_L_IMUX21_10", + "CMT_TOP_IMUX21_10" + ], + [ + "CMT_FIFO_SW4END2_5", + "CMT_TOP_SW4END2_5" + ], + [ + "CMT_FIFO_MONITOR_P_2", + "CMT_TOP_MONITOR_P_2" + ], + [ + "CMT_FIFO_SW2A0_8", + "CMT_TOP_SW2A0_8" + ], + [ + "CMT_FIFO_L_IMUX45_7", + "CMT_TOP_IMUX45_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_9", + "CMT_TOP_LOGIC_OUTS_L_B4_9" + ], + [ + "CMT_FIFO_SE4BEG1_3", + "CMT_TOP_SE4BEG1_3" + ], + [ + "CMT_FIFO_WR1END2_0", + "CMT_TOP_WR1END2_0" + ], + [ + "CMT_FIFO_L_CLK1_11", + "CMT_TOP_CLK1_11" + ], + [ + "CMT_FIFO_EE4A3_10", + "CMT_TOP_EE4A3_10" + ], + [ + "CMT_FIFO_SE4BEG2_8", + "CMT_TOP_SE4BEG2_8" + ], + [ + "CMT_FIFO_L_IMUX24_3", + "CMT_TOP_IMUX24_3" + ], + [ + "CMT_FIFO_EE2BEG1_4", + "CMT_TOP_EE2BEG1_4" + ], + [ + "CMT_FIFO_WW4B2_0", + "CMT_TOP_WW4B2_0" + ], + [ + "CMT_FIFO_NE4C0_3", + "CMT_TOP_NE4C0_3" + ], + [ + "CMT_FIFO_L_BYP7_7", + "CMT_TOP_BYP7_7" + ], + [ + "CMT_FIFO_L_FAN7_1", + "CMT_TOP_FAN7_1" + ], + [ + "CMT_FIFO_SW4A3_8", + "CMT_TOP_SW4A3_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "CMT_TOP_ICLK_8" + ], + [ + "CMT_FIFO_EE2A2_4", + "CMT_TOP_EE2A2_4" + ], + [ + "CMT_FIFO_LH6_10", + "CMT_TOP_LH6_10" + ], + [ + "CMT_FIFO_NE2A1_11", + "CMT_TOP_NE2A1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_4" + ], + [ + "CMT_FIFO_L_IMUX20_6", + "CMT_TOP_IMUX20_6" + ], + [ + "CMT_FIFO_L_IMUX14_9", + "CMT_TOP_IMUX14_9" + ], + [ + "CMT_FIFO_NW2A1_9", + "CMT_TOP_NW2A1_9" + ], + [ + "CMT_FIFO_SW4END3_6", + "CMT_TOP_SW4END3_6" + ], + [ + "CMT_FIFO_L_BYP6_4", + "CMT_TOP_BYP6_4" + ], + [ + "CMT_FIFO_L_IMUX37_3", + "CMT_TOP_IMUX37_3" + ], + [ + "CMT_FIFO_L_IMUX32_11", + "CMT_TOP_IMUX32_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_2", + "CMT_TOP_LOGIC_OUTS_L_B20_2" + ], + [ + "CMT_FIFO_EL1BEG0_3", + "CMT_TOP_EL1BEG0_3" + ], + [ + "CMT_FIFO_L_IMUX40_11", + "CMT_TOP_IMUX40_11" + ], + [ + "CMT_FIFO_WW4END1_11", + "CMT_TOP_WW4END1_11" + ], + [ + "CMT_FIFO_L_IMUX17_1", + "CMT_TOP_IMUX17_1" + ], + [ + "CMT_FIFO_L_IMUX29_3", + "CMT_TOP_IMUX29_3" + ], + [ + "CMT_FIFO_NW4A1_0", + "CMT_TOP_NW4A1_0" + ], + [ + "CMT_FIFO_SW4A2_6", + "CMT_TOP_SW4A2_6" + ], + [ + "CMT_FIFO_EE4B0_8", + "CMT_TOP_EE4B0_8" + ], + [ + "CMT_FIFO_EE2BEG3_4", + "CMT_TOP_EE2BEG3_4" + ], + [ + "CMT_FIFO_ER1BEG1_10", + "CMT_TOP_ER1BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX43_9", + "CMT_TOP_IMUX43_9" + ], + [ + "CMT_FIFO_LH8_7", + "CMT_TOP_LH8_7" + ], + [ + "CMT_FIFO_EE4B2_1", + "CMT_TOP_EE4B2_1" + ], + [ + "CMT_FIFO_NW4END2_3", + "CMT_TOP_NW4END2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_0", + "CMT_TOP_LOGIC_OUTS_L_B14_0" + ], + [ + "CMT_FIFO_WW4A3_5", + "CMT_TOP_WW4A3_5" + ], + [ + "CMT_FIFO_L_BYP6_6", + "CMT_TOP_BYP6_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "CMT_TOP_ICLKDIV_5" + ], + [ + "CMT_FIFO_L_IMUX3_7", + "CMT_TOP_IMUX3_7" + ], + [ + "CMT_FIFO_WW2A1_4", + "CMT_TOP_WW2A1_4" + ], + [ + "CMT_FIFO_EE4B1_6", + "CMT_TOP_EE4B1_6" + ], + [ + "CMT_FIFO_LH10_4", + "CMT_TOP_LH10_4" + ], + [ + "CMT_FIFO_L_IMUX45_3", + "CMT_TOP_IMUX45_3" + ], + [ + "CMT_FIFO_LH4_0", + "CMT_TOP_LH4_0" + ], + [ + "CMT_FIFO_EE2A1_8", + "CMT_TOP_EE2A1_8" + ], + [ + "CMT_FIFO_EE4C1_8", + "CMT_TOP_EE4C1_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "CMT_TOP_ICLKDIV_1" + ], + [ + "CMT_FIFO_L_IMUX8_11", + "CMT_TOP_IMUX8_11" + ], + [ + "CMT_FIFO_L_IMUX36_3", + "CMT_TOP_IMUX36_3" + ], + [ + "CMT_FIFO_SW4A2_0", + "CMT_TOP_SW4A2_0" + ], + [ + "CMT_FIFO_EE2A3_1", + "CMT_TOP_EE2A3_1" + ], + [ + "CMT_FIFO_WL1END2_8", + "CMT_TOP_WL1END2_8" + ], + [ + "CMT_FIFO_SW4A2_4", + "CMT_TOP_SW4A2_4" + ], + [ + "CMT_FIFO_EE4BEG0_10", + "CMT_TOP_EE4BEG0_10" + ], + [ + "CMT_FIFO_EE4C0_3", + "CMT_TOP_EE4C0_3" + ], + [ + "CMT_FIFO_NE4BEG2_8", + "CMT_TOP_NE4BEG2_8" + ], + [ + "CMT_FIFO_EE2A2_8", + "CMT_TOP_EE2A2_8" + ], + [ + "CMT_FIFO_SW2A3_7", + "CMT_TOP_SW2A3_7" + ], + [ + "CMT_FIFO_WW2A2_9", + "CMT_TOP_WW2A2_9" + ], + [ + "CMT_FIFO_SW4A3_3", + "CMT_TOP_SW4A3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_4", + "CMT_TOP_LOGIC_OUTS_L_B20_4" + ], + [ + "CMT_FIFO_NE4C3_3", + "CMT_TOP_NE4C3_3" + ], + [ + "CMT_FIFO_WL1END0_10", + "CMT_TOP_WL1END0_10" + ], + [ + "CMT_FIFO_L_IMUX8_5", + "CMT_TOP_IMUX8_5" + ], + [ + "CMT_FIFO_WW4B1_9", + "CMT_TOP_WW4B1_9" + ], + [ + "CMT_FIFO_NW2A0_9", + "CMT_TOP_NW2A0_9" + ], + [ + "CMT_FIFO_EE2A1_2", + "CMT_TOP_EE2A1_2" + ], + [ + "CMT_FIFO_WW4C0_0", + "CMT_TOP_WW4C0_0" + ], + [ + "CMT_FIFO_WW4B0_4", + "CMT_TOP_WW4B0_4" + ], + [ + "CMT_FIFO_NW2A3_3", + "CMT_TOP_NW2A3_3" + ], + [ + "CMT_FIFO_ER1BEG2_8", + "CMT_TOP_ER1BEG2_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "CMT_TOP_OCLKDIV_4" + ], + [ + "CMT_FIFO_WW4C2_10", + "CMT_TOP_WW4C2_10" + ], + [ + "CMT_FIFO_L_CTRL0_1", + "CMT_TOP_CTRL0_1" + ], + [ + "CMT_FIFO_SW2A0_1", + "CMT_TOP_SW2A0_1" + ], + [ + "CMT_FIFO_EE2BEG0_1", + "CMT_TOP_EE2BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_7", + "CMT_TOP_LOGIC_OUTS_L_B14_7" + ], + [ + "CMT_FIFO_EE2BEG1_6", + "CMT_TOP_EE2BEG1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_7", + "CMT_TOP_LOGIC_OUTS_L_B11_7" + ], + [ + "CMT_FIFO_L_IMUX12_4", + "CMT_TOP_IMUX12_4" + ], + [ + "CMT_FIFO_EE4B2_0", + "CMT_TOP_EE4B2_0" + ], + [ + "CMT_FIFO_SE4C3_11", + "CMT_TOP_SE4C3_11" + ], + [ + "CMT_FIFO_LH10_7", + "CMT_TOP_LH10_7" + ], + [ + "CMT_FIFO_EE2BEG2_2", + "CMT_TOP_EE2BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX23_1", + "CMT_TOP_IMUX23_1" + ], + [ + "CMT_FIFO_WW4A1_5", + "CMT_TOP_WW4A1_5" + ], + [ + "CMT_FIFO_WR1END0_0", + "CMT_TOP_WR1END0_0" + ], + [ + "CMT_FIFO_ER1BEG1_7", + "CMT_TOP_ER1BEG1_7" + ], + [ + "CMT_FIFO_EE4B2_10", + "CMT_TOP_EE4B2_10" + ], + [ + "CMT_FIFO_WW4A1_6", + "CMT_TOP_WW4A1_6" + ], + [ + "CMT_FIFO_L_IMUX42_9", + "CMT_TOP_IMUX42_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "CMT_TOP_ICLK_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_1", + "CMT_TOP_LOGIC_OUTS_L_B8_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_0", + "CMT_TOP_LOGIC_OUTS_L_B6_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "CMT_TOP_ICLK_9" + ], + [ + "CMT_FIFO_NE4BEG3_4", + "CMT_TOP_NE4BEG3_4" + ], + [ + "CMT_FIFO_EE2BEG3_9", + "CMT_TOP_EE2BEG3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_6", + "CMT_TOP_LOGIC_OUTS_L_B12_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_1", + "CMT_TOP_LOGIC_OUTS_L_B10_1" + ], + [ + "CMT_FIFO_NE2A0_6", + "CMT_TOP_NE2A0_6" + ], + [ + "CMT_FIFO_EE4BEG2_7", + "CMT_TOP_EE4BEG2_7" + ], + [ + "CMT_FIFO_NE4BEG1_1", + "CMT_TOP_NE4BEG1_1" + ], + [ + "CMT_FIFO_EE4C2_5", + "CMT_TOP_EE4C2_5" + ], + [ + "CMT_FIFO_WW4C1_3", + "CMT_TOP_WW4C1_3" + ], + [ + "CMT_FIFO_LH10_8", + "CMT_TOP_LH10_8" + ], + [ + "CMT_FIFO_L_IMUX15_0", + "CMT_TOP_IMUX15_0" + ], + [ + "CMT_FIFO_L_FAN7_3", + "CMT_TOP_FAN7_3" + ], + [ + "CMT_FIFO_L_CLK0_9", + "CMT_TOP_CLK0_9" + ], + [ + "CMT_FIFO_NE4BEG0_5", + "CMT_TOP_NE4BEG0_5" + ], + [ + "CMT_FIFO_WR1END0_5", + "CMT_TOP_WR1END0_5" + ], + [ + "CMT_FIFO_SE4BEG3_7", + "CMT_TOP_SE4BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX38_9", + "CMT_TOP_IMUX38_9" + ], + [ + "CMT_FIFO_EE4C1_3", + "CMT_TOP_EE4C1_3" + ], + [ + "CMT_FIFO_SE4C2_8", + "CMT_TOP_SE4C2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_2", + "CMT_TOP_LOGIC_OUTS_L_B12_2" + ], + [ + "CMT_FIFO_L_IMUX43_0", + "CMT_TOP_IMUX43_0" + ], + [ + "CMT_FIFO_L_IMUX15_1", + "CMT_TOP_IMUX15_1" + ], + [ + "CMT_FIFO_ER1BEG3_5", + "CMT_TOP_ER1BEG3_5" + ], + [ + "CMT_FIFO_L_BYP6_7", + "CMT_TOP_BYP6_7" + ], + [ + "CMT_FIFO_L_BYP3_3", + "CMT_TOP_BYP3_3" + ], + [ + "CMT_FIFO_NE2A3_11", + "CMT_TOP_NE2A3_11" + ], + [ + "CMT_FIFO_WL1END1_0", + "CMT_TOP_WL1END1_0" + ], + [ + "CMT_FIFO_L_IMUX21_0", + "CMT_TOP_IMUX21_0" + ], + [ + "CMT_FIFO_WL1END1_6", + "CMT_TOP_WL1END1_6" + ], + [ + "CMT_FIFO_L_IMUX26_2", + "CMT_TOP_IMUX26_2" + ], + [ + "CMT_FIFO_WL1END2_4", + "CMT_TOP_WL1END2_4" + ], + [ + "CMT_FIFO_WW4B0_5", + "CMT_TOP_WW4B0_5" + ], + [ + "CMT_FIFO_EE2A3_10", + "CMT_TOP_EE2A3_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_9", + "CMT_TOP_LOGIC_OUTS_L_B8_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_1", + "CMT_TOP_LOGIC_OUTS_L_B15_1" + ], + [ + "CMT_FIFO_WR1END0_7", + "CMT_TOP_WR1END0_7" + ], + [ + "CMT_FIFO_WW4END0_7", + "CMT_TOP_WW4END0_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_10", + "CMT_TOP_LOGIC_OUTS_L_B2_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_11", + "CMT_TOP_LOGIC_OUTS_L_B5_11" + ], + [ + "CMT_FIFO_L_IMUX24_4", + "CMT_TOP_IMUX24_4" + ], + [ + "CMT_FIFO_SE4BEG2_0", + "CMT_TOP_SE4BEG2_0" + ], + [ + "CMT_FIFO_SW2A2_5", + "CMT_TOP_SW2A2_5" + ], + [ + "CMT_FIFO_L_CTRL1_10", + "CMT_TOP_CTRL1_10" + ], + [ + "CMT_FIFO_L_IMUX7_4", + "CMT_TOP_IMUX7_4" + ], + [ + "CMT_FIFO_WW4C1_0", + "CMT_TOP_WW4C1_0" + ], + [ + "CMT_FIFO_L_IMUX47_7", + "CMT_TOP_IMUX47_7" + ], + [ + "CMT_FIFO_EE4A3_2", + "CMT_TOP_EE4A3_2" + ], + [ + "CMT_FIFO_WW4B3_4", + "CMT_TOP_WW4B3_4" + ], + [ + "CMT_FIFO_L_IMUX0_9", + "CMT_TOP_IMUX0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_9", + "CMT_TOP_LOGIC_OUTS_L_B0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_7", + "CMT_TOP_LOGIC_OUTS_L_B18_7" + ], + [ + "CMT_FIFO_WW4A3_2", + "CMT_TOP_WW4A3_2" + ], + [ + "CMT_FIFO_WW4A3_8", + "CMT_TOP_WW4A3_8" + ], + [ + "CMT_FIFO_L_BYP2_11", + "CMT_TOP_BYP2_11" + ], + [ + "CMT_FIFO_L_IMUX5_1", + "CMT_TOP_IMUX5_1" + ], + [ + "CMT_FIFO_L_IMUX5_8", + "CMT_TOP_IMUX5_8" + ], + [ + "CMT_FIFO_EL1BEG3_11", + "CMT_TOP_EL1BEG3_11" + ], + [ + "CMT_FIFO_NW4A1_8", + "CMT_TOP_NW4A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_4", + "CMT_TOP_LOGIC_OUTS_L_B21_4" + ], + [ + "CMT_FIFO_NE4C0_1", + "CMT_TOP_NE4C0_1" + ], + [ + "CMT_FIFO_WW4B0_3", + "CMT_TOP_WW4B0_3" + ], + [ + "CMT_FIFO_SW4A3_0", + "CMT_TOP_SW4A3_0" + ], + [ + "CMT_FIFO_LH10_9", + "CMT_TOP_LH10_9" + ], + [ + "CMT_FIFO_L_IMUX13_3", + "CMT_TOP_IMUX13_3" + ], + [ + "CMT_FIFO_NE4BEG2_7", + "CMT_TOP_NE4BEG2_7" + ], + [ + "CMT_FIFO_L_BYP0_6", + "CMT_TOP_BYP0_6" + ], + [ + "CMT_FIFO_EL1BEG0_11", + "CMT_TOP_EL1BEG0_11" + ], + [ + "CMT_FIFO_LH6_8", + "CMT_TOP_LH6_8" + ], + [ + "CMT_FIFO_L_IMUX28_4", + "CMT_TOP_IMUX28_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "CMT_TOP_ICLK_3" + ], + [ + "CMT_FIFO_WL1END3_9", + "CMT_TOP_WL1END3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_10", + "CMT_TOP_LOGIC_OUTS_L_B15_10" + ], + [ + "CMT_FIFO_SE2A1_3", + "CMT_TOP_SE2A1_3" + ], + [ + "CMT_FIFO_L_IMUX47_10", + "CMT_TOP_IMUX47_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_7", + "CMT_TOP_LOGIC_OUTS_L_B3_7" + ], + [ + "CMT_FIFO_SW2A2_2", + "CMT_TOP_SW2A2_2" + ], + [ + "CMT_FIFO_SW2A3_3", + "CMT_TOP_SW2A3_3" + ], + [ + "CMT_FIFO_EE4A2_10", + "CMT_TOP_EE4A2_10" + ], + [ + "CMT_FIFO_WL1END1_5", + "CMT_TOP_WL1END1_5" + ], + [ + "CMT_FIFO_L_FAN4_1", + "CMT_TOP_FAN4_1" + ], + [ + "CMT_FIFO_L_IMUX21_2", + "CMT_TOP_IMUX21_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_4", + "CMT_TOP_LOGIC_OUTS_L_B12_4" + ], + [ + "CMT_FIFO_LH6_5", + "CMT_TOP_LH6_5" + ], + [ + "CMT_FIFO_L_IMUX43_2", + "CMT_TOP_IMUX43_2" + ], + [ + "CMT_FIFO_WL1END0_8", + "CMT_TOP_WL1END0_8" + ], + [ + "CMT_FIFO_SE2A2_2", + "CMT_TOP_SE2A2_2" + ], + [ + "CMT_FIFO_EL1BEG1_5", + "CMT_TOP_EL1BEG1_5" + ], + [ + "CMT_FIFO_EE4A2_11", + "CMT_TOP_EE4A2_11" + ], + [ + "CMT_FIFO_EE4BEG3_2", + "CMT_TOP_EE4BEG3_2" + ], + [ + "CMT_FIFO_WW4A2_7", + "CMT_TOP_WW4A2_7" + ], + [ + "CMT_FIFO_L_IMUX32_2", + "CMT_TOP_IMUX32_2" + ], + [ + "CMT_FIFO_LH4_8", + "CMT_TOP_LH4_8" + ], + [ + "CMT_FIFO_LH12_5", + "CMT_TOP_LH12_5" + ], + [ + "CMT_FIFO_L_IMUX18_9", + "CMT_TOP_IMUX18_9" + ], + [ + "CMT_FIFO_L_IMUX1_9", + "CMT_TOP_IMUX1_9" + ], + [ + "CMT_FIFO_WW4B0_6", + "CMT_TOP_WW4B0_6" + ], + [ + "CMT_FIFO_L_FAN5_8", + "CMT_TOP_FAN5_8" + ], + [ + "CMT_FIFO_SW4END1_2", + "CMT_TOP_SW4END1_2" + ], + [ + "CMT_FIFO_L_IMUX35_11", + "CMT_TOP_IMUX35_11" + ], + [ + "CMT_FIFO_NW4END1_10", + "CMT_TOP_NW4END1_10" + ], + [ + "CMT_FIFO_WR1END3_11", + "CMT_TOP_WR1END3_11" + ], + [ + "CMT_FIFO_L_IMUX14_2", + "CMT_TOP_IMUX14_2" + ], + [ + "CMT_FIFO_L_IMUX4_7", + "CMT_TOP_IMUX4_7" + ], + [ + "CMT_FIFO_WW4END3_0", + "CMT_TOP_WW4END3_0" + ], + [ + "CMT_FIFO_L_IMUX13_9", + "CMT_TOP_IMUX13_9" + ], + [ + "CMT_FIFO_L_IMUX17_5", + "CMT_TOP_IMUX17_5" + ], + [ + "CMT_FIFO_SE2A0_10", + "CMT_TOP_SE2A0_10" + ], + [ + "CMT_FIFO_L_IMUX26_3", + "CMT_TOP_IMUX26_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "CMT_TOP_ICLKDIV_3" + ], + [ + "CMT_FIFO_NE4C1_9", + "CMT_TOP_NE4C1_9" + ], + [ + "CMT_FIFO_L_BYP4_5", + "CMT_TOP_BYP4_5" + ], + [ + "CMT_FIFO_SW4A0_5", + "CMT_TOP_SW4A0_5" + ], + [ + "CMT_FIFO_L_BYP4_3", + "CMT_TOP_BYP4_3" + ], + [ + "CMT_FIFO_NW2A0_2", + "CMT_TOP_NW2A0_2" + ], + [ + "CMT_FIFO_SW2A1_10", + "CMT_TOP_SW2A1_10" + ], + [ + "CMT_FIFO_EE4C0_8", + "CMT_TOP_EE4C0_8" + ], + [ + "CMT_FIFO_L_BYP0_8", + "CMT_TOP_BYP0_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "CMT_TOP_ICLK_10" + ], + [ + "CMT_FIFO_WL1END2_2", + "CMT_TOP_WL1END2_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "CMT_TOP_OCLK_11" + ], + [ + "CMT_FIFO_L_IMUX12_1", + "CMT_TOP_IMUX12_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_9", + "CMT_TOP_LOGIC_OUTS_L_B7_9" + ], + [ + "CMT_FIFO_L_IMUX41_9", + "CMT_TOP_IMUX41_9" + ], + [ + "CMT_FIFO_L_FAN7_11", + "CMT_TOP_FAN7_11" + ], + [ + "CMT_FIFO_EE2A3_5", + "CMT_TOP_EE2A3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_3", + "CMT_TOP_LOGIC_OUTS_L_B21_3" + ], + [ + "CMT_FIFO_WW4B2_4", + "CMT_TOP_WW4B2_4" + ], + [ + "CMT_FIFO_L_IMUX3_2", + "CMT_TOP_IMUX3_2" + ], + [ + "CMT_FIFO_WR1END0_3", + "CMT_TOP_WR1END0_3" + ], + [ + "CMT_FIFO_SE4BEG0_10", + "CMT_TOP_SE4BEG0_10" + ], + [ + "CMT_FIFO_L_IMUX8_8", + "CMT_TOP_IMUX8_8" + ], + [ + "CMT_FIFO_WW4B3_9", + "CMT_TOP_WW4B3_9" + ], + [ + "CMT_FIFO_L_IMUX11_1", + "CMT_TOP_IMUX11_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_4", + "CMT_TOP_LOGIC_OUTS_L_B5_4" + ], + [ + "CMT_FIFO_LH3_0", + "CMT_TOP_LH3_0" + ], + [ + "CMT_FIFO_WR1END2_7", + "CMT_TOP_WR1END2_7" + ], + [ + "CMT_FIFO_NE2A2_7", + "CMT_TOP_NE2A2_7" + ], + [ + "CMT_FIFO_ER1BEG3_2", + "CMT_TOP_ER1BEG3_2" + ], + [ + "CMT_FIFO_WW2A1_0", + "CMT_TOP_WW2A1_0" + ], + [ + "CMT_FIFO_WL1END0_11", + "CMT_TOP_WL1END0_11" + ], + [ + "CMT_FIFO_NE4BEG1_9", + "CMT_TOP_NE4BEG1_9" + ], + [ + "CMT_FIFO_SW4A3_10", + "CMT_TOP_SW4A3_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_7", + "CMT_TOP_LOGIC_OUTS_L_B12_7" + ], + [ + "CMT_FIFO_WW4B3_1", + "CMT_TOP_WW4B3_1" + ], + [ + "CMT_FIFO_NW4END0_5", + "CMT_TOP_NW4END0_5" + ], + [ + "CMT_FIFO_L_BYP7_5", + "CMT_TOP_BYP7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_8", + "CMT_TOP_LOGIC_OUTS_L_B16_8" + ], + [ + "CMT_FIFO_SE4C1_6", + "CMT_TOP_SE4C1_6" + ], + [ + "CMT_FIFO_WW4B2_3", + "CMT_TOP_WW4B2_3" + ], + [ + "CMT_FIFO_L_IMUX3_1", + "CMT_TOP_IMUX3_1" + ], + [ + "CMT_FIFO_L_FAN4_5", + "CMT_TOP_FAN4_5" + ], + [ + "CMT_FIFO_L_IMUX32_8", + "CMT_TOP_IMUX32_8" + ], + [ + "CMT_FIFO_L_IMUX36_7", + "CMT_TOP_IMUX36_7" + ], + [ + "CMT_FIFO_EE4A0_8", + "CMT_TOP_EE4A0_8" + ], + [ + "CMT_FIFO_EE4C0_11", + "CMT_TOP_EE4C0_11" + ], + [ + "CMT_FIFO_NW2A0_5", + "CMT_TOP_NW2A0_5" + ], + [ + "CMT_FIFO_L_CLK0_10", + "CMT_TOP_CLK0_10" + ], + [ + "CMT_FIFO_EE4B3_5", + "CMT_TOP_EE4B3_5" + ], + [ + "CMT_FIFO_EE4BEG0_6", + "CMT_TOP_EE4BEG0_6" + ], + [ + "CMT_FIFO_L_IMUX1_0", + "CMT_TOP_IMUX1_0" + ], + [ + "CMT_FIFO_L_IMUX12_11", + "CMT_TOP_IMUX12_11" + ], + [ + "CMT_FIFO_L_IMUX14_8", + "CMT_TOP_IMUX14_8" + ], + [ + "CMT_FIFO_NW4A1_3", + "CMT_TOP_NW4A1_3" + ], + [ + "CMT_FIFO_L_IMUX17_11", + "CMT_TOP_IMUX17_11" + ], + [ + "CMT_FIFO_SE4BEG1_8", + "CMT_TOP_SE4BEG1_8" + ], + [ + "CMT_FIFO_L_IMUX5_10", + "CMT_TOP_IMUX5_10" + ], + [ + "CMT_FIFO_NE2A3_2", + "CMT_TOP_NE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX0_4", + "CMT_TOP_IMUX0_4" + ], + [ + "CMT_FIFO_NE4C3_2", + "CMT_TOP_NE4C3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_8", + "CMT_TOP_LOGIC_OUTS_L_B2_8" + ], + [ + "CMT_FIFO_LH4_6", + "CMT_TOP_LH4_6" + ], + [ + "CMT_FIFO_L_IMUX27_5", + "CMT_TOP_IMUX27_5" + ], + [ + "CMT_FIFO_LH5_0", + "CMT_TOP_LH5_0" + ], + [ + "CMT_FIFO_EE4B3_10", + "CMT_TOP_EE4B3_10" + ], + [ + "CMT_FIFO_NW4A3_8", + "CMT_TOP_NW4A3_8" + ], + [ + "CMT_FIFO_L_BYP0_3", + "CMT_TOP_BYP0_3" + ], + [ + "CMT_FIFO_L_IMUX24_8", + "CMT_TOP_IMUX24_8" + ], + [ + "CMT_FIFO_L_IMUX30_3", + "CMT_TOP_IMUX30_3" + ], + [ + "CMT_FIFO_L_FAN7_9", + "CMT_TOP_FAN7_9" + ], + [ + "CMT_FIFO_EE4B2_6", + "CMT_TOP_EE4B2_6" + ], + [ + "CMT_FIFO_L_IMUX14_4", + "CMT_TOP_IMUX14_4" + ], + [ + "CMT_FIFO_LH10_6", + "CMT_TOP_LH10_6" + ], + [ + "CMT_FIFO_WW4A0_2", + "CMT_TOP_WW4A0_2" + ], + [ + "CMT_FIFO_L_BYP0_10", + "CMT_TOP_BYP0_10" + ], + [ + "CMT_FIFO_L_IMUX36_2", + "CMT_TOP_IMUX36_2" + ], + [ + "CMT_FIFO_L_IMUX13_7", + "CMT_TOP_IMUX13_7" + ], + [ + "CMT_FIFO_SE2A1_11", + "CMT_TOP_SE2A1_11" + ], + [ + "CMT_FIFO_L_CTRL0_8", + "CMT_TOP_CTRL0_8" + ], + [ + "CMT_FIFO_SE4C2_1", + "CMT_TOP_SE4C2_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_7", + "CMT_TOP_LOGIC_OUTS_L_B17_7" + ], + [ + "CMT_FIFO_L_IMUX5_2", + "CMT_TOP_IMUX5_2" + ], + [ + "CMT_FIFO_EE4BEG0_5", + "CMT_TOP_EE4BEG0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_0", + "CMT_TOP_LOGIC_OUTS_L_B7_0" + ], + [ + "CMT_FIFO_EE4B0_2", + "CMT_TOP_EE4B0_2" + ], + [ + "CMT_FIFO_L_BYP4_1", + "CMT_TOP_BYP4_1" + ], + [ + "CMT_FIFO_L_FAN1_7", + "CMT_TOP_FAN1_7" + ], + [ + "CMT_FIFO_L_IMUX28_6", + "CMT_TOP_IMUX28_6" + ], + [ + "CMT_FIFO_NE2A2_4", + "CMT_TOP_NE2A2_4" + ], + [ + "CMT_FIFO_WW2A1_9", + "CMT_TOP_WW2A1_9" + ], + [ + "CMT_FIFO_L_FAN1_6", + "CMT_TOP_FAN1_6" + ], + [ + "CMT_FIFO_L_IMUX13_5", + "CMT_TOP_IMUX13_5" + ], + [ + "CMT_FIFO_L_IMUX27_2", + "CMT_TOP_IMUX27_2" + ], + [ + "CMT_FIFO_L_IMUX8_4", + "CMT_TOP_IMUX8_4" + ], + [ + "CMT_FIFO_NE4C0_0", + "CMT_TOP_NE4C0_0" + ], + [ + "CMT_FIFO_NW4END1_11", + "CMT_TOP_NW4END1_11" + ], + [ + "CMT_FIFO_LH8_1", + "CMT_TOP_LH8_1" + ], + [ + "CMT_FIFO_L_IMUX30_7", + "CMT_TOP_IMUX30_7" + ], + [ + "CMT_FIFO_WW2A0_5", + "CMT_TOP_WW2A0_5" + ], + [ + "CMT_FIFO_LH6_4", + "CMT_TOP_LH6_4" + ], + [ + "CMT_FIFO_L_IMUX14_7", + "CMT_TOP_IMUX14_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_2", + "CMT_TOP_LOGIC_OUTS_L_B16_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_10", + "CMT_TOP_LOGIC_OUTS_L_B17_10" + ], + [ + "CMT_FIFO_L_IMUX11_6", + "CMT_TOP_IMUX11_6" + ], + [ + "CMT_FIFO_L_CLK1_9", + "CMT_TOP_CLK1_9" + ], + [ + "CMT_FIFO_L_IMUX13_1", + "CMT_TOP_IMUX13_1" + ], + [ + "CMT_FIFO_SE4C1_7", + "CMT_TOP_SE4C1_7" + ], + [ + "CMT_FIFO_LH9_6", + "CMT_TOP_LH9_6" + ], + [ + "CMT_FIFO_L_IMUX24_7", + "CMT_TOP_IMUX24_7" + ], + [ + "CMT_FIFO_L_IMUX41_10", + "CMT_TOP_IMUX41_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_4", + "CMT_TOP_LOGIC_OUTS_L_B11_4" + ], + [ + "CMT_FIFO_LH3_9", + "CMT_TOP_LH3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_9", + "CMT_TOP_LOGIC_OUTS_L_B20_9" + ], + [ + "CMT_FIFO_L_IMUX20_5", + "CMT_TOP_IMUX20_5" + ], + [ + "CMT_FIFO_EE4A2_6", + "CMT_TOP_EE4A2_6" + ], + [ + "CMT_FIFO_WR1END2_5", + "CMT_TOP_WR1END2_5" + ], + [ + "CMT_FIFO_LH1_7", + "CMT_TOP_LH1_7" + ], + [ + "CMT_FIFO_L_IMUX34_5", + "CMT_TOP_IMUX34_5" + ], + [ + "CMT_FIFO_EE4A0_4", + "CMT_TOP_EE4A0_4" + ], + [ + "CMT_FIFO_L_IMUX26_8", + "CMT_TOP_IMUX26_8" + ], + [ + "CMT_FIFO_LH8_8", + "CMT_TOP_LH8_8" + ], + [ + "CMT_FIFO_LH11_3", + "CMT_TOP_LH11_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_4", + "CMT_TOP_LOGIC_OUTS_L_B14_4" + ], + [ + "CMT_FIFO_EE2BEG0_4", + "CMT_TOP_EE2BEG0_4" + ], + [ + "CMT_FIFO_L_IMUX39_6", + "CMT_TOP_IMUX39_6" + ], + [ + "CMT_FIFO_WW4C1_5", + "CMT_TOP_WW4C1_5" + ], + [ + "CMT_FIFO_WW4END1_7", + "CMT_TOP_WW4END1_7" + ], + [ + "CMT_FIFO_L_BYP2_5", + "CMT_TOP_BYP2_5" + ], + [ + "CMT_FIFO_MONITOR_P_4", + "CMT_TOP_MONITOR_P_4" + ], + [ + "CMT_FIFO_L_IMUX4_1", + "CMT_TOP_IMUX4_1" + ], + [ + "CMT_FIFO_NW4END3_0", + "CMT_TOP_NW4END3_0" + ], + [ + "CMT_FIFO_ER1BEG3_10", + "CMT_TOP_ER1BEG3_10" + ], + [ + "CMT_FIFO_L_IMUX12_5", + "CMT_TOP_IMUX12_5" + ], + [ + "CMT_FIFO_L_IMUX1_2", + "CMT_TOP_IMUX1_2" + ], + [ + "CMT_FIFO_L_IMUX7_11", + "CMT_TOP_IMUX7_11" + ], + [ + "CMT_FIFO_L_IMUX28_11", + "CMT_TOP_IMUX28_11" + ], + [ + "CMT_FIFO_L_IMUX9_2", + "CMT_TOP_IMUX9_2" + ], + [ + "CMT_FIFO_L_BYP3_11", + "CMT_TOP_BYP3_11" + ], + [ + "CMT_FIFO_NW4A3_1", + "CMT_TOP_NW4A3_1" + ], + [ + "CMT_FIFO_L_CTRL1_2", + "CMT_TOP_CTRL1_2" + ], + [ + "CMT_FIFO_LH12_0", + "CMT_TOP_LH12_0" + ], + [ + "CMT_FIFO_L_IMUX23_5", + "CMT_TOP_IMUX23_5" + ], + [ + "CMT_FIFO_LH12_3", + "CMT_TOP_LH12_3" + ], + [ + "CMT_FIFO_L_IMUX16_4", + "CMT_TOP_IMUX16_4" + ], + [ + "CMT_FIFO_WR1END1_10", + "CMT_TOP_WR1END1_10" + ], + [ + "CMT_FIFO_L_IMUX11_4", + "CMT_TOP_IMUX11_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_3", + "CMT_TOP_LOGIC_OUTS_L_B20_3" + ], + [ + "CMT_FIFO_L_IMUX13_8", + "CMT_TOP_IMUX13_8" + ], + [ + "CMT_FIFO_L_IMUX34_7", + "CMT_TOP_IMUX34_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_10", + "CMT_TOP_LOGIC_OUTS_L_B5_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_7", + "CMT_TOP_LOGIC_OUTS_L_B10_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_2", + "CMT_TOP_LOGIC_OUTS_L_B15_2" + ], + [ + "CMT_FIFO_L_IMUX10_4", + "CMT_TOP_IMUX10_4" + ], + [ + "CMT_FIFO_L_IMUX34_4", + "CMT_TOP_IMUX34_4" + ], + [ + "CMT_FIFO_NW4A2_5", + "CMT_TOP_NW4A2_5" + ], + [ + "CMT_FIFO_L_IMUX27_6", + "CMT_TOP_IMUX27_6" + ], + [ + "CMT_FIFO_L_IMUX42_8", + "CMT_TOP_IMUX42_8" + ], + [ + "CMT_FIFO_L_IMUX31_1", + "CMT_TOP_IMUX31_1" + ], + [ + "CMT_FIFO_WW4END2_0", + "CMT_TOP_WW4END2_0" + ], + [ + "CMT_FIFO_SW4A0_10", + "CMT_TOP_SW4A0_10" + ], + [ + "CMT_FIFO_LH12_11", + "CMT_TOP_LH12_11" + ], + [ + "CMT_FIFO_NW4END2_4", + "CMT_TOP_NW4END2_4" + ], + [ + "CMT_FIFO_SE2A2_0", + "CMT_TOP_SE2A2_0" + ], + [ + "CMT_FIFO_SE2A3_5", + "CMT_TOP_SE2A3_5" + ], + [ + "CMT_FIFO_L_IMUX7_5", + "CMT_TOP_IMUX7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_7", + "CMT_TOP_LOGIC_OUTS_L_B9_7" + ], + [ + "CMT_FIFO_L_FAN3_6", + "CMT_TOP_FAN3_6" + ], + [ + "CMT_FIFO_EE4A2_2", + "CMT_TOP_EE4A2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_2", + "CMT_TOP_LOGIC_OUTS_L_B17_2" + ], + [ + "CMT_FIFO_L_IMUX22_10", + "CMT_TOP_IMUX22_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_9", + "CMT_TOP_LOGIC_OUTS_L_B22_9" + ], + [ + "CMT_FIFO_L_IMUX4_10", + "CMT_TOP_IMUX4_10" + ], + [ + "CMT_FIFO_L_BYP7_3", + "CMT_TOP_BYP7_3" + ], + [ + "CMT_FIFO_NE4BEG3_6", + "CMT_TOP_NE4BEG3_6" + ], + [ + "CMT_FIFO_L_CTRL0_10", + "CMT_TOP_CTRL0_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_5", + "CMT_TOP_LOGIC_OUTS_L_B13_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_11", + "CMT_TOP_LOGIC_OUTS_L_B19_11" + ], + [ + "CMT_FIFO_L_IMUX41_8", + "CMT_TOP_IMUX41_8" + ], + [ + "CMT_FIFO_SE2A1_0", + "CMT_TOP_SE2A1_0" + ], + [ + "CMT_FIFO_SW4END2_11", + "CMT_TOP_SW4END2_11" + ], + [ + "CMT_FIFO_WL1END0_3", + "CMT_TOP_WL1END0_3" + ], + [ + "CMT_FIFO_L_IMUX37_5", + "CMT_TOP_IMUX37_5" + ], + [ + "CMT_FIFO_LH12_8", + "CMT_TOP_LH12_8" + ], + [ + "CMT_FIFO_SW4END3_3", + "CMT_TOP_SW4END3_3" + ], + [ + "CMT_FIFO_NW4A1_5", + "CMT_TOP_NW4A1_5" + ], + [ + "CMT_FIFO_WW4END3_5", + "CMT_TOP_WW4END3_5" + ], + [ + "CMT_FIFO_L_BYP7_4", + "CMT_TOP_BYP7_4" + ], + [ + "CMT_FIFO_L_IMUX10_0", + "CMT_TOP_IMUX10_0" + ], + [ + "CMT_FIFO_EE4BEG0_2", + "CMT_TOP_EE4BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX33_0", + "CMT_TOP_IMUX33_0" + ], + [ + "CMT_FIFO_EL1BEG0_7", + "CMT_TOP_EL1BEG0_7" + ], + [ + "CMT_FIFO_SE2A2_5", + "CMT_TOP_SE2A2_5" + ], + [ + "CMT_FIFO_ER1BEG2_0", + "CMT_TOP_ER1BEG2_0" + ], + [ + "CMT_FIFO_L_CLK0_11", + "CMT_TOP_CLK0_11" + ], + [ + "CMT_FIFO_L_IMUX13_4", + "CMT_TOP_IMUX13_4" + ], + [ + "CMT_FIFO_L_BYP5_9", + "CMT_TOP_BYP5_9" + ], + [ + "CMT_FIFO_LH10_2", + "CMT_TOP_LH10_2" + ], + [ + "CMT_FIFO_L_IMUX33_4", + "CMT_TOP_IMUX33_4" + ], + [ + "CMT_FIFO_SW4END0_8", + "CMT_TOP_SW4END0_8" + ], + [ + "CMT_FIFO_L_IMUX11_11", + "CMT_TOP_IMUX11_11" + ], + [ + "CMT_FIFO_SW4END0_1", + "CMT_TOP_SW4END0_1" + ], + [ + "CMT_FIFO_L_IMUX14_0", + "CMT_TOP_IMUX14_0" + ], + [ + "CMT_FIFO_NW4END3_11", + "CMT_TOP_NW4END3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_6", + "CMT_TOP_LOGIC_OUTS_L_B21_6" + ], + [ + "CMT_FIFO_L_FAN7_8", + "CMT_TOP_FAN7_8" + ], + [ + "CMT_FIFO_EE4BEG1_7", + "CMT_TOP_EE4BEG1_7" + ], + [ + "CMT_FIFO_L_BYP3_7", + "CMT_TOP_BYP3_7" + ], + [ + "CMT_FIFO_L_IMUX26_0", + "CMT_TOP_IMUX26_0" + ], + [ + "CMT_FIFO_LH8_5", + "CMT_TOP_LH8_5" + ], + [ + "CMT_FIFO_WL1END0_7", + "CMT_TOP_WL1END0_7" + ], + [ + "CMT_FIFO_L_IMUX11_9", + "CMT_TOP_IMUX11_9" + ], + [ + "CMT_FIFO_WR1END0_4", + "CMT_TOP_WR1END0_4" + ], + [ + "CMT_FIFO_L_IMUX36_10", + "CMT_TOP_IMUX36_10" + ], + [ + "CMT_FIFO_EL1BEG1_1", + "CMT_TOP_EL1BEG1_1" + ], + [ + "CMT_FIFO_SE4C1_10", + "CMT_TOP_SE4C1_10" + ], + [ + "CMT_FIFO_NW4END0_10", + "CMT_TOP_NW4END0_10" + ], + [ + "CMT_FIFO_WW2END0_9", + "CMT_TOP_WW2END0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_6", + "CMT_TOP_LOGIC_OUTS_L_B1_6" + ], + [ + "CMT_FIFO_ER1BEG2_2", + "CMT_TOP_ER1BEG2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_9", + "CMT_TOP_LOGIC_OUTS_L_B19_9" + ], + [ + "CMT_FIFO_NE4C0_9", + "CMT_TOP_NE4C0_9" + ], + [ + "CMT_FIFO_SE2A0_4", + "CMT_TOP_SE2A0_4" + ], + [ + "CMT_FIFO_WW2A3_9", + "CMT_TOP_WW2A3_9" + ], + [ + "CMT_FIFO_L_IMUX21_9", + "CMT_TOP_IMUX21_9" + ], + [ + "CMT_FIFO_NE2A3_5", + "CMT_TOP_NE2A3_5" + ], + [ + "CMT_FIFO_NW2A0_7", + "CMT_TOP_NW2A0_7" + ], + [ + "CMT_FIFO_L_IMUX40_10", + "CMT_TOP_IMUX40_10" + ], + [ + "CMT_FIFO_L_IMUX6_9", + "CMT_TOP_IMUX6_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_4", + "CMT_TOP_LOGIC_OUTS_L_B8_4" + ], + [ + "CMT_FIFO_ER1BEG1_5", + "CMT_TOP_ER1BEG1_5" + ], + [ + "CMT_FIFO_WW4A2_1", + "CMT_TOP_WW4A2_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "CMT_TOP_OCLKDIV_6" + ], + [ + "CMT_FIFO_LH3_5", + "CMT_TOP_LH3_5" + ], + [ + "CMT_FIFO_SW4END0_9", + "CMT_TOP_SW4END0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_4", + "CMT_TOP_LOGIC_OUTS_L_B16_4" + ], + [ + "CMT_FIFO_SE4BEG0_9", + "CMT_TOP_SE4BEG0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_3", + "CMT_TOP_LOGIC_OUTS_L_B9_3" + ], + [ + "CMT_FIFO_ER1BEG1_1", + "CMT_TOP_ER1BEG1_1" + ], + [ + "CMT_FIFO_EE2A2_0", + "CMT_TOP_EE2A2_0" + ], + [ + "CMT_FIFO_L_IMUX40_2", + "CMT_TOP_IMUX40_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_2", + "CMT_TOP_LOGIC_OUTS_L_B13_2" + ], + [ + "CMT_FIFO_L_IMUX22_9", + "CMT_TOP_IMUX22_9" + ], + [ + "CMT_FIFO_LH9_11", + "CMT_TOP_LH9_11" + ], + [ + "CMT_FIFO_WL1END3_3", + "CMT_TOP_WL1END3_3" + ], + [ + "CMT_FIFO_EE2A1_9", + "CMT_TOP_EE2A1_9" + ], + [ + "CMT_FIFO_LH4_9", + "CMT_TOP_LH4_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_3", + "CMT_TOP_LOGIC_OUTS_L_B12_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_9", + "CMT_TOP_LOGIC_OUTS_L_B21_9" + ], + [ + "CMT_FIFO_NW4END0_3", + "CMT_TOP_NW4END0_3" + ], + [ + "CMT_FIFO_SW4A3_1", + "CMT_TOP_SW4A3_1" + ], + [ + "CMT_FIFO_SW4END2_10", + "CMT_TOP_SW4END2_10" + ], + [ + "CMT_FIFO_SW4END0_7", + "CMT_TOP_SW4END0_7" + ], + [ + "CMT_FIFO_L_IMUX11_5", + "CMT_TOP_IMUX11_5" + ], + [ + "CMT_FIFO_ER1BEG3_7", + "CMT_TOP_ER1BEG3_7" + ], + [ + "CMT_FIFO_EE2BEG2_9", + "CMT_TOP_EE2BEG2_9" + ], + [ + "CMT_FIFO_EE4C0_10", + "CMT_TOP_EE4C0_10" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "CMT_TOP_R_UPPER_B" + ] + }, + { + "grid_deltas": [ + 1, + -8 + ], + "wire_pairs": [ + [ + "MONITOR_NE4BEG0_8", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_IMUX20_8", + "VFRAME_IMUX20" + ], + [ + "MONITOR_WW4A2_8", + "VFRAME_WW4A2" + ], + [ + "MONITOR_WR1END3_8", + "VFRAME_WR1END3" + ], + [ + "MONITOR_FAN0_8", + "VFRAME_FAN0" + ], + [ + "MONITOR_ER1BEG0_8", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_IMUX25_8", + "VFRAME_IMUX25" + ], + [ + "MONITOR_EE2BEG2_8", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_IMUX42_8", + "VFRAME_IMUX42" + ], + [ + "MONITOR_WW4B1_8", + "VFRAME_WW4B1" + ], + [ + "MONITOR_SW2A2_8", + "VFRAME_SW2A2" + ], + [ + "MONITOR_WW4C0_8", + "VFRAME_WW4C0" + ], + [ + "MONITOR_EE2A3_8", + "VFRAME_EE2A3" + ], + [ + "MONITOR_EE4B3_8", + "VFRAME_EE4B3" + ], + [ + "MONITOR_EE2A0_8", + "VFRAME_EE2A0" + ], + [ + "MONITOR_IMUX44_8", + "VFRAME_IMUX44" + ], + [ + "MONITOR_LH1_8", + "VFRAME_LH1" + ], + [ + "MONITOR_WL1END1_8", + "VFRAME_WL1END1" + ], + [ + "MONITOR_SW2A0_8", + "VFRAME_SW2A0" + ], + [ + "MONITOR_IMUX15_8", + "VFRAME_IMUX15" + ], + [ + "MONITOR_IMUX46_8", + "VFRAME_IMUX46" + ], + [ + "MONITOR_IMUX34_8", + "VFRAME_IMUX34" + ], + [ + "MONITOR_SE4BEG1_8", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_FAN6_8", + "VFRAME_FAN6" + ], + [ + "MONITOR_IMUX16_8", + "VFRAME_IMUX16" + ], + [ + "MONITOR_IMUX1_8", + "VFRAME_IMUX1" + ], + [ + "MONITOR_CTRL1_8", + "VFRAME_CTRL1" + ], + [ + "MONITOR_FAN2_8", + "VFRAME_FAN2" + ], + [ + "MONITOR_IMUX12_8", + "VFRAME_IMUX12" + ], + [ + "MONITOR_BYP0_8", + "VFRAME_BYP0" + ], + [ + "MONITOR_IMUX4_8", + "VFRAME_IMUX4" + ], + [ + "MONITOR_EE4BEG3_8", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_WR1END2_8", + "VFRAME_WR1END2" + ], + [ + "MONITOR_NE2A1_8", + "VFRAME_NE2A1" + ], + [ + "MONITOR_WW2END3_8", + "VFRAME_WW2END3" + ], + [ + "MONITOR_NE4C1_8", + "VFRAME_NE4C1" + ], + [ + "MONITOR_SE2A0_8", + "VFRAME_SE2A0" + ], + [ + "MONITOR_BYP4_8", + "VFRAME_BYP4" + ], + [ + "MONITOR_IMUX37_8", + "VFRAME_IMUX37" + ], + [ + "MONITOR_SE4C2_8", + "VFRAME_SE4C2" + ], + [ + "MONITOR_EE4A3_8", + "VFRAME_EE4A3" + ], + [ + "MONITOR_IMUX8_8", + "VFRAME_IMUX8" + ], + [ + "MONITOR_NW2A3_8", + "VFRAME_NW2A3" + ], + [ + "MONITOR_NW4END0_8", + "VFRAME_NW4END0" + ], + [ + "MONITOR_EE4A0_8", + "VFRAME_EE4A0" + ], + [ + "MONITOR_WW2A0_8", + "VFRAME_WW2A0" + ], + [ + "MONITOR_FAN7_8", + "VFRAME_FAN7" + ], + [ + "MONITOR_BYP1_8", + "VFRAME_BYP1" + ], + [ + "MONITOR_NE4C0_8", + "VFRAME_NE4C0" + ], + [ + "MONITOR_ER1BEG1_8", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_EL1BEG0_8", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_EE2A1_8", + "VFRAME_EE2A1" + ], + [ + "MONITOR_SW4A2_8", + "VFRAME_SW4A2" + ], + [ + "MONITOR_EE4B2_8", + "VFRAME_EE4B2" + ], + [ + "MONITOR_IMUX9_8", + "VFRAME_IMUX9" + ], + [ + "MONITOR_IMUX38_8", + "VFRAME_IMUX38" + ], + [ + "MONITOR_IMUX32_8", + "VFRAME_IMUX32" + ], + [ + "MONITOR_WW4END1_8", + "VFRAME_WW4END1" + ], + [ + "MONITOR_IMUX33_8", + "VFRAME_IMUX33" + ], + [ + "MONITOR_EE2BEG1_8", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_LH2_8", + "VFRAME_LH2" + ], + [ + "MONITOR_IMUX6_8", + "VFRAME_IMUX6" + ], + [ + "MONITOR_SE4BEG0_8", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_IMUX22_8", + "VFRAME_IMUX22" + ], + [ + "MONITOR_NE4BEG3_8", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_EE4B1_8", + "VFRAME_EE4B1" + ], + [ + "MONITOR_EE4C3_8", + "VFRAME_EE4C3" + ], + [ + "MONITOR_IMUX2_8", + "VFRAME_IMUX2" + ], + [ + "MONITOR_IMUX40_8", + "VFRAME_IMUX40" + ], + [ + "MONITOR_IMUX45_8", + "VFRAME_IMUX45" + ], + [ + "MONITOR_SW2A3_8", + "VFRAME_SW2A3" + ], + [ + "MONITOR_WL1END0_8", + "VFRAME_WL1END0" + ], + [ + "MONITOR_NW2A0_8", + "VFRAME_NW2A0" + ], + [ + "MONITOR_LH5_8", + "VFRAME_LH5" + ], + [ + "MONITOR_EL1BEG1_8", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_CTRL0_8", + "VFRAME_CTRL0" + ], + [ + "MONITOR_NW4END1_8", + "VFRAME_NW4END1" + ], + [ + "MONITOR_SE4C0_8", + "VFRAME_SE4C0" + ], + [ + "MONITOR_SE4BEG2_8", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_IMUX35_8", + "VFRAME_IMUX35" + ], + [ + "MONITOR_ER1BEG2_8", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_WW4END2_8", + "VFRAME_WW4END2" + ], + [ + "MONITOR_CLK1_8", + "VFRAME_CLK1" + ], + [ + "MONITOR_NE2A3_8", + "VFRAME_NE2A3" + ], + [ + "MONITOR_EE4BEG2_8", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_IMUX41_8", + "VFRAME_IMUX41" + ], + [ + "MONITOR_NE4C2_8", + "VFRAME_NE4C2" + ], + [ + "MONITOR_NE4BEG2_8", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_WW4C3_8", + "VFRAME_WW4C3" + ], + [ + "MONITOR_WL1END2_8", + "VFRAME_WL1END2" + ], + [ + "MONITOR_EL1BEG2_8", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_IMUX3_8", + "VFRAME_IMUX3" + ], + [ + "MONITOR_WW4B2_8", + "VFRAME_WW4B2" + ], + [ + "MONITOR_LH6_8", + "VFRAME_LH6" + ], + [ + "MONITOR_SE2A2_8", + "VFRAME_SE2A2" + ], + [ + "MONITOR_EE2BEG0_8", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_IMUX28_8", + "VFRAME_IMUX28" + ], + [ + "MONITOR_IMUX21_8", + "VFRAME_IMUX21" + ], + [ + "MONITOR_WW2END1_8", + "VFRAME_WW2END1" + ], + [ + "MONITOR_WW4B0_8", + "VFRAME_WW4B0" + ], + [ + "MONITOR_NE4BEG1_8", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_IMUX14_8", + "VFRAME_IMUX14" + ], + [ + "MONITOR_LH4_8", + "VFRAME_LH4" + ], + [ + "MONITOR_WW2END2_8", + "VFRAME_WW2END2" + ], + [ + "MONITOR_BYP5_8", + "VFRAME_BYP5" + ], + [ + "MONITOR_SW2A1_8", + "VFRAME_SW2A1" + ], + [ + "MONITOR_EE4B0_8", + "VFRAME_EE4B0" + ], + [ + "MONITOR_SE4BEG3_8", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_FAN1_8", + "VFRAME_FAN1" + ], + [ + "MONITOR_IMUX31_8", + "VFRAME_IMUX31" + ], + [ + "MONITOR_SE2A3_8", + "VFRAME_SE2A3" + ], + [ + "MONITOR_EE2BEG3_8", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_SE2A1_8", + "VFRAME_SE2A1" + ], + [ + "MONITOR_IMUX7_8", + "VFRAME_IMUX7" + ], + [ + "MONITOR_LH9_8", + "VFRAME_LH9" + ], + [ + "MONITOR_SW4END3_8", + "VFRAME_SW4END3" + ], + [ + "MONITOR_IMUX13_8", + "VFRAME_IMUX13" + ], + [ + "MONITOR_IMUX47_8", + "VFRAME_IMUX47" + ], + [ + "MONITOR_WW4B3_8", + "VFRAME_WW4B3" + ], + [ + "MONITOR_WW2A3_8", + "VFRAME_WW2A3" + ], + [ + "MONITOR_FAN5_8", + "VFRAME_FAN5" + ], + [ + "MONITOR_SE4C1_8", + "VFRAME_SE4C1" + ], + [ + "MONITOR_EE2A2_8", + "VFRAME_EE2A2" + ], + [ + "MONITOR_EE4C0_8", + "VFRAME_EE4C0" + ], + [ + "MONITOR_EE4BEG0_8", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_IMUX24_8", + "VFRAME_IMUX24" + ], + [ + "MONITOR_NW4END2_8", + "VFRAME_NW4END2" + ], + [ + "MONITOR_IMUX10_8", + "VFRAME_IMUX10" + ], + [ + "MONITOR_WW4END0_8", + "VFRAME_WW4END0" + ], + [ + "MONITOR_NW4END3_8", + "VFRAME_NW4END3" + ], + [ + "MONITOR_EL1BEG3_8", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_SW4END0_8", + "VFRAME_SW4END0" + ], + [ + "MONITOR_WW2A2_8", + "VFRAME_WW2A2" + ], + [ + "MONITOR_NW4A1_8", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WW4END3_8", + "VFRAME_WW4END3" + ], + [ + "MONITOR_SW4END1_8", + "VFRAME_SW4END1" + ], + [ + "MONITOR_LH10_8", + "VFRAME_LH10" + ], + [ + "MONITOR_WL1END3_8", + "VFRAME_WL1END3" + ], + [ + "MONITOR_BYP7_8", + "VFRAME_BYP7" + ], + [ + "MONITOR_CLK0_8", + "VFRAME_CLK0" + ], + [ + "MONITOR_WW4C2_8", + "VFRAME_WW4C2" + ], + [ + "MONITOR_WW4C1_8", + "VFRAME_WW4C1" + ], + [ + "MONITOR_SW4END2_8", + "VFRAME_SW4END2" + ], + [ + "MONITOR_NW2A1_8", + "VFRAME_NW2A1" + ], + [ + "MONITOR_IMUX26_8", + "VFRAME_IMUX26" + ], + [ + "MONITOR_FAN3_8", + "VFRAME_FAN3" + ], + [ + "MONITOR_WW4A3_8", + "VFRAME_WW4A3" + ], + [ + "MONITOR_BYP3_8", + "VFRAME_BYP3" + ], + [ + "MONITOR_LH11_8", + "VFRAME_LH11" + ], + [ + "MONITOR_IMUX29_8", + "VFRAME_IMUX29" + ], + [ + "MONITOR_ER1BEG3_8", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_LH3_8", + "VFRAME_LH3" + ], + [ + "MONITOR_NW4A2_8", + "VFRAME_NW4A2" + ], + [ + "MONITOR_BYP6_8", + "VFRAME_BYP6" + ], + [ + "MONITOR_IMUX39_8", + "VFRAME_IMUX39" + ], + [ + "MONITOR_IMUX17_8", + "VFRAME_IMUX17" + ], + [ + "MONITOR_NW4A3_8", + "VFRAME_NW4A3" + ], + [ + "MONITOR_WR1END1_8", + "VFRAME_WR1END1" + ], + [ + "MONITOR_EE4BEG1_8", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX30_8", + "VFRAME_IMUX30" + ], + [ + "MONITOR_FAN4_8", + "VFRAME_FAN4" + ], + [ + "MONITOR_WW2A1_8", + "VFRAME_WW2A1" + ], + [ + "MONITOR_SW4A1_8", + "VFRAME_SW4A1" + ], + [ + "MONITOR_LH8_8", + "VFRAME_LH8" + ], + [ + "MONITOR_LH12_8", + "VFRAME_LH12" + ], + [ + "MONITOR_LH7_8", + "VFRAME_LH7" + ], + [ + "MONITOR_IMUX19_8", + "VFRAME_IMUX19" + ], + [ + "MONITOR_IMUX11_8", + "VFRAME_IMUX11" + ], + [ + "MONITOR_IMUX5_8", + "VFRAME_IMUX5" + ], + [ + "MONITOR_NE2A2_8", + "VFRAME_NE2A2" + ], + [ + "MONITOR_IMUX36_8", + "VFRAME_IMUX36" + ], + [ + "MONITOR_WW2END0_8", + "VFRAME_WW2END0" + ], + [ + "MONITOR_WR1END0_8", + "VFRAME_WR1END0" + ], + [ + "MONITOR_NW2A2_8", + "VFRAME_NW2A2" + ], + [ + "MONITOR_NE4C3_8", + "VFRAME_NE4C3" + ], + [ + "MONITOR_SW4A0_8", + "VFRAME_SW4A0" + ], + [ + "MONITOR_IMUX43_8", + "VFRAME_IMUX43" + ], + [ + "MONITOR_NW4A0_8", + "VFRAME_NW4A0" + ], + [ + "MONITOR_EE4A1_8", + "VFRAME_EE4A1" + ], + [ + "MONITOR_SE4C3_8", + "VFRAME_SE4C3" + ], + [ + "MONITOR_NE2A0_8", + "VFRAME_NE2A0" + ], + [ + "MONITOR_IMUX0_8", + "VFRAME_IMUX0" + ], + [ + "MONITOR_WW4A0_8", + "VFRAME_WW4A0" + ], + [ + "MONITOR_IMUX23_8", + "VFRAME_IMUX23" + ], + [ + "MONITOR_EE4A2_8", + "VFRAME_EE4A2" + ], + [ + "MONITOR_IMUX18_8", + "VFRAME_IMUX18" + ], + [ + "MONITOR_BYP2_8", + "VFRAME_BYP2" + ], + [ + "MONITOR_SW4A3_8", + "VFRAME_SW4A3" + ], + [ + "MONITOR_EE4C1_8", + "VFRAME_EE4C1" + ], + [ + "MONITOR_EE4C2_8", + "VFRAME_EE4C2" + ], + [ + "MONITOR_IMUX27_8", + "VFRAME_IMUX27" + ], + [ + "MONITOR_WW4A1_8", + "VFRAME_WW4A1" + ] + ], + "tile_types": [ + "MONITOR_MID_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 6 + ], + "wire_pairs": [ + [ + "CFG_CENTER_IMUX2_4", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_SE4BEG2_4", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_WW2A2_4", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_CTRL0_4", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX28_4", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_EL1BEG3_4", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_EE4A0_4", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_LH4_4", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_IMUX26_4", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_BYP5_4", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_WW4C2_4", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX21_4", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_SW2A2_4", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_IMUX17_4", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX1_4", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_SE4BEG3_4", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_SW4A0_4", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_EE4A1_4", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_EE4BEG2_4", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX39_4", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_IMUX4_4", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX40_4", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_EE2BEG2_4", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_SW4A1_4", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_LH9_4", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EE2A3_4", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NW4A3_4", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_IMUX6_4", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_NE4C2_4", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_SE4BEG1_4", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE4B0_4", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_NE2A1_4", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_EE4C3_4", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_NE2A0_4", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_SW2A3_4", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_IMUX35_4", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_FAN1_4", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_NE4C3_4", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_EE4A3_4", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_CLK0_4", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_EE2BEG1_4", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_SE4C2_4", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WW2A1_4", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_BYP6_4", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_NW4A0_4", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NE2A2_4", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_SE2A1_4", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NW4A1_4", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_BYP2_4", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_FAN3_4", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_IMUX19_4", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_WL1END1_4", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_WW4B1_4", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_ER1BEG1_4", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_IMUX9_4", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_EE4BEG0_4", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_WL1END3_4", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_BYP1_4", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WR1END2_4", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_WW4B2_4", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_BYP7_4", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_SE2A2_4", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX14_4", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_NW4END2_4", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_EE4C2_4", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_WW4B3_4", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_NW2A3_4", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_IMUX0_4", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_IMUX43_4", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX5_4", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX32_4", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_LH5_4", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX46_4", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_SE4C1_4", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX44_4", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_EE4B3_4", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_WL1END0_4", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_WW2A3_4", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX31_4", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_IMUX41_4", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_WW4A1_4", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_SW4A3_4", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EL1BEG2_4", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX12_4", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_WR1END1_4", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_FAN7_4", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX10_4", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_WW4A3_4", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_NE4C1_4", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_ER1BEG0_4", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_NE4BEG0_4", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_ER1BEG2_4", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_WR1END3_4", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_WW2END3_4", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_EL1BEG0_4", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_SE4BEG0_4", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_IMUX24_4", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_SW2A0_4", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_WW2END1_4", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_FAN4_4", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_EE2A1_4", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_LH10_4", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_CTRL1_4", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_BYP0_4", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_SE2A0_4", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_WW4A2_4", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_EE4C1_4", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_EE4B1_4", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_IMUX15_4", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_LH3_4", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_WW4A0_4", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_LH11_4", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_LH7_4", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_NE2A3_4", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_WW4C0_4", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_NW2A2_4", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_SW4END1_4", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_NE4BEG3_4", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX7_4", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_WW2END2_4", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_IMUX3_4", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_FAN5_4", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_ER1BEG3_4", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_BYP4_4", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_IMUX37_4", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SE4C0_4", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_SE4C3_4", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_LH1_4", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NW2A0_4", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_FAN0_4", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX11_4", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_LH6_4", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX8_4", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_IMUX36_4", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_EE4BEG1_4", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_LH2_4", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EE4B2_4", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX45_4", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX27_4", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_EE4A2_4", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_EE2BEG3_4", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX13_4", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_SW4END2_4", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_IMUX42_4", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX38_4", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_FAN6_4", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_EE2BEG0_4", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_EE2A0_4", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_SW4END3_4", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_CLK1_4", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_EE2A2_4", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_EE4C0_4", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_NW2A1_4", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_NE4C0_4", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE4BEG3_4", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_WW2A0_4", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_NW4END0_4", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_SW4END0_4", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_NW4A2_4", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_IMUX18_4", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX25_4", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_NW4END1_4", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_WW4END2_4", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_SW2A1_4", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WR1END0_4", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_WL1END2_4", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_FAN2_4", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_WW4B0_4", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_LH8_4", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_IMUX29_4", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_BYP3_4", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_NE4BEG1_4", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_WW4END0_4", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX22_4", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW4C1_4", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_WW4END3_4", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_NE4BEG2_4", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG1_4", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_IMUX16_4", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_SE2A3_4", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_IMUX30_4", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_WW4END1_4", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX23_4", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW4C3_4", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX33_4", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_IMUX20_4", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_IMUX34_4", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_IMUX47_4", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_LH12_4", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_SW4A2_4", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_WW2END0_4", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_NW4END3_4", + "VFRAME_NW4END3" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "DSP_WW4C0_1", + "INT_INTERFACE_WW4C0" + ], + [ + "DSP_SW4A2_1", + "INT_INTERFACE_SW4A2" + ], + [ + "DSP_WW4A1_1", + "INT_INTERFACE_WW4A1" + ], + [ + "DSP_IMUX39_1", + "INT_INTERFACE_IMUX39" + ], + [ + "DSP_LOGIC_OUTS_B17_1", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "DSP_NW4END2_1", + "INT_INTERFACE_NW4END2" + ], + [ + "DSP_NE4BEG2_1", + "INT_INTERFACE_NE4BEG2" + ], + [ + "DSP_BYP5_1", + "INT_INTERFACE_BYP5" + ], + [ + "DSP_EE2BEG3_1", + "INT_INTERFACE_EE2BEG3" + ], + [ + "DSP_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "DSP_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "DSP_EE4C3_1", + "INT_INTERFACE_EE4C3" + ], + [ + "DSP_LOGIC_OUTS_B12_1", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "DSP_BYP4_1", + "INT_INTERFACE_BYP4" + ], + [ + "DSP_SW4END3_1", + "INT_INTERFACE_SW4END3" + ], + [ + "DSP_EE4C2_1", + "INT_INTERFACE_EE4C2" + ], + [ + "DSP_ER1BEG3_1", + "INT_INTERFACE_ER1BEG3" + ], + [ + "DSP_NE4BEG0_1", + "INT_INTERFACE_NE4BEG0" + ], + [ + "DSP_IMUX6_1", + "INT_INTERFACE_IMUX6" + ], + [ + "DSP_IMUX15_1", + "INT_INTERFACE_IMUX15" + ], + [ + "DSP_IMUX44_1", + "INT_INTERFACE_IMUX44" + ], + [ + "DSP_FAN3_1", + "INT_INTERFACE_FAN3" + ], + [ + "DSP_WL1END2_1", + "INT_INTERFACE_WL1END2" + ], + [ + "DSP_IMUX8_1", + "INT_INTERFACE_IMUX8" + ], + [ + "DSP_IMUX2_1", + "INT_INTERFACE_IMUX2" + ], + [ + "DSP_NW4END0_1", + "INT_INTERFACE_NW4END0" + ], + [ + "DSP_BYP3_1", + "INT_INTERFACE_BYP3" + ], + [ + "DSP_SE4BEG0_1", + "INT_INTERFACE_SE4BEG0" + ], + [ + "DSP_WR1END2_1", + "INT_INTERFACE_WR1END2" + ], + [ + "DSP_FAN0_1", + "INT_INTERFACE_FAN0" + ], + [ + "DSP_EE4C0_1", + "INT_INTERFACE_EE4C0" + ], + [ + "DSP_BYP1_1", + "INT_INTERFACE_BYP1" + ], + [ + "DSP_WW4A0_1", + "INT_INTERFACE_WW4A0" + ], + [ + "DSP_LOGIC_OUTS_B0_1", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "DSP_EE2A3_1", + "INT_INTERFACE_EE2A3" + ], + [ + "DSP_EE4A2_1", + "INT_INTERFACE_EE4A2" + ], + [ + "DSP_NE4BEG3_1", + "INT_INTERFACE_NE4BEG3" + ], + [ + "DSP_LH12_1", + "INT_INTERFACE_LH12" + ], + [ + "DSP_IMUX3_1", + "INT_INTERFACE_IMUX3" + ], + [ + "DSP_WW4C1_1", + "INT_INTERFACE_WW4C1" + ], + [ + "DSP_IMUX1_1", + "INT_INTERFACE_IMUX1" + ], + [ + "DSP_NW4A1_1", + "INT_INTERFACE_NW4A1" + ], + [ + "DSP_EE4C1_1", + "INT_INTERFACE_EE4C1" + ], + [ + "DSP_WL1END1_1", + "INT_INTERFACE_WL1END1" + ], + [ + "DSP_SW4A1_1", + "INT_INTERFACE_SW4A1" + ], + [ + "DSP_SE2A3_1", + "INT_INTERFACE_SE2A3" + ], + [ + "DSP_IMUX29_1", + "INT_INTERFACE_IMUX29" + ], + [ + "DSP_EE4B3_1", + "INT_INTERFACE_EE4B3" + ], + [ + "DSP_SE4BEG2_1", + "INT_INTERFACE_SE4BEG2" + ], + [ + "DSP_IMUX38_1", + "INT_INTERFACE_IMUX38" + ], + [ + "DSP_NE2A0_1", + "INT_INTERFACE_NE2A0" + ], + [ + "DSP_EE2BEG1_1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "DSP_IMUX12_1", + "INT_INTERFACE_IMUX12" + ], + [ + "DSP_FAN2_1", + "INT_INTERFACE_FAN2" + ], + [ + "DSP_IMUX46_1", + "INT_INTERFACE_IMUX46" + ], + [ + "DSP_NE2A1_1", + "INT_INTERFACE_NE2A1" + ], + [ + "DSP_WR1END0_1", + "INT_INTERFACE_WR1END0" + ], + [ + "DSP_SW2A2_1", + "INT_INTERFACE_SW2A2" + ], + [ + "DSP_LH8_1", + "INT_INTERFACE_LH8" + ], + [ + "DSP_LOGIC_OUTS_B20_1", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "DSP_LOGIC_OUTS_B6_1", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "DSP_WW4B1_1", + "INT_INTERFACE_WW4B1" + ], + [ + "DSP_NE4BEG1_1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "DSP_IMUX18_1", + "INT_INTERFACE_IMUX18" + ], + [ + "DSP_SW2A0_1", + "INT_INTERFACE_SW2A0" + ], + [ + "DSP_MONITOR_P_1", + "INT_INTERFACE_MONITOR_P" + ], + [ + "DSP_SE4BEG1_1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "DSP_IMUX31_1", + "INT_INTERFACE_IMUX31" + ], + [ + "DSP_NW2A1_1", + "INT_INTERFACE_NW2A1" + ], + [ + "DSP_IMUX28_1", + "INT_INTERFACE_IMUX28" + ], + [ + "DSP_NE4C1_1", + "INT_INTERFACE_NE4C1" + ], + [ + "DSP_SE4C2_1", + "INT_INTERFACE_SE4C2" + ], + [ + "DSP_IMUX27_1", + "INT_INTERFACE_IMUX27" + ], + [ + "DSP_IMUX24_1", + "INT_INTERFACE_IMUX24" + ], + [ + "DSP_WW2END3_1", + "INT_INTERFACE_WW2END3" + ], + [ + "DSP_LH11_1", + "INT_INTERFACE_LH11" + ], + [ + "DSP_IMUX22_1", + "INT_INTERFACE_IMUX22" + ], + [ + "DSP_SE2A0_1", + "INT_INTERFACE_SE2A0" + ], + [ + "DSP_LOGIC_OUTS_B1_1", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "DSP_CTRL0_1", + "INT_INTERFACE_CTRL0" + ], + [ + "DSP_WW4B2_1", + "INT_INTERFACE_WW4B2" + ], + [ + "DSP_SW4A3_1", + "INT_INTERFACE_SW4A3" + ], + [ + "DSP_IMUX41_1", + "INT_INTERFACE_IMUX41" + ], + [ + "DSP_LH7_1", + "INT_INTERFACE_LH7" + ], + [ + "DSP_LOGIC_OUTS_B16_1", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "DSP_EE4BEG2_1", + "INT_INTERFACE_EE4BEG2" + ], + [ + "DSP_MONITOR_N_1", + "INT_INTERFACE_MONITOR_N" + ], + [ + "DSP_IMUX13_1", + "INT_INTERFACE_IMUX13" + ], + [ + "DSP_WW4C2_1", + "INT_INTERFACE_WW4C2" + ], + [ + "DSP_LOGIC_OUTS_B11_1", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "DSP_IMUX10_1", + "INT_INTERFACE_IMUX10" + ], + [ + "DSP_CLK0_1", + "INT_INTERFACE_CLK0" + ], + [ + "DSP_WW4C3_1", + "INT_INTERFACE_WW4C3" + ], + [ + "DSP_IMUX37_1", + "INT_INTERFACE_IMUX37" + ], + [ + "DSP_IMUX16_1", + "INT_INTERFACE_IMUX16" + ], + [ + "DSP_IMUX34_1", + "INT_INTERFACE_IMUX34" + ], + [ + "DSP_EL1BEG1_1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "DSP_IMUX45_1", + "INT_INTERFACE_IMUX45" + ], + [ + "DSP_LH5_1", + "INT_INTERFACE_LH5" + ], + [ + "DSP_WW4B3_1", + "INT_INTERFACE_WW4B3" + ], + [ + "DSP_SW2A1_1", + "INT_INTERFACE_SW2A1" + ], + [ + "DSP_EE4B2_1", + "INT_INTERFACE_EE4B2" + ], + [ + "DSP_NW4END1_1", + "INT_INTERFACE_NW4END1" + ], + [ + "DSP_WR1END1_1", + "INT_INTERFACE_WR1END1" + ], + [ + "DSP_LOGIC_OUTS_B2_1", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "DSP_EE4A0_1", + "INT_INTERFACE_EE4A0" + ], + [ + "DSP_WL1END0_1", + "INT_INTERFACE_WL1END0" + ], + [ + "DSP_LH4_1", + "INT_INTERFACE_LH4" + ], + [ + "DSP_ER1BEG2_1", + "INT_INTERFACE_ER1BEG2" + ], + [ + "DSP_CLK1_1", + "INT_INTERFACE_CLK1" + ], + [ + "DSP_SE4BEG3_1", + "INT_INTERFACE_SE4BEG3" + ], + [ + "DSP_SE4C0_1", + "INT_INTERFACE_SE4C0" + ], + [ + "DSP_LOGIC_OUTS_B7_1", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "DSP_EE4B1_1", + "INT_INTERFACE_EE4B1" + ], + [ + "DSP_EE4BEG1_1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "DSP_EE2A2_1", + "INT_INTERFACE_EE2A2" + ], + [ + "DSP_WW4END3_1", + "INT_INTERFACE_WW4END3" + ], + [ + "DSP_LOGIC_OUTS_B19_1", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "DSP_LOGIC_OUTS_B23_1", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "DSP_SW4A0_1", + "INT_INTERFACE_SW4A0" + ], + [ + "DSP_WR1END3_1", + "INT_INTERFACE_WR1END3" + ], + [ + "DSP_SE2A1_1", + "INT_INTERFACE_SE2A1" + ], + [ + "DSP_IMUX36_1", + "INT_INTERFACE_IMUX36" + ], + [ + "DSP_SW4END1_1", + "INT_INTERFACE_SW4END1" + ], + [ + "DSP_IMUX0_1", + "INT_INTERFACE_IMUX0" + ], + [ + "DSP_LOGIC_OUTS_B5_1", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "DSP_FAN6_1", + "INT_INTERFACE_FAN6" + ], + [ + "DSP_SE2A2_1", + "INT_INTERFACE_SE2A2" + ], + [ + "DSP_LH6_1", + "INT_INTERFACE_LH6" + ], + [ + "DSP_EE4A1_1", + "INT_INTERFACE_EE4A1" + ], + [ + "DSP_ER1BEG1_1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "DSP_EE2BEG2_1", + "INT_INTERFACE_EE2BEG2" + ], + [ + "DSP_NE2A3_1", + "INT_INTERFACE_NE2A3" + ], + [ + "DSP_EE4A3_1", + "INT_INTERFACE_EE4A3" + ], + [ + "DSP_WW4B0_1", + "INT_INTERFACE_WW4B0" + ], + [ + "DSP_NE2A2_1", + "INT_INTERFACE_NE2A2" + ], + [ + "DSP_NW4A3_1", + "INT_INTERFACE_NW4A3" + ], + [ + "DSP_SW4END0_1", + "INT_INTERFACE_SW4END0" + ], + [ + "DSP_LH9_1", + "INT_INTERFACE_LH9" + ], + [ + "DSP_LOGIC_OUTS_B18_1", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "DSP_SW4END2_1", + "INT_INTERFACE_SW4END2" + ], + [ + "DSP_IMUX30_1", + "INT_INTERFACE_IMUX30" + ], + [ + "DSP_FAN5_1", + "INT_INTERFACE_FAN5" + ], + [ + "DSP_WW2A0_1", + "INT_INTERFACE_WW2A0" + ], + [ + "DSP_EE2BEG0_1", + "INT_INTERFACE_EE2BEG0" + ], + [ + "DSP_EE4B0_1", + "INT_INTERFACE_EE4B0" + ], + [ + "DSP_CTRL1_1", + "INT_INTERFACE_CTRL1" + ], + [ + "DSP_IMUX9_1", + "INT_INTERFACE_IMUX9" + ], + [ + "DSP_IMUX14_1", + "INT_INTERFACE_IMUX14" + ], + [ + "DSP_EE4BEG0_1", + "INT_INTERFACE_EE4BEG0" + ], + [ + "DSP_EE4BEG3_1", + "INT_INTERFACE_EE4BEG3" + ], + [ + "DSP_WW2END1_1", + "INT_INTERFACE_WW2END1" + ], + [ + "DSP_WW4END1_1", + "INT_INTERFACE_WW4END1" + ], + [ + "DSP_LOGIC_OUTS_B13_1", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "DSP_BYP2_1", + "INT_INTERFACE_BYP2" + ], + [ + "DSP_IMUX35_1", + "INT_INTERFACE_IMUX35" + ], + [ + "DSP_NW4A0_1", + "INT_INTERFACE_NW4A0" + ], + [ + "DSP_LOGIC_OUTS_B10_1", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "DSP_IMUX32_1", + "INT_INTERFACE_IMUX32" + ], + [ + "DSP_IMUX17_1", + "INT_INTERFACE_IMUX17" + ], + [ + "DSP_BYP0_1", + "INT_INTERFACE_BYP0" + ], + [ + "DSP_NW2A2_1", + "INT_INTERFACE_NW2A2" + ], + [ + "DSP_LOGIC_OUTS_B22_1", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "DSP_IMUX11_1", + "INT_INTERFACE_IMUX11" + ], + [ + "DSP_EL1BEG3_1", + "INT_INTERFACE_EL1BEG3" + ], + [ + "DSP_LH10_1", + "INT_INTERFACE_LH10" + ], + [ + "DSP_EE2A1_1", + "INT_INTERFACE_EE2A1" + ], + [ + "DSP_IMUX47_1", + "INT_INTERFACE_IMUX47" + ], + [ + "DSP_BYP6_1", + "INT_INTERFACE_BYP6" + ], + [ + "DSP_FAN4_1", + "INT_INTERFACE_FAN4" + ], + [ + "DSP_ER1BEG0_1", + "INT_INTERFACE_ER1BEG0" + ], + [ + "DSP_IMUX4_1", + "INT_INTERFACE_IMUX4" + ], + [ + "DSP_LOGIC_OUTS_B4_1", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "DSP_FAN1_1", + "INT_INTERFACE_FAN1" + ], + [ + "DSP_IMUX26_1", + "INT_INTERFACE_IMUX26" + ], + [ + "DSP_IMUX7_1", + "INT_INTERFACE_IMUX7" + ], + [ + "DSP_SE4C3_1", + "INT_INTERFACE_SE4C3" + ], + [ + "DSP_IMUX33_1", + "INT_INTERFACE_IMUX33" + ], + [ + "DSP_LOGIC_OUTS_B3_1", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "DSP_IMUX43_1", + "INT_INTERFACE_IMUX43" + ], + [ + "DSP_FAN7_1", + "INT_INTERFACE_FAN7" + ], + [ + "DSP_WW4END0_1", + "INT_INTERFACE_WW4END0" + ], + [ + "DSP_NW2A0_1", + "INT_INTERFACE_NW2A0" + ], + [ + "DSP_EL1BEG2_1", + "INT_INTERFACE_EL1BEG2" + ], + [ + "DSP_WW2END0_1", + "INT_INTERFACE_WW2END0" + ], + [ + "DSP_EE2A0_1", + "INT_INTERFACE_EE2A0" + ], + [ + "DSP_IMUX42_1", + "INT_INTERFACE_IMUX42" + ], + [ + "DSP_IMUX25_1", + "INT_INTERFACE_IMUX25" + ], + [ + "DSP_NE4C3_1", + "INT_INTERFACE_NE4C3" + ], + [ + "DSP_LH1_1", + "INT_INTERFACE_LH1" + ], + [ + "DSP_LOGIC_OUTS_B21_1", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "DSP_LH2_1", + "INT_INTERFACE_LH2" + ], + [ + "DSP_NE4C2_1", + "INT_INTERFACE_NE4C2" + ], + [ + "DSP_IMUX23_1", + "INT_INTERFACE_IMUX23" + ], + [ + "DSP_WL1END3_1", + "INT_INTERFACE_WL1END3" + ], + [ + "DSP_BYP7_1", + "INT_INTERFACE_BYP7" + ], + [ + "DSP_NE4C0_1", + "INT_INTERFACE_NE4C0" + ], + [ + "DSP_SE4C1_1", + "INT_INTERFACE_SE4C1" + ], + [ + "DSP_EL1BEG0_1", + "INT_INTERFACE_EL1BEG0" + ], + [ + "DSP_IMUX5_1", + "INT_INTERFACE_IMUX5" + ], + [ + "DSP_IMUX20_1", + "INT_INTERFACE_IMUX20" + ], + [ + "DSP_WW2A3_1", + "INT_INTERFACE_WW2A3" + ], + [ + "DSP_WW4A3_1", + "INT_INTERFACE_WW4A3" + ], + [ + "DSP_IMUX21_1", + "INT_INTERFACE_IMUX21" + ], + [ + "DSP_IMUX40_1", + "INT_INTERFACE_IMUX40" + ], + [ + "DSP_WW4END2_1", + "INT_INTERFACE_WW4END2" + ], + [ + "DSP_SW2A3_1", + "INT_INTERFACE_SW2A3" + ], + [ + "DSP_IMUX19_1", + "INT_INTERFACE_IMUX19" + ], + [ + "DSP_NW2A3_1", + "INT_INTERFACE_NW2A3" + ], + [ + "DSP_NW4END3_1", + "INT_INTERFACE_NW4END3" + ], + [ + "DSP_WW2END2_1", + "INT_INTERFACE_WW2END2" + ], + [ + "DSP_LH3_1", + "INT_INTERFACE_LH3" + ], + [ + "DSP_WW4A2_1", + "INT_INTERFACE_WW4A2" + ], + [ + "DSP_NW4A2_1", + "INT_INTERFACE_NW4A2" + ] + ], + "tile_types": [ + "DSP_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "DSP_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "DSP_LH11_2", + "VBRK_LH11" + ], + [ + "DSP_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "DSP_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "DSP_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "DSP_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "DSP_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "DSP_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "DSP_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "DSP_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "DSP_LH4_2", + "VBRK_LH4" + ], + [ + "DSP_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "DSP_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "DSP_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "DSP_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "DSP_LH8_2", + "VBRK_LH8" + ], + [ + "DSP_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "DSP_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "DSP_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "DSP_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "DSP_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "DSP_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "DSP_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "DSP_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "DSP_MONITOR_N_2", + "VBRK_MONITOR_N" + ], + [ + "DSP_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "DSP_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "DSP_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "DSP_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "DSP_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "DSP_LH2_2", + "VBRK_LH2" + ], + [ + "DSP_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "DSP_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "DSP_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "DSP_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "DSP_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "DSP_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "DSP_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "DSP_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "DSP_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "DSP_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "DSP_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "DSP_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "DSP_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "DSP_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "DSP_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "DSP_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "DSP_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "DSP_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "DSP_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "DSP_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "DSP_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "DSP_LH6_2", + "VBRK_LH6" + ], + [ + "DSP_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "DSP_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "DSP_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "DSP_LH5_2", + "VBRK_LH5" + ], + [ + "DSP_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "DSP_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "DSP_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "DSP_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "DSP_LH3_2", + "VBRK_LH3" + ], + [ + "DSP_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "DSP_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "DSP_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "DSP_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "DSP_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "DSP_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "DSP_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "DSP_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "DSP_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "DSP_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "DSP_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "DSP_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "DSP_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "DSP_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "DSP_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "DSP_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "DSP_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "DSP_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "DSP_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "DSP_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "DSP_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "DSP_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "DSP_LH7_2", + "VBRK_LH7" + ], + [ + "DSP_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "DSP_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "DSP_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "DSP_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "DSP_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "DSP_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "DSP_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "DSP_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "DSP_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "DSP_MONITOR_P_2", + "VBRK_MONITOR_P" + ], + [ + "DSP_EE4B3_2", + "VBRK_EE4B3" + ], + [ + "DSP_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "DSP_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "DSP_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "DSP_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "DSP_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "DSP_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "DSP_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "DSP_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "DSP_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "DSP_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "DSP_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "DSP_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "DSP_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "DSP_NW2A2_2", + "VBRK_NW2A2" + ], + [ + "DSP_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "DSP_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "DSP_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "DSP_LH1_2", + "VBRK_LH1" + ], + [ + "DSP_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "DSP_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "DSP_LH9_2", + "VBRK_LH9" + ], + [ + "DSP_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "DSP_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "DSP_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "DSP_LH10_2", + "VBRK_LH10" + ], + [ + "DSP_LH12_2", + "VBRK_LH12" + ], + [ + "DSP_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "DSP_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "DSP_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "DSP_NE4BEG0_2", + "VBRK_NE4BEG0" + ] + ], + "tile_types": [ + "DSP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "CLK_HROW_WW4A3_7", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_NE4BEG1_7", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_ER1BEG0_7", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_ER1BEG1_7", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_NE2A1_7", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_LH11_7", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH8_7", + "VBRK_LH8" + ], + [ + "CLK_HROW_LH9_7", + "VBRK_LH9" + ], + [ + "CLK_HROW_NE4C2_7", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_SW4A2_7", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_SW4END2_7", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_EE4B0_7", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WW4B3_7", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_EE4A1_7", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_SW2A0_7", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_SE4C1_7", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_EE4BEG1_7", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WW4B2_7", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_LH7_7", + "VBRK_LH7" + ], + [ + "CLK_HROW_SE2A0_7", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_WW4B1_7", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_EE4C0_7", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_EE4C2_7", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_WW4END2_7", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_EE2A2_7", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_NW4A3_7", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_EL1BEG0_7", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_WW2END3_7", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_EE2BEG1_7", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_SW2A1_7", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_NE4BEG0_7", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_EE2BEG0_7", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_LH1_7", + "VBRK_LH1" + ], + [ + "CLK_HROW_SE4C0_7", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_SE2A3_7", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_SE4C2_7", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_NE4C3_7", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_SW4END0_7", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_WL1END1_7", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_WW2END2_7", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_LH12_7", + "VBRK_LH12" + ], + [ + "CLK_HROW_WR1END2_7", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_NE4BEG2_7", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WL1END3_7", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_SE4BEG1_7", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_WW4A0_7", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_EE4A3_7", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_EL1BEG1_7", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_LH3_7", + "VBRK_LH3" + ], + [ + "CLK_HROW_WW4A1_7", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_NW4END2_7", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_WW4C3_7", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_EE4BEG2_7", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_WR1END1_7", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_EE2A1_7", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_WL1END0_7", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_NW2A1_7", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_NW4A1_7", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_WW4END3_7", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_NW2A0_7", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_LH4_7", + "VBRK_LH4" + ], + [ + "CLK_HROW_EL1BEG3_7", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_NW2A2_7", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_SW2A3_7", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_NW4A0_7", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_WW2A1_7", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_SE4BEG3_7", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_NE2A3_7", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_EE4BEG3_7", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_SE2A1_7", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_SW2A2_7", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_SE4C3_7", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_WR1END3_7", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_SW4A3_7", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_WW4C0_7", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_SE2A2_7", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_WW4A2_7", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_EE2BEG3_7", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_SE4BEG2_7", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_NW4A2_7", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_WW4C1_7", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_SW4END1_7", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_EE4B1_7", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_ER1BEG2_7", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_WW2END0_7", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_EE4A0_7", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_LH10_7", + "VBRK_LH10" + ], + [ + "CLK_HROW_SW4END3_7", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_NW4END0_7", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_EE4B2_7", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_SE4BEG0_7", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_NW4END1_7", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_EE2A0_7", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_ER1BEG3_7", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_LH5_7", + "VBRK_LH5" + ], + [ + "CLK_HROW_EE4C1_7", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WW4END1_7", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_NE2A2_7", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_EE2A3_7", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_EL1BEG2_7", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_NE4BEG3_7", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_WW4C2_7", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_NW2A3_7", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_NW4END3_7", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_WW2A2_7", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_WW2A0_7", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_EE4BEG0_7", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_NE4C0_7", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WW2A3_7", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_LH6_7", + "VBRK_LH6" + ], + [ + "CLK_HROW_WW4B0_7", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EE2BEG2_7", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_WL1END2_7", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_WR1END0_7", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_LH2_7", + "VBRK_LH2" + ], + [ + "CLK_HROW_SW4A0_7", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_EE4B3_7", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_NE2A0_7", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_NE4C1_7", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_SW4A1_7", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_WW2END1_7", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_EE4C3_7", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_EE4A2_7", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_WW4END0_7", + "VBRK_WW4END0" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLK_FEED_EE4B1", + "VBRK_EE4B1" + ], + [ + "CLK_FEED_SE4C1", + "VBRK_SE4C1" + ], + [ + "CLK_FEED_EE2BEG0", + "VBRK_EE2BEG0" + ], + [ + "CLK_FEED_SW2A1", + "VBRK_SW2A1" + ], + [ + "CLK_FEED_WR1END1", + "VBRK_WR1END1" + ], + [ + "CLK_FEED_WL1END3", + "VBRK_WL1END3" + ], + [ + "CLK_FEED_NE2A2", + "VBRK_NE2A2" + ], + [ + "CLK_FEED_WW2END0", + "VBRK_WW2END0" + ], + [ + "CLK_FEED_LH9", + "VBRK_LH9" + ], + [ + "CLK_FEED_EE4C1", + "VBRK_EE4C1" + ], + [ + "CLK_FEED_NW2A0", + "VBRK_NW2A0" + ], + [ + "CLK_FEED_WW4A1", + "VBRK_WW4A1" + ], + [ + "CLK_FEED_NE2A1", + "VBRK_NE2A1" + ], + [ + "CLK_FEED_WW4A3", + "VBRK_WW4A3" + ], + [ + "CLK_FEED_WW2END1", + "VBRK_WW2END1" + ], + [ + "CLK_FEED_WW4C3", + "VBRK_WW4C3" + ], + [ + "CLK_FEED_LH5", + "VBRK_LH5" + ], + [ + "CLK_FEED_LH10", + "VBRK_LH10" + ], + [ + "CLK_FEED_LH12", + "VBRK_LH12" + ], + [ + "CLK_FEED_EE4B0", + "VBRK_EE4B0" + ], + [ + "CLK_FEED_EE4A2", + "VBRK_EE4A2" + ], + [ + "CLK_FEED_WW4END2", + "VBRK_WW4END2" + ], + [ + "CLK_FEED_NE4C2", + "VBRK_NE4C2" + ], + [ + "CLK_FEED_NW4A1", + "VBRK_NW4A1" + ], + [ + "CLK_FEED_SW4A2", + "VBRK_SW4A2" + ], + [ + "CLK_FEED_NW4END0", + "VBRK_NW4END0" + ], + [ + "CLK_FEED_WW2END3", + "VBRK_WW2END3" + ], + [ + "CLK_FEED_WW4C1", + "VBRK_WW4C1" + ], + [ + "CLK_FEED_SW2A0", + "VBRK_SW2A0" + ], + [ + "CLK_FEED_SW4A0", + "VBRK_SW4A0" + ], + [ + "CLK_FEED_NE4BEG3", + "VBRK_NE4BEG3" + ], + [ + "CLK_FEED_ER1BEG0", + "VBRK_ER1BEG0" + ], + [ + "CLK_FEED_EE2BEG2", + "VBRK_EE2BEG2" + ], + [ + "CLK_FEED_WW4B3", + "VBRK_WW4B3" + ], + [ + "CLK_FEED_WW2A3", + "VBRK_WW2A3" + ], + [ + "CLK_FEED_WW4C2", + "VBRK_WW4C2" + ], + [ + "CLK_FEED_LH8", + "VBRK_LH8" + ], + [ + "CLK_FEED_NE4C0", + "VBRK_NE4C0" + ], + [ + "CLK_FEED_EL1BEG3", + "VBRK_EL1BEG3" + ], + [ + "CLK_FEED_LH1", + "VBRK_LH1" + ], + [ + "CLK_FEED_EL1BEG0", + "VBRK_EL1BEG0" + ], + [ + "CLK_FEED_EE4A1", + "VBRK_EE4A1" + ], + [ + "CLK_FEED_SW2A2", + "VBRK_SW2A2" + ], + [ + "CLK_FEED_SE4C3", + "VBRK_SE4C3" + ], + [ + "CLK_FEED_EE4BEG0", + "VBRK_EE4BEG0" + ], + [ + "CLK_FEED_LH4", + "VBRK_LH4" + ], + [ + "CLK_FEED_NW4A2", + "VBRK_NW4A2" + ], + [ + "CLK_FEED_EE2BEG3", + "VBRK_EE2BEG3" + ], + [ + "CLK_FEED_SE4BEG0", + "VBRK_SE4BEG0" + ], + [ + "CLK_FEED_SE4BEG3", + "VBRK_SE4BEG3" + ], + [ + "CLK_FEED_WW4END0", + "VBRK_WW4END0" + ], + [ + "CLK_FEED_EE4B3", + "VBRK_EE4B3" + ], + [ + "CLK_FEED_SW4A3", + "VBRK_SW4A3" + ], + [ + "CLK_FEED_WL1END0", + "VBRK_WL1END0" + ], + [ + "CLK_FEED_WW2A1", + "VBRK_WW2A1" + ], + [ + "CLK_FEED_NE4C1", + "VBRK_NE4C1" + ], + [ + "CLK_FEED_WW2END2", + "VBRK_WW2END2" + ], + [ + "CLK_FEED_EE2A0", + "VBRK_EE2A0" + ], + [ + "CLK_FEED_SE4C2", + "VBRK_SE4C2" + ], + [ + "CLK_FEED_SW4END1", + "VBRK_SW4END1" + ], + [ + "CLK_FEED_EE4BEG2", + "VBRK_EE4BEG2" + ], + [ + "CLK_FEED_WL1END2", + "VBRK_WL1END2" + ], + [ + "CLK_FEED_EL1BEG2", + "VBRK_EL1BEG2" + ], + [ + "CLK_FEED_EE4BEG1", + "VBRK_EE4BEG1" + ], + [ + "CLK_FEED_WR1END3", + "VBRK_WR1END3" + ], + [ + "CLK_FEED_EE4C2", + "VBRK_EE4C2" + ], + [ + "CLK_FEED_NW4A3", + "VBRK_NW4A3" + ], + [ + "CLK_FEED_SW4END0", + "VBRK_SW4END0" + ], + [ + "CLK_FEED_WR1END0", + "VBRK_WR1END0" + ], + [ + "CLK_FEED_SE2A1", + "VBRK_SE2A1" + ], + [ + "CLK_FEED_WW4END3", + "VBRK_WW4END3" + ], + [ + "CLK_FEED_NW2A3", + "VBRK_NW2A3" + ], + [ + "CLK_FEED_WR1END2", + "VBRK_WR1END2" + ], + [ + "CLK_FEED_NW4END1", + "VBRK_NW4END1" + ], + [ + "CLK_FEED_LH11", + "VBRK_LH11" + ], + [ + "CLK_FEED_WW4B0", + "VBRK_WW4B0" + ], + [ + "CLK_FEED_NW4A0", + "VBRK_NW4A0" + ], + [ + "CLK_FEED_MONITOR_P", + "VBRK_MONITOR_P" + ], + [ + "CLK_FEED_NW2A1", + "VBRK_NW2A1" + ], + [ + "CLK_FEED_EE4A0", + "VBRK_EE4A0" + ], + [ + "CLK_FEED_NE4C3", + "VBRK_NE4C3" + ], + [ + "CLK_FEED_EE2A1", + "VBRK_EE2A1" + ], + [ + "CLK_FEED_LH6", + "VBRK_LH6" + ], + [ + "CLK_FEED_LH7", + "VBRK_LH7" + ], + [ + "CLK_FEED_WW4B2", + "VBRK_WW4B2" + ], + [ + "CLK_FEED_SW4END2", + "VBRK_SW4END2" + ], + [ + "CLK_FEED_WW4B1", + "VBRK_WW4B1" + ], + [ + "CLK_FEED_NW4END2", + "VBRK_NW4END2" + ], + [ + "CLK_FEED_WL1END1", + "VBRK_WL1END1" + ], + [ + "CLK_FEED_SW4A1", + "VBRK_SW4A1" + ], + [ + "CLK_FEED_NE2A0", + "VBRK_NE2A0" + ], + [ + "CLK_FEED_NW2A2", + "VBRK_NW2A2" + ], + [ + "CLK_FEED_WW2A0", + "VBRK_WW2A0" + ], + [ + "CLK_FEED_EE2A3", + "VBRK_EE2A3" + ], + [ + "CLK_FEED_WW2A2", + "VBRK_WW2A2" + ], + [ + "CLK_FEED_LH2", + "VBRK_LH2" + ], + [ + "CLK_FEED_EE4C3", + "VBRK_EE4C3" + ], + [ + "CLK_FEED_WW4END1", + "VBRK_WW4END1" + ], + [ + "CLK_FEED_NE4BEG0", + "VBRK_NE4BEG0" + ], + [ + "CLK_FEED_NW4END3", + "VBRK_NW4END3" + ], + [ + "CLK_FEED_SW2A3", + "VBRK_SW2A3" + ], + [ + "CLK_FEED_EE2A2", + "VBRK_EE2A2" + ], + [ + "CLK_FEED_EE4B2", + "VBRK_EE4B2" + ], + [ + "CLK_FEED_WW4A2", + "VBRK_WW4A2" + ], + [ + "CLK_FEED_ER1BEG2", + "VBRK_ER1BEG2" + ], + [ + "CLK_FEED_EE4BEG3", + "VBRK_EE4BEG3" + ], + [ + "CLK_FEED_EE4C0", + "VBRK_EE4C0" + ], + [ + "CLK_FEED_MONITOR_N", + "VBRK_MONITOR_N" + ], + [ + "CLK_FEED_NE4BEG2", + "VBRK_NE4BEG2" + ], + [ + "CLK_FEED_SW4END3", + "VBRK_SW4END3" + ], + [ + "CLK_FEED_WW4A0", + "VBRK_WW4A0" + ], + [ + "CLK_FEED_NE4BEG1", + "VBRK_NE4BEG1" + ], + [ + "CLK_FEED_SE2A0", + "VBRK_SE2A0" + ], + [ + "CLK_FEED_EE2BEG1", + "VBRK_EE2BEG1" + ], + [ + "CLK_FEED_ER1BEG3", + "VBRK_ER1BEG3" + ], + [ + "CLK_FEED_LH3", + "VBRK_LH3" + ], + [ + "CLK_FEED_ER1BEG1", + "VBRK_ER1BEG1" + ], + [ + "CLK_FEED_EL1BEG1", + "VBRK_EL1BEG1" + ], + [ + "CLK_FEED_SE4C0", + "VBRK_SE4C0" + ], + [ + "CLK_FEED_SE4BEG1", + "VBRK_SE4BEG1" + ], + [ + "CLK_FEED_SE2A2", + "VBRK_SE2A2" + ], + [ + "CLK_FEED_EE4A3", + "VBRK_EE4A3" + ], + [ + "CLK_FEED_SE2A3", + "VBRK_SE2A3" + ], + [ + "CLK_FEED_WW4C0", + "VBRK_WW4C0" + ], + [ + "CLK_FEED_SE4BEG2", + "VBRK_SE4BEG2" + ], + [ + "CLK_FEED_NE2A3", + "VBRK_NE2A3" + ] + ], + "tile_types": [ + "CLK_MTBF2", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 6 + ], + "wire_pairs": [ + [ + "CFG_CENTER_CK_BUFHCLK5", + "HCLK_FEEDTHRU_2_CK_BUFHCLK5" + ], + [ + "CFG_CENTER_CK_BUFRCLK1", + "HCLK_FEEDTHRU_2_CK_BUFRCLK1" + ], + [ + "CFG_CENTER_CK_BUFHCLK9", + "HCLK_FEEDTHRU_2_CK_BUFHCLK9" + ], + [ + "CFG_CENTER_CK_IN10", + "HCLK_FEEDTHRU_2_CK_IN10" + ], + [ + "CFG_CENTER_CK_BUFRCLK3", + "HCLK_FEEDTHRU_2_CK_BUFRCLK3" + ], + [ + "CFG_CENTER_CK_BUFHCLK11", + "HCLK_FEEDTHRU_2_CK_BUFHCLK11" + ], + [ + "CFG_CENTER_CK_BUFRCLK0", + "HCLK_FEEDTHRU_2_CK_BUFRCLK0" + ], + [ + "CFG_CENTER_CK_IN5", + "HCLK_FEEDTHRU_2_CK_IN5" + ], + [ + "CFG_CENTER_CK_IN12", + "HCLK_FEEDTHRU_2_CK_IN12" + ], + [ + "CFG_CENTER_CK_IN11", + "HCLK_FEEDTHRU_2_CK_IN11" + ], + [ + "CFG_CENTER_CK_BUFRCLK2", + "HCLK_FEEDTHRU_2_CK_BUFRCLK2" + ], + [ + "CFG_CENTER_CK_IN13", + "HCLK_FEEDTHRU_2_CK_IN13" + ], + [ + "CFG_CENTER_CK_BUFHCLK6", + "HCLK_FEEDTHRU_2_CK_BUFHCLK6" + ], + [ + "CFG_CENTER_CK_BUFHCLK8", + "HCLK_FEEDTHRU_2_CK_BUFHCLK8" + ], + [ + "CFG_CENTER_CK_BUFHCLK4", + "HCLK_FEEDTHRU_2_CK_BUFHCLK4" + ], + [ + "CFG_CENTER_CK_BUFHCLK7", + "HCLK_FEEDTHRU_2_CK_BUFHCLK7" + ], + [ + "CFG_CENTER_CK_IN3", + "HCLK_FEEDTHRU_2_CK_IN3" + ], + [ + "CFG_CENTER_CK_BUFHCLK2", + "HCLK_FEEDTHRU_2_CK_BUFHCLK2" + ], + [ + "CFG_CENTER_CK_IN6", + "HCLK_FEEDTHRU_2_CK_IN6" + ], + [ + "CFG_CENTER_CK_IN1", + "HCLK_FEEDTHRU_2_CK_IN1" + ], + [ + "CFG_CENTER_CK_IN0", + "HCLK_FEEDTHRU_2_CK_IN0" + ], + [ + "CFG_CENTER_CK_IN9", + "HCLK_FEEDTHRU_2_CK_IN9" + ], + [ + "CFG_CENTER_CK_IN7", + "HCLK_FEEDTHRU_2_CK_IN7" + ], + [ + "CFG_CENTER_CK_IN2", + "HCLK_FEEDTHRU_2_CK_IN2" + ], + [ + "CFG_CENTER_CK_IN4", + "HCLK_FEEDTHRU_2_CK_IN4" + ], + [ + "CFG_CENTER_CK_IN8", + "HCLK_FEEDTHRU_2_CK_IN8" + ], + [ + "CFG_CENTER_CK_BUFHCLK0", + "HCLK_FEEDTHRU_2_CK_BUFHCLK0" + ], + [ + "CFG_CENTER_CK_BUFHCLK1", + "HCLK_FEEDTHRU_2_CK_BUFHCLK1" + ], + [ + "CFG_CENTER_CK_BUFHCLK3", + "HCLK_FEEDTHRU_2_CK_BUFHCLK3" + ], + [ + "CFG_CENTER_CK_BUFHCLK10", + "HCLK_FEEDTHRU_2_CK_BUFHCLK10" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "HCLK_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "IOI_IMUX11_0", + "TERM_INT_IMUX11" + ], + [ + "IOI_IMUX43_0", + "TERM_INT_IMUX43" + ], + [ + "IOI_FAN1_0", + "TERM_INT_FAN1" + ], + [ + "IOI_CTRL1_0", + "TERM_INT_CTRL1" + ], + [ + "IOI_LOGIC_OUTS18_0", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_BYP2_0", + "TERM_INT_BYP2" + ], + [ + "IOI_LOGIC_OUTS2_0", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_IMUX6_0", + "TERM_INT_IMUX6" + ], + [ + "IOI_IMUX36_0", + "TERM_INT_IMUX36" + ], + [ + "IOI_IMUX34_0", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX0_0", + "TERM_INT_IMUX0" + ], + [ + "IOI_IMUX46_0", + "TERM_INT_IMUX46" + ], + [ + "IOI_IMUX20_0", + "TERM_INT_IMUX20" + ], + [ + "IOI_LOGIC_OUTS23_0", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_LOGIC_OUTS15_0", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX19_0", + "TERM_INT_IMUX19" + ], + [ + "IOI_IMUX47_0", + "TERM_INT_IMUX47" + ], + [ + "IOI_LOGIC_OUTS17_0", + "TERM_INT_LOGIC_OUTS_L_B17" + ], + [ + "IOI_IMUX25_0", + "TERM_INT_IMUX25" + ], + [ + "IOI_LOGIC_OUTS7_0", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_FAN2_0", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX45_0", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX31_0", + "TERM_INT_IMUX31" + ], + [ + "IOI_LOGIC_OUTS19_0", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_IMUX1_0", + "TERM_INT_IMUX1" + ], + [ + "IOI_MONITOR_N", + "TERM_INT_MONITOR_N" + ], + [ + "IOI_IMUX22_0", + "TERM_INT_IMUX22" + ], + [ + "IOI_IMUX12_0", + "TERM_INT_IMUX12" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_BLOCK_OUTS2_0", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "IOI_IMUX40_0", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX10_0", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX16_0", + "TERM_INT_IMUX16" + ], + [ + "IOI_FAN0_0", + "TERM_INT_FAN0" + ], + [ + "IOI_IMUX38_0", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX26_0", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX3_0", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX24_0", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX37_0", + "TERM_INT_IMUX37" + ], + [ + "IOI_LOGIC_OUTS3_0", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_FAN4_0", + "TERM_INT_FAN4" + ], + [ + "IOI_FAN6_0", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX7_0", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX39_0", + "TERM_INT_IMUX39" + ], + [ + "IOI_CTRL0_0", + "TERM_INT_CTRL0" + ], + [ + "IOI_CLK0_0", + "TERM_INT_CLK0" + ], + [ + "IOI_CLK1_0", + "TERM_INT_CLK1" + ], + [ + "IOI_FAN7_0", + "TERM_INT_FAN7" + ], + [ + "IOI_BYP0_0", + "TERM_INT_BYP0" + ], + [ + "IOI_LOGIC_OUTS0_0", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_LOGIC_OUTS21_0", + "TERM_INT_LOGIC_OUTS_L_B21" + ], + [ + "IOI_LOGIC_OUTS6_0", + "TERM_INT_LOGIC_OUTS_L_B6" + ], + [ + "IOI_IMUX8_0", + "TERM_INT_IMUX8" + ], + [ + "IOI_LOGIC_OUTS11_0", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_BYP6_0", + "TERM_INT_BYP6" + ], + [ + "IOI_IMUX42_0", + "TERM_INT_IMUX42" + ], + [ + "IOI_IMUX30_0", + "TERM_INT_IMUX30" + ], + [ + "IOI_LOGIC_OUTS1_0", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX5_0", + "TERM_INT_IMUX5" + ], + [ + "IOI_IMUX4_0", + "TERM_INT_IMUX4" + ], + [ + "IOI_IMUX17_0", + "TERM_INT_IMUX17" + ], + [ + "IOI_IMUX23_0", + "TERM_INT_IMUX23" + ], + [ + "IOI_PHASER_TO_IO_ICLK", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_IMUX33_0", + "TERM_INT_IMUX33" + ], + [ + "IOI_FAN5_0", + "TERM_INT_FAN5" + ], + [ + "IOI_BYP1_0", + "TERM_INT_BYP1" + ], + [ + "IOI_LOGIC_OUTS9_0", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_LOGIC_OUTS14_0", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_IMUX13_0", + "TERM_INT_IMUX13" + ], + [ + "IOI_IMUX44_0", + "TERM_INT_IMUX44" + ], + [ + "IOI_LOGIC_OUTS20_0", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_LOGIC_OUTS5_0", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_IMUX27_0", + "TERM_INT_IMUX27" + ], + [ + "IOI_IMUX18_0", + "TERM_INT_IMUX18" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_IMUX9_0", + "TERM_INT_IMUX9" + ], + [ + "IOI_BLOCK_OUTS1_0", + "TERM_INT_BLOCK_OUTS_L_B1" + ], + [ + "IOI_FAN3_0", + "TERM_INT_FAN3" + ], + [ + "IOI_BYP5_0", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS8_0", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_PHASER_TO_IO_OCLK", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_LOGIC_OUTS4_0", + "TERM_INT_LOGIC_OUTS_L_B4" + ], + [ + "IOI_BYP4_0", + "TERM_INT_BYP4" + ], + [ + "IOI_BYP7_0", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_0", + "TERM_INT_IMUX2" + ], + [ + "IOI_IMUX35_0", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP3_0", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX15_0", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX29_0", + "TERM_INT_IMUX29" + ], + [ + "IOI_LOGIC_OUTS10_0", + "TERM_INT_LOGIC_OUTS_L_B10" + ], + [ + "IOI_LOGIC_OUTS12_0", + "TERM_INT_LOGIC_OUTS_L_B12" + ], + [ + "IOI_IMUX14_0", + "TERM_INT_IMUX14" + ], + [ + "IOI_MONITOR_P", + "TERM_INT_MONITOR_P" + ], + [ + "IOI_IMUX21_0", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX28_0", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX41_0", + "TERM_INT_IMUX41" + ], + [ + "IOI_BLOCK_OUTS0_0", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_IMUX32_0", + "TERM_INT_IMUX32" + ] + ], + "tile_types": [ + "RIOI_TBYTETERM", + "R_TERM_INT" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ] + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_IMUX47_6", + "CMT_TOP_IMUX47_6" + ], + [ + "CMT_FIFO_L_IMUX45_6", + "CMT_TOP_IMUX45_6" + ], + [ + "CMT_FIFO_WW4B2_7", + "CMT_TOP_WW4B2_7" + ], + [ + "CMT_FIFO_SE4BEG3_3", + "CMT_TOP_SE4BEG3_3" + ], + [ + "CMT_FIFO_SW4END2_3", + "CMT_TOP_SW4END2_3" + ], + [ + "CMT_FIFO_L_BYP4_6", + "CMT_TOP_BYP4_6" + ], + [ + "CMT_FIFO_LH11_10", + "CMT_TOP_LH11_10" + ], + [ + "CMT_FIFO_L_IMUX22_4", + "CMT_TOP_IMUX22_4" + ], + [ + "CMT_FIFO_L_IMUX12_3", + "CMT_TOP_IMUX12_3" + ], + [ + "CMT_FIFO_SE2A3_1", + "CMT_TOP_SE2A3_1" + ], + [ + "CMT_FIFO_SW4A0_2", + "CMT_TOP_SW4A0_2" + ], + [ + "CMT_FIFO_LH3_2", + "CMT_TOP_LH3_2" + ], + [ + "CMT_FIFO_SW4END1_9", + "CMT_TOP_SW4END1_9" + ], + [ + "CMT_FIFO_L_IMUX8_9", + "CMT_TOP_IMUX8_9" + ], + [ + "CMT_FIFO_EE4A3_7", + "CMT_TOP_EE4A3_7" + ], + [ + "CMT_FIFO_SW4END3_11", + "CMT_TOP_SW4END3_11" + ], + [ + "CMT_FIFO_SE4C3_9", + "CMT_TOP_SE4C3_9" + ], + [ + "CMT_FIFO_NE4C0_10", + "CMT_TOP_NE4C0_10" + ], + [ + "CMT_FIFO_NE2A1_6", + "CMT_TOP_NE2A1_6" + ], + [ + "CMT_FIFO_WW2A0_8", + "CMT_TOP_WW2A0_8" + ], + [ + "CMT_FIFO_L_FAN3_4", + "CMT_TOP_FAN3_4" + ], + [ + "CMT_FIFO_NW4END3_6", + "CMT_TOP_NW4END3_6" + ], + [ + "CMT_FIFO_NW2A2_6", + "CMT_TOP_NW2A2_6" + ], + [ + "CMT_FIFO_SW4END1_8", + "CMT_TOP_SW4END1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_2", + "CMT_TOP_LOGIC_OUTS_L_B21_2" + ], + [ + "CMT_FIFO_WW2END1_5", + "CMT_TOP_WW2END1_5" + ], + [ + "CMT_FIFO_L_BYP6_2", + "CMT_TOP_BYP6_2" + ], + [ + "CMT_FIFO_NE4C0_8", + "CMT_TOP_NE4C0_8" + ], + [ + "CMT_FIFO_EE4A2_1", + "CMT_TOP_EE4A2_1" + ], + [ + "CMT_FIFO_EL1BEG0_9", + "CMT_TOP_EL1BEG0_9" + ], + [ + "CMT_FIFO_LH1_9", + "CMT_TOP_LH1_9" + ], + [ + "CMT_FIFO_WL1END1_11", + "CMT_TOP_WL1END1_11" + ], + [ + "CMT_FIFO_WW4C0_9", + "CMT_TOP_WW4C0_9" + ], + [ + "CMT_FIFO_WW2A2_7", + "CMT_TOP_WW2A2_7" + ], + [ + "CMT_FIFO_NW2A0_6", + "CMT_TOP_NW2A0_6" + ], + [ + "CMT_FIFO_NW4END3_7", + "CMT_TOP_NW4END3_7" + ], + [ + "CMT_FIFO_NE2A3_10", + "CMT_TOP_NE2A3_10" + ], + [ + "CMT_FIFO_EE2A0_9", + "CMT_TOP_EE2A0_9" + ], + [ + "CMT_FIFO_ER1BEG0_11", + "CMT_TOP_ER1BEG0_11" + ], + [ + "CMT_FIFO_ER1BEG2_7", + "CMT_TOP_ER1BEG2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_4", + "CMT_TOP_LOGIC_OUTS_L_B17_4" + ], + [ + "CMT_FIFO_LH3_8", + "CMT_TOP_LH3_8" + ], + [ + "CMT_FIFO_L_FAN5_2", + "CMT_TOP_FAN5_2" + ], + [ + "CMT_FIFO_L_BYP7_0", + "CMT_TOP_BYP7_0" + ], + [ + "CMT_FIFO_L_IMUX43_10", + "CMT_TOP_IMUX43_10" + ], + [ + "CMT_FIFO_L_IMUX5_9", + "CMT_TOP_IMUX5_9" + ], + [ + "CMT_FIFO_WW4C3_8", + "CMT_TOP_WW4C3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_8", + "CMT_TOP_LOGIC_OUTS_L_B15_8" + ], + [ + "CMT_FIFO_WW2A3_11", + "CMT_TOP_WW2A3_11" + ], + [ + "CMT_FIFO_WW4A0_8", + "CMT_TOP_WW4A0_8" + ], + [ + "CMT_FIFO_WW4END1_0", + "CMT_TOP_WW4END1_0" + ], + [ + "CMT_FIFO_WW4END2_2", + "CMT_TOP_WW4END2_2" + ], + [ + "CMT_FIFO_WW4END3_4", + "CMT_TOP_WW4END3_4" + ], + [ + "CMT_FIFO_EE4BEG3_9", + "CMT_TOP_EE4BEG3_9" + ], + [ + "CMT_FIFO_SW4A1_3", + "CMT_TOP_SW4A1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_4", + "CMT_TOP_LOGIC_OUTS_L_B9_4" + ], + [ + "CMT_FIFO_L_FAN6_1", + "CMT_TOP_FAN6_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_11", + "CMT_TOP_LOGIC_OUTS_L_B1_11" + ], + [ + "CMT_FIFO_L_IMUX14_1", + "CMT_TOP_IMUX14_1" + ], + [ + "CMT_FIFO_EL1BEG2_8", + "CMT_TOP_EL1BEG2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "CMT_TOP_ICLK_1" + ], + [ + "CMT_FIFO_SW4A2_5", + "CMT_TOP_SW4A2_5" + ], + [ + "CMT_FIFO_L_BYP6_8", + "CMT_TOP_BYP6_8" + ], + [ + "CMT_FIFO_EE4BEG3_0", + "CMT_TOP_EE4BEG3_0" + ], + [ + "CMT_FIFO_L_CTRL0_2", + "CMT_TOP_CTRL0_2" + ], + [ + "CMT_FIFO_WL1END3_4", + "CMT_TOP_WL1END3_4" + ], + [ + "CMT_FIFO_L_IMUX9_7", + "CMT_TOP_IMUX9_7" + ], + [ + "CMT_FIFO_L_BYP6_1", + "CMT_TOP_BYP6_1" + ], + [ + "CMT_FIFO_L_IMUX18_2", + "CMT_TOP_IMUX18_2" + ], + [ + "CMT_FIFO_EL1BEG2_7", + "CMT_TOP_EL1BEG2_7" + ], + [ + "CMT_FIFO_L_IMUX16_5", + "CMT_TOP_IMUX16_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_1", + "CMT_TOP_LOGIC_OUTS_L_B11_1" + ], + [ + "CMT_FIFO_LH2_6", + "CMT_TOP_LH2_6" + ], + [ + "CMT_FIFO_NE4C1_2", + "CMT_TOP_NE4C1_2" + ], + [ + "CMT_FIFO_NE2A0_2", + "CMT_TOP_NE2A0_2" + ], + [ + "CMT_FIFO_SW4END3_9", + "CMT_TOP_SW4END3_9" + ], + [ + "CMT_FIFO_SW4A0_7", + "CMT_TOP_SW4A0_7" + ], + [ + "CMT_FIFO_EL1BEG0_10", + "CMT_TOP_EL1BEG0_10" + ], + [ + "CMT_FIFO_ER1BEG2_10", + "CMT_TOP_ER1BEG2_10" + ], + [ + "CMT_FIFO_WW4C1_9", + "CMT_TOP_WW4C1_9" + ], + [ + "CMT_FIFO_LH7_0", + "CMT_TOP_LH7_0" + ], + [ + "CMT_FIFO_WW2A0_9", + "CMT_TOP_WW2A0_9" + ], + [ + "CMT_FIFO_NE2A2_0", + "CMT_TOP_NE2A2_0" + ], + [ + "CMT_FIFO_L_IMUX0_5", + "CMT_TOP_IMUX0_5" + ], + [ + "CMT_FIFO_L_IMUX24_10", + "CMT_TOP_IMUX24_10" + ], + [ + "CMT_FIFO_ER1BEG3_3", + "CMT_TOP_ER1BEG3_3" + ], + [ + "CMT_FIFO_L_FAN4_4", + "CMT_TOP_FAN4_4" + ], + [ + "CMT_FIFO_LH12_6", + "CMT_TOP_LH12_6" + ], + [ + "CMT_FIFO_SW2A0_10", + "CMT_TOP_SW2A0_10" + ], + [ + "CMT_FIFO_L_IMUX24_1", + "CMT_TOP_IMUX24_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "CMT_TOP_ICLKDIV_2" + ], + [ + "CMT_FIFO_L_IMUX47_8", + "CMT_TOP_IMUX47_8" + ], + [ + "CMT_FIFO_SW2A3_2", + "CMT_TOP_SW2A3_2" + ], + [ + "CMT_FIFO_L_IMUX26_6", + "CMT_TOP_IMUX26_6" + ], + [ + "CMT_FIFO_WW4C0_11", + "CMT_TOP_WW4C0_11" + ], + [ + "CMT_FIFO_L_FAN3_8", + "CMT_TOP_FAN3_8" + ], + [ + "CMT_FIFO_SW2A3_9", + "CMT_TOP_SW2A3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_10", + "CMT_TOP_LOGIC_OUTS_L_B20_10" + ], + [ + "CMT_FIFO_L_BYP5_1", + "CMT_TOP_BYP5_1" + ], + [ + "CMT_FIFO_SE4C3_8", + "CMT_TOP_SE4C3_8" + ], + [ + "CMT_FIFO_WW4B1_10", + "CMT_TOP_WW4B1_10" + ], + [ + "CMT_FIFO_WW2A3_7", + "CMT_TOP_WW2A3_7" + ], + [ + "CMT_FIFO_L_BYP0_0", + "CMT_TOP_BYP0_0" + ], + [ + "CMT_FIFO_L_IMUX36_5", + "CMT_TOP_IMUX36_5" + ], + [ + "CMT_FIFO_L_FAN6_6", + "CMT_TOP_FAN6_6" + ], + [ + "CMT_FIFO_WW4A3_3", + "CMT_TOP_WW4A3_3" + ], + [ + "CMT_FIFO_L_IMUX31_5", + "CMT_TOP_IMUX31_5" + ], + [ + "CMT_FIFO_L_FAN1_4", + "CMT_TOP_FAN1_4" + ], + [ + "CMT_FIFO_WW2END3_11", + "CMT_TOP_WW2END3_11" + ], + [ + "CMT_FIFO_L_CLK1_10", + "CMT_TOP_CLK1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_3", + "CMT_TOP_LOGIC_OUTS_L_B15_3" + ], + [ + "CMT_FIFO_ER1BEG3_6", + "CMT_TOP_ER1BEG3_6" + ], + [ + "CMT_FIFO_NW4END3_3", + "CMT_TOP_NW4END3_3" + ], + [ + "CMT_FIFO_WR1END1_8", + "CMT_TOP_WR1END1_8" + ], + [ + "CMT_FIFO_WW4B2_6", + "CMT_TOP_WW4B2_6" + ], + [ + "CMT_FIFO_L_FAN5_6", + "CMT_TOP_FAN5_6" + ], + [ + "CMT_FIFO_NW4END2_9", + "CMT_TOP_NW4END2_9" + ], + [ + "CMT_FIFO_WW2A2_8", + "CMT_TOP_WW2A2_8" + ], + [ + "CMT_FIFO_NE2A0_8", + "CMT_TOP_NE2A0_8" + ], + [ + "CMT_FIFO_EE4C0_4", + "CMT_TOP_EE4C0_4" + ], + [ + "CMT_FIFO_LH9_2", + "CMT_TOP_LH9_2" + ], + [ + "CMT_FIFO_EL1BEG1_11", + "CMT_TOP_EL1BEG1_11" + ], + [ + "CMT_FIFO_L_IMUX5_7", + "CMT_TOP_IMUX5_7" + ], + [ + "CMT_FIFO_L_IMUX5_3", + "CMT_TOP_IMUX5_3" + ], + [ + "CMT_FIFO_LH2_3", + "CMT_TOP_LH2_3" + ], + [ + "CMT_FIFO_EE2A3_4", + "CMT_TOP_EE2A3_4" + ], + [ + "CMT_FIFO_EL1BEG3_6", + "CMT_TOP_EL1BEG3_6" + ], + [ + "CMT_FIFO_L_BYP5_3", + "CMT_TOP_BYP5_3" + ], + [ + "CMT_FIFO_L_IMUX7_8", + "CMT_TOP_IMUX7_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_7", + "CMT_TOP_LOGIC_OUTS_L_B2_7" + ], + [ + "CMT_FIFO_EE4A0_7", + "CMT_TOP_EE4A0_7" + ], + [ + "CMT_FIFO_L_IMUX30_10", + "CMT_TOP_IMUX30_10" + ], + [ + "CMT_FIFO_WW2END1_4", + "CMT_TOP_WW2END1_4" + ], + [ + "CMT_FIFO_WW4END2_4", + "CMT_TOP_WW4END2_4" + ], + [ + "CMT_FIFO_L_FAN5_10", + "CMT_TOP_FAN5_10" + ], + [ + "CMT_FIFO_L_IMUX9_0", + "CMT_TOP_IMUX9_0" + ], + [ + "CMT_FIFO_WL1END1_2", + "CMT_TOP_WL1END1_2" + ], + [ + "CMT_FIFO_NE2A2_1", + "CMT_TOP_NE2A2_1" + ], + [ + "CMT_FIFO_L_FAN6_8", + "CMT_TOP_FAN6_8" + ], + [ + "CMT_FIFO_L_IMUX21_3", + "CMT_TOP_IMUX21_3" + ], + [ + "CMT_FIFO_WW2END0_1", + "CMT_TOP_WW2END0_1" + ], + [ + "CMT_FIFO_LH2_8", + "CMT_TOP_LH2_8" + ], + [ + "CMT_FIFO_L_IMUX27_9", + "CMT_TOP_IMUX27_9" + ], + [ + "CMT_FIFO_SW4END1_1", + "CMT_TOP_SW4END1_1" + ], + [ + "CMT_FIFO_EE2A0_4", + "CMT_TOP_EE2A0_4" + ], + [ + "CMT_FIFO_WW4END0_10", + "CMT_TOP_WW4END0_10" + ], + [ + "CMT_FIFO_L_IMUX7_2", + "CMT_TOP_IMUX7_2" + ], + [ + "CMT_FIFO_NW4A0_6", + "CMT_TOP_NW4A0_6" + ], + [ + "CMT_FIFO_L_IMUX42_0", + "CMT_TOP_IMUX42_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_10" + ], + [ + "CMT_FIFO_L_BYP4_4", + "CMT_TOP_BYP4_4" + ], + [ + "CMT_FIFO_SE2A2_3", + "CMT_TOP_SE2A2_3" + ], + [ + "CMT_FIFO_NE2A1_9", + "CMT_TOP_NE2A1_9" + ], + [ + "CMT_FIFO_WW2A0_3", + "CMT_TOP_WW2A0_3" + ], + [ + "CMT_FIFO_L_IMUX9_5", + "CMT_TOP_IMUX9_5" + ], + [ + "CMT_FIFO_NE4C1_8", + "CMT_TOP_NE4C1_8" + ], + [ + "CMT_FIFO_WL1END0_2", + "CMT_TOP_WL1END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_3", + "CMT_TOP_LOGIC_OUTS_L_B4_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_2", + "CMT_TOP_LOGIC_OUTS_L_B8_2" + ], + [ + "CMT_FIFO_L_FAN4_6", + "CMT_TOP_FAN4_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_3", + "CMT_TOP_LOGIC_OUTS_L_B23_3" + ], + [ + "CMT_FIFO_L_IMUX16_9", + "CMT_TOP_IMUX16_9" + ], + [ + "CMT_FIFO_SE2A1_9", + "CMT_TOP_SE2A1_9" + ], + [ + "CMT_FIFO_NW4END1_7", + "CMT_TOP_NW4END1_7" + ], + [ + "CMT_FIFO_SE2A2_10", + "CMT_TOP_SE2A2_10" + ], + [ + "CMT_FIFO_L_IMUX25_10", + "CMT_TOP_IMUX25_10" + ], + [ + "CMT_FIFO_L_BYP4_9", + "CMT_TOP_BYP4_9" + ], + [ + "CMT_FIFO_EE2BEG2_11", + "CMT_TOP_EE2BEG2_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_6", + "CMT_TOP_LOGIC_OUTS_L_B6_6" + ], + [ + "CMT_FIFO_WW2END1_1", + "CMT_TOP_WW2END1_1" + ], + [ + "CMT_FIFO_WW2END3_6", + "CMT_TOP_WW2END3_6" + ], + [ + "CMT_FIFO_L_CLK1_7", + "CMT_TOP_CLK1_7" + ], + [ + "CMT_FIFO_SE4BEG3_10", + "CMT_TOP_SE4BEG3_10" + ], + [ + "CMT_FIFO_SW4A1_1", + "CMT_TOP_SW4A1_1" + ], + [ + "CMT_FIFO_LH8_3", + "CMT_TOP_LH8_3" + ], + [ + "CMT_FIFO_WW4A1_9", + "CMT_TOP_WW4A1_9" + ], + [ + "CMT_FIFO_L_IMUX45_1", + "CMT_TOP_IMUX45_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_2", + "CMT_TOP_LOGIC_OUTS_L_B18_2" + ], + [ + "CMT_FIFO_L_IMUX28_10", + "CMT_TOP_IMUX28_10" + ], + [ + "CMT_FIFO_SE4C0_0", + "CMT_TOP_SE4C0_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "CMT_TOP_OCLK_2" + ], + [ + "CMT_FIFO_L_IMUX21_11", + "CMT_TOP_IMUX21_11" + ], + [ + "CMT_FIFO_NE4BEG1_0", + "CMT_TOP_NE4BEG1_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_7", + "CMT_TOP_LOGIC_OUTS_L_B15_7" + ], + [ + "CMT_FIFO_SW4END1_11", + "CMT_TOP_SW4END1_11" + ], + [ + "CMT_FIFO_NE4C2_7", + "CMT_TOP_NE4C2_7" + ], + [ + "CMT_FIFO_SE4C2_4", + "CMT_TOP_SE4C2_4" + ], + [ + "CMT_FIFO_SW4A3_4", + "CMT_TOP_SW4A3_4" + ], + [ + "CMT_FIFO_ER1BEG1_0", + "CMT_TOP_ER1BEG1_0" + ], + [ + "CMT_FIFO_NW4A2_3", + "CMT_TOP_NW4A2_3" + ], + [ + "CMT_FIFO_WW4A1_0", + "CMT_TOP_WW4A1_0" + ], + [ + "CMT_FIFO_EL1BEG1_9", + "CMT_TOP_EL1BEG1_9" + ], + [ + "CMT_FIFO_L_IMUX34_11", + "CMT_TOP_IMUX34_11" + ], + [ + "CMT_FIFO_SW2A0_0", + "CMT_TOP_SW2A0_0" + ], + [ + "CMT_FIFO_SE4BEG1_5", + "CMT_TOP_SE4BEG1_5" + ], + [ + "CMT_FIFO_NW4END0_6", + "CMT_TOP_NW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX23_2", + "CMT_TOP_IMUX23_2" + ], + [ + "CMT_FIFO_L_IMUX1_11", + "CMT_TOP_IMUX1_11" + ], + [ + "CMT_FIFO_WW4END1_1", + "CMT_TOP_WW4END1_1" + ], + [ + "CMT_FIFO_EE2BEG3_7", + "CMT_TOP_EE2BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX33_5", + "CMT_TOP_IMUX33_5" + ], + [ + "CMT_FIFO_WW4B3_3", + "CMT_TOP_WW4B3_3" + ], + [ + "CMT_FIFO_L_FAN5_0", + "CMT_TOP_FAN5_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_6", + "CMT_TOP_LOGIC_OUTS_L_B17_6" + ], + [ + "CMT_FIFO_WW4END2_8", + "CMT_TOP_WW4END2_8" + ], + [ + "CMT_FIFO_L_BYP0_1", + "CMT_TOP_BYP0_1" + ], + [ + "CMT_FIFO_WL1END3_7", + "CMT_TOP_WL1END3_7" + ], + [ + "CMT_FIFO_L_IMUX39_9", + "CMT_TOP_IMUX39_9" + ], + [ + "CMT_FIFO_WR1END3_6", + "CMT_TOP_WR1END3_6" + ], + [ + "CMT_FIFO_SE4C3_1", + "CMT_TOP_SE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX33_7", + "CMT_TOP_IMUX33_7" + ], + [ + "CMT_FIFO_L_BYP4_11", + "CMT_TOP_BYP4_11" + ], + [ + "CMT_FIFO_L_IMUX32_6", + "CMT_TOP_IMUX32_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "CMT_TOP_OCLKDIV_2" + ], + [ + "CMT_FIFO_L_IMUX33_11", + "CMT_TOP_IMUX33_11" + ], + [ + "CMT_FIFO_SE2A3_4", + "CMT_TOP_SE2A3_4" + ], + [ + "CMT_FIFO_L_IMUX44_2", + "CMT_TOP_IMUX44_2" + ], + [ + "CMT_FIFO_NE4C3_5", + "CMT_TOP_NE4C3_5" + ], + [ + "CMT_FIFO_EE4B1_4", + "CMT_TOP_EE4B1_4" + ], + [ + "CMT_FIFO_SW2A2_11", + "CMT_TOP_SW2A2_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_0", + "CMT_TOP_LOGIC_OUTS_L_B22_0" + ], + [ + "CMT_FIFO_WW4C3_9", + "CMT_TOP_WW4C3_9" + ], + [ + "CMT_FIFO_EE2BEG0_11", + "CMT_TOP_EE2BEG0_11" + ], + [ + "CMT_FIFO_ER1BEG0_0", + "CMT_TOP_ER1BEG0_0" + ], + [ + "CMT_FIFO_NW4END2_8", + "CMT_TOP_NW4END2_8" + ], + [ + "CMT_FIFO_L_IMUX25_3", + "CMT_TOP_IMUX25_3" + ], + [ + "CMT_FIFO_NW4A0_2", + "CMT_TOP_NW4A0_2" + ], + [ + "CMT_FIFO_SE4C1_0", + "CMT_TOP_SE4C1_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_8", + "CMT_TOP_LOGIC_OUTS_L_B1_8" + ], + [ + "CMT_FIFO_WW4A1_7", + "CMT_TOP_WW4A1_7" + ], + [ + "CMT_FIFO_L_IMUX21_1", + "CMT_TOP_IMUX21_1" + ], + [ + "CMT_FIFO_LH11_2", + "CMT_TOP_LH11_2" + ], + [ + "CMT_FIFO_SE2A1_8", + "CMT_TOP_SE2A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_4", + "CMT_TOP_LOGIC_OUTS_L_B13_4" + ], + [ + "CMT_FIFO_WW4END3_1", + "CMT_TOP_WW4END3_1" + ], + [ + "CMT_FIFO_L_BYP1_6", + "CMT_TOP_BYP1_6" + ], + [ + "CMT_FIFO_LH7_7", + "CMT_TOP_LH7_7" + ], + [ + "CMT_FIFO_EE4BEG0_0", + "CMT_TOP_EE4BEG0_0" + ], + [ + "CMT_FIFO_NE4BEG2_11", + "CMT_TOP_NE4BEG2_11" + ], + [ + "CMT_FIFO_WW4A2_9", + "CMT_TOP_WW4A2_9" + ], + [ + "CMT_FIFO_L_IMUX29_6", + "CMT_TOP_IMUX29_6" + ], + [ + "CMT_FIFO_WW2A2_2", + "CMT_TOP_WW2A2_2" + ], + [ + "CMT_FIFO_L_BYP0_2", + "CMT_TOP_BYP0_2" + ], + [ + "CMT_FIFO_NE4BEG1_6", + "CMT_TOP_NE4BEG1_6" + ], + [ + "CMT_FIFO_NW2A1_4", + "CMT_TOP_NW2A1_4" + ], + [ + "CMT_FIFO_L_IMUX2_11", + "CMT_TOP_IMUX2_11" + ], + [ + "CMT_FIFO_WW4A3_9", + "CMT_TOP_WW4A3_9" + ], + [ + "CMT_FIFO_SW2A0_7", + "CMT_TOP_SW2A0_7" + ], + [ + "CMT_FIFO_L_FAN0_8", + "CMT_TOP_FAN0_8" + ], + [ + "CMT_FIFO_NE4BEG3_5", + "CMT_TOP_NE4BEG3_5" + ], + [ + "CMT_FIFO_LH5_1", + "CMT_TOP_LH5_1" + ], + [ + "CMT_FIFO_SE4BEG0_4", + "CMT_TOP_SE4BEG0_4" + ], + [ + "CMT_FIFO_WW4END1_3", + "CMT_TOP_WW4END1_3" + ], + [ + "CMT_FIFO_NE2A1_8", + "CMT_TOP_NE2A1_8" + ], + [ + "CMT_FIFO_L_IMUX8_2", + "CMT_TOP_IMUX8_2" + ], + [ + "CMT_FIFO_SE2A0_8", + "CMT_TOP_SE2A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_6", + "CMT_TOP_LOGIC_OUTS_L_B8_6" + ], + [ + "CMT_FIFO_L_BYP3_0", + "CMT_TOP_BYP3_0" + ], + [ + "CMT_FIFO_EE2BEG0_6", + "CMT_TOP_EE2BEG0_6" + ], + [ + "CMT_FIFO_EL1BEG2_9", + "CMT_TOP_EL1BEG2_9" + ], + [ + "CMT_FIFO_EE4B2_9", + "CMT_TOP_EE4B2_9" + ], + [ + "CMT_FIFO_SE4C3_4", + "CMT_TOP_SE4C3_4" + ], + [ + "CMT_FIFO_L_IMUX30_1", + "CMT_TOP_IMUX30_1" + ], + [ + "CMT_FIFO_L_BYP4_0", + "CMT_TOP_BYP4_0" + ], + [ + "CMT_FIFO_L_IMUX34_10", + "CMT_TOP_IMUX34_10" + ], + [ + "CMT_FIFO_SW2A0_6", + "CMT_TOP_SW2A0_6" + ], + [ + "CMT_FIFO_NW4A3_4", + "CMT_TOP_NW4A3_4" + ], + [ + "CMT_FIFO_L_IMUX17_3", + "CMT_TOP_IMUX17_3" + ], + [ + "CMT_FIFO_WW2END0_5", + "CMT_TOP_WW2END0_5" + ], + [ + "CMT_FIFO_EE2BEG2_0", + "CMT_TOP_EE2BEG2_0" + ], + [ + "CMT_FIFO_WR1END3_10", + "CMT_TOP_WR1END3_10" + ], + [ + "CMT_FIFO_L_IMUX41_1", + "CMT_TOP_IMUX41_1" + ], + [ + "CMT_FIFO_EE4A0_10", + "CMT_TOP_EE4A0_10" + ], + [ + "CMT_FIFO_EE4B1_9", + "CMT_TOP_EE4B1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_3", + "CMT_TOP_LOGIC_OUTS_L_B11_3" + ], + [ + "CMT_FIFO_NW2A0_0", + "CMT_TOP_NW2A0_0" + ], + [ + "CMT_FIFO_L_IMUX26_11", + "CMT_TOP_IMUX26_11" + ], + [ + "CMT_FIFO_L_IMUX2_10", + "CMT_TOP_IMUX2_10" + ], + [ + "CMT_FIFO_L_IMUX5_4", + "CMT_TOP_IMUX5_4" + ], + [ + "CMT_FIFO_SW4END3_10", + "CMT_TOP_SW4END3_10" + ], + [ + "CMT_FIFO_WW4C2_2", + "CMT_TOP_WW4C2_2" + ], + [ + "CMT_FIFO_SE4BEG1_7", + "CMT_TOP_SE4BEG1_7" + ], + [ + "CMT_FIFO_SW4A1_5", + "CMT_TOP_SW4A1_5" + ], + [ + "CMT_FIFO_SW2A0_11", + "CMT_TOP_SW2A0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_3", + "CMT_TOP_LOGIC_OUTS_L_B13_3" + ], + [ + "CMT_FIFO_L_IMUX29_5", + "CMT_TOP_IMUX29_5" + ], + [ + "CMT_FIFO_L_FAN6_3", + "CMT_TOP_FAN6_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_4", + "CMT_TOP_LOGIC_OUTS_L_B23_4" + ], + [ + "CMT_FIFO_L_IMUX25_5", + "CMT_TOP_IMUX25_5" + ], + [ + "CMT_FIFO_SE4C0_2", + "CMT_TOP_SE4C0_2" + ], + [ + "CMT_FIFO_WW2A2_10", + "CMT_TOP_WW2A2_10" + ], + [ + "CMT_FIFO_L_CLK1_1", + "CMT_TOP_CLK1_1" + ], + [ + "CMT_FIFO_L_IMUX0_0", + "CMT_TOP_IMUX0_0" + ], + [ + "CMT_FIFO_L_IMUX29_11", + "CMT_TOP_IMUX29_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "CMT_TOP_ICLKDIV_7" + ], + [ + "CMT_FIFO_L_FAN6_4", + "CMT_TOP_FAN6_4" + ], + [ + "CMT_FIFO_NE4BEG1_10", + "CMT_TOP_NE4BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX0_8", + "CMT_TOP_IMUX0_8" + ], + [ + "CMT_FIFO_L_IMUX34_1", + "CMT_TOP_IMUX34_1" + ], + [ + "CMT_FIFO_EL1BEG2_3", + "CMT_TOP_EL1BEG2_3" + ], + [ + "CMT_FIFO_SW2A0_9", + "CMT_TOP_SW2A0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_1", + "CMT_TOP_LOGIC_OUTS_L_B0_1" + ], + [ + "CMT_FIFO_WW4A2_11", + "CMT_TOP_WW4A2_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "CMT_TOP_OCLKDIV_0" + ], + [ + "CMT_FIFO_NW4A1_10", + "CMT_TOP_NW4A1_10" + ], + [ + "CMT_FIFO_LH11_7", + "CMT_TOP_LH11_7" + ], + [ + "CMT_FIFO_NE4C3_11", + "CMT_TOP_NE4C3_11" + ], + [ + "CMT_FIFO_L_IMUX23_0", + "CMT_TOP_IMUX23_0" + ], + [ + "CMT_FIFO_NW4A3_6", + "CMT_TOP_NW4A3_6" + ], + [ + "CMT_FIFO_SW2A2_9", + "CMT_TOP_SW2A2_9" + ], + [ + "CMT_FIFO_L_FAN3_2", + "CMT_TOP_FAN3_2" + ], + [ + "CMT_FIFO_WL1END1_3", + "CMT_TOP_WL1END1_3" + ], + [ + "CMT_FIFO_L_IMUX12_0", + "CMT_TOP_IMUX12_0" + ], + [ + "CMT_FIFO_WW4C0_2", + "CMT_TOP_WW4C0_2" + ], + [ + "CMT_FIFO_NW4A2_7", + "CMT_TOP_NW4A2_7" + ], + [ + "CMT_FIFO_ER1BEG1_3", + "CMT_TOP_ER1BEG1_3" + ], + [ + "CMT_FIFO_WW4C1_4", + "CMT_TOP_WW4C1_4" + ], + [ + "CMT_FIFO_WW4END3_3", + "CMT_TOP_WW4END3_3" + ], + [ + "CMT_FIFO_EE4A1_5", + "CMT_TOP_EE4A1_5" + ], + [ + "CMT_FIFO_SE2A2_7", + "CMT_TOP_SE2A2_7" + ], + [ + "CMT_FIFO_NW2A1_0", + "CMT_TOP_NW2A1_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "CMT_TOP_OCLK1X_90_7" + ], + [ + "CMT_FIFO_L_CTRL1_5", + "CMT_TOP_CTRL1_5" + ], + [ + "FIFO_DQS_IOTOPHASER_1", + "CMT_PLL_DQS_TO_PHASER_D" + ], + [ + "CMT_FIFO_WW4B0_11", + "CMT_TOP_WW4B0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_6", + "CMT_TOP_LOGIC_OUTS_L_B7_6" + ], + [ + "CMT_FIFO_L_IMUX34_3", + "CMT_TOP_IMUX34_3" + ], + [ + "CMT_FIFO_WW2A1_3", + "CMT_TOP_WW2A1_3" + ], + [ + "CMT_FIFO_EL1BEG3_7", + "CMT_TOP_EL1BEG3_7" + ], + [ + "CMT_FIFO_EE2BEG2_4", + "CMT_TOP_EE2BEG2_4" + ], + [ + "CMT_FIFO_LH10_11", + "CMT_TOP_LH10_11" + ], + [ + "CMT_FIFO_SW2A1_0", + "CMT_TOP_SW2A1_0" + ], + [ + "CMT_FIFO_L_IMUX15_9", + "CMT_TOP_IMUX15_9" + ], + [ + "CMT_FIFO_L_IMUX1_4", + "CMT_TOP_IMUX1_4" + ], + [ + "CMT_FIFO_L_IMUX22_7", + "CMT_TOP_IMUX22_7" + ], + [ + "CMT_FIFO_EE4A0_11", + "CMT_TOP_EE4A0_11" + ], + [ + "CMT_FIFO_WL1END2_3", + "CMT_TOP_WL1END2_3" + ], + [ + "CMT_FIFO_EE2BEG3_1", + "CMT_TOP_EE2BEG3_1" + ], + [ + "CMT_FIFO_EE2A2_1", + "CMT_TOP_EE2A2_1" + ], + [ + "CMT_FIFO_NW4END2_1", + "CMT_TOP_NW4END2_1" + ], + [ + "CMT_FIFO_L_IMUX16_7", + "CMT_TOP_IMUX16_7" + ], + [ + "CMT_FIFO_SW4A2_2", + "CMT_TOP_SW4A2_2" + ], + [ + "CMT_FIFO_LH11_9", + "CMT_TOP_LH11_9" + ], + [ + "CMT_FIFO_ER1BEG2_9", + "CMT_TOP_ER1BEG2_9" + ], + [ + "CMT_FIFO_LH6_2", + "CMT_TOP_LH6_2" + ], + [ + "CMT_FIFO_SE4C1_5", + "CMT_TOP_SE4C1_5" + ], + [ + "CMT_FIFO_L_IMUX2_2", + "CMT_TOP_IMUX2_2" + ], + [ + "CMT_FIFO_NE4C3_8", + "CMT_TOP_NE4C3_8" + ], + [ + "CMT_FIFO_WR1END0_11", + "CMT_TOP_WR1END0_11" + ], + [ + "CMT_FIFO_L_IMUX25_2", + "CMT_TOP_IMUX25_2" + ], + [ + "CMT_FIFO_SW4END0_2", + "CMT_TOP_SW4END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_7", + "CMT_TOP_LOGIC_OUTS_L_B5_7" + ], + [ + "CMT_FIFO_L_IMUX32_1", + "CMT_TOP_IMUX32_1" + ], + [ + "CMT_FIFO_L_IMUX41_5", + "CMT_TOP_IMUX41_5" + ], + [ + "CMT_FIFO_EE4C1_0", + "CMT_TOP_EE4C1_0" + ], + [ + "CMT_FIFO_EE4C0_6", + "CMT_TOP_EE4C0_6" + ], + [ + "CMT_FIFO_WW2A3_1", + "CMT_TOP_WW2A3_1" + ], + [ + "CMT_FIFO_NE4C2_1", + "CMT_TOP_NE4C2_1" + ], + [ + "CMT_FIFO_NW2A3_0", + "CMT_TOP_NW2A3_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "CMT_TOP_OCLK_7" + ], + [ + "CMT_FIFO_L_IMUX15_6", + "CMT_TOP_IMUX15_6" + ], + [ + "CMT_FIFO_EE2A0_3", + "CMT_TOP_EE2A0_3" + ], + [ + "CMT_FIFO_EE4BEG1_11", + "CMT_TOP_EE4BEG1_11" + ], + [ + "CMT_FIFO_LH7_5", + "CMT_TOP_LH7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_7", + "CMT_TOP_LOGIC_OUTS_L_B20_7" + ], + [ + "CMT_FIFO_SE4BEG0_8", + "CMT_TOP_SE4BEG0_8" + ], + [ + "CMT_FIFO_EE4C1_4", + "CMT_TOP_EE4C1_4" + ], + [ + "CMT_FIFO_NW2A2_1", + "CMT_TOP_NW2A2_1" + ], + [ + "CMT_FIFO_ER1BEG3_9", + "CMT_TOP_ER1BEG3_9" + ], + [ + "CMT_FIFO_EE4A3_0", + "CMT_TOP_EE4A3_0" + ], + [ + "CMT_FIFO_L_IMUX3_9", + "CMT_TOP_IMUX3_9" + ], + [ + "CMT_FIFO_EE4C0_7", + "CMT_TOP_EE4C0_7" + ], + [ + "CMT_FIFO_L_BYP1_1", + "CMT_TOP_BYP1_1" + ], + [ + "CMT_FIFO_SE4BEG3_0", + "CMT_TOP_SE4BEG3_0" + ], + [ + "CMT_FIFO_L_IMUX31_2", + "CMT_TOP_IMUX31_2" + ], + [ + "CMT_FIFO_WW2END3_5", + "CMT_TOP_WW2END3_5" + ], + [ + "CMT_FIFO_L_IMUX1_10", + "CMT_TOP_IMUX1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_1", + "CMT_TOP_LOGIC_OUTS_L_B20_1" + ], + [ + "CMT_FIFO_EE4BEG2_3", + "CMT_TOP_EE4BEG2_3" + ], + [ + "CMT_FIFO_L_FAN1_5", + "CMT_TOP_FAN1_5" + ], + [ + "CMT_FIFO_L_IMUX34_0", + "CMT_TOP_IMUX34_0" + ], + [ + "CMT_FIFO_L_IMUX23_3", + "CMT_TOP_IMUX23_3" + ], + [ + "CMT_FIFO_L_IMUX27_8", + "CMT_TOP_IMUX27_8" + ], + [ + "CMT_FIFO_WW4C1_1", + "CMT_TOP_WW4C1_1" + ], + [ + "CMT_FIFO_NE4BEG1_5", + "CMT_TOP_NE4BEG1_5" + ], + [ + "CMT_FIFO_NE4BEG2_4", + "CMT_TOP_NE4BEG2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_5", + "CMT_TOP_LOGIC_OUTS_L_B5_5" + ], + [ + "CMT_FIFO_WW4A0_1", + "CMT_TOP_WW4A0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_1", + "CMT_TOP_LOGIC_OUTS_L_B4_1" + ], + [ + "CMT_FIFO_WW2A3_5", + "CMT_TOP_WW2A3_5" + ], + [ + "CMT_FIFO_WW4A0_6", + "CMT_TOP_WW4A0_6" + ], + [ + "CMT_FIFO_WW4C0_6", + "CMT_TOP_WW4C0_6" + ], + [ + "CMT_FIFO_SW4END1_4", + "CMT_TOP_SW4END1_4" + ], + [ + "CMT_FIFO_EE4A1_1", + "CMT_TOP_EE4A1_1" + ], + [ + "CMT_FIFO_LH4_7", + "CMT_TOP_LH4_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_7", + "CMT_TOP_LOGIC_OUTS_L_B7_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_9", + "CMT_TOP_LOGIC_OUTS_L_B23_9" + ], + [ + "CMT_FIFO_SE4C2_3", + "CMT_TOP_SE4C2_3" + ], + [ + "CMT_FIFO_NW4END1_1", + "CMT_TOP_NW4END1_1" + ], + [ + "CMT_FIFO_WW2END3_8", + "CMT_TOP_WW2END3_8" + ], + [ + "CMT_FIFO_NW2A2_4", + "CMT_TOP_NW2A2_4" + ], + [ + "CMT_FIFO_EE4BEG2_8", + "CMT_TOP_EE4BEG2_8" + ], + [ + "CMT_FIFO_NW2A3_5", + "CMT_TOP_NW2A3_5" + ], + [ + "CMT_FIFO_L_IMUX11_3", + "CMT_TOP_IMUX11_3" + ], + [ + "CMT_FIFO_WW4A0_0", + "CMT_TOP_WW4A0_0" + ], + [ + "CMT_FIFO_WW4END0_4", + "CMT_TOP_WW4END0_4" + ], + [ + "CMT_FIFO_L_IMUX39_4", + "CMT_TOP_IMUX39_4" + ], + [ + "CMT_FIFO_SE4C3_10", + "CMT_TOP_SE4C3_10" + ], + [ + "CMT_FIFO_L_IMUX22_8", + "CMT_TOP_IMUX22_8" + ], + [ + "CMT_FIFO_L_IMUX42_11", + "CMT_TOP_IMUX42_11" + ], + [ + "CMT_FIFO_WW2END3_1", + "CMT_TOP_WW2END3_1" + ], + [ + "CMT_FIFO_L_IMUX2_4", + "CMT_TOP_IMUX2_4" + ], + [ + "CMT_FIFO_L_BYP6_3", + "CMT_TOP_BYP6_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_4", + "CMT_TOP_LOGIC_OUTS_L_B7_4" + ], + [ + "CMT_FIFO_WW4A3_4", + "CMT_TOP_WW4A3_4" + ], + [ + "CMT_FIFO_L_IMUX7_3", + "CMT_TOP_IMUX7_3" + ], + [ + "CMT_FIFO_SW2A1_9", + "CMT_TOP_SW2A1_9" + ], + [ + "CMT_FIFO_L_IMUX18_6", + "CMT_TOP_IMUX18_6" + ], + [ + "CMT_FIFO_L_IMUX12_2", + "CMT_TOP_IMUX12_2" + ], + [ + "CMT_FIFO_LH12_2", + "CMT_TOP_LH12_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_3", + "CMT_TOP_LOGIC_OUTS_L_B8_3" + ], + [ + "CMT_FIFO_WW2END0_4", + "CMT_TOP_WW2END0_4" + ], + [ + "CMT_FIFO_L_IMUX22_3", + "CMT_TOP_IMUX22_3" + ], + [ + "CMT_FIFO_NE4BEG3_10", + "CMT_TOP_NE4BEG3_10" + ], + [ + "CMT_FIFO_LH11_5", + "CMT_TOP_LH11_5" + ], + [ + "CMT_FIFO_L_IMUX10_3", + "CMT_TOP_IMUX10_3" + ], + [ + "CMT_FIFO_LH3_10", + "CMT_TOP_LH3_10" + ], + [ + "CMT_FIFO_LH9_8", + "CMT_TOP_LH9_8" + ], + [ + "CMT_FIFO_NW4END2_11", + "CMT_TOP_NW4END2_11" + ], + [ + "CMT_FIFO_L_IMUX15_3", + "CMT_TOP_IMUX15_3" + ], + [ + "CMT_FIFO_L_IMUX47_11", + "CMT_TOP_IMUX47_11" + ], + [ + "CMT_FIFO_SE2A2_11", + "CMT_TOP_SE2A2_11" + ], + [ + "CMT_FIFO_EE4B1_5", + "CMT_TOP_EE4B1_5" + ], + [ + "CMT_FIFO_SE4BEG1_6", + "CMT_TOP_SE4BEG1_6" + ], + [ + "CMT_FIFO_LH6_6", + "CMT_TOP_LH6_6" + ], + [ + "CMT_FIFO_NE2A3_0", + "CMT_TOP_NE2A3_0" + ], + [ + "CMT_FIFO_L_BYP0_4", + "CMT_TOP_BYP0_4" + ], + [ + "CMT_FIFO_WW2END2_5", + "CMT_TOP_WW2END2_5" + ], + [ + "CMT_FIFO_EE4B3_6", + "CMT_TOP_EE4B3_6" + ], + [ + "CMT_FIFO_L_IMUX39_3", + "CMT_TOP_IMUX39_3" + ], + [ + "CMT_FIFO_L_FAN7_5", + "CMT_TOP_FAN7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_6", + "CMT_TOP_LOGIC_OUTS_L_B2_6" + ], + [ + "CMT_FIFO_WW2END0_2", + "CMT_TOP_WW2END0_2" + ], + [ + "CMT_FIFO_SE4C3_3", + "CMT_TOP_SE4C3_3" + ], + [ + "CMT_FIFO_NE4C3_1", + "CMT_TOP_NE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX40_3", + "CMT_TOP_IMUX40_3" + ], + [ + "CMT_FIFO_WW4A3_0", + "CMT_TOP_WW4A3_0" + ], + [ + "CMT_FIFO_L_IMUX37_10", + "CMT_TOP_IMUX37_10" + ], + [ + "CMT_FIFO_L_IMUX21_4", + "CMT_TOP_IMUX21_4" + ], + [ + "CMT_FIFO_SE4BEG0_11", + "CMT_TOP_SE4BEG0_11" + ], + [ + "CMT_FIFO_WW4B2_10", + "CMT_TOP_WW4B2_10" + ], + [ + "CMT_FIFO_EE4B1_11", + "CMT_TOP_EE4B1_11" + ], + [ + "CMT_FIFO_WW2A1_6", + "CMT_TOP_WW2A1_6" + ], + [ + "CMT_FIFO_NE2A0_10", + "CMT_TOP_NE2A0_10" + ], + [ + "CMT_FIFO_EE4B2_7", + "CMT_TOP_EE4B2_7" + ], + [ + "CMT_FIFO_SE4C0_10", + "CMT_TOP_SE4C0_10" + ], + [ + "CMT_FIFO_SE2A0_2", + "CMT_TOP_SE2A0_2" + ], + [ + "CMT_FIFO_NE4C1_4", + "CMT_TOP_NE4C1_4" + ], + [ + "CMT_FIFO_L_IMUX4_5", + "CMT_TOP_IMUX4_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_10" + ], + [ + "CMT_FIFO_L_IMUX26_5", + "CMT_TOP_IMUX26_5" + ], + [ + "CMT_FIFO_EE4A3_8", + "CMT_TOP_EE4A3_8" + ], + [ + "CMT_FIFO_L_IMUX38_7", + "CMT_TOP_IMUX38_7" + ], + [ + "CMT_FIFO_EL1BEG0_1", + "CMT_TOP_EL1BEG0_1" + ], + [ + "CMT_FIFO_L_IMUX33_10", + "CMT_TOP_IMUX33_10" + ], + [ + "CMT_FIFO_LH4_11", + "CMT_TOP_LH4_11" + ], + [ + "CMT_FIFO_L_IMUX37_6", + "CMT_TOP_IMUX37_6" + ], + [ + "CMT_FIFO_L_IMUX15_10", + "CMT_TOP_IMUX15_10" + ], + [ + "CMT_FIFO_EL1BEG1_8", + "CMT_TOP_EL1BEG1_8" + ], + [ + "CMT_FIFO_NE2A2_5", + "CMT_TOP_NE2A2_5" + ], + [ + "CMT_FIFO_SW2A2_4", + "CMT_TOP_SW2A2_4" + ], + [ + "CMT_FIFO_SW4END3_2", + "CMT_TOP_SW4END3_2" + ], + [ + "CMT_FIFO_L_IMUX31_9", + "CMT_TOP_IMUX31_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "CMT_TOP_OCLKDIV_7" + ], + [ + "CMT_FIFO_L_IMUX23_8", + "CMT_TOP_IMUX23_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_7", + "CMT_TOP_LOGIC_OUTS_L_B16_7" + ], + [ + "CMT_FIFO_EE4A2_3", + "CMT_TOP_EE4A2_3" + ], + [ + "CMT_FIFO_L_IMUX46_10", + "CMT_TOP_IMUX46_10" + ], + [ + "CMT_FIFO_MONITOR_N_4", + "CMT_TOP_MONITOR_N_4" + ], + [ + "CMT_FIFO_WW4A3_10", + "CMT_TOP_WW4A3_10" + ], + [ + "CMT_FIFO_SW4A2_11", + "CMT_TOP_SW4A2_11" + ], + [ + "CMT_FIFO_LH3_11", + "CMT_TOP_LH3_11" + ], + [ + "CMT_FIFO_L_IMUX33_3", + "CMT_TOP_IMUX33_3" + ], + [ + "CMT_FIFO_WR1END3_3", + "CMT_TOP_WR1END3_3" + ], + [ + "CMT_FIFO_WR1END2_4", + "CMT_TOP_WR1END2_4" + ], + [ + "CMT_FIFO_WW4B2_5", + "CMT_TOP_WW4B2_5" + ], + [ + "CMT_FIFO_L_FAN7_2", + "CMT_TOP_FAN7_2" + ], + [ + "CMT_FIFO_NW2A1_1", + "CMT_TOP_NW2A1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_1", + "CMT_TOP_LOGIC_OUTS_L_B12_1" + ], + [ + "CMT_FIFO_NW4A2_10", + "CMT_TOP_NW4A2_10" + ], + [ + "CMT_FIFO_WL1END2_5", + "CMT_TOP_WL1END2_5" + ], + [ + "CMT_FIFO_L_CLK0_7", + "CMT_TOP_CLK0_7" + ], + [ + "CMT_FIFO_L_IMUX28_2", + "CMT_TOP_IMUX28_2" + ], + [ + "CMT_FIFO_EL1BEG2_11", + "CMT_TOP_EL1BEG2_11" + ], + [ + "CMT_FIFO_WW4END3_10", + "CMT_TOP_WW4END3_10" + ], + [ + "CMT_FIFO_EE2BEG3_10", + "CMT_TOP_EE2BEG3_10" + ], + [ + "CMT_FIFO_ER1BEG2_4", + "CMT_TOP_ER1BEG2_4" + ], + [ + "CMT_FIFO_WW4END1_2", + "CMT_TOP_WW4END1_2" + ], + [ + "CMT_FIFO_L_FAN1_3", + "CMT_TOP_FAN1_3" + ], + [ + "CMT_FIFO_L_BYP6_9", + "CMT_TOP_BYP6_9" + ], + [ + "CMT_FIFO_L_BYP7_9", + "CMT_TOP_BYP7_9" + ], + [ + "CMT_FIFO_SW4A0_6", + "CMT_TOP_SW4A0_6" + ], + [ + "CMT_FIFO_L_FAN0_4", + "CMT_TOP_FAN0_4" + ], + [ + "CMT_FIFO_SW4A1_7", + "CMT_TOP_SW4A1_7" + ], + [ + "CMT_FIFO_L_IMUX11_2", + "CMT_TOP_IMUX11_2" + ], + [ + "CMT_FIFO_EE2A1_0", + "CMT_TOP_EE2A1_0" + ], + [ + "CMT_FIFO_LH12_9", + "CMT_TOP_LH12_9" + ], + [ + "CMT_FIFO_LH10_10", + "CMT_TOP_LH10_10" + ], + [ + "CMT_FIFO_L_IMUX39_7", + "CMT_TOP_IMUX39_7" + ], + [ + "CMT_FIFO_L_IMUX9_9", + "CMT_TOP_IMUX9_9" + ], + [ + "CMT_FIFO_NW2A0_10", + "CMT_TOP_NW2A0_10" + ], + [ + "CMT_FIFO_WW2A1_2", + "CMT_TOP_WW2A1_2" + ], + [ + "CMT_FIFO_SE4C1_8", + "CMT_TOP_SE4C1_8" + ], + [ + "CMT_FIFO_L_IMUX45_2", + "CMT_TOP_IMUX45_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_5", + "CMT_TOP_LOGIC_OUTS_L_B18_5" + ], + [ + "CMT_FIFO_SW4END2_7", + "CMT_TOP_SW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX31_8", + "CMT_TOP_IMUX31_8" + ], + [ + "CMT_FIFO_L_FAN2_11", + "CMT_TOP_FAN2_11" + ], + [ + "CMT_FIFO_NW4END1_8", + "CMT_TOP_NW4END1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_3" + ], + [ + "CMT_FIFO_L_IMUX0_3", + "CMT_TOP_IMUX0_3" + ], + [ + "CMT_FIFO_SE4BEG3_9", + "CMT_TOP_SE4BEG3_9" + ], + [ + "CMT_FIFO_ER1BEG0_1", + "CMT_TOP_ER1BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_9", + "CMT_TOP_LOGIC_OUTS_L_B2_9" + ], + [ + "CMT_FIFO_NE4C2_3", + "CMT_TOP_NE4C2_3" + ], + [ + "CMT_FIFO_LH1_6", + "CMT_TOP_LH1_6" + ], + [ + "CMT_FIFO_L_IMUX21_7", + "CMT_TOP_IMUX21_7" + ], + [ + "CMT_FIFO_SE2A2_8", + "CMT_TOP_SE2A2_8" + ], + [ + "CMT_FIFO_WW4A2_3", + "CMT_TOP_WW4A2_3" + ], + [ + "CMT_FIFO_SE4BEG1_0", + "CMT_TOP_SE4BEG1_0" + ], + [ + "CMT_FIFO_WR1END1_5", + "CMT_TOP_WR1END1_5" + ], + [ + "CMT_FIFO_WW2END2_7", + "CMT_TOP_WW2END2_7" + ], + [ + "CMT_FIFO_L_IMUX38_8", + "CMT_TOP_IMUX38_8" + ], + [ + "CMT_FIFO_LH5_9", + "CMT_TOP_LH5_9" + ], + [ + "CMT_FIFO_L_FAN4_10", + "CMT_TOP_FAN4_10" + ], + [ + "CMT_FIFO_NW4END1_5", + "CMT_TOP_NW4END1_5" + ], + [ + "CMT_FIFO_EE2A2_11", + "CMT_TOP_EE2A2_11" + ], + [ + "CMT_FIFO_SE2A0_9", + "CMT_TOP_SE2A0_9" + ], + [ + "CMT_FIFO_WW4B3_7", + "CMT_TOP_WW4B3_7" + ], + [ + "CMT_FIFO_L_FAN3_11", + "CMT_TOP_FAN3_11" + ], + [ + "CMT_FIFO_LH5_2", + "CMT_TOP_LH5_2" + ], + [ + "CMT_FIFO_SE4BEG1_1", + "CMT_TOP_SE4BEG1_1" + ], + [ + "CMT_FIFO_LH1_4", + "CMT_TOP_LH1_4" + ], + [ + "CMT_FIFO_EL1BEG0_4", + "CMT_TOP_EL1BEG0_4" + ], + [ + "CMT_FIFO_WW4B1_5", + "CMT_TOP_WW4B1_5" + ], + [ + "CMT_FIFO_LH7_2", + "CMT_TOP_LH7_2" + ], + [ + "CMT_FIFO_L_IMUX5_11", + "CMT_TOP_IMUX5_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_5", + "CMT_TOP_LOGIC_OUTS_L_B12_5" + ], + [ + "CMT_FIFO_EE4B0_4", + "CMT_TOP_EE4B0_4" + ], + [ + "CMT_FIFO_EE2BEG0_2", + "CMT_TOP_EE2BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX44_1", + "CMT_TOP_IMUX44_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_8", + "CMT_TOP_LOGIC_OUTS_L_B0_8" + ], + [ + "CMT_FIFO_L_IMUX13_10", + "CMT_TOP_IMUX13_10" + ], + [ + "CMT_FIFO_NE2A3_4", + "CMT_TOP_NE2A3_4" + ], + [ + "CMT_FIFO_ER1BEG2_5", + "CMT_TOP_ER1BEG2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_3" + ], + [ + "CMT_FIFO_EE4A3_6", + "CMT_TOP_EE4A3_6" + ], + [ + "CMT_FIFO_L_FAN1_2", + "CMT_TOP_FAN1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "CMT_TOP_OCLKDIV_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_8", + "CMT_TOP_LOGIC_OUTS_L_B10_8" + ], + [ + "CMT_FIFO_WW2END2_0", + "CMT_TOP_WW2END2_0" + ], + [ + "CMT_FIFO_NE4C2_8", + "CMT_TOP_NE4C2_8" + ], + [ + "CMT_FIFO_LH1_5", + "CMT_TOP_LH1_5" + ], + [ + "CMT_FIFO_NW2A3_9", + "CMT_TOP_NW2A3_9" + ], + [ + "CMT_FIFO_SE4BEG0_0", + "CMT_TOP_SE4BEG0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_9", + "CMT_TOP_LOGIC_OUTS_L_B9_9" + ], + [ + "CMT_FIFO_L_BYP0_5", + "CMT_TOP_BYP0_5" + ], + [ + "CMT_FIFO_L_IMUX27_3", + "CMT_TOP_IMUX27_3" + ], + [ + "CMT_FIFO_L_IMUX16_0", + "CMT_TOP_IMUX16_0" + ], + [ + "CMT_FIFO_NW4END2_2", + "CMT_TOP_NW4END2_2" + ], + [ + "CMT_FIFO_SW4A1_4", + "CMT_TOP_SW4A1_4" + ], + [ + "CMT_FIFO_WW4B3_11", + "CMT_TOP_WW4B3_11" + ], + [ + "CMT_FIFO_L_IMUX15_4", + "CMT_TOP_IMUX15_4" + ], + [ + "CMT_FIFO_WR1END2_3", + "CMT_TOP_WR1END2_3" + ], + [ + "CMT_FIFO_NW4END2_10", + "CMT_TOP_NW4END2_10" + ], + [ + "CMT_FIFO_WW4END3_9", + "CMT_TOP_WW4END3_9" + ], + [ + "CMT_FIFO_L_IMUX18_8", + "CMT_TOP_IMUX18_8" + ], + [ + "CMT_FIFO_L_FAN4_8", + "CMT_TOP_FAN4_8" + ], + [ + "CMT_FIFO_WW4A2_8", + "CMT_TOP_WW4A2_8" + ], + [ + "CMT_FIFO_L_IMUX35_4", + "CMT_TOP_IMUX35_4" + ], + [ + "CMT_FIFO_L_IMUX19_10", + "CMT_TOP_IMUX19_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_3" + ], + [ + "CMT_FIFO_L_IMUX22_0", + "CMT_TOP_IMUX22_0" + ], + [ + "CMT_FIFO_EE4B1_3", + "CMT_TOP_EE4B1_3" + ], + [ + "CMT_FIFO_NW2A1_10", + "CMT_TOP_NW2A1_10" + ], + [ + "CMT_FIFO_SE2A3_0", + "CMT_TOP_SE2A3_0" + ], + [ + "CMT_FIFO_SW4A0_9", + "CMT_TOP_SW4A0_9" + ], + [ + "CMT_FIFO_EE4A2_4", + "CMT_TOP_EE4A2_4" + ], + [ + "CMT_FIFO_EE2BEG0_7", + "CMT_TOP_EE2BEG0_7" + ], + [ + "CMT_FIFO_LH4_1", + "CMT_TOP_LH4_1" + ], + [ + "CMT_FIFO_L_IMUX8_6", + "CMT_TOP_IMUX8_6" + ], + [ + "CMT_FIFO_L_BYP1_3", + "CMT_TOP_BYP1_3" + ], + [ + "CMT_FIFO_L_FAN0_5", + "CMT_TOP_FAN0_5" + ], + [ + "CMT_FIFO_L_IMUX23_9", + "CMT_TOP_IMUX23_9" + ], + [ + "CMT_FIFO_EE4C2_6", + "CMT_TOP_EE4C2_6" + ], + [ + "CMT_FIFO_NW4END2_7", + "CMT_TOP_NW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX22_5", + "CMT_TOP_IMUX22_5" + ], + [ + "CMT_FIFO_EE2BEG0_9", + "CMT_TOP_EE2BEG0_9" + ], + [ + "CMT_FIFO_EE4B3_0", + "CMT_TOP_EE4B3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_5", + "CMT_TOP_LOGIC_OUTS_L_B7_5" + ], + [ + "CMT_FIFO_L_IMUX15_8", + "CMT_TOP_IMUX15_8" + ], + [ + "CMT_FIFO_NE4C1_3", + "CMT_TOP_NE4C1_3" + ], + [ + "CMT_FIFO_NE4BEG1_2", + "CMT_TOP_NE4BEG1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_7", + "CMT_TOP_LOGIC_OUTS_L_B19_7" + ], + [ + "CMT_FIFO_NW2A2_9", + "CMT_TOP_NW2A2_9" + ], + [ + "CMT_FIFO_SW2A1_7", + "CMT_TOP_SW2A1_7" + ], + [ + "CMT_FIFO_L_IMUX1_8", + "CMT_TOP_IMUX1_8" + ], + [ + "CMT_FIFO_L_IMUX30_5", + "CMT_TOP_IMUX30_5" + ], + [ + "CMT_FIFO_L_IMUX39_11", + "CMT_TOP_IMUX39_11" + ], + [ + "CMT_FIFO_SE4BEG2_6", + "CMT_TOP_SE4BEG2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_2", + "CMT_TOP_LOGIC_OUTS_L_B1_2" + ], + [ + "CMT_FIFO_LH7_9", + "CMT_TOP_LH7_9" + ], + [ + "CMT_FIFO_EE4C0_2", + "CMT_TOP_EE4C0_2" + ], + [ + "CMT_FIFO_L_IMUX46_1", + "CMT_TOP_IMUX46_1" + ], + [ + "CMT_FIFO_SW2A3_6", + "CMT_TOP_SW2A3_6" + ], + [ + "CMT_FIFO_NW4END3_4", + "CMT_TOP_NW4END3_4" + ], + [ + "CMT_FIFO_L_BYP2_6", + "CMT_TOP_BYP2_6" + ], + [ + "CMT_FIFO_L_CLK1_3", + "CMT_TOP_CLK1_3" + ], + [ + "CMT_FIFO_L_CLK0_8", + "CMT_TOP_CLK0_8" + ], + [ + "CMT_FIFO_SW2A1_8", + "CMT_TOP_SW2A1_8" + ], + [ + "CMT_FIFO_WW2END1_3", + "CMT_TOP_WW2END1_3" + ], + [ + "CMT_FIFO_EE4BEG1_10", + "CMT_TOP_EE4BEG1_10" + ], + [ + "CMT_FIFO_WW2END1_10", + "CMT_TOP_WW2END1_10" + ], + [ + "CMT_FIFO_SE2A0_7", + "CMT_TOP_SE2A0_7" + ], + [ + "CMT_FIFO_NE4C3_4", + "CMT_TOP_NE4C3_4" + ], + [ + "CMT_FIFO_SW4END1_6", + "CMT_TOP_SW4END1_6" + ], + [ + "CMT_FIFO_WW2END3_2", + "CMT_TOP_WW2END3_2" + ], + [ + "CMT_FIFO_EE2A1_1", + "CMT_TOP_EE2A1_1" + ], + [ + "CMT_FIFO_L_FAN1_1", + "CMT_TOP_FAN1_1" + ], + [ + "CMT_FIFO_LH9_10", + "CMT_TOP_LH9_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_7", + "CMT_TOP_LOGIC_OUTS_L_B13_7" + ], + [ + "CMT_FIFO_L_IMUX18_10", + "CMT_TOP_IMUX18_10" + ], + [ + "CMT_FIFO_L_IMUX10_9", + "CMT_TOP_IMUX10_9" + ], + [ + "CMT_FIFO_WW4B2_9", + "CMT_TOP_WW4B2_9" + ], + [ + "CMT_FIFO_L_BYP7_6", + "CMT_TOP_BYP7_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_8", + "CMT_TOP_LOGIC_OUTS_L_B22_8" + ], + [ + "CMT_FIFO_SE4BEG0_3", + "CMT_TOP_SE4BEG0_3" + ], + [ + "CMT_FIFO_LH7_1", + "CMT_TOP_LH7_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_8", + "CMT_TOP_LOGIC_OUTS_L_B4_8" + ], + [ + "CMT_FIFO_L_IMUX29_2", + "CMT_TOP_IMUX29_2" + ], + [ + "CMT_FIFO_NE4BEG1_4", + "CMT_TOP_NE4BEG1_4" + ], + [ + "CMT_FIFO_WW4END0_0", + "CMT_TOP_WW4END0_0" + ], + [ + "CMT_FIFO_NW4END1_6", + "CMT_TOP_NW4END1_6" + ], + [ + "CMT_FIFO_NW4A1_2", + "CMT_TOP_NW4A1_2" + ], + [ + "CMT_FIFO_LH8_2", + "CMT_TOP_LH8_2" + ], + [ + "CMT_FIFO_WL1END0_5", + "CMT_TOP_WL1END0_5" + ], + [ + "CMT_FIFO_SE2A2_1", + "CMT_TOP_SE2A2_1" + ], + [ + "CMT_FIFO_NE2A0_4", + "CMT_TOP_NE2A0_4" + ], + [ + "CMT_FIFO_L_IMUX18_11", + "CMT_TOP_IMUX18_11" + ], + [ + "CMT_FIFO_L_IMUX25_7", + "CMT_TOP_IMUX25_7" + ], + [ + "CMT_FIFO_NW4END0_4", + "CMT_TOP_NW4END0_4" + ], + [ + "CMT_FIFO_WL1END1_8", + "CMT_TOP_WL1END1_8" + ], + [ + "CMT_FIFO_EE4B2_5", + "CMT_TOP_EE4B2_5" + ], + [ + "CMT_FIFO_NE4BEG0_0", + "CMT_TOP_NE4BEG0_0" + ], + [ + "CMT_FIFO_SW4END1_7", + "CMT_TOP_SW4END1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_6", + "CMT_TOP_LOGIC_OUTS_L_B10_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_6", + "CMT_TOP_LOGIC_OUTS_L_B14_6" + ], + [ + "CMT_FIFO_NE4BEG1_3", + "CMT_TOP_NE4BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX20_2", + "CMT_TOP_IMUX20_2" + ], + [ + "CMT_FIFO_SE4BEG0_5", + "CMT_TOP_SE4BEG0_5" + ], + [ + "CMT_FIFO_NW4END0_2", + "CMT_TOP_NW4END0_2" + ], + [ + "CMT_FIFO_NW4A2_6", + "CMT_TOP_NW4A2_6" + ], + [ + "CMT_FIFO_WW2A3_10", + "CMT_TOP_WW2A3_10" + ], + [ + "CMT_FIFO_L_IMUX40_7", + "CMT_TOP_IMUX40_7" + ], + [ + "CMT_FIFO_LH8_11", + "CMT_TOP_LH8_11" + ], + [ + "CMT_FIFO_L_IMUX19_2", + "CMT_TOP_IMUX19_2" + ], + [ + "CMT_FIFO_WL1END3_6", + "CMT_TOP_WL1END3_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "CMT_TOP_OCLK_5" + ], + [ + "CMT_FIFO_L_IMUX16_8", + "CMT_TOP_IMUX16_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_8", + "CMT_TOP_LOGIC_OUTS_L_B12_8" + ], + [ + "CMT_FIFO_EE4BEG0_1", + "CMT_TOP_EE4BEG0_1" + ], + [ + "CMT_FIFO_WR1END1_6", + "CMT_TOP_WR1END1_6" + ], + [ + "CMT_FIFO_NE2A2_3", + "CMT_TOP_NE2A2_3" + ], + [ + "CMT_FIFO_WW4END1_5", + "CMT_TOP_WW4END1_5" + ], + [ + "CMT_FIFO_L_IMUX2_8", + "CMT_TOP_IMUX2_8" + ], + [ + "CMT_FIFO_NW4A2_9", + "CMT_TOP_NW4A2_9" + ], + [ + "CMT_FIFO_EL1BEG2_2", + "CMT_TOP_EL1BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX4_0", + "CMT_TOP_IMUX4_0" + ], + [ + "CMT_FIFO_EE4A1_7", + "CMT_TOP_EE4A1_7" + ], + [ + "CMT_FIFO_L_IMUX35_1", + "CMT_TOP_IMUX35_1" + ], + [ + "CMT_FIFO_WL1END2_7", + "CMT_TOP_WL1END2_7" + ], + [ + "CMT_FIFO_L_FAN5_3", + "CMT_TOP_FAN5_3" + ], + [ + "CMT_FIFO_LH1_3", + "CMT_TOP_LH1_3" + ], + [ + "CMT_FIFO_L_IMUX11_8", + "CMT_TOP_IMUX11_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "CMT_TOP_ICLKDIV_4" + ], + [ + "CMT_FIFO_EE4B0_7", + "CMT_TOP_EE4B0_7" + ], + [ + "CMT_FIFO_WW4A0_9", + "CMT_TOP_WW4A0_9" + ], + [ + "CMT_FIFO_L_IMUX40_0", + "CMT_TOP_IMUX40_0" + ], + [ + "CMT_FIFO_L_CTRL0_5", + "CMT_TOP_CTRL0_5" + ], + [ + "CMT_FIFO_L_BYP2_2", + "CMT_TOP_BYP2_2" + ], + [ + "CMT_FIFO_L_IMUX19_0", + "CMT_TOP_IMUX19_0" + ], + [ + "CMT_FIFO_WR1END3_0", + "CMT_TOP_WR1END3_0" + ], + [ + "CMT_FIFO_EL1BEG0_5", + "CMT_TOP_EL1BEG0_5" + ], + [ + "CMT_FIFO_EE4B1_10", + "CMT_TOP_EE4B1_10" + ], + [ + "CMT_FIFO_EE4A1_3", + "CMT_TOP_EE4A1_3" + ], + [ + "CMT_FIFO_EE4BEG3_10", + "CMT_TOP_EE4BEG3_10" + ], + [ + "CMT_FIFO_EE2A1_3", + "CMT_TOP_EE2A1_3" + ], + [ + "CMT_FIFO_L_BYP6_0", + "CMT_TOP_BYP6_0" + ], + [ + "CMT_FIFO_NE4BEG2_9", + "CMT_TOP_NE4BEG2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_11", + "CMT_TOP_LOGIC_OUTS_L_B0_11" + ], + [ + "CMT_FIFO_SW4END2_0", + "CMT_TOP_SW4END2_0" + ], + [ + "CMT_FIFO_L_IMUX33_8", + "CMT_TOP_IMUX33_8" + ], + [ + "CMT_FIFO_SW4END3_5", + "CMT_TOP_SW4END3_5" + ], + [ + "CMT_FIFO_L_IMUX24_9", + "CMT_TOP_IMUX24_9" + ], + [ + "CMT_FIFO_SW2A3_11", + "CMT_TOP_SW2A3_11" + ], + [ + "CMT_FIFO_L_IMUX37_4", + "CMT_TOP_IMUX37_4" + ], + [ + "CMT_FIFO_NW4A0_0", + "CMT_TOP_NW4A0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_8", + "CMT_TOP_LOGIC_OUTS_L_B9_8" + ], + [ + "CMT_FIFO_LH8_10", + "CMT_TOP_LH8_10" + ], + [ + "CMT_FIFO_NE4C2_11", + "CMT_TOP_NE4C2_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "CMT_TOP_ICLKDIV_8" + ], + [ + "CMT_FIFO_WW4B1_3", + "CMT_TOP_WW4B1_3" + ], + [ + "CMT_FIFO_WW4B0_1", + "CMT_TOP_WW4B0_1" + ], + [ + "CMT_FIFO_L_IMUX6_1", + "CMT_TOP_IMUX6_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_11", + "CMT_TOP_LOGIC_OUTS_L_B8_11" + ], + [ + "CMT_FIFO_WL1END1_9", + "CMT_TOP_WL1END1_9" + ], + [ + "CMT_FIFO_L_IMUX20_1", + "CMT_TOP_IMUX20_1" + ], + [ + "CMT_FIFO_L_IMUX43_3", + "CMT_TOP_IMUX43_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_3", + "CMT_TOP_LOGIC_OUTS_L_B2_3" + ], + [ + "CMT_FIFO_L_FAN7_0", + "CMT_TOP_FAN7_0" + ], + [ + "CMT_FIFO_L_BYP6_10", + "CMT_TOP_BYP6_10" + ], + [ + "CMT_FIFO_EE4B0_6", + "CMT_TOP_EE4B0_6" + ], + [ + "CMT_FIFO_EE4BEG1_6", + "CMT_TOP_EE4BEG1_6" + ], + [ + "CMT_FIFO_EE2A2_10", + "CMT_TOP_EE2A2_10" + ], + [ + "CMT_FIFO_L_IMUX28_5", + "CMT_TOP_IMUX28_5" + ], + [ + "CMT_FIFO_L_IMUX20_3", + "CMT_TOP_IMUX20_3" + ], + [ + "CMT_FIFO_SE4BEG2_3", + "CMT_TOP_SE4BEG2_3" + ], + [ + "CMT_FIFO_L_CLK0_2", + "CMT_TOP_CLK0_2" + ], + [ + "CMT_FIFO_SW4END2_1", + "CMT_TOP_SW4END2_1" + ], + [ + "CMT_FIFO_EE4A3_11", + "CMT_TOP_EE4A3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_7", + "CMT_TOP_LOGIC_OUTS_L_B6_7" + ], + [ + "CMT_FIFO_WL1END1_10", + "CMT_TOP_WL1END1_10" + ], + [ + "CMT_FIFO_LH2_11", + "CMT_TOP_LH2_11" + ], + [ + "CMT_FIFO_EL1BEG1_6", + "CMT_TOP_EL1BEG1_6" + ], + [ + "CMT_FIFO_NE4C1_10", + "CMT_TOP_NE4C1_10" + ], + [ + "CMT_FIFO_NE4C2_4", + "CMT_TOP_NE4C2_4" + ], + [ + "CMT_FIFO_L_IMUX24_11", + "CMT_TOP_IMUX24_11" + ], + [ + "CMT_FIFO_L_IMUX27_10", + "CMT_TOP_IMUX27_10" + ], + [ + "CMT_FIFO_EE4A2_7", + "CMT_TOP_EE4A2_7" + ], + [ + "CMT_FIFO_EE4BEG2_9", + "CMT_TOP_EE4BEG2_9" + ], + [ + "CMT_FIFO_LH9_9", + "CMT_TOP_LH9_9" + ], + [ + "CMT_FIFO_WR1END0_2", + "CMT_TOP_WR1END0_2" + ], + [ + "CMT_FIFO_L_IMUX9_11", + "CMT_TOP_IMUX9_11" + ], + [ + "CMT_FIFO_WW4B1_7", + "CMT_TOP_WW4B1_7" + ], + [ + "CMT_FIFO_L_CLK0_1", + "CMT_TOP_CLK0_1" + ], + [ + "CMT_FIFO_WW2END2_9", + "CMT_TOP_WW2END2_9" + ], + [ + "CMT_FIFO_NE4BEG3_8", + "CMT_TOP_NE4BEG3_8" + ], + [ + "CMT_FIFO_WW4A2_0", + "CMT_TOP_WW4A2_0" + ], + [ + "CMT_FIFO_WL1END2_0", + "CMT_TOP_WL1END2_0" + ], + [ + "CMT_FIFO_EE2BEG2_7", + "CMT_TOP_EE2BEG2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_9", + "CMT_TOP_LOGIC_OUTS_L_B18_9" + ], + [ + "CMT_FIFO_WW2END1_9", + "CMT_TOP_WW2END1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_10", + "CMT_TOP_LOGIC_OUTS_L_B12_10" + ], + [ + "CMT_FIFO_WW4C2_11", + "CMT_TOP_WW4C2_11" + ], + [ + "CMT_FIFO_SE4C1_9", + "CMT_TOP_SE4C1_9" + ], + [ + "CMT_FIFO_WL1END2_9", + "CMT_TOP_WL1END2_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "CMT_TOP_OCLKDIV_10" + ], + [ + "CMT_FIFO_EE2BEG1_3", + "CMT_TOP_EE2BEG1_3" + ], + [ + "CMT_FIFO_WW2END2_1", + "CMT_TOP_WW2END2_1" + ], + [ + "CMT_FIFO_L_BYP5_0", + "CMT_TOP_BYP5_0" + ], + [ + "CMT_FIFO_NE4C2_10", + "CMT_TOP_NE4C2_10" + ], + [ + "CMT_FIFO_NE4BEG0_11", + "CMT_TOP_NE4BEG0_11" + ], + [ + "CMT_FIFO_NE4C2_0", + "CMT_TOP_NE4C2_0" + ], + [ + "CMT_FIFO_SW4A2_7", + "CMT_TOP_SW4A2_7" + ], + [ + "CMT_FIFO_SW4END1_3", + "CMT_TOP_SW4END1_3" + ], + [ + "CMT_FIFO_L_IMUX9_3", + "CMT_TOP_IMUX9_3" + ], + [ + "CMT_FIFO_LH2_0", + "CMT_TOP_LH2_0" + ], + [ + "CMT_FIFO_EL1BEG2_1", + "CMT_TOP_EL1BEG2_1" + ], + [ + "CMT_FIFO_WL1END2_1", + "CMT_TOP_WL1END2_1" + ], + [ + "CMT_FIFO_EE4C3_3", + "CMT_TOP_EE4C3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_6", + "CMT_TOP_LOGIC_OUTS_L_B15_6" + ], + [ + "CMT_FIFO_L_IMUX22_1", + "CMT_TOP_IMUX22_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_5", + "CMT_TOP_LOGIC_OUTS_L_B21_5" + ], + [ + "CMT_FIFO_SW4END1_0", + "CMT_TOP_SW4END1_0" + ], + [ + "CMT_FIFO_SE4C3_5", + "CMT_TOP_SE4C3_5" + ], + [ + "CMT_FIFO_EE4BEG0_8", + "CMT_TOP_EE4BEG0_8" + ], + [ + "CMT_FIFO_L_IMUX27_7", + "CMT_TOP_IMUX27_7" + ], + [ + "CMT_FIFO_NW4END0_8", + "CMT_TOP_NW4END0_8" + ], + [ + "CMT_FIFO_L_IMUX33_1", + "CMT_TOP_IMUX33_1" + ], + [ + "CMT_FIFO_L_IMUX11_0", + "CMT_TOP_IMUX11_0" + ], + [ + "CMT_FIFO_L_FAN0_0", + "CMT_TOP_FAN0_0" + ], + [ + "CMT_FIFO_SW4END2_9", + "CMT_TOP_SW4END2_9" + ], + [ + "CMT_FIFO_L_IMUX35_10", + "CMT_TOP_IMUX35_10" + ], + [ + "CMT_FIFO_WW2END3_7", + "CMT_TOP_WW2END3_7" + ], + [ + "CMT_FIFO_EE4BEG1_3", + "CMT_TOP_EE4BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX19_3", + "CMT_TOP_IMUX19_3" + ], + [ + "CMT_FIFO_EE4B3_9", + "CMT_TOP_EE4B3_9" + ], + [ + "CMT_FIFO_LH3_3", + "CMT_TOP_LH3_3" + ], + [ + "CMT_FIFO_EE2A1_5", + "CMT_TOP_EE2A1_5" + ], + [ + "CMT_FIFO_NW2A1_5", + "CMT_TOP_NW2A1_5" + ], + [ + "CMT_FIFO_EE2A0_2", + "CMT_TOP_EE2A0_2" + ], + [ + "CMT_FIFO_SW4A2_10", + "CMT_TOP_SW4A2_10" + ], + [ + "CMT_FIFO_EE4C2_2", + "CMT_TOP_EE4C2_2" + ], + [ + "CMT_FIFO_LH2_7", + "CMT_TOP_LH2_7" + ], + [ + "CMT_FIFO_EE4BEG3_6", + "CMT_TOP_EE4BEG3_6" + ], + [ + "CMT_FIFO_L_IMUX44_8", + "CMT_TOP_IMUX44_8" + ], + [ + "CMT_FIFO_L_IMUX23_4", + "CMT_TOP_IMUX23_4" + ], + [ + "CMT_FIFO_SE4BEG2_10", + "CMT_TOP_SE4BEG2_10" + ], + [ + "CMT_FIFO_L_IMUX30_6", + "CMT_TOP_IMUX30_6" + ], + [ + "CMT_FIFO_L_CTRL0_3", + "CMT_TOP_CTRL0_3" + ], + [ + "CMT_FIFO_WR1END3_2", + "CMT_TOP_WR1END3_2" + ], + [ + "CMT_FIFO_SW4A0_3", + "CMT_TOP_SW4A0_3" + ], + [ + "CMT_FIFO_L_IMUX22_11", + "CMT_TOP_IMUX22_11" + ], + [ + "CMT_FIFO_LH9_3", + "CMT_TOP_LH9_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_11", + "CMT_TOP_LOGIC_OUTS_L_B11_11" + ], + [ + "CMT_FIFO_L_IMUX24_5", + "CMT_TOP_IMUX24_5" + ], + [ + "CMT_FIFO_WR1END1_11", + "CMT_TOP_WR1END1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_4", + "CMT_TOP_LOGIC_OUTS_L_B10_4" + ], + [ + "CMT_FIFO_SE4C0_6", + "CMT_TOP_SE4C0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_10", + "CMT_TOP_LOGIC_OUTS_L_B9_10" + ], + [ + "CMT_FIFO_LH4_10", + "CMT_TOP_LH4_10" + ], + [ + "CMT_FIFO_L_IMUX2_1", + "CMT_TOP_IMUX2_1" + ], + [ + "CMT_FIFO_LH7_6", + "CMT_TOP_LH7_6" + ], + [ + "CMT_FIFO_L_BYP5_7", + "CMT_TOP_BYP5_7" + ], + [ + "CMT_FIFO_L_IMUX4_11", + "CMT_TOP_IMUX4_11" + ], + [ + "CMT_FIFO_L_IMUX43_5", + "CMT_TOP_IMUX43_5" + ], + [ + "CMT_FIFO_L_IMUX18_5", + "CMT_TOP_IMUX18_5" + ], + [ + "CMT_FIFO_WW4END1_9", + "CMT_TOP_WW4END1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_1", + "CMT_TOP_LOGIC_OUTS_L_B9_1" + ], + [ + "CMT_FIFO_NE4BEG2_2", + "CMT_TOP_NE4BEG2_2" + ], + [ + "CMT_FIFO_WW2A3_8", + "CMT_TOP_WW2A3_8" + ], + [ + "CMT_FIFO_EL1BEG1_4", + "CMT_TOP_EL1BEG1_4" + ], + [ + "CMT_FIFO_SE2A1_7", + "CMT_TOP_SE2A1_7" + ], + [ + "CMT_FIFO_WW2A0_1", + "CMT_TOP_WW2A0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_10", + "CMT_TOP_LOGIC_OUTS_L_B19_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "CMT_TOP_ICLK_7" + ], + [ + "CMT_FIFO_NW4END1_3", + "CMT_TOP_NW4END1_3" + ], + [ + "CMT_FIFO_WW4C2_8", + "CMT_TOP_WW4C2_8" + ], + [ + "CMT_FIFO_NE4BEG1_11", + "CMT_TOP_NE4BEG1_11" + ], + [ + "CMT_FIFO_NE2A1_4", + "CMT_TOP_NE2A1_4" + ], + [ + "CMT_FIFO_NE4BEG0_10", + "CMT_TOP_NE4BEG0_10" + ], + [ + "CMT_FIFO_L_BYP1_4", + "CMT_TOP_BYP1_4" + ], + [ + "CMT_FIFO_EL1BEG3_3", + "CMT_TOP_EL1BEG3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_7" + ], + [ + "CMT_FIFO_NW2A2_10", + "CMT_TOP_NW2A2_10" + ], + [ + "CMT_FIFO_L_IMUX32_0", + "CMT_TOP_IMUX32_0" + ], + [ + "CMT_FIFO_SE4C0_4", + "CMT_TOP_SE4C0_4" + ], + [ + "CMT_FIFO_L_IMUX1_1", + "CMT_TOP_IMUX1_1" + ], + [ + "CMT_FIFO_L_IMUX39_10", + "CMT_TOP_IMUX39_10" + ], + [ + "CMT_FIFO_EE4C1_10", + "CMT_TOP_EE4C1_10" + ], + [ + "CMT_FIFO_L_BYP1_10", + "CMT_TOP_BYP1_10" + ], + [ + "CMT_FIFO_SE4BEG3_11", + "CMT_TOP_SE4BEG3_11" + ], + [ + "CMT_FIFO_L_IMUX47_9", + "CMT_TOP_IMUX47_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_4", + "CMT_TOP_LOGIC_OUTS_L_B4_4" + ], + [ + "CMT_FIFO_WL1END3_8", + "CMT_TOP_WL1END3_8" + ], + [ + "CMT_FIFO_L_IMUX13_11", + "CMT_TOP_IMUX13_11" + ], + [ + "CMT_FIFO_L_BYP5_8", + "CMT_TOP_BYP5_8" + ], + [ + "CMT_FIFO_NE4C3_9", + "CMT_TOP_NE4C3_9" + ], + [ + "CMT_FIFO_NE4C3_10", + "CMT_TOP_NE4C3_10" + ], + [ + "CMT_FIFO_L_IMUX26_10", + "CMT_TOP_IMUX26_10" + ], + [ + "CMT_FIFO_L_IMUX17_0", + "CMT_TOP_IMUX17_0" + ], + [ + "CMT_FIFO_L_IMUX25_9", + "CMT_TOP_IMUX25_9" + ], + [ + "CMT_FIFO_NW2A1_2", + "CMT_TOP_NW2A1_2" + ], + [ + "CMT_FIFO_L_IMUX45_11", + "CMT_TOP_IMUX45_11" + ], + [ + "CMT_FIFO_WW4C3_5", + "CMT_TOP_WW4C3_5" + ], + [ + "CMT_FIFO_WW4END2_10", + "CMT_TOP_WW4END2_10" + ], + [ + "CMT_FIFO_EE2A0_10", + "CMT_TOP_EE2A0_10" + ], + [ + "CMT_FIFO_ER1BEG0_7", + "CMT_TOP_ER1BEG0_7" + ], + [ + "CMT_FIFO_EE4BEG3_3", + "CMT_TOP_EE4BEG3_3" + ], + [ + "CMT_FIFO_L_IMUX42_1", + "CMT_TOP_IMUX42_1" + ], + [ + "CMT_FIFO_NE2A1_5", + "CMT_TOP_NE2A1_5" + ], + [ + "CMT_FIFO_L_IMUX22_2", + "CMT_TOP_IMUX22_2" + ], + [ + "CMT_FIFO_WR1END1_1", + "CMT_TOP_WR1END1_1" + ], + [ + "CMT_FIFO_EE2BEG1_8", + "CMT_TOP_EE2BEG1_8" + ], + [ + "CMT_FIFO_EL1BEG3_8", + "CMT_TOP_EL1BEG3_8" + ], + [ + "CMT_FIFO_L_IMUX19_9", + "CMT_TOP_IMUX19_9" + ], + [ + "CMT_FIFO_ER1BEG1_6", + "CMT_TOP_ER1BEG1_6" + ], + [ + "CMT_FIFO_L_BYP3_6", + "CMT_TOP_BYP3_6" + ], + [ + "CMT_FIFO_SW2A3_5", + "CMT_TOP_SW2A3_5" + ], + [ + "CMT_FIFO_ER1BEG3_1", + "CMT_TOP_ER1BEG3_1" + ], + [ + "CMT_FIFO_L_BYP4_10", + "CMT_TOP_BYP4_10" + ], + [ + "CMT_FIFO_SW4A3_9", + "CMT_TOP_SW4A3_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "CMT_TOP_OCLK_3" + ], + [ + "CMT_FIFO_L_IMUX20_10", + "CMT_TOP_IMUX20_10" + ], + [ + "CMT_FIFO_NW2A2_11", + "CMT_TOP_NW2A2_11" + ], + [ + "CMT_FIFO_L_FAN2_8", + "CMT_TOP_FAN2_8" + ], + [ + "CMT_FIFO_L_FAN0_6", + "CMT_TOP_FAN0_6" + ], + [ + "CMT_FIFO_WW2A0_11", + "CMT_TOP_WW2A0_11" + ], + [ + "CMT_FIFO_WW4A1_3", + "CMT_TOP_WW4A1_3" + ], + [ + "CMT_FIFO_L_IMUX40_4", + "CMT_TOP_IMUX40_4" + ], + [ + "CMT_FIFO_L_IMUX46_2", + "CMT_TOP_IMUX46_2" + ], + [ + "CMT_FIFO_NW4END3_9", + "CMT_TOP_NW4END3_9" + ], + [ + "CMT_FIFO_ER1BEG2_6", + "CMT_TOP_ER1BEG2_6" + ], + [ + "CMT_FIFO_EE4A3_4", + "CMT_TOP_EE4A3_4" + ], + [ + "CMT_FIFO_EE4BEG2_1", + "CMT_TOP_EE4BEG2_1" + ], + [ + "CMT_FIFO_WW2A3_6", + "CMT_TOP_WW2A3_6" + ], + [ + "CMT_FIFO_WW4B0_9", + "CMT_TOP_WW4B0_9" + ], + [ + "CMT_FIFO_L_IMUX43_1", + "CMT_TOP_IMUX43_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_9", + "CMT_TOP_LOGIC_OUTS_L_B11_9" + ], + [ + "CMT_FIFO_L_IMUX16_6", + "CMT_TOP_IMUX16_6" + ], + [ + "CMT_FIFO_L_IMUX44_10", + "CMT_TOP_IMUX44_10" + ], + [ + "CMT_FIFO_L_IMUX4_8", + "CMT_TOP_IMUX4_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_5" + ], + [ + "CMT_FIFO_EE4BEG1_8", + "CMT_TOP_EE4BEG1_8" + ], + [ + "CMT_FIFO_WW4A0_3", + "CMT_TOP_WW4A0_3" + ], + [ + "CMT_FIFO_ER1BEG2_11", + "CMT_TOP_ER1BEG2_11" + ], + [ + "CMT_FIFO_EE2A0_6", + "CMT_TOP_EE2A0_6" + ], + [ + "CMT_FIFO_EE4BEG2_4", + "CMT_TOP_EE4BEG2_4" + ], + [ + "CMT_FIFO_L_IMUX37_1", + "CMT_TOP_IMUX37_1" + ], + [ + "CMT_FIFO_LH2_1", + "CMT_TOP_LH2_1" + ], + [ + "CMT_FIFO_WW4B1_0", + "CMT_TOP_WW4B1_0" + ], + [ + "CMT_FIFO_WW4B1_1", + "CMT_TOP_WW4B1_1" + ], + [ + "CMT_FIFO_NW2A3_8", + "CMT_TOP_NW2A3_8" + ], + [ + "CMT_FIFO_NW4A1_11", + "CMT_TOP_NW4A1_11" + ], + [ + "CMT_FIFO_EE4A1_10", + "CMT_TOP_EE4A1_10" + ], + [ + "CMT_FIFO_WR1END1_2", + "CMT_TOP_WR1END1_2" + ], + [ + "CMT_FIFO_WW4B0_0", + "CMT_TOP_WW4B0_0" + ], + [ + "CMT_FIFO_L_IMUX29_10", + "CMT_TOP_IMUX29_10" + ], + [ + "CMT_FIFO_WW2END1_11", + "CMT_TOP_WW2END1_11" + ], + [ + "CMT_FIFO_L_BYP2_4", + "CMT_TOP_BYP2_4" + ], + [ + "CMT_FIFO_WW4C2_6", + "CMT_TOP_WW4C2_6" + ], + [ + "CMT_FIFO_L_BYP7_2", + "CMT_TOP_BYP7_2" + ], + [ + "CMT_FIFO_L_IMUX45_0", + "CMT_TOP_IMUX45_0" + ], + [ + "CMT_FIFO_L_IMUX42_10", + "CMT_TOP_IMUX42_10" + ], + [ + "CMT_FIFO_L_CLK0_6", + "CMT_TOP_CLK0_6" + ], + [ + "CMT_FIFO_SW2A3_8", + "CMT_TOP_SW2A3_8" + ], + [ + "CMT_FIFO_NW4END1_4", + "CMT_TOP_NW4END1_4" + ], + [ + "CMT_FIFO_L_CLK1_2", + "CMT_TOP_CLK1_2" + ], + [ + "CMT_FIFO_EE2BEG3_2", + "CMT_TOP_EE2BEG3_2" + ], + [ + "CMT_FIFO_L_IMUX3_3", + "CMT_TOP_IMUX3_3" + ], + [ + "CMT_FIFO_WW4C0_1", + "CMT_TOP_WW4C0_1" + ], + [ + "CMT_FIFO_NE2A1_1", + "CMT_TOP_NE2A1_1" + ], + [ + "CMT_FIFO_L_BYP2_9", + "CMT_TOP_BYP2_9" + ], + [ + "CMT_FIFO_WW2A1_1", + "CMT_TOP_WW2A1_1" + ], + [ + "CMT_FIFO_L_FAN0_2", + "CMT_TOP_FAN0_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "CMT_TOP_OCLK_9" + ], + [ + "CMT_FIFO_SW2A2_6", + "CMT_TOP_SW2A2_6" + ], + [ + "CMT_FIFO_L_IMUX1_7", + "CMT_TOP_IMUX1_7" + ], + [ + "CMT_FIFO_SE4BEG2_4", + "CMT_TOP_SE4BEG2_4" + ], + [ + "CMT_FIFO_NW4A2_11", + "CMT_TOP_NW4A2_11" + ], + [ + "CMT_FIFO_EE4B0_11", + "CMT_TOP_EE4B0_11" + ], + [ + "CMT_FIFO_SW4A2_8", + "CMT_TOP_SW4A2_8" + ], + [ + "CMT_FIFO_WR1END3_1", + "CMT_TOP_WR1END3_1" + ], + [ + "CMT_FIFO_L_IMUX34_8", + "CMT_TOP_IMUX34_8" + ], + [ + "CMT_FIFO_L_IMUX47_3", + "CMT_TOP_IMUX47_3" + ], + [ + "CMT_FIFO_EE4A3_5", + "CMT_TOP_EE4A3_5" + ], + [ + "CMT_FIFO_EE4A0_0", + "CMT_TOP_EE4A0_0" + ], + [ + "CMT_FIFO_SE4BEG1_10", + "CMT_TOP_SE4BEG1_10" + ], + [ + "CMT_FIFO_LH2_10", + "CMT_TOP_LH2_10" + ], + [ + "CMT_FIFO_SE4C2_7", + "CMT_TOP_SE4C2_7" + ], + [ + "CMT_FIFO_L_IMUX15_5", + "CMT_TOP_IMUX15_5" + ], + [ + "CMT_FIFO_EE4C3_6", + "CMT_TOP_EE4C3_6" + ], + [ + "CMT_FIFO_L_IMUX44_5", + "CMT_TOP_IMUX44_5" + ], + [ + "CMT_FIFO_WW4C0_5", + "CMT_TOP_WW4C0_5" + ], + [ + "CMT_FIFO_L_IMUX31_10", + "CMT_TOP_IMUX31_10" + ], + [ + "CMT_FIFO_EL1BEG2_0", + "CMT_TOP_EL1BEG2_0" + ], + [ + "CMT_FIFO_SE4BEG0_7", + "CMT_TOP_SE4BEG0_7" + ], + [ + "CMT_FIFO_WW4END0_3", + "CMT_TOP_WW4END0_3" + ], + [ + "CMT_FIFO_WL1END1_7", + "CMT_TOP_WL1END1_7" + ], + [ + "CMT_FIFO_MONITOR_N_2", + "CMT_TOP_MONITOR_N_2" + ], + [ + "CMT_FIFO_NE4BEG0_4", + "CMT_TOP_NE4BEG0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_11", + "CMT_TOP_LOGIC_OUTS_L_B12_11" + ], + [ + "CMT_FIFO_SE4BEG2_5", + "CMT_TOP_SE4BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX17_2", + "CMT_TOP_IMUX17_2" + ], + [ + "CMT_FIFO_L_IMUX16_2", + "CMT_TOP_IMUX16_2" + ], + [ + "CMT_FIFO_WW4END1_8", + "CMT_TOP_WW4END1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_7", + "CMT_TOP_LOGIC_OUTS_L_B1_7" + ], + [ + "CMT_FIFO_L_IMUX20_0", + "CMT_TOP_IMUX20_0" + ], + [ + "CMT_FIFO_SE2A3_9", + "CMT_TOP_SE2A3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_3", + "CMT_TOP_LOGIC_OUTS_L_B7_3" + ], + [ + "CMT_FIFO_EE4C2_0", + "CMT_TOP_EE4C2_0" + ], + [ + "CMT_FIFO_L_FAN3_5", + "CMT_TOP_FAN3_5" + ], + [ + "CMT_FIFO_WW4B0_2", + "CMT_TOP_WW4B0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_2", + "CMT_TOP_LOGIC_OUTS_L_B9_2" + ], + [ + "CMT_FIFO_L_IMUX26_1", + "CMT_TOP_IMUX26_1" + ], + [ + "CMT_FIFO_EE4C3_1", + "CMT_TOP_EE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX38_3", + "CMT_TOP_IMUX38_3" + ], + [ + "CMT_FIFO_L_IMUX36_9", + "CMT_TOP_IMUX36_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_5", + "CMT_TOP_LOGIC_OUTS_L_B1_5" + ], + [ + "CMT_FIFO_EE4C0_1", + "CMT_TOP_EE4C0_1" + ], + [ + "CMT_FIFO_L_IMUX2_7", + "CMT_TOP_IMUX2_7" + ], + [ + "CMT_FIFO_NE4BEG1_8", + "CMT_TOP_NE4BEG1_8" + ], + [ + "CMT_FIFO_WW2A1_11", + "CMT_TOP_WW2A1_11" + ], + [ + "CMT_FIFO_L_CLK1_5", + "CMT_TOP_CLK1_5" + ], + [ + "CMT_FIFO_L_FAN0_3", + "CMT_TOP_FAN0_3" + ], + [ + "CMT_FIFO_WW4C3_7", + "CMT_TOP_WW4C3_7" + ], + [ + "CMT_FIFO_EE2BEG2_10", + "CMT_TOP_EE2BEG2_10" + ], + [ + "CMT_FIFO_SE4C2_5", + "CMT_TOP_SE4C2_5" + ], + [ + "CMT_FIFO_SW2A0_4", + "CMT_TOP_SW2A0_4" + ], + [ + "CMT_FIFO_L_IMUX2_3", + "CMT_TOP_IMUX2_3" + ], + [ + "CMT_FIFO_WR1END2_8", + "CMT_TOP_WR1END2_8" + ], + [ + "CMT_FIFO_L_IMUX8_0", + "CMT_TOP_IMUX8_0" + ], + [ + "CMT_FIFO_EE2BEG1_2", + "CMT_TOP_EE2BEG1_2" + ], + [ + "CMT_FIFO_WW2END0_3", + "CMT_TOP_WW2END0_3" + ], + [ + "CMT_FIFO_EE4A0_2", + "CMT_TOP_EE4A0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_2", + "CMT_TOP_LOGIC_OUTS_L_B10_2" + ], + [ + "CMT_FIFO_WW2END0_8", + "CMT_TOP_WW2END0_8" + ], + [ + "CMT_FIFO_L_FAN1_8", + "CMT_TOP_FAN1_8" + ], + [ + "CMT_FIFO_L_IMUX40_9", + "CMT_TOP_IMUX40_9" + ], + [ + "CMT_FIFO_WW2END3_9", + "CMT_TOP_WW2END3_9" + ], + [ + "CMT_FIFO_EE4C1_6", + "CMT_TOP_EE4C1_6" + ], + [ + "CMT_FIFO_L_BYP5_5", + "CMT_TOP_BYP5_5" + ], + [ + "CMT_FIFO_LH5_8", + "CMT_TOP_LH5_8" + ], + [ + "CMT_FIFO_L_FAN6_11", + "CMT_TOP_FAN6_11" + ], + [ + "CMT_FIFO_WW2A2_3", + "CMT_TOP_WW2A2_3" + ], + [ + "CMT_FIFO_WW2A3_3", + "CMT_TOP_WW2A3_3" + ], + [ + "CMT_FIFO_L_IMUX4_2", + "CMT_TOP_IMUX4_2" + ], + [ + "CMT_FIFO_L_IMUX36_4", + "CMT_TOP_IMUX36_4" + ], + [ + "CMT_FIFO_LH1_11", + "CMT_TOP_LH1_11" + ], + [ + "CMT_FIFO_WW4B3_0", + "CMT_TOP_WW4B3_0" + ], + [ + "CMT_FIFO_EE4B3_7", + "CMT_TOP_EE4B3_7" + ], + [ + "CMT_FIFO_LH5_11", + "CMT_TOP_LH5_11" + ], + [ + "CMT_FIFO_NW2A1_11", + "CMT_TOP_NW2A1_11" + ], + [ + "CMT_FIFO_SE4C2_9", + "CMT_TOP_SE4C2_9" + ], + [ + "CMT_FIFO_L_CTRL1_11", + "CMT_TOP_CTRL1_11" + ], + [ + "CMT_FIFO_SW2A0_5", + "CMT_TOP_SW2A0_5" + ], + [ + "CMT_FIFO_LH7_10", + "CMT_TOP_LH7_10" + ], + [ + "CMT_FIFO_L_IMUX25_0", + "CMT_TOP_IMUX25_0" + ], + [ + "CMT_FIFO_L_FAN2_5", + "CMT_TOP_FAN2_5" + ], + [ + "CMT_FIFO_NE4BEG3_2", + "CMT_TOP_NE4BEG3_2" + ], + [ + "CMT_FIFO_EE4B2_4", + "CMT_TOP_EE4B2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_4", + "CMT_TOP_LOGIC_OUTS_L_B19_4" + ], + [ + "CMT_FIFO_NE2A1_0", + "CMT_TOP_NE2A1_0" + ], + [ + "CMT_FIFO_WW2A0_6", + "CMT_TOP_WW2A0_6" + ], + [ + "CMT_FIFO_L_IMUX19_11", + "CMT_TOP_IMUX19_11" + ], + [ + "CMT_FIFO_L_IMUX3_5", + "CMT_TOP_IMUX3_5" + ], + [ + "CMT_FIFO_L_BYP7_1", + "CMT_TOP_BYP7_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_8", + "CMT_TOP_LOGIC_OUTS_L_B7_8" + ], + [ + "CMT_FIFO_WW4C3_2", + "CMT_TOP_WW4C3_2" + ], + [ + "CMT_FIFO_L_IMUX18_0", + "CMT_TOP_IMUX18_0" + ], + [ + "CMT_FIFO_LH2_9", + "CMT_TOP_LH2_9" + ], + [ + "CMT_FIFO_L_IMUX46_6", + "CMT_TOP_IMUX46_6" + ], + [ + "CMT_FIFO_L_IMUX29_9", + "CMT_TOP_IMUX29_9" + ], + [ + "CMT_FIFO_SE4C1_2", + "CMT_TOP_SE4C1_2" + ], + [ + "CMT_FIFO_L_IMUX24_6", + "CMT_TOP_IMUX24_6" + ], + [ + "CMT_FIFO_EE4A0_9", + "CMT_TOP_EE4A0_9" + ], + [ + "CMT_FIFO_SE2A3_3", + "CMT_TOP_SE2A3_3" + ], + [ + "CMT_FIFO_L_IMUX46_9", + "CMT_TOP_IMUX46_9" + ], + [ + "CMT_FIFO_NE4C0_5", + "CMT_TOP_NE4C0_5" + ], + [ + "CMT_FIFO_WW2A0_4", + "CMT_TOP_WW2A0_4" + ], + [ + "CMT_FIFO_L_FAN7_6", + "CMT_TOP_FAN7_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_8", + "CMT_TOP_LOGIC_OUTS_L_B13_8" + ], + [ + "CMT_FIFO_L_IMUX6_10", + "CMT_TOP_IMUX6_10" + ], + [ + "CMT_FIFO_SW2A1_4", + "CMT_TOP_SW2A1_4" + ], + [ + "CMT_FIFO_NE4BEG2_1", + "CMT_TOP_NE4BEG2_1" + ], + [ + "CMT_FIFO_ER1BEG0_8", + "CMT_TOP_ER1BEG0_8" + ], + [ + "CMT_FIFO_L_BYP1_9", + "CMT_TOP_BYP1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_2", + "CMT_TOP_LOGIC_OUTS_L_B22_2" + ], + [ + "CMT_FIFO_L_IMUX26_9", + "CMT_TOP_IMUX26_9" + ], + [ + "CMT_FIFO_WW4B1_8", + "CMT_TOP_WW4B1_8" + ], + [ + "CMT_FIFO_L_FAN6_0", + "CMT_TOP_FAN6_0" + ], + [ + "CMT_FIFO_L_IMUX20_4", + "CMT_TOP_IMUX20_4" + ], + [ + "CMT_FIFO_NW2A3_2", + "CMT_TOP_NW2A3_2" + ], + [ + "CMT_FIFO_NE4C1_11", + "CMT_TOP_NE4C1_11" + ], + [ + "CMT_FIFO_L_FAN1_11", + "CMT_TOP_FAN1_11" + ], + [ + "CMT_FIFO_LH10_3", + "CMT_TOP_LH10_3" + ], + [ + "CMT_FIFO_SE4C0_11", + "CMT_TOP_SE4C0_11" + ], + [ + "CMT_FIFO_L_FAN4_7", + "CMT_TOP_FAN4_7" + ], + [ + "CMT_FIFO_L_FAN2_3", + "CMT_TOP_FAN2_3" + ], + [ + "CMT_FIFO_NW4END3_2", + "CMT_TOP_NW4END3_2" + ], + [ + "CMT_FIFO_WW4A3_11", + "CMT_TOP_WW4A3_11" + ], + [ + "CMT_FIFO_L_IMUX25_8", + "CMT_TOP_IMUX25_8" + ], + [ + "CMT_FIFO_L_BYP5_2", + "CMT_TOP_BYP5_2" + ], + [ + "CMT_FIFO_EE4A1_9", + "CMT_TOP_EE4A1_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "CMT_TOP_OCLKDIV_3" + ], + [ + "CMT_FIFO_SE2A0_0", + "CMT_TOP_SE2A0_0" + ], + [ + "CMT_FIFO_L_CLK0_4", + "CMT_TOP_CLK0_4" + ], + [ + "CMT_FIFO_L_IMUX19_8", + "CMT_TOP_IMUX19_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_9", + "CMT_TOP_LOGIC_OUTS_L_B1_9" + ], + [ + "CMT_FIFO_NW2A0_4", + "CMT_TOP_NW2A0_4" + ], + [ + "CMT_FIFO_SE4C3_2", + "CMT_TOP_SE4C3_2" + ], + [ + "CMT_FIFO_SE2A1_5", + "CMT_TOP_SE2A1_5" + ], + [ + "CMT_FIFO_EE4BEG1_0", + "CMT_TOP_EE4BEG1_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_8", + "CMT_TOP_LOGIC_OUTS_L_B20_8" + ], + [ + "CMT_FIFO_L_IMUX45_5", + "CMT_TOP_IMUX45_5" + ], + [ + "CMT_FIFO_EL1BEG1_2", + "CMT_TOP_EL1BEG1_2" + ], + [ + "CMT_FIFO_L_FAN0_7", + "CMT_TOP_FAN0_7" + ], + [ + "CMT_FIFO_EE4B1_1", + "CMT_TOP_EE4B1_1" + ], + [ + "CMT_FIFO_L_IMUX21_5", + "CMT_TOP_IMUX21_5" + ], + [ + "CMT_FIFO_EL1BEG3_5", + "CMT_TOP_EL1BEG3_5" + ], + [ + "CMT_FIFO_EE4BEG1_2", + "CMT_TOP_EE4BEG1_2" + ], + [ + "CMT_FIFO_EE4BEG2_2", + "CMT_TOP_EE4BEG2_2" + ], + [ + "CMT_FIFO_LH8_6", + "CMT_TOP_LH8_6" + ], + [ + "CMT_FIFO_L_IMUX24_2", + "CMT_TOP_IMUX24_2" + ], + [ + "CMT_FIFO_L_IMUX32_4", + "CMT_TOP_IMUX32_4" + ], + [ + "CMT_FIFO_ER1BEG0_2", + "CMT_TOP_ER1BEG0_2" + ], + [ + "CMT_FIFO_EE4C3_5", + "CMT_TOP_EE4C3_5" + ], + [ + "CMT_FIFO_L_IMUX41_11", + "CMT_TOP_IMUX41_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_10", + "CMT_TOP_LOGIC_OUTS_L_B8_10" + ], + [ + "CMT_FIFO_WW4B3_6", + "CMT_TOP_WW4B3_6" + ], + [ + "CMT_FIFO_NW2A1_6", + "CMT_TOP_NW2A1_6" + ], + [ + "CMT_FIFO_L_BYP1_11", + "CMT_TOP_BYP1_11" + ], + [ + "CMT_FIFO_WW2A3_2", + "CMT_TOP_WW2A3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_2", + "CMT_TOP_LOGIC_OUTS_L_B11_2" + ], + [ + "CMT_FIFO_L_IMUX45_8", + "CMT_TOP_IMUX45_8" + ], + [ + "CMT_FIFO_WW2A1_10", + "CMT_TOP_WW2A1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_9", + "CMT_TOP_LOGIC_OUTS_L_B10_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_7", + "CMT_TOP_LOGIC_OUTS_L_B4_7" + ], + [ + "CMT_FIFO_L_IMUX6_6", + "CMT_TOP_IMUX6_6" + ], + [ + "CMT_FIFO_L_IMUX12_10", + "CMT_TOP_IMUX12_10" + ], + [ + "CMT_FIFO_L_CTRL0_0", + "CMT_TOP_CTRL0_0" + ], + [ + "CMT_FIFO_SW4A0_11", + "CMT_TOP_SW4A0_11" + ], + [ + "CMT_FIFO_L_FAN5_4", + "CMT_TOP_FAN5_4" + ], + [ + "CMT_FIFO_WW2END1_7", + "CMT_TOP_WW2END1_7" + ], + [ + "CMT_FIFO_WW2END0_0", + "CMT_TOP_WW2END0_0" + ], + [ + "CMT_FIFO_EE4B0_0", + "CMT_TOP_EE4B0_0" + ], + [ + "CMT_FIFO_NW4A1_6", + "CMT_TOP_NW4A1_6" + ], + [ + "CMT_FIFO_SE4BEG2_7", + "CMT_TOP_SE4BEG2_7" + ], + [ + "CMT_FIFO_SW4END0_5", + "CMT_TOP_SW4END0_5" + ], + [ + "CMT_FIFO_EE2BEG0_5", + "CMT_TOP_EE2BEG0_5" + ], + [ + "CMT_FIFO_L_CTRL1_7", + "CMT_TOP_CTRL1_7" + ], + [ + "CMT_FIFO_SW4END3_0", + "CMT_TOP_SW4END3_0" + ], + [ + "CMT_FIFO_SW4A2_1", + "CMT_TOP_SW4A2_1" + ], + [ + "CMT_FIFO_EL1BEG3_2", + "CMT_TOP_EL1BEG3_2" + ], + [ + "CMT_FIFO_SE4BEG1_11", + "CMT_TOP_SE4BEG1_11" + ], + [ + "CMT_FIFO_NW4END3_5", + "CMT_TOP_NW4END3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_11", + "CMT_TOP_LOGIC_OUTS_L_B16_11" + ], + [ + "CMT_FIFO_L_IMUX16_1", + "CMT_TOP_IMUX16_1" + ], + [ + "CMT_FIFO_WW4C3_4", + "CMT_TOP_WW4C3_4" + ], + [ + "CMT_FIFO_L_FAN0_10", + "CMT_TOP_FAN0_10" + ], + [ + "CMT_FIFO_L_FAN2_1", + "CMT_TOP_FAN2_1" + ], + [ + "CMT_FIFO_L_BYP3_8", + "CMT_TOP_BYP3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_11", + "CMT_TOP_LOGIC_OUTS_L_B20_11" + ], + [ + "CMT_FIFO_L_CLK0_3", + "CMT_TOP_CLK0_3" + ], + [ + "CMT_FIFO_WW4C0_8", + "CMT_TOP_WW4C0_8" + ], + [ + "CMT_FIFO_L_IMUX31_4", + "CMT_TOP_IMUX31_4" + ], + [ + "CMT_FIFO_L_IMUX43_7", + "CMT_TOP_IMUX43_7" + ], + [ + "CMT_FIFO_SE4C0_1", + "CMT_TOP_SE4C0_1" + ], + [ + "CMT_FIFO_EE4C3_8", + "CMT_TOP_EE4C3_8" + ], + [ + "CMT_FIFO_L_IMUX31_11", + "CMT_TOP_IMUX31_11" + ], + [ + "CMT_FIFO_NW4END0_0", + "CMT_TOP_NW4END0_0" + ], + [ + "CMT_FIFO_EE4C3_10", + "CMT_TOP_EE4C3_10" + ], + [ + "CMT_FIFO_NW4A1_1", + "CMT_TOP_NW4A1_1" + ], + [ + "CMT_FIFO_LH1_8", + "CMT_TOP_LH1_8" + ], + [ + "CMT_FIFO_L_IMUX3_11", + "CMT_TOP_IMUX3_11" + ], + [ + "CMT_FIFO_WW2A0_10", + "CMT_TOP_WW2A0_10" + ], + [ + "CMT_FIFO_L_FAN4_0", + "CMT_TOP_FAN4_0" + ], + [ + "CMT_FIFO_WW2A2_6", + "CMT_TOP_WW2A2_6" + ], + [ + "CMT_FIFO_L_IMUX42_6", + "CMT_TOP_IMUX42_6" + ], + [ + "CMT_FIFO_L_IMUX37_2", + "CMT_TOP_IMUX37_2" + ], + [ + "CMT_FIFO_EE4C2_11", + "CMT_TOP_EE4C2_11" + ], + [ + "CMT_FIFO_LH5_4", + "CMT_TOP_LH5_4" + ], + [ + "CMT_FIFO_EE2BEG1_0", + "CMT_TOP_EE2BEG1_0" + ], + [ + "CMT_FIFO_L_IMUX38_6", + "CMT_TOP_IMUX38_6" + ], + [ + "CMT_FIFO_EE4C2_8", + "CMT_TOP_EE4C2_8" + ], + [ + "CMT_FIFO_EE4BEG2_5", + "CMT_TOP_EE4BEG2_5" + ], + [ + "CMT_FIFO_WW4C1_7", + "CMT_TOP_WW4C1_7" + ], + [ + "CMT_FIFO_WW4C2_7", + "CMT_TOP_WW4C2_7" + ], + [ + "CMT_FIFO_L_BYP3_9", + "CMT_TOP_BYP3_9" + ], + [ + "CMT_FIFO_L_FAN4_11", + "CMT_TOP_FAN4_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_0", + "CMT_TOP_LOGIC_OUTS_L_B19_0" + ], + [ + "CMT_FIFO_SW4END0_4", + "CMT_TOP_SW4END0_4" + ], + [ + "CMT_FIFO_L_IMUX35_2", + "CMT_TOP_IMUX35_2" + ], + [ + "CMT_FIFO_WW4C1_10", + "CMT_TOP_WW4C1_10" + ], + [ + "CMT_FIFO_EE2A2_6", + "CMT_TOP_EE2A2_6" + ], + [ + "CMT_FIFO_EE4C3_11", + "CMT_TOP_EE4C3_11" + ], + [ + "CMT_FIFO_L_BYP7_10", + "CMT_TOP_BYP7_10" + ], + [ + "CMT_FIFO_L_IMUX29_8", + "CMT_TOP_IMUX29_8" + ], + [ + "CMT_FIFO_NE2A0_0", + "CMT_TOP_NE2A0_0" + ], + [ + "CMT_FIFO_NE2A0_9", + "CMT_TOP_NE2A0_9" + ], + [ + "CMT_FIFO_L_IMUX9_10", + "CMT_TOP_IMUX9_10" + ], + [ + "CMT_FIFO_WW2END1_0", + "CMT_TOP_WW2END1_0" + ], + [ + "CMT_FIFO_SE2A1_10", + "CMT_TOP_SE2A1_10" + ], + [ + "CMT_FIFO_L_IMUX34_6", + "CMT_TOP_IMUX34_6" + ], + [ + "CMT_FIFO_L_IMUX43_11", + "CMT_TOP_IMUX43_11" + ], + [ + "CMT_FIFO_EL1BEG2_10", + "CMT_TOP_EL1BEG2_10" + ], + [ + "CMT_FIFO_WW2END3_3", + "CMT_TOP_WW2END3_3" + ], + [ + "CMT_FIFO_L_IMUX15_2", + "CMT_TOP_IMUX15_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "CMT_TOP_OCLK_4" + ], + [ + "CMT_FIFO_EE4A3_1", + "CMT_TOP_EE4A3_1" + ], + [ + "CMT_FIFO_L_IMUX33_6", + "CMT_TOP_IMUX33_6" + ], + [ + "CMT_FIFO_WL1END3_5", + "CMT_TOP_WL1END3_5" + ], + [ + "CMT_FIFO_NE4C1_1", + "CMT_TOP_NE4C1_1" + ], + [ + "CMT_FIFO_ER1BEG0_3", + "CMT_TOP_ER1BEG0_3" + ], + [ + "CMT_FIFO_LH4_5", + "CMT_TOP_LH4_5" + ], + [ + "CMT_FIFO_L_IMUX16_3", + "CMT_TOP_IMUX16_3" + ], + [ + "CMT_FIFO_NE2A3_9", + "CMT_TOP_NE2A3_9" + ], + [ + "CMT_FIFO_NE4BEG2_10", + "CMT_TOP_NE4BEG2_10" + ], + [ + "CMT_FIFO_L_BYP3_1", + "CMT_TOP_BYP3_1" + ], + [ + "CMT_FIFO_WW4C3_11", + "CMT_TOP_WW4C3_11" + ], + [ + "CMT_FIFO_EL1BEG1_0", + "CMT_TOP_EL1BEG1_0" + ], + [ + "CMT_FIFO_L_CTRL0_11", + "CMT_TOP_CTRL0_11" + ], + [ + "CMT_FIFO_L_IMUX18_1", + "CMT_TOP_IMUX18_1" + ], + [ + "CMT_FIFO_SE4BEG0_2", + "CMT_TOP_SE4BEG0_2" + ], + [ + "CMT_FIFO_EE2BEG1_7", + "CMT_TOP_EE2BEG1_7" + ], + [ + "CMT_FIFO_EL1BEG1_7", + "CMT_TOP_EL1BEG1_7" + ], + [ + "CMT_FIFO_LH12_10", + "CMT_TOP_LH12_10" + ], + [ + "CMT_FIFO_ER1BEG0_6", + "CMT_TOP_ER1BEG0_6" + ], + [ + "CMT_FIFO_LH11_11", + "CMT_TOP_LH11_11" + ], + [ + "CMT_FIFO_L_IMUX5_6", + "CMT_TOP_IMUX5_6" + ], + [ + "CMT_FIFO_WW2END1_6", + "CMT_TOP_WW2END1_6" + ], + [ + "CMT_FIFO_WW4A2_6", + "CMT_TOP_WW4A2_6" + ], + [ + "CMT_FIFO_L_FAN4_2", + "CMT_TOP_FAN4_2" + ], + [ + "CMT_FIFO_WL1END0_6", + "CMT_TOP_WL1END0_6" + ], + [ + "CMT_FIFO_WW4END0_9", + "CMT_TOP_WW4END0_9" + ], + [ + "CMT_FIFO_WW4A0_11", + "CMT_TOP_WW4A0_11" + ], + [ + "CMT_FIFO_EE4B3_1", + "CMT_TOP_EE4B3_1" + ], + [ + "CMT_FIFO_L_IMUX19_1", + "CMT_TOP_IMUX19_1" + ], + [ + "CMT_FIFO_NW4A2_2", + "CMT_TOP_NW4A2_2" + ], + [ + "CMT_FIFO_L_IMUX3_10", + "CMT_TOP_IMUX3_10" + ], + [ + "CMT_FIFO_EE4C3_9", + "CMT_TOP_EE4C3_9" + ], + [ + "CMT_FIFO_SW4END2_8", + "CMT_TOP_SW4END2_8" + ], + [ + "CMT_FIFO_SE4C2_2", + "CMT_TOP_SE4C2_2" + ], + [ + "CMT_FIFO_NE2A2_11", + "CMT_TOP_NE2A2_11" + ], + [ + "CMT_FIFO_L_PHASER_RDCLK", + "CMT_PLL_PHASER_RDCLK_TOFIFO" + ], + [ + "CMT_FIFO_L_IMUX36_8", + "CMT_TOP_IMUX36_8" + ], + [ + "CMT_FIFO_L_IMUX44_11", + "CMT_TOP_IMUX44_11" + ], + [ + "CMT_FIFO_LH11_4", + "CMT_TOP_LH11_4" + ], + [ + "CMT_FIFO_L_BYP7_11", + "CMT_TOP_BYP7_11" + ], + [ + "CMT_FIFO_LH1_1", + "CMT_TOP_LH1_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "CMT_TOP_OCLKDIV_5" + ], + [ + "CMT_FIFO_LH6_3", + "CMT_TOP_LH6_3" + ], + [ + "CMT_FIFO_WW4C2_3", + "CMT_TOP_WW4C2_3" + ], + [ + "CMT_FIFO_NE4BEG3_9", + "CMT_TOP_NE4BEG3_9" + ], + [ + "CMT_FIFO_LH7_3", + "CMT_TOP_LH7_3" + ], + [ + "CMT_FIFO_L_IMUX1_5", + "CMT_TOP_IMUX1_5" + ], + [ + "CMT_FIFO_SW4A1_10", + "CMT_TOP_SW4A1_10" + ], + [ + "CMT_FIFO_L_FAN0_11", + "CMT_TOP_FAN0_11" + ], + [ + "CMT_FIFO_EE2BEG1_10", + "CMT_TOP_EE2BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX45_10", + "CMT_TOP_IMUX45_10" + ], + [ + "CMT_FIFO_NW4END0_7", + "CMT_TOP_NW4END0_7" + ], + [ + "CMT_FIFO_L_IMUX41_2", + "CMT_TOP_IMUX41_2" + ], + [ + "CMT_FIFO_EE4A1_4", + "CMT_TOP_EE4A1_4" + ], + [ + "CMT_FIFO_NE2A3_7", + "CMT_TOP_NE2A3_7" + ], + [ + "CMT_FIFO_L_IMUX19_5", + "CMT_TOP_IMUX19_5" + ], + [ + "CMT_FIFO_NE4C2_6", + "CMT_TOP_NE4C2_6" + ], + [ + "CMT_FIFO_L_IMUX0_6", + "CMT_TOP_IMUX0_6" + ], + [ + "CMT_FIFO_SE4C3_6", + "CMT_TOP_SE4C3_6" + ], + [ + "CMT_FIFO_L_IMUX12_6", + "CMT_TOP_IMUX12_6" + ], + [ + "CMT_FIFO_SE4C0_8", + "CMT_TOP_SE4C0_8" + ], + [ + "CMT_FIFO_L_IMUX38_4", + "CMT_TOP_IMUX38_4" + ], + [ + "CMT_FIFO_EE4C2_9", + "CMT_TOP_EE4C2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_9", + "CMT_TOP_LOGIC_OUTS_L_B13_9" + ], + [ + "CMT_FIFO_L_IMUX16_11", + "CMT_TOP_IMUX16_11" + ], + [ + "CMT_FIFO_L_IMUX28_7", + "CMT_TOP_IMUX28_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_5", + "CMT_TOP_LOGIC_OUTS_L_B11_5" + ], + [ + "CMT_FIFO_L_IMUX7_1", + "CMT_TOP_IMUX7_1" + ], + [ + "CMT_FIFO_MONITOR_N_8", + "CMT_TOP_MONITOR_N_8" + ], + [ + "CMT_FIFO_L_IMUX47_1", + "CMT_TOP_IMUX47_1" + ], + [ + "CMT_FIFO_L_FAN2_9", + "CMT_TOP_FAN2_9" + ], + [ + "CMT_FIFO_SE2A2_4", + "CMT_TOP_SE2A2_4" + ], + [ + "CMT_FIFO_LH4_3", + "CMT_TOP_LH4_3" + ], + [ + "CMT_FIFO_EE4A0_5", + "CMT_TOP_EE4A0_5" + ], + [ + "CMT_FIFO_L_CLK1_4", + "CMT_TOP_CLK1_4" + ], + [ + "CMT_FIFO_LH5_3", + "CMT_TOP_LH5_3" + ], + [ + "CMT_FIFO_LH10_0", + "CMT_TOP_LH10_0" + ], + [ + "CMT_FIFO_L_IMUX21_6", + "CMT_TOP_IMUX21_6" + ], + [ + "CMT_FIFO_NW4A3_10", + "CMT_TOP_NW4A3_10" + ], + [ + "CMT_FIFO_L_IMUX18_4", + "CMT_TOP_IMUX18_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_6", + "CMT_TOP_LOGIC_OUTS_L_B23_6" + ], + [ + "CMT_FIFO_NW2A0_8", + "CMT_TOP_NW2A0_8" + ], + [ + "CMT_FIFO_EE4A1_0", + "CMT_TOP_EE4A1_0" + ], + [ + "CMT_FIFO_SE4C2_10", + "CMT_TOP_SE4C2_10" + ], + [ + "CMT_FIFO_WW4END0_5", + "CMT_TOP_WW4END0_5" + ], + [ + "CMT_FIFO_SW4END3_4", + "CMT_TOP_SW4END3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_10", + "CMT_TOP_LOGIC_OUTS_L_B13_10" + ], + [ + "CMT_FIFO_WW4A1_1", + "CMT_TOP_WW4A1_1" + ], + [ + "CMT_FIFO_WW4END1_6", + "CMT_TOP_WW4END1_6" + ], + [ + "CMT_FIFO_SW2A1_1", + "CMT_TOP_SW2A1_1" + ], + [ + "CMT_FIFO_NW4A3_3", + "CMT_TOP_NW4A3_3" + ], + [ + "CMT_FIFO_L_FAN7_7", + "CMT_TOP_FAN7_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "CMT_TOP_ICLKDIV_6" + ], + [ + "CMT_FIFO_L_IMUX32_10", + "CMT_TOP_IMUX32_10" + ], + [ + "CMT_FIFO_L_IMUX0_7", + "CMT_TOP_IMUX0_7" + ], + [ + "CMT_FIFO_L_BYP3_5", + "CMT_TOP_BYP3_5" + ], + [ + "CMT_FIFO_EE4C0_5", + "CMT_TOP_EE4C0_5" + ], + [ + "CMT_FIFO_WR1END0_6", + "CMT_TOP_WR1END0_6" + ], + [ + "CMT_FIFO_SE4BEG1_2", + "CMT_TOP_SE4BEG1_2" + ], + [ + "CMT_FIFO_NW2A1_3", + "CMT_TOP_NW2A1_3" + ], + [ + "CMT_FIFO_L_IMUX10_5", + "CMT_TOP_IMUX10_5" + ], + [ + "CMT_FIFO_L_IMUX45_4", + "CMT_TOP_IMUX45_4" + ], + [ + "CMT_FIFO_EE4C3_2", + "CMT_TOP_EE4C3_2" + ], + [ + "CMT_FIFO_SE4BEG3_4", + "CMT_TOP_SE4BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_2", + "CMT_TOP_LOGIC_OUTS_L_B23_2" + ], + [ + "CMT_FIFO_ER1BEG0_10", + "CMT_TOP_ER1BEG0_10" + ], + [ + "CMT_FIFO_NW4A3_5", + "CMT_TOP_NW4A3_5" + ], + [ + "CMT_FIFO_LH9_0", + "CMT_TOP_LH9_0" + ], + [ + "CMT_FIFO_SW4A3_5", + "CMT_TOP_SW4A3_5" + ], + [ + "CMT_FIFO_WW4A3_6", + "CMT_TOP_WW4A3_6" + ], + [ + "CMT_FIFO_SE2A1_1", + "CMT_TOP_SE2A1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_1", + "CMT_TOP_LOGIC_OUTS_L_B19_1" + ], + [ + "CMT_FIFO_L_FAN5_9", + "CMT_TOP_FAN5_9" + ], + [ + "CMT_FIFO_NE4C3_7", + "CMT_TOP_NE4C3_7" + ], + [ + "CMT_FIFO_NW2A3_11", + "CMT_TOP_NW2A3_11" + ], + [ + "CMT_FIFO_WW4END2_3", + "CMT_TOP_WW4END2_3" + ], + [ + "CMT_FIFO_LH1_2", + "CMT_TOP_LH1_2" + ], + [ + "CMT_FIFO_SW4END2_2", + "CMT_TOP_SW4END2_2" + ], + [ + "CMT_FIFO_L_IMUX23_10", + "CMT_TOP_IMUX23_10" + ], + [ + "CMT_FIFO_WR1END3_9", + "CMT_TOP_WR1END3_9" + ], + [ + "CMT_FIFO_L_IMUX42_5", + "CMT_TOP_IMUX42_5" + ], + [ + "CMT_FIFO_NE4C1_7", + "CMT_TOP_NE4C1_7" + ], + [ + "CMT_FIFO_LH7_11", + "CMT_TOP_LH7_11" + ], + [ + "CMT_FIFO_L_BYP5_11", + "CMT_TOP_BYP5_11" + ], + [ + "CMT_FIFO_MONITOR_P_8", + "CMT_TOP_MONITOR_P_8" + ], + [ + "CMT_FIFO_SE4C0_9", + "CMT_TOP_SE4C0_9" + ], + [ + "CMT_FIFO_L_IMUX46_8", + "CMT_TOP_IMUX46_8" + ], + [ + "CMT_FIFO_MONITOR_P_10", + "CMT_TOP_MONITOR_P_10" + ], + [ + "CMT_FIFO_L_IMUX10_10", + "CMT_TOP_IMUX10_10" + ], + [ + "CMT_FIFO_L_IMUX4_9", + "CMT_TOP_IMUX4_9" + ], + [ + "CMT_FIFO_SW2A2_3", + "CMT_TOP_SW2A2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_5", + "CMT_TOP_LOGIC_OUTS_L_B15_5" + ], + [ + "CMT_FIFO_EE4B2_8", + "CMT_TOP_EE4B2_8" + ], + [ + "CMT_FIFO_L_IMUX17_6", + "CMT_TOP_IMUX17_6" + ], + [ + "CMT_FIFO_EL1BEG3_1", + "CMT_TOP_EL1BEG3_1" + ], + [ + "CMT_FIFO_L_IMUX34_9", + "CMT_TOP_IMUX34_9" + ], + [ + "CMT_FIFO_EL1BEG2_6", + "CMT_TOP_EL1BEG2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_10", + "CMT_TOP_LOGIC_OUTS_L_B4_10" + ], + [ + "CMT_FIFO_L_IMUX44_7", + "CMT_TOP_IMUX44_7" + ], + [ + "CMT_FIFO_SW4A3_11", + "CMT_TOP_SW4A3_11" + ], + [ + "CMT_FIFO_NW4A2_0", + "CMT_TOP_NW4A2_0" + ], + [ + "CMT_FIFO_LH7_8", + "CMT_TOP_LH7_8" + ], + [ + "CMT_FIFO_EE2BEG2_6", + "CMT_TOP_EE2BEG2_6" + ], + [ + "CMT_FIFO_SE4BEG0_1", + "CMT_TOP_SE4BEG0_1" + ], + [ + "CMT_FIFO_WW4B1_4", + "CMT_TOP_WW4B1_4" + ], + [ + "CMT_FIFO_L_CTRL0_9", + "CMT_TOP_CTRL0_9" + ], + [ + "CMT_FIFO_SE4C1_3", + "CMT_TOP_SE4C1_3" + ], + [ + "CMT_FIFO_WW2END2_11", + "CMT_TOP_WW2END2_11" + ], + [ + "CMT_FIFO_WR1END3_7", + "CMT_TOP_WR1END3_7" + ], + [ + "CMT_FIFO_WW4B2_2", + "CMT_TOP_WW4B2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_6", + "CMT_TOP_LOGIC_OUTS_L_B18_6" + ], + [ + "CMT_FIFO_LH3_6", + "CMT_TOP_LH3_6" + ], + [ + "CMT_FIFO_LH7_4", + "CMT_TOP_LH7_4" + ], + [ + "CMT_FIFO_LH12_1", + "CMT_TOP_LH12_1" + ], + [ + "CMT_FIFO_WW2A2_4", + "CMT_TOP_WW2A2_4" + ], + [ + "CMT_FIFO_ER1BEG2_1", + "CMT_TOP_ER1BEG2_1" + ], + [ + "CMT_FIFO_WW4A3_1", + "CMT_TOP_WW4A3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_10", + "CMT_TOP_LOGIC_OUTS_L_B22_10" + ], + [ + "CMT_FIFO_SW4END1_10", + "CMT_TOP_SW4END1_10" + ], + [ + "CMT_FIFO_L_IMUX30_9", + "CMT_TOP_IMUX30_9" + ], + [ + "CMT_FIFO_EE4C1_1", + "CMT_TOP_EE4C1_1" + ], + [ + "CMT_FIFO_NW2A2_7", + "CMT_TOP_NW2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_4", + "CMT_TOP_LOGIC_OUTS_L_B1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_6", + "CMT_TOP_LOGIC_OUTS_L_B9_6" + ], + [ + "CMT_FIFO_NE2A3_6", + "CMT_TOP_NE2A3_6" + ], + [ + "CMT_FIFO_L_IMUX30_8", + "CMT_TOP_IMUX30_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "CMT_TOP_ICLKDIV_10" + ], + [ + "CMT_FIFO_NW4END3_8", + "CMT_TOP_NW4END3_8" + ], + [ + "CMT_FIFO_EE2BEG3_8", + "CMT_TOP_EE2BEG3_8" + ], + [ + "CMT_FIFO_NW2A0_3", + "CMT_TOP_NW2A0_3" + ], + [ + "CMT_FIFO_WR1END0_10", + "CMT_TOP_WR1END0_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "CMT_TOP_ICLKDIV_11" + ], + [ + "CMT_FIFO_L_BYP2_0", + "CMT_TOP_BYP2_0" + ], + [ + "CMT_FIFO_L_IMUX2_5", + "CMT_TOP_IMUX2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_11", + "CMT_TOP_LOGIC_OUTS_L_B9_11" + ], + [ + "CMT_FIFO_NW2A2_5", + "CMT_TOP_NW2A2_5" + ], + [ + "CMT_FIFO_NW2A2_3", + "CMT_TOP_NW2A2_3" + ], + [ + "CMT_FIFO_NW4A0_9", + "CMT_TOP_NW4A0_9" + ], + [ + "CMT_FIFO_SW2A1_5", + "CMT_TOP_SW2A1_5" + ], + [ + "CMT_FIFO_SE2A3_10", + "CMT_TOP_SE2A3_10" + ], + [ + "CMT_FIFO_EE2BEG2_1", + "CMT_TOP_EE2BEG2_1" + ], + [ + "CMT_FIFO_L_CTRL1_1", + "CMT_TOP_CTRL1_1" + ], + [ + "CMT_FIFO_NE2A3_8", + "CMT_TOP_NE2A3_8" + ], + [ + "CMT_FIFO_L_IMUX30_4", + "CMT_TOP_IMUX30_4" + ], + [ + "CMT_FIFO_L_BYP3_4", + "CMT_TOP_BYP3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_5", + "CMT_TOP_LOGIC_OUTS_L_B17_5" + ], + [ + "CMT_FIFO_WW4B3_5", + "CMT_TOP_WW4B3_5" + ], + [ + "CMT_FIFO_EE4B1_7", + "CMT_TOP_EE4B1_7" + ], + [ + "CMT_FIFO_EE4C0_9", + "CMT_TOP_EE4C0_9" + ], + [ + "CMT_FIFO_EE2BEG0_0", + "CMT_TOP_EE2BEG0_0" + ], + [ + "CMT_FIFO_LH8_0", + "CMT_TOP_LH8_0" + ], + [ + "CMT_FIFO_WR1END1_9", + "CMT_TOP_WR1END1_9" + ], + [ + "CMT_FIFO_EE2BEG3_5", + "CMT_TOP_EE2BEG3_5" + ], + [ + "CMT_FIFO_SE2A1_4", + "CMT_TOP_SE2A1_4" + ], + [ + "CMT_FIFO_L_IMUX32_3", + "CMT_TOP_IMUX32_3" + ], + [ + "CMT_FIFO_L_BYP5_10", + "CMT_TOP_BYP5_10" + ], + [ + "CMT_FIFO_EE4B3_11", + "CMT_TOP_EE4B3_11" + ], + [ + "CMT_FIFO_NW2A3_1", + "CMT_TOP_NW2A3_1" + ], + [ + "CMT_FIFO_SE4C1_1", + "CMT_TOP_SE4C1_1" + ], + [ + "CMT_FIFO_L_IMUX46_4", + "CMT_TOP_IMUX46_4" + ], + [ + "CMT_FIFO_EE4B2_2", + "CMT_TOP_EE4B2_2" + ], + [ + "CMT_FIFO_SW4END3_1", + "CMT_TOP_SW4END3_1" + ], + [ + "CMT_FIFO_WW2A1_7", + "CMT_TOP_WW2A1_7" + ], + [ + "CMT_FIFO_EL1BEG0_6", + "CMT_TOP_EL1BEG0_6" + ], + [ + "CMT_FIFO_EE2A2_2", + "CMT_TOP_EE2A2_2" + ], + [ + "CMT_FIFO_WR1END3_5", + "CMT_TOP_WR1END3_5" + ], + [ + "CMT_FIFO_L_BYP5_6", + "CMT_TOP_BYP5_6" + ], + [ + "CMT_FIFO_L_IMUX30_11", + "CMT_TOP_IMUX30_11" + ], + [ + "CMT_FIFO_L_IMUX4_4", + "CMT_TOP_IMUX4_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_6", + "CMT_TOP_LOGIC_OUTS_L_B3_6" + ], + [ + "CMT_FIFO_L_IMUX44_9", + "CMT_TOP_IMUX44_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_6", + "CMT_TOP_LOGIC_OUTS_L_B20_6" + ], + [ + "CMT_FIFO_EE4B1_0", + "CMT_TOP_EE4B1_0" + ], + [ + "CMT_FIFO_L_IMUX26_4", + "CMT_TOP_IMUX26_4" + ], + [ + "CMT_FIFO_L_IMUX39_0", + "CMT_TOP_IMUX39_0" + ], + [ + "CMT_FIFO_NW4A0_11", + "CMT_TOP_NW4A0_11" + ], + [ + "CMT_FIFO_WW4C0_10", + "CMT_TOP_WW4C0_10" + ], + [ + "CMT_FIFO_L_IMUX45_9", + "CMT_TOP_IMUX45_9" + ], + [ + "CMT_FIFO_NE4C1_0", + "CMT_TOP_NE4C1_0" + ], + [ + "CMT_FIFO_EE4A2_9", + "CMT_TOP_EE4A2_9" + ], + [ + "CMT_FIFO_L_FAN1_10", + "CMT_TOP_FAN1_10" + ], + [ + "CMT_FIFO_ER1BEG3_11", + "CMT_TOP_ER1BEG3_11" + ], + [ + "CMT_FIFO_NW4END3_10", + "CMT_TOP_NW4END3_10" + ], + [ + "CMT_FIFO_L_IMUX28_8", + "CMT_TOP_IMUX28_8" + ], + [ + "CMT_FIFO_L_IMUX38_5", + "CMT_TOP_IMUX38_5" + ], + [ + "CMT_FIFO_L_IMUX38_2", + "CMT_TOP_IMUX38_2" + ], + [ + "CMT_FIFO_ER1BEG0_4", + "CMT_TOP_ER1BEG0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_3", + "CMT_TOP_LOGIC_OUTS_L_B5_3" + ], + [ + "CMT_FIFO_L_BYP2_8", + "CMT_TOP_BYP2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_3", + "CMT_TOP_LOGIC_OUTS_L_B17_3" + ], + [ + "CMT_FIFO_SW2A3_0", + "CMT_TOP_SW2A3_0" + ], + [ + "CMT_FIFO_WW4C1_11", + "CMT_TOP_WW4C1_11" + ], + [ + "CMT_FIFO_NE2A2_2", + "CMT_TOP_NE2A2_2" + ], + [ + "CMT_FIFO_L_IMUX25_6", + "CMT_TOP_IMUX25_6" + ], + [ + "CMT_FIFO_L_IMUX15_11", + "CMT_TOP_IMUX15_11" + ], + [ + "CMT_FIFO_L_IMUX10_8", + "CMT_TOP_IMUX10_8" + ], + [ + "CMT_FIFO_L_IMUX38_11", + "CMT_TOP_IMUX38_11" + ], + [ + "CMT_FIFO_EE4B0_10", + "CMT_TOP_EE4B0_10" + ], + [ + "CMT_FIFO_WW4END2_9", + "CMT_TOP_WW4END2_9" + ], + [ + "CMT_FIFO_L_IMUX31_6", + "CMT_TOP_IMUX31_6" + ], + [ + "CMT_FIFO_L_IMUX35_3", + "CMT_TOP_IMUX35_3" + ], + [ + "CMT_FIFO_SW2A2_0", + "CMT_TOP_SW2A2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_0", + "CMT_TOP_LOGIC_OUTS_L_B11_0" + ], + [ + "CMT_FIFO_NW4A0_5", + "CMT_TOP_NW4A0_5" + ], + [ + "CMT_FIFO_L_IMUX14_10", + "CMT_TOP_IMUX14_10" + ], + [ + "CMT_FIFO_NE4C3_6", + "CMT_TOP_NE4C3_6" + ], + [ + "CMT_FIFO_L_IMUX31_3", + "CMT_TOP_IMUX31_3" + ], + [ + "CMT_FIFO_WW4B0_10", + "CMT_TOP_WW4B0_10" + ], + [ + "CMT_FIFO_L_CLK1_8", + "CMT_TOP_CLK1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_8", + "CMT_TOP_LOGIC_OUTS_L_B17_8" + ], + [ + "CMT_FIFO_L_FAN6_7", + "CMT_TOP_FAN6_7" + ], + [ + "CMT_FIFO_LH6_1", + "CMT_TOP_LH6_1" + ], + [ + "CMT_FIFO_L_FAN3_0", + "CMT_TOP_FAN3_0" + ], + [ + "CMT_FIFO_WW4C3_10", + "CMT_TOP_WW4C3_10" + ], + [ + "CMT_FIFO_EE2A3_6", + "CMT_TOP_EE2A3_6" + ], + [ + "CMT_FIFO_EL1BEG0_0", + "CMT_TOP_EL1BEG0_0" + ], + [ + "CMT_FIFO_EE4BEG2_11", + "CMT_TOP_EE4BEG2_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "CMT_TOP_ICLK_11" + ], + [ + "CMT_FIFO_SE2A2_9", + "CMT_TOP_SE2A2_9" + ], + [ + "CMT_FIFO_L_IMUX43_8", + "CMT_TOP_IMUX43_8" + ], + [ + "CMT_FIFO_EE4C2_7", + "CMT_TOP_EE4C2_7" + ], + [ + "CMT_FIFO_EE2BEG3_6", + "CMT_TOP_EE2BEG3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_7", + "CMT_TOP_LOGIC_OUTS_L_B23_7" + ], + [ + "CMT_FIFO_NE4BEG0_1", + "CMT_TOP_NE4BEG0_1" + ], + [ + "CMT_FIFO_NW4A0_8", + "CMT_TOP_NW4A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_7", + "CMT_TOP_LOGIC_OUTS_L_B21_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_3", + "CMT_TOP_LOGIC_OUTS_L_B19_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_8", + "CMT_TOP_LOGIC_OUTS_L_B23_8" + ], + [ + "CMT_FIFO_L_FAN7_4", + "CMT_TOP_FAN7_4" + ], + [ + "CMT_FIFO_WW4A2_2", + "CMT_TOP_WW4A2_2" + ], + [ + "CMT_FIFO_SE4C2_11", + "CMT_TOP_SE4C2_11" + ], + [ + "CMT_FIFO_L_IMUX27_1", + "CMT_TOP_IMUX27_1" + ], + [ + "CMT_FIFO_ER1BEG1_4", + "CMT_TOP_ER1BEG1_4" + ], + [ + "CMT_FIFO_L_FAN2_10", + "CMT_TOP_FAN2_10" + ], + [ + "CMT_FIFO_WW2END2_8", + "CMT_TOP_WW2END2_8" + ], + [ + "CMT_FIFO_L_IMUX23_11", + "CMT_TOP_IMUX23_11" + ], + [ + "CMT_FIFO_EE4C3_4", + "CMT_TOP_EE4C3_4" + ], + [ + "CMT_FIFO_L_IMUX41_0", + "CMT_TOP_IMUX41_0" + ], + [ + "CMT_FIFO_ER1BEG1_11", + "CMT_TOP_ER1BEG1_11" + ], + [ + "CMT_FIFO_SE4C3_7", + "CMT_TOP_SE4C3_7" + ], + [ + "CMT_FIFO_L_IMUX7_10", + "CMT_TOP_IMUX7_10" + ], + [ + "CMT_FIFO_L_FAN4_3", + "CMT_TOP_FAN4_3" + ], + [ + "CMT_FIFO_L_IMUX35_5", + "CMT_TOP_IMUX35_5" + ], + [ + "CMT_FIFO_WW4A0_5", + "CMT_TOP_WW4A0_5" + ], + [ + "CMT_FIFO_L_IMUX47_0", + "CMT_TOP_IMUX47_0" + ], + [ + "CMT_FIFO_WW4B3_2", + "CMT_TOP_WW4B3_2" + ], + [ + "CMT_FIFO_L_IMUX6_7", + "CMT_TOP_IMUX6_7" + ], + [ + "CMT_FIFO_L_IMUX28_0", + "CMT_TOP_IMUX28_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_5", + "CMT_TOP_LOGIC_OUTS_L_B23_5" + ], + [ + "CMT_FIFO_LH2_2", + "CMT_TOP_LH2_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "CMT_TOP_OCLKDIV_11" + ], + [ + "CMT_FIFO_WW4B1_11", + "CMT_TOP_WW4B1_11" + ], + [ + "CMT_FIFO_MONITOR_N_0", + "CMT_TOP_MONITOR_N_0" + ], + [ + "CMT_FIFO_WW4A2_5", + "CMT_TOP_WW4A2_5" + ], + [ + "CMT_FIFO_SE4BEG2_9", + "CMT_TOP_SE4BEG2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_0", + "CMT_TOP_LOGIC_OUTS_L_B5_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_5", + "CMT_TOP_LOGIC_OUTS_L_B20_5" + ], + [ + "CMT_FIFO_SE4C1_11", + "CMT_TOP_SE4C1_11" + ], + [ + "CMT_FIFO_EE4C2_1", + "CMT_TOP_EE4C2_1" + ], + [ + "CMT_FIFO_EE4B3_8", + "CMT_TOP_EE4B3_8" + ], + [ + "CMT_FIFO_L_IMUX37_8", + "CMT_TOP_IMUX37_8" + ], + [ + "CMT_FIFO_LH3_7", + "CMT_TOP_LH3_7" + ], + [ + "CMT_FIFO_L_IMUX22_6", + "CMT_TOP_IMUX22_6" + ], + [ + "CMT_FIFO_SE2A0_5", + "CMT_TOP_SE2A0_5" + ], + [ + "CMT_FIFO_L_BYP4_2", + "CMT_TOP_BYP4_2" + ], + [ + "CMT_FIFO_MONITOR_P_6", + "CMT_TOP_MONITOR_P_6" + ], + [ + "CMT_FIFO_WW4END2_11", + "CMT_TOP_WW4END2_11" + ], + [ + "CMT_FIFO_SE4BEG3_8", + "CMT_TOP_SE4BEG3_8" + ], + [ + "CMT_FIFO_NW2A3_10", + "CMT_TOP_NW2A3_10" + ], + [ + "CMT_FIFO_L_IMUX32_5", + "CMT_TOP_IMUX32_5" + ], + [ + "CMT_FIFO_L_IMUX17_7", + "CMT_TOP_IMUX17_7" + ], + [ + "CMT_FIFO_SE2A3_2", + "CMT_TOP_SE2A3_2" + ], + [ + "CMT_FIFO_WW4END3_11", + "CMT_TOP_WW4END3_11" + ], + [ + "CMT_FIFO_L_IMUX42_7", + "CMT_TOP_IMUX42_7" + ], + [ + "CMT_FIFO_L_IMUX32_7", + "CMT_TOP_IMUX32_7" + ], + [ + "CMT_FIFO_L_IMUX0_2", + "CMT_TOP_IMUX0_2" + ], + [ + "CMT_FIFO_L_IMUX46_7", + "CMT_TOP_IMUX46_7" + ], + [ + "CMT_FIFO_L_IMUX31_7", + "CMT_TOP_IMUX31_7" + ], + [ + "CMT_FIFO_WL1END3_1", + "CMT_TOP_WL1END3_1" + ], + [ + "CMT_FIFO_WW4B1_2", + "CMT_TOP_WW4B1_2" + ], + [ + "CMT_FIFO_LH5_5", + "CMT_TOP_LH5_5" + ], + [ + "CMT_FIFO_LH10_1", + "CMT_TOP_LH10_1" + ], + [ + "CMT_FIFO_NE2A1_7", + "CMT_TOP_NE2A1_7" + ], + [ + "CMT_FIFO_L_IMUX0_10", + "CMT_TOP_IMUX0_10" + ], + [ + "CMT_FIFO_L_BYP2_10", + "CMT_TOP_BYP2_10" + ], + [ + "CMT_FIFO_L_CTRL1_6", + "CMT_TOP_CTRL1_6" + ], + [ + "CMT_FIFO_WR1END0_9", + "CMT_TOP_WR1END0_9" + ], + [ + "CMT_FIFO_L_BYP1_7", + "CMT_TOP_BYP1_7" + ], + [ + "CMT_FIFO_L_FAN1_9", + "CMT_TOP_FAN1_9" + ], + [ + "CMT_FIFO_WW4C2_5", + "CMT_TOP_WW4C2_5" + ], + [ + "CMT_FIFO_WL1END2_11", + "CMT_TOP_WL1END2_11" + ], + [ + "CMT_FIFO_NW4A3_11", + "CMT_TOP_NW4A3_11" + ], + [ + "CMT_FIFO_L_BYP6_5", + "CMT_TOP_BYP6_5" + ], + [ + "CMT_FIFO_EE4BEG3_1", + "CMT_TOP_EE4BEG3_1" + ], + [ + "CMT_FIFO_L_IMUX17_8", + "CMT_TOP_IMUX17_8" + ], + [ + "CMT_FIFO_WW2END3_0", + "CMT_TOP_WW2END3_0" + ], + [ + "CMT_FIFO_L_IMUX42_4", + "CMT_TOP_IMUX42_4" + ], + [ + "CMT_FIFO_NE4BEG3_3", + "CMT_TOP_NE4BEG3_3" + ], + [ + "CMT_FIFO_SE4C2_0", + "CMT_TOP_SE4C2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_6", + "CMT_TOP_LOGIC_OUTS_L_B5_6" + ], + [ + "CMT_FIFO_WW4C2_9", + "CMT_TOP_WW4C2_9" + ], + [ + "CMT_FIFO_WW2END2_4", + "CMT_TOP_WW2END2_4" + ], + [ + "CMT_FIFO_SW2A0_2", + "CMT_TOP_SW2A0_2" + ], + [ + "CMT_FIFO_EE4BEG2_6", + "CMT_TOP_EE4BEG2_6" + ], + [ + "CMT_FIFO_EE2BEG0_3", + "CMT_TOP_EE2BEG0_3" + ], + [ + "CMT_FIFO_L_IMUX47_4", + "CMT_TOP_IMUX47_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_6", + "CMT_TOP_LOGIC_OUTS_L_B11_6" + ], + [ + "CMT_FIFO_L_FAN6_5", + "CMT_TOP_FAN6_5" + ], + [ + "CMT_FIFO_EE2BEG3_3", + "CMT_TOP_EE2BEG3_3" + ], + [ + "CMT_FIFO_L_IMUX31_0", + "CMT_TOP_IMUX31_0" + ], + [ + "CMT_FIFO_WR1END1_3", + "CMT_TOP_WR1END1_3" + ], + [ + "CMT_FIFO_NW2A1_8", + "CMT_TOP_NW2A1_8" + ], + [ + "CMT_FIFO_L_IMUX42_3", + "CMT_TOP_IMUX42_3" + ], + [ + "CMT_FIFO_NW2A2_0", + "CMT_TOP_NW2A2_0" + ], + [ + "CMT_FIFO_L_BYP1_0", + "CMT_TOP_BYP1_0" + ], + [ + "CMT_FIFO_EE2BEG3_11", + "CMT_TOP_EE2BEG3_11" + ], + [ + "CMT_FIFO_L_FAN5_1", + "CMT_TOP_FAN5_1" + ], + [ + "CMT_FIFO_SW2A1_6", + "CMT_TOP_SW2A1_6" + ], + [ + "CMT_FIFO_NW2A3_7", + "CMT_TOP_NW2A3_7" + ], + [ + "CMT_FIFO_EE4C1_9", + "CMT_TOP_EE4C1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_11", + "CMT_TOP_LOGIC_OUTS_L_B22_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_2", + "CMT_TOP_LOGIC_OUTS_L_B5_2" + ], + [ + "CMT_FIFO_WW4B2_8", + "CMT_TOP_WW4B2_8" + ], + [ + "CMT_FIFO_EE4A0_1", + "CMT_TOP_EE4A0_1" + ], + [ + "CMT_FIFO_WW4END2_1", + "CMT_TOP_WW4END2_1" + ], + [ + "CMT_FIFO_WL1END2_10", + "CMT_TOP_WL1END2_10" + ], + [ + "CMT_FIFO_L_IMUX12_7", + "CMT_TOP_IMUX12_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_0", + "CMT_TOP_LOGIC_OUTS_L_B13_0" + ], + [ + "CMT_FIFO_SW4A2_3", + "CMT_TOP_SW4A2_3" + ], + [ + "CMT_FIFO_WL1END3_0", + "CMT_TOP_WL1END3_0" + ], + [ + "CMT_FIFO_SW4END2_6", + "CMT_TOP_SW4END2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_0", + "CMT_TOP_LOGIC_OUTS_L_B8_0" + ], + [ + "CMT_FIFO_SW4A0_1", + "CMT_TOP_SW4A0_1" + ], + [ + "CMT_FIFO_WW4END3_7", + "CMT_TOP_WW4END3_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "CMT_TOP_OCLKDIV_1" + ], + [ + "CMT_FIFO_EE4BEG0_9", + "CMT_TOP_EE4BEG0_9" + ], + [ + "CMT_FIFO_SE4BEG3_2", + "CMT_TOP_SE4BEG3_2" + ], + [ + "CMT_FIFO_NW4A0_10", + "CMT_TOP_NW4A0_10" + ], + [ + "CMT_FIFO_ER1BEG3_8", + "CMT_TOP_ER1BEG3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_5", + "CMT_TOP_LOGIC_OUTS_L_B10_5" + ], + [ + "CMT_FIFO_SW2A2_10", + "CMT_TOP_SW2A2_10" + ], + [ + "CMT_FIFO_L_BYP2_3", + "CMT_TOP_BYP2_3" + ], + [ + "CMT_FIFO_WW4C0_7", + "CMT_TOP_WW4C0_7" + ], + [ + "CMT_FIFO_L_IMUX9_8", + "CMT_TOP_IMUX9_8" + ], + [ + "CMT_FIFO_NW4END2_5", + "CMT_TOP_NW4END2_5" + ], + [ + "CMT_FIFO_L_IMUX30_2", + "CMT_TOP_IMUX30_2" + ], + [ + "CMT_FIFO_L_BYP7_8", + "CMT_TOP_BYP7_8" + ], + [ + "CMT_FIFO_WL1END3_10", + "CMT_TOP_WL1END3_10" + ], + [ + "CMT_FIFO_L_IMUX11_10", + "CMT_TOP_IMUX11_10" + ], + [ + "CMT_FIFO_L_FAN5_11", + "CMT_TOP_FAN5_11" + ], + [ + "CMT_FIFO_NE4BEG3_0", + "CMT_TOP_NE4BEG3_0" + ], + [ + "CMT_FIFO_EE2A2_7", + "CMT_TOP_EE2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_5", + "CMT_TOP_LOGIC_OUTS_L_B8_5" + ], + [ + "CMT_FIFO_WW4A2_10", + "CMT_TOP_WW4A2_10" + ], + [ + "CMT_FIFO_EE4C2_10", + "CMT_TOP_EE4C2_10" + ], + [ + "CMT_FIFO_L_IMUX8_10", + "CMT_TOP_IMUX8_10" + ], + [ + "CMT_FIFO_SW4A1_8", + "CMT_TOP_SW4A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_9", + "CMT_TOP_LOGIC_OUTS_L_B15_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_3", + "CMT_TOP_LOGIC_OUTS_L_B10_3" + ], + [ + "CMT_FIFO_EL1BEG1_3", + "CMT_TOP_EL1BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX7_0", + "CMT_TOP_IMUX7_0" + ], + [ + "CMT_FIFO_L_IMUX29_0", + "CMT_TOP_IMUX29_0" + ], + [ + "CMT_FIFO_WW4B0_8", + "CMT_TOP_WW4B0_8" + ], + [ + "CMT_FIFO_NE4BEG2_6", + "CMT_TOP_NE4BEG2_6" + ], + [ + "CMT_FIFO_L_FAN1_0", + "CMT_TOP_FAN1_0" + ], + [ + "CMT_FIFO_WW2END0_11", + "CMT_TOP_WW2END0_11" + ], + [ + "CMT_FIFO_L_FAN3_1", + "CMT_TOP_FAN3_1" + ], + [ + "CMT_FIFO_LH12_7", + "CMT_TOP_LH12_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_3", + "CMT_TOP_LOGIC_OUTS_L_B18_3" + ], + [ + "CMT_FIFO_ER1BEG0_9", + "CMT_TOP_ER1BEG0_9" + ], + [ + "CMT_FIFO_SW4END1_5", + "CMT_TOP_SW4END1_5" + ], + [ + "CMT_FIFO_EE2BEG1_5", + "CMT_TOP_EE2BEG1_5" + ], + [ + "CMT_FIFO_EE2BEG2_5", + "CMT_TOP_EE2BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX14_5", + "CMT_TOP_IMUX14_5" + ], + [ + "CMT_FIFO_WW4A0_7", + "CMT_TOP_WW4A0_7" + ], + [ + "CMT_FIFO_L_IMUX23_6", + "CMT_TOP_IMUX23_6" + ], + [ + "CMT_FIFO_SW4END3_7", + "CMT_TOP_SW4END3_7" + ], + [ + "CMT_FIFO_L_IMUX46_3", + "CMT_TOP_IMUX46_3" + ], + [ + "CMT_FIFO_WR1END0_1", + "CMT_TOP_WR1END0_1" + ], + [ + "CMT_FIFO_SE4BEG2_2", + "CMT_TOP_SE4BEG2_2" + ], + [ + "CMT_FIFO_WW4END3_6", + "CMT_TOP_WW4END3_6" + ], + [ + "CMT_FIFO_SW4END2_4", + "CMT_TOP_SW4END2_4" + ], + [ + "CMT_FIFO_WW2A2_11", + "CMT_TOP_WW2A2_11" + ], + [ + "CMT_FIFO_WW2A2_0", + "CMT_TOP_WW2A2_0" + ], + [ + "CMT_FIFO_SE4C2_6", + "CMT_TOP_SE4C2_6" + ], + [ + "CMT_FIFO_SW2A3_1", + "CMT_TOP_SW2A3_1" + ], + [ + "CMT_FIFO_EE4C3_7", + "CMT_TOP_EE4C3_7" + ], + [ + "CMT_FIFO_EE4A2_8", + "CMT_TOP_EE4A2_8" + ], + [ + "CMT_FIFO_NE4BEG2_0", + "CMT_TOP_NE4BEG2_0" + ], + [ + "CMT_FIFO_NE4C1_6", + "CMT_TOP_NE4C1_6" + ], + [ + "CMT_FIFO_NE4C0_4", + "CMT_TOP_NE4C0_4" + ], + [ + "CMT_FIFO_L_IMUX13_6", + "CMT_TOP_IMUX13_6" + ], + [ + "CMT_FIFO_LH2_4", + "CMT_TOP_LH2_4" + ], + [ + "CMT_FIFO_LH1_10", + "CMT_TOP_LH1_10" + ], + [ + "CMT_FIFO_WW2END0_10", + "CMT_TOP_WW2END0_10" + ], + [ + "CMT_FIFO_L_IMUX7_9", + "CMT_TOP_IMUX7_9" + ], + [ + "CMT_FIFO_L_IMUX20_7", + "CMT_TOP_IMUX20_7" + ], + [ + "CMT_FIFO_NW2A3_6", + "CMT_TOP_NW2A3_6" + ], + [ + "CMT_FIFO_ER1BEG1_8", + "CMT_TOP_ER1BEG1_8" + ], + [ + "CMT_FIFO_SE2A0_6", + "CMT_TOP_SE2A0_6" + ], + [ + "CMT_FIFO_NW4A1_7", + "CMT_TOP_NW4A1_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "CMT_TOP_ICLK_2" + ], + [ + "CMT_FIFO_L_IMUX10_7", + "CMT_TOP_IMUX10_7" + ], + [ + "CMT_FIFO_EE4B0_3", + "CMT_TOP_EE4B0_3" + ], + [ + "CMT_FIFO_NE4C2_2", + "CMT_TOP_NE4C2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_8", + "CMT_TOP_LOGIC_OUTS_L_B19_8" + ], + [ + "CMT_FIFO_L_IMUX47_2", + "CMT_TOP_IMUX47_2" + ], + [ + "CMT_FIFO_EE4B0_9", + "CMT_TOP_EE4B0_9" + ], + [ + "CMT_FIFO_NW4A3_0", + "CMT_TOP_NW4A3_0" + ], + [ + "CMT_FIFO_NW4A0_7", + "CMT_TOP_NW4A0_7" + ], + [ + "CMT_FIFO_NE4C0_2", + "CMT_TOP_NE4C0_2" + ], + [ + "CMT_FIFO_WW2A2_5", + "CMT_TOP_WW2A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_5", + "CMT_TOP_LOGIC_OUTS_L_B2_5" + ], + [ + "CMT_FIFO_WW4B2_1", + "CMT_TOP_WW4B2_1" + ], + [ + "CMT_FIFO_WW2END1_8", + "CMT_TOP_WW2END1_8" + ], + [ + "CMT_FIFO_L_IMUX38_0", + "CMT_TOP_IMUX38_0" + ], + [ + "CMT_FIFO_L_IMUX14_11", + "CMT_TOP_IMUX14_11" + ], + [ + "CMT_FIFO_SE4BEG2_1", + "CMT_TOP_SE4BEG2_1" + ], + [ + "CMT_FIFO_L_IMUX36_6", + "CMT_TOP_IMUX36_6" + ], + [ + "CMT_FIFO_L_IMUX37_11", + "CMT_TOP_IMUX37_11" + ], + [ + "CMT_FIFO_EE4BEG3_11", + "CMT_TOP_EE4BEG3_11" + ], + [ + "CMT_FIFO_WW4A0_4", + "CMT_TOP_WW4A0_4" + ], + [ + "CMT_FIFO_EE4BEG1_5", + "CMT_TOP_EE4BEG1_5" + ], + [ + "CMT_FIFO_EE4BEG2_10", + "CMT_TOP_EE4BEG2_10" + ], + [ + "CMT_FIFO_NE2A0_3", + "CMT_TOP_NE2A0_3" + ], + [ + "CMT_FIFO_NE2A0_1", + "CMT_TOP_NE2A0_1" + ], + [ + "CMT_FIFO_EE4A1_6", + "CMT_TOP_EE4A1_6" + ], + [ + "CMT_FIFO_L_FAN7_10", + "CMT_TOP_FAN7_10" + ], + [ + "CMT_FIFO_L_IMUX37_0", + "CMT_TOP_IMUX37_0" + ], + [ + "CMT_FIFO_SW4A3_7", + "CMT_TOP_SW4A3_7" + ], + [ + "CMT_FIFO_LH11_8", + "CMT_TOP_LH11_8" + ], + [ + "CMT_FIFO_L_BYP5_4", + "CMT_TOP_BYP5_4" + ], + [ + "CMT_FIFO_WL1END0_4", + "CMT_TOP_WL1END0_4" + ], + [ + "CMT_FIFO_L_IMUX40_8", + "CMT_TOP_IMUX40_8" + ], + [ + "CMT_FIFO_LH8_4", + "CMT_TOP_LH8_4" + ], + [ + "CMT_FIFO_EL1BEG2_4", + "CMT_TOP_EL1BEG2_4" + ], + [ + "CMT_FIFO_EE2A3_7", + "CMT_TOP_EE2A3_7" + ], + [ + "CMT_FIFO_NE4C0_11", + "CMT_TOP_NE4C0_11" + ], + [ + "CMT_FIFO_WW2A0_2", + "CMT_TOP_WW2A0_2" + ], + [ + "CMT_FIFO_WW2A3_0", + "CMT_TOP_WW2A3_0" + ], + [ + "CMT_FIFO_WW4A3_7", + "CMT_TOP_WW4A3_7" + ], + [ + "CMT_FIFO_SE2A0_1", + "CMT_TOP_SE2A0_1" + ], + [ + "CMT_FIFO_WW4C1_8", + "CMT_TOP_WW4C1_8" + ], + [ + "CMT_FIFO_NW4END3_1", + "CMT_TOP_NW4END3_1" + ], + [ + "CMT_FIFO_L_IMUX11_7", + "CMT_TOP_IMUX11_7" + ], + [ + "CMT_FIFO_NE4C1_5", + "CMT_TOP_NE4C1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_7", + "CMT_TOP_LOGIC_OUTS_L_B8_7" + ], + [ + "CMT_FIFO_L_IMUX41_6", + "CMT_TOP_IMUX41_6" + ], + [ + "CMT_FIFO_SE4BEG3_5", + "CMT_TOP_SE4BEG3_5" + ], + [ + "CMT_FIFO_L_IMUX6_2", + "CMT_TOP_IMUX6_2" + ], + [ + "CMT_FIFO_L_IMUX12_8", + "CMT_TOP_IMUX12_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_4", + "CMT_TOP_LOGIC_OUTS_L_B22_4" + ], + [ + "CMT_FIFO_SW4A1_11", + "CMT_TOP_SW4A1_11" + ], + [ + "CMT_FIFO_L_FAN5_7", + "CMT_TOP_FAN5_7" + ], + [ + "CMT_FIFO_L_CLK0_0", + "CMT_TOP_CLK0_0" + ], + [ + "CMT_FIFO_L_IMUX20_9", + "CMT_TOP_IMUX20_9" + ], + [ + "CMT_FIFO_L_BYP6_11", + "CMT_TOP_BYP6_11" + ], + [ + "CMT_FIFO_SW4A0_4", + "CMT_TOP_SW4A0_4" + ], + [ + "CMT_FIFO_EE2BEG0_8", + "CMT_TOP_EE2BEG0_8" + ], + [ + "CMT_FIFO_NE4BEG0_8", + "CMT_TOP_NE4BEG0_8" + ], + [ + "CMT_FIFO_LH4_4", + "CMT_TOP_LH4_4" + ], + [ + "CMT_FIFO_L_IMUX34_2", + "CMT_TOP_IMUX34_2" + ], + [ + "CMT_FIFO_L_IMUX0_1", + "CMT_TOP_IMUX0_1" + ], + [ + "CMT_FIFO_NW2A2_8", + "CMT_TOP_NW2A2_8" + ], + [ + "CMT_FIFO_L_IMUX10_2", + "CMT_TOP_IMUX10_2" + ], + [ + "CMT_FIFO_L_FAN0_1", + "CMT_TOP_FAN0_1" + ], + [ + "CMT_FIFO_LH12_4", + "CMT_TOP_LH12_4" + ], + [ + "CMT_FIFO_EL1BEG3_4", + "CMT_TOP_EL1BEG3_4" + ], + [ + "CMT_FIFO_WW4END0_11", + "CMT_TOP_WW4END0_11" + ], + [ + "CMT_FIFO_EE2A3_0", + "CMT_TOP_EE2A3_0" + ], + [ + "CMT_FIFO_L_IMUX12_9", + "CMT_TOP_IMUX12_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_4", + "CMT_TOP_LOGIC_OUTS_L_B18_4" + ], + [ + "CMT_FIFO_EE4C3_0", + "CMT_TOP_EE4C3_0" + ], + [ + "CMT_FIFO_NW4END1_0", + "CMT_TOP_NW4END1_0" + ], + [ + "CMT_FIFO_SE4C0_3", + "CMT_TOP_SE4C0_3" + ], + [ + "CMT_FIFO_L_IMUX2_6", + "CMT_TOP_IMUX2_6" + ], + [ + "CMT_FIFO_WW4END0_6", + "CMT_TOP_WW4END0_6" + ], + [ + "CMT_FIFO_L_FAN6_10", + "CMT_TOP_FAN6_10" + ], + [ + "CMT_FIFO_L_IMUX9_4", + "CMT_TOP_IMUX9_4" + ], + [ + "CMT_FIFO_EE4BEG1_1", + "CMT_TOP_EE4BEG1_1" + ], + [ + "CMT_FIFO_L_IMUX32_9", + "CMT_TOP_IMUX32_9" + ], + [ + "CMT_FIFO_EE2A1_4", + "CMT_TOP_EE2A1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_8", + "CMT_TOP_LOGIC_OUTS_L_B11_8" + ], + [ + "CMT_FIFO_L_IMUX43_4", + "CMT_TOP_IMUX43_4" + ], + [ + "CMT_FIFO_NW4A0_3", + "CMT_TOP_NW4A0_3" + ], + [ + "CMT_FIFO_WW4END3_2", + "CMT_TOP_WW4END3_2" + ], + [ + "CMT_FIFO_NW4END1_2", + "CMT_TOP_NW4END1_2" + ], + [ + "CMT_FIFO_EL1BEG3_9", + "CMT_TOP_EL1BEG3_9" + ], + [ + "CMT_FIFO_L_FAN3_9", + "CMT_TOP_FAN3_9" + ], + [ + "CMT_FIFO_EE4B2_3", + "CMT_TOP_EE4B2_3" + ], + [ + "CMT_FIFO_WW4A1_2", + "CMT_TOP_WW4A1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_11", + "CMT_TOP_LOGIC_OUTS_L_B13_11" + ], + [ + "CMT_FIFO_LH5_10", + "CMT_TOP_LH5_10" + ], + [ + "CMT_FIFO_EE4BEG0_11", + "CMT_TOP_EE4BEG0_11" + ], + [ + "CMT_FIFO_EE4A0_6", + "CMT_TOP_EE4A0_6" + ], + [ + "CMT_FIFO_LH10_5", + "CMT_TOP_LH10_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_6", + "CMT_TOP_LOGIC_OUTS_L_B13_6" + ], + [ + "CMT_FIFO_EE4BEG3_8", + "CMT_TOP_EE4BEG3_8" + ], + [ + "CMT_FIFO_L_IMUX17_4", + "CMT_TOP_IMUX17_4" + ], + [ + "CMT_FIFO_L_IMUX6_4", + "CMT_TOP_IMUX6_4" + ], + [ + "CMT_FIFO_LH11_0", + "CMT_TOP_LH11_0" + ], + [ + "CMT_FIFO_L_IMUX30_0", + "CMT_TOP_IMUX30_0" + ], + [ + "CMT_FIFO_L_FAN6_9", + "CMT_TOP_FAN6_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "CMT_TOP_ICLK_5" + ], + [ + "CMT_FIFO_L_IMUX36_1", + "CMT_TOP_IMUX36_1" + ], + [ + "CMT_FIFO_L_IMUX3_0", + "CMT_TOP_IMUX3_0" + ], + [ + "CMT_FIFO_L_IMUX41_7", + "CMT_TOP_IMUX41_7" + ], + [ + "CMT_FIFO_L_IMUX6_3", + "CMT_TOP_IMUX6_3" + ], + [ + "CMT_FIFO_NE2A3_1", + "CMT_TOP_NE2A3_1" + ], + [ + "CMT_FIFO_ER1BEG3_4", + "CMT_TOP_ER1BEG3_4" + ], + [ + "CMT_FIFO_L_IMUX8_1", + "CMT_TOP_IMUX8_1" + ], + [ + "CMT_FIFO_SE2A0_3", + "CMT_TOP_SE2A0_3" + ], + [ + "CMT_FIFO_EE4B3_2", + "CMT_TOP_EE4B3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_8", + "CMT_TOP_LOGIC_OUTS_L_B5_8" + ], + [ + "CMT_FIFO_NW4END0_1", + "CMT_TOP_NW4END0_1" + ], + [ + "CMT_FIFO_EL1BEG1_10", + "CMT_TOP_EL1BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX5_5", + "CMT_TOP_IMUX5_5" + ], + [ + "CMT_FIFO_L_FAN2_0", + "CMT_TOP_FAN2_0" + ], + [ + "CMT_FIFO_EE4B0_5", + "CMT_TOP_EE4B0_5" + ], + [ + "CMT_FIFO_NW4A2_4", + "CMT_TOP_NW4A2_4" + ], + [ + "CMT_FIFO_NW4END2_0", + "CMT_TOP_NW4END2_0" + ], + [ + "CMT_FIFO_WW4END3_8", + "CMT_TOP_WW4END3_8" + ], + [ + "CMT_FIFO_LH9_4", + "CMT_TOP_LH9_4" + ], + [ + "CMT_FIFO_NE4BEG1_7", + "CMT_TOP_NE4BEG1_7" + ], + [ + "CMT_FIFO_SW4A1_9", + "CMT_TOP_SW4A1_9" + ], + [ + "CMT_FIFO_SE4BEG1_4", + "CMT_TOP_SE4BEG1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_2", + "CMT_TOP_LOGIC_OUTS_L_B7_2" + ], + [ + "CMT_FIFO_L_CTRL1_9", + "CMT_TOP_CTRL1_9" + ], + [ + "CMT_FIFO_L_IMUX13_2", + "CMT_TOP_IMUX13_2" + ], + [ + "CMT_FIFO_WW4A1_11", + "CMT_TOP_WW4A1_11" + ], + [ + "CMT_FIFO_L_IMUX25_1", + "CMT_TOP_IMUX25_1" + ], + [ + "CMT_FIFO_L_FAN4_9", + "CMT_TOP_FAN4_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "CMT_TOP_ICLK_4" + ], + [ + "CMT_FIFO_SW2A1_11", + "CMT_TOP_SW2A1_11" + ], + [ + "CMT_FIFO_EE4BEG3_7", + "CMT_TOP_EE4BEG3_7" + ], + [ + "CMT_FIFO_SE4BEG1_9", + "CMT_TOP_SE4BEG1_9" + ], + [ + "CMT_FIFO_WW4C0_3", + "CMT_TOP_WW4C0_3" + ], + [ + "CMT_FIFO_SW2A1_3", + "CMT_TOP_SW2A1_3" + ], + [ + "CMT_FIFO_SE4C0_5", + "CMT_TOP_SE4C0_5" + ], + [ + "CMT_FIFO_EE2A0_5", + "CMT_TOP_EE2A0_5" + ], + [ + "CMT_FIFO_SE4C1_4", + "CMT_TOP_SE4C1_4" + ], + [ + "CMT_FIFO_EL1BEG0_8", + "CMT_TOP_EL1BEG0_8" + ], + [ + "CMT_FIFO_WW4A1_8", + "CMT_TOP_WW4A1_8" + ], + [ + "CMT_FIFO_NW2A1_7", + "CMT_TOP_NW2A1_7" + ], + [ + "CMT_FIFO_NE2A1_2", + "CMT_TOP_NE2A1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_8", + "CMT_TOP_LOGIC_OUTS_L_B8_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_0", + "CMT_TOP_LOGIC_OUTS_L_B12_0" + ], + [ + "CMT_FIFO_SW4A3_2", + "CMT_TOP_SW4A3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_9", + "CMT_TOP_LOGIC_OUTS_L_B5_9" + ], + [ + "CMT_FIFO_L_CTRL1_3", + "CMT_TOP_CTRL1_3" + ], + [ + "CMT_FIFO_L_IMUX20_11", + "CMT_TOP_IMUX20_11" + ], + [ + "CMT_FIFO_ER1BEG3_0", + "CMT_TOP_ER1BEG3_0" + ], + [ + "CMT_FIFO_NW4A2_8", + "CMT_TOP_NW4A2_8" + ], + [ + "CMT_FIFO_NE4BEG0_2", + "CMT_TOP_NE4BEG0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_7", + "CMT_TOP_LOGIC_OUTS_L_B22_7" + ], + [ + "CMT_FIFO_SW4END0_10", + "CMT_TOP_SW4END0_10" + ], + [ + "CMT_FIFO_EE2A1_7", + "CMT_TOP_EE2A1_7" + ], + [ + "CMT_FIFO_NE4BEG0_6", + "CMT_TOP_NE4BEG0_6" + ], + [ + "CMT_FIFO_LH9_5", + "CMT_TOP_LH9_5" + ], + [ + "CMT_FIFO_EE2BEG2_3", + "CMT_TOP_EE2BEG2_3" + ], + [ + "CMT_FIFO_L_IMUX40_6", + "CMT_TOP_IMUX40_6" + ], + [ + "CMT_FIFO_WW4END1_4", + "CMT_TOP_WW4END1_4" + ], + [ + "CMT_FIFO_NE2A2_9", + "CMT_TOP_NE2A2_9" + ], + [ + "CMT_FIFO_SW2A1_2", + "CMT_TOP_SW2A1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "CMT_TOP_OCLK_8" + ], + [ + "CMT_FIFO_EE2A0_7", + "CMT_TOP_EE2A0_7" + ], + [ + "CMT_FIFO_WW4B0_7", + "CMT_TOP_WW4B0_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "CMT_TOP_OCLKDIV_9" + ], + [ + "CMT_FIFO_L_CTRL1_4", + "CMT_TOP_CTRL1_4" + ], + [ + "CMT_FIFO_L_IMUX37_7", + "CMT_TOP_IMUX37_7" + ], + [ + "CMT_FIFO_WW4A2_4", + "CMT_TOP_WW4A2_4" + ], + [ + "CMT_FIFO_MONITOR_N_6", + "CMT_TOP_MONITOR_N_6" + ], + [ + "CMT_FIFO_WR1END0_8", + "CMT_TOP_WR1END0_8" + ], + [ + "CMT_FIFO_WW2END3_4", + "CMT_TOP_WW2END3_4" + ], + [ + "CMT_FIFO_L_BYP1_2", + "CMT_TOP_BYP1_2" + ], + [ + "CMT_FIFO_L_IMUX46_11", + "CMT_TOP_IMUX46_11" + ], + [ + "CMT_FIFO_EE4BEG0_3", + "CMT_TOP_EE4BEG0_3" + ], + [ + "CMT_FIFO_L_BYP0_9", + "CMT_TOP_BYP0_9" + ], + [ + "CMT_FIFO_EE4BEG0_7", + "CMT_TOP_EE4BEG0_7" + ], + [ + "CMT_FIFO_SE4BEG0_6", + "CMT_TOP_SE4BEG0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_8", + "CMT_TOP_LOGIC_OUTS_L_B18_8" + ], + [ + "CMT_FIFO_L_IMUX27_11", + "CMT_TOP_IMUX27_11" + ], + [ + "CMT_FIFO_SE2A1_6", + "CMT_TOP_SE2A1_6" + ], + [ + "CMT_FIFO_NW4A0_4", + "CMT_TOP_NW4A0_4" + ], + [ + "CMT_FIFO_L_IMUX39_1", + "CMT_TOP_IMUX39_1" + ], + [ + "CMT_FIFO_EE4C2_4", + "CMT_TOP_EE4C2_4" + ], + [ + "CMT_FIFO_NE2A0_5", + "CMT_TOP_NE2A0_5" + ], + [ + "CMT_FIFO_L_CLK0_5", + "CMT_TOP_CLK0_5" + ], + [ + "CMT_FIFO_L_IMUX24_0", + "CMT_TOP_IMUX24_0" + ], + [ + "CMT_FIFO_EE4A2_5", + "CMT_TOP_EE4A2_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "CMT_TOP_OCLK_6" + ], + [ + "CMT_FIFO_L_IMUX8_7", + "CMT_TOP_IMUX8_7" + ], + [ + "CMT_FIFO_L_IMUX36_0", + "CMT_TOP_IMUX36_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_10", + "CMT_TOP_LOGIC_OUTS_L_B11_10" + ], + [ + "CMT_FIFO_L_IMUX39_2", + "CMT_TOP_IMUX39_2" + ], + [ + "CMT_FIFO_L_IMUX9_6", + "CMT_TOP_IMUX9_6" + ], + [ + "CMT_FIFO_NW4A1_4", + "CMT_TOP_NW4A1_4" + ], + [ + "CMT_FIFO_EE4C1_2", + "CMT_TOP_EE4C1_2" + ], + [ + "CMT_FIFO_L_IMUX44_0", + "CMT_TOP_IMUX44_0" + ], + [ + "CMT_FIFO_L_IMUX14_6", + "CMT_TOP_IMUX14_6" + ], + [ + "CMT_FIFO_L_IMUX16_10", + "CMT_TOP_IMUX16_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_5", + "CMT_TOP_LOGIC_OUTS_L_B19_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_4", + "CMT_TOP_LOGIC_OUTS_L_B15_4" + ], + [ + "CMT_FIFO_EE4A0_3", + "CMT_TOP_EE4A0_3" + ], + [ + "CMT_FIFO_L_FAN6_2", + "CMT_TOP_FAN6_2" + ], + [ + "CMT_FIFO_WW4B2_11", + "CMT_TOP_WW4B2_11" + ], + [ + "CMT_FIFO_L_BYP0_11", + "CMT_TOP_BYP0_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "CMT_TOP_ICLKDIV_0" + ], + [ + "CMT_FIFO_WW4C2_0", + "CMT_TOP_WW4C2_0" + ], + [ + "CMT_FIFO_L_IMUX28_1", + "CMT_TOP_IMUX28_1" + ], + [ + "CMT_FIFO_WW4B1_6", + "CMT_TOP_WW4B1_6" + ], + [ + "CMT_FIFO_EE4BEG0_4", + "CMT_TOP_EE4BEG0_4" + ], + [ + "CMT_FIFO_EE2A2_3", + "CMT_TOP_EE2A2_3" + ], + [ + "CMT_FIFO_EE4BEG1_9", + "CMT_TOP_EE4BEG1_9" + ], + [ + "CMT_FIFO_SE2A1_2", + "CMT_TOP_SE2A1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "CMT_TOP_ICLK_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_1", + "CMT_TOP_LOGIC_OUTS_L_B1_1" + ], + [ + "CMT_FIFO_WR1END2_6", + "CMT_TOP_WR1END2_6" + ], + [ + "CMT_FIFO_NW4END0_9", + "CMT_TOP_NW4END0_9" + ], + [ + "CMT_FIFO_EE4C2_3", + "CMT_TOP_EE4C2_3" + ], + [ + "CMT_FIFO_SE4C0_7", + "CMT_TOP_SE4C0_7" + ], + [ + "CMT_FIFO_L_IMUX15_7", + "CMT_TOP_IMUX15_7" + ], + [ + "CMT_FIFO_L_FAN0_9", + "CMT_TOP_FAN0_9" + ], + [ + "CMT_FIFO_SW4A3_6", + "CMT_TOP_SW4A3_6" + ], + [ + "CMT_FIFO_L_IMUX35_7", + "CMT_TOP_IMUX35_7" + ], + [ + "CMT_FIFO_ER1BEG0_5", + "CMT_TOP_ER1BEG0_5" + ], + [ + "CMT_FIFO_L_IMUX6_0", + "CMT_TOP_IMUX6_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_4", + "CMT_TOP_LOGIC_OUTS_L_B0_4" + ], + [ + "CMT_FIFO_NE4C0_6", + "CMT_TOP_NE4C0_6" + ], + [ + "CMT_FIFO_EE2A0_8", + "CMT_TOP_EE2A0_8" + ], + [ + "CMT_FIFO_EE4BEG3_4", + "CMT_TOP_EE4BEG3_4" + ], + [ + "CMT_FIFO_NE2A3_3", + "CMT_TOP_NE2A3_3" + ], + [ + "CMT_FIFO_SW2A3_4", + "CMT_TOP_SW2A3_4" + ], + [ + "CMT_FIFO_LH6_0", + "CMT_TOP_LH6_0" + ], + [ + "CMT_FIFO_EE2BEG3_0", + "CMT_TOP_EE2BEG3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_0", + "CMT_TOP_LOGIC_OUTS_L_B1_0" + ], + [ + "CMT_FIFO_SW2A2_7", + "CMT_TOP_SW2A2_7" + ], + [ + "CMT_FIFO_EE4B2_11", + "CMT_TOP_EE4B2_11" + ], + [ + "CMT_FIFO_WW4END2_6", + "CMT_TOP_WW4END2_6" + ], + [ + "CMT_FIFO_L_PHASER_RDENABLE", + "CMT_PLL_PHASER_RDENABLE_TOFIFO" + ], + [ + "CMT_FIFO_WW4B3_10", + "CMT_TOP_WW4B3_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_1", + "CMT_TOP_LOGIC_OUTS_L_B5_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_5", + "CMT_TOP_LOGIC_OUTS_L_B9_5" + ], + [ + "CMT_FIFO_SW2A2_1", + "CMT_TOP_SW2A2_1" + ], + [ + "CMT_FIFO_EE2A1_11", + "CMT_TOP_EE2A1_11" + ], + [ + "CMT_FIFO_L_IMUX3_6", + "CMT_TOP_IMUX3_6" + ], + [ + "CMT_FIFO_NE4BEG2_5", + "CMT_TOP_NE4BEG2_5" + ], + [ + "CMT_FIFO_L_FAN5_5", + "CMT_TOP_FAN5_5" + ], + [ + "CMT_FIFO_NE4BEG0_7", + "CMT_TOP_NE4BEG0_7" + ], + [ + "CMT_FIFO_L_IMUX14_3", + "CMT_TOP_IMUX14_3" + ], + [ + "CMT_FIFO_EE2BEG0_10", + "CMT_TOP_EE2BEG0_10" + ], + [ + "CMT_FIFO_L_BYP1_8", + "CMT_TOP_BYP1_8" + ], + [ + "CMT_FIFO_L_IMUX19_4", + "CMT_TOP_IMUX19_4" + ], + [ + "CMT_FIFO_LH4_2", + "CMT_TOP_LH4_2" + ], + [ + "CMT_FIFO_WW2A1_8", + "CMT_TOP_WW2A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6" + ], + [ + "CMT_FIFO_WL1END3_2", + "CMT_TOP_WL1END3_2" + ], + [ + "CMT_FIFO_L_IMUX29_1", + "CMT_TOP_IMUX29_1" + ], + [ + "CMT_FIFO_SW4A1_0", + "CMT_TOP_SW4A1_0" + ], + [ + "CMT_FIFO_EE2A3_8", + "CMT_TOP_EE2A3_8" + ], + [ + "CMT_FIFO_L_CLK1_0", + "CMT_TOP_CLK1_0" + ], + [ + "CMT_FIFO_L_IMUX26_7", + "CMT_TOP_IMUX26_7" + ], + [ + "CMT_FIFO_EE4C1_11", + "CMT_TOP_EE4C1_11" + ], + [ + "CMT_FIFO_NE2A0_7", + "CMT_TOP_NE2A0_7" + ], + [ + "CMT_FIFO_LH6_9", + "CMT_TOP_LH6_9" + ], + [ + "CMT_FIFO_NW2A3_4", + "CMT_TOP_NW2A3_4" + ], + [ + "CMT_FIFO_EE2A3_11", + "CMT_TOP_EE2A3_11" + ], + [ + "CMT_FIFO_L_IMUX3_8", + "CMT_TOP_IMUX3_8" + ], + [ + "CMT_FIFO_NE4C2_5", + "CMT_TOP_NE4C2_5" + ], + [ + "CMT_FIFO_L_BYP2_1", + "CMT_TOP_BYP2_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "CMT_TOP_OCLK_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_2", + "CMT_TOP_LOGIC_OUTS_L_B0_2" + ], + [ + "CMT_FIFO_L_IMUX28_9", + "CMT_TOP_IMUX28_9" + ], + [ + "CMT_FIFO_L_IMUX27_4", + "CMT_TOP_IMUX27_4" + ], + [ + "CMT_FIFO_SE4BEG3_1", + "CMT_TOP_SE4BEG3_1" + ], + [ + "CMT_FIFO_NE4C2_9", + "CMT_TOP_NE4C2_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "CMT_TOP_OCLK_1" + ], + [ + "CMT_FIFO_NE4BEG3_11", + "CMT_TOP_NE4BEG3_11" + ], + [ + "CMT_FIFO_ER1BEG1_9", + "CMT_TOP_ER1BEG1_9" + ], + [ + "CMT_FIFO_LH3_4", + "CMT_TOP_LH3_4" + ], + [ + "CMT_FIFO_LH5_7", + "CMT_TOP_LH5_7" + ], + [ + "CMT_FIFO_L_FAN2_7", + "CMT_TOP_FAN2_7" + ], + [ + "CMT_FIFO_WW2END2_3", + "CMT_TOP_WW2END2_3" + ], + [ + "CMT_FIFO_L_IMUX25_4", + "CMT_TOP_IMUX25_4" + ], + [ + "CMT_FIFO_L_IMUX40_1", + "CMT_TOP_IMUX40_1" + ], + [ + "CMT_FIFO_WL1END0_0", + "CMT_TOP_WL1END0_0" + ], + [ + "CMT_FIFO_L_BYP2_7", + "CMT_TOP_BYP2_7" + ], + [ + "CMT_FIFO_L_CTRL1_8", + "CMT_TOP_CTRL1_8" + ], + [ + "CMT_FIFO_EE4B3_3", + "CMT_TOP_EE4B3_3" + ], + [ + "CMT_FIFO_L_IMUX0_11", + "CMT_TOP_IMUX0_11" + ], + [ + "CMT_FIFO_WW2A1_5", + "CMT_TOP_WW2A1_5" + ], + [ + "CMT_FIFO_WL1END0_1", + "CMT_TOP_WL1END0_1" + ], + [ + "CMT_FIFO_L_BYP4_8", + "CMT_TOP_BYP4_8" + ], + [ + "CMT_FIFO_NW4A1_9", + "CMT_TOP_NW4A1_9" + ], + [ + "CMT_FIFO_NW4END1_9", + "CMT_TOP_NW4END1_9" + ], + [ + "CMT_FIFO_WR1END2_1", + "CMT_TOP_WR1END2_1" + ], + [ + "CMT_FIFO_EE4A3_3", + "CMT_TOP_EE4A3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_0", + "CMT_TOP_LOGIC_OUTS_L_B20_0" + ], + [ + "CMT_FIFO_SE2A2_6", + "CMT_TOP_SE2A2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_11", + "CMT_TOP_LOGIC_OUTS_L_B21_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_1", + "CMT_TOP_LOGIC_OUTS_L_B13_1" + ], + [ + "CMT_FIFO_L_IMUX6_5", + "CMT_TOP_IMUX6_5" + ], + [ + "CMT_FIFO_WR1END2_10", + "CMT_TOP_WR1END2_10" + ], + [ + "CMT_FIFO_LH9_1", + "CMT_TOP_LH9_1" + ], + [ + "CMT_FIFO_NW4A3_9", + "CMT_TOP_NW4A3_9" + ], + [ + "CMT_FIFO_SE2A3_6", + "CMT_TOP_SE2A3_6" + ], + [ + "CMT_FIFO_L_IMUX44_4", + "CMT_TOP_IMUX44_4" + ], + [ + "CMT_FIFO_L_IMUX35_6", + "CMT_TOP_IMUX35_6" + ], + [ + "CMT_FIFO_WR1END3_8", + "CMT_TOP_WR1END3_8" + ], + [ + "CMT_FIFO_NW2A0_11", + "CMT_TOP_NW2A0_11" + ], + [ + "CMT_FIFO_L_IMUX33_9", + "CMT_TOP_IMUX33_9" + ], + [ + "CMT_FIFO_EE2BEG1_9", + "CMT_TOP_EE2BEG1_9" + ], + [ + "CMT_FIFO_SE2A3_7", + "CMT_TOP_SE2A3_7" + ], + [ + "CMT_FIFO_EE4B3_4", + "CMT_TOP_EE4B3_4" + ], + [ + "CMT_FIFO_L_IMUX19_7", + "CMT_TOP_IMUX19_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "CMT_TOP_OCLK_0" + ], + [ + "CMT_FIFO_L_IMUX6_8", + "CMT_TOP_IMUX6_8" + ], + [ + "CMT_FIFO_L_CTRL0_4", + "CMT_TOP_CTRL0_4" + ], + [ + "CMT_FIFO_L_IMUX29_4", + "CMT_TOP_IMUX29_4" + ], + [ + "CMT_FIFO_WW4A1_10", + "CMT_TOP_WW4A1_10" + ], + [ + "CMT_FIFO_NE2A1_3", + "CMT_TOP_NE2A1_3" + ], + [ + "CMT_FIFO_L_IMUX46_0", + "CMT_TOP_IMUX46_0" + ], + [ + "CMT_FIFO_WW4B3_8", + "CMT_TOP_WW4B3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6" + ], + [ + "CMT_FIFO_L_IMUX35_8", + "CMT_TOP_IMUX35_8" + ], + [ + "CMT_FIFO_SW4END0_0", + "CMT_TOP_SW4END0_0" + ], + [ + "CMT_FIFO_EE4BEG2_0", + "CMT_TOP_EE4BEG2_0" + ], + [ + "CMT_FIFO_MONITOR_N_10", + "CMT_TOP_MONITOR_N_10" + ], + [ + "CMT_FIFO_L_FAN3_7", + "CMT_TOP_FAN3_7" + ], + [ + "CMT_FIFO_WW2END2_2", + "CMT_TOP_WW2END2_2" + ], + [ + "CMT_FIFO_EE4A1_8", + "CMT_TOP_EE4A1_8" + ], + [ + "CMT_FIFO_NW4END2_6", + "CMT_TOP_NW4END2_6" + ], + [ + "CMT_FIFO_EE2A0_11", + "CMT_TOP_EE2A0_11" + ], + [ + "CMT_FIFO_EE4B1_8", + "CMT_TOP_EE4B1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_1", + "CMT_TOP_LOGIC_OUTS_L_B22_1" + ], + [ + "CMT_FIFO_L_IMUX39_5", + "CMT_TOP_IMUX39_5" + ], + [ + "CMT_FIFO_LH2_5", + "CMT_TOP_LH2_5" + ], + [ + "CMT_FIFO_SW2A3_10", + "CMT_TOP_SW2A3_10" + ], + [ + "CMT_FIFO_WW4END0_8", + "CMT_TOP_WW4END0_8" + ], + [ + "CMT_FIFO_SE2A3_8", + "CMT_TOP_SE2A3_8" + ], + [ + "CMT_FIFO_L_IMUX29_7", + "CMT_TOP_IMUX29_7" + ], + [ + "CMT_FIFO_L_CTRL0_7", + "CMT_TOP_CTRL0_7" + ], + [ + "CMT_FIFO_L_BYP1_5", + "CMT_TOP_BYP1_5" + ], + [ + "CMT_FIFO_NE2A0_11", + "CMT_TOP_NE2A0_11" + ], + [ + "CMT_FIFO_L_IMUX20_8", + "CMT_TOP_IMUX20_8" + ], + [ + "CMT_FIFO_WR1END1_0", + "CMT_TOP_WR1END1_0" + ], + [ + "CMT_FIFO_EE4BEG1_4", + "CMT_TOP_EE4BEG1_4" + ], + [ + "CMT_FIFO_WW2END2_10", + "CMT_TOP_WW2END2_10" + ], + [ + "CMT_FIFO_L_CTRL0_6", + "CMT_TOP_CTRL0_6" + ], + [ + "CMT_FIFO_WW4C0_4", + "CMT_TOP_WW4C0_4" + ], + [ + "CMT_FIFO_NE2A2_8", + "CMT_TOP_NE2A2_8" + ], + [ + "CMT_FIFO_L_IMUX4_6", + "CMT_TOP_IMUX4_6" + ], + [ + "CMT_FIFO_SW4END0_3", + "CMT_TOP_SW4END0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_0", + "CMT_TOP_LOGIC_OUTS_L_B4_0" + ], + [ + "CMT_FIFO_SW4END0_11", + "CMT_TOP_SW4END0_11" + ], + [ + "CMT_FIFO_EE2A0_1", + "CMT_TOP_EE2A0_1" + ], + [ + "CMT_FIFO_EE4B1_2", + "CMT_TOP_EE4B1_2" + ], + [ + "CMT_FIFO_NE4C3_0", + "CMT_TOP_NE4C3_0" + ], + [ + "CMT_FIFO_L_IMUX40_5", + "CMT_TOP_IMUX40_5" + ], + [ + "CMT_FIFO_WW2END1_2", + "CMT_TOP_WW2END1_2" + ], + [ + "CMT_FIFO_WW2A0_0", + "CMT_TOP_WW2A0_0" + ], + [ + "CMT_FIFO_EE2BEG1_11", + "CMT_TOP_EE2BEG1_11" + ], + [ + "CMT_FIFO_EE4A1_2", + "CMT_TOP_EE4A1_2" + ], + [ + "CMT_FIFO_ER1BEG2_3", + "CMT_TOP_ER1BEG2_3" + ], + [ + "CMT_FIFO_L_IMUX33_2", + "CMT_TOP_IMUX33_2" + ], + [ + "CMT_FIFO_SW2A2_8", + "CMT_TOP_SW2A2_8" + ], + [ + "CMT_FIFO_L_IMUX13_0", + "CMT_TOP_IMUX13_0" + ], + [ + "CMT_FIFO_EE2BEG1_1", + "CMT_TOP_EE2BEG1_1" + ], + [ + "CMT_FIFO_WW4C3_0", + "CMT_TOP_WW4C3_0" + ], + [ + "CMT_FIFO_WL1END1_1", + "CMT_TOP_WL1END1_1" + ], + [ + "CMT_FIFO_L_IMUX18_3", + "CMT_TOP_IMUX18_3" + ], + [ + "CMT_FIFO_WL1END0_9", + "CMT_TOP_WL1END0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_11", + "CMT_TOP_LOGIC_OUTS_L_B4_11" + ], + [ + "CMT_FIFO_L_IMUX44_3", + "CMT_TOP_IMUX44_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_2", + "CMT_TOP_LOGIC_OUTS_L_B19_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5" + ], + [ + "CMT_FIFO_L_IMUX23_7", + "CMT_TOP_IMUX23_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_6", + "CMT_TOP_LOGIC_OUTS_L_B19_6" + ], + [ + "CMT_FIFO_L_IMUX2_0", + "CMT_TOP_IMUX2_0" + ], + [ + "CMT_FIFO_L_IMUX35_9", + "CMT_TOP_IMUX35_9" + ], + [ + "CMT_FIFO_WR1END1_7", + "CMT_TOP_WR1END1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_9", + "CMT_TOP_LOGIC_OUTS_L_B17_9" + ], + [ + "CMT_FIFO_L_IMUX39_8", + "CMT_TOP_IMUX39_8" + ], + [ + "CMT_FIFO_WR1END3_4", + "CMT_TOP_WR1END3_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "CMT_TOP_ICLKDIV_9" + ], + [ + "CMT_FIFO_NE4BEG3_1", + "CMT_TOP_NE4BEG3_1" + ], + [ + "CMT_FIFO_WL1END2_6", + "CMT_TOP_WL1END2_6" + ], + [ + "CMT_FIFO_SE2A3_11", + "CMT_TOP_SE2A3_11" + ], + [ + "CMT_FIFO_NW4A3_7", + "CMT_TOP_NW4A3_7" + ], + [ + "CMT_FIFO_L_BYP0_7", + "CMT_TOP_BYP0_7" + ], + [ + "CMT_FIFO_SW2A0_3", + "CMT_TOP_SW2A0_3" + ], + [ + "CMT_FIFO_EE2BEG2_8", + "CMT_TOP_EE2BEG2_8" + ], + [ + "CMT_FIFO_EE2A1_6", + "CMT_TOP_EE2A1_6" + ], + [ + "CMT_FIFO_EE4C1_7", + "CMT_TOP_EE4C1_7" + ], + [ + "CMT_FIFO_WW4A0_10", + "CMT_TOP_WW4A0_10" + ], + [ + "CMT_FIFO_WR1END2_9", + "CMT_TOP_WR1END2_9" + ], + [ + "CMT_FIFO_WW4C3_6", + "CMT_TOP_WW4C3_6" + ], + [ + "CMT_FIFO_WW4END2_7", + "CMT_TOP_WW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX6_11", + "CMT_TOP_IMUX6_11" + ], + [ + "CMT_FIFO_L_IMUX10_6", + "CMT_TOP_IMUX10_6" + ], + [ + "CMT_FIFO_LH9_7", + "CMT_TOP_LH9_7" + ], + [ + "CMT_FIFO_L_CTRL1_0", + "CMT_TOP_CTRL1_0" + ], + [ + "CMT_FIFO_L_IMUX1_3", + "CMT_TOP_IMUX1_3" + ], + [ + "CMT_FIFO_WW2END3_10", + "CMT_TOP_WW2END3_10" + ], + [ + "CMT_FIFO_WW2A2_1", + "CMT_TOP_WW2A2_1" + ], + [ + "CMT_FIFO_L_CLK1_6", + "CMT_TOP_CLK1_6" + ], + [ + "CMT_FIFO_LH8_9", + "CMT_TOP_LH8_9" + ], + [ + "CMT_FIFO_L_IMUX46_5", + "CMT_TOP_IMUX46_5" + ], + [ + "CMT_FIFO_WW4A1_4", + "CMT_TOP_WW4A1_4" + ], + [ + "CMT_FIFO_L_IMUX25_11", + "CMT_TOP_IMUX25_11" + ], + [ + "CMT_FIFO_L_IMUX2_9", + "CMT_TOP_IMUX2_9" + ], + [ + "CMT_FIFO_SE4C3_0", + "CMT_TOP_SE4C3_0" + ], + [ + "CMT_FIFO_WW4C2_4", + "CMT_TOP_WW4C2_4" + ], + [ + "CMT_FIFO_WW4C1_6", + "CMT_TOP_WW4C1_6" + ], + [ + "CMT_FIFO_L_IMUX38_1", + "CMT_TOP_IMUX38_1" + ], + [ + "CMT_FIFO_MONITOR_P_0", + "CMT_TOP_MONITOR_P_0" + ], + [ + "CMT_FIFO_WL1END1_4", + "CMT_TOP_WL1END1_4" + ], + [ + "CMT_FIFO_EE4A2_0", + "CMT_TOP_EE4A2_0" + ], + [ + "CMT_FIFO_EL1BEG3_10", + "CMT_TOP_EL1BEG3_10" + ], + [ + "CMT_FIFO_L_IMUX27_0", + "CMT_TOP_IMUX27_0" + ], + [ + "CMT_FIFO_NE4C0_7", + "CMT_TOP_NE4C0_7" + ], + [ + "CMT_FIFO_ER1BEG1_2", + "CMT_TOP_ER1BEG1_2" + ], + [ + "CMT_FIFO_NE2A1_10", + "CMT_TOP_NE2A1_10" + ], + [ + "CMT_FIFO_SE4BEG3_6", + "CMT_TOP_SE4BEG3_6" + ], + [ + "CMT_FIFO_WL1END3_11", + "CMT_TOP_WL1END3_11" + ], + [ + "CMT_FIFO_SW4A1_6", + "CMT_TOP_SW4A1_6" + ], + [ + "CMT_FIFO_EE4A3_9", + "CMT_TOP_EE4A3_9" + ], + [ + "CMT_FIFO_EL1BEG0_2", + "CMT_TOP_EL1BEG0_2" + ], + [ + "CMT_FIFO_WW4C3_3", + "CMT_TOP_WW4C3_3" + ], + [ + "CMT_FIFO_SW4END0_6", + "CMT_TOP_SW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX41_4", + "CMT_TOP_IMUX41_4" + ], + [ + "CMT_FIFO_L_FAN3_3", + "CMT_TOP_FAN3_3" + ], + [ + "CMT_FIFO_WW4C2_1", + "CMT_TOP_WW4C2_1" + ], + [ + "CMT_FIFO_L_BYP3_2", + "CMT_TOP_BYP3_2" + ], + [ + "CMT_FIFO_L_IMUX8_3", + "CMT_TOP_IMUX8_3" + ], + [ + "CMT_FIFO_LH6_11", + "CMT_TOP_LH6_11" + ], + [ + "CMT_FIFO_EE2A2_9", + "CMT_TOP_EE2A2_9" + ], + [ + "CMT_FIFO_WW2A0_7", + "CMT_TOP_WW2A0_7" + ], + [ + "CMT_FIFO_WW4END2_5", + "CMT_TOP_WW4END2_5" + ], + [ + "CMT_FIFO_WW2END0_7", + "CMT_TOP_WW2END0_7" + ], + [ + "CMT_FIFO_EE4B0_1", + "CMT_TOP_EE4B0_1" + ], + [ + "CMT_FIFO_L_IMUX38_10", + "CMT_TOP_IMUX38_10" + ], + [ + "CMT_FIFO_NE2A2_10", + "CMT_TOP_NE2A2_10" + ], + [ + "CMT_FIFO_EE2A3_2", + "CMT_TOP_EE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX4_3", + "CMT_TOP_IMUX4_3" + ], + [ + "CMT_FIFO_L_FAN2_6", + "CMT_TOP_FAN2_6" + ], + [ + "CMT_FIFO_WW4END0_2", + "CMT_TOP_WW4END0_2" + ], + [ + "CMT_FIFO_NE4BEG0_3", + "CMT_TOP_NE4BEG0_3" + ], + [ + "CMT_FIFO_SW4END3_8", + "CMT_TOP_SW4END3_8" + ], + [ + "CMT_FIFO_LH6_7", + "CMT_TOP_LH6_7" + ], + [ + "CMT_FIFO_WW2END0_6", + "CMT_TOP_WW2END0_6" + ], + [ + "CMT_FIFO_NW4A2_1", + "CMT_TOP_NW4A2_1" + ], + [ + "CMT_FIFO_WW2A3_4", + "CMT_TOP_WW2A3_4" + ], + [ + "CMT_FIFO_SW4A0_8", + "CMT_TOP_SW4A0_8" + ], + [ + "CMT_FIFO_L_IMUX19_6", + "CMT_TOP_IMUX19_6" + ], + [ + "CMT_FIFO_EL1BEG3_0", + "CMT_TOP_EL1BEG3_0" + ], + [ + "CMT_FIFO_LH3_1", + "CMT_TOP_LH3_1" + ], + [ + "CMT_FIFO_L_IMUX10_1", + "CMT_TOP_IMUX10_1" + ], + [ + "CMT_FIFO_WW4END1_10", + "CMT_TOP_WW4END1_10" + ], + [ + "CMT_FIFO_L_IMUX43_6", + "CMT_TOP_IMUX43_6" + ], + [ + "CMT_FIFO_L_FAN2_4", + "CMT_TOP_FAN2_4" + ], + [ + "CMT_FIFO_WR1END2_11", + "CMT_TOP_WR1END2_11" + ], + [ + "CMT_FIFO_NW4END0_11", + "CMT_TOP_NW4END0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_2", + "CMT_TOP_LOGIC_OUTS_L_B2_2" + ], + [ + "CMT_FIFO_SE4BEG2_11", + "CMT_TOP_SE4BEG2_11" + ], + [ + "CMT_FIFO_EE2A3_3", + "CMT_TOP_EE2A3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_5", + "CMT_TOP_LOGIC_OUTS_L_B22_5" + ], + [ + "CMT_FIFO_SW4A0_0", + "CMT_TOP_SW4A0_0" + ], + [ + "CMT_FIFO_NE4BEG3_7", + "CMT_TOP_NE4BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX9_1", + "CMT_TOP_IMUX9_1" + ], + [ + "CMT_FIFO_NW4A3_2", + "CMT_TOP_NW4A3_2" + ], + [ + "CMT_FIFO_NW4A0_1", + "CMT_TOP_NW4A0_1" + ], + [ + "CMT_FIFO_WW4END0_1", + "CMT_TOP_WW4END0_1" + ], + [ + "CMT_FIFO_L_IMUX37_9", + "CMT_TOP_IMUX37_9" + ], + [ + "CMT_FIFO_L_IMUX7_7", + "CMT_TOP_IMUX7_7" + ], + [ + "CMT_FIFO_NE2A2_6", + "CMT_TOP_NE2A2_6" + ], + [ + "CMT_FIFO_EE2A1_10", + "CMT_TOP_EE2A1_10" + ], + [ + "CMT_FIFO_NE4BEG2_3", + "CMT_TOP_NE4BEG2_3" + ], + [ + "CMT_FIFO_WW2END2_6", + "CMT_TOP_WW2END2_6" + ], + [ + "CMT_FIFO_SW4A2_9", + "CMT_TOP_SW4A2_9" + ], + [ + "CMT_FIFO_L_IMUX1_6", + "CMT_TOP_IMUX1_6" + ], + [ + "CMT_FIFO_L_IMUX18_7", + "CMT_TOP_IMUX18_7" + ], + [ + "CMT_FIFO_WR1END2_2", + "CMT_TOP_WR1END2_2" + ], + [ + "CMT_FIFO_L_IMUX41_3", + "CMT_TOP_IMUX41_3" + ], + [ + "CMT_FIFO_L_IMUX17_9", + "CMT_TOP_IMUX17_9" + ], + [ + "CMT_FIFO_EE4BEG3_5", + "CMT_TOP_EE4BEG3_5" + ], + [ + "CMT_FIFO_NW2A0_1", + "CMT_TOP_NW2A0_1" + ], + [ + "CMT_FIFO_EE4A1_11", + "CMT_TOP_EE4A1_11" + ], + [ + "CMT_FIFO_SE2A0_11", + "CMT_TOP_SE2A0_11" + ], + [ + "CMT_FIFO_L_IMUX10_11", + "CMT_TOP_IMUX10_11" + ], + [ + "CMT_FIFO_L_IMUX47_5", + "CMT_TOP_IMUX47_5" + ], + [ + "CMT_FIFO_L_IMUX42_2", + "CMT_TOP_IMUX42_2" + ], + [ + "CMT_FIFO_L_IMUX36_11", + "CMT_TOP_IMUX36_11" + ], + [ + "CMT_FIFO_L_IMUX5_0", + "CMT_TOP_IMUX5_0" + ], + [ + "CMT_FIFO_LH1_0", + "CMT_TOP_LH1_0" + ], + [ + "CMT_FIFO_L_IMUX17_10", + "CMT_TOP_IMUX17_10" + ], + [ + "CMT_FIFO_WW4C1_2", + "CMT_TOP_WW4C1_2" + ], + [ + "CMT_FIFO_WR1END1_4", + "CMT_TOP_WR1END1_4" + ], + [ + "CMT_FIFO_WW4C3_1", + "CMT_TOP_WW4C3_1" + ], + [ + "CMT_FIFO_EE4C1_5", + "CMT_TOP_EE4C1_5" + ], + [ + "CMT_FIFO_LH5_6", + "CMT_TOP_LH5_6" + ], + [ + "CMT_FIFO_EL1BEG2_5", + "CMT_TOP_EL1BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX3_4", + "CMT_TOP_IMUX3_4" + ], + [ + "CMT_FIFO_L_IMUX21_8", + "CMT_TOP_IMUX21_8" + ], + [ + "CMT_FIFO_L_FAN2_2", + "CMT_TOP_FAN2_2" + ], + [ + "CMT_FIFO_L_IMUX44_6", + "CMT_TOP_IMUX44_6" + ], + [ + "CMT_FIFO_L_BYP3_10", + "CMT_TOP_BYP3_10" + ], + [ + "CMT_FIFO_LH11_6", + "CMT_TOP_LH11_6" + ], + [ + "CMT_FIFO_NE4BEG0_9", + "CMT_TOP_NE4BEG0_9" + ], + [ + "CMT_FIFO_L_IMUX7_6", + "CMT_TOP_IMUX7_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_9", + "CMT_TOP_LOGIC_OUTS_L_B12_9" + ], + [ + "CMT_FIFO_EE2A2_5", + "CMT_TOP_EE2A2_5" + ], + [ + "CMT_FIFO_LH11_1", + "CMT_TOP_LH11_1" + ], + [ + "CMT_FIFO_NW2A2_2", + "CMT_TOP_NW2A2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_0" + ], + [ + "CMT_FIFO_SW4A1_2", + "CMT_TOP_SW4A1_2" + ], + [ + "CMT_FIFO_EE4C0_0", + "CMT_TOP_EE4C0_0" + ], + [ + "CMT_FIFO_L_IMUX35_0", + "CMT_TOP_IMUX35_0" + ], + [ + "CMT_FIFO_EE2A3_9", + "CMT_TOP_EE2A3_9" + ], + [ + "CMT_FIFO_L_FAN3_10", + "CMT_TOP_FAN3_10" + ], + [ + "CMT_FIFO_L_BYP4_7", + "CMT_TOP_BYP4_7" + ], + [ + "CMT_FIFO_L_IMUX28_3", + "CMT_TOP_IMUX28_3" + ], + [ + "CMT_FIFO_EE2A0_0", + "CMT_TOP_EE2A0_0" + ], + [ + "CMT_FIFO_L_IMUX21_10", + "CMT_TOP_IMUX21_10" + ], + [ + "CMT_FIFO_SW4END2_5", + "CMT_TOP_SW4END2_5" + ], + [ + "CMT_FIFO_MONITOR_P_2", + "CMT_TOP_MONITOR_P_2" + ], + [ + "CMT_FIFO_SW2A0_8", + "CMT_TOP_SW2A0_8" + ], + [ + "CMT_FIFO_L_IMUX45_7", + "CMT_TOP_IMUX45_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_9", + "CMT_TOP_LOGIC_OUTS_L_B4_9" + ], + [ + "CMT_FIFO_SE4BEG1_3", + "CMT_TOP_SE4BEG1_3" + ], + [ + "CMT_FIFO_WR1END2_0", + "CMT_TOP_WR1END2_0" + ], + [ + "CMT_FIFO_L_CLK1_11", + "CMT_TOP_CLK1_11" + ], + [ + "CMT_FIFO_EE4A3_10", + "CMT_TOP_EE4A3_10" + ], + [ + "CMT_FIFO_SE4BEG2_8", + "CMT_TOP_SE4BEG2_8" + ], + [ + "CMT_FIFO_L_PHASER_WRCLK", + "CMT_PLL_PHASER_WRCLK_TOFIFO" + ], + [ + "CMT_FIFO_L_IMUX24_3", + "CMT_TOP_IMUX24_3" + ], + [ + "CMT_FIFO_EE2BEG1_4", + "CMT_TOP_EE2BEG1_4" + ], + [ + "CMT_FIFO_WW4B2_0", + "CMT_TOP_WW4B2_0" + ], + [ + "CMT_FIFO_NE4C0_3", + "CMT_TOP_NE4C0_3" + ], + [ + "CMT_FIFO_L_BYP7_7", + "CMT_TOP_BYP7_7" + ], + [ + "CMT_FIFO_L_FAN7_1", + "CMT_TOP_FAN7_1" + ], + [ + "CMT_FIFO_SW4A3_8", + "CMT_TOP_SW4A3_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "CMT_TOP_ICLK_8" + ], + [ + "CMT_FIFO_EE2A2_4", + "CMT_TOP_EE2A2_4" + ], + [ + "CMT_FIFO_LH6_10", + "CMT_TOP_LH6_10" + ], + [ + "CMT_FIFO_NE2A1_11", + "CMT_TOP_NE2A1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_4" + ], + [ + "CMT_FIFO_L_IMUX20_6", + "CMT_TOP_IMUX20_6" + ], + [ + "CMT_FIFO_L_IMUX14_9", + "CMT_TOP_IMUX14_9" + ], + [ + "CMT_FIFO_NW2A1_9", + "CMT_TOP_NW2A1_9" + ], + [ + "CMT_FIFO_SW4END3_6", + "CMT_TOP_SW4END3_6" + ], + [ + "CMT_FIFO_L_BYP6_4", + "CMT_TOP_BYP6_4" + ], + [ + "CMT_FIFO_L_IMUX37_3", + "CMT_TOP_IMUX37_3" + ], + [ + "CMT_FIFO_L_IMUX32_11", + "CMT_TOP_IMUX32_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_2", + "CMT_TOP_LOGIC_OUTS_L_B20_2" + ], + [ + "CMT_FIFO_EL1BEG0_3", + "CMT_TOP_EL1BEG0_3" + ], + [ + "CMT_FIFO_L_IMUX40_11", + "CMT_TOP_IMUX40_11" + ], + [ + "CMT_FIFO_WW4END1_11", + "CMT_TOP_WW4END1_11" + ], + [ + "CMT_FIFO_L_IMUX17_1", + "CMT_TOP_IMUX17_1" + ], + [ + "CMT_FIFO_L_IMUX29_3", + "CMT_TOP_IMUX29_3" + ], + [ + "CMT_FIFO_NW4A1_0", + "CMT_TOP_NW4A1_0" + ], + [ + "CMT_FIFO_SW4A2_6", + "CMT_TOP_SW4A2_6" + ], + [ + "CMT_FIFO_EE4B0_8", + "CMT_TOP_EE4B0_8" + ], + [ + "CMT_FIFO_EE2BEG3_4", + "CMT_TOP_EE2BEG3_4" + ], + [ + "CMT_FIFO_ER1BEG1_10", + "CMT_TOP_ER1BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX43_9", + "CMT_TOP_IMUX43_9" + ], + [ + "CMT_FIFO_LH8_7", + "CMT_TOP_LH8_7" + ], + [ + "CMT_FIFO_EE4B2_1", + "CMT_TOP_EE4B2_1" + ], + [ + "CMT_FIFO_NW4END2_3", + "CMT_TOP_NW4END2_3" + ], + [ + "CMT_FIFO_WW4A3_5", + "CMT_TOP_WW4A3_5" + ], + [ + "CMT_FIFO_L_BYP6_6", + "CMT_TOP_BYP6_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "CMT_TOP_ICLKDIV_5" + ], + [ + "CMT_FIFO_L_IMUX3_7", + "CMT_TOP_IMUX3_7" + ], + [ + "CMT_FIFO_WW2A1_4", + "CMT_TOP_WW2A1_4" + ], + [ + "CMT_FIFO_EE4B1_6", + "CMT_TOP_EE4B1_6" + ], + [ + "CMT_FIFO_LH10_4", + "CMT_TOP_LH10_4" + ], + [ + "CMT_FIFO_L_IMUX45_3", + "CMT_TOP_IMUX45_3" + ], + [ + "CMT_FIFO_LH4_0", + "CMT_TOP_LH4_0" + ], + [ + "CMT_FIFO_EE2A1_8", + "CMT_TOP_EE2A1_8" + ], + [ + "CMT_FIFO_EE4C1_8", + "CMT_TOP_EE4C1_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "CMT_TOP_ICLKDIV_1" + ], + [ + "CMT_FIFO_L_IMUX8_11", + "CMT_TOP_IMUX8_11" + ], + [ + "CMT_FIFO_L_IMUX36_3", + "CMT_TOP_IMUX36_3" + ], + [ + "CMT_FIFO_SW4A2_0", + "CMT_TOP_SW4A2_0" + ], + [ + "CMT_FIFO_EE2A3_1", + "CMT_TOP_EE2A3_1" + ], + [ + "CMT_FIFO_WL1END2_8", + "CMT_TOP_WL1END2_8" + ], + [ + "CMT_FIFO_SW4A2_4", + "CMT_TOP_SW4A2_4" + ], + [ + "CMT_FIFO_EE4BEG0_10", + "CMT_TOP_EE4BEG0_10" + ], + [ + "CMT_FIFO_EE4C0_3", + "CMT_TOP_EE4C0_3" + ], + [ + "CMT_FIFO_NE4BEG2_8", + "CMT_TOP_NE4BEG2_8" + ], + [ + "CMT_FIFO_EE2A2_8", + "CMT_TOP_EE2A2_8" + ], + [ + "CMT_FIFO_SW2A3_7", + "CMT_TOP_SW2A3_7" + ], + [ + "CMT_FIFO_WW2A2_9", + "CMT_TOP_WW2A2_9" + ], + [ + "CMT_FIFO_SW4A3_3", + "CMT_TOP_SW4A3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_4", + "CMT_TOP_LOGIC_OUTS_L_B20_4" + ], + [ + "CMT_FIFO_NE4C3_3", + "CMT_TOP_NE4C3_3" + ], + [ + "CMT_FIFO_WL1END0_10", + "CMT_TOP_WL1END0_10" + ], + [ + "CMT_FIFO_L_IMUX8_5", + "CMT_TOP_IMUX8_5" + ], + [ + "CMT_FIFO_WW4B1_9", + "CMT_TOP_WW4B1_9" + ], + [ + "CMT_FIFO_NW2A0_9", + "CMT_TOP_NW2A0_9" + ], + [ + "CMT_FIFO_EE2A1_2", + "CMT_TOP_EE2A1_2" + ], + [ + "CMT_FIFO_WW4C0_0", + "CMT_TOP_WW4C0_0" + ], + [ + "CMT_FIFO_WW4B0_4", + "CMT_TOP_WW4B0_4" + ], + [ + "CMT_FIFO_NW2A3_3", + "CMT_TOP_NW2A3_3" + ], + [ + "CMT_FIFO_ER1BEG2_8", + "CMT_TOP_ER1BEG2_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "CMT_TOP_OCLKDIV_4" + ], + [ + "CMT_FIFO_WW4C2_10", + "CMT_TOP_WW4C2_10" + ], + [ + "CMT_FIFO_L_CTRL0_1", + "CMT_TOP_CTRL0_1" + ], + [ + "CMT_FIFO_SW2A0_1", + "CMT_TOP_SW2A0_1" + ], + [ + "CMT_FIFO_EE2BEG0_1", + "CMT_TOP_EE2BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_7", + "CMT_TOP_LOGIC_OUTS_L_B14_7" + ], + [ + "CMT_FIFO_EE2BEG1_6", + "CMT_TOP_EE2BEG1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_7", + "CMT_TOP_LOGIC_OUTS_L_B11_7" + ], + [ + "CMT_FIFO_L_IMUX12_4", + "CMT_TOP_IMUX12_4" + ], + [ + "CMT_FIFO_EE4B2_0", + "CMT_TOP_EE4B2_0" + ], + [ + "CMT_FIFO_SE4C3_11", + "CMT_TOP_SE4C3_11" + ], + [ + "CMT_FIFO_LH10_7", + "CMT_TOP_LH10_7" + ], + [ + "CMT_FIFO_EE2BEG2_2", + "CMT_TOP_EE2BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX23_1", + "CMT_TOP_IMUX23_1" + ], + [ + "CMT_FIFO_WW4A1_5", + "CMT_TOP_WW4A1_5" + ], + [ + "CMT_FIFO_WR1END0_0", + "CMT_TOP_WR1END0_0" + ], + [ + "CMT_FIFO_ER1BEG1_7", + "CMT_TOP_ER1BEG1_7" + ], + [ + "CMT_FIFO_EE4B2_10", + "CMT_TOP_EE4B2_10" + ], + [ + "CMT_FIFO_WW4A1_6", + "CMT_TOP_WW4A1_6" + ], + [ + "CMT_FIFO_L_IMUX42_9", + "CMT_TOP_IMUX42_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "CMT_TOP_ICLK_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_1", + "CMT_TOP_LOGIC_OUTS_L_B8_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "CMT_TOP_ICLK_9" + ], + [ + "CMT_FIFO_NE4BEG3_4", + "CMT_TOP_NE4BEG3_4" + ], + [ + "CMT_FIFO_EE2BEG3_9", + "CMT_TOP_EE2BEG3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_6", + "CMT_TOP_LOGIC_OUTS_L_B12_6" + ], + [ + "CMT_FIFO_NE2A0_6", + "CMT_TOP_NE2A0_6" + ], + [ + "CMT_FIFO_EE4BEG2_7", + "CMT_TOP_EE4BEG2_7" + ], + [ + "CMT_FIFO_NE4BEG1_1", + "CMT_TOP_NE4BEG1_1" + ], + [ + "CMT_FIFO_EE4C2_5", + "CMT_TOP_EE4C2_5" + ], + [ + "CMT_FIFO_WW4C1_3", + "CMT_TOP_WW4C1_3" + ], + [ + "CMT_FIFO_LH10_8", + "CMT_TOP_LH10_8" + ], + [ + "CMT_FIFO_L_IMUX15_0", + "CMT_TOP_IMUX15_0" + ], + [ + "CMT_FIFO_L_FAN7_3", + "CMT_TOP_FAN7_3" + ], + [ + "CMT_FIFO_L_CLK0_9", + "CMT_TOP_CLK0_9" + ], + [ + "CMT_FIFO_NE4BEG0_5", + "CMT_TOP_NE4BEG0_5" + ], + [ + "CMT_FIFO_WR1END0_5", + "CMT_TOP_WR1END0_5" + ], + [ + "CMT_FIFO_SE4BEG3_7", + "CMT_TOP_SE4BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX38_9", + "CMT_TOP_IMUX38_9" + ], + [ + "CMT_FIFO_EE4C1_3", + "CMT_TOP_EE4C1_3" + ], + [ + "CMT_FIFO_SE4C2_8", + "CMT_TOP_SE4C2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_2", + "CMT_TOP_LOGIC_OUTS_L_B12_2" + ], + [ + "CMT_FIFO_L_IMUX43_0", + "CMT_TOP_IMUX43_0" + ], + [ + "CMT_FIFO_L_IMUX15_1", + "CMT_TOP_IMUX15_1" + ], + [ + "CMT_FIFO_ER1BEG3_5", + "CMT_TOP_ER1BEG3_5" + ], + [ + "CMT_FIFO_L_BYP6_7", + "CMT_TOP_BYP6_7" + ], + [ + "CMT_FIFO_L_BYP3_3", + "CMT_TOP_BYP3_3" + ], + [ + "CMT_FIFO_NE2A3_11", + "CMT_TOP_NE2A3_11" + ], + [ + "CMT_FIFO_WL1END1_0", + "CMT_TOP_WL1END1_0" + ], + [ + "CMT_FIFO_L_IMUX21_0", + "CMT_TOP_IMUX21_0" + ], + [ + "CMT_FIFO_WL1END1_6", + "CMT_TOP_WL1END1_6" + ], + [ + "CMT_FIFO_L_IMUX26_2", + "CMT_TOP_IMUX26_2" + ], + [ + "CMT_FIFO_WL1END2_4", + "CMT_TOP_WL1END2_4" + ], + [ + "CMT_FIFO_WW4B0_5", + "CMT_TOP_WW4B0_5" + ], + [ + "CMT_FIFO_EE2A3_10", + "CMT_TOP_EE2A3_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_9", + "CMT_TOP_LOGIC_OUTS_L_B8_9" + ], + [ + "CMT_FIFO_WR1END0_7", + "CMT_TOP_WR1END0_7" + ], + [ + "CMT_FIFO_WW4END0_7", + "CMT_TOP_WW4END0_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_11", + "CMT_TOP_LOGIC_OUTS_L_B5_11" + ], + [ + "CMT_FIFO_L_IMUX24_4", + "CMT_TOP_IMUX24_4" + ], + [ + "CMT_FIFO_SE4BEG2_0", + "CMT_TOP_SE4BEG2_0" + ], + [ + "CMT_FIFO_SW2A2_5", + "CMT_TOP_SW2A2_5" + ], + [ + "CMT_FIFO_L_CTRL1_10", + "CMT_TOP_CTRL1_10" + ], + [ + "CMT_FIFO_L_IMUX7_4", + "CMT_TOP_IMUX7_4" + ], + [ + "CMT_FIFO_WW4C1_0", + "CMT_TOP_WW4C1_0" + ], + [ + "CMT_FIFO_L_IMUX47_7", + "CMT_TOP_IMUX47_7" + ], + [ + "CMT_FIFO_EE4A3_2", + "CMT_TOP_EE4A3_2" + ], + [ + "CMT_FIFO_WW4B3_4", + "CMT_TOP_WW4B3_4" + ], + [ + "CMT_FIFO_L_IMUX0_9", + "CMT_TOP_IMUX0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_9", + "CMT_TOP_LOGIC_OUTS_L_B0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_7", + "CMT_TOP_LOGIC_OUTS_L_B18_7" + ], + [ + "CMT_FIFO_WW4A3_2", + "CMT_TOP_WW4A3_2" + ], + [ + "CMT_FIFO_WW4A3_8", + "CMT_TOP_WW4A3_8" + ], + [ + "CMT_FIFO_L_BYP2_11", + "CMT_TOP_BYP2_11" + ], + [ + "CMT_FIFO_L_IMUX5_1", + "CMT_TOP_IMUX5_1" + ], + [ + "CMT_FIFO_L_IMUX5_8", + "CMT_TOP_IMUX5_8" + ], + [ + "CMT_FIFO_EL1BEG3_11", + "CMT_TOP_EL1BEG3_11" + ], + [ + "CMT_FIFO_NW4A1_8", + "CMT_TOP_NW4A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_4", + "CMT_TOP_LOGIC_OUTS_L_B21_4" + ], + [ + "CMT_FIFO_NE4C0_1", + "CMT_TOP_NE4C0_1" + ], + [ + "CMT_FIFO_WW4B0_3", + "CMT_TOP_WW4B0_3" + ], + [ + "CMT_FIFO_SW4A3_0", + "CMT_TOP_SW4A3_0" + ], + [ + "CMT_FIFO_LH10_9", + "CMT_TOP_LH10_9" + ], + [ + "CMT_FIFO_L_IMUX13_3", + "CMT_TOP_IMUX13_3" + ], + [ + "CMT_FIFO_NE4BEG2_7", + "CMT_TOP_NE4BEG2_7" + ], + [ + "CMT_FIFO_L_BYP0_6", + "CMT_TOP_BYP0_6" + ], + [ + "CMT_FIFO_EL1BEG0_11", + "CMT_TOP_EL1BEG0_11" + ], + [ + "CMT_FIFO_LH6_8", + "CMT_TOP_LH6_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "CMT_TOP_ICLK_3" + ], + [ + "CMT_FIFO_L_IMUX28_4", + "CMT_TOP_IMUX28_4" + ], + [ + "CMT_FIFO_WL1END3_9", + "CMT_TOP_WL1END3_9" + ], + [ + "CMT_FIFO_SE2A1_3", + "CMT_TOP_SE2A1_3" + ], + [ + "CMT_FIFO_L_IMUX47_10", + "CMT_TOP_IMUX47_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_7", + "CMT_TOP_LOGIC_OUTS_L_B3_7" + ], + [ + "CMT_FIFO_SW2A2_2", + "CMT_TOP_SW2A2_2" + ], + [ + "CMT_FIFO_SW2A3_3", + "CMT_TOP_SW2A3_3" + ], + [ + "CMT_FIFO_EE4A2_10", + "CMT_TOP_EE4A2_10" + ], + [ + "CMT_FIFO_WL1END1_5", + "CMT_TOP_WL1END1_5" + ], + [ + "CMT_FIFO_L_FAN4_1", + "CMT_TOP_FAN4_1" + ], + [ + "CMT_FIFO_L_IMUX21_2", + "CMT_TOP_IMUX21_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_4", + "CMT_TOP_LOGIC_OUTS_L_B12_4" + ], + [ + "CMT_FIFO_LH6_5", + "CMT_TOP_LH6_5" + ], + [ + "CMT_FIFO_L_IMUX43_2", + "CMT_TOP_IMUX43_2" + ], + [ + "CMT_FIFO_WL1END0_8", + "CMT_TOP_WL1END0_8" + ], + [ + "CMT_FIFO_SE2A2_2", + "CMT_TOP_SE2A2_2" + ], + [ + "CMT_FIFO_EL1BEG1_5", + "CMT_TOP_EL1BEG1_5" + ], + [ + "CMT_FIFO_EE4A2_11", + "CMT_TOP_EE4A2_11" + ], + [ + "CMT_FIFO_EE4BEG3_2", + "CMT_TOP_EE4BEG3_2" + ], + [ + "CMT_FIFO_WW4A2_7", + "CMT_TOP_WW4A2_7" + ], + [ + "CMT_FIFO_L_IMUX32_2", + "CMT_TOP_IMUX32_2" + ], + [ + "CMT_FIFO_LH4_8", + "CMT_TOP_LH4_8" + ], + [ + "CMT_FIFO_LH12_5", + "CMT_TOP_LH12_5" + ], + [ + "CMT_FIFO_L_IMUX18_9", + "CMT_TOP_IMUX18_9" + ], + [ + "CMT_FIFO_L_IMUX1_9", + "CMT_TOP_IMUX1_9" + ], + [ + "CMT_FIFO_WW4B0_6", + "CMT_TOP_WW4B0_6" + ], + [ + "CMT_FIFO_L_FAN5_8", + "CMT_TOP_FAN5_8" + ], + [ + "CMT_FIFO_SW4END1_2", + "CMT_TOP_SW4END1_2" + ], + [ + "CMT_FIFO_L_IMUX35_11", + "CMT_TOP_IMUX35_11" + ], + [ + "CMT_FIFO_NW4END1_10", + "CMT_TOP_NW4END1_10" + ], + [ + "CMT_FIFO_WR1END3_11", + "CMT_TOP_WR1END3_11" + ], + [ + "CMT_FIFO_L_IMUX14_2", + "CMT_TOP_IMUX14_2" + ], + [ + "CMT_FIFO_L_IMUX4_7", + "CMT_TOP_IMUX4_7" + ], + [ + "CMT_FIFO_WW4END3_0", + "CMT_TOP_WW4END3_0" + ], + [ + "CMT_FIFO_L_IMUX13_9", + "CMT_TOP_IMUX13_9" + ], + [ + "CMT_FIFO_L_IMUX17_5", + "CMT_TOP_IMUX17_5" + ], + [ + "CMT_FIFO_SE2A0_10", + "CMT_TOP_SE2A0_10" + ], + [ + "CMT_FIFO_L_IMUX26_3", + "CMT_TOP_IMUX26_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "CMT_TOP_ICLKDIV_3" + ], + [ + "CMT_FIFO_NE4C1_9", + "CMT_TOP_NE4C1_9" + ], + [ + "CMT_FIFO_L_BYP4_5", + "CMT_TOP_BYP4_5" + ], + [ + "CMT_FIFO_SW4A0_5", + "CMT_TOP_SW4A0_5" + ], + [ + "CMT_FIFO_L_BYP4_3", + "CMT_TOP_BYP4_3" + ], + [ + "CMT_FIFO_NW2A0_2", + "CMT_TOP_NW2A0_2" + ], + [ + "CMT_FIFO_SW2A1_10", + "CMT_TOP_SW2A1_10" + ], + [ + "CMT_FIFO_EE4C0_8", + "CMT_TOP_EE4C0_8" + ], + [ + "CMT_FIFO_L_BYP0_8", + "CMT_TOP_BYP0_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "CMT_TOP_ICLK_10" + ], + [ + "CMT_FIFO_WL1END2_2", + "CMT_TOP_WL1END2_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "CMT_TOP_OCLK_11" + ], + [ + "CMT_FIFO_L_IMUX12_1", + "CMT_TOP_IMUX12_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_9", + "CMT_TOP_LOGIC_OUTS_L_B7_9" + ], + [ + "CMT_FIFO_L_IMUX41_9", + "CMT_TOP_IMUX41_9" + ], + [ + "CMT_FIFO_L_FAN7_11", + "CMT_TOP_FAN7_11" + ], + [ + "CMT_FIFO_EE2A3_5", + "CMT_TOP_EE2A3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_3", + "CMT_TOP_LOGIC_OUTS_L_B21_3" + ], + [ + "CMT_FIFO_WW4B2_4", + "CMT_TOP_WW4B2_4" + ], + [ + "CMT_FIFO_L_IMUX3_2", + "CMT_TOP_IMUX3_2" + ], + [ + "CMT_FIFO_WR1END0_3", + "CMT_TOP_WR1END0_3" + ], + [ + "CMT_FIFO_SE4BEG0_10", + "CMT_TOP_SE4BEG0_10" + ], + [ + "CMT_FIFO_L_IMUX8_8", + "CMT_TOP_IMUX8_8" + ], + [ + "CMT_FIFO_WW4B3_9", + "CMT_TOP_WW4B3_9" + ], + [ + "CMT_FIFO_L_IMUX11_1", + "CMT_TOP_IMUX11_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_4", + "CMT_TOP_LOGIC_OUTS_L_B5_4" + ], + [ + "CMT_FIFO_LH3_0", + "CMT_TOP_LH3_0" + ], + [ + "CMT_FIFO_WR1END2_7", + "CMT_TOP_WR1END2_7" + ], + [ + "CMT_FIFO_NE2A2_7", + "CMT_TOP_NE2A2_7" + ], + [ + "CMT_FIFO_ER1BEG3_2", + "CMT_TOP_ER1BEG3_2" + ], + [ + "CMT_FIFO_WW2A1_0", + "CMT_TOP_WW2A1_0" + ], + [ + "CMT_FIFO_WL1END0_11", + "CMT_TOP_WL1END0_11" + ], + [ + "CMT_FIFO_NE4BEG1_9", + "CMT_TOP_NE4BEG1_9" + ], + [ + "CMT_FIFO_SW4A3_10", + "CMT_TOP_SW4A3_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_7", + "CMT_TOP_LOGIC_OUTS_L_B12_7" + ], + [ + "CMT_FIFO_WW4B3_1", + "CMT_TOP_WW4B3_1" + ], + [ + "CMT_FIFO_NW4END0_5", + "CMT_TOP_NW4END0_5" + ], + [ + "CMT_FIFO_L_BYP7_5", + "CMT_TOP_BYP7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_8", + "CMT_TOP_LOGIC_OUTS_L_B16_8" + ], + [ + "CMT_FIFO_SE4C1_6", + "CMT_TOP_SE4C1_6" + ], + [ + "CMT_FIFO_WW4B2_3", + "CMT_TOP_WW4B2_3" + ], + [ + "CMT_FIFO_L_IMUX3_1", + "CMT_TOP_IMUX3_1" + ], + [ + "CMT_FIFO_L_FAN4_5", + "CMT_TOP_FAN4_5" + ], + [ + "CMT_FIFO_L_IMUX32_8", + "CMT_TOP_IMUX32_8" + ], + [ + "CMT_FIFO_L_IMUX36_7", + "CMT_TOP_IMUX36_7" + ], + [ + "CMT_FIFO_EE4A0_8", + "CMT_TOP_EE4A0_8" + ], + [ + "CMT_FIFO_EE4C0_11", + "CMT_TOP_EE4C0_11" + ], + [ + "CMT_FIFO_NW2A0_5", + "CMT_TOP_NW2A0_5" + ], + [ + "CMT_FIFO_L_CLK0_10", + "CMT_TOP_CLK0_10" + ], + [ + "CMT_FIFO_EE4B3_5", + "CMT_TOP_EE4B3_5" + ], + [ + "CMT_FIFO_EE4BEG0_6", + "CMT_TOP_EE4BEG0_6" + ], + [ + "CMT_FIFO_L_IMUX1_0", + "CMT_TOP_IMUX1_0" + ], + [ + "CMT_FIFO_L_IMUX12_11", + "CMT_TOP_IMUX12_11" + ], + [ + "CMT_FIFO_L_IMUX14_8", + "CMT_TOP_IMUX14_8" + ], + [ + "CMT_FIFO_NW4A1_3", + "CMT_TOP_NW4A1_3" + ], + [ + "CMT_FIFO_L_IMUX17_11", + "CMT_TOP_IMUX17_11" + ], + [ + "CMT_FIFO_SE4BEG1_8", + "CMT_TOP_SE4BEG1_8" + ], + [ + "CMT_FIFO_L_IMUX5_10", + "CMT_TOP_IMUX5_10" + ], + [ + "CMT_FIFO_NE2A3_2", + "CMT_TOP_NE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX0_4", + "CMT_TOP_IMUX0_4" + ], + [ + "CMT_FIFO_NE4C3_2", + "CMT_TOP_NE4C3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_8", + "CMT_TOP_LOGIC_OUTS_L_B2_8" + ], + [ + "CMT_FIFO_LH4_6", + "CMT_TOP_LH4_6" + ], + [ + "CMT_FIFO_L_IMUX27_5", + "CMT_TOP_IMUX27_5" + ], + [ + "CMT_FIFO_LH5_0", + "CMT_TOP_LH5_0" + ], + [ + "CMT_FIFO_EE4B3_10", + "CMT_TOP_EE4B3_10" + ], + [ + "CMT_FIFO_NW4A3_8", + "CMT_TOP_NW4A3_8" + ], + [ + "CMT_FIFO_L_BYP0_3", + "CMT_TOP_BYP0_3" + ], + [ + "CMT_FIFO_L_IMUX24_8", + "CMT_TOP_IMUX24_8" + ], + [ + "CMT_FIFO_L_IMUX30_3", + "CMT_TOP_IMUX30_3" + ], + [ + "CMT_FIFO_L_FAN7_9", + "CMT_TOP_FAN7_9" + ], + [ + "CMT_FIFO_EE4B2_6", + "CMT_TOP_EE4B2_6" + ], + [ + "CMT_FIFO_L_IMUX14_4", + "CMT_TOP_IMUX14_4" + ], + [ + "CMT_FIFO_LH10_6", + "CMT_TOP_LH10_6" + ], + [ + "CMT_FIFO_WW4A0_2", + "CMT_TOP_WW4A0_2" + ], + [ + "CMT_FIFO_L_BYP0_10", + "CMT_TOP_BYP0_10" + ], + [ + "CMT_FIFO_L_IMUX36_2", + "CMT_TOP_IMUX36_2" + ], + [ + "CMT_FIFO_L_IMUX13_7", + "CMT_TOP_IMUX13_7" + ], + [ + "CMT_FIFO_SE2A1_11", + "CMT_TOP_SE2A1_11" + ], + [ + "CMT_FIFO_L_CTRL0_8", + "CMT_TOP_CTRL0_8" + ], + [ + "CMT_FIFO_SE4C2_1", + "CMT_TOP_SE4C2_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_7", + "CMT_TOP_LOGIC_OUTS_L_B17_7" + ], + [ + "CMT_FIFO_L_IMUX5_2", + "CMT_TOP_IMUX5_2" + ], + [ + "CMT_FIFO_EE4BEG0_5", + "CMT_TOP_EE4BEG0_5" + ], + [ + "CMT_FIFO_EE4B0_2", + "CMT_TOP_EE4B0_2" + ], + [ + "CMT_FIFO_L_BYP4_1", + "CMT_TOP_BYP4_1" + ], + [ + "CMT_FIFO_L_FAN1_7", + "CMT_TOP_FAN1_7" + ], + [ + "CMT_FIFO_L_IMUX28_6", + "CMT_TOP_IMUX28_6" + ], + [ + "CMT_FIFO_NE2A2_4", + "CMT_TOP_NE2A2_4" + ], + [ + "CMT_FIFO_WW2A1_9", + "CMT_TOP_WW2A1_9" + ], + [ + "CMT_FIFO_L_FAN1_6", + "CMT_TOP_FAN1_6" + ], + [ + "CMT_FIFO_L_IMUX13_5", + "CMT_TOP_IMUX13_5" + ], + [ + "CMT_FIFO_L_IMUX27_2", + "CMT_TOP_IMUX27_2" + ], + [ + "CMT_FIFO_L_IMUX8_4", + "CMT_TOP_IMUX8_4" + ], + [ + "CMT_FIFO_NE4C0_0", + "CMT_TOP_NE4C0_0" + ], + [ + "CMT_FIFO_NW4END1_11", + "CMT_TOP_NW4END1_11" + ], + [ + "CMT_FIFO_LH8_1", + "CMT_TOP_LH8_1" + ], + [ + "CMT_FIFO_L_IMUX30_7", + "CMT_TOP_IMUX30_7" + ], + [ + "CMT_FIFO_WW2A0_5", + "CMT_TOP_WW2A0_5" + ], + [ + "CMT_FIFO_LH6_4", + "CMT_TOP_LH6_4" + ], + [ + "CMT_FIFO_L_IMUX14_7", + "CMT_TOP_IMUX14_7" + ], + [ + "CMT_FIFO_L_IMUX11_6", + "CMT_TOP_IMUX11_6" + ], + [ + "CMT_FIFO_L_CLK1_9", + "CMT_TOP_CLK1_9" + ], + [ + "CMT_FIFO_L_IMUX13_1", + "CMT_TOP_IMUX13_1" + ], + [ + "CMT_FIFO_SE4C1_7", + "CMT_TOP_SE4C1_7" + ], + [ + "CMT_FIFO_LH9_6", + "CMT_TOP_LH9_6" + ], + [ + "CMT_FIFO_L_IMUX24_7", + "CMT_TOP_IMUX24_7" + ], + [ + "CMT_FIFO_L_IMUX41_10", + "CMT_TOP_IMUX41_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_4", + "CMT_TOP_LOGIC_OUTS_L_B11_4" + ], + [ + "CMT_FIFO_LH3_9", + "CMT_TOP_LH3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_9", + "CMT_TOP_LOGIC_OUTS_L_B20_9" + ], + [ + "CMT_FIFO_L_IMUX20_5", + "CMT_TOP_IMUX20_5" + ], + [ + "CMT_FIFO_EE4A2_6", + "CMT_TOP_EE4A2_6" + ], + [ + "CMT_FIFO_WR1END2_5", + "CMT_TOP_WR1END2_5" + ], + [ + "CMT_FIFO_LH1_7", + "CMT_TOP_LH1_7" + ], + [ + "CMT_FIFO_L_IMUX34_5", + "CMT_TOP_IMUX34_5" + ], + [ + "CMT_FIFO_EE4A0_4", + "CMT_TOP_EE4A0_4" + ], + [ + "CMT_FIFO_L_IMUX26_8", + "CMT_TOP_IMUX26_8" + ], + [ + "CMT_FIFO_LH8_8", + "CMT_TOP_LH8_8" + ], + [ + "CMT_FIFO_LH11_3", + "CMT_TOP_LH11_3" + ], + [ + "CMT_FIFO_EE2BEG0_4", + "CMT_TOP_EE2BEG0_4" + ], + [ + "CMT_FIFO_L_IMUX39_6", + "CMT_TOP_IMUX39_6" + ], + [ + "CMT_FIFO_WW4C1_5", + "CMT_TOP_WW4C1_5" + ], + [ + "CMT_FIFO_WW4END1_7", + "CMT_TOP_WW4END1_7" + ], + [ + "CMT_FIFO_L_BYP2_5", + "CMT_TOP_BYP2_5" + ], + [ + "CMT_FIFO_MONITOR_P_4", + "CMT_TOP_MONITOR_P_4" + ], + [ + "CMT_FIFO_L_IMUX4_1", + "CMT_TOP_IMUX4_1" + ], + [ + "CMT_FIFO_NW4END3_0", + "CMT_TOP_NW4END3_0" + ], + [ + "CMT_FIFO_ER1BEG3_10", + "CMT_TOP_ER1BEG3_10" + ], + [ + "CMT_FIFO_L_IMUX12_5", + "CMT_TOP_IMUX12_5" + ], + [ + "CMT_FIFO_L_IMUX1_2", + "CMT_TOP_IMUX1_2" + ], + [ + "CMT_FIFO_L_IMUX7_11", + "CMT_TOP_IMUX7_11" + ], + [ + "CMT_FIFO_L_IMUX28_11", + "CMT_TOP_IMUX28_11" + ], + [ + "CMT_FIFO_L_IMUX9_2", + "CMT_TOP_IMUX9_2" + ], + [ + "CMT_FIFO_L_BYP3_11", + "CMT_TOP_BYP3_11" + ], + [ + "CMT_FIFO_NW4A3_1", + "CMT_TOP_NW4A3_1" + ], + [ + "CMT_FIFO_L_CTRL1_2", + "CMT_TOP_CTRL1_2" + ], + [ + "CMT_FIFO_LH12_0", + "CMT_TOP_LH12_0" + ], + [ + "CMT_FIFO_L_IMUX23_5", + "CMT_TOP_IMUX23_5" + ], + [ + "CMT_FIFO_LH12_3", + "CMT_TOP_LH12_3" + ], + [ + "CMT_FIFO_L_IMUX16_4", + "CMT_TOP_IMUX16_4" + ], + [ + "CMT_FIFO_WR1END1_10", + "CMT_TOP_WR1END1_10" + ], + [ + "CMT_FIFO_L_IMUX11_4", + "CMT_TOP_IMUX11_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_3", + "CMT_TOP_LOGIC_OUTS_L_B20_3" + ], + [ + "CMT_FIFO_L_IMUX13_8", + "CMT_TOP_IMUX13_8" + ], + [ + "CMT_FIFO_L_IMUX34_7", + "CMT_TOP_IMUX34_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_10", + "CMT_TOP_LOGIC_OUTS_L_B5_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_7", + "CMT_TOP_LOGIC_OUTS_L_B10_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_2", + "CMT_TOP_LOGIC_OUTS_L_B15_2" + ], + [ + "CMT_FIFO_L_IMUX10_4", + "CMT_TOP_IMUX10_4" + ], + [ + "CMT_FIFO_L_IMUX34_4", + "CMT_TOP_IMUX34_4" + ], + [ + "CMT_FIFO_NW4A2_5", + "CMT_TOP_NW4A2_5" + ], + [ + "CMT_FIFO_L_IMUX27_6", + "CMT_TOP_IMUX27_6" + ], + [ + "CMT_FIFO_L_IMUX42_8", + "CMT_TOP_IMUX42_8" + ], + [ + "CMT_FIFO_L_IMUX31_1", + "CMT_TOP_IMUX31_1" + ], + [ + "CMT_FIFO_WW4END2_0", + "CMT_TOP_WW4END2_0" + ], + [ + "CMT_FIFO_SW4A0_10", + "CMT_TOP_SW4A0_10" + ], + [ + "CMT_FIFO_LH12_11", + "CMT_TOP_LH12_11" + ], + [ + "CMT_FIFO_NW4END2_4", + "CMT_TOP_NW4END2_4" + ], + [ + "CMT_FIFO_SE2A2_0", + "CMT_TOP_SE2A2_0" + ], + [ + "CMT_FIFO_SE2A3_5", + "CMT_TOP_SE2A3_5" + ], + [ + "CMT_FIFO_L_IMUX7_5", + "CMT_TOP_IMUX7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_7", + "CMT_TOP_LOGIC_OUTS_L_B9_7" + ], + [ + "CMT_FIFO_L_FAN3_6", + "CMT_TOP_FAN3_6" + ], + [ + "CMT_FIFO_EE4A2_2", + "CMT_TOP_EE4A2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_2", + "CMT_TOP_LOGIC_OUTS_L_B17_2" + ], + [ + "CMT_FIFO_L_IMUX22_10", + "CMT_TOP_IMUX22_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_9", + "CMT_TOP_LOGIC_OUTS_L_B22_9" + ], + [ + "CMT_FIFO_L_IMUX4_10", + "CMT_TOP_IMUX4_10" + ], + [ + "CMT_FIFO_L_BYP7_3", + "CMT_TOP_BYP7_3" + ], + [ + "CMT_FIFO_NE4BEG3_6", + "CMT_TOP_NE4BEG3_6" + ], + [ + "CMT_FIFO_L_CTRL0_10", + "CMT_TOP_CTRL0_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_5", + "CMT_TOP_LOGIC_OUTS_L_B13_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_11", + "CMT_TOP_LOGIC_OUTS_L_B19_11" + ], + [ + "CMT_FIFO_L_IMUX41_8", + "CMT_TOP_IMUX41_8" + ], + [ + "CMT_FIFO_SE2A1_0", + "CMT_TOP_SE2A1_0" + ], + [ + "CMT_FIFO_SW4END2_11", + "CMT_TOP_SW4END2_11" + ], + [ + "CMT_FIFO_L_PHASER_WRENABLE", + "CMT_PLL_PHASER_WRENABLE_TOFIFO" + ], + [ + "CMT_FIFO_WL1END0_3", + "CMT_TOP_WL1END0_3" + ], + [ + "CMT_FIFO_L_IMUX37_5", + "CMT_TOP_IMUX37_5" + ], + [ + "CMT_FIFO_LH12_8", + "CMT_TOP_LH12_8" + ], + [ + "CMT_FIFO_SW4END3_3", + "CMT_TOP_SW4END3_3" + ], + [ + "CMT_FIFO_NW4A1_5", + "CMT_TOP_NW4A1_5" + ], + [ + "CMT_FIFO_WW4END3_5", + "CMT_TOP_WW4END3_5" + ], + [ + "CMT_FIFO_L_BYP7_4", + "CMT_TOP_BYP7_4" + ], + [ + "CMT_FIFO_L_IMUX10_0", + "CMT_TOP_IMUX10_0" + ], + [ + "CMT_FIFO_EE4BEG0_2", + "CMT_TOP_EE4BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX33_0", + "CMT_TOP_IMUX33_0" + ], + [ + "CMT_FIFO_EL1BEG0_7", + "CMT_TOP_EL1BEG0_7" + ], + [ + "CMT_FIFO_SE2A2_5", + "CMT_TOP_SE2A2_5" + ], + [ + "CMT_FIFO_ER1BEG2_0", + "CMT_TOP_ER1BEG2_0" + ], + [ + "CMT_FIFO_L_CLK0_11", + "CMT_TOP_CLK0_11" + ], + [ + "CMT_FIFO_L_IMUX13_4", + "CMT_TOP_IMUX13_4" + ], + [ + "CMT_FIFO_L_BYP5_9", + "CMT_TOP_BYP5_9" + ], + [ + "CMT_FIFO_LH10_2", + "CMT_TOP_LH10_2" + ], + [ + "CMT_FIFO_L_IMUX33_4", + "CMT_TOP_IMUX33_4" + ], + [ + "CMT_FIFO_L_IMUX11_11", + "CMT_TOP_IMUX11_11" + ], + [ + "CMT_FIFO_SW4END0_8", + "CMT_TOP_SW4END0_8" + ], + [ + "CMT_FIFO_SW4END0_1", + "CMT_TOP_SW4END0_1" + ], + [ + "CMT_FIFO_L_IMUX14_0", + "CMT_TOP_IMUX14_0" + ], + [ + "CMT_FIFO_NW4END3_11", + "CMT_TOP_NW4END3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_6", + "CMT_TOP_LOGIC_OUTS_L_B21_6" + ], + [ + "CMT_FIFO_L_FAN7_8", + "CMT_TOP_FAN7_8" + ], + [ + "CMT_FIFO_EE4BEG1_7", + "CMT_TOP_EE4BEG1_7" + ], + [ + "CMT_FIFO_L_BYP3_7", + "CMT_TOP_BYP3_7" + ], + [ + "CMT_FIFO_L_IMUX26_0", + "CMT_TOP_IMUX26_0" + ], + [ + "CMT_FIFO_LH8_5", + "CMT_TOP_LH8_5" + ], + [ + "CMT_FIFO_WL1END0_7", + "CMT_TOP_WL1END0_7" + ], + [ + "CMT_FIFO_L_IMUX11_9", + "CMT_TOP_IMUX11_9" + ], + [ + "CMT_FIFO_WR1END0_4", + "CMT_TOP_WR1END0_4" + ], + [ + "CMT_FIFO_L_IMUX36_10", + "CMT_TOP_IMUX36_10" + ], + [ + "CMT_FIFO_EL1BEG1_1", + "CMT_TOP_EL1BEG1_1" + ], + [ + "CMT_FIFO_SE4C1_10", + "CMT_TOP_SE4C1_10" + ], + [ + "CMT_FIFO_NW4END0_10", + "CMT_TOP_NW4END0_10" + ], + [ + "CMT_FIFO_WW2END0_9", + "CMT_TOP_WW2END0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_6", + "CMT_TOP_LOGIC_OUTS_L_B1_6" + ], + [ + "CMT_FIFO_ER1BEG2_2", + "CMT_TOP_ER1BEG2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_9", + "CMT_TOP_LOGIC_OUTS_L_B19_9" + ], + [ + "CMT_FIFO_NE4C0_9", + "CMT_TOP_NE4C0_9" + ], + [ + "CMT_FIFO_SE2A0_4", + "CMT_TOP_SE2A0_4" + ], + [ + "CMT_FIFO_WW2A3_9", + "CMT_TOP_WW2A3_9" + ], + [ + "CMT_FIFO_L_IMUX21_9", + "CMT_TOP_IMUX21_9" + ], + [ + "CMT_FIFO_NE2A3_5", + "CMT_TOP_NE2A3_5" + ], + [ + "CMT_FIFO_NW2A0_7", + "CMT_TOP_NW2A0_7" + ], + [ + "CMT_FIFO_L_IMUX40_10", + "CMT_TOP_IMUX40_10" + ], + [ + "CMT_FIFO_L_IMUX6_9", + "CMT_TOP_IMUX6_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_4", + "CMT_TOP_LOGIC_OUTS_L_B8_4" + ], + [ + "CMT_FIFO_ER1BEG1_5", + "CMT_TOP_ER1BEG1_5" + ], + [ + "CMT_FIFO_WW4A2_1", + "CMT_TOP_WW4A2_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "CMT_TOP_OCLKDIV_6" + ], + [ + "CMT_FIFO_LH3_5", + "CMT_TOP_LH3_5" + ], + [ + "CMT_FIFO_SW4END0_9", + "CMT_TOP_SW4END0_9" + ], + [ + "CMT_FIFO_SE4BEG0_9", + "CMT_TOP_SE4BEG0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_3", + "CMT_TOP_LOGIC_OUTS_L_B9_3" + ], + [ + "CMT_FIFO_ER1BEG1_1", + "CMT_TOP_ER1BEG1_1" + ], + [ + "CMT_FIFO_EE2A2_0", + "CMT_TOP_EE2A2_0" + ], + [ + "CMT_FIFO_L_IMUX40_2", + "CMT_TOP_IMUX40_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_2", + "CMT_TOP_LOGIC_OUTS_L_B13_2" + ], + [ + "CMT_FIFO_L_IMUX22_9", + "CMT_TOP_IMUX22_9" + ], + [ + "CMT_FIFO_LH9_11", + "CMT_TOP_LH9_11" + ], + [ + "CMT_FIFO_WL1END3_3", + "CMT_TOP_WL1END3_3" + ], + [ + "CMT_FIFO_EE2A1_9", + "CMT_TOP_EE2A1_9" + ], + [ + "CMT_FIFO_LH4_9", + "CMT_TOP_LH4_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_3", + "CMT_TOP_LOGIC_OUTS_L_B12_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_9", + "CMT_TOP_LOGIC_OUTS_L_B21_9" + ], + [ + "CMT_FIFO_NW4END0_3", + "CMT_TOP_NW4END0_3" + ], + [ + "CMT_FIFO_SW4A3_1", + "CMT_TOP_SW4A3_1" + ], + [ + "CMT_FIFO_SW4END2_10", + "CMT_TOP_SW4END2_10" + ], + [ + "CMT_FIFO_SW4END0_7", + "CMT_TOP_SW4END0_7" + ], + [ + "CMT_FIFO_L_IMUX11_5", + "CMT_TOP_IMUX11_5" + ], + [ + "CMT_FIFO_ER1BEG3_7", + "CMT_TOP_ER1BEG3_7" + ], + [ + "CMT_FIFO_EE2BEG2_9", + "CMT_TOP_EE2BEG2_9" + ], + [ + "CMT_FIFO_EE4C0_10", + "CMT_TOP_EE4C0_10" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "CMT_TOP_R_UPPER_T" + ] + }, + { + "grid_deltas": [ + -1, + 5 + ], + "wire_pairs": [ + [ + "PCIE_IMUX32_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_IMUX9_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_IMUX18_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_IMUX23_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_SE2A3_5", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_IMUX10_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_FAN1_R_5", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_LH10_5", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_LH6_5", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_5", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_EE2A2_5", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_WW4B0_5", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_5", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_LH8_5", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4A0_5", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_IMUX1_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_IMUX5_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_EE2BEG3_5", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_WW2END2_5", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_EE2A1_5", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_IMUX4_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_IMUX44_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_IMUX6_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_IMUX41_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_WL1END2_5", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_SW2A1_5", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_NE2A2_5", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_LH2_5", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_WW2A2_5", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_NE2A3_5", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_WW2END1_5", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_5", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_IMUX19_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_IMUX43_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_IMUX11_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_WW4END2_5", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_IMUX29_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_IMUX21_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_WW4C1_5", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_5", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_NW2A3_5", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_EE2BEG1_5", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX40_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_WR1END0_5", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_BYP6_R_5", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_FAN6_R_5", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_WR1END1_5", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_IMUX15_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_FAN5_R_5", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_IMUX27_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_SE2A1_5", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_NW2A1_5", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_EE2BEG0_5", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_SE2A0_5", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_SW4END3_5", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_LH11_5", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_5", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_NE4BEG1_5", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_NW4A1_5", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_EE4BEG3_5", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_NE4C0_5", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_FAN7_R_5", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_BYP0_R_5", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_NW4END0_5", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_IMUX20_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_5", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_EL1BEG3_5", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_5", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_BYP4_R_5", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_5", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_IMUX17_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_NE2A0_5", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_IMUX2_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_WW4B1_5", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_WW4END0_5", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_IMUX24_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_SE4BEG2_5", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_5", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_NW4END2_5", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_EL1BEG1_5", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_FAN0_R_5", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_WW4A3_5", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_NW4END3_5", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_CTRL0_R_5", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_ER1BEG1_5", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_NE4C3_5", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_WW2END3_5", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_5", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_5", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_IMUX31_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_LH1_5", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_NW4A0_5", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WW4C0_5", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_IMUX34_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_WW2END0_5", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_IMUX7_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_NE4BEG0_5", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_5", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_5", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_SW4A0_5", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_EE4C3_5", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_EL1BEG0_5", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_NW4A3_5", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_LH12_5", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_IMUX28_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_IMUX13_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_WW4A0_5", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_BYP5_R_5", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_CLK1_R_5", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_IMUX47_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_WL1END0_5", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_5", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_IMUX42_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_LH3_5", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_EE2A0_5", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_IMUX8_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_ER1BEG3_5", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_EL1BEG2_5", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_LH4_5", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_IMUX30_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_MONITOR_P_5", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_IMUX26_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_SE4BEG0_5", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_IMUX25_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_SW4END0_5", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_LH5_5", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_SW4A3_5", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_LH7_5", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_WW2A0_5", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_IMUX38_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_BYP1_R_5", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_EE4BEG2_5", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_WW2A3_5", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_BYP7_R_5", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_IMUX16_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_NW4A2_5", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_WW4B2_5", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_SE4BEG1_5", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_SW4A1_5", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_SE4BEG3_5", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_SW2A0_5", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_WL1END3_5", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_WW4A1_5", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_5", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_5", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_5", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_NE4BEG2_5", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_EE4B3_5", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_EE4BEG0_5", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX45_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_IMUX3_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_NE4BEG3_5", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_NW2A0_5", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_WW4C2_5", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_SW4A2_5", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_IMUX46_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_EE4B0_5", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX12_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_FAN3_R_5", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_NW4END1_5", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_CTRL1_R_5", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_EE4C0_5", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_WW4END1_5", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_5", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_SW2A3_5", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_EE4A2_5", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_IMUX39_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_SW4END1_5", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_IMUX33_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_EE4BEG1_5", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_IMUX22_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_IMUX0_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_LH9_5", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_EE4B1_5", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_EE2BEG2_5", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_ER1BEG0_5", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_SE4C2_5", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_WW4A2_5", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_5", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_EE4C2_5", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_5", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_EE2A3_5", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_EE4A1_5", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_5", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_SE2A2_5", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_5", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_EE4A3_5", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_5", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_CLK0_R_5", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_WR1END3_5", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_SW4END2_5", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_SE4C1_5", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_EE4C1_5", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_BYP3_R_5", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_WW4C3_5", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_NE2A1_5", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_SE4C3_5", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_SE4C0_5", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_EE4B2_5", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_5", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_SW2A2_5", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_IMUX35_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_NE4C1_5", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_NE4C2_5", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_WR1END2_5", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_WW4B3_5", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_WL1END1_5", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_ER1BEG2_5", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_WW2A1_5", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_BYP2_R_5", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_MONITOR_N_5", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_IMUX37_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_IMUX36_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_FAN4_R_5", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_IMUX14_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_NW2A2_5", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_FAN2_R_5", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_WW4END3_5", + "INT_INTERFACE_WW4END3" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 5, + 4 + ], + "wire_pairs": [ + [ + "PCIE_LOGIC_OUTS_B1_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_WW4C1_6", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_WW4A0_6", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_SW4A1_6", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_LH10_6", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_EL1BEG1_6", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_SE4C0_6", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_EE2A3_6", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_FAN6_L_6", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_EE4C0_6", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_NW4A2_6", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_CLK0_L_6", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_BYP1_L_6", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_IMUX5_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_IMUX7_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_LH11_6", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_BYP4_L_6", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_NW4END1_6", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_WW4C2_6", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_EE4BEG2_6", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX29_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_WW4A2_6", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_IMUX31_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_SW4END2_6", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_LH7_6", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_SE4BEG0_6", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_FAN1_L_6", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_BYP7_L_6", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_LH12_6", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_NW4A1_6", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_EL1BEG3_6", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_WL1END2_6", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_WR1END2_6", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_NW2A0_6", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_WR1END0_6", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_NE4BEG2_6", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_IMUX47_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_WW2END3_6", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_IMUX33_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_IMUX23_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_WW4B3_6", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_IMUX42_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_IMUX24_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_IMUX46_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_CTRL1_L_6", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_NE2A0_6", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_CTRL0_L_6", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_WL1END1_6", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_IMUX0_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_IMUX15_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_IMUX1_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_WW2A0_6", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_WW4B1_6", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_SW4END0_6", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_IMUX25_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_SE4BEG3_6", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_NW4END2_6", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_SW2A0_6", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX36_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_BYP6_L_6", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_ER1BEG0_6", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_EE4BEG1_6", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_IMUX16_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_EE4A0_6", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_EE2A1_6", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_IMUX26_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_NW4A3_6", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_BYP0_L_6", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_EE2A2_6", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_WW4END2_6", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_EE4C1_6", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_EE4A3_6", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_FAN3_L_6", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_NE2A2_6", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_BYP5_L_6", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_WW4END0_6", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_NW4END3_6", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_LH6_6", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_IMUX13_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_LH4_6", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_NW2A3_6", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_IMUX41_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_FAN7_L_6", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_IMUX35_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_NE4C1_6", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_EE4B1_6", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_IMUX3_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_SE4BEG2_6", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_IMUX20_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_EE2BEG2_6", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_SW4A3_6", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_IMUX22_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_WW2A1_6", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_WW4END3_6", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_LH1_6", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_SE2A2_6", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_NW4A0_6", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_NE4C2_6", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_LH3_6", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_EE4BEG0_6", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX34_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_NE2A3_6", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_LH5_6", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_WL1END3_6", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_ER1BEG3_6", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_SE2A3_6", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_IMUX43_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_SE2A0_6", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_EE4B2_6", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_SE4C1_6", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_EE4B0_6", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_BYP3_L_6", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_SE4C3_6", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_WR1END3_6", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_FAN2_L_6", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_IMUX6_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_WL1END0_6", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_WW4B0_6", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_NW2A1_6", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_IMUX44_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_IMUX8_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_EE4C3_6", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_WW2END0_6", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_IMUX4_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_IMUX2_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_IMUX12_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_EE2BEG3_6", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_NW2A2_6", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_ER1BEG2_6", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_WW2END1_6", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_EE4C2_6", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_IMUX14_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_SE2A1_6", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_EE2BEG1_6", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_IMUX32_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_SW4A2_6", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_WW2A2_6", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_WR1END1_6", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_FAN0_L_6", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_EE4A1_6", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_EE4B3_6", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_IMUX11_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_NE4C0_6", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_NE4BEG3_6", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_WW4C3_6", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_SW2A1_6", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_WW4A1_6", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_FAN5_L_6", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_NE2A1_6", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_WW2END2_6", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_IMUX18_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_IMUX21_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_EL1BEG2_6", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_EE4A2_6", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_SE4BEG1_6", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_IMUX30_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_WW4A3_6", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_IMUX40_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_EL1BEG0_6", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_IMUX39_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_SW4A0_6", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_BYP2_L_6", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_CLK1_L_6", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_SW4END1_6", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_IMUX19_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_LH8_6", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_IMUX45_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_ER1BEG1_6", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_EE2BEG0_6", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_EE4BEG3_6", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_NW4END0_6", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_IMUX17_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_SW4END3_6", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_NE4BEG0_6", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_WW4END1_6", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_IMUX27_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_WW2A3_6", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_WW4B2_6", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_FAN4_L_6", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_SW2A3_6", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX28_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_LH2_6", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_LH9_6", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_IMUX38_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_6", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_SE4C2_6", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_WW4C0_6", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_EE2A0_6", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_IMUX9_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_SW2A2_6", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_NE4C3_6", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_IMUX37_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_IMUX10_L_6", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_NE4BEG1_6", + "INT_INTERFACE_NE4BEG1" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CCIO1", + "HCLK_CCIO1" + ], + [ + "HCLK_INT_INTERFACE_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_INT_INTERFACE_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_INT_INTERFACE_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_INT_INTERFACE_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_INT_INTERFACE_CCIO3", + "HCLK_CCIO3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_INT_INTERFACE_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CCIO0", + "HCLK_CCIO0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_INT_INTERFACE_CCIO2", + "HCLK_CCIO2" + ], + [ + "HCLK_INT_INTERFACE_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_INT_INTERFACE_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_INT_PERFCLK3" + ] + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_R" + ] + }, + { + "grid_deltas": [ + -1, + -6 + ], + "wire_pairs": [ + [ + "CMT_TOP_SW4END0_14", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4C0_14", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4C3_14", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE2BEG3_14", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_EE2A0_14", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_WW4B2_14", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_SE4C3_14", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH12_14", + "VBRK_LH12" + ], + [ + "CMT_TOP_WW4END2_14", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4B0_14", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C1_14", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NE4BEG3_14", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SE4C2_14", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_SW2A1_14", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4C2_14", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE4BEG1_14", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4A3_14", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4A3_14", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_ER1BEG0_14", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_ER1BEG2_14", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SE4C1_14", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A3_14", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4C3_14", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_EE4BEG3_14", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW4A1_14", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW4A0_14", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4END0_14", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE2A1_14", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C2_14", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WR1END2_14", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END3_14", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WW4C0_14", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NE4BEG2_14", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A0_14", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END1_14", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4B1_14", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A2_14", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE2BEG2_14", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH6_14", + "VBRK_LH6" + ], + [ + "CMT_TOP_NE2A0_14", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SW4A1_14", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SW2A3_14", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4END3_14", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_WW4B0_14", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE2BEG1_14", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_NE4C2_14", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NE4BEG1_14", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG1_14", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH10_14", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4C1_14", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG0_14", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WL1END1_14", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_NE2A3_14", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW4B3_14", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW2A0_14", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_EE2A2_14", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EL1BEG0_14", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_EE4C3_14", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4A2_14", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4A2_14", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_WW2A2_14", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NE4BEG0_14", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_EE4A1_14", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WL1END3_14", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_EE2BEG0_14", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW2A3_14", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SW4END1_14", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4A3_14", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_NW4A3_14", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NW4END2_14", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE2A2_14", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_SE2A1_14", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4END1_14", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SW4END2_14", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE4B2_14", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE4BEG0_14", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_EL1BEG2_14", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4B1_14", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_NW4A1_14", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WR1END0_14", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4A0_14", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NW2A3_14", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_LH4_14", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW2A1_14", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WR1END1_14", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EL1BEG3_14", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SE2A0_14", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_LH2_14", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4B3_14", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_WW2A0_14", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH9_14", + "VBRK_LH9" + ], + [ + "CMT_TOP_LH8_14", + "VBRK_LH8" + ], + [ + "CMT_TOP_ER1BEG3_14", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WW2END1_14", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW2END0_14", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_ER1BEG1_14", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SE4BEG3_14", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_SW2A0_14", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NW4A2_14", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_WW4END3_14", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE2A1_14", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_SW4A2_14", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_LH5_14", + "VBRK_LH5" + ], + [ + "CMT_TOP_LH3_14", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C0_14", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_NE4C1_14", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_SE4BEG2_14", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SE4BEG1_14", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH1_14", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW4END0_14", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE2A2_14", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END2_14", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4BEG2_14", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WL1END0_14", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4C0_14", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NW2A2_14", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A1_14", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH7_14", + "VBRK_LH7" + ], + [ + "CMT_TOP_WR1END3_14", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SW4END3_14", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE2A3_14", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW4A0_14", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_LH11_14", + "VBRK_LH11" + ], + [ + "CMT_TOP_WL1END2_14", + "VBRK_WL1END2" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 4 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_4" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_4" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_4" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_4" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_4" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_4" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_4" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_4" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_4" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_4" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_4" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_4" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_4" + ], + [ + "INT_FEEDTHRU_2_MONITOR_N", + "MONITOR_HORIZ_VAUXN4_LEFT" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_4" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_4" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_4" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_4" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_4" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_4" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_4" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_4" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_4" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_4" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_4" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_4" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_4" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_4" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_4" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_4" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_4" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_4" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_4" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_4" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_4" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_4" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_4" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_4" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_4" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_4" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_4" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_4" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_4" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_4" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_4" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_4" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_4" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_4" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_4" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_4" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_4" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_4" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_4" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_4" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_4" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_4" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_4" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_4" + ], + [ + "INT_FEEDTHRU_2_MONITOR_P", + "MONITOR_HORIZ_VAUXP4_LEFT" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_4" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_4" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_4" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_4" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_4" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_4" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_4" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_4" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_4" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_4" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_4" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_4" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_4" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_4" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_4" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_4" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_4" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_4" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_4" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_4" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_4" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_4" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_4" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_4" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_4" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_4" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_4" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_4" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_4" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_4" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_4" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_4" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_4" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_4" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_4" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_4" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_4" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_4" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_4" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_4" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_4" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_4" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_4" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_4" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_4" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_4" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_4" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_4" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_4" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_4" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_4" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_4" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_4" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_4" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_4" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_4" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_4" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_4" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_4" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_4" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_4" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_4" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_4" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_4" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_4" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_4" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_4" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_BOT_FUJI2" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SW4END0_11", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_SE4C1_11", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_EE4C2_11", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_WW4A3_11", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_EL1BEG0_11", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_WW2A0_11", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_NE2A3_11", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_WW4A2_11", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EL1BEG1_11", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW2END1_11", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_NW2A2_11", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_WW4A1_11", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_NW4A0_11", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SE4BEG0_11", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_NW4END0_11", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SE2A2_11", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4BEG0_11", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE4BEG2_11", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SW4A3_11", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_LH7_11", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_SW4END3_11", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_ER1BEG1_11", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_EE4C1_11", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE4B0_11", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WR1END3_11", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE4BEG3_11", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_NE4C3_11", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_NE4BEG3_11", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_SE4BEG3_11", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_WW4C3_11", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE2BEG1_11", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_WW2END3_11", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_WW4C1_11", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_NE4BEG2_11", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_LH1_11", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_EE2A2_11", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_SE4C3_11", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_LH3_11", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SW4END1_11", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_WR1END0_11", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_NE4BEG1_11", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_LH9_11", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_EE4BEG1_11", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_LH8_11", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_EE2A0_11", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_SE2A0_11", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_WL1END1_11", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_LH10_11", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_EE4A2_11", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_WW2A2_11", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4C1_11", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE4BEG0_11", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_EE2BEG3_11", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_WW4B3_11", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_WR1END2_11", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_EE2A3_11", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW2END0_11", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NE2A2_11", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_SE2A3_11", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_NE4C2_11", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_SW2A0_11", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WW2END2_11", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SW2A2_11", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WW4B0_11", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_EE4A0_11", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_WL1END0_11", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_NE2A1_11", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NW2A0_11", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_LH6_11", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WW4B1_11", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_SE4BEG1_11", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_WW4END1_11", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_LH2_11", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_ER1BEG3_11", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_NE2A0_11", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_ER1BEG0_11", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_WW4C2_11", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NW4A3_11", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WW2A1_11", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WW4END0_11", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EE4B1_11", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_WW2A3_11", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_EE2A1_11", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_SW2A1_11", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4A1_11", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NE4C0_11", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_LH12_11", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_SE2A1_11", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_NW4END3_11", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_NW2A1_11", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SW4A0_11", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_LH5_11", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE4C0_11", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EL1BEG2_11", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_EE4C3_11", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_SE4C0_11", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_SW4END2_11", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_EE2BEG2_11", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW4A0_11", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_WW4END2_11", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_SW4A2_11", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_LH4_11", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_LH11_11", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WL1END3_11", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_ER1BEG2_11", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_WL1END2_11", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_NW2A3_11", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_WW4B2_11", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE4B3_11", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_EE2BEG0_11", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WR1END1_11", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SE4C2_11", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_NW4A2_11", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NW4END2_11", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4END3_11", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4C0_11", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_SW4A1_11", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NW4A1_11", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SW2A3_11", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_EE4B2_11", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_NW4END1_11", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_SE4BEG2_11", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG3_11", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_EE4A3_11", + "INT_FEEDTHRU_2_EE4A3" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 0, + 5 + ], + "wire_pairs": [ + [ + "BRKH_DSP_PCIN5", + "DSP_PCOUT5" + ], + [ + "BRKH_DSP_PCIN12", + "DSP_PCOUT12" + ], + [ + "BRKH_DSP_PCIN44", + "DSP_PCOUT44" + ], + [ + "BRKH_DSP_CARRYCASCIN", + "DSP_CARRYCASCOUT" + ], + [ + "BRKH_DSP_PCIN30", + "DSP_PCOUT30" + ], + [ + "BRKH_DSP_PCIN47", + "DSP_PCOUT47" + ], + [ + "BRKH_DSP_PCIN0", + "DSP_PCOUT0" + ], + [ + "BRKH_DSP_PCIN15", + "DSP_PCOUT15" + ], + [ + "BRKH_DSP_ACIN27", + "DSP_ACOUT27" + ], + [ + "BRKH_DSP_ACIN26", + "DSP_ACOUT26" + ], + [ + "BRKH_DSP_ACIN22", + "DSP_ACOUT22" + ], + [ + "BRKH_DSP_ACIN18", + "DSP_ACOUT18" + ], + [ + "BRKH_DSP_BCIN15", + "DSP_BCOUT15" + ], + [ + "BRKH_DSP_PCIN20", + "DSP_PCOUT20" + ], + [ + "BRKH_DSP_BCIN11", + "DSP_BCOUT11" + ], + [ + "BRKH_DSP_PCIN43", + "DSP_PCOUT43" + ], + [ + "BRKH_DSP_PCIN2", + "DSP_PCOUT2" + ], + [ + "BRKH_DSP_ACIN1", + "DSP_ACOUT1" + ], + [ + "BRKH_DSP_ACIN5", + "DSP_ACOUT5" + ], + [ + "BRKH_DSP_PCIN10", + "DSP_PCOUT10" + ], + [ + "BRKH_DSP_ACIN11", + "DSP_ACOUT11" + ], + [ + "BRKH_DSP_BCIN2", + "DSP_BCOUT2" + ], + [ + "BRKH_DSP_PCIN46", + "DSP_PCOUT46" + ], + [ + "BRKH_DSP_BCIN8", + "DSP_BCOUT8" + ], + [ + "BRKH_DSP_PCIN35", + "DSP_PCOUT35" + ], + [ + "BRKH_DSP_PCIN9", + "DSP_PCOUT9" + ], + [ + "BRKH_DSP_BCIN6", + "DSP_BCOUT6" + ], + [ + "BRKH_DSP_PCIN16", + "DSP_PCOUT16" + ], + [ + "BRKH_DSP_BCIN16", + "DSP_BCOUT16" + ], + [ + "BRKH_DSP_ACIN0", + "DSP_ACOUT0" + ], + [ + "BRKH_DSP_ACIN4", + "DSP_ACOUT4" + ], + [ + "BRKH_DSP_BCIN17", + "DSP_BCOUT17" + ], + [ + "BRKH_DSP_PCIN13", + "DSP_PCOUT13" + ], + [ + "BRKH_DSP_PCIN26", + "DSP_PCOUT26" + ], + [ + "BRKH_DSP_ACIN9", + "DSP_ACOUT9" + ], + [ + "BRKH_DSP_ACIN17", + "DSP_ACOUT17" + ], + [ + "BRKH_DSP_ACIN28", + "DSP_ACOUT28" + ], + [ + "BRKH_DSP_ACIN12", + "DSP_ACOUT12" + ], + [ + "BRKH_DSP_PCIN4", + "DSP_PCOUT4" + ], + [ + "BRKH_DSP_ACIN3", + "DSP_ACOUT3" + ], + [ + "BRKH_DSP_BCIN10", + "DSP_BCOUT10" + ], + [ + "BRKH_DSP_PCIN8", + "DSP_PCOUT8" + ], + [ + "BRKH_DSP_ACIN21", + "DSP_ACOUT21" + ], + [ + "BRKH_DSP_PCIN33", + "DSP_PCOUT33" + ], + [ + "BRKH_DSP_PCIN22", + "DSP_PCOUT22" + ], + [ + "BRKH_DSP_PCIN24", + "DSP_PCOUT24" + ], + [ + "BRKH_DSP_ACIN20", + "DSP_ACOUT20" + ], + [ + "BRKH_DSP_PCIN14", + "DSP_PCOUT14" + ], + [ + "BRKH_DSP_PCIN45", + "DSP_PCOUT45" + ], + [ + "BRKH_DSP_PCIN25", + "DSP_PCOUT25" + ], + [ + "BRKH_DSP_PCIN31", + "DSP_PCOUT31" + ], + [ + "BRKH_DSP_PCIN17", + "DSP_PCOUT17" + ], + [ + "BRKH_DSP_PCIN36", + "DSP_PCOUT36" + ], + [ + "BRKH_DSP_BCIN13", + "DSP_BCOUT13" + ], + [ + "BRKH_DSP_ACIN8", + "DSP_ACOUT8" + ], + [ + "BRKH_DSP_ACIN6", + "DSP_ACOUT6" + ], + [ + "BRKH_DSP_PCIN41", + "DSP_PCOUT41" + ], + [ + "BRKH_DSP_PCIN27", + "DSP_PCOUT27" + ], + [ + "BRKH_DSP_ACIN14", + "DSP_ACOUT14" + ], + [ + "BRKH_DSP_PCIN11", + "DSP_PCOUT11" + ], + [ + "BRKH_DSP_PCIN32", + "DSP_PCOUT32" + ], + [ + "BRKH_DSP_BCIN4", + "DSP_BCOUT4" + ], + [ + "BRKH_DSP_BCIN1", + "DSP_BCOUT1" + ], + [ + "BRKH_DSP_PCIN23", + "DSP_PCOUT23" + ], + [ + "BRKH_DSP_MULTSIGNIN", + "DSP_MULTSIGNOUT" + ], + [ + "BRKH_DSP_ACIN23", + "DSP_ACOUT23" + ], + [ + "BRKH_DSP_PCIN39", + "DSP_PCOUT39" + ], + [ + "BRKH_DSP_PCIN7", + "DSP_PCOUT7" + ], + [ + "BRKH_DSP_PCIN19", + "DSP_PCOUT19" + ], + [ + "BRKH_DSP_ACIN24", + "DSP_ACOUT24" + ], + [ + "BRKH_DSP_BCIN3", + "DSP_BCOUT3" + ], + [ + "BRKH_DSP_PCIN6", + "DSP_PCOUT6" + ], + [ + "BRKH_DSP_ACIN10", + "DSP_ACOUT10" + ], + [ + "BRKH_DSP_BCIN12", + "DSP_BCOUT12" + ], + [ + "BRKH_DSP_PCIN1", + "DSP_PCOUT1" + ], + [ + "BRKH_DSP_PCIN37", + "DSP_PCOUT37" + ], + [ + "BRKH_DSP_BCIN14", + "DSP_BCOUT14" + ], + [ + "BRKH_DSP_PCIN34", + "DSP_PCOUT34" + ], + [ + "BRKH_DSP_PCIN42", + "DSP_PCOUT42" + ], + [ + "BRKH_DSP_PCIN21", + "DSP_PCOUT21" + ], + [ + "BRKH_DSP_PCIN38", + "DSP_PCOUT38" + ], + [ + "BRKH_DSP_PCIN3", + "DSP_PCOUT3" + ], + [ + "BRKH_DSP_ACIN7", + "DSP_ACOUT7" + ], + [ + "BRKH_DSP_BCIN9", + "DSP_BCOUT9" + ], + [ + "BRKH_DSP_PCIN28", + "DSP_PCOUT28" + ], + [ + "BRKH_DSP_BCIN7", + "DSP_BCOUT7" + ], + [ + "BRKH_DSP_ACIN16", + "DSP_ACOUT16" + ], + [ + "BRKH_DSP_BCIN0", + "DSP_BCOUT0" + ], + [ + "BRKH_DSP_ACIN19", + "DSP_ACOUT19" + ], + [ + "BRKH_DSP_PCIN40", + "DSP_PCOUT40" + ], + [ + "BRKH_DSP_ACIN15", + "DSP_ACOUT15" + ], + [ + "BRKH_DSP_PCIN18", + "DSP_PCOUT18" + ], + [ + "BRKH_DSP_ACIN25", + "DSP_ACOUT25" + ], + [ + "BRKH_DSP_PCIN29", + "DSP_PCOUT29" + ], + [ + "BRKH_DSP_ACIN29", + "DSP_ACOUT29" + ], + [ + "BRKH_DSP_ACIN13", + "DSP_ACOUT13" + ], + [ + "BRKH_DSP_ACIN2", + "DSP_ACOUT2" + ], + [ + "BRKH_DSP_BCIN5", + "DSP_BCOUT5" + ] + ], + "tile_types": [ + "BRKH_DSP_L", + "DSP_L" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "CLK_HROW_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_LH10_3", + "VBRK_LH10" + ], + [ + "CLK_HROW_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_LH7_3", + "VBRK_LH7" + ], + [ + "CLK_HROW_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_LH1_3", + "VBRK_LH1" + ], + [ + "CLK_HROW_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_LH4_3", + "VBRK_LH4" + ], + [ + "CLK_HROW_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_LH8_3", + "VBRK_LH8" + ], + [ + "CLK_HROW_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_LH6_3", + "VBRK_LH6" + ], + [ + "CLK_HROW_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_LH9_3", + "VBRK_LH9" + ], + [ + "CLK_HROW_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_LH3_3", + "VBRK_LH3" + ], + [ + "CLK_HROW_LH11_3", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH12_3", + "VBRK_LH12" + ], + [ + "CLK_HROW_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_EL1BEG1_3", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_LH2_3", + "VBRK_LH2" + ], + [ + "CLK_HROW_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_LH5_3", + "VBRK_LH5" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -7 + ], + "wire_pairs": [ + [ + "CMT_TOP_EL1BEG1_8", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG1_8", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NW4A0_8", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4B0_8", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_8", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW2A0_8", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW2A0_8", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4BEG2_8", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_NE4C0_8", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_ER1BEG2_8", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_8", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_LH12_8", + "VBRK_LH12" + ], + [ + "CMT_TOP_EL1BEG2_8", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_LH1_8", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH10_8", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW4B1_8", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG2_8", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW4A3_8", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4C3_8", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_NW2A0_8", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NW4END0_8", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE2A2_8", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4C1_8", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW4C2_8", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW4A1_8", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NW2A1_8", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SE4BEG0_8", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_8", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_LH3_8", + "VBRK_LH3" + ], + [ + "CMT_TOP_WR1END2_8", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A0_8", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4A2_8", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END1_8", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A0_8", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A1_8", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EL1BEG0_8", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_EE4A3_8", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C3_8", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE4A0_8", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END1_8", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH4_8", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2A0_8", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH2_8", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4C1_8", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NE2A2_8", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2A3_8", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_NW4A3_8", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4END2_8", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE2A1_8", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END2_8", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2END0_8", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2BEG0_8", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4C0_8", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG0_8", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_WR1END0_8", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_SE4C2_8", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4END1_8", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NE2A1_8", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4B3_8", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_8", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C2_8", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4B1_8", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW2A3_8", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SE4C1_8", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WR1END3_8", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW2A2_8", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C0_8", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4C1_8", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH11_8", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4B2_8", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW2A3_8", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NW4END2_8", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A0_8", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WR1END1_8", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH5_8", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END3_8", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH6_8", + "VBRK_LH6" + ], + [ + "CMT_TOP_NE4BEG3_8", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_LH8_8", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A1_8", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE2BEG2_8", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4C3_8", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NW2A2_8", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END3_8", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE2A3_8", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_ER1BEG1_8", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_8", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_NE4BEG1_8", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_WW4A2_8", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG0_8", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NE4C2_8", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SE4BEG3_8", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C0_8", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_8", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2BEG3_8", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH9_8", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE4B2_8", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_WL1END0_8", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_WW2END3_8", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EL1BEG3_8", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG3_8", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4BEG3_8", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WL1END1_8", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2A1_8", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SE4BEG2_8", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW2A3_8", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SE4C3_8", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE2A2_8", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_8", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4A1_8", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW4A2_8", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SW2A2_8", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_NW4END3_8", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SW4END1_8", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END3_8", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4BEG1_8", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4END2_8", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH7_8", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4BEG0_8", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2BEG1_8", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_8", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A3_8", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WL1END2_8", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A0_8", + "VBRK_WW4A0" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "CLK_HROW_SW2A3_1", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_EE2BEG1_1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_IMUX47_1", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_IMUX32_1", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_BYP3_1", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_WL1END0_1", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_WW4C0_1", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_NE2A1_1", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_WW4A2_1", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_NE4C0_1", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_FAN4_1", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_IMUX26_1", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_NE4BEG1_1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_IMUX9_1", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_IMUX35_1", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_IMUX25_1", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_EE2BEG0_1", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_EE2A1_1", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_IMUX33_1", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_EL1BEG1_1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_EE4A1_1", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_SW4A2_1", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_IMUX15_1", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_IMUX41_1", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_NW4A2_1", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_EE2A2_1", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_IMUX11_1", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_IMUX38_1", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_EE2A0_1", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_FAN2_1", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_SE4C3_1", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_EE4BEG3_1", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_WW4C3_1", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_SW4END0_1", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_CLK0_1", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_IMUX30_1", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_CTRL0_1", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_EE4BEG1_1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_IMUX42_1", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_WW2END2_1", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_WR1END0_1", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_WW2END0_1", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_EE2BEG3_1", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_BYP5_1", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_NW2A0_1", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_IMUX17_1", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_LH4_1", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_NE2A3_1", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_FAN7_1", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_EE4BEG2_1", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_IMUX14_1", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_IMUX39_1", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_WW2END3_1", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_NE2A2_1", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_SW4END1_1", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_SW2A1_1", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_EE4B0_1", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_WW2A3_1", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_NW4A3_1", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_IMUX31_1", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_IMUX34_1", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_WR1END3_1", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_IMUX20_1", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_NE4BEG2_1", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_CTRL1_1", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_EE2A3_1", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_IMUX46_1", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_IMUX13_1", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_WW4END2_1", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_EL1BEG3_1", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_IMUX28_1", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_IMUX8_1", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_LH8_1", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_NW4END0_1", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_BYP1_1", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_WW4A1_1", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_LH2_1", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_NW4END2_1", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_EE2BEG2_1", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_IMUX43_1", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_NE4C2_1", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_SE2A1_1", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_EE4A0_1", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_CLK1_1", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_LH10_1", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_IMUX12_1", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_NW2A1_1", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_LH7_1", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_LH12_1", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_FAN0_1", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_NE4C3_1", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_LH5_1", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_IMUX44_1", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_SW2A0_1", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE4C0_1", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_IMUX29_1", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_IMUX7_1", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_WW4B0_1", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_WL1END2_1", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_FAN5_1", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_NW4A0_1", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_SW4A3_1", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_IMUX6_1", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_NE4BEG3_1", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_WW2END1_1", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_SW4A1_1", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_LH3_1", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_IMUX2_1", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_WW2A0_1", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4B1_1", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_ER1BEG1_1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_WR1END1_1", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_NE4BEG0_1", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_WW4B1_1", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_SW4END2_1", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_NE4C1_1", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_LH9_1", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_IMUX19_1", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_LH11_1", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_SW4A0_1", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_SE2A3_1", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_BYP6_1", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_SW2A2_1", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_SE4BEG0_1", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_IMUX22_1", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_NW2A2_1", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_WW4C1_1", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_IMUX23_1", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_ER1BEG3_1", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_IMUX37_1", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_IMUX4_1", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_SE4BEG3_1", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_NW4END1_1", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_IMUX45_1", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_BYP0_1", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_IMUX27_1", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_WW4C2_1", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_LH6_1", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_EL1BEG0_1", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_EE4B2_1", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_FAN3_1", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_LH1_1", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_NW4END3_1", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_WL1END3_1", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_WW4B3_1", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_BYP7_1", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_IMUX1_1", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_SE4C0_1", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_EE4C3_1", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_SE2A2_1", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_NW4A1_1", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_WW4A0_1", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_FAN6_1", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_EE4C1_1", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_EE4B3_1", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_EE4A3_1", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_IMUX10_1", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_IMUX36_1", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_IMUX21_1", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_NE2A0_1", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_WW4B2_1", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_ER1BEG2_1", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_WW4END1_1", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_WW4END0_1", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_IMUX16_1", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_SW4END3_1", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_EL1BEG2_1", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_FAN1_1", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_IMUX24_1", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_BYP2_1", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_WL1END1_1", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_EE4BEG0_1", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_IMUX3_1", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_SE4C2_1", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_WW4A3_1", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_WR1END2_1", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_SE4BEG2_1", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_SE4C1_1", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_IMUX40_1", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_NW2A3_1", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_WW4END3_1", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_IMUX0_1", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_EE4C2_1", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_IMUX5_1", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_BYP4_1", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_ER1BEG0_1", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_EE4A2_1", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_IMUX18_1", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_SE2A0_1", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_SE4BEG1_1", + "INT_INTERFACE_SE4BEG1" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + -2 + ], + "wire_pairs": [ + [ + "IOI_IOCLK1", + "IOI_SING_IOCLK1" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_SING_LEAF_GCLK2" + ], + [ + "IOI_IOCLK3", + "IOI_SING_IOCLK3" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_SING_LEAF_GCLK4" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_SING_RCLK_FORIO2" + ], + [ + "IOI_IOCLK2", + "IOI_SING_IOCLK2" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_SING_LEAF_GCLK5" + ], + [ + "IOI_TBYTEIN", + "IOI_SING_TBYTEIN" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_SING_LEAF_GCLK1" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_SING_RCLK_FORIO1" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_SING_LEAF_GCLK3" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_SING_RCLK_FORIO0" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_SING_LEAF_GCLK0" + ], + [ + "IOI_IOCLK0", + "IOI_SING_IOCLK0" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_SING_RCLK_FORIO3" + ] + ], + "tile_types": [ + "RIOI", + "RIOI_SING" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "DSP_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "DSP_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "DSP_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "DSP_LH3_4", + "VBRK_LH3" + ], + [ + "DSP_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "DSP_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "DSP_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "DSP_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "DSP_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "DSP_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "DSP_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "DSP_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "DSP_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "DSP_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "DSP_LH6_4", + "VBRK_LH6" + ], + [ + "DSP_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "DSP_LH8_4", + "VBRK_LH8" + ], + [ + "DSP_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "DSP_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "DSP_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "DSP_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "DSP_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "DSP_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "DSP_LH1_4", + "VBRK_LH1" + ], + [ + "DSP_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "DSP_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "DSP_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "DSP_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "DSP_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "DSP_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "DSP_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "DSP_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "DSP_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "DSP_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "DSP_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "DSP_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "DSP_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "DSP_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "DSP_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "DSP_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "DSP_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "DSP_LH2_4", + "VBRK_LH2" + ], + [ + "DSP_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "DSP_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "DSP_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "DSP_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "DSP_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "DSP_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "DSP_LH10_4", + "VBRK_LH10" + ], + [ + "DSP_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "DSP_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "DSP_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "DSP_LH5_4", + "VBRK_LH5" + ], + [ + "DSP_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "DSP_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "DSP_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "DSP_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "DSP_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "DSP_LH4_4", + "VBRK_LH4" + ], + [ + "DSP_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "DSP_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "DSP_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "DSP_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "DSP_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "DSP_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "DSP_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "DSP_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "DSP_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "DSP_LH9_4", + "VBRK_LH9" + ], + [ + "DSP_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "DSP_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "DSP_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "DSP_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "DSP_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "DSP_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "DSP_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "DSP_MONITOR_N_4", + "VBRK_MONITOR_N" + ], + [ + "DSP_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "DSP_LH7_4", + "VBRK_LH7" + ], + [ + "DSP_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "DSP_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "DSP_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "DSP_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "DSP_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "DSP_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "DSP_LH11_4", + "VBRK_LH11" + ], + [ + "DSP_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "DSP_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "DSP_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "DSP_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "DSP_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "DSP_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "DSP_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "DSP_MONITOR_P_4", + "VBRK_MONITOR_P" + ], + [ + "DSP_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "DSP_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "DSP_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "DSP_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "DSP_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "DSP_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "DSP_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "DSP_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "DSP_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "DSP_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "DSP_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "DSP_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "DSP_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "DSP_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "DSP_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "DSP_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "DSP_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "DSP_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "DSP_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "DSP_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "DSP_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "DSP_LH12_4", + "VBRK_LH12" + ], + [ + "DSP_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "DSP_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "DSP_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "DSP_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "DSP_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "DSP_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "DSP_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "DSP_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "DSP_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "DSP_SW4A2_4", + "VBRK_SW4A2" + ] + ], + "tile_types": [ + "DSP_L", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "CMT_TOP_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH1_2", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH2_2", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_LH6_2", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH7_2", + "VBRK_LH7" + ], + [ + "CMT_TOP_LH12_2", + "VBRK_LH12" + ], + [ + "CMT_TOP_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_LH11_2", + "VBRK_LH11" + ], + [ + "CMT_TOP_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4B3_2", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_MONITOR_P_2", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_LH4_2", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_LH5_2", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH3_2", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_MONITOR_N_2", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH10_2", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH8_2", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_LH9_2", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW2A2_2", + "VBRK_NW2A2" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "DSP_WW2END2_3", + "INT_INTERFACE_WW2END2" + ], + [ + "DSP_SE4C0_3", + "INT_INTERFACE_SE4C0" + ], + [ + "DSP_NE2A1_3", + "INT_INTERFACE_NE2A1" + ], + [ + "DSP_IMUX14_3", + "INT_INTERFACE_IMUX14" + ], + [ + "DSP_NE4C0_3", + "INT_INTERFACE_NE4C0" + ], + [ + "DSP_IMUX7_3", + "INT_INTERFACE_IMUX7" + ], + [ + "DSP_IMUX1_3", + "INT_INTERFACE_IMUX1" + ], + [ + "DSP_SW4END3_3", + "INT_INTERFACE_SW4END3" + ], + [ + "DSP_NW4END0_3", + "INT_INTERFACE_NW4END0" + ], + [ + "DSP_EE4BEG0_3", + "INT_INTERFACE_EE4BEG0" + ], + [ + "DSP_WR1END3_3", + "INT_INTERFACE_WR1END3" + ], + [ + "DSP_WL1END0_3", + "INT_INTERFACE_WL1END0" + ], + [ + "DSP_WW4C3_3", + "INT_INTERFACE_WW4C3" + ], + [ + "DSP_IMUX19_3", + "INT_INTERFACE_IMUX19" + ], + [ + "DSP_SW4A0_3", + "INT_INTERFACE_SW4A0" + ], + [ + "DSP_EE2A0_3", + "INT_INTERFACE_EE2A0" + ], + [ + "DSP_ER1BEG1_3", + "INT_INTERFACE_ER1BEG1" + ], + [ + "DSP_IMUX39_3", + "INT_INTERFACE_IMUX39" + ], + [ + "DSP_NE4BEG0_3", + "INT_INTERFACE_NE4BEG0" + ], + [ + "DSP_LH1_3", + "INT_INTERFACE_LH1" + ], + [ + "DSP_LOGIC_OUTS_B2_3", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "DSP_EL1BEG0_3", + "INT_INTERFACE_EL1BEG0" + ], + [ + "DSP_CTRL0_3", + "INT_INTERFACE_CTRL0" + ], + [ + "DSP_NE4C3_3", + "INT_INTERFACE_NE4C3" + ], + [ + "DSP_SW4A1_3", + "INT_INTERFACE_SW4A1" + ], + [ + "DSP_WW2END3_3", + "INT_INTERFACE_WW2END3" + ], + [ + "DSP_FAN4_3", + "INT_INTERFACE_FAN4" + ], + [ + "DSP_LOGIC_OUTS_B19_3", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "DSP_EL1BEG3_3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "DSP_WW2A1_3", + "INT_INTERFACE_WW2A1" + ], + [ + "DSP_SW2A3_3", + "INT_INTERFACE_SW2A3" + ], + [ + "DSP_NW4END3_3", + "INT_INTERFACE_NW4END3" + ], + [ + "DSP_EE2BEG2_3", + "INT_INTERFACE_EE2BEG2" + ], + [ + "DSP_EE4BEG2_3", + "INT_INTERFACE_EE4BEG2" + ], + [ + "DSP_EE4C0_3", + "INT_INTERFACE_EE4C0" + ], + [ + "DSP_WW4A2_3", + "INT_INTERFACE_WW4A2" + ], + [ + "DSP_WW2A3_3", + "INT_INTERFACE_WW2A3" + ], + [ + "DSP_NE2A3_3", + "INT_INTERFACE_NE2A3" + ], + [ + "DSP_LOGIC_OUTS_B14_3", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "DSP_EE4C1_3", + "INT_INTERFACE_EE4C1" + ], + [ + "DSP_SE2A2_3", + "INT_INTERFACE_SE2A2" + ], + [ + "DSP_LH8_3", + "INT_INTERFACE_LH8" + ], + [ + "DSP_NW2A2_3", + "INT_INTERFACE_NW2A2" + ], + [ + "DSP_SW4END2_3", + "INT_INTERFACE_SW4END2" + ], + [ + "DSP_IMUX23_3", + "INT_INTERFACE_IMUX23" + ], + [ + "DSP_IMUX4_3", + "INT_INTERFACE_IMUX4" + ], + [ + "DSP_IMUX6_3", + "INT_INTERFACE_IMUX6" + ], + [ + "DSP_NE4BEG1_3", + "INT_INTERFACE_NE4BEG1" + ], + [ + "DSP_FAN1_3", + "INT_INTERFACE_FAN1" + ], + [ + "DSP_LOGIC_OUTS_B22_3", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "DSP_MONITOR_N_3", + "INT_INTERFACE_MONITOR_N" + ], + [ + "DSP_NW4A2_3", + "INT_INTERFACE_NW4A2" + ], + [ + "DSP_IMUX11_3", + "INT_INTERFACE_IMUX11" + ], + [ + "DSP_ER1BEG3_3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "DSP_IMUX15_3", + "INT_INTERFACE_IMUX15" + ], + [ + "DSP_LOGIC_OUTS_B11_3", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "DSP_NW2A1_3", + "INT_INTERFACE_NW2A1" + ], + [ + "DSP_SE4BEG3_3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "DSP_SW2A2_3", + "INT_INTERFACE_SW2A2" + ], + [ + "DSP_FAN2_3", + "INT_INTERFACE_FAN2" + ], + [ + "DSP_BYP4_3", + "INT_INTERFACE_BYP4" + ], + [ + "DSP_EE2BEG0_3", + "INT_INTERFACE_EE2BEG0" + ], + [ + "DSP_WW4A3_3", + "INT_INTERFACE_WW4A3" + ], + [ + "DSP_LOGIC_OUTS_B7_3", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "DSP_LH10_3", + "INT_INTERFACE_LH10" + ], + [ + "DSP_EE4B0_3", + "INT_INTERFACE_EE4B0" + ], + [ + "DSP_BYP6_3", + "INT_INTERFACE_BYP6" + ], + [ + "DSP_NW4A1_3", + "INT_INTERFACE_NW4A1" + ], + [ + "DSP_IMUX37_3", + "INT_INTERFACE_IMUX37" + ], + [ + "DSP_NE2A0_3", + "INT_INTERFACE_NE2A0" + ], + [ + "DSP_WW4END2_3", + "INT_INTERFACE_WW4END2" + ], + [ + "DSP_LOGIC_OUTS_B20_3", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "DSP_IMUX30_3", + "INT_INTERFACE_IMUX30" + ], + [ + "DSP_EE4BEG3_3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "DSP_FAN6_3", + "INT_INTERFACE_FAN6" + ], + [ + "DSP_NE4C1_3", + "INT_INTERFACE_NE4C1" + ], + [ + "DSP_IMUX45_3", + "INT_INTERFACE_IMUX45" + ], + [ + "DSP_WW4B0_3", + "INT_INTERFACE_WW4B0" + ], + [ + "DSP_ER1BEG0_3", + "INT_INTERFACE_ER1BEG0" + ], + [ + "DSP_WW4END3_3", + "INT_INTERFACE_WW4END3" + ], + [ + "DSP_LH3_3", + "INT_INTERFACE_LH3" + ], + [ + "DSP_SE4BEG1_3", + "INT_INTERFACE_SE4BEG1" + ], + [ + "DSP_LOGIC_OUTS_B3_3", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "DSP_SE4C3_3", + "INT_INTERFACE_SE4C3" + ], + [ + "DSP_FAN3_3", + "INT_INTERFACE_FAN3" + ], + [ + "DSP_LOGIC_OUTS_B16_3", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "DSP_BYP0_3", + "INT_INTERFACE_BYP0" + ], + [ + "DSP_LH5_3", + "INT_INTERFACE_LH5" + ], + [ + "DSP_SE4C1_3", + "INT_INTERFACE_SE4C1" + ], + [ + "DSP_EE4A2_3", + "INT_INTERFACE_EE4A2" + ], + [ + "DSP_NE4C2_3", + "INT_INTERFACE_NE4C2" + ], + [ + "DSP_NW4A0_3", + "INT_INTERFACE_NW4A0" + ], + [ + "DSP_EE4C2_3", + "INT_INTERFACE_EE4C2" + ], + [ + "DSP_NW4END1_3", + "INT_INTERFACE_NW4END1" + ], + [ + "DSP_WW4B1_3", + "INT_INTERFACE_WW4B1" + ], + [ + "DSP_IMUX44_3", + "INT_INTERFACE_IMUX44" + ], + [ + "DSP_SE2A1_3", + "INT_INTERFACE_SE2A1" + ], + [ + "DSP_IMUX0_3", + "INT_INTERFACE_IMUX0" + ], + [ + "DSP_SW2A0_3", + "INT_INTERFACE_SW2A0" + ], + [ + "DSP_WW2A0_3", + "INT_INTERFACE_WW2A0" + ], + [ + "DSP_LH9_3", + "INT_INTERFACE_LH9" + ], + [ + "DSP_IMUX32_3", + "INT_INTERFACE_IMUX32" + ], + [ + "DSP_WR1END0_3", + "INT_INTERFACE_WR1END0" + ], + [ + "DSP_BYP2_3", + "INT_INTERFACE_BYP2" + ], + [ + "DSP_IMUX16_3", + "INT_INTERFACE_IMUX16" + ], + [ + "DSP_IMUX33_3", + "INT_INTERFACE_IMUX33" + ], + [ + "DSP_LH11_3", + "INT_INTERFACE_LH11" + ], + [ + "DSP_SE4BEG2_3", + "INT_INTERFACE_SE4BEG2" + ], + [ + "DSP_WW4C1_3", + "INT_INTERFACE_WW4C1" + ], + [ + "DSP_IMUX31_3", + "INT_INTERFACE_IMUX31" + ], + [ + "DSP_IMUX40_3", + "INT_INTERFACE_IMUX40" + ], + [ + "DSP_EE2BEG3_3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "DSP_IMUX46_3", + "INT_INTERFACE_IMUX46" + ], + [ + "DSP_EE4C3_3", + "INT_INTERFACE_EE4C3" + ], + [ + "DSP_IMUX35_3", + "INT_INTERFACE_IMUX35" + ], + [ + "DSP_SE4BEG0_3", + "INT_INTERFACE_SE4BEG0" + ], + [ + "DSP_CLK0_3", + "INT_INTERFACE_CLK0" + ], + [ + "DSP_EL1BEG2_3", + "INT_INTERFACE_EL1BEG2" + ], + [ + "DSP_WW4A0_3", + "INT_INTERFACE_WW4A0" + ], + [ + "DSP_WL1END3_3", + "INT_INTERFACE_WL1END3" + ], + [ + "DSP_NW4A3_3", + "INT_INTERFACE_NW4A3" + ], + [ + "DSP_WW2END1_3", + "INT_INTERFACE_WW2END1" + ], + [ + "DSP_WL1END1_3", + "INT_INTERFACE_WL1END1" + ], + [ + "DSP_SW2A1_3", + "INT_INTERFACE_SW2A1" + ], + [ + "DSP_MONITOR_P_3", + "INT_INTERFACE_MONITOR_P" + ], + [ + "DSP_BYP5_3", + "INT_INTERFACE_BYP5" + ], + [ + "DSP_IMUX12_3", + "INT_INTERFACE_IMUX12" + ], + [ + "DSP_SE2A0_3", + "INT_INTERFACE_SE2A0" + ], + [ + "DSP_IMUX2_3", + "INT_INTERFACE_IMUX2" + ], + [ + "DSP_IMUX10_3", + "INT_INTERFACE_IMUX10" + ], + [ + "DSP_WW4B3_3", + "INT_INTERFACE_WW4B3" + ], + [ + "DSP_IMUX43_3", + "INT_INTERFACE_IMUX43" + ], + [ + "DSP_BYP3_3", + "INT_INTERFACE_BYP3" + ], + [ + "DSP_LOGIC_OUTS_B18_3", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "DSP_LOGIC_OUTS_B23_3", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "DSP_SE4C2_3", + "INT_INTERFACE_SE4C2" + ], + [ + "DSP_IMUX5_3", + "INT_INTERFACE_IMUX5" + ], + [ + "DSP_IMUX36_3", + "INT_INTERFACE_IMUX36" + ], + [ + "DSP_BYP1_3", + "INT_INTERFACE_BYP1" + ], + [ + "DSP_EE2BEG1_3", + "INT_INTERFACE_EE2BEG1" + ], + [ + "DSP_EL1BEG1_3", + "INT_INTERFACE_EL1BEG1" + ], + [ + "DSP_FAN0_3", + "INT_INTERFACE_FAN0" + ], + [ + "DSP_WW4END0_3", + "INT_INTERFACE_WW4END0" + ], + [ + "DSP_NW2A3_3", + "INT_INTERFACE_NW2A3" + ], + [ + "DSP_LOGIC_OUTS_B4_3", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "DSP_LOGIC_OUTS_B6_3", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "DSP_SW4A3_3", + "INT_INTERFACE_SW4A3" + ], + [ + "DSP_WW2A2_3", + "INT_INTERFACE_WW2A2" + ], + [ + "DSP_WW4END1_3", + "INT_INTERFACE_WW4END1" + ], + [ + "DSP_LOGIC_OUTS_B8_3", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "DSP_LOGIC_OUTS_B0_3", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "DSP_IMUX28_3", + "INT_INTERFACE_IMUX28" + ], + [ + "DSP_NE4BEG2_3", + "INT_INTERFACE_NE4BEG2" + ], + [ + "DSP_LH4_3", + "INT_INTERFACE_LH4" + ], + [ + "DSP_LH2_3", + "INT_INTERFACE_LH2" + ], + [ + "DSP_LOGIC_OUTS_B21_3", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "DSP_EE2A3_3", + "INT_INTERFACE_EE2A3" + ], + [ + "DSP_IMUX3_3", + "INT_INTERFACE_IMUX3" + ], + [ + "DSP_WR1END1_3", + "INT_INTERFACE_WR1END1" + ], + [ + "DSP_IMUX26_3", + "INT_INTERFACE_IMUX26" + ], + [ + "DSP_IMUX22_3", + "INT_INTERFACE_IMUX22" + ], + [ + "DSP_SE2A3_3", + "INT_INTERFACE_SE2A3" + ], + [ + "DSP_FAN5_3", + "INT_INTERFACE_FAN5" + ], + [ + "DSP_WL1END2_3", + "INT_INTERFACE_WL1END2" + ], + [ + "DSP_CTRL1_3", + "INT_INTERFACE_CTRL1" + ], + [ + "DSP_IMUX27_3", + "INT_INTERFACE_IMUX27" + ], + [ + "DSP_LH7_3", + "INT_INTERFACE_LH7" + ], + [ + "DSP_EE4B2_3", + "INT_INTERFACE_EE4B2" + ], + [ + "DSP_EE4A3_3", + "INT_INTERFACE_EE4A3" + ], + [ + "DSP_IMUX17_3", + "INT_INTERFACE_IMUX17" + ], + [ + "DSP_EE4B3_3", + "INT_INTERFACE_EE4B3" + ], + [ + "DSP_FAN7_3", + "INT_INTERFACE_FAN7" + ], + [ + "DSP_SW4END1_3", + "INT_INTERFACE_SW4END1" + ], + [ + "DSP_SW4A2_3", + "INT_INTERFACE_SW4A2" + ], + [ + "DSP_IMUX29_3", + "INT_INTERFACE_IMUX29" + ], + [ + "DSP_CLK1_3", + "INT_INTERFACE_CLK1" + ], + [ + "DSP_LOGIC_OUTS_B1_3", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "DSP_IMUX8_3", + "INT_INTERFACE_IMUX8" + ], + [ + "DSP_NW4END2_3", + "INT_INTERFACE_NW4END2" + ], + [ + "DSP_WW4C0_3", + "INT_INTERFACE_WW4C0" + ], + [ + "DSP_LOGIC_OUTS_B10_3", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "DSP_LOGIC_OUTS_B17_3", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "DSP_WR1END2_3", + "INT_INTERFACE_WR1END2" + ], + [ + "DSP_SW4END0_3", + "INT_INTERFACE_SW4END0" + ], + [ + "DSP_EE4B1_3", + "INT_INTERFACE_EE4B1" + ], + [ + "DSP_IMUX20_3", + "INT_INTERFACE_IMUX20" + ], + [ + "DSP_IMUX21_3", + "INT_INTERFACE_IMUX21" + ], + [ + "DSP_NE2A2_3", + "INT_INTERFACE_NE2A2" + ], + [ + "DSP_IMUX42_3", + "INT_INTERFACE_IMUX42" + ], + [ + "DSP_IMUX34_3", + "INT_INTERFACE_IMUX34" + ], + [ + "DSP_LH12_3", + "INT_INTERFACE_LH12" + ], + [ + "DSP_IMUX13_3", + "INT_INTERFACE_IMUX13" + ], + [ + "DSP_WW4C2_3", + "INT_INTERFACE_WW4C2" + ], + [ + "DSP_WW4A1_3", + "INT_INTERFACE_WW4A1" + ], + [ + "DSP_EE4BEG1_3", + "INT_INTERFACE_EE4BEG1" + ], + [ + "DSP_IMUX41_3", + "INT_INTERFACE_IMUX41" + ], + [ + "DSP_ER1BEG2_3", + "INT_INTERFACE_ER1BEG2" + ], + [ + "DSP_WW2END0_3", + "INT_INTERFACE_WW2END0" + ], + [ + "DSP_IMUX24_3", + "INT_INTERFACE_IMUX24" + ], + [ + "DSP_LH6_3", + "INT_INTERFACE_LH6" + ], + [ + "DSP_IMUX25_3", + "INT_INTERFACE_IMUX25" + ], + [ + "DSP_EE4A0_3", + "INT_INTERFACE_EE4A0" + ], + [ + "DSP_EE4A1_3", + "INT_INTERFACE_EE4A1" + ], + [ + "DSP_NW2A0_3", + "INT_INTERFACE_NW2A0" + ], + [ + "DSP_IMUX47_3", + "INT_INTERFACE_IMUX47" + ], + [ + "DSP_IMUX38_3", + "INT_INTERFACE_IMUX38" + ], + [ + "DSP_IMUX18_3", + "INT_INTERFACE_IMUX18" + ], + [ + "DSP_IMUX9_3", + "INT_INTERFACE_IMUX9" + ], + [ + "DSP_NE4BEG3_3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "DSP_BYP7_3", + "INT_INTERFACE_BYP7" + ], + [ + "DSP_EE2A2_3", + "INT_INTERFACE_EE2A2" + ], + [ + "DSP_WW4B2_3", + "INT_INTERFACE_WW4B2" + ], + [ + "DSP_LOGIC_OUTS_B5_3", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "DSP_EE2A1_3", + "INT_INTERFACE_EE2A1" + ], + [ + "DSP_LOGIC_OUTS_B15_3", + "INT_INTERFACE_LOGIC_OUTS_B15" + ] + ], + "tile_types": [ + "DSP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX32", + "BRAM_IMUX32_UTURN_2" + ], + [ + "INT_INTERFACE_FAN7", + "BRAM_FAN7_2" + ], + [ + "INT_INTERFACE_WW4B0", + "BRAM_WW4B0_2" + ], + [ + "INT_INTERFACE_SW4A0", + "BRAM_SW4A0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX45", + "BRAM_IMUX45_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_2" + ], + [ + "INT_INTERFACE_WR1END0", + "BRAM_WR1END0_2" + ], + [ + "INT_INTERFACE_EE4BEG3", + "BRAM_EE4BEG3_2" + ], + [ + "INT_INTERFACE_LH9", + "BRAM_LH9_2" + ], + [ + "INT_INTERFACE_WR1END3", + "BRAM_WR1END3_2" + ], + [ + "INT_INTERFACE_WW2END0", + "BRAM_WW2END0_2" + ], + [ + "INT_INTERFACE_SW4A2", + "BRAM_SW4A2_2" + ], + [ + "INT_INTERFACE_EE2A3", + "BRAM_EE2A3_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B13", + "BRAM_LOGIC_OUTS_B13_2" + ], + [ + "INT_INTERFACE_SW2A1", + "BRAM_SW2A1_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX11", + "BRAM_IMUX11_UTURN_2" + ], + [ + "INT_INTERFACE_WW4C1", + "BRAM_WW4C1_2" + ], + [ + "INT_INTERFACE_NE4C3", + "BRAM_NE4C3_2" + ], + [ + "INT_INTERFACE_WW2END1", + "BRAM_WW2END1_2" + ], + [ + "INT_INTERFACE_SE4C2", + "BRAM_SE4C2_2" + ], + [ + "INT_INTERFACE_SW4END3", + "BRAM_SW4END3_2" + ], + [ + "INT_INTERFACE_EE4A1", + "BRAM_EE4A1_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_2" + ], + [ + "INT_INTERFACE_WR1END2", + "BRAM_WR1END2_2" + ], + [ + "INT_INTERFACE_BYP3", + "BRAM_BYP3_2" + ], + [ + "INT_INTERFACE_BYP7", + "BRAM_BYP7_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX23", + "BRAM_IMUX23_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX15", + "BRAM_IMUX15_UTURN_2" + ], + [ + "INT_INTERFACE_CLK1", + "BRAM_CLK1_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B4", + "BRAM_LOGIC_OUTS_B4_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B20", + "BRAM_LOGIC_OUTS_B20_2" + ], + [ + "INT_INTERFACE_WW4B3", + "BRAM_WW4B3_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B12", + "BRAM_LOGIC_OUTS_B12_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B16", + "BRAM_LOGIC_OUTS_B16_2" + ], + [ + "INT_INTERFACE_EE4B1", + "BRAM_EE4B1_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX27", + "BRAM_IMUX27_2" + ], + [ + "INT_INTERFACE_FAN3", + "BRAM_FAN3_2" + ], + [ + "INT_INTERFACE_ER1BEG0", + "BRAM_ER1BEG0_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B21", + "BRAM_LOGIC_OUTS_B21_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX43", + "BRAM_IMUX43_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX40", + "BRAM_IMUX40_2" + ], + [ + "INT_INTERFACE_EE4C0", + "BRAM_EE4C0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_2" + ], + [ + "INT_INTERFACE_MONITOR_N", + "BRAM_MONITOR_N_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_2" + ], + [ + "INT_INTERFACE_SE2A0", + "BRAM_SE2A0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_2" + ], + [ + "INT_INTERFACE_EL1BEG0", + "BRAM_EL1BEG0_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B17", + "BRAM_LOGIC_OUTS_B17_2" + ], + [ + "INT_INTERFACE_NE4BEG3", + "BRAM_NE4BEG3_2" + ], + [ + "INT_INTERFACE_CLK0", + "BRAM_CLK0_2" + ], + [ + "INT_INTERFACE_SE2A1", + "BRAM_SE2A1_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX30", + "BRAM_IMUX30_2" + ], + [ + "INT_INTERFACE_MONITOR_P", + "BRAM_MONITOR_P_2" + ], + [ + "INT_INTERFACE_CTRL1", + "BRAM_CTRL1_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_2" + ], + [ + "INT_INTERFACE_EL1BEG2", + "BRAM_EL1BEG2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX22", + "BRAM_IMUX22_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX7", + "BRAM_IMUX7_UTURN_2" + ], + [ + "INT_INTERFACE_FAN1", + "BRAM_FAN1_2" + ], + [ + "INT_INTERFACE_ER1BEG1", + "BRAM_ER1BEG1_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX21", + "BRAM_IMUX21_2" + ], + [ + "INT_INTERFACE_WW4A0", + "BRAM_WW4A0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX35", + "BRAM_IMUX35_2" + ], + [ + "INT_INTERFACE_BYP2", + "BRAM_BYP2_2" + ], + [ + "INT_INTERFACE_NW4A0", + "BRAM_NW4A0_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B18", + "BRAM_LOGIC_OUTS_B18_2" + ], + [ + "INT_INTERFACE_WW4A1", + "BRAM_WW4A1_2" + ], + [ + "INT_INTERFACE_SW4A3", + "BRAM_SW4A3_2" + ], + [ + "INT_INTERFACE_SE4BEG1", + "BRAM_SE4BEG1_2" + ], + [ + "INT_INTERFACE_WW4C3", + "BRAM_WW4C3_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX12", + "BRAM_IMUX12_UTURN_2" + ], + [ + "INT_INTERFACE_ER1BEG2", + "BRAM_ER1BEG2_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX31", + "BRAM_IMUX31_2" + ], + [ + "INT_INTERFACE_FAN5", + "BRAM_FAN5_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX28", + "BRAM_IMUX28_UTURN_2" + ], + [ + "INT_INTERFACE_WW4B2", + "BRAM_WW4B2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX26", + "BRAM_IMUX26_UTURN_2" + ], + [ + "INT_INTERFACE_WW2END2", + "BRAM_WW2END2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B9", + "BRAM_LOGIC_OUTS_B9_2" + ], + [ + "INT_INTERFACE_WL1END2", + "BRAM_WL1END2_2" + ], + [ + "INT_INTERFACE_NE4BEG0", + "BRAM_NE4BEG0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX13", + "BRAM_IMUX13_UTURN_2" + ], + [ + "INT_INTERFACE_NE2A3", + "BRAM_NE2A3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX33", + "BRAM_IMUX33_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX29", + "BRAM_IMUX29_UTURN_2" + ], + [ + "INT_INTERFACE_EE2BEG0", + "BRAM_EE2BEG0_2" + ], + [ + "INT_INTERFACE_SE4C3", + "BRAM_SE4C3_2" + ], + [ + "INT_INTERFACE_SW2A0", + "BRAM_SW2A0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX47", + "BRAM_IMUX47_2" + ], + [ + "INT_INTERFACE_NW4A2", + "BRAM_NW4A2_2" + ], + [ + "INT_INTERFACE_EE2A0", + "BRAM_EE2A0_2" + ], + [ + "INT_INTERFACE_LH10", + "BRAM_LH10_2" + ], + [ + "INT_INTERFACE_LH2", + "BRAM_LH2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B23", + "BRAM_LOGIC_OUTS_B23_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX34", + "BRAM_IMUX34_UTURN_2" + ], + [ + "INT_INTERFACE_EE2A1", + "BRAM_EE2A1_2" + ], + [ + "INT_INTERFACE_SE4C0", + "BRAM_SE4C0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX36", + "BRAM_IMUX36_UTURN_2" + ], + [ + "INT_INTERFACE_NW4END1", + "BRAM_NW4END1_2" + ], + [ + "INT_INTERFACE_EE4A3", + "BRAM_EE4A3_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B19", + "BRAM_LOGIC_OUTS_B19_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX29", + "BRAM_IMUX29_2" + ], + [ + "INT_INTERFACE_NW4A3", + "BRAM_NW4A3_2" + ], + [ + "INT_INTERFACE_LH1", + "BRAM_LH1_2" + ], + [ + "INT_INTERFACE_EE4C1", + "BRAM_EE4C1_2" + ], + [ + "INT_INTERFACE_BYP1", + "BRAM_BYP1_2" + ], + [ + "INT_INTERFACE_NE2A1", + "BRAM_NE2A1_2" + ], + [ + "INT_INTERFACE_SW4END1", + "BRAM_SW4END1_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B3", + "BRAM_LOGIC_OUTS_B3_2" + ], + [ + "INT_INTERFACE_WW2A1", + "BRAM_WW2A1_2" + ], + [ + "INT_INTERFACE_NE4C0", + "BRAM_NE4C0_2" + ], + [ + "INT_INTERFACE_SE4BEG3", + "BRAM_SE4BEG3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_2" + ], + [ + "INT_INTERFACE_NE2A2", + "BRAM_NE2A2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX37", + "BRAM_IMUX37_UTURN_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B22", + "BRAM_LOGIC_OUTS_B22_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX45", + "BRAM_IMUX45_UTURN_2" + ], + [ + "INT_INTERFACE_BYP5", + "BRAM_BYP5_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX28", + "BRAM_IMUX28_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX36", + "BRAM_IMUX36_2" + ], + [ + "INT_INTERFACE_LH12", + "BRAM_LH12_2" + ], + [ + "INT_INTERFACE_EL1BEG3", + "BRAM_EL1BEG3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX25", + "BRAM_IMUX25_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX9", + "BRAM_IMUX9_UTURN_2" + ], + [ + "INT_INTERFACE_SW2A2", + "BRAM_SW2A2_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_2" + ], + [ + "INT_INTERFACE_SE4BEG2", + "BRAM_SE4BEG2_2" + ], + [ + "INT_INTERFACE_SW2A3", + "BRAM_SW2A3_2" + ], + [ + "INT_INTERFACE_NW2A1", + "BRAM_NW2A1_2" + ], + [ + "INT_INTERFACE_SE4BEG0", + "BRAM_SE4BEG0_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B2", + "BRAM_LOGIC_OUTS_B2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B1", + "BRAM_LOGIC_OUTS_B1_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX2", + "BRAM_IMUX2_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX8", + "BRAM_IMUX8_UTURN_2" + ], + [ + "INT_INTERFACE_SW4END0", + "BRAM_SW4END0_2" + ], + [ + "INT_INTERFACE_NE4C1", + "BRAM_NE4C1_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX18", + "BRAM_IMUX18_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX42", + "BRAM_IMUX42_2" + ], + [ + "INT_INTERFACE_EE4B3", + "BRAM_EE4B3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX34", + "BRAM_IMUX34_2" + ], + [ + "INT_INTERFACE_LH4", + "BRAM_LH4_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX24", + "BRAM_IMUX24_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX1", + "BRAM_IMUX1_UTURN_2" + ], + [ + "INT_INTERFACE_EE4B0", + "BRAM_EE4B0_2" + ], + [ + "INT_INTERFACE_EE2BEG1", + "BRAM_EE2BEG1_2" + ], + [ + "INT_INTERFACE_BYP0", + "BRAM_BYP0_2" + ], + [ + "INT_INTERFACE_SE4C1", + "BRAM_SE4C1_2" + ], + [ + "INT_INTERFACE_NW2A3", + "BRAM_NW2A3_2" + ], + [ + "INT_INTERFACE_EE4A2", + "BRAM_EE4A2_2" + ], + [ + "INT_INTERFACE_NW2A0", + "BRAM_NW2A0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX30", + "BRAM_IMUX30_UTURN_2" + ], + [ + "INT_INTERFACE_EE2BEG2", + "BRAM_EE2BEG2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX6", + "BRAM_IMUX6_UTURN_2" + ], + [ + "INT_INTERFACE_NW4A1", + "BRAM_NW4A1_2" + ], + [ + "INT_INTERFACE_WW4C0", + "BRAM_WW4C0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX26", + "BRAM_IMUX26_2" + ], + [ + "INT_INTERFACE_NE4BEG2", + "BRAM_NE4BEG2_2" + ], + [ + "INT_INTERFACE_WW2A3", + "BRAM_WW2A3_2" + ], + [ + "INT_INTERFACE_FAN6", + "BRAM_FAN6_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX23", + "BRAM_IMUX23_UTURN_2" + ], + [ + "INT_INTERFACE_EE4C2", + "BRAM_EE4C2_2" + ], + [ + "INT_INTERFACE_NE4BEG1", + "BRAM_NE4BEG1_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX35", + "BRAM_IMUX35_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX40", + "BRAM_IMUX40_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX25", + "BRAM_IMUX25_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX5", + "BRAM_IMUX5_UTURN_2" + ], + [ + "INT_INTERFACE_NW4END2", + "BRAM_NW4END2_2" + ], + [ + "INT_INTERFACE_WL1END0", + "BRAM_WL1END0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX19", + "BRAM_IMUX19_UTURN_2" + ], + [ + "INT_INTERFACE_EE4BEG1", + "BRAM_EE4BEG1_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B6", + "BRAM_LOGIC_OUTS_B6_2" + ], + [ + "INT_INTERFACE_FAN2", + "BRAM_FAN2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B5", + "BRAM_LOGIC_OUTS_B5_2" + ], + [ + "INT_INTERFACE_SW4A1", + "BRAM_SW4A1_2" + ], + [ + "INT_INTERFACE_WW4END1", + "BRAM_WW4END1_2" + ], + [ + "INT_INTERFACE_LH6", + "BRAM_LH6_2" + ], + [ + "INT_INTERFACE_WW4END0", + "BRAM_WW4END0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX37", + "BRAM_IMUX37_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX21", + "BRAM_IMUX21_UTURN_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B7", + "BRAM_LOGIC_OUTS_B7_2" + ], + [ + "INT_INTERFACE_BYP4", + "BRAM_BYP4_2" + ], + [ + "INT_INTERFACE_SE2A3", + "BRAM_SE2A3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_2" + ], + [ + "INT_INTERFACE_EE4A0", + "BRAM_EE4A0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_2" + ], + [ + "INT_INTERFACE_FAN4", + "BRAM_FAN4_2" + ], + [ + "INT_INTERFACE_WW2END3", + "BRAM_WW2END3_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX39", + "BRAM_IMUX39_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX46", + "BRAM_IMUX46_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX39", + "BRAM_IMUX39_2" + ], + [ + "INT_INTERFACE_NE2A0", + "BRAM_NE2A0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX0", + "BRAM_IMUX0_UTURN_2" + ], + [ + "INT_INTERFACE_EE4B2", + "BRAM_EE4B2_2" + ], + [ + "INT_INTERFACE_LH11", + "BRAM_LH11_2" + ], + [ + "INT_INTERFACE_EE4BEG2", + "BRAM_EE4BEG2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B14", + "BRAM_LOGIC_OUTS_B14_2" + ], + [ + "INT_INTERFACE_WL1END1", + "BRAM_WL1END1_2" + ], + [ + "INT_INTERFACE_ER1BEG3", + "BRAM_ER1BEG3_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX27", + "BRAM_IMUX27_UTURN_2" + ], + [ + "INT_INTERFACE_NE4C2", + "BRAM_NE4C2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B10", + "BRAM_LOGIC_OUTS_B10_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_2" + ], + [ + "INT_INTERFACE_WW4A2", + "BRAM_WW4A2_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX38", + "BRAM_IMUX38_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_2" + ], + [ + "INT_INTERFACE_BYP6", + "BRAM_BYP6_2" + ], + [ + "INT_INTERFACE_EE4C3", + "BRAM_EE4C3_2" + ], + [ + "INT_INTERFACE_SE2A2", + "BRAM_SE2A2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B15", + "BRAM_LOGIC_OUTS_B15_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX44", + "BRAM_IMUX44_2" + ], + [ + "INT_INTERFACE_LH5", + "BRAM_LH5_2" + ], + [ + "INT_INTERFACE_WW4END3", + "BRAM_WW4END3_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX17", + "BRAM_IMUX17_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX47", + "BRAM_IMUX47_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX41", + "BRAM_IMUX41_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX32", + "BRAM_IMUX32_2" + ], + [ + "INT_INTERFACE_EE2BEG3", + "BRAM_EE2BEG3_2" + ], + [ + "INT_INTERFACE_WW4C2", + "BRAM_WW4C2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX3", + "BRAM_IMUX3_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX38", + "BRAM_IMUX38_UTURN_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B0", + "BRAM_LOGIC_OUTS_B0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX14", + "BRAM_IMUX14_UTURN_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B11", + "BRAM_LOGIC_OUTS_B11_2" + ], + [ + "INT_INTERFACE_FAN0", + "BRAM_FAN0_2" + ], + [ + "INT_INTERFACE_WL1END3", + "BRAM_WL1END3_2" + ], + [ + "INT_INTERFACE_WW2A2", + "BRAM_WW2A2_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX22", + "BRAM_IMUX22_2" + ], + [ + "INT_INTERFACE_SW4END2", + "BRAM_SW4END2_2" + ], + [ + "INT_INTERFACE_WW4A3", + "BRAM_WW4A3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX24", + "BRAM_IMUX24_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX31", + "BRAM_IMUX31_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX43", + "BRAM_IMUX43_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX46", + "BRAM_IMUX46_UTURN_2" + ], + [ + "INT_INTERFACE_CTRL0", + "BRAM_CTRL0_2" + ], + [ + "INT_INTERFACE_WW4B1", + "BRAM_WW4B1_2" + ], + [ + "INT_INTERFACE_NW2A2", + "BRAM_NW2A2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX16", + "BRAM_IMUX16_UTURN_2" + ], + [ + "INT_INTERFACE_LH3", + "BRAM_LH3_2" + ], + [ + "INT_INTERFACE_LH8", + "BRAM_LH8_2" + ], + [ + "INT_INTERFACE_EE4BEG0", + "BRAM_EE4BEG0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX10", + "BRAM_IMUX10_UTURN_2" + ], + [ + "INT_INTERFACE_EE2A2", + "BRAM_EE2A2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX42", + "BRAM_IMUX42_UTURN_2" + ], + [ + "INT_INTERFACE_WR1END1", + "BRAM_WR1END1_2" + ], + [ + "INT_INTERFACE_WW4END2", + "BRAM_WW4END2_2" + ], + [ + "INT_INTERFACE_WW2A0", + "BRAM_WW2A0_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B8", + "BRAM_LOGIC_OUTS_B8_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX44", + "BRAM_IMUX44_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX41", + "BRAM_IMUX41_UTURN_2" + ], + [ + "INT_INTERFACE_NW4END0", + "BRAM_NW4END0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX20", + "BRAM_IMUX20_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX4", + "BRAM_IMUX4_UTURN_2" + ], + [ + "INT_INTERFACE_EL1BEG1", + "BRAM_EL1BEG1_2" + ], + [ + "INT_INTERFACE_LH7", + "BRAM_LH7_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX33", + "BRAM_IMUX33_2" + ], + [ + "INT_INTERFACE_NW4END3", + "BRAM_NW4END3_2" + ] + ], + "tile_types": [ + "BRAM_INT_INTERFACE_R", + "BRAM_R" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW2END1_5", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE2A0_5", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_SW2A1_5", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_SW2A2_5", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_SE2A1_5", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW4B0_5", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_NW4END3_5", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW2END3_5", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_NW2A2_5", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_WL1END1_5", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_EE4C1_5", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_WW2A2_5", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_LH8_5", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW4END3_5", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_SE4BEG2_5", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_SW4END2_5", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SW4END1_5", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_WR1END2_5", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_EE4BEG1_5", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_WW4C3_5", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4B1_5", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_NW2A3_5", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE2A2_5", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_WR1END0_5", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH4_5", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_NW4A2_5", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WL1END3_5", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE2A2_5", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WW4B3_5", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SE4C1_5", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_NW4END0_5", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SW4A0_5", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WW4END2_5", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_LH2_5", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NE4C0_5", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_EE2A1_5", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_NE2A1_5", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_LH10_5", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_EE4BEG2_5", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WL1END0_5", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_LH6_5", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WW4C0_5", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_ER1BEG0_5", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NE4BEG1_5", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_NE4BEG0_5", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NW2A1_5", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C2_5", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW4A0_5", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_NW4END1_5", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NE4C2_5", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE4BEG0_5", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WL1END2_5", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SW2A0_5", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_SE4C0_5", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_EE4B3_5", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_EE4A3_5", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_WW2END0_5", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WW4A0_5", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SE4BEG0_5", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SW4END0_5", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WW4A2_5", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_NE2A3_5", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_EE4B0_5", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH5_5", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE4B2_5", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_NE4C1_5", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW4A3_5", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_WR1END1_5", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_NW4A3_5", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_EE4A0_5", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_SE4C2_5", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_EL1BEG0_5", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_LH7_5", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_LH12_5", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW4END1_5", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE2BEG3_5", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_LH1_5", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_NW4END2_5", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_NE4BEG3_5", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW4C2_5", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_WW4END0_5", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WR1END3_5", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_SW4A3_5", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE2A3_5", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NW2A0_5", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_LH11_5", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EL1BEG2_5", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_SE2A0_5", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE4A1_5", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_SE4BEG3_5", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_SW2A3_5", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_ER1BEG2_5", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_WW2A0_5", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_EE2BEG0_5", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_ER1BEG3_5", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW4B2_5", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_LH9_5", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_SW4A2_5", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NE4C3_5", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_EE4C3_5", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_SE4C3_5", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WW4C1_5", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_EE2BEG1_5", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_EE2BEG2_5", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW2A1_5", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_NW4A1_5", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SE2A2_5", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4A2_5", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4B1_5", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_LH3_5", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_WW2A3_5", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_ER1BEG1_5", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WW4A1_5", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EL1BEG3_5", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_NE2A0_5", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EL1BEG1_5", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SW4END3_5", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NE4BEG2_5", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EE4C0_5", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EE4BEG3_5", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_SE4BEG1_5", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SW4A1_5", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_SE2A3_5", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_WW2END2_5", + "INT_FEEDTHRU_2_WW2END2" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + -7 + ], + "wire_pairs": [ + [ + "CMT_TOP_ER1BEG2_12", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WR1END0_12", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4C0_12", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WW4END0_12", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_LH10_12", + "VBRK_LH10" + ], + [ + "CMT_TOP_NE4BEG2_12", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_NW4END3_12", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4BEG3_12", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH1_12", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A1_12", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SE4BEG1_12", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NE4BEG1_12", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_NW4A3_12", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE2BEG3_12", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WL1END2_12", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE2BEG2_12", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW4B2_12", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EL1BEG1_12", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SW4END1_12", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_WW4C0_12", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SW2A2_12", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4B0_12", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE4C2_12", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_LH2_12", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4B1_12", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4C3_12", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE4C0_12", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_LH7_12", + "VBRK_LH7" + ], + [ + "CMT_TOP_NE2A0_12", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4A0_12", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WR1END2_12", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW4END1_12", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4BEG3_12", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW2A1_12", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4END2_12", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_SE2A0_12", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW4A1_12", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SE4C1_12", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE2A1_12", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4B1_12", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_EE4C3_12", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4BEG1_12", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_12", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_WR1END3_12", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE2BEG0_12", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EL1BEG2_12", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4A1_12", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW4C2_12", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_LH3_12", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4A2_12", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NE2A3_12", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW2END2_12", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_ER1BEG0_12", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END3_12", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EL1BEG0_12", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_WW2END0_12", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2END1_12", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW2A2_12", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_WL1END3_12", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_EE4BEG2_12", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW4END2_12", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE4C2_12", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4A2_12", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG0_12", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4END3_12", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NW2A2_12", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A3_12", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_SW4A0_12", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_LH11_12", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH4_12", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2A0_12", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SW2A3_12", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4A0_12", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EL1BEG3_12", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE4B3_12", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4A1_12", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_LH5_12", + "VBRK_LH5" + ], + [ + "CMT_TOP_NW2A3_12", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C3_12", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_NE4C2_12", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SW2A1_12", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH9_12", + "VBRK_LH9" + ], + [ + "CMT_TOP_NW2A0_12", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_EE2A3_12", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW2A0_12", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4BEG3_12", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EE4B2_12", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_NW4END1_12", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A1_12", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NE4C3_12", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_ER1BEG1_12", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2A2_12", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WR1END1_12", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A2_12", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2BEG1_12", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SE2A2_12", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_NE4C1_12", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH12_12", + "VBRK_LH12" + ], + [ + "CMT_TOP_SW4END0_12", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WL1END1_12", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_ER1BEG3_12", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4A3_12", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_WW4B3_12", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4C1_12", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2A3_12", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_LH6_12", + "VBRK_LH6" + ], + [ + "CMT_TOP_LH8_12", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A3_12", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_SE2A1_12", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4A2_12", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4B0_12", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_NW4A0_12", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_SW4END2_12", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE2A1_12", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_WW2END3_12", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EE4C1_12", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SE2A3_12", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG0_12", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE4BEG2_12", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW4A2_12", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NE4C0_12", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WL1END0_12", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_WW2A0_12", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END0_12", + "VBRK_NW4END0" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 9 + ], + "wire_pairs": [ + [ + "MMCM_CLK_FREQ_BB_REBUF3_NS", + "TERM_CMT_FREQ_REF_NS3" + ], + [ + "MMCM_CLK_FREQ_BB_REBUF0_NS", + "TERM_CMT_FREQ_REF_NS0" + ], + [ + "MMCM_CLK_FREQ_BB_REBUF1_NS", + "TERM_CMT_FREQ_REF_NS1" + ], + [ + "MMCM_CLK_FREQ_BB_REBUF2_NS", + "TERM_CMT_FREQ_REF_NS2" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "TERM_CMT" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "CLK_HROW_EL1BEG3_7", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_WW2A1_7", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_SE4C3_7", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_WW4END3_7", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_EE4C0_7", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_SW4A2_7", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_NE2A3_7", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_CLK1_7", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_BYP6_7", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_WW4B0_7", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_IMUX38_7", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_ER1BEG0_7", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_IMUX4_7", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_WL1END2_7", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_WW2A0_7", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_IMUX1_7", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_WW4A2_7", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_SE2A1_7", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_NW4END1_7", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_EE4C2_7", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_SE4BEG0_7", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_CTRL1_7", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_WW2END0_7", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_IMUX13_7", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_SE2A3_7", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_IMUX22_7", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_NE4BEG1_7", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_SW4A1_7", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_SW2A0_7", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE2A0_7", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_IMUX24_7", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_WW4END2_7", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_IMUX36_7", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_WW4C3_7", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_EL1BEG1_7", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_WW4B1_7", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_EE4B3_7", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_IMUX44_7", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_CTRL0_7", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_LH10_7", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_IMUX7_7", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_EE2BEG1_7", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_NW4A1_7", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_IMUX2_7", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_ER1BEG3_7", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_FAN3_7", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_WW2END2_7", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_WW4C2_7", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_EE2A3_7", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_IMUX5_7", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_IMUX15_7", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_IMUX34_7", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_EL1BEG0_7", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_EE2BEG3_7", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_SW4A0_7", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_IMUX18_7", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_NW4A3_7", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_IMUX6_7", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_WR1END2_7", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_IMUX40_7", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_SW2A1_7", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_EE2A2_7", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_WW4C0_7", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_EE4A3_7", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_IMUX30_7", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_IMUX47_7", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_SW4END2_7", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_IMUX42_7", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_IMUX29_7", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_BYP7_7", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_FAN7_7", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_IMUX28_7", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_NW2A2_7", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_WW2END1_7", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_BYP2_7", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_IMUX9_7", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_LH9_7", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_IMUX3_7", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_IMUX21_7", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_NW4A0_7", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_IMUX23_7", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_WW4C1_7", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_IMUX32_7", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_FAN2_7", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_SE4BEG3_7", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_SE4BEG1_7", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_LH4_7", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_NE4BEG0_7", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_NE4BEG2_7", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_NE2A2_7", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_WW2END3_7", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_IMUX35_7", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_FAN0_7", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_WW4A1_7", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_IMUX8_7", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_NE2A0_7", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_LH3_7", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_IMUX31_7", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_NW4END2_7", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_NW4END3_7", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_EE4BEG3_7", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_SW2A2_7", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_IMUX20_7", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_SW4END1_7", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_ER1BEG1_7", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_WW4END1_7", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_FAN6_7", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_SE4C0_7", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_LH6_7", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_EE4B0_7", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_NW4END0_7", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_SE2A2_7", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_EE4C1_7", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_IMUX43_7", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_BYP5_7", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_IMUX37_7", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_FAN4_7", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_NE4C0_7", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_CLK0_7", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_WW4B2_7", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_SW4END3_7", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_WW4A0_7", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_WW4END0_7", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_IMUX25_7", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_NE4C2_7", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_IMUX33_7", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_WR1END0_7", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_SW2A3_7", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_SE2A0_7", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_SE4C1_7", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_IMUX0_7", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_FAN5_7", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_SE4C2_7", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_IMUX11_7", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_SW4A3_7", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_EE4A0_7", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_LH1_7", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_BYP3_7", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_IMUX19_7", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_EE4C3_7", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_LH7_7", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_IMUX39_7", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_NE4C3_7", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_EE2BEG0_7", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_WL1END1_7", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_EE2A1_7", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_WL1END3_7", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_SE4BEG2_7", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_IMUX16_7", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_WR1END3_7", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_IMUX45_7", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_NW4A2_7", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_EE4BEG1_7", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_EE4B2_7", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_EE4BEG2_7", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_EE4A2_7", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_NW2A3_7", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_WW4B3_7", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_IMUX17_7", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_IMUX26_7", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_WW2A3_7", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_WW2A2_7", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_BYP4_7", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_EE4BEG0_7", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_NE2A1_7", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_EE2BEG2_7", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_EE4B1_7", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_LH11_7", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_IMUX27_7", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_NE4C1_7", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_LH8_7", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_BYP1_7", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_EL1BEG2_7", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_ER1BEG2_7", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_LH5_7", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_WR1END1_7", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_NW2A1_7", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_IMUX14_7", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_IMUX10_7", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_BYP0_7", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_IMUX12_7", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_FAN1_7", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_WW4A3_7", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_IMUX46_7", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_NE4BEG3_7", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_NW2A0_7", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_IMUX41_7", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_EE4A1_7", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_LH12_7", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_WL1END0_7", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_SW4END0_7", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_LH2_7", + "INT_INTERFACE_LH2" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + -13 + ], + "wire_pairs": [ + [ + "CMT_R_TOP_UPPER_B_CLKPLL1", + "CMT_TOP_R_UPPER_T_CLKPLL1" + ], + [ + "CMT_PHASER_UP_PHASERREF_ABOVE1", + "CMT_PLL_PHASERREF_ABOVE1" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL2", + "CMT_TOP_R_UPPER_T_CLKPLL2" + ], + [ + "CMT_PHASER_OUT_D_OCLK", + "CMT_PLL_PHASER_OUT_D_OCLK" + ], + [ + "CMT_PHASERD_DTSBUS0", + "CMT_PLL_PHASERD_DTSBUS0" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL0", + "CMT_TOP_R_UPPER_T_CLKPLL0" + ], + [ + "CMT_PHASER_UP_PHASERREF0", + "CMT_PLL_PHASERREF0" + ], + [ + "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "PLLOUT_CLK_FREQ_BB_2" + ], + [ + "CMT_PHASER_OUT_D_RDENABLE_TOFIFO", + "CMT_PLL_PHASER_RDENABLE_TOFIFO" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT3", + "PLL_CLK_FREQ_BB3_NS" + ], + [ + "CMT_R_TOP_UPPER_B_CLKFBIN", + "CMT_TOP_R_UPPER_T_CLKFBIN" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT1", + "PLL_CLK_FREQ_BB1_NS" + ], + [ + "CMT_PHASER_IN_D_ICLKDIV", + "CMT_PLL_PHASER_IN_D_ICLKDIV" + ], + [ + "CMT_PHASERD_CTSBUS0", + "CMT_PLL_PHASERD_CTSBUS0" + ], + [ + "CMT_PHASER_OUT_D_OCLKDIV", + "CMT_PLL_PHASER_OUT_D_OCLKDIV" + ], + [ + "CMT_PHASER_UP_PHASERREF1", + "CMT_PLL_PHASERREF1" + ], + [ + "CMT_PHASER_OUT_D_RDCLK_TOFIFO", + "CMT_PLL_PHASER_RDCLK_TOFIFO" + ], + [ + "CMT_PHASERD_DTSBUS1", + "CMT_PLL_PHASERD_DTSBUS1" + ], + [ + "CMT_PHASER_IN_D_WRCLK_TOFIFO", + "CMT_PLL_PHASER_WRCLK_TOFIFO" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL5", + "CMT_TOP_R_UPPER_T_CLKPLL5" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL4", + "CMT_TOP_R_UPPER_T_CLKPLL4" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL6", + "CMT_TOP_R_UPPER_T_CLKPLL6" + ], + [ + "CMT_PHASERD_DQSBUS0", + "CMT_PLL_PHASERD_DQSBUS0" + ], + [ + "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "PLLOUT_CLK_FREQ_BB_0" + ], + [ + "CMT_PHASER_UP_PHASERREF_ABOVE0", + "CMT_PLL_PHASERREF_ABOVE0" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT2", + "PLL_CLK_FREQ_BB2_NS" + ], + [ + "CMT_PHASER_IN_D_ICLK", + "CMT_PLL_PHASER_IN_D_ICLK" + ], + [ + "CMT_PHASER_TOP_SYNC_BB", + "CMT_PLL_PHYCTRL_SYNC_BB_DN" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT0", + "PLL_CLK_FREQ_BB0_NS" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL7", + "CMT_TOP_R_UPPER_T_CLKPLL7" + ], + [ + "CMT_PHASER_OUT_D_OCLK1X_90", + "CMT_PLL_PHASER_OUT_D_OCLK1X_90" + ], + [ + "CMT_R_TOP_UPPER_B_CLKIN2", + "CMT_TOP_R_UPPER_T_CLKIN2" + ], + [ + "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "PLLOUT_CLK_FREQ_BB_3" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL3", + "CMT_TOP_R_UPPER_T_CLKPLL3" + ], + [ + "CMT_R_TOP_UPPER_B_CLKIN1", + "CMT_TOP_R_UPPER_T_CLKIN1" + ], + [ + "CMT_PHASERD_DQSBUS1", + "CMT_PLL_PHASERD_DQSBUS1" + ], + [ + "CMT_PHASER_UP_PHASERREF_BELOW1", + "CMT_PLL_PHASERREF_BELOW1" + ], + [ + "CMT_PHASER_IN_D_WRENABLE_FIFO", + "CMT_PLL_PHASER_WRENABLE_TOFIFO" + ], + [ + "CMT_PHASERD_CTSBUS1", + "CMT_PLL_PHASERD_CTSBUS1" + ], + [ + "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "PLLOUT_CLK_FREQ_BB_1" + ], + [ + "CMT_PHASER_UP_PHASERREF_BELOW0", + "CMT_PLL_PHASERREF_BELOW0" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "CMT_TOP_R_UPPER_T" + ] + }, + { + "grid_deltas": [ + 1, + 3 + ], + "wire_pairs": [ + [ + "CMT_TOP_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH1_2", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH2_2", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_LH6_2", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH7_2", + "VBRK_LH7" + ], + [ + "CMT_TOP_LH12_2", + "VBRK_LH12" + ], + [ + "CMT_TOP_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_LH11_2", + "VBRK_LH11" + ], + [ + "CMT_TOP_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4B3_2", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_MONITOR_P_2", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_LH4_2", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_LH5_2", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH3_2", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_MONITOR_N_2", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH10_2", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH8_2", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_LH9_2", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW2A2_2", + "VBRK_NW2A2" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH12_0", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH9_0", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH1_0", + "VBRK_LH1" + ], + [ + "CMT_TOP_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH8_0", + "VBRK_LH8" + ], + [ + "CMT_TOP_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH5_0", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH4_0", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH3_0", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_LH10_0", + "VBRK_LH10" + ], + [ + "CMT_TOP_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH11_0", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH7_0", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH2_0", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH6_0", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SW4A1_0", + "VBRK_SW4A1" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -5 + ], + "wire_pairs": [ + [ + "BRAM_CASCINTOP_ADDRARDADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" + ], + [ + "BRAM_FIFO36_CASCADEOUTB_1", + "BRKH_BRAM_CASCADEB_R" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" + ], + [ + "BRAM_FIFO36_CASCADEOUTA_1", + "BRKH_BRAM_CASCADEA_R" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7" + ] + ], + "tile_types": [ + "BRAM_R", + "BRKH_BRAM" + ] + }, + { + "grid_deltas": [ + -1, + 10 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SW4A0_0", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EL1BEG1_0", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_EE4A3_0", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE4C1_0", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_NW2A2_0", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_SE4BEG2_0", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW4C2_0", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_EE4B3_0", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SW4A3_0", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_NE4C2_0", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_ER1BEG1_0", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_EE2A2_0", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_EE2A3_0", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NE2A0_0", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_NW4A2_0", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NE4C1_0", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW2A1_0", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_SE4BEG0_0", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_WW4END0_0", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_NE4BEG3_0", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_EE4BEG2_0", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SE2A3_0", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SE2A1_0", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_ER1BEG0_0", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_SW4END1_0", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_WW4A2_0", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_NW4END0_0", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_EE2BEG1_0", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_WW4B1_0", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW4END2_0", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_SE4BEG3_0", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_LH1_0", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_LH3_0", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_NW2A3_0", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_EE4B2_0", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_SE4BEG1_0", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SW2A3_0", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_EL1BEG0_0", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_SW2A2_0", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_ER1BEG3_0", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW4B0_0", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_EE2A1_0", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_LH10_0", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WW4END1_0", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE4C3_0", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_EE2A0_0", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_EE2BEG2_0", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NW4END3_0", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_NW4END2_0", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4END3_0", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_EE4A0_0", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4B0_0", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH2_0", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_SE2A0_0", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SE4C2_0", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_LH5_0", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_WW4A0_0", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_NE4C3_0", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WL1END3_0", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_WW2A3_0", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WW4C0_0", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_LH7_0", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_NE4BEG2_0", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_WL1END1_0", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_WW2END2_0", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_WW2END1_0", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_SE4C3_0", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WW4B2_0", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE4B1_0", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_WL1END2_0", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WW2END0_0", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NE4BEG0_0", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NE4BEG1_0", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_LH9_0", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_EL1BEG2_0", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_WW4A3_0", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_LH11_0", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW2A0_0", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WR1END1_0", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_NW2A0_0", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_SW4A1_0", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_LH8_0", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_EE2BEG3_0", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_SE2A2_0", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4A2_0", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SW2A0_0", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WL1END0_0", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_EE4BEG3_0", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WR1END3_0", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_NE2A2_0", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_SW4END0_0", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_LH4_0", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE4BEG0_0", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NW4END1_0", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_SW4END3_0", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_EE2BEG0_0", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_NW4A1_0", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SW4A2_0", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_EL1BEG3_0", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WW4C1_0", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_LH6_0", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_NW4A0_0", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SE4C1_0", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_NE2A3_0", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_WW4A1_0", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_WW4C3_0", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE4C0_0", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_LH12_0", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_ER1BEG2_0", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_WR1END2_0", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_EE4A1_0", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_WW2A2_0", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WW2END3_0", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_NW4A3_0", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_EE4C2_0", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NE4C0_0", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_SW2A1_0", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4BEG1_0", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_WW4B3_0", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SE4C0_0", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_SW4END2_0", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WR1END0_0", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_NW2A1_0", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_NE2A1_0", + "INT_FEEDTHRU_2_NE2A1" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "CLK_HROW_LH10_2", + "VBRK_LH10" + ], + [ + "CLK_HROW_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_LH11_2", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH7_2", + "VBRK_LH7" + ], + [ + "CLK_HROW_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_LH1_2", + "VBRK_LH1" + ], + [ + "CLK_HROW_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_LH8_2", + "VBRK_LH8" + ], + [ + "CLK_HROW_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_LH12_2", + "VBRK_LH12" + ], + [ + "CLK_HROW_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_LH4_2", + "VBRK_LH4" + ], + [ + "CLK_HROW_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_LH5_2", + "VBRK_LH5" + ], + [ + "CLK_HROW_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_NW2A2_2", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_LH9_2", + "VBRK_LH9" + ], + [ + "CLK_HROW_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_LH2_2", + "VBRK_LH2" + ], + [ + "CLK_HROW_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_LH3_2", + "VBRK_LH3" + ], + [ + "CLK_HROW_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_LH6_2", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE4B3_2", + "VBRK_EE4B3" + ] + ], + "tile_types": [ + "CLK_BUFG_TOP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -10 + ], + "wire_pairs": [ + [ + "MONITOR_VERT_VAUXN0", + "MONITOR_VERT_SHORT_VAUXN0" + ], + [ + "MONITOR_VERT_VAUXP8", + "MONITOR_VERT_SHORT_VAUXP8" + ], + [ + "MONITOR_VERT_VAUXP12", + "MONITOR_VERT_SHORT_VAUXP12" + ], + [ + "MONITOR_VERT_VAUXP2", + "MONITOR_VERT_SHORT_VAUXP2" + ], + [ + "MONITOR_VERT_VAUXP9", + "MONITOR_VERT_SHORT_VAUXP9" + ], + [ + "MONITOR_VERT_VAUXN9", + "MONITOR_VERT_SHORT_VAUXN9" + ], + [ + "MONITOR_VERT_VAUXN3", + "MONITOR_VERT_SHORT_VAUXN3" + ], + [ + "MONITOR_VERT_VAUXP1", + "MONITOR_VERT_SHORT_VAUXP1" + ], + [ + "MONITOR_VERT_VAUXP0", + "MONITOR_VERT_SHORT_VAUXP0" + ], + [ + "MONITOR_VERT_VAUXP11", + "MONITOR_VERT_SHORT_VAUXP11" + ], + [ + "MONITOR_VERT_VAUXN11", + "MONITOR_VERT_SHORT_VAUXN11" + ], + [ + "MONITOR_VERT_VAUXP4", + "MONITOR_VERT_SHORT_VAUXP4" + ], + [ + "MONITOR_VERT_VAUXP5", + "MONITOR_VERT_SHORT_VAUXP5" + ], + [ + "MONITOR_VERT_VAUXP3", + "MONITOR_VERT_SHORT_VAUXP3" + ], + [ + "MONITOR_VERT_VAUXN2", + "MONITOR_VERT_SHORT_VAUXN2" + ], + [ + "MONITOR_VERT_VAUXN4", + "MONITOR_VERT_SHORT_VAUXN4" + ], + [ + "MONITOR_VERT_VAUXN12", + "MONITOR_VERT_SHORT_VAUXN12" + ], + [ + "MONITOR_VERT_VAUXN1", + "MONITOR_VERT_SHORT_VAUXN1" + ], + [ + "MONITOR_VERT_VAUXN5", + "MONITOR_VERT_SHORT_VAUXN5" + ], + [ + "MONITOR_VERT_VAUXN10", + "MONITOR_VERT_SHORT_VAUXN10" + ], + [ + "MONITOR_VERT_VAUXN8", + "MONITOR_VERT_SHORT_VAUXN8" + ], + [ + "MONITOR_VERT_VAUXP10", + "MONITOR_VERT_SHORT_VAUXP10" + ] + ], + "tile_types": [ + "MONITOR_MID_FUJI2", + "MONITOR_TOP_FUJI2" + ] + }, + { + "grid_deltas": [ + 1, + -6 + ], + "wire_pairs": [ + [ + "MONITOR_SE4C2_6", + "VFRAME_SE4C2" + ], + [ + "MONITOR_LH4_6", + "VFRAME_LH4" + ], + [ + "MONITOR_SW4A2_6", + "VFRAME_SW4A2" + ], + [ + "MONITOR_NW4A3_6", + "VFRAME_NW4A3" + ], + [ + "MONITOR_SW2A2_6", + "VFRAME_SW2A2" + ], + [ + "MONITOR_SE4C1_6", + "VFRAME_SE4C1" + ], + [ + "MONITOR_IMUX21_6", + "VFRAME_IMUX21" + ], + [ + "MONITOR_IMUX19_6", + "VFRAME_IMUX19" + ], + [ + "MONITOR_WR1END1_6", + "VFRAME_WR1END1" + ], + [ + "MONITOR_EE4A2_6", + "VFRAME_EE4A2" + ], + [ + "MONITOR_WW4A0_6", + "VFRAME_WW4A0" + ], + [ + "MONITOR_SW4A0_6", + "VFRAME_SW4A0" + ], + [ + "MONITOR_WW2END3_6", + "VFRAME_WW2END3" + ], + [ + "MONITOR_IMUX7_6", + "VFRAME_IMUX7" + ], + [ + "MONITOR_WW4B3_6", + "VFRAME_WW4B3" + ], + [ + "MONITOR_EE4BEG0_6", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_IMUX27_6", + "VFRAME_IMUX27" + ], + [ + "MONITOR_EE2A0_6", + "VFRAME_EE2A0" + ], + [ + "MONITOR_IMUX44_6", + "VFRAME_IMUX44" + ], + [ + "MONITOR_NW4END0_6", + "VFRAME_NW4END0" + ], + [ + "MONITOR_IMUX14_6", + "VFRAME_IMUX14" + ], + [ + "MONITOR_IMUX12_6", + "VFRAME_IMUX12" + ], + [ + "MONITOR_WW4C1_6", + "VFRAME_WW4C1" + ], + [ + "MONITOR_IMUX9_6", + "VFRAME_IMUX9" + ], + [ + "MONITOR_WR1END2_6", + "VFRAME_WR1END2" + ], + [ + "MONITOR_IMUX39_6", + "VFRAME_IMUX39" + ], + [ + "MONITOR_SW2A3_6", + "VFRAME_SW2A3" + ], + [ + "MONITOR_WW2A1_6", + "VFRAME_WW2A1" + ], + [ + "MONITOR_IMUX35_6", + "VFRAME_IMUX35" + ], + [ + "MONITOR_WW4END0_6", + "VFRAME_WW4END0" + ], + [ + "MONITOR_FAN4_6", + "VFRAME_FAN4" + ], + [ + "MONITOR_SW2A0_6", + "VFRAME_SW2A0" + ], + [ + "MONITOR_IMUX30_6", + "VFRAME_IMUX30" + ], + [ + "MONITOR_BYP1_6", + "VFRAME_BYP1" + ], + [ + "MONITOR_IMUX40_6", + "VFRAME_IMUX40" + ], + [ + "MONITOR_IMUX17_6", + "VFRAME_IMUX17" + ], + [ + "MONITOR_EE4B2_6", + "VFRAME_EE4B2" + ], + [ + "MONITOR_SW4A3_6", + "VFRAME_SW4A3" + ], + [ + "MONITOR_ER1BEG0_6", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_IMUX43_6", + "VFRAME_IMUX43" + ], + [ + "MONITOR_IMUX32_6", + "VFRAME_IMUX32" + ], + [ + "MONITOR_IMUX24_6", + "VFRAME_IMUX24" + ], + [ + "MONITOR_SE2A2_6", + "VFRAME_SE2A2" + ], + [ + "MONITOR_SW4END2_6", + "VFRAME_SW4END2" + ], + [ + "MONITOR_FAN3_6", + "VFRAME_FAN3" + ], + [ + "MONITOR_WW2A2_6", + "VFRAME_WW2A2" + ], + [ + "MONITOR_CTRL1_6", + "VFRAME_CTRL1" + ], + [ + "MONITOR_SE2A3_6", + "VFRAME_SE2A3" + ], + [ + "MONITOR_SW4A1_6", + "VFRAME_SW4A1" + ], + [ + "MONITOR_NE4BEG0_6", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_BYP6_6", + "VFRAME_BYP6" + ], + [ + "MONITOR_WL1END2_6", + "VFRAME_WL1END2" + ], + [ + "MONITOR_SE4BEG0_6", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_IMUX46_6", + "VFRAME_IMUX46" + ], + [ + "MONITOR_WW2A0_6", + "VFRAME_WW2A0" + ], + [ + "MONITOR_IMUX1_6", + "VFRAME_IMUX1" + ], + [ + "MONITOR_LH3_6", + "VFRAME_LH3" + ], + [ + "MONITOR_NW4END2_6", + "VFRAME_NW4END2" + ], + [ + "MONITOR_IMUX37_6", + "VFRAME_IMUX37" + ], + [ + "MONITOR_FAN2_6", + "VFRAME_FAN2" + ], + [ + "MONITOR_EE4BEG1_6", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_SW4END0_6", + "VFRAME_SW4END0" + ], + [ + "MONITOR_LH1_6", + "VFRAME_LH1" + ], + [ + "MONITOR_SW2A1_6", + "VFRAME_SW2A1" + ], + [ + "MONITOR_EE4C2_6", + "VFRAME_EE4C2" + ], + [ + "MONITOR_IMUX3_6", + "VFRAME_IMUX3" + ], + [ + "MONITOR_NE4C1_6", + "VFRAME_NE4C1" + ], + [ + "MONITOR_IMUX47_6", + "VFRAME_IMUX47" + ], + [ + "MONITOR_NE4C2_6", + "VFRAME_NE4C2" + ], + [ + "MONITOR_IMUX13_6", + "VFRAME_IMUX13" + ], + [ + "MONITOR_WW4A3_6", + "VFRAME_WW4A3" + ], + [ + "MONITOR_BYP0_6", + "VFRAME_BYP0" + ], + [ + "MONITOR_IMUX6_6", + "VFRAME_IMUX6" + ], + [ + "MONITOR_EE4A3_6", + "VFRAME_EE4A3" + ], + [ + "MONITOR_LH9_6", + "VFRAME_LH9" + ], + [ + "MONITOR_NE4BEG1_6", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_CTRL0_6", + "VFRAME_CTRL0" + ], + [ + "MONITOR_CLK1_6", + "VFRAME_CLK1" + ], + [ + "MONITOR_NE4BEG3_6", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_WW4C2_6", + "VFRAME_WW4C2" + ], + [ + "MONITOR_NW4A2_6", + "VFRAME_NW4A2" + ], + [ + "MONITOR_LH8_6", + "VFRAME_LH8" + ], + [ + "MONITOR_IMUX10_6", + "VFRAME_IMUX10" + ], + [ + "MONITOR_NE4C0_6", + "VFRAME_NE4C0" + ], + [ + "MONITOR_NE2A3_6", + "VFRAME_NE2A3" + ], + [ + "MONITOR_EE2A2_6", + "VFRAME_EE2A2" + ], + [ + "MONITOR_WW2END2_6", + "VFRAME_WW2END2" + ], + [ + "MONITOR_BYP5_6", + "VFRAME_BYP5" + ], + [ + "MONITOR_IMUX29_6", + "VFRAME_IMUX29" + ], + [ + "MONITOR_WW4B1_6", + "VFRAME_WW4B1" + ], + [ + "MONITOR_IMUX34_6", + "VFRAME_IMUX34" + ], + [ + "MONITOR_EE4C1_6", + "VFRAME_EE4C1" + ], + [ + "MONITOR_EE2A3_6", + "VFRAME_EE2A3" + ], + [ + "MONITOR_IMUX2_6", + "VFRAME_IMUX2" + ], + [ + "MONITOR_LH6_6", + "VFRAME_LH6" + ], + [ + "MONITOR_IMUX18_6", + "VFRAME_IMUX18" + ], + [ + "MONITOR_IMUX26_6", + "VFRAME_IMUX26" + ], + [ + "MONITOR_CLK0_6", + "VFRAME_CLK0" + ], + [ + "MONITOR_WR1END0_6", + "VFRAME_WR1END0" + ], + [ + "MONITOR_SW4END1_6", + "VFRAME_SW4END1" + ], + [ + "MONITOR_IMUX33_6", + "VFRAME_IMUX33" + ], + [ + "MONITOR_EE4A0_6", + "VFRAME_EE4A0" + ], + [ + "MONITOR_IMUX5_6", + "VFRAME_IMUX5" + ], + [ + "MONITOR_EE4C0_6", + "VFRAME_EE4C0" + ], + [ + "MONITOR_LH2_6", + "VFRAME_LH2" + ], + [ + "MONITOR_IMUX23_6", + "VFRAME_IMUX23" + ], + [ + "MONITOR_SE2A0_6", + "VFRAME_SE2A0" + ], + [ + "MONITOR_EE4B3_6", + "VFRAME_EE4B3" + ], + [ + "MONITOR_EE4A1_6", + "VFRAME_EE4A1" + ], + [ + "MONITOR_ER1BEG1_6", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_WR1END3_6", + "VFRAME_WR1END3" + ], + [ + "MONITOR_WW4END3_6", + "VFRAME_WW4END3" + ], + [ + "MONITOR_IMUX0_6", + "VFRAME_IMUX0" + ], + [ + "MONITOR_IMUX28_6", + "VFRAME_IMUX28" + ], + [ + "MONITOR_WL1END1_6", + "VFRAME_WL1END1" + ], + [ + "MONITOR_NE2A0_6", + "VFRAME_NE2A0" + ], + [ + "MONITOR_IMUX11_6", + "VFRAME_IMUX11" + ], + [ + "MONITOR_EE4BEG2_6", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_LH5_6", + "VFRAME_LH5" + ], + [ + "MONITOR_FAN5_6", + "VFRAME_FAN5" + ], + [ + "MONITOR_EL1BEG1_6", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_IMUX38_6", + "VFRAME_IMUX38" + ], + [ + "MONITOR_SE2A1_6", + "VFRAME_SE2A1" + ], + [ + "MONITOR_WW2END1_6", + "VFRAME_WW2END1" + ], + [ + "MONITOR_IMUX31_6", + "VFRAME_IMUX31" + ], + [ + "MONITOR_IMUX45_6", + "VFRAME_IMUX45" + ], + [ + "MONITOR_SE4BEG2_6", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_FAN0_6", + "VFRAME_FAN0" + ], + [ + "MONITOR_EE2BEG2_6", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_LH7_6", + "VFRAME_LH7" + ], + [ + "MONITOR_EE4B0_6", + "VFRAME_EE4B0" + ], + [ + "MONITOR_EL1BEG0_6", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_WL1END0_6", + "VFRAME_WL1END0" + ], + [ + "MONITOR_BYP3_6", + "VFRAME_BYP3" + ], + [ + "MONITOR_IMUX16_6", + "VFRAME_IMUX16" + ], + [ + "MONITOR_ER1BEG3_6", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_WW4END2_6", + "VFRAME_WW4END2" + ], + [ + "MONITOR_EE4B1_6", + "VFRAME_EE4B1" + ], + [ + "MONITOR_LH10_6", + "VFRAME_LH10" + ], + [ + "MONITOR_IMUX20_6", + "VFRAME_IMUX20" + ], + [ + "MONITOR_NW4A1_6", + "VFRAME_NW4A1" + ], + [ + "MONITOR_NE4BEG2_6", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_WL1END3_6", + "VFRAME_WL1END3" + ], + [ + "MONITOR_EE4C3_6", + "VFRAME_EE4C3" + ], + [ + "MONITOR_SE4BEG3_6", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_IMUX42_6", + "VFRAME_IMUX42" + ], + [ + "MONITOR_IMUX36_6", + "VFRAME_IMUX36" + ], + [ + "MONITOR_IMUX22_6", + "VFRAME_IMUX22" + ], + [ + "MONITOR_WW2END0_6", + "VFRAME_WW2END0" + ], + [ + "MONITOR_WW2A3_6", + "VFRAME_WW2A3" + ], + [ + "MONITOR_ER1BEG2_6", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_NW2A2_6", + "VFRAME_NW2A2" + ], + [ + "MONITOR_LH11_6", + "VFRAME_LH11" + ], + [ + "MONITOR_WW4A2_6", + "VFRAME_WW4A2" + ], + [ + "MONITOR_BYP7_6", + "VFRAME_BYP7" + ], + [ + "MONITOR_NW2A0_6", + "VFRAME_NW2A0" + ], + [ + "MONITOR_FAN7_6", + "VFRAME_FAN7" + ], + [ + "MONITOR_IMUX8_6", + "VFRAME_IMUX8" + ], + [ + "MONITOR_IMUX15_6", + "VFRAME_IMUX15" + ], + [ + "MONITOR_EL1BEG2_6", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_IMUX25_6", + "VFRAME_IMUX25" + ], + [ + "MONITOR_SW4END3_6", + "VFRAME_SW4END3" + ], + [ + "MONITOR_EL1BEG3_6", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_NW4END1_6", + "VFRAME_NW4END1" + ], + [ + "MONITOR_EE2BEG1_6", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_SE4C0_6", + "VFRAME_SE4C0" + ], + [ + "MONITOR_IMUX4_6", + "VFRAME_IMUX4" + ], + [ + "MONITOR_FAN1_6", + "VFRAME_FAN1" + ], + [ + "MONITOR_NW4A0_6", + "VFRAME_NW4A0" + ], + [ + "MONITOR_WW4B2_6", + "VFRAME_WW4B2" + ], + [ + "MONITOR_NW2A3_6", + "VFRAME_NW2A3" + ], + [ + "MONITOR_NE4C3_6", + "VFRAME_NE4C3" + ], + [ + "MONITOR_WW4C3_6", + "VFRAME_WW4C3" + ], + [ + "MONITOR_EE2BEG0_6", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_NE2A2_6", + "VFRAME_NE2A2" + ], + [ + "MONITOR_SE4BEG1_6", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_NE2A1_6", + "VFRAME_NE2A1" + ], + [ + "MONITOR_EE4BEG3_6", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_LH12_6", + "VFRAME_LH12" + ], + [ + "MONITOR_NW4END3_6", + "VFRAME_NW4END3" + ], + [ + "MONITOR_BYP4_6", + "VFRAME_BYP4" + ], + [ + "MONITOR_WW4END1_6", + "VFRAME_WW4END1" + ], + [ + "MONITOR_EE2A1_6", + "VFRAME_EE2A1" + ], + [ + "MONITOR_NW2A1_6", + "VFRAME_NW2A1" + ], + [ + "MONITOR_FAN6_6", + "VFRAME_FAN6" + ], + [ + "MONITOR_SE4C3_6", + "VFRAME_SE4C3" + ], + [ + "MONITOR_BYP2_6", + "VFRAME_BYP2" + ], + [ + "MONITOR_EE2BEG3_6", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_IMUX41_6", + "VFRAME_IMUX41" + ], + [ + "MONITOR_WW4A1_6", + "VFRAME_WW4A1" + ], + [ + "MONITOR_WW4C0_6", + "VFRAME_WW4C0" + ], + [ + "MONITOR_WW4B0_6", + "VFRAME_WW4B0" + ] + ], + "tile_types": [ + "MONITOR_MID_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_LH12", + "PCIE_LH12_1" + ], + [ + "INT_INTERFACE_FAN6", + "PCIE_FAN6_R_1" + ], + [ + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_1" + ], + [ + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_1" + ], + [ + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_1" + ], + [ + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_1" + ], + [ + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_1" + ], + [ + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT15", + "PCIE_IMUX15_R_1" + ], + [ + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_1" + ], + [ + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_1" + ], + [ + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_1" + ], + [ + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT30", + "PCIE_IMUX30_R_1" + ], + [ + "INT_INTERFACE_FAN0", + "PCIE_FAN0_R_1" + ], + [ + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B16", + "PCIE_LOGIC_OUTS_B16_R_1" + ], + [ + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_1" + ], + [ + "INT_INTERFACE_BYP1", + "PCIE_BYP1_R_1" + ], + [ + "INT_INTERFACE_EL1BEG3", + "PCIE_EL1BEG3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT8", + "PCIE_IMUX8_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT6", + "PCIE_IMUX6_R_1" + ], + [ + "INT_INTERFACE_FAN1", + "PCIE_FAN1_R_1" + ], + [ + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_1" + ], + [ + "INT_INTERFACE_EE4A0", + "PCIE_EE4A0_1" + ], + [ + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT5", + "PCIE_IMUX5_R_1" + ], + [ + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B3", + "PCIE_LOGIC_OUTS_B3_R_1" + ], + [ + "INT_INTERFACE_EE4B0", + "PCIE_EE4B0_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT25", + "PCIE_IMUX25_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT42", + "PCIE_IMUX42_R_1" + ], + [ + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT18", + "PCIE_IMUX18_R_1" + ], + [ + "INT_INTERFACE_LH7", + "PCIE_LH7_1" + ], + [ + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT28", + "PCIE_IMUX28_R_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B7", + "PCIE_LOGIC_OUTS_B7_R_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B2", + "PCIE_LOGIC_OUTS_B2_R_1" + ], + [ + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_1" + ], + [ + "INT_INTERFACE_FAN5", + "PCIE_FAN5_R_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B1", + "PCIE_LOGIC_OUTS_B1_R_1" + ], + [ + "INT_INTERFACE_LH3", + "PCIE_LH3_1" + ], + [ + "INT_INTERFACE_CTRL1", + "PCIE_CTRL1_R_1" + ], + [ + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_1" + ], + [ + "INT_INTERFACE_EE4C0", + "PCIE_EE4C0_1" + ], + [ + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B22", + "PCIE_LOGIC_OUTS_B22_R_1" + ], + [ + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT46", + "PCIE_IMUX46_R_1" + ], + [ + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B19", + "PCIE_LOGIC_OUTS_B19_R_1" + ], + [ + "INT_INTERFACE_LH11", + "PCIE_LH11_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT31", + "PCIE_IMUX31_R_1" + ], + [ + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_1" + ], + [ + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT11", + "PCIE_IMUX11_R_1" + ], + [ + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT29", + "PCIE_IMUX29_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT23", + "PCIE_IMUX23_R_1" + ], + [ + "INT_INTERFACE_EE2A3", + "PCIE_EE2A3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT45", + "PCIE_IMUX45_R_1" + ], + [ + "INT_INTERFACE_BYP4", + "PCIE_BYP4_R_1" + ], + [ + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT2", + "PCIE_IMUX2_R_1" + ], + [ + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_1" + ], + [ + "INT_INTERFACE_CLK1", + "PCIE_CLK1_R_1" + ], + [ + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_1" + ], + [ + "INT_INTERFACE_LH9", + "PCIE_LH9_1" + ], + [ + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_1" + ], + [ + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_1" + ], + [ + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_1" + ], + [ + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT32", + "PCIE_IMUX32_R_1" + ], + [ + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_1" + ], + [ + "INT_INTERFACE_ER1BEG0", + "PCIE_ER1BEG0_1" + ], + [ + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_1" + ], + [ + "INT_INTERFACE_MONITOR_N", + "PCIE_MONITOR_N_1" + ], + [ + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_1" + ], + [ + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_1" + ], + [ + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_1" + ], + [ + "INT_INTERFACE_LH2", + "PCIE_LH2_1" + ], + [ + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B15", + "PCIE_LOGIC_OUTS_B15_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT17", + "PCIE_IMUX17_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT47", + "PCIE_IMUX47_R_1" + ], + [ + "INT_INTERFACE_EE2A1", + "PCIE_EE2A1_1" + ], + [ + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B8", + "PCIE_LOGIC_OUTS_B8_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT4", + "PCIE_IMUX4_R_1" + ], + [ + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT9", + "PCIE_IMUX9_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT24", + "PCIE_IMUX24_R_1" + ], + [ + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_1" + ], + [ + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_1" + ], + [ + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_1" + ], + [ + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_1" + ], + [ + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT16", + "PCIE_IMUX16_R_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B13", + "PCIE_LOGIC_OUTS_B13_R_1" + ], + [ + "INT_INTERFACE_FAN7", + "PCIE_FAN7_R_1" + ], + [ + "INT_INTERFACE_CLK0", + "PCIE_CLK0_R_1" + ], + [ + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_1" + ], + [ + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_1" + ], + [ + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT27", + "PCIE_IMUX27_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT37", + "PCIE_IMUX37_R_1" + ], + [ + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_1" + ], + [ + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B17", + "PCIE_LOGIC_OUTS_B17_R_1" + ], + [ + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_1" + ], + [ + "INT_INTERFACE_BYP7", + "PCIE_BYP7_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT41", + "PCIE_IMUX41_R_1" + ], + [ + "INT_INTERFACE_EE2A2", + "PCIE_EE2A2_1" + ], + [ + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT40", + "PCIE_IMUX40_R_1" + ], + [ + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B20", + "PCIE_LOGIC_OUTS_B20_R_1" + ], + [ + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_1" + ], + [ + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_1" + ], + [ + "INT_INTERFACE_LH5", + "PCIE_LH5_1" + ], + [ + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_1" + ], + [ + "INT_INTERFACE_EE2BEG0", + "PCIE_EE2BEG0_1" + ], + [ + "INT_INTERFACE_EE4C2", + "PCIE_EE4C2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B18", + "PCIE_LOGIC_OUTS_B18_R_1" + ], + [ + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_1" + ], + [ + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT7", + "PCIE_IMUX7_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT22", + "PCIE_IMUX22_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT33", + "PCIE_IMUX33_R_1" + ], + [ + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_1" + ], + [ + "INT_INTERFACE_EE2BEG1", + "PCIE_EE2BEG1_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT35", + "PCIE_IMUX35_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT38", + "PCIE_IMUX38_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT0", + "PCIE_IMUX0_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT13", + "PCIE_IMUX13_R_1" + ], + [ + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_1" + ], + [ + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_1" + ], + [ + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_1" + ], + [ + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_1" + ], + [ + "INT_INTERFACE_LH8", + "PCIE_LH8_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B12", + "PCIE_LOGIC_OUTS_B12_R_1" + ], + [ + "INT_INTERFACE_BYP6", + "PCIE_BYP6_R_1" + ], + [ + "INT_INTERFACE_EE4C1", + "PCIE_EE4C1_1" + ], + [ + "INT_INTERFACE_CTRL0", + "PCIE_CTRL0_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT3", + "PCIE_IMUX3_R_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B6", + "PCIE_LOGIC_OUTS_B6_R_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B14", + "PCIE_LOGIC_OUTS_B14_R_1" + ], + [ + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_1" + ], + [ + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_1" + ], + [ + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B23", + "PCIE_LOGIC_OUTS_B23_R_1" + ], + [ + "INT_INTERFACE_BYP3", + "PCIE_BYP3_R_1" + ], + [ + "INT_INTERFACE_FAN4", + "PCIE_FAN4_R_1" + ], + [ + "INT_INTERFACE_EE2BEG3", + "PCIE_EE2BEG3_1" + ], + [ + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_1" + ], + [ + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_1" + ], + [ + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT12", + "PCIE_IMUX12_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT20", + "PCIE_IMUX20_R_1" + ], + [ + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT43", + "PCIE_IMUX43_R_1" + ], + [ + "INT_INTERFACE_BYP0", + "PCIE_BYP0_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT39", + "PCIE_IMUX39_R_1" + ], + [ + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_1" + ], + [ + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_1" + ], + [ + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B10", + "PCIE_LOGIC_OUTS_B10_R_1" + ], + [ + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_1" + ], + [ + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_1" + ], + [ + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_1" + ], + [ + "INT_INTERFACE_FAN2", + "PCIE_FAN2_R_1" + ], + [ + "INT_INTERFACE_FAN3", + "PCIE_FAN3_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT26", + "PCIE_IMUX26_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT21", + "PCIE_IMUX21_R_1" + ], + [ + "INT_INTERFACE_LH6", + "PCIE_LH6_1" + ], + [ + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_1" + ], + [ + "INT_INTERFACE_LH4", + "PCIE_LH4_1" + ], + [ + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_1" + ], + [ + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_1" + ], + [ + "INT_INTERFACE_LH1", + "PCIE_LH1_1" + ], + [ + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B9", + "PCIE_LOGIC_OUTS_B9_R_1" + ], + [ + "INT_INTERFACE_EE2BEG2", + "PCIE_EE2BEG2_1" + ], + [ + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_1" + ], + [ + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_1" + ], + [ + "INT_INTERFACE_EE4A1", + "PCIE_EE4A1_1" + ], + [ + "INT_INTERFACE_BYP5", + "PCIE_BYP5_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT36", + "PCIE_IMUX36_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT1", + "PCIE_IMUX1_R_1" + ], + [ + "INT_INTERFACE_LH10", + "PCIE_LH10_1" + ], + [ + "INT_INTERFACE_BYP2", + "PCIE_BYP2_R_1" + ], + [ + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT44", + "PCIE_IMUX44_R_1" + ], + [ + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_1" + ], + [ + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B21", + "PCIE_LOGIC_OUTS_B21_R_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B5", + "PCIE_LOGIC_OUTS_B5_R_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT34", + "PCIE_IMUX34_R_1" + ], + [ + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_1" + ], + [ + "INT_INTERFACE_EE4A3", + "PCIE_EE4A3_1" + ], + [ + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_1" + ], + [ + "INT_INTERFACE_MONITOR_P", + "PCIE_MONITOR_P_1" + ], + [ + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B0", + "PCIE_LOGIC_OUTS_B0_R_1" + ], + [ + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_1" + ], + [ + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT14", + "PCIE_IMUX14_R_1" + ], + [ + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B11", + "PCIE_LOGIC_OUTS_B11_R_1" + ], + [ + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_1" + ], + [ + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_1" + ], + [ + "INT_INTERFACE_EE2A0", + "PCIE_EE2A0_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT10", + "PCIE_IMUX10_R_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B4", + "PCIE_LOGIC_OUTS_B4_R_1" + ], + [ + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_1" + ], + [ + "INT_INTERFACE_EE4A2", + "PCIE_EE4A2_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT19", + "PCIE_IMUX19_R_1" + ] + ], + "tile_types": [ + "PCIE_INT_INTERFACE_R", + "PCIE_TOP" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CK_IN13", + "HCLK_VFRAME_CK_IN13" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_VFRAME_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_VFRAME_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN10", + "HCLK_VFRAME_CK_IN10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_VFRAME_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_VFRAME_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_VFRAME_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_IN3", + "HCLK_VFRAME_CK_IN3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN7", + "HCLK_VFRAME_CK_IN7" + ], + [ + "HCLK_INT_INTERFACE_CK_IN2", + "HCLK_VFRAME_CK_IN2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_VFRAME_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_IN8", + "HCLK_VFRAME_CK_IN8" + ], + [ + "HCLK_INT_INTERFACE_CK_IN12", + "HCLK_VFRAME_CK_IN12" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_VFRAME_CK_IN5" + ], + [ + "HCLK_INT_INTERFACE_CK_IN6", + "HCLK_VFRAME_CK_IN6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_VFRAME_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_IN1", + "HCLK_VFRAME_CK_IN1" + ], + [ + "HCLK_INT_INTERFACE_CK_IN9", + "HCLK_VFRAME_CK_IN9" + ], + [ + "HCLK_INT_INTERFACE_CK_IN11", + "HCLK_VFRAME_CK_IN11" + ], + [ + "HCLK_INT_INTERFACE_CK_IN0", + "HCLK_VFRAME_CK_IN0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_VFRAME_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_IN4", + "HCLK_VFRAME_CK_IN4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_VFRAME_CK_BUFHCLK1" + ] + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + -5 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4A3_10", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SE2A3_10", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG0_10", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END2_10", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW4C2_10", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_LH8_10", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4B2_10", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A1_10", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW4C0_10", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WL1END3_10", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WL1END0_10", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW2A0_10", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2END0_10", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE4C3_10", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE2BEG1_10", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_LH7_10", + "VBRK_LH7" + ], + [ + "CMT_TOP_EL1BEG1_10", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE4C2_10", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH10_10", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4B1_10", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4C0_10", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH12_10", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_10", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4BEG3_10", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW2END2_10", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW4A2_10", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG3_10", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE4A1_10", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_SW2A0_10", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE2BEG0_10", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE2A0_10", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH5_10", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW2A3_10", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW2A1_10", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WR1END2_10", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SW4END1_10", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW2A3_10", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SW4END2_10", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EL1BEG0_10", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH3_10", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END0_10", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A1_10", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SE4BEG2_10", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4C2_10", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WR1END3_10", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WR1END1_10", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NW4A0_10", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_10", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW4B1_10", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C2_10", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE4BEG3_10", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4BEG1_10", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EE4C1_10", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG2_10", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG3_10", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE4BEG3_10", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE2A1_10", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4A3_10", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_LH11_10", + "VBRK_LH11" + ], + [ + "CMT_TOP_SE4C1_10", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WL1END1_10", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW4B0_10", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2A2_10", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4BEG1_10", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW4A0_10", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END1_10", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_ER1BEG3_10", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WW4END2_10", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_ER1BEG0_10", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_10", + "VBRK_LH1" + ], + [ + "CMT_TOP_WW4C3_10", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END0_10", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW4END3_10", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_LH9_10", + "VBRK_LH9" + ], + [ + "CMT_TOP_NW2A2_10", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_10", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_LH6_10", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A0_10", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE2A2_10", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2BEG2_10", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW2END1_10", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4B0_10", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C1_10", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SW2A2_10", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG2_10", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_NE2A0_10", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE2A1_10", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_10", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW2A0_10", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4A2_10", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW4A1_10", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WR1END0_10", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4B2_10", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END0_10", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4C0_10", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_10", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4B3_10", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4A0_10", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END3_10", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WL1END2_10", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4A2_10", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4B3_10", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NE4C1_10", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A1_10", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2A2_10", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EE4C3_10", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_MONITOR_N_10", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW4A2_10", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NE4BEG2_10", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_SW2A1_10", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4BEG0_10", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SE2A0_10", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4BEG1_10", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_10", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_10", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_SE2A2_10", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4END3_10", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE4C3_10", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4A3_10", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_ER1BEG2_10", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_LH2_10", + "VBRK_LH2" + ], + [ + "CMT_TOP_NE2A3_10", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2A3_10", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C0_10", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_ER1BEG1_10", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_MONITOR_P_10", + "VBRK_MONITOR_P" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "BRKH_CLB_COUT1_L", + "CLBLM_L_COUT_N" + ], + [ + "BRKH_CLB_COUT0_L", + "CLBLM_M_COUT_N" + ] + ], + "tile_types": [ + "BRKH_CLB", + "CLBLM_L" + ] + }, + { + "grid_deltas": [ + 0, + 5 + ], + "wire_pairs": [ + [ + "BRKH_DSP_PCIN5", + "DSP_PCOUT5" + ], + [ + "BRKH_DSP_PCIN12", + "DSP_PCOUT12" + ], + [ + "BRKH_DSP_PCIN44", + "DSP_PCOUT44" + ], + [ + "BRKH_DSP_CARRYCASCIN", + "DSP_CARRYCASCOUT" + ], + [ + "BRKH_DSP_PCIN30", + "DSP_PCOUT30" + ], + [ + "BRKH_DSP_PCIN47", + "DSP_PCOUT47" + ], + [ + "BRKH_DSP_PCIN0", + "DSP_PCOUT0" + ], + [ + "BRKH_DSP_PCIN15", + "DSP_PCOUT15" + ], + [ + "BRKH_DSP_ACIN27", + "DSP_ACOUT27" + ], + [ + "BRKH_DSP_ACIN26", + "DSP_ACOUT26" + ], + [ + "BRKH_DSP_ACIN22", + "DSP_ACOUT22" + ], + [ + "BRKH_DSP_ACIN18", + "DSP_ACOUT18" + ], + [ + "BRKH_DSP_BCIN15", + "DSP_BCOUT15" + ], + [ + "BRKH_DSP_PCIN20", + "DSP_PCOUT20" + ], + [ + "BRKH_DSP_BCIN11", + "DSP_BCOUT11" + ], + [ + "BRKH_DSP_PCIN43", + "DSP_PCOUT43" + ], + [ + "BRKH_DSP_PCIN2", + "DSP_PCOUT2" + ], + [ + "BRKH_DSP_ACIN1", + "DSP_ACOUT1" + ], + [ + "BRKH_DSP_ACIN5", + "DSP_ACOUT5" + ], + [ + "BRKH_DSP_PCIN10", + "DSP_PCOUT10" + ], + [ + "BRKH_DSP_ACIN11", + "DSP_ACOUT11" + ], + [ + "BRKH_DSP_BCIN2", + "DSP_BCOUT2" + ], + [ + "BRKH_DSP_PCIN46", + "DSP_PCOUT46" + ], + [ + "BRKH_DSP_BCIN8", + "DSP_BCOUT8" + ], + [ + "BRKH_DSP_PCIN35", + "DSP_PCOUT35" + ], + [ + "BRKH_DSP_PCIN9", + "DSP_PCOUT9" + ], + [ + "BRKH_DSP_BCIN6", + "DSP_BCOUT6" + ], + [ + "BRKH_DSP_PCIN16", + "DSP_PCOUT16" + ], + [ + "BRKH_DSP_BCIN16", + "DSP_BCOUT16" + ], + [ + "BRKH_DSP_ACIN0", + "DSP_ACOUT0" + ], + [ + "BRKH_DSP_ACIN4", + "DSP_ACOUT4" + ], + [ + "BRKH_DSP_BCIN17", + "DSP_BCOUT17" + ], + [ + "BRKH_DSP_PCIN13", + "DSP_PCOUT13" + ], + [ + "BRKH_DSP_PCIN26", + "DSP_PCOUT26" + ], + [ + "BRKH_DSP_ACIN9", + "DSP_ACOUT9" + ], + [ + "BRKH_DSP_ACIN17", + "DSP_ACOUT17" + ], + [ + "BRKH_DSP_ACIN28", + "DSP_ACOUT28" + ], + [ + "BRKH_DSP_ACIN12", + "DSP_ACOUT12" + ], + [ + "BRKH_DSP_PCIN4", + "DSP_PCOUT4" + ], + [ + "BRKH_DSP_ACIN3", + "DSP_ACOUT3" + ], + [ + "BRKH_DSP_BCIN10", + "DSP_BCOUT10" + ], + [ + "BRKH_DSP_PCIN8", + "DSP_PCOUT8" + ], + [ + "BRKH_DSP_ACIN21", + "DSP_ACOUT21" + ], + [ + "BRKH_DSP_PCIN33", + "DSP_PCOUT33" + ], + [ + "BRKH_DSP_PCIN22", + "DSP_PCOUT22" + ], + [ + "BRKH_DSP_PCIN24", + "DSP_PCOUT24" + ], + [ + "BRKH_DSP_ACIN20", + "DSP_ACOUT20" + ], + [ + "BRKH_DSP_PCIN45", + "DSP_PCOUT45" + ], + [ + "BRKH_DSP_PCIN14", + "DSP_PCOUT14" + ], + [ + "BRKH_DSP_PCIN25", + "DSP_PCOUT25" + ], + [ + "BRKH_DSP_PCIN31", + "DSP_PCOUT31" + ], + [ + "BRKH_DSP_PCIN17", + "DSP_PCOUT17" + ], + [ + "BRKH_DSP_PCIN36", + "DSP_PCOUT36" + ], + [ + "BRKH_DSP_BCIN13", + "DSP_BCOUT13" + ], + [ + "BRKH_DSP_ACIN8", + "DSP_ACOUT8" + ], + [ + "BRKH_DSP_ACIN6", + "DSP_ACOUT6" + ], + [ + "BRKH_DSP_PCIN41", + "DSP_PCOUT41" + ], + [ + "BRKH_DSP_PCIN27", + "DSP_PCOUT27" + ], + [ + "BRKH_DSP_ACIN14", + "DSP_ACOUT14" + ], + [ + "BRKH_DSP_PCIN11", + "DSP_PCOUT11" + ], + [ + "BRKH_DSP_PCIN32", + "DSP_PCOUT32" + ], + [ + "BRKH_DSP_BCIN4", + "DSP_BCOUT4" + ], + [ + "BRKH_DSP_BCIN1", + "DSP_BCOUT1" + ], + [ + "BRKH_DSP_PCIN23", + "DSP_PCOUT23" + ], + [ + "BRKH_DSP_MULTSIGNIN", + "DSP_MULTSIGNOUT" + ], + [ + "BRKH_DSP_ACIN23", + "DSP_ACOUT23" + ], + [ + "BRKH_DSP_PCIN39", + "DSP_PCOUT39" + ], + [ + "BRKH_DSP_PCIN7", + "DSP_PCOUT7" + ], + [ + "BRKH_DSP_PCIN19", + "DSP_PCOUT19" + ], + [ + "BRKH_DSP_ACIN24", + "DSP_ACOUT24" + ], + [ + "BRKH_DSP_BCIN3", + "DSP_BCOUT3" + ], + [ + "BRKH_DSP_PCIN6", + "DSP_PCOUT6" + ], + [ + "BRKH_DSP_ACIN10", + "DSP_ACOUT10" + ], + [ + "BRKH_DSP_BCIN12", + "DSP_BCOUT12" + ], + [ + "BRKH_DSP_PCIN37", + "DSP_PCOUT37" + ], + [ + "BRKH_DSP_PCIN1", + "DSP_PCOUT1" + ], + [ + "BRKH_DSP_BCIN14", + "DSP_BCOUT14" + ], + [ + "BRKH_DSP_PCIN34", + "DSP_PCOUT34" + ], + [ + "BRKH_DSP_PCIN42", + "DSP_PCOUT42" + ], + [ + "BRKH_DSP_PCIN21", + "DSP_PCOUT21" + ], + [ + "BRKH_DSP_PCIN38", + "DSP_PCOUT38" + ], + [ + "BRKH_DSP_PCIN3", + "DSP_PCOUT3" + ], + [ + "BRKH_DSP_ACIN7", + "DSP_ACOUT7" + ], + [ + "BRKH_DSP_BCIN9", + "DSP_BCOUT9" + ], + [ + "BRKH_DSP_PCIN28", + "DSP_PCOUT28" + ], + [ + "BRKH_DSP_BCIN7", + "DSP_BCOUT7" + ], + [ + "BRKH_DSP_ACIN16", + "DSP_ACOUT16" + ], + [ + "BRKH_DSP_BCIN0", + "DSP_BCOUT0" + ], + [ + "BRKH_DSP_ACIN19", + "DSP_ACOUT19" + ], + [ + "BRKH_DSP_PCIN40", + "DSP_PCOUT40" + ], + [ + "BRKH_DSP_ACIN15", + "DSP_ACOUT15" + ], + [ + "BRKH_DSP_PCIN18", + "DSP_PCOUT18" + ], + [ + "BRKH_DSP_ACIN25", + "DSP_ACOUT25" + ], + [ + "BRKH_DSP_PCIN29", + "DSP_PCOUT29" + ], + [ + "BRKH_DSP_ACIN29", + "DSP_ACOUT29" + ], + [ + "BRKH_DSP_ACIN13", + "DSP_ACOUT13" + ], + [ + "BRKH_DSP_ACIN2", + "DSP_ACOUT2" + ], + [ + "BRKH_DSP_BCIN5", + "DSP_BCOUT5" + ] + ], + "tile_types": [ + "BRKH_DSP_R", + "DSP_R" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_PMV2_SVT" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "CLK_PMV_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "CLK_PMV_LH10_2", + "VBRK_LH10" + ], + [ + "CLK_PMV_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "CLK_PMV_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "CLK_PMV_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "CLK_PMV_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "CLK_PMV_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "CLK_PMV_MONITOR_N_2", + "VBRK_MONITOR_N" + ], + [ + "CLK_PMV_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "CLK_PMV_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "CLK_PMV_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "CLK_PMV_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "CLK_PMV_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "CLK_PMV_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "CLK_PMV_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "CLK_PMV_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "CLK_PMV_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "CLK_PMV_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "CLK_PMV_LH9_2", + "VBRK_LH9" + ], + [ + "CLK_PMV_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "CLK_PMV_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "CLK_PMV_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "CLK_PMV_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "CLK_PMV_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CLK_PMV_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "CLK_PMV_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "CLK_PMV_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "CLK_PMV_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "CLK_PMV_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "CLK_PMV_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "CLK_PMV_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "CLK_PMV_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CLK_PMV_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "CLK_PMV_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "CLK_PMV_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "CLK_PMV_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "CLK_PMV_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CLK_PMV_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "CLK_PMV_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "CLK_PMV_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "CLK_PMV_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "CLK_PMV_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "CLK_PMV_LH12_2", + "VBRK_LH12" + ], + [ + "CLK_PMV_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "CLK_PMV_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "CLK_PMV_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "CLK_PMV_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "CLK_PMV_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "CLK_PMV_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "CLK_PMV_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "CLK_PMV_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "CLK_PMV_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "CLK_PMV_MONITOR_P_2", + "VBRK_MONITOR_P" + ], + [ + "CLK_PMV_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "CLK_PMV_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "CLK_PMV_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "CLK_PMV_LH2_2", + "VBRK_LH2" + ], + [ + "CLK_PMV_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "CLK_PMV_LH8_2", + "VBRK_LH8" + ], + [ + "CLK_PMV_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "CLK_PMV_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "CLK_PMV_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "CLK_PMV_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "CLK_PMV_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CLK_PMV_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "CLK_PMV_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "CLK_PMV_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "CLK_PMV_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "CLK_PMV_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "CLK_PMV_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CLK_PMV_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "CLK_PMV_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "CLK_PMV_LH5_2", + "VBRK_LH5" + ], + [ + "CLK_PMV_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "CLK_PMV_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "CLK_PMV_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "CLK_PMV_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "CLK_PMV_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "CLK_PMV_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "CLK_PMV_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "CLK_PMV_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "CLK_PMV_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "CLK_PMV_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "CLK_PMV_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "CLK_PMV_LH3_2", + "VBRK_LH3" + ], + [ + "CLK_PMV_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "CLK_PMV_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "CLK_PMV_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "CLK_PMV_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "CLK_PMV_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "CLK_PMV_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "CLK_PMV_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "CLK_PMV_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "CLK_PMV_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "CLK_PMV_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "CLK_PMV_LH6_2", + "VBRK_LH6" + ], + [ + "CLK_PMV_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "CLK_PMV_LH4_2", + "VBRK_LH4" + ], + [ + "CLK_PMV_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "CLK_PMV_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "CLK_PMV_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CLK_PMV_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "CLK_PMV_NW2A2_2", + "VBRK_NW2A2" + ], + [ + "CLK_PMV_LH11_2", + "VBRK_LH11" + ], + [ + "CLK_PMV_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "CLK_PMV_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "CLK_PMV_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "CLK_PMV_EE4B3_2", + "VBRK_EE4B3" + ], + [ + "CLK_PMV_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "CLK_PMV_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "CLK_PMV_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "CLK_PMV_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "CLK_PMV_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "CLK_PMV_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "CLK_PMV_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "CLK_PMV_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "CLK_PMV_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "CLK_PMV_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "CLK_PMV_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "CLK_PMV_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CLK_PMV_LH1_2", + "VBRK_LH1" + ], + [ + "CLK_PMV_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "CLK_PMV_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "CLK_PMV_LH7_2", + "VBRK_LH7" + ], + [ + "CLK_PMV_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "CLK_PMV_WR1END1_2", + "VBRK_WR1END1" + ] + ], + "tile_types": [ + "CLK_PMV", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "BRKH_CLB_COUT0_R", + "CLBLM_L_CIN" + ], + [ + "BRKH_CLB_COUT1_R", + "CLBLM_M_CIN" + ] + ], + "tile_types": [ + "BRKH_CLB", + "CLBLM_R" + ] + }, + { + "grid_deltas": [ + 0, + -5 + ], + "wire_pairs": [ + [ + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "BRAM_CASCOUT_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "BRAM_CASCOUT_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "BRAM_CASCOUT_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "BRAM_CASCOUT_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU8", + "BRAM_CASCOUT_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU10", + "BRAM_CASCOUT_ADDRARDADDRU10" + ], + [ + "BRAM_PMVBRAM_O_1", + "BRAM_PMVBRAM_O_2" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "BRAM_CASCOUT_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "BRAM_CASCOUT_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "BRAM_CASCOUT_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRAM_CASCOUT_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "BRAM_CASCOUT_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRAM_CASCOUT_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "BRAM_CASCOUT_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU13", + "BRAM_CASCOUT_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRAM_CASCOUT_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "BRAM_CASCOUT_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU2", + "BRAM_CASCOUT_ADDRARDADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRAM_CASCOUT_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "BRAM_CASCOUT_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "BRAM_CASCOUT_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "BRAM_CASCOUT_ADDRBWRADDRU8" + ], + [ + "BRAM_PMVBRAM_ODIV2", + "BRAM_PMVBRAM_ODIV2_1" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU5", + "BRAM_CASCOUT_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU12", + "BRAM_CASCOUT_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU0", + "BRAM_CASCOUT_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU6", + "BRAM_CASCOUT_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU3", + "BRAM_CASCOUT_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU9", + "BRAM_CASCOUT_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "BRAM_CASCOUT_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "BRAM_CASCOUT_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU11", + "BRAM_CASCOUT_ADDRARDADDRU11" + ], + [ + "BRAM_PMVBRAM_O", + "BRAM_PMVBRAM_O_1" + ] + ], + "tile_types": [ + "BRAM_L", + "BRAM_L" + ] + }, + { + "grid_deltas": [ + 1, + 3 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_3" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_3" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_3" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_3" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_3" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_3" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_3" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_3" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_3" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_3" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_3" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_3" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_3" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_3" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_3" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_3" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_3" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_3" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_3" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_3" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_3" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_3" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_3" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_3" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_3" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_3" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_3" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_3" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_3" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_3" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_3" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_3" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_3" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_3" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_3" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_3" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_3" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_3" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_3" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_3" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_3" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_3" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_3" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_3" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_3" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_3" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_3" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_3" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_3" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_3" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_3" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_3" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_3" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_3" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_3" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_3" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_3" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_3" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_3" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_3" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_3" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_3" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_3" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_3" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_3" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_3" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_3" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_3" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_3" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_3" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_3" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_3" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_3" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_3" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_3" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_3" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_3" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_3" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_3" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_3" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_3" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_3" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_3" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_3" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_3" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_3" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_3" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_3" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_3" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_3" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_3" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_3" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_3" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_3" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_3" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_3" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_3" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_3" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_3" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_3" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_3" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_3" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_3" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_3" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_3" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_3" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_3" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_3" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_3" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_3" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_3" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_3" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_3" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_3" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_3" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_3" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_3" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_3" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_3" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_3" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_TOP_FUJI2" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B21_3", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_LOGIC_OUTS_B9_3", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX40_3", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B10_3", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_CTRL0_3", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_BYP0_3", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_BYP3_3", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_BYP5_3", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX2_3", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_FAN2_3", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_FAN1_3", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B8_3", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_LOGIC_OUTS_B13_3", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_CTRL1_3", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX47_3", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_LOGIC_OUTS_B0_3", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX9_3", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX32_3", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX25_3", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX39_3", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX4_3", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX6_3", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX14_3", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX36_3", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX43_3", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX46_3", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_FAN5_3", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX16_3", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX31_3", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B2_3", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_LOGIC_OUTS_B4_3", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B3_3", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX29_3", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_FAN4_3", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX3_3", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX5_3", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B23_3", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX45_3", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX41_3", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX12_3", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX42_3", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_FAN7_3", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B20_3", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX23_3", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_LOGIC_OUTS_B11_3", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_IMUX30_3", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX33_3", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX10_3", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX27_3", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX7_3", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX37_3", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX38_3", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX26_3", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_CLK1_3", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX17_3", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX21_3", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_LOGIC_OUTS_B6_3", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX18_3", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_FAN6_3", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_LOGIC_OUTS_B22_3", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B12_3", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX35_3", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_LOGIC_OUTS_B18_3", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX44_3", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX34_3", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX15_3", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX13_3", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP6_3", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX0_3", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX22_3", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX20_3", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_LOGIC_OUTS_B14_3", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_CLK0_3", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX24_3", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B7_3", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_FAN3_3", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX1_3", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_LOGIC_OUTS_B16_3", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B17_3", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B5_3", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_BYP1_3", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX28_3", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_LOGIC_OUTS_B1_3", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_3", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_BYP2_3", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_BYP4_3", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX8_3", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_LOGIC_OUTS_B15_3", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX19_3", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX11_3", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP7_3", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_FAN0_3", + "VBRK_EXT_FAN0" + ] + ], + "tile_types": [ + "GTX_CHANNEL_2", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + 3 + ], + "wire_pairs": [ + [ + "CMT_FIFO_SW2A2_3", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_NE4BEG0_3", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_3", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "CMT_FIFO_SE4C2_3", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_L_IMUX17_3", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_WW4END1_3", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_NE4BEG2_3", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_SE2A3_3", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_ER1BEG2_3", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_WW4A3_3", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_EE2BEG3_3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_WL1END3_3", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_EE4BEG3_3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_EE2A3_3", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_SE4C0_3", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_SW2A3_3", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_SW4A1_3", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_SE2A1_3", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_SE4BEG1_3", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX46_3", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_EE4A3_3", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_BYP2_3", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_L_IMUX45_3", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_SW4A3_3", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_NW2A3_3", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_WR1END0_3", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_SW4A0_3", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_WW4C3_3", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_NW2A0_3", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_LH12_3", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_WL1END1_3", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_L_IMUX5_3", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_NW2A1_3", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_WR1END3_3", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_ER1BEG0_3", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_NW4END2_3", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_BYP6_3", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_EE4B0_3", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_3", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "CMT_FIFO_L_IMUX11_3", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_NE2A1_3", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_L_IMUX18_3", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_L_IMUX38_3", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_L_IMUX33_3", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_L_BYP7_3", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_L_IMUX19_3", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_EE4BEG0_3", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_SW4A2_3", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_L_IMUX12_3", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_L_FAN3_3", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_NE2A3_3", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_L_IMUX20_3", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_EE4C2_3", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_3", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "CMT_FIFO_L_IMUX1_3", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_3", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "CMT_FIFO_SE4BEG2_3", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_3", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "CMT_FIFO_WW4END2_3", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_L_IMUX32_3", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_L_BYP3_3", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_L_IMUX40_3", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_LH2_3", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_L_IMUX3_3", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_L_BYP0_3", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_LH5_3", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_LH4_3", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_NE2A2_3", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_EL1BEG2_3", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_WL1END0_3", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_NW2A2_3", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_EE4B3_3", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_NE4C1_3", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_L_IMUX25_3", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_L_BYP5_3", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_WW4B3_3", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_L_IMUX15_3", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_EE2A1_3", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_WW4C0_3", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_EE4C0_3", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_L_IMUX41_3", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_LH7_3", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_L_CTRL0_3", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_L_IMUX24_3", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_NW4A1_3", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_L_CLK0_3", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_WW2END0_3", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_EE4BEG1_3", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX14_3", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_NW4END1_3", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_WW2A1_3", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_L_IMUX0_3", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_WW4A1_3", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_SE4C1_3", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_L_IMUX27_3", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_3", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "CMT_FIFO_SW4END1_3", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_EE4A2_3", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_FAN2_3", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_WW2END3_3", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_WW4A0_3", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_NE4BEG3_3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_SE2A2_3", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_3", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "CMT_FIFO_L_IMUX28_3", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_WW4B0_3", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_LH1_3", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_L_IMUX39_3", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_L_IMUX29_3", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_L_IMUX9_3", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX31_3", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_3", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "CMT_FIFO_SW4END0_3", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_WW4END0_3", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_IMUX35_3", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_NE4C3_3", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_3", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "CMT_FIFO_SE4BEG0_3", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_NE4C0_3", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_NW4A3_3", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_SE4BEG3_3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX44_3", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_IMUX23_3", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_L_IMUX13_3", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_EE4BEG2_3", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX16_3", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_L_IMUX7_3", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_NW4A2_3", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_L_FAN4_3", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_WW2A2_3", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_3", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "CMT_FIFO_EE2A0_3", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_IMUX4_3", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_L_IMUX42_3", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_WR1END1_3", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_3", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_3", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_3", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "CMT_FIFO_LH10_3", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_LH6_3", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_WW4END3_3", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_WW2END1_3", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_L_IMUX26_3", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_FAN6_3", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_EE2A2_3", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_NW4END3_3", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_WW2A0_3", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_3", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "CMT_FIFO_L_FAN7_3", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_L_IMUX30_3", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_L_IMUX6_3", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_SW4END3_3", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_L_BYP4_3", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_L_IMUX36_3", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_SW4END2_3", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_EE4C1_3", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_WW4C1_3", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_L_BYP1_3", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_NE4C2_3", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_L_CLK1_3", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_LH8_3", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_IMUX2_3", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_3", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "CMT_FIFO_L_IMUX37_3", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_L_CTRL1_3", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_NW4A0_3", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_EE4B1_3", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_EE2BEG1_3", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_EL1BEG3_3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_L_IMUX21_3", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_3", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "CMT_FIFO_SE4C3_3", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_IMUX10_3", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_3", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "CMT_FIFO_L_IMUX43_3", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_LH9_3", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_NW4END0_3", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_L_FAN5_3", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_L_FAN0_3", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_3", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "CMT_FIFO_EE4B2_3", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_L_IMUX34_3", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_3", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "CMT_FIFO_LH11_3", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_3", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "CMT_FIFO_WW2A3_3", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_EL1BEG0_3", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_NE2A0_3", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_SE2A0_3", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_L_FAN1_3", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_SW2A0_3", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_SW2A1_3", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_EE2BEG2_3", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_WR1END2_3", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_L_IMUX8_3", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_WW2END2_3", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_WL1END2_3", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_EE4C3_3", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_EE4A1_3", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_WW4B2_3", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_EE2BEG0_3", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_ER1BEG3_3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_3", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_3", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "CMT_FIFO_ER1BEG1_3", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_IMUX22_3", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_LH3_3", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_EE4A0_3", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_WW4B1_3", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_NE4BEG1_3", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_WW4A2_3", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_EL1BEG1_3", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_3", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "CMT_FIFO_WW4C2_3", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_3", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "CMT_FIFO_L_IMUX47_3", + "INT_INTERFACE_IMUX47" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "CLBLL_LL_COUT_N", + "HCLK_CLB_COUT0_L" + ], + [ + "CLBLL_L_COUT_N", + "HCLK_CLB_COUT1_L" + ] + ], + "tile_types": [ + "CLBLL_L", + "HCLK_CLB" + ] + }, + { + "grid_deltas": [ + -1, + -6 + ], + "wire_pairs": [ + [ + "CMT_TOP_EE4C0_11", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EL1BEG1_11", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG0_11", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH7_11", + "VBRK_LH7" + ], + [ + "CMT_TOP_LH3_11", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE2A0_11", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_ER1BEG1_11", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_NE4C1_11", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH2_11", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW2A1_11", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NE2A3_11", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_ER1BEG2_11", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NW4END2_11", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE4BEG3_11", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C3_11", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE2A2_11", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_SW2A0_11", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW4A1_11", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_LH9_11", + "VBRK_LH9" + ], + [ + "CMT_TOP_SE4C3_11", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WR1END0_11", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_11", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EL1BEG2_11", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_NE4BEG2_11", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_11", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4C2_11", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4C2_11", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW4C3_11", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_LH4_11", + "VBRK_LH4" + ], + [ + "CMT_TOP_NE4C2_11", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EE4BEG0_11", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NE2A0_11", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NW4A1_11", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG1_11", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4C1_11", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_EE2A1_11", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END1_11", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SE4C2_11", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A0_11", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE4B0_11", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_11", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW4B0_11", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C0_11", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4BEG2_11", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_LH11_11", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE2BEG3_11", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END2_11", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_11", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4A2_11", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EE4BEG3_11", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_NW4END3_11", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_LH1_11", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE4C0_11", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SW4END3_11", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SW4END1_11", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_11", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END1_11", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW2A3_11", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH8_11", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A0_11", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_11", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW4B3_11", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW4A2_11", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4B2_11", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE2A0_11", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WW2END3_11", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EE4A3_11", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SE4C1_11", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_ER1BEG0_11", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_NW4END1_11", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A3_11", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4A2_11", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4C3_11", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW2A0_11", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NE2A1_11", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW4A3_11", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NW2A3_11", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NE4BEG3_11", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_WW2A2_11", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG0_11", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW2END0_11", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2A3_11", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4A2_11", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG2_11", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW2A1_11", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SW4END2_11", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG0_11", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_EE4C1_11", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG1_11", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG1_11", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2BEG2_11", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SW2A1_11", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE2A2_11", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WR1END1_11", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW2A3_11", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW2A0_11", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW4B1_11", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C0_11", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4BEG1_11", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH12_11", + "VBRK_LH12" + ], + [ + "CMT_TOP_WW4END2_11", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW2A2_11", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_EE4A1_11", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH5_11", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4A0_11", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_SE2A1_11", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END2_11", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WL1END3_11", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_ER1BEG3_11", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WW4B2_11", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WL1END0_11", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW4END0_11", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_11", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A3_11", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4END3_11", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_11", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4A0_11", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A1_11", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH10_11", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW4END1_11", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SW4END0_11", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE2A2_11", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW2A2_11", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG0_11", + "VBRK_EL1BEG0" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_BRAM_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_BRAM_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_BRAM_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_BRAM_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_BRAM_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_BRAM_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_BRAM_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_BRAM_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_BRAM_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_BRAM_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_BRAM_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_BRAM_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_BRAM_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_BRAM_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ] + ], + "tile_types": [ + "HCLK_BRAM", + "HCLK_VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "IMUX41", + "INT_INTERFACE_IMUX41" + ], + [ + "SE6E1", + "INT_INTERFACE_SE4C1" + ], + [ + "IMUX19", + "INT_INTERFACE_IMUX19" + ], + [ + "NE6BEG3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "WR1END1", + "INT_INTERFACE_WR1END1" + ], + [ + "BYP3", + "INT_INTERFACE_BYP3" + ], + [ + "EE4C3", + "INT_INTERFACE_EE4C3" + ], + [ + "EE4BEG1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "SE2A1", + "INT_INTERFACE_SE2A1" + ], + [ + "FAN2", + "INT_INTERFACE_FAN2" + ], + [ + "LH6", + "INT_INTERFACE_LH6" + ], + [ + "LOGIC_OUTS4", + "INT_INTERFACE_LOGIC_OUTS4" + ], + [ + "NW6A2", + "INT_INTERFACE_NW4A2" + ], + [ + "SE2A2", + "INT_INTERFACE_SE2A2" + ], + [ + "EE2BEG0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "LOGIC_OUTS13", + "INT_INTERFACE_LOGIC_OUTS13" + ], + [ + "EL1BEG0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "ER1BEG0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "IMUX14", + "INT_INTERFACE_IMUX14" + ], + [ + "SE6E0", + "INT_INTERFACE_SE4C0" + ], + [ + "IMUX6", + "INT_INTERFACE_IMUX6" + ], + [ + "FAN0", + "INT_INTERFACE_FAN0" + ], + [ + "IMUX3", + "INT_INTERFACE_IMUX3" + ], + [ + "IMUX5", + "INT_INTERFACE_IMUX5" + ], + [ + "SE2A0", + "INT_INTERFACE_SE2A0" + ], + [ + "IMUX1", + "INT_INTERFACE_IMUX1" + ], + [ + "WW2A3", + "INT_INTERFACE_WW2A3" + ], + [ + "WL1END1", + "INT_INTERFACE_WL1END1" + ], + [ + "SW2END2", + "INT_INTERFACE_SW2A2" + ], + [ + "NW6END2", + "INT_INTERFACE_NW4END2" + ], + [ + "EE2A1", + "INT_INTERFACE_EE2A1" + ], + [ + "LOGIC_OUTS12", + "INT_INTERFACE_LOGIC_OUTS12" + ], + [ + "IMUX47", + "INT_INTERFACE_IMUX47" + ], + [ + "SE6BEG3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "NE6E2", + "INT_INTERFACE_NE4C2" + ], + [ + "LOGIC_OUTS23", + "INT_INTERFACE_LOGIC_OUTS23" + ], + [ + "NE6E0", + "INT_INTERFACE_NE4C0" + ], + [ + "IMUX13", + "INT_INTERFACE_IMUX13" + ], + [ + "IMUX18", + "INT_INTERFACE_IMUX18" + ], + [ + "EE4A2", + "INT_INTERFACE_EE4A2" + ], + [ + "IMUX4", + "INT_INTERFACE_IMUX4" + ], + [ + "LOGIC_OUTS5", + "INT_INTERFACE_LOGIC_OUTS5" + ], + [ + "LH11", + "INT_INTERFACE_LH11" + ], + [ + "WW4C2", + "INT_INTERFACE_WW4C2" + ], + [ + "NW2END2", + "INT_INTERFACE_NW2A2" + ], + [ + "WW4END1", + "INT_INTERFACE_WW4END1" + ], + [ + "EE2BEG1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "LH9", + "INT_INTERFACE_LH9" + ], + [ + "WR1END0", + "INT_INTERFACE_WR1END0" + ], + [ + "SE6E2", + "INT_INTERFACE_SE4C2" + ], + [ + "LOGIC_OUTS0", + "INT_INTERFACE_LOGIC_OUTS0" + ], + [ + "EE4A1", + "INT_INTERFACE_EE4A1" + ], + [ + "LOGIC_OUTS11", + "INT_INTERFACE_LOGIC_OUTS11" + ], + [ + "INT_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "WW4A3", + "INT_INTERFACE_WW4A3" + ], + [ + "INT_PHASER_TO_IO_ICLK", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "IMUX34", + "INT_INTERFACE_IMUX34" + ], + [ + "NE2A0", + "INT_INTERFACE_NE2A0" + ], + [ + "IMUX43", + "INT_INTERFACE_IMUX43" + ], + [ + "LOGIC_OUTS8", + "INT_INTERFACE_LOGIC_OUTS8" + ], + [ + "IMUX11", + "INT_INTERFACE_IMUX11" + ], + [ + "INT_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90" + ], + [ + "IMUX40", + "INT_INTERFACE_IMUX40" + ], + [ + "IMUX0", + "INT_INTERFACE_IMUX0" + ], + [ + "SE6BEG2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK0", + "INT_INTERFACE_CLK0" + ], + [ + "NE2A2", + "INT_INTERFACE_NE2A2" + ], + [ + "EE4B2", + "INT_INTERFACE_EE4B2" + ], + [ + "WW4END2", + "INT_INTERFACE_WW4END2" + ], + [ + "IMUX46", + "INT_INTERFACE_IMUX46" + ], + [ + "EL1BEG3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "IMUX30", + "INT_INTERFACE_IMUX30" + ], + [ + "LOGIC_OUTS1", + "INT_INTERFACE_LOGIC_OUTS1" + ], + [ + "NW2END1", + "INT_INTERFACE_NW2A1" + ], + [ + "WR1END2", + "INT_INTERFACE_WR1END2" + ], + [ + "WW4END3", + "INT_INTERFACE_WW4END3" + ], + [ + "IMUX38", + "INT_INTERFACE_IMUX38" + ], + [ + "IMUX39", + "INT_INTERFACE_IMUX39" + ], + [ + "IMUX10", + "INT_INTERFACE_IMUX10" + ], + [ + "EE4B1", + "INT_INTERFACE_EE4B1" + ], + [ + "WW4B3", + "INT_INTERFACE_WW4B3" + ], + [ + "WW2A1", + "INT_INTERFACE_WW2A1" + ], + [ + "WW4END0", + "INT_INTERFACE_WW4END0" + ], + [ + "EE4BEG2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "SW6A0", + "INT_INTERFACE_SW4A0" + ], + [ + "ER1BEG3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "NE6BEG2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "SW2END1", + "INT_INTERFACE_SW2A1" + ], + [ + "CTRL0", + "INT_INTERFACE_CTRL0" + ], + [ + "BYP5", + "INT_INTERFACE_BYP5" + ], + [ + "IMUX17", + "INT_INTERFACE_IMUX17" + ], + [ + "LOGIC_OUTS18", + "INT_INTERFACE_LOGIC_OUTS18" + ], + [ + "WW2END2", + "INT_INTERFACE_WW2END2" + ], + [ + "WW2A2", + "INT_INTERFACE_WW2A2" + ], + [ + "FAN7", + "INT_INTERFACE_FAN7" + ], + [ + "LOGIC_OUTS2", + "INT_INTERFACE_LOGIC_OUTS2" + ], + [ + "IMUX31", + "INT_INTERFACE_IMUX31" + ], + [ + "SW2END0", + "INT_INTERFACE_SW2A0" + ], + [ + "SW6END2", + "INT_INTERFACE_SW4END2" + ], + [ + "SW2END3", + "INT_INTERFACE_SW2A3" + ], + [ + "LH12", + "INT_INTERFACE_LH12" + ], + [ + "LOGIC_OUTS22", + "INT_INTERFACE_LOGIC_OUTS22" + ], + [ + "LOGIC_OUTS6", + "INT_INTERFACE_LOGIC_OUTS6" + ], + [ + "BYP1", + "INT_INTERFACE_BYP1" + ], + [ + "NW6END3", + "INT_INTERFACE_NW4END3" + ], + [ + "IMUX36", + "INT_INTERFACE_IMUX36" + ], + [ + "NE6BEG1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "WW4A2", + "INT_INTERFACE_WW4A2" + ], + [ + "NE6E1", + "INT_INTERFACE_NE4C1" + ], + [ + "EE2BEG3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "WW2END1", + "INT_INTERFACE_WW2END1" + ], + [ + "EE4C0", + "INT_INTERFACE_EE4C0" + ], + [ + "LOGIC_OUTS10", + "INT_INTERFACE_LOGIC_OUTS10" + ], + [ + "EE4A0", + "INT_INTERFACE_EE4A0" + ], + [ + "EE2BEG2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "LH2", + "INT_INTERFACE_LH2" + ], + [ + "IMUX37", + "INT_INTERFACE_IMUX37" + ], + [ + "INT_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "LOGIC_OUTS15", + "INT_INTERFACE_LOGIC_OUTS15" + ], + [ + "BYP0", + "INT_INTERFACE_BYP0" + ], + [ + "WW4C1", + "INT_INTERFACE_WW4C1" + ], + [ + "BYP4", + "INT_INTERFACE_BYP4" + ], + [ + "LH10", + "INT_INTERFACE_LH10" + ], + [ + "LOGIC_OUTS20", + "INT_INTERFACE_LOGIC_OUTS20" + ], + [ + "MONITOR_P", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK1", + "INT_INTERFACE_CLK1" + ], + [ + "IMUX16", + "INT_INTERFACE_IMUX16" + ], + [ + "EE4C2", + "INT_INTERFACE_EE4C2" + ], + [ + "IMUX44", + "INT_INTERFACE_IMUX44" + ], + [ + "EL1BEG2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "NE2A1", + "INT_INTERFACE_NE2A1" + ], + [ + "LH1", + "INT_INTERFACE_LH1" + ], + [ + "WL1END2", + "INT_INTERFACE_WL1END2" + ], + [ + "EE4A3", + "INT_INTERFACE_EE4A3" + ], + [ + "WW4C0", + "INT_INTERFACE_WW4C0" + ], + [ + "BYP7", + "INT_INTERFACE_BYP7" + ], + [ + "NW2END0", + "INT_INTERFACE_NW2A0" + ], + [ + "INT_PHASER_TO_IO_OCLK", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "LOGIC_OUTS14", + "INT_INTERFACE_LOGIC_OUTS14" + ], + [ + "IMUX33", + "INT_INTERFACE_IMUX33" + ], + [ + "EE4B3", + "INT_INTERFACE_EE4B3" + ], + [ + "SW6A3", + "INT_INTERFACE_SW4A3" + ], + [ + "WW4B1", + "INT_INTERFACE_WW4B1" + ], + [ + "WW2END0", + "INT_INTERFACE_WW2END0" + ], + [ + "MONITOR_N", + "INT_INTERFACE_MONITOR_N" + ], + [ + "SW6END0", + "INT_INTERFACE_SW4END0" + ], + [ + "SE6BEG1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "WR1END3", + "INT_INTERFACE_WR1END3" + ], + [ + "EE4C1", + "INT_INTERFACE_EE4C1" + ], + [ + "WW2END3", + "INT_INTERFACE_WW2END3" + ], + [ + "IMUX45", + "INT_INTERFACE_IMUX45" + ], + [ + "LH7", + "INT_INTERFACE_LH7" + ], + [ + "LH3", + "INT_INTERFACE_LH3" + ], + [ + "IMUX8", + "INT_INTERFACE_IMUX8" + ], + [ + "IMUX23", + "INT_INTERFACE_IMUX23" + ], + [ + "NW6A3", + "INT_INTERFACE_NW4A3" + ], + [ + "NE6BEG0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "NW6A0", + "INT_INTERFACE_NW4A0" + ], + [ + "EE4BEG0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "LOGIC_OUTS16", + "INT_INTERFACE_LOGIC_OUTS16" + ], + [ + "IMUX26", + "INT_INTERFACE_IMUX26" + ], + [ + "EE4B0", + "INT_INTERFACE_EE4B0" + ], + [ + "INT_DQS_IOTOPHASER", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "IMUX35", + "INT_INTERFACE_IMUX35" + ], + [ + "BYP6", + "INT_INTERFACE_BYP6" + ], + [ + "ER1BEG2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "WL1END3", + "INT_INTERFACE_WL1END3" + ], + [ + "SW6END1", + "INT_INTERFACE_SW4END1" + ], + [ + "SE2A3", + "INT_INTERFACE_SE2A3" + ], + [ + "WW4A1", + "INT_INTERFACE_WW4A1" + ], + [ + "LH8", + "INT_INTERFACE_LH8" + ], + [ + "NW6END0", + "INT_INTERFACE_NW4END0" + ], + [ + "FAN5", + "INT_INTERFACE_FAN5" + ], + [ + "LH5", + "INT_INTERFACE_LH5" + ], + [ + "NE2A3", + "INT_INTERFACE_NE2A3" + ], + [ + "IMUX9", + "INT_INTERFACE_IMUX9" + ], + [ + "NW6END1", + "INT_INTERFACE_NW4END1" + ], + [ + "SW6END3", + "INT_INTERFACE_SW4END3" + ], + [ + "NE6E3", + "INT_INTERFACE_NE4C3" + ], + [ + "IMUX24", + "INT_INTERFACE_IMUX24" + ], + [ + "ER1BEG1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "FAN3", + "INT_INTERFACE_FAN3" + ], + [ + "SE6BEG0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "SW6A2", + "INT_INTERFACE_SW4A2" + ], + [ + "NW2END3", + "INT_INTERFACE_NW2A3" + ], + [ + "IMUX42", + "INT_INTERFACE_IMUX42" + ], + [ + "IMUX2", + "INT_INTERFACE_IMUX2" + ], + [ + "FAN6", + "INT_INTERFACE_FAN6" + ], + [ + "SW6A1", + "INT_INTERFACE_SW4A1" + ], + [ + "LOGIC_OUTS17", + "INT_INTERFACE_LOGIC_OUTS17" + ], + [ + "IMUX27", + "INT_INTERFACE_IMUX27" + ], + [ + "SE6E3", + "INT_INTERFACE_SE4C3" + ], + [ + "IMUX15", + "INT_INTERFACE_IMUX15" + ], + [ + "WW4B2", + "INT_INTERFACE_WW4B2" + ], + [ + "EL1BEG1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "WL1END0", + "INT_INTERFACE_WL1END0" + ], + [ + "FAN4", + "INT_INTERFACE_FAN4" + ], + [ + "BYP2", + "INT_INTERFACE_BYP2" + ], + [ + "LOGIC_OUTS19", + "INT_INTERFACE_LOGIC_OUTS19" + ], + [ + "LOGIC_OUTS21", + "INT_INTERFACE_LOGIC_OUTS21" + ], + [ + "EE2A0", + "INT_INTERFACE_EE2A0" + ], + [ + "IMUX20", + "INT_INTERFACE_IMUX20" + ], + [ + "IMUX29", + "INT_INTERFACE_IMUX29" + ], + [ + "EE2A3", + "INT_INTERFACE_EE2A3" + ], + [ + "FAN1", + "INT_INTERFACE_FAN1" + ], + [ + "EE4BEG3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "IMUX22", + "INT_INTERFACE_IMUX22" + ], + [ + "CTRL1", + "INT_INTERFACE_CTRL1" + ], + [ + "IMUX25", + "INT_INTERFACE_IMUX25" + ], + [ + "WW4A0", + "INT_INTERFACE_WW4A0" + ], + [ + "EE2A2", + "INT_INTERFACE_EE2A2" + ], + [ + "IMUX28", + "INT_INTERFACE_IMUX28" + ], + [ + "IMUX32", + "INT_INTERFACE_IMUX32" + ], + [ + "WW4B0", + "INT_INTERFACE_WW4B0" + ], + [ + "IMUX7", + "INT_INTERFACE_IMUX7" + ], + [ + "LOGIC_OUTS3", + "INT_INTERFACE_LOGIC_OUTS3" + ], + [ + "LOGIC_OUTS7", + "INT_INTERFACE_LOGIC_OUTS7" + ], + [ + "LOGIC_OUTS9", + "INT_INTERFACE_LOGIC_OUTS9" + ], + [ + "LH4", + "INT_INTERFACE_LH4" + ], + [ + "WW4C3", + "INT_INTERFACE_WW4C3" + ], + [ + "IMUX21", + "INT_INTERFACE_IMUX21" + ], + [ + "NW6A1", + "INT_INTERFACE_NW4A1" + ], + [ + "IMUX12", + "INT_INTERFACE_IMUX12" + ], + [ + "WW2A0", + "INT_INTERFACE_WW2A0" + ] + ], + "tile_types": [ + "INT_R", + "IO_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CMT_TOP_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_LH2_1", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH11_1", + "VBRK_LH11" + ], + [ + "CMT_TOP_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH10_1", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_LH8_1", + "VBRK_LH8" + ], + [ + "CMT_TOP_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH3_1", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH4_1", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH5_1", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_MONITOR_P_1", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_1", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_LH6_1", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH1_1", + "VBRK_LH1" + ], + [ + "CMT_TOP_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_LH7_1", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_MONITOR_N_1", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH9_1", + "VBRK_LH9" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "BRAM_WL1END3_0", + "CLBLM_WL1END3" + ], + [ + "BRAM_WW2END0_0", + "CLBLM_WW2END0" + ], + [ + "BRAM_NE4BEG3_0", + "CLBLM_NE4BEG3" + ], + [ + "BRAM_EE4C3_0", + "CLBLM_EE4C3" + ], + [ + "BRAM_SW4END2_0", + "CLBLM_SW4END2" + ], + [ + "BRAM_WW4A1_0", + "CLBLM_WW4A1" + ], + [ + "BRAM_NW4END1_0", + "CLBLM_NW4END1" + ], + [ + "BRAM_WW2A3_0", + "CLBLM_WW2A3" + ], + [ + "BRAM_EE2A1_0", + "CLBLM_EE2A1" + ], + [ + "BRAM_EE4A2_0", + "CLBLM_EE4A2" + ], + [ + "BRAM_EE4BEG3_0", + "CLBLM_EE4BEG3" + ], + [ + "BRAM_LH7_0", + "CLBLM_LH7" + ], + [ + "BRAM_LH10_0", + "CLBLM_LH10" + ], + [ + "BRAM_NE2A3_0", + "CLBLM_NE2A3" + ], + [ + "BRAM_NE2A0_0", + "CLBLM_NE2A0" + ], + [ + "BRAM_SW2A3_0", + "CLBLM_SW2A3" + ], + [ + "BRAM_ER1BEG2_0", + "CLBLM_ER1BEG2" + ], + [ + "BRAM_NW2A2_0", + "CLBLM_NW2A2" + ], + [ + "BRAM_SW4END1_0", + "CLBLM_SW4END1" + ], + [ + "BRAM_SW2A0_0", + "CLBLM_SW2A0" + ], + [ + "BRAM_SE2A0_0", + "CLBLM_SE2A0" + ], + [ + "BRAM_WW2END2_0", + "CLBLM_WW2END2" + ], + [ + "BRAM_SE4C2_0", + "CLBLM_SE4C2" + ], + [ + "BRAM_LH3_0", + "CLBLM_LH3" + ], + [ + "BRAM_NW4A1_0", + "CLBLM_NW4A1" + ], + [ + "BRAM_EE2BEG0_0", + "CLBLM_EE2BEG0" + ], + [ + "BRAM_WW4B1_0", + "CLBLM_WW4B1" + ], + [ + "BRAM_EE4BEG1_0", + "CLBLM_EE4BEG1" + ], + [ + "BRAM_ER1BEG1_0", + "CLBLM_ER1BEG1" + ], + [ + "BRAM_WR1END1_0", + "CLBLM_WR1END1" + ], + [ + "BRAM_EE4A0_0", + "CLBLM_EE4A0" + ], + [ + "BRAM_NW4END0_0", + "CLBLM_NW4END0" + ], + [ + "BRAM_WW2END3_0", + "CLBLM_WW2END3" + ], + [ + "BRAM_EE4A3_0", + "CLBLM_EE4A3" + ], + [ + "BRAM_SW2A1_0", + "CLBLM_SW2A1" + ], + [ + "BRAM_WW4END0_0", + "CLBLM_WW4END0" + ], + [ + "BRAM_ER1BEG0_0", + "CLBLM_ER1BEG0" + ], + [ + "BRAM_WW4B0_0", + "CLBLM_WW4B0" + ], + [ + "BRAM_SW4A0_0", + "CLBLM_SW4A0" + ], + [ + "BRAM_MONITOR_P_0", + "CLBLM_MONITOR_P" + ], + [ + "BRAM_SE4BEG3_0", + "CLBLM_SE4BEG3" + ], + [ + "BRAM_SW4A1_0", + "CLBLM_SW4A1" + ], + [ + "BRAM_EE4B0_0", + "CLBLM_EE4B0" + ], + [ + "BRAM_WR1END0_0", + "CLBLM_WR1END0" + ], + [ + "BRAM_NE4C2_0", + "CLBLM_NE4C2" + ], + [ + "BRAM_WW4END3_0", + "CLBLM_WW4END3" + ], + [ + "BRAM_EE4B3_0", + "CLBLM_EE4B3" + ], + [ + "BRAM_EE4C0_0", + "CLBLM_EE4C0" + ], + [ + "BRAM_WW4A3_0", + "CLBLM_WW4A3" + ], + [ + "BRAM_EE4BEG0_0", + "CLBLM_EE4BEG0" + ], + [ + "BRAM_EE2A0_0", + "CLBLM_EE2A0" + ], + [ + "BRAM_WW2A1_0", + "CLBLM_WW2A1" + ], + [ + "BRAM_NE4BEG1_0", + "CLBLM_NE4BEG1" + ], + [ + "BRAM_NE4C1_0", + "CLBLM_NE4C1" + ], + [ + "BRAM_EE4B2_0", + "CLBLM_EE4B2" + ], + [ + "BRAM_WR1END3_0", + "CLBLM_WR1END3" + ], + [ + "BRAM_NW4END3_0", + "CLBLM_NW4END3" + ], + [ + "BRAM_EE2A2_0", + "CLBLM_EE2A2" + ], + [ + "BRAM_WW2A0_0", + "CLBLM_WW2A0" + ], + [ + "BRAM_SW4END3_0", + "CLBLM_SW4END3" + ], + [ + "BRAM_SE4C1_0", + "CLBLM_SE4C1" + ], + [ + "BRAM_NW4A3_0", + "CLBLM_NW4A3" + ], + [ + "BRAM_SE2A3_0", + "CLBLM_SE2A3" + ], + [ + "BRAM_WW4C3_0", + "CLBLM_WW4C3" + ], + [ + "BRAM_NE4BEG2_0", + "CLBLM_NE4BEG2" + ], + [ + "BRAM_SE4BEG1_0", + "CLBLM_SE4BEG1" + ], + [ + "BRAM_EL1BEG1_0", + "CLBLM_EL1BEG1" + ], + [ + "BRAM_WW4B2_0", + "CLBLM_WW4B2" + ], + [ + "BRAM_SW2A2_0", + "CLBLM_SW2A2" + ], + [ + "BRAM_LH6_0", + "CLBLM_LH6" + ], + [ + "BRAM_EE4A1_0", + "CLBLM_EE4A1" + ], + [ + "BRAM_EL1BEG0_0", + "CLBLM_EL1BEG0" + ], + [ + "BRAM_LH8_0", + "CLBLM_LH8" + ], + [ + "BRAM_EE4B1_0", + "CLBLM_EE4B1" + ], + [ + "BRAM_WW4A0_0", + "CLBLM_WW4A0" + ], + [ + "BRAM_WW4B3_0", + "CLBLM_WW4B3" + ], + [ + "BRAM_WW4END2_0", + "CLBLM_WW4END2" + ], + [ + "BRAM_LH12_0", + "CLBLM_LH12" + ], + [ + "BRAM_SE4C0_0", + "CLBLM_SE4C0" + ], + [ + "BRAM_SE2A2_0", + "CLBLM_SE2A2" + ], + [ + "BRAM_LH1_0", + "CLBLM_LH1" + ], + [ + "BRAM_LH9_0", + "CLBLM_LH9" + ], + [ + "BRAM_WL1END2_0", + "CLBLM_WL1END2" + ], + [ + "BRAM_NW2A0_0", + "CLBLM_NW2A0" + ], + [ + "BRAM_EE4C2_0", + "CLBLM_EE4C2" + ], + [ + "BRAM_EE4BEG2_0", + "CLBLM_EE4BEG2" + ], + [ + "BRAM_ER1BEG3_0", + "CLBLM_ER1BEG3" + ], + [ + "BRAM_NE4BEG0_0", + "CLBLM_NE4BEG0" + ], + [ + "BRAM_NE2A1_0", + "CLBLM_NE2A1" + ], + [ + "BRAM_LH2_0", + "CLBLM_LH2" + ], + [ + "BRAM_WW4C0_0", + "CLBLM_WW4C0" + ], + [ + "BRAM_SW4A3_0", + "CLBLM_SW4A3" + ], + [ + "BRAM_WW2A2_0", + "CLBLM_WW2A2" + ], + [ + "BRAM_NW2A3_0", + "CLBLM_NW2A3" + ], + [ + "BRAM_NE2A2_0", + "CLBLM_NE2A2" + ], + [ + "BRAM_LH5_0", + "CLBLM_LH5" + ], + [ + "BRAM_NW4A2_0", + "CLBLM_NW4A2" + ], + [ + "BRAM_EE2BEG2_0", + "CLBLM_EE2BEG2" + ], + [ + "BRAM_SE4C3_0", + "CLBLM_SE4C3" + ], + [ + "BRAM_EE2BEG3_0", + "CLBLM_EE2BEG3" + ], + [ + "BRAM_EE2A3_0", + "CLBLM_EE2A3" + ], + [ + "BRAM_SE4BEG0_0", + "CLBLM_SE4BEG0" + ], + [ + "BRAM_WW4C1_0", + "CLBLM_WW4C1" + ], + [ + "BRAM_SE2A1_0", + "CLBLM_SE2A1" + ], + [ + "BRAM_SW4A2_0", + "CLBLM_SW4A2" + ], + [ + "BRAM_SW4END0_0", + "CLBLM_SW4END0" + ], + [ + "BRAM_WR1END2_0", + "CLBLM_WR1END2" + ], + [ + "BRAM_WL1END0_0", + "CLBLM_WL1END0" + ], + [ + "BRAM_EL1BEG3_0", + "CLBLM_EL1BEG3" + ], + [ + "BRAM_WW4A2_0", + "CLBLM_WW4A2" + ], + [ + "BRAM_MONITOR_N_0", + "CLBLM_MONITOR_N" + ], + [ + "BRAM_EE2BEG1_0", + "CLBLM_EE2BEG1" + ], + [ + "BRAM_LH11_0", + "CLBLM_LH11" + ], + [ + "BRAM_WL1END1_0", + "CLBLM_WL1END1" + ], + [ + "BRAM_NE4C0_0", + "CLBLM_NE4C0" + ], + [ + "BRAM_NW4END2_0", + "CLBLM_NW4END2" + ], + [ + "BRAM_LH4_0", + "CLBLM_LH4" + ], + [ + "BRAM_EE4C1_0", + "CLBLM_EE4C1" + ], + [ + "BRAM_NW2A1_0", + "CLBLM_NW2A1" + ], + [ + "BRAM_WW2END1_0", + "CLBLM_WW2END1" + ], + [ + "BRAM_WW4END1_0", + "CLBLM_WW4END1" + ], + [ + "BRAM_WW4C2_0", + "CLBLM_WW4C2" + ], + [ + "BRAM_NE4C3_0", + "CLBLM_NE4C3" + ], + [ + "BRAM_NW4A0_0", + "CLBLM_NW4A0" + ], + [ + "BRAM_SE4BEG2_0", + "CLBLM_SE4BEG2" + ], + [ + "BRAM_EL1BEG2_0", + "CLBLM_EL1BEG2" + ] + ], + "tile_types": [ + "BRAM_L", + "CLBLM_R" + ] + }, + { + "grid_deltas": [ + -1, + 8 + ], + "wire_pairs": [ + [ + "CFG_CENTER_NE2A3_3", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_EL1BEG3_3", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_NW4A1_3", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_EE4BEG3_3", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_NE2A0_3", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EE4BEG1_3", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_LH3_3", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_WR1END3_3", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_WW4B3_3", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_ER1BEG3_3", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW4END0_3", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EL1BEG2_3", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_SW4END0_3", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_NE4BEG2_3", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_ER1BEG0_3", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_EE4C1_3", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE4A0_3", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_LH2_3", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_EE4B1_3", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EE2A0_3", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_EE4A1_3", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_SE4BEG2_3", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW4END1_3", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_LH7_3", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4A0_3", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SW2A0_3", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WL1END1_3", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_SW4A0_3", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE2BEG2_3", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NE4C0_3", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_NE4C3_3", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_EE4A2_3", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SE4C3_3", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WW4A1_3", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_LH9_3", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NE2A2_3", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE4BEG0_3", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WW2END3_3", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_NE4C1_3", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW4A2_3", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE2A3_3", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW2A2_3", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4C2_3", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW4C0_3", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_SW4A2_3", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NW4END3_3", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_LH11_3", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW2END1_3", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE4B0_3", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_SE2A0_3", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_LH6_3", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WW4C2_3", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_EE2BEG0_3", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_SW4END1_3", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EE4B2_3", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_WW4C1_3", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SE4C2_3", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_LH8_3", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_NE4BEG0_3", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NW4A3_3", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_NW2A2_3", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_NW4END1_3", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NW2A0_3", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WR1END0_3", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_SE2A1_3", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_SW2A1_3", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4C2_3", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NE2A1_3", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_ER1BEG2_3", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_EL1BEG0_3", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_ER1BEG1_3", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SE4C0_3", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_LH4_3", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE2BEG3_3", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_WW4B2_3", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_LH1_3", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_SE4BEG3_3", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_WW2END2_3", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_WW4A3_3", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_SW4END2_3", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SW2A3_3", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_EE4C0_3", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_SE4BEG0_3", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_EE2A2_3", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_SW4A1_3", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NW2A1_3", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SW4A3_3", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE4B3_3", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NE4BEG3_3", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_SE2A3_3", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_NE4BEG1_3", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_EE2BEG1_3", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_LH12_3", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW4END2_3", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_WW2A1_3", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WL1END0_3", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SE4BEG1_3", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_NW4END2_3", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_NW4END0_3", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_WW4END3_3", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_SE2A2_3", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_WR1END2_3", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_WL1END3_3", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_SE4C1_3", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_LH5_3", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_LH10_3", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_NW4A0_3", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_EE4C3_3", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_SW4END3_3", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_SW2A2_3", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WW2A0_3", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_EL1BEG1_3", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW2A3_3", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WR1END1_3", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WW4C3_3", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE4A3_3", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_NW2A3_3", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_EE4BEG2_3", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WW4B0_3", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_NW4A2_3", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WL1END2_3", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_EE2A1_3", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_WW4B1_3", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW2END0_3", + "INT_FEEDTHRU_2_WW2END0" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -5 + ], + "wire_pairs": [ + [ + "CMT_FIFO_LH1_11", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_EE2BEG1_11", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_EE4B2_11", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_EE4BEG3_11", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_NE4BEG0_11", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_NE4BEG3_11", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_SE4BEG1_11", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX18_11", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_L_IMUX42_11", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_IMUX16_11", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_11", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "CMT_FIFO_L_IMUX1_11", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_11", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "CMT_FIFO_WL1END1_11", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_EE4B3_11", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_SE2A0_11", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_EE4C1_11", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_NE4BEG2_11", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_11", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "CMT_FIFO_WW4C3_11", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_L_IMUX0_11", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_L_IMUX17_11", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_L_IMUX34_11", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_WR1END2_11", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_L_IMUX7_11", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_SW4A1_11", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_EE2BEG2_11", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_EE4C3_11", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_L_BYP6_11", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_WL1END2_11", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_EE4BEG2_11", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_WW4B2_11", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_EE2BEG3_11", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_L_IMUX44_11", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_CTRL0_11", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_SW4A2_11", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_11", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "CMT_FIFO_EE4BEG1_11", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_LH10_11", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_LH5_11", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_WL1END3_11", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_SW2A1_11", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_L_BYP4_11", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_WW4B3_11", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_L_IMUX35_11", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_EE4BEG0_11", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_WW4C1_11", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_L_FAN6_11", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_EE2A1_11", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_WW4B1_11", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_EL1BEG2_11", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_L_BYP0_11", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_SE2A2_11", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_NW2A1_11", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_EE4B1_11", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_WW2END2_11", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_ER1BEG2_11", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_IMUX46_11", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_SW4A3_11", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_EE4C0_11", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_LH4_11", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_L_IMUX9_11", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX23_11", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_LH9_11", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_LH11_11", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_NW2A0_11", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_WW2A3_11", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_NE2A2_11", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_L_IMUX28_11", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_WW2A2_11", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_L_IMUX24_11", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_NW4A1_11", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_WW4C0_11", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_NE2A0_11", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_IMUX26_11", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_IMUX22_11", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_WW2END3_11", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_LH2_11", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_EE4A1_11", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_EE2BEG0_11", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_IMUX43_11", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_NW4END2_11", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_EE4A0_11", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_SE4C2_11", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_L_CTRL1_11", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_NE4C2_11", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_L_FAN2_11", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_WW4B0_11", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_11", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_11", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "CMT_FIFO_LH6_11", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_EE2A2_11", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_EL1BEG0_11", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_L_IMUX37_11", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_SE4BEG2_11", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX21_11", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_L_BYP5_11", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_SW4A0_11", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_NW4END3_11", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_L_IMUX4_11", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_L_IMUX2_11", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_WW4A3_11", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_11", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "CMT_FIFO_EE2A0_11", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_FAN1_11", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_L_IMUX29_11", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_WW4A0_11", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_SE2A3_11", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_L_IMUX14_11", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_L_CLK0_11", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_WW2END1_11", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_L_IMUX12_11", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_WW4C2_11", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_SW4END2_11", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_LH8_11", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_IMUX5_11", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_L_BYP2_11", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_L_IMUX38_11", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_WW4END1_11", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_WW4A1_11", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_NE2A1_11", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_WW2A1_11", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_L_IMUX10_11", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_SE4C0_11", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_L_FAN0_11", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_SW4END0_11", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_NE4C1_11", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_11", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "CMT_FIFO_NW4A0_11", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_L_IMUX11_11", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_NW4END1_11", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_11", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "CMT_FIFO_L_IMUX45_11", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_L_IMUX30_11", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_L_FAN4_11", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_L_FAN7_11", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_ER1BEG3_11", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_L_CLK1_11", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_L_FAN3_11", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_L_IMUX13_11", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_EL1BEG1_11", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_L_IMUX3_11", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_L_IMUX8_11", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_IMUX33_11", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_WL1END0_11", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_WW4END2_11", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_L_BYP7_11", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_EL1BEG3_11", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_L_IMUX47_11", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_SW2A3_11", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_ER1BEG0_11", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_NE4C0_11", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_ER1BEG1_11", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_SE4BEG3_11", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_11", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "CMT_FIFO_L_FAN5_11", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_SW2A0_11", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_WW2A0_11", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_L_BYP3_11", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_WW4A2_11", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_EE4C2_11", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_WW4END3_11", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_11", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_11", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "CMT_FIFO_NW4A2_11", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_WR1END3_11", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_NW2A3_11", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_LH12_11", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_SW2A2_11", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_EE4A3_11", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_IMUX40_11", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_NW4END0_11", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_L_IMUX41_11", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_LH7_11", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_L_IMUX15_11", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_SE4C1_11", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_WR1END0_11", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_NE2A3_11", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_NW2A2_11", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_L_IMUX25_11", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_WW2END0_11", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_SW4END3_11", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_L_IMUX31_11", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_EE4B0_11", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_11", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_11", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "CMT_FIFO_SE4C3_11", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_SE4BEG0_11", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_NE4C3_11", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_11", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "CMT_FIFO_WW4END0_11", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_IMUX19_11", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_L_IMUX32_11", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_11", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "CMT_FIFO_L_IMUX39_11", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_NW4A3_11", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_NE4BEG1_11", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX36_11", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_11", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_11", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "CMT_FIFO_EE4A2_11", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_IMUX27_11", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_WR1END1_11", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_L_BYP1_11", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_SW4END1_11", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_SE2A1_11", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_L_IMUX6_11", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_EE2A3_11", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_L_IMUX20_11", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_11", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "CMT_FIFO_LH3_11", + "INT_INTERFACE_LH3" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "IOI_CLK1_1", + "TERM_INT_CLK1" + ], + [ + "IOI_IMUX29_1", + "TERM_INT_IMUX29" + ], + [ + "IOI_BYP0_1", + "TERM_INT_BYP0" + ], + [ + "IOI_IMUX44_1", + "TERM_INT_IMUX44" + ], + [ + "IOI_IMUX28_1", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX5_1", + "TERM_INT_IMUX5" + ], + [ + "IOI_LOGIC_OUTS0_1", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_IMUX30_1", + "TERM_INT_IMUX30" + ], + [ + "IOI_CTRL1_1", + "TERM_INT_CTRL1" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_PHASER_TO_IO_ICLK_0", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_IMUX43_1", + "TERM_INT_IMUX43" + ], + [ + "IOI_IMUX23_1", + "TERM_INT_IMUX23" + ], + [ + "IOI_IMUX18_1", + "TERM_INT_IMUX18" + ], + [ + "IOI_IMUX37_1", + "TERM_INT_IMUX37" + ], + [ + "IOI_IMUX33_1", + "TERM_INT_IMUX33" + ], + [ + "IOI_LOGIC_OUTS7_1", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_LOGIC_OUTS18_1", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_BYP4_1", + "TERM_INT_BYP4" + ], + [ + "IOI_IMUX47_1", + "TERM_INT_IMUX47" + ], + [ + "IOI_LOGIC_OUTS1_1", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX34_1", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX39_1", + "TERM_INT_IMUX39" + ], + [ + "IOI_BYP1_1", + "TERM_INT_BYP1" + ], + [ + "IOI_FAN6_1", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX38_1", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX3_1", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX21_1", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX22_1", + "TERM_INT_IMUX22" + ], + [ + "IOI_PHASER_TO_IO_OCLK_0", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_IMUX26_1", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX11_1", + "TERM_INT_IMUX11" + ], + [ + "IOI_CLK0_1", + "TERM_INT_CLK0" + ], + [ + "IOI_LOGIC_OUTS20_1", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_BYP2_1", + "TERM_INT_BYP2" + ], + [ + "IOI_IMUX8_1", + "TERM_INT_IMUX8" + ], + [ + "IOI_IMUX19_1", + "TERM_INT_IMUX19" + ], + [ + "IOI_LOGIC_OUTS2_1", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_FAN2_1", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX14_1", + "TERM_INT_IMUX14" + ], + [ + "IOI_IMUX7_1", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX40_1", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX25_1", + "TERM_INT_IMUX25" + ], + [ + "IOI_LOGIC_OUTS16_1", + "TERM_INT_LOGIC_OUTS_L_B16" + ], + [ + "IOI_IMUX15_1", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX24_1", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX6_1", + "TERM_INT_IMUX6" + ], + [ + "IOI_IMUX4_1", + "TERM_INT_IMUX4" + ], + [ + "IOI_LOGIC_OUTS15_1", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX41_1", + "TERM_INT_IMUX41" + ], + [ + "IOI_BYP6_1", + "TERM_INT_BYP6" + ], + [ + "IOI_FAN4_1", + "TERM_INT_FAN4" + ], + [ + "IOI_FAN1_1", + "TERM_INT_FAN1" + ], + [ + "IOI_IMUX32_1", + "TERM_INT_IMUX32" + ], + [ + "IOI_IMUX45_1", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX20_1", + "TERM_INT_IMUX20" + ], + [ + "IOI_IMUX46_1", + "TERM_INT_IMUX46" + ], + [ + "IOI_IMUX31_1", + "TERM_INT_IMUX31" + ], + [ + "IOI_FAN0_1", + "TERM_INT_FAN0" + ], + [ + "IOI_LOGIC_OUTS13_1", + "TERM_INT_LOGIC_OUTS_L_B13" + ], + [ + "IOI_IMUX35_1", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP7_1", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_1", + "TERM_INT_IMUX2" + ], + [ + "IOI_IMUX9_1", + "TERM_INT_IMUX9" + ], + [ + "IOI_BYP5_1", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS19_1", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_FAN3_1", + "TERM_INT_FAN3" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_IMUX36_1", + "TERM_INT_IMUX36" + ], + [ + "IOI_LOGIC_OUTS22_1", + "TERM_INT_LOGIC_OUTS_L_B22" + ], + [ + "IOI_BLOCK_OUTS2_1", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "IOI_FAN7_1", + "TERM_INT_FAN7" + ], + [ + "IOI_LOGIC_OUTS5_1", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_LOGIC_OUTS11_1", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_IMUX27_1", + "TERM_INT_IMUX27" + ], + [ + "IOI_LOGIC_OUTS8_1", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_IMUX12_1", + "TERM_INT_IMUX12" + ], + [ + "IOI_LOGIC_OUTS3_1", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_IMUX16_1", + "TERM_INT_IMUX16" + ], + [ + "IOI_LOGIC_OUTS14_1", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_LOGIC_OUTS9_1", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_FAN5_1", + "TERM_INT_FAN5" + ], + [ + "IOI_IMUX1_1", + "TERM_INT_IMUX1" + ], + [ + "IOI_IMUX13_1", + "TERM_INT_IMUX13" + ], + [ + "IOI_IMUX10_1", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX42_1", + "TERM_INT_IMUX42" + ], + [ + "IOI_BLOCK_OUTS0_1", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_CTRL0_1", + "TERM_INT_CTRL0" + ], + [ + "IOI_LOGIC_OUTS23_1", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_IMUX17_1", + "TERM_INT_IMUX17" + ], + [ + "IOI_BYP3_1", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX0_1", + "TERM_INT_IMUX0" + ], + [ + "IOI_LOGIC_OUTS10_1", + "TERM_INT_LOGIC_OUTS_L_B10" + ] + ], + "tile_types": [ + "LIOI3", + "L_TERM_INT" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "MONITOR_NE2A0_1", + "VFRAME_NE2A0" + ], + [ + "MONITOR_EE4A0_1", + "VFRAME_EE4A0" + ], + [ + "MONITOR_ER1BEG3_1", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_BYP3_1", + "VFRAME_BYP3" + ], + [ + "MONITOR_IMUX7_1", + "VFRAME_IMUX7" + ], + [ + "MONITOR_NW4A0_1", + "VFRAME_NW4A0" + ], + [ + "MONITOR_WW4B0_1", + "VFRAME_WW4B0" + ], + [ + "MONITOR_IMUX4_1", + "VFRAME_IMUX4" + ], + [ + "MONITOR_FAN1_1", + "VFRAME_FAN1" + ], + [ + "MONITOR_EE2A1_1", + "VFRAME_EE2A1" + ], + [ + "MONITOR_IMUX31_1", + "VFRAME_IMUX31" + ], + [ + "MONITOR_WW4B1_1", + "VFRAME_WW4B1" + ], + [ + "MONITOR_EE4C3_1", + "VFRAME_EE4C3" + ], + [ + "MONITOR_WW4END1_1", + "VFRAME_WW4END1" + ], + [ + "MONITOR_NW4A2_1", + "VFRAME_NW4A2" + ], + [ + "MONITOR_SE4C0_1", + "VFRAME_SE4C0" + ], + [ + "MONITOR_NW2A3_1", + "VFRAME_NW2A3" + ], + [ + "MONITOR_SW4END1_1", + "VFRAME_SW4END1" + ], + [ + "MONITOR_NE4BEG3_1", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_IMUX46_1", + "VFRAME_IMUX46" + ], + [ + "MONITOR_FAN5_1", + "VFRAME_FAN5" + ], + [ + "MONITOR_LH5_1", + "VFRAME_LH5" + ], + [ + "MONITOR_EL1BEG0_1", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_SE4C3_1", + "VFRAME_SE4C3" + ], + [ + "MONITOR_SW4A2_1", + "VFRAME_SW4A2" + ], + [ + "MONITOR_NE4BEG2_1", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_IMUX16_1", + "VFRAME_IMUX16" + ], + [ + "MONITOR_EL1BEG1_1", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_NE2A1_1", + "VFRAME_NE2A1" + ], + [ + "MONITOR_WR1END0_1", + "VFRAME_WR1END0" + ], + [ + "MONITOR_FAN7_1", + "VFRAME_FAN7" + ], + [ + "MONITOR_NE4BEG1_1", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_NE4BEG0_1", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_IMUX38_1", + "VFRAME_IMUX38" + ], + [ + "MONITOR_EE4A1_1", + "VFRAME_EE4A1" + ], + [ + "MONITOR_FAN3_1", + "VFRAME_FAN3" + ], + [ + "MONITOR_SE4BEG0_1", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_IMUX42_1", + "VFRAME_IMUX42" + ], + [ + "MONITOR_IMUX29_1", + "VFRAME_IMUX29" + ], + [ + "MONITOR_EE4B3_1", + "VFRAME_EE4B3" + ], + [ + "MONITOR_LH8_1", + "VFRAME_LH8" + ], + [ + "MONITOR_IMUX43_1", + "VFRAME_IMUX43" + ], + [ + "MONITOR_WW2END0_1", + "VFRAME_WW2END0" + ], + [ + "MONITOR_NE2A3_1", + "VFRAME_NE2A3" + ], + [ + "MONITOR_WW4C0_1", + "VFRAME_WW4C0" + ], + [ + "MONITOR_LH11_1", + "VFRAME_LH11" + ], + [ + "MONITOR_BYP1_1", + "VFRAME_BYP1" + ], + [ + "MONITOR_WW2END3_1", + "VFRAME_WW2END3" + ], + [ + "MONITOR_EE4BEG2_1", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_IMUX3_1", + "VFRAME_IMUX3" + ], + [ + "MONITOR_CLK0_1", + "VFRAME_CLK0" + ], + [ + "MONITOR_WR1END3_1", + "VFRAME_WR1END3" + ], + [ + "MONITOR_SW2A1_1", + "VFRAME_SW2A1" + ], + [ + "MONITOR_EE4A2_1", + "VFRAME_EE4A2" + ], + [ + "MONITOR_EE4BEG3_1", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_NW4A1_1", + "VFRAME_NW4A1" + ], + [ + "MONITOR_EL1BEG2_1", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_WW2A2_1", + "VFRAME_WW2A2" + ], + [ + "MONITOR_NE4C2_1", + "VFRAME_NE4C2" + ], + [ + "MONITOR_SE4BEG3_1", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_LH9_1", + "VFRAME_LH9" + ], + [ + "MONITOR_IMUX0_1", + "VFRAME_IMUX0" + ], + [ + "MONITOR_IMUX12_1", + "VFRAME_IMUX12" + ], + [ + "MONITOR_WL1END1_1", + "VFRAME_WL1END1" + ], + [ + "MONITOR_LH10_1", + "VFRAME_LH10" + ], + [ + "MONITOR_ER1BEG2_1", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_EE2A2_1", + "VFRAME_EE2A2" + ], + [ + "MONITOR_EE2BEG0_1", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_EE4BEG1_1", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX30_1", + "VFRAME_IMUX30" + ], + [ + "MONITOR_FAN6_1", + "VFRAME_FAN6" + ], + [ + "MONITOR_IMUX41_1", + "VFRAME_IMUX41" + ], + [ + "MONITOR_EE2BEG2_1", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_IMUX10_1", + "VFRAME_IMUX10" + ], + [ + "MONITOR_IMUX40_1", + "VFRAME_IMUX40" + ], + [ + "MONITOR_SW4A0_1", + "VFRAME_SW4A0" + ], + [ + "MONITOR_EE4B1_1", + "VFRAME_EE4B1" + ], + [ + "MONITOR_IMUX33_1", + "VFRAME_IMUX33" + ], + [ + "MONITOR_FAN0_1", + "VFRAME_FAN0" + ], + [ + "MONITOR_BYP2_1", + "VFRAME_BYP2" + ], + [ + "MONITOR_ER1BEG0_1", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_WW2A0_1", + "VFRAME_WW2A0" + ], + [ + "MONITOR_SE4C2_1", + "VFRAME_SE4C2" + ], + [ + "MONITOR_WW2A1_1", + "VFRAME_WW2A1" + ], + [ + "MONITOR_EE4B2_1", + "VFRAME_EE4B2" + ], + [ + "MONITOR_EE4B0_1", + "VFRAME_EE4B0" + ], + [ + "MONITOR_IMUX44_1", + "VFRAME_IMUX44" + ], + [ + "MONITOR_WL1END0_1", + "VFRAME_WL1END0" + ], + [ + "MONITOR_IMUX45_1", + "VFRAME_IMUX45" + ], + [ + "MONITOR_WW4B3_1", + "VFRAME_WW4B3" + ], + [ + "MONITOR_SW4END0_1", + "VFRAME_SW4END0" + ], + [ + "MONITOR_WW2A3_1", + "VFRAME_WW2A3" + ], + [ + "MONITOR_IMUX5_1", + "VFRAME_IMUX5" + ], + [ + "MONITOR_WW4A0_1", + "VFRAME_WW4A0" + ], + [ + "MONITOR_NW4END1_1", + "VFRAME_NW4END1" + ], + [ + "MONITOR_EE2BEG1_1", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_EE2BEG3_1", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_NW4END0_1", + "VFRAME_NW4END0" + ], + [ + "MONITOR_IMUX27_1", + "VFRAME_IMUX27" + ], + [ + "MONITOR_IMUX2_1", + "VFRAME_IMUX2" + ], + [ + "MONITOR_CLK1_1", + "VFRAME_CLK1" + ], + [ + "MONITOR_EE4C1_1", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX37_1", + "VFRAME_IMUX37" + ], + [ + "MONITOR_WW4A1_1", + "VFRAME_WW4A1" + ], + [ + "MONITOR_SE2A3_1", + "VFRAME_SE2A3" + ], + [ + "MONITOR_IMUX21_1", + "VFRAME_IMUX21" + ], + [ + "MONITOR_LH1_1", + "VFRAME_LH1" + ], + [ + "MONITOR_WW4C3_1", + "VFRAME_WW4C3" + ], + [ + "MONITOR_IMUX20_1", + "VFRAME_IMUX20" + ], + [ + "MONITOR_LH3_1", + "VFRAME_LH3" + ], + [ + "MONITOR_IMUX34_1", + "VFRAME_IMUX34" + ], + [ + "MONITOR_NW2A1_1", + "VFRAME_NW2A1" + ], + [ + "MONITOR_WW4END0_1", + "VFRAME_WW4END0" + ], + [ + "MONITOR_NE4C3_1", + "VFRAME_NE4C3" + ], + [ + "MONITOR_IMUX15_1", + "VFRAME_IMUX15" + ], + [ + "MONITOR_WW2END2_1", + "VFRAME_WW2END2" + ], + [ + "MONITOR_FAN2_1", + "VFRAME_FAN2" + ], + [ + "MONITOR_NW2A0_1", + "VFRAME_NW2A0" + ], + [ + "MONITOR_IMUX18_1", + "VFRAME_IMUX18" + ], + [ + "MONITOR_IMUX6_1", + "VFRAME_IMUX6" + ], + [ + "MONITOR_IMUX35_1", + "VFRAME_IMUX35" + ], + [ + "MONITOR_WW4B2_1", + "VFRAME_WW4B2" + ], + [ + "MONITOR_LH12_1", + "VFRAME_LH12" + ], + [ + "MONITOR_SE4BEG2_1", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_WW4A2_1", + "VFRAME_WW4A2" + ], + [ + "MONITOR_NW4END3_1", + "VFRAME_NW4END3" + ], + [ + "MONITOR_WW4END3_1", + "VFRAME_WW4END3" + ], + [ + "MONITOR_IMUX28_1", + "VFRAME_IMUX28" + ], + [ + "MONITOR_EE4BEG0_1", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_WW2END1_1", + "VFRAME_WW2END1" + ], + [ + "MONITOR_IMUX26_1", + "VFRAME_IMUX26" + ], + [ + "MONITOR_EE4C2_1", + "VFRAME_EE4C2" + ], + [ + "MONITOR_SE2A0_1", + "VFRAME_SE2A0" + ], + [ + "MONITOR_NW2A2_1", + "VFRAME_NW2A2" + ], + [ + "MONITOR_WW4END2_1", + "VFRAME_WW4END2" + ], + [ + "MONITOR_ER1BEG1_1", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_BYP6_1", + "VFRAME_BYP6" + ], + [ + "MONITOR_BYP7_1", + "VFRAME_BYP7" + ], + [ + "MONITOR_WR1END1_1", + "VFRAME_WR1END1" + ], + [ + "MONITOR_IMUX24_1", + "VFRAME_IMUX24" + ], + [ + "MONITOR_SW4A1_1", + "VFRAME_SW4A1" + ], + [ + "MONITOR_WR1END2_1", + "VFRAME_WR1END2" + ], + [ + "MONITOR_IMUX8_1", + "VFRAME_IMUX8" + ], + [ + "MONITOR_SW4A3_1", + "VFRAME_SW4A3" + ], + [ + "MONITOR_SW4END2_1", + "VFRAME_SW4END2" + ], + [ + "MONITOR_IMUX47_1", + "VFRAME_IMUX47" + ], + [ + "MONITOR_IMUX36_1", + "VFRAME_IMUX36" + ], + [ + "MONITOR_SW2A2_1", + "VFRAME_SW2A2" + ], + [ + "MONITOR_SE4C1_1", + "VFRAME_SE4C1" + ], + [ + "MONITOR_FAN4_1", + "VFRAME_FAN4" + ], + [ + "MONITOR_CTRL0_1", + "VFRAME_CTRL0" + ], + [ + "MONITOR_SE2A1_1", + "VFRAME_SE2A1" + ], + [ + "MONITOR_IMUX22_1", + "VFRAME_IMUX22" + ], + [ + "MONITOR_LH2_1", + "VFRAME_LH2" + ], + [ + "MONITOR_EL1BEG3_1", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_NW4A3_1", + "VFRAME_NW4A3" + ], + [ + "MONITOR_CTRL1_1", + "VFRAME_CTRL1" + ], + [ + "MONITOR_SW2A3_1", + "VFRAME_SW2A3" + ], + [ + "MONITOR_WL1END2_1", + "VFRAME_WL1END2" + ], + [ + "MONITOR_LH4_1", + "VFRAME_LH4" + ], + [ + "MONITOR_IMUX25_1", + "VFRAME_IMUX25" + ], + [ + "MONITOR_BYP0_1", + "VFRAME_BYP0" + ], + [ + "MONITOR_WW4C1_1", + "VFRAME_WW4C1" + ], + [ + "MONITOR_EE2A3_1", + "VFRAME_EE2A3" + ], + [ + "MONITOR_EE4A3_1", + "VFRAME_EE4A3" + ], + [ + "MONITOR_IMUX23_1", + "VFRAME_IMUX23" + ], + [ + "MONITOR_SE2A2_1", + "VFRAME_SE2A2" + ], + [ + "MONITOR_EE4C0_1", + "VFRAME_EE4C0" + ], + [ + "MONITOR_NE4C1_1", + "VFRAME_NE4C1" + ], + [ + "MONITOR_WL1END3_1", + "VFRAME_WL1END3" + ], + [ + "MONITOR_IMUX1_1", + "VFRAME_IMUX1" + ], + [ + "MONITOR_NE4C0_1", + "VFRAME_NE4C0" + ], + [ + "MONITOR_IMUX11_1", + "VFRAME_IMUX11" + ], + [ + "MONITOR_BYP4_1", + "VFRAME_BYP4" + ], + [ + "MONITOR_SW2A0_1", + "VFRAME_SW2A0" + ], + [ + "MONITOR_LH6_1", + "VFRAME_LH6" + ], + [ + "MONITOR_SE4BEG1_1", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_LH7_1", + "VFRAME_LH7" + ], + [ + "MONITOR_NW4END2_1", + "VFRAME_NW4END2" + ], + [ + "MONITOR_BYP5_1", + "VFRAME_BYP5" + ], + [ + "MONITOR_IMUX14_1", + "VFRAME_IMUX14" + ], + [ + "MONITOR_WW4A3_1", + "VFRAME_WW4A3" + ], + [ + "MONITOR_NE2A2_1", + "VFRAME_NE2A2" + ], + [ + "MONITOR_IMUX32_1", + "VFRAME_IMUX32" + ], + [ + "MONITOR_IMUX13_1", + "VFRAME_IMUX13" + ], + [ + "MONITOR_IMUX17_1", + "VFRAME_IMUX17" + ], + [ + "MONITOR_WW4C2_1", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE2A0_1", + "VFRAME_EE2A0" + ], + [ + "MONITOR_IMUX9_1", + "VFRAME_IMUX9" + ], + [ + "MONITOR_IMUX39_1", + "VFRAME_IMUX39" + ], + [ + "MONITOR_SW4END3_1", + "VFRAME_SW4END3" + ], + [ + "MONITOR_IMUX19_1", + "VFRAME_IMUX19" + ] + ], + "tile_types": [ + "MONITOR_MID_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW2A2_5", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A0_5", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END2_5", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SE4C1_5", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SW4END3_5", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NW4END0_5", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW2A0_5", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WL1END3_5", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SE2A2_5", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4B3_5", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_LH3_5", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE2A2_5", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_5", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4C2_5", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2A0_5", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG1_5", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A1_5", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4A2_5", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END1_5", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW4C0_5", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_5", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4END3_5", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4BEG0_5", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH6_5", + "VBRK_LH6" + ], + [ + "CMT_TOP_EL1BEG1_5", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_EE4A1_5", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_MONITOR_N_5", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW4A2_5", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4A3_5", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NE4BEG0_5", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW2A2_5", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C3_5", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH7_5", + "VBRK_LH7" + ], + [ + "CMT_TOP_WW4B2_5", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH5_5", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4A1_5", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4A0_5", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C1_5", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW2A0_5", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WL1END2_5", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_SE4C0_5", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SW4END2_5", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END1_5", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG0_5", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_WR1END1_5", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EE4C1_5", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG0_5", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NW4END2_5", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_EE2BEG2_5", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4B1_5", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_ER1BEG3_5", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NW2A1_5", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B0_5", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END2_5", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A1_5", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE2A3_5", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_LH11_5", + "VBRK_LH11" + ], + [ + "CMT_TOP_WL1END0_5", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SW4END0_5", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4BEG3_5", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C3_5", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_SE4BEG1_5", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NE2A2_5", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B0_5", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_ER1BEG2_5", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_5", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NE2A0_5", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4BEG1_5", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE2A3_5", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG2_5", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_LH9_5", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4END2_5", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4BEG2_5", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2END0_5", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_ER1BEG0_5", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH4_5", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2A1_5", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE2BEG1_5", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_NE4BEG3_5", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C0_5", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_MONITOR_P_5", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_LH8_5", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4A3_5", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2BEG0_5", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_NE2A1_5", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C3_5", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WL1END1_5", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW4A1_5", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_5", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4A0_5", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4END1_5", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH2_5", + "VBRK_LH2" + ], + [ + "CMT_TOP_NE2A3_5", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW4A0_5", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4A3_5", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4C0_5", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_LH12_5", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH1_5", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_5", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_ER1BEG1_5", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2BEG3_5", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH10_5", + "VBRK_LH10" + ], + [ + "CMT_TOP_SW2A2_5", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WR1END3_5", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NW4END1_5", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NW4A1_5", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WW4C2_5", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WR1END0_5", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4END3_5", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW4A3_5", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4END0_5", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW2A3_5", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4C2_5", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG3_5", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW2A3_5", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4A2_5", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4BEG3_5", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE4B2_5", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW2A0_5", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SE2A0_5", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SE4BEG2_5", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B1_5", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4C1_5", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C2_5", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4C3_5", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_EL1BEG2_5", + "VBRK_EL1BEG2" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "BRAM_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "BRAM_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "BRAM_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "BRAM_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "BRAM_LH4_3", + "VBRK_LH4" + ], + [ + "BRAM_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "BRAM_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "BRAM_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "BRAM_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "BRAM_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "BRAM_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "BRAM_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "BRAM_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "BRAM_LH1_3", + "VBRK_LH1" + ], + [ + "BRAM_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "BRAM_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "BRAM_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "BRAM_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "BRAM_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "BRAM_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "BRAM_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "BRAM_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "BRAM_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "BRAM_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "BRAM_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "BRAM_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "BRAM_LH7_3", + "VBRK_LH7" + ], + [ + "BRAM_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "BRAM_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "BRAM_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "BRAM_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "BRAM_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "BRAM_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "BRAM_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "BRAM_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "BRAM_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "BRAM_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "BRAM_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "BRAM_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "BRAM_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "BRAM_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "BRAM_LH8_3", + "VBRK_LH8" + ], + [ + "BRAM_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "BRAM_EL1BEG1_3", + "VBRK_EL1BEG1" + ], + [ + "BRAM_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "BRAM_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "BRAM_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "BRAM_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "BRAM_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "BRAM_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "BRAM_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "BRAM_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "BRAM_LH11_3", + "VBRK_LH11" + ], + [ + "BRAM_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "BRAM_MONITOR_P_3", + "VBRK_MONITOR_P" + ], + [ + "BRAM_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "BRAM_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "BRAM_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "BRAM_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "BRAM_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "BRAM_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "BRAM_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "BRAM_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "BRAM_LH10_3", + "VBRK_LH10" + ], + [ + "BRAM_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "BRAM_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "BRAM_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "BRAM_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "BRAM_LH3_3", + "VBRK_LH3" + ], + [ + "BRAM_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "BRAM_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "BRAM_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "BRAM_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "BRAM_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "BRAM_LH12_3", + "VBRK_LH12" + ], + [ + "BRAM_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "BRAM_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "BRAM_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "BRAM_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "BRAM_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "BRAM_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "BRAM_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "BRAM_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "BRAM_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "BRAM_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "BRAM_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "BRAM_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "BRAM_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "BRAM_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "BRAM_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "BRAM_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "BRAM_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "BRAM_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "BRAM_MONITOR_N_3", + "VBRK_MONITOR_N" + ], + [ + "BRAM_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "BRAM_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "BRAM_LH2_3", + "VBRK_LH2" + ], + [ + "BRAM_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "BRAM_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "BRAM_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "BRAM_LH5_3", + "VBRK_LH5" + ], + [ + "BRAM_LH9_3", + "VBRK_LH9" + ], + [ + "BRAM_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "BRAM_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "BRAM_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "BRAM_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "BRAM_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "BRAM_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "BRAM_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "BRAM_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "BRAM_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "BRAM_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "BRAM_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "BRAM_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "BRAM_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "BRAM_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "BRAM_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "BRAM_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "BRAM_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "BRAM_LH6_3", + "VBRK_LH6" + ], + [ + "BRAM_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "BRAM_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "BRAM_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "BRAM_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "BRAM_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "BRAM_WW4A3_3", + "VBRK_WW4A3" + ] + ], + "tile_types": [ + "BRAM_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_LH8", + "BRAM_LH8_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX35", + "BRAM_IMUX35_UTURN_0" + ], + [ + "INT_INTERFACE_EL1BEG3", + "BRAM_EL1BEG3_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX16", + "BRAM_IMUX16_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX47", + "BRAM_IMUX47_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX37", + "BRAM_IMUX37_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX24", + "BRAM_IMUX24_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_0" + ], + [ + "INT_INTERFACE_EL1BEG0", + "BRAM_EL1BEG0_0" + ], + [ + "INT_INTERFACE_WW4B2", + "BRAM_WW4B2_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "BRAM_LOGIC_OUTS_B15_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX38", + "BRAM_IMUX38_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX39", + "BRAM_IMUX39_0" + ], + [ + "INT_INTERFACE_EL1BEG2", + "BRAM_EL1BEG2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX4", + "BRAM_IMUX4_UTURN_0" + ], + [ + "INT_INTERFACE_NW4A3", + "BRAM_NW4A3_0" + ], + [ + "INT_INTERFACE_EE4B1", + "BRAM_EE4B1_0" + ], + [ + "INT_INTERFACE_WW4B0", + "BRAM_WW4B0_0" + ], + [ + "INT_INTERFACE_BYP4", + "BRAM_BYP4_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX43", + "BRAM_IMUX43_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX14", + "BRAM_IMUX14_UTURN_0" + ], + [ + "INT_INTERFACE_WR1END1", + "BRAM_WR1END1_0" + ], + [ + "INT_INTERFACE_WW2A2", + "BRAM_WW2A2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX15", + "BRAM_IMUX15_UTURN_0" + ], + [ + "INT_INTERFACE_CTRL0", + "BRAM_CTRL0_0" + ], + [ + "INT_INTERFACE_EE4C1", + "BRAM_EE4C1_0" + ], + [ + "INT_INTERFACE_SE4C3", + "BRAM_SE4C3_0" + ], + [ + "INT_INTERFACE_FAN0", + "BRAM_FAN0_0" + ], + [ + "INT_INTERFACE_SW2A0", + "BRAM_SW2A0_0" + ], + [ + "INT_INTERFACE_FAN4", + "BRAM_FAN4_0" + ], + [ + "INT_INTERFACE_EE4B3", + "BRAM_EE4B3_0" + ], + [ + "INT_INTERFACE_NE2A2", + "BRAM_NE2A2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX19", + "BRAM_IMUX19_UTURN_0" + ], + [ + "INT_INTERFACE_NE4C0", + "BRAM_NE4C0_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX42", + "BRAM_IMUX42_UTURN_0" + ], + [ + "INT_INTERFACE_WR1END2", + "BRAM_WR1END2_0" + ], + [ + "INT_INTERFACE_NE2A1", + "BRAM_NE2A1_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX36", + "BRAM_IMUX36_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "BRAM_LOGIC_OUTS_B8_0" + ], + [ + "INT_INTERFACE_LH3", + "BRAM_LH3_0" + ], + [ + "INT_INTERFACE_NW4END2", + "BRAM_NW4END2_0" + ], + [ + "INT_INTERFACE_WW4C0", + "BRAM_WW4C0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "BRAM_LOGIC_OUTS_B2_0" + ], + [ + "INT_INTERFACE_WW4END1", + "BRAM_WW4END1_0" + ], + [ + "INT_INTERFACE_SE2A0", + "BRAM_SE2A0_0" + ], + [ + "INT_INTERFACE_WW4A2", + "BRAM_WW4A2_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "BRAM_LOGIC_OUTS_B5_0" + ], + [ + "INT_INTERFACE_WW4A0", + "BRAM_WW4A0_0" + ], + [ + "INT_INTERFACE_EE2A0", + "BRAM_EE2A0_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_0" + ], + [ + "INT_INTERFACE_SE4C1", + "BRAM_SE4C1_0" + ], + [ + "INT_INTERFACE_NE2A3", + "BRAM_NE2A3_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "BRAM_LOGIC_OUTS_B3_0" + ], + [ + "INT_INTERFACE_NE4BEG1", + "BRAM_NE4BEG1_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_0" + ], + [ + "INT_INTERFACE_FAN6", + "BRAM_FAN6_0" + ], + [ + "INT_INTERFACE_WW2END2", + "BRAM_WW2END2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX21", + "BRAM_IMUX21_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_0" + ], + [ + "INT_INTERFACE_SW2A2", + "BRAM_SW2A2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_0" + ], + [ + "INT_INTERFACE_EE2BEG3", + "BRAM_EE2BEG3_0" + ], + [ + "INT_INTERFACE_WW4A1", + "BRAM_WW4A1_0" + ], + [ + "INT_INTERFACE_NW4A0", + "BRAM_NW4A0_0" + ], + [ + "INT_INTERFACE_SW4A2", + "BRAM_SW4A2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_0" + ], + [ + "INT_INTERFACE_BYP1", + "BRAM_BYP1_0" + ], + [ + "INT_INTERFACE_BYP5", + "BRAM_BYP5_0" + ], + [ + "INT_INTERFACE_SW4END2", + "BRAM_SW4END2_0" + ], + [ + "INT_INTERFACE_LH9", + "BRAM_LH9_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_0" + ], + [ + "INT_INTERFACE_LH2", + "BRAM_LH2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_0" + ], + [ + "INT_INTERFACE_EE2A2", + "BRAM_EE2A2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX3", + "BRAM_IMUX3_UTURN_0" + ], + [ + "INT_INTERFACE_BYP3", + "BRAM_BYP3_0" + ], + [ + "INT_INTERFACE_EE4A3", + "BRAM_EE4A3_0" + ], + [ + "INT_INTERFACE_SW4END1", + "BRAM_SW4END1_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX32", + "BRAM_IMUX32_0" + ], + [ + "INT_INTERFACE_WW2A3", + "BRAM_WW2A3_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX29", + "BRAM_IMUX29_0" + ], + [ + "INT_INTERFACE_NW2A2", + "BRAM_NW2A2_0" + ], + [ + "INT_INTERFACE_NW4END1", + "BRAM_NW4END1_0" + ], + [ + "INT_INTERFACE_SW2A1", + "BRAM_SW2A1_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX9", + "BRAM_IMUX9_UTURN_0" + ], + [ + "INT_INTERFACE_FAN7", + "BRAM_FAN7_0" + ], + [ + "INT_INTERFACE_EE4C0", + "BRAM_EE4C0_0" + ], + [ + "INT_INTERFACE_SE4BEG0", + "BRAM_SE4BEG0_0" + ], + [ + "INT_INTERFACE_EE4C2", + "BRAM_EE4C2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX30", + "BRAM_IMUX30_UTURN_0" + ], + [ + "INT_INTERFACE_CLK0", + "BRAM_CLK0_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX35", + "BRAM_IMUX35_0" + ], + [ + "INT_INTERFACE_FAN2", + "BRAM_FAN2_0" + ], + [ + "INT_INTERFACE_EE4BEG1", + "BRAM_EE4BEG1_0" + ], + [ + "INT_INTERFACE_WL1END3", + "BRAM_WL1END3_0" + ], + [ + "INT_INTERFACE_SW2A3", + "BRAM_SW2A3_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX40", + "BRAM_IMUX40_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX34", + "BRAM_IMUX34_0" + ], + [ + "INT_INTERFACE_SE4C0", + "BRAM_SE4C0_0" + ], + [ + "INT_INTERFACE_LH6", + "BRAM_LH6_0" + ], + [ + "INT_INTERFACE_NE4BEG2", + "BRAM_NE4BEG2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX23", + "BRAM_IMUX23_0" + ], + [ + "INT_INTERFACE_SE2A3", + "BRAM_SE2A3_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_0" + ], + [ + "INT_INTERFACE_WW2END3", + "BRAM_WW2END3_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX25", + "BRAM_IMUX25_UTURN_0" + ], + [ + "INT_INTERFACE_FAN5", + "BRAM_FAN5_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX41", + "BRAM_IMUX41_UTURN_0" + ], + [ + "INT_INTERFACE_EE4B0", + "BRAM_EE4B0_0" + ], + [ + "INT_INTERFACE_LH11", + "BRAM_LH11_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX34", + "BRAM_IMUX34_UTURN_0" + ], + [ + "INT_INTERFACE_EE4B2", + "BRAM_EE4B2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX22", + "BRAM_IMUX22_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX47", + "BRAM_IMUX47_0" + ], + [ + "INT_INTERFACE_LH1", + "BRAM_LH1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "BRAM_LOGIC_OUTS_B21_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX11", + "BRAM_IMUX11_UTURN_0" + ], + [ + "INT_INTERFACE_WW2END0", + "BRAM_WW2END0_0" + ], + [ + "INT_INTERFACE_WW4A3", + "BRAM_WW4A3_0" + ], + [ + "INT_INTERFACE_BYP6", + "BRAM_BYP6_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "BRAM_LOGIC_OUTS_B23_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "BRAM_LOGIC_OUTS_B0_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX45", + "BRAM_IMUX45_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX46", + "BRAM_IMUX46_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX26", + "BRAM_IMUX26_0" + ], + [ + "INT_INTERFACE_NW4END3", + "BRAM_NW4END3_0" + ], + [ + "INT_INTERFACE_EE4A1", + "BRAM_EE4A1_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX17", + "BRAM_IMUX17_UTURN_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "BRAM_LOGIC_OUTS_B20_0" + ], + [ + "INT_INTERFACE_WL1END1", + "BRAM_WL1END1_0" + ], + [ + "INT_INTERFACE_WW4END0", + "BRAM_WW4END0_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX30", + "BRAM_IMUX30_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_0" + ], + [ + "INT_INTERFACE_WW4C2", + "BRAM_WW4C2_0" + ], + [ + "INT_INTERFACE_SW4A0", + "BRAM_SW4A0_0" + ], + [ + "INT_INTERFACE_WW4END2", + "BRAM_WW4END2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX23", + "BRAM_IMUX23_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX32", + "BRAM_IMUX32_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX28", + "BRAM_IMUX28_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX44", + "BRAM_IMUX44_0" + ], + [ + "INT_INTERFACE_NE2A0", + "BRAM_NE2A0_0" + ], + [ + "INT_INTERFACE_FAN1", + "BRAM_FAN1_0" + ], + [ + "INT_INTERFACE_SW4END0", + "BRAM_SW4END0_0" + ], + [ + "INT_INTERFACE_ER1BEG2", + "BRAM_ER1BEG2_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "BRAM_LOGIC_OUTS_B6_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX45", + "BRAM_IMUX45_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "BRAM_LOGIC_OUTS_B1_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX38", + "BRAM_IMUX38_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX33", + "BRAM_IMUX33_0" + ], + [ + "INT_INTERFACE_NW4A1", + "BRAM_NW4A1_0" + ], + [ + "INT_INTERFACE_EE2A1", + "BRAM_EE2A1_0" + ], + [ + "INT_INTERFACE_SE4C2", + "BRAM_SE4C2_0" + ], + [ + "INT_INTERFACE_WW4C1", + "BRAM_WW4C1_0" + ], + [ + "INT_INTERFACE_SE4BEG2", + "BRAM_SE4BEG2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX31", + "BRAM_IMUX31_UTURN_0" + ], + [ + "INT_INTERFACE_WL1END0", + "BRAM_WL1END0_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX29", + "BRAM_IMUX29_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX41", + "BRAM_IMUX41_0" + ], + [ + "INT_INTERFACE_NW2A3", + "BRAM_NW2A3_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX27", + "BRAM_IMUX27_UTURN_0" + ], + [ + "INT_INTERFACE_NE4C1", + "BRAM_NE4C1_0" + ], + [ + "INT_INTERFACE_NE4BEG3", + "BRAM_NE4BEG3_0" + ], + [ + "INT_INTERFACE_BYP7", + "BRAM_BYP7_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX5", + "BRAM_IMUX5_UTURN_0" + ], + [ + "INT_INTERFACE_EE4A0", + "BRAM_EE4A0_0" + ], + [ + "INT_INTERFACE_EE4BEG0", + "BRAM_EE4BEG0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "BRAM_LOGIC_OUTS_B12_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX21", + "BRAM_IMUX21_0" + ], + [ + "INT_INTERFACE_LH5", + "BRAM_LH5_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "BRAM_LOGIC_OUTS_B18_0" + ], + [ + "INT_INTERFACE_NW4A2", + "BRAM_NW4A2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX2", + "BRAM_IMUX2_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX39", + "BRAM_IMUX39_UTURN_0" + ], + [ + "INT_INTERFACE_NW2A1", + "BRAM_NW2A1_0" + ], + [ + "INT_INTERFACE_LH4", + "BRAM_LH4_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "BRAM_LOGIC_OUTS_B22_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX8", + "BRAM_IMUX8_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "BRAM_LOGIC_OUTS_B13_0" + ], + [ + "INT_INTERFACE_SW4END3", + "BRAM_SW4END3_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX20", + "BRAM_IMUX20_UTURN_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "BRAM_LOGIC_OUTS_B9_0" + ], + [ + "INT_INTERFACE_WL1END2", + "BRAM_WL1END2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX18", + "BRAM_IMUX18_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX36", + "BRAM_IMUX36_UTURN_0" + ], + [ + "INT_INTERFACE_WW4B3", + "BRAM_WW4B3_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "BRAM_LOGIC_OUTS_B16_0" + ], + [ + "INT_INTERFACE_BYP2", + "BRAM_BYP2_0" + ], + [ + "INT_INTERFACE_NE4C3", + "BRAM_NE4C3_0" + ], + [ + "INT_INTERFACE_WR1END0", + "BRAM_WR1END0_0" + ], + [ + "INT_INTERFACE_ER1BEG1", + "BRAM_ER1BEG1_0" + ], + [ + "INT_INTERFACE_LH7", + "BRAM_LH7_0" + ], + [ + "INT_INTERFACE_WW2END1", + "BRAM_WW2END1_0" + ], + [ + "INT_INTERFACE_EE4BEG2", + "BRAM_EE4BEG2_0" + ], + [ + "INT_INTERFACE_WW4C3", + "BRAM_WW4C3_0" + ], + [ + "INT_INTERFACE_CLK1", + "BRAM_CLK1_0" + ], + [ + "INT_INTERFACE_LH12", + "BRAM_LH12_0" + ], + [ + "INT_INTERFACE_EE2BEG0", + "BRAM_EE2BEG0_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX42", + "BRAM_IMUX42_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX1", + "BRAM_IMUX1_UTURN_0" + ], + [ + "INT_INTERFACE_WW2A1", + "BRAM_WW2A1_0" + ], + [ + "INT_INTERFACE_WW4B1", + "BRAM_WW4B1_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX31", + "BRAM_IMUX31_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX44", + "BRAM_IMUX44_UTURN_0" + ], + [ + "INT_INTERFACE_EE4A2", + "BRAM_EE4A2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX46", + "BRAM_IMUX46_0" + ], + [ + "INT_INTERFACE_SE2A2", + "BRAM_SE2A2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX37", + "BRAM_IMUX37_0" + ], + [ + "INT_INTERFACE_ER1BEG3", + "BRAM_ER1BEG3_0" + ], + [ + "INT_INTERFACE_FAN3", + "BRAM_FAN3_0" + ], + [ + "INT_INTERFACE_EE4BEG3", + "BRAM_EE4BEG3_0" + ], + [ + "INT_INTERFACE_LH10", + "BRAM_LH10_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "BRAM_LOGIC_OUTS_B7_0" + ], + [ + "INT_INTERFACE_EE2BEG1", + "BRAM_EE2BEG1_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX6", + "BRAM_IMUX6_UTURN_0" + ], + [ + "INT_INTERFACE_SW4A1", + "BRAM_SW4A1_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX26", + "BRAM_IMUX26_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX27", + "BRAM_IMUX27_0" + ], + [ + "INT_INTERFACE_BYP0", + "BRAM_BYP0_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX33", + "BRAM_IMUX33_UTURN_0" + ], + [ + "INT_INTERFACE_WW4END3", + "BRAM_WW4END3_0" + ], + [ + "INT_INTERFACE_MONITOR_P", + "BRAM_MONITOR_P_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX12", + "BRAM_IMUX12_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX13", + "BRAM_IMUX13_UTURN_0" + ], + [ + "INT_INTERFACE_NE4C2", + "BRAM_NE4C2_0" + ], + [ + "INT_INTERFACE_EE2BEG2", + "BRAM_EE2BEG2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX22", + "BRAM_IMUX22_UTURN_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "BRAM_LOGIC_OUTS_B19_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "BRAM_LOGIC_OUTS_B17_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX24", + "BRAM_IMUX24_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX7", + "BRAM_IMUX7_UTURN_0" + ], + [ + "INT_INTERFACE_SE4BEG1", + "BRAM_SE4BEG1_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX40", + "BRAM_IMUX40_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX43", + "BRAM_IMUX43_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "BRAM_LOGIC_OUTS_B10_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX0", + "BRAM_IMUX0_UTURN_0" + ], + [ + "INT_INTERFACE_SE4BEG3", + "BRAM_SE4BEG3_0" + ], + [ + "INT_INTERFACE_EE4C3", + "BRAM_EE4C3_0" + ], + [ + "INT_INTERFACE_MONITOR_N", + "BRAM_MONITOR_N_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX25", + "BRAM_IMUX25_0" + ], + [ + "INT_INTERFACE_EL1BEG1", + "BRAM_EL1BEG1_0" + ], + [ + "INT_INTERFACE_CTRL1", + "BRAM_CTRL1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "BRAM_LOGIC_OUTS_B4_0" + ], + [ + "INT_INTERFACE_SW4A3", + "BRAM_SW4A3_0" + ], + [ + "INT_INTERFACE_WR1END3", + "BRAM_WR1END3_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX10", + "BRAM_IMUX10_UTURN_0" + ], + [ + "INT_INTERFACE_NW4END0", + "BRAM_NW4END0_0" + ], + [ + "INT_INTERFACE_WW2A0", + "BRAM_WW2A0_0" + ], + [ + "INT_INTERFACE_EE2A3", + "BRAM_EE2A3_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX28", + "BRAM_IMUX28_UTURN_0" + ], + [ + "INT_INTERFACE_NE4BEG0", + "BRAM_NE4BEG0_0" + ], + [ + "INT_INTERFACE_NW2A0", + "BRAM_NW2A0_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_0" + ], + [ + "INT_INTERFACE_SE2A1", + "BRAM_SE2A1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "BRAM_LOGIC_OUTS_B14_0" + ], + [ + "INT_INTERFACE_ER1BEG0", + "BRAM_ER1BEG0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "BRAM_LOGIC_OUTS_B11_0" + ] + ], + "tile_types": [ + "BRAM_INT_INTERFACE_L", + "BRAM_L" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLBLM_WW2END1", + "WW2A1" + ], + [ + "CLBLM_WR1END1", + "WR1BEG1" + ], + [ + "CLBLM_NW4END3", + "NW6E3" + ], + [ + "CLBLM_NE2A0", + "NE2END0" + ], + [ + "CLBLM_SW4END3", + "SW6E3" + ], + [ + "CLBLM_IMUX39", + "IMUX_L39" + ], + [ + "CLBLM_LOGIC_OUTS23", + "LOGIC_OUTS_L23" + ], + [ + "CLBLM_SE4BEG0", + "SE6A0" + ], + [ + "CLBLM_IMUX3", + "IMUX_L3" + ], + [ + "CLBLM_EE4BEG2", + "EE4A2" + ], + [ + "CLBLM_NE2A3", + "NE2END3" + ], + [ + "CLBLM_IMUX47", + "IMUX_L47" + ], + [ + "CLBLM_WR1END0", + "WR1BEG0" + ], + [ + "CLBLM_WW4END1", + "WW4C1" + ], + [ + "CLBLM_EE4BEG3", + "EE4A3" + ], + [ + "CLBLM_EE2A3", + "EE2END3" + ], + [ + "CLBLM_IMUX19", + "IMUX_L19" + ], + [ + "CLBLM_LH2", + "LH1" + ], + [ + "CLBLM_EE4C1", + "EE4END1" + ], + [ + "CLBLM_EE4A0", + "EE4B0" + ], + [ + "CLBLM_EL1BEG0", + "EL1END0" + ], + [ + "CLBLM_WW4B1", + "WW4A1" + ], + [ + "CLBLM_NW2A3", + "NW2A3" + ], + [ + "CLBLM_FAN5", + "FAN_L5" + ], + [ + "CLBLM_IMUX5", + "IMUX_L5" + ], + [ + "CLBLM_LH3", + "LH2" + ], + [ + "CLBLM_SW4END1", + "SW6E1" + ], + [ + "CLBLM_WW4C2", + "WW4B2" + ], + [ + "CLBLM_LOGIC_OUTS19", + "LOGIC_OUTS_L19" + ], + [ + "CLBLM_IMUX35", + "IMUX_L35" + ], + [ + "CLBLM_NW4A3", + "NW6BEG3" + ], + [ + "CLBLM_LOGIC_OUTS16", + "LOGIC_OUTS_L16" + ], + [ + "CLBLM_SW2A0", + "SW2A0" + ], + [ + "CLBLM_EE2BEG1", + "EE2A1" + ], + [ + "CLBLM_NW4A2", + "NW6BEG2" + ], + [ + "CLBLM_LOGIC_OUTS18", + "LOGIC_OUTS_L18" + ], + [ + "CLBLM_IMUX16", + "IMUX_L16" + ], + [ + "CLBLM_IMUX17", + "IMUX_L17" + ], + [ + "CLBLM_IMUX27", + "IMUX_L27" + ], + [ + "CLBLM_LOGIC_OUTS12", + "LOGIC_OUTS_L12" + ], + [ + "CLBLM_FAN1", + "FAN_L1" + ], + [ + "CLBLM_SE4BEG2", + "SE6A2" + ], + [ + "CLBLM_IMUX20", + "IMUX_L20" + ], + [ + "CLBLM_IMUX32", + "IMUX_L32" + ], + [ + "CLBLM_IMUX18", + "IMUX_L18" + ], + [ + "CLBLM_LH7", + "LH6" + ], + [ + "CLBLM_EE4A2", + "EE4B2" + ], + [ + "CLBLM_IMUX43", + "IMUX_L43" + ], + [ + "CLBLM_BYP7", + "BYP_L7" + ], + [ + "CLBLM_WW4A2", + "WW4BEG2" + ], + [ + "CLBLM_ER1BEG2", + "ER1END2" + ], + [ + "CLBLM_MONITOR_N", + "MONITOR_N" + ], + [ + "CLBLM_LOGIC_OUTS4", + "LOGIC_OUTS_L4" + ], + [ + "CLBLM_SW2A2", + "SW2A2" + ], + [ + "CLBLM_LH8", + "LH7" + ], + [ + "CLBLM_SE2A0", + "SE2END0" + ], + [ + "CLBLM_NE4BEG0", + "NE6A0" + ], + [ + "CLBLM_LOGIC_OUTS1", + "LOGIC_OUTS_L1" + ], + [ + "CLBLM_LOGIC_OUTS3", + "LOGIC_OUTS_L3" + ], + [ + "CLBLM_FAN6", + "FAN_L6" + ], + [ + "CLBLM_SW4A0", + "SW6BEG0" + ], + [ + "CLBLM_IMUX29", + "IMUX_L29" + ], + [ + "CLBLM_EL1BEG1", + "EL1END1" + ], + [ + "CLBLM_SE4C1", + "SE6END1" + ], + [ + "CLBLM_WL1END0", + "WL1BEG0" + ], + [ + "CLBLM_LH11", + "LH10" + ], + [ + "CLBLM_SE4C3", + "SE6END3" + ], + [ + "CLBLM_SW2A1", + "SW2A1" + ], + [ + "CLBLM_LH5", + "LH4" + ], + [ + "CLBLM_NW4A0", + "NW6BEG0" + ], + [ + "CLBLM_SW4END2", + "SW6E2" + ], + [ + "CLBLM_LOGIC_OUTS11", + "LOGIC_OUTS_L11" + ], + [ + "CLBLM_WW4A0", + "WW4BEG0" + ], + [ + "CLBLM_LOGIC_OUTS22", + "LOGIC_OUTS_L22" + ], + [ + "CLBLM_IMUX12", + "IMUX_L12" + ], + [ + "CLBLM_WW2A0", + "WW2BEG0" + ], + [ + "CLBLM_WW4C1", + "WW4B1" + ], + [ + "CLBLM_NE2A1", + "NE2END1" + ], + [ + "CLBLM_ER1BEG3", + "ER1END3" + ], + [ + "CLBLM_IMUX8", + "IMUX_L8" + ], + [ + "CLBLM_EL1BEG2", + "EL1END2" + ], + [ + "CLBLM_NW4END1", + "NW6E1" + ], + [ + "CLBLM_NE4BEG2", + "NE6A2" + ], + [ + "CLBLM_LOGIC_OUTS5", + "LOGIC_OUTS_L5" + ], + [ + "CLBLM_CTRL0", + "CTRL_L0" + ], + [ + "CLBLM_EE4BEG0", + "EE4A0" + ], + [ + "CLBLM_CLK0", + "CLK_L0" + ], + [ + "CLBLM_SW4END0", + "SW6E0" + ], + [ + "CLBLM_NW2A2", + "NW2A2" + ], + [ + "CLBLM_LOGIC_OUTS14", + "LOGIC_OUTS_L14" + ], + [ + "CLBLM_NW4END0", + "NW6E0" + ], + [ + "CLBLM_FAN4", + "FAN_L4" + ], + [ + "CLBLM_LOGIC_OUTS20", + "LOGIC_OUTS_L20" + ], + [ + "CLBLM_LH1", + "LH0" + ], + [ + "CLBLM_NW2A1", + "NW2A1" + ], + [ + "CLBLM_SE4C2", + "SE6END2" + ], + [ + "CLBLM_WL1END2", + "WL1BEG2" + ], + [ + "CLBLM_IMUX46", + "IMUX_L46" + ], + [ + "CLBLM_EE2A2", + "EE2END2" + ], + [ + "CLBLM_SE4C0", + "SE6END0" + ], + [ + "CLBLM_EE4A3", + "EE4B3" + ], + [ + "CLBLM_IMUX42", + "IMUX_L42" + ], + [ + "CLBLM_IMUX33", + "IMUX_L33" + ], + [ + "CLBLM_IMUX22", + "IMUX_L22" + ], + [ + "CLBLM_WW2END2", + "WW2A2" + ], + [ + "CLBLM_IMUX9", + "IMUX_L9" + ], + [ + "CLBLM_WL1END1", + "WL1BEG1" + ], + [ + "CLBLM_LOGIC_OUTS2", + "LOGIC_OUTS_L2" + ], + [ + "CLBLM_SE4BEG3", + "SE6A3" + ], + [ + "CLBLM_IMUX38", + "IMUX_L38" + ], + [ + "CLBLM_IMUX0", + "IMUX_L0" + ], + [ + "CLBLM_SE2A3", + "SE2END3" + ], + [ + "CLBLM_WW4A1", + "WW4BEG1" + ], + [ + "CLBLM_SW4A1", + "SW6BEG1" + ], + [ + "CLBLM_NE4C3", + "NE6END3" + ], + [ + "CLBLM_IMUX36", + "IMUX_L36" + ], + [ + "CLBLM_ER1BEG1", + "ER1END1" + ], + [ + "CLBLM_IMUX41", + "IMUX_L41" + ], + [ + "CLBLM_IMUX21", + "IMUX_L21" + ], + [ + "CLBLM_BYP0", + "BYP_L0" + ], + [ + "CLBLM_WW4END2", + "WW4C2" + ], + [ + "CLBLM_EE4C0", + "EE4END0" + ], + [ + "CLBLM_IMUX34", + "IMUX_L34" + ], + [ + "CLBLM_SE4BEG1", + "SE6A1" + ], + [ + "CLBLM_BYP4", + "BYP_L4" + ], + [ + "CLBLM_LOGIC_OUTS7", + "LOGIC_OUTS_L7" + ], + [ + "CLBLM_IMUX37", + "IMUX_L37" + ], + [ + "CLBLM_WW4A3", + "WW4BEG3" + ], + [ + "CLBLM_MONITOR_P", + "MONITOR_P" + ], + [ + "CLBLM_NE2A2", + "NE2END2" + ], + [ + "CLBLM_NE4C1", + "NE6END1" + ], + [ + "CLBLM_ER1BEG0", + "ER1END0" + ], + [ + "CLBLM_LOGIC_OUTS6", + "LOGIC_OUTS_L6" + ], + [ + "CLBLM_SW2A3", + "SW2A3" + ], + [ + "CLBLM_LOGIC_OUTS21", + "LOGIC_OUTS_L21" + ], + [ + "CLBLM_EE4B3", + "EE4C3" + ], + [ + "CLBLM_IMUX4", + "IMUX_L4" + ], + [ + "CLBLM_WW4END3", + "WW4C3" + ], + [ + "CLBLM_BYP3", + "BYP_L3" + ], + [ + "CLBLM_WW4C3", + "WW4B3" + ], + [ + "CLBLM_EE4A1", + "EE4B1" + ], + [ + "CLBLM_WW2END3", + "WW2A3" + ], + [ + "CLBLM_EL1BEG3", + "EL1END3" + ], + [ + "CLBLM_BYP6", + "BYP_L6" + ], + [ + "CLBLM_FAN7", + "FAN_L7" + ], + [ + "CLBLM_IMUX44", + "IMUX_L44" + ], + [ + "CLBLM_IMUX26", + "IMUX_L26" + ], + [ + "CLBLM_IMUX40", + "IMUX_L40" + ], + [ + "CLBLM_CLK1", + "CLK_L1" + ], + [ + "CLBLM_NW4END2", + "NW6E2" + ], + [ + "CLBLM_EE4C3", + "EE4END3" + ], + [ + "CLBLM_WR1END2", + "WR1BEG2" + ], + [ + "CLBLM_IMUX13", + "IMUX_L13" + ], + [ + "CLBLM_BYP5", + "BYP_L5" + ], + [ + "CLBLM_LOGIC_OUTS10", + "LOGIC_OUTS_L10" + ], + [ + "CLBLM_LOGIC_OUTS0", + "LOGIC_OUTS_L0" + ], + [ + "CLBLM_IMUX7", + "IMUX_L7" + ], + [ + "CLBLM_SW4A3", + "SW6BEG3" + ], + [ + "CLBLM_LH4", + "LH3" + ], + [ + "CLBLM_BYP1", + "BYP_L1" + ], + [ + "CLBLM_NW4A1", + "NW6BEG1" + ], + [ + "CLBLM_IMUX6", + "IMUX_L6" + ], + [ + "CLBLM_IMUX25", + "IMUX_L25" + ], + [ + "CLBLM_EE2BEG2", + "EE2A2" + ], + [ + "CLBLM_EE4B1", + "EE4C1" + ], + [ + "CLBLM_WW2END0", + "WW2A0" + ], + [ + "CLBLM_IMUX11", + "IMUX_L11" + ], + [ + "CLBLM_WW4B3", + "WW4A3" + ], + [ + "CLBLM_LOGIC_OUTS17", + "LOGIC_OUTS_L17" + ], + [ + "CLBLM_LOGIC_OUTS9", + "LOGIC_OUTS_L9" + ], + [ + "CLBLM_IMUX28", + "IMUX_L28" + ], + [ + "CLBLM_LOGIC_OUTS8", + "LOGIC_OUTS_L8" + ], + [ + "CLBLM_EE4B2", + "EE4C2" + ], + [ + "CLBLM_NE4BEG3", + "NE6A3" + ], + [ + "CLBLM_LH9", + "LH8" + ], + [ + "CLBLM_LOGIC_OUTS13", + "LOGIC_OUTS_L13" + ], + [ + "CLBLM_IMUX15", + "IMUX_L15" + ], + [ + "CLBLM_LH12", + "LH11" + ], + [ + "CLBLM_NE4BEG1", + "NE6A1" + ], + [ + "CLBLM_EE2A1", + "EE2END1" + ], + [ + "CLBLM_WW4B2", + "WW4A2" + ], + [ + "CLBLM_WW2A2", + "WW2BEG2" + ], + [ + "CLBLM_WW2A3", + "WW2BEG3" + ], + [ + "CLBLM_WW4C0", + "WW4B0" + ], + [ + "CLBLM_CTRL1", + "CTRL_L1" + ], + [ + "CLBLM_WW4B0", + "WW4A0" + ], + [ + "CLBLM_IMUX10", + "IMUX_L10" + ], + [ + "CLBLM_LOGIC_OUTS15", + "LOGIC_OUTS_L15" + ], + [ + "CLBLM_NW2A0", + "NW2A0" + ], + [ + "CLBLM_EE2BEG3", + "EE2A3" + ], + [ + "CLBLM_WW4END0", + "WW4C0" + ], + [ + "CLBLM_SE2A1", + "SE2END1" + ], + [ + "CLBLM_EE2A0", + "EE2END0" + ], + [ + "CLBLM_IMUX30", + "IMUX_L30" + ], + [ + "CLBLM_LH10", + "LH9" + ], + [ + "CLBLM_NE4C0", + "NE6END0" + ], + [ + "CLBLM_IMUX24", + "IMUX_L24" + ], + [ + "CLBLM_LH6", + "LH5" + ], + [ + "CLBLM_FAN2", + "FAN_L2" + ], + [ + "CLBLM_IMUX2", + "IMUX_L2" + ], + [ + "CLBLM_WW2A1", + "WW2BEG1" + ], + [ + "CLBLM_IMUX14", + "IMUX_L14" + ], + [ + "CLBLM_IMUX23", + "IMUX_L23" + ], + [ + "CLBLM_IMUX45", + "IMUX_L45" + ], + [ + "CLBLM_FAN3", + "FAN_L3" + ], + [ + "CLBLM_IMUX1", + "IMUX_L1" + ], + [ + "CLBLM_EE4C2", + "EE4END2" + ], + [ + "CLBLM_EE4BEG1", + "EE4A1" + ], + [ + "CLBLM_FAN0", + "FAN_L0" + ], + [ + "CLBLM_WL1END3", + "WL1BEG3" + ], + [ + "CLBLM_SE2A2", + "SE2END2" + ], + [ + "CLBLM_WR1END3", + "WR1BEG3" + ], + [ + "CLBLM_EE4B0", + "EE4C0" + ], + [ + "CLBLM_BYP2", + "BYP_L2" + ], + [ + "CLBLM_SW4A2", + "SW6BEG2" + ], + [ + "CLBLM_EE2BEG0", + "EE2A0" + ], + [ + "CLBLM_NE4C2", + "NE6END2" + ], + [ + "CLBLM_IMUX31", + "IMUX_L31" + ] + ], + "tile_types": [ + "CLBLM_L", + "INT_L" + ] + }, + { + "grid_deltas": [ + 0, + -2 + ], + "wire_pairs": [ + [ + "IOI_RCLK_DIV_CE3_1", + "IOI_RCLK_DIV_CE3" + ], + [ + "IOI_RCLK_DIV_CE2_1", + "IOI_RCLK_DIV_CE2" + ], + [ + "IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "IOI_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1_1" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_LEAF_GCLK3" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_LEAF_GCLK1" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_LEAF_GCLK0" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_RCLK_FORIO1" + ], + [ + "IOI_TBYTEIN", + "IOI_TBYTEIN" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_RCLK_FORIO3" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_RCLK_FORIO2" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_LEAF_GCLK5" + ], + [ + "IOI_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0_1" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_RCLK_FORIO0" + ], + [ + "IOI_IMUX_RC2", + "IOI_IMUX_RC0" + ], + [ + "IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "IOI_IMUX_RC3", + "IOI_IMUX_RC1" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_LEAF_GCLK4" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_LEAF_GCLK2" + ] + ], + "tile_types": [ + "LIOI3", + "LIOI3_TBYTESRC" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CMT_TOP_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_LH2_1", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH11_1", + "VBRK_LH11" + ], + [ + "CMT_TOP_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH10_1", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_LH8_1", + "VBRK_LH8" + ], + [ + "CMT_TOP_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH3_1", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH4_1", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH5_1", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_MONITOR_P_1", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_1", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_LH6_1", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH1_1", + "VBRK_LH1" + ], + [ + "CMT_TOP_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_LH7_1", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_MONITOR_N_1", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_LH9_1", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2BEG2_1", + "VBRK_EE2BEG2" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_IOB_CK_BUFHCLK10", + "HCLK_IOI_CK_BUFHCLK10" + ], + [ + "HCLK_IOB_CK_BUFHCLK6", + "HCLK_IOI_CK_BUFHCLK6" + ], + [ + "HCLK_IOB_PERFCLK2", + "HCLK_IOI_IOCLK_PLL2" + ], + [ + "HCLK_IOB_CK_BUFRCLK1", + "HCLK_IOI_CK_BUFRCLK1" + ], + [ + "HCLK_IOB_PERFCLK0", + "HCLK_IOI_IOCLK_PLL0" + ], + [ + "HCLK_IOB_CK_BUFHCLK11", + "HCLK_IOI_CK_BUFHCLK11" + ], + [ + "HCLK_IOB_CK_BUFHCLK4", + "HCLK_IOI_CK_BUFHCLK4" + ], + [ + "HCLK_IOB_CK_BUFRCLK2", + "HCLK_IOI_CK_BUFRCLK2" + ], + [ + "HCLK_IOB_PERFCLK3", + "HCLK_IOI_IOCLK_PLL3" + ], + [ + "HCLK_IOB_CK_BUFHCLK7", + "HCLK_IOI_CK_BUFHCLK7" + ], + [ + "HCLK_IOB_CK_BUFHCLK3", + "HCLK_IOI_CK_BUFHCLK3" + ], + [ + "HCLK_IOB_CK_BUFHCLK2", + "HCLK_IOI_CK_BUFHCLK2" + ], + [ + "HCLK_IOB_CK_BUFHCLK1", + "HCLK_IOI_CK_BUFHCLK1" + ], + [ + "HCLK_IOB_CK_BUFHCLK5", + "HCLK_IOI_CK_BUFHCLK5" + ], + [ + "HCLK_IOB_CK_BUFHCLK0", + "HCLK_IOI_CK_BUFHCLK0" + ], + [ + "HCLK_IOB_CK_BUFHCLK8", + "HCLK_IOI_CK_BUFHCLK8" + ], + [ + "HCLK_IOB_CK_BUFRCLK0", + "HCLK_IOI_CK_BUFRCLK0" + ], + [ + "HCLK_IOB_CK_BUFHCLK9", + "HCLK_IOI_CK_BUFHCLK9" + ], + [ + "HCLK_IOB_PERFCLK1", + "HCLK_IOI_IOCLK_PLL1" + ], + [ + "HCLK_IOB_CK_BUFRCLK3", + "HCLK_IOI_CK_BUFRCLK3" + ] + ], + "tile_types": [ + "HCLK_IOB", + "HCLK_IOI3" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "BRKH_INT_SR1END2_SLOW", + "SR1BEG2" + ], + [ + "BRKH_INT_SE6D0", + "SE6C0" + ], + [ + "BRKH_INT_NN6D2", + "NN6E2" + ], + [ + "BRKH_INT_SW6C1", + "SW6B1" + ], + [ + "BRKH_INT_NW6A3", + "NW6B3" + ], + [ + "BRKH_INT_SE6C1", + "SE6B1" + ], + [ + "BRKH_INT_LV17", + "LV18" + ], + [ + "BRKH_INT_NN6A3", + "NN6B3" + ], + [ + "BRKH_INT_SE6C0", + "SE6B0" + ], + [ + "BRKH_INT_LVB9", + "LVB9" + ], + [ + "BRKH_INT_SW6D0", + "SW6C0" + ], + [ + "BRKH_INT_SE6D1", + "SE6C1" + ], + [ + "BRKH_INT_SS2END3", + "SS2A3" + ], + [ + "BRKH_INT_LVB4", + "LVB4" + ], + [ + "BRKH_INT_LV0", + "LV1" + ], + [ + "BRKH_INT_SS6B0", + "SS6A0" + ], + [ + "BRKH_INT_SE2A3", + "SE2BEG3" + ], + [ + "BRKH_INT_ER1BEG_S0", + "ER1BEG0" + ], + [ + "BRKH_INT_WW2END3", + "WW2END_N0_3" + ], + [ + "BRKH_INT_SS6END_N0_3", + "SS6END_N0_3" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_4", + "FAN_BOUNCE4" + ], + [ + "BRKH_INT_NE6D2", + "NE6E2" + ], + [ + "BRKH_INT_SW2A1", + "SW2BEG1" + ], + [ + "BRKH_INT_SR1END_N3_3", + "SR1END_N3_3" + ], + [ + "BRKH_INT_SS6C0", + "SS6B0" + ], + [ + "BRKH_INT_NE2BEG1", + "NE2A1" + ], + [ + "BRKH_INT_SL1END2_SLOW", + "SL1BEG2" + ], + [ + "BRKH_INT_NR1BEG1_SLOW", + "NR1END1" + ], + [ + "BRKH_INT_LVB7", + "LVB7" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_6", + "FAN_BOUNCE6" + ], + [ + "BRKH_INT_NN6A0", + "NN6B0" + ], + [ + "BRKH_INT_SE2A1", + "SE2BEG1" + ], + [ + "BRKH_INT_NN2BEG2", + "NN2A2" + ], + [ + "BRKH_INT_NW6C0", + "NW6D0" + ], + [ + "BRKH_INT_LV1", + "LV2" + ], + [ + "BRKH_INT_NN6BEG2", + "NN6A2" + ], + [ + "BRKH_INT_LV8", + "LV9" + ], + [ + "BRKH_INT_SE6C2", + "SE6B2" + ], + [ + "BRKH_INT_SS2END1", + "SS2A1" + ], + [ + "BRKH_INT_NW2BEG0", + "NW2A0" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_0", + "FAN_BOUNCE0" + ], + [ + "BRKH_INT_LV11", + "LV12" + ], + [ + "BRKH_INT_NE6A0", + "NE6B0" + ], + [ + "BRKH_INT_SW6C0", + "SW6B0" + ], + [ + "BRKH_INT_NE2END_S3_0", + "NE2END0" + ], + [ + "BRKH_INT_NE2BEG0", + "NE2A0" + ], + [ + "BRKH_INT_SW6E3", + "SW6D3" + ], + [ + "BRKH_INT_NW6END_S0_0", + "NW6END0" + ], + [ + "BRKH_INT_BYP_BOUNCE7", + "BYP_BOUNCE_N3_7" + ], + [ + "BRKH_INT_NE6B0", + "NE6C0" + ], + [ + "BRKH_INT_NW6B2", + "NW6C2" + ], + [ + "BRKH_INT_SS6D2", + "SS6C2" + ], + [ + "BRKH_INT_NE6C0", + "NE6D0" + ], + [ + "BRKH_INT_LV3", + "LV4" + ], + [ + "BRKH_INT_SS2A2", + "SS2BEG2" + ], + [ + "BRKH_INT_SS2A3", + "SS2BEG3" + ], + [ + "BRKH_INT_SS6A2", + "SS6BEG2" + ], + [ + "BRKH_INT_NN2BEG3", + "NN2A3" + ], + [ + "BRKH_INT_SW6E1", + "SW6D1" + ], + [ + "BRKH_INT_NE2BEG2", + "NE2A2" + ], + [ + "BRKH_INT_LVB8", + "LVB8" + ], + [ + "BRKH_INT_EL1BEG3", + "EL1BEG_N3" + ], + [ + "BRKH_INT_NE6D1", + "NE6E1" + ], + [ + "BRKH_INT_SW6E2", + "SW6D2" + ], + [ + "BRKH_INT_NN6E3", + "NN6END3" + ], + [ + "BRKH_INT_NE6C2", + "NE6D2" + ], + [ + "BRKH_INT_SW6B3", + "SW6A3" + ], + [ + "BRKH_INT_NE6C3", + "NE6D3" + ], + [ + "BRKH_INT_SE6B3", + "SE6A3" + ], + [ + "BRKH_INT_NN6E2", + "NN6END2" + ], + [ + "BRKH_INT_NE6A1", + "NE6B1" + ], + [ + "BRKH_INT_SW6B0", + "SW6A0" + ], + [ + "BRKH_INT_NN6END_S1_0", + "NN6END0" + ], + [ + "BRKH_INT_LV16", + "LV17" + ], + [ + "BRKH_INT_BYP_BOUNCE6", + "BYP_BOUNCE_N3_6" + ], + [ + "BRKH_INT_SW6D3", + "SW6C3" + ], + [ + "BRKH_INT_NN2END_S2_0", + "NN2END0" + ], + [ + "BRKH_INT_NN6BEG3", + "NN6A3" + ], + [ + "BRKH_INT_SS6C1", + "SS6B1" + ], + [ + "BRKH_INT_SS6END1", + "SS6E1" + ], + [ + "BRKH_INT_NW6D3", + "NW6E3" + ], + [ + "BRKH_INT_SL1END1_SLOW", + "SL1BEG1" + ], + [ + "BRKH_INT_SE6C3", + "SE6B3" + ], + [ + "BRKH_INT_SS2A0", + "SS2BEG0" + ], + [ + "BRKH_INT_LVB6", + "LVB6" + ], + [ + "BRKH_INT_NN6E1", + "NN6END1" + ], + [ + "BRKH_INT_NN6C0", + "NN6D0" + ], + [ + "BRKH_INT_NN6D3", + "NN6E3" + ], + [ + "BRKH_INT_NN6D1", + "NN6E1" + ], + [ + "BRKH_INT_SE6E1", + "SE6D1" + ], + [ + "BRKH_INT_SS2END2", + "SS2A2" + ], + [ + "BRKH_INT_NN6B2", + "NN6C2" + ], + [ + "BRKH_INT_SS2A1", + "SS2BEG1" + ], + [ + "BRKH_INT_NR1BEG3_SLOW", + "NR1END3" + ], + [ + "BRKH_INT_NN6B0", + "NN6C0" + ], + [ + "BRKH_INT_NW2BEG2", + "NW2A2" + ], + [ + "BRKH_INT_NE6D0", + "NE6E0" + ], + [ + "BRKH_INT_NL1BEG1_SLOW", + "NL1END1" + ], + [ + "BRKH_INT_NW6D0", + "NW6E0" + ], + [ + "BRKH_INT_SS6C3", + "SS6B3" + ], + [ + "BRKH_INT_NE6B3", + "NE6C3" + ], + [ + "BRKH_INT_SW6C2", + "SW6B2" + ], + [ + "BRKH_INT_SW6D2", + "SW6C2" + ], + [ + "BRKH_INT_SS6A0", + "SS6BEG0" + ], + [ + "BRKH_INT_BYP_BOUNCE3", + "BYP_BOUNCE_N3_3" + ], + [ + "BRKH_INT_SS2END0", + "SS2A0" + ], + [ + "BRKH_INT_SE6D2", + "SE6C2" + ], + [ + "BRKH_INT_NN6A1", + "NN6B1" + ], + [ + "BRKH_INT_NW6C2", + "NW6D2" + ], + [ + "BRKH_INT_NW6A1", + "NW6B1" + ], + [ + "BRKH_INT_NW6B1", + "NW6C1" + ], + [ + "BRKH_INT_LVB12", + "LVB12" + ], + [ + "BRKH_INT_SS6E3", + "SS6D3" + ], + [ + "BRKH_INT_NN6C3", + "NN6D3" + ], + [ + "BRKH_INT_SE6D3", + "SE6C3" + ], + [ + "BRKH_INT_WW4END_S0_0", + "WW4END0" + ], + [ + "BRKH_INT_NN2BEG0", + "NN2A0" + ], + [ + "BRKH_INT_NE6B1", + "NE6C1" + ], + [ + "BRKH_INT_LVB11", + "LVB11" + ], + [ + "BRKH_INT_SS6D0", + "SS6C0" + ], + [ + "BRKH_INT_SS6END2", + "SS6E2" + ], + [ + "BRKH_INT_LV4", + "LV5" + ], + [ + "BRKH_INT_NW6C1", + "NW6D1" + ], + [ + "BRKH_INT_NN6E0", + "NN6END0" + ], + [ + "BRKH_INT_NN6B3", + "NN6C3" + ], + [ + "BRKH_INT_NE6D3", + "NE6E3" + ], + [ + "BRKH_INT_LV7", + "LV8" + ], + [ + "BRKH_INT_NW2END_S0_0", + "NW2END0" + ], + [ + "BRKH_INT_NE6A2", + "NE6B2" + ], + [ + "BRKH_INT_NW6B0", + "NW6C0" + ], + [ + "BRKH_INT_WL1BEG3", + "WL1BEG_N3" + ], + [ + "BRKH_INT_LV5", + "LV6" + ], + [ + "BRKH_INT_SW2A0", + "SW2BEG0" + ], + [ + "BRKH_INT_SW6END3", + "SW6END_N0_3" + ], + [ + "BRKH_INT_NN2A0", + "NN2END0" + ], + [ + "BRKH_INT_NN6C2", + "NN6D2" + ], + [ + "BRKH_INT_SS6A1", + "SS6BEG1" + ], + [ + "BRKH_INT_NR1BEG0_SLOW", + "NR1END0" + ], + [ + "BRKH_INT_LV12", + "LV13" + ], + [ + "BRKH_INT_LVB5", + "LVB5" + ], + [ + "BRKH_INT_SE6E3", + "SE6D3" + ], + [ + "BRKH_INT_SW6B2", + "SW6A2" + ], + [ + "BRKH_INT_SW2END3", + "SW2END_N0_3" + ], + [ + "BRKH_INT_SE6B1", + "SE6A1" + ], + [ + "BRKH_INT_NN2A3", + "NN2END3" + ], + [ + "BRKH_INT_NW6D1", + "NW6E1" + ], + [ + "BRKH_INT_SW6D1", + "SW6C1" + ], + [ + "BRKH_INT_WR1END_S1_0", + "WR1END0" + ], + [ + "BRKH_INT_SS2END_N0_3", + "SS2END_N0_3" + ], + [ + "BRKH_INT_SS6B1", + "SS6A1" + ], + [ + "BRKH_INT_SE2A0", + "SE2BEG0" + ], + [ + "BRKH_INT_ER1END3", + "ER1END_N3_3" + ], + [ + "BRKH_INT_NW6C3", + "NW6D3" + ], + [ + "BRKH_INT_NW6D2", + "NW6E2" + ], + [ + "BRKH_INT_SS6END3", + "SS6E3" + ], + [ + "BRKH_INT_NN2BEG1", + "NN2A1" + ], + [ + "BRKH_INT_LVB1", + "LVB1" + ], + [ + "BRKH_INT_SR1END1_SLOW", + "SR1BEG1" + ], + [ + "BRKH_INT_WR1BEG_S0", + "WR1BEG0" + ], + [ + "BRKH_INT_SW6C3", + "SW6B3" + ], + [ + "BRKH_INT_NN6BEG1", + "NN6A1" + ], + [ + "BRKH_INT_NL1BEG0_SLOW", + "NL1END0" + ], + [ + "BRKH_INT_SW2A3", + "SW2BEG3" + ], + [ + "BRKH_INT_SS6B3", + "SS6A3" + ], + [ + "BRKH_INT_SE2A2", + "SE2BEG2" + ], + [ + "BRKH_INT_NW2BEG3", + "NW2A3" + ], + [ + "BRKH_INT_LVB2", + "LVB2" + ], + [ + "BRKH_INT_SS6B2", + "SS6A2" + ], + [ + "BRKH_INT_NW6A0", + "NW6B0" + ], + [ + "BRKH_INT_NN2A1", + "NN2END1" + ], + [ + "BRKH_INT_SR1END3_SLOW", + "SR1BEG3" + ], + [ + "BRKH_INT_NN6C1", + "NN6D1" + ], + [ + "BRKH_INT_LVB10", + "LVB10" + ], + [ + "BRKH_INT_SE6B2", + "SE6A2" + ], + [ + "BRKH_INT_SS6C2", + "SS6B2" + ], + [ + "BRKH_INT_SW2A2", + "SW2BEG2" + ], + [ + "BRKH_INT_SS6E0", + "SS6D0" + ], + [ + "BRKH_INT_SS6E2", + "SS6D2" + ], + [ + "BRKH_INT_LV2", + "LV3" + ], + [ + "BRKH_INT_EL1END_S3_0", + "EL1END0" + ], + [ + "BRKH_INT_LV9", + "LV10" + ], + [ + "BRKH_INT_NW2BEG1", + "NW2A1" + ], + [ + "BRKH_INT_NW6A2", + "NW6B2" + ], + [ + "BRKH_INT_SS6END0", + "SS6E0" + ], + [ + "BRKH_INT_NN6BEG0", + "NN6A0" + ], + [ + "BRKH_INT_NR1BEG2_SLOW", + "NR1END2" + ], + [ + "BRKH_INT_NN6A2", + "NN6B2" + ], + [ + "BRKH_INT_LV10", + "LV11" + ], + [ + "BRKH_INT_NW6B3", + "NW6C3" + ], + [ + "BRKH_INT_SW6B1", + "SW6A1" + ], + [ + "BRKH_INT_SS6E1", + "SS6D1" + ], + [ + "BRKH_INT_NE6C1", + "NE6D1" + ], + [ + "BRKH_INT_LV13", + "LV14" + ], + [ + "BRKH_INT_LV14", + "LV15" + ], + [ + "BRKH_INT_WL1END3", + "WL1END_N1_3" + ], + [ + "BRKH_INT_NN6D0", + "NN6E0" + ], + [ + "BRKH_INT_LVB3", + "LVB3" + ], + [ + "BRKH_INT_SE6E2", + "SE6D2" + ], + [ + "BRKH_INT_NE6A3", + "NE6B3" + ], + [ + "BRKH_INT_NL1BEG2_SLOW", + "NL1END2" + ], + [ + "BRKH_INT_LV6", + "LV7" + ], + [ + "BRKH_INT_SS6D3", + "SS6C3" + ], + [ + "BRKH_INT_BYP_BOUNCE2", + "BYP_BOUNCE_N3_2" + ], + [ + "BRKH_INT_LV15", + "LV16" + ], + [ + "BRKH_INT_NL1END_S3_0", + "NL1END0" + ], + [ + "BRKH_INT_SS6D1", + "SS6C1" + ], + [ + "BRKH_INT_NN2A2", + "NN2END2" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_2", + "FAN_BOUNCE2" + ], + [ + "BRKH_INT_SL1END3_SLOW", + "SL1BEG3" + ], + [ + "BRKH_INT_SE6E0", + "SE6D0" + ], + [ + "BRKH_INT_SW6E0", + "SW6D0" + ], + [ + "BRKH_INT_SL1END0_SLOW", + "SL1BEG0" + ], + [ + "BRKH_INT_SE6B0", + "SE6A0" + ], + [ + "BRKH_INT_NE2BEG3", + "NE2A3" + ], + [ + "BRKH_INT_NN6B1", + "NN6C1" + ], + [ + "BRKH_INT_SS6A3", + "SS6BEG3" + ], + [ + "BRKH_INT_NE6B2", + "NE6C2" + ] + ], + "tile_types": [ + "BRKH_INT", + "INT_R" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B21_3", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_LOGIC_OUTS_B9_3", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX40_3", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B10_3", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_CTRL0_3", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_BYP0_3", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_BYP3_3", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_BYP5_3", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX2_3", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_FAN2_3", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_FAN1_3", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B8_3", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_LOGIC_OUTS_B13_3", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_CTRL1_3", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX47_3", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_LOGIC_OUTS_B0_3", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX9_3", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX32_3", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX25_3", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX39_3", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX4_3", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX6_3", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX14_3", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX36_3", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX43_3", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX46_3", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_FAN5_3", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX16_3", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX31_3", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B2_3", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_LOGIC_OUTS_B4_3", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B3_3", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX29_3", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_FAN4_3", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX3_3", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX5_3", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B23_3", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX45_3", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX41_3", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX12_3", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX42_3", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_FAN7_3", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B20_3", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX23_3", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_LOGIC_OUTS_B11_3", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_IMUX30_3", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX33_3", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX10_3", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX27_3", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX7_3", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX37_3", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX38_3", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX26_3", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_CLK1_3", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX17_3", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX21_3", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_LOGIC_OUTS_B6_3", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX18_3", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_FAN6_3", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_LOGIC_OUTS_B22_3", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B12_3", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX35_3", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_LOGIC_OUTS_B18_3", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX44_3", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX34_3", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX15_3", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX13_3", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP6_3", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX0_3", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX22_3", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX20_3", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_LOGIC_OUTS_B14_3", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_CLK0_3", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX24_3", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B7_3", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_FAN3_3", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX1_3", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_LOGIC_OUTS_B16_3", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B17_3", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B5_3", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_BYP1_3", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX28_3", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_LOGIC_OUTS_B1_3", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_3", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_BYP2_3", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_BYP4_3", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX8_3", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_LOGIC_OUTS_B15_3", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX19_3", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX11_3", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP7_3", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_FAN0_3", + "VBRK_EXT_FAN0" + ] + ], + "tile_types": [ + "GTX_CHANNEL_3", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ] + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_L_BOT_UTURN" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "FAN_BOUNCE4" + ], + [ + "B_TERM_UTURN_INT_SW6B0", + "NW6C3" + ], + [ + "B_TERM_UTURN_INT_SS6B1", + "NN6C2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG0", + "SL1BEG0" + ], + [ + "B_TERM_UTURN_INT_LVB1", + "LVB11" + ], + [ + "B_TERM_UTURN_INT_SS6C2", + "SS6C2" + ], + [ + "B_TERM_UTURN_INT_LV6", + "LV6" + ], + [ + "B_TERM_UTURN_INT_SS6E0", + "SS6E0" + ], + [ + "B_TERM_UTURN_INT_SW6A3", + "NW6B0" + ], + [ + "B_TERM_UTURN_INT_SW6B0", + "SW6B0" + ], + [ + "B_TERM_UTURN_INT_SS6BEG0", + "NN6A3" + ], + [ + "B_TERM_UTURN_INT_LV8", + "LV11" + ], + [ + "B_TERM_UTURN_INT_LV6", + "LV13" + ], + [ + "B_TERM_UTURN_INT_SS6C2", + "NN6D1" + ], + [ + "B_TERM_UTURN_INT_SS6A2", + "NN6B1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG0", + "SS2BEG0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG1", + "NL1END2" + ], + [ + "B_TERM_UTURN_INT_SW6B1", + "NW6C2" + ], + [ + "B_TERM_UTURN_INT_SS6C3", + "SS6C3" + ], + [ + "B_TERM_UTURN_INT_ER1END_N3_3", + "ER1END_N3_3" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "FAN_BOUNCE0" + ], + [ + "B_TERM_UTURN_INT_SS6A3", + "NN6B0" + ], + [ + "B_TERM_UTURN_INT_SE6D1", + "NE6E2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG1", + "NR1END2" + ], + [ + "B_TERM_UTURN_INT_LV3", + "LV3" + ], + [ + "B_TERM_UTURN_INT_SW6C0", + "SW6C0" + ], + [ + "B_TERM_UTURN_INT_SE6A0", + "SE6A0" + ], + [ + "B_TERM_UTURN_INT_LV9", + "LV10" + ], + [ + "B_TERM_UTURN_INT_SW6A0", + "NW6B3" + ], + [ + "B_TERM_UTURN_INT_LV18", + "LV18" + ], + [ + "B_TERM_UTURN_INT_SS6E0", + "NN6END3" + ], + [ + "B_TERM_UTURN_INT_WR1END0", + "WR1END0" + ], + [ + "B_TERM_UTURN_INT_SE6A2", + "SE6A2" + ], + [ + "B_TERM_UTURN_INT_SS6D1", + "SS6D1" + ], + [ + "B_TERM_UTURN_INT_SE6B0", + "SE6B0" + ], + [ + "B_TERM_UTURN_INT_LV7", + "LV7" + ], + [ + "B_TERM_UTURN_INT_LV8", + "LV8" + ], + [ + "B_TERM_UTURN_INT_LV4", + "LV15" + ], + [ + "B_TERM_UTURN_INT_SS6A3", + "SS6A3" + ], + [ + "B_TERM_UTURN_INT_SW6B3", + "NW6C0" + ], + [ + "B_TERM_UTURN_INT_ER1BEG0", + "EL1BEG_N3" + ], + [ + "B_TERM_UTURN_INT_SE6B2", + "SE6B2" + ], + [ + "B_TERM_UTURN_INT_SE6C2", + "SE6C2" + ], + [ + "B_TERM_UTURN_INT_SE6B0", + "NE6C3" + ], + [ + "B_TERM_UTURN_INT_SE6D0", + "NE6E3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG3", + "NN6A0" + ], + [ + "B_TERM_UTURN_INT_SW6D3", + "NW6E0" + ], + [ + "B_TERM_UTURN_INT_LVB1", + "LVB2" + ], + [ + "B_TERM_UTURN_INT_SS6BEG0", + "SS6BEG0" + ], + [ + "B_TERM_UTURN_INT_SE6D2", + "NE6E1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG1", + "NN2A2" + ], + [ + "B_TERM_UTURN_INT_SS6D1", + "NN6E2" + ], + [ + "B_TERM_UTURN_INT_SE6C3", + "SE6C3" + ], + [ + "B_TERM_UTURN_INT_SS2A2", + "NN2END1" + ], + [ + "B_TERM_UTURN_INT_SE6D1", + "SE6D1" + ], + [ + "B_TERM_UTURN_INT_SS6D0", + "NN6E3" + ], + [ + "B_TERM_UTURN_INT_SS6B3", + "NN6C0" + ], + [ + "B_TERM_UTURN_INT_SE6A1", + "NE6B2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG2", + "SL1BEG2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "FAN_BOUNCE6" + ], + [ + "B_TERM_UTURN_INT_LVB3", + "LVB4" + ], + [ + "B_TERM_UTURN_INT_SE6C3", + "NE6D0" + ], + [ + "B_TERM_UTURN_INT_SE6A0", + "NE6B3" + ], + [ + "B_TERM_UTURN_INT_SE6A2", + "NE6B1" + ], + [ + "B_TERM_UTURN_INT_SS6E3", + "SS6E3" + ], + [ + "B_TERM_UTURN_INT_SS2A0", + "SS2A0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG2", + "SS2BEG2" + ], + [ + "B_TERM_UTURN_INT_ER1BEG0", + "ER1BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG3", + "NR1END0" + ], + [ + "B_TERM_UTURN_INT_SW6A3", + "SW6A3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG3", + "NW2A0" + ], + [ + "B_TERM_UTURN_INT_SS6C1", + "NN6D2" + ], + [ + "B_TERM_UTURN_INT_SE6C0", + "NE6D3" + ], + [ + "B_TERM_UTURN_INT_SW6C0", + "NW6D3" + ], + [ + "B_TERM_UTURN_INT_SW6B2", + "SW6B2" + ], + [ + "B_TERM_UTURN_INT_SS6C1", + "SS6C1" + ], + [ + "B_TERM_UTURN_INT_SS6D3", + "SS6D3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG1", + "SE2BEG1" + ], + [ + "B_TERM_UTURN_INT_SS6B1", + "SS6B1" + ], + [ + "B_TERM_UTURN_INT_LV4", + "LV4" + ], + [ + "B_TERM_UTURN_INT_SW6D0", + "NW6E3" + ], + [ + "B_TERM_UTURN_INT_SS6B0", + "SS6B0" + ], + [ + "B_TERM_UTURN_INT_LV5", + "LV14" + ], + [ + "B_TERM_UTURN_INT_SE2BEG1", + "NE2A2" + ], + [ + "B_TERM_UTURN_INT_SW6D2", + "NW6E1" + ], + [ + "B_TERM_UTURN_INT_SS6BEG3", + "SS6BEG3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG0", + "SE2BEG0" + ], + [ + "B_TERM_UTURN_INT_SW6B3", + "SW6B3" + ], + [ + "B_TERM_UTURN_INT_SW6C1", + "SW6C1" + ], + [ + "B_TERM_UTURN_INT_SE6C1", + "NE6D2" + ], + [ + "B_TERM_UTURN_INT_LV3", + "LV16" + ], + [ + "B_TERM_UTURN_INT_SW6A2", + "NW6B1" + ], + [ + "B_TERM_UTURN_INT_SE6D3", + "SE6D3" + ], + [ + "B_TERM_UTURN_INT_SW6D2", + "SW6D2" + ], + [ + "B_TERM_UTURN_INT_SR1BEG2", + "NL1END1" + ], + [ + "B_TERM_UTURN_INT_SS2A3", + "SS2A3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG2", + "SS6BEG2" + ], + [ + "B_TERM_UTURN_INT_SS6E2", + "SS6E2" + ], + [ + "B_TERM_UTURN_INT_SW6C1", + "NW6D2" + ], + [ + "B_TERM_UTURN_INT_SS6E1", + "SS6E1" + ], + [ + "B_TERM_UTURN_INT_SS6E3", + "NN6END0" + ], + [ + "B_TERM_UTURN_INT_LVB0", + "LVB1" + ], + [ + "B_TERM_UTURN_INT_SE6D0", + "SE6D0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG2", + "SR1BEG2" + ], + [ + "B_TERM_UTURN_INT_SS6B2", + "SS6B2" + ], + [ + "B_TERM_UTURN_INT_SS6A1", + "SS6A1" + ], + [ + "B_TERM_UTURN_INT_WR1BEG0", + "WL1BEG_N3" + ], + [ + "B_TERM_UTURN_INT_SW6D1", + "SW6D1" + ], + [ + "B_TERM_UTURN_INT_SS6B0", + "NN6C3" + ], + [ + "B_TERM_UTURN_INT_SS6C0", + "SS6C0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG3", + "SS2BEG3" + ], + [ + "B_TERM_UTURN_INT_SS2BEG1", + "SS2BEG1" + ], + [ + "B_TERM_UTURN_INT_SW6C2", + "SW6C2" + ], + [ + "B_TERM_UTURN_INT_SW2BEG0", + "SW2BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG1", + "SL1BEG1" + ], + [ + "B_TERM_UTURN_INT_LV18", + "LV1" + ], + [ + "B_TERM_UTURN_INT_SS6D3", + "NN6E0" + ], + [ + "B_TERM_UTURN_INT_LVB5", + "LVB7" + ], + [ + "B_TERM_UTURN_INT_SS6A0", + "NN6B3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG1", + "SW2BEG1" + ], + [ + "B_TERM_UTURN_INT_LVB4", + "LVB8" + ], + [ + "B_TERM_UTURN_INT_SW6A1", + "NW6B2" + ], + [ + "B_TERM_UTURN_INT_SS6C3", + "NN6D0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG2", + "NE2A1" + ], + [ + "B_TERM_UTURN_INT_SS6A0", + "SS6A0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG1", + "SR1BEG1" + ], + [ + "B_TERM_UTURN_INT_SW6C2", + "NW6D1" + ], + [ + "B_TERM_UTURN_INT_LV7", + "LV12" + ], + [ + "B_TERM_UTURN_INT_LVB3", + "LVB9" + ], + [ + "B_TERM_UTURN_INT_SW6C3", + "SW6C3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG1", + "SS6BEG1" + ], + [ + "B_TERM_UTURN_INT_SR1BEG3", + "SR1BEG3" + ], + [ + "B_TERM_UTURN_INT_SE6D3", + "NE6E0" + ], + [ + "B_TERM_UTURN_INT_SE6B3", + "SE6B3" + ], + [ + "B_TERM_UTURN_INT_WR1END0", + "WL1END_N1_3" + ], + [ + "B_TERM_UTURN_INT_SW6D0", + "SW6D0" + ], + [ + "B_TERM_UTURN_INT_LV2", + "LV17" + ], + [ + "B_TERM_UTURN_INT_SW2BEG0", + "NW2A3" + ], + [ + "B_TERM_UTURN_INT_SW6A2", + "SW6A2" + ], + [ + "B_TERM_UTURN_INT_LVB0", + "LVB12" + ], + [ + "B_TERM_UTURN_INT_SR1BEG3", + "NL1END0" + ], + [ + "B_TERM_UTURN_INT_LVB2", + "LVB10" + ], + [ + "B_TERM_UTURN_INT_SS6E1", + "NN6END2" + ], + [ + "B_TERM_UTURN_INT_SS2A0", + "NN2END3" + ], + [ + "B_TERM_UTURN_INT_SW6C3", + "NW6D0" + ], + [ + "B_TERM_UTURN_INT_SE6B2", + "NE6C1" + ], + [ + "B_TERM_UTURN_INT_SW2BEG1", + "NW2A2" + ], + [ + "B_TERM_UTURN_INT_SS6C0", + "NN6D3" + ], + [ + "B_TERM_UTURN_INT_SS6A1", + "NN6B2" + ], + [ + "B_TERM_UTURN_INT_SS6A2", + "SS6A2" + ], + [ + "B_TERM_UTURN_INT_SS6E2", + "NN6END1" + ], + [ + "B_TERM_UTURN_INT_SS6D2", + "SS6D2" + ], + [ + "B_TERM_UTURN_INT_SS6B2", + "NN6C1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "BYP_BOUNCE_N3_7" + ], + [ + "B_TERM_UTURN_INT_SW6D1", + "NW6E2" + ], + [ + "B_TERM_UTURN_INT_ER1END_N3_3", + "EL1END0" + ], + [ + "B_TERM_UTURN_INT_SS2A3", + "NN2END0" + ], + [ + "B_TERM_UTURN_INT_LV9", + "LV9" + ], + [ + "B_TERM_UTURN_INT_SS6D2", + "NN6E1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "BYP_BOUNCE_N3_6" + ], + [ + "B_TERM_UTURN_INT_SS2BEG2", + "NN2A1" + ], + [ + "B_TERM_UTURN_INT_SE6B1", + "SE6B1" + ], + [ + "B_TERM_UTURN_INT_SW2BEG3", + "SW2BEG3" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "BYP_BOUNCE_N3_2" + ], + [ + "B_TERM_UTURN_INT_SE6C1", + "SE6C1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "BYP_BOUNCE_N3_3" + ], + [ + "B_TERM_UTURN_INT_SS6D0", + "SS6D0" + ], + [ + "B_TERM_UTURN_INT_SW2BEG2", + "NW2A1" + ], + [ + "B_TERM_UTURN_INT_LV2", + "LV2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "FAN_BOUNCE2" + ], + [ + "B_TERM_UTURN_INT_SS6BEG2", + "NN6A1" + ], + [ + "B_TERM_UTURN_INT_SS2A1", + "NN2END2" + ], + [ + "B_TERM_UTURN_INT_SE6B3", + "NE6C0" + ], + [ + "B_TERM_UTURN_INT_LV5", + "LV5" + ], + [ + "B_TERM_UTURN_INT_SE2BEG3", + "NE2A0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG3", + "NN2A0" + ], + [ + "B_TERM_UTURN_INT_SW6B2", + "NW6C1" + ], + [ + "B_TERM_UTURN_INT_SW6A0", + "SW6A0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG2", + "NR1END1" + ], + [ + "B_TERM_UTURN_INT_SE2BEG0", + "NE2A3" + ], + [ + "B_TERM_UTURN_INT_SW6B1", + "SW6B1" + ], + [ + "B_TERM_UTURN_INT_SS2A2", + "SS2A2" + ], + [ + "B_TERM_UTURN_INT_SS6B3", + "SS6B3" + ], + [ + "B_TERM_UTURN_INT_SE6D2", + "SE6D2" + ], + [ + "B_TERM_UTURN_INT_LVB2", + "LVB3" + ], + [ + "B_TERM_UTURN_INT_SW6END_N0_3", + "SW6END_N0_3" + ], + [ + "B_TERM_UTURN_INT_SE6A3", + "SE6A3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG2", + "SW2BEG2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG0", + "NR1END3" + ], + [ + "B_TERM_UTURN_INT_SE6C2", + "NE6D1" + ], + [ + "B_TERM_UTURN_INT_WR1BEG0", + "WR1BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG3", + "SL1BEG3" + ], + [ + "B_TERM_UTURN_INT_SE6C0", + "SE6C0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG0", + "NN2A3" + ], + [ + "B_TERM_UTURN_INT_SW6END_N0_3", + "NW6END0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG3", + "SE2BEG3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG1", + "NN6A2" + ], + [ + "B_TERM_UTURN_INT_LVB4", + "LVB5" + ], + [ + "B_TERM_UTURN_INT_SE2BEG2", + "SE2BEG2" + ], + [ + "B_TERM_UTURN_INT_SE6A1", + "SE6A1" + ], + [ + "B_TERM_UTURN_INT_SE6B1", + "NE6C2" + ], + [ + "B_TERM_UTURN_INT_SW6D3", + "SW6D3" + ], + [ + "B_TERM_UTURN_INT_LVB5", + "LVB6" + ], + [ + "B_TERM_UTURN_INT_SE6A3", + "NE6B0" + ], + [ + "B_TERM_UTURN_INT_SW6A1", + "SW6A1" + ], + [ + "B_TERM_UTURN_INT_SS2A1", + "SS2A1" + ] + ], + "tile_types": [ + "BRKH_B_TERM_INT", + "INT_R" + ] + }, + { + "grid_deltas": [ + 1, + -5 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4BEG2_5", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE2A2_5", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_IMUX6_5", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_EL1BEG1_5", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_WW4B1_5", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_BYP2_5", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_FAN4_5", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_SW4END2_5", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_EE2A3_5", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EE2BEG0_5", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX0_5", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_EE2BEG1_5", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX47_5", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX28_5", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_NW4END2_5", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_WW4B2_5", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_LH4_5", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_LH8_5", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_EE2BEG2_5", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_EE4B0_5", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_NW2A1_5", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_WL1END3_5", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_BYP6_5", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX44_5", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_NE4BEG1_5", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_NE2A0_5", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_EE4A2_5", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX2_5", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_SW2A1_5", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_SW4END0_5", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX26_5", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_WW4B3_5", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_FAN1_5", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_WR1END2_5", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_WR1END3_5", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX32_5", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_NE2A1_5", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_WW2END3_5", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW2END2_5", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_FAN6_5", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_FAN0_5", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_NE2A3_5", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_EE4BEG3_5", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_SE4BEG3_5", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_ER1BEG1_5", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_WR1END0_5", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EE4C0_5", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_IMUX41_5", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX19_5", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_IMUX24_5", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_WW4END1_5", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_WW4A3_5", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_SW4A3_5", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EL1BEG2_5", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NW4A3_5", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SE4C2_5", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_LH5_5", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_ER1BEG0_5", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_IMUX45_5", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_LH3_5", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX36_5", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_NE4BEG0_5", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX3_5", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_5", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_5", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_SW2A0_5", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_LH2_5", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EL1BEG0_5", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_WL1END2_5", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WW4END0_5", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_5", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_SE2A1_5", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NW4A0_5", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NW4END3_5", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_NW2A3_5", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_SW4A2_5", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_IMUX4_5", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX5_5", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_NW4A1_5", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_EE4B3_5", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_IMUX33_5", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_EE4C1_5", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_WW4B0_5", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_SW4END3_5", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX7_5", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_WW4C2_5", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX22_5", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW2A1_5", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_IMUX9_5", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_WL1END0_5", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_IMUX14_5", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_SE4C1_5", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX30_5", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_ER1BEG2_5", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX38_5", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX1_5", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX43_5", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_SW4A1_5", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_BYP4_5", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_EE4A0_5", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_NE4C0_5", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_BYP1_5", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW4END2_5", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_BYP0_5", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_NW4A2_5", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_EE4BEG0_5", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_IMUX18_5", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX8_5", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_LH1_5", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NE4BEG3_5", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX25_5", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_SW4A0_5", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_CLK1_5", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_NW2A2_5", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW4A2_5", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_WW4C1_5", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_CTRL1_5", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_EE4B2_5", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX37_5", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_FAN2_5", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_5", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_SE4C0_5", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_5", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_WW4C0_5", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX11_5", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_LH7_5", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_IMUX16_5", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_NE4C1_5", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_LH12_5", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_SE2A3_5", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SE4BEG0_5", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_IMUX39_5", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_5", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_WL1END1_5", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_SW2A2_5", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_SE4BEG1_5", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_IMUX17_5", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_EE4C2_5", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_WW2A0_5", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_WW2END0_5", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_NE2A2_5", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_IMUX34_5", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_EE4BEG1_5", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_IMUX10_5", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SW2A3_5", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_SE4C3_5", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_BYP7_5", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_EE4C3_5", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE4A3_5", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_WW2A3_5", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_NW4END0_5", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX35_5", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_5", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_IMUX31_5", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_BYP5_5", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_EE2A1_5", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX13_5", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_IMUX12_5", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX42_5", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_BYP3_5", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_NE4C2_5", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_WW4A1_5", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_WR1END1_5", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_FAN5_5", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SE2A2_5", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_SW4END1_5", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_FAN3_5", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_NE4C3_5", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_IMUX20_5", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_WW4END3_5", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_EE2A0_5", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_EE4A1_5", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX23_5", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_SE4BEG2_5", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE4B1_5", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_IMUX40_5", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_FAN7_5", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_LH6_5", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_WW2END1_5", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_NW4END1_5", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SE2A0_5", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_LH11_5", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_IMUX27_5", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX21_5", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_LH9_5", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_5", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_EL1BEG3_5", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_NE4BEG2_5", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW4C3_5", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NW2A0_5", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_IMUX46_5", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_CTRL0_5", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_EE2BEG3_5", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_CLK0_5", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX29_5", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX15_5", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_WW2A2_5", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_LH10_5", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_ER1BEG3_5", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_WW4A0_5", + "VFRAME_WW4A0" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 10 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4C2_0", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX20_0", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_WW4B3_0", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_WW4C0_0", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_EE4BEG3_0", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_WL1END1_0", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_LH4_0", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_SW4END0_0", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX23_0", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW2END0_0", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_SW2A2_0", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_WW2A2_0", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_WL1END0_0", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_IMUX0_0", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_IMUX11_0", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_FAN6_0", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX5_0", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_NW4END3_0", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_SE2A2_0", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_WW4A2_0", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_FAN4_0", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_LH7_0", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_NE4BEG1_0", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_FAN5_0", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SW4A3_0", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_IMUX24_0", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_NE2A1_0", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_SE4BEG3_0", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_WW4A3_0", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW4END1_0", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX32_0", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_BYP2_0", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_WW4C3_0", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_EE4A1_0", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_SW4A1_0", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_IMUX2_0", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_WW4C1_0", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_BYP0_0", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX44_0", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_SW4A2_0", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NE4BEG2_0", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_IMUX18_0", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_CTRL0_0", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_SE2A0_0", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_SW4END2_0", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_ER1BEG2_0", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_ER1BEG1_0", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_NE4C3_0", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_LH9_0", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_IMUX9_0", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX25_0", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_IMUX41_0", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_EL1BEG2_0", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NW2A1_0", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_IMUX14_0", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_NW4END2_0", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_IMUX4_0", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_WW2END1_0", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_CLK0_0", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX28_0", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX21_0", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_NW2A3_0", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NE4BEG0_0", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX7_0", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_IMUX17_0", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX10_0", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SW2A3_0", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_ER1BEG3_0", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_SE4BEG2_0", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_IMUX39_0", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_NW4END0_0", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_EL1BEG1_0", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_EE2BEG0_0", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_WW4B1_0", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_EE4BEG1_0", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_IMUX36_0", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_WW4END3_0", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_EL1BEG0_0", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_IMUX8_0", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_BYP7_0", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_CLK1_0", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_WW2A3_0", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX27_0", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX46_0", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_EE2A1_0", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_SE4C2_0", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_EE2BEG1_0", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_SW4END3_0", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_EE4B1_0", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_WW4B2_0", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_LH12_0", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_WW4A0_0", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_WL1END3_0", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_NW2A2_0", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_SW4A0_0", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_FAN0_0", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX29_0", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_NW4A3_0", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_FAN3_0", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_WW4C2_0", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_NW4A1_0", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_FAN1_0", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX42_0", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_LH5_0", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX31_0", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_WR1END1_0", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_LH6_0", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_SW2A0_0", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_SW4END1_0", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_EE4A3_0", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX38_0", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_WR1END2_0", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_EE2A2_0", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_WW4B0_0", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_EE2A3_0", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NE2A2_0", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WR1END0_0", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_FAN2_0", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_IMUX22_0", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX1_0", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_LH3_0", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_NE4BEG3_0", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX13_0", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_NW2A0_0", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_LH1_0", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NW4A0_0", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX19_0", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_LH2_0", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EE2BEG3_0", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX12_0", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_EE4C1_0", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX45_0", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_BYP6_0", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_SE4C0_0", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_WW2A0_0", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_IMUX47_0", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_WW4END2_0", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_EE4B2_0", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX6_0", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_WW4A1_0", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_SE4C3_0", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX34_0", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_BYP5_0", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_SE2A1_0", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_EE4C0_0", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_EE4B0_0", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WL1END2_0", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WW2A1_0", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_FAN7_0", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_EE4B3_0", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_IMUX15_0", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_WR1END3_0", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_SE4BEG0_0", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_ER1BEG0_0", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_NE4C0_0", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EL1BEG3_0", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_NW4A2_0", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_NE4C1_0", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_NE4C2_0", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_EE2A0_0", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_SE4C1_0", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_LH11_0", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_BYP1_0", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SE4BEG1_0", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE4BEG2_0", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX33_0", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_IMUX40_0", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_LH10_0", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_SE2A3_0", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_IMUX26_0", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_LH8_0", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_SW2A1_0", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WW2END3_0", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_NE2A0_0", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX3_0", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_BYP3_0", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_EE4A2_0", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_EE2BEG2_0", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX30_0", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_IMUX37_0", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_NW4END1_0", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_IMUX16_0", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX43_0", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_WW4END0_0", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX35_0", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_BYP4_0", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WW2END2_0", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_EE4A0_0", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_EE4C3_0", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_NE2A3_0", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_CTRL1_0", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_EE4BEG0_0", + "VFRAME_EE4BEG0" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + 7 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_PMV_R_CK_BUFG_CASC15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_PMV_R_CK_BUFG_CASC2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_PMV_R_CK_BUFG_CASC26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_PMV_R_CK_BUFG_CASC18" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_PMV_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_PMV_R_CK_BUFG_CASC23" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_PMV_R_CK_BUFG_CASC29" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_PMV_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_PMV_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_PMV_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_PMV_R_CK_BUFG_CASC14" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_PMV_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_PMV_R_CK_BUFG_CASC11" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_PMV_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_PMV_R_CK_BUFG_CASC31" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_PMV_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_PMV_R_CK_BUFG_CASC17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_PMV_R_CK_BUFG_CASC6" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_PMV_R_CK_BUFG_CASC4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_PMV_R_CK_BUFG_CASC9" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_PMV_R_CK_GCLK4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_PMV_R_CK_BUFG_CASC8" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_PMV_R_CK_BUFG_CASC30" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_PMV_R_CK_BUFG_CASC10" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_PMV_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_PMV_R_CK_BUFG_CASC27" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_PMV_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_PMV_R_CK_BUFG_CASC5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_PMV_R_CK_BUFG_CASC13" + ], + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_PMV_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_PMV_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_PMV_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_PMV_R_CK_BUFG_CASC24" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_PMV_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_PMV_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_PMV_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_PMV_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_PMV_R_CK_BUFG_CASC3" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_PMV_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_PMV_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_PMV_R_CK_BUFG_CASC12" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_PMV_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_PMV_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_PMV_R_CK_BUFG_CASC16" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_PMV_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_PMV_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_PMV_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_PMV_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_PMV_R_CK_BUFG_CASC1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_PMV_R_CK_BUFG_CASC20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_PMV_R_CK_BUFG_CASC21" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_PMV_R_CK_BUFG_CASC25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_PMV_R_CK_BUFG_CASC22" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_PMV_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_PMV_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_PMV_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_PMV_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_PMV_R_CK_BUFG_CASC7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_PMV_R_CK_BUFG_CASC0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_PMV_R_CK_BUFG_CASC28" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_PMV_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_PMV_R_CK_BUFG_CASC19" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_PMV_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_PMV_R_CK_GCLK15" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_PMV" + ] + }, + { + "grid_deltas": [ + 1, + -8 + ], + "wire_pairs": [ + [ + "CMT_PMV_BYP2", + "CMT_TOP_BYP2_0" + ], + [ + "CMT_PMV_IMUX4", + "CMT_TOP_IMUX4_0" + ], + [ + "CMT_PMV_EE4B0", + "CMT_TOP_EE4B0_0" + ], + [ + "CMT_PMV_SW2A1", + "CMT_TOP_SW2A1_0" + ], + [ + "CMT_PMV_FAN2", + "CMT_TOP_FAN2_0" + ], + [ + "CMT_PMV_IMUX7", + "CMT_TOP_IMUX7_0" + ], + [ + "CMT_PMV_EE4B2", + "CMT_TOP_EE4B2_0" + ], + [ + "CMT_PMV_LOGIC_OUTS10", + "CMT_TOP_LOGIC_OUTS_L_B10_0" + ], + [ + "CMT_PMV_ER1BEG1", + "CMT_TOP_ER1BEG1_0" + ], + [ + "CMT_PMV_IMUX46", + "CMT_TOP_IMUX46_0" + ], + [ + "CMT_PMV_EE2BEG0", + "CMT_TOP_EE2BEG0_0" + ], + [ + "CMT_PMV_NW4A0", + "CMT_TOP_NW4A0_0" + ], + [ + "CMT_PMV_LOGIC_OUTS15", + "CMT_TOP_LOGIC_OUTS_L_B15_0" + ], + [ + "CMT_PMV_FAN5", + "CMT_TOP_FAN5_0" + ], + [ + "CMT_PMV_LOGIC_OUTS13", + "CMT_TOP_LOGIC_OUTS_L_B13_0" + ], + [ + "CMT_PMV_IMUX3", + "CMT_TOP_IMUX3_0" + ], + [ + "CMT_PMV_NW2A1", + "CMT_TOP_NW2A1_0" + ], + [ + "CMT_PMV_FAN1", + "CMT_TOP_FAN1_0" + ], + [ + "CMT_PMV_WW4B0", + "CMT_TOP_WW4B0_0" + ], + [ + "CMT_PMV_NE4C3", + "CMT_TOP_NE4C3_0" + ], + [ + "CMT_PMV_EE2BEG1", + "CMT_TOP_EE2BEG1_0" + ], + [ + "CMT_PMV_IMUX34", + "CMT_TOP_IMUX34_0" + ], + [ + "CMT_PMV_SW4A3", + "CMT_TOP_SW4A3_0" + ], + [ + "CMT_PMV_IMUX25", + "CMT_TOP_IMUX25_0" + ], + [ + "CMT_PMV_FAN3", + "CMT_TOP_FAN3_0" + ], + [ + "CMT_PMV_EL1BEG0", + "CMT_TOP_EL1BEG0_0" + ], + [ + "CMT_PMV_EE4C2", + "CMT_TOP_EE4C2_0" + ], + [ + "CMT_PMV_WW2A2", + "CMT_TOP_WW2A2_0" + ], + [ + "CMT_PMV_IMUX1", + "CMT_TOP_IMUX1_0" + ], + [ + "CMT_PMV_IMUX36", + "CMT_TOP_IMUX36_0" + ], + [ + "CMT_PMV_EE4BEG1", + "CMT_TOP_EE4BEG1_0" + ], + [ + "CMT_PMV_IMUX21", + "CMT_TOP_IMUX21_0" + ], + [ + "CMT_PMV_WW4A0", + "CMT_TOP_WW4A0_0" + ], + [ + "CMT_PMV_ER1BEG2", + "CMT_TOP_ER1BEG2_0" + ], + [ + "CMT_PMV_BYP1", + "CMT_TOP_BYP1_0" + ], + [ + "CMT_PMV_IMUX6", + "CMT_TOP_IMUX6_0" + ], + [ + "CMT_PMV_IMUX5", + "CMT_TOP_IMUX5_0" + ], + [ + "CMT_PMV_IMUX45", + "CMT_TOP_IMUX45_0" + ], + [ + "CMT_PMV_WW4END1", + "CMT_TOP_WW4END1_0" + ], + [ + "CMT_PMV_NW2A2", + "CMT_TOP_NW2A2_0" + ], + [ + "CMT_PMV_WW4C3", + "CMT_TOP_WW4C3_0" + ], + [ + "CMT_PMV_SW4A2", + "CMT_TOP_SW4A2_0" + ], + [ + "CMT_PMV_WW4B1", + "CMT_TOP_WW4B1_0" + ], + [ + "CMT_PMV_SE4C2", + "CMT_TOP_SE4C2_0" + ], + [ + "CMT_PMV_IMUX32", + "CMT_TOP_IMUX32_0" + ], + [ + "CMT_PMV_IMUX42", + "CMT_TOP_IMUX42_0" + ], + [ + "CMT_PMV_LOGIC_OUTS16", + "CMT_TOP_LOGIC_OUTS_L_B16_0" + ], + [ + "CMT_PMV_EE4A0", + "CMT_TOP_EE4A0_0" + ], + [ + "CMT_PMV_IMUX31", + "CMT_TOP_IMUX31_0" + ], + [ + "CMT_PMV_LH2", + "CMT_TOP_LH2_0" + ], + [ + "CMT_PMV_WL1END0", + "CMT_TOP_WL1END0_0" + ], + [ + "CMT_PMV_EE2A3", + "CMT_TOP_EE2A3_0" + ], + [ + "CMT_PMV_BYP4", + "CMT_TOP_BYP4_0" + ], + [ + "CMT_PMV_SW4END2", + "CMT_TOP_SW4END2_0" + ], + [ + "CMT_PMV_IMUX35", + "CMT_TOP_IMUX35_0" + ], + [ + "CMT_PMV_NW4A2", + "CMT_TOP_NW4A2_0" + ], + [ + "CMT_PMV_NE4C0", + "CMT_TOP_NE4C0_0" + ], + [ + "CMT_PMV_LOGIC_OUTS2", + "CMT_TOP_LOGIC_OUTS_L_B2_0" + ], + [ + "CMT_PMV_SE4C1", + "CMT_TOP_SE4C1_0" + ], + [ + "CMT_PMV_IMUX19", + "CMT_TOP_IMUX19_0" + ], + [ + "CMT_PMV_NW4END0", + "CMT_TOP_NW4END0_0" + ], + [ + "CMT_PMV_NE4BEG1", + "CMT_TOP_NE4BEG1_0" + ], + [ + "CMT_PMV_IMUX0", + "CMT_TOP_IMUX0_0" + ], + [ + "CMT_PMV_IMUX8", + "CMT_TOP_IMUX8_0" + ], + [ + "CMT_PMV_IMUX40", + "CMT_TOP_IMUX40_0" + ], + [ + "CMT_PMV_LOGIC_OUTS5", + "CMT_TOP_LOGIC_OUTS_L_B5_0" + ], + [ + "CMT_PMV_WL1END1", + "CMT_TOP_WL1END1_0" + ], + [ + "CMT_PMV_EE4B3", + "CMT_TOP_EE4B3_0" + ], + [ + "CMT_PMV_LH1", + "CMT_TOP_LH1_0" + ], + [ + "CMT_PMV_CLK1", + "CMT_TOP_CLK1_0" + ], + [ + "CMT_PMV_LH4", + "CMT_TOP_LH4_0" + ], + [ + "CMT_PMV_SE4C0", + "CMT_TOP_SE4C0_0" + ], + [ + "CMT_PMV_IMUX37", + "CMT_TOP_IMUX37_0" + ], + [ + "CMT_PMV_IMUX47", + "CMT_TOP_IMUX47_0" + ], + [ + "L_TERM_INT_PHASER_TO_IO_OCLK", + "CMT_TOP_OCLK_0" + ], + [ + "CMT_PMV_NE2A3", + "CMT_TOP_NE2A3_0" + ], + [ + "CMT_PMV_WR1END1", + "CMT_TOP_WR1END1_0" + ], + [ + "CMT_PMV_SW4A0", + "CMT_TOP_SW4A0_0" + ], + [ + "CMT_PMV_WW4A3", + "CMT_TOP_WW4A3_0" + ], + [ + "CMT_PMV_LH7", + "CMT_TOP_LH7_0" + ], + [ + "CMT_PMV_IMUX44", + "CMT_TOP_IMUX44_0" + ], + [ + "CMT_PMV_NE2A0", + "CMT_TOP_NE2A0_0" + ], + [ + "CMT_PMV_EE4C3", + "CMT_TOP_EE4C3_0" + ], + [ + "CMT_PMV_IMUX30", + "CMT_TOP_IMUX30_0" + ], + [ + "CMT_PMV_IMUX43", + "CMT_TOP_IMUX43_0" + ], + [ + "CMT_PMV_EE4BEG3", + "CMT_TOP_EE4BEG3_0" + ], + [ + "CMT_PMV_CLK0", + "CMT_TOP_CLK0_0" + ], + [ + "CMT_PMV_WR1END0", + "CMT_TOP_WR1END0_0" + ], + [ + "CMT_PMV_SE2A0", + "CMT_TOP_SE2A0_0" + ], + [ + "CMT_PMV_IMUX17", + "CMT_TOP_IMUX17_0" + ], + [ + "CMT_PMV_LOGIC_OUTS18", + "CMT_TOP_LOGIC_OUTS_L_B18_0" + ], + [ + "CMT_PMV_SW2A0", + "CMT_TOP_SW2A0_0" + ], + [ + "CMT_PMV_SE2A3", + "CMT_TOP_SE2A3_0" + ], + [ + "CMT_PMV_WW4B2", + "CMT_TOP_WW4B2_0" + ], + [ + "CMT_PMV_SE4C3", + "CMT_TOP_SE4C3_0" + ], + [ + "CMT_PMV_LOGIC_OUTS17", + "CMT_TOP_LOGIC_OUTS_L_B17_0" + ], + [ + "L_TERM_INT_PHASER_TO_IO_ICLK", + "CMT_TOP_ICLK_0" + ], + [ + "CMT_PMV_IMUX11", + "CMT_TOP_IMUX11_0" + ], + [ + "CMT_PMV_NE4BEG2", + "CMT_TOP_NE4BEG2_0" + ], + [ + "CMT_PMV_EE2A1", + "CMT_TOP_EE2A1_0" + ], + [ + "CMT_PMV_LOGIC_OUTS22", + "CMT_TOP_LOGIC_OUTS_L_B22_0" + ], + [ + "CMT_PMV_IMUX39", + "CMT_TOP_IMUX39_0" + ], + [ + "CMT_PMV_EL1BEG2", + "CMT_TOP_EL1BEG2_0" + ], + [ + "CMT_PMV_EE4BEG2", + "CMT_TOP_EE4BEG2_0" + ], + [ + "CMT_PMV_WW4B3", + "CMT_TOP_WW4B3_0" + ], + [ + "CMT_PMV_EE2A0", + "CMT_TOP_EE2A0_0" + ], + [ + "CMT_PMV_FAN0", + "CMT_TOP_FAN0_0" + ], + [ + "CMT_PMV_LH6", + "CMT_TOP_LH6_0" + ], + [ + "CMT_PMV_SW4END1", + "CMT_TOP_SW4END1_0" + ], + [ + "CMT_PMV_SE4BEG1", + "CMT_TOP_SE4BEG1_0" + ], + [ + "CMT_PMV_BYP0", + "CMT_TOP_BYP0_0" + ], + [ + "CMT_PMV_NE4C1", + "CMT_TOP_NE4C1_0" + ], + [ + "CMT_PMV_SE4BEG3", + "CMT_TOP_SE4BEG3_0" + ], + [ + "CMT_PMV_EE4A3", + "CMT_TOP_EE4A3_0" + ], + [ + "CMT_PMV_EE4BEG0", + "CMT_TOP_EE4BEG0_0" + ], + [ + "CMT_PMV_IMUX41", + "CMT_TOP_IMUX41_0" + ], + [ + "CMT_PMV_WW4A2", + "CMT_TOP_WW4A2_0" + ], + [ + "CMT_PMV_IMUX10", + "CMT_TOP_IMUX10_0" + ], + [ + "CMT_PMV_IMUX38", + "CMT_TOP_IMUX38_0" + ], + [ + "CMT_PMV_BYP5", + "CMT_TOP_BYP5_0" + ], + [ + "CMT_PMV_NW2A3", + "CMT_TOP_NW2A3_0" + ], + [ + "CMT_PMV_LOGIC_OUTS19", + "CMT_TOP_LOGIC_OUTS_L_B19_0" + ], + [ + "CMT_PMV_EE4A2", + "CMT_TOP_EE4A2_0" + ], + [ + "CMT_PMV_ER1BEG3", + "CMT_TOP_ER1BEG3_0" + ], + [ + "CMT_PMV_IMUX16", + "CMT_TOP_IMUX16_0" + ], + [ + "CMT_PMV_LOGIC_OUTS23", + "CMT_TOP_LOGIC_OUTS_L_B23_0" + ], + [ + "CMT_PMV_NW2A0", + "CMT_TOP_NW2A0_0" + ], + [ + "CMT_PMV_SW2A3", + "CMT_TOP_SW2A3_0" + ], + [ + "CMT_PMV_CTRL1", + "CMT_TOP_CTRL1_0" + ], + [ + "CMT_PMV_SE2A1", + "CMT_TOP_SE2A1_0" + ], + [ + "CMT_PMV_IMUX20", + "CMT_TOP_IMUX20_0" + ], + [ + "CMT_PMV_EE4B1", + "CMT_TOP_EE4B1_0" + ], + [ + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "CMT_TOP_OCLKDIV_0" + ], + [ + "CMT_PMV_WW2END1", + "CMT_TOP_WW2END1_0" + ], + [ + "CMT_PMV_ER1BEG0", + "CMT_TOP_ER1BEG0_0" + ], + [ + "CMT_PMV_NE2A2", + "CMT_TOP_NE2A2_0" + ], + [ + "CMT_PMV_WW2END3", + "CMT_TOP_WW2END3_0" + ], + [ + "CMT_PMV_SW2A2", + "CMT_TOP_SW2A2_0" + ], + [ + "CMT_PMV_LOGIC_OUTS7", + "CMT_TOP_LOGIC_OUTS_L_B7_0" + ], + [ + "CMT_PMV_IMUX29", + "CMT_TOP_IMUX29_0" + ], + [ + "CMT_PMV_IMUX27", + "CMT_TOP_IMUX27_0" + ], + [ + "CMT_PMV_WL1END3", + "CMT_TOP_WL1END3_0" + ], + [ + "CMT_PMV_IMUX2", + "CMT_TOP_IMUX2_0" + ], + [ + "CMT_PMV_SW4END3", + "CMT_TOP_SW4END3_0" + ], + [ + "CMT_PMV_BYP6", + "CMT_TOP_BYP6_0" + ], + [ + "CMT_PMV_IMUX23", + "CMT_TOP_IMUX23_0" + ], + [ + "CMT_PMV_NW4END2", + "CMT_TOP_NW4END2_0" + ], + [ + "CMT_PMV_WW4END3", + "CMT_TOP_WW4END3_0" + ], + [ + "CMT_PMV_FAN4", + "CMT_TOP_FAN4_0" + ], + [ + "CMT_PMV_NE4BEG0", + "CMT_TOP_NE4BEG0_0" + ], + [ + "CMT_PMV_LH8", + "CMT_TOP_LH8_0" + ], + [ + "CMT_PMV_LOGIC_OUTS0", + "CMT_TOP_LOGIC_OUTS_L_B0_0" + ], + [ + "CMT_PMV_WR1END3", + "CMT_TOP_WR1END3_0" + ], + [ + "CMT_PMV_LH10", + "CMT_TOP_LH10_0" + ], + [ + "CMT_PMV_EE4A1", + "CMT_TOP_EE4A1_0" + ], + [ + "CMT_PMV_IMUX18", + "CMT_TOP_IMUX18_0" + ], + [ + "CMT_PMV_LH5", + "CMT_TOP_LH5_0" + ], + [ + "CMT_PMV_FAN6", + "CMT_TOP_FAN6_0" + ], + [ + "CMT_PMV_SE4BEG0", + "CMT_TOP_SE4BEG0_0" + ], + [ + "CMT_PMV_WW4END2", + "CMT_TOP_WW4END2_0" + ], + [ + "CMT_PMV_NE2A1", + "CMT_TOP_NE2A1_0" + ], + [ + "CMT_PMV_IMUX33", + "CMT_TOP_IMUX33_0" + ], + [ + "CMT_PMV_WW4C2", + "CMT_TOP_WW4C2_0" + ], + [ + "CMT_PMV_WW2A0", + "CMT_TOP_WW2A0_0" + ], + [ + "CMT_PMV_CTRL0", + "CMT_TOP_CTRL0_0" + ], + [ + "CMT_PMV_WW2END0", + "CMT_TOP_WW2END0_0" + ], + [ + "CMT_PMV_EE2A2", + "CMT_TOP_EE2A2_0" + ], + [ + "CMT_PMV_EL1BEG1", + "CMT_TOP_EL1BEG1_0" + ], + [ + "CMT_PMV_EE2BEG2", + "CMT_TOP_EE2BEG2_0" + ], + [ + "CMT_PMV_EE2BEG3", + "CMT_TOP_EE2BEG3_0" + ], + [ + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "CMT_TOP_ICLKDIV_0" + ], + [ + "CMT_PMV_BYP7", + "CMT_TOP_BYP7_0" + ], + [ + "CMT_PMV_WW4END0", + "CMT_TOP_WW4END0_0" + ], + [ + "CMT_PMV_EE4C1", + "CMT_TOP_EE4C1_0" + ], + [ + "CMT_PMV_IMUX12", + "CMT_TOP_IMUX12_0" + ], + [ + "CMT_PMV_WW2END2", + "CMT_TOP_WW2END2_0" + ], + [ + "CMT_PMV_NW4END1", + "CMT_TOP_NW4END1_0" + ], + [ + "CMT_PMV_IMUX26", + "CMT_TOP_IMUX26_0" + ], + [ + "CMT_PMV_SW4A1", + "CMT_TOP_SW4A1_0" + ], + [ + "CMT_PMV_IMUX14", + "CMT_TOP_IMUX14_0" + ], + [ + "CMT_PMV_LH9", + "CMT_TOP_LH9_0" + ], + [ + "CMT_PMV_NW4A1", + "CMT_TOP_NW4A1_0" + ], + [ + "CMT_PMV_IMUX22", + "CMT_TOP_IMUX22_0" + ], + [ + "CMT_PMV_LOGIC_OUTS8", + "CMT_TOP_LOGIC_OUTS_L_B8_0" + ], + [ + "CMT_PMV_IMUX24", + "CMT_TOP_IMUX24_0" + ], + [ + "CMT_PMV_SE2A2", + "CMT_TOP_SE2A2_0" + ], + [ + "CMT_PMV_NW4END3", + "CMT_TOP_NW4END3_0" + ], + [ + "CMT_PMV_NW4A3", + "CMT_TOP_NW4A3_0" + ], + [ + "CMT_PMV_NE4BEG3", + "CMT_TOP_NE4BEG3_0" + ], + [ + "CMT_PMV_SE4BEG2", + "CMT_TOP_SE4BEG2_0" + ], + [ + "CMT_PMV_LH11", + "CMT_TOP_LH11_0" + ], + [ + "CMT_PMV_LH12", + "CMT_TOP_LH12_0" + ], + [ + "CMT_PMV_WR1END2", + "CMT_TOP_WR1END2_0" + ], + [ + "CMT_PMV_BYP3", + "CMT_TOP_BYP3_0" + ], + [ + "CMT_PMV_FAN7", + "CMT_TOP_FAN7_0" + ], + [ + "CMT_PMV_IMUX15", + "CMT_TOP_IMUX15_0" + ], + [ + "CMT_PMV_IMUX13", + "CMT_TOP_IMUX13_0" + ], + [ + "CMT_PMV_LOGIC_OUTS20", + "CMT_TOP_LOGIC_OUTS_L_B20_0" + ], + [ + "CMT_PMV_NE4C2", + "CMT_TOP_NE4C2_0" + ], + [ + "CMT_PMV_WW4C1", + "CMT_TOP_WW4C1_0" + ], + [ + "CMT_PMV_LOGIC_OUTS21", + "CMT_TOP_LOGIC_OUTS_L_B21_0" + ], + [ + "CMT_PMV_EE4C0", + "CMT_TOP_EE4C0_0" + ], + [ + "CMT_PMV_WW2A1", + "CMT_TOP_WW2A1_0" + ], + [ + "CMT_PMV_SW4END0", + "CMT_TOP_SW4END0_0" + ], + [ + "CMT_PMV_IMUX28", + "CMT_TOP_IMUX28_0" + ], + [ + "CMT_PMV_WW4A1", + "CMT_TOP_WW4A1_0" + ], + [ + "CMT_PMV_WW4C0", + "CMT_TOP_WW4C0_0" + ], + [ + "CMT_PMV_WL1END2", + "CMT_TOP_WL1END2_0" + ], + [ + "CMT_PMV_EL1BEG3", + "CMT_TOP_EL1BEG3_0" + ], + [ + "CMT_PMV_LH3", + "CMT_TOP_LH3_0" + ], + [ + "CMT_PMV_IMUX9", + "CMT_TOP_IMUX9_0" + ], + [ + "CMT_PMV_WW2A3", + "CMT_TOP_WW2A3_0" + ] + ], + "tile_types": [ + "CMT_PMV", + "CMT_TOP_R_LOWER_B" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLK_HROW_CK_BUFHCLK_R1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "CLK_HROW_CK_IN_R5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "CLK_HROW_CK_BUFHCLK_R5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "CLK_HROW_CK_BUFHCLK_R10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "CLK_HROW_CK_IN_R10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "CLK_HROW_CK_IN_R1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "CLK_HROW_CK_BUFHCLK_R4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "CLK_HROW_CK_IN_R13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "CLK_HROW_CK_BUFRCLK_R3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "CLK_HROW_CK_IN_R0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "CLK_HROW_CK_BUFRCLK_R2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "CLK_HROW_CK_IN_R2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "CLK_HROW_CK_BUFHCLK_R8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "CLK_HROW_CK_IN_R8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "CLK_HROW_CK_IN_R7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "CLK_HROW_CK_IN_R12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "CLK_HROW_CK_BUFHCLK_R0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "CLK_HROW_CK_BUFHCLK_R7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "CLK_HROW_CK_BUFRCLK_R1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "CLK_HROW_CK_BUFHCLK_R9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "CLK_HROW_CK_IN_R11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "CLK_HROW_CK_IN_R9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "CLK_HROW_CK_BUFHCLK_R6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "CLK_HROW_CK_BUFHCLK_R3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "CLK_HROW_CK_BUFHCLK_R11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "CLK_HROW_CK_BUFRCLK_R0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "CLK_HROW_CK_IN_R4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "CLK_HROW_CK_IN_R3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "CLK_HROW_CK_BUFHCLK_R2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "CLK_HROW_CK_IN_R6", + "HCLK_VBRK_MUX_CLK6" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "HCLK_VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "CLK_HROW_IMUX32_6", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_NW2A2_6", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_BYP3_6", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_EE2A0_6", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_EE2BEG3_6", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_SE4C1_6", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_LH10_6", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_ER1BEG0_6", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_WW2A0_6", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4C1_6", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_SW4A0_6", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_EE4BEG3_6", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_IMUX0_6", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_CTRL0_6", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_NE4C0_6", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_MONITOR_N_6", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_HROW_WW4C2_6", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_NW4END0_6", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_LH3_6", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_SW2A2_6", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_IMUX24_6", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_FAN0_6", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_SW4END2_6", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_EE2A1_6", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_EE4C3_6", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_SW4A2_6", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_WW4B3_6", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_WW2END3_6", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_IMUX30_6", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_IMUX9_6", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_IMUX31_6", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_WW4B1_6", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_NE2A2_6", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_LH7_6", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_WW4END3_6", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_FAN7_6", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_IMUX20_6", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_IMUX38_6", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_WW4B0_6", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_SW4A3_6", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_WR1END1_6", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_EE4A1_6", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_FAN6_6", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_EE2BEG2_6", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_EE4B2_6", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_NE4BEG3_6", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_IMUX10_6", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_NW4A3_6", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_FAN2_6", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_WL1END0_6", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_FAN3_6", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_EL1BEG2_6", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_IMUX25_6", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_SW2A0_6", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_IMUX13_6", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_NW4END2_6", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_SW4A1_6", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_LH11_6", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_WL1END3_6", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_EE4A0_6", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_BYP6_6", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_IMUX15_6", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_WW2A2_6", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_WW2A3_6", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_WW2END2_6", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_SE4BEG3_6", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_IMUX19_6", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_LH12_6", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_SE4BEG0_6", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_IMUX21_6", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_NW2A0_6", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_LH4_6", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_IMUX14_6", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_IMUX23_6", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_NE4C2_6", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_EE4B1_6", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_FAN1_6", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_EE4C0_6", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_EE4A3_6", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_IMUX29_6", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_IMUX17_6", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_IMUX43_6", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_SE2A2_6", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_WL1END1_6", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_WW4C0_6", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_LH5_6", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_IMUX2_6", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_NE4BEG0_6", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_IMUX8_6", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_ER1BEG1_6", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_EE4C2_6", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_SW4END0_6", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_WW4END1_6", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_LH2_6", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_IMUX35_6", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_SE4BEG1_6", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_EE4BEG0_6", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_IMUX40_6", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_IMUX47_6", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_EL1BEG1_6", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_WR1END2_6", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_IMUX34_6", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_IMUX44_6", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_BYP5_6", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_WW4C3_6", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_NW4A2_6", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_IMUX3_6", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_NE4BEG1_6", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_IMUX12_6", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_WW4C1_6", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_NE4BEG2_6", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_NW4A1_6", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_NE4C1_6", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_ER1BEG2_6", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_WW4A3_6", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_IMUX1_6", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_IMUX41_6", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_NW2A1_6", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_IMUX37_6", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_LH6_6", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_NE4C3_6", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_IMUX28_6", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_SW4END3_6", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_IMUX5_6", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_IMUX16_6", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_EL1BEG0_6", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_SW4END1_6", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_BYP2_6", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_NW4END3_6", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_LH1_6", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_IMUX45_6", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_EE2A2_6", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_EE4B3_6", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_LH8_6", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_IMUX42_6", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_FAN4_6", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_WW4A0_6", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_WW2A1_6", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_WR1END0_6", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_WR1END3_6", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_SE2A3_6", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_SE2A0_6", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_BYP4_6", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_NW4A0_6", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_EE2BEG0_6", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_SE4C2_6", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_EE4B0_6", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_WL1END2_6", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_SE4BEG2_6", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_EE2A3_6", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_IMUX27_6", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_WW4A2_6", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_WW4END2_6", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_LH9_6", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_SE4C3_6", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_ER1BEG3_6", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_WW4B2_6", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_BYP0_6", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_IMUX26_6", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_EE4BEG2_6", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_NE2A0_6", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_CLK1_6", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_WW2END0_6", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_IMUX33_6", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_IMUX7_6", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_SW2A3_6", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_IMUX4_6", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_EE2BEG1_6", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_WW2END1_6", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_SE4C0_6", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_NE2A3_6", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_EE4A2_6", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_SW2A1_6", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_IMUX6_6", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_IMUX11_6", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_CLK0_6", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_CTRL1_6", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_IMUX36_6", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_MONITOR_P_6", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_HROW_NE2A1_6", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_EE4BEG1_6", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_NW4END1_6", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_IMUX46_6", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_SE2A1_6", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_WW4END0_6", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_NW2A3_6", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_IMUX39_6", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_IMUX22_6", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_BYP1_6", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_BYP7_6", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_IMUX18_6", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_EL1BEG3_6", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_WW4A1_6", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_FAN5_6", + "INT_INTERFACE_FAN5" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CMT_TOP_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH1_2", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH2_2", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_LH6_2", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH7_2", + "VBRK_LH7" + ], + [ + "CMT_TOP_LH12_2", + "VBRK_LH12" + ], + [ + "CMT_TOP_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_LH11_2", + "VBRK_LH11" + ], + [ + "CMT_TOP_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4B3_2", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_LH4_2", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_LH5_2", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH3_2", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH10_2", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH8_2", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_LH9_2", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW2A2_2", + "VBRK_NW2A2" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4A3_10", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SE2A3_10", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG0_10", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END2_10", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW4C0_10", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_LH8_10", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4B2_10", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A1_10", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW4C2_10", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WL1END3_10", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WL1END0_10", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW2A0_10", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2END0_10", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE4C3_10", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE2BEG1_10", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_LH7_10", + "VBRK_LH7" + ], + [ + "CMT_TOP_EL1BEG1_10", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE4C2_10", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH10_10", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4B1_10", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4C0_10", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH12_10", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_10", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4BEG3_10", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW2END2_10", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW4A2_10", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG3_10", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE4A1_10", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_SW2A0_10", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE2BEG0_10", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE2A0_10", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH5_10", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW2A3_10", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW2A1_10", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WR1END2_10", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SW4END1_10", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW2A3_10", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SW4END2_10", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_LH3_10", + "VBRK_LH3" + ], + [ + "CMT_TOP_EL1BEG0_10", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4END0_10", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A1_10", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SE4BEG2_10", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4C2_10", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WR1END3_10", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WR1END1_10", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NW4A0_10", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_10", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW4B1_10", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C2_10", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE4BEG3_10", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4BEG1_10", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EE4C1_10", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG2_10", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG3_10", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE4BEG3_10", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE2A1_10", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_LH11_10", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE4A3_10", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SE4C1_10", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WL1END1_10", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW4B0_10", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2A2_10", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4BEG1_10", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW4A0_10", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END1_10", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_ER1BEG3_10", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WW4END2_10", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_ER1BEG0_10", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_10", + "VBRK_LH1" + ], + [ + "CMT_TOP_WW4C3_10", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END0_10", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW4END3_10", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_LH9_10", + "VBRK_LH9" + ], + [ + "CMT_TOP_NW2A2_10", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_10", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_LH6_10", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A0_10", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE2A2_10", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2BEG2_10", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW2END1_10", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4B0_10", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C1_10", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SW2A2_10", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG2_10", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_NE2A0_10", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE2A1_10", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_10", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW2A0_10", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4A2_10", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW4A1_10", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WR1END0_10", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4B2_10", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END0_10", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4C0_10", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_10", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4B3_10", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4A0_10", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END3_10", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WL1END2_10", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4A2_10", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4B3_10", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NE4C1_10", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A1_10", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2A2_10", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EE4C3_10", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_MONITOR_N_10", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW4A2_10", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NE4BEG2_10", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_SW2A1_10", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4BEG0_10", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SE2A0_10", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4BEG1_10", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_10", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_10", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4END3_10", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE2A2_10", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SE4C3_10", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4A3_10", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_LH2_10", + "VBRK_LH2" + ], + [ + "CMT_TOP_ER1BEG2_10", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NE2A3_10", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2A3_10", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C0_10", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_ER1BEG1_10", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_MONITOR_P_10", + "VBRK_MONITOR_P" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "CMT_FIFO_SE2A3_9", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_SW2A2_9", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_L_FAN4_9", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_LH7_9", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_ER1BEG0_9", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_9", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "CMT_FIFO_EE2BEG0_9", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_FAN5_9", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_WR1END1_9", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_LH6_9", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_SW2A1_9", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_EE2A2_9", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_EE4A2_9", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_IMUX13_9", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_WW4END3_9", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_L_BYP5_9", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_NW4A0_9", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_L_IMUX15_9", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_IMUX22_9", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_LH12_9", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_SW4END3_9", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_L_IMUX21_9", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_NE4BEG3_9", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_NE2A3_9", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_9", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "CMT_FIFO_WW2A0_9", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_L_IMUX16_9", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_LH11_9", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_L_FAN1_9", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_L_FAN7_9", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_SW4A2_9", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_L_IMUX37_9", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_EE2BEG1_9", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_SE2A0_9", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_L_IMUX41_9", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_SW4A3_9", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_ER1BEG3_9", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_SW4END2_9", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_L_CTRL0_9", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_WW4A3_9", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_EE4C0_9", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_LH10_9", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_EE4C1_9", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_SW2A0_9", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_L_FAN6_9", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_NE4C2_9", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_NW4END3_9", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_WW2END2_9", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_EE4BEG1_9", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX32_9", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_9", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_9", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "CMT_FIFO_L_IMUX28_9", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_9", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "CMT_FIFO_L_BYP6_9", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_9", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "CMT_FIFO_L_IMUX1_9", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_SE2A1_9", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_SE4C1_9", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_WW4END2_9", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_EE4A0_9", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_EE4C2_9", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_LH2_9", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_L_IMUX2_9", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_SE4BEG2_9", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_EE2A0_9", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_IMUX9_9", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX5_9", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_WW4END0_9", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_IMUX12_9", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_L_IMUX33_9", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_9", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "CMT_FIFO_SE4BEG1_9", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX25_9", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_EE4C3_9", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_ER1BEG2_9", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_IMUX10_9", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_L_IMUX36_9", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_SE4C0_9", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_L_IMUX42_9", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_FAN0_9", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_NW4END2_9", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_IMUX39_9", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_NE4C3_9", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_9", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "CMT_FIFO_L_IMUX34_9", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_L_IMUX27_9", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_L_BYP3_9", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_EE4A3_9", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_IMUX23_9", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_L_IMUX14_9", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_WW4END1_9", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_NE4C0_9", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_SW2A3_9", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_EL1BEG0_9", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_L_IMUX20_9", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_NE4BEG1_9", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX30_9", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_L_IMUX43_9", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_NW4A2_9", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_L_CLK0_9", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_LH8_9", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_EL1BEG3_9", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_WW4B2_9", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_L_IMUX11_9", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_L_CTRL1_9", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_NE4C1_9", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_NW2A2_9", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_EE2A3_9", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_WL1END3_9", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_WW4A0_9", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_EE4A1_9", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_NE4BEG0_9", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_WR1END3_9", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_SW4END0_9", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_WW4B0_9", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_WW4A1_9", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_9", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "CMT_FIFO_L_IMUX6_9", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_L_IMUX47_9", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_EE4BEG2_9", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_WW4C2_9", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_IMUX8_9", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_9", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "CMT_FIFO_L_IMUX46_9", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_WR1END2_9", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_EE4B3_9", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_L_IMUX7_9", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_L_CLK1_9", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_9", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "CMT_FIFO_L_IMUX35_9", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_EE2BEG3_9", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_L_BYP1_9", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_L_IMUX38_9", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_9", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_EE4B1_9", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_9", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "CMT_FIFO_WW2END1_9", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_L_IMUX44_9", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_NW4END1_9", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_WW2END3_9", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_SE4C3_9", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_IMUX40_9", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_WL1END0_9", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_LH9_9", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_WW4B1_9", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_LH4_9", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_WW2END0_9", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_NE2A2_9", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_WW4B3_9", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_L_IMUX24_9", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_NW4A1_9", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_9", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "CMT_FIFO_L_BYP2_9", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_9", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "CMT_FIFO_LH1_9", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_9", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "CMT_FIFO_WW4C1_9", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_L_IMUX4_9", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_NW4END0_9", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_L_IMUX31_9", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_NW2A0_9", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_9", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "CMT_FIFO_EE4BEG0_9", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_9", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "CMT_FIFO_SW4END1_9", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_LH5_9", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_L_IMUX18_9", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_L_BYP7_9", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_EL1BEG2_9", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_EE2BEG2_9", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_L_IMUX3_9", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_NE4BEG2_9", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_WW2A1_9", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_WW2A2_9", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_NW2A3_9", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_SE4C2_9", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_SE4BEG0_9", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_L_BYP4_9", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_L_IMUX19_9", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_WR1END0_9", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_NW2A1_9", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_L_IMUX29_9", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_WW4C0_9", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_EE2A1_9", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_L_BYP0_9", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_WL1END2_9", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_L_IMUX17_9", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_NW4A3_9", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_9", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "CMT_FIFO_WW4A2_9", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_LH3_9", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_L_IMUX0_9", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_ER1BEG1_9", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_FAN3_9", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_L_FAN2_9", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_9", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "CMT_FIFO_SE2A2_9", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_NE2A0_9", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_IMUX26_9", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_SW4A0_9", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_NE2A1_9", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_EE4BEG3_9", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_9", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "CMT_FIFO_WW2A3_9", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_SE4BEG3_9", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_SW4A1_9", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_EE4B0_9", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_WL1END1_9", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_9", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_9", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "CMT_FIFO_EL1BEG1_9", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_9", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "CMT_FIFO_L_IMUX45_9", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_WW4C3_9", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_EE4B2_9", + "INT_INTERFACE_EE4B2" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + -7 + ], + "wire_pairs": [ + [ + "MONITOR_NW4A0_7", + "VFRAME_NW4A0" + ], + [ + "MONITOR_IMUX25_7", + "VFRAME_IMUX25" + ], + [ + "MONITOR_EE4A2_7", + "VFRAME_EE4A2" + ], + [ + "MONITOR_FAN6_7", + "VFRAME_FAN6" + ], + [ + "MONITOR_SE4BEG1_7", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_LH1_7", + "VFRAME_LH1" + ], + [ + "MONITOR_IMUX20_7", + "VFRAME_IMUX20" + ], + [ + "MONITOR_WW2A3_7", + "VFRAME_WW2A3" + ], + [ + "MONITOR_BYP1_7", + "VFRAME_BYP1" + ], + [ + "MONITOR_WW4B1_7", + "VFRAME_WW4B1" + ], + [ + "MONITOR_NE2A3_7", + "VFRAME_NE2A3" + ], + [ + "MONITOR_NW2A2_7", + "VFRAME_NW2A2" + ], + [ + "MONITOR_EE2BEG1_7", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_EE4BEG3_7", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_IMUX43_7", + "VFRAME_IMUX43" + ], + [ + "MONITOR_LH5_7", + "VFRAME_LH5" + ], + [ + "MONITOR_IMUX24_7", + "VFRAME_IMUX24" + ], + [ + "MONITOR_SE4C0_7", + "VFRAME_SE4C0" + ], + [ + "MONITOR_ER1BEG1_7", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_EE4B0_7", + "VFRAME_EE4B0" + ], + [ + "MONITOR_IMUX35_7", + "VFRAME_IMUX35" + ], + [ + "MONITOR_CTRL1_7", + "VFRAME_CTRL1" + ], + [ + "MONITOR_SE4BEG0_7", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_IMUX22_7", + "VFRAME_IMUX22" + ], + [ + "MONITOR_NW2A0_7", + "VFRAME_NW2A0" + ], + [ + "MONITOR_EE4B2_7", + "VFRAME_EE4B2" + ], + [ + "MONITOR_EL1BEG1_7", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_SE4BEG2_7", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_IMUX42_7", + "VFRAME_IMUX42" + ], + [ + "MONITOR_WL1END2_7", + "VFRAME_WL1END2" + ], + [ + "MONITOR_EE4B3_7", + "VFRAME_EE4B3" + ], + [ + "MONITOR_SW2A3_7", + "VFRAME_SW2A3" + ], + [ + "MONITOR_LH10_7", + "VFRAME_LH10" + ], + [ + "MONITOR_LH12_7", + "VFRAME_LH12" + ], + [ + "MONITOR_CTRL0_7", + "VFRAME_CTRL0" + ], + [ + "MONITOR_IMUX7_7", + "VFRAME_IMUX7" + ], + [ + "MONITOR_EE2BEG0_7", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_NE2A2_7", + "VFRAME_NE2A2" + ], + [ + "MONITOR_BYP5_7", + "VFRAME_BYP5" + ], + [ + "MONITOR_EE2A1_7", + "VFRAME_EE2A1" + ], + [ + "MONITOR_NE4C1_7", + "VFRAME_NE4C1" + ], + [ + "MONITOR_WW4B3_7", + "VFRAME_WW4B3" + ], + [ + "MONITOR_IMUX14_7", + "VFRAME_IMUX14" + ], + [ + "MONITOR_IMUX36_7", + "VFRAME_IMUX36" + ], + [ + "MONITOR_EE4C0_7", + "VFRAME_EE4C0" + ], + [ + "MONITOR_SE2A0_7", + "VFRAME_SE2A0" + ], + [ + "MONITOR_IMUX32_7", + "VFRAME_IMUX32" + ], + [ + "MONITOR_SE2A1_7", + "VFRAME_SE2A1" + ], + [ + "MONITOR_NE4BEG0_7", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_BYP6_7", + "VFRAME_BYP6" + ], + [ + "MONITOR_IMUX15_7", + "VFRAME_IMUX15" + ], + [ + "MONITOR_EE4BEG2_7", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_IMUX18_7", + "VFRAME_IMUX18" + ], + [ + "MONITOR_NE2A1_7", + "VFRAME_NE2A1" + ], + [ + "MONITOR_NW4A1_7", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WR1END0_7", + "VFRAME_WR1END0" + ], + [ + "MONITOR_WW4A3_7", + "VFRAME_WW4A3" + ], + [ + "MONITOR_WW4END3_7", + "VFRAME_WW4END3" + ], + [ + "MONITOR_NW4END0_7", + "VFRAME_NW4END0" + ], + [ + "MONITOR_IMUX23_7", + "VFRAME_IMUX23" + ], + [ + "MONITOR_SW4END3_7", + "VFRAME_SW4END3" + ], + [ + "MONITOR_NW4A2_7", + "VFRAME_NW4A2" + ], + [ + "MONITOR_IMUX26_7", + "VFRAME_IMUX26" + ], + [ + "MONITOR_IMUX46_7", + "VFRAME_IMUX46" + ], + [ + "MONITOR_WW2END3_7", + "VFRAME_WW2END3" + ], + [ + "MONITOR_NW4END1_7", + "VFRAME_NW4END1" + ], + [ + "MONITOR_IMUX30_7", + "VFRAME_IMUX30" + ], + [ + "MONITOR_SW4END0_7", + "VFRAME_SW4END0" + ], + [ + "MONITOR_WW4B2_7", + "VFRAME_WW4B2" + ], + [ + "MONITOR_WW4A1_7", + "VFRAME_WW4A1" + ], + [ + "MONITOR_EE2A3_7", + "VFRAME_EE2A3" + ], + [ + "MONITOR_EE4BEG1_7", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_NE4BEG3_7", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_NE4BEG2_7", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_SE2A2_7", + "VFRAME_SE2A2" + ], + [ + "MONITOR_WL1END0_7", + "VFRAME_WL1END0" + ], + [ + "MONITOR_IMUX12_7", + "VFRAME_IMUX12" + ], + [ + "MONITOR_IMUX16_7", + "VFRAME_IMUX16" + ], + [ + "MONITOR_IMUX37_7", + "VFRAME_IMUX37" + ], + [ + "MONITOR_WW4A0_7", + "VFRAME_WW4A0" + ], + [ + "MONITOR_SW4A0_7", + "VFRAME_SW4A0" + ], + [ + "MONITOR_EE4B1_7", + "VFRAME_EE4B1" + ], + [ + "MONITOR_CLK1_7", + "VFRAME_CLK1" + ], + [ + "MONITOR_WW4C1_7", + "VFRAME_WW4C1" + ], + [ + "MONITOR_IMUX27_7", + "VFRAME_IMUX27" + ], + [ + "MONITOR_NE4C3_7", + "VFRAME_NE4C3" + ], + [ + "MONITOR_BYP2_7", + "VFRAME_BYP2" + ], + [ + "MONITOR_WW4C2_7", + "VFRAME_WW4C2" + ], + [ + "MONITOR_IMUX29_7", + "VFRAME_IMUX29" + ], + [ + "MONITOR_EE4C3_7", + "VFRAME_EE4C3" + ], + [ + "MONITOR_FAN2_7", + "VFRAME_FAN2" + ], + [ + "MONITOR_EE4A1_7", + "VFRAME_EE4A1" + ], + [ + "MONITOR_SW2A0_7", + "VFRAME_SW2A0" + ], + [ + "MONITOR_FAN5_7", + "VFRAME_FAN5" + ], + [ + "MONITOR_FAN7_7", + "VFRAME_FAN7" + ], + [ + "MONITOR_ER1BEG3_7", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_CLK0_7", + "VFRAME_CLK0" + ], + [ + "MONITOR_BYP0_7", + "VFRAME_BYP0" + ], + [ + "MONITOR_WR1END3_7", + "VFRAME_WR1END3" + ], + [ + "MONITOR_SE4C3_7", + "VFRAME_SE4C3" + ], + [ + "MONITOR_IMUX11_7", + "VFRAME_IMUX11" + ], + [ + "MONITOR_LH6_7", + "VFRAME_LH6" + ], + [ + "MONITOR_IMUX38_7", + "VFRAME_IMUX38" + ], + [ + "MONITOR_IMUX17_7", + "VFRAME_IMUX17" + ], + [ + "MONITOR_EL1BEG2_7", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_IMUX28_7", + "VFRAME_IMUX28" + ], + [ + "MONITOR_WW4END0_7", + "VFRAME_WW4END0" + ], + [ + "MONITOR_NW4END2_7", + "VFRAME_NW4END2" + ], + [ + "MONITOR_IMUX31_7", + "VFRAME_IMUX31" + ], + [ + "MONITOR_IMUX39_7", + "VFRAME_IMUX39" + ], + [ + "MONITOR_NE4C2_7", + "VFRAME_NE4C2" + ], + [ + "MONITOR_EL1BEG3_7", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_FAN3_7", + "VFRAME_FAN3" + ], + [ + "MONITOR_SW4A2_7", + "VFRAME_SW4A2" + ], + [ + "MONITOR_IMUX8_7", + "VFRAME_IMUX8" + ], + [ + "MONITOR_FAN4_7", + "VFRAME_FAN4" + ], + [ + "MONITOR_IMUX1_7", + "VFRAME_IMUX1" + ], + [ + "MONITOR_WW4C3_7", + "VFRAME_WW4C3" + ], + [ + "MONITOR_SE4C1_7", + "VFRAME_SE4C1" + ], + [ + "MONITOR_EE2A0_7", + "VFRAME_EE2A0" + ], + [ + "MONITOR_WW2A0_7", + "VFRAME_WW2A0" + ], + [ + "MONITOR_WW2END1_7", + "VFRAME_WW2END1" + ], + [ + "MONITOR_WW4C0_7", + "VFRAME_WW4C0" + ], + [ + "MONITOR_IMUX6_7", + "VFRAME_IMUX6" + ], + [ + "MONITOR_LH4_7", + "VFRAME_LH4" + ], + [ + "MONITOR_IMUX0_7", + "VFRAME_IMUX0" + ], + [ + "MONITOR_LH11_7", + "VFRAME_LH11" + ], + [ + "MONITOR_BYP3_7", + "VFRAME_BYP3" + ], + [ + "MONITOR_IMUX10_7", + "VFRAME_IMUX10" + ], + [ + "MONITOR_IMUX19_7", + "VFRAME_IMUX19" + ], + [ + "MONITOR_IMUX3_7", + "VFRAME_IMUX3" + ], + [ + "MONITOR_WW2A1_7", + "VFRAME_WW2A1" + ], + [ + "MONITOR_SW4END2_7", + "VFRAME_SW4END2" + ], + [ + "MONITOR_EE4BEG0_7", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_SW4END1_7", + "VFRAME_SW4END1" + ], + [ + "MONITOR_SW4A1_7", + "VFRAME_SW4A1" + ], + [ + "MONITOR_WW4END2_7", + "VFRAME_WW4END2" + ], + [ + "MONITOR_NE4C0_7", + "VFRAME_NE4C0" + ], + [ + "MONITOR_LH8_7", + "VFRAME_LH8" + ], + [ + "MONITOR_WR1END2_7", + "VFRAME_WR1END2" + ], + [ + "MONITOR_SW2A1_7", + "VFRAME_SW2A1" + ], + [ + "MONITOR_EE2BEG3_7", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_IMUX34_7", + "VFRAME_IMUX34" + ], + [ + "MONITOR_IMUX5_7", + "VFRAME_IMUX5" + ], + [ + "MONITOR_LH7_7", + "VFRAME_LH7" + ], + [ + "MONITOR_IMUX2_7", + "VFRAME_IMUX2" + ], + [ + "MONITOR_NE4BEG1_7", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_BYP7_7", + "VFRAME_BYP7" + ], + [ + "MONITOR_WW4END1_7", + "VFRAME_WW4END1" + ], + [ + "MONITOR_IMUX4_7", + "VFRAME_IMUX4" + ], + [ + "MONITOR_WW4B0_7", + "VFRAME_WW4B0" + ], + [ + "MONITOR_EE4A0_7", + "VFRAME_EE4A0" + ], + [ + "MONITOR_NW4END3_7", + "VFRAME_NW4END3" + ], + [ + "MONITOR_LH9_7", + "VFRAME_LH9" + ], + [ + "MONITOR_WW2A2_7", + "VFRAME_WW2A2" + ], + [ + "MONITOR_SE4C2_7", + "VFRAME_SE4C2" + ], + [ + "MONITOR_BYP4_7", + "VFRAME_BYP4" + ], + [ + "MONITOR_IMUX9_7", + "VFRAME_IMUX9" + ], + [ + "MONITOR_IMUX33_7", + "VFRAME_IMUX33" + ], + [ + "MONITOR_EL1BEG0_7", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_IMUX13_7", + "VFRAME_IMUX13" + ], + [ + "MONITOR_WL1END3_7", + "VFRAME_WL1END3" + ], + [ + "MONITOR_LH2_7", + "VFRAME_LH2" + ], + [ + "MONITOR_SW2A2_7", + "VFRAME_SW2A2" + ], + [ + "MONITOR_IMUX41_7", + "VFRAME_IMUX41" + ], + [ + "MONITOR_EE4C1_7", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX45_7", + "VFRAME_IMUX45" + ], + [ + "MONITOR_FAN1_7", + "VFRAME_FAN1" + ], + [ + "MONITOR_FAN0_7", + "VFRAME_FAN0" + ], + [ + "MONITOR_WL1END1_7", + "VFRAME_WL1END1" + ], + [ + "MONITOR_IMUX44_7", + "VFRAME_IMUX44" + ], + [ + "MONITOR_ER1BEG0_7", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_SE2A3_7", + "VFRAME_SE2A3" + ], + [ + "MONITOR_IMUX40_7", + "VFRAME_IMUX40" + ], + [ + "MONITOR_WR1END1_7", + "VFRAME_WR1END1" + ], + [ + "MONITOR_NW2A1_7", + "VFRAME_NW2A1" + ], + [ + "MONITOR_WW2END2_7", + "VFRAME_WW2END2" + ], + [ + "MONITOR_NW4A3_7", + "VFRAME_NW4A3" + ], + [ + "MONITOR_SW4A3_7", + "VFRAME_SW4A3" + ], + [ + "MONITOR_ER1BEG2_7", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_EE2A2_7", + "VFRAME_EE2A2" + ], + [ + "MONITOR_EE4C2_7", + "VFRAME_EE4C2" + ], + [ + "MONITOR_NE2A0_7", + "VFRAME_NE2A0" + ], + [ + "MONITOR_WW4A2_7", + "VFRAME_WW4A2" + ], + [ + "MONITOR_EE4A3_7", + "VFRAME_EE4A3" + ], + [ + "MONITOR_SE4BEG3_7", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_IMUX47_7", + "VFRAME_IMUX47" + ], + [ + "MONITOR_WW2END0_7", + "VFRAME_WW2END0" + ], + [ + "MONITOR_IMUX21_7", + "VFRAME_IMUX21" + ], + [ + "MONITOR_NW2A3_7", + "VFRAME_NW2A3" + ], + [ + "MONITOR_LH3_7", + "VFRAME_LH3" + ], + [ + "MONITOR_EE2BEG2_7", + "VFRAME_EE2BEG2" + ] + ], + "tile_types": [ + "MONITOR_MID_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + -13 + ], + "wire_pairs": [ + [ + "CMT_PHASER_UP_PHASERREF_ABOVE1", + "CMT_PLL_PHASERREF_ABOVE1" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL3", + "CMT_TOP_L_UPPER_T_CLKPLL3" + ], + [ + "CMT_PHASERD_DTSBUS0", + "CMT_PLL_PHASERD_DTSBUS0" + ], + [ + "CMT_PHASER_OUT_D_OCLK", + "CMT_PLL_PHASER_OUT_D_OCLK" + ], + [ + "CMT_PHASER_UP_PHASERREF0", + "CMT_PLL_PHASERREF0" + ], + [ + "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "PLLOUT_CLK_FREQ_BB_2" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL2", + "CMT_TOP_L_UPPER_T_CLKPLL2" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT3", + "PLL_CLK_FREQ_BB3_NS" + ], + [ + "CMT_R_PHASER_IN_D_WRCLK_TOFIFO", + "CMT_PLL_PHASER_WRCLK_TOFIFO" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT1", + "PLL_CLK_FREQ_BB1_NS" + ], + [ + "CMT_PHASERD_CTSBUS1", + "CMT_PLL_PHASERD_CTSBUS1" + ], + [ + "CMT_PHASER_IN_D_ICLKDIV", + "CMT_PLL_PHASER_IN_D_ICLKDIV" + ], + [ + "CMT_PHASERD_CTSBUS0", + "CMT_PLL_PHASERD_CTSBUS0" + ], + [ + "CMT_PHASER_OUT_D_OCLKDIV", + "CMT_PLL_PHASER_OUT_D_OCLKDIV" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL5", + "CMT_TOP_L_UPPER_T_CLKPLL5" + ], + [ + "CMT_PHASER_UP_PHASERREF1", + "CMT_PLL_PHASERREF1" + ], + [ + "CMT_PHASERD_DTSBUS1", + "CMT_PLL_PHASERD_DTSBUS1" + ], + [ + "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO", + "CMT_PLL_PHASER_RDCLK_TOFIFO" + ], + [ + "CMT_R_TOP_UPPER_B_CLKIN2", + "CMT_TOP_L_UPPER_T_CLKIN2" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL6", + "CMT_TOP_L_UPPER_T_CLKPLL6" + ], + [ + "CMT_R_TOP_UPPER_B_CLKIN1", + "CMT_TOP_L_UPPER_T_CLKIN1" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL4", + "CMT_TOP_L_UPPER_T_CLKPLL4" + ], + [ + "CMT_R_TOP_UPPER_B_CLKFBIN", + "CMT_TOP_L_UPPER_T_CLKFBIN" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL0", + "CMT_TOP_L_UPPER_T_CLKPLL0" + ], + [ + "CMT_PHASERD_DQSBUS0", + "CMT_PLL_PHASERD_DQSBUS0" + ], + [ + "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "PLLOUT_CLK_FREQ_BB_0" + ], + [ + "CMT_PHASER_UP_PHASERREF_ABOVE0", + "CMT_PLL_PHASERREF_ABOVE0" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT2", + "PLL_CLK_FREQ_BB2_NS" + ], + [ + "CMT_PHASER_IN_D_ICLK", + "CMT_PLL_PHASER_IN_D_ICLK" + ], + [ + "CMT_PHASER_TOP_SYNC_BB", + "CMT_PLL_PHYCTRL_SYNC_BB_DN" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT0", + "PLL_CLK_FREQ_BB0_NS" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL1", + "CMT_TOP_L_UPPER_T_CLKPLL1" + ], + [ + "CMT_PHASER_OUT_D_OCLK1X_90", + "CMT_PLL_PHASER_OUT_D_OCLK1X_90" + ], + [ + "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "PLLOUT_CLK_FREQ_BB_3" + ], + [ + "CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO", + "CMT_PLL_PHASER_RDENABLE_TOFIFO" + ], + [ + "CMT_PHASERD_DQSBUS1", + "CMT_PLL_PHASERD_DQSBUS1" + ], + [ + "CMT_PHASER_UP_PHASERREF_BELOW1", + "CMT_PLL_PHASERREF_BELOW1" + ], + [ + "CMT_PHASER_IN_D_WRENABLE_FIFO", + "CMT_PLL_PHASER_WRENABLE_TOFIFO" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL7", + "CMT_TOP_L_UPPER_T_CLKPLL7" + ], + [ + "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "PLLOUT_CLK_FREQ_BB_1" + ], + [ + "CMT_PHASER_UP_PHASERREF_BELOW0", + "CMT_PLL_PHASERREF_BELOW0" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "CMT_TOP_L_UPPER_T" + ] + }, + { + "grid_deltas": [ + -1, + 7 + ], + "wire_pairs": [ + [ + "CMT_PMV_LOGIC_OUTS8", + "CMT_TOP_LOGIC_OUTS_L_B8_12" + ], + [ + "CMT_PMV_IMUX25", + "CMT_TOP_IMUX25_12" + ], + [ + "CMT_PMV_IMUX3", + "CMT_TOP_IMUX3_12" + ], + [ + "CMT_PMV_IMUX24", + "CMT_TOP_IMUX24_12" + ], + [ + "CMT_PMV_IMUX29", + "CMT_TOP_IMUX29_12" + ], + [ + "CMT_PMV_WW2A2", + "CMT_TOP_WW2A2_12" + ], + [ + "CMT_PMV_EE4B2", + "CMT_TOP_EE4B2_12" + ], + [ + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "CMT_TOP_ICLKDIV_12" + ], + [ + "CMT_PMV_IMUX30", + "CMT_TOP_IMUX30_12" + ], + [ + "CMT_PMV_WW4C1", + "CMT_TOP_WW4C1_12" + ], + [ + "CMT_PMV_LOGIC_OUTS5", + "CMT_TOP_LOGIC_OUTS_L_B5_12" + ], + [ + "CMT_PMV_WW4END1", + "CMT_TOP_WW4END1_12" + ], + [ + "CMT_PMV_IMUX46", + "CMT_TOP_IMUX46_12" + ], + [ + "CMT_PMV_SE4BEG3", + "CMT_TOP_SE4BEG3_12" + ], + [ + "CMT_PMV_EE2BEG0", + "CMT_TOP_EE2BEG0_12" + ], + [ + "CMT_PMV_IMUX7", + "CMT_TOP_IMUX7_12" + ], + [ + "CMT_PMV_WW4A1", + "CMT_TOP_WW4A1_12" + ], + [ + "CMT_PMV_SE2A3", + "CMT_TOP_SE2A3_12" + ], + [ + "CMT_PMV_EE4C3", + "CMT_TOP_EE4C3_12" + ], + [ + "CMT_PMV_IMUX40", + "CMT_TOP_IMUX40_12" + ], + [ + "CMT_PMV_FAN3", + "CMT_TOP_FAN3_12" + ], + [ + "CMT_PMV_NW4END3", + "CMT_TOP_NW4END3_12" + ], + [ + "CMT_PMV_EE2A1", + "CMT_TOP_EE2A1_12" + ], + [ + "CMT_PMV_WW2A3", + "CMT_TOP_WW2A3_12" + ], + [ + "CMT_PMV_EE4BEG2", + "CMT_TOP_EE4BEG2_12" + ], + [ + "CMT_PMV_BYP0", + "CMT_TOP_BYP0_12" + ], + [ + "CMT_PMV_IMUX5", + "CMT_TOP_IMUX5_12" + ], + [ + "CMT_PMV_WW2A1", + "CMT_TOP_WW2A1_12" + ], + [ + "CMT_PMV_EE4BEG3", + "CMT_TOP_EE4BEG3_12" + ], + [ + "CMT_PMV_EE4B1", + "CMT_TOP_EE4B1_12" + ], + [ + "CMT_PMV_SW4A0", + "CMT_TOP_SW4A0_12" + ], + [ + "CMT_PMV_LOGIC_OUTS0", + "CMT_TOP_LOGIC_OUTS_L_B0_12" + ], + [ + "CMT_PMV_IMUX12", + "CMT_TOP_IMUX12_12" + ], + [ + "CMT_PMV_SE4BEG0", + "CMT_TOP_SE4BEG0_12" + ], + [ + "CMT_PMV_IMUX39", + "CMT_TOP_IMUX39_12" + ], + [ + "CMT_PMV_IMUX23", + "CMT_TOP_IMUX23_12" + ], + [ + "CMT_PMV_NE2A3", + "CMT_TOP_NE2A3_12" + ], + [ + "CMT_PMV_NW4A0", + "CMT_TOP_NW4A0_12" + ], + [ + "CMT_PMV_NE4C1", + "CMT_TOP_NE4C1_12" + ], + [ + "CMT_PMV_LOGIC_OUTS22", + "CMT_TOP_LOGIC_OUTS_L_B22_12" + ], + [ + "CMT_PMV_LH7", + "CMT_TOP_LH7_12" + ], + [ + "CMT_PMV_NW2A1", + "CMT_TOP_NW2A1_12" + ], + [ + "CMT_PMV_SE2A1", + "CMT_TOP_SE2A1_12" + ], + [ + "CMT_PMV_IMUX17", + "CMT_TOP_IMUX17_12" + ], + [ + "CMT_PMV_IMUX28", + "CMT_TOP_IMUX28_12" + ], + [ + "CMT_PMV_FAN0", + "CMT_TOP_FAN0_12" + ], + [ + "CMT_PMV_LOGIC_OUTS23", + "CMT_TOP_LOGIC_OUTS_L_B23_12" + ], + [ + "CMT_PMV_NE4C2", + "CMT_TOP_NE4C2_12" + ], + [ + "CMT_PMV_SE4BEG2", + "CMT_TOP_SE4BEG2_12" + ], + [ + "CMT_PMV_IMUX47", + "CMT_TOP_IMUX47_12" + ], + [ + "CMT_PMV_IMUX0", + "CMT_TOP_IMUX0_12" + ], + [ + "CMT_PMV_IMUX21", + "CMT_TOP_IMUX21_12" + ], + [ + "CMT_PMV_NW4A2", + "CMT_TOP_NW4A2_12" + ], + [ + "CMT_PMV_NE2A0", + "CMT_TOP_NE2A0_12" + ], + [ + "CMT_PMV_WW4END2", + "CMT_TOP_WW4END2_12" + ], + [ + "CMT_PMV_WW4B0", + "CMT_TOP_WW4B0_12" + ], + [ + "CMT_PMV_LH8", + "CMT_TOP_LH8_12" + ], + [ + "CMT_PMV_IMUX20", + "CMT_TOP_IMUX20_12" + ], + [ + "CMT_PMV_SW2A0", + "CMT_TOP_SW2A0_12" + ], + [ + "CMT_PMV_NE2A1", + "CMT_TOP_NE2A1_12" + ], + [ + "CMT_PMV_NW2A0", + "CMT_TOP_NW2A0_12" + ], + [ + "CMT_PMV_EE4A3", + "CMT_TOP_EE4A3_12" + ], + [ + "CMT_PMV_LH1", + "CMT_TOP_LH1_12" + ], + [ + "CMT_PMV_SW2A3", + "CMT_TOP_SW2A3_12" + ], + [ + "CMT_PMV_EE2BEG1", + "CMT_TOP_EE2BEG1_12" + ], + [ + "CMT_PMV_IMUX44", + "CMT_TOP_IMUX44_12" + ], + [ + "CMT_PMV_WL1END1", + "CMT_TOP_WL1END1_12" + ], + [ + "CMT_PMV_LOGIC_OUTS13", + "CMT_TOP_LOGIC_OUTS_L_B13_12" + ], + [ + "CMT_PMV_BYP3", + "CMT_TOP_BYP3_12" + ], + [ + "CMT_PMV_WW4B2", + "CMT_TOP_WW4B2_12" + ], + [ + "CMT_PMV_IMUX33", + "CMT_TOP_IMUX33_12" + ], + [ + "CMT_PMV_EE4B3", + "CMT_TOP_EE4B3_12" + ], + [ + "CMT_PMV_LH5", + "CMT_TOP_LH5_12" + ], + [ + "CMT_PMV_BYP2", + "CMT_TOP_BYP2_12" + ], + [ + "CMT_PMV_ER1BEG1", + "CMT_TOP_ER1BEG1_12" + ], + [ + "CMT_PMV_SE2A0", + "CMT_TOP_SE2A0_12" + ], + [ + "CMT_PMV_WW2END3", + "CMT_TOP_WW2END3_12" + ], + [ + "CMT_PMV_IMUX38", + "CMT_TOP_IMUX38_12" + ], + [ + "CMT_PMV_BYP5", + "CMT_TOP_BYP5_12" + ], + [ + "CMT_PMV_SW4END3", + "CMT_TOP_SW4END3_12" + ], + [ + "CMT_PMV_NE4BEG3", + "CMT_TOP_NE4BEG3_12" + ], + [ + "CMT_PMV_NE4BEG1", + "CMT_TOP_NE4BEG1_12" + ], + [ + "CMT_PMV_EE2A0", + "CMT_TOP_EE2A0_12" + ], + [ + "CMT_PMV_LOGIC_OUTS7", + "CMT_TOP_LOGIC_OUTS_L_B7_12" + ], + [ + "CMT_PMV_WW4B1", + "CMT_TOP_WW4B1_12" + ], + [ + "CMT_PMV_LH10", + "CMT_TOP_LH10_12" + ], + [ + "CMT_PMV_WW4C0", + "CMT_TOP_WW4C0_12" + ], + [ + "CMT_PMV_IMUX19", + "CMT_TOP_IMUX19_12" + ], + [ + "CMT_PMV_IMUX6", + "CMT_TOP_IMUX6_12" + ], + [ + "CMT_PMV_IMUX11", + "CMT_TOP_IMUX11_12" + ], + [ + "CMT_PMV_NW4A3", + "CMT_TOP_NW4A3_12" + ], + [ + "CMT_PMV_LOGIC_OUTS21", + "CMT_TOP_LOGIC_OUTS_L_B21_12" + ], + [ + "CMT_PMV_LOGIC_OUTS19", + "CMT_TOP_LOGIC_OUTS_L_B19_12" + ], + [ + "CMT_PMV_IMUX43", + "CMT_TOP_IMUX43_12" + ], + [ + "CMT_PMV_WW2A0", + "CMT_TOP_WW2A0_12" + ], + [ + "CMT_PMV_BYP4", + "CMT_TOP_BYP4_12" + ], + [ + "CMT_PMV_WR1END0", + "CMT_TOP_WR1END0_12" + ], + [ + "CMT_PMV_SE2A2", + "CMT_TOP_SE2A2_12" + ], + [ + "CMT_PMV_EE2BEG2", + "CMT_TOP_EE2BEG2_12" + ], + [ + "CMT_PMV_WR1END3", + "CMT_TOP_WR1END3_12" + ], + [ + "CMT_PMV_LOGIC_OUTS16", + "CMT_TOP_LOGIC_OUTS_L_B16_12" + ], + [ + "L_TERM_INT_PHASER_TO_IO_OCLK", + "CMT_TOP_OCLK_12" + ], + [ + "CMT_PMV_NE4BEG2", + "CMT_TOP_NE4BEG2_12" + ], + [ + "CMT_PMV_WR1END1", + "CMT_TOP_WR1END1_12" + ], + [ + "CMT_PMV_WW2END0", + "CMT_TOP_WW2END0_12" + ], + [ + "CMT_PMV_NW4END1", + "CMT_TOP_NW4END1_12" + ], + [ + "CMT_PMV_LOGIC_OUTS20", + "CMT_TOP_LOGIC_OUTS_L_B20_12" + ], + [ + "CMT_PMV_IMUX14", + "CMT_TOP_IMUX14_12" + ], + [ + "CMT_PMV_WW4END0", + "CMT_TOP_WW4END0_12" + ], + [ + "CMT_PMV_WW4C3", + "CMT_TOP_WW4C3_12" + ], + [ + "CMT_PMV_WW4B3", + "CMT_TOP_WW4B3_12" + ], + [ + "CMT_PMV_NW2A3", + "CMT_TOP_NW2A3_12" + ], + [ + "CMT_PMV_NW4END2", + "CMT_TOP_NW4END2_12" + ], + [ + "CMT_PMV_FAN1", + "CMT_TOP_FAN1_12" + ], + [ + "CMT_PMV_SW4A3", + "CMT_TOP_SW4A3_12" + ], + [ + "CMT_PMV_SE4C3", + "CMT_TOP_SE4C3_12" + ], + [ + "CMT_PMV_IMUX4", + "CMT_TOP_IMUX4_12" + ], + [ + "CMT_PMV_NE4C0", + "CMT_TOP_NE4C0_12" + ], + [ + "CMT_PMV_LH3", + "CMT_TOP_LH3_12" + ], + [ + "CMT_PMV_IMUX16", + "CMT_TOP_IMUX16_12" + ], + [ + "CMT_PMV_EL1BEG1", + "CMT_TOP_EL1BEG1_12" + ], + [ + "CMT_PMV_IMUX35", + "CMT_TOP_IMUX35_12" + ], + [ + "CMT_PMV_IMUX26", + "CMT_TOP_IMUX26_12" + ], + [ + "CMT_PMV_EE2A3", + "CMT_TOP_EE2A3_12" + ], + [ + "CMT_PMV_WW4C2", + "CMT_TOP_WW4C2_12" + ], + [ + "CMT_PMV_NW2A2", + "CMT_TOP_NW2A2_12" + ], + [ + "CMT_PMV_IMUX41", + "CMT_TOP_IMUX41_12" + ], + [ + "CMT_PMV_IMUX37", + "CMT_TOP_IMUX37_12" + ], + [ + "CMT_PMV_NE4BEG0", + "CMT_TOP_NE4BEG0_12" + ], + [ + "CMT_PMV_BYP1", + "CMT_TOP_BYP1_12" + ], + [ + "CMT_PMV_EE4A1", + "CMT_TOP_EE4A1_12" + ], + [ + "CMT_PMV_CTRL1", + "CMT_TOP_CTRL1_12" + ], + [ + "CMT_PMV_WW2END1", + "CMT_TOP_WW2END1_12" + ], + [ + "CMT_PMV_SE4C0", + "CMT_TOP_SE4C0_12" + ], + [ + "CMT_PMV_FAN5", + "CMT_TOP_FAN5_12" + ], + [ + "CMT_PMV_IMUX31", + "CMT_TOP_IMUX31_12" + ], + [ + "CMT_PMV_SW2A1", + "CMT_TOP_SW2A1_12" + ], + [ + "CMT_PMV_EE4B0", + "CMT_TOP_EE4B0_12" + ], + [ + "CMT_PMV_WW4A0", + "CMT_TOP_WW4A0_12" + ], + [ + "L_TERM_INT_PHASER_TO_IO_ICLK", + "CMT_TOP_ICLK_12" + ], + [ + "CMT_PMV_IMUX32", + "CMT_TOP_IMUX32_12" + ], + [ + "CMT_PMV_ER1BEG0", + "CMT_TOP_ER1BEG0_12" + ], + [ + "CMT_PMV_WL1END2", + "CMT_TOP_WL1END2_12" + ], + [ + "CMT_PMV_WW4A3", + "CMT_TOP_WW4A3_12" + ], + [ + "CMT_PMV_SW4END0", + "CMT_TOP_SW4END0_12" + ], + [ + "CMT_PMV_FAN7", + "CMT_TOP_FAN7_12" + ], + [ + "CMT_PMV_SW4END1", + "CMT_TOP_SW4END1_12" + ], + [ + "CMT_PMV_LH11", + "CMT_TOP_LH11_12" + ], + [ + "CMT_PMV_LH12", + "CMT_TOP_LH12_12" + ], + [ + "CMT_PMV_WW2END2", + "CMT_TOP_WW2END2_12" + ], + [ + "CMT_PMV_EE4A2", + "CMT_TOP_EE4A2_12" + ], + [ + "CMT_PMV_NW4A1", + "CMT_TOP_NW4A1_12" + ], + [ + "CMT_PMV_IMUX18", + "CMT_TOP_IMUX18_12" + ], + [ + "CMT_PMV_SE4C2", + "CMT_TOP_SE4C2_12" + ], + [ + "CMT_PMV_EL1BEG0", + "CMT_TOP_EL1BEG0_12" + ], + [ + "CMT_PMV_BYP6", + "CMT_TOP_BYP6_12" + ], + [ + "CMT_PMV_WW4END3", + "CMT_TOP_WW4END3_12" + ], + [ + "CMT_PMV_EE4C0", + "CMT_TOP_EE4C0_12" + ], + [ + "CMT_PMV_FAN4", + "CMT_TOP_FAN4_12" + ], + [ + "CMT_PMV_LOGIC_OUTS18", + "CMT_TOP_LOGIC_OUTS_L_B18_12" + ], + [ + "CMT_PMV_NW4END0", + "CMT_TOP_NW4END0_12" + ], + [ + "CMT_PMV_FAN2", + "CMT_TOP_FAN2_12" + ], + [ + "CMT_PMV_BYP7", + "CMT_TOP_BYP7_12" + ], + [ + "CMT_PMV_LH9", + "CMT_TOP_LH9_12" + ], + [ + "CMT_PMV_LH6", + "CMT_TOP_LH6_12" + ], + [ + "CMT_PMV_IMUX22", + "CMT_TOP_IMUX22_12" + ], + [ + "CMT_PMV_WW4A2", + "CMT_TOP_WW4A2_12" + ], + [ + "CMT_PMV_CLK0", + "CMT_TOP_CLK0_12" + ], + [ + "CMT_PMV_EE2A2", + "CMT_TOP_EE2A2_12" + ], + [ + "CMT_PMV_CLK1", + "CMT_TOP_CLK1_12" + ], + [ + "CMT_PMV_LH4", + "CMT_TOP_LH4_12" + ], + [ + "CMT_PMV_NE2A2", + "CMT_TOP_NE2A2_12" + ], + [ + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "CMT_TOP_OCLKDIV_12" + ], + [ + "CMT_PMV_EL1BEG2", + "CMT_TOP_EL1BEG2_12" + ], + [ + "CMT_PMV_WL1END0", + "CMT_TOP_WL1END0_12" + ], + [ + "CMT_PMV_LOGIC_OUTS17", + "CMT_TOP_LOGIC_OUTS_L_B17_12" + ], + [ + "CMT_PMV_SW4A1", + "CMT_TOP_SW4A1_12" + ], + [ + "CMT_PMV_IMUX2", + "CMT_TOP_IMUX2_12" + ], + [ + "CMT_PMV_EL1BEG3", + "CMT_TOP_EL1BEG3_12" + ], + [ + "CMT_PMV_EE4A0", + "CMT_TOP_EE4A0_12" + ], + [ + "CMT_PMV_IMUX34", + "CMT_TOP_IMUX34_12" + ], + [ + "CMT_PMV_IMUX9", + "CMT_TOP_IMUX9_12" + ], + [ + "CMT_PMV_IMUX42", + "CMT_TOP_IMUX42_12" + ], + [ + "CMT_PMV_IMUX27", + "CMT_TOP_IMUX27_12" + ], + [ + "CMT_PMV_ER1BEG3", + "CMT_TOP_ER1BEG3_12" + ], + [ + "CMT_PMV_SE4BEG1", + "CMT_TOP_SE4BEG1_12" + ], + [ + "CMT_PMV_IMUX45", + "CMT_TOP_IMUX45_12" + ], + [ + "CMT_PMV_IMUX10", + "CMT_TOP_IMUX10_12" + ], + [ + "CMT_PMV_WR1END2", + "CMT_TOP_WR1END2_12" + ], + [ + "CMT_PMV_EE4C2", + "CMT_TOP_EE4C2_12" + ], + [ + "CMT_PMV_SW2A2", + "CMT_TOP_SW2A2_12" + ], + [ + "CMT_PMV_EE4BEG0", + "CMT_TOP_EE4BEG0_12" + ], + [ + "CMT_PMV_EE4BEG1", + "CMT_TOP_EE4BEG1_12" + ], + [ + "CMT_PMV_EE2BEG3", + "CMT_TOP_EE2BEG3_12" + ], + [ + "CMT_PMV_IMUX13", + "CMT_TOP_IMUX13_12" + ], + [ + "CMT_PMV_ER1BEG2", + "CMT_TOP_ER1BEG2_12" + ], + [ + "CMT_PMV_IMUX8", + "CMT_TOP_IMUX8_12" + ], + [ + "CMT_PMV_EE4C1", + "CMT_TOP_EE4C1_12" + ], + [ + "CMT_PMV_IMUX1", + "CMT_TOP_IMUX1_12" + ], + [ + "CMT_PMV_SE4C1", + "CMT_TOP_SE4C1_12" + ], + [ + "CMT_PMV_FAN6", + "CMT_TOP_FAN6_12" + ], + [ + "CMT_PMV_CTRL0", + "CMT_TOP_CTRL0_12" + ], + [ + "CMT_PMV_SW4END2", + "CMT_TOP_SW4END2_12" + ], + [ + "CMT_PMV_WL1END3", + "CMT_TOP_WL1END3_12" + ], + [ + "CMT_PMV_NE4C3", + "CMT_TOP_NE4C3_12" + ], + [ + "CMT_PMV_LOGIC_OUTS15", + "CMT_TOP_LOGIC_OUTS_L_B15_12" + ], + [ + "CMT_PMV_LOGIC_OUTS10", + "CMT_TOP_LOGIC_OUTS_L_B10_12" + ], + [ + "CMT_PMV_IMUX15", + "CMT_TOP_IMUX15_12" + ], + [ + "CMT_PMV_SW4A2", + "CMT_TOP_SW4A2_12" + ], + [ + "CMT_PMV_LOGIC_OUTS2", + "CMT_TOP_LOGIC_OUTS_L_B2_12" + ], + [ + "CMT_PMV_IMUX36", + "CMT_TOP_IMUX36_12" + ], + [ + "CMT_PMV_LH2", + "CMT_TOP_LH2_12" + ] + ], + "tile_types": [ + "CMT_PMV_L", + "CMT_TOP_L_UPPER_T" + ] + }, + { + "grid_deltas": [ + 5, + -2 + ], + "wire_pairs": [ + [ + "PCIE_IMUX47_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_NW4A2_12", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_IMUX12_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_FAN3_L_12", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_SW4A1_12", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_IMUX22_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_IMUX44_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_SW4END0_12", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_NW2A1_12", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_BYP7_L_12", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_SE4C0_12", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_NE4BEG0_12", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_NW4END2_12", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_BYP1_L_12", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_NE4C2_12", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_NE4C0_12", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_IMUX18_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_EE4B2_12", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_IMUX37_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_IMUX34_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_EE2BEG2_12", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_IMUX9_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_LH2_12", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_IMUX28_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_IMUX15_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_SW4A2_12", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_WL1END3_12", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_IMUX19_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_BYP4_L_12", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_NE4C1_12", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_NW2A0_12", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_LH10_12", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_SE4C1_12", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_FAN7_L_12", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_EE4A1_12", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_EE4BEG2_12", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_SE4BEG3_12", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_WR1END3_12", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_EE2BEG1_12", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_EE2A2_12", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_EE2BEG3_12", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_NW4A0_12", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WW4END0_12", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_WR1END0_12", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_FAN0_L_12", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_EL1BEG0_12", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_LH11_12", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_NW4END3_12", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_WW2A2_12", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_FAN4_L_12", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_EE4B0_12", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_EE4BEG0_12", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX16_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_WW2END0_12", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_SE4BEG2_12", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_NW4END0_12", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_LH6_12", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_WW4B0_12", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_IMUX10_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_SE2A0_12", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_WW4B2_12", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_NW2A3_12", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_WW4A1_12", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_IMUX42_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_BYP6_L_12", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_IMUX23_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_IMUX5_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_WW2A0_12", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_IMUX8_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_EE4C3_12", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_NE2A1_12", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_EE2A1_12", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_IMUX4_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_WW4END2_12", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_SW4A0_12", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_EE4C0_12", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_WW4A3_12", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_BYP3_L_12", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_CTRL0_L_12", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_FAN2_L_12", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_WW4C3_12", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_EE4C1_12", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_IMUX2_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_WR1END2_12", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_FAN5_L_12", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_BYP2_L_12", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_WW4END1_12", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_LH5_12", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_SE2A3_12", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_NE2A2_12", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_IMUX17_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_EE2A0_12", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_NW2A2_12", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_SW4END3_12", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_WR1END1_12", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_WW2END2_12", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_NE4C3_12", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_IMUX25_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_CLK0_L_12", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_CTRL1_L_12", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_FAN6_L_12", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_SE4C2_12", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_NW4END1_12", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_IMUX45_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_NE2A3_12", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_ER1BEG1_12", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_WW2A1_12", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_IMUX21_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_EL1BEG2_12", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_IMUX41_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_WW2A3_12", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_LH9_12", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_WW4C1_12", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_LH8_12", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_LH12_12", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_SW2A3_12", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_SW2A1_12", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_SW4END1_12", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_IMUX27_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_IMUX29_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_WW4A2_12", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_EE2A3_12", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_WW2END3_12", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_IMUX0_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_SW4END2_12", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_ER1BEG0_12", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_ER1BEG3_12", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_IMUX6_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_WW4C2_12", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_IMUX13_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_WL1END1_12", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_FAN1_L_12", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_NE4BEG3_12", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_EL1BEG3_12", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_CLK1_L_12", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_NW4A3_12", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_EE4BEG3_12", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_LH7_12", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_SE2A1_12", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_NE4BEG2_12", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_SE4BEG0_12", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_SE2A2_12", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_IMUX30_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_NE2A0_12", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_WW4B3_12", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_LH1_12", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_IMUX39_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_EE4B1_12", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_EL1BEG1_12", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_IMUX33_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_IMUX1_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_SE4BEG1_12", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_IMUX36_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_IMUX31_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_IMUX32_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_LH3_12", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_IMUX20_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_SE4C3_12", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_IMUX14_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_NW4A1_12", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_EE4C2_12", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_EE2BEG0_12", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_EE4A3_12", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_WL1END2_12", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_WW4B1_12", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_WW4END3_12", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_EE4A0_12", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_BYP5_L_12", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_IMUX11_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_SW2A2_12", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_EE4A2_12", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_IMUX43_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_NE4BEG1_12", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_WW4C0_12", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_IMUX38_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_SW4A3_12", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_IMUX24_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_IMUX46_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_IMUX40_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_IMUX26_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_WW4A0_12", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_WW2END1_12", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_SW2A0_12", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX3_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_EE4B3_12", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_LH4_12", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_ER1BEG2_12", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_EE4BEG1_12", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_BYP0_L_12", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_IMUX7_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_IMUX35_L_12", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_WL1END0_12", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_12", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_FIFO_CCIO0", + "HCLK_INT_INTERFACE_CCIO0" + ], + [ + "HCLK_FIFO_CCIO1", + "HCLK_INT_INTERFACE_CCIO1" + ], + [ + "HCLK_FIFO_PERFCLK2", + "HCLK_INT_INTERFACE_PERFCLK2" + ], + [ + "HCLK_FIFO_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_FIFO_PERFCLK0", + "HCLK_INT_INTERFACE_PERFCLK0" + ], + [ + "HCLK_FIFO_CCIO3", + "HCLK_INT_INTERFACE_CCIO3" + ], + [ + "HCLK_FIFO_PERFCLK3", + "HCLK_INT_INTERFACE_PERFCLK3" + ], + [ + "HCLK_FIFO_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_FIFO_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_FIFO_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_FIFO_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_FIFO_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_FIFO_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_FIFO_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_FIFO_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_FIFO_PERFCLK1", + "HCLK_INT_INTERFACE_PERFCLK1" + ], + [ + "HCLK_FIFO_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_FIFO_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_FIFO_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_FIFO_CCIO2", + "HCLK_INT_INTERFACE_CCIO2" + ], + [ + "HCLK_FIFO_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_FIFO_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_FIFO_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_FIFO_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ] + ], + "tile_types": [ + "HCLK_FIFO_L", + "HCLK_INT_INTERFACE" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ] + ], + "tile_types": [ + "HCLK_DSP_L", + "HCLK_VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -6 + ], + "wire_pairs": [ + [ + "GTXE2_CHANNEL_RXOUTCLK_3", + "GTXE2_COMMON_RXOUTCLK_3" + ], + [ + "GTXE2_CHANNEL_QPLLCLK", + "GTXE2_COMMON_QPLLOUTCLK" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_3", + "GTXE2_COMMON_TXOUTCLK_3" + ], + [ + "GTXE2_CHANNEL_SOUTHREFCLK1", + "GTXE2_COMMON_SOUTHREFCLK1" + ], + [ + "GTXE2_CHANNEL_RXOUTCLK_0", + "GTXE2_COMMON_RXOUTCLK_0" + ], + [ + "GTXE2_CHANNEL_RXOUTCLK_2", + "GTXE2_COMMON_RXOUTCLK_2" + ], + [ + "GTXE2_CHANNEL_NORTHREFCLK0", + "GTXE2_COMMON_NORTHREFCLK0" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_2", + "GTXE2_COMMON_TXOUTCLK_2" + ], + [ + "GTXE2_CHANNEL_REFCLK1", + "GTXE2_COMMON_REFCLK1" + ], + [ + "GTXE2_CHANNEL_REFCLK0", + "GTXE2_COMMON_REFCLK0" + ], + [ + "GTXE2_CHANNEL_NORTHREFCLK1", + "GTXE2_COMMON_NORTHREFCLK1" + ], + [ + "GTXE2_CHANNEL_SOUTHREFCLK0", + "GTXE2_COMMON_SOUTHREFCLK0" + ], + [ + "GTXE2_CHANNEL_QPLLREFCLK", + "GTXE2_COMMON_QPLLOUTREFCLK" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_0", + "GTXE2_COMMON_TXOUTCLK_0" + ], + [ + "GTXE2_CHANNEL_RXOUTCLK_1", + "GTXE2_COMMON_RXOUTCLK_1" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_1", + "GTXE2_COMMON_TXOUTCLK_1" + ] + ], + "tile_types": [ + "GTX_CHANNEL_1", + "GTX_COMMON" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "PCIE_INT_INTERFACE_IMUX_OUT31", + "PCIE_IMUX31_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT4", + "PCIE_IMUX4_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT32", + "PCIE_IMUX32_R_0" + ], + [ + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_0" + ], + [ + "INT_INTERFACE_LH5", + "PCIE_LH5_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT11", + "PCIE_IMUX11_R_0" + ], + [ + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_0" + ], + [ + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_0" + ], + [ + "INT_INTERFACE_EE4C1", + "PCIE_EE4C1_0" + ], + [ + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT19", + "PCIE_IMUX19_R_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B14", + "PCIE_LOGIC_OUTS_B14_R_0" + ], + [ + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_0" + ], + [ + "INT_INTERFACE_CLK1", + "PCIE_CLK1_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT5", + "PCIE_IMUX5_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT18", + "PCIE_IMUX18_R_0" + ], + [ + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_0" + ], + [ + "INT_INTERFACE_LH12", + "PCIE_LH12_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B22", + "PCIE_LOGIC_OUTS_B22_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT8", + "PCIE_IMUX8_R_0" + ], + [ + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_0" + ], + [ + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_0" + ], + [ + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B12", + "PCIE_LOGIC_OUTS_B12_R_0" + ], + [ + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_0" + ], + [ + "INT_INTERFACE_EE2BEG1", + "PCIE_EE2BEG1_0" + ], + [ + "INT_INTERFACE_BYP7", + "PCIE_BYP7_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT14", + "PCIE_IMUX14_R_0" + ], + [ + "INT_INTERFACE_EE2BEG3", + "PCIE_EE2BEG3_0" + ], + [ + "INT_INTERFACE_FAN3", + "PCIE_FAN3_R_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B17", + "PCIE_LOGIC_OUTS_B17_R_0" + ], + [ + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_0" + ], + [ + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_0" + ], + [ + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_0" + ], + [ + "INT_INTERFACE_BYP2", + "PCIE_BYP2_R_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B6", + "PCIE_LOGIC_OUTS_B6_R_0" + ], + [ + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_0" + ], + [ + "INT_INTERFACE_LH8", + "PCIE_LH8_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT16", + "PCIE_IMUX16_R_0" + ], + [ + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_0" + ], + [ + "INT_INTERFACE_LH7", + "PCIE_LH7_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B2", + "PCIE_LOGIC_OUTS_B2_R_0" + ], + [ + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT34", + "PCIE_IMUX34_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT41", + "PCIE_IMUX41_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT29", + "PCIE_IMUX29_R_0" + ], + [ + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_0" + ], + [ + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_0" + ], + [ + "INT_INTERFACE_EE2BEG2", + "PCIE_EE2BEG2_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B3", + "PCIE_LOGIC_OUTS_B3_R_0" + ], + [ + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_0" + ], + [ + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_0" + ], + [ + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_0" + ], + [ + "INT_INTERFACE_EE2A0", + "PCIE_EE2A0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT45", + "PCIE_IMUX45_R_0" + ], + [ + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_0" + ], + [ + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT25", + "PCIE_IMUX25_R_0" + ], + [ + "INT_INTERFACE_CLK0", + "PCIE_CLK0_R_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B4", + "PCIE_LOGIC_OUTS_B4_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT13", + "PCIE_IMUX13_R_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B11", + "PCIE_LOGIC_OUTS_B11_R_0" + ], + [ + "INT_INTERFACE_EE4C2", + "PCIE_EE4C2_0" + ], + [ + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT46", + "PCIE_IMUX46_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT27", + "PCIE_IMUX27_R_0" + ], + [ + "INT_INTERFACE_BYP3", + "PCIE_BYP3_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT30", + "PCIE_IMUX30_R_0" + ], + [ + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_0" + ], + [ + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_0" + ], + [ + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_0" + ], + [ + "INT_INTERFACE_BYP4", + "PCIE_BYP4_R_0" + ], + [ + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_0" + ], + [ + "INT_INTERFACE_EL1BEG3", + "PCIE_EL1BEG3_0" + ], + [ + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_0" + ], + [ + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT22", + "PCIE_IMUX22_R_0" + ], + [ + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_0" + ], + [ + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_0" + ], + [ + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_0" + ], + [ + "INT_INTERFACE_LH3", + "PCIE_LH3_0" + ], + [ + "INT_INTERFACE_EE2A1", + "PCIE_EE2A1_0" + ], + [ + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_0" + ], + [ + "INT_INTERFACE_BYP0", + "PCIE_BYP0_R_0" + ], + [ + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_0" + ], + [ + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT6", + "PCIE_IMUX6_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT42", + "PCIE_IMUX42_R_0" + ], + [ + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_0" + ], + [ + "INT_INTERFACE_LH6", + "PCIE_LH6_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT21", + "PCIE_IMUX21_R_0" + ], + [ + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_0" + ], + [ + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT44", + "PCIE_IMUX44_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT36", + "PCIE_IMUX36_R_0" + ], + [ + "INT_INTERFACE_CTRL0", + "PCIE_CTRL0_R_0" + ], + [ + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT20", + "PCIE_IMUX20_R_0" + ], + [ + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_0" + ], + [ + "INT_INTERFACE_LH11", + "PCIE_LH11_0" + ], + [ + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT0", + "PCIE_IMUX0_R_0" + ], + [ + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_0" + ], + [ + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_0" + ], + [ + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_0" + ], + [ + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_0" + ], + [ + "INT_INTERFACE_EE2A2", + "PCIE_EE2A2_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B18", + "PCIE_LOGIC_OUTS_B18_R_0" + ], + [ + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_0" + ], + [ + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B20", + "PCIE_LOGIC_OUTS_B20_R_0" + ], + [ + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B0", + "PCIE_LOGIC_OUTS_B0_R_0" + ], + [ + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_0" + ], + [ + "INT_INTERFACE_LH10", + "PCIE_LH10_0" + ], + [ + "INT_INTERFACE_FAN7", + "PCIE_FAN7_R_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B9", + "PCIE_LOGIC_OUTS_B9_R_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B5", + "PCIE_LOGIC_OUTS_B5_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT33", + "PCIE_IMUX33_R_0" + ], + [ + "INT_INTERFACE_FAN6", + "PCIE_FAN6_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT38", + "PCIE_IMUX38_R_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B23", + "PCIE_LOGIC_OUTS_B23_R_0" + ], + [ + "INT_INTERFACE_BYP6", + "PCIE_BYP6_R_0" + ], + [ + "INT_INTERFACE_EE4A0", + "PCIE_EE4A0_0" + ], + [ + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT40", + "PCIE_IMUX40_R_0" + ], + [ + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_0" + ], + [ + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_0" + ], + [ + "INT_INTERFACE_EE4C0", + "PCIE_EE4C0_0" + ], + [ + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_0" + ], + [ + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_0" + ], + [ + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_0" + ], + [ + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT35", + "PCIE_IMUX35_R_0" + ], + [ + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B15", + "PCIE_LOGIC_OUTS_B15_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT9", + "PCIE_IMUX9_R_0" + ], + [ + "INT_INTERFACE_EE4A2", + "PCIE_EE4A2_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B10", + "PCIE_LOGIC_OUTS_B10_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT23", + "PCIE_IMUX23_R_0" + ], + [ + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_0" + ], + [ + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_0" + ], + [ + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_0" + ], + [ + "INT_INTERFACE_FAN1", + "PCIE_FAN1_R_0" + ], + [ + "INT_INTERFACE_CTRL1", + "PCIE_CTRL1_R_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B8", + "PCIE_LOGIC_OUTS_B8_R_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B16", + "PCIE_LOGIC_OUTS_B16_R_0" + ], + [ + "INT_INTERFACE_LH4", + "PCIE_LH4_0" + ], + [ + "INT_INTERFACE_FAN0", + "PCIE_FAN0_R_0" + ], + [ + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_0" + ], + [ + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_0" + ], + [ + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_0" + ], + [ + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_0" + ], + [ + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_0" + ], + [ + "INT_INTERFACE_BYP5", + "PCIE_BYP5_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT10", + "PCIE_IMUX10_R_0" + ], + [ + "INT_INTERFACE_EE2BEG0", + "PCIE_EE2BEG0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT43", + "PCIE_IMUX43_R_0" + ], + [ + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_0" + ], + [ + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_0" + ], + [ + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_0" + ], + [ + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT2", + "PCIE_IMUX2_R_0" + ], + [ + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_0" + ], + [ + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B13", + "PCIE_LOGIC_OUTS_B13_R_0" + ], + [ + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_0" + ], + [ + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_0" + ], + [ + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_0" + ], + [ + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT12", + "PCIE_IMUX12_R_0" + ], + [ + "INT_INTERFACE_LH1", + "PCIE_LH1_0" + ], + [ + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_0" + ], + [ + "INT_INTERFACE_FAN4", + "PCIE_FAN4_R_0" + ], + [ + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_0" + ], + [ + "INT_INTERFACE_LH2", + "PCIE_LH2_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B1", + "PCIE_LOGIC_OUTS_B1_R_0" + ], + [ + "INT_INTERFACE_EE4B0", + "PCIE_EE4B0_0" + ], + [ + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_0" + ], + [ + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_0" + ], + [ + "INT_INTERFACE_BYP1", + "PCIE_BYP1_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT24", + "PCIE_IMUX24_R_0" + ], + [ + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_0" + ], + [ + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT39", + "PCIE_IMUX39_R_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B7", + "PCIE_LOGIC_OUTS_B7_R_0" + ], + [ + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT47", + "PCIE_IMUX47_R_0" + ], + [ + "INT_INTERFACE_FAN5", + "PCIE_FAN5_R_0" + ], + [ + "INT_INTERFACE_EE4A1", + "PCIE_EE4A1_0" + ], + [ + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_0" + ], + [ + "INT_INTERFACE_EE2A3", + "PCIE_EE2A3_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT15", + "PCIE_IMUX15_R_0" + ], + [ + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_0" + ], + [ + "INT_INTERFACE_ER1BEG0", + "PCIE_ER1BEG0_0" + ], + [ + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT7", + "PCIE_IMUX7_R_0" + ], + [ + "INT_INTERFACE_FAN2", + "PCIE_FAN2_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT26", + "PCIE_IMUX26_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT37", + "PCIE_IMUX37_R_0" + ], + [ + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_0" + ], + [ + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT17", + "PCIE_IMUX17_R_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT28", + "PCIE_IMUX28_R_0" + ], + [ + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_0" + ], + [ + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B19", + "PCIE_LOGIC_OUTS_B19_R_0" + ], + [ + "INT_INTERFACE_LH9", + "PCIE_LH9_0" + ], + [ + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_0" + ], + [ + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT3", + "PCIE_IMUX3_R_0" + ], + [ + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_0" + ], + [ + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_0" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT1", + "PCIE_IMUX1_R_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B21", + "PCIE_LOGIC_OUTS_B21_R_0" + ], + [ + "INT_INTERFACE_EE4A3", + "PCIE_EE4A3_0" + ] + ], + "tile_types": [ + "PCIE_INT_INTERFACE_R", + "PCIE_TOP" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_2" + ], + [ + "INT_INTERFACE_FAN7", + "PCIE_FAN7_R_2" + ], + [ + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT27", + "PCIE_IMUX27_R_2" + ], + [ + "INT_INTERFACE_BYP4", + "PCIE_BYP4_R_2" + ], + [ + "INT_INTERFACE_LH2", + "PCIE_LH2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT12", + "PCIE_IMUX12_R_2" + ], + [ + "INT_INTERFACE_EE4C2", + "PCIE_EE4C2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT31", + "PCIE_IMUX31_R_2" + ], + [ + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT18", + "PCIE_IMUX18_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT25", + "PCIE_IMUX25_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT21", + "PCIE_IMUX21_R_2" + ], + [ + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT38", + "PCIE_IMUX38_R_2" + ], + [ + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_2" + ], + [ + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B21", + "PCIE_LOGIC_OUTS_B21_R_2" + ], + [ + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_2" + ], + [ + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_2" + ], + [ + "INT_INTERFACE_FAN5", + "PCIE_FAN5_R_2" + ], + [ + "INT_INTERFACE_LH3", + "PCIE_LH3_2" + ], + [ + "INT_INTERFACE_EE4A1", + "PCIE_EE4A1_2" + ], + [ + "INT_INTERFACE_EE4A2", + "PCIE_EE4A2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B17", + "PCIE_LOGIC_OUTS_B17_R_2" + ], + [ + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_2" + ], + [ + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_2" + ], + [ + "INT_INTERFACE_FAN6", + "PCIE_FAN6_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT19", + "PCIE_IMUX19_R_2" + ], + [ + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_2" + ], + [ + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_2" + ], + [ + "INT_INTERFACE_EE2A3", + "PCIE_EE2A3_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT35", + "PCIE_IMUX35_R_2" + ], + [ + "INT_INTERFACE_EE4A3", + "PCIE_EE4A3_2" + ], + [ + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT28", + "PCIE_IMUX28_R_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B11", + "PCIE_LOGIC_OUTS_B11_R_2" + ], + [ + "INT_INTERFACE_LH8", + "PCIE_LH8_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT34", + "PCIE_IMUX34_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT9", + "PCIE_IMUX9_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT23", + "PCIE_IMUX23_R_2" + ], + [ + "INT_INTERFACE_EE2BEG1", + "PCIE_EE2BEG1_2" + ], + [ + "INT_INTERFACE_CLK1", + "PCIE_CLK1_R_2" + ], + [ + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_2" + ], + [ + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B9", + "PCIE_LOGIC_OUTS_B9_R_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B6", + "PCIE_LOGIC_OUTS_B6_R_2" + ], + [ + "INT_INTERFACE_BYP6", + "PCIE_BYP6_R_2" + ], + [ + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_2" + ], + [ + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT8", + "PCIE_IMUX8_R_2" + ], + [ + "INT_INTERFACE_EE2BEG3", + "PCIE_EE2BEG3_2" + ], + [ + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_2" + ], + [ + "INT_INTERFACE_BYP0", + "PCIE_BYP0_R_2" + ], + [ + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B10", + "PCIE_LOGIC_OUTS_B10_R_2" + ], + [ + "INT_INTERFACE_CLK0", + "PCIE_CLK0_R_2" + ], + [ + "INT_INTERFACE_EE4B0", + "PCIE_EE4B0_2" + ], + [ + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT17", + "PCIE_IMUX17_R_2" + ], + [ + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_2" + ], + [ + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT33", + "PCIE_IMUX33_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT26", + "PCIE_IMUX26_R_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B23", + "PCIE_LOGIC_OUTS_B23_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT42", + "PCIE_IMUX42_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT13", + "PCIE_IMUX13_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT46", + "PCIE_IMUX46_R_2" + ], + [ + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_2" + ], + [ + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B13", + "PCIE_LOGIC_OUTS_B13_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT24", + "PCIE_IMUX24_R_2" + ], + [ + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_2" + ], + [ + "INT_INTERFACE_ER1BEG0", + "PCIE_ER1BEG0_2" + ], + [ + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_2" + ], + [ + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT47", + "PCIE_IMUX47_R_2" + ], + [ + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_2" + ], + [ + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_2" + ], + [ + "INT_INTERFACE_LH1", + "PCIE_LH1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT30", + "PCIE_IMUX30_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT45", + "PCIE_IMUX45_R_2" + ], + [ + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B3", + "PCIE_LOGIC_OUTS_B3_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT29", + "PCIE_IMUX29_R_2" + ], + [ + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_2" + ], + [ + "INT_INTERFACE_BYP2", + "PCIE_BYP2_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT10", + "PCIE_IMUX10_R_2" + ], + [ + "INT_INTERFACE_EE4A0", + "PCIE_EE4A0_2" + ], + [ + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_2" + ], + [ + "INT_INTERFACE_BYP7", + "PCIE_BYP7_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT0", + "PCIE_IMUX0_R_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B22", + "PCIE_LOGIC_OUTS_B22_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT6", + "PCIE_IMUX6_R_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B15", + "PCIE_LOGIC_OUTS_B15_R_2" + ], + [ + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_2" + ], + [ + "INT_INTERFACE_EE4C1", + "PCIE_EE4C1_2" + ], + [ + "INT_INTERFACE_BYP5", + "PCIE_BYP5_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT36", + "PCIE_IMUX36_R_2" + ], + [ + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_2" + ], + [ + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_2" + ], + [ + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_2" + ], + [ + "INT_INTERFACE_LH10", + "PCIE_LH10_2" + ], + [ + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B12", + "PCIE_LOGIC_OUTS_B12_R_2" + ], + [ + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_2" + ], + [ + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_2" + ], + [ + "INT_INTERFACE_EL1BEG3", + "PCIE_EL1BEG3_2" + ], + [ + "INT_INTERFACE_BYP1", + "PCIE_BYP1_R_2" + ], + [ + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_2" + ], + [ + "INT_INTERFACE_LH6", + "PCIE_LH6_2" + ], + [ + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_2" + ], + [ + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT14", + "PCIE_IMUX14_R_2" + ], + [ + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_2" + ], + [ + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_2" + ], + [ + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_2" + ], + [ + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_2" + ], + [ + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_2" + ], + [ + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT11", + "PCIE_IMUX11_R_2" + ], + [ + "INT_INTERFACE_FAN0", + "PCIE_FAN0_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT43", + "PCIE_IMUX43_R_2" + ], + [ + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT39", + "PCIE_IMUX39_R_2" + ], + [ + "INT_INTERFACE_CTRL0", + "PCIE_CTRL0_R_2" + ], + [ + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_2" + ], + [ + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_2" + ], + [ + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_2" + ], + [ + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_2" + ], + [ + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_2" + ], + [ + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT44", + "PCIE_IMUX44_R_2" + ], + [ + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_2" + ], + [ + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT1", + "PCIE_IMUX1_R_2" + ], + [ + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_2" + ], + [ + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_2" + ], + [ + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_2" + ], + [ + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B2", + "PCIE_LOGIC_OUTS_B2_R_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B7", + "PCIE_LOGIC_OUTS_B7_R_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B20", + "PCIE_LOGIC_OUTS_B20_R_2" + ], + [ + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_2" + ], + [ + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT16", + "PCIE_IMUX16_R_2" + ], + [ + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_2" + ], + [ + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_2" + ], + [ + "INT_INTERFACE_CTRL1", + "PCIE_CTRL1_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT2", + "PCIE_IMUX2_R_2" + ], + [ + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_2" + ], + [ + "INT_INTERFACE_LH12", + "PCIE_LH12_2" + ], + [ + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT41", + "PCIE_IMUX41_R_2" + ], + [ + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_2" + ], + [ + "INT_INTERFACE_FAN3", + "PCIE_FAN3_R_2" + ], + [ + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B0", + "PCIE_LOGIC_OUTS_B0_R_2" + ], + [ + "INT_INTERFACE_LH7", + "PCIE_LH7_2" + ], + [ + "INT_INTERFACE_FAN4", + "PCIE_FAN4_R_2" + ], + [ + "INT_INTERFACE_BYP3", + "PCIE_BYP3_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT22", + "PCIE_IMUX22_R_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B18", + "PCIE_LOGIC_OUTS_B18_R_2" + ], + [ + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_2" + ], + [ + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_2" + ], + [ + "INT_INTERFACE_FAN2", + "PCIE_FAN2_R_2" + ], + [ + "INT_INTERFACE_EE2A2", + "PCIE_EE2A2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT7", + "PCIE_IMUX7_R_2" + ], + [ + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_2" + ], + [ + "INT_INTERFACE_LH9", + "PCIE_LH9_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT15", + "PCIE_IMUX15_R_2" + ], + [ + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_2" + ], + [ + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT20", + "PCIE_IMUX20_R_2" + ], + [ + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B1", + "PCIE_LOGIC_OUTS_B1_R_2" + ], + [ + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_2" + ], + [ + "INT_INTERFACE_LH11", + "PCIE_LH11_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B8", + "PCIE_LOGIC_OUTS_B8_R_2" + ], + [ + "INT_INTERFACE_EE2A1", + "PCIE_EE2A1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT40", + "PCIE_IMUX40_R_2" + ], + [ + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT37", + "PCIE_IMUX37_R_2" + ], + [ + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_2" + ], + [ + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT4", + "PCIE_IMUX4_R_2" + ], + [ + "INT_INTERFACE_FAN1", + "PCIE_FAN1_R_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B14", + "PCIE_LOGIC_OUTS_B14_R_2" + ], + [ + "INT_INTERFACE_LH4", + "PCIE_LH4_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B5", + "PCIE_LOGIC_OUTS_B5_R_2" + ], + [ + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_2" + ], + [ + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_2" + ], + [ + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_2" + ], + [ + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B16", + "PCIE_LOGIC_OUTS_B16_R_2" + ], + [ + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_2" + ], + [ + "INT_INTERFACE_EE2BEG0", + "PCIE_EE2BEG0_2" + ], + [ + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_2" + ], + [ + "INT_INTERFACE_EE4C0", + "PCIE_EE4C0_2" + ], + [ + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_2" + ], + [ + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_2" + ], + [ + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_2" + ], + [ + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_2" + ], + [ + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_2" + ], + [ + "INT_INTERFACE_LH5", + "PCIE_LH5_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B4", + "PCIE_LOGIC_OUTS_B4_R_2" + ], + [ + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B19", + "PCIE_LOGIC_OUTS_B19_R_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT3", + "PCIE_IMUX3_R_2" + ], + [ + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_2" + ], + [ + "INT_INTERFACE_EE2A0", + "PCIE_EE2A0_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT32", + "PCIE_IMUX32_R_2" + ], + [ + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_2" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT5", + "PCIE_IMUX5_R_2" + ], + [ + "INT_INTERFACE_EE2BEG2", + "PCIE_EE2BEG2_2" + ], + [ + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_2" + ] + ], + "tile_types": [ + "PCIE_INT_INTERFACE_R", + "PCIE_TOP" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "MONITOR_EL1BEG1_3", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_EE4A0_3", + "VFRAME_EE4A0" + ], + [ + "MONITOR_SW2A0_3", + "VFRAME_SW2A0" + ], + [ + "MONITOR_WL1END2_3", + "VFRAME_WL1END2" + ], + [ + "MONITOR_EE2BEG1_3", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_BYP5_3", + "VFRAME_BYP5" + ], + [ + "MONITOR_NW4A0_3", + "VFRAME_NW4A0" + ], + [ + "MONITOR_WL1END3_3", + "VFRAME_WL1END3" + ], + [ + "MONITOR_IMUX8_3", + "VFRAME_IMUX8" + ], + [ + "MONITOR_FAN6_3", + "VFRAME_FAN6" + ], + [ + "MONITOR_CLK1_3", + "VFRAME_CLK1" + ], + [ + "MONITOR_IMUX23_3", + "VFRAME_IMUX23" + ], + [ + "MONITOR_EE4BEG2_3", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_SE4C3_3", + "VFRAME_SE4C3" + ], + [ + "MONITOR_IMUX35_3", + "VFRAME_IMUX35" + ], + [ + "MONITOR_FAN2_3", + "VFRAME_FAN2" + ], + [ + "MONITOR_NE4BEG0_3", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_WW4C1_3", + "VFRAME_WW4C1" + ], + [ + "MONITOR_IMUX29_3", + "VFRAME_IMUX29" + ], + [ + "MONITOR_IMUX28_3", + "VFRAME_IMUX28" + ], + [ + "MONITOR_IMUX0_3", + "VFRAME_IMUX0" + ], + [ + "MONITOR_LH9_3", + "VFRAME_LH9" + ], + [ + "MONITOR_SW4END2_3", + "VFRAME_SW4END2" + ], + [ + "MONITOR_IMUX16_3", + "VFRAME_IMUX16" + ], + [ + "MONITOR_SW4A3_3", + "VFRAME_SW4A3" + ], + [ + "MONITOR_LH1_3", + "VFRAME_LH1" + ], + [ + "MONITOR_EE4B0_3", + "VFRAME_EE4B0" + ], + [ + "MONITOR_IMUX44_3", + "VFRAME_IMUX44" + ], + [ + "MONITOR_FAN4_3", + "VFRAME_FAN4" + ], + [ + "MONITOR_IMUX45_3", + "VFRAME_IMUX45" + ], + [ + "MONITOR_IMUX18_3", + "VFRAME_IMUX18" + ], + [ + "MONITOR_IMUX2_3", + "VFRAME_IMUX2" + ], + [ + "MONITOR_IMUX6_3", + "VFRAME_IMUX6" + ], + [ + "MONITOR_IMUX30_3", + "VFRAME_IMUX30" + ], + [ + "MONITOR_IMUX22_3", + "VFRAME_IMUX22" + ], + [ + "MONITOR_FAN1_3", + "VFRAME_FAN1" + ], + [ + "MONITOR_NE4BEG3_3", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_ER1BEG0_3", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_EE4B2_3", + "VFRAME_EE4B2" + ], + [ + "MONITOR_SW2A1_3", + "VFRAME_SW2A1" + ], + [ + "MONITOR_LH5_3", + "VFRAME_LH5" + ], + [ + "MONITOR_IMUX7_3", + "VFRAME_IMUX7" + ], + [ + "MONITOR_WR1END3_3", + "VFRAME_WR1END3" + ], + [ + "MONITOR_BYP4_3", + "VFRAME_BYP4" + ], + [ + "MONITOR_WW4A2_3", + "VFRAME_WW4A2" + ], + [ + "MONITOR_SE2A0_3", + "VFRAME_SE2A0" + ], + [ + "MONITOR_SW4END1_3", + "VFRAME_SW4END1" + ], + [ + "MONITOR_IMUX33_3", + "VFRAME_IMUX33" + ], + [ + "MONITOR_WW4A0_3", + "VFRAME_WW4A0" + ], + [ + "MONITOR_WW2END3_3", + "VFRAME_WW2END3" + ], + [ + "MONITOR_IMUX10_3", + "VFRAME_IMUX10" + ], + [ + "MONITOR_WW2A0_3", + "VFRAME_WW2A0" + ], + [ + "MONITOR_BYP3_3", + "VFRAME_BYP3" + ], + [ + "MONITOR_IMUX39_3", + "VFRAME_IMUX39" + ], + [ + "MONITOR_EL1BEG2_3", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_EE2A0_3", + "VFRAME_EE2A0" + ], + [ + "MONITOR_IMUX24_3", + "VFRAME_IMUX24" + ], + [ + "MONITOR_NE2A0_3", + "VFRAME_NE2A0" + ], + [ + "MONITOR_IMUX5_3", + "VFRAME_IMUX5" + ], + [ + "MONITOR_NE4C3_3", + "VFRAME_NE4C3" + ], + [ + "MONITOR_SE2A2_3", + "VFRAME_SE2A2" + ], + [ + "MONITOR_IMUX46_3", + "VFRAME_IMUX46" + ], + [ + "MONITOR_NW2A1_3", + "VFRAME_NW2A1" + ], + [ + "MONITOR_IMUX37_3", + "VFRAME_IMUX37" + ], + [ + "MONITOR_NW4A3_3", + "VFRAME_NW4A3" + ], + [ + "MONITOR_SW4A0_3", + "VFRAME_SW4A0" + ], + [ + "MONITOR_WW4END1_3", + "VFRAME_WW4END1" + ], + [ + "MONITOR_FAN0_3", + "VFRAME_FAN0" + ], + [ + "MONITOR_SE2A3_3", + "VFRAME_SE2A3" + ], + [ + "MONITOR_SW4A2_3", + "VFRAME_SW4A2" + ], + [ + "MONITOR_WW4B1_3", + "VFRAME_WW4B1" + ], + [ + "MONITOR_NE2A3_3", + "VFRAME_NE2A3" + ], + [ + "MONITOR_IMUX26_3", + "VFRAME_IMUX26" + ], + [ + "MONITOR_IMUX31_3", + "VFRAME_IMUX31" + ], + [ + "MONITOR_NE4C2_3", + "VFRAME_NE4C2" + ], + [ + "MONITOR_NE4BEG1_3", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_NW2A3_3", + "VFRAME_NW2A3" + ], + [ + "MONITOR_BYP1_3", + "VFRAME_BYP1" + ], + [ + "MONITOR_CLK0_3", + "VFRAME_CLK0" + ], + [ + "MONITOR_IMUX12_3", + "VFRAME_IMUX12" + ], + [ + "MONITOR_WW4A1_3", + "VFRAME_WW4A1" + ], + [ + "MONITOR_LH10_3", + "VFRAME_LH10" + ], + [ + "MONITOR_WW2END2_3", + "VFRAME_WW2END2" + ], + [ + "MONITOR_WW2END0_3", + "VFRAME_WW2END0" + ], + [ + "MONITOR_NE4C1_3", + "VFRAME_NE4C1" + ], + [ + "MONITOR_NE4BEG2_3", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_EE4B3_3", + "VFRAME_EE4B3" + ], + [ + "MONITOR_FAN5_3", + "VFRAME_FAN5" + ], + [ + "MONITOR_IMUX17_3", + "VFRAME_IMUX17" + ], + [ + "MONITOR_NE4C0_3", + "VFRAME_NE4C0" + ], + [ + "MONITOR_NW4END1_3", + "VFRAME_NW4END1" + ], + [ + "MONITOR_CTRL0_3", + "VFRAME_CTRL0" + ], + [ + "MONITOR_NW2A0_3", + "VFRAME_NW2A0" + ], + [ + "MONITOR_IMUX25_3", + "VFRAME_IMUX25" + ], + [ + "MONITOR_LH2_3", + "VFRAME_LH2" + ], + [ + "MONITOR_IMUX1_3", + "VFRAME_IMUX1" + ], + [ + "MONITOR_LH11_3", + "VFRAME_LH11" + ], + [ + "MONITOR_NW4END0_3", + "VFRAME_NW4END0" + ], + [ + "MONITOR_IMUX40_3", + "VFRAME_IMUX40" + ], + [ + "MONITOR_ER1BEG2_3", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_IMUX3_3", + "VFRAME_IMUX3" + ], + [ + "MONITOR_NE2A1_3", + "VFRAME_NE2A1" + ], + [ + "MONITOR_SE4BEG1_3", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_BYP7_3", + "VFRAME_BYP7" + ], + [ + "MONITOR_EE4A1_3", + "VFRAME_EE4A1" + ], + [ + "MONITOR_SW2A3_3", + "VFRAME_SW2A3" + ], + [ + "MONITOR_IMUX38_3", + "VFRAME_IMUX38" + ], + [ + "MONITOR_NW4END3_3", + "VFRAME_NW4END3" + ], + [ + "MONITOR_SW4END0_3", + "VFRAME_SW4END0" + ], + [ + "MONITOR_WW4END0_3", + "VFRAME_WW4END0" + ], + [ + "MONITOR_SW4END3_3", + "VFRAME_SW4END3" + ], + [ + "MONITOR_FAN7_3", + "VFRAME_FAN7" + ], + [ + "MONITOR_ER1BEG3_3", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_SE4C0_3", + "VFRAME_SE4C0" + ], + [ + "MONITOR_WW2A3_3", + "VFRAME_WW2A3" + ], + [ + "MONITOR_EL1BEG3_3", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_IMUX32_3", + "VFRAME_IMUX32" + ], + [ + "MONITOR_EE2A2_3", + "VFRAME_EE2A2" + ], + [ + "MONITOR_NW2A2_3", + "VFRAME_NW2A2" + ], + [ + "MONITOR_SE4BEG3_3", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_EE4A2_3", + "VFRAME_EE4A2" + ], + [ + "MONITOR_NE2A2_3", + "VFRAME_NE2A2" + ], + [ + "MONITOR_IMUX19_3", + "VFRAME_IMUX19" + ], + [ + "MONITOR_IMUX11_3", + "VFRAME_IMUX11" + ], + [ + "MONITOR_IMUX20_3", + "VFRAME_IMUX20" + ], + [ + "MONITOR_IMUX42_3", + "VFRAME_IMUX42" + ], + [ + "MONITOR_WW4B2_3", + "VFRAME_WW4B2" + ], + [ + "MONITOR_IMUX9_3", + "VFRAME_IMUX9" + ], + [ + "MONITOR_SW2A2_3", + "VFRAME_SW2A2" + ], + [ + "MONITOR_LH4_3", + "VFRAME_LH4" + ], + [ + "MONITOR_SE4C1_3", + "VFRAME_SE4C1" + ], + [ + "MONITOR_WW4END2_3", + "VFRAME_WW4END2" + ], + [ + "MONITOR_CTRL1_3", + "VFRAME_CTRL1" + ], + [ + "MONITOR_WW4A3_3", + "VFRAME_WW4A3" + ], + [ + "MONITOR_BYP0_3", + "VFRAME_BYP0" + ], + [ + "MONITOR_EE4BEG1_3", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX15_3", + "VFRAME_IMUX15" + ], + [ + "MONITOR_FAN3_3", + "VFRAME_FAN3" + ], + [ + "MONITOR_WW4C0_3", + "VFRAME_WW4C0" + ], + [ + "MONITOR_WL1END0_3", + "VFRAME_WL1END0" + ], + [ + "MONITOR_WW2END1_3", + "VFRAME_WW2END1" + ], + [ + "MONITOR_WW2A2_3", + "VFRAME_WW2A2" + ], + [ + "MONITOR_EE2A3_3", + "VFRAME_EE2A3" + ], + [ + "MONITOR_IMUX27_3", + "VFRAME_IMUX27" + ], + [ + "MONITOR_WR1END2_3", + "VFRAME_WR1END2" + ], + [ + "MONITOR_EL1BEG0_3", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_WW4C2_3", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE2BEG3_3", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_BYP2_3", + "VFRAME_BYP2" + ], + [ + "MONITOR_EE2BEG2_3", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_WW4B0_3", + "VFRAME_WW4B0" + ], + [ + "MONITOR_SE2A1_3", + "VFRAME_SE2A1" + ], + [ + "MONITOR_IMUX36_3", + "VFRAME_IMUX36" + ], + [ + "MONITOR_SE4BEG2_3", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_IMUX34_3", + "VFRAME_IMUX34" + ], + [ + "MONITOR_WR1END0_3", + "VFRAME_WR1END0" + ], + [ + "MONITOR_ER1BEG1_3", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_BYP6_3", + "VFRAME_BYP6" + ], + [ + "MONITOR_NW4END2_3", + "VFRAME_NW4END2" + ], + [ + "MONITOR_WL1END1_3", + "VFRAME_WL1END1" + ], + [ + "MONITOR_SE4C2_3", + "VFRAME_SE4C2" + ], + [ + "MONITOR_EE4BEG0_3", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_LH7_3", + "VFRAME_LH7" + ], + [ + "MONITOR_LH12_3", + "VFRAME_LH12" + ], + [ + "MONITOR_SW4A1_3", + "VFRAME_SW4A1" + ], + [ + "MONITOR_NW4A1_3", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WW4B3_3", + "VFRAME_WW4B3" + ], + [ + "MONITOR_WR1END1_3", + "VFRAME_WR1END1" + ], + [ + "MONITOR_EE4BEG3_3", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_IMUX47_3", + "VFRAME_IMUX47" + ], + [ + "MONITOR_EE2A1_3", + "VFRAME_EE2A1" + ], + [ + "MONITOR_LH8_3", + "VFRAME_LH8" + ], + [ + "MONITOR_WW4C3_3", + "VFRAME_WW4C3" + ], + [ + "MONITOR_WW4END3_3", + "VFRAME_WW4END3" + ], + [ + "MONITOR_EE4B1_3", + "VFRAME_EE4B1" + ], + [ + "MONITOR_LH3_3", + "VFRAME_LH3" + ], + [ + "MONITOR_LH6_3", + "VFRAME_LH6" + ], + [ + "MONITOR_EE4C3_3", + "VFRAME_EE4C3" + ], + [ + "MONITOR_EE4C1_3", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX21_3", + "VFRAME_IMUX21" + ], + [ + "MONITOR_EE4A3_3", + "VFRAME_EE4A3" + ], + [ + "MONITOR_EE4C0_3", + "VFRAME_EE4C0" + ], + [ + "MONITOR_IMUX14_3", + "VFRAME_IMUX14" + ], + [ + "MONITOR_EE2BEG0_3", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_IMUX4_3", + "VFRAME_IMUX4" + ], + [ + "MONITOR_IMUX43_3", + "VFRAME_IMUX43" + ], + [ + "MONITOR_EE4C2_3", + "VFRAME_EE4C2" + ], + [ + "MONITOR_IMUX13_3", + "VFRAME_IMUX13" + ], + [ + "MONITOR_SE4BEG0_3", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_NW4A2_3", + "VFRAME_NW4A2" + ], + [ + "MONITOR_IMUX41_3", + "VFRAME_IMUX41" + ], + [ + "MONITOR_WW2A1_3", + "VFRAME_WW2A1" + ] + ], + "tile_types": [ + "MONITOR_MID_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "CLBLM_NW2A3", + "DSP_NW2A3_3" + ], + [ + "CLBLM_SE2A2", + "DSP_SE2A2_3" + ], + [ + "CLBLM_NE4BEG2", + "DSP_NE4BEG2_3" + ], + [ + "CLBLM_WW4C2", + "DSP_WW4C2_3" + ], + [ + "CLBLM_NE2A2", + "DSP_NE2A2_3" + ], + [ + "CLBLM_ER1BEG0", + "DSP_ER1BEG0_3" + ], + [ + "CLBLM_LH9", + "DSP_LH9_3" + ], + [ + "CLBLM_NW2A1", + "DSP_NW2A1_3" + ], + [ + "CLBLM_LH12", + "DSP_LH12_3" + ], + [ + "CLBLM_SW4END0", + "DSP_SW4END0_3" + ], + [ + "CLBLM_SE4BEG0", + "DSP_SE4BEG0_3" + ], + [ + "CLBLM_SW4END3", + "DSP_SW4END3_3" + ], + [ + "CLBLM_LH8", + "DSP_LH8_3" + ], + [ + "CLBLM_SE4C0", + "DSP_SE4C0_3" + ], + [ + "CLBLM_EE4C0", + "DSP_EE4C0_3" + ], + [ + "CLBLM_EE4B0", + "DSP_EE4B0_3" + ], + [ + "CLBLM_WW4END0", + "DSP_WW4END0_3" + ], + [ + "CLBLM_WL1END3", + "DSP_WL1END3_3" + ], + [ + "CLBLM_EE4B1", + "DSP_EE4B1_3" + ], + [ + "CLBLM_WW2END2", + "DSP_WW2END2_3" + ], + [ + "CLBLM_EE2BEG3", + "DSP_EE2BEG3_3" + ], + [ + "CLBLM_LH10", + "DSP_LH10_3" + ], + [ + "CLBLM_NW4A2", + "DSP_NW4A2_3" + ], + [ + "CLBLM_EL1BEG3", + "DSP_EL1BEG3_3" + ], + [ + "CLBLM_MONITOR_P", + "DSP_MONITOR_P_3" + ], + [ + "CLBLM_WW2A1", + "DSP_WW2A1_3" + ], + [ + "CLBLM_LH6", + "DSP_LH6_3" + ], + [ + "CLBLM_EE4A1", + "DSP_EE4A1_3" + ], + [ + "CLBLM_WW2A3", + "DSP_WW2A3_3" + ], + [ + "CLBLM_EE4B3", + "DSP_EE4B3_3" + ], + [ + "CLBLM_SE4C2", + "DSP_SE4C2_3" + ], + [ + "CLBLM_WW4END3", + "DSP_WW4END3_3" + ], + [ + "CLBLM_NW4A0", + "DSP_NW4A0_3" + ], + [ + "CLBLM_EE2A1", + "DSP_EE2A1_3" + ], + [ + "CLBLM_SW4A2", + "DSP_SW4A2_3" + ], + [ + "CLBLM_EL1BEG1", + "DSP_EL1BEG1_3" + ], + [ + "CLBLM_EE4BEG3", + "DSP_EE4BEG3_3" + ], + [ + "CLBLM_NW4END0", + "DSP_NW4END0_3" + ], + [ + "CLBLM_NE4C1", + "DSP_NE4C1_3" + ], + [ + "CLBLM_WW4C1", + "DSP_WW4C1_3" + ], + [ + "CLBLM_EE4C2", + "DSP_EE4C2_3" + ], + [ + "CLBLM_ER1BEG3", + "DSP_ER1BEG3_3" + ], + [ + "CLBLM_LH2", + "DSP_LH2_3" + ], + [ + "CLBLM_SW2A1", + "DSP_SW2A1_3" + ], + [ + "CLBLM_WW2A0", + "DSP_WW2A0_3" + ], + [ + "CLBLM_LH7", + "DSP_LH7_3" + ], + [ + "CLBLM_WW2A2", + "DSP_WW2A2_3" + ], + [ + "CLBLM_WR1END3", + "DSP_WR1END3_3" + ], + [ + "CLBLM_SW2A0", + "DSP_SW2A0_3" + ], + [ + "CLBLM_EE4BEG1", + "DSP_EE4BEG1_3" + ], + [ + "CLBLM_WW4A3", + "DSP_WW4A3_3" + ], + [ + "CLBLM_NE4BEG3", + "DSP_NE4BEG3_3" + ], + [ + "CLBLM_NW4A1", + "DSP_NW4A1_3" + ], + [ + "CLBLM_NW4END2", + "DSP_NW4END2_3" + ], + [ + "CLBLM_LH3", + "DSP_LH3_3" + ], + [ + "CLBLM_WL1END0", + "DSP_WL1END0_3" + ], + [ + "CLBLM_SE2A0", + "DSP_SE2A0_3" + ], + [ + "CLBLM_EE4BEG0", + "DSP_EE4BEG0_3" + ], + [ + "CLBLM_WW4B1", + "DSP_WW4B1_3" + ], + [ + "CLBLM_EE4A3", + "DSP_EE4A3_3" + ], + [ + "CLBLM_EL1BEG0", + "DSP_EL1BEG0_3" + ], + [ + "CLBLM_WW4B0", + "DSP_WW4B0_3" + ], + [ + "CLBLM_WW4B2", + "DSP_WW4B2_3" + ], + [ + "CLBLM_WW2END0", + "DSP_WW2END0_3" + ], + [ + "CLBLM_WW4END1", + "DSP_WW4END1_3" + ], + [ + "CLBLM_SW4END1", + "DSP_SW4END1_3" + ], + [ + "CLBLM_WW4A1", + "DSP_WW4A1_3" + ], + [ + "CLBLM_WW4A0", + "DSP_WW4A0_3" + ], + [ + "CLBLM_WW4C3", + "DSP_WW4C3_3" + ], + [ + "CLBLM_WR1END0", + "DSP_WR1END0_3" + ], + [ + "CLBLM_NE4C3", + "DSP_NE4C3_3" + ], + [ + "CLBLM_WW4END2", + "DSP_WW4END2_3" + ], + [ + "CLBLM_WW2END1", + "DSP_WW2END1_3" + ], + [ + "CLBLM_WW2END3", + "DSP_WW2END3_3" + ], + [ + "CLBLM_EE4A0", + "DSP_EE4A0_3" + ], + [ + "CLBLM_SE4BEG3", + "DSP_SE4BEG3_3" + ], + [ + "CLBLM_SW4A3", + "DSP_SW4A3_3" + ], + [ + "CLBLM_LH1", + "DSP_LH1_3" + ], + [ + "CLBLM_EE4B2", + "DSP_EE4B2_3" + ], + [ + "CLBLM_SW4END2", + "DSP_SW4END2_3" + ], + [ + "CLBLM_LH4", + "DSP_LH4_3" + ], + [ + "CLBLM_WR1END2", + "DSP_WR1END2_3" + ], + [ + "CLBLM_LH5", + "DSP_LH5_3" + ], + [ + "CLBLM_NW4END3", + "DSP_NW4END3_3" + ], + [ + "CLBLM_SE4BEG2", + "DSP_SE4BEG2_3" + ], + [ + "CLBLM_NE2A1", + "DSP_NE2A1_3" + ], + [ + "CLBLM_LH11", + "DSP_LH11_3" + ], + [ + "CLBLM_NW2A0", + "DSP_NW2A0_3" + ], + [ + "CLBLM_EE4C3", + "DSP_EE4C3_3" + ], + [ + "CLBLM_EE4BEG2", + "DSP_EE4BEG2_3" + ], + [ + "CLBLM_WW4B3", + "DSP_WW4B3_3" + ], + [ + "CLBLM_EE2BEG1", + "DSP_EE2BEG1_3" + ], + [ + "CLBLM_NE2A0", + "DSP_NE2A0_3" + ], + [ + "CLBLM_EL1BEG2", + "DSP_EL1BEG2_3" + ], + [ + "CLBLM_WR1END1", + "DSP_WR1END1_3" + ], + [ + "CLBLM_NW2A2", + "DSP_NW2A2_3" + ], + [ + "CLBLM_SE4C3", + "DSP_SE4C3_3" + ], + [ + "CLBLM_EE2A0", + "DSP_EE2A0_3" + ], + [ + "CLBLM_NE4BEG0", + "DSP_NE4BEG0_3" + ], + [ + "CLBLM_EE2BEG2", + "DSP_EE2BEG2_3" + ], + [ + "CLBLM_SE2A3", + "DSP_SE2A3_3" + ], + [ + "CLBLM_MONITOR_N", + "DSP_MONITOR_N_3" + ], + [ + "CLBLM_ER1BEG2", + "DSP_ER1BEG2_3" + ], + [ + "CLBLM_NE4BEG1", + "DSP_NE4BEG1_3" + ], + [ + "CLBLM_SW4A1", + "DSP_SW4A1_3" + ], + [ + "CLBLM_WW4A2", + "DSP_WW4A2_3" + ], + [ + "CLBLM_EE2A3", + "DSP_EE2A3_3" + ], + [ + "CLBLM_WL1END2", + "DSP_WL1END2_3" + ], + [ + "CLBLM_NW4A3", + "DSP_NW4A3_3" + ], + [ + "CLBLM_ER1BEG1", + "DSP_ER1BEG1_3" + ], + [ + "CLBLM_SW4A0", + "DSP_SW4A0_3" + ], + [ + "CLBLM_NE4C0", + "DSP_NE4C0_3" + ], + [ + "CLBLM_EE4C1", + "DSP_EE4C1_3" + ], + [ + "CLBLM_SE4C1", + "DSP_SE4C1_3" + ], + [ + "CLBLM_EE2BEG0", + "DSP_EE2BEG0_3" + ], + [ + "CLBLM_EE4A2", + "DSP_EE4A2_3" + ], + [ + "CLBLM_WL1END1", + "DSP_WL1END1_3" + ], + [ + "CLBLM_NE2A3", + "DSP_NE2A3_3" + ], + [ + "CLBLM_SW2A2", + "DSP_SW2A2_3" + ], + [ + "CLBLM_SE4BEG1", + "DSP_SE4BEG1_3" + ], + [ + "CLBLM_NW4END1", + "DSP_NW4END1_3" + ], + [ + "CLBLM_SE2A1", + "DSP_SE2A1_3" + ], + [ + "CLBLM_SW2A3", + "DSP_SW2A3_3" + ], + [ + "CLBLM_EE2A2", + "DSP_EE2A2_3" + ], + [ + "CLBLM_WW4C0", + "DSP_WW4C0_3" + ], + [ + "CLBLM_NE4C2", + "DSP_NE4C2_3" + ] + ], + "tile_types": [ + "CLBLM_L", + "DSP_R" + ] + }, + { + "grid_deltas": [ + 0, + -9 + ], + "wire_pairs": [ + [ + "BRKH_CMT_FREQ_REF_NS2", + "MMCM_CLK_FREQ_BB_REBUF2_NS" + ], + [ + "BRKH_CMT_FREQ_REF_NS0", + "MMCM_CLK_FREQ_BB_REBUF0_NS" + ], + [ + "BRKH_CMT_FREQ_REF_NS1", + "MMCM_CLK_FREQ_BB_REBUF1_NS" + ], + [ + "BRKH_CMT_PHASEREF_BELOW0", + "CMT_MMCM_PHASERREF_BELOW0" + ], + [ + "BRKH_CMT_PHASEREF1", + "CMT_MMCM_PHASERREF1" + ], + [ + "BRKH_CMT_PHYCTRL_SYNC_BB", + "CMT_MMCM_PHYCTRL_SYNC_BB_DN" + ], + [ + "BRKH_CMT_PHASEREF_BELOW1", + "CMT_MMCM_PHASERREF_BELOW1" + ], + [ + "BRKH_CMT_FREQ_REF_NS3", + "MMCM_CLK_FREQ_BB_REBUF3_NS" + ], + [ + "BRKH_CMT_PHASEREF0", + "CMT_MMCM_PHASERREF0" + ] + ], + "tile_types": [ + "BRKH_CMT", + "CMT_TOP_R_LOWER_B" + ] + }, + { + "grid_deltas": [ + 1, + 6 + ], + "wire_pairs": [ + [ + "CMT_TOP_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH1_2", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH2_2", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_LH6_2", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH7_2", + "VBRK_LH7" + ], + [ + "CMT_TOP_LH12_2", + "VBRK_LH12" + ], + [ + "CMT_TOP_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_LH11_2", + "VBRK_LH11" + ], + [ + "CMT_TOP_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4B3_2", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_LH4_2", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_LH5_2", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH3_2", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH10_2", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH8_2", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_LH9_2", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW2A2_2", + "VBRK_NW2A2" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 5 + ], + "wire_pairs": [ + [ + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "BRAM_CASCOUT_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "BRAM_CASCOUT_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "BRAM_CASCOUT_ADDRBWRADDRU9" + ], + [ + "BRAM_FIFO36_CASCADEINA", + "BRAM_FIFO36_CASCADEOUTA_1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU3", + "BRAM_CASCOUT_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU14", + "BRAM_CASCOUT_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "BRAM_CASCOUT_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU7", + "BRAM_CASCOUT_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "BRAM_CASCOUT_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU2", + "BRAM_CASCOUT_ADDRARDADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU5", + "BRAM_CASCOUT_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "BRAM_CASCOUT_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "BRAM_CASCOUT_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "BRAM_CASCOUT_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU1", + "BRAM_CASCOUT_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU6", + "BRAM_CASCOUT_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "BRAM_CASCOUT_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "BRAM_CASCOUT_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "BRAM_CASCOUT_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "BRAM_CASCOUT_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU9", + "BRAM_CASCOUT_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU4", + "BRAM_CASCOUT_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "BRAM_CASCOUT_ADDRBWRADDRU12" + ], + [ + "BRAM_FIFO36_CASCADEINB", + "BRAM_FIFO36_CASCADEOUTB_1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU12", + "BRAM_CASCOUT_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU8", + "BRAM_CASCOUT_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU13", + "BRAM_CASCOUT_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "BRAM_CASCOUT_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU10", + "BRAM_CASCOUT_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU0", + "BRAM_CASCOUT_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "BRAM_CASCOUT_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU11", + "BRAM_CASCOUT_ADDRARDADDRU11" + ] + ], + "tile_types": [ + "BRAM_R", + "BRAM_R" + ] + }, + { + "grid_deltas": [ + -5, + 3 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_3" + ], + [ + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_3" + ], + [ + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT39", + "PCIE_IMUX39_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT28", + "PCIE_IMUX28_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT31", + "PCIE_IMUX31_L_3" + ], + [ + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_3" + ], + [ + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_3" + ], + [ + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "PCIE_LOGIC_OUTS_B14_L_3" + ], + [ + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_3" + ], + [ + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_3" + ], + [ + "INT_INTERFACE_EE4A2", + "PCIE_EE4A2_3" + ], + [ + "INT_INTERFACE_CLK0", + "PCIE_CLK0_L_3" + ], + [ + "INT_INTERFACE_BYP6", + "PCIE_BYP6_L_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "PCIE_LOGIC_OUTS_B23_L_3" + ], + [ + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_3" + ], + [ + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_3" + ], + [ + "INT_INTERFACE_FAN1", + "PCIE_FAN1_L_3" + ], + [ + "INT_INTERFACE_BYP0", + "PCIE_BYP0_L_3" + ], + [ + "INT_INTERFACE_EE2A2", + "PCIE_EE2A2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT8", + "PCIE_IMUX8_L_3" + ], + [ + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_3" + ], + [ + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_3" + ], + [ + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_3" + ], + [ + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_3" + ], + [ + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT10", + "PCIE_IMUX10_L_3" + ], + [ + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_3" + ], + [ + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "PCIE_LOGIC_OUTS_B21_L_3" + ], + [ + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_3" + ], + [ + "INT_INTERFACE_EE2A1", + "PCIE_EE2A1_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT15", + "PCIE_IMUX15_L_3" + ], + [ + "INT_INTERFACE_EE4A3", + "PCIE_EE4A3_3" + ], + [ + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "PCIE_LOGIC_OUTS_B17_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT24", + "PCIE_IMUX24_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT30", + "PCIE_IMUX30_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT18", + "PCIE_IMUX18_L_3" + ], + [ + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_3" + ], + [ + "INT_INTERFACE_LH12", + "PCIE_LH12_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT45", + "PCIE_IMUX45_L_3" + ], + [ + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_3" + ], + [ + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "PCIE_LOGIC_OUTS_B5_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT7", + "PCIE_IMUX7_L_3" + ], + [ + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT5", + "PCIE_IMUX5_L_3" + ], + [ + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "PCIE_LOGIC_OUTS_B7_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT42", + "PCIE_IMUX42_L_3" + ], + [ + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_3" + ], + [ + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_3" + ], + [ + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_3" + ], + [ + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT33", + "PCIE_IMUX33_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT22", + "PCIE_IMUX22_L_3" + ], + [ + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_3" + ], + [ + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "PCIE_LOGIC_OUTS_B13_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT36", + "PCIE_IMUX36_L_3" + ], + [ + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT29", + "PCIE_IMUX29_L_3" + ], + [ + "INT_INTERFACE_EE2BEG2", + "PCIE_EE2BEG2_3" + ], + [ + "INT_INTERFACE_LH5", + "PCIE_LH5_3" + ], + [ + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_3" + ], + [ + "INT_INTERFACE_LH7", + "PCIE_LH7_3" + ], + [ + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_3" + ], + [ + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_3" + ], + [ + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT21", + "PCIE_IMUX21_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT6", + "PCIE_IMUX6_L_3" + ], + [ + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT2", + "PCIE_IMUX2_L_3" + ], + [ + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_3" + ], + [ + "INT_INTERFACE_FAN6", + "PCIE_FAN6_L_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "PCIE_LOGIC_OUTS_B1_L_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "PCIE_LOGIC_OUTS_B19_L_3" + ], + [ + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_3" + ], + [ + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_3" + ], + [ + "INT_INTERFACE_CTRL1", + "PCIE_CTRL1_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT46", + "PCIE_IMUX46_L_3" + ], + [ + "INT_INTERFACE_ER1BEG0", + "PCIE_ER1BEG0_3" + ], + [ + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_3" + ], + [ + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "PCIE_LOGIC_OUTS_B4_L_3" + ], + [ + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_3" + ], + [ + "INT_INTERFACE_BYP4", + "PCIE_BYP4_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT3", + "PCIE_IMUX3_L_3" + ], + [ + "INT_INTERFACE_BYP1", + "PCIE_BYP1_L_3" + ], + [ + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_3" + ], + [ + "INT_INTERFACE_EE2BEG3", + "PCIE_EE2BEG3_3" + ], + [ + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT20", + "PCIE_IMUX20_L_3" + ], + [ + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_3" + ], + [ + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT9", + "PCIE_IMUX9_L_3" + ], + [ + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_3" + ], + [ + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_3" + ], + [ + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT44", + "PCIE_IMUX44_L_3" + ], + [ + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_3" + ], + [ + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_3" + ], + [ + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT35", + "PCIE_IMUX35_L_3" + ], + [ + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_3" + ], + [ + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_3" + ], + [ + "INT_INTERFACE_EE4C0", + "PCIE_EE4C0_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "PCIE_LOGIC_OUTS_B15_L_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "PCIE_LOGIC_OUTS_B0_L_3" + ], + [ + "INT_INTERFACE_LH2", + "PCIE_LH2_3" + ], + [ + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_3" + ], + [ + "INT_INTERFACE_EE2BEG1", + "PCIE_EE2BEG1_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT27", + "PCIE_IMUX27_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT17", + "PCIE_IMUX17_L_3" + ], + [ + "INT_INTERFACE_FAN4", + "PCIE_FAN4_L_3" + ], + [ + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_3" + ], + [ + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_3" + ], + [ + "INT_INTERFACE_MONITOR_P", + "PCIE_MONITOR_P_3" + ], + [ + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_3" + ], + [ + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_3" + ], + [ + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_3" + ], + [ + "INT_INTERFACE_LH8", + "PCIE_LH8_3" + ], + [ + "INT_INTERFACE_FAN5", + "PCIE_FAN5_L_3" + ], + [ + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT38", + "PCIE_IMUX38_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT26", + "PCIE_IMUX26_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT43", + "PCIE_IMUX43_L_3" + ], + [ + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_3" + ], + [ + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT34", + "PCIE_IMUX34_L_3" + ], + [ + "INT_INTERFACE_CLK1", + "PCIE_CLK1_L_3" + ], + [ + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_3" + ], + [ + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_3" + ], + [ + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_3" + ], + [ + "INT_INTERFACE_FAN3", + "PCIE_FAN3_L_3" + ], + [ + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "PCIE_LOGIC_OUTS_B22_L_3" + ], + [ + "INT_INTERFACE_LH9", + "PCIE_LH9_3" + ], + [ + "INT_INTERFACE_FAN0", + "PCIE_FAN0_L_3" + ], + [ + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_3" + ], + [ + "INT_INTERFACE_LH4", + "PCIE_LH4_3" + ], + [ + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_3" + ], + [ + "INT_INTERFACE_EE4C1", + "PCIE_EE4C1_3" + ], + [ + "INT_INTERFACE_FAN7", + "PCIE_FAN7_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT19", + "PCIE_IMUX19_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT16", + "PCIE_IMUX16_L_3" + ], + [ + "INT_INTERFACE_EL1BEG3", + "PCIE_EL1BEG3_3" + ], + [ + "INT_INTERFACE_EE2A0", + "PCIE_EE2A0_3" + ], + [ + "INT_INTERFACE_EE2A3", + "PCIE_EE2A3_3" + ], + [ + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT25", + "PCIE_IMUX25_L_3" + ], + [ + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT37", + "PCIE_IMUX37_L_3" + ], + [ + "INT_INTERFACE_BYP3", + "PCIE_BYP3_L_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "PCIE_LOGIC_OUTS_B16_L_3" + ], + [ + "INT_INTERFACE_LH10", + "PCIE_LH10_3" + ], + [ + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_3" + ], + [ + "INT_INTERFACE_EE2BEG0", + "PCIE_EE2BEG0_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT4", + "PCIE_IMUX4_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT32", + "PCIE_IMUX32_L_3" + ], + [ + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_3" + ], + [ + "INT_INTERFACE_MONITOR_N", + "PCIE_MONITOR_N_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT0", + "PCIE_IMUX0_L_3" + ], + [ + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_3" + ], + [ + "INT_INTERFACE_LH1", + "PCIE_LH1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "PCIE_LOGIC_OUTS_B3_L_3" + ], + [ + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_3" + ], + [ + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "PCIE_LOGIC_OUTS_B18_L_3" + ], + [ + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "PCIE_LOGIC_OUTS_B11_L_3" + ], + [ + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "PCIE_LOGIC_OUTS_B10_L_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "PCIE_LOGIC_OUTS_B6_L_3" + ], + [ + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT13", + "PCIE_IMUX13_L_3" + ], + [ + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "PCIE_LOGIC_OUTS_B20_L_3" + ], + [ + "INT_INTERFACE_LH3", + "PCIE_LH3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "PCIE_LOGIC_OUTS_B8_L_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "PCIE_LOGIC_OUTS_B12_L_3" + ], + [ + "INT_INTERFACE_EE4C2", + "PCIE_EE4C2_3" + ], + [ + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_3" + ], + [ + "INT_INTERFACE_EE4B0", + "PCIE_EE4B0_3" + ], + [ + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_3" + ], + [ + "INT_INTERFACE_EE4A1", + "PCIE_EE4A1_3" + ], + [ + "INT_INTERFACE_LH11", + "PCIE_LH11_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT40", + "PCIE_IMUX40_L_3" + ], + [ + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_3" + ], + [ + "INT_INTERFACE_BYP7", + "PCIE_BYP7_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT23", + "PCIE_IMUX23_L_3" + ], + [ + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_3" + ], + [ + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "PCIE_LOGIC_OUTS_B9_L_3" + ], + [ + "INT_INTERFACE_CTRL0", + "PCIE_CTRL0_L_3" + ], + [ + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_3" + ], + [ + "INT_INTERFACE_EE4A0", + "PCIE_EE4A0_3" + ], + [ + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_3" + ], + [ + "INT_INTERFACE_BYP5", + "PCIE_BYP5_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT1", + "PCIE_IMUX1_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT41", + "PCIE_IMUX41_L_3" + ], + [ + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_3" + ], + [ + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_3" + ], + [ + "INT_INTERFACE_FAN2", + "PCIE_FAN2_L_3" + ], + [ + "INT_INTERFACE_BYP2", + "PCIE_BYP2_L_3" + ], + [ + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_3" + ], + [ + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT12", + "PCIE_IMUX12_L_3" + ], + [ + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_3" + ], + [ + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT14", + "PCIE_IMUX14_L_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT47", + "PCIE_IMUX47_L_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "PCIE_LOGIC_OUTS_B2_L_3" + ], + [ + "INT_INTERFACE_LH6", + "PCIE_LH6_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT11", + "PCIE_IMUX11_L_3" + ], + [ + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_3" + ] + ], + "tile_types": [ + "PCIE_INT_INTERFACE_L", + "PCIE_TOP" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_IOI_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_IOI_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_IOI_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_IOI_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_IOI_IOCLK_PLL3", + "HCLK_TERM_PERFCLK3" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_IOI_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_IOI_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_IOI_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_IOI_IOCLK_PLL1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_IOI_I2IOCLK_TOP0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_IOI_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_IOI_IOCLK_PLL0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_IOI_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_IOI_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_IOI_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_IOI_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_IOI_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_IOI_I2IOCLK_BOT0", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_IOI_IOCLK_PLL2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_IOI_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_IOI_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_IOI_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ] + ], + "tile_types": [ + "HCLK_IOI3", + "HCLK_TERM" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CCIO1", + "HCLK_CCIO1" + ], + [ + "HCLK_INT_INTERFACE_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_INT_INTERFACE_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_INT_INTERFACE_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_INT_INTERFACE_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_INT_INTERFACE_CCIO3", + "HCLK_CCIO3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_INT_INTERFACE_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CCIO0", + "HCLK_CCIO0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_INT_INTERFACE_CCIO2", + "HCLK_CCIO2" + ], + [ + "HCLK_INT_INTERFACE_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_INT_INTERFACE_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_INT_PERFCLK3" + ] + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_L" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "CMT_TOP_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH6_3", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_LH1_3", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_LH12_3", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_LH7_3", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_3", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH3_3", + "VBRK_LH3" + ], + [ + "CMT_TOP_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_MONITOR_P_3", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_LH2_3", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_MONITOR_N_3", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_LH9_3", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH5_3", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH11_3", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_LH10_3", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH8_3", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EL1BEG1_3", + "VBRK_EL1BEG1" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_FIFO_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CCIO2", + "HCLK_FIFO_CCIO2" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_FIFO_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_FIFO_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_FIFO_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_FIFO_PERFCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_FIFO_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_FIFO_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_FIFO_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_FIFO_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_FIFO_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_FIFO_PERFCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_FIFO_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_FIFO_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_FIFO_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_FIFO_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_FIFO_PERFCLK0" + ], + [ + "HCLK_CMT_CCIO0", + "HCLK_FIFO_CCIO0" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_FIFO_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_FIFO_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CCIO3", + "HCLK_FIFO_CCIO3" + ], + [ + "HCLK_CMT_CCIO1", + "HCLK_FIFO_CCIO1" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_FIFO_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_FIFO_CK_BUFRCLK2" + ] + ], + "tile_types": [ + "HCLK_CMT_L", + "HCLK_FIFO_L" + ] + }, + { + "grid_deltas": [ + 5, + -7 + ], + "wire_pairs": [ + [ + "PCIE_LH6_17", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_WL1END0_17", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_EE4BEG0_17", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX43_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_IMUX22_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_WW4END0_17", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_WR1END3_17", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_BYP0_L_17", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_EE4C3_17", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_SE2A2_17", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_IMUX41_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_BYP3_L_17", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_IMUX46_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_NW4A1_17", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_EE2BEG3_17", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_WW4A2_17", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_BYP2_L_17", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_WW4C1_17", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_SE4C0_17", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_FAN4_L_17", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_EE2A2_17", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_IMUX33_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_SE4BEG2_17", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_IMUX19_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_FAN7_L_17", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_WW2A1_17", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_IMUX6_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_NW4END0_17", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_SW2A2_17", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_CLK1_L_17", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_EE4B0_17", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX26_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_SE4C3_17", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_SW2A3_17", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX17_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_IMUX20_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_IMUX23_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_SW4A3_17", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_FAN5_L_17", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_LH5_17", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_NW4END3_17", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_NW2A0_17", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_IMUX39_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_WW4B1_17", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_NE4BEG3_17", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_WW2END3_17", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_IMUX1_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_WW4A3_17", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_IMUX12_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_IMUX18_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_EE4C2_17", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_FAN6_L_17", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_WR1END2_17", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_IMUX0_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_IMUX9_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_NE4C3_17", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_WL1END2_17", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_CLK0_L_17", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_NW2A3_17", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_LH1_17", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_SE2A1_17", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_BYP5_L_17", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_NE2A1_17", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_IMUX44_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_NE4C0_17", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_IMUX24_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_EE4A1_17", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_LH12_17", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_LH3_17", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_ER1BEG0_17", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_IMUX4_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_IMUX3_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_WW2A0_17", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_EE2BEG0_17", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_ER1BEG1_17", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_SE4C1_17", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_NE4BEG2_17", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_SW4A0_17", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_EE4A3_17", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_SE2A0_17", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_IMUX15_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_WW2END0_17", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_EE2BEG1_17", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_BYP7_L_17", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_WW2END2_17", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_IMUX37_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_EL1BEG0_17", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_LH2_17", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_SW4A1_17", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_BYP6_L_17", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_WW2A2_17", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_SE4BEG3_17", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_IMUX10_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_SW4END3_17", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_IMUX38_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_NW4END1_17", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_SE2A3_17", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_EE2BEG2_17", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_NE4C1_17", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_LH10_17", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_SE4C2_17", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_WL1END1_17", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_IMUX7_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_EE4C1_17", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_SW4END2_17", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_FAN3_L_17", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX27_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_IMUX45_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_FAN2_L_17", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_BYP4_L_17", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_MONITOR_N_17", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_SE4BEG0_17", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_WW4A0_17", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_WW4B2_17", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_WW4C0_17", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_NE2A0_17", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_CTRL1_L_17", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_IMUX31_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_EE4B2_17", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_EE2A3_17", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_ER1BEG2_17", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_IMUX35_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_IMUX42_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_SW4END1_17", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_WW4END3_17", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_EE4BEG3_17", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_IMUX5_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_ER1BEG3_17", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_IMUX40_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_SW2A1_17", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_EE4BEG2_17", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_NE2A2_17", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_WW4B3_17", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_LH9_17", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_WL1END3_17", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_WW4C3_17", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_WW4A1_17", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_NE4BEG0_17", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_EE2A1_17", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_MONITOR_P_17", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_IMUX29_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_NW4END2_17", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_IMUX30_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_NW4A2_17", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_WW2A3_17", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_IMUX36_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_NE2A3_17", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_IMUX21_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_NW2A1_17", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_WW4END1_17", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_LH11_17", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_EE4C0_17", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX28_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_LH4_17", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_IMUX32_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_IMUX8_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_EE4A0_17", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_EL1BEG2_17", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_IMUX13_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_WW4B0_17", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_WR1END0_17", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_SE4BEG1_17", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_CTRL0_L_17", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_SW4A2_17", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_EL1BEG1_17", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_IMUX16_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_NW4A3_17", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_EE4BEG1_17", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_IMUX2_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_EE4B1_17", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_NW4A0_17", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WW4END2_17", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_NW2A2_17", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_EL1BEG3_17", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_NE4C2_17", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_IMUX11_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_LH7_17", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_BYP1_L_17", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_SW4END0_17", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_IMUX47_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_WR1END1_17", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_IMUX14_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_NE4BEG1_17", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_FAN1_L_17", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_WW2END1_17", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_17", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_LH8_17", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4A2_17", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_EE2A0_17", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_IMUX25_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_FAN0_L_17", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_IMUX34_L_17", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_SW2A0_17", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_EE4B3_17", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_WW4C2_17", + "INT_INTERFACE_WW4C2" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_PMVIOB" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "CLK_BUFG_IMUX27_3", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_SW4END2_3", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_CTRL1_3", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_WW4C2_3", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_EE4A3_3", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B2_3", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CLK_HROW_CLK0_3", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_BUFG_IMUX9_3", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_FAN2_3", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_BUFG_IMUX45_3", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_SE4BEG2_3", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_EE4C1_3", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_BUFG_IMUX36_3", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_NE2A1_3", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_FAN0_3", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_WW2A3_3", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_FAN4_3", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B6_3", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CLK_HROW_EE2BEG3_3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_WW4A3_3", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_BUFG_IMUX14_3", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_SE4BEG3_3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_BUFG_IMUX3_3", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_BUFG_IMUX22_3", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_NW2A2_3", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B3_3", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CLK_BUFG_IMUX15_3", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B7_3", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CLK_HROW_WW4END1_3", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_SW2A1_3", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_SE4C3_3", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_BUFG_IMUX34_3", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_SE4BEG0_3", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_EE4BEG0_3", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_BUFG_IMUX8_3", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_BUFG_IMUX30_3", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_EL1BEG3_3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_WR1END0_3", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_NW4A1_3", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_WL1END0_3", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_WL1END1_3", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_SE2A1_3", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_BUFG_IMUX12_3", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_BUFG_IMUX47_3", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_NW4END1_3", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_BUFG_IMUX28_3", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_SW4END1_3", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_BUFG_IMUX46_3", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_NW2A1_3", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_ER1BEG2_3", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_BUFG_IMUX7_3", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_BUFG_IMUX21_3", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_EE2BEG0_3", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_BUFG_IMUX0_3", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_SW4END3_3", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_WW2END0_3", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_NE4C2_3", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_BUFG_IMUX5_3", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_BUFG_IMUX40_3", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_BYP6_3", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_EE2A0_3", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_WL1END3_3", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_WW4B2_3", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_LH9_3", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_BYP4_3", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_WW4A1_3", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_LH12_3", + "INT_INTERFACE_LH12" + ], + [ + "CLK_BUFG_IMUX23_3", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_SW2A3_3", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_NE2A0_3", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_EE2BEG2_3", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_ER1BEG0_3", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_LH4_3", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_WW2A2_3", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_ER1BEG1_3", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_SE2A3_3", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_EE4B3_3", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_BUFG_IMUX1_3", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_WW4END3_3", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_BUFG_IMUX44_3", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_BUFG_IMUX10_3", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_LH1_3", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_EE2A1_3", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_EE4B2_3", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_BUFG_IMUX37_3", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_BYP5_3", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_BYP2_3", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_NW4END2_3", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_WW2END1_3", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_SE4C1_3", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_BUFG_IMUX11_3", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_EE2BEG1_3", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_BUFG_IMUX42_3", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_WW4A2_3", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_EE4A0_3", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_EE4C3_3", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_NE4BEG1_3", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_WW2END2_3", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_WW4C0_3", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_EE2A3_3", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_EL1BEG2_3", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_SW4A2_3", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_WW2A1_3", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_WW4END0_3", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_CTRL0_3", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_SW4A0_3", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_BUFG_IMUX24_3", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_EL1BEG1_3", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_SE2A0_3", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_LH6_3", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_EE4C0_3", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_EE4B0_3", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_NE4C0_3", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_BUFG_IMUX32_3", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_BYP1_3", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_FAN5_3", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_EE4C2_3", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_EE2A2_3", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_BUFG_IMUX43_3", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_WW4B3_3", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_LH2_3", + "INT_INTERFACE_LH2" + ], + [ + "CLK_BUFG_IMUX6_3", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_NW2A0_3", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_BYP7_3", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_SE4C0_3", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_NE4C1_3", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_WW2END3_3", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_BUFG_IMUX20_3", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_SE2A2_3", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_NE4C3_3", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_WL1END2_3", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_BUFG_IMUX38_3", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_SW4END0_3", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_SW2A2_3", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_WR1END2_3", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_NE2A3_3", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B1_3", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CLK_HROW_SW4A3_3", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_NW4A0_3", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_NW4A2_3", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_FAN7_3", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_WW4B0_3", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_BUFG_IMUX33_3", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_BUFG_IMUX13_3", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_BYP0_3", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_CLK1_3", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_BUFG_IMUX25_3", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_SW2A0_3", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE4A2_3", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_ER1BEG3_3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_LH5_3", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_NW2A3_3", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_NE2A2_3", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_WW2A0_3", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_NE4BEG3_3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B5_3", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CLK_HROW_FAN6_3", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_FAN1_3", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_BUFG_IMUX39_3", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_BYP3_3", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_WW4END2_3", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_WW4A0_3", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_SE4BEG1_3", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_NW4A3_3", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_BUFG_IMUX16_3", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_EE4BEG2_3", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_BUFG_IMUX19_3", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_EL1BEG0_3", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_LH10_3", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_FAN3_3", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_BUFG_IMUX17_3", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_WW4B1_3", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_NW4END0_3", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_LH7_3", + "INT_INTERFACE_LH7" + ], + [ + "CLK_BUFG_IMUX31_3", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B4_3", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CLK_HROW_LH8_3", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_EE4A1_3", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_BUFG_IMUX35_3", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_EE4BEG3_3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B0_3", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CLK_BUFG_IMUX29_3", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_SW4A1_3", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_LH11_3", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_WR1END1_3", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_WW4C3_3", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_NE4BEG2_3", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_LH3_3", + "INT_INTERFACE_LH3" + ], + [ + "CLK_BUFG_IMUX41_3", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_BUFG_IMUX2_3", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_BUFG_IMUX18_3", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_EE4BEG1_3", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_EE4B1_3", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_SE4C2_3", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_BUFG_IMUX26_3", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_BUFG_IMUX4_3", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_NE4BEG0_3", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_NW4END3_3", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_WW4C1_3", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_WR1END3_3", + "INT_INTERFACE_WR1END3" + ] + ], + "tile_types": [ + "CLK_BUFG_BOT_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 8 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_8" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_8" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_8" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_8" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_8" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_8" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_8" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_8" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_8" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_8" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_8" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_8" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_8" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_8" + ], + [ + "INT_FEEDTHRU_2_MONITOR_P", + "MONITOR_HORIZ_VAUXP3" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_8" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_8" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_8" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_8" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_8" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_8" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_8" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_8" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_8" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_8" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_8" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_8" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_8" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_8" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_8" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_8" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_8" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_8" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_8" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_8" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_8" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_8" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_8" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_8" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_8" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_8" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_8" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_8" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_8" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_8" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_8" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_8" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_8" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_8" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_8" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_8" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_8" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_8" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_8" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_8" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_8" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_8" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_8" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_8" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_8" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_8" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_8" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_8" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_8" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_8" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_8" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_8" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_8" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_8" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_8" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_8" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_8" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_8" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_8" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_8" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_8" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_8" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_8" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_8" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_8" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_8" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_8" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_8" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_8" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_8" + ], + [ + "INT_FEEDTHRU_2_MONITOR_N", + "MONITOR_HORIZ_VAUXN3" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_8" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_8" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_8" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_8" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_8" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_8" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_8" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_8" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_8" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_8" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_8" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_8" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_8" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_8" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_8" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_8" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_8" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_8" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_8" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_8" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_8" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_8" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_8" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_8" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_8" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_8" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_8" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_8" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_8" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_8" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_8" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_8" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_8" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_8" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_8" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_8" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_8" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_8" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_8" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_8" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_BOT_FUJI2" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "BRAM_CASCINBOT_ADDRARDADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" + ], + [ + "BRAM_PMVBRAM_SELECT1", + "HCLK_BRAM_PMVBRAM_SELECT1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" + ], + [ + "BRAM_FIFO36_CASCADEINA", + "HCLK_BRAM_CASCADEA_R" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" + ], + [ + "BRAM_FIFO36_CASCADEINB", + "HCLK_BRAM_CASCADEB_R" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" + ], + [ + "BRAM_PMVBRAM_SELECT3", + "HCLK_BRAM_PMVBRAM_SELECT3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" + ], + [ + "BRAM_PMVBRAM_SELECT4", + "HCLK_BRAM_PMVBRAM_SELECT4" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" + ], + [ + "BRAM_PMVBRAM_SELECT2", + "HCLK_BRAM_PMVBRAM_SELECT2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" + ], + [ + "BRAM_PMVBRAM_ODIV4", + "HCLK_BRAM_PMVBRAM_ODIV4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" + ], + [ + "BRAM_PMVBRAM_ODIV2", + "HCLK_BRAM_PMVBRAM_ODIV2" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" + ], + [ + "BRAM_PMVBRAM_O", + "HCLK_BRAM_PMVBRAM_O" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" + ] + ], + "tile_types": [ + "BRAM_R", + "HCLK_BRAM" + ] + }, + { + "grid_deltas": [ + 0, + -2 + ], + "wire_pairs": [ + [ + "IOI_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1_1" + ], + [ + "IOI_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0_1" + ] + ], + "tile_types": [ + "LIOI3", + "LIOI3" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_2" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_2" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_2" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_2" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_2" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_2" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_2" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_2" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_2" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_2" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_2" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_2" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_2" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_2" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_2" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_2" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_2" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_2" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_2" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_2" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_2" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_2" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_2" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_2" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_2" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_2" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_2" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_2" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_2" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_2" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_2" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_2" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_2" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_2" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_2" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_2" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_2" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_2" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_2" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_2" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_2" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_2" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_2" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_2" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_2" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_2" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_2" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_2" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_2" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_2" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_2" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_2" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_2" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_2" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_2" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_2" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_2" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_2" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_2" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_2" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_2" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_2" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_2" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_2" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_2" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_2" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_2" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_2" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_2" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_2" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_2" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_2" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_2" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_2" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_2" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_2" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_2" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_2" + ], + [ + "INT_FEEDTHRU_2_MONITOR_N", + "MONITOR_HORIZ_VAUXN0" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_2" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_2" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_2" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_2" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_2" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_2" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_2" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_2" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_2" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_2" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_2" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_2" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_2" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_2" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_2" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_2" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_2" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_2" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_2" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_2" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_2" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_2" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_2" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_2" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_2" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_2" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_2" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_2" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_2" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_2" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_2" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_2" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_2" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_2" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_2" + ], + [ + "INT_FEEDTHRU_2_MONITOR_P", + "MONITOR_HORIZ_VAUXP0" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_2" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_2" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_2" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_2" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_2" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_2" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_2" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_2" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_TOP_FUJI2" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "BRAM_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "BRAM_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "BRAM_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "BRAM_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "BRAM_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "BRAM_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "BRAM_LH3_0", + "VBRK_LH3" + ], + [ + "BRAM_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "BRAM_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "BRAM_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "BRAM_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "BRAM_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "BRAM_LH9_0", + "VBRK_LH9" + ], + [ + "BRAM_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "BRAM_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "BRAM_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "BRAM_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "BRAM_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "BRAM_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "BRAM_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "BRAM_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "BRAM_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "BRAM_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "BRAM_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "BRAM_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "BRAM_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "BRAM_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "BRAM_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "BRAM_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "BRAM_LH1_0", + "VBRK_LH1" + ], + [ + "BRAM_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "BRAM_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "BRAM_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "BRAM_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "BRAM_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "BRAM_LH10_0", + "VBRK_LH10" + ], + [ + "BRAM_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "BRAM_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "BRAM_LH11_0", + "VBRK_LH11" + ], + [ + "BRAM_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "BRAM_LH12_0", + "VBRK_LH12" + ], + [ + "BRAM_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "BRAM_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "BRAM_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "BRAM_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "BRAM_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "BRAM_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "BRAM_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "BRAM_LH4_0", + "VBRK_LH4" + ], + [ + "BRAM_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "BRAM_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "BRAM_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "BRAM_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "BRAM_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "BRAM_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "BRAM_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "BRAM_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "BRAM_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "BRAM_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "BRAM_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "BRAM_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "BRAM_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "BRAM_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "BRAM_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "BRAM_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "BRAM_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "BRAM_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "BRAM_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "BRAM_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "BRAM_SW4A1_0", + "VBRK_SW4A1" + ], + [ + "BRAM_MONITOR_P_0", + "VBRK_MONITOR_P" + ], + [ + "BRAM_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "BRAM_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "BRAM_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "BRAM_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "BRAM_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "BRAM_LH8_0", + "VBRK_LH8" + ], + [ + "BRAM_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "BRAM_MONITOR_N_0", + "VBRK_MONITOR_N" + ], + [ + "BRAM_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "BRAM_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "BRAM_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "BRAM_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "BRAM_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "BRAM_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "BRAM_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "BRAM_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "BRAM_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "BRAM_LH2_0", + "VBRK_LH2" + ], + [ + "BRAM_LH6_0", + "VBRK_LH6" + ], + [ + "BRAM_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "BRAM_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "BRAM_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "BRAM_LH7_0", + "VBRK_LH7" + ], + [ + "BRAM_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "BRAM_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "BRAM_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "BRAM_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "BRAM_LH5_0", + "VBRK_LH5" + ], + [ + "BRAM_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "BRAM_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "BRAM_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "BRAM_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "BRAM_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "BRAM_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "BRAM_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "BRAM_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "BRAM_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "BRAM_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "BRAM_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "BRAM_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "BRAM_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "BRAM_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "BRAM_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "BRAM_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "BRAM_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "BRAM_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "BRAM_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "BRAM_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "BRAM_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "BRAM_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "BRAM_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "BRAM_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "BRAM_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "BRAM_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "BRAM_EE4BEG0_0", + "VBRK_EE4BEG0" + ] + ], + "tile_types": [ + "BRAM_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "IOI_BLOCK_OUTS1_1", + "TERM_INT_BLOCK_OUTS_L_B1" + ], + [ + "IOI_CLK1_1", + "TERM_INT_CLK1" + ], + [ + "IOI_IMUX29_1", + "TERM_INT_IMUX29" + ], + [ + "IOI_BYP0_1", + "TERM_INT_BYP0" + ], + [ + "IOI_IMUX44_1", + "TERM_INT_IMUX44" + ], + [ + "IOI_IMUX28_1", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX5_1", + "TERM_INT_IMUX5" + ], + [ + "IOI_LOGIC_OUTS0_1", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_IMUX30_1", + "TERM_INT_IMUX30" + ], + [ + "IOI_CTRL1_1", + "TERM_INT_CTRL1" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_PHASER_TO_IO_ICLK_0", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_IMUX43_1", + "TERM_INT_IMUX43" + ], + [ + "IOI_LOGIC_OUTS21_1", + "TERM_INT_LOGIC_OUTS_L_B21" + ], + [ + "IOI_IMUX23_1", + "TERM_INT_IMUX23" + ], + [ + "IOI_IMUX18_1", + "TERM_INT_IMUX18" + ], + [ + "IOI_IMUX37_1", + "TERM_INT_IMUX37" + ], + [ + "IOI_IMUX33_1", + "TERM_INT_IMUX33" + ], + [ + "IOI_LOGIC_OUTS7_1", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_LOGIC_OUTS18_1", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_BYP4_1", + "TERM_INT_BYP4" + ], + [ + "IOI_IMUX47_1", + "TERM_INT_IMUX47" + ], + [ + "IOI_LOGIC_OUTS1_1", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX34_1", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX39_1", + "TERM_INT_IMUX39" + ], + [ + "IOI_LOGIC_OUTS4_1", + "TERM_INT_LOGIC_OUTS_L_B4" + ], + [ + "IOI_BYP1_1", + "TERM_INT_BYP1" + ], + [ + "IOI_FAN6_1", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX38_1", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX3_1", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX21_1", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX22_1", + "TERM_INT_IMUX22" + ], + [ + "IOI_PHASER_TO_IO_OCLK_0", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_IMUX26_1", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX11_1", + "TERM_INT_IMUX11" + ], + [ + "IOI_CLK0_1", + "TERM_INT_CLK0" + ], + [ + "IOI_LOGIC_OUTS20_1", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_BYP2_1", + "TERM_INT_BYP2" + ], + [ + "IOI_IMUX8_1", + "TERM_INT_IMUX8" + ], + [ + "IOI_LOGIC_OUTS6_1", + "TERM_INT_LOGIC_OUTS_L_B6" + ], + [ + "IOI_IMUX19_1", + "TERM_INT_IMUX19" + ], + [ + "IOI_LOGIC_OUTS2_1", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_FAN2_1", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX14_1", + "TERM_INT_IMUX14" + ], + [ + "IOI_IMUX7_1", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX40_1", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX25_1", + "TERM_INT_IMUX25" + ], + [ + "IOI_LOGIC_OUTS16_1", + "TERM_INT_LOGIC_OUTS_L_B16" + ], + [ + "IOI_IMUX15_1", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX24_1", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX6_1", + "TERM_INT_IMUX6" + ], + [ + "IOI_IMUX4_1", + "TERM_INT_IMUX4" + ], + [ + "IOI_LOGIC_OUTS15_1", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX41_1", + "TERM_INT_IMUX41" + ], + [ + "IOI_LOGIC_OUTS17_1", + "TERM_INT_LOGIC_OUTS_L_B17" + ], + [ + "IOI_BYP6_1", + "TERM_INT_BYP6" + ], + [ + "IOI_FAN4_1", + "TERM_INT_FAN4" + ], + [ + "IOI_FAN1_1", + "TERM_INT_FAN1" + ], + [ + "IOI_IMUX32_1", + "TERM_INT_IMUX32" + ], + [ + "IOI_IMUX45_1", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX20_1", + "TERM_INT_IMUX20" + ], + [ + "IOI_IMUX46_1", + "TERM_INT_IMUX46" + ], + [ + "IOI_LOGIC_OUTS12_1", + "TERM_INT_LOGIC_OUTS_L_B12" + ], + [ + "IOI_IMUX31_1", + "TERM_INT_IMUX31" + ], + [ + "IOI_FAN0_1", + "TERM_INT_FAN0" + ], + [ + "IOI_LOGIC_OUTS13_1", + "TERM_INT_LOGIC_OUTS_L_B13" + ], + [ + "IOI_IMUX35_1", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP7_1", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_1", + "TERM_INT_IMUX2" + ], + [ + "IOI_IMUX9_1", + "TERM_INT_IMUX9" + ], + [ + "IOI_BYP5_1", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS19_1", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_FAN3_1", + "TERM_INT_FAN3" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_IMUX36_1", + "TERM_INT_IMUX36" + ], + [ + "IOI_LOGIC_OUTS22_1", + "TERM_INT_LOGIC_OUTS_L_B22" + ], + [ + "IOI_BLOCK_OUTS2_1", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "IOI_FAN7_1", + "TERM_INT_FAN7" + ], + [ + "IOI_LOGIC_OUTS5_1", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_LOGIC_OUTS11_1", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_IMUX27_1", + "TERM_INT_IMUX27" + ], + [ + "IOI_LOGIC_OUTS8_1", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_IMUX12_1", + "TERM_INT_IMUX12" + ], + [ + "IOI_LOGIC_OUTS3_1", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_IMUX16_1", + "TERM_INT_IMUX16" + ], + [ + "IOI_LOGIC_OUTS14_1", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_LOGIC_OUTS9_1", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_FAN5_1", + "TERM_INT_FAN5" + ], + [ + "IOI_IMUX1_1", + "TERM_INT_IMUX1" + ], + [ + "IOI_IMUX42_1", + "TERM_INT_IMUX42" + ], + [ + "IOI_IMUX10_1", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX13_1", + "TERM_INT_IMUX13" + ], + [ + "IOI_BLOCK_OUTS0_1", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_CTRL0_1", + "TERM_INT_CTRL0" + ], + [ + "IOI_LOGIC_OUTS23_1", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_IMUX17_1", + "TERM_INT_IMUX17" + ], + [ + "IOI_BYP3_1", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX0_1", + "TERM_INT_IMUX0" + ], + [ + "IOI_LOGIC_OUTS10_1", + "TERM_INT_LOGIC_OUTS_L_B10" + ] + ], + "tile_types": [ + "RIOI", + "R_TERM_INT" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "CLK_PMV_SW2A0_5", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_PMV_EL1BEG2_5", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_PMV_NW2A3_5", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_PMV_IMUX24_5", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_PMV_CTRL1_5", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_PMV_WR1END3_5", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_PMV_IMUX43_5", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_PMV_IMUX2_5", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_PMV_IMUX25_5", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_PMV_SE4C1_5", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_PMV_LH3_5", + "INT_INTERFACE_LH3" + ], + [ + "CLK_PMV_FAN2_5", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_PMV_WW4A0_5", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_PMV_WW2END1_5", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_PMV_NE2A2_5", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_PMV_SW4END3_5", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_PMV_IMUX33_5", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_PMV_EE4A0_5", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_PMV_LH10_5", + "INT_INTERFACE_LH10" + ], + [ + "CLK_PMV_FAN6_5", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_PMV_SW4A3_5", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_PMV_EE2BEG0_5", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_PMV_LH6_5", + "INT_INTERFACE_LH6" + ], + [ + "CLK_PMV_SE2A2_5", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_PMV_IMUX22_5", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_PMV_SE4C0_5", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_PMV_EE2A0_5", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_PMV_WW4B1_5", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_PMV_WW2END3_5", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_PMV_EL1BEG3_5", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_PMV_IMUX34_5", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_PMV_IMUX14_5", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_PMV_SE4BEG2_5", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_PMV_BYP1_5", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_PMV_NE4BEG2_5", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_PMV_IMUX8_5", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_PMV_SE4C3_5", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_PMV_EE4A2_5", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_PMV_ER1BEG1_5", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_PMV_WW4A2_5", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_PMV_SW2A3_5", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_PMV_EE2BEG3_5", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_PMV_NW4A0_5", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_PMV_FAN7_5", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_PMV_BYP5_5", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_PMV_LH4_5", + "INT_INTERFACE_LH4" + ], + [ + "CLK_PMV_EE4C1_5", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_PMV_IMUX37_5", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_PMV_IMUX30_5", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_PMV_EE4A3_5", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_PMV_WL1END2_5", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_PMV_LH1_5", + "INT_INTERFACE_LH1" + ], + [ + "CLK_PMV_IMUX36_5", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_PMV_IMUX29_5", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_PMV_IMUX32_5", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_PMV_EL1BEG0_5", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_PMV_NW2A1_5", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_PMV_WW4END1_5", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_PMV_BYP7_5", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_PMV_IMUX5_5", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_PMV_FAN3_5", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_PMV_IMUX45_5", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_PMV_ER1BEG3_5", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_PMV_WL1END3_5", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_PMV_EE4C0_5", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_PMV_IMUX41_5", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_PMV_LH12_5", + "INT_INTERFACE_LH12" + ], + [ + "CLK_PMV_EE4B1_5", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_PMV_SE4BEG0_5", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_PMV_EE4B0_5", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_PMV_IMUX10_5", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_PMV_EE4A1_5", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_PMV_IMUX26_5", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_PMV_SE4BEG3_5", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_PMV_BYP6_5", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_PMV_BYP2_5", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_PMV_EE4C2_5", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_PMV_IMUX23_5", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_PMV_IMUX1_5", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_PMV_LH7_5", + "INT_INTERFACE_LH7" + ], + [ + "CLK_PMV_WW2A0_5", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_PMV_IMUX39_5", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_PMV_IMUX42_5", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_PMV_WW4END3_5", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_PMV_WW4B0_5", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_PMV_WW2A2_5", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_PMV_SE2A3_5", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_PMV_NE4BEG1_5", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_PMV_NE4C0_5", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_PMV_LH9_5", + "INT_INTERFACE_LH9" + ], + [ + "CLK_PMV_LH8_5", + "INT_INTERFACE_LH8" + ], + [ + "CLK_PMV_IMUX4_5", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_PMV_CLK0_5", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_PMV_IMUX18_5", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_PMV_EL1BEG1_5", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_PMV_WW2END2_5", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_PMV_BYP0_5", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_PMV_EE2A3_5", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_PMV_WL1END0_5", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_PMV_FAN5_5", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_PMV_IMUX35_5", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_PMV_IMUX15_5", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_PMV_SE4C2_5", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_PMV_IMUX17_5", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_PMV_WW4C0_5", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_PMV_WW4C2_5", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_PMV_NW4END0_5", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_PMV_NE4BEG3_5", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_PMV_SE2A0_5", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_PMV_WL1END1_5", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_PMV_SE2A1_5", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_PMV_LH5_5", + "INT_INTERFACE_LH5" + ], + [ + "CLK_PMV_NE4BEG0_5", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_PMV_BYP4_5", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_PMV_NW4END3_5", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_PMV_SW4A0_5", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_PMV_FAN1_5", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_PMV_IMUX21_5", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_PMV_WW4END2_5", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_PMV_WW2A1_5", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_PMV_WW4A1_5", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_PMV_SW4END2_5", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_PMV_ER1BEG0_5", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_PMV_EE4C3_5", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_PMV_SW4A2_5", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_PMV_WW2A3_5", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_PMV_SW2A2_5", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_PMV_CLK1_5", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_PMV_WR1END1_5", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_PMV_WW4END0_5", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_PMV_IMUX19_5", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_PMV_WW4C3_5", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_PMV_IMUX27_5", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_PMV_IMUX20_5", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_PMV_IMUX44_5", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_PMV_EE4BEG3_5", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_PMV_WW2END0_5", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_PMV_SW4A1_5", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_PMV_EE4BEG0_5", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_PMV_NE4C1_5", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_PMV_NE2A3_5", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_PMV_IMUX38_5", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_PMV_IMUX31_5", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_PMV_EE4BEG1_5", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_PMV_FAN4_5", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_PMV_EE2A1_5", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_PMV_IMUX16_5", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_PMV_EE4B2_5", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_PMV_LH11_5", + "INT_INTERFACE_LH11" + ], + [ + "CLK_PMV_IMUX47_5", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_PMV_FAN0_5", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_PMV_NW4A1_5", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_PMV_WW4A3_5", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_PMV_IMUX12_5", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_PMV_CTRL0_5", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_PMV_IMUX0_5", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_PMV_IMUX3_5", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_PMV_SW2A1_5", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_PMV_WW4B3_5", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_PMV_ER1BEG2_5", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_PMV_NW4A3_5", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_PMV_SW4END0_5", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_PMV_IMUX40_5", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_PMV_IMUX46_5", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_PMV_IMUX11_5", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_PMV_WW4C1_5", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_PMV_NW4A2_5", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_PMV_EE4B3_5", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_PMV_NE2A0_5", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_PMV_SE4BEG1_5", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_PMV_BYP3_5", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_PMV_EE2A2_5", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_PMV_EE2BEG1_5", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_PMV_NE4C3_5", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_PMV_NE2A1_5", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_PMV_WR1END2_5", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_PMV_IMUX7_5", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_PMV_IMUX13_5", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_PMV_NW2A2_5", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_PMV_IMUX9_5", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_PMV_SW4END1_5", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_PMV_EE2BEG2_5", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_PMV_WW4B2_5", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_PMV_NW4END2_5", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_PMV_NW4END1_5", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_PMV_IMUX6_5", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_PMV_IMUX28_5", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_PMV_EE4BEG2_5", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_PMV_NE4C2_5", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_PMV_LH2_5", + "INT_INTERFACE_LH2" + ], + [ + "CLK_PMV_NW2A0_5", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_PMV_WR1END0_5", + "INT_INTERFACE_WR1END0" + ] + ], + "tile_types": [ + "CLK_PMV", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CMT_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CMT_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CMT_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CMT_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CMT_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ], + [ + "HCLK_CMT_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ] + ], + "tile_types": [ + "HCLK_CMT_L", + "HCLK_VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B23_9", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_LOGIC_OUTS_B4_9", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B7_9", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B8_9", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX0_9", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX42_9", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX38_9", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_LOGIC_OUTS_B3_9", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX13_9", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX10_9", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B15_9", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_FAN2_9", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_BYP4_9", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX27_9", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_FAN1_9", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_BYP2_9", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX40_9", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX44_9", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_CLK1_9", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_LOGIC_OUTS_B2_9", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX14_9", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX11_9", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX3_9", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX47_9", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_LOGIC_OUTS_B11_9", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_FAN3_9", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX33_9", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_FAN5_9", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_BYP1_9", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B20_9", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX8_9", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX20_9", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX34_9", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX18_9", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX1_9", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_LOGIC_OUTS_B18_9", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX5_9", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B19_9", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_BYP3_9", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B14_9", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX30_9", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX15_9", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_BYP6_9", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX43_9", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX23_9", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX7_9", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX26_9", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX9_9", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX46_9", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_LOGIC_OUTS_B0_9", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX29_9", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX4_9", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX6_9", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX22_9", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B9_9", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_LOGIC_OUTS_B10_9", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX21_9", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_FAN6_9", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_BYP0_9", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX39_9", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX16_9", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX35_9", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_FAN0_9", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_LOGIC_OUTS_B16_9", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B6_9", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_LOGIC_OUTS_B21_9", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_LOGIC_OUTS_B13_9", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_CTRL0_9", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX28_9", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_LOGIC_OUTS_B17_9", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_CLK0_9", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_FAN4_9", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_FAN7_9", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX45_9", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX36_9", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX2_9", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_BYP5_9", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX41_9", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B5_9", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_LOGIC_OUTS_B12_9", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX31_9", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B1_9", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_CTRL1_9", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX17_9", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX24_9", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX12_9", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX32_9", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B22_9", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_BYP7_9", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX25_9", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX19_9", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX37_9", + "VBRK_EXT_IMUX37" + ] + ], + "tile_types": [ + "GTX_CHANNEL_3", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "CMT_TOP_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_LH2_1", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH11_1", + "VBRK_LH11" + ], + [ + "CMT_TOP_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH10_1", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_LH8_1", + "VBRK_LH8" + ], + [ + "CMT_TOP_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH3_1", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH4_1", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH5_1", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_1", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_LH6_1", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH1_1", + "VBRK_LH1" + ], + [ + "CMT_TOP_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_LH7_1", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_LH9_1", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2BEG2_1", + "VBRK_EE2BEG2" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLBLM_NE4C0", + "CLBLM_NE4C0" + ], + [ + "CLBLM_WW4C0", + "CLBLM_WW4C0" + ], + [ + "CLBLM_WW4END1", + "CLBLM_WW4END1" + ], + [ + "CLBLM_NW2A0", + "CLBLM_NW2A0" + ], + [ + "CLBLM_WR1END1", + "CLBLM_WR1END1" + ], + [ + "CLBLM_EE4C3", + "CLBLM_EE4C3" + ], + [ + "CLBLM_SE4BEG3", + "CLBLM_SE4BEG3" + ], + [ + "CLBLM_NW4A3", + "CLBLM_NW4A3" + ], + [ + "CLBLM_WW4C3", + "CLBLM_WW4C3" + ], + [ + "CLBLM_SE2A2", + "CLBLM_SE2A2" + ], + [ + "CLBLM_ER1BEG1", + "CLBLM_ER1BEG1" + ], + [ + "CLBLM_SE4C2", + "CLBLM_SE4C2" + ], + [ + "CLBLM_EE2A2", + "CLBLM_EE2A2" + ], + [ + "CLBLM_EE2BEG3", + "CLBLM_EE2BEG3" + ], + [ + "CLBLM_EL1BEG1", + "CLBLM_EL1BEG1" + ], + [ + "CLBLM_WL1END3", + "CLBLM_WL1END3" + ], + [ + "CLBLM_SE2A3", + "CLBLM_SE2A3" + ], + [ + "CLBLM_WW4END3", + "CLBLM_WW4END3" + ], + [ + "CLBLM_NE2A0", + "CLBLM_NE2A0" + ], + [ + "CLBLM_EL1BEG0", + "CLBLM_EL1BEG0" + ], + [ + "CLBLM_SW4A0", + "CLBLM_SW4A0" + ], + [ + "CLBLM_SE4BEG0", + "CLBLM_SE4BEG0" + ], + [ + "CLBLM_WW2END0", + "CLBLM_WW2END0" + ], + [ + "CLBLM_NW2A1", + "CLBLM_NW2A1" + ], + [ + "CLBLM_NW4END3", + "CLBLM_NW4END3" + ], + [ + "CLBLM_SW4A1", + "CLBLM_SW4A1" + ], + [ + "CLBLM_EE4C0", + "CLBLM_EE4C0" + ], + [ + "CLBLM_SE4C3", + "CLBLM_SE4C3" + ], + [ + "CLBLM_SE4BEG2", + "CLBLM_SE4BEG2" + ], + [ + "CLBLM_EE4A2", + "CLBLM_EE4A2" + ], + [ + "CLBLM_ER1BEG2", + "CLBLM_ER1BEG2" + ], + [ + "CLBLM_EE4BEG3", + "CLBLM_EE4BEG3" + ], + [ + "CLBLM_NW2A3", + "CLBLM_NW2A3" + ], + [ + "CLBLM_WW4A2", + "CLBLM_WW4A2" + ], + [ + "CLBLM_NW4A0", + "CLBLM_NW4A0" + ], + [ + "CLBLM_LH8", + "CLBLM_LH8" + ], + [ + "CLBLM_SW4END3", + "CLBLM_SW4END3" + ], + [ + "CLBLM_WW4A1", + "CLBLM_WW4A1" + ], + [ + "CLBLM_WL1END0", + "CLBLM_WL1END0" + ], + [ + "CLBLM_LH4", + "CLBLM_LH4" + ], + [ + "CLBLM_EE2BEG1", + "CLBLM_EE2BEG1" + ], + [ + "CLBLM_WW4END2", + "CLBLM_WW4END2" + ], + [ + "CLBLM_ER1BEG0", + "CLBLM_ER1BEG0" + ], + [ + "CLBLM_WR1END0", + "CLBLM_WR1END0" + ], + [ + "CLBLM_WW4B1", + "CLBLM_WW4B1" + ], + [ + "CLBLM_NW4A1", + "CLBLM_NW4A1" + ], + [ + "CLBLM_WW2END1", + "CLBLM_WW2END1" + ], + [ + "CLBLM_NE2A1", + "CLBLM_NE2A1" + ], + [ + "CLBLM_NW4END1", + "CLBLM_NW4END1" + ], + [ + "CLBLM_LH10", + "CLBLM_LH10" + ], + [ + "CLBLM_MONITOR_P", + "CLBLM_MONITOR_P" + ], + [ + "CLBLM_EE4B1", + "CLBLM_EE4B1" + ], + [ + "CLBLM_MONITOR_N", + "CLBLM_MONITOR_N" + ], + [ + "CLBLM_EE4A3", + "CLBLM_EE4A3" + ], + [ + "CLBLM_SW2A3", + "CLBLM_SW2A3" + ], + [ + "CLBLM_WW4C2", + "CLBLM_WW4C2" + ], + [ + "CLBLM_EL1BEG3", + "CLBLM_EL1BEG3" + ], + [ + "CLBLM_WW4B0", + "CLBLM_WW4B0" + ], + [ + "CLBLM_LH1", + "CLBLM_LH1" + ], + [ + "CLBLM_SE4C1", + "CLBLM_SE4C1" + ], + [ + "CLBLM_NE2A2", + "CLBLM_NE2A2" + ], + [ + "CLBLM_WR1END2", + "CLBLM_WR1END2" + ], + [ + "CLBLM_EE4B3", + "CLBLM_EE4B3" + ], + [ + "CLBLM_EE2A0", + "CLBLM_EE2A0" + ], + [ + "CLBLM_EE4C2", + "CLBLM_EE4C2" + ], + [ + "CLBLM_WW2A2", + "CLBLM_WW2A2" + ], + [ + "CLBLM_LH11", + "CLBLM_LH11" + ], + [ + "CLBLM_EE4BEG2", + "CLBLM_EE4BEG2" + ], + [ + "CLBLM_SW4A2", + "CLBLM_SW4A2" + ], + [ + "CLBLM_EE4A0", + "CLBLM_EE4A0" + ], + [ + "CLBLM_NE4BEG2", + "CLBLM_NE4BEG2" + ], + [ + "CLBLM_LH12", + "CLBLM_LH12" + ], + [ + "CLBLM_WL1END2", + "CLBLM_WL1END2" + ], + [ + "CLBLM_SW2A2", + "CLBLM_SW2A2" + ], + [ + "CLBLM_EE4B2", + "CLBLM_EE4B2" + ], + [ + "CLBLM_EE2BEG2", + "CLBLM_EE2BEG2" + ], + [ + "CLBLM_EL1BEG2", + "CLBLM_EL1BEG2" + ], + [ + "CLBLM_LH7", + "CLBLM_LH7" + ], + [ + "CLBLM_WW2A3", + "CLBLM_WW2A3" + ], + [ + "CLBLM_SW2A1", + "CLBLM_SW2A1" + ], + [ + "CLBLM_SW4END2", + "CLBLM_SW4END2" + ], + [ + "CLBLM_LH5", + "CLBLM_LH5" + ], + [ + "CLBLM_SE2A1", + "CLBLM_SE2A1" + ], + [ + "CLBLM_NE4C1", + "CLBLM_NE4C1" + ], + [ + "CLBLM_WR1END3", + "CLBLM_WR1END3" + ], + [ + "CLBLM_NE4BEG1", + "CLBLM_NE4BEG1" + ], + [ + "CLBLM_LH2", + "CLBLM_LH2" + ], + [ + "CLBLM_WW4B3", + "CLBLM_WW4B3" + ], + [ + "CLBLM_NE4C2", + "CLBLM_NE4C2" + ], + [ + "CLBLM_SW4END1", + "CLBLM_SW4END1" + ], + [ + "CLBLM_EE2BEG0", + "CLBLM_EE2BEG0" + ], + [ + "CLBLM_EE4C1", + "CLBLM_EE4C1" + ], + [ + "CLBLM_EE4BEG1", + "CLBLM_EE4BEG1" + ], + [ + "CLBLM_WW2END2", + "CLBLM_WW2END2" + ], + [ + "CLBLM_EE4A1", + "CLBLM_EE4A1" + ], + [ + "CLBLM_SE2A0", + "CLBLM_SE2A0" + ], + [ + "CLBLM_WL1END1", + "CLBLM_WL1END1" + ], + [ + "CLBLM_WW4B2", + "CLBLM_WW4B2" + ], + [ + "CLBLM_WW4END0", + "CLBLM_WW4END0" + ], + [ + "CLBLM_SW4A3", + "CLBLM_SW4A3" + ], + [ + "CLBLM_WW2A0", + "CLBLM_WW2A0" + ], + [ + "CLBLM_EE2A1", + "CLBLM_EE2A1" + ], + [ + "CLBLM_SE4BEG1", + "CLBLM_SE4BEG1" + ], + [ + "CLBLM_WW4A3", + "CLBLM_WW4A3" + ], + [ + "CLBLM_SW2A0", + "CLBLM_SW2A0" + ], + [ + "CLBLM_EE4B0", + "CLBLM_EE4B0" + ], + [ + "CLBLM_LH6", + "CLBLM_LH6" + ], + [ + "CLBLM_NE2A3", + "CLBLM_NE2A3" + ], + [ + "CLBLM_LH3", + "CLBLM_LH3" + ], + [ + "CLBLM_SW4END0", + "CLBLM_SW4END0" + ], + [ + "CLBLM_WW4C1", + "CLBLM_WW4C1" + ], + [ + "CLBLM_NW4END2", + "CLBLM_NW4END2" + ], + [ + "CLBLM_NE4BEG0", + "CLBLM_NE4BEG0" + ], + [ + "CLBLM_NW4END0", + "CLBLM_NW4END0" + ], + [ + "CLBLM_NW4A2", + "CLBLM_NW4A2" + ], + [ + "CLBLM_WW2A1", + "CLBLM_WW2A1" + ], + [ + "CLBLM_EE4BEG0", + "CLBLM_EE4BEG0" + ], + [ + "CLBLM_NE4C3", + "CLBLM_NE4C3" + ], + [ + "CLBLM_ER1BEG3", + "CLBLM_ER1BEG3" + ], + [ + "CLBLM_WW2END3", + "CLBLM_WW2END3" + ], + [ + "CLBLM_LH9", + "CLBLM_LH9" + ], + [ + "CLBLM_SE4C0", + "CLBLM_SE4C0" + ], + [ + "CLBLM_NE4BEG3", + "CLBLM_NE4BEG3" + ], + [ + "CLBLM_WW4A0", + "CLBLM_WW4A0" + ], + [ + "CLBLM_NW2A2", + "CLBLM_NW2A2" + ], + [ + "CLBLM_EE2A3", + "CLBLM_EE2A3" + ] + ], + "tile_types": [ + "CLBLM_L", + "CLBLM_R" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLK_PMV_IMUX25_0", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_PMV_IMUX14_0", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_PMV_IMUX6_0", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_PMV_IMUX46_0", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_PMV_IMUX34_0", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_FEED_WW4B1", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_PMV_IMUX7_0", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_PMV_IMUX28_0", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_PMV_IMUX11_0", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_FEED_WL1END2", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_FEED_EE4BEG2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_FEED_LH8", + "INT_INTERFACE_LH8" + ], + [ + "CLK_PMV_IMUX8_0", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_FEED_WW4C1", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_PMV_IMUX37_0", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_PMV_IMUX19_0", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_FEED_WR1END3", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_FEED_EE4B3", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_PMV_IMUX3_0", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_PMV_FAN0_0", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_FEED_NE2A2", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_PMV_IMUX10_0", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_FEED_WL1END0", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_FEED_NE2A1", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_FEED_WW4C2", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_PMV_IMUX45_0", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_FEED_NW2A2", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_FEED_WW2A0", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_FEED_WR1END1", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_PMV_IMUX18_0", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_FEED_SE4BEG2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_PMV_BYP1_0", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_PMV_IMUX39_0", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_FEED_NW2A1", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_FEED_EE4A2", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_PMV_FAN7_0", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_PMV_IMUX17_0", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_FEED_NW2A0", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_PMV_IMUX29_0", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_FEED_WW4B2", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_FEED_WL1END1", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_PMV_IMUX35_0", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_FEED_NE2A0", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_FEED_WW4C0", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_FEED_WW4END0", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_FEED_EE4C1", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_FEED_EE4C0", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_FEED_EE4BEG0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_FEED_LH11", + "INT_INTERFACE_LH11" + ], + [ + "CLK_PMV_IMUX27_0", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_PMV_IMUX22_0", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_PMV_BYP4_0", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_FEED_WW4END2", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_FEED_SE4BEG1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_FEED_NW4A3", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_PMV_IMUX1_0", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_FEED_EE2BEG3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_FEED_SE2A2", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_FEED_EE2BEG2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_FEED_NW4A0", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_PMV_FAN5_0", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_FEED_LH5", + "INT_INTERFACE_LH5" + ], + [ + "CLK_FEED_WW2A1", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_PMV_IMUX40_0", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_FEED_WW4C3", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_FEED_WW4A2", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_FEED_SW4END1", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_FEED_EE2A2", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_PMV_BYP2_0", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_FEED_NW4END2", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_PMV_IMUX38_0", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_FEED_SW4END2", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_PMV_BYP7_0", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_PMV_BYP5_0", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_FEED_ER1BEG1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_FEED_EE4BEG3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_FEED_WW4A0", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_FEED_NE4C2", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_PMV_IMUX21_0", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_FEED_EE2A0", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_PMV_IMUX26_0", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_FEED_NE4C1", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_PMV_BYP6_0", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_FEED_SE4C2", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_FEED_SE2A1", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_PMV_IMUX43_0", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_FEED_SE4C0", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_FEED_LH1", + "INT_INTERFACE_LH1" + ], + [ + "CLK_FEED_NE4BEG3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_PMV_CTRL0_0", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_FEED_WW2END2", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_FEED_EE4B2", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_FEED_WW2END0", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_PMV_FAN1_0", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_FEED_EE4B1", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_FEED_NE2A3", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_PMV_IMUX0_0", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_PMV_IMUX9_0", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_PMV_BYP3_0", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_FEED_WW4B0", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_FEED_SW4A1", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_FEED_SE2A3", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_FEED_WW4END1", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_PMV_IMUX30_0", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_FEED_ER1BEG2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_FEED_WR1END2", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_FEED_WR1END0", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_FEED_EE2A3", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_FEED_NE4C0", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_FEED_SE4C3", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_FEED_LH9", + "INT_INTERFACE_LH9" + ], + [ + "CLK_FEED_WW4A1", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_FEED_LH3", + "INT_INTERFACE_LH3" + ], + [ + "CLK_FEED_EL1BEG3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_FEED_EE4A0", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_PMV_IMUX23_0", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_PMV_IMUX31_0", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_FEED_SW4A3", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_FEED_NW2A3", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_PMV_IMUX20_0", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_FEED_SW4END3", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_FEED_WL1END3", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_PMV_IMUX47_0", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_FEED_SE2A0", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_PMV_IMUX24_0", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_PMV_FAN3_0", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_FEED_NW4END3", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_FEED_EE2A1", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_FEED_SW4END0", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_FEED_EL1BEG2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_FEED_LH2", + "INT_INTERFACE_LH2" + ], + [ + "CLK_FEED_EE2BEG1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_PMV_IMUX15_0", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_FEED_SW2A2", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_FEED_EE4B0", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_FEED_LH6", + "INT_INTERFACE_LH6" + ], + [ + "CLK_FEED_SW2A1", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_PMV_IMUX41_0", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_FEED_SW2A0", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_FEED_EE4A3", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_FEED_EE4A1", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_FEED_EE4BEG1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_FEED_ER1BEG0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_FEED_NE4BEG1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_PMV_CLK0_0", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_PMV_FAN2_0", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_PMV_FAN4_0", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_FEED_EL1BEG0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_PMV_IMUX13_0", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_FEED_WW2END1", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_FEED_NE4BEG2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_FEED_WW4A3", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_FEED_EE2BEG0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_PMV_CLK1_0", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_PMV_LOGIC_OUTS19_0", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CLK_FEED_WW4END3", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_PMV_IMUX2_0", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_PMV_FAN6_0", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_FEED_NE4BEG0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_FEED_SW4A2", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_PMV_IMUX12_0", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_FEED_WW4B3", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_FEED_NE4C3", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_PMV_IMUX5_0", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_PMV_IMUX32_0", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_PMV_LOGIC_OUTS5_0", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CLK_PMV_IMUX42_0", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_FEED_SE4BEG0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_FEED_LH12", + "INT_INTERFACE_LH12" + ], + [ + "CLK_PMV_LOGIC_OUTS9_0", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CLK_FEED_ER1BEG3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_PMV_CTRL1_0", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_PMV_IMUX36_0", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_PMV_IMUX16_0", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_PMV_BYP0_0", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_FEED_NW4END0", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_FEED_LH4", + "INT_INTERFACE_LH4" + ], + [ + "CLK_FEED_EE4C3", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_FEED_SW2A3", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_FEED_EL1BEG1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_FEED_SW4A0", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_FEED_LH10", + "INT_INTERFACE_LH10" + ], + [ + "CLK_FEED_NW4END1", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_PMV_IMUX33_0", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_FEED_WW2A3", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_PMV_IMUX44_0", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_FEED_NW4A2", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_FEED_WW2END3", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_FEED_LH7", + "INT_INTERFACE_LH7" + ], + [ + "CLK_FEED_EE4C2", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_FEED_SE4C1", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_FEED_NW4A1", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_FEED_WW2A2", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_PMV_IMUX4_0", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_FEED_SE4BEG3", + "INT_INTERFACE_SE4BEG3" + ] + ], + "tile_types": [ + "CLK_PMV2_SVT", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLBLM_M_CIN", + "CLBLM_M_COUT_N" + ], + [ + "CLBLM_L_CIN", + "CLBLM_L_COUT_N" + ] + ], + "tile_types": [ + "CLBLM_R", + "CLBLM_R" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CMT_TOP_EL1BEG1_8", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG1_8", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NW4A0_8", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4B0_8", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_8", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW2A0_8", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW2A0_8", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4BEG2_8", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_NE4C0_8", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_ER1BEG2_8", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_8", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_LH12_8", + "VBRK_LH12" + ], + [ + "CMT_TOP_EL1BEG2_8", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_LH1_8", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH10_8", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW4B1_8", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG2_8", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW4A3_8", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4C3_8", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_NW2A0_8", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NW4END0_8", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE2A2_8", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4C1_8", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW4C2_8", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW4A1_8", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NW2A1_8", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SE4BEG0_8", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_8", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_LH3_8", + "VBRK_LH3" + ], + [ + "CMT_TOP_WR1END2_8", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A0_8", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4A2_8", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END1_8", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A0_8", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A1_8", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EL1BEG0_8", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_EE4A3_8", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C3_8", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE4A0_8", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END1_8", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH4_8", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2A0_8", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH2_8", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4C1_8", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NE2A2_8", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2A3_8", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_NW4A3_8", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4END2_8", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE2A1_8", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END2_8", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2END0_8", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2BEG0_8", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4C0_8", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG0_8", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_WR1END0_8", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_SE4C2_8", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4END1_8", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NE2A1_8", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4B3_8", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_8", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C2_8", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4B1_8", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW2A3_8", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SE4C1_8", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WR1END3_8", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW2A2_8", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C0_8", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4C1_8", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH11_8", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4B2_8", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW2A3_8", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NW4END2_8", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A0_8", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WR1END1_8", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH5_8", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END3_8", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH6_8", + "VBRK_LH6" + ], + [ + "CMT_TOP_NE4BEG3_8", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_LH8_8", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A1_8", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE2BEG2_8", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4C3_8", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NW2A2_8", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END3_8", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE2A3_8", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_ER1BEG1_8", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_8", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_NE4BEG1_8", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_WW4A2_8", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG0_8", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NE4C2_8", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SE4BEG3_8", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C0_8", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_8", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2BEG3_8", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH9_8", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE4B2_8", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_WL1END0_8", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_WW2END3_8", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EL1BEG3_8", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG3_8", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4BEG3_8", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WL1END1_8", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2A1_8", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SE4BEG2_8", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW2A3_8", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SE4C3_8", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE2A2_8", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_8", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4A1_8", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW4A2_8", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SW2A2_8", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_NW4END3_8", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SW4END1_8", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END3_8", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4BEG1_8", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4END2_8", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH7_8", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4BEG0_8", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2BEG1_8", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_8", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A3_8", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WL1END2_8", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A0_8", + "VBRK_WW4A0" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "BRAM_SW4A2_3", + "CLBLM_SW4A2" + ], + [ + "BRAM_ER1BEG2_3", + "CLBLM_ER1BEG2" + ], + [ + "BRAM_WW4B3_3", + "CLBLM_WW4B3" + ], + [ + "BRAM_NE4C1_3", + "CLBLM_NE4C1" + ], + [ + "BRAM_LH5_3", + "CLBLM_LH5" + ], + [ + "BRAM_SW2A3_3", + "CLBLM_SW2A3" + ], + [ + "BRAM_WR1END3_3", + "CLBLM_WR1END3" + ], + [ + "BRAM_WW4A0_3", + "CLBLM_WW4A0" + ], + [ + "BRAM_SW4END2_3", + "CLBLM_SW4END2" + ], + [ + "BRAM_NW4A1_3", + "CLBLM_NW4A1" + ], + [ + "BRAM_WW4C0_3", + "CLBLM_WW4C0" + ], + [ + "BRAM_NE4C2_3", + "CLBLM_NE4C2" + ], + [ + "BRAM_LH6_3", + "CLBLM_LH6" + ], + [ + "BRAM_SW4A3_3", + "CLBLM_SW4A3" + ], + [ + "BRAM_SW4A0_3", + "CLBLM_SW4A0" + ], + [ + "BRAM_SE2A0_3", + "CLBLM_SE2A0" + ], + [ + "BRAM_LH7_3", + "CLBLM_LH7" + ], + [ + "BRAM_WR1END1_3", + "CLBLM_WR1END1" + ], + [ + "BRAM_LH8_3", + "CLBLM_LH8" + ], + [ + "BRAM_EE4BEG2_3", + "CLBLM_EE4BEG2" + ], + [ + "BRAM_EE2A3_3", + "CLBLM_EE2A3" + ], + [ + "BRAM_WW4END1_3", + "CLBLM_WW4END1" + ], + [ + "BRAM_LH2_3", + "CLBLM_LH2" + ], + [ + "BRAM_EE2A2_3", + "CLBLM_EE2A2" + ], + [ + "BRAM_LH11_3", + "CLBLM_LH11" + ], + [ + "BRAM_NE4C0_3", + "CLBLM_NE4C0" + ], + [ + "BRAM_WW4B0_3", + "CLBLM_WW4B0" + ], + [ + "BRAM_EE4B0_3", + "CLBLM_EE4B0" + ], + [ + "BRAM_EE4BEG0_3", + "CLBLM_EE4BEG0" + ], + [ + "BRAM_WW4B2_3", + "CLBLM_WW4B2" + ], + [ + "BRAM_MONITOR_P_3", + "CLBLM_MONITOR_P" + ], + [ + "BRAM_LH3_3", + "CLBLM_LH3" + ], + [ + "BRAM_WW2END3_3", + "CLBLM_WW2END3" + ], + [ + "BRAM_WW4A2_3", + "CLBLM_WW4A2" + ], + [ + "BRAM_EL1BEG0_3", + "CLBLM_EL1BEG0" + ], + [ + "BRAM_NE2A2_3", + "CLBLM_NE2A2" + ], + [ + "BRAM_WW4A3_3", + "CLBLM_WW4A3" + ], + [ + "BRAM_SW2A2_3", + "CLBLM_SW2A2" + ], + [ + "BRAM_LH12_3", + "CLBLM_LH12" + ], + [ + "BRAM_EL1BEG2_3", + "CLBLM_EL1BEG2" + ], + [ + "BRAM_SE4BEG3_3", + "CLBLM_SE4BEG3" + ], + [ + "BRAM_WW2A2_3", + "CLBLM_WW2A2" + ], + [ + "BRAM_WW4C1_3", + "CLBLM_WW4C1" + ], + [ + "BRAM_NE2A0_3", + "CLBLM_NE2A0" + ], + [ + "BRAM_EE4B2_3", + "CLBLM_EE4B2" + ], + [ + "BRAM_NE2A3_3", + "CLBLM_NE2A3" + ], + [ + "BRAM_SW2A0_3", + "CLBLM_SW2A0" + ], + [ + "BRAM_LH10_3", + "CLBLM_LH10" + ], + [ + "BRAM_SE2A1_3", + "CLBLM_SE2A1" + ], + [ + "BRAM_NE4BEG3_3", + "CLBLM_NE4BEG3" + ], + [ + "BRAM_EE2A1_3", + "CLBLM_EE2A1" + ], + [ + "BRAM_NW2A2_3", + "CLBLM_NW2A2" + ], + [ + "BRAM_NW4END2_3", + "CLBLM_NW4END2" + ], + [ + "BRAM_ER1BEG1_3", + "CLBLM_ER1BEG1" + ], + [ + "BRAM_NW4END3_3", + "CLBLM_NW4END3" + ], + [ + "BRAM_EE4A1_3", + "CLBLM_EE4A1" + ], + [ + "BRAM_NE4C3_3", + "CLBLM_NE4C3" + ], + [ + "BRAM_EE4A2_3", + "CLBLM_EE4A2" + ], + [ + "BRAM_EE2A0_3", + "CLBLM_EE2A0" + ], + [ + "BRAM_NW4A2_3", + "CLBLM_NW4A2" + ], + [ + "BRAM_WW4C3_3", + "CLBLM_WW4C3" + ], + [ + "BRAM_WW2END2_3", + "CLBLM_WW2END2" + ], + [ + "BRAM_NE2A1_3", + "CLBLM_NE2A1" + ], + [ + "BRAM_NW4A3_3", + "CLBLM_NW4A3" + ], + [ + "BRAM_EE4C2_3", + "CLBLM_EE4C2" + ], + [ + "BRAM_SW4A1_3", + "CLBLM_SW4A1" + ], + [ + "BRAM_EL1BEG3_3", + "CLBLM_EL1BEG3" + ], + [ + "BRAM_ER1BEG3_3", + "CLBLM_ER1BEG3" + ], + [ + "BRAM_WL1END3_3", + "CLBLM_WL1END3" + ], + [ + "BRAM_WL1END2_3", + "CLBLM_WL1END2" + ], + [ + "BRAM_NE4BEG0_3", + "CLBLM_NE4BEG0" + ], + [ + "BRAM_WW2END1_3", + "CLBLM_WW2END1" + ], + [ + "BRAM_WW4END2_3", + "CLBLM_WW4END2" + ], + [ + "BRAM_LH9_3", + "CLBLM_LH9" + ], + [ + "BRAM_EE4BEG3_3", + "CLBLM_EE4BEG3" + ], + [ + "BRAM_WW4C2_3", + "CLBLM_WW4C2" + ], + [ + "BRAM_WW4A1_3", + "CLBLM_WW4A1" + ], + [ + "BRAM_SE2A3_3", + "CLBLM_SE2A3" + ], + [ + "BRAM_EE2BEG0_3", + "CLBLM_EE2BEG0" + ], + [ + "BRAM_SW4END3_3", + "CLBLM_SW4END3" + ], + [ + "BRAM_EE2BEG1_3", + "CLBLM_EE2BEG1" + ], + [ + "BRAM_SE4C1_3", + "CLBLM_SE4C1" + ], + [ + "BRAM_NW2A3_3", + "CLBLM_NW2A3" + ], + [ + "BRAM_EE4BEG1_3", + "CLBLM_EE4BEG1" + ], + [ + "BRAM_EE2BEG3_3", + "CLBLM_EE2BEG3" + ], + [ + "BRAM_LH1_3", + "CLBLM_LH1" + ], + [ + "BRAM_SE4BEG0_3", + "CLBLM_SE4BEG0" + ], + [ + "BRAM_SE4C0_3", + "CLBLM_SE4C0" + ], + [ + "BRAM_WW2A0_3", + "CLBLM_WW2A0" + ], + [ + "BRAM_MONITOR_N_3", + "CLBLM_MONITOR_N" + ], + [ + "BRAM_WL1END1_3", + "CLBLM_WL1END1" + ], + [ + "BRAM_SW4END1_3", + "CLBLM_SW4END1" + ], + [ + "BRAM_WL1END0_3", + "CLBLM_WL1END0" + ], + [ + "BRAM_NW2A1_3", + "CLBLM_NW2A1" + ], + [ + "BRAM_NW4END0_3", + "CLBLM_NW4END0" + ], + [ + "BRAM_LH4_3", + "CLBLM_LH4" + ], + [ + "BRAM_WW2END0_3", + "CLBLM_WW2END0" + ], + [ + "BRAM_SE4C2_3", + "CLBLM_SE4C2" + ], + [ + "BRAM_ER1BEG0_3", + "CLBLM_ER1BEG0" + ], + [ + "BRAM_EE4B1_3", + "CLBLM_EE4B1" + ], + [ + "BRAM_EE4A3_3", + "CLBLM_EE4A3" + ], + [ + "BRAM_NW4A0_3", + "CLBLM_NW4A0" + ], + [ + "BRAM_WW2A3_3", + "CLBLM_WW2A3" + ], + [ + "BRAM_WR1END0_3", + "CLBLM_WR1END0" + ], + [ + "BRAM_EE4C1_3", + "CLBLM_EE4C1" + ], + [ + "BRAM_WW4END3_3", + "CLBLM_WW4END3" + ], + [ + "BRAM_NW2A0_3", + "CLBLM_NW2A0" + ], + [ + "BRAM_EE4C3_3", + "CLBLM_EE4C3" + ], + [ + "BRAM_NE4BEG1_3", + "CLBLM_NE4BEG1" + ], + [ + "BRAM_SW4END0_3", + "CLBLM_SW4END0" + ], + [ + "BRAM_NE4BEG2_3", + "CLBLM_NE4BEG2" + ], + [ + "BRAM_EE2BEG2_3", + "CLBLM_EE2BEG2" + ], + [ + "BRAM_EL1BEG1_3", + "CLBLM_EL1BEG1" + ], + [ + "BRAM_WW2A1_3", + "CLBLM_WW2A1" + ], + [ + "BRAM_EE4A0_3", + "CLBLM_EE4A0" + ], + [ + "BRAM_SE2A2_3", + "CLBLM_SE2A2" + ], + [ + "BRAM_EE4C0_3", + "CLBLM_EE4C0" + ], + [ + "BRAM_NW4END1_3", + "CLBLM_NW4END1" + ], + [ + "BRAM_WR1END2_3", + "CLBLM_WR1END2" + ], + [ + "BRAM_SE4BEG2_3", + "CLBLM_SE4BEG2" + ], + [ + "BRAM_EE4B3_3", + "CLBLM_EE4B3" + ], + [ + "BRAM_SW2A1_3", + "CLBLM_SW2A1" + ], + [ + "BRAM_SE4BEG1_3", + "CLBLM_SE4BEG1" + ], + [ + "BRAM_SE4C3_3", + "CLBLM_SE4C3" + ], + [ + "BRAM_WW4B1_3", + "CLBLM_WW4B1" + ], + [ + "BRAM_WW4END0_3", + "CLBLM_WW4END0" + ] + ], + "tile_types": [ + "BRAM_L", + "CLBLM_R" + ] + }, + { + "grid_deltas": [ + 1, + 8 + ], + "wire_pairs": [ + [ + "CFG_CENTER_NE4BEG0_3", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_NE4C0_3", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_BYP5_3", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_IMUX25_3", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_NW2A1_3", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_SW2A3_3", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_CTRL1_3", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_SW2A0_3", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_SW4END0_3", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_WW4B3_3", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_SE4C3_3", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_NE4BEG1_3", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX46_3", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_EL1BEG2_3", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NE2A0_3", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_WL1END2_3", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_NW4A1_3", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SW4END2_3", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_NW2A3_3", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_EE4C0_3", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_WW4C0_3", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_NW2A0_3", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_NE4C2_3", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_WR1END2_3", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SW2A1_3", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WW2A2_3", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_IMUX9_3", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_EE4A1_3", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX4_3", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_EE4B1_3", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_EL1BEG0_3", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_FAN1_3", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX14_3", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_WW4END3_3", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_EE4C3_3", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_SW2A2_3", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_BYP4_3", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_EE2BEG0_3", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX3_3", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_BYP0_3", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_LH3_3", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_3", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_IMUX33_3", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_IMUX40_3", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_EE2BEG2_3", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_CLK1_3", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX41_3", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_NW4END2_3", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B10_3", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "CFG_CENTER_EE4B0_3", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_NW4END1_3", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_IMUX28_3", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_SE4BEG0_3", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_3", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_IMUX30_3", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_LH12_3", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_SW4END3_3", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX2_3", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_SE2A0_3", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_EE2BEG3_3", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_WR1END3_3", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_3", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_EE4A3_3", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_LH2_3", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX12_3", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_FAN3_3", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_FAN2_3", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_IMUX45_3", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_LH10_3", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW2END1_3", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_3", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_IMUX7_3", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_IMUX39_3", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_SE4C2_3", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_EE4B3_3", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_NE2A2_3", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE4A2_3", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX31_3", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_CLK0_3", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX32_3", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_3", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_LH11_3", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_SE2A1_3", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_EE4C2_3", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX6_3", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX42_3", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_WR1END1_3", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_IMUX18_3", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_WW4A2_3", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_NE2A3_3", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX17_3", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_3", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_LH8_3", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_WW4B2_3", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_NW4A3_3", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SW4A3_3", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_IMUX8_3", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_IMUX19_3", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_FAN4_3", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW2END3_3", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_EE2A1_3", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_EE4BEG0_3", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_EE4BEG1_3", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_EL1BEG1_3", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_BYP7_3", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_EE4A0_3", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_NE4C3_3", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_3", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_WW4B0_3", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_WL1END0_3", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_WR1END0_3", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_NW4END0_3", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_WL1END3_3", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_IMUX35_3", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_ER1BEG2_3", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX11_3", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_WL1END1_3", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_BYP3_3", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_LH9_3", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_IMUX16_3", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_SE4C1_3", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_FAN7_3", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_3", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_IMUX23_3", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NW4A2_3", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_SE4C0_3", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_LH5_3", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX47_3", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX37_3", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_IMUX10_3", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SW4A0_3", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_FAN5_3", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_WW4C3_3", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX22_3", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW4C2_3", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX1_3", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX13_3", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_WW4A1_3", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_NE4C1_3", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_LH1_3", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NE2A1_3", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_SE4BEG1_3", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_FAN6_3", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_CTRL0_3", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_EE2A0_3", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WW2A0_3", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_SE4BEG2_3", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE2A3_3", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B11_3", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "CFG_CENTER_SE4BEG3_3", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX5_3", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WW2A1_3", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_WW4END2_3", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_FAN0_3", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX0_3", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_ER1BEG3_3", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_LH4_3", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_LH6_3", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX29_3", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_ER1BEG1_3", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SW4END1_3", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_SE2A2_3", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_BYP2_3", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_NW4A0_3", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B8_3", + "VFRAME_LOGIC_OUTS_B8" + ], + [ + "CFG_CENTER_NE4BEG2_3", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_NE4BEG3_3", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_WW4A0_3", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX21_3", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_LH7_3", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_IMUX44_3", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_3", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_EL1BEG3_3", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW2END2_3", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_EE4BEG2_3", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE2BEG1_3", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX43_3", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_WW4END1_3", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_EE4C1_3", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX15_3", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_IMUX24_3", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_SE2A3_3", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SW4A1_3", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_EE2A2_3", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_EE4B2_3", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_BYP1_3", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW4B1_3", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_IMUX38_3", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_NW4END3_3", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_3", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_EE4BEG3_3", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_WW4END0_3", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B9_3", + "VFRAME_LOGIC_OUTS_B9" + ], + [ + "CFG_CENTER_IMUX36_3", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_ER1BEG0_3", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_3", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_WW2END0_3", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WW4C1_3", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_IMUX34_3", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_WW4A3_3", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_NW2A2_3", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW2A3_3", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_3", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_IMUX27_3", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_BYP6_3", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX26_3", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX20_3", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SW4A2_3", + "VFRAME_SW4A2" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_BRAM_CK_IN1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_BRAM_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_BRAM_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_BRAM_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_BRAM_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_BRAM_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_BRAM_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "HCLK_BRAM_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_BRAM_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "HCLK_BRAM_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_BRAM_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ], + [ + "HCLK_BRAM_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "HCLK_BRAM_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_BRAM_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ] + ], + "tile_types": [ + "HCLK_BRAM", + "HCLK_INT_INTERFACE" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH3_4", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH4_4", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH12_4", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH11_4", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH9_4", + "VBRK_LH9" + ], + [ + "CMT_TOP_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH1_4", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_LH10_4", + "VBRK_LH10" + ], + [ + "CMT_TOP_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH2_4", + "VBRK_LH2" + ], + [ + "CMT_TOP_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_LH8_4", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH7_4", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_4", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH6_4", + "VBRK_LH6" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "GTXE2_BYP3_1", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX31_1", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX35_1", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX17_1", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX28_1", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_FAN7_1", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX21_1", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_FAN6_1", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX12_1", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B18_1", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX40_1", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B14_1", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX8_1", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX0_1", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX6_1", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX44_1", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_FAN3_1", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX7_1", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX37_1", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_BYP6_1", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX10_1", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX20_1", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN1_1", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_1", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B6_1", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_FAN2_1", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX41_1", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B13_1", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_CLK0_1", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX5_1", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX24_1", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_CLK1_1", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_CTRL0_1", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_CTRL1_1", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX9_1", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_LOGIC_OUTS_B16_1", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX34_1", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_LOGIC_OUTS_B3_1", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX45_1", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX43_1", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX19_1", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_LOGIC_OUTS_B4_1", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B1_1", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX29_1", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_BYP1_1", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX15_1", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_LOGIC_OUTS_B15_1", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX39_1", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B17_1", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX27_1", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B10_1", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX47_1", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX46_1", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX36_1", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_LOGIC_OUTS_B2_1", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_FAN5_1", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_BYP0_1", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_FAN4_1", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_BYP5_1", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX3_1", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX22_1", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX38_1", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_LOGIC_OUTS_B0_1", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_LOGIC_OUTS_B5_1", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX30_1", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_BYP4_1", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX42_1", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX13_1", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP7_1", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX25_1", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B9_1", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX18_1", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_LOGIC_OUTS_B7_1", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_IMUX32_1", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN0_1", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_LOGIC_OUTS_B22_1", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B20_1", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_LOGIC_OUTS_B11_1", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_LOGIC_OUTS_B8_1", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_BYP2_1", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX26_1", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX33_1", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX2_1", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX11_1", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX16_1", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX4_1", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX23_1", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX14_1", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX1_1", + "VBRK_EXT_IMUX1" + ] + ], + "tile_types": [ + "GTX_CHANNEL_3", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + 3 + ], + "wire_pairs": [ + [ + "CLK_HROW_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_LH2_1", + "VBRK_LH2" + ], + [ + "CLK_HROW_LH4_1", + "VBRK_LH4" + ], + [ + "CLK_HROW_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_LH10_1", + "VBRK_LH10" + ], + [ + "CLK_HROW_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_LH3_1", + "VBRK_LH3" + ], + [ + "CLK_HROW_LH9_1", + "VBRK_LH9" + ], + [ + "CLK_HROW_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_LH7_1", + "VBRK_LH7" + ], + [ + "CLK_HROW_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_LH11_1", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH12_1", + "VBRK_LH12" + ], + [ + "CLK_HROW_LH8_1", + "VBRK_LH8" + ], + [ + "CLK_HROW_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_LH5_1", + "VBRK_LH5" + ], + [ + "CLK_HROW_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_LH1_1", + "VBRK_LH1" + ], + [ + "CLK_HROW_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_LH6_1", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_WW2END2_1", + "VBRK_WW2END2" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "SE6B3", + "SE6C3" + ], + [ + "SS6D3", + "SS6E3" + ], + [ + "NN6A1", + "NN6BEG1" + ], + [ + "SW6A1", + "SW6B1" + ], + [ + "FAN_BOUNCE2", + "FAN_BOUNCE_S3_2" + ], + [ + "SW6D1", + "SW6E1" + ], + [ + "SW6B1", + "SW6C1" + ], + [ + "SE6D2", + "SE6E2" + ], + [ + "SW6C0", + "SW6D0" + ], + [ + "WW4END0", + "WW4END_S0_0" + ], + [ + "SS6E0", + "SS6END0" + ], + [ + "SR1BEG2", + "SR1END2" + ], + [ + "SW6B0", + "SW6C0" + ], + [ + "GCLK_L_B11", + "GCLK_L_B11" + ], + [ + "SS6E1", + "SS6END1" + ], + [ + "NE2A2", + "NE2BEG2" + ], + [ + "WR1BEG0", + "WR1BEG_S0" + ], + [ + "NW2A3", + "NW2BEG3" + ], + [ + "SW6D2", + "SW6E2" + ], + [ + "SS6C1", + "SS6D1" + ], + [ + "NN2A0", + "NN2BEG0" + ], + [ + "SS6E2", + "SS6END2" + ], + [ + "SE6D0", + "SE6E0" + ], + [ + "GCLK_L_B6", + "GCLK_L_B6" + ], + [ + "SW6D0", + "SW6E0" + ], + [ + "NN6A2", + "NN6BEG2" + ], + [ + "SS6B2", + "SS6C2" + ], + [ + "GCLK_L_B9", + "GCLK_L_B9" + ], + [ + "SS2A1", + "SS2END1" + ], + [ + "SE6A3", + "SE6B3" + ], + [ + "SS6C0", + "SS6D0" + ], + [ + "SE6A0", + "SE6B0" + ], + [ + "SS2A3", + "SS2END3" + ], + [ + "SE6C2", + "SE6D2" + ], + [ + "SE6D1", + "SE6E1" + ], + [ + "SE6B0", + "SE6C0" + ], + [ + "NN2A1", + "NN2BEG1" + ], + [ + "NN2A2", + "NN2BEG2" + ], + [ + "NW2A2", + "NW2BEG2" + ], + [ + "SE6C0", + "SE6D0" + ], + [ + "SW6A3", + "SW6B3" + ], + [ + "SW6B2", + "SW6C2" + ], + [ + "GCLK_L_B10", + "GCLK_L_B10" + ], + [ + "NE2END0", + "NE2END_S3_0" + ], + [ + "SS6C2", + "SS6D2" + ], + [ + "NE2A0", + "NE2BEG0" + ], + [ + "NW6END0", + "NW6END_S0_0" + ], + [ + "NE2A1", + "NE2BEG1" + ], + [ + "SW6C1", + "SW6D1" + ], + [ + "FAN_BOUNCE6", + "FAN_BOUNCE_S3_6" + ], + [ + "NN2END0", + "NN2END_S2_0" + ], + [ + "GCLK_L_B7", + "GCLK_L_B7" + ], + [ + "SS6A1", + "SS6B1" + ], + [ + "SW6A0", + "SW6B0" + ], + [ + "SW6A2", + "SW6B2" + ], + [ + "LV_L10", + "LV_L9" + ], + [ + "SS6B3", + "SS6C3" + ], + [ + "SE6D3", + "SE6E3" + ], + [ + "SL1BEG1", + "SL1END1" + ], + [ + "EL1END0", + "EL1END_S3_0" + ], + [ + "NE2A3", + "NE2BEG3" + ], + [ + "SS6D0", + "SS6E0" + ], + [ + "NN2A3", + "NN2BEG3" + ], + [ + "SW6C3", + "SW6D3" + ], + [ + "FAN_BOUNCE0", + "FAN_BOUNCE_S3_0" + ], + [ + "SS6C3", + "SS6D3" + ], + [ + "SS6E3", + "SS6END3" + ], + [ + "SW6C2", + "SW6D2" + ], + [ + "SS6B1", + "SS6C1" + ], + [ + "GCLK_L_B8", + "GCLK_L_B8" + ], + [ + "NW2A1", + "NW2BEG1" + ], + [ + "SS6B0", + "SS6C0" + ], + [ + "NN6END0", + "NN6END_S1_0" + ], + [ + "NN6A3", + "NN6BEG3" + ], + [ + "SS2A2", + "SS2END2" + ], + [ + "SW6B3", + "SW6C3" + ], + [ + "SS6A3", + "SS6B3" + ], + [ + "SS6D2", + "SS6E2" + ], + [ + "SE6B2", + "SE6C2" + ], + [ + "SE6A2", + "SE6B2" + ], + [ + "SE6C3", + "SE6D3" + ], + [ + "SL1BEG0", + "SL1END0" + ], + [ + "ER1BEG0", + "ER1BEG_S0" + ], + [ + "SR1BEG3", + "SR1END3" + ], + [ + "SL1BEG3", + "SL1END3" + ], + [ + "SR1BEG1", + "SR1END1" + ], + [ + "SE6B1", + "SE6C1" + ], + [ + "NN6A0", + "NN6BEG0" + ], + [ + "SW6D3", + "SW6E3" + ], + [ + "SS2A0", + "SS2END0" + ], + [ + "SE6C1", + "SE6D1" + ], + [ + "LVB_L10", + "LVB_L9" + ], + [ + "SE6A1", + "SE6B1" + ], + [ + "NW2A0", + "NW2BEG0" + ], + [ + "NL1END0", + "NL1END_S3_0" + ], + [ + "WR1END0", + "WR1END_S1_0" + ], + [ + "FAN_BOUNCE4", + "FAN_BOUNCE_S3_4" + ], + [ + "SS6D1", + "SS6E1" + ], + [ + "SS6A0", + "SS6B0" + ], + [ + "SL1BEG2", + "SL1END2" + ], + [ + "SS6A2", + "SS6B2" + ], + [ + "NW2END0", + "NW2END_S0_0" + ] + ], + "tile_types": [ + "INT_L", + "INT_L" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "CLK_HROW_SE2A0_2", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_WW2A0_2", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4C1_2", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_EE4BEG0_2", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_IMUX22_2", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_SE2A1_2", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_IMUX16_2", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_NE4BEG3_2", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_IMUX2_2", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_WW4END3_2", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_SW2A1_2", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_IMUX39_2", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_EE4A2_2", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_WW4B0_2", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_IMUX10_2", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_EE4C2_2", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_NW2A2_2", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_IMUX21_2", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_LH8_2", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_IMUX31_2", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_EE4B1_2", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_WL1END2_2", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_SE4BEG1_2", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_IMUX19_2", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_NW4A3_2", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WW2END2_2", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_IMUX25_2", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_IMUX24_2", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_WW4END1_2", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_LH12_2", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_EE2BEG3_2", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_IMUX35_2", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_IMUX23_2", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_IMUX8_2", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_IMUX26_2", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_NE4C0_2", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_WW4B2_2", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_SE4C2_2", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_SW4END3_2", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_FAN7_2", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_IMUX5_2", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_IMUX4_2", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_IMUX20_2", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_NW4END3_2", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_LH10_2", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_IMUX15_2", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_SW4END1_2", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_WW2A3_2", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_BYP4_2", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_FAN2_2", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_LH1_2", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_NE2A3_2", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_BYP0_2", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_EE4BEG2_2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_WW4B3_2", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_WR1END2_2", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_ER1BEG3_2", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_BYP5_2", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_SW4END0_2", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_SE4C0_2", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_NE4BEG2_2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_LH2_2", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_IMUX13_2", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_WW4END2_2", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_NW4END0_2", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_NW4A1_2", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_WW4C3_2", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_MONITOR_N_2", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_HROW_IMUX45_2", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_BYP1_2", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_NE2A1_2", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_ER1BEG1_2", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_SE2A2_2", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_EL1BEG1_2", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_NW2A0_2", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_SW2A2_2", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_IMUX44_2", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_EE4A1_2", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_IMUX0_2", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_NE4BEG1_2", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_IMUX27_2", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_IMUX43_2", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_WW4B1_2", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_NE2A2_2", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_SE4BEG2_2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_WW4A0_2", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_WW2END3_2", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_IMUX28_2", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_BYP7_2", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_WW4A3_2", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_SW4END2_2", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_WW2END0_2", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_EE2BEG2_2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_NW4A2_2", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_WW4A1_2", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_IMUX29_2", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_BYP3_2", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_IMUX46_2", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_LH6_2", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_NW2A3_2", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_EE2A1_2", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_IMUX11_2", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_LH9_2", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_EE4BEG1_2", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_WR1END3_2", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_WL1END0_2", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_CLK0_2", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_IMUX32_2", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_FAN5_2", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_WR1END1_2", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_WW4C0_2", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_IMUX37_2", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_SE4C3_2", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_IMUX33_2", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_LH3_2", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_WW2A1_2", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_NW4END1_2", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_IMUX12_2", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_SE4C1_2", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_CTRL0_2", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_FAN1_2", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_EL1BEG0_2", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_NE4C1_2", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_BYP6_2", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_IMUX41_2", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_NE4BEG0_2", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_FAN6_2", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_SW2A3_2", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_IMUX17_2", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_EL1BEG3_2", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_MONITOR_P_2", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_HROW_BYP2_2", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_SW4A1_2", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_WW4C1_2", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_NW2A1_2", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_LH11_2", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_NE4C3_2", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_IMUX1_2", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_SW4A3_2", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_IMUX36_2", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_EE2A2_2", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_FAN3_2", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_SW2A0_2", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE2A0_2", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_SW4A0_2", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_WW4END0_2", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_LH7_2", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_SE4BEG0_2", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_EE2A3_2", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_IMUX47_2", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_SE4BEG3_2", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_WW2END1_2", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_IMUX30_2", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_EE4B3_2", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_EE2BEG0_2", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_IMUX3_2", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_CTRL1_2", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_EE4A0_2", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_IMUX7_2", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_NW4END2_2", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_SE2A3_2", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_IMUX40_2", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_FAN4_2", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_EE2BEG1_2", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_IMUX14_2", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_NE2A0_2", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_IMUX6_2", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_EE4BEG3_2", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_IMUX18_2", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_WR1END0_2", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_ER1BEG0_2", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_WW4A2_2", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_SW4A2_2", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_WW2A2_2", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_EE4C0_2", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_CLK1_2", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_EE4B2_2", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_EL1BEG2_2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_WW4C2_2", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_EE4A3_2", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_EE4B0_2", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_FAN0_2", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_IMUX42_2", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_IMUX9_2", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_ER1BEG2_2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_IMUX34_2", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_WL1END3_2", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_WL1END1_2", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_NE4C2_2", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_LH4_2", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_NW4A0_2", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_LH5_2", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_EE4C3_2", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_IMUX38_2", + "INT_INTERFACE_IMUX38" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + -9 + ], + "wire_pairs": [ + [ + "CMT_R_LOWER_B_CLK_PERF3", + "CMT_LR_LOWER_T_CLK_PERF3" + ], + [ + "CMT_MMCM_PHASER_OUT_B_OCLK", + "CMT_PHASER_B_TOMMCM_OCLK" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM3", + "CMT_LR_LOWER_T_CLK_MMCM3" + ], + [ + "CMT_MMCM_PHASERREF0", + "CMT_PHASER_DOWN_PHASERREF0" + ], + [ + "CMT_R_LOWER_B_CLK_IN3_HCLK", + "CMT_LR_LOWER_T_CLK_IN3_HCLK" + ], + [ + "CMT_MMCM_PHASERREF_ABOVE1", + "CMT_PHASER_DOWN_PHASERREF_ABOVE1" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM11", + "CMT_LR_LOWER_T_CLK_MMCM11" + ], + [ + "MMCM_CLK_FREQ_BB_NS0", + "MMCM_CLK_FREQBB_REBUFOUT0" + ], + [ + "CMT_MMCM_PHASERA_DQSBUS1", + "CMT_PHASERA_DQSBUS1" + ], + [ + "CMT_MMCM_PHASER_IN_B_ICLK", + "CMT_PHASER_B_TOMMCM_ICLK" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM10", + "CMT_LR_LOWER_T_CLK_MMCM10" + ], + [ + "CMT_MMCM_A_WREN_TOFIFO", + "CMT_PHASER_IN_A_WREN_TOFIFO" + ], + [ + "CMT_R_LOWER_B_CLK_IN2_HCLK", + "CMT_LR_LOWER_T_CLK_IN2_HCLK" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM6", + "CMT_LR_LOWER_T_CLK_MMCM6" + ], + [ + "MMCMOUT_CLK_FREQ_BB_1", + "MMCMOUT_CLK_FREQ_BB_REBUFIN1" + ], + [ + "MMCMOUT_CLK_FREQ_BB_2", + "MMCMOUT_CLK_FREQ_BB_REBUFIN2" + ], + [ + "CMT_MMCM_A_RDEN_TOFIFO", + "CMT_PHASER_OUT_A_RDEN_TOFIFO" + ], + [ + "CMT_MMCM_PHASERA_DQSBUS0", + "CMT_PHASERA_DQSBUS0" + ], + [ + "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "CMT_PHASER_B_TOMMCM_ICLKDIV" + ], + [ + "MMCMOUT_CLK_FREQ_BB_3", + "MMCMOUT_CLK_FREQ_BB_REBUFIN3" + ], + [ + "CMT_MMCM_A_WRCLK_TOFIFO", + "CMT_PHASER_IN_A_WRCLK_TOFIFO" + ], + [ + "CMT_MMCM_PHASER_IN_A_ICLKDIV", + "CMT_PHASER_IN_A_ICLKDIV" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM8", + "CMT_LR_LOWER_T_CLK_MMCM8" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM2", + "CMT_LR_LOWER_T_CLK_MMCM2" + ], + [ + "CMT_MMCM_PHASERA_CTSBUS0", + "CMT_PHASERA_CTSBUS0" + ], + [ + "MMCM_CLK_FREQ_BB_NS1", + "MMCM_CLK_FREQBB_REBUFOUT1" + ], + [ + "CMT_MMCM_PHASERREF_ABOVE0", + "CMT_PHASER_DOWN_PHASERREF_ABOVE0" + ], + [ + "CMT_R_LOWER_B_CLK_IN1_HCLK", + "CMT_LR_LOWER_T_CLK_IN1_HCLK" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM9", + "CMT_LR_LOWER_T_CLK_MMCM9" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM12", + "CMT_LR_LOWER_T_CLK_MMCM12" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM1", + "CMT_LR_LOWER_T_CLK_MMCM1" + ], + [ + "CMT_R_LOWER_B_CLK_PERF2", + "CMT_LR_LOWER_T_CLK_PERF2" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM13", + "CMT_LR_LOWER_T_CLK_MMCM13" + ], + [ + "CMT_MMCM_PHASER_OUT_A_OCLKDIV", + "CMT_PHASER_OUT_A_OCLKDIV" + ], + [ + "CMT_MMCM_PHASERREF1", + "CMT_PHASER_DOWN_PHASERREF1" + ], + [ + "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "CMT_PHASER_B_TOMMCM_OCLKDIV" + ], + [ + "MMCM_CLK_FREQ_BB_NS2", + "MMCM_CLK_FREQBB_REBUFOUT2" + ], + [ + "CMT_MMCM_PHASER_OUT_A_OCLK", + "CMT_PHASER_OUT_A_OCLK" + ], + [ + "CMT_MMCM_PHASER_IN_A_ICLK", + "CMT_PHASER_IN_A_ICLK" + ], + [ + "CMT_MMCM_PHASERA_DTSBUS0", + "CMT_PHASERA_DTSBUS0" + ], + [ + "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", + "CMT_PHASER_OUT_A_OCLK1X_90" + ], + [ + "CMT_MMCM_PHYCTRL_SYNC_BB_UP", + "CMT_PHASER_BOT_SYNC_BB" + ], + [ + "CMT_MMCM_PHASERA_CTSBUS1", + "CMT_PHASERA_CTSBUS1" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM4", + "CMT_LR_LOWER_T_CLK_MMCM4" + ], + [ + "CMT_MMCM_PHASERREF_BELOW1", + "CMT_PHASER_DOWN_PHASERREF_BELOW1" + ], + [ + "MMCM_CLK_FREQ_BB_NS3", + "MMCM_CLK_FREQBB_REBUFOUT3" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM0", + "CMT_LR_LOWER_T_CLK_MMCM0" + ], + [ + "MMCMOUT_CLK_FREQ_BB_0", + "MMCMOUT_CLK_FREQ_BB_REBUFIN0" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM5", + "CMT_LR_LOWER_T_CLK_MMCM5" + ], + [ + "CMT_MMCM_PHASERA_DTSBUS1", + "CMT_PHASERA_DTSBUS1" + ], + [ + "CMT_R_LOWER_B_CLK_PERF0", + "CMT_LR_LOWER_T_CLK_PERF0" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM7", + "CMT_LR_LOWER_T_CLK_MMCM7" + ], + [ + "CMT_MMCM_PHASERREF_BELOW0", + "CMT_PHASER_DOWN_PHASERREF_BELOW0" + ], + [ + "CMT_MMCM_A_RDCLK_TOFIFO", + "CMT_PHASER_OUT_A_RDCLK_TOFIFO" + ], + [ + "CMT_R_LOWER_B_CLK_PERF1", + "CMT_LR_LOWER_T_CLK_PERF1" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "CMT_TOP_R_LOWER_T" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "CMT_TOP_ER1BEG2_12", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WR1END0_12", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4C0_12", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WW4END0_12", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_LH10_12", + "VBRK_LH10" + ], + [ + "CMT_TOP_NE4BEG2_12", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_NW4END3_12", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4BEG3_12", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH1_12", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A1_12", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SE4BEG1_12", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NE4BEG1_12", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_NW4A3_12", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE2BEG3_12", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WL1END2_12", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE2BEG2_12", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW4B2_12", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_SW4END1_12", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG1_12", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4C0_12", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SW2A2_12", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4B0_12", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE4C2_12", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_LH2_12", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4B1_12", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4C3_12", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE4C0_12", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_LH7_12", + "VBRK_LH7" + ], + [ + "CMT_TOP_NE2A0_12", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4A0_12", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WR1END2_12", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW4END1_12", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4BEG3_12", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW2A1_12", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4END2_12", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_SE2A0_12", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW4A1_12", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SE4C1_12", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE2A1_12", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4B1_12", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_EE4C3_12", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4BEG1_12", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_12", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_WR1END3_12", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE2BEG0_12", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EL1BEG2_12", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4A1_12", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW4C2_12", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW4A2_12", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_LH3_12", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE2A3_12", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW2END2_12", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_ER1BEG0_12", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END3_12", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EL1BEG0_12", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_WW2END0_12", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2END1_12", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW2A2_12", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_WL1END3_12", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_EE4BEG2_12", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW4END2_12", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE4C2_12", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4A2_12", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG0_12", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4END3_12", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NW2A2_12", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A3_12", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_SW4A0_12", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_LH11_12", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE2A0_12", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH4_12", + "VBRK_LH4" + ], + [ + "CMT_TOP_SW2A3_12", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4A0_12", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EL1BEG3_12", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE4B3_12", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4A1_12", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_LH5_12", + "VBRK_LH5" + ], + [ + "CMT_TOP_NW2A3_12", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C3_12", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_NE4C2_12", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SW2A1_12", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH9_12", + "VBRK_LH9" + ], + [ + "CMT_TOP_NW2A0_12", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_EE2A3_12", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW2A0_12", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4BEG3_12", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EE4B2_12", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_NW4END1_12", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A1_12", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NE4C3_12", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_ER1BEG1_12", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2A2_12", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WR1END1_12", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A2_12", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2BEG1_12", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SE2A2_12", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_NE4C1_12", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_SW4END0_12", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_LH12_12", + "VBRK_LH12" + ], + [ + "CMT_TOP_WL1END1_12", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_ER1BEG3_12", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4A3_12", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_WW4B3_12", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4C1_12", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2A3_12", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_LH6_12", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A3_12", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH8_12", + "VBRK_LH8" + ], + [ + "CMT_TOP_SE2A1_12", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4A2_12", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4B0_12", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_NW4A0_12", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_SW4END2_12", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE2A1_12", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_WW2END3_12", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SE2A3_12", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4C1_12", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NE4BEG0_12", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE4BEG2_12", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW4A2_12", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NE4C0_12", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WL1END0_12", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_WW2A0_12", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END0_12", + "VBRK_NW4END0" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 7 + ], + "wire_pairs": [ + [ + "CMT_TOP_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_LH2_1", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH11_1", + "VBRK_LH11" + ], + [ + "CMT_TOP_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH10_1", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_LH8_1", + "VBRK_LH8" + ], + [ + "CMT_TOP_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH3_1", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH4_1", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH5_1", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_MONITOR_P_1", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_1", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_LH6_1", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH1_1", + "VBRK_LH1" + ], + [ + "CMT_TOP_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_LH7_1", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_MONITOR_N_1", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_LH9_1", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2BEG2_1", + "VBRK_EE2BEG2" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 5, + 2 + ], + "wire_pairs": [ + [ + "PCIE_SE2A2_8", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_WW2END1_8", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_BYP3_L_8", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_WW2A1_8", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_NE4BEG2_8", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_SW4END1_8", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_EE4C1_8", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_EE2A1_8", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_WW2A2_8", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_EE2A3_8", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_WW4B3_8", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_SW4A1_8", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_LH9_8", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_CLK0_L_8", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_WW4END2_8", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_IMUX31_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_BYP0_L_8", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_NW4A2_8", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_SW4END0_8", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_BYP7_L_8", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_IMUX2_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_WW4A1_8", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_WW4B1_8", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_IMUX6_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_NW2A1_8", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_EE4BEG2_8", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_EE4A3_8", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_NW4END1_8", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_IMUX35_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_IMUX19_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_BYP1_L_8", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_LH11_8", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_WW4END3_8", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_IMUX3_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_IMUX32_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_IMUX42_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_FAN7_L_8", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_EL1BEG3_8", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_IMUX36_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_FAN4_L_8", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_SE2A0_8", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_WR1END3_8", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_LH6_8", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_IMUX27_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_NE2A2_8", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_NE4BEG3_8", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_WW2END3_8", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_WW4END1_8", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_CLK1_L_8", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_IMUX44_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_SW2A1_8", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_SE4C0_8", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_NW4A3_8", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_WR1END2_8", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_IMUX5_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_EE2BEG3_8", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_WW4C0_8", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_IMUX25_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_FAN0_L_8", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_ER1BEG0_8", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_EE4B1_8", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_IMUX37_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_IMUX46_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_SE4C2_8", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_EE2A2_8", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_WW4B2_8", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_EE4B0_8", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_EE4A1_8", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_SW2A0_8", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_EL1BEG1_8", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_IMUX10_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_IMUX15_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_WW4C1_8", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_IMUX17_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_NE4C3_8", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_IMUX47_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_IMUX16_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_SE4BEG0_8", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_WW4B0_8", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_ER1BEG1_8", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_EE4B3_8", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_SW4A2_8", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_IMUX1_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_IMUX7_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_EE4C0_8", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_SE4BEG3_8", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_IMUX22_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_WW2END2_8", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_IMUX14_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_LH4_8", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_NE4C2_8", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_EE4BEG3_8", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_WR1END1_8", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_NE2A1_8", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_SE4C1_8", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_LH3_8", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_IMUX24_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_FAN6_L_8", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_IMUX39_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_WW4A3_8", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_LH7_8", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_WW2END0_8", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_WR1END0_8", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_BYP4_L_8", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_ER1BEG2_8", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_WL1END2_8", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_LH12_8", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_WW4C2_8", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_EE4A0_8", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_BYP5_L_8", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_NW4A1_8", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_IMUX41_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_WW4END0_8", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_IMUX4_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_SE4BEG2_8", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_WW4A2_8", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_IMUX0_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_IMUX28_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_WW2A0_8", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_NW4END0_8", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_WL1END1_8", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_EL1BEG0_8", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_LH5_8", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_IMUX23_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_IMUX12_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_CTRL1_L_8", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_IMUX8_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_FAN3_L_8", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_IMUX34_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_NE4C1_8", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_IMUX18_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_SE4BEG1_8", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_IMUX43_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_BYP2_L_8", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_SW4A0_8", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_NE2A0_8", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_NE4C0_8", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_IMUX26_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_WL1END0_8", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_EE2BEG1_8", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX38_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_NW2A0_8", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_SW4A3_8", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_IMUX21_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_LH2_8", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_SW4END2_8", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_EE4C2_8", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_SW2A3_8", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX13_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_EE2BEG2_8", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_ER1BEG3_8", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_NW2A3_8", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_NW4END2_8", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_EE2A0_8", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_EE2BEG0_8", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_EE4B2_8", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_IMUX40_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_EE4A2_8", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_NE2A3_8", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_EE4BEG0_8", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_SE2A3_8", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_FAN1_L_8", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_IMUX9_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_IMUX33_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_FAN2_L_8", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_SW2A2_8", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_SE2A1_8", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_IMUX20_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_FAN5_L_8", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_SE4C3_8", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_NE4BEG1_8", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_BYP6_L_8", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_LH8_8", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4C3_8", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_IMUX29_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_IMUX45_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_LH1_8", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_WW4C3_8", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_SW4END3_8", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_8", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_WW2A3_8", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_EL1BEG2_8", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_NW2A2_8", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_WL1END3_8", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_LH10_8", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_EE4BEG1_8", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_NE4BEG0_8", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_NW4A0_8", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_NW4END3_8", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_WW4A0_8", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_CTRL0_L_8", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_IMUX30_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_IMUX11_L_8", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLBLL_LL_CIN", + "HCLK_CLB_COUT1_R" + ], + [ + "CLBLL_L_CIN", + "HCLK_CLB_COUT0_R" + ] + ], + "tile_types": [ + "CLBLL_R", + "HCLK_CLB" + ] + }, + { + "grid_deltas": [ + -1, + 10 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW2END1_1", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE4BEG0_1", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_LH9_1", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NW4A1_1", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WW2END3_1", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_SW4A3_1", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_WW4B3_1", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SE2A3_1", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_LH5_1", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_LH2_1", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_ER1BEG3_1", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_LH6_1", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WL1END0_1", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_WW4A0_1", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE2BEG2_1", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NE4BEG0_1", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NW4END1_1", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_EE4B0_1", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_SW4A1_1", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NW4END0_1", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_LH7_1", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_LH11_1", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_LH10_1", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WW4A3_1", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NE4BEG3_1", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW2END2_1", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_WR1END3_1", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_SW4A0_1", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_SW2A1_1", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4B3_1", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SE2A0_1", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE2A3_1", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_SE4C3_1", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_NW2A1_1", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_NW2A0_1", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WW4C0_1", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NW4A0_1", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_WW2END0_1", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NW4END3_1", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WL1END1_1", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_NW2A2_1", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_EL1BEG2_1", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_NE4C2_1", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WR1END2_1", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_SE4C2_1", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_EE2A1_1", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_EE4C2_1", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_WW4B1_1", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_SW4A2_1", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_LH8_1", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW4A1_1", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_NE4BEG1_1", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_EE4B1_1", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EE4BEG2_1", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WW2A1_1", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_LH1_1", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_WW2A2_1", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_EE4B2_1", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_WW4B0_1", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_LH3_1", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_EE2A0_1", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_EE4A3_1", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_WW4A2_1", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EL1BEG1_1", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NW2A3_1", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE2A0_1", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_SW4END1_1", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_NE2A3_1", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_SE4BEG3_1", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EE4BEG1_1", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG0_1", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SE4C0_1", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_NE2A1_1", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_WW4C2_1", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NW4END2_1", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_EE4C1_1", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE2BEG0_1", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4END1_1", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE2BEG1_1", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_SW4END2_1", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_NE2A2_1", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE4C3_1", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW4C1_1", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_EL1BEG3_1", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_SE2A1_1", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_SE2A2_1", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_WL1END2_1", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_LH12_1", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_NE4C0_1", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_WW4END0_1", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_NE4C3_1", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_EE4A1_1", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EL1BEG0_1", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_SW2A2_1", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_EE4A2_1", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_WW4C3_1", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_LH4_1", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE2A2_1", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WL1END3_1", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4C0_1", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_SE4BEG2_1", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_EE2BEG3_1", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NE4C1_1", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE4BEG2_1", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_ER1BEG0_1", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NW4A2_1", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_EE4A0_1", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_ER1BEG2_1", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_SW2A3_1", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_ER1BEG1_1", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WW4END3_1", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WR1END0_1", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_SW4END0_1", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WW2A3_1", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_EE4BEG3_1", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_SW4END3_1", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_WW2A0_1", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_SW2A0_1", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WW4END2_1", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_NW4A3_1", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_SE4BEG1_1", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_WW4B2_1", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_WR1END1_1", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SE4C1_1", + "INT_FEEDTHRU_2_SE4C1" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + 5 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH12_0", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH9_0", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH1_0", + "VBRK_LH1" + ], + [ + "CMT_TOP_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH8_0", + "VBRK_LH8" + ], + [ + "CMT_TOP_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH5_0", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH4_0", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH3_0", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_LH10_0", + "VBRK_LH10" + ], + [ + "CMT_TOP_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH11_0", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_MONITOR_N_0", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH7_0", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH2_0", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH6_0", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_MONITOR_P_0", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SW4A1_0", + "VBRK_SW4A1" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_INT_PERFCLK3" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CK_IN2" + ] + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_R" + ] + }, + { + "grid_deltas": [ + 0, + -21 + ], + "wire_pairs": [ + [ + "CFG_CENTER_BOT_USR_ACCESS_DATA3", + "CFG_CENTER_MID_USR_ACCESS_DATA3" + ], + [ + "CFG_CENTER_BOT_USR_ACCESS_DATA11", + "CFG_CENTER_MID_USR_ACCESS_DATA11" + ], + [ + "CFG_CENTER_BOT_USR_ACCESS_DATA12", + "CFG_CENTER_MID_USR_ACCESS_DATA12" + ], + [ + "CFG_CENTER_BOT_USR_ACCESS_DATA13", + "CFG_CENTER_MID_USR_ACCESS_DATA13" + ], + [ + "CFG_CENTER_BOT_USR_ACCESS_DATA8", + "CFG_CENTER_MID_USR_ACCESS_DATA8" + ], + [ + "CFG_CENTER_BOT_USR_ACCESS_DATA14", + "CFG_CENTER_MID_USR_ACCESS_DATA14" + ], + [ + "CFG_CENTER_BOT_USR_ACCESS_DATA6", + "CFG_CENTER_MID_USR_ACCESS_DATA6" + ], + [ + "CFG_CENTER_BOT_USR_ACCESS_DATA9", + "CFG_CENTER_MID_USR_ACCESS_DATA9" + ], + [ + "CFG_CENTER_BOT_USR_ACCESS_DATA4", + "CFG_CENTER_MID_USR_ACCESS_DATA4" + ], + [ + "CFG_CENTER_BOT_USR_ACCESS_DATA7", + "CFG_CENTER_MID_USR_ACCESS_DATA7" + ], + [ + "CFG_CENTER_BOT_USR_ACCESS_DATA2", + "CFG_CENTER_MID_USR_ACCESS_DATA2" + ], + [ + "CFG_CENTER_BOT_CFG_IO_ACCESS_VGGCOMPOUT", + "CFG_CENTER_MID_CFG_IO_ACCESS_VGGCOMPOUT" + ], + [ + "CFG_CENTER_BOT_USR_ACCESS_DATA10", + "CFG_CENTER_MID_USR_ACCESS_DATA10" + ], + [ + "CFG_CENTER_BOT_USR_ACCESS_DATA5", + "CFG_CENTER_MID_USR_ACCESS_DATA5" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "CFG_CENTER_MID" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "PCIE_NW4A2_12", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_IMUX32_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_IMUX17_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_SW4A1_12", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_BYP2_R_12", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_FAN5_R_12", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_12", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_IMUX47_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_IMUX37_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_NW2A1_12", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_SW4END0_12", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_IMUX6_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_12", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_IMUX11_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_IMUX43_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_SE4C0_12", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_IMUX23_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_12", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_NE4BEG0_12", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_IMUX44_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_IMUX20_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_IMUX19_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_IMUX45_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_12", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_NE4C0_12", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_NE4C2_12", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_EE4B2_12", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_NW4END2_12", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_EE2BEG2_12", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_LH2_12", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_SW4A2_12", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_WL1END3_12", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_IMUX9_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_IMUX27_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_IMUX24_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_NE4C1_12", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_IMUX4_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_FAN2_R_12", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_IMUX41_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_IMUX42_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_LH10_12", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_SE4C1_12", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_NW2A0_12", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_12", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_EE4A1_12", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_SE4BEG3_12", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_EE4BEG2_12", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_12", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_WR1END3_12", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_EE2BEG1_12", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_BYP4_R_12", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_EE2A2_12", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_CTRL1_R_12", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_EE2BEG3_12", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_IMUX38_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_NW4A0_12", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WW4END0_12", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_WR1END0_12", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_12", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_IMUX31_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_IMUX34_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_EL1BEG0_12", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_LH11_12", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_NW4END3_12", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_WW2A2_12", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_EE4B0_12", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_EE4BEG0_12", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_12", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_IMUX35_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_WW2END0_12", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_SE4BEG2_12", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_NW4END0_12", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_LH6_12", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_WW4B0_12", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_SE2A0_12", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_WW4B2_12", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_NW2A3_12", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_WW4A1_12", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_IMUX1_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_BYP6_R_12", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_12", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_WW2A0_12", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_EE4C3_12", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_IMUX29_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_EE2A1_12", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_NE2A1_12", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_WW4END2_12", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_SW4A0_12", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_EE4C0_12", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_CTRL0_R_12", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_WW4A3_12", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_WW4C3_12", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_WW4END1_12", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_12", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_EE4C1_12", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_WR1END2_12", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_FAN0_R_12", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_LH5_12", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_SE2A3_12", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_FAN7_R_12", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_IMUX10_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_12", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_NE2A2_12", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_EE2A0_12", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_NW2A2_12", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_BYP5_R_12", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_SW4END3_12", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_WR1END1_12", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_WW2END2_12", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_NE4C3_12", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_IMUX26_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_IMUX13_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_CLK0_R_12", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_IMUX33_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_12", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_NW4END1_12", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_SE4C2_12", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_IMUX15_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_IMUX21_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_NE2A3_12", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_ER1BEG1_12", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_IMUX2_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_WW2A1_12", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_IMUX25_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_12", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_EL1BEG2_12", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_IMUX36_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_12", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_IMUX7_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_12", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_WW2A3_12", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_LH9_12", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_12", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_WW4C1_12", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_LH8_12", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_IMUX12_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_LH12_12", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_SW2A3_12", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_SW2A1_12", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_SW4END1_12", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_IMUX14_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_WW4A2_12", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_EE2A3_12", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_WW2END3_12", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_SW4END2_12", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_IMUX5_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_ER1BEG0_12", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_ER1BEG3_12", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_WW4C2_12", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_IMUX22_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_WL1END1_12", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_FAN1_R_12", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_NE4BEG3_12", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_EL1BEG3_12", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_NW4A3_12", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_EE4BEG3_12", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_LH7_12", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_IMUX30_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_SE2A1_12", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_NE4BEG2_12", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_IMUX39_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_12", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_FAN3_R_12", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_SE4BEG0_12", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_SE2A2_12", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_NE2A0_12", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_WW4B3_12", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_12", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_LH1_12", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_BYP1_R_12", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_IMUX8_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_EE4B1_12", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_EL1BEG1_12", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_CLK1_R_12", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_12", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_BYP3_R_12", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_SE4BEG1_12", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_LH3_12", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_SE4C3_12", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_NW4A1_12", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_EE4C2_12", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_EE2BEG0_12", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_FAN4_R_12", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_12", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_EE4A3_12", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_IMUX28_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_WL1END2_12", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_IMUX0_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_WW4B1_12", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_WW4END3_12", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_EE4A0_12", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_IMUX16_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_IMUX46_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_BYP7_R_12", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_SW2A2_12", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_FAN6_R_12", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_EE4A2_12", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_NE4BEG1_12", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_WW4C0_12", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_SW4A3_12", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_12", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_WW4A0_12", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_12", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_BYP0_R_12", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_IMUX3_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_IMUX40_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_WW2END1_12", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_SW2A0_12", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_EE4B3_12", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_IMUX18_R_12", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_LH4_12", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_ER1BEG2_12", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_EE4BEG1_12", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_12", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_WL1END0_12", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_12", + "INT_INTERFACE_LOGIC_OUTS_B6" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SE4C2_8", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WL1END1_8", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_SE4BEG1_8", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_IMUX40_8", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_BYP1_8", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SE2A0_8", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_EL1BEG1_8", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_IMUX21_8", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_IMUX23_8", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NW2A3_8", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_LH11_8", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_SW2A0_8", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_IMUX44_8", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_NW4A3_8", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_WW2END2_8", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_IMUX16_8", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WW4C0_8", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX18_8", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_BYP3_8", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_WR1END2_8", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_IMUX8_8", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW4END3_8", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_LH5_8", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX31_8", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_SW2A3_8", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_LH6_8", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_NE2A2_8", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WR1END3_8", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_SE4C1_8", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_LH3_8", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_SW4A0_8", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_IMUX37_8", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SE4BEG2_8", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_FAN6_8", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_NW2A0_8", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_EE4C3_8", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE2BEG2_8", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_EE4A3_8", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX45_8", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX24_8", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_NE4C3_8", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_IMUX38_8", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_NE4C2_8", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_NW4A0_8", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX12_8", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_WW2A0_8", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_WW2END0_8", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_ER1BEG1_8", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_IMUX15_8", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_EE4B0_8", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_EE4BEG0_8", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_BYP0_8", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_WW2A2_8", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_EE2A3_8", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_IMUX13_8", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_IMUX42_8", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX25_8", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_WW4A0_8", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX33_8", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_BYP7_8", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_NW4END0_8", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_EE4B1_8", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_SE2A1_8", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_IMUX9_8", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX27_8", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX6_8", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_WR1END1_8", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_FAN0_8", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX3_8", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_NW2A1_8", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_CTRL0_8", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX32_8", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_8", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_IMUX26_8", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_CLK0_8", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX36_8", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_BYP4_8", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_NW4END1_8", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_EE2BEG1_8", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX14_8", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_IMUX20_8", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_FAN3_8", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_SW4END3_8", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_WW4C2_8", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WW4A3_8", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WL1END3_8", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_IMUX39_8", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_EE4C0_8", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_FAN2_8", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_NE2A1_8", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX0_8", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW4END1_8", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_NW4END2_8", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_WW4A2_8", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_NE4C1_8", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_EE2BEG0_8", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX22_8", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_BYP6_8", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_WW4C1_8", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_ER1BEG3_8", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_WL1END2_8", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WW4B0_8", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_EE4B3_8", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_LH8_8", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_IMUX28_8", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_FAN5_8", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_NW4A2_8", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_EL1BEG3_8", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_SW2A2_8", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_EE4C2_8", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX2_8", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_WL1END0_8", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_CTRL1_8", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_8", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_LH7_8", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_SW4END2_8", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_NE4BEG0_8", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_EE2A1_8", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_NE4BEG1_8", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_EE4A2_8", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX17_8", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_ER1BEG2_8", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX30_8", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_NW4A1_8", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SE4BEG0_8", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_IMUX1_8", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX10_8", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SE4C0_8", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_SE4BEG3_8", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_EE4B2_8", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX29_8", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX34_8", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_8", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_ER1BEG0_8", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_SW4END1_8", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_LH1_8", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_8", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_EL1BEG2_8", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NW4END3_8", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_IMUX7_8", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_EE2A2_8", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_SW4A3_8", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EE4BEG3_8", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX46_8", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_EE4A1_8", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_8", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_IMUX43_8", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX4_8", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_8", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_EE4A0_8", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_IMUX41_8", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_LH12_8", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_SW2A1_8", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_NE4BEG3_8", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_SE4C3_8", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX11_8", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_EE2A0_8", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_EE4BEG1_8", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_BYP2_8", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_IMUX5_8", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WW4C3_8", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NE2A0_8", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_EE2BEG3_8", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_CLK1_8", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_WR1END0_8", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_WW4B2_8", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_LH10_8", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW2END1_8", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_EL1BEG0_8", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_WW4END0_8", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_SE2A2_8", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_FAN4_8", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_8", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_WW4END2_8", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_SW4END0_8", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX35_8", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_LH2_8", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_SW4A2_8", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NW2A2_8", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_BYP5_8", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_WW4A1_8", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_NE4C0_8", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_FAN1_8", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_WW2A1_8", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_NE4BEG2_8", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW4B3_8", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_WW4B1_8", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_EE4BEG2_8", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_LH4_8", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_WW2END3_8", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW2A3_8", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_FAN7_8", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_NE2A3_8", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX47_8", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_EE4C1_8", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX19_8", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_LH9_8", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_SE2A3_8", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SW4A1_8", + "VFRAME_SW4A1" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + -10 + ], + "wire_pairs": [ + [ + "MONITOR_VERT_VAUXN3", + "MONITOR_VERT_VAUXN3" + ], + [ + "MONITOR_VERT_VAUXN8", + "MONITOR_VERT_VAUXN8" + ], + [ + "MONITOR_VERT_VAUXN10", + "MONITOR_VERT_VAUXN10" + ], + [ + "MONITOR_VERT_VAUXP10", + "MONITOR_VERT_VAUXP10" + ], + [ + "MONITOR_VERT_VAUXP11", + "MONITOR_VERT_VAUXP11" + ], + [ + "MONITOR_VERT_VAUXN5", + "MONITOR_VERT_VAUXN5" + ], + [ + "MONITOR_VERT_VAUXP0", + "MONITOR_VERT_VAUXP0" + ], + [ + "MONITOR_VERT_VAUXP5", + "MONITOR_VERT_VAUXP5" + ], + [ + "MONITOR_VERT_VAUXN11", + "MONITOR_VERT_VAUXN11" + ], + [ + "MONITOR_VERT_VAUXN1", + "MONITOR_VERT_VAUXN1" + ], + [ + "MONITOR_VERT_VAUXN9", + "MONITOR_VERT_VAUXN9" + ], + [ + "MONITOR_VERT_VAUXN12", + "MONITOR_VERT_VAUXN12" + ], + [ + "MONITOR_VERT_VAUXN4", + "MONITOR_VERT_VAUXN4" + ], + [ + "MONITOR_VERT_VAUXN0", + "MONITOR_VERT_VAUXN0" + ], + [ + "MONITOR_VERT_VAUXN2", + "MONITOR_VERT_VAUXN2" + ], + [ + "MONITOR_VERT_VAUXP2", + "MONITOR_VERT_VAUXP2" + ], + [ + "MONITOR_VERT_VAUXP1", + "MONITOR_VERT_VAUXP1" + ], + [ + "MONITOR_VERT_VAUXP8", + "MONITOR_VERT_VAUXP8" + ], + [ + "MONITOR_VERT_VAUXP3", + "MONITOR_VERT_VAUXP3" + ], + [ + "MONITOR_VERT_VAUXP9", + "MONITOR_VERT_VAUXP9" + ], + [ + "MONITOR_VERT_VAUXP4", + "MONITOR_VERT_VAUXP4" + ], + [ + "MONITOR_VERT_VAUXP12", + "MONITOR_VERT_VAUXP12" + ] + ], + "tile_types": [ + "MONITOR_BOT_FUJI2", + "MONITOR_MID_FUJI2" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "MONITOR_EL1BEG1_3", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_EE4A0_3", + "VFRAME_EE4A0" + ], + [ + "MONITOR_SW2A0_3", + "VFRAME_SW2A0" + ], + [ + "MONITOR_WL1END2_3", + "VFRAME_WL1END2" + ], + [ + "MONITOR_EE2BEG1_3", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_BYP5_3", + "VFRAME_BYP5" + ], + [ + "MONITOR_NW4A0_3", + "VFRAME_NW4A0" + ], + [ + "MONITOR_WL1END3_3", + "VFRAME_WL1END3" + ], + [ + "MONITOR_IMUX8_3", + "VFRAME_IMUX8" + ], + [ + "MONITOR_FAN6_3", + "VFRAME_FAN6" + ], + [ + "MONITOR_CLK1_3", + "VFRAME_CLK1" + ], + [ + "MONITOR_IMUX23_3", + "VFRAME_IMUX23" + ], + [ + "MONITOR_EE4BEG2_3", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_SE4C3_3", + "VFRAME_SE4C3" + ], + [ + "MONITOR_IMUX35_3", + "VFRAME_IMUX35" + ], + [ + "MONITOR_FAN2_3", + "VFRAME_FAN2" + ], + [ + "MONITOR_NE4BEG0_3", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_WW4C1_3", + "VFRAME_WW4C1" + ], + [ + "MONITOR_IMUX29_3", + "VFRAME_IMUX29" + ], + [ + "MONITOR_IMUX28_3", + "VFRAME_IMUX28" + ], + [ + "MONITOR_IMUX0_3", + "VFRAME_IMUX0" + ], + [ + "MONITOR_LH9_3", + "VFRAME_LH9" + ], + [ + "MONITOR_SW4END2_3", + "VFRAME_SW4END2" + ], + [ + "MONITOR_IMUX16_3", + "VFRAME_IMUX16" + ], + [ + "MONITOR_SW4A3_3", + "VFRAME_SW4A3" + ], + [ + "MONITOR_LH1_3", + "VFRAME_LH1" + ], + [ + "MONITOR_EE4B0_3", + "VFRAME_EE4B0" + ], + [ + "MONITOR_IMUX44_3", + "VFRAME_IMUX44" + ], + [ + "MONITOR_FAN4_3", + "VFRAME_FAN4" + ], + [ + "MONITOR_IMUX45_3", + "VFRAME_IMUX45" + ], + [ + "MONITOR_IMUX18_3", + "VFRAME_IMUX18" + ], + [ + "MONITOR_IMUX2_3", + "VFRAME_IMUX2" + ], + [ + "MONITOR_IMUX6_3", + "VFRAME_IMUX6" + ], + [ + "MONITOR_IMUX30_3", + "VFRAME_IMUX30" + ], + [ + "MONITOR_IMUX22_3", + "VFRAME_IMUX22" + ], + [ + "MONITOR_FAN1_3", + "VFRAME_FAN1" + ], + [ + "MONITOR_NE4BEG3_3", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_ER1BEG0_3", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_EE4B2_3", + "VFRAME_EE4B2" + ], + [ + "MONITOR_SW2A1_3", + "VFRAME_SW2A1" + ], + [ + "MONITOR_LH5_3", + "VFRAME_LH5" + ], + [ + "MONITOR_IMUX7_3", + "VFRAME_IMUX7" + ], + [ + "MONITOR_WR1END3_3", + "VFRAME_WR1END3" + ], + [ + "MONITOR_BYP4_3", + "VFRAME_BYP4" + ], + [ + "MONITOR_WW4A2_3", + "VFRAME_WW4A2" + ], + [ + "MONITOR_SE2A0_3", + "VFRAME_SE2A0" + ], + [ + "MONITOR_SW4END1_3", + "VFRAME_SW4END1" + ], + [ + "MONITOR_IMUX33_3", + "VFRAME_IMUX33" + ], + [ + "MONITOR_WW4A0_3", + "VFRAME_WW4A0" + ], + [ + "MONITOR_WW2END3_3", + "VFRAME_WW2END3" + ], + [ + "MONITOR_IMUX10_3", + "VFRAME_IMUX10" + ], + [ + "MONITOR_WW2A0_3", + "VFRAME_WW2A0" + ], + [ + "MONITOR_BYP3_3", + "VFRAME_BYP3" + ], + [ + "MONITOR_IMUX39_3", + "VFRAME_IMUX39" + ], + [ + "MONITOR_EL1BEG2_3", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_EE2A0_3", + "VFRAME_EE2A0" + ], + [ + "MONITOR_IMUX24_3", + "VFRAME_IMUX24" + ], + [ + "MONITOR_NE2A0_3", + "VFRAME_NE2A0" + ], + [ + "MONITOR_IMUX5_3", + "VFRAME_IMUX5" + ], + [ + "MONITOR_NE4C3_3", + "VFRAME_NE4C3" + ], + [ + "MONITOR_SE2A2_3", + "VFRAME_SE2A2" + ], + [ + "MONITOR_IMUX46_3", + "VFRAME_IMUX46" + ], + [ + "MONITOR_NW2A1_3", + "VFRAME_NW2A1" + ], + [ + "MONITOR_IMUX37_3", + "VFRAME_IMUX37" + ], + [ + "MONITOR_NW4A3_3", + "VFRAME_NW4A3" + ], + [ + "MONITOR_SW4A0_3", + "VFRAME_SW4A0" + ], + [ + "MONITOR_WW4END1_3", + "VFRAME_WW4END1" + ], + [ + "MONITOR_FAN0_3", + "VFRAME_FAN0" + ], + [ + "MONITOR_SE2A3_3", + "VFRAME_SE2A3" + ], + [ + "MONITOR_SW4A2_3", + "VFRAME_SW4A2" + ], + [ + "MONITOR_WW4B1_3", + "VFRAME_WW4B1" + ], + [ + "MONITOR_NE2A3_3", + "VFRAME_NE2A3" + ], + [ + "MONITOR_IMUX26_3", + "VFRAME_IMUX26" + ], + [ + "MONITOR_IMUX31_3", + "VFRAME_IMUX31" + ], + [ + "MONITOR_NE4C2_3", + "VFRAME_NE4C2" + ], + [ + "MONITOR_NE4BEG1_3", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_NW2A3_3", + "VFRAME_NW2A3" + ], + [ + "MONITOR_BYP1_3", + "VFRAME_BYP1" + ], + [ + "MONITOR_CLK0_3", + "VFRAME_CLK0" + ], + [ + "MONITOR_IMUX12_3", + "VFRAME_IMUX12" + ], + [ + "MONITOR_WW4A1_3", + "VFRAME_WW4A1" + ], + [ + "MONITOR_LH10_3", + "VFRAME_LH10" + ], + [ + "MONITOR_WW2END2_3", + "VFRAME_WW2END2" + ], + [ + "MONITOR_WW2END0_3", + "VFRAME_WW2END0" + ], + [ + "MONITOR_NE4C1_3", + "VFRAME_NE4C1" + ], + [ + "MONITOR_NE4BEG2_3", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_EE4B3_3", + "VFRAME_EE4B3" + ], + [ + "MONITOR_FAN5_3", + "VFRAME_FAN5" + ], + [ + "MONITOR_IMUX17_3", + "VFRAME_IMUX17" + ], + [ + "MONITOR_NE4C0_3", + "VFRAME_NE4C0" + ], + [ + "MONITOR_NW4END1_3", + "VFRAME_NW4END1" + ], + [ + "MONITOR_CTRL0_3", + "VFRAME_CTRL0" + ], + [ + "MONITOR_NW2A0_3", + "VFRAME_NW2A0" + ], + [ + "MONITOR_IMUX25_3", + "VFRAME_IMUX25" + ], + [ + "MONITOR_LH2_3", + "VFRAME_LH2" + ], + [ + "MONITOR_IMUX1_3", + "VFRAME_IMUX1" + ], + [ + "MONITOR_LH11_3", + "VFRAME_LH11" + ], + [ + "MONITOR_NW4END0_3", + "VFRAME_NW4END0" + ], + [ + "MONITOR_IMUX40_3", + "VFRAME_IMUX40" + ], + [ + "MONITOR_ER1BEG2_3", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_IMUX3_3", + "VFRAME_IMUX3" + ], + [ + "MONITOR_NE2A1_3", + "VFRAME_NE2A1" + ], + [ + "MONITOR_SE4BEG1_3", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_BYP7_3", + "VFRAME_BYP7" + ], + [ + "MONITOR_EE4A1_3", + "VFRAME_EE4A1" + ], + [ + "MONITOR_SW2A3_3", + "VFRAME_SW2A3" + ], + [ + "MONITOR_IMUX38_3", + "VFRAME_IMUX38" + ], + [ + "MONITOR_NW4END3_3", + "VFRAME_NW4END3" + ], + [ + "MONITOR_SW4END0_3", + "VFRAME_SW4END0" + ], + [ + "MONITOR_WW4END0_3", + "VFRAME_WW4END0" + ], + [ + "MONITOR_SW4END3_3", + "VFRAME_SW4END3" + ], + [ + "MONITOR_FAN7_3", + "VFRAME_FAN7" + ], + [ + "MONITOR_ER1BEG3_3", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_SE4C0_3", + "VFRAME_SE4C0" + ], + [ + "MONITOR_WW2A3_3", + "VFRAME_WW2A3" + ], + [ + "MONITOR_EL1BEG3_3", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_IMUX32_3", + "VFRAME_IMUX32" + ], + [ + "MONITOR_EE2A2_3", + "VFRAME_EE2A2" + ], + [ + "MONITOR_NW2A2_3", + "VFRAME_NW2A2" + ], + [ + "MONITOR_SE4BEG3_3", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_EE4A2_3", + "VFRAME_EE4A2" + ], + [ + "MONITOR_NE2A2_3", + "VFRAME_NE2A2" + ], + [ + "MONITOR_IMUX19_3", + "VFRAME_IMUX19" + ], + [ + "MONITOR_IMUX11_3", + "VFRAME_IMUX11" + ], + [ + "MONITOR_IMUX20_3", + "VFRAME_IMUX20" + ], + [ + "MONITOR_IMUX42_3", + "VFRAME_IMUX42" + ], + [ + "MONITOR_WW4B2_3", + "VFRAME_WW4B2" + ], + [ + "MONITOR_IMUX9_3", + "VFRAME_IMUX9" + ], + [ + "MONITOR_SW2A2_3", + "VFRAME_SW2A2" + ], + [ + "MONITOR_LH4_3", + "VFRAME_LH4" + ], + [ + "MONITOR_SE4C1_3", + "VFRAME_SE4C1" + ], + [ + "MONITOR_WW4END2_3", + "VFRAME_WW4END2" + ], + [ + "MONITOR_CTRL1_3", + "VFRAME_CTRL1" + ], + [ + "MONITOR_WW4A3_3", + "VFRAME_WW4A3" + ], + [ + "MONITOR_BYP0_3", + "VFRAME_BYP0" + ], + [ + "MONITOR_EE4BEG1_3", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX15_3", + "VFRAME_IMUX15" + ], + [ + "MONITOR_FAN3_3", + "VFRAME_FAN3" + ], + [ + "MONITOR_WW4C0_3", + "VFRAME_WW4C0" + ], + [ + "MONITOR_WL1END0_3", + "VFRAME_WL1END0" + ], + [ + "MONITOR_WW2END1_3", + "VFRAME_WW2END1" + ], + [ + "MONITOR_WW2A2_3", + "VFRAME_WW2A2" + ], + [ + "MONITOR_EE2A3_3", + "VFRAME_EE2A3" + ], + [ + "MONITOR_IMUX27_3", + "VFRAME_IMUX27" + ], + [ + "MONITOR_WR1END2_3", + "VFRAME_WR1END2" + ], + [ + "MONITOR_EL1BEG0_3", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_WW4C2_3", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE2BEG3_3", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_BYP2_3", + "VFRAME_BYP2" + ], + [ + "MONITOR_EE2BEG2_3", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_WW4B0_3", + "VFRAME_WW4B0" + ], + [ + "MONITOR_SE2A1_3", + "VFRAME_SE2A1" + ], + [ + "MONITOR_IMUX36_3", + "VFRAME_IMUX36" + ], + [ + "MONITOR_SE4BEG2_3", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_IMUX34_3", + "VFRAME_IMUX34" + ], + [ + "MONITOR_WR1END0_3", + "VFRAME_WR1END0" + ], + [ + "MONITOR_ER1BEG1_3", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_BYP6_3", + "VFRAME_BYP6" + ], + [ + "MONITOR_NW4END2_3", + "VFRAME_NW4END2" + ], + [ + "MONITOR_WL1END1_3", + "VFRAME_WL1END1" + ], + [ + "MONITOR_SE4C2_3", + "VFRAME_SE4C2" + ], + [ + "MONITOR_EE4BEG0_3", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_LH7_3", + "VFRAME_LH7" + ], + [ + "MONITOR_LH12_3", + "VFRAME_LH12" + ], + [ + "MONITOR_SW4A1_3", + "VFRAME_SW4A1" + ], + [ + "MONITOR_NW4A1_3", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WW4B3_3", + "VFRAME_WW4B3" + ], + [ + "MONITOR_WR1END1_3", + "VFRAME_WR1END1" + ], + [ + "MONITOR_EE4BEG3_3", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_IMUX47_3", + "VFRAME_IMUX47" + ], + [ + "MONITOR_EE2A1_3", + "VFRAME_EE2A1" + ], + [ + "MONITOR_LH8_3", + "VFRAME_LH8" + ], + [ + "MONITOR_WW4C3_3", + "VFRAME_WW4C3" + ], + [ + "MONITOR_WW4END3_3", + "VFRAME_WW4END3" + ], + [ + "MONITOR_EE4B1_3", + "VFRAME_EE4B1" + ], + [ + "MONITOR_LH3_3", + "VFRAME_LH3" + ], + [ + "MONITOR_LH6_3", + "VFRAME_LH6" + ], + [ + "MONITOR_EE4C3_3", + "VFRAME_EE4C3" + ], + [ + "MONITOR_EE4C1_3", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX21_3", + "VFRAME_IMUX21" + ], + [ + "MONITOR_EE4A3_3", + "VFRAME_EE4A3" + ], + [ + "MONITOR_EE4C0_3", + "VFRAME_EE4C0" + ], + [ + "MONITOR_IMUX14_3", + "VFRAME_IMUX14" + ], + [ + "MONITOR_EE2BEG0_3", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_IMUX4_3", + "VFRAME_IMUX4" + ], + [ + "MONITOR_IMUX43_3", + "VFRAME_IMUX43" + ], + [ + "MONITOR_EE4C2_3", + "VFRAME_EE4C2" + ], + [ + "MONITOR_IMUX13_3", + "VFRAME_IMUX13" + ], + [ + "MONITOR_SE4BEG0_3", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_NW4A2_3", + "VFRAME_NW4A2" + ], + [ + "MONITOR_IMUX41_3", + "VFRAME_IMUX41" + ], + [ + "MONITOR_WW2A1_3", + "VFRAME_WW2A1" + ] + ], + "tile_types": [ + "MONITOR_TOP_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_INT_INTERFACE_CCIO1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_INT_INTERFACE_CCIO0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CCIO2", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CCIO3", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_TERM_PERFCLK3" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_TERM_PERFCLK0" + ] + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_TERM" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "CMT_FIFO_NE2A0_4", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_4", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "CMT_FIFO_SE2A0_4", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_SW2A3_4", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_4", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_4", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CMT_FIFO_EE4BEG0_4", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_EE4C3_4", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_NW4A1_4", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_WW4A2_4", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_L_IMUX36_4", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_NW4A0_4", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_SW2A1_4", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_EE4A0_4", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_WW4A1_4", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_LH7_4", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_L_BYP4_4", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_EE2A3_4", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_SE4BEG3_4", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX43_4", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_L_FAN4_4", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_L_IMUX40_4", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_NW2A2_4", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_4", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "CMT_FIFO_WW4C0_4", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_SW2A0_4", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_EE4B1_4", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_EE4B3_4", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_L_IMUX17_4", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_L_IMUX14_4", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_NE2A1_4", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_EE4A3_4", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_IMUX9_4", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_EE2BEG3_4", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_WR1END2_4", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_L_IMUX15_4", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_LH3_4", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_NW2A0_4", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_NE4C2_4", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_L_IMUX45_4", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_L_FAN5_4", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_WW2END2_4", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_4", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CMT_FIFO_L_FAN3_4", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_ER1BEG1_4", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_IMUX42_4", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_IMUX10_4", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_NE4BEG1_4", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX47_4", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_WW2A1_4", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_4", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CMT_FIFO_L_IMUX6_4", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_EE4C2_4", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_EE4C1_4", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_NW4END1_4", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_4", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CMT_FIFO_WR1END0_4", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_L_IMUX31_4", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_LH10_4", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_EE2BEG2_4", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_L_IMUX24_4", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_SE2A1_4", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_L_BYP5_4", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_WW4END1_4", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_EL1BEG0_4", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_L_IMUX32_4", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_NW4A2_4", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_NW4END0_4", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_4", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "CMT_FIFO_L_IMUX35_4", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_WW4END3_4", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_L_BYP2_4", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_NE4C1_4", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_EE4A1_4", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_WW4END2_4", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_L_IMUX27_4", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_4", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_4", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "CMT_FIFO_L_CLK0_4", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_L_IMUX3_4", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_NW4A3_4", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_WW4C1_4", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_LH8_4", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_NE4BEG2_4", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_SW2A2_4", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_L_IMUX34_4", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_WL1END3_4", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_SE4C0_4", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_WW4END0_4", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_NW2A3_4", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_L_BYP1_4", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_L_CLK1_4", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_WW2A3_4", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_4", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CMT_FIFO_EE4BEG3_4", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_SE4C2_4", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_L_IMUX12_4", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_LH2_4", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_LH6_4", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_LH11_4", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_NW4END3_4", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_L_IMUX8_4", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_IMUX7_4", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_WW2END1_4", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_EL1BEG2_4", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_EL1BEG3_4", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_L_IMUX33_4", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_EE2BEG0_4", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_FAN2_4", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_WW4B3_4", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_4", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "CMT_FIFO_WL1END0_4", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_CTRL1_4", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_L_IMUX2_4", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_WW4B0_4", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_EE2A2_4", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_WW4B2_4", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_EE4BEG2_4", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_WL1END1_4", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_ER1BEG0_4", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_MONITOR_P_4", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CMT_FIFO_EE4C0_4", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_SE4C1_4", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_L_IMUX16_4", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_EE4B0_4", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_SW4A1_4", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_WW4C3_4", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_4", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CMT_FIFO_WW2A0_4", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_SW4A2_4", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_WW4C2_4", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_NE4BEG3_4", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_NE4C3_4", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_LH9_4", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_WW4A3_4", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_LH4_4", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_L_CTRL0_4", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_4", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "CMT_FIFO_SW4END0_4", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_EE4B2_4", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_SW4A0_4", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_SE2A3_4", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_L_IMUX37_4", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_ER1BEG2_4", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_LH1_4", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_NW2A1_4", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_NW4END2_4", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_WW2A2_4", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_L_IMUX30_4", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_L_BYP3_4", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_LH5_4", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_L_IMUX11_4", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_L_IMUX5_4", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_L_IMUX18_4", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_SE4BEG0_4", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_WW2END0_4", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_MONITOR_N_4", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CMT_FIFO_SW4END2_4", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_L_IMUX44_4", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_SW4END3_4", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_4", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CMT_FIFO_NE4C0_4", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_L_IMUX13_4", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_L_IMUX21_4", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_L_IMUX46_4", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_L_IMUX0_4", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_WR1END1_4", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_4", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "CMT_FIFO_L_IMUX23_4", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_L_IMUX26_4", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_SW4END1_4", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_SE4BEG2_4", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX25_4", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_WL1END2_4", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_4", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CMT_FIFO_L_IMUX38_4", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_4", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CMT_FIFO_L_FAN6_4", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_SW4A3_4", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_L_BYP6_4", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_SE2A2_4", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_EL1BEG1_4", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_SE4C3_4", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_BYP0_4", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_WR1END3_4", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_L_FAN7_4", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_EE4A2_4", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_4", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_4", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CMT_FIFO_NE4BEG0_4", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX22_4", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_EE4BEG1_4", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_WW2END3_4", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_L_IMUX41_4", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_WW4B1_4", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_4", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_4", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_4", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "CMT_FIFO_L_IMUX4_4", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_L_IMUX19_4", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_L_FAN0_4", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_WW4A0_4", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_EE2A1_4", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_NE2A2_4", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_LH12_4", + "INT_INTERFACE_LH12" + ], + [ + "FIFO_DQS_IOTOPHASER_22", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "CMT_FIFO_L_IMUX28_4", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_ER1BEG3_4", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_L_FAN1_4", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_L_BYP7_4", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_SE4BEG1_4", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_EE2BEG1_4", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_L_IMUX20_4", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_L_IMUX1_4", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_4", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CMT_FIFO_L_IMUX29_4", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_L_IMUX39_4", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_NE2A3_4", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_EE2A0_4", + "INT_INTERFACE_EE2A0" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + -5 + ], + "wire_pairs": [ + [ + "BRAM_CASCINTOP_ADDRARDADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_FIFO36_CASCADEOUTB_1", + "BRKH_BRAM_CASCADEB_L" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" + ], + [ + "BRAM_FIFO36_CASCADEOUTA_1", + "BRKH_BRAM_CASCADEA_L" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7" + ] + ], + "tile_types": [ + "BRAM_L", + "BRKH_BRAM" + ] + }, + { + "grid_deltas": [ + -1, + 11 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SW4A0_0", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EL1BEG1_0", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_EE4A3_0", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE4C1_0", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_NW2A2_0", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_SE4BEG2_0", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW4C2_0", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_EE4B3_0", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SW4A3_0", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_NE4C2_0", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_ER1BEG1_0", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_EE2A2_0", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_EE2A3_0", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NE2A0_0", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_NW4A2_0", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NE4C1_0", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW2A1_0", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_SE4BEG0_0", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_WW4END0_0", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_NE4BEG3_0", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_EE4BEG2_0", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SE2A3_0", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SE2A1_0", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_ER1BEG0_0", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_SW4END1_0", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_WW4A2_0", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_NW4END0_0", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_WW4B1_0", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_EE2BEG1_0", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_WW4END2_0", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_SE4BEG3_0", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_LH1_0", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_LH3_0", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_NW2A3_0", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_EE4B2_0", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_SE4BEG1_0", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SW2A3_0", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_EL1BEG0_0", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_SW2A2_0", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_ER1BEG3_0", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW4B0_0", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_EE2A1_0", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_LH10_0", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WW4END1_0", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE4C3_0", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_EE2A0_0", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_EE2BEG2_0", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NW4END3_0", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_NW4END2_0", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4END3_0", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_EE4A0_0", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4B0_0", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH2_0", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_SE2A0_0", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SE4C2_0", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_LH5_0", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_WW4A0_0", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_NE4C3_0", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WL1END3_0", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_WW2A3_0", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WW4C0_0", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_LH7_0", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_NE4BEG2_0", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_WL1END1_0", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_WW2END2_0", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_WW2END1_0", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_SE4C3_0", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WW4B2_0", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE4B1_0", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_WL1END2_0", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WW2END0_0", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NE4BEG0_0", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NE4BEG1_0", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_LH9_0", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_EL1BEG2_0", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_WW4A3_0", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_LH11_0", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW2A0_0", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WR1END1_0", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_NW2A0_0", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_SW4A1_0", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_LH8_0", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_EE2BEG3_0", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_SE2A2_0", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4A2_0", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SW2A0_0", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WL1END0_0", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_EE4BEG3_0", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WR1END3_0", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_NE2A2_0", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_SW4END0_0", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_LH4_0", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE4BEG0_0", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NW4END1_0", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_SW4END3_0", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_EE2BEG0_0", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_NW4A1_0", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SW4A2_0", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_EL1BEG3_0", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WW4C1_0", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_LH6_0", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_NW4A0_0", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SE4C1_0", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_NE2A3_0", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_WW4A1_0", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_WW4C3_0", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE4C0_0", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_LH12_0", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_ER1BEG2_0", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_WR1END2_0", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_EE4A1_0", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_WW2A2_0", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WW2END3_0", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_NW4A3_0", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_EE4C2_0", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NE4C0_0", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_SW2A1_0", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4BEG1_0", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_WW4B3_0", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SE4C0_0", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_SW4END2_0", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WR1END0_0", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_NW2A1_0", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_NE2A1_0", + "INT_FEEDTHRU_2_NE2A1" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "CMT_FIFO_NE2A0_4", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_4", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "CMT_FIFO_SE2A0_4", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_SW2A3_4", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_EE4BEG0_4", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_NW4A1_4", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_EE4C3_4", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_WW4A2_4", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_L_IMUX36_4", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_NW4A0_4", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_SW2A1_4", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_EE4A0_4", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_WW4A1_4", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_LH7_4", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_L_BYP4_4", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_EE2A3_4", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_SE4BEG3_4", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX43_4", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_L_FAN4_4", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_L_IMUX40_4", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_NW2A2_4", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_WW4C0_4", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_4", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "CMT_FIFO_SW2A0_4", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_EE4B1_4", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_EE4B3_4", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_L_IMUX17_4", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_L_IMUX14_4", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_NE2A1_4", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_EE4A3_4", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_4", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "CMT_FIFO_EE2BEG3_4", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_L_IMUX9_4", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_4", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "CMT_FIFO_WR1END2_4", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_L_IMUX15_4", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_LH3_4", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_NW2A0_4", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_NE4C2_4", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_L_IMUX45_4", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_L_FAN5_4", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_WW2END2_4", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_L_FAN3_4", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_4", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "CMT_FIFO_ER1BEG1_4", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_4", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "CMT_FIFO_L_IMUX10_4", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_L_IMUX42_4", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_NE4BEG1_4", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX47_4", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_WW2A1_4", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_EE4C2_4", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_EE4C1_4", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_L_IMUX6_4", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_NW4END1_4", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_4", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "CMT_FIFO_WR1END0_4", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_L_IMUX31_4", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_LH10_4", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_EE2BEG2_4", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_L_IMUX24_4", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_SE2A1_4", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_L_BYP5_4", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_WW4END1_4", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_EL1BEG0_4", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_L_IMUX32_4", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_NW4A2_4", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_NW4END0_4", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_L_IMUX35_4", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_WW4END3_4", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_L_BYP2_4", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_4", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "CMT_FIFO_NE4C1_4", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_EE4A1_4", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_WW4END2_4", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_L_IMUX27_4", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_L_CLK0_4", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_L_IMUX3_4", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_NW4A3_4", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_WW4C1_4", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_LH8_4", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_NE4BEG2_4", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_SW2A2_4", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_L_IMUX34_4", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_WL1END3_4", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_SE4C0_4", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_WW4END0_4", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_NW2A3_4", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_L_BYP1_4", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_L_CLK1_4", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_WW2A3_4", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_EE4BEG3_4", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_SE4C2_4", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_LH2_4", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_LH6_4", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_L_IMUX12_4", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_LH11_4", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_NW4END3_4", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_L_IMUX8_4", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_IMUX7_4", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_WW2END1_4", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_EL1BEG2_4", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_EL1BEG3_4", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_L_IMUX33_4", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_EE2BEG0_4", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_FAN2_4", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_WW4B3_4", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_WL1END0_4", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_CTRL1_4", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_4", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "CMT_FIFO_L_IMUX2_4", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_WW4B0_4", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_4", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "CMT_FIFO_EE2A2_4", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_WW4B2_4", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_EE4BEG2_4", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_WL1END1_4", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_ER1BEG0_4", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_EE4C0_4", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_MONITOR_P_4", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CMT_FIFO_SE4C1_4", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_L_IMUX16_4", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_EE4B0_4", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_SW4A1_4", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_WW4C3_4", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_WW2A0_4", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_SW4A2_4", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_WW4C2_4", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_4", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "CMT_FIFO_NE4BEG3_4", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_NE4C3_4", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_LH4_4", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_LH9_4", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_WW4A3_4", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_L_CTRL0_4", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_4", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "CMT_FIFO_SW4END0_4", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_EE4B2_4", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_SW4A0_4", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_SE2A3_4", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_ER1BEG2_4", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_LH1_4", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_L_IMUX37_4", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_NW2A1_4", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_NW4END2_4", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_WW2A2_4", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_L_IMUX30_4", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_L_BYP3_4", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_LH5_4", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_4", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_SE4BEG0_4", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX18_4", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_L_IMUX11_4", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_L_IMUX5_4", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_WW2END0_4", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_MONITOR_N_4", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CMT_FIFO_SW4END2_4", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_L_IMUX44_4", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_SW4END3_4", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_NE4C0_4", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_L_IMUX13_4", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_L_IMUX21_4", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_4", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "CMT_FIFO_L_IMUX0_4", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_L_IMUX46_4", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_WR1END1_4", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_L_IMUX23_4", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_L_IMUX26_4", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_4", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "CMT_FIFO_SW4END1_4", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_SE4BEG2_4", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX25_4", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_WL1END2_4", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_4", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_4", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_4", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "CMT_FIFO_L_IMUX38_4", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_SW4A3_4", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_L_FAN6_4", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_L_BYP6_4", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_SE2A2_4", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_EL1BEG1_4", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_SE4C3_4", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_BYP0_4", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_WR1END3_4", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_L_FAN7_4", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_EE4A2_4", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_WW2END3_4", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_NE4BEG0_4", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_EE4BEG1_4", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_4", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "CMT_FIFO_L_IMUX22_4", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_4", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "CMT_FIFO_L_IMUX41_4", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_WW4B1_4", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_L_IMUX4_4", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_L_IMUX19_4", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_L_FAN0_4", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_WW4A0_4", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_EE2A1_4", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_NE2A2_4", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_LH12_4", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_4", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "CMT_FIFO_L_IMUX28_4", + "INT_INTERFACE_IMUX28" + ], + [ + "FIFO_DQS_IOTOPHASER_22", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_4", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "CMT_FIFO_ER1BEG3_4", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_L_FAN1_4", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_L_BYP7_4", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_SE4BEG1_4", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_4", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "CMT_FIFO_EE2BEG1_4", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_L_IMUX20_4", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_L_IMUX1_4", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_4", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "CMT_FIFO_L_IMUX29_4", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_L_IMUX39_4", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_NE2A3_4", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_EE2A0_4", + "INT_INTERFACE_EE2A0" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "PCIE_LOGIC_OUTS_B14_R_15", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_SW4END1_15", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_15", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_SE4BEG1_15", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_FAN2_R_15", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_EE4A0_15", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_NE4C3_15", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_NE2A2_15", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_IMUX42_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_15", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_ER1BEG0_15", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_SW4END3_15", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_WW4B2_15", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_LH9_15", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_IMUX43_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_IMUX34_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_WW4B3_15", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_IMUX15_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_WW4END2_15", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_15", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_NE4BEG3_15", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_WW2END1_15", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_SW2A0_15", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_EE4A3_15", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_IMUX28_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_NW4A2_15", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_NW4END0_15", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_IMUX35_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_15", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_WW4C2_15", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_15", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_IMUX27_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_NE4BEG1_15", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_15", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_15", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_WW2END2_15", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_IMUX33_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_ER1BEG2_15", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_SE4C0_15", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_SE4C1_15", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_SW2A3_15", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX0_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_WW2A3_15", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_NW4A0_15", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_BYP0_R_15", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_EE2A0_15", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_EE2BEG2_15", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_IMUX37_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_IMUX40_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_BYP1_R_15", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_15", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_SE2A2_15", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_NW2A1_15", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_IMUX31_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_IMUX24_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_WW4C3_15", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_15", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_SE4BEG2_15", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_EE4BEG3_15", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_IMUX5_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_IMUX29_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_IMUX25_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_WR1END3_15", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_WW4B0_15", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_SW4END0_15", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_NW2A3_15", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_15", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_IMUX13_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_EE4C3_15", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_FAN4_R_15", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_WW2A2_15", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_IMUX4_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_WW4C1_15", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_EL1BEG3_15", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_EE4BEG0_15", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_NW2A0_15", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_IMUX41_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_NW4A3_15", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_IMUX10_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_WW4END3_15", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_SE2A3_15", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_EE4B0_15", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_SW4A0_15", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_15", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_WW2END0_15", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_15", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_WW4A1_15", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_LH2_15", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_FAN5_R_15", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_IMUX2_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_NE4C0_15", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_WR1END2_15", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_IMUX19_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_NW4END3_15", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_15", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_WW2END3_15", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_EE4A2_15", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_WW4END0_15", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_LH10_15", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_WL1END3_15", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_15", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_IMUX12_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_WW2A1_15", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_IMUX23_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_EE4B3_15", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_BYP5_R_15", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_EL1BEG2_15", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_15", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_WL1END2_15", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_15", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_LH4_15", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_IMUX39_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_WL1END1_15", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_CLK0_R_15", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_EE4C1_15", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_WW4END1_15", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_15", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_NW4END1_15", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_15", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_LH11_15", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_WW2A0_15", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_BYP2_R_15", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_LH6_15", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_IMUX18_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_SW4END2_15", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_15", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_15", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_EE2A2_15", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_EE4BEG1_15", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_SE4BEG3_15", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_NE2A0_15", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_EE4BEG2_15", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_SE2A0_15", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_15", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_WR1END1_15", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_BYP3_R_15", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_IMUX11_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_EE4A1_15", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_IMUX45_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_EE4C2_15", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_IMUX47_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_NE2A1_15", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_IMUX30_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_EE4B1_15", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_NE4BEG2_15", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_ER1BEG3_15", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_ER1BEG1_15", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_IMUX16_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_IMUX26_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_WL1END0_15", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_LH8_15", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_LH1_15", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_CTRL1_R_15", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_WW4A2_15", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_SW4A2_15", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_BYP7_R_15", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_SW2A2_15", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_IMUX9_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_CLK1_R_15", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_EE2BEG3_15", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_EL1BEG1_15", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_LH3_15", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_FAN0_R_15", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_WW4A0_15", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_FAN1_R_15", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_EE2BEG1_15", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX44_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_NE4C1_15", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_EE2A3_15", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_SE4BEG0_15", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_LH12_15", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_EE4B2_15", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_WW4C0_15", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_FAN6_R_15", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_EE2A1_15", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_LH5_15", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_SW2A1_15", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_IMUX14_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_IMUX20_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_NW4A1_15", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_CTRL0_R_15", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_NE2A3_15", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_IMUX1_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_LH7_15", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_FAN3_R_15", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX7_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_SW4A1_15", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_BYP6_R_15", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_EE2BEG0_15", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_IMUX21_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_BYP4_R_15", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_IMUX17_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_NW4END2_15", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_FAN7_R_15", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_SW4A3_15", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_NW2A2_15", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_SE2A1_15", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_IMUX32_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_SE4C2_15", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_IMUX46_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_WW4B1_15", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_IMUX36_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_IMUX6_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_MONITOR_N_15", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_IMUX38_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_EL1BEG0_15", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_WR1END0_15", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_EE4C0_15", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_NE4BEG0_15", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_NE4C2_15", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_15", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_IMUX8_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_MONITOR_P_15", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_IMUX22_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_IMUX3_R_15", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_SE4C3_15", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_15", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_WW4A3_15", + "INT_INTERFACE_WW4A3" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "BRAM_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "BRAM_LH2_1", + "VBRK_LH2" + ], + [ + "BRAM_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "BRAM_LH5_1", + "VBRK_LH5" + ], + [ + "BRAM_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "BRAM_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "BRAM_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "BRAM_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "BRAM_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "BRAM_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "BRAM_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "BRAM_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "BRAM_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "BRAM_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "BRAM_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "BRAM_MONITOR_N_1", + "VBRK_MONITOR_N" + ], + [ + "BRAM_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "BRAM_LH3_1", + "VBRK_LH3" + ], + [ + "BRAM_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "BRAM_LH9_1", + "VBRK_LH9" + ], + [ + "BRAM_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "BRAM_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "BRAM_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "BRAM_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "BRAM_MONITOR_P_1", + "VBRK_MONITOR_P" + ], + [ + "BRAM_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "BRAM_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "BRAM_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "BRAM_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "BRAM_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "BRAM_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "BRAM_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "BRAM_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "BRAM_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "BRAM_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "BRAM_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "BRAM_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "BRAM_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "BRAM_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "BRAM_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "BRAM_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "BRAM_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "BRAM_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "BRAM_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "BRAM_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "BRAM_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "BRAM_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "BRAM_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "BRAM_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "BRAM_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "BRAM_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "BRAM_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "BRAM_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "BRAM_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "BRAM_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "BRAM_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "BRAM_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "BRAM_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "BRAM_LH10_1", + "VBRK_LH10" + ], + [ + "BRAM_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "BRAM_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "BRAM_LH7_1", + "VBRK_LH7" + ], + [ + "BRAM_LH11_1", + "VBRK_LH11" + ], + [ + "BRAM_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "BRAM_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "BRAM_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "BRAM_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "BRAM_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "BRAM_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "BRAM_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "BRAM_LH12_1", + "VBRK_LH12" + ], + [ + "BRAM_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "BRAM_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "BRAM_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "BRAM_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "BRAM_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "BRAM_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "BRAM_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "BRAM_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "BRAM_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "BRAM_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "BRAM_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "BRAM_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "BRAM_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "BRAM_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "BRAM_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "BRAM_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "BRAM_LH4_1", + "VBRK_LH4" + ], + [ + "BRAM_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "BRAM_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "BRAM_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "BRAM_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "BRAM_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "BRAM_LH8_1", + "VBRK_LH8" + ], + [ + "BRAM_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "BRAM_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "BRAM_LH1_1", + "VBRK_LH1" + ], + [ + "BRAM_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "BRAM_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "BRAM_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "BRAM_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "BRAM_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "BRAM_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "BRAM_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "BRAM_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "BRAM_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "BRAM_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "BRAM_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "BRAM_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "BRAM_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "BRAM_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "BRAM_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "BRAM_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "BRAM_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "BRAM_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "BRAM_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "BRAM_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "BRAM_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "BRAM_LH6_1", + "VBRK_LH6" + ], + [ + "BRAM_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "BRAM_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "BRAM_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "BRAM_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "BRAM_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "BRAM_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "BRAM_SW4A1_1", + "VBRK_SW4A1" + ] + ], + "tile_types": [ + "BRAM_L", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "CMT_TOP_EL1BEG1_11", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_EE4C0_11", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SE4BEG0_11", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH7_11", + "VBRK_LH7" + ], + [ + "CMT_TOP_ER1BEG1_11", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2A0_11", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH3_11", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C1_11", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH2_11", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW2A1_11", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NE2A3_11", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_MONITOR_N_11", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_ER1BEG2_11", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NW4END2_11", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE4BEG3_11", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C3_11", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE2A2_11", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_SW2A0_11", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW4A1_11", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_LH9_11", + "VBRK_LH9" + ], + [ + "CMT_TOP_SE4C3_11", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WR1END0_11", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_11", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EL1BEG2_11", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_NE4BEG2_11", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_11", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4C2_11", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4C2_11", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW4C3_11", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_LH4_11", + "VBRK_LH4" + ], + [ + "CMT_TOP_NE4C2_11", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EE4BEG0_11", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NE2A0_11", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NW4A1_11", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG1_11", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4C1_11", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_EE2A1_11", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END1_11", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SE4C2_11", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A0_11", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE4B0_11", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_11", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW4B0_11", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C0_11", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4BEG2_11", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_LH11_11", + "VBRK_LH11" + ], + [ + "CMT_TOP_MONITOR_P_11", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_EE2BEG3_11", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END2_11", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_11", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4A2_11", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EE4BEG3_11", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_NW4END3_11", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_LH1_11", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE4C0_11", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SW4END3_11", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SW4END1_11", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_11", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END1_11", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_LH8_11", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW2A3_11", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SW4A0_11", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_11", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW4B3_11", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW4A2_11", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4B2_11", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE2A0_11", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WW2END3_11", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EE4A3_11", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SE4C1_11", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_ER1BEG0_11", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_NW4END1_11", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A3_11", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4A2_11", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4C3_11", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW2A0_11", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NE2A1_11", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW4A3_11", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NW2A3_11", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NE4BEG3_11", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_WW2A2_11", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG0_11", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW2END0_11", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2A3_11", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4A2_11", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG2_11", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW2A1_11", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SW4END2_11", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG0_11", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE4BEG1_11", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE4C1_11", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG1_11", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EE2BEG2_11", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SW2A1_11", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE2A2_11", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WR1END1_11", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW2A3_11", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW2A0_11", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW4B1_11", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C0_11", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4BEG1_11", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH12_11", + "VBRK_LH12" + ], + [ + "CMT_TOP_WW4END2_11", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW2A2_11", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_EE4A1_11", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH5_11", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4A0_11", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_SE2A1_11", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END2_11", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WL1END3_11", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_ER1BEG3_11", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WW4B2_11", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WL1END0_11", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW4END0_11", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_11", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A3_11", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4END3_11", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_11", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4A0_11", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A1_11", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH10_11", + "VBRK_LH10" + ], + [ + "CMT_TOP_SW4END0_11", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW4END1_11", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE2A2_11", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW2A2_11", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG0_11", + "VBRK_EL1BEG0" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_LH8", + "BRAM_LH8_0" + ], + [ + "INT_INTERFACE_EL1BEG3", + "BRAM_EL1BEG3_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX24", + "BRAM_IMUX24_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_0" + ], + [ + "INT_INTERFACE_EL1BEG0", + "BRAM_EL1BEG0_0" + ], + [ + "INT_INTERFACE_WW4B2", + "BRAM_WW4B2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX26", + "BRAM_IMUX26_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX39", + "BRAM_IMUX39_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B23", + "BRAM_LOGIC_OUTS_B23_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX43", + "BRAM_IMUX43_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX4", + "BRAM_IMUX4_UTURN_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B13", + "BRAM_LOGIC_OUTS_B13_0" + ], + [ + "INT_INTERFACE_EL1BEG2", + "BRAM_EL1BEG2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX29", + "BRAM_IMUX29_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX41", + "BRAM_IMUX41_UTURN_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B18", + "BRAM_LOGIC_OUTS_B18_0" + ], + [ + "INT_INTERFACE_EE4B1", + "BRAM_EE4B1_0" + ], + [ + "INT_INTERFACE_NW4A3", + "BRAM_NW4A3_0" + ], + [ + "INT_INTERFACE_WW4B0", + "BRAM_WW4B0_0" + ], + [ + "INT_INTERFACE_BYP4", + "BRAM_BYP4_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_0" + ], + [ + "INT_INTERFACE_WR1END1", + "BRAM_WR1END1_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX34", + "BRAM_IMUX34_UTURN_0" + ], + [ + "INT_INTERFACE_WW2A2", + "BRAM_WW2A2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX38", + "BRAM_IMUX38_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX18", + "BRAM_IMUX18_UTURN_0" + ], + [ + "INT_INTERFACE_CTRL0", + "BRAM_CTRL0_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX35", + "BRAM_IMUX35_UTURN_0" + ], + [ + "INT_INTERFACE_EE4C1", + "BRAM_EE4C1_0" + ], + [ + "INT_INTERFACE_SE4C3", + "BRAM_SE4C3_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B20", + "BRAM_LOGIC_OUTS_B20_0" + ], + [ + "INT_INTERFACE_FAN0", + "BRAM_FAN0_0" + ], + [ + "INT_INTERFACE_SW2A0", + "BRAM_SW2A0_0" + ], + [ + "INT_INTERFACE_FAN4", + "BRAM_FAN4_0" + ], + [ + "INT_INTERFACE_EE4B3", + "BRAM_EE4B3_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX36", + "BRAM_IMUX36_UTURN_0" + ], + [ + "INT_INTERFACE_NE2A2", + "BRAM_NE2A2_0" + ], + [ + "INT_INTERFACE_NE4C0", + "BRAM_NE4C0_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX44", + "BRAM_IMUX44_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX20", + "BRAM_IMUX20_UTURN_0" + ], + [ + "INT_INTERFACE_WR1END2", + "BRAM_WR1END2_0" + ], + [ + "INT_INTERFACE_NE2A1", + "BRAM_NE2A1_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX36", + "BRAM_IMUX36_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B2", + "BRAM_LOGIC_OUTS_B2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX10", + "BRAM_IMUX10_UTURN_0" + ], + [ + "INT_INTERFACE_LH3", + "BRAM_LH3_0" + ], + [ + "INT_INTERFACE_NW4END2", + "BRAM_NW4END2_0" + ], + [ + "INT_INTERFACE_WW4C0", + "BRAM_WW4C0_0" + ], + [ + "INT_INTERFACE_WW4END1", + "BRAM_WW4END1_0" + ], + [ + "INT_INTERFACE_SE2A0", + "BRAM_SE2A0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B16", + "BRAM_LOGIC_OUTS_B16_0" + ], + [ + "INT_INTERFACE_WW4A2", + "BRAM_WW4A2_0" + ], + [ + "INT_INTERFACE_WW4A0", + "BRAM_WW4A0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B6", + "BRAM_LOGIC_OUTS_B6_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B4", + "BRAM_LOGIC_OUTS_B4_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B10", + "BRAM_LOGIC_OUTS_B10_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX27", + "BRAM_IMUX27_UTURN_0" + ], + [ + "INT_INTERFACE_EE2A0", + "BRAM_EE2A0_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_0" + ], + [ + "INT_INTERFACE_SE4C1", + "BRAM_SE4C1_0" + ], + [ + "INT_INTERFACE_NE2A3", + "BRAM_NE2A3_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX46", + "BRAM_IMUX46_UTURN_0" + ], + [ + "INT_INTERFACE_NE4BEG1", + "BRAM_NE4BEG1_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_0" + ], + [ + "INT_INTERFACE_FAN6", + "BRAM_FAN6_0" + ], + [ + "INT_INTERFACE_WW2END2", + "BRAM_WW2END2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX23", + "BRAM_IMUX23_UTURN_0" + ], + [ + "INT_INTERFACE_SW2A2", + "BRAM_SW2A2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_0" + ], + [ + "INT_INTERFACE_EE2BEG3", + "BRAM_EE2BEG3_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX6", + "BRAM_IMUX6_UTURN_0" + ], + [ + "INT_INTERFACE_WW4A1", + "BRAM_WW4A1_0" + ], + [ + "INT_INTERFACE_NW4A0", + "BRAM_NW4A0_0" + ], + [ + "INT_INTERFACE_SW4A2", + "BRAM_SW4A2_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B9", + "BRAM_LOGIC_OUTS_B9_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_0" + ], + [ + "INT_INTERFACE_BYP1", + "BRAM_BYP1_0" + ], + [ + "INT_INTERFACE_BYP5", + "BRAM_BYP5_0" + ], + [ + "INT_INTERFACE_SW4END2", + "BRAM_SW4END2_0" + ], + [ + "INT_INTERFACE_LH9", + "BRAM_LH9_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX47", + "BRAM_IMUX47_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX45", + "BRAM_IMUX45_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_0" + ], + [ + "INT_INTERFACE_LH2", + "BRAM_LH2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_0" + ], + [ + "INT_INTERFACE_EE2A2", + "BRAM_EE2A2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX37", + "BRAM_IMUX37_UTURN_0" + ], + [ + "INT_INTERFACE_BYP3", + "BRAM_BYP3_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX17", + "BRAM_IMUX17_UTURN_0" + ], + [ + "INT_INTERFACE_EE4A3", + "BRAM_EE4A3_0" + ], + [ + "INT_INTERFACE_SW4END1", + "BRAM_SW4END1_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX32", + "BRAM_IMUX32_0" + ], + [ + "INT_INTERFACE_WW2A3", + "BRAM_WW2A3_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX29", + "BRAM_IMUX29_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX31", + "BRAM_IMUX31_UTURN_0" + ], + [ + "INT_INTERFACE_NW2A2", + "BRAM_NW2A2_0" + ], + [ + "INT_INTERFACE_NW4END1", + "BRAM_NW4END1_0" + ], + [ + "INT_INTERFACE_SW2A1", + "BRAM_SW2A1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B8", + "BRAM_LOGIC_OUTS_B8_0" + ], + [ + "INT_INTERFACE_FAN7", + "BRAM_FAN7_0" + ], + [ + "INT_INTERFACE_EE4C0", + "BRAM_EE4C0_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX13", + "BRAM_IMUX13_UTURN_0" + ], + [ + "INT_INTERFACE_SE4BEG0", + "BRAM_SE4BEG0_0" + ], + [ + "INT_INTERFACE_EE4C2", + "BRAM_EE4C2_0" + ], + [ + "INT_INTERFACE_CLK0", + "BRAM_CLK0_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX35", + "BRAM_IMUX35_0" + ], + [ + "INT_INTERFACE_FAN2", + "BRAM_FAN2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX34", + "BRAM_IMUX34_0" + ], + [ + "INT_INTERFACE_WL1END3", + "BRAM_WL1END3_0" + ], + [ + "INT_INTERFACE_SW2A3", + "BRAM_SW2A3_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX40", + "BRAM_IMUX40_0" + ], + [ + "INT_INTERFACE_EE4BEG1", + "BRAM_EE4BEG1_0" + ], + [ + "INT_INTERFACE_SE4C0", + "BRAM_SE4C0_0" + ], + [ + "INT_INTERFACE_LH6", + "BRAM_LH6_0" + ], + [ + "INT_INTERFACE_NE4BEG2", + "BRAM_NE4BEG2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX23", + "BRAM_IMUX23_0" + ], + [ + "INT_INTERFACE_SE2A3", + "BRAM_SE2A3_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX12", + "BRAM_IMUX12_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX5", + "BRAM_IMUX5_UTURN_0" + ], + [ + "INT_INTERFACE_WW2END3", + "BRAM_WW2END3_0" + ], + [ + "INT_INTERFACE_FAN5", + "BRAM_FAN5_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX9", + "BRAM_IMUX9_UTURN_0" + ], + [ + "INT_INTERFACE_EE4B0", + "BRAM_EE4B0_0" + ], + [ + "INT_INTERFACE_LH11", + "BRAM_LH11_0" + ], + [ + "INT_INTERFACE_EE4B2", + "BRAM_EE4B2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX22", + "BRAM_IMUX22_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX3", + "BRAM_IMUX3_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX47", + "BRAM_IMUX47_0" + ], + [ + "INT_INTERFACE_LH1", + "BRAM_LH1_0" + ], + [ + "INT_INTERFACE_WW2END0", + "BRAM_WW2END0_0" + ], + [ + "INT_INTERFACE_WW4A3", + "BRAM_WW4A3_0" + ], + [ + "INT_INTERFACE_BYP6", + "BRAM_BYP6_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX32", + "BRAM_IMUX32_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX26", + "BRAM_IMUX26_0" + ], + [ + "INT_INTERFACE_NW4END3", + "BRAM_NW4END3_0" + ], + [ + "INT_INTERFACE_EE4A1", + "BRAM_EE4A1_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX14", + "BRAM_IMUX14_UTURN_0" + ], + [ + "INT_INTERFACE_WL1END1", + "BRAM_WL1END1_0" + ], + [ + "INT_INTERFACE_WW4END0", + "BRAM_WW4END0_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX30", + "BRAM_IMUX30_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_0" + ], + [ + "INT_INTERFACE_WW4C2", + "BRAM_WW4C2_0" + ], + [ + "INT_INTERFACE_SW4A0", + "BRAM_SW4A0_0" + ], + [ + "INT_INTERFACE_WW4END2", + "BRAM_WW4END2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX28", + "BRAM_IMUX28_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX8", + "BRAM_IMUX8_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX28", + "BRAM_IMUX28_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX25", + "BRAM_IMUX25_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX44", + "BRAM_IMUX44_0" + ], + [ + "INT_INTERFACE_NE2A0", + "BRAM_NE2A0_0" + ], + [ + "INT_INTERFACE_FAN1", + "BRAM_FAN1_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX7", + "BRAM_IMUX7_UTURN_0" + ], + [ + "INT_INTERFACE_SW4END0", + "BRAM_SW4END0_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX45", + "BRAM_IMUX45_0" + ], + [ + "INT_INTERFACE_ER1BEG2", + "BRAM_ER1BEG2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX16", + "BRAM_IMUX16_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX38", + "BRAM_IMUX38_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX33", + "BRAM_IMUX33_0" + ], + [ + "INT_INTERFACE_NW4A1", + "BRAM_NW4A1_0" + ], + [ + "INT_INTERFACE_EE2A1", + "BRAM_EE2A1_0" + ], + [ + "INT_INTERFACE_SE4C2", + "BRAM_SE4C2_0" + ], + [ + "INT_INTERFACE_WW4C1", + "BRAM_WW4C1_0" + ], + [ + "INT_INTERFACE_SE4BEG2", + "BRAM_SE4BEG2_0" + ], + [ + "INT_INTERFACE_WL1END0", + "BRAM_WL1END0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B11", + "BRAM_LOGIC_OUTS_B11_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX41", + "BRAM_IMUX41_0" + ], + [ + "INT_INTERFACE_NW2A3", + "BRAM_NW2A3_0" + ], + [ + "INT_INTERFACE_NE4C1", + "BRAM_NE4C1_0" + ], + [ + "INT_INTERFACE_NE4BEG3", + "BRAM_NE4BEG3_0" + ], + [ + "INT_INTERFACE_BYP7", + "BRAM_BYP7_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B19", + "BRAM_LOGIC_OUTS_B19_0" + ], + [ + "INT_INTERFACE_EE4A0", + "BRAM_EE4A0_0" + ], + [ + "INT_INTERFACE_EE4BEG0", + "BRAM_EE4BEG0_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX30", + "BRAM_IMUX30_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX21", + "BRAM_IMUX21_0" + ], + [ + "INT_INTERFACE_LH5", + "BRAM_LH5_0" + ], + [ + "INT_INTERFACE_NW4A2", + "BRAM_NW4A2_0" + ], + [ + "INT_INTERFACE_NW2A1", + "BRAM_NW2A1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B7", + "BRAM_LOGIC_OUTS_B7_0" + ], + [ + "INT_INTERFACE_LH4", + "BRAM_LH4_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B3", + "BRAM_LOGIC_OUTS_B3_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B5", + "BRAM_LOGIC_OUTS_B5_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B21", + "BRAM_LOGIC_OUTS_B21_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_0" + ], + [ + "INT_INTERFACE_SW4END3", + "BRAM_SW4END3_0" + ], + [ + "INT_INTERFACE_WL1END2", + "BRAM_WL1END2_0" + ], + [ + "INT_INTERFACE_WW4B3", + "BRAM_WW4B3_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX15", + "BRAM_IMUX15_UTURN_0" + ], + [ + "INT_INTERFACE_BYP2", + "BRAM_BYP2_0" + ], + [ + "INT_INTERFACE_NE4C3", + "BRAM_NE4C3_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B1", + "BRAM_LOGIC_OUTS_B1_0" + ], + [ + "INT_INTERFACE_WR1END0", + "BRAM_WR1END0_0" + ], + [ + "INT_INTERFACE_LH7", + "BRAM_LH7_0" + ], + [ + "INT_INTERFACE_ER1BEG1", + "BRAM_ER1BEG1_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX21", + "BRAM_IMUX21_UTURN_0" + ], + [ + "INT_INTERFACE_WW2END1", + "BRAM_WW2END1_0" + ], + [ + "INT_INTERFACE_EE4BEG2", + "BRAM_EE4BEG2_0" + ], + [ + "INT_INTERFACE_WW4C3", + "BRAM_WW4C3_0" + ], + [ + "INT_INTERFACE_CLK1", + "BRAM_CLK1_0" + ], + [ + "INT_INTERFACE_LH12", + "BRAM_LH12_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX42", + "BRAM_IMUX42_UTURN_0" + ], + [ + "INT_INTERFACE_EE2BEG0", + "BRAM_EE2BEG0_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX42", + "BRAM_IMUX42_0" + ], + [ + "INT_INTERFACE_WW2A1", + "BRAM_WW2A1_0" + ], + [ + "INT_INTERFACE_WW4B1", + "BRAM_WW4B1_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX31", + "BRAM_IMUX31_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX46", + "BRAM_IMUX46_0" + ], + [ + "INT_INTERFACE_EE4A2", + "BRAM_EE4A2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX0", + "BRAM_IMUX0_UTURN_0" + ], + [ + "INT_INTERFACE_SE2A2", + "BRAM_SE2A2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX2", + "BRAM_IMUX2_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX37", + "BRAM_IMUX37_0" + ], + [ + "INT_INTERFACE_ER1BEG3", + "BRAM_ER1BEG3_0" + ], + [ + "INT_INTERFACE_FAN3", + "BRAM_FAN3_0" + ], + [ + "INT_INTERFACE_EE4BEG3", + "BRAM_EE4BEG3_0" + ], + [ + "INT_INTERFACE_LH10", + "BRAM_LH10_0" + ], + [ + "INT_INTERFACE_EE2BEG1", + "BRAM_EE2BEG1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B22", + "BRAM_LOGIC_OUTS_B22_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B12", + "BRAM_LOGIC_OUTS_B12_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX19", + "BRAM_IMUX19_UTURN_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B14", + "BRAM_LOGIC_OUTS_B14_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX39", + "BRAM_IMUX39_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX27", + "BRAM_IMUX27_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX22", + "BRAM_IMUX22_UTURN_0" + ], + [ + "INT_INTERFACE_SW4A1", + "BRAM_SW4A1_0" + ], + [ + "INT_INTERFACE_BYP0", + "BRAM_BYP0_0" + ], + [ + "INT_INTERFACE_WW4END3", + "BRAM_WW4END3_0" + ], + [ + "INT_INTERFACE_MONITOR_P", + "BRAM_MONITOR_P_0" + ], + [ + "INT_INTERFACE_NE4C2", + "BRAM_NE4C2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_0" + ], + [ + "INT_INTERFACE_EE2BEG2", + "BRAM_EE2BEG2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX40", + "BRAM_IMUX40_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX33", + "BRAM_IMUX33_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX43", + "BRAM_IMUX43_0" + ], + [ + "INT_INTERFACE_SE4BEG1", + "BRAM_SE4BEG1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B15", + "BRAM_LOGIC_OUTS_B15_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX25", + "BRAM_IMUX25_0" + ], + [ + "INT_INTERFACE_EE4C3", + "BRAM_EE4C3_0" + ], + [ + "INT_INTERFACE_MONITOR_N", + "BRAM_MONITOR_N_0" + ], + [ + "INT_INTERFACE_SE4BEG3", + "BRAM_SE4BEG3_0" + ], + [ + "INT_INTERFACE_EL1BEG1", + "BRAM_EL1BEG1_0" + ], + [ + "INT_INTERFACE_CTRL1", + "BRAM_CTRL1_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX1", + "BRAM_IMUX1_UTURN_0" + ], + [ + "INT_INTERFACE_SW4A3", + "BRAM_SW4A3_0" + ], + [ + "INT_INTERFACE_WR1END3", + "BRAM_WR1END3_0" + ], + [ + "INT_INTERFACE_NW4END0", + "BRAM_NW4END0_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B17", + "BRAM_LOGIC_OUTS_B17_0" + ], + [ + "INT_INTERFACE_WW2A0", + "BRAM_WW2A0_0" + ], + [ + "INT_INTERFACE_EE2A3", + "BRAM_EE2A3_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_0" + ], + [ + "INT_INTERFACE_NE4BEG0", + "BRAM_NE4BEG0_0" + ], + [ + "INT_INTERFACE_NW2A0", + "BRAM_NW2A0_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX24", + "BRAM_IMUX24_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX11", + "BRAM_IMUX11_UTURN_0" + ], + [ + "INT_INTERFACE_SE2A1", + "BRAM_SE2A1_0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B0", + "BRAM_LOGIC_OUTS_B0_0" + ], + [ + "INT_INTERFACE_ER1BEG0", + "BRAM_ER1BEG0_0" + ] + ], + "tile_types": [ + "BRAM_INT_INTERFACE_R", + "BRAM_R" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLBLL_EE4BEG1", + "VFRAME_EE4BEG1" + ], + [ + "CLBLL_WW2A2", + "VFRAME_WW2A2" + ], + [ + "CLBLL_SW2A2", + "VFRAME_SW2A2" + ], + [ + "CLBLL_WR1END2", + "VFRAME_WR1END2" + ], + [ + "CLBLL_SW4A3", + "VFRAME_SW4A3" + ], + [ + "CLBLL_SE4C3", + "VFRAME_SE4C3" + ], + [ + "CLBLL_NW4A0", + "VFRAME_NW4A0" + ], + [ + "CLBLL_ER1BEG1", + "VFRAME_ER1BEG1" + ], + [ + "CLBLL_NW4END0", + "VFRAME_NW4END0" + ], + [ + "CLBLL_EE4C1", + "VFRAME_EE4C1" + ], + [ + "CLBLL_NE2A0", + "VFRAME_NE2A0" + ], + [ + "CLBLL_WW4A3", + "VFRAME_WW4A3" + ], + [ + "CLBLL_WW4B2", + "VFRAME_WW4B2" + ], + [ + "CLBLL_EL1BEG3", + "VFRAME_EL1BEG3" + ], + [ + "CLBLL_EL1BEG0", + "VFRAME_EL1BEG0" + ], + [ + "CLBLL_SW4A1", + "VFRAME_SW4A1" + ], + [ + "CLBLL_NW4END2", + "VFRAME_NW4END2" + ], + [ + "CLBLL_NE2A3", + "VFRAME_NE2A3" + ], + [ + "CLBLL_NW4END1", + "VFRAME_NW4END1" + ], + [ + "CLBLL_EE4C2", + "VFRAME_EE4C2" + ], + [ + "CLBLL_NE4BEG2", + "VFRAME_NE4BEG2" + ], + [ + "CLBLL_WW2END0", + "VFRAME_WW2END0" + ], + [ + "CLBLL_MONITOR_N", + "VFRAME_MONITOR_N" + ], + [ + "CLBLL_ER1BEG2", + "VFRAME_ER1BEG2" + ], + [ + "CLBLL_NW4A2", + "VFRAME_NW4A2" + ], + [ + "CLBLL_LH4", + "VFRAME_LH4" + ], + [ + "CLBLL_NE2A1", + "VFRAME_NE2A1" + ], + [ + "CLBLL_LH3", + "VFRAME_LH3" + ], + [ + "CLBLL_LH5", + "VFRAME_LH5" + ], + [ + "CLBLL_WW4C0", + "VFRAME_WW4C0" + ], + [ + "CLBLL_SE2A2", + "VFRAME_SE2A2" + ], + [ + "CLBLL_EE2BEG0", + "VFRAME_EE2BEG0" + ], + [ + "CLBLL_EE4B1", + "VFRAME_EE4B1" + ], + [ + "CLBLL_NE4BEG3", + "VFRAME_NE4BEG3" + ], + [ + "CLBLL_WW4C1", + "VFRAME_WW4C1" + ], + [ + "CLBLL_MONITOR_P", + "VFRAME_MONITOR_P" + ], + [ + "CLBLL_SE4BEG0", + "VFRAME_SE4BEG0" + ], + [ + "CLBLL_LH10", + "VFRAME_LH10" + ], + [ + "CLBLL_WW2A0", + "VFRAME_WW2A0" + ], + [ + "CLBLL_EE4B3", + "VFRAME_EE4B3" + ], + [ + "CLBLL_SW4A0", + "VFRAME_SW4A0" + ], + [ + "CLBLL_EE4B2", + "VFRAME_EE4B2" + ], + [ + "CLBLL_WL1END2", + "VFRAME_WL1END2" + ], + [ + "CLBLL_WW4C2", + "VFRAME_WW4C2" + ], + [ + "CLBLL_WR1END0", + "VFRAME_WR1END0" + ], + [ + "CLBLL_LH8", + "VFRAME_LH8" + ], + [ + "CLBLL_WW2END2", + "VFRAME_WW2END2" + ], + [ + "CLBLL_WW4A1", + "VFRAME_WW4A1" + ], + [ + "CLBLL_SE2A1", + "VFRAME_SE2A1" + ], + [ + "CLBLL_EE2A1", + "VFRAME_EE2A1" + ], + [ + "CLBLL_EE4A2", + "VFRAME_EE4A2" + ], + [ + "CLBLL_LH11", + "VFRAME_LH11" + ], + [ + "CLBLL_WL1END3", + "VFRAME_WL1END3" + ], + [ + "CLBLL_WW4A2", + "VFRAME_WW4A2" + ], + [ + "CLBLL_LH12", + "VFRAME_LH12" + ], + [ + "CLBLL_WW2A1", + "VFRAME_WW2A1" + ], + [ + "CLBLL_LH7", + "VFRAME_LH7" + ], + [ + "CLBLL_EE4C0", + "VFRAME_EE4C0" + ], + [ + "CLBLL_EL1BEG1", + "VFRAME_EL1BEG1" + ], + [ + "CLBLL_EE2A2", + "VFRAME_EE2A2" + ], + [ + "CLBLL_WR1END1", + "VFRAME_WR1END1" + ], + [ + "CLBLL_EE4BEG2", + "VFRAME_EE4BEG2" + ], + [ + "CLBLL_EE4BEG3", + "VFRAME_EE4BEG3" + ], + [ + "CLBLL_SW4END3", + "VFRAME_SW4END3" + ], + [ + "CLBLL_LH6", + "VFRAME_LH6" + ], + [ + "CLBLL_NE4BEG1", + "VFRAME_NE4BEG1" + ], + [ + "CLBLL_SE4C2", + "VFRAME_SE4C2" + ], + [ + "CLBLL_NW4END3", + "VFRAME_NW4END3" + ], + [ + "CLBLL_SE4BEG3", + "VFRAME_SE4BEG3" + ], + [ + "CLBLL_SE4BEG1", + "VFRAME_SE4BEG1" + ], + [ + "CLBLL_WW4END3", + "VFRAME_WW4END3" + ], + [ + "CLBLL_WL1END1", + "VFRAME_WL1END1" + ], + [ + "CLBLL_NW4A3", + "VFRAME_NW4A3" + ], + [ + "CLBLL_WW4END1", + "VFRAME_WW4END1" + ], + [ + "CLBLL_EE4B0", + "VFRAME_EE4B0" + ], + [ + "CLBLL_NW4A1", + "VFRAME_NW4A1" + ], + [ + "CLBLL_SW4END0", + "VFRAME_SW4END0" + ], + [ + "CLBLL_WW4END0", + "VFRAME_WW4END0" + ], + [ + "CLBLL_EE4A0", + "VFRAME_EE4A0" + ], + [ + "CLBLL_EE2A0", + "VFRAME_EE2A0" + ], + [ + "CLBLL_NW2A2", + "VFRAME_NW2A2" + ], + [ + "CLBLL_WL1END0", + "VFRAME_WL1END0" + ], + [ + "CLBLL_EE2BEG1", + "VFRAME_EE2BEG1" + ], + [ + "CLBLL_LH2", + "VFRAME_LH2" + ], + [ + "CLBLL_ER1BEG3", + "VFRAME_ER1BEG3" + ], + [ + "CLBLL_LH9", + "VFRAME_LH9" + ], + [ + "CLBLL_SE4C1", + "VFRAME_SE4C1" + ], + [ + "CLBLL_LH1", + "VFRAME_LH1" + ], + [ + "CLBLL_SE4BEG2", + "VFRAME_SE4BEG2" + ], + [ + "CLBLL_EE2A3", + "VFRAME_EE2A3" + ], + [ + "CLBLL_NE4C1", + "VFRAME_NE4C1" + ], + [ + "CLBLL_WW4A0", + "VFRAME_WW4A0" + ], + [ + "CLBLL_EE4A1", + "VFRAME_EE4A1" + ], + [ + "CLBLL_SW4A2", + "VFRAME_SW4A2" + ], + [ + "CLBLL_SE2A3", + "VFRAME_SE2A3" + ], + [ + "CLBLL_SW4END1", + "VFRAME_SW4END1" + ], + [ + "CLBLL_EE4A3", + "VFRAME_EE4A3" + ], + [ + "CLBLL_SW2A1", + "VFRAME_SW2A1" + ], + [ + "CLBLL_NE4C3", + "VFRAME_NE4C3" + ], + [ + "CLBLL_EE4C3", + "VFRAME_EE4C3" + ], + [ + "CLBLL_EE4BEG0", + "VFRAME_EE4BEG0" + ], + [ + "CLBLL_NW2A1", + "VFRAME_NW2A1" + ], + [ + "CLBLL_NW2A3", + "VFRAME_NW2A3" + ], + [ + "CLBLL_SW2A0", + "VFRAME_SW2A0" + ], + [ + "CLBLL_WW4END2", + "VFRAME_WW4END2" + ], + [ + "CLBLL_NE4C0", + "VFRAME_NE4C0" + ], + [ + "CLBLL_EE2BEG2", + "VFRAME_EE2BEG2" + ], + [ + "CLBLL_NW2A0", + "VFRAME_NW2A0" + ], + [ + "CLBLL_WR1END3", + "VFRAME_WR1END3" + ], + [ + "CLBLL_NE4C2", + "VFRAME_NE4C2" + ], + [ + "CLBLL_NE2A2", + "VFRAME_NE2A2" + ], + [ + "CLBLL_SW2A3", + "VFRAME_SW2A3" + ], + [ + "CLBLL_SE4C0", + "VFRAME_SE4C0" + ], + [ + "CLBLL_SE2A0", + "VFRAME_SE2A0" + ], + [ + "CLBLL_WW4B0", + "VFRAME_WW4B0" + ], + [ + "CLBLL_WW2END1", + "VFRAME_WW2END1" + ], + [ + "CLBLL_SW4END2", + "VFRAME_SW4END2" + ], + [ + "CLBLL_WW4B3", + "VFRAME_WW4B3" + ], + [ + "CLBLL_EL1BEG2", + "VFRAME_EL1BEG2" + ], + [ + "CLBLL_WW2A3", + "VFRAME_WW2A3" + ], + [ + "CLBLL_ER1BEG0", + "VFRAME_ER1BEG0" + ], + [ + "CLBLL_WW4B1", + "VFRAME_WW4B1" + ], + [ + "CLBLL_WW4C3", + "VFRAME_WW4C3" + ], + [ + "CLBLL_NE4BEG0", + "VFRAME_NE4BEG0" + ], + [ + "CLBLL_WW2END3", + "VFRAME_WW2END3" + ], + [ + "CLBLL_EE2BEG3", + "VFRAME_EE2BEG3" + ] + ], + "tile_types": [ + "CLBLL_R", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + -6 + ], + "wire_pairs": [ + [ + "CFG_CENTER_IMUX11_16", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX6_16", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_CTRL0_16", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_NW2A1_16", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_SE4C0_16", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_IMUX42_16", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_EE4A1_16", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_SE4C1_16", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_LH7_16", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_LH2_16", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_SW4END0_16", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_SW4A0_16", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_EE4B1_16", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_SW4A1_16", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_EE4B0_16", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_SW2A1_16", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_EE4C3_16", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE4BEG0_16", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_IMUX37_16", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_WW4C1_16", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_NW4A3_16", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_NE2A2_16", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_LH6_16", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_LH1_16", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_BYP2_16", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_IMUX8_16", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW2END0_16", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_CTRL1_16", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_EE4A2_16", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX31_16", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_FAN5_16", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_IMUX46_16", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_LH11_16", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_NE4C1_16", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_EE4A3_16", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_WW4A1_16", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_FAN7_16", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX7_16", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_SW4END2_16", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_IMUX25_16", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_IMUX36_16", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_FAN0_16", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_NW4A0_16", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NE2A0_16", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX12_16", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_ER1BEG0_16", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_FAN3_16", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_IMUX43_16", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX30_16", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_WW4C3_16", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_SE2A0_16", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_IMUX3_16", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_WL1END3_16", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_IMUX34_16", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_IMUX32_16", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_SW4A2_16", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_WW4END1_16", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_SE4BEG1_16", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_WW2END2_16", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_NE4BEG0_16", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_EE4BEG2_16", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_NW4END3_16", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_WW4B3_16", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_WW4END3_16", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX41_16", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_WW4A2_16", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_IMUX1_16", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_NW2A0_16", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_IMUX47_16", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_EE4BEG3_16", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG1_16", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_LH4_16", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_SE4C2_16", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_LH5_16", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_SE2A3_16", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_CLK0_16", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_NW4END1_16", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SE4BEG3_16", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX44_16", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_BYP3_16", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_IMUX17_16", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX20_16", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_EE4C1_16", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_WW4A3_16", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_EL1BEG3_16", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_IMUX15_16", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_IMUX35_16", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_EE4C2_16", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_LH9_16", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EL1BEG2_16", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_WR1END3_16", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_NE2A1_16", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_ER1BEG1_16", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_EE2BEG3_16", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_EL1BEG0_16", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_ER1BEG2_16", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_EE4C0_16", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_EE2BEG0_16", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX13_16", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_EE4B3_16", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_IMUX4_16", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_NW4A2_16", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_FAN4_16", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_IMUX40_16", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_IMUX18_16", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_FAN2_16", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_IMUX22_16", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW2A0_16", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_WW4C0_16", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_NW2A2_16", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_SW2A0_16", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_SE2A2_16", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX16_16", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX2_16", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_FAN1_16", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX24_16", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_IMUX29_16", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_BYP5_16", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_EE2A1_16", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_ER1BEG3_16", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_SW4A3_16", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_WL1END2_16", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WW4A0_16", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_EE2A3_16", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_IMUX45_16", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_FAN6_16", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_NE4C0_16", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_IMUX26_16", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX5_16", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX21_16", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_IMUX23_16", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NE4BEG3_16", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NE2A3_16", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_NE4BEG2_16", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW4B0_16", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_LH8_16", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_EE2A2_16", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_SW4END3_16", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_EE4A0_16", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_NE4C2_16", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_SW4END1_16", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_IMUX28_16", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX10_16", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_EE4BEG1_16", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_EE2BEG2_16", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_EE4B2_16", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_CLK1_16", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_SW2A3_16", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_BYP7_16", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_BYP6_16", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_SW2A2_16", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_NW4A1_16", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_WW4B1_16", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_NW2A3_16", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_WW2A3_16", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_BYP0_16", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX27_16", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_WL1END1_16", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_NW4END0_16", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_WW2A1_16", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_BYP4_16", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WW4END2_16", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX39_16", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_WW2END3_16", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_NE4BEG1_16", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG2_16", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_LH3_16", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_WW2A2_16", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_SE2A1_16", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_WL1END0_16", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_WR1END2_16", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_LH12_16", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_LH10_16", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_SE4C3_16", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_WR1END1_16", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_IMUX9_16", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX19_16", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_IMUX0_16", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW4C2_16", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WW4END0_16", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_EE2BEG1_16", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_EE2A0_16", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WR1END0_16", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_SE4BEG0_16", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_IMUX14_16", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_BYP1_16", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW2END1_16", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_NE4C3_16", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_IMUX38_16", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX33_16", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_NW4END2_16", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_WW4B2_16", + "VFRAME_WW4B2" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW4C0_6", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4END2_6", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW2A3_6", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4BEG0_6", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_6", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_6", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A3_6", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4A1_6", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4B0_6", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SW4A3_6", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_NE4BEG2_6", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE4B0_6", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE4C1_6", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A1_6", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END1_6", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_6", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_6", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_6", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C1_6", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW4A1_6", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_ER1BEG0_6", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_6", + "VBRK_LH1" + ], + [ + "CMT_TOP_EE4BEG2_6", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG2_6", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SE2A0_6", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WL1END2_6", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A1_6", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WR1END3_6", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NE2A2_6", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_LH4_6", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END1_6", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH8_6", + "VBRK_LH8" + ], + [ + "CMT_TOP_SE4BEG2_6", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4END2_6", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH6_6", + "VBRK_LH6" + ], + [ + "CMT_TOP_LH3_6", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C2_6", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NE2A3_6", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE4C3_6", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4A0_6", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C3_6", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_ER1BEG3_6", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_6", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WR1END2_6", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END0_6", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4C0_6", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SE4C0_6", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SE2A3_6", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_LH2_6", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW2END1_6", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW2END3_6", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE2A0_6", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NE4C0_6", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WW4C3_6", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END1_6", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4BEG3_6", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A1_6", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4B3_6", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4B1_6", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A1_6", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WL1END3_6", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH7_6", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW2A0_6", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A0_6", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NW2A1_6", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2BEG0_6", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_6", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE2BEG1_6", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4END3_6", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NW4END3_6", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4BEG1_6", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_6", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_SW4END2_6", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NW4A3_6", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4BEG0_6", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SW4A2_6", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4C1_6", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2A0_6", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4END0_6", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_ER1BEG2_6", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2A3_6", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW2A0_6", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_LH11_6", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH9_6", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2BEG3_6", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WW4A3_6", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4A0_6", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE2A0_6", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NW2A2_6", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_6", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C3_6", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4A1_6", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WR1END0_6", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4C2_6", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE4C1_6", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG3_6", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW4B3_6", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END2_6", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A2_6", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4B2_6", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW4A0_6", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW2A1_6", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH5_6", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4B1_6", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_NE4BEG1_6", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH10_6", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_6", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4A2_6", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG1_6", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE2A1_6", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C2_6", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END0_6", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SE4BEG0_6", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_6", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE4A2_6", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4END0_6", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4BEG3_6", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A3_6", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_6", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_6", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A2_6", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NW2A3_6", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_6", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE4C2_6", + "VBRK_SE4C2" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLK_HROW_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_SW4A1_0", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_LH4_0", + "VBRK_LH4" + ], + [ + "CLK_HROW_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_LH11_0", + "VBRK_LH11" + ], + [ + "CLK_HROW_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_LH6_0", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_LH1_0", + "VBRK_LH1" + ], + [ + "CLK_HROW_LH10_0", + "VBRK_LH10" + ], + [ + "CLK_HROW_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_LH5_0", + "VBRK_LH5" + ], + [ + "CLK_HROW_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_LH8_0", + "VBRK_LH8" + ], + [ + "CLK_HROW_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_LH2_0", + "VBRK_LH2" + ], + [ + "CLK_HROW_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_LH12_0", + "VBRK_LH12" + ], + [ + "CLK_HROW_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_LH3_0", + "VBRK_LH3" + ], + [ + "CLK_HROW_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_LH7_0", + "VBRK_LH7" + ], + [ + "CLK_HROW_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_LH9_0", + "VBRK_LH9" + ], + [ + "CLK_HROW_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_WW4C2_0", + "VBRK_WW4C2" + ] + ], + "tile_types": [ + "CLK_BUFG_BOT_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "NE6C3", + "T_TERM_UTURN_INT_SE6D0" + ], + [ + "LV15", + "T_TERM_INT_UTURN_LV_R2" + ], + [ + "SS6D3", + "T_TERM_UTURN_INT_SS6D3" + ], + [ + "SS6END2", + "T_TERM_UTURN_INT_SS6END2" + ], + [ + "SE6D3", + "T_TERM_UTURN_INT_SE6D3" + ], + [ + "LV12", + "T_TERM_INT_UTURN_LV_R5" + ], + [ + "SL1END0", + "T_TERM_UTURN_INT_SL1END0" + ], + [ + "SS2A0", + "T_TERM_UTURN_INT_SS2A0" + ], + [ + "WL1BEG3", + "T_TERM_UTURN_INT_WR1BEG_S0" + ], + [ + "NE2BEG2", + "T_TERM_UTURN_INT_SE2A1" + ], + [ + "SS6B0", + "T_TERM_UTURN_INT_SS6B0" + ], + [ + "LVB6", + "T_TERM_UTURN_INT_LVB5" + ], + [ + "NE6B1", + "T_TERM_UTURN_INT_SE6C2" + ], + [ + "SW6C3", + "T_TERM_UTURN_INT_SW6C3" + ], + [ + "SW6E2", + "T_TERM_UTURN_INT_SW6E2" + ], + [ + "SS6D2", + "T_TERM_UTURN_INT_SS6D2" + ], + [ + "LV8", + "T_TERM_INT_UTURN_LV_R9" + ], + [ + "LV17", + "T_TERM_INT_UTURN_LV_R17" + ], + [ + "SE2A1", + "T_TERM_UTURN_INT_SE2A1" + ], + [ + "LV10", + "T_TERM_INT_UTURN_LV_R7" + ], + [ + "SW2A2", + "T_TERM_UTURN_INT_SW2A2" + ], + [ + "NW6D3", + "T_TERM_UTURN_INT_SW6E0" + ], + [ + "SE2A2", + "T_TERM_UTURN_INT_SE2A2" + ], + [ + "NN6C2", + "T_TERM_UTURN_INT_SS6D1" + ], + [ + "SS2END1", + "T_TERM_UTURN_INT_SS2END1" + ], + [ + "NE6D2", + "T_TERM_UTURN_INT_SE6E1" + ], + [ + "LVB7", + "T_TERM_UTURN_INT_LVB4" + ], + [ + "SE2A3", + "T_TERM_UTURN_INT_SE2A3" + ], + [ + "SS6END1", + "T_TERM_UTURN_INT_SS6END1" + ], + [ + "SS6B3", + "T_TERM_UTURN_INT_SS6B3" + ], + [ + "NN2BEG1", + "T_TERM_UTURN_INT_SS2A2" + ], + [ + "LVB8", + "T_TERM_UTURN_INT_LVB3" + ], + [ + "LV11", + "T_TERM_INT_UTURN_LV_R6" + ], + [ + "SE6B1", + "T_TERM_UTURN_INT_SE6B1" + ], + [ + "NN6A1", + "T_TERM_UTURN_INT_SS6B2" + ], + [ + "SS6E0", + "T_TERM_UTURN_INT_SS6E0" + ], + [ + "BYP_BOUNCE7", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0" + ], + [ + "NW6C1", + "T_TERM_UTURN_INT_SW6D2" + ], + [ + "NN6B3", + "T_TERM_UTURN_INT_SS6C0" + ], + [ + "NW2BEG1", + "T_TERM_UTURN_INT_SW2A2" + ], + [ + "SS6END0", + "T_TERM_UTURN_INT_SS6END0" + ], + [ + "NW2BEG2", + "T_TERM_UTURN_INT_SW2A1" + ], + [ + "NE6B0", + "T_TERM_UTURN_INT_SE6C3" + ], + [ + "SW6B1", + "T_TERM_UTURN_INT_SW6B1" + ], + [ + "NW6A2", + "T_TERM_UTURN_INT_SW6B1" + ], + [ + "NN2A0", + "T_TERM_UTURN_INT_SS2END3" + ], + [ + "WL1END3", + "T_TERM_UTURN_INT_WR1END_S1_0" + ], + [ + "SW6B3", + "T_TERM_UTURN_INT_SW6B3" + ], + [ + "NN6E0", + "T_TERM_UTURN_INT_SS6END3" + ], + [ + "NE6A0", + "T_TERM_UTURN_INT_SE6B3" + ], + [ + "NW6A3", + "T_TERM_UTURN_INT_SW6B0" + ], + [ + "NW6A0", + "T_TERM_UTURN_INT_SW6B3" + ], + [ + "SR1END1", + "T_TERM_UTURN_INT_SR1END1" + ], + [ + "NE6C1", + "T_TERM_UTURN_INT_SE6D2" + ], + [ + "SS6E3", + "T_TERM_UTURN_INT_SS6E3" + ], + [ + "NE2BEG3", + "T_TERM_UTURN_INT_SE2A0" + ], + [ + "SR1END3", + "T_TERM_UTURN_INT_SR1END3" + ], + [ + "SW6D0", + "T_TERM_UTURN_INT_SW6D0" + ], + [ + "LV1", + "T_TERM_INT_UTURN_LV_R16" + ], + [ + "NR1BEG1", + "T_TERM_UTURN_INT_SL1END2" + ], + [ + "SS6D1", + "T_TERM_UTURN_INT_SS6D1" + ], + [ + "SE6B0", + "T_TERM_UTURN_INT_SE6B0" + ], + [ + "SW6C1", + "T_TERM_UTURN_INT_SW6C1" + ], + [ + "SW2A0", + "T_TERM_UTURN_INT_SW2A0" + ], + [ + "SE6D1", + "T_TERM_UTURN_INT_SE6D1" + ], + [ + "FAN_BOUNCE_S3_6", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6" + ], + [ + "NW6C3", + "T_TERM_UTURN_INT_SW6D0" + ], + [ + "EL1END_S3_0", + "T_TERM_UTURN_INT_ER1END3" + ], + [ + "LV4", + "T_TERM_INT_UTURN_LV_R4" + ], + [ + "SS6A2", + "T_TERM_UTURN_INT_SS6A2" + ], + [ + "NN6D2", + "T_TERM_UTURN_INT_SS6E1" + ], + [ + "SW6E1", + "T_TERM_UTURN_INT_SW6E1" + ], + [ + "NW2BEG0", + "T_TERM_UTURN_INT_SW2A3" + ], + [ + "SR1END2", + "T_TERM_UTURN_INT_SR1END2" + ], + [ + "SE6C3", + "T_TERM_UTURN_INT_SE6C3" + ], + [ + "NN6BEG1", + "T_TERM_UTURN_INT_SS6A2" + ], + [ + "NE6C0", + "T_TERM_UTURN_INT_SE6D3" + ], + [ + "LV7", + "T_TERM_INT_UTURN_LV_R7" + ], + [ + "SE6D0", + "T_TERM_UTURN_INT_SE6D0" + ], + [ + "SE6E0", + "T_TERM_UTURN_INT_SE6E0" + ], + [ + "SW6E0", + "T_TERM_UTURN_INT_SW6E0" + ], + [ + "LV13", + "T_TERM_INT_UTURN_LV_R4" + ], + [ + "LVB5", + "T_TERM_UTURN_INT_LVB5" + ], + [ + "SL1END3", + "T_TERM_UTURN_INT_SL1END3" + ], + [ + "NN2A2", + "T_TERM_UTURN_INT_SS2END1" + ], + [ + "NE2BEG1", + "T_TERM_UTURN_INT_SE2A2" + ], + [ + "EL1BEG3", + "T_TERM_UTURN_INT_ER1BEG_S0" + ], + [ + "SS2A1", + "T_TERM_UTURN_INT_SS2A1" + ], + [ + "BYP_BOUNCE3", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2" + ], + [ + "NN6B2", + "T_TERM_UTURN_INT_SS6C1" + ], + [ + "NE6A2", + "T_TERM_UTURN_INT_SE6B1" + ], + [ + "NE6D1", + "T_TERM_UTURN_INT_SE6E2" + ], + [ + "NN6D3", + "T_TERM_UTURN_INT_SS6E0" + ], + [ + "WR1BEG_S0", + "T_TERM_UTURN_INT_WR1BEG_S0" + ], + [ + "SE6C1", + "T_TERM_UTURN_INT_SE6C1" + ], + [ + "WR1END_S1_0", + "T_TERM_UTURN_INT_WR1END_S1_0" + ], + [ + "NN2BEG2", + "T_TERM_UTURN_INT_SS2A1" + ], + [ + "NN6C3", + "T_TERM_UTURN_INT_SS6D0" + ], + [ + "NW6B2", + "T_TERM_UTURN_INT_SW6C1" + ], + [ + "LV16", + "T_TERM_INT_UTURN_LV_R16" + ], + [ + "SE2A0", + "T_TERM_UTURN_INT_SE2A0" + ], + [ + "SE6E1", + "T_TERM_UTURN_INT_SE6E1" + ], + [ + "NN6E3", + "T_TERM_UTURN_INT_SS6END0" + ], + [ + "SS6A3", + "T_TERM_UTURN_INT_SS6A3" + ], + [ + "NW6C0", + "T_TERM_UTURN_INT_SW6D3" + ], + [ + "NW6D2", + "T_TERM_UTURN_INT_SW6E1" + ], + [ + "SE6B3", + "T_TERM_UTURN_INT_SE6B3" + ], + [ + "SW2A3", + "T_TERM_UTURN_INT_SW2A3" + ], + [ + "NL1BEG0", + "T_TERM_UTURN_INT_SR1END3" + ], + [ + "SL1END2", + "T_TERM_UTURN_INT_SL1END2" + ], + [ + "SS6C2", + "T_TERM_UTURN_INT_SS6C2" + ], + [ + "SE6D2", + "T_TERM_UTURN_INT_SE6D2" + ], + [ + "SE6B2", + "T_TERM_UTURN_INT_SE6B2" + ], + [ + "NW6D1", + "T_TERM_UTURN_INT_SW6E2" + ], + [ + "NN6E1", + "T_TERM_UTURN_INT_SS6END2" + ], + [ + "SE6C0", + "T_TERM_UTURN_INT_SE6C0" + ], + [ + "LV6", + "T_TERM_INT_UTURN_LV_R6" + ], + [ + "SS6C3", + "T_TERM_UTURN_INT_SS6C3" + ], + [ + "NW6C2", + "T_TERM_UTURN_INT_SW6D1" + ], + [ + "NN6B0", + "T_TERM_UTURN_INT_SS6C3" + ], + [ + "FAN_BOUNCE_S3_0", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0" + ], + [ + "SW6D2", + "T_TERM_UTURN_INT_SW6D2" + ], + [ + "NN6C0", + "T_TERM_UTURN_INT_SS6D3" + ], + [ + "LV3", + "T_TERM_INT_UTURN_LV_R3" + ], + [ + "NN2A3", + "T_TERM_UTURN_INT_SS2END0" + ], + [ + "SE6C2", + "T_TERM_UTURN_INT_SE6C2" + ], + [ + "NN6D1", + "T_TERM_UTURN_INT_SS6E2" + ], + [ + "LV5", + "T_TERM_INT_UTURN_LV_R5" + ], + [ + "NN6BEG2", + "T_TERM_UTURN_INT_SS6A1" + ], + [ + "SS2A2", + "T_TERM_UTURN_INT_SS2A2" + ], + [ + "NW6B3", + "T_TERM_UTURN_INT_SW6C0" + ], + [ + "NN6D0", + "T_TERM_UTURN_INT_SS6E3" + ], + [ + "SS6D0", + "T_TERM_UTURN_INT_SS6D0" + ], + [ + "FAN_BOUNCE_S3_4", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4" + ], + [ + "SE6E2", + "T_TERM_UTURN_INT_SE6E2" + ], + [ + "LVB1", + "T_TERM_UTURN_INT_LVB1" + ], + [ + "SS6END3", + "T_TERM_UTURN_INT_SS6END3" + ], + [ + "LV2", + "T_TERM_INT_UTURN_LV_R2" + ], + [ + "BYP_BOUNCE2", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6" + ], + [ + "NW6B0", + "T_TERM_UTURN_INT_SW6C3" + ], + [ + "NN6A0", + "T_TERM_UTURN_INT_SS6B3" + ], + [ + "SS2END0", + "T_TERM_UTURN_INT_SS2END0" + ], + [ + "NR1BEG0", + "T_TERM_UTURN_INT_SL1END3" + ], + [ + "ER1BEG_S0", + "T_TERM_UTURN_INT_ER1BEG_S0" + ], + [ + "SS6A1", + "T_TERM_UTURN_INT_SS6A1" + ], + [ + "SS6B2", + "T_TERM_UTURN_INT_SS6B2" + ], + [ + "SW6B2", + "T_TERM_UTURN_INT_SW6B2" + ], + [ + "NW6A1", + "T_TERM_UTURN_INT_SW6B2" + ], + [ + "SW6C2", + "T_TERM_UTURN_INT_SW6C2" + ], + [ + "SW6E3", + "T_TERM_UTURN_INT_SW6E3" + ], + [ + "LVB4", + "T_TERM_UTURN_INT_LVB4" + ], + [ + "SS6C1", + "T_TERM_UTURN_INT_SS6C1" + ], + [ + "NN6B1", + "T_TERM_UTURN_INT_SS6C2" + ], + [ + "NW2BEG3", + "T_TERM_UTURN_INT_SW2A0" + ], + [ + "LVB3", + "T_TERM_UTURN_INT_LVB3" + ], + [ + "NW6D0", + "T_TERM_UTURN_INT_SW6E3" + ], + [ + "LVB10", + "T_TERM_UTURN_INT_LVB1" + ], + [ + "NE6B3", + "T_TERM_UTURN_INT_SE6C0" + ], + [ + "NN2A1", + "T_TERM_UTURN_INT_SS2END2" + ], + [ + "NN6A2", + "T_TERM_UTURN_INT_SS6B1" + ], + [ + "SW6C0", + "T_TERM_UTURN_INT_SW6C0" + ], + [ + "NN2BEG0", + "T_TERM_UTURN_INT_SS2A3" + ], + [ + "NN6A3", + "T_TERM_UTURN_INT_SS6B0" + ], + [ + "NE6D3", + "T_TERM_UTURN_INT_SE6E0" + ], + [ + "SS6E1", + "T_TERM_UTURN_INT_SS6E1" + ], + [ + "LV9", + "T_TERM_INT_UTURN_LV_R9" + ], + [ + "NR1BEG3", + "T_TERM_UTURN_INT_SL1END0" + ], + [ + "NW6B1", + "T_TERM_UTURN_INT_SW6C2" + ], + [ + "SS6C0", + "T_TERM_UTURN_INT_SS6C0" + ], + [ + "NN2BEG3", + "T_TERM_UTURN_INT_SS2A0" + ], + [ + "ER1END3", + "T_TERM_UTURN_INT_ER1END3" + ], + [ + "LV0", + "T_TERM_INT_UTURN_LV_R17" + ], + [ + "SW6D1", + "T_TERM_UTURN_INT_SW6D1" + ], + [ + "NN6BEG3", + "T_TERM_UTURN_INT_SS6A0" + ], + [ + "LVB0", + "T_TERM_UTURN_INT_LVB0" + ], + [ + "SS2END2", + "T_TERM_UTURN_INT_SS2END2" + ], + [ + "NE6A3", + "T_TERM_UTURN_INT_SE6B0" + ], + [ + "FAN_BOUNCE_S3_2", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2" + ], + [ + "NE6B2", + "T_TERM_UTURN_INT_SE6C1" + ], + [ + "NN6BEG0", + "T_TERM_UTURN_INT_SS6A3" + ], + [ + "SS2A3", + "T_TERM_UTURN_INT_SS2A3" + ], + [ + "NL1BEG2", + "T_TERM_UTURN_INT_SR1END1" + ], + [ + "SW6B0", + "T_TERM_UTURN_INT_SW6B0" + ], + [ + "SS2END3", + "T_TERM_UTURN_INT_SS2END3" + ], + [ + "LVB2", + "T_TERM_UTURN_INT_LVB2" + ], + [ + "SS6A0", + "T_TERM_UTURN_INT_SS6A0" + ], + [ + "LVB9", + "T_TERM_UTURN_INT_LVB2" + ], + [ + "SS6B1", + "T_TERM_UTURN_INT_SS6B1" + ], + [ + "NE6A1", + "T_TERM_UTURN_INT_SE6B2" + ], + [ + "SW6D3", + "T_TERM_UTURN_INT_SW6D3" + ], + [ + "SW2A1", + "T_TERM_UTURN_INT_SW2A1" + ], + [ + "LVB11", + "T_TERM_UTURN_INT_LVB0" + ], + [ + "SE6E3", + "T_TERM_UTURN_INT_SE6E3" + ], + [ + "SS6E2", + "T_TERM_UTURN_INT_SS6E2" + ], + [ + "LV14", + "T_TERM_INT_UTURN_LV_R3" + ], + [ + "NE2BEG0", + "T_TERM_UTURN_INT_SE2A3" + ], + [ + "SL1END1", + "T_TERM_UTURN_INT_SL1END1" + ], + [ + "BYP_BOUNCE6", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4" + ], + [ + "NN6E2", + "T_TERM_UTURN_INT_SS6END1" + ], + [ + "NL1BEG1", + "T_TERM_UTURN_INT_SR1END2" + ], + [ + "NE6D0", + "T_TERM_UTURN_INT_SE6E3" + ], + [ + "NE6C2", + "T_TERM_UTURN_INT_SE6D1" + ], + [ + "NN6C1", + "T_TERM_UTURN_INT_SS6D2" + ], + [ + "NR1BEG2", + "T_TERM_UTURN_INT_SL1END1" + ] + ], + "tile_types": [ + "INT_R", + "T_TERM_INT" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_FIFO_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CCIO2", + "HCLK_FIFO_CCIO2" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_FIFO_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_FIFO_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_FIFO_PERFCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_FIFO_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_FIFO_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_FIFO_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_FIFO_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_FIFO_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_FIFO_PERFCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_FIFO_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_FIFO_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_FIFO_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_FIFO_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_FIFO_PERFCLK0" + ], + [ + "HCLK_CMT_CCIO0", + "HCLK_FIFO_CCIO0" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_FIFO_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_FIFO_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_FIFO_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CCIO3", + "HCLK_FIFO_CCIO3" + ], + [ + "HCLK_CMT_CCIO1", + "HCLK_FIFO_CCIO1" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_FIFO_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_FIFO_CK_BUFRCLK2" + ] + ], + "tile_types": [ + "HCLK_CMT", + "HCLK_FIFO_L" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "CLK_HROW_SW2A3_1", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_EE2BEG1_1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_IMUX47_1", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_IMUX32_1", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_BYP3_1", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_WL1END0_1", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_WW4C0_1", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_NE2A1_1", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_WW4A2_1", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_NE4C0_1", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_FAN4_1", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_IMUX26_1", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_NE4BEG1_1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_IMUX9_1", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_IMUX35_1", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_IMUX25_1", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_EE2BEG0_1", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_EE2A1_1", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_IMUX33_1", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_EL1BEG1_1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_EE4A1_1", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_SW4A2_1", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_IMUX15_1", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_IMUX41_1", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_NW4A2_1", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_EE2A2_1", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_IMUX11_1", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_IMUX38_1", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_EE2A0_1", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_FAN2_1", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_SE4C3_1", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_EE4BEG3_1", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_WW4C3_1", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_SW4END0_1", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_CLK0_1", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_IMUX30_1", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_CTRL0_1", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_EE4BEG1_1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_IMUX42_1", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_WW2END2_1", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_WR1END0_1", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_WW2END0_1", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_EE2BEG3_1", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_BYP5_1", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_NW2A0_1", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_IMUX17_1", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_LH4_1", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_NE2A3_1", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_FAN7_1", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_EE4BEG2_1", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_IMUX14_1", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_IMUX39_1", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_WW2END3_1", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_NE2A2_1", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_SW4END1_1", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_SW2A1_1", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_EE4B0_1", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_WW2A3_1", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_NW4A3_1", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_IMUX31_1", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_IMUX34_1", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_WR1END3_1", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_IMUX20_1", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_NE4BEG2_1", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_CTRL1_1", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_EE2A3_1", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_IMUX46_1", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_IMUX13_1", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_WW4END2_1", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_EL1BEG3_1", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_IMUX28_1", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_IMUX8_1", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_LH8_1", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_NW4END0_1", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_BYP1_1", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_WW4A1_1", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_LH2_1", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_NW4END2_1", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_EE2BEG2_1", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_IMUX43_1", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_NE4C2_1", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_SE2A1_1", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_EE4A0_1", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_CLK1_1", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_LH10_1", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_IMUX12_1", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_NW2A1_1", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_LH7_1", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_LH12_1", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_FAN0_1", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_NE4C3_1", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_LH5_1", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_IMUX44_1", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_SW2A0_1", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE4C0_1", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_IMUX29_1", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_IMUX7_1", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_WW4B0_1", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_WL1END2_1", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_FAN5_1", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_NW4A0_1", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_SW4A3_1", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_IMUX6_1", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_NE4BEG3_1", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_WW2END1_1", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_SW4A1_1", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_LH3_1", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_IMUX2_1", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_WW2A0_1", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4B1_1", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_ER1BEG1_1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_WR1END1_1", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_NE4BEG0_1", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_WW4B1_1", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_SW4END2_1", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_NE4C1_1", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_LH9_1", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_IMUX19_1", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_LH11_1", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_SW4A0_1", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_SE2A3_1", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_BYP6_1", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_SW2A2_1", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_SE4BEG0_1", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_IMUX22_1", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_NW2A2_1", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_WW4C1_1", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_IMUX23_1", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_ER1BEG3_1", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_IMUX37_1", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_IMUX4_1", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_SE4BEG3_1", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_NW4END1_1", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_IMUX45_1", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_BYP0_1", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_IMUX27_1", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_WW4C2_1", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_LH6_1", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_EL1BEG0_1", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_EE4B2_1", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_FAN3_1", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_LH1_1", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_NW4END3_1", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_WL1END3_1", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_WW4B3_1", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_BYP7_1", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_IMUX1_1", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_SE4C0_1", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_EE4C3_1", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_SE2A2_1", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_NW4A1_1", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_WW4A0_1", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_FAN6_1", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_EE4C1_1", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_EE4B3_1", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_EE4A3_1", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_IMUX10_1", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_IMUX36_1", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_IMUX21_1", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_NE2A0_1", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_WW4B2_1", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_ER1BEG2_1", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_WW4END1_1", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_WW4END0_1", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_IMUX16_1", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_SW4END3_1", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_EL1BEG2_1", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_FAN1_1", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_IMUX24_1", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_BYP2_1", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_WL1END1_1", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_EE4BEG0_1", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_IMUX3_1", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_SE4C2_1", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_WW4A3_1", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_WR1END2_1", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_SE4BEG2_1", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_SE4C1_1", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_IMUX40_1", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_NW2A3_1", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_WW4END3_1", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_IMUX0_1", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_EE4C2_1", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_IMUX5_1", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_BYP4_1", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_ER1BEG0_1", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_EE4A2_1", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_IMUX18_1", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_SE2A0_1", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_SE4BEG1_1", + "INT_INTERFACE_SE4BEG1" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CLK_BUFG_REBUF_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CLK_BUFG_REBUF_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CLK_BUFG_REBUF_LH9_1", + "VBRK_LH9" + ], + [ + "CLK_BUFG_REBUF_LH6_1", + "VBRK_LH6" + ], + [ + "CLK_BUFG_REBUF_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CLK_BUFG_REBUF_LH4_1", + "VBRK_LH4" + ], + [ + "CLK_BUFG_REBUF_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CLK_BUFG_REBUF_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CLK_BUFG_REBUF_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CLK_BUFG_REBUF_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CLK_BUFG_REBUF_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CLK_BUFG_REBUF_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CLK_BUFG_REBUF_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CLK_BUFG_REBUF_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CLK_BUFG_REBUF_LH7_1", + "VBRK_LH7" + ], + [ + "CLK_BUFG_REBUF_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CLK_BUFG_REBUF_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CLK_BUFG_REBUF_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CLK_BUFG_REBUF_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CLK_BUFG_REBUF_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CLK_BUFG_REBUF_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CLK_BUFG_REBUF_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CLK_BUFG_REBUF_LH5_1", + "VBRK_LH5" + ], + [ + "CLK_BUFG_REBUF_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CLK_BUFG_REBUF_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CLK_BUFG_REBUF_MONITOR_P_1", + "VBRK_MONITOR_P" + ], + [ + "CLK_BUFG_REBUF_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CLK_BUFG_REBUF_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CLK_BUFG_REBUF_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CLK_BUFG_REBUF_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CLK_BUFG_REBUF_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CLK_BUFG_REBUF_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CLK_BUFG_REBUF_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CLK_BUFG_REBUF_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CLK_BUFG_REBUF_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CLK_BUFG_REBUF_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CLK_BUFG_REBUF_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CLK_BUFG_REBUF_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CLK_BUFG_REBUF_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CLK_BUFG_REBUF_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CLK_BUFG_REBUF_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CLK_BUFG_REBUF_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CLK_BUFG_REBUF_LH3_1", + "VBRK_LH3" + ], + [ + "CLK_BUFG_REBUF_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CLK_BUFG_REBUF_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CLK_BUFG_REBUF_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CLK_BUFG_REBUF_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CLK_BUFG_REBUF_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CLK_BUFG_REBUF_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CLK_BUFG_REBUF_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CLK_BUFG_REBUF_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CLK_BUFG_REBUF_LH11_1", + "VBRK_LH11" + ], + [ + "CLK_BUFG_REBUF_MONITOR_N_1", + "VBRK_MONITOR_N" + ], + [ + "CLK_BUFG_REBUF_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CLK_BUFG_REBUF_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CLK_BUFG_REBUF_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CLK_BUFG_REBUF_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CLK_BUFG_REBUF_LH8_1", + "VBRK_LH8" + ], + [ + "CLK_BUFG_REBUF_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CLK_BUFG_REBUF_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CLK_BUFG_REBUF_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CLK_BUFG_REBUF_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CLK_BUFG_REBUF_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CLK_BUFG_REBUF_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CLK_BUFG_REBUF_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CLK_BUFG_REBUF_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CLK_BUFG_REBUF_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CLK_BUFG_REBUF_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CLK_BUFG_REBUF_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CLK_BUFG_REBUF_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CLK_BUFG_REBUF_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CLK_BUFG_REBUF_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CLK_BUFG_REBUF_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CLK_BUFG_REBUF_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CLK_BUFG_REBUF_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CLK_BUFG_REBUF_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CLK_BUFG_REBUF_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CLK_BUFG_REBUF_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CLK_BUFG_REBUF_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CLK_BUFG_REBUF_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CLK_BUFG_REBUF_LH10_1", + "VBRK_LH10" + ], + [ + "CLK_BUFG_REBUF_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CLK_BUFG_REBUF_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CLK_BUFG_REBUF_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CLK_BUFG_REBUF_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CLK_BUFG_REBUF_LH2_1", + "VBRK_LH2" + ], + [ + "CLK_BUFG_REBUF_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CLK_BUFG_REBUF_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CLK_BUFG_REBUF_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CLK_BUFG_REBUF_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CLK_BUFG_REBUF_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CLK_BUFG_REBUF_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CLK_BUFG_REBUF_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "CLK_BUFG_REBUF_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CLK_BUFG_REBUF_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CLK_BUFG_REBUF_LH12_1", + "VBRK_LH12" + ], + [ + "CLK_BUFG_REBUF_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CLK_BUFG_REBUF_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CLK_BUFG_REBUF_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CLK_BUFG_REBUF_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CLK_BUFG_REBUF_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CLK_BUFG_REBUF_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CLK_BUFG_REBUF_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CLK_BUFG_REBUF_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CLK_BUFG_REBUF_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CLK_BUFG_REBUF_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CLK_BUFG_REBUF_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CLK_BUFG_REBUF_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CLK_BUFG_REBUF_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CLK_BUFG_REBUF_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CLK_BUFG_REBUF_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CLK_BUFG_REBUF_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CLK_BUFG_REBUF_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CLK_BUFG_REBUF_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CLK_BUFG_REBUF_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CLK_BUFG_REBUF_LH1_1", + "VBRK_LH1" + ], + [ + "CLK_BUFG_REBUF_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CLK_BUFG_REBUF_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "CLK_BUFG_REBUF_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CLK_BUFG_REBUF_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CLK_BUFG_REBUF_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CLK_BUFG_REBUF_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CLK_BUFG_REBUF_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CLK_BUFG_REBUF_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CLK_BUFG_REBUF_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CLK_BUFG_REBUF_EE2A1_1", + "VBRK_EE2A1" + ] + ], + "tile_types": [ + "CLK_BUFG_REBUF", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CMT_TOP_EL1BEG1_8", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG1_8", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NW4A0_8", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4B0_8", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_8", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW2A0_8", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW2A0_8", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4BEG2_8", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_NE4C0_8", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_ER1BEG2_8", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_8", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_LH12_8", + "VBRK_LH12" + ], + [ + "CMT_TOP_EL1BEG2_8", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_LH1_8", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH10_8", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW4B1_8", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG2_8", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW4A3_8", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4C3_8", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_NW2A0_8", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NW4END0_8", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE2A2_8", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4C1_8", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW4C2_8", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW4A1_8", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NW2A1_8", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SE4BEG0_8", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_8", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_LH3_8", + "VBRK_LH3" + ], + [ + "CMT_TOP_WR1END2_8", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A0_8", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4A2_8", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END1_8", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A0_8", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A1_8", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EL1BEG0_8", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_EE4A3_8", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C3_8", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_LH4_8", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE4A0_8", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END1_8", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2A0_8", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH2_8", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4C1_8", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NE2A2_8", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2A3_8", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_NW4A3_8", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4END2_8", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE2A1_8", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END2_8", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2END0_8", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2BEG0_8", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4C0_8", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG0_8", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_WR1END0_8", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_SE4C2_8", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4END1_8", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NE2A1_8", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4B3_8", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_8", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C2_8", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4B1_8", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW2A3_8", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SE4C1_8", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WR1END3_8", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW2A2_8", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C0_8", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4C1_8", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH11_8", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4B2_8", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW2A3_8", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NW4END2_8", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A0_8", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WR1END1_8", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH5_8", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END3_8", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH6_8", + "VBRK_LH6" + ], + [ + "CMT_TOP_NE4BEG3_8", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_LH8_8", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A1_8", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE2BEG2_8", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4C3_8", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NW2A2_8", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END3_8", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE2A3_8", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_ER1BEG1_8", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_8", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_NE4BEG1_8", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_WW4A2_8", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG0_8", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NE4C2_8", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SE4BEG3_8", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C0_8", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_8", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2BEG3_8", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH9_8", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE4B2_8", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_WL1END0_8", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_WW2END3_8", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EL1BEG3_8", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG3_8", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4BEG3_8", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WL1END1_8", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2A1_8", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SE4BEG2_8", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW2A3_8", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SE4C3_8", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE2A2_8", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_8", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4A1_8", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW4A2_8", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SW2A2_8", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_NW4END3_8", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SW4END1_8", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END3_8", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4BEG1_8", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4END2_8", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH7_8", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4BEG0_8", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2BEG1_8", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_8", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A3_8", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WL1END2_8", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A0_8", + "VBRK_WW4A0" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ] + ], + "tile_types": [ + "HCLK_DSP_R", + "HCLK_VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 4 + ], + "wire_pairs": [ + [ + "CMT_TOP_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_LH2_1", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH11_1", + "VBRK_LH11" + ], + [ + "CMT_TOP_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH10_1", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_LH8_1", + "VBRK_LH8" + ], + [ + "CMT_TOP_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH3_1", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH4_1", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH5_1", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_1", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_LH6_1", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH1_1", + "VBRK_LH1" + ], + [ + "CMT_TOP_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_LH7_1", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH9_1", + "VBRK_LH9" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "BRAM_LH4_2", + "VBRK_LH4" + ], + [ + "BRAM_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "BRAM_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "BRAM_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "BRAM_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "BRAM_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "BRAM_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "BRAM_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "BRAM_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "BRAM_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "BRAM_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "BRAM_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "BRAM_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "BRAM_EE4B3_2", + "VBRK_EE4B3" + ], + [ + "BRAM_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "BRAM_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "BRAM_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "BRAM_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "BRAM_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "BRAM_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "BRAM_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "BRAM_LH11_2", + "VBRK_LH11" + ], + [ + "BRAM_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "BRAM_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "BRAM_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "BRAM_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "BRAM_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "BRAM_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "BRAM_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "BRAM_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "BRAM_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "BRAM_LH7_2", + "VBRK_LH7" + ], + [ + "BRAM_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "BRAM_LH5_2", + "VBRK_LH5" + ], + [ + "BRAM_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "BRAM_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "BRAM_NW2A2_2", + "VBRK_NW2A2" + ], + [ + "BRAM_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "BRAM_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "BRAM_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "BRAM_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "BRAM_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "BRAM_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "BRAM_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "BRAM_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "BRAM_MONITOR_N_2", + "VBRK_MONITOR_N" + ], + [ + "BRAM_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "BRAM_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "BRAM_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "BRAM_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "BRAM_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "BRAM_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "BRAM_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "BRAM_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "BRAM_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "BRAM_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "BRAM_LH12_2", + "VBRK_LH12" + ], + [ + "BRAM_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "BRAM_LH10_2", + "VBRK_LH10" + ], + [ + "BRAM_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "BRAM_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "BRAM_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "BRAM_MONITOR_P_2", + "VBRK_MONITOR_P" + ], + [ + "BRAM_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "BRAM_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "BRAM_LH8_2", + "VBRK_LH8" + ], + [ + "BRAM_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "BRAM_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "BRAM_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "BRAM_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "BRAM_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "BRAM_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "BRAM_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "BRAM_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "BRAM_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "BRAM_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "BRAM_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "BRAM_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "BRAM_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "BRAM_LH3_2", + "VBRK_LH3" + ], + [ + "BRAM_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "BRAM_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "BRAM_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "BRAM_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "BRAM_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "BRAM_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "BRAM_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "BRAM_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "BRAM_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "BRAM_LH6_2", + "VBRK_LH6" + ], + [ + "BRAM_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "BRAM_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "BRAM_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "BRAM_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "BRAM_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "BRAM_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "BRAM_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "BRAM_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "BRAM_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "BRAM_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "BRAM_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "BRAM_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "BRAM_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "BRAM_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "BRAM_LH2_2", + "VBRK_LH2" + ], + [ + "BRAM_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "BRAM_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "BRAM_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "BRAM_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "BRAM_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "BRAM_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "BRAM_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "BRAM_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "BRAM_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "BRAM_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "BRAM_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "BRAM_LH9_2", + "VBRK_LH9" + ], + [ + "BRAM_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "BRAM_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "BRAM_LH1_2", + "VBRK_LH1" + ], + [ + "BRAM_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "BRAM_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "BRAM_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "BRAM_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "BRAM_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "BRAM_SW2A1_2", + "VBRK_SW2A1" + ] + ], + "tile_types": [ + "BRAM_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 8 + ], + "wire_pairs": [ + [ + "BRKH_CMT_PHASEREF1", + "CMT_PLL_PHASERREF_ABOVE1" + ], + [ + "BRKH_CMT_PHASEREF_BELOW1", + "CMT_PLL_PHASERREF1" + ], + [ + "BRKH_CMT_PHYCTRL_SYNC_BB", + "CMT_PLL_PHYCTRL_SYNC_BB_UP" + ], + [ + "BRKH_CMT_FREQ_REF_NS0", + "PLL_CLK_FREQ_BB_BUFOUT_NS0" + ], + [ + "BRKH_CMT_FREQ_REF_NS3", + "PLL_CLK_FREQ_BB_BUFOUT_NS3" + ], + [ + "BRKH_CMT_PHASEREF0", + "CMT_PLL_PHASERREF_ABOVE0" + ], + [ + "BRKH_CMT_FREQ_REF_NS2", + "PLL_CLK_FREQ_BB_BUFOUT_NS2" + ], + [ + "BRKH_CMT_PHASEREF_BELOW0", + "CMT_PLL_PHASERREF0" + ], + [ + "BRKH_CMT_FREQ_REF_NS1", + "PLL_CLK_FREQ_BB_BUFOUT_NS1" + ] + ], + "tile_types": [ + "BRKH_CMT", + "CMT_TOP_L_UPPER_T" + ] + }, + { + "grid_deltas": [ + 1, + 3 + ], + "wire_pairs": [ + [ + "CFG_CENTER_LH4_7", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_EE2BEG2_7", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX46_7", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW4C2_7", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WW4A1_7", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_LH11_7", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_CTRL0_7", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX16_7", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX7_7", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_CLK1_7", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_NW2A1_7", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_BYP3_7", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_BYP6_7", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_SE2A3_7", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_WW2END3_7", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_IMUX37_7", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SW4A1_7", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_NW4A0_7", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NW4A1_7", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_LH12_7", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX2_7", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_IMUX40_7", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_NW4A2_7", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_WL1END2_7", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_EE4C0_7", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_IMUX8_7", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_EE2A2_7", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_CTRL1_7", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_ER1BEG0_7", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_SW2A0_7", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_EE4BEG2_7", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX34_7", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_NE4C2_7", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_NW4END3_7", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_WR1END0_7", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EE4C1_7", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_LH10_7", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW4END1_7", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX27_7", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_WW2A2_7", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_WW4B1_7", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_SE2A1_7", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_IMUX39_7", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_WR1END3_7", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX21_7", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_EE4A0_7", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_SW2A1_7", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_EE4BEG0_7", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_EE2BEG1_7", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX41_7", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_LH1_7", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_SW2A2_7", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_EE4B0_7", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_EE2BEG0_7", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_NE4BEG2_7", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_FAN5_7", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SE4BEG1_7", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_WW4B2_7", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_IMUX44_7", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WW4END0_7", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX22_7", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_SW4A0_7", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_NW4END1_7", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SW4A3_7", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_WW4C3_7", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_SE4BEG0_7", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_SW2A3_7", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_IMUX45_7", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_EE4A1_7", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX1_7", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_NE2A0_7", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_FAN4_7", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_LH5_7", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_SE4BEG3_7", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX47_7", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_FAN1_7", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_NW4A3_7", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SW4END2_7", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_EL1BEG0_7", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_BYP4_7", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WW2END2_7", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_WW4A0_7", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_EE2A0_7", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WW2A1_7", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_EE4B2_7", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_SE2A0_7", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_LH3_7", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX38_7", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX25_7", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_EE4BEG1_7", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_IMUX30_7", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_EE4BEG3_7", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_NE4BEG1_7", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX42_7", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX4_7", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_WL1END1_7", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_IMUX32_7", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_NW4END2_7", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_NE4BEG0_7", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX3_7", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_WL1END0_7", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_SE2A2_7", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX28_7", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX10_7", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_BYP0_7", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_LH6_7", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX43_7", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX11_7", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_NE2A3_7", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_EL1BEG3_7", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW4C1_7", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_EE4A2_7", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX31_7", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_NW4END0_7", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_SW4END3_7", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX5_7", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_ER1BEG2_7", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_LH8_7", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_NE4C0_7", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_IMUX15_7", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_IMUX9_7", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_EL1BEG2_7", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX17_7", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_NW2A3_7", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_IMUX12_7", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_FAN6_7", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX23_7", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WL1END3_7", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_NW2A2_7", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW4B0_7", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_CLK0_7", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_WW2A0_7", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_EE4C3_7", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_WW2A3_7", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX18_7", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_EE4B1_7", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_SW4END0_7", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_NE4BEG3_7", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_EE2BEG3_7", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX36_7", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_FAN0_7", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX6_7", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_WW4C0_7", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX19_7", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_WW2END1_7", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_NE4C3_7", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_FAN3_7", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_SE4C3_7", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_NE4C1_7", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_ER1BEG1_7", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SE4C2_7", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WW4END2_7", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_WW2END0_7", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_LH7_7", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_BYP2_7", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_BYP7_7", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_SE4C1_7", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_EE4C2_7", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_EE4A3_7", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_SW4A2_7", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NW2A0_7", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_LH9_7", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_SW4END1_7", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_IMUX33_7", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_WW4A3_7", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_LH2_7", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX35_7", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_BYP5_7", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_EE4B3_7", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_IMUX0_7", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW4END3_7", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_EE2A1_7", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX13_7", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_SE4C0_7", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_WW4B3_7", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_WR1END2_7", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_ER1BEG3_7", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_BYP1_7", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_EE2A3_7", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EL1BEG1_7", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_IMUX14_7", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_FAN7_7", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX24_7", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_SE4BEG2_7", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_WW4A2_7", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_NE2A2_7", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WR1END1_7", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NE2A1_7", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX29_7", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX20_7", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_IMUX26_7", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_FAN2_7", + "VFRAME_FAN2" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "wire_pairs": [ + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IDELAYCTRL_RDY", + "IOI_IDELAYCTRL_RDY" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_RCLK_DIV_CLR3", + "IOI_RCLK_DIV_CLR3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "RIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK_IMUX3", + "IOI_IMUX_RC3" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN1", + "IOI_IDELAYCTRL_OUTN1" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_RCLK_IMUX2", + "IOI_IMUX_RC2" + ], + [ + "HCLK_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_RCLK_DIV_CLR2", + "IOI_RCLK_DIV_CLR2" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN65", + "IOI_IDELAYCTRL_OUTN65" + ], + [ + "HCLK_IOI_INT_DCI_EN", + "IOI_INT_DCI_EN" + ], + [ + "HCLK_IOI_I2IOCLK_BOT0", + "RIOI_I2GCLK_BOT1" + ], + [ + "HCLK_IOI_DCI_TSTCLK", + "IOI_DCI_TSTCLK" + ] + ], + "tile_types": [ + "HCLK_IOI", + "RIOI" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "IOI_IOCLK1", + "IOI_SING_IOCLK1" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_SING_LEAF_GCLK2" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_SING_RCLK_FORIO3" + ], + [ + "IOI_IOCLK3", + "IOI_SING_IOCLK3" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_SING_LEAF_GCLK4" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_SING_RCLK_FORIO2" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_SING_LEAF_GCLK5" + ], + [ + "IOI_TBYTEIN", + "IOI_SING_TBYTEIN" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_SING_LEAF_GCLK1" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_SING_RCLK_FORIO1" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_SING_LEAF_GCLK3" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_SING_RCLK_FORIO0" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_SING_LEAF_GCLK0" + ], + [ + "IOI_IOCLK0", + "IOI_SING_IOCLK0" + ], + [ + "IOI_IOCLK2", + "IOI_SING_IOCLK2" + ] + ], + "tile_types": [ + "LIOI3", + "LIOI3_SING" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX21_2", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX41_2", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_BYP5_2", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX20_2", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX39_2", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B4_2", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_FAN4_2", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX31_2", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX2_2", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_FAN0_2", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_LOGIC_OUTS_B18_2", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX26_2", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX6_2", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B2_2", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX3_2", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_FAN5_2", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_LOGIC_OUTS_B22_2", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B3_2", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_LOGIC_OUTS_B6_2", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_LOGIC_OUTS_B8_2", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX16_2", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX32_2", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B9_2", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_BYP3_2", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX17_2", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX30_2", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_LOGIC_OUTS_B23_2", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX13_2", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_LOGIC_OUTS_B0_2", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX9_2", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX1_2", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_FAN3_2", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN6_2", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX18_2", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX27_2", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B7_2", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_BYP6_2", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX46_2", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP7_2", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX36_2", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_LOGIC_OUTS_B13_2", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B21_2", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_IMUX33_2", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX34_2", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX35_2", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_CTRL0_2", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX37_2", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_BYP4_2", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX5_2", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX44_2", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_FAN1_2", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_BYP1_2", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX12_2", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX0_2", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX29_2", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_LOGIC_OUTS_B16_2", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B11_2", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_CLK0_2", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX45_2", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX10_2", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B5_2", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_LOGIC_OUTS_B17_2", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX23_2", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_LOGIC_OUTS_B20_2", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX7_2", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX24_2", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX47_2", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX28_2", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX4_2", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX11_2", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP0_2", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_CTRL1_2", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX8_2", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX22_2", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX14_2", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_LOGIC_OUTS_B10_2", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_FAN2_2", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX43_2", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_FAN7_2", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX42_2", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_BYP2_2", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_CLK1_2", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX38_2", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX40_2", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX15_2", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX19_2", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX25_2", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B1_2", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_2", + "VBRK_EXT_LOGIC_OUTS_B19" + ] + ], + "tile_types": [ + "GTX_CHANNEL_1", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + -8 + ], + "wire_pairs": [ + [ + "CFG_CENTER_NE2A2_18", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_WW2END0_18", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NE4C1_18", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE2A3_18", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_NW4END2_18", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_NW4A0_18", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_EE4B2_18", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_WL1END0_18", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_LH3_18", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_NE4C2_18", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EL1BEG1_18", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SE4C3_18", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_LH6_18", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WL1END3_18", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_SW4END3_18", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NW4END1_18", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_LH7_18", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_NW2A3_18", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_SW4A3_18", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_WW4END1_18", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_WW2A0_18", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WW2A2_18", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_LH11_18", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW2END3_18", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_EL1BEG0_18", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_SE4BEG1_18", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_NE2A0_18", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_WL1END1_18", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_EE4A0_18", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_SW4A2_18", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_ER1BEG2_18", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_SW4END2_18", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_NE4BEG1_18", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WW4C3_18", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4B1_18", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW2A1_18", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_SW2A3_18", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_SE4BEG3_18", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_NE4BEG2_18", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EE2A0_18", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW4A0_18", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_NW2A1_18", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SW4A0_18", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WW4B3_18", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SW4END0_18", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EE4C3_18", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_EE2A1_18", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_EE4BEG1_18", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_SW2A2_18", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_LH1_18", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_SW2A1_18", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE2BEG2_18", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW4A2_18", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE2BEG0_18", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_SW4END1_18", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EE4BEG0_18", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EL1BEG2_18", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_NW4A1_18", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_EE4B3_18", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_EE4B0_18", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_EE2BEG3_18", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_SW2A0_18", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_LH12_18", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WR1END1_18", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SE4C2_18", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_WW4B0_18", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_EE4A1_18", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EE2A2_18", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_EL1BEG3_18", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WW4A3_18", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_WW4END3_18", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4END0_18", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EE4C2_18", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_WW2END1_18", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE4C1_18", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_ER1BEG0_18", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_SE2A1_18", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW2A3_18", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WW4END2_18", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_LH4_18", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SE2A2_18", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_WW4B2_18", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE2A3_18", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_SE2A3_18", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_EE4BEG3_18", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_SW4A1_18", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NW2A0_18", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WR1END0_18", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_WR1END2_18", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_NE2A1_18", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_SE4BEG0_18", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_EE4A2_18", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4B1_18", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_LH5_18", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE2BEG1_18", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NW2A2_18", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_SE4BEG2_18", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_LH2_18", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NE4BEG0_18", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_LH10_18", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_EE4C0_18", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WL1END2_18", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WW4C0_18", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NW4END3_18", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_SE4C1_18", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_NW4A3_18", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_ER1BEG1_18", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WW4C2_18", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_WW4A1_18", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_LH9_18", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NE4BEG3_18", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_EE4A3_18", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_NW4A2_18", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NE4C0_18", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_SE2A0_18", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SE4C0_18", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_LH8_18", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_ER1BEG3_18", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_EE4BEG2_18", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WR1END3_18", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_WW4C1_18", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_NW4END0_18", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_WW2END2_18", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_NE4C3_18", + "INT_FEEDTHRU_2_NE4C3" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW4C0_6", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4END2_6", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW2A3_6", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4BEG0_6", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_6", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_6", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A3_6", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4A1_6", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4B0_6", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SW4A3_6", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_NE4BEG2_6", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE4B0_6", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE4C1_6", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A1_6", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END1_6", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_6", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_6", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_6", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C1_6", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW4A1_6", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_ER1BEG0_6", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_6", + "VBRK_LH1" + ], + [ + "CMT_TOP_EE4BEG2_6", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG2_6", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SE2A0_6", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WL1END2_6", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A1_6", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WR1END3_6", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NE2A2_6", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_LH4_6", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END1_6", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH8_6", + "VBRK_LH8" + ], + [ + "CMT_TOP_SE4BEG2_6", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4END2_6", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH6_6", + "VBRK_LH6" + ], + [ + "CMT_TOP_MONITOR_N_6", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_LH3_6", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C2_6", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NE2A3_6", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE4C3_6", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4A0_6", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C3_6", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_ER1BEG3_6", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_6", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WR1END2_6", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END0_6", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4C0_6", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SE4C0_6", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SE2A3_6", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_LH2_6", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW2END1_6", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW2END3_6", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE2A0_6", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NE4C0_6", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WW4C3_6", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END1_6", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4BEG3_6", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A1_6", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4B3_6", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4B1_6", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A1_6", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WL1END3_6", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH7_6", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW2A0_6", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A0_6", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NW2A1_6", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2BEG0_6", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_6", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE2BEG1_6", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4END3_6", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NW4END3_6", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4BEG1_6", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_6", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_SW4END2_6", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NW4A3_6", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4BEG0_6", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SW4A2_6", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4C1_6", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2A0_6", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4END0_6", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_ER1BEG2_6", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2A3_6", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW2A0_6", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_LH11_6", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH9_6", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2BEG3_6", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WW4A3_6", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4A0_6", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE2A0_6", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NW2A2_6", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_6", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C3_6", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4A1_6", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WR1END0_6", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4C2_6", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_MONITOR_P_6", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_EE4C1_6", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG3_6", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW4B3_6", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END2_6", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A2_6", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4B2_6", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW4A0_6", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW2A1_6", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH5_6", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4B1_6", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_NE4BEG1_6", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH10_6", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_6", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4A2_6", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG1_6", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE2A1_6", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C2_6", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END0_6", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SE4BEG0_6", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_6", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE4A2_6", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4END0_6", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4BEG3_6", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A3_6", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_6", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_6", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A2_6", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NW2A3_6", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_6", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE4C2_6", + "VBRK_SE4C2" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 8 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH12_0", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH9_0", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH1_0", + "VBRK_LH1" + ], + [ + "CMT_TOP_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH8_0", + "VBRK_LH8" + ], + [ + "CMT_TOP_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH5_0", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH4_0", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH3_0", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_LH10_0", + "VBRK_LH10" + ], + [ + "CMT_TOP_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH11_0", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH7_0", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH2_0", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH6_0", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SW4A1_0", + "VBRK_SW4A1" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "GTXE2_BYP3_1", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX42_1", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX13_1", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP7_1", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX31_1", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX35_1", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX15_1", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX25_1", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B15_1", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX39_1", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_FAN2_1", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX17_1", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_LOGIC_OUTS_B9_1", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX28_1", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX18_1", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX27_1", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B10_1", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX32_1", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN0_1", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_FAN7_1", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX21_1", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX41_1", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX47_1", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_FAN6_1", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_LOGIC_OUTS_B13_1", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B11_1", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_IMUX12_1", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX46_1", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX36_1", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_LOGIC_OUTS_B8_1", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX40_1", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_CLK0_1", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_FAN5_1", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_BYP0_1", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX5_1", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B12_1", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_LOGIC_OUTS_B14_1", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_BYP2_1", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX24_1", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_FAN4_1", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_CLK1_1", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX8_1", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX0_1", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_CTRL0_1", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX6_1", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_CTRL1_1", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX26_1", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_BYP5_1", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX9_1", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX33_1", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX44_1", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX2_1", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX3_1", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX22_1", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX38_1", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_FAN3_1", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX11_1", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX7_1", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX34_1", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX37_1", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX16_1", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_BYP6_1", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX4_1", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX45_1", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX10_1", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX43_1", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX19_1", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX30_1", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_BYP4_1", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX14_1", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX23_1", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX20_1", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX29_1", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX1_1", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_FAN1_1", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_BYP1_1", + "VBRK_EXT_BYP1" + ] + ], + "tile_types": [ + "GTX_COMMON", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + 5 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_5" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_5" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_5" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_5" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_5" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_5" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_5" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_5" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_5" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_5" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_5" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_5" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_5" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_5" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_5" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_5" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_5" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_5" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_5" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_5" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_5" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_5" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_5" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_5" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_5" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_5" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_5" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_5" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_5" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_5" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_5" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_5" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_5" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_5" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_5" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_5" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_5" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_5" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_5" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_5" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_5" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_5" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_5" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_5" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_5" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_5" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_5" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_5" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_5" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_5" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_5" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_5" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_5" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_5" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_5" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_5" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_5" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_5" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_5" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_5" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_5" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_5" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_5" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_5" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_5" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_5" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_5" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_5" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_5" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_5" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_5" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_5" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_5" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_5" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_5" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_5" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_5" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_5" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_5" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_5" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_5" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_5" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_5" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_5" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_5" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_5" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_5" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_5" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_5" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_5" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_5" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_5" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_5" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_5" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_5" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_5" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_5" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_5" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_5" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_5" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_5" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_5" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_5" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_5" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_5" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_5" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_5" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_5" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_5" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_5" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_5" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_5" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_5" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_5" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_5" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_5" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_5" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_5" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_5" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_5" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_5" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_5" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_5" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_5" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_MID_FUJI2" + ] + }, + { + "grid_deltas": [ + 1, + -6 + ], + "wire_pairs": [ + [ + "CFG_CENTER_IMUX3_6", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_WW4B0_6", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_EE4BEG1_6", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_NW2A2_6", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_BYP0_6", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_FAN7_6", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX38_6", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_SW4A2_6", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_BYP6_6", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_NE4C3_6", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_IMUX24_6", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_NW4A0_6", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_WW4A2_6", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_WW2A0_6", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_LH6_6", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX18_6", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX1_6", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_SW2A2_6", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_NW4END0_6", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_EE2A1_6", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_WR1END0_6", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_SE4BEG0_6", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_SW4END3_6", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_BYP1_6", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_NW2A1_6", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_IMUX19_6", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_IMUX36_6", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_WL1END0_6", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_6", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_NW4A1_6", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_LH2_6", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EE4BEG3_6", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_EE4B0_6", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_IMUX45_6", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX37_6", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SW2A3_6", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_BYP2_6", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_EL1BEG0_6", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_FAN1_6", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_LH10_6", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW4END1_6", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_NW4END2_6", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_WW4B3_6", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_LH5_6", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_BYP5_6", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_SE2A2_6", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX4_6", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX17_6", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_6", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_IMUX2_6", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_FAN3_6", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_IMUX27_6", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_SW4A1_6", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_LH7_6", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_FAN0_6", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_6", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_EE4A0_6", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_IMUX9_6", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX13_6", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_SW2A1_6", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_ER1BEG0_6", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_LH12_6", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_WW4C3_6", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX5_6", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX42_6", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_WR1END3_6", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX41_6", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX32_6", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_WW2END3_6", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_IMUX35_6", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_CLK1_6", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX16_6", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WW4A1_6", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_EE4C3_6", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_SE4C2_6", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_SW4END2_6", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_EE2BEG3_6", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX28_6", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_EE4A1_6", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_NE4BEG2_6", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_FAN4_6", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_CLK0_6", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_FAN5_6", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_WW4C2_6", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_BYP4_6", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_EE4BEG0_6", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_FAN2_6", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_NE4BEG1_6", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX8_6", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_SE4BEG3_6", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX29_6", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_EE2A2_6", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_6", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_SE4BEG1_6", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_BYP3_6", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_SW4END0_6", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_EE4C0_6", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_EE4C2_6", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_WW2END1_6", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_EE4B2_6", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_LH1_6", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_IMUX23_6", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW4A0_6", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX20_6", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_IMUX7_6", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_SW4END1_6", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_EE2A0_6", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_SE4C3_6", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_WW4END3_6", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX39_6", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_IMUX31_6", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_EE4A2_6", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX44_6", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WW2END2_6", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_EE2BEG2_6", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX30_6", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_EE2BEG1_6", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX15_6", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_6", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_CTRL0_6", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX11_6", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_EL1BEG3_6", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW2A2_6", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_WW4C1_6", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_LH8_6", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_NE4BEG3_6", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NE4C2_6", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_IMUX47_6", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_NW4A2_6", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_IMUX21_6", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_SE4C1_6", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_EE4B1_6", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_WW2A1_6", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_WW4B1_6", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_IMUX12_6", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_ER1BEG1_6", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_NW4END1_6", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_6", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_NE4BEG0_6", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_EE4C1_6", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_WR1END2_6", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_IMUX46_6", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_IMUX0_6", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WL1END2_6", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_LH3_6", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_SW2A0_6", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_SE4C0_6", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_NW2A0_6", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_NW4A3_6", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_LH9_6", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_IMUX14_6", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_SW4A3_6", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_LH11_6", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_IMUX34_6", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_FAN6_6", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX26_6", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX25_6", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_NE2A3_6", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_EL1BEG2_6", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_SW4A0_6", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_CTRL1_6", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_NE2A2_6", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WL1END3_6", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_ER1BEG3_6", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_NE4C1_6", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_IMUX22_6", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW4END2_6", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_WR1END1_6", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NW4END3_6", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_WW4B2_6", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_IMUX6_6", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_NE2A0_6", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX40_6", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_ER1BEG2_6", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_SE2A0_6", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_IMUX10_6", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_EE4A3_6", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_EE2A3_6", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NW2A3_6", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NE4C0_6", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_WL1END1_6", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_EE4BEG2_6", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE4B3_6", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_SE4BEG2_6", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_WW2END0_6", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_6", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_SE2A3_6", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_EE2BEG0_6", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_SE2A1_6", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_EL1BEG1_6", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_WW4END0_6", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX33_6", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_6", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_BYP7_6", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_WW4C0_6", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_NE2A1_6", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_WW2A3_6", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_WW4A3_6", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_IMUX43_6", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_LH4_6", + "VFRAME_LH4" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLK_BUFG_REBUF_LH7_0", + "VBRK_LH7" + ], + [ + "CLK_BUFG_REBUF_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CLK_BUFG_REBUF_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CLK_BUFG_REBUF_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CLK_BUFG_REBUF_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CLK_BUFG_REBUF_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CLK_BUFG_REBUF_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CLK_BUFG_REBUF_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CLK_BUFG_REBUF_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CLK_BUFG_REBUF_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CLK_BUFG_REBUF_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CLK_BUFG_REBUF_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CLK_BUFG_REBUF_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CLK_BUFG_REBUF_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CLK_BUFG_REBUF_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CLK_BUFG_REBUF_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CLK_BUFG_REBUF_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CLK_BUFG_REBUF_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CLK_BUFG_REBUF_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CLK_BUFG_REBUF_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CLK_BUFG_REBUF_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CLK_BUFG_REBUF_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CLK_BUFG_REBUF_LH2_0", + "VBRK_LH2" + ], + [ + "CLK_BUFG_REBUF_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CLK_BUFG_REBUF_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CLK_BUFG_REBUF_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CLK_BUFG_REBUF_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CLK_BUFG_REBUF_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CLK_BUFG_REBUF_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CLK_BUFG_REBUF_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CLK_BUFG_REBUF_LH12_0", + "VBRK_LH12" + ], + [ + "CLK_BUFG_REBUF_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "CLK_BUFG_REBUF_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CLK_BUFG_REBUF_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CLK_BUFG_REBUF_LH4_0", + "VBRK_LH4" + ], + [ + "CLK_BUFG_REBUF_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CLK_BUFG_REBUF_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CLK_BUFG_REBUF_LH5_0", + "VBRK_LH5" + ], + [ + "CLK_BUFG_REBUF_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CLK_BUFG_REBUF_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CLK_BUFG_REBUF_LH6_0", + "VBRK_LH6" + ], + [ + "CLK_BUFG_REBUF_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CLK_BUFG_REBUF_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CLK_BUFG_REBUF_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CLK_BUFG_REBUF_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CLK_BUFG_REBUF_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CLK_BUFG_REBUF_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CLK_BUFG_REBUF_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CLK_BUFG_REBUF_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CLK_BUFG_REBUF_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CLK_BUFG_REBUF_LH9_0", + "VBRK_LH9" + ], + [ + "CLK_BUFG_REBUF_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CLK_BUFG_REBUF_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CLK_BUFG_REBUF_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CLK_BUFG_REBUF_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CLK_BUFG_REBUF_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CLK_BUFG_REBUF_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CLK_BUFG_REBUF_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CLK_BUFG_REBUF_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CLK_BUFG_REBUF_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CLK_BUFG_REBUF_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CLK_BUFG_REBUF_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CLK_BUFG_REBUF_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CLK_BUFG_REBUF_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CLK_BUFG_REBUF_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CLK_BUFG_REBUF_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CLK_BUFG_REBUF_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CLK_BUFG_REBUF_LH10_0", + "VBRK_LH10" + ], + [ + "CLK_BUFG_REBUF_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CLK_BUFG_REBUF_LH11_0", + "VBRK_LH11" + ], + [ + "CLK_BUFG_REBUF_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CLK_BUFG_REBUF_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CLK_BUFG_REBUF_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CLK_BUFG_REBUF_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CLK_BUFG_REBUF_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CLK_BUFG_REBUF_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CLK_BUFG_REBUF_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CLK_BUFG_REBUF_LH3_0", + "VBRK_LH3" + ], + [ + "CLK_BUFG_REBUF_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CLK_BUFG_REBUF_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CLK_BUFG_REBUF_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CLK_BUFG_REBUF_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CLK_BUFG_REBUF_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CLK_BUFG_REBUF_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CLK_BUFG_REBUF_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CLK_BUFG_REBUF_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CLK_BUFG_REBUF_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CLK_BUFG_REBUF_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CLK_BUFG_REBUF_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CLK_BUFG_REBUF_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CLK_BUFG_REBUF_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CLK_BUFG_REBUF_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CLK_BUFG_REBUF_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CLK_BUFG_REBUF_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CLK_BUFG_REBUF_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CLK_BUFG_REBUF_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CLK_BUFG_REBUF_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CLK_BUFG_REBUF_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CLK_BUFG_REBUF_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CLK_BUFG_REBUF_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CLK_BUFG_REBUF_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CLK_BUFG_REBUF_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CLK_BUFG_REBUF_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CLK_BUFG_REBUF_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CLK_BUFG_REBUF_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CLK_BUFG_REBUF_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CLK_BUFG_REBUF_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CLK_BUFG_REBUF_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CLK_BUFG_REBUF_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CLK_BUFG_REBUF_LH1_0", + "VBRK_LH1" + ], + [ + "CLK_BUFG_REBUF_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CLK_BUFG_REBUF_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CLK_BUFG_REBUF_LH8_0", + "VBRK_LH8" + ], + [ + "CLK_BUFG_REBUF_SW4A1_0", + "VBRK_SW4A1" + ], + [ + "CLK_BUFG_REBUF_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CLK_BUFG_REBUF_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CLK_BUFG_REBUF_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CLK_BUFG_REBUF_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CLK_BUFG_REBUF_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CLK_BUFG_REBUF_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CLK_BUFG_REBUF_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CLK_BUFG_REBUF_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CLK_BUFG_REBUF_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CLK_BUFG_REBUF_NE4C3_0", + "VBRK_NE4C3" + ] + ], + "tile_types": [ + "CLK_BUFG_REBUF", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B21_3", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_FAN7_3", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B9_3", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX6_3", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX40_3", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B10_3", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX23_3", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX35_3", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_CTRL0_3", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX14_3", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX44_3", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX36_3", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_BYP0_3", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX34_3", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX30_3", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX33_3", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX15_3", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX13_3", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP3_3", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_BYP6_3", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX0_3", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_BYP5_3", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX43_3", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX2_3", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX22_3", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX46_3", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX10_3", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_FAN2_3", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX20_3", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN5_3", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX16_3", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_CLK0_3", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX24_3", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX7_3", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_FAN1_3", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX27_3", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX37_3", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX31_3", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B2_3", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_CTRL1_3", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX29_3", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX38_3", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX26_3", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_FAN4_3", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_FAN3_3", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX1_3", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX47_3", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_CLK1_3", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_LOGIC_OUTS_B17_3", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_BYP1_3", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX28_3", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX3_3", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX9_3", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX5_3", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B23_3", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX45_3", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX32_3", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX17_3", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_BYP2_3", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_LOGIC_OUTS_B19_3", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_BYP4_3", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX8_3", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX21_3", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX25_3", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX19_3", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX11_3", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX18_3", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX41_3", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_FAN6_3", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_BYP7_3", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_FAN0_3", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX12_3", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX42_3", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX39_3", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX4_3", + "VBRK_EXT_IMUX4" + ] + ], + "tile_types": [ + "GTX_COMMON", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW2A2_5", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A0_5", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END2_5", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SE4C1_5", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SW4END3_5", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NW4END0_5", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW2A0_5", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WL1END3_5", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SE2A2_5", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4B3_5", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_LH3_5", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE2A2_5", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_5", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4C2_5", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2A0_5", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG1_5", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A1_5", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4A2_5", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END1_5", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW4C0_5", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_5", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4END3_5", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4BEG0_5", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH6_5", + "VBRK_LH6" + ], + [ + "CMT_TOP_EL1BEG1_5", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_EE4A1_5", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_MONITOR_N_5", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW4A2_5", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4A3_5", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NE4BEG0_5", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW2A2_5", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C3_5", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH7_5", + "VBRK_LH7" + ], + [ + "CMT_TOP_WW4B2_5", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH5_5", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4A1_5", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4A0_5", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C1_5", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW2A0_5", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WL1END2_5", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_SE4C0_5", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SW4END2_5", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END1_5", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG0_5", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_WR1END1_5", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EE4C1_5", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG0_5", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NW4END2_5", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_EE2BEG2_5", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4B1_5", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_ER1BEG3_5", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NW2A1_5", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B0_5", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END2_5", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A1_5", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE2A3_5", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_LH11_5", + "VBRK_LH11" + ], + [ + "CMT_TOP_WL1END0_5", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SW4END0_5", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4BEG3_5", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C3_5", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_SE4BEG1_5", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NE2A2_5", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B0_5", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_ER1BEG2_5", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_5", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NE2A0_5", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4BEG1_5", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE2A3_5", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG2_5", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_LH9_5", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4END2_5", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4BEG2_5", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2END0_5", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_ER1BEG0_5", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH4_5", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2A1_5", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE2BEG1_5", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_NE4BEG3_5", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C0_5", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_MONITOR_P_5", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_LH8_5", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4A3_5", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2BEG0_5", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_NE2A1_5", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C3_5", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WL1END1_5", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW4A1_5", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_5", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4A0_5", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4END1_5", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH2_5", + "VBRK_LH2" + ], + [ + "CMT_TOP_NE2A3_5", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW4A0_5", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4A3_5", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4C0_5", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_LH12_5", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH1_5", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_5", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_ER1BEG1_5", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2BEG3_5", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH10_5", + "VBRK_LH10" + ], + [ + "CMT_TOP_SW2A2_5", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WR1END3_5", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NW4END1_5", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NW4A1_5", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WW4C2_5", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WR1END0_5", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4END3_5", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW4A3_5", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4END0_5", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW2A3_5", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4C2_5", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG3_5", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW2A3_5", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4A2_5", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4BEG3_5", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE4B2_5", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW2A0_5", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SE2A0_5", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SE4BEG2_5", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B1_5", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4C1_5", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C2_5", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4C3_5", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_EL1BEG2_5", + "VBRK_EL1BEG2" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_IMUX44", + "IMUX_L44" + ], + [ + "INT_INTERFACE_WW4END3", + "WW4C3" + ], + [ + "INT_INTERFACE_WW2END0", + "WW2A0" + ], + [ + "INT_INTERFACE_EL1BEG2", + "EL1END2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L21", + "LOGIC_OUTS_L21" + ], + [ + "INT_INTERFACE_NE4BEG0", + "NE6A0" + ], + [ + "INT_INTERFACE_EE4A3", + "EE4B3" + ], + [ + "INT_INTERFACE_BYP1", + "BYP_L1" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_PHASER_TO_IO_ICLK" + ], + [ + "INT_INTERFACE_EL1BEG1", + "EL1END1" + ], + [ + "INT_INTERFACE_IMUX30", + "IMUX_L30" + ], + [ + "INT_INTERFACE_WL1END1", + "WL1BEG1" + ], + [ + "INT_INTERFACE_SW4A3", + "SW6BEG3" + ], + [ + "INT_INTERFACE_NW2A3", + "NW2A3" + ], + [ + "INT_INTERFACE_IMUX10", + "IMUX_L10" + ], + [ + "INT_INTERFACE_SE4BEG3", + "SE6A3" + ], + [ + "INT_INTERFACE_IMUX1", + "IMUX_L1" + ], + [ + "INT_INTERFACE_IMUX18", + "IMUX_L18" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "INT_INTERFACE_IMUX45", + "IMUX_L45" + ], + [ + "INT_INTERFACE_ER1BEG1", + "ER1END1" + ], + [ + "INT_INTERFACE_IMUX31", + "IMUX_L31" + ], + [ + "INT_INTERFACE_NW4A1", + "NW6BEG1" + ], + [ + "INT_INTERFACE_SW4A0", + "SW6BEG0" + ], + [ + "INT_INTERFACE_FAN5", + "FAN_L5" + ], + [ + "INT_INTERFACE_IMUX6", + "IMUX_L6" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L20", + "LOGIC_OUTS_L20" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_PHASER_TO_IO_OCLK" + ], + [ + "INT_INTERFACE_CLK0", + "CLK_L0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L14", + "LOGIC_OUTS_L14" + ], + [ + "INT_INTERFACE_NW4END2", + "NW6E2" + ], + [ + "INT_INTERFACE_LH11", + "LH10" + ], + [ + "INT_INTERFACE_IMUX14", + "IMUX_L14" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L19", + "LOGIC_OUTS_L19" + ], + [ + "INT_INTERFACE_WW4A0", + "WW4BEG0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L2", + "LOGIC_OUTS_L2" + ], + [ + "INT_INTERFACE_IMUX2", + "IMUX_L2" + ], + [ + "INT_INTERFACE_WW2END3", + "WW2A3" + ], + [ + "INT_INTERFACE_NW2A0", + "NW2A0" + ], + [ + "INT_INTERFACE_EE4BEG1", + "EE4A1" + ], + [ + "INT_INTERFACE_NW4A2", + "NW6BEG2" + ], + [ + "INT_INTERFACE_EE4B0", + "EE4C0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L17", + "LOGIC_OUTS_L17" + ], + [ + "INT_INTERFACE_WR1END1", + "WR1BEG1" + ], + [ + "INT_INTERFACE_SE4C2", + "SE6END2" + ], + [ + "INT_INTERFACE_CLK1", + "CLK_L1" + ], + [ + "INT_INTERFACE_NE4C1", + "NE6END1" + ], + [ + "INT_INTERFACE_ER1BEG0", + "ER1END0" + ], + [ + "INT_INTERFACE_SW4END3", + "SW6E3" + ], + [ + "INT_INTERFACE_NW2A1", + "NW2A1" + ], + [ + "INT_INTERFACE_WW4C2", + "WW4B2" + ], + [ + "INT_INTERFACE_NE2A1", + "NE2END1" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "INT_INTERFACE_EE4A2", + "EE4B2" + ], + [ + "INT_INTERFACE_IMUX25", + "IMUX_L25" + ], + [ + "INT_INTERFACE_SE4BEG1", + "SE6A1" + ], + [ + "INT_INTERFACE_EE2A2", + "EE2END2" + ], + [ + "INT_INTERFACE_IMUX16", + "IMUX_L16" + ], + [ + "INT_INTERFACE_WR1END0", + "WR1BEG0" + ], + [ + "INT_INTERFACE_SW2A3", + "SW2A3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L11", + "LOGIC_OUTS_L11" + ], + [ + "INT_INTERFACE_WW2END2", + "WW2A2" + ], + [ + "INT_INTERFACE_SE2A3", + "SE2END3" + ], + [ + "INT_INTERFACE_BYP3", + "BYP_L3" + ], + [ + "INT_INTERFACE_EL1BEG0", + "EL1END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L7", + "LOGIC_OUTS_L7" + ], + [ + "INT_INTERFACE_IMUX41", + "IMUX_L41" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L5", + "LOGIC_OUTS_L5" + ], + [ + "INT_INTERFACE_ER1BEG3", + "ER1END3" + ], + [ + "INT_INTERFACE_IMUX47", + "IMUX_L47" + ], + [ + "INT_INTERFACE_EE4A0", + "EE4B0" + ], + [ + "INT_INTERFACE_WW4A2", + "WW4BEG2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L16", + "LOGIC_OUTS_L16" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L10", + "LOGIC_OUTS_L10" + ], + [ + "INT_INTERFACE_SE4BEG2", + "SE6A2" + ], + [ + "INT_INTERFACE_SE4C0", + "SE6END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L15", + "LOGIC_OUTS_L15" + ], + [ + "INT_INTERFACE_EL1BEG3", + "EL1END3" + ], + [ + "INT_INTERFACE_FAN0", + "FAN_L0" + ], + [ + "INT_INTERFACE_IMUX3", + "IMUX_L3" + ], + [ + "INT_INTERFACE_FAN6", + "FAN_L6" + ], + [ + "INT_INTERFACE_NW4END3", + "NW6E3" + ], + [ + "INT_INTERFACE_FAN2", + "FAN_L2" + ], + [ + "INT_INTERFACE_NE2A0", + "NE2END0" + ], + [ + "INT_INTERFACE_WW4A1", + "WW4BEG1" + ], + [ + "INT_INTERFACE_NW4END1", + "NW6E1" + ], + [ + "INT_INTERFACE_IMUX39", + "IMUX_L39" + ], + [ + "INT_INTERFACE_IMUX13", + "IMUX_L13" + ], + [ + "INT_INTERFACE_NE4BEG1", + "NE6A1" + ], + [ + "INT_INTERFACE_IMUX33", + "IMUX_L33" + ], + [ + "INT_INTERFACE_NE4C3", + "NE6END3" + ], + [ + "INT_INTERFACE_IMUX20", + "IMUX_L20" + ], + [ + "INT_INTERFACE_IMUX9", + "IMUX_L9" + ], + [ + "INT_INTERFACE_ER1BEG2", + "ER1END2" + ], + [ + "INT_INTERFACE_EE4C1", + "EE4END1" + ], + [ + "INT_INTERFACE_BYP4", + "BYP_L4" + ], + [ + "INT_INTERFACE_IMUX17", + "IMUX_L17" + ], + [ + "INT_INTERFACE_NE4BEG3", + "NE6A3" + ], + [ + "INT_INTERFACE_SW4A1", + "SW6BEG1" + ], + [ + "INT_INTERFACE_BYP5", + "BYP_L5" + ], + [ + "INT_INTERFACE_EE2BEG0", + "EE2A0" + ], + [ + "INT_INTERFACE_IMUX5", + "IMUX_L5" + ], + [ + "INT_INTERFACE_SE4BEG0", + "SE6A0" + ], + [ + "INT_INTERFACE_LH4", + "LH3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L22", + "LOGIC_OUTS_L22" + ], + [ + "INT_INTERFACE_SE2A0", + "SE2END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L0", + "LOGIC_OUTS_L0" + ], + [ + "INT_INTERFACE_EE2BEG2", + "EE2A2" + ], + [ + "INT_INTERFACE_BYP2", + "BYP_L2" + ], + [ + "INT_INTERFACE_EE4C3", + "EE4END3" + ], + [ + "INT_INTERFACE_IMUX11", + "IMUX_L11" + ], + [ + "INT_INTERFACE_IMUX7", + "IMUX_L7" + ], + [ + "INT_INTERFACE_WW4B2", + "WW4A2" + ], + [ + "INT_INTERFACE_EE2A3", + "EE2END3" + ], + [ + "INT_INTERFACE_SE2A1", + "SE2END1" + ], + [ + "INT_INTERFACE_LH9", + "LH8" + ], + [ + "INT_INTERFACE_IMUX40", + "IMUX_L40" + ], + [ + "INT_INTERFACE_CTRL1", + "CTRL_L1" + ], + [ + "INT_INTERFACE_LH12", + "LH11" + ], + [ + "INT_INTERFACE_IMUX4", + "IMUX_L4" + ], + [ + "INT_INTERFACE_WW4A3", + "WW4BEG3" + ], + [ + "INT_INTERFACE_EE4B3", + "EE4C3" + ], + [ + "INT_INTERFACE_NE4C2", + "NE6END2" + ], + [ + "INT_INTERFACE_EE2BEG1", + "EE2A1" + ], + [ + "INT_INTERFACE_WW2A1", + "WW2BEG1" + ], + [ + "INT_INTERFACE_LH3", + "LH2" + ], + [ + "INT_INTERFACE_BYP7", + "BYP_L7" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L1", + "LOGIC_OUTS_L1" + ], + [ + "INT_INTERFACE_IMUX28", + "IMUX_L28" + ], + [ + "INT_INTERFACE_EE4C0", + "EE4END0" + ], + [ + "INT_INTERFACE_IMUX29", + "IMUX_L29" + ], + [ + "INT_INTERFACE_IMUX27", + "IMUX_L27" + ], + [ + "INT_INTERFACE_LH6", + "LH5" + ], + [ + "L_INT_INTER_DQS_IOTOPHASER", + "INT_DQS_IOTOPHASER" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L6", + "LOGIC_OUTS_L6" + ], + [ + "INT_INTERFACE_IMUX12", + "IMUX_L12" + ], + [ + "INT_INTERFACE_IMUX37", + "IMUX_L37" + ], + [ + "INT_INTERFACE_IMUX22", + "IMUX_L22" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L8", + "LOGIC_OUTS_L8" + ], + [ + "INT_INTERFACE_WL1END0", + "WL1BEG0" + ], + [ + "INT_INTERFACE_IMUX36", + "IMUX_L36" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L13", + "LOGIC_OUTS_L13" + ], + [ + "INT_INTERFACE_WL1END3", + "WL1BEG3" + ], + [ + "INT_INTERFACE_MONITOR_P", + "MONITOR_P" + ], + [ + "INT_INTERFACE_EE2A0", + "EE2END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L23", + "LOGIC_OUTS_L23" + ], + [ + "INT_INTERFACE_SW4END0", + "SW6E0" + ], + [ + "INT_INTERFACE_WW4B1", + "WW4A1" + ], + [ + "INT_INTERFACE_WW4C3", + "WW4B3" + ], + [ + "INT_INTERFACE_WW4C1", + "WW4B1" + ], + [ + "INT_INTERFACE_NW2A2", + "NW2A2" + ], + [ + "INT_INTERFACE_EE4BEG2", + "EE4A2" + ], + [ + "INT_INTERFACE_IMUX43", + "IMUX_L43" + ], + [ + "INT_INTERFACE_EE2A1", + "EE2END1" + ], + [ + "INT_INTERFACE_WW2A0", + "WW2BEG0" + ], + [ + "INT_INTERFACE_WW2A3", + "WW2BEG3" + ], + [ + "INT_INTERFACE_SW2A2", + "SW2A2" + ], + [ + "INT_INTERFACE_NW4END0", + "NW6E0" + ], + [ + "INT_INTERFACE_EE4A1", + "EE4B1" + ], + [ + "INT_INTERFACE_BYP0", + "BYP_L0" + ], + [ + "INT_INTERFACE_SW4END1", + "SW6E1" + ], + [ + "INT_INTERFACE_SE4C3", + "SE6END3" + ], + [ + "INT_INTERFACE_LH10", + "LH9" + ], + [ + "INT_INTERFACE_WR1END2", + "WR1BEG2" + ], + [ + "INT_INTERFACE_EE2BEG3", + "EE2A3" + ], + [ + "INT_INTERFACE_WW4B0", + "WW4A0" + ], + [ + "INT_INTERFACE_IMUX19", + "IMUX_L19" + ], + [ + "INT_INTERFACE_IMUX42", + "IMUX_L42" + ], + [ + "INT_INTERFACE_LH1", + "LH0" + ], + [ + "INT_INTERFACE_LH2", + "LH1" + ], + [ + "INT_INTERFACE_IMUX26", + "IMUX_L26" + ], + [ + "INT_INTERFACE_WL1END2", + "WL1BEG2" + ], + [ + "INT_INTERFACE_LH5", + "LH4" + ], + [ + "INT_INTERFACE_IMUX24", + "IMUX_L24" + ], + [ + "INT_INTERFACE_FAN7", + "FAN_L7" + ], + [ + "INT_INTERFACE_SW2A0", + "SW2A0" + ], + [ + "INT_INTERFACE_SE2A2", + "SE2END2" + ], + [ + "INT_INTERFACE_EE4B2", + "EE4C2" + ], + [ + "INT_INTERFACE_IMUX34", + "IMUX_L34" + ], + [ + "INT_INTERFACE_EE4BEG3", + "EE4A3" + ], + [ + "INT_INTERFACE_LH7", + "LH6" + ], + [ + "INT_INTERFACE_WR1END3", + "WR1BEG3" + ], + [ + "INT_INTERFACE_WW4B3", + "WW4A3" + ], + [ + "INT_INTERFACE_LH8", + "LH7" + ], + [ + "INT_INTERFACE_WW4END2", + "WW4C2" + ], + [ + "INT_INTERFACE_IMUX35", + "IMUX_L35" + ], + [ + "INT_INTERFACE_SE4C1", + "SE6END1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L3", + "LOGIC_OUTS_L3" + ], + [ + "INT_INTERFACE_NE2A3", + "NE2END3" + ], + [ + "INT_INTERFACE_IMUX46", + "IMUX_L46" + ], + [ + "INT_INTERFACE_NE4BEG2", + "NE6A2" + ], + [ + "INT_INTERFACE_FAN1", + "FAN_L1" + ], + [ + "INT_INTERFACE_NW4A0", + "NW6BEG0" + ], + [ + "INT_INTERFACE_IMUX8", + "IMUX_L8" + ], + [ + "INT_INTERFACE_WW4C0", + "WW4B0" + ], + [ + "INT_INTERFACE_NE2A2", + "NE2END2" + ], + [ + "INT_INTERFACE_IMUX32", + "IMUX_L32" + ], + [ + "INT_INTERFACE_SW4END2", + "SW6E2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L18", + "LOGIC_OUTS_L18" + ], + [ + "INT_INTERFACE_MONITOR_N", + "MONITOR_N" + ], + [ + "INT_INTERFACE_WW4END1", + "WW4C1" + ], + [ + "INT_INTERFACE_IMUX21", + "IMUX_L21" + ], + [ + "INT_INTERFACE_EE4B1", + "EE4C1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L12", + "LOGIC_OUTS_L12" + ], + [ + "INT_INTERFACE_FAN4", + "FAN_L4" + ], + [ + "INT_INTERFACE_WW4END0", + "WW4C0" + ], + [ + "INT_INTERFACE_EE4BEG0", + "EE4A0" + ], + [ + "INT_INTERFACE_BYP6", + "BYP_L6" + ], + [ + "INT_INTERFACE_WW2A2", + "WW2BEG2" + ], + [ + "INT_INTERFACE_IMUX0", + "IMUX_L0" + ], + [ + "INT_INTERFACE_NW4A3", + "NW6BEG3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L4", + "LOGIC_OUTS_L4" + ], + [ + "INT_INTERFACE_FAN3", + "FAN_L3" + ], + [ + "INT_INTERFACE_EE4C2", + "EE4END2" + ], + [ + "INT_INTERFACE_IMUX23", + "IMUX_L23" + ], + [ + "INT_INTERFACE_SW4A2", + "SW6BEG2" + ], + [ + "INT_INTERFACE_WW2END1", + "WW2A1" + ], + [ + "INT_INTERFACE_IMUX38", + "IMUX_L38" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_PHASER_TO_IO_OCLK1X_90" + ], + [ + "INT_INTERFACE_SW2A1", + "SW2A1" + ], + [ + "INT_INTERFACE_NE4C0", + "NE6END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L9", + "LOGIC_OUTS_L9" + ], + [ + "INT_INTERFACE_CTRL0", + "CTRL_L0" + ], + [ + "INT_INTERFACE_IMUX15", + "IMUX_L15" + ] + ], + "tile_types": [ + "INT_INTERFACE_L", + "INT_L" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH12_0", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH9_0", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH1_0", + "VBRK_LH1" + ], + [ + "CMT_TOP_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH8_0", + "VBRK_LH8" + ], + [ + "CMT_TOP_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH5_0", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH4_0", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH3_0", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_LH10_0", + "VBRK_LH10" + ], + [ + "CMT_TOP_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH11_0", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_MONITOR_N_0", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH7_0", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH2_0", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH6_0", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_MONITOR_P_0", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SW4A1_0", + "VBRK_SW4A1" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLK_PMV_IMUX25_0", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_PMV_IMUX14_0", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_PMV_IMUX6_0", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_PMV_IMUX46_0", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_PMV_IMUX34_0", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_FEED_WW4B1", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_PMV_IMUX7_0", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_PMV_IMUX28_0", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_PMV_IMUX11_0", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_FEED_WL1END2", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_FEED_EE4BEG2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_FEED_LH8", + "INT_INTERFACE_LH8" + ], + [ + "CLK_PMV_IMUX8_0", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_FEED_WW4C1", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_PMV_IMUX37_0", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_PMV_IMUX19_0", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_FEED_WR1END3", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_FEED_EE4B3", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_PMV_IMUX3_0", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_PMV_FAN0_0", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_FEED_NE2A2", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_PMV_IMUX10_0", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_FEED_WL1END0", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_FEED_NE2A1", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_FEED_WW4C2", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_PMV_IMUX45_0", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_FEED_NW2A2", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_FEED_WW2A0", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_FEED_WR1END1", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_PMV_IMUX18_0", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_FEED_SE4BEG2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_PMV_BYP1_0", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_PMV_IMUX39_0", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_FEED_NW2A1", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_FEED_EE4A2", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_PMV_FAN7_0", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_PMV_IMUX17_0", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_FEED_NW2A0", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_PMV_IMUX29_0", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_FEED_WW4B2", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_FEED_WL1END1", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_PMV_IMUX35_0", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_FEED_NE2A0", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_FEED_WW4C0", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_FEED_WW4END0", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_FEED_EE4C1", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_FEED_EE4C0", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_FEED_EE4BEG0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_FEED_LH11", + "INT_INTERFACE_LH11" + ], + [ + "CLK_PMV_IMUX27_0", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_PMV_IMUX22_0", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_PMV_BYP4_0", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_FEED_WW4END2", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_FEED_SE4BEG1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_FEED_NW4A3", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_PMV_IMUX1_0", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_FEED_EE2BEG3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_FEED_SE2A2", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_FEED_EE2BEG2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_FEED_NW4A0", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_PMV_FAN5_0", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_FEED_LH5", + "INT_INTERFACE_LH5" + ], + [ + "CLK_FEED_WW2A1", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_PMV_IMUX40_0", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_FEED_WW4C3", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_FEED_WW4A2", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_FEED_SW4END1", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_FEED_EE2A2", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_PMV_BYP2_0", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_FEED_NW4END2", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_PMV_IMUX38_0", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_FEED_SW4END2", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_PMV_BYP7_0", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_PMV_BYP5_0", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_FEED_ER1BEG1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_FEED_EE4BEG3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_FEED_WW4A0", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_FEED_NE4C2", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_PMV_IMUX21_0", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_FEED_EE2A0", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_PMV_IMUX26_0", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_FEED_NE4C1", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_PMV_BYP6_0", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_FEED_SE4C2", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_FEED_SE2A1", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_PMV_IMUX43_0", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_FEED_SE4C0", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_FEED_LH1", + "INT_INTERFACE_LH1" + ], + [ + "CLK_FEED_NE4BEG3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_PMV_CTRL0_0", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_FEED_WW2END2", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_FEED_EE4B2", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_FEED_MONITOR_P", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_FEED_WW2END0", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_PMV_FAN1_0", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_FEED_EE4B1", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_FEED_NE2A3", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_PMV_IMUX0_0", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_PMV_IMUX9_0", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_FEED_MONITOR_N", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_PMV_BYP3_0", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_FEED_WW4B0", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_FEED_SW4A1", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_FEED_SE2A3", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_FEED_WW4END1", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_PMV_IMUX30_0", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_FEED_ER1BEG2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_FEED_WR1END2", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_FEED_WR1END0", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_FEED_EE2A3", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_FEED_NE4C0", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_FEED_SE4C3", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_FEED_LH9", + "INT_INTERFACE_LH9" + ], + [ + "CLK_FEED_WW4A1", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_FEED_LH3", + "INT_INTERFACE_LH3" + ], + [ + "CLK_FEED_EL1BEG3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_FEED_EE4A0", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_PMV_IMUX23_0", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_PMV_IMUX31_0", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_FEED_SW4A3", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_FEED_NW2A3", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_PMV_IMUX20_0", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_FEED_SW4END3", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_FEED_WL1END3", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_PMV_IMUX47_0", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_FEED_SE2A0", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_PMV_IMUX24_0", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_PMV_FAN3_0", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_FEED_NW4END3", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_FEED_EE2A1", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_FEED_SW4END0", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_FEED_EL1BEG2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_FEED_LH2", + "INT_INTERFACE_LH2" + ], + [ + "CLK_FEED_EE2BEG1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_PMV_IMUX15_0", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_FEED_SW2A2", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_FEED_EE4B0", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_FEED_LH6", + "INT_INTERFACE_LH6" + ], + [ + "CLK_FEED_SW2A1", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_PMV_IMUX41_0", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_FEED_SW2A0", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_FEED_EE4A3", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_FEED_EE4A1", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_FEED_EE4BEG1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_FEED_ER1BEG0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_FEED_NE4BEG1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_PMV_CLK0_0", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_PMV_FAN2_0", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_PMV_FAN4_0", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_FEED_EL1BEG0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_PMV_IMUX13_0", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_FEED_WW2END1", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_FEED_NE4BEG2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_FEED_WW4A3", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_FEED_EE2BEG0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_PMV_CLK1_0", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_PMV_LOGIC_OUTS19_0", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CLK_FEED_WW4END3", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_PMV_IMUX2_0", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_PMV_FAN6_0", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_FEED_NE4BEG0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_FEED_SW4A2", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_PMV_IMUX12_0", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_FEED_WW4B3", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_FEED_NE4C3", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_PMV_IMUX5_0", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_PMV_IMUX32_0", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_PMV_LOGIC_OUTS5_0", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CLK_PMV_IMUX42_0", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_FEED_SE4BEG0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_FEED_LH12", + "INT_INTERFACE_LH12" + ], + [ + "CLK_PMV_LOGIC_OUTS9_0", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CLK_FEED_ER1BEG3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_PMV_CTRL1_0", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_PMV_IMUX36_0", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_PMV_IMUX16_0", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_PMV_BYP0_0", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_FEED_NW4END0", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_FEED_LH4", + "INT_INTERFACE_LH4" + ], + [ + "CLK_FEED_EE4C3", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_FEED_SW2A3", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_FEED_EL1BEG1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_FEED_SW4A0", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_FEED_LH10", + "INT_INTERFACE_LH10" + ], + [ + "CLK_FEED_NW4END1", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_PMV_IMUX33_0", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_FEED_WW2A3", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_PMV_IMUX44_0", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_FEED_NW4A2", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_FEED_WW2END3", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_FEED_LH7", + "INT_INTERFACE_LH7" + ], + [ + "CLK_FEED_EE4C2", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_FEED_SE4C1", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_FEED_NW4A1", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_FEED_WW2A2", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_PMV_IMUX4_0", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_FEED_SE4BEG3", + "INT_INTERFACE_SE4BEG3" + ] + ], + "tile_types": [ + "CLK_PMV2", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLBLL_EE4A3", + "EE4B3" + ], + [ + "CLBLL_EE4A0", + "EE4B0" + ], + [ + "CLBLL_BYP0", + "BYP_L0" + ], + [ + "CLBLL_EE4B1", + "EE4C1" + ], + [ + "CLBLL_EE4C2", + "EE4END2" + ], + [ + "CLBLL_IMUX5", + "IMUX_L5" + ], + [ + "CLBLL_CTRL0", + "CTRL_L0" + ], + [ + "CLBLL_NW2A2", + "NW2A2" + ], + [ + "CLBLL_EE2A1", + "EE2END1" + ], + [ + "CLBLL_LH7", + "LH6" + ], + [ + "CLBLL_LH11", + "LH10" + ], + [ + "CLBLL_EE2BEG1", + "EE2A1" + ], + [ + "CLBLL_NE4BEG2", + "NE6A2" + ], + [ + "CLBLL_IMUX44", + "IMUX_L44" + ], + [ + "CLBLL_BYP2", + "BYP_L2" + ], + [ + "CLBLL_IMUX39", + "IMUX_L39" + ], + [ + "CLBLL_IMUX7", + "IMUX_L7" + ], + [ + "CLBLL_SE2A2", + "SE2END2" + ], + [ + "CLBLL_WW4END0", + "WW4C0" + ], + [ + "CLBLL_IMUX3", + "IMUX_L3" + ], + [ + "CLBLL_LH10", + "LH9" + ], + [ + "CLBLL_EE2A2", + "EE2END2" + ], + [ + "CLBLL_LOGIC_OUTS17", + "LOGIC_OUTS_L17" + ], + [ + "CLBLL_WR1END0", + "WR1BEG0" + ], + [ + "CLBLL_EE2A3", + "EE2END3" + ], + [ + "CLBLL_WW4B3", + "WW4A3" + ], + [ + "CLBLL_NE2A1", + "NE2END1" + ], + [ + "CLBLL_FAN4", + "FAN_L4" + ], + [ + "CLBLL_IMUX11", + "IMUX_L11" + ], + [ + "CLBLL_BYP6", + "BYP_L6" + ], + [ + "CLBLL_WW4C2", + "WW4B2" + ], + [ + "CLBLL_LOGIC_OUTS20", + "LOGIC_OUTS_L20" + ], + [ + "CLBLL_WW4END1", + "WW4C1" + ], + [ + "CLBLL_IMUX9", + "IMUX_L9" + ], + [ + "CLBLL_NW4END1", + "NW6E1" + ], + [ + "CLBLL_SE2A3", + "SE2END3" + ], + [ + "CLBLL_IMUX18", + "IMUX_L18" + ], + [ + "CLBLL_WW4C0", + "WW4B0" + ], + [ + "CLBLL_SE2A0", + "SE2END0" + ], + [ + "CLBLL_WW2A2", + "WW2BEG2" + ], + [ + "CLBLL_EE4A2", + "EE4B2" + ], + [ + "CLBLL_NW4END0", + "NW6E0" + ], + [ + "CLBLL_SW4END0", + "SW6E0" + ], + [ + "CLBLL_EE4BEG0", + "EE4A0" + ], + [ + "CLBLL_SW4A0", + "SW6BEG0" + ], + [ + "CLBLL_WW2A1", + "WW2BEG1" + ], + [ + "CLBLL_SW2A0", + "SW2A0" + ], + [ + "CLBLL_IMUX41", + "IMUX_L41" + ], + [ + "CLBLL_SE4C1", + "SE6END1" + ], + [ + "CLBLL_IMUX15", + "IMUX_L15" + ], + [ + "CLBLL_IMUX24", + "IMUX_L24" + ], + [ + "CLBLL_WR1END2", + "WR1BEG2" + ], + [ + "CLBLL_IMUX34", + "IMUX_L34" + ], + [ + "CLBLL_IMUX26", + "IMUX_L26" + ], + [ + "CLBLL_LH4", + "LH3" + ], + [ + "CLBLL_SW4A2", + "SW6BEG2" + ], + [ + "CLBLL_IMUX35", + "IMUX_L35" + ], + [ + "CLBLL_IMUX2", + "IMUX_L2" + ], + [ + "CLBLL_BYP4", + "BYP_L4" + ], + [ + "CLBLL_MONITOR_N", + "MONITOR_N" + ], + [ + "CLBLL_IMUX42", + "IMUX_L42" + ], + [ + "CLBLL_LH1", + "LH0" + ], + [ + "CLBLL_FAN6", + "FAN_L6" + ], + [ + "CLBLL_NW2A3", + "NW2A3" + ], + [ + "CLBLL_IMUX20", + "IMUX_L20" + ], + [ + "CLBLL_WW2END1", + "WW2A1" + ], + [ + "CLBLL_IMUX1", + "IMUX_L1" + ], + [ + "CLBLL_NE2A3", + "NE2END3" + ], + [ + "CLBLL_WW2A0", + "WW2BEG0" + ], + [ + "CLBLL_NE2A2", + "NE2END2" + ], + [ + "CLBLL_LOGIC_OUTS5", + "LOGIC_OUTS_L5" + ], + [ + "CLBLL_SW4END3", + "SW6E3" + ], + [ + "CLBLL_IMUX37", + "IMUX_L37" + ], + [ + "CLBLL_IMUX6", + "IMUX_L6" + ], + [ + "CLBLL_NW4END2", + "NW6E2" + ], + [ + "CLBLL_IMUX0", + "IMUX_L0" + ], + [ + "CLBLL_NW4A3", + "NW6BEG3" + ], + [ + "CLBLL_WW4A0", + "WW4BEG0" + ], + [ + "CLBLL_EL1BEG3", + "EL1END3" + ], + [ + "CLBLL_FAN3", + "FAN_L3" + ], + [ + "CLBLL_IMUX13", + "IMUX_L13" + ], + [ + "CLBLL_IMUX46", + "IMUX_L46" + ], + [ + "CLBLL_WW2END2", + "WW2A2" + ], + [ + "CLBLL_WW4B0", + "WW4A0" + ], + [ + "CLBLL_EE4C3", + "EE4END3" + ], + [ + "CLBLL_SE4C3", + "SE6END3" + ], + [ + "CLBLL_EE4B2", + "EE4C2" + ], + [ + "CLBLL_IMUX16", + "IMUX_L16" + ], + [ + "CLBLL_IMUX27", + "IMUX_L27" + ], + [ + "CLBLL_LOGIC_OUTS4", + "LOGIC_OUTS_L4" + ], + [ + "CLBLL_WL1END0", + "WL1BEG0" + ], + [ + "CLBLL_SW4END1", + "SW6E1" + ], + [ + "CLBLL_CTRL1", + "CTRL_L1" + ], + [ + "CLBLL_WW4C3", + "WW4B3" + ], + [ + "CLBLL_NE4C3", + "NE6END3" + ], + [ + "CLBLL_LOGIC_OUTS13", + "LOGIC_OUTS_L13" + ], + [ + "CLBLL_LOGIC_OUTS22", + "LOGIC_OUTS_L22" + ], + [ + "CLBLL_LH9", + "LH8" + ], + [ + "CLBLL_WW4C1", + "WW4B1" + ], + [ + "CLBLL_EE4BEG3", + "EE4A3" + ], + [ + "CLBLL_IMUX12", + "IMUX_L12" + ], + [ + "CLBLL_WL1END2", + "WL1BEG2" + ], + [ + "CLBLL_EE2BEG0", + "EE2A0" + ], + [ + "CLBLL_LOGIC_OUTS19", + "LOGIC_OUTS_L19" + ], + [ + "CLBLL_LOGIC_OUTS11", + "LOGIC_OUTS_L11" + ], + [ + "CLBLL_NE4C2", + "NE6END2" + ], + [ + "CLBLL_NE4C0", + "NE6END0" + ], + [ + "CLBLL_IMUX22", + "IMUX_L22" + ], + [ + "CLBLL_SE4BEG0", + "SE6A0" + ], + [ + "CLBLL_IMUX47", + "IMUX_L47" + ], + [ + "CLBLL_LOGIC_OUTS23", + "LOGIC_OUTS_L23" + ], + [ + "CLBLL_IMUX17", + "IMUX_L17" + ], + [ + "CLBLL_WL1END3", + "WL1BEG3" + ], + [ + "CLBLL_SE4BEG3", + "SE6A3" + ], + [ + "CLBLL_CLK1", + "CLK_L1" + ], + [ + "CLBLL_NW2A0", + "NW2A0" + ], + [ + "CLBLL_LOGIC_OUTS7", + "LOGIC_OUTS_L7" + ], + [ + "CLBLL_SE4C2", + "SE6END2" + ], + [ + "CLBLL_SW4A1", + "SW6BEG1" + ], + [ + "CLBLL_LOGIC_OUTS2", + "LOGIC_OUTS_L2" + ], + [ + "CLBLL_SW2A2", + "SW2A2" + ], + [ + "CLBLL_WW4END2", + "WW4C2" + ], + [ + "CLBLL_LOGIC_OUTS1", + "LOGIC_OUTS_L1" + ], + [ + "CLBLL_SE4BEG2", + "SE6A2" + ], + [ + "CLBLL_WW4B1", + "WW4A1" + ], + [ + "CLBLL_EE4B0", + "EE4C0" + ], + [ + "CLBLL_FAN0", + "FAN_L0" + ], + [ + "CLBLL_NE2A0", + "NE2END0" + ], + [ + "CLBLL_LH3", + "LH2" + ], + [ + "CLBLL_NE4BEG0", + "NE6A0" + ], + [ + "CLBLL_LH2", + "LH1" + ], + [ + "CLBLL_NW2A1", + "NW2A1" + ], + [ + "CLBLL_SE4C0", + "SE6END0" + ], + [ + "CLBLL_IMUX45", + "IMUX_L45" + ], + [ + "CLBLL_LH6", + "LH5" + ], + [ + "CLBLL_IMUX33", + "IMUX_L33" + ], + [ + "CLBLL_WR1END3", + "WR1BEG3" + ], + [ + "CLBLL_SE2A1", + "SE2END1" + ], + [ + "CLBLL_LOGIC_OUTS3", + "LOGIC_OUTS_L3" + ], + [ + "CLBLL_LOGIC_OUTS14", + "LOGIC_OUTS_L14" + ], + [ + "CLBLL_FAN1", + "FAN_L1" + ], + [ + "CLBLL_SW4END2", + "SW6E2" + ], + [ + "CLBLL_SE4BEG1", + "SE6A1" + ], + [ + "CLBLL_NE4C1", + "NE6END1" + ], + [ + "CLBLL_SW2A1", + "SW2A1" + ], + [ + "CLBLL_IMUX36", + "IMUX_L36" + ], + [ + "CLBLL_IMUX28", + "IMUX_L28" + ], + [ + "CLBLL_WW2END0", + "WW2A0" + ], + [ + "CLBLL_WW2A3", + "WW2BEG3" + ], + [ + "CLBLL_EE4B3", + "EE4C3" + ], + [ + "CLBLL_EL1BEG2", + "EL1END2" + ], + [ + "CLBLL_LOGIC_OUTS8", + "LOGIC_OUTS_L8" + ], + [ + "CLBLL_EE4BEG2", + "EE4A2" + ], + [ + "CLBLL_EE4C1", + "EE4END1" + ], + [ + "CLBLL_BYP3", + "BYP_L3" + ], + [ + "CLBLL_IMUX38", + "IMUX_L38" + ], + [ + "CLBLL_LOGIC_OUTS12", + "LOGIC_OUTS_L12" + ], + [ + "CLBLL_WW4END3", + "WW4C3" + ], + [ + "CLBLL_FAN7", + "FAN_L7" + ], + [ + "CLBLL_LOGIC_OUTS18", + "LOGIC_OUTS_L18" + ], + [ + "CLBLL_IMUX43", + "IMUX_L43" + ], + [ + "CLBLL_LH8", + "LH7" + ], + [ + "CLBLL_BYP1", + "BYP_L1" + ], + [ + "CLBLL_IMUX21", + "IMUX_L21" + ], + [ + "CLBLL_ER1BEG1", + "ER1END1" + ], + [ + "CLBLL_WL1END1", + "WL1BEG1" + ], + [ + "CLBLL_SW4A3", + "SW6BEG3" + ], + [ + "CLBLL_EE2BEG3", + "EE2A3" + ], + [ + "CLBLL_NE4BEG3", + "NE6A3" + ], + [ + "CLBLL_IMUX19", + "IMUX_L19" + ], + [ + "CLBLL_IMUX30", + "IMUX_L30" + ], + [ + "CLBLL_LOGIC_OUTS0", + "LOGIC_OUTS_L0" + ], + [ + "CLBLL_IMUX25", + "IMUX_L25" + ], + [ + "CLBLL_EE4BEG1", + "EE4A1" + ], + [ + "CLBLL_IMUX14", + "IMUX_L14" + ], + [ + "CLBLL_IMUX32", + "IMUX_L32" + ], + [ + "CLBLL_WW4A1", + "WW4BEG1" + ], + [ + "CLBLL_IMUX31", + "IMUX_L31" + ], + [ + "CLBLL_LOGIC_OUTS21", + "LOGIC_OUTS_L21" + ], + [ + "CLBLL_IMUX10", + "IMUX_L10" + ], + [ + "CLBLL_LOGIC_OUTS6", + "LOGIC_OUTS_L6" + ], + [ + "CLBLL_IMUX8", + "IMUX_L8" + ], + [ + "CLBLL_LOGIC_OUTS15", + "LOGIC_OUTS_L15" + ], + [ + "CLBLL_IMUX29", + "IMUX_L29" + ], + [ + "CLBLL_EL1BEG0", + "EL1END0" + ], + [ + "CLBLL_EE2BEG2", + "EE2A2" + ], + [ + "CLBLL_MONITOR_P", + "MONITOR_P" + ], + [ + "CLBLL_FAN2", + "FAN_L2" + ], + [ + "CLBLL_LH5", + "LH4" + ], + [ + "CLBLL_IMUX23", + "IMUX_L23" + ], + [ + "CLBLL_IMUX4", + "IMUX_L4" + ], + [ + "CLBLL_EL1BEG1", + "EL1END1" + ], + [ + "CLBLL_NW4A1", + "NW6BEG1" + ], + [ + "CLBLL_NW4END3", + "NW6E3" + ], + [ + "CLBLL_WW4A3", + "WW4BEG3" + ], + [ + "CLBLL_BYP7", + "BYP_L7" + ], + [ + "CLBLL_LOGIC_OUTS16", + "LOGIC_OUTS_L16" + ], + [ + "CLBLL_NE4BEG1", + "NE6A1" + ], + [ + "CLBLL_ER1BEG0", + "ER1END0" + ], + [ + "CLBLL_LOGIC_OUTS9", + "LOGIC_OUTS_L9" + ], + [ + "CLBLL_EE4A1", + "EE4B1" + ], + [ + "CLBLL_LH12", + "LH11" + ], + [ + "CLBLL_EE4C0", + "EE4END0" + ], + [ + "CLBLL_WW4A2", + "WW4BEG2" + ], + [ + "CLBLL_NW4A0", + "NW6BEG0" + ], + [ + "CLBLL_LOGIC_OUTS10", + "LOGIC_OUTS_L10" + ], + [ + "CLBLL_NW4A2", + "NW6BEG2" + ], + [ + "CLBLL_CLK0", + "CLK_L0" + ], + [ + "CLBLL_IMUX40", + "IMUX_L40" + ], + [ + "CLBLL_BYP5", + "BYP_L5" + ], + [ + "CLBLL_FAN5", + "FAN_L5" + ], + [ + "CLBLL_EE2A0", + "EE2END0" + ], + [ + "CLBLL_WW4B2", + "WW4A2" + ], + [ + "CLBLL_WW2END3", + "WW2A3" + ], + [ + "CLBLL_WR1END1", + "WR1BEG1" + ], + [ + "CLBLL_SW2A3", + "SW2A3" + ], + [ + "CLBLL_ER1BEG2", + "ER1END2" + ], + [ + "CLBLL_ER1BEG3", + "ER1END3" + ] + ], + "tile_types": [ + "CLBLL_L", + "INT_L" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_1" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_1" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_1" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_1" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_1" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_1" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_1" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_1" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_1" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_1" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_1" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_1" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_1" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_1" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_1" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_1" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_1" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_1" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_1" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_1" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_1" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_1" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_1" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_1" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_1" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_1" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_1" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_1" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_1" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_1" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_1" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_1" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_1" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_1" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_1" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_1" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_1" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_1" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_1" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_1" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_1" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_1" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_1" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_1" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_1" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_1" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_1" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_1" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_1" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_1" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_1" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_1" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_1" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_1" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_1" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_1" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_1" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_1" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_1" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_1" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_1" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_1" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_1" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_1" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_1" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_1" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_1" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_1" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_1" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_1" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_1" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_1" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_1" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_1" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_1" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_1" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_1" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_1" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_1" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_1" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_1" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_1" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_1" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_1" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_1" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_1" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_1" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_1" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_1" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_1" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_1" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_1" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_1" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_1" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_1" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_1" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_1" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_1" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_1" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_1" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_1" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_1" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_1" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_1" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_1" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_1" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_1" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_1" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_1" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_1" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_1" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_1" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_1" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_1" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_1" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_1" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_1" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_1" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_1" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_1" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_BOT_FUJI2" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "BRAM_EE4A1_2", + "CLBLM_EE4A1" + ], + [ + "BRAM_SE4BEG1_2", + "CLBLM_SE4BEG1" + ], + [ + "BRAM_LH6_2", + "CLBLM_LH6" + ], + [ + "BRAM_WR1END3_2", + "CLBLM_WR1END3" + ], + [ + "BRAM_EE4BEG2_2", + "CLBLM_EE4BEG2" + ], + [ + "BRAM_EL1BEG0_2", + "CLBLM_EL1BEG0" + ], + [ + "BRAM_WW4C3_2", + "CLBLM_WW4C3" + ], + [ + "BRAM_NE2A2_2", + "CLBLM_NE2A2" + ], + [ + "BRAM_WW4B1_2", + "CLBLM_WW4B1" + ], + [ + "BRAM_NW4END2_2", + "CLBLM_NW4END2" + ], + [ + "BRAM_ER1BEG1_2", + "CLBLM_ER1BEG1" + ], + [ + "BRAM_WW4C2_2", + "CLBLM_WW4C2" + ], + [ + "BRAM_NW4A0_2", + "CLBLM_NW4A0" + ], + [ + "BRAM_EE4C1_2", + "CLBLM_EE4C1" + ], + [ + "BRAM_NW2A0_2", + "CLBLM_NW2A0" + ], + [ + "BRAM_SW4A2_2", + "CLBLM_SW4A2" + ], + [ + "BRAM_EE4BEG0_2", + "CLBLM_EE4BEG0" + ], + [ + "BRAM_SW4A0_2", + "CLBLM_SW4A0" + ], + [ + "BRAM_WW2A1_2", + "CLBLM_WW2A1" + ], + [ + "BRAM_WL1END0_2", + "CLBLM_WL1END0" + ], + [ + "BRAM_WW4C1_2", + "CLBLM_WW4C1" + ], + [ + "BRAM_EL1BEG2_2", + "CLBLM_EL1BEG2" + ], + [ + "BRAM_NE4BEG2_2", + "CLBLM_NE4BEG2" + ], + [ + "BRAM_SW2A2_2", + "CLBLM_SW2A2" + ], + [ + "BRAM_ER1BEG2_2", + "CLBLM_ER1BEG2" + ], + [ + "BRAM_WL1END1_2", + "CLBLM_WL1END1" + ], + [ + "BRAM_SE4BEG2_2", + "CLBLM_SE4BEG2" + ], + [ + "BRAM_NE2A3_2", + "CLBLM_NE2A3" + ], + [ + "BRAM_EE4A2_2", + "CLBLM_EE4A2" + ], + [ + "BRAM_WL1END3_2", + "CLBLM_WL1END3" + ], + [ + "BRAM_NE2A1_2", + "CLBLM_NE2A1" + ], + [ + "BRAM_WW4C0_2", + "CLBLM_WW4C0" + ], + [ + "BRAM_EE4B1_2", + "CLBLM_EE4B1" + ], + [ + "BRAM_LH12_2", + "CLBLM_LH12" + ], + [ + "BRAM_NW4END0_2", + "CLBLM_NW4END0" + ], + [ + "BRAM_LH10_2", + "CLBLM_LH10" + ], + [ + "BRAM_EE2A2_2", + "CLBLM_EE2A2" + ], + [ + "BRAM_EE2A0_2", + "CLBLM_EE2A0" + ], + [ + "BRAM_NE4BEG3_2", + "CLBLM_NE4BEG3" + ], + [ + "BRAM_WW4B0_2", + "CLBLM_WW4B0" + ], + [ + "BRAM_LH4_2", + "CLBLM_LH4" + ], + [ + "BRAM_NW4A3_2", + "CLBLM_NW4A3" + ], + [ + "BRAM_WW2END0_2", + "CLBLM_WW2END0" + ], + [ + "BRAM_SE4BEG3_2", + "CLBLM_SE4BEG3" + ], + [ + "BRAM_WW2A2_2", + "CLBLM_WW2A2" + ], + [ + "BRAM_SE2A1_2", + "CLBLM_SE2A1" + ], + [ + "BRAM_SW4END3_2", + "CLBLM_SW4END3" + ], + [ + "BRAM_EE2BEG3_2", + "CLBLM_EE2BEG3" + ], + [ + "BRAM_SE2A0_2", + "CLBLM_SE2A0" + ], + [ + "BRAM_WW4A0_2", + "CLBLM_WW4A0" + ], + [ + "BRAM_EE4BEG1_2", + "CLBLM_EE4BEG1" + ], + [ + "BRAM_MONITOR_P_2", + "CLBLM_MONITOR_P" + ], + [ + "BRAM_NW4A2_2", + "CLBLM_NW4A2" + ], + [ + "BRAM_WR1END1_2", + "CLBLM_WR1END1" + ], + [ + "BRAM_SW2A0_2", + "CLBLM_SW2A0" + ], + [ + "BRAM_LH5_2", + "CLBLM_LH5" + ], + [ + "BRAM_WW2A3_2", + "CLBLM_WW2A3" + ], + [ + "BRAM_WW4END2_2", + "CLBLM_WW4END2" + ], + [ + "BRAM_NW4END1_2", + "CLBLM_NW4END1" + ], + [ + "BRAM_WW4B3_2", + "CLBLM_WW4B3" + ], + [ + "BRAM_EE2A1_2", + "CLBLM_EE2A1" + ], + [ + "BRAM_NE2A0_2", + "CLBLM_NE2A0" + ], + [ + "BRAM_WW4END0_2", + "CLBLM_WW4END0" + ], + [ + "BRAM_NE4C3_2", + "CLBLM_NE4C3" + ], + [ + "BRAM_WW4B2_2", + "CLBLM_WW4B2" + ], + [ + "BRAM_EE2BEG2_2", + "CLBLM_EE2BEG2" + ], + [ + "BRAM_ER1BEG0_2", + "CLBLM_ER1BEG0" + ], + [ + "BRAM_SW4A3_2", + "CLBLM_SW4A3" + ], + [ + "BRAM_NW2A1_2", + "CLBLM_NW2A1" + ], + [ + "BRAM_WW2END1_2", + "CLBLM_WW2END1" + ], + [ + "BRAM_NW2A3_2", + "CLBLM_NW2A3" + ], + [ + "BRAM_EL1BEG3_2", + "CLBLM_EL1BEG3" + ], + [ + "BRAM_SW4END2_2", + "CLBLM_SW4END2" + ], + [ + "BRAM_NE4C1_2", + "CLBLM_NE4C1" + ], + [ + "BRAM_WW2END3_2", + "CLBLM_WW2END3" + ], + [ + "BRAM_LH1_2", + "CLBLM_LH1" + ], + [ + "BRAM_SE4C1_2", + "CLBLM_SE4C1" + ], + [ + "BRAM_EE4C2_2", + "CLBLM_EE4C2" + ], + [ + "BRAM_NW4END3_2", + "CLBLM_NW4END3" + ], + [ + "BRAM_SE4BEG0_2", + "CLBLM_SE4BEG0" + ], + [ + "BRAM_SE2A3_2", + "CLBLM_SE2A3" + ], + [ + "BRAM_NW4A1_2", + "CLBLM_NW4A1" + ], + [ + "BRAM_SW2A1_2", + "CLBLM_SW2A1" + ], + [ + "BRAM_ER1BEG3_2", + "CLBLM_ER1BEG3" + ], + [ + "BRAM_EE4B0_2", + "CLBLM_EE4B0" + ], + [ + "BRAM_WW4END1_2", + "CLBLM_WW4END1" + ], + [ + "BRAM_EE4B2_2", + "CLBLM_EE4B2" + ], + [ + "BRAM_EE4BEG3_2", + "CLBLM_EE4BEG3" + ], + [ + "BRAM_WW2END2_2", + "CLBLM_WW2END2" + ], + [ + "BRAM_LH3_2", + "CLBLM_LH3" + ], + [ + "BRAM_LH7_2", + "CLBLM_LH7" + ], + [ + "BRAM_MONITOR_N_2", + "CLBLM_MONITOR_N" + ], + [ + "BRAM_NE4BEG1_2", + "CLBLM_NE4BEG1" + ], + [ + "BRAM_WW4A2_2", + "CLBLM_WW4A2" + ], + [ + "BRAM_EE4A0_2", + "CLBLM_EE4A0" + ], + [ + "BRAM_SE4C2_2", + "CLBLM_SE4C2" + ], + [ + "BRAM_NE4C2_2", + "CLBLM_NE4C2" + ], + [ + "BRAM_EE4A3_2", + "CLBLM_EE4A3" + ], + [ + "BRAM_EE2A3_2", + "CLBLM_EE2A3" + ], + [ + "BRAM_EE4C0_2", + "CLBLM_EE4C0" + ], + [ + "BRAM_NE4C0_2", + "CLBLM_NE4C0" + ], + [ + "BRAM_WW4A3_2", + "CLBLM_WW4A3" + ], + [ + "BRAM_WW4END3_2", + "CLBLM_WW4END3" + ], + [ + "BRAM_EE4B3_2", + "CLBLM_EE4B3" + ], + [ + "BRAM_SW4END0_2", + "CLBLM_SW4END0" + ], + [ + "BRAM_LH9_2", + "CLBLM_LH9" + ], + [ + "BRAM_NW2A2_2", + "CLBLM_NW2A2" + ], + [ + "BRAM_WR1END0_2", + "CLBLM_WR1END0" + ], + [ + "BRAM_EE4C3_2", + "CLBLM_EE4C3" + ], + [ + "BRAM_SW4END1_2", + "CLBLM_SW4END1" + ], + [ + "BRAM_WR1END2_2", + "CLBLM_WR1END2" + ], + [ + "BRAM_LH8_2", + "CLBLM_LH8" + ], + [ + "BRAM_SE4C3_2", + "CLBLM_SE4C3" + ], + [ + "BRAM_SE4C0_2", + "CLBLM_SE4C0" + ], + [ + "BRAM_EE2BEG1_2", + "CLBLM_EE2BEG1" + ], + [ + "BRAM_SW4A1_2", + "CLBLM_SW4A1" + ], + [ + "BRAM_NE4BEG0_2", + "CLBLM_NE4BEG0" + ], + [ + "BRAM_SE2A2_2", + "CLBLM_SE2A2" + ], + [ + "BRAM_WL1END2_2", + "CLBLM_WL1END2" + ], + [ + "BRAM_LH11_2", + "CLBLM_LH11" + ], + [ + "BRAM_WW4A1_2", + "CLBLM_WW4A1" + ], + [ + "BRAM_EL1BEG1_2", + "CLBLM_EL1BEG1" + ], + [ + "BRAM_LH2_2", + "CLBLM_LH2" + ], + [ + "BRAM_WW2A0_2", + "CLBLM_WW2A0" + ], + [ + "BRAM_EE2BEG0_2", + "CLBLM_EE2BEG0" + ], + [ + "BRAM_SW2A3_2", + "CLBLM_SW2A3" + ] + ], + "tile_types": [ + "BRAM_L", + "CLBLM_R" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "HCLK_SS2END_N0_3", + "SS2END3" + ], + [ + "HCLK_NN6C3", + "NN6C3" + ], + [ + "HCLK_SS2A1", + "SS2A1" + ], + [ + "HCLK_FAN_BOUNCE_S3_6", + "FAN_BOUNCE_S3_6" + ], + [ + "HCLK_NN6E0", + "NN6E0" + ], + [ + "HCLK_NN6D3", + "NN6D3" + ], + [ + "HCLK_SW6C0", + "SW6C0" + ], + [ + "HCLK_NE6B2", + "NE6B2" + ], + [ + "HCLK_LEAF_CLK_B_BOT5", + "GCLK_B5" + ], + [ + "HCLK_SE6E2", + "SE6E2" + ], + [ + "HCLK_NN6D1", + "NN6D1" + ], + [ + "HCLK_SS6A1", + "SS6A1" + ], + [ + "HCLK_NE2BEG3", + "NE2BEG3" + ], + [ + "HCLK_SE6C2", + "SE6C2" + ], + [ + "HCLK_SE6E3", + "SE6E3" + ], + [ + "HCLK_SW6C1", + "SW6C1" + ], + [ + "HCLK_SL1END2", + "SL1END2" + ], + [ + "HCLK_NW2END_S0_0", + "NW2END_S0_0" + ], + [ + "HCLK_LV2", + "LV2" + ], + [ + "HCLK_SS6END2", + "SS6END2" + ], + [ + "HCLK_LVB4", + "LVB3" + ], + [ + "HCLK_LEAF_CLK_B_BOT3", + "GCLK_B3" + ], + [ + "HCLK_NN6END_S1_0", + "NN6END_S1_0" + ], + [ + "HCLK_SE6C3", + "SE6C3" + ], + [ + "HCLK_NR1BEG1", + "NR1BEG1" + ], + [ + "HCLK_SE6C0", + "SE6C0" + ], + [ + "HCLK_SS6B1", + "SS6B1" + ], + [ + "HCLK_NE6C0", + "NE6C0" + ], + [ + "HCLK_NE6D3", + "NE6D3" + ], + [ + "HCLK_SW6B2", + "SW6B2" + ], + [ + "HCLK_SW6E1", + "SW6E1" + ], + [ + "HCLK_SS6C0", + "SS6C0" + ], + [ + "HCLK_LV17", + "LV17" + ], + [ + "HCLK_SW6D0", + "SW6D0" + ], + [ + "HCLK_NE6C3", + "NE6C3" + ], + [ + "HCLK_SS6A0", + "SS6A0" + ], + [ + "HCLK_SS6END1", + "SS6END1" + ], + [ + "HCLK_NR1BEG0", + "NR1BEG0" + ], + [ + "HCLK_NN2BEG0", + "NN2BEG0" + ], + [ + "HCLK_NW2A2", + "NW2BEG2" + ], + [ + "HCLK_SW2END0", + "SW2A0" + ], + [ + "HCLK_NN6A3", + "NN6A3" + ], + [ + "HCLK_LVB6", + "LVB5" + ], + [ + "HCLK_LVB7", + "LVB6" + ], + [ + "HCLK_SE6E1", + "SE6E1" + ], + [ + "HCLK_SE6D0", + "SE6D0" + ], + [ + "HCLK_NN2BEG3", + "NN2BEG3" + ], + [ + "HCLK_NW6A0", + "NW6A0" + ], + [ + "HCLK_NR1BEG2", + "NR1BEG2" + ], + [ + "HCLK_NL1BEG1", + "NL1BEG1" + ], + [ + "HCLK_SE6B3", + "SE6B3" + ], + [ + "HCLK_LVB9", + "LVB8" + ], + [ + "HCLK_LV15", + "LV15" + ], + [ + "HCLK_SS6E1", + "SS6E1" + ], + [ + "HCLK_SR1BEG3", + "SR1END3" + ], + [ + "HCLK_SS6C1", + "SS6C1" + ], + [ + "HCLK_LV4", + "LV4" + ], + [ + "HCLK_LVB8", + "LVB7" + ], + [ + "HCLK_SE6B0", + "SE6B0" + ], + [ + "HCLK_SE6D3", + "SE6D3" + ], + [ + "HCLK_NE6A0", + "NE6A0" + ], + [ + "HCLK_NE6D2", + "NE6D2" + ], + [ + "HCLK_SE2A1", + "SE2A1" + ], + [ + "HCLK_SS6C3", + "SS6C3" + ], + [ + "HCLK_NL1BEG0", + "NL1BEG0" + ], + [ + "HCLK_NN2A1", + "NN2A1" + ], + [ + "HCLK_SS6A2", + "SS6A2" + ], + [ + "HCLK_SE2A2", + "SE2A2" + ], + [ + "HCLK_LV6", + "LV6" + ], + [ + "HCLK_NN6A2", + "NN6A2" + ], + [ + "HCLK_NN2A3", + "NN2A3" + ], + [ + "HCLK_WR1END_S1_0", + "WR1END_S1_0" + ], + [ + "HCLK_SE6D1", + "SE6D1" + ], + [ + "HCLK_NN2BEG1", + "NN2BEG1" + ], + [ + "HCLK_NW6C2", + "NW6C2" + ], + [ + "HCLK_LV10", + "LV10" + ], + [ + "HCLK_NW6D3", + "NW6D3" + ], + [ + "HCLK_SR1END2", + "SR1END2" + ], + [ + "HCLK_NN6A0", + "NN6A0" + ], + [ + "HCLK_SS6END0", + "SS6END0" + ], + [ + "HCLK_LV13", + "LV13" + ], + [ + "HCLK_SE6E0", + "SE6E0" + ], + [ + "HCLK_SS6E2", + "SS6E2" + ], + [ + "HCLK_SE2A0", + "SE2A0" + ], + [ + "HCLK_NE6B3", + "NE6B3" + ], + [ + "HCLK_SE6B1", + "SE6B1" + ], + [ + "HCLK_SW6C3", + "SW6C3" + ], + [ + "HCLK_NW6D0", + "NW6D0" + ], + [ + "HCLK_WL1BEG3", + "WL1BEG3" + ], + [ + "HCLK_WL1END3", + "WL1END3" + ], + [ + "HCLK_SS6B0", + "SS6B0" + ], + [ + "HCLK_SS2END0", + "SS2END0" + ], + [ + "HCLK_SW2END_N0_3", + "SW2END3" + ], + [ + "HCLK_NW6A3", + "NW6A3" + ], + [ + "HCLK_SW6B0", + "SW6B0" + ], + [ + "HCLK_SW6E3", + "SW6E3" + ], + [ + "HCLK_SW6B1", + "SW6B1" + ], + [ + "HCLK_NN2A0", + "NN2A0" + ], + [ + "HCLK_NE6B0", + "NE6B0" + ], + [ + "HCLK_NW6C3", + "NW6C3" + ], + [ + "HCLK_ER1BEG_S0", + "ER1BEG_S0" + ], + [ + "HCLK_SW6D3", + "SW6D3" + ], + [ + "HCLK_NN6D0", + "NN6D0" + ], + [ + "HCLK_LV3", + "LV3" + ], + [ + "HCLK_NE2BEG0", + "NE2BEG0" + ], + [ + "HCLK_LV5", + "LV5" + ], + [ + "HCLK_NW6C1", + "NW6C1" + ], + [ + "HCLK_SS2END1", + "SS2END1" + ], + [ + "HCLK_NN6BEG0", + "NN6BEG0" + ], + [ + "HCLK_SS6B2", + "SS6B2" + ], + [ + "HCLK_NN6BEG3", + "NN6BEG3" + ], + [ + "HCLK_NN6C2", + "NN6C2" + ], + [ + "HCLK_SR1END1", + "SR1END1" + ], + [ + "HCLK_NW6B1", + "NW6B1" + ], + [ + "HCLK_ER1END3", + "ER1END3" + ], + [ + "HCLK_SW2END2", + "SW2A2" + ], + [ + "HCLK_SR1END_N3_3", + "SR1END3" + ], + [ + "HCLK_LEAF_CLK_B_BOT2", + "GCLK_B2" + ], + [ + "HCLK_NE6C1", + "NE6C1" + ], + [ + "HCLK_LV11", + "LV11" + ], + [ + "HCLK_EL1END_S3_0", + "EL1END_S3_0" + ], + [ + "HCLK_SE2A3", + "SE2A3" + ], + [ + "HCLK_FAN_BOUNCE_S3_2", + "FAN_BOUNCE_S3_2" + ], + [ + "HCLK_NE6A3", + "NE6A3" + ], + [ + "HCLK_NE6A1", + "NE6A1" + ], + [ + "HCLK_SS6D2", + "SS6D2" + ], + [ + "HCLK_LVB1", + "LVB0" + ], + [ + "HCLK_NW6B3", + "NW6B3" + ], + [ + "HCLK_NN6E1", + "NN6E1" + ], + [ + "HCLK_BYP_BOUNCE6", + "BYP_BOUNCE6" + ], + [ + "HCLK_LVB3", + "LVB2" + ], + [ + "HCLK_LVB11", + "LVB10" + ], + [ + "HCLK_NN2BEG2", + "NN2BEG2" + ], + [ + "HCLK_LV16", + "LV16" + ], + [ + "HCLK_SS6D0", + "SS6D0" + ], + [ + "HCLK_FAN_BOUNCE_S3_4", + "FAN_BOUNCE_S3_4" + ], + [ + "HCLK_WW4END_S0_0", + "WW4END_S0_0" + ], + [ + "HCLK_LV1", + "LV1" + ], + [ + "HCLK_SS6END_N0_3", + "SS6END3" + ], + [ + "HCLK_SW6E0", + "SW6E0" + ], + [ + "HCLK_LEAF_CLK_B_BOT0", + "GCLK_B0" + ], + [ + "HCLK_NN6BEG1", + "NN6BEG1" + ], + [ + "HCLK_NW6B0", + "NW6B0" + ], + [ + "HCLK_NW2A1", + "NW2BEG1" + ], + [ + "HCLK_SL1END1", + "SL1END1" + ], + [ + "HCLK_SS6E0", + "SS6E0" + ], + [ + "HCLK_WR1BEG_S0", + "WR1BEG_S0" + ], + [ + "HCLK_LV0", + "LV0" + ], + [ + "HCLK_SS2BEG3", + "SS2A3" + ], + [ + "HCLK_NE6B1", + "NE6B1" + ], + [ + "HCLK_LVB12", + "LVB11" + ], + [ + "HCLK_NN6C1", + "NN6C1" + ], + [ + "HCLK_LV12", + "LV12" + ], + [ + "HCLK_SS6C2", + "SS6C2" + ], + [ + "HCLK_SW2END1", + "SW2A1" + ], + [ + "HCLK_WW2END3", + "WW2END3" + ], + [ + "HCLK_NN6E2", + "NN6E2" + ], + [ + "HCLK_SS6D3", + "SS6D3" + ], + [ + "HCLK_NW6END_S0_0", + "NW6END_S0_0" + ], + [ + "HCLK_NW6D1", + "NW6D1" + ], + [ + "HCLK_NW2A3", + "NW2BEG3" + ], + [ + "HCLK_SE6B2", + "SE6B2" + ], + [ + "HCLK_LV14", + "LV14" + ], + [ + "HCLK_NE2BEG1", + "NE2BEG1" + ], + [ + "HCLK_NN6D2", + "NN6D2" + ], + [ + "HCLK_LV9", + "LV9" + ], + [ + "HCLK_SS2A3", + "SS2END3" + ], + [ + "HCLK_SW6END3", + "SW6END3" + ], + [ + "HCLK_SW6D1", + "SW6D1" + ], + [ + "HCLK_SW6D2", + "SW6D2" + ], + [ + "HCLK_LVB10", + "LVB9" + ], + [ + "HCLK_NW6B2", + "NW6B2" + ], + [ + "HCLK_SS6B3", + "SS6B3" + ], + [ + "HCLK_LVB5", + "LVB4" + ], + [ + "HCLK_SW6E2", + "SW6E2" + ], + [ + "HCLK_LEAF_CLK_B_BOT1", + "GCLK_B1" + ], + [ + "HCLK_NN6B0", + "NN6B0" + ], + [ + "HCLK_SW6C2", + "SW6C2" + ], + [ + "HCLK_NN6E3", + "NN6E3" + ], + [ + "HCLK_NE6C2", + "NE6C2" + ], + [ + "HCLK_BYP_BOUNCE2", + "BYP_BOUNCE2" + ], + [ + "HCLK_SS2A0", + "SS2A0" + ], + [ + "HCLK_SW6B3", + "SW6B3" + ], + [ + "HCLK_SS2END2", + "SS2END2" + ], + [ + "HCLK_NL1END_S3_0", + "NL1END_S3_0" + ], + [ + "HCLK_NN6BEG2", + "NN6BEG2" + ], + [ + "HCLK_NW6C0", + "NW6C0" + ], + [ + "HCLK_SE6C1", + "SE6C1" + ], + [ + "HCLK_NN6C0", + "NN6C0" + ], + [ + "HCLK_SE6D2", + "SE6D2" + ], + [ + "HCLK_SS6A3", + "SS6A3" + ], + [ + "HCLK_NE6A2", + "NE6A2" + ], + [ + "HCLK_SS2A2", + "SS2A2" + ], + [ + "HCLK_NR1BEG3", + "NR1BEG3" + ], + [ + "HCLK_SW2A3", + "SW2A3" + ], + [ + "HCLK_NN6B1", + "NN6B1" + ], + [ + "HCLK_NE2BEG2", + "NE2BEG2" + ], + [ + "HCLK_NW6A2", + "NW6A2" + ], + [ + "HCLK_NN2END_S2_0", + "NN2END_S2_0" + ], + [ + "HCLK_SS6END3", + "SS6END3" + ], + [ + "HCLK_BYP_BOUNCE7", + "BYP_BOUNCE7" + ], + [ + "HCLK_SL1END3", + "SL1END3" + ], + [ + "HCLK_NE2END_S3_0", + "NE2END_S3_0" + ], + [ + "HCLK_NW6D2", + "NW6D2" + ], + [ + "HCLK_BYP_BOUNCE3", + "BYP_BOUNCE3" + ], + [ + "HCLK_SS6D1", + "SS6D1" + ], + [ + "HCLK_LV8", + "LV8" + ], + [ + "HCLK_FAN_BOUNCE_S3_0", + "FAN_BOUNCE_S3_0" + ], + [ + "HCLK_EL1BEG3", + "EL1BEG3" + ], + [ + "HCLK_LEAF_CLK_B_BOT4", + "GCLK_B4" + ], + [ + "HCLK_NN6A1", + "NN6A1" + ], + [ + "HCLK_LVB2", + "LVB1" + ], + [ + "HCLK_NN6B3", + "NN6B3" + ], + [ + "HCLK_SS6E3", + "SS6E3" + ], + [ + "HCLK_NE6D1", + "NE6D1" + ], + [ + "HCLK_NW2A0", + "NW2BEG0" + ], + [ + "HCLK_NE6D0", + "NE6D0" + ], + [ + "HCLK_NW6A1", + "NW6A1" + ], + [ + "HCLK_SL1END0", + "SL1END0" + ], + [ + "HCLK_NL1BEG2", + "NL1BEG2" + ], + [ + "HCLK_NN6B2", + "NN6B2" + ], + [ + "HCLK_LV7", + "LV7" + ], + [ + "HCLK_NN2A2", + "NN2A2" + ] + ], + "tile_types": [ + "HCLK_R", + "INT_R" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "CMT_TOP_ER1BEG2_12", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WR1END0_12", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4C0_12", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WW4END0_12", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_LH10_12", + "VBRK_LH10" + ], + [ + "CMT_TOP_NE4BEG2_12", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_NW4END3_12", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4BEG3_12", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH1_12", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A1_12", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SE4BEG1_12", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NE4BEG1_12", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_NW4A3_12", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE2BEG3_12", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WL1END2_12", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE2BEG2_12", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW4B2_12", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_SW4END1_12", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG1_12", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4C0_12", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SW2A2_12", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4B0_12", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE4C2_12", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_LH2_12", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4B1_12", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4C3_12", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE4C0_12", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_LH7_12", + "VBRK_LH7" + ], + [ + "CMT_TOP_NE2A0_12", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4A0_12", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WR1END2_12", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW4END1_12", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4BEG3_12", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW2A1_12", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4END2_12", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_SE2A0_12", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW4A1_12", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SE4C1_12", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE2A1_12", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4B1_12", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_EE4C3_12", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4BEG1_12", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_12", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_WR1END3_12", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE2BEG0_12", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EL1BEG2_12", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4A1_12", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW4C2_12", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_LH3_12", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4A2_12", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NE2A3_12", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW2END2_12", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_ER1BEG0_12", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END3_12", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EL1BEG0_12", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_WW2END0_12", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2END1_12", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW2A2_12", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_WL1END3_12", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_EE4BEG2_12", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW4END2_12", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE4C2_12", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4A2_12", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG0_12", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4END3_12", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NW2A2_12", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A3_12", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_SW4A0_12", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_LH11_12", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH4_12", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2A0_12", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SW2A3_12", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4A0_12", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EL1BEG3_12", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE4B3_12", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4A1_12", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_LH5_12", + "VBRK_LH5" + ], + [ + "CMT_TOP_NW2A3_12", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C3_12", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_NE4C2_12", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SW2A1_12", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH9_12", + "VBRK_LH9" + ], + [ + "CMT_TOP_NW2A0_12", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_EE2A3_12", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW2A0_12", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4BEG3_12", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EE4B2_12", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_NW4END1_12", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A1_12", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NE4C3_12", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_ER1BEG1_12", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2A2_12", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WR1END1_12", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A2_12", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2BEG1_12", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SE2A2_12", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_NE4C1_12", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_SW4END0_12", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_LH12_12", + "VBRK_LH12" + ], + [ + "CMT_TOP_WL1END1_12", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_ER1BEG3_12", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4A3_12", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_WW4B3_12", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4C1_12", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2A3_12", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_LH6_12", + "VBRK_LH6" + ], + [ + "CMT_TOP_LH8_12", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A3_12", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_SE2A1_12", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4A2_12", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4B0_12", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_NW4A0_12", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_SW4END2_12", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE2A1_12", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_WW2END3_12", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SE2A3_12", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4C1_12", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SE4BEG2_12", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_NE4BEG0_12", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SW4A2_12", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NE4C0_12", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WL1END0_12", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_WW2A0_12", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END0_12", + "VBRK_NW4END0" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -5 + ], + "wire_pairs": [ + [ + "DSP_PCOUT30", + "HCLK_DSP_PCIN30" + ], + [ + "DSP_PCOUT19", + "HCLK_DSP_PCIN19" + ], + [ + "DSP_BCOUT6", + "HCLK_DSP_BCIN6" + ], + [ + "DSP_PCOUT1", + "HCLK_DSP_PCIN1" + ], + [ + "DSP_ACOUT24", + "HCLK_DSP_ACIN24" + ], + [ + "DSP_ACOUT18", + "HCLK_DSP_ACIN18" + ], + [ + "DSP_PCOUT36", + "HCLK_DSP_PCIN36" + ], + [ + "DSP_BCOUT15", + "HCLK_DSP_BCIN15" + ], + [ + "DSP_BCOUT13", + "HCLK_DSP_BCIN13" + ], + [ + "DSP_BCOUT2", + "HCLK_DSP_BCIN2" + ], + [ + "DSP_ACOUT17", + "HCLK_DSP_ACIN17" + ], + [ + "DSP_ACOUT3", + "HCLK_DSP_ACIN3" + ], + [ + "DSP_PCOUT4", + "HCLK_DSP_PCIN4" + ], + [ + "DSP_PCOUT22", + "HCLK_DSP_PCIN22" + ], + [ + "DSP_PCOUT10", + "HCLK_DSP_PCIN10" + ], + [ + "DSP_ACOUT19", + "HCLK_DSP_ACIN19" + ], + [ + "DSP_PCOUT44", + "HCLK_DSP_PCIN44" + ], + [ + "DSP_PCOUT13", + "HCLK_DSP_PCIN13" + ], + [ + "DSP_ACOUT23", + "HCLK_DSP_ACIN23" + ], + [ + "DSP_PCOUT37", + "HCLK_DSP_PCIN37" + ], + [ + "DSP_PCOUT8", + "HCLK_DSP_PCIN8" + ], + [ + "DSP_ACOUT21", + "HCLK_DSP_ACIN21" + ], + [ + "DSP_PCOUT14", + "HCLK_DSP_PCIN14" + ], + [ + "DSP_ACOUT29", + "HCLK_DSP_ACIN29" + ], + [ + "DSP_ACOUT1", + "HCLK_DSP_ACIN1" + ], + [ + "DSP_PCOUT7", + "HCLK_DSP_PCIN7" + ], + [ + "DSP_ACOUT12", + "HCLK_DSP_ACIN12" + ], + [ + "DSP_PCOUT21", + "HCLK_DSP_PCIN21" + ], + [ + "DSP_PCOUT45", + "HCLK_DSP_PCIN45" + ], + [ + "DSP_PCOUT11", + "HCLK_DSP_PCIN11" + ], + [ + "DSP_BCOUT10", + "HCLK_DSP_BCIN10" + ], + [ + "DSP_BCOUT16", + "HCLK_DSP_BCIN16" + ], + [ + "DSP_PCOUT35", + "HCLK_DSP_PCIN35" + ], + [ + "DSP_PCOUT29", + "HCLK_DSP_PCIN29" + ], + [ + "DSP_BCOUT4", + "HCLK_DSP_BCIN4" + ], + [ + "DSP_ACOUT6", + "HCLK_DSP_ACIN6" + ], + [ + "DSP_ACOUT16", + "HCLK_DSP_ACIN16" + ], + [ + "DSP_ACOUT11", + "HCLK_DSP_ACIN11" + ], + [ + "DSP_ACOUT20", + "HCLK_DSP_ACIN20" + ], + [ + "DSP_ACOUT8", + "HCLK_DSP_ACIN8" + ], + [ + "DSP_BCOUT11", + "HCLK_DSP_BCIN11" + ], + [ + "DSP_PCOUT38", + "HCLK_DSP_PCIN38" + ], + [ + "DSP_PCOUT42", + "HCLK_DSP_PCIN42" + ], + [ + "DSP_PCOUT47", + "HCLK_DSP_PCIN47" + ], + [ + "DSP_ACOUT26", + "HCLK_DSP_ACIN26" + ], + [ + "DSP_ACOUT14", + "HCLK_DSP_ACIN14" + ], + [ + "DSP_ACOUT15", + "HCLK_DSP_ACIN15" + ], + [ + "DSP_BCOUT0", + "HCLK_DSP_BCIN0" + ], + [ + "DSP_PCOUT26", + "HCLK_DSP_PCIN26" + ], + [ + "DSP_PCOUT0", + "HCLK_DSP_PCIN0" + ], + [ + "DSP_BCOUT9", + "HCLK_DSP_BCIN9" + ], + [ + "DSP_BCOUT7", + "HCLK_DSP_BCIN7" + ], + [ + "DSP_PCOUT32", + "HCLK_DSP_PCIN32" + ], + [ + "DSP_PCOUT25", + "HCLK_DSP_PCIN25" + ], + [ + "DSP_ACOUT4", + "HCLK_DSP_ACIN4" + ], + [ + "DSP_PCOUT16", + "HCLK_DSP_PCIN16" + ], + [ + "DSP_ACOUT22", + "HCLK_DSP_ACIN22" + ], + [ + "DSP_BCOUT12", + "HCLK_DSP_BCIN12" + ], + [ + "DSP_ACOUT28", + "HCLK_DSP_ACIN28" + ], + [ + "DSP_ACOUT27", + "HCLK_DSP_ACIN27" + ], + [ + "DSP_PCOUT3", + "HCLK_DSP_PCIN3" + ], + [ + "DSP_PCOUT2", + "HCLK_DSP_PCIN2" + ], + [ + "DSP_PCOUT15", + "HCLK_DSP_PCIN15" + ], + [ + "DSP_PCOUT33", + "HCLK_DSP_PCIN33" + ], + [ + "DSP_PCOUT43", + "HCLK_DSP_PCIN43" + ], + [ + "DSP_PCOUT28", + "HCLK_DSP_PCIN28" + ], + [ + "DSP_CARRYCASCOUT", + "HCLK_DSP_CARRYCASCIN" + ], + [ + "DSP_BCOUT1", + "HCLK_DSP_BCIN1" + ], + [ + "DSP_BCOUT5", + "HCLK_DSP_BCIN5" + ], + [ + "DSP_ACOUT2", + "HCLK_DSP_ACIN2" + ], + [ + "DSP_ACOUT25", + "HCLK_DSP_ACIN25" + ], + [ + "DSP_PCOUT24", + "HCLK_DSP_PCIN24" + ], + [ + "DSP_BCOUT8", + "HCLK_DSP_BCIN8" + ], + [ + "DSP_PCOUT9", + "HCLK_DSP_PCIN9" + ], + [ + "DSP_PCOUT31", + "HCLK_DSP_PCIN31" + ], + [ + "DSP_ACOUT9", + "HCLK_DSP_ACIN9" + ], + [ + "DSP_PCOUT40", + "HCLK_DSP_PCIN40" + ], + [ + "DSP_PCOUT27", + "HCLK_DSP_PCIN27" + ], + [ + "DSP_PCOUT12", + "HCLK_DSP_PCIN12" + ], + [ + "DSP_ACOUT10", + "HCLK_DSP_ACIN10" + ], + [ + "DSP_ACOUT0", + "HCLK_DSP_ACIN0" + ], + [ + "DSP_PCOUT5", + "HCLK_DSP_PCIN5" + ], + [ + "DSP_PCOUT18", + "HCLK_DSP_PCIN18" + ], + [ + "DSP_PCOUT6", + "HCLK_DSP_PCIN6" + ], + [ + "DSP_ACOUT7", + "HCLK_DSP_ACIN7" + ], + [ + "DSP_PCOUT39", + "HCLK_DSP_PCIN39" + ], + [ + "DSP_PCOUT41", + "HCLK_DSP_PCIN41" + ], + [ + "DSP_BCOUT3", + "HCLK_DSP_BCIN3" + ], + [ + "DSP_PCOUT34", + "HCLK_DSP_PCIN34" + ], + [ + "DSP_PCOUT20", + "HCLK_DSP_PCIN20" + ], + [ + "DSP_ACOUT5", + "HCLK_DSP_ACIN5" + ], + [ + "DSP_MULTSIGNOUT", + "HCLK_DSP_MULTSIGNIN" + ], + [ + "DSP_BCOUT14", + "HCLK_DSP_BCIN14" + ], + [ + "DSP_PCOUT46", + "HCLK_DSP_PCIN46" + ], + [ + "DSP_ACOUT13", + "HCLK_DSP_ACIN13" + ], + [ + "DSP_BCOUT17", + "HCLK_DSP_BCIN17" + ], + [ + "DSP_PCOUT17", + "HCLK_DSP_PCIN17" + ], + [ + "DSP_PCOUT23", + "HCLK_DSP_PCIN23" + ] + ], + "tile_types": [ + "DSP_R", + "HCLK_DSP_R" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_1" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_1" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_1" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_1" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_1" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_1" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_1" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_1" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_1" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_1" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_1" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_1" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_1" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_1" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_1" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_1" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_1" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_1" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_1" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_1" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_1" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_1" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_1" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_1" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_1" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_1" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_1" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_1" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_1" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_1" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_1" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_1" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_1" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_1" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_1" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_1" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_1" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_1" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_1" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_1" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_1" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_1" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_1" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_1" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_1" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_1" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_1" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_1" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_1" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_1" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_1" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_1" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_1" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_1" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_1" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_1" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_1" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_1" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_1" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_1" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_1" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_1" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_1" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_1" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_1" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_1" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_1" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_1" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_1" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_1" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_1" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_1" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_1" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_1" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_1" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_1" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_1" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_1" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_1" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_1" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_1" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_1" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_1" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_1" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_1" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_1" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_1" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_1" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_1" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_1" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_1" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_1" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_1" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_1" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_1" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_1" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_1" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_1" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_1" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_1" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_1" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_1" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_1" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_1" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_1" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_1" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_1" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_1" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_1" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_1" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_1" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_1" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_1" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_1" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_1" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_1" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_1" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_1" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_1" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_1" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_MID_FUJI2" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLK_PMV_IMUX25_0", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_PMV_IMUX14_0", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_PMV_IMUX6_0", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_PMV_IMUX46_0", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_PMV_IMUX34_0", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_FEED_WW4B1", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_PMV_IMUX7_0", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_PMV_IMUX28_0", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_PMV_IMUX11_0", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_FEED_WL1END2", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_FEED_EE4BEG2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_FEED_LH8", + "INT_INTERFACE_LH8" + ], + [ + "CLK_PMV_IMUX8_0", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_FEED_WW4C1", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_PMV_IMUX37_0", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_PMV_IMUX19_0", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_FEED_WR1END3", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_FEED_EE4B3", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_PMV_IMUX3_0", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_PMV_FAN0_0", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_FEED_NE2A2", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_PMV_IMUX10_0", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_FEED_WL1END0", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_FEED_NE2A1", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_FEED_WW4C2", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_PMV_IMUX45_0", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_FEED_NW2A2", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_FEED_WW2A0", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_FEED_WR1END1", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_PMV_IMUX18_0", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_FEED_SE4BEG2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_PMV_BYP1_0", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_PMV_IMUX39_0", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_FEED_NW2A1", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_FEED_EE4A2", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_PMV_FAN7_0", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_PMV_IMUX17_0", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_FEED_NW2A0", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_PMV_IMUX29_0", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_FEED_WW4B2", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_FEED_WL1END1", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_PMV_IMUX35_0", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_FEED_NE2A0", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_FEED_WW4C0", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_FEED_WW4END0", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_FEED_EE4C1", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_FEED_EE4C0", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_FEED_EE4BEG0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_FEED_LH11", + "INT_INTERFACE_LH11" + ], + [ + "CLK_PMV_IMUX27_0", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_PMV_IMUX22_0", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_PMV_BYP4_0", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_FEED_WW4END2", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_FEED_SE4BEG1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_FEED_NW4A3", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_PMV_IMUX1_0", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_FEED_EE2BEG3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_PMV_LOGIC_OUTS16_0", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CLK_FEED_SE2A2", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_FEED_EE2BEG2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_FEED_NW4A0", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_PMV_FAN5_0", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_FEED_LH5", + "INT_INTERFACE_LH5" + ], + [ + "CLK_FEED_WW2A1", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_PMV_IMUX40_0", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_FEED_WW4C3", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_FEED_WW4A2", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_FEED_SW4END1", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_FEED_EE2A2", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_PMV_BYP2_0", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_PMV_LOGIC_OUTS6_0", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CLK_FEED_NW4END2", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_PMV_IMUX38_0", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_FEED_SW4END2", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_PMV_BYP7_0", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_PMV_BYP5_0", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_FEED_ER1BEG1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_FEED_EE4BEG3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_FEED_WW4A0", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_FEED_NE4C2", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_PMV_IMUX21_0", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_FEED_EE2A0", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_PMV_IMUX26_0", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_FEED_NE4C1", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_PMV_BYP6_0", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_FEED_SE4C2", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_FEED_SE2A1", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_PMV_IMUX43_0", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_FEED_SE4C0", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_FEED_LH1", + "INT_INTERFACE_LH1" + ], + [ + "CLK_FEED_NE4BEG3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_PMV_CTRL0_0", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_FEED_WW2END2", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_FEED_EE4B2", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_FEED_MONITOR_P", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_FEED_WW2END0", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_PMV_FAN1_0", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_FEED_EE4B1", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_PMV_LOGIC_OUTS10_0", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CLK_FEED_NE2A3", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_PMV_IMUX0_0", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_PMV_IMUX9_0", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_FEED_MONITOR_N", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_PMV_BYP3_0", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_FEED_WW4B0", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_FEED_SW4A1", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_FEED_SE2A3", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_FEED_WW4END1", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_PMV_IMUX30_0", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_FEED_ER1BEG2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_FEED_WR1END2", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_FEED_WR1END0", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_FEED_EE2A3", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_FEED_NE4C0", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_FEED_SE4C3", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_FEED_LH9", + "INT_INTERFACE_LH9" + ], + [ + "CLK_FEED_WW4A1", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_FEED_LH3", + "INT_INTERFACE_LH3" + ], + [ + "CLK_FEED_EL1BEG3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_FEED_EE4A0", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_PMV_IMUX23_0", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_PMV_IMUX31_0", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_FEED_SW4A3", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_FEED_NW2A3", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_PMV_IMUX20_0", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_FEED_SW4END3", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_FEED_WL1END3", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_PMV_IMUX47_0", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_PMV_LOGIC_OUTS14_0", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "CLK_FEED_SE2A0", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_PMV_IMUX24_0", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_PMV_FAN3_0", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_FEED_NW4END3", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_FEED_EE2A1", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_FEED_SW4END0", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_FEED_EL1BEG2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_FEED_LH2", + "INT_INTERFACE_LH2" + ], + [ + "CLK_FEED_EE2BEG1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_PMV_IMUX15_0", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_FEED_SW2A2", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_FEED_EE4B0", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_FEED_LH6", + "INT_INTERFACE_LH6" + ], + [ + "CLK_FEED_SW2A1", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_PMV_IMUX41_0", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_FEED_SW2A0", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_FEED_EE4A3", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_FEED_EE4A1", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_FEED_EE4BEG1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_FEED_ER1BEG0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_FEED_NE4BEG1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_PMV_CLK0_0", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_PMV_FAN2_0", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_PMV_FAN4_0", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_FEED_EL1BEG0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_PMV_IMUX13_0", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_FEED_WW2END1", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_FEED_NE4BEG2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_FEED_WW4A3", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_FEED_EE2BEG0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_PMV_CLK1_0", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_PMV_LOGIC_OUTS19_0", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CLK_FEED_WW4END3", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_PMV_IMUX2_0", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_PMV_FAN6_0", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_FEED_NE4BEG0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_FEED_SW4A2", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_PMV_IMUX12_0", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_FEED_WW4B3", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_FEED_NE4C3", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_PMV_IMUX5_0", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_PMV_IMUX32_0", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_PMV_LOGIC_OUTS5_0", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CLK_PMV_IMUX42_0", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_FEED_LH12", + "INT_INTERFACE_LH12" + ], + [ + "CLK_FEED_SE4BEG0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_PMV_LOGIC_OUTS9_0", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CLK_FEED_ER1BEG3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_PMV_CTRL1_0", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_PMV_IMUX36_0", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_PMV_IMUX16_0", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_PMV_BYP0_0", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_FEED_NW4END0", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_PMV_LOGIC_OUTS2_0", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CLK_FEED_LH4", + "INT_INTERFACE_LH4" + ], + [ + "CLK_FEED_EE4C3", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_FEED_SW2A3", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_FEED_EL1BEG1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_FEED_SW4A0", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_FEED_LH10", + "INT_INTERFACE_LH10" + ], + [ + "CLK_FEED_NW4END1", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_PMV_IMUX33_0", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_FEED_WW2A3", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_PMV_IMUX44_0", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_FEED_NW4A2", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_FEED_WW2END3", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_FEED_LH7", + "INT_INTERFACE_LH7" + ], + [ + "CLK_FEED_EE4C2", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_FEED_SE4C1", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_FEED_NW4A1", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_FEED_WW2A2", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_PMV_IMUX4_0", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_FEED_SE4BEG3", + "INT_INTERFACE_SE4BEG3" + ] + ], + "tile_types": [ + "CLK_MTBF2", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "BRKH_CLK_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "BRKH_CLK_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "BRKH_CLK_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "BRKH_CLK_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "BRKH_CLK_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "BRKH_CLK_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ], + [ + "BRKH_CLK_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "BRKH_CLK_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "BRKH_CLK_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "BRKH_CLK_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "BRKH_CLK_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "BRKH_CLK_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "BRKH_CLK_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "BRKH_CLK_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "BRKH_CLK_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "BRKH_CLK_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "BRKH_CLK_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "BRKH_CLK_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "BRKH_CLK_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "BRKH_CLK_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "BRKH_CLK_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "BRKH_CLK_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "BRKH_CLK_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "BRKH_CLK_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "BRKH_CLK_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "BRKH_CLK_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "BRKH_CLK_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "BRKH_CLK_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "BRKH_CLK_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "BRKH_CLK_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "BRKH_CLK_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "BRKH_CLK_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "BRKH_CLK_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ] + ], + "tile_types": [ + "BRKH_CLK", + "CLK_FEED" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "MONITOR_EE2A1_0", + "VFRAME_EE2A1" + ], + [ + "MONITOR_IMUX27_0", + "VFRAME_IMUX27" + ], + [ + "MONITOR_ER1BEG2_0", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_NW4END0_0", + "VFRAME_NW4END0" + ], + [ + "MONITOR_EE4A3_0", + "VFRAME_EE4A3" + ], + [ + "MONITOR_IMUX11_0", + "VFRAME_IMUX11" + ], + [ + "MONITOR_BYP1_0", + "VFRAME_BYP1" + ], + [ + "MONITOR_FAN3_0", + "VFRAME_FAN3" + ], + [ + "MONITOR_LH2_0", + "VFRAME_LH2" + ], + [ + "MONITOR_SW2A0_0", + "VFRAME_SW2A0" + ], + [ + "MONITOR_LH10_0", + "VFRAME_LH10" + ], + [ + "MONITOR_IMUX26_0", + "VFRAME_IMUX26" + ], + [ + "MONITOR_IMUX9_0", + "VFRAME_IMUX9" + ], + [ + "MONITOR_SW2A2_0", + "VFRAME_SW2A2" + ], + [ + "MONITOR_IMUX8_0", + "VFRAME_IMUX8" + ], + [ + "MONITOR_EE4BEG2_0", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_WW2END0_0", + "VFRAME_WW2END0" + ], + [ + "MONITOR_FAN6_0", + "VFRAME_FAN6" + ], + [ + "MONITOR_SW2A1_0", + "VFRAME_SW2A1" + ], + [ + "MONITOR_SW4A1_0", + "VFRAME_SW4A1" + ], + [ + "MONITOR_EE4BEG3_0", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_IMUX44_0", + "VFRAME_IMUX44" + ], + [ + "MONITOR_IMUX22_0", + "VFRAME_IMUX22" + ], + [ + "MONITOR_WW4A3_0", + "VFRAME_WW4A3" + ], + [ + "MONITOR_FAN2_0", + "VFRAME_FAN2" + ], + [ + "MONITOR_NW2A3_0", + "VFRAME_NW2A3" + ], + [ + "MONITOR_IMUX46_0", + "VFRAME_IMUX46" + ], + [ + "MONITOR_SW4END1_0", + "VFRAME_SW4END1" + ], + [ + "MONITOR_NE4BEG1_0", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_SE4BEG0_0", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_IMUX41_0", + "VFRAME_IMUX41" + ], + [ + "MONITOR_SW4END0_0", + "VFRAME_SW4END0" + ], + [ + "MONITOR_IMUX2_0", + "VFRAME_IMUX2" + ], + [ + "MONITOR_SW4END2_0", + "VFRAME_SW4END2" + ], + [ + "MONITOR_SE4BEG1_0", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_EE4C1_0", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX15_0", + "VFRAME_IMUX15" + ], + [ + "MONITOR_NE2A0_0", + "VFRAME_NE2A0" + ], + [ + "MONITOR_ER1BEG0_0", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_IMUX36_0", + "VFRAME_IMUX36" + ], + [ + "MONITOR_WW4B1_0", + "VFRAME_WW4B1" + ], + [ + "MONITOR_NW4END1_0", + "VFRAME_NW4END1" + ], + [ + "MONITOR_EE4A0_0", + "VFRAME_EE4A0" + ], + [ + "MONITOR_LH1_0", + "VFRAME_LH1" + ], + [ + "MONITOR_SE4C2_0", + "VFRAME_SE4C2" + ], + [ + "MONITOR_LH6_0", + "VFRAME_LH6" + ], + [ + "MONITOR_IMUX10_0", + "VFRAME_IMUX10" + ], + [ + "MONITOR_IMUX23_0", + "VFRAME_IMUX23" + ], + [ + "MONITOR_SE4C3_0", + "VFRAME_SE4C3" + ], + [ + "MONITOR_SW4END3_0", + "VFRAME_SW4END3" + ], + [ + "MONITOR_EE4A2_0", + "VFRAME_EE4A2" + ], + [ + "MONITOR_IMUX5_0", + "VFRAME_IMUX5" + ], + [ + "MONITOR_NE4BEG3_0", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_IMUX35_0", + "VFRAME_IMUX35" + ], + [ + "MONITOR_CLK0_0", + "VFRAME_CLK0" + ], + [ + "MONITOR_IMUX21_0", + "VFRAME_IMUX21" + ], + [ + "MONITOR_NE4C1_0", + "VFRAME_NE4C1" + ], + [ + "MONITOR_IMUX14_0", + "VFRAME_IMUX14" + ], + [ + "MONITOR_LH12_0", + "VFRAME_LH12" + ], + [ + "MONITOR_WW2A1_0", + "VFRAME_WW2A1" + ], + [ + "MONITOR_IMUX34_0", + "VFRAME_IMUX34" + ], + [ + "MONITOR_EE2A2_0", + "VFRAME_EE2A2" + ], + [ + "MONITOR_EE2BEG2_0", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_WL1END3_0", + "VFRAME_WL1END3" + ], + [ + "MONITOR_IMUX45_0", + "VFRAME_IMUX45" + ], + [ + "MONITOR_IMUX0_0", + "VFRAME_IMUX0" + ], + [ + "MONITOR_WW2END1_0", + "VFRAME_WW2END1" + ], + [ + "MONITOR_IMUX40_0", + "VFRAME_IMUX40" + ], + [ + "MONITOR_ER1BEG1_0", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_IMUX6_0", + "VFRAME_IMUX6" + ], + [ + "MONITOR_EE4C2_0", + "VFRAME_EE4C2" + ], + [ + "MONITOR_WW4END1_0", + "VFRAME_WW4END1" + ], + [ + "MONITOR_NW4A2_0", + "VFRAME_NW4A2" + ], + [ + "MONITOR_FAN0_0", + "VFRAME_FAN0" + ], + [ + "MONITOR_WW4C0_0", + "VFRAME_WW4C0" + ], + [ + "MONITOR_IMUX13_0", + "VFRAME_IMUX13" + ], + [ + "MONITOR_WW4C2_0", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE2A3_0", + "VFRAME_EE2A3" + ], + [ + "MONITOR_IMUX29_0", + "VFRAME_IMUX29" + ], + [ + "MONITOR_WW2A0_0", + "VFRAME_WW2A0" + ], + [ + "MONITOR_ER1BEG3_0", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_EE4A1_0", + "VFRAME_EE4A1" + ], + [ + "MONITOR_BYP3_0", + "VFRAME_BYP3" + ], + [ + "MONITOR_EE4BEG1_0", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_SW4A2_0", + "VFRAME_SW4A2" + ], + [ + "MONITOR_IMUX43_0", + "VFRAME_IMUX43" + ], + [ + "MONITOR_IMUX24_0", + "VFRAME_IMUX24" + ], + [ + "MONITOR_CTRL1_0", + "VFRAME_CTRL1" + ], + [ + "MONITOR_IMUX28_0", + "VFRAME_IMUX28" + ], + [ + "MONITOR_FAN5_0", + "VFRAME_FAN5" + ], + [ + "MONITOR_SE2A0_0", + "VFRAME_SE2A0" + ], + [ + "MONITOR_IMUX31_0", + "VFRAME_IMUX31" + ], + [ + "MONITOR_WW4B3_0", + "VFRAME_WW4B3" + ], + [ + "MONITOR_WW2A2_0", + "VFRAME_WW2A2" + ], + [ + "MONITOR_FAN7_0", + "VFRAME_FAN7" + ], + [ + "MONITOR_IMUX19_0", + "VFRAME_IMUX19" + ], + [ + "MONITOR_EE2BEG1_0", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_EE4C3_0", + "VFRAME_EE4C3" + ], + [ + "MONITOR_FAN4_0", + "VFRAME_FAN4" + ], + [ + "MONITOR_SE2A2_0", + "VFRAME_SE2A2" + ], + [ + "MONITOR_IMUX47_0", + "VFRAME_IMUX47" + ], + [ + "MONITOR_NE4C3_0", + "VFRAME_NE4C3" + ], + [ + "MONITOR_IMUX17_0", + "VFRAME_IMUX17" + ], + [ + "MONITOR_WL1END1_0", + "VFRAME_WL1END1" + ], + [ + "MONITOR_IMUX37_0", + "VFRAME_IMUX37" + ], + [ + "MONITOR_IMUX30_0", + "VFRAME_IMUX30" + ], + [ + "MONITOR_SW4A0_0", + "VFRAME_SW4A0" + ], + [ + "MONITOR_EE2BEG3_0", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_IMUX33_0", + "VFRAME_IMUX33" + ], + [ + "MONITOR_NW2A0_0", + "VFRAME_NW2A0" + ], + [ + "MONITOR_EE4BEG0_0", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_NW4A3_0", + "VFRAME_NW4A3" + ], + [ + "MONITOR_WR1END2_0", + "VFRAME_WR1END2" + ], + [ + "MONITOR_WW4END0_0", + "VFRAME_WW4END0" + ], + [ + "MONITOR_SW2A3_0", + "VFRAME_SW2A3" + ], + [ + "MONITOR_NW4END2_0", + "VFRAME_NW4END2" + ], + [ + "MONITOR_WW2A3_0", + "VFRAME_WW2A3" + ], + [ + "MONITOR_LH3_0", + "VFRAME_LH3" + ], + [ + "MONITOR_IMUX3_0", + "VFRAME_IMUX3" + ], + [ + "MONITOR_EL1BEG0_0", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_EE4C0_0", + "VFRAME_EE4C0" + ], + [ + "MONITOR_NE4BEG2_0", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_BYP0_0", + "VFRAME_BYP0" + ], + [ + "MONITOR_WW4A0_0", + "VFRAME_WW4A0" + ], + [ + "MONITOR_NE4C2_0", + "VFRAME_NE4C2" + ], + [ + "MONITOR_NE4BEG0_0", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_SE4BEG3_0", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_NE4C0_0", + "VFRAME_NE4C0" + ], + [ + "MONITOR_NW2A1_0", + "VFRAME_NW2A1" + ], + [ + "MONITOR_SE4C1_0", + "VFRAME_SE4C1" + ], + [ + "MONITOR_IMUX32_0", + "VFRAME_IMUX32" + ], + [ + "MONITOR_EE4B1_0", + "VFRAME_EE4B1" + ], + [ + "MONITOR_BYP7_0", + "VFRAME_BYP7" + ], + [ + "MONITOR_IMUX7_0", + "VFRAME_IMUX7" + ], + [ + "MONITOR_IMUX18_0", + "VFRAME_IMUX18" + ], + [ + "MONITOR_NW2A2_0", + "VFRAME_NW2A2" + ], + [ + "MONITOR_BYP4_0", + "VFRAME_BYP4" + ], + [ + "MONITOR_IMUX25_0", + "VFRAME_IMUX25" + ], + [ + "MONITOR_WW4B0_0", + "VFRAME_WW4B0" + ], + [ + "MONITOR_NE2A1_0", + "VFRAME_NE2A1" + ], + [ + "MONITOR_WW4C3_0", + "VFRAME_WW4C3" + ], + [ + "MONITOR_IMUX4_0", + "VFRAME_IMUX4" + ], + [ + "MONITOR_EE4B3_0", + "VFRAME_EE4B3" + ], + [ + "MONITOR_LH7_0", + "VFRAME_LH7" + ], + [ + "MONITOR_SE4BEG2_0", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_IMUX1_0", + "VFRAME_IMUX1" + ], + [ + "MONITOR_NW4A0_0", + "VFRAME_NW4A0" + ], + [ + "MONITOR_LH9_0", + "VFRAME_LH9" + ], + [ + "MONITOR_WL1END2_0", + "VFRAME_WL1END2" + ], + [ + "MONITOR_BYP5_0", + "VFRAME_BYP5" + ], + [ + "MONITOR_IMUX20_0", + "VFRAME_IMUX20" + ], + [ + "MONITOR_SE2A1_0", + "VFRAME_SE2A1" + ], + [ + "MONITOR_EE4B0_0", + "VFRAME_EE4B0" + ], + [ + "MONITOR_NE2A3_0", + "VFRAME_NE2A3" + ], + [ + "MONITOR_LH5_0", + "VFRAME_LH5" + ], + [ + "MONITOR_NE2A2_0", + "VFRAME_NE2A2" + ], + [ + "MONITOR_IMUX39_0", + "VFRAME_IMUX39" + ], + [ + "MONITOR_WW4A1_0", + "VFRAME_WW4A1" + ], + [ + "MONITOR_IMUX42_0", + "VFRAME_IMUX42" + ], + [ + "MONITOR_EE2BEG0_0", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_BYP6_0", + "VFRAME_BYP6" + ], + [ + "MONITOR_SW4A3_0", + "VFRAME_SW4A3" + ], + [ + "MONITOR_NW4A1_0", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WR1END3_0", + "VFRAME_WR1END3" + ], + [ + "MONITOR_EL1BEG3_0", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_WW4C1_0", + "VFRAME_WW4C1" + ], + [ + "MONITOR_IMUX12_0", + "VFRAME_IMUX12" + ], + [ + "MONITOR_WR1END1_0", + "VFRAME_WR1END1" + ], + [ + "MONITOR_IMUX38_0", + "VFRAME_IMUX38" + ], + [ + "MONITOR_SE2A3_0", + "VFRAME_SE2A3" + ], + [ + "MONITOR_LH4_0", + "VFRAME_LH4" + ], + [ + "MONITOR_FAN1_0", + "VFRAME_FAN1" + ], + [ + "MONITOR_NW4END3_0", + "VFRAME_NW4END3" + ], + [ + "MONITOR_EE4B2_0", + "VFRAME_EE4B2" + ], + [ + "MONITOR_BYP2_0", + "VFRAME_BYP2" + ], + [ + "MONITOR_LH11_0", + "VFRAME_LH11" + ], + [ + "MONITOR_CLK1_0", + "VFRAME_CLK1" + ], + [ + "MONITOR_CTRL0_0", + "VFRAME_CTRL0" + ], + [ + "MONITOR_LH8_0", + "VFRAME_LH8" + ], + [ + "MONITOR_WW4A2_0", + "VFRAME_WW4A2" + ], + [ + "MONITOR_WW4END3_0", + "VFRAME_WW4END3" + ], + [ + "MONITOR_EL1BEG1_0", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_WL1END0_0", + "VFRAME_WL1END0" + ], + [ + "MONITOR_SE4C0_0", + "VFRAME_SE4C0" + ], + [ + "MONITOR_WW4END2_0", + "VFRAME_WW4END2" + ], + [ + "MONITOR_IMUX16_0", + "VFRAME_IMUX16" + ], + [ + "MONITOR_WW2END3_0", + "VFRAME_WW2END3" + ], + [ + "MONITOR_WR1END0_0", + "VFRAME_WR1END0" + ], + [ + "MONITOR_EL1BEG2_0", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_WW2END2_0", + "VFRAME_WW2END2" + ], + [ + "MONITOR_WW4B2_0", + "VFRAME_WW4B2" + ], + [ + "MONITOR_EE2A0_0", + "VFRAME_EE2A0" + ] + ], + "tile_types": [ + "MONITOR_TOP_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SW4END0_11", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_SE4C1_11", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_EE4C2_11", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_WW4A3_11", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_EL1BEG0_11", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_WW2A0_11", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_NE2A3_11", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_WW4A2_11", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EL1BEG1_11", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW2END1_11", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_NW2A2_11", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_WW4A1_11", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_NW4A0_11", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SE4BEG0_11", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_NW4END0_11", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SE2A2_11", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4BEG0_11", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE4BEG2_11", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SW4A3_11", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_LH7_11", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_SW4END3_11", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_ER1BEG1_11", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_EE4C1_11", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE4B0_11", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WR1END3_11", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE4BEG3_11", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_NE4C3_11", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_NE4BEG3_11", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_SE4BEG3_11", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_WW4C3_11", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE2BEG1_11", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_WW2END3_11", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_WW4C1_11", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_NE4BEG2_11", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_LH1_11", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_EE2A2_11", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_SE4C3_11", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_LH3_11", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SW4END1_11", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_WR1END0_11", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_NE4BEG1_11", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_LH9_11", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_EE4BEG1_11", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_LH8_11", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_EE2A0_11", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_SE2A0_11", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_WL1END1_11", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_LH10_11", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_EE4A2_11", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_WW2A2_11", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4C1_11", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE4BEG0_11", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_EE2BEG3_11", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_WW4B3_11", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_WR1END2_11", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_EE2A3_11", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW2END0_11", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NE2A2_11", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_SE2A3_11", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_NE4C2_11", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_SW2A0_11", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WW2END2_11", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SW2A2_11", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WW4B0_11", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_EE4A0_11", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_WL1END0_11", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_NE2A1_11", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NW2A0_11", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_LH6_11", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WW4B1_11", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_SE4BEG1_11", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_WW4END1_11", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_LH2_11", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_ER1BEG3_11", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_NE2A0_11", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_ER1BEG0_11", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_WW4C2_11", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NW4A3_11", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WW2A1_11", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WW4END0_11", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EE4B1_11", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_WW2A3_11", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_EE2A1_11", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_SW2A1_11", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4A1_11", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NE4C0_11", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_LH12_11", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_SE2A1_11", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_NW4END3_11", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_NW2A1_11", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SW4A0_11", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_LH5_11", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE4C0_11", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EL1BEG2_11", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_EE4C3_11", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_SE4C0_11", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_SW4END2_11", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_EE2BEG2_11", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW4A0_11", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_WW4END2_11", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_SW4A2_11", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_LH4_11", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_LH11_11", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WL1END3_11", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_ER1BEG2_11", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_WL1END2_11", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_NW2A3_11", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_WW4B2_11", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE4B3_11", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_EE2BEG0_11", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WR1END1_11", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SE4C2_11", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_NW4A2_11", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NW4END2_11", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4END3_11", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4C0_11", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_SW4A1_11", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NW4A1_11", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SW2A3_11", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_EE4B2_11", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_NW4END1_11", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_SE4BEG2_11", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG3_11", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_EE4A3_11", + "INT_FEEDTHRU_2_EE4A3" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 5, + 0 + ], + "wire_pairs": [ + [ + "PCIE_EL1BEG1_10", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_SW4END3_10", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_WW2A2_10", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_SE4C1_10", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_IMUX24_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_IMUX18_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_NE4C3_10", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_IMUX32_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_SW2A2_10", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_IMUX15_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_BYP3_L_10", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_SE4BEG3_10", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_IMUX42_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_BYP5_L_10", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_BYP6_L_10", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_SE2A0_10", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_IMUX20_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_BYP7_L_10", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_WW2A3_10", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_WL1END0_10", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_NW2A1_10", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_SW4A1_10", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_EE4A2_10", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_WW2A0_10", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_IMUX31_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_NE2A0_10", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_IMUX35_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_SE4BEG2_10", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_WW2A1_10", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_EE4C1_10", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_EE4BEG1_10", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_IMUX11_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_NW2A2_10", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_WW4END1_10", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_BYP0_L_10", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_IMUX38_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_EE4B1_10", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_IMUX44_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_LH6_10", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_ER1BEG0_10", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_IMUX10_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_IMUX3_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_FAN5_L_10", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_IMUX45_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_EE4B2_10", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_LH10_10", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_FAN7_L_10", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_LH11_10", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_EE4B3_10", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_NW4A3_10", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_IMUX33_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_IMUX4_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_EL1BEG3_10", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_WW4A0_10", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_SW2A1_10", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_LH1_10", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_NW4A1_10", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_IMUX25_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_SW4A2_10", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_SE2A3_10", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_SE2A1_10", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_EL1BEG2_10", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_WR1END2_10", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_IMUX0_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_LH4_10", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_WW4C1_10", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_EE2A0_10", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_EE2A3_10", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_NE4BEG0_10", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_IMUX26_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_EE2A1_10", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_NE4BEG1_10", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX5_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_SW4END2_10", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_WL1END2_10", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_FAN2_L_10", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_WW4END2_10", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_LH9_10", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_EE2BEG3_10", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_WW4A3_10", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_NW2A3_10", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_FAN4_L_10", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_IMUX43_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_EE2BEG0_10", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_EE4A0_10", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_EE4C3_10", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_WL1END3_10", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_SE4C0_10", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_WW4A2_10", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_FAN3_L_10", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_NW4A2_10", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_IMUX39_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_IMUX22_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_WW2END2_10", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_WW4C0_10", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_NE2A1_10", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_LH5_10", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_EE2A2_10", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_IMUX29_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_SW4A3_10", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_NW4END0_10", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_IMUX40_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_WW4C3_10", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_IMUX2_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_IMUX34_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_EE4C2_10", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_NW4END1_10", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_IMUX46_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_EE4B0_10", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_SE4BEG0_10", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_EE4C0_10", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX13_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_IMUX14_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_FAN0_L_10", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_WW4B2_10", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_WW2END3_10", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_WW4C2_10", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_SW2A0_10", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX37_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_FAN1_L_10", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_WW4B0_10", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_IMUX7_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_IMUX27_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_IMUX9_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_EE2BEG2_10", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_NE4C2_10", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_SE4BEG1_10", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_NW4END3_10", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_BYP4_L_10", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_SW2A3_10", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_WW2END0_10", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_SE2A2_10", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_BYP1_L_10", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_LH2_10", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_WL1END1_10", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_WW4B1_10", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_IMUX36_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_NE4C1_10", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_NW4A0_10", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_CTRL0_L_10", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_IMUX1_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_WW4B3_10", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_EE4BEG2_10", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_ER1BEG2_10", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_EE4BEG3_10", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_SW4END0_10", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_IMUX28_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_IMUX47_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_WR1END3_10", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_ER1BEG1_10", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_LH12_10", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_EL1BEG0_10", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_BYP2_L_10", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_WR1END1_10", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_IMUX17_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_SE4C2_10", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_NE4BEG3_10", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_IMUX30_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_LH8_10", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_NW4END2_10", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_CLK1_L_10", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_NE2A2_10", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_SW4END1_10", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_WW4END0_10", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_IMUX41_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_CTRL1_L_10", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_FAN6_L_10", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_WW2END1_10", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_EE4A1_10", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_IMUX21_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_WW4A1_10", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_LH7_10", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_NW2A0_10", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_IMUX19_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_IMUX23_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_WR1END0_10", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_IMUX6_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_ER1BEG3_10", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_NE2A3_10", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_IMUX16_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_LH3_10", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_CLK0_L_10", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_IMUX12_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_NE4BEG2_10", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_NE4C0_10", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_EE4BEG0_10", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_EE4A3_10", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_WW4END3_10", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_10", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_SW4A0_10", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_IMUX8_L_10", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_EE2BEG1_10", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_SE4C3_10", + "INT_INTERFACE_SE4C3" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "IOI_IOCLK1", + "IOI_SING_IOCLK1" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_SING_LEAF_GCLK2" + ], + [ + "IOI_IOCLK3", + "IOI_SING_IOCLK3" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_SING_LEAF_GCLK4" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_SING_RCLK_FORIO2" + ], + [ + "IOI_IOCLK2", + "IOI_SING_IOCLK2" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_SING_LEAF_GCLK5" + ], + [ + "IOI_TBYTEIN", + "IOI_SING_TBYTEIN" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_SING_LEAF_GCLK1" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_SING_RCLK_FORIO1" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_SING_LEAF_GCLK3" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_SING_RCLK_FORIO0" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_SING_LEAF_GCLK0" + ], + [ + "IOI_IOCLK0", + "IOI_SING_IOCLK0" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_SING_RCLK_FORIO3" + ] + ], + "tile_types": [ + "RIOI", + "RIOI_SING" + ] + }, + { + "grid_deltas": [ + 5, + 9 + ], + "wire_pairs": [ + [ + "PCIE_CTRL1_L_1", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_SW2A1_1", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_WW4A1_1", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_IMUX21_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_IMUX28_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_BYP5_L_1", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_SE4BEG2_1", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_IMUX2_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_IMUX40_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_BYP2_L_1", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_IMUX15_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_LH10_1", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_SE2A3_1", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_BYP0_L_1", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_WW4A2_1", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_IMUX46_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_IMUX34_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_IMUX16_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_NE4BEG3_1", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_EE2A1_1", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_CLK0_L_1", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_WW2END0_1", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_LH2_1", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_WL1END0_1", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_IMUX10_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_LH1_1", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_NW4A0_1", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_NE2A0_1", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_WW4A0_1", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_NE2A1_1", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_EE4A3_1", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_IMUX0_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_SW4A3_1", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_WW4C1_1", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_EE4BEG3_1", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_NE4BEG2_1", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_SW4END2_1", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_EE2BEG0_1", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_LH3_1", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_IMUX25_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_WW4END2_1", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_SW4A1_1", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_SW2A3_1", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_FAN4_L_1", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_IMUX38_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_NW4END1_1", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_EE2BEG3_1", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_EE4B0_1", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX37_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_NW4A2_1", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_SE4C3_1", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_IMUX32_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_ER1BEG0_1", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_EL1BEG3_1", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_FAN5_L_1", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_IMUX35_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_BYP7_L_1", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_WW4END1_1", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_WW2END2_1", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_EE4C2_1", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_EE4B2_1", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_ER1BEG2_1", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_NW2A1_1", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_WR1END0_1", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_SW4END3_1", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_NW4END2_1", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_IMUX26_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_LH11_1", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_LH7_1", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_IMUX44_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_SW4END1_1", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_SW4A2_1", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_FAN6_L_1", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_WW4C2_1", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_IMUX11_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_IMUX1_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_ER1BEG1_1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_WR1END1_1", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_IMUX45_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_NW2A3_1", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_BYP3_L_1", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_EE4BEG2_1", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_EE4A0_1", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_NE4BEG0_1", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_IMUX5_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_IMUX8_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_WW4B2_1", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_IMUX30_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_NW4A3_1", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_IMUX29_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_IMUX13_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_IMUX23_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_NW2A2_1", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_EE4C3_1", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_WW4B1_1", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_IMUX20_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_LH8_1", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_IMUX4_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_CTRL0_L_1", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_EE2BEG2_1", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_WW4C3_1", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_SE2A0_1", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_WW4END0_1", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_NW4END3_1", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_IMUX7_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_IMUX19_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_IMUX12_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_SE4BEG3_1", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_WW4B0_1", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_NE4C3_1", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_ER1BEG3_1", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_FAN2_L_1", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_BYP6_L_1", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_LH9_1", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_EE4BEG1_1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_FAN3_L_1", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_WW2END3_1", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_CLK1_L_1", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_EE4A1_1", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_IMUX27_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_SE4C1_1", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_SW4END0_1", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_WR1END2_1", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_SE2A2_1", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_IMUX3_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_WW4END3_1", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_EL1BEG1_1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_SW4A0_1", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_SW2A0_1", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_EL1BEG2_1", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_LH12_1", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_MONITOR_N_1", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_NE2A2_1", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_BYP1_L_1", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_IMUX22_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_IMUX47_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_EE2BEG1_1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_NE4C1_1", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_WL1END2_1", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_SW2A2_1", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_EE4A2_1", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_EE4BEG0_1", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_IMUX42_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_BYP4_L_1", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_WW4C0_1", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_SE4C2_1", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_EE2A3_1", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_WW2A0_1", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_IMUX24_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_IMUX14_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_NW2A0_1", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_EE4B3_1", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_MONITOR_P_1", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_WW2END1_1", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_SE2A1_1", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_IMUX18_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_IMUX9_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_WW4A3_1", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_IMUX6_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_LH6_1", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_IMUX17_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_WL1END3_1", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_FAN1_L_1", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_1", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_IMUX36_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_WW4B3_1", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_LH5_1", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_FAN0_L_1", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_SE4C0_1", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_EL1BEG0_1", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_IMUX39_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_NW4A1_1", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_NE4C0_1", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_WL1END1_1", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_EE2A0_1", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_NE2A3_1", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_IMUX31_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_EE4B1_1", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_IMUX43_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_FAN7_L_1", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_LH4_1", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_EE4C1_1", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_NE4BEG1_1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_EE4C0_1", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_EE2A2_1", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_SE4BEG0_1", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_WR1END3_1", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_NE4C2_1", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_NW4END0_1", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_WW2A3_1", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_IMUX41_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_IMUX33_L_1", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_SE4BEG1_1", + "INT_INTERFACE_SE4BEG1" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "BRAM_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "BRAM_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "BRAM_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "BRAM_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "BRAM_LH4_3", + "VBRK_LH4" + ], + [ + "BRAM_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "BRAM_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "BRAM_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "BRAM_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "BRAM_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "BRAM_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "BRAM_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "BRAM_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "BRAM_LH1_3", + "VBRK_LH1" + ], + [ + "BRAM_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "BRAM_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "BRAM_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "BRAM_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "BRAM_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "BRAM_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "BRAM_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "BRAM_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "BRAM_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "BRAM_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "BRAM_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "BRAM_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "BRAM_LH7_3", + "VBRK_LH7" + ], + [ + "BRAM_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "BRAM_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "BRAM_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "BRAM_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "BRAM_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "BRAM_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "BRAM_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "BRAM_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "BRAM_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "BRAM_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "BRAM_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "BRAM_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "BRAM_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "BRAM_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "BRAM_LH8_3", + "VBRK_LH8" + ], + [ + "BRAM_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "BRAM_EL1BEG1_3", + "VBRK_EL1BEG1" + ], + [ + "BRAM_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "BRAM_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "BRAM_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "BRAM_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "BRAM_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "BRAM_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "BRAM_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "BRAM_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "BRAM_LH11_3", + "VBRK_LH11" + ], + [ + "BRAM_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "BRAM_MONITOR_P_3", + "VBRK_MONITOR_P" + ], + [ + "BRAM_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "BRAM_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "BRAM_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "BRAM_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "BRAM_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "BRAM_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "BRAM_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "BRAM_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "BRAM_LH10_3", + "VBRK_LH10" + ], + [ + "BRAM_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "BRAM_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "BRAM_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "BRAM_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "BRAM_LH3_3", + "VBRK_LH3" + ], + [ + "BRAM_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "BRAM_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "BRAM_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "BRAM_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "BRAM_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "BRAM_LH12_3", + "VBRK_LH12" + ], + [ + "BRAM_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "BRAM_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "BRAM_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "BRAM_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "BRAM_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "BRAM_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "BRAM_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "BRAM_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "BRAM_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "BRAM_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "BRAM_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "BRAM_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "BRAM_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "BRAM_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "BRAM_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "BRAM_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "BRAM_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "BRAM_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "BRAM_MONITOR_N_3", + "VBRK_MONITOR_N" + ], + [ + "BRAM_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "BRAM_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "BRAM_LH2_3", + "VBRK_LH2" + ], + [ + "BRAM_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "BRAM_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "BRAM_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "BRAM_LH5_3", + "VBRK_LH5" + ], + [ + "BRAM_LH9_3", + "VBRK_LH9" + ], + [ + "BRAM_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "BRAM_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "BRAM_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "BRAM_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "BRAM_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "BRAM_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "BRAM_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "BRAM_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "BRAM_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "BRAM_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "BRAM_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "BRAM_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "BRAM_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "BRAM_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "BRAM_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "BRAM_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "BRAM_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "BRAM_LH6_3", + "VBRK_LH6" + ], + [ + "BRAM_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "BRAM_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "BRAM_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "BRAM_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "BRAM_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "BRAM_WW4A3_3", + "VBRK_WW4A3" + ] + ], + "tile_types": [ + "BRAM_L", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "BRAM_CASCOUT_ADDRARDADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0" + ], + [ + "BRAM_FIFO36_CASCADEINB", + "BRKH_BRAM_CASCADEB_L" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" + ], + [ + "BRAM_FIFO36_CASCADEINA", + "BRKH_BRAM_CASCADEA_L" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" + ] + ], + "tile_types": [ + "BRAM_L", + "BRKH_BRAM" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX27_5", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX13_5", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_LOGIC_OUTS_B4_5", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B22_5", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX30_5", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_LOGIC_OUTS_B14_5", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX0_5", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_BYP4_5", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX18_5", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_LOGIC_OUTS_B8_5", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX16_5", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX42_5", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX46_5", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX11_5", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX6_5", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B9_5", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX45_5", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX7_5", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_BYP0_5", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX33_5", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX38_5", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_LOGIC_OUTS_B11_5", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_BYP2_5", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX23_5", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_LOGIC_OUTS_B6_5", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_LOGIC_OUTS_B2_5", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX41_5", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B5_5", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX12_5", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX14_5", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX22_5", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_CLK0_5", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX43_5", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX37_5", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX9_5", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX29_5", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_BYP1_5", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_CTRL1_5", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_CLK1_5", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_CTRL0_5", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX28_5", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX32_5", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX17_5", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_FAN6_5", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_BYP5_5", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B7_5", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B17_5", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX26_5", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX1_5", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_FAN0_5", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX8_5", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_LOGIC_OUTS_B16_5", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX4_5", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_BYP7_5", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B3_5", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX35_5", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX39_5", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B18_5", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_LOGIC_OUTS_B12_5", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX19_5", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_FAN7_5", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B13_5", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B23_5", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_LOGIC_OUTS_B0_5", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX36_5", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX2_5", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX40_5", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_FAN3_5", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX3_5", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX10_5", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_FAN5_5", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX34_5", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX20_5", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN4_5", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX24_5", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B10_5", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_BYP3_5", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B15_5", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX31_5", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_FAN1_5", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_FAN2_5", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_LOGIC_OUTS_B20_5", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX5_5", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_BYP6_5", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX47_5", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX15_5", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX25_5", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX21_5", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX44_5", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_LOGIC_OUTS_B19_5", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B1_5", + "VBRK_EXT_LOGIC_OUTS_B1" + ] + ], + "tile_types": [ + "GTX_CHANNEL_0", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW2END1_1", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE4BEG0_1", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_LH9_1", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NW4A1_1", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WW2END3_1", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_SW4A3_1", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_WW4B3_1", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SE2A3_1", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_LH5_1", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_LH2_1", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_ER1BEG3_1", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_LH6_1", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WL1END0_1", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_WW4A0_1", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE2BEG2_1", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NE4BEG0_1", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NW4END1_1", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_EE4B0_1", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_SW4A1_1", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NW4END0_1", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_LH7_1", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_LH11_1", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_LH10_1", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WW4A3_1", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NE4BEG3_1", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW2END2_1", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_WR1END3_1", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_SW4A0_1", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_SW2A1_1", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4B3_1", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SE2A0_1", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE2A3_1", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_SE4C3_1", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_NW2A1_1", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_NW2A0_1", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WW4C0_1", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NW4A0_1", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_WW2END0_1", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NW4END3_1", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WL1END1_1", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_NW2A2_1", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_EL1BEG2_1", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_NE4C2_1", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WR1END2_1", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_SE4C2_1", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_EE2A1_1", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_EE4C2_1", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_WW4B1_1", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_SW4A2_1", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_LH8_1", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW4A1_1", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_NE4BEG1_1", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_EE4B1_1", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EE4BEG2_1", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WW2A1_1", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_LH1_1", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_WW2A2_1", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_EE4B2_1", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_WW4B0_1", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_LH3_1", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_EE2A0_1", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_EE4A3_1", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_WW4A2_1", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EL1BEG1_1", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NW2A3_1", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE2A0_1", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_SW4END1_1", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_NE2A3_1", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_SE4BEG3_1", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EE4BEG1_1", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG0_1", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SE4C0_1", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_NE2A1_1", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_WW4C2_1", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NW4END2_1", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_EE4C1_1", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE2BEG0_1", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4END1_1", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE2BEG1_1", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_SW4END2_1", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_NE2A2_1", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE4C3_1", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW4C1_1", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_EL1BEG3_1", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_SE2A1_1", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_SE2A2_1", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_WL1END2_1", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_LH12_1", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_NE4C0_1", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_WW4END0_1", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_NE4C3_1", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_EE4A1_1", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EL1BEG0_1", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_SW2A2_1", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_EE4A2_1", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_WW4C3_1", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_LH4_1", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE2A2_1", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WL1END3_1", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4C0_1", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_SE4BEG2_1", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_EE2BEG3_1", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NE4C1_1", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE4BEG2_1", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_ER1BEG0_1", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NW4A2_1", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_EE4A0_1", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_ER1BEG2_1", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_SW2A3_1", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_ER1BEG1_1", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WW4END3_1", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WR1END0_1", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_SW4END0_1", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WW2A3_1", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_EE4BEG3_1", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_SW4END3_1", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_WW2A0_1", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_SW2A0_1", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WW4END2_1", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_NW4A3_1", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_SE4BEG1_1", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_WW4B2_1", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_WR1END1_1", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SE4C1_1", + "INT_FEEDTHRU_2_SE4C1" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 0, + 5 + ], + "wire_pairs": [ + [ + "DSP_0_PCIN30", + "DSP_PCOUT30" + ], + [ + "DSP_0_ACIN5", + "DSP_ACOUT5" + ], + [ + "DSP_0_ACIN20", + "DSP_ACOUT20" + ], + [ + "DSP_0_PCIN47", + "DSP_PCOUT47" + ], + [ + "DSP_0_ACIN15", + "DSP_ACOUT15" + ], + [ + "DSP_0_ACIN8", + "DSP_ACOUT8" + ], + [ + "DSP_0_ACIN18", + "DSP_ACOUT18" + ], + [ + "DSP_0_PCIN22", + "DSP_PCOUT22" + ], + [ + "DSP_0_ACIN26", + "DSP_ACOUT26" + ], + [ + "DSP_0_ACIN14", + "DSP_ACOUT14" + ], + [ + "DSP_0_ACIN21", + "DSP_ACOUT21" + ], + [ + "DSP_0_PCIN5", + "DSP_PCOUT5" + ], + [ + "DSP_0_PCIN45", + "DSP_PCOUT45" + ], + [ + "DSP_0_MULTSIGNIN", + "DSP_MULTSIGNOUT" + ], + [ + "DSP_0_ACIN28", + "DSP_ACOUT28" + ], + [ + "DSP_0_PCIN20", + "DSP_PCOUT20" + ], + [ + "DSP_0_BCIN13", + "DSP_BCOUT13" + ], + [ + "DSP_0_ACIN25", + "DSP_ACOUT25" + ], + [ + "DSP_0_PCIN2", + "DSP_PCOUT2" + ], + [ + "DSP_0_PCIN0", + "DSP_PCOUT0" + ], + [ + "DSP_0_PCIN16", + "DSP_PCOUT16" + ], + [ + "DSP_0_BCIN16", + "DSP_BCOUT16" + ], + [ + "DSP_0_ACIN4", + "DSP_ACOUT4" + ], + [ + "DSP_0_PCIN7", + "DSP_PCOUT7" + ], + [ + "DSP_0_PCIN25", + "DSP_PCOUT25" + ], + [ + "DSP_0_BCIN15", + "DSP_BCOUT15" + ], + [ + "DSP_0_PCIN11", + "DSP_PCOUT11" + ], + [ + "DSP_0_ACIN19", + "DSP_ACOUT19" + ], + [ + "DSP_0_BCIN12", + "DSP_BCOUT12" + ], + [ + "DSP_0_ACIN0", + "DSP_ACOUT0" + ], + [ + "DSP_0_BCIN6", + "DSP_BCOUT6" + ], + [ + "DSP_0_PCIN42", + "DSP_PCOUT42" + ], + [ + "DSP_0_PCIN3", + "DSP_PCOUT3" + ], + [ + "DSP_0_CARRYCASCIN", + "DSP_CARRYCASCOUT" + ], + [ + "DSP_0_PCIN38", + "DSP_PCOUT38" + ], + [ + "DSP_0_PCIN18", + "DSP_PCOUT18" + ], + [ + "DSP_0_PCIN34", + "DSP_PCOUT34" + ], + [ + "DSP_0_PCIN23", + "DSP_PCOUT23" + ], + [ + "DSP_0_ACIN24", + "DSP_ACOUT24" + ], + [ + "DSP_0_ACIN22", + "DSP_ACOUT22" + ], + [ + "DSP_0_PCIN6", + "DSP_PCOUT6" + ], + [ + "DSP_0_PCIN12", + "DSP_PCOUT12" + ], + [ + "DSP_0_PCIN1", + "DSP_PCOUT1" + ], + [ + "DSP_0_PCIN13", + "DSP_PCOUT13" + ], + [ + "DSP_0_BCIN1", + "DSP_BCOUT1" + ], + [ + "DSP_0_PCIN17", + "DSP_PCOUT17" + ], + [ + "DSP_0_BCIN5", + "DSP_BCOUT5" + ], + [ + "DSP_0_BCIN0", + "DSP_BCOUT0" + ], + [ + "DSP_0_PCIN32", + "DSP_PCOUT32" + ], + [ + "DSP_0_PCIN39", + "DSP_PCOUT39" + ], + [ + "DSP_0_PCIN9", + "DSP_PCOUT9" + ], + [ + "DSP_0_PCIN4", + "DSP_PCOUT4" + ], + [ + "DSP_0_BCIN10", + "DSP_BCOUT10" + ], + [ + "DSP_0_ACIN10", + "DSP_ACOUT10" + ], + [ + "DSP_0_PCIN8", + "DSP_PCOUT8" + ], + [ + "DSP_0_BCIN17", + "DSP_BCOUT17" + ], + [ + "DSP_0_PCIN26", + "DSP_PCOUT26" + ], + [ + "DSP_0_ACIN13", + "DSP_ACOUT13" + ], + [ + "DSP_0_PCIN37", + "DSP_PCOUT37" + ], + [ + "DSP_0_ACIN23", + "DSP_ACOUT23" + ], + [ + "DSP_0_ACIN17", + "DSP_ACOUT17" + ], + [ + "DSP_0_PCIN21", + "DSP_PCOUT21" + ], + [ + "DSP_0_BCIN11", + "DSP_BCOUT11" + ], + [ + "DSP_0_ACIN1", + "DSP_ACOUT1" + ], + [ + "DSP_0_PCIN46", + "DSP_PCOUT46" + ], + [ + "DSP_0_PCIN14", + "DSP_PCOUT14" + ], + [ + "DSP_0_PCIN36", + "DSP_PCOUT36" + ], + [ + "DSP_0_PCIN35", + "DSP_PCOUT35" + ], + [ + "DSP_0_ACIN9", + "DSP_ACOUT9" + ], + [ + "DSP_0_BCIN8", + "DSP_BCOUT8" + ], + [ + "DSP_0_PCIN40", + "DSP_PCOUT40" + ], + [ + "DSP_0_PCIN41", + "DSP_PCOUT41" + ], + [ + "DSP_0_ACIN27", + "DSP_ACOUT27" + ], + [ + "DSP_0_PCIN15", + "DSP_PCOUT15" + ], + [ + "DSP_0_ACIN2", + "DSP_ACOUT2" + ], + [ + "DSP_0_ACIN29", + "DSP_ACOUT29" + ], + [ + "DSP_0_PCIN31", + "DSP_PCOUT31" + ], + [ + "DSP_0_BCIN2", + "DSP_BCOUT2" + ], + [ + "DSP_0_PCIN33", + "DSP_PCOUT33" + ], + [ + "DSP_0_BCIN4", + "DSP_BCOUT4" + ], + [ + "DSP_0_PCIN28", + "DSP_PCOUT28" + ], + [ + "DSP_0_BCIN7", + "DSP_BCOUT7" + ], + [ + "DSP_0_ACIN6", + "DSP_ACOUT6" + ], + [ + "DSP_0_BCIN3", + "DSP_BCOUT3" + ], + [ + "DSP_0_ACIN16", + "DSP_ACOUT16" + ], + [ + "DSP_0_PCIN43", + "DSP_PCOUT43" + ], + [ + "DSP_0_PCIN24", + "DSP_PCOUT24" + ], + [ + "DSP_0_ACIN7", + "DSP_ACOUT7" + ], + [ + "DSP_0_PCIN27", + "DSP_PCOUT27" + ], + [ + "DSP_0_PCIN44", + "DSP_PCOUT44" + ], + [ + "DSP_0_BCIN9", + "DSP_BCOUT9" + ], + [ + "DSP_0_BCIN14", + "DSP_BCOUT14" + ], + [ + "DSP_0_PCIN29", + "DSP_PCOUT29" + ], + [ + "DSP_0_ACIN11", + "DSP_ACOUT11" + ], + [ + "DSP_0_PCIN10", + "DSP_PCOUT10" + ], + [ + "DSP_0_ACIN3", + "DSP_ACOUT3" + ], + [ + "DSP_0_ACIN12", + "DSP_ACOUT12" + ], + [ + "DSP_0_PCIN19", + "DSP_PCOUT19" + ] + ], + "tile_types": [ + "DSP_R", + "DSP_R" + ] + }, + { + "grid_deltas": [ + 1, + 3 + ], + "wire_pairs": [ + [ + "CMT_TOP_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_LH2_1", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH11_1", + "VBRK_LH11" + ], + [ + "CMT_TOP_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH10_1", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_LH8_1", + "VBRK_LH8" + ], + [ + "CMT_TOP_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH3_1", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH4_1", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH5_1", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_1", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_LH6_1", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH1_1", + "VBRK_LH1" + ], + [ + "CMT_TOP_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_LH7_1", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH9_1", + "VBRK_LH9" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -9 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW4B2_19", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_IMUX0_19", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW2A1_19", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_WW2A3_19", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_WW4B0_19", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_IMUX10_19", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_NW4END1_19", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_EE4B3_19", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_NW4END3_19", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_IMUX32_19", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_WR1END3_19", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_BYP2_19", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_EE4BEG0_19", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_NW4A2_19", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_SW4END1_19", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_WW4A0_19", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_EL1BEG1_19", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_LH11_19", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_EE4BEG2_19", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX46_19", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_FAN6_19", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_EE2A1_19", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_SW2A2_19", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_NE4C0_19", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE4C3_19", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE4B0_19", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WW2END3_19", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW4END3_19", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_WW4C1_19", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_EE4BEG1_19", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_NE4BEG1_19", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_SE4C1_19", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX16_19", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_NE2A0_19", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_WW4A3_19", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_LH8_19", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_CLK0_19", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_NE4C3_19", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_SW2A0_19", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_WW4END2_19", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_WW4B1_19", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_CTRL0_19", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_SE4BEG0_19", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_CTRL1_19", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_LH10_19", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_IMUX9_19", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX37_19", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_EE4C2_19", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_SW4A0_19", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_IMUX40_19", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_BYP4_19", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_NW4A1_19", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_BYP7_19", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_NE2A3_19", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_NW4A3_19", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_FAN4_19", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_CLK1_19", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX19_19", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_IMUX20_19", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_LH4_19", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_ER1BEG2_19", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX21_19", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_LH3_19", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX30_19", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_SW4END2_19", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_BYP1_19", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_BYP3_19", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_IMUX38_19", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_SE2A1_19", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_EE2BEG0_19", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_WW2A2_19", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_SE4C0_19", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_WL1END3_19", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_EE4B2_19", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_LH7_19", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_LH5_19", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX14_19", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_IMUX25_19", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_NW2A3_19", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NW2A2_19", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WR1END2_19", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_NE4BEG3_19", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX24_19", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_SW2A3_19", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_EL1BEG3_19", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW4A1_19", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_IMUX17_19", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_BYP5_19", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_NE4BEG2_19", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW2END0_19", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_LH1_19", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_EE4C0_19", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_EE4A3_19", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX8_19", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_IMUX15_19", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_BYP6_19", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_LH2_19", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_FAN2_19", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_LH9_19", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EL1BEG2_19", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX2_19", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_SE4BEG1_19", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG3_19", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_WR1END1_19", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_IMUX7_19", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_IMUX28_19", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_FAN7_19", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_EE2BEG2_19", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX3_19", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_FAN1_19", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX13_19", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_EE4B1_19", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_IMUX12_19", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX23_19", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NW4END2_19", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_IMUX44_19", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WW4B3_19", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_EE2BEG1_19", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_EE4A2_19", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_SW4A3_19", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_SW4END3_19", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_ER1BEG0_19", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_EE2A0_19", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_BYP0_19", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX36_19", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_NW2A0_19", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_EE4A0_19", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_WW4C3_19", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NW4A0_19", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX29_19", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_NE4BEG0_19", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_WW2END2_19", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_NW4END0_19", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX42_19", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_LH12_19", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_SE2A3_19", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_NE4C1_19", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_SE4BEG2_19", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_IMUX1_19", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX4_19", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX39_19", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_WW4A2_19", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_IMUX26_19", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX27_19", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_LH6_19", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_SW4A1_19", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_IMUX35_19", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_WW2END1_19", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_WW4C0_19", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX18_19", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_SE2A0_19", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_IMUX22_19", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_FAN5_19", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_EE4A1_19", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX47_19", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX11_19", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX33_19", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_WL1END0_19", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_SE2A2_19", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_WL1END2_19", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_IMUX41_19", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_WW4END1_19", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_NW2A1_19", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_ER1BEG1_19", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_NE2A1_19", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_ER1BEG3_19", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_NE2A2_19", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE2BEG3_19", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX45_19", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX31_19", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_WW2A0_19", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_SW4A2_19", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NE4C2_19", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_SE4C3_19", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX5_19", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX6_19", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_EE2A3_19", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_FAN3_19", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_IMUX43_19", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_SW2A1_19", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_FAN0_19", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_EL1BEG0_19", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_SE4C2_19", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_IMUX34_19", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_WR1END0_19", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EE4BEG3_19", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_SW4END0_19", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_WW4END0_19", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_WL1END1_19", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_EE4C1_19", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_EE2A2_19", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_WW4C2_19", + "VFRAME_WW4C2" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLK_HROW_CK_BUFHCLK_R1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "CLK_HROW_CK_IN_R5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "CLK_HROW_CK_BUFHCLK_R5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "CLK_HROW_CK_BUFHCLK_R10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "CLK_HROW_CK_IN_R10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "CLK_HROW_CK_BUFHCLK_R4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "CLK_HROW_CK_IN_R13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "CLK_HROW_CK_BUFHCLK_R8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "CLK_HROW_CK_IN_R8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "CLK_HROW_CK_IN_R12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "CLK_HROW_CK_IN_R7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "CLK_HROW_CK_BUFHCLK_R0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "CLK_HROW_CK_BUFHCLK_R7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "CLK_HROW_CK_IN_R11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "CLK_HROW_CK_BUFHCLK_R9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "CLK_HROW_CK_IN_R9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "CLK_HROW_CK_BUFHCLK_R6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "CLK_HROW_CK_BUFHCLK_R3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "CLK_HROW_CK_BUFHCLK_R11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "CLK_HROW_CK_IN_R4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "CLK_HROW_CK_BUFHCLK_R2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "CLK_HROW_CK_IN_R6", + "HCLK_VBRK_MUX_CLK6" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "HCLK_VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "CMT_TOP_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH1_2", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH2_2", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_LH6_2", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_LH7_2", + "VBRK_LH7" + ], + [ + "CMT_TOP_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH12_2", + "VBRK_LH12" + ], + [ + "CMT_TOP_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_LH11_2", + "VBRK_LH11" + ], + [ + "CMT_TOP_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4B3_2", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_MONITOR_P_2", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH4_2", + "VBRK_LH4" + ], + [ + "CMT_TOP_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_LH5_2", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH3_2", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_MONITOR_N_2", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH10_2", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH8_2", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_LH9_2", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW2A2_2", + "VBRK_NW2A2" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 4 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_LOGIC_OUTS1_2", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "CMT_FIFO_L_IMUX21_2", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_2", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "CMT_FIFO_LH11_2", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_SE2A2_2", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_L_IMUX37_2", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_EE4B3_2", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_WW4A1_2", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_EE4A1_2", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_SW2A2_2", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_2", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "CMT_FIFO_L_IMUX14_2", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_EE4BEG0_2", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX17_2", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_WW4END0_2", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_2", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "CMT_FIFO_EE4A0_2", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_2", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "CMT_FIFO_L_IMUX42_2", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_NE2A3_2", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_EL1BEG2_2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_WW4C2_2", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_IMUX47_2", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_SW4END2_2", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_2", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "CMT_FIFO_L_IMUX10_2", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_NE4BEG1_2", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_2", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "CMT_FIFO_L_BYP0_2", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_L_IMUX39_2", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_L_CLK1_2", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_EE2A0_2", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_WW2END0_2", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_WW4C0_2", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_L_IMUX26_2", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_FAN6_2", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_WW2A2_2", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_ER1BEG2_2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_LH12_2", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_WR1END1_2", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_L_BYP6_2", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_NE2A2_2", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_EL1BEG0_2", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_L_IMUX2_2", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_NE4C2_2", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_L_IMUX7_2", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_L_IMUX19_2", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_NW2A3_2", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_EE4C2_2", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_EE2A3_2", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_WR1END2_2", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_L_IMUX43_2", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_L_FAN5_2", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_L_IMUX25_2", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_SW2A3_2", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_LH9_2", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_NE4C1_2", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_ER1BEG1_2", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_2", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "CMT_FIFO_EE4B2_2", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_EE4BEG2_2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX6_2", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_2", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "CMT_FIFO_L_IMUX41_2", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_LH3_2", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_L_BYP7_2", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_WW4B1_2", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_WW2A0_2", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_SW2A1_2", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_WR1END3_2", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_L_CTRL1_2", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_WW2END3_2", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_L_IMUX34_2", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_L_IMUX12_2", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_SW4A2_2", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_L_FAN7_2", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_L_IMUX0_2", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_EE4A2_2", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_IMUX46_2", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_WW2A1_2", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_L_IMUX33_2", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_L_IMUX22_2", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_2", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "CMT_FIFO_L_FAN3_2", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_L_IMUX32_2", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_2", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "CMT_FIFO_NW2A1_2", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_NW4END2_2", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_EE2BEG3_2", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_L_IMUX11_2", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_L_BYP2_2", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_L_BYP3_2", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_SE4C1_2", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_NE2A0_2", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_NW4A3_2", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_SE2A1_2", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_L_CLK0_2", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_EL1BEG3_2", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_NW4END0_2", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_SE2A0_2", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_2", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "CMT_FIFO_SE4BEG0_2", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_WL1END0_2", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_WW4END2_2", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_EE2BEG2_2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_WW4C1_2", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_MONITOR_N_2", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_2", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "CMT_FIFO_EE2A1_2", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_L_IMUX44_2", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_WW4B2_2", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_SW4A3_2", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_L_BYP1_2", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_SE4BEG3_2", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_WW4END3_2", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_L_IMUX20_2", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_L_IMUX29_2", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_SE4BEG2_2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_ER1BEG0_2", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_L_IMUX16_2", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_EE2BEG1_2", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_L_IMUX1_2", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_IMUX15_2", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_SW4A1_2", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_LH4_2", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_LH1_2", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_LH10_2", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_L_BYP4_2", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_EE4C1_2", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_WW4END1_2", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_L_IMUX31_2", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_MONITOR_P_2", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CMT_FIFO_WL1END1_2", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_EE4A3_2", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_NW4A2_2", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_2", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "CMT_FIFO_WW4A3_2", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_NW4A0_2", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_NW4A1_2", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_L_IMUX27_2", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_EE4B1_2", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_2", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_2", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "CMT_FIFO_NE4BEG3_2", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_L_FAN0_2", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_WW4B3_2", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_L_IMUX4_2", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_2", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "CMT_FIFO_L_IMUX45_2", + "INT_INTERFACE_IMUX45" + ], + [ + "FIFO_DQS_IOTOPHASER_44", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "CMT_FIFO_EE4C0_2", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_2", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_2", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_2", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "CMT_FIFO_SW4A0_2", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_L_IMUX8_2", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_SE4C0_2", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_WL1END3_2", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_SE2A3_2", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_EL1BEG1_2", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_WW4A2_2", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_ER1BEG3_2", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_WW2END2_2", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_WW2A3_2", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_2", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "CMT_FIFO_NE4BEG2_2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX40_2", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_SW4END1_2", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_SW4END0_2", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_2", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "CMT_FIFO_LH8_2", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_BYP5_2", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_NE4C0_2", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_WL1END2_2", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_L_IMUX5_2", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_EE4C3_2", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_NE2A1_2", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_L_IMUX36_2", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_WW4A0_2", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_NW4END3_2", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_L_FAN2_2", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_L_CTRL0_2", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_NW4END1_2", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_LH6_2", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_L_IMUX35_2", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_L_IMUX23_2", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_EE2A2_2", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_EE4BEG1_2", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_WW4C3_2", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_NE4BEG0_2", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_EE2BEG0_2", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_IMUX3_2", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_L_IMUX9_2", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_WW4B0_2", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_NW2A2_2", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_SE4BEG1_2", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX18_2", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_SE4C2_2", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_L_IMUX28_2", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_L_IMUX38_2", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_NW2A0_2", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_LH7_2", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_LH2_2", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_WW2END1_2", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_LH5_2", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_L_FAN1_2", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_2", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "CMT_FIFO_EE4B0_2", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_SW4END3_2", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_L_IMUX13_2", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_SE4C3_2", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_IMUX30_2", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_EE4BEG3_2", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_SW2A0_2", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_2", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "CMT_FIFO_NE4C3_2", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_WR1END0_2", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_L_FAN4_2", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_L_IMUX24_2", + "INT_INTERFACE_IMUX24" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 5, + -4 + ], + "wire_pairs": [ + [ + "PCIE_FAN7_L_14", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_EE2A2_14", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_EE4BEG3_14", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_NE2A0_14", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_EL1BEG2_14", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_IMUX41_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_WL1END1_14", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_WR1END3_14", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_IMUX17_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_IMUX31_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_NE2A2_14", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_SE4C0_14", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_BYP3_L_14", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_IMUX26_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_IMUX5_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_NW4END1_14", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_LH4_14", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_EE4B2_14", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_EE4BEG0_14", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX35_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_NW4A0_14", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_SE2A3_14", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_FAN3_L_14", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_WW4C3_14", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_CTRL0_L_14", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_IMUX8_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_WW2END2_14", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_WL1END2_14", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_IMUX33_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_SW4END3_14", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_LH8_14", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_WW4B0_14", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_SW4END1_14", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_ER1BEG1_14", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_BYP7_L_14", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_IMUX19_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_LH12_14", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_EE4A1_14", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_IMUX10_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_EE2A3_14", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_ER1BEG3_14", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_CLK1_L_14", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_BYP4_L_14", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_IMUX37_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_IMUX28_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_NE2A1_14", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_SW4END2_14", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_WR1END2_14", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_WW2END0_14", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_NE4C2_14", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_WW4C0_14", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_NW2A3_14", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_EE4C1_14", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_EE4C2_14", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_IMUX0_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_ER1BEG2_14", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_CLK0_L_14", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_SW2A0_14", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_SE2A1_14", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_SW2A3_14", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX40_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_SE2A0_14", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_BYP1_L_14", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_WW4A1_14", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_NE2A3_14", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_EE4B0_14", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX4_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_WW4B2_14", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_LH7_14", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_SE4BEG2_14", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_CTRL1_L_14", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_IMUX36_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_IMUX32_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_WW4END1_14", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_FAN4_L_14", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_NE4BEG2_14", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_EL1BEG3_14", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_EE2BEG2_14", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_SE4C1_14", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_IMUX3_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_WL1END3_14", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_IMUX13_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_NW4END3_14", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_SE2A2_14", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_EE4BEG1_14", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_NW4A3_14", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_IMUX22_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_BYP6_L_14", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_WW2END3_14", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_IMUX23_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_IMUX2_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_EE4C3_14", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_SW4A3_14", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_NW4A2_14", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_NW2A0_14", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_SE4BEG1_14", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_EE4A3_14", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_EE4C0_14", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_EL1BEG1_14", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_IMUX20_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_FAN0_L_14", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_EE4B3_14", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_IMUX6_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_LH6_14", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_WW4END3_14", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_FAN6_L_14", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_IMUX47_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_SE4BEG0_14", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_SW2A2_14", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_IMUX24_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_WW4B1_14", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_WW4END0_14", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_EE2BEG1_14", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_LH3_14", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_NE4BEG3_14", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_IMUX34_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_SW4A1_14", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_NE4BEG0_14", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_LH9_14", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_IMUX44_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_IMUX1_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_NW2A2_14", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_NE4C1_14", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_LH10_14", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_WL1END0_14", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_IMUX7_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_WW2A0_14", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_IMUX16_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_BYP0_L_14", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_NW4END0_14", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_IMUX43_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_FAN5_L_14", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_WW4A2_14", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_IMUX42_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_WW4B3_14", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_FAN2_L_14", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_WW2A2_14", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_WW2A1_14", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_NE4C3_14", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_IMUX46_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_SE4C3_14", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_WW4A3_14", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_EE2A1_14", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_EE4BEG2_14", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX45_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_EE4B1_14", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_IMUX39_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_LH1_14", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_SW4A0_14", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_NW4A1_14", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_IMUX12_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_SW4END0_14", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_EE4A0_14", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_WR1END0_14", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_IMUX9_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_IMUX27_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_EL1BEG0_14", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_FAN1_L_14", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_WW4A0_14", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_WW4C2_14", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_LH5_14", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_IMUX18_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_WW2A3_14", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_LH11_14", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_EE4A2_14", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_IMUX29_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_WW4C1_14", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_EE2BEG3_14", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_IMUX14_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_EE2A0_14", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_NE4BEG1_14", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_SE4BEG3_14", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_BYP5_L_14", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_IMUX11_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_IMUX38_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_EE2BEG0_14", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_IMUX15_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_IMUX21_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_IMUX30_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_NW4END2_14", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_IMUX25_L_14", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_NE4C0_14", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_WR1END1_14", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_LH2_14", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_SW4A2_14", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_SE4C2_14", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_SW2A1_14", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_WW2END1_14", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_14", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_BYP2_L_14", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_WW4END2_14", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_NW2A1_14", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_ER1BEG0_14", + "INT_INTERFACE_ER1BEG0" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + -1, + -6 + ], + "wire_pairs": [ + [ + "CLK_PMV_EE4BEG0_6", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_PMV_EE4BEG1_6", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_PMV_EE2BEG1_6", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_PMV_EE4A0_6", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_PMV_BYP4_6", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_PMV_SE2A0_6", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_PMV_WW4B0_6", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_PMV_NE2A0_6", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_PMV_WR1END1_6", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_PMV_LH11_6", + "INT_INTERFACE_LH11" + ], + [ + "CLK_PMV_SE4BEG2_6", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_PMV_SE4C3_6", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_PMV_EE4C2_6", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_PMV_IMUX36_6", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_PMV_EL1BEG0_6", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_PMV_NE4BEG1_6", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_PMV_LH9_6", + "INT_INTERFACE_LH9" + ], + [ + "CLK_PMV_IMUX20_6", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_PMV_FAN5_6", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_PMV_NE2A3_6", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_PMV_IMUX1_6", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_PMV_ER1BEG2_6", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_PMV_WL1END0_6", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_PMV_IMUX33_6", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_PMV_WW4C0_6", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_PMV_WW4END3_6", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_PMV_LH12_6", + "INT_INTERFACE_LH12" + ], + [ + "CLK_PMV_EE2A1_6", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_PMV_IMUX39_6", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_PMV_NE4BEG3_6", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_PMV_LH5_6", + "INT_INTERFACE_LH5" + ], + [ + "CLK_PMV_IMUX9_6", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_PMV_NE4C1_6", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_PMV_EE4A2_6", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_PMV_WW4A0_6", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_PMV_IMUX46_6", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_PMV_EE2A2_6", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_PMV_NW2A0_6", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_PMV_EE4BEG3_6", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_PMV_IMUX10_6", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_PMV_SW2A2_6", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_PMV_NW4END2_6", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_PMV_SW2A3_6", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_PMV_WR1END0_6", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_PMV_IMUX41_6", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_PMV_WW4END1_6", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_PMV_WW4A2_6", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_PMV_NE2A2_6", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_PMV_IMUX23_6", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_PMV_IMUX38_6", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_PMV_WW4END0_6", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_PMV_IMUX4_6", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_PMV_IMUX27_6", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_PMV_IMUX34_6", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_PMV_BYP6_6", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_PMV_IMUX35_6", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_PMV_LH7_6", + "INT_INTERFACE_LH7" + ], + [ + "CLK_PMV_WW4C3_6", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_PMV_NW4A1_6", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_PMV_SE4C2_6", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_PMV_NW4A0_6", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_PMV_LH2_6", + "INT_INTERFACE_LH2" + ], + [ + "CLK_PMV_IMUX6_6", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_PMV_EE4C3_6", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_PMV_LH1_6", + "INT_INTERFACE_LH1" + ], + [ + "CLK_PMV_WW4B3_6", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_PMV_ER1BEG3_6", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_PMV_ER1BEG1_6", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_PMV_SE4BEG0_6", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_PMV_IMUX40_6", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_PMV_NW4END3_6", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_PMV_WL1END1_6", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_PMV_IMUX18_6", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_PMV_IMUX32_6", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_PMV_EL1BEG2_6", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_PMV_WL1END3_6", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_PMV_IMUX43_6", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_PMV_SW4A2_6", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_PMV_SE4BEG3_6", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_PMV_SW4END3_6", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_PMV_IMUX0_6", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_PMV_IMUX47_6", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_PMV_NW4A3_6", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_PMV_NW4END0_6", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_PMV_EE4A1_6", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_PMV_SE4C0_6", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_PMV_EL1BEG1_6", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_PMV_IMUX2_6", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_PMV_SW2A1_6", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_PMV_IMUX5_6", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_PMV_BYP1_6", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_PMV_FAN1_6", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_PMV_WW2A2_6", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_PMV_SW4A1_6", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_PMV_WW2A0_6", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_PMV_IMUX25_6", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_PMV_WW2A1_6", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_PMV_IMUX22_6", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_PMV_WW4A3_6", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_PMV_WW2A3_6", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_PMV_WR1END3_6", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_PMV_FAN7_6", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_PMV_BYP7_6", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_PMV_IMUX45_6", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_PMV_SE4BEG1_6", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_PMV_CLK0_6", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_PMV_IMUX44_6", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_PMV_EE2BEG0_6", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_PMV_LH10_6", + "INT_INTERFACE_LH10" + ], + [ + "CLK_PMV_EE4B2_6", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_PMV_SW4A3_6", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_PMV_SW4END0_6", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_PMV_WW4C1_6", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_PMV_IMUX29_6", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_PMV_WW2END0_6", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_PMV_NW2A2_6", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_PMV_WW4C2_6", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_PMV_NE4C2_6", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_PMV_LH3_6", + "INT_INTERFACE_LH3" + ], + [ + "CLK_PMV_NW2A1_6", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_PMV_IMUX24_6", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_PMV_IMUX14_6", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_PMV_NW4END1_6", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_PMV_EE4A3_6", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_PMV_IMUX37_6", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_PMV_IMUX3_6", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_PMV_WR1END2_6", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_PMV_WW4END2_6", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_PMV_IMUX21_6", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_PMV_FAN6_6", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_PMV_IMUX17_6", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_PMV_IMUX11_6", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_PMV_FAN3_6", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_PMV_WW4B2_6", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_PMV_LH6_6", + "INT_INTERFACE_LH6" + ], + [ + "CLK_PMV_NE2A1_6", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_PMV_IMUX12_6", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_PMV_NE4C0_6", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_PMV_ER1BEG0_6", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_PMV_IMUX28_6", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_PMV_FAN4_6", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_PMV_IMUX42_6", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_PMV_IMUX13_6", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_PMV_LH4_6", + "INT_INTERFACE_LH4" + ], + [ + "CLK_PMV_IMUX7_6", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_PMV_NE4C3_6", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_PMV_WW4A1_6", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_PMV_WW2END1_6", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_PMV_BYP0_6", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_PMV_IMUX8_6", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_PMV_EE4B0_6", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_PMV_EE4B1_6", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_PMV_CLK1_6", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_PMV_NW2A3_6", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_PMV_EE2BEG3_6", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_PMV_SW4END2_6", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_PMV_EL1BEG3_6", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_PMV_WW2END3_6", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_PMV_IMUX31_6", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_PMV_CTRL1_6", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_PMV_NE4BEG2_6", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_PMV_EE4B3_6", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_PMV_WW4B1_6", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_PMV_CTRL0_6", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_PMV_EE2A0_6", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_PMV_MONITOR_P_6", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_PMV_WL1END2_6", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_PMV_EE4BEG2_6", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_PMV_SE2A2_6", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_PMV_SE4C1_6", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_PMV_EE2A3_6", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_PMV_IMUX30_6", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_PMV_FAN0_6", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_PMV_BYP5_6", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_PMV_MONITOR_N_6", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_PMV_IMUX19_6", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_PMV_SE2A3_6", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_PMV_NE4BEG0_6", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_PMV_WW2END2_6", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_PMV_IMUX26_6", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_PMV_SW4END1_6", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_PMV_IMUX16_6", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_PMV_NW4A2_6", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_PMV_SW2A0_6", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_PMV_EE4C1_6", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_PMV_FAN2_6", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_PMV_BYP2_6", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_PMV_BYP3_6", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_PMV_SW4A0_6", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_PMV_EE2BEG2_6", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_PMV_SE2A1_6", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_PMV_LH8_6", + "INT_INTERFACE_LH8" + ], + [ + "CLK_PMV_EE4C0_6", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_PMV_IMUX15_6", + "INT_INTERFACE_IMUX15" + ] + ], + "tile_types": [ + "CLK_PMV", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -7 + ], + "wire_pairs": [ + [ + "CFG_CENTER_LH11_17", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_WW2END1_17", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_SW2A2_17", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_SW2A1_17", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_IMUX25_17", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_SW2A0_17", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_BYP3_17", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_FAN2_17", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_SW4A0_17", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_LH2_17", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX30_17", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_BYP0_17", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_WW4B1_17", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_IMUX44_17", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_EL1BEG0_17", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_IMUX27_17", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_EE2A2_17", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_IMUX35_17", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_SE2A3_17", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_FAN7_17", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_FAN6_17", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_WW4A1_17", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_WW4B2_17", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_IMUX1_17", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_WW4C0_17", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX38_17", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_NW4A3_17", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_ER1BEG0_17", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_LH9_17", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EE4A3_17", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_SE4C0_17", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_IMUX4_17", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_NW2A0_17", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_FAN3_17", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_WW4END1_17", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_EE4C1_17", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_NW4END2_17", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_EL1BEG2_17", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX9_17", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_BYP4_17", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_SE4BEG0_17", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_EE2A3_17", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_WR1END3_17", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_CLK1_17", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_WW4B0_17", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_IMUX33_17", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_FAN4_17", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_EE4BEG0_17", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_FAN1_17", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_NE4C1_17", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_IMUX42_17", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX47_17", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_WR1END1_17", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NW2A3_17", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_SE4C1_17", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX28_17", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_SE2A0_17", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_SW4A1_17", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_EE4C2_17", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_WW4END2_17", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX40_17", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_ER1BEG2_17", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX13_17", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_EE4A1_17", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_WL1END0_17", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_FAN0_17", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX21_17", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_FAN5_17", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_WW4A2_17", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_WW2END2_17", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_IMUX17_17", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX29_17", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX20_17", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SW4A3_17", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_NW4END0_17", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_EE4BEG1_17", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_WL1END1_17", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_SW2A3_17", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_NE4BEG0_17", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX16_17", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX45_17", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_EE4B1_17", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_BYP5_17", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_NE4BEG1_17", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX10_17", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_IMUX2_17", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_IMUX0_17", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_NE2A1_17", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_EL1BEG1_17", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_NE4C3_17", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_SW4END1_17", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_WW4END3_17", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_NW4A1_17", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SE4BEG3_17", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_WW2A2_17", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_EE2BEG0_17", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_EE4B2_17", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_SE4C2_17", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_IMUX46_17", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW4C1_17", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_BYP2_17", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_NW2A1_17", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_IMUX6_17", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX11_17", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX39_17", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_IMUX14_17", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_LH10_17", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WR1END0_17", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EE4A2_17", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX26_17", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX24_17", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_NE4BEG3_17", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_WW4C3_17", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_ER1BEG3_17", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_IMUX41_17", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX36_17", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW4END0_17", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX18_17", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_WW2END3_17", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW4END0_17", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_CTRL1_17", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_NW4END3_17", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_EE2BEG3_17", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_SE2A2_17", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_SW4END3_17", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_EE2BEG2_17", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_NW4A2_17", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_IMUX31_17", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_IMUX19_17", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_EE4B0_17", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WW2END0_17", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WR1END2_17", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_IMUX34_17", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_IMUX22_17", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_LH6_17", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_BYP1_17", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW2A1_17", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_EE2A1_17", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_NE4C0_17", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_SW4END2_17", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_NE4C2_17", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_EE2BEG1_17", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_NW2A2_17", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_EE4C0_17", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_WL1END2_17", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_LH1_17", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NE2A2_17", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_LH8_17", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_IMUX15_17", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_SE4BEG1_17", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_BYP7_17", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_LH7_17", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_EE2A0_17", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_LH5_17", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_EL1BEG3_17", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_SE4BEG2_17", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_CTRL0_17", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_EE4BEG3_17", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_WW4A3_17", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW2A0_17", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_IMUX8_17", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW4A0_17", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_SE2A1_17", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NE2A3_17", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX37_17", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SW4A2_17", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_EE4B3_17", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_NE4BEG2_17", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WL1END3_17", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_LH12_17", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX3_17", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_IMUX7_17", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_ER1BEG1_17", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_NE2A0_17", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX5_17", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_NW4END1_17", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_BYP6_17", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_EE4C3_17", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_WW4B3_17", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_NW4A0_17", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_EE4A0_17", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_IMUX32_17", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_CLK0_17", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX23_17", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_SE4C3_17", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_WW4C2_17", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WW2A3_17", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX43_17", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_LH4_17", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_IMUX12_17", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_LH3_17", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_EE4BEG2_17", + "VFRAME_EE4BEG2" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + -6 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE2A3_6", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NE4C2_6", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_LH4_6", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_WW2END3_6", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_LH8_6", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW2A0_6", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_EE4A1_6", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NW4A1_6", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SE2A1_6", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WL1END3_6", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4A2_6", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_WW4B3_6", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_LH3_6", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_EE2A1_6", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_SW2A2_6", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WR1END2_6", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_SW2A3_6", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NE4BEG3_6", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW2END2_6", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SE4BEG2_6", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW2END1_6", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_NW4END3_6", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_ER1BEG1_6", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SW4END1_6", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EL1BEG2_6", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_EL1BEG3_6", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WW4A2_6", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE4BEG1_6", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_NW4END0_6", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_EE2BEG0_6", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WL1END2_6", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SW4END3_6", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NE2A3_6", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_EE4BEG0_6", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NE4BEG0_6", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NW4END2_6", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4C1_6", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_WR1END1_6", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SW4A3_6", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE4A0_6", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4BEG3_6", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG0_6", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_NW2A1_6", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SE4C3_6", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_LH6_6", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_LH12_6", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WR1END3_6", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_WW4B0_6", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_EE4C0_6", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EL1BEG1_6", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW4A0_6", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_LH7_6", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_EE4C2_6", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_WW2A2_6", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WW4C0_6", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NW4A2_6", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_LH5_6", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_SW2A1_6", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_NW4A0_6", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_ER1BEG0_6", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_WW2END0_6", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_SW4END2_6", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_LH9_6", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NE4C1_6", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE2A2_6", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_SE4C2_6", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_NE2A1_6", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NW2A2_6", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_SW4A1_6", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_EE4B0_6", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WW4A3_6", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_WW4A1_6", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_ER1BEG3_6", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_EE4BEG2_6", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_NW2A0_6", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WW4END2_6", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_EE4C3_6", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW4C3_6", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WR1END0_6", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_WW4B1_6", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_LH10_6", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WL1END1_6", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_EE4B3_6", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NE2A0_6", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_NW4A3_6", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WW4END0_6", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WL1END0_6", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_NE4C0_6", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_SW2A0_6", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_SE4BEG1_6", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG3_6", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_NW4END1_6", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_EE2A2_6", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_SE4C1_6", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_ER1BEG2_6", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_NE4C3_6", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_LH11_6", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_SE4BEG0_6", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_WW4END1_6", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE4B2_6", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE2BEG3_6", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_WW4B2_6", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_SE2A3_6", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SW4A2_6", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_EE4A3_6", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_NE4BEG2_6", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_LH1_6", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_EE2BEG2_6", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_SE2A0_6", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE4C1_6", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE2A0_6", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW2A3_6", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_SE2A2_6", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4B1_6", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NE4BEG1_6", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WW4C2_6", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_SE4C0_6", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_EE2BEG1_6", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NW2A3_6", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_LH2_6", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_SW4END0_6", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WW4END3_6", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW2A1_6", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_SW4A0_6", + "INT_FEEDTHRU_2_SW4A0" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX27_5", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX13_5", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_LOGIC_OUTS_B4_5", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B22_5", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX30_5", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_LOGIC_OUTS_B14_5", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX0_5", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_BYP4_5", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX18_5", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_LOGIC_OUTS_B8_5", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX16_5", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX42_5", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX46_5", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX11_5", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX6_5", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B9_5", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX7_5", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX45_5", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_BYP0_5", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX38_5", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX33_5", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_LOGIC_OUTS_B11_5", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_BYP2_5", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX23_5", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_LOGIC_OUTS_B6_5", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_LOGIC_OUTS_B2_5", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX41_5", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B5_5", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX12_5", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX14_5", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX22_5", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_CLK0_5", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX43_5", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX37_5", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX9_5", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX29_5", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_BYP1_5", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_CTRL1_5", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_CLK1_5", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_CTRL0_5", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX28_5", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX32_5", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX17_5", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_FAN6_5", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_BYP5_5", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B7_5", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B17_5", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX1_5", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX26_5", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_FAN0_5", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX8_5", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_LOGIC_OUTS_B16_5", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX4_5", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_BYP7_5", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B3_5", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX39_5", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX35_5", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_LOGIC_OUTS_B18_5", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_LOGIC_OUTS_B12_5", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX19_5", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_FAN7_5", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B13_5", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B23_5", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_LOGIC_OUTS_B0_5", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX36_5", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX2_5", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX40_5", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_FAN3_5", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX3_5", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX10_5", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_FAN5_5", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX34_5", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX20_5", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN4_5", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX24_5", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B10_5", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_BYP3_5", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B15_5", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX31_5", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_FAN1_5", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_FAN2_5", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_LOGIC_OUTS_B20_5", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX5_5", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_BYP6_5", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX47_5", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX15_5", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX25_5", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX21_5", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX44_5", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_LOGIC_OUTS_B19_5", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B1_5", + "VBRK_EXT_LOGIC_OUTS_B1" + ] + ], + "tile_types": [ + "GTX_CHANNEL_3", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + 4 + ], + "wire_pairs": [ + [ + "CFG_CENTER_IMUX3_6", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_WW4B0_6", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_EE4BEG1_6", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_NW2A2_6", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_FAN7_6", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_BYP0_6", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX38_6", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_SW4A2_6", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_BYP6_6", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_NE4C3_6", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_IMUX24_6", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_NW4A0_6", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_WW4A2_6", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_WW2A0_6", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_LH6_6", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX18_6", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX1_6", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_SW2A2_6", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_NW4END0_6", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_EE2A1_6", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_WR1END0_6", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_SE4BEG0_6", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_SW4END3_6", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_BYP1_6", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_NW2A1_6", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_IMUX19_6", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_6", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_IMUX36_6", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_WL1END0_6", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_NW4A1_6", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_6", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_6", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_LH2_6", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EE4BEG3_6", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_EE4B0_6", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_IMUX45_6", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX37_6", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SW2A3_6", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_6", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_BYP2_6", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_EL1BEG0_6", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_FAN1_6", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_LH10_6", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW4END1_6", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_NW4END2_6", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_WW4B3_6", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_LH5_6", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_BYP5_6", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_SE2A2_6", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX17_6", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_6", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_IMUX4_6", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX2_6", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_FAN3_6", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_IMUX27_6", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_6", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_LH7_6", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_SW4A1_6", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_FAN0_6", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_EE4A0_6", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_IMUX9_6", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX13_6", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_SW2A1_6", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_ER1BEG0_6", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_LH12_6", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_WW4C3_6", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX5_6", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX42_6", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_WR1END3_6", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX41_6", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX32_6", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_WW2END3_6", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_IMUX35_6", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_CLK1_6", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX16_6", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WW4A1_6", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_EE4C3_6", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_SE4C2_6", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_SW4END2_6", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_EE2BEG3_6", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX28_6", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_EE4A1_6", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_NE4BEG2_6", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_FAN5_6", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_CLK0_6", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_FAN4_6", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW4C2_6", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_BYP4_6", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_EE4BEG0_6", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_FAN2_6", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_NE4BEG1_6", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX8_6", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_SE4BEG3_6", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX29_6", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B9_6", + "VFRAME_LOGIC_OUTS_B9" + ], + [ + "CFG_CENTER_EE2A2_6", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_6", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_SE4BEG1_6", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_BYP3_6", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_SW4END0_6", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_EE4C0_6", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_EE4C2_6", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_WW2END1_6", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_EE4B2_6", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_LH1_6", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_IMUX23_6", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW4A0_6", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B8_6", + "VFRAME_LOGIC_OUTS_B8" + ], + [ + "CFG_CENTER_IMUX20_6", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_IMUX7_6", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_SW4END1_6", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_EE2A0_6", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_SE4C3_6", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_WW4END3_6", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX39_6", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_IMUX31_6", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_EE4A2_6", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX44_6", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WW2END2_6", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_EE2BEG2_6", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX30_6", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_EE2BEG1_6", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX15_6", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_6", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_CTRL0_6", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_EL1BEG3_6", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_IMUX11_6", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_WW2A2_6", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_WW4C1_6", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_LH8_6", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_NE4BEG3_6", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NE4C2_6", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_IMUX47_6", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_NW4A2_6", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_IMUX21_6", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_SE4C1_6", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_EE4B1_6", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_6", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_WW2A1_6", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_IMUX12_6", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_ER1BEG1_6", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_WW4B1_6", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_NW4END1_6", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_NE4BEG0_6", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_EE4C1_6", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_WR1END2_6", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_IMUX46_6", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_IMUX0_6", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WL1END2_6", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_LH3_6", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_SW2A0_6", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_SE4C0_6", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_NW2A0_6", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_NW4A3_6", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_LH9_6", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_IMUX14_6", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_SW4A3_6", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_LH11_6", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_IMUX34_6", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_FAN6_6", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX26_6", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX25_6", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_NE2A3_6", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_EL1BEG2_6", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_SW4A0_6", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_CTRL1_6", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_NE2A2_6", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WL1END3_6", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_ER1BEG3_6", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_NE4C1_6", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_IMUX22_6", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW4END2_6", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_WR1END1_6", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B11_6", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "CFG_CENTER_NW4END3_6", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_WW4B2_6", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_IMUX6_6", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_NE2A0_6", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX40_6", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_ER1BEG2_6", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_6", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_SE2A0_6", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_IMUX10_6", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_EE4A3_6", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_EE2A3_6", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NW2A3_6", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NE4C0_6", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_WL1END1_6", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_EE4BEG2_6", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE4B3_6", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_SE4BEG2_6", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_WW2END0_6", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_6", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_SE2A3_6", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_EE2BEG0_6", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_SE2A1_6", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_EL1BEG1_6", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_WW4END0_6", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_6", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_IMUX33_6", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_BYP7_6", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_WW4C0_6", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_NE2A1_6", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_WW2A3_6", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_WW4A3_6", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B10_6", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "CFG_CENTER_IMUX43_6", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_LH4_6", + "VFRAME_LH4" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "CMT_TOP_LH12_7", + "VBRK_LH12" + ], + [ + "CMT_TOP_SW4END1_7", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_7", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE4C2_7", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_ER1BEG3_7", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END1_7", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WL1END2_7", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_NW4A0_7", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WR1END2_7", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW4A2_7", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG3_7", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EL1BEG0_7", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH11_7", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW2END2_7", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4A1_7", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NE2A1_7", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SW2A2_7", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_ER1BEG0_7", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_7", + "VBRK_LH1" + ], + [ + "CMT_TOP_SW4A3_7", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH10_7", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4BEG3_7", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C3_7", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4END3_7", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_ER1BEG1_7", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_7", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW2END0_7", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END2_7", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NE4C0_7", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EL1BEG1_7", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4END0_7", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EE2BEG3_7", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4C1_7", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A2_7", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_7", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE2A3_7", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4A1_7", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_LH2_7", + "VBRK_LH2" + ], + [ + "CMT_TOP_EL1BEG2_7", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WL1END0_7", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4C1_7", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW2END1_7", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2BEG0_7", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4B0_7", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C2_7", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A0_7", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_7", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_MONITOR_P_7", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_EE4B2_7", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG2_7", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A0_7", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG0_7", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW4A1_7", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_SE2A1_7", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4END2_7", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE2A3_7", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW4C0_7", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_7", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE4BEG2_7", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_SE4C0_7", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_ER1BEG2_7", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NE2A0_7", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4A3_7", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4BEG2_7", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_7", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4B3_7", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END3_7", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WW4C1_7", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WL1END3_7", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH9_7", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2A0_7", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG1_7", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_7", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_LH3_7", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_7", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE4BEG1_7", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EE4A2_7", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG0_7", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE4BEG2_7", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW4END3_7", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NE4BEG1_7", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A2_7", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NW4END0_7", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_7", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4A0_7", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END0_7", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_7", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW4END1_7", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH7_7", + "VBRK_LH7" + ], + [ + "CMT_TOP_SE4BEG1_7", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE4A3_7", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C2_7", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A3_7", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW2A1_7", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C3_7", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE2A2_7", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NE4C3_7", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE4C0_7", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WR1END1_7", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A2_7", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_NW4END3_7", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_WW4B1_7", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C1_7", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_7", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE2A1_7", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_7", + "VBRK_LH5" + ], + [ + "CMT_TOP_SE4C2_7", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B0_7", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE2A0_7", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW4A1_7", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SW2A0_7", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW2A3_7", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW2A0_7", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_7", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EL1BEG3_7", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_NW4A2_7", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG3_7", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NW2A3_7", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW4C3_7", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_7", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_LH4_7", + "VBRK_LH4" + ], + [ + "CMT_TOP_LH8_7", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B3_7", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_MONITOR_N_7", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_EE4BEG0_7", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2A3_7", + "VBRK_EE2A3" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "wire_pairs": [ + [ + "IOI_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2_1" + ], + [ + "IOI_IMUX_RC0", + "IOI_IMUX_RC2" + ], + [ + "IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_LEAF_GCLK3" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_LEAF_GCLK1" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_LEAF_GCLK0" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_RCLK_FORIO1" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_RCLK_FORIO0" + ], + [ + "IOI_TBYTEIN", + "IOI_TBYTEIN" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_RCLK_FORIO3" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_RCLK_FORIO2" + ], + [ + "IOI_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3_1" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_LEAF_GCLK5" + ], + [ + "IOI_IMUX_RC1", + "IOI_IMUX_RC3" + ], + [ + "IOI_RCLK_DIV_CLR1_1", + "IOI_RCLK_DIV_CLR1" + ], + [ + "IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "IOI_RCLK_DIV_CLR0_1", + "IOI_RCLK_DIV_CLR0" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_LEAF_GCLK4" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_LEAF_GCLK2" + ] + ], + "tile_types": [ + "LIOI3", + "LIOI3_TBYTESRC" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_IMUX11_9", + "CMT_TOP_IMUX11_6" + ], + [ + "CMT_FIFO_SE2A3_6", + "CMT_TOP_SE2A3_3" + ], + [ + "CMT_FIFO_SW2A2_11", + "CMT_TOP_SW2A2_8" + ], + [ + "CMT_FIFO_ER1BEG2_6", + "CMT_TOP_ER1BEG2_3" + ], + [ + "CMT_FIFO_WR1END0_6", + "CMT_TOP_WR1END0_3" + ], + [ + "CMT_FIFO_NE4BEG2_9", + "CMT_TOP_NE4BEG2_6" + ], + [ + "CMT_FIFO_SE2A3_8", + "CMT_TOP_SE2A3_5" + ], + [ + "CMT_FIFO_WR1END0_10", + "CMT_TOP_WR1END0_7" + ], + [ + "CMT_FIFO_SE4C1_9", + "CMT_TOP_SE4C1_6" + ], + [ + "CMT_FIFO_NW4A0_11", + "CMT_TOP_NW4A0_8" + ], + [ + "CMT_FIFO_NW4END2_5", + "CMT_TOP_NW4END2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_4", + "CMT_TOP_LOGIC_OUTS_L_B1_1" + ], + [ + "CMT_FIFO_EE2A1_8", + "CMT_TOP_EE2A1_5" + ], + [ + "CMT_FIFO_EE2BEG3_10", + "CMT_TOP_EE2BEG3_7" + ], + [ + "CMT_FIFO_NE4BEG2_4", + "CMT_TOP_NE4BEG2_1" + ], + [ + "CMT_FIFO_L_IMUX31_6", + "CMT_TOP_IMUX31_3" + ], + [ + "CMT_FIFO_NW4END3_11", + "CMT_TOP_NW4END3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_10", + "CMT_TOP_LOGIC_OUTS_L_B14_7" + ], + [ + "CMT_FIFO_L_IMUX2_9", + "CMT_TOP_IMUX2_6" + ], + [ + "CMT_FIFO_L_FAN2_5", + "CMT_TOP_FAN2_2" + ], + [ + "CMT_FIFO_L_BYP4_4", + "CMT_TOP_BYP4_1" + ], + [ + "CMT_FIFO_WW2END3_5", + "CMT_TOP_WW2END3_2" + ], + [ + "CMT_FIFO_LH11_5", + "CMT_TOP_LH11_2" + ], + [ + "CMT_FIFO_L_IMUX6_8", + "CMT_TOP_IMUX6_5" + ], + [ + "CMT_FIFO_SE4BEG0_4", + "CMT_TOP_SE4BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_9", + "CMT_TOP_LOGIC_OUTS_L_B22_6" + ], + [ + "CMT_FIFO_LH1_4", + "CMT_TOP_LH1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_3", + "CMT_TOP_LOGIC_OUTS_L_B18_0" + ], + [ + "CMT_FIFO_SW4A0_9", + "CMT_TOP_SW4A0_6" + ], + [ + "CMT_FIFO_L_IMUX40_11", + "CMT_TOP_IMUX40_8" + ], + [ + "CMT_FIFO_L_IMUX9_11", + "CMT_TOP_IMUX9_8" + ], + [ + "CMT_FIFO_EE2A1_9", + "CMT_TOP_EE2A1_6" + ], + [ + "CMT_FIFO_WW4END1_8", + "CMT_TOP_WW4END1_5" + ], + [ + "CMT_FIFO_NW2A3_4", + "CMT_TOP_NW2A3_1" + ], + [ + "CMT_FIFO_SW2A1_4", + "CMT_TOP_SW2A1_1" + ], + [ + "CMT_FIFO_WR1END1_10", + "CMT_TOP_WR1END1_7" + ], + [ + "CMT_FIFO_L_IMUX29_8", + "CMT_TOP_IMUX29_5" + ], + [ + "CMT_FIFO_WW4B0_4", + "CMT_TOP_WW4B0_1" + ], + [ + "CMT_FIFO_L_IMUX14_3", + "CMT_TOP_IMUX14_0" + ], + [ + "CMT_FIFO_L_FAN4_4", + "CMT_TOP_FAN4_1" + ], + [ + "CMT_FIFO_L_IMUX12_3", + "CMT_TOP_IMUX12_0" + ], + [ + "CMT_FIFO_SE4C1_7", + "CMT_TOP_SE4C1_4" + ], + [ + "CMT_FIFO_L_IMUX41_7", + "CMT_TOP_IMUX41_4" + ], + [ + "CMT_FIFO_EE4B2_3", + "CMT_TOP_EE4B2_0" + ], + [ + "CMT_FIFO_SW4A0_10", + "CMT_TOP_SW4A0_7" + ], + [ + "CMT_FIFO_NE4BEG2_7", + "CMT_TOP_NE4BEG2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_11", + "CMT_TOP_LOGIC_OUTS_L_B1_8" + ], + [ + "CMT_FIFO_LH4_10", + "CMT_TOP_LH4_7" + ], + [ + "CMT_FIFO_EE2A3_9", + "CMT_TOP_EE2A3_6" + ], + [ + "CMT_FIFO_SE4BEG3_5", + "CMT_TOP_SE4BEG3_2" + ], + [ + "CMT_FIFO_NW4A0_5", + "CMT_TOP_NW4A0_2" + ], + [ + "CMT_FIFO_WW4A2_11", + "CMT_TOP_WW4A2_8" + ], + [ + "CMT_FIFO_WW4B0_9", + "CMT_TOP_WW4B0_6" + ], + [ + "CMT_FIFO_EE4BEG0_4", + "CMT_TOP_EE4BEG0_1" + ], + [ + "CMT_FIFO_EL1BEG1_4", + "CMT_TOP_EL1BEG1_1" + ], + [ + "CMT_FIFO_MONITOR_N_6", + "CMT_TOP_MONITOR_N_3" + ], + [ + "CMT_FIFO_L_IMUX27_7", + "CMT_TOP_IMUX27_4" + ], + [ + "CMT_FIFO_SE4C2_10", + "CMT_TOP_SE4C2_7" + ], + [ + "CMT_FIFO_L_IMUX17_9", + "CMT_TOP_IMUX17_6" + ], + [ + "CMT_FIFO_EE4C2_7", + "CMT_TOP_EE4C2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_6", + "CMT_TOP_LOGIC_OUTS_L_B7_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_8", + "CMT_TOP_LOGIC_OUTS_L_B7_5" + ], + [ + "CMT_FIFO_WL1END0_10", + "CMT_TOP_WL1END0_7" + ], + [ + "CMT_FIFO_EE2BEG2_3", + "CMT_TOP_EE2BEG2_0" + ], + [ + "CMT_FIFO_WW4B0_10", + "CMT_TOP_WW4B0_7" + ], + [ + "CMT_FIFO_L_IMUX24_3", + "CMT_TOP_IMUX24_0" + ], + [ + "CMT_FIFO_NE4BEG2_8", + "CMT_TOP_NE4BEG2_5" + ], + [ + "CMT_FIFO_EE2A0_9", + "CMT_TOP_EE2A0_6" + ], + [ + "CMT_FIFO_L_IMUX22_8", + "CMT_TOP_IMUX22_5" + ], + [ + "CMT_FIFO_EE2A3_10", + "CMT_TOP_EE2A3_7" + ], + [ + "CMT_FIFO_WW4B0_8", + "CMT_TOP_WW4B0_5" + ], + [ + "CMT_FIFO_LH11_4", + "CMT_TOP_LH11_1" + ], + [ + "CMT_FIFO_SE4C0_3", + "CMT_TOP_SE4C0_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "CMT_TOP_ICLK_4" + ], + [ + "CMT_FIFO_L_BYP2_10", + "CMT_TOP_BYP2_7" + ], + [ + "CMT_FIFO_L_IMUX39_4", + "CMT_TOP_IMUX39_1" + ], + [ + "CMT_FIFO_WW4C3_10", + "CMT_TOP_WW4C3_7" + ], + [ + "CMT_FIFO_SE2A1_8", + "CMT_TOP_SE2A1_5" + ], + [ + "CMT_FIFO_L_BYP3_7", + "CMT_TOP_BYP3_4" + ], + [ + "CMT_FIFO_L_BYP7_5", + "CMT_TOP_BYP7_2" + ], + [ + "CMT_FIFO_EE4BEG3_6", + "CMT_TOP_EE4BEG3_3" + ], + [ + "CMT_FIFO_L_IMUX14_6", + "CMT_TOP_IMUX14_3" + ], + [ + "CMT_FIFO_WW2END2_6", + "CMT_TOP_WW2END2_3" + ], + [ + "CMT_FIFO_L_BYP2_8", + "CMT_TOP_BYP2_5" + ], + [ + "CMT_FIFO_WR1END3_4", + "CMT_TOP_WR1END3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_9", + "CMT_TOP_LOGIC_OUTS_L_B1_6" + ], + [ + "CMT_FIFO_NE4BEG3_6", + "CMT_TOP_NE4BEG3_3" + ], + [ + "CMT_FIFO_EE2A2_11", + "CMT_TOP_EE2A2_8" + ], + [ + "CMT_FIFO_WW2END2_9", + "CMT_TOP_WW2END2_6" + ], + [ + "CMT_FIFO_L_IMUX40_4", + "CMT_TOP_IMUX40_1" + ], + [ + "CMT_FIFO_SE4BEG0_8", + "CMT_TOP_SE4BEG0_5" + ], + [ + "CMT_FIFO_L_IMUX7_6", + "CMT_TOP_IMUX7_3" + ], + [ + "CMT_FIFO_NW4A1_10", + "CMT_TOP_NW4A1_7" + ], + [ + "CMT_FIFO_EE4B3_4", + "CMT_TOP_EE4B3_1" + ], + [ + "CMT_FIFO_MONITOR_N_8", + "CMT_TOP_MONITOR_N_5" + ], + [ + "CMT_FIFO_L_FAN3_10", + "CMT_TOP_FAN3_7" + ], + [ + "CMT_FIFO_NE4C2_5", + "CMT_TOP_NE4C2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_11", + "CMT_TOP_LOGIC_OUTS_L_B20_8" + ], + [ + "CMT_FIFO_L_IMUX34_8", + "CMT_TOP_IMUX34_5" + ], + [ + "CMT_FIFO_WL1END3_5", + "CMT_TOP_WL1END3_2" + ], + [ + "CMT_FIFO_EE4BEG3_5", + "CMT_TOP_EE4BEG3_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "CMT_TOP_ICLKDIV_2" + ], + [ + "CMT_FIFO_EE2A0_7", + "CMT_TOP_EE2A0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_9", + "CMT_TOP_LOGIC_OUTS_L_B0_6" + ], + [ + "CMT_FIFO_WW2A0_3", + "CMT_TOP_WW2A0_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "CMT_TOP_OCLKDIV_4" + ], + [ + "CMT_FIFO_WW4C3_7", + "CMT_TOP_WW4C3_4" + ], + [ + "CMT_FIFO_WW2A3_5", + "CMT_TOP_WW2A3_2" + ], + [ + "CMT_FIFO_L_IMUX16_5", + "CMT_TOP_IMUX16_2" + ], + [ + "CMT_FIFO_NW2A2_10", + "CMT_TOP_NW2A2_7" + ], + [ + "CMT_FIFO_L_IMUX47_9", + "CMT_TOP_IMUX47_6" + ], + [ + "CMT_FIFO_L_CTRL1_6", + "CMT_TOP_CTRL1_3" + ], + [ + "CMT_FIFO_EE2BEG1_5", + "CMT_TOP_EE2BEG1_2" + ], + [ + "CMT_FIFO_EE2A2_6", + "CMT_TOP_EE2A2_3" + ], + [ + "CMT_FIFO_NE4C2_3", + "CMT_TOP_NE4C2_0" + ], + [ + "CMT_FIFO_SE4C2_9", + "CMT_TOP_SE4C2_6" + ], + [ + "CMT_FIFO_NE4BEG2_3", + "CMT_TOP_NE4BEG2_0" + ], + [ + "CMT_FIFO_EE2A0_6", + "CMT_TOP_EE2A0_3" + ], + [ + "CMT_FIFO_WW2END2_5", + "CMT_TOP_WW2END2_2" + ], + [ + "CMT_FIFO_WW4B2_4", + "CMT_TOP_WW4B2_1" + ], + [ + "CMT_FIFO_LH6_9", + "CMT_TOP_LH6_6" + ], + [ + "CMT_FIFO_L_IMUX27_9", + "CMT_TOP_IMUX27_6" + ], + [ + "CMT_FIFO_ER1BEG3_9", + "CMT_TOP_ER1BEG3_6" + ], + [ + "CMT_FIFO_WL1END2_4", + "CMT_TOP_WL1END2_1" + ], + [ + "CMT_FIFO_WW4A3_8", + "CMT_TOP_WW4A3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_7" + ], + [ + "CMT_FIFO_EE2BEG3_9", + "CMT_TOP_EE2BEG3_6" + ], + [ + "CMT_FIFO_L_BYP1_7", + "CMT_TOP_BYP1_4" + ], + [ + "CMT_FIFO_L_IMUX0_5", + "CMT_TOP_IMUX0_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "CMT_TOP_OCLKDIV_6" + ], + [ + "CMT_FIFO_EE4BEG2_9", + "CMT_TOP_EE4BEG2_6" + ], + [ + "CMT_FIFO_NE4BEG3_11", + "CMT_TOP_NE4BEG3_8" + ], + [ + "CMT_FIFO_LH10_10", + "CMT_TOP_LH10_7" + ], + [ + "CMT_FIFO_L_IMUX18_6", + "CMT_TOP_IMUX18_3" + ], + [ + "CMT_FIFO_L_IMUX10_9", + "CMT_TOP_IMUX10_6" + ], + [ + "CMT_FIFO_LH11_7", + "CMT_TOP_LH11_4" + ], + [ + "CMT_FIFO_LH7_6", + "CMT_TOP_LH7_3" + ], + [ + "CMT_FIFO_WW4C2_5", + "CMT_TOP_WW4C2_2" + ], + [ + "CMT_FIFO_EE2BEG1_9", + "CMT_TOP_EE2BEG1_6" + ], + [ + "CMT_FIFO_WW4A0_8", + "CMT_TOP_WW4A0_5" + ], + [ + "CMT_FIFO_WW4C2_4", + "CMT_TOP_WW4C2_1" + ], + [ + "CMT_FIFO_L_CLK1_8", + "CMT_TOP_CLK1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_10", + "CMT_TOP_LOGIC_OUTS_L_B5_7" + ], + [ + "CMT_FIFO_L_IMUX21_3", + "CMT_TOP_IMUX21_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_9", + "CMT_TOP_LOGIC_OUTS_L_B4_6" + ], + [ + "CMT_FIFO_WL1END0_9", + "CMT_TOP_WL1END0_6" + ], + [ + "CMT_FIFO_L_BYP7_11", + "CMT_TOP_BYP7_8" + ], + [ + "CMT_FIFO_EL1BEG3_11", + "CMT_TOP_EL1BEG3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_6", + "CMT_TOP_LOGIC_OUTS_L_B4_3" + ], + [ + "CMT_FIFO_L_IMUX38_8", + "CMT_TOP_IMUX38_5" + ], + [ + "CMT_FIFO_WL1END3_3", + "CMT_TOP_WL1END3_0" + ], + [ + "CMT_FIFO_EE4C0_4", + "CMT_TOP_EE4C0_1" + ], + [ + "CMT_FIFO_L_FAN3_6", + "CMT_TOP_FAN3_3" + ], + [ + "CMT_FIFO_EL1BEG2_5", + "CMT_TOP_EL1BEG2_2" + ], + [ + "CMT_FIFO_NW2A0_5", + "CMT_TOP_NW2A0_2" + ], + [ + "CMT_FIFO_EE4BEG2_5", + "CMT_TOP_EE4BEG2_2" + ], + [ + "CMT_FIFO_EE2A1_3", + "CMT_TOP_EE2A1_0" + ], + [ + "CMT_FIFO_WW4END3_4", + "CMT_TOP_WW4END3_1" + ], + [ + "CMT_FIFO_L_IMUX6_4", + "CMT_TOP_IMUX6_1" + ], + [ + "CMT_FIFO_NE4BEG0_9", + "CMT_TOP_NE4BEG0_6" + ], + [ + "CMT_FIFO_L_IMUX24_9", + "CMT_TOP_IMUX24_6" + ], + [ + "CMT_FIFO_L_FAN5_4", + "CMT_TOP_FAN5_1" + ], + [ + "CMT_FIFO_NW4A3_6", + "CMT_TOP_NW4A3_3" + ], + [ + "CMT_FIFO_EE4BEG1_9", + "CMT_TOP_EE4BEG1_6" + ], + [ + "CMT_FIFO_L_IMUX12_9", + "CMT_TOP_IMUX12_6" + ], + [ + "CMT_FIFO_WW4B1_6", + "CMT_TOP_WW4B1_3" + ], + [ + "CMT_FIFO_NW4A3_4", + "CMT_TOP_NW4A3_1" + ], + [ + "CMT_FIFO_L_IMUX7_9", + "CMT_TOP_IMUX7_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_7", + "CMT_TOP_LOGIC_OUTS_L_B5_4" + ], + [ + "CMT_FIFO_EE4B1_5", + "CMT_TOP_EE4B1_2" + ], + [ + "CMT_FIFO_NE4BEG2_11", + "CMT_TOP_NE4BEG2_8" + ], + [ + "CMT_FIFO_WW2A3_9", + "CMT_TOP_WW2A3_6" + ], + [ + "CMT_FIFO_L_IMUX1_9", + "CMT_TOP_IMUX1_6" + ], + [ + "CMT_FIFO_WL1END0_5", + "CMT_TOP_WL1END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_5", + "CMT_TOP_LOGIC_OUTS_L_B6_2" + ], + [ + "CMT_FIFO_LH6_3", + "CMT_TOP_LH6_0" + ], + [ + "CMT_FIFO_NW2A1_8", + "CMT_TOP_NW2A1_5" + ], + [ + "CMT_FIFO_LH2_5", + "CMT_TOP_LH2_2" + ], + [ + "CMT_FIFO_WW2END1_8", + "CMT_TOP_WW2END1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_5", + "CMT_TOP_LOGIC_OUTS_L_B14_2" + ], + [ + "CMT_FIFO_L_BYP3_5", + "CMT_TOP_BYP3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_6", + "CMT_TOP_LOGIC_OUTS_L_B6_3" + ], + [ + "CMT_FIFO_EL1BEG1_6", + "CMT_TOP_EL1BEG1_3" + ], + [ + "CMT_FIFO_NW2A3_5", + "CMT_TOP_NW2A3_2" + ], + [ + "CMT_FIFO_EE4C3_3", + "CMT_TOP_EE4C3_0" + ], + [ + "CMT_FIFO_WW4C1_3", + "CMT_TOP_WW4C1_0" + ], + [ + "CMT_FIFO_L_IMUX44_11", + "CMT_TOP_IMUX44_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_7", + "CMT_TOP_LOGIC_OUTS_L_B3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_7", + "CMT_TOP_LOGIC_OUTS_L_B17_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_4", + "CMT_TOP_LOGIC_OUTS_L_B13_1" + ], + [ + "CMT_FIFO_WW4C1_5", + "CMT_TOP_WW4C1_2" + ], + [ + "CMT_FIFO_WW4C2_8", + "CMT_TOP_WW4C2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_9", + "CMT_TOP_LOGIC_OUTS_L_B19_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_0" + ], + [ + "CMT_FIFO_L_IMUX36_11", + "CMT_TOP_IMUX36_8" + ], + [ + "CMT_FIFO_L_IMUX35_6", + "CMT_TOP_IMUX35_3" + ], + [ + "CMT_FIFO_NE2A1_11", + "CMT_TOP_NE2A1_8" + ], + [ + "CMT_FIFO_WR1END0_8", + "CMT_TOP_WR1END0_5" + ], + [ + "CMT_FIFO_SE2A1_7", + "CMT_TOP_SE2A1_4" + ], + [ + "CMT_FIFO_L_IMUX8_7", + "CMT_TOP_IMUX8_4" + ], + [ + "CMT_FIFO_WR1END3_5", + "CMT_TOP_WR1END3_2" + ], + [ + "CMT_FIFO_L_FAN3_4", + "CMT_TOP_FAN3_1" + ], + [ + "CMT_FIFO_L_IMUX4_7", + "CMT_TOP_IMUX4_4" + ], + [ + "CMT_FIFO_L_IMUX6_11", + "CMT_TOP_IMUX6_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_10", + "CMT_TOP_LOGIC_OUTS_L_B11_7" + ], + [ + "CMT_FIFO_EE4BEG2_3", + "CMT_TOP_EE4BEG2_0" + ], + [ + "CMT_FIFO_L_BYP5_6", + "CMT_TOP_BYP5_3" + ], + [ + "CMT_FIFO_NE2A0_9", + "CMT_TOP_NE2A0_6" + ], + [ + "CMT_FIFO_NE2A3_7", + "CMT_TOP_NE2A3_4" + ], + [ + "CMT_FIFO_NW4A0_3", + "CMT_TOP_NW4A0_0" + ], + [ + "CMT_FIFO_SE4C0_8", + "CMT_TOP_SE4C0_5" + ], + [ + "CMT_FIFO_L_IMUX12_8", + "CMT_TOP_IMUX12_5" + ], + [ + "CMT_FIFO_NE4C2_8", + "CMT_TOP_NE4C2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_8", + "CMT_TOP_LOGIC_OUTS_L_B15_5" + ], + [ + "CMT_FIFO_NE2A0_4", + "CMT_TOP_NE2A0_1" + ], + [ + "CMT_FIFO_LH3_4", + "CMT_TOP_LH3_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "CMT_TOP_ICLK_8" + ], + [ + "CMT_FIFO_WW2END1_7", + "CMT_TOP_WW2END1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_3", + "CMT_TOP_LOGIC_OUTS_L_B5_0" + ], + [ + "CMT_FIFO_WW2A0_7", + "CMT_TOP_WW2A0_4" + ], + [ + "CMT_FIFO_L_IMUX13_9", + "CMT_TOP_IMUX13_6" + ], + [ + "CMT_FIFO_L_IMUX29_5", + "CMT_TOP_IMUX29_2" + ], + [ + "CMT_FIFO_WW4A1_5", + "CMT_TOP_WW4A1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_10", + "CMT_TOP_LOGIC_OUTS_L_B10_7" + ], + [ + "CMT_FIFO_EE4BEG1_3", + "CMT_TOP_EE4BEG1_0" + ], + [ + "CMT_FIFO_WW4B2_9", + "CMT_TOP_WW4B2_6" + ], + [ + "CMT_FIFO_SE4C1_10", + "CMT_TOP_SE4C1_7" + ], + [ + "CMT_FIFO_L_IMUX36_3", + "CMT_TOP_IMUX36_0" + ], + [ + "CMT_FIFO_SE4C3_6", + "CMT_TOP_SE4C3_3" + ], + [ + "CMT_FIFO_L_IMUX47_3", + "CMT_TOP_IMUX47_0" + ], + [ + "CMT_FIFO_NE2A3_8", + "CMT_TOP_NE2A3_5" + ], + [ + "CMT_FIFO_L_IMUX19_11", + "CMT_TOP_IMUX19_8" + ], + [ + "CMT_FIFO_NE4BEG2_10", + "CMT_TOP_NE4BEG2_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "CMT_TOP_OCLK_1" + ], + [ + "CMT_FIFO_L_IMUX7_8", + "CMT_TOP_IMUX7_5" + ], + [ + "CMT_FIFO_NW4A2_10", + "CMT_TOP_NW4A2_7" + ], + [ + "CMT_FIFO_WW4END3_9", + "CMT_TOP_WW4END3_6" + ], + [ + "CMT_FIFO_NE4C2_11", + "CMT_TOP_NE4C2_8" + ], + [ + "CMT_FIFO_EE2BEG1_8", + "CMT_TOP_EE2BEG1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_5", + "CMT_TOP_LOGIC_OUTS_L_B9_2" + ], + [ + "CMT_FIFO_NW2A3_7", + "CMT_TOP_NW2A3_4" + ], + [ + "CMT_FIFO_NW4A1_4", + "CMT_TOP_NW4A1_1" + ], + [ + "CMT_FIFO_L_IMUX7_5", + "CMT_TOP_IMUX7_2" + ], + [ + "CMT_FIFO_WW2END1_10", + "CMT_TOP_WW2END1_7" + ], + [ + "CMT_FIFO_MONITOR_P_8", + "CMT_TOP_MONITOR_P_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_9", + "CMT_TOP_LOGIC_OUTS_L_B10_6" + ], + [ + "CMT_FIFO_L_IMUX41_9", + "CMT_TOP_IMUX41_6" + ], + [ + "CMT_FIFO_WW2A3_11", + "CMT_TOP_WW2A3_8" + ], + [ + "CMT_FIFO_LH1_10", + "CMT_TOP_LH1_7" + ], + [ + "CMT_FIFO_SE4C1_8", + "CMT_TOP_SE4C1_5" + ], + [ + "CMT_FIFO_NE4C0_9", + "CMT_TOP_NE4C0_6" + ], + [ + "CMT_FIFO_L_IMUX39_8", + "CMT_TOP_IMUX39_5" + ], + [ + "CMT_FIFO_L_IMUX46_11", + "CMT_TOP_IMUX46_8" + ], + [ + "CMT_FIFO_EE4A0_10", + "CMT_TOP_EE4A0_7" + ], + [ + "CMT_FIFO_EE4C3_4", + "CMT_TOP_EE4C3_1" + ], + [ + "CMT_FIFO_WR1END3_11", + "CMT_TOP_WR1END3_8" + ], + [ + "CMT_FIFO_L_BYP2_7", + "CMT_TOP_BYP2_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "CMT_TOP_ICLK_0" + ], + [ + "CMT_FIFO_SW2A3_9", + "CMT_TOP_SW2A3_6" + ], + [ + "CMT_FIFO_NE2A0_11", + "CMT_TOP_NE2A0_8" + ], + [ + "CMT_FIFO_SW4A0_11", + "CMT_TOP_SW4A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_7", + "CMT_TOP_LOGIC_OUTS_L_B23_4" + ], + [ + "CMT_FIFO_MONITOR_P_10", + "CMT_TOP_MONITOR_P_7" + ], + [ + "CMT_FIFO_SE4C1_5", + "CMT_TOP_SE4C1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "CMT_TOP_ICLK_7" + ], + [ + "CMT_FIFO_WL1END2_5", + "CMT_TOP_WL1END2_2" + ], + [ + "CMT_FIFO_NE4C0_3", + "CMT_TOP_NE4C0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_11", + "CMT_TOP_LOGIC_OUTS_L_B5_8" + ], + [ + "CMT_FIFO_L_FAN1_7", + "CMT_TOP_FAN1_4" + ], + [ + "CMT_FIFO_SE4C1_4", + "CMT_TOP_SE4C1_1" + ], + [ + "CMT_FIFO_L_IMUX1_11", + "CMT_TOP_IMUX1_8" + ], + [ + "CMT_FIFO_NE4C0_11", + "CMT_TOP_NE4C0_8" + ], + [ + "CMT_FIFO_WW4C2_3", + "CMT_TOP_WW4C2_0" + ], + [ + "CMT_FIFO_WW4C2_7", + "CMT_TOP_WW4C2_4" + ], + [ + "CMT_FIFO_LH5_9", + "CMT_TOP_LH5_6" + ], + [ + "CMT_FIFO_WW4A0_3", + "CMT_TOP_WW4A0_0" + ], + [ + "CMT_FIFO_LH5_8", + "CMT_TOP_LH5_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_7", + "CMT_TOP_LOGIC_OUTS_L_B7_4" + ], + [ + "CMT_FIFO_ER1BEG2_3", + "CMT_TOP_ER1BEG2_0" + ], + [ + "CMT_FIFO_L_BYP5_4", + "CMT_TOP_BYP5_1" + ], + [ + "CMT_FIFO_WL1END2_9", + "CMT_TOP_WL1END2_6" + ], + [ + "CMT_FIFO_L_IMUX46_5", + "CMT_TOP_IMUX46_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_9", + "CMT_TOP_LOGIC_OUTS_L_B6_6" + ], + [ + "CMT_FIFO_L_IMUX6_10", + "CMT_TOP_IMUX6_7" + ], + [ + "CMT_FIFO_SW2A3_11", + "CMT_TOP_SW2A3_8" + ], + [ + "CMT_FIFO_WW2A2_11", + "CMT_TOP_WW2A2_8" + ], + [ + "CMT_FIFO_NE4C2_9", + "CMT_TOP_NE4C2_6" + ], + [ + "CMT_FIFO_WW2A1_10", + "CMT_TOP_WW2A1_7" + ], + [ + "CMT_FIFO_WW4C0_4", + "CMT_TOP_WW4C0_1" + ], + [ + "CMT_FIFO_EL1BEG3_6", + "CMT_TOP_EL1BEG3_3" + ], + [ + "CMT_FIFO_L_IMUX7_4", + "CMT_TOP_IMUX7_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_6", + "CMT_TOP_LOGIC_OUTS_L_B11_3" + ], + [ + "CMT_FIFO_WW4B3_4", + "CMT_TOP_WW4B3_1" + ], + [ + "CMT_FIFO_L_IMUX39_10", + "CMT_TOP_IMUX39_7" + ], + [ + "CMT_FIFO_L_IMUX32_4", + "CMT_TOP_IMUX32_1" + ], + [ + "CMT_FIFO_L_FAN7_5", + "CMT_TOP_FAN7_2" + ], + [ + "CMT_FIFO_SW2A1_6", + "CMT_TOP_SW2A1_3" + ], + [ + "CMT_FIFO_L_IMUX46_9", + "CMT_TOP_IMUX46_6" + ], + [ + "CMT_FIFO_WW4B1_11", + "CMT_TOP_WW4B1_8" + ], + [ + "CMT_FIFO_L_IMUX14_9", + "CMT_TOP_IMUX14_6" + ], + [ + "CMT_FIFO_L_BYP0_11", + "CMT_TOP_BYP0_8" + ], + [ + "CMT_FIFO_L_IMUX4_11", + "CMT_TOP_IMUX4_8" + ], + [ + "CMT_FIFO_WW4A0_6", + "CMT_TOP_WW4A0_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "CMT_TOP_OCLKDIV_0" + ], + [ + "CMT_FIFO_NW4END2_4", + "CMT_TOP_NW4END2_1" + ], + [ + "CMT_FIFO_L_BYP4_5", + "CMT_TOP_BYP4_2" + ], + [ + "CMT_FIFO_WW2A0_10", + "CMT_TOP_WW2A0_7" + ], + [ + "CMT_FIFO_L_CTRL1_8", + "CMT_TOP_CTRL1_5" + ], + [ + "CMT_FIFO_EE4A3_7", + "CMT_TOP_EE4A3_4" + ], + [ + "CMT_FIFO_EE2BEG2_7", + "CMT_TOP_EE2BEG2_4" + ], + [ + "CMT_FIFO_L_PHASER_WRCLK", + "CMT_PHASER_IN_B_WRCLK_TOFIFO" + ], + [ + "CMT_FIFO_EE4C0_5", + "CMT_TOP_EE4C0_2" + ], + [ + "CMT_FIFO_L_IMUX33_7", + "CMT_TOP_IMUX33_4" + ], + [ + "CMT_FIFO_L_IMUX42_10", + "CMT_TOP_IMUX42_7" + ], + [ + "CMT_FIFO_SE2A2_4", + "CMT_TOP_SE2A2_1" + ], + [ + "CMT_FIFO_L_CLK1_6", + "CMT_TOP_CLK1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_9", + "CMT_TOP_LOGIC_OUTS_L_B7_6" + ], + [ + "CMT_FIFO_NW4END1_8", + "CMT_TOP_NW4END1_5" + ], + [ + "CMT_FIFO_WW2END0_5", + "CMT_TOP_WW2END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_11", + "CMT_TOP_LOGIC_OUTS_L_B4_8" + ], + [ + "CMT_FIFO_L_IMUX9_6", + "CMT_TOP_IMUX9_3" + ], + [ + "CMT_FIFO_NE2A1_8", + "CMT_TOP_NE2A1_5" + ], + [ + "CMT_FIFO_L_FAN0_8", + "CMT_TOP_FAN0_5" + ], + [ + "CMT_FIFO_L_IMUX43_7", + "CMT_TOP_IMUX43_4" + ], + [ + "CMT_FIFO_NE4C3_7", + "CMT_TOP_NE4C3_4" + ], + [ + "CMT_FIFO_SE4BEG1_8", + "CMT_TOP_SE4BEG1_5" + ], + [ + "CMT_FIFO_L_BYP4_11", + "CMT_TOP_BYP4_8" + ], + [ + "CMT_FIFO_SE2A0_10", + "CMT_TOP_SE2A0_7" + ], + [ + "CMT_FIFO_SE4C1_3", + "CMT_TOP_SE4C1_0" + ], + [ + "CMT_FIFO_L_FAN2_7", + "CMT_TOP_FAN2_4" + ], + [ + "CMT_FIFO_SE4BEG0_5", + "CMT_TOP_SE4BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX3_10", + "CMT_TOP_IMUX3_7" + ], + [ + "CMT_FIFO_SW4END2_3", + "CMT_TOP_SW4END2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_10", + "CMT_TOP_LOGIC_OUTS_L_B2_7" + ], + [ + "CMT_FIFO_L_IMUX35_4", + "CMT_TOP_IMUX35_1" + ], + [ + "CMT_FIFO_L_IMUX6_9", + "CMT_TOP_IMUX6_6" + ], + [ + "CMT_FIFO_EE4B3_9", + "CMT_TOP_EE4B3_6" + ], + [ + "CMT_FIFO_WW4A2_5", + "CMT_TOP_WW4A2_2" + ], + [ + "CMT_FIFO_L_BYP6_9", + "CMT_TOP_BYP6_6" + ], + [ + "CMT_FIFO_SW4A2_9", + "CMT_TOP_SW4A2_6" + ], + [ + "CMT_FIFO_L_IMUX43_11", + "CMT_TOP_IMUX43_8" + ], + [ + "CMT_FIFO_L_IMUX38_4", + "CMT_TOP_IMUX38_1" + ], + [ + "CMT_FIFO_WW4B1_7", + "CMT_TOP_WW4B1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_8", + "CMT_TOP_LOGIC_OUTS_L_B4_5" + ], + [ + "CMT_FIFO_WW2A3_8", + "CMT_TOP_WW2A3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_6", + "CMT_TOP_LOGIC_OUTS_L_B23_3" + ], + [ + "CMT_FIFO_SW2A0_6", + "CMT_TOP_SW2A0_3" + ], + [ + "CMT_FIFO_L_BYP0_6", + "CMT_TOP_BYP0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_5", + "CMT_TOP_LOGIC_OUTS_L_B12_2" + ], + [ + "CMT_FIFO_L_IMUX13_10", + "CMT_TOP_IMUX13_7" + ], + [ + "CMT_FIFO_ER1BEG3_7", + "CMT_TOP_ER1BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_11", + "CMT_TOP_LOGIC_OUTS_L_B11_8" + ], + [ + "CMT_FIFO_L_IMUX19_7", + "CMT_TOP_IMUX19_4" + ], + [ + "CMT_FIFO_L_IMUX4_10", + "CMT_TOP_IMUX4_7" + ], + [ + "CMT_FIFO_L_IMUX40_10", + "CMT_TOP_IMUX40_7" + ], + [ + "CMT_FIFO_SW2A2_8", + "CMT_TOP_SW2A2_5" + ], + [ + "CMT_FIFO_L_IMUX25_7", + "CMT_TOP_IMUX25_4" + ], + [ + "CMT_FIFO_EE4BEG0_11", + "CMT_TOP_EE4BEG0_8" + ], + [ + "CMT_FIFO_WW4B2_6", + "CMT_TOP_WW4B2_3" + ], + [ + "CMT_FIFO_NW4END1_11", + "CMT_TOP_NW4END1_8" + ], + [ + "CMT_FIFO_EE4A3_4", + "CMT_TOP_EE4A3_1" + ], + [ + "CMT_FIFO_SW4A2_11", + "CMT_TOP_SW4A2_8" + ], + [ + "CMT_FIFO_SE4BEG2_9", + "CMT_TOP_SE4BEG2_6" + ], + [ + "CMT_FIFO_SE4C2_6", + "CMT_TOP_SE4C2_3" + ], + [ + "CMT_FIFO_SW4END1_9", + "CMT_TOP_SW4END1_6" + ], + [ + "CMT_FIFO_NE4BEG3_9", + "CMT_TOP_NE4BEG3_6" + ], + [ + "CMT_FIFO_EE4C2_3", + "CMT_TOP_EE4C2_0" + ], + [ + "CMT_FIFO_NE4BEG1_10", + "CMT_TOP_NE4BEG1_7" + ], + [ + "CMT_FIFO_L_IMUX31_5", + "CMT_TOP_IMUX31_2" + ], + [ + "CMT_FIFO_SW4END2_5", + "CMT_TOP_SW4END2_2" + ], + [ + "CMT_FIFO_EL1BEG2_10", + "CMT_TOP_EL1BEG2_7" + ], + [ + "CMT_FIFO_L_IMUX4_6", + "CMT_TOP_IMUX4_3" + ], + [ + "CMT_FIFO_L_IMUX36_4", + "CMT_TOP_IMUX36_1" + ], + [ + "CMT_FIFO_L_IMUX29_10", + "CMT_TOP_IMUX29_7" + ], + [ + "CMT_FIFO_SE4C0_6", + "CMT_TOP_SE4C0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_6", + "CMT_TOP_LOGIC_OUTS_L_B14_3" + ], + [ + "CMT_FIFO_NW2A2_4", + "CMT_TOP_NW2A2_1" + ], + [ + "CMT_FIFO_SW4END0_10", + "CMT_TOP_SW4END0_7" + ], + [ + "CMT_FIFO_L_IMUX5_11", + "CMT_TOP_IMUX5_8" + ], + [ + "CMT_FIFO_SW2A0_4", + "CMT_TOP_SW2A0_1" + ], + [ + "CMT_FIFO_L_FAN0_6", + "CMT_TOP_FAN0_3" + ], + [ + "CMT_FIFO_L_IMUX34_4", + "CMT_TOP_IMUX34_1" + ], + [ + "CMT_FIFO_L_IMUX14_11", + "CMT_TOP_IMUX14_8" + ], + [ + "CMT_FIFO_NW4A3_8", + "CMT_TOP_NW4A3_5" + ], + [ + "CMT_FIFO_WR1END1_7", + "CMT_TOP_WR1END1_4" + ], + [ + "CMT_FIFO_NE4C1_9", + "CMT_TOP_NE4C1_6" + ], + [ + "CMT_FIFO_LH6_8", + "CMT_TOP_LH6_5" + ], + [ + "CMT_FIFO_L_IMUX43_6", + "CMT_TOP_IMUX43_3" + ], + [ + "CMT_FIFO_WW4A2_7", + "CMT_TOP_WW4A2_4" + ], + [ + "CMT_FIFO_EL1BEG3_3", + "CMT_TOP_EL1BEG3_0" + ], + [ + "CMT_FIFO_L_BYP3_3", + "CMT_TOP_BYP3_0" + ], + [ + "CMT_FIFO_L_FAN6_4", + "CMT_TOP_FAN6_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_3", + "CMT_TOP_LOGIC_OUTS_L_B20_0" + ], + [ + "CMT_FIFO_SW4A2_3", + "CMT_TOP_SW4A2_0" + ], + [ + "CMT_FIFO_SE4C3_5", + "CMT_TOP_SE4C3_2" + ], + [ + "CMT_FIFO_L_IMUX45_11", + "CMT_TOP_IMUX45_8" + ], + [ + "CMT_FIFO_L_FAN5_8", + "CMT_TOP_FAN5_5" + ], + [ + "CMT_FIFO_L_IMUX32_10", + "CMT_TOP_IMUX32_7" + ], + [ + "CMT_FIFO_L_IMUX26_7", + "CMT_TOP_IMUX26_4" + ], + [ + "CMT_FIFO_NW4END0_4", + "CMT_TOP_NW4END0_1" + ], + [ + "CMT_FIFO_WW2A0_8", + "CMT_TOP_WW2A0_5" + ], + [ + "CMT_FIFO_EL1BEG0_10", + "CMT_TOP_EL1BEG0_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_6", + "CMT_TOP_LOGIC_OUTS_L_B16_3" + ], + [ + "CMT_FIFO_EE4B3_11", + "CMT_TOP_EE4B3_8" + ], + [ + "CMT_FIFO_WL1END2_3", + "CMT_TOP_WL1END2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_4" + ], + [ + "CMT_FIFO_L_IMUX36_9", + "CMT_TOP_IMUX36_6" + ], + [ + "CMT_FIFO_EE4BEG2_4", + "CMT_TOP_EE4BEG2_1" + ], + [ + "CMT_FIFO_L_IMUX16_10", + "CMT_TOP_IMUX16_7" + ], + [ + "CMT_FIFO_LH10_7", + "CMT_TOP_LH10_4" + ], + [ + "CMT_FIFO_L_BYP1_9", + "CMT_TOP_BYP1_6" + ], + [ + "CMT_FIFO_ER1BEG0_3", + "CMT_TOP_ER1BEG0_0" + ], + [ + "CMT_FIFO_WR1END3_8", + "CMT_TOP_WR1END3_5" + ], + [ + "CMT_FIFO_NW2A0_10", + "CMT_TOP_NW2A0_7" + ], + [ + "CMT_FIFO_SW2A3_5", + "CMT_TOP_SW2A3_2" + ], + [ + "CMT_FIFO_NW4A3_7", + "CMT_TOP_NW4A3_4" + ], + [ + "CMT_FIFO_L_FAN4_11", + "CMT_TOP_FAN4_8" + ], + [ + "CMT_FIFO_WL1END0_6", + "CMT_TOP_WL1END0_3" + ], + [ + "CMT_FIFO_L_BYP4_7", + "CMT_TOP_BYP4_4" + ], + [ + "CMT_FIFO_WW4C0_7", + "CMT_TOP_WW4C0_4" + ], + [ + "CMT_FIFO_SE2A3_4", + "CMT_TOP_SE2A3_1" + ], + [ + "CMT_FIFO_L_IMUX33_3", + "CMT_TOP_IMUX33_0" + ], + [ + "CMT_FIFO_L_IMUX43_9", + "CMT_TOP_IMUX43_6" + ], + [ + "CMT_FIFO_EE2A2_5", + "CMT_TOP_EE2A2_2" + ], + [ + "CMT_FIFO_EE4C2_5", + "CMT_TOP_EE4C2_2" + ], + [ + "CMT_FIFO_ER1BEG3_11", + "CMT_TOP_ER1BEG3_8" + ], + [ + "CMT_FIFO_WW4C2_10", + "CMT_TOP_WW4C2_7" + ], + [ + "CMT_FIFO_WW4A1_8", + "CMT_TOP_WW4A1_5" + ], + [ + "CMT_FIFO_L_IMUX17_8", + "CMT_TOP_IMUX17_5" + ], + [ + "CMT_FIFO_L_IMUX17_5", + "CMT_TOP_IMUX17_2" + ], + [ + "CMT_FIFO_L_IMUX32_3", + "CMT_TOP_IMUX32_0" + ], + [ + "CMT_FIFO_LH1_6", + "CMT_TOP_LH1_3" + ], + [ + "CMT_FIFO_NW4END2_11", + "CMT_TOP_NW4END2_8" + ], + [ + "CMT_FIFO_L_BYP4_3", + "CMT_TOP_BYP4_0" + ], + [ + "CMT_FIFO_L_IMUX43_10", + "CMT_TOP_IMUX43_7" + ], + [ + "CMT_FIFO_L_FAN0_7", + "CMT_TOP_FAN0_4" + ], + [ + "CMT_FIFO_EL1BEG1_5", + "CMT_TOP_EL1BEG1_2" + ], + [ + "CMT_FIFO_SW4END0_11", + "CMT_TOP_SW4END0_8" + ], + [ + "CMT_FIFO_NE4BEG3_4", + "CMT_TOP_NE4BEG3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_5", + "CMT_TOP_LOGIC_OUTS_L_B4_2" + ], + [ + "CMT_FIFO_L_BYP7_3", + "CMT_TOP_BYP7_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_3", + "CMT_TOP_LOGIC_OUTS_L_B14_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_9", + "CMT_TOP_LOGIC_OUTS_L_B15_6" + ], + [ + "CMT_FIFO_WW4B2_3", + "CMT_TOP_WW4B2_0" + ], + [ + "CMT_FIFO_WL1END0_7", + "CMT_TOP_WL1END0_4" + ], + [ + "CMT_FIFO_L_IMUX15_11", + "CMT_TOP_IMUX15_8" + ], + [ + "CMT_FIFO_SE4BEG2_10", + "CMT_TOP_SE4BEG2_7" + ], + [ + "CMT_FIFO_SE2A1_6", + "CMT_TOP_SE2A1_3" + ], + [ + "CMT_FIFO_WW2A0_5", + "CMT_TOP_WW2A0_2" + ], + [ + "CMT_FIFO_L_IMUX4_4", + "CMT_TOP_IMUX4_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_3", + "CMT_TOP_LOGIC_OUTS_L_B16_0" + ], + [ + "CMT_FIFO_NW2A3_3", + "CMT_TOP_NW2A3_0" + ], + [ + "CMT_FIFO_NW4A2_6", + "CMT_TOP_NW4A2_3" + ], + [ + "CMT_FIFO_L_FAN2_4", + "CMT_TOP_FAN2_1" + ], + [ + "CMT_FIFO_L_IMUX25_11", + "CMT_TOP_IMUX25_8" + ], + [ + "CMT_FIFO_NE2A1_5", + "CMT_TOP_NE2A1_2" + ], + [ + "CMT_FIFO_SW4END3_3", + "CMT_TOP_SW4END3_0" + ], + [ + "CMT_FIFO_ER1BEG1_5", + "CMT_TOP_ER1BEG1_2" + ], + [ + "CMT_FIFO_WW4C2_11", + "CMT_TOP_WW4C2_8" + ], + [ + "CMT_FIFO_NE4BEG1_6", + "CMT_TOP_NE4BEG1_3" + ], + [ + "CMT_FIFO_EE4A1_3", + "CMT_TOP_EE4A1_0" + ], + [ + "CMT_FIFO_NW4A0_10", + "CMT_TOP_NW4A0_7" + ], + [ + "CMT_FIFO_LH4_4", + "CMT_TOP_LH4_1" + ], + [ + "CMT_FIFO_L_IMUX28_8", + "CMT_TOP_IMUX28_5" + ], + [ + "CMT_FIFO_ER1BEG3_3", + "CMT_TOP_ER1BEG3_0" + ], + [ + "CMT_FIFO_L_IMUX5_10", + "CMT_TOP_IMUX5_7" + ], + [ + "CMT_FIFO_L_IMUX44_6", + "CMT_TOP_IMUX44_3" + ], + [ + "CMT_FIFO_L_BYP3_10", + "CMT_TOP_BYP3_7" + ], + [ + "CMT_FIFO_L_BYP5_11", + "CMT_TOP_BYP5_8" + ], + [ + "CMT_FIFO_NE4BEG1_3", + "CMT_TOP_NE4BEG1_0" + ], + [ + "CMT_FIFO_L_IMUX12_7", + "CMT_TOP_IMUX12_4" + ], + [ + "CMT_FIFO_LH7_3", + "CMT_TOP_LH7_0" + ], + [ + "CMT_FIFO_SW4A0_7", + "CMT_TOP_SW4A0_4" + ], + [ + "CMT_FIFO_L_BYP4_10", + "CMT_TOP_BYP4_7" + ], + [ + "CMT_FIFO_WR1END1_8", + "CMT_TOP_WR1END1_5" + ], + [ + "CMT_FIFO_SE2A1_3", + "CMT_TOP_SE2A1_0" + ], + [ + "CMT_FIFO_EE2BEG0_7", + "CMT_TOP_EE2BEG0_4" + ], + [ + "CMT_FIFO_L_IMUX12_11", + "CMT_TOP_IMUX12_8" + ], + [ + "CMT_FIFO_L_FAN4_3", + "CMT_TOP_FAN4_0" + ], + [ + "CMT_FIFO_L_IMUX8_11", + "CMT_TOP_IMUX8_8" + ], + [ + "CMT_FIFO_NW4END2_10", + "CMT_TOP_NW4END2_7" + ], + [ + "CMT_FIFO_ER1BEG1_11", + "CMT_TOP_ER1BEG1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_5", + "CMT_TOP_LOGIC_OUTS_L_B16_2" + ], + [ + "CMT_FIFO_WW2A3_4", + "CMT_TOP_WW2A3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_4", + "CMT_TOP_LOGIC_OUTS_L_B14_1" + ], + [ + "CMT_FIFO_L_IMUX23_5", + "CMT_TOP_IMUX23_2" + ], + [ + "CMT_FIFO_NW4END0_11", + "CMT_TOP_NW4END0_8" + ], + [ + "CMT_FIFO_ER1BEG3_10", + "CMT_TOP_ER1BEG3_7" + ], + [ + "CMT_FIFO_SE4C3_4", + "CMT_TOP_SE4C3_1" + ], + [ + "CMT_FIFO_WW2END3_4", + "CMT_TOP_WW2END3_1" + ], + [ + "CMT_FIFO_L_FAN1_11", + "CMT_TOP_FAN1_8" + ], + [ + "CMT_FIFO_SW4END1_4", + "CMT_TOP_SW4END1_1" + ], + [ + "CMT_FIFO_SW4END3_11", + "CMT_TOP_SW4END3_8" + ], + [ + "CMT_FIFO_EE4B1_8", + "CMT_TOP_EE4B1_5" + ], + [ + "CMT_FIFO_L_FAN1_10", + "CMT_TOP_FAN1_7" + ], + [ + "CMT_FIFO_L_IMUX43_3", + "CMT_TOP_IMUX43_0" + ], + [ + "CMT_FIFO_WR1END1_6", + "CMT_TOP_WR1END1_3" + ], + [ + "CMT_FIFO_WW4END0_9", + "CMT_TOP_WW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX24_4", + "CMT_TOP_IMUX24_1" + ], + [ + "CMT_FIFO_EE4C3_5", + "CMT_TOP_EE4C3_2" + ], + [ + "CMT_FIFO_SE2A3_5", + "CMT_TOP_SE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX47_6", + "CMT_TOP_IMUX47_3" + ], + [ + "CMT_FIFO_L_IMUX22_6", + "CMT_TOP_IMUX22_3" + ], + [ + "CMT_FIFO_NE4C1_8", + "CMT_TOP_NE4C1_5" + ], + [ + "CMT_FIFO_EL1BEG1_7", + "CMT_TOP_EL1BEG1_4" + ], + [ + "CMT_FIFO_L_IMUX5_8", + "CMT_TOP_IMUX5_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_4", + "CMT_TOP_LOGIC_OUTS_L_B7_1" + ], + [ + "CMT_FIFO_SE4BEG0_9", + "CMT_TOP_SE4BEG0_6" + ], + [ + "CMT_FIFO_L_BYP7_6", + "CMT_TOP_BYP7_3" + ], + [ + "CMT_FIFO_L_IMUX39_7", + "CMT_TOP_IMUX39_4" + ], + [ + "CMT_FIFO_SW2A2_10", + "CMT_TOP_SW2A2_7" + ], + [ + "CMT_FIFO_WW4A0_7", + "CMT_TOP_WW4A0_4" + ], + [ + "CMT_FIFO_NW2A1_3", + "CMT_TOP_NW2A1_0" + ], + [ + "CMT_FIFO_LH11_3", + "CMT_TOP_LH11_0" + ], + [ + "CMT_FIFO_EE4BEG3_3", + "CMT_TOP_EE4BEG3_0" + ], + [ + "CMT_FIFO_L_IMUX20_3", + "CMT_TOP_IMUX20_0" + ], + [ + "CMT_FIFO_ER1BEG1_6", + "CMT_TOP_ER1BEG1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_8", + "CMT_TOP_LOGIC_OUTS_L_B22_5" + ], + [ + "CMT_FIFO_WW4B1_5", + "CMT_TOP_WW4B1_2" + ], + [ + "CMT_FIFO_EE4B1_3", + "CMT_TOP_EE4B1_0" + ], + [ + "CMT_FIFO_L_IMUX30_5", + "CMT_TOP_IMUX30_2" + ], + [ + "CMT_FIFO_EE4A2_11", + "CMT_TOP_EE4A2_8" + ], + [ + "CMT_FIFO_WW4A2_6", + "CMT_TOP_WW4A2_3" + ], + [ + "CMT_FIFO_EE4B3_7", + "CMT_TOP_EE4B3_4" + ], + [ + "CMT_FIFO_WW4B1_9", + "CMT_TOP_WW4B1_6" + ], + [ + "CMT_FIFO_L_IMUX21_7", + "CMT_TOP_IMUX21_4" + ], + [ + "CMT_FIFO_WR1END2_8", + "CMT_TOP_WR1END2_5" + ], + [ + "CMT_FIFO_WW2END0_3", + "CMT_TOP_WW2END0_0" + ], + [ + "CMT_FIFO_WW2END0_6", + "CMT_TOP_WW2END0_3" + ], + [ + "CMT_FIFO_NW4A0_8", + "CMT_TOP_NW4A0_5" + ], + [ + "CMT_FIFO_SW4END2_7", + "CMT_TOP_SW4END2_4" + ], + [ + "CMT_FIFO_L_IMUX16_6", + "CMT_TOP_IMUX16_3" + ], + [ + "CMT_FIFO_L_IMUX3_5", + "CMT_TOP_IMUX3_2" + ], + [ + "CMT_FIFO_EL1BEG0_7", + "CMT_TOP_EL1BEG0_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "CMT_TOP_ICLK_3" + ], + [ + "CMT_FIFO_SE4C0_11", + "CMT_TOP_SE4C0_8" + ], + [ + "CMT_FIFO_L_IMUX11_7", + "CMT_TOP_IMUX11_4" + ], + [ + "CMT_FIFO_WR1END2_6", + "CMT_TOP_WR1END2_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "CMT_TOP_ICLKDIV_3" + ], + [ + "CMT_FIFO_LH11_9", + "CMT_TOP_LH11_6" + ], + [ + "CMT_FIFO_NW4A2_7", + "CMT_TOP_NW4A2_4" + ], + [ + "CMT_FIFO_SE4BEG0_6", + "CMT_TOP_SE4BEG0_3" + ], + [ + "CMT_FIFO_SW4A0_6", + "CMT_TOP_SW4A0_3" + ], + [ + "CMT_FIFO_EE4B0_10", + "CMT_TOP_EE4B0_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "CMT_TOP_OCLKDIV_2" + ], + [ + "CMT_FIFO_L_IMUX37_4", + "CMT_TOP_IMUX37_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_10", + "CMT_TOP_LOGIC_OUTS_L_B18_7" + ], + [ + "CMT_FIFO_EE4C2_8", + "CMT_TOP_EE4C2_5" + ], + [ + "CMT_FIFO_NW4END1_6", + "CMT_TOP_NW4END1_3" + ], + [ + "CMT_FIFO_LH5_5", + "CMT_TOP_LH5_2" + ], + [ + "CMT_FIFO_L_IMUX39_3", + "CMT_TOP_IMUX39_0" + ], + [ + "CMT_FIFO_LH6_4", + "CMT_TOP_LH6_1" + ], + [ + "CMT_FIFO_EE2BEG2_5", + "CMT_TOP_EE2BEG2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_8", + "CMT_TOP_LOGIC_OUTS_L_B21_5" + ], + [ + "CMT_FIFO_EL1BEG3_10", + "CMT_TOP_EL1BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX34_7", + "CMT_TOP_IMUX34_4" + ], + [ + "CMT_FIFO_L_IMUX18_4", + "CMT_TOP_IMUX18_1" + ], + [ + "CMT_FIFO_L_IMUX40_8", + "CMT_TOP_IMUX40_5" + ], + [ + "CMT_FIFO_NW4END3_6", + "CMT_TOP_NW4END3_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "CMT_TOP_ICLKDIV_7" + ], + [ + "CMT_FIFO_SW4END2_4", + "CMT_TOP_SW4END2_1" + ], + [ + "CMT_FIFO_SW2A2_5", + "CMT_TOP_SW2A2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_10", + "CMT_TOP_LOGIC_OUTS_L_B16_7" + ], + [ + "CMT_FIFO_WW4A3_10", + "CMT_TOP_WW4A3_7" + ], + [ + "CMT_FIFO_NE4C3_3", + "CMT_TOP_NE4C3_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "CMT_TOP_ICLK_5" + ], + [ + "CMT_FIFO_L_IMUX8_6", + "CMT_TOP_IMUX8_3" + ], + [ + "CMT_FIFO_L_FAN6_8", + "CMT_TOP_FAN6_5" + ], + [ + "CMT_FIFO_L_IMUX19_6", + "CMT_TOP_IMUX19_3" + ], + [ + "CMT_FIFO_L_IMUX11_11", + "CMT_TOP_IMUX11_8" + ], + [ + "CMT_FIFO_L_IMUX0_11", + "CMT_TOP_IMUX0_8" + ], + [ + "CMT_FIFO_EL1BEG3_7", + "CMT_TOP_EL1BEG3_4" + ], + [ + "CMT_FIFO_L_IMUX45_9", + "CMT_TOP_IMUX45_6" + ], + [ + "CMT_FIFO_L_CLK0_10", + "CMT_TOP_CLK0_7" + ], + [ + "CMT_FIFO_L_IMUX28_10", + "CMT_TOP_IMUX28_7" + ], + [ + "CMT_FIFO_SW4A3_8", + "CMT_TOP_SW4A3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_9", + "CMT_TOP_LOGIC_OUTS_L_B8_6" + ], + [ + "CMT_FIFO_WR1END1_5", + "CMT_TOP_WR1END1_2" + ], + [ + "CMT_FIFO_WW4END1_6", + "CMT_TOP_WW4END1_3" + ], + [ + "CMT_FIFO_LH4_8", + "CMT_TOP_LH4_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_3", + "CMT_TOP_LOGIC_OUTS_L_B13_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_9", + "CMT_TOP_LOGIC_OUTS_L_B14_6" + ], + [ + "CMT_FIFO_LH2_3", + "CMT_TOP_LH2_0" + ], + [ + "CMT_FIFO_LH3_8", + "CMT_TOP_LH3_5" + ], + [ + "CMT_FIFO_NE4C3_10", + "CMT_TOP_NE4C3_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "CMT_TOP_ICLKDIV_6" + ], + [ + "CMT_FIFO_WW4A0_5", + "CMT_TOP_WW4A0_2" + ], + [ + "CMT_FIFO_WW2END0_8", + "CMT_TOP_WW2END0_5" + ], + [ + "CMT_FIFO_L_IMUX46_3", + "CMT_TOP_IMUX46_0" + ], + [ + "CMT_FIFO_WR1END2_10", + "CMT_TOP_WR1END2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_5", + "CMT_TOP_LOGIC_OUTS_L_B7_2" + ], + [ + "CMT_FIFO_WR1END2_5", + "CMT_TOP_WR1END2_2" + ], + [ + "CMT_FIFO_L_BYP7_7", + "CMT_TOP_BYP7_4" + ], + [ + "CMT_FIFO_EE4A0_4", + "CMT_TOP_EE4A0_1" + ], + [ + "CMT_FIFO_L_IMUX25_6", + "CMT_TOP_IMUX25_3" + ], + [ + "CMT_FIFO_L_CTRL0_3", + "CMT_TOP_CTRL0_0" + ], + [ + "CMT_FIFO_L_BYP0_9", + "CMT_TOP_BYP0_6" + ], + [ + "CMT_FIFO_L_BYP1_8", + "CMT_TOP_BYP1_5" + ], + [ + "CMT_FIFO_EE4A2_7", + "CMT_TOP_EE4A2_4" + ], + [ + "CMT_FIFO_NW4END3_4", + "CMT_TOP_NW4END3_1" + ], + [ + "CMT_FIFO_ER1BEG3_6", + "CMT_TOP_ER1BEG3_3" + ], + [ + "CMT_FIFO_SW2A1_7", + "CMT_TOP_SW2A1_4" + ], + [ + "CMT_FIFO_EE4B0_4", + "CMT_TOP_EE4B0_1" + ], + [ + "CMT_FIFO_LH4_3", + "CMT_TOP_LH4_0" + ], + [ + "CMT_FIFO_L_CLK0_8", + "CMT_TOP_CLK0_5" + ], + [ + "CMT_FIFO_L_FAN0_11", + "CMT_TOP_FAN0_8" + ], + [ + "CMT_FIFO_EE4B0_6", + "CMT_TOP_EE4B0_3" + ], + [ + "CMT_FIFO_L_IMUX5_9", + "CMT_TOP_IMUX5_6" + ], + [ + "CMT_FIFO_L_IMUX34_9", + "CMT_TOP_IMUX34_6" + ], + [ + "CMT_FIFO_L_IMUX15_4", + "CMT_TOP_IMUX15_1" + ], + [ + "CMT_FIFO_L_IMUX30_6", + "CMT_TOP_IMUX30_3" + ], + [ + "CMT_FIFO_L_FAN7_9", + "CMT_TOP_FAN7_6" + ], + [ + "CMT_FIFO_ER1BEG1_7", + "CMT_TOP_ER1BEG1_4" + ], + [ + "CMT_FIFO_SE2A0_6", + "CMT_TOP_SE2A0_3" + ], + [ + "CMT_FIFO_NW4A1_7", + "CMT_TOP_NW4A1_4" + ], + [ + "CMT_FIFO_L_FAN6_11", + "CMT_TOP_FAN6_8" + ], + [ + "CMT_FIFO_SW4A1_7", + "CMT_TOP_SW4A1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_7", + "CMT_TOP_LOGIC_OUTS_L_B22_4" + ], + [ + "CMT_FIFO_WW4B2_5", + "CMT_TOP_WW4B2_2" + ], + [ + "CMT_FIFO_SW4END1_5", + "CMT_TOP_SW4END1_2" + ], + [ + "CMT_FIFO_EE4A1_10", + "CMT_TOP_EE4A1_7" + ], + [ + "CMT_FIFO_SE4BEG0_7", + "CMT_TOP_SE4BEG0_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "CMT_TOP_ICLK_2" + ], + [ + "CMT_FIFO_WW2END3_7", + "CMT_TOP_WW2END3_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "CMT_TOP_OCLKDIV_3" + ], + [ + "CMT_FIFO_L_FAN1_8", + "CMT_TOP_FAN1_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "CMT_TOP_OCLK1X_90_4" + ], + [ + "CMT_FIFO_L_IMUX29_11", + "CMT_TOP_IMUX29_8" + ], + [ + "CMT_FIFO_LH1_11", + "CMT_TOP_LH1_8" + ], + [ + "CMT_FIFO_WW4A2_3", + "CMT_TOP_WW4A2_0" + ], + [ + "CMT_FIFO_LH12_8", + "CMT_TOP_LH12_5" + ], + [ + "CMT_FIFO_NW4END0_9", + "CMT_TOP_NW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX29_3", + "CMT_TOP_IMUX29_0" + ], + [ + "CMT_FIFO_NE4BEG0_4", + "CMT_TOP_NE4BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_11", + "CMT_TOP_LOGIC_OUTS_L_B12_8" + ], + [ + "CMT_FIFO_EE4A0_7", + "CMT_TOP_EE4A0_4" + ], + [ + "CMT_FIFO_EE4B1_4", + "CMT_TOP_EE4B1_1" + ], + [ + "CMT_FIFO_SE2A2_10", + "CMT_TOP_SE2A2_7" + ], + [ + "CMT_FIFO_L_IMUX15_5", + "CMT_TOP_IMUX15_2" + ], + [ + "CMT_FIFO_EE4B2_4", + "CMT_TOP_EE4B2_1" + ], + [ + "CMT_FIFO_EE2BEG0_11", + "CMT_TOP_EE2BEG0_8" + ], + [ + "CMT_FIFO_L_IMUX30_10", + "CMT_TOP_IMUX30_7" + ], + [ + "CMT_FIFO_SW4A1_11", + "CMT_TOP_SW4A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_6", + "CMT_TOP_LOGIC_OUTS_L_B1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_7", + "CMT_TOP_LOGIC_OUTS_L_B21_4" + ], + [ + "CMT_FIFO_L_FAN0_5", + "CMT_TOP_FAN0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_3", + "CMT_TOP_LOGIC_OUTS_L_B12_0" + ], + [ + "CMT_FIFO_SW4A0_3", + "CMT_TOP_SW4A0_0" + ], + [ + "CMT_FIFO_WW2END1_5", + "CMT_TOP_WW2END1_2" + ], + [ + "CMT_FIFO_SW2A3_6", + "CMT_TOP_SW2A3_3" + ], + [ + "CMT_FIFO_LH6_11", + "CMT_TOP_LH6_8" + ], + [ + "CMT_FIFO_ER1BEG0_4", + "CMT_TOP_ER1BEG0_1" + ], + [ + "CMT_FIFO_L_IMUX0_8", + "CMT_TOP_IMUX0_5" + ], + [ + "CMT_FIFO_EE4A0_5", + "CMT_TOP_EE4A0_2" + ], + [ + "CMT_FIFO_L_IMUX41_5", + "CMT_TOP_IMUX41_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_5", + "CMT_TOP_LOGIC_OUTS_L_B17_2" + ], + [ + "CMT_FIFO_SE2A1_11", + "CMT_TOP_SE2A1_8" + ], + [ + "CMT_FIFO_EE4BEG0_10", + "CMT_TOP_EE4BEG0_7" + ], + [ + "CMT_FIFO_L_FAN5_9", + "CMT_TOP_FAN5_6" + ], + [ + "CMT_FIFO_L_FAN0_9", + "CMT_TOP_FAN0_6" + ], + [ + "CMT_FIFO_NE4C2_10", + "CMT_TOP_NE4C2_7" + ], + [ + "CMT_FIFO_WL1END1_7", + "CMT_TOP_WL1END1_4" + ], + [ + "CMT_FIFO_L_IMUX25_8", + "CMT_TOP_IMUX25_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_3", + "CMT_TOP_LOGIC_OUTS_L_B23_0" + ], + [ + "CMT_FIFO_ER1BEG0_11", + "CMT_TOP_ER1BEG0_8" + ], + [ + "CMT_FIFO_WW4END2_7", + "CMT_TOP_WW4END2_4" + ], + [ + "CMT_FIFO_WW4B3_6", + "CMT_TOP_WW4B3_3" + ], + [ + "CMT_FIFO_ER1BEG2_9", + "CMT_TOP_ER1BEG2_6" + ], + [ + "CMT_FIFO_EE4A3_6", + "CMT_TOP_EE4A3_3" + ], + [ + "CMT_FIFO_NE4C3_8", + "CMT_TOP_NE4C3_5" + ], + [ + "CMT_FIFO_EE4B0_5", + "CMT_TOP_EE4B0_2" + ], + [ + "CMT_FIFO_WW4C2_6", + "CMT_TOP_WW4C2_3" + ], + [ + "CMT_FIFO_EE4BEG2_10", + "CMT_TOP_EE4BEG2_7" + ], + [ + "CMT_FIFO_NE4C1_10", + "CMT_TOP_NE4C1_7" + ], + [ + "CMT_FIFO_L_IMUX13_5", + "CMT_TOP_IMUX13_2" + ], + [ + "CMT_FIFO_EE2BEG2_10", + "CMT_TOP_EE2BEG2_7" + ], + [ + "CMT_FIFO_WL1END2_11", + "CMT_TOP_WL1END2_8" + ], + [ + "CMT_FIFO_L_IMUX17_10", + "CMT_TOP_IMUX17_7" + ], + [ + "CMT_FIFO_WW4END2_10", + "CMT_TOP_WW4END2_7" + ], + [ + "CMT_FIFO_NW2A1_10", + "CMT_TOP_NW2A1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_7", + "CMT_TOP_LOGIC_OUTS_L_B14_4" + ], + [ + "CMT_FIFO_SW4END2_10", + "CMT_TOP_SW4END2_7" + ], + [ + "CMT_FIFO_NW4END1_5", + "CMT_TOP_NW4END1_2" + ], + [ + "CMT_FIFO_L_IMUX38_5", + "CMT_TOP_IMUX38_2" + ], + [ + "CMT_FIFO_LH7_10", + "CMT_TOP_LH7_7" + ], + [ + "CMT_FIFO_LH12_4", + "CMT_TOP_LH12_1" + ], + [ + "CMT_FIFO_WW4A1_4", + "CMT_TOP_WW4A1_1" + ], + [ + "CMT_FIFO_L_CTRL0_8", + "CMT_TOP_CTRL0_5" + ], + [ + "CMT_FIFO_EE4B1_9", + "CMT_TOP_EE4B1_6" + ], + [ + "CMT_FIFO_EE4A0_9", + "CMT_TOP_EE4A0_6" + ], + [ + "CMT_FIFO_L_IMUX15_3", + "CMT_TOP_IMUX15_0" + ], + [ + "CMT_FIFO_WW4B2_7", + "CMT_TOP_WW4B2_4" + ], + [ + "CMT_FIFO_NE2A2_9", + "CMT_TOP_NE2A2_6" + ], + [ + "CMT_FIFO_L_IMUX1_10", + "CMT_TOP_IMUX1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_4", + "CMT_TOP_LOGIC_OUTS_L_B5_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_8", + "CMT_TOP_LOGIC_OUTS_L_B6_5" + ], + [ + "CMT_FIFO_EE2A2_4", + "CMT_TOP_EE2A2_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_5", + "CMT_TOP_LOGIC_OUTS_L_B13_2" + ], + [ + "CMT_FIFO_WW2A2_7", + "CMT_TOP_WW2A2_4" + ], + [ + "CMT_FIFO_L_FAN6_3", + "CMT_TOP_FAN6_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_5", + "CMT_TOP_LOGIC_OUTS_L_B8_2" + ], + [ + "CMT_FIFO_L_IMUX32_9", + "CMT_TOP_IMUX32_6" + ], + [ + "CMT_FIFO_LH8_9", + "CMT_TOP_LH8_6" + ], + [ + "CMT_FIFO_NE4BEG0_11", + "CMT_TOP_NE4BEG0_8" + ], + [ + "CMT_FIFO_WW4END0_4", + "CMT_TOP_WW4END0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_4", + "CMT_TOP_LOGIC_OUTS_L_B18_1" + ], + [ + "CMT_FIFO_L_IMUX21_10", + "CMT_TOP_IMUX21_7" + ], + [ + "CMT_FIFO_WW4A2_8", + "CMT_TOP_WW4A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_3", + "CMT_TOP_LOGIC_OUTS_L_B19_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_5", + "CMT_TOP_LOGIC_OUTS_L_B3_2" + ], + [ + "CMT_FIFO_WW4END2_11", + "CMT_TOP_WW4END2_8" + ], + [ + "CMT_FIFO_NW4END3_3", + "CMT_TOP_NW4END3_0" + ], + [ + "CMT_FIFO_SE4BEG3_7", + "CMT_TOP_SE4BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_7", + "CMT_TOP_LOGIC_OUTS_L_B8_4" + ], + [ + "CMT_FIFO_NW4A2_8", + "CMT_TOP_NW4A2_5" + ], + [ + "CMT_FIFO_EE4BEG3_10", + "CMT_TOP_EE4BEG3_7" + ], + [ + "CMT_FIFO_NE4BEG0_6", + "CMT_TOP_NE4BEG0_3" + ], + [ + "CMT_FIFO_NE2A0_8", + "CMT_TOP_NE2A0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_8", + "CMT_TOP_LOGIC_OUTS_L_B12_5" + ], + [ + "CMT_FIFO_WR1END0_7", + "CMT_TOP_WR1END0_4" + ], + [ + "CMT_FIFO_LH8_4", + "CMT_TOP_LH8_1" + ], + [ + "CMT_FIFO_NE2A2_10", + "CMT_TOP_NE2A2_7" + ], + [ + "CMT_FIFO_WW4A3_7", + "CMT_TOP_WW4A3_4" + ], + [ + "CMT_FIFO_SW4A1_3", + "CMT_TOP_SW4A1_0" + ], + [ + "CMT_FIFO_L_FAN6_9", + "CMT_TOP_FAN6_6" + ], + [ + "CMT_FIFO_ER1BEG1_3", + "CMT_TOP_ER1BEG1_0" + ], + [ + "CMT_FIFO_L_IMUX8_5", + "CMT_TOP_IMUX8_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_3", + "CMT_TOP_LOGIC_OUTS_L_B8_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_8", + "CMT_TOP_LOGIC_OUTS_L_B10_5" + ], + [ + "CMT_FIFO_WW4C3_4", + "CMT_TOP_WW4C3_1" + ], + [ + "CMT_FIFO_L_IMUX3_7", + "CMT_TOP_IMUX3_4" + ], + [ + "CMT_FIFO_L_IMUX0_7", + "CMT_TOP_IMUX0_4" + ], + [ + "CMT_FIFO_L_IMUX10_11", + "CMT_TOP_IMUX10_8" + ], + [ + "CMT_FIFO_LH1_9", + "CMT_TOP_LH1_6" + ], + [ + "CMT_FIFO_L_FAN5_5", + "CMT_TOP_FAN5_2" + ], + [ + "CMT_FIFO_L_IMUX21_6", + "CMT_TOP_IMUX21_3" + ], + [ + "CMT_FIFO_EL1BEG3_5", + "CMT_TOP_EL1BEG3_2" + ], + [ + "CMT_FIFO_WL1END1_5", + "CMT_TOP_WL1END1_2" + ], + [ + "CMT_FIFO_L_IMUX0_4", + "CMT_TOP_IMUX0_1" + ], + [ + "CMT_FIFO_LH6_10", + "CMT_TOP_LH6_7" + ], + [ + "CMT_FIFO_SE2A0_3", + "CMT_TOP_SE2A0_0" + ], + [ + "CMT_FIFO_EE4A1_8", + "CMT_TOP_EE4A1_5" + ], + [ + "CMT_FIFO_L_IMUX30_4", + "CMT_TOP_IMUX30_1" + ], + [ + "CMT_FIFO_NW4A3_5", + "CMT_TOP_NW4A3_2" + ], + [ + "CMT_FIFO_L_IMUX37_8", + "CMT_TOP_IMUX37_5" + ], + [ + "CMT_FIFO_SE4C0_7", + "CMT_TOP_SE4C0_4" + ], + [ + "CMT_FIFO_ER1BEG0_6", + "CMT_TOP_ER1BEG0_3" + ], + [ + "CMT_FIFO_WW2A3_3", + "CMT_TOP_WW2A3_0" + ], + [ + "CMT_FIFO_WW4C1_4", + "CMT_TOP_WW4C1_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "CMT_TOP_ICLK_1" + ], + [ + "CMT_FIFO_WW4C3_8", + "CMT_TOP_WW4C3_5" + ], + [ + "CMT_FIFO_WW2END0_9", + "CMT_TOP_WW2END0_6" + ], + [ + "CMT_FIFO_SE4BEG3_8", + "CMT_TOP_SE4BEG3_5" + ], + [ + "CMT_FIFO_LH3_11", + "CMT_TOP_LH3_8" + ], + [ + "CMT_FIFO_L_CLK1_11", + "CMT_TOP_CLK1_8" + ], + [ + "CMT_FIFO_EE4BEG0_5", + "CMT_TOP_EE4BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX10_4", + "CMT_TOP_IMUX10_1" + ], + [ + "CMT_FIFO_WW2A2_3", + "CMT_TOP_WW2A2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_4", + "CMT_TOP_LOGIC_OUTS_L_B9_1" + ], + [ + "CMT_FIFO_L_IMUX7_11", + "CMT_TOP_IMUX7_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_5", + "CMT_TOP_LOGIC_OUTS_L_B20_2" + ], + [ + "CMT_FIFO_L_IMUX44_5", + "CMT_TOP_IMUX44_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "CMT_TOP_OCLK_0" + ], + [ + "CMT_FIFO_L_IMUX1_4", + "CMT_TOP_IMUX1_1" + ], + [ + "CMT_FIFO_WW2A0_11", + "CMT_TOP_WW2A0_8" + ], + [ + "CMT_FIFO_L_IMUX38_9", + "CMT_TOP_IMUX38_6" + ], + [ + "CMT_FIFO_NE4C0_6", + "CMT_TOP_NE4C0_3" + ], + [ + "CMT_FIFO_L_IMUX14_4", + "CMT_TOP_IMUX14_1" + ], + [ + "CMT_FIFO_L_BYP1_6", + "CMT_TOP_BYP1_3" + ], + [ + "CMT_FIFO_L_BYP1_4", + "CMT_TOP_BYP1_1" + ], + [ + "CMT_FIFO_L_IMUX23_7", + "CMT_TOP_IMUX23_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "CMT_TOP_OCLK_6" + ], + [ + "CMT_FIFO_L_IMUX10_3", + "CMT_TOP_IMUX10_0" + ], + [ + "CMT_FIFO_SE4C3_11", + "CMT_TOP_SE4C3_8" + ], + [ + "CMT_FIFO_WW4END1_7", + "CMT_TOP_WW4END1_4" + ], + [ + "CMT_FIFO_SW4A3_7", + "CMT_TOP_SW4A3_4" + ], + [ + "CMT_FIFO_NW4END2_6", + "CMT_TOP_NW4END2_3" + ], + [ + "CMT_FIFO_LH6_6", + "CMT_TOP_LH6_3" + ], + [ + "CMT_FIFO_L_FAN5_3", + "CMT_TOP_FAN5_0" + ], + [ + "CMT_FIFO_L_IMUX33_8", + "CMT_TOP_IMUX33_5" + ], + [ + "CMT_FIFO_NE4BEG1_7", + "CMT_TOP_NE4BEG1_4" + ], + [ + "CMT_FIFO_L_IMUX43_4", + "CMT_TOP_IMUX43_1" + ], + [ + "CMT_FIFO_L_IMUX8_9", + "CMT_TOP_IMUX8_6" + ], + [ + "CMT_FIFO_L_IMUX19_5", + "CMT_TOP_IMUX19_2" + ], + [ + "CMT_FIFO_L_IMUX41_6", + "CMT_TOP_IMUX41_3" + ], + [ + "CMT_FIFO_L_IMUX38_11", + "CMT_TOP_IMUX38_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_7", + "CMT_TOP_LOGIC_OUTS_L_B16_4" + ], + [ + "CMT_FIFO_LH1_5", + "CMT_TOP_LH1_2" + ], + [ + "CMT_FIFO_L_IMUX1_7", + "CMT_TOP_IMUX1_4" + ], + [ + "CMT_FIFO_NE4BEG2_5", + "CMT_TOP_NE4BEG2_2" + ], + [ + "CMT_FIFO_WW4C3_11", + "CMT_TOP_WW4C3_8" + ], + [ + "CMT_FIFO_L_FAN1_9", + "CMT_TOP_FAN1_6" + ], + [ + "CMT_FIFO_ER1BEG1_4", + "CMT_TOP_ER1BEG1_1" + ], + [ + "CMT_FIFO_L_IMUX29_4", + "CMT_TOP_IMUX29_1" + ], + [ + "CMT_FIFO_SW4END0_3", + "CMT_TOP_SW4END0_0" + ], + [ + "CMT_FIFO_L_BYP7_4", + "CMT_TOP_BYP7_1" + ], + [ + "CMT_FIFO_SE4C2_11", + "CMT_TOP_SE4C2_8" + ], + [ + "CMT_FIFO_NE4C3_11", + "CMT_TOP_NE4C3_8" + ], + [ + "CMT_FIFO_L_FAN3_9", + "CMT_TOP_FAN3_6" + ], + [ + "CMT_FIFO_WR1END0_9", + "CMT_TOP_WR1END0_6" + ], + [ + "CMT_FIFO_SW4A3_4", + "CMT_TOP_SW4A3_1" + ], + [ + "CMT_FIFO_WW4A1_6", + "CMT_TOP_WW4A1_3" + ], + [ + "CMT_FIFO_LH12_9", + "CMT_TOP_LH12_6" + ], + [ + "CMT_FIFO_L_CLK0_7", + "CMT_TOP_CLK0_4" + ], + [ + "CMT_FIFO_EE2BEG2_4", + "CMT_TOP_EE2BEG2_1" + ], + [ + "CMT_FIFO_ER1BEG2_7", + "CMT_TOP_ER1BEG2_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "CMT_TOP_OCLK_8" + ], + [ + "CMT_FIFO_L_IMUX11_4", + "CMT_TOP_IMUX11_1" + ], + [ + "CMT_FIFO_EE2A1_6", + "CMT_TOP_EE2A1_3" + ], + [ + "CMT_FIFO_L_FAN2_10", + "CMT_TOP_FAN2_7" + ], + [ + "CMT_FIFO_EE4BEG1_5", + "CMT_TOP_EE4BEG1_2" + ], + [ + "CMT_FIFO_L_IMUX20_10", + "CMT_TOP_IMUX20_7" + ], + [ + "CMT_FIFO_L_IMUX42_11", + "CMT_TOP_IMUX42_8" + ], + [ + "CMT_FIFO_L_IMUX47_4", + "CMT_TOP_IMUX47_1" + ], + [ + "CMT_FIFO_WW2A3_6", + "CMT_TOP_WW2A3_3" + ], + [ + "CMT_FIFO_SW2A2_6", + "CMT_TOP_SW2A2_3" + ], + [ + "CMT_FIFO_EE2BEG3_6", + "CMT_TOP_EE2BEG3_3" + ], + [ + "CMT_FIFO_L_IMUX41_3", + "CMT_TOP_IMUX41_0" + ], + [ + "CMT_FIFO_L_IMUX22_5", + "CMT_TOP_IMUX22_2" + ], + [ + "CMT_FIFO_L_IMUX13_8", + "CMT_TOP_IMUX13_5" + ], + [ + "CMT_FIFO_SE2A3_3", + "CMT_TOP_SE2A3_0" + ], + [ + "CMT_FIFO_WW4A1_9", + "CMT_TOP_WW4A1_6" + ], + [ + "CMT_FIFO_L_IMUX35_8", + "CMT_TOP_IMUX35_5" + ], + [ + "CMT_FIFO_EE2A1_4", + "CMT_TOP_EE2A1_1" + ], + [ + "CMT_FIFO_L_FAN3_8", + "CMT_TOP_FAN3_5" + ], + [ + "CMT_FIFO_L_FAN5_6", + "CMT_TOP_FAN5_3" + ], + [ + "CMT_FIFO_EL1BEG0_3", + "CMT_TOP_EL1BEG0_0" + ], + [ + "CMT_FIFO_LH10_9", + "CMT_TOP_LH10_6" + ], + [ + "CMT_FIFO_L_IMUX39_5", + "CMT_TOP_IMUX39_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_3", + "CMT_TOP_LOGIC_OUTS_L_B10_0" + ], + [ + "CMT_FIFO_WW4A2_9", + "CMT_TOP_WW4A2_6" + ], + [ + "CMT_FIFO_SW4A1_9", + "CMT_TOP_SW4A1_6" + ], + [ + "CMT_FIFO_LH8_5", + "CMT_TOP_LH8_2" + ], + [ + "CMT_FIFO_WW4B3_9", + "CMT_TOP_WW4B3_6" + ], + [ + "CMT_FIFO_SE4BEG3_3", + "CMT_TOP_SE4BEG3_0" + ], + [ + "CMT_FIFO_L_BYP5_8", + "CMT_TOP_BYP5_5" + ], + [ + "CMT_FIFO_NE4BEG2_6", + "CMT_TOP_NE4BEG2_3" + ], + [ + "CMT_FIFO_LH4_9", + "CMT_TOP_LH4_6" + ], + [ + "CMT_FIFO_L_IMUX19_4", + "CMT_TOP_IMUX19_1" + ], + [ + "CMT_FIFO_NW4END0_10", + "CMT_TOP_NW4END0_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_11", + "CMT_TOP_LOGIC_OUTS_L_B22_8" + ], + [ + "CMT_FIFO_L_BYP0_4", + "CMT_TOP_BYP0_1" + ], + [ + "CMT_FIFO_WW4C0_6", + "CMT_TOP_WW4C0_3" + ], + [ + "CMT_FIFO_L_IMUX29_7", + "CMT_TOP_IMUX29_4" + ], + [ + "CMT_FIFO_L_BYP1_11", + "CMT_TOP_BYP1_8" + ], + [ + "CMT_FIFO_LH7_11", + "CMT_TOP_LH7_8" + ], + [ + "CMT_FIFO_WR1END2_4", + "CMT_TOP_WR1END2_1" + ], + [ + "CMT_FIFO_SE2A3_9", + "CMT_TOP_SE2A3_6" + ], + [ + "CMT_FIFO_NE2A1_9", + "CMT_TOP_NE2A1_6" + ], + [ + "CMT_FIFO_L_IMUX8_4", + "CMT_TOP_IMUX8_1" + ], + [ + "CMT_FIFO_EE4B1_10", + "CMT_TOP_EE4B1_7" + ], + [ + "CMT_FIFO_L_IMUX33_9", + "CMT_TOP_IMUX33_6" + ], + [ + "CMT_FIFO_SW2A3_3", + "CMT_TOP_SW2A3_0" + ], + [ + "CMT_FIFO_NW2A3_6", + "CMT_TOP_NW2A3_3" + ], + [ + "CMT_FIFO_WW2END2_8", + "CMT_TOP_WW2END2_5" + ], + [ + "CMT_FIFO_EE2BEG0_8", + "CMT_TOP_EE2BEG0_5" + ], + [ + "CMT_FIFO_LH9_6", + "CMT_TOP_LH9_3" + ], + [ + "CMT_FIFO_L_IMUX2_4", + "CMT_TOP_IMUX2_1" + ], + [ + "CMT_FIFO_L_IMUX5_7", + "CMT_TOP_IMUX5_4" + ], + [ + "CMT_FIFO_L_FAN1_5", + "CMT_TOP_FAN1_2" + ], + [ + "CMT_FIFO_LH5_7", + "CMT_TOP_LH5_4" + ], + [ + "CMT_FIFO_L_IMUX35_10", + "CMT_TOP_IMUX35_7" + ], + [ + "CMT_FIFO_WW4C3_6", + "CMT_TOP_WW4C3_3" + ], + [ + "CMT_FIFO_LH8_6", + "CMT_TOP_LH8_3" + ], + [ + "CMT_FIFO_LH3_6", + "CMT_TOP_LH3_3" + ], + [ + "CMT_FIFO_NE4BEG1_8", + "CMT_TOP_NE4BEG1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_4", + "CMT_TOP_LOGIC_OUTS_L_B20_1" + ], + [ + "CMT_FIFO_EE2BEG3_11", + "CMT_TOP_EE2BEG3_8" + ], + [ + "CMT_FIFO_NW4END2_7", + "CMT_TOP_NW4END2_4" + ], + [ + "CMT_FIFO_WL1END1_3", + "CMT_TOP_WL1END1_0" + ], + [ + "CMT_FIFO_NE4BEG0_3", + "CMT_TOP_NE4BEG0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_3", + "CMT_TOP_LOGIC_OUTS_L_B9_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_7", + "CMT_TOP_LOGIC_OUTS_L_B18_4" + ], + [ + "CMT_FIFO_L_IMUX21_9", + "CMT_TOP_IMUX21_6" + ], + [ + "CMT_FIFO_L_IMUX0_3", + "CMT_TOP_IMUX0_0" + ], + [ + "CMT_FIFO_WW4B0_5", + "CMT_TOP_WW4B0_2" + ], + [ + "CMT_FIFO_WW4END1_3", + "CMT_TOP_WW4END1_0" + ], + [ + "CMT_FIFO_WW2END3_8", + "CMT_TOP_WW2END3_5" + ], + [ + "CMT_FIFO_EE4A0_8", + "CMT_TOP_EE4A0_5" + ], + [ + "CMT_FIFO_WW4END1_4", + "CMT_TOP_WW4END1_1" + ], + [ + "CMT_FIFO_LH2_4", + "CMT_TOP_LH2_1" + ], + [ + "CMT_FIFO_WW4C3_3", + "CMT_TOP_WW4C3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_10", + "CMT_TOP_LOGIC_OUTS_L_B15_7" + ], + [ + "CMT_FIFO_L_BYP5_10", + "CMT_TOP_BYP5_7" + ], + [ + "CMT_FIFO_EE4A3_3", + "CMT_TOP_EE4A3_0" + ], + [ + "CMT_FIFO_EE4A1_11", + "CMT_TOP_EE4A1_8" + ], + [ + "CMT_FIFO_L_IMUX46_6", + "CMT_TOP_IMUX46_3" + ], + [ + "CMT_FIFO_SW4A1_10", + "CMT_TOP_SW4A1_7" + ], + [ + "CMT_FIFO_L_IMUX20_8", + "CMT_TOP_IMUX20_5" + ], + [ + "CMT_FIFO_LH7_5", + "CMT_TOP_LH7_2" + ], + [ + "CMT_FIFO_L_IMUX31_3", + "CMT_TOP_IMUX31_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_3", + "CMT_TOP_LOGIC_OUTS_L_B11_0" + ], + [ + "CMT_FIFO_L_IMUX17_6", + "CMT_TOP_IMUX17_3" + ], + [ + "CMT_FIFO_WL1END0_8", + "CMT_TOP_WL1END0_5" + ], + [ + "CMT_FIFO_WR1END3_7", + "CMT_TOP_WR1END3_4" + ], + [ + "CMT_FIFO_SW4A3_11", + "CMT_TOP_SW4A3_8" + ], + [ + "CMT_FIFO_L_IMUX2_7", + "CMT_TOP_IMUX2_4" + ], + [ + "CMT_FIFO_SW2A3_4", + "CMT_TOP_SW2A3_1" + ], + [ + "CMT_FIFO_SE4BEG3_4", + "CMT_TOP_SE4BEG3_1" + ], + [ + "CMT_FIFO_EE2A0_3", + "CMT_TOP_EE2A0_0" + ], + [ + "CMT_FIFO_ER1BEG1_8", + "CMT_TOP_ER1BEG1_5" + ], + [ + "CMT_FIFO_L_IMUX47_11", + "CMT_TOP_IMUX47_8" + ], + [ + "CMT_FIFO_L_IMUX28_5", + "CMT_TOP_IMUX28_2" + ], + [ + "CMT_FIFO_L_FAN6_6", + "CMT_TOP_FAN6_3" + ], + [ + "CMT_FIFO_L_IMUX47_7", + "CMT_TOP_IMUX47_4" + ], + [ + "CMT_FIFO_SW4END0_7", + "CMT_TOP_SW4END0_4" + ], + [ + "CMT_FIFO_L_IMUX13_4", + "CMT_TOP_IMUX13_1" + ], + [ + "CMT_FIFO_SW4A1_4", + "CMT_TOP_SW4A1_1" + ], + [ + "CMT_FIFO_L_BYP6_10", + "CMT_TOP_BYP6_7" + ], + [ + "CMT_FIFO_NW4END0_7", + "CMT_TOP_NW4END0_4" + ], + [ + "CMT_FIFO_SE4BEG1_6", + "CMT_TOP_SE4BEG1_3" + ], + [ + "CMT_FIFO_LH5_11", + "CMT_TOP_LH5_8" + ], + [ + "CMT_FIFO_EE2BEG0_6", + "CMT_TOP_EE2BEG0_3" + ], + [ + "CMT_FIFO_L_BYP6_6", + "CMT_TOP_BYP6_3" + ], + [ + "CMT_FIFO_L_IMUX27_8", + "CMT_TOP_IMUX27_5" + ], + [ + "CMT_FIFO_NW4A2_5", + "CMT_TOP_NW4A2_2" + ], + [ + "CMT_FIFO_L_IMUX24_5", + "CMT_TOP_IMUX24_2" + ], + [ + "CMT_FIFO_L_IMUX32_7", + "CMT_TOP_IMUX32_4" + ], + [ + "CMT_FIFO_L_IMUX37_5", + "CMT_TOP_IMUX37_2" + ], + [ + "CMT_FIFO_LH2_9", + "CMT_TOP_LH2_6" + ], + [ + "CMT_FIFO_WW4END3_8", + "CMT_TOP_WW4END3_5" + ], + [ + "CMT_FIFO_EE4C2_9", + "CMT_TOP_EE4C2_6" + ], + [ + "CMT_FIFO_SW4A1_8", + "CMT_TOP_SW4A1_5" + ], + [ + "CMT_FIFO_NE4BEG0_5", + "CMT_TOP_NE4BEG0_2" + ], + [ + "CMT_FIFO_L_CLK0_6", + "CMT_TOP_CLK0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_4", + "CMT_TOP_LOGIC_OUTS_L_B17_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_5", + "CMT_TOP_LOGIC_OUTS_L_B18_2" + ], + [ + "CMT_FIFO_SW2A2_9", + "CMT_TOP_SW2A2_6" + ], + [ + "CMT_FIFO_LH4_11", + "CMT_TOP_LH4_8" + ], + [ + "CMT_FIFO_SE4C0_10", + "CMT_TOP_SE4C0_7" + ], + [ + "CMT_FIFO_EL1BEG0_11", + "CMT_TOP_EL1BEG0_8" + ], + [ + "CMT_FIFO_EE2A2_8", + "CMT_TOP_EE2A2_5" + ], + [ + "CMT_FIFO_EE4C0_7", + "CMT_TOP_EE4C0_4" + ], + [ + "CMT_FIFO_WW2END1_9", + "CMT_TOP_WW2END1_6" + ], + [ + "CMT_FIFO_WW2END2_3", + "CMT_TOP_WW2END2_0" + ], + [ + "CMT_FIFO_SE4C0_9", + "CMT_TOP_SE4C0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_7", + "CMT_TOP_LOGIC_OUTS_L_B15_4" + ], + [ + "CMT_FIFO_L_IMUX15_8", + "CMT_TOP_IMUX15_5" + ], + [ + "CMT_FIFO_L_BYP2_6", + "CMT_TOP_BYP2_3" + ], + [ + "CMT_FIFO_L_CTRL0_10", + "CMT_TOP_CTRL0_7" + ], + [ + "CMT_FIFO_SE4C3_8", + "CMT_TOP_SE4C3_5" + ], + [ + "CMT_FIFO_L_IMUX25_9", + "CMT_TOP_IMUX25_6" + ], + [ + "CMT_FIFO_L_IMUX36_10", + "CMT_TOP_IMUX36_7" + ], + [ + "CMT_FIFO_LH7_7", + "CMT_TOP_LH7_4" + ], + [ + "CMT_FIFO_SE4BEG0_10", + "CMT_TOP_SE4BEG0_7" + ], + [ + "CMT_FIFO_EE4B3_6", + "CMT_TOP_EE4B3_3" + ], + [ + "CMT_FIFO_L_IMUX1_6", + "CMT_TOP_IMUX1_3" + ], + [ + "CMT_FIFO_NE4C1_7", + "CMT_TOP_NE4C1_4" + ], + [ + "CMT_FIFO_NW4END1_9", + "CMT_TOP_NW4END1_6" + ], + [ + "CMT_FIFO_NW4A2_4", + "CMT_TOP_NW4A2_1" + ], + [ + "CMT_FIFO_EE4A2_3", + "CMT_TOP_EE4A2_0" + ], + [ + "CMT_FIFO_WR1END2_9", + "CMT_TOP_WR1END2_6" + ], + [ + "CMT_FIFO_L_CTRL0_7", + "CMT_TOP_CTRL0_4" + ], + [ + "CMT_FIFO_SE4BEG1_11", + "CMT_TOP_SE4BEG1_8" + ], + [ + "CMT_FIFO_L_BYP7_10", + "CMT_TOP_BYP7_7" + ], + [ + "CMT_FIFO_EE4C1_10", + "CMT_TOP_EE4C1_7" + ], + [ + "CMT_FIFO_EE4C1_9", + "CMT_TOP_EE4C1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_10", + "CMT_TOP_LOGIC_OUTS_L_B4_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_3", + "CMT_TOP_LOGIC_OUTS_L_B6_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_4", + "CMT_TOP_LOGIC_OUTS_L_B3_1" + ], + [ + "CMT_FIFO_L_IMUX14_5", + "CMT_TOP_IMUX14_2" + ], + [ + "CMT_FIFO_L_IMUX27_10", + "CMT_TOP_IMUX27_7" + ], + [ + "CMT_FIFO_SE4C1_11", + "CMT_TOP_SE4C1_8" + ], + [ + "CMT_FIFO_NW2A2_6", + "CMT_TOP_NW2A2_3" + ], + [ + "CMT_FIFO_LH7_4", + "CMT_TOP_LH7_1" + ], + [ + "CMT_FIFO_LH6_7", + "CMT_TOP_LH6_4" + ], + [ + "CMT_FIFO_L_FAN6_7", + "CMT_TOP_FAN6_4" + ], + [ + "CMT_FIFO_SW2A2_3", + "CMT_TOP_SW2A2_0" + ], + [ + "CMT_FIFO_EE4C1_3", + "CMT_TOP_EE4C1_0" + ], + [ + "CMT_FIFO_L_IMUX18_8", + "CMT_TOP_IMUX18_5" + ], + [ + "CMT_FIFO_EL1BEG0_6", + "CMT_TOP_EL1BEG0_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "CMT_TOP_ICLKDIV_1" + ], + [ + "CMT_FIFO_L_IMUX30_7", + "CMT_TOP_IMUX30_4" + ], + [ + "CMT_FIFO_WW2A1_9", + "CMT_TOP_WW2A1_6" + ], + [ + "CMT_FIFO_EE2BEG2_9", + "CMT_TOP_EE2BEG2_6" + ], + [ + "CMT_FIFO_WW4A3_6", + "CMT_TOP_WW4A3_3" + ], + [ + "CMT_FIFO_NE4C0_7", + "CMT_TOP_NE4C0_4" + ], + [ + "CMT_FIFO_SE4BEG2_8", + "CMT_TOP_SE4BEG2_5" + ], + [ + "CMT_FIFO_EE4A1_5", + "CMT_TOP_EE4A1_2" + ], + [ + "CMT_FIFO_LH8_8", + "CMT_TOP_LH8_5" + ], + [ + "CMT_FIFO_L_IMUX11_8", + "CMT_TOP_IMUX11_5" + ], + [ + "CMT_FIFO_WL1END2_7", + "CMT_TOP_WL1END2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_3", + "CMT_TOP_LOGIC_OUTS_L_B21_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_5", + "CMT_TOP_LOGIC_OUTS_L_B23_2" + ], + [ + "CMT_FIFO_L_IMUX27_6", + "CMT_TOP_IMUX27_3" + ], + [ + "CMT_FIFO_LH11_10", + "CMT_TOP_LH11_7" + ], + [ + "CMT_FIFO_L_IMUX38_6", + "CMT_TOP_IMUX38_3" + ], + [ + "CMT_FIFO_L_CTRL0_5", + "CMT_TOP_CTRL0_2" + ], + [ + "CMT_FIFO_WW2END3_3", + "CMT_TOP_WW2END3_0" + ], + [ + "CMT_FIFO_SE4BEG1_9", + "CMT_TOP_SE4BEG1_6" + ], + [ + "CMT_FIFO_NE2A0_6", + "CMT_TOP_NE2A0_3" + ], + [ + "CMT_FIFO_SE2A3_7", + "CMT_TOP_SE2A3_4" + ], + [ + "CMT_FIFO_ER1BEG2_5", + "CMT_TOP_ER1BEG2_2" + ], + [ + "CMT_FIFO_SE4BEG2_11", + "CMT_TOP_SE4BEG2_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "CMT_TOP_ICLKDIV_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "CMT_TOP_ICLK_6" + ], + [ + "CMT_FIFO_NE2A3_10", + "CMT_TOP_NE2A3_7" + ], + [ + "CMT_FIFO_L_BYP7_8", + "CMT_TOP_BYP7_5" + ], + [ + "CMT_FIFO_L_IMUX34_10", + "CMT_TOP_IMUX34_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_9", + "CMT_TOP_LOGIC_OUTS_L_B5_6" + ], + [ + "CMT_FIFO_L_IMUX6_3", + "CMT_TOP_IMUX6_0" + ], + [ + "CMT_FIFO_WW4A2_4", + "CMT_TOP_WW4A2_1" + ], + [ + "CMT_FIFO_SE2A1_10", + "CMT_TOP_SE2A1_7" + ], + [ + "CMT_FIFO_L_IMUX42_5", + "CMT_TOP_IMUX42_2" + ], + [ + "CMT_FIFO_WR1END3_3", + "CMT_TOP_WR1END3_0" + ], + [ + "CMT_FIFO_WR1END3_9", + "CMT_TOP_WR1END3_6" + ], + [ + "CMT_FIFO_L_CLK0_11", + "CMT_TOP_CLK0_8" + ], + [ + "CMT_FIFO_L_IMUX36_6", + "CMT_TOP_IMUX36_3" + ], + [ + "CMT_FIFO_SW4END0_5", + "CMT_TOP_SW4END0_2" + ], + [ + "CMT_FIFO_SE4BEG1_7", + "CMT_TOP_SE4BEG1_4" + ], + [ + "CMT_FIFO_NW4A0_4", + "CMT_TOP_NW4A0_1" + ], + [ + "CMT_FIFO_LH2_7", + "CMT_TOP_LH2_4" + ], + [ + "CMT_FIFO_L_IMUX42_3", + "CMT_TOP_IMUX42_0" + ], + [ + "CMT_FIFO_EE4BEG0_6", + "CMT_TOP_EE4BEG0_3" + ], + [ + "CMT_FIFO_EL1BEG0_5", + "CMT_TOP_EL1BEG0_2" + ], + [ + "CMT_FIFO_NE4BEG0_8", + "CMT_TOP_NE4BEG0_5" + ], + [ + "CMT_FIFO_WW2A1_11", + "CMT_TOP_WW2A1_8" + ], + [ + "CMT_FIFO_SW4END3_8", + "CMT_TOP_SW4END3_5" + ], + [ + "CMT_FIFO_L_BYP2_9", + "CMT_TOP_BYP2_6" + ], + [ + "CMT_FIFO_LH1_3", + "CMT_TOP_LH1_0" + ], + [ + "CMT_FIFO_L_BYP0_8", + "CMT_TOP_BYP0_5" + ], + [ + "CMT_FIFO_NE4C0_4", + "CMT_TOP_NE4C0_1" + ], + [ + "CMT_FIFO_L_IMUX45_6", + "CMT_TOP_IMUX45_3" + ], + [ + "CMT_FIFO_L_FAN3_3", + "CMT_TOP_FAN3_0" + ], + [ + "CMT_FIFO_SW4A0_4", + "CMT_TOP_SW4A0_1" + ], + [ + "CMT_FIFO_ER1BEG0_5", + "CMT_TOP_ER1BEG0_2" + ], + [ + "CMT_FIFO_NW4END3_9", + "CMT_TOP_NW4END3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_9", + "CMT_TOP_LOGIC_OUTS_L_B23_6" + ], + [ + "CMT_FIFO_SE4BEG2_4", + "CMT_TOP_SE4BEG2_1" + ], + [ + "CMT_FIFO_NW4END2_9", + "CMT_TOP_NW4END2_6" + ], + [ + "CMT_FIFO_EE4B2_7", + "CMT_TOP_EE4B2_4" + ], + [ + "CMT_FIFO_NE4BEG1_4", + "CMT_TOP_NE4BEG1_1" + ], + [ + "CMT_FIFO_WR1END1_9", + "CMT_TOP_WR1END1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_8", + "CMT_TOP_LOGIC_OUTS_L_B3_5" + ], + [ + "CMT_FIFO_WW4B1_3", + "CMT_TOP_WW4B1_0" + ], + [ + "CMT_FIFO_L_IMUX21_4", + "CMT_TOP_IMUX21_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_5", + "CMT_TOP_LOGIC_OUTS_L_B21_2" + ], + [ + "CMT_FIFO_NW2A1_5", + "CMT_TOP_NW2A1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "CMT_TOP_ICLKDIV_8" + ], + [ + "CMT_FIFO_L_CTRL0_11", + "CMT_TOP_CTRL0_8" + ], + [ + "CMT_FIFO_WW4B0_6", + "CMT_TOP_WW4B0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_7", + "CMT_TOP_LOGIC_OUTS_L_B6_4" + ], + [ + "CMT_FIFO_L_BYP0_10", + "CMT_TOP_BYP0_7" + ], + [ + "CMT_FIFO_WW4B1_10", + "CMT_TOP_WW4B1_7" + ], + [ + "CMT_FIFO_L_IMUX11_5", + "CMT_TOP_IMUX11_2" + ], + [ + "CMT_FIFO_EE4C0_3", + "CMT_TOP_EE4C0_0" + ], + [ + "CMT_FIFO_L_IMUX25_4", + "CMT_TOP_IMUX25_1" + ], + [ + "CMT_FIFO_L_FAN4_7", + "CMT_TOP_FAN4_4" + ], + [ + "CMT_FIFO_EE4C0_11", + "CMT_TOP_EE4C0_8" + ], + [ + "CMT_FIFO_NE4C3_4", + "CMT_TOP_NE4C3_1" + ], + [ + "CMT_FIFO_WR1END2_7", + "CMT_TOP_WR1END2_4" + ], + [ + "CMT_FIFO_L_IMUX22_11", + "CMT_TOP_IMUX22_8" + ], + [ + "CMT_FIFO_L_IMUX8_3", + "CMT_TOP_IMUX8_0" + ], + [ + "CMT_FIFO_LH11_6", + "CMT_TOP_LH11_3" + ], + [ + "CMT_FIFO_EE4A2_5", + "CMT_TOP_EE4A2_2" + ], + [ + "CMT_FIFO_EE4A3_11", + "CMT_TOP_EE4A3_8" + ], + [ + "CMT_FIFO_L_IMUX40_6", + "CMT_TOP_IMUX40_3" + ], + [ + "CMT_FIFO_SW4END0_8", + "CMT_TOP_SW4END0_5" + ], + [ + "CMT_FIFO_WL1END2_6", + "CMT_TOP_WL1END2_3" + ], + [ + "CMT_FIFO_SW2A2_7", + "CMT_TOP_SW2A2_4" + ], + [ + "CMT_FIFO_NE4BEG1_5", + "CMT_TOP_NE4BEG1_2" + ], + [ + "CMT_FIFO_LH9_9", + "CMT_TOP_LH9_6" + ], + [ + "CMT_FIFO_WW4END0_11", + "CMT_TOP_WW4END0_8" + ], + [ + "CMT_FIFO_EE4C2_6", + "CMT_TOP_EE4C2_3" + ], + [ + "CMT_FIFO_NW4END1_7", + "CMT_TOP_NW4END1_4" + ], + [ + "CMT_FIFO_EE2A3_6", + "CMT_TOP_EE2A3_3" + ], + [ + "CMT_FIFO_L_IMUX19_8", + "CMT_TOP_IMUX19_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_0" + ], + [ + "CMT_FIFO_WW2A1_4", + "CMT_TOP_WW2A1_1" + ], + [ + "CMT_FIFO_L_BYP5_3", + "CMT_TOP_BYP5_0" + ], + [ + "CMT_FIFO_WW4END0_7", + "CMT_TOP_WW4END0_4" + ], + [ + "CMT_FIFO_NE4C2_6", + "CMT_TOP_NE4C2_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "CMT_TOP_OCLKDIV_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "CMT_TOP_OCLK_4" + ], + [ + "CMT_FIFO_EE4B3_10", + "CMT_TOP_EE4B3_7" + ], + [ + "CMT_FIFO_LH10_6", + "CMT_TOP_LH10_3" + ], + [ + "CMT_FIFO_L_IMUX14_8", + "CMT_TOP_IMUX14_5" + ], + [ + "CMT_FIFO_L_FAN1_4", + "CMT_TOP_FAN1_1" + ], + [ + "CMT_FIFO_SE4C2_3", + "CMT_TOP_SE4C2_0" + ], + [ + "CMT_FIFO_SW4END3_9", + "CMT_TOP_SW4END3_6" + ], + [ + "CMT_FIFO_WL1END3_7", + "CMT_TOP_WL1END3_4" + ], + [ + "CMT_FIFO_EE2A3_3", + "CMT_TOP_EE2A3_0" + ], + [ + "CMT_FIFO_WW4B0_3", + "CMT_TOP_WW4B0_0" + ], + [ + "CMT_FIFO_NW4END0_5", + "CMT_TOP_NW4END0_2" + ], + [ + "CMT_FIFO_WW4B0_7", + "CMT_TOP_WW4B0_4" + ], + [ + "CMT_FIFO_L_FAN3_11", + "CMT_TOP_FAN3_8" + ], + [ + "CMT_FIFO_NW2A0_8", + "CMT_TOP_NW2A0_5" + ], + [ + "CMT_FIFO_L_IMUX20_6", + "CMT_TOP_IMUX20_3" + ], + [ + "CMT_FIFO_ER1BEG2_10", + "CMT_TOP_ER1BEG2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_9", + "CMT_TOP_LOGIC_OUTS_L_B16_6" + ], + [ + "CMT_FIFO_L_IMUX12_5", + "CMT_TOP_IMUX12_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_8", + "CMT_TOP_LOGIC_OUTS_L_B19_5" + ], + [ + "CMT_FIFO_MONITOR_N_4", + "CMT_TOP_MONITOR_N_1" + ], + [ + "CMT_FIFO_NE4BEG0_10", + "CMT_TOP_NE4BEG0_7" + ], + [ + "CMT_FIFO_L_IMUX38_3", + "CMT_TOP_IMUX38_0" + ], + [ + "CMT_FIFO_L_BYP6_3", + "CMT_TOP_BYP6_0" + ], + [ + "CMT_FIFO_WW4END3_11", + "CMT_TOP_WW4END3_8" + ], + [ + "CMT_FIFO_SW4A2_6", + "CMT_TOP_SW4A2_3" + ], + [ + "CMT_FIFO_L_FAN2_3", + "CMT_TOP_FAN2_0" + ], + [ + "CMT_FIFO_SE2A2_7", + "CMT_TOP_SE2A2_4" + ], + [ + "CMT_FIFO_L_FAN7_11", + "CMT_TOP_FAN7_8" + ], + [ + "CMT_FIFO_NW4A1_9", + "CMT_TOP_NW4A1_6" + ], + [ + "CMT_FIFO_L_IMUX15_6", + "CMT_TOP_IMUX15_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_9", + "CMT_TOP_LOGIC_OUTS_L_B2_6" + ], + [ + "CMT_FIFO_WW4A3_5", + "CMT_TOP_WW4A3_2" + ], + [ + "CMT_FIFO_L_IMUX3_4", + "CMT_TOP_IMUX3_1" + ], + [ + "CMT_FIFO_WW4END2_9", + "CMT_TOP_WW4END2_6" + ], + [ + "CMT_FIFO_EE4C1_5", + "CMT_TOP_EE4C1_2" + ], + [ + "CMT_FIFO_L_IMUX45_10", + "CMT_TOP_IMUX45_7" + ], + [ + "CMT_FIFO_EL1BEG0_4", + "CMT_TOP_EL1BEG0_1" + ], + [ + "CMT_FIFO_L_IMUX23_11", + "CMT_TOP_IMUX23_8" + ], + [ + "CMT_FIFO_WW2A3_7", + "CMT_TOP_WW2A3_4" + ], + [ + "CMT_FIFO_EE2BEG3_8", + "CMT_TOP_EE2BEG3_5" + ], + [ + "CMT_FIFO_LH3_9", + "CMT_TOP_LH3_6" + ], + [ + "CMT_FIFO_WW4END1_9", + "CMT_TOP_WW4END1_6" + ], + [ + "CMT_FIFO_L_BYP1_3", + "CMT_TOP_BYP1_0" + ], + [ + "CMT_FIFO_EE2A1_7", + "CMT_TOP_EE2A1_4" + ], + [ + "CMT_FIFO_EE2BEG0_10", + "CMT_TOP_EE2BEG0_7" + ], + [ + "CMT_FIFO_NE2A0_5", + "CMT_TOP_NE2A0_2" + ], + [ + "CMT_FIFO_EE4BEG3_4", + "CMT_TOP_EE4BEG3_1" + ], + [ + "CMT_FIFO_LH1_7", + "CMT_TOP_LH1_4" + ], + [ + "CMT_FIFO_L_IMUX9_7", + "CMT_TOP_IMUX9_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_8", + "CMT_TOP_LOGIC_OUTS_L_B8_5" + ], + [ + "CMT_FIFO_WL1END3_10", + "CMT_TOP_WL1END3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_6", + "CMT_TOP_LOGIC_OUTS_L_B0_3" + ], + [ + "CMT_FIFO_L_IMUX36_8", + "CMT_TOP_IMUX36_5" + ], + [ + "CMT_FIFO_LH9_11", + "CMT_TOP_LH9_8" + ], + [ + "CMT_FIFO_L_FAN0_3", + "CMT_TOP_FAN0_0" + ], + [ + "CMT_FIFO_SW2A0_8", + "CMT_TOP_SW2A0_5" + ], + [ + "CMT_FIFO_LH8_3", + "CMT_TOP_LH8_0" + ], + [ + "CMT_FIFO_L_BYP1_10", + "CMT_TOP_BYP1_7" + ], + [ + "CMT_FIFO_SW2A0_3", + "CMT_TOP_SW2A0_0" + ], + [ + "CMT_FIFO_EE4BEG2_11", + "CMT_TOP_EE4BEG2_8" + ], + [ + "CMT_FIFO_L_IMUX31_10", + "CMT_TOP_IMUX31_7" + ], + [ + "CMT_FIFO_L_IMUX23_8", + "CMT_TOP_IMUX23_5" + ], + [ + "CMT_FIFO_NE2A2_4", + "CMT_TOP_NE2A2_1" + ], + [ + "CMT_FIFO_WW2A2_4", + "CMT_TOP_WW2A2_1" + ], + [ + "CMT_FIFO_L_IMUX47_5", + "CMT_TOP_IMUX47_2" + ], + [ + "CMT_FIFO_L_IMUX33_5", + "CMT_TOP_IMUX33_2" + ], + [ + "CMT_FIFO_L_IMUX16_11", + "CMT_TOP_IMUX16_8" + ], + [ + "CMT_FIFO_EE4B3_8", + "CMT_TOP_EE4B3_5" + ], + [ + "CMT_FIFO_EE2BEG2_8", + "CMT_TOP_EE2BEG2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_5", + "CMT_TOP_LOGIC_OUTS_L_B5_2" + ], + [ + "CMT_FIFO_L_IMUX31_9", + "CMT_TOP_IMUX31_6" + ], + [ + "CMT_FIFO_EL1BEG1_10", + "CMT_TOP_EL1BEG1_7" + ], + [ + "CMT_FIFO_L_IMUX33_4", + "CMT_TOP_IMUX33_1" + ], + [ + "CMT_FIFO_L_FAN6_10", + "CMT_TOP_FAN6_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_10", + "CMT_TOP_LOGIC_OUTS_L_B23_7" + ], + [ + "CMT_FIFO_NE4BEG3_5", + "CMT_TOP_NE4BEG3_2" + ], + [ + "CMT_FIFO_NE2A3_4", + "CMT_TOP_NE2A3_1" + ], + [ + "CMT_FIFO_EE2BEG2_11", + "CMT_TOP_EE2BEG2_8" + ], + [ + "CMT_FIFO_EE4B2_9", + "CMT_TOP_EE4B2_6" + ], + [ + "CMT_FIFO_L_IMUX26_11", + "CMT_TOP_IMUX26_8" + ], + [ + "CMT_FIFO_WL1END0_11", + "CMT_TOP_WL1END0_8" + ], + [ + "CMT_FIFO_WL1END2_10", + "CMT_TOP_WL1END2_7" + ], + [ + "CMT_FIFO_ER1BEG3_5", + "CMT_TOP_ER1BEG3_2" + ], + [ + "CMT_FIFO_WW4C1_9", + "CMT_TOP_WW4C1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_8", + "CMT_TOP_LOGIC_OUTS_L_B17_5" + ], + [ + "CMT_FIFO_WL1END2_8", + "CMT_TOP_WL1END2_5" + ], + [ + "CMT_FIFO_L_IMUX18_3", + "CMT_TOP_IMUX18_0" + ], + [ + "CMT_FIFO_NW2A2_11", + "CMT_TOP_NW2A2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_5", + "CMT_TOP_LOGIC_OUTS_L_B2_2" + ], + [ + "CMT_FIFO_SE2A0_8", + "CMT_TOP_SE2A0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_9", + "CMT_TOP_LOGIC_OUTS_L_B11_6" + ], + [ + "CMT_FIFO_L_IMUX34_5", + "CMT_TOP_IMUX34_2" + ], + [ + "CMT_FIFO_EL1BEG1_11", + "CMT_TOP_EL1BEG1_8" + ], + [ + "CMT_FIFO_L_IMUX32_8", + "CMT_TOP_IMUX32_5" + ], + [ + "CMT_FIFO_L_IMUX19_10", + "CMT_TOP_IMUX19_7" + ], + [ + "CMT_FIFO_EE4C1_4", + "CMT_TOP_EE4C1_1" + ], + [ + "CMT_FIFO_ER1BEG2_4", + "CMT_TOP_ER1BEG2_1" + ], + [ + "CMT_FIFO_NE4C1_5", + "CMT_TOP_NE4C1_2" + ], + [ + "CMT_FIFO_WR1END1_4", + "CMT_TOP_WR1END1_1" + ], + [ + "CMT_FIFO_SW2A0_11", + "CMT_TOP_SW2A0_8" + ], + [ + "CMT_FIFO_SE4C3_10", + "CMT_TOP_SE4C3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_10", + "CMT_TOP_LOGIC_OUTS_L_B12_7" + ], + [ + "CMT_FIFO_L_CTRL0_6", + "CMT_TOP_CTRL0_3" + ], + [ + "CMT_FIFO_EE4BEG1_7", + "CMT_TOP_EE4BEG1_4" + ], + [ + "CMT_FIFO_L_CTRL0_9", + "CMT_TOP_CTRL0_6" + ], + [ + "CMT_FIFO_EE2BEG0_4", + "CMT_TOP_EE2BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_4", + "CMT_TOP_LOGIC_OUTS_L_B10_1" + ], + [ + "CMT_FIFO_NW2A2_9", + "CMT_TOP_NW2A2_6" + ], + [ + "CMT_FIFO_MONITOR_P_4", + "CMT_TOP_MONITOR_P_1" + ], + [ + "CMT_FIFO_NW2A2_8", + "CMT_TOP_NW2A2_5" + ], + [ + "CMT_FIFO_L_BYP2_11", + "CMT_TOP_BYP2_8" + ], + [ + "CMT_FIFO_L_IMUX18_10", + "CMT_TOP_IMUX18_7" + ], + [ + "CMT_FIFO_WW4A2_10", + "CMT_TOP_WW4A2_7" + ], + [ + "CMT_FIFO_L_IMUX5_6", + "CMT_TOP_IMUX5_3" + ], + [ + "CMT_FIFO_L_IMUX28_6", + "CMT_TOP_IMUX28_3" + ], + [ + "CMT_FIFO_L_BYP3_4", + "CMT_TOP_BYP3_1" + ], + [ + "CMT_FIFO_L_IMUX20_11", + "CMT_TOP_IMUX20_8" + ], + [ + "CMT_FIFO_SW2A1_11", + "CMT_TOP_SW2A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_11", + "CMT_TOP_LOGIC_OUTS_L_B13_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_8", + "CMT_TOP_LOGIC_OUTS_L_B16_5" + ], + [ + "CMT_FIFO_WL1END1_8", + "CMT_TOP_WL1END1_5" + ], + [ + "CMT_FIFO_L_IMUX37_9", + "CMT_TOP_IMUX37_6" + ], + [ + "CMT_FIFO_ER1BEG2_8", + "CMT_TOP_ER1BEG2_5" + ], + [ + "CMT_FIFO_WL1END0_4", + "CMT_TOP_WL1END0_1" + ], + [ + "CMT_FIFO_EE4BEG0_7", + "CMT_TOP_EE4BEG0_4" + ], + [ + "CMT_FIFO_LH7_9", + "CMT_TOP_LH7_6" + ], + [ + "CMT_FIFO_LH1_8", + "CMT_TOP_LH1_5" + ], + [ + "CMT_FIFO_L_CTRL1_10", + "CMT_TOP_CTRL1_7" + ], + [ + "CMT_FIFO_NE4C3_6", + "CMT_TOP_NE4C3_3" + ], + [ + "CMT_FIFO_SW4END2_11", + "CMT_TOP_SW4END2_8" + ], + [ + "CMT_FIFO_NW4A3_9", + "CMT_TOP_NW4A3_6" + ], + [ + "CMT_FIFO_L_IMUX8_8", + "CMT_TOP_IMUX8_5" + ], + [ + "CMT_FIFO_L_FAN4_9", + "CMT_TOP_FAN4_6" + ], + [ + "CMT_FIFO_EE4BEG0_8", + "CMT_TOP_EE4BEG0_5" + ], + [ + "CMT_FIFO_SE4C3_3", + "CMT_TOP_SE4C3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_7", + "CMT_TOP_LOGIC_OUTS_L_B9_4" + ], + [ + "CMT_FIFO_WW4A3_4", + "CMT_TOP_WW4A3_1" + ], + [ + "CMT_FIFO_L_BYP6_8", + "CMT_TOP_BYP6_5" + ], + [ + "CMT_FIFO_WW4B3_7", + "CMT_TOP_WW4B3_4" + ], + [ + "CMT_FIFO_L_IMUX18_11", + "CMT_TOP_IMUX18_8" + ], + [ + "CMT_FIFO_L_IMUX31_7", + "CMT_TOP_IMUX31_4" + ], + [ + "CMT_FIFO_L_IMUX3_9", + "CMT_TOP_IMUX3_6" + ], + [ + "CMT_FIFO_NW2A2_3", + "CMT_TOP_NW2A2_0" + ], + [ + "CMT_FIFO_L_IMUX25_3", + "CMT_TOP_IMUX25_0" + ], + [ + "CMT_FIFO_SW4A2_5", + "CMT_TOP_SW4A2_2" + ], + [ + "CMT_FIFO_SE4BEG3_6", + "CMT_TOP_SE4BEG3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_7", + "CMT_TOP_LOGIC_OUTS_L_B13_4" + ], + [ + "CMT_FIFO_L_IMUX11_10", + "CMT_TOP_IMUX11_7" + ], + [ + "CMT_FIFO_L_IMUX9_3", + "CMT_TOP_IMUX9_0" + ], + [ + "CMT_FIFO_WR1END0_11", + "CMT_TOP_WR1END0_8" + ], + [ + "CMT_FIFO_SW4A2_4", + "CMT_TOP_SW4A2_1" + ], + [ + "CMT_FIFO_ER1BEG0_8", + "CMT_TOP_ER1BEG0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_3", + "CMT_TOP_LOGIC_OUTS_L_B3_0" + ], + [ + "CMT_FIFO_SW4A2_10", + "CMT_TOP_SW4A2_7" + ], + [ + "CMT_FIFO_NE4C1_4", + "CMT_TOP_NE4C1_1" + ], + [ + "CMT_FIFO_LH11_8", + "CMT_TOP_LH11_5" + ], + [ + "CMT_FIFO_EE2A3_8", + "CMT_TOP_EE2A3_5" + ], + [ + "CMT_FIFO_NW4A1_5", + "CMT_TOP_NW4A1_2" + ], + [ + "CMT_FIFO_L_IMUX27_11", + "CMT_TOP_IMUX27_8" + ], + [ + "CMT_FIFO_L_FAN2_11", + "CMT_TOP_FAN2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_7", + "CMT_TOP_LOGIC_OUTS_L_B1_4" + ], + [ + "CMT_FIFO_WW4B0_11", + "CMT_TOP_WW4B0_8" + ], + [ + "CMT_FIFO_L_IMUX34_11", + "CMT_TOP_IMUX34_8" + ], + [ + "CMT_FIFO_WL1END3_6", + "CMT_TOP_WL1END3_3" + ], + [ + "CMT_FIFO_SW4A1_6", + "CMT_TOP_SW4A1_3" + ], + [ + "CMT_FIFO_WW2END3_10", + "CMT_TOP_WW2END3_7" + ], + [ + "CMT_FIFO_L_BYP3_8", + "CMT_TOP_BYP3_5" + ], + [ + "CMT_FIFO_WW4END3_7", + "CMT_TOP_WW4END3_4" + ], + [ + "CMT_FIFO_NW4A1_6", + "CMT_TOP_NW4A1_3" + ], + [ + "CMT_FIFO_LH10_11", + "CMT_TOP_LH10_8" + ], + [ + "CMT_FIFO_LH10_8", + "CMT_TOP_LH10_5" + ], + [ + "CMT_FIFO_L_CLK0_3", + "CMT_TOP_CLK0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_6", + "CMT_TOP_LOGIC_OUTS_L_B19_3" + ], + [ + "CMT_FIFO_L_IMUX4_8", + "CMT_TOP_IMUX4_5" + ], + [ + "CMT_FIFO_L_IMUX45_3", + "CMT_TOP_IMUX45_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "CMT_TOP_OCLKDIV_5" + ], + [ + "CMT_FIFO_NW4A0_9", + "CMT_TOP_NW4A0_6" + ], + [ + "CMT_FIFO_EE2BEG2_6", + "CMT_TOP_EE2BEG2_3" + ], + [ + "CMT_FIFO_L_FAN1_3", + "CMT_TOP_FAN1_0" + ], + [ + "CMT_FIFO_L_IMUX4_9", + "CMT_TOP_IMUX4_6" + ], + [ + "CMT_FIFO_WW2A1_3", + "CMT_TOP_WW2A1_0" + ], + [ + "CMT_FIFO_SE2A2_6", + "CMT_TOP_SE2A2_3" + ], + [ + "CMT_FIFO_LH12_3", + "CMT_TOP_LH12_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "CMT_TOP_OCLK_5" + ], + [ + "CMT_FIFO_SE4C1_6", + "CMT_TOP_SE4C1_3" + ], + [ + "CMT_FIFO_ER1BEG1_10", + "CMT_TOP_ER1BEG1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_4", + "CMT_TOP_LOGIC_OUTS_L_B19_1" + ], + [ + "CMT_FIFO_WR1END3_10", + "CMT_TOP_WR1END3_7" + ], + [ + "CMT_FIFO_EE4A1_4", + "CMT_TOP_EE4A1_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "CMT_TOP_OCLKDIV_8" + ], + [ + "CMT_FIFO_L_IMUX31_8", + "CMT_TOP_IMUX31_5" + ], + [ + "CMT_FIFO_EE4BEG1_10", + "CMT_TOP_EE4BEG1_7" + ], + [ + "CMT_FIFO_NE2A3_3", + "CMT_TOP_NE2A3_0" + ], + [ + "CMT_FIFO_L_IMUX15_9", + "CMT_TOP_IMUX15_6" + ], + [ + "CMT_FIFO_L_IMUX45_7", + "CMT_TOP_IMUX45_4" + ], + [ + "CMT_FIFO_WW4END3_6", + "CMT_TOP_WW4END3_3" + ], + [ + "CMT_FIFO_WW4C0_10", + "CMT_TOP_WW4C0_7" + ], + [ + "CMT_FIFO_SE2A3_11", + "CMT_TOP_SE2A3_8" + ], + [ + "CMT_FIFO_ER1BEG2_11", + "CMT_TOP_ER1BEG2_8" + ], + [ + "CMT_FIFO_SW4END2_9", + "CMT_TOP_SW4END2_6" + ], + [ + "CMT_FIFO_SW4A1_5", + "CMT_TOP_SW4A1_2" + ], + [ + "CMT_FIFO_L_IMUX23_9", + "CMT_TOP_IMUX23_6" + ], + [ + "CMT_FIFO_EE2A3_7", + "CMT_TOP_EE2A3_4" + ], + [ + "CMT_FIFO_SW2A1_3", + "CMT_TOP_SW2A1_0" + ], + [ + "CMT_FIFO_EL1BEG2_4", + "CMT_TOP_EL1BEG2_1" + ], + [ + "CMT_FIFO_WW4END2_6", + "CMT_TOP_WW4END2_3" + ], + [ + "CMT_FIFO_EE2BEG0_5", + "CMT_TOP_EE2BEG0_2" + ], + [ + "CMT_FIFO_L_BYP6_11", + "CMT_TOP_BYP6_8" + ], + [ + "CMT_FIFO_EE4A1_6", + "CMT_TOP_EE4A1_3" + ], + [ + "CMT_FIFO_SW2A1_10", + "CMT_TOP_SW2A1_7" + ], + [ + "CMT_FIFO_SW4END1_7", + "CMT_TOP_SW4END1_4" + ], + [ + "CMT_FIFO_WL1END3_11", + "CMT_TOP_WL1END3_8" + ], + [ + "CMT_FIFO_LH2_6", + "CMT_TOP_LH2_3" + ], + [ + "CMT_FIFO_NE2A2_7", + "CMT_TOP_NE2A2_4" + ], + [ + "CMT_FIFO_NE2A1_6", + "CMT_TOP_NE2A1_3" + ], + [ + "CMT_FIFO_WW4END2_4", + "CMT_TOP_WW4END2_1" + ], + [ + "CMT_FIFO_EL1BEG1_9", + "CMT_TOP_EL1BEG1_6" + ], + [ + "CMT_FIFO_L_IMUX13_6", + "CMT_TOP_IMUX13_3" + ], + [ + "CMT_FIFO_NW4A1_3", + "CMT_TOP_NW4A1_0" + ], + [ + "CMT_FIFO_WW4C0_8", + "CMT_TOP_WW4C0_5" + ], + [ + "CMT_FIFO_L_IMUX20_9", + "CMT_TOP_IMUX20_6" + ], + [ + "CMT_FIFO_L_IMUX34_6", + "CMT_TOP_IMUX34_3" + ], + [ + "CMT_FIFO_SE4BEG2_3", + "CMT_TOP_SE4BEG2_0" + ], + [ + "CMT_FIFO_NW2A1_11", + "CMT_TOP_NW2A1_8" + ], + [ + "CMT_FIFO_L_IMUX27_4", + "CMT_TOP_IMUX27_1" + ], + [ + "CMT_FIFO_EE4BEG2_7", + "CMT_TOP_EE4BEG2_4" + ], + [ + "CMT_FIFO_EE2BEG0_3", + "CMT_TOP_EE2BEG0_0" + ], + [ + "CMT_FIFO_L_IMUX1_5", + "CMT_TOP_IMUX1_2" + ], + [ + "CMT_FIFO_L_IMUX27_5", + "CMT_TOP_IMUX27_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "CMT_TOP_ICLKDIV_0" + ], + [ + "CMT_FIFO_SW4A3_5", + "CMT_TOP_SW4A3_2" + ], + [ + "CMT_FIFO_SW4END1_3", + "CMT_TOP_SW4END1_0" + ], + [ + "CMT_FIFO_L_IMUX6_5", + "CMT_TOP_IMUX6_2" + ], + [ + "CMT_FIFO_L_BYP3_11", + "CMT_TOP_BYP3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_4", + "CMT_TOP_LOGIC_OUTS_L_B11_1" + ], + [ + "CMT_FIFO_WW4END2_8", + "CMT_TOP_WW4END2_5" + ], + [ + "CMT_FIFO_SW2A0_10", + "CMT_TOP_SW2A0_7" + ], + [ + "CMT_FIFO_L_FAN3_7", + "CMT_TOP_FAN3_4" + ], + [ + "CMT_FIFO_EE2BEG1_6", + "CMT_TOP_EE2BEG1_3" + ], + [ + "CMT_FIFO_WL1END1_9", + "CMT_TOP_WL1END1_6" + ], + [ + "CMT_FIFO_NW2A0_7", + "CMT_TOP_NW2A0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_4", + "CMT_TOP_LOGIC_OUTS_L_B12_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_8", + "CMT_TOP_LOGIC_OUTS_L_B13_5" + ], + [ + "CMT_FIFO_L_IMUX46_8", + "CMT_TOP_IMUX46_5" + ], + [ + "CMT_FIFO_EE2A1_10", + "CMT_TOP_EE2A1_7" + ], + [ + "CMT_FIFO_EE4B3_5", + "CMT_TOP_EE4B3_2" + ], + [ + "CMT_FIFO_EE4C1_6", + "CMT_TOP_EE4C1_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "CMT_TOP_OCLK_2" + ], + [ + "CMT_FIFO_NW4END2_8", + "CMT_TOP_NW4END2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_8", + "CMT_TOP_LOGIC_OUTS_L_B0_5" + ], + [ + "CMT_FIFO_SE4BEG1_5", + "CMT_TOP_SE4BEG1_2" + ], + [ + "CMT_FIFO_EL1BEG2_8", + "CMT_TOP_EL1BEG2_5" + ], + [ + "CMT_FIFO_EL1BEG3_4", + "CMT_TOP_EL1BEG3_1" + ], + [ + "CMT_FIFO_NW4END1_4", + "CMT_TOP_NW4END1_1" + ], + [ + "CMT_FIFO_LH9_3", + "CMT_TOP_LH9_0" + ], + [ + "CMT_FIFO_SW4A3_3", + "CMT_TOP_SW4A3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_10", + "CMT_TOP_LOGIC_OUTS_L_B22_7" + ], + [ + "CMT_FIFO_L_CLK0_9", + "CMT_TOP_CLK0_6" + ], + [ + "CMT_FIFO_L_PHASER_RDENABLE", + "CMT_PHASER_OUT_B_RDEN_TOFIFO" + ], + [ + "CMT_FIFO_EE4BEG3_8", + "CMT_TOP_EE4BEG3_5" + ], + [ + "CMT_FIFO_NE4BEG1_9", + "CMT_TOP_NE4BEG1_6" + ], + [ + "CMT_FIFO_L_IMUX38_10", + "CMT_TOP_IMUX38_7" + ], + [ + "CMT_FIFO_NE2A1_10", + "CMT_TOP_NE2A1_7" + ], + [ + "CMT_FIFO_EE2A3_11", + "CMT_TOP_EE2A3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_8", + "CMT_TOP_LOGIC_OUTS_L_B20_5" + ], + [ + "CMT_FIFO_SW4END0_6", + "CMT_TOP_SW4END0_3" + ], + [ + "CMT_FIFO_NE4C1_11", + "CMT_TOP_NE4C1_8" + ], + [ + "CMT_FIFO_EE2BEG1_10", + "CMT_TOP_EE2BEG1_7" + ], + [ + "CMT_FIFO_SE4BEG3_10", + "CMT_TOP_SE4BEG3_7" + ], + [ + "CMT_FIFO_LH12_5", + "CMT_TOP_LH12_2" + ], + [ + "CMT_FIFO_WW2END1_4", + "CMT_TOP_WW2END1_1" + ], + [ + "CMT_FIFO_EE4B1_7", + "CMT_TOP_EE4B1_4" + ], + [ + "CMT_FIFO_L_FAN7_10", + "CMT_TOP_FAN7_7" + ], + [ + "CMT_FIFO_SE4BEG3_9", + "CMT_TOP_SE4BEG3_6" + ], + [ + "CMT_FIFO_NW2A1_4", + "CMT_TOP_NW2A1_1" + ], + [ + "CMT_FIFO_L_IMUX32_6", + "CMT_TOP_IMUX32_3" + ], + [ + "CMT_FIFO_EE4B1_6", + "CMT_TOP_EE4B1_3" + ], + [ + "CMT_FIFO_L_BYP0_7", + "CMT_TOP_BYP0_4" + ], + [ + "CMT_FIFO_WW4END1_11", + "CMT_TOP_WW4END1_8" + ], + [ + "CMT_FIFO_L_IMUX1_8", + "CMT_TOP_IMUX1_5" + ], + [ + "CMT_FIFO_SE4C2_5", + "CMT_TOP_SE4C2_2" + ], + [ + "CMT_FIFO_EE4A2_9", + "CMT_TOP_EE4A2_6" + ], + [ + "CMT_FIFO_EE4A2_6", + "CMT_TOP_EE4A2_3" + ], + [ + "CMT_FIFO_LH5_10", + "CMT_TOP_LH5_7" + ], + [ + "CMT_FIFO_MONITOR_N_10", + "CMT_TOP_MONITOR_N_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_11", + "CMT_TOP_LOGIC_OUTS_L_B23_8" + ], + [ + "CMT_FIFO_WL1END1_10", + "CMT_TOP_WL1END1_7" + ], + [ + "CMT_FIFO_WW4C1_10", + "CMT_TOP_WW4C1_7" + ], + [ + "CMT_FIFO_WW4B3_3", + "CMT_TOP_WW4B3_0" + ], + [ + "CMT_FIFO_EE4B0_11", + "CMT_TOP_EE4B0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_9", + "CMT_TOP_LOGIC_OUTS_L_B12_6" + ], + [ + "CMT_FIFO_L_IMUX37_10", + "CMT_TOP_IMUX37_7" + ], + [ + "CMT_FIFO_SW4END3_5", + "CMT_TOP_SW4END3_2" + ], + [ + "CMT_FIFO_L_IMUX35_11", + "CMT_TOP_IMUX35_8" + ], + [ + "CMT_FIFO_LH9_8", + "CMT_TOP_LH9_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_6", + "CMT_TOP_LOGIC_OUTS_L_B18_3" + ], + [ + "CMT_FIFO_EE4C0_8", + "CMT_TOP_EE4C0_5" + ], + [ + "CMT_FIFO_SW4END2_6", + "CMT_TOP_SW4END2_3" + ], + [ + "CMT_FIFO_WR1END1_3", + "CMT_TOP_WR1END1_0" + ], + [ + "CMT_FIFO_EE4C1_11", + "CMT_TOP_EE4C1_8" + ], + [ + "CMT_FIFO_NE4BEG3_10", + "CMT_TOP_NE4BEG3_7" + ], + [ + "CMT_FIFO_EE4A3_8", + "CMT_TOP_EE4A3_5" + ], + [ + "CMT_FIFO_EE4BEG0_3", + "CMT_TOP_EE4BEG0_0" + ], + [ + "CMT_FIFO_L_BYP0_3", + "CMT_TOP_BYP0_0" + ], + [ + "CMT_FIFO_SW2A3_7", + "CMT_TOP_SW2A3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_6", + "CMT_TOP_LOGIC_OUTS_L_B2_3" + ], + [ + "CMT_FIFO_EL1BEG2_11", + "CMT_TOP_EL1BEG2_8" + ], + [ + "CMT_FIFO_EE4A0_6", + "CMT_TOP_EE4A0_3" + ], + [ + "CMT_FIFO_LH5_6", + "CMT_TOP_LH5_3" + ], + [ + "CMT_FIFO_SE4BEG2_6", + "CMT_TOP_SE4BEG2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_7", + "CMT_TOP_LOGIC_OUTS_L_B2_4" + ], + [ + "CMT_FIFO_NE2A0_7", + "CMT_TOP_NE2A0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_7", + "CMT_TOP_LOGIC_OUTS_L_B20_4" + ], + [ + "CMT_FIFO_EE4A3_5", + "CMT_TOP_EE4A3_2" + ], + [ + "CMT_FIFO_LH8_10", + "CMT_TOP_LH8_7" + ], + [ + "CMT_FIFO_NE2A2_3", + "CMT_TOP_NE2A2_0" + ], + [ + "CMT_FIFO_L_IMUX22_3", + "CMT_TOP_IMUX22_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_10", + "CMT_TOP_LOGIC_OUTS_L_B6_7" + ], + [ + "CMT_FIFO_SE4C3_9", + "CMT_TOP_SE4C3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_6", + "CMT_TOP_LOGIC_OUTS_L_B22_3" + ], + [ + "CMT_FIFO_L_FAN0_10", + "CMT_TOP_FAN0_7" + ], + [ + "CMT_FIFO_EE4B2_11", + "CMT_TOP_EE4B2_8" + ], + [ + "CMT_FIFO_LH8_7", + "CMT_TOP_LH8_4" + ], + [ + "CMT_FIFO_L_IMUX10_10", + "CMT_TOP_IMUX10_7" + ], + [ + "CMT_FIFO_L_IMUX40_7", + "CMT_TOP_IMUX40_4" + ], + [ + "CMT_FIFO_WW2END2_7", + "CMT_TOP_WW2END2_4" + ], + [ + "CMT_FIFO_WW2A3_10", + "CMT_TOP_WW2A3_7" + ], + [ + "CMT_FIFO_L_CTRL1_11", + "CMT_TOP_CTRL1_8" + ], + [ + "CMT_FIFO_WW4END0_6", + "CMT_TOP_WW4END0_3" + ], + [ + "CMT_FIFO_SE2A3_10", + "CMT_TOP_SE2A3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_8", + "CMT_TOP_LOGIC_OUTS_L_B1_5" + ], + [ + "CMT_FIFO_EE4C0_9", + "CMT_TOP_EE4C0_6" + ], + [ + "CMT_FIFO_NW2A0_11", + "CMT_TOP_NW2A0_8" + ], + [ + "CMT_FIFO_L_IMUX28_7", + "CMT_TOP_IMUX28_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_9", + "CMT_TOP_LOGIC_OUTS_L_B17_6" + ], + [ + "CMT_FIFO_EL1BEG1_8", + "CMT_TOP_EL1BEG1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_6", + "CMT_TOP_LOGIC_OUTS_L_B17_3" + ], + [ + "CMT_FIFO_L_IMUX26_8", + "CMT_TOP_IMUX26_5" + ], + [ + "CMT_FIFO_L_IMUX42_4", + "CMT_TOP_IMUX42_1" + ], + [ + "CMT_FIFO_L_IMUX46_7", + "CMT_TOP_IMUX46_4" + ], + [ + "CMT_FIFO_L_IMUX10_8", + "CMT_TOP_IMUX10_5" + ], + [ + "CMT_FIFO_SE4C0_5", + "CMT_TOP_SE4C0_2" + ], + [ + "CMT_FIFO_NW4END1_3", + "CMT_TOP_NW4END1_0" + ], + [ + "CMT_FIFO_WW2A0_4", + "CMT_TOP_WW2A0_1" + ], + [ + "CMT_FIFO_L_IMUX12_6", + "CMT_TOP_IMUX12_3" + ], + [ + "CMT_FIFO_WW4B3_5", + "CMT_TOP_WW4B3_2" + ], + [ + "CMT_FIFO_L_CLK1_10", + "CMT_TOP_CLK1_7" + ], + [ + "CMT_FIFO_L_IMUX16_3", + "CMT_TOP_IMUX16_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_3", + "CMT_TOP_LOGIC_OUTS_L_B17_0" + ], + [ + "CMT_FIFO_L_IMUX9_8", + "CMT_TOP_IMUX9_5" + ], + [ + "CMT_FIFO_L_IMUX18_9", + "CMT_TOP_IMUX18_6" + ], + [ + "CMT_FIFO_L_FAN7_3", + "CMT_TOP_FAN7_0" + ], + [ + "CMT_FIFO_L_FAN5_7", + "CMT_TOP_FAN5_4" + ], + [ + "CMT_FIFO_LH5_3", + "CMT_TOP_LH5_0" + ], + [ + "CMT_FIFO_L_IMUX43_5", + "CMT_TOP_IMUX43_2" + ], + [ + "CMT_FIFO_L_IMUX42_8", + "CMT_TOP_IMUX42_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_1" + ], + [ + "CMT_FIFO_EE2BEG3_7", + "CMT_TOP_EE2BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_7", + "CMT_TOP_LOGIC_OUTS_L_B4_4" + ], + [ + "CMT_FIFO_L_IMUX30_9", + "CMT_TOP_IMUX30_6" + ], + [ + "CMT_FIFO_WW4B1_4", + "CMT_TOP_WW4B1_1" + ], + [ + "CMT_FIFO_EE4C2_4", + "CMT_TOP_EE4C2_1" + ], + [ + "CMT_FIFO_L_IMUX26_10", + "CMT_TOP_IMUX26_7" + ], + [ + "CMT_FIFO_EE2A2_10", + "CMT_TOP_EE2A2_7" + ], + [ + "CMT_FIFO_SE2A1_4", + "CMT_TOP_SE2A1_1" + ], + [ + "CMT_FIFO_L_IMUX30_11", + "CMT_TOP_IMUX30_8" + ], + [ + "CMT_FIFO_L_IMUX24_11", + "CMT_TOP_IMUX24_8" + ], + [ + "CMT_FIFO_L_FAN4_6", + "CMT_TOP_FAN4_3" + ], + [ + "CMT_FIFO_WW4B3_8", + "CMT_TOP_WW4B3_5" + ], + [ + "CMT_FIFO_NW4END3_5", + "CMT_TOP_NW4END3_2" + ], + [ + "CMT_FIFO_NW4END0_6", + "CMT_TOP_NW4END0_3" + ], + [ + "CMT_FIFO_L_CTRL0_4", + "CMT_TOP_CTRL0_1" + ], + [ + "CMT_FIFO_EE4C1_7", + "CMT_TOP_EE4C1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_7", + "CMT_TOP_LOGIC_OUTS_L_B19_4" + ], + [ + "CMT_FIFO_WW2A1_8", + "CMT_TOP_WW2A1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_8", + "CMT_TOP_LOGIC_OUTS_L_B2_5" + ], + [ + "CMT_FIFO_SW2A1_5", + "CMT_TOP_SW2A1_2" + ], + [ + "CMT_FIFO_EE4A1_7", + "CMT_TOP_EE4A1_4" + ], + [ + "CMT_FIFO_L_IMUX42_6", + "CMT_TOP_IMUX42_3" + ], + [ + "CMT_FIFO_EE4B2_6", + "CMT_TOP_EE4B2_3" + ], + [ + "CMT_FIFO_WW4C0_9", + "CMT_TOP_WW4C0_6" + ], + [ + "CMT_FIFO_L_FAN4_10", + "CMT_TOP_FAN4_7" + ], + [ + "CMT_FIFO_WW4END0_3", + "CMT_TOP_WW4END0_0" + ], + [ + "CMT_FIFO_NW2A1_6", + "CMT_TOP_NW2A1_3" + ], + [ + "CMT_FIFO_ER1BEG0_7", + "CMT_TOP_ER1BEG0_4" + ], + [ + "CMT_FIFO_EE4BEG3_7", + "CMT_TOP_EE4BEG3_4" + ], + [ + "CMT_FIFO_L_FAN6_5", + "CMT_TOP_FAN6_2" + ], + [ + "CMT_FIFO_L_IMUX6_7", + "CMT_TOP_IMUX6_4" + ], + [ + "CMT_FIFO_EE4A0_3", + "CMT_TOP_EE4A0_0" + ], + [ + "CMT_FIFO_L_IMUX23_3", + "CMT_TOP_IMUX23_0" + ], + [ + "CMT_FIFO_L_IMUX9_10", + "CMT_TOP_IMUX9_7" + ], + [ + "CMT_FIFO_EE4BEG2_8", + "CMT_TOP_EE4BEG2_5" + ], + [ + "CMT_FIFO_LH5_4", + "CMT_TOP_LH5_1" + ], + [ + "CMT_FIFO_WW4A3_9", + "CMT_TOP_WW4A3_6" + ], + [ + "CMT_FIFO_EE4C3_9", + "CMT_TOP_EE4C3_6" + ], + [ + "CMT_FIFO_NE4BEG3_7", + "CMT_TOP_NE4BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_4", + "CMT_TOP_LOGIC_OUTS_L_B22_1" + ], + [ + "CMT_FIFO_L_FAN0_4", + "CMT_TOP_FAN0_1" + ], + [ + "CMT_FIFO_EE2A0_4", + "CMT_TOP_EE2A0_1" + ], + [ + "CMT_FIFO_LH4_5", + "CMT_TOP_LH4_2" + ], + [ + "CMT_FIFO_WW2END0_7", + "CMT_TOP_WW2END0_4" + ], + [ + "CMT_FIFO_NW4A1_11", + "CMT_TOP_NW4A1_8" + ], + [ + "CMT_FIFO_SW2A1_9", + "CMT_TOP_SW2A1_6" + ], + [ + "CMT_FIFO_SW4A3_9", + "CMT_TOP_SW4A3_6" + ], + [ + "CMT_FIFO_NE2A2_8", + "CMT_TOP_NE2A2_5" + ], + [ + "CMT_FIFO_SE2A2_5", + "CMT_TOP_SE2A2_2" + ], + [ + "CMT_FIFO_LH3_5", + "CMT_TOP_LH3_2" + ], + [ + "CMT_FIFO_NW2A0_3", + "CMT_TOP_NW2A0_0" + ], + [ + "CMT_FIFO_SE2A0_4", + "CMT_TOP_SE2A0_1" + ], + [ + "CMT_FIFO_WW4B2_11", + "CMT_TOP_WW4B2_8" + ], + [ + "CMT_FIFO_NW2A1_9", + "CMT_TOP_NW2A1_6" + ], + [ + "CMT_FIFO_L_FAN7_8", + "CMT_TOP_FAN7_5" + ], + [ + "CMT_FIFO_NW4END3_10", + "CMT_TOP_NW4END3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_7" + ], + [ + "CMT_FIFO_NW2A3_10", + "CMT_TOP_NW2A3_7" + ], + [ + "CMT_FIFO_L_IMUX28_3", + "CMT_TOP_IMUX28_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_7", + "CMT_TOP_LOGIC_OUTS_L_B12_4" + ], + [ + "CMT_FIFO_NW4A3_10", + "CMT_TOP_NW4A3_7" + ], + [ + "CMT_FIFO_L_IMUX9_5", + "CMT_TOP_IMUX9_2" + ], + [ + "CMT_FIFO_WR1END2_3", + "CMT_TOP_WR1END2_0" + ], + [ + "CMT_FIFO_L_IMUX35_3", + "CMT_TOP_IMUX35_0" + ], + [ + "CMT_FIFO_WW2END2_10", + "CMT_TOP_WW2END2_7" + ], + [ + "CMT_FIFO_ER1BEG0_9", + "CMT_TOP_ER1BEG0_6" + ], + [ + "CMT_FIFO_L_PHASER_WRENABLE", + "CMT_PHASER_IN_B_WREN_TOFIFO" + ], + [ + "CMT_FIFO_L_IMUX10_5", + "CMT_TOP_IMUX10_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_5", + "CMT_TOP_LOGIC_OUTS_L_B15_2" + ], + [ + "CMT_FIFO_EE4BEG1_8", + "CMT_TOP_EE4BEG1_5" + ], + [ + "CMT_FIFO_L_IMUX17_3", + "CMT_TOP_IMUX17_0" + ], + [ + "CMT_FIFO_WW2END3_9", + "CMT_TOP_WW2END3_6" + ], + [ + "CMT_FIFO_LH9_4", + "CMT_TOP_LH9_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_4", + "CMT_TOP_LOGIC_OUTS_L_B21_1" + ], + [ + "CMT_FIFO_L_IMUX2_3", + "CMT_TOP_IMUX2_0" + ], + [ + "CMT_FIFO_SE4C0_4", + "CMT_TOP_SE4C0_1" + ], + [ + "CMT_FIFO_L_IMUX44_10", + "CMT_TOP_IMUX44_7" + ], + [ + "CMT_FIFO_WW2END0_11", + "CMT_TOP_WW2END0_8" + ], + [ + "CMT_FIFO_L_IMUX22_7", + "CMT_TOP_IMUX22_4" + ], + [ + "CMT_FIFO_L_IMUX20_5", + "CMT_TOP_IMUX20_2" + ], + [ + "CMT_FIFO_L_IMUX15_10", + "CMT_TOP_IMUX15_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_4", + "CMT_TOP_LOGIC_OUTS_L_B23_1" + ], + [ + "CMT_FIFO_L_IMUX0_10", + "CMT_TOP_IMUX0_7" + ], + [ + "CMT_FIFO_L_IMUX35_9", + "CMT_TOP_IMUX35_6" + ], + [ + "CMT_FIFO_L_CTRL1_7", + "CMT_TOP_CTRL1_4" + ], + [ + "CMT_FIFO_L_BYP4_9", + "CMT_TOP_BYP4_6" + ], + [ + "CMT_FIFO_L_BYP2_3", + "CMT_TOP_BYP2_0" + ], + [ + "CMT_FIFO_L_FAN7_4", + "CMT_TOP_FAN7_1" + ], + [ + "CMT_FIFO_WW4A0_11", + "CMT_TOP_WW4A0_8" + ], + [ + "CMT_FIFO_L_IMUX19_9", + "CMT_TOP_IMUX19_6" + ], + [ + "CMT_FIFO_L_IMUX37_3", + "CMT_TOP_IMUX37_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "CMT_TOP_OCLK_3" + ], + [ + "CMT_FIFO_L_IMUX1_3", + "CMT_TOP_IMUX1_0" + ], + [ + "CMT_FIFO_L_BYP6_4", + "CMT_TOP_BYP6_1" + ], + [ + "CMT_FIFO_L_IMUX34_3", + "CMT_TOP_IMUX34_0" + ], + [ + "CMT_FIFO_NW4A1_8", + "CMT_TOP_NW4A1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_8", + "CMT_TOP_LOGIC_OUTS_L_B9_5" + ], + [ + "CMT_FIFO_NE2A3_9", + "CMT_TOP_NE2A3_6" + ], + [ + "CMT_FIFO_EE4BEG1_11", + "CMT_TOP_EE4BEG1_8" + ], + [ + "CMT_FIFO_NW4END0_8", + "CMT_TOP_NW4END0_5" + ], + [ + "CMT_FIFO_SW2A0_5", + "CMT_TOP_SW2A0_2" + ], + [ + "CMT_FIFO_L_BYP0_5", + "CMT_TOP_BYP0_2" + ], + [ + "CMT_FIFO_WW4B2_10", + "CMT_TOP_WW4B2_7" + ], + [ + "CMT_FIFO_NE2A0_10", + "CMT_TOP_NE2A0_7" + ], + [ + "CMT_FIFO_L_IMUX23_10", + "CMT_TOP_IMUX23_7" + ], + [ + "CMT_FIFO_L_IMUX32_5", + "CMT_TOP_IMUX32_2" + ], + [ + "CMT_FIFO_L_IMUX13_3", + "CMT_TOP_IMUX13_0" + ], + [ + "CMT_FIFO_L_IMUX4_3", + "CMT_TOP_IMUX4_0" + ], + [ + "CMT_FIFO_L_IMUX41_4", + "CMT_TOP_IMUX41_1" + ], + [ + "CMT_FIFO_L_IMUX39_11", + "CMT_TOP_IMUX39_8" + ], + [ + "CMT_FIFO_NW4END3_8", + "CMT_TOP_NW4END3_5" + ], + [ + "CMT_FIFO_LH4_6", + "CMT_TOP_LH4_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_5", + "CMT_TOP_LOGIC_OUTS_L_B1_2" + ], + [ + "CMT_FIFO_WW2END1_3", + "CMT_TOP_WW2END1_0" + ], + [ + "CMT_FIFO_L_IMUX22_10", + "CMT_TOP_IMUX22_7" + ], + [ + "CMT_FIFO_NW2A3_9", + "CMT_TOP_NW2A3_6" + ], + [ + "CMT_FIFO_L_IMUX30_8", + "CMT_TOP_IMUX30_5" + ], + [ + "CMT_FIFO_EE4B0_8", + "CMT_TOP_EE4B0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_4", + "CMT_TOP_LOGIC_OUTS_L_B0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_0" + ], + [ + "CMT_FIFO_L_IMUX27_3", + "CMT_TOP_IMUX27_0" + ], + [ + "CMT_FIFO_L_IMUX16_4", + "CMT_TOP_IMUX16_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_8", + "CMT_TOP_LOGIC_OUTS_L_B11_5" + ], + [ + "CMT_FIFO_NE4BEG0_7", + "CMT_TOP_NE4BEG0_4" + ], + [ + "CMT_FIFO_L_IMUX37_7", + "CMT_TOP_IMUX37_4" + ], + [ + "CMT_FIFO_L_IMUX20_7", + "CMT_TOP_IMUX20_4" + ], + [ + "CMT_FIFO_WW4A0_4", + "CMT_TOP_WW4A0_1" + ], + [ + "CMT_FIFO_L_IMUX33_11", + "CMT_TOP_IMUX33_8" + ], + [ + "CMT_FIFO_NE4C2_7", + "CMT_TOP_NE4C2_4" + ], + [ + "CMT_FIFO_NE4C0_10", + "CMT_TOP_NE4C0_7" + ], + [ + "CMT_FIFO_LH12_7", + "CMT_TOP_LH12_4" + ], + [ + "CMT_FIFO_SW4END3_7", + "CMT_TOP_SW4END3_4" + ], + [ + "CMT_FIFO_SW4A3_10", + "CMT_TOP_SW4A3_7" + ], + [ + "CMT_FIFO_EE4A0_11", + "CMT_TOP_EE4A0_8" + ], + [ + "CMT_FIFO_L_IMUX5_5", + "CMT_TOP_IMUX5_2" + ], + [ + "CMT_FIFO_L_IMUX25_10", + "CMT_TOP_IMUX25_7" + ], + [ + "CMT_FIFO_EE2BEG3_5", + "CMT_TOP_EE2BEG3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_7", + "CMT_TOP_LOGIC_OUTS_L_B11_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_10", + "CMT_TOP_LOGIC_OUTS_L_B3_7" + ], + [ + "CMT_FIFO_EE2A2_7", + "CMT_TOP_EE2A2_4" + ], + [ + "CMT_FIFO_WL1END3_4", + "CMT_TOP_WL1END3_1" + ], + [ + "CMT_FIFO_WW4C0_3", + "CMT_TOP_WW4C0_0" + ], + [ + "CMT_FIFO_EE4BEG2_6", + "CMT_TOP_EE4BEG2_3" + ], + [ + "CMT_FIFO_L_FAN1_6", + "CMT_TOP_FAN1_3" + ], + [ + "CMT_FIFO_WW4C1_8", + "CMT_TOP_WW4C1_5" + ], + [ + "CMT_FIFO_L_FAN2_6", + "CMT_TOP_FAN2_3" + ], + [ + "CMT_FIFO_SW4END1_11", + "CMT_TOP_SW4END1_8" + ], + [ + "CMT_FIFO_WW2A0_6", + "CMT_TOP_WW2A0_3" + ], + [ + "CMT_FIFO_WW2A0_9", + "CMT_TOP_WW2A0_6" + ], + [ + "CMT_FIFO_NW2A0_9", + "CMT_TOP_NW2A0_6" + ], + [ + "CMT_FIFO_SW4END3_10", + "CMT_TOP_SW4END3_7" + ], + [ + "CMT_FIFO_WW4END3_3", + "CMT_TOP_WW4END3_0" + ], + [ + "CMT_FIFO_L_CLK1_9", + "CMT_TOP_CLK1_6" + ], + [ + "CMT_FIFO_L_IMUX42_7", + "CMT_TOP_IMUX42_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_9", + "CMT_TOP_LOGIC_OUTS_L_B9_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_11", + "CMT_TOP_LOGIC_OUTS_L_B10_8" + ], + [ + "CMT_FIFO_SW4A0_8", + "CMT_TOP_SW4A0_5" + ], + [ + "CMT_FIFO_WW2END1_6", + "CMT_TOP_WW2END1_3" + ], + [ + "CMT_FIFO_L_IMUX2_11", + "CMT_TOP_IMUX2_8" + ], + [ + "CMT_FIFO_L_IMUX2_10", + "CMT_TOP_IMUX2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_10", + "CMT_TOP_LOGIC_OUTS_L_B9_7" + ], + [ + "CMT_FIFO_WW4A3_11", + "CMT_TOP_WW4A3_8" + ], + [ + "CMT_FIFO_L_IMUX4_5", + "CMT_TOP_IMUX4_2" + ], + [ + "CMT_FIFO_EL1BEG2_3", + "CMT_TOP_EL1BEG2_0" + ], + [ + "CMT_FIFO_LH10_4", + "CMT_TOP_LH10_1" + ], + [ + "CMT_FIFO_L_IMUX21_8", + "CMT_TOP_IMUX21_5" + ], + [ + "CMT_FIFO_L_IMUX7_3", + "CMT_TOP_IMUX7_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_4", + "CMT_TOP_LOGIC_OUTS_L_B4_1" + ], + [ + "CMT_FIFO_L_FAN5_10", + "CMT_TOP_FAN5_7" + ], + [ + "CMT_FIFO_SW4END2_8", + "CMT_TOP_SW4END2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_8", + "CMT_TOP_LOGIC_OUTS_L_B18_5" + ], + [ + "CMT_FIFO_EE2BEG1_3", + "CMT_TOP_EE2BEG1_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_6", + "CMT_TOP_LOGIC_OUTS_L_B10_3" + ], + [ + "CMT_FIFO_L_PHASER_RDCLK", + "CMT_PHASER_OUT_B_RDCLK_TOFIFO" + ], + [ + "CMT_FIFO_NE4C1_6", + "CMT_TOP_NE4C1_3" + ], + [ + "CMT_FIFO_L_IMUX0_9", + "CMT_TOP_IMUX0_6" + ], + [ + "CMT_FIFO_L_IMUX31_4", + "CMT_TOP_IMUX31_1" + ], + [ + "CMT_FIFO_WW4C0_11", + "CMT_TOP_WW4C0_8" + ], + [ + "CMT_FIFO_LH2_8", + "CMT_TOP_LH2_5" + ], + [ + "CMT_FIFO_WR1END3_6", + "CMT_TOP_WR1END3_3" + ], + [ + "CMT_FIFO_MONITOR_P_6", + "CMT_TOP_MONITOR_P_3" + ], + [ + "CMT_FIFO_EE4A2_10", + "CMT_TOP_EE4A2_7" + ], + [ + "CMT_FIFO_L_IMUX2_8", + "CMT_TOP_IMUX2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_11", + "CMT_TOP_LOGIC_OUTS_L_B0_8" + ], + [ + "CMT_FIFO_L_IMUX29_6", + "CMT_TOP_IMUX29_3" + ], + [ + "CMT_FIFO_NW4A2_3", + "CMT_TOP_NW4A2_0" + ], + [ + "CMT_FIFO_L_CTRL1_4", + "CMT_TOP_CTRL1_1" + ], + [ + "CMT_FIFO_NE2A1_3", + "CMT_TOP_NE2A1_0" + ], + [ + "CMT_FIFO_EE2BEG1_7", + "CMT_TOP_EE2BEG1_4" + ], + [ + "CMT_FIFO_SE2A1_5", + "CMT_TOP_SE2A1_2" + ], + [ + "CMT_FIFO_EE4C3_8", + "CMT_TOP_EE4C3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_3", + "CMT_TOP_LOGIC_OUTS_L_B2_0" + ], + [ + "CMT_FIFO_L_IMUX47_10", + "CMT_TOP_IMUX47_7" + ], + [ + "CMT_FIFO_L_IMUX16_8", + "CMT_TOP_IMUX16_5" + ], + [ + "CMT_FIFO_WW2END1_11", + "CMT_TOP_WW2END1_8" + ], + [ + "CMT_FIFO_LH3_10", + "CMT_TOP_LH3_7" + ], + [ + "CMT_FIFO_WL1END0_3", + "CMT_TOP_WL1END0_0" + ], + [ + "CMT_FIFO_L_IMUX37_6", + "CMT_TOP_IMUX37_3" + ], + [ + "CMT_FIFO_LH2_11", + "CMT_TOP_LH2_8" + ], + [ + "CMT_FIFO_L_IMUX17_11", + "CMT_TOP_IMUX17_8" + ], + [ + "CMT_FIFO_NW4A0_7", + "CMT_TOP_NW4A0_4" + ], + [ + "CMT_FIFO_SE4BEG2_5", + "CMT_TOP_SE4BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX18_5", + "CMT_TOP_IMUX18_2" + ], + [ + "CMT_FIFO_L_BYP1_5", + "CMT_TOP_BYP1_2" + ], + [ + "CMT_FIFO_WL1END1_6", + "CMT_TOP_WL1END1_3" + ], + [ + "CMT_FIFO_SE2A0_5", + "CMT_TOP_SE2A0_2" + ], + [ + "CMT_FIFO_LH4_7", + "CMT_TOP_LH4_4" + ], + [ + "CMT_FIFO_WR1END2_11", + "CMT_TOP_WR1END2_8" + ], + [ + "CMT_FIFO_LH12_11", + "CMT_TOP_LH12_8" + ], + [ + "CMT_FIFO_WW4END1_5", + "CMT_TOP_WW4END1_2" + ], + [ + "CMT_FIFO_L_FAN4_5", + "CMT_TOP_FAN4_2" + ], + [ + "CMT_FIFO_EE2A3_4", + "CMT_TOP_EE2A3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_11", + "CMT_TOP_LOGIC_OUTS_L_B18_8" + ], + [ + "CMT_FIFO_WL1END1_11", + "CMT_TOP_WL1END1_8" + ], + [ + "CMT_FIFO_L_IMUX44_3", + "CMT_TOP_IMUX44_0" + ], + [ + "CMT_FIFO_LH10_5", + "CMT_TOP_LH10_2" + ], + [ + "CMT_FIFO_L_IMUX17_7", + "CMT_TOP_IMUX17_4" + ], + [ + "CMT_FIFO_L_IMUX5_4", + "CMT_TOP_IMUX5_1" + ], + [ + "CMT_FIFO_LH3_3", + "CMT_TOP_LH3_0" + ], + [ + "CMT_FIFO_L_FAN4_8", + "CMT_TOP_FAN4_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "CMT_TOP_OCLK_7" + ], + [ + "CMT_FIFO_SE4C2_8", + "CMT_TOP_SE4C2_5" + ], + [ + "CMT_FIFO_EE2A1_5", + "CMT_TOP_EE2A1_2" + ], + [ + "CMT_FIFO_SE2A2_11", + "CMT_TOP_SE2A2_8" + ], + [ + "CMT_FIFO_SW2A3_10", + "CMT_TOP_SW2A3_7" + ], + [ + "CMT_FIFO_WW4END0_8", + "CMT_TOP_WW4END0_5" + ], + [ + "CMT_FIFO_SW2A0_9", + "CMT_TOP_SW2A0_6" + ], + [ + "CMT_FIFO_L_IMUX28_11", + "CMT_TOP_IMUX28_8" + ], + [ + "CMT_FIFO_NE2A3_11", + "CMT_TOP_NE2A3_8" + ], + [ + "CMT_FIFO_L_IMUX40_5", + "CMT_TOP_IMUX40_2" + ], + [ + "CMT_FIFO_L_IMUX3_6", + "CMT_TOP_IMUX3_3" + ], + [ + "CMT_FIFO_L_BYP5_7", + "CMT_TOP_BYP5_4" + ], + [ + "CMT_FIFO_EE4C3_6", + "CMT_TOP_EE4C3_3" + ], + [ + "CMT_FIFO_EE4BEG0_9", + "CMT_TOP_EE4BEG0_6" + ], + [ + "CMT_FIFO_L_IMUX44_8", + "CMT_TOP_IMUX44_5" + ], + [ + "CMT_FIFO_L_BYP6_5", + "CMT_TOP_BYP6_2" + ], + [ + "CMT_FIFO_WW4C1_7", + "CMT_TOP_WW4C1_4" + ], + [ + "CMT_FIFO_NE4C2_4", + "CMT_TOP_NE4C2_1" + ], + [ + "CMT_FIFO_WW4END2_5", + "CMT_TOP_WW4END2_2" + ], + [ + "CMT_FIFO_L_IMUX24_6", + "CMT_TOP_IMUX24_3" + ], + [ + "CMT_FIFO_L_IMUX36_5", + "CMT_TOP_IMUX36_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_4", + "CMT_TOP_LOGIC_OUTS_L_B16_1" + ], + [ + "CMT_FIFO_L_IMUX29_9", + "CMT_TOP_IMUX29_6" + ], + [ + "CMT_FIFO_EL1BEG2_7", + "CMT_TOP_EL1BEG2_4" + ], + [ + "CMT_FIFO_EE2A0_10", + "CMT_TOP_EE2A0_7" + ], + [ + "CMT_FIFO_WW4C1_11", + "CMT_TOP_WW4C1_8" + ], + [ + "CMT_FIFO_L_IMUX7_10", + "CMT_TOP_IMUX7_7" + ], + [ + "CMT_FIFO_SW4END1_6", + "CMT_TOP_SW4END1_3" + ], + [ + "CMT_FIFO_SW4END3_4", + "CMT_TOP_SW4END3_1" + ], + [ + "CMT_FIFO_NW2A0_4", + "CMT_TOP_NW2A0_1" + ], + [ + "CMT_FIFO_WW4END0_10", + "CMT_TOP_WW4END0_7" + ], + [ + "CMT_FIFO_SE4BEG2_7", + "CMT_TOP_SE4BEG2_4" + ], + [ + "CMT_FIFO_EE4B2_8", + "CMT_TOP_EE4B2_5" + ], + [ + "CMT_FIFO_SE2A0_7", + "CMT_TOP_SE2A0_4" + ], + [ + "CMT_FIFO_SW4END0_4", + "CMT_TOP_SW4END0_1" + ], + [ + "CMT_FIFO_NW4END3_7", + "CMT_TOP_NW4END3_4" + ], + [ + "CMT_FIFO_WW4B3_10", + "CMT_TOP_WW4B3_7" + ], + [ + "CMT_FIFO_WW4END1_10", + "CMT_TOP_WW4END1_7" + ], + [ + "CMT_FIFO_WW4END0_5", + "CMT_TOP_WW4END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_3", + "CMT_TOP_LOGIC_OUTS_L_B4_0" + ], + [ + "CMT_FIFO_L_IMUX40_9", + "CMT_TOP_IMUX40_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_3", + "CMT_TOP_LOGIC_OUTS_L_B7_0" + ], + [ + "CMT_FIFO_EE2A0_5", + "CMT_TOP_EE2A0_2" + ], + [ + "CMT_FIFO_EL1BEG2_6", + "CMT_TOP_EL1BEG2_3" + ], + [ + "CMT_FIFO_L_IMUX13_7", + "CMT_TOP_IMUX13_4" + ], + [ + "CMT_FIFO_WW2A2_8", + "CMT_TOP_WW2A2_5" + ], + [ + "CMT_FIFO_SE2A0_9", + "CMT_TOP_SE2A0_6" + ], + [ + "CMT_FIFO_NW4A3_3", + "CMT_TOP_NW4A3_0" + ], + [ + "CMT_FIFO_L_BYP3_9", + "CMT_TOP_BYP3_6" + ], + [ + "CMT_FIFO_L_IMUX33_6", + "CMT_TOP_IMUX33_3" + ], + [ + "CMT_FIFO_EE4A2_8", + "CMT_TOP_EE4A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_8", + "CMT_TOP_LOGIC_OUTS_L_B23_5" + ], + [ + "CMT_FIFO_WW4C3_9", + "CMT_TOP_WW4C3_6" + ], + [ + "CMT_FIFO_L_IMUX22_4", + "CMT_TOP_IMUX22_1" + ], + [ + "CMT_FIFO_WW2END2_11", + "CMT_TOP_WW2END2_8" + ], + [ + "CMT_FIFO_SE2A2_8", + "CMT_TOP_SE2A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_9", + "CMT_TOP_LOGIC_OUTS_L_B20_6" + ], + [ + "CMT_FIFO_L_IMUX46_10", + "CMT_TOP_IMUX46_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_11", + "CMT_TOP_LOGIC_OUTS_L_B8_8" + ], + [ + "CMT_FIFO_WR1END0_3", + "CMT_TOP_WR1END0_0" + ], + [ + "CMT_FIFO_WW2A2_5", + "CMT_TOP_WW2A2_2" + ], + [ + "CMT_FIFO_NE2A3_5", + "CMT_TOP_NE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX26_5", + "CMT_TOP_IMUX26_2" + ], + [ + "CMT_FIFO_L_BYP7_9", + "CMT_TOP_BYP7_6" + ], + [ + "CMT_FIFO_SE2A2_9", + "CMT_TOP_SE2A2_6" + ], + [ + "CMT_FIFO_EE4BEG3_11", + "CMT_TOP_EE4BEG3_8" + ], + [ + "CMT_FIFO_LH7_8", + "CMT_TOP_LH7_5" + ], + [ + "CMT_FIFO_WW4A1_10", + "CMT_TOP_WW4A1_7" + ], + [ + "CMT_FIFO_L_IMUX38_7", + "CMT_TOP_IMUX38_4" + ], + [ + "CMT_FIFO_WW2A2_9", + "CMT_TOP_WW2A2_6" + ], + [ + "CMT_FIFO_EE4C3_7", + "CMT_TOP_EE4C3_4" + ], + [ + "CMT_FIFO_EE2BEG0_9", + "CMT_TOP_EE2BEG0_6" + ], + [ + "CMT_FIFO_L_IMUX43_8", + "CMT_TOP_IMUX43_5" + ], + [ + "CMT_FIFO_L_IMUX13_11", + "CMT_TOP_IMUX13_8" + ], + [ + "FIFO_DQS_IOTOPHASER_1", + "CMT_PHASER_DOWN_DQS_TO_PHASER_B" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_10", + "CMT_TOP_LOGIC_OUTS_L_B19_7" + ], + [ + "CMT_FIFO_LH8_11", + "CMT_TOP_LH8_8" + ], + [ + "CMT_FIFO_L_IMUX14_10", + "CMT_TOP_IMUX14_7" + ], + [ + "CMT_FIFO_EE2BEG1_4", + "CMT_TOP_EE2BEG1_1" + ], + [ + "CMT_FIFO_EL1BEG1_3", + "CMT_TOP_EL1BEG1_0" + ], + [ + "CMT_FIFO_L_IMUX2_6", + "CMT_TOP_IMUX2_3" + ], + [ + "CMT_FIFO_LH9_7", + "CMT_TOP_LH9_4" + ], + [ + "CMT_FIFO_L_IMUX35_5", + "CMT_TOP_IMUX35_2" + ], + [ + "CMT_FIFO_L_BYP2_4", + "CMT_TOP_BYP2_1" + ], + [ + "CMT_FIFO_L_CLK0_4", + "CMT_TOP_CLK0_1" + ], + [ + "CMT_FIFO_NE4C1_3", + "CMT_TOP_NE4C1_0" + ], + [ + "CMT_FIFO_L_IMUX2_5", + "CMT_TOP_IMUX2_2" + ], + [ + "CMT_FIFO_SW4END1_8", + "CMT_TOP_SW4END1_5" + ], + [ + "CMT_FIFO_WW2END2_4", + "CMT_TOP_WW2END2_1" + ], + [ + "CMT_FIFO_L_IMUX24_7", + "CMT_TOP_IMUX24_4" + ], + [ + "CMT_FIFO_SW2A0_7", + "CMT_TOP_SW2A0_4" + ], + [ + "CMT_FIFO_EE4BEG1_6", + "CMT_TOP_EE4BEG1_3" + ], + [ + "CMT_FIFO_WW4C3_5", + "CMT_TOP_WW4C3_2" + ], + [ + "CMT_FIFO_L_IMUX26_3", + "CMT_TOP_IMUX26_0" + ], + [ + "CMT_FIFO_SE2A2_3", + "CMT_TOP_SE2A2_0" + ], + [ + "CMT_FIFO_NE2A0_3", + "CMT_TOP_NE2A0_0" + ], + [ + "CMT_FIFO_SE2A1_9", + "CMT_TOP_SE2A1_6" + ], + [ + "CMT_FIFO_EE4C2_10", + "CMT_TOP_EE4C2_7" + ], + [ + "CMT_FIFO_LH12_10", + "CMT_TOP_LH12_7" + ], + [ + "CMT_FIFO_L_IMUX25_5", + "CMT_TOP_IMUX25_2" + ], + [ + "CMT_FIFO_L_IMUX18_7", + "CMT_TOP_IMUX18_4" + ], + [ + "CMT_FIFO_LH9_10", + "CMT_TOP_LH9_7" + ], + [ + "CMT_FIFO_WW4B3_11", + "CMT_TOP_WW4B3_8" + ], + [ + "CMT_FIFO_SE4BEG0_11", + "CMT_TOP_SE4BEG0_8" + ], + [ + "CMT_FIFO_L_BYP6_7", + "CMT_TOP_BYP6_4" + ], + [ + "CMT_FIFO_EE4B2_10", + "CMT_TOP_EE4B2_7" + ], + [ + "CMT_FIFO_L_IMUX9_9", + "CMT_TOP_IMUX9_6" + ], + [ + "CMT_FIFO_L_FAN7_7", + "CMT_TOP_FAN7_4" + ], + [ + "CMT_FIFO_L_IMUX45_4", + "CMT_TOP_IMUX45_1" + ], + [ + "CMT_FIFO_L_IMUX12_10", + "CMT_TOP_IMUX12_7" + ], + [ + "CMT_FIFO_WW4B2_8", + "CMT_TOP_WW4B2_5" + ], + [ + "CMT_FIFO_L_BYP4_8", + "CMT_TOP_BYP4_5" + ], + [ + "CMT_FIFO_EE4B2_5", + "CMT_TOP_EE4B2_2" + ], + [ + "CMT_FIFO_WW4A1_11", + "CMT_TOP_WW4A1_8" + ], + [ + "CMT_FIFO_NE2A2_6", + "CMT_TOP_NE2A2_3" + ], + [ + "CMT_FIFO_L_IMUX17_4", + "CMT_TOP_IMUX17_1" + ], + [ + "CMT_FIFO_L_IMUX42_9", + "CMT_TOP_IMUX42_6" + ], + [ + "CMT_FIFO_WW4C0_5", + "CMT_TOP_WW4C0_2" + ], + [ + "CMT_FIFO_SW4A3_6", + "CMT_TOP_SW4A3_3" + ], + [ + "CMT_FIFO_L_IMUX46_4", + "CMT_TOP_IMUX46_1" + ], + [ + "CMT_FIFO_SE4C2_4", + "CMT_TOP_SE4C2_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "CMT_TOP_ICLKDIV_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_9", + "CMT_TOP_LOGIC_OUTS_L_B18_6" + ], + [ + "CMT_FIFO_L_IMUX8_10", + "CMT_TOP_IMUX8_7" + ], + [ + "CMT_FIFO_WW2A1_6", + "CMT_TOP_WW2A1_3" + ], + [ + "CMT_FIFO_EE4C0_10", + "CMT_TOP_EE4C0_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_6", + "CMT_TOP_LOGIC_OUTS_L_B20_3" + ], + [ + "CMT_FIFO_EE4C0_6", + "CMT_TOP_EE4C0_3" + ], + [ + "CMT_FIFO_L_IMUX3_8", + "CMT_TOP_IMUX3_5" + ], + [ + "CMT_FIFO_NE4BEG1_11", + "CMT_TOP_NE4BEG1_8" + ], + [ + "CMT_FIFO_SE4BEG1_4", + "CMT_TOP_SE4BEG1_1" + ], + [ + "CMT_FIFO_L_CLK1_7", + "CMT_TOP_CLK1_4" + ], + [ + "CMT_FIFO_L_IMUX44_4", + "CMT_TOP_IMUX44_1" + ], + [ + "CMT_FIFO_NW4A3_11", + "CMT_TOP_NW4A3_8" + ], + [ + "CMT_FIFO_WW4A1_7", + "CMT_TOP_WW4A1_4" + ], + [ + "CMT_FIFO_WW4A3_3", + "CMT_TOP_WW4A3_0" + ], + [ + "CMT_FIFO_L_IMUX44_9", + "CMT_TOP_IMUX44_6" + ], + [ + "CMT_FIFO_L_IMUX6_6", + "CMT_TOP_IMUX6_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_10", + "CMT_TOP_LOGIC_OUTS_L_B13_7" + ], + [ + "CMT_FIFO_L_FAN2_8", + "CMT_TOP_FAN2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_6", + "CMT_TOP_LOGIC_OUTS_L_B8_3" + ], + [ + "CMT_FIFO_L_CLK0_5", + "CMT_TOP_CLK0_2" + ], + [ + "CMT_FIFO_EE2A2_3", + "CMT_TOP_EE2A2_0" + ], + [ + "CMT_FIFO_ER1BEG3_8", + "CMT_TOP_ER1BEG3_5" + ], + [ + "CMT_FIFO_L_IMUX33_10", + "CMT_TOP_IMUX33_7" + ], + [ + "CMT_FIFO_L_BYP5_5", + "CMT_TOP_BYP5_2" + ], + [ + "CMT_FIFO_EL1BEG3_8", + "CMT_TOP_EL1BEG3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_5", + "CMT_TOP_LOGIC_OUTS_L_B10_2" + ], + [ + "CMT_FIFO_EE2BEG3_4", + "CMT_TOP_EE2BEG3_1" + ], + [ + "CMT_FIFO_EE2BEG3_3", + "CMT_TOP_EE2BEG3_0" + ], + [ + "CMT_FIFO_L_BYP2_5", + "CMT_TOP_BYP2_2" + ], + [ + "CMT_FIFO_NE2A2_11", + "CMT_TOP_NE2A2_8" + ], + [ + "CMT_FIFO_EE4A3_9", + "CMT_TOP_EE4A3_6" + ], + [ + "CMT_FIFO_NW4END0_3", + "CMT_TOP_NW4END0_0" + ], + [ + "CMT_FIFO_L_IMUX28_9", + "CMT_TOP_IMUX28_6" + ], + [ + "CMT_FIFO_L_IMUX36_7", + "CMT_TOP_IMUX36_4" + ], + [ + "CMT_FIFO_SW4END3_6", + "CMT_TOP_SW4END3_3" + ], + [ + "CMT_FIFO_NE2A2_5", + "CMT_TOP_NE2A2_2" + ], + [ + "CMT_FIFO_EE4B3_3", + "CMT_TOP_EE4B3_0" + ], + [ + "CMT_FIFO_L_IMUX24_10", + "CMT_TOP_IMUX24_7" + ], + [ + "CMT_FIFO_L_IMUX41_8", + "CMT_TOP_IMUX41_5" + ], + [ + "CMT_FIFO_WL1END1_4", + "CMT_TOP_WL1END1_1" + ], + [ + "CMT_FIFO_NW2A2_5", + "CMT_TOP_NW2A2_2" + ], + [ + "CMT_FIFO_SE4BEG1_10", + "CMT_TOP_SE4BEG1_7" + ], + [ + "CMT_FIFO_EE2A2_9", + "CMT_TOP_EE2A2_6" + ], + [ + "CMT_FIFO_NE4BEG3_3", + "CMT_TOP_NE4BEG3_0" + ], + [ + "CMT_FIFO_L_CLK1_3", + "CMT_TOP_CLK1_0" + ], + [ + "CMT_FIFO_WW4C2_9", + "CMT_TOP_WW4C2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_11", + "CMT_TOP_LOGIC_OUTS_L_B9_8" + ], + [ + "CMT_FIFO_ER1BEG0_10", + "CMT_TOP_ER1BEG0_7" + ], + [ + "CMT_FIFO_LH3_7", + "CMT_TOP_LH3_4" + ], + [ + "CMT_FIFO_EE4B0_9", + "CMT_TOP_EE4B0_6" + ], + [ + "CMT_FIFO_NE4BEG3_8", + "CMT_TOP_NE4BEG3_5" + ], + [ + "CMT_FIFO_EE4A2_4", + "CMT_TOP_EE4A2_1" + ], + [ + "CMT_FIFO_EE2A0_11", + "CMT_TOP_EE2A0_8" + ], + [ + "CMT_FIFO_L_BYP5_9", + "CMT_TOP_BYP5_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_8", + "CMT_TOP_LOGIC_OUTS_L_B5_5" + ], + [ + "CMT_FIFO_L_CTRL1_5", + "CMT_TOP_CTRL1_2" + ], + [ + "CMT_FIFO_LH2_10", + "CMT_TOP_LH2_7" + ], + [ + "CMT_FIFO_L_IMUX7_7", + "CMT_TOP_IMUX7_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_2" + ], + [ + "CMT_FIFO_L_IMUX45_5", + "CMT_TOP_IMUX45_2" + ], + [ + "CMT_FIFO_L_IMUX3_11", + "CMT_TOP_IMUX3_8" + ], + [ + "CMT_FIFO_WW4C1_6", + "CMT_TOP_WW4C1_3" + ], + [ + "CMT_FIFO_WW2A1_7", + "CMT_TOP_WW2A1_4" + ], + [ + "CMT_FIFO_NE2A1_4", + "CMT_TOP_NE2A1_1" + ], + [ + "CMT_FIFO_L_IMUX19_3", + "CMT_TOP_IMUX19_0" + ], + [ + "CMT_FIFO_EE2BEG1_11", + "CMT_TOP_EE2BEG1_8" + ], + [ + "CMT_FIFO_L_IMUX41_10", + "CMT_TOP_IMUX41_7" + ], + [ + "CMT_FIFO_WW4END3_5", + "CMT_TOP_WW4END3_2" + ], + [ + "CMT_FIFO_L_IMUX35_7", + "CMT_TOP_IMUX35_4" + ], + [ + "CMT_FIFO_L_IMUX10_6", + "CMT_TOP_IMUX10_3" + ], + [ + "CMT_FIFO_L_IMUX16_7", + "CMT_TOP_IMUX16_4" + ], + [ + "CMT_FIFO_LH6_5", + "CMT_TOP_LH6_2" + ], + [ + "CMT_FIFO_L_IMUX24_8", + "CMT_TOP_IMUX24_5" + ], + [ + "CMT_FIFO_L_IMUX23_4", + "CMT_TOP_IMUX23_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_6", + "CMT_TOP_LOGIC_OUTS_L_B3_3" + ], + [ + "CMT_FIFO_L_CLK1_4", + "CMT_TOP_CLK1_1" + ], + [ + "CMT_FIFO_WW4A0_10", + "CMT_TOP_WW4A0_7" + ], + [ + "CMT_FIFO_SW4END0_9", + "CMT_TOP_SW4END0_6" + ], + [ + "CMT_FIFO_EE4B1_11", + "CMT_TOP_EE4B1_8" + ], + [ + "CMT_FIFO_EL1BEG0_9", + "CMT_TOP_EL1BEG0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_9", + "CMT_TOP_LOGIC_OUTS_L_B3_6" + ], + [ + "CMT_FIFO_L_CTRL1_3", + "CMT_TOP_CTRL1_0" + ], + [ + "CMT_FIFO_ER1BEG3_4", + "CMT_TOP_ER1BEG3_1" + ], + [ + "CMT_FIFO_WW4END2_3", + "CMT_TOP_WW4END2_0" + ], + [ + "CMT_FIFO_WW4A1_3", + "CMT_TOP_WW4A1_0" + ], + [ + "CMT_FIFO_WW2END0_10", + "CMT_TOP_WW2END0_7" + ], + [ + "CMT_FIFO_WW2A1_5", + "CMT_TOP_WW2A1_2" + ], + [ + "CMT_FIFO_NW2A3_11", + "CMT_TOP_NW2A3_8" + ], + [ + "CMT_FIFO_EE4C3_10", + "CMT_TOP_EE4C3_7" + ], + [ + "CMT_FIFO_WW2END3_6", + "CMT_TOP_WW2END3_3" + ], + [ + "CMT_FIFO_WR1END0_5", + "CMT_TOP_WR1END0_2" + ], + [ + "CMT_FIFO_L_IMUX21_11", + "CMT_TOP_IMUX21_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_7", + "CMT_TOP_LOGIC_OUTS_L_B10_4" + ], + [ + "CMT_FIFO_EE2A1_11", + "CMT_TOP_EE2A1_8" + ], + [ + "CMT_FIFO_SE4BEG1_3", + "CMT_TOP_SE4BEG1_0" + ], + [ + "CMT_FIFO_WW4END3_10", + "CMT_TOP_WW4END3_7" + ], + [ + "CMT_FIFO_L_IMUX39_6", + "CMT_TOP_IMUX39_3" + ], + [ + "CMT_FIFO_NE4C3_9", + "CMT_TOP_NE4C3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_9", + "CMT_TOP_LOGIC_OUTS_L_B13_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_4", + "CMT_TOP_LOGIC_OUTS_L_B6_1" + ], + [ + "CMT_FIFO_L_IMUX10_7", + "CMT_TOP_IMUX10_4" + ], + [ + "CMT_FIFO_L_IMUX21_5", + "CMT_TOP_IMUX21_2" + ], + [ + "CMT_FIFO_SE4BEG0_3", + "CMT_TOP_SE4BEG0_0" + ], + [ + "CMT_FIFO_L_IMUX3_3", + "CMT_TOP_IMUX3_0" + ], + [ + "CMT_FIFO_L_IMUX14_7", + "CMT_TOP_IMUX14_4" + ], + [ + "CMT_FIFO_EE2A0_8", + "CMT_TOP_EE2A0_5" + ], + [ + "CMT_FIFO_L_IMUX11_6", + "CMT_TOP_IMUX11_3" + ], + [ + "CMT_FIFO_L_IMUX12_4", + "CMT_TOP_IMUX12_1" + ], + [ + "CMT_FIFO_NW4A2_9", + "CMT_TOP_NW4A2_6" + ], + [ + "CMT_FIFO_NE4C0_8", + "CMT_TOP_NE4C0_5" + ], + [ + "CMT_FIFO_L_CLK1_5", + "CMT_TOP_CLK1_2" + ], + [ + "CMT_FIFO_EE4A1_9", + "CMT_TOP_EE4A1_6" + ], + [ + "CMT_FIFO_SE4BEG3_11", + "CMT_TOP_SE4BEG3_8" + ], + [ + "CMT_FIFO_EE4BEG3_9", + "CMT_TOP_EE4BEG3_6" + ], + [ + "CMT_FIFO_SW2A1_8", + "CMT_TOP_SW2A1_5" + ], + [ + "CMT_FIFO_NW4END2_3", + "CMT_TOP_NW4END2_0" + ], + [ + "CMT_FIFO_SW4A2_7", + "CMT_TOP_SW4A2_4" + ], + [ + "CMT_FIFO_L_FAN2_9", + "CMT_TOP_FAN2_6" + ], + [ + "CMT_FIFO_L_IMUX45_8", + "CMT_TOP_IMUX45_5" + ], + [ + "CMT_FIFO_L_IMUX23_6", + "CMT_TOP_IMUX23_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_4", + "CMT_TOP_LOGIC_OUTS_L_B8_1" + ], + [ + "CMT_FIFO_EE4BEG1_4", + "CMT_TOP_EE4BEG1_1" + ], + [ + "CMT_FIFO_L_FAN3_5", + "CMT_TOP_FAN3_2" + ], + [ + "CMT_FIFO_ER1BEG1_9", + "CMT_TOP_ER1BEG1_6" + ], + [ + "CMT_FIFO_L_IMUX47_8", + "CMT_TOP_IMUX47_5" + ], + [ + "CMT_FIFO_EE4B0_3", + "CMT_TOP_EE4B0_0" + ], + [ + "CMT_FIFO_SW4A0_5", + "CMT_TOP_SW4A0_2" + ], + [ + "CMT_FIFO_LH12_6", + "CMT_TOP_LH12_3" + ], + [ + "CMT_FIFO_NW2A3_8", + "CMT_TOP_NW2A3_5" + ], + [ + "CMT_FIFO_L_IMUX30_3", + "CMT_TOP_IMUX30_0" + ], + [ + "CMT_FIFO_L_IMUX5_3", + "CMT_TOP_IMUX5_0" + ], + [ + "CMT_FIFO_WR1END0_4", + "CMT_TOP_WR1END0_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "CMT_TOP_OCLKDIV_7" + ], + [ + "CMT_FIFO_L_CTRL1_9", + "CMT_TOP_CTRL1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_5", + "CMT_TOP_LOGIC_OUTS_L_B11_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_8", + "CMT_TOP_LOGIC_OUTS_L_B14_5" + ], + [ + "CMT_FIFO_NE4C0_5", + "CMT_TOP_NE4C0_2" + ], + [ + "CMT_FIFO_L_FAN5_11", + "CMT_TOP_FAN5_8" + ], + [ + "CMT_FIFO_SW4END1_10", + "CMT_TOP_SW4END1_7" + ], + [ + "CMT_FIFO_EE4C2_11", + "CMT_TOP_EE4C2_8" + ], + [ + "CMT_FIFO_L_IMUX40_3", + "CMT_TOP_IMUX40_0" + ], + [ + "CMT_FIFO_L_IMUX26_6", + "CMT_TOP_IMUX26_3" + ], + [ + "CMT_FIFO_L_IMUX0_6", + "CMT_TOP_IMUX0_3" + ], + [ + "CMT_FIFO_L_IMUX11_3", + "CMT_TOP_IMUX11_0" + ], + [ + "CMT_FIFO_SE2A0_11", + "CMT_TOP_SE2A0_8" + ], + [ + "CMT_FIFO_L_IMUX44_7", + "CMT_TOP_IMUX44_4" + ], + [ + "CMT_FIFO_L_IMUX26_9", + "CMT_TOP_IMUX26_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_6", + "CMT_TOP_LOGIC_OUTS_L_B5_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_10", + "CMT_TOP_LOGIC_OUTS_L_B8_7" + ], + [ + "CMT_FIFO_L_BYP4_6", + "CMT_TOP_BYP4_3" + ], + [ + "CMT_FIFO_L_IMUX39_9", + "CMT_TOP_IMUX39_6" + ], + [ + "CMT_FIFO_WL1END3_8", + "CMT_TOP_WL1END3_5" + ], + [ + "CMT_FIFO_L_IMUX41_11", + "CMT_TOP_IMUX41_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_6", + "CMT_TOP_LOGIC_OUTS_L_B12_3" + ], + [ + "CMT_FIFO_WR1END1_11", + "CMT_TOP_WR1END1_8" + ], + [ + "CMT_FIFO_NW4A0_6", + "CMT_TOP_NW4A0_3" + ], + [ + "CMT_FIFO_SW2A3_8", + "CMT_TOP_SW2A3_5" + ], + [ + "CMT_FIFO_EE4C1_8", + "CMT_TOP_EE4C1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_10", + "CMT_TOP_LOGIC_OUTS_L_B20_7" + ], + [ + "CMT_FIFO_WW2A2_10", + "CMT_TOP_WW2A2_7" + ], + [ + "CMT_FIFO_WW4B1_8", + "CMT_TOP_WW4B1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_11", + "CMT_TOP_LOGIC_OUTS_L_B6_8" + ], + [ + "CMT_FIFO_NW2A1_7", + "CMT_TOP_NW2A1_4" + ], + [ + "CMT_FIFO_L_IMUX26_4", + "CMT_TOP_IMUX26_1" + ], + [ + "CMT_FIFO_L_IMUX20_4", + "CMT_TOP_IMUX20_1" + ], + [ + "CMT_FIFO_EE4A3_10", + "CMT_TOP_EE4A3_7" + ], + [ + "CMT_FIFO_NW2A2_7", + "CMT_TOP_NW2A2_4" + ], + [ + "CMT_FIFO_L_IMUX9_4", + "CMT_TOP_IMUX9_1" + ], + [ + "CMT_FIFO_L_IMUX32_11", + "CMT_TOP_IMUX32_8" + ], + [ + "CMT_FIFO_EE4B0_7", + "CMT_TOP_EE4B0_4" + ], + [ + "CMT_FIFO_SE4C2_7", + "CMT_TOP_SE4C2_4" + ], + [ + "CMT_FIFO_EE2A3_5", + "CMT_TOP_EE2A3_2" + ], + [ + "CMT_FIFO_EL1BEG2_9", + "CMT_TOP_EL1BEG2_6" + ], + [ + "CMT_FIFO_L_IMUX37_11", + "CMT_TOP_IMUX37_8" + ], + [ + "CMT_FIFO_NW2A0_6", + "CMT_TOP_NW2A0_3" + ], + [ + "CMT_FIFO_SE4C3_7", + "CMT_TOP_SE4C3_4" + ], + [ + "CMT_FIFO_EL1BEG0_8", + "CMT_TOP_EL1BEG0_5" + ], + [ + "CMT_FIFO_SW2A2_4", + "CMT_TOP_SW2A2_1" + ], + [ + "CMT_FIFO_WW4A0_9", + "CMT_TOP_WW4A0_6" + ], + [ + "CMT_FIFO_NW4A2_11", + "CMT_TOP_NW4A2_8" + ], + [ + "CMT_FIFO_WW2END3_11", + "CMT_TOP_WW2END3_8" + ], + [ + "CMT_FIFO_WL1END3_9", + "CMT_TOP_WL1END3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_5", + "CMT_TOP_LOGIC_OUTS_L_B22_2" + ], + [ + "CMT_FIFO_L_BYP3_6", + "CMT_TOP_BYP3_3" + ], + [ + "CMT_FIFO_NW4END1_10", + "CMT_TOP_NW4END1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_5", + "CMT_TOP_LOGIC_OUTS_L_B19_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_10", + "CMT_TOP_LOGIC_OUTS_L_B21_7" + ], + [ + "CMT_FIFO_L_IMUX31_11", + "CMT_TOP_IMUX31_8" + ], + [ + "CMT_FIFO_EL1BEG3_9", + "CMT_TOP_EL1BEG3_6" + ], + [ + "CMT_FIFO_L_IMUX15_7", + "CMT_TOP_IMUX15_4" + ], + [ + "CMT_FIFO_NE2A1_7", + "CMT_TOP_NE2A1_4" + ], + [ + "CMT_FIFO_NE2A3_6", + "CMT_TOP_NE2A3_3" + ], + [ + "CMT_FIFO_EE4C3_11", + "CMT_TOP_EE4C3_8" + ], + [ + "CMT_FIFO_SW4A2_8", + "CMT_TOP_SW4A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_6", + "CMT_TOP_LOGIC_OUTS_L_B13_3" + ], + [ + "CMT_FIFO_WW2A2_6", + "CMT_TOP_WW2A2_3" + ], + [ + "CMT_FIFO_L_IMUX28_4", + "CMT_TOP_IMUX28_1" + ], + [ + "CMT_FIFO_LH10_3", + "CMT_TOP_LH10_0" + ], + [ + "CMT_FIFO_L_FAN7_6", + "CMT_TOP_FAN7_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_11", + "CMT_TOP_LOGIC_OUTS_L_B19_8" + ], + [ + "CMT_FIFO_LH9_5", + "CMT_TOP_LH9_2" + ], + [ + "CMT_FIFO_L_IMUX16_9", + "CMT_TOP_IMUX16_6" + ], + [ + "CMT_FIFO_WW2END0_4", + "CMT_TOP_WW2END0_1" + ], + [ + "CMT_FIFO_LH11_11", + "CMT_TOP_LH11_8" + ], + [ + "CMT_FIFO_L_IMUX22_9", + "CMT_TOP_IMUX22_6" + ], + [ + "CMT_FIFO_NE4C3_5", + "CMT_TOP_NE4C3_2" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "CMT_TOP_L_LOWER_T" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_PMV2_SVT" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_MTBF2" + ] + }, + { + "grid_deltas": [ + -1, + 6 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW4A2_4", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_LH8_4", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_NW2A2_4", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_NE2A3_4", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_ER1BEG0_4", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_SE4BEG1_4", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_EL1BEG1_4", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NE4BEG3_4", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW4A1_4", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EL1BEG0_4", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE2BEG0_4", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW2A3_4", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WW4C1_4", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_EE4B3_4", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_EE2BEG1_4", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NE4BEG0_4", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_WW4A3_4", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NE4BEG1_4", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG0_4", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_LH10_4", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_NW4A0_4", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SW2A2_4", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_LH5_4", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_NW4END2_4", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4B3_4", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_EE2A3_4", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW4C3_4", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4END1_4", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_SW4A2_4", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_EE4A1_4", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NW4A3_4", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_NW4END3_4", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_NW4END1_4", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_LH7_4", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4A0_4", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE4C0_4", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WL1END1_4", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_NW2A3_4", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NW2A0_4", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WW2END3_4", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_LH3_4", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_WW4END0_4", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EL1BEG2_4", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_EE4B1_4", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_SE4C1_4", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_SW4A1_4", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NW4A2_4", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_EE4A3_4", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE4BEG2_4", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_NE4C0_4", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_WW4END2_4", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_EE4C1_4", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE2BEG2_4", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_EE4BEG1_4", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG3_4", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EE2A0_4", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_SE4BEG2_4", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WR1END0_4", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_WW2END1_4", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_WW4END3_4", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4C2_4", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_LH6_4", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_EE4BEG0_4", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NE4C1_4", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NW4END0_4", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SE2A1_4", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_EE4B2_4", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE4BEG3_4", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_SW2A0_4", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WW4B2_4", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_WW4B0_4", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_SW4END3_4", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_EE2A1_4", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_LH12_4", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_SW4END0_4", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WR1END2_4", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_NE2A1_4", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_EE4A2_4", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_NE4BEG2_4", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EE4A0_4", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_ER1BEG2_4", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_WW2END0_4", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NE2A2_4", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_ER1BEG1_4", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SE2A0_4", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SW2A1_4", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_WL1END2_4", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_EE2A2_4", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WL1END3_4", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE2BEG3_4", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_LH4_4", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SE2A3_4", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_WW4B1_4", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_EL1BEG3_4", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WL1END0_4", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_WW2A2_4", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4C3_4", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WR1END1_4", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SW4END2_4", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WW2END2_4", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SE4C2_4", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_WW2A0_4", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WW4C0_4", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_SW2A3_4", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_LH9_4", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_ER1BEG3_4", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_EE4C2_4", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW4A1_4", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SE4C0_4", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_LH1_4", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_SW4END1_4", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_SW4A3_4", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_WR1END3_4", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_NW2A1_4", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C3_4", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_NE2A0_4", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_SW4A0_4", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE4B0_4", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_SE2A2_4", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_LH11_4", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_SE4C3_4", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_LH2_4", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NE4C2_4", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW2A1_4", + "INT_FEEDTHRU_2_WW2A1" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "BRAM_LH2_4", + "VBRK_LH2" + ], + [ + "BRAM_LH12_4", + "VBRK_LH12" + ], + [ + "BRAM_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "BRAM_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "BRAM_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "BRAM_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "BRAM_MONITOR_N_4", + "VBRK_MONITOR_N" + ], + [ + "BRAM_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "BRAM_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "BRAM_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "BRAM_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "BRAM_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "BRAM_LH11_4", + "VBRK_LH11" + ], + [ + "BRAM_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "BRAM_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "BRAM_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "BRAM_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "BRAM_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "BRAM_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "BRAM_LH1_4", + "VBRK_LH1" + ], + [ + "BRAM_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "BRAM_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "BRAM_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "BRAM_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "BRAM_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "BRAM_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "BRAM_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "BRAM_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "BRAM_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "BRAM_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "BRAM_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "BRAM_LH4_4", + "VBRK_LH4" + ], + [ + "BRAM_LH9_4", + "VBRK_LH9" + ], + [ + "BRAM_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "BRAM_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "BRAM_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "BRAM_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "BRAM_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "BRAM_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "BRAM_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "BRAM_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "BRAM_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "BRAM_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "BRAM_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "BRAM_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "BRAM_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "BRAM_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "BRAM_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "BRAM_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "BRAM_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "BRAM_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "BRAM_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "BRAM_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "BRAM_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "BRAM_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "BRAM_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "BRAM_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "BRAM_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "BRAM_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "BRAM_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "BRAM_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "BRAM_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "BRAM_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "BRAM_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "BRAM_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "BRAM_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "BRAM_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "BRAM_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "BRAM_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "BRAM_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "BRAM_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "BRAM_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "BRAM_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "BRAM_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "BRAM_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "BRAM_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "BRAM_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "BRAM_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "BRAM_LH3_4", + "VBRK_LH3" + ], + [ + "BRAM_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "BRAM_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "BRAM_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "BRAM_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "BRAM_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "BRAM_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "BRAM_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "BRAM_MONITOR_P_4", + "VBRK_MONITOR_P" + ], + [ + "BRAM_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "BRAM_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "BRAM_LH5_4", + "VBRK_LH5" + ], + [ + "BRAM_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "BRAM_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "BRAM_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "BRAM_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "BRAM_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "BRAM_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "BRAM_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "BRAM_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "BRAM_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "BRAM_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "BRAM_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "BRAM_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "BRAM_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "BRAM_LH6_4", + "VBRK_LH6" + ], + [ + "BRAM_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "BRAM_LH7_4", + "VBRK_LH7" + ], + [ + "BRAM_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "BRAM_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "BRAM_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "BRAM_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "BRAM_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "BRAM_LH10_4", + "VBRK_LH10" + ], + [ + "BRAM_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "BRAM_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "BRAM_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "BRAM_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "BRAM_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "BRAM_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "BRAM_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "BRAM_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "BRAM_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "BRAM_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "BRAM_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "BRAM_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "BRAM_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "BRAM_LH8_4", + "VBRK_LH8" + ] + ], + "tile_types": [ + "BRAM_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 5 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX5_0", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_FAN1_0", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX11_0", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_FAN5_0", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_BYP5_0", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX6_0", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX0_0", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX23_0", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX40_0", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_CTRL0_0", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX25_0", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B17_0", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B10_0", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_BYP4_0", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX4_0", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX3_0", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_FAN2_0", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX7_0", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX18_0", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX31_0", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX46_0", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX45_0", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_BYP3_0", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX14_0", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX24_0", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_FAN3_0", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN6_0", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_LOGIC_OUTS_B3_0", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_LOGIC_OUTS_B13_0", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B9_0", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX26_0", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX1_0", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX27_0", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX47_0", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX44_0", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_CLK1_0", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX39_0", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B7_0", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_FAN0_0", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX30_0", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_CTRL1_0", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX12_0", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B4_0", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_IMUX19_0", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX38_0", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_BYP2_0", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX22_0", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B5_0", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_FAN4_0", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX20_0", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX42_0", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_BYP7_0", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_BYP0_0", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX33_0", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX43_0", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_LOGIC_OUTS_B20_0", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX13_0", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_CLK0_0", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX21_0", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX35_0", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_LOGIC_OUTS_B6_0", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX36_0", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX41_0", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX28_0", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX10_0", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX9_0", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX32_0", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B16_0", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_BYP6_0", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX8_0", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_BYP1_0", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX15_0", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_LOGIC_OUTS_B19_0", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX17_0", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX29_0", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_LOGIC_OUTS_B1_0", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_FAN7_0", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B0_0", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX2_0", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX16_0", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX37_0", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX34_0", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_LOGIC_OUTS_B2_0", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_LOGIC_OUTS_B11_0", + "VBRK_EXT_LOGIC_OUTS_B11" + ] + ], + "tile_types": [ + "GTX_CHANNEL_2", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + 7 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_7" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_7" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_7" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_7" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_7" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_7" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_7" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_7" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_7" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_7" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_7" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_7" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_7" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_7" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_7" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_7" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_7" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_7" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_7" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_7" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_7" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_7" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_7" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_7" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_7" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_7" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_7" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_7" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_7" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_7" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_7" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_7" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_7" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_7" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_7" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_7" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_7" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_7" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_7" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_7" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_7" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_7" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_7" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_7" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_7" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_7" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_7" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_7" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_7" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_7" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_7" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_7" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_7" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_7" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_7" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_7" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_7" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_7" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_7" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_7" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_7" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_7" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_7" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_7" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_7" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_7" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_7" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_7" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_7" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_7" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_7" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_7" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_7" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_7" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_7" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_7" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_7" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_7" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_7" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_7" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_7" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_7" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_7" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_7" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_7" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_7" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_7" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_7" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_7" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_7" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_7" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_7" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_7" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_7" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_7" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_7" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_7" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_7" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_7" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_7" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_7" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_7" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_7" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_7" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_7" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_7" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_7" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_7" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_7" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_7" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_7" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_7" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_7" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_7" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_7" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_7" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_7" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_7" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_7" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_7" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_7" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_7" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_7" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_7" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_MID_FUJI2" + ] + }, + { + "grid_deltas": [ + 0, + -5 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN26" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_HROW_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN31" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_HROW_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_HROW_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN25" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_HROW_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_HROW_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN23" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN6" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_HROW_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_HROW_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN21" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_HROW_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_HROW_R_CK_GCLK4" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_HROW_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_HROW_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_HROW_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN8" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_HROW_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_HROW_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_HROW_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN29" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_HROW_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_HROW_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN24" + ], + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_HROW_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_HROW_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN7" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_HROW_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_HROW_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN2" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_HROW_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN16" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_HROW_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN19" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_HROW_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_HROW_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_HROW_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_HROW_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN30" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN3" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_HROW_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN14" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_HROW_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN9" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_HROW_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_HROW_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN20" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_HROW_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN10" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_HROW_BOT_R" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_TERM_R_GCLK0" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_TERM_R_GCLK31" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_TERM_R_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_TERM_R_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_TERM_R_GCLK15" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_TERM_R_GCLK24" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_TERM_R_GCLK29" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_TERM_R_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_TERM_R_GCLK22" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_TERM_R_GCLK14" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_TERM_R_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_TERM_R_GCLK16" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_TERM_R_GCLK9" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_TERM_R_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_TERM_R_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_TERM_R_GCLK10" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_TERM_R_GCLK26" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_TERM_R_GCLK4" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_TERM_R_GCLK3" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_TERM_R_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_TERM_R_GCLK28" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_TERM_R_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_TERM_R_GCLK25" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_TERM_R_GCLK18" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_TERM_R_GCLK20" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_TERM_R_GCLK12" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_TERM_R_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_TERM_R_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_TERM_R_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_TERM_R_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_TERM_R_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_TERM_R_GCLK6" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_TERM" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLBLL_L_CIN", + "HCLK_CLB_COUT1_L" + ], + [ + "CLBLL_LL_CIN", + "HCLK_CLB_COUT0_L" + ] + ], + "tile_types": [ + "CLBLL_L", + "HCLK_CLB" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "EE4B1", + "INT_INTERFACE_EE4A1" + ], + [ + "WW4B0", + "INT_INTERFACE_WW4C0" + ], + [ + "LOGIC_OUTS_L5", + "INT_INTERFACE_LOGIC_OUTS_L5" + ], + [ + "IMUX_L26", + "INT_INTERFACE_IMUX26" + ], + [ + "SE2END0", + "INT_INTERFACE_SE2A0" + ], + [ + "LOGIC_OUTS_L17", + "INT_INTERFACE_LOGIC_OUTS_L17" + ], + [ + "ER1END3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "BYP_L2", + "INT_INTERFACE_BYP2" + ], + [ + "EE2A2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "NW6BEG3", + "INT_INTERFACE_NW4A3" + ], + [ + "IMUX_L32", + "INT_INTERFACE_IMUX32" + ], + [ + "NE6A3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "SW6E0", + "INT_INTERFACE_SW4END0" + ], + [ + "IMUX_L28", + "INT_INTERFACE_IMUX28" + ], + [ + "NE6END3", + "INT_INTERFACE_NE4C3" + ], + [ + "LOGIC_OUTS_L14", + "INT_INTERFACE_LOGIC_OUTS_L14" + ], + [ + "NW2A3", + "INT_INTERFACE_NW2A3" + ], + [ + "WW2BEG3", + "INT_INTERFACE_WW2A3" + ], + [ + "EE4A3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "BYP_L7", + "INT_INTERFACE_BYP7" + ], + [ + "SW6E3", + "INT_INTERFACE_SW4END3" + ], + [ + "WW4C2", + "INT_INTERFACE_WW4END2" + ], + [ + "WW2BEG1", + "INT_INTERFACE_WW2A1" + ], + [ + "BYP_L0", + "INT_INTERFACE_BYP0" + ], + [ + "LH7", + "INT_INTERFACE_LH8" + ], + [ + "LOGIC_OUTS_L3", + "INT_INTERFACE_LOGIC_OUTS_L3" + ], + [ + "SW2A1", + "INT_INTERFACE_SW2A1" + ], + [ + "NE6A0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "WW2A1", + "INT_INTERFACE_WW2END1" + ], + [ + "IMUX_L11", + "INT_INTERFACE_IMUX11" + ], + [ + "LOGIC_OUTS_L4", + "INT_INTERFACE_LOGIC_OUTS_L4" + ], + [ + "IMUX_L4", + "INT_INTERFACE_IMUX4" + ], + [ + "IMUX_L35", + "INT_INTERFACE_IMUX35" + ], + [ + "EE4END1", + "INT_INTERFACE_EE4C1" + ], + [ + "IMUX_L19", + "INT_INTERFACE_IMUX19" + ], + [ + "LOGIC_OUTS_L15", + "INT_INTERFACE_LOGIC_OUTS_L15" + ], + [ + "EL1END2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "EE4C3", + "INT_INTERFACE_EE4B3" + ], + [ + "LOGIC_OUTS_L22", + "INT_INTERFACE_LOGIC_OUTS_L22" + ], + [ + "EE4A1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "IMUX_L15", + "INT_INTERFACE_IMUX15" + ], + [ + "SE6A2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "ER1END1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "NW6E2", + "INT_INTERFACE_NW4END2" + ], + [ + "IMUX_L12", + "INT_INTERFACE_IMUX12" + ], + [ + "IMUX_L13", + "INT_INTERFACE_IMUX13" + ], + [ + "IMUX_L1", + "INT_INTERFACE_IMUX1" + ], + [ + "WW4A3", + "INT_INTERFACE_WW4B3" + ], + [ + "SW6E1", + "INT_INTERFACE_SW4END1" + ], + [ + "NE6A2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "LH8", + "INT_INTERFACE_LH9" + ], + [ + "IMUX_L27", + "INT_INTERFACE_IMUX27" + ], + [ + "FAN_L7", + "INT_INTERFACE_FAN7" + ], + [ + "LH10", + "INT_INTERFACE_LH11" + ], + [ + "BYP_L6", + "INT_INTERFACE_BYP6" + ], + [ + "SW6BEG3", + "INT_INTERFACE_SW4A3" + ], + [ + "NW6BEG0", + "INT_INTERFACE_NW4A0" + ], + [ + "EE4END3", + "INT_INTERFACE_EE4C3" + ], + [ + "BYP_L1", + "INT_INTERFACE_BYP1" + ], + [ + "NE2END2", + "INT_INTERFACE_NE2A2" + ], + [ + "INT_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "LH6", + "INT_INTERFACE_LH7" + ], + [ + "INT_PHASER_TO_IO_ICLK", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "IMUX_L7", + "INT_INTERFACE_IMUX7" + ], + [ + "WW4BEG2", + "INT_INTERFACE_WW4A2" + ], + [ + "LOGIC_OUTS_L8", + "INT_INTERFACE_LOGIC_OUTS_L8" + ], + [ + "WL1BEG3", + "INT_INTERFACE_WL1END3" + ], + [ + "WL1BEG2", + "INT_INTERFACE_WL1END2" + ], + [ + "NW6BEG1", + "INT_INTERFACE_NW4A1" + ], + [ + "LH1", + "INT_INTERFACE_LH2" + ], + [ + "WR1BEG3", + "INT_INTERFACE_WR1END3" + ], + [ + "EE2END3", + "INT_INTERFACE_EE2A3" + ], + [ + "WW4C3", + "INT_INTERFACE_WW4END3" + ], + [ + "SE6END3", + "INT_INTERFACE_SE4C3" + ], + [ + "LOGIC_OUTS_L13", + "INT_INTERFACE_LOGIC_OUTS_L13" + ], + [ + "WR1BEG0", + "INT_INTERFACE_WR1END0" + ], + [ + "INT_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90" + ], + [ + "IMUX_L18", + "INT_INTERFACE_IMUX18" + ], + [ + "LOGIC_OUTS_L19", + "INT_INTERFACE_LOGIC_OUTS_L19" + ], + [ + "IMUX_L43", + "INT_INTERFACE_IMUX43" + ], + [ + "IMUX_L29", + "INT_INTERFACE_IMUX29" + ], + [ + "EE4B0", + "INT_INTERFACE_EE4A0" + ], + [ + "NW6E3", + "INT_INTERFACE_NW4END3" + ], + [ + "IMUX_L6", + "INT_INTERFACE_IMUX6" + ], + [ + "LOGIC_OUTS_L10", + "INT_INTERFACE_LOGIC_OUTS_L10" + ], + [ + "WL1BEG0", + "INT_INTERFACE_WL1END0" + ], + [ + "NW6BEG2", + "INT_INTERFACE_NW4A2" + ], + [ + "SE6END0", + "INT_INTERFACE_SE4C0" + ], + [ + "IMUX_L20", + "INT_INTERFACE_IMUX20" + ], + [ + "SW6BEG0", + "INT_INTERFACE_SW4A0" + ], + [ + "FAN_L5", + "INT_INTERFACE_FAN5" + ], + [ + "LOGIC_OUTS_L12", + "INT_INTERFACE_LOGIC_OUTS_L12" + ], + [ + "SE6A3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "SE6A0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "WW4BEG0", + "INT_INTERFACE_WW4A0" + ], + [ + "SW2A3", + "INT_INTERFACE_SW2A3" + ], + [ + "IMUX_L30", + "INT_INTERFACE_IMUX30" + ], + [ + "LH3", + "INT_INTERFACE_LH4" + ], + [ + "IMUX_L0", + "INT_INTERFACE_IMUX0" + ], + [ + "SE6END1", + "INT_INTERFACE_SE4C1" + ], + [ + "LOGIC_OUTS_L2", + "INT_INTERFACE_LOGIC_OUTS_L2" + ], + [ + "NW6E1", + "INT_INTERFACE_NW4END1" + ], + [ + "IMUX_L44", + "INT_INTERFACE_IMUX44" + ], + [ + "WW2BEG2", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_L1", + "INT_INTERFACE_CLK1" + ], + [ + "EE4A0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "FAN_L0", + "INT_INTERFACE_FAN0" + ], + [ + "SE6A1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "WW4A1", + "INT_INTERFACE_WW4B1" + ], + [ + "ER1END0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "FAN_L1", + "INT_INTERFACE_FAN1" + ], + [ + "EE4END2", + "INT_INTERFACE_EE4C2" + ], + [ + "EL1END0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "LH5", + "INT_INTERFACE_LH6" + ], + [ + "IMUX_L21", + "INT_INTERFACE_IMUX21" + ], + [ + "EE2A3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "EE2END2", + "INT_INTERFACE_EE2A2" + ], + [ + "SW6BEG2", + "INT_INTERFACE_SW4A2" + ], + [ + "LOGIC_OUTS_L7", + "INT_INTERFACE_LOGIC_OUTS_L7" + ], + [ + "IMUX_L40", + "INT_INTERFACE_IMUX40" + ], + [ + "EL1END3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "WW2A2", + "INT_INTERFACE_WW2END2" + ], + [ + "IMUX_L3", + "INT_INTERFACE_IMUX3" + ], + [ + "LH2", + "INT_INTERFACE_LH3" + ], + [ + "WR1BEG2", + "INT_INTERFACE_WR1END2" + ], + [ + "IMUX_L37", + "INT_INTERFACE_IMUX37" + ], + [ + "WL1BEG1", + "INT_INTERFACE_WL1END1" + ], + [ + "EE4C0", + "INT_INTERFACE_EE4B0" + ], + [ + "EE4B3", + "INT_INTERFACE_EE4A3" + ], + [ + "WW4A0", + "INT_INTERFACE_WW4B0" + ], + [ + "EL1END1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "IMUX_L16", + "INT_INTERFACE_IMUX16" + ], + [ + "IMUX_L14", + "INT_INTERFACE_IMUX14" + ], + [ + "IMUX_L8", + "INT_INTERFACE_IMUX8" + ], + [ + "NE2END1", + "INT_INTERFACE_NE2A1" + ], + [ + "IMUX_L24", + "INT_INTERFACE_IMUX24" + ], + [ + "LOGIC_OUTS_L23", + "INT_INTERFACE_LOGIC_OUTS_L23" + ], + [ + "WW2A3", + "INT_INTERFACE_WW2END3" + ], + [ + "INT_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "IMUX_L2", + "INT_INTERFACE_IMUX2" + ], + [ + "IMUX_L25", + "INT_INTERFACE_IMUX25" + ], + [ + "SW6E2", + "INT_INTERFACE_SW4END2" + ], + [ + "BYP_L4", + "INT_INTERFACE_BYP4" + ], + [ + "MONITOR_P", + "INT_INTERFACE_MONITOR_P" + ], + [ + "EE4END0", + "INT_INTERFACE_EE4C0" + ], + [ + "WR1BEG1", + "INT_INTERFACE_WR1END1" + ], + [ + "EE2A0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "IMUX_L39", + "INT_INTERFACE_IMUX39" + ], + [ + "WW4C1", + "INT_INTERFACE_WW4END1" + ], + [ + "CTRL_L1", + "INT_INTERFACE_CTRL1" + ], + [ + "BYP_L3", + "INT_INTERFACE_BYP3" + ], + [ + "LOGIC_OUTS_L20", + "INT_INTERFACE_LOGIC_OUTS_L20" + ], + [ + "SE2END3", + "INT_INTERFACE_SE2A3" + ], + [ + "NE6END1", + "INT_INTERFACE_NE4C1" + ], + [ + "INT_PHASER_TO_IO_OCLK", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "MONITOR_N", + "INT_INTERFACE_MONITOR_N" + ], + [ + "LOGIC_OUTS_L0", + "INT_INTERFACE_LOGIC_OUTS_L0" + ], + [ + "LOGIC_OUTS_L18", + "INT_INTERFACE_LOGIC_OUTS_L18" + ], + [ + "WW4A2", + "INT_INTERFACE_WW4B2" + ], + [ + "WW4BEG1", + "INT_INTERFACE_WW4A1" + ], + [ + "LH11", + "INT_INTERFACE_LH12" + ], + [ + "NE6END0", + "INT_INTERFACE_NE4C0" + ], + [ + "EE2END0", + "INT_INTERFACE_EE2A0" + ], + [ + "LOGIC_OUTS_L21", + "INT_INTERFACE_LOGIC_OUTS_L21" + ], + [ + "WW2A0", + "INT_INTERFACE_WW2END0" + ], + [ + "EE4A2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "IMUX_L5", + "INT_INTERFACE_IMUX5" + ], + [ + "LH0", + "INT_INTERFACE_LH1" + ], + [ + "WW4B1", + "INT_INTERFACE_WW4C1" + ], + [ + "EE2A1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "INT_DQS_IOTOPHASER", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "WW4BEG3", + "INT_INTERFACE_WW4A3" + ], + [ + "LOGIC_OUTS_L6", + "INT_INTERFACE_LOGIC_OUTS_L6" + ], + [ + "SE2END2", + "INT_INTERFACE_SE2A2" + ], + [ + "EE4C1", + "INT_INTERFACE_EE4B1" + ], + [ + "EE4C2", + "INT_INTERFACE_EE4B2" + ], + [ + "IMUX_L41", + "INT_INTERFACE_IMUX41" + ], + [ + "IMUX_L9", + "INT_INTERFACE_IMUX9" + ], + [ + "IMUX_L38", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_L0", + "INT_INTERFACE_CLK0" + ], + [ + "FAN_L4", + "INT_INTERFACE_FAN4" + ], + [ + "LOGIC_OUTS_L16", + "INT_INTERFACE_LOGIC_OUTS_L16" + ], + [ + "EE4B2", + "INT_INTERFACE_EE4A2" + ], + [ + "IMUX_L33", + "INT_INTERFACE_IMUX33" + ], + [ + "ER1END2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "WW4B2", + "INT_INTERFACE_WW4C2" + ], + [ + "BYP_L5", + "INT_INTERFACE_BYP5" + ], + [ + "LH4", + "INT_INTERFACE_LH5" + ], + [ + "LOGIC_OUTS_L9", + "INT_INTERFACE_LOGIC_OUTS_L9" + ], + [ + "LOGIC_OUTS_L1", + "INT_INTERFACE_LOGIC_OUTS_L1" + ], + [ + "NW2A2", + "INT_INTERFACE_NW2A2" + ], + [ + "NW2A0", + "INT_INTERFACE_NW2A0" + ], + [ + "IMUX_L10", + "INT_INTERFACE_IMUX10" + ], + [ + "WW2BEG0", + "INT_INTERFACE_WW2A0" + ], + [ + "IMUX_L23", + "INT_INTERFACE_IMUX23" + ], + [ + "IMUX_L36", + "INT_INTERFACE_IMUX36" + ], + [ + "SE2END1", + "INT_INTERFACE_SE2A1" + ], + [ + "WW4C0", + "INT_INTERFACE_WW4END0" + ], + [ + "IMUX_L46", + "INT_INTERFACE_IMUX46" + ], + [ + "FAN_L2", + "INT_INTERFACE_FAN2" + ], + [ + "SW2A2", + "INT_INTERFACE_SW2A2" + ], + [ + "IMUX_L22", + "INT_INTERFACE_IMUX22" + ], + [ + "NE2END0", + "INT_INTERFACE_NE2A0" + ], + [ + "IMUX_L31", + "INT_INTERFACE_IMUX31" + ], + [ + "NE6END2", + "INT_INTERFACE_NE4C2" + ], + [ + "LOGIC_OUTS_L11", + "INT_INTERFACE_LOGIC_OUTS_L11" + ], + [ + "FAN_L6", + "INT_INTERFACE_FAN6" + ], + [ + "WW4B3", + "INT_INTERFACE_WW4C3" + ], + [ + "IMUX_L17", + "INT_INTERFACE_IMUX17" + ], + [ + "SW2A0", + "INT_INTERFACE_SW2A0" + ], + [ + "SW6BEG1", + "INT_INTERFACE_SW4A1" + ], + [ + "NE6A1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "NE2END3", + "INT_INTERFACE_NE2A3" + ], + [ + "IMUX_L45", + "INT_INTERFACE_IMUX45" + ], + [ + "IMUX_L34", + "INT_INTERFACE_IMUX34" + ], + [ + "CTRL_L0", + "INT_INTERFACE_CTRL0" + ], + [ + "EE2END1", + "INT_INTERFACE_EE2A1" + ], + [ + "NW2A1", + "INT_INTERFACE_NW2A1" + ], + [ + "LH9", + "INT_INTERFACE_LH10" + ], + [ + "IMUX_L47", + "INT_INTERFACE_IMUX47" + ], + [ + "IMUX_L42", + "INT_INTERFACE_IMUX42" + ], + [ + "SE6END2", + "INT_INTERFACE_SE4C2" + ], + [ + "FAN_L3", + "INT_INTERFACE_FAN3" + ], + [ + "NW6E0", + "INT_INTERFACE_NW4END0" + ] + ], + "tile_types": [ + "INT_L", + "IO_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX21_2", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX41_2", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_BYP5_2", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX20_2", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX39_2", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B4_2", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_FAN4_2", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX31_2", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX2_2", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_FAN0_2", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_LOGIC_OUTS_B18_2", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX26_2", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX6_2", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B2_2", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX3_2", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_FAN5_2", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_LOGIC_OUTS_B22_2", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B3_2", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_LOGIC_OUTS_B6_2", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_LOGIC_OUTS_B8_2", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX16_2", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX32_2", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B9_2", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_BYP3_2", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX17_2", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX30_2", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_LOGIC_OUTS_B23_2", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX13_2", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_LOGIC_OUTS_B0_2", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX9_2", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX1_2", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_FAN3_2", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN6_2", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX18_2", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX27_2", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B7_2", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_BYP6_2", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX46_2", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP7_2", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX36_2", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_LOGIC_OUTS_B13_2", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B21_2", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_IMUX33_2", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX34_2", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX35_2", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_CTRL0_2", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX37_2", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_BYP4_2", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX5_2", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX44_2", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_FAN1_2", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_BYP1_2", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX12_2", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX0_2", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX29_2", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_CLK0_2", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_LOGIC_OUTS_B11_2", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_LOGIC_OUTS_B16_2", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX45_2", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX10_2", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B5_2", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_LOGIC_OUTS_B17_2", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX23_2", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_LOGIC_OUTS_B20_2", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX7_2", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX24_2", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX47_2", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX28_2", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX4_2", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX11_2", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP0_2", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_CTRL1_2", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX8_2", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX22_2", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX14_2", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_LOGIC_OUTS_B10_2", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_FAN2_2", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX43_2", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_FAN7_2", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX42_2", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_CLK1_2", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_BYP2_2", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX38_2", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX40_2", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX15_2", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX19_2", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX25_2", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B1_2", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_2", + "VBRK_EXT_LOGIC_OUTS_B19" + ] + ], + "tile_types": [ + "GTX_CHANNEL_3", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 0, + -5 + ], + "wire_pairs": [ + [ + "DSP_PCOUT30", + "HCLK_DSP_PCIN30" + ], + [ + "DSP_PCOUT19", + "HCLK_DSP_PCIN19" + ], + [ + "DSP_BCOUT6", + "HCLK_DSP_BCIN6" + ], + [ + "DSP_PCOUT1", + "HCLK_DSP_PCIN1" + ], + [ + "DSP_ACOUT24", + "HCLK_DSP_ACIN24" + ], + [ + "DSP_ACOUT18", + "HCLK_DSP_ACIN18" + ], + [ + "DSP_PCOUT36", + "HCLK_DSP_PCIN36" + ], + [ + "DSP_BCOUT15", + "HCLK_DSP_BCIN15" + ], + [ + "DSP_BCOUT13", + "HCLK_DSP_BCIN13" + ], + [ + "DSP_BCOUT2", + "HCLK_DSP_BCIN2" + ], + [ + "DSP_ACOUT17", + "HCLK_DSP_ACIN17" + ], + [ + "DSP_ACOUT3", + "HCLK_DSP_ACIN3" + ], + [ + "DSP_PCOUT4", + "HCLK_DSP_PCIN4" + ], + [ + "DSP_PCOUT22", + "HCLK_DSP_PCIN22" + ], + [ + "DSP_PCOUT10", + "HCLK_DSP_PCIN10" + ], + [ + "DSP_ACOUT19", + "HCLK_DSP_ACIN19" + ], + [ + "DSP_PCOUT44", + "HCLK_DSP_PCIN44" + ], + [ + "DSP_PCOUT13", + "HCLK_DSP_PCIN13" + ], + [ + "DSP_ACOUT23", + "HCLK_DSP_ACIN23" + ], + [ + "DSP_PCOUT37", + "HCLK_DSP_PCIN37" + ], + [ + "DSP_PCOUT8", + "HCLK_DSP_PCIN8" + ], + [ + "DSP_ACOUT21", + "HCLK_DSP_ACIN21" + ], + [ + "DSP_PCOUT14", + "HCLK_DSP_PCIN14" + ], + [ + "DSP_ACOUT29", + "HCLK_DSP_ACIN29" + ], + [ + "DSP_ACOUT1", + "HCLK_DSP_ACIN1" + ], + [ + "DSP_PCOUT7", + "HCLK_DSP_PCIN7" + ], + [ + "DSP_PCOUT21", + "HCLK_DSP_PCIN21" + ], + [ + "DSP_ACOUT12", + "HCLK_DSP_ACIN12" + ], + [ + "DSP_PCOUT45", + "HCLK_DSP_PCIN45" + ], + [ + "DSP_PCOUT11", + "HCLK_DSP_PCIN11" + ], + [ + "DSP_BCOUT10", + "HCLK_DSP_BCIN10" + ], + [ + "DSP_BCOUT16", + "HCLK_DSP_BCIN16" + ], + [ + "DSP_PCOUT35", + "HCLK_DSP_PCIN35" + ], + [ + "DSP_PCOUT29", + "HCLK_DSP_PCIN29" + ], + [ + "DSP_BCOUT4", + "HCLK_DSP_BCIN4" + ], + [ + "DSP_ACOUT6", + "HCLK_DSP_ACIN6" + ], + [ + "DSP_ACOUT20", + "HCLK_DSP_ACIN20" + ], + [ + "DSP_ACOUT16", + "HCLK_DSP_ACIN16" + ], + [ + "DSP_ACOUT11", + "HCLK_DSP_ACIN11" + ], + [ + "DSP_ACOUT8", + "HCLK_DSP_ACIN8" + ], + [ + "DSP_BCOUT11", + "HCLK_DSP_BCIN11" + ], + [ + "DSP_PCOUT38", + "HCLK_DSP_PCIN38" + ], + [ + "DSP_PCOUT42", + "HCLK_DSP_PCIN42" + ], + [ + "DSP_PCOUT47", + "HCLK_DSP_PCIN47" + ], + [ + "DSP_ACOUT26", + "HCLK_DSP_ACIN26" + ], + [ + "DSP_ACOUT14", + "HCLK_DSP_ACIN14" + ], + [ + "DSP_PCOUT26", + "HCLK_DSP_PCIN26" + ], + [ + "DSP_ACOUT15", + "HCLK_DSP_ACIN15" + ], + [ + "DSP_BCOUT0", + "HCLK_DSP_BCIN0" + ], + [ + "DSP_PCOUT0", + "HCLK_DSP_PCIN0" + ], + [ + "DSP_BCOUT9", + "HCLK_DSP_BCIN9" + ], + [ + "DSP_BCOUT7", + "HCLK_DSP_BCIN7" + ], + [ + "DSP_PCOUT32", + "HCLK_DSP_PCIN32" + ], + [ + "DSP_PCOUT25", + "HCLK_DSP_PCIN25" + ], + [ + "DSP_ACOUT4", + "HCLK_DSP_ACIN4" + ], + [ + "DSP_PCOUT16", + "HCLK_DSP_PCIN16" + ], + [ + "DSP_ACOUT22", + "HCLK_DSP_ACIN22" + ], + [ + "DSP_BCOUT12", + "HCLK_DSP_BCIN12" + ], + [ + "DSP_ACOUT28", + "HCLK_DSP_ACIN28" + ], + [ + "DSP_ACOUT27", + "HCLK_DSP_ACIN27" + ], + [ + "DSP_PCOUT3", + "HCLK_DSP_PCIN3" + ], + [ + "DSP_PCOUT15", + "HCLK_DSP_PCIN15" + ], + [ + "DSP_PCOUT2", + "HCLK_DSP_PCIN2" + ], + [ + "DSP_PCOUT33", + "HCLK_DSP_PCIN33" + ], + [ + "DSP_PCOUT43", + "HCLK_DSP_PCIN43" + ], + [ + "DSP_PCOUT28", + "HCLK_DSP_PCIN28" + ], + [ + "DSP_CARRYCASCOUT", + "HCLK_DSP_CARRYCASCIN" + ], + [ + "DSP_BCOUT1", + "HCLK_DSP_BCIN1" + ], + [ + "DSP_BCOUT5", + "HCLK_DSP_BCIN5" + ], + [ + "DSP_ACOUT2", + "HCLK_DSP_ACIN2" + ], + [ + "DSP_ACOUT25", + "HCLK_DSP_ACIN25" + ], + [ + "DSP_PCOUT24", + "HCLK_DSP_PCIN24" + ], + [ + "DSP_BCOUT8", + "HCLK_DSP_BCIN8" + ], + [ + "DSP_PCOUT9", + "HCLK_DSP_PCIN9" + ], + [ + "DSP_PCOUT31", + "HCLK_DSP_PCIN31" + ], + [ + "DSP_ACOUT9", + "HCLK_DSP_ACIN9" + ], + [ + "DSP_PCOUT40", + "HCLK_DSP_PCIN40" + ], + [ + "DSP_PCOUT27", + "HCLK_DSP_PCIN27" + ], + [ + "DSP_PCOUT12", + "HCLK_DSP_PCIN12" + ], + [ + "DSP_ACOUT10", + "HCLK_DSP_ACIN10" + ], + [ + "DSP_ACOUT0", + "HCLK_DSP_ACIN0" + ], + [ + "DSP_PCOUT5", + "HCLK_DSP_PCIN5" + ], + [ + "DSP_PCOUT18", + "HCLK_DSP_PCIN18" + ], + [ + "DSP_PCOUT6", + "HCLK_DSP_PCIN6" + ], + [ + "DSP_ACOUT7", + "HCLK_DSP_ACIN7" + ], + [ + "DSP_PCOUT39", + "HCLK_DSP_PCIN39" + ], + [ + "DSP_PCOUT41", + "HCLK_DSP_PCIN41" + ], + [ + "DSP_BCOUT3", + "HCLK_DSP_BCIN3" + ], + [ + "DSP_PCOUT34", + "HCLK_DSP_PCIN34" + ], + [ + "DSP_PCOUT20", + "HCLK_DSP_PCIN20" + ], + [ + "DSP_ACOUT5", + "HCLK_DSP_ACIN5" + ], + [ + "DSP_MULTSIGNOUT", + "HCLK_DSP_MULTSIGNIN" + ], + [ + "DSP_BCOUT14", + "HCLK_DSP_BCIN14" + ], + [ + "DSP_PCOUT46", + "HCLK_DSP_PCIN46" + ], + [ + "DSP_ACOUT13", + "HCLK_DSP_ACIN13" + ], + [ + "DSP_BCOUT17", + "HCLK_DSP_BCIN17" + ], + [ + "DSP_PCOUT17", + "HCLK_DSP_PCIN17" + ], + [ + "DSP_PCOUT23", + "HCLK_DSP_PCIN23" + ] + ], + "tile_types": [ + "DSP_L", + "HCLK_DSP_L" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLBLL_WR1END1", + "VBRK_WR1END1" + ], + [ + "CLBLL_WW4C0", + "VBRK_WW4C0" + ], + [ + "CLBLL_EE4B0", + "VBRK_EE4B0" + ], + [ + "CLBLL_NW4END0", + "VBRK_NW4END0" + ], + [ + "CLBLL_WW4A1", + "VBRK_WW4A1" + ], + [ + "CLBLL_SE2A2", + "VBRK_SE2A2" + ], + [ + "CLBLL_LH9", + "VBRK_LH9" + ], + [ + "CLBLL_SW2A0", + "VBRK_SW2A0" + ], + [ + "CLBLL_WW4B3", + "VBRK_WW4B3" + ], + [ + "CLBLL_NW2A0", + "VBRK_NW2A0" + ], + [ + "CLBLL_ER1BEG0", + "VBRK_ER1BEG0" + ], + [ + "CLBLL_LH7", + "VBRK_LH7" + ], + [ + "CLBLL_WW2A1", + "VBRK_WW2A1" + ], + [ + "CLBLL_SE4C3", + "VBRK_SE4C3" + ], + [ + "CLBLL_WW4END3", + "VBRK_WW4END3" + ], + [ + "CLBLL_EE2BEG3", + "VBRK_EE2BEG3" + ], + [ + "CLBLL_WW2A0", + "VBRK_WW2A0" + ], + [ + "CLBLL_SE2A3", + "VBRK_SE2A3" + ], + [ + "CLBLL_EL1BEG1", + "VBRK_EL1BEG1" + ], + [ + "CLBLL_SE4C0", + "VBRK_SE4C0" + ], + [ + "CLBLL_EE4BEG2", + "VBRK_EE4BEG2" + ], + [ + "CLBLL_SW4END2", + "VBRK_SW4END2" + ], + [ + "CLBLL_WW2A2", + "VBRK_WW2A2" + ], + [ + "CLBLL_EE4C0", + "VBRK_EE4C0" + ], + [ + "CLBLL_SE4BEG1", + "VBRK_SE4BEG1" + ], + [ + "CLBLL_NE4BEG1", + "VBRK_NE4BEG1" + ], + [ + "CLBLL_WL1END1", + "VBRK_WL1END1" + ], + [ + "CLBLL_WW2END0", + "VBRK_WW2END0" + ], + [ + "CLBLL_ER1BEG1", + "VBRK_ER1BEG1" + ], + [ + "CLBLL_EE4C3", + "VBRK_EE4C3" + ], + [ + "CLBLL_SE2A1", + "VBRK_SE2A1" + ], + [ + "CLBLL_SW4END3", + "VBRK_SW4END3" + ], + [ + "CLBLL_EE4C2", + "VBRK_EE4C2" + ], + [ + "CLBLL_WW2END1", + "VBRK_WW2END1" + ], + [ + "CLBLL_NW4END1", + "VBRK_NW4END1" + ], + [ + "CLBLL_EE4BEG3", + "VBRK_EE4BEG3" + ], + [ + "CLBLL_WW4A0", + "VBRK_WW4A0" + ], + [ + "CLBLL_LH8", + "VBRK_LH8" + ], + [ + "CLBLL_EE4C1", + "VBRK_EE4C1" + ], + [ + "CLBLL_NE4BEG0", + "VBRK_NE4BEG0" + ], + [ + "CLBLL_SE4BEG2", + "VBRK_SE4BEG2" + ], + [ + "CLBLL_EE4B1", + "VBRK_EE4B1" + ], + [ + "CLBLL_WW4B1", + "VBRK_WW4B1" + ], + [ + "CLBLL_EE4BEG0", + "VBRK_EE4BEG0" + ], + [ + "CLBLL_LH5", + "VBRK_LH5" + ], + [ + "CLBLL_EE2BEG2", + "VBRK_EE2BEG2" + ], + [ + "CLBLL_NE2A0", + "VBRK_NE2A0" + ], + [ + "CLBLL_NW2A3", + "VBRK_NW2A3" + ], + [ + "CLBLL_EL1BEG2", + "VBRK_EL1BEG2" + ], + [ + "CLBLL_WW4B2", + "VBRK_WW4B2" + ], + [ + "CLBLL_SE4C2", + "VBRK_SE4C2" + ], + [ + "CLBLL_LH6", + "VBRK_LH6" + ], + [ + "CLBLL_WR1END0", + "VBRK_WR1END0" + ], + [ + "CLBLL_NW4A2", + "VBRK_NW4A2" + ], + [ + "CLBLL_WL1END0", + "VBRK_WL1END0" + ], + [ + "CLBLL_WW4C2", + "VBRK_WW4C2" + ], + [ + "CLBLL_LH10", + "VBRK_LH10" + ], + [ + "CLBLL_WW4END1", + "VBRK_WW4END1" + ], + [ + "CLBLL_EE4A0", + "VBRK_EE4A0" + ], + [ + "CLBLL_EL1BEG0", + "VBRK_EL1BEG0" + ], + [ + "CLBLL_EE4B3", + "VBRK_EE4B3" + ], + [ + "CLBLL_WW2END3", + "VBRK_WW2END3" + ], + [ + "CLBLL_SW4END0", + "VBRK_SW4END0" + ], + [ + "CLBLL_EE2A0", + "VBRK_EE2A0" + ], + [ + "CLBLL_EE4A3", + "VBRK_EE4A3" + ], + [ + "CLBLL_LH11", + "VBRK_LH11" + ], + [ + "CLBLL_WL1END3", + "VBRK_WL1END3" + ], + [ + "CLBLL_NE4C0", + "VBRK_NE4C0" + ], + [ + "CLBLL_NW4A1", + "VBRK_NW4A1" + ], + [ + "CLBLL_SW4END1", + "VBRK_SW4END1" + ], + [ + "CLBLL_SW4A2", + "VBRK_SW4A2" + ], + [ + "CLBLL_EE2BEG0", + "VBRK_EE2BEG0" + ], + [ + "CLBLL_EE2A3", + "VBRK_EE2A3" + ], + [ + "CLBLL_SE4BEG0", + "VBRK_SE4BEG0" + ], + [ + "CLBLL_WR1END2", + "VBRK_WR1END2" + ], + [ + "CLBLL_WW4C3", + "VBRK_WW4C3" + ], + [ + "CLBLL_LH1", + "VBRK_LH1" + ], + [ + "CLBLL_NW2A1", + "VBRK_NW2A1" + ], + [ + "CLBLL_NW4END2", + "VBRK_NW4END2" + ], + [ + "CLBLL_WL1END2", + "VBRK_WL1END2" + ], + [ + "CLBLL_NW4A3", + "VBRK_NW4A3" + ], + [ + "CLBLL_NW2A2", + "VBRK_NW2A2" + ], + [ + "CLBLL_WR1END3", + "VBRK_WR1END3" + ], + [ + "CLBLL_MONITOR_N", + "VBRK_MONITOR_N" + ], + [ + "CLBLL_LH4", + "VBRK_LH4" + ], + [ + "CLBLL_SW2A3", + "VBRK_SW2A3" + ], + [ + "CLBLL_NW4A0", + "VBRK_NW4A0" + ], + [ + "CLBLL_WW2A3", + "VBRK_WW2A3" + ], + [ + "CLBLL_WW4A2", + "VBRK_WW4A2" + ], + [ + "CLBLL_NE4C2", + "VBRK_NE4C2" + ], + [ + "CLBLL_EE4A1", + "VBRK_EE4A1" + ], + [ + "CLBLL_EL1BEG3", + "VBRK_EL1BEG3" + ], + [ + "CLBLL_NE4BEG2", + "VBRK_NE4BEG2" + ], + [ + "CLBLL_WW4C1", + "VBRK_WW4C1" + ], + [ + "CLBLL_SW2A1", + "VBRK_SW2A1" + ], + [ + "CLBLL_WW4END2", + "VBRK_WW4END2" + ], + [ + "CLBLL_ER1BEG3", + "VBRK_ER1BEG3" + ], + [ + "CLBLL_LH12", + "VBRK_LH12" + ], + [ + "CLBLL_NE4C1", + "VBRK_NE4C1" + ], + [ + "CLBLL_SW4A0", + "VBRK_SW4A0" + ], + [ + "CLBLL_SE4BEG3", + "VBRK_SE4BEG3" + ], + [ + "CLBLL_NW4END3", + "VBRK_NW4END3" + ], + [ + "CLBLL_EE4A2", + "VBRK_EE4A2" + ], + [ + "CLBLL_LH3", + "VBRK_LH3" + ], + [ + "CLBLL_SW2A2", + "VBRK_SW2A2" + ], + [ + "CLBLL_LH2", + "VBRK_LH2" + ], + [ + "CLBLL_NE2A3", + "VBRK_NE2A3" + ], + [ + "CLBLL_NE4C3", + "VBRK_NE4C3" + ], + [ + "CLBLL_EE2BEG1", + "VBRK_EE2BEG1" + ], + [ + "CLBLL_WW4END0", + "VBRK_WW4END0" + ], + [ + "CLBLL_EE2A1", + "VBRK_EE2A1" + ], + [ + "CLBLL_SE4C1", + "VBRK_SE4C1" + ], + [ + "CLBLL_WW4A3", + "VBRK_WW4A3" + ], + [ + "CLBLL_SW4A1", + "VBRK_SW4A1" + ], + [ + "CLBLL_EE4BEG1", + "VBRK_EE4BEG1" + ], + [ + "CLBLL_MONITOR_P", + "VBRK_MONITOR_P" + ], + [ + "CLBLL_EE2A2", + "VBRK_EE2A2" + ], + [ + "CLBLL_ER1BEG2", + "VBRK_ER1BEG2" + ], + [ + "CLBLL_SW4A3", + "VBRK_SW4A3" + ], + [ + "CLBLL_SE2A0", + "VBRK_SE2A0" + ], + [ + "CLBLL_WW4B0", + "VBRK_WW4B0" + ], + [ + "CLBLL_NE4BEG3", + "VBRK_NE4BEG3" + ], + [ + "CLBLL_WW2END2", + "VBRK_WW2END2" + ], + [ + "CLBLL_EE4B2", + "VBRK_EE4B2" + ], + [ + "CLBLL_NE2A2", + "VBRK_NE2A2" + ], + [ + "CLBLL_NE2A1", + "VBRK_NE2A1" + ] + ], + "tile_types": [ + "CLBLL_L", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW2A2_5", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A0_5", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END2_5", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SE4C1_5", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SW4END3_5", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NW4END0_5", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW2A0_5", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WL1END3_5", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SE2A2_5", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4B3_5", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_LH3_5", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE2A2_5", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_5", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4C2_5", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2A0_5", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG1_5", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A1_5", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4A2_5", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END1_5", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW4C0_5", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_5", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4END3_5", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4BEG0_5", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH6_5", + "VBRK_LH6" + ], + [ + "CMT_TOP_EL1BEG1_5", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_EE4A1_5", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NW4A2_5", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4A3_5", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NE4BEG0_5", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW2A2_5", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C3_5", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH7_5", + "VBRK_LH7" + ], + [ + "CMT_TOP_WW4B2_5", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH5_5", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4A1_5", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4A0_5", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C1_5", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW2A0_5", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WL1END2_5", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_SE4C0_5", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SW4END2_5", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END1_5", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG0_5", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_WR1END1_5", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EE4C1_5", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG0_5", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NW4END2_5", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_EE2BEG2_5", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4B1_5", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_ER1BEG3_5", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NW2A1_5", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B0_5", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END2_5", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A1_5", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE2A3_5", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_LH11_5", + "VBRK_LH11" + ], + [ + "CMT_TOP_WL1END0_5", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SW4END0_5", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4BEG3_5", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C3_5", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_SE4BEG1_5", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NE2A2_5", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B0_5", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_ER1BEG2_5", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_5", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NE2A0_5", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4BEG1_5", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE2A3_5", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG2_5", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_LH9_5", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4END2_5", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4BEG2_5", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2END0_5", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_ER1BEG0_5", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH4_5", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2A1_5", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE2BEG1_5", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_NE4BEG3_5", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C0_5", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH8_5", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4A3_5", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2BEG0_5", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_NE2A1_5", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C3_5", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WL1END1_5", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW4A1_5", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_5", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4A0_5", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4END1_5", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH2_5", + "VBRK_LH2" + ], + [ + "CMT_TOP_NE2A3_5", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW4A0_5", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4A3_5", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4C0_5", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_LH12_5", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH1_5", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_5", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_ER1BEG1_5", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2BEG3_5", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH10_5", + "VBRK_LH10" + ], + [ + "CMT_TOP_SW2A2_5", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WR1END3_5", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NW4END1_5", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NW4A1_5", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WW4C2_5", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WR1END0_5", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4END3_5", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW4A3_5", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4END0_5", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW2A3_5", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4C2_5", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG3_5", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW2A3_5", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4A2_5", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4BEG3_5", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE4B2_5", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW2A0_5", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SE2A0_5", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SE4BEG2_5", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B1_5", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4C1_5", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C2_5", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4C3_5", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_EL1BEG2_5", + "VBRK_EL1BEG2" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLK_HROW_CK_IN_L12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "CLK_HROW_CK_BUFRCLK_L2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "CLK_HROW_CK_IN_L2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "CLK_HROW_CK_IN_L6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "CLK_HROW_CK_BUFHCLK_L11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "CLK_HROW_CK_BUFHCLK_L3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "CLK_HROW_CK_IN_L11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "CLK_HROW_CK_BUFHCLK_L8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "CLK_HROW_CK_BUFHCLK_L0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "CLK_HROW_CK_IN_L5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "CLK_HROW_CK_BUFHCLK_L1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "CLK_HROW_CK_BUFHCLK_L7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "CLK_HROW_CK_BUFHCLK_L10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "CLK_HROW_CK_IN_L9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "CLK_HROW_CK_IN_L7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "CLK_HROW_CK_IN_L0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "CLK_HROW_CK_BUFHCLK_L9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "CLK_HROW_CK_BUFRCLK_L0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "CLK_HROW_CK_IN_L4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "CLK_HROW_CK_IN_L3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "CLK_HROW_CK_IN_L13", + "HCLK_INT_INTERFACE_CK_IN13" + ], + [ + "CLK_HROW_CK_IN_L1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "CLK_HROW_CK_BUFHCLK_L4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "CLK_HROW_CK_BUFRCLK_L1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "CLK_HROW_CK_IN_L8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "CLK_HROW_CK_BUFRCLK_L3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "CLK_HROW_CK_BUFHCLK_L2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "CLK_HROW_CK_BUFHCLK_L6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "CLK_HROW_CK_IN_L10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "CLK_HROW_CK_BUFHCLK_L5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "HCLK_INT_INTERFACE" + ] + }, + { + "grid_deltas": [ + 1, + 7 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_7" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_7" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_7" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_7" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_7" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_7" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_7" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_7" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_7" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_7" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_7" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_7" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_7" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_7" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_7" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_7" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_7" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_7" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_7" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_7" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_7" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_7" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_7" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_7" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_7" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_7" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_7" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_7" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_7" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_7" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_7" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_7" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_7" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_7" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_7" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_7" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_7" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_7" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_7" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_7" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_7" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_7" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_7" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_7" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_7" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_7" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_7" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_7" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_7" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_7" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_7" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_7" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_7" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_7" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_7" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_7" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_7" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_7" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_7" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_7" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_7" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_7" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_7" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_7" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_7" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_7" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_7" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_7" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_7" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_7" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_7" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_7" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_7" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_7" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_7" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_7" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_7" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_7" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_7" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_7" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_7" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_7" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_7" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_7" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_7" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_7" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_7" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_7" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_7" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_7" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_7" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_7" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_7" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_7" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_7" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_7" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_7" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_7" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_7" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_7" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_7" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_7" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_7" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_7" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_7" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_7" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_7" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_7" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_7" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_7" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_7" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_7" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_7" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_7" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_7" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_7" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_7" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_7" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_7" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_7" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_7" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_7" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_7" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_7" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_BOT_FUJI2" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_IN7", + "HCLK_CLB_CK_IN7" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CLB_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CLB_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CLB_CK_IN4" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_CLB_PERFCLK3" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_CLB_PERFCLK2" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CLB_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CLB_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CLB_CK_IN3" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CLB_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CLB_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CLB_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CLB_CK_IN13" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CLB_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CLB_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CLB_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CLB_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CLB_CK_IN1" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CLB_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CLB_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CLB_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_CLB_CK_IN0" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CLB_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CLB_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_CLB_PERFCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CLB_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CLB_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CLB_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CLB_CK_IN2" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CLB_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CLB_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CLB_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CLB_CK_IN6" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_CLB_PERFCLK0" + ] + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_CLB" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW4A2_4", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_LH8_4", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_NW2A2_4", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_NE2A3_4", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_ER1BEG0_4", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_SE4BEG1_4", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_EL1BEG1_4", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NE4BEG3_4", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW4A1_4", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EL1BEG0_4", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE2BEG0_4", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW2A3_4", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WW4C1_4", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_EE4B3_4", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_EE2BEG1_4", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NE4BEG0_4", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_WW4A3_4", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NE4BEG1_4", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG0_4", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_LH10_4", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_NW4A0_4", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SW2A2_4", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_LH5_4", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_NW4END2_4", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4B3_4", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_EE2A3_4", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW4C3_4", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4END1_4", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_SW4A2_4", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_EE4A1_4", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NW4A3_4", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_NW4END3_4", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_NW4END1_4", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_LH7_4", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4A0_4", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE4C0_4", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WL1END1_4", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_NW2A3_4", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NW2A0_4", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WW2END3_4", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_LH3_4", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_WW4END0_4", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EL1BEG2_4", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_EE4B1_4", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_SE4C1_4", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_SW4A1_4", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NW4A2_4", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_EE4A3_4", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE4BEG2_4", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_NE4C0_4", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_WW4END2_4", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_EE4C1_4", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE2BEG2_4", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_EE4BEG1_4", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG3_4", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EE2A0_4", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_SE4BEG2_4", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WR1END0_4", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_WW2END1_4", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_WW4END3_4", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4C2_4", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_LH6_4", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_EE4BEG0_4", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NE4C1_4", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NW4END0_4", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SE2A1_4", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_EE4B2_4", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE4BEG3_4", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_SW2A0_4", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WW4B2_4", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_WW4B0_4", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_SW4END3_4", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_EE2A1_4", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_LH12_4", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_SW4END0_4", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WR1END2_4", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_NE2A1_4", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_EE4A2_4", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_NE4BEG2_4", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EE4A0_4", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_ER1BEG2_4", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_WW2END0_4", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NE2A2_4", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_ER1BEG1_4", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SE2A0_4", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SW2A1_4", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_WL1END2_4", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_EE2A2_4", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WL1END3_4", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE2BEG3_4", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_LH4_4", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SE2A3_4", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_WW4B1_4", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_EL1BEG3_4", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WL1END0_4", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_WW2A2_4", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4C3_4", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WR1END1_4", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SW4END2_4", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WW2END2_4", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SE4C2_4", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_WW2A0_4", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WW4C0_4", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_SW2A3_4", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_LH9_4", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_ER1BEG3_4", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_EE4C2_4", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW4A1_4", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SE4C0_4", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_LH1_4", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_SW4END1_4", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_SW4A3_4", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_WR1END3_4", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_NW2A1_4", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C3_4", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_NE2A0_4", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_SW4A0_4", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE4B0_4", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_SE2A2_4", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_LH11_4", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_SE4C3_4", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_LH2_4", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NE4C2_4", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW2A1_4", + "INT_FEEDTHRU_2_WW2A1" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_FIFO_CCIO0", + "HCLK_INT_INTERFACE_CCIO0" + ], + [ + "HCLK_FIFO_CCIO1", + "HCLK_INT_INTERFACE_CCIO1" + ], + [ + "HCLK_FIFO_PERFCLK2", + "HCLK_INT_INTERFACE_PERFCLK2" + ], + [ + "HCLK_FIFO_PERFCLK0", + "HCLK_INT_INTERFACE_PERFCLK0" + ], + [ + "HCLK_FIFO_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_FIFO_CCIO3", + "HCLK_INT_INTERFACE_CCIO3" + ], + [ + "HCLK_FIFO_PERFCLK3", + "HCLK_INT_INTERFACE_PERFCLK3" + ], + [ + "HCLK_FIFO_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_FIFO_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_FIFO_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_FIFO_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_FIFO_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_FIFO_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_FIFO_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_FIFO_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_FIFO_PERFCLK1", + "HCLK_INT_INTERFACE_PERFCLK1" + ], + [ + "HCLK_FIFO_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_FIFO_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_FIFO_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_FIFO_CCIO2", + "HCLK_INT_INTERFACE_CCIO2" + ], + [ + "HCLK_FIFO_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_FIFO_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_FIFO_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_FIFO_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ] + ], + "tile_types": [ + "HCLK_FIFO_L", + "HCLK_INT_INTERFACE" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "BRKH_CLB_COUT1_L", + "CLBLL_L_CIN" + ], + [ + "BRKH_CLB_COUT0_L", + "CLBLL_LL_CIN" + ] + ], + "tile_types": [ + "BRKH_CLB", + "CLBLL_L" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "IOI_IMUX11_0", + "TERM_INT_IMUX11" + ], + [ + "IOI_IMUX43_0", + "TERM_INT_IMUX43" + ], + [ + "IOI_FAN1_0", + "TERM_INT_FAN1" + ], + [ + "IOI_LOGIC_OUTS18_0", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_CTRL1_0", + "TERM_INT_CTRL1" + ], + [ + "IOI_BYP2_0", + "TERM_INT_BYP2" + ], + [ + "IOI_LOGIC_OUTS2_0", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_IMUX6_0", + "TERM_INT_IMUX6" + ], + [ + "IOI_IMUX36_0", + "TERM_INT_IMUX36" + ], + [ + "IOI_IMUX34_0", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX0_0", + "TERM_INT_IMUX0" + ], + [ + "IOI_IMUX46_0", + "TERM_INT_IMUX46" + ], + [ + "IOI_LOGIC_OUTS23_0", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_IMUX20_0", + "TERM_INT_IMUX20" + ], + [ + "IOI_LOGIC_OUTS15_0", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX19_0", + "TERM_INT_IMUX19" + ], + [ + "IOI_IMUX47_0", + "TERM_INT_IMUX47" + ], + [ + "IOI_IMUX25_0", + "TERM_INT_IMUX25" + ], + [ + "IOI_LOGIC_OUTS7_0", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_FAN2_0", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX45_0", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX31_0", + "TERM_INT_IMUX31" + ], + [ + "IOI_LOGIC_OUTS19_0", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_IMUX1_0", + "TERM_INT_IMUX1" + ], + [ + "IOI_MONITOR_N", + "TERM_INT_MONITOR_N" + ], + [ + "IOI_IMUX22_0", + "TERM_INT_IMUX22" + ], + [ + "IOI_IMUX12_0", + "TERM_INT_IMUX12" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_BLOCK_OUTS2_0", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "IOI_IMUX40_0", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX10_0", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX16_0", + "TERM_INT_IMUX16" + ], + [ + "IOI_FAN0_0", + "TERM_INT_FAN0" + ], + [ + "IOI_IMUX38_0", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX26_0", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX3_0", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX24_0", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX37_0", + "TERM_INT_IMUX37" + ], + [ + "IOI_LOGIC_OUTS3_0", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_FAN4_0", + "TERM_INT_FAN4" + ], + [ + "IOI_FAN6_0", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX7_0", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX39_0", + "TERM_INT_IMUX39" + ], + [ + "IOI_CLK0_0", + "TERM_INT_CLK0" + ], + [ + "IOI_CTRL0_0", + "TERM_INT_CTRL0" + ], + [ + "IOI_CLK1_0", + "TERM_INT_CLK1" + ], + [ + "IOI_FAN7_0", + "TERM_INT_FAN7" + ], + [ + "IOI_BYP0_0", + "TERM_INT_BYP0" + ], + [ + "IOI_LOGIC_OUTS0_0", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_IMUX8_0", + "TERM_INT_IMUX8" + ], + [ + "IOI_LOGIC_OUTS11_0", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_BYP6_0", + "TERM_INT_BYP6" + ], + [ + "IOI_IMUX42_0", + "TERM_INT_IMUX42" + ], + [ + "IOI_IMUX30_0", + "TERM_INT_IMUX30" + ], + [ + "IOI_LOGIC_OUTS1_0", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX5_0", + "TERM_INT_IMUX5" + ], + [ + "IOI_IMUX4_0", + "TERM_INT_IMUX4" + ], + [ + "IOI_IMUX17_0", + "TERM_INT_IMUX17" + ], + [ + "IOI_IMUX23_0", + "TERM_INT_IMUX23" + ], + [ + "IOI_PHASER_TO_IO_ICLK", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_IMUX33_0", + "TERM_INT_IMUX33" + ], + [ + "IOI_FAN5_0", + "TERM_INT_FAN5" + ], + [ + "IOI_LOGIC_OUTS9_0", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_BYP1_0", + "TERM_INT_BYP1" + ], + [ + "IOI_LOGIC_OUTS14_0", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_IMUX13_0", + "TERM_INT_IMUX13" + ], + [ + "IOI_IMUX44_0", + "TERM_INT_IMUX44" + ], + [ + "IOI_LOGIC_OUTS20_0", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_LOGIC_OUTS5_0", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_IMUX27_0", + "TERM_INT_IMUX27" + ], + [ + "IOI_IMUX18_0", + "TERM_INT_IMUX18" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_IMUX9_0", + "TERM_INT_IMUX9" + ], + [ + "IOI_FAN3_0", + "TERM_INT_FAN3" + ], + [ + "IOI_BYP5_0", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS8_0", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_PHASER_TO_IO_OCLK", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_BYP4_0", + "TERM_INT_BYP4" + ], + [ + "IOI_BYP7_0", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_0", + "TERM_INT_IMUX2" + ], + [ + "IOI_IMUX35_0", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP3_0", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX15_0", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX29_0", + "TERM_INT_IMUX29" + ], + [ + "IOI_LOGIC_OUTS10_0", + "TERM_INT_LOGIC_OUTS_L_B10" + ], + [ + "IOI_IMUX14_0", + "TERM_INT_IMUX14" + ], + [ + "IOI_MONITOR_P", + "TERM_INT_MONITOR_P" + ], + [ + "IOI_IMUX21_0", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX28_0", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX41_0", + "TERM_INT_IMUX41" + ], + [ + "IOI_BLOCK_OUTS0_0", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_IMUX32_0", + "TERM_INT_IMUX32" + ] + ], + "tile_types": [ + "LIOI3_TBYTETERM", + "L_TERM_INT" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ] + ], + "tile_types": [ + "HCLK_DSP_L", + "HCLK_INT_INTERFACE" + ] + }, + { + "grid_deltas": [ + 1, + -6 + ], + "wire_pairs": [ + [ + "CMT_TOP_EE4C0_11", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EL1BEG1_11", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG0_11", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH7_11", + "VBRK_LH7" + ], + [ + "CMT_TOP_ER1BEG1_11", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2A0_11", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH3_11", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C1_11", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH2_11", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW2A1_11", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NE2A3_11", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_ER1BEG2_11", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NW4END2_11", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE4BEG3_11", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C3_11", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE2A2_11", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_SW2A0_11", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW4A1_11", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_LH9_11", + "VBRK_LH9" + ], + [ + "CMT_TOP_SE4C3_11", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WR1END0_11", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_11", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EL1BEG2_11", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_NE4BEG2_11", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_11", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4C2_11", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4C2_11", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW4C3_11", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_LH4_11", + "VBRK_LH4" + ], + [ + "CMT_TOP_NE4C2_11", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EE4BEG0_11", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NE2A0_11", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NW4A1_11", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG1_11", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4C1_11", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_EE2A1_11", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END1_11", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SE4C2_11", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A0_11", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE4B0_11", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_11", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW4B0_11", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C0_11", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4BEG2_11", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_LH11_11", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE2BEG3_11", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END2_11", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_11", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4A2_11", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EE4BEG3_11", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_NW4END3_11", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_LH1_11", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE4C0_11", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SW4END3_11", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SW4END1_11", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_11", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END1_11", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW2A3_11", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH8_11", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A0_11", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_11", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW4B3_11", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW4A2_11", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4B2_11", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE2A0_11", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WW2END3_11", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EE4A3_11", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SE4C1_11", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_ER1BEG0_11", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_NW4END1_11", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A3_11", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4A2_11", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4C3_11", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW2A0_11", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NE2A1_11", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW4A3_11", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NW2A3_11", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NE4BEG3_11", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_WW2A2_11", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG0_11", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW2END0_11", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2A3_11", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4A2_11", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG2_11", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW2A1_11", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SW4END2_11", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG0_11", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_EE4C1_11", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG1_11", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG1_11", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2BEG2_11", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SW2A1_11", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE2A2_11", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WR1END1_11", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW2A3_11", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW2A0_11", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW4B1_11", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C0_11", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4BEG1_11", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH12_11", + "VBRK_LH12" + ], + [ + "CMT_TOP_WW4END2_11", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW2A2_11", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_EE4A1_11", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH5_11", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4A0_11", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_SE2A1_11", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END2_11", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WL1END3_11", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_ER1BEG3_11", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WW4B2_11", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WL1END0_11", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW4END0_11", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_11", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A3_11", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4END3_11", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_11", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4A0_11", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A1_11", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH10_11", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW4END1_11", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SW4END0_11", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE2A2_11", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW2A2_11", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG0_11", + "VBRK_EL1BEG0" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4B0_9", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_EE4A1_9", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EE4BEG3_9", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WW2END0_9", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WW4C3_9", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE2BEG3_9", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NW2A3_9", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_EE4A0_9", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_SE4BEG3_9", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_NW4END2_9", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_EL1BEG1_9", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SW4A0_9", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_NE2A3_9", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_NE2A2_9", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_NE4BEG0_9", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_SW2A2_9", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_LH3_9", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SW4END3_9", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_WW4B1_9", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_EE4C3_9", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_NE4C1_9", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_EE2A1_9", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_NE4C3_9", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WW4A3_9", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_SW4A1_9", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_LH10_9", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WW2END2_9", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SE4BEG1_9", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_LH9_9", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_SE4BEG2_9", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_EE4B2_9", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE4B3_9", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NE4BEG1_9", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WR1END1_9", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_EL1BEG2_9", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_NW2A0_9", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_LH11_9", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EE2BEG1_9", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_SW2A1_9", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_LH1_9", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_LH2_9", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_SE2A2_9", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_ER1BEG2_9", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_LH5_9", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE2BEG0_9", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4B3_9", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_WR1END2_9", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_NE2A1_9", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NW4A3_9", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_SW2A3_9", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_WW4A0_9", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SE4C1_9", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_WW4B0_9", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_ER1BEG3_9", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_SE2A0_9", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SE4C2_9", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_NW4A2_9", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NE2A0_9", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_WW2END1_9", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE2A0_9", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_EE4C1_9", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EL1BEG3_9", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WL1END1_9", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_NW4A1_9", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WW2A0_9", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WW2END3_9", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_NE4C0_9", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_ER1BEG1_9", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SE4C3_9", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WL1END0_9", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SW2A0_9", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WR1END3_9", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE2BEG2_9", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_EE4A3_9", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE4BEG1_9", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_EE4A2_9", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_LH4_9", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE4C2_9", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_WW2A1_9", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WW4B2_9", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE4C0_9", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WW4A2_9", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WW4END3_9", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4END2_9", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_NW4END3_9", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_EE4BEG0_9", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WW2A2_9", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WW4C0_9", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NE4BEG2_9", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_NW2A2_9", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_LH8_9", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW2A3_9", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_NW4A0_9", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_LH6_9", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_EE4BEG2_9", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SW4A2_9", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_SE4BEG0_9", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_LH7_9", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4C2_9", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_WW4C1_9", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_LH12_9", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW4A1_9", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_SW4END1_9", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_NW4END0_9", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_ER1BEG0_9", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_WR1END0_9", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_EE4B1_9", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NE4C2_9", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_SE4C0_9", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_WW4END0_9", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_NW4END1_9", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_EL1BEG0_9", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE2A3_9", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NE4BEG3_9", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW4END1_9", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_SE2A3_9", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SW4A3_9", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE2A2_9", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_SW4END0_9", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_SW4END2_9", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WL1END3_9", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_NW2A1_9", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_WL1END2_9", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SE2A1_9", + "INT_FEEDTHRU_2_SE2A1" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -7 + ], + "wire_pairs": [ + [ + "CFG_CENTER_LH11_17", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_WW2END1_17", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_SW2A2_17", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_SW2A1_17", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_IMUX25_17", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_SW2A0_17", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_BYP3_17", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_FAN2_17", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_SW4A0_17", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_LH2_17", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX30_17", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_BYP0_17", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_WW4B1_17", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_IMUX44_17", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_EL1BEG0_17", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_IMUX27_17", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_EE2A2_17", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_IMUX35_17", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_SE2A3_17", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_FAN7_17", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_FAN6_17", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_WW4A1_17", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_WW4B2_17", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_IMUX1_17", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_WW4C0_17", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX38_17", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_NW4A3_17", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_ER1BEG0_17", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_LH9_17", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EE4A3_17", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_SE4C0_17", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_IMUX4_17", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_NW2A0_17", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_FAN3_17", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_WW4END1_17", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_EE4C1_17", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_NW4END2_17", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_EL1BEG2_17", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX9_17", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_WR1END3_17", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_SE4BEG0_17", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_EE2A3_17", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_BYP4_17", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_CLK1_17", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_WW4B0_17", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_IMUX33_17", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_FAN4_17", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_EE4BEG0_17", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_FAN1_17", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_NE4C1_17", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_IMUX42_17", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX47_17", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_WR1END1_17", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NW2A3_17", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_SE4C1_17", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX28_17", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_SE2A0_17", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_SW4A1_17", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_EE4C2_17", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_WW4END2_17", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX40_17", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_ER1BEG2_17", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX13_17", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_EE4A1_17", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_WL1END0_17", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_FAN0_17", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX21_17", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_FAN5_17", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_WW4A2_17", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_WW2END2_17", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_IMUX17_17", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX29_17", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX20_17", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SW4A3_17", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_NW4END0_17", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_EE4BEG1_17", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_WL1END1_17", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_SW2A3_17", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_NE4BEG0_17", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX16_17", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX45_17", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_EE4B1_17", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_BYP5_17", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_NE4BEG1_17", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX10_17", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_IMUX2_17", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_IMUX0_17", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_NE2A1_17", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_EL1BEG1_17", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_NE4C3_17", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_SW4END1_17", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_WW4END3_17", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_NW4A1_17", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SE4BEG3_17", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_WW2A2_17", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_EE2BEG0_17", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_EE4B2_17", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_SE4C2_17", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_IMUX46_17", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW4C1_17", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_BYP2_17", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_NW2A1_17", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_IMUX6_17", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX11_17", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX39_17", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_IMUX14_17", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_LH10_17", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WR1END0_17", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EE4A2_17", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX26_17", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX24_17", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_NE4BEG3_17", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_WW4C3_17", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_ER1BEG3_17", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_IMUX41_17", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX36_17", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW4END0_17", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX18_17", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_WW2END3_17", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW4END0_17", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_CTRL1_17", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_NW4END3_17", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_EE2BEG3_17", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_SE2A2_17", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_SW4END3_17", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_EE2BEG2_17", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_NW4A2_17", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_IMUX31_17", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_IMUX19_17", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_EE4B0_17", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WW2END0_17", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WR1END2_17", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_IMUX22_17", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX34_17", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_LH6_17", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_BYP1_17", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW2A1_17", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_EE2A1_17", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_NE4C0_17", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_SW4END2_17", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_NE4C2_17", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_EE2BEG1_17", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_NW2A2_17", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_EE4C0_17", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_WL1END2_17", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_LH1_17", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NE2A2_17", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_LH8_17", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_IMUX15_17", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_SE4BEG1_17", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_BYP7_17", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_LH7_17", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_EE2A0_17", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_LH5_17", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_EL1BEG3_17", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_SE4BEG2_17", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_CTRL0_17", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_EE4BEG3_17", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_WW4A3_17", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW2A0_17", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_IMUX8_17", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW4A0_17", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_SE2A1_17", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NE2A3_17", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX37_17", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SW4A2_17", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_EE4B3_17", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_NE4BEG2_17", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WL1END3_17", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_LH12_17", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX3_17", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_IMUX7_17", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_ER1BEG1_17", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_NE2A0_17", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX5_17", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_NW4END1_17", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_BYP6_17", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_EE4C3_17", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_WW4B3_17", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_NW4A0_17", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_EE4A0_17", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_IMUX32_17", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_CLK0_17", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX23_17", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_SE4C3_17", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_WW4C2_17", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WW2A3_17", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX43_17", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_LH4_17", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_IMUX12_17", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_LH3_17", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_EE4BEG2_17", + "VFRAME_EE4BEG2" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "B_TERM_UTURN_INT_LVB_L1", + "LVB_L11" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "FAN_BOUNCE4" + ], + [ + "B_TERM_UTURN_INT_SW6B0", + "NW6C3" + ], + [ + "B_TERM_UTURN_INT_SS6B1", + "NN6C2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG0", + "SL1BEG0" + ], + [ + "B_TERM_UTURN_INT_LV_L2", + "LV_L2" + ], + [ + "B_TERM_UTURN_INT_SS6C2", + "SS6C2" + ], + [ + "B_TERM_UTURN_INT_SS6E0", + "SS6E0" + ], + [ + "B_TERM_UTURN_INT_SW6A3", + "NW6B0" + ], + [ + "B_TERM_UTURN_INT_SW6B0", + "SW6B0" + ], + [ + "HCLK_LEAF_CLK_B_TOPL4", + "GCLK_L_B10" + ], + [ + "B_TERM_UTURN_INT_SS6BEG0", + "NN6A3" + ], + [ + "B_TERM_UTURN_INT_SS6A2", + "NN6B1" + ], + [ + "B_TERM_UTURN_INT_SS6C2", + "NN6D1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG0", + "SS2BEG0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG1", + "NL1END2" + ], + [ + "B_TERM_UTURN_INT_SW6B1", + "NW6C2" + ], + [ + "B_TERM_UTURN_INT_SS6C3", + "SS6C3" + ], + [ + "B_TERM_UTURN_INT_ER1END_N3_3", + "ER1END_N3_3" + ], + [ + "B_TERM_UTURN_INT_LV_L3", + "LV_L3" + ], + [ + "B_TERM_UTURN_INT_LV_L6", + "LV_L13" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "FAN_BOUNCE0" + ], + [ + "B_TERM_UTURN_INT_SS6A3", + "NN6B0" + ], + [ + "B_TERM_UTURN_INT_SE6D1", + "NE6E2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG1", + "NR1END2" + ], + [ + "HCLK_LEAF_CLK_B_TOPL0", + "GCLK_L_B6" + ], + [ + "B_TERM_UTURN_INT_SW6C0", + "SW6C0" + ], + [ + "B_TERM_UTURN_INT_SE6A0", + "SE6A0" + ], + [ + "B_TERM_UTURN_INT_LVB_L0", + "LVB_L1" + ], + [ + "B_TERM_UTURN_INT_LV_L18", + "LV_L18" + ], + [ + "B_TERM_UTURN_INT_SW6A0", + "NW6B3" + ], + [ + "B_TERM_UTURN_INT_SS6E0", + "NN6END3" + ], + [ + "B_TERM_UTURN_INT_WR1END0", + "WR1END0" + ], + [ + "B_TERM_UTURN_INT_SE6A2", + "SE6A2" + ], + [ + "B_TERM_UTURN_INT_SS6D1", + "SS6D1" + ], + [ + "B_TERM_UTURN_INT_LVB_L2", + "LVB_L10" + ], + [ + "B_TERM_UTURN_INT_LV_L6", + "LV_L6" + ], + [ + "B_TERM_UTURN_INT_SE6B0", + "SE6B0" + ], + [ + "B_TERM_UTURN_INT_LV_L5", + "LV_L5" + ], + [ + "B_TERM_UTURN_INT_SS6A3", + "SS6A3" + ], + [ + "B_TERM_UTURN_INT_ER1BEG0", + "EL1BEG_N3" + ], + [ + "B_TERM_UTURN_INT_SW6B3", + "NW6C0" + ], + [ + "B_TERM_UTURN_INT_LV_L9", + "LV_L10" + ], + [ + "B_TERM_UTURN_INT_LV_L7", + "LV_L7" + ], + [ + "B_TERM_UTURN_INT_SE6C2", + "SE6C2" + ], + [ + "B_TERM_UTURN_INT_SE6B2", + "SE6B2" + ], + [ + "B_TERM_UTURN_INT_SE6B0", + "NE6C3" + ], + [ + "B_TERM_UTURN_INT_SE6D0", + "NE6E3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG3", + "NN6A0" + ], + [ + "B_TERM_UTURN_INT_SW6D3", + "NW6E0" + ], + [ + "B_TERM_UTURN_INT_SS6BEG0", + "SS6BEG0" + ], + [ + "B_TERM_UTURN_INT_SE6D2", + "NE6E1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG1", + "NN2A2" + ], + [ + "B_TERM_UTURN_INT_SS6D1", + "NN6E2" + ], + [ + "B_TERM_UTURN_INT_SE6C3", + "SE6C3" + ], + [ + "B_TERM_UTURN_INT_SS2A2", + "NN2END1" + ], + [ + "B_TERM_UTURN_INT_SE6D1", + "SE6D1" + ], + [ + "B_TERM_UTURN_INT_SS6D0", + "NN6E3" + ], + [ + "B_TERM_UTURN_INT_SS6B3", + "NN6C0" + ], + [ + "B_TERM_UTURN_INT_SE6A1", + "NE6B2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG2", + "SL1BEG2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "FAN_BOUNCE6" + ], + [ + "B_TERM_UTURN_INT_SE6C3", + "NE6D0" + ], + [ + "B_TERM_UTURN_INT_SE6A0", + "NE6B3" + ], + [ + "B_TERM_UTURN_INT_SE6A2", + "NE6B1" + ], + [ + "B_TERM_UTURN_INT_SS6E3", + "SS6E3" + ], + [ + "B_TERM_UTURN_INT_SS2A0", + "SS2A0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG2", + "SS2BEG2" + ], + [ + "B_TERM_UTURN_INT_ER1BEG0", + "ER1BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG3", + "NR1END0" + ], + [ + "B_TERM_UTURN_INT_SW6A3", + "SW6A3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG3", + "NW2A0" + ], + [ + "B_TERM_UTURN_INT_SS6C1", + "NN6D2" + ], + [ + "B_TERM_UTURN_INT_SE6C0", + "NE6D3" + ], + [ + "B_TERM_UTURN_INT_SW6C0", + "NW6D3" + ], + [ + "B_TERM_UTURN_INT_SW6B2", + "SW6B2" + ], + [ + "B_TERM_UTURN_INT_SS6C1", + "SS6C1" + ], + [ + "B_TERM_UTURN_INT_SS6D3", + "SS6D3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG1", + "SE2BEG1" + ], + [ + "B_TERM_UTURN_INT_SS6B1", + "SS6B1" + ], + [ + "B_TERM_UTURN_INT_SW6D0", + "NW6E3" + ], + [ + "B_TERM_UTURN_INT_SS6B0", + "SS6B0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG1", + "NE2A2" + ], + [ + "B_TERM_UTURN_INT_LV_L2", + "LV_L17" + ], + [ + "B_TERM_UTURN_INT_LV_L18", + "LV_L1" + ], + [ + "B_TERM_UTURN_INT_SW6D2", + "NW6E1" + ], + [ + "B_TERM_UTURN_INT_SS6BEG3", + "SS6BEG3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG0", + "SE2BEG0" + ], + [ + "B_TERM_UTURN_INT_SW6B3", + "SW6B3" + ], + [ + "B_TERM_UTURN_INT_SW6C1", + "SW6C1" + ], + [ + "B_TERM_UTURN_INT_SE6C1", + "NE6D2" + ], + [ + "B_TERM_UTURN_INT_SW6A2", + "NW6B1" + ], + [ + "B_TERM_UTURN_INT_SE6D3", + "SE6D3" + ], + [ + "B_TERM_UTURN_INT_LVB_L4", + "LVB_L8" + ], + [ + "B_TERM_UTURN_INT_SW6D2", + "SW6D2" + ], + [ + "B_TERM_UTURN_INT_LVB_L5", + "LVB_L7" + ], + [ + "B_TERM_UTURN_INT_LV_L4", + "LV_L4" + ], + [ + "B_TERM_UTURN_INT_SR1BEG2", + "NL1END1" + ], + [ + "B_TERM_UTURN_INT_SS2A3", + "SS2A3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG2", + "SS6BEG2" + ], + [ + "B_TERM_UTURN_INT_SS6E2", + "SS6E2" + ], + [ + "B_TERM_UTURN_INT_SW6C1", + "NW6D2" + ], + [ + "B_TERM_UTURN_INT_SS6E3", + "NN6END0" + ], + [ + "B_TERM_UTURN_INT_SS6E1", + "SS6E1" + ], + [ + "B_TERM_UTURN_INT_SE6D0", + "SE6D0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG2", + "SR1BEG2" + ], + [ + "B_TERM_UTURN_INT_LVB_L2", + "LVB_L3" + ], + [ + "B_TERM_UTURN_INT_SS6B2", + "SS6B2" + ], + [ + "B_TERM_UTURN_INT_SS6A1", + "SS6A1" + ], + [ + "B_TERM_UTURN_INT_WR1BEG0", + "WL1BEG_N3" + ], + [ + "B_TERM_UTURN_INT_SW6D1", + "SW6D1" + ], + [ + "B_TERM_UTURN_INT_SS6B0", + "NN6C3" + ], + [ + "B_TERM_UTURN_INT_SS6C0", + "SS6C0" + ], + [ + "B_TERM_UTURN_INT_LV_L3", + "LV_L16" + ], + [ + "B_TERM_UTURN_INT_SS2BEG3", + "SS2BEG3" + ], + [ + "B_TERM_UTURN_INT_SS2BEG1", + "SS2BEG1" + ], + [ + "B_TERM_UTURN_INT_SW6C2", + "SW6C2" + ], + [ + "B_TERM_UTURN_INT_LV_L8", + "LV_L11" + ], + [ + "B_TERM_UTURN_INT_SW2BEG0", + "SW2BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG1", + "SL1BEG1" + ], + [ + "B_TERM_UTURN_INT_SS6D3", + "NN6E0" + ], + [ + "B_TERM_UTURN_INT_LVB_L4", + "LVB_L5" + ], + [ + "B_TERM_UTURN_INT_SS6A0", + "NN6B3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG1", + "SW2BEG1" + ], + [ + "B_TERM_UTURN_INT_SW6A1", + "NW6B2" + ], + [ + "B_TERM_UTURN_INT_SS6C3", + "NN6D0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG2", + "NE2A1" + ], + [ + "B_TERM_UTURN_INT_LVB_L0", + "LVB_L12" + ], + [ + "B_TERM_UTURN_INT_SS6A0", + "SS6A0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG1", + "SR1BEG1" + ], + [ + "HCLK_LEAF_CLK_B_TOPL1", + "GCLK_L_B7" + ], + [ + "B_TERM_UTURN_INT_SW6C2", + "NW6D1" + ], + [ + "B_TERM_UTURN_INT_SW6C3", + "SW6C3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG1", + "SS6BEG1" + ], + [ + "B_TERM_UTURN_INT_SR1BEG3", + "SR1BEG3" + ], + [ + "B_TERM_UTURN_INT_LV_L9", + "LV_L9" + ], + [ + "B_TERM_UTURN_INT_SE6D3", + "NE6E0" + ], + [ + "B_TERM_UTURN_INT_SE6B3", + "SE6B3" + ], + [ + "B_TERM_UTURN_INT_WR1END0", + "WL1END_N1_3" + ], + [ + "B_TERM_UTURN_INT_SW6D0", + "SW6D0" + ], + [ + "HCLK_LEAF_CLK_B_TOPL5", + "GCLK_L_B11" + ], + [ + "B_TERM_UTURN_INT_SW6A2", + "SW6A2" + ], + [ + "B_TERM_UTURN_INT_SW2BEG0", + "NW2A3" + ], + [ + "B_TERM_UTURN_INT_LV_L4", + "LV_L15" + ], + [ + "B_TERM_UTURN_INT_SR1BEG3", + "NL1END0" + ], + [ + "B_TERM_UTURN_INT_SS6E1", + "NN6END2" + ], + [ + "B_TERM_UTURN_INT_SS2A0", + "NN2END3" + ], + [ + "B_TERM_UTURN_INT_SW6C3", + "NW6D0" + ], + [ + "B_TERM_UTURN_INT_SE6B2", + "NE6C1" + ], + [ + "B_TERM_UTURN_INT_SW2BEG1", + "NW2A2" + ], + [ + "B_TERM_UTURN_INT_SS6C0", + "NN6D3" + ], + [ + "HCLK_LEAF_CLK_B_TOPL3", + "GCLK_L_B9" + ], + [ + "B_TERM_UTURN_INT_SS6A1", + "NN6B2" + ], + [ + "B_TERM_UTURN_INT_SS6A2", + "SS6A2" + ], + [ + "B_TERM_UTURN_INT_SS6E2", + "NN6END1" + ], + [ + "B_TERM_UTURN_INT_SS6D2", + "SS6D2" + ], + [ + "B_TERM_UTURN_INT_SS6B2", + "NN6C1" + ], + [ + "B_TERM_UTURN_INT_LVB_L5", + "LVB_L6" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "BYP_BOUNCE_N3_7" + ], + [ + "B_TERM_UTURN_INT_SW6D1", + "NW6E2" + ], + [ + "B_TERM_UTURN_INT_ER1END_N3_3", + "EL1END0" + ], + [ + "B_TERM_UTURN_INT_SS2A3", + "NN2END0" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "BYP_BOUNCE_N3_6" + ], + [ + "B_TERM_UTURN_INT_SS6D2", + "NN6E1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG2", + "NN2A1" + ], + [ + "B_TERM_UTURN_INT_LV_L5", + "LV_L14" + ], + [ + "B_TERM_UTURN_INT_SE6B1", + "SE6B1" + ], + [ + "B_TERM_UTURN_INT_SW2BEG3", + "SW2BEG3" + ], + [ + "B_TERM_UTURN_INT_SE6C1", + "SE6C1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "BYP_BOUNCE_N3_2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "BYP_BOUNCE_N3_3" + ], + [ + "B_TERM_UTURN_INT_SS6D0", + "SS6D0" + ], + [ + "B_TERM_UTURN_INT_SW2BEG2", + "NW2A1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "FAN_BOUNCE2" + ], + [ + "B_TERM_UTURN_INT_SS6BEG2", + "NN6A1" + ], + [ + "B_TERM_UTURN_INT_SS2A1", + "NN2END2" + ], + [ + "B_TERM_UTURN_INT_SE6B3", + "NE6C0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG3", + "NE2A0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG3", + "NN2A0" + ], + [ + "B_TERM_UTURN_INT_SW6B2", + "NW6C1" + ], + [ + "B_TERM_UTURN_INT_SW6A0", + "SW6A0" + ], + [ + "B_TERM_UTURN_INT_LV_L8", + "LV_L8" + ], + [ + "B_TERM_UTURN_INT_SL1BEG2", + "NR1END1" + ], + [ + "B_TERM_UTURN_INT_SE2BEG0", + "NE2A3" + ], + [ + "B_TERM_UTURN_INT_SW6B1", + "SW6B1" + ], + [ + "B_TERM_UTURN_INT_SS2A2", + "SS2A2" + ], + [ + "B_TERM_UTURN_INT_LVB_L1", + "LVB_L2" + ], + [ + "B_TERM_UTURN_INT_SS6B3", + "SS6B3" + ], + [ + "B_TERM_UTURN_INT_SE6D2", + "SE6D2" + ], + [ + "B_TERM_UTURN_INT_SW6END_N0_3", + "SW6END_N0_3" + ], + [ + "B_TERM_UTURN_INT_SE6A3", + "SE6A3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG2", + "SW2BEG2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG0", + "NR1END3" + ], + [ + "B_TERM_UTURN_INT_LVB_L3", + "LVB_L4" + ], + [ + "B_TERM_UTURN_INT_SE6C2", + "NE6D1" + ], + [ + "B_TERM_UTURN_INT_WR1BEG0", + "WR1BEG0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG0", + "NN2A3" + ], + [ + "B_TERM_UTURN_INT_SE6C0", + "SE6C0" + ], + [ + "B_TERM_UTURN_INT_LV_L7", + "LV_L12" + ], + [ + "B_TERM_UTURN_INT_SW6END_N0_3", + "NW6END0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG3", + "SL1BEG3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG3", + "SE2BEG3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG1", + "NN6A2" + ], + [ + "B_TERM_UTURN_INT_SE2BEG2", + "SE2BEG2" + ], + [ + "B_TERM_UTURN_INT_SE6A1", + "SE6A1" + ], + [ + "B_TERM_UTURN_INT_SE6B1", + "NE6C2" + ], + [ + "B_TERM_UTURN_INT_SW6D3", + "SW6D3" + ], + [ + "B_TERM_UTURN_INT_SE6A3", + "NE6B0" + ], + [ + "B_TERM_UTURN_INT_SW6A1", + "SW6A1" + ], + [ + "B_TERM_UTURN_INT_SS2A1", + "SS2A1" + ], + [ + "HCLK_LEAF_CLK_B_TOPL2", + "GCLK_L_B8" + ], + [ + "B_TERM_UTURN_INT_LVB_L3", + "LVB_L9" + ] + ], + "tile_types": [ + "HCLK_L_BOT_UTURN", + "INT_L" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "LV_L15", + "LV_L16" + ], + [ + "NW6D0", + "NW6E0" + ], + [ + "LVB_L3", + "LVB_L4" + ], + [ + "NW6D2", + "NW6E2" + ], + [ + "SW2A2", + "SW2BEG2" + ], + [ + "LVB_L2", + "LVB_L3" + ], + [ + "NN6E2", + "NN6END2" + ], + [ + "LV_L16", + "LV_L17" + ], + [ + "NW6A1", + "NW6B1" + ], + [ + "NW6B3", + "NW6C3" + ], + [ + "LVB_L6", + "LVB_L7" + ], + [ + "NE6C0", + "NE6D0" + ], + [ + "NE6A1", + "NE6B1" + ], + [ + "NN6A1", + "NN6B1" + ], + [ + "NN6E1", + "NN6END1" + ], + [ + "LV_L1", + "LV_L2" + ], + [ + "NN2A2", + "NN2END2" + ], + [ + "SE2A3", + "SE2BEG3" + ], + [ + "NE6B2", + "NE6C2" + ], + [ + "NL1BEG1", + "NL1END1" + ], + [ + "NE6D0", + "NE6E0" + ], + [ + "NN6C1", + "NN6D1" + ], + [ + "SS6A3", + "SS6BEG3" + ], + [ + "NL1BEG0", + "NL1END0" + ], + [ + "NN6D2", + "NN6E2" + ], + [ + "LV_L10", + "LV_L11" + ], + [ + "SE2A1", + "SE2BEG1" + ], + [ + "NE6B3", + "NE6C3" + ], + [ + "NL1BEG2", + "NL1END2" + ], + [ + "LVB_L10", + "LVB_L11" + ], + [ + "SE2A2", + "SE2BEG2" + ], + [ + "NN6D1", + "NN6E1" + ], + [ + "NW6A3", + "NW6B3" + ], + [ + "NE6C2", + "NE6D2" + ], + [ + "NN6B3", + "NN6C3" + ], + [ + "LV_L3", + "LV_L4" + ], + [ + "NW6A2", + "NW6B2" + ], + [ + "LVB_L8", + "LVB_L9" + ], + [ + "SS2A0", + "SS2BEG0" + ], + [ + "SW2A1", + "SW2BEG1" + ], + [ + "NW6C1", + "NW6D1" + ], + [ + "BYP_BOUNCE2", + "BYP_BOUNCE_N3_2" + ], + [ + "LVB_L0", + "LVB_L1" + ], + [ + "NN6A0", + "NN6B0" + ], + [ + "NE6A0", + "NE6B0" + ], + [ + "NN6E3", + "NN6END3" + ], + [ + "NN2A0", + "NN2END0" + ], + [ + "NE6A2", + "NE6B2" + ], + [ + "SS2A1", + "SS2BEG1" + ], + [ + "SS2A2", + "SS2BEG2" + ], + [ + "BYP_BOUNCE3", + "BYP_BOUNCE_N3_3" + ], + [ + "NE6D2", + "NE6E2" + ], + [ + "NR1BEG2", + "NR1END2" + ], + [ + "NN6E0", + "NN6END0" + ], + [ + "NN6B0", + "NN6C0" + ], + [ + "NW6A0", + "NW6B0" + ], + [ + "NE6B1", + "NE6C1" + ], + [ + "NN2A3", + "NN2END3" + ], + [ + "BYP_BOUNCE7", + "BYP_BOUNCE_N3_7" + ], + [ + "NW6C3", + "NW6D3" + ], + [ + "LVB_L11", + "LVB_L12" + ], + [ + "LV_L13", + "LV_L14" + ], + [ + "SS2A3", + "SS2BEG3" + ], + [ + "ER1END3", + "ER1END_N3_3" + ], + [ + "WW2END3", + "WW2END_N0_3" + ], + [ + "NW6D1", + "NW6E1" + ], + [ + "LV_L6", + "LV_L7" + ], + [ + "SW2A3", + "SW2BEG3" + ], + [ + "SR1END3", + "SR1END_N3_3" + ], + [ + "LV_L11", + "LV_L12" + ], + [ + "NN6D0", + "NN6E0" + ], + [ + "WL1BEG3", + "WL1BEG_N3" + ], + [ + "NE6D3", + "NE6E3" + ], + [ + "SW2A0", + "SW2BEG0" + ], + [ + "NN2A1", + "NN2END1" + ], + [ + "NN6A2", + "NN6B2" + ], + [ + "SS6END3", + "SS6END_N0_3" + ], + [ + "NN6A3", + "NN6B3" + ], + [ + "NN6C2", + "NN6D2" + ], + [ + "WL1END3", + "WL1END_N1_3" + ], + [ + "NW6D3", + "NW6E3" + ], + [ + "NW6B0", + "NW6C0" + ], + [ + "LV_L0", + "LV_L1" + ], + [ + "SE2A0", + "SE2BEG0" + ], + [ + "NN6B1", + "NN6C1" + ], + [ + "NR1BEG1", + "NR1END1" + ], + [ + "LV_L8", + "LV_L9" + ], + [ + "NE6A3", + "NE6B3" + ], + [ + "NW6C2", + "NW6D2" + ], + [ + "EL1BEG3", + "EL1BEG_N3" + ], + [ + "SS6A2", + "SS6BEG2" + ], + [ + "LV_L2", + "LV_L3" + ], + [ + "NW6B2", + "NW6C2" + ], + [ + "NR1BEG3", + "NR1END3" + ], + [ + "NE6C3", + "NE6D3" + ], + [ + "LV_L14", + "LV_L15" + ], + [ + "LV_L17", + "LV_L18" + ], + [ + "BYP_BOUNCE6", + "BYP_BOUNCE_N3_6" + ], + [ + "NE6C1", + "NE6D1" + ], + [ + "NN6C0", + "NN6D0" + ], + [ + "LV_L5", + "LV_L6" + ], + [ + "NN6B2", + "NN6C2" + ], + [ + "NE6D1", + "NE6E1" + ], + [ + "NW6B1", + "NW6C1" + ], + [ + "LV_L7", + "LV_L8" + ], + [ + "LVB_L4", + "LVB_L5" + ], + [ + "NR1BEG0", + "NR1END0" + ], + [ + "SS6A1", + "SS6BEG1" + ], + [ + "LV_L4", + "LV_L5" + ], + [ + "SS2END3", + "SS2END_N0_3" + ], + [ + "SW2END3", + "SW2END_N0_3" + ], + [ + "NW6C0", + "NW6D0" + ], + [ + "NN6D3", + "NN6E3" + ], + [ + "LV_L12", + "LV_L13" + ], + [ + "NN6C3", + "NN6D3" + ], + [ + "LVB_L7", + "LVB_L8" + ], + [ + "SS6A0", + "SS6BEG0" + ], + [ + "SW6END3", + "SW6END_N0_3" + ], + [ + "NE6B0", + "NE6C0" + ], + [ + "LVB_L5", + "LVB_L6" + ], + [ + "LVB_L1", + "LVB_L2" + ] + ], + "tile_types": [ + "INT_L", + "INT_L" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "CLK_HROW_SE2A0_2", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_WW2A0_2", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4C1_2", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_EE4BEG0_2", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_IMUX22_2", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_SE2A1_2", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_IMUX16_2", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_NE4BEG3_2", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_IMUX2_2", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_WW4END3_2", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_SW2A1_2", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_IMUX39_2", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_EE4A2_2", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_WW4B0_2", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_IMUX10_2", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_EE4C2_2", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_NW2A2_2", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_IMUX21_2", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_LH8_2", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_IMUX31_2", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_EE4B1_2", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_WL1END2_2", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_SE4BEG1_2", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_IMUX19_2", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_NW4A3_2", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WW2END2_2", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_IMUX25_2", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_IMUX24_2", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_WW4END1_2", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_LH12_2", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_EE2BEG3_2", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_IMUX35_2", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_IMUX23_2", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_IMUX8_2", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_IMUX26_2", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_NE4C0_2", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_WW4B2_2", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_SE4C2_2", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_SW4END3_2", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_FAN7_2", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_IMUX5_2", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_IMUX4_2", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_IMUX20_2", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_NW4END3_2", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_LH10_2", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_IMUX15_2", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_SW4END1_2", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_WW2A3_2", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_BYP4_2", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_FAN2_2", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_LH1_2", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_NE2A3_2", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_EE4BEG2_2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_BYP0_2", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_WW4B3_2", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_WR1END2_2", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_ER1BEG3_2", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_BYP5_2", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_SW4END0_2", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_SE4C0_2", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_NE4BEG2_2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_LH2_2", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_IMUX13_2", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_WW4END2_2", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_NW4END0_2", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_NW4A1_2", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_WW4C3_2", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_MONITOR_N_2", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_HROW_IMUX45_2", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_BYP1_2", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_NE2A1_2", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_ER1BEG1_2", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_SE2A2_2", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_EL1BEG1_2", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_NW2A0_2", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_SW2A2_2", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_IMUX44_2", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_EE4A1_2", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_IMUX0_2", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_NE4BEG1_2", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_IMUX27_2", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_IMUX43_2", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_WW4B1_2", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_NE2A2_2", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_SE4BEG2_2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_WW4A0_2", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_WW2END3_2", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_IMUX28_2", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_BYP7_2", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_WW4A3_2", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_SW4END2_2", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_WW2END0_2", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_EE2BEG2_2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_WW4A1_2", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_NW4A2_2", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_IMUX29_2", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_BYP3_2", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_IMUX46_2", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_LH6_2", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_NW2A3_2", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_EE2A1_2", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_IMUX11_2", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_LH9_2", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_EE4BEG1_2", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_WR1END3_2", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_WL1END0_2", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_CLK0_2", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_IMUX32_2", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_FAN5_2", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_WR1END1_2", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_WW4C0_2", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_IMUX37_2", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_SE4C3_2", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_IMUX33_2", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_LH3_2", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_WW2A1_2", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_NW4END1_2", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_IMUX12_2", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_SE4C1_2", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_CTRL0_2", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_FAN1_2", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_EL1BEG0_2", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_NE4C1_2", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_BYP6_2", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_IMUX41_2", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_NE4BEG0_2", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_FAN6_2", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_SW2A3_2", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_IMUX17_2", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_MONITOR_P_2", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_HROW_EL1BEG3_2", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_BYP2_2", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_SW4A1_2", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_WW4C1_2", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_NW2A1_2", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_LH11_2", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_NE4C3_2", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_IMUX1_2", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_SW4A3_2", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_IMUX36_2", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_EE2A2_2", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_FAN3_2", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_SW2A0_2", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE2A0_2", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_SW4A0_2", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_WW4END0_2", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_LH7_2", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_SE4BEG0_2", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_EE2A3_2", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_IMUX47_2", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_SE4BEG3_2", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_WW2END1_2", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_IMUX30_2", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_EE4B3_2", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_EE2BEG0_2", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_IMUX3_2", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_CTRL1_2", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_EE4A0_2", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_IMUX7_2", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_NW4END2_2", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_SE2A3_2", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_IMUX40_2", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_FAN4_2", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_EE2BEG1_2", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_IMUX14_2", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_NE2A0_2", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_IMUX6_2", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_EE4BEG3_2", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_IMUX18_2", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_WR1END0_2", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_ER1BEG0_2", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_WW4A2_2", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_SW4A2_2", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_WW2A2_2", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_EE4C0_2", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_CLK1_2", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_EE4B2_2", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_EL1BEG2_2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_WW4C2_2", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_EE4A3_2", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_EE4B0_2", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_FAN0_2", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_IMUX42_2", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_IMUX9_2", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_ER1BEG2_2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_IMUX34_2", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_WL1END3_2", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_WL1END1_2", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_NE4C2_2", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_LH4_2", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_NW4A0_2", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_LH5_2", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_EE4C3_2", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_IMUX38_2", + "INT_INTERFACE_IMUX38" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -7 + ], + "wire_pairs": [ + [ + "CMT_TOP_EE4C0_11", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EL1BEG1_11", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG0_11", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH7_11", + "VBRK_LH7" + ], + [ + "CMT_TOP_ER1BEG1_11", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2A0_11", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH3_11", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C1_11", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH2_11", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW2A1_11", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NE2A3_11", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_ER1BEG2_11", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NW4END2_11", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE4BEG3_11", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C3_11", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE2A2_11", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_SW2A0_11", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW4A1_11", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_LH9_11", + "VBRK_LH9" + ], + [ + "CMT_TOP_SE4C3_11", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WR1END0_11", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_11", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EL1BEG2_11", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_NE4BEG2_11", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_11", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4C2_11", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4C2_11", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW4C3_11", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_LH4_11", + "VBRK_LH4" + ], + [ + "CMT_TOP_NE4C2_11", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EE4BEG0_11", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NE2A0_11", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NW4A1_11", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG1_11", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4C1_11", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_EE2A1_11", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END1_11", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SE4C2_11", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A0_11", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE4B0_11", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_11", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW4B0_11", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C0_11", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4BEG2_11", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_LH11_11", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE2BEG3_11", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END2_11", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_11", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4A2_11", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EE4BEG3_11", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_NW4END3_11", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_LH1_11", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE4C0_11", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SW4END3_11", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SW4END1_11", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_11", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END1_11", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW2A3_11", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH8_11", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A0_11", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_11", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW4B3_11", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW4A2_11", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4B2_11", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE2A0_11", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WW2END3_11", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EE4A3_11", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SE4C1_11", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_ER1BEG0_11", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_NW4END1_11", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A3_11", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4A2_11", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4C3_11", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW2A0_11", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NE2A1_11", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW4A3_11", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NW2A3_11", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NE4BEG3_11", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_WW2A2_11", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG0_11", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW2END0_11", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2A3_11", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4A2_11", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG2_11", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW2A1_11", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SW4END2_11", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG0_11", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_EE4C1_11", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG1_11", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG1_11", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2BEG2_11", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SW2A1_11", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE2A2_11", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WR1END1_11", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW2A3_11", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW2A0_11", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW4B1_11", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C0_11", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4BEG1_11", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH12_11", + "VBRK_LH12" + ], + [ + "CMT_TOP_WW4END2_11", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW2A2_11", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_EE4A1_11", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH5_11", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4A0_11", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_SE2A1_11", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END2_11", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WL1END3_11", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_ER1BEG3_11", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WW4B2_11", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WL1END0_11", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW4END0_11", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_11", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A3_11", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4END3_11", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_11", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4A0_11", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A1_11", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH10_11", + "VBRK_LH10" + ], + [ + "CMT_TOP_SW4END0_11", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW4END1_11", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE2A2_11", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW2A2_11", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG0_11", + "VBRK_EL1BEG0" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "CLK_HROW_LH10_2", + "VBRK_LH10" + ], + [ + "CLK_HROW_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_LH11_2", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH7_2", + "VBRK_LH7" + ], + [ + "CLK_HROW_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_LH1_2", + "VBRK_LH1" + ], + [ + "CLK_HROW_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_LH8_2", + "VBRK_LH8" + ], + [ + "CLK_HROW_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_LH12_2", + "VBRK_LH12" + ], + [ + "CLK_HROW_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_LH4_2", + "VBRK_LH4" + ], + [ + "CLK_HROW_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_LH5_2", + "VBRK_LH5" + ], + [ + "CLK_HROW_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_NW2A2_2", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_LH9_2", + "VBRK_LH9" + ], + [ + "CLK_HROW_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_LH2_2", + "VBRK_LH2" + ], + [ + "CLK_HROW_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_LH3_2", + "VBRK_LH3" + ], + [ + "CLK_HROW_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_LH6_2", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE4B3_2", + "VBRK_EE4B3" + ] + ], + "tile_types": [ + "CLK_BUFG_BOT_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX23_10", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_BYP6_10", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_CLK0_10", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_LOGIC_OUTS_B19_10", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX7_10", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX12_10", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX28_10", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX18_10", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_FAN0_10", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_FAN6_10", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX31_10", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B8_10", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_BYP2_10", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX36_10", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX42_10", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX45_10", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX22_10", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B2_10", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_LOGIC_OUTS_B0_10", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX21_10", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX14_10", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX9_10", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX3_10", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_LOGIC_OUTS_B17_10", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX33_10", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_LOGIC_OUTS_B10_10", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX17_10", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_LOGIC_OUTS_B12_10", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX15_10", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX24_10", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B7_10", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_IMUX44_10", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_FAN3_10", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_BYP3_10", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX8_10", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_BYP7_10", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B23_10", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX38_10", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX19_10", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_BYP1_10", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX29_10", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX10_10", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_FAN7_10", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B16_10", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX46_10", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_LOGIC_OUTS_B15_10", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX0_10", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX11_10", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX4_10", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_BYP0_10", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX26_10", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX40_10", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_FAN2_10", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX43_10", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_CTRL0_10", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX5_10", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX41_10", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX13_10", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_FAN5_10", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_FAN4_10", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_LOGIC_OUTS_B18_10", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX27_10", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_BYP4_10", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_CTRL1_10", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX1_10", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX30_10", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_LOGIC_OUTS_B4_10", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B20_10", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX20_10", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX47_10", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX2_10", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_LOGIC_OUTS_B9_10", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_LOGIC_OUTS_B5_10", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_FAN1_10", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX35_10", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_CLK1_10", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX16_10", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_LOGIC_OUTS_B14_10", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_LOGIC_OUTS_B1_10", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX37_10", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_LOGIC_OUTS_B13_10", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B22_10", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX32_10", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX25_10", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_BYP5_10", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B3_10", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX34_10", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_LOGIC_OUTS_B6_10", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX6_10", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX39_10", + "VBRK_EXT_IMUX39" + ] + ], + "tile_types": [ + "GTX_CHANNEL_0", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + -6 + ], + "wire_pairs": [ + [ + "CMT_TOP_SW4END0_14", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4C0_14", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4C3_14", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE2BEG3_14", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_EE2A0_14", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_WW4B2_14", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_SE4C3_14", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH12_14", + "VBRK_LH12" + ], + [ + "CMT_TOP_WW4END2_14", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4B0_14", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C1_14", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NE4BEG3_14", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SE4C2_14", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_SW2A1_14", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4C2_14", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE4BEG1_14", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4A3_14", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4A3_14", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_ER1BEG0_14", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_ER1BEG2_14", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SE4C1_14", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A3_14", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4C3_14", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_EE4BEG3_14", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW4A1_14", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW4A0_14", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4END0_14", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE2A1_14", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C2_14", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WR1END2_14", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END3_14", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WW4C0_14", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NE4BEG2_14", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A0_14", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END1_14", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4B1_14", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A2_14", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE2BEG2_14", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH6_14", + "VBRK_LH6" + ], + [ + "CMT_TOP_NE2A0_14", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SW4A1_14", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SW2A3_14", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4END3_14", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_WW4B0_14", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE2BEG1_14", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_NE4C2_14", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NE4BEG1_14", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG1_14", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH10_14", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4C1_14", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG0_14", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WL1END1_14", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_NE2A3_14", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW4B3_14", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW2A0_14", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_EE2A2_14", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EL1BEG0_14", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_EE4C3_14", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4A2_14", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4A2_14", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_WW2A2_14", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NE4BEG0_14", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_EE4A1_14", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WL1END3_14", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_EE2BEG0_14", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW2A3_14", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SW4END1_14", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4A3_14", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_NW4A3_14", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NW4END2_14", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE2A2_14", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_SE2A1_14", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4END1_14", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SW4END2_14", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE4B2_14", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE4BEG0_14", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_EL1BEG2_14", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4B1_14", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_NW4A1_14", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WR1END0_14", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4A0_14", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NW2A3_14", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_LH4_14", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW2A1_14", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WR1END1_14", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EL1BEG3_14", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SE2A0_14", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_LH2_14", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4B3_14", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_WW2A0_14", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH9_14", + "VBRK_LH9" + ], + [ + "CMT_TOP_ER1BEG3_14", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH8_14", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW2END1_14", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW2END0_14", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_ER1BEG1_14", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SE4BEG3_14", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_SW2A0_14", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NW4A2_14", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_WW4END3_14", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE2A1_14", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_SW4A2_14", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_LH5_14", + "VBRK_LH5" + ], + [ + "CMT_TOP_LH3_14", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C0_14", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_NE4C1_14", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_SE4BEG2_14", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SE4BEG1_14", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH1_14", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW4END0_14", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE2A2_14", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END2_14", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4BEG2_14", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WL1END0_14", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4C0_14", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NW2A2_14", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A1_14", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH7_14", + "VBRK_LH7" + ], + [ + "CMT_TOP_WR1END3_14", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SW4END3_14", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE2A3_14", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW4A0_14", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_LH11_14", + "VBRK_LH11" + ], + [ + "CMT_TOP_WL1END2_14", + "VBRK_WL1END2" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "CMT_TOP_EE2BEG2_9", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NE4C0_9", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EE2A0_9", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_9", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SE4BEG2_9", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_NE2A2_9", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW2A2_9", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_LH6_9", + "VBRK_LH6" + ], + [ + "CMT_TOP_EE4B1_9", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW4A1_9", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SW4A2_9", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WR1END2_9", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH8_9", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A3_9", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4BEG3_9", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WW2END2_9", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2A1_9", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4A0_9", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4C1_9", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NE4C3_9", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW2A0_9", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_9", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2END0_9", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4C2_9", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A3_9", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_ER1BEG0_9", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EL1BEG1_9", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG0_9", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH3_9", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END2_9", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH2_9", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW4A3_9", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW2A2_9", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4A2_9", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END3_9", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE2A3_9", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4BEG2_9", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4END0_9", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SW4A0_9", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4C1_9", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A1_9", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4END2_9", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EL1BEG3_9", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_9", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW2A0_9", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4B0_9", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE4C0_9", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE4B3_9", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW4A1_9", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_LH4_9", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW4C1_9", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_EE2BEG1_9", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4A0_9", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4BEG0_9", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_9", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2A2_9", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EE4A1_9", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4END0_9", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW4B1_9", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4A3_9", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END3_9", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH11_9", + "VBRK_LH11" + ], + [ + "CMT_TOP_SW4END3_9", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_9", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END1_9", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_LH12_9", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C1_9", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE4C3_9", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_SE2A1_9", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE4A0_9", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_EE2BEG3_9", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END1_9", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A1_9", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE2BEG0_9", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE2A2_9", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END3_9", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_ER1BEG3_9", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NE2A3_9", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW2A3_9", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_9", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH9_9", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4B0_9", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A0_9", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NE4BEG2_9", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A2_9", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_WW4C0_9", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SW2A1_9", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH5_9", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END0_9", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NE4BEG1_9", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_9", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A2_9", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4BEG1_9", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C0_9", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_WW4END2_9", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_WW4END1_9", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NW2A0_9", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4C2_9", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_WW4B3_9", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WR1END0_9", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW2A3_9", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW2A2_9", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_EE4BEG3_9", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C2_9", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_SE4BEG1_9", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_9", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_NE2A0_9", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4B2_9", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WL1END2_9", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG0_9", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG2_9", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4C3_9", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4A1_9", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH1_9", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW4END0_9", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_EE4A3_9", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_LH10_9", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW2END1_9", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WL1END3_9", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_EE2A1_9", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4C3_9", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WR1END3_9", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SW2A3_9", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH7_9", + "VBRK_LH7" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW4C0_6", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4END2_6", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW2A3_6", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4BEG0_6", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_6", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_6", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A3_6", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4A1_6", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4B0_6", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SW4A3_6", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_NE4BEG2_6", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE4B0_6", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE4C1_6", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A1_6", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END1_6", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_6", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_6", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_6", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C1_6", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW4A1_6", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_ER1BEG0_6", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_6", + "VBRK_LH1" + ], + [ + "CMT_TOP_EE4BEG2_6", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG2_6", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SE2A0_6", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WL1END2_6", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A1_6", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WR1END3_6", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NE2A2_6", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_LH4_6", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END1_6", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH8_6", + "VBRK_LH8" + ], + [ + "CMT_TOP_SE4BEG2_6", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4END2_6", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH6_6", + "VBRK_LH6" + ], + [ + "CMT_TOP_MONITOR_N_6", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_LH3_6", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C2_6", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NE2A3_6", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE4C3_6", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4A0_6", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C3_6", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_ER1BEG3_6", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_6", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WR1END2_6", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END0_6", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4C0_6", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SE4C0_6", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SE2A3_6", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_LH2_6", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW2END1_6", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW2END3_6", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE2A0_6", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NE4C0_6", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WW4C3_6", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END1_6", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4BEG3_6", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A1_6", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4B3_6", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4B1_6", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A1_6", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WL1END3_6", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH7_6", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW2A0_6", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A0_6", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NW2A1_6", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2BEG0_6", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_6", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE2BEG1_6", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4END3_6", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NW4END3_6", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4BEG1_6", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_6", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_SW4END2_6", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NW4A3_6", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4BEG0_6", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SW4A2_6", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4C1_6", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2A0_6", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4END0_6", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_ER1BEG2_6", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2A3_6", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW2A0_6", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_LH11_6", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH9_6", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2BEG3_6", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WW4A3_6", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4A0_6", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE2A0_6", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NW2A2_6", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_6", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C3_6", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4A1_6", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WR1END0_6", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4C2_6", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_MONITOR_P_6", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_EE4C1_6", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG3_6", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW4B3_6", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END2_6", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A2_6", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4B2_6", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW4A0_6", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW2A1_6", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH5_6", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4B1_6", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_NE4BEG1_6", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH10_6", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_6", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4A2_6", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG1_6", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE2A1_6", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C2_6", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END0_6", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SE4BEG0_6", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_6", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE4A2_6", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4END0_6", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4BEG3_6", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A3_6", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_6", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_6", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A2_6", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NW2A3_6", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_6", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE4C2_6", + "VBRK_SE4C2" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 4 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_4" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_4" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_4" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_4" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_4" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_4" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_4" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_4" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_4" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_4" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_4" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_4" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_4" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_4" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_4" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_4" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_4" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_4" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_4" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_4" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_4" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_4" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_4" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_4" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_4" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_4" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_4" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_4" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_4" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_4" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_4" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_4" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_4" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_4" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_4" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_4" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_4" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_4" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_4" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_4" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_4" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_4" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_4" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_4" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_4" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_4" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_4" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_4" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_4" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_4" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_4" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_4" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_4" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_4" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_4" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_4" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_4" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_4" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_4" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_4" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_4" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_4" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_4" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_4" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_4" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_4" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_4" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_4" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_4" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_4" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_4" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_4" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_4" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_4" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_4" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_4" + ], + [ + "INT_FEEDTHRU_2_MONITOR_N", + "MONITOR_HORIZ_VAUXN2" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_4" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_4" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_4" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_4" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_4" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_4" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_4" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_4" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_4" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_4" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_4" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_4" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_4" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_4" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_4" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_4" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_4" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_4" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_4" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_4" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_4" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_4" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_4" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_4" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_4" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_4" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_4" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_4" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_4" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_4" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_4" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_4" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_4" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_4" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_4" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_4" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_4" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_4" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_4" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_4" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_4" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_4" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_4" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_4" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_4" + ], + [ + "INT_FEEDTHRU_2_MONITOR_P", + "MONITOR_HORIZ_VAUXP2" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_4" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_4" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_4" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_MID_FUJI2" + ] + }, + { + "grid_deltas": [ + 1, + 3 + ], + "wire_pairs": [ + [ + "CLK_HROW_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_LH2_1", + "VBRK_LH2" + ], + [ + "CLK_HROW_LH4_1", + "VBRK_LH4" + ], + [ + "CLK_HROW_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_LH10_1", + "VBRK_LH10" + ], + [ + "CLK_HROW_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_LH3_1", + "VBRK_LH3" + ], + [ + "CLK_HROW_LH9_1", + "VBRK_LH9" + ], + [ + "CLK_HROW_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_LH7_1", + "VBRK_LH7" + ], + [ + "CLK_HROW_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_LH11_1", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH12_1", + "VBRK_LH12" + ], + [ + "CLK_HROW_LH8_1", + "VBRK_LH8" + ], + [ + "CLK_HROW_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_LH5_1", + "VBRK_LH5" + ], + [ + "CLK_HROW_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_LH1_1", + "VBRK_LH1" + ], + [ + "CLK_HROW_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_LH6_1", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_WW2END2_1", + "VBRK_WW2END2" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLBLL_L_CIN", + "CLBLL_L_COUT_N" + ], + [ + "CLBLL_LL_CIN", + "CLBLL_LL_COUT_N" + ] + ], + "tile_types": [ + "CLBLL_R", + "CLBLL_R" + ] + }, + { + "grid_deltas": [ + -1, + -8 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SE2A1_8", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_LH6_8", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_NE4BEG1_8", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WW4END3_8", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4END2_8", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_NE2A1_8", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NE4C2_8", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW4B1_8", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_NE4BEG0_8", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_WW4C3_8", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_LH9_8", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_WW4B3_8", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_EE4C1_8", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE4A1_8", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_WW4A3_8", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_ER1BEG3_8", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_LH11_8", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_NE4C3_8", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WW2A2_8", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4BEG2_8", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG3_8", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_SE4C1_8", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_EE2A3_8", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW2A0_8", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_SE4C3_8", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_SW4END1_8", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EE4BEG2_8", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_ER1BEG1_8", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SW2A0_8", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WW2END1_8", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_SW4END2_8", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_EE4C3_8", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_EE2BEG1_8", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_SW4A3_8", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_NW4A0_8", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_EE2BEG0_8", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_LH2_8", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NE2A3_8", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_WL1END2_8", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_LH7_8", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_EL1BEG0_8", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE2BEG3_8", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_WW2END3_8", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_EE4BEG1_8", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_NW4A3_8", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WW4END1_8", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_WW4B2_8", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_NW2A0_8", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_EE2A1_8", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_ER1BEG2_8", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_EE4A2_8", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SE4C0_8", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_EE4B2_8", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_ER1BEG0_8", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NW4END3_8", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_EE2A2_8", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_NW2A2_8", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_LH3_8", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_WW2A3_8", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WR1END0_8", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH10_8", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_SE4BEG2_8", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW4C1_8", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SW4A2_8", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NW2A1_8", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C0_8", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WL1END0_8", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_WW4A1_8", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_WL1END3_8", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4A0_8", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE2BEG2_8", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NW4END2_8", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4A2_8", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_NE2A0_8", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_WW4C0_8", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_LH1_8", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_EE2A0_8", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_SW4END0_8", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WW4C2_8", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NW4END1_8", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_SE2A3_8", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_WW2END0_8", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WW4A0_8", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_NE4BEG3_8", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_NW4A2_8", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WW2END2_8", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_EE4B1_8", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NE2A2_8", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EL1BEG2_8", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_SW2A3_8", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NE4C1_8", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_SW2A2_8", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_NW4END0_8", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_NW4A1_8", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_LH5_8", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE4B3_8", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SE4BEG0_8", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_LH12_8", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW4B0_8", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_WL1END1_8", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_SW4END3_8", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_SW4A0_8", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WR1END1_8", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WR1END2_8", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_SE2A2_8", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4C2_8", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW2A3_8", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_WW2A1_8", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_NE4C0_8", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_LH4_8", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SE4BEG3_8", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_SW4A1_8", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_SE2A0_8", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SW2A1_8", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_SE4BEG1_8", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_EE4BEG0_8", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE4A3_8", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EL1BEG1_8", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SE4C2_8", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_EE4BEG3_8", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_LH8_8", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW4END0_8", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WR1END3_8", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE4B0_8", + "INT_FEEDTHRU_2_EE4B0" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLBLL_EE4B0", + "EE4B0" + ], + [ + "CLBLL_EE2BEG1", + "EE2BEG1" + ], + [ + "CLBLL_LOGIC_OUTS6", + "LOGIC_OUTS6" + ], + [ + "CLBLL_LOGIC_OUTS14", + "LOGIC_OUTS14" + ], + [ + "CLBLL_IMUX45", + "IMUX45" + ], + [ + "CLBLL_FAN0", + "FAN0" + ], + [ + "CLBLL_WL1END1", + "WL1END1" + ], + [ + "CLBLL_WW2END1", + "WW2END1" + ], + [ + "CLBLL_LH5", + "LH5" + ], + [ + "CLBLL_NE4BEG3", + "NE6BEG3" + ], + [ + "CLBLL_NE4BEG1", + "NE6BEG1" + ], + [ + "CLBLL_EL1BEG0", + "EL1BEG0" + ], + [ + "CLBLL_WL1END2", + "WL1END2" + ], + [ + "CLBLL_EE4C1", + "EE4C1" + ], + [ + "CLBLL_EL1BEG1", + "EL1BEG1" + ], + [ + "CLBLL_LOGIC_OUTS4", + "LOGIC_OUTS4" + ], + [ + "CLBLL_SW4A3", + "SW6A3" + ], + [ + "CLBLL_LH4", + "LH4" + ], + [ + "CLBLL_WW2END3", + "WW2END3" + ], + [ + "CLBLL_EL1BEG3", + "EL1BEG3" + ], + [ + "CLBLL_WW4END3", + "WW4END3" + ], + [ + "CLBLL_IMUX32", + "IMUX32" + ], + [ + "CLBLL_EE2BEG2", + "EE2BEG2" + ], + [ + "CLBLL_NE4BEG2", + "NE6BEG2" + ], + [ + "CLBLL_WW4END1", + "WW4END1" + ], + [ + "CLBLL_NE4C3", + "NE6E3" + ], + [ + "CLBLL_SW4END3", + "SW6END3" + ], + [ + "CLBLL_NW4A1", + "NW6A1" + ], + [ + "CLBLL_FAN6", + "FAN6" + ], + [ + "CLBLL_EE4C0", + "EE4C0" + ], + [ + "CLBLL_SE4C1", + "SE6E1" + ], + [ + "CLBLL_WW2A2", + "WW2A2" + ], + [ + "CLBLL_BYP0", + "BYP0" + ], + [ + "CLBLL_NW4A2", + "NW6A2" + ], + [ + "CLBLL_SE2A1", + "SE2A1" + ], + [ + "CLBLL_NW2A3", + "NW2END3" + ], + [ + "CLBLL_IMUX27", + "IMUX27" + ], + [ + "CLBLL_LH2", + "LH2" + ], + [ + "CLBLL_SE2A3", + "SE2A3" + ], + [ + "CLBLL_EE2A2", + "EE2A2" + ], + [ + "CLBLL_LH8", + "LH8" + ], + [ + "CLBLL_IMUX11", + "IMUX11" + ], + [ + "CLBLL_IMUX21", + "IMUX21" + ], + [ + "CLBLL_IMUX8", + "IMUX8" + ], + [ + "CLBLL_NW4END1", + "NW6END1" + ], + [ + "CLBLL_IMUX33", + "IMUX33" + ], + [ + "CLBLL_BYP7", + "BYP7" + ], + [ + "CLBLL_EE4A2", + "EE4A2" + ], + [ + "CLBLL_NW4END3", + "NW6END3" + ], + [ + "CLBLL_IMUX34", + "IMUX34" + ], + [ + "CLBLL_IMUX39", + "IMUX39" + ], + [ + "CLBLL_FAN4", + "FAN4" + ], + [ + "CLBLL_LOGIC_OUTS5", + "LOGIC_OUTS5" + ], + [ + "CLBLL_SW4A2", + "SW6A2" + ], + [ + "CLBLL_WR1END3", + "WR1END3" + ], + [ + "CLBLL_WR1END0", + "WR1END0" + ], + [ + "CLBLL_MONITOR_N", + "MONITOR_N" + ], + [ + "CLBLL_LH1", + "LH1" + ], + [ + "CLBLL_WW2END0", + "WW2END0" + ], + [ + "CLBLL_IMUX5", + "IMUX5" + ], + [ + "CLBLL_WW4C1", + "WW4C1" + ], + [ + "CLBLL_EE4A0", + "EE4A0" + ], + [ + "CLBLL_IMUX13", + "IMUX13" + ], + [ + "CLBLL_WW2A1", + "WW2A1" + ], + [ + "CLBLL_LOGIC_OUTS7", + "LOGIC_OUTS7" + ], + [ + "CLBLL_WW2A3", + "WW2A3" + ], + [ + "CLBLL_NE2A3", + "NE2A3" + ], + [ + "CLBLL_SW4A0", + "SW6A0" + ], + [ + "CLBLL_IMUX46", + "IMUX46" + ], + [ + "CLBLL_FAN2", + "FAN2" + ], + [ + "CLBLL_NE2A1", + "NE2A1" + ], + [ + "CLBLL_EE4BEG0", + "EE4BEG0" + ], + [ + "CLBLL_CLK0", + "CLK0" + ], + [ + "CLBLL_IMUX0", + "IMUX0" + ], + [ + "CLBLL_WW4B0", + "WW4B0" + ], + [ + "CLBLL_FAN3", + "FAN3" + ], + [ + "CLBLL_IMUX12", + "IMUX12" + ], + [ + "CLBLL_EL1BEG2", + "EL1BEG2" + ], + [ + "CLBLL_IMUX28", + "IMUX28" + ], + [ + "CLBLL_CTRL0", + "CTRL0" + ], + [ + "CLBLL_SE4BEG1", + "SE6BEG1" + ], + [ + "CLBLL_IMUX9", + "IMUX9" + ], + [ + "CLBLL_BYP5", + "BYP5" + ], + [ + "CLBLL_LOGIC_OUTS10", + "LOGIC_OUTS10" + ], + [ + "CLBLL_WW4A2", + "WW4A2" + ], + [ + "CLBLL_EE4A3", + "EE4A3" + ], + [ + "CLBLL_WW4A1", + "WW4A1" + ], + [ + "CLBLL_WR1END2", + "WR1END2" + ], + [ + "CLBLL_EE2A1", + "EE2A1" + ], + [ + "CLBLL_NE4C1", + "NE6E1" + ], + [ + "CLBLL_IMUX18", + "IMUX18" + ], + [ + "CLBLL_SW4A1", + "SW6A1" + ], + [ + "CLBLL_ER1BEG0", + "ER1BEG0" + ], + [ + "CLBLL_WR1END1", + "WR1END1" + ], + [ + "CLBLL_LH9", + "LH9" + ], + [ + "CLBLL_NE2A2", + "NE2A2" + ], + [ + "CLBLL_FAN5", + "FAN5" + ], + [ + "CLBLL_IMUX38", + "IMUX38" + ], + [ + "CLBLL_IMUX7", + "IMUX7" + ], + [ + "CLBLL_IMUX17", + "IMUX17" + ], + [ + "CLBLL_SE4BEG0", + "SE6BEG0" + ], + [ + "CLBLL_LH6", + "LH6" + ], + [ + "CLBLL_LOGIC_OUTS17", + "LOGIC_OUTS17" + ], + [ + "CLBLL_EE4B1", + "EE4B1" + ], + [ + "CLBLL_IMUX4", + "IMUX4" + ], + [ + "CLBLL_NE2A0", + "NE2A0" + ], + [ + "CLBLL_IMUX23", + "IMUX23" + ], + [ + "CLBLL_SE4BEG2", + "SE6BEG2" + ], + [ + "CLBLL_WW2A0", + "WW2A0" + ], + [ + "CLBLL_CTRL1", + "CTRL1" + ], + [ + "CLBLL_LOGIC_OUTS0", + "LOGIC_OUTS0" + ], + [ + "CLBLL_SE4BEG3", + "SE6BEG3" + ], + [ + "CLBLL_LOGIC_OUTS20", + "LOGIC_OUTS20" + ], + [ + "CLBLL_EE4BEG2", + "EE4BEG2" + ], + [ + "CLBLL_NW2A2", + "NW2END2" + ], + [ + "CLBLL_LOGIC_OUTS15", + "LOGIC_OUTS15" + ], + [ + "CLBLL_CLK1", + "CLK1" + ], + [ + "CLBLL_WW4C0", + "WW4C0" + ], + [ + "CLBLL_LOGIC_OUTS8", + "LOGIC_OUTS8" + ], + [ + "CLBLL_LOGIC_OUTS19", + "LOGIC_OUTS19" + ], + [ + "CLBLL_IMUX20", + "IMUX20" + ], + [ + "CLBLL_IMUX16", + "IMUX16" + ], + [ + "CLBLL_WW4C2", + "WW4C2" + ], + [ + "CLBLL_IMUX47", + "IMUX47" + ], + [ + "CLBLL_IMUX14", + "IMUX14" + ], + [ + "CLBLL_LH11", + "LH11" + ], + [ + "CLBLL_WL1END3", + "WL1END3" + ], + [ + "CLBLL_NW2A1", + "NW2END1" + ], + [ + "CLBLL_IMUX15", + "IMUX15" + ], + [ + "CLBLL_LOGIC_OUTS12", + "LOGIC_OUTS12" + ], + [ + "CLBLL_WW4C3", + "WW4C3" + ], + [ + "CLBLL_EE4C2", + "EE4C2" + ], + [ + "CLBLL_WW4A0", + "WW4A0" + ], + [ + "CLBLL_SW4END2", + "SW6END2" + ], + [ + "CLBLL_EE4BEG3", + "EE4BEG3" + ], + [ + "CLBLL_SW2A3", + "SW2END3" + ], + [ + "CLBLL_IMUX10", + "IMUX10" + ], + [ + "CLBLL_LOGIC_OUTS3", + "LOGIC_OUTS3" + ], + [ + "CLBLL_EE2BEG0", + "EE2BEG0" + ], + [ + "CLBLL_IMUX37", + "IMUX37" + ], + [ + "CLBLL_WW4END0", + "WW4END0" + ], + [ + "CLBLL_EE4BEG1", + "EE4BEG1" + ], + [ + "CLBLL_SW2A2", + "SW2END2" + ], + [ + "CLBLL_SW4END0", + "SW6END0" + ], + [ + "CLBLL_IMUX25", + "IMUX25" + ], + [ + "CLBLL_SW2A0", + "SW2END0" + ], + [ + "CLBLL_EE4A1", + "EE4A1" + ], + [ + "CLBLL_LH7", + "LH7" + ], + [ + "CLBLL_SE4C3", + "SE6E3" + ], + [ + "CLBLL_IMUX43", + "IMUX43" + ], + [ + "CLBLL_BYP6", + "BYP6" + ], + [ + "CLBLL_BYP1", + "BYP1" + ], + [ + "CLBLL_LH10", + "LH10" + ], + [ + "CLBLL_IMUX41", + "IMUX41" + ], + [ + "CLBLL_BYP4", + "BYP4" + ], + [ + "CLBLL_LOGIC_OUTS13", + "LOGIC_OUTS13" + ], + [ + "CLBLL_IMUX24", + "IMUX24" + ], + [ + "CLBLL_IMUX31", + "IMUX31" + ], + [ + "CLBLL_IMUX40", + "IMUX40" + ], + [ + "CLBLL_NW4A0", + "NW6A0" + ], + [ + "CLBLL_SE4C0", + "SE6E0" + ], + [ + "CLBLL_IMUX35", + "IMUX35" + ], + [ + "CLBLL_LOGIC_OUTS11", + "LOGIC_OUTS11" + ], + [ + "CLBLL_LOGIC_OUTS23", + "LOGIC_OUTS23" + ], + [ + "CLBLL_WW4B3", + "WW4B3" + ], + [ + "CLBLL_NW4END0", + "NW6END0" + ], + [ + "CLBLL_LH3", + "LH3" + ], + [ + "CLBLL_IMUX29", + "IMUX29" + ], + [ + "CLBLL_LH12", + "LH12" + ], + [ + "CLBLL_EE4B3", + "EE4B3" + ], + [ + "CLBLL_FAN1", + "FAN1" + ], + [ + "CLBLL_NW4A3", + "NW6A3" + ], + [ + "CLBLL_IMUX3", + "IMUX3" + ], + [ + "CLBLL_LOGIC_OUTS21", + "LOGIC_OUTS21" + ], + [ + "CLBLL_WW4B2", + "WW4B2" + ], + [ + "CLBLL_SW2A1", + "SW2END1" + ], + [ + "CLBLL_IMUX36", + "IMUX36" + ], + [ + "CLBLL_WW4A3", + "WW4A3" + ], + [ + "CLBLL_WW4B1", + "WW4B1" + ], + [ + "CLBLL_NW4END2", + "NW6END2" + ], + [ + "CLBLL_ER1BEG1", + "ER1BEG1" + ], + [ + "CLBLL_EE4C3", + "EE4C3" + ], + [ + "CLBLL_IMUX26", + "IMUX26" + ], + [ + "CLBLL_IMUX44", + "IMUX44" + ], + [ + "CLBLL_BYP2", + "BYP2" + ], + [ + "CLBLL_BYP3", + "BYP3" + ], + [ + "CLBLL_MONITOR_P", + "MONITOR_P" + ], + [ + "CLBLL_ER1BEG3", + "ER1BEG3" + ], + [ + "CLBLL_SE2A2", + "SE2A2" + ], + [ + "CLBLL_LOGIC_OUTS1", + "LOGIC_OUTS1" + ], + [ + "CLBLL_NE4C0", + "NE6E0" + ], + [ + "CLBLL_IMUX1", + "IMUX1" + ], + [ + "CLBLL_LOGIC_OUTS18", + "LOGIC_OUTS18" + ], + [ + "CLBLL_IMUX6", + "IMUX6" + ], + [ + "CLBLL_EE2A0", + "EE2A0" + ], + [ + "CLBLL_FAN7", + "FAN7" + ], + [ + "CLBLL_EE4B2", + "EE4B2" + ], + [ + "CLBLL_LOGIC_OUTS22", + "LOGIC_OUTS22" + ], + [ + "CLBLL_SW4END1", + "SW6END1" + ], + [ + "CLBLL_IMUX42", + "IMUX42" + ], + [ + "CLBLL_NW2A0", + "NW2END0" + ], + [ + "CLBLL_EE2A3", + "EE2A3" + ], + [ + "CLBLL_IMUX2", + "IMUX2" + ], + [ + "CLBLL_NE4BEG0", + "NE6BEG0" + ], + [ + "CLBLL_EE2BEG3", + "EE2BEG3" + ], + [ + "CLBLL_IMUX19", + "IMUX19" + ], + [ + "CLBLL_IMUX30", + "IMUX30" + ], + [ + "CLBLL_LOGIC_OUTS2", + "LOGIC_OUTS2" + ], + [ + "CLBLL_IMUX22", + "IMUX22" + ], + [ + "CLBLL_NE4C2", + "NE6E2" + ], + [ + "CLBLL_WW2END2", + "WW2END2" + ], + [ + "CLBLL_SE2A0", + "SE2A0" + ], + [ + "CLBLL_WL1END0", + "WL1END0" + ], + [ + "CLBLL_SE4C2", + "SE6E2" + ], + [ + "CLBLL_ER1BEG2", + "ER1BEG2" + ], + [ + "CLBLL_LOGIC_OUTS16", + "LOGIC_OUTS16" + ], + [ + "CLBLL_WW4END2", + "WW4END2" + ], + [ + "CLBLL_LOGIC_OUTS9", + "LOGIC_OUTS9" + ] + ], + "tile_types": [ + "CLBLL_R", + "INT_R" + ] + }, + { + "grid_deltas": [ + 1, + 4 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_NW2A0", + "BRAM_NW2A0_4" + ], + [ + "INT_INTERFACE_WW2A3", + "BRAM_WW2A3_4" + ], + [ + "INT_INTERFACE_LH9", + "BRAM_LH9_4" + ], + [ + "INT_INTERFACE_CTRL1", + "BRAM_CTRL1_4" + ], + [ + "INT_INTERFACE_EE2A1", + "BRAM_EE2A1_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX45", + "BRAM_IMUX45_UTURN_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B22", + "BRAM_LOGIC_OUTS_B22_4" + ], + [ + "INT_INTERFACE_EE4A1", + "BRAM_EE4A1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_4" + ], + [ + "INT_INTERFACE_EE4B1", + "BRAM_EE4B1_4" + ], + [ + "INT_INTERFACE_WW2A0", + "BRAM_WW2A0_4" + ], + [ + "INT_INTERFACE_EE4A2", + "BRAM_EE4A2_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX35", + "BRAM_IMUX35_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX40", + "BRAM_IMUX40_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX21", + "BRAM_IMUX21_UTURN_4" + ], + [ + "INT_INTERFACE_LH6", + "BRAM_LH6_4" + ], + [ + "INT_INTERFACE_WW4C1", + "BRAM_WW4C1_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B19", + "BRAM_LOGIC_OUTS_B19_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B11", + "BRAM_LOGIC_OUTS_B11_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX36", + "BRAM_IMUX36_UTURN_4" + ], + [ + "INT_INTERFACE_CLK1", + "BRAM_CLK1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX27", + "BRAM_IMUX27_4" + ], + [ + "INT_INTERFACE_WW4B2", + "BRAM_WW4B2_4" + ], + [ + "INT_INTERFACE_NE4BEG0", + "BRAM_NE4BEG0_4" + ], + [ + "INT_INTERFACE_FAN0", + "BRAM_FAN0_4" + ], + [ + "INT_INTERFACE_EL1BEG3", + "BRAM_EL1BEG3_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_4" + ], + [ + "INT_INTERFACE_BYP7", + "BRAM_BYP7_4" + ], + [ + "INT_INTERFACE_WW4B3", + "BRAM_WW4B3_4" + ], + [ + "INT_INTERFACE_WW2A1", + "BRAM_WW2A1_4" + ], + [ + "INT_INTERFACE_SW4END3", + "BRAM_SW4END3_4" + ], + [ + "INT_INTERFACE_WW4END2", + "BRAM_WW4END2_4" + ], + [ + "INT_INTERFACE_LH10", + "BRAM_LH10_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX41", + "BRAM_IMUX41_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX30", + "BRAM_IMUX30_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX28", + "BRAM_IMUX28_4" + ], + [ + "INT_INTERFACE_WW4C3", + "BRAM_WW4C3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX19", + "BRAM_IMUX19_UTURN_4" + ], + [ + "INT_INTERFACE_LH2", + "BRAM_LH2_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_4" + ], + [ + "INT_INTERFACE_BYP6", + "BRAM_BYP6_4" + ], + [ + "INT_INTERFACE_MONITOR_P", + "BRAM_MONITOR_P_4" + ], + [ + "INT_INTERFACE_SE4BEG0", + "BRAM_SE4BEG0_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX32", + "BRAM_IMUX32_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B12", + "BRAM_LOGIC_OUTS_B12_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX46", + "BRAM_IMUX46_UTURN_4" + ], + [ + "INT_INTERFACE_NW4END1", + "BRAM_NW4END1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX43", + "BRAM_IMUX43_4" + ], + [ + "INT_INTERFACE_EE4C1", + "BRAM_EE4C1_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX28", + "BRAM_IMUX28_UTURN_4" + ], + [ + "INT_INTERFACE_WW4B0", + "BRAM_WW4B0_4" + ], + [ + "INT_INTERFACE_SE2A3", + "BRAM_SE2A3_4" + ], + [ + "INT_INTERFACE_EE4B0", + "BRAM_EE4B0_4" + ], + [ + "INT_INTERFACE_SE4BEG3", + "BRAM_SE4BEG3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX42", + "BRAM_IMUX42_UTURN_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B1", + "BRAM_LOGIC_OUTS_B1_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B6", + "BRAM_LOGIC_OUTS_B6_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B0", + "BRAM_LOGIC_OUTS_B0_4" + ], + [ + "INT_INTERFACE_EE4B3", + "BRAM_EE4B3_4" + ], + [ + "INT_INTERFACE_FAN5", + "BRAM_FAN5_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX21", + "BRAM_IMUX21_4" + ], + [ + "INT_INTERFACE_WW4END1", + "BRAM_WW4END1_4" + ], + [ + "INT_INTERFACE_NW4END2", + "BRAM_NW4END2_4" + ], + [ + "INT_INTERFACE_EL1BEG2", + "BRAM_EL1BEG2_4" + ], + [ + "INT_INTERFACE_EE4C0", + "BRAM_EE4C0_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_4" + ], + [ + "INT_INTERFACE_EL1BEG0", + "BRAM_EL1BEG0_4" + ], + [ + "INT_INTERFACE_NE4C3", + "BRAM_NE4C3_4" + ], + [ + "INT_INTERFACE_EE2BEG1", + "BRAM_EE2BEG1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B13", + "BRAM_LOGIC_OUTS_B13_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B5", + "BRAM_LOGIC_OUTS_B5_4" + ], + [ + "INT_INTERFACE_EE2A0", + "BRAM_EE2A0_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX22", + "BRAM_IMUX22_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX31", + "BRAM_IMUX31_UTURN_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B8", + "BRAM_LOGIC_OUTS_B8_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX23", + "BRAM_IMUX23_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX5", + "BRAM_IMUX5_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX43", + "BRAM_IMUX43_UTURN_4" + ], + [ + "INT_INTERFACE_LH5", + "BRAM_LH5_4" + ], + [ + "INT_INTERFACE_SW2A2", + "BRAM_SW2A2_4" + ], + [ + "INT_INTERFACE_LH4", + "BRAM_LH4_4" + ], + [ + "INT_INTERFACE_ER1BEG2", + "BRAM_ER1BEG2_4" + ], + [ + "INT_INTERFACE_EE2A2", + "BRAM_EE2A2_4" + ], + [ + "INT_INTERFACE_LH12", + "BRAM_LH12_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX46", + "BRAM_IMUX46_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX41", + "BRAM_IMUX41_4" + ], + [ + "INT_INTERFACE_EE4BEG2", + "BRAM_EE4BEG2_4" + ], + [ + "INT_INTERFACE_SE4C3", + "BRAM_SE4C3_4" + ], + [ + "INT_INTERFACE_SW4END2", + "BRAM_SW4END2_4" + ], + [ + "INT_INTERFACE_WW4END0", + "BRAM_WW4END0_4" + ], + [ + "INT_INTERFACE_NE4C0", + "BRAM_NE4C0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX34", + "BRAM_IMUX34_UTURN_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B16", + "BRAM_LOGIC_OUTS_B16_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B2", + "BRAM_LOGIC_OUTS_B2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B15", + "BRAM_LOGIC_OUTS_B15_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B20", + "BRAM_LOGIC_OUTS_B20_4" + ], + [ + "INT_INTERFACE_SE4BEG1", + "BRAM_SE4BEG1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_4" + ], + [ + "INT_INTERFACE_FAN2", + "BRAM_FAN2_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX20", + "BRAM_IMUX20_UTURN_4" + ], + [ + "INT_INTERFACE_SW4A3", + "BRAM_SW4A3_4" + ], + [ + "INT_INTERFACE_EE4BEG3", + "BRAM_EE4BEG3_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B7", + "BRAM_LOGIC_OUTS_B7_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX44", + "BRAM_IMUX44_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX25", + "BRAM_IMUX25_4" + ], + [ + "INT_INTERFACE_BYP0", + "BRAM_BYP0_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX47", + "BRAM_IMUX47_4" + ], + [ + "INT_INTERFACE_SW4A0", + "BRAM_SW4A0_4" + ], + [ + "INT_INTERFACE_WW4A2", + "BRAM_WW4A2_4" + ], + [ + "INT_INTERFACE_EE2A3", + "BRAM_EE2A3_4" + ], + [ + "INT_INTERFACE_SW4A2", + "BRAM_SW4A2_4" + ], + [ + "INT_INTERFACE_NE4C1", + "BRAM_NE4C1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX26", + "BRAM_IMUX26_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX32", + "BRAM_IMUX32_UTURN_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B9", + "BRAM_LOGIC_OUTS_B9_4" + ], + [ + "INT_INTERFACE_EE4C3", + "BRAM_EE4C3_4" + ], + [ + "INT_INTERFACE_LH3", + "BRAM_LH3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX11", + "BRAM_IMUX11_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX44", + "BRAM_IMUX44_UTURN_4" + ], + [ + "INT_INTERFACE_NW4END0", + "BRAM_NW4END0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX16", + "BRAM_IMUX16_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX36", + "BRAM_IMUX36_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B21", + "BRAM_LOGIC_OUTS_B21_4" + ], + [ + "INT_INTERFACE_FAN7", + "BRAM_FAN7_4" + ], + [ + "INT_INTERFACE_WL1END3", + "BRAM_WL1END3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX2", + "BRAM_IMUX2_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_4" + ], + [ + "INT_INTERFACE_NW4A2", + "BRAM_NW4A2_4" + ], + [ + "INT_INTERFACE_CTRL0", + "BRAM_CTRL0_4" + ], + [ + "INT_INTERFACE_LH11", + "BRAM_LH11_4" + ], + [ + "INT_INTERFACE_FAN4", + "BRAM_FAN4_4" + ], + [ + "INT_INTERFACE_SW2A1", + "BRAM_SW2A1_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B18", + "BRAM_LOGIC_OUTS_B18_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B4", + "BRAM_LOGIC_OUTS_B4_4" + ], + [ + "INT_INTERFACE_WW4C0", + "BRAM_WW4C0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX12", + "BRAM_IMUX12_UTURN_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B3", + "BRAM_LOGIC_OUTS_B3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX1", + "BRAM_IMUX1_UTURN_4" + ], + [ + "INT_INTERFACE_SE2A1", + "BRAM_SE2A1_4" + ], + [ + "INT_INTERFACE_NE2A3", + "BRAM_NE2A3_4" + ], + [ + "INT_INTERFACE_SE4C0", + "BRAM_SE4C0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX22", + "BRAM_IMUX22_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX4", + "BRAM_IMUX4_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX7", + "BRAM_IMUX7_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_4" + ], + [ + "INT_INTERFACE_EE4C2", + "BRAM_EE4C2_4" + ], + [ + "INT_INTERFACE_NW2A1", + "BRAM_NW2A1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_4" + ], + [ + "INT_INTERFACE_NE4BEG1", + "BRAM_NE4BEG1_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX26", + "BRAM_IMUX26_UTURN_4" + ], + [ + "INT_INTERFACE_BYP5", + "BRAM_BYP5_4" + ], + [ + "INT_INTERFACE_BYP4", + "BRAM_BYP4_4" + ], + [ + "INT_INTERFACE_SE4C2", + "BRAM_SE4C2_4" + ], + [ + "INT_INTERFACE_SW4END1", + "BRAM_SW4END1_4" + ], + [ + "INT_INTERFACE_WW4B1", + "BRAM_WW4B1_4" + ], + [ + "INT_INTERFACE_WR1END1", + "BRAM_WR1END1_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX8", + "BRAM_IMUX8_UTURN_4" + ], + [ + "INT_INTERFACE_WW2END0", + "BRAM_WW2END0_4" + ], + [ + "INT_INTERFACE_NE4C2", + "BRAM_NE4C2_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX37", + "BRAM_IMUX37_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX24", + "BRAM_IMUX24_4" + ], + [ + "INT_INTERFACE_NE4BEG3", + "BRAM_NE4BEG3_4" + ], + [ + "INT_INTERFACE_WL1END0", + "BRAM_WL1END0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B10", + "BRAM_LOGIC_OUTS_B10_4" + ], + [ + "INT_INTERFACE_SW4END0", + "BRAM_SW4END0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX24", + "BRAM_IMUX24_UTURN_4" + ], + [ + "INT_INTERFACE_EE2BEG0", + "BRAM_EE2BEG0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B23", + "BRAM_LOGIC_OUTS_B23_4" + ], + [ + "INT_INTERFACE_WL1END2", + "BRAM_WL1END2_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX14", + "BRAM_IMUX14_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX39", + "BRAM_IMUX39_UTURN_4" + ], + [ + "INT_INTERFACE_LH7", + "BRAM_LH7_4" + ], + [ + "INT_INTERFACE_WW4C2", + "BRAM_WW4C2_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX18", + "BRAM_IMUX18_UTURN_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B17", + "BRAM_LOGIC_OUTS_B17_4" + ], + [ + "INT_INTERFACE_WL1END1", + "BRAM_WL1END1_4" + ], + [ + "INT_INTERFACE_NW2A3", + "BRAM_NW2A3_4" + ], + [ + "INT_INTERFACE_WW2END3", + "BRAM_WW2END3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX9", + "BRAM_IMUX9_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_4" + ], + [ + "INT_INTERFACE_NE2A0", + "BRAM_NE2A0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX25", + "BRAM_IMUX25_UTURN_4" + ], + [ + "INT_INTERFACE_WW2END2", + "BRAM_WW2END2_4" + ], + [ + "INT_INTERFACE_ER1BEG3", + "BRAM_ER1BEG3_4" + ], + [ + "INT_INTERFACE_WW2END1", + "BRAM_WW2END1_4" + ], + [ + "INT_INTERFACE_WW2A2", + "BRAM_WW2A2_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX15", + "BRAM_IMUX15_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX39", + "BRAM_IMUX39_4" + ], + [ + "INT_INTERFACE_NE2A2", + "BRAM_NE2A2_4" + ], + [ + "INT_INTERFACE_LH8", + "BRAM_LH8_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX45", + "BRAM_IMUX45_4" + ], + [ + "INT_INTERFACE_WR1END3", + "BRAM_WR1END3_4" + ], + [ + "INT_INTERFACE_CLK0", + "BRAM_CLK0_4" + ], + [ + "INT_INTERFACE_NE2A1", + "BRAM_NE2A1_4" + ], + [ + "INT_INTERFACE_WW4A0", + "BRAM_WW4A0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX17", + "BRAM_IMUX17_UTURN_4" + ], + [ + "INT_INTERFACE_EE4A0", + "BRAM_EE4A0_4" + ], + [ + "INT_INTERFACE_SW4A1", + "BRAM_SW4A1_4" + ], + [ + "INT_INTERFACE_SW2A0", + "BRAM_SW2A0_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX42", + "BRAM_IMUX42_4" + ], + [ + "INT_INTERFACE_SW2A3", + "BRAM_SW2A3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX38", + "BRAM_IMUX38_UTURN_4" + ], + [ + "INT_INTERFACE_NW4A1", + "BRAM_NW4A1_4" + ], + [ + "INT_INTERFACE_SE2A2", + "BRAM_SE2A2_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX31", + "BRAM_IMUX31_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX33", + "BRAM_IMUX33_4" + ], + [ + "INT_INTERFACE_ER1BEG1", + "BRAM_ER1BEG1_4" + ], + [ + "INT_INTERFACE_FAN6", + "BRAM_FAN6_4" + ], + [ + "INT_INTERFACE_FAN1", + "BRAM_FAN1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX40", + "BRAM_IMUX40_4" + ], + [ + "INT_INTERFACE_BYP2", + "BRAM_BYP2_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX30", + "BRAM_IMUX30_4" + ], + [ + "INT_INTERFACE_WW4A3", + "BRAM_WW4A3_4" + ], + [ + "INT_INTERFACE_LH1", + "BRAM_LH1_4" + ], + [ + "INT_INTERFACE_NW4A3", + "BRAM_NW4A3_4" + ], + [ + "INT_INTERFACE_EE2BEG3", + "BRAM_EE2BEG3_4" + ], + [ + "INT_INTERFACE_SE2A0", + "BRAM_SE2A0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX33", + "BRAM_IMUX33_UTURN_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B14", + "BRAM_LOGIC_OUTS_B14_4" + ], + [ + "INT_INTERFACE_WW4A1", + "BRAM_WW4A1_4" + ], + [ + "INT_INTERFACE_SE4BEG2", + "BRAM_SE4BEG2_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX3", + "BRAM_IMUX3_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_4" + ], + [ + "INT_INTERFACE_EL1BEG1", + "BRAM_EL1BEG1_4" + ], + [ + "INT_INTERFACE_BYP1", + "BRAM_BYP1_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX34", + "BRAM_IMUX34_4" + ], + [ + "INT_INTERFACE_EE4B2", + "BRAM_EE4B2_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX13", + "BRAM_IMUX13_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX47", + "BRAM_IMUX47_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX29", + "BRAM_IMUX29_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_4" + ], + [ + "INT_INTERFACE_EE4A3", + "BRAM_EE4A3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX0", + "BRAM_IMUX0_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX37", + "BRAM_IMUX37_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX23", + "BRAM_IMUX23_4" + ], + [ + "INT_INTERFACE_EE4BEG0", + "BRAM_EE4BEG0_4" + ], + [ + "INT_INTERFACE_ER1BEG0", + "BRAM_ER1BEG0_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX38", + "BRAM_IMUX38_4" + ], + [ + "INT_INTERFACE_EE2BEG2", + "BRAM_EE2BEG2_4" + ], + [ + "INT_INTERFACE_NE4BEG2", + "BRAM_NE4BEG2_4" + ], + [ + "INT_INTERFACE_FAN3", + "BRAM_FAN3_4" + ], + [ + "INT_INTERFACE_NW2A2", + "BRAM_NW2A2_4" + ], + [ + "INT_INTERFACE_WR1END2", + "BRAM_WR1END2_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX35", + "BRAM_IMUX35_4" + ], + [ + "INT_INTERFACE_MONITOR_N", + "BRAM_MONITOR_N_4" + ], + [ + "INT_INTERFACE_NW4END3", + "BRAM_NW4END3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX10", + "BRAM_IMUX10_UTURN_4" + ], + [ + "INT_INTERFACE_WR1END0", + "BRAM_WR1END0_4" + ], + [ + "INT_INTERFACE_WW4END3", + "BRAM_WW4END3_4" + ], + [ + "INT_INTERFACE_SE4C1", + "BRAM_SE4C1_4" + ], + [ + "INT_INTERFACE_EE4BEG1", + "BRAM_EE4BEG1_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX6", + "BRAM_IMUX6_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_4" + ], + [ + "INT_INTERFACE_NW4A0", + "BRAM_NW4A0_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX29", + "BRAM_IMUX29_UTURN_4" + ], + [ + "INT_INTERFACE_BYP3", + "BRAM_BYP3_4" + ], + [ + "INT_INTERFACE_BRAM_UTURN_R_IMUX27", + "BRAM_IMUX27_UTURN_4" + ], + [ + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_4" + ] + ], + "tile_types": [ + "BRAM_INT_INTERFACE_R", + "BRAM_R" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "IOB_PU_INT_EN_1", + "RIOI_PU_INT_EN_1" + ], + [ + "IOB_O0", + "RIOI_O0" + ], + [ + "IOB_KEEPER_INT_EN_1", + "RIOI_KEEPER_INT_EN_1" + ], + [ + "IOB_DCI_T_TERM0", + "RIOI_DCI_T_TERM0" + ], + [ + "IOB_PD_INT_EN_1", + "RIOI_PD_INT_EN_1" + ], + [ + "IOB_IBUF_DISABLE0", + "RIOI_IBUF_DISABLE0" + ], + [ + "IOB_IBUF0", + "RIOI_IBUF0" + ], + [ + "IOB_T0", + "RIOI_T0" + ] + ], + "tile_types": [ + "RIOB18_SING", + "RIOI_SING" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "IOB_PD_INT_EN_0", + "RIOI_PD_INT_EN_0" + ], + [ + "IOB_DIFF_TERM_INT_EN", + "RIOI_DIFF_TERM_INT_EN" + ], + [ + "IOB_KEEPER_INT_EN_0", + "RIOI_KEEPER_INT_EN_0" + ], + [ + "IOB_PU_INT_EN_1", + "RIOI_PU_INT_EN_1" + ], + [ + "IOB_O0", + "RIOI_O0" + ], + [ + "IOB_KEEPER_INT_EN_1", + "RIOI_KEEPER_INT_EN_1" + ], + [ + "IOB_DCI_T_TERM0", + "RIOI_DCI_T_TERM0" + ], + [ + "IOB_PD_INT_EN_1", + "RIOI_PD_INT_EN_1" + ], + [ + "IOB_T1", + "RIOI_T1" + ], + [ + "IOB_O1", + "RIOI_O1" + ], + [ + "IOB_IBUF_DISABLE1", + "RIOI_IBUF_DISABLE1" + ], + [ + "IOB_IBUF1", + "RIOI_IBUF1" + ], + [ + "RIOB_MONITOR_N", + "IOI_MONITOR_N" + ], + [ + "IOB_IBUF_DISABLE0", + "RIOI_IBUF_DISABLE0" + ], + [ + "IOB_DCI_T_TERM1", + "RIOI_DCI_T_TERM1" + ], + [ + "IOB_IBUF0", + "RIOI_IBUF0" + ], + [ + "IOB_PU_INT_EN_0", + "RIOI_PU_INT_EN_0" + ], + [ + "IOB_T0", + "RIOI_T0" + ], + [ + "RIOB_MONITOR_P", + "IOI_MONITOR_P" + ] + ], + "tile_types": [ + "RIOB18", + "RIOI" + ] + }, + { + "grid_deltas": [ + 5, + -6 + ], + "wire_pairs": [ + [ + "PCIE_IMUX47_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_FAN4_L_16", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_EE4B0_16", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_NW4A1_16", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_IMUX41_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_BYP5_L_16", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_IMUX16_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_IMUX23_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_IMUX10_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_EE4BEG0_16", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_BYP7_L_16", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_BYP3_L_16", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_WW4B3_16", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_WW2A1_16", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_IMUX24_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_BYP1_L_16", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_SE2A1_16", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_BYP4_L_16", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_IMUX6_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_EE2A1_16", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_NE4C0_16", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_SW4END3_16", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_IMUX11_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_IMUX44_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_NW4END3_16", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_IMUX35_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_NW4A0_16", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_EE2A3_16", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_EE4B2_16", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_FAN3_L_16", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_NW2A0_16", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_IMUX26_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_EE4B1_16", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_NE2A0_16", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_EE2BEG0_16", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_EL1BEG2_16", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_CTRL0_L_16", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_WW2END2_16", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_IMUX8_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_WW4C2_16", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_LH1_16", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_WW4A3_16", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_SE4C3_16", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_WW4A0_16", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_EL1BEG3_16", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_SE4BEG2_16", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_LH10_16", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_NE4BEG2_16", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_IMUX15_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_EE2A0_16", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_SW4END2_16", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_CLK1_L_16", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_IMUX29_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_NE4C3_16", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_WW4B1_16", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_EE4C2_16", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_WW4B0_16", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_SW4A3_16", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_LH5_16", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_WW2A0_16", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_IMUX46_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_WR1END1_16", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_IMUX2_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_SE4BEG1_16", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_SE4BEG0_16", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_IMUX42_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_IMUX25_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_CTRL1_L_16", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_EE2A2_16", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_NW2A2_16", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_EE2BEG1_16", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_FAN6_L_16", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_NE4BEG3_16", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_EE2BEG2_16", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_NW2A1_16", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_EE4A0_16", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_SE2A0_16", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_IMUX43_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_BYP2_L_16", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_SE4BEG3_16", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_ER1BEG1_16", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_NE4BEG0_16", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_EE4BEG3_16", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_LH3_16", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_EE4A2_16", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_IMUX21_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_WW4B2_16", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_WW4A1_16", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_CLK0_L_16", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_IMUX45_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_EE4A3_16", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_SE2A3_16", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_SE4C2_16", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_FAN0_L_16", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_IMUX34_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_IMUX0_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_BYP6_L_16", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_SE4C0_16", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_WW4C0_16", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_FAN5_L_16", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_WW2END3_16", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_WL1END0_16", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_WW4C3_16", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_NW2A3_16", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_IMUX39_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_SW4A0_16", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_EE4A1_16", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_NW4END1_16", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_SW2A1_16", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_NW4END2_16", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_EL1BEG0_16", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_NE4C2_16", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_NW4A3_16", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_EL1BEG1_16", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_WW2END0_16", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_NE2A2_16", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_FAN1_L_16", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_IMUX5_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_WW4END2_16", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_WR1END2_16", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_IMUX20_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_WR1END0_16", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_WW4END3_16", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_WW4END1_16", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_NW4END0_16", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_IMUX37_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_ER1BEG0_16", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_FAN2_L_16", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_IMUX40_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_EE4BEG2_16", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX7_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_EE2BEG3_16", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_EE4C3_16", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_NW4A2_16", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_WL1END3_16", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_SW4END0_16", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_LH9_16", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_WW2END1_16", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_WL1END1_16", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_IMUX12_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_IMUX19_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_IMUX38_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_IMUX4_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_WW4A2_16", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_NE4C1_16", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_ER1BEG2_16", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_IMUX22_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_LH8_16", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4B3_16", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_SE4C1_16", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_LH4_16", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_LH7_16", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_WW2A3_16", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_IMUX32_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_IMUX27_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_EE4C1_16", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_LH11_16", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_IMUX30_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_SW4END1_16", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_SW2A2_16", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_IMUX33_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_LH6_16", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_NE4BEG1_16", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX36_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_BYP0_L_16", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_WW4END0_16", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_IMUX9_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_IMUX31_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_IMUX28_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_EE4BEG1_16", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_ER1BEG3_16", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_SW2A0_16", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_SW4A2_16", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_FAN7_L_16", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_WW4C1_16", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_SW4A1_16", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_IMUX17_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_IMUX13_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_IMUX14_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_16", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_SE2A2_16", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_WW2A2_16", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_WR1END3_16", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_NE2A3_16", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_NE2A1_16", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_IMUX1_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_EE4C0_16", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_LH12_16", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_IMUX3_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_WL1END2_16", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_LH2_16", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_SW2A3_16", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX18_L_16", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "MONITOR_EE2A1_0", + "VFRAME_EE2A1" + ], + [ + "MONITOR_IMUX27_0", + "VFRAME_IMUX27" + ], + [ + "MONITOR_ER1BEG2_0", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_NW4END0_0", + "VFRAME_NW4END0" + ], + [ + "MONITOR_EE4A3_0", + "VFRAME_EE4A3" + ], + [ + "MONITOR_IMUX11_0", + "VFRAME_IMUX11" + ], + [ + "MONITOR_BYP1_0", + "VFRAME_BYP1" + ], + [ + "MONITOR_FAN3_0", + "VFRAME_FAN3" + ], + [ + "MONITOR_LH2_0", + "VFRAME_LH2" + ], + [ + "MONITOR_SW2A0_0", + "VFRAME_SW2A0" + ], + [ + "MONITOR_LH10_0", + "VFRAME_LH10" + ], + [ + "MONITOR_IMUX26_0", + "VFRAME_IMUX26" + ], + [ + "MONITOR_IMUX9_0", + "VFRAME_IMUX9" + ], + [ + "MONITOR_SW2A2_0", + "VFRAME_SW2A2" + ], + [ + "MONITOR_IMUX8_0", + "VFRAME_IMUX8" + ], + [ + "MONITOR_EE4BEG2_0", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_WW2END0_0", + "VFRAME_WW2END0" + ], + [ + "MONITOR_FAN6_0", + "VFRAME_FAN6" + ], + [ + "MONITOR_SW2A1_0", + "VFRAME_SW2A1" + ], + [ + "MONITOR_SW4A1_0", + "VFRAME_SW4A1" + ], + [ + "MONITOR_EE4BEG3_0", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_IMUX44_0", + "VFRAME_IMUX44" + ], + [ + "MONITOR_IMUX22_0", + "VFRAME_IMUX22" + ], + [ + "MONITOR_WW4A3_0", + "VFRAME_WW4A3" + ], + [ + "MONITOR_FAN2_0", + "VFRAME_FAN2" + ], + [ + "MONITOR_NW2A3_0", + "VFRAME_NW2A3" + ], + [ + "MONITOR_IMUX46_0", + "VFRAME_IMUX46" + ], + [ + "MONITOR_SW4END1_0", + "VFRAME_SW4END1" + ], + [ + "MONITOR_NE4BEG1_0", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_SE4BEG0_0", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_IMUX41_0", + "VFRAME_IMUX41" + ], + [ + "MONITOR_SW4END0_0", + "VFRAME_SW4END0" + ], + [ + "MONITOR_IMUX2_0", + "VFRAME_IMUX2" + ], + [ + "MONITOR_SW4END2_0", + "VFRAME_SW4END2" + ], + [ + "MONITOR_SE4BEG1_0", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_EE4C1_0", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX15_0", + "VFRAME_IMUX15" + ], + [ + "MONITOR_NE2A0_0", + "VFRAME_NE2A0" + ], + [ + "MONITOR_ER1BEG0_0", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_IMUX36_0", + "VFRAME_IMUX36" + ], + [ + "MONITOR_WW4B1_0", + "VFRAME_WW4B1" + ], + [ + "MONITOR_NW4END1_0", + "VFRAME_NW4END1" + ], + [ + "MONITOR_EE4A0_0", + "VFRAME_EE4A0" + ], + [ + "MONITOR_LH1_0", + "VFRAME_LH1" + ], + [ + "MONITOR_SE4C2_0", + "VFRAME_SE4C2" + ], + [ + "MONITOR_LH6_0", + "VFRAME_LH6" + ], + [ + "MONITOR_IMUX10_0", + "VFRAME_IMUX10" + ], + [ + "MONITOR_IMUX23_0", + "VFRAME_IMUX23" + ], + [ + "MONITOR_SE4C3_0", + "VFRAME_SE4C3" + ], + [ + "MONITOR_SW4END3_0", + "VFRAME_SW4END3" + ], + [ + "MONITOR_EE4A2_0", + "VFRAME_EE4A2" + ], + [ + "MONITOR_IMUX5_0", + "VFRAME_IMUX5" + ], + [ + "MONITOR_NE4BEG3_0", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_IMUX35_0", + "VFRAME_IMUX35" + ], + [ + "MONITOR_CLK0_0", + "VFRAME_CLK0" + ], + [ + "MONITOR_IMUX21_0", + "VFRAME_IMUX21" + ], + [ + "MONITOR_NE4C1_0", + "VFRAME_NE4C1" + ], + [ + "MONITOR_IMUX14_0", + "VFRAME_IMUX14" + ], + [ + "MONITOR_LH12_0", + "VFRAME_LH12" + ], + [ + "MONITOR_WW2A1_0", + "VFRAME_WW2A1" + ], + [ + "MONITOR_IMUX34_0", + "VFRAME_IMUX34" + ], + [ + "MONITOR_EE2A2_0", + "VFRAME_EE2A2" + ], + [ + "MONITOR_EE2BEG2_0", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_WL1END3_0", + "VFRAME_WL1END3" + ], + [ + "MONITOR_IMUX45_0", + "VFRAME_IMUX45" + ], + [ + "MONITOR_IMUX0_0", + "VFRAME_IMUX0" + ], + [ + "MONITOR_WW2END1_0", + "VFRAME_WW2END1" + ], + [ + "MONITOR_IMUX40_0", + "VFRAME_IMUX40" + ], + [ + "MONITOR_ER1BEG1_0", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_IMUX6_0", + "VFRAME_IMUX6" + ], + [ + "MONITOR_EE4C2_0", + "VFRAME_EE4C2" + ], + [ + "MONITOR_WW4END1_0", + "VFRAME_WW4END1" + ], + [ + "MONITOR_NW4A2_0", + "VFRAME_NW4A2" + ], + [ + "MONITOR_FAN0_0", + "VFRAME_FAN0" + ], + [ + "MONITOR_WW4C0_0", + "VFRAME_WW4C0" + ], + [ + "MONITOR_IMUX13_0", + "VFRAME_IMUX13" + ], + [ + "MONITOR_WW4C2_0", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE2A3_0", + "VFRAME_EE2A3" + ], + [ + "MONITOR_IMUX29_0", + "VFRAME_IMUX29" + ], + [ + "MONITOR_WW2A0_0", + "VFRAME_WW2A0" + ], + [ + "MONITOR_ER1BEG3_0", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_EE4A1_0", + "VFRAME_EE4A1" + ], + [ + "MONITOR_BYP3_0", + "VFRAME_BYP3" + ], + [ + "MONITOR_EE4BEG1_0", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_SW4A2_0", + "VFRAME_SW4A2" + ], + [ + "MONITOR_IMUX43_0", + "VFRAME_IMUX43" + ], + [ + "MONITOR_IMUX24_0", + "VFRAME_IMUX24" + ], + [ + "MONITOR_CTRL1_0", + "VFRAME_CTRL1" + ], + [ + "MONITOR_IMUX28_0", + "VFRAME_IMUX28" + ], + [ + "MONITOR_FAN5_0", + "VFRAME_FAN5" + ], + [ + "MONITOR_SE2A0_0", + "VFRAME_SE2A0" + ], + [ + "MONITOR_IMUX31_0", + "VFRAME_IMUX31" + ], + [ + "MONITOR_WW4B3_0", + "VFRAME_WW4B3" + ], + [ + "MONITOR_WW2A2_0", + "VFRAME_WW2A2" + ], + [ + "MONITOR_FAN7_0", + "VFRAME_FAN7" + ], + [ + "MONITOR_IMUX19_0", + "VFRAME_IMUX19" + ], + [ + "MONITOR_EE2BEG1_0", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_EE4C3_0", + "VFRAME_EE4C3" + ], + [ + "MONITOR_FAN4_0", + "VFRAME_FAN4" + ], + [ + "MONITOR_SE2A2_0", + "VFRAME_SE2A2" + ], + [ + "MONITOR_IMUX47_0", + "VFRAME_IMUX47" + ], + [ + "MONITOR_NE4C3_0", + "VFRAME_NE4C3" + ], + [ + "MONITOR_IMUX17_0", + "VFRAME_IMUX17" + ], + [ + "MONITOR_WL1END1_0", + "VFRAME_WL1END1" + ], + [ + "MONITOR_IMUX37_0", + "VFRAME_IMUX37" + ], + [ + "MONITOR_IMUX30_0", + "VFRAME_IMUX30" + ], + [ + "MONITOR_SW4A0_0", + "VFRAME_SW4A0" + ], + [ + "MONITOR_EE2BEG3_0", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_IMUX33_0", + "VFRAME_IMUX33" + ], + [ + "MONITOR_NW2A0_0", + "VFRAME_NW2A0" + ], + [ + "MONITOR_EE4BEG0_0", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_NW4A3_0", + "VFRAME_NW4A3" + ], + [ + "MONITOR_WR1END2_0", + "VFRAME_WR1END2" + ], + [ + "MONITOR_WW4END0_0", + "VFRAME_WW4END0" + ], + [ + "MONITOR_SW2A3_0", + "VFRAME_SW2A3" + ], + [ + "MONITOR_NW4END2_0", + "VFRAME_NW4END2" + ], + [ + "MONITOR_WW2A3_0", + "VFRAME_WW2A3" + ], + [ + "MONITOR_LH3_0", + "VFRAME_LH3" + ], + [ + "MONITOR_IMUX3_0", + "VFRAME_IMUX3" + ], + [ + "MONITOR_EL1BEG0_0", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_EE4C0_0", + "VFRAME_EE4C0" + ], + [ + "MONITOR_NE4BEG2_0", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_BYP0_0", + "VFRAME_BYP0" + ], + [ + "MONITOR_WW4A0_0", + "VFRAME_WW4A0" + ], + [ + "MONITOR_NE4C2_0", + "VFRAME_NE4C2" + ], + [ + "MONITOR_NE4BEG0_0", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_SE4BEG3_0", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_NE4C0_0", + "VFRAME_NE4C0" + ], + [ + "MONITOR_NW2A1_0", + "VFRAME_NW2A1" + ], + [ + "MONITOR_SE4C1_0", + "VFRAME_SE4C1" + ], + [ + "MONITOR_IMUX32_0", + "VFRAME_IMUX32" + ], + [ + "MONITOR_EE4B1_0", + "VFRAME_EE4B1" + ], + [ + "MONITOR_BYP7_0", + "VFRAME_BYP7" + ], + [ + "MONITOR_IMUX7_0", + "VFRAME_IMUX7" + ], + [ + "MONITOR_IMUX18_0", + "VFRAME_IMUX18" + ], + [ + "MONITOR_NW2A2_0", + "VFRAME_NW2A2" + ], + [ + "MONITOR_BYP4_0", + "VFRAME_BYP4" + ], + [ + "MONITOR_IMUX25_0", + "VFRAME_IMUX25" + ], + [ + "MONITOR_WW4B0_0", + "VFRAME_WW4B0" + ], + [ + "MONITOR_NE2A1_0", + "VFRAME_NE2A1" + ], + [ + "MONITOR_WW4C3_0", + "VFRAME_WW4C3" + ], + [ + "MONITOR_IMUX4_0", + "VFRAME_IMUX4" + ], + [ + "MONITOR_EE4B3_0", + "VFRAME_EE4B3" + ], + [ + "MONITOR_LH7_0", + "VFRAME_LH7" + ], + [ + "MONITOR_SE4BEG2_0", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_IMUX1_0", + "VFRAME_IMUX1" + ], + [ + "MONITOR_NW4A0_0", + "VFRAME_NW4A0" + ], + [ + "MONITOR_LH9_0", + "VFRAME_LH9" + ], + [ + "MONITOR_WL1END2_0", + "VFRAME_WL1END2" + ], + [ + "MONITOR_BYP5_0", + "VFRAME_BYP5" + ], + [ + "MONITOR_IMUX20_0", + "VFRAME_IMUX20" + ], + [ + "MONITOR_SE2A1_0", + "VFRAME_SE2A1" + ], + [ + "MONITOR_EE4B0_0", + "VFRAME_EE4B0" + ], + [ + "MONITOR_NE2A3_0", + "VFRAME_NE2A3" + ], + [ + "MONITOR_LH5_0", + "VFRAME_LH5" + ], + [ + "MONITOR_NE2A2_0", + "VFRAME_NE2A2" + ], + [ + "MONITOR_IMUX39_0", + "VFRAME_IMUX39" + ], + [ + "MONITOR_WW4A1_0", + "VFRAME_WW4A1" + ], + [ + "MONITOR_IMUX42_0", + "VFRAME_IMUX42" + ], + [ + "MONITOR_EE2BEG0_0", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_BYP6_0", + "VFRAME_BYP6" + ], + [ + "MONITOR_SW4A3_0", + "VFRAME_SW4A3" + ], + [ + "MONITOR_NW4A1_0", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WR1END3_0", + "VFRAME_WR1END3" + ], + [ + "MONITOR_EL1BEG3_0", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_WW4C1_0", + "VFRAME_WW4C1" + ], + [ + "MONITOR_IMUX12_0", + "VFRAME_IMUX12" + ], + [ + "MONITOR_WR1END1_0", + "VFRAME_WR1END1" + ], + [ + "MONITOR_IMUX38_0", + "VFRAME_IMUX38" + ], + [ + "MONITOR_SE2A3_0", + "VFRAME_SE2A3" + ], + [ + "MONITOR_LH4_0", + "VFRAME_LH4" + ], + [ + "MONITOR_FAN1_0", + "VFRAME_FAN1" + ], + [ + "MONITOR_NW4END3_0", + "VFRAME_NW4END3" + ], + [ + "MONITOR_EE4B2_0", + "VFRAME_EE4B2" + ], + [ + "MONITOR_BYP2_0", + "VFRAME_BYP2" + ], + [ + "MONITOR_LH11_0", + "VFRAME_LH11" + ], + [ + "MONITOR_CLK1_0", + "VFRAME_CLK1" + ], + [ + "MONITOR_CTRL0_0", + "VFRAME_CTRL0" + ], + [ + "MONITOR_LH8_0", + "VFRAME_LH8" + ], + [ + "MONITOR_WW4A2_0", + "VFRAME_WW4A2" + ], + [ + "MONITOR_WW4END3_0", + "VFRAME_WW4END3" + ], + [ + "MONITOR_EL1BEG1_0", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_WL1END0_0", + "VFRAME_WL1END0" + ], + [ + "MONITOR_SE4C0_0", + "VFRAME_SE4C0" + ], + [ + "MONITOR_WW4END2_0", + "VFRAME_WW4END2" + ], + [ + "MONITOR_IMUX16_0", + "VFRAME_IMUX16" + ], + [ + "MONITOR_WW2END3_0", + "VFRAME_WW2END3" + ], + [ + "MONITOR_WR1END0_0", + "VFRAME_WR1END0" + ], + [ + "MONITOR_EL1BEG2_0", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_WW2END2_0", + "VFRAME_WW2END2" + ], + [ + "MONITOR_WW4B2_0", + "VFRAME_WW4B2" + ], + [ + "MONITOR_EE2A0_0", + "VFRAME_EE2A0" + ] + ], + "tile_types": [ + "MONITOR_MID_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + -6 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4A3_10", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SE2A3_10", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG0_10", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END2_10", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW4C0_10", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_LH8_10", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4B2_10", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A1_10", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW4C2_10", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WL1END3_10", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WL1END0_10", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW2A0_10", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2END0_10", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE4C3_10", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE2BEG1_10", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_LH7_10", + "VBRK_LH7" + ], + [ + "CMT_TOP_EL1BEG1_10", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE4C2_10", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH10_10", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4B1_10", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4C0_10", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH12_10", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_10", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4BEG3_10", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW2END2_10", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW4A2_10", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG3_10", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE4A1_10", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_SW2A0_10", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE2BEG0_10", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE2A0_10", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH5_10", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW2A3_10", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW2A1_10", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WR1END2_10", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SW4END1_10", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW2A3_10", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SW4END2_10", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_LH3_10", + "VBRK_LH3" + ], + [ + "CMT_TOP_EL1BEG0_10", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4END0_10", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A1_10", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SE4BEG2_10", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4C2_10", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WR1END3_10", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WR1END1_10", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NW4A0_10", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_10", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW4B1_10", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C2_10", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE4BEG3_10", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4BEG1_10", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EE4C1_10", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG2_10", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG3_10", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE4BEG3_10", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE2A1_10", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_LH11_10", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE4A3_10", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SE4C1_10", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WL1END1_10", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW4B0_10", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2A2_10", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4BEG1_10", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW4A0_10", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END1_10", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_ER1BEG3_10", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WW4END2_10", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_ER1BEG0_10", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_10", + "VBRK_LH1" + ], + [ + "CMT_TOP_WW4C3_10", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END0_10", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW4END3_10", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_LH9_10", + "VBRK_LH9" + ], + [ + "CMT_TOP_NW2A2_10", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_10", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_LH6_10", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A0_10", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE2A2_10", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2BEG2_10", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW2END1_10", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4B0_10", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C1_10", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SW2A2_10", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG2_10", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_NE2A0_10", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE2A1_10", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_10", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW2A0_10", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4A2_10", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW4A1_10", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WR1END0_10", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4B2_10", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END0_10", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4C0_10", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_10", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4B3_10", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4A0_10", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END3_10", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WL1END2_10", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4A2_10", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4B3_10", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NE4C1_10", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A1_10", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2A2_10", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EE4C3_10", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_MONITOR_N_10", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW4A2_10", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NE4BEG2_10", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_SW2A1_10", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4BEG0_10", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SE2A0_10", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4BEG1_10", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_10", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_10", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4END3_10", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE2A2_10", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SE4C3_10", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4A3_10", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_LH2_10", + "VBRK_LH2" + ], + [ + "CMT_TOP_ER1BEG2_10", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NE2A3_10", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2A3_10", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C0_10", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_ER1BEG1_10", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_MONITOR_P_10", + "VBRK_MONITOR_P" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "EE4B1", + "INT_INTERFACE_EE4A1" + ], + [ + "WW4B0", + "INT_INTERFACE_WW4C0" + ], + [ + "IMUX_L12", + "PCIE_INT_INTERFACE_IMUX_L12" + ], + [ + "LOGIC_OUTS_L5", + "INT_INTERFACE_LOGIC_OUTS_L5" + ], + [ + "SE2END0", + "INT_INTERFACE_SE2A0" + ], + [ + "LOGIC_OUTS_L17", + "INT_INTERFACE_LOGIC_OUTS_L17" + ], + [ + "ER1END3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "BYP_L2", + "INT_INTERFACE_BYP2" + ], + [ + "EE2A2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "NW6BEG3", + "INT_INTERFACE_NW4A3" + ], + [ + "IMUX_L40", + "PCIE_INT_INTERFACE_IMUX_L40" + ], + [ + "NE6A3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "SW6E0", + "INT_INTERFACE_SW4END0" + ], + [ + "NE6END3", + "INT_INTERFACE_NE4C3" + ], + [ + "LOGIC_OUTS_L14", + "INT_INTERFACE_LOGIC_OUTS_L14" + ], + [ + "NW2A3", + "INT_INTERFACE_NW2A3" + ], + [ + "WW2BEG3", + "INT_INTERFACE_WW2A3" + ], + [ + "EE4A3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "IMUX_L24", + "PCIE_INT_INTERFACE_IMUX_L24" + ], + [ + "IMUX_L16", + "PCIE_INT_INTERFACE_IMUX_L16" + ], + [ + "BYP_L7", + "INT_INTERFACE_BYP7" + ], + [ + "IMUX_L1", + "PCIE_INT_INTERFACE_IMUX_L1" + ], + [ + "SW6E3", + "INT_INTERFACE_SW4END3" + ], + [ + "WW4C2", + "INT_INTERFACE_WW4END2" + ], + [ + "IMUX_L3", + "PCIE_INT_INTERFACE_IMUX_L3" + ], + [ + "IMUX_L42", + "PCIE_INT_INTERFACE_IMUX_L42" + ], + [ + "IMUX_L46", + "PCIE_INT_INTERFACE_IMUX_L46" + ], + [ + "WW2BEG1", + "INT_INTERFACE_WW2A1" + ], + [ + "BYP_L0", + "INT_INTERFACE_BYP0" + ], + [ + "LH7", + "INT_INTERFACE_LH8" + ], + [ + "LOGIC_OUTS_L3", + "INT_INTERFACE_LOGIC_OUTS_L3" + ], + [ + "SW2A1", + "INT_INTERFACE_SW2A1" + ], + [ + "NE6A0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "WW2A1", + "INT_INTERFACE_WW2END1" + ], + [ + "LOGIC_OUTS_L4", + "INT_INTERFACE_LOGIC_OUTS_L4" + ], + [ + "IMUX_L23", + "PCIE_INT_INTERFACE_IMUX_L23" + ], + [ + "EE4END1", + "INT_INTERFACE_EE4C1" + ], + [ + "LOGIC_OUTS_L15", + "INT_INTERFACE_LOGIC_OUTS_L15" + ], + [ + "IMUX_L5", + "PCIE_INT_INTERFACE_IMUX_L5" + ], + [ + "EL1END2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "EE4C3", + "INT_INTERFACE_EE4B3" + ], + [ + "IMUX_L22", + "PCIE_INT_INTERFACE_IMUX_L22" + ], + [ + "LOGIC_OUTS_L22", + "INT_INTERFACE_LOGIC_OUTS_L22" + ], + [ + "EE4A1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "ER1END1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "SE6A2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "IMUX_L27", + "PCIE_INT_INTERFACE_IMUX_L27" + ], + [ + "NW6E2", + "INT_INTERFACE_NW4END2" + ], + [ + "WW4A3", + "INT_INTERFACE_WW4B3" + ], + [ + "SW6E1", + "INT_INTERFACE_SW4END1" + ], + [ + "NE6A2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "LH8", + "INT_INTERFACE_LH9" + ], + [ + "FAN_L7", + "INT_INTERFACE_FAN7" + ], + [ + "LH10", + "INT_INTERFACE_LH11" + ], + [ + "BYP_L6", + "INT_INTERFACE_BYP6" + ], + [ + "SW6BEG3", + "INT_INTERFACE_SW4A3" + ], + [ + "NW6BEG0", + "INT_INTERFACE_NW4A0" + ], + [ + "EE4END3", + "INT_INTERFACE_EE4C3" + ], + [ + "BYP_L1", + "INT_INTERFACE_BYP1" + ], + [ + "NE2END2", + "INT_INTERFACE_NE2A2" + ], + [ + "LH6", + "INT_INTERFACE_LH7" + ], + [ + "WW4BEG2", + "INT_INTERFACE_WW4A2" + ], + [ + "LOGIC_OUTS_L8", + "INT_INTERFACE_LOGIC_OUTS_L8" + ], + [ + "WL1BEG3", + "INT_INTERFACE_WL1END3" + ], + [ + "EE2END3", + "INT_INTERFACE_EE2A3" + ], + [ + "LH1", + "INT_INTERFACE_LH2" + ], + [ + "WL1BEG2", + "INT_INTERFACE_WL1END2" + ], + [ + "NW6BEG1", + "INT_INTERFACE_NW4A1" + ], + [ + "WR1BEG3", + "INT_INTERFACE_WR1END3" + ], + [ + "WW4C3", + "INT_INTERFACE_WW4END3" + ], + [ + "SE6END3", + "INT_INTERFACE_SE4C3" + ], + [ + "LOGIC_OUTS_L13", + "INT_INTERFACE_LOGIC_OUTS_L13" + ], + [ + "WR1BEG0", + "INT_INTERFACE_WR1END0" + ], + [ + "EE4B0", + "INT_INTERFACE_EE4A0" + ], + [ + "LOGIC_OUTS_L19", + "INT_INTERFACE_LOGIC_OUTS_L19" + ], + [ + "NW6E3", + "INT_INTERFACE_NW4END3" + ], + [ + "IMUX_L17", + "PCIE_INT_INTERFACE_IMUX_L17" + ], + [ + "LOGIC_OUTS_L10", + "INT_INTERFACE_LOGIC_OUTS_L10" + ], + [ + "WL1BEG0", + "INT_INTERFACE_WL1END0" + ], + [ + "NW6BEG2", + "INT_INTERFACE_NW4A2" + ], + [ + "IMUX_L4", + "PCIE_INT_INTERFACE_IMUX_L4" + ], + [ + "IMUX_L36", + "PCIE_INT_INTERFACE_IMUX_L36" + ], + [ + "SE6END0", + "INT_INTERFACE_SE4C0" + ], + [ + "IMUX_L21", + "PCIE_INT_INTERFACE_IMUX_L21" + ], + [ + "FAN_L5", + "INT_INTERFACE_FAN5" + ], + [ + "SW6BEG0", + "INT_INTERFACE_SW4A0" + ], + [ + "LOGIC_OUTS_L12", + "INT_INTERFACE_LOGIC_OUTS_L12" + ], + [ + "IMUX_L35", + "PCIE_INT_INTERFACE_IMUX_L35" + ], + [ + "SE6A0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "SE6A3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "IMUX_L10", + "PCIE_INT_INTERFACE_IMUX_L10" + ], + [ + "WW4BEG0", + "INT_INTERFACE_WW4A0" + ], + [ + "SW2A3", + "INT_INTERFACE_SW2A3" + ], + [ + "IMUX_L39", + "PCIE_INT_INTERFACE_IMUX_L39" + ], + [ + "LH3", + "INT_INTERFACE_LH4" + ], + [ + "SE6END1", + "INT_INTERFACE_SE4C1" + ], + [ + "LOGIC_OUTS_L2", + "INT_INTERFACE_LOGIC_OUTS_L2" + ], + [ + "NW6E1", + "INT_INTERFACE_NW4END1" + ], + [ + "WW2BEG2", + "INT_INTERFACE_WW2A2" + ], + [ + "IMUX_L30", + "PCIE_INT_INTERFACE_IMUX_L30" + ], + [ + "CLK_L1", + "INT_INTERFACE_CLK1" + ], + [ + "EE4A0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "FAN_L0", + "INT_INTERFACE_FAN0" + ], + [ + "SE6A1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "WW4A1", + "INT_INTERFACE_WW4B1" + ], + [ + "ER1END0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "IMUX_L47", + "PCIE_INT_INTERFACE_IMUX_L47" + ], + [ + "FAN_L1", + "INT_INTERFACE_FAN1" + ], + [ + "EE4END2", + "INT_INTERFACE_EE4C2" + ], + [ + "EL1END0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "LH5", + "INT_INTERFACE_LH6" + ], + [ + "IMUX_L8", + "PCIE_INT_INTERFACE_IMUX_L8" + ], + [ + "EE2A3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "EE2END2", + "INT_INTERFACE_EE2A2" + ], + [ + "IMUX_L44", + "PCIE_INT_INTERFACE_IMUX_L44" + ], + [ + "LOGIC_OUTS_L7", + "INT_INTERFACE_LOGIC_OUTS_L7" + ], + [ + "SW6BEG2", + "INT_INTERFACE_SW4A2" + ], + [ + "EL1END3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "IMUX_L2", + "PCIE_INT_INTERFACE_IMUX_L2" + ], + [ + "WW2A2", + "INT_INTERFACE_WW2END2" + ], + [ + "LH2", + "INT_INTERFACE_LH3" + ], + [ + "WR1BEG2", + "INT_INTERFACE_WR1END2" + ], + [ + "WL1BEG1", + "INT_INTERFACE_WL1END1" + ], + [ + "EE4C0", + "INT_INTERFACE_EE4B0" + ], + [ + "EE4B3", + "INT_INTERFACE_EE4A3" + ], + [ + "WW4A0", + "INT_INTERFACE_WW4B0" + ], + [ + "EL1END1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "NE2END1", + "INT_INTERFACE_NE2A1" + ], + [ + "LOGIC_OUTS_L23", + "INT_INTERFACE_LOGIC_OUTS_L23" + ], + [ + "WW2A3", + "INT_INTERFACE_WW2END3" + ], + [ + "IMUX_L38", + "PCIE_INT_INTERFACE_IMUX_L38" + ], + [ + "IMUX_L13", + "PCIE_INT_INTERFACE_IMUX_L13" + ], + [ + "SW6E2", + "INT_INTERFACE_SW4END2" + ], + [ + "BYP_L4", + "INT_INTERFACE_BYP4" + ], + [ + "MONITOR_P", + "INT_INTERFACE_MONITOR_P" + ], + [ + "EE4END0", + "INT_INTERFACE_EE4C0" + ], + [ + "IMUX_L28", + "PCIE_INT_INTERFACE_IMUX_L28" + ], + [ + "WR1BEG1", + "INT_INTERFACE_WR1END1" + ], + [ + "EE2A0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "WW4C1", + "INT_INTERFACE_WW4END1" + ], + [ + "CTRL_L1", + "INT_INTERFACE_CTRL1" + ], + [ + "BYP_L3", + "INT_INTERFACE_BYP3" + ], + [ + "LOGIC_OUTS_L20", + "INT_INTERFACE_LOGIC_OUTS_L20" + ], + [ + "SE2END3", + "INT_INTERFACE_SE2A3" + ], + [ + "NE6END1", + "INT_INTERFACE_NE4C1" + ], + [ + "MONITOR_N", + "INT_INTERFACE_MONITOR_N" + ], + [ + "LOGIC_OUTS_L0", + "INT_INTERFACE_LOGIC_OUTS_L0" + ], + [ + "IMUX_L25", + "PCIE_INT_INTERFACE_IMUX_L25" + ], + [ + "LOGIC_OUTS_L18", + "INT_INTERFACE_LOGIC_OUTS_L18" + ], + [ + "WW4A2", + "INT_INTERFACE_WW4B2" + ], + [ + "LH11", + "INT_INTERFACE_LH12" + ], + [ + "WW4BEG1", + "INT_INTERFACE_WW4A1" + ], + [ + "NE6END0", + "INT_INTERFACE_NE4C0" + ], + [ + "IMUX_L7", + "PCIE_INT_INTERFACE_IMUX_L7" + ], + [ + "EE2END0", + "INT_INTERFACE_EE2A0" + ], + [ + "LOGIC_OUTS_L21", + "INT_INTERFACE_LOGIC_OUTS_L21" + ], + [ + "IMUX_L14", + "PCIE_INT_INTERFACE_IMUX_L14" + ], + [ + "EE4A2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "IMUX_L9", + "PCIE_INT_INTERFACE_IMUX_L9" + ], + [ + "IMUX_L26", + "PCIE_INT_INTERFACE_IMUX_L26" + ], + [ + "LH0", + "INT_INTERFACE_LH1" + ], + [ + "WW2A0", + "INT_INTERFACE_WW2END0" + ], + [ + "IMUX_L31", + "PCIE_INT_INTERFACE_IMUX_L31" + ], + [ + "WW4B1", + "INT_INTERFACE_WW4C1" + ], + [ + "EE2A1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "WW4BEG3", + "INT_INTERFACE_WW4A3" + ], + [ + "LOGIC_OUTS_L6", + "INT_INTERFACE_LOGIC_OUTS_L6" + ], + [ + "IMUX_L20", + "PCIE_INT_INTERFACE_IMUX_L20" + ], + [ + "SE2END2", + "INT_INTERFACE_SE2A2" + ], + [ + "IMUX_L34", + "PCIE_INT_INTERFACE_IMUX_L34" + ], + [ + "EE4C1", + "INT_INTERFACE_EE4B1" + ], + [ + "EE4C2", + "INT_INTERFACE_EE4B2" + ], + [ + "IMUX_L0", + "PCIE_INT_INTERFACE_IMUX_L0" + ], + [ + "CLK_L0", + "INT_INTERFACE_CLK0" + ], + [ + "IMUX_L15", + "PCIE_INT_INTERFACE_IMUX_L15" + ], + [ + "FAN_L4", + "INT_INTERFACE_FAN4" + ], + [ + "LOGIC_OUTS_L16", + "INT_INTERFACE_LOGIC_OUTS_L16" + ], + [ + "EE4B2", + "INT_INTERFACE_EE4A2" + ], + [ + "ER1END2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "WW4B2", + "INT_INTERFACE_WW4C2" + ], + [ + "BYP_L5", + "INT_INTERFACE_BYP5" + ], + [ + "LH4", + "INT_INTERFACE_LH5" + ], + [ + "IMUX_L19", + "PCIE_INT_INTERFACE_IMUX_L19" + ], + [ + "LOGIC_OUTS_L1", + "INT_INTERFACE_LOGIC_OUTS_L1" + ], + [ + "LOGIC_OUTS_L9", + "INT_INTERFACE_LOGIC_OUTS_L9" + ], + [ + "IMUX_L11", + "PCIE_INT_INTERFACE_IMUX_L11" + ], + [ + "NW2A2", + "INT_INTERFACE_NW2A2" + ], + [ + "WW2BEG0", + "INT_INTERFACE_WW2A0" + ], + [ + "NW2A0", + "INT_INTERFACE_NW2A0" + ], + [ + "IMUX_L18", + "PCIE_INT_INTERFACE_IMUX_L18" + ], + [ + "IMUX_L32", + "PCIE_INT_INTERFACE_IMUX_L32" + ], + [ + "SE2END1", + "INT_INTERFACE_SE2A1" + ], + [ + "IMUX_L43", + "PCIE_INT_INTERFACE_IMUX_L43" + ], + [ + "WW4C0", + "INT_INTERFACE_WW4END0" + ], + [ + "IMUX_L29", + "PCIE_INT_INTERFACE_IMUX_L29" + ], + [ + "SW2A2", + "INT_INTERFACE_SW2A2" + ], + [ + "FAN_L2", + "INT_INTERFACE_FAN2" + ], + [ + "NE2END0", + "INT_INTERFACE_NE2A0" + ], + [ + "NE6END2", + "INT_INTERFACE_NE4C2" + ], + [ + "IMUX_L37", + "PCIE_INT_INTERFACE_IMUX_L37" + ], + [ + "LOGIC_OUTS_L11", + "INT_INTERFACE_LOGIC_OUTS_L11" + ], + [ + "FAN_L6", + "INT_INTERFACE_FAN6" + ], + [ + "WW4B3", + "INT_INTERFACE_WW4C3" + ], + [ + "IMUX_L33", + "PCIE_INT_INTERFACE_IMUX_L33" + ], + [ + "SW2A0", + "INT_INTERFACE_SW2A0" + ], + [ + "SW6BEG1", + "INT_INTERFACE_SW4A1" + ], + [ + "NE6A1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "NE2END3", + "INT_INTERFACE_NE2A3" + ], + [ + "IMUX_L41", + "PCIE_INT_INTERFACE_IMUX_L41" + ], + [ + "IMUX_L45", + "PCIE_INT_INTERFACE_IMUX_L45" + ], + [ + "EE2END1", + "INT_INTERFACE_EE2A1" + ], + [ + "CTRL_L0", + "INT_INTERFACE_CTRL0" + ], + [ + "IMUX_L6", + "PCIE_INT_INTERFACE_IMUX_L6" + ], + [ + "LH9", + "INT_INTERFACE_LH10" + ], + [ + "NW2A1", + "INT_INTERFACE_NW2A1" + ], + [ + "SE6END2", + "INT_INTERFACE_SE4C2" + ], + [ + "FAN_L3", + "INT_INTERFACE_FAN3" + ], + [ + "NW6E0", + "INT_INTERFACE_NW4END0" + ] + ], + "tile_types": [ + "INT_L", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLK_FEED_EE4B1", + "VBRK_EE4B1" + ], + [ + "CLK_FEED_SE4C1", + "VBRK_SE4C1" + ], + [ + "CLK_FEED_EE2BEG0", + "VBRK_EE2BEG0" + ], + [ + "CLK_FEED_SW2A1", + "VBRK_SW2A1" + ], + [ + "CLK_FEED_WR1END1", + "VBRK_WR1END1" + ], + [ + "CLK_FEED_WL1END3", + "VBRK_WL1END3" + ], + [ + "CLK_FEED_NE2A2", + "VBRK_NE2A2" + ], + [ + "CLK_FEED_WW2END0", + "VBRK_WW2END0" + ], + [ + "CLK_FEED_LH9", + "VBRK_LH9" + ], + [ + "CLK_FEED_EE4C1", + "VBRK_EE4C1" + ], + [ + "CLK_FEED_NW2A0", + "VBRK_NW2A0" + ], + [ + "CLK_FEED_WW4A1", + "VBRK_WW4A1" + ], + [ + "CLK_FEED_NE2A1", + "VBRK_NE2A1" + ], + [ + "CLK_FEED_WW4A3", + "VBRK_WW4A3" + ], + [ + "CLK_FEED_WW2END1", + "VBRK_WW2END1" + ], + [ + "CLK_FEED_WW4C3", + "VBRK_WW4C3" + ], + [ + "CLK_FEED_LH5", + "VBRK_LH5" + ], + [ + "CLK_FEED_LH10", + "VBRK_LH10" + ], + [ + "CLK_FEED_LH12", + "VBRK_LH12" + ], + [ + "CLK_FEED_EE4B0", + "VBRK_EE4B0" + ], + [ + "CLK_FEED_EE4A2", + "VBRK_EE4A2" + ], + [ + "CLK_FEED_WW4END2", + "VBRK_WW4END2" + ], + [ + "CLK_FEED_NE4C2", + "VBRK_NE4C2" + ], + [ + "CLK_FEED_NW4A1", + "VBRK_NW4A1" + ], + [ + "CLK_FEED_SW4A2", + "VBRK_SW4A2" + ], + [ + "CLK_FEED_NW4END0", + "VBRK_NW4END0" + ], + [ + "CLK_FEED_WW2END3", + "VBRK_WW2END3" + ], + [ + "CLK_FEED_WW4C1", + "VBRK_WW4C1" + ], + [ + "CLK_FEED_SW2A0", + "VBRK_SW2A0" + ], + [ + "CLK_FEED_SW4A0", + "VBRK_SW4A0" + ], + [ + "CLK_FEED_NE4BEG3", + "VBRK_NE4BEG3" + ], + [ + "CLK_FEED_ER1BEG0", + "VBRK_ER1BEG0" + ], + [ + "CLK_FEED_EE2BEG2", + "VBRK_EE2BEG2" + ], + [ + "CLK_FEED_WW4B3", + "VBRK_WW4B3" + ], + [ + "CLK_FEED_WW2A3", + "VBRK_WW2A3" + ], + [ + "CLK_FEED_WW4C2", + "VBRK_WW4C2" + ], + [ + "CLK_FEED_LH8", + "VBRK_LH8" + ], + [ + "CLK_FEED_NE4C0", + "VBRK_NE4C0" + ], + [ + "CLK_FEED_EL1BEG3", + "VBRK_EL1BEG3" + ], + [ + "CLK_FEED_LH1", + "VBRK_LH1" + ], + [ + "CLK_FEED_EL1BEG0", + "VBRK_EL1BEG0" + ], + [ + "CLK_FEED_EE4A1", + "VBRK_EE4A1" + ], + [ + "CLK_FEED_SW2A2", + "VBRK_SW2A2" + ], + [ + "CLK_FEED_SE4C3", + "VBRK_SE4C3" + ], + [ + "CLK_FEED_EE4BEG0", + "VBRK_EE4BEG0" + ], + [ + "CLK_FEED_LH4", + "VBRK_LH4" + ], + [ + "CLK_FEED_NW4A2", + "VBRK_NW4A2" + ], + [ + "CLK_FEED_EE2BEG3", + "VBRK_EE2BEG3" + ], + [ + "CLK_FEED_SE4BEG0", + "VBRK_SE4BEG0" + ], + [ + "CLK_FEED_SE4BEG3", + "VBRK_SE4BEG3" + ], + [ + "CLK_FEED_WW4END0", + "VBRK_WW4END0" + ], + [ + "CLK_FEED_EE4B3", + "VBRK_EE4B3" + ], + [ + "CLK_FEED_SW4A3", + "VBRK_SW4A3" + ], + [ + "CLK_FEED_WL1END0", + "VBRK_WL1END0" + ], + [ + "CLK_FEED_WW2A1", + "VBRK_WW2A1" + ], + [ + "CLK_FEED_NE4C1", + "VBRK_NE4C1" + ], + [ + "CLK_FEED_WW2END2", + "VBRK_WW2END2" + ], + [ + "CLK_FEED_EE2A0", + "VBRK_EE2A0" + ], + [ + "CLK_FEED_SE4C2", + "VBRK_SE4C2" + ], + [ + "CLK_FEED_SW4END1", + "VBRK_SW4END1" + ], + [ + "CLK_FEED_EE4BEG2", + "VBRK_EE4BEG2" + ], + [ + "CLK_FEED_WL1END2", + "VBRK_WL1END2" + ], + [ + "CLK_FEED_EL1BEG2", + "VBRK_EL1BEG2" + ], + [ + "CLK_FEED_EE4BEG1", + "VBRK_EE4BEG1" + ], + [ + "CLK_FEED_WR1END3", + "VBRK_WR1END3" + ], + [ + "CLK_FEED_EE4C2", + "VBRK_EE4C2" + ], + [ + "CLK_FEED_NW4A3", + "VBRK_NW4A3" + ], + [ + "CLK_FEED_SW4END0", + "VBRK_SW4END0" + ], + [ + "CLK_FEED_WR1END0", + "VBRK_WR1END0" + ], + [ + "CLK_FEED_SE2A1", + "VBRK_SE2A1" + ], + [ + "CLK_FEED_WW4END3", + "VBRK_WW4END3" + ], + [ + "CLK_FEED_NW2A3", + "VBRK_NW2A3" + ], + [ + "CLK_FEED_WR1END2", + "VBRK_WR1END2" + ], + [ + "CLK_FEED_NW4END1", + "VBRK_NW4END1" + ], + [ + "CLK_FEED_LH11", + "VBRK_LH11" + ], + [ + "CLK_FEED_WW4B0", + "VBRK_WW4B0" + ], + [ + "CLK_FEED_NW4A0", + "VBRK_NW4A0" + ], + [ + "CLK_FEED_MONITOR_P", + "VBRK_MONITOR_P" + ], + [ + "CLK_FEED_NW2A1", + "VBRK_NW2A1" + ], + [ + "CLK_FEED_EE4A0", + "VBRK_EE4A0" + ], + [ + "CLK_FEED_NE4C3", + "VBRK_NE4C3" + ], + [ + "CLK_FEED_EE2A1", + "VBRK_EE2A1" + ], + [ + "CLK_FEED_LH6", + "VBRK_LH6" + ], + [ + "CLK_FEED_LH7", + "VBRK_LH7" + ], + [ + "CLK_FEED_WW4B2", + "VBRK_WW4B2" + ], + [ + "CLK_FEED_SW4END2", + "VBRK_SW4END2" + ], + [ + "CLK_FEED_WW4B1", + "VBRK_WW4B1" + ], + [ + "CLK_FEED_NW4END2", + "VBRK_NW4END2" + ], + [ + "CLK_FEED_WL1END1", + "VBRK_WL1END1" + ], + [ + "CLK_FEED_SW4A1", + "VBRK_SW4A1" + ], + [ + "CLK_FEED_NE2A0", + "VBRK_NE2A0" + ], + [ + "CLK_FEED_NW2A2", + "VBRK_NW2A2" + ], + [ + "CLK_FEED_WW2A0", + "VBRK_WW2A0" + ], + [ + "CLK_FEED_EE2A3", + "VBRK_EE2A3" + ], + [ + "CLK_FEED_WW2A2", + "VBRK_WW2A2" + ], + [ + "CLK_FEED_LH2", + "VBRK_LH2" + ], + [ + "CLK_FEED_EE4C3", + "VBRK_EE4C3" + ], + [ + "CLK_FEED_WW4END1", + "VBRK_WW4END1" + ], + [ + "CLK_FEED_NE4BEG0", + "VBRK_NE4BEG0" + ], + [ + "CLK_FEED_NW4END3", + "VBRK_NW4END3" + ], + [ + "CLK_FEED_SW2A3", + "VBRK_SW2A3" + ], + [ + "CLK_FEED_EE2A2", + "VBRK_EE2A2" + ], + [ + "CLK_FEED_EE4B2", + "VBRK_EE4B2" + ], + [ + "CLK_FEED_WW4A2", + "VBRK_WW4A2" + ], + [ + "CLK_FEED_ER1BEG2", + "VBRK_ER1BEG2" + ], + [ + "CLK_FEED_EE4BEG3", + "VBRK_EE4BEG3" + ], + [ + "CLK_FEED_EE4C0", + "VBRK_EE4C0" + ], + [ + "CLK_FEED_MONITOR_N", + "VBRK_MONITOR_N" + ], + [ + "CLK_FEED_NE4BEG2", + "VBRK_NE4BEG2" + ], + [ + "CLK_FEED_SW4END3", + "VBRK_SW4END3" + ], + [ + "CLK_FEED_WW4A0", + "VBRK_WW4A0" + ], + [ + "CLK_FEED_NE4BEG1", + "VBRK_NE4BEG1" + ], + [ + "CLK_FEED_SE2A0", + "VBRK_SE2A0" + ], + [ + "CLK_FEED_EE2BEG1", + "VBRK_EE2BEG1" + ], + [ + "CLK_FEED_ER1BEG3", + "VBRK_ER1BEG3" + ], + [ + "CLK_FEED_LH3", + "VBRK_LH3" + ], + [ + "CLK_FEED_ER1BEG1", + "VBRK_ER1BEG1" + ], + [ + "CLK_FEED_EL1BEG1", + "VBRK_EL1BEG1" + ], + [ + "CLK_FEED_SE4C0", + "VBRK_SE4C0" + ], + [ + "CLK_FEED_SE4BEG1", + "VBRK_SE4BEG1" + ], + [ + "CLK_FEED_SE2A2", + "VBRK_SE2A2" + ], + [ + "CLK_FEED_EE4A3", + "VBRK_EE4A3" + ], + [ + "CLK_FEED_SE2A3", + "VBRK_SE2A3" + ], + [ + "CLK_FEED_WW4C0", + "VBRK_WW4C0" + ], + [ + "CLK_FEED_SE4BEG2", + "VBRK_SE4BEG2" + ], + [ + "CLK_FEED_NE2A3", + "VBRK_NE2A3" + ] + ], + "tile_types": [ + "CLK_PMV2", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B23_9", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_LOGIC_OUTS_B4_9", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B7_9", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B8_9", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX0_9", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX42_9", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX38_9", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_LOGIC_OUTS_B3_9", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX13_9", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX10_9", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B15_9", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_FAN2_9", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_BYP4_9", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX27_9", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_BYP2_9", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_FAN1_9", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX40_9", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX44_9", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_CLK1_9", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_LOGIC_OUTS_B2_9", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX14_9", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX11_9", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX3_9", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX47_9", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_LOGIC_OUTS_B11_9", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_FAN3_9", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX33_9", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_FAN5_9", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_BYP1_9", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B20_9", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX8_9", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX20_9", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX34_9", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX18_9", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX1_9", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_LOGIC_OUTS_B18_9", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX5_9", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B19_9", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_BYP3_9", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B14_9", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX30_9", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX15_9", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_BYP6_9", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX43_9", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX23_9", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX7_9", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX26_9", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX9_9", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX46_9", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_LOGIC_OUTS_B0_9", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX29_9", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX4_9", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX6_9", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX22_9", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B9_9", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_LOGIC_OUTS_B10_9", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX21_9", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_FAN6_9", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_BYP0_9", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX39_9", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX16_9", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX35_9", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_FAN0_9", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_LOGIC_OUTS_B16_9", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B6_9", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_LOGIC_OUTS_B21_9", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_LOGIC_OUTS_B13_9", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_CTRL0_9", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX28_9", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_LOGIC_OUTS_B17_9", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_CLK0_9", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_FAN4_9", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_FAN7_9", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX45_9", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX36_9", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX2_9", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_BYP5_9", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX41_9", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B5_9", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_LOGIC_OUTS_B12_9", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX31_9", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B1_9", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_CTRL1_9", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX17_9", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX24_9", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX12_9", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX32_9", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B22_9", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_BYP7_9", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX25_9", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX19_9", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX37_9", + "VBRK_EXT_IMUX37" + ] + ], + "tile_types": [ + "GTX_CHANNEL_2", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLBLM_L_CIN", + "HCLK_CLB_COUT1_L" + ], + [ + "CLBLM_M_CIN", + "HCLK_CLB_COUT0_L" + ] + ], + "tile_types": [ + "CLBLM_L", + "HCLK_CLB" + ] + }, + { + "grid_deltas": [ + -1, + -7 + ], + "wire_pairs": [ + [ + "CMT_TOP_EL1BEG1_8", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG1_8", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NW4A0_8", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4B0_8", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_8", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW2A0_8", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW2A0_8", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4BEG2_8", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_NE4C0_8", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_ER1BEG2_8", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_8", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_LH12_8", + "VBRK_LH12" + ], + [ + "CMT_TOP_EL1BEG2_8", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_LH1_8", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH10_8", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW4B1_8", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG2_8", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW4A3_8", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4C3_8", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_NW2A0_8", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NW4END0_8", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE2A2_8", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4C1_8", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW4C2_8", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW4A1_8", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NW2A1_8", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SE4BEG0_8", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_8", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_LH3_8", + "VBRK_LH3" + ], + [ + "CMT_TOP_WR1END2_8", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A0_8", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4A2_8", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END1_8", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A0_8", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A1_8", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EL1BEG0_8", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_EE4A3_8", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C3_8", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_LH4_8", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE4A0_8", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END1_8", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2A0_8", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH2_8", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4C1_8", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NE2A2_8", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2A3_8", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_NW4A3_8", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4END2_8", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE2A1_8", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END2_8", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2END0_8", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2BEG0_8", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4C0_8", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG0_8", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_WR1END0_8", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_SE4C2_8", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4END1_8", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NE2A1_8", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4B3_8", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_8", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C2_8", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4B1_8", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW2A3_8", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SE4C1_8", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WR1END3_8", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW2A2_8", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C0_8", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4C1_8", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH11_8", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4B2_8", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW2A3_8", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NW4END2_8", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A0_8", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WR1END1_8", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH5_8", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END3_8", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH6_8", + "VBRK_LH6" + ], + [ + "CMT_TOP_NE4BEG3_8", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_LH8_8", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A1_8", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE2BEG2_8", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4C3_8", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NW2A2_8", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END3_8", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE2A3_8", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_ER1BEG1_8", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_8", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_NE4BEG1_8", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_WW4A2_8", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG0_8", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NE4C2_8", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SE4BEG3_8", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C0_8", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_8", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2BEG3_8", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH9_8", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE4B2_8", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_WL1END0_8", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_WW2END3_8", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EL1BEG3_8", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG3_8", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4BEG3_8", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WL1END1_8", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2A1_8", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SE4BEG2_8", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW2A3_8", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SE4C3_8", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE2A2_8", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_8", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4A1_8", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW4A2_8", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SW2A2_8", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_NW4END3_8", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SW4END1_8", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END3_8", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4BEG1_8", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4END2_8", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH7_8", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4BEG0_8", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2BEG1_8", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_8", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A3_8", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WL1END2_8", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A0_8", + "VBRK_WW4A0" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "PCIE_FAN7_R_11", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_WW2A3_11", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_NW2A2_11", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_11", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_11", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_SE4BEG2_11", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_SE4C1_11", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_IMUX23_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_SW4END0_11", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_IMUX13_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_NE4BEG2_11", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_NW4A1_11", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_SW4A2_11", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_EE4B0_11", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_WW2END2_11", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_WW4END2_11", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_LH5_11", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_WW4A0_11", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_EE2BEG1_11", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_11", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_WW2END3_11", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_NE4C2_11", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_IMUX9_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_IMUX24_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_IMUX26_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_IMUX18_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_WW4A3_11", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_EE4B3_11", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_IMUX35_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_CLK1_R_11", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_SE4BEG3_11", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_WW4END1_11", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_EE4BEG2_11", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX47_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_11", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_NW4END0_11", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_IMUX0_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_11", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_SE2A0_11", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_CTRL0_R_11", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_WR1END1_11", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_SW4END2_11", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_LH2_11", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_IMUX43_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_IMUX1_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_NW2A1_11", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_SW2A3_11", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX22_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_SW2A1_11", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_EE2A0_11", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_WW2A1_11", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_IMUX41_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_EE2BEG3_11", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_SE4C2_11", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_SE2A1_11", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_CLK0_R_11", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_FAN6_R_11", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_BYP1_R_11", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_EL1BEG0_11", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_WR1END3_11", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_IMUX46_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_LH8_11", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_11", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_11", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_BYP3_R_11", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_WW4A2_11", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_NE2A2_11", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_11", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_WW4C0_11", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_EE4A0_11", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_IMUX27_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_FAN5_R_11", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_WW4C2_11", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_EE4BEG0_11", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX20_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_CTRL1_R_11", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_IMUX32_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_11", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_11", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_NE4C1_11", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_EE4A2_11", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_EE2A1_11", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_LH9_11", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_EE4C3_11", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_IMUX37_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_LH12_11", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_IMUX39_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_EE4BEG3_11", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_WR1END2_11", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_SW4A0_11", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_FAN4_R_11", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_SE2A2_11", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_IMUX16_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_11", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_IMUX40_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_WR1END0_11", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_11", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_EE4BEG1_11", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_EL1BEG1_11", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_LH7_11", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_FAN2_R_11", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_NE4BEG0_11", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_IMUX33_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_WW4B2_11", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_IMUX42_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_IMUX10_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_SW4A3_11", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_WL1END3_11", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_EE2A3_11", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_NW4A3_11", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_WW2END1_11", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_FAN0_R_11", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_EE4A3_11", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_WL1END1_11", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_IMUX4_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_IMUX45_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_SE4C0_11", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_WW2A2_11", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_11", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_WW4END0_11", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_NW2A3_11", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_11", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_IMUX21_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_SE4BEG1_11", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_IMUX5_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_IMUX7_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_WW4B0_11", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_IMUX36_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_WW4END3_11", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_LH3_11", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_IMUX25_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_SW4A1_11", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_NW4A2_11", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_FAN3_R_11", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_WW2A0_11", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_EE2A2_11", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_LH11_11", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_EE4C0_11", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_WW4B3_11", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_11", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_WL1END2_11", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_MONITOR_P_11", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_IMUX2_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_WW2END0_11", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_LH4_11", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_SE2A3_11", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_11", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_NE4BEG3_11", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_IMUX28_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_SW4END3_11", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_ER1BEG3_11", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_IMUX38_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_ER1BEG0_11", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_11", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_NE2A1_11", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_IMUX3_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_NE2A3_11", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_FAN1_R_11", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_IMUX15_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_WW4C3_11", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_BYP6_R_11", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_WW4A1_11", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_EE4B1_11", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_SW4END1_11", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_EE4B2_11", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_IMUX12_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_WW4B1_11", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_NE4C3_11", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_NW2A0_11", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_IMUX29_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_11", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_BYP5_R_11", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_SE4BEG0_11", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_EL1BEG2_11", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_11", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_EE2BEG2_11", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_EE4C2_11", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_NE4C0_11", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_BYP0_R_11", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_BYP4_R_11", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_11", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_EE4C1_11", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_EE2BEG0_11", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_ER1BEG2_11", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_11", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_11", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_IMUX31_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_LH6_11", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_NW4A0_11", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_SW2A2_11", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_BYP2_R_11", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_IMUX30_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_WW4C1_11", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_MONITOR_N_11", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_11", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_SW2A0_11", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX8_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_NW4END1_11", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_IMUX14_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_NW4END3_11", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_ER1BEG1_11", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_EE4A1_11", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_IMUX11_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_NW4END2_11", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_EL1BEG3_11", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_LH10_11", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_LH1_11", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_IMUX19_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_IMUX34_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_IMUX44_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_SE4C3_11", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_BYP7_R_11", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_WL1END0_11", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_11", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_NE2A0_11", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_NE4BEG1_11", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX6_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_IMUX17_R_11", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "WW4A3", + "WW4BEG3" + ], + [ + "EE4BEG2", + "EE4A2" + ], + [ + "GCLK_L_B10_EAST", + "GCLK_B10" + ], + [ + "WW2END2", + "WW2A2" + ], + [ + "NE6BEG2", + "NE6A2" + ], + [ + "EL1BEG0", + "EL1END0" + ], + [ + "GCLK_L_B6_EAST", + "GCLK_B6" + ], + [ + "SW6A3", + "SW6BEG3" + ], + [ + "ER1BEG0", + "ER1END0" + ], + [ + "EE4C2", + "EE4END2" + ], + [ + "GCLK_L_B8_EAST", + "GCLK_B8" + ], + [ + "EL1BEG1", + "EL1END1" + ], + [ + "NW6A1", + "NW6BEG1" + ], + [ + "WW4END0", + "WW4C0" + ], + [ + "LH7", + "LH6" + ], + [ + "EL1BEG3", + "EL1END3" + ], + [ + "NE6BEG3", + "NE6A3" + ], + [ + "WL1END2", + "WL1BEG2" + ], + [ + "GCLK_L_B1", + "GCLK_B1_WEST" + ], + [ + "WW4B2", + "WW4A2" + ], + [ + "WW4A0", + "WW4BEG0" + ], + [ + "LH11", + "LH10" + ], + [ + "WW4B1", + "WW4A1" + ], + [ + "LH2", + "LH1" + ], + [ + "NE6BEG1", + "NE6A1" + ], + [ + "LH1", + "LH0" + ], + [ + "SE2A1", + "SE2END1" + ], + [ + "LH3", + "LH2" + ], + [ + "INT_PHASER_TO_IO_OCLK1X_90", + "INT_PHASER_TO_IO_OCLK1X_90" + ], + [ + "SE6E3", + "SE6END3" + ], + [ + "SW2END0", + "SW2A0" + ], + [ + "SE6BEG0", + "SE6A0" + ], + [ + "SE6BEG1", + "SE6A1" + ], + [ + "WW4C2", + "WW4B2" + ], + [ + "MONITOR_N", + "MONITOR_N" + ], + [ + "ER1BEG3", + "ER1END3" + ], + [ + "EE4B1", + "EE4C1" + ], + [ + "WW2A2", + "WW2BEG2" + ], + [ + "GCLK_L_B11_EAST", + "GCLK_B11" + ], + [ + "NW6END3", + "NW6E3" + ], + [ + "EE4C1", + "EE4END1" + ], + [ + "LH8", + "LH7" + ], + [ + "EE2A0", + "EE2END0" + ], + [ + "NW6END2", + "NW6E2" + ], + [ + "SW6A0", + "SW6BEG0" + ], + [ + "SE6BEG2", + "SE6A2" + ], + [ + "NE2A1", + "NE2END1" + ], + [ + "WW2A1", + "WW2BEG1" + ], + [ + "EE2A3", + "EE2END3" + ], + [ + "SE6E2", + "SE6END2" + ], + [ + "ER1BEG2", + "ER1END2" + ], + [ + "WW2END0", + "WW2A0" + ], + [ + "GCLK_L_B0", + "GCLK_B0_WEST" + ], + [ + "WW4END3", + "WW4C3" + ], + [ + "LH12", + "LH11" + ], + [ + "NW2END0", + "NW2A0" + ], + [ + "EE4C0", + "EE4END0" + ], + [ + "WW4C3", + "WW4B3" + ], + [ + "NE2A3", + "NE2END3" + ], + [ + "GCLK_L_B7_EAST", + "GCLK_B7" + ], + [ + "GCLK_L_B3", + "GCLK_B3_WEST" + ], + [ + "EE4A2", + "EE4B2" + ], + [ + "NW6A3", + "NW6BEG3" + ], + [ + "SE2A0", + "SE2END0" + ], + [ + "EE4B3", + "EE4C3" + ], + [ + "NW2END2", + "NW2A2" + ], + [ + "INT_DQS_IOTOPHASER", + "INT_DQS_IOTOPHASER" + ], + [ + "NE6E0", + "NE6END0" + ], + [ + "EE2BEG3", + "EE2A3" + ], + [ + "NE6E1", + "NE6END1" + ], + [ + "NE6E2", + "NE6END2" + ], + [ + "SE6BEG3", + "SE6A3" + ], + [ + "WR1END3", + "WR1BEG3" + ], + [ + "LH10", + "LH9" + ], + [ + "EE4BEG1", + "EE4A1" + ], + [ + "WW4B0", + "WW4A0" + ], + [ + "WW4END2", + "WW4C2" + ], + [ + "SW6END2", + "SW6E2" + ], + [ + "LH6", + "LH5" + ], + [ + "WW2END3", + "WW2A3" + ], + [ + "WL1END0", + "WL1BEG0" + ], + [ + "WR1END0", + "WR1BEG0" + ], + [ + "MONITOR_P", + "MONITOR_P" + ], + [ + "WR1END2", + "WR1BEG2" + ], + [ + "SW6A2", + "SW6BEG2" + ], + [ + "WW2A0", + "WW2BEG0" + ], + [ + "SE6E0", + "SE6END0" + ], + [ + "EE4BEG0", + "EE4A0" + ], + [ + "WW4C1", + "WW4B1" + ], + [ + "NE6E3", + "NE6END3" + ], + [ + "EE2A1", + "EE2END1" + ], + [ + "INT_PHASER_TO_IO_ICLKDIV", + "INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "WW2END1", + "WW2A1" + ], + [ + "EL1BEG2", + "EL1END2" + ], + [ + "EE4A0", + "EE4B0" + ], + [ + "NW6END0", + "NW6E0" + ], + [ + "NW6END1", + "NW6E1" + ], + [ + "GCLK_L_B4", + "GCLK_B4_WEST" + ], + [ + "SE2A3", + "SE2END3" + ], + [ + "SW2END1", + "SW2A1" + ], + [ + "EE4A3", + "EE4B3" + ], + [ + "NW2END3", + "NW2A3" + ], + [ + "ER1BEG1", + "ER1END1" + ], + [ + "WW2A3", + "WW2BEG3" + ], + [ + "INT_PHASER_TO_IO_ICLK", + "INT_PHASER_TO_IO_ICLK" + ], + [ + "EE2BEG0", + "EE2A0" + ], + [ + "EE4C3", + "EE4END3" + ], + [ + "EE4BEG3", + "EE4A3" + ], + [ + "LH4", + "LH3" + ], + [ + "EE2BEG1", + "EE2A1" + ], + [ + "NW6A0", + "NW6BEG0" + ], + [ + "WW4A1", + "WW4BEG1" + ], + [ + "WW4A2", + "WW4BEG2" + ], + [ + "SW2END3", + "SW2A3" + ], + [ + "SW6END0", + "SW6E0" + ], + [ + "WL1END3", + "WL1BEG3" + ], + [ + "SE6E1", + "SE6END1" + ], + [ + "LH9", + "LH8" + ], + [ + "WR1END1", + "WR1BEG1" + ], + [ + "LH5", + "LH4" + ], + [ + "GCLK_L_B9_EAST", + "GCLK_B9" + ], + [ + "WW4C0", + "WW4B0" + ], + [ + "GCLK_L_B2", + "GCLK_B2_WEST" + ], + [ + "SW6END3", + "SW6E3" + ], + [ + "EE2BEG2", + "EE2A2" + ], + [ + "EE4B2", + "EE4C2" + ], + [ + "SW6END1", + "SW6E1" + ], + [ + "WW4END1", + "WW4C1" + ], + [ + "EE4A1", + "EE4B1" + ], + [ + "NE2A2", + "NE2END2" + ], + [ + "EE2A2", + "EE2END2" + ], + [ + "SW6A1", + "SW6BEG1" + ], + [ + "NE6BEG0", + "NE6A0" + ], + [ + "WW4B3", + "WW4A3" + ], + [ + "NW6A2", + "NW6BEG2" + ], + [ + "EE4B0", + "EE4C0" + ], + [ + "WL1END1", + "WL1BEG1" + ], + [ + "GCLK_L_B5", + "GCLK_B5_WEST" + ], + [ + "NE2A0", + "NE2END0" + ], + [ + "INT_PHASER_TO_IO_OCLK", + "INT_PHASER_TO_IO_OCLK" + ], + [ + "SW2END2", + "SW2A2" + ], + [ + "NW2END1", + "NW2A1" + ], + [ + "INT_PHASER_TO_IO_OCLKDIV", + "INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "SE2A2", + "SE2END2" + ] + ], + "tile_types": [ + "INT_L", + "INT_R" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CMT_TOP_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH1_2", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH2_2", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_LH6_2", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_LH7_2", + "VBRK_LH7" + ], + [ + "CMT_TOP_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH12_2", + "VBRK_LH12" + ], + [ + "CMT_TOP_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_LH11_2", + "VBRK_LH11" + ], + [ + "CMT_TOP_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4B3_2", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH4_2", + "VBRK_LH4" + ], + [ + "CMT_TOP_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_LH5_2", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH3_2", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH10_2", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH8_2", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_LH9_2", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW2A2_2", + "VBRK_NW2A2" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "CMT_TOP_EL1BEG1_8", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG1_8", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NW4A0_8", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4B0_8", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_8", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW2A0_8", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW2A0_8", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4BEG2_8", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_MONITOR_P_8", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_NE4C0_8", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_ER1BEG2_8", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_8", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_LH12_8", + "VBRK_LH12" + ], + [ + "CMT_TOP_EL1BEG2_8", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_LH1_8", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH10_8", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW4B1_8", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG2_8", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW4A3_8", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4C3_8", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_MONITOR_N_8", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW2A0_8", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NW4END0_8", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE2A2_8", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4C1_8", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW4C2_8", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW4A1_8", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NW2A1_8", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SE4BEG0_8", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_8", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_LH3_8", + "VBRK_LH3" + ], + [ + "CMT_TOP_WR1END2_8", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A0_8", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4A2_8", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END1_8", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A0_8", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A1_8", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EL1BEG0_8", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_EE4A3_8", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C3_8", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_LH4_8", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE4A0_8", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END1_8", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2A0_8", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH2_8", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4C1_8", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NE2A2_8", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2A3_8", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_NW4A3_8", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4END2_8", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE2A1_8", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END2_8", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2END0_8", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2BEG0_8", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4C0_8", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG0_8", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_WR1END0_8", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_SE4C2_8", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4END1_8", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NE2A1_8", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4B3_8", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_8", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C2_8", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4B1_8", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW2A3_8", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SE4C1_8", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WR1END3_8", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW2A2_8", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C0_8", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4C1_8", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH11_8", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4B2_8", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW2A3_8", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NW4END2_8", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A0_8", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WR1END1_8", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH5_8", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END3_8", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH6_8", + "VBRK_LH6" + ], + [ + "CMT_TOP_NE4BEG3_8", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_LH8_8", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A1_8", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE2BEG2_8", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4C3_8", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NW2A2_8", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END3_8", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE2A3_8", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_ER1BEG1_8", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_8", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_NE4BEG1_8", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_WW4A2_8", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG0_8", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NE4C2_8", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SE4BEG3_8", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C0_8", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_8", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2BEG3_8", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH9_8", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE4B2_8", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_WL1END0_8", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_WW2END3_8", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EL1BEG3_8", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG3_8", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4BEG3_8", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WL1END1_8", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2A1_8", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SE4BEG2_8", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW2A3_8", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SE4C3_8", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE2A2_8", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_8", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4A1_8", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW4A2_8", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SW2A2_8", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_NW4END3_8", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SW4END1_8", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END3_8", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4BEG1_8", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4END2_8", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH7_8", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4BEG0_8", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2BEG1_8", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_8", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A3_8", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WL1END2_8", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A0_8", + "VBRK_WW4A0" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "CLK_HROW_LH10_2", + "VBRK_LH10" + ], + [ + "CLK_HROW_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_LH11_2", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH7_2", + "VBRK_LH7" + ], + [ + "CLK_HROW_MONITOR_N_2", + "VBRK_MONITOR_N" + ], + [ + "CLK_HROW_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_LH1_2", + "VBRK_LH1" + ], + [ + "CLK_HROW_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_LH8_2", + "VBRK_LH8" + ], + [ + "CLK_HROW_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_LH12_2", + "VBRK_LH12" + ], + [ + "CLK_HROW_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_LH4_2", + "VBRK_LH4" + ], + [ + "CLK_HROW_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_LH5_2", + "VBRK_LH5" + ], + [ + "CLK_HROW_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_NW2A2_2", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_LH9_2", + "VBRK_LH9" + ], + [ + "CLK_HROW_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_LH2_2", + "VBRK_LH2" + ], + [ + "CLK_HROW_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_LH3_2", + "VBRK_LH3" + ], + [ + "CLK_HROW_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_MONITOR_P_2", + "VBRK_MONITOR_P" + ], + [ + "CLK_HROW_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_LH6_2", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE4B3_2", + "VBRK_EE4B3" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_INT_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CK_INOUT_L6", + "HCLK_CK_OUTIN_R2" + ], + [ + "HCLK_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_INT_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CK_INOUT_L4", + "HCLK_CK_OUTIN_R0" + ], + [ + "HCLK_CK_INOUT_L5", + "HCLK_CK_OUTIN_R1" + ], + [ + "HCLK_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CK_INOUT_L0", + "HCLK_CK_OUTIN_R4" + ], + [ + "HCLK_CK_INOUT_L3", + "HCLK_CK_OUTIN_R7" + ], + [ + "HCLK_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CK_INOUT_L7", + "HCLK_CK_OUTIN_R3" + ], + [ + "HCLK_CK_OUTIN_L1", + "HCLK_CK_INOUT_R1" + ], + [ + "HCLK_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_INT_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_INT_PERFCLK3", + "HCLK_INT_PERFCLK3" + ], + [ + "HCLK_CK_OUTIN_L2", + "HCLK_CK_INOUT_R2" + ], + [ + "HCLK_CK_INOUT_L1", + "HCLK_CK_OUTIN_R5" + ], + [ + "HCLK_CK_OUTIN_L4", + "HCLK_CK_INOUT_R4" + ], + [ + "HCLK_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CK_OUTIN_L7", + "HCLK_CK_INOUT_R7" + ], + [ + "HCLK_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CK_OUTIN_L0", + "HCLK_CK_INOUT_R0" + ], + [ + "HCLK_CK_OUTIN_L3", + "HCLK_CK_INOUT_R3" + ], + [ + "HCLK_CK_OUTIN_L5", + "HCLK_CK_INOUT_R5" + ], + [ + "HCLK_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CCIO3", + "HCLK_CCIO3" + ], + [ + "HCLK_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CCIO1", + "HCLK_CCIO1" + ], + [ + "HCLK_CCIO2", + "HCLK_CCIO2" + ], + [ + "HCLK_CK_INOUT_L2", + "HCLK_CK_OUTIN_R6" + ], + [ + "HCLK_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CCIO0", + "HCLK_CCIO0" + ], + [ + "HCLK_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CK_OUTIN_L6", + "HCLK_CK_INOUT_R6" + ] + ], + "tile_types": [ + "HCLK_L", + "HCLK_R" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SW4A3_11", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_SE4C3_11", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_BYP7_11", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B11_11", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "CFG_CENTER_IMUX37_11", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_EE4BEG0_11", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_SE2A1_11", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_CTRL1_11", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_IMUX4_11", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX23_11", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_IMUX13_11", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_IMUX2_11", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_11", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_NE2A1_11", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_NW2A3_11", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_LH7_11", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_WW2A0_11", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_IMUX30_11", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_IMUX39_11", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_IMUX27_11", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_SW2A2_11", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_IMUX3_11", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_CLK0_11", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX17_11", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_WL1END0_11", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_EE4B1_11", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_11", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_EE4A1_11", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_WW4C1_11", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_ER1BEG1_11", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SW2A1_11", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WW4B2_11", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_WW2END2_11", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_BYP5_11", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_WW4END2_11", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX20_11", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_ER1BEG2_11", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_SE4C0_11", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_IMUX32_11", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_SW4A2_11", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NW4END0_11", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX18_11", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_EL1BEG0_11", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_WL1END3_11", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_LH9_11", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_WL1END1_11", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_WW2END0_11", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_IMUX1_11", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_WW4END0_11", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_SW4END0_11", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_ER1BEG0_11", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_IMUX44_11", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_EE4A3_11", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_SE4C2_11", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_BYP6_11", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX31_11", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_CLK1_11", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX0_11", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_IMUX22_11", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WR1END1_11", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NW4A3_11", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_EE4B2_11", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_NW4A1_11", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_BYP1_11", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW2A2_11", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_IMUX41_11", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_LH12_11", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX42_11", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_SE4BEG0_11", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_11", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_EE2BEG1_11", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_EE2A1_11", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_EE2BEG0_11", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_WL1END2_11", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_11", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_WW4B3_11", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_IMUX29_11", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_WW4END3_11", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX43_11", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX21_11", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_EE4A2_11", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_EE4C1_11", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_EL1BEG2_11", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX36_11", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_EE4BEG3_11", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX33_11", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_NE4C2_11", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_FAN0_11", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_FAN5_11", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SE2A3_11", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_WR1END0_11", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_SE4BEG3_11", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_LH6_11", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_NE2A0_11", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_SE2A0_11", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_NE4C3_11", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_BYP3_11", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_IMUX40_11", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_NW2A0_11", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_NE4BEG0_11", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX45_11", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_WW4B0_11", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_NE4C0_11", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE4B0_11", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_SW2A0_11", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_SE4BEG2_11", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE4C2_11", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_BYP0_11", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_NW4A0_11", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_WW4C0_11", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_EE2A3_11", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EL1BEG3_11", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_IMUX46_11", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_LH8_11", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_WW4C3_11", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX6_11", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_EE4A0_11", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_IMUX47_11", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_WW4A2_11", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_EE2A2_11", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_IMUX14_11", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_11", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_LH4_11", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_WW2A3_11", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_LH2_11", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX5_11", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_EE4B3_11", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_BYP2_11", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_FAN2_11", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_IMUX25_11", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_FAN6_11", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_11", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_IMUX10_11", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SE2A2_11", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_EE4C0_11", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_EE4BEG2_11", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_WW2A1_11", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_LH11_11", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_SW4END2_11", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_NW4A2_11", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_BYP4_11", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_NW2A2_11", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_NE2A2_11", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE2BEG2_11", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_11", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_SW2A3_11", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_IMUX8_11", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_FAN3_11", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_IMUX24_11", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_11", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_WW2END3_11", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_IMUX28_11", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_LH5_11", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX16_11", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_FAN4_11", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_NE4C1_11", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_IMUX7_11", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_EE2BEG3_11", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX38_11", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_CTRL0_11", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_WW4END1_11", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_NW4END3_11", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_NW2A1_11", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_WR1END3_11", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_NE4BEG3_11", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NE4BEG1_11", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX35_11", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_NE2A3_11", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_11", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_EE4C3_11", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_WW4A3_11", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_SW4A0_11", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_NW4END2_11", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_FAN1_11", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_WW4A0_11", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_SW4END3_11", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX26_11", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_LH1_11", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_IMUX15_11", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_ER1BEG3_11", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_EE4BEG1_11", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_WW4A1_11", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_SE4BEG1_11", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE2A0_11", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_IMUX19_11", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_IMUX11_11", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_WW4C2_11", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX12_11", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_WW2END1_11", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_WW4B1_11", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_11", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_IMUX9_11", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_SW4A1_11", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_LH3_11", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_11", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_NE4BEG2_11", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG1_11", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_FAN7_11", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_LH10_11", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_NW4END1_11", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SW4END1_11", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_WR1END2_11", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SE4C1_11", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX34_11", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_11", + "VFRAME_LOGIC_OUTS_B15" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLK_FEED_EE4B1", + "VBRK_EE4B1" + ], + [ + "CLK_FEED_SE4C1", + "VBRK_SE4C1" + ], + [ + "CLK_FEED_EE2BEG0", + "VBRK_EE2BEG0" + ], + [ + "CLK_FEED_SW2A1", + "VBRK_SW2A1" + ], + [ + "CLK_FEED_WR1END1", + "VBRK_WR1END1" + ], + [ + "CLK_FEED_WL1END3", + "VBRK_WL1END3" + ], + [ + "CLK_FEED_NE2A2", + "VBRK_NE2A2" + ], + [ + "CLK_FEED_WW2END0", + "VBRK_WW2END0" + ], + [ + "CLK_FEED_LH9", + "VBRK_LH9" + ], + [ + "CLK_FEED_EE4C1", + "VBRK_EE4C1" + ], + [ + "CLK_FEED_NW2A0", + "VBRK_NW2A0" + ], + [ + "CLK_FEED_WW4A1", + "VBRK_WW4A1" + ], + [ + "CLK_FEED_NE2A1", + "VBRK_NE2A1" + ], + [ + "CLK_FEED_WW4A3", + "VBRK_WW4A3" + ], + [ + "CLK_FEED_WW2END1", + "VBRK_WW2END1" + ], + [ + "CLK_FEED_WW4C3", + "VBRK_WW4C3" + ], + [ + "CLK_FEED_LH5", + "VBRK_LH5" + ], + [ + "CLK_FEED_LH10", + "VBRK_LH10" + ], + [ + "CLK_FEED_LH12", + "VBRK_LH12" + ], + [ + "CLK_FEED_EE4B0", + "VBRK_EE4B0" + ], + [ + "CLK_FEED_EE4A2", + "VBRK_EE4A2" + ], + [ + "CLK_FEED_WW4END2", + "VBRK_WW4END2" + ], + [ + "CLK_FEED_NE4C2", + "VBRK_NE4C2" + ], + [ + "CLK_FEED_NW4A1", + "VBRK_NW4A1" + ], + [ + "CLK_FEED_SW4A2", + "VBRK_SW4A2" + ], + [ + "CLK_FEED_NW4END0", + "VBRK_NW4END0" + ], + [ + "CLK_FEED_WW2END3", + "VBRK_WW2END3" + ], + [ + "CLK_FEED_WW4C1", + "VBRK_WW4C1" + ], + [ + "CLK_FEED_SW2A0", + "VBRK_SW2A0" + ], + [ + "CLK_FEED_SW4A0", + "VBRK_SW4A0" + ], + [ + "CLK_FEED_NE4BEG3", + "VBRK_NE4BEG3" + ], + [ + "CLK_FEED_ER1BEG0", + "VBRK_ER1BEG0" + ], + [ + "CLK_FEED_EE2BEG2", + "VBRK_EE2BEG2" + ], + [ + "CLK_FEED_WW4B3", + "VBRK_WW4B3" + ], + [ + "CLK_FEED_WW2A3", + "VBRK_WW2A3" + ], + [ + "CLK_FEED_WW4C2", + "VBRK_WW4C2" + ], + [ + "CLK_FEED_LH8", + "VBRK_LH8" + ], + [ + "CLK_FEED_NE4C0", + "VBRK_NE4C0" + ], + [ + "CLK_FEED_EL1BEG3", + "VBRK_EL1BEG3" + ], + [ + "CLK_FEED_LH1", + "VBRK_LH1" + ], + [ + "CLK_FEED_EL1BEG0", + "VBRK_EL1BEG0" + ], + [ + "CLK_FEED_EE4A1", + "VBRK_EE4A1" + ], + [ + "CLK_FEED_SW2A2", + "VBRK_SW2A2" + ], + [ + "CLK_FEED_SE4C3", + "VBRK_SE4C3" + ], + [ + "CLK_FEED_EE4BEG0", + "VBRK_EE4BEG0" + ], + [ + "CLK_FEED_LH4", + "VBRK_LH4" + ], + [ + "CLK_FEED_NW4A2", + "VBRK_NW4A2" + ], + [ + "CLK_FEED_EE2BEG3", + "VBRK_EE2BEG3" + ], + [ + "CLK_FEED_SE4BEG0", + "VBRK_SE4BEG0" + ], + [ + "CLK_FEED_SE4BEG3", + "VBRK_SE4BEG3" + ], + [ + "CLK_FEED_WW4END0", + "VBRK_WW4END0" + ], + [ + "CLK_FEED_EE4B3", + "VBRK_EE4B3" + ], + [ + "CLK_FEED_WL1END0", + "VBRK_WL1END0" + ], + [ + "CLK_FEED_SW4A3", + "VBRK_SW4A3" + ], + [ + "CLK_FEED_WW2A1", + "VBRK_WW2A1" + ], + [ + "CLK_FEED_NE4C1", + "VBRK_NE4C1" + ], + [ + "CLK_FEED_WW2END2", + "VBRK_WW2END2" + ], + [ + "CLK_FEED_EE2A0", + "VBRK_EE2A0" + ], + [ + "CLK_FEED_SE4C2", + "VBRK_SE4C2" + ], + [ + "CLK_FEED_SW4END1", + "VBRK_SW4END1" + ], + [ + "CLK_FEED_EE4BEG2", + "VBRK_EE4BEG2" + ], + [ + "CLK_FEED_WL1END2", + "VBRK_WL1END2" + ], + [ + "CLK_FEED_EL1BEG2", + "VBRK_EL1BEG2" + ], + [ + "CLK_FEED_EE4BEG1", + "VBRK_EE4BEG1" + ], + [ + "CLK_FEED_WR1END3", + "VBRK_WR1END3" + ], + [ + "CLK_FEED_EE4C2", + "VBRK_EE4C2" + ], + [ + "CLK_FEED_NW4A3", + "VBRK_NW4A3" + ], + [ + "CLK_FEED_SW4END0", + "VBRK_SW4END0" + ], + [ + "CLK_FEED_WR1END0", + "VBRK_WR1END0" + ], + [ + "CLK_FEED_SE2A1", + "VBRK_SE2A1" + ], + [ + "CLK_FEED_WW4END3", + "VBRK_WW4END3" + ], + [ + "CLK_FEED_NW2A3", + "VBRK_NW2A3" + ], + [ + "CLK_FEED_WR1END2", + "VBRK_WR1END2" + ], + [ + "CLK_FEED_NW4END1", + "VBRK_NW4END1" + ], + [ + "CLK_FEED_LH11", + "VBRK_LH11" + ], + [ + "CLK_FEED_WW4B0", + "VBRK_WW4B0" + ], + [ + "CLK_FEED_NW4A0", + "VBRK_NW4A0" + ], + [ + "CLK_FEED_NW2A1", + "VBRK_NW2A1" + ], + [ + "CLK_FEED_MONITOR_P", + "VBRK_MONITOR_P" + ], + [ + "CLK_FEED_EE4A0", + "VBRK_EE4A0" + ], + [ + "CLK_FEED_NE4C3", + "VBRK_NE4C3" + ], + [ + "CLK_FEED_EE2A1", + "VBRK_EE2A1" + ], + [ + "CLK_FEED_LH6", + "VBRK_LH6" + ], + [ + "CLK_FEED_LH7", + "VBRK_LH7" + ], + [ + "CLK_FEED_WW4B2", + "VBRK_WW4B2" + ], + [ + "CLK_FEED_SW4END2", + "VBRK_SW4END2" + ], + [ + "CLK_FEED_WW4B1", + "VBRK_WW4B1" + ], + [ + "CLK_FEED_NW4END2", + "VBRK_NW4END2" + ], + [ + "CLK_FEED_WL1END1", + "VBRK_WL1END1" + ], + [ + "CLK_FEED_SW4A1", + "VBRK_SW4A1" + ], + [ + "CLK_FEED_NE2A0", + "VBRK_NE2A0" + ], + [ + "CLK_FEED_NW2A2", + "VBRK_NW2A2" + ], + [ + "CLK_FEED_WW2A0", + "VBRK_WW2A0" + ], + [ + "CLK_FEED_EE2A3", + "VBRK_EE2A3" + ], + [ + "CLK_FEED_WW2A2", + "VBRK_WW2A2" + ], + [ + "CLK_FEED_LH2", + "VBRK_LH2" + ], + [ + "CLK_FEED_EE4C3", + "VBRK_EE4C3" + ], + [ + "CLK_FEED_WW4END1", + "VBRK_WW4END1" + ], + [ + "CLK_FEED_NE4BEG0", + "VBRK_NE4BEG0" + ], + [ + "CLK_FEED_NW4END3", + "VBRK_NW4END3" + ], + [ + "CLK_FEED_SW2A3", + "VBRK_SW2A3" + ], + [ + "CLK_FEED_EE2A2", + "VBRK_EE2A2" + ], + [ + "CLK_FEED_EE4B2", + "VBRK_EE4B2" + ], + [ + "CLK_FEED_WW4A2", + "VBRK_WW4A2" + ], + [ + "CLK_FEED_ER1BEG2", + "VBRK_ER1BEG2" + ], + [ + "CLK_FEED_EE4BEG3", + "VBRK_EE4BEG3" + ], + [ + "CLK_FEED_EE4C0", + "VBRK_EE4C0" + ], + [ + "CLK_FEED_MONITOR_N", + "VBRK_MONITOR_N" + ], + [ + "CLK_FEED_NE4BEG2", + "VBRK_NE4BEG2" + ], + [ + "CLK_FEED_SW4END3", + "VBRK_SW4END3" + ], + [ + "CLK_FEED_WW4A0", + "VBRK_WW4A0" + ], + [ + "CLK_FEED_NE4BEG1", + "VBRK_NE4BEG1" + ], + [ + "CLK_FEED_SE2A0", + "VBRK_SE2A0" + ], + [ + "CLK_FEED_EE2BEG1", + "VBRK_EE2BEG1" + ], + [ + "CLK_FEED_ER1BEG3", + "VBRK_ER1BEG3" + ], + [ + "CLK_FEED_LH3", + "VBRK_LH3" + ], + [ + "CLK_FEED_ER1BEG1", + "VBRK_ER1BEG1" + ], + [ + "CLK_FEED_EL1BEG1", + "VBRK_EL1BEG1" + ], + [ + "CLK_FEED_SE4C0", + "VBRK_SE4C0" + ], + [ + "CLK_FEED_SE4BEG1", + "VBRK_SE4BEG1" + ], + [ + "CLK_FEED_SE2A2", + "VBRK_SE2A2" + ], + [ + "CLK_FEED_EE4A3", + "VBRK_EE4A3" + ], + [ + "CLK_FEED_SE2A3", + "VBRK_SE2A3" + ], + [ + "CLK_FEED_WW4C0", + "VBRK_WW4C0" + ], + [ + "CLK_FEED_SE4BEG2", + "VBRK_SE4BEG2" + ], + [ + "CLK_FEED_NE2A3", + "VBRK_NE2A3" + ] + ], + "tile_types": [ + "CLK_FEED", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "IOB_PD_INT_EN_0", + "RIOI_PD_INT_EN_0" + ], + [ + "IOB_DIFF_TERM_INT_EN", + "RIOI_DIFF_TERM_INT_EN" + ], + [ + "IOB_PU_INT_EN_1", + "RIOI_PU_INT_EN_1" + ], + [ + "IOB_KEEPER_INT_EN_0", + "RIOI_KEEPER_INT_EN_0" + ], + [ + "IOB_O0", + "RIOI_O0" + ], + [ + "IOB_KEEPER_INT_EN_1", + "RIOI_KEEPER_INT_EN_1" + ], + [ + "IOB_DCI_T_TERM0", + "RIOI_DCI_T_TERM0" + ], + [ + "IOB_PD_INT_EN_1", + "RIOI_PD_INT_EN_1" + ], + [ + "IOB_T1", + "RIOI_T1" + ], + [ + "IOB_O1", + "RIOI_O1" + ], + [ + "IOB_IBUF_DISABLE1", + "RIOI_IBUF_DISABLE1" + ], + [ + "RIOB_MONITOR_N", + "IOI_MONITOR_N" + ], + [ + "IOB_IBUF1", + "RIOI_IBUF1" + ], + [ + "IOB_IBUF_DISABLE0", + "RIOI_IBUF_DISABLE0" + ], + [ + "IOB_DCI_T_TERM1", + "RIOI_DCI_T_TERM1" + ], + [ + "IOB_IBUF0", + "RIOI_IBUF0" + ], + [ + "IOB_PU_INT_EN_0", + "RIOI_PU_INT_EN_0" + ], + [ + "IOB_T0", + "RIOI_T0" + ], + [ + "RIOB_MONITOR_P", + "IOI_MONITOR_P" + ] + ], + "tile_types": [ + "RIOB18", + "RIOI_TBYTETERM" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX21_2", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX41_2", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_BYP5_2", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX20_2", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX39_2", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B4_2", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_FAN4_2", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX31_2", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX2_2", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_FAN0_2", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_LOGIC_OUTS_B18_2", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX26_2", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX6_2", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B2_2", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX3_2", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_FAN5_2", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_LOGIC_OUTS_B22_2", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B3_2", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_LOGIC_OUTS_B6_2", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_LOGIC_OUTS_B8_2", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX16_2", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX32_2", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B9_2", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_BYP3_2", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX17_2", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX30_2", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_LOGIC_OUTS_B23_2", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX13_2", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_LOGIC_OUTS_B0_2", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX9_2", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX1_2", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_FAN3_2", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN6_2", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX18_2", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX27_2", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B7_2", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_BYP6_2", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX46_2", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP7_2", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX36_2", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_LOGIC_OUTS_B13_2", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B21_2", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_IMUX33_2", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX34_2", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX35_2", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_CTRL0_2", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX37_2", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_BYP4_2", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX5_2", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX44_2", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_FAN1_2", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_BYP1_2", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX12_2", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX0_2", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX29_2", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_LOGIC_OUTS_B16_2", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B11_2", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_CLK0_2", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX45_2", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX10_2", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B5_2", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_LOGIC_OUTS_B17_2", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX23_2", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_LOGIC_OUTS_B20_2", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX7_2", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX24_2", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX47_2", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX28_2", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX4_2", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX11_2", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP0_2", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_CTRL1_2", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX8_2", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX22_2", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX14_2", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_LOGIC_OUTS_B10_2", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_FAN2_2", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX43_2", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_FAN7_2", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX42_2", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_CLK1_2", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_BYP2_2", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX38_2", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX40_2", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX15_2", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX19_2", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX25_2", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B1_2", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_2", + "VBRK_EXT_LOGIC_OUTS_B19" + ] + ], + "tile_types": [ + "GTX_CHANNEL_2", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "GTXE2_COMMON_MGT_CLK0", + "HCLK_TERM_GTX_CK_IN4" + ], + [ + "GTXE2_COMMON_MGT_CLK8", + "HCLK_TERM_GTX_CK_IN12" + ], + [ + "GTXE2_COMMON_MGT_CLK2", + "HCLK_TERM_GTX_CK_IN6" + ], + [ + "GTXE2_COMMON_MGT_CLK5", + "HCLK_TERM_GTX_CK_IN9" + ], + [ + "GTXE2_COMMON_MGT_CLK1", + "HCLK_TERM_GTX_CK_IN5" + ], + [ + "GTXE2_COMMON_MGT_CLK7", + "HCLK_TERM_GTX_CK_IN11" + ], + [ + "GTXE2_COMMON_MGT_CLK6", + "HCLK_TERM_GTX_CK_IN10" + ], + [ + "GTXE2_COMMON_MGT_CLK9", + "HCLK_TERM_GTX_CK_IN13" + ], + [ + "GTXE2_COMMON_MGT_CLK4", + "HCLK_TERM_GTX_CK_IN8" + ], + [ + "GTXE2_COMMON_MGT_CLK3", + "HCLK_TERM_GTX_CK_IN7" + ] + ], + "tile_types": [ + "GTX_COMMON", + "HCLK_TERM_GTX" + ] + }, + { + "grid_deltas": [ + 0, + -10 + ], + "wire_pairs": [ + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA14", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA14" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA26", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA26" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA30", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA30" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA20", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA20" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA31", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA31" + ], + [ + "CFG_CENTER_MID_DNA_PORT_CLK", + "CFG_CENTER_TOP_DNA_PORT_CLK" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA24", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA24" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA13", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA13" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA11", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA11" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA27", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA27" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA15", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA15" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA29", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA29" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA12", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA12" + ], + [ + "CFG_CENTER_MID_ICAP1_CLK", + "CFG_CENTER_TOP_ICAP1_CLK" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA17", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA17" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA19", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA19" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA28", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA28" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA21", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA21" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA18", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA18" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA25", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA25" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA16", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA16" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA22", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA22" + ], + [ + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA23", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA23" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "CFG_CENTER_TOP" + ] + }, + { + "grid_deltas": [ + 0, + -2 + ], + "wire_pairs": [ + [ + "IOI_IOCLK1", + "IOI_SING_IOCLK1" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_SING_LEAF_GCLK2" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_SING_RCLK_FORIO3" + ], + [ + "IOI_IOCLK3", + "IOI_SING_IOCLK3" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_SING_LEAF_GCLK4" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_SING_RCLK_FORIO2" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_SING_LEAF_GCLK5" + ], + [ + "IOI_TBYTEIN", + "IOI_SING_TBYTEIN" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_SING_LEAF_GCLK1" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_SING_RCLK_FORIO1" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_SING_LEAF_GCLK3" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_SING_RCLK_FORIO0" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_SING_LEAF_GCLK0" + ], + [ + "IOI_IOCLK0", + "IOI_SING_IOCLK0" + ], + [ + "IOI_IOCLK2", + "IOI_SING_IOCLK2" + ] + ], + "tile_types": [ + "LIOI3", + "LIOI3_SING" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4A3_10", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SE2A3_10", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG0_10", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END2_10", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW4C0_10", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_LH8_10", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4B2_10", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A1_10", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW4C2_10", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WL1END3_10", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WL1END0_10", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW2A0_10", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2END0_10", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE4C3_10", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE2BEG1_10", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_LH7_10", + "VBRK_LH7" + ], + [ + "CMT_TOP_EL1BEG1_10", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE4C2_10", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH10_10", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4B1_10", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4C0_10", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH12_10", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_10", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4BEG3_10", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW2END2_10", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW4A2_10", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG3_10", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE4A1_10", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_SW2A0_10", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE2BEG0_10", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE2A0_10", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH5_10", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW2A3_10", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW2A1_10", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WR1END2_10", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SW4END1_10", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW2A3_10", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SW4END2_10", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_LH3_10", + "VBRK_LH3" + ], + [ + "CMT_TOP_EL1BEG0_10", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4END0_10", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A1_10", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SE4BEG2_10", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4C2_10", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WR1END3_10", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WR1END1_10", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NW4A0_10", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_10", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW4B1_10", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C2_10", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE4BEG3_10", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4BEG1_10", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EE4C1_10", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG2_10", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG3_10", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE4BEG3_10", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE2A1_10", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_LH11_10", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE4A3_10", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SE4C1_10", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WL1END1_10", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW4B0_10", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2A2_10", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4BEG1_10", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW4A0_10", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END1_10", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_ER1BEG3_10", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WW4END2_10", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_ER1BEG0_10", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_10", + "VBRK_LH1" + ], + [ + "CMT_TOP_WW4C3_10", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END0_10", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW4END3_10", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_LH9_10", + "VBRK_LH9" + ], + [ + "CMT_TOP_NW2A2_10", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_10", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_LH6_10", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A0_10", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE2A2_10", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2BEG2_10", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW2END1_10", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4B0_10", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C1_10", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SW2A2_10", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG2_10", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_NE2A0_10", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE2A1_10", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_10", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW2A0_10", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4A2_10", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW4A1_10", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WR1END0_10", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4B2_10", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END0_10", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4C0_10", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_10", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4B3_10", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4A0_10", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END3_10", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WL1END2_10", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4A2_10", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4B3_10", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NE4C1_10", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A1_10", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2A2_10", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EE4C3_10", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NW4A2_10", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NE4BEG2_10", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_SW2A1_10", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4BEG0_10", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SE2A0_10", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4BEG1_10", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_10", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_10", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4END3_10", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE2A2_10", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SE4C3_10", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4A3_10", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_LH2_10", + "VBRK_LH2" + ], + [ + "CMT_TOP_ER1BEG2_10", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NE2A3_10", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2A3_10", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C0_10", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_ER1BEG1_10", + "VBRK_ER1BEG1" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "CLK_HROW_WW2END2_6", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_NE4C3_6", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_LH10_6", + "VBRK_LH10" + ], + [ + "CLK_HROW_NE4C0_6", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WR1END2_6", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_SE4BEG1_6", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_SW4A2_6", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_SW4A0_6", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_WW4C3_6", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_SE4C0_6", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_EE2A2_6", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_EE4B3_6", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_NW2A3_6", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_SE4BEG0_6", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_SE2A2_6", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE4C1_6", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_SE4C2_6", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_NE4C1_6", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_WW4C0_6", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_EE2A1_6", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_EE4A3_6", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_MONITOR_P_6", + "VBRK_MONITOR_P" + ], + [ + "CLK_HROW_SW2A3_6", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_EL1BEG1_6", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_WW4B3_6", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_NE2A2_6", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_SW2A0_6", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_LH1_6", + "VBRK_LH1" + ], + [ + "CLK_HROW_LH11_6", + "VBRK_LH11" + ], + [ + "CLK_HROW_EE4A1_6", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_WW2A3_6", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_SW2A1_6", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_EE4B2_6", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_WW4A0_6", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_NE2A0_6", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_WL1END2_6", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_EL1BEG2_6", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WW4C2_6", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_WW2END0_6", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_EE4A0_6", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_EE4BEG0_6", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_ER1BEG2_6", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_NW4A0_6", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_NE4BEG1_6", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_SW4END2_6", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_SW4END3_6", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_NE2A1_6", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_WR1END0_6", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_EE2BEG3_6", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_EE2A0_6", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_SW4A3_6", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_SE4C1_6", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_LH6_6", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE2BEG2_6", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_EE4B0_6", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_LH4_6", + "VBRK_LH4" + ], + [ + "CLK_HROW_EE4BEG2_6", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_SE2A0_6", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_WR1END1_6", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_EE4A2_6", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_WW4END1_6", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_NE2A3_6", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_NE4BEG0_6", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_NW4END0_6", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_NE4BEG2_6", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WW4C1_6", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_WL1END3_6", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_SE2A3_6", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_ER1BEG1_6", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_EE4C2_6", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_LH5_6", + "VBRK_LH5" + ], + [ + "CLK_HROW_WW4A3_6", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_SW4A1_6", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_WW4END3_6", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_LH12_6", + "VBRK_LH12" + ], + [ + "CLK_HROW_WW2A1_6", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_WW4B0_6", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EE2BEG1_6", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_SE4BEG2_6", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_EL1BEG0_6", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_ER1BEG0_6", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4B2_6", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_EE4BEG3_6", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NW4END1_6", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_SE2A1_6", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_LH8_6", + "VBRK_LH8" + ], + [ + "CLK_HROW_MONITOR_N_6", + "VBRK_MONITOR_N" + ], + [ + "CLK_HROW_NW2A1_6", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_NW4END2_6", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_WW2A2_6", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_WW2END1_6", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_SW2A2_6", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_LH3_6", + "VBRK_LH3" + ], + [ + "CLK_HROW_NW4A2_6", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_WR1END3_6", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_SE4BEG3_6", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_SW4END1_6", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_LH7_6", + "VBRK_LH7" + ], + [ + "CLK_HROW_NE4C2_6", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_WW4END0_6", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_NW2A2_6", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_NW2A0_6", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_EE2A3_6", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_EE2BEG0_6", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_SW4END0_6", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_NE4BEG3_6", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_WW4A1_6", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_EE4BEG1_6", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WL1END1_6", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_NW4A1_6", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_LH9_6", + "VBRK_LH9" + ], + [ + "CLK_HROW_WL1END0_6", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_EE4B1_6", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_NW4END3_6", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_WW2END3_6", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_WW4A2_6", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_ER1BEG3_6", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_EL1BEG3_6", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_EE4C3_6", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_EE4C0_6", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_WW4END2_6", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_SE4C3_6", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_WW4B1_6", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_LH2_6", + "VBRK_LH2" + ], + [ + "CLK_HROW_NW4A3_6", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_WW2A0_6", + "VBRK_WW2A0" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLK_FEED_WW4B1", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_FEED_WL1END2", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_FEED_EE4BEG2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_FEED_LH8", + "INT_INTERFACE_LH8" + ], + [ + "CLK_FEED_WW4C1", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_FEED_WR1END3", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_FEED_EE4B3", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_FEED_NE2A2", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_FEED_WL1END0", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_FEED_NE2A1", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_FEED_WW4C2", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_FEED_NW2A2", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_FEED_WW2A0", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_FEED_WR1END1", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_FEED_SE4BEG2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_FEED_NW2A1", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_FEED_EE4A2", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_FEED_NW2A0", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_FEED_WW4B2", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_FEED_WL1END1", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_FEED_NE2A0", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_FEED_WW4C0", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_FEED_WW4END0", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_FEED_EE4C1", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_FEED_EE4C0", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_FEED_EE4BEG0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_FEED_LH11", + "INT_INTERFACE_LH11" + ], + [ + "CLK_FEED_WW4END2", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_FEED_SE4BEG1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_FEED_NW4A3", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_FEED_EE2BEG3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_FEED_SE2A2", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_FEED_EE2BEG2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_FEED_NW4A0", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_FEED_LH5", + "INT_INTERFACE_LH5" + ], + [ + "CLK_FEED_WW2A1", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_FEED_WW4C3", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_FEED_WW4A2", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_FEED_EE2A2", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_FEED_SW4END1", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_FEED_NW4END2", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_FEED_SW4END2", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_FEED_ER1BEG1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_FEED_EE4BEG3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_FEED_WW4A0", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_FEED_NE4C2", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_FEED_EE2A0", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_FEED_NE4C1", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_FEED_SE4C2", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_FEED_SE2A1", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_FEED_SE4C0", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_FEED_LH1", + "INT_INTERFACE_LH1" + ], + [ + "CLK_FEED_NE4BEG3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_FEED_WW2END2", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_FEED_EE4B2", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_FEED_MONITOR_P", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_FEED_WW2END0", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_FEED_NE2A3", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_FEED_EE4B1", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_FEED_MONITOR_N", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_FEED_WW4B0", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_FEED_SW4A1", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_FEED_SE2A3", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_FEED_WW4END1", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_FEED_ER1BEG2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_FEED_WR1END2", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_FEED_WR1END0", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_FEED_EE2A3", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_FEED_NE4C0", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_FEED_SE4C3", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_FEED_LH9", + "INT_INTERFACE_LH9" + ], + [ + "CLK_FEED_WW4A1", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_FEED_LH3", + "INT_INTERFACE_LH3" + ], + [ + "CLK_FEED_EE4A0", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_FEED_EL1BEG3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_FEED_SW4A3", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_FEED_NW2A3", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_FEED_WL1END3", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_FEED_SW4END3", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_FEED_SE2A0", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_FEED_NW4END3", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_FEED_EE2A1", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_FEED_SW4END0", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_FEED_EL1BEG2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_FEED_LH2", + "INT_INTERFACE_LH2" + ], + [ + "CLK_FEED_EE2BEG1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_FEED_EE4B0", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_FEED_SW2A2", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_FEED_LH6", + "INT_INTERFACE_LH6" + ], + [ + "CLK_FEED_SW2A1", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_FEED_SW2A0", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_FEED_EE4A3", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_FEED_EE4A1", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_FEED_EE4BEG1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_FEED_ER1BEG0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_FEED_NE4BEG1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_FEED_EL1BEG0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_FEED_WW2END1", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_FEED_NE4BEG2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_FEED_WW4A3", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_FEED_EE2BEG0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_FEED_WW4END3", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_FEED_NE4BEG0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_FEED_SW4A2", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_FEED_WW4B3", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_FEED_NE4C3", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_FEED_SE4BEG0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_FEED_LH12", + "INT_INTERFACE_LH12" + ], + [ + "CLK_FEED_NW4END0", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_FEED_LH4", + "INT_INTERFACE_LH4" + ], + [ + "CLK_FEED_EE4C3", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_FEED_EL1BEG1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_FEED_SW2A3", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_FEED_SW4A0", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_FEED_LH10", + "INT_INTERFACE_LH10" + ], + [ + "CLK_FEED_NW4END1", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_FEED_WW2A3", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_FEED_WW2END3", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_FEED_NW4A2", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_FEED_LH7", + "INT_INTERFACE_LH7" + ], + [ + "CLK_FEED_EE4C2", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_FEED_SE4C1", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_FEED_NW4A1", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_FEED_WW2A2", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_FEED_ER1BEG3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_FEED_SE4BEG3", + "INT_INTERFACE_SE4BEG3" + ] + ], + "tile_types": [ + "CLK_FEED", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX23_10", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_BYP6_10", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_CLK0_10", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_LOGIC_OUTS_B19_10", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX7_10", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX12_10", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX28_10", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX18_10", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_FAN0_10", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_FAN6_10", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX31_10", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B8_10", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_BYP2_10", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX36_10", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX42_10", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX45_10", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX22_10", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B2_10", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_LOGIC_OUTS_B0_10", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX21_10", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX14_10", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX9_10", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX3_10", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_LOGIC_OUTS_B17_10", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX33_10", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_LOGIC_OUTS_B10_10", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX17_10", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_LOGIC_OUTS_B12_10", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX15_10", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX24_10", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B7_10", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_IMUX44_10", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_FAN3_10", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_BYP3_10", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX8_10", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_BYP7_10", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B23_10", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX38_10", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX19_10", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_BYP1_10", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX29_10", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX10_10", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_FAN7_10", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B16_10", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX46_10", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_LOGIC_OUTS_B15_10", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX0_10", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX11_10", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX4_10", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_BYP0_10", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX26_10", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX40_10", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_FAN2_10", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX43_10", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_CTRL0_10", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX5_10", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX41_10", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX13_10", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_FAN5_10", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_FAN4_10", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_LOGIC_OUTS_B18_10", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX27_10", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_BYP4_10", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX1_10", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_CTRL1_10", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX30_10", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_LOGIC_OUTS_B4_10", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B20_10", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX20_10", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX47_10", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX2_10", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_LOGIC_OUTS_B9_10", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_LOGIC_OUTS_B5_10", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_FAN1_10", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX35_10", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_CLK1_10", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX16_10", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_LOGIC_OUTS_B14_10", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_LOGIC_OUTS_B1_10", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX37_10", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_LOGIC_OUTS_B13_10", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B22_10", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX32_10", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX25_10", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_BYP5_10", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B3_10", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX34_10", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_LOGIC_OUTS_B6_10", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX6_10", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX39_10", + "VBRK_EXT_IMUX39" + ] + ], + "tile_types": [ + "GTX_CHANNEL_2", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + 5 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_5" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_5" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_5" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_5" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_5" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_5" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_5" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_5" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_5" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_5" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_5" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_5" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_5" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_5" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_5" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_5" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_5" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_5" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_5" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_5" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_5" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_5" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_5" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_5" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_5" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_5" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_5" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_5" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_5" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_5" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_5" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_5" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_5" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_5" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_5" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_5" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_5" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_5" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_5" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_5" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_5" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_5" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_5" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_5" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_5" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_5" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_5" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_5" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_5" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_5" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_5" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_5" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_5" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_5" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_5" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_5" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_5" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_5" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_5" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_5" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_5" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_5" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_5" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_5" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_5" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_5" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_5" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_5" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_5" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_5" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_5" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_5" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_5" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_5" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_5" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_5" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_5" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_5" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_5" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_5" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_5" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_5" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_5" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_5" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_5" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_5" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_5" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_5" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_5" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_5" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_5" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_5" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_5" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_5" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_5" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_5" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_5" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_5" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_5" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_5" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_5" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_5" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_5" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_5" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_5" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_5" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_5" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_5" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_5" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_5" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_5" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_5" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_5" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_5" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_5" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_5" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_5" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_5" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_5" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_5" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_5" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_5" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_5" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_5" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_BOT_FUJI2" + ] + }, + { + "grid_deltas": [ + -1, + 5 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW2END1_5", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE2A0_5", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_SW2A1_5", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_SW2A2_5", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_SE2A1_5", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW4B0_5", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_NW4END3_5", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW2END3_5", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_NW2A2_5", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_WL1END1_5", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_EE4C1_5", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_WW2A2_5", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_LH8_5", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW4END3_5", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_SE4BEG2_5", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_SW4END2_5", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SW4END1_5", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_WR1END2_5", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_EE4BEG1_5", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_WW4C3_5", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4B1_5", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_NW2A3_5", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE2A2_5", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_WR1END0_5", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH4_5", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_NW4A2_5", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WL1END3_5", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE2A2_5", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WW4B3_5", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SE4C1_5", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_NW4END0_5", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SW4A0_5", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WW4END2_5", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_LH2_5", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NE4C0_5", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_EE2A1_5", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_NE2A1_5", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_LH10_5", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_EE4BEG2_5", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WL1END0_5", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_LH6_5", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WW4C0_5", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_ER1BEG0_5", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NE4BEG1_5", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_NE4BEG0_5", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NW2A1_5", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C2_5", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW4A0_5", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_NW4END1_5", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NE4C2_5", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE4BEG0_5", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WL1END2_5", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SW2A0_5", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_SE4C0_5", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_EE4B3_5", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_EE4A3_5", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_WW2END0_5", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WW4A0_5", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SE4BEG0_5", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SW4END0_5", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WW4A2_5", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_NE2A3_5", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_EE4B0_5", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH5_5", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE4B2_5", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_NE4C1_5", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW4A3_5", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_WR1END1_5", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_NW4A3_5", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_EE4A0_5", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_SE4C2_5", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_EL1BEG0_5", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_LH7_5", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_LH12_5", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW4END1_5", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE2BEG3_5", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_LH1_5", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_NW4END2_5", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_NE4BEG3_5", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW4C2_5", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_WW4END0_5", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WR1END3_5", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_SW4A3_5", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE2A3_5", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NW2A0_5", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_LH11_5", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EL1BEG2_5", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_SE2A0_5", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE4A1_5", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_SE4BEG3_5", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_SW2A3_5", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_ER1BEG2_5", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_WW2A0_5", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_EE2BEG0_5", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_ER1BEG3_5", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW4B2_5", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_LH9_5", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_SW4A2_5", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NE4C3_5", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_EE4C3_5", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_SE4C3_5", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WW4C1_5", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_EE2BEG1_5", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_EE2BEG2_5", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW2A1_5", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_NW4A1_5", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SE2A2_5", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4A2_5", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4B1_5", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_LH3_5", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_WW2A3_5", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_ER1BEG1_5", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WW4A1_5", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EL1BEG3_5", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_NE2A0_5", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EL1BEG1_5", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SW4END3_5", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NE4BEG2_5", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EE4C0_5", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EE4BEG3_5", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_SE4BEG1_5", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SW4A1_5", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_SE2A3_5", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_WW2END2_5", + "INT_FEEDTHRU_2_WW2END2" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_INT_INTERFACE_CCIO1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_INT_INTERFACE_CCIO0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CCIO2", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CCIO3", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_TERM_PERFCLK3" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_TERM_PERFCLK0" + ] + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_TERM" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX44_4", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX34_4", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX28_4", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_LOGIC_OUTS_B11_4", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_IMUX6_4", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B22_4", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX36_4", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX4_4", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_CTRL1_4", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX29_4", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX30_4", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX35_4", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX12_4", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX45_4", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_LOGIC_OUTS_B14_4", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX7_4", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX10_4", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX39_4", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX23_4", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX33_4", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_LOGIC_OUTS_B15_4", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_FAN4_4", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_LOGIC_OUTS_B0_4", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_LOGIC_OUTS_B23_4", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_BYP6_4", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX27_4", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B8_4", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX15_4", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_FAN0_4", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_BYP3_4", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B13_4", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_IMUX5_4", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B12_4", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_LOGIC_OUTS_B16_4", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_CTRL0_4", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX9_4", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX11_4", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX19_4", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX21_4", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX17_4", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX16_4", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_LOGIC_OUTS_B9_4", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_FAN7_4", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX37_4", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_LOGIC_OUTS_B19_4", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B17_4", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B5_4", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_BYP0_4", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX26_4", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX22_4", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B6_4", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX2_4", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_BYP1_4", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B7_4", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_BYP2_4", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX8_4", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_FAN5_4", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX38_4", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX43_4", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_CLK1_4", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX41_4", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B18_4", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX1_4", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_FAN3_4", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN1_4", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B4_4", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B10_4", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_LOGIC_OUTS_B3_4", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_LOGIC_OUTS_B20_4", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX20_4", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX24_4", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_FAN2_4", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX46_4", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX13_4", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX3_4", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX42_4", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX18_4", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX0_4", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_BYP4_4", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX32_4", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN6_4", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX14_4", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_BYP7_4", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B1_4", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX31_4", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX40_4", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B2_4", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX25_4", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_BYP5_4", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX47_4", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_CLK0_4", + "VBRK_EXT_CLK0" + ] + ], + "tile_types": [ + "GTX_CHANNEL_2", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "CMT_FIFO_SW2A2_3", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_NE4BEG0_3", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_SE4C2_3", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_L_IMUX17_3", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_WW4END1_3", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_3", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "CMT_FIFO_NE4BEG2_3", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_SE2A3_3", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_ER1BEG2_3", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_WW4A3_3", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_3", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "CMT_FIFO_EE2BEG3_3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_WL1END3_3", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_EE4BEG3_3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_EE2A3_3", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_SE4C0_3", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_SW2A3_3", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_SW4A1_3", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_SE2A1_3", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_3", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CMT_FIFO_L_IMUX46_3", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_SE4BEG1_3", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_3", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "CMT_FIFO_EE4A3_3", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_IMUX45_3", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_L_BYP2_3", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_SW4A3_3", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_NW2A3_3", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_WR1END0_3", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_SW4A0_3", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_WW4C3_3", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_NW2A0_3", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_LH12_3", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_WL1END1_3", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_L_IMUX5_3", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_NW2A1_3", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_WR1END3_3", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_ER1BEG0_3", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_NW4END2_3", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_BYP6_3", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_EE4B0_3", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_L_IMUX11_3", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_NE2A1_3", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_L_IMUX38_3", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_L_IMUX18_3", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_L_IMUX33_3", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_L_BYP7_3", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_L_IMUX19_3", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_EE4BEG0_3", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_SW4A2_3", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_L_IMUX12_3", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_L_FAN3_3", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_NE2A3_3", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_L_IMUX20_3", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_EE4C2_3", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_L_IMUX1_3", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_SE4BEG2_3", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_WW4END2_3", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_3", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CMT_FIFO_L_IMUX32_3", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_L_BYP3_3", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_L_IMUX40_3", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_LH2_3", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_L_IMUX3_3", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_L_BYP0_3", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_LH5_3", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_3", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CMT_FIFO_LH4_3", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_EL1BEG2_3", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_NE2A2_3", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_WL1END0_3", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_NW2A2_3", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_EE4B3_3", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_NE4C1_3", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_L_IMUX25_3", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_L_BYP5_3", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_WW4B3_3", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_L_IMUX15_3", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_EE2A1_3", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_WW4C0_3", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_EE4C0_3", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_L_IMUX41_3", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_3", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "CMT_FIFO_L_CLK0_3", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_L_IMUX24_3", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_L_CTRL0_3", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_NW4A1_3", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_WW2END0_3", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_EE4BEG1_3", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_LH7_3", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_L_IMUX14_3", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_NW4END1_3", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_WW2A1_3", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_L_IMUX0_3", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_WW4A1_3", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_SE4C1_3", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_3", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CMT_FIFO_L_IMUX27_3", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_3", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CMT_FIFO_SW4END1_3", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_EE4A2_3", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_FAN2_3", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_WW2END3_3", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_WW4A0_3", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_NE4BEG3_3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_SE2A2_3", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_L_IMUX28_3", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_WW4B0_3", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_L_IMUX39_3", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_LH1_3", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_L_IMUX29_3", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_L_IMUX9_3", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX31_3", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_SW4END0_3", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_WW4END0_3", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_IMUX35_3", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_NE4C3_3", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_SE4BEG0_3", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_NE4C0_3", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_3", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "CMT_FIFO_SE4BEG3_3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_NW4A3_3", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_L_IMUX44_3", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_IMUX23_3", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_3", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CMT_FIFO_L_IMUX13_3", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_L_IMUX7_3", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_L_IMUX16_3", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_L_FAN4_3", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_EE4BEG2_3", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_NW4A2_3", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_WW2A2_3", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_EE2A0_3", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_IMUX4_3", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_L_IMUX42_3", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_WR1END1_3", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_LH10_3", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_LH6_3", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_WW4END3_3", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_WW2END1_3", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_L_IMUX26_3", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_FAN6_3", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_EE2A2_3", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_NW4END3_3", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_WW2A0_3", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_L_FAN7_3", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_L_IMUX30_3", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_3", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "CMT_FIFO_L_IMUX6_3", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_SW4END3_3", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_L_BYP4_3", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_3", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "CMT_FIFO_L_IMUX36_3", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_SW4END2_3", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_EE4C1_3", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_WW4C1_3", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_L_BYP1_3", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_NE4C2_3", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_L_CLK1_3", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_3", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CMT_FIFO_L_IMUX2_3", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_LH8_3", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_3", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "CMT_FIFO_L_IMUX37_3", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_L_CTRL1_3", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_NW4A0_3", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_3", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CMT_FIFO_EE4B1_3", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_EE2BEG1_3", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_EL1BEG3_3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_L_IMUX21_3", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_SE4C3_3", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_IMUX10_3", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_L_IMUX43_3", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_LH9_3", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_NW4END0_3", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_L_FAN5_3", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_L_FAN0_3", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_EE4B2_3", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_L_IMUX34_3", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_LH11_3", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_3", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_3", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_3", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_EL1BEG0_3", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_WW2A3_3", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_NE2A0_3", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_SE2A0_3", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_L_FAN1_3", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_SW2A0_3", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_SW2A1_3", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_EE2BEG2_3", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_3", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CMT_FIFO_WR1END2_3", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_L_IMUX8_3", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_WW2END2_3", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_WL1END2_3", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_EE4C3_3", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_EE4A1_3", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_WW4B2_3", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_EE2BEG0_3", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_ER1BEG3_3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_ER1BEG1_3", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_IMUX22_3", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_LH3_3", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_3", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CMT_FIFO_EE4A0_3", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_WW4B1_3", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_NE4BEG1_3", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_WW4A2_3", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_EL1BEG1_3", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_3", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "CMT_FIFO_WW4C2_3", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_3", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "CMT_FIFO_L_IMUX47_3", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_3", + "INT_INTERFACE_LOGIC_OUTS_B6" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", + "CLK_FEED_R_CK_GCLK4" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK12_BOT", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ] + ], + "tile_types": [ + "CLK_BUFG_REBUF", + "CLK_FEED" + ] + }, + { + "grid_deltas": [ + 0, + -10 + ], + "wire_pairs": [ + [ + "PCIE_CFGERRTLPCPLHEADER35", + "PCIE_TOP_CFGERRTLPCPLHEADER35" + ], + [ + "PCIE_MIMRXWDATA2", + "PCIE_TOP_MIMRXWDATA2" + ], + [ + "PCIE_CFGDEVCONTROL2IDOREQEN", + "PCIE_TOP_CFGDEVCONTROL2IDOREQEN" + ], + [ + "PCIE_MIMRXWDATA22", + "PCIE_TOP_MIMRXWDATA22" + ], + [ + "PCIE_CFGDEVCONTROL2ATOMICREQUESTEREN", + "PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN" + ], + [ + "PCIE_MIMRXRDATA38", + "PCIE_TOP_MIMRXRDATA38" + ], + [ + "PCIE_CFGDEVID15", + "PCIE_TOP_CFGDEVID15" + ], + [ + "PCIE_CFGCOMMANDIOENABLE", + "PCIE_TOP_CFGCOMMANDIOENABLE" + ], + [ + "PCIE_DRPDI11", + "PCIE_TOP_DRPDI11" + ], + [ + "PCIE_CFGERRAERHEADERLOG6", + "PCIE_TOP_CFGERRAERHEADERLOG6" + ], + [ + "PCIE_DBGVECA3", + "PCIE_TOP_DBGVECA3" + ], + [ + "PCIE_CFGLINKCONTROLASPMCONTROL1", + "PCIE_TOP_CFGLINKCONTROLASPMCONTROL1" + ], + [ + "PCIE_TRNRDLLPDATA61", + "PCIE_TOP_TRNRDLLPDATA61" + ], + [ + "PCIE_TRNRDLLPDATA49", + "PCIE_TOP_TRNRDLLPDATA49" + ], + [ + "PCIE_TRNTD33", + "PCIE_TOP_TRNTD33" + ], + [ + "PCIE_TRNRD66", + "PCIE_TOP_TRNRD66" + ], + [ + "PCIE_CFGCOMMANDMEMENABLE", + "PCIE_TOP_CFGCOMMANDMEMENABLE" + ], + [ + "PCIE_CFGMGMTDO24", + "PCIE_TOP_CFGMGMTDO24" + ], + [ + "PCIE_TRNTD38", + "PCIE_TOP_TRNTD38" + ], + [ + "PCIE_TRNRDLLPDATA47", + "PCIE_TOP_TRNRDLLPDATA47" + ], + [ + "PCIE_MIMRXRDATA22", + "PCIE_TOP_MIMRXRDATA22" + ], + [ + "PCIE_DBGVECA6", + "PCIE_TOP_DBGVECA6" + ], + [ + "PCIE_TRNRD73", + "PCIE_TOP_TRNRD73" + ], + [ + "PCIE_TRNRD98", + "PCIE_TOP_TRNRD98" + ], + [ + "PCIE_TRNTDLLPDATA31", + "PCIE_TOP_TRNTDLLPDATA31" + ], + [ + "PCIE_TRNRD68", + "PCIE_TOP_TRNRD68" + ], + [ + "PCIE_CFGPMRCVASREQL1N", + "PCIE_TOP_CFGPMRCVASREQL1N" + ], + [ + "PCIE_LL2SENDENTERL23", + "PCIE_TOP_LL2SENDENTERL23" + ], + [ + "PCIE_CFGDSN57", + "PCIE_TOP_CFGDSN57" + ], + [ + "PCIE_MIMRXWDATA33", + "PCIE_TOP_MIMRXWDATA33" + ], + [ + "PCIE_PIPERX4CHARISK0", + "PCIE_TOP_PIPERX4CHARISK0" + ], + [ + "PCIE_TRNRD65", + "PCIE_TOP_TRNRD65" + ], + [ + "PCIE_DBGVECA11", + "PCIE_TOP_DBGVECA11" + ], + [ + "PCIE_CFGERRAERHEADERLOG10", + "PCIE_TOP_CFGERRAERHEADERLOG10" + ], + [ + "PCIE_CFGPMCSRPOWERSTATE1", + "PCIE_TOP_CFGPMCSRPOWERSTATE1" + ], + [ + "PCIE_TRNTDLLPDATA30", + "PCIE_TOP_TRNTDLLPDATA30" + ], + [ + "PCIE_TRNTDLLPDATA20", + "PCIE_TOP_TRNTDLLPDATA20" + ], + [ + "PCIE_CFGDEVCONTROL2IDOCPLEN", + "PCIE_TOP_CFGDEVCONTROL2IDOCPLEN" + ], + [ + "PCIE_MIMRXRADDR8", + "PCIE_TOP_MIMRXRADDR8" + ], + [ + "PCIE_DRPDO1", + "PCIE_TOP_DRPDO1" + ], + [ + "PCIE_TRNRDLLPSRCRDY1", + "PCIE_TOP_TRNRDLLPSRCRDY1" + ], + [ + "PCIE_MIMRXWDATA8", + "PCIE_TOP_MIMRXWDATA8" + ], + [ + "PCIE_CFGTRANSACTIONADDR6", + "PCIE_TOP_CFGTRANSACTIONADDR6" + ], + [ + "PCIE_MIMRXWDATA23", + "PCIE_TOP_MIMRXWDATA23" + ], + [ + "PCIE_TRNRDLLPDATA45", + "PCIE_TOP_TRNRDLLPDATA45" + ], + [ + "PCIE_CFGERRAERHEADERLOG1", + "PCIE_TOP_CFGERRAERHEADERLOG1" + ], + [ + "PCIE_TRNTD20", + "PCIE_TOP_TRNTD20" + ], + [ + "PCIE_TRNRDLLPDATA55", + "PCIE_TOP_TRNRDLLPDATA55" + ], + [ + "PCIE_CFGERRAERHEADERLOG0", + "PCIE_TOP_CFGERRAERHEADERLOG0" + ], + [ + "PCIE_TRNTD12", + "PCIE_TOP_TRNTD12" + ], + [ + "PCIE_MIMRXWDATA1", + "PCIE_TOP_MIMRXWDATA1" + ], + [ + "PCIE_TRNTDLLPDATA25", + "PCIE_TOP_TRNTDLLPDATA25" + ], + [ + "PCIE_TRNRD75", + "PCIE_TOP_TRNRD75" + ], + [ + "PCIE_PIPETXMARGIN0", + "PCIE_TOP_PIPETXMARGIN0" + ], + [ + "PCIE_PIPERX4PHYSTATUS", + "PCIE_TOP_PIPERX4PHYSTATUS" + ], + [ + "PCIE_MIMRXWDATA51", + "PCIE_TOP_MIMRXWDATA51" + ], + [ + "PCIE_DRPDO13", + "PCIE_TOP_DRPDO13" + ], + [ + "PCIE_TRNRD71", + "PCIE_TOP_TRNRD71" + ], + [ + "PCIE_DRPDI2", + "PCIE_TOP_DRPDI2" + ], + [ + "PCIE_CFGLINKCONTROLCLOCKPMEN", + "PCIE_TOP_CFGLINKCONTROLCLOCKPMEN" + ], + [ + "PCIE_CFGERRTLPCPLHEADER37", + "PCIE_TOP_CFGERRTLPCPLHEADER37" + ], + [ + "PCIE_MIMRXRADDR1", + "PCIE_TOP_MIMRXRADDR1" + ], + [ + "PCIE_DBGVECA0", + "PCIE_TOP_DBGVECA0" + ], + [ + "PCIE_TRNRD93", + "PCIE_TOP_TRNRD93" + ], + [ + "PCIE_PIPERX0DATA0", + "PCIE_TOP_PIPERX0DATA0" + ], + [ + "PCIE_CFGMGMTDO30", + "PCIE_TOP_CFGMGMTDO30" + ], + [ + "PCIE_LL2SENDASREQL1", + "PCIE_TOP_LL2SENDASREQL1" + ], + [ + "PCIE_TRNRD91", + "PCIE_TOP_TRNRD91" + ], + [ + "PCIE_CFGPMRCVENTERL23N", + "PCIE_TOP_CFGPMRCVENTERL23N" + ], + [ + "PCIE_MIMRXRDATA44", + "PCIE_TOP_MIMRXRDATA44" + ], + [ + "PCIE_CFGERRTLPCPLHEADER26", + "PCIE_TOP_CFGERRTLPCPLHEADER26" + ], + [ + "PCIE_DRPDO6", + "PCIE_TOP_DRPDO6" + ], + [ + "PCIE_TRNRDLLPDATA38", + "PCIE_TOP_TRNRDLLPDATA38" + ], + [ + "PCIE_MIMRXRDATA27", + "PCIE_TOP_MIMRXRDATA27" + ], + [ + "PCIE_MIMRXRDATA41", + "PCIE_TOP_MIMRXRDATA41" + ], + [ + "PCIE_CFGDEVID1", + "PCIE_TOP_CFGDEVID1" + ], + [ + "PCIE_TRNRD80", + "PCIE_TOP_TRNRD80" + ], + [ + "PCIE_DRPDO5", + "PCIE_TOP_DRPDO5" + ], + [ + "PCIE_CFGDSN61", + "PCIE_TOP_CFGDSN61" + ], + [ + "PCIE_MIMRXRDATA52", + "PCIE_TOP_MIMRXRDATA52" + ], + [ + "PCIE_CFGDEVID10", + "PCIE_TOP_CFGDEVID10" + ], + [ + "PCIE_CFGPMCSRPMESTATUS", + "PCIE_TOP_CFGPMCSRPMESTATUS" + ], + [ + "PCIE_PIPERX0VALID", + "PCIE_TOP_PIPERX0VALID" + ], + [ + "PCIE_TRNRDLLPDATA56", + "PCIE_TOP_TRNRDLLPDATA56" + ], + [ + "PCIE_TRNRD69", + "PCIE_TOP_TRNRD69" + ], + [ + "PCIE_CFGDEVCONTROL2ATOMICEGRESSBLOCK", + "PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK" + ], + [ + "PCIE_MIMRXRDATA39", + "PCIE_TOP_MIMRXRDATA39" + ], + [ + "PCIE_PIPERX0DATA4", + "PCIE_TOP_PIPERX0DATA4" + ], + [ + "PCIE_CFGERRTLPCPLHEADER47", + "PCIE_TOP_CFGERRTLPCPLHEADER47" + ], + [ + "PCIE_CFGVENDID0", + "PCIE_TOP_CFGVENDID0" + ], + [ + "PCIE_MIMRXWDATA49", + "PCIE_TOP_MIMRXWDATA49" + ], + [ + "PCIE_MIMRXWDATA21", + "PCIE_TOP_MIMRXWDATA21" + ], + [ + "PCIE_DRPDI10", + "PCIE_TOP_DRPDI10" + ], + [ + "PCIE_PLDBGVEC8", + "PCIE_TOP_PLDBGVEC8" + ], + [ + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL1", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1" + ], + [ + "PCIE_CFGERRTLPCPLHEADER39", + "PCIE_TOP_CFGERRTLPCPLHEADER39" + ], + [ + "PCIE_MIMRXRDATA26", + "PCIE_TOP_MIMRXRDATA26" + ], + [ + "PCIE_CFGDEVID3", + "PCIE_TOP_CFGDEVID3" + ], + [ + "PCIE_PIPERX4DATA7", + "PCIE_TOP_PIPERX4DATA7" + ], + [ + "PCIE_TRNTDLLPSRCRDY", + "PCIE_TOP_TRNTDLLPSRCRDY" + ], + [ + "PCIE_MIMRXWDATA27", + "PCIE_TOP_MIMRXWDATA27" + ], + [ + "PCIE_MIMRXRDATA49", + "PCIE_TOP_MIMRXRDATA49" + ], + [ + "PCIE_TRNRD74", + "PCIE_TOP_TRNRD74" + ], + [ + "PCIE_TRNRD85", + "PCIE_TOP_TRNRD85" + ], + [ + "PCIE_CFGERRTLPCPLHEADER38", + "PCIE_TOP_CFGERRTLPCPLHEADER38" + ], + [ + "PCIE_CFGPCIELINKSTATE2", + "PCIE_TOP_CFGPCIELINKSTATE2" + ], + [ + "PCIE_TRNRDLLPDATA39", + "PCIE_TOP_TRNRDLLPDATA39" + ], + [ + "PCIE_CFGERRTLPCPLHEADER31", + "PCIE_TOP_CFGERRTLPCPLHEADER31" + ], + [ + "PCIE_TRNTDLLPDATA19", + "PCIE_TOP_TRNTDLLPDATA19" + ], + [ + "PCIE_TRNRDLLPDATA41", + "PCIE_TOP_TRNRDLLPDATA41" + ], + [ + "PCIE_TRNTDLLPDATA24", + "PCIE_TOP_TRNTDLLPDATA24" + ], + [ + "PCIE_DBGVECA19", + "PCIE_TOP_DBGVECA19" + ], + [ + "PCIE_CFGMGMTDO19", + "PCIE_TOP_CFGMGMTDO19" + ], + [ + "PCIE_DBGVECB10", + "PCIE_TOP_DBGVECB10" + ], + [ + "PCIE_TRNRD60", + "PCIE_TOP_TRNRD60" + ], + [ + "PCIE_EDTCONFIGURATION", + "PCIE_TOP_EDTCONFIGURATION" + ], + [ + "PCIE_CFGINTERRUPTN", + "PCIE_TOP_CFGINTERRUPTN" + ], + [ + "PCIE_TRNTD25", + "PCIE_TOP_TRNTD25" + ], + [ + "PCIE_MIMRXWDATA24", + "PCIE_TOP_MIMRXWDATA24" + ], + [ + "PCIE_CFGLINKCONTROLEXTENDEDSYNC", + "PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC" + ], + [ + "PCIE_MIMRXWDATA0", + "PCIE_TOP_MIMRXWDATA0" + ], + [ + "PCIE_DRPDI7", + "PCIE_TOP_DRPDI7" + ], + [ + "PCIE_TRNRD82", + "PCIE_TOP_TRNRD82" + ], + [ + "PCIE_TRNRDLLPDATA33", + "PCIE_TOP_TRNRDLLPDATA33" + ], + [ + "PCIE_MIMRXWDATA4", + "PCIE_TOP_MIMRXWDATA4" + ], + [ + "PCIE_CFGMGMTDO27", + "PCIE_TOP_CFGMGMTDO27" + ], + [ + "PCIE_CFGERRTLPCPLHEADER40", + "PCIE_TOP_CFGERRTLPCPLHEADER40" + ], + [ + "PCIE_TRNTD26", + "PCIE_TOP_TRNTD26" + ], + [ + "PCIE_DBGVECA10", + "PCIE_TOP_DBGVECA10" + ], + [ + "PCIE_TRNRD59", + "PCIE_TOP_TRNRD59" + ], + [ + "PCIE_TRNTD36", + "PCIE_TOP_TRNTD36" + ], + [ + "PCIE_MIMRXRDATA25", + "PCIE_TOP_MIMRXRDATA25" + ], + [ + "PCIE_TRNRDLLPDATA52", + "PCIE_TOP_TRNRDLLPDATA52" + ], + [ + "PCIE_TRNTD29", + "PCIE_TOP_TRNTD29" + ], + [ + "PCIE_TRNRD96", + "PCIE_TOP_TRNRD96" + ], + [ + "PCIE_CFGPMCSRPMEEN", + "PCIE_TOP_CFGPMCSRPMEEN" + ], + [ + "PCIE_MIMRXRDATA31", + "PCIE_TOP_MIMRXRDATA31" + ], + [ + "PCIE_MIMRXRDATA50", + "PCIE_TOP_MIMRXRDATA50" + ], + [ + "PCIE_CFGAERROOTERRNONFATALERRREPORTINGEN", + "PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN" + ], + [ + "PCIE_MIMRXWDATA31", + "PCIE_TOP_MIMRXWDATA31" + ], + [ + "PCIE_PIPETXMARGIN1", + "PCIE_TOP_PIPETXMARGIN1" + ], + [ + "PCIE_CFGDEVID6", + "PCIE_TOP_CFGDEVID6" + ], + [ + "PCIE_TRNRD81", + "PCIE_TOP_TRNRD81" + ], + [ + "PCIE_TL2PPMSUSPENDREQ", + "PCIE_TOP_TL2PPMSUSPENDREQ" + ], + [ + "PCIE_DBGVECA2", + "PCIE_TOP_DBGVECA2" + ], + [ + "PCIE_TRNTD8", + "PCIE_TOP_TRNTD8" + ], + [ + "PCIE_CFGTRANSACTIONTYPE", + "PCIE_TOP_CFGTRANSACTIONTYPE" + ], + [ + "PCIE_TRNRDLLPDATA53", + "PCIE_TOP_TRNRDLLPDATA53" + ], + [ + "PCIE_PL2DIRECTEDLSTATE2", + "PCIE_TOP_PL2DIRECTEDLSTATE2" + ], + [ + "PCIE_TRNTD41", + "PCIE_TOP_TRNTD41" + ], + [ + "PCIE_DRPDO12", + "PCIE_TOP_DRPDO12" + ], + [ + "PCIE_DBGVECA13", + "PCIE_TOP_DBGVECA13" + ], + [ + "PCIE_MIMRXWEN", + "PCIE_TOP_MIMRXWEN" + ], + [ + "PCIE_MIMRXWDATA30", + "PCIE_TOP_MIMRXWDATA30" + ], + [ + "PCIE_CFGDEVID2", + "PCIE_TOP_CFGDEVID2" + ], + [ + "PCIE_TRNTD16", + "PCIE_TOP_TRNTD16" + ], + [ + "PCIE_TRNRDLLPDATA62", + "PCIE_TOP_TRNRDLLPDATA62" + ], + [ + "PCIE_DRPDO14", + "PCIE_TOP_DRPDO14" + ], + [ + "PCIE_PIPERX0DATA1", + "PCIE_TOP_PIPERX0DATA1" + ], + [ + "PCIE_PIPERX0DATA5", + "PCIE_TOP_PIPERX0DATA5" + ], + [ + "PCIE_PIPERX4VALID", + "PCIE_TOP_PIPERX4VALID" + ], + [ + "PCIE_CFGMGMTDO21", + "PCIE_TOP_CFGMGMTDO21" + ], + [ + "PCIE_TRNRDLLPDATA54", + "PCIE_TOP_TRNRDLLPDATA54" + ], + [ + "PCIE_PIPERX4DATA4", + "PCIE_TOP_PIPERX4DATA4" + ], + [ + "PCIE_TRNTD31", + "PCIE_TOP_TRNTD31" + ], + [ + "PCIE_MIMRXWDATA5", + "PCIE_TOP_MIMRXWDATA5" + ], + [ + "PCIE_MIMRXRDATA48", + "PCIE_TOP_MIMRXRDATA48" + ], + [ + "PCIE_PIPERX0DATA3", + "PCIE_TOP_PIPERX0DATA3" + ], + [ + "PCIE_CFGERRTLPCPLHEADER41", + "PCIE_TOP_CFGERRTLPCPLHEADER41" + ], + [ + "PCIE_TRNTD32", + "PCIE_TOP_TRNTD32" + ], + [ + "PCIE_PIPERX4CHANISALIGNED", + "PCIE_TOP_PIPERX4CHANISALIGNED" + ], + [ + "PCIE_DRPDI3", + "PCIE_TOP_DRPDI3" + ], + [ + "PCIE_PL2DIRECTEDLSTATE3", + "PCIE_TOP_PL2DIRECTEDLSTATE3" + ], + [ + "PCIE_TRNTD39", + "PCIE_TOP_TRNTD39" + ], + [ + "PCIE_TRNRD87", + "PCIE_TOP_TRNRD87" + ], + [ + "PCIE_CFGVCTCVCMAP1", + "PCIE_TOP_CFGVCTCVCMAP1" + ], + [ + "PCIE_CFGVCTCVCMAP3", + "PCIE_TOP_CFGVCTCVCMAP3" + ], + [ + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL3", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3" + ], + [ + "PCIE_DRPDO2", + "PCIE_TOP_DRPDO2" + ], + [ + "PCIE_MIMRXWADDR12", + "PCIE_TOP_MIMRXWADDR12" + ], + [ + "PCIE_MIMRXWDATA3", + "PCIE_TOP_MIMRXWDATA3" + ], + [ + "PCIE_TRNRD79", + "PCIE_TOP_TRNRD79" + ], + [ + "PCIE_CFGPMRCVREQACKN", + "PCIE_TOP_CFGPMRCVREQACKN" + ], + [ + "PCIE_CFGERRAERHEADERLOG2", + "PCIE_TOP_CFGERRAERHEADERLOG2" + ], + [ + "PCIE_CFGERRTLPCPLHEADER34", + "PCIE_TOP_CFGERRTLPCPLHEADER34" + ], + [ + "PCIE_TRNTD11", + "PCIE_TOP_TRNTD11" + ], + [ + "PCIE_MIMRXRDATA33", + "PCIE_TOP_MIMRXRDATA33" + ], + [ + "PCIE_MIMRXWDATA28", + "PCIE_TOP_MIMRXWDATA28" + ], + [ + "PCIE_MIMRXRDATA43", + "PCIE_TOP_MIMRXRDATA43" + ], + [ + "PCIE_TRNTD23", + "PCIE_TOP_TRNTD23" + ], + [ + "PCIE_CFGERRLOCKEDN", + "PCIE_TOP_CFGERRLOCKEDN" + ], + [ + "PCIE_DRPDI0", + "PCIE_TOP_DRPDI0" + ], + [ + "PCIE_DBGMODE0", + "PCIE_TOP_DBGMODE0" + ], + [ + "PCIE_DRPDI15", + "PCIE_TOP_DRPDI15" + ], + [ + "PCIE_CFGTRANSACTIONADDR5", + "PCIE_TOP_CFGTRANSACTIONADDR5" + ], + [ + "PCIE_DRPDI4", + "PCIE_TOP_DRPDI4" + ], + [ + "PCIE_TRNRD92", + "PCIE_TOP_TRNRD92" + ], + [ + "PCIE_TRNRD61", + "PCIE_TOP_TRNRD61" + ], + [ + "PCIE_MIMRXRDATA46", + "PCIE_TOP_MIMRXRDATA46" + ], + [ + "PCIE_TRNRD70", + "PCIE_TOP_TRNRD70" + ], + [ + "PCIE_CFGDEVID7", + "PCIE_TOP_CFGDEVID7" + ], + [ + "PCIE_MIMRXWDATA20", + "PCIE_TOP_MIMRXWDATA20" + ], + [ + "PCIE_MIMRXWDATA15", + "PCIE_TOP_MIMRXWDATA15" + ], + [ + "PCIE_MIMRXWDATA11", + "PCIE_TOP_MIMRXWDATA11" + ], + [ + "PCIE_MIMRXRADDR9", + "PCIE_TOP_MIMRXRADDR9" + ], + [ + "PCIE_PIPERX0CHARISK0", + "PCIE_TOP_PIPERX0CHARISK0" + ], + [ + "PCIE_CFGCOMMANDBUSMASTERENABLE", + "PCIE_TOP_CFGCOMMANDBUSMASTERENABLE" + ], + [ + "PCIE_LL2TLPRCV", + "PCIE_TOP_LL2TLPRCV" + ], + [ + "PCIE_EDTBYPASS", + "PCIE_TOP_EDTBYPASS" + ], + [ + "PCIE_CFGINTERRUPTDI0", + "PCIE_TOP_CFGINTERRUPTDI0" + ], + [ + "PCIE_TRNTDLLPDATA27", + "PCIE_TOP_TRNTDLLPDATA27" + ], + [ + "PCIE_CFGLINKCONTROLRCB", + "PCIE_TOP_CFGLINKCONTROLRCB" + ], + [ + "PCIE_MIMRXRDATA32", + "PCIE_TOP_MIMRXRDATA32" + ], + [ + "PCIE_CFGMGMTDO23", + "PCIE_TOP_CFGMGMTDO23" + ], + [ + "PCIE_MIMRXWDATA19", + "PCIE_TOP_MIMRXWDATA19" + ], + [ + "PCIE_CFGMGMTDO18", + "PCIE_TOP_CFGMGMTDO18" + ], + [ + "PCIE_TRNTDLLPDATA23", + "PCIE_TOP_TRNTDLLPDATA23" + ], + [ + "PCIE_TRNRDLLPDATA43", + "PCIE_TOP_TRNRDLLPDATA43" + ], + [ + "PCIE_TRNRD67", + "PCIE_TOP_TRNRD67" + ], + [ + "PCIE_MIMRXRDATA29", + "PCIE_TOP_MIMRXRDATA29" + ], + [ + "PCIE_MIMRXRDATA37", + "PCIE_TOP_MIMRXRDATA37" + ], + [ + "PCIE_DRPADDR8", + "PCIE_TOP_DRPADDR8" + ], + [ + "PCIE_TRNRD86", + "PCIE_TOP_TRNRD86" + ], + [ + "PCIE_CFGERRNORECOVERYN", + "PCIE_TOP_CFGERRNORECOVERYN" + ], + [ + "PCIE_TRNTD27", + "PCIE_TOP_TRNTD27" + ], + [ + "PCIE_TRNRDLLPDATA32", + "PCIE_TOP_TRNRDLLPDATA32" + ], + [ + "PCIE_CFGAERROOTERRFATALERRRECEIVED", + "PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED" + ], + [ + "PCIE_DRPDO11", + "PCIE_TOP_DRPDO11" + ], + [ + "PCIE_TRNRDLLPDATA42", + "PCIE_TOP_TRNRDLLPDATA42" + ], + [ + "PCIE_MIMRXWADDR2", + "PCIE_TOP_MIMRXWADDR2" + ], + [ + "PCIE_MIMRXRADDR10", + "PCIE_TOP_MIMRXRADDR10" + ], + [ + "PCIE_CFGVCTCVCMAP2", + "PCIE_TOP_CFGVCTCVCMAP2" + ], + [ + "PCIE_DBGVECA18", + "PCIE_TOP_DBGVECA18" + ], + [ + "PCIE_LL2SENDPMACK", + "PCIE_TOP_LL2SENDPMACK" + ], + [ + "PCIE_DBGVECA9", + "PCIE_TOP_DBGVECA9" + ], + [ + "PCIE_CFGDSN59", + "PCIE_TOP_CFGDSN59" + ], + [ + "PCIE_DBGVECA20", + "PCIE_TOP_DBGVECA20" + ], + [ + "PCIE_TRNRD77", + "PCIE_TOP_TRNRD77" + ], + [ + "PCIE_TRNRD84", + "PCIE_TOP_TRNRD84" + ], + [ + "PCIE_CFGPMCSRPOWERSTATE0", + "PCIE_TOP_CFGPMCSRPOWERSTATE0" + ], + [ + "PCIE_CFGDEVCONTROL2LTREN", + "PCIE_TOP_CFGDEVCONTROL2LTREN" + ], + [ + "PCIE_TRNTD15", + "PCIE_TOP_TRNTD15" + ], + [ + "PCIE_TRNRD62", + "PCIE_TOP_TRNRD62" + ], + [ + "PCIE_TRNRD64", + "PCIE_TOP_TRNRD64" + ], + [ + "PCIE_DBGVECA17", + "PCIE_TOP_DBGVECA17" + ], + [ + "PCIE_CFGAERROOTERRFATALERRREPORTINGEN", + "PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN" + ], + [ + "PCIE_LL2TFCINIT1SEQ", + "PCIE_TOP_LL2TFCINIT1SEQ" + ], + [ + "PCIE_DRPDO0", + "PCIE_TOP_DRPDO0" + ], + [ + "PCIE_PL2DIRECTEDLSTATE0", + "PCIE_TOP_PL2DIRECTEDLSTATE0" + ], + [ + "PCIE_DRPDI8", + "PCIE_TOP_DRPDI8" + ], + [ + "PCIE_PL2SUSPENDOK", + "PCIE_TOP_PL2SUSPENDOK" + ], + [ + "PCIE_CFGERRTLPCPLHEADER30", + "PCIE_TOP_CFGERRTLPCPLHEADER30" + ], + [ + "PCIE_TRNRDLLPDATA59", + "PCIE_TOP_TRNRDLLPDATA59" + ], + [ + "PCIE_MIMRXRDATA28", + "PCIE_TOP_MIMRXRDATA28" + ], + [ + "PCIE_PIPERX0DATA2", + "PCIE_TOP_PIPERX0DATA2" + ], + [ + "PCIE_MIMRXWDATA35", + "PCIE_TOP_MIMRXWDATA35" + ], + [ + "PCIE_CFGVCTCVCMAP4", + "PCIE_TOP_CFGVCTCVCMAP4" + ], + [ + "PCIE_TRNRDLLPDATA51", + "PCIE_TOP_TRNRDLLPDATA51" + ], + [ + "PCIE_MIMRXWADDR1", + "PCIE_TOP_MIMRXWADDR1" + ], + [ + "PCIE_PIPERX0CHANISALIGNED", + "PCIE_TOP_PIPERX0CHANISALIGNED" + ], + [ + "PCIE_TRNTD18", + "PCIE_TOP_TRNTD18" + ], + [ + "PCIE_CFGTRANSACTIONADDR2", + "PCIE_TOP_CFGTRANSACTIONADDR2" + ], + [ + "PCIE_MIMRXRDATA40", + "PCIE_TOP_MIMRXRDATA40" + ], + [ + "PCIE_MIMRXWDATA25", + "PCIE_TOP_MIMRXWDATA25" + ], + [ + "PCIE_TRNTD21", + "PCIE_TOP_TRNTD21" + ], + [ + "PCIE_CFGPMRCVENTERL1N", + "PCIE_TOP_CFGPMRCVENTERL1N" + ], + [ + "PCIE_DRPDO3", + "PCIE_TOP_DRPDO3" + ], + [ + "PCIE_CFGMGMTDO22", + "PCIE_TOP_CFGMGMTDO22" + ], + [ + "PCIE_CFGAERROOTERRNONFATALERRRECEIVED", + "PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED" + ], + [ + "PCIE_CFGPCIELINKSTATE1", + "PCIE_TOP_CFGPCIELINKSTATE1" + ], + [ + "PCIE_CFGMGMTDO17", + "PCIE_TOP_CFGMGMTDO17" + ], + [ + "PCIE_TRNTD34", + "PCIE_TOP_TRNTD34" + ], + [ + "PCIE_DRPDI14", + "PCIE_TOP_DRPDI14" + ], + [ + "PCIE_MIMRXWDATA9", + "PCIE_TOP_MIMRXWDATA9" + ], + [ + "PCIE_CFGERRAERHEADERLOG3", + "PCIE_TOP_CFGERRAERHEADERLOG3" + ], + [ + "PCIE_CFGDEVID9", + "PCIE_TOP_CFGDEVID9" + ], + [ + "PCIE_DRPDO15", + "PCIE_TOP_DRPDO15" + ], + [ + "PCIE_MIMRXRDATA54", + "PCIE_TOP_MIMRXRDATA54" + ], + [ + "PCIE_MIMRXRDATA35", + "PCIE_TOP_MIMRXRDATA35" + ], + [ + "PCIE_LL2SENDENTERL1", + "PCIE_TOP_LL2SENDENTERL1" + ], + [ + "PCIE_PIPERX0DATA7", + "PCIE_TOP_PIPERX0DATA7" + ], + [ + "PCIE_TRNRDLLPDATA57", + "PCIE_TOP_TRNRDLLPDATA57" + ], + [ + "PCIE_CFGDEVID13", + "PCIE_TOP_CFGDEVID13" + ], + [ + "PCIE_TRNTD13", + "PCIE_TOP_TRNTD13" + ], + [ + "PCIE_DBGVECA15", + "PCIE_TOP_DBGVECA15" + ], + [ + "PCIE_CFGMGMTDO25", + "PCIE_TOP_CFGMGMTDO25" + ], + [ + "PCIE_MIMRXRADDR2", + "PCIE_TOP_MIMRXRADDR2" + ], + [ + "PCIE_MIMRXRDATA53", + "PCIE_TOP_MIMRXRDATA53" + ], + [ + "PCIE_TRNRDLLPDATA63", + "PCIE_TOP_TRNRDLLPDATA63" + ], + [ + "PCIE_MIMRXRDATA20", + "PCIE_TOP_MIMRXRDATA20" + ], + [ + "PCIE_DBGVECA5", + "PCIE_TOP_DBGVECA5" + ], + [ + "PCIE_TRNTD10", + "PCIE_TOP_TRNTD10" + ], + [ + "PCIE_PIPERX4DATA0", + "PCIE_TOP_PIPERX4DATA0" + ], + [ + "PCIE_CFGERRTLPCPLHEADER45", + "PCIE_TOP_CFGERRTLPCPLHEADER45" + ], + [ + "PCIE_CFGERRAERHEADERLOG8", + "PCIE_TOP_CFGERRAERHEADERLOG8" + ], + [ + "PCIE_CFGDEVCONTROL2CPLTIMEOUTDIS", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS" + ], + [ + "PCIE_PIPERX4DATA3", + "PCIE_TOP_PIPERX4DATA3" + ], + [ + "PCIE_TRNTDLLPDATA22", + "PCIE_TOP_TRNTDLLPDATA22" + ], + [ + "PCIE_CFGTRANSACTIONADDR3", + "PCIE_TOP_CFGTRANSACTIONADDR3" + ], + [ + "PCIE_TRNRDLLPDATA34", + "PCIE_TOP_TRNRDLLPDATA34" + ], + [ + "PCIE_TRNRDLLPDATA40", + "PCIE_TOP_TRNRDLLPDATA40" + ], + [ + "PCIE_TRNTD19", + "PCIE_TOP_TRNTD19" + ], + [ + "PCIE_CFGERRTLPCPLHEADER46", + "PCIE_TOP_CFGERRTLPCPLHEADER46" + ], + [ + "PCIE_PIPERX0DATA6", + "PCIE_TOP_PIPERX0DATA6" + ], + [ + "PCIE_CFGERRTLPCPLHEADER28", + "PCIE_TOP_CFGERRTLPCPLHEADER28" + ], + [ + "PCIE_PL2RECOVERY", + "PCIE_TOP_PL2RECOVERY" + ], + [ + "PCIE_CFGERRTLPCPLHEADER32", + "PCIE_TOP_CFGERRTLPCPLHEADER32" + ], + [ + "PCIE_CFGERRTLPCPLHEADER44", + "PCIE_TOP_CFGERRTLPCPLHEADER44" + ], + [ + "PCIE_CFGVCTCVCMAP0", + "PCIE_TOP_CFGVCTCVCMAP0" + ], + [ + "PCIE_TRNRD83", + "PCIE_TOP_TRNRD83" + ], + [ + "PCIE_TRNTD22", + "PCIE_TOP_TRNTD22" + ], + [ + "PCIE_DRPDO4", + "PCIE_TOP_DRPDO4" + ], + [ + "PCIE_CFGDEVID14", + "PCIE_TOP_CFGDEVID14" + ], + [ + "PCIE_TRNRD76", + "PCIE_TOP_TRNRD76" + ], + [ + "PCIE_CFGDSN62", + "PCIE_TOP_CFGDSN62" + ], + [ + "PCIE_MIMRXWDATA26", + "PCIE_TOP_MIMRXWDATA26" + ], + [ + "PCIE_PIPERX4DATA1", + "PCIE_TOP_PIPERX4DATA1" + ], + [ + "PCIE_MIMRXWDATA34", + "PCIE_TOP_MIMRXWDATA34" + ], + [ + "PCIE_MIMRXRDATA30", + "PCIE_TOP_MIMRXRDATA30" + ], + [ + "PCIE_CFGTRANSACTIONADDR0", + "PCIE_TOP_CFGTRANSACTIONADDR0" + ], + [ + "PCIE_SCANENABLEN", + "PCIE_TOP_SCANENABLEN" + ], + [ + "PCIE_CFGERRTLPCPLHEADER29", + "PCIE_TOP_CFGERRTLPCPLHEADER29" + ], + [ + "PCIE_TRNRDLLPDATA48", + "PCIE_TOP_TRNRDLLPDATA48" + ], + [ + "PCIE_CFGERRTLPCPLHEADER33", + "PCIE_TOP_CFGERRTLPCPLHEADER33" + ], + [ + "PCIE_TRNTD30", + "PCIE_TOP_TRNTD30" + ], + [ + "PCIE_MIMRXRDATA34", + "PCIE_TOP_MIMRXRDATA34" + ], + [ + "PCIE_MIMRXWDATA7", + "PCIE_TOP_MIMRXWDATA7" + ], + [ + "PCIE_CFGERRTLPCPLHEADER36", + "PCIE_TOP_CFGERRTLPCPLHEADER36" + ], + [ + "PCIE_TRNRDLLPDATA44", + "PCIE_TOP_TRNRDLLPDATA44" + ], + [ + "PCIE_CFGDEVID8", + "PCIE_TOP_CFGDEVID8" + ], + [ + "PCIE_MIMRXREN", + "PCIE_TOP_MIMRXREN" + ], + [ + "PCIE_CFGERRAERHEADERLOG7", + "PCIE_TOP_CFGERRAERHEADERLOG7" + ], + [ + "PCIE_DBGVECA14", + "PCIE_TOP_DBGVECA14" + ], + [ + "PCIE_MIMRXRDATA36", + "PCIE_TOP_MIMRXRDATA36" + ], + [ + "PCIE_DRPDI13", + "PCIE_TOP_DRPDI13" + ], + [ + "PCIE_TRNRDLLPDATA37", + "PCIE_TOP_TRNRDLLPDATA37" + ], + [ + "PCIE_DBGVECA7", + "PCIE_TOP_DBGVECA7" + ], + [ + "PCIE_DBGVECA8", + "PCIE_TOP_DBGVECA8" + ], + [ + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL2", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2" + ], + [ + "PCIE_LL2TFCINIT2SEQ", + "PCIE_TOP_LL2TFCINIT2SEQ" + ], + [ + "PCIE_DRPDI6", + "PCIE_TOP_DRPDI6" + ], + [ + "PCIE_CFGTRANSACTIONADDR4", + "PCIE_TOP_CFGTRANSACTIONADDR4" + ], + [ + "PCIE_DBGVECA12", + "PCIE_TOP_DBGVECA12" + ], + [ + "PCIE_TRNTDLLPDATA29", + "PCIE_TOP_TRNTDLLPDATA29" + ], + [ + "PCIE_PIPERX4DATA2", + "PCIE_TOP_PIPERX4DATA2" + ], + [ + "PCIE_TRNRD72", + "PCIE_TOP_TRNRD72" + ], + [ + "PCIE_CFGMGMTDO16", + "PCIE_TOP_CFGMGMTDO16" + ], + [ + "PCIE_DRPDI1", + "PCIE_TOP_DRPDI1" + ], + [ + "PCIE_MIMRXRDATA55", + "PCIE_TOP_MIMRXRDATA55" + ], + [ + "PCIE_TRNTDLLPDATA28", + "PCIE_TOP_TRNTDLLPDATA28" + ], + [ + "PCIE_DBGVECA16", + "PCIE_TOP_DBGVECA16" + ], + [ + "PCIE_CFGVCTCVCMAP6", + "PCIE_TOP_CFGVCTCVCMAP6" + ], + [ + "PCIE_CFGMGMTDO20", + "PCIE_TOP_CFGMGMTDO20" + ], + [ + "PCIE_TRNTD40", + "PCIE_TOP_TRNTD40" + ], + [ + "PCIE_MIMRXRDATA51", + "PCIE_TOP_MIMRXRDATA51" + ], + [ + "PCIE_XILUNCONNOUT28", + "PCIE_TOP_XILUNCONNOUT28" + ], + [ + "PCIE_CFGDEVID12", + "PCIE_TOP_CFGDEVID12" + ], + [ + "PCIE_MIMRXRDATA21", + "PCIE_TOP_MIMRXRDATA21" + ], + [ + "PCIE_MIMRXWDATA10", + "PCIE_TOP_MIMRXWDATA10" + ], + [ + "PCIE_MIMRXRADDR4", + "PCIE_TOP_MIMRXRADDR4" + ], + [ + "PCIE_TRNRDLLPDATA60", + "PCIE_TOP_TRNRDLLPDATA60" + ], + [ + "PCIE_CFGMGMTDO26", + "PCIE_TOP_CFGMGMTDO26" + ], + [ + "PCIE_MIMRXWDATA17", + "PCIE_TOP_MIMRXWDATA17" + ], + [ + "PCIE_MIMRXRDATA24", + "PCIE_TOP_MIMRXRDATA24" + ], + [ + "PCIE_DBGVECA21", + "PCIE_TOP_DBGVECA21" + ], + [ + "PCIE_PIPERX4DATA6", + "PCIE_TOP_PIPERX4DATA6" + ], + [ + "PCIE_LL2SUSPENDNOW", + "PCIE_TOP_LL2SUSPENDNOW" + ], + [ + "PCIE_TRNTD17", + "PCIE_TOP_TRNTD17" + ], + [ + "PCIE_TRNRDLLPDATA46", + "PCIE_TOP_TRNRDLLPDATA46" + ], + [ + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL0", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0" + ], + [ + "PCIE_MIMRXRDATA23", + "PCIE_TOP_MIMRXRDATA23" + ], + [ + "PCIE_MIMRXRADDR0", + "PCIE_TOP_MIMRXRADDR0" + ], + [ + "PCIE_CFGMGMTDO29", + "PCIE_TOP_CFGMGMTDO29" + ], + [ + "PCIE_DRPDI9", + "PCIE_TOP_DRPDI9" + ], + [ + "PCIE_CFGERRAERHEADERLOG4", + "PCIE_TOP_CFGERRAERHEADERLOG4" + ], + [ + "PCIE_SCANMODEN", + "PCIE_TOP_SCANMODEN" + ], + [ + "PCIE_MIMRXWDATA32", + "PCIE_TOP_MIMRXWDATA32" + ], + [ + "PCIE_CFGDEVID5", + "PCIE_TOP_CFGDEVID5" + ], + [ + "PCIE_CFGDSN63", + "PCIE_TOP_CFGDSN63" + ], + [ + "PCIE_CFGERRTLPCPLHEADER27", + "PCIE_TOP_CFGERRTLPCPLHEADER27" + ], + [ + "PCIE_CFGDEVID4", + "PCIE_TOP_CFGDEVID4" + ], + [ + "PCIE_TRNRD78", + "PCIE_TOP_TRNRD78" + ], + [ + "PCIE_CFGDEVID0", + "PCIE_TOP_CFGDEVID0" + ], + [ + "PCIE_CFGLINKCONTROLHWAUTOWIDTHDIS", + "PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS" + ], + [ + "PCIE_CFGLINKCONTROLBANDWIDTHINTEN", + "PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN" + ], + [ + "PCIE_CFGAERROOTERRCORRERRRECEIVED", + "PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED" + ], + [ + "PCIE_TRNRD88", + "PCIE_TOP_TRNRD88" + ], + [ + "PCIE_TRNTD14", + "PCIE_TOP_TRNTD14" + ], + [ + "PCIE_CFGDEVID11", + "PCIE_TOP_CFGDEVID11" + ], + [ + "PCIE_CFGTRANSACTIONADDR1", + "PCIE_TOP_CFGTRANSACTIONADDR1" + ], + [ + "PCIE_DRPDI5", + "PCIE_TOP_DRPDI5" + ], + [ + "PCIE_TRNTD37", + "PCIE_TOP_TRNTD37" + ], + [ + "PCIE_CFGERRAERHEADERLOG5", + "PCIE_TOP_CFGERRAERHEADERLOG5" + ], + [ + "PCIE_MIMRXWDATA12", + "PCIE_TOP_MIMRXWDATA12" + ], + [ + "PCIE_CFGLINKCONTROLCOMMONCLOCK", + "PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK" + ], + [ + "PCIE_CFGDSN58", + "PCIE_TOP_CFGDSN58" + ], + [ + "PCIE_CFGLINKCONTROLLINKDISABLE", + "PCIE_TOP_CFGLINKCONTROLLINKDISABLE" + ], + [ + "PCIE_TRNRD89", + "PCIE_TOP_TRNRD89" + ], + [ + "PCIE_TRNTD9", + "PCIE_TOP_TRNTD9" + ], + [ + "PCIE_PIPERX4DATA5", + "PCIE_TOP_PIPERX4DATA5" + ], + [ + "PCIE_CFGLINKCONTROLAUTOBANDWIDTHINTEN", + "PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN" + ], + [ + "PCIE_DBGVECA4", + "PCIE_TOP_DBGVECA4" + ], + [ + "PCIE_DRPDI12", + "PCIE_TOP_DRPDI12" + ], + [ + "PCIE_DRPRDY", + "PCIE_TOP_DRPRDY" + ], + [ + "PCIE_MIMRXRDATA45", + "PCIE_TOP_MIMRXRDATA45" + ], + [ + "PCIE_TRNTDLLPDATA21", + "PCIE_TOP_TRNTDLLPDATA21" + ], + [ + "PCIE_CFGTRANSACTION", + "PCIE_TOP_CFGTRANSACTION" + ], + [ + "PCIE_CFGDEVCONTROL2ARIFORWARDEN", + "PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN" + ], + [ + "PCIE_MIMRXRDATA42", + "PCIE_TOP_MIMRXRDATA42" + ], + [ + "PCIE_TRNRDLLPDATA50", + "PCIE_TOP_TRNRDLLPDATA50" + ], + [ + "PCIE_CFGERRAERHEADERLOG9", + "PCIE_TOP_CFGERRAERHEADERLOG9" + ], + [ + "PCIE_MIMRXWDATA29", + "PCIE_TOP_MIMRXWDATA29" + ], + [ + "PCIE_CFGERRAERHEADERLOG11", + "PCIE_TOP_CFGERRAERHEADERLOG11" + ], + [ + "PCIE_MIMRXWDATA6", + "PCIE_TOP_MIMRXWDATA6" + ], + [ + "PCIE_TRNRD63", + "PCIE_TOP_TRNRD63" + ], + [ + "PCIE_DRPADDR7", + "PCIE_TOP_DRPADDR7" + ], + [ + "PCIE_MIMRXWADDR5", + "PCIE_TOP_MIMRXWADDR5" + ], + [ + "PCIE_CFGLINKCONTROLRETRAINLINK", + "PCIE_TOP_CFGLINKCONTROLRETRAINLINK" + ], + [ + "PCIE_TL2ASPMSUSPENDCREDITCHECK", + "PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK" + ], + [ + "PCIE_TRNTD28", + "PCIE_TOP_TRNTD28" + ], + [ + "PCIE_TRNTD35", + "PCIE_TOP_TRNTD35" + ], + [ + "PCIE_CFGMGMTDO28", + "PCIE_TOP_CFGMGMTDO28" + ], + [ + "PCIE_EDTUPDATE", + "PCIE_TOP_EDTUPDATE" + ], + [ + "PCIE_CFGCOMMANDINTERRUPTDISABLE", + "PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE" + ], + [ + "PCIE_PL2DIRECTEDLSTATE4", + "PCIE_TOP_PL2DIRECTEDLSTATE4" + ], + [ + "PCIE_TRNRD90", + "PCIE_TOP_TRNRD90" + ], + [ + "PCIE_DBGVECA1", + "PCIE_TOP_DBGVECA1" + ], + [ + "PCIE_TRNRD95", + "PCIE_TOP_TRNRD95" + ], + [ + "PCIE_TRNRDLLPSRCRDY0", + "PCIE_TOP_TRNRDLLPSRCRDY0" + ], + [ + "PCIE_CFGDSN60", + "PCIE_TOP_CFGDSN60" + ], + [ + "PCIE_TRNRDLLPDATA35", + "PCIE_TOP_TRNRDLLPDATA35" + ], + [ + "PCIE_TRNRD94", + "PCIE_TOP_TRNRD94" + ], + [ + "PCIE_PIPETXMARGIN2", + "PCIE_TOP_PIPETXMARGIN2" + ], + [ + "PCIE_TRNTD24", + "PCIE_TOP_TRNTD24" + ], + [ + "PCIE_TRNTDLLPDATA26", + "PCIE_TOP_TRNTDLLPDATA26" + ], + [ + "PCIE_CFGERRTLPCPLHEADER43", + "PCIE_TOP_CFGERRTLPCPLHEADER43" + ], + [ + "PCIE_TRNRDLLPDATA36", + "PCIE_TOP_TRNRDLLPDATA36" + ], + [ + "PCIE_MIMRXRDATA47", + "PCIE_TOP_MIMRXRDATA47" + ], + [ + "PCIE_TRNRD97", + "PCIE_TOP_TRNRD97" + ], + [ + "PCIE_CFGERRTLPCPLHEADER42", + "PCIE_TOP_CFGERRTLPCPLHEADER42" + ], + [ + "PCIE_TRNRDLLPDATA58", + "PCIE_TOP_TRNRDLLPDATA58" + ], + [ + "PCIE_MIMRXRADDR11", + "PCIE_TOP_MIMRXRADDR11" + ], + [ + "PCIE_PL2DIRECTEDLSTATE1", + "PCIE_TOP_PL2DIRECTEDLSTATE1" + ], + [ + "PCIE_TRNTDSTRDY3", + "PCIE_TOP_TRNTDSTRDY3" + ], + [ + "PCIE_CFGVCTCVCMAP5", + "PCIE_TOP_CFGVCTCVCMAP5" + ], + [ + "PCIE_MIMRXWDATA13", + "PCIE_TOP_MIMRXWDATA13" + ], + [ + "PCIE_PIPERX0PHYSTATUS", + "PCIE_TOP_PIPERX0PHYSTATUS" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_TOP" + ] + }, + { + "grid_deltas": [ + 0, + 4 + ], + "wire_pairs": [ + [ + "BRKH_CLK_R_CK_GCLK24", + "CLK_BUFG_CK_GCLK24" + ], + [ + "BRKH_CLK_R_CK_GCLK23", + "CLK_BUFG_CK_GCLK23" + ], + [ + "BRKH_CLK_R_CK_GCLK0", + "CLK_BUFG_CK_GCLK0" + ], + [ + "BRKH_CLK_R_CK_GCLK25", + "CLK_BUFG_CK_GCLK25" + ], + [ + "BRKH_CLK_R_CK_GCLK27", + "CLK_BUFG_CK_GCLK27" + ], + [ + "BRKH_CLK_R_CK_GCLK11", + "CLK_BUFG_CK_GCLK11" + ], + [ + "BRKH_CLK_R_CK_GCLK2", + "CLK_BUFG_CK_GCLK2" + ], + [ + "BRKH_CLK_R_CK_GCLK8", + "CLK_BUFG_CK_GCLK8" + ], + [ + "BRKH_CLK_R_CK_GCLK21", + "CLK_BUFG_CK_GCLK21" + ], + [ + "BRKH_CLK_R_CK_GCLK3", + "CLK_BUFG_CK_GCLK3" + ], + [ + "BRKH_CLK_R_CK_GCLK14", + "CLK_BUFG_CK_GCLK14" + ], + [ + "BRKH_CLK_R_CK_GCLK13", + "CLK_BUFG_CK_GCLK13" + ], + [ + "BRKH_CLK_R_CK_GCLK30", + "CLK_BUFG_CK_GCLK30" + ], + [ + "BRKH_CLK_R_CK_GCLK29", + "CLK_BUFG_CK_GCLK29" + ], + [ + "BRKH_CLK_R_CK_GCLK19", + "CLK_BUFG_CK_GCLK19" + ], + [ + "BRKH_CLK_R_CK_GCLK17", + "CLK_BUFG_CK_GCLK17" + ], + [ + "BRKH_CLK_R_CK_GCLK7", + "CLK_BUFG_CK_GCLK7" + ], + [ + "BRKH_CLK_R_CK_GCLK20", + "CLK_BUFG_CK_GCLK20" + ], + [ + "BRKH_CLK_R_CK_GCLK5", + "CLK_BUFG_CK_GCLK5" + ], + [ + "BRKH_CLK_R_CK_GCLK10", + "CLK_BUFG_CK_GCLK10" + ], + [ + "BRKH_CLK_R_CK_GCLK16", + "CLK_BUFG_CK_GCLK16" + ], + [ + "BRKH_CLK_R_CK_GCLK1", + "CLK_BUFG_CK_GCLK1" + ], + [ + "BRKH_CLK_R_CK_GCLK12", + "CLK_BUFG_CK_GCLK12" + ], + [ + "BRKH_CLK_R_CK_GCLK15", + "CLK_BUFG_CK_GCLK15" + ], + [ + "BRKH_CLK_R_CK_GCLK22", + "CLK_BUFG_CK_GCLK22" + ], + [ + "BRKH_CLK_R_CK_GCLK9", + "CLK_BUFG_CK_GCLK9" + ], + [ + "BRKH_CLK_R_CK_GCLK18", + "CLK_BUFG_CK_GCLK18" + ], + [ + "BRKH_CLK_R_CK_GCLK6", + "CLK_BUFG_CK_GCLK6" + ], + [ + "BRKH_CLK_R_CK_GCLK4", + "CLK_BUFG_CK_GCLK4" + ], + [ + "BRKH_CLK_R_CK_GCLK26", + "CLK_BUFG_CK_GCLK26" + ], + [ + "BRKH_CLK_R_CK_GCLK28", + "CLK_BUFG_CK_GCLK28" + ], + [ + "BRKH_CLK_R_CK_GCLK31", + "CLK_BUFG_CK_GCLK31" + ] + ], + "tile_types": [ + "BRKH_CLK", + "CLK_BUFG_BOT_R" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "IOI_IMUX11_0", + "TERM_INT_IMUX11" + ], + [ + "IOI_IMUX43_0", + "TERM_INT_IMUX43" + ], + [ + "IOI_FAN1_0", + "TERM_INT_FAN1" + ], + [ + "IOI_CTRL1_0", + "TERM_INT_CTRL1" + ], + [ + "IOI_LOGIC_OUTS18_0", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_BYP2_0", + "TERM_INT_BYP2" + ], + [ + "IOI_LOGIC_OUTS2_0", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_IMUX6_0", + "TERM_INT_IMUX6" + ], + [ + "IOI_IMUX36_0", + "TERM_INT_IMUX36" + ], + [ + "IOI_IMUX34_0", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX0_0", + "TERM_INT_IMUX0" + ], + [ + "IOI_IMUX46_0", + "TERM_INT_IMUX46" + ], + [ + "IOI_IMUX20_0", + "TERM_INT_IMUX20" + ], + [ + "IOI_LOGIC_OUTS23_0", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_LOGIC_OUTS15_0", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX19_0", + "TERM_INT_IMUX19" + ], + [ + "IOI_IMUX47_0", + "TERM_INT_IMUX47" + ], + [ + "IOI_LOGIC_OUTS17_0", + "TERM_INT_LOGIC_OUTS_L_B17" + ], + [ + "IOI_IMUX25_0", + "TERM_INT_IMUX25" + ], + [ + "IOI_LOGIC_OUTS7_0", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_FAN2_0", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX45_0", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX31_0", + "TERM_INT_IMUX31" + ], + [ + "IOI_LOGIC_OUTS19_0", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_IMUX1_0", + "TERM_INT_IMUX1" + ], + [ + "IOI_IMUX22_0", + "TERM_INT_IMUX22" + ], + [ + "IOI_IMUX12_0", + "TERM_INT_IMUX12" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_BLOCK_OUTS2_0", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "IOI_IMUX40_0", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX10_0", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX16_0", + "TERM_INT_IMUX16" + ], + [ + "IOI_FAN0_0", + "TERM_INT_FAN0" + ], + [ + "IOI_IMUX38_0", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX26_0", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX3_0", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX24_0", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX37_0", + "TERM_INT_IMUX37" + ], + [ + "IOI_LOGIC_OUTS3_0", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_FAN4_0", + "TERM_INT_FAN4" + ], + [ + "IOI_FAN6_0", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX7_0", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX39_0", + "TERM_INT_IMUX39" + ], + [ + "IOI_CTRL0_0", + "TERM_INT_CTRL0" + ], + [ + "IOI_CLK0_0", + "TERM_INT_CLK0" + ], + [ + "IOI_CLK1_0", + "TERM_INT_CLK1" + ], + [ + "IOI_FAN7_0", + "TERM_INT_FAN7" + ], + [ + "IOI_BYP0_0", + "TERM_INT_BYP0" + ], + [ + "IOI_LOGIC_OUTS0_0", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_LOGIC_OUTS21_0", + "TERM_INT_LOGIC_OUTS_L_B21" + ], + [ + "IOI_LOGIC_OUTS6_0", + "TERM_INT_LOGIC_OUTS_L_B6" + ], + [ + "IOI_IMUX8_0", + "TERM_INT_IMUX8" + ], + [ + "IOI_LOGIC_OUTS11_0", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_BYP6_0", + "TERM_INT_BYP6" + ], + [ + "IOI_IMUX42_0", + "TERM_INT_IMUX42" + ], + [ + "IOI_IMUX30_0", + "TERM_INT_IMUX30" + ], + [ + "IOI_LOGIC_OUTS1_0", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX5_0", + "TERM_INT_IMUX5" + ], + [ + "IOI_IMUX4_0", + "TERM_INT_IMUX4" + ], + [ + "IOI_IMUX17_0", + "TERM_INT_IMUX17" + ], + [ + "IOI_IMUX23_0", + "TERM_INT_IMUX23" + ], + [ + "IOI_IMUX33_0", + "TERM_INT_IMUX33" + ], + [ + "IOI_PHASER_TO_IO_ICLK", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_FAN5_0", + "TERM_INT_FAN5" + ], + [ + "IOI_BYP1_0", + "TERM_INT_BYP1" + ], + [ + "IOI_LOGIC_OUTS9_0", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_LOGIC_OUTS14_0", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_IMUX13_0", + "TERM_INT_IMUX13" + ], + [ + "IOI_IMUX44_0", + "TERM_INT_IMUX44" + ], + [ + "IOI_LOGIC_OUTS20_0", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_LOGIC_OUTS5_0", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_IMUX27_0", + "TERM_INT_IMUX27" + ], + [ + "IOI_IMUX18_0", + "TERM_INT_IMUX18" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_IMUX9_0", + "TERM_INT_IMUX9" + ], + [ + "IOI_BLOCK_OUTS1_0", + "TERM_INT_BLOCK_OUTS_L_B1" + ], + [ + "IOI_FAN3_0", + "TERM_INT_FAN3" + ], + [ + "IOI_BYP5_0", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS8_0", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_PHASER_TO_IO_OCLK", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_LOGIC_OUTS4_0", + "TERM_INT_LOGIC_OUTS_L_B4" + ], + [ + "IOI_BYP4_0", + "TERM_INT_BYP4" + ], + [ + "IOI_BYP7_0", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_0", + "TERM_INT_IMUX2" + ], + [ + "IOI_IMUX35_0", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP3_0", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX15_0", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX29_0", + "TERM_INT_IMUX29" + ], + [ + "IOI_LOGIC_OUTS10_0", + "TERM_INT_LOGIC_OUTS_L_B10" + ], + [ + "IOI_LOGIC_OUTS12_0", + "TERM_INT_LOGIC_OUTS_L_B12" + ], + [ + "IOI_IMUX14_0", + "TERM_INT_IMUX14" + ], + [ + "IOI_IMUX21_0", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX28_0", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX41_0", + "TERM_INT_IMUX41" + ], + [ + "IOI_BLOCK_OUTS0_0", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_IMUX32_0", + "TERM_INT_IMUX32" + ] + ], + "tile_types": [ + "RIOI_SING", + "R_TERM_INT" + ] + }, + { + "grid_deltas": [ + 0, + 12 + ], + "wire_pairs": [ + [ + "GTXE2_CHANNEL_RXOUTCLK_3", + "GTXE2_COMMON_RXOUTCLK_3" + ], + [ + "GTXE2_CHANNEL_QPLLCLK", + "GTXE2_COMMON_QPLLOUTCLK" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_3", + "GTXE2_COMMON_TXOUTCLK_3" + ], + [ + "GTXE2_CHANNEL_SOUTHREFCLK1", + "GTXE2_COMMON_SOUTHREFCLK1" + ], + [ + "GTXE2_CHANNEL_RXOUTCLK_0", + "GTXE2_COMMON_RXOUTCLK_0" + ], + [ + "GTXE2_CHANNEL_RXOUTCLK_2", + "GTXE2_COMMON_RXOUTCLK_2" + ], + [ + "GTXE2_CHANNEL_NORTHREFCLK0", + "GTXE2_COMMON_NORTHREFCLK0" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_2", + "GTXE2_COMMON_TXOUTCLK_2" + ], + [ + "GTXE2_CHANNEL_REFCLK1", + "GTXE2_COMMON_REFCLK1" + ], + [ + "GTXE2_CHANNEL_REFCLK0", + "GTXE2_COMMON_REFCLK0" + ], + [ + "GTXE2_CHANNEL_NORTHREFCLK1", + "GTXE2_COMMON_NORTHREFCLK1" + ], + [ + "GTXE2_CHANNEL_SOUTHREFCLK0", + "GTXE2_COMMON_SOUTHREFCLK0" + ], + [ + "GTXE2_CHANNEL_QPLLREFCLK", + "GTXE2_COMMON_QPLLOUTREFCLK" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_0", + "GTXE2_COMMON_TXOUTCLK_0" + ], + [ + "GTXE2_CHANNEL_RXOUTCLK_1", + "GTXE2_COMMON_RXOUTCLK_1" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_1", + "GTXE2_COMMON_TXOUTCLK_1" + ] + ], + "tile_types": [ + "GTX_CHANNEL_2", + "GTX_COMMON" + ] + }, + { + "grid_deltas": [ + 5, + 7 + ], + "wire_pairs": [ + [ + "PCIE_CLK0_L_3", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_IMUX22_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_IMUX5_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_EE4A2_3", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_SE4BEG3_3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_WR1END0_3", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_NW4A2_3", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_NE4C0_3", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_IMUX29_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_IMUX3_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_IMUX40_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_EE2A0_3", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_WW2A0_3", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_WW2END1_3", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_IMUX38_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_WW2A2_3", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_IMUX6_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_SE4C2_3", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_IMUX34_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_CTRL0_L_3", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_WW4B0_3", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_IMUX42_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_WW4END3_3", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_FAN4_L_3", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_SW4A1_3", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_WW4B1_3", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_LH9_3", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_NE4C2_3", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_WW4C2_3", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_IMUX43_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_WL1END0_3", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_SW2A2_3", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_WR1END3_3", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_NE2A3_3", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_LH11_3", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_NW4END3_3", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_WW4END1_3", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_EE4BEG2_3", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_EE2BEG0_3", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_IMUX21_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_IMUX37_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_FAN6_L_3", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_BYP1_L_3", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_SE2A2_3", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_IMUX12_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_EL1BEG3_3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_IMUX2_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_WW2A3_3", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_EE4A0_3", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_NE4BEG1_3", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX30_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_IMUX28_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_SE4C3_3", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_LH4_3", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_SW4A0_3", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_NE2A2_3", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_ER1BEG0_3", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_WW4A1_3", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_NW4END0_3", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_WW2END2_3", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_EE2A2_3", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_LH12_3", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_SW4END1_3", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_IMUX31_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_WW2END3_3", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_LH7_3", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_EL1BEG2_3", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_WW4B3_3", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_FAN7_L_3", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_SW2A3_3", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX44_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_NE4C1_3", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_SE2A3_3", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_IMUX26_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_NW4A1_3", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_NW2A1_3", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_SE4BEG0_3", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_IMUX9_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_IMUX1_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_SE4BEG2_3", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_WW4A3_3", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_MONITOR_P_3", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_IMUX16_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_IMUX45_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_NW2A3_3", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_EE4C1_3", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_EE4B3_3", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_WW4END2_3", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_CTRL1_L_3", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_LH10_3", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_IMUX41_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_EE2BEG1_3", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_FAN5_L_3", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_NW4A0_3", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WW4A0_3", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_BYP3_L_3", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_NW2A2_3", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_SE4C0_3", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_BYP2_L_3", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_WL1END3_3", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_LH1_3", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_NE2A1_3", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_IMUX33_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_WW4A2_3", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_WW4B2_3", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_IMUX20_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_EE2BEG3_3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_LH3_3", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_SW4A3_3", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_WW4C1_3", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_WL1END1_3", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_BYP6_L_3", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_SE4C1_3", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_NW4END1_3", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_IMUX18_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_NE4BEG0_3", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_BYP5_L_3", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_FAN3_L_3", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_EE4A1_3", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_EE4BEG3_3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_IMUX23_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_IMUX14_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_SE2A0_3", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_WR1END2_3", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_NE4BEG2_3", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_SW4END3_3", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_MONITOR_N_3", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_SE4BEG1_3", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_IMUX11_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_EE4BEG1_3", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LH8_3", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4C3_3", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_IMUX35_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_IMUX10_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_IMUX27_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_IMUX46_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_NW4END2_3", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_SW2A0_3", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_EL1BEG0_3", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_NW2A0_3", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_EE4BEG0_3", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_NE4C3_3", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_NE2A0_3", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_LH2_3", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_BYP4_L_3", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_WW4END0_3", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_IMUX4_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_IMUX0_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_EE4B0_3", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX13_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_WL1END2_3", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_IMUX39_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_SW4END0_3", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_IMUX19_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_SW2A1_3", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_LH6_3", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_NE4BEG3_3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_EE4C2_3", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_ER1BEG1_3", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_SW4A2_3", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_NW4A3_3", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_FAN1_L_3", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_EE2BEG2_3", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_ER1BEG3_3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_IMUX24_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_IMUX17_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_WW4C3_3", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_BYP0_L_3", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_SW4END2_3", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_EE4C0_3", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_EL1BEG1_3", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_EE4B2_3", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_CLK1_L_3", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_WW4C0_3", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_LH5_3", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_EE4A3_3", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_IMUX15_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_FAN0_L_3", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_EE2A1_3", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_WW2END0_3", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_FAN2_L_3", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_BYP7_L_3", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_WW2A1_3", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_WR1END1_3", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_IMUX36_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_ER1BEG2_3", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_IMUX7_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_SE2A1_3", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_3", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_IMUX8_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_IMUX32_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_IMUX25_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_EE4B1_3", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_EE2A3_3", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_IMUX47_L_3", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "CLK_HROW_IMUX18_0", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_IMUX39_0", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_IMUX5_0", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_FAN1_0", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_WW4A2_0", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_EE2BEG2_0", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_SE4BEG2_0", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_MONITOR_P_0", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_HROW_BYP5_0", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_IMUX19_0", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_NW2A2_0", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_FAN3_0", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_EE4A2_0", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_ER1BEG3_0", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_WR1END0_0", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_WW2A0_0", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4BEG2_0", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_CLK1_0", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_IMUX30_0", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_SW4A2_0", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_LH2_0", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_WW4A3_0", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_IMUX6_0", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_NE2A0_0", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_IMUX22_0", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_EE4BEG1_0", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_SW2A2_0", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_IMUX40_0", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_BYP4_0", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_EE4B3_0", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_IMUX14_0", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_EE2BEG0_0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_SE4C2_0", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_BYP7_0", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_SW4END0_0", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_EE4A0_0", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_SE4C3_0", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_IMUX16_0", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_BYP2_0", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_SE4BEG1_0", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_SW4A0_0", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_EE2BEG1_0", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_BYP6_0", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_IMUX1_0", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_IMUX37_0", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_FAN4_0", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_IMUX7_0", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_IMUX34_0", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_IMUX12_0", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_WL1END1_0", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_WW2END3_0", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_EL1BEG3_0", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_IMUX46_0", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_IMUX24_0", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_IMUX26_0", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_EE2BEG3_0", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_BYP3_0", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_WW4END3_0", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_NE4BEG3_0", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_EE2A0_0", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_IMUX8_0", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_IMUX35_0", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_IMUX28_0", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_IMUX32_0", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_SE4BEG0_0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_WW4C2_0", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_LH5_0", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_EL1BEG2_0", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_IMUX21_0", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_NW2A3_0", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_IMUX27_0", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_NE4C1_0", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_EE4C1_0", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_WW4END2_0", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_EE4BEG3_0", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_NE2A3_0", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_NW4END1_0", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_IMUX20_0", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_SW4END1_0", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_WW2A1_0", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_SW4END2_0", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_EE4C3_0", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_IMUX17_0", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_IMUX42_0", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_NW4END0_0", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_SW2A0_0", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_SW4A1_0", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_IMUX15_0", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_WW2A2_0", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_NE4C2_0", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_IMUX0_0", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_IMUX38_0", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_NW4A1_0", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_IMUX41_0", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_WW4END0_0", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_IMUX10_0", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_WW4C0_0", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_IMUX43_0", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_WW4A1_0", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_IMUX4_0", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_LH6_0", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_SW4END3_0", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_IMUX45_0", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_SE4C0_0", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_SE2A3_0", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_EE4A3_0", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_EE4B0_0", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_WW2A3_0", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_WW4A0_0", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_IMUX11_0", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_IMUX31_0", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_EE4A1_0", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_ER1BEG2_0", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_IMUX2_0", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_WW4C1_0", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_WL1END3_0", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_LH11_0", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_LH12_0", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_EE4BEG0_0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_IMUX47_0", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_IMUX13_0", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_NW4A0_0", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_MONITOR_N_0", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_HROW_WW4B1_0", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_WL1END2_0", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_EL1BEG0_0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_EE2A3_0", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_LH3_0", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_NE4BEG1_0", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_SE4C1_0", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_BYP1_0", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_WW2END0_0", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_NE4BEG2_0", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_NE4C3_0", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_SW2A1_0", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_WL1END0_0", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_NW4END3_0", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_CTRL0_0", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_CTRL1_0", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_WR1END2_0", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_WW4C3_0", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_EE2A2_0", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_LH9_0", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_EL1BEG1_0", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_IMUX33_0", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_IMUX44_0", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_BYP0_0", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_WR1END1_0", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_ER1BEG0_0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_FAN6_0", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_WW4END1_0", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_NE2A1_0", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_IMUX3_0", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_NW2A0_0", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_WW2END1_0", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_LH4_0", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_ER1BEG1_0", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_SE4BEG3_0", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_FAN7_0", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_FAN0_0", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_NE4C0_0", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_EE2A1_0", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_WW4B2_0", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_LH1_0", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_WW2END2_0", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_WW4B3_0", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_FAN2_0", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_SE2A2_0", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_LH10_0", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_IMUX9_0", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_NW2A1_0", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_IMUX36_0", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_NE2A2_0", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_EE4B2_0", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_FAN5_0", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_NE4BEG0_0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_IMUX23_0", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_SW2A3_0", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_SE2A0_0", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_SW4A3_0", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_NW4A2_0", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_EE4B1_0", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_LH7_0", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_IMUX29_0", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_NW4END2_0", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_NW4A3_0", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WR1END3_0", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_CLK0_0", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_WW4B0_0", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_LH8_0", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_SE2A1_0", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_EE4C2_0", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_IMUX25_0", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_EE4C0_0", + "INT_INTERFACE_EE4C0" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -5 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW4B1_13", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4BEG0_13", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_EE2BEG3_13", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH10_13", + "VBRK_LH10" + ], + [ + "CMT_TOP_NW4A1_13", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NW2A3_13", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW2END2_13", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2END3_13", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4C0_13", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_NW4END1_13", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW4C2_13", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW4END0_13", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NE2A3_13", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_LH9_13", + "VBRK_LH9" + ], + [ + "CMT_TOP_LH2_13", + "VBRK_LH2" + ], + [ + "CMT_TOP_SW2A0_13", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4C2_13", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EE4A3_13", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_LH1_13", + "VBRK_LH1" + ], + [ + "CMT_TOP_SW4END3_13", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NW2A2_13", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A2_13", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE2A0_13", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4B0_13", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_LH11_13", + "VBRK_LH11" + ], + [ + "CMT_TOP_SW4A2_13", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW2A1_13", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH3_13", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4BEG0_13", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE2A1_13", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW2END1_13", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2A2_13", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END0_13", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW4END2_13", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WR1END1_13", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH5_13", + "VBRK_LH5" + ], + [ + "CMT_TOP_SE4BEG3_13", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_MONITOR_P_13", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_EE2BEG1_13", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4C0_13", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SE4BEG1_13", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH8_13", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW2A2_13", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4A3_13", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2A3_13", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_NW4A0_13", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NW4A3_13", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WW2END0_13", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4B0_13", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE2A0_13", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_WW4B3_13", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_LH6_13", + "VBRK_LH6" + ], + [ + "CMT_TOP_NE4BEG3_13", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_LH12_13", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE2A3_13", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG2_13", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW2A3_13", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4C3_13", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WL1END3_13", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_ER1BEG2_13", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2BEG0_13", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW2A0_13", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WW4END0_13", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WR1END2_13", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A2_13", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4BEG2_13", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NE4BEG1_13", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SE4C0_13", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4C3_13", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_LH7_13", + "VBRK_LH7" + ], + [ + "CMT_TOP_ER1BEG0_13", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END1_13", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_13", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_NE2A0_13", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NE4C3_13", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW4A0_13", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NW2A0_13", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WR1END3_13", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SW4END2_13", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_WW4A3_13", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_NE2A1_13", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C1_13", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SE2A2_13", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2A1_13", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE4C1_13", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE4C2_13", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4C1_13", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_EL1BEG0_13", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_EE4A1_13", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EE2A1_13", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_SE4C2_13", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4END1_13", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SW4END0_13", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_NW2A1_13", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4END2_13", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_SE4C1_13", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE4BEG1_13", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EE4A0_13", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_LH4_13", + "VBRK_LH4" + ], + [ + "CMT_TOP_SW4A1_13", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4END3_13", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE2BEG2_13", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SW2A3_13", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_13", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4BEG0_13", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SW4A0_13", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_ER1BEG1_13", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE4A2_13", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4A1_13", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_MONITOR_N_13", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW4END3_13", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4C3_13", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4B1_13", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_EE4BEG3_13", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4BEG2_13", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW2A2_13", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG1_13", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_ER1BEG3_13", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WR1END0_13", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WL1END1_13", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW4B2_13", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4C0_13", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EL1BEG2_13", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WL1END2_13", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B3_13", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4B2_13", + "VBRK_EE4B2" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 5 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW2END1_5", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE2A0_5", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_SW2A1_5", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_SW2A2_5", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_SE2A1_5", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW4B0_5", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_NW4END3_5", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW2END3_5", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_NW2A2_5", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_WL1END1_5", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_EE4C1_5", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_WW2A2_5", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_LH8_5", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW4END3_5", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_SE4BEG2_5", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_SW4END2_5", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SW4END1_5", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_WR1END2_5", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_EE4BEG1_5", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_WW4C3_5", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4B1_5", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_NW2A3_5", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE2A2_5", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_WR1END0_5", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH4_5", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_NW4A2_5", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WL1END3_5", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE2A2_5", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WW4B3_5", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SE4C1_5", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_NW4END0_5", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SW4A0_5", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WW4END2_5", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_LH2_5", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NE4C0_5", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_EE2A1_5", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_NE2A1_5", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_LH10_5", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_EE4BEG2_5", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WL1END0_5", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_LH6_5", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WW4C0_5", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_ER1BEG0_5", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NE4BEG1_5", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_NE4BEG0_5", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NW2A1_5", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C2_5", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW4A0_5", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_NW4END1_5", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NE4C2_5", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE4BEG0_5", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WL1END2_5", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SW2A0_5", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_SE4C0_5", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_EE4B3_5", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_EE4A3_5", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_WW2END0_5", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WW4A0_5", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SE4BEG0_5", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SW4END0_5", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WW4A2_5", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_NE2A3_5", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_EE4B0_5", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH5_5", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE4B2_5", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_NE4C1_5", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW4A3_5", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_WR1END1_5", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_NW4A3_5", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_EE4A0_5", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_SE4C2_5", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_EL1BEG0_5", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_LH7_5", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_LH12_5", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW4END1_5", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE2BEG3_5", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_LH1_5", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_NW4END2_5", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_NE4BEG3_5", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW4C2_5", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_WW4END0_5", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WR1END3_5", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_SW4A3_5", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE2A3_5", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NW2A0_5", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_LH11_5", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EL1BEG2_5", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_SE2A0_5", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE4A1_5", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_SE4BEG3_5", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_SW2A3_5", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_ER1BEG2_5", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_WW2A0_5", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_EE2BEG0_5", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_ER1BEG3_5", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW4B2_5", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_LH9_5", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_SW4A2_5", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NE4C3_5", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_EE4C3_5", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_SE4C3_5", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WW4C1_5", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_EE2BEG1_5", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_EE2BEG2_5", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW2A1_5", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_NW4A1_5", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SE2A2_5", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4A2_5", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4B1_5", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_LH3_5", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_WW2A3_5", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_ER1BEG1_5", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WW4A1_5", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EL1BEG3_5", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_NE2A0_5", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EL1BEG1_5", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SW4END3_5", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NE4BEG2_5", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EE4C0_5", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EE4BEG3_5", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_SE4BEG1_5", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SW4A1_5", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_SE2A3_5", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_WW2END2_5", + "INT_FEEDTHRU_2_WW2END2" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 0, + -2 + ], + "wire_pairs": [ + [ + "IOI_RCLK_DIV_CE3_1", + "IOI_RCLK_DIV_CE3" + ], + [ + "IOI_RCLK_DIV_CE2_1", + "IOI_RCLK_DIV_CE2" + ], + [ + "IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "IOI_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1_1" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_LEAF_GCLK3" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_LEAF_GCLK1" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_LEAF_GCLK0" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_RCLK_FORIO1" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_RCLK_FORIO3" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_LEAF_GCLK5" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_RCLK_FORIO2" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_RCLK_FORIO0" + ], + [ + "IOI_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0_1" + ], + [ + "IOI_IMUX_RC2", + "IOI_IMUX_RC0" + ], + [ + "IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "IOI_IMUX_RC3", + "IOI_IMUX_RC1" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_LEAF_GCLK4" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_LEAF_GCLK2" + ] + ], + "tile_types": [ + "LIOI3", + "LIOI3_TBYTETERM" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SE2A1_8", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_LH6_8", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_NE4BEG1_8", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WW4END3_8", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4END2_8", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_NE2A1_8", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NE4C2_8", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW4B1_8", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_NE4BEG0_8", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_WW4C3_8", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_LH9_8", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_WW4B3_8", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_EE4C1_8", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE4A1_8", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_WW4A3_8", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_ER1BEG3_8", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_LH11_8", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_NE4C3_8", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WW2A2_8", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4BEG2_8", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG3_8", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_SE4C1_8", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_EE2A3_8", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW2A0_8", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_SE4C3_8", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_SW4END1_8", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EE4BEG2_8", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_ER1BEG1_8", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SW2A0_8", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WW2END1_8", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_SW4END2_8", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_EE4C3_8", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_EE2BEG1_8", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_SW4A3_8", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_NW4A0_8", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_EE2BEG0_8", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_LH2_8", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NE2A3_8", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_WL1END2_8", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_LH7_8", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_EL1BEG0_8", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE2BEG3_8", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_WW2END3_8", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_EE4BEG1_8", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_NW4A3_8", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WW4END1_8", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_WW4B2_8", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_NW2A0_8", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_EE2A1_8", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_ER1BEG2_8", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_EE4A2_8", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SE4C0_8", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_EE4B2_8", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_ER1BEG0_8", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NW4END3_8", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_EE2A2_8", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_NW2A2_8", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_LH3_8", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_WW2A3_8", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WR1END0_8", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH10_8", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_SE4BEG2_8", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW4C1_8", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SW4A2_8", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NW2A1_8", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C0_8", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WL1END0_8", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_WW4A1_8", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_WL1END3_8", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4A0_8", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE2BEG2_8", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NW4END2_8", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4A2_8", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_NE2A0_8", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_WW4C0_8", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_LH1_8", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_EE2A0_8", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_SW4END0_8", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WW4C2_8", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NW4END1_8", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_SE2A3_8", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_WW2END0_8", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WW4A0_8", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_NE4BEG3_8", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_NW4A2_8", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WW2END2_8", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_EE4B1_8", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NE2A2_8", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EL1BEG2_8", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_SW2A3_8", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NE4C1_8", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_SW2A2_8", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_NW4END0_8", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_NW4A1_8", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_LH5_8", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE4B3_8", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_LH12_8", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_SE4BEG0_8", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_WW4B0_8", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_WL1END1_8", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_SW4END3_8", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_SW4A0_8", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WR1END1_8", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WR1END2_8", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_SE2A2_8", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4C2_8", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW2A3_8", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_WW2A1_8", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_NE4C0_8", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_LH4_8", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SE4BEG3_8", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_SW4A1_8", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_SE2A0_8", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SW2A1_8", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_SE4BEG1_8", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_EE4BEG0_8", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE4A3_8", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE4BEG3_8", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_SE4C2_8", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_EL1BEG1_8", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_LH8_8", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW4END0_8", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WR1END3_8", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE4B0_8", + "INT_FEEDTHRU_2_EE4B0" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + 3 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW2A2_5", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A0_5", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END2_5", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SE4C1_5", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SW4END3_5", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NW4END0_5", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW2A0_5", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WL1END3_5", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SE2A2_5", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4B3_5", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE2A2_5", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_5", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_LH3_5", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE4C2_5", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2A0_5", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG1_5", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A1_5", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4A2_5", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END1_5", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW4C0_5", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_5", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4END3_5", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4BEG0_5", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_EL1BEG1_5", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH6_5", + "VBRK_LH6" + ], + [ + "CMT_TOP_EE4A1_5", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_MONITOR_N_5", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW4A2_5", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4A3_5", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NE4BEG0_5", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW2A2_5", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C3_5", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH7_5", + "VBRK_LH7" + ], + [ + "CMT_TOP_WW4B2_5", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH5_5", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4A1_5", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4A0_5", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C1_5", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW2A0_5", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WL1END2_5", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_SE4C0_5", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SW4END2_5", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END1_5", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG0_5", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_WR1END1_5", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EE4C1_5", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG0_5", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NW4END2_5", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_EE2BEG2_5", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4B1_5", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_ER1BEG3_5", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NW2A1_5", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW2END2_5", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW4B0_5", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A1_5", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE2A3_5", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_LH11_5", + "VBRK_LH11" + ], + [ + "CMT_TOP_WL1END0_5", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SW4END0_5", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4BEG3_5", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C3_5", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_SE4BEG1_5", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NE2A2_5", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B0_5", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_ER1BEG2_5", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_5", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NE2A0_5", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4BEG1_5", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE2A3_5", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG2_5", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_LH9_5", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4END2_5", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4BEG2_5", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2END0_5", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_ER1BEG0_5", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE2A1_5", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH4_5", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2BEG1_5", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_NE4BEG3_5", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C0_5", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_MONITOR_P_5", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_LH8_5", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4A3_5", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2BEG0_5", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_NE2A1_5", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C3_5", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WL1END1_5", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW4A1_5", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_5", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4A0_5", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4END1_5", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH2_5", + "VBRK_LH2" + ], + [ + "CMT_TOP_NE2A3_5", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW4A0_5", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4A3_5", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4C0_5", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_LH12_5", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH1_5", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_5", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_ER1BEG1_5", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2BEG3_5", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH10_5", + "VBRK_LH10" + ], + [ + "CMT_TOP_SW2A2_5", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WR1END3_5", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NW4END1_5", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NW4A1_5", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WW4C2_5", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WR1END0_5", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4END3_5", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW4A3_5", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW2A3_5", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4END0_5", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4C2_5", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG3_5", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW2A3_5", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4A2_5", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4BEG3_5", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE4B2_5", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW2A0_5", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SE2A0_5", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SE4BEG2_5", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B1_5", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4C1_5", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C2_5", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4C3_5", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_EL1BEG2_5", + "VBRK_EL1BEG2" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 5 + ], + "wire_pairs": [ + [ + "DSP_0_PCIN30", + "DSP_PCOUT30" + ], + [ + "DSP_0_ACIN5", + "DSP_ACOUT5" + ], + [ + "DSP_0_ACIN20", + "DSP_ACOUT20" + ], + [ + "DSP_0_PCIN47", + "DSP_PCOUT47" + ], + [ + "DSP_0_ACIN15", + "DSP_ACOUT15" + ], + [ + "DSP_0_ACIN8", + "DSP_ACOUT8" + ], + [ + "DSP_0_ACIN18", + "DSP_ACOUT18" + ], + [ + "DSP_0_PCIN22", + "DSP_PCOUT22" + ], + [ + "DSP_0_ACIN26", + "DSP_ACOUT26" + ], + [ + "DSP_0_ACIN14", + "DSP_ACOUT14" + ], + [ + "DSP_0_ACIN21", + "DSP_ACOUT21" + ], + [ + "DSP_0_PCIN5", + "DSP_PCOUT5" + ], + [ + "DSP_0_PCIN45", + "DSP_PCOUT45" + ], + [ + "DSP_0_MULTSIGNIN", + "DSP_MULTSIGNOUT" + ], + [ + "DSP_0_ACIN28", + "DSP_ACOUT28" + ], + [ + "DSP_0_PCIN20", + "DSP_PCOUT20" + ], + [ + "DSP_0_BCIN13", + "DSP_BCOUT13" + ], + [ + "DSP_0_ACIN25", + "DSP_ACOUT25" + ], + [ + "DSP_0_PCIN2", + "DSP_PCOUT2" + ], + [ + "DSP_0_PCIN0", + "DSP_PCOUT0" + ], + [ + "DSP_0_PCIN16", + "DSP_PCOUT16" + ], + [ + "DSP_0_BCIN16", + "DSP_BCOUT16" + ], + [ + "DSP_0_ACIN4", + "DSP_ACOUT4" + ], + [ + "DSP_0_PCIN7", + "DSP_PCOUT7" + ], + [ + "DSP_0_PCIN25", + "DSP_PCOUT25" + ], + [ + "DSP_0_BCIN15", + "DSP_BCOUT15" + ], + [ + "DSP_0_PCIN11", + "DSP_PCOUT11" + ], + [ + "DSP_0_ACIN19", + "DSP_ACOUT19" + ], + [ + "DSP_0_BCIN12", + "DSP_BCOUT12" + ], + [ + "DSP_0_ACIN0", + "DSP_ACOUT0" + ], + [ + "DSP_0_BCIN6", + "DSP_BCOUT6" + ], + [ + "DSP_0_PCIN42", + "DSP_PCOUT42" + ], + [ + "DSP_0_PCIN3", + "DSP_PCOUT3" + ], + [ + "DSP_0_CARRYCASCIN", + "DSP_CARRYCASCOUT" + ], + [ + "DSP_0_PCIN38", + "DSP_PCOUT38" + ], + [ + "DSP_0_PCIN18", + "DSP_PCOUT18" + ], + [ + "DSP_0_PCIN34", + "DSP_PCOUT34" + ], + [ + "DSP_0_PCIN23", + "DSP_PCOUT23" + ], + [ + "DSP_0_ACIN24", + "DSP_ACOUT24" + ], + [ + "DSP_0_ACIN22", + "DSP_ACOUT22" + ], + [ + "DSP_0_PCIN6", + "DSP_PCOUT6" + ], + [ + "DSP_0_PCIN12", + "DSP_PCOUT12" + ], + [ + "DSP_0_PCIN1", + "DSP_PCOUT1" + ], + [ + "DSP_0_PCIN13", + "DSP_PCOUT13" + ], + [ + "DSP_0_BCIN1", + "DSP_BCOUT1" + ], + [ + "DSP_0_PCIN17", + "DSP_PCOUT17" + ], + [ + "DSP_0_BCIN5", + "DSP_BCOUT5" + ], + [ + "DSP_0_BCIN0", + "DSP_BCOUT0" + ], + [ + "DSP_0_PCIN32", + "DSP_PCOUT32" + ], + [ + "DSP_0_PCIN39", + "DSP_PCOUT39" + ], + [ + "DSP_0_PCIN9", + "DSP_PCOUT9" + ], + [ + "DSP_0_PCIN4", + "DSP_PCOUT4" + ], + [ + "DSP_0_BCIN10", + "DSP_BCOUT10" + ], + [ + "DSP_0_ACIN10", + "DSP_ACOUT10" + ], + [ + "DSP_0_PCIN8", + "DSP_PCOUT8" + ], + [ + "DSP_0_BCIN17", + "DSP_BCOUT17" + ], + [ + "DSP_0_PCIN26", + "DSP_PCOUT26" + ], + [ + "DSP_0_ACIN13", + "DSP_ACOUT13" + ], + [ + "DSP_0_PCIN37", + "DSP_PCOUT37" + ], + [ + "DSP_0_ACIN23", + "DSP_ACOUT23" + ], + [ + "DSP_0_ACIN17", + "DSP_ACOUT17" + ], + [ + "DSP_0_PCIN21", + "DSP_PCOUT21" + ], + [ + "DSP_0_BCIN11", + "DSP_BCOUT11" + ], + [ + "DSP_0_ACIN1", + "DSP_ACOUT1" + ], + [ + "DSP_0_PCIN46", + "DSP_PCOUT46" + ], + [ + "DSP_0_PCIN36", + "DSP_PCOUT36" + ], + [ + "DSP_0_PCIN14", + "DSP_PCOUT14" + ], + [ + "DSP_0_PCIN35", + "DSP_PCOUT35" + ], + [ + "DSP_0_ACIN9", + "DSP_ACOUT9" + ], + [ + "DSP_0_BCIN8", + "DSP_BCOUT8" + ], + [ + "DSP_0_PCIN40", + "DSP_PCOUT40" + ], + [ + "DSP_0_PCIN41", + "DSP_PCOUT41" + ], + [ + "DSP_0_ACIN27", + "DSP_ACOUT27" + ], + [ + "DSP_0_PCIN15", + "DSP_PCOUT15" + ], + [ + "DSP_0_ACIN2", + "DSP_ACOUT2" + ], + [ + "DSP_0_ACIN29", + "DSP_ACOUT29" + ], + [ + "DSP_0_PCIN31", + "DSP_PCOUT31" + ], + [ + "DSP_0_BCIN2", + "DSP_BCOUT2" + ], + [ + "DSP_0_PCIN33", + "DSP_PCOUT33" + ], + [ + "DSP_0_BCIN4", + "DSP_BCOUT4" + ], + [ + "DSP_0_PCIN28", + "DSP_PCOUT28" + ], + [ + "DSP_0_BCIN7", + "DSP_BCOUT7" + ], + [ + "DSP_0_ACIN6", + "DSP_ACOUT6" + ], + [ + "DSP_0_BCIN3", + "DSP_BCOUT3" + ], + [ + "DSP_0_ACIN16", + "DSP_ACOUT16" + ], + [ + "DSP_0_PCIN43", + "DSP_PCOUT43" + ], + [ + "DSP_0_PCIN24", + "DSP_PCOUT24" + ], + [ + "DSP_0_ACIN7", + "DSP_ACOUT7" + ], + [ + "DSP_0_PCIN27", + "DSP_PCOUT27" + ], + [ + "DSP_0_PCIN44", + "DSP_PCOUT44" + ], + [ + "DSP_0_BCIN9", + "DSP_BCOUT9" + ], + [ + "DSP_0_BCIN14", + "DSP_BCOUT14" + ], + [ + "DSP_0_PCIN29", + "DSP_PCOUT29" + ], + [ + "DSP_0_ACIN11", + "DSP_ACOUT11" + ], + [ + "DSP_0_PCIN10", + "DSP_PCOUT10" + ], + [ + "DSP_0_ACIN3", + "DSP_ACOUT3" + ], + [ + "DSP_0_ACIN12", + "DSP_ACOUT12" + ], + [ + "DSP_0_PCIN19", + "DSP_PCOUT19" + ] + ], + "tile_types": [ + "DSP_L", + "DSP_L" + ] + }, + { + "grid_deltas": [ + -1, + -8 + ], + "wire_pairs": [ + [ + "PCIE_CLK0_R_18", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_FAN3_R_18", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_WW4A2_18", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_EE2BEG2_18", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_NW2A3_18", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_18", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_BYP0_R_18", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_NE4BEG0_18", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_BYP6_R_18", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_EE2BEG0_18", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_18", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_EE4BEG3_18", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_LH3_18", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_IMUX2_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_SW4A1_18", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_IMUX10_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_ER1BEG1_18", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_EE4B2_18", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_SE2A3_18", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_EE4A3_18", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_EE4BEG2_18", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX5_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_SE4C2_18", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_ER1BEG2_18", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_IMUX24_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_WW4C1_18", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_18", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_EE2A1_18", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_NE4BEG2_18", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_SW2A0_18", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_18", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_SW2A2_18", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_CTRL1_R_18", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_NW4A0_18", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_IMUX20_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_NW4END3_18", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_18", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_NW2A2_18", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_LH8_18", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4BEG0_18", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_WW4A1_18", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_IMUX19_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_NW2A0_18", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_SW4END0_18", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_LH10_18", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_FAN1_R_18", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_WW4C2_18", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_18", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_FAN0_R_18", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_LH2_18", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_IMUX30_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_IMUX41_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_WW4B3_18", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_WW4END0_18", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_FAN7_R_18", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_IMUX12_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_LH12_18", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_SE4BEG1_18", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_WW4END2_18", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_IMUX9_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_SW4END3_18", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_NE2A1_18", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_IMUX35_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_IMUX7_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_EE4C2_18", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_IMUX15_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_IMUX4_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_WR1END1_18", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_EE2BEG3_18", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_IMUX43_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_WW4END1_18", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_18", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_WW4A3_18", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_EL1BEG3_18", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_18", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_WL1END0_18", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_NE4BEG3_18", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_NE2A2_18", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_LH4_18", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_WW2END1_18", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_FAN5_R_18", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_WR1END3_18", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_NE4C1_18", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_NW4A1_18", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_WR1END2_18", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_LH11_18", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_18", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_WW2A2_18", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_SW4END1_18", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_WW4C3_18", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_SE2A1_18", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_IMUX18_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_SE2A2_18", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_SE4C1_18", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_FAN4_R_18", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_IMUX42_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_SE2A0_18", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_IMUX44_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_18", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_IMUX29_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_IMUX34_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_IMUX0_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_CTRL0_R_18", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_IMUX32_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_BYP2_R_18", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_IMUX14_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_18", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_SE4BEG3_18", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_18", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_EE2BEG1_18", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_EL1BEG0_18", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_SE4BEG2_18", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_EE4B3_18", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_IMUX40_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_WW2END3_18", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_EE2A2_18", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_WW2END0_18", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_18", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_WR1END0_18", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_WW4B0_18", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_NE2A0_18", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_WW4A0_18", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_18", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_NW2A1_18", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_18", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_ER1BEG3_18", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_SE4C3_18", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_FAN2_R_18", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_EE4C3_18", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_IMUX8_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_SW4A0_18", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_NW4A2_18", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_WW2A1_18", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_EE4B1_18", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_WW2END2_18", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_IMUX13_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_IMUX16_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_NW4END2_18", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_EL1BEG2_18", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_EE4A0_18", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_18", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_IMUX47_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_IMUX46_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_ER1BEG0_18", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_WW4B1_18", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_WL1END1_18", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_IMUX22_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_NE4C2_18", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_WW4C0_18", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_SW4A2_18", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_IMUX3_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_WL1END3_18", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_IMUX36_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_BYP3_R_18", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_BYP5_R_18", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_IMUX25_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_IMUX28_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_18", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_SE4C0_18", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_BYP1_R_18", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_18", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_18", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_IMUX1_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_IMUX17_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_EE2A3_18", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_NE2A3_18", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_WW4B2_18", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_WL1END2_18", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_EE2A0_18", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_EL1BEG1_18", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_SW4END2_18", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_BYP4_R_18", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_IMUX33_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_SE4BEG0_18", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_NE4BEG1_18", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_EE4A2_18", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_IMUX27_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_IMUX21_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_EE4A1_18", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_18", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_18", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_IMUX31_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_EE4C0_18", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_WW4END3_18", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_IMUX11_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_NW4A3_18", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_NE4C3_18", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_EE4B0_18", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_WW2A3_18", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_EE4C1_18", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_LH9_18", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_NW4END1_18", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_EE4BEG1_18", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_18", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_IMUX38_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_LH1_18", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_IMUX6_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_NE4C0_18", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_NW4END0_18", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_LH7_18", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_SW2A3_18", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX45_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_LH5_18", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_CLK1_R_18", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_LH6_18", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_BYP7_R_18", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_FAN6_R_18", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_SW2A1_18", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_IMUX23_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_IMUX39_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_WW2A0_18", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_18", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_IMUX37_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_IMUX26_R_18", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_SW4A3_18", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_18", + "INT_INTERFACE_LOGIC_OUTS_B5" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "CLK_HROW_SW4END2_3", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_CTRL1_3", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_IMUX24_3", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_WW4C2_3", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_EE4A3_3", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_IMUX7_3", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_CLK0_3", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_FAN2_3", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_SE4BEG2_3", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_IMUX35_3", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_EE4C1_3", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_NE2A1_3", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_FAN0_3", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_WW2A3_3", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_FAN4_3", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_EE2BEG3_3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_WW4A3_3", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_SE4BEG3_3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_NW2A2_3", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_IMUX21_3", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_WW4END1_3", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_SW2A1_3", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_SE4C3_3", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_IMUX27_3", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_SE4BEG0_3", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_EE4BEG0_3", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_WR1END0_3", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_EL1BEG3_3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_IMUX43_3", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_NW4A1_3", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_WL1END0_3", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_WL1END1_3", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_IMUX6_3", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_SE2A1_3", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_NW4END1_3", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_SW4END1_3", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_NW2A1_3", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_ER1BEG2_3", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_IMUX39_3", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_EE2BEG0_3", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_WW2END0_3", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_SW4END3_3", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_NE4C2_3", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_IMUX42_3", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_BYP6_3", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_EE2A0_3", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_WL1END3_3", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_WW4B2_3", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_LH9_3", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_IMUX30_3", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_BYP4_3", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_IMUX23_3", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_WW4A1_3", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_LH12_3", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_SW2A3_3", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_NE2A0_3", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_EE2BEG2_3", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_ER1BEG0_3", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_IMUX36_3", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_IMUX0_3", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_LH4_3", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_IMUX19_3", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_WW2A2_3", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_ER1BEG1_3", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_SE2A3_3", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_EE4B3_3", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_IMUX5_3", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_IMUX1_3", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_WW4END3_3", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_LH1_3", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_EE2A1_3", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_EE4B2_3", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_BYP5_3", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_NW4END2_3", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_BYP2_3", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_WW2END1_3", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_SE4C1_3", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_EE2BEG1_3", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_WW4A2_3", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_EE4A0_3", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_EE4C3_3", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_IMUX46_3", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_IMUX9_3", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_IMUX18_3", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_NE4BEG1_3", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_WW2END2_3", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_IMUX28_3", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_WW4C0_3", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_EE2A3_3", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_IMUX3_3", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_EL1BEG2_3", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_WW2A1_3", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_SW4A2_3", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_CTRL0_3", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_WW4END0_3", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_SW4A0_3", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_EL1BEG1_3", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_IMUX2_3", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_SE2A0_3", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_LH6_3", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_EE4C0_3", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_EE4B0_3", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_NE4C0_3", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_IMUX22_3", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_BYP1_3", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_FAN5_3", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_EE4C2_3", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_EE2A2_3", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_WW4B3_3", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_LH2_3", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_IMUX13_3", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_NW2A0_3", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_BYP7_3", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_IMUX37_3", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_SE4C0_3", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_NE4C1_3", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_WW2END3_3", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_IMUX44_3", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_IMUX20_3", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_SE2A2_3", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_IMUX31_3", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_NE4C3_3", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_WL1END2_3", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_SW4END0_3", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_IMUX4_3", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_SW2A2_3", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_WR1END2_3", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_NE2A3_3", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_SW4A3_3", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_NW4A0_3", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_NW4A2_3", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_FAN7_3", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_IMUX26_3", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_WW4B0_3", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_IMUX10_3", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_IMUX14_3", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_BYP0_3", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_CLK1_3", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_ER1BEG3_3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_SW2A0_3", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE4A2_3", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_LH5_3", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_NW2A3_3", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_NE2A2_3", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_WW2A0_3", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_IMUX47_3", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_NE4BEG3_3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_FAN6_3", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_FAN1_3", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_BYP3_3", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_WW4END2_3", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_WW4A0_3", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_SE4BEG1_3", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_NW4A3_3", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_EE4BEG2_3", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_IMUX25_3", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_IMUX32_3", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_IMUX33_3", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_LH10_3", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_IMUX15_3", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_EL1BEG0_3", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_FAN3_3", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_IMUX40_3", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_WW4B1_3", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_IMUX34_3", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_NW4END0_3", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_LH7_3", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_IMUX17_3", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_LH8_3", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_EE4A1_3", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_EE4BEG3_3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_IMUX11_3", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_SW4A1_3", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_LH11_3", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_WR1END1_3", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_WW4C3_3", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_IMUX45_3", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_NE4BEG2_3", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_IMUX41_3", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_LH3_3", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_IMUX38_3", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_IMUX8_3", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_EE4BEG1_3", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_EE4B1_3", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_SE4C2_3", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_IMUX16_3", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_IMUX29_3", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_IMUX12_3", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_NE4BEG0_3", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_NW4END3_3", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_WW4C1_3", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_WR1END3_3", + "INT_INTERFACE_WR1END3" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -7 + ], + "wire_pairs": [ + [ + "CMT_TOP_ER1BEG2_12", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WR1END0_12", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4C0_12", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WW4END0_12", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_LH10_12", + "VBRK_LH10" + ], + [ + "CMT_TOP_NE4BEG2_12", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_NW4END3_12", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4BEG3_12", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH1_12", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A1_12", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SE4BEG1_12", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NE4BEG1_12", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_NW4A3_12", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE2BEG3_12", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WL1END2_12", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE2BEG2_12", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW4B2_12", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EL1BEG1_12", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SW4END1_12", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_WW4C0_12", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SW2A2_12", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4B0_12", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE4C2_12", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_LH2_12", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4B1_12", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4C3_12", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE4C0_12", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_LH7_12", + "VBRK_LH7" + ], + [ + "CMT_TOP_NE2A0_12", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4A0_12", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WR1END2_12", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW4END1_12", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4BEG3_12", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW2A1_12", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4END2_12", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_SE2A0_12", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW4A1_12", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SE4C1_12", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE2A1_12", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4B1_12", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_EE4C3_12", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4BEG1_12", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_12", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_WR1END3_12", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE2BEG0_12", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EL1BEG2_12", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4A1_12", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW4C2_12", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW4A2_12", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_LH3_12", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE2A3_12", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW2END2_12", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_ER1BEG0_12", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END3_12", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EL1BEG0_12", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_WW2END0_12", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2END1_12", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW2A2_12", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_WL1END3_12", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_EE4BEG2_12", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW4END2_12", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE4C2_12", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4A2_12", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG0_12", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4END3_12", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NW2A2_12", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A3_12", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_SW4A0_12", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_LH11_12", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE2A0_12", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH4_12", + "VBRK_LH4" + ], + [ + "CMT_TOP_SW2A3_12", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4A0_12", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EL1BEG3_12", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE4B3_12", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4A1_12", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_LH5_12", + "VBRK_LH5" + ], + [ + "CMT_TOP_NW2A3_12", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C3_12", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_NE4C2_12", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SW2A1_12", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH9_12", + "VBRK_LH9" + ], + [ + "CMT_TOP_NW2A0_12", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_EE2A3_12", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW2A0_12", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4BEG3_12", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EE4B2_12", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_NW4END1_12", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A1_12", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NE4C3_12", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_ER1BEG1_12", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2A2_12", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WR1END1_12", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A2_12", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2BEG1_12", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SE2A2_12", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_NE4C1_12", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH12_12", + "VBRK_LH12" + ], + [ + "CMT_TOP_SW4END0_12", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WL1END1_12", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_ER1BEG3_12", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4A3_12", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_WW4B3_12", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4C1_12", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2A3_12", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_LH6_12", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A3_12", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH8_12", + "VBRK_LH8" + ], + [ + "CMT_TOP_SE2A1_12", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4A2_12", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4B0_12", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_NW4A0_12", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_SW4END2_12", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE2A1_12", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_WW2END3_12", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SE2A3_12", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4C1_12", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NE4BEG0_12", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE4BEG2_12", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW4A2_12", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NE4C0_12", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WL1END0_12", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_WW2A0_12", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END0_12", + "VBRK_NW4END0" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_IMUX21_2", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_LH11_2", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_SE2A2_2", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_L_IMUX37_2", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_EE4B3_2", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_WW4A1_2", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_EE4A1_2", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_SW2A2_2", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_2", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CMT_FIFO_WW4END0_2", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_IMUX14_2", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_EE4BEG0_2", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX17_2", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_EE4A0_2", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_L_IMUX42_2", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_NE2A3_2", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_EL1BEG2_2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_WW4C2_2", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_IMUX47_2", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_SW4END2_2", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_L_IMUX10_2", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_NE4BEG1_2", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_BYP0_2", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_L_IMUX39_2", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_L_CLK1_2", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_EE2A0_2", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_WW2END0_2", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_WW4C0_2", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_L_IMUX26_2", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_FAN6_2", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_WW2A2_2", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_2", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "CMT_FIFO_ER1BEG2_2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_LH12_2", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_WR1END1_2", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_L_BYP6_2", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_2", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CMT_FIFO_NE2A2_2", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_EL1BEG0_2", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_2", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CMT_FIFO_L_IMUX2_2", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_NE4C2_2", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_L_IMUX7_2", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_L_IMUX19_2", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_NW2A3_2", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_EE4C2_2", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_EE2A3_2", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_WR1END2_2", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_L_IMUX43_2", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_L_FAN5_2", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_L_IMUX25_2", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_SW2A3_2", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_LH9_2", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_NE4C1_2", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_ER1BEG1_2", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_2", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "CMT_FIFO_EE4B2_2", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_L_IMUX6_2", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_EE4BEG2_2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX41_2", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_BYP7_2", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_WW4B1_2", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_WW2END3_2", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_WW2A0_2", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_2", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "CMT_FIFO_SW2A1_2", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_L_CTRL1_2", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_WR1END3_2", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_LH3_2", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_2", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CMT_FIFO_L_IMUX34_2", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_L_IMUX12_2", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_SW4A2_2", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_L_FAN7_2", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_L_IMUX0_2", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_EE4A2_2", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_IMUX46_2", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_WW2A1_2", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_L_IMUX33_2", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_L_IMUX22_2", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_L_FAN3_2", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_2", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CMT_FIFO_L_IMUX32_2", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_NW2A1_2", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_NW4END2_2", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_IMUX11_2", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_EE2BEG3_2", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_L_BYP2_2", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_L_BYP3_2", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_SE4C1_2", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_NE2A0_2", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_NW4A3_2", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_SE2A1_2", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_L_CLK0_2", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_2", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "CMT_FIFO_EL1BEG3_2", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_NW4END0_2", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_SE2A0_2", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_2", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_2", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CMT_FIFO_SE4BEG0_2", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_WL1END0_2", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_EE2BEG2_2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_WW4C1_2", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_WW4END2_2", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_MONITOR_N_2", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CMT_FIFO_EE2A1_2", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_L_IMUX44_2", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_WW4B2_2", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_SW4A3_2", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_2", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "CMT_FIFO_L_BYP1_2", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_SE4BEG3_2", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_WW4END3_2", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_L_IMUX20_2", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_L_IMUX29_2", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_SE4BEG2_2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_ER1BEG0_2", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_L_IMUX16_2", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_L_IMUX1_2", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_EE2BEG1_2", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_L_IMUX15_2", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_2", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CMT_FIFO_SW4A1_2", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_LH4_2", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_L_BYP4_2", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_LH10_2", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_LH1_2", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_EE4C1_2", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_2", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "CMT_FIFO_MONITOR_P_2", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CMT_FIFO_L_IMUX31_2", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_WW4END1_2", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_WL1END1_2", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_EE4A3_2", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_NW4A2_2", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_WW4A3_2", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_NW4A0_2", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_NW4A1_2", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_2", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CMT_FIFO_L_IMUX27_2", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_2", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "CMT_FIFO_EE4B1_2", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_2", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "CMT_FIFO_NE4BEG3_2", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_L_FAN0_2", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_WW4B3_2", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_L_IMUX4_2", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_L_IMUX45_2", + "INT_INTERFACE_IMUX45" + ], + [ + "FIFO_DQS_IOTOPHASER_44", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "CMT_FIFO_EE4C0_2", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_SW4A0_2", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_L_IMUX8_2", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_SE4C0_2", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_WL1END3_2", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_SE2A3_2", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_EL1BEG1_2", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_WW4A2_2", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_ER1BEG3_2", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_WW2END2_2", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_2", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CMT_FIFO_WW2A3_2", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_L_IMUX40_2", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_NE4BEG2_2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_SW4END1_2", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_SW4END0_2", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_2", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "CMT_FIFO_LH8_2", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_BYP5_2", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_NE4C0_2", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_WL1END2_2", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_L_IMUX5_2", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_EE4C3_2", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_NE2A1_2", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_L_IMUX36_2", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_WW4A0_2", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_NW4END3_2", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_L_FAN2_2", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_L_CTRL0_2", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_2", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "CMT_FIFO_LH6_2", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_L_IMUX35_2", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_2", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CMT_FIFO_EE2A2_2", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_L_IMUX23_2", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_EE4BEG1_2", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_NE4BEG0_2", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_EE2BEG0_2", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_WW4C3_2", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_L_IMUX3_2", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_L_IMUX9_2", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_2", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "CMT_FIFO_WW4B0_2", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_NW2A2_2", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_SE4BEG1_2", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX18_2", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_SE4C2_2", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_L_IMUX28_2", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_2", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CMT_FIFO_L_IMUX38_2", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_NW2A0_2", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_LH7_2", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_WW2END1_2", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_LH2_2", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_LH5_2", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_L_FAN1_2", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_2", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "CMT_FIFO_SW4END3_2", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_EE4B0_2", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_L_IMUX13_2", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_SE4C3_2", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_IMUX30_2", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_EE4BEG3_2", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_SW2A0_2", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_NW4END1_2", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_NE4C3_2", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_WR1END0_2", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_L_FAN4_2", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_L_IMUX24_2", + "INT_INTERFACE_IMUX24" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "GTXE2_FAN7_4", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX44_4", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX37_4", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_BYP0_4", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX23_4", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX28_4", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX26_4", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX34_4", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX22_4", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX33_4", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_LOGIC_OUTS_B20_4", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX7_4", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX6_4", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_FAN4_4", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX20_4", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX24_4", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_FAN2_4", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX46_4", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX13_4", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX36_4", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_LOGIC_OUTS_B22_4", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX3_4", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX2_4", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_BYP6_4", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX27_4", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_BYP1_4", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX42_4", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX15_4", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX18_4", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_FAN0_4", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX4_4", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_BYP2_4", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX0_4", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_BYP3_4", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_BYP4_4", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX8_4", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_CTRL1_4", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX32_4", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN6_4", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX14_4", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_FAN5_4", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX29_4", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX30_4", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX38_4", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX43_4", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_BYP7_4", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX5_4", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX35_4", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX1_4", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_CLK1_4", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX12_4", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX31_4", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX45_4", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_CTRL0_4", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX40_4", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX9_4", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX11_4", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX39_4", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX25_4", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_BYP5_4", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B16_4", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX41_4", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B18_4", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX47_4", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX19_4", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX21_4", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_CLK0_4", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX10_4", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX17_4", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX16_4", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_FAN3_4", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_LOGIC_OUTS_B9_4", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_FAN1_4", + "VBRK_EXT_FAN1" + ] + ], + "tile_types": [ + "GTX_COMMON", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "CMT_TOP_LH12_7", + "VBRK_LH12" + ], + [ + "CMT_TOP_SW4END1_7", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_7", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE4C2_7", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_ER1BEG3_7", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END1_7", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WL1END2_7", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_NW4A0_7", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WR1END2_7", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW4A2_7", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG3_7", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EL1BEG0_7", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH11_7", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW2END2_7", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4A1_7", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NE2A1_7", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SW2A2_7", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_ER1BEG0_7", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_7", + "VBRK_LH1" + ], + [ + "CMT_TOP_SW4A3_7", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH10_7", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4BEG3_7", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C3_7", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4END3_7", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_ER1BEG1_7", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_7", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW2END0_7", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END2_7", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NE4C0_7", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EL1BEG1_7", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_EE2BEG3_7", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WW4END0_7", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4C1_7", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A2_7", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_7", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE2A3_7", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4A1_7", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_LH2_7", + "VBRK_LH2" + ], + [ + "CMT_TOP_EL1BEG2_7", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WL1END0_7", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4C1_7", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW2END1_7", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2BEG0_7", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4B0_7", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C2_7", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A0_7", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_7", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_EE4B2_7", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG2_7", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A0_7", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG0_7", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW4A1_7", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_SE2A1_7", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4END2_7", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE2A3_7", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW4C0_7", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_7", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE4BEG2_7", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_SE4C0_7", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_ER1BEG2_7", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NE2A0_7", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4A3_7", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4BEG2_7", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_7", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4B3_7", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END3_7", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WW4C1_7", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WL1END3_7", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH9_7", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2A0_7", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG1_7", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_7", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_LH3_7", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_7", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE4BEG1_7", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EE4A2_7", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG0_7", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE4BEG2_7", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW4END3_7", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NE4BEG1_7", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A2_7", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NW4END0_7", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_7", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4A0_7", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END0_7", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_7", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW4END1_7", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE4BEG1_7", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH7_7", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4A3_7", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C2_7", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A3_7", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW2A1_7", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C3_7", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE2A2_7", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NE4C3_7", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE4C0_7", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WR1END1_7", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NW4END3_7", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_WW4B1_7", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C1_7", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_7", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE2A1_7", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_7", + "VBRK_LH5" + ], + [ + "CMT_TOP_SE4C2_7", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B0_7", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE2A0_7", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW4A1_7", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SW2A0_7", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW2A3_7", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW2A0_7", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_7", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EL1BEG3_7", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_NW4A2_7", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG3_7", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NW2A3_7", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW4C3_7", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_7", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_LH4_7", + "VBRK_LH4" + ], + [ + "CMT_TOP_LH8_7", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B3_7", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NE2A2_7", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4BEG0_7", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2A3_7", + "VBRK_EE2A3" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLBLM_SW4A0", + "VBRK_SW4A0" + ], + [ + "CLBLM_SE4BEG2", + "VBRK_SE4BEG2" + ], + [ + "CLBLM_EE2BEG2", + "VBRK_EE2BEG2" + ], + [ + "CLBLM_NW4END3", + "VBRK_NW4END3" + ], + [ + "CLBLM_EE4C2", + "VBRK_EE4C2" + ], + [ + "CLBLM_EL1BEG0", + "VBRK_EL1BEG0" + ], + [ + "CLBLM_SE4C1", + "VBRK_SE4C1" + ], + [ + "CLBLM_NE4C2", + "VBRK_NE4C2" + ], + [ + "CLBLM_EE4A1", + "VBRK_EE4A1" + ], + [ + "CLBLM_WW4A2", + "VBRK_WW4A2" + ], + [ + "CLBLM_EE4A3", + "VBRK_EE4A3" + ], + [ + "CLBLM_EE4B3", + "VBRK_EE4B3" + ], + [ + "CLBLM_NW4A3", + "VBRK_NW4A3" + ], + [ + "CLBLM_NE2A3", + "VBRK_NE2A3" + ], + [ + "CLBLM_NW2A1", + "VBRK_NW2A1" + ], + [ + "CLBLM_LH9", + "VBRK_LH9" + ], + [ + "CLBLM_MONITOR_P", + "VBRK_MONITOR_P" + ], + [ + "CLBLM_EE2A0", + "VBRK_EE2A0" + ], + [ + "CLBLM_EE2A1", + "VBRK_EE2A1" + ], + [ + "CLBLM_EE4B0", + "VBRK_EE4B0" + ], + [ + "CLBLM_SE4BEG1", + "VBRK_SE4BEG1" + ], + [ + "CLBLM_WW4END2", + "VBRK_WW4END2" + ], + [ + "CLBLM_EE4BEG3", + "VBRK_EE4BEG3" + ], + [ + "CLBLM_EE4C0", + "VBRK_EE4C0" + ], + [ + "CLBLM_WW4C3", + "VBRK_WW4C3" + ], + [ + "CLBLM_EE2BEG0", + "VBRK_EE2BEG0" + ], + [ + "CLBLM_NE4C3", + "VBRK_NE4C3" + ], + [ + "CLBLM_NW2A0", + "VBRK_NW2A0" + ], + [ + "CLBLM_WL1END2", + "VBRK_WL1END2" + ], + [ + "CLBLM_EE4B1", + "VBRK_EE4B1" + ], + [ + "CLBLM_NE4C1", + "VBRK_NE4C1" + ], + [ + "CLBLM_WR1END2", + "VBRK_WR1END2" + ], + [ + "CLBLM_EE4C3", + "VBRK_EE4C3" + ], + [ + "CLBLM_NE2A0", + "VBRK_NE2A0" + ], + [ + "CLBLM_WW4B3", + "VBRK_WW4B3" + ], + [ + "CLBLM_SW4END3", + "VBRK_SW4END3" + ], + [ + "CLBLM_WL1END1", + "VBRK_WL1END1" + ], + [ + "CLBLM_SW4END0", + "VBRK_SW4END0" + ], + [ + "CLBLM_SE2A3", + "VBRK_SE2A3" + ], + [ + "CLBLM_NE2A2", + "VBRK_NE2A2" + ], + [ + "CLBLM_LH6", + "VBRK_LH6" + ], + [ + "CLBLM_EE4B2", + "VBRK_EE4B2" + ], + [ + "CLBLM_LH2", + "VBRK_LH2" + ], + [ + "CLBLM_SE4C0", + "VBRK_SE4C0" + ], + [ + "CLBLM_NW2A2", + "VBRK_NW2A2" + ], + [ + "CLBLM_MONITOR_N", + "VBRK_MONITOR_N" + ], + [ + "CLBLM_WW2A1", + "VBRK_WW2A1" + ], + [ + "CLBLM_LH3", + "VBRK_LH3" + ], + [ + "CLBLM_LH7", + "VBRK_LH7" + ], + [ + "CLBLM_WW4B0", + "VBRK_WW4B0" + ], + [ + "CLBLM_WW4B2", + "VBRK_WW4B2" + ], + [ + "CLBLM_EE4C1", + "VBRK_EE4C1" + ], + [ + "CLBLM_SE2A1", + "VBRK_SE2A1" + ], + [ + "CLBLM_EE2A3", + "VBRK_EE2A3" + ], + [ + "CLBLM_EE2BEG3", + "VBRK_EE2BEG3" + ], + [ + "CLBLM_WW4END0", + "VBRK_WW4END0" + ], + [ + "CLBLM_LH1", + "VBRK_LH1" + ], + [ + "CLBLM_WW2A2", + "VBRK_WW2A2" + ], + [ + "CLBLM_WR1END0", + "VBRK_WR1END0" + ], + [ + "CLBLM_NE4BEG1", + "VBRK_NE4BEG1" + ], + [ + "CLBLM_SW2A3", + "VBRK_SW2A3" + ], + [ + "CLBLM_WW4END1", + "VBRK_WW4END1" + ], + [ + "CLBLM_SE4BEG3", + "VBRK_SE4BEG3" + ], + [ + "CLBLM_WW4C2", + "VBRK_WW4C2" + ], + [ + "CLBLM_NE4C0", + "VBRK_NE4C0" + ], + [ + "CLBLM_SE2A0", + "VBRK_SE2A0" + ], + [ + "CLBLM_SW4A3", + "VBRK_SW4A3" + ], + [ + "CLBLM_SE4BEG0", + "VBRK_SE4BEG0" + ], + [ + "CLBLM_SW2A1", + "VBRK_SW2A1" + ], + [ + "CLBLM_EE2A2", + "VBRK_EE2A2" + ], + [ + "CLBLM_WW4A0", + "VBRK_WW4A0" + ], + [ + "CLBLM_WW2A0", + "VBRK_WW2A0" + ], + [ + "CLBLM_SW4A2", + "VBRK_SW4A2" + ], + [ + "CLBLM_WW2END0", + "VBRK_WW2END0" + ], + [ + "CLBLM_ER1BEG2", + "VBRK_ER1BEG2" + ], + [ + "CLBLM_SW4END2", + "VBRK_SW4END2" + ], + [ + "CLBLM_EE4BEG2", + "VBRK_EE4BEG2" + ], + [ + "CLBLM_WW2END2", + "VBRK_WW2END2" + ], + [ + "CLBLM_LH11", + "VBRK_LH11" + ], + [ + "CLBLM_SE4C3", + "VBRK_SE4C3" + ], + [ + "CLBLM_LH8", + "VBRK_LH8" + ], + [ + "CLBLM_ER1BEG0", + "VBRK_ER1BEG0" + ], + [ + "CLBLM_EE4A0", + "VBRK_EE4A0" + ], + [ + "CLBLM_WL1END0", + "VBRK_WL1END0" + ], + [ + "CLBLM_NE2A1", + "VBRK_NE2A1" + ], + [ + "CLBLM_ER1BEG3", + "VBRK_ER1BEG3" + ], + [ + "CLBLM_SE2A2", + "VBRK_SE2A2" + ], + [ + "CLBLM_WW2A3", + "VBRK_WW2A3" + ], + [ + "CLBLM_EL1BEG1", + "VBRK_EL1BEG1" + ], + [ + "CLBLM_WW2END1", + "VBRK_WW2END1" + ], + [ + "CLBLM_NW4A0", + "VBRK_NW4A0" + ], + [ + "CLBLM_WL1END3", + "VBRK_WL1END3" + ], + [ + "CLBLM_SW4A1", + "VBRK_SW4A1" + ], + [ + "CLBLM_EE4BEG1", + "VBRK_EE4BEG1" + ], + [ + "CLBLM_LH5", + "VBRK_LH5" + ], + [ + "CLBLM_NW4A2", + "VBRK_NW4A2" + ], + [ + "CLBLM_SW2A2", + "VBRK_SW2A2" + ], + [ + "CLBLM_NE4BEG0", + "VBRK_NE4BEG0" + ], + [ + "CLBLM_LH10", + "VBRK_LH10" + ], + [ + "CLBLM_LH4", + "VBRK_LH4" + ], + [ + "CLBLM_NW4END2", + "VBRK_NW4END2" + ], + [ + "CLBLM_WW2END3", + "VBRK_WW2END3" + ], + [ + "CLBLM_EL1BEG2", + "VBRK_EL1BEG2" + ], + [ + "CLBLM_NW2A3", + "VBRK_NW2A3" + ], + [ + "CLBLM_WW4C0", + "VBRK_WW4C0" + ], + [ + "CLBLM_NW4END0", + "VBRK_NW4END0" + ], + [ + "CLBLM_WW4END3", + "VBRK_WW4END3" + ], + [ + "CLBLM_EE2BEG1", + "VBRK_EE2BEG1" + ], + [ + "CLBLM_SE4C2", + "VBRK_SE4C2" + ], + [ + "CLBLM_EE4BEG0", + "VBRK_EE4BEG0" + ], + [ + "CLBLM_WW4A3", + "VBRK_WW4A3" + ], + [ + "CLBLM_NW4END1", + "VBRK_NW4END1" + ], + [ + "CLBLM_WR1END1", + "VBRK_WR1END1" + ], + [ + "CLBLM_ER1BEG1", + "VBRK_ER1BEG1" + ], + [ + "CLBLM_WR1END3", + "VBRK_WR1END3" + ], + [ + "CLBLM_WW4B1", + "VBRK_WW4B1" + ], + [ + "CLBLM_EL1BEG3", + "VBRK_EL1BEG3" + ], + [ + "CLBLM_SW4END1", + "VBRK_SW4END1" + ], + [ + "CLBLM_LH12", + "VBRK_LH12" + ], + [ + "CLBLM_WW4C1", + "VBRK_WW4C1" + ], + [ + "CLBLM_WW4A1", + "VBRK_WW4A1" + ], + [ + "CLBLM_NE4BEG2", + "VBRK_NE4BEG2" + ], + [ + "CLBLM_NE4BEG3", + "VBRK_NE4BEG3" + ], + [ + "CLBLM_EE4A2", + "VBRK_EE4A2" + ], + [ + "CLBLM_SW2A0", + "VBRK_SW2A0" + ], + [ + "CLBLM_NW4A1", + "VBRK_NW4A1" + ] + ], + "tile_types": [ + "CLBLM_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SE2A1_8", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_LH6_8", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_NE4BEG1_8", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WW4END3_8", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4END2_8", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_NE2A1_8", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NE4C2_8", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW4B1_8", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_NE4BEG0_8", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_WW4C3_8", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_LH9_8", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_WW4B3_8", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_EE4C1_8", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE4A1_8", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_WW4A3_8", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_ER1BEG3_8", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_LH11_8", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_NE4C3_8", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WW2A2_8", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4BEG2_8", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG3_8", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_SE4C1_8", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_EE2A3_8", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW2A0_8", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_SE4C3_8", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_SW4END1_8", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EE4BEG2_8", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_ER1BEG1_8", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SW2A0_8", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WW2END1_8", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_SW4END2_8", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_EE4C3_8", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_EE2BEG1_8", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_SW4A3_8", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_NW4A0_8", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_EE2BEG0_8", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_LH2_8", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NE2A3_8", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_WL1END2_8", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_LH7_8", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_EL1BEG0_8", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE2BEG3_8", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_WW2END3_8", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_EE4BEG1_8", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_NW4A3_8", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WW4END1_8", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_WW4B2_8", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_NW2A0_8", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_EE2A1_8", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_ER1BEG2_8", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_EE4A2_8", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SE4C0_8", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_EE4B2_8", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_ER1BEG0_8", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NW4END3_8", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_EE2A2_8", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_NW2A2_8", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_LH3_8", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_WW2A3_8", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WR1END0_8", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH10_8", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_SE4BEG2_8", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW4C1_8", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SW4A2_8", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NW2A1_8", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C0_8", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WL1END0_8", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_WW4A1_8", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_WL1END3_8", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4A0_8", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE2BEG2_8", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NW4END2_8", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4A2_8", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_NE2A0_8", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_WW4C0_8", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_LH1_8", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_EE2A0_8", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_SW4END0_8", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WW4C2_8", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NW4END1_8", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_SE2A3_8", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_WW2END0_8", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WW4A0_8", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_NE4BEG3_8", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_NW4A2_8", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WW2END2_8", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_EE4B1_8", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NE2A2_8", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EL1BEG2_8", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_SW2A3_8", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NE4C1_8", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_SW2A2_8", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_NW4END0_8", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_NW4A1_8", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_LH5_8", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE4B3_8", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_LH12_8", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_SE4BEG0_8", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_WW4B0_8", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_WL1END1_8", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_SW4END3_8", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_SW4A0_8", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WR1END1_8", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WR1END2_8", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_SE2A2_8", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4C2_8", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW2A3_8", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_WW2A1_8", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_NE4C0_8", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_LH4_8", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SE4BEG3_8", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_SW4A1_8", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_SE2A0_8", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SW2A1_8", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_SE4BEG1_8", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_EE4BEG0_8", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE4A3_8", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EL1BEG1_8", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SE4C2_8", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_EE4BEG3_8", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_LH8_8", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW4END0_8", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WR1END3_8", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE4B0_8", + "INT_FEEDTHRU_2_EE4B0" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "MONITOR_NE2A0_1", + "VFRAME_NE2A0" + ], + [ + "MONITOR_EE4A0_1", + "VFRAME_EE4A0" + ], + [ + "MONITOR_ER1BEG3_1", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_BYP3_1", + "VFRAME_BYP3" + ], + [ + "MONITOR_IMUX7_1", + "VFRAME_IMUX7" + ], + [ + "MONITOR_NW4A0_1", + "VFRAME_NW4A0" + ], + [ + "MONITOR_WW4B0_1", + "VFRAME_WW4B0" + ], + [ + "MONITOR_IMUX4_1", + "VFRAME_IMUX4" + ], + [ + "MONITOR_FAN1_1", + "VFRAME_FAN1" + ], + [ + "MONITOR_EE2A1_1", + "VFRAME_EE2A1" + ], + [ + "MONITOR_IMUX31_1", + "VFRAME_IMUX31" + ], + [ + "MONITOR_WW4B1_1", + "VFRAME_WW4B1" + ], + [ + "MONITOR_LOGIC_OUTS_B15_1", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "MONITOR_EE4C3_1", + "VFRAME_EE4C3" + ], + [ + "MONITOR_WW4END1_1", + "VFRAME_WW4END1" + ], + [ + "MONITOR_NW4A2_1", + "VFRAME_NW4A2" + ], + [ + "MONITOR_SE4C0_1", + "VFRAME_SE4C0" + ], + [ + "MONITOR_NW2A3_1", + "VFRAME_NW2A3" + ], + [ + "MONITOR_SW4END1_1", + "VFRAME_SW4END1" + ], + [ + "MONITOR_NE4BEG3_1", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_IMUX46_1", + "VFRAME_IMUX46" + ], + [ + "MONITOR_FAN5_1", + "VFRAME_FAN5" + ], + [ + "MONITOR_LH5_1", + "VFRAME_LH5" + ], + [ + "MONITOR_EL1BEG0_1", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_SE4C3_1", + "VFRAME_SE4C3" + ], + [ + "MONITOR_SW4A2_1", + "VFRAME_SW4A2" + ], + [ + "MONITOR_NE4BEG2_1", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_IMUX16_1", + "VFRAME_IMUX16" + ], + [ + "MONITOR_EL1BEG1_1", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_NE2A1_1", + "VFRAME_NE2A1" + ], + [ + "MONITOR_LOGIC_OUTS_B19_1", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "MONITOR_WR1END0_1", + "VFRAME_WR1END0" + ], + [ + "MONITOR_FAN7_1", + "VFRAME_FAN7" + ], + [ + "MONITOR_NE4BEG1_1", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_NE4BEG0_1", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_LOGIC_OUTS_B16_1", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "MONITOR_IMUX38_1", + "VFRAME_IMUX38" + ], + [ + "MONITOR_EE4A1_1", + "VFRAME_EE4A1" + ], + [ + "MONITOR_FAN3_1", + "VFRAME_FAN3" + ], + [ + "MONITOR_SE4BEG0_1", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_IMUX42_1", + "VFRAME_IMUX42" + ], + [ + "MONITOR_IMUX29_1", + "VFRAME_IMUX29" + ], + [ + "MONITOR_EE4B3_1", + "VFRAME_EE4B3" + ], + [ + "MONITOR_LH8_1", + "VFRAME_LH8" + ], + [ + "MONITOR_IMUX43_1", + "VFRAME_IMUX43" + ], + [ + "MONITOR_WW2END0_1", + "VFRAME_WW2END0" + ], + [ + "MONITOR_NE2A3_1", + "VFRAME_NE2A3" + ], + [ + "MONITOR_WW4C0_1", + "VFRAME_WW4C0" + ], + [ + "MONITOR_LH11_1", + "VFRAME_LH11" + ], + [ + "MONITOR_BYP1_1", + "VFRAME_BYP1" + ], + [ + "MONITOR_WW2END3_1", + "VFRAME_WW2END3" + ], + [ + "MONITOR_LOGIC_OUTS_B14_1", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "MONITOR_EE4BEG2_1", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_IMUX3_1", + "VFRAME_IMUX3" + ], + [ + "MONITOR_CLK0_1", + "VFRAME_CLK0" + ], + [ + "MONITOR_WR1END3_1", + "VFRAME_WR1END3" + ], + [ + "MONITOR_SW2A1_1", + "VFRAME_SW2A1" + ], + [ + "MONITOR_EE4A2_1", + "VFRAME_EE4A2" + ], + [ + "MONITOR_EE4BEG3_1", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_NW4A1_1", + "VFRAME_NW4A1" + ], + [ + "MONITOR_EL1BEG2_1", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_WW2A2_1", + "VFRAME_WW2A2" + ], + [ + "MONITOR_NE4C2_1", + "VFRAME_NE4C2" + ], + [ + "MONITOR_SE4BEG3_1", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_LH9_1", + "VFRAME_LH9" + ], + [ + "MONITOR_IMUX0_1", + "VFRAME_IMUX0" + ], + [ + "MONITOR_IMUX12_1", + "VFRAME_IMUX12" + ], + [ + "MONITOR_WL1END1_1", + "VFRAME_WL1END1" + ], + [ + "MONITOR_LH10_1", + "VFRAME_LH10" + ], + [ + "MONITOR_ER1BEG2_1", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_LOGIC_OUTS_B11_1", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "MONITOR_EE2A2_1", + "VFRAME_EE2A2" + ], + [ + "MONITOR_EE2BEG0_1", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_EE4BEG1_1", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX30_1", + "VFRAME_IMUX30" + ], + [ + "MONITOR_FAN6_1", + "VFRAME_FAN6" + ], + [ + "MONITOR_IMUX41_1", + "VFRAME_IMUX41" + ], + [ + "MONITOR_EE2BEG2_1", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_IMUX10_1", + "VFRAME_IMUX10" + ], + [ + "MONITOR_IMUX40_1", + "VFRAME_IMUX40" + ], + [ + "MONITOR_SW4A0_1", + "VFRAME_SW4A0" + ], + [ + "MONITOR_EE4B1_1", + "VFRAME_EE4B1" + ], + [ + "MONITOR_IMUX33_1", + "VFRAME_IMUX33" + ], + [ + "MONITOR_FAN0_1", + "VFRAME_FAN0" + ], + [ + "MONITOR_BYP2_1", + "VFRAME_BYP2" + ], + [ + "MONITOR_ER1BEG0_1", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_WW2A0_1", + "VFRAME_WW2A0" + ], + [ + "MONITOR_SE4C2_1", + "VFRAME_SE4C2" + ], + [ + "MONITOR_WW2A1_1", + "VFRAME_WW2A1" + ], + [ + "MONITOR_EE4B2_1", + "VFRAME_EE4B2" + ], + [ + "MONITOR_EE4B0_1", + "VFRAME_EE4B0" + ], + [ + "MONITOR_IMUX44_1", + "VFRAME_IMUX44" + ], + [ + "MONITOR_WL1END0_1", + "VFRAME_WL1END0" + ], + [ + "MONITOR_IMUX45_1", + "VFRAME_IMUX45" + ], + [ + "MONITOR_WW4B3_1", + "VFRAME_WW4B3" + ], + [ + "MONITOR_SW4END0_1", + "VFRAME_SW4END0" + ], + [ + "MONITOR_WW2A3_1", + "VFRAME_WW2A3" + ], + [ + "MONITOR_IMUX5_1", + "VFRAME_IMUX5" + ], + [ + "MONITOR_WW4A0_1", + "VFRAME_WW4A0" + ], + [ + "MONITOR_NW4END1_1", + "VFRAME_NW4END1" + ], + [ + "MONITOR_EE2BEG1_1", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_EE2BEG3_1", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_NW4END0_1", + "VFRAME_NW4END0" + ], + [ + "MONITOR_IMUX27_1", + "VFRAME_IMUX27" + ], + [ + "MONITOR_LOGIC_OUTS_B20_1", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "MONITOR_LOGIC_OUTS_B21_1", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "MONITOR_IMUX2_1", + "VFRAME_IMUX2" + ], + [ + "MONITOR_CLK1_1", + "VFRAME_CLK1" + ], + [ + "MONITOR_EE4C1_1", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX37_1", + "VFRAME_IMUX37" + ], + [ + "MONITOR_WW4A1_1", + "VFRAME_WW4A1" + ], + [ + "MONITOR_SE2A3_1", + "VFRAME_SE2A3" + ], + [ + "MONITOR_IMUX21_1", + "VFRAME_IMUX21" + ], + [ + "MONITOR_LOGIC_OUTS_B23_1", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "MONITOR_LH1_1", + "VFRAME_LH1" + ], + [ + "MONITOR_WW4C3_1", + "VFRAME_WW4C3" + ], + [ + "MONITOR_IMUX20_1", + "VFRAME_IMUX20" + ], + [ + "MONITOR_LOGIC_OUTS_B12_1", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "MONITOR_LOGIC_OUTS_B18_1", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "MONITOR_LH3_1", + "VFRAME_LH3" + ], + [ + "MONITOR_IMUX34_1", + "VFRAME_IMUX34" + ], + [ + "MONITOR_NW2A1_1", + "VFRAME_NW2A1" + ], + [ + "MONITOR_WW4END0_1", + "VFRAME_WW4END0" + ], + [ + "MONITOR_NE4C3_1", + "VFRAME_NE4C3" + ], + [ + "MONITOR_IMUX15_1", + "VFRAME_IMUX15" + ], + [ + "MONITOR_WW2END2_1", + "VFRAME_WW2END2" + ], + [ + "MONITOR_FAN2_1", + "VFRAME_FAN2" + ], + [ + "MONITOR_NW2A0_1", + "VFRAME_NW2A0" + ], + [ + "MONITOR_IMUX18_1", + "VFRAME_IMUX18" + ], + [ + "MONITOR_IMUX6_1", + "VFRAME_IMUX6" + ], + [ + "MONITOR_IMUX35_1", + "VFRAME_IMUX35" + ], + [ + "MONITOR_WW4B2_1", + "VFRAME_WW4B2" + ], + [ + "MONITOR_SE4BEG2_1", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_LH12_1", + "VFRAME_LH12" + ], + [ + "MONITOR_WW4A2_1", + "VFRAME_WW4A2" + ], + [ + "MONITOR_NW4END3_1", + "VFRAME_NW4END3" + ], + [ + "MONITOR_WW4END3_1", + "VFRAME_WW4END3" + ], + [ + "MONITOR_IMUX28_1", + "VFRAME_IMUX28" + ], + [ + "MONITOR_EE4BEG0_1", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_LOGIC_OUTS_B22_1", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "MONITOR_WW2END1_1", + "VFRAME_WW2END1" + ], + [ + "MONITOR_IMUX26_1", + "VFRAME_IMUX26" + ], + [ + "MONITOR_EE4C2_1", + "VFRAME_EE4C2" + ], + [ + "MONITOR_SE2A0_1", + "VFRAME_SE2A0" + ], + [ + "MONITOR_NW2A2_1", + "VFRAME_NW2A2" + ], + [ + "MONITOR_WW4END2_1", + "VFRAME_WW4END2" + ], + [ + "MONITOR_ER1BEG1_1", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_BYP6_1", + "VFRAME_BYP6" + ], + [ + "MONITOR_BYP7_1", + "VFRAME_BYP7" + ], + [ + "MONITOR_WR1END1_1", + "VFRAME_WR1END1" + ], + [ + "MONITOR_IMUX24_1", + "VFRAME_IMUX24" + ], + [ + "MONITOR_LOGIC_OUTS_B13_1", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "MONITOR_SW4A1_1", + "VFRAME_SW4A1" + ], + [ + "MONITOR_WR1END2_1", + "VFRAME_WR1END2" + ], + [ + "MONITOR_IMUX8_1", + "VFRAME_IMUX8" + ], + [ + "MONITOR_SW4A3_1", + "VFRAME_SW4A3" + ], + [ + "MONITOR_SW4END2_1", + "VFRAME_SW4END2" + ], + [ + "MONITOR_IMUX47_1", + "VFRAME_IMUX47" + ], + [ + "MONITOR_IMUX36_1", + "VFRAME_IMUX36" + ], + [ + "MONITOR_LOGIC_OUTS_B17_1", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "MONITOR_SW2A2_1", + "VFRAME_SW2A2" + ], + [ + "MONITOR_SE4C1_1", + "VFRAME_SE4C1" + ], + [ + "MONITOR_FAN4_1", + "VFRAME_FAN4" + ], + [ + "MONITOR_CTRL0_1", + "VFRAME_CTRL0" + ], + [ + "MONITOR_SE2A1_1", + "VFRAME_SE2A1" + ], + [ + "MONITOR_IMUX22_1", + "VFRAME_IMUX22" + ], + [ + "MONITOR_LH2_1", + "VFRAME_LH2" + ], + [ + "MONITOR_EL1BEG3_1", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_NW4A3_1", + "VFRAME_NW4A3" + ], + [ + "MONITOR_CTRL1_1", + "VFRAME_CTRL1" + ], + [ + "MONITOR_SW2A3_1", + "VFRAME_SW2A3" + ], + [ + "MONITOR_WL1END2_1", + "VFRAME_WL1END2" + ], + [ + "MONITOR_LH4_1", + "VFRAME_LH4" + ], + [ + "MONITOR_IMUX25_1", + "VFRAME_IMUX25" + ], + [ + "MONITOR_BYP0_1", + "VFRAME_BYP0" + ], + [ + "MONITOR_WW4C1_1", + "VFRAME_WW4C1" + ], + [ + "MONITOR_EE2A3_1", + "VFRAME_EE2A3" + ], + [ + "MONITOR_EE4A3_1", + "VFRAME_EE4A3" + ], + [ + "MONITOR_IMUX23_1", + "VFRAME_IMUX23" + ], + [ + "MONITOR_SE2A2_1", + "VFRAME_SE2A2" + ], + [ + "MONITOR_EE4C0_1", + "VFRAME_EE4C0" + ], + [ + "MONITOR_NE4C1_1", + "VFRAME_NE4C1" + ], + [ + "MONITOR_WL1END3_1", + "VFRAME_WL1END3" + ], + [ + "MONITOR_IMUX1_1", + "VFRAME_IMUX1" + ], + [ + "MONITOR_NE4C0_1", + "VFRAME_NE4C0" + ], + [ + "MONITOR_IMUX11_1", + "VFRAME_IMUX11" + ], + [ + "MONITOR_BYP4_1", + "VFRAME_BYP4" + ], + [ + "MONITOR_SW2A0_1", + "VFRAME_SW2A0" + ], + [ + "MONITOR_LH6_1", + "VFRAME_LH6" + ], + [ + "MONITOR_SE4BEG1_1", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_LH7_1", + "VFRAME_LH7" + ], + [ + "MONITOR_NW4END2_1", + "VFRAME_NW4END2" + ], + [ + "MONITOR_BYP5_1", + "VFRAME_BYP5" + ], + [ + "MONITOR_IMUX14_1", + "VFRAME_IMUX14" + ], + [ + "MONITOR_WW4A3_1", + "VFRAME_WW4A3" + ], + [ + "MONITOR_NE2A2_1", + "VFRAME_NE2A2" + ], + [ + "MONITOR_IMUX32_1", + "VFRAME_IMUX32" + ], + [ + "MONITOR_IMUX13_1", + "VFRAME_IMUX13" + ], + [ + "MONITOR_IMUX17_1", + "VFRAME_IMUX17" + ], + [ + "MONITOR_WW4C2_1", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE2A0_1", + "VFRAME_EE2A0" + ], + [ + "MONITOR_IMUX9_1", + "VFRAME_IMUX9" + ], + [ + "MONITOR_IMUX39_1", + "VFRAME_IMUX39" + ], + [ + "MONITOR_SW4END3_1", + "VFRAME_SW4END3" + ], + [ + "MONITOR_IMUX19_1", + "VFRAME_IMUX19" + ] + ], + "tile_types": [ + "MONITOR_BOT_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "LIOB_IN_TERM0", + "LIOI_DCI_T_TERM0" + ], + [ + "IOB_PD_INT_EN_0", + "LIOI_PD_INT_EN_0" + ], + [ + "IOB_KEEPER_INT_EN_0", + "LIOI_KEEPER_INT_EN_0" + ], + [ + "LIOB_MONITOR_N", + "IOI_MONITOR_N" + ], + [ + "IOB_IBUF0", + "LIOI_IBUF0" + ], + [ + "IOB_KEEPER_INT_EN_1", + "LIOI_KEEPER_INT_EN_1" + ], + [ + "IOB_PU_INT_EN_1", + "LIOI_PU_INT_EN_1" + ], + [ + "IOB_T1", + "LIOI_T1" + ], + [ + "LIOB_IN_TERM1", + "LIOI_DCI_T_TERM1" + ], + [ + "IOB_PU_INT_EN_0", + "LIOI_PU_INT_EN_0" + ], + [ + "IOB_PD_INT_EN_1", + "LIOI_PD_INT_EN_1" + ], + [ + "IOB_O1", + "LIOI_O1" + ], + [ + "LIOB_MONITOR_P", + "IOI_MONITOR_P" + ], + [ + "IOB_T0", + "LIOI_T0" + ], + [ + "IOB_IBUF1", + "LIOI_IBUF1" + ], + [ + "IOB_IBUF_DISABLE1", + "LIOI_IBUF_DISABLE1" + ], + [ + "IOB_IBUF_DISABLE0", + "LIOI_IBUF_DISABLE0" + ], + [ + "IOB_O0", + "LIOI_O0" + ], + [ + "IOB_DIFF_TERM_INT_EN", + "LIOI_DIFF_TERM_INT_EN" + ] + ], + "tile_types": [ + "LIOB33", + "LIOI3_TBYTESRC" + ] + }, + { + "grid_deltas": [ + 5, + -8 + ], + "wire_pairs": [ + [ + "PCIE_IMUX33_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_WW4A2_18", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_EE2BEG2_18", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_NW2A3_18", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_IMUX38_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_NE4BEG0_18", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_CTRL0_L_18", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_EE2BEG0_18", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_EE4BEG3_18", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_CLK1_L_18", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_LH3_18", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_SW4A1_18", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_IMUX47_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_ER1BEG1_18", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_EE4B2_18", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_IMUX34_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_SE2A3_18", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_EE4A3_18", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_EE4BEG2_18", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_WW4C1_18", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_SE4C2_18", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_ER1BEG2_18", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_EE2A1_18", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_NE4BEG2_18", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_SW2A0_18", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_SW2A2_18", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_NW4A0_18", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_NW4END3_18", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_IMUX3_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_NW2A2_18", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_LH8_18", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4BEG0_18", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_WW4A1_18", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_FAN0_L_18", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_IMUX35_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_FAN4_L_18", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_NW2A0_18", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_SW4END0_18", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_LH10_18", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_WW4C2_18", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_IMUX28_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_IMUX15_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_LH2_18", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_BYP4_L_18", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_IMUX16_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_WW4B3_18", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_IMUX8_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_IMUX36_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_WW4END0_18", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_IMUX2_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_IMUX1_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_IMUX21_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_LH12_18", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_SE4BEG1_18", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_BYP3_L_18", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_WW4END2_18", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_SW4END3_18", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_BYP0_L_18", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_NE2A1_18", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_EE4C2_18", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_FAN6_L_18", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_WR1END1_18", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_EE2BEG3_18", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_WW4END1_18", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_IMUX0_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_WW4A3_18", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_IMUX27_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_EL1BEG3_18", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_BYP1_L_18", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_WL1END0_18", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_NE4BEG3_18", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_NE2A2_18", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_IMUX30_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_LH4_18", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_WW2END1_18", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_NE4C1_18", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_WR1END3_18", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_IMUX5_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_IMUX17_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_NW4A1_18", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_WR1END2_18", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_BYP7_L_18", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_LH11_18", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_WW2A2_18", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_SW4END1_18", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_WW4C3_18", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_FAN7_L_18", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_SE2A1_18", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_SE2A2_18", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_SE4C1_18", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_IMUX20_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_SE2A0_18", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_IMUX26_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_IMUX29_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_IMUX44_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_IMUX19_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_IMUX4_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_SE4BEG3_18", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_EE2BEG1_18", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_EL1BEG0_18", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_IMUX11_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_IMUX43_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_IMUX22_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_BYP5_L_18", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_SE4BEG2_18", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_EE4B3_18", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_WW2END0_18", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_WW2END3_18", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_EE2A2_18", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_WR1END0_18", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_WW4B0_18", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_NE2A0_18", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_WW4A0_18", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_NW2A1_18", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_ER1BEG3_18", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_SE4C3_18", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_EE4C3_18", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_IMUX31_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_SW4A0_18", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_NW4A2_18", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_FAN5_L_18", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_EE4B1_18", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_WW2A1_18", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_BYP6_L_18", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_WW2END2_18", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_NW4END2_18", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_EL1BEG2_18", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_IMUX18_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_EE4A0_18", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_IMUX42_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_ER1BEG0_18", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_WW4B1_18", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_WL1END1_18", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_NE4C2_18", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_IMUX24_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_WW4C0_18", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_SW4A2_18", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_WL1END3_18", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_IMUX41_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_FAN2_L_18", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_CTRL1_L_18", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_SE4C0_18", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_IMUX40_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_CLK0_L_18", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_BYP2_L_18", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_IMUX14_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_IMUX46_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_EE2A3_18", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_NE2A3_18", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_WW4B2_18", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_WL1END2_18", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_EE2A0_18", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_IMUX6_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_EL1BEG1_18", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_SW4END2_18", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_SE4BEG0_18", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_IMUX12_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_NE4BEG1_18", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_EE4A2_18", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_IMUX32_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_EE4A1_18", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_EE4C0_18", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_WW4END3_18", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_FAN3_L_18", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX7_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_NW4A3_18", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_IMUX45_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_NE4C3_18", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_EE4B0_18", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_WW2A3_18", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_EE4C1_18", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_LH9_18", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_NW4END1_18", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_FAN1_L_18", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_EE4BEG1_18", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_IMUX37_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_LH1_18", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_NE4C0_18", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_NW4END0_18", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_LH7_18", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_IMUX23_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_IMUX10_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_SW2A3_18", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_IMUX9_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_LH5_18", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_LH6_18", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_IMUX39_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_IMUX13_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_18", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_SW2A1_18", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_WW2A0_18", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_SW4A3_18", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_IMUX25_L_18", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "CLBLM_SW4END1", + "DSP_SW4END1_1" + ], + [ + "CLBLM_WL1END3", + "DSP_WL1END3_1" + ], + [ + "CLBLM_WW4C2", + "DSP_WW4C2_1" + ], + [ + "CLBLM_WW4END1", + "DSP_WW4END1_1" + ], + [ + "CLBLM_NE4C1", + "DSP_NE4C1_1" + ], + [ + "CLBLM_NE2A1", + "DSP_NE2A1_1" + ], + [ + "CLBLM_EE4C0", + "DSP_EE4C0_1" + ], + [ + "CLBLM_EE2BEG2", + "DSP_EE2BEG2_1" + ], + [ + "CLBLM_EE4C2", + "DSP_EE4C2_1" + ], + [ + "CLBLM_SW2A3", + "DSP_SW2A3_1" + ], + [ + "CLBLM_EE4A1", + "DSP_EE4A1_1" + ], + [ + "CLBLM_NW4END3", + "DSP_NW4END3_1" + ], + [ + "CLBLM_LH10", + "DSP_LH10_1" + ], + [ + "CLBLM_NE4C3", + "DSP_NE4C3_1" + ], + [ + "CLBLM_WW4B2", + "DSP_WW4B2_1" + ], + [ + "CLBLM_NW4END2", + "DSP_NW4END2_1" + ], + [ + "CLBLM_EE4B0", + "DSP_EE4B0_1" + ], + [ + "CLBLM_WL1END2", + "DSP_WL1END2_1" + ], + [ + "CLBLM_WW2END3", + "DSP_WW2END3_1" + ], + [ + "CLBLM_SE4C0", + "DSP_SE4C0_1" + ], + [ + "CLBLM_NW2A1", + "DSP_NW2A1_1" + ], + [ + "CLBLM_EE4BEG0", + "DSP_EE4BEG0_1" + ], + [ + "CLBLM_SW2A2", + "DSP_SW2A2_1" + ], + [ + "CLBLM_NW2A2", + "DSP_NW2A2_1" + ], + [ + "CLBLM_LH2", + "DSP_LH2_1" + ], + [ + "CLBLM_NW4A1", + "DSP_NW4A1_1" + ], + [ + "CLBLM_SW4A1", + "DSP_SW4A1_1" + ], + [ + "CLBLM_SE4BEG3", + "DSP_SE4BEG3_1" + ], + [ + "CLBLM_SW2A1", + "DSP_SW2A1_1" + ], + [ + "CLBLM_SW2A0", + "DSP_SW2A0_1" + ], + [ + "CLBLM_WW4A2", + "DSP_WW4A2_1" + ], + [ + "CLBLM_EE2BEG3", + "DSP_EE2BEG3_1" + ], + [ + "CLBLM_WW4B0", + "DSP_WW4B0_1" + ], + [ + "CLBLM_LH3", + "DSP_LH3_1" + ], + [ + "CLBLM_WW2A0", + "DSP_WW2A0_1" + ], + [ + "CLBLM_EE2A3", + "DSP_EE2A3_1" + ], + [ + "CLBLM_EE4B3", + "DSP_EE4B3_1" + ], + [ + "CLBLM_ER1BEG3", + "DSP_ER1BEG3_1" + ], + [ + "CLBLM_EE4C3", + "DSP_EE4C3_1" + ], + [ + "CLBLM_SE4BEG1", + "DSP_SE4BEG1_1" + ], + [ + "CLBLM_SW4END2", + "DSP_SW4END2_1" + ], + [ + "CLBLM_WW4END2", + "DSP_WW4END2_1" + ], + [ + "CLBLM_EE4BEG3", + "DSP_EE4BEG3_1" + ], + [ + "CLBLM_NE4C0", + "DSP_NE4C0_1" + ], + [ + "CLBLM_NE2A0", + "DSP_NE2A0_1" + ], + [ + "CLBLM_LH4", + "DSP_LH4_1" + ], + [ + "CLBLM_WW2END1", + "DSP_WW2END1_1" + ], + [ + "CLBLM_LH12", + "DSP_LH12_1" + ], + [ + "CLBLM_EE4C1", + "DSP_EE4C1_1" + ], + [ + "CLBLM_EE4A0", + "DSP_EE4A0_1" + ], + [ + "CLBLM_EE4B2", + "DSP_EE4B2_1" + ], + [ + "CLBLM_SE2A0", + "DSP_SE2A0_1" + ], + [ + "CLBLM_SE4C3", + "DSP_SE4C3_1" + ], + [ + "CLBLM_EE2A0", + "DSP_EE2A0_1" + ], + [ + "CLBLM_NW4A3", + "DSP_NW4A3_1" + ], + [ + "CLBLM_EE2A2", + "DSP_EE2A2_1" + ], + [ + "CLBLM_WW4END3", + "DSP_WW4END3_1" + ], + [ + "CLBLM_NW4END1", + "DSP_NW4END1_1" + ], + [ + "CLBLM_LH11", + "DSP_LH11_1" + ], + [ + "CLBLM_MONITOR_N", + "DSP_MONITOR_N_1" + ], + [ + "CLBLM_WW2A3", + "DSP_WW2A3_1" + ], + [ + "CLBLM_EE4A2", + "DSP_EE4A2_1" + ], + [ + "CLBLM_LH5", + "DSP_LH5_1" + ], + [ + "CLBLM_WW2A2", + "DSP_WW2A2_1" + ], + [ + "CLBLM_EE4BEG1", + "DSP_EE4BEG1_1" + ], + [ + "CLBLM_NW2A0", + "DSP_NW2A0_1" + ], + [ + "CLBLM_WR1END2", + "DSP_WR1END2_1" + ], + [ + "CLBLM_NE4BEG1", + "DSP_NE4BEG1_1" + ], + [ + "CLBLM_EL1BEG3", + "DSP_EL1BEG3_1" + ], + [ + "CLBLM_WW4A3", + "DSP_WW4A3_1" + ], + [ + "CLBLM_NW4A0", + "DSP_NW4A0_1" + ], + [ + "CLBLM_NE4BEG3", + "DSP_NE4BEG3_1" + ], + [ + "CLBLM_SW4A0", + "DSP_SW4A0_1" + ], + [ + "CLBLM_SE2A3", + "DSP_SE2A3_1" + ], + [ + "CLBLM_EE4BEG2", + "DSP_EE4BEG2_1" + ], + [ + "CLBLM_WW4C3", + "DSP_WW4C3_1" + ], + [ + "CLBLM_EE4A3", + "DSP_EE4A3_1" + ], + [ + "CLBLM_NW2A3", + "DSP_NW2A3_1" + ], + [ + "CLBLM_WW4B3", + "DSP_WW4B3_1" + ], + [ + "CLBLM_SE4BEG0", + "DSP_SE4BEG0_1" + ], + [ + "CLBLM_SW4A3", + "DSP_SW4A3_1" + ], + [ + "CLBLM_WL1END0", + "DSP_WL1END0_1" + ], + [ + "CLBLM_WW2END2", + "DSP_WW2END2_1" + ], + [ + "CLBLM_SE4C2", + "DSP_SE4C2_1" + ], + [ + "CLBLM_WW4A1", + "DSP_WW4A1_1" + ], + [ + "CLBLM_WW2END0", + "DSP_WW2END0_1" + ], + [ + "CLBLM_EE2A1", + "DSP_EE2A1_1" + ], + [ + "CLBLM_LH1", + "DSP_LH1_1" + ], + [ + "CLBLM_EE2BEG0", + "DSP_EE2BEG0_1" + ], + [ + "CLBLM_LH8", + "DSP_LH8_1" + ], + [ + "CLBLM_NE4BEG0", + "DSP_NE4BEG0_1" + ], + [ + "CLBLM_NW4A2", + "DSP_NW4A2_1" + ], + [ + "CLBLM_WW4END0", + "DSP_WW4END0_1" + ], + [ + "CLBLM_SE2A1", + "DSP_SE2A1_1" + ], + [ + "CLBLM_WW4C0", + "DSP_WW4C0_1" + ], + [ + "CLBLM_SW4END3", + "DSP_SW4END3_1" + ], + [ + "CLBLM_NE4BEG2", + "DSP_NE4BEG2_1" + ], + [ + "CLBLM_WW2A1", + "DSP_WW2A1_1" + ], + [ + "CLBLM_WW4C1", + "DSP_WW4C1_1" + ], + [ + "CLBLM_ER1BEG0", + "DSP_ER1BEG0_1" + ], + [ + "CLBLM_ER1BEG2", + "DSP_ER1BEG2_1" + ], + [ + "CLBLM_NE2A3", + "DSP_NE2A3_1" + ], + [ + "CLBLM_NW4END0", + "DSP_NW4END0_1" + ], + [ + "CLBLM_EE2BEG1", + "DSP_EE2BEG1_1" + ], + [ + "CLBLM_NE4C2", + "DSP_NE4C2_1" + ], + [ + "CLBLM_SW4END0", + "DSP_SW4END0_1" + ], + [ + "CLBLM_NE2A2", + "DSP_NE2A2_1" + ], + [ + "CLBLM_SE4C1", + "DSP_SE4C1_1" + ], + [ + "CLBLM_SW4A2", + "DSP_SW4A2_1" + ], + [ + "CLBLM_LH7", + "DSP_LH7_1" + ], + [ + "CLBLM_WL1END1", + "DSP_WL1END1_1" + ], + [ + "CLBLM_SE2A2", + "DSP_SE2A2_1" + ], + [ + "CLBLM_LH9", + "DSP_LH9_1" + ], + [ + "CLBLM_SE4BEG2", + "DSP_SE4BEG2_1" + ], + [ + "CLBLM_EE4B1", + "DSP_EE4B1_1" + ], + [ + "CLBLM_EL1BEG1", + "DSP_EL1BEG1_1" + ], + [ + "CLBLM_ER1BEG1", + "DSP_ER1BEG1_1" + ], + [ + "CLBLM_WR1END3", + "DSP_WR1END3_1" + ], + [ + "CLBLM_WW4B1", + "DSP_WW4B1_1" + ], + [ + "CLBLM_EL1BEG0", + "DSP_EL1BEG0_1" + ], + [ + "CLBLM_WW4A0", + "DSP_WW4A0_1" + ], + [ + "CLBLM_MONITOR_P", + "DSP_MONITOR_P_1" + ], + [ + "CLBLM_WR1END0", + "DSP_WR1END0_1" + ], + [ + "CLBLM_WR1END1", + "DSP_WR1END1_1" + ], + [ + "CLBLM_LH6", + "DSP_LH6_1" + ], + [ + "CLBLM_EL1BEG2", + "DSP_EL1BEG2_1" + ] + ], + "tile_types": [ + "CLBLM_L", + "DSP_R" + ] + }, + { + "grid_deltas": [ + 1, + 11 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4C2_0", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX20_0", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_WW4B3_0", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_WW4C0_0", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_EE4BEG3_0", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_WL1END1_0", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_0", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_LH4_0", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_SW4END0_0", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX23_0", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW2END0_0", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_SW2A2_0", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_WW2A2_0", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_WL1END0_0", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_0", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_IMUX11_0", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX0_0", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_FAN6_0", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX5_0", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_NW4END3_0", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_0", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_SE2A2_0", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_WW4A2_0", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_FAN4_0", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_LH7_0", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_NE4BEG1_0", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_FAN5_0", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SW4A3_0", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_IMUX24_0", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_NE2A1_0", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_SE4BEG3_0", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_WW4A3_0", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW4END1_0", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B11_0", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "CFG_CENTER_IMUX32_0", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_BYP2_0", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_WW4C3_0", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_EE4A1_0", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_SW4A1_0", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_IMUX2_0", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_WW4C1_0", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_BYP0_0", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX44_0", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_SW4A2_0", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NE4BEG2_0", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_IMUX18_0", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_CTRL0_0", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_SE2A0_0", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_SW4END2_0", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_ER1BEG2_0", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_ER1BEG1_0", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_NE4C3_0", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_LH9_0", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_IMUX9_0", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX25_0", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_IMUX41_0", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_EL1BEG2_0", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NW2A1_0", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B10_0", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "CFG_CENTER_IMUX14_0", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_NW4END2_0", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_IMUX4_0", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_WW2END1_0", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_CLK0_0", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX28_0", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX21_0", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_NW2A3_0", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_0", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_NE4BEG0_0", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX7_0", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_0", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_IMUX17_0", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX10_0", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SW2A3_0", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_ER1BEG3_0", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_SE4BEG2_0", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_IMUX39_0", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B9_0", + "VFRAME_LOGIC_OUTS_B9" + ], + [ + "CFG_CENTER_NW4END0_0", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_EL1BEG1_0", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_EE2BEG0_0", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_0", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_WW4B1_0", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_EE4BEG1_0", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_IMUX36_0", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_WW4END3_0", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_0", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_EL1BEG0_0", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_IMUX8_0", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_BYP7_0", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_CLK1_0", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_WW2A3_0", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX27_0", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX46_0", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_EE2A1_0", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_SE4C2_0", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_EE2BEG1_0", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_SW4END3_0", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_EE4B1_0", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_WW4B2_0", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_LH12_0", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_WW4A0_0", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_WL1END3_0", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_NW2A2_0", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B8_0", + "VFRAME_LOGIC_OUTS_B8" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_0", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_SW4A0_0", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_FAN0_0", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX29_0", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_NW4A3_0", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_FAN3_0", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_WW4C2_0", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_NW4A1_0", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_FAN1_0", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX42_0", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_LH5_0", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX31_0", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_WR1END1_0", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_LH6_0", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_SW4END1_0", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_SW2A0_0", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_EE4A3_0", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX38_0", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_WR1END2_0", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_0", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_EE2A2_0", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_WW4B0_0", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_EE2A3_0", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NE2A2_0", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WR1END0_0", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_FAN2_0", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_IMUX22_0", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX1_0", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_LH3_0", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_NE4BEG3_0", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX13_0", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_NW2A0_0", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_LH1_0", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NW4A0_0", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX19_0", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_LH2_0", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EE2BEG3_0", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX12_0", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_0", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_EE4C1_0", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX45_0", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_BYP6_0", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_0", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_0", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_SE4C0_0", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_WW2A0_0", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_IMUX47_0", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_WW4END2_0", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_EE4B2_0", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX6_0", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_WW4A1_0", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_SE4C3_0", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX34_0", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_BYP5_0", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_SE2A1_0", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_EE4C0_0", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_EE4B0_0", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WL1END2_0", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_FAN7_0", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_WW2A1_0", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_EE4B3_0", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_IMUX15_0", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_WR1END3_0", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_SE4BEG0_0", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_ER1BEG0_0", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_NE4C0_0", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EL1BEG3_0", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_NW4A2_0", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_NE4C1_0", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_NE4C2_0", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_EE2A0_0", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_SE4C1_0", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_LH11_0", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_BYP1_0", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SE4BEG1_0", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE4BEG2_0", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX33_0", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_IMUX40_0", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_LH10_0", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_SE2A3_0", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_IMUX26_0", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_LH8_0", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_SW2A1_0", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WW2END3_0", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_NE2A0_0", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX3_0", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_BYP3_0", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_EE4A2_0", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_EE2BEG2_0", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX30_0", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_IMUX37_0", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_NW4END1_0", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_IMUX16_0", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX43_0", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_WW4END0_0", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX35_0", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_BYP4_0", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WW2END2_0", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_EE4A0_0", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_EE4C3_0", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_NE2A3_0", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_CTRL1_0", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_EE4BEG0_0", + "VFRAME_EE4BEG0" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_PMV2" + ] + }, + { + "grid_deltas": [ + -1, + 10 + ], + "wire_pairs": [ + [ + "PCIE_EE4B0_0", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_NE4BEG1_0", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX41_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_FAN5_R_0", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_WW2A2_0", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_IMUX27_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_NW2A0_0", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_NW4END1_0", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_0", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_SE2A2_0", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_NE4C1_0", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_SE4C2_0", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_WL1END2_0", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_BYP7_R_0", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_EE4BEG0_0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_BYP6_R_0", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_IMUX24_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_WW4B2_0", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_WW4END2_0", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_WW4END0_0", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_LH8_0", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_IMUX33_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_IMUX14_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_CLK1_R_0", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_WR1END2_0", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_NE2A2_0", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_WW2END3_0", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_0", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_NE2A3_0", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_0", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_0", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_SW4A2_0", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_WW4END1_0", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_EL1BEG0_0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_IMUX17_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_LH2_0", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_0", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_WW4C3_0", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_SW4END3_0", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_IMUX35_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_IMUX15_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_IMUX10_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_LH5_0", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_WL1END0_0", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_IMUX28_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_EE4B3_0", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_SE4BEG0_0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_IMUX32_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_0", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_SW2A3_0", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_WW4A3_0", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_IMUX45_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_WW4B0_0", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_0", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_EE4C2_0", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_IMUX36_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_EE2BEG2_0", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_NE4BEG3_0", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_LH3_0", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_EE2BEG0_0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_EE2BEG3_0", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_0", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_EE4C1_0", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_WW2A0_0", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_0", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_0", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_IMUX12_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_LH4_0", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_WR1END3_0", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_IMUX4_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_NE4C3_0", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_IMUX5_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_NW4END2_0", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_ER1BEG1_0", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_WW4C2_0", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_NE2A1_0", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_EL1BEG3_0", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_FAN0_R_0", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_0", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_EE4B2_0", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_SE4BEG2_0", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_WW4A2_0", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_SW4A1_0", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_WL1END1_0", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_BYP1_R_0", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_SW2A2_0", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_IMUX16_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_IMUX42_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_EE4B1_0", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_SW4A0_0", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_WW2A1_0", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_WW4C0_0", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_NW4A0_0", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WR1END1_0", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_IMUX21_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_SE4C0_0", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_0", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_EE4C3_0", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_WW4B3_0", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_0", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_WW4A0_0", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_BYP2_R_0", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_EE4A0_0", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_FAN6_R_0", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_EE4BEG2_0", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_0", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_NE2A0_0", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_0", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_IMUX44_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_WW4B1_0", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_CTRL0_R_0", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_BYP5_R_0", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_IMUX1_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_EE2A1_0", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_EE2A2_0", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_IMUX31_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_LH9_0", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_NW4END0_0", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_IMUX39_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_WL1END3_0", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_IMUX37_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_IMUX18_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_SW4END0_0", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_0", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_NW4END3_0", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_WW2END0_0", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_IMUX7_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_IMUX23_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_NE4C0_0", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_EE2A3_0", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_IMUX0_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_IMUX13_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_NW2A2_0", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_ER1BEG3_0", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_EE4A1_0", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_SE2A0_0", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_EE4BEG3_0", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_IMUX2_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_IMUX29_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_FAN4_R_0", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_0", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_SW2A0_0", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX19_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_IMUX46_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_SE2A1_0", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_EE4C0_0", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_LH1_0", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_IMUX22_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_LH7_0", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_SE4C3_0", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_SE4C1_0", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_SE4BEG3_0", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_NW4A3_0", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_FAN7_R_0", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_LH10_0", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_0", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_WW4A1_0", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_WW2A3_0", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_NW4A1_0", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_EE2A0_0", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_EE2BEG1_0", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX6_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_IMUX25_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_IMUX47_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_IMUX8_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_0", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_IMUX3_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_IMUX20_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_SW4END1_0", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_0", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_BYP4_R_0", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_CTRL1_R_0", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_EL1BEG1_0", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_ER1BEG0_0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_NE4BEG0_0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_SE4BEG1_0", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_WW2END1_0", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_IMUX26_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_0", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_BYP3_R_0", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_SW4A3_0", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_NW2A1_0", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_WW4END3_0", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_ER1BEG2_0", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_IMUX38_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_LH11_0", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_BYP0_R_0", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_FAN3_R_0", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX9_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_IMUX11_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_EL1BEG2_0", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_0", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_FAN2_R_0", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_CLK0_R_0", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_IMUX43_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_0", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_FAN1_R_0", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_IMUX40_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_LH12_0", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_IMUX30_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_WW4C1_0", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_NE4BEG2_0", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_LH6_0", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_NE4C2_0", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_SE2A3_0", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_SW2A1_0", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_IMUX34_R_0", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_WR1END0_0", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_NW4A2_0", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_EE4A2_0", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_0", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_SW4END2_0", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_EE4BEG1_0", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_WW2END2_0", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_EE4A3_0", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_NW2A3_0", + "INT_INTERFACE_NW2A3" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_0" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_0" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_0" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_0" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_0" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_0" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_0" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_0" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_0" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_0" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_0" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_0" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_0" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_0" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_0" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_0" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_0" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_0" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_0" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_0" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_0" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_0" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_0" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_0" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_0" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_0" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_0" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_0" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_0" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_0" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_0" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_0" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_0" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_0" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_0" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_0" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_0" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_0" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_0" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_0" + ], + [ + "INT_FEEDTHRU_2_MONITOR_P", + "MONITOR_HORIZ_VAUXP5_LEFT" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_0" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_0" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_0" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_0" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_0" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_0" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_0" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_0" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_0" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_0" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_0" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_0" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_0" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_0" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_0" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_0" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_0" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_0" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_0" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_0" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_0" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_0" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_0" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_0" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_0" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_0" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_0" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_0" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_0" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_0" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_0" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_0" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_0" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_0" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_0" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_0" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_0" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_0" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_0" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_0" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_0" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_0" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_0" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_0" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_0" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_0" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_0" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_0" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_0" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_0" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_0" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_0" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_0" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_0" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_0" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_0" + ], + [ + "INT_FEEDTHRU_2_MONITOR_N", + "MONITOR_HORIZ_VAUXN5_LEFT" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_0" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_0" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_0" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_0" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_0" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_0" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_0" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_0" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_0" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_0" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_0" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_0" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_0" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_0" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_0" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_0" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_0" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_0" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_0" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_0" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_0" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_0" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_0" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_0" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_0" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_0" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_0" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_0" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_BOT_FUJI2" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "IOI_IMUX11_0", + "TERM_INT_IMUX11" + ], + [ + "IOI_IMUX43_0", + "TERM_INT_IMUX43" + ], + [ + "IOI_FAN1_0", + "TERM_INT_FAN1" + ], + [ + "IOI_LOGIC_OUTS18_0", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_CTRL1_0", + "TERM_INT_CTRL1" + ], + [ + "IOI_BYP2_0", + "TERM_INT_BYP2" + ], + [ + "IOI_LOGIC_OUTS2_0", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_IMUX6_0", + "TERM_INT_IMUX6" + ], + [ + "IOI_IMUX36_0", + "TERM_INT_IMUX36" + ], + [ + "IOI_IMUX34_0", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX0_0", + "TERM_INT_IMUX0" + ], + [ + "IOI_IMUX46_0", + "TERM_INT_IMUX46" + ], + [ + "IOI_LOGIC_OUTS23_0", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_IMUX20_0", + "TERM_INT_IMUX20" + ], + [ + "IOI_LOGIC_OUTS15_0", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX19_0", + "TERM_INT_IMUX19" + ], + [ + "IOI_IMUX47_0", + "TERM_INT_IMUX47" + ], + [ + "IOI_IMUX25_0", + "TERM_INT_IMUX25" + ], + [ + "IOI_LOGIC_OUTS7_0", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_FAN2_0", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX45_0", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX31_0", + "TERM_INT_IMUX31" + ], + [ + "IOI_LOGIC_OUTS19_0", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_IMUX1_0", + "TERM_INT_IMUX1" + ], + [ + "IOI_IMUX22_0", + "TERM_INT_IMUX22" + ], + [ + "IOI_IMUX12_0", + "TERM_INT_IMUX12" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_BLOCK_OUTS2_0", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "IOI_IMUX40_0", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX10_0", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX16_0", + "TERM_INT_IMUX16" + ], + [ + "IOI_FAN0_0", + "TERM_INT_FAN0" + ], + [ + "IOI_IMUX38_0", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX26_0", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX3_0", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX24_0", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX37_0", + "TERM_INT_IMUX37" + ], + [ + "IOI_LOGIC_OUTS3_0", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_FAN4_0", + "TERM_INT_FAN4" + ], + [ + "IOI_FAN6_0", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX7_0", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX39_0", + "TERM_INT_IMUX39" + ], + [ + "IOI_CLK0_0", + "TERM_INT_CLK0" + ], + [ + "IOI_CTRL0_0", + "TERM_INT_CTRL0" + ], + [ + "IOI_CLK1_0", + "TERM_INT_CLK1" + ], + [ + "IOI_FAN7_0", + "TERM_INT_FAN7" + ], + [ + "IOI_BYP0_0", + "TERM_INT_BYP0" + ], + [ + "IOI_LOGIC_OUTS0_0", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_IMUX8_0", + "TERM_INT_IMUX8" + ], + [ + "IOI_LOGIC_OUTS11_0", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_BYP6_0", + "TERM_INT_BYP6" + ], + [ + "IOI_IMUX42_0", + "TERM_INT_IMUX42" + ], + [ + "IOI_IMUX30_0", + "TERM_INT_IMUX30" + ], + [ + "IOI_LOGIC_OUTS1_0", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX5_0", + "TERM_INT_IMUX5" + ], + [ + "IOI_IMUX4_0", + "TERM_INT_IMUX4" + ], + [ + "IOI_IMUX17_0", + "TERM_INT_IMUX17" + ], + [ + "IOI_IMUX23_0", + "TERM_INT_IMUX23" + ], + [ + "IOI_IMUX33_0", + "TERM_INT_IMUX33" + ], + [ + "IOI_PHASER_TO_IO_ICLK", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_FAN5_0", + "TERM_INT_FAN5" + ], + [ + "IOI_LOGIC_OUTS9_0", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_BYP1_0", + "TERM_INT_BYP1" + ], + [ + "IOI_LOGIC_OUTS14_0", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_IMUX13_0", + "TERM_INT_IMUX13" + ], + [ + "IOI_IMUX44_0", + "TERM_INT_IMUX44" + ], + [ + "IOI_LOGIC_OUTS20_0", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_LOGIC_OUTS5_0", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_IMUX27_0", + "TERM_INT_IMUX27" + ], + [ + "IOI_IMUX18_0", + "TERM_INT_IMUX18" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_IMUX9_0", + "TERM_INT_IMUX9" + ], + [ + "IOI_FAN3_0", + "TERM_INT_FAN3" + ], + [ + "IOI_BYP5_0", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS8_0", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_PHASER_TO_IO_OCLK", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_BYP4_0", + "TERM_INT_BYP4" + ], + [ + "IOI_BYP7_0", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_0", + "TERM_INT_IMUX2" + ], + [ + "IOI_IMUX35_0", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP3_0", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX15_0", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX29_0", + "TERM_INT_IMUX29" + ], + [ + "IOI_LOGIC_OUTS10_0", + "TERM_INT_LOGIC_OUTS_L_B10" + ], + [ + "IOI_IMUX14_0", + "TERM_INT_IMUX14" + ], + [ + "IOI_IMUX21_0", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX28_0", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX41_0", + "TERM_INT_IMUX41" + ], + [ + "IOI_BLOCK_OUTS0_0", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_IMUX32_0", + "TERM_INT_IMUX32" + ] + ], + "tile_types": [ + "LIOI3_SING", + "L_TERM_INT" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLK_FEED_EE4B1", + "VBRK_EE4B1" + ], + [ + "CLK_FEED_SE4C1", + "VBRK_SE4C1" + ], + [ + "CLK_FEED_EE2BEG0", + "VBRK_EE2BEG0" + ], + [ + "CLK_FEED_SW2A1", + "VBRK_SW2A1" + ], + [ + "CLK_FEED_WR1END1", + "VBRK_WR1END1" + ], + [ + "CLK_FEED_WL1END3", + "VBRK_WL1END3" + ], + [ + "CLK_FEED_NE2A2", + "VBRK_NE2A2" + ], + [ + "CLK_FEED_WW2END0", + "VBRK_WW2END0" + ], + [ + "CLK_FEED_LH9", + "VBRK_LH9" + ], + [ + "CLK_FEED_EE4C1", + "VBRK_EE4C1" + ], + [ + "CLK_FEED_NW2A0", + "VBRK_NW2A0" + ], + [ + "CLK_FEED_WW4A1", + "VBRK_WW4A1" + ], + [ + "CLK_FEED_NE2A1", + "VBRK_NE2A1" + ], + [ + "CLK_FEED_WW4A3", + "VBRK_WW4A3" + ], + [ + "CLK_FEED_WW2END1", + "VBRK_WW2END1" + ], + [ + "CLK_FEED_WW4C3", + "VBRK_WW4C3" + ], + [ + "CLK_FEED_LH5", + "VBRK_LH5" + ], + [ + "CLK_FEED_LH10", + "VBRK_LH10" + ], + [ + "CLK_FEED_LH12", + "VBRK_LH12" + ], + [ + "CLK_FEED_EE4B0", + "VBRK_EE4B0" + ], + [ + "CLK_FEED_EE4A2", + "VBRK_EE4A2" + ], + [ + "CLK_FEED_WW4END2", + "VBRK_WW4END2" + ], + [ + "CLK_FEED_NE4C2", + "VBRK_NE4C2" + ], + [ + "CLK_FEED_NW4A1", + "VBRK_NW4A1" + ], + [ + "CLK_FEED_SW4A2", + "VBRK_SW4A2" + ], + [ + "CLK_FEED_NW4END0", + "VBRK_NW4END0" + ], + [ + "CLK_FEED_WW2END3", + "VBRK_WW2END3" + ], + [ + "CLK_FEED_WW4C1", + "VBRK_WW4C1" + ], + [ + "CLK_FEED_SW2A0", + "VBRK_SW2A0" + ], + [ + "CLK_FEED_SW4A0", + "VBRK_SW4A0" + ], + [ + "CLK_FEED_NE4BEG3", + "VBRK_NE4BEG3" + ], + [ + "CLK_FEED_ER1BEG0", + "VBRK_ER1BEG0" + ], + [ + "CLK_FEED_EE2BEG2", + "VBRK_EE2BEG2" + ], + [ + "CLK_FEED_WW4B3", + "VBRK_WW4B3" + ], + [ + "CLK_FEED_WW2A3", + "VBRK_WW2A3" + ], + [ + "CLK_FEED_WW4C2", + "VBRK_WW4C2" + ], + [ + "CLK_FEED_LH8", + "VBRK_LH8" + ], + [ + "CLK_FEED_NE4C0", + "VBRK_NE4C0" + ], + [ + "CLK_FEED_EL1BEG3", + "VBRK_EL1BEG3" + ], + [ + "CLK_FEED_LH1", + "VBRK_LH1" + ], + [ + "CLK_FEED_EL1BEG0", + "VBRK_EL1BEG0" + ], + [ + "CLK_FEED_EE4A1", + "VBRK_EE4A1" + ], + [ + "CLK_FEED_SW2A2", + "VBRK_SW2A2" + ], + [ + "CLK_FEED_SE4C3", + "VBRK_SE4C3" + ], + [ + "CLK_FEED_EE4BEG0", + "VBRK_EE4BEG0" + ], + [ + "CLK_FEED_LH4", + "VBRK_LH4" + ], + [ + "CLK_FEED_NW4A2", + "VBRK_NW4A2" + ], + [ + "CLK_FEED_EE2BEG3", + "VBRK_EE2BEG3" + ], + [ + "CLK_FEED_SE4BEG0", + "VBRK_SE4BEG0" + ], + [ + "CLK_FEED_SE4BEG3", + "VBRK_SE4BEG3" + ], + [ + "CLK_FEED_WW4END0", + "VBRK_WW4END0" + ], + [ + "CLK_FEED_EE4B3", + "VBRK_EE4B3" + ], + [ + "CLK_FEED_WL1END0", + "VBRK_WL1END0" + ], + [ + "CLK_FEED_SW4A3", + "VBRK_SW4A3" + ], + [ + "CLK_FEED_WW2A1", + "VBRK_WW2A1" + ], + [ + "CLK_FEED_NE4C1", + "VBRK_NE4C1" + ], + [ + "CLK_FEED_WW2END2", + "VBRK_WW2END2" + ], + [ + "CLK_FEED_EE2A0", + "VBRK_EE2A0" + ], + [ + "CLK_FEED_SE4C2", + "VBRK_SE4C2" + ], + [ + "CLK_FEED_SW4END1", + "VBRK_SW4END1" + ], + [ + "CLK_FEED_EE4BEG2", + "VBRK_EE4BEG2" + ], + [ + "CLK_FEED_WL1END2", + "VBRK_WL1END2" + ], + [ + "CLK_FEED_EL1BEG2", + "VBRK_EL1BEG2" + ], + [ + "CLK_FEED_EE4BEG1", + "VBRK_EE4BEG1" + ], + [ + "CLK_FEED_WR1END3", + "VBRK_WR1END3" + ], + [ + "CLK_FEED_EE4C2", + "VBRK_EE4C2" + ], + [ + "CLK_FEED_NW4A3", + "VBRK_NW4A3" + ], + [ + "CLK_FEED_SW4END0", + "VBRK_SW4END0" + ], + [ + "CLK_FEED_WR1END0", + "VBRK_WR1END0" + ], + [ + "CLK_FEED_SE2A1", + "VBRK_SE2A1" + ], + [ + "CLK_FEED_WW4END3", + "VBRK_WW4END3" + ], + [ + "CLK_FEED_NW2A3", + "VBRK_NW2A3" + ], + [ + "CLK_FEED_WR1END2", + "VBRK_WR1END2" + ], + [ + "CLK_FEED_NW4END1", + "VBRK_NW4END1" + ], + [ + "CLK_FEED_LH11", + "VBRK_LH11" + ], + [ + "CLK_FEED_WW4B0", + "VBRK_WW4B0" + ], + [ + "CLK_FEED_NW4A0", + "VBRK_NW4A0" + ], + [ + "CLK_FEED_NW2A1", + "VBRK_NW2A1" + ], + [ + "CLK_FEED_EE4A0", + "VBRK_EE4A0" + ], + [ + "CLK_FEED_NE4C3", + "VBRK_NE4C3" + ], + [ + "CLK_FEED_EE2A1", + "VBRK_EE2A1" + ], + [ + "CLK_FEED_LH6", + "VBRK_LH6" + ], + [ + "CLK_FEED_LH7", + "VBRK_LH7" + ], + [ + "CLK_FEED_WW4B2", + "VBRK_WW4B2" + ], + [ + "CLK_FEED_SW4END2", + "VBRK_SW4END2" + ], + [ + "CLK_FEED_WW4B1", + "VBRK_WW4B1" + ], + [ + "CLK_FEED_NW4END2", + "VBRK_NW4END2" + ], + [ + "CLK_FEED_WL1END1", + "VBRK_WL1END1" + ], + [ + "CLK_FEED_SW4A1", + "VBRK_SW4A1" + ], + [ + "CLK_FEED_NE2A0", + "VBRK_NE2A0" + ], + [ + "CLK_FEED_NW2A2", + "VBRK_NW2A2" + ], + [ + "CLK_FEED_WW2A0", + "VBRK_WW2A0" + ], + [ + "CLK_FEED_EE2A3", + "VBRK_EE2A3" + ], + [ + "CLK_FEED_WW2A2", + "VBRK_WW2A2" + ], + [ + "CLK_FEED_LH2", + "VBRK_LH2" + ], + [ + "CLK_FEED_EE4C3", + "VBRK_EE4C3" + ], + [ + "CLK_FEED_WW4END1", + "VBRK_WW4END1" + ], + [ + "CLK_FEED_NE4BEG0", + "VBRK_NE4BEG0" + ], + [ + "CLK_FEED_NW4END3", + "VBRK_NW4END3" + ], + [ + "CLK_FEED_SW2A3", + "VBRK_SW2A3" + ], + [ + "CLK_FEED_EE2A2", + "VBRK_EE2A2" + ], + [ + "CLK_FEED_EE4B2", + "VBRK_EE4B2" + ], + [ + "CLK_FEED_WW4A2", + "VBRK_WW4A2" + ], + [ + "CLK_FEED_ER1BEG2", + "VBRK_ER1BEG2" + ], + [ + "CLK_FEED_EE4BEG3", + "VBRK_EE4BEG3" + ], + [ + "CLK_FEED_EE4C0", + "VBRK_EE4C0" + ], + [ + "CLK_FEED_NE4BEG2", + "VBRK_NE4BEG2" + ], + [ + "CLK_FEED_SW4END3", + "VBRK_SW4END3" + ], + [ + "CLK_FEED_WW4A0", + "VBRK_WW4A0" + ], + [ + "CLK_FEED_NE4BEG1", + "VBRK_NE4BEG1" + ], + [ + "CLK_FEED_SE2A0", + "VBRK_SE2A0" + ], + [ + "CLK_FEED_EE2BEG1", + "VBRK_EE2BEG1" + ], + [ + "CLK_FEED_ER1BEG3", + "VBRK_ER1BEG3" + ], + [ + "CLK_FEED_LH3", + "VBRK_LH3" + ], + [ + "CLK_FEED_ER1BEG1", + "VBRK_ER1BEG1" + ], + [ + "CLK_FEED_EL1BEG1", + "VBRK_EL1BEG1" + ], + [ + "CLK_FEED_SE4C0", + "VBRK_SE4C0" + ], + [ + "CLK_FEED_SE4BEG1", + "VBRK_SE4BEG1" + ], + [ + "CLK_FEED_SE2A2", + "VBRK_SE2A2" + ], + [ + "CLK_FEED_EE4A3", + "VBRK_EE4A3" + ], + [ + "CLK_FEED_SE2A3", + "VBRK_SE2A3" + ], + [ + "CLK_FEED_WW4C0", + "VBRK_WW4C0" + ], + [ + "CLK_FEED_SE4BEG2", + "VBRK_SE4BEG2" + ], + [ + "CLK_FEED_NE2A3", + "VBRK_NE2A3" + ] + ], + "tile_types": [ + "CLK_PMV2_SVT", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -8 + ], + "wire_pairs": [ + [ + "PLL_CLK_FREQ_BB_BUFOUT_NS0", + "TERM_CMT_FREQ_REF_NS0" + ], + [ + "PLL_CLK_FREQ_BB_BUFOUT_NS1", + "TERM_CMT_FREQ_REF_NS1" + ], + [ + "PLL_CLK_FREQ_BB_BUFOUT_NS2", + "TERM_CMT_FREQ_REF_NS2" + ], + [ + "PLL_CLK_FREQ_BB_BUFOUT_NS3", + "TERM_CMT_FREQ_REF_NS3" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "TERM_CMT" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "CMT_TOP_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH1_2", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH2_2", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_LH6_2", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_LH7_2", + "VBRK_LH7" + ], + [ + "CMT_TOP_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH12_2", + "VBRK_LH12" + ], + [ + "CMT_TOP_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_LH11_2", + "VBRK_LH11" + ], + [ + "CMT_TOP_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4B3_2", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_MONITOR_P_2", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH4_2", + "VBRK_LH4" + ], + [ + "CMT_TOP_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_LH5_2", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH3_2", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_MONITOR_N_2", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH10_2", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH8_2", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_LH9_2", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW2A2_2", + "VBRK_NW2A2" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -4 + ], + "wire_pairs": [ + [ + "CLK_BUFG_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_BUFG_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_BUFG_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_BUFG_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_BUFG_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_BUFG_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_BUFG_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_BUFG_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_BUFG_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_BUFG_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_BUFG_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_BUFG_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_BUFG_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_BUFG_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_BUFG_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_BUFG_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_BUFG_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_BUFG_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_BUFG_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_BUFG_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_BUFG_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_BUFG_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_BUFG_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_BUFG_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_BUFG_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_BUFG_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_BUFG_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_BUFG_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_BUFG_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_BUFG_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_BUFG_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_BUFG_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED9", + "CLK_FEED_R_CK_BUFG_CASC9" + ] + ], + "tile_types": [ + "CLK_BUFG_TOP_R", + "CLK_FEED" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ] + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_R_BOT_UTURN" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLK_HROW_FAN1_0", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_WW4A2_0", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_BUFG_IMUX10_0", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_BUFG_IMUX38_0", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_EE2BEG2_0", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_SE4BEG2_0", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_BUFG_IMUX5_0", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_BYP5_0", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_NW2A2_0", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_FAN3_0", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_EE4A2_0", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_ER1BEG3_0", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_WR1END0_0", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_BUFG_IMUX3_0", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_BUFG_IMUX2_0", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_BUFG_IMUX46_0", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_BUFG_IMUX9_0", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_WW2A0_0", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4BEG2_0", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_CLK1_0", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_SW4A2_0", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_LH2_0", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_WW4A3_0", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_BUFG_IMUX14_0", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_NE2A0_0", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_EE4BEG1_0", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_SW2A2_0", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B3_0", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CLK_HROW_BYP4_0", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B0_0", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CLK_HROW_EE4B3_0", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_EE2BEG0_0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_SE4C2_0", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_BYP7_0", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_SW4END0_0", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_EE4A0_0", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_SE4C3_0", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_BUFG_IMUX25_0", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_BYP2_0", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_SE4BEG1_0", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_SW4A0_0", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_EE2BEG1_0", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_BYP6_0", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_BUFG_IMUX30_0", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B1_0", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CLK_HROW_FAN4_0", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_WL1END1_0", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_BUFG_IMUX39_0", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_WW2END3_0", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_EL1BEG3_0", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_EE2BEG3_0", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_WW4END3_0", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_BYP3_0", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_NE4BEG3_0", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_BUFG_IMUX17_0", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_EE2A0_0", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_SE4BEG0_0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_BUFG_IMUX31_0", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_WW4C2_0", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_BUFG_IMUX26_0", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_LH5_0", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_EL1BEG2_0", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_BUFG_IMUX1_0", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_NW2A3_0", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_NE4C1_0", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_EE4C1_0", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_BUFG_IMUX18_0", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_WW4END2_0", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_EE4BEG3_0", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_NE2A3_0", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_NW4END1_0", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_BUFG_IMUX12_0", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_SW4END1_0", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_WW2A1_0", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_SW4END2_0", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_EE4C3_0", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_BUFG_IMUX45_0", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_NW4END0_0", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_SW2A0_0", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_SW4A1_0", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_BUFG_IMUX33_0", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_WW2A2_0", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B4_0", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CLK_HROW_NE4C2_0", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_BUFG_IMUX43_0", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_NW4A1_0", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_BUFG_IMUX19_0", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_BUFG_IMUX21_0", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_WW4END0_0", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_WW4C0_0", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_BUFG_IMUX20_0", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_WW4A1_0", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_LH6_0", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_SW4END3_0", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_BUFG_IMUX32_0", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_SE4C0_0", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_BUFG_IMUX13_0", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_SE2A3_0", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_EE4A3_0", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_BUFG_IMUX24_0", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_EE4B0_0", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_WW2A3_0", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_BUFG_IMUX15_0", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_WW4A0_0", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_EE4A1_0", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_ER1BEG2_0", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_BUFG_IMUX28_0", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_BUFG_IMUX7_0", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_WW4C1_0", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_WL1END3_0", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_BUFG_IMUX23_0", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_LH11_0", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_LH12_0", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_EE4BEG0_0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_NW4A0_0", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_BUFG_IMUX6_0", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_WW4B1_0", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_WL1END2_0", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_BUFG_IMUX47_0", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_EL1BEG0_0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_EE2A3_0", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_LH3_0", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_NE4BEG1_0", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_SE4C1_0", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_BUFG_IMUX42_0", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_BYP1_0", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_WW2END0_0", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_BUFG_IMUX27_0", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_NE4BEG2_0", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_NE4C3_0", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_SW2A1_0", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_BUFG_IMUX11_0", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B2_0", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CLK_BUFG_IMUX8_0", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_WL1END0_0", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_NW4END3_0", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_CTRL0_0", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_CTRL1_0", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_WR1END2_0", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_BUFG_IMUX4_0", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_WW4C3_0", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_EE2A2_0", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_LH9_0", + "INT_INTERFACE_LH9" + ], + [ + "CLK_BUFG_IMUX36_0", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_EL1BEG1_0", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_BUFG_IMUX41_0", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_BYP0_0", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_WR1END1_0", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_ER1BEG0_0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_FAN6_0", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_WW4END1_0", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_NE2A1_0", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_NW2A0_0", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_WW2END1_0", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_LH4_0", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_ER1BEG1_0", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_SE4BEG3_0", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_FAN7_0", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_FAN0_0", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_NE4C0_0", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_EE2A1_0", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_WW4B2_0", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_LH1_0", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_WW2END2_0", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_WW4B3_0", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_FAN2_0", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_BUFG_IMUX0_0", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_SE2A2_0", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_LH10_0", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_NW2A1_0", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_NE2A2_0", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B7_0", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CLK_HROW_EE4B2_0", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_FAN5_0", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_NE4BEG0_0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_BUFG_IMUX22_0", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_SW2A3_0", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_SE2A0_0", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_SW4A3_0", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_NW4A2_0", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_EE4B1_0", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_LH7_0", + "INT_INTERFACE_LH7" + ], + [ + "CLK_BUFG_IMUX44_0", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B5_0", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CLK_BUFG_IMUX35_0", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_BUFG_IMUX37_0", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_NW4A3_0", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WR1END3_0", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_CLK0_0", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_NW4END2_0", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_WW4B0_0", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_LH8_0", + "INT_INTERFACE_LH8" + ], + [ + "CLK_BUFG_IMUX16_0", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_SE2A1_0", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_EE4C2_0", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_BUFG_IMUX34_0", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_BUFG_IMUX40_0", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_BUFG_IMUX29_0", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B6_0", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CLK_HROW_EE4C0_0", + "INT_INTERFACE_EE4C0" + ] + ], + "tile_types": [ + "CLK_BUFG_BOT_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -8 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SE4BEG2_18", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_WR1END0_18", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_IMUX37_18", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_IMUX38_18", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_BYP1_18", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SE4BEG0_18", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_SW4A3_18", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_WW2A2_18", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_SE4C3_18", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX30_18", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_EE4B1_18", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_SE2A0_18", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_WW2A3_18", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_EE4BEG0_18", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_NW4A2_18", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_EE2A1_18", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_WW4END1_18", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_EL1BEG0_18", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_NE2A3_18", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_WW2A0_18", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_EE2A3_18", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NW2A3_18", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NW4END3_18", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_FAN7_18", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX15_18", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_SW4END1_18", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_SW4A0_18", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_NW2A1_18", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_EE2BEG3_18", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_BYP0_18", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_EE4A3_18", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_NW2A2_18", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_IMUX1_18", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_ER1BEG0_18", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_LH8_18", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_NE2A0_18", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_SW4A1_18", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_EE2A0_18", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_IMUX18_18", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_SE4BEG1_18", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_IMUX34_18", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_ER1BEG1_18", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_CLK1_18", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX41_18", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_WL1END3_18", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_FAN5_18", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SW2A1_18", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_CLK0_18", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_NE4BEG2_18", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG1_18", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_WW4C0_18", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_WW2A1_18", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_LH10_18", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_BYP4_18", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_NW4A3_18", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_IMUX6_18", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX33_18", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_NE4BEG3_18", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_FAN2_18", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_EE2A2_18", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_WL1END1_18", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_LH12_18", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_WW4B3_18", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_IMUX27_18", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_BYP5_18", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_LH11_18", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_WL1END0_18", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_LH1_18", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_EE4BEG2_18", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE4A2_18", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_WW2END0_18", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WL1END2_18", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_IMUX12_18", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_SE4BEG3_18", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX14_18", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_SW2A0_18", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_BYP6_18", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_WW4C1_18", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_FAN3_18", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_BYP7_18", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_LH2_18", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX21_18", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_IMUX23_18", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_CTRL0_18", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_EE2BEG2_18", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX36_18", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_IMUX39_18", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_NW4END1_18", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SW4A2_18", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_IMUX2_18", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_IMUX43_18", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_WW4END2_18", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX25_18", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_EE4B2_18", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_LH5_18", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX0_18", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_ER1BEG2_18", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_ER1BEG3_18", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_IMUX4_18", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_WW4B0_18", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_FAN0_18", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_WW4B2_18", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_FAN6_18", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_WW2END1_18", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_WW4C3_18", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NE2A2_18", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_SW4END2_18", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_IMUX20_18", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_IMUX17_18", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_WW4C2_18", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_LH9_18", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_IMUX5_18", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WW4A2_18", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_EE4B0_18", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_SW2A3_18", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_LH6_18", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_LH7_18", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_WW2END3_18", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_IMUX47_18", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX42_18", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_BYP2_18", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_WW4END3_18", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX28_18", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_WW4A1_18", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_NE2A1_18", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_NE4BEG0_18", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX44_18", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WR1END3_18", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_EE4A0_18", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_WR1END1_18", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_EE2BEG0_18", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_WR1END2_18", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SE4C2_18", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_IMUX40_18", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_IMUX31_18", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_NW2A0_18", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_IMUX19_18", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_LH4_18", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_IMUX29_18", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX22_18", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX11_18", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_NW4A1_18", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SE4C0_18", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_EE4A1_18", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_SW4END0_18", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_WW2END2_18", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_WW4END0_18", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_WW4A0_18", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_FAN1_18", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_BYP3_18", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_IMUX9_18", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX32_18", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_SE4C1_18", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX13_18", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_CTRL1_18", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_NE4C2_18", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_EE4BEG1_18", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_IMUX24_18", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_NE4BEG1_18", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX46_18", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_EE4C0_18", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_NW4END0_18", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX35_18", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_SW4END3_18", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX45_18", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_NE4C0_18", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE4C2_18", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_EE4C1_18", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_EE4BEG3_18", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG2_18", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_SE2A1_18", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_IMUX7_18", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_LH3_18", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX16_18", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX8_18", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_NW4END2_18", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_SW2A2_18", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_SE2A2_18", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_EE2BEG1_18", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX26_18", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_EL1BEG3_18", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_IMUX3_18", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_NE4C1_18", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_EE4C3_18", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE4B3_18", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_NW4A0_18", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX10_18", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SE2A3_18", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_NE4C3_18", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_WW4A3_18", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_FAN4_18", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW4B1_18", + "VFRAME_WW4B1" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B21_3", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_LOGIC_OUTS_B9_3", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX40_3", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B10_3", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_CTRL0_3", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_BYP0_3", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_BYP3_3", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_BYP5_3", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX2_3", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_FAN2_3", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_FAN1_3", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B8_3", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_LOGIC_OUTS_B13_3", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_CTRL1_3", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX47_3", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_LOGIC_OUTS_B0_3", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX9_3", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX32_3", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX25_3", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX39_3", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX4_3", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX6_3", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX14_3", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX36_3", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX43_3", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX46_3", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_FAN5_3", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX16_3", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX31_3", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B2_3", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_LOGIC_OUTS_B4_3", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B3_3", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX29_3", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_FAN4_3", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX3_3", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX5_3", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B23_3", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX45_3", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX41_3", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX12_3", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX42_3", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_FAN7_3", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B20_3", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX23_3", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_LOGIC_OUTS_B11_3", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_IMUX30_3", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX33_3", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX10_3", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX27_3", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX7_3", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX37_3", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX38_3", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX26_3", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_CLK1_3", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX17_3", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX21_3", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_LOGIC_OUTS_B6_3", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX18_3", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_FAN6_3", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_LOGIC_OUTS_B22_3", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B12_3", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX35_3", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_LOGIC_OUTS_B18_3", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX44_3", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX34_3", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX15_3", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX13_3", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP6_3", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX0_3", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX22_3", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX20_3", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_LOGIC_OUTS_B14_3", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_CLK0_3", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX24_3", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B7_3", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_FAN3_3", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX1_3", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_LOGIC_OUTS_B16_3", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B17_3", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B5_3", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_BYP1_3", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX28_3", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_LOGIC_OUTS_B1_3", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_3", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_BYP2_3", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_BYP4_3", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX8_3", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_LOGIC_OUTS_B15_3", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX19_3", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX11_3", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP7_3", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_FAN0_3", + "VBRK_EXT_FAN0" + ] + ], + "tile_types": [ + "GTX_CHANNEL_1", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "CMT_TOP_LH12_7", + "VBRK_LH12" + ], + [ + "CMT_TOP_SW4END1_7", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_7", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE4C2_7", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_ER1BEG3_7", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END1_7", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WL1END2_7", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_NW4A0_7", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WR1END2_7", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW4A2_7", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG3_7", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EL1BEG0_7", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH11_7", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW2END2_7", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4A1_7", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NE2A1_7", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SW2A2_7", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_ER1BEG0_7", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_7", + "VBRK_LH1" + ], + [ + "CMT_TOP_SW4A3_7", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH10_7", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4BEG3_7", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C3_7", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4END3_7", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_ER1BEG1_7", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_7", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW2END0_7", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END2_7", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NE4C0_7", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EL1BEG1_7", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_EE2BEG3_7", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WW4END0_7", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4C1_7", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A2_7", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_7", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE2A3_7", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4A1_7", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_LH2_7", + "VBRK_LH2" + ], + [ + "CMT_TOP_EL1BEG2_7", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WL1END0_7", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4C1_7", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW2END1_7", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2BEG0_7", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4B0_7", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C2_7", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A0_7", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_7", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_EE4B2_7", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG2_7", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A0_7", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG0_7", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW4A1_7", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_SE2A1_7", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4END2_7", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE2A3_7", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW4C0_7", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_7", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE4BEG2_7", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_SE4C0_7", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_ER1BEG2_7", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NE2A0_7", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4A3_7", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4BEG2_7", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_7", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4B3_7", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END3_7", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WW4C1_7", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WL1END3_7", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH9_7", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2A0_7", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG1_7", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_7", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_LH3_7", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_7", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE4BEG1_7", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EE4A2_7", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG0_7", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE4BEG2_7", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW4END3_7", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NE4BEG1_7", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A2_7", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NW4END0_7", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_7", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4A0_7", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END0_7", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_7", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW4END1_7", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE4BEG1_7", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH7_7", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4A3_7", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C2_7", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A3_7", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW2A1_7", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C3_7", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE2A2_7", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NE4C3_7", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE4C0_7", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WR1END1_7", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NW4END3_7", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_WW4B1_7", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C1_7", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_7", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE2A1_7", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_7", + "VBRK_LH5" + ], + [ + "CMT_TOP_SE4C2_7", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B0_7", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE2A0_7", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW4A1_7", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SW2A0_7", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW2A3_7", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW2A0_7", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_7", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EL1BEG3_7", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_NW4A2_7", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG3_7", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NW2A3_7", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW4C3_7", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_7", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_LH4_7", + "VBRK_LH4" + ], + [ + "CMT_TOP_LH8_7", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B3_7", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NE2A2_7", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4BEG0_7", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2A3_7", + "VBRK_EE2A3" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_1" + ], + [ + "INT_INTERFACE_ER1BEG2", + "BRAM_ER1BEG2_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX36", + "BRAM_IMUX36_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "BRAM_LOGIC_OUTS_B19_1" + ], + [ + "INT_INTERFACE_EE4A0", + "BRAM_EE4A0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX29", + "BRAM_IMUX29_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX2", + "BRAM_IMUX2_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX1", + "BRAM_IMUX1_UTURN_1" + ], + [ + "INT_INTERFACE_SW4END0", + "BRAM_SW4END0_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "BRAM_LOGIC_OUTS_B16_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX27", + "BRAM_IMUX27_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "BRAM_LOGIC_OUTS_B15_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX32", + "BRAM_IMUX32_UTURN_1" + ], + [ + "INT_INTERFACE_SW2A2", + "BRAM_SW2A2_1" + ], + [ + "INT_INTERFACE_CLK0", + "BRAM_CLK0_1" + ], + [ + "INT_INTERFACE_FAN6", + "BRAM_FAN6_1" + ], + [ + "INT_INTERFACE_EE4A1", + "BRAM_EE4A1_1" + ], + [ + "INT_INTERFACE_NW4A2", + "BRAM_NW4A2_1" + ], + [ + "INT_INTERFACE_WR1END1", + "BRAM_WR1END1_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX20", + "BRAM_IMUX20_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX21", + "BRAM_IMUX21_UTURN_1" + ], + [ + "INT_INTERFACE_ER1BEG3", + "BRAM_ER1BEG3_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX43", + "BRAM_IMUX43_UTURN_1" + ], + [ + "INT_INTERFACE_LH3", + "BRAM_LH3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX18", + "BRAM_IMUX18_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX31", + "BRAM_IMUX31_1" + ], + [ + "INT_INTERFACE_SE2A0", + "BRAM_SE2A0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX38", + "BRAM_IMUX38_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX36", + "BRAM_IMUX36_1" + ], + [ + "INT_INTERFACE_NW4A1", + "BRAM_NW4A1_1" + ], + [ + "INT_INTERFACE_BYP0", + "BRAM_BYP0_1" + ], + [ + "INT_INTERFACE_BYP1", + "BRAM_BYP1_1" + ], + [ + "INT_INTERFACE_WW4END0", + "BRAM_WW4END0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX33", + "BRAM_IMUX33_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX25", + "BRAM_IMUX25_1" + ], + [ + "INT_INTERFACE_FAN7", + "BRAM_FAN7_1" + ], + [ + "INT_INTERFACE_NE2A2", + "BRAM_NE2A2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "BRAM_LOGIC_OUTS_B5_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "BRAM_LOGIC_OUTS_B22_1" + ], + [ + "INT_INTERFACE_NE2A1", + "BRAM_NE2A1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "BRAM_LOGIC_OUTS_B11_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX16", + "BRAM_IMUX16_UTURN_1" + ], + [ + "INT_INTERFACE_CLK1", + "BRAM_CLK1_1" + ], + [ + "INT_INTERFACE_EE2BEG2", + "BRAM_EE2BEG2_1" + ], + [ + "INT_INTERFACE_EE2A2", + "BRAM_EE2A2_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_1" + ], + [ + "INT_INTERFACE_WW4B1", + "BRAM_WW4B1_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX34", + "BRAM_IMUX34_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX24", + "BRAM_IMUX24_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX24", + "BRAM_IMUX24_1" + ], + [ + "INT_INTERFACE_WW4B0", + "BRAM_WW4B0_1" + ], + [ + "INT_INTERFACE_BYP4", + "BRAM_BYP4_1" + ], + [ + "INT_INTERFACE_SW4A2", + "BRAM_SW4A2_1" + ], + [ + "INT_INTERFACE_EE4C2", + "BRAM_EE4C2_1" + ], + [ + "INT_INTERFACE_EE4BEG2", + "BRAM_EE4BEG2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "BRAM_LOGIC_OUTS_B20_1" + ], + [ + "INT_INTERFACE_LH6", + "BRAM_LH6_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "BRAM_LOGIC_OUTS_B4_1" + ], + [ + "INT_INTERFACE_EE4B2", + "BRAM_EE4B2_1" + ], + [ + "INT_INTERFACE_LH12", + "BRAM_LH12_1" + ], + [ + "INT_INTERFACE_NE4BEG2", + "BRAM_NE4BEG2_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_1" + ], + [ + "INT_INTERFACE_EE4B3", + "BRAM_EE4B3_1" + ], + [ + "INT_INTERFACE_EE4A3", + "BRAM_EE4A3_1" + ], + [ + "INT_INTERFACE_FAN4", + "BRAM_FAN4_1" + ], + [ + "INT_INTERFACE_WW2A2", + "BRAM_WW2A2_1" + ], + [ + "INT_INTERFACE_FAN1", + "BRAM_FAN1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "BRAM_LOGIC_OUTS_B6_1" + ], + [ + "INT_INTERFACE_NW2A0", + "BRAM_NW2A0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX37", + "BRAM_IMUX37_1" + ], + [ + "INT_INTERFACE_WR1END0", + "BRAM_WR1END0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_1" + ], + [ + "INT_INTERFACE_FAN5", + "BRAM_FAN5_1" + ], + [ + "INT_INTERFACE_NE2A3", + "BRAM_NE2A3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX0", + "BRAM_IMUX0_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX26", + "BRAM_IMUX26_1" + ], + [ + "INT_INTERFACE_NE4C3", + "BRAM_NE4C3_1" + ], + [ + "INT_INTERFACE_WW2A1", + "BRAM_WW2A1_1" + ], + [ + "INT_INTERFACE_WR1END3", + "BRAM_WR1END3_1" + ], + [ + "INT_INTERFACE_EE4C3", + "BRAM_EE4C3_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX30", + "BRAM_IMUX30_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "BRAM_LOGIC_OUTS_B10_1" + ], + [ + "INT_INTERFACE_NE4BEG1", + "BRAM_NE4BEG1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "BRAM_LOGIC_OUTS_B8_1" + ], + [ + "INT_INTERFACE_SW2A1", + "BRAM_SW2A1_1" + ], + [ + "INT_INTERFACE_SE4BEG1", + "BRAM_SE4BEG1_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX3", + "BRAM_IMUX3_UTURN_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "BRAM_LOGIC_OUTS_B14_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX43", + "BRAM_IMUX43_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX13", + "BRAM_IMUX13_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX35", + "BRAM_IMUX35_1" + ], + [ + "INT_INTERFACE_BYP5", + "BRAM_BYP5_1" + ], + [ + "INT_INTERFACE_LH7", + "BRAM_LH7_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX22", + "BRAM_IMUX22_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX5", + "BRAM_IMUX5_UTURN_1" + ], + [ + "INT_INTERFACE_LH9", + "BRAM_LH9_1" + ], + [ + "INT_INTERFACE_WW2END1", + "BRAM_WW2END1_1" + ], + [ + "INT_INTERFACE_SE2A1", + "BRAM_SE2A1_1" + ], + [ + "INT_INTERFACE_EL1BEG3", + "BRAM_EL1BEG3_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX21", + "BRAM_IMUX21_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "BRAM_LOGIC_OUTS_B21_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "BRAM_LOGIC_OUTS_B3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX40", + "BRAM_IMUX40_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX9", + "BRAM_IMUX9_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX4", + "BRAM_IMUX4_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX35", + "BRAM_IMUX35_UTURN_1" + ], + [ + "INT_INTERFACE_SW4A1", + "BRAM_SW4A1_1" + ], + [ + "INT_INTERFACE_LH1", + "BRAM_LH1_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "BRAM_LOGIC_OUTS_B17_1" + ], + [ + "INT_INTERFACE_EE2A3", + "BRAM_EE2A3_1" + ], + [ + "INT_INTERFACE_WL1END1", + "BRAM_WL1END1_1" + ], + [ + "INT_INTERFACE_SE2A2", + "BRAM_SE2A2_1" + ], + [ + "INT_INTERFACE_FAN0", + "BRAM_FAN0_1" + ], + [ + "INT_INTERFACE_SE2A3", + "BRAM_SE2A3_1" + ], + [ + "INT_INTERFACE_NW2A2", + "BRAM_NW2A2_1" + ], + [ + "INT_INTERFACE_NW2A3", + "BRAM_NW2A3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX31", + "BRAM_IMUX31_UTURN_1" + ], + [ + "INT_INTERFACE_WW4C0", + "BRAM_WW4C0_1" + ], + [ + "INT_INTERFACE_EL1BEG1", + "BRAM_EL1BEG1_1" + ], + [ + "INT_INTERFACE_NE4BEG3", + "BRAM_NE4BEG3_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_1" + ], + [ + "INT_INTERFACE_SE4C2", + "BRAM_SE4C2_1" + ], + [ + "INT_INTERFACE_EL1BEG2", + "BRAM_EL1BEG2_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX45", + "BRAM_IMUX45_UTURN_1" + ], + [ + "INT_INTERFACE_NW2A1", + "BRAM_NW2A1_1" + ], + [ + "INT_INTERFACE_EE2A0", + "BRAM_EE2A0_1" + ], + [ + "INT_INTERFACE_CTRL0", + "BRAM_CTRL0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_1" + ], + [ + "INT_INTERFACE_WL1END3", + "BRAM_WL1END3_1" + ], + [ + "INT_INTERFACE_WW2A0", + "BRAM_WW2A0_1" + ], + [ + "INT_INTERFACE_EE4B0", + "BRAM_EE4B0_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX7", + "BRAM_IMUX7_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX41", + "BRAM_IMUX41_1" + ], + [ + "INT_INTERFACE_WW2END3", + "BRAM_WW2END3_1" + ], + [ + "INT_INTERFACE_WW4C1", + "BRAM_WW4C1_1" + ], + [ + "INT_INTERFACE_SE4BEG3", + "BRAM_SE4BEG3_1" + ], + [ + "INT_INTERFACE_EE4BEG0", + "BRAM_EE4BEG0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_1" + ], + [ + "INT_INTERFACE_WW4A1", + "BRAM_WW4A1_1" + ], + [ + "INT_INTERFACE_WW4END1", + "BRAM_WW4END1_1" + ], + [ + "INT_INTERFACE_SW2A3", + "BRAM_SW2A3_1" + ], + [ + "INT_INTERFACE_SW4END1", + "BRAM_SW4END1_1" + ], + [ + "INT_INTERFACE_WW4A3", + "BRAM_WW4A3_1" + ], + [ + "INT_INTERFACE_NE4C0", + "BRAM_NE4C0_1" + ], + [ + "INT_INTERFACE_EE4C1", + "BRAM_EE4C1_1" + ], + [ + "INT_INTERFACE_WW2A3", + "BRAM_WW2A3_1" + ], + [ + "INT_INTERFACE_EE4B1", + "BRAM_EE4B1_1" + ], + [ + "INT_INTERFACE_WW4END3", + "BRAM_WW4END3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX33", + "BRAM_IMUX33_UTURN_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "BRAM_LOGIC_OUTS_B23_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX39", + "BRAM_IMUX39_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX44", + "BRAM_IMUX44_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX10", + "BRAM_IMUX10_UTURN_1" + ], + [ + "INT_INTERFACE_EE2A1", + "BRAM_EE2A1_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_1" + ], + [ + "INT_INTERFACE_NW4A0", + "BRAM_NW4A0_1" + ], + [ + "INT_INTERFACE_BYP6", + "BRAM_BYP6_1" + ], + [ + "INT_INTERFACE_SE4BEG2", + "BRAM_SE4BEG2_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX34", + "BRAM_IMUX34_1" + ], + [ + "INT_INTERFACE_EE4BEG3", + "BRAM_EE4BEG3_1" + ], + [ + "INT_INTERFACE_WW4B3", + "BRAM_WW4B3_1" + ], + [ + "INT_INTERFACE_SE4BEG0", + "BRAM_SE4BEG0_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX23", + "BRAM_IMUX23_UTURN_1" + ], + [ + "INT_INTERFACE_NE4C1", + "BRAM_NE4C1_1" + ], + [ + "INT_INTERFACE_WR1END2", + "BRAM_WR1END2_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX42", + "BRAM_IMUX42_1" + ], + [ + "INT_INTERFACE_SW2A0", + "BRAM_SW2A0_1" + ], + [ + "INT_INTERFACE_LH8", + "BRAM_LH8_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "BRAM_LOGIC_OUTS_B13_1" + ], + [ + "INT_INTERFACE_EE4C0", + "BRAM_EE4C0_1" + ], + [ + "INT_INTERFACE_LH5", + "BRAM_LH5_1" + ], + [ + "INT_INTERFACE_SW4END3", + "BRAM_SW4END3_1" + ], + [ + "INT_INTERFACE_ER1BEG1", + "BRAM_ER1BEG1_1" + ], + [ + "INT_INTERFACE_SW4A3", + "BRAM_SW4A3_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "BRAM_LOGIC_OUTS_B2_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX14", + "BRAM_IMUX14_UTURN_1" + ], + [ + "INT_INTERFACE_BYP7", + "BRAM_BYP7_1" + ], + [ + "INT_INTERFACE_NW4END0", + "BRAM_NW4END0_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "BRAM_LOGIC_OUTS_B0_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX19", + "BRAM_IMUX19_UTURN_1" + ], + [ + "INT_INTERFACE_WW4C3", + "BRAM_WW4C3_1" + ], + [ + "INT_INTERFACE_NE2A0", + "BRAM_NE2A0_1" + ], + [ + "INT_INTERFACE_NW4A3", + "BRAM_NW4A3_1" + ], + [ + "INT_INTERFACE_SE4C1", + "BRAM_SE4C1_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX46", + "BRAM_IMUX46_1" + ], + [ + "INT_INTERFACE_EE4BEG1", + "BRAM_EE4BEG1_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX29", + "BRAM_IMUX29_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX23", + "BRAM_IMUX23_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX15", + "BRAM_IMUX15_UTURN_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "BRAM_LOGIC_OUTS_B7_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX26", + "BRAM_IMUX26_UTURN_1" + ], + [ + "INT_INTERFACE_LH4", + "BRAM_LH4_1" + ], + [ + "INT_INTERFACE_WW2END0", + "BRAM_WW2END0_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX8", + "BRAM_IMUX8_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX44", + "BRAM_IMUX44_UTURN_1" + ], + [ + "INT_INTERFACE_LH11", + "BRAM_LH11_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "BRAM_LOGIC_OUTS_B12_1" + ], + [ + "INT_INTERFACE_EE2BEG0", + "BRAM_EE2BEG0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_1" + ], + [ + "INT_INTERFACE_FAN3", + "BRAM_FAN3_1" + ], + [ + "INT_INTERFACE_EE2BEG1", + "BRAM_EE2BEG1_1" + ], + [ + "INT_INTERFACE_WW4B2", + "BRAM_WW4B2_1" + ], + [ + "INT_INTERFACE_MONITOR_N", + "BRAM_MONITOR_N_1" + ], + [ + "INT_INTERFACE_NE4BEG0", + "BRAM_NE4BEG0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX47", + "BRAM_IMUX47_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX47", + "BRAM_IMUX47_UTURN_1" + ], + [ + "INT_INTERFACE_BYP3", + "BRAM_BYP3_1" + ], + [ + "INT_INTERFACE_NW4END3", + "BRAM_NW4END3_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX41", + "BRAM_IMUX41_UTURN_1" + ], + [ + "INT_INTERFACE_EE4A2", + "BRAM_EE4A2_1" + ], + [ + "INT_INTERFACE_FAN2", + "BRAM_FAN2_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX28", + "BRAM_IMUX28_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX11", + "BRAM_IMUX11_UTURN_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "BRAM_LOGIC_OUTS_B18_1" + ], + [ + "INT_INTERFACE_WL1END0", + "BRAM_WL1END0_1" + ], + [ + "INT_INTERFACE_LH10", + "BRAM_LH10_1" + ], + [ + "INT_INTERFACE_SW4A0", + "BRAM_SW4A0_1" + ], + [ + "INT_INTERFACE_NW4END2", + "BRAM_NW4END2_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX46", + "BRAM_IMUX46_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX28", + "BRAM_IMUX28_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX42", + "BRAM_IMUX42_UTURN_1" + ], + [ + "INT_INTERFACE_EE2BEG3", + "BRAM_EE2BEG3_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX25", + "BRAM_IMUX25_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX27", + "BRAM_IMUX27_UTURN_1" + ], + [ + "INT_INTERFACE_ER1BEG0", + "BRAM_ER1BEG0_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX30", + "BRAM_IMUX30_UTURN_1" + ], + [ + "INT_INTERFACE_EL1BEG0", + "BRAM_EL1BEG0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX22", + "BRAM_IMUX22_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "BRAM_LOGIC_OUTS_B9_1" + ], + [ + "INT_INTERFACE_NW4END1", + "BRAM_NW4END1_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX39", + "BRAM_IMUX39_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX12", + "BRAM_IMUX12_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX40", + "BRAM_IMUX40_1" + ], + [ + "INT_INTERFACE_BYP2", + "BRAM_BYP2_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX37", + "BRAM_IMUX37_UTURN_1" + ], + [ + "INT_INTERFACE_WW4C2", + "BRAM_WW4C2_1" + ], + [ + "INT_INTERFACE_NE4C2", + "BRAM_NE4C2_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX6", + "BRAM_IMUX6_UTURN_1" + ], + [ + "INT_INTERFACE_WL1END2", + "BRAM_WL1END2_1" + ], + [ + "INT_INTERFACE_CTRL1", + "BRAM_CTRL1_1" + ], + [ + "INT_INTERFACE_SE4C0", + "BRAM_SE4C0_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_1" + ], + [ + "INT_INTERFACE_WW4A2", + "BRAM_WW4A2_1" + ], + [ + "INT_INTERFACE_WW2END2", + "BRAM_WW2END2_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX17", + "BRAM_IMUX17_UTURN_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX45", + "BRAM_IMUX45_1" + ], + [ + "INT_INTERFACE_SE4C3", + "BRAM_SE4C3_1" + ], + [ + "INT_INTERFACE_LH2", + "BRAM_LH2_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX32", + "BRAM_IMUX32_1" + ], + [ + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_1" + ], + [ + "INT_INTERFACE_SW4END2", + "BRAM_SW4END2_1" + ], + [ + "INT_INTERFACE_WW4A0", + "BRAM_WW4A0_1" + ], + [ + "INT_INTERFACE_WW4END2", + "BRAM_WW4END2_1" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX38", + "BRAM_IMUX38_UTURN_1" + ], + [ + "INT_INTERFACE_MONITOR_P", + "BRAM_MONITOR_P_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "BRAM_LOGIC_OUTS_B1_1" + ] + ], + "tile_types": [ + "BRAM_INT_INTERFACE_L", + "BRAM_L" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH3_4", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH4_4", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH12_4", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH11_4", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH9_4", + "VBRK_LH9" + ], + [ + "CMT_TOP_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH1_4", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_MONITOR_N_4", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_LH10_4", + "VBRK_LH10" + ], + [ + "CMT_TOP_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH2_4", + "VBRK_LH2" + ], + [ + "CMT_TOP_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_MONITOR_P_4", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_LH8_4", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH7_4", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_4", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH6_4", + "VBRK_LH6" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "CMT_TOP_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH6_3", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_LH1_3", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_LH12_3", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_LH7_3", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_3", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH3_3", + "VBRK_LH3" + ], + [ + "CMT_TOP_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_LH2_3", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH9_3", + "VBRK_LH9" + ], + [ + "CMT_TOP_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH5_3", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH11_3", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_LH10_3", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH8_3", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EL1BEG1_3", + "VBRK_EL1BEG1" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 4 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH3_4", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH4_4", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH12_4", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH11_4", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH9_4", + "VBRK_LH9" + ], + [ + "CMT_TOP_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH1_4", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_LH10_4", + "VBRK_LH10" + ], + [ + "CMT_TOP_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH2_4", + "VBRK_LH2" + ], + [ + "CMT_TOP_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_LH8_4", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH7_4", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_4", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH6_4", + "VBRK_LH6" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 8 + ], + "wire_pairs": [ + [ + "PCIE_WR1END0_2", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_2", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_SW4A3_2", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_NW4END0_2", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_WW4A0_2", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_2", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_2", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_2", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_EE2BEG0_2", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_NE4BEG1_2", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_2", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_IMUX5_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_IMUX21_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_NE4C0_2", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_2", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_SW4END0_2", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_2", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_WW4C2_2", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_LH7_2", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_WW4END2_2", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_IMUX37_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_2", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_ER1BEG3_2", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_LH9_2", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_WW4C3_2", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_NE4BEG0_2", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_BYP5_R_2", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_EE2A3_2", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_CTRL1_R_2", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_NE2A1_2", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_WL1END3_2", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_EE4A0_2", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_SW2A1_2", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_ER1BEG0_2", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_NW2A1_2", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_IMUX23_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_IMUX0_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_NE2A0_2", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_WW2A0_2", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_IMUX8_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_WW4A1_2", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_EE4B2_2", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_EE2BEG3_2", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_NE4BEG2_2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_WL1END1_2", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_IMUX39_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_IMUX17_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_2", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_SW2A0_2", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_WW2A1_2", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_LH11_2", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_SW2A2_2", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_BYP0_R_2", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_EE2BEG1_2", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_WR1END3_2", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_WR1END1_2", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_2", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_2", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_EE4BEG1_2", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_FAN2_R_2", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_IMUX7_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_IMUX34_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_2", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_SE4BEG1_2", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_EE4BEG3_2", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_IMUX26_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_FAN7_R_2", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_IMUX30_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_WW2END2_2", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_LH3_2", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_IMUX2_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_WW2A2_2", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_NW4END3_2", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_IMUX6_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_LH8_2", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_ER1BEG2_2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_NW4END2_2", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_NW2A2_2", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_2", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_2", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_LH6_2", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_EL1BEG3_2", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_LH2_2", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_LH4_2", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_EE4A1_2", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_IMUX16_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_SW4END2_2", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_EE4A3_2", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_2", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_EL1BEG1_2", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_FAN5_R_2", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_WR1END2_2", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_2", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_BYP1_R_2", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_BYP3_R_2", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_IMUX28_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_SE4C2_2", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_IMUX33_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_LH10_2", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_IMUX32_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_SE4BEG0_2", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_LH1_2", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_SW4END1_2", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_WW4C1_2", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_NE2A2_2", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_IMUX15_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_LH5_2", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_SW4A2_2", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_NE4C1_2", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_FAN1_R_2", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_EE4B0_2", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX47_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_CTRL0_R_2", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_2", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_SE2A2_2", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_EE4B3_2", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_BYP4_R_2", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_SE4BEG3_2", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_FAN6_R_2", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_IMUX19_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_ER1BEG1_2", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_WW4A3_2", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_LH12_2", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_WW4B0_2", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_WW4A2_2", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_IMUX40_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_WW2END1_2", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_2", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_IMUX24_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_WW4END1_2", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_SE4C0_2", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_IMUX13_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_IMUX31_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_EE4A2_2", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_EE2A2_2", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_WW2END0_2", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_IMUX12_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_IMUX27_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_IMUX20_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_EE4C3_2", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_CLK0_R_2", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_WL1END0_2", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_2", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_IMUX1_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_SW4END3_2", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_SE2A3_2", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_IMUX4_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_BYP2_R_2", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_EE2A1_2", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_IMUX36_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_SE2A0_2", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_WW4END3_2", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_EL1BEG0_2", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_IMUX35_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_WW2A3_2", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_EE4C2_2", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_NW4END1_2", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_2", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_2", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_IMUX42_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_WW2END3_2", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_BYP7_R_2", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_IMUX38_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_WW4END0_2", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_EE2A0_2", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_EE4BEG0_2", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_EE4BEG2_2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_NW2A3_2", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_WW4B2_2", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_IMUX10_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_WW4B1_2", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_IMUX25_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_EL1BEG2_2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_IMUX3_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_EE2BEG2_2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_IMUX43_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_SW4A1_2", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_NE4C2_2", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_WL1END2_2", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_IMUX41_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_NW4A0_2", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_NE4BEG3_2", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_2", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_IMUX14_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_IMUX45_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_2", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_SE4C1_2", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_EE4C0_2", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX22_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_NW2A0_2", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_FAN4_R_2", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_WW4B3_2", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_CLK1_R_2", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_IMUX46_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_EE4C1_2", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_SE4C3_2", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_FAN3_R_2", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX11_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_NW4A3_2", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_NW4A2_2", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_2", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_IMUX9_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_IMUX18_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_SW4A0_2", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_NW4A1_2", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_IMUX44_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_WW4C0_2", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_SW2A3_2", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_NE4C3_2", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_SE2A1_2", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_FAN0_R_2", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_SE4BEG2_2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_NE2A3_2", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_EE4B1_2", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_IMUX29_R_2", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_BYP6_R_2", + "INT_INTERFACE_BYP6" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4C0_12", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EE4A0_12", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE2BEG2_12", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_LH12_12", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_EE4BEG0_12", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WW4A2_12", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WW2A1_12", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_EE4C2_12", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW4A1_12", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WW4A0_12", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE2BEG0_12", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW2A2_12", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_EE2A2_12", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WW4END0_12", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_SW2A1_12", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4B0_12", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WL1END2_12", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WL1END1_12", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_SW4END1_12", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EL1BEG3_12", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WW4END3_12", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_EE2A1_12", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_EE2BEG1_12", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_SW4A0_12", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_ER1BEG1_12", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SW4END3_12", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_SE2A1_12", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_NE4C2_12", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW4B1_12", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW4C2_12", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_WR1END0_12", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_EE4C3_12", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_ER1BEG3_12", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_EE4C1_12", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_WW4C0_12", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_EE2A0_12", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW2END2_12", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_EE4BEG1_12", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG0_12", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_LH1_12", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_NE2A0_12", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_LH10_12", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WW2END0_12", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WR1END3_12", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_NE4BEG1_12", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_SE4C1_12", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_SE4C3_12", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_SE2A3_12", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_EE4BEG2_12", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WW4C3_12", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_SW2A3_12", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NE4C3_12", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WW2END1_12", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_SE4C2_12", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_ER1BEG2_12", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_NW4END1_12", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NW4A2_12", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NE2A2_12", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_SE2A2_12", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_SW2A2_12", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_EE4B2_12", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EL1BEG1_12", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SE4BEG3_12", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_WW4C1_12", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_WR1END1_12", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WW4END1_12", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE4A3_12", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_WR1END2_12", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_WW4B0_12", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_WW4A3_12", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NE2A3_12", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_LH7_12", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_NE4BEG2_12", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_LH5_12", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_NW2A3_12", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_EL1BEG0_12", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE4B3_12", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NW4END0_12", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SW4A3_12", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_NW4END3_12", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW2END3_12", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_EE4A2_12", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SE4BEG2_12", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_NW4A3_12", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_SE4C0_12", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_WL1END3_12", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4A1_12", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_SW2A0_12", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_SW4END2_12", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WW4END2_12", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_LH4_12", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SW4A2_12", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_EE4B1_12", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_SW4END0_12", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_NW4A0_12", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SE4BEG1_12", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SW4A1_12", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_ER1BEG0_12", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_LH6_12", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_LH9_12", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_WW4B3_12", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_LH2_12", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NE4BEG3_12", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_NE4C0_12", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_WW4A1_12", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_LH8_12", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_NW2A0_12", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WL1END0_12", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SE2A0_12", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_NE4BEG0_12", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NE2A1_12", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_EE2BEG3_12", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_EE4BEG3_12", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_NW2A2_12", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_WW2A3_12", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_LH11_12", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EE2A3_12", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_EL1BEG2_12", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_WW4B2_12", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_NW2A1_12", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_NW4END2_12", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW2A0_12", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_NE4C1_12", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_LH3_12", + "INT_FEEDTHRU_2_LH3" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + 8 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW4END1_2", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE4B0_2", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WW2END0_2", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_LH2_2", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_EE4A1_2", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EE2BEG2_2", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW4A0_2", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SW4A1_2", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_WW4B2_2", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_SE2A3_2", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SE4BEG3_2", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EE4C1_2", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_WR1END2_2", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_WW4END2_2", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_NE2A0_2", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EE4BEG1_2", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_WR1END1_2", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WW4C0_2", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_LH4_2", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_NW4END3_2", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW4C3_2", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4A2_2", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE2A3_2", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW4A1_2", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EE2BEG3_2", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NW4END0_2", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SW2A2_2", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WW4END0_2", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EE4B1_2", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NE2A3_2", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_LH12_2", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_LH7_2", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_LH3_2", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_NW4A0_2", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SW2A0_2", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WR1END3_2", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE4BEG0_2", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WW4B1_2", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW4A3_2", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NW2A2_2", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_LH10_2", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_LH1_2", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_WW4C2_2", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NW2A3_2", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE4C3_2", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_ER1BEG2_2", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_NW4END1_2", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_LH11_2", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW4B3_2", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_NE4C1_2", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE4C0_2", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_EE4BEG2_2", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_NE2A2_2", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_NW4END2_2", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WL1END2_2", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WW2A3_2", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WW2END2_2", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_NE4BEG2_2", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG0_2", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_SE4BEG0_2", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SE2A0_2", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SW2A3_2", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_EL1BEG2_2", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_LH9_2", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_SE4C1_2", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_WW2A1_2", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_SE4BEG1_2", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SE2A2_2", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4C2_2", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_ER1BEG0_2", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_SW4A2_2", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_SE4C3_2", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_EE2BEG1_2", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_WW4B0_2", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_NE2A1_2", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_SE2A1_2", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_EE4C0_2", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WW2END1_2", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_WW4C1_2", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_NW4A1_2", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SW4END3_2", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NW4A2_2", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WW2A0_2", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_SW4A0_2", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE2A2_2", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_EE4B2_2", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_SW4END2_2", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_NE4BEG1_2", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_EE4BEG3_2", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WL1END0_2", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SW4END0_2", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EE2BEG0_2", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_SE4C2_2", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_NW2A0_2", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_EE2A1_2", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_WL1END1_2", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_ER1BEG1_2", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WL1END3_2", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4A0_2", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4A3_2", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_WW2END3_2", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_SW4END1_2", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_LH6_2", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_LH8_2", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_EL1BEG1_2", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NW4A3_2", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_NE4BEG3_2", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_EE4B3_2", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_ER1BEG3_2", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_NW2A1_2", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C3_2", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW2A2_2", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WR1END0_2", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_EL1BEG3_2", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_EE2A0_2", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_LH5_2", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_SW4A3_2", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_WW4END3_2", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_NE4BEG0_2", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_SE4C0_2", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_SW2A1_2", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_NE4C2_2", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE4A2_2", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SE4BEG2_2", + "INT_FEEDTHRU_2_SE4BEG2" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "DSP_LH2_1", + "VBRK_LH2" + ], + [ + "DSP_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "DSP_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "DSP_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "DSP_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "DSP_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "DSP_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "DSP_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "DSP_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "DSP_LH9_1", + "VBRK_LH9" + ], + [ + "DSP_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "DSP_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "DSP_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "DSP_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "DSP_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "DSP_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "DSP_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "DSP_LH3_1", + "VBRK_LH3" + ], + [ + "DSP_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "DSP_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "DSP_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "DSP_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "DSP_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "DSP_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "DSP_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "DSP_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "DSP_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "DSP_LH8_1", + "VBRK_LH8" + ], + [ + "DSP_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "DSP_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "DSP_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "DSP_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "DSP_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "DSP_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "DSP_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "DSP_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "DSP_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "DSP_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "DSP_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "DSP_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "DSP_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "DSP_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "DSP_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "DSP_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "DSP_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "DSP_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "DSP_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "DSP_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "DSP_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "DSP_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "DSP_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "DSP_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "DSP_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "DSP_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "DSP_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "DSP_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "DSP_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "DSP_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "DSP_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "DSP_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "DSP_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "DSP_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "DSP_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "DSP_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "DSP_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "DSP_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "DSP_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "DSP_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "DSP_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "DSP_LH12_1", + "VBRK_LH12" + ], + [ + "DSP_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "DSP_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "DSP_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "DSP_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "DSP_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "DSP_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "DSP_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "DSP_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "DSP_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "DSP_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "DSP_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "DSP_MONITOR_N_1", + "VBRK_MONITOR_N" + ], + [ + "DSP_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "DSP_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "DSP_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "DSP_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "DSP_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "DSP_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "DSP_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "DSP_LH11_1", + "VBRK_LH11" + ], + [ + "DSP_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "DSP_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "DSP_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "DSP_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "DSP_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "DSP_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "DSP_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "DSP_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "DSP_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "DSP_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "DSP_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "DSP_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "DSP_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "DSP_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "DSP_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "DSP_LH7_1", + "VBRK_LH7" + ], + [ + "DSP_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "DSP_LH6_1", + "VBRK_LH6" + ], + [ + "DSP_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "DSP_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "DSP_LH4_1", + "VBRK_LH4" + ], + [ + "DSP_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "DSP_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "DSP_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "DSP_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "DSP_MONITOR_P_1", + "VBRK_MONITOR_P" + ], + [ + "DSP_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "DSP_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "DSP_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "DSP_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "DSP_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "DSP_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "DSP_LH5_1", + "VBRK_LH5" + ], + [ + "DSP_LH10_1", + "VBRK_LH10" + ], + [ + "DSP_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "DSP_LH1_1", + "VBRK_LH1" + ] + ], + "tile_types": [ + "DSP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4C2_0", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX20_0", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_WW4B3_0", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_WW4C0_0", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_EE4BEG3_0", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_WL1END1_0", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_LH4_0", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_SW4END0_0", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX23_0", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW2END0_0", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_SW2A2_0", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_WW2A2_0", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_WL1END0_0", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_IMUX11_0", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX0_0", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_FAN6_0", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX5_0", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_NW4END3_0", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_SE2A2_0", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_WW4A2_0", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_FAN4_0", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_LH7_0", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_NE4BEG1_0", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_FAN5_0", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SW4A3_0", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_IMUX24_0", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_NE2A1_0", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_SE4BEG3_0", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_WW4A3_0", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW4END1_0", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX32_0", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_BYP2_0", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_WW4C3_0", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_EE4A1_0", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_SW4A1_0", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_IMUX2_0", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_WW4C1_0", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_BYP0_0", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX44_0", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_SW4A2_0", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NE4BEG2_0", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_IMUX18_0", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_CTRL0_0", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_SE2A0_0", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_SW4END2_0", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_ER1BEG2_0", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_ER1BEG1_0", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_NE4C3_0", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_LH9_0", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_IMUX9_0", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX25_0", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_IMUX41_0", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_EL1BEG2_0", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NW2A1_0", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_IMUX14_0", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_NW4END2_0", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_IMUX4_0", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_WW2END1_0", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_CLK0_0", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX28_0", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX21_0", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_NW2A3_0", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NE4BEG0_0", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX7_0", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_IMUX17_0", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX10_0", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SW2A3_0", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_ER1BEG3_0", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_SE4BEG2_0", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_IMUX39_0", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_NW4END0_0", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_EL1BEG1_0", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_EE2BEG0_0", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_WW4B1_0", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_EE4BEG1_0", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_IMUX36_0", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_WW4END3_0", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_EL1BEG0_0", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_IMUX8_0", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_BYP7_0", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_CLK1_0", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_WW2A3_0", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX27_0", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX46_0", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_EE2A1_0", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_SE4C2_0", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_EE2BEG1_0", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_SW4END3_0", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_EE4B1_0", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_WW4B2_0", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_LH12_0", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_WW4A0_0", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_WL1END3_0", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_NW2A2_0", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_SW4A0_0", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_FAN0_0", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX29_0", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_NW4A3_0", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_FAN3_0", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_WW4C2_0", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_NW4A1_0", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_FAN1_0", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX42_0", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_LH5_0", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX31_0", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_WR1END1_0", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_LH6_0", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_SW2A0_0", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_SW4END1_0", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_EE4A3_0", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX38_0", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_WR1END2_0", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_EE2A2_0", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_WW4B0_0", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_EE2A3_0", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NE2A2_0", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WR1END0_0", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_FAN2_0", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_IMUX22_0", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX1_0", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_LH3_0", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_NE4BEG3_0", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX13_0", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_NW2A0_0", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_LH1_0", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NW4A0_0", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX19_0", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_LH2_0", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EE2BEG3_0", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX12_0", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_EE4C1_0", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX45_0", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_BYP6_0", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_SE4C0_0", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_WW2A0_0", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_IMUX47_0", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_WW4END2_0", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_EE4B2_0", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX6_0", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_WW4A1_0", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_SE4C3_0", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX34_0", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_BYP5_0", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_SE2A1_0", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_EE4C0_0", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_EE4B0_0", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WW2A1_0", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_WL1END2_0", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_FAN7_0", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_EE4B3_0", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_IMUX15_0", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_WR1END3_0", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_SE4BEG0_0", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_ER1BEG0_0", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_NE4C0_0", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EL1BEG3_0", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_NW4A2_0", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_NE4C1_0", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_NE4C2_0", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_EE2A0_0", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_SE4C1_0", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_LH11_0", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_BYP1_0", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SE4BEG1_0", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE4BEG2_0", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX33_0", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_IMUX40_0", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_LH10_0", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_SE2A3_0", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_IMUX26_0", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_LH8_0", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_SW2A1_0", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WW2END3_0", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_NE2A0_0", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX3_0", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_BYP3_0", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_EE4A2_0", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_EE2BEG2_0", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX30_0", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_IMUX37_0", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_NW4END1_0", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_IMUX16_0", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX43_0", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_WW4END0_0", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX35_0", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_BYP4_0", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WW2END2_0", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_EE4A0_0", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_EE4C3_0", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_NE2A3_0", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_CTRL1_0", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_EE4BEG0_0", + "VFRAME_EE4BEG0" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "CMT_TOP_LH12_7", + "VBRK_LH12" + ], + [ + "CMT_TOP_SW4END1_7", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_7", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE4C2_7", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_ER1BEG3_7", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END1_7", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WL1END2_7", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_NW4A0_7", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WR1END2_7", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW4A2_7", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG3_7", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EL1BEG0_7", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH11_7", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW2END2_7", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4A1_7", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NE2A1_7", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SW2A2_7", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_ER1BEG0_7", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_7", + "VBRK_LH1" + ], + [ + "CMT_TOP_SW4A3_7", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH10_7", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4BEG3_7", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C3_7", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4END3_7", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_ER1BEG1_7", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_7", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW2END0_7", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END2_7", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NE4C0_7", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EL1BEG1_7", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_EE2BEG3_7", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WW4END0_7", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4C1_7", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A2_7", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_7", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE2A3_7", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4A1_7", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_LH2_7", + "VBRK_LH2" + ], + [ + "CMT_TOP_EL1BEG2_7", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WL1END0_7", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4C1_7", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW2END1_7", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2BEG0_7", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4B0_7", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4C2_7", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A0_7", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4B1_7", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_MONITOR_P_7", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_EE4B2_7", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG2_7", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A0_7", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG0_7", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW4A1_7", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_SE2A1_7", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4END2_7", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE2A3_7", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WW4C0_7", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_7", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE4BEG2_7", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_SE4C0_7", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_ER1BEG2_7", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NE2A0_7", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4A3_7", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE4BEG2_7", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_7", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4B3_7", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END3_7", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WW4C1_7", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WL1END3_7", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH9_7", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE2A0_7", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG1_7", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_7", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_LH3_7", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_7", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE4BEG1_7", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EE4A2_7", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE4BEG0_7", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE4BEG2_7", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW4END3_7", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NE4BEG1_7", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A2_7", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NW4END0_7", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_LH6_7", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4A0_7", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END0_7", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WR1END3_7", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW4END1_7", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE4BEG1_7", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH7_7", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4A3_7", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C2_7", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A3_7", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW2A1_7", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C3_7", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE2A2_7", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NE4C3_7", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE4C0_7", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WR1END1_7", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A2_7", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_NW4END3_7", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_WW4B1_7", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C1_7", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_7", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE2A1_7", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_7", + "VBRK_LH5" + ], + [ + "CMT_TOP_SE4C2_7", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B0_7", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE2A0_7", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW4A1_7", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SW2A0_7", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW2A3_7", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW2A0_7", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_7", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EL1BEG3_7", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_NW4A2_7", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG3_7", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NW2A3_7", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW4C3_7", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_7", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_LH4_7", + "VBRK_LH4" + ], + [ + "CMT_TOP_LH8_7", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B3_7", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_MONITOR_N_7", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_EE4BEG0_7", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2A3_7", + "VBRK_EE2A3" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "CFG_CENTER_NE4BEG0_3", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_NE4C0_3", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_BYP5_3", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_IMUX25_3", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_NW2A1_3", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_SW2A3_3", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_CTRL1_3", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_SW2A0_3", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_SW4END0_3", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_WW4B3_3", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_SE4C3_3", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_NE4BEG1_3", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX46_3", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_EL1BEG2_3", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NE2A0_3", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_WL1END2_3", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_NW4A1_3", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SW4END2_3", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_NW2A3_3", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_EE4C0_3", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_WW4C0_3", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_NW2A0_3", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_NE4C2_3", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_WR1END2_3", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SW2A1_3", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WW2A2_3", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_IMUX9_3", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_EE4A1_3", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX4_3", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_EE4B1_3", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_EL1BEG0_3", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_FAN1_3", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX14_3", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_WW4END3_3", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_EE4C3_3", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_SW2A2_3", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_BYP4_3", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_EE2BEG0_3", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX3_3", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_BYP0_3", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_LH3_3", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX33_3", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_IMUX40_3", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_EE2BEG2_3", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_CLK1_3", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX41_3", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_NW4END2_3", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_EE4B0_3", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_NW4END1_3", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_IMUX28_3", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_SE4BEG0_3", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_IMUX30_3", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_LH12_3", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_SW4END3_3", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX2_3", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_SE2A0_3", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_EE2BEG3_3", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_WR1END3_3", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_3", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_EE4A3_3", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_LH2_3", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX12_3", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_FAN3_3", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_FAN2_3", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_IMUX45_3", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_LH10_3", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW2END1_3", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_3", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_IMUX7_3", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_IMUX39_3", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_SE4C2_3", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_EE4B3_3", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_NE2A2_3", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE4A2_3", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX31_3", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_CLK0_3", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX32_3", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_LH11_3", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_3", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_SE2A1_3", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_EE4C2_3", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX6_3", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX42_3", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_WR1END1_3", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_IMUX18_3", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_WW4A2_3", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_NE2A3_3", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX17_3", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_3", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_LH8_3", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_WW4B2_3", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_NW4A3_3", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SW4A3_3", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_IMUX8_3", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_IMUX19_3", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_FAN4_3", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW2END3_3", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_EE2A1_3", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_EE4BEG0_3", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_EE4BEG1_3", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_EL1BEG1_3", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_BYP7_3", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_EE4A0_3", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_NE4C3_3", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_3", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_WW4B0_3", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_WL1END0_3", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_WR1END0_3", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_NW4END0_3", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_WL1END3_3", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_IMUX35_3", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_ER1BEG2_3", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX11_3", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_WL1END1_3", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_BYP3_3", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_LH9_3", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_IMUX16_3", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_SE4C1_3", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_FAN7_3", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_3", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_IMUX23_3", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NW4A2_3", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_SE4C0_3", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_LH5_3", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX47_3", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX37_3", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_IMUX10_3", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SW4A0_3", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_FAN5_3", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_WW4C3_3", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX22_3", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW4C2_3", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX1_3", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX13_3", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_WW4A1_3", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_NE4C1_3", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_LH1_3", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NE2A1_3", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_SE4BEG1_3", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_FAN6_3", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_CTRL0_3", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_EE2A0_3", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WW2A0_3", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_SE4BEG2_3", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE2A3_3", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_WW2A1_3", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_SE4BEG3_3", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX5_3", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WW4END2_3", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_FAN0_3", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX0_3", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_ER1BEG3_3", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_LH4_3", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_LH6_3", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX29_3", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_ER1BEG1_3", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SW4END1_3", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_SE2A2_3", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_BYP2_3", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_NW4A0_3", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NE4BEG2_3", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_NE4BEG3_3", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_WW4A0_3", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX21_3", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_LH7_3", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_IMUX44_3", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_EL1BEG3_3", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW2END2_3", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_EE4BEG2_3", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE2BEG1_3", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX43_3", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_WW4END1_3", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_EE4C1_3", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX15_3", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_IMUX24_3", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_SE2A3_3", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SW4A1_3", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_EE2A2_3", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_EE4B2_3", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_BYP1_3", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW4B1_3", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_IMUX38_3", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_NW4END3_3", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_3", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_EE4BEG3_3", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_WW4END0_3", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_ER1BEG0_3", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_IMUX36_3", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_WW2END0_3", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WW4C1_3", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_IMUX34_3", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_WW4A3_3", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_NW2A2_3", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW2A3_3", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX27_3", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_3", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_BYP6_3", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX26_3", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX20_3", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SW4A2_3", + "VFRAME_SW4A2" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLBLL_L_CIN", + "CLBLL_L_COUT_N" + ], + [ + "CLBLL_LL_CIN", + "CLBLL_LL_COUT_N" + ] + ], + "tile_types": [ + "CLBLL_L", + "CLBLL_L" + ] + }, + { + "grid_deltas": [ + 0, + -2 + ], + "wire_pairs": [ + [ + "IOI_RCLK_DIV_CE3_1", + "IOI_RCLK_DIV_CE3" + ], + [ + "IOI_RCLK_DIV_CE2_1", + "IOI_RCLK_DIV_CE2" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_LEAF_GCLK1" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_LEAF_GCLK0" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_LEAF_GCLK3" + ], + [ + "IOI_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1_1" + ], + [ + "IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_RCLK_FORIO0" + ], + [ + "IOI_TBYTEIN", + "IOI_TBYTEIN" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_LEAF_GCLK5" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_RCLK_FORIO3" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_RCLK_FORIO1" + ], + [ + "IOI_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0_1" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_RCLK_FORIO2" + ], + [ + "IOI_IMUX_RC2", + "IOI_IMUX_RC0" + ], + [ + "IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "IOI_IMUX_RC3", + "IOI_IMUX_RC1" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_LEAF_GCLK4" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_LEAF_GCLK2" + ] + ], + "tile_types": [ + "RIOI", + "RIOI_TBYTESRC" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "CMT_FIFO_EE2BEG1_11", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_NW4A3_11", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_EE4B2_11", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_EE4BEG3_11", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX42_11", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_IMUX18_11", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_NE4BEG3_11", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_NE4BEG0_11", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_SE4BEG1_11", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX16_11", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_L_IMUX1_11", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_WL1END1_11", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_EE4B3_11", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_11", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_11", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "CMT_FIFO_SE2A0_11", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_EE4C1_11", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_NE4BEG2_11", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_WW4C3_11", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_L_IMUX0_11", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_L_IMUX17_11", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_11", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "CMT_FIFO_L_IMUX34_11", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_WR1END2_11", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_L_IMUX7_11", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_SW4A1_11", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_11", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "CMT_FIFO_EE2BEG2_11", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_EE4C3_11", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_L_BYP6_11", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_WL1END2_11", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_EE4BEG2_11", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_WW4B2_11", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_EE2BEG3_11", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_L_IMUX44_11", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_CTRL0_11", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_SW4A2_11", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_EE4BEG1_11", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_LH10_11", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_LH5_11", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_WL1END3_11", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_SW2A1_11", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_L_BYP4_11", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_WW4B3_11", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_L_IMUX35_11", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_EE4BEG0_11", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_WW4C1_11", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_L_FAN6_11", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_EE2A1_11", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_WW4B1_11", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_EL1BEG2_11", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_11", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CMT_FIFO_L_BYP0_11", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_SE2A2_11", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_NW2A1_11", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_EE4B1_11", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_WW2END2_11", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_ER1BEG2_11", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_IMUX46_11", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_SW4A3_11", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_EE4C0_11", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_LH4_11", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_L_IMUX9_11", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX23_11", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_LH9_11", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_11", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "CMT_FIFO_LH11_11", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_NW2A0_11", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_WW2A3_11", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_11", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CMT_FIFO_NE2A2_11", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_L_IMUX28_11", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_WW2A2_11", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_L_IMUX24_11", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_NW4A1_11", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_WW4C0_11", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_NE2A0_11", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_IMUX26_11", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_IMUX22_11", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_WW2END3_11", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_LH2_11", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_EE4A1_11", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_L_IMUX43_11", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_EE2BEG0_11", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_NW4END2_11", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_EE4A0_11", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_SE4C2_11", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_L_CTRL1_11", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_NE4C2_11", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_L_FAN2_11", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_WW4B0_11", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_LH6_11", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_EE2A2_11", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_EL1BEG0_11", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_L_IMUX37_11", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_SE4BEG2_11", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX21_11", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_L_BYP5_11", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_SW4A0_11", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_NW4END3_11", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_L_IMUX4_11", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_L_IMUX2_11", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_WW4A3_11", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_EE2A0_11", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_FAN1_11", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_L_IMUX29_11", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_WW4A0_11", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_SE2A3_11", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_L_IMUX14_11", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_L_CLK0_11", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_WW2END1_11", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_L_IMUX12_11", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_WW4C2_11", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_SW4END2_11", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_LH8_11", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_11", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "CMT_FIFO_L_IMUX5_11", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_L_BYP2_11", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_L_IMUX38_11", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_WW4END1_11", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_WW4A1_11", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_NE2A1_11", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_WW2A1_11", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_L_IMUX10_11", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_SE4C0_11", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_L_FAN0_11", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_SW4END0_11", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_NE4C1_11", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_11", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CMT_FIFO_NW4A0_11", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_L_IMUX11_11", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_NW4END1_11", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_L_IMUX45_11", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_L_IMUX30_11", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_L_FAN4_11", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_L_FAN7_11", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_ER1BEG3_11", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_11", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CMT_FIFO_L_CLK1_11", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_L_FAN3_11", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_L_IMUX13_11", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_EL1BEG1_11", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_L_IMUX3_11", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_L_IMUX8_11", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_IMUX33_11", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_WL1END0_11", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_11", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CMT_FIFO_WW4END2_11", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_11", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CMT_FIFO_L_BYP7_11", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_11", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "CMT_FIFO_EL1BEG3_11", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_11", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "CMT_FIFO_L_IMUX47_11", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_SW2A3_11", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_ER1BEG0_11", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_NE4C0_11", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_ER1BEG1_11", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_SE4BEG3_11", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_L_FAN5_11", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_SW2A0_11", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_WW2A0_11", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_L_BYP3_11", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_WW4A2_11", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_EE4C2_11", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_WW4END3_11", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_NW4A2_11", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_WR1END3_11", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_NW2A3_11", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_LH12_11", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_SW2A2_11", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_EE4A3_11", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_IMUX40_11", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_NW4END0_11", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_L_IMUX41_11", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_LH7_11", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_L_IMUX15_11", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_SE4C1_11", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_WR1END0_11", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_NE2A3_11", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_NW2A2_11", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_L_IMUX25_11", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_WW2END0_11", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_SW4END3_11", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_L_IMUX31_11", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_EE4B0_11", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_LH1_11", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_SE4C3_11", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_SE4BEG0_11", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_NE4C3_11", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_WW4END0_11", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_IMUX32_11", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_L_IMUX19_11", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_L_IMUX39_11", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_L_IMUX36_11", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_NE4BEG1_11", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_11", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_11", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "CMT_FIFO_EE4A2_11", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_IMUX27_11", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_WR1END1_11", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_L_BYP1_11", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_11", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_11", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_11", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CMT_FIFO_SW4END1_11", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_SE2A1_11", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_L_IMUX6_11", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_EE2A3_11", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_L_IMUX20_11", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_LH3_11", + "INT_INTERFACE_LH3" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 7 + ], + "wire_pairs": [ + [ + "CFG_CENTER_NE4BEG0_3", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_NE4C0_3", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_BYP5_3", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_IMUX25_3", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_NW2A1_3", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_SW2A3_3", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_CTRL1_3", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_SW2A0_3", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_SW4END0_3", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_WW4B3_3", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_SE4C3_3", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_NE4BEG1_3", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX46_3", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_EL1BEG2_3", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NE2A0_3", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_WL1END2_3", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_NW4A1_3", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SW4END2_3", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_NW2A3_3", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_EE4C0_3", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_WW4C0_3", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_NW2A0_3", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_NE4C2_3", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_WR1END2_3", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SW2A1_3", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WW2A2_3", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_IMUX9_3", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_EE4A1_3", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX4_3", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_EE4B1_3", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_EL1BEG0_3", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_FAN1_3", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX14_3", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_WW4END3_3", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_EE4C3_3", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_SW2A2_3", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_BYP4_3", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_EE2BEG0_3", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX3_3", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_BYP0_3", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_LH3_3", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX33_3", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_IMUX40_3", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_EE2BEG2_3", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_CLK1_3", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX41_3", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_NW4END2_3", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_EE4B0_3", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_NW4END1_3", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_IMUX28_3", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_SE4BEG0_3", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_IMUX30_3", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_LH12_3", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_SW4END3_3", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX2_3", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_SE2A0_3", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_EE2BEG3_3", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_WR1END3_3", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_EE4A3_3", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_LH2_3", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX12_3", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_FAN3_3", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_FAN2_3", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_IMUX45_3", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_LH10_3", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW2END1_3", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_IMUX7_3", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_IMUX39_3", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_SE4C2_3", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_EE4B3_3", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_NE2A2_3", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE4A2_3", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX31_3", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_CLK0_3", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX32_3", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_LH11_3", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_SE2A1_3", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_EE4C2_3", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX6_3", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX42_3", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_WR1END1_3", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_IMUX18_3", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_WW4A2_3", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_NE2A3_3", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX17_3", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_LH8_3", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_WW4B2_3", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_NW4A3_3", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SW4A3_3", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_IMUX8_3", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_IMUX19_3", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_FAN4_3", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW2END3_3", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_EE2A1_3", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_EE4BEG0_3", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_EE4BEG1_3", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_EL1BEG1_3", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_BYP7_3", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_EE4A0_3", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_NE4C3_3", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_WW4B0_3", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_WL1END0_3", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_WR1END0_3", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_NW4END0_3", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_WL1END3_3", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_IMUX35_3", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_ER1BEG2_3", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX11_3", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_WL1END1_3", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_BYP3_3", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_LH9_3", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_IMUX16_3", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_SE4C1_3", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_FAN7_3", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX23_3", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NW4A2_3", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_SE4C0_3", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_LH5_3", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX47_3", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX37_3", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_IMUX10_3", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SW4A0_3", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_FAN5_3", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_WW4C3_3", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX22_3", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW4C2_3", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX1_3", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX13_3", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_WW4A1_3", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_NE4C1_3", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_LH1_3", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NE2A1_3", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_SE4BEG1_3", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_FAN6_3", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_CTRL0_3", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_EE2A0_3", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WW2A0_3", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_SE4BEG2_3", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE2A3_3", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_WW2A1_3", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_SE4BEG3_3", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX5_3", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WW4END2_3", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_FAN0_3", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX0_3", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_ER1BEG3_3", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_LH4_3", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_LH6_3", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX29_3", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_ER1BEG1_3", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SW4END1_3", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_SE2A2_3", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_BYP2_3", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_NW4A0_3", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NE4BEG2_3", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_NE4BEG3_3", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_WW4A0_3", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX21_3", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_LH7_3", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_IMUX44_3", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_EL1BEG3_3", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW2END2_3", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_EE4BEG2_3", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE2BEG1_3", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX43_3", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_WW4END1_3", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_EE4C1_3", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX15_3", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_IMUX24_3", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_SE2A3_3", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SW4A1_3", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_EE2A2_3", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_EE4B2_3", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_BYP1_3", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW4B1_3", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_IMUX38_3", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_NW4END3_3", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_EE4BEG3_3", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_WW4END0_3", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_ER1BEG0_3", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_IMUX36_3", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_WW2END0_3", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WW4C1_3", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_IMUX34_3", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_WW4A3_3", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_NW2A2_3", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW2A3_3", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX27_3", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_BYP6_3", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX26_3", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX20_3", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SW4A2_3", + "VFRAME_SW4A2" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "LIOB_IN_TERM0", + "LIOI_DCI_T_TERM0" + ], + [ + "IOB_PD_INT_EN_0", + "LIOI_PD_INT_EN_0" + ], + [ + "IOB_KEEPER_INT_EN_0", + "LIOI_KEEPER_INT_EN_0" + ], + [ + "IOB_O0", + "LIOI_O0" + ], + [ + "IOB_IBUF0", + "LIOI_IBUF0" + ], + [ + "IOB_KEEPER_INT_EN_1", + "LIOI_KEEPER_INT_EN_1" + ], + [ + "IOB_PU_INT_EN_1", + "LIOI_PU_INT_EN_1" + ], + [ + "IOB_T1", + "LIOI_T1" + ], + [ + "LIOB_IN_TERM1", + "LIOI_DCI_T_TERM1" + ], + [ + "IOB_PU_INT_EN_0", + "LIOI_PU_INT_EN_0" + ], + [ + "LIOB_MONITOR_P", + "IOI_MONITOR_P" + ], + [ + "IOB_PD_INT_EN_1", + "LIOI_PD_INT_EN_1" + ], + [ + "IOB_O1", + "LIOI_O1" + ], + [ + "IOB_T0", + "LIOI_T0" + ], + [ + "IOB_IBUF1", + "LIOI_IBUF1" + ], + [ + "IOB_IBUF_DISABLE1", + "LIOI_IBUF_DISABLE1" + ], + [ + "IOB_IBUF_DISABLE0", + "LIOI_IBUF_DISABLE0" + ], + [ + "LIOB_MONITOR_N", + "IOI_MONITOR_N" + ], + [ + "IOB_DIFF_TERM_INT_EN", + "LIOI_DIFF_TERM_INT_EN" + ] + ], + "tile_types": [ + "LIOB33", + "LIOI3_TBYTETERM" + ] + }, + { + "grid_deltas": [ + 1, + -5 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4A1_15", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_WL1END0_15", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_WW2A3_15", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX32_15", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_IMUX7_15", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_LH6_15", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX16_15", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WW4END2_15", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_WR1END3_15", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX38_15", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_WR1END2_15", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_EE4B3_15", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_LH5_15", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX6_15", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_WL1END2_15", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_BYP2_15", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_IMUX35_15", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_WW4A1_15", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_IMUX36_15", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW4END3_15", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_CTRL0_15", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_SE4BEG3_15", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_WW4C3_15", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NE2A0_15", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_NE4BEG3_15", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_SE2A0_15", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_EE4B0_15", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_NE4BEG1_15", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_FAN0_15", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_WR1END1_15", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_EE2A1_15", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX27_15", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_WW2A2_15", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_IMUX12_15", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX45_15", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_WW4END0_15", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_EL1BEG2_15", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NE4C0_15", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_SE4C2_15", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_SW4A3_15", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_SW4END0_15", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_FAN2_15", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_BYP1_15", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_IMUX31_15", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_IMUX1_15", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_WW2END3_15", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WL1END1_15", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_WW2A1_15", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_NW4END2_15", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_NE4BEG0_15", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX24_15", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_WW4B0_15", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_WL1END3_15", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_SW2A3_15", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_SE4BEG1_15", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE4A0_15", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_SE4BEG2_15", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_SE4C3_15", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX0_15", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_IMUX18_15", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_LH7_15", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_FAN5_15", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_WW4B2_15", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_IMUX43_15", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_NE2A1_15", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX15_15", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_BYP6_15", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_EE4BEG0_15", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_NW4END3_15", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_SW2A0_15", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_IMUX14_15", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_WW4A3_15", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_IMUX3_15", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_EE4BEG3_15", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX25_15", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_NE4C1_15", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_WW4A0_15", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_NW2A0_15", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_SE4C0_15", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_EE2BEG1_15", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_EE4A2_15", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_NW4END1_15", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_LH10_15", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_NW4A3_15", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_IMUX8_15", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_SW2A1_15", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WW4END1_15", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX41_15", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_EE2BEG3_15", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_ER1BEG3_15", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_WW4B1_15", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_IMUX30_15", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_IMUX37_15", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SE2A1_15", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_IMUX39_15", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_LH9_15", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EE4B1_15", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_EE4C1_15", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX28_15", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_NW4END0_15", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_FAN7_15", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX21_15", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_IMUX44_15", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_SE4C1_15", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_LH8_15", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_WW4A2_15", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_CTRL1_15", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_IMUX11_15", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_WW4B3_15", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_FAN4_15", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_LH1_15", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_LH4_15", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_NW4A2_15", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_EE2A3_15", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EE4A3_15", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_NW2A2_15", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_NE2A3_15", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_SW2A2_15", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_IMUX42_15", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_EE4BEG2_15", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_WW4C2_15", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_SW4END1_15", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_NW4A0_15", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX40_15", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_EL1BEG3_15", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_NE2A2_15", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_FAN1_15", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX26_15", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_SW4A1_15", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_IMUX20_15", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SW4A0_15", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_WW2A0_15", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_FAN6_15", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX23_15", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_LH2_15", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_WW4C0_15", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_WW2END1_15", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_BYP5_15", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_IMUX2_15", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_NE4C2_15", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_IMUX29_15", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_EE4C0_15", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_IMUX22_15", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX17_15", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_SE4BEG0_15", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_EL1BEG0_15", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_LH12_15", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_EL1BEG1_15", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_IMUX9_15", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX4_15", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_ER1BEG2_15", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_EE4BEG1_15", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_IMUX33_15", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_BYP3_15", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_IMUX46_15", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW2END2_15", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_SE2A2_15", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_EE2A2_15", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_NE4C3_15", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_EE2BEG0_15", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_EE2BEG2_15", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_WW2END0_15", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_IMUX10_15", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_IMUX19_15", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_IMUX34_15", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_LH11_15", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_WR1END0_15", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_NW2A1_15", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_WW4END3_15", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX13_15", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_SW4END2_15", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_EE4B2_15", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_CLK0_15", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_FAN3_15", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_BYP0_15", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_BYP4_15", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_NW4A1_15", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_IMUX5_15", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX47_15", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_SW4A2_15", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_BYP7_15", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_EE2A0_15", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WW4C1_15", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_EE4C3_15", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_NE4BEG2_15", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_NW2A3_15", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_CLK1_15", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_ER1BEG1_15", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_LH3_15", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_SE2A3_15", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_ER1BEG0_15", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_EE4C2_15", + "VFRAME_EE4C2" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "DSP_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "DSP_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "DSP_LH6_0", + "VBRK_LH6" + ], + [ + "DSP_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "DSP_LH2_0", + "VBRK_LH2" + ], + [ + "DSP_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "DSP_LH12_0", + "VBRK_LH12" + ], + [ + "DSP_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "DSP_LH4_0", + "VBRK_LH4" + ], + [ + "DSP_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "DSP_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "DSP_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "DSP_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "DSP_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "DSP_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "DSP_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "DSP_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "DSP_MONITOR_N_0", + "VBRK_MONITOR_N" + ], + [ + "DSP_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "DSP_SW4A1_0", + "VBRK_SW4A1" + ], + [ + "DSP_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "DSP_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "DSP_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "DSP_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "DSP_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "DSP_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "DSP_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "DSP_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "DSP_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "DSP_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "DSP_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "DSP_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "DSP_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "DSP_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "DSP_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "DSP_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "DSP_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "DSP_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "DSP_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "DSP_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "DSP_LH3_0", + "VBRK_LH3" + ], + [ + "DSP_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "DSP_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "DSP_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "DSP_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "DSP_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "DSP_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "DSP_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "DSP_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "DSP_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "DSP_LH10_0", + "VBRK_LH10" + ], + [ + "DSP_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "DSP_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "DSP_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "DSP_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "DSP_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "DSP_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "DSP_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "DSP_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "DSP_LH1_0", + "VBRK_LH1" + ], + [ + "DSP_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "DSP_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "DSP_LH11_0", + "VBRK_LH11" + ], + [ + "DSP_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "DSP_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "DSP_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "DSP_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "DSP_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "DSP_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "DSP_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "DSP_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "DSP_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "DSP_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "DSP_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "DSP_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "DSP_LH5_0", + "VBRK_LH5" + ], + [ + "DSP_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "DSP_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "DSP_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "DSP_LH9_0", + "VBRK_LH9" + ], + [ + "DSP_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "DSP_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "DSP_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "DSP_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "DSP_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "DSP_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "DSP_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "DSP_MONITOR_P_0", + "VBRK_MONITOR_P" + ], + [ + "DSP_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "DSP_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "DSP_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "DSP_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "DSP_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "DSP_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "DSP_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "DSP_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "DSP_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "DSP_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "DSP_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "DSP_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "DSP_LH7_0", + "VBRK_LH7" + ], + [ + "DSP_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "DSP_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "DSP_LH8_0", + "VBRK_LH8" + ], + [ + "DSP_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "DSP_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "DSP_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "DSP_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "DSP_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "DSP_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "DSP_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "DSP_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "DSP_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "DSP_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "DSP_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "DSP_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "DSP_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "DSP_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "DSP_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "DSP_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "DSP_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "DSP_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "DSP_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "DSP_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "DSP_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "DSP_WW4C0_0", + "VBRK_WW4C0" + ] + ], + "tile_types": [ + "DSP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 5 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX5_0", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_FAN1_0", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX11_0", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_FAN5_0", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_BYP5_0", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX6_0", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX0_0", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX40_0", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX23_0", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_CTRL0_0", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX25_0", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B17_0", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B10_0", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_BYP4_0", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX4_0", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX3_0", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_FAN2_0", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX7_0", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX18_0", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX42_0", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX39_0", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX46_0", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP3_0", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX14_0", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX24_0", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_FAN3_0", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN6_0", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_LOGIC_OUTS_B3_0", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_LOGIC_OUTS_B13_0", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B9_0", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX44_0", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX1_0", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX26_0", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX27_0", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX47_0", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_CLK1_0", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_LOGIC_OUTS_B7_0", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_FAN0_0", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX30_0", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_CTRL1_0", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX12_0", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B4_0", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_IMUX38_0", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX19_0", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_BYP2_0", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX22_0", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B5_0", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_FAN4_0", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX20_0", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_BYP7_0", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_BYP0_0", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX33_0", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX43_0", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_LOGIC_OUTS_B20_0", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX13_0", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_CLK0_0", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX36_0", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX21_0", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_LOGIC_OUTS_B6_0", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX35_0", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX41_0", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX28_0", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX10_0", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX9_0", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX45_0", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX32_0", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B16_0", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_BYP6_0", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX8_0", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX31_0", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_BYP1_0", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX15_0", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_LOGIC_OUTS_B19_0", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX17_0", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX37_0", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_LOGIC_OUTS_B1_0", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_FAN7_0", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B0_0", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX2_0", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX16_0", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX29_0", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX34_0", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_LOGIC_OUTS_B2_0", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_LOGIC_OUTS_B11_0", + "VBRK_EXT_LOGIC_OUTS_B11" + ] + ], + "tile_types": [ + "GTX_CHANNEL_3", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + 11 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_IMUX23_2", + "CMT_TOP_IMUX23_15" + ], + [ + "CMT_FIFO_L_IMUX8_1", + "CMT_TOP_IMUX8_14" + ], + [ + "CMT_FIFO_EE4BEG3_2", + "CMT_TOP_EE4BEG3_15" + ], + [ + "CMT_FIFO_L_FAN6_2", + "CMT_TOP_FAN6_15" + ], + [ + "CMT_FIFO_WW4C2_2", + "CMT_TOP_WW4C2_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_0", + "CMT_TOP_LOGIC_OUTS_L_B12_13" + ], + [ + "CMT_FIFO_WW4B0_2", + "CMT_TOP_WW4B0_15" + ], + [ + "CMT_FIFO_EE2A2_2", + "CMT_TOP_EE2A2_15" + ], + [ + "CMT_FIFO_L_IMUX20_0", + "CMT_TOP_IMUX20_13" + ], + [ + "CMT_FIFO_L_BYP1_2", + "CMT_TOP_BYP1_15" + ], + [ + "CMT_FIFO_L_FAN0_1", + "CMT_TOP_FAN0_14" + ], + [ + "CMT_FIFO_L_IMUX36_0", + "CMT_TOP_IMUX36_13" + ], + [ + "CMT_FIFO_SW2A2_2", + "CMT_TOP_SW2A2_15" + ], + [ + "CMT_FIFO_EE2BEG3_1", + "CMT_TOP_EE2BEG3_14" + ], + [ + "CMT_FIFO_L_IMUX28_1", + "CMT_TOP_IMUX28_14" + ], + [ + "CMT_FIFO_WW4B2_2", + "CMT_TOP_WW4B2_15" + ], + [ + "CMT_FIFO_NW4A1_2", + "CMT_TOP_NW4A1_15" + ], + [ + "CMT_FIFO_NW4A2_1", + "CMT_TOP_NW4A2_14" + ], + [ + "CMT_FIFO_L_IMUX9_1", + "CMT_TOP_IMUX9_14" + ], + [ + "CMT_FIFO_NE2A1_1", + "CMT_TOP_NE2A1_14" + ], + [ + "CMT_FIFO_EE2BEG0_0", + "CMT_TOP_EE2BEG0_13" + ], + [ + "CMT_FIFO_L_FAN0_2", + "CMT_TOP_FAN0_15" + ], + [ + "CMT_FIFO_L_IMUX38_1", + "CMT_TOP_IMUX38_14" + ], + [ + "CMT_FIFO_L_IMUX36_1", + "CMT_TOP_IMUX36_14" + ], + [ + "CMT_FIFO_EE2A1_2", + "CMT_TOP_EE2A1_15" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "CMT_TOP_OCLKDIV_14" + ], + [ + "CMT_FIFO_EE4A2_1", + "CMT_TOP_EE4A2_14" + ], + [ + "CMT_FIFO_WW2END0_1", + "CMT_TOP_WW2END0_14" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "CMT_TOP_OCLKDIV_13" + ], + [ + "CMT_FIFO_EE2A0_2", + "CMT_TOP_EE2A0_15" + ], + [ + "CMT_FIFO_SE4BEG2_1", + "CMT_TOP_SE4BEG2_14" + ], + [ + "CMT_FIFO_EE4BEG1_2", + "CMT_TOP_EE4BEG1_15" + ], + [ + "CMT_FIFO_EE4A0_2", + "CMT_TOP_EE4A0_15" + ], + [ + "CMT_FIFO_L_IMUX31_1", + "CMT_TOP_IMUX31_14" + ], + [ + "CMT_FIFO_EE4B3_2", + "CMT_TOP_EE4B3_15" + ], + [ + "CMT_FIFO_EE4BEG3_0", + "CMT_TOP_EE4BEG3_13" + ], + [ + "CMT_FIFO_L_IMUX33_2", + "CMT_TOP_IMUX33_15" + ], + [ + "CMT_FIFO_NW4A1_0", + "CMT_TOP_NW4A1_13" + ], + [ + "CMT_FIFO_SE4C3_0", + "CMT_TOP_SE4C3_13" + ], + [ + "CMT_FIFO_WW4B3_0", + "CMT_TOP_WW4B3_13" + ], + [ + "CMT_FIFO_WW4A2_1", + "CMT_TOP_WW4A2_14" + ], + [ + "CMT_FIFO_L_BYP2_0", + "CMT_TOP_BYP2_13" + ], + [ + "CMT_FIFO_L_IMUX26_1", + "CMT_TOP_IMUX26_14" + ], + [ + "CMT_FIFO_WR1END1_1", + "CMT_TOP_WR1END1_14" + ], + [ + "CMT_FIFO_EE4C1_2", + "CMT_TOP_EE4C1_15" + ], + [ + "CMT_FIFO_ER1BEG1_1", + "CMT_TOP_ER1BEG1_14" + ], + [ + "CMT_FIFO_LH2_0", + "CMT_TOP_LH2_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_0", + "CMT_TOP_LOGIC_OUTS_L_B5_13" + ], + [ + "CMT_FIFO_LH10_1", + "CMT_TOP_LH10_14" + ], + [ + "CMT_FIFO_L_IMUX42_2", + "CMT_TOP_IMUX42_15" + ], + [ + "CMT_FIFO_L_IMUX6_0", + "CMT_TOP_IMUX6_13" + ], + [ + "CMT_FIFO_SE2A1_1", + "CMT_TOP_SE2A1_14" + ], + [ + "CMT_FIFO_SE2A0_1", + "CMT_TOP_SE2A0_14" + ], + [ + "CMT_FIFO_SW2A1_1", + "CMT_TOP_SW2A1_14" + ], + [ + "CMT_FIFO_SE4C2_0", + "CMT_TOP_SE4C2_13" + ], + [ + "CMT_FIFO_WW2A3_1", + "CMT_TOP_WW2A3_14" + ], + [ + "CMT_FIFO_L_IMUX3_1", + "CMT_TOP_IMUX3_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_15" + ], + [ + "CMT_FIFO_L_IMUX12_0", + "CMT_TOP_IMUX12_13" + ], + [ + "CMT_FIFO_NE4C0_0", + "CMT_TOP_NE4C0_13" + ], + [ + "CMT_FIFO_L_BYP7_0", + "CMT_TOP_BYP7_13" + ], + [ + "CMT_FIFO_WR1END1_2", + "CMT_TOP_WR1END1_15" + ], + [ + "CMT_FIFO_SE4C3_2", + "CMT_TOP_SE4C3_15" + ], + [ + "CMT_FIFO_NE4BEG1_0", + "CMT_TOP_NE4BEG1_13" + ], + [ + "CMT_FIFO_EL1BEG0_1", + "CMT_TOP_EL1BEG0_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_1", + "CMT_TOP_LOGIC_OUTS_L_B9_14" + ], + [ + "CMT_FIFO_WW4C0_0", + "CMT_TOP_WW4C0_13" + ], + [ + "CMT_FIFO_L_IMUX0_0", + "CMT_TOP_IMUX0_13" + ], + [ + "CMT_FIFO_WW2END2_0", + "CMT_TOP_WW2END2_13" + ], + [ + "CMT_FIFO_L_IMUX15_0", + "CMT_TOP_IMUX15_13" + ], + [ + "CMT_FIFO_NE4BEG1_1", + "CMT_TOP_NE4BEG1_14" + ], + [ + "CMT_FIFO_WL1END0_2", + "CMT_TOP_WL1END0_15" + ], + [ + "CMT_FIFO_EE4A0_0", + "CMT_TOP_EE4A0_13" + ], + [ + "CMT_FIFO_L_FAN1_2", + "CMT_TOP_FAN1_15" + ], + [ + "CMT_FIFO_L_IMUX2_2", + "CMT_TOP_IMUX2_15" + ], + [ + "CMT_FIFO_SW4END2_2", + "CMT_TOP_SW4END2_15" + ], + [ + "CMT_FIFO_L_IMUX33_0", + "CMT_TOP_IMUX33_13" + ], + [ + "CMT_FIFO_L_FAN2_1", + "CMT_TOP_FAN2_14" + ], + [ + "CMT_FIFO_EE2BEG0_1", + "CMT_TOP_EE2BEG0_14" + ], + [ + "CMT_FIFO_NW4END3_2", + "CMT_TOP_NW4END3_15" + ], + [ + "CMT_FIFO_SE4C0_2", + "CMT_TOP_SE4C0_15" + ], + [ + "CMT_FIFO_L_BYP7_2", + "CMT_TOP_BYP7_15" + ], + [ + "CMT_FIFO_L_IMUX21_0", + "CMT_TOP_IMUX21_13" + ], + [ + "CMT_FIFO_L_IMUX27_0", + "CMT_TOP_IMUX27_13" + ], + [ + "CMT_FIFO_NW2A0_2", + "CMT_TOP_NW2A0_15" + ], + [ + "CMT_FIFO_WL1END3_0", + "CMT_TOP_WL1END3_13" + ], + [ + "CMT_FIFO_SW4A2_2", + "CMT_TOP_SW4A2_15" + ], + [ + "CMT_FIFO_L_IMUX7_2", + "CMT_TOP_IMUX7_15" + ], + [ + "CMT_FIFO_SW4END1_1", + "CMT_TOP_SW4END1_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_2", + "CMT_TOP_LOGIC_OUTS_L_B11_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_1", + "CMT_TOP_LOGIC_OUTS_L_B1_14" + ], + [ + "CMT_FIFO_EE4A1_2", + "CMT_TOP_EE4A1_15" + ], + [ + "CMT_FIFO_L_IMUX47_0", + "CMT_TOP_IMUX47_13" + ], + [ + "CMT_FIFO_L_IMUX29_1", + "CMT_TOP_IMUX29_14" + ], + [ + "CMT_FIFO_SW4A1_1", + "CMT_TOP_SW4A1_14" + ], + [ + "CMT_FIFO_L_IMUX10_2", + "CMT_TOP_IMUX10_15" + ], + [ + "CMT_FIFO_NE2A0_2", + "CMT_TOP_NE2A0_15" + ], + [ + "CMT_FIFO_L_IMUX7_1", + "CMT_TOP_IMUX7_14" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "CMT_TOP_OCLKDIV_15" + ], + [ + "CMT_FIFO_L_IMUX12_2", + "CMT_TOP_IMUX12_15" + ], + [ + "CMT_FIFO_EE4B2_1", + "CMT_TOP_EE4B2_14" + ], + [ + "CMT_FIFO_L_IMUX39_2", + "CMT_TOP_IMUX39_15" + ], + [ + "CMT_FIFO_L_BYP2_1", + "CMT_TOP_BYP2_14" + ], + [ + "CMT_FIFO_EE4B0_2", + "CMT_TOP_EE4B0_15" + ], + [ + "CMT_FIFO_L_IMUX44_2", + "CMT_TOP_IMUX44_15" + ], + [ + "CMT_FIFO_EE4C1_0", + "CMT_TOP_EE4C1_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_0", + "CMT_TOP_LOGIC_OUTS_L_B20_13" + ], + [ + "CMT_FIFO_SE4BEG0_1", + "CMT_TOP_SE4BEG0_14" + ], + [ + "CMT_FIFO_L_IMUX22_0", + "CMT_TOP_IMUX22_13" + ], + [ + "CMT_FIFO_WL1END0_1", + "CMT_TOP_WL1END0_14" + ], + [ + "CMT_FIFO_SE4BEG3_0", + "CMT_TOP_SE4BEG3_13" + ], + [ + "CMT_FIFO_NE2A0_0", + "CMT_TOP_NE2A0_13" + ], + [ + "CMT_FIFO_WW2A0_2", + "CMT_TOP_WW2A0_15" + ], + [ + "CMT_FIFO_WW4END1_1", + "CMT_TOP_WW4END1_14" + ], + [ + "CMT_FIFO_EE4B2_2", + "CMT_TOP_EE4B2_15" + ], + [ + "CMT_FIFO_L_FAN6_0", + "CMT_TOP_FAN6_13" + ], + [ + "CMT_FIFO_L_FAN4_2", + "CMT_TOP_FAN4_15" + ], + [ + "CMT_FIFO_ER1BEG0_0", + "CMT_TOP_ER1BEG0_13" + ], + [ + "CMT_FIFO_L_IMUX24_2", + "CMT_TOP_IMUX24_15" + ], + [ + "CMT_FIFO_L_BYP0_1", + "CMT_TOP_BYP0_14" + ], + [ + "CMT_FIFO_L_CTRL1_2", + "CMT_TOP_CTRL1_15" + ], + [ + "CMT_FIFO_NW4A3_2", + "CMT_TOP_NW4A3_15" + ], + [ + "CMT_FIFO_EE4C3_2", + "CMT_TOP_EE4C3_15" + ], + [ + "CMT_FIFO_NW2A2_0", + "CMT_TOP_NW2A2_13" + ], + [ + "CMT_FIFO_L_IMUX25_0", + "CMT_TOP_IMUX25_13" + ], + [ + "CMT_FIFO_WR1END2_1", + "CMT_TOP_WR1END2_14" + ], + [ + "CMT_FIFO_EE4A2_2", + "CMT_TOP_EE4A2_15" + ], + [ + "CMT_FIFO_LH8_0", + "CMT_TOP_LH8_13" + ], + [ + "CMT_FIFO_NW2A0_1", + "CMT_TOP_NW2A0_14" + ], + [ + "CMT_FIFO_WL1END3_2", + "CMT_TOP_WL1END3_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_0", + "CMT_TOP_LOGIC_OUTS_L_B13_13" + ], + [ + "CMT_FIFO_EE4BEG2_2", + "CMT_TOP_EE4BEG2_15" + ], + [ + "CMT_FIFO_L_IMUX1_1", + "CMT_TOP_IMUX1_14" + ], + [ + "CMT_FIFO_L_BYP3_0", + "CMT_TOP_BYP3_13" + ], + [ + "CMT_FIFO_L_CTRL0_1", + "CMT_TOP_CTRL0_14" + ], + [ + "CMT_FIFO_WW2A2_0", + "CMT_TOP_WW2A2_13" + ], + [ + "CMT_FIFO_L_FAN7_2", + "CMT_TOP_FAN7_15" + ], + [ + "CMT_FIFO_EE4A0_1", + "CMT_TOP_EE4A0_14" + ], + [ + "CMT_FIFO_L_IMUX11_1", + "CMT_TOP_IMUX11_14" + ], + [ + "CMT_FIFO_NE4BEG2_0", + "CMT_TOP_NE4BEG2_13" + ], + [ + "CMT_FIFO_NW4END3_1", + "CMT_TOP_NW4END3_14" + ], + [ + "CMT_FIFO_SW4END0_1", + "CMT_TOP_SW4END0_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_1", + "CMT_TOP_LOGIC_OUTS_L_B5_14" + ], + [ + "CMT_FIFO_SW2A3_1", + "CMT_TOP_SW2A3_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_1", + "CMT_TOP_LOGIC_OUTS_L_B13_14" + ], + [ + "CMT_FIFO_EE4B1_1", + "CMT_TOP_EE4B1_14" + ], + [ + "CMT_FIFO_L_IMUX3_2", + "CMT_TOP_IMUX3_15" + ], + [ + "CMT_FIFO_SW4A2_0", + "CMT_TOP_SW4A2_13" + ], + [ + "CMT_FIFO_EE2A0_0", + "CMT_TOP_EE2A0_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_2", + "CMT_TOP_LOGIC_OUTS_L_B22_15" + ], + [ + "CMT_FIFO_NW4A3_1", + "CMT_TOP_NW4A3_14" + ], + [ + "CMT_FIFO_L_IMUX18_1", + "CMT_TOP_IMUX18_14" + ], + [ + "CMT_FIFO_EE4A2_0", + "CMT_TOP_EE4A2_13" + ], + [ + "CMT_FIFO_L_IMUX47_1", + "CMT_TOP_IMUX47_14" + ], + [ + "CMT_FIFO_L_IMUX43_2", + "CMT_TOP_IMUX43_15" + ], + [ + "CMT_FIFO_ER1BEG3_0", + "CMT_TOP_ER1BEG3_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_0", + "CMT_TOP_LOGIC_OUTS_L_B9_13" + ], + [ + "CMT_FIFO_WW4C1_1", + "CMT_TOP_WW4C1_14" + ], + [ + "CMT_FIFO_WW2END1_1", + "CMT_TOP_WW2END1_14" + ], + [ + "CMT_FIFO_WL1END2_0", + "CMT_TOP_WL1END2_13" + ], + [ + "CMT_FIFO_EE4B3_1", + "CMT_TOP_EE4B3_14" + ], + [ + "CMT_FIFO_EL1BEG0_2", + "CMT_TOP_EL1BEG0_15" + ], + [ + "CMT_FIFO_NW4A3_0", + "CMT_TOP_NW4A3_13" + ], + [ + "CMT_FIFO_LH12_0", + "CMT_TOP_LH12_13" + ], + [ + "CMT_FIFO_NW4A0_0", + "CMT_TOP_NW4A0_13" + ], + [ + "CMT_FIFO_SW4END1_2", + "CMT_TOP_SW4END1_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_0", + "CMT_TOP_LOGIC_OUTS_L_B19_13" + ], + [ + "CMT_FIFO_SW4END3_2", + "CMT_TOP_SW4END3_15" + ], + [ + "CMT_FIFO_SW2A3_2", + "CMT_TOP_SW2A3_15" + ], + [ + "CMT_FIFO_LH5_2", + "CMT_TOP_LH5_15" + ], + [ + "CMT_FIFO_L_CLK1_1", + "CMT_TOP_CLK1_14" + ], + [ + "CMT_FIFO_L_IMUX8_2", + "CMT_TOP_IMUX8_15" + ], + [ + "CMT_FIFO_L_IMUX32_2", + "CMT_TOP_IMUX32_15" + ], + [ + "CMT_FIFO_L_BYP1_0", + "CMT_TOP_BYP1_13" + ], + [ + "CMT_FIFO_WW4B3_2", + "CMT_TOP_WW4B3_15" + ], + [ + "CMT_FIFO_L_FAN3_2", + "CMT_TOP_FAN3_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_2", + "CMT_TOP_LOGIC_OUTS_L_B13_15" + ], + [ + "CMT_FIFO_EE4BEG0_2", + "CMT_TOP_EE4BEG0_15" + ], + [ + "CMT_FIFO_L_IMUX40_0", + "CMT_TOP_IMUX40_13" + ], + [ + "CMT_FIFO_L_IMUX39_0", + "CMT_TOP_IMUX39_13" + ], + [ + "CMT_FIFO_WR1END0_1", + "CMT_TOP_WR1END0_14" + ], + [ + "CMT_FIFO_L_IMUX21_1", + "CMT_TOP_IMUX21_14" + ], + [ + "CMT_FIFO_LH6_0", + "CMT_TOP_LH6_13" + ], + [ + "CMT_FIFO_L_IMUX24_1", + "CMT_TOP_IMUX24_14" + ], + [ + "CMT_FIFO_WW4END0_2", + "CMT_TOP_WW4END0_15" + ], + [ + "CMT_FIFO_WR1END0_2", + "CMT_TOP_WR1END0_15" + ], + [ + "CMT_FIFO_EL1BEG1_0", + "CMT_TOP_EL1BEG1_13" + ], + [ + "CMT_FIFO_WW4B0_1", + "CMT_TOP_WW4B0_14" + ], + [ + "CMT_FIFO_EE4BEG1_0", + "CMT_TOP_EE4BEG1_13" + ], + [ + "CMT_FIFO_NE4C0_1", + "CMT_TOP_NE4C0_14" + ], + [ + "CMT_FIFO_WL1END2_1", + "CMT_TOP_WL1END2_14" + ], + [ + "CMT_FIFO_NW4END3_0", + "CMT_TOP_NW4END3_13" + ], + [ + "CMT_FIFO_LH11_2", + "CMT_TOP_LH11_15" + ], + [ + "CMT_FIFO_WW2END3_2", + "CMT_TOP_WW2END3_15" + ], + [ + "CMT_FIFO_EL1BEG0_0", + "CMT_TOP_EL1BEG0_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_1", + "CMT_TOP_LOGIC_OUTS_L_B20_14" + ], + [ + "CMT_FIFO_L_FAN4_1", + "CMT_TOP_FAN4_14" + ], + [ + "CMT_FIFO_NE4BEG3_0", + "CMT_TOP_NE4BEG3_13" + ], + [ + "CMT_FIFO_SW4A1_0", + "CMT_TOP_SW4A1_13" + ], + [ + "CMT_FIFO_EE4C1_1", + "CMT_TOP_EE4C1_14" + ], + [ + "CMT_FIFO_NW2A1_1", + "CMT_TOP_NW2A1_14" + ], + [ + "CMT_FIFO_L_FAN1_1", + "CMT_TOP_FAN1_14" + ], + [ + "CMT_FIFO_L_CTRL0_2", + "CMT_TOP_CTRL0_15" + ], + [ + "CMT_FIFO_L_FAN6_1", + "CMT_TOP_FAN6_14" + ], + [ + "CMT_FIFO_EE4B2_0", + "CMT_TOP_EE4B2_13" + ], + [ + "CMT_FIFO_L_IMUX32_1", + "CMT_TOP_IMUX32_14" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "CMT_TOP_ICLK_14" + ], + [ + "CMT_FIFO_WW4A0_0", + "CMT_TOP_WW4A0_13" + ], + [ + "CMT_FIFO_WW4B1_1", + "CMT_TOP_WW4B1_14" + ], + [ + "CMT_FIFO_L_IMUX17_0", + "CMT_TOP_IMUX17_13" + ], + [ + "CMT_FIFO_WW2A3_0", + "CMT_TOP_WW2A3_13" + ], + [ + "CMT_FIFO_NE4C0_2", + "CMT_TOP_NE4C0_15" + ], + [ + "CMT_FIFO_SE4BEG1_0", + "CMT_TOP_SE4BEG1_13" + ], + [ + "CMT_FIFO_L_IMUX38_0", + "CMT_TOP_IMUX38_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_2", + "CMT_TOP_LOGIC_OUTS_L_B8_15" + ], + [ + "CMT_FIFO_L_IMUX11_0", + "CMT_TOP_IMUX11_13" + ], + [ + "CMT_FIFO_NW2A1_2", + "CMT_TOP_NW2A1_15" + ], + [ + "CMT_FIFO_WR1END0_0", + "CMT_TOP_WR1END0_13" + ], + [ + "CMT_FIFO_WW4B2_0", + "CMT_TOP_WW4B2_13" + ], + [ + "CMT_FIFO_WW4A3_0", + "CMT_TOP_WW4A3_13" + ], + [ + "CMT_FIFO_L_IMUX20_1", + "CMT_TOP_IMUX20_14" + ], + [ + "CMT_FIFO_SE4BEG2_0", + "CMT_TOP_SE4BEG2_13" + ], + [ + "CMT_FIFO_WW2END3_1", + "CMT_TOP_WW2END3_14" + ], + [ + "CMT_FIFO_L_BYP6_1", + "CMT_TOP_BYP6_14" + ], + [ + "CMT_FIFO_SE4BEG3_2", + "CMT_TOP_SE4BEG3_15" + ], + [ + "CMT_FIFO_LH11_0", + "CMT_TOP_LH11_13" + ], + [ + "CMT_FIFO_L_IMUX27_1", + "CMT_TOP_IMUX27_14" + ], + [ + "CMT_FIFO_L_IMUX16_0", + "CMT_TOP_IMUX16_13" + ], + [ + "CMT_FIFO_L_IMUX19_1", + "CMT_TOP_IMUX19_14" + ], + [ + "CMT_FIFO_LH7_1", + "CMT_TOP_LH7_14" + ], + [ + "CMT_FIFO_L_CLK1_2", + "CMT_TOP_CLK1_15" + ], + [ + "CMT_FIFO_SW2A0_2", + "CMT_TOP_SW2A0_15" + ], + [ + "CMT_FIFO_WW4B3_1", + "CMT_TOP_WW4B3_14" + ], + [ + "CMT_FIFO_L_IMUX29_2", + "CMT_TOP_IMUX29_15" + ], + [ + "CMT_FIFO_LH1_0", + "CMT_TOP_LH1_13" + ], + [ + "CMT_FIFO_WW2A2_1", + "CMT_TOP_WW2A2_14" + ], + [ + "CMT_FIFO_WW2A1_2", + "CMT_TOP_WW2A1_15" + ], + [ + "CMT_FIFO_EL1BEG1_1", + "CMT_TOP_EL1BEG1_14" + ], + [ + "CMT_FIFO_SW2A2_1", + "CMT_TOP_SW2A2_14" + ], + [ + "CMT_FIFO_WR1END3_0", + "CMT_TOP_WR1END3_13" + ], + [ + "CMT_FIFO_EE2A3_0", + "CMT_TOP_EE2A3_13" + ], + [ + "CMT_FIFO_SE4BEG2_2", + "CMT_TOP_SE4BEG2_15" + ], + [ + "CMT_FIFO_L_CTRL1_1", + "CMT_TOP_CTRL1_14" + ], + [ + "CMT_FIFO_L_IMUX0_2", + "CMT_TOP_IMUX0_15" + ], + [ + "CMT_FIFO_WW4A2_2", + "CMT_TOP_WW4A2_15" + ], + [ + "CMT_FIFO_LH11_1", + "CMT_TOP_LH11_14" + ], + [ + "CMT_FIFO_EE4A3_1", + "CMT_TOP_EE4A3_14" + ], + [ + "CMT_FIFO_L_IMUX18_2", + "CMT_TOP_IMUX18_15" + ], + [ + "CMT_FIFO_LH6_1", + "CMT_TOP_LH6_14" + ], + [ + "CMT_FIFO_L_IMUX23_0", + "CMT_TOP_IMUX23_13" + ], + [ + "CMT_FIFO_LH4_2", + "CMT_TOP_LH4_15" + ], + [ + "CMT_FIFO_WW4END2_2", + "CMT_TOP_WW4END2_15" + ], + [ + "CMT_FIFO_NW4END2_0", + "CMT_TOP_NW4END2_13" + ], + [ + "CMT_FIFO_EE4C0_0", + "CMT_TOP_EE4C0_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_2", + "CMT_TOP_LOGIC_OUTS_L_B5_15" + ], + [ + "CMT_FIFO_EE2A1_0", + "CMT_TOP_EE2A1_13" + ], + [ + "CMT_FIFO_ER1BEG1_0", + "CMT_TOP_ER1BEG1_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_2", + "CMT_TOP_LOGIC_OUTS_L_B20_15" + ], + [ + "CMT_FIFO_WL1END1_1", + "CMT_TOP_WL1END1_14" + ], + [ + "CMT_FIFO_WW2END2_2", + "CMT_TOP_WW2END2_15" + ], + [ + "CMT_FIFO_SE4BEG0_0", + "CMT_TOP_SE4BEG0_13" + ], + [ + "CMT_FIFO_L_IMUX40_2", + "CMT_TOP_IMUX40_15" + ], + [ + "CMT_FIFO_NE4BEG0_2", + "CMT_TOP_NE4BEG0_15" + ], + [ + "CMT_FIFO_SW4A1_2", + "CMT_TOP_SW4A1_15" + ], + [ + "CMT_FIFO_L_IMUX9_0", + "CMT_TOP_IMUX9_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_2", + "CMT_TOP_LOGIC_OUTS_L_B12_15" + ], + [ + "CMT_FIFO_WW4B1_2", + "CMT_TOP_WW4B1_15" + ], + [ + "CMT_FIFO_SW2A2_0", + "CMT_TOP_SW2A2_13" + ], + [ + "CMT_FIFO_WW2END1_0", + "CMT_TOP_WW2END1_13" + ], + [ + "CMT_FIFO_L_FAN3_0", + "CMT_TOP_FAN3_13" + ], + [ + "CMT_FIFO_WW4C2_1", + "CMT_TOP_WW4C2_14" + ], + [ + "CMT_FIFO_L_IMUX2_0", + "CMT_TOP_IMUX2_13" + ], + [ + "CMT_FIFO_L_IMUX28_2", + "CMT_TOP_IMUX28_15" + ], + [ + "CMT_FIFO_NE4C3_0", + "CMT_TOP_NE4C3_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_1", + "CMT_TOP_LOGIC_OUTS_L_B0_14" + ], + [ + "CMT_FIFO_L_BYP1_1", + "CMT_TOP_BYP1_14" + ], + [ + "CMT_FIFO_WL1END1_2", + "CMT_TOP_WL1END1_15" + ], + [ + "CMT_FIFO_SE2A1_0", + "CMT_TOP_SE2A1_13" + ], + [ + "CMT_FIFO_L_IMUX41_2", + "CMT_TOP_IMUX41_15" + ], + [ + "CMT_FIFO_NE4C3_2", + "CMT_TOP_NE4C3_15" + ], + [ + "CMT_FIFO_NW4END2_2", + "CMT_TOP_NW4END2_15" + ], + [ + "CMT_FIFO_SW4END0_0", + "CMT_TOP_SW4END0_13" + ], + [ + "CMT_FIFO_SE4C0_0", + "CMT_TOP_SE4C0_13" + ], + [ + "CMT_FIFO_NW4END1_1", + "CMT_TOP_NW4END1_14" + ], + [ + "CMT_FIFO_SE4BEG1_2", + "CMT_TOP_SE4BEG1_15" + ], + [ + "CMT_FIFO_EE4C0_1", + "CMT_TOP_EE4C0_14" + ], + [ + "CMT_FIFO_NE2A2_0", + "CMT_TOP_NE2A2_13" + ], + [ + "CMT_FIFO_L_BYP5_0", + "CMT_TOP_BYP5_13" + ], + [ + "CMT_FIFO_LH7_2", + "CMT_TOP_LH7_15" + ], + [ + "CMT_FIFO_EE4BEG2_1", + "CMT_TOP_EE4BEG2_14" + ], + [ + "CMT_FIFO_EE4BEG2_0", + "CMT_TOP_EE4BEG2_13" + ], + [ + "CMT_FIFO_L_CTRL1_0", + "CMT_TOP_CTRL1_13" + ], + [ + "CMT_FIFO_NW4A0_1", + "CMT_TOP_NW4A0_14" + ], + [ + "CMT_FIFO_NW2A2_2", + "CMT_TOP_NW2A2_15" + ], + [ + "CMT_FIFO_NE2A2_1", + "CMT_TOP_NE2A2_14" + ], + [ + "CMT_FIFO_NE4C2_0", + "CMT_TOP_NE4C2_13" + ], + [ + "CMT_FIFO_SE4BEG0_2", + "CMT_TOP_SE4BEG0_15" + ], + [ + "CMT_FIFO_L_IMUX14_2", + "CMT_TOP_IMUX14_15" + ], + [ + "CMT_FIFO_L_BYP6_2", + "CMT_TOP_BYP6_15" + ], + [ + "CMT_FIFO_WW2A1_0", + "CMT_TOP_WW2A1_13" + ], + [ + "CMT_FIFO_NW4END0_1", + "CMT_TOP_NW4END0_14" + ], + [ + "CMT_FIFO_EE4C2_2", + "CMT_TOP_EE4C2_15" + ], + [ + "CMT_FIFO_WR1END3_2", + "CMT_TOP_WR1END3_15" + ], + [ + "CMT_FIFO_WW4A0_1", + "CMT_TOP_WW4A0_14" + ], + [ + "CMT_FIFO_EE2BEG1_2", + "CMT_TOP_EE2BEG1_15" + ], + [ + "CMT_FIFO_NW2A3_0", + "CMT_TOP_NW2A3_13" + ], + [ + "CMT_FIFO_WL1END1_0", + "CMT_TOP_WL1END1_13" + ], + [ + "CMT_FIFO_EE2A2_0", + "CMT_TOP_EE2A2_13" + ], + [ + "CMT_FIFO_SE2A2_2", + "CMT_TOP_SE2A2_15" + ], + [ + "CMT_FIFO_L_IMUX46_1", + "CMT_TOP_IMUX46_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_2", + "CMT_TOP_LOGIC_OUTS_L_B9_15" + ], + [ + "CMT_FIFO_EE4B0_0", + "CMT_TOP_EE4B0_13" + ], + [ + "CMT_FIFO_NE2A3_0", + "CMT_TOP_NE2A3_13" + ], + [ + "CMT_FIFO_SW4END1_0", + "CMT_TOP_SW4END1_13" + ], + [ + "CMT_FIFO_NE4C2_1", + "CMT_TOP_NE4C2_14" + ], + [ + "CMT_FIFO_WW4END2_1", + "CMT_TOP_WW4END2_14" + ], + [ + "CMT_FIFO_SE4C1_0", + "CMT_TOP_SE4C1_13" + ], + [ + "CMT_FIFO_SW4END0_2", + "CMT_TOP_SW4END0_15" + ], + [ + "CMT_FIFO_NE4C2_2", + "CMT_TOP_NE4C2_15" + ], + [ + "CMT_FIFO_NW4END0_2", + "CMT_TOP_NW4END0_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_0", + "CMT_TOP_LOGIC_OUTS_L_B4_13" + ], + [ + "CMT_FIFO_MONITOR_N_0", + "CMT_TOP_MONITOR_N_13" + ], + [ + "CMT_FIFO_EL1BEG3_2", + "CMT_TOP_EL1BEG3_15" + ], + [ + "CMT_FIFO_LH8_2", + "CMT_TOP_LH8_15" + ], + [ + "CMT_FIFO_L_IMUX15_1", + "CMT_TOP_IMUX15_14" + ], + [ + "CMT_FIFO_L_IMUX33_1", + "CMT_TOP_IMUX33_14" + ], + [ + "CMT_FIFO_EE2BEG2_1", + "CMT_TOP_EE2BEG2_14" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "CMT_TOP_ICLKDIV_13" + ], + [ + "CMT_FIFO_L_IMUX16_1", + "CMT_TOP_IMUX16_14" + ], + [ + "CMT_FIFO_L_CLK0_2", + "CMT_TOP_CLK0_15" + ], + [ + "CMT_FIFO_NE2A2_2", + "CMT_TOP_NE2A2_15" + ], + [ + "CMT_FIFO_ER1BEG0_2", + "CMT_TOP_ER1BEG0_15" + ], + [ + "CMT_FIFO_EE4BEG0_1", + "CMT_TOP_EE4BEG0_14" + ], + [ + "CMT_FIFO_L_IMUX34_0", + "CMT_TOP_IMUX34_13" + ], + [ + "CMT_FIFO_WW4A3_2", + "CMT_TOP_WW4A3_15" + ], + [ + "CMT_FIFO_L_IMUX8_0", + "CMT_TOP_IMUX8_13" + ], + [ + "CMT_FIFO_NW2A2_1", + "CMT_TOP_NW2A2_14" + ], + [ + "CMT_FIFO_EE2A2_1", + "CMT_TOP_EE2A2_14" + ], + [ + "CMT_FIFO_SW4A0_1", + "CMT_TOP_SW4A0_14" + ], + [ + "CMT_FIFO_EE4A1_0", + "CMT_TOP_EE4A1_13" + ], + [ + "CMT_FIFO_L_IMUX3_0", + "CMT_TOP_IMUX3_13" + ], + [ + "CMT_FIFO_EE2BEG2_0", + "CMT_TOP_EE2BEG2_13" + ], + [ + "CMT_FIFO_LH2_1", + "CMT_TOP_LH2_14" + ], + [ + "CMT_FIFO_EE4A3_2", + "CMT_TOP_EE4A3_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_1", + "CMT_TOP_LOGIC_OUTS_L_B11_14" + ], + [ + "CMT_FIFO_LH1_2", + "CMT_TOP_LH1_15" + ], + [ + "CMT_FIFO_EE4A1_1", + "CMT_TOP_EE4A1_14" + ], + [ + "CMT_FIFO_L_IMUX47_2", + "CMT_TOP_IMUX47_15" + ], + [ + "CMT_FIFO_L_IMUX17_2", + "CMT_TOP_IMUX17_15" + ], + [ + "CMT_FIFO_NE4BEG2_2", + "CMT_TOP_NE4BEG2_15" + ], + [ + "CMT_FIFO_WW4C0_2", + "CMT_TOP_WW4C0_15" + ], + [ + "CMT_FIFO_EL1BEG2_0", + "CMT_TOP_EL1BEG2_13" + ], + [ + "CMT_FIFO_SE2A2_1", + "CMT_TOP_SE2A2_14" + ], + [ + "CMT_FIFO_L_IMUX13_0", + "CMT_TOP_IMUX13_13" + ], + [ + "CMT_FIFO_L_IMUX30_1", + "CMT_TOP_IMUX30_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_13" + ], + [ + "CMT_FIFO_LH12_2", + "CMT_TOP_LH12_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_1", + "CMT_TOP_LOGIC_OUTS_L_B4_14" + ], + [ + "CMT_FIFO_WW4A3_1", + "CMT_TOP_WW4A3_14" + ], + [ + "CMT_FIFO_WW4C2_0", + "CMT_TOP_WW4C2_13" + ], + [ + "CMT_FIFO_L_BYP3_1", + "CMT_TOP_BYP3_14" + ], + [ + "CMT_FIFO_L_IMUX5_2", + "CMT_TOP_IMUX5_15" + ], + [ + "CMT_FIFO_MONITOR_N_2", + "CMT_TOP_MONITOR_N_15" + ], + [ + "CMT_FIFO_SE4C3_1", + "CMT_TOP_SE4C3_14" + ], + [ + "CMT_FIFO_SE2A3_1", + "CMT_TOP_SE2A3_14" + ], + [ + "CMT_FIFO_NE4BEG3_1", + "CMT_TOP_NE4BEG3_14" + ], + [ + "CMT_FIFO_WW4END1_2", + "CMT_TOP_WW4END1_15" + ], + [ + "CMT_FIFO_EE2A0_1", + "CMT_TOP_EE2A0_14" + ], + [ + "CMT_FIFO_WR1END1_0", + "CMT_TOP_WR1END1_13" + ], + [ + "CMT_FIFO_L_IMUX26_0", + "CMT_TOP_IMUX26_13" + ], + [ + "CMT_FIFO_L_IMUX41_1", + "CMT_TOP_IMUX41_14" + ], + [ + "CMT_FIFO_WW4A1_0", + "CMT_TOP_WW4A1_13" + ], + [ + "CMT_FIFO_WW4C3_0", + "CMT_TOP_WW4C3_13" + ], + [ + "CMT_FIFO_SW4END3_0", + "CMT_TOP_SW4END3_13" + ], + [ + "CMT_FIFO_L_IMUX0_1", + "CMT_TOP_IMUX0_14" + ], + [ + "CMT_FIFO_L_IMUX25_2", + "CMT_TOP_IMUX25_15" + ], + [ + "CMT_FIFO_MONITOR_P_0", + "CMT_TOP_MONITOR_P_13" + ], + [ + "CMT_FIFO_SE4C1_2", + "CMT_TOP_SE4C1_15" + ], + [ + "CMT_FIFO_L_IMUX45_2", + "CMT_TOP_IMUX45_15" + ], + [ + "CMT_FIFO_WW2END2_1", + "CMT_TOP_WW2END2_14" + ], + [ + "CMT_FIFO_L_IMUX45_0", + "CMT_TOP_IMUX45_13" + ], + [ + "CMT_FIFO_WR1END2_0", + "CMT_TOP_WR1END2_13" + ], + [ + "CMT_FIFO_WW4A2_0", + "CMT_TOP_WW4A2_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_1", + "CMT_TOP_LOGIC_OUTS_L_B19_14" + ], + [ + "CMT_FIFO_NE4BEG0_0", + "CMT_TOP_NE4BEG0_13" + ], + [ + "CMT_FIFO_SW4END2_0", + "CMT_TOP_SW4END2_13" + ], + [ + "CMT_FIFO_L_IMUX27_2", + "CMT_TOP_IMUX27_15" + ], + [ + "CMT_FIFO_NE4C1_0", + "CMT_TOP_NE4C1_13" + ], + [ + "CMT_FIFO_SE4BEG3_1", + "CMT_TOP_SE4BEG3_14" + ], + [ + "CMT_FIFO_LH2_2", + "CMT_TOP_LH2_15" + ], + [ + "CMT_FIFO_LH9_2", + "CMT_TOP_LH9_15" + ], + [ + "CMT_FIFO_WW4C1_0", + "CMT_TOP_WW4C1_13" + ], + [ + "CMT_FIFO_SE4BEG1_1", + "CMT_TOP_SE4BEG1_14" + ], + [ + "CMT_FIFO_SW4A0_2", + "CMT_TOP_SW4A0_15" + ], + [ + "CMT_FIFO_NE4BEG1_2", + "CMT_TOP_NE4BEG1_15" + ], + [ + "CMT_FIFO_L_IMUX1_2", + "CMT_TOP_IMUX1_15" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "CMT_TOP_OCLK_15" + ], + [ + "CMT_FIFO_EE4BEG1_1", + "CMT_TOP_EE4BEG1_14" + ], + [ + "CMT_FIFO_LH7_0", + "CMT_TOP_LH7_13" + ], + [ + "CMT_FIFO_L_IMUX19_2", + "CMT_TOP_IMUX19_15" + ], + [ + "CMT_FIFO_WW2END0_2", + "CMT_TOP_WW2END0_15" + ], + [ + "CMT_FIFO_EE4B1_2", + "CMT_TOP_EE4B1_15" + ], + [ + "CMT_FIFO_L_IMUX35_2", + "CMT_TOP_IMUX35_15" + ], + [ + "CMT_FIFO_MONITOR_P_2", + "CMT_TOP_MONITOR_P_15" + ], + [ + "CMT_FIFO_WW4A1_1", + "CMT_TOP_WW4A1_14" + ], + [ + "CMT_FIFO_L_IMUX6_2", + "CMT_TOP_IMUX6_15" + ], + [ + "CMT_FIFO_ER1BEG1_2", + "CMT_TOP_ER1BEG1_15" + ], + [ + "CMT_FIFO_L_FAN5_1", + "CMT_TOP_FAN5_14" + ], + [ + "CMT_FIFO_L_IMUX37_1", + "CMT_TOP_IMUX37_14" + ], + [ + "CMT_FIFO_NW4END0_0", + "CMT_TOP_NW4END0_13" + ], + [ + "CMT_FIFO_L_IMUX31_0", + "CMT_TOP_IMUX31_13" + ], + [ + "CMT_FIFO_L_IMUX45_1", + "CMT_TOP_IMUX45_14" + ], + [ + "CMT_FIFO_SE2A0_2", + "CMT_TOP_SE2A0_15" + ], + [ + "CMT_FIFO_L_IMUX1_0", + "CMT_TOP_IMUX1_13" + ], + [ + "CMT_FIFO_LH3_1", + "CMT_TOP_LH3_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_2", + "CMT_TOP_LOGIC_OUTS_L_B1_15" + ], + [ + "CMT_FIFO_NE2A3_1", + "CMT_TOP_NE2A3_14" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "CMT_TOP_OCLK_14" + ], + [ + "CMT_FIFO_L_IMUX43_0", + "CMT_TOP_IMUX43_13" + ], + [ + "CMT_FIFO_WW2A1_1", + "CMT_TOP_WW2A1_14" + ], + [ + "CMT_FIFO_EL1BEG2_1", + "CMT_TOP_EL1BEG2_14" + ], + [ + "CMT_FIFO_NE4C1_1", + "CMT_TOP_NE4C1_14" + ], + [ + "CMT_FIFO_L_IMUX13_2", + "CMT_TOP_IMUX13_15" + ], + [ + "CMT_FIFO_L_IMUX6_1", + "CMT_TOP_IMUX6_14" + ], + [ + "CMT_FIFO_L_IMUX32_0", + "CMT_TOP_IMUX32_13" + ], + [ + "CMT_FIFO_SE4C0_1", + "CMT_TOP_SE4C0_14" + ], + [ + "CMT_FIFO_LH5_0", + "CMT_TOP_LH5_13" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "CMT_TOP_ICLK_15" + ], + [ + "CMT_FIFO_L_IMUX16_2", + "CMT_TOP_IMUX16_15" + ], + [ + "CMT_FIFO_SE4C2_1", + "CMT_TOP_SE4C2_14" + ], + [ + "CMT_FIFO_L_IMUX34_2", + "CMT_TOP_IMUX34_15" + ], + [ + "CMT_FIFO_L_BYP2_2", + "CMT_TOP_BYP2_15" + ], + [ + "CMT_FIFO_L_IMUX2_1", + "CMT_TOP_IMUX2_14" + ], + [ + "CMT_FIFO_NW4END1_0", + "CMT_TOP_NW4END1_13" + ], + [ + "CMT_FIFO_L_BYP0_0", + "CMT_TOP_BYP0_13" + ], + [ + "CMT_FIFO_L_IMUX11_2", + "CMT_TOP_IMUX11_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_0", + "CMT_TOP_LOGIC_OUTS_L_B8_13" + ], + [ + "CMT_FIFO_LH1_1", + "CMT_TOP_LH1_14" + ], + [ + "CMT_FIFO_L_IMUX46_2", + "CMT_TOP_IMUX46_15" + ], + [ + "CMT_FIFO_SW4A3_1", + "CMT_TOP_SW4A3_14" + ], + [ + "CMT_FIFO_NE4BEG0_1", + "CMT_TOP_NE4BEG0_14" + ], + [ + "CMT_FIFO_NE4C1_2", + "CMT_TOP_NE4C1_15" + ], + [ + "CMT_FIFO_L_IMUX42_1", + "CMT_TOP_IMUX42_14" + ], + [ + "CMT_FIFO_L_IMUX24_0", + "CMT_TOP_IMUX24_13" + ], + [ + "CMT_FIFO_LH4_1", + "CMT_TOP_LH4_14" + ], + [ + "CMT_FIFO_SW2A0_0", + "CMT_TOP_SW2A0_13" + ], + [ + "CMT_FIFO_NE2A1_0", + "CMT_TOP_NE2A1_13" + ], + [ + "CMT_FIFO_L_IMUX44_1", + "CMT_TOP_IMUX44_14" + ], + [ + "CMT_FIFO_L_IMUX31_2", + "CMT_TOP_IMUX31_15" + ], + [ + "CMT_FIFO_WW2A3_2", + "CMT_TOP_WW2A3_15" + ], + [ + "CMT_FIFO_L_IMUX7_0", + "CMT_TOP_IMUX7_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_1", + "CMT_TOP_LOGIC_OUTS_L_B22_14" + ], + [ + "CMT_FIFO_LH12_1", + "CMT_TOP_LH12_14" + ], + [ + "CMT_FIFO_LH10_2", + "CMT_TOP_LH10_15" + ], + [ + "CMT_FIFO_EE4C2_0", + "CMT_TOP_EE4C2_13" + ], + [ + "CMT_FIFO_WW2A2_2", + "CMT_TOP_WW2A2_15" + ], + [ + "CMT_FIFO_WW2END1_2", + "CMT_TOP_WW2END1_15" + ], + [ + "CMT_FIFO_WW4C3_1", + "CMT_TOP_WW4C3_14" + ], + [ + "CMT_FIFO_NW2A3_1", + "CMT_TOP_NW2A3_14" + ], + [ + "CMT_FIFO_SE2A2_0", + "CMT_TOP_SE2A2_13" + ], + [ + "CMT_FIFO_L_FAN7_1", + "CMT_TOP_FAN7_14" + ], + [ + "CMT_FIFO_L_BYP5_2", + "CMT_TOP_BYP5_15" + ], + [ + "CMT_FIFO_NW4END2_1", + "CMT_TOP_NW4END2_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_0", + "CMT_TOP_LOGIC_OUTS_L_B1_13" + ], + [ + "CMT_FIFO_EE2BEG2_2", + "CMT_TOP_EE2BEG2_15" + ], + [ + "CMT_FIFO_L_IMUX22_1", + "CMT_TOP_IMUX22_14" + ], + [ + "CMT_FIFO_SE4C1_1", + "CMT_TOP_SE4C1_14" + ], + [ + "CMT_FIFO_SE2A3_2", + "CMT_TOP_SE2A3_15" + ], + [ + "CMT_FIFO_L_BYP4_2", + "CMT_TOP_BYP4_15" + ], + [ + "CMT_FIFO_WW4C0_1", + "CMT_TOP_WW4C0_14" + ], + [ + "CMT_FIFO_WL1END0_0", + "CMT_TOP_WL1END0_13" + ], + [ + "CMT_FIFO_WW4END3_1", + "CMT_TOP_WW4END3_14" + ], + [ + "CMT_FIFO_LH9_1", + "CMT_TOP_LH9_14" + ], + [ + "CMT_FIFO_WR1END3_1", + "CMT_TOP_WR1END3_14" + ], + [ + "CMT_FIFO_L_IMUX35_0", + "CMT_TOP_IMUX35_13" + ], + [ + "CMT_FIFO_L_IMUX35_1", + "CMT_TOP_IMUX35_14" + ], + [ + "CMT_FIFO_L_IMUX22_2", + "CMT_TOP_IMUX22_15" + ], + [ + "CMT_FIFO_NE4BEG3_2", + "CMT_TOP_NE4BEG3_15" + ], + [ + "CMT_FIFO_NE2A3_2", + "CMT_TOP_NE2A3_15" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "CMT_TOP_ICLK_13" + ], + [ + "CMT_FIFO_WW4C1_2", + "CMT_TOP_WW4C1_15" + ], + [ + "CMT_FIFO_L_IMUX29_0", + "CMT_TOP_IMUX29_13" + ], + [ + "CMT_FIFO_NW4A0_2", + "CMT_TOP_NW4A0_15" + ], + [ + "CMT_FIFO_EL1BEG1_2", + "CMT_TOP_EL1BEG1_15" + ], + [ + "CMT_FIFO_SW4END3_1", + "CMT_TOP_SW4END3_14" + ], + [ + "CMT_FIFO_SW4A0_0", + "CMT_TOP_SW4A0_13" + ], + [ + "CMT_FIFO_LH5_1", + "CMT_TOP_LH5_14" + ], + [ + "CMT_FIFO_WW4A1_2", + "CMT_TOP_WW4A1_15" + ], + [ + "CMT_FIFO_L_FAN3_1", + "CMT_TOP_FAN3_14" + ], + [ + "CMT_FIFO_L_FAN5_2", + "CMT_TOP_FAN5_15" + ], + [ + "CMT_FIFO_L_CTRL0_0", + "CMT_TOP_CTRL0_13" + ], + [ + "CMT_FIFO_L_IMUX40_1", + "CMT_TOP_IMUX40_14" + ], + [ + "CMT_FIFO_L_BYP4_0", + "CMT_TOP_BYP4_13" + ], + [ + "CMT_FIFO_L_IMUX25_1", + "CMT_TOP_IMUX25_14" + ], + [ + "CMT_FIFO_SE4C2_2", + "CMT_TOP_SE4C2_15" + ], + [ + "CMT_FIFO_L_BYP5_1", + "CMT_TOP_BYP5_14" + ], + [ + "CMT_FIFO_EE2BEG3_2", + "CMT_TOP_EE2BEG3_15" + ], + [ + "CMT_FIFO_ER1BEG3_2", + "CMT_TOP_ER1BEG3_15" + ], + [ + "CMT_FIFO_SW4A3_0", + "CMT_TOP_SW4A3_13" + ], + [ + "CMT_FIFO_L_IMUX20_2", + "CMT_TOP_IMUX20_15" + ], + [ + "CMT_FIFO_L_IMUX39_1", + "CMT_TOP_IMUX39_14" + ], + [ + "CMT_FIFO_L_IMUX30_2", + "CMT_TOP_IMUX30_15" + ], + [ + "CMT_FIFO_SW4A2_1", + "CMT_TOP_SW4A2_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_2", + "CMT_TOP_LOGIC_OUTS_L_B19_15" + ], + [ + "CMT_FIFO_EE4C0_2", + "CMT_TOP_EE4C0_15" + ], + [ + "CMT_FIFO_WW2A0_1", + "CMT_TOP_WW2A0_14" + ], + [ + "CMT_FIFO_L_FAN7_0", + "CMT_TOP_FAN7_13" + ], + [ + "CMT_FIFO_EE4A3_0", + "CMT_TOP_EE4A3_13" + ], + [ + "CMT_FIFO_EE4B1_0", + "CMT_TOP_EE4B1_13" + ], + [ + "CMT_FIFO_EE4B0_1", + "CMT_TOP_EE4B0_14" + ], + [ + "CMT_FIFO_WW4END1_0", + "CMT_TOP_WW4END1_13" + ], + [ + "CMT_FIFO_L_IMUX4_1", + "CMT_TOP_IMUX4_14" + ], + [ + "CMT_FIFO_SW4A3_2", + "CMT_TOP_SW4A3_15" + ], + [ + "CMT_FIFO_SW2A1_2", + "CMT_TOP_SW2A1_15" + ], + [ + "CMT_FIFO_LH3_0", + "CMT_TOP_LH3_13" + ], + [ + "CMT_FIFO_EE4BEG0_0", + "CMT_TOP_EE4BEG0_13" + ], + [ + "CMT_FIFO_NW4A2_2", + "CMT_TOP_NW4A2_15" + ], + [ + "CMT_FIFO_L_IMUX10_0", + "CMT_TOP_IMUX10_13" + ], + [ + "CMT_FIFO_SE2A3_0", + "CMT_TOP_SE2A3_13" + ], + [ + "CMT_FIFO_WW4END3_0", + "CMT_TOP_WW4END3_13" + ], + [ + "CMT_FIFO_EE2A3_2", + "CMT_TOP_EE2A3_15" + ], + [ + "CMT_FIFO_NE2A1_2", + "CMT_TOP_NE2A1_15" + ], + [ + "CMT_FIFO_WW4C3_2", + "CMT_TOP_WW4C3_15" + ], + [ + "CMT_FIFO_EE2A3_1", + "CMT_TOP_EE2A3_14" + ], + [ + "CMT_FIFO_SW2A0_1", + "CMT_TOP_SW2A0_14" + ], + [ + "CMT_FIFO_WL1END3_1", + "CMT_TOP_WL1END3_14" + ], + [ + "CMT_FIFO_WW2END0_0", + "CMT_TOP_WW2END0_13" + ], + [ + "CMT_FIFO_NE4C3_1", + "CMT_TOP_NE4C3_14" + ], + [ + "CMT_FIFO_WW4END2_0", + "CMT_TOP_WW4END2_13" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "CMT_TOP_ICLKDIV_14" + ], + [ + "CMT_FIFO_L_IMUX38_2", + "CMT_TOP_IMUX38_15" + ], + [ + "CMT_FIFO_L_IMUX15_2", + "CMT_TOP_IMUX15_15" + ], + [ + "CMT_FIFO_L_BYP0_2", + "CMT_TOP_BYP0_15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_0", + "CMT_TOP_LOGIC_OUTS_L_B11_13" + ], + [ + "CMT_FIFO_NE4BEG2_1", + "CMT_TOP_NE4BEG2_14" + ], + [ + "CMT_FIFO_EE4BEG3_1", + "CMT_TOP_EE4BEG3_14" + ], + [ + "CMT_FIFO_EE4B3_0", + "CMT_TOP_EE4B3_13" + ], + [ + "CMT_FIFO_L_CLK1_0", + "CMT_TOP_CLK1_13" + ], + [ + "CMT_FIFO_WW4B0_0", + "CMT_TOP_WW4B0_13" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "CMT_TOP_ICLKDIV_15" + ], + [ + "CMT_FIFO_ER1BEG2_2", + "CMT_TOP_ER1BEG2_15" + ], + [ + "CMT_FIFO_L_IMUX43_1", + "CMT_TOP_IMUX43_14" + ], + [ + "CMT_FIFO_L_BYP3_2", + "CMT_TOP_BYP3_15" + ], + [ + "CMT_FIFO_WR1END2_2", + "CMT_TOP_WR1END2_15" + ], + [ + "CMT_FIFO_EE2BEG1_1", + "CMT_TOP_EE2BEG1_14" + ], + [ + "CMT_FIFO_L_FAN1_0", + "CMT_TOP_FAN1_13" + ], + [ + "CMT_FIFO_L_IMUX19_0", + "CMT_TOP_IMUX19_13" + ], + [ + "CMT_FIFO_L_IMUX30_0", + "CMT_TOP_IMUX30_13" + ], + [ + "CMT_FIFO_WW4END0_1", + "CMT_TOP_WW4END0_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_1", + "CMT_TOP_LOGIC_OUTS_L_B8_14" + ], + [ + "CMT_FIFO_LH4_0", + "CMT_TOP_LH4_13" + ], + [ + "CMT_FIFO_L_IMUX41_0", + "CMT_TOP_IMUX41_13" + ], + [ + "CMT_FIFO_L_IMUX37_0", + "CMT_TOP_IMUX37_13" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "CMT_TOP_OCLK_13" + ], + [ + "CMT_FIFO_ER1BEG3_1", + "CMT_TOP_ER1BEG3_14" + ], + [ + "CMT_FIFO_L_IMUX34_1", + "CMT_TOP_IMUX34_14" + ], + [ + "CMT_FIFO_L_IMUX5_0", + "CMT_TOP_IMUX5_13" + ], + [ + "CMT_FIFO_SW2A3_0", + "CMT_TOP_SW2A3_13" + ], + [ + "CMT_FIFO_L_IMUX13_1", + "CMT_TOP_IMUX13_14" + ], + [ + "CMT_FIFO_SW2A1_0", + "CMT_TOP_SW2A1_13" + ], + [ + "CMT_FIFO_L_IMUX46_0", + "CMT_TOP_IMUX46_13" + ], + [ + "CMT_FIFO_EE2BEG1_0", + "CMT_TOP_EE2BEG1_13" + ], + [ + "CMT_FIFO_LH9_0", + "CMT_TOP_LH9_13" + ], + [ + "CMT_FIFO_WW4B1_0", + "CMT_TOP_WW4B1_13" + ], + [ + "CMT_FIFO_SE2A1_2", + "CMT_TOP_SE2A1_15" + ], + [ + "CMT_FIFO_LH3_2", + "CMT_TOP_LH3_15" + ], + [ + "CMT_FIFO_L_IMUX9_2", + "CMT_TOP_IMUX9_15" + ], + [ + "CMT_FIFO_L_IMUX12_1", + "CMT_TOP_IMUX12_14" + ], + [ + "CMT_FIFO_NE2A0_1", + "CMT_TOP_NE2A0_14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_1", + "CMT_TOP_LOGIC_OUTS_L_B12_14" + ], + [ + "CMT_FIFO_WW4A0_2", + "CMT_TOP_WW4A0_15" + ], + [ + "CMT_FIFO_NW4A1_1", + "CMT_TOP_NW4A1_14" + ], + [ + "CMT_FIFO_SE2A0_0", + "CMT_TOP_SE2A0_13" + ], + [ + "CMT_FIFO_LH10_0", + "CMT_TOP_LH10_13" + ], + [ + "CMT_FIFO_L_IMUX14_0", + "CMT_TOP_IMUX14_13" + ], + [ + "CMT_FIFO_LH8_1", + "CMT_TOP_LH8_14" + ], + [ + "CMT_FIFO_NW2A3_2", + "CMT_TOP_NW2A3_15" + ], + [ + "CMT_FIFO_ER1BEG2_0", + "CMT_TOP_ER1BEG2_13" + ], + [ + "CMT_FIFO_WW4END0_0", + "CMT_TOP_WW4END0_13" + ], + [ + "CMT_FIFO_L_FAN5_0", + "CMT_TOP_FAN5_13" + ], + [ + "CMT_FIFO_L_FAN0_0", + "CMT_TOP_FAN0_13" + ], + [ + "CMT_FIFO_EL1BEG3_0", + "CMT_TOP_EL1BEG3_13" + ], + [ + "CMT_FIFO_L_IMUX44_0", + "CMT_TOP_IMUX44_13" + ], + [ + "CMT_FIFO_L_FAN2_2", + "CMT_TOP_FAN2_15" + ], + [ + "CMT_FIFO_WW4END3_2", + "CMT_TOP_WW4END3_15" + ], + [ + "CMT_FIFO_LH6_2", + "CMT_TOP_LH6_15" + ], + [ + "CMT_FIFO_L_BYP7_1", + "CMT_TOP_BYP7_14" + ], + [ + "CMT_FIFO_L_CLK0_0", + "CMT_TOP_CLK0_13" + ], + [ + "CMT_FIFO_L_IMUX36_2", + "CMT_TOP_IMUX36_15" + ], + [ + "CMT_FIFO_L_IMUX4_0", + "CMT_TOP_IMUX4_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_0", + "CMT_TOP_LOGIC_OUTS_L_B22_13" + ], + [ + "CMT_FIFO_L_IMUX14_1", + "CMT_TOP_IMUX14_14" + ], + [ + "CMT_FIFO_L_IMUX5_1", + "CMT_TOP_IMUX5_14" + ], + [ + "CMT_FIFO_EE4C3_1", + "CMT_TOP_EE4C3_14" + ], + [ + "CMT_FIFO_L_IMUX21_2", + "CMT_TOP_IMUX21_15" + ], + [ + "CMT_FIFO_L_IMUX10_1", + "CMT_TOP_IMUX10_14" + ], + [ + "CMT_FIFO_L_IMUX17_1", + "CMT_TOP_IMUX17_14" + ], + [ + "CMT_FIFO_L_IMUX23_1", + "CMT_TOP_IMUX23_14" + ], + [ + "CMT_FIFO_NW2A0_0", + "CMT_TOP_NW2A0_13" + ], + [ + "CMT_FIFO_EE2BEG3_0", + "CMT_TOP_EE2BEG3_13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_2", + "CMT_TOP_LOGIC_OUTS_L_B0_15" + ], + [ + "CMT_FIFO_EL1BEG3_1", + "CMT_TOP_EL1BEG3_14" + ], + [ + "CMT_FIFO_EE4C3_0", + "CMT_TOP_EE4C3_13" + ], + [ + "CMT_FIFO_WW4B2_1", + "CMT_TOP_WW4B2_14" + ], + [ + "CMT_FIFO_L_FAN2_0", + "CMT_TOP_FAN2_13" + ], + [ + "CMT_FIFO_L_IMUX37_2", + "CMT_TOP_IMUX37_15" + ], + [ + "CMT_FIFO_L_IMUX42_0", + "CMT_TOP_IMUX42_13" + ], + [ + "CMT_FIFO_EL1BEG2_2", + "CMT_TOP_EL1BEG2_15" + ], + [ + "CMT_FIFO_L_IMUX18_0", + "CMT_TOP_IMUX18_13" + ], + [ + "CMT_FIFO_ER1BEG2_1", + "CMT_TOP_ER1BEG2_14" + ], + [ + "CMT_FIFO_EE4C2_1", + "CMT_TOP_EE4C2_14" + ], + [ + "CMT_FIFO_L_IMUX28_0", + "CMT_TOP_IMUX28_13" + ], + [ + "CMT_FIFO_EE2A1_1", + "CMT_TOP_EE2A1_14" + ], + [ + "CMT_FIFO_L_BYP4_1", + "CMT_TOP_BYP4_14" + ], + [ + "CMT_FIFO_ER1BEG0_1", + "CMT_TOP_ER1BEG0_14" + ], + [ + "CMT_FIFO_L_FAN4_0", + "CMT_TOP_FAN4_13" + ], + [ + "CMT_FIFO_NW4END1_2", + "CMT_TOP_NW4END1_15" + ], + [ + "CMT_FIFO_WL1END2_2", + "CMT_TOP_WL1END2_15" + ], + [ + "CMT_FIFO_NW4A2_0", + "CMT_TOP_NW4A2_13" + ], + [ + "CMT_FIFO_L_BYP6_0", + "CMT_TOP_BYP6_13" + ], + [ + "CMT_FIFO_L_IMUX4_2", + "CMT_TOP_IMUX4_15" + ], + [ + "CMT_FIFO_L_IMUX26_2", + "CMT_TOP_IMUX26_15" + ], + [ + "CMT_FIFO_NW2A1_0", + "CMT_TOP_NW2A1_13" + ], + [ + "CMT_FIFO_EE2BEG0_2", + "CMT_TOP_EE2BEG0_15" + ], + [ + "CMT_FIFO_L_CLK0_1", + "CMT_TOP_CLK0_14" + ], + [ + "CMT_FIFO_WW2END3_0", + "CMT_TOP_WW2END3_13" + ], + [ + "CMT_FIFO_WW2A0_0", + "CMT_TOP_WW2A0_13" + ], + [ + "CMT_FIFO_SW4END2_1", + "CMT_TOP_SW4END2_14" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "CMT_TOP_L_LOWER_B" + ] + }, + { + "grid_deltas": [ + 1, + 9 + ], + "wire_pairs": [ + [ + "CFG_CENTER_NW4A1_1", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_WW4A1_1", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_IMUX3_1", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_SW4END0_1", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_WW2A3_1", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_BYP1_1", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW2END3_1", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_SE2A2_1", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_LH4_1", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_CTRL0_1", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX10_1", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_FAN2_1", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_EE4B2_1", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX31_1", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_EE4C3_1", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_WW4B2_1", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_LH3_1", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX46_1", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW2A2_1", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_EE4A1_1", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_WW2END0_1", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_NW4END3_1", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_EE2BEG3_1", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX33_1", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_WW2END1_1", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_ER1BEG2_1", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX5_1", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WR1END3_1", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX32_1", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_IMUX17_1", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_NW4END2_1", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_IMUX22_1", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX24_1", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_BYP2_1", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_IMUX38_1", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX21_1", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_WL1END3_1", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_NE2A1_1", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_BYP6_1", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_LH7_1", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_SE2A3_1", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_FAN5_1", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_IMUX37_1", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_IMUX42_1", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX13_1", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_FAN7_1", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_ER1BEG1_1", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SW2A1_1", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_LH2_1", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_SW4A0_1", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_EE4BEG1_1", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG0_1", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_SW4END1_1", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_IMUX23_1", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WR1END0_1", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_WR1END1_1", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NE4BEG0_1", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_SW2A2_1", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_WW4B0_1", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_LH9_1", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_NE4C0_1", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_SE2A0_1", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_SE4BEG2_1", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE2A3_1", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NW2A0_1", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_NE4C1_1", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_BYP4_1", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WW4END2_1", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_WW4C1_1", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_SW4A1_1", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_IMUX41_1", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_NW4A2_1", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_EE2A2_1", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_IMUX35_1", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_NE2A2_1", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE4BEG0_1", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_NW2A3_1", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NE2A0_1", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_BYP0_1", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX34_1", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_WW4C2_1", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX18_1", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_EL1BEG0_1", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_LH11_1", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_WW4END1_1", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_EE4A0_1", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_IMUX47_1", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX43_1", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_SW4A2_1", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_WL1END1_1", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_NW4A0_1", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX20_1", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SE4BEG1_1", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_BYP5_1", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_SE4BEG3_1", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_WW4A0_1", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX12_1", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX4_1", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_EE4B0_1", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_CLK1_1", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX7_1", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_IMUX6_1", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_NE4BEG2_1", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW4END3_1", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX2_1", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_WW4C3_1", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_WR1END2_1", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_EE4C0_1", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_WW4END0_1", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_FAN1_1", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX1_1", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_SW4A3_1", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_IMUX36_1", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_EE4A2_1", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_SE4C0_1", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_NW2A1_1", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_ER1BEG3_1", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_SW4END2_1", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_WL1END0_1", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_SW2A3_1", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_EE2BEG2_1", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_EE2BEG0_1", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX9_1", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_EL1BEG3_1", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW4A3_1", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_IMUX11_1", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_NE4BEG1_1", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX29_1", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_FAN6_1", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_EE4A3_1", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_NE4C2_1", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_BYP3_1", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_IMUX14_1", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_IMUX0_1", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_EE4BEG3_1", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_SW4END3_1", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_NE4BEG3_1", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX25_1", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_FAN3_1", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_EE2A0_1", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_ER1BEG0_1", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_WL1END2_1", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WW2A1_1", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_SE4C2_1", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_LH10_1", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_FAN0_1", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_EE4C1_1", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX16_1", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WW4A2_1", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_NW4END1_1", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SE4C1_1", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX39_1", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_CTRL1_1", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_LH6_1", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_EL1BEG1_1", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_IMUX28_1", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX44_1", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_EE4B1_1", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_WW2END2_1", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_WW4C0_1", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_EE2A1_1", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX15_1", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_NW4A3_1", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SE2A1_1", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_SW2A0_1", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_LH5_1", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX45_1", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX27_1", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_NW4END0_1", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_BYP7_1", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_IMUX26_1", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_CLK0_1", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_WW4B3_1", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_IMUX30_1", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_IMUX40_1", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_EE2BEG1_1", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_NE4C3_1", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_LH12_1", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_LH8_1", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_NE2A3_1", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_NW2A2_1", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW4B1_1", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_LH1_1", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_EE4C2_1", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_EL1BEG2_1", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_FAN4_1", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW2A0_1", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_IMUX8_1", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_SE4C3_1", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX19_1", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_EE4BEG2_1", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE4B3_1", + "VFRAME_EE4B3" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 5, + 10 + ], + "wire_pairs": [ + [ + "PCIE_LOGIC_OUTS_B2_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_EE4B0_0", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_NE4BEG1_0", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX36_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_IMUX39_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_WW2A2_0", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_IMUX5_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_NW2A0_0", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_NW4END1_0", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_SE2A2_0", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_NE4C1_0", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_IMUX8_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_SE4C2_0", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_IMUX31_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_WL1END2_0", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_EE4BEG0_0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_WW4B2_0", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_WW4END2_0", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_WW4END0_0", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_LH8_0", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_CTRL1_L_0", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_WR1END2_0", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_IMUX23_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_NE2A2_0", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_WW2END3_0", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_NE2A3_0", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_WW4END1_0", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_SW4A2_0", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_EL1BEG0_0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_IMUX20_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_LH2_0", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_IMUX33_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_WW4C3_0", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_SW4END3_0", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_BYP0_L_0", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_LH5_0", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_IMUX16_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_WL1END0_0", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_FAN6_L_0", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_EE4B3_0", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_SE4BEG0_0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_BYP5_L_0", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_SW2A3_0", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX15_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_WW4A3_0", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_WW4B0_0", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_IMUX6_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_EE4C2_0", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_EE2BEG2_0", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_IMUX25_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_NE4BEG3_0", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_LH3_0", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_EE2BEG0_0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_EE2BEG3_0", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_IMUX4_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_EE4C1_0", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_WW2A0_0", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_LH4_0", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_WR1END3_0", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_NE4C3_0", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_IMUX14_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_NW4END2_0", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_ER1BEG1_0", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_IMUX34_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_FAN3_L_0", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_WW4C2_0", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_NE2A1_0", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_IMUX42_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_EL1BEG3_0", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_IMUX21_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_EE4B2_0", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_SE4BEG2_0", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_WW4A2_0", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_SW4A1_0", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_WL1END1_0", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_WW2A1_0", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_SW2A2_0", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_WW4C0_0", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_EE4B1_0", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_SW4A0_0", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_CLK1_L_0", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_NW4A0_0", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WR1END1_0", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_FAN7_L_0", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_SE4C0_0", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_EE4C3_0", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_WW4B3_0", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_WW4A0_0", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_EE4A0_0", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_IMUX35_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_IMUX38_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_EE4BEG2_0", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX40_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_NE2A0_0", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_IMUX27_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_CLK0_L_0", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_IMUX41_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_FAN1_L_0", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_WW4B1_0", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_FAN4_L_0", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_EE2A1_0", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_CTRL0_L_0", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_EE2A2_0", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_NW4END0_0", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_LH9_0", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_WL1END3_0", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_IMUX44_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_BYP2_L_0", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_FAN5_L_0", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_SW4END0_0", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_NW4END3_0", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_WW2END0_0", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_IMUX45_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_IMUX30_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_NE4C0_0", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_IMUX28_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_EE2A3_0", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_NW2A2_0", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_ER1BEG3_0", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_EE4A1_0", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_SE2A0_0", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_EE4BEG3_0", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_IMUX26_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_FAN0_L_0", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_SW2A0_0", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX0_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_IMUX19_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_IMUX11_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_FAN2_L_0", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_SE2A1_0", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_EE4C0_0", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX1_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_IMUX43_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_LH1_0", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_IMUX3_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_IMUX12_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_LH7_0", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_SE4C3_0", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_SE4C1_0", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_SE4BEG3_0", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_NW4A3_0", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_LH10_0", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_WW4A1_0", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_WW2A3_0", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_NW4A1_0", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_EE2A0_0", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_BYP3_L_0", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_EE2BEG1_0", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_IMUX32_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_BYP6_L_0", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_SW4END1_0", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_IMUX13_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_EL1BEG1_0", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_IMUX9_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_ER1BEG0_0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_NE4BEG0_0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_SE4BEG1_0", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_WW2END1_0", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_IMUX24_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_SW4A3_0", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_NW2A1_0", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_IMUX46_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_IMUX29_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_WW4END3_0", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_ER1BEG2_0", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_LH11_0", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_IMUX10_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_IMUX17_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_EL1BEG2_0", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_LH12_0", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_IMUX18_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_IMUX47_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_WW4C1_0", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_NE4BEG2_0", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_BYP4_L_0", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_LH6_0", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_NE4C2_0", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_BYP1_L_0", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_SE2A3_0", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_SW2A1_0", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_BYP7_L_0", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_IMUX2_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_WR1END0_0", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_NW4A2_0", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_IMUX7_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_EE4A2_0", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_IMUX37_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_SW4END2_0", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_EE4BEG1_0", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_0", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_IMUX22_L_0", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_WW2END2_0", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_EE4A3_0", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_NW2A3_0", + "INT_INTERFACE_NW2A3" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE2A3_6", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NE4C2_6", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_LH4_6", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_WW2END3_6", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_LH8_6", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW2A0_6", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_EE4A1_6", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NW4A1_6", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SE2A1_6", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WL1END3_6", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4A2_6", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_WW4B3_6", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_LH3_6", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_EE2A1_6", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_SW2A2_6", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WR1END2_6", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_SW2A3_6", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NE4BEG3_6", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW2END2_6", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SE4BEG2_6", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW2END1_6", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_NW4END3_6", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_ER1BEG1_6", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SW4END1_6", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EL1BEG2_6", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_EL1BEG3_6", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WW4A2_6", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE4BEG1_6", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_NW4END0_6", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_EE2BEG0_6", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WL1END2_6", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SW4END3_6", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NE2A3_6", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_EE4BEG0_6", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NE4BEG0_6", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NW4END2_6", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4C1_6", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_WR1END1_6", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SW4A3_6", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE4A0_6", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4BEG3_6", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG0_6", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_NW2A1_6", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SE4C3_6", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_LH6_6", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_LH12_6", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WR1END3_6", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_WW4B0_6", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_EE4C0_6", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EL1BEG1_6", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW4A0_6", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_LH7_6", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_EE4C2_6", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_WW2A2_6", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WW4C0_6", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NW4A2_6", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_LH5_6", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_SW2A1_6", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_NW4A0_6", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_ER1BEG0_6", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_WW2END0_6", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_SW4END2_6", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_LH9_6", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NE4C1_6", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE2A2_6", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_SE4C2_6", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_NE2A1_6", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NW2A2_6", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_SW4A1_6", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_EE4B0_6", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WW4A3_6", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_WW4A1_6", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_ER1BEG3_6", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_EE4BEG2_6", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_NW2A0_6", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WW4END2_6", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_EE4C3_6", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW4C3_6", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WR1END0_6", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_WW4B1_6", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_LH10_6", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WL1END1_6", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_EE4B3_6", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NE2A0_6", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_NW4A3_6", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WW4END0_6", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WL1END0_6", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_NE4C0_6", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_SW2A0_6", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_SE4BEG1_6", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG3_6", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_NW4END1_6", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_EE2A2_6", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_SE4C1_6", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_ER1BEG2_6", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_NE4C3_6", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_LH11_6", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_SE4BEG0_6", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_WW4END1_6", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE4B2_6", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE2BEG3_6", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_WW4B2_6", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_SE2A3_6", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SW4A2_6", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_EE4A3_6", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_NE4BEG2_6", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_LH1_6", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_EE2BEG2_6", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_SE2A0_6", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE4C1_6", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE2A0_6", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW2A3_6", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_SE2A2_6", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4B1_6", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NE4BEG1_6", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WW4C2_6", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_SE4C0_6", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_EE2BEG1_6", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NW2A3_6", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_LH2_6", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_SW4END0_6", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WW4END3_6", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW2A1_6", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_SW4A0_6", + "INT_FEEDTHRU_2_SW4A0" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "HCLK_LV11", + "LV12" + ], + [ + "HCLK_NW6A0", + "NW6B0" + ], + [ + "HCLK_LV12", + "LV13" + ], + [ + "HCLK_NW6END_S0_0", + "NW6END0" + ], + [ + "HCLK_SS2END2", + "SS2A2" + ], + [ + "HCLK_LV0", + "LV1" + ], + [ + "HCLK_SW6B1", + "SW6A1" + ], + [ + "HCLK_NE6D2", + "NE6E2" + ], + [ + "HCLK_NE6B0", + "NE6C0" + ], + [ + "HCLK_SW6B0", + "SW6A0" + ], + [ + "HCLK_NW2END_S0_0", + "NW2END0" + ], + [ + "HCLK_LVB5", + "LVB5" + ], + [ + "HCLK_NL1BEG1", + "NL1END1" + ], + [ + "HCLK_NW6D2", + "NW6E2" + ], + [ + "HCLK_SE6B0", + "SE6A0" + ], + [ + "HCLK_NE6C3", + "NE6D3" + ], + [ + "HCLK_SE6D2", + "SE6C2" + ], + [ + "HCLK_SS6C1", + "SS6B1" + ], + [ + "HCLK_NN6D3", + "NN6E3" + ], + [ + "HCLK_SW6D0", + "SW6C0" + ], + [ + "HCLK_SS6C3", + "SS6B3" + ], + [ + "HCLK_WW4END_S0_0", + "WW4END0" + ], + [ + "HCLK_NN6END_S1_0", + "NN6END0" + ], + [ + "HCLK_SS6B1", + "SS6A1" + ], + [ + "HCLK_NE6A3", + "NE6B3" + ], + [ + "HCLK_WR1END_S1_0", + "WR1END0" + ], + [ + "HCLK_NN6C0", + "NN6D0" + ], + [ + "HCLK_SS2END1", + "SS2A1" + ], + [ + "HCLK_SR1BEG3", + "SR1BEG3" + ], + [ + "HCLK_SR1END_N3_3", + "SR1END_N3_3" + ], + [ + "HCLK_LVB8", + "LVB8" + ], + [ + "HCLK_LV17", + "LV18" + ], + [ + "HCLK_LV4", + "LV5" + ], + [ + "HCLK_SW6E2", + "SW6D2" + ], + [ + "HCLK_SE6E1", + "SE6D1" + ], + [ + "HCLK_LV9", + "LV10" + ], + [ + "HCLK_NW6B1", + "NW6C1" + ], + [ + "HCLK_SL1END2", + "SL1BEG2" + ], + [ + "HCLK_BYP_BOUNCE3", + "BYP_BOUNCE_N3_3" + ], + [ + "HCLK_FAN_BOUNCE_S3_6", + "FAN_BOUNCE6" + ], + [ + "HCLK_NL1BEG2", + "NL1END2" + ], + [ + "HCLK_NW6A3", + "NW6B3" + ], + [ + "HCLK_SW6C1", + "SW6B1" + ], + [ + "HCLK_SS6C0", + "SS6B0" + ], + [ + "HCLK_LVB9", + "LVB9" + ], + [ + "HCLK_SW6E1", + "SW6D1" + ], + [ + "HCLK_SS6D2", + "SS6C2" + ], + [ + "HCLK_FAN_BOUNCE_S3_2", + "FAN_BOUNCE2" + ], + [ + "HCLK_NE6B3", + "NE6C3" + ], + [ + "HCLK_NE6D3", + "NE6E3" + ], + [ + "HCLK_SS6A1", + "SS6BEG1" + ], + [ + "HCLK_EL1BEG3", + "EL1BEG_N3" + ], + [ + "HCLK_SW6C0", + "SW6B0" + ], + [ + "HCLK_SE6B3", + "SE6A3" + ], + [ + "HCLK_LVB10", + "LVB10" + ], + [ + "HCLK_NW2A1", + "NW2A1" + ], + [ + "HCLK_SS6C2", + "SS6B2" + ], + [ + "HCLK_NN6BEG0", + "NN6A0" + ], + [ + "HCLK_NW2A3", + "NW2A3" + ], + [ + "HCLK_SS6END1", + "SS6E1" + ], + [ + "HCLK_SR1END1", + "SR1BEG1" + ], + [ + "HCLK_SS2A0", + "SS2BEG0" + ], + [ + "HCLK_WL1END3", + "WL1END_N1_3" + ], + [ + "HCLK_EL1END_S3_0", + "EL1END0" + ], + [ + "HCLK_NE6A0", + "NE6B0" + ], + [ + "HCLK_NN2A3", + "NN2END3" + ], + [ + "HCLK_SS6END3", + "SS6E3" + ], + [ + "HCLK_SW6D3", + "SW6C3" + ], + [ + "HCLK_SE6E3", + "SE6D3" + ], + [ + "HCLK_NN6D1", + "NN6E1" + ], + [ + "HCLK_NN2A2", + "NN2END2" + ], + [ + "HCLK_LV1", + "LV2" + ], + [ + "HCLK_NN6E0", + "NN6END0" + ], + [ + "HCLK_WW2END3", + "WW2END_N0_3" + ], + [ + "HCLK_SW6E3", + "SW6D3" + ], + [ + "HCLK_NE6A2", + "NE6B2" + ], + [ + "HCLK_SW6D1", + "SW6C1" + ], + [ + "HCLK_NE2BEG2", + "NE2A2" + ], + [ + "HCLK_SE6B1", + "SE6A1" + ], + [ + "HCLK_LVB1", + "LVB1" + ], + [ + "HCLK_NW6C3", + "NW6D3" + ], + [ + "HCLK_SS2BEG3", + "SS2BEG3" + ], + [ + "HCLK_NE6C2", + "NE6D2" + ], + [ + "HCLK_NW6D1", + "NW6E1" + ], + [ + "HCLK_NN6BEG1", + "NN6A1" + ], + [ + "HCLK_LV16", + "LV17" + ], + [ + "HCLK_SW2END2", + "SW2BEG2" + ], + [ + "HCLK_WL1BEG3", + "WL1BEG_N3" + ], + [ + "HCLK_NN6C2", + "NN6D2" + ], + [ + "HCLK_SS6D3", + "SS6C3" + ], + [ + "HCLK_LV5", + "LV6" + ], + [ + "HCLK_LEAF_CLK_B_TOP1", + "GCLK_B1" + ], + [ + "HCLK_NN6B3", + "NN6C3" + ], + [ + "HCLK_LV10", + "LV11" + ], + [ + "HCLK_NW6B2", + "NW6C2" + ], + [ + "HCLK_SW2END_N0_3", + "SW2END_N0_3" + ], + [ + "HCLK_NN6BEG3", + "NN6A3" + ], + [ + "HCLK_SS6A0", + "SS6BEG0" + ], + [ + "HCLK_LV2", + "LV3" + ], + [ + "HCLK_NW6A1", + "NW6B1" + ], + [ + "HCLK_SW6END3", + "SW6END_N0_3" + ], + [ + "HCLK_NN6A1", + "NN6B1" + ], + [ + "HCLK_WR1BEG_S0", + "WR1BEG0" + ], + [ + "HCLK_NN6BEG2", + "NN6A2" + ], + [ + "HCLK_NN6B1", + "NN6C1" + ], + [ + "HCLK_LV8", + "LV9" + ], + [ + "HCLK_NN2BEG1", + "NN2A1" + ], + [ + "HCLK_LV6", + "LV7" + ], + [ + "HCLK_NE6C0", + "NE6D0" + ], + [ + "HCLK_NN2A1", + "NN2END1" + ], + [ + "HCLK_SS6E1", + "SS6D1" + ], + [ + "HCLK_LEAF_CLK_B_TOP3", + "GCLK_B3" + ], + [ + "HCLK_NN2END_S2_0", + "NN2END0" + ], + [ + "HCLK_SW2END0", + "SW2BEG0" + ], + [ + "HCLK_ER1BEG_S0", + "ER1BEG0" + ], + [ + "HCLK_SS2END0", + "SS2A0" + ], + [ + "HCLK_SW2END1", + "SW2BEG1" + ], + [ + "HCLK_NE6D0", + "NE6E0" + ], + [ + "HCLK_LEAF_CLK_B_TOP0", + "GCLK_B0" + ], + [ + "HCLK_NN6C3", + "NN6D3" + ], + [ + "HCLK_BYP_BOUNCE7", + "BYP_BOUNCE_N3_7" + ], + [ + "HCLK_NN6B0", + "NN6C0" + ], + [ + "HCLK_SW6C2", + "SW6B2" + ], + [ + "HCLK_SS6E2", + "SS6D2" + ], + [ + "HCLK_NE6D1", + "NE6E1" + ], + [ + "HCLK_SE6D0", + "SE6C0" + ], + [ + "HCLK_NW2A0", + "NW2A0" + ], + [ + "HCLK_NW6C0", + "NW6D0" + ], + [ + "HCLK_SE6C1", + "SE6B1" + ], + [ + "HCLK_SS2A1", + "SS2BEG1" + ], + [ + "HCLK_SE2A1", + "SE2BEG1" + ], + [ + "HCLK_LVB4", + "LVB4" + ], + [ + "HCLK_LVB12", + "LVB12" + ], + [ + "HCLK_LV13", + "LV14" + ], + [ + "HCLK_NW6B0", + "NW6C0" + ], + [ + "HCLK_SE6D3", + "SE6C3" + ], + [ + "HCLK_NN6E2", + "NN6END2" + ], + [ + "HCLK_NN2BEG2", + "NN2A2" + ], + [ + "HCLK_SS6B3", + "SS6A3" + ], + [ + "HCLK_NR1BEG2", + "NR1END2" + ], + [ + "HCLK_NN6A3", + "NN6B3" + ], + [ + "HCLK_LV7", + "LV8" + ], + [ + "HCLK_BYP_BOUNCE6", + "BYP_BOUNCE_N3_6" + ], + [ + "HCLK_SS6A2", + "SS6BEG2" + ], + [ + "HCLK_SW6D2", + "SW6C2" + ], + [ + "HCLK_SW6C3", + "SW6B3" + ], + [ + "HCLK_LV14", + "LV15" + ], + [ + "HCLK_LV15", + "LV16" + ], + [ + "HCLK_SS6END0", + "SS6E0" + ], + [ + "HCLK_SS2END_N0_3", + "SS2END_N0_3" + ], + [ + "HCLK_SE6C2", + "SE6B2" + ], + [ + "HCLK_SW6B3", + "SW6A3" + ], + [ + "HCLK_LEAF_CLK_B_TOP2", + "GCLK_B2" + ], + [ + "HCLK_NE2END_S3_0", + "NE2END0" + ], + [ + "HCLK_SS6B0", + "SS6A0" + ], + [ + "HCLK_NE2BEG0", + "NE2A0" + ], + [ + "HCLK_NN6A2", + "NN6B2" + ], + [ + "HCLK_NW6D0", + "NW6E0" + ], + [ + "HCLK_LEAF_CLK_B_TOP4", + "GCLK_B4" + ], + [ + "HCLK_SE6E2", + "SE6D2" + ], + [ + "HCLK_NN2A0", + "NN2END0" + ], + [ + "HCLK_NN2BEG3", + "NN2A3" + ], + [ + "HCLK_NN2BEG0", + "NN2A0" + ], + [ + "HCLK_SR1END2", + "SR1BEG2" + ], + [ + "HCLK_NW6C1", + "NW6D1" + ], + [ + "HCLK_NW6B3", + "NW6C3" + ], + [ + "HCLK_SS6D1", + "SS6C1" + ], + [ + "HCLK_LVB11", + "LVB11" + ], + [ + "HCLK_FAN_BOUNCE_S3_4", + "FAN_BOUNCE4" + ], + [ + "HCLK_NN6C1", + "NN6D1" + ], + [ + "HCLK_BYP_BOUNCE2", + "BYP_BOUNCE_N3_2" + ], + [ + "HCLK_SE6B2", + "SE6A2" + ], + [ + "HCLK_LEAF_CLK_B_TOP5", + "GCLK_B5" + ], + [ + "HCLK_NE6A1", + "NE6B1" + ], + [ + "HCLK_SW6B2", + "SW6A2" + ], + [ + "HCLK_SS6B2", + "SS6A2" + ], + [ + "HCLK_LV3", + "LV4" + ], + [ + "HCLK_SE6C3", + "SE6B3" + ], + [ + "HCLK_NW6A2", + "NW6B2" + ], + [ + "HCLK_FAN_BOUNCE_S3_0", + "FAN_BOUNCE0" + ], + [ + "HCLK_NN6E3", + "NN6END3" + ], + [ + "HCLK_SW6E0", + "SW6D0" + ], + [ + "HCLK_SS6END_N0_3", + "SS6END_N0_3" + ], + [ + "HCLK_NR1BEG1", + "NR1END1" + ], + [ + "HCLK_NR1BEG0", + "NR1END0" + ], + [ + "HCLK_NN6B2", + "NN6C2" + ], + [ + "HCLK_SL1END3", + "SL1BEG3" + ], + [ + "HCLK_SS6E0", + "SS6D0" + ], + [ + "HCLK_SS6D0", + "SS6C0" + ], + [ + "HCLK_SS2A3", + "SS2A3" + ], + [ + "HCLK_SS6A3", + "SS6BEG3" + ], + [ + "HCLK_LVB6", + "LVB6" + ], + [ + "HCLK_SS6END2", + "SS6E2" + ], + [ + "HCLK_SE6E0", + "SE6D0" + ], + [ + "HCLK_NW2A2", + "NW2A2" + ], + [ + "HCLK_NE6B1", + "NE6C1" + ], + [ + "HCLK_NW6C2", + "NW6D2" + ], + [ + "HCLK_NE6B2", + "NE6C2" + ], + [ + "HCLK_NL1END_S3_0", + "NL1END0" + ], + [ + "HCLK_SS6E3", + "SS6D3" + ], + [ + "HCLK_NE2BEG3", + "NE2A3" + ], + [ + "HCLK_NN6E1", + "NN6END1" + ], + [ + "HCLK_SL1END0", + "SL1BEG0" + ], + [ + "HCLK_SE6D1", + "SE6C1" + ], + [ + "HCLK_SE2A3", + "SE2BEG3" + ], + [ + "HCLK_ER1END3", + "ER1END_N3_3" + ], + [ + "HCLK_LVB7", + "LVB7" + ], + [ + "HCLK_SL1END1", + "SL1BEG1" + ], + [ + "HCLK_NL1BEG0", + "NL1END0" + ], + [ + "HCLK_SS2A2", + "SS2BEG2" + ], + [ + "HCLK_NN6D0", + "NN6E0" + ], + [ + "HCLK_NE2BEG1", + "NE2A1" + ], + [ + "HCLK_NN6A0", + "NN6B0" + ], + [ + "HCLK_SW2A3", + "SW2BEG3" + ], + [ + "HCLK_SE2A2", + "SE2BEG2" + ], + [ + "HCLK_NW6D3", + "NW6E3" + ], + [ + "HCLK_NN6D2", + "NN6E2" + ], + [ + "HCLK_LVB3", + "LVB3" + ], + [ + "HCLK_SE2A0", + "SE2BEG0" + ], + [ + "HCLK_SE6C0", + "SE6B0" + ], + [ + "HCLK_LVB2", + "LVB2" + ], + [ + "HCLK_NE6C1", + "NE6D1" + ], + [ + "HCLK_NR1BEG3", + "NR1END3" + ] + ], + "tile_types": [ + "HCLK_R", + "INT_R" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4C0_12", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EE4A0_12", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE2BEG2_12", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_LH12_12", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_EE4BEG0_12", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WW4A2_12", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WW2A1_12", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_EE4C2_12", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW4A1_12", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WW4A0_12", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE2BEG0_12", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW2A2_12", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_EE2A2_12", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WW4END0_12", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_SW2A1_12", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4B0_12", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WL1END2_12", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WL1END1_12", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_SW4END1_12", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EL1BEG3_12", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WW4END3_12", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_EE2A1_12", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_EE2BEG1_12", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_SW4A0_12", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_ER1BEG1_12", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SW4END3_12", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_SE2A1_12", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_NE4C2_12", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW4B1_12", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW4C2_12", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_WR1END0_12", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_EE4C3_12", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_ER1BEG3_12", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_EE4C1_12", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_WW4C0_12", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_EE2A0_12", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW2END2_12", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_EE4BEG1_12", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG0_12", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_LH1_12", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_NE2A0_12", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_LH10_12", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WW2END0_12", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WR1END3_12", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_NE4BEG1_12", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_SE4C1_12", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_SE4C3_12", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_SE2A3_12", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_EE4BEG2_12", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WW4C3_12", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_SW2A3_12", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NE4C3_12", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WW2END1_12", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_SE4C2_12", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_ER1BEG2_12", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_NW4END1_12", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NW4A2_12", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NE2A2_12", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_SE2A2_12", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_SW2A2_12", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_EE4B2_12", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EL1BEG1_12", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SE4BEG3_12", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_WW4C1_12", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_WR1END1_12", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WW4END1_12", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE4A3_12", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_WR1END2_12", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_WW4B0_12", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_WW4A3_12", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NE2A3_12", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_LH7_12", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_NE4BEG2_12", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_LH5_12", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_NW2A3_12", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_EL1BEG0_12", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE4B3_12", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NW4END0_12", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SW4A3_12", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_NW4END3_12", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW2END3_12", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_EE4A2_12", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SE4BEG2_12", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_NW4A3_12", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_SE4C0_12", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_WL1END3_12", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4A1_12", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_SW2A0_12", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_SW4END2_12", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WW4END2_12", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_LH4_12", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SW4A2_12", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_EE4B1_12", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_SW4END0_12", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_NW4A0_12", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SE4BEG1_12", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SW4A1_12", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_ER1BEG0_12", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_LH6_12", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_LH9_12", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_WW4B3_12", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_LH2_12", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NE4BEG3_12", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_NE4C0_12", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_WW4A1_12", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_LH8_12", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_NW2A0_12", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WL1END0_12", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SE2A0_12", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_NE4BEG0_12", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NE2A1_12", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_EE2BEG3_12", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_EE4BEG3_12", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_NW2A2_12", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_WW2A3_12", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_LH11_12", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EE2A3_12", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_EL1BEG2_12", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_WW4B2_12", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_NW2A1_12", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_NW4END2_12", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW2A0_12", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_NE4C1_12", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_LH3_12", + "INT_FEEDTHRU_2_LH3" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ] + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "CFG_CENTER_IMUX2_4", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_SE4BEG2_4", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_WW2A2_4", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_CTRL0_4", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX28_4", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_EL1BEG3_4", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_EE4A0_4", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_LH4_4", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_IMUX26_4", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_BYP5_4", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_WW4C2_4", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX21_4", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_SW2A2_4", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_IMUX17_4", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX1_4", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_SE4BEG3_4", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_SW4A0_4", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_EE4A1_4", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_EE4BEG2_4", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX39_4", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_IMUX4_4", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX40_4", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_EE2BEG2_4", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_SW4A1_4", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_LH9_4", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EE2A3_4", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NW4A3_4", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_IMUX6_4", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_NE4C2_4", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_SE4BEG1_4", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE4B0_4", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_NE2A1_4", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_EE4C3_4", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_NE2A0_4", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_SW2A3_4", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_IMUX35_4", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_FAN1_4", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_NE4C3_4", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_EE4A3_4", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_CLK0_4", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_EE2BEG1_4", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_SE4C2_4", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WW2A1_4", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_BYP6_4", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_NW4A0_4", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NE2A2_4", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_SE2A1_4", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NW4A1_4", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_BYP2_4", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_FAN3_4", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_IMUX19_4", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_WL1END1_4", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_WW4B1_4", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_ER1BEG1_4", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_IMUX9_4", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_EE4BEG0_4", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_WL1END3_4", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_BYP1_4", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WR1END2_4", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_WW4B2_4", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_BYP7_4", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_SE2A2_4", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX14_4", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_NW4END2_4", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_EE4C2_4", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_WW4B3_4", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_NW2A3_4", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_IMUX0_4", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_IMUX43_4", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX5_4", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX32_4", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_LH5_4", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX46_4", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_SE4C1_4", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX44_4", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_EE4B3_4", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_WL1END0_4", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_WW2A3_4", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX31_4", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_IMUX41_4", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_WW4A1_4", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_SW4A3_4", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EL1BEG2_4", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX12_4", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_FAN7_4", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_WR1END1_4", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_IMUX10_4", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_WW4A3_4", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_NE4C1_4", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_ER1BEG0_4", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_NE4BEG0_4", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_ER1BEG2_4", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_WR1END3_4", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_WW2END3_4", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_EL1BEG0_4", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_SE4BEG0_4", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_IMUX24_4", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_SW2A0_4", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_WW2END1_4", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_FAN4_4", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_EE2A1_4", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_LH10_4", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_CTRL1_4", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_BYP0_4", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_4", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_SE2A0_4", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_4", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_WW4A2_4", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_EE4C1_4", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_EE4B1_4", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_IMUX15_4", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_LH3_4", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_WW4A0_4", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_LH11_4", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_LH7_4", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_NE2A3_4", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_WW4C0_4", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_NW2A2_4", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_SW4END1_4", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_NE4BEG3_4", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX7_4", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_WW2END2_4", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_IMUX3_4", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_FAN5_4", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_ER1BEG3_4", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_BYP4_4", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_IMUX37_4", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SE4C0_4", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_SE4C3_4", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_LH1_4", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NW2A0_4", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_FAN0_4", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX11_4", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_LH6_4", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX8_4", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_IMUX36_4", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_EE4BEG1_4", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_LH2_4", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EE4B2_4", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX45_4", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX27_4", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_EE4A2_4", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_EE2BEG3_4", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX13_4", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_SW4END2_4", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_IMUX42_4", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX38_4", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_FAN6_4", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_EE2BEG0_4", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_EE2A0_4", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_SW4END3_4", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_CLK1_4", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_EE2A2_4", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_EE4C0_4", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_NW2A1_4", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_NE4C0_4", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE4BEG3_4", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_WW2A0_4", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_NW4END0_4", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_SW4END0_4", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_NW4A2_4", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_IMUX18_4", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX25_4", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_NW4END1_4", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_WW4END2_4", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_SW2A1_4", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WR1END0_4", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_WL1END2_4", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_FAN2_4", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_WW4B0_4", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_LH8_4", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_IMUX29_4", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_BYP3_4", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_NE4BEG1_4", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_WW4END0_4", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX22_4", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW4C1_4", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_WW4END3_4", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_NE4BEG2_4", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG1_4", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_IMUX16_4", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_SE2A3_4", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_IMUX30_4", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_WW4END1_4", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX23_4", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW4C3_4", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX33_4", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_IMUX20_4", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_IMUX34_4", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_IMUX47_4", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_LH12_4", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_SW4A2_4", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_WW2END0_4", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_NW4END3_4", + "VFRAME_NW4END3" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 8 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH12_0", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH9_0", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH1_0", + "VBRK_LH1" + ], + [ + "CMT_TOP_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH8_0", + "VBRK_LH8" + ], + [ + "CMT_TOP_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH5_0", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH4_0", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH3_0", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_LH10_0", + "VBRK_LH10" + ], + [ + "CMT_TOP_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH11_0", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SW4A1_0", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH7_0", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH2_0", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH6_0", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WW4B3_0", + "VBRK_WW4B3" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "PCIE_LOGIC_OUTS_B2_R_6", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_WW4C1_6", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_WW4A0_6", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_6", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_IMUX42_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_SW4A1_6", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_LH10_6", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_EL1BEG1_6", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_SE4C0_6", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_EE2A3_6", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_EE4C0_6", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX37_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_NW4A2_6", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_LH11_6", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_NW4END1_6", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_WW4C2_6", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_EE4BEG2_6", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_FAN0_R_6", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_WW4A2_6", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_SW4END2_6", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_LH7_6", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_SE4BEG0_6", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_LH12_6", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_IMUX10_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_EL1BEG3_6", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_WL1END2_6", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_6", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_IMUX7_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_NW4A1_6", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_WR1END2_6", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_NE4BEG2_6", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_WW2END3_6", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_FAN2_R_6", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_IMUX23_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_WR1END0_6", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_IMUX34_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_NW2A0_6", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_WW4B3_6", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_IMUX47_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_NE2A0_6", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_6", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_IMUX13_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_WL1END1_6", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_WW4B1_6", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_WW2A0_6", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_SW4END0_6", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_SE4BEG3_6", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_IMUX6_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_IMUX30_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_NW4END2_6", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_SW2A0_6", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX24_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_FAN3_R_6", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_ER1BEG0_6", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_EE4BEG1_6", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_EE4A0_6", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_IMUX1_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_EE2A1_6", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_NW4A3_6", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_NE4C2_6", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_EE2A2_6", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_WW4END2_6", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_EE4C1_6", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_EE4A3_6", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_NE2A2_6", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_WW4END0_6", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_NW4END3_6", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_LH6_6", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_BYP6_R_6", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_LH4_6", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_IMUX12_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_NW2A3_6", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_IMUX0_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_6", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_FAN5_R_6", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_FAN6_R_6", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_IMUX25_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_NE4C1_6", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_EE4B1_6", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_SE4BEG2_6", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_BYP2_R_6", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_EE2BEG2_6", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_6", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_SW4A3_6", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_WW2A1_6", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_WW4END3_6", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_LH1_6", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_SE2A2_6", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_CLK0_R_6", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_NW4A0_6", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_IMUX18_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_CLK1_R_6", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_LH3_6", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_EE4BEG0_6", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_BYP3_R_6", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_IMUX29_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_IMUX20_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_LH5_6", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_NE2A3_6", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_6", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_WL1END3_6", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_ER1BEG3_6", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_IMUX21_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_SE2A3_6", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_BYP5_R_6", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_6", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_SE2A0_6", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_6", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_EE4B2_6", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_SE4C1_6", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_BYP0_R_6", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_EE4B0_6", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX35_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_IMUX46_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_IMUX45_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_SE4C3_6", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_IMUX16_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_6", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_WR1END3_6", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_WL1END0_6", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_WW4B0_6", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_6", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_BYP4_R_6", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_NW2A1_6", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_FAN7_R_6", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_EE4C3_6", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_WW2END0_6", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_6", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_EE2BEG3_6", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_IMUX44_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_NW2A2_6", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_ER1BEG2_6", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_IMUX28_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_IMUX17_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_IMUX19_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_CTRL0_R_6", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_WW2END1_6", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_EE4C2_6", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_IMUX43_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_SE2A1_6", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_EE2BEG1_6", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX15_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_SW4A2_6", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_WW2A2_6", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_FAN4_R_6", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_IMUX4_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_WR1END1_6", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_6", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_IMUX8_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_EE4B3_6", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_EE4A1_6", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_NE4C0_6", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_6", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_NE4BEG3_6", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_WW4C3_6", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_SW2A1_6", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_IMUX5_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_WW4A1_6", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_NE2A1_6", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_WW2END2_6", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_6", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_IMUX38_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_EL1BEG2_6", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_EE4A2_6", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_CTRL1_R_6", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_6", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_IMUX22_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_SE4BEG1_6", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_6", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_FAN1_R_6", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_WW4A3_6", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_BYP1_R_6", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_EL1BEG0_6", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_IMUX2_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_IMUX27_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_SW4A0_6", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_IMUX32_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_SW4END1_6", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_IMUX14_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_6", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_IMUX36_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_IMUX40_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_LH8_6", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_ER1BEG1_6", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_IMUX9_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_EE2BEG0_6", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_EE4BEG3_6", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_NW4END0_6", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_6", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_SW4END3_6", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_NE4BEG0_6", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_IMUX11_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_BYP7_R_6", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_WW4END1_6", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_WW2A3_6", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_IMUX41_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_6", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_WW4B2_6", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_IMUX31_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_6", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_6", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_SW2A3_6", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_LH2_6", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_6", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_LH9_6", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_IMUX3_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_IMUX26_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_SE4C2_6", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_IMUX39_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_WW4C0_6", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_IMUX33_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_EE2A0_6", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_SW2A2_6", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_NE4C3_6", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_6", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_NE4BEG1_6", + "INT_INTERFACE_NE4BEG1" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -6 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE2A3_16", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_SE4C2_16", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_EL1BEG2_16", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_LH8_16", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_LH2_16", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_WW4END0_16", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WW4B2_16", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_NW2A2_16", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_EE2A0_16", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW4A3_16", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NE4BEG3_16", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WL1END3_16", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_WR1END1_16", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_EE4C2_16", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_EL1BEG0_16", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE2A1_16", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_EE4A2_16", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_WL1END2_16", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WW4B3_16", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_WR1END3_16", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_SW2A2_16", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_EE4BEG2_16", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SE4C1_16", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_EE4BEG3_16", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_LH1_16", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_SW2A1_16", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_NE4BEG0_16", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_WW4C1_16", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_WW4END1_16", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_SW4END3_16", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_EE4BEG0_16", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NE2A3_16", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_WW2END0_16", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_EE4C1_16", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_WW4A0_16", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE4A0_16", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_LH6_16", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WW2A2_16", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NW4A0_16", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SW2A0_16", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_NE4C2_16", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_SE4BEG2_16", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_SE4C0_16", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_SE2A0_16", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_WL1END0_16", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SW4END1_16", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EE4BEG1_16", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_NW4A1_16", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SW4A1_16", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_LH10_16", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_NE2A1_16", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_EL1BEG3_16", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_SE2A1_16", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW2END3_16", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_WW2A1_16", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WW4C2_16", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_EE2BEG3_16", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NW4A2_16", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NW4END2_16", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4A2_16", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WR1END2_16", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_NW2A1_16", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_NE4BEG1_16", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_SE4C3_16", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_NW4END0_16", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SW4END2_16", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SE2A2_16", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4A3_16", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_LH11_16", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_NW4END1_16", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NE4C0_16", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_WW2A0_16", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WR1END0_16", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH9_16", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_EE4B1_16", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EL1BEG1_16", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW4END3_16", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_SE4BEG3_16", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_ER1BEG2_16", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_ER1BEG1_16", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_NW2A0_16", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_EE4C3_16", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_EE4B0_16", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH4_16", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SW2A3_16", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NE4BEG2_16", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_WW4B0_16", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_WW4END2_16", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_WW2A3_16", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WW4B1_16", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_SW4A3_16", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE2A2_16", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WL1END1_16", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_SE2A3_16", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SW4END0_16", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_NE2A2_16", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE2BEG2_16", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NE4C3_16", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_EE4B3_16", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SW4A0_16", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_SE4BEG0_16", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_EE4A1_16", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NW2A3_16", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE4C1_16", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW4C0_16", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_LH5_16", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_ER1BEG3_16", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_NW4A3_16", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_LH7_16", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_EE2BEG1_16", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_LH12_16", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_SW4A2_16", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_WW2END2_16", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_LH3_16", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_EE2BEG0_16", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW2END1_16", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_SE4BEG1_16", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_NW4END3_16", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW4C3_16", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE4B2_16", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE4C0_16", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_NE2A0_16", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_WW4A1_16", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_ER1BEG0_16", + "INT_FEEDTHRU_2_ER1BEG0" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B5_7", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX47_7", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_LOGIC_OUTS_B14_7", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX41_7", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX20_7", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_BYP2_7", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_FAN3_7", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN2_7", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_BYP4_7", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_CTRL0_7", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX7_7", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX30_7", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX29_7", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_FAN4_7", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX8_7", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_LOGIC_OUTS_B23_7", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX35_7", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_BYP3_7", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B0_7", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_LOGIC_OUTS_B1_7", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX1_7", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX9_7", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX21_7", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX10_7", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B12_7", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_LOGIC_OUTS_B15_7", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_BYP7_7", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX40_7", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX28_7", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_FAN1_7", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B6_7", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_BYP1_7", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX22_7", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B13_7", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B19_7", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B4_7", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_IMUX34_7", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX18_7", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_LOGIC_OUTS_B16_7", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B9_7", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX16_7", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX0_7", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX32_7", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_CTRL1_7", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_FAN5_7", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_FAN7_7", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX43_7", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_LOGIC_OUTS_B18_7", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX3_7", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_FAN0_7", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX23_7", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX19_7", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX25_7", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX33_7", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_CLK1_7", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX14_7", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_BYP0_7", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_LOGIC_OUTS_B3_7", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX4_7", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX2_7", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX36_7", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX15_7", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_LOGIC_OUTS_B7_7", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_IMUX12_7", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX38_7", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX11_7", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_CLK0_7", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX24_7", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX39_7", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX5_7", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX13_7", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP5_7", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B8_7", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX45_7", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_FAN6_7", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_BYP6_7", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_LOGIC_OUTS_B10_7", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX26_7", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX31_7", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B20_7", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX37_7", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX6_7", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX42_7", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_LOGIC_OUTS_B2_7", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX17_7", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_LOGIC_OUTS_B22_7", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX46_7", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX44_7", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX27_7", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B11_7", + "VBRK_EXT_LOGIC_OUTS_B11" + ] + ], + "tile_types": [ + "GTX_CHANNEL_0", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_LOGIC_OUTS4", + "LOGIC_OUTS4" + ], + [ + "INT_INTERFACE_IMUX33", + "IMUX33" + ], + [ + "INT_INTERFACE_FAN4", + "FAN4" + ], + [ + "INT_INTERFACE_NW4END3", + "NW6END3" + ], + [ + "INT_INTERFACE_WW2A2", + "WW2A2" + ], + [ + "INT_INTERFACE_SE4BEG3", + "SE6BEG3" + ], + [ + "INT_INTERFACE_NW4A0", + "NW6A0" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_PHASER_TO_IO_ICLK" + ], + [ + "INT_INTERFACE_SE4C0", + "SE6E0" + ], + [ + "INT_INTERFACE_SW4A0", + "SW6A0" + ], + [ + "INT_INTERFACE_EE4BEG3", + "EE4BEG3" + ], + [ + "INT_INTERFACE_IMUX11", + "IMUX11" + ], + [ + "INT_INTERFACE_CLK1", + "CLK1" + ], + [ + "INT_INTERFACE_WW4END3", + "WW4END3" + ], + [ + "INT_INTERFACE_WR1END0", + "WR1END0" + ], + [ + "INT_INTERFACE_WW2END1", + "WW2END1" + ], + [ + "INT_INTERFACE_IMUX44", + "IMUX44" + ], + [ + "INT_INTERFACE_FAN7", + "FAN7" + ], + [ + "INT_INTERFACE_LH5", + "LH5" + ], + [ + "INT_INTERFACE_SE4C2", + "SE6E2" + ], + [ + "INT_INTERFACE_IMUX30", + "IMUX30" + ], + [ + "INT_INTERFACE_IMUX32", + "IMUX32" + ], + [ + "INT_INTERFACE_EE2BEG0", + "EE2BEG0" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "INT_INTERFACE_SE2A2", + "SE2A2" + ], + [ + "INT_INTERFACE_BYP0", + "BYP0" + ], + [ + "INT_INTERFACE_BYP5", + "BYP5" + ], + [ + "INT_INTERFACE_WL1END0", + "WL1END0" + ], + [ + "INT_INTERFACE_WW4A3", + "WW4A3" + ], + [ + "INT_INTERFACE_LH4", + "LH4" + ], + [ + "INT_INTERFACE_WW4C3", + "WW4C3" + ], + [ + "INT_INTERFACE_IMUX18", + "IMUX18" + ], + [ + "INT_INTERFACE_SW2A2", + "SW2END2" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_PHASER_TO_IO_OCLK" + ], + [ + "INT_INTERFACE_EE2BEG3", + "EE2BEG3" + ], + [ + "INT_INTERFACE_IMUX21", + "IMUX21" + ], + [ + "INT_INTERFACE_LH11", + "LH11" + ], + [ + "INT_INTERFACE_LOGIC_OUTS12", + "LOGIC_OUTS12" + ], + [ + "INT_INTERFACE_WW2A3", + "WW2A3" + ], + [ + "INT_INTERFACE_NE2A0", + "NE2A0" + ], + [ + "INT_INTERFACE_IMUX4", + "IMUX4" + ], + [ + "INT_INTERFACE_IMUX1", + "IMUX1" + ], + [ + "INT_INTERFACE_IMUX13", + "IMUX13" + ], + [ + "INT_INTERFACE_SE4C3", + "SE6E3" + ], + [ + "INT_INTERFACE_SE2A3", + "SE2A3" + ], + [ + "INT_INTERFACE_ER1BEG3", + "ER1BEG3" + ], + [ + "INT_INTERFACE_NE4BEG3", + "NE6BEG3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS2", + "LOGIC_OUTS2" + ], + [ + "INT_INTERFACE_WW4END0", + "WW4END0" + ], + [ + "INT_INTERFACE_IMUX25", + "IMUX25" + ], + [ + "INT_INTERFACE_IMUX22", + "IMUX22" + ], + [ + "INT_INTERFACE_EE4A2", + "EE4A2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS14", + "LOGIC_OUTS14" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "INT_INTERFACE_IMUX16", + "IMUX16" + ], + [ + "INT_INTERFACE_IMUX14", + "IMUX14" + ], + [ + "INT_INTERFACE_IMUX9", + "IMUX9" + ], + [ + "INT_INTERFACE_IMUX5", + "IMUX5" + ], + [ + "INT_INTERFACE_WW2END2", + "WW2END2" + ], + [ + "INT_INTERFACE_WW4END2", + "WW4END2" + ], + [ + "INT_INTERFACE_NW4END2", + "NW6END2" + ], + [ + "INT_INTERFACE_IMUX47", + "IMUX47" + ], + [ + "INT_INTERFACE_IMUX41", + "IMUX41" + ], + [ + "INT_INTERFACE_SW2A0", + "SW2END0" + ], + [ + "INT_INTERFACE_EE4C1", + "EE4C1" + ], + [ + "INT_INTERFACE_NE4BEG2", + "NE6BEG2" + ], + [ + "INT_INTERFACE_EE2BEG2", + "EE2BEG2" + ], + [ + "INT_INTERFACE_WL1END2", + "WL1END2" + ], + [ + "INT_INTERFACE_NW2A1", + "NW2END1" + ], + [ + "INT_INTERFACE_WW4A2", + "WW4A2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS6", + "LOGIC_OUTS6" + ], + [ + "INT_INTERFACE_SW4END3", + "SW6END3" + ], + [ + "INT_INTERFACE_NW2A0", + "NW2END0" + ], + [ + "INT_INTERFACE_EE4B2", + "EE4B2" + ], + [ + "INT_INTERFACE_IMUX34", + "IMUX34" + ], + [ + "INT_INTERFACE_EE4C2", + "EE4C2" + ], + [ + "INT_INTERFACE_ER1BEG0", + "ER1BEG0" + ], + [ + "INT_INTERFACE_EE2A1", + "EE2A1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS15", + "LOGIC_OUTS15" + ], + [ + "INT_INTERFACE_WW2END0", + "WW2END0" + ], + [ + "INT_INTERFACE_WW4C0", + "WW4C0" + ], + [ + "INT_INTERFACE_NE2A2", + "NE2A2" + ], + [ + "INT_INTERFACE_LH3", + "LH3" + ], + [ + "INT_INTERFACE_EE4B1", + "EE4B1" + ], + [ + "INT_INTERFACE_BYP4", + "BYP4" + ], + [ + "INT_INTERFACE_IMUX46", + "IMUX46" + ], + [ + "INT_INTERFACE_IMUX12", + "IMUX12" + ], + [ + "INT_INTERFACE_SE4BEG0", + "SE6BEG0" + ], + [ + "INT_INTERFACE_NW2A3", + "NW2END3" + ], + [ + "INT_INTERFACE_CTRL0", + "CTRL0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS23", + "LOGIC_OUTS23" + ], + [ + "INT_INTERFACE_LH8", + "LH8" + ], + [ + "INT_INTERFACE_LOGIC_OUTS21", + "LOGIC_OUTS21" + ], + [ + "INT_INTERFACE_IMUX42", + "IMUX42" + ], + [ + "INT_INTERFACE_ER1BEG2", + "ER1BEG2" + ], + [ + "INT_INTERFACE_FAN5", + "FAN5" + ], + [ + "INT_INTERFACE_IMUX36", + "IMUX36" + ], + [ + "INT_INTERFACE_IMUX26", + "IMUX26" + ], + [ + "INT_INTERFACE_CTRL1", + "CTRL1" + ], + [ + "INT_INTERFACE_BYP7", + "BYP7" + ], + [ + "INT_INTERFACE_LH6", + "LH6" + ], + [ + "INT_INTERFACE_SW4END2", + "SW6END2" + ], + [ + "INT_INTERFACE_WW4B3", + "WW4B3" + ], + [ + "INT_INTERFACE_WR1END3", + "WR1END3" + ], + [ + "INT_INTERFACE_IMUX19", + "IMUX19" + ], + [ + "INT_INTERFACE_IMUX6", + "IMUX6" + ], + [ + "INT_INTERFACE_IMUX45", + "IMUX45" + ], + [ + "INT_INTERFACE_SE2A1", + "SE2A1" + ], + [ + "INT_INTERFACE_SW4A2", + "SW6A2" + ], + [ + "INT_INTERFACE_SW2A3", + "SW2END3" + ], + [ + "INT_INTERFACE_IMUX37", + "IMUX37" + ], + [ + "INT_INTERFACE_WW2A1", + "WW2A1" + ], + [ + "INT_INTERFACE_IMUX10", + "IMUX10" + ], + [ + "INT_INTERFACE_LOGIC_OUTS10", + "LOGIC_OUTS10" + ], + [ + "INT_INTERFACE_IMUX38", + "IMUX38" + ], + [ + "INT_INTERFACE_EE4C3", + "EE4C3" + ], + [ + "INT_INTERFACE_SE4C1", + "SE6E1" + ], + [ + "INT_INTERFACE_EE4A1", + "EE4A1" + ], + [ + "INT_INTERFACE_EE4B3", + "EE4B3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS18", + "LOGIC_OUTS18" + ], + [ + "INT_INTERFACE_EL1BEG0", + "EL1BEG0" + ], + [ + "INT_INTERFACE_FAN2", + "FAN2" + ], + [ + "INT_INTERFACE_BYP1", + "BYP1" + ], + [ + "INT_INTERFACE_WL1END3", + "WL1END3" + ], + [ + "INT_INTERFACE_WR1END2", + "WR1END2" + ], + [ + "INT_INTERFACE_WW4B1", + "WW4B1" + ], + [ + "INT_INTERFACE_EE2A3", + "EE2A3" + ], + [ + "INT_INTERFACE_IMUX43", + "IMUX43" + ], + [ + "INT_INTERFACE_WW4A1", + "WW4A1" + ], + [ + "INT_INTERFACE_EE4B0", + "EE4B0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS5", + "LOGIC_OUTS5" + ], + [ + "INT_INTERFACE_LOGIC_OUTS3", + "LOGIC_OUTS3" + ], + [ + "INT_INTERFACE_NW4A2", + "NW6A2" + ], + [ + "INT_INTERFACE_EL1BEG3", + "EL1BEG3" + ], + [ + "INT_INTERFACE_FAN6", + "FAN6" + ], + [ + "INT_INTERFACE_NE4C2", + "NE6E2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS8", + "LOGIC_OUTS8" + ], + [ + "INT_INTERFACE_IMUX35", + "IMUX35" + ], + [ + "INT_INTERFACE_IMUX23", + "IMUX23" + ], + [ + "INT_INTERFACE_NW2A2", + "NW2END2" + ], + [ + "INT_INTERFACE_SE4BEG1", + "SE6BEG1" + ], + [ + "INT_INTERFACE_SW4A1", + "SW6A1" + ], + [ + "INT_INTERFACE_IMUX29", + "IMUX29" + ], + [ + "INT_INTERFACE_SW2A1", + "SW2END1" + ], + [ + "L_INT_INTER_DQS_IOTOPHASER", + "INT_DQS_IOTOPHASER" + ], + [ + "INT_INTERFACE_SE4BEG2", + "SE6BEG2" + ], + [ + "INT_INTERFACE_FAN3", + "FAN3" + ], + [ + "INT_INTERFACE_IMUX8", + "IMUX8" + ], + [ + "INT_INTERFACE_ER1BEG1", + "ER1BEG1" + ], + [ + "INT_INTERFACE_EE4A0", + "EE4A0" + ], + [ + "INT_INTERFACE_WW4A0", + "WW4A0" + ], + [ + "INT_INTERFACE_NW4A1", + "NW6A1" + ], + [ + "INT_INTERFACE_WW4B0", + "WW4B0" + ], + [ + "INT_INTERFACE_SW4END1", + "SW6END1" + ], + [ + "INT_INTERFACE_WW4C1", + "WW4C1" + ], + [ + "INT_INTERFACE_NE4C3", + "NE6E3" + ], + [ + "INT_INTERFACE_BYP3", + "BYP3" + ], + [ + "INT_INTERFACE_EE4BEG0", + "EE4BEG0" + ], + [ + "INT_INTERFACE_MONITOR_P", + "MONITOR_P" + ], + [ + "INT_INTERFACE_IMUX24", + "IMUX24" + ], + [ + "INT_INTERFACE_WW4END1", + "WW4END1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS17", + "LOGIC_OUTS17" + ], + [ + "INT_INTERFACE_NE4C1", + "NE6E1" + ], + [ + "INT_INTERFACE_IMUX7", + "IMUX7" + ], + [ + "INT_INTERFACE_LOGIC_OUTS13", + "LOGIC_OUTS13" + ], + [ + "INT_INTERFACE_WW2END3", + "WW2END3" + ], + [ + "INT_INTERFACE_EL1BEG1", + "EL1BEG1" + ], + [ + "INT_INTERFACE_NW4A3", + "NW6A3" + ], + [ + "INT_INTERFACE_SW4A3", + "SW6A3" + ], + [ + "INT_INTERFACE_NE4BEG0", + "NE6BEG0" + ], + [ + "INT_INTERFACE_IMUX15", + "IMUX15" + ], + [ + "INT_INTERFACE_CLK0", + "CLK0" + ], + [ + "INT_INTERFACE_EE2A0", + "EE2A0" + ], + [ + "INT_INTERFACE_NE4BEG1", + "NE6BEG1" + ], + [ + "INT_INTERFACE_LH2", + "LH2" + ], + [ + "INT_INTERFACE_SW4END0", + "SW6END0" + ], + [ + "INT_INTERFACE_NE2A3", + "NE2A3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS9", + "LOGIC_OUTS9" + ], + [ + "INT_INTERFACE_NE2A1", + "NE2A1" + ], + [ + "INT_INTERFACE_BYP2", + "BYP2" + ], + [ + "INT_INTERFACE_IMUX20", + "IMUX20" + ], + [ + "INT_INTERFACE_LOGIC_OUTS11", + "LOGIC_OUTS11" + ], + [ + "INT_INTERFACE_WL1END1", + "WL1END1" + ], + [ + "INT_INTERFACE_EE4BEG1", + "EE4BEG1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS19", + "LOGIC_OUTS19" + ], + [ + "INT_INTERFACE_WW2A0", + "WW2A0" + ], + [ + "INT_INTERFACE_EL1BEG2", + "EL1BEG2" + ], + [ + "INT_INTERFACE_WR1END1", + "WR1END1" + ], + [ + "INT_INTERFACE_WW4B2", + "WW4B2" + ], + [ + "INT_INTERFACE_IMUX3", + "IMUX3" + ], + [ + "INT_INTERFACE_EE2BEG1", + "EE2BEG1" + ], + [ + "INT_INTERFACE_IMUX2", + "IMUX2" + ], + [ + "INT_INTERFACE_FAN0", + "FAN0" + ], + [ + "INT_INTERFACE_LH10", + "LH10" + ], + [ + "INT_INTERFACE_IMUX17", + "IMUX17" + ], + [ + "INT_INTERFACE_IMUX27", + "IMUX27" + ], + [ + "INT_INTERFACE_MONITOR_N", + "MONITOR_N" + ], + [ + "INT_INTERFACE_LH7", + "LH7" + ], + [ + "INT_INTERFACE_EE4A3", + "EE4A3" + ], + [ + "INT_INTERFACE_LH9", + "LH9" + ], + [ + "INT_INTERFACE_EE4BEG2", + "EE4BEG2" + ], + [ + "INT_INTERFACE_IMUX31", + "IMUX31" + ], + [ + "INT_INTERFACE_LOGIC_OUTS22", + "LOGIC_OUTS22" + ], + [ + "INT_INTERFACE_LOGIC_OUTS16", + "LOGIC_OUTS16" + ], + [ + "INT_INTERFACE_LOGIC_OUTS20", + "LOGIC_OUTS20" + ], + [ + "INT_INTERFACE_WW4C2", + "WW4C2" + ], + [ + "INT_INTERFACE_NW4END0", + "NW6END0" + ], + [ + "INT_INTERFACE_IMUX28", + "IMUX28" + ], + [ + "INT_INTERFACE_LOGIC_OUTS0", + "LOGIC_OUTS0" + ], + [ + "INT_INTERFACE_EE2A2", + "EE2A2" + ], + [ + "INT_INTERFACE_BYP6", + "BYP6" + ], + [ + "INT_INTERFACE_EE4C0", + "EE4C0" + ], + [ + "INT_INTERFACE_IMUX40", + "IMUX40" + ], + [ + "INT_INTERFACE_LH12", + "LH12" + ], + [ + "INT_INTERFACE_LH1", + "LH1" + ], + [ + "INT_INTERFACE_IMUX0", + "IMUX0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS7", + "LOGIC_OUTS7" + ], + [ + "INT_INTERFACE_SE2A0", + "SE2A0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS1", + "LOGIC_OUTS1" + ], + [ + "INT_INTERFACE_NW4END1", + "NW6END1" + ], + [ + "INT_INTERFACE_NE4C0", + "NE6E0" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_PHASER_TO_IO_OCLK1X_90" + ], + [ + "INT_INTERFACE_IMUX39", + "IMUX39" + ], + [ + "INT_INTERFACE_FAN1", + "FAN1" + ] + ], + "tile_types": [ + "INT_INTERFACE_R", + "INT_R" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "BRKH_CLK_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "BRKH_CLK_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "BRKH_CLK_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "BRKH_CLK_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "BRKH_CLK_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "BRKH_CLK_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ], + [ + "BRKH_CLK_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "BRKH_CLK_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "BRKH_CLK_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "BRKH_CLK_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "BRKH_CLK_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "BRKH_CLK_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "BRKH_CLK_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "BRKH_CLK_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "BRKH_CLK_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "BRKH_CLK_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "BRKH_CLK_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "BRKH_CLK_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "BRKH_CLK_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "BRKH_CLK_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "BRKH_CLK_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "BRKH_CLK_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "BRKH_CLK_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "BRKH_CLK_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "BRKH_CLK_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "BRKH_CLK_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "BRKH_CLK_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "BRKH_CLK_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "BRKH_CLK_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "BRKH_CLK_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "BRKH_CLK_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "BRKH_CLK_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "BRKH_CLK_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ] + ], + "tile_types": [ + "BRKH_CLK", + "CLK_FEED" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "BRAM_LH4_2", + "VBRK_LH4" + ], + [ + "BRAM_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "BRAM_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "BRAM_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "BRAM_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "BRAM_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "BRAM_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "BRAM_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "BRAM_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "BRAM_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "BRAM_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "BRAM_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "BRAM_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "BRAM_EE4B3_2", + "VBRK_EE4B3" + ], + [ + "BRAM_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "BRAM_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "BRAM_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "BRAM_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "BRAM_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "BRAM_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "BRAM_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "BRAM_LH11_2", + "VBRK_LH11" + ], + [ + "BRAM_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "BRAM_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "BRAM_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "BRAM_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "BRAM_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "BRAM_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "BRAM_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "BRAM_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "BRAM_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "BRAM_LH7_2", + "VBRK_LH7" + ], + [ + "BRAM_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "BRAM_LH5_2", + "VBRK_LH5" + ], + [ + "BRAM_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "BRAM_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "BRAM_NW2A2_2", + "VBRK_NW2A2" + ], + [ + "BRAM_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "BRAM_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "BRAM_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "BRAM_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "BRAM_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "BRAM_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "BRAM_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "BRAM_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "BRAM_MONITOR_N_2", + "VBRK_MONITOR_N" + ], + [ + "BRAM_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "BRAM_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "BRAM_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "BRAM_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "BRAM_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "BRAM_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "BRAM_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "BRAM_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "BRAM_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "BRAM_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "BRAM_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "BRAM_LH10_2", + "VBRK_LH10" + ], + [ + "BRAM_LH12_2", + "VBRK_LH12" + ], + [ + "BRAM_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "BRAM_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "BRAM_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "BRAM_MONITOR_P_2", + "VBRK_MONITOR_P" + ], + [ + "BRAM_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "BRAM_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "BRAM_LH8_2", + "VBRK_LH8" + ], + [ + "BRAM_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "BRAM_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "BRAM_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "BRAM_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "BRAM_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "BRAM_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "BRAM_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "BRAM_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "BRAM_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "BRAM_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "BRAM_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "BRAM_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "BRAM_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "BRAM_LH3_2", + "VBRK_LH3" + ], + [ + "BRAM_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "BRAM_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "BRAM_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "BRAM_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "BRAM_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "BRAM_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "BRAM_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "BRAM_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "BRAM_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "BRAM_LH6_2", + "VBRK_LH6" + ], + [ + "BRAM_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "BRAM_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "BRAM_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "BRAM_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "BRAM_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "BRAM_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "BRAM_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "BRAM_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "BRAM_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "BRAM_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "BRAM_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "BRAM_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "BRAM_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "BRAM_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "BRAM_LH2_2", + "VBRK_LH2" + ], + [ + "BRAM_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "BRAM_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "BRAM_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "BRAM_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "BRAM_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "BRAM_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "BRAM_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "BRAM_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "BRAM_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "BRAM_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "BRAM_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "BRAM_LH9_2", + "VBRK_LH9" + ], + [ + "BRAM_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "BRAM_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "BRAM_LH1_2", + "VBRK_LH1" + ], + [ + "BRAM_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "BRAM_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "BRAM_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "BRAM_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "BRAM_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "BRAM_SW2A1_2", + "VBRK_SW2A1" + ] + ], + "tile_types": [ + "BRAM_L", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "DSP_LOGIC_OUTS_B19_0", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "DSP_IMUX39_0", + "INT_INTERFACE_IMUX39" + ], + [ + "DSP_ER1BEG2_0", + "INT_INTERFACE_ER1BEG2" + ], + [ + "DSP_ER1BEG3_0", + "INT_INTERFACE_ER1BEG3" + ], + [ + "DSP_EL1BEG2_0", + "INT_INTERFACE_EL1BEG2" + ], + [ + "DSP_WW4B2_0", + "INT_INTERFACE_WW4B2" + ], + [ + "DSP_IMUX26_0", + "INT_INTERFACE_IMUX26" + ], + [ + "DSP_EE4C1_0", + "INT_INTERFACE_EE4C1" + ], + [ + "DSP_WW2A2_0", + "INT_INTERFACE_WW2A2" + ], + [ + "DSP_EE4A0_0", + "INT_INTERFACE_EE4A0" + ], + [ + "DSP_EE4BEG3_0", + "INT_INTERFACE_EE4BEG3" + ], + [ + "DSP_IMUX20_0", + "INT_INTERFACE_IMUX20" + ], + [ + "DSP_WL1END0_0", + "INT_INTERFACE_WL1END0" + ], + [ + "DSP_EE4C2_0", + "INT_INTERFACE_EE4C2" + ], + [ + "DSP_IMUX44_0", + "INT_INTERFACE_IMUX44" + ], + [ + "DSP_NW4END3_0", + "INT_INTERFACE_NW4END3" + ], + [ + "DSP_IMUX35_0", + "INT_INTERFACE_IMUX35" + ], + [ + "DSP_IMUX30_0", + "INT_INTERFACE_IMUX30" + ], + [ + "DSP_NE4C1_0", + "INT_INTERFACE_NE4C1" + ], + [ + "DSP_LH3_0", + "INT_INTERFACE_LH3" + ], + [ + "DSP_LOGIC_OUTS_B18_0", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "DSP_EE4B0_0", + "INT_INTERFACE_EE4B0" + ], + [ + "DSP_SE4BEG1_0", + "INT_INTERFACE_SE4BEG1" + ], + [ + "DSP_WW2A1_0", + "INT_INTERFACE_WW2A1" + ], + [ + "DSP_WL1END2_0", + "INT_INTERFACE_WL1END2" + ], + [ + "DSP_LOGIC_OUTS_B22_0", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "DSP_IMUX19_0", + "INT_INTERFACE_IMUX19" + ], + [ + "DSP_EE2A2_0", + "INT_INTERFACE_EE2A2" + ], + [ + "DSP_WW4A2_0", + "INT_INTERFACE_WW4A2" + ], + [ + "DSP_LOGIC_OUTS_B20_0", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "DSP_WW4B3_0", + "INT_INTERFACE_WW4B3" + ], + [ + "DSP_IMUX43_0", + "INT_INTERFACE_IMUX43" + ], + [ + "DSP_WW4END2_0", + "INT_INTERFACE_WW4END2" + ], + [ + "DSP_LH8_0", + "INT_INTERFACE_LH8" + ], + [ + "DSP_EE4BEG1_0", + "INT_INTERFACE_EE4BEG1" + ], + [ + "DSP_NE2A2_0", + "INT_INTERFACE_NE2A2" + ], + [ + "DSP_WW2END1_0", + "INT_INTERFACE_WW2END1" + ], + [ + "DSP_BYP2_0", + "INT_INTERFACE_BYP2" + ], + [ + "DSP_LOGIC_OUTS_B2_0", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "DSP_LH4_0", + "INT_INTERFACE_LH4" + ], + [ + "DSP_EE4C0_0", + "INT_INTERFACE_EE4C0" + ], + [ + "DSP_CLK0_0", + "INT_INTERFACE_CLK0" + ], + [ + "DSP_BYP3_0", + "INT_INTERFACE_BYP3" + ], + [ + "DSP_NW2A1_0", + "INT_INTERFACE_NW2A1" + ], + [ + "DSP_FAN0_0", + "INT_INTERFACE_FAN0" + ], + [ + "DSP_MONITOR_N_0", + "INT_INTERFACE_MONITOR_N" + ], + [ + "DSP_IMUX23_0", + "INT_INTERFACE_IMUX23" + ], + [ + "DSP_EE2BEG0_0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "DSP_LOGIC_OUTS_B17_0", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "DSP_SE4C1_0", + "INT_INTERFACE_SE4C1" + ], + [ + "DSP_LOGIC_OUTS_B14_0", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "DSP_WW4A3_0", + "INT_INTERFACE_WW4A3" + ], + [ + "DSP_EL1BEG3_0", + "INT_INTERFACE_EL1BEG3" + ], + [ + "DSP_NE4BEG3_0", + "INT_INTERFACE_NE4BEG3" + ], + [ + "DSP_IMUX29_0", + "INT_INTERFACE_IMUX29" + ], + [ + "DSP_IMUX28_0", + "INT_INTERFACE_IMUX28" + ], + [ + "DSP_FAN1_0", + "INT_INTERFACE_FAN1" + ], + [ + "DSP_IMUX0_0", + "INT_INTERFACE_IMUX0" + ], + [ + "DSP_WL1END1_0", + "INT_INTERFACE_WL1END1" + ], + [ + "DSP_IMUX15_0", + "INT_INTERFACE_IMUX15" + ], + [ + "DSP_IMUX33_0", + "INT_INTERFACE_IMUX33" + ], + [ + "DSP_EL1BEG0_0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "DSP_IMUX36_0", + "INT_INTERFACE_IMUX36" + ], + [ + "DSP_SE4C2_0", + "INT_INTERFACE_SE4C2" + ], + [ + "DSP_WW4C3_0", + "INT_INTERFACE_WW4C3" + ], + [ + "DSP_LH11_0", + "INT_INTERFACE_LH11" + ], + [ + "DSP_WR1END2_0", + "INT_INTERFACE_WR1END2" + ], + [ + "DSP_LH12_0", + "INT_INTERFACE_LH12" + ], + [ + "DSP_IMUX34_0", + "INT_INTERFACE_IMUX34" + ], + [ + "DSP_NW2A0_0", + "INT_INTERFACE_NW2A0" + ], + [ + "DSP_SE2A1_0", + "INT_INTERFACE_SE2A1" + ], + [ + "DSP_EE4BEG2_0", + "INT_INTERFACE_EE4BEG2" + ], + [ + "DSP_FAN2_0", + "INT_INTERFACE_FAN2" + ], + [ + "DSP_IMUX1_0", + "INT_INTERFACE_IMUX1" + ], + [ + "DSP_FAN3_0", + "INT_INTERFACE_FAN3" + ], + [ + "DSP_MONITOR_P_0", + "INT_INTERFACE_MONITOR_P" + ], + [ + "DSP_NE4BEG1_0", + "INT_INTERFACE_NE4BEG1" + ], + [ + "DSP_IMUX3_0", + "INT_INTERFACE_IMUX3" + ], + [ + "DSP_WW4END1_0", + "INT_INTERFACE_WW4END1" + ], + [ + "DSP_EL1BEG1_0", + "INT_INTERFACE_EL1BEG1" + ], + [ + "DSP_IMUX17_0", + "INT_INTERFACE_IMUX17" + ], + [ + "DSP_IMUX22_0", + "INT_INTERFACE_IMUX22" + ], + [ + "DSP_SE4C3_0", + "INT_INTERFACE_SE4C3" + ], + [ + "DSP_LOGIC_OUTS_B15_0", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "DSP_NE4C2_0", + "INT_INTERFACE_NE4C2" + ], + [ + "DSP_LH1_0", + "INT_INTERFACE_LH1" + ], + [ + "DSP_SW4END3_0", + "INT_INTERFACE_SW4END3" + ], + [ + "DSP_FAN5_0", + "INT_INTERFACE_FAN5" + ], + [ + "DSP_BYP5_0", + "INT_INTERFACE_BYP5" + ], + [ + "DSP_LH2_0", + "INT_INTERFACE_LH2" + ], + [ + "DSP_SW4END2_0", + "INT_INTERFACE_SW4END2" + ], + [ + "DSP_SW4A2_0", + "INT_INTERFACE_SW4A2" + ], + [ + "DSP_LH6_0", + "INT_INTERFACE_LH6" + ], + [ + "DSP_IMUX10_0", + "INT_INTERFACE_IMUX10" + ], + [ + "DSP_SE4BEG3_0", + "INT_INTERFACE_SE4BEG3" + ], + [ + "DSP_BYP1_0", + "INT_INTERFACE_BYP1" + ], + [ + "DSP_WR1END3_0", + "INT_INTERFACE_WR1END3" + ], + [ + "DSP_WL1END3_0", + "INT_INTERFACE_WL1END3" + ], + [ + "DSP_SE2A3_0", + "INT_INTERFACE_SE2A3" + ], + [ + "DSP_NW4A2_0", + "INT_INTERFACE_NW4A2" + ], + [ + "DSP_LOGIC_OUTS_B5_0", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "DSP_WW4C0_0", + "INT_INTERFACE_WW4C0" + ], + [ + "DSP_IMUX4_0", + "INT_INTERFACE_IMUX4" + ], + [ + "DSP_SW4A1_0", + "INT_INTERFACE_SW4A1" + ], + [ + "DSP_IMUX12_0", + "INT_INTERFACE_IMUX12" + ], + [ + "DSP_NW4A3_0", + "INT_INTERFACE_NW4A3" + ], + [ + "DSP_SW4END1_0", + "INT_INTERFACE_SW4END1" + ], + [ + "DSP_NE4BEG2_0", + "INT_INTERFACE_NE4BEG2" + ], + [ + "DSP_LOGIC_OUTS_B11_0", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "DSP_WW2END0_0", + "INT_INTERFACE_WW2END0" + ], + [ + "DSP_EE4A2_0", + "INT_INTERFACE_EE4A2" + ], + [ + "DSP_SE4BEG0_0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "DSP_EE2A1_0", + "INT_INTERFACE_EE2A1" + ], + [ + "DSP_WR1END1_0", + "INT_INTERFACE_WR1END1" + ], + [ + "DSP_SW2A3_0", + "INT_INTERFACE_SW2A3" + ], + [ + "DSP_SW2A1_0", + "INT_INTERFACE_SW2A1" + ], + [ + "DSP_IMUX38_0", + "INT_INTERFACE_IMUX38" + ], + [ + "DSP_IMUX47_0", + "INT_INTERFACE_IMUX47" + ], + [ + "DSP_EE2BEG3_0", + "INT_INTERFACE_EE2BEG3" + ], + [ + "DSP_BYP7_0", + "INT_INTERFACE_BYP7" + ], + [ + "DSP_LOGIC_OUTS_B3_0", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "DSP_FAN7_0", + "INT_INTERFACE_FAN7" + ], + [ + "DSP_IMUX2_0", + "INT_INTERFACE_IMUX2" + ], + [ + "DSP_IMUX8_0", + "INT_INTERFACE_IMUX8" + ], + [ + "DSP_WW4A1_0", + "INT_INTERFACE_WW4A1" + ], + [ + "DSP_NE2A3_0", + "INT_INTERFACE_NE2A3" + ], + [ + "DSP_IMUX18_0", + "INT_INTERFACE_IMUX18" + ], + [ + "DSP_BYP4_0", + "INT_INTERFACE_BYP4" + ], + [ + "DSP_LOGIC_OUTS_B12_0", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "DSP_FAN4_0", + "INT_INTERFACE_FAN4" + ], + [ + "DSP_LH7_0", + "INT_INTERFACE_LH7" + ], + [ + "DSP_SE4C0_0", + "INT_INTERFACE_SE4C0" + ], + [ + "DSP_IMUX13_0", + "INT_INTERFACE_IMUX13" + ], + [ + "DSP_FAN6_0", + "INT_INTERFACE_FAN6" + ], + [ + "DSP_EE2A3_0", + "INT_INTERFACE_EE2A3" + ], + [ + "DSP_WW2A3_0", + "INT_INTERFACE_WW2A3" + ], + [ + "DSP_NW4A1_0", + "INT_INTERFACE_NW4A1" + ], + [ + "DSP_IMUX27_0", + "INT_INTERFACE_IMUX27" + ], + [ + "DSP_IMUX9_0", + "INT_INTERFACE_IMUX9" + ], + [ + "DSP_EE4C3_0", + "INT_INTERFACE_EE4C3" + ], + [ + "DSP_WW2END2_0", + "INT_INTERFACE_WW2END2" + ], + [ + "DSP_WW4C1_0", + "INT_INTERFACE_WW4C1" + ], + [ + "DSP_EE4A1_0", + "INT_INTERFACE_EE4A1" + ], + [ + "DSP_NE4BEG0_0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "DSP_CTRL0_0", + "INT_INTERFACE_CTRL0" + ], + [ + "DSP_LOGIC_OUTS_B23_0", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "DSP_LOGIC_OUTS_B21_0", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "DSP_WW2A0_0", + "INT_INTERFACE_WW2A0" + ], + [ + "DSP_LOGIC_OUTS_B8_0", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "DSP_SE2A0_0", + "INT_INTERFACE_SE2A0" + ], + [ + "DSP_WW4END0_0", + "INT_INTERFACE_WW4END0" + ], + [ + "DSP_EE4B1_0", + "INT_INTERFACE_EE4B1" + ], + [ + "DSP_SW4A0_0", + "INT_INTERFACE_SW4A0" + ], + [ + "DSP_LH5_0", + "INT_INTERFACE_LH5" + ], + [ + "DSP_WW4C2_0", + "INT_INTERFACE_WW4C2" + ], + [ + "DSP_EE4B3_0", + "INT_INTERFACE_EE4B3" + ], + [ + "DSP_WW4END3_0", + "INT_INTERFACE_WW4END3" + ], + [ + "DSP_IMUX37_0", + "INT_INTERFACE_IMUX37" + ], + [ + "DSP_NE2A0_0", + "INT_INTERFACE_NE2A0" + ], + [ + "DSP_SE2A2_0", + "INT_INTERFACE_SE2A2" + ], + [ + "DSP_BYP0_0", + "INT_INTERFACE_BYP0" + ], + [ + "DSP_SW2A0_0", + "INT_INTERFACE_SW2A0" + ], + [ + "DSP_IMUX46_0", + "INT_INTERFACE_IMUX46" + ], + [ + "DSP_NW4A0_0", + "INT_INTERFACE_NW4A0" + ], + [ + "DSP_IMUX32_0", + "INT_INTERFACE_IMUX32" + ], + [ + "DSP_LOGIC_OUTS_B13_0", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "DSP_EE2A0_0", + "INT_INTERFACE_EE2A0" + ], + [ + "DSP_LOGIC_OUTS_B10_0", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "DSP_EE4BEG0_0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "DSP_EE4A3_0", + "INT_INTERFACE_EE4A3" + ], + [ + "DSP_EE4B2_0", + "INT_INTERFACE_EE4B2" + ], + [ + "DSP_BYP6_0", + "INT_INTERFACE_BYP6" + ], + [ + "DSP_NE4C0_0", + "INT_INTERFACE_NE4C0" + ], + [ + "DSP_LOGIC_OUTS_B4_0", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "DSP_LOGIC_OUTS_B0_0", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "DSP_SE4BEG2_0", + "INT_INTERFACE_SE4BEG2" + ], + [ + "DSP_WW4B0_0", + "INT_INTERFACE_WW4B0" + ], + [ + "DSP_SW2A2_0", + "INT_INTERFACE_SW2A2" + ], + [ + "DSP_IMUX21_0", + "INT_INTERFACE_IMUX21" + ], + [ + "DSP_NW4END0_0", + "INT_INTERFACE_NW4END0" + ], + [ + "DSP_IMUX11_0", + "INT_INTERFACE_IMUX11" + ], + [ + "DSP_IMUX6_0", + "INT_INTERFACE_IMUX6" + ], + [ + "DSP_IMUX40_0", + "INT_INTERFACE_IMUX40" + ], + [ + "DSP_CTRL1_0", + "INT_INTERFACE_CTRL1" + ], + [ + "DSP_NW4END1_0", + "INT_INTERFACE_NW4END1" + ], + [ + "DSP_IMUX14_0", + "INT_INTERFACE_IMUX14" + ], + [ + "DSP_NW2A2_0", + "INT_INTERFACE_NW2A2" + ], + [ + "DSP_ER1BEG0_0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "DSP_IMUX7_0", + "INT_INTERFACE_IMUX7" + ], + [ + "DSP_SW4A3_0", + "INT_INTERFACE_SW4A3" + ], + [ + "DSP_WW4A0_0", + "INT_INTERFACE_WW4A0" + ], + [ + "DSP_NW4END2_0", + "INT_INTERFACE_NW4END2" + ], + [ + "DSP_NE2A1_0", + "INT_INTERFACE_NE2A1" + ], + [ + "DSP_NW2A3_0", + "INT_INTERFACE_NW2A3" + ], + [ + "DSP_IMUX45_0", + "INT_INTERFACE_IMUX45" + ], + [ + "DSP_IMUX24_0", + "INT_INTERFACE_IMUX24" + ], + [ + "DSP_IMUX25_0", + "INT_INTERFACE_IMUX25" + ], + [ + "DSP_SW4END0_0", + "INT_INTERFACE_SW4END0" + ], + [ + "DSP_EE2BEG2_0", + "INT_INTERFACE_EE2BEG2" + ], + [ + "DSP_LOGIC_OUTS_B16_0", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "DSP_CLK1_0", + "INT_INTERFACE_CLK1" + ], + [ + "DSP_WR1END0_0", + "INT_INTERFACE_WR1END0" + ], + [ + "DSP_IMUX31_0", + "INT_INTERFACE_IMUX31" + ], + [ + "DSP_WW2END3_0", + "INT_INTERFACE_WW2END3" + ], + [ + "DSP_IMUX16_0", + "INT_INTERFACE_IMUX16" + ], + [ + "DSP_LOGIC_OUTS_B1_0", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "DSP_IMUX42_0", + "INT_INTERFACE_IMUX42" + ], + [ + "DSP_ER1BEG1_0", + "INT_INTERFACE_ER1BEG1" + ], + [ + "DSP_LH10_0", + "INT_INTERFACE_LH10" + ], + [ + "DSP_EE2BEG1_0", + "INT_INTERFACE_EE2BEG1" + ], + [ + "DSP_LOGIC_OUTS_B9_0", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "DSP_NE4C3_0", + "INT_INTERFACE_NE4C3" + ], + [ + "DSP_LOGIC_OUTS_B6_0", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "DSP_WW4B1_0", + "INT_INTERFACE_WW4B1" + ], + [ + "DSP_LOGIC_OUTS_B7_0", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "DSP_IMUX5_0", + "INT_INTERFACE_IMUX5" + ], + [ + "DSP_IMUX41_0", + "INT_INTERFACE_IMUX41" + ], + [ + "DSP_LH9_0", + "INT_INTERFACE_LH9" + ] + ], + "tile_types": [ + "DSP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -6 + ], + "wire_pairs": [ + [ + "PCIE_EE4B0_16", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX45_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_NW4A1_16", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_16", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_IMUX21_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_EE4BEG0_16", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_FAN4_R_16", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_CLK1_R_16", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_16", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_WW4B3_16", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_IMUX30_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_WW2A1_16", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_IMUX39_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_IMUX47_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_SE2A1_16", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_IMUX10_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_IMUX8_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_IMUX2_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_EE2A1_16", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_CLK0_R_16", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_IMUX4_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_IMUX43_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_NE4C0_16", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_16", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_16", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_SW4END3_16", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_NW4END3_16", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_FAN5_R_16", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_NW4A0_16", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_EE2A3_16", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_EE4B2_16", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_16", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_NW2A0_16", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_16", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_EE4B1_16", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_IMUX16_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_NE2A0_16", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_EE2BEG0_16", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_EL1BEG2_16", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_IMUX28_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_IMUX17_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_WW2END2_16", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_16", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_WW4C2_16", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_LH1_16", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_FAN6_R_16", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_WW4A3_16", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_16", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_SE4C3_16", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_WW4A0_16", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_IMUX29_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_IMUX33_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_EL1BEG3_16", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_SE4BEG2_16", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_IMUX36_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_IMUX22_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_LH10_16", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_NE4BEG2_16", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_IMUX23_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_EE2A0_16", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_SW4END2_16", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_16", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_NE4C3_16", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_WW4B1_16", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_EE4C2_16", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_WW4B0_16", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_IMUX24_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_LH5_16", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_SW4A3_16", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_WW2A0_16", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_IMUX40_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_WR1END1_16", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_BYP7_R_16", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_IMUX32_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_SE4BEG1_16", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_16", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_SE4BEG0_16", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_NW2A2_16", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_EE2A2_16", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_IMUX19_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_EE2BEG1_16", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_BYP6_R_16", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_FAN3_R_16", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_16", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_NE4BEG3_16", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_EE2BEG2_16", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_NW2A1_16", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_EE4A0_16", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_IMUX34_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_SE2A0_16", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_BYP4_R_16", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_IMUX0_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_SE4BEG3_16", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_ER1BEG1_16", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_NE4BEG0_16", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_CTRL0_R_16", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_EE4BEG3_16", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_LH3_16", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_EE4A2_16", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_WW4B2_16", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_16", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_WW4A1_16", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_EE4A3_16", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_SE2A3_16", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_SE4C2_16", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_IMUX42_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_16", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_FAN0_R_16", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_SE4C0_16", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_CTRL1_R_16", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_IMUX5_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_WW4C0_16", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_FAN1_R_16", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_WW2END3_16", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_WL1END0_16", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_FAN7_R_16", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_IMUX41_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_WW4C3_16", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_NW2A3_16", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_SW4A0_16", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_16", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_EE4A1_16", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_IMUX35_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_IMUX9_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_FAN2_R_16", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_NW4END1_16", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_SW2A1_16", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_BYP0_R_16", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_NW4END2_16", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_EL1BEG0_16", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_NE4C2_16", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_IMUX14_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_IMUX15_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_16", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_NW4A3_16", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_EL1BEG1_16", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_WW2END0_16", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_NE2A2_16", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_IMUX13_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_IMUX7_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_WW4END2_16", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_WR1END2_16", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_WR1END0_16", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_WW4END3_16", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_WW4END1_16", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_IMUX38_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_NW4END0_16", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_ER1BEG0_16", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_EE4BEG2_16", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX46_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_EE2BEG3_16", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_IMUX1_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_EE4C3_16", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_16", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_NW4A2_16", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_WL1END3_16", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_16", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_SW4END0_16", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_BYP2_R_16", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_IMUX31_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_LH9_16", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_WW2END1_16", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_IMUX20_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_WL1END1_16", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_16", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_IMUX25_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_BYP5_R_16", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_16", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_WW4A2_16", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_NE4C1_16", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_16", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_ER1BEG2_16", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_LH8_16", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4B3_16", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_SE4C1_16", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_LH4_16", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_LH7_16", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_WW2A3_16", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_EE4C1_16", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_LH11_16", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_16", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_IMUX18_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_16", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_SW4END1_16", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_SW2A2_16", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_16", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_LH6_16", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_NE4BEG1_16", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX37_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_IMUX12_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_WW4END0_16", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_IMUX26_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_EE4BEG1_16", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_ER1BEG3_16", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_SW2A0_16", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX11_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_IMUX6_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_IMUX44_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_SW4A2_16", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_WW4C1_16", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_16", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_IMUX27_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_SW4A1_16", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_BYP3_R_16", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_SE2A2_16", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_WW2A2_16", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_WR1END3_16", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_NE2A3_16", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_NE2A1_16", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_LH12_16", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_EE4C0_16", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX3_R_16", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_WL1END2_16", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_LH2_16", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_SW2A3_16", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_BYP1_R_16", + "INT_INTERFACE_BYP1" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_LOGIC_OUTS20_9", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "CMT_FIFO_SE2A3_9", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_SW2A2_9", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_L_FAN4_9", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_LH7_9", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_ER1BEG0_9", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_9", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "CMT_FIFO_EE2BEG0_9", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_FAN5_9", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_WR1END1_9", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_EE2A2_9", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_SW2A1_9", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_L_IMUX13_9", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_EE4A2_9", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_LH6_9", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_WW4END3_9", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_L_BYP5_9", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_NW4A0_9", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_L_IMUX15_9", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_IMUX21_9", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_L_IMUX22_9", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_SW4END3_9", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_LH12_9", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_NE4BEG3_9", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_NE2A3_9", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_9", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "CMT_FIFO_WW2A0_9", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_L_IMUX16_9", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_LH11_9", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_L_FAN1_9", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_L_FAN7_9", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_SW4A2_9", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_L_IMUX37_9", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_9", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CMT_FIFO_EE2BEG1_9", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_SE2A0_9", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_L_IMUX41_9", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_CTRL0_9", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_ER1BEG3_9", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_SW4END2_9", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_SW4A3_9", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_WW4A3_9", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_EE4C0_9", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_LH10_9", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_EE4C1_9", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_SW2A0_9", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_L_FAN6_9", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_NE4C2_9", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_NW4END3_9", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_9", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CMT_FIFO_WW2END2_9", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_9", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CMT_FIFO_L_IMUX32_9", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_EE4BEG1_9", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_L_IMUX28_9", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_L_BYP6_9", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_L_IMUX1_9", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_SE2A1_9", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_SE4C1_9", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_WW4END2_9", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_9", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "CMT_FIFO_EE4A0_9", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_EE4C2_9", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_L_IMUX9_9", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX5_9", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_L_IMUX2_9", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_EE2A0_9", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_SE4BEG2_9", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_LH2_9", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_WW4END0_9", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_IMUX12_9", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_9", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "CMT_FIFO_L_IMUX33_9", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_SE4BEG1_9", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX25_9", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_EE4C3_9", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_ER1BEG2_9", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_IMUX10_9", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_L_IMUX36_9", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_SE4C0_9", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_L_IMUX42_9", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_FAN0_9", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_9", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "CMT_FIFO_NW4END2_9", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_IMUX39_9", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_NE4C3_9", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_L_IMUX34_9", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_L_IMUX27_9", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_L_BYP3_9", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_EE4A3_9", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_IMUX23_9", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_L_IMUX14_9", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_WW4END1_9", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_NE4C0_9", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_SW2A3_9", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_L_IMUX20_9", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_EL1BEG0_9", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_NE4BEG1_9", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX30_9", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_L_IMUX43_9", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_L_CLK0_9", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_NW4A2_9", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_LH8_9", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_9", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_9", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CMT_FIFO_EL1BEG3_9", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_WW4B2_9", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_L_IMUX11_9", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_L_CTRL1_9", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_NE4C1_9", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_NW2A2_9", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_EE2A3_9", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_WL1END3_9", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_WW4A0_9", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_EE4A1_9", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_NE4BEG0_9", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_WR1END3_9", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_9", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "CMT_FIFO_SW4END0_9", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_WW4B0_9", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_WW4A1_9", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_L_IMUX6_9", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_L_IMUX47_9", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_EE4BEG2_9", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_WW4C2_9", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_IMUX8_9", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_9", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CMT_FIFO_L_IMUX46_9", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_WR1END2_9", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_9", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "CMT_FIFO_EE4B3_9", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_L_IMUX7_9", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_L_CLK1_9", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_9", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_9", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "CMT_FIFO_L_IMUX35_9", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_EE2BEG3_9", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_L_BYP1_9", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_L_IMUX38_9", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_EE4B1_9", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_WW2END1_9", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_L_IMUX44_9", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_NW4END1_9", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_WW2END3_9", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_SE4C3_9", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_IMUX40_9", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_WL1END0_9", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_LH9_9", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_WW4B1_9", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_WW2END0_9", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_LH4_9", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_9", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CMT_FIFO_NE2A2_9", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_9", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CMT_FIFO_WW4B3_9", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_L_IMUX24_9", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_NW4A1_9", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_L_BYP2_9", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_LH1_9", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_WW4C1_9", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_L_IMUX4_9", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_NW4END0_9", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_L_IMUX31_9", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_NW2A0_9", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_EE4BEG0_9", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_SW4END1_9", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_LH5_9", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_L_IMUX18_9", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_L_BYP7_9", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_EL1BEG2_9", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_EE2BEG2_9", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_9", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CMT_FIFO_L_IMUX3_9", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_NE4BEG2_9", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_WW2A1_9", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_9", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "CMT_FIFO_WW2A2_9", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_NW2A3_9", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_SE4C2_9", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_SE4BEG0_9", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_L_BYP4_9", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_9", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CMT_FIFO_L_IMUX19_9", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_WR1END0_9", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_NW2A1_9", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_L_IMUX29_9", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_WW4C0_9", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_EE2A1_9", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_L_BYP0_9", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_WL1END2_9", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_L_IMUX17_9", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_NW4A3_9", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_WW4A2_9", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_LH3_9", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_L_IMUX0_9", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_ER1BEG1_9", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_FAN3_9", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_L_FAN2_9", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_SE2A2_9", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_NE2A0_9", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_IMUX26_9", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_9", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CMT_FIFO_SW4A0_9", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_NE2A1_9", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_EE4BEG3_9", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_WW2A3_9", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_SE4BEG3_9", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_SW4A1_9", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_EE4B0_9", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_WL1END1_9", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_9", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CMT_FIFO_EL1BEG1_9", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_9", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CMT_FIFO_L_IMUX45_9", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_WW4C3_9", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_EE4B2_9", + "INT_INTERFACE_EE4B2" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -7 + ], + "wire_pairs": [ + [ + "CMT_TOP_EE2A1_15", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW4B1_15", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_NW4END0_15", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_EE4B0_15", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WL1END0_15", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SW4A3_15", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WL1END3_15", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NE2A2_15", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_SW2A3_15", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH5_15", + "VBRK_LH5" + ], + [ + "CMT_TOP_NW4END1_15", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A1_15", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EE2A0_15", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_WR1END3_15", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW4B2_15", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4A2_15", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_SE2A0_15", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NE4C0_15", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_NW2A0_15", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG2_15", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_NW4A0_15", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_SW2A0_15", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NW4A1_15", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE4C2_15", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2BEG3_15", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4C3_15", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW2A3_15", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WR1END0_15", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_NW4END2_15", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4C2_15", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SW4END0_15", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_LH1_15", + "VBRK_LH1" + ], + [ + "CMT_TOP_MONITOR_N_15", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WW4END3_15", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE2A3_15", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4BEG1_15", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WL1END2_15", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_SE4BEG2_15", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4C3_15", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE4BEG1_15", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_WW4C0_15", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4A3_15", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_WW2A1_15", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW2A3_15", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4BEG3_15", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NW4A2_15", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_WW4END0_15", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EE4A0_15", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_SE4BEG1_15", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2A2_15", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4C2_15", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW2A2_15", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SE4C3_15", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_SE2A1_15", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_LH8_15", + "VBRK_LH8" + ], + [ + "CMT_TOP_LH7_15", + "VBRK_LH7" + ], + [ + "CMT_TOP_SW2A2_15", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4B1_15", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_LH12_15", + "VBRK_LH12" + ], + [ + "CMT_TOP_NE4BEG0_15", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_EL1BEG2_15", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_ER1BEG1_15", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_NE2A1_15", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_WW4B0_15", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END2_15", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_LH9_15", + "VBRK_LH9" + ], + [ + "CMT_TOP_SE4C1_15", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE4C1_15", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG0_15", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_LH4_15", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW4A3_15", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_SE4C0_15", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_WW4END2_15", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_WW4A2_15", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG0_15", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_SW4A2_15", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EE4BEG3_15", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW2A2_15", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4A0_15", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_SW4END3_15", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SW4END1_15", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_WW2A0_15", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WR1END1_15", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH6_15", + "VBRK_LH6" + ], + [ + "CMT_TOP_NW2A1_15", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_LH3_15", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C1_15", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE2BEG1_15", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SW4A1_15", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE4BEG2_15", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW4END3_15", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EL1BEG3_15", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW2END3_15", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_ER1BEG0_15", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SE4BEG3_15", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH10_15", + "VBRK_LH10" + ], + [ + "CMT_TOP_LH11_15", + "VBRK_LH11" + ], + [ + "CMT_TOP_NE2A3_15", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WL1END1_15", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW4C1_15", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_EE4C0_15", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WW2END0_15", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2END1_15", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4B3_15", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW4END2_15", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_WW4END1_15", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_WW4A1_15", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE2BEG0_15", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_ER1BEG2_15", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_NW4A3_15", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SE2A2_15", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4A0_15", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_SW2A1_15", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_SE4C2_15", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE2A0_15", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_MONITOR_P_15", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW4B3_15", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4B2_15", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_WW4C3_15", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_LH2_15", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE2A3_15", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4BEG0_15", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_WR1END2_15", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_ER1BEG3_15", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE2BEG2_15", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EL1BEG1_15", + "VBRK_EL1BEG1" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX15_8", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX45_8", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX12_8", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B4_8", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B2_8", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_FAN2_8", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_LOGIC_OUTS_B0_8", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_BYP5_8", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX39_8", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX40_8", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B9_8", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX16_8", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX0_8", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX13_8", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX14_8", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX10_8", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX20_8", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX38_8", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_FAN5_8", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX46_8", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP6_8", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX2_8", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_LOGIC_OUTS_B10_8", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX5_8", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX19_8", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX41_8", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B15_8", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_LOGIC_OUTS_B7_8", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B20_8", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_FAN6_8", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX23_8", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX44_8", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_LOGIC_OUTS_B6_8", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX28_8", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX22_8", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX47_8", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX21_8", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX1_8", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX27_8", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_FAN0_8", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX9_8", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_FAN1_8", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B8_8", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_BYP7_8", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX18_8", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_BYP3_8", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B11_8", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_LOGIC_OUTS_B22_8", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B23_8", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX8_8", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX4_8", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_CLK1_8", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX24_8", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B1_8", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX7_8", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX31_8", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX6_8", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B18_8", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX32_8", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B16_8", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_FAN7_8", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX30_8", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX34_8", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX26_8", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_LOGIC_OUTS_B21_8", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_CLK0_8", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX17_8", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX35_8", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_LOGIC_OUTS_B13_8", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_BYP4_8", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_LOGIC_OUTS_B19_8", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX11_8", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP0_8", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX36_8", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX25_8", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B3_8", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX29_8", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_CTRL1_8", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX43_8", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_BYP2_8", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX33_8", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_CTRL0_8", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX42_8", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_FAN3_8", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_LOGIC_OUTS_B14_8", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_LOGIC_OUTS_B17_8", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B5_8", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX3_8", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX37_8", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_BYP1_8", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B12_8", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_FAN4_8", + "VBRK_EXT_FAN4" + ] + ], + "tile_types": [ + "GTX_CHANNEL_2", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "CLK_HROW_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_LH10_3", + "VBRK_LH10" + ], + [ + "CLK_HROW_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_LH7_3", + "VBRK_LH7" + ], + [ + "CLK_HROW_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_LH1_3", + "VBRK_LH1" + ], + [ + "CLK_HROW_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_LH4_3", + "VBRK_LH4" + ], + [ + "CLK_HROW_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_LH8_3", + "VBRK_LH8" + ], + [ + "CLK_HROW_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_LH6_3", + "VBRK_LH6" + ], + [ + "CLK_HROW_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_LH9_3", + "VBRK_LH9" + ], + [ + "CLK_HROW_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_LH3_3", + "VBRK_LH3" + ], + [ + "CLK_HROW_LH11_3", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH12_3", + "VBRK_LH12" + ], + [ + "CLK_HROW_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_EL1BEG1_3", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_LH2_3", + "VBRK_LH2" + ], + [ + "CLK_HROW_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_LH5_3", + "VBRK_LH5" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_RCLK_DIV_CE0", + "IOI_RCLK_DIV_CE0" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_I2IOCLK_TOP0", + "LIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0" + ], + [ + "HCLK_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "LIOI_I2GCLK_TOP1" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IDELAYCTRL_UPPULSEOUT" + ], + [ + "HCLK_RCLK_DIV_CE1", + "IOI_RCLK_DIV_CE1" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_RCLK_IMUX1", + "IOI_IMUX_RC1" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_RCLK_IMUX0", + "IOI_IMUX_RC0" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_IDELAYCTRL_RST", + "IOI_IDELAYCTRL_RST" + ], + [ + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IDELAYCTRL_DNPULSEOUT" + ] + ], + "tile_types": [ + "HCLK_IOI3", + "LIOI3" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4B0_9", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_EE4A1_9", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EE4BEG3_9", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WW2END0_9", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WW4C3_9", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE2BEG3_9", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NW2A3_9", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_EE4A0_9", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_SE4BEG3_9", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_NW4END2_9", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_EL1BEG1_9", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SW4A0_9", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_NE2A3_9", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_NE2A2_9", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_NE4BEG0_9", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_SW2A2_9", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_LH3_9", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SW4END3_9", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_WW4B1_9", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_EE4C3_9", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_NE4C1_9", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_EE2A1_9", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_NE4C3_9", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WW4A3_9", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_SW4A1_9", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_LH10_9", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WW2END2_9", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SE4BEG1_9", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_LH9_9", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_SE4BEG2_9", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_EE4B2_9", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE4B3_9", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NE4BEG1_9", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WR1END1_9", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_EL1BEG2_9", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_NW2A0_9", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_LH11_9", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EE2BEG1_9", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_SW2A1_9", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_LH1_9", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_LH2_9", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_SE2A2_9", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_ER1BEG2_9", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_LH5_9", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE2BEG0_9", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4B3_9", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_WR1END2_9", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_NE2A1_9", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NW4A3_9", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_SW2A3_9", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_WW4A0_9", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SE4C1_9", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_WW4B0_9", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_ER1BEG3_9", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_SE2A0_9", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SE4C2_9", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_NW4A2_9", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NE2A0_9", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_WW2END1_9", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE2A0_9", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_EE4C1_9", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EL1BEG3_9", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WL1END1_9", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_NW4A1_9", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WW2A0_9", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WW2END3_9", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_NE4C0_9", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_ER1BEG1_9", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SE4C3_9", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WL1END0_9", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SW2A0_9", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WR1END3_9", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE2BEG2_9", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_EE4A3_9", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE4BEG1_9", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_EE4A2_9", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_LH4_9", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE4C2_9", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_WW2A1_9", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WW4B2_9", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE4C0_9", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WW4A2_9", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WW4END3_9", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4END2_9", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_NW4END3_9", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_EE4BEG0_9", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WW2A2_9", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WW4C0_9", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NE4BEG2_9", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_NW2A2_9", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_LH8_9", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW2A3_9", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_NW4A0_9", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_LH6_9", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_EE4BEG2_9", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SW4A2_9", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_SE4BEG0_9", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_LH7_9", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4C2_9", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_WW4C1_9", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_LH12_9", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW4A1_9", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_SW4END1_9", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_NW4END0_9", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_ER1BEG0_9", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_WR1END0_9", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_EE4B1_9", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NE4C2_9", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_SE4C0_9", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_WW4END0_9", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_NW4END1_9", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_EL1BEG0_9", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE2A3_9", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NE4BEG3_9", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW4END1_9", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_SE2A3_9", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SW4A3_9", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE2A2_9", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_SW4END0_9", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_SW4END2_9", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WL1END3_9", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_NW2A1_9", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_WL1END2_9", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SE2A1_9", + "INT_FEEDTHRU_2_SE2A1" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -8 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SE4C2_8", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WL1END1_8", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_SE4BEG1_8", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_IMUX40_8", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_BYP1_8", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SE2A0_8", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_EL1BEG1_8", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_IMUX21_8", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_IMUX23_8", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NW2A3_8", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_LH11_8", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_SW2A0_8", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_IMUX44_8", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_NW4A3_8", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_WW2END2_8", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_IMUX16_8", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WW4C0_8", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX18_8", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_BYP3_8", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_WR1END2_8", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_IMUX8_8", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW4END3_8", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_LH5_8", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX31_8", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_SW2A3_8", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_LH6_8", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_NE2A2_8", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WR1END3_8", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_SE4C1_8", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_LH3_8", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_SW4A0_8", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_IMUX37_8", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SE4BEG2_8", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_FAN6_8", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_NW2A0_8", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_EE4C3_8", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE2BEG2_8", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_EE4A3_8", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX45_8", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX24_8", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_NE4C3_8", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_IMUX38_8", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_NE4C2_8", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_NW4A0_8", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX12_8", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_WW2A0_8", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_WW2END0_8", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_ER1BEG1_8", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_IMUX15_8", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_EE4B0_8", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_EE4BEG0_8", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_BYP0_8", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_WW2A2_8", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_EE2A3_8", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_IMUX13_8", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_IMUX42_8", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX25_8", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_WW4A0_8", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX33_8", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_BYP7_8", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_NW4END0_8", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_EE4B1_8", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_SE2A1_8", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_IMUX9_8", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX27_8", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX6_8", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_WR1END1_8", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_FAN0_8", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX3_8", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_NW2A1_8", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_CTRL0_8", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX32_8", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_8", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_IMUX26_8", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_CLK0_8", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX36_8", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_BYP4_8", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_NW4END1_8", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_EE2BEG1_8", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX14_8", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_IMUX20_8", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_FAN3_8", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_SW4END3_8", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_WW4C2_8", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WW4A3_8", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WL1END3_8", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_IMUX39_8", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_EE4C0_8", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_FAN2_8", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_NE2A1_8", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX0_8", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW4END1_8", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_NW4END2_8", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_WW4A2_8", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_NE4C1_8", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_EE2BEG0_8", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX22_8", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_BYP6_8", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_WW4C1_8", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_ER1BEG3_8", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_WL1END2_8", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WW4B0_8", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_EE4B3_8", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_LH8_8", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_IMUX28_8", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_FAN5_8", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_NW4A2_8", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_EL1BEG3_8", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_SW2A2_8", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_EE4C2_8", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX2_8", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_WL1END0_8", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_CTRL1_8", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_8", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_LH7_8", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_SW4END2_8", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_NE4BEG0_8", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_EE2A1_8", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_NE4BEG1_8", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_EE4A2_8", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX17_8", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_ER1BEG2_8", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX30_8", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_NW4A1_8", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SE4BEG0_8", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_IMUX1_8", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX10_8", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SE4C0_8", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_SE4BEG3_8", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_EE4B2_8", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX29_8", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX34_8", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_8", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_ER1BEG0_8", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_SW4END1_8", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_LH1_8", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NW4END3_8", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_EL1BEG2_8", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_8", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_IMUX7_8", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_EE2A2_8", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_SW4A3_8", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EE4BEG3_8", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX46_8", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_EE4A1_8", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_8", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_IMUX43_8", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX4_8", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_8", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_EE4A0_8", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_LH12_8", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX41_8", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_SW2A1_8", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_NE4BEG3_8", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_SE4C3_8", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX11_8", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_EE2A0_8", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_EE4BEG1_8", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_BYP2_8", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_IMUX5_8", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WW4C3_8", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NE2A0_8", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_EE2BEG3_8", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_CLK1_8", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_WR1END0_8", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_WW4B2_8", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_LH10_8", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW2END1_8", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_EL1BEG0_8", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_WW4END0_8", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_SE2A2_8", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_FAN4_8", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_8", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_WW4END2_8", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_SW4END0_8", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX35_8", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_LH2_8", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_SW4A2_8", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NW2A2_8", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_BYP5_8", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_WW4A1_8", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_NE4C0_8", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_FAN1_8", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_WW2A1_8", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_NE4BEG2_8", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW4B3_8", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_WW4B1_8", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_EE4BEG2_8", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_LH4_8", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_WW2END3_8", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW2A3_8", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_FAN7_8", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_NE2A3_8", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX19_8", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_EE4C1_8", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX47_8", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_LH9_8", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_SE2A3_8", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_8", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_SW4A1_8", + "VFRAME_SW4A1" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + -6 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE2A3_16", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_SE4C2_16", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_EL1BEG2_16", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_LH8_16", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_LH2_16", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_WW4END0_16", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WW4B2_16", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_NW2A2_16", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_EE2A0_16", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW4A3_16", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NE4BEG3_16", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WL1END3_16", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_WR1END1_16", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_EE4C2_16", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_EL1BEG0_16", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EE2A1_16", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_EE4A2_16", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_WL1END2_16", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WW4B3_16", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_WR1END3_16", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_SW2A2_16", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_EE4BEG2_16", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SE4C1_16", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_EE4BEG3_16", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_LH1_16", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_SW2A1_16", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_NE4BEG0_16", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_WW4C1_16", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_WW4END1_16", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_SW4END3_16", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_EE4BEG0_16", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NE2A3_16", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_WW2END0_16", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_EE4C1_16", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_WW4A0_16", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE4A0_16", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_LH6_16", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WW2A2_16", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NW4A0_16", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SW2A0_16", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_NE4C2_16", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_SE4BEG2_16", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_SE4C0_16", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_SE2A0_16", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_WL1END0_16", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SW4END1_16", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EE4BEG1_16", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_NW4A1_16", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SW4A1_16", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_LH10_16", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_NE2A1_16", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_SE2A1_16", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_EL1BEG3_16", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WW2END3_16", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_WW2A1_16", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WW4C2_16", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_EE2BEG3_16", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NW4A2_16", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NW4END2_16", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WW4A2_16", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WR1END2_16", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_NW2A1_16", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_NE4BEG1_16", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_SE4C3_16", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_NW4END0_16", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SW4END2_16", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SE2A2_16", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4A3_16", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_LH11_16", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_NW4END1_16", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NE4C0_16", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_WW2A0_16", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WR1END0_16", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH9_16", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_EE4B1_16", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EL1BEG1_16", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW4END3_16", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_SE4BEG3_16", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_ER1BEG2_16", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_ER1BEG1_16", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_NW2A0_16", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_EE4C3_16", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_EE4B0_16", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH4_16", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SW2A3_16", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_NE4BEG2_16", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_WW4B0_16", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_WW4END2_16", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_WW2A3_16", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WW4B1_16", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_SW4A3_16", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE2A2_16", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WL1END1_16", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_SE2A3_16", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SW4END0_16", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_NE2A2_16", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE2BEG2_16", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NE4C3_16", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_EE4B3_16", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SW4A0_16", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_SE4BEG0_16", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_EE4A1_16", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NW2A3_16", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE4C1_16", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW4C0_16", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_LH5_16", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_ER1BEG3_16", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_NW4A3_16", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_LH7_16", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_EE2BEG1_16", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_LH12_16", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_SW4A2_16", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_WW2END2_16", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_LH3_16", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_EE2BEG0_16", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW2END1_16", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_SE4BEG1_16", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_NW4END3_16", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW4C3_16", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE4B2_16", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE4C0_16", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_NE2A0_16", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_WW4A1_16", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_ER1BEG0_16", + "INT_FEEDTHRU_2_ER1BEG0" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLK_HROW_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_SW4A1_0", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_LH4_0", + "VBRK_LH4" + ], + [ + "CLK_HROW_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_LH11_0", + "VBRK_LH11" + ], + [ + "CLK_HROW_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_LH6_0", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_LH1_0", + "VBRK_LH1" + ], + [ + "CLK_HROW_LH10_0", + "VBRK_LH10" + ], + [ + "CLK_HROW_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_LH5_0", + "VBRK_LH5" + ], + [ + "CLK_HROW_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_LH8_0", + "VBRK_LH8" + ], + [ + "CLK_HROW_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_LH2_0", + "VBRK_LH2" + ], + [ + "CLK_HROW_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_LH12_0", + "VBRK_LH12" + ], + [ + "CLK_HROW_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_LH3_0", + "VBRK_LH3" + ], + [ + "CLK_HROW_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_LH7_0", + "VBRK_LH7" + ], + [ + "CLK_HROW_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_LH9_0", + "VBRK_LH9" + ], + [ + "CLK_HROW_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_WW4C2_0", + "VBRK_WW4C2" + ] + ], + "tile_types": [ + "CLK_BUFG_TOP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CLK_HROW_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_LH2_4", + "VBRK_LH2" + ], + [ + "CLK_HROW_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_LH8_4", + "VBRK_LH8" + ], + [ + "CLK_HROW_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_LH1_4", + "VBRK_LH1" + ], + [ + "CLK_HROW_LH10_4", + "VBRK_LH10" + ], + [ + "CLK_HROW_LH6_4", + "VBRK_LH6" + ], + [ + "CLK_HROW_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_LH12_4", + "VBRK_LH12" + ], + [ + "CLK_HROW_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_LH5_4", + "VBRK_LH5" + ], + [ + "CLK_HROW_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_LH4_4", + "VBRK_LH4" + ], + [ + "CLK_HROW_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_MONITOR_N_4", + "VBRK_MONITOR_N" + ], + [ + "CLK_HROW_LH3_4", + "VBRK_LH3" + ], + [ + "CLK_HROW_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_LH7_4", + "VBRK_LH7" + ], + [ + "CLK_HROW_LH11_4", + "VBRK_LH11" + ], + [ + "CLK_HROW_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_MONITOR_P_4", + "VBRK_MONITOR_P" + ], + [ + "CLK_HROW_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_LH9_4", + "VBRK_LH9" + ], + [ + "CLK_HROW_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_NE2A0_4", + "VBRK_NE2A0" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 6 + ], + "wire_pairs": [ + [ + "CMT_FIFO_NE4BEG0_0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_WW4A0_0", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_L_CLK1_0", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_WW4B0_0", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_L_IMUX11_0", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_LH7_0", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_0", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_L_BYP1_0", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_L_IMUX12_0", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_0", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "CMT_FIFO_L_IMUX16_0", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_EE4C2_0", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_NE2A0_0", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_SW4A2_0", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_SW4END1_0", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_EE4B2_0", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_NE2A1_0", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_SW2A0_0", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_EE2A0_0", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_FAN2_0", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_EE2BEG3_0", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_ER1BEG3_0", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_WL1END0_0", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_FAN0_0", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_WR1END0_0", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_NW4END2_0", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_IMUX20_0", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_0", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "CMT_FIFO_MONITOR_P_0", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CMT_FIFO_EE2BEG2_0", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_NE4BEG1_0", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_0", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "FIFO_DQS_IOTOPHASER_66", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "CMT_FIFO_LH6_0", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_SE4C3_0", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_WW2END2_0", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_0", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "CMT_FIFO_NW2A2_0", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_LH2_0", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_SE4BEG3_0", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX18_0", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_L_IMUX44_0", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_IMUX22_0", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_L_IMUX40_0", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_SE2A1_0", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_L_IMUX26_0", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_NE4C2_0", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_WR1END1_0", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_0", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "CMT_FIFO_WW2A0_0", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_L_IMUX14_0", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_ER1BEG0_0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_0", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "CMT_FIFO_WW2END3_0", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_EE2A2_0", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_NW4END3_0", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_L_IMUX29_0", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_SE2A2_0", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_EE4BEG1_0", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_SW4A3_0", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_NW4A0_0", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_NE4C0_0", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_0", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "CMT_FIFO_WL1END3_0", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_SW4A1_0", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_L_IMUX39_0", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_WL1END2_0", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_0", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "CMT_FIFO_L_IMUX23_0", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_0", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "CMT_FIFO_EE4A2_0", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_WL1END1_0", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_L_IMUX46_0", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_EE4C0_0", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_L_FAN6_0", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_L_BYP5_0", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_L_IMUX36_0", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_WW4B3_0", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_SE4BEG1_0", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_0", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "CMT_FIFO_LH12_0", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_L_IMUX9_0", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_FAN1_0", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_L_IMUX1_0", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_CTRL0_0", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_L_IMUX32_0", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_0", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "CMT_FIFO_SW4END2_0", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_L_IMUX25_0", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_SW4END3_0", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_WW2A3_0", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_EE2BEG1_0", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_WW2A1_0", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_EL1BEG0_0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_L_IMUX45_0", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_WW2END0_0", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_NE4C1_0", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_EE4C3_0", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_L_CLK0_0", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_L_IMUX35_0", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_SW2A1_0", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_0", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "CMT_FIFO_L_IMUX31_0", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_WW4END3_0", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_L_BYP7_0", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_WW4C3_0", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_NW2A1_0", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_0", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "CMT_FIFO_EE4BEG2_0", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_NW4A3_0", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_SW4END0_0", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_0", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "CMT_FIFO_SW2A3_0", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_0", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "CMT_FIFO_NW4A1_0", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_WR1END3_0", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_EE4A1_0", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_0", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "CMT_FIFO_L_IMUX2_0", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_L_IMUX42_0", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_NW2A3_0", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_NW4END1_0", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_WW4A3_0", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_0", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "CMT_FIFO_SW4A0_0", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_0", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "CMT_FIFO_WW4C0_0", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_NE4C3_0", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_SE2A0_0", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_WW4B2_0", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_L_CTRL1_0", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_L_IMUX4_0", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_L_IMUX34_0", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_SE4C0_0", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_EE2BEG0_0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_WW4C2_0", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_EE4B0_0", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_0", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "CMT_FIFO_LH1_0", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_NE2A3_0", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_NE2A2_0", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_L_IMUX7_0", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_0", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "CMT_FIFO_L_BYP6_0", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_L_IMUX0_0", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_EE4C1_0", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_L_IMUX5_0", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_SW2A2_0", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_L_IMUX27_0", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_NW4END0_0", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_SE4C2_0", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_EE4BEG3_0", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX8_0", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_IMUX38_0", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_LH5_0", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_WW4END0_0", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_LH11_0", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_EE4BEG0_0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX43_0", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_L_IMUX24_0", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_WW4B1_0", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_WW4END1_0", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_WW4END2_0", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_LH9_0", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_EE4A0_0", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_L_BYP3_0", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_L_IMUX13_0", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_L_BYP0_0", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_L_IMUX6_0", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_WW2A2_0", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_MONITOR_N_0", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CMT_FIFO_L_IMUX15_0", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_FAN7_0", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_L_BYP2_0", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_SE4BEG2_0", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_EL1BEG2_0", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_WW2END1_0", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_WR1END2_0", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_EL1BEG1_0", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_LH10_0", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_L_IMUX21_0", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_WW4C1_0", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_EE2A3_0", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_0", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "CMT_FIFO_SE2A3_0", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_LH8_0", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_IMUX30_0", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_L_FAN5_0", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_L_FAN4_0", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_L_IMUX28_0", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_EE4B1_0", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_0", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "CMT_FIFO_NE4BEG3_0", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX10_0", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_ER1BEG2_0", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_IMUX41_0", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_IMUX33_0", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_L_IMUX3_0", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_0", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "CMT_FIFO_NW2A0_0", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_ER1BEG1_0", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_EE2A1_0", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_SE4C1_0", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_L_IMUX19_0", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_WW4A1_0", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_L_IMUX17_0", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_EE4B3_0", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_EE4A3_0", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_NW4A2_0", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_L_IMUX47_0", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_EL1BEG3_0", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_L_IMUX37_0", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_L_FAN3_0", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_LH3_0", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_LH4_0", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_WW4A2_0", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_L_BYP4_0", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_SE4BEG0_0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_NE4BEG2_0", + "INT_INTERFACE_NE4BEG2" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + 6 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_6" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_6" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_6" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_6" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_6" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_6" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_6" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_6" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_6" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_6" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_6" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_6" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_6" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_6" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_6" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_6" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_6" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_6" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_6" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_6" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_6" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_6" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_6" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_6" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_6" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_6" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_6" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_6" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_6" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_6" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_6" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_6" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_6" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_6" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_6" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_6" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_6" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_6" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_6" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_6" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_6" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_6" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_6" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_6" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_6" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_6" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_6" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_6" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_6" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_6" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_6" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_6" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_6" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_6" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_6" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_6" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_6" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_6" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_6" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_6" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_6" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_6" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_6" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_6" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_6" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_6" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_6" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_6" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_6" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_6" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_6" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_6" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_6" + ], + [ + "INT_FEEDTHRU_2_MONITOR_P", + "MONITOR_HORIZ_VAUXP11" + ], + [ + "INT_FEEDTHRU_2_MONITOR_N", + "MONITOR_HORIZ_VAUXN11" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_6" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_6" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_6" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_6" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_6" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_6" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_6" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_6" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_6" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_6" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_6" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_6" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_6" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_6" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_6" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_6" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_6" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_6" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_6" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_6" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_6" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_6" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_6" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_6" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_6" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_6" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_6" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_6" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_6" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_6" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_6" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_6" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_6" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_6" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_6" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_6" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_6" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_6" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_6" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_6" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_6" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_6" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_6" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_6" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_6" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_6" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_6" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_6" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_6" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_6" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_6" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_BOT_FUJI2" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "CLK_HROW_IMUX32_6", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_NW2A2_6", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_BYP3_6", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_EE2A0_6", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_EE2BEG3_6", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_SE4C1_6", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_LH10_6", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_ER1BEG0_6", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_WW2A0_6", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4C1_6", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_SW4A0_6", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_EE4BEG3_6", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_IMUX0_6", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_CTRL0_6", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_NE4C0_6", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_MONITOR_N_6", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_HROW_WW4C2_6", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_NW4END0_6", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_LH3_6", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_SW2A2_6", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_IMUX24_6", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_FAN0_6", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_SW4END2_6", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_EE2A1_6", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_EE4C3_6", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_SW4A2_6", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_WW4B3_6", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_WW2END3_6", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_IMUX30_6", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_IMUX9_6", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_IMUX31_6", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_WW4B1_6", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_NE2A2_6", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_LH7_6", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_WW4END3_6", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_FAN7_6", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_IMUX20_6", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_IMUX38_6", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_WW4B0_6", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_SW4A3_6", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_WR1END1_6", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_EE4A1_6", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_FAN6_6", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_EE2BEG2_6", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_EE4B2_6", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_NE4BEG3_6", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_IMUX10_6", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_NW4A3_6", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_FAN2_6", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_WL1END0_6", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_FAN3_6", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_EL1BEG2_6", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_IMUX25_6", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_SW2A0_6", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_IMUX13_6", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_NW4END2_6", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_SW4A1_6", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_LH11_6", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_WL1END3_6", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_EE4A0_6", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_BYP6_6", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_IMUX15_6", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_WW2A2_6", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_WW2A3_6", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_WW2END2_6", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_SE4BEG3_6", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_IMUX19_6", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_LH12_6", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_SE4BEG0_6", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_IMUX21_6", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_NW2A0_6", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_LH4_6", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_IMUX14_6", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_IMUX23_6", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_NE4C2_6", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_EE4B1_6", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_FAN1_6", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_EE4C0_6", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_EE4A3_6", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_IMUX29_6", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_IMUX17_6", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_IMUX43_6", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_SE2A2_6", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_WL1END1_6", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_WW4C0_6", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_LH5_6", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_IMUX2_6", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_NE4BEG0_6", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_IMUX8_6", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_ER1BEG1_6", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_EE4C2_6", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_SW4END0_6", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_WW4END1_6", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_LH2_6", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_IMUX35_6", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_SE4BEG1_6", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_EE4BEG0_6", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_IMUX40_6", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_IMUX47_6", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_EL1BEG1_6", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_WR1END2_6", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_IMUX34_6", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_IMUX44_6", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_BYP5_6", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_WW4C3_6", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_NW4A2_6", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_IMUX3_6", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_NE4BEG1_6", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_IMUX12_6", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_WW4C1_6", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_NE4BEG2_6", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_NW4A1_6", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_NE4C1_6", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_ER1BEG2_6", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_WW4A3_6", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_IMUX1_6", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_IMUX41_6", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_NW2A1_6", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_IMUX37_6", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_LH6_6", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_NE4C3_6", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_IMUX28_6", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_SW4END3_6", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_IMUX5_6", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_IMUX16_6", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_EL1BEG0_6", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_SW4END1_6", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_BYP2_6", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_NW4END3_6", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_LH1_6", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_IMUX45_6", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_EE2A2_6", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_EE4B3_6", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_LH8_6", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_IMUX42_6", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_FAN4_6", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_WW4A0_6", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_WW2A1_6", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_WR1END0_6", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_WR1END3_6", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_SE2A3_6", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_SE2A0_6", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_BYP4_6", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_NW4A0_6", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_EE2BEG0_6", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_SE4C2_6", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_EE4B0_6", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_WL1END2_6", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_SE4BEG2_6", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_EE2A3_6", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_IMUX27_6", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_WW4A2_6", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_WW4END2_6", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_LH9_6", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_SE4C3_6", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_ER1BEG3_6", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_WW4B2_6", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_BYP0_6", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_IMUX26_6", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_EE4BEG2_6", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_NE2A0_6", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_CLK1_6", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_WW2END0_6", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_IMUX33_6", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_IMUX7_6", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_SW2A3_6", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_IMUX4_6", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_EE2BEG1_6", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_WW2END1_6", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_SE4C0_6", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_NE2A3_6", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_EE4A2_6", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_SW2A1_6", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_IMUX6_6", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_IMUX11_6", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_CLK0_6", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_CTRL1_6", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_IMUX36_6", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_MONITOR_P_6", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_HROW_NE2A1_6", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_EE4BEG1_6", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_NW4END1_6", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_IMUX46_6", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_SE2A1_6", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_WW4END0_6", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_NW2A3_6", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_IMUX39_6", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_IMUX22_6", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_BYP1_6", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_BYP7_6", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_IMUX18_6", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_EL1BEG3_6", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_WW4A1_6", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_FAN5_6", + "INT_INTERFACE_FAN5" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_BRAM_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_BRAM_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_BRAM_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_BRAM_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_BRAM_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_BRAM_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_BRAM_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_BRAM_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_BRAM_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_BRAM_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_BRAM_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_BRAM_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_BRAM_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_BRAM_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ] + ], + "tile_types": [ + "HCLK_BRAM", + "HCLK_VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "SE6E1", + "INT_INTERFACE_SE4C1" + ], + [ + "NE6BEG3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "WR1END1", + "INT_INTERFACE_WR1END1" + ], + [ + "EE4C3", + "INT_INTERFACE_EE4C3" + ], + [ + "IMUX40", + "PCIE_INT_INTERFACE_IMUX40" + ], + [ + "EE4BEG1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "IMUX6", + "PCIE_INT_INTERFACE_IMUX6" + ], + [ + "SE2A1", + "INT_INTERFACE_SE2A1" + ], + [ + "FAN2", + "INT_INTERFACE_FAN2" + ], + [ + "IMUX30", + "PCIE_INT_INTERFACE_IMUX30" + ], + [ + "LH6", + "INT_INTERFACE_LH6" + ], + [ + "LOGIC_OUTS4", + "INT_INTERFACE_LOGIC_OUTS4" + ], + [ + "NW6A2", + "INT_INTERFACE_NW4A2" + ], + [ + "SE2A2", + "INT_INTERFACE_SE2A2" + ], + [ + "EE2BEG0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "LOGIC_OUTS13", + "INT_INTERFACE_LOGIC_OUTS13" + ], + [ + "EL1BEG0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "ER1BEG0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "NW6A1", + "INT_INTERFACE_NW4A1" + ], + [ + "SE6E0", + "INT_INTERFACE_SE4C0" + ], + [ + "FAN0", + "INT_INTERFACE_FAN0" + ], + [ + "IMUX23", + "PCIE_INT_INTERFACE_IMUX23" + ], + [ + "SE2A0", + "INT_INTERFACE_SE2A0" + ], + [ + "WW2A3", + "INT_INTERFACE_WW2A3" + ], + [ + "WL1END1", + "INT_INTERFACE_WL1END1" + ], + [ + "SW2END2", + "INT_INTERFACE_SW2A2" + ], + [ + "NW6END2", + "INT_INTERFACE_NW4END2" + ], + [ + "EE2A1", + "INT_INTERFACE_EE2A1" + ], + [ + "LOGIC_OUTS12", + "INT_INTERFACE_LOGIC_OUTS12" + ], + [ + "SE6BEG3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "NE6E2", + "INT_INTERFACE_NE4C2" + ], + [ + "LOGIC_OUTS23", + "INT_INTERFACE_LOGIC_OUTS23" + ], + [ + "NE6E0", + "INT_INTERFACE_NE4C0" + ], + [ + "IMUX10", + "PCIE_INT_INTERFACE_IMUX10" + ], + [ + "IMUX16", + "PCIE_INT_INTERFACE_IMUX16" + ], + [ + "EE4A2", + "INT_INTERFACE_EE4A2" + ], + [ + "LOGIC_OUTS5", + "INT_INTERFACE_LOGIC_OUTS5" + ], + [ + "LH11", + "INT_INTERFACE_LH11" + ], + [ + "WW4C2", + "INT_INTERFACE_WW4C2" + ], + [ + "NW2END2", + "INT_INTERFACE_NW2A2" + ], + [ + "EE2BEG1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "WW4END1", + "INT_INTERFACE_WW4END1" + ], + [ + "LH9", + "INT_INTERFACE_LH9" + ], + [ + "WR1END0", + "INT_INTERFACE_WR1END0" + ], + [ + "WW2END3", + "INT_INTERFACE_WW2END3" + ], + [ + "IMUX7", + "PCIE_INT_INTERFACE_IMUX7" + ], + [ + "SE6E2", + "INT_INTERFACE_SE4C2" + ], + [ + "LOGIC_OUTS0", + "INT_INTERFACE_LOGIC_OUTS0" + ], + [ + "EE4A1", + "INT_INTERFACE_EE4A1" + ], + [ + "LOGIC_OUTS11", + "INT_INTERFACE_LOGIC_OUTS11" + ], + [ + "WW4A3", + "INT_INTERFACE_WW4A3" + ], + [ + "NE2A0", + "INT_INTERFACE_NE2A0" + ], + [ + "LOGIC_OUTS8", + "INT_INTERFACE_LOGIC_OUTS8" + ], + [ + "SE6BEG2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK0", + "INT_INTERFACE_CLK0" + ], + [ + "NE2A2", + "INT_INTERFACE_NE2A2" + ], + [ + "EL1BEG3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "EE4B2", + "INT_INTERFACE_EE4B2" + ], + [ + "WW4END2", + "INT_INTERFACE_WW4END2" + ], + [ + "LOGIC_OUTS1", + "INT_INTERFACE_LOGIC_OUTS1" + ], + [ + "NW2END1", + "INT_INTERFACE_NW2A1" + ], + [ + "WR1END2", + "INT_INTERFACE_WR1END2" + ], + [ + "WW4END3", + "INT_INTERFACE_WW4END3" + ], + [ + "IMUX26", + "PCIE_INT_INTERFACE_IMUX26" + ], + [ + "IMUX18", + "PCIE_INT_INTERFACE_IMUX18" + ], + [ + "EE4B1", + "INT_INTERFACE_EE4B1" + ], + [ + "WW4B3", + "INT_INTERFACE_WW4B3" + ], + [ + "WW2A1", + "INT_INTERFACE_WW2A1" + ], + [ + "WW4END0", + "INT_INTERFACE_WW4END0" + ], + [ + "IMUX5", + "PCIE_INT_INTERFACE_IMUX5" + ], + [ + "IMUX22", + "PCIE_INT_INTERFACE_IMUX22" + ], + [ + "EE4BEG2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "IMUX21", + "PCIE_INT_INTERFACE_IMUX21" + ], + [ + "SW6A0", + "INT_INTERFACE_SW4A0" + ], + [ + "IMUX14", + "PCIE_INT_INTERFACE_IMUX14" + ], + [ + "IMUX36", + "PCIE_INT_INTERFACE_IMUX36" + ], + [ + "ER1BEG3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "IMUX2", + "PCIE_INT_INTERFACE_IMUX2" + ], + [ + "NE6BEG2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "SW2END1", + "INT_INTERFACE_SW2A1" + ], + [ + "CTRL0", + "INT_INTERFACE_CTRL0" + ], + [ + "BYP5", + "INT_INTERFACE_BYP5" + ], + [ + "IMUX37", + "PCIE_INT_INTERFACE_IMUX37" + ], + [ + "LOGIC_OUTS18", + "INT_INTERFACE_LOGIC_OUTS18" + ], + [ + "FAN7", + "INT_INTERFACE_FAN7" + ], + [ + "WW2A2", + "INT_INTERFACE_WW2A2" + ], + [ + "WW2END2", + "INT_INTERFACE_WW2END2" + ], + [ + "IMUX19", + "PCIE_INT_INTERFACE_IMUX19" + ], + [ + "SW2END0", + "INT_INTERFACE_SW2A0" + ], + [ + "IMUX24", + "PCIE_INT_INTERFACE_IMUX24" + ], + [ + "SW6END2", + "INT_INTERFACE_SW4END2" + ], + [ + "IMUX17", + "PCIE_INT_INTERFACE_IMUX17" + ], + [ + "LOGIC_OUTS2", + "INT_INTERFACE_LOGIC_OUTS2" + ], + [ + "SW2END3", + "INT_INTERFACE_SW2A3" + ], + [ + "IMUX29", + "PCIE_INT_INTERFACE_IMUX29" + ], + [ + "LH12", + "INT_INTERFACE_LH12" + ], + [ + "LOGIC_OUTS22", + "INT_INTERFACE_LOGIC_OUTS22" + ], + [ + "LOGIC_OUTS6", + "INT_INTERFACE_LOGIC_OUTS6" + ], + [ + "BYP1", + "INT_INTERFACE_BYP1" + ], + [ + "NW6END3", + "INT_INTERFACE_NW4END3" + ], + [ + "NE6BEG1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "WW4A2", + "INT_INTERFACE_WW4A2" + ], + [ + "NE6E1", + "INT_INTERFACE_NE4C1" + ], + [ + "EE2BEG3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "WW2END1", + "INT_INTERFACE_WW2END1" + ], + [ + "EE4C0", + "INT_INTERFACE_EE4C0" + ], + [ + "LOGIC_OUTS10", + "INT_INTERFACE_LOGIC_OUTS10" + ], + [ + "EE4A0", + "INT_INTERFACE_EE4A0" + ], + [ + "LH2", + "INT_INTERFACE_LH2" + ], + [ + "LOGIC_OUTS15", + "INT_INTERFACE_LOGIC_OUTS15" + ], + [ + "IMUX8", + "PCIE_INT_INTERFACE_IMUX8" + ], + [ + "IMUX31", + "PCIE_INT_INTERFACE_IMUX31" + ], + [ + "BYP0", + "INT_INTERFACE_BYP0" + ], + [ + "BYP4", + "INT_INTERFACE_BYP4" + ], + [ + "WW4C1", + "INT_INTERFACE_WW4C1" + ], + [ + "LH10", + "INT_INTERFACE_LH10" + ], + [ + "LOGIC_OUTS20", + "INT_INTERFACE_LOGIC_OUTS20" + ], + [ + "MONITOR_P", + "INT_INTERFACE_MONITOR_P" + ], + [ + "IMUX33", + "PCIE_INT_INTERFACE_IMUX33" + ], + [ + "CLK1", + "INT_INTERFACE_CLK1" + ], + [ + "EE4C2", + "INT_INTERFACE_EE4C2" + ], + [ + "IMUX1", + "PCIE_INT_INTERFACE_IMUX1" + ], + [ + "EL1BEG2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "NE2A1", + "INT_INTERFACE_NE2A1" + ], + [ + "LH1", + "INT_INTERFACE_LH1" + ], + [ + "IMUX44", + "PCIE_INT_INTERFACE_IMUX44" + ], + [ + "WL1END2", + "INT_INTERFACE_WL1END2" + ], + [ + "EE4A3", + "INT_INTERFACE_EE4A3" + ], + [ + "BYP7", + "INT_INTERFACE_BYP7" + ], + [ + "WW4C0", + "INT_INTERFACE_WW4C0" + ], + [ + "NW2END0", + "INT_INTERFACE_NW2A0" + ], + [ + "LOGIC_OUTS14", + "INT_INTERFACE_LOGIC_OUTS14" + ], + [ + "EE4B3", + "INT_INTERFACE_EE4B3" + ], + [ + "SW6A3", + "INT_INTERFACE_SW4A3" + ], + [ + "WW4B1", + "INT_INTERFACE_WW4B1" + ], + [ + "WW2END0", + "INT_INTERFACE_WW2END0" + ], + [ + "MONITOR_N", + "INT_INTERFACE_MONITOR_N" + ], + [ + "SW6END0", + "INT_INTERFACE_SW4END0" + ], + [ + "SE6BEG1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "WR1END3", + "INT_INTERFACE_WR1END3" + ], + [ + "EE4C1", + "INT_INTERFACE_EE4C1" + ], + [ + "NE6BEG0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "BYP3", + "INT_INTERFACE_BYP3" + ], + [ + "LH7", + "INT_INTERFACE_LH7" + ], + [ + "LH3", + "INT_INTERFACE_LH3" + ], + [ + "EE4BEG0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "NW6A3", + "INT_INTERFACE_NW4A3" + ], + [ + "IMUX41", + "PCIE_INT_INTERFACE_IMUX41" + ], + [ + "NW6A0", + "INT_INTERFACE_NW4A0" + ], + [ + "LOGIC_OUTS16", + "INT_INTERFACE_LOGIC_OUTS16" + ], + [ + "IMUX3", + "PCIE_INT_INTERFACE_IMUX3" + ], + [ + "IMUX28", + "PCIE_INT_INTERFACE_IMUX28" + ], + [ + "EE4B0", + "INT_INTERFACE_EE4B0" + ], + [ + "IMUX43", + "PCIE_INT_INTERFACE_IMUX43" + ], + [ + "BYP6", + "INT_INTERFACE_BYP6" + ], + [ + "IMUX42", + "PCIE_INT_INTERFACE_IMUX42" + ], + [ + "ER1BEG2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "WL1END3", + "INT_INTERFACE_WL1END3" + ], + [ + "SW6END1", + "INT_INTERFACE_SW4END1" + ], + [ + "SE2A3", + "INT_INTERFACE_SE2A3" + ], + [ + "WW4A1", + "INT_INTERFACE_WW4A1" + ], + [ + "LH8", + "INT_INTERFACE_LH8" + ], + [ + "IMUX0", + "PCIE_INT_INTERFACE_IMUX0" + ], + [ + "IMUX38", + "PCIE_INT_INTERFACE_IMUX38" + ], + [ + "FAN5", + "INT_INTERFACE_FAN5" + ], + [ + "NW6END0", + "INT_INTERFACE_NW4END0" + ], + [ + "LH5", + "INT_INTERFACE_LH5" + ], + [ + "NE2A3", + "INT_INTERFACE_NE2A3" + ], + [ + "IMUX15", + "PCIE_INT_INTERFACE_IMUX15" + ], + [ + "NW6END1", + "INT_INTERFACE_NW4END1" + ], + [ + "IMUX46", + "PCIE_INT_INTERFACE_IMUX46" + ], + [ + "SW6END3", + "INT_INTERFACE_SW4END3" + ], + [ + "NE6E3", + "INT_INTERFACE_NE4C3" + ], + [ + "IMUX32", + "PCIE_INT_INTERFACE_IMUX32" + ], + [ + "IMUX47", + "PCIE_INT_INTERFACE_IMUX47" + ], + [ + "IMUX11", + "PCIE_INT_INTERFACE_IMUX11" + ], + [ + "IMUX35", + "PCIE_INT_INTERFACE_IMUX35" + ], + [ + "ER1BEG1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "FAN3", + "INT_INTERFACE_FAN3" + ], + [ + "SE6BEG0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "SW6A2", + "INT_INTERFACE_SW4A2" + ], + [ + "IMUX45", + "PCIE_INT_INTERFACE_IMUX45" + ], + [ + "NW2END3", + "INT_INTERFACE_NW2A3" + ], + [ + "FAN6", + "INT_INTERFACE_FAN6" + ], + [ + "SW6A1", + "INT_INTERFACE_SW4A1" + ], + [ + "LOGIC_OUTS17", + "INT_INTERFACE_LOGIC_OUTS17" + ], + [ + "IMUX12", + "PCIE_INT_INTERFACE_IMUX12" + ], + [ + "SE6E3", + "INT_INTERFACE_SE4C3" + ], + [ + "IMUX27", + "PCIE_INT_INTERFACE_IMUX27" + ], + [ + "EL1BEG1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "WW4B2", + "INT_INTERFACE_WW4B2" + ], + [ + "IMUX9", + "PCIE_INT_INTERFACE_IMUX9" + ], + [ + "WL1END0", + "INT_INTERFACE_WL1END0" + ], + [ + "IMUX25", + "PCIE_INT_INTERFACE_IMUX25" + ], + [ + "IMUX13", + "PCIE_INT_INTERFACE_IMUX13" + ], + [ + "BYP2", + "INT_INTERFACE_BYP2" + ], + [ + "IMUX39", + "PCIE_INT_INTERFACE_IMUX39" + ], + [ + "FAN4", + "INT_INTERFACE_FAN4" + ], + [ + "LOGIC_OUTS19", + "INT_INTERFACE_LOGIC_OUTS19" + ], + [ + "LOGIC_OUTS21", + "INT_INTERFACE_LOGIC_OUTS21" + ], + [ + "EE2A0", + "INT_INTERFACE_EE2A0" + ], + [ + "IMUX4", + "PCIE_INT_INTERFACE_IMUX4" + ], + [ + "IMUX20", + "PCIE_INT_INTERFACE_IMUX20" + ], + [ + "CTRL1", + "INT_INTERFACE_CTRL1" + ], + [ + "FAN1", + "INT_INTERFACE_FAN1" + ], + [ + "EE2A3", + "INT_INTERFACE_EE2A3" + ], + [ + "EE4BEG3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "LOGIC_OUTS3", + "INT_INTERFACE_LOGIC_OUTS3" + ], + [ + "WW4A0", + "INT_INTERFACE_WW4A0" + ], + [ + "EE2A2", + "INT_INTERFACE_EE2A2" + ], + [ + "WW4B0", + "INT_INTERFACE_WW4B0" + ], + [ + "LOGIC_OUTS7", + "INT_INTERFACE_LOGIC_OUTS7" + ], + [ + "LOGIC_OUTS9", + "INT_INTERFACE_LOGIC_OUTS9" + ], + [ + "LH4", + "INT_INTERFACE_LH4" + ], + [ + "WW4C3", + "INT_INTERFACE_WW4C3" + ], + [ + "IMUX34", + "PCIE_INT_INTERFACE_IMUX34" + ], + [ + "EE2BEG2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "WW2A0", + "INT_INTERFACE_WW2A0" + ] + ], + "tile_types": [ + "INT_R", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SE4C2_8", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WL1END1_8", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_SE4BEG1_8", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_IMUX40_8", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_BYP1_8", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SE2A0_8", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_EL1BEG1_8", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_IMUX21_8", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_IMUX23_8", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NW2A3_8", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_LH11_8", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_SW2A0_8", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_IMUX44_8", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_NW4A3_8", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_WW2END2_8", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_IMUX16_8", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WW4C0_8", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX18_8", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_BYP3_8", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_WR1END2_8", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_IMUX8_8", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW4END3_8", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_LH5_8", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX31_8", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_SW2A3_8", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_LH6_8", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_NE2A2_8", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WR1END3_8", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_SE4C1_8", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_LH3_8", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_SW4A0_8", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_IMUX37_8", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SE4BEG2_8", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_FAN6_8", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_NW2A0_8", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_EE4C3_8", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE2BEG2_8", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_EE4A3_8", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX45_8", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX24_8", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_NE4C3_8", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_IMUX38_8", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_NE4C2_8", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_NW4A0_8", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX12_8", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_WW2A0_8", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_WW2END0_8", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_ER1BEG1_8", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_IMUX15_8", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_EE4B0_8", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_EE4BEG0_8", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_BYP0_8", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_WW2A2_8", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_EE2A3_8", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_IMUX13_8", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_IMUX42_8", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX25_8", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_WW4A0_8", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX33_8", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_BYP7_8", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_NW4END0_8", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_EE4B1_8", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_SE2A1_8", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_IMUX9_8", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX27_8", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX6_8", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_WR1END1_8", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_FAN0_8", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX3_8", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_NW2A1_8", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_CTRL0_8", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX32_8", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_IMUX26_8", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_CLK0_8", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX36_8", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_BYP4_8", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_NW4END1_8", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_EE2BEG1_8", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX14_8", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_IMUX20_8", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_FAN3_8", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_SW4END3_8", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_WW4C2_8", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WW4A3_8", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WL1END3_8", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_IMUX39_8", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_EE4C0_8", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_FAN2_8", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_NE2A1_8", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX0_8", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW4END1_8", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_NW4END2_8", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_WW4A2_8", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_NE4C1_8", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_EE2BEG0_8", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX22_8", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_BYP6_8", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_WW4C1_8", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_ER1BEG3_8", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_WL1END2_8", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WW4B0_8", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_EE4B3_8", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_LH8_8", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_IMUX28_8", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_FAN5_8", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_NW4A2_8", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_EL1BEG3_8", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_SW2A2_8", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_EE4C2_8", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX2_8", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_WL1END0_8", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_CTRL1_8", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_LH7_8", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_SW4END2_8", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_NE4BEG0_8", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_EE2A1_8", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_NE4BEG1_8", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_EE4A2_8", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX17_8", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_ER1BEG2_8", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX30_8", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_NW4A1_8", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SE4BEG0_8", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_IMUX1_8", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX10_8", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SE4C0_8", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_SE4BEG3_8", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_EE4B2_8", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX29_8", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX34_8", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_ER1BEG0_8", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_SW4END1_8", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_LH1_8", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NW4END3_8", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_EL1BEG2_8", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX7_8", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_EE2A2_8", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_SW4A3_8", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EE4BEG3_8", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX46_8", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_EE4A1_8", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX43_8", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX4_8", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_EE4A0_8", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_LH12_8", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX41_8", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_SW2A1_8", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_NE4BEG3_8", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_SE4C3_8", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX11_8", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_EE2A0_8", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_EE4BEG1_8", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_BYP2_8", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_IMUX5_8", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WW4C3_8", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NE2A0_8", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_EE2BEG3_8", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_CLK1_8", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_WR1END0_8", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_WW4B2_8", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_LH10_8", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW2END1_8", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_EL1BEG0_8", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_WW4END0_8", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_SE2A2_8", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_FAN4_8", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW4END2_8", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_SW4END0_8", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX35_8", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_LH2_8", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_SW4A2_8", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NW2A2_8", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_BYP5_8", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_WW4A1_8", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_NE4C0_8", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_FAN1_8", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_WW2A1_8", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_NE4BEG2_8", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW4B3_8", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_WW4B1_8", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_EE4BEG2_8", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_LH4_8", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_WW2END3_8", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_FAN7_8", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_WW2A3_8", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_NE2A3_8", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX19_8", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_EE4C1_8", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX47_8", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_LH9_8", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_SE2A3_8", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SW4A1_8", + "VFRAME_SW4A1" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "IOI_CLK1_1", + "TERM_INT_CLK1" + ], + [ + "IOI_IMUX29_1", + "TERM_INT_IMUX29" + ], + [ + "IOI_BYP0_1", + "TERM_INT_BYP0" + ], + [ + "IOI_IMUX44_1", + "TERM_INT_IMUX44" + ], + [ + "IOI_IMUX28_1", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX5_1", + "TERM_INT_IMUX5" + ], + [ + "IOI_LOGIC_OUTS0_1", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_IMUX30_1", + "TERM_INT_IMUX30" + ], + [ + "IOI_CTRL1_1", + "TERM_INT_CTRL1" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_PHASER_TO_IO_ICLK_0", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_IMUX43_1", + "TERM_INT_IMUX43" + ], + [ + "IOI_IMUX23_1", + "TERM_INT_IMUX23" + ], + [ + "IOI_IMUX18_1", + "TERM_INT_IMUX18" + ], + [ + "IOI_IMUX37_1", + "TERM_INT_IMUX37" + ], + [ + "IOI_IMUX33_1", + "TERM_INT_IMUX33" + ], + [ + "IOI_LOGIC_OUTS7_1", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_LOGIC_OUTS18_1", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_BYP4_1", + "TERM_INT_BYP4" + ], + [ + "IOI_IMUX47_1", + "TERM_INT_IMUX47" + ], + [ + "IOI_LOGIC_OUTS1_1", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX34_1", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX39_1", + "TERM_INT_IMUX39" + ], + [ + "IOI_BYP1_1", + "TERM_INT_BYP1" + ], + [ + "IOI_FAN6_1", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX38_1", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX3_1", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX21_1", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX22_1", + "TERM_INT_IMUX22" + ], + [ + "IOI_PHASER_TO_IO_OCLK_0", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_IMUX26_1", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX11_1", + "TERM_INT_IMUX11" + ], + [ + "IOI_CLK0_1", + "TERM_INT_CLK0" + ], + [ + "IOI_LOGIC_OUTS20_1", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_BYP2_1", + "TERM_INT_BYP2" + ], + [ + "IOI_IMUX8_1", + "TERM_INT_IMUX8" + ], + [ + "IOI_IMUX19_1", + "TERM_INT_IMUX19" + ], + [ + "IOI_LOGIC_OUTS2_1", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_FAN2_1", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX14_1", + "TERM_INT_IMUX14" + ], + [ + "IOI_IMUX7_1", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX40_1", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX25_1", + "TERM_INT_IMUX25" + ], + [ + "IOI_IMUX15_1", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX24_1", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX6_1", + "TERM_INT_IMUX6" + ], + [ + "IOI_IMUX4_1", + "TERM_INT_IMUX4" + ], + [ + "IOI_LOGIC_OUTS15_1", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX41_1", + "TERM_INT_IMUX41" + ], + [ + "IOI_BYP6_1", + "TERM_INT_BYP6" + ], + [ + "IOI_FAN4_1", + "TERM_INT_FAN4" + ], + [ + "IOI_FAN1_1", + "TERM_INT_FAN1" + ], + [ + "IOI_IMUX32_1", + "TERM_INT_IMUX32" + ], + [ + "IOI_IMUX45_1", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX20_1", + "TERM_INT_IMUX20" + ], + [ + "IOI_IMUX46_1", + "TERM_INT_IMUX46" + ], + [ + "IOI_IMUX31_1", + "TERM_INT_IMUX31" + ], + [ + "IOI_FAN0_1", + "TERM_INT_FAN0" + ], + [ + "IOI_IMUX35_1", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP7_1", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_1", + "TERM_INT_IMUX2" + ], + [ + "IOI_IMUX9_1", + "TERM_INT_IMUX9" + ], + [ + "IOI_BYP5_1", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS19_1", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_FAN3_1", + "TERM_INT_FAN3" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_IMUX36_1", + "TERM_INT_IMUX36" + ], + [ + "IOI_BLOCK_OUTS2_1", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "IOI_FAN7_1", + "TERM_INT_FAN7" + ], + [ + "IOI_LOGIC_OUTS5_1", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_LOGIC_OUTS11_1", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_IMUX27_1", + "TERM_INT_IMUX27" + ], + [ + "IOI_LOGIC_OUTS8_1", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_IMUX12_1", + "TERM_INT_IMUX12" + ], + [ + "IOI_LOGIC_OUTS3_1", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_IMUX16_1", + "TERM_INT_IMUX16" + ], + [ + "IOI_LOGIC_OUTS14_1", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_LOGIC_OUTS9_1", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_FAN5_1", + "TERM_INT_FAN5" + ], + [ + "IOI_IMUX1_1", + "TERM_INT_IMUX1" + ], + [ + "IOI_IMUX13_1", + "TERM_INT_IMUX13" + ], + [ + "IOI_IMUX10_1", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX42_1", + "TERM_INT_IMUX42" + ], + [ + "IOI_BLOCK_OUTS0_1", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_CTRL0_1", + "TERM_INT_CTRL0" + ], + [ + "IOI_LOGIC_OUTS23_1", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_IMUX17_1", + "TERM_INT_IMUX17" + ], + [ + "IOI_BYP3_1", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX0_1", + "TERM_INT_IMUX0" + ], + [ + "IOI_LOGIC_OUTS10_1", + "TERM_INT_LOGIC_OUTS_L_B10" + ] + ], + "tile_types": [ + "LIOI3_TBYTETERM", + "L_TERM_INT" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "BRAM_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "BRAM_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "BRAM_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "BRAM_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "BRAM_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "BRAM_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "BRAM_LH3_0", + "VBRK_LH3" + ], + [ + "BRAM_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "BRAM_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "BRAM_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "BRAM_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "BRAM_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "BRAM_LH9_0", + "VBRK_LH9" + ], + [ + "BRAM_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "BRAM_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "BRAM_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "BRAM_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "BRAM_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "BRAM_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "BRAM_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "BRAM_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "BRAM_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "BRAM_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "BRAM_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "BRAM_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "BRAM_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "BRAM_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "BRAM_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "BRAM_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "BRAM_LH1_0", + "VBRK_LH1" + ], + [ + "BRAM_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "BRAM_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "BRAM_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "BRAM_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "BRAM_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "BRAM_LH10_0", + "VBRK_LH10" + ], + [ + "BRAM_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "BRAM_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "BRAM_LH11_0", + "VBRK_LH11" + ], + [ + "BRAM_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "BRAM_LH12_0", + "VBRK_LH12" + ], + [ + "BRAM_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "BRAM_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "BRAM_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "BRAM_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "BRAM_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "BRAM_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "BRAM_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "BRAM_LH4_0", + "VBRK_LH4" + ], + [ + "BRAM_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "BRAM_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "BRAM_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "BRAM_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "BRAM_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "BRAM_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "BRAM_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "BRAM_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "BRAM_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "BRAM_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "BRAM_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "BRAM_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "BRAM_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "BRAM_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "BRAM_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "BRAM_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "BRAM_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "BRAM_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "BRAM_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "BRAM_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "BRAM_SW4A1_0", + "VBRK_SW4A1" + ], + [ + "BRAM_MONITOR_P_0", + "VBRK_MONITOR_P" + ], + [ + "BRAM_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "BRAM_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "BRAM_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "BRAM_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "BRAM_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "BRAM_LH8_0", + "VBRK_LH8" + ], + [ + "BRAM_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "BRAM_MONITOR_N_0", + "VBRK_MONITOR_N" + ], + [ + "BRAM_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "BRAM_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "BRAM_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "BRAM_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "BRAM_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "BRAM_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "BRAM_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "BRAM_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "BRAM_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "BRAM_LH6_0", + "VBRK_LH6" + ], + [ + "BRAM_LH2_0", + "VBRK_LH2" + ], + [ + "BRAM_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "BRAM_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "BRAM_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "BRAM_LH7_0", + "VBRK_LH7" + ], + [ + "BRAM_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "BRAM_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "BRAM_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "BRAM_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "BRAM_LH5_0", + "VBRK_LH5" + ], + [ + "BRAM_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "BRAM_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "BRAM_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "BRAM_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "BRAM_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "BRAM_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "BRAM_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "BRAM_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "BRAM_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "BRAM_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "BRAM_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "BRAM_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "BRAM_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "BRAM_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "BRAM_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "BRAM_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "BRAM_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "BRAM_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "BRAM_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "BRAM_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "BRAM_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "BRAM_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "BRAM_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "BRAM_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "BRAM_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "BRAM_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "BRAM_EE4BEG0_0", + "VBRK_EE4BEG0" + ] + ], + "tile_types": [ + "BRAM_L", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_FEEDTHRU_1_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ] + ], + "tile_types": [ + "HCLK_FEEDTHRU_1", + "HCLK_VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "CMT_TOP_EL1BEG1_8", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG1_8", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NW4A0_8", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4B0_8", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_8", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW2A0_8", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW2A0_8", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4BEG2_8", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_MONITOR_P_8", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_NE4C0_8", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_ER1BEG2_8", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_8", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_LH12_8", + "VBRK_LH12" + ], + [ + "CMT_TOP_EL1BEG2_8", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_LH1_8", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH10_8", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW4B1_8", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG2_8", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW4A3_8", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4C3_8", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_MONITOR_N_8", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW2A0_8", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NW4END0_8", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE2A2_8", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4C1_8", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW4C2_8", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW4A1_8", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NW2A1_8", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SE4BEG0_8", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_8", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_LH3_8", + "VBRK_LH3" + ], + [ + "CMT_TOP_WR1END2_8", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A0_8", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4A2_8", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END1_8", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A0_8", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A1_8", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EL1BEG0_8", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_EE4A3_8", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C3_8", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_LH4_8", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE4A0_8", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END1_8", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2A0_8", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH2_8", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4C1_8", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NE2A2_8", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2A3_8", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_NW4A3_8", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4END2_8", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE2A1_8", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END2_8", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2END0_8", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2BEG0_8", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4C0_8", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG0_8", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_WR1END0_8", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_SE4C2_8", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4END1_8", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NE2A1_8", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4B3_8", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_8", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C2_8", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4B1_8", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW2A3_8", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SE4C1_8", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WR1END3_8", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW2A2_8", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C0_8", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4C1_8", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH11_8", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4B2_8", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW2A3_8", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NW4END2_8", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A0_8", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WR1END1_8", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH5_8", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END3_8", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH6_8", + "VBRK_LH6" + ], + [ + "CMT_TOP_NE4BEG3_8", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_LH8_8", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A1_8", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE2BEG2_8", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4C3_8", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NW2A2_8", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END3_8", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE2A3_8", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_ER1BEG1_8", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_8", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_NE4BEG1_8", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_WW4A2_8", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG0_8", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NE4C2_8", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SE4BEG3_8", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C0_8", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_8", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2BEG3_8", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH9_8", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE4B2_8", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_WL1END0_8", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_WW2END3_8", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EL1BEG3_8", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG3_8", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4BEG3_8", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WL1END1_8", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2A1_8", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SE4BEG2_8", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW2A3_8", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SE4C3_8", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE2A2_8", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_8", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4A1_8", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW4A2_8", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SW2A2_8", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_NW4END3_8", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SW4END1_8", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END3_8", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4BEG1_8", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4END2_8", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH7_8", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4BEG0_8", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2BEG1_8", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_8", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A3_8", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WL1END2_8", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A0_8", + "VBRK_WW4A0" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "DSP_0_PCIN21", + "HCLK_DSP_PCIN21" + ], + [ + "DSP_0_BCIN15", + "HCLK_DSP_BCIN15" + ], + [ + "DSP_0_BCIN14", + "HCLK_DSP_BCIN14" + ], + [ + "DSP_0_ACIN23", + "HCLK_DSP_ACIN23" + ], + [ + "DSP_0_BCIN12", + "HCLK_DSP_BCIN12" + ], + [ + "DSP_0_ACIN5", + "HCLK_DSP_ACIN5" + ], + [ + "DSP_0_PCIN28", + "HCLK_DSP_PCIN28" + ], + [ + "DSP_0_BCIN2", + "HCLK_DSP_BCIN2" + ], + [ + "DSP_0_ACIN1", + "HCLK_DSP_ACIN1" + ], + [ + "DSP_0_PCIN47", + "HCLK_DSP_PCIN47" + ], + [ + "DSP_0_PCIN39", + "HCLK_DSP_PCIN39" + ], + [ + "DSP_0_ACIN14", + "HCLK_DSP_ACIN14" + ], + [ + "DSP_0_ACIN12", + "HCLK_DSP_ACIN12" + ], + [ + "DSP_0_ACIN10", + "HCLK_DSP_ACIN10" + ], + [ + "DSP_0_BCIN8", + "HCLK_DSP_BCIN8" + ], + [ + "DSP_0_PCIN6", + "HCLK_DSP_PCIN6" + ], + [ + "DSP_0_BCIN11", + "HCLK_DSP_BCIN11" + ], + [ + "DSP_0_PCIN46", + "HCLK_DSP_PCIN46" + ], + [ + "DSP_0_ACIN13", + "HCLK_DSP_ACIN13" + ], + [ + "DSP_0_PCIN24", + "HCLK_DSP_PCIN24" + ], + [ + "DSP_0_ACIN21", + "HCLK_DSP_ACIN21" + ], + [ + "DSP_0_PCIN9", + "HCLK_DSP_PCIN9" + ], + [ + "DSP_0_PCIN22", + "HCLK_DSP_PCIN22" + ], + [ + "DSP_0_PCIN16", + "HCLK_DSP_PCIN16" + ], + [ + "DSP_0_ACIN3", + "HCLK_DSP_ACIN3" + ], + [ + "DSP_0_ACIN2", + "HCLK_DSP_ACIN2" + ], + [ + "DSP_0_ACIN22", + "HCLK_DSP_ACIN22" + ], + [ + "DSP_0_PCIN40", + "HCLK_DSP_PCIN40" + ], + [ + "DSP_0_PCIN45", + "HCLK_DSP_PCIN45" + ], + [ + "DSP_0_PCIN19", + "HCLK_DSP_PCIN19" + ], + [ + "DSP_0_PCIN38", + "HCLK_DSP_PCIN38" + ], + [ + "DSP_0_ACIN24", + "HCLK_DSP_ACIN24" + ], + [ + "DSP_0_ACIN20", + "HCLK_DSP_ACIN20" + ], + [ + "DSP_0_ACIN7", + "HCLK_DSP_ACIN7" + ], + [ + "DSP_0_BCIN13", + "HCLK_DSP_BCIN13" + ], + [ + "DSP_0_PCIN11", + "HCLK_DSP_PCIN11" + ], + [ + "DSP_0_PCIN0", + "HCLK_DSP_PCIN0" + ], + [ + "DSP_0_ACIN11", + "HCLK_DSP_ACIN11" + ], + [ + "DSP_0_PCIN3", + "HCLK_DSP_PCIN3" + ], + [ + "DSP_0_ACIN9", + "HCLK_DSP_ACIN9" + ], + [ + "DSP_0_ACIN17", + "HCLK_DSP_ACIN17" + ], + [ + "DSP_0_PCIN17", + "HCLK_DSP_PCIN17" + ], + [ + "DSP_0_BCIN16", + "HCLK_DSP_BCIN16" + ], + [ + "DSP_0_BCIN0", + "HCLK_DSP_BCIN0" + ], + [ + "DSP_0_ACIN6", + "HCLK_DSP_ACIN6" + ], + [ + "DSP_0_PCIN33", + "HCLK_DSP_PCIN33" + ], + [ + "DSP_0_ACIN15", + "HCLK_DSP_ACIN15" + ], + [ + "DSP_0_BCIN10", + "HCLK_DSP_BCIN10" + ], + [ + "DSP_0_PCIN2", + "HCLK_DSP_PCIN2" + ], + [ + "DSP_0_PCIN4", + "HCLK_DSP_PCIN4" + ], + [ + "DSP_0_ACIN27", + "HCLK_DSP_ACIN27" + ], + [ + "DSP_0_ACIN16", + "HCLK_DSP_ACIN16" + ], + [ + "DSP_0_PCIN20", + "HCLK_DSP_PCIN20" + ], + [ + "DSP_0_ACIN19", + "HCLK_DSP_ACIN19" + ], + [ + "DSP_0_MULTSIGNIN", + "HCLK_DSP_MULTSIGNIN" + ], + [ + "DSP_0_PCIN25", + "HCLK_DSP_PCIN25" + ], + [ + "DSP_0_BCIN9", + "HCLK_DSP_BCIN9" + ], + [ + "DSP_0_PCIN41", + "HCLK_DSP_PCIN41" + ], + [ + "DSP_0_PCIN12", + "HCLK_DSP_PCIN12" + ], + [ + "DSP_0_BCIN1", + "HCLK_DSP_BCIN1" + ], + [ + "DSP_0_PCIN34", + "HCLK_DSP_PCIN34" + ], + [ + "DSP_0_BCIN17", + "HCLK_DSP_BCIN17" + ], + [ + "DSP_0_ACIN26", + "HCLK_DSP_ACIN26" + ], + [ + "DSP_0_PCIN35", + "HCLK_DSP_PCIN35" + ], + [ + "DSP_0_ACIN28", + "HCLK_DSP_ACIN28" + ], + [ + "DSP_0_PCIN44", + "HCLK_DSP_PCIN44" + ], + [ + "DSP_0_PCIN18", + "HCLK_DSP_PCIN18" + ], + [ + "DSP_0_ACIN29", + "HCLK_DSP_ACIN29" + ], + [ + "DSP_0_PCIN31", + "HCLK_DSP_PCIN31" + ], + [ + "DSP_0_PCIN15", + "HCLK_DSP_PCIN15" + ], + [ + "DSP_0_ACIN8", + "HCLK_DSP_ACIN8" + ], + [ + "DSP_0_PCIN32", + "HCLK_DSP_PCIN32" + ], + [ + "DSP_0_PCIN27", + "HCLK_DSP_PCIN27" + ], + [ + "DSP_0_PCIN1", + "HCLK_DSP_PCIN1" + ], + [ + "DSP_0_ACIN25", + "HCLK_DSP_ACIN25" + ], + [ + "DSP_0_BCIN4", + "HCLK_DSP_BCIN4" + ], + [ + "DSP_0_PCIN8", + "HCLK_DSP_PCIN8" + ], + [ + "DSP_0_BCIN5", + "HCLK_DSP_BCIN5" + ], + [ + "DSP_0_PCIN30", + "HCLK_DSP_PCIN30" + ], + [ + "DSP_0_BCIN3", + "HCLK_DSP_BCIN3" + ], + [ + "DSP_0_PCIN37", + "HCLK_DSP_PCIN37" + ], + [ + "DSP_0_PCIN29", + "HCLK_DSP_PCIN29" + ], + [ + "DSP_0_PCIN43", + "HCLK_DSP_PCIN43" + ], + [ + "DSP_0_PCIN14", + "HCLK_DSP_PCIN14" + ], + [ + "DSP_0_BCIN7", + "HCLK_DSP_BCIN7" + ], + [ + "DSP_0_PCIN13", + "HCLK_DSP_PCIN13" + ], + [ + "DSP_0_PCIN23", + "HCLK_DSP_PCIN23" + ], + [ + "DSP_0_PCIN36", + "HCLK_DSP_PCIN36" + ], + [ + "DSP_0_PCIN5", + "HCLK_DSP_PCIN5" + ], + [ + "DSP_0_PCIN42", + "HCLK_DSP_PCIN42" + ], + [ + "DSP_0_PCIN7", + "HCLK_DSP_PCIN7" + ], + [ + "DSP_0_ACIN0", + "HCLK_DSP_ACIN0" + ], + [ + "DSP_0_PCIN26", + "HCLK_DSP_PCIN26" + ], + [ + "DSP_0_PCIN10", + "HCLK_DSP_PCIN10" + ], + [ + "DSP_0_BCIN6", + "HCLK_DSP_BCIN6" + ], + [ + "DSP_0_ACIN4", + "HCLK_DSP_ACIN4" + ], + [ + "DSP_0_ACIN18", + "HCLK_DSP_ACIN18" + ], + [ + "DSP_0_CARRYCASCIN", + "HCLK_DSP_CARRYCASCIN" + ] + ], + "tile_types": [ + "DSP_R", + "HCLK_DSP_R" + ] + }, + { + "grid_deltas": [ + -1, + -7 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW4C0_7", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_WL1END1_7", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_WW4A0_7", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_NW4A3_7", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_NW4END2_7", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_SW4END0_7", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EE4C0_7", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EL1BEG1_7", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NE4BEG0_7", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_SW4A2_7", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NW4A2_7", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_SW2A3_7", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_WW4C3_7", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_NE4C0_7", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_LH6_7", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_EE4B3_7", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SE4C0_7", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_NW2A0_7", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_EE4C2_7", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW2A2_7", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_EE4B1_7", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EE2A2_7", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_NE4BEG3_7", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_LH9_7", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_LH8_7", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_LH2_7", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_EL1BEG0_7", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_WW2A3_7", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_SW2A2_7", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WW2END2_7", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_NW4A1_7", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_EE2BEG0_7", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_SE4BEG2_7", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_NW4END1_7", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_WW4END3_7", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_SW4END1_7", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_WW4END1_7", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EL1BEG3_7", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WL1END2_7", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SE2A1_7", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW4END0_7", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WW4B1_7", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_EE4BEG0_7", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE4C1_7", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_ER1BEG0_7", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_WL1END0_7", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SW2A0_7", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_EE4B0_7", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WW4A1_7", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EE4C3_7", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW4C1_7", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SE4BEG1_7", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_NW2A1_7", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SE2A3_7", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_EE2A3_7", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_EE4A1_7", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NE2A2_7", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_WR1END1_7", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SW4A3_7", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE4A3_7", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_SW4A0_7", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WR1END3_7", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_LH1_7", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_NE2A3_7", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_LH4_7", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_WW2A2_7", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_SE2A2_7", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_WW4C2_7", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_LH5_7", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_NE4BEG1_7", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_ER1BEG3_7", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW4B0_7", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_SW4END3_7", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NE2A0_7", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EE2A1_7", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_NE4C1_7", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_SE4C1_7", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_NE4BEG2_7", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG2_7", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_WW2END0_7", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_LH10_7", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WL1END3_7", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_LH11_7", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_LH3_7", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SE2A0_7", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE4A2_7", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4A0_7", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE2BEG1_7", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_EE2A0_7", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_NW4A0_7", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_WW4A3_7", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NW2A3_7", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NW4END0_7", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SE4BEG0_7", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_ER1BEG2_7", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_SE4C2_7", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_ER1BEG1_7", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WR1END0_7", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_EE4BEG1_7", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_EE2BEG3_7", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_EE4BEG3_7", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WW4END2_7", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_SW4A1_7", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_SE4BEG3_7", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EE4B2_7", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_LH7_7", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4A2_7", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WW4B2_7", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_NE4C2_7", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW2A0_7", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_NE4C3_7", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WW2END3_7", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_WW4B3_7", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SW4END2_7", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SE4C3_7", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_NW4END3_7", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_EE4BEG2_7", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_LH12_7", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW2END1_7", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE2BEG2_7", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW2A1_7", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_NE2A1_7", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_SW2A1_7", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_WR1END2_7", + "INT_FEEDTHRU_2_WR1END2" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_CLB_CK_BUFRCLK2" + ], + [ + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_CLB_CK_BUFRCLK0" + ], + [ + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_CLB_CK_BUFHCLK8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_CLB_CK_BUFHCLK6" + ], + [ + "HCLK_BRAM_CK_IN5", + "HCLK_CLB_CK_IN5" + ], + [ + "HCLK_BRAM_CK_IN3", + "HCLK_CLB_CK_IN3" + ], + [ + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_CLB_CK_BUFRCLK3" + ], + [ + "HCLK_BRAM_CK_IN0", + "HCLK_CLB_CK_IN0" + ], + [ + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_CLB_CK_BUFHCLK10" + ], + [ + "HCLK_BRAM_CK_IN1", + "HCLK_CLB_CK_IN1" + ], + [ + "HCLK_BRAM_CK_IN13", + "HCLK_CLB_CK_IN13" + ], + [ + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_CLB_CK_BUFHCLK4" + ], + [ + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_CLB_CK_BUFHCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_CLB_CK_BUFHCLK7" + ], + [ + "HCLK_BRAM_CK_IN11", + "HCLK_CLB_CK_IN11" + ], + [ + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_CLB_CK_BUFHCLK0" + ], + [ + "HCLK_BRAM_CK_IN4", + "HCLK_CLB_CK_IN4" + ], + [ + "HCLK_BRAM_CK_IN10", + "HCLK_CLB_CK_IN10" + ], + [ + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_CLB_CK_BUFHCLK9" + ], + [ + "HCLK_BRAM_CK_IN2", + "HCLK_CLB_CK_IN2" + ], + [ + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_CLB_CK_BUFRCLK1" + ], + [ + "HCLK_BRAM_CK_IN6", + "HCLK_CLB_CK_IN6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_CLB_CK_BUFHCLK5" + ], + [ + "HCLK_BRAM_CK_IN12", + "HCLK_CLB_CK_IN12" + ], + [ + "HCLK_BRAM_CK_IN9", + "HCLK_CLB_CK_IN9" + ], + [ + "HCLK_BRAM_CK_IN8", + "HCLK_CLB_CK_IN8" + ], + [ + "HCLK_BRAM_CK_IN7", + "HCLK_CLB_CK_IN7" + ], + [ + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_CLB_CK_BUFHCLK2" + ], + [ + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_CLB_CK_BUFHCLK1" + ], + [ + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_CLB_CK_BUFHCLK11" + ] + ], + "tile_types": [ + "HCLK_BRAM", + "HCLK_CLB" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "CFG_CENTER_LH3_12", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_FAN6_12", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_SE2A2_12", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_BYP0_12", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX2_12", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_NE2A3_12", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX23_12", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW2A0_12", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_EE4B2_12", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_SW4A1_12", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_LH4_12", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_SW4END2_12", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_IMUX1_12", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_ER1BEG1_12", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_WL1END2_12", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_EL1BEG0_12", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_WW4B1_12", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_IMUX18_12", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_12", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_IMUX41_12", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_12", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_IMUX0_12", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_EE4BEG0_12", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_EE4C0_12", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_SW4A2_12", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_ER1BEG2_12", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX39_12", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_IMUX3_12", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_EE4A3_12", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX4_12", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_EE4B1_12", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_IMUX47_12", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_SW4A3_12", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_IMUX25_12", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_FAN2_12", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_LH11_12", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_12", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_FAN5_12", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_WW4C3_12", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_SE2A0_12", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_SW2A2_12", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_SE2A1_12", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_12", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_NW4END3_12", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_NE4BEG2_12", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW4A3_12", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW2A1_12", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_WW4A2_12", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_IMUX36_12", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_NW4A1_12", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_WW2END3_12", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_IMUX10_12", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_NW2A1_12", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_12", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_IMUX9_12", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_SE2A3_12", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_WL1END3_12", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_LH9_12", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EE2BEG3_12", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_EE2A2_12", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_NE4BEG3_12", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_BYP5_12", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_IMUX32_12", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_FAN4_12", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_IMUX7_12", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_EL1BEG3_12", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_SE4BEG1_12", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_IMUX13_12", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_WW4END2_12", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX40_12", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_EE4C2_12", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX12_12", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_WR1END2_12", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_NE4C1_12", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_NW2A3_12", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_EE4C3_12", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_IMUX11_12", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_NW4A3_12", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_LH5_12", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX34_12", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_IMUX16_12", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_SW2A1_12", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_IMUX30_12", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_SE4C1_12", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_BYP3_12", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_EE2BEG0_12", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_WL1END1_12", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_WW2A3_12", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX15_12", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_BYP7_12", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_CTRL1_12", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_SE4C2_12", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_NW4A2_12", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_WW4A0_12", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_EE2A1_12", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_EE2BEG2_12", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_ER1BEG3_12", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_NE4C0_12", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_BYP1_12", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW4B2_12", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_NW2A2_12", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW2END0_12", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WW4A1_12", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_SE4C3_12", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_WW4END0_12", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_NE4C3_12", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_EE4C1_12", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_EE2BEG1_12", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_NE2A0_12", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX29_12", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_EL1BEG2_12", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_BYP2_12", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_SW2A3_12", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_EE2A3_12", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_IMUX28_12", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_EE4BEG3_12", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_EE4A1_12", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_NE4BEG1_12", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_EE4A2_12", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX17_12", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX14_12", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_EE4B0_12", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WR1END1_12", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NE2A2_12", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_NW4END1_12", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_IMUX38_12", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX27_12", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX5_12", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX6_12", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_SE4BEG3_12", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_EE4A0_12", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_LH7_12", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_EE4B3_12", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_SE4BEG0_12", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_FAN3_12", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_LH1_12", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_SW4END1_12", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_IMUX35_12", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_SW4A0_12", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_WW4B3_12", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_IMUX26_12", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_FAN1_12", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_12", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_LH10_12", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW4C0_12", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_WW4END3_12", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_12", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_SE4C0_12", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_WW2A2_12", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_IMUX21_12", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_WW4C2_12", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WR1END0_12", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_NW4A0_12", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_BYP6_12", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX42_12", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_EE2A0_12", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_IMUX45_12", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX31_12", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_IMUX46_12", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_CTRL0_12", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX20_12", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SW2A0_12", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_LH12_12", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_NE2A1_12", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_12", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_FAN7_12", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_12", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_LH2_12", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX33_12", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_FAN0_12", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_NW4END2_12", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_NW2A0_12", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_EE4BEG1_12", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_SW4END3_12", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX43_12", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_EL1BEG1_12", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_CLK1_12", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_WR1END3_12", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_WW4C1_12", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_IMUX8_12", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW2END2_12", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_LH6_12", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_BYP4_12", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WL1END0_12", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_WW4B0_12", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_CLK0_12", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_NE4C2_12", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_WW2END1_12", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_IMUX22_12", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_12", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_IMUX37_12", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_NE4BEG0_12", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_12", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_12", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_NW4END0_12", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX44_12", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WW4END1_12", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_SE4BEG2_12", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE4BEG2_12", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX19_12", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_LH8_12", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_SW4END0_12", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_ER1BEG0_12", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_IMUX24_12", + "VFRAME_IMUX24" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + -9 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE2BEG2_19", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_SW2A3_19", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_WW2A0_19", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_EE2A2_19", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WR1END2_19", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_ER1BEG2_19", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_SW4A0_19", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_LH2_19", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NW4END0_19", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SW2A0_19", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_NW4A0_19", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_NE2A0_19", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_SW4A1_19", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_WL1END0_19", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_NE4BEG0_19", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_WW4END0_19", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WW4END2_19", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_EE4A2_19", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SW4A3_19", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_NE4C2_19", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE2A0_19", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_ER1BEG0_19", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_EL1BEG0_19", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_LH9_19", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NE4C1_19", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW4A1_19", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EE4A1_19", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_WW4C0_19", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NE4C0_19", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_NW4END2_19", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_SE2A1_19", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_SE4BEG3_19", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG1_19", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_EE4B3_19", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_LH1_19", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_WW4A0_19", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE4BEG3_19", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_NE4BEG3_19", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_NE2A1_19", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_EE4BEG0_19", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE4BEG2_19", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_EE4C0_19", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WW2A1_19", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_SW4END1_19", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EL1BEG3_19", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WW4B0_19", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_SW2A1_19", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_WR1END0_19", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_NW4END1_19", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_WW4C3_19", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE2A3_19", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_LH6_19", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_SE4C2_19", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_EL1BEG2_19", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_EE2BEG3_19", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_SE2A0_19", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_LH4_19", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_ER1BEG1_19", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WW4END3_19", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_NW4A3_19", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WW4B2_19", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_WW4END1_19", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE2BEG1_19", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NW4A2_19", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_SE4BEG0_19", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_WW4B3_19", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_NE4C3_19", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_LH5_19", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_WW4A2_19", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_NE4BEG2_19", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_NW2A3_19", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_LH7_19", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_EE4B0_19", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WL1END2_19", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SE4C3_19", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_SE2A2_19", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_WW4A3_19", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_EE4C1_19", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_SW4A2_19", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_EE2A1_19", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_WR1END1_19", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SE4C0_19", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_WW4B1_19", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW2END3_19", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_EE4B2_19", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_NW2A0_19", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_SW4END0_19", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_LH8_19", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_SW4END3_19", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_SW2A2_19", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WW4C2_19", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NE2A2_19", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_LH10_19", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_EE4A3_19", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_NE2A3_19", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_ER1BEG3_19", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WR1END3_19", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_SW4END2_19", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WL1END1_19", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_NW2A1_19", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_LH11_19", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EE2BEG0_19", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4C1_19", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SE2A3_19", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_NW4END3_19", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW2END1_19", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE4BEG1_19", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_EE4C3_19", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW2END2_19", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SE4BEG1_19", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_LH12_19", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW2A3_19", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_LH3_19", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SE4C1_19", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_EE4C2_19", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_EE4B1_19", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NW2A2_19", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_WW2END0_19", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WW2A2_19", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4BEG1_19", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_NW4A1_19", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WL1END3_19", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_SE4BEG2_19", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_EE4A0_19", + "INT_FEEDTHRU_2_EE4A0" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "CMT_TOP_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH6_3", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_LH1_3", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_LH12_3", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_LH7_3", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_3", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH3_3", + "VBRK_LH3" + ], + [ + "CMT_TOP_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_LH2_3", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH9_3", + "VBRK_LH9" + ], + [ + "CMT_TOP_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH5_3", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH11_3", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_LH10_3", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH8_3", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EL1BEG1_3", + "VBRK_EL1BEG1" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4C1_13", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX8_13", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW4END3_13", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_CTRL0_13", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_NE2A0_13", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_LH4_13", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_LH5_13", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_NW4A1_13", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_NE2A1_13", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_FAN0_13", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX31_13", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_IMUX47_13", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX45_13", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_SE2A0_13", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_WW4B1_13", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_FAN6_13", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_LH3_13", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_WW4C0_13", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_SE4BEG0_13", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_CLK1_13", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX40_13", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_NE4BEG0_13", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_BYP0_13", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_WW2END2_13", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_IMUX38_13", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX22_13", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX25_13", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_SW4END3_13", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_WW2END0_13", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WW4END2_13", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_FAN7_13", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_NW4END1_13", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_EE4A3_13", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_SW4END0_13", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX43_13", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_SE4BEG3_13", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG3_13", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW4C1_13", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_SE4C3_13", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_EE4C2_13", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX41_13", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_FAN2_13", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_WW4END1_13", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_WW4A1_13", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_IMUX46_13", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WL1END2_13", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_IMUX18_13", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX12_13", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX26_13", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_NE4BEG3_13", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NW4A0_13", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX3_13", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_BYP5_13", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_LH2_13", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_BYP3_13", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_EL1BEG1_13", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_FAN1_13", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_SW2A1_13", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WW4B3_13", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_EE4BEG2_13", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX27_13", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_SE4BEG2_13", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE2BEG3_13", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX20_13", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_EE4C3_13", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_SE2A2_13", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_EE2BEG1_13", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_WL1END3_13", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_EE4B1_13", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_LH11_13", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_IMUX2_13", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_BYP6_13", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_SW4A2_13", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_LH6_13", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_EE4BEG0_13", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_EE4A0_13", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_SW2A2_13", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_EE2A0_13", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WL1END1_13", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_IMUX1_13", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_SW4A3_13", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_LH7_13", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_IMUX23_13", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NW4END3_13", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_WW4A3_13", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_IMUX4_13", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_SW2A0_13", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_IMUX30_13", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_SW4END1_13", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_IMUX13_13", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_EE4C0_13", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_IMUX33_13", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_ER1BEG1_13", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_LH1_13", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_IMUX16_13", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_LH9_13", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_WR1END2_13", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SW2A3_13", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_SW4A0_13", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_NE4BEG1_13", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_NW2A0_13", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_IMUX37_13", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SE4C1_13", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_NE4C0_13", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE2BEG2_13", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX15_13", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_IMUX34_13", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_BYP1_13", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_IMUX0_13", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW4B2_13", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_NW4A2_13", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_FAN4_13", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW4C2_13", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_CLK0_13", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_WR1END3_13", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_ER1BEG3_13", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_NE4C2_13", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_SE2A1_13", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NW2A1_13", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_BYP7_13", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_WR1END0_13", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EL1BEG0_13", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_NE4C1_13", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_IMUX39_13", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_EE4A1_13", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_WW4B0_13", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_IMUX28_13", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_FAN5_13", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_NW4A3_13", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_IMUX6_13", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_EE4BEG1_13", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_WW4A2_13", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_IMUX36_13", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_EE4B3_13", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_NE4BEG2_13", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_IMUX32_13", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_WW2A2_13", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_FAN3_13", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_SW4END2_13", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_WW2A1_13", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_BYP4_13", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_EE2BEG0_13", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX5_13", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WW4END0_13", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_WW2END3_13", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW2A3_13", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_EE4A2_13", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX42_13", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_SW4A1_13", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_EL1BEG2_13", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX24_13", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_LH8_13", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_SE2A3_13", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_NW2A3_13", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_BYP2_13", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_ER1BEG2_13", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_WW4C3_13", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NE2A2_13", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WR1END1_13", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_IMUX17_13", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX21_13", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_WW4A0_13", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX35_13", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_WW2A0_13", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_CTRL1_13", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_EE4BEG3_13", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX10_13", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_IMUX11_13", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX44_13", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_EE2A2_13", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_EE2A3_13", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EE4B2_13", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_LH12_13", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX14_13", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_IMUX7_13", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_NE2A3_13", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX29_13", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_SE4C2_13", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_NW2A2_13", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_SE4BEG1_13", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_SE4C0_13", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_NW4END0_13", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_NW4END2_13", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_IMUX9_13", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_NE4C3_13", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_ER1BEG0_13", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_EE2A1_13", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX19_13", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_WW2END1_13", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_LH10_13", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_EE4B0_13", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WL1END0_13", + "VFRAME_WL1END0" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_PMV_R_CK_BUFG_CASC15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_PMV_R_CK_BUFG_CASC2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_PMV_R_CK_BUFG_CASC26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_PMV_R_CK_BUFG_CASC18" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_PMV_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_PMV_R_CK_BUFG_CASC23" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_PMV_R_CK_BUFG_CASC29" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_PMV_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_PMV_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_PMV_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_PMV_R_CK_BUFG_CASC14" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_PMV_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_PMV_R_CK_BUFG_CASC11" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_PMV_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_PMV_R_CK_BUFG_CASC31" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_PMV_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_PMV_R_CK_BUFG_CASC17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_PMV_R_CK_BUFG_CASC6" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_PMV_R_CK_BUFG_CASC4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_PMV_R_CK_BUFG_CASC9" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_PMV_R_CK_GCLK4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_PMV_R_CK_BUFG_CASC8" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_PMV_R_CK_BUFG_CASC30" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_PMV_R_CK_BUFG_CASC10" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_PMV_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_PMV_R_CK_BUFG_CASC27" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_PMV_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_PMV_R_CK_BUFG_CASC5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_PMV_R_CK_BUFG_CASC13" + ], + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_PMV_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_PMV_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_PMV_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_PMV_R_CK_BUFG_CASC24" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_PMV_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_PMV_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_PMV_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_PMV_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_PMV_R_CK_BUFG_CASC3" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_PMV_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_PMV_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_PMV_R_CK_BUFG_CASC12" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_PMV_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_PMV_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_PMV_R_CK_BUFG_CASC16" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_PMV_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_PMV_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_PMV_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_PMV_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_PMV_R_CK_BUFG_CASC1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_PMV_R_CK_BUFG_CASC20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_PMV_R_CK_BUFG_CASC21" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_PMV_R_CK_BUFG_CASC25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_PMV_R_CK_BUFG_CASC22" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_PMV_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_PMV_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_PMV_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_PMV_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_PMV_R_CK_BUFG_CASC7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_PMV_R_CK_BUFG_CASC0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_PMV_R_CK_BUFG_CASC28" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_PMV_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_PMV_R_CK_BUFG_CASC19" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_PMV_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_PMV_R_CK_GCLK15" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_PMV" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX44_4", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX34_4", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX28_4", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_LOGIC_OUTS_B11_4", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_IMUX6_4", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B22_4", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX36_4", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX4_4", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_CTRL1_4", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX29_4", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX30_4", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX35_4", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX12_4", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX45_4", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_LOGIC_OUTS_B14_4", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX7_4", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX10_4", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX39_4", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX23_4", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX33_4", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_LOGIC_OUTS_B15_4", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_FAN4_4", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_LOGIC_OUTS_B0_4", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_LOGIC_OUTS_B23_4", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_BYP6_4", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX27_4", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B8_4", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX15_4", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_FAN0_4", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_BYP3_4", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B13_4", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_IMUX5_4", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B12_4", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_LOGIC_OUTS_B16_4", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_CTRL0_4", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX9_4", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX11_4", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX19_4", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX21_4", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX17_4", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX16_4", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_LOGIC_OUTS_B9_4", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_FAN7_4", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX37_4", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_LOGIC_OUTS_B19_4", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B17_4", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B5_4", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_BYP0_4", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX26_4", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX22_4", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B6_4", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX2_4", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_BYP1_4", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B7_4", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_BYP2_4", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX8_4", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_FAN5_4", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX38_4", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX43_4", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_CLK1_4", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX41_4", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B18_4", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX1_4", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_FAN3_4", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN1_4", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B4_4", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B10_4", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_LOGIC_OUTS_B3_4", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_LOGIC_OUTS_B20_4", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX20_4", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX24_4", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_FAN2_4", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX46_4", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX13_4", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX3_4", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX42_4", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX18_4", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX0_4", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_BYP4_4", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX32_4", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN6_4", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX14_4", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_BYP7_4", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B1_4", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX31_4", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX40_4", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B2_4", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX25_4", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_BYP5_4", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX47_4", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_CLK0_4", + "VBRK_EXT_CLK0" + ] + ], + "tile_types": [ + "GTX_CHANNEL_0", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLK_BUFG_REBUF_EE4C3_0", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_BUFG_REBUF_SW4END1_0", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_BUFG_REBUF_EE4BEG1_0", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_BUFG_REBUF_NW2A0_0", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_BUFG_REBUF_SE4C1_0", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_BUFG_REBUF_EE4A2_0", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_BUFG_REBUF_WW4B3_0", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_BUFG_REBUF_WW4A1_0", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_BUFG_REBUF_EE4BEG3_0", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_BUFG_REBUF_NW2A2_0", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_BUFG_REBUF_SE2A1_0", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_BUFG_REBUF_NW4END3_0", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_BUFG_REBUF_EL1BEG0_0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_BUFG_REBUF_ER1BEG3_0", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_BUFG_REBUF_WW4B2_0", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_BUFG_REBUF_SE2A3_0", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_BUFG_REBUF_WW4END1_0", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_BUFG_REBUF_NE4C3_0", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_BUFG_REBUF_SE2A2_0", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_BUFG_REBUF_WW2END3_0", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_BUFG_REBUF_EE2A0_0", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_BUFG_REBUF_EE4BEG0_0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_BUFG_REBUF_EE2A3_0", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_BUFG_REBUF_SE4C0_0", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_BUFG_REBUF_NE4C1_0", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_BUFG_REBUF_EL1BEG1_0", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_BUFG_REBUF_EE4C2_0", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_BUFG_REBUF_EE4B2_0", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_BUFG_REBUF_EE4A0_0", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_BUFG_REBUF_ER1BEG0_0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_BUFG_REBUF_SW4A2_0", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_BUFG_REBUF_SW2A0_0", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_BUFG_REBUF_WW4C1_0", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_BUFG_REBUF_WL1END0_0", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_BUFG_REBUF_NW4A0_0", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_BUFG_REBUF_SW2A1_0", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_BUFG_REBUF_EL1BEG2_0", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_BUFG_REBUF_NE2A1_0", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_BUFG_REBUF_LH2_0", + "INT_INTERFACE_LH2" + ], + [ + "CLK_BUFG_REBUF_WW2END0_0", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_BUFG_REBUF_LH3_0", + "INT_INTERFACE_LH3" + ], + [ + "CLK_BUFG_REBUF_LH5_0", + "INT_INTERFACE_LH5" + ], + [ + "CLK_BUFG_REBUF_EE4B1_0", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_BUFG_REBUF_NE4BEG2_0", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_BUFG_REBUF_NW2A3_0", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_BUFG_REBUF_NE4C2_0", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_BUFG_REBUF_SE4BEG2_0", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_BUFG_REBUF_WR1END1_0", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_BUFG_REBUF_WR1END0_0", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_BUFG_REBUF_SE2A0_0", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_BUFG_REBUF_EE4B3_0", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_BUFG_REBUF_NW4END2_0", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_BUFG_REBUF_NW4A2_0", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_BUFG_REBUF_SW4END2_0", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_BUFG_REBUF_EE2BEG3_0", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_BUFG_REBUF_WW4B0_0", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_BUFG_REBUF_EE4BEG2_0", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_BUFG_REBUF_LH12_0", + "INT_INTERFACE_LH12" + ], + [ + "CLK_BUFG_REBUF_WW2A0_0", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_BUFG_REBUF_WL1END1_0", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_BUFG_REBUF_NE4BEG1_0", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_BUFG_REBUF_SE4C3_0", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_BUFG_REBUF_WW4A2_0", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_BUFG_REBUF_WW4A0_0", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_BUFG_REBUF_LH9_0", + "INT_INTERFACE_LH9" + ], + [ + "CLK_BUFG_REBUF_LH8_0", + "INT_INTERFACE_LH8" + ], + [ + "CLK_BUFG_REBUF_ER1BEG2_0", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_BUFG_REBUF_SW4END0_0", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_BUFG_REBUF_SW4A0_0", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_BUFG_REBUF_SW4A1_0", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_BUFG_REBUF_LH4_0", + "INT_INTERFACE_LH4" + ], + [ + "CLK_BUFG_REBUF_ER1BEG1_0", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_BUFG_REBUF_LH1_0", + "INT_INTERFACE_LH1" + ], + [ + "CLK_BUFG_REBUF_SW2A2_0", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_BUFG_REBUF_WW4C2_0", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_BUFG_REBUF_SE4BEG3_0", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_BUFG_REBUF_SE4BEG0_0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_BUFG_REBUF_EE2BEG1_0", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_BUFG_REBUF_NW4A3_0", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_BUFG_REBUF_LH6_0", + "INT_INTERFACE_LH6" + ], + [ + "CLK_BUFG_REBUF_WW4END0_0", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_BUFG_REBUF_SE4BEG1_0", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_BUFG_REBUF_EE4A3_0", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_BUFG_REBUF_EE2A2_0", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_BUFG_REBUF_WR1END3_0", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_BUFG_REBUF_EE4A1_0", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_BUFG_REBUF_WW4C3_0", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_BUFG_REBUF_SE4C2_0", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_BUFG_REBUF_LH10_0", + "INT_INTERFACE_LH10" + ], + [ + "CLK_BUFG_REBUF_WW2A3_0", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_BUFG_REBUF_NW4A1_0", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_BUFG_REBUF_EE2BEG0_0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_BUFG_REBUF_WW2END2_0", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_BUFG_REBUF_WL1END3_0", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_BUFG_REBUF_NE4BEG0_0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_BUFG_REBUF_NE2A0_0", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_BUFG_REBUF_SW4END3_0", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_BUFG_REBUF_EL1BEG3_0", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_BUFG_REBUF_SW2A3_0", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_BUFG_REBUF_WW4END2_0", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_BUFG_REBUF_EE4C0_0", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_BUFG_REBUF_WL1END2_0", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_BUFG_REBUF_SW4A3_0", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_BUFG_REBUF_WW2A1_0", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_BUFG_REBUF_EE2A1_0", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_BUFG_REBUF_EE2BEG2_0", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_BUFG_REBUF_NE2A2_0", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_BUFG_REBUF_NE2A3_0", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_BUFG_REBUF_LH7_0", + "INT_INTERFACE_LH7" + ], + [ + "CLK_BUFG_REBUF_EE4C1_0", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_BUFG_REBUF_LH11_0", + "INT_INTERFACE_LH11" + ], + [ + "CLK_BUFG_REBUF_WW4C0_0", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_BUFG_REBUF_NW4END1_0", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_BUFG_REBUF_WW4END3_0", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_BUFG_REBUF_NW2A1_0", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_BUFG_REBUF_WW2END1_0", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_BUFG_REBUF_WR1END2_0", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_BUFG_REBUF_NW4END0_0", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_BUFG_REBUF_WW4A3_0", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_BUFG_REBUF_NE4C0_0", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_BUFG_REBUF_EE4B0_0", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_BUFG_REBUF_NE4BEG3_0", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_BUFG_REBUF_WW2A2_0", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_BUFG_REBUF_WW4B1_0", + "INT_INTERFACE_WW4B1" + ] + ], + "tile_types": [ + "CLK_BUFG_REBUF", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -5 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW4B1_13", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4BEG0_13", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_EE2BEG3_13", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH10_13", + "VBRK_LH10" + ], + [ + "CMT_TOP_NW4A1_13", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NW2A3_13", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW2END2_13", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2END3_13", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4C0_13", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_NW4END1_13", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW4C2_13", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW4END0_13", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NE2A3_13", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_LH2_13", + "VBRK_LH2" + ], + [ + "CMT_TOP_LH9_13", + "VBRK_LH9" + ], + [ + "CMT_TOP_SW2A0_13", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4C2_13", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EE4A3_13", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_LH1_13", + "VBRK_LH1" + ], + [ + "CMT_TOP_SW4END3_13", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NW2A2_13", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A2_13", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE2A0_13", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4B0_13", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_LH11_13", + "VBRK_LH11" + ], + [ + "CMT_TOP_SW4A2_13", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW2A1_13", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH3_13", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4BEG0_13", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE2A1_13", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW2END1_13", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE2A2_13", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END0_13", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW4END2_13", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WR1END1_13", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH5_13", + "VBRK_LH5" + ], + [ + "CMT_TOP_SE4BEG3_13", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE2BEG1_13", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4C0_13", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_MONITOR_P_13", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_SE4BEG1_13", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH8_13", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW2A2_13", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4A3_13", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2A3_13", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_NW4A0_13", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NW4A3_13", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WW2END0_13", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4B0_13", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE2A0_13", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH6_13", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B3_13", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NE4BEG3_13", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_LH12_13", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE2A3_13", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG2_13", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW2A3_13", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4C3_13", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WL1END3_13", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_ER1BEG2_13", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2BEG0_13", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW2A0_13", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WW4END0_13", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WR1END2_13", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A2_13", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4BEG2_13", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NE4BEG1_13", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SE4C0_13", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_LH7_13", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4C3_13", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_ER1BEG0_13", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END1_13", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_13", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_NE2A0_13", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NE4C3_13", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW4A0_13", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NW2A0_13", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WR1END3_13", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SW4END2_13", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_WW4A3_13", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_NE2A1_13", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C1_13", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SE2A2_13", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2A1_13", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE4C1_13", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE4C2_13", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4C1_13", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_EL1BEG0_13", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_EE4A1_13", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EE2A1_13", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_SE4C2_13", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4END1_13", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SW4END0_13", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_NW2A1_13", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4END2_13", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_SE4C1_13", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE4BEG1_13", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EE4A0_13", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_LH4_13", + "VBRK_LH4" + ], + [ + "CMT_TOP_SW4A1_13", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4END3_13", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE2BEG2_13", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SW2A3_13", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_13", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4BEG0_13", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SW4A0_13", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_ER1BEG1_13", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE4A2_13", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4A1_13", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_MONITOR_N_13", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW4END3_13", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4C3_13", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4B1_13", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_EE4BEG3_13", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4BEG2_13", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW2A2_13", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG1_13", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_ER1BEG3_13", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WR1END0_13", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WL1END1_13", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW4B2_13", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4C0_13", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EL1BEG2_13", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WL1END2_13", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B3_13", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4B2_13", + "VBRK_EE4B2" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 9 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW4END1_2", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE4B0_2", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WW2END0_2", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_LH2_2", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_EE4A1_2", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EE2BEG2_2", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW4A0_2", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SW4A1_2", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_WW4B2_2", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_SE2A3_2", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SE4BEG3_2", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EE4C1_2", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_WR1END2_2", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_WW4END2_2", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_NE2A0_2", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EE4BEG1_2", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_WR1END1_2", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WW4C0_2", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_LH4_2", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_NW4END3_2", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW4C3_2", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4A2_2", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE2A3_2", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW4A1_2", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EE2BEG3_2", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NW4END0_2", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SW2A2_2", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WW4END0_2", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EE4B1_2", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NE2A3_2", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_LH12_2", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_LH7_2", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_LH3_2", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_NW4A0_2", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SW2A0_2", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WR1END3_2", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE4BEG0_2", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WW4B1_2", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW4A3_2", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NW2A2_2", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_LH10_2", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_LH1_2", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_WW4C2_2", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NW2A3_2", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE4C3_2", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_ER1BEG2_2", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_NW4END1_2", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_LH11_2", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW4B3_2", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_NE4C1_2", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE4C0_2", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_EE4BEG2_2", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_NE2A2_2", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_NW4END2_2", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WL1END2_2", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WW2A3_2", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WW2END2_2", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_NE4BEG2_2", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG0_2", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_SE4BEG0_2", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SE2A0_2", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SW2A3_2", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_EL1BEG2_2", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_LH9_2", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_SE4C1_2", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_WW2A1_2", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_SE4BEG1_2", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SE2A2_2", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4C2_2", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_ER1BEG0_2", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_SW4A2_2", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_SE4C3_2", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_EE2BEG1_2", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_WW4B0_2", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_NE2A1_2", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_SE2A1_2", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_EE4C0_2", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WW2END1_2", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_WW4C1_2", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_NW4A1_2", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SW4END3_2", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NW4A2_2", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WW2A0_2", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_SW4A0_2", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE2A2_2", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_EE4B2_2", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_SW4END2_2", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_NE4BEG1_2", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_EE4BEG3_2", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WL1END0_2", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SW4END0_2", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EE2BEG0_2", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_SE4C2_2", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_NW2A0_2", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_EE2A1_2", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_WL1END1_2", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_ER1BEG1_2", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WL1END3_2", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4A0_2", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4A3_2", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_WW2END3_2", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_SW4END1_2", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_LH6_2", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_LH8_2", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_EL1BEG1_2", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NW4A3_2", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_NE4BEG3_2", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_EE4B3_2", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_ER1BEG3_2", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_NW2A1_2", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C3_2", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW2A2_2", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WR1END0_2", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_EL1BEG3_2", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_EE2A0_2", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_LH5_2", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_SW4A3_2", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_WW4END3_2", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_NE4BEG0_2", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_SE4C0_2", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_SW2A1_2", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_NE4C2_2", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE4A2_2", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SE4BEG2_2", + "INT_FEEDTHRU_2_SE4BEG2" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "IOI_IMUX11_0", + "TERM_INT_IMUX11" + ], + [ + "IOI_IMUX43_0", + "TERM_INT_IMUX43" + ], + [ + "IOI_FAN1_0", + "TERM_INT_FAN1" + ], + [ + "IOI_LOGIC_OUTS18_0", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_CTRL1_0", + "TERM_INT_CTRL1" + ], + [ + "IOI_BYP2_0", + "TERM_INT_BYP2" + ], + [ + "IOI_LOGIC_OUTS2_0", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_IMUX6_0", + "TERM_INT_IMUX6" + ], + [ + "IOI_IMUX36_0", + "TERM_INT_IMUX36" + ], + [ + "IOI_IMUX34_0", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX0_0", + "TERM_INT_IMUX0" + ], + [ + "IOI_IMUX46_0", + "TERM_INT_IMUX46" + ], + [ + "IOI_LOGIC_OUTS23_0", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_IMUX20_0", + "TERM_INT_IMUX20" + ], + [ + "IOI_LOGIC_OUTS15_0", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX19_0", + "TERM_INT_IMUX19" + ], + [ + "IOI_IMUX47_0", + "TERM_INT_IMUX47" + ], + [ + "IOI_IMUX25_0", + "TERM_INT_IMUX25" + ], + [ + "IOI_LOGIC_OUTS7_0", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_FAN2_0", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX45_0", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX31_0", + "TERM_INT_IMUX31" + ], + [ + "IOI_LOGIC_OUTS19_0", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_IMUX1_0", + "TERM_INT_IMUX1" + ], + [ + "IOI_MONITOR_N", + "TERM_INT_MONITOR_N" + ], + [ + "IOI_IMUX22_0", + "TERM_INT_IMUX22" + ], + [ + "IOI_IMUX12_0", + "TERM_INT_IMUX12" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_BLOCK_OUTS2_0", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "LIOI_I2GCLK_TOP0", + "L_TERM_INT_DQS_IOTOPHASER" + ], + [ + "IOI_IMUX40_0", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX10_0", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX16_0", + "TERM_INT_IMUX16" + ], + [ + "IOI_FAN0_0", + "TERM_INT_FAN0" + ], + [ + "IOI_IMUX38_0", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX26_0", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX3_0", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX24_0", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX37_0", + "TERM_INT_IMUX37" + ], + [ + "IOI_LOGIC_OUTS3_0", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_FAN4_0", + "TERM_INT_FAN4" + ], + [ + "IOI_FAN6_0", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX7_0", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX39_0", + "TERM_INT_IMUX39" + ], + [ + "IOI_CLK0_0", + "TERM_INT_CLK0" + ], + [ + "IOI_CTRL0_0", + "TERM_INT_CTRL0" + ], + [ + "IOI_CLK1_0", + "TERM_INT_CLK1" + ], + [ + "IOI_FAN7_0", + "TERM_INT_FAN7" + ], + [ + "IOI_BYP0_0", + "TERM_INT_BYP0" + ], + [ + "IOI_LOGIC_OUTS0_0", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_IMUX8_0", + "TERM_INT_IMUX8" + ], + [ + "IOI_LOGIC_OUTS11_0", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_BYP6_0", + "TERM_INT_BYP6" + ], + [ + "IOI_IMUX42_0", + "TERM_INT_IMUX42" + ], + [ + "IOI_IMUX30_0", + "TERM_INT_IMUX30" + ], + [ + "IOI_LOGIC_OUTS1_0", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX5_0", + "TERM_INT_IMUX5" + ], + [ + "IOI_IMUX4_0", + "TERM_INT_IMUX4" + ], + [ + "IOI_IMUX17_0", + "TERM_INT_IMUX17" + ], + [ + "IOI_IMUX23_0", + "TERM_INT_IMUX23" + ], + [ + "IOI_IMUX33_0", + "TERM_INT_IMUX33" + ], + [ + "IOI_PHASER_TO_IO_ICLK", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_FAN5_0", + "TERM_INT_FAN5" + ], + [ + "IOI_LOGIC_OUTS9_0", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_BYP1_0", + "TERM_INT_BYP1" + ], + [ + "IOI_LOGIC_OUTS14_0", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_IMUX13_0", + "TERM_INT_IMUX13" + ], + [ + "IOI_IMUX44_0", + "TERM_INT_IMUX44" + ], + [ + "IOI_LOGIC_OUTS20_0", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_LOGIC_OUTS5_0", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_IMUX27_0", + "TERM_INT_IMUX27" + ], + [ + "IOI_IMUX18_0", + "TERM_INT_IMUX18" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_IMUX9_0", + "TERM_INT_IMUX9" + ], + [ + "IOI_FAN3_0", + "TERM_INT_FAN3" + ], + [ + "IOI_BYP5_0", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS8_0", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_PHASER_TO_IO_OCLK", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_BYP4_0", + "TERM_INT_BYP4" + ], + [ + "IOI_BYP7_0", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_0", + "TERM_INT_IMUX2" + ], + [ + "IOI_IMUX35_0", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP3_0", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX15_0", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX29_0", + "TERM_INT_IMUX29" + ], + [ + "IOI_LOGIC_OUTS10_0", + "TERM_INT_LOGIC_OUTS_L_B10" + ], + [ + "IOI_IMUX14_0", + "TERM_INT_IMUX14" + ], + [ + "IOI_MONITOR_P", + "TERM_INT_MONITOR_P" + ], + [ + "IOI_IMUX21_0", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX28_0", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX41_0", + "TERM_INT_IMUX41" + ], + [ + "IOI_BLOCK_OUTS0_0", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_IMUX32_0", + "TERM_INT_IMUX32" + ] + ], + "tile_types": [ + "LIOI3_TBYTESRC", + "L_TERM_INT" + ] + }, + { + "grid_deltas": [ + 1, + 7 + ], + "wire_pairs": [ + [ + "CMT_TOP_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_LH2_1", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH11_1", + "VBRK_LH11" + ], + [ + "CMT_TOP_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH10_1", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_LH8_1", + "VBRK_LH8" + ], + [ + "CMT_TOP_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH3_1", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH4_1", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH5_1", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_MONITOR_P_1", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_1", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_LH6_1", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH1_1", + "VBRK_LH1" + ], + [ + "CMT_TOP_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_LH7_1", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_MONITOR_N_1", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH9_1", + "VBRK_LH9" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "BRKH_CLK_R_CK_GCLK24", + "CLK_BUFG_CK_GCLK24" + ], + [ + "BRKH_CLK_R_CK_GCLK23", + "CLK_BUFG_CK_GCLK23" + ], + [ + "BRKH_CLK_R_CK_GCLK0", + "CLK_BUFG_CK_GCLK0" + ], + [ + "BRKH_CLK_R_CK_GCLK25", + "CLK_BUFG_CK_GCLK25" + ], + [ + "BRKH_CLK_R_CK_GCLK27", + "CLK_BUFG_CK_GCLK27" + ], + [ + "BRKH_CLK_R_CK_GCLK11", + "CLK_BUFG_CK_GCLK11" + ], + [ + "BRKH_CLK_R_CK_GCLK2", + "CLK_BUFG_CK_GCLK2" + ], + [ + "BRKH_CLK_R_CK_GCLK8", + "CLK_BUFG_CK_GCLK8" + ], + [ + "BRKH_CLK_R_CK_GCLK21", + "CLK_BUFG_CK_GCLK21" + ], + [ + "BRKH_CLK_R_CK_GCLK3", + "CLK_BUFG_CK_GCLK3" + ], + [ + "BRKH_CLK_R_CK_GCLK14", + "CLK_BUFG_CK_GCLK14" + ], + [ + "BRKH_CLK_R_CK_GCLK13", + "CLK_BUFG_CK_GCLK13" + ], + [ + "BRKH_CLK_R_CK_GCLK30", + "CLK_BUFG_CK_GCLK30" + ], + [ + "BRKH_CLK_R_CK_GCLK29", + "CLK_BUFG_CK_GCLK29" + ], + [ + "BRKH_CLK_R_CK_GCLK19", + "CLK_BUFG_CK_GCLK19" + ], + [ + "BRKH_CLK_R_CK_GCLK17", + "CLK_BUFG_CK_GCLK17" + ], + [ + "BRKH_CLK_R_CK_GCLK7", + "CLK_BUFG_CK_GCLK7" + ], + [ + "BRKH_CLK_R_CK_GCLK20", + "CLK_BUFG_CK_GCLK20" + ], + [ + "BRKH_CLK_R_CK_GCLK5", + "CLK_BUFG_CK_GCLK5" + ], + [ + "BRKH_CLK_R_CK_GCLK10", + "CLK_BUFG_CK_GCLK10" + ], + [ + "BRKH_CLK_R_CK_GCLK16", + "CLK_BUFG_CK_GCLK16" + ], + [ + "BRKH_CLK_R_CK_GCLK1", + "CLK_BUFG_CK_GCLK1" + ], + [ + "BRKH_CLK_R_CK_GCLK12", + "CLK_BUFG_CK_GCLK12" + ], + [ + "BRKH_CLK_R_CK_GCLK15", + "CLK_BUFG_CK_GCLK15" + ], + [ + "BRKH_CLK_R_CK_GCLK22", + "CLK_BUFG_CK_GCLK22" + ], + [ + "BRKH_CLK_R_CK_GCLK9", + "CLK_BUFG_CK_GCLK9" + ], + [ + "BRKH_CLK_R_CK_GCLK18", + "CLK_BUFG_CK_GCLK18" + ], + [ + "BRKH_CLK_R_CK_GCLK6", + "CLK_BUFG_CK_GCLK6" + ], + [ + "BRKH_CLK_R_CK_GCLK4", + "CLK_BUFG_CK_GCLK4" + ], + [ + "BRKH_CLK_R_CK_GCLK26", + "CLK_BUFG_CK_GCLK26" + ], + [ + "BRKH_CLK_R_CK_GCLK28", + "CLK_BUFG_CK_GCLK28" + ], + [ + "BRKH_CLK_R_CK_GCLK31", + "CLK_BUFG_CK_GCLK31" + ] + ], + "tile_types": [ + "BRKH_CLK", + "CLK_BUFG_TOP_R" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_IMUX47_6", + "CMT_TOP_IMUX47_6" + ], + [ + "CMT_FIFO_L_IMUX45_6", + "CMT_TOP_IMUX45_6" + ], + [ + "CMT_FIFO_WW4B2_7", + "CMT_TOP_WW4B2_7" + ], + [ + "CMT_FIFO_SE4BEG3_3", + "CMT_TOP_SE4BEG3_3" + ], + [ + "CMT_FIFO_SW4END2_3", + "CMT_TOP_SW4END2_3" + ], + [ + "CMT_FIFO_L_BYP4_6", + "CMT_TOP_BYP4_6" + ], + [ + "CMT_FIFO_LH11_10", + "CMT_TOP_LH11_10" + ], + [ + "CMT_FIFO_L_IMUX22_4", + "CMT_TOP_IMUX22_4" + ], + [ + "CMT_FIFO_L_IMUX12_3", + "CMT_TOP_IMUX12_3" + ], + [ + "CMT_FIFO_SE2A3_1", + "CMT_TOP_SE2A3_1" + ], + [ + "CMT_FIFO_SW4A0_2", + "CMT_TOP_SW4A0_2" + ], + [ + "CMT_FIFO_LH3_2", + "CMT_TOP_LH3_2" + ], + [ + "CMT_FIFO_SW4END1_9", + "CMT_TOP_SW4END1_9" + ], + [ + "CMT_FIFO_L_IMUX8_9", + "CMT_TOP_IMUX8_9" + ], + [ + "CMT_FIFO_EE4A3_7", + "CMT_TOP_EE4A3_7" + ], + [ + "CMT_FIFO_SW4END3_11", + "CMT_TOP_SW4END3_11" + ], + [ + "CMT_FIFO_SE4C3_9", + "CMT_TOP_SE4C3_9" + ], + [ + "CMT_FIFO_NE4C0_10", + "CMT_TOP_NE4C0_10" + ], + [ + "CMT_FIFO_NE2A1_6", + "CMT_TOP_NE2A1_6" + ], + [ + "CMT_FIFO_WW2A0_8", + "CMT_TOP_WW2A0_8" + ], + [ + "CMT_FIFO_L_FAN3_4", + "CMT_TOP_FAN3_4" + ], + [ + "CMT_FIFO_NW4END3_6", + "CMT_TOP_NW4END3_6" + ], + [ + "CMT_FIFO_NW2A2_6", + "CMT_TOP_NW2A2_6" + ], + [ + "CMT_FIFO_SW4END1_8", + "CMT_TOP_SW4END1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_2", + "CMT_TOP_LOGIC_OUTS_L_B21_2" + ], + [ + "CMT_FIFO_WW2END1_5", + "CMT_TOP_WW2END1_5" + ], + [ + "CMT_FIFO_L_BYP6_2", + "CMT_TOP_BYP6_2" + ], + [ + "CMT_FIFO_NE4C0_8", + "CMT_TOP_NE4C0_8" + ], + [ + "CMT_FIFO_EE4A2_1", + "CMT_TOP_EE4A2_1" + ], + [ + "CMT_FIFO_EL1BEG0_9", + "CMT_TOP_EL1BEG0_9" + ], + [ + "CMT_FIFO_LH1_9", + "CMT_TOP_LH1_9" + ], + [ + "CMT_FIFO_WL1END1_11", + "CMT_TOP_WL1END1_11" + ], + [ + "CMT_FIFO_WW4C0_9", + "CMT_TOP_WW4C0_9" + ], + [ + "CMT_FIFO_WW2A2_7", + "CMT_TOP_WW2A2_7" + ], + [ + "CMT_FIFO_NW2A0_6", + "CMT_TOP_NW2A0_6" + ], + [ + "CMT_FIFO_NW4END3_7", + "CMT_TOP_NW4END3_7" + ], + [ + "CMT_FIFO_NE2A3_10", + "CMT_TOP_NE2A3_10" + ], + [ + "CMT_FIFO_EE2A0_9", + "CMT_TOP_EE2A0_9" + ], + [ + "CMT_FIFO_ER1BEG0_11", + "CMT_TOP_ER1BEG0_11" + ], + [ + "CMT_FIFO_ER1BEG2_7", + "CMT_TOP_ER1BEG2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_4", + "CMT_TOP_LOGIC_OUTS_L_B17_4" + ], + [ + "CMT_FIFO_LH3_8", + "CMT_TOP_LH3_8" + ], + [ + "CMT_FIFO_L_FAN5_2", + "CMT_TOP_FAN5_2" + ], + [ + "CMT_FIFO_L_BYP7_0", + "CMT_TOP_BYP7_0" + ], + [ + "CMT_FIFO_L_IMUX43_10", + "CMT_TOP_IMUX43_10" + ], + [ + "CMT_FIFO_L_IMUX5_9", + "CMT_TOP_IMUX5_9" + ], + [ + "CMT_FIFO_WW4C3_8", + "CMT_TOP_WW4C3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_8", + "CMT_TOP_LOGIC_OUTS_L_B15_8" + ], + [ + "CMT_FIFO_WW2A3_11", + "CMT_TOP_WW2A3_11" + ], + [ + "CMT_FIFO_WW4A0_8", + "CMT_TOP_WW4A0_8" + ], + [ + "CMT_FIFO_WW4END1_0", + "CMT_TOP_WW4END1_0" + ], + [ + "CMT_FIFO_WW4END2_2", + "CMT_TOP_WW4END2_2" + ], + [ + "CMT_FIFO_WW4END3_4", + "CMT_TOP_WW4END3_4" + ], + [ + "CMT_FIFO_EE4BEG3_9", + "CMT_TOP_EE4BEG3_9" + ], + [ + "CMT_FIFO_SW4A1_3", + "CMT_TOP_SW4A1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_4", + "CMT_TOP_LOGIC_OUTS_L_B9_4" + ], + [ + "CMT_FIFO_L_FAN6_1", + "CMT_TOP_FAN6_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_11", + "CMT_TOP_LOGIC_OUTS_L_B1_11" + ], + [ + "CMT_FIFO_L_IMUX14_1", + "CMT_TOP_IMUX14_1" + ], + [ + "CMT_FIFO_EL1BEG2_8", + "CMT_TOP_EL1BEG2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "CMT_TOP_ICLK_1" + ], + [ + "CMT_FIFO_SW4A2_5", + "CMT_TOP_SW4A2_5" + ], + [ + "CMT_FIFO_L_BYP6_8", + "CMT_TOP_BYP6_8" + ], + [ + "CMT_FIFO_EE4BEG3_0", + "CMT_TOP_EE4BEG3_0" + ], + [ + "CMT_FIFO_L_CTRL0_2", + "CMT_TOP_CTRL0_2" + ], + [ + "CMT_FIFO_WL1END3_4", + "CMT_TOP_WL1END3_4" + ], + [ + "CMT_FIFO_L_IMUX9_7", + "CMT_TOP_IMUX9_7" + ], + [ + "CMT_FIFO_L_BYP6_1", + "CMT_TOP_BYP6_1" + ], + [ + "CMT_FIFO_L_IMUX18_2", + "CMT_TOP_IMUX18_2" + ], + [ + "CMT_FIFO_EL1BEG2_7", + "CMT_TOP_EL1BEG2_7" + ], + [ + "CMT_FIFO_L_IMUX16_5", + "CMT_TOP_IMUX16_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_1", + "CMT_TOP_LOGIC_OUTS_L_B11_1" + ], + [ + "CMT_FIFO_LH2_6", + "CMT_TOP_LH2_6" + ], + [ + "CMT_FIFO_NE4C1_2", + "CMT_TOP_NE4C1_2" + ], + [ + "CMT_FIFO_NE2A0_2", + "CMT_TOP_NE2A0_2" + ], + [ + "CMT_FIFO_SW4END3_9", + "CMT_TOP_SW4END3_9" + ], + [ + "CMT_FIFO_SW4A0_7", + "CMT_TOP_SW4A0_7" + ], + [ + "CMT_FIFO_ER1BEG2_10", + "CMT_TOP_ER1BEG2_10" + ], + [ + "CMT_FIFO_EL1BEG0_10", + "CMT_TOP_EL1BEG0_10" + ], + [ + "CMT_FIFO_WW4C1_9", + "CMT_TOP_WW4C1_9" + ], + [ + "CMT_FIFO_LH7_0", + "CMT_TOP_LH7_0" + ], + [ + "CMT_FIFO_WW2A0_9", + "CMT_TOP_WW2A0_9" + ], + [ + "CMT_FIFO_NE2A2_0", + "CMT_TOP_NE2A2_0" + ], + [ + "CMT_FIFO_L_IMUX0_5", + "CMT_TOP_IMUX0_5" + ], + [ + "CMT_FIFO_L_IMUX24_10", + "CMT_TOP_IMUX24_10" + ], + [ + "CMT_FIFO_ER1BEG3_3", + "CMT_TOP_ER1BEG3_3" + ], + [ + "CMT_FIFO_L_FAN4_4", + "CMT_TOP_FAN4_4" + ], + [ + "CMT_FIFO_LH12_6", + "CMT_TOP_LH12_6" + ], + [ + "CMT_FIFO_SW2A0_10", + "CMT_TOP_SW2A0_10" + ], + [ + "CMT_FIFO_L_IMUX24_1", + "CMT_TOP_IMUX24_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "CMT_TOP_ICLKDIV_2" + ], + [ + "CMT_FIFO_L_IMUX47_8", + "CMT_TOP_IMUX47_8" + ], + [ + "CMT_FIFO_SW2A3_2", + "CMT_TOP_SW2A3_2" + ], + [ + "CMT_FIFO_L_IMUX26_6", + "CMT_TOP_IMUX26_6" + ], + [ + "CMT_FIFO_WW4C0_11", + "CMT_TOP_WW4C0_11" + ], + [ + "CMT_FIFO_L_FAN3_8", + "CMT_TOP_FAN3_8" + ], + [ + "CMT_FIFO_SW2A3_9", + "CMT_TOP_SW2A3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_10", + "CMT_TOP_LOGIC_OUTS_L_B20_10" + ], + [ + "CMT_FIFO_L_BYP5_1", + "CMT_TOP_BYP5_1" + ], + [ + "CMT_FIFO_SE4C3_8", + "CMT_TOP_SE4C3_8" + ], + [ + "CMT_FIFO_WW4B1_10", + "CMT_TOP_WW4B1_10" + ], + [ + "CMT_FIFO_WW2A3_7", + "CMT_TOP_WW2A3_7" + ], + [ + "CMT_FIFO_L_BYP0_0", + "CMT_TOP_BYP0_0" + ], + [ + "CMT_FIFO_L_IMUX36_5", + "CMT_TOP_IMUX36_5" + ], + [ + "CMT_FIFO_L_FAN6_6", + "CMT_TOP_FAN6_6" + ], + [ + "CMT_FIFO_WW4A3_3", + "CMT_TOP_WW4A3_3" + ], + [ + "CMT_FIFO_L_IMUX31_5", + "CMT_TOP_IMUX31_5" + ], + [ + "CMT_FIFO_L_FAN1_4", + "CMT_TOP_FAN1_4" + ], + [ + "CMT_FIFO_WW2END3_11", + "CMT_TOP_WW2END3_11" + ], + [ + "CMT_FIFO_L_CLK1_10", + "CMT_TOP_CLK1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_3", + "CMT_TOP_LOGIC_OUTS_L_B15_3" + ], + [ + "CMT_FIFO_ER1BEG3_6", + "CMT_TOP_ER1BEG3_6" + ], + [ + "CMT_FIFO_NW4END3_3", + "CMT_TOP_NW4END3_3" + ], + [ + "CMT_FIFO_WR1END1_8", + "CMT_TOP_WR1END1_8" + ], + [ + "CMT_FIFO_WW4B2_6", + "CMT_TOP_WW4B2_6" + ], + [ + "CMT_FIFO_L_FAN5_6", + "CMT_TOP_FAN5_6" + ], + [ + "CMT_FIFO_NW4END2_9", + "CMT_TOP_NW4END2_9" + ], + [ + "CMT_FIFO_WW2A2_8", + "CMT_TOP_WW2A2_8" + ], + [ + "CMT_FIFO_NE2A0_8", + "CMT_TOP_NE2A0_8" + ], + [ + "CMT_FIFO_EE4C0_4", + "CMT_TOP_EE4C0_4" + ], + [ + "CMT_FIFO_LH9_2", + "CMT_TOP_LH9_2" + ], + [ + "CMT_FIFO_EL1BEG1_11", + "CMT_TOP_EL1BEG1_11" + ], + [ + "CMT_FIFO_L_IMUX5_7", + "CMT_TOP_IMUX5_7" + ], + [ + "CMT_FIFO_L_IMUX5_3", + "CMT_TOP_IMUX5_3" + ], + [ + "CMT_FIFO_LH2_3", + "CMT_TOP_LH2_3" + ], + [ + "CMT_FIFO_EE2A3_4", + "CMT_TOP_EE2A3_4" + ], + [ + "CMT_FIFO_EL1BEG3_6", + "CMT_TOP_EL1BEG3_6" + ], + [ + "CMT_FIFO_L_BYP5_3", + "CMT_TOP_BYP5_3" + ], + [ + "CMT_FIFO_L_IMUX7_8", + "CMT_TOP_IMUX7_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_7", + "CMT_TOP_LOGIC_OUTS_L_B2_7" + ], + [ + "CMT_FIFO_EE4A0_7", + "CMT_TOP_EE4A0_7" + ], + [ + "CMT_FIFO_L_IMUX30_10", + "CMT_TOP_IMUX30_10" + ], + [ + "CMT_FIFO_WW2END1_4", + "CMT_TOP_WW2END1_4" + ], + [ + "CMT_FIFO_WW4END2_4", + "CMT_TOP_WW4END2_4" + ], + [ + "CMT_FIFO_L_FAN5_10", + "CMT_TOP_FAN5_10" + ], + [ + "CMT_FIFO_NE2A2_1", + "CMT_TOP_NE2A2_1" + ], + [ + "CMT_FIFO_WL1END1_2", + "CMT_TOP_WL1END1_2" + ], + [ + "CMT_FIFO_L_IMUX9_0", + "CMT_TOP_IMUX9_0" + ], + [ + "CMT_FIFO_L_FAN6_8", + "CMT_TOP_FAN6_8" + ], + [ + "CMT_FIFO_L_IMUX21_3", + "CMT_TOP_IMUX21_3" + ], + [ + "CMT_FIFO_WW2END0_1", + "CMT_TOP_WW2END0_1" + ], + [ + "CMT_FIFO_LH2_8", + "CMT_TOP_LH2_8" + ], + [ + "CMT_FIFO_L_IMUX27_9", + "CMT_TOP_IMUX27_9" + ], + [ + "CMT_FIFO_SW4END1_1", + "CMT_TOP_SW4END1_1" + ], + [ + "CMT_FIFO_EE2A0_4", + "CMT_TOP_EE2A0_4" + ], + [ + "CMT_FIFO_WW4END0_10", + "CMT_TOP_WW4END0_10" + ], + [ + "CMT_FIFO_L_IMUX7_2", + "CMT_TOP_IMUX7_2" + ], + [ + "CMT_FIFO_NW4A0_6", + "CMT_TOP_NW4A0_6" + ], + [ + "CMT_FIFO_L_IMUX42_0", + "CMT_TOP_IMUX42_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_10" + ], + [ + "CMT_FIFO_L_BYP4_4", + "CMT_TOP_BYP4_4" + ], + [ + "CMT_FIFO_SE2A2_3", + "CMT_TOP_SE2A2_3" + ], + [ + "CMT_FIFO_NE2A1_9", + "CMT_TOP_NE2A1_9" + ], + [ + "CMT_FIFO_WW2A0_3", + "CMT_TOP_WW2A0_3" + ], + [ + "CMT_FIFO_L_IMUX9_5", + "CMT_TOP_IMUX9_5" + ], + [ + "CMT_FIFO_NE4C1_8", + "CMT_TOP_NE4C1_8" + ], + [ + "CMT_FIFO_WL1END0_2", + "CMT_TOP_WL1END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_3", + "CMT_TOP_LOGIC_OUTS_L_B4_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_2", + "CMT_TOP_LOGIC_OUTS_L_B8_2" + ], + [ + "CMT_FIFO_L_FAN4_6", + "CMT_TOP_FAN4_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_3", + "CMT_TOP_LOGIC_OUTS_L_B23_3" + ], + [ + "CMT_FIFO_L_IMUX16_9", + "CMT_TOP_IMUX16_9" + ], + [ + "CMT_FIFO_SE2A1_9", + "CMT_TOP_SE2A1_9" + ], + [ + "CMT_FIFO_NW4END1_7", + "CMT_TOP_NW4END1_7" + ], + [ + "CMT_FIFO_SE2A2_10", + "CMT_TOP_SE2A2_10" + ], + [ + "CMT_FIFO_L_IMUX25_10", + "CMT_TOP_IMUX25_10" + ], + [ + "CMT_FIFO_L_BYP4_9", + "CMT_TOP_BYP4_9" + ], + [ + "CMT_FIFO_EE2BEG2_11", + "CMT_TOP_EE2BEG2_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_6", + "CMT_TOP_LOGIC_OUTS_L_B6_6" + ], + [ + "CMT_FIFO_WW2END1_1", + "CMT_TOP_WW2END1_1" + ], + [ + "CMT_FIFO_WW2END3_6", + "CMT_TOP_WW2END3_6" + ], + [ + "CMT_FIFO_L_CLK1_7", + "CMT_TOP_CLK1_7" + ], + [ + "CMT_FIFO_SE4BEG3_10", + "CMT_TOP_SE4BEG3_10" + ], + [ + "CMT_FIFO_SW4A1_1", + "CMT_TOP_SW4A1_1" + ], + [ + "CMT_FIFO_LH8_3", + "CMT_TOP_LH8_3" + ], + [ + "CMT_FIFO_WW4A1_9", + "CMT_TOP_WW4A1_9" + ], + [ + "CMT_FIFO_L_IMUX45_1", + "CMT_TOP_IMUX45_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_2", + "CMT_TOP_LOGIC_OUTS_L_B18_2" + ], + [ + "CMT_FIFO_L_IMUX28_10", + "CMT_TOP_IMUX28_10" + ], + [ + "CMT_FIFO_SE4C0_0", + "CMT_TOP_SE4C0_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "CMT_TOP_OCLK_2" + ], + [ + "CMT_FIFO_L_IMUX21_11", + "CMT_TOP_IMUX21_11" + ], + [ + "CMT_FIFO_NE4BEG1_0", + "CMT_TOP_NE4BEG1_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_7", + "CMT_TOP_LOGIC_OUTS_L_B15_7" + ], + [ + "CMT_FIFO_SW4END1_11", + "CMT_TOP_SW4END1_11" + ], + [ + "CMT_FIFO_NE4C2_7", + "CMT_TOP_NE4C2_7" + ], + [ + "CMT_FIFO_SE4C2_4", + "CMT_TOP_SE4C2_4" + ], + [ + "CMT_FIFO_SW4A3_4", + "CMT_TOP_SW4A3_4" + ], + [ + "CMT_FIFO_ER1BEG1_0", + "CMT_TOP_ER1BEG1_0" + ], + [ + "CMT_FIFO_NW4A2_3", + "CMT_TOP_NW4A2_3" + ], + [ + "CMT_FIFO_WW4A1_0", + "CMT_TOP_WW4A1_0" + ], + [ + "CMT_FIFO_EL1BEG1_9", + "CMT_TOP_EL1BEG1_9" + ], + [ + "CMT_FIFO_L_IMUX34_11", + "CMT_TOP_IMUX34_11" + ], + [ + "CMT_FIFO_SW2A0_0", + "CMT_TOP_SW2A0_0" + ], + [ + "CMT_FIFO_SE4BEG1_5", + "CMT_TOP_SE4BEG1_5" + ], + [ + "CMT_FIFO_NW4END0_6", + "CMT_TOP_NW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX23_2", + "CMT_TOP_IMUX23_2" + ], + [ + "CMT_FIFO_L_IMUX1_11", + "CMT_TOP_IMUX1_11" + ], + [ + "CMT_FIFO_WW4END1_1", + "CMT_TOP_WW4END1_1" + ], + [ + "CMT_FIFO_EE2BEG3_7", + "CMT_TOP_EE2BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX33_5", + "CMT_TOP_IMUX33_5" + ], + [ + "CMT_FIFO_WW4B3_3", + "CMT_TOP_WW4B3_3" + ], + [ + "CMT_FIFO_L_FAN5_0", + "CMT_TOP_FAN5_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_6", + "CMT_TOP_LOGIC_OUTS_L_B17_6" + ], + [ + "CMT_FIFO_WW4END2_8", + "CMT_TOP_WW4END2_8" + ], + [ + "CMT_FIFO_L_BYP0_1", + "CMT_TOP_BYP0_1" + ], + [ + "CMT_FIFO_WL1END3_7", + "CMT_TOP_WL1END3_7" + ], + [ + "CMT_FIFO_L_IMUX39_9", + "CMT_TOP_IMUX39_9" + ], + [ + "CMT_FIFO_WR1END3_6", + "CMT_TOP_WR1END3_6" + ], + [ + "CMT_FIFO_SE4C3_1", + "CMT_TOP_SE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX33_7", + "CMT_TOP_IMUX33_7" + ], + [ + "CMT_FIFO_L_BYP4_11", + "CMT_TOP_BYP4_11" + ], + [ + "CMT_FIFO_L_IMUX32_6", + "CMT_TOP_IMUX32_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "CMT_TOP_OCLKDIV_2" + ], + [ + "CMT_FIFO_L_IMUX33_11", + "CMT_TOP_IMUX33_11" + ], + [ + "CMT_FIFO_SE2A3_4", + "CMT_TOP_SE2A3_4" + ], + [ + "CMT_FIFO_L_IMUX44_2", + "CMT_TOP_IMUX44_2" + ], + [ + "CMT_FIFO_NE4C3_5", + "CMT_TOP_NE4C3_5" + ], + [ + "CMT_FIFO_EE4B1_4", + "CMT_TOP_EE4B1_4" + ], + [ + "CMT_FIFO_SW2A2_11", + "CMT_TOP_SW2A2_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_0", + "CMT_TOP_LOGIC_OUTS_L_B22_0" + ], + [ + "CMT_FIFO_WW4C3_9", + "CMT_TOP_WW4C3_9" + ], + [ + "CMT_FIFO_EE2BEG0_11", + "CMT_TOP_EE2BEG0_11" + ], + [ + "CMT_FIFO_ER1BEG0_0", + "CMT_TOP_ER1BEG0_0" + ], + [ + "CMT_FIFO_NW4END2_8", + "CMT_TOP_NW4END2_8" + ], + [ + "CMT_FIFO_L_IMUX25_3", + "CMT_TOP_IMUX25_3" + ], + [ + "CMT_FIFO_NW4A0_2", + "CMT_TOP_NW4A0_2" + ], + [ + "CMT_FIFO_SE4C1_0", + "CMT_TOP_SE4C1_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_8", + "CMT_TOP_LOGIC_OUTS_L_B1_8" + ], + [ + "CMT_FIFO_WW4A1_7", + "CMT_TOP_WW4A1_7" + ], + [ + "CMT_FIFO_L_IMUX21_1", + "CMT_TOP_IMUX21_1" + ], + [ + "CMT_FIFO_LH11_2", + "CMT_TOP_LH11_2" + ], + [ + "CMT_FIFO_SE2A1_8", + "CMT_TOP_SE2A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_4", + "CMT_TOP_LOGIC_OUTS_L_B13_4" + ], + [ + "CMT_FIFO_WW4END3_1", + "CMT_TOP_WW4END3_1" + ], + [ + "CMT_FIFO_L_BYP1_6", + "CMT_TOP_BYP1_6" + ], + [ + "CMT_FIFO_LH7_7", + "CMT_TOP_LH7_7" + ], + [ + "CMT_FIFO_EE4BEG0_0", + "CMT_TOP_EE4BEG0_0" + ], + [ + "CMT_FIFO_NE4BEG2_11", + "CMT_TOP_NE4BEG2_11" + ], + [ + "CMT_FIFO_WW4A2_9", + "CMT_TOP_WW4A2_9" + ], + [ + "CMT_FIFO_L_IMUX29_6", + "CMT_TOP_IMUX29_6" + ], + [ + "CMT_FIFO_WW2A2_2", + "CMT_TOP_WW2A2_2" + ], + [ + "CMT_FIFO_L_BYP0_2", + "CMT_TOP_BYP0_2" + ], + [ + "CMT_FIFO_NE4BEG1_6", + "CMT_TOP_NE4BEG1_6" + ], + [ + "CMT_FIFO_NW2A1_4", + "CMT_TOP_NW2A1_4" + ], + [ + "CMT_FIFO_L_IMUX2_11", + "CMT_TOP_IMUX2_11" + ], + [ + "CMT_FIFO_WW4A3_9", + "CMT_TOP_WW4A3_9" + ], + [ + "CMT_FIFO_SW2A0_7", + "CMT_TOP_SW2A0_7" + ], + [ + "CMT_FIFO_L_FAN0_8", + "CMT_TOP_FAN0_8" + ], + [ + "CMT_FIFO_NE4BEG3_5", + "CMT_TOP_NE4BEG3_5" + ], + [ + "CMT_FIFO_LH5_1", + "CMT_TOP_LH5_1" + ], + [ + "CMT_FIFO_SE4BEG0_4", + "CMT_TOP_SE4BEG0_4" + ], + [ + "CMT_FIFO_WW4END1_3", + "CMT_TOP_WW4END1_3" + ], + [ + "CMT_FIFO_NE2A1_8", + "CMT_TOP_NE2A1_8" + ], + [ + "CMT_FIFO_L_IMUX8_2", + "CMT_TOP_IMUX8_2" + ], + [ + "CMT_FIFO_SE2A0_8", + "CMT_TOP_SE2A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_6", + "CMT_TOP_LOGIC_OUTS_L_B8_6" + ], + [ + "CMT_FIFO_L_BYP3_0", + "CMT_TOP_BYP3_0" + ], + [ + "CMT_FIFO_EE2BEG0_6", + "CMT_TOP_EE2BEG0_6" + ], + [ + "CMT_FIFO_EL1BEG2_9", + "CMT_TOP_EL1BEG2_9" + ], + [ + "CMT_FIFO_EE4B2_9", + "CMT_TOP_EE4B2_9" + ], + [ + "CMT_FIFO_SE4C3_4", + "CMT_TOP_SE4C3_4" + ], + [ + "CMT_FIFO_L_IMUX30_1", + "CMT_TOP_IMUX30_1" + ], + [ + "CMT_FIFO_L_BYP4_0", + "CMT_TOP_BYP4_0" + ], + [ + "CMT_FIFO_L_IMUX34_10", + "CMT_TOP_IMUX34_10" + ], + [ + "CMT_FIFO_SW2A0_6", + "CMT_TOP_SW2A0_6" + ], + [ + "CMT_FIFO_NW4A3_4", + "CMT_TOP_NW4A3_4" + ], + [ + "CMT_FIFO_L_IMUX17_3", + "CMT_TOP_IMUX17_3" + ], + [ + "CMT_FIFO_WW2END0_5", + "CMT_TOP_WW2END0_5" + ], + [ + "CMT_FIFO_EE2BEG2_0", + "CMT_TOP_EE2BEG2_0" + ], + [ + "CMT_FIFO_WR1END3_10", + "CMT_TOP_WR1END3_10" + ], + [ + "CMT_FIFO_L_IMUX41_1", + "CMT_TOP_IMUX41_1" + ], + [ + "CMT_FIFO_EE4A0_10", + "CMT_TOP_EE4A0_10" + ], + [ + "CMT_FIFO_EE4B1_9", + "CMT_TOP_EE4B1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_3", + "CMT_TOP_LOGIC_OUTS_L_B11_3" + ], + [ + "CMT_FIFO_NW2A0_0", + "CMT_TOP_NW2A0_0" + ], + [ + "CMT_FIFO_L_IMUX26_11", + "CMT_TOP_IMUX26_11" + ], + [ + "CMT_FIFO_L_IMUX2_10", + "CMT_TOP_IMUX2_10" + ], + [ + "CMT_FIFO_L_IMUX5_4", + "CMT_TOP_IMUX5_4" + ], + [ + "CMT_FIFO_SW4END3_10", + "CMT_TOP_SW4END3_10" + ], + [ + "CMT_FIFO_WW4C2_2", + "CMT_TOP_WW4C2_2" + ], + [ + "CMT_FIFO_SE4BEG1_7", + "CMT_TOP_SE4BEG1_7" + ], + [ + "CMT_FIFO_SW4A1_5", + "CMT_TOP_SW4A1_5" + ], + [ + "CMT_FIFO_SW2A0_11", + "CMT_TOP_SW2A0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_3", + "CMT_TOP_LOGIC_OUTS_L_B13_3" + ], + [ + "CMT_FIFO_L_IMUX29_5", + "CMT_TOP_IMUX29_5" + ], + [ + "CMT_FIFO_L_FAN6_3", + "CMT_TOP_FAN6_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_4", + "CMT_TOP_LOGIC_OUTS_L_B23_4" + ], + [ + "CMT_FIFO_L_IMUX25_5", + "CMT_TOP_IMUX25_5" + ], + [ + "CMT_FIFO_SE4C0_2", + "CMT_TOP_SE4C0_2" + ], + [ + "CMT_FIFO_WW2A2_10", + "CMT_TOP_WW2A2_10" + ], + [ + "CMT_FIFO_L_CLK1_1", + "CMT_TOP_CLK1_1" + ], + [ + "CMT_FIFO_L_IMUX0_0", + "CMT_TOP_IMUX0_0" + ], + [ + "CMT_FIFO_L_IMUX29_11", + "CMT_TOP_IMUX29_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "CMT_TOP_ICLKDIV_7" + ], + [ + "CMT_FIFO_L_FAN6_4", + "CMT_TOP_FAN6_4" + ], + [ + "CMT_FIFO_NE4BEG1_10", + "CMT_TOP_NE4BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX0_8", + "CMT_TOP_IMUX0_8" + ], + [ + "CMT_FIFO_L_IMUX34_1", + "CMT_TOP_IMUX34_1" + ], + [ + "CMT_FIFO_EL1BEG2_3", + "CMT_TOP_EL1BEG2_3" + ], + [ + "CMT_FIFO_SW2A0_9", + "CMT_TOP_SW2A0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_1", + "CMT_TOP_LOGIC_OUTS_L_B0_1" + ], + [ + "CMT_FIFO_WW4A2_11", + "CMT_TOP_WW4A2_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "CMT_TOP_OCLKDIV_0" + ], + [ + "CMT_FIFO_NW4A1_10", + "CMT_TOP_NW4A1_10" + ], + [ + "CMT_FIFO_LH11_7", + "CMT_TOP_LH11_7" + ], + [ + "CMT_FIFO_NE4C3_11", + "CMT_TOP_NE4C3_11" + ], + [ + "CMT_FIFO_L_IMUX23_0", + "CMT_TOP_IMUX23_0" + ], + [ + "CMT_FIFO_NW4A3_6", + "CMT_TOP_NW4A3_6" + ], + [ + "CMT_FIFO_SW2A2_9", + "CMT_TOP_SW2A2_9" + ], + [ + "CMT_FIFO_L_FAN3_2", + "CMT_TOP_FAN3_2" + ], + [ + "CMT_FIFO_WL1END1_3", + "CMT_TOP_WL1END1_3" + ], + [ + "CMT_FIFO_L_IMUX12_0", + "CMT_TOP_IMUX12_0" + ], + [ + "CMT_FIFO_WW4C0_2", + "CMT_TOP_WW4C0_2" + ], + [ + "CMT_FIFO_NW4A2_7", + "CMT_TOP_NW4A2_7" + ], + [ + "CMT_FIFO_ER1BEG1_3", + "CMT_TOP_ER1BEG1_3" + ], + [ + "CMT_FIFO_WW4C1_4", + "CMT_TOP_WW4C1_4" + ], + [ + "CMT_FIFO_WW4END3_3", + "CMT_TOP_WW4END3_3" + ], + [ + "CMT_FIFO_EE4A1_5", + "CMT_TOP_EE4A1_5" + ], + [ + "CMT_FIFO_SE2A2_7", + "CMT_TOP_SE2A2_7" + ], + [ + "CMT_FIFO_NW2A1_0", + "CMT_TOP_NW2A1_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "CMT_TOP_OCLK1X_90_7" + ], + [ + "CMT_FIFO_L_CTRL1_5", + "CMT_TOP_CTRL1_5" + ], + [ + "FIFO_DQS_IOTOPHASER_1", + "CMT_PLL_DQS_TO_PHASER_D" + ], + [ + "CMT_FIFO_WW4B0_11", + "CMT_TOP_WW4B0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_6", + "CMT_TOP_LOGIC_OUTS_L_B7_6" + ], + [ + "CMT_FIFO_L_IMUX34_3", + "CMT_TOP_IMUX34_3" + ], + [ + "CMT_FIFO_WW2A1_3", + "CMT_TOP_WW2A1_3" + ], + [ + "CMT_FIFO_EL1BEG3_7", + "CMT_TOP_EL1BEG3_7" + ], + [ + "CMT_FIFO_EE2BEG2_4", + "CMT_TOP_EE2BEG2_4" + ], + [ + "CMT_FIFO_LH10_11", + "CMT_TOP_LH10_11" + ], + [ + "CMT_FIFO_SW2A1_0", + "CMT_TOP_SW2A1_0" + ], + [ + "CMT_FIFO_L_IMUX15_9", + "CMT_TOP_IMUX15_9" + ], + [ + "CMT_FIFO_L_IMUX1_4", + "CMT_TOP_IMUX1_4" + ], + [ + "CMT_FIFO_L_IMUX22_7", + "CMT_TOP_IMUX22_7" + ], + [ + "CMT_FIFO_EE4A0_11", + "CMT_TOP_EE4A0_11" + ], + [ + "CMT_FIFO_WL1END2_3", + "CMT_TOP_WL1END2_3" + ], + [ + "CMT_FIFO_EE2BEG3_1", + "CMT_TOP_EE2BEG3_1" + ], + [ + "CMT_FIFO_EE2A2_1", + "CMT_TOP_EE2A2_1" + ], + [ + "CMT_FIFO_NW4END2_1", + "CMT_TOP_NW4END2_1" + ], + [ + "CMT_FIFO_L_IMUX16_7", + "CMT_TOP_IMUX16_7" + ], + [ + "CMT_FIFO_SW4A2_2", + "CMT_TOP_SW4A2_2" + ], + [ + "CMT_FIFO_LH11_9", + "CMT_TOP_LH11_9" + ], + [ + "CMT_FIFO_ER1BEG2_9", + "CMT_TOP_ER1BEG2_9" + ], + [ + "CMT_FIFO_LH6_2", + "CMT_TOP_LH6_2" + ], + [ + "CMT_FIFO_SE4C1_5", + "CMT_TOP_SE4C1_5" + ], + [ + "CMT_FIFO_L_IMUX2_2", + "CMT_TOP_IMUX2_2" + ], + [ + "CMT_FIFO_NE4C3_8", + "CMT_TOP_NE4C3_8" + ], + [ + "CMT_FIFO_WR1END0_11", + "CMT_TOP_WR1END0_11" + ], + [ + "CMT_FIFO_L_IMUX25_2", + "CMT_TOP_IMUX25_2" + ], + [ + "CMT_FIFO_SW4END0_2", + "CMT_TOP_SW4END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_7", + "CMT_TOP_LOGIC_OUTS_L_B5_7" + ], + [ + "CMT_FIFO_L_IMUX32_1", + "CMT_TOP_IMUX32_1" + ], + [ + "CMT_FIFO_L_IMUX41_5", + "CMT_TOP_IMUX41_5" + ], + [ + "CMT_FIFO_EE4C1_0", + "CMT_TOP_EE4C1_0" + ], + [ + "CMT_FIFO_EE4C0_6", + "CMT_TOP_EE4C0_6" + ], + [ + "CMT_FIFO_WW2A3_1", + "CMT_TOP_WW2A3_1" + ], + [ + "CMT_FIFO_NE4C2_1", + "CMT_TOP_NE4C2_1" + ], + [ + "CMT_FIFO_NW2A3_0", + "CMT_TOP_NW2A3_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "CMT_TOP_OCLK_7" + ], + [ + "CMT_FIFO_L_IMUX15_6", + "CMT_TOP_IMUX15_6" + ], + [ + "CMT_FIFO_EE2A0_3", + "CMT_TOP_EE2A0_3" + ], + [ + "CMT_FIFO_EE4BEG1_11", + "CMT_TOP_EE4BEG1_11" + ], + [ + "CMT_FIFO_LH7_5", + "CMT_TOP_LH7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_7", + "CMT_TOP_LOGIC_OUTS_L_B20_7" + ], + [ + "CMT_FIFO_SE4BEG0_8", + "CMT_TOP_SE4BEG0_8" + ], + [ + "CMT_FIFO_EE4C1_4", + "CMT_TOP_EE4C1_4" + ], + [ + "CMT_FIFO_NW2A2_1", + "CMT_TOP_NW2A2_1" + ], + [ + "CMT_FIFO_ER1BEG3_9", + "CMT_TOP_ER1BEG3_9" + ], + [ + "CMT_FIFO_EE4A3_0", + "CMT_TOP_EE4A3_0" + ], + [ + "CMT_FIFO_L_IMUX3_9", + "CMT_TOP_IMUX3_9" + ], + [ + "CMT_FIFO_EE4C0_7", + "CMT_TOP_EE4C0_7" + ], + [ + "CMT_FIFO_L_BYP1_1", + "CMT_TOP_BYP1_1" + ], + [ + "CMT_FIFO_SE4BEG3_0", + "CMT_TOP_SE4BEG3_0" + ], + [ + "CMT_FIFO_L_IMUX31_2", + "CMT_TOP_IMUX31_2" + ], + [ + "CMT_FIFO_WW2END3_5", + "CMT_TOP_WW2END3_5" + ], + [ + "CMT_FIFO_L_IMUX1_10", + "CMT_TOP_IMUX1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_1", + "CMT_TOP_LOGIC_OUTS_L_B20_1" + ], + [ + "CMT_FIFO_EE4BEG2_3", + "CMT_TOP_EE4BEG2_3" + ], + [ + "CMT_FIFO_L_FAN1_5", + "CMT_TOP_FAN1_5" + ], + [ + "CMT_FIFO_L_IMUX34_0", + "CMT_TOP_IMUX34_0" + ], + [ + "CMT_FIFO_L_IMUX23_3", + "CMT_TOP_IMUX23_3" + ], + [ + "CMT_FIFO_L_IMUX27_8", + "CMT_TOP_IMUX27_8" + ], + [ + "CMT_FIFO_WW4C1_1", + "CMT_TOP_WW4C1_1" + ], + [ + "CMT_FIFO_NE4BEG1_5", + "CMT_TOP_NE4BEG1_5" + ], + [ + "CMT_FIFO_NE4BEG2_4", + "CMT_TOP_NE4BEG2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_5", + "CMT_TOP_LOGIC_OUTS_L_B5_5" + ], + [ + "CMT_FIFO_WW4A0_1", + "CMT_TOP_WW4A0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_1", + "CMT_TOP_LOGIC_OUTS_L_B4_1" + ], + [ + "CMT_FIFO_WW2A3_5", + "CMT_TOP_WW2A3_5" + ], + [ + "CMT_FIFO_WW4A0_6", + "CMT_TOP_WW4A0_6" + ], + [ + "CMT_FIFO_WW4C0_6", + "CMT_TOP_WW4C0_6" + ], + [ + "CMT_FIFO_SW4END1_4", + "CMT_TOP_SW4END1_4" + ], + [ + "CMT_FIFO_EE4A1_1", + "CMT_TOP_EE4A1_1" + ], + [ + "CMT_FIFO_LH4_7", + "CMT_TOP_LH4_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_7", + "CMT_TOP_LOGIC_OUTS_L_B7_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_9", + "CMT_TOP_LOGIC_OUTS_L_B23_9" + ], + [ + "CMT_FIFO_SE4C2_3", + "CMT_TOP_SE4C2_3" + ], + [ + "CMT_FIFO_NW4END1_1", + "CMT_TOP_NW4END1_1" + ], + [ + "CMT_FIFO_WW2END3_8", + "CMT_TOP_WW2END3_8" + ], + [ + "CMT_FIFO_NW2A2_4", + "CMT_TOP_NW2A2_4" + ], + [ + "CMT_FIFO_EE4BEG2_8", + "CMT_TOP_EE4BEG2_8" + ], + [ + "CMT_FIFO_NW2A3_5", + "CMT_TOP_NW2A3_5" + ], + [ + "CMT_FIFO_L_IMUX11_3", + "CMT_TOP_IMUX11_3" + ], + [ + "CMT_FIFO_WW4A0_0", + "CMT_TOP_WW4A0_0" + ], + [ + "CMT_FIFO_WW4END0_4", + "CMT_TOP_WW4END0_4" + ], + [ + "CMT_FIFO_L_IMUX39_4", + "CMT_TOP_IMUX39_4" + ], + [ + "CMT_FIFO_SE4C3_10", + "CMT_TOP_SE4C3_10" + ], + [ + "CMT_FIFO_L_IMUX22_8", + "CMT_TOP_IMUX22_8" + ], + [ + "CMT_FIFO_L_IMUX42_11", + "CMT_TOP_IMUX42_11" + ], + [ + "CMT_FIFO_WW2END3_1", + "CMT_TOP_WW2END3_1" + ], + [ + "CMT_FIFO_L_IMUX2_4", + "CMT_TOP_IMUX2_4" + ], + [ + "CMT_FIFO_L_BYP6_3", + "CMT_TOP_BYP6_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_4", + "CMT_TOP_LOGIC_OUTS_L_B7_4" + ], + [ + "CMT_FIFO_WW4A3_4", + "CMT_TOP_WW4A3_4" + ], + [ + "CMT_FIFO_L_IMUX7_3", + "CMT_TOP_IMUX7_3" + ], + [ + "CMT_FIFO_SW2A1_9", + "CMT_TOP_SW2A1_9" + ], + [ + "CMT_FIFO_L_IMUX18_6", + "CMT_TOP_IMUX18_6" + ], + [ + "CMT_FIFO_L_IMUX12_2", + "CMT_TOP_IMUX12_2" + ], + [ + "CMT_FIFO_LH12_2", + "CMT_TOP_LH12_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_3", + "CMT_TOP_LOGIC_OUTS_L_B8_3" + ], + [ + "CMT_FIFO_WW2END0_4", + "CMT_TOP_WW2END0_4" + ], + [ + "CMT_FIFO_L_IMUX22_3", + "CMT_TOP_IMUX22_3" + ], + [ + "CMT_FIFO_NE4BEG3_10", + "CMT_TOP_NE4BEG3_10" + ], + [ + "CMT_FIFO_LH11_5", + "CMT_TOP_LH11_5" + ], + [ + "CMT_FIFO_L_IMUX10_3", + "CMT_TOP_IMUX10_3" + ], + [ + "CMT_FIFO_LH3_10", + "CMT_TOP_LH3_10" + ], + [ + "CMT_FIFO_LH9_8", + "CMT_TOP_LH9_8" + ], + [ + "CMT_FIFO_NW4END2_11", + "CMT_TOP_NW4END2_11" + ], + [ + "CMT_FIFO_L_IMUX15_3", + "CMT_TOP_IMUX15_3" + ], + [ + "CMT_FIFO_L_IMUX47_11", + "CMT_TOP_IMUX47_11" + ], + [ + "CMT_FIFO_SE2A2_11", + "CMT_TOP_SE2A2_11" + ], + [ + "CMT_FIFO_EE4B1_5", + "CMT_TOP_EE4B1_5" + ], + [ + "CMT_FIFO_SE4BEG1_6", + "CMT_TOP_SE4BEG1_6" + ], + [ + "CMT_FIFO_LH6_6", + "CMT_TOP_LH6_6" + ], + [ + "CMT_FIFO_NE2A3_0", + "CMT_TOP_NE2A3_0" + ], + [ + "CMT_FIFO_L_BYP0_4", + "CMT_TOP_BYP0_4" + ], + [ + "CMT_FIFO_WW2END2_5", + "CMT_TOP_WW2END2_5" + ], + [ + "CMT_FIFO_EE4B3_6", + "CMT_TOP_EE4B3_6" + ], + [ + "CMT_FIFO_L_IMUX39_3", + "CMT_TOP_IMUX39_3" + ], + [ + "CMT_FIFO_L_FAN7_5", + "CMT_TOP_FAN7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_6", + "CMT_TOP_LOGIC_OUTS_L_B2_6" + ], + [ + "CMT_FIFO_WW2END0_2", + "CMT_TOP_WW2END0_2" + ], + [ + "CMT_FIFO_SE4C3_3", + "CMT_TOP_SE4C3_3" + ], + [ + "CMT_FIFO_NE4C3_1", + "CMT_TOP_NE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX40_3", + "CMT_TOP_IMUX40_3" + ], + [ + "CMT_FIFO_WW4A3_0", + "CMT_TOP_WW4A3_0" + ], + [ + "CMT_FIFO_L_IMUX37_10", + "CMT_TOP_IMUX37_10" + ], + [ + "CMT_FIFO_L_IMUX21_4", + "CMT_TOP_IMUX21_4" + ], + [ + "CMT_FIFO_SE4BEG0_11", + "CMT_TOP_SE4BEG0_11" + ], + [ + "CMT_FIFO_WW4B2_10", + "CMT_TOP_WW4B2_10" + ], + [ + "CMT_FIFO_EE4B1_11", + "CMT_TOP_EE4B1_11" + ], + [ + "CMT_FIFO_WW2A1_6", + "CMT_TOP_WW2A1_6" + ], + [ + "CMT_FIFO_NE2A0_10", + "CMT_TOP_NE2A0_10" + ], + [ + "CMT_FIFO_EE4B2_7", + "CMT_TOP_EE4B2_7" + ], + [ + "CMT_FIFO_SE4C0_10", + "CMT_TOP_SE4C0_10" + ], + [ + "CMT_FIFO_SE2A0_2", + "CMT_TOP_SE2A0_2" + ], + [ + "CMT_FIFO_NE4C1_4", + "CMT_TOP_NE4C1_4" + ], + [ + "CMT_FIFO_L_IMUX4_5", + "CMT_TOP_IMUX4_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_10" + ], + [ + "CMT_FIFO_L_IMUX26_5", + "CMT_TOP_IMUX26_5" + ], + [ + "CMT_FIFO_EE4A3_8", + "CMT_TOP_EE4A3_8" + ], + [ + "CMT_FIFO_L_IMUX38_7", + "CMT_TOP_IMUX38_7" + ], + [ + "CMT_FIFO_EL1BEG0_1", + "CMT_TOP_EL1BEG0_1" + ], + [ + "CMT_FIFO_L_IMUX33_10", + "CMT_TOP_IMUX33_10" + ], + [ + "CMT_FIFO_LH4_11", + "CMT_TOP_LH4_11" + ], + [ + "CMT_FIFO_L_IMUX37_6", + "CMT_TOP_IMUX37_6" + ], + [ + "CMT_FIFO_L_IMUX15_10", + "CMT_TOP_IMUX15_10" + ], + [ + "CMT_FIFO_EL1BEG1_8", + "CMT_TOP_EL1BEG1_8" + ], + [ + "CMT_FIFO_NE2A2_5", + "CMT_TOP_NE2A2_5" + ], + [ + "CMT_FIFO_SW2A2_4", + "CMT_TOP_SW2A2_4" + ], + [ + "CMT_FIFO_SW4END3_2", + "CMT_TOP_SW4END3_2" + ], + [ + "CMT_FIFO_L_IMUX31_9", + "CMT_TOP_IMUX31_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "CMT_TOP_OCLKDIV_7" + ], + [ + "CMT_FIFO_L_IMUX23_8", + "CMT_TOP_IMUX23_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_7", + "CMT_TOP_LOGIC_OUTS_L_B16_7" + ], + [ + "CMT_FIFO_EE4A2_3", + "CMT_TOP_EE4A2_3" + ], + [ + "CMT_FIFO_L_IMUX46_10", + "CMT_TOP_IMUX46_10" + ], + [ + "CMT_FIFO_MONITOR_N_4", + "CMT_TOP_MONITOR_N_4" + ], + [ + "CMT_FIFO_WW4A3_10", + "CMT_TOP_WW4A3_10" + ], + [ + "CMT_FIFO_LH3_11", + "CMT_TOP_LH3_11" + ], + [ + "CMT_FIFO_SW4A2_11", + "CMT_TOP_SW4A2_11" + ], + [ + "CMT_FIFO_L_IMUX33_3", + "CMT_TOP_IMUX33_3" + ], + [ + "CMT_FIFO_WR1END3_3", + "CMT_TOP_WR1END3_3" + ], + [ + "CMT_FIFO_WR1END2_4", + "CMT_TOP_WR1END2_4" + ], + [ + "CMT_FIFO_WW4B2_5", + "CMT_TOP_WW4B2_5" + ], + [ + "CMT_FIFO_L_FAN7_2", + "CMT_TOP_FAN7_2" + ], + [ + "CMT_FIFO_NW2A1_1", + "CMT_TOP_NW2A1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_1", + "CMT_TOP_LOGIC_OUTS_L_B12_1" + ], + [ + "CMT_FIFO_NW4A2_10", + "CMT_TOP_NW4A2_10" + ], + [ + "CMT_FIFO_WL1END2_5", + "CMT_TOP_WL1END2_5" + ], + [ + "CMT_FIFO_L_CLK0_7", + "CMT_TOP_CLK0_7" + ], + [ + "CMT_FIFO_L_IMUX28_2", + "CMT_TOP_IMUX28_2" + ], + [ + "CMT_FIFO_EL1BEG2_11", + "CMT_TOP_EL1BEG2_11" + ], + [ + "CMT_FIFO_WW4END3_10", + "CMT_TOP_WW4END3_10" + ], + [ + "CMT_FIFO_EE2BEG3_10", + "CMT_TOP_EE2BEG3_10" + ], + [ + "CMT_FIFO_ER1BEG2_4", + "CMT_TOP_ER1BEG2_4" + ], + [ + "CMT_FIFO_WW4END1_2", + "CMT_TOP_WW4END1_2" + ], + [ + "CMT_FIFO_L_FAN1_3", + "CMT_TOP_FAN1_3" + ], + [ + "CMT_FIFO_L_BYP6_9", + "CMT_TOP_BYP6_9" + ], + [ + "CMT_FIFO_L_BYP7_9", + "CMT_TOP_BYP7_9" + ], + [ + "CMT_FIFO_SW4A0_6", + "CMT_TOP_SW4A0_6" + ], + [ + "CMT_FIFO_L_FAN0_4", + "CMT_TOP_FAN0_4" + ], + [ + "CMT_FIFO_SW4A1_7", + "CMT_TOP_SW4A1_7" + ], + [ + "CMT_FIFO_L_IMUX11_2", + "CMT_TOP_IMUX11_2" + ], + [ + "CMT_FIFO_EE2A1_0", + "CMT_TOP_EE2A1_0" + ], + [ + "CMT_FIFO_LH12_9", + "CMT_TOP_LH12_9" + ], + [ + "CMT_FIFO_LH10_10", + "CMT_TOP_LH10_10" + ], + [ + "CMT_FIFO_L_IMUX39_7", + "CMT_TOP_IMUX39_7" + ], + [ + "CMT_FIFO_L_IMUX9_9", + "CMT_TOP_IMUX9_9" + ], + [ + "CMT_FIFO_NW2A0_10", + "CMT_TOP_NW2A0_10" + ], + [ + "CMT_FIFO_WW2A1_2", + "CMT_TOP_WW2A1_2" + ], + [ + "CMT_FIFO_SE4C1_8", + "CMT_TOP_SE4C1_8" + ], + [ + "CMT_FIFO_L_IMUX45_2", + "CMT_TOP_IMUX45_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_5", + "CMT_TOP_LOGIC_OUTS_L_B18_5" + ], + [ + "CMT_FIFO_SW4END2_7", + "CMT_TOP_SW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX31_8", + "CMT_TOP_IMUX31_8" + ], + [ + "CMT_FIFO_L_FAN2_11", + "CMT_TOP_FAN2_11" + ], + [ + "CMT_FIFO_NW4END1_8", + "CMT_TOP_NW4END1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_3" + ], + [ + "CMT_FIFO_L_IMUX0_3", + "CMT_TOP_IMUX0_3" + ], + [ + "CMT_FIFO_SE4BEG3_9", + "CMT_TOP_SE4BEG3_9" + ], + [ + "CMT_FIFO_ER1BEG0_1", + "CMT_TOP_ER1BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_9", + "CMT_TOP_LOGIC_OUTS_L_B2_9" + ], + [ + "CMT_FIFO_NE4C2_3", + "CMT_TOP_NE4C2_3" + ], + [ + "CMT_FIFO_LH1_6", + "CMT_TOP_LH1_6" + ], + [ + "CMT_FIFO_L_IMUX21_7", + "CMT_TOP_IMUX21_7" + ], + [ + "CMT_FIFO_SE2A2_8", + "CMT_TOP_SE2A2_8" + ], + [ + "CMT_FIFO_WW4A2_3", + "CMT_TOP_WW4A2_3" + ], + [ + "CMT_FIFO_SE4BEG1_0", + "CMT_TOP_SE4BEG1_0" + ], + [ + "CMT_FIFO_WR1END1_5", + "CMT_TOP_WR1END1_5" + ], + [ + "CMT_FIFO_WW2END2_7", + "CMT_TOP_WW2END2_7" + ], + [ + "CMT_FIFO_L_IMUX38_8", + "CMT_TOP_IMUX38_8" + ], + [ + "CMT_FIFO_LH5_9", + "CMT_TOP_LH5_9" + ], + [ + "CMT_FIFO_L_FAN4_10", + "CMT_TOP_FAN4_10" + ], + [ + "CMT_FIFO_NW4END1_5", + "CMT_TOP_NW4END1_5" + ], + [ + "CMT_FIFO_EE2A2_11", + "CMT_TOP_EE2A2_11" + ], + [ + "CMT_FIFO_SE2A0_9", + "CMT_TOP_SE2A0_9" + ], + [ + "CMT_FIFO_WW4B3_7", + "CMT_TOP_WW4B3_7" + ], + [ + "CMT_FIFO_L_FAN3_11", + "CMT_TOP_FAN3_11" + ], + [ + "CMT_FIFO_LH5_2", + "CMT_TOP_LH5_2" + ], + [ + "CMT_FIFO_SE4BEG1_1", + "CMT_TOP_SE4BEG1_1" + ], + [ + "CMT_FIFO_LH1_4", + "CMT_TOP_LH1_4" + ], + [ + "CMT_FIFO_EL1BEG0_4", + "CMT_TOP_EL1BEG0_4" + ], + [ + "CMT_FIFO_WW4B1_5", + "CMT_TOP_WW4B1_5" + ], + [ + "CMT_FIFO_LH7_2", + "CMT_TOP_LH7_2" + ], + [ + "CMT_FIFO_L_IMUX5_11", + "CMT_TOP_IMUX5_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_5", + "CMT_TOP_LOGIC_OUTS_L_B12_5" + ], + [ + "CMT_FIFO_EE4B0_4", + "CMT_TOP_EE4B0_4" + ], + [ + "CMT_FIFO_EE2BEG0_2", + "CMT_TOP_EE2BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX44_1", + "CMT_TOP_IMUX44_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_8", + "CMT_TOP_LOGIC_OUTS_L_B0_8" + ], + [ + "CMT_FIFO_L_IMUX13_10", + "CMT_TOP_IMUX13_10" + ], + [ + "CMT_FIFO_NE2A3_4", + "CMT_TOP_NE2A3_4" + ], + [ + "CMT_FIFO_ER1BEG2_5", + "CMT_TOP_ER1BEG2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_3" + ], + [ + "CMT_FIFO_EE4A3_6", + "CMT_TOP_EE4A3_6" + ], + [ + "CMT_FIFO_L_FAN1_2", + "CMT_TOP_FAN1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "CMT_TOP_OCLKDIV_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_8", + "CMT_TOP_LOGIC_OUTS_L_B10_8" + ], + [ + "CMT_FIFO_WW2END2_0", + "CMT_TOP_WW2END2_0" + ], + [ + "CMT_FIFO_NE4C2_8", + "CMT_TOP_NE4C2_8" + ], + [ + "CMT_FIFO_LH1_5", + "CMT_TOP_LH1_5" + ], + [ + "CMT_FIFO_NW2A3_9", + "CMT_TOP_NW2A3_9" + ], + [ + "CMT_FIFO_SE4BEG0_0", + "CMT_TOP_SE4BEG0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_9", + "CMT_TOP_LOGIC_OUTS_L_B9_9" + ], + [ + "CMT_FIFO_L_BYP0_5", + "CMT_TOP_BYP0_5" + ], + [ + "CMT_FIFO_L_IMUX27_3", + "CMT_TOP_IMUX27_3" + ], + [ + "CMT_FIFO_L_IMUX16_0", + "CMT_TOP_IMUX16_0" + ], + [ + "CMT_FIFO_NW4END2_2", + "CMT_TOP_NW4END2_2" + ], + [ + "CMT_FIFO_SW4A1_4", + "CMT_TOP_SW4A1_4" + ], + [ + "CMT_FIFO_WW4B3_11", + "CMT_TOP_WW4B3_11" + ], + [ + "CMT_FIFO_L_IMUX15_4", + "CMT_TOP_IMUX15_4" + ], + [ + "CMT_FIFO_WR1END2_3", + "CMT_TOP_WR1END2_3" + ], + [ + "CMT_FIFO_NW4END2_10", + "CMT_TOP_NW4END2_10" + ], + [ + "CMT_FIFO_WW4END3_9", + "CMT_TOP_WW4END3_9" + ], + [ + "CMT_FIFO_L_IMUX18_8", + "CMT_TOP_IMUX18_8" + ], + [ + "CMT_FIFO_L_FAN4_8", + "CMT_TOP_FAN4_8" + ], + [ + "CMT_FIFO_WW4A2_8", + "CMT_TOP_WW4A2_8" + ], + [ + "CMT_FIFO_L_IMUX35_4", + "CMT_TOP_IMUX35_4" + ], + [ + "CMT_FIFO_L_IMUX19_10", + "CMT_TOP_IMUX19_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_3" + ], + [ + "CMT_FIFO_L_IMUX22_0", + "CMT_TOP_IMUX22_0" + ], + [ + "CMT_FIFO_EE4B1_3", + "CMT_TOP_EE4B1_3" + ], + [ + "CMT_FIFO_NW2A1_10", + "CMT_TOP_NW2A1_10" + ], + [ + "CMT_FIFO_SE2A3_0", + "CMT_TOP_SE2A3_0" + ], + [ + "CMT_FIFO_SW4A0_9", + "CMT_TOP_SW4A0_9" + ], + [ + "CMT_FIFO_EE4A2_4", + "CMT_TOP_EE4A2_4" + ], + [ + "CMT_FIFO_EE2BEG0_7", + "CMT_TOP_EE2BEG0_7" + ], + [ + "CMT_FIFO_LH4_1", + "CMT_TOP_LH4_1" + ], + [ + "CMT_FIFO_L_IMUX8_6", + "CMT_TOP_IMUX8_6" + ], + [ + "CMT_FIFO_L_BYP1_3", + "CMT_TOP_BYP1_3" + ], + [ + "CMT_FIFO_L_FAN0_5", + "CMT_TOP_FAN0_5" + ], + [ + "CMT_FIFO_L_IMUX23_9", + "CMT_TOP_IMUX23_9" + ], + [ + "CMT_FIFO_EE4C2_6", + "CMT_TOP_EE4C2_6" + ], + [ + "CMT_FIFO_NW4END2_7", + "CMT_TOP_NW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX22_5", + "CMT_TOP_IMUX22_5" + ], + [ + "CMT_FIFO_EE2BEG0_9", + "CMT_TOP_EE2BEG0_9" + ], + [ + "CMT_FIFO_EE4B3_0", + "CMT_TOP_EE4B3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_5", + "CMT_TOP_LOGIC_OUTS_L_B7_5" + ], + [ + "CMT_FIFO_L_IMUX15_8", + "CMT_TOP_IMUX15_8" + ], + [ + "CMT_FIFO_NE4C1_3", + "CMT_TOP_NE4C1_3" + ], + [ + "CMT_FIFO_NE4BEG1_2", + "CMT_TOP_NE4BEG1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_7", + "CMT_TOP_LOGIC_OUTS_L_B19_7" + ], + [ + "CMT_FIFO_NW2A2_9", + "CMT_TOP_NW2A2_9" + ], + [ + "CMT_FIFO_SW2A1_7", + "CMT_TOP_SW2A1_7" + ], + [ + "CMT_FIFO_L_IMUX1_8", + "CMT_TOP_IMUX1_8" + ], + [ + "CMT_FIFO_L_IMUX30_5", + "CMT_TOP_IMUX30_5" + ], + [ + "CMT_FIFO_L_IMUX39_11", + "CMT_TOP_IMUX39_11" + ], + [ + "CMT_FIFO_SE4BEG2_6", + "CMT_TOP_SE4BEG2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_2", + "CMT_TOP_LOGIC_OUTS_L_B1_2" + ], + [ + "CMT_FIFO_LH7_9", + "CMT_TOP_LH7_9" + ], + [ + "CMT_FIFO_EE4C0_2", + "CMT_TOP_EE4C0_2" + ], + [ + "CMT_FIFO_L_IMUX46_1", + "CMT_TOP_IMUX46_1" + ], + [ + "CMT_FIFO_SW2A3_6", + "CMT_TOP_SW2A3_6" + ], + [ + "CMT_FIFO_NW4END3_4", + "CMT_TOP_NW4END3_4" + ], + [ + "CMT_FIFO_L_BYP2_6", + "CMT_TOP_BYP2_6" + ], + [ + "CMT_FIFO_L_CLK1_3", + "CMT_TOP_CLK1_3" + ], + [ + "CMT_FIFO_L_CLK0_8", + "CMT_TOP_CLK0_8" + ], + [ + "CMT_FIFO_SW2A1_8", + "CMT_TOP_SW2A1_8" + ], + [ + "CMT_FIFO_WW2END1_3", + "CMT_TOP_WW2END1_3" + ], + [ + "CMT_FIFO_EE4BEG1_10", + "CMT_TOP_EE4BEG1_10" + ], + [ + "CMT_FIFO_WW2END1_10", + "CMT_TOP_WW2END1_10" + ], + [ + "CMT_FIFO_SE2A0_7", + "CMT_TOP_SE2A0_7" + ], + [ + "CMT_FIFO_NE4C3_4", + "CMT_TOP_NE4C3_4" + ], + [ + "CMT_FIFO_SW4END1_6", + "CMT_TOP_SW4END1_6" + ], + [ + "CMT_FIFO_WW2END3_2", + "CMT_TOP_WW2END3_2" + ], + [ + "CMT_FIFO_EE2A1_1", + "CMT_TOP_EE2A1_1" + ], + [ + "CMT_FIFO_L_FAN1_1", + "CMT_TOP_FAN1_1" + ], + [ + "CMT_FIFO_LH9_10", + "CMT_TOP_LH9_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_7", + "CMT_TOP_LOGIC_OUTS_L_B13_7" + ], + [ + "CMT_FIFO_L_IMUX18_10", + "CMT_TOP_IMUX18_10" + ], + [ + "CMT_FIFO_L_IMUX10_9", + "CMT_TOP_IMUX10_9" + ], + [ + "CMT_FIFO_WW4B2_9", + "CMT_TOP_WW4B2_9" + ], + [ + "CMT_FIFO_L_BYP7_6", + "CMT_TOP_BYP7_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_8", + "CMT_TOP_LOGIC_OUTS_L_B22_8" + ], + [ + "CMT_FIFO_SE4BEG0_3", + "CMT_TOP_SE4BEG0_3" + ], + [ + "CMT_FIFO_LH7_1", + "CMT_TOP_LH7_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_8", + "CMT_TOP_LOGIC_OUTS_L_B4_8" + ], + [ + "CMT_FIFO_L_IMUX29_2", + "CMT_TOP_IMUX29_2" + ], + [ + "CMT_FIFO_NE4BEG1_4", + "CMT_TOP_NE4BEG1_4" + ], + [ + "CMT_FIFO_WW4END0_0", + "CMT_TOP_WW4END0_0" + ], + [ + "CMT_FIFO_NW4END1_6", + "CMT_TOP_NW4END1_6" + ], + [ + "CMT_FIFO_LH8_2", + "CMT_TOP_LH8_2" + ], + [ + "CMT_FIFO_NW4A1_2", + "CMT_TOP_NW4A1_2" + ], + [ + "CMT_FIFO_WL1END0_5", + "CMT_TOP_WL1END0_5" + ], + [ + "CMT_FIFO_SE2A2_1", + "CMT_TOP_SE2A2_1" + ], + [ + "CMT_FIFO_NE2A0_4", + "CMT_TOP_NE2A0_4" + ], + [ + "CMT_FIFO_L_IMUX18_11", + "CMT_TOP_IMUX18_11" + ], + [ + "CMT_FIFO_L_IMUX25_7", + "CMT_TOP_IMUX25_7" + ], + [ + "CMT_FIFO_NW4END0_4", + "CMT_TOP_NW4END0_4" + ], + [ + "CMT_FIFO_WL1END1_8", + "CMT_TOP_WL1END1_8" + ], + [ + "CMT_FIFO_EE4B2_5", + "CMT_TOP_EE4B2_5" + ], + [ + "CMT_FIFO_NE4BEG0_0", + "CMT_TOP_NE4BEG0_0" + ], + [ + "CMT_FIFO_SW4END1_7", + "CMT_TOP_SW4END1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_6", + "CMT_TOP_LOGIC_OUTS_L_B10_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_6", + "CMT_TOP_LOGIC_OUTS_L_B14_6" + ], + [ + "CMT_FIFO_NE4BEG1_3", + "CMT_TOP_NE4BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX20_2", + "CMT_TOP_IMUX20_2" + ], + [ + "CMT_FIFO_SE4BEG0_5", + "CMT_TOP_SE4BEG0_5" + ], + [ + "CMT_FIFO_NW4END0_2", + "CMT_TOP_NW4END0_2" + ], + [ + "CMT_FIFO_NW4A2_6", + "CMT_TOP_NW4A2_6" + ], + [ + "CMT_FIFO_WW2A3_10", + "CMT_TOP_WW2A3_10" + ], + [ + "CMT_FIFO_L_IMUX40_7", + "CMT_TOP_IMUX40_7" + ], + [ + "CMT_FIFO_LH8_11", + "CMT_TOP_LH8_11" + ], + [ + "CMT_FIFO_L_IMUX19_2", + "CMT_TOP_IMUX19_2" + ], + [ + "CMT_FIFO_WL1END3_6", + "CMT_TOP_WL1END3_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "CMT_TOP_OCLK_5" + ], + [ + "CMT_FIFO_L_IMUX16_8", + "CMT_TOP_IMUX16_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_8", + "CMT_TOP_LOGIC_OUTS_L_B12_8" + ], + [ + "CMT_FIFO_EE4BEG0_1", + "CMT_TOP_EE4BEG0_1" + ], + [ + "CMT_FIFO_WR1END1_6", + "CMT_TOP_WR1END1_6" + ], + [ + "CMT_FIFO_NE2A2_3", + "CMT_TOP_NE2A2_3" + ], + [ + "CMT_FIFO_WW4END1_5", + "CMT_TOP_WW4END1_5" + ], + [ + "CMT_FIFO_L_IMUX2_8", + "CMT_TOP_IMUX2_8" + ], + [ + "CMT_FIFO_NW4A2_9", + "CMT_TOP_NW4A2_9" + ], + [ + "CMT_FIFO_EL1BEG2_2", + "CMT_TOP_EL1BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX4_0", + "CMT_TOP_IMUX4_0" + ], + [ + "CMT_FIFO_EE4A1_7", + "CMT_TOP_EE4A1_7" + ], + [ + "CMT_FIFO_L_IMUX35_1", + "CMT_TOP_IMUX35_1" + ], + [ + "CMT_FIFO_WL1END2_7", + "CMT_TOP_WL1END2_7" + ], + [ + "CMT_FIFO_LH1_3", + "CMT_TOP_LH1_3" + ], + [ + "CMT_FIFO_L_FAN5_3", + "CMT_TOP_FAN5_3" + ], + [ + "CMT_FIFO_L_IMUX11_8", + "CMT_TOP_IMUX11_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "CMT_TOP_ICLKDIV_4" + ], + [ + "CMT_FIFO_EE4B0_7", + "CMT_TOP_EE4B0_7" + ], + [ + "CMT_FIFO_WW4A0_9", + "CMT_TOP_WW4A0_9" + ], + [ + "CMT_FIFO_L_IMUX40_0", + "CMT_TOP_IMUX40_0" + ], + [ + "CMT_FIFO_L_CTRL0_5", + "CMT_TOP_CTRL0_5" + ], + [ + "CMT_FIFO_L_BYP2_2", + "CMT_TOP_BYP2_2" + ], + [ + "CMT_FIFO_L_IMUX19_0", + "CMT_TOP_IMUX19_0" + ], + [ + "CMT_FIFO_WR1END3_0", + "CMT_TOP_WR1END3_0" + ], + [ + "CMT_FIFO_EL1BEG0_5", + "CMT_TOP_EL1BEG0_5" + ], + [ + "CMT_FIFO_EE4B1_10", + "CMT_TOP_EE4B1_10" + ], + [ + "CMT_FIFO_EE4A1_3", + "CMT_TOP_EE4A1_3" + ], + [ + "CMT_FIFO_EE4BEG3_10", + "CMT_TOP_EE4BEG3_10" + ], + [ + "CMT_FIFO_EE2A1_3", + "CMT_TOP_EE2A1_3" + ], + [ + "CMT_FIFO_L_BYP6_0", + "CMT_TOP_BYP6_0" + ], + [ + "CMT_FIFO_NE4BEG2_9", + "CMT_TOP_NE4BEG2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_11", + "CMT_TOP_LOGIC_OUTS_L_B0_11" + ], + [ + "CMT_FIFO_SW4END2_0", + "CMT_TOP_SW4END2_0" + ], + [ + "CMT_FIFO_L_IMUX33_8", + "CMT_TOP_IMUX33_8" + ], + [ + "CMT_FIFO_SW4END3_5", + "CMT_TOP_SW4END3_5" + ], + [ + "CMT_FIFO_L_IMUX24_9", + "CMT_TOP_IMUX24_9" + ], + [ + "CMT_FIFO_SW2A3_11", + "CMT_TOP_SW2A3_11" + ], + [ + "CMT_FIFO_L_IMUX37_4", + "CMT_TOP_IMUX37_4" + ], + [ + "CMT_FIFO_NW4A0_0", + "CMT_TOP_NW4A0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_8", + "CMT_TOP_LOGIC_OUTS_L_B9_8" + ], + [ + "CMT_FIFO_LH8_10", + "CMT_TOP_LH8_10" + ], + [ + "CMT_FIFO_NE4C2_11", + "CMT_TOP_NE4C2_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "CMT_TOP_ICLKDIV_8" + ], + [ + "CMT_FIFO_WW4B1_3", + "CMT_TOP_WW4B1_3" + ], + [ + "CMT_FIFO_WW4B0_1", + "CMT_TOP_WW4B0_1" + ], + [ + "CMT_FIFO_L_IMUX6_1", + "CMT_TOP_IMUX6_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_11", + "CMT_TOP_LOGIC_OUTS_L_B8_11" + ], + [ + "CMT_FIFO_WL1END1_9", + "CMT_TOP_WL1END1_9" + ], + [ + "CMT_FIFO_L_IMUX20_1", + "CMT_TOP_IMUX20_1" + ], + [ + "CMT_FIFO_L_IMUX43_3", + "CMT_TOP_IMUX43_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_3", + "CMT_TOP_LOGIC_OUTS_L_B2_3" + ], + [ + "CMT_FIFO_L_FAN7_0", + "CMT_TOP_FAN7_0" + ], + [ + "CMT_FIFO_L_BYP6_10", + "CMT_TOP_BYP6_10" + ], + [ + "CMT_FIFO_EE4B0_6", + "CMT_TOP_EE4B0_6" + ], + [ + "CMT_FIFO_EE4BEG1_6", + "CMT_TOP_EE4BEG1_6" + ], + [ + "CMT_FIFO_EE2A2_10", + "CMT_TOP_EE2A2_10" + ], + [ + "CMT_FIFO_L_IMUX28_5", + "CMT_TOP_IMUX28_5" + ], + [ + "CMT_FIFO_L_IMUX20_3", + "CMT_TOP_IMUX20_3" + ], + [ + "CMT_FIFO_SE4BEG2_3", + "CMT_TOP_SE4BEG2_3" + ], + [ + "CMT_FIFO_L_CLK0_2", + "CMT_TOP_CLK0_2" + ], + [ + "CMT_FIFO_SW4END2_1", + "CMT_TOP_SW4END2_1" + ], + [ + "CMT_FIFO_EE4A3_11", + "CMT_TOP_EE4A3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_7", + "CMT_TOP_LOGIC_OUTS_L_B6_7" + ], + [ + "CMT_FIFO_WL1END1_10", + "CMT_TOP_WL1END1_10" + ], + [ + "CMT_FIFO_LH2_11", + "CMT_TOP_LH2_11" + ], + [ + "CMT_FIFO_EL1BEG1_6", + "CMT_TOP_EL1BEG1_6" + ], + [ + "CMT_FIFO_NE4C1_10", + "CMT_TOP_NE4C1_10" + ], + [ + "CMT_FIFO_NE4C2_4", + "CMT_TOP_NE4C2_4" + ], + [ + "CMT_FIFO_L_IMUX24_11", + "CMT_TOP_IMUX24_11" + ], + [ + "CMT_FIFO_L_IMUX27_10", + "CMT_TOP_IMUX27_10" + ], + [ + "CMT_FIFO_EE4A2_7", + "CMT_TOP_EE4A2_7" + ], + [ + "CMT_FIFO_EE4BEG2_9", + "CMT_TOP_EE4BEG2_9" + ], + [ + "CMT_FIFO_LH9_9", + "CMT_TOP_LH9_9" + ], + [ + "CMT_FIFO_WR1END0_2", + "CMT_TOP_WR1END0_2" + ], + [ + "CMT_FIFO_L_IMUX9_11", + "CMT_TOP_IMUX9_11" + ], + [ + "CMT_FIFO_WW4B1_7", + "CMT_TOP_WW4B1_7" + ], + [ + "CMT_FIFO_L_CLK0_1", + "CMT_TOP_CLK0_1" + ], + [ + "CMT_FIFO_WW2END2_9", + "CMT_TOP_WW2END2_9" + ], + [ + "CMT_FIFO_NE4BEG3_8", + "CMT_TOP_NE4BEG3_8" + ], + [ + "CMT_FIFO_WW4A2_0", + "CMT_TOP_WW4A2_0" + ], + [ + "CMT_FIFO_WL1END2_0", + "CMT_TOP_WL1END2_0" + ], + [ + "CMT_FIFO_EE2BEG2_7", + "CMT_TOP_EE2BEG2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_9", + "CMT_TOP_LOGIC_OUTS_L_B18_9" + ], + [ + "CMT_FIFO_WW2END1_9", + "CMT_TOP_WW2END1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_10", + "CMT_TOP_LOGIC_OUTS_L_B12_10" + ], + [ + "CMT_FIFO_WW4C2_11", + "CMT_TOP_WW4C2_11" + ], + [ + "CMT_FIFO_SE4C1_9", + "CMT_TOP_SE4C1_9" + ], + [ + "CMT_FIFO_WL1END2_9", + "CMT_TOP_WL1END2_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "CMT_TOP_OCLKDIV_10" + ], + [ + "CMT_FIFO_EE2BEG1_3", + "CMT_TOP_EE2BEG1_3" + ], + [ + "CMT_FIFO_WW2END2_1", + "CMT_TOP_WW2END2_1" + ], + [ + "CMT_FIFO_L_BYP5_0", + "CMT_TOP_BYP5_0" + ], + [ + "CMT_FIFO_NE4C2_10", + "CMT_TOP_NE4C2_10" + ], + [ + "CMT_FIFO_NE4BEG0_11", + "CMT_TOP_NE4BEG0_11" + ], + [ + "CMT_FIFO_NE4C2_0", + "CMT_TOP_NE4C2_0" + ], + [ + "CMT_FIFO_SW4A2_7", + "CMT_TOP_SW4A2_7" + ], + [ + "CMT_FIFO_SW4END1_3", + "CMT_TOP_SW4END1_3" + ], + [ + "CMT_FIFO_L_IMUX9_3", + "CMT_TOP_IMUX9_3" + ], + [ + "CMT_FIFO_LH2_0", + "CMT_TOP_LH2_0" + ], + [ + "CMT_FIFO_EL1BEG2_1", + "CMT_TOP_EL1BEG2_1" + ], + [ + "CMT_FIFO_WL1END2_1", + "CMT_TOP_WL1END2_1" + ], + [ + "CMT_FIFO_EE4C3_3", + "CMT_TOP_EE4C3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_6", + "CMT_TOP_LOGIC_OUTS_L_B15_6" + ], + [ + "CMT_FIFO_L_IMUX22_1", + "CMT_TOP_IMUX22_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_5", + "CMT_TOP_LOGIC_OUTS_L_B21_5" + ], + [ + "CMT_FIFO_SW4END1_0", + "CMT_TOP_SW4END1_0" + ], + [ + "CMT_FIFO_SE4C3_5", + "CMT_TOP_SE4C3_5" + ], + [ + "CMT_FIFO_EE4BEG0_8", + "CMT_TOP_EE4BEG0_8" + ], + [ + "CMT_FIFO_L_IMUX27_7", + "CMT_TOP_IMUX27_7" + ], + [ + "CMT_FIFO_NW4END0_8", + "CMT_TOP_NW4END0_8" + ], + [ + "CMT_FIFO_L_IMUX33_1", + "CMT_TOP_IMUX33_1" + ], + [ + "CMT_FIFO_L_IMUX11_0", + "CMT_TOP_IMUX11_0" + ], + [ + "CMT_FIFO_L_FAN0_0", + "CMT_TOP_FAN0_0" + ], + [ + "CMT_FIFO_SW4END2_9", + "CMT_TOP_SW4END2_9" + ], + [ + "CMT_FIFO_L_IMUX35_10", + "CMT_TOP_IMUX35_10" + ], + [ + "CMT_FIFO_WW2END3_7", + "CMT_TOP_WW2END3_7" + ], + [ + "CMT_FIFO_EE4BEG1_3", + "CMT_TOP_EE4BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX19_3", + "CMT_TOP_IMUX19_3" + ], + [ + "CMT_FIFO_EE4B3_9", + "CMT_TOP_EE4B3_9" + ], + [ + "CMT_FIFO_LH3_3", + "CMT_TOP_LH3_3" + ], + [ + "CMT_FIFO_EE2A1_5", + "CMT_TOP_EE2A1_5" + ], + [ + "CMT_FIFO_NW2A1_5", + "CMT_TOP_NW2A1_5" + ], + [ + "CMT_FIFO_EE2A0_2", + "CMT_TOP_EE2A0_2" + ], + [ + "CMT_FIFO_SW4A2_10", + "CMT_TOP_SW4A2_10" + ], + [ + "CMT_FIFO_EE4C2_2", + "CMT_TOP_EE4C2_2" + ], + [ + "CMT_FIFO_LH2_7", + "CMT_TOP_LH2_7" + ], + [ + "CMT_FIFO_EE4BEG3_6", + "CMT_TOP_EE4BEG3_6" + ], + [ + "CMT_FIFO_L_IMUX44_8", + "CMT_TOP_IMUX44_8" + ], + [ + "CMT_FIFO_L_IMUX23_4", + "CMT_TOP_IMUX23_4" + ], + [ + "CMT_FIFO_SE4BEG2_10", + "CMT_TOP_SE4BEG2_10" + ], + [ + "CMT_FIFO_L_IMUX30_6", + "CMT_TOP_IMUX30_6" + ], + [ + "CMT_FIFO_L_CTRL0_3", + "CMT_TOP_CTRL0_3" + ], + [ + "CMT_FIFO_WR1END3_2", + "CMT_TOP_WR1END3_2" + ], + [ + "CMT_FIFO_SW4A0_3", + "CMT_TOP_SW4A0_3" + ], + [ + "CMT_FIFO_L_IMUX22_11", + "CMT_TOP_IMUX22_11" + ], + [ + "CMT_FIFO_LH9_3", + "CMT_TOP_LH9_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_11", + "CMT_TOP_LOGIC_OUTS_L_B11_11" + ], + [ + "CMT_FIFO_L_IMUX24_5", + "CMT_TOP_IMUX24_5" + ], + [ + "CMT_FIFO_WR1END1_11", + "CMT_TOP_WR1END1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_4", + "CMT_TOP_LOGIC_OUTS_L_B10_4" + ], + [ + "CMT_FIFO_SE4C0_6", + "CMT_TOP_SE4C0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_10", + "CMT_TOP_LOGIC_OUTS_L_B9_10" + ], + [ + "CMT_FIFO_LH4_10", + "CMT_TOP_LH4_10" + ], + [ + "CMT_FIFO_L_IMUX2_1", + "CMT_TOP_IMUX2_1" + ], + [ + "CMT_FIFO_LH7_6", + "CMT_TOP_LH7_6" + ], + [ + "CMT_FIFO_L_BYP5_7", + "CMT_TOP_BYP5_7" + ], + [ + "CMT_FIFO_L_IMUX4_11", + "CMT_TOP_IMUX4_11" + ], + [ + "CMT_FIFO_L_IMUX43_5", + "CMT_TOP_IMUX43_5" + ], + [ + "CMT_FIFO_L_IMUX18_5", + "CMT_TOP_IMUX18_5" + ], + [ + "CMT_FIFO_WW4END1_9", + "CMT_TOP_WW4END1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_1", + "CMT_TOP_LOGIC_OUTS_L_B9_1" + ], + [ + "CMT_FIFO_NE4BEG2_2", + "CMT_TOP_NE4BEG2_2" + ], + [ + "CMT_FIFO_WW2A3_8", + "CMT_TOP_WW2A3_8" + ], + [ + "CMT_FIFO_EL1BEG1_4", + "CMT_TOP_EL1BEG1_4" + ], + [ + "CMT_FIFO_SE2A1_7", + "CMT_TOP_SE2A1_7" + ], + [ + "CMT_FIFO_WW2A0_1", + "CMT_TOP_WW2A0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_10", + "CMT_TOP_LOGIC_OUTS_L_B19_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "CMT_TOP_ICLK_7" + ], + [ + "CMT_FIFO_NW4END1_3", + "CMT_TOP_NW4END1_3" + ], + [ + "CMT_FIFO_WW4C2_8", + "CMT_TOP_WW4C2_8" + ], + [ + "CMT_FIFO_NE4BEG1_11", + "CMT_TOP_NE4BEG1_11" + ], + [ + "CMT_FIFO_NE2A1_4", + "CMT_TOP_NE2A1_4" + ], + [ + "CMT_FIFO_NE4BEG0_10", + "CMT_TOP_NE4BEG0_10" + ], + [ + "CMT_FIFO_L_BYP1_4", + "CMT_TOP_BYP1_4" + ], + [ + "CMT_FIFO_EL1BEG3_3", + "CMT_TOP_EL1BEG3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_7" + ], + [ + "CMT_FIFO_NW2A2_10", + "CMT_TOP_NW2A2_10" + ], + [ + "CMT_FIFO_L_IMUX32_0", + "CMT_TOP_IMUX32_0" + ], + [ + "CMT_FIFO_SE4C0_4", + "CMT_TOP_SE4C0_4" + ], + [ + "CMT_FIFO_L_IMUX1_1", + "CMT_TOP_IMUX1_1" + ], + [ + "CMT_FIFO_L_IMUX39_10", + "CMT_TOP_IMUX39_10" + ], + [ + "CMT_FIFO_EE4C1_10", + "CMT_TOP_EE4C1_10" + ], + [ + "CMT_FIFO_L_BYP1_10", + "CMT_TOP_BYP1_10" + ], + [ + "CMT_FIFO_SE4BEG3_11", + "CMT_TOP_SE4BEG3_11" + ], + [ + "CMT_FIFO_L_IMUX47_9", + "CMT_TOP_IMUX47_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_4", + "CMT_TOP_LOGIC_OUTS_L_B4_4" + ], + [ + "CMT_FIFO_WL1END3_8", + "CMT_TOP_WL1END3_8" + ], + [ + "CMT_FIFO_L_IMUX13_11", + "CMT_TOP_IMUX13_11" + ], + [ + "CMT_FIFO_L_BYP5_8", + "CMT_TOP_BYP5_8" + ], + [ + "CMT_FIFO_NE4C3_9", + "CMT_TOP_NE4C3_9" + ], + [ + "CMT_FIFO_NE4C3_10", + "CMT_TOP_NE4C3_10" + ], + [ + "CMT_FIFO_L_IMUX26_10", + "CMT_TOP_IMUX26_10" + ], + [ + "CMT_FIFO_L_IMUX17_0", + "CMT_TOP_IMUX17_0" + ], + [ + "CMT_FIFO_L_IMUX25_9", + "CMT_TOP_IMUX25_9" + ], + [ + "CMT_FIFO_NW2A1_2", + "CMT_TOP_NW2A1_2" + ], + [ + "CMT_FIFO_L_IMUX45_11", + "CMT_TOP_IMUX45_11" + ], + [ + "CMT_FIFO_WW4C3_5", + "CMT_TOP_WW4C3_5" + ], + [ + "CMT_FIFO_WW4END2_10", + "CMT_TOP_WW4END2_10" + ], + [ + "CMT_FIFO_EE2A0_10", + "CMT_TOP_EE2A0_10" + ], + [ + "CMT_FIFO_ER1BEG0_7", + "CMT_TOP_ER1BEG0_7" + ], + [ + "CMT_FIFO_EE4BEG3_3", + "CMT_TOP_EE4BEG3_3" + ], + [ + "CMT_FIFO_L_IMUX42_1", + "CMT_TOP_IMUX42_1" + ], + [ + "CMT_FIFO_NE2A1_5", + "CMT_TOP_NE2A1_5" + ], + [ + "CMT_FIFO_L_IMUX22_2", + "CMT_TOP_IMUX22_2" + ], + [ + "CMT_FIFO_WR1END1_1", + "CMT_TOP_WR1END1_1" + ], + [ + "CMT_FIFO_EE2BEG1_8", + "CMT_TOP_EE2BEG1_8" + ], + [ + "CMT_FIFO_EL1BEG3_8", + "CMT_TOP_EL1BEG3_8" + ], + [ + "CMT_FIFO_L_IMUX19_9", + "CMT_TOP_IMUX19_9" + ], + [ + "CMT_FIFO_ER1BEG1_6", + "CMT_TOP_ER1BEG1_6" + ], + [ + "CMT_FIFO_SW2A3_5", + "CMT_TOP_SW2A3_5" + ], + [ + "CMT_FIFO_L_BYP3_6", + "CMT_TOP_BYP3_6" + ], + [ + "CMT_FIFO_ER1BEG3_1", + "CMT_TOP_ER1BEG3_1" + ], + [ + "CMT_FIFO_L_BYP4_10", + "CMT_TOP_BYP4_10" + ], + [ + "CMT_FIFO_SW4A3_9", + "CMT_TOP_SW4A3_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "CMT_TOP_OCLK_3" + ], + [ + "CMT_FIFO_L_IMUX20_10", + "CMT_TOP_IMUX20_10" + ], + [ + "CMT_FIFO_NW2A2_11", + "CMT_TOP_NW2A2_11" + ], + [ + "CMT_FIFO_L_FAN2_8", + "CMT_TOP_FAN2_8" + ], + [ + "CMT_FIFO_L_FAN0_6", + "CMT_TOP_FAN0_6" + ], + [ + "CMT_FIFO_WW2A0_11", + "CMT_TOP_WW2A0_11" + ], + [ + "CMT_FIFO_WW4A1_3", + "CMT_TOP_WW4A1_3" + ], + [ + "CMT_FIFO_L_IMUX40_4", + "CMT_TOP_IMUX40_4" + ], + [ + "CMT_FIFO_L_IMUX46_2", + "CMT_TOP_IMUX46_2" + ], + [ + "CMT_FIFO_NW4END3_9", + "CMT_TOP_NW4END3_9" + ], + [ + "CMT_FIFO_ER1BEG2_6", + "CMT_TOP_ER1BEG2_6" + ], + [ + "CMT_FIFO_EE4A3_4", + "CMT_TOP_EE4A3_4" + ], + [ + "CMT_FIFO_EE4BEG2_1", + "CMT_TOP_EE4BEG2_1" + ], + [ + "CMT_FIFO_WW2A3_6", + "CMT_TOP_WW2A3_6" + ], + [ + "CMT_FIFO_WW4B0_9", + "CMT_TOP_WW4B0_9" + ], + [ + "CMT_FIFO_L_IMUX43_1", + "CMT_TOP_IMUX43_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_9", + "CMT_TOP_LOGIC_OUTS_L_B11_9" + ], + [ + "CMT_FIFO_L_IMUX16_6", + "CMT_TOP_IMUX16_6" + ], + [ + "CMT_FIFO_L_IMUX44_10", + "CMT_TOP_IMUX44_10" + ], + [ + "CMT_FIFO_EE4BEG1_8", + "CMT_TOP_EE4BEG1_8" + ], + [ + "CMT_FIFO_L_IMUX4_8", + "CMT_TOP_IMUX4_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_5" + ], + [ + "CMT_FIFO_WW4A0_3", + "CMT_TOP_WW4A0_3" + ], + [ + "CMT_FIFO_ER1BEG2_11", + "CMT_TOP_ER1BEG2_11" + ], + [ + "CMT_FIFO_EE2A0_6", + "CMT_TOP_EE2A0_6" + ], + [ + "CMT_FIFO_EE4BEG2_4", + "CMT_TOP_EE4BEG2_4" + ], + [ + "CMT_FIFO_LH2_1", + "CMT_TOP_LH2_1" + ], + [ + "CMT_FIFO_L_IMUX37_1", + "CMT_TOP_IMUX37_1" + ], + [ + "CMT_FIFO_WW4B1_0", + "CMT_TOP_WW4B1_0" + ], + [ + "CMT_FIFO_WW4B1_1", + "CMT_TOP_WW4B1_1" + ], + [ + "CMT_FIFO_NW2A3_8", + "CMT_TOP_NW2A3_8" + ], + [ + "CMT_FIFO_NW4A1_11", + "CMT_TOP_NW4A1_11" + ], + [ + "CMT_FIFO_EE4A1_10", + "CMT_TOP_EE4A1_10" + ], + [ + "CMT_FIFO_WR1END1_2", + "CMT_TOP_WR1END1_2" + ], + [ + "CMT_FIFO_WW4B0_0", + "CMT_TOP_WW4B0_0" + ], + [ + "CMT_FIFO_L_IMUX29_10", + "CMT_TOP_IMUX29_10" + ], + [ + "CMT_FIFO_WW2END1_11", + "CMT_TOP_WW2END1_11" + ], + [ + "CMT_FIFO_L_BYP2_4", + "CMT_TOP_BYP2_4" + ], + [ + "CMT_FIFO_WW4C2_6", + "CMT_TOP_WW4C2_6" + ], + [ + "CMT_FIFO_L_BYP7_2", + "CMT_TOP_BYP7_2" + ], + [ + "CMT_FIFO_L_IMUX45_0", + "CMT_TOP_IMUX45_0" + ], + [ + "CMT_FIFO_L_IMUX42_10", + "CMT_TOP_IMUX42_10" + ], + [ + "CMT_FIFO_L_CLK0_6", + "CMT_TOP_CLK0_6" + ], + [ + "CMT_FIFO_SW2A3_8", + "CMT_TOP_SW2A3_8" + ], + [ + "CMT_FIFO_NW4END1_4", + "CMT_TOP_NW4END1_4" + ], + [ + "CMT_FIFO_L_CLK1_2", + "CMT_TOP_CLK1_2" + ], + [ + "CMT_FIFO_EE2BEG3_2", + "CMT_TOP_EE2BEG3_2" + ], + [ + "CMT_FIFO_L_IMUX3_3", + "CMT_TOP_IMUX3_3" + ], + [ + "CMT_FIFO_WW4C0_1", + "CMT_TOP_WW4C0_1" + ], + [ + "CMT_FIFO_NE2A1_1", + "CMT_TOP_NE2A1_1" + ], + [ + "CMT_FIFO_L_BYP2_9", + "CMT_TOP_BYP2_9" + ], + [ + "CMT_FIFO_WW2A1_1", + "CMT_TOP_WW2A1_1" + ], + [ + "CMT_FIFO_L_FAN0_2", + "CMT_TOP_FAN0_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "CMT_TOP_OCLK_9" + ], + [ + "CMT_FIFO_SW2A2_6", + "CMT_TOP_SW2A2_6" + ], + [ + "CMT_FIFO_L_IMUX1_7", + "CMT_TOP_IMUX1_7" + ], + [ + "CMT_FIFO_SE4BEG2_4", + "CMT_TOP_SE4BEG2_4" + ], + [ + "CMT_FIFO_NW4A2_11", + "CMT_TOP_NW4A2_11" + ], + [ + "CMT_FIFO_EE4B0_11", + "CMT_TOP_EE4B0_11" + ], + [ + "CMT_FIFO_SW4A2_8", + "CMT_TOP_SW4A2_8" + ], + [ + "CMT_FIFO_WR1END3_1", + "CMT_TOP_WR1END3_1" + ], + [ + "CMT_FIFO_L_IMUX34_8", + "CMT_TOP_IMUX34_8" + ], + [ + "CMT_FIFO_L_IMUX47_3", + "CMT_TOP_IMUX47_3" + ], + [ + "CMT_FIFO_EE4A3_5", + "CMT_TOP_EE4A3_5" + ], + [ + "CMT_FIFO_EE4A0_0", + "CMT_TOP_EE4A0_0" + ], + [ + "CMT_FIFO_SE4BEG1_10", + "CMT_TOP_SE4BEG1_10" + ], + [ + "CMT_FIFO_LH2_10", + "CMT_TOP_LH2_10" + ], + [ + "CMT_FIFO_SE4C2_7", + "CMT_TOP_SE4C2_7" + ], + [ + "CMT_FIFO_L_IMUX15_5", + "CMT_TOP_IMUX15_5" + ], + [ + "CMT_FIFO_EE4C3_6", + "CMT_TOP_EE4C3_6" + ], + [ + "CMT_FIFO_L_IMUX44_5", + "CMT_TOP_IMUX44_5" + ], + [ + "CMT_FIFO_WW4C0_5", + "CMT_TOP_WW4C0_5" + ], + [ + "CMT_FIFO_L_IMUX31_10", + "CMT_TOP_IMUX31_10" + ], + [ + "CMT_FIFO_EL1BEG2_0", + "CMT_TOP_EL1BEG2_0" + ], + [ + "CMT_FIFO_SE4BEG0_7", + "CMT_TOP_SE4BEG0_7" + ], + [ + "CMT_FIFO_WW4END0_3", + "CMT_TOP_WW4END0_3" + ], + [ + "CMT_FIFO_WL1END1_7", + "CMT_TOP_WL1END1_7" + ], + [ + "CMT_FIFO_MONITOR_N_2", + "CMT_TOP_MONITOR_N_2" + ], + [ + "CMT_FIFO_NE4BEG0_4", + "CMT_TOP_NE4BEG0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_11", + "CMT_TOP_LOGIC_OUTS_L_B12_11" + ], + [ + "CMT_FIFO_SE4BEG2_5", + "CMT_TOP_SE4BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX17_2", + "CMT_TOP_IMUX17_2" + ], + [ + "CMT_FIFO_L_IMUX16_2", + "CMT_TOP_IMUX16_2" + ], + [ + "CMT_FIFO_WW4END1_8", + "CMT_TOP_WW4END1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_7", + "CMT_TOP_LOGIC_OUTS_L_B1_7" + ], + [ + "CMT_FIFO_L_IMUX20_0", + "CMT_TOP_IMUX20_0" + ], + [ + "CMT_FIFO_SE2A3_9", + "CMT_TOP_SE2A3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_3", + "CMT_TOP_LOGIC_OUTS_L_B7_3" + ], + [ + "CMT_FIFO_EE4C2_0", + "CMT_TOP_EE4C2_0" + ], + [ + "CMT_FIFO_L_FAN3_5", + "CMT_TOP_FAN3_5" + ], + [ + "CMT_FIFO_WW4B0_2", + "CMT_TOP_WW4B0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_2", + "CMT_TOP_LOGIC_OUTS_L_B9_2" + ], + [ + "CMT_FIFO_L_IMUX26_1", + "CMT_TOP_IMUX26_1" + ], + [ + "CMT_FIFO_EE4C3_1", + "CMT_TOP_EE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX38_3", + "CMT_TOP_IMUX38_3" + ], + [ + "CMT_FIFO_L_IMUX36_9", + "CMT_TOP_IMUX36_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_5", + "CMT_TOP_LOGIC_OUTS_L_B1_5" + ], + [ + "CMT_FIFO_EE4C0_1", + "CMT_TOP_EE4C0_1" + ], + [ + "CMT_FIFO_L_IMUX2_7", + "CMT_TOP_IMUX2_7" + ], + [ + "CMT_FIFO_NE4BEG1_8", + "CMT_TOP_NE4BEG1_8" + ], + [ + "CMT_FIFO_WW2A1_11", + "CMT_TOP_WW2A1_11" + ], + [ + "CMT_FIFO_L_CLK1_5", + "CMT_TOP_CLK1_5" + ], + [ + "CMT_FIFO_L_FAN0_3", + "CMT_TOP_FAN0_3" + ], + [ + "CMT_FIFO_WW4C3_7", + "CMT_TOP_WW4C3_7" + ], + [ + "CMT_FIFO_EE2BEG2_10", + "CMT_TOP_EE2BEG2_10" + ], + [ + "CMT_FIFO_SE4C2_5", + "CMT_TOP_SE4C2_5" + ], + [ + "CMT_FIFO_SW2A0_4", + "CMT_TOP_SW2A0_4" + ], + [ + "CMT_FIFO_L_IMUX2_3", + "CMT_TOP_IMUX2_3" + ], + [ + "CMT_FIFO_WR1END2_8", + "CMT_TOP_WR1END2_8" + ], + [ + "CMT_FIFO_L_IMUX8_0", + "CMT_TOP_IMUX8_0" + ], + [ + "CMT_FIFO_EE2BEG1_2", + "CMT_TOP_EE2BEG1_2" + ], + [ + "CMT_FIFO_WW2END0_3", + "CMT_TOP_WW2END0_3" + ], + [ + "CMT_FIFO_EE4A0_2", + "CMT_TOP_EE4A0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_2", + "CMT_TOP_LOGIC_OUTS_L_B10_2" + ], + [ + "CMT_FIFO_WW2END0_8", + "CMT_TOP_WW2END0_8" + ], + [ + "CMT_FIFO_L_FAN1_8", + "CMT_TOP_FAN1_8" + ], + [ + "CMT_FIFO_L_IMUX40_9", + "CMT_TOP_IMUX40_9" + ], + [ + "CMT_FIFO_WW2END3_9", + "CMT_TOP_WW2END3_9" + ], + [ + "CMT_FIFO_EE4C1_6", + "CMT_TOP_EE4C1_6" + ], + [ + "CMT_FIFO_L_BYP5_5", + "CMT_TOP_BYP5_5" + ], + [ + "CMT_FIFO_LH5_8", + "CMT_TOP_LH5_8" + ], + [ + "CMT_FIFO_L_FAN6_11", + "CMT_TOP_FAN6_11" + ], + [ + "CMT_FIFO_WW2A2_3", + "CMT_TOP_WW2A2_3" + ], + [ + "CMT_FIFO_WW2A3_3", + "CMT_TOP_WW2A3_3" + ], + [ + "CMT_FIFO_L_IMUX4_2", + "CMT_TOP_IMUX4_2" + ], + [ + "CMT_FIFO_L_IMUX36_4", + "CMT_TOP_IMUX36_4" + ], + [ + "CMT_FIFO_LH1_11", + "CMT_TOP_LH1_11" + ], + [ + "CMT_FIFO_WW4B3_0", + "CMT_TOP_WW4B3_0" + ], + [ + "CMT_FIFO_EE4B3_7", + "CMT_TOP_EE4B3_7" + ], + [ + "CMT_FIFO_LH5_11", + "CMT_TOP_LH5_11" + ], + [ + "CMT_FIFO_NW2A1_11", + "CMT_TOP_NW2A1_11" + ], + [ + "CMT_FIFO_SE4C2_9", + "CMT_TOP_SE4C2_9" + ], + [ + "CMT_FIFO_L_CTRL1_11", + "CMT_TOP_CTRL1_11" + ], + [ + "CMT_FIFO_SW2A0_5", + "CMT_TOP_SW2A0_5" + ], + [ + "CMT_FIFO_LH7_10", + "CMT_TOP_LH7_10" + ], + [ + "CMT_FIFO_L_IMUX25_0", + "CMT_TOP_IMUX25_0" + ], + [ + "CMT_FIFO_L_FAN2_5", + "CMT_TOP_FAN2_5" + ], + [ + "CMT_FIFO_NE4BEG3_2", + "CMT_TOP_NE4BEG3_2" + ], + [ + "CMT_FIFO_EE4B2_4", + "CMT_TOP_EE4B2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_4", + "CMT_TOP_LOGIC_OUTS_L_B19_4" + ], + [ + "CMT_FIFO_NE2A1_0", + "CMT_TOP_NE2A1_0" + ], + [ + "CMT_FIFO_WW2A0_6", + "CMT_TOP_WW2A0_6" + ], + [ + "CMT_FIFO_L_IMUX19_11", + "CMT_TOP_IMUX19_11" + ], + [ + "CMT_FIFO_L_IMUX3_5", + "CMT_TOP_IMUX3_5" + ], + [ + "CMT_FIFO_L_BYP7_1", + "CMT_TOP_BYP7_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_8", + "CMT_TOP_LOGIC_OUTS_L_B7_8" + ], + [ + "CMT_FIFO_WW4C3_2", + "CMT_TOP_WW4C3_2" + ], + [ + "CMT_FIFO_L_IMUX18_0", + "CMT_TOP_IMUX18_0" + ], + [ + "CMT_FIFO_LH2_9", + "CMT_TOP_LH2_9" + ], + [ + "CMT_FIFO_L_IMUX46_6", + "CMT_TOP_IMUX46_6" + ], + [ + "CMT_FIFO_L_IMUX29_9", + "CMT_TOP_IMUX29_9" + ], + [ + "CMT_FIFO_SE4C1_2", + "CMT_TOP_SE4C1_2" + ], + [ + "CMT_FIFO_L_IMUX24_6", + "CMT_TOP_IMUX24_6" + ], + [ + "CMT_FIFO_EE4A0_9", + "CMT_TOP_EE4A0_9" + ], + [ + "CMT_FIFO_SE2A3_3", + "CMT_TOP_SE2A3_3" + ], + [ + "CMT_FIFO_L_IMUX46_9", + "CMT_TOP_IMUX46_9" + ], + [ + "CMT_FIFO_NE4C0_5", + "CMT_TOP_NE4C0_5" + ], + [ + "CMT_FIFO_WW2A0_4", + "CMT_TOP_WW2A0_4" + ], + [ + "CMT_FIFO_L_FAN7_6", + "CMT_TOP_FAN7_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_8", + "CMT_TOP_LOGIC_OUTS_L_B13_8" + ], + [ + "CMT_FIFO_L_IMUX6_10", + "CMT_TOP_IMUX6_10" + ], + [ + "CMT_FIFO_SW2A1_4", + "CMT_TOP_SW2A1_4" + ], + [ + "CMT_FIFO_NE4BEG2_1", + "CMT_TOP_NE4BEG2_1" + ], + [ + "CMT_FIFO_ER1BEG0_8", + "CMT_TOP_ER1BEG0_8" + ], + [ + "CMT_FIFO_L_BYP1_9", + "CMT_TOP_BYP1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_2", + "CMT_TOP_LOGIC_OUTS_L_B22_2" + ], + [ + "CMT_FIFO_L_IMUX26_9", + "CMT_TOP_IMUX26_9" + ], + [ + "CMT_FIFO_WW4B1_8", + "CMT_TOP_WW4B1_8" + ], + [ + "CMT_FIFO_L_FAN6_0", + "CMT_TOP_FAN6_0" + ], + [ + "CMT_FIFO_L_IMUX20_4", + "CMT_TOP_IMUX20_4" + ], + [ + "CMT_FIFO_NW2A3_2", + "CMT_TOP_NW2A3_2" + ], + [ + "CMT_FIFO_NE4C1_11", + "CMT_TOP_NE4C1_11" + ], + [ + "CMT_FIFO_L_FAN1_11", + "CMT_TOP_FAN1_11" + ], + [ + "CMT_FIFO_LH10_3", + "CMT_TOP_LH10_3" + ], + [ + "CMT_FIFO_SE4C0_11", + "CMT_TOP_SE4C0_11" + ], + [ + "CMT_FIFO_L_FAN4_7", + "CMT_TOP_FAN4_7" + ], + [ + "CMT_FIFO_L_FAN2_3", + "CMT_TOP_FAN2_3" + ], + [ + "CMT_FIFO_NW4END3_2", + "CMT_TOP_NW4END3_2" + ], + [ + "CMT_FIFO_WW4A3_11", + "CMT_TOP_WW4A3_11" + ], + [ + "CMT_FIFO_L_IMUX25_8", + "CMT_TOP_IMUX25_8" + ], + [ + "CMT_FIFO_L_BYP5_2", + "CMT_TOP_BYP5_2" + ], + [ + "CMT_FIFO_EE4A1_9", + "CMT_TOP_EE4A1_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "CMT_TOP_OCLKDIV_3" + ], + [ + "CMT_FIFO_SE2A0_0", + "CMT_TOP_SE2A0_0" + ], + [ + "CMT_FIFO_L_CLK0_4", + "CMT_TOP_CLK0_4" + ], + [ + "CMT_FIFO_L_IMUX19_8", + "CMT_TOP_IMUX19_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_9", + "CMT_TOP_LOGIC_OUTS_L_B1_9" + ], + [ + "CMT_FIFO_NW2A0_4", + "CMT_TOP_NW2A0_4" + ], + [ + "CMT_FIFO_SE4C3_2", + "CMT_TOP_SE4C3_2" + ], + [ + "CMT_FIFO_SE2A1_5", + "CMT_TOP_SE2A1_5" + ], + [ + "CMT_FIFO_EE4BEG1_0", + "CMT_TOP_EE4BEG1_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_8", + "CMT_TOP_LOGIC_OUTS_L_B20_8" + ], + [ + "CMT_FIFO_L_IMUX45_5", + "CMT_TOP_IMUX45_5" + ], + [ + "CMT_FIFO_EL1BEG1_2", + "CMT_TOP_EL1BEG1_2" + ], + [ + "CMT_FIFO_L_FAN0_7", + "CMT_TOP_FAN0_7" + ], + [ + "CMT_FIFO_EE4B1_1", + "CMT_TOP_EE4B1_1" + ], + [ + "CMT_FIFO_L_IMUX21_5", + "CMT_TOP_IMUX21_5" + ], + [ + "CMT_FIFO_EL1BEG3_5", + "CMT_TOP_EL1BEG3_5" + ], + [ + "CMT_FIFO_EE4BEG1_2", + "CMT_TOP_EE4BEG1_2" + ], + [ + "CMT_FIFO_EE4BEG2_2", + "CMT_TOP_EE4BEG2_2" + ], + [ + "CMT_FIFO_LH8_6", + "CMT_TOP_LH8_6" + ], + [ + "CMT_FIFO_L_IMUX24_2", + "CMT_TOP_IMUX24_2" + ], + [ + "CMT_FIFO_L_IMUX32_4", + "CMT_TOP_IMUX32_4" + ], + [ + "CMT_FIFO_ER1BEG0_2", + "CMT_TOP_ER1BEG0_2" + ], + [ + "CMT_FIFO_EE4C3_5", + "CMT_TOP_EE4C3_5" + ], + [ + "CMT_FIFO_L_IMUX41_11", + "CMT_TOP_IMUX41_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_10", + "CMT_TOP_LOGIC_OUTS_L_B8_10" + ], + [ + "CMT_FIFO_WW4B3_6", + "CMT_TOP_WW4B3_6" + ], + [ + "CMT_FIFO_NW2A1_6", + "CMT_TOP_NW2A1_6" + ], + [ + "CMT_FIFO_L_BYP1_11", + "CMT_TOP_BYP1_11" + ], + [ + "CMT_FIFO_WW2A3_2", + "CMT_TOP_WW2A3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_2", + "CMT_TOP_LOGIC_OUTS_L_B11_2" + ], + [ + "CMT_FIFO_L_IMUX45_8", + "CMT_TOP_IMUX45_8" + ], + [ + "CMT_FIFO_WW2A1_10", + "CMT_TOP_WW2A1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_9", + "CMT_TOP_LOGIC_OUTS_L_B10_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_7", + "CMT_TOP_LOGIC_OUTS_L_B4_7" + ], + [ + "CMT_FIFO_L_IMUX6_6", + "CMT_TOP_IMUX6_6" + ], + [ + "CMT_FIFO_L_IMUX12_10", + "CMT_TOP_IMUX12_10" + ], + [ + "CMT_FIFO_L_CTRL0_0", + "CMT_TOP_CTRL0_0" + ], + [ + "CMT_FIFO_SW4A0_11", + "CMT_TOP_SW4A0_11" + ], + [ + "CMT_FIFO_L_FAN5_4", + "CMT_TOP_FAN5_4" + ], + [ + "CMT_FIFO_WW2END1_7", + "CMT_TOP_WW2END1_7" + ], + [ + "CMT_FIFO_WW2END0_0", + "CMT_TOP_WW2END0_0" + ], + [ + "CMT_FIFO_EE4B0_0", + "CMT_TOP_EE4B0_0" + ], + [ + "CMT_FIFO_NW4A1_6", + "CMT_TOP_NW4A1_6" + ], + [ + "CMT_FIFO_EE2BEG0_5", + "CMT_TOP_EE2BEG0_5" + ], + [ + "CMT_FIFO_SW4END0_5", + "CMT_TOP_SW4END0_5" + ], + [ + "CMT_FIFO_SE4BEG2_7", + "CMT_TOP_SE4BEG2_7" + ], + [ + "CMT_FIFO_L_CTRL1_7", + "CMT_TOP_CTRL1_7" + ], + [ + "CMT_FIFO_SW4END3_0", + "CMT_TOP_SW4END3_0" + ], + [ + "CMT_FIFO_SW4A2_1", + "CMT_TOP_SW4A2_1" + ], + [ + "CMT_FIFO_EL1BEG3_2", + "CMT_TOP_EL1BEG3_2" + ], + [ + "CMT_FIFO_SE4BEG1_11", + "CMT_TOP_SE4BEG1_11" + ], + [ + "CMT_FIFO_NW4END3_5", + "CMT_TOP_NW4END3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_11", + "CMT_TOP_LOGIC_OUTS_L_B16_11" + ], + [ + "CMT_FIFO_L_IMUX16_1", + "CMT_TOP_IMUX16_1" + ], + [ + "CMT_FIFO_WW4C3_4", + "CMT_TOP_WW4C3_4" + ], + [ + "CMT_FIFO_L_FAN0_10", + "CMT_TOP_FAN0_10" + ], + [ + "CMT_FIFO_L_FAN2_1", + "CMT_TOP_FAN2_1" + ], + [ + "CMT_FIFO_L_BYP3_8", + "CMT_TOP_BYP3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_11", + "CMT_TOP_LOGIC_OUTS_L_B20_11" + ], + [ + "CMT_FIFO_L_CLK0_3", + "CMT_TOP_CLK0_3" + ], + [ + "CMT_FIFO_WW4C0_8", + "CMT_TOP_WW4C0_8" + ], + [ + "CMT_FIFO_L_IMUX31_4", + "CMT_TOP_IMUX31_4" + ], + [ + "CMT_FIFO_L_IMUX43_7", + "CMT_TOP_IMUX43_7" + ], + [ + "CMT_FIFO_SE4C0_1", + "CMT_TOP_SE4C0_1" + ], + [ + "CMT_FIFO_EE4C3_8", + "CMT_TOP_EE4C3_8" + ], + [ + "CMT_FIFO_L_IMUX31_11", + "CMT_TOP_IMUX31_11" + ], + [ + "CMT_FIFO_NW4END0_0", + "CMT_TOP_NW4END0_0" + ], + [ + "CMT_FIFO_EE4C3_10", + "CMT_TOP_EE4C3_10" + ], + [ + "CMT_FIFO_NW4A1_1", + "CMT_TOP_NW4A1_1" + ], + [ + "CMT_FIFO_LH1_8", + "CMT_TOP_LH1_8" + ], + [ + "CMT_FIFO_L_IMUX3_11", + "CMT_TOP_IMUX3_11" + ], + [ + "CMT_FIFO_WW2A0_10", + "CMT_TOP_WW2A0_10" + ], + [ + "CMT_FIFO_L_FAN4_0", + "CMT_TOP_FAN4_0" + ], + [ + "CMT_FIFO_WW2A2_6", + "CMT_TOP_WW2A2_6" + ], + [ + "CMT_FIFO_L_IMUX42_6", + "CMT_TOP_IMUX42_6" + ], + [ + "CMT_FIFO_L_IMUX37_2", + "CMT_TOP_IMUX37_2" + ], + [ + "CMT_FIFO_EE4C2_11", + "CMT_TOP_EE4C2_11" + ], + [ + "CMT_FIFO_LH5_4", + "CMT_TOP_LH5_4" + ], + [ + "CMT_FIFO_EE2BEG1_0", + "CMT_TOP_EE2BEG1_0" + ], + [ + "CMT_FIFO_L_IMUX38_6", + "CMT_TOP_IMUX38_6" + ], + [ + "CMT_FIFO_EE4C2_8", + "CMT_TOP_EE4C2_8" + ], + [ + "CMT_FIFO_EE4BEG2_5", + "CMT_TOP_EE4BEG2_5" + ], + [ + "CMT_FIFO_WW4C1_7", + "CMT_TOP_WW4C1_7" + ], + [ + "CMT_FIFO_WW4C2_7", + "CMT_TOP_WW4C2_7" + ], + [ + "CMT_FIFO_L_BYP3_9", + "CMT_TOP_BYP3_9" + ], + [ + "CMT_FIFO_L_FAN4_11", + "CMT_TOP_FAN4_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_0", + "CMT_TOP_LOGIC_OUTS_L_B19_0" + ], + [ + "CMT_FIFO_SW4END0_4", + "CMT_TOP_SW4END0_4" + ], + [ + "CMT_FIFO_L_IMUX35_2", + "CMT_TOP_IMUX35_2" + ], + [ + "CMT_FIFO_WW4C1_10", + "CMT_TOP_WW4C1_10" + ], + [ + "CMT_FIFO_EE2A2_6", + "CMT_TOP_EE2A2_6" + ], + [ + "CMT_FIFO_EE4C3_11", + "CMT_TOP_EE4C3_11" + ], + [ + "CMT_FIFO_L_BYP7_10", + "CMT_TOP_BYP7_10" + ], + [ + "CMT_FIFO_L_IMUX29_8", + "CMT_TOP_IMUX29_8" + ], + [ + "CMT_FIFO_NE2A0_0", + "CMT_TOP_NE2A0_0" + ], + [ + "CMT_FIFO_NE2A0_9", + "CMT_TOP_NE2A0_9" + ], + [ + "CMT_FIFO_L_IMUX9_10", + "CMT_TOP_IMUX9_10" + ], + [ + "CMT_FIFO_WW2END1_0", + "CMT_TOP_WW2END1_0" + ], + [ + "CMT_FIFO_SE2A1_10", + "CMT_TOP_SE2A1_10" + ], + [ + "CMT_FIFO_L_IMUX34_6", + "CMT_TOP_IMUX34_6" + ], + [ + "CMT_FIFO_L_IMUX43_11", + "CMT_TOP_IMUX43_11" + ], + [ + "CMT_FIFO_EL1BEG2_10", + "CMT_TOP_EL1BEG2_10" + ], + [ + "CMT_FIFO_WW2END3_3", + "CMT_TOP_WW2END3_3" + ], + [ + "CMT_FIFO_L_IMUX15_2", + "CMT_TOP_IMUX15_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "CMT_TOP_OCLK_4" + ], + [ + "CMT_FIFO_EE4A3_1", + "CMT_TOP_EE4A3_1" + ], + [ + "CMT_FIFO_L_IMUX33_6", + "CMT_TOP_IMUX33_6" + ], + [ + "CMT_FIFO_WL1END3_5", + "CMT_TOP_WL1END3_5" + ], + [ + "CMT_FIFO_NE4C1_1", + "CMT_TOP_NE4C1_1" + ], + [ + "CMT_FIFO_ER1BEG0_3", + "CMT_TOP_ER1BEG0_3" + ], + [ + "CMT_FIFO_LH4_5", + "CMT_TOP_LH4_5" + ], + [ + "CMT_FIFO_L_IMUX16_3", + "CMT_TOP_IMUX16_3" + ], + [ + "CMT_FIFO_NE2A3_9", + "CMT_TOP_NE2A3_9" + ], + [ + "CMT_FIFO_NE4BEG2_10", + "CMT_TOP_NE4BEG2_10" + ], + [ + "CMT_FIFO_L_BYP3_1", + "CMT_TOP_BYP3_1" + ], + [ + "CMT_FIFO_WW4C3_11", + "CMT_TOP_WW4C3_11" + ], + [ + "CMT_FIFO_EL1BEG1_0", + "CMT_TOP_EL1BEG1_0" + ], + [ + "CMT_FIFO_L_CTRL0_11", + "CMT_TOP_CTRL0_11" + ], + [ + "CMT_FIFO_L_IMUX18_1", + "CMT_TOP_IMUX18_1" + ], + [ + "CMT_FIFO_SE4BEG0_2", + "CMT_TOP_SE4BEG0_2" + ], + [ + "CMT_FIFO_EE2BEG1_7", + "CMT_TOP_EE2BEG1_7" + ], + [ + "CMT_FIFO_EL1BEG1_7", + "CMT_TOP_EL1BEG1_7" + ], + [ + "CMT_FIFO_LH12_10", + "CMT_TOP_LH12_10" + ], + [ + "CMT_FIFO_ER1BEG0_6", + "CMT_TOP_ER1BEG0_6" + ], + [ + "CMT_FIFO_LH11_11", + "CMT_TOP_LH11_11" + ], + [ + "CMT_FIFO_L_IMUX5_6", + "CMT_TOP_IMUX5_6" + ], + [ + "CMT_FIFO_WW2END1_6", + "CMT_TOP_WW2END1_6" + ], + [ + "CMT_FIFO_WW4A2_6", + "CMT_TOP_WW4A2_6" + ], + [ + "CMT_FIFO_L_FAN4_2", + "CMT_TOP_FAN4_2" + ], + [ + "CMT_FIFO_WL1END0_6", + "CMT_TOP_WL1END0_6" + ], + [ + "CMT_FIFO_WW4END0_9", + "CMT_TOP_WW4END0_9" + ], + [ + "CMT_FIFO_WW4A0_11", + "CMT_TOP_WW4A0_11" + ], + [ + "CMT_FIFO_EE4B3_1", + "CMT_TOP_EE4B3_1" + ], + [ + "CMT_FIFO_L_IMUX19_1", + "CMT_TOP_IMUX19_1" + ], + [ + "CMT_FIFO_NW4A2_2", + "CMT_TOP_NW4A2_2" + ], + [ + "CMT_FIFO_L_IMUX3_10", + "CMT_TOP_IMUX3_10" + ], + [ + "CMT_FIFO_EE4C3_9", + "CMT_TOP_EE4C3_9" + ], + [ + "CMT_FIFO_SW4END2_8", + "CMT_TOP_SW4END2_8" + ], + [ + "CMT_FIFO_SE4C2_2", + "CMT_TOP_SE4C2_2" + ], + [ + "CMT_FIFO_NE2A2_11", + "CMT_TOP_NE2A2_11" + ], + [ + "CMT_FIFO_L_PHASER_RDCLK", + "CMT_PLL_PHASER_RDCLK_TOFIFO" + ], + [ + "CMT_FIFO_L_IMUX36_8", + "CMT_TOP_IMUX36_8" + ], + [ + "CMT_FIFO_L_IMUX44_11", + "CMT_TOP_IMUX44_11" + ], + [ + "CMT_FIFO_LH11_4", + "CMT_TOP_LH11_4" + ], + [ + "CMT_FIFO_L_BYP7_11", + "CMT_TOP_BYP7_11" + ], + [ + "CMT_FIFO_LH1_1", + "CMT_TOP_LH1_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "CMT_TOP_OCLKDIV_5" + ], + [ + "CMT_FIFO_LH6_3", + "CMT_TOP_LH6_3" + ], + [ + "CMT_FIFO_WW4C2_3", + "CMT_TOP_WW4C2_3" + ], + [ + "CMT_FIFO_NE4BEG3_9", + "CMT_TOP_NE4BEG3_9" + ], + [ + "CMT_FIFO_LH7_3", + "CMT_TOP_LH7_3" + ], + [ + "CMT_FIFO_L_IMUX1_5", + "CMT_TOP_IMUX1_5" + ], + [ + "CMT_FIFO_SW4A1_10", + "CMT_TOP_SW4A1_10" + ], + [ + "CMT_FIFO_L_FAN0_11", + "CMT_TOP_FAN0_11" + ], + [ + "CMT_FIFO_EE2BEG1_10", + "CMT_TOP_EE2BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX45_10", + "CMT_TOP_IMUX45_10" + ], + [ + "CMT_FIFO_NW4END0_7", + "CMT_TOP_NW4END0_7" + ], + [ + "CMT_FIFO_L_IMUX41_2", + "CMT_TOP_IMUX41_2" + ], + [ + "CMT_FIFO_EE4A1_4", + "CMT_TOP_EE4A1_4" + ], + [ + "CMT_FIFO_NE2A3_7", + "CMT_TOP_NE2A3_7" + ], + [ + "CMT_FIFO_L_IMUX19_5", + "CMT_TOP_IMUX19_5" + ], + [ + "CMT_FIFO_NE4C2_6", + "CMT_TOP_NE4C2_6" + ], + [ + "CMT_FIFO_L_IMUX12_6", + "CMT_TOP_IMUX12_6" + ], + [ + "CMT_FIFO_SE4C3_6", + "CMT_TOP_SE4C3_6" + ], + [ + "CMT_FIFO_L_IMUX0_6", + "CMT_TOP_IMUX0_6" + ], + [ + "CMT_FIFO_SE4C0_8", + "CMT_TOP_SE4C0_8" + ], + [ + "CMT_FIFO_L_IMUX38_4", + "CMT_TOP_IMUX38_4" + ], + [ + "CMT_FIFO_EE4C2_9", + "CMT_TOP_EE4C2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_9", + "CMT_TOP_LOGIC_OUTS_L_B13_9" + ], + [ + "CMT_FIFO_L_IMUX16_11", + "CMT_TOP_IMUX16_11" + ], + [ + "CMT_FIFO_L_IMUX28_7", + "CMT_TOP_IMUX28_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_5", + "CMT_TOP_LOGIC_OUTS_L_B11_5" + ], + [ + "CMT_FIFO_L_IMUX7_1", + "CMT_TOP_IMUX7_1" + ], + [ + "CMT_FIFO_MONITOR_N_8", + "CMT_TOP_MONITOR_N_8" + ], + [ + "CMT_FIFO_L_IMUX47_1", + "CMT_TOP_IMUX47_1" + ], + [ + "CMT_FIFO_L_FAN2_9", + "CMT_TOP_FAN2_9" + ], + [ + "CMT_FIFO_SE2A2_4", + "CMT_TOP_SE2A2_4" + ], + [ + "CMT_FIFO_LH4_3", + "CMT_TOP_LH4_3" + ], + [ + "CMT_FIFO_EE4A0_5", + "CMT_TOP_EE4A0_5" + ], + [ + "CMT_FIFO_L_CLK1_4", + "CMT_TOP_CLK1_4" + ], + [ + "CMT_FIFO_LH5_3", + "CMT_TOP_LH5_3" + ], + [ + "CMT_FIFO_LH10_0", + "CMT_TOP_LH10_0" + ], + [ + "CMT_FIFO_L_IMUX21_6", + "CMT_TOP_IMUX21_6" + ], + [ + "CMT_FIFO_NW4A3_10", + "CMT_TOP_NW4A3_10" + ], + [ + "CMT_FIFO_L_IMUX18_4", + "CMT_TOP_IMUX18_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_6", + "CMT_TOP_LOGIC_OUTS_L_B23_6" + ], + [ + "CMT_FIFO_NW2A0_8", + "CMT_TOP_NW2A0_8" + ], + [ + "CMT_FIFO_EE4A1_0", + "CMT_TOP_EE4A1_0" + ], + [ + "CMT_FIFO_SE4C2_10", + "CMT_TOP_SE4C2_10" + ], + [ + "CMT_FIFO_WW4END0_5", + "CMT_TOP_WW4END0_5" + ], + [ + "CMT_FIFO_SW4END3_4", + "CMT_TOP_SW4END3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_10", + "CMT_TOP_LOGIC_OUTS_L_B13_10" + ], + [ + "CMT_FIFO_WW4A1_1", + "CMT_TOP_WW4A1_1" + ], + [ + "CMT_FIFO_WW4END1_6", + "CMT_TOP_WW4END1_6" + ], + [ + "CMT_FIFO_SW2A1_1", + "CMT_TOP_SW2A1_1" + ], + [ + "CMT_FIFO_NW4A3_3", + "CMT_TOP_NW4A3_3" + ], + [ + "CMT_FIFO_L_FAN7_7", + "CMT_TOP_FAN7_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "CMT_TOP_ICLKDIV_6" + ], + [ + "CMT_FIFO_L_IMUX32_10", + "CMT_TOP_IMUX32_10" + ], + [ + "CMT_FIFO_L_IMUX0_7", + "CMT_TOP_IMUX0_7" + ], + [ + "CMT_FIFO_L_BYP3_5", + "CMT_TOP_BYP3_5" + ], + [ + "CMT_FIFO_EE4C0_5", + "CMT_TOP_EE4C0_5" + ], + [ + "CMT_FIFO_WR1END0_6", + "CMT_TOP_WR1END0_6" + ], + [ + "CMT_FIFO_SE4BEG1_2", + "CMT_TOP_SE4BEG1_2" + ], + [ + "CMT_FIFO_NW2A1_3", + "CMT_TOP_NW2A1_3" + ], + [ + "CMT_FIFO_L_IMUX10_5", + "CMT_TOP_IMUX10_5" + ], + [ + "CMT_FIFO_L_IMUX45_4", + "CMT_TOP_IMUX45_4" + ], + [ + "CMT_FIFO_EE4C3_2", + "CMT_TOP_EE4C3_2" + ], + [ + "CMT_FIFO_SE4BEG3_4", + "CMT_TOP_SE4BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_2", + "CMT_TOP_LOGIC_OUTS_L_B23_2" + ], + [ + "CMT_FIFO_ER1BEG0_10", + "CMT_TOP_ER1BEG0_10" + ], + [ + "CMT_FIFO_NW4A3_5", + "CMT_TOP_NW4A3_5" + ], + [ + "CMT_FIFO_LH9_0", + "CMT_TOP_LH9_0" + ], + [ + "CMT_FIFO_SW4A3_5", + "CMT_TOP_SW4A3_5" + ], + [ + "CMT_FIFO_WW4A3_6", + "CMT_TOP_WW4A3_6" + ], + [ + "CMT_FIFO_SE2A1_1", + "CMT_TOP_SE2A1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_1", + "CMT_TOP_LOGIC_OUTS_L_B19_1" + ], + [ + "CMT_FIFO_L_FAN5_9", + "CMT_TOP_FAN5_9" + ], + [ + "CMT_FIFO_NE4C3_7", + "CMT_TOP_NE4C3_7" + ], + [ + "CMT_FIFO_NW2A3_11", + "CMT_TOP_NW2A3_11" + ], + [ + "CMT_FIFO_WW4END2_3", + "CMT_TOP_WW4END2_3" + ], + [ + "CMT_FIFO_LH1_2", + "CMT_TOP_LH1_2" + ], + [ + "CMT_FIFO_SW4END2_2", + "CMT_TOP_SW4END2_2" + ], + [ + "CMT_FIFO_L_IMUX23_10", + "CMT_TOP_IMUX23_10" + ], + [ + "CMT_FIFO_WR1END3_9", + "CMT_TOP_WR1END3_9" + ], + [ + "CMT_FIFO_L_IMUX42_5", + "CMT_TOP_IMUX42_5" + ], + [ + "CMT_FIFO_NE4C1_7", + "CMT_TOP_NE4C1_7" + ], + [ + "CMT_FIFO_LH7_11", + "CMT_TOP_LH7_11" + ], + [ + "CMT_FIFO_L_BYP5_11", + "CMT_TOP_BYP5_11" + ], + [ + "CMT_FIFO_MONITOR_P_8", + "CMT_TOP_MONITOR_P_8" + ], + [ + "CMT_FIFO_SE4C0_9", + "CMT_TOP_SE4C0_9" + ], + [ + "CMT_FIFO_L_IMUX46_8", + "CMT_TOP_IMUX46_8" + ], + [ + "CMT_FIFO_L_IMUX10_10", + "CMT_TOP_IMUX10_10" + ], + [ + "CMT_FIFO_MONITOR_P_10", + "CMT_TOP_MONITOR_P_10" + ], + [ + "CMT_FIFO_L_IMUX4_9", + "CMT_TOP_IMUX4_9" + ], + [ + "CMT_FIFO_SW2A2_3", + "CMT_TOP_SW2A2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_5", + "CMT_TOP_LOGIC_OUTS_L_B15_5" + ], + [ + "CMT_FIFO_EE4B2_8", + "CMT_TOP_EE4B2_8" + ], + [ + "CMT_FIFO_L_IMUX17_6", + "CMT_TOP_IMUX17_6" + ], + [ + "CMT_FIFO_EL1BEG3_1", + "CMT_TOP_EL1BEG3_1" + ], + [ + "CMT_FIFO_L_IMUX34_9", + "CMT_TOP_IMUX34_9" + ], + [ + "CMT_FIFO_EL1BEG2_6", + "CMT_TOP_EL1BEG2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_10", + "CMT_TOP_LOGIC_OUTS_L_B4_10" + ], + [ + "CMT_FIFO_L_IMUX44_7", + "CMT_TOP_IMUX44_7" + ], + [ + "CMT_FIFO_SW4A3_11", + "CMT_TOP_SW4A3_11" + ], + [ + "CMT_FIFO_NW4A2_0", + "CMT_TOP_NW4A2_0" + ], + [ + "CMT_FIFO_LH7_8", + "CMT_TOP_LH7_8" + ], + [ + "CMT_FIFO_EE2BEG2_6", + "CMT_TOP_EE2BEG2_6" + ], + [ + "CMT_FIFO_SE4BEG0_1", + "CMT_TOP_SE4BEG0_1" + ], + [ + "CMT_FIFO_WW4B1_4", + "CMT_TOP_WW4B1_4" + ], + [ + "CMT_FIFO_L_CTRL0_9", + "CMT_TOP_CTRL0_9" + ], + [ + "CMT_FIFO_SE4C1_3", + "CMT_TOP_SE4C1_3" + ], + [ + "CMT_FIFO_WW2END2_11", + "CMT_TOP_WW2END2_11" + ], + [ + "CMT_FIFO_WR1END3_7", + "CMT_TOP_WR1END3_7" + ], + [ + "CMT_FIFO_WW4B2_2", + "CMT_TOP_WW4B2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_6", + "CMT_TOP_LOGIC_OUTS_L_B18_6" + ], + [ + "CMT_FIFO_LH3_6", + "CMT_TOP_LH3_6" + ], + [ + "CMT_FIFO_LH7_4", + "CMT_TOP_LH7_4" + ], + [ + "CMT_FIFO_LH12_1", + "CMT_TOP_LH12_1" + ], + [ + "CMT_FIFO_WW2A2_4", + "CMT_TOP_WW2A2_4" + ], + [ + "CMT_FIFO_ER1BEG2_1", + "CMT_TOP_ER1BEG2_1" + ], + [ + "CMT_FIFO_WW4A3_1", + "CMT_TOP_WW4A3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_10", + "CMT_TOP_LOGIC_OUTS_L_B22_10" + ], + [ + "CMT_FIFO_SW4END1_10", + "CMT_TOP_SW4END1_10" + ], + [ + "CMT_FIFO_L_IMUX30_9", + "CMT_TOP_IMUX30_9" + ], + [ + "CMT_FIFO_EE4C1_1", + "CMT_TOP_EE4C1_1" + ], + [ + "CMT_FIFO_NW2A2_7", + "CMT_TOP_NW2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_4", + "CMT_TOP_LOGIC_OUTS_L_B1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_6", + "CMT_TOP_LOGIC_OUTS_L_B9_6" + ], + [ + "CMT_FIFO_NE2A3_6", + "CMT_TOP_NE2A3_6" + ], + [ + "CMT_FIFO_L_IMUX30_8", + "CMT_TOP_IMUX30_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "CMT_TOP_ICLKDIV_10" + ], + [ + "CMT_FIFO_NW4END3_8", + "CMT_TOP_NW4END3_8" + ], + [ + "CMT_FIFO_EE2BEG3_8", + "CMT_TOP_EE2BEG3_8" + ], + [ + "CMT_FIFO_NW2A0_3", + "CMT_TOP_NW2A0_3" + ], + [ + "CMT_FIFO_WR1END0_10", + "CMT_TOP_WR1END0_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "CMT_TOP_ICLKDIV_11" + ], + [ + "CMT_FIFO_L_BYP2_0", + "CMT_TOP_BYP2_0" + ], + [ + "CMT_FIFO_L_IMUX2_5", + "CMT_TOP_IMUX2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_11", + "CMT_TOP_LOGIC_OUTS_L_B9_11" + ], + [ + "CMT_FIFO_NW2A2_5", + "CMT_TOP_NW2A2_5" + ], + [ + "CMT_FIFO_NW2A2_3", + "CMT_TOP_NW2A2_3" + ], + [ + "CMT_FIFO_NW4A0_9", + "CMT_TOP_NW4A0_9" + ], + [ + "CMT_FIFO_SW2A1_5", + "CMT_TOP_SW2A1_5" + ], + [ + "CMT_FIFO_SE2A3_10", + "CMT_TOP_SE2A3_10" + ], + [ + "CMT_FIFO_EE2BEG2_1", + "CMT_TOP_EE2BEG2_1" + ], + [ + "CMT_FIFO_L_CTRL1_1", + "CMT_TOP_CTRL1_1" + ], + [ + "CMT_FIFO_NE2A3_8", + "CMT_TOP_NE2A3_8" + ], + [ + "CMT_FIFO_L_IMUX30_4", + "CMT_TOP_IMUX30_4" + ], + [ + "CMT_FIFO_L_BYP3_4", + "CMT_TOP_BYP3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_5", + "CMT_TOP_LOGIC_OUTS_L_B17_5" + ], + [ + "CMT_FIFO_WW4B3_5", + "CMT_TOP_WW4B3_5" + ], + [ + "CMT_FIFO_EE4B1_7", + "CMT_TOP_EE4B1_7" + ], + [ + "CMT_FIFO_EE4C0_9", + "CMT_TOP_EE4C0_9" + ], + [ + "CMT_FIFO_EE2BEG0_0", + "CMT_TOP_EE2BEG0_0" + ], + [ + "CMT_FIFO_LH8_0", + "CMT_TOP_LH8_0" + ], + [ + "CMT_FIFO_WR1END1_9", + "CMT_TOP_WR1END1_9" + ], + [ + "CMT_FIFO_EE2BEG3_5", + "CMT_TOP_EE2BEG3_5" + ], + [ + "CMT_FIFO_SE2A1_4", + "CMT_TOP_SE2A1_4" + ], + [ + "CMT_FIFO_L_IMUX32_3", + "CMT_TOP_IMUX32_3" + ], + [ + "CMT_FIFO_L_BYP5_10", + "CMT_TOP_BYP5_10" + ], + [ + "CMT_FIFO_EE4B3_11", + "CMT_TOP_EE4B3_11" + ], + [ + "CMT_FIFO_NW2A3_1", + "CMT_TOP_NW2A3_1" + ], + [ + "CMT_FIFO_SE4C1_1", + "CMT_TOP_SE4C1_1" + ], + [ + "CMT_FIFO_L_IMUX46_4", + "CMT_TOP_IMUX46_4" + ], + [ + "CMT_FIFO_EE4B2_2", + "CMT_TOP_EE4B2_2" + ], + [ + "CMT_FIFO_SW4END3_1", + "CMT_TOP_SW4END3_1" + ], + [ + "CMT_FIFO_WW2A1_7", + "CMT_TOP_WW2A1_7" + ], + [ + "CMT_FIFO_EL1BEG0_6", + "CMT_TOP_EL1BEG0_6" + ], + [ + "CMT_FIFO_EE2A2_2", + "CMT_TOP_EE2A2_2" + ], + [ + "CMT_FIFO_WR1END3_5", + "CMT_TOP_WR1END3_5" + ], + [ + "CMT_FIFO_L_BYP5_6", + "CMT_TOP_BYP5_6" + ], + [ + "CMT_FIFO_L_IMUX30_11", + "CMT_TOP_IMUX30_11" + ], + [ + "CMT_FIFO_L_IMUX4_4", + "CMT_TOP_IMUX4_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_6", + "CMT_TOP_LOGIC_OUTS_L_B3_6" + ], + [ + "CMT_FIFO_L_IMUX44_9", + "CMT_TOP_IMUX44_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_6", + "CMT_TOP_LOGIC_OUTS_L_B20_6" + ], + [ + "CMT_FIFO_EE4B1_0", + "CMT_TOP_EE4B1_0" + ], + [ + "CMT_FIFO_L_IMUX26_4", + "CMT_TOP_IMUX26_4" + ], + [ + "CMT_FIFO_L_IMUX39_0", + "CMT_TOP_IMUX39_0" + ], + [ + "CMT_FIFO_NW4A0_11", + "CMT_TOP_NW4A0_11" + ], + [ + "CMT_FIFO_WW4C0_10", + "CMT_TOP_WW4C0_10" + ], + [ + "CMT_FIFO_L_IMUX45_9", + "CMT_TOP_IMUX45_9" + ], + [ + "CMT_FIFO_NE4C1_0", + "CMT_TOP_NE4C1_0" + ], + [ + "CMT_FIFO_EE4A2_9", + "CMT_TOP_EE4A2_9" + ], + [ + "CMT_FIFO_L_FAN1_10", + "CMT_TOP_FAN1_10" + ], + [ + "CMT_FIFO_ER1BEG3_11", + "CMT_TOP_ER1BEG3_11" + ], + [ + "CMT_FIFO_NW4END3_10", + "CMT_TOP_NW4END3_10" + ], + [ + "CMT_FIFO_L_IMUX28_8", + "CMT_TOP_IMUX28_8" + ], + [ + "CMT_FIFO_L_IMUX38_5", + "CMT_TOP_IMUX38_5" + ], + [ + "CMT_FIFO_L_IMUX38_2", + "CMT_TOP_IMUX38_2" + ], + [ + "CMT_FIFO_ER1BEG0_4", + "CMT_TOP_ER1BEG0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_3", + "CMT_TOP_LOGIC_OUTS_L_B5_3" + ], + [ + "CMT_FIFO_L_BYP2_8", + "CMT_TOP_BYP2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_3", + "CMT_TOP_LOGIC_OUTS_L_B17_3" + ], + [ + "CMT_FIFO_SW2A3_0", + "CMT_TOP_SW2A3_0" + ], + [ + "CMT_FIFO_WW4C1_11", + "CMT_TOP_WW4C1_11" + ], + [ + "CMT_FIFO_NE2A2_2", + "CMT_TOP_NE2A2_2" + ], + [ + "CMT_FIFO_L_IMUX25_6", + "CMT_TOP_IMUX25_6" + ], + [ + "CMT_FIFO_L_IMUX15_11", + "CMT_TOP_IMUX15_11" + ], + [ + "CMT_FIFO_L_IMUX10_8", + "CMT_TOP_IMUX10_8" + ], + [ + "CMT_FIFO_L_IMUX38_11", + "CMT_TOP_IMUX38_11" + ], + [ + "CMT_FIFO_EE4B0_10", + "CMT_TOP_EE4B0_10" + ], + [ + "CMT_FIFO_WW4END2_9", + "CMT_TOP_WW4END2_9" + ], + [ + "CMT_FIFO_L_IMUX31_6", + "CMT_TOP_IMUX31_6" + ], + [ + "CMT_FIFO_L_IMUX35_3", + "CMT_TOP_IMUX35_3" + ], + [ + "CMT_FIFO_SW2A2_0", + "CMT_TOP_SW2A2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_0", + "CMT_TOP_LOGIC_OUTS_L_B11_0" + ], + [ + "CMT_FIFO_NW4A0_5", + "CMT_TOP_NW4A0_5" + ], + [ + "CMT_FIFO_L_IMUX14_10", + "CMT_TOP_IMUX14_10" + ], + [ + "CMT_FIFO_NE4C3_6", + "CMT_TOP_NE4C3_6" + ], + [ + "CMT_FIFO_L_IMUX31_3", + "CMT_TOP_IMUX31_3" + ], + [ + "CMT_FIFO_WW4B0_10", + "CMT_TOP_WW4B0_10" + ], + [ + "CMT_FIFO_L_CLK1_8", + "CMT_TOP_CLK1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_8", + "CMT_TOP_LOGIC_OUTS_L_B17_8" + ], + [ + "CMT_FIFO_L_FAN6_7", + "CMT_TOP_FAN6_7" + ], + [ + "CMT_FIFO_LH6_1", + "CMT_TOP_LH6_1" + ], + [ + "CMT_FIFO_L_FAN3_0", + "CMT_TOP_FAN3_0" + ], + [ + "CMT_FIFO_WW4C3_10", + "CMT_TOP_WW4C3_10" + ], + [ + "CMT_FIFO_EE2A3_6", + "CMT_TOP_EE2A3_6" + ], + [ + "CMT_FIFO_EL1BEG0_0", + "CMT_TOP_EL1BEG0_0" + ], + [ + "CMT_FIFO_EE4BEG2_11", + "CMT_TOP_EE4BEG2_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "CMT_TOP_ICLK_11" + ], + [ + "CMT_FIFO_SE2A2_9", + "CMT_TOP_SE2A2_9" + ], + [ + "CMT_FIFO_L_IMUX43_8", + "CMT_TOP_IMUX43_8" + ], + [ + "CMT_FIFO_EE4C2_7", + "CMT_TOP_EE4C2_7" + ], + [ + "CMT_FIFO_EE2BEG3_6", + "CMT_TOP_EE2BEG3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_7", + "CMT_TOP_LOGIC_OUTS_L_B23_7" + ], + [ + "CMT_FIFO_NE4BEG0_1", + "CMT_TOP_NE4BEG0_1" + ], + [ + "CMT_FIFO_NW4A0_8", + "CMT_TOP_NW4A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_7", + "CMT_TOP_LOGIC_OUTS_L_B21_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_3", + "CMT_TOP_LOGIC_OUTS_L_B19_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_8", + "CMT_TOP_LOGIC_OUTS_L_B23_8" + ], + [ + "CMT_FIFO_L_FAN7_4", + "CMT_TOP_FAN7_4" + ], + [ + "CMT_FIFO_WW4A2_2", + "CMT_TOP_WW4A2_2" + ], + [ + "CMT_FIFO_SE4C2_11", + "CMT_TOP_SE4C2_11" + ], + [ + "CMT_FIFO_L_IMUX27_1", + "CMT_TOP_IMUX27_1" + ], + [ + "CMT_FIFO_ER1BEG1_4", + "CMT_TOP_ER1BEG1_4" + ], + [ + "CMT_FIFO_L_FAN2_10", + "CMT_TOP_FAN2_10" + ], + [ + "CMT_FIFO_WW2END2_8", + "CMT_TOP_WW2END2_8" + ], + [ + "CMT_FIFO_L_IMUX23_11", + "CMT_TOP_IMUX23_11" + ], + [ + "CMT_FIFO_EE4C3_4", + "CMT_TOP_EE4C3_4" + ], + [ + "CMT_FIFO_L_IMUX41_0", + "CMT_TOP_IMUX41_0" + ], + [ + "CMT_FIFO_ER1BEG1_11", + "CMT_TOP_ER1BEG1_11" + ], + [ + "CMT_FIFO_SE4C3_7", + "CMT_TOP_SE4C3_7" + ], + [ + "CMT_FIFO_L_IMUX7_10", + "CMT_TOP_IMUX7_10" + ], + [ + "CMT_FIFO_L_FAN4_3", + "CMT_TOP_FAN4_3" + ], + [ + "CMT_FIFO_L_IMUX35_5", + "CMT_TOP_IMUX35_5" + ], + [ + "CMT_FIFO_WW4A0_5", + "CMT_TOP_WW4A0_5" + ], + [ + "CMT_FIFO_L_IMUX47_0", + "CMT_TOP_IMUX47_0" + ], + [ + "CMT_FIFO_WW4B3_2", + "CMT_TOP_WW4B3_2" + ], + [ + "CMT_FIFO_L_IMUX6_7", + "CMT_TOP_IMUX6_7" + ], + [ + "CMT_FIFO_L_IMUX28_0", + "CMT_TOP_IMUX28_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_5", + "CMT_TOP_LOGIC_OUTS_L_B23_5" + ], + [ + "CMT_FIFO_LH2_2", + "CMT_TOP_LH2_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "CMT_TOP_OCLKDIV_11" + ], + [ + "CMT_FIFO_WW4B1_11", + "CMT_TOP_WW4B1_11" + ], + [ + "CMT_FIFO_MONITOR_N_0", + "CMT_TOP_MONITOR_N_0" + ], + [ + "CMT_FIFO_WW4A2_5", + "CMT_TOP_WW4A2_5" + ], + [ + "CMT_FIFO_SE4BEG2_9", + "CMT_TOP_SE4BEG2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_0", + "CMT_TOP_LOGIC_OUTS_L_B5_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_5", + "CMT_TOP_LOGIC_OUTS_L_B20_5" + ], + [ + "CMT_FIFO_SE4C1_11", + "CMT_TOP_SE4C1_11" + ], + [ + "CMT_FIFO_EE4C2_1", + "CMT_TOP_EE4C2_1" + ], + [ + "CMT_FIFO_EE4B3_8", + "CMT_TOP_EE4B3_8" + ], + [ + "CMT_FIFO_L_IMUX37_8", + "CMT_TOP_IMUX37_8" + ], + [ + "CMT_FIFO_LH3_7", + "CMT_TOP_LH3_7" + ], + [ + "CMT_FIFO_SE2A0_5", + "CMT_TOP_SE2A0_5" + ], + [ + "CMT_FIFO_L_IMUX22_6", + "CMT_TOP_IMUX22_6" + ], + [ + "CMT_FIFO_L_BYP4_2", + "CMT_TOP_BYP4_2" + ], + [ + "CMT_FIFO_MONITOR_P_6", + "CMT_TOP_MONITOR_P_6" + ], + [ + "CMT_FIFO_WW4END2_11", + "CMT_TOP_WW4END2_11" + ], + [ + "CMT_FIFO_SE4BEG3_8", + "CMT_TOP_SE4BEG3_8" + ], + [ + "CMT_FIFO_NW2A3_10", + "CMT_TOP_NW2A3_10" + ], + [ + "CMT_FIFO_L_IMUX32_5", + "CMT_TOP_IMUX32_5" + ], + [ + "CMT_FIFO_L_IMUX17_7", + "CMT_TOP_IMUX17_7" + ], + [ + "CMT_FIFO_SE2A3_2", + "CMT_TOP_SE2A3_2" + ], + [ + "CMT_FIFO_WW4END3_11", + "CMT_TOP_WW4END3_11" + ], + [ + "CMT_FIFO_L_IMUX42_7", + "CMT_TOP_IMUX42_7" + ], + [ + "CMT_FIFO_L_IMUX32_7", + "CMT_TOP_IMUX32_7" + ], + [ + "CMT_FIFO_L_IMUX0_2", + "CMT_TOP_IMUX0_2" + ], + [ + "CMT_FIFO_L_IMUX46_7", + "CMT_TOP_IMUX46_7" + ], + [ + "CMT_FIFO_L_IMUX31_7", + "CMT_TOP_IMUX31_7" + ], + [ + "CMT_FIFO_WL1END3_1", + "CMT_TOP_WL1END3_1" + ], + [ + "CMT_FIFO_WW4B1_2", + "CMT_TOP_WW4B1_2" + ], + [ + "CMT_FIFO_LH5_5", + "CMT_TOP_LH5_5" + ], + [ + "CMT_FIFO_LH10_1", + "CMT_TOP_LH10_1" + ], + [ + "CMT_FIFO_NE2A1_7", + "CMT_TOP_NE2A1_7" + ], + [ + "CMT_FIFO_L_IMUX0_10", + "CMT_TOP_IMUX0_10" + ], + [ + "CMT_FIFO_L_BYP2_10", + "CMT_TOP_BYP2_10" + ], + [ + "CMT_FIFO_L_CTRL1_6", + "CMT_TOP_CTRL1_6" + ], + [ + "CMT_FIFO_WR1END0_9", + "CMT_TOP_WR1END0_9" + ], + [ + "CMT_FIFO_L_BYP1_7", + "CMT_TOP_BYP1_7" + ], + [ + "CMT_FIFO_L_FAN1_9", + "CMT_TOP_FAN1_9" + ], + [ + "CMT_FIFO_WW4C2_5", + "CMT_TOP_WW4C2_5" + ], + [ + "CMT_FIFO_NW4A3_11", + "CMT_TOP_NW4A3_11" + ], + [ + "CMT_FIFO_WL1END2_11", + "CMT_TOP_WL1END2_11" + ], + [ + "CMT_FIFO_L_BYP6_5", + "CMT_TOP_BYP6_5" + ], + [ + "CMT_FIFO_EE4BEG3_1", + "CMT_TOP_EE4BEG3_1" + ], + [ + "CMT_FIFO_L_IMUX17_8", + "CMT_TOP_IMUX17_8" + ], + [ + "CMT_FIFO_WW2END3_0", + "CMT_TOP_WW2END3_0" + ], + [ + "CMT_FIFO_L_IMUX42_4", + "CMT_TOP_IMUX42_4" + ], + [ + "CMT_FIFO_NE4BEG3_3", + "CMT_TOP_NE4BEG3_3" + ], + [ + "CMT_FIFO_SE4C2_0", + "CMT_TOP_SE4C2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_6", + "CMT_TOP_LOGIC_OUTS_L_B5_6" + ], + [ + "CMT_FIFO_WW4C2_9", + "CMT_TOP_WW4C2_9" + ], + [ + "CMT_FIFO_WW2END2_4", + "CMT_TOP_WW2END2_4" + ], + [ + "CMT_FIFO_SW2A0_2", + "CMT_TOP_SW2A0_2" + ], + [ + "CMT_FIFO_EE4BEG2_6", + "CMT_TOP_EE4BEG2_6" + ], + [ + "CMT_FIFO_EE2BEG0_3", + "CMT_TOP_EE2BEG0_3" + ], + [ + "CMT_FIFO_L_IMUX47_4", + "CMT_TOP_IMUX47_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_6", + "CMT_TOP_LOGIC_OUTS_L_B11_6" + ], + [ + "CMT_FIFO_L_FAN6_5", + "CMT_TOP_FAN6_5" + ], + [ + "CMT_FIFO_EE2BEG3_3", + "CMT_TOP_EE2BEG3_3" + ], + [ + "CMT_FIFO_L_IMUX31_0", + "CMT_TOP_IMUX31_0" + ], + [ + "CMT_FIFO_WR1END1_3", + "CMT_TOP_WR1END1_3" + ], + [ + "CMT_FIFO_NW2A1_8", + "CMT_TOP_NW2A1_8" + ], + [ + "CMT_FIFO_L_IMUX42_3", + "CMT_TOP_IMUX42_3" + ], + [ + "CMT_FIFO_NW2A2_0", + "CMT_TOP_NW2A2_0" + ], + [ + "CMT_FIFO_L_BYP1_0", + "CMT_TOP_BYP1_0" + ], + [ + "CMT_FIFO_EE2BEG3_11", + "CMT_TOP_EE2BEG3_11" + ], + [ + "CMT_FIFO_L_FAN5_1", + "CMT_TOP_FAN5_1" + ], + [ + "CMT_FIFO_SW2A1_6", + "CMT_TOP_SW2A1_6" + ], + [ + "CMT_FIFO_NW2A3_7", + "CMT_TOP_NW2A3_7" + ], + [ + "CMT_FIFO_EE4C1_9", + "CMT_TOP_EE4C1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_11", + "CMT_TOP_LOGIC_OUTS_L_B22_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_2", + "CMT_TOP_LOGIC_OUTS_L_B5_2" + ], + [ + "CMT_FIFO_WW4B2_8", + "CMT_TOP_WW4B2_8" + ], + [ + "CMT_FIFO_EE4A0_1", + "CMT_TOP_EE4A0_1" + ], + [ + "CMT_FIFO_WW4END2_1", + "CMT_TOP_WW4END2_1" + ], + [ + "CMT_FIFO_WL1END2_10", + "CMT_TOP_WL1END2_10" + ], + [ + "CMT_FIFO_L_IMUX12_7", + "CMT_TOP_IMUX12_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_0", + "CMT_TOP_LOGIC_OUTS_L_B13_0" + ], + [ + "CMT_FIFO_SW4A2_3", + "CMT_TOP_SW4A2_3" + ], + [ + "CMT_FIFO_WL1END3_0", + "CMT_TOP_WL1END3_0" + ], + [ + "CMT_FIFO_SW4END2_6", + "CMT_TOP_SW4END2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_0", + "CMT_TOP_LOGIC_OUTS_L_B8_0" + ], + [ + "CMT_FIFO_SW4A0_1", + "CMT_TOP_SW4A0_1" + ], + [ + "CMT_FIFO_WW4END3_7", + "CMT_TOP_WW4END3_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "CMT_TOP_OCLKDIV_1" + ], + [ + "CMT_FIFO_EE4BEG0_9", + "CMT_TOP_EE4BEG0_9" + ], + [ + "CMT_FIFO_SE4BEG3_2", + "CMT_TOP_SE4BEG3_2" + ], + [ + "CMT_FIFO_NW4A0_10", + "CMT_TOP_NW4A0_10" + ], + [ + "CMT_FIFO_ER1BEG3_8", + "CMT_TOP_ER1BEG3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_5", + "CMT_TOP_LOGIC_OUTS_L_B10_5" + ], + [ + "CMT_FIFO_SW2A2_10", + "CMT_TOP_SW2A2_10" + ], + [ + "CMT_FIFO_L_BYP2_3", + "CMT_TOP_BYP2_3" + ], + [ + "CMT_FIFO_WW4C0_7", + "CMT_TOP_WW4C0_7" + ], + [ + "CMT_FIFO_L_IMUX9_8", + "CMT_TOP_IMUX9_8" + ], + [ + "CMT_FIFO_NW4END2_5", + "CMT_TOP_NW4END2_5" + ], + [ + "CMT_FIFO_L_IMUX30_2", + "CMT_TOP_IMUX30_2" + ], + [ + "CMT_FIFO_L_BYP7_8", + "CMT_TOP_BYP7_8" + ], + [ + "CMT_FIFO_WL1END3_10", + "CMT_TOP_WL1END3_10" + ], + [ + "CMT_FIFO_L_IMUX11_10", + "CMT_TOP_IMUX11_10" + ], + [ + "CMT_FIFO_L_FAN5_11", + "CMT_TOP_FAN5_11" + ], + [ + "CMT_FIFO_NE4BEG3_0", + "CMT_TOP_NE4BEG3_0" + ], + [ + "CMT_FIFO_EE2A2_7", + "CMT_TOP_EE2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_5", + "CMT_TOP_LOGIC_OUTS_L_B8_5" + ], + [ + "CMT_FIFO_WW4A2_10", + "CMT_TOP_WW4A2_10" + ], + [ + "CMT_FIFO_EE4C2_10", + "CMT_TOP_EE4C2_10" + ], + [ + "CMT_FIFO_L_IMUX8_10", + "CMT_TOP_IMUX8_10" + ], + [ + "CMT_FIFO_SW4A1_8", + "CMT_TOP_SW4A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_9", + "CMT_TOP_LOGIC_OUTS_L_B15_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_3", + "CMT_TOP_LOGIC_OUTS_L_B10_3" + ], + [ + "CMT_FIFO_EL1BEG1_3", + "CMT_TOP_EL1BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX7_0", + "CMT_TOP_IMUX7_0" + ], + [ + "CMT_FIFO_L_IMUX29_0", + "CMT_TOP_IMUX29_0" + ], + [ + "CMT_FIFO_WW4B0_8", + "CMT_TOP_WW4B0_8" + ], + [ + "CMT_FIFO_NE4BEG2_6", + "CMT_TOP_NE4BEG2_6" + ], + [ + "CMT_FIFO_L_FAN1_0", + "CMT_TOP_FAN1_0" + ], + [ + "CMT_FIFO_WW2END0_11", + "CMT_TOP_WW2END0_11" + ], + [ + "CMT_FIFO_L_FAN3_1", + "CMT_TOP_FAN3_1" + ], + [ + "CMT_FIFO_LH12_7", + "CMT_TOP_LH12_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_3", + "CMT_TOP_LOGIC_OUTS_L_B18_3" + ], + [ + "CMT_FIFO_ER1BEG0_9", + "CMT_TOP_ER1BEG0_9" + ], + [ + "CMT_FIFO_SW4END1_5", + "CMT_TOP_SW4END1_5" + ], + [ + "CMT_FIFO_EE2BEG1_5", + "CMT_TOP_EE2BEG1_5" + ], + [ + "CMT_FIFO_EE2BEG2_5", + "CMT_TOP_EE2BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX14_5", + "CMT_TOP_IMUX14_5" + ], + [ + "CMT_FIFO_WW4A0_7", + "CMT_TOP_WW4A0_7" + ], + [ + "CMT_FIFO_L_IMUX23_6", + "CMT_TOP_IMUX23_6" + ], + [ + "CMT_FIFO_SW4END3_7", + "CMT_TOP_SW4END3_7" + ], + [ + "CMT_FIFO_L_IMUX46_3", + "CMT_TOP_IMUX46_3" + ], + [ + "CMT_FIFO_WR1END0_1", + "CMT_TOP_WR1END0_1" + ], + [ + "CMT_FIFO_SE4BEG2_2", + "CMT_TOP_SE4BEG2_2" + ], + [ + "CMT_FIFO_WW4END3_6", + "CMT_TOP_WW4END3_6" + ], + [ + "CMT_FIFO_SW4END2_4", + "CMT_TOP_SW4END2_4" + ], + [ + "CMT_FIFO_WW2A2_11", + "CMT_TOP_WW2A2_11" + ], + [ + "CMT_FIFO_WW2A2_0", + "CMT_TOP_WW2A2_0" + ], + [ + "CMT_FIFO_SE4C2_6", + "CMT_TOP_SE4C2_6" + ], + [ + "CMT_FIFO_SW2A3_1", + "CMT_TOP_SW2A3_1" + ], + [ + "CMT_FIFO_EE4C3_7", + "CMT_TOP_EE4C3_7" + ], + [ + "CMT_FIFO_EE4A2_8", + "CMT_TOP_EE4A2_8" + ], + [ + "CMT_FIFO_NE4BEG2_0", + "CMT_TOP_NE4BEG2_0" + ], + [ + "CMT_FIFO_NE4C1_6", + "CMT_TOP_NE4C1_6" + ], + [ + "CMT_FIFO_NE4C0_4", + "CMT_TOP_NE4C0_4" + ], + [ + "CMT_FIFO_L_IMUX13_6", + "CMT_TOP_IMUX13_6" + ], + [ + "CMT_FIFO_LH2_4", + "CMT_TOP_LH2_4" + ], + [ + "CMT_FIFO_LH1_10", + "CMT_TOP_LH1_10" + ], + [ + "CMT_FIFO_WW2END0_10", + "CMT_TOP_WW2END0_10" + ], + [ + "CMT_FIFO_L_IMUX7_9", + "CMT_TOP_IMUX7_9" + ], + [ + "CMT_FIFO_L_IMUX20_7", + "CMT_TOP_IMUX20_7" + ], + [ + "CMT_FIFO_NW2A3_6", + "CMT_TOP_NW2A3_6" + ], + [ + "CMT_FIFO_ER1BEG1_8", + "CMT_TOP_ER1BEG1_8" + ], + [ + "CMT_FIFO_SE2A0_6", + "CMT_TOP_SE2A0_6" + ], + [ + "CMT_FIFO_NW4A1_7", + "CMT_TOP_NW4A1_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "CMT_TOP_ICLK_2" + ], + [ + "CMT_FIFO_L_IMUX10_7", + "CMT_TOP_IMUX10_7" + ], + [ + "CMT_FIFO_EE4B0_3", + "CMT_TOP_EE4B0_3" + ], + [ + "CMT_FIFO_NE4C2_2", + "CMT_TOP_NE4C2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_8", + "CMT_TOP_LOGIC_OUTS_L_B19_8" + ], + [ + "CMT_FIFO_L_IMUX47_2", + "CMT_TOP_IMUX47_2" + ], + [ + "CMT_FIFO_EE4B0_9", + "CMT_TOP_EE4B0_9" + ], + [ + "CMT_FIFO_NW4A3_0", + "CMT_TOP_NW4A3_0" + ], + [ + "CMT_FIFO_NW4A0_7", + "CMT_TOP_NW4A0_7" + ], + [ + "CMT_FIFO_NE4C0_2", + "CMT_TOP_NE4C0_2" + ], + [ + "CMT_FIFO_WW2A2_5", + "CMT_TOP_WW2A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_5", + "CMT_TOP_LOGIC_OUTS_L_B2_5" + ], + [ + "CMT_FIFO_WW4B2_1", + "CMT_TOP_WW4B2_1" + ], + [ + "CMT_FIFO_WW2END1_8", + "CMT_TOP_WW2END1_8" + ], + [ + "CMT_FIFO_L_IMUX38_0", + "CMT_TOP_IMUX38_0" + ], + [ + "CMT_FIFO_L_IMUX14_11", + "CMT_TOP_IMUX14_11" + ], + [ + "CMT_FIFO_SE4BEG2_1", + "CMT_TOP_SE4BEG2_1" + ], + [ + "CMT_FIFO_L_IMUX36_6", + "CMT_TOP_IMUX36_6" + ], + [ + "CMT_FIFO_L_IMUX37_11", + "CMT_TOP_IMUX37_11" + ], + [ + "CMT_FIFO_EE4BEG3_11", + "CMT_TOP_EE4BEG3_11" + ], + [ + "CMT_FIFO_WW4A0_4", + "CMT_TOP_WW4A0_4" + ], + [ + "CMT_FIFO_EE4BEG1_5", + "CMT_TOP_EE4BEG1_5" + ], + [ + "CMT_FIFO_EE4BEG2_10", + "CMT_TOP_EE4BEG2_10" + ], + [ + "CMT_FIFO_NE2A0_3", + "CMT_TOP_NE2A0_3" + ], + [ + "CMT_FIFO_NE2A0_1", + "CMT_TOP_NE2A0_1" + ], + [ + "CMT_FIFO_EE4A1_6", + "CMT_TOP_EE4A1_6" + ], + [ + "CMT_FIFO_L_FAN7_10", + "CMT_TOP_FAN7_10" + ], + [ + "CMT_FIFO_L_IMUX37_0", + "CMT_TOP_IMUX37_0" + ], + [ + "CMT_FIFO_SW4A3_7", + "CMT_TOP_SW4A3_7" + ], + [ + "CMT_FIFO_LH11_8", + "CMT_TOP_LH11_8" + ], + [ + "CMT_FIFO_L_BYP5_4", + "CMT_TOP_BYP5_4" + ], + [ + "CMT_FIFO_WL1END0_4", + "CMT_TOP_WL1END0_4" + ], + [ + "CMT_FIFO_L_IMUX40_8", + "CMT_TOP_IMUX40_8" + ], + [ + "CMT_FIFO_LH8_4", + "CMT_TOP_LH8_4" + ], + [ + "CMT_FIFO_EL1BEG2_4", + "CMT_TOP_EL1BEG2_4" + ], + [ + "CMT_FIFO_NE4C0_11", + "CMT_TOP_NE4C0_11" + ], + [ + "CMT_FIFO_EE2A3_7", + "CMT_TOP_EE2A3_7" + ], + [ + "CMT_FIFO_WW2A0_2", + "CMT_TOP_WW2A0_2" + ], + [ + "CMT_FIFO_WW2A3_0", + "CMT_TOP_WW2A3_0" + ], + [ + "CMT_FIFO_WW4A3_7", + "CMT_TOP_WW4A3_7" + ], + [ + "CMT_FIFO_SE2A0_1", + "CMT_TOP_SE2A0_1" + ], + [ + "CMT_FIFO_WW4C1_8", + "CMT_TOP_WW4C1_8" + ], + [ + "CMT_FIFO_NW4END3_1", + "CMT_TOP_NW4END3_1" + ], + [ + "CMT_FIFO_L_IMUX11_7", + "CMT_TOP_IMUX11_7" + ], + [ + "CMT_FIFO_NE4C1_5", + "CMT_TOP_NE4C1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_7", + "CMT_TOP_LOGIC_OUTS_L_B8_7" + ], + [ + "CMT_FIFO_L_IMUX41_6", + "CMT_TOP_IMUX41_6" + ], + [ + "CMT_FIFO_SE4BEG3_5", + "CMT_TOP_SE4BEG3_5" + ], + [ + "CMT_FIFO_L_IMUX6_2", + "CMT_TOP_IMUX6_2" + ], + [ + "CMT_FIFO_L_IMUX12_8", + "CMT_TOP_IMUX12_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_4", + "CMT_TOP_LOGIC_OUTS_L_B22_4" + ], + [ + "CMT_FIFO_SW4A1_11", + "CMT_TOP_SW4A1_11" + ], + [ + "CMT_FIFO_L_FAN5_7", + "CMT_TOP_FAN5_7" + ], + [ + "CMT_FIFO_L_CLK0_0", + "CMT_TOP_CLK0_0" + ], + [ + "CMT_FIFO_L_IMUX20_9", + "CMT_TOP_IMUX20_9" + ], + [ + "CMT_FIFO_L_BYP6_11", + "CMT_TOP_BYP6_11" + ], + [ + "CMT_FIFO_SW4A0_4", + "CMT_TOP_SW4A0_4" + ], + [ + "CMT_FIFO_EE2BEG0_8", + "CMT_TOP_EE2BEG0_8" + ], + [ + "CMT_FIFO_NE4BEG0_8", + "CMT_TOP_NE4BEG0_8" + ], + [ + "CMT_FIFO_LH4_4", + "CMT_TOP_LH4_4" + ], + [ + "CMT_FIFO_L_IMUX34_2", + "CMT_TOP_IMUX34_2" + ], + [ + "CMT_FIFO_L_IMUX0_1", + "CMT_TOP_IMUX0_1" + ], + [ + "CMT_FIFO_NW2A2_8", + "CMT_TOP_NW2A2_8" + ], + [ + "CMT_FIFO_L_IMUX10_2", + "CMT_TOP_IMUX10_2" + ], + [ + "CMT_FIFO_L_FAN0_1", + "CMT_TOP_FAN0_1" + ], + [ + "CMT_FIFO_LH12_4", + "CMT_TOP_LH12_4" + ], + [ + "CMT_FIFO_EL1BEG3_4", + "CMT_TOP_EL1BEG3_4" + ], + [ + "CMT_FIFO_WW4END0_11", + "CMT_TOP_WW4END0_11" + ], + [ + "CMT_FIFO_EE2A3_0", + "CMT_TOP_EE2A3_0" + ], + [ + "CMT_FIFO_L_IMUX12_9", + "CMT_TOP_IMUX12_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_4", + "CMT_TOP_LOGIC_OUTS_L_B18_4" + ], + [ + "CMT_FIFO_EE4C3_0", + "CMT_TOP_EE4C3_0" + ], + [ + "CMT_FIFO_NW4END1_0", + "CMT_TOP_NW4END1_0" + ], + [ + "CMT_FIFO_SE4C0_3", + "CMT_TOP_SE4C0_3" + ], + [ + "CMT_FIFO_L_IMUX2_6", + "CMT_TOP_IMUX2_6" + ], + [ + "CMT_FIFO_WW4END0_6", + "CMT_TOP_WW4END0_6" + ], + [ + "CMT_FIFO_L_FAN6_10", + "CMT_TOP_FAN6_10" + ], + [ + "CMT_FIFO_L_IMUX9_4", + "CMT_TOP_IMUX9_4" + ], + [ + "CMT_FIFO_EE4BEG1_1", + "CMT_TOP_EE4BEG1_1" + ], + [ + "CMT_FIFO_L_IMUX32_9", + "CMT_TOP_IMUX32_9" + ], + [ + "CMT_FIFO_EE2A1_4", + "CMT_TOP_EE2A1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_8", + "CMT_TOP_LOGIC_OUTS_L_B11_8" + ], + [ + "CMT_FIFO_L_IMUX43_4", + "CMT_TOP_IMUX43_4" + ], + [ + "CMT_FIFO_NW4A0_3", + "CMT_TOP_NW4A0_3" + ], + [ + "CMT_FIFO_WW4END3_2", + "CMT_TOP_WW4END3_2" + ], + [ + "CMT_FIFO_NW4END1_2", + "CMT_TOP_NW4END1_2" + ], + [ + "CMT_FIFO_EL1BEG3_9", + "CMT_TOP_EL1BEG3_9" + ], + [ + "CMT_FIFO_L_FAN3_9", + "CMT_TOP_FAN3_9" + ], + [ + "CMT_FIFO_EE4B2_3", + "CMT_TOP_EE4B2_3" + ], + [ + "CMT_FIFO_WW4A1_2", + "CMT_TOP_WW4A1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_11", + "CMT_TOP_LOGIC_OUTS_L_B13_11" + ], + [ + "CMT_FIFO_LH5_10", + "CMT_TOP_LH5_10" + ], + [ + "CMT_FIFO_EE4BEG0_11", + "CMT_TOP_EE4BEG0_11" + ], + [ + "CMT_FIFO_EE4A0_6", + "CMT_TOP_EE4A0_6" + ], + [ + "CMT_FIFO_LH10_5", + "CMT_TOP_LH10_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_6", + "CMT_TOP_LOGIC_OUTS_L_B13_6" + ], + [ + "CMT_FIFO_EE4BEG3_8", + "CMT_TOP_EE4BEG3_8" + ], + [ + "CMT_FIFO_L_IMUX17_4", + "CMT_TOP_IMUX17_4" + ], + [ + "CMT_FIFO_L_IMUX6_4", + "CMT_TOP_IMUX6_4" + ], + [ + "CMT_FIFO_LH11_0", + "CMT_TOP_LH11_0" + ], + [ + "CMT_FIFO_L_IMUX30_0", + "CMT_TOP_IMUX30_0" + ], + [ + "CMT_FIFO_L_FAN6_9", + "CMT_TOP_FAN6_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "CMT_TOP_ICLK_5" + ], + [ + "CMT_FIFO_L_IMUX36_1", + "CMT_TOP_IMUX36_1" + ], + [ + "CMT_FIFO_L_IMUX3_0", + "CMT_TOP_IMUX3_0" + ], + [ + "CMT_FIFO_L_IMUX41_7", + "CMT_TOP_IMUX41_7" + ], + [ + "CMT_FIFO_L_IMUX6_3", + "CMT_TOP_IMUX6_3" + ], + [ + "CMT_FIFO_NE2A3_1", + "CMT_TOP_NE2A3_1" + ], + [ + "CMT_FIFO_ER1BEG3_4", + "CMT_TOP_ER1BEG3_4" + ], + [ + "CMT_FIFO_L_IMUX8_1", + "CMT_TOP_IMUX8_1" + ], + [ + "CMT_FIFO_SE2A0_3", + "CMT_TOP_SE2A0_3" + ], + [ + "CMT_FIFO_EE4B3_2", + "CMT_TOP_EE4B3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_8", + "CMT_TOP_LOGIC_OUTS_L_B5_8" + ], + [ + "CMT_FIFO_NW4END0_1", + "CMT_TOP_NW4END0_1" + ], + [ + "CMT_FIFO_EL1BEG1_10", + "CMT_TOP_EL1BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX5_5", + "CMT_TOP_IMUX5_5" + ], + [ + "CMT_FIFO_L_FAN2_0", + "CMT_TOP_FAN2_0" + ], + [ + "CMT_FIFO_EE4B0_5", + "CMT_TOP_EE4B0_5" + ], + [ + "CMT_FIFO_NW4A2_4", + "CMT_TOP_NW4A2_4" + ], + [ + "CMT_FIFO_NW4END2_0", + "CMT_TOP_NW4END2_0" + ], + [ + "CMT_FIFO_WW4END3_8", + "CMT_TOP_WW4END3_8" + ], + [ + "CMT_FIFO_LH9_4", + "CMT_TOP_LH9_4" + ], + [ + "CMT_FIFO_NE4BEG1_7", + "CMT_TOP_NE4BEG1_7" + ], + [ + "CMT_FIFO_SW4A1_9", + "CMT_TOP_SW4A1_9" + ], + [ + "CMT_FIFO_SE4BEG1_4", + "CMT_TOP_SE4BEG1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_2", + "CMT_TOP_LOGIC_OUTS_L_B7_2" + ], + [ + "CMT_FIFO_L_CTRL1_9", + "CMT_TOP_CTRL1_9" + ], + [ + "CMT_FIFO_L_IMUX13_2", + "CMT_TOP_IMUX13_2" + ], + [ + "CMT_FIFO_WW4A1_11", + "CMT_TOP_WW4A1_11" + ], + [ + "CMT_FIFO_L_IMUX25_1", + "CMT_TOP_IMUX25_1" + ], + [ + "CMT_FIFO_L_FAN4_9", + "CMT_TOP_FAN4_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "CMT_TOP_ICLK_4" + ], + [ + "CMT_FIFO_SW2A1_11", + "CMT_TOP_SW2A1_11" + ], + [ + "CMT_FIFO_EE4BEG3_7", + "CMT_TOP_EE4BEG3_7" + ], + [ + "CMT_FIFO_SE4BEG1_9", + "CMT_TOP_SE4BEG1_9" + ], + [ + "CMT_FIFO_WW4C0_3", + "CMT_TOP_WW4C0_3" + ], + [ + "CMT_FIFO_SW2A1_3", + "CMT_TOP_SW2A1_3" + ], + [ + "CMT_FIFO_SE4C0_5", + "CMT_TOP_SE4C0_5" + ], + [ + "CMT_FIFO_EE2A0_5", + "CMT_TOP_EE2A0_5" + ], + [ + "CMT_FIFO_SE4C1_4", + "CMT_TOP_SE4C1_4" + ], + [ + "CMT_FIFO_EL1BEG0_8", + "CMT_TOP_EL1BEG0_8" + ], + [ + "CMT_FIFO_WW4A1_8", + "CMT_TOP_WW4A1_8" + ], + [ + "CMT_FIFO_NW2A1_7", + "CMT_TOP_NW2A1_7" + ], + [ + "CMT_FIFO_NE2A1_2", + "CMT_TOP_NE2A1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_8", + "CMT_TOP_LOGIC_OUTS_L_B8_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_0", + "CMT_TOP_LOGIC_OUTS_L_B12_0" + ], + [ + "CMT_FIFO_SW4A3_2", + "CMT_TOP_SW4A3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_9", + "CMT_TOP_LOGIC_OUTS_L_B5_9" + ], + [ + "CMT_FIFO_L_CTRL1_3", + "CMT_TOP_CTRL1_3" + ], + [ + "CMT_FIFO_L_IMUX20_11", + "CMT_TOP_IMUX20_11" + ], + [ + "CMT_FIFO_ER1BEG3_0", + "CMT_TOP_ER1BEG3_0" + ], + [ + "CMT_FIFO_NW4A2_8", + "CMT_TOP_NW4A2_8" + ], + [ + "CMT_FIFO_NE4BEG0_2", + "CMT_TOP_NE4BEG0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_7", + "CMT_TOP_LOGIC_OUTS_L_B22_7" + ], + [ + "CMT_FIFO_SW4END0_10", + "CMT_TOP_SW4END0_10" + ], + [ + "CMT_FIFO_EE2A1_7", + "CMT_TOP_EE2A1_7" + ], + [ + "CMT_FIFO_LH9_5", + "CMT_TOP_LH9_5" + ], + [ + "CMT_FIFO_NE4BEG0_6", + "CMT_TOP_NE4BEG0_6" + ], + [ + "CMT_FIFO_EE2BEG2_3", + "CMT_TOP_EE2BEG2_3" + ], + [ + "CMT_FIFO_L_IMUX40_6", + "CMT_TOP_IMUX40_6" + ], + [ + "CMT_FIFO_WW4END1_4", + "CMT_TOP_WW4END1_4" + ], + [ + "CMT_FIFO_NE2A2_9", + "CMT_TOP_NE2A2_9" + ], + [ + "CMT_FIFO_SW2A1_2", + "CMT_TOP_SW2A1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "CMT_TOP_OCLK_8" + ], + [ + "CMT_FIFO_EE2A0_7", + "CMT_TOP_EE2A0_7" + ], + [ + "CMT_FIFO_WW4B0_7", + "CMT_TOP_WW4B0_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "CMT_TOP_OCLKDIV_9" + ], + [ + "CMT_FIFO_L_CTRL1_4", + "CMT_TOP_CTRL1_4" + ], + [ + "CMT_FIFO_L_IMUX37_7", + "CMT_TOP_IMUX37_7" + ], + [ + "CMT_FIFO_WW4A2_4", + "CMT_TOP_WW4A2_4" + ], + [ + "CMT_FIFO_MONITOR_N_6", + "CMT_TOP_MONITOR_N_6" + ], + [ + "CMT_FIFO_WR1END0_8", + "CMT_TOP_WR1END0_8" + ], + [ + "CMT_FIFO_WW2END3_4", + "CMT_TOP_WW2END3_4" + ], + [ + "CMT_FIFO_L_BYP1_2", + "CMT_TOP_BYP1_2" + ], + [ + "CMT_FIFO_L_IMUX46_11", + "CMT_TOP_IMUX46_11" + ], + [ + "CMT_FIFO_EE4BEG0_3", + "CMT_TOP_EE4BEG0_3" + ], + [ + "CMT_FIFO_L_BYP0_9", + "CMT_TOP_BYP0_9" + ], + [ + "CMT_FIFO_EE4BEG0_7", + "CMT_TOP_EE4BEG0_7" + ], + [ + "CMT_FIFO_SE4BEG0_6", + "CMT_TOP_SE4BEG0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_8", + "CMT_TOP_LOGIC_OUTS_L_B18_8" + ], + [ + "CMT_FIFO_L_IMUX27_11", + "CMT_TOP_IMUX27_11" + ], + [ + "CMT_FIFO_SE2A1_6", + "CMT_TOP_SE2A1_6" + ], + [ + "CMT_FIFO_NW4A0_4", + "CMT_TOP_NW4A0_4" + ], + [ + "CMT_FIFO_L_IMUX39_1", + "CMT_TOP_IMUX39_1" + ], + [ + "CMT_FIFO_EE4C2_4", + "CMT_TOP_EE4C2_4" + ], + [ + "CMT_FIFO_NE2A0_5", + "CMT_TOP_NE2A0_5" + ], + [ + "CMT_FIFO_L_CLK0_5", + "CMT_TOP_CLK0_5" + ], + [ + "CMT_FIFO_L_IMUX24_0", + "CMT_TOP_IMUX24_0" + ], + [ + "CMT_FIFO_EE4A2_5", + "CMT_TOP_EE4A2_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "CMT_TOP_OCLK_6" + ], + [ + "CMT_FIFO_L_IMUX8_7", + "CMT_TOP_IMUX8_7" + ], + [ + "CMT_FIFO_L_IMUX36_0", + "CMT_TOP_IMUX36_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_10", + "CMT_TOP_LOGIC_OUTS_L_B11_10" + ], + [ + "CMT_FIFO_L_IMUX39_2", + "CMT_TOP_IMUX39_2" + ], + [ + "CMT_FIFO_L_IMUX9_6", + "CMT_TOP_IMUX9_6" + ], + [ + "CMT_FIFO_NW4A1_4", + "CMT_TOP_NW4A1_4" + ], + [ + "CMT_FIFO_EE4C1_2", + "CMT_TOP_EE4C1_2" + ], + [ + "CMT_FIFO_L_IMUX44_0", + "CMT_TOP_IMUX44_0" + ], + [ + "CMT_FIFO_L_IMUX14_6", + "CMT_TOP_IMUX14_6" + ], + [ + "CMT_FIFO_L_IMUX16_10", + "CMT_TOP_IMUX16_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_5", + "CMT_TOP_LOGIC_OUTS_L_B19_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_4", + "CMT_TOP_LOGIC_OUTS_L_B15_4" + ], + [ + "CMT_FIFO_EE4A0_3", + "CMT_TOP_EE4A0_3" + ], + [ + "CMT_FIFO_L_FAN6_2", + "CMT_TOP_FAN6_2" + ], + [ + "CMT_FIFO_WW4B2_11", + "CMT_TOP_WW4B2_11" + ], + [ + "CMT_FIFO_L_BYP0_11", + "CMT_TOP_BYP0_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "CMT_TOP_ICLKDIV_0" + ], + [ + "CMT_FIFO_WW4C2_0", + "CMT_TOP_WW4C2_0" + ], + [ + "CMT_FIFO_L_IMUX28_1", + "CMT_TOP_IMUX28_1" + ], + [ + "CMT_FIFO_WW4B1_6", + "CMT_TOP_WW4B1_6" + ], + [ + "CMT_FIFO_EE4BEG0_4", + "CMT_TOP_EE4BEG0_4" + ], + [ + "CMT_FIFO_EE2A2_3", + "CMT_TOP_EE2A2_3" + ], + [ + "CMT_FIFO_EE4BEG1_9", + "CMT_TOP_EE4BEG1_9" + ], + [ + "CMT_FIFO_SE2A1_2", + "CMT_TOP_SE2A1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "CMT_TOP_ICLK_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_1", + "CMT_TOP_LOGIC_OUTS_L_B1_1" + ], + [ + "CMT_FIFO_WR1END2_6", + "CMT_TOP_WR1END2_6" + ], + [ + "CMT_FIFO_NW4END0_9", + "CMT_TOP_NW4END0_9" + ], + [ + "CMT_FIFO_EE4C2_3", + "CMT_TOP_EE4C2_3" + ], + [ + "CMT_FIFO_SE4C0_7", + "CMT_TOP_SE4C0_7" + ], + [ + "CMT_FIFO_SW4A3_6", + "CMT_TOP_SW4A3_6" + ], + [ + "CMT_FIFO_L_IMUX15_7", + "CMT_TOP_IMUX15_7" + ], + [ + "CMT_FIFO_L_FAN0_9", + "CMT_TOP_FAN0_9" + ], + [ + "CMT_FIFO_L_IMUX35_7", + "CMT_TOP_IMUX35_7" + ], + [ + "CMT_FIFO_ER1BEG0_5", + "CMT_TOP_ER1BEG0_5" + ], + [ + "CMT_FIFO_L_IMUX6_0", + "CMT_TOP_IMUX6_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_4", + "CMT_TOP_LOGIC_OUTS_L_B0_4" + ], + [ + "CMT_FIFO_NE4C0_6", + "CMT_TOP_NE4C0_6" + ], + [ + "CMT_FIFO_EE2A0_8", + "CMT_TOP_EE2A0_8" + ], + [ + "CMT_FIFO_EE4BEG3_4", + "CMT_TOP_EE4BEG3_4" + ], + [ + "CMT_FIFO_NE2A3_3", + "CMT_TOP_NE2A3_3" + ], + [ + "CMT_FIFO_SW2A3_4", + "CMT_TOP_SW2A3_4" + ], + [ + "CMT_FIFO_LH6_0", + "CMT_TOP_LH6_0" + ], + [ + "CMT_FIFO_EE2BEG3_0", + "CMT_TOP_EE2BEG3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_0", + "CMT_TOP_LOGIC_OUTS_L_B1_0" + ], + [ + "CMT_FIFO_SW2A2_7", + "CMT_TOP_SW2A2_7" + ], + [ + "CMT_FIFO_EE4B2_11", + "CMT_TOP_EE4B2_11" + ], + [ + "CMT_FIFO_WW4END2_6", + "CMT_TOP_WW4END2_6" + ], + [ + "CMT_FIFO_L_PHASER_RDENABLE", + "CMT_PLL_PHASER_RDENABLE_TOFIFO" + ], + [ + "CMT_FIFO_WW4B3_10", + "CMT_TOP_WW4B3_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_1", + "CMT_TOP_LOGIC_OUTS_L_B5_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_5", + "CMT_TOP_LOGIC_OUTS_L_B9_5" + ], + [ + "CMT_FIFO_SW2A2_1", + "CMT_TOP_SW2A2_1" + ], + [ + "CMT_FIFO_EE2A1_11", + "CMT_TOP_EE2A1_11" + ], + [ + "CMT_FIFO_L_IMUX3_6", + "CMT_TOP_IMUX3_6" + ], + [ + "CMT_FIFO_NE4BEG2_5", + "CMT_TOP_NE4BEG2_5" + ], + [ + "CMT_FIFO_L_FAN5_5", + "CMT_TOP_FAN5_5" + ], + [ + "CMT_FIFO_NE4BEG0_7", + "CMT_TOP_NE4BEG0_7" + ], + [ + "CMT_FIFO_L_IMUX14_3", + "CMT_TOP_IMUX14_3" + ], + [ + "CMT_FIFO_EE2BEG0_10", + "CMT_TOP_EE2BEG0_10" + ], + [ + "CMT_FIFO_L_BYP1_8", + "CMT_TOP_BYP1_8" + ], + [ + "CMT_FIFO_L_IMUX19_4", + "CMT_TOP_IMUX19_4" + ], + [ + "CMT_FIFO_LH4_2", + "CMT_TOP_LH4_2" + ], + [ + "CMT_FIFO_WW2A1_8", + "CMT_TOP_WW2A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6" + ], + [ + "CMT_FIFO_WL1END3_2", + "CMT_TOP_WL1END3_2" + ], + [ + "CMT_FIFO_L_IMUX29_1", + "CMT_TOP_IMUX29_1" + ], + [ + "CMT_FIFO_SW4A1_0", + "CMT_TOP_SW4A1_0" + ], + [ + "CMT_FIFO_EE2A3_8", + "CMT_TOP_EE2A3_8" + ], + [ + "CMT_FIFO_L_CLK1_0", + "CMT_TOP_CLK1_0" + ], + [ + "CMT_FIFO_L_IMUX26_7", + "CMT_TOP_IMUX26_7" + ], + [ + "CMT_FIFO_EE4C1_11", + "CMT_TOP_EE4C1_11" + ], + [ + "CMT_FIFO_NE2A0_7", + "CMT_TOP_NE2A0_7" + ], + [ + "CMT_FIFO_LH6_9", + "CMT_TOP_LH6_9" + ], + [ + "CMT_FIFO_NW2A3_4", + "CMT_TOP_NW2A3_4" + ], + [ + "CMT_FIFO_EE2A3_11", + "CMT_TOP_EE2A3_11" + ], + [ + "CMT_FIFO_L_IMUX3_8", + "CMT_TOP_IMUX3_8" + ], + [ + "CMT_FIFO_NE4C2_5", + "CMT_TOP_NE4C2_5" + ], + [ + "CMT_FIFO_L_BYP2_1", + "CMT_TOP_BYP2_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "CMT_TOP_OCLK_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_2", + "CMT_TOP_LOGIC_OUTS_L_B0_2" + ], + [ + "CMT_FIFO_L_IMUX28_9", + "CMT_TOP_IMUX28_9" + ], + [ + "CMT_FIFO_L_IMUX27_4", + "CMT_TOP_IMUX27_4" + ], + [ + "CMT_FIFO_SE4BEG3_1", + "CMT_TOP_SE4BEG3_1" + ], + [ + "CMT_FIFO_NE4C2_9", + "CMT_TOP_NE4C2_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "CMT_TOP_OCLK_1" + ], + [ + "CMT_FIFO_NE4BEG3_11", + "CMT_TOP_NE4BEG3_11" + ], + [ + "CMT_FIFO_ER1BEG1_9", + "CMT_TOP_ER1BEG1_9" + ], + [ + "CMT_FIFO_LH3_4", + "CMT_TOP_LH3_4" + ], + [ + "CMT_FIFO_LH5_7", + "CMT_TOP_LH5_7" + ], + [ + "CMT_FIFO_L_FAN2_7", + "CMT_TOP_FAN2_7" + ], + [ + "CMT_FIFO_WW2END2_3", + "CMT_TOP_WW2END2_3" + ], + [ + "CMT_FIFO_L_IMUX25_4", + "CMT_TOP_IMUX25_4" + ], + [ + "CMT_FIFO_L_IMUX40_1", + "CMT_TOP_IMUX40_1" + ], + [ + "CMT_FIFO_WL1END0_0", + "CMT_TOP_WL1END0_0" + ], + [ + "CMT_FIFO_L_BYP2_7", + "CMT_TOP_BYP2_7" + ], + [ + "CMT_FIFO_L_CTRL1_8", + "CMT_TOP_CTRL1_8" + ], + [ + "CMT_FIFO_EE4B3_3", + "CMT_TOP_EE4B3_3" + ], + [ + "CMT_FIFO_L_IMUX0_11", + "CMT_TOP_IMUX0_11" + ], + [ + "CMT_FIFO_WW2A1_5", + "CMT_TOP_WW2A1_5" + ], + [ + "CMT_FIFO_WL1END0_1", + "CMT_TOP_WL1END0_1" + ], + [ + "CMT_FIFO_L_BYP4_8", + "CMT_TOP_BYP4_8" + ], + [ + "CMT_FIFO_NW4A1_9", + "CMT_TOP_NW4A1_9" + ], + [ + "CMT_FIFO_NW4END1_9", + "CMT_TOP_NW4END1_9" + ], + [ + "CMT_FIFO_WR1END2_1", + "CMT_TOP_WR1END2_1" + ], + [ + "CMT_FIFO_EE4A3_3", + "CMT_TOP_EE4A3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_0", + "CMT_TOP_LOGIC_OUTS_L_B20_0" + ], + [ + "CMT_FIFO_SE2A2_6", + "CMT_TOP_SE2A2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_11", + "CMT_TOP_LOGIC_OUTS_L_B21_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_1", + "CMT_TOP_LOGIC_OUTS_L_B13_1" + ], + [ + "CMT_FIFO_L_IMUX6_5", + "CMT_TOP_IMUX6_5" + ], + [ + "CMT_FIFO_WR1END2_10", + "CMT_TOP_WR1END2_10" + ], + [ + "CMT_FIFO_LH9_1", + "CMT_TOP_LH9_1" + ], + [ + "CMT_FIFO_NW4A3_9", + "CMT_TOP_NW4A3_9" + ], + [ + "CMT_FIFO_SE2A3_6", + "CMT_TOP_SE2A3_6" + ], + [ + "CMT_FIFO_L_IMUX44_4", + "CMT_TOP_IMUX44_4" + ], + [ + "CMT_FIFO_L_IMUX35_6", + "CMT_TOP_IMUX35_6" + ], + [ + "CMT_FIFO_WR1END3_8", + "CMT_TOP_WR1END3_8" + ], + [ + "CMT_FIFO_NW2A0_11", + "CMT_TOP_NW2A0_11" + ], + [ + "CMT_FIFO_L_IMUX33_9", + "CMT_TOP_IMUX33_9" + ], + [ + "CMT_FIFO_EE2BEG1_9", + "CMT_TOP_EE2BEG1_9" + ], + [ + "CMT_FIFO_SE2A3_7", + "CMT_TOP_SE2A3_7" + ], + [ + "CMT_FIFO_EE4B3_4", + "CMT_TOP_EE4B3_4" + ], + [ + "CMT_FIFO_L_IMUX19_7", + "CMT_TOP_IMUX19_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "CMT_TOP_OCLK_0" + ], + [ + "CMT_FIFO_L_IMUX6_8", + "CMT_TOP_IMUX6_8" + ], + [ + "CMT_FIFO_L_CTRL0_4", + "CMT_TOP_CTRL0_4" + ], + [ + "CMT_FIFO_L_IMUX29_4", + "CMT_TOP_IMUX29_4" + ], + [ + "CMT_FIFO_WW4A1_10", + "CMT_TOP_WW4A1_10" + ], + [ + "CMT_FIFO_NE2A1_3", + "CMT_TOP_NE2A1_3" + ], + [ + "CMT_FIFO_L_IMUX46_0", + "CMT_TOP_IMUX46_0" + ], + [ + "CMT_FIFO_WW4B3_8", + "CMT_TOP_WW4B3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6" + ], + [ + "CMT_FIFO_L_IMUX35_8", + "CMT_TOP_IMUX35_8" + ], + [ + "CMT_FIFO_SW4END0_0", + "CMT_TOP_SW4END0_0" + ], + [ + "CMT_FIFO_EE4BEG2_0", + "CMT_TOP_EE4BEG2_0" + ], + [ + "CMT_FIFO_MONITOR_N_10", + "CMT_TOP_MONITOR_N_10" + ], + [ + "CMT_FIFO_L_FAN3_7", + "CMT_TOP_FAN3_7" + ], + [ + "CMT_FIFO_WW2END2_2", + "CMT_TOP_WW2END2_2" + ], + [ + "CMT_FIFO_EE4A1_8", + "CMT_TOP_EE4A1_8" + ], + [ + "CMT_FIFO_NW4END2_6", + "CMT_TOP_NW4END2_6" + ], + [ + "CMT_FIFO_EE2A0_11", + "CMT_TOP_EE2A0_11" + ], + [ + "CMT_FIFO_EE4B1_8", + "CMT_TOP_EE4B1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_1", + "CMT_TOP_LOGIC_OUTS_L_B22_1" + ], + [ + "CMT_FIFO_LH2_5", + "CMT_TOP_LH2_5" + ], + [ + "CMT_FIFO_L_IMUX39_5", + "CMT_TOP_IMUX39_5" + ], + [ + "CMT_FIFO_SW2A3_10", + "CMT_TOP_SW2A3_10" + ], + [ + "CMT_FIFO_WW4END0_8", + "CMT_TOP_WW4END0_8" + ], + [ + "CMT_FIFO_SE2A3_8", + "CMT_TOP_SE2A3_8" + ], + [ + "CMT_FIFO_L_IMUX29_7", + "CMT_TOP_IMUX29_7" + ], + [ + "CMT_FIFO_L_CTRL0_7", + "CMT_TOP_CTRL0_7" + ], + [ + "CMT_FIFO_L_BYP1_5", + "CMT_TOP_BYP1_5" + ], + [ + "CMT_FIFO_NE2A0_11", + "CMT_TOP_NE2A0_11" + ], + [ + "CMT_FIFO_L_IMUX20_8", + "CMT_TOP_IMUX20_8" + ], + [ + "CMT_FIFO_WR1END1_0", + "CMT_TOP_WR1END1_0" + ], + [ + "CMT_FIFO_EE4BEG1_4", + "CMT_TOP_EE4BEG1_4" + ], + [ + "CMT_FIFO_WW2END2_10", + "CMT_TOP_WW2END2_10" + ], + [ + "CMT_FIFO_L_CTRL0_6", + "CMT_TOP_CTRL0_6" + ], + [ + "CMT_FIFO_WW4C0_4", + "CMT_TOP_WW4C0_4" + ], + [ + "CMT_FIFO_NE2A2_8", + "CMT_TOP_NE2A2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_0", + "CMT_TOP_LOGIC_OUTS_L_B4_0" + ], + [ + "CMT_FIFO_SW4END0_3", + "CMT_TOP_SW4END0_3" + ], + [ + "CMT_FIFO_L_IMUX4_6", + "CMT_TOP_IMUX4_6" + ], + [ + "CMT_FIFO_SW4END0_11", + "CMT_TOP_SW4END0_11" + ], + [ + "CMT_FIFO_EE2A0_1", + "CMT_TOP_EE2A0_1" + ], + [ + "CMT_FIFO_EE4B1_2", + "CMT_TOP_EE4B1_2" + ], + [ + "CMT_FIFO_NE4C3_0", + "CMT_TOP_NE4C3_0" + ], + [ + "CMT_FIFO_L_IMUX40_5", + "CMT_TOP_IMUX40_5" + ], + [ + "CMT_FIFO_WW2END1_2", + "CMT_TOP_WW2END1_2" + ], + [ + "CMT_FIFO_WW2A0_0", + "CMT_TOP_WW2A0_0" + ], + [ + "CMT_FIFO_EE2BEG1_11", + "CMT_TOP_EE2BEG1_11" + ], + [ + "CMT_FIFO_EE4A1_2", + "CMT_TOP_EE4A1_2" + ], + [ + "CMT_FIFO_ER1BEG2_3", + "CMT_TOP_ER1BEG2_3" + ], + [ + "CMT_FIFO_L_IMUX33_2", + "CMT_TOP_IMUX33_2" + ], + [ + "CMT_FIFO_SW2A2_8", + "CMT_TOP_SW2A2_8" + ], + [ + "CMT_FIFO_L_IMUX13_0", + "CMT_TOP_IMUX13_0" + ], + [ + "CMT_FIFO_EE2BEG1_1", + "CMT_TOP_EE2BEG1_1" + ], + [ + "CMT_FIFO_WW4C3_0", + "CMT_TOP_WW4C3_0" + ], + [ + "CMT_FIFO_WL1END1_1", + "CMT_TOP_WL1END1_1" + ], + [ + "CMT_FIFO_L_IMUX18_3", + "CMT_TOP_IMUX18_3" + ], + [ + "CMT_FIFO_WL1END0_9", + "CMT_TOP_WL1END0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_11", + "CMT_TOP_LOGIC_OUTS_L_B4_11" + ], + [ + "CMT_FIFO_L_IMUX44_3", + "CMT_TOP_IMUX44_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_2", + "CMT_TOP_LOGIC_OUTS_L_B19_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5" + ], + [ + "CMT_FIFO_L_IMUX23_7", + "CMT_TOP_IMUX23_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_6", + "CMT_TOP_LOGIC_OUTS_L_B19_6" + ], + [ + "CMT_FIFO_L_IMUX2_0", + "CMT_TOP_IMUX2_0" + ], + [ + "CMT_FIFO_L_IMUX35_9", + "CMT_TOP_IMUX35_9" + ], + [ + "CMT_FIFO_WR1END1_7", + "CMT_TOP_WR1END1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_9", + "CMT_TOP_LOGIC_OUTS_L_B17_9" + ], + [ + "CMT_FIFO_L_IMUX39_8", + "CMT_TOP_IMUX39_8" + ], + [ + "CMT_FIFO_WR1END3_4", + "CMT_TOP_WR1END3_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "CMT_TOP_ICLKDIV_9" + ], + [ + "CMT_FIFO_NE4BEG3_1", + "CMT_TOP_NE4BEG3_1" + ], + [ + "CMT_FIFO_WL1END2_6", + "CMT_TOP_WL1END2_6" + ], + [ + "CMT_FIFO_SE2A3_11", + "CMT_TOP_SE2A3_11" + ], + [ + "CMT_FIFO_NW4A3_7", + "CMT_TOP_NW4A3_7" + ], + [ + "CMT_FIFO_L_BYP0_7", + "CMT_TOP_BYP0_7" + ], + [ + "CMT_FIFO_SW2A0_3", + "CMT_TOP_SW2A0_3" + ], + [ + "CMT_FIFO_EE2BEG2_8", + "CMT_TOP_EE2BEG2_8" + ], + [ + "CMT_FIFO_EE2A1_6", + "CMT_TOP_EE2A1_6" + ], + [ + "CMT_FIFO_EE4C1_7", + "CMT_TOP_EE4C1_7" + ], + [ + "CMT_FIFO_WW4A0_10", + "CMT_TOP_WW4A0_10" + ], + [ + "CMT_FIFO_WR1END2_9", + "CMT_TOP_WR1END2_9" + ], + [ + "CMT_FIFO_WW4C3_6", + "CMT_TOP_WW4C3_6" + ], + [ + "CMT_FIFO_WW4END2_7", + "CMT_TOP_WW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX6_11", + "CMT_TOP_IMUX6_11" + ], + [ + "CMT_FIFO_L_IMUX10_6", + "CMT_TOP_IMUX10_6" + ], + [ + "CMT_FIFO_LH9_7", + "CMT_TOP_LH9_7" + ], + [ + "CMT_FIFO_L_CTRL1_0", + "CMT_TOP_CTRL1_0" + ], + [ + "CMT_FIFO_L_IMUX1_3", + "CMT_TOP_IMUX1_3" + ], + [ + "CMT_FIFO_WW2END3_10", + "CMT_TOP_WW2END3_10" + ], + [ + "CMT_FIFO_WW2A2_1", + "CMT_TOP_WW2A2_1" + ], + [ + "CMT_FIFO_L_CLK1_6", + "CMT_TOP_CLK1_6" + ], + [ + "CMT_FIFO_LH8_9", + "CMT_TOP_LH8_9" + ], + [ + "CMT_FIFO_L_IMUX46_5", + "CMT_TOP_IMUX46_5" + ], + [ + "CMT_FIFO_WW4A1_4", + "CMT_TOP_WW4A1_4" + ], + [ + "CMT_FIFO_L_IMUX25_11", + "CMT_TOP_IMUX25_11" + ], + [ + "CMT_FIFO_L_IMUX2_9", + "CMT_TOP_IMUX2_9" + ], + [ + "CMT_FIFO_SE4C3_0", + "CMT_TOP_SE4C3_0" + ], + [ + "CMT_FIFO_WW4C2_4", + "CMT_TOP_WW4C2_4" + ], + [ + "CMT_FIFO_WW4C1_6", + "CMT_TOP_WW4C1_6" + ], + [ + "CMT_FIFO_L_IMUX38_1", + "CMT_TOP_IMUX38_1" + ], + [ + "CMT_FIFO_MONITOR_P_0", + "CMT_TOP_MONITOR_P_0" + ], + [ + "CMT_FIFO_WL1END1_4", + "CMT_TOP_WL1END1_4" + ], + [ + "CMT_FIFO_EE4A2_0", + "CMT_TOP_EE4A2_0" + ], + [ + "CMT_FIFO_EL1BEG3_10", + "CMT_TOP_EL1BEG3_10" + ], + [ + "CMT_FIFO_L_IMUX27_0", + "CMT_TOP_IMUX27_0" + ], + [ + "CMT_FIFO_NE4C0_7", + "CMT_TOP_NE4C0_7" + ], + [ + "CMT_FIFO_ER1BEG1_2", + "CMT_TOP_ER1BEG1_2" + ], + [ + "CMT_FIFO_NE2A1_10", + "CMT_TOP_NE2A1_10" + ], + [ + "CMT_FIFO_SE4BEG3_6", + "CMT_TOP_SE4BEG3_6" + ], + [ + "CMT_FIFO_WL1END3_11", + "CMT_TOP_WL1END3_11" + ], + [ + "CMT_FIFO_SW4A1_6", + "CMT_TOP_SW4A1_6" + ], + [ + "CMT_FIFO_EE4A3_9", + "CMT_TOP_EE4A3_9" + ], + [ + "CMT_FIFO_EL1BEG0_2", + "CMT_TOP_EL1BEG0_2" + ], + [ + "CMT_FIFO_WW4C3_3", + "CMT_TOP_WW4C3_3" + ], + [ + "CMT_FIFO_SW4END0_6", + "CMT_TOP_SW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX41_4", + "CMT_TOP_IMUX41_4" + ], + [ + "CMT_FIFO_L_FAN3_3", + "CMT_TOP_FAN3_3" + ], + [ + "CMT_FIFO_WW4C2_1", + "CMT_TOP_WW4C2_1" + ], + [ + "CMT_FIFO_L_BYP3_2", + "CMT_TOP_BYP3_2" + ], + [ + "CMT_FIFO_L_IMUX8_3", + "CMT_TOP_IMUX8_3" + ], + [ + "CMT_FIFO_LH6_11", + "CMT_TOP_LH6_11" + ], + [ + "CMT_FIFO_EE2A2_9", + "CMT_TOP_EE2A2_9" + ], + [ + "CMT_FIFO_WW2A0_7", + "CMT_TOP_WW2A0_7" + ], + [ + "CMT_FIFO_WW4END2_5", + "CMT_TOP_WW4END2_5" + ], + [ + "CMT_FIFO_WW2END0_7", + "CMT_TOP_WW2END0_7" + ], + [ + "CMT_FIFO_EE4B0_1", + "CMT_TOP_EE4B0_1" + ], + [ + "CMT_FIFO_L_IMUX38_10", + "CMT_TOP_IMUX38_10" + ], + [ + "CMT_FIFO_NE2A2_10", + "CMT_TOP_NE2A2_10" + ], + [ + "CMT_FIFO_EE2A3_2", + "CMT_TOP_EE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX4_3", + "CMT_TOP_IMUX4_3" + ], + [ + "CMT_FIFO_L_FAN2_6", + "CMT_TOP_FAN2_6" + ], + [ + "CMT_FIFO_WW4END0_2", + "CMT_TOP_WW4END0_2" + ], + [ + "CMT_FIFO_NE4BEG0_3", + "CMT_TOP_NE4BEG0_3" + ], + [ + "CMT_FIFO_SW4END3_8", + "CMT_TOP_SW4END3_8" + ], + [ + "CMT_FIFO_LH6_7", + "CMT_TOP_LH6_7" + ], + [ + "CMT_FIFO_WW2END0_6", + "CMT_TOP_WW2END0_6" + ], + [ + "CMT_FIFO_NW4A2_1", + "CMT_TOP_NW4A2_1" + ], + [ + "CMT_FIFO_WW2A3_4", + "CMT_TOP_WW2A3_4" + ], + [ + "CMT_FIFO_SW4A0_8", + "CMT_TOP_SW4A0_8" + ], + [ + "CMT_FIFO_L_IMUX19_6", + "CMT_TOP_IMUX19_6" + ], + [ + "CMT_FIFO_EL1BEG3_0", + "CMT_TOP_EL1BEG3_0" + ], + [ + "CMT_FIFO_LH3_1", + "CMT_TOP_LH3_1" + ], + [ + "CMT_FIFO_L_IMUX10_1", + "CMT_TOP_IMUX10_1" + ], + [ + "CMT_FIFO_WW4END1_10", + "CMT_TOP_WW4END1_10" + ], + [ + "CMT_FIFO_L_IMUX43_6", + "CMT_TOP_IMUX43_6" + ], + [ + "CMT_FIFO_L_FAN2_4", + "CMT_TOP_FAN2_4" + ], + [ + "CMT_FIFO_WR1END2_11", + "CMT_TOP_WR1END2_11" + ], + [ + "CMT_FIFO_NW4END0_11", + "CMT_TOP_NW4END0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_2", + "CMT_TOP_LOGIC_OUTS_L_B2_2" + ], + [ + "CMT_FIFO_SE4BEG2_11", + "CMT_TOP_SE4BEG2_11" + ], + [ + "CMT_FIFO_EE2A3_3", + "CMT_TOP_EE2A3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_5", + "CMT_TOP_LOGIC_OUTS_L_B22_5" + ], + [ + "CMT_FIFO_SW4A0_0", + "CMT_TOP_SW4A0_0" + ], + [ + "CMT_FIFO_NE4BEG3_7", + "CMT_TOP_NE4BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX9_1", + "CMT_TOP_IMUX9_1" + ], + [ + "CMT_FIFO_NW4A3_2", + "CMT_TOP_NW4A3_2" + ], + [ + "CMT_FIFO_NW4A0_1", + "CMT_TOP_NW4A0_1" + ], + [ + "CMT_FIFO_WW4END0_1", + "CMT_TOP_WW4END0_1" + ], + [ + "CMT_FIFO_L_IMUX37_9", + "CMT_TOP_IMUX37_9" + ], + [ + "CMT_FIFO_L_IMUX7_7", + "CMT_TOP_IMUX7_7" + ], + [ + "CMT_FIFO_NE2A2_6", + "CMT_TOP_NE2A2_6" + ], + [ + "CMT_FIFO_EE2A1_10", + "CMT_TOP_EE2A1_10" + ], + [ + "CMT_FIFO_NE4BEG2_3", + "CMT_TOP_NE4BEG2_3" + ], + [ + "CMT_FIFO_WW2END2_6", + "CMT_TOP_WW2END2_6" + ], + [ + "CMT_FIFO_SW4A2_9", + "CMT_TOP_SW4A2_9" + ], + [ + "CMT_FIFO_L_IMUX1_6", + "CMT_TOP_IMUX1_6" + ], + [ + "CMT_FIFO_L_IMUX18_7", + "CMT_TOP_IMUX18_7" + ], + [ + "CMT_FIFO_WR1END2_2", + "CMT_TOP_WR1END2_2" + ], + [ + "CMT_FIFO_L_IMUX41_3", + "CMT_TOP_IMUX41_3" + ], + [ + "CMT_FIFO_L_IMUX17_9", + "CMT_TOP_IMUX17_9" + ], + [ + "CMT_FIFO_EE4BEG3_5", + "CMT_TOP_EE4BEG3_5" + ], + [ + "CMT_FIFO_NW2A0_1", + "CMT_TOP_NW2A0_1" + ], + [ + "CMT_FIFO_EE4A1_11", + "CMT_TOP_EE4A1_11" + ], + [ + "CMT_FIFO_SE2A0_11", + "CMT_TOP_SE2A0_11" + ], + [ + "CMT_FIFO_L_IMUX10_11", + "CMT_TOP_IMUX10_11" + ], + [ + "CMT_FIFO_L_IMUX47_5", + "CMT_TOP_IMUX47_5" + ], + [ + "CMT_FIFO_L_IMUX42_2", + "CMT_TOP_IMUX42_2" + ], + [ + "CMT_FIFO_L_IMUX36_11", + "CMT_TOP_IMUX36_11" + ], + [ + "CMT_FIFO_LH1_0", + "CMT_TOP_LH1_0" + ], + [ + "CMT_FIFO_L_IMUX5_0", + "CMT_TOP_IMUX5_0" + ], + [ + "CMT_FIFO_L_IMUX17_10", + "CMT_TOP_IMUX17_10" + ], + [ + "CMT_FIFO_WW4C1_2", + "CMT_TOP_WW4C1_2" + ], + [ + "CMT_FIFO_WR1END1_4", + "CMT_TOP_WR1END1_4" + ], + [ + "CMT_FIFO_WW4C3_1", + "CMT_TOP_WW4C3_1" + ], + [ + "CMT_FIFO_EE4C1_5", + "CMT_TOP_EE4C1_5" + ], + [ + "CMT_FIFO_LH5_6", + "CMT_TOP_LH5_6" + ], + [ + "CMT_FIFO_EL1BEG2_5", + "CMT_TOP_EL1BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX3_4", + "CMT_TOP_IMUX3_4" + ], + [ + "CMT_FIFO_L_IMUX21_8", + "CMT_TOP_IMUX21_8" + ], + [ + "CMT_FIFO_L_FAN2_2", + "CMT_TOP_FAN2_2" + ], + [ + "CMT_FIFO_L_IMUX44_6", + "CMT_TOP_IMUX44_6" + ], + [ + "CMT_FIFO_L_BYP3_10", + "CMT_TOP_BYP3_10" + ], + [ + "CMT_FIFO_LH11_6", + "CMT_TOP_LH11_6" + ], + [ + "CMT_FIFO_NE4BEG0_9", + "CMT_TOP_NE4BEG0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_9", + "CMT_TOP_LOGIC_OUTS_L_B12_9" + ], + [ + "CMT_FIFO_L_IMUX7_6", + "CMT_TOP_IMUX7_6" + ], + [ + "CMT_FIFO_EE2A2_5", + "CMT_TOP_EE2A2_5" + ], + [ + "CMT_FIFO_LH11_1", + "CMT_TOP_LH11_1" + ], + [ + "CMT_FIFO_NW2A2_2", + "CMT_TOP_NW2A2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_0" + ], + [ + "CMT_FIFO_SW4A1_2", + "CMT_TOP_SW4A1_2" + ], + [ + "CMT_FIFO_EE4C0_0", + "CMT_TOP_EE4C0_0" + ], + [ + "CMT_FIFO_L_IMUX35_0", + "CMT_TOP_IMUX35_0" + ], + [ + "CMT_FIFO_EE2A3_9", + "CMT_TOP_EE2A3_9" + ], + [ + "CMT_FIFO_L_FAN3_10", + "CMT_TOP_FAN3_10" + ], + [ + "CMT_FIFO_L_BYP4_7", + "CMT_TOP_BYP4_7" + ], + [ + "CMT_FIFO_L_IMUX28_3", + "CMT_TOP_IMUX28_3" + ], + [ + "CMT_FIFO_EE2A0_0", + "CMT_TOP_EE2A0_0" + ], + [ + "CMT_FIFO_L_IMUX21_10", + "CMT_TOP_IMUX21_10" + ], + [ + "CMT_FIFO_SW4END2_5", + "CMT_TOP_SW4END2_5" + ], + [ + "CMT_FIFO_MONITOR_P_2", + "CMT_TOP_MONITOR_P_2" + ], + [ + "CMT_FIFO_SW2A0_8", + "CMT_TOP_SW2A0_8" + ], + [ + "CMT_FIFO_L_IMUX45_7", + "CMT_TOP_IMUX45_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_9", + "CMT_TOP_LOGIC_OUTS_L_B4_9" + ], + [ + "CMT_FIFO_SE4BEG1_3", + "CMT_TOP_SE4BEG1_3" + ], + [ + "CMT_FIFO_WR1END2_0", + "CMT_TOP_WR1END2_0" + ], + [ + "CMT_FIFO_L_CLK1_11", + "CMT_TOP_CLK1_11" + ], + [ + "CMT_FIFO_EE4A3_10", + "CMT_TOP_EE4A3_10" + ], + [ + "CMT_FIFO_SE4BEG2_8", + "CMT_TOP_SE4BEG2_8" + ], + [ + "CMT_FIFO_L_PHASER_WRCLK", + "CMT_PLL_PHASER_WRCLK_TOFIFO" + ], + [ + "CMT_FIFO_L_IMUX24_3", + "CMT_TOP_IMUX24_3" + ], + [ + "CMT_FIFO_EE2BEG1_4", + "CMT_TOP_EE2BEG1_4" + ], + [ + "CMT_FIFO_WW4B2_0", + "CMT_TOP_WW4B2_0" + ], + [ + "CMT_FIFO_NE4C0_3", + "CMT_TOP_NE4C0_3" + ], + [ + "CMT_FIFO_L_BYP7_7", + "CMT_TOP_BYP7_7" + ], + [ + "CMT_FIFO_L_FAN7_1", + "CMT_TOP_FAN7_1" + ], + [ + "CMT_FIFO_SW4A3_8", + "CMT_TOP_SW4A3_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "CMT_TOP_ICLK_8" + ], + [ + "CMT_FIFO_EE2A2_4", + "CMT_TOP_EE2A2_4" + ], + [ + "CMT_FIFO_LH6_10", + "CMT_TOP_LH6_10" + ], + [ + "CMT_FIFO_NE2A1_11", + "CMT_TOP_NE2A1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_4" + ], + [ + "CMT_FIFO_L_IMUX20_6", + "CMT_TOP_IMUX20_6" + ], + [ + "CMT_FIFO_L_IMUX14_9", + "CMT_TOP_IMUX14_9" + ], + [ + "CMT_FIFO_NW2A1_9", + "CMT_TOP_NW2A1_9" + ], + [ + "CMT_FIFO_SW4END3_6", + "CMT_TOP_SW4END3_6" + ], + [ + "CMT_FIFO_L_BYP6_4", + "CMT_TOP_BYP6_4" + ], + [ + "CMT_FIFO_L_IMUX37_3", + "CMT_TOP_IMUX37_3" + ], + [ + "CMT_FIFO_L_IMUX32_11", + "CMT_TOP_IMUX32_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_2", + "CMT_TOP_LOGIC_OUTS_L_B20_2" + ], + [ + "CMT_FIFO_EL1BEG0_3", + "CMT_TOP_EL1BEG0_3" + ], + [ + "CMT_FIFO_L_IMUX40_11", + "CMT_TOP_IMUX40_11" + ], + [ + "CMT_FIFO_WW4END1_11", + "CMT_TOP_WW4END1_11" + ], + [ + "CMT_FIFO_L_IMUX17_1", + "CMT_TOP_IMUX17_1" + ], + [ + "CMT_FIFO_L_IMUX29_3", + "CMT_TOP_IMUX29_3" + ], + [ + "CMT_FIFO_NW4A1_0", + "CMT_TOP_NW4A1_0" + ], + [ + "CMT_FIFO_SW4A2_6", + "CMT_TOP_SW4A2_6" + ], + [ + "CMT_FIFO_EE4B0_8", + "CMT_TOP_EE4B0_8" + ], + [ + "CMT_FIFO_EE2BEG3_4", + "CMT_TOP_EE2BEG3_4" + ], + [ + "CMT_FIFO_ER1BEG1_10", + "CMT_TOP_ER1BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX43_9", + "CMT_TOP_IMUX43_9" + ], + [ + "CMT_FIFO_LH8_7", + "CMT_TOP_LH8_7" + ], + [ + "CMT_FIFO_EE4B2_1", + "CMT_TOP_EE4B2_1" + ], + [ + "CMT_FIFO_NW4END2_3", + "CMT_TOP_NW4END2_3" + ], + [ + "CMT_FIFO_WW4A3_5", + "CMT_TOP_WW4A3_5" + ], + [ + "CMT_FIFO_L_BYP6_6", + "CMT_TOP_BYP6_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "CMT_TOP_ICLKDIV_5" + ], + [ + "CMT_FIFO_L_IMUX3_7", + "CMT_TOP_IMUX3_7" + ], + [ + "CMT_FIFO_WW2A1_4", + "CMT_TOP_WW2A1_4" + ], + [ + "CMT_FIFO_EE4B1_6", + "CMT_TOP_EE4B1_6" + ], + [ + "CMT_FIFO_LH10_4", + "CMT_TOP_LH10_4" + ], + [ + "CMT_FIFO_L_IMUX45_3", + "CMT_TOP_IMUX45_3" + ], + [ + "CMT_FIFO_LH4_0", + "CMT_TOP_LH4_0" + ], + [ + "CMT_FIFO_EE2A1_8", + "CMT_TOP_EE2A1_8" + ], + [ + "CMT_FIFO_EE4C1_8", + "CMT_TOP_EE4C1_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "CMT_TOP_ICLKDIV_1" + ], + [ + "CMT_FIFO_L_IMUX8_11", + "CMT_TOP_IMUX8_11" + ], + [ + "CMT_FIFO_L_IMUX36_3", + "CMT_TOP_IMUX36_3" + ], + [ + "CMT_FIFO_SW4A2_0", + "CMT_TOP_SW4A2_0" + ], + [ + "CMT_FIFO_EE2A3_1", + "CMT_TOP_EE2A3_1" + ], + [ + "CMT_FIFO_WL1END2_8", + "CMT_TOP_WL1END2_8" + ], + [ + "CMT_FIFO_SW4A2_4", + "CMT_TOP_SW4A2_4" + ], + [ + "CMT_FIFO_EE4BEG0_10", + "CMT_TOP_EE4BEG0_10" + ], + [ + "CMT_FIFO_EE4C0_3", + "CMT_TOP_EE4C0_3" + ], + [ + "CMT_FIFO_NE4BEG2_8", + "CMT_TOP_NE4BEG2_8" + ], + [ + "CMT_FIFO_EE2A2_8", + "CMT_TOP_EE2A2_8" + ], + [ + "CMT_FIFO_SW2A3_7", + "CMT_TOP_SW2A3_7" + ], + [ + "CMT_FIFO_WW2A2_9", + "CMT_TOP_WW2A2_9" + ], + [ + "CMT_FIFO_SW4A3_3", + "CMT_TOP_SW4A3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_4", + "CMT_TOP_LOGIC_OUTS_L_B20_4" + ], + [ + "CMT_FIFO_NE4C3_3", + "CMT_TOP_NE4C3_3" + ], + [ + "CMT_FIFO_WL1END0_10", + "CMT_TOP_WL1END0_10" + ], + [ + "CMT_FIFO_L_IMUX8_5", + "CMT_TOP_IMUX8_5" + ], + [ + "CMT_FIFO_WW4B1_9", + "CMT_TOP_WW4B1_9" + ], + [ + "CMT_FIFO_NW2A0_9", + "CMT_TOP_NW2A0_9" + ], + [ + "CMT_FIFO_EE2A1_2", + "CMT_TOP_EE2A1_2" + ], + [ + "CMT_FIFO_WW4C0_0", + "CMT_TOP_WW4C0_0" + ], + [ + "CMT_FIFO_WW4B0_4", + "CMT_TOP_WW4B0_4" + ], + [ + "CMT_FIFO_NW2A3_3", + "CMT_TOP_NW2A3_3" + ], + [ + "CMT_FIFO_ER1BEG2_8", + "CMT_TOP_ER1BEG2_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "CMT_TOP_OCLKDIV_4" + ], + [ + "CMT_FIFO_WW4C2_10", + "CMT_TOP_WW4C2_10" + ], + [ + "CMT_FIFO_L_CTRL0_1", + "CMT_TOP_CTRL0_1" + ], + [ + "CMT_FIFO_SW2A0_1", + "CMT_TOP_SW2A0_1" + ], + [ + "CMT_FIFO_EE2BEG0_1", + "CMT_TOP_EE2BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_7", + "CMT_TOP_LOGIC_OUTS_L_B14_7" + ], + [ + "CMT_FIFO_EE2BEG1_6", + "CMT_TOP_EE2BEG1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_7", + "CMT_TOP_LOGIC_OUTS_L_B11_7" + ], + [ + "CMT_FIFO_L_IMUX12_4", + "CMT_TOP_IMUX12_4" + ], + [ + "CMT_FIFO_EE4B2_0", + "CMT_TOP_EE4B2_0" + ], + [ + "CMT_FIFO_SE4C3_11", + "CMT_TOP_SE4C3_11" + ], + [ + "CMT_FIFO_LH10_7", + "CMT_TOP_LH10_7" + ], + [ + "CMT_FIFO_EE2BEG2_2", + "CMT_TOP_EE2BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX23_1", + "CMT_TOP_IMUX23_1" + ], + [ + "CMT_FIFO_WW4A1_5", + "CMT_TOP_WW4A1_5" + ], + [ + "CMT_FIFO_WR1END0_0", + "CMT_TOP_WR1END0_0" + ], + [ + "CMT_FIFO_ER1BEG1_7", + "CMT_TOP_ER1BEG1_7" + ], + [ + "CMT_FIFO_EE4B2_10", + "CMT_TOP_EE4B2_10" + ], + [ + "CMT_FIFO_WW4A1_6", + "CMT_TOP_WW4A1_6" + ], + [ + "CMT_FIFO_L_IMUX42_9", + "CMT_TOP_IMUX42_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "CMT_TOP_ICLK_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_1", + "CMT_TOP_LOGIC_OUTS_L_B8_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "CMT_TOP_ICLK_9" + ], + [ + "CMT_FIFO_NE4BEG3_4", + "CMT_TOP_NE4BEG3_4" + ], + [ + "CMT_FIFO_EE2BEG3_9", + "CMT_TOP_EE2BEG3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_6", + "CMT_TOP_LOGIC_OUTS_L_B12_6" + ], + [ + "CMT_FIFO_NE2A0_6", + "CMT_TOP_NE2A0_6" + ], + [ + "CMT_FIFO_EE4BEG2_7", + "CMT_TOP_EE4BEG2_7" + ], + [ + "CMT_FIFO_NE4BEG1_1", + "CMT_TOP_NE4BEG1_1" + ], + [ + "CMT_FIFO_EE4C2_5", + "CMT_TOP_EE4C2_5" + ], + [ + "CMT_FIFO_WW4C1_3", + "CMT_TOP_WW4C1_3" + ], + [ + "CMT_FIFO_LH10_8", + "CMT_TOP_LH10_8" + ], + [ + "CMT_FIFO_L_IMUX15_0", + "CMT_TOP_IMUX15_0" + ], + [ + "CMT_FIFO_L_FAN7_3", + "CMT_TOP_FAN7_3" + ], + [ + "CMT_FIFO_L_CLK0_9", + "CMT_TOP_CLK0_9" + ], + [ + "CMT_FIFO_NE4BEG0_5", + "CMT_TOP_NE4BEG0_5" + ], + [ + "CMT_FIFO_WR1END0_5", + "CMT_TOP_WR1END0_5" + ], + [ + "CMT_FIFO_SE4BEG3_7", + "CMT_TOP_SE4BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX38_9", + "CMT_TOP_IMUX38_9" + ], + [ + "CMT_FIFO_EE4C1_3", + "CMT_TOP_EE4C1_3" + ], + [ + "CMT_FIFO_SE4C2_8", + "CMT_TOP_SE4C2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_2", + "CMT_TOP_LOGIC_OUTS_L_B12_2" + ], + [ + "CMT_FIFO_L_IMUX43_0", + "CMT_TOP_IMUX43_0" + ], + [ + "CMT_FIFO_L_IMUX15_1", + "CMT_TOP_IMUX15_1" + ], + [ + "CMT_FIFO_ER1BEG3_5", + "CMT_TOP_ER1BEG3_5" + ], + [ + "CMT_FIFO_L_BYP6_7", + "CMT_TOP_BYP6_7" + ], + [ + "CMT_FIFO_L_BYP3_3", + "CMT_TOP_BYP3_3" + ], + [ + "CMT_FIFO_NE2A3_11", + "CMT_TOP_NE2A3_11" + ], + [ + "CMT_FIFO_WL1END1_0", + "CMT_TOP_WL1END1_0" + ], + [ + "CMT_FIFO_L_IMUX21_0", + "CMT_TOP_IMUX21_0" + ], + [ + "CMT_FIFO_WL1END1_6", + "CMT_TOP_WL1END1_6" + ], + [ + "CMT_FIFO_L_IMUX26_2", + "CMT_TOP_IMUX26_2" + ], + [ + "CMT_FIFO_WL1END2_4", + "CMT_TOP_WL1END2_4" + ], + [ + "CMT_FIFO_WW4B0_5", + "CMT_TOP_WW4B0_5" + ], + [ + "CMT_FIFO_EE2A3_10", + "CMT_TOP_EE2A3_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_9", + "CMT_TOP_LOGIC_OUTS_L_B8_9" + ], + [ + "CMT_FIFO_WR1END0_7", + "CMT_TOP_WR1END0_7" + ], + [ + "CMT_FIFO_WW4END0_7", + "CMT_TOP_WW4END0_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_11", + "CMT_TOP_LOGIC_OUTS_L_B5_11" + ], + [ + "CMT_FIFO_L_IMUX24_4", + "CMT_TOP_IMUX24_4" + ], + [ + "CMT_FIFO_SE4BEG2_0", + "CMT_TOP_SE4BEG2_0" + ], + [ + "CMT_FIFO_SW2A2_5", + "CMT_TOP_SW2A2_5" + ], + [ + "CMT_FIFO_L_CTRL1_10", + "CMT_TOP_CTRL1_10" + ], + [ + "CMT_FIFO_L_IMUX7_4", + "CMT_TOP_IMUX7_4" + ], + [ + "CMT_FIFO_WW4C1_0", + "CMT_TOP_WW4C1_0" + ], + [ + "CMT_FIFO_L_IMUX47_7", + "CMT_TOP_IMUX47_7" + ], + [ + "CMT_FIFO_EE4A3_2", + "CMT_TOP_EE4A3_2" + ], + [ + "CMT_FIFO_WW4B3_4", + "CMT_TOP_WW4B3_4" + ], + [ + "CMT_FIFO_L_IMUX0_9", + "CMT_TOP_IMUX0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_9", + "CMT_TOP_LOGIC_OUTS_L_B0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_7", + "CMT_TOP_LOGIC_OUTS_L_B18_7" + ], + [ + "CMT_FIFO_WW4A3_2", + "CMT_TOP_WW4A3_2" + ], + [ + "CMT_FIFO_WW4A3_8", + "CMT_TOP_WW4A3_8" + ], + [ + "CMT_FIFO_L_BYP2_11", + "CMT_TOP_BYP2_11" + ], + [ + "CMT_FIFO_L_IMUX5_1", + "CMT_TOP_IMUX5_1" + ], + [ + "CMT_FIFO_L_IMUX5_8", + "CMT_TOP_IMUX5_8" + ], + [ + "CMT_FIFO_EL1BEG3_11", + "CMT_TOP_EL1BEG3_11" + ], + [ + "CMT_FIFO_NW4A1_8", + "CMT_TOP_NW4A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_4", + "CMT_TOP_LOGIC_OUTS_L_B21_4" + ], + [ + "CMT_FIFO_NE4C0_1", + "CMT_TOP_NE4C0_1" + ], + [ + "CMT_FIFO_WW4B0_3", + "CMT_TOP_WW4B0_3" + ], + [ + "CMT_FIFO_SW4A3_0", + "CMT_TOP_SW4A3_0" + ], + [ + "CMT_FIFO_LH10_9", + "CMT_TOP_LH10_9" + ], + [ + "CMT_FIFO_L_IMUX13_3", + "CMT_TOP_IMUX13_3" + ], + [ + "CMT_FIFO_NE4BEG2_7", + "CMT_TOP_NE4BEG2_7" + ], + [ + "CMT_FIFO_L_BYP0_6", + "CMT_TOP_BYP0_6" + ], + [ + "CMT_FIFO_EL1BEG0_11", + "CMT_TOP_EL1BEG0_11" + ], + [ + "CMT_FIFO_LH6_8", + "CMT_TOP_LH6_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "CMT_TOP_ICLK_3" + ], + [ + "CMT_FIFO_L_IMUX28_4", + "CMT_TOP_IMUX28_4" + ], + [ + "CMT_FIFO_WL1END3_9", + "CMT_TOP_WL1END3_9" + ], + [ + "CMT_FIFO_SE2A1_3", + "CMT_TOP_SE2A1_3" + ], + [ + "CMT_FIFO_L_IMUX47_10", + "CMT_TOP_IMUX47_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_7", + "CMT_TOP_LOGIC_OUTS_L_B3_7" + ], + [ + "CMT_FIFO_SW2A2_2", + "CMT_TOP_SW2A2_2" + ], + [ + "CMT_FIFO_SW2A3_3", + "CMT_TOP_SW2A3_3" + ], + [ + "CMT_FIFO_EE4A2_10", + "CMT_TOP_EE4A2_10" + ], + [ + "CMT_FIFO_WL1END1_5", + "CMT_TOP_WL1END1_5" + ], + [ + "CMT_FIFO_L_FAN4_1", + "CMT_TOP_FAN4_1" + ], + [ + "CMT_FIFO_L_IMUX21_2", + "CMT_TOP_IMUX21_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_4", + "CMT_TOP_LOGIC_OUTS_L_B12_4" + ], + [ + "CMT_FIFO_LH6_5", + "CMT_TOP_LH6_5" + ], + [ + "CMT_FIFO_L_IMUX43_2", + "CMT_TOP_IMUX43_2" + ], + [ + "CMT_FIFO_WL1END0_8", + "CMT_TOP_WL1END0_8" + ], + [ + "CMT_FIFO_SE2A2_2", + "CMT_TOP_SE2A2_2" + ], + [ + "CMT_FIFO_EL1BEG1_5", + "CMT_TOP_EL1BEG1_5" + ], + [ + "CMT_FIFO_EE4A2_11", + "CMT_TOP_EE4A2_11" + ], + [ + "CMT_FIFO_EE4BEG3_2", + "CMT_TOP_EE4BEG3_2" + ], + [ + "CMT_FIFO_WW4A2_7", + "CMT_TOP_WW4A2_7" + ], + [ + "CMT_FIFO_L_IMUX32_2", + "CMT_TOP_IMUX32_2" + ], + [ + "CMT_FIFO_LH4_8", + "CMT_TOP_LH4_8" + ], + [ + "CMT_FIFO_LH12_5", + "CMT_TOP_LH12_5" + ], + [ + "CMT_FIFO_L_IMUX18_9", + "CMT_TOP_IMUX18_9" + ], + [ + "CMT_FIFO_L_IMUX1_9", + "CMT_TOP_IMUX1_9" + ], + [ + "CMT_FIFO_WW4B0_6", + "CMT_TOP_WW4B0_6" + ], + [ + "CMT_FIFO_L_FAN5_8", + "CMT_TOP_FAN5_8" + ], + [ + "CMT_FIFO_SW4END1_2", + "CMT_TOP_SW4END1_2" + ], + [ + "CMT_FIFO_L_IMUX35_11", + "CMT_TOP_IMUX35_11" + ], + [ + "CMT_FIFO_NW4END1_10", + "CMT_TOP_NW4END1_10" + ], + [ + "CMT_FIFO_WR1END3_11", + "CMT_TOP_WR1END3_11" + ], + [ + "CMT_FIFO_L_IMUX14_2", + "CMT_TOP_IMUX14_2" + ], + [ + "CMT_FIFO_L_IMUX4_7", + "CMT_TOP_IMUX4_7" + ], + [ + "CMT_FIFO_WW4END3_0", + "CMT_TOP_WW4END3_0" + ], + [ + "CMT_FIFO_L_IMUX13_9", + "CMT_TOP_IMUX13_9" + ], + [ + "CMT_FIFO_L_IMUX17_5", + "CMT_TOP_IMUX17_5" + ], + [ + "CMT_FIFO_SE2A0_10", + "CMT_TOP_SE2A0_10" + ], + [ + "CMT_FIFO_L_IMUX26_3", + "CMT_TOP_IMUX26_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "CMT_TOP_ICLKDIV_3" + ], + [ + "CMT_FIFO_NE4C1_9", + "CMT_TOP_NE4C1_9" + ], + [ + "CMT_FIFO_L_BYP4_5", + "CMT_TOP_BYP4_5" + ], + [ + "CMT_FIFO_SW4A0_5", + "CMT_TOP_SW4A0_5" + ], + [ + "CMT_FIFO_L_BYP4_3", + "CMT_TOP_BYP4_3" + ], + [ + "CMT_FIFO_NW2A0_2", + "CMT_TOP_NW2A0_2" + ], + [ + "CMT_FIFO_SW2A1_10", + "CMT_TOP_SW2A1_10" + ], + [ + "CMT_FIFO_EE4C0_8", + "CMT_TOP_EE4C0_8" + ], + [ + "CMT_FIFO_L_BYP0_8", + "CMT_TOP_BYP0_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "CMT_TOP_ICLK_10" + ], + [ + "CMT_FIFO_WL1END2_2", + "CMT_TOP_WL1END2_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "CMT_TOP_OCLK_11" + ], + [ + "CMT_FIFO_L_IMUX12_1", + "CMT_TOP_IMUX12_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_9", + "CMT_TOP_LOGIC_OUTS_L_B7_9" + ], + [ + "CMT_FIFO_L_IMUX41_9", + "CMT_TOP_IMUX41_9" + ], + [ + "CMT_FIFO_L_FAN7_11", + "CMT_TOP_FAN7_11" + ], + [ + "CMT_FIFO_EE2A3_5", + "CMT_TOP_EE2A3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_3", + "CMT_TOP_LOGIC_OUTS_L_B21_3" + ], + [ + "CMT_FIFO_WW4B2_4", + "CMT_TOP_WW4B2_4" + ], + [ + "CMT_FIFO_L_IMUX3_2", + "CMT_TOP_IMUX3_2" + ], + [ + "CMT_FIFO_WR1END0_3", + "CMT_TOP_WR1END0_3" + ], + [ + "CMT_FIFO_SE4BEG0_10", + "CMT_TOP_SE4BEG0_10" + ], + [ + "CMT_FIFO_L_IMUX8_8", + "CMT_TOP_IMUX8_8" + ], + [ + "CMT_FIFO_WW4B3_9", + "CMT_TOP_WW4B3_9" + ], + [ + "CMT_FIFO_L_IMUX11_1", + "CMT_TOP_IMUX11_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_4", + "CMT_TOP_LOGIC_OUTS_L_B5_4" + ], + [ + "CMT_FIFO_LH3_0", + "CMT_TOP_LH3_0" + ], + [ + "CMT_FIFO_WR1END2_7", + "CMT_TOP_WR1END2_7" + ], + [ + "CMT_FIFO_NE2A2_7", + "CMT_TOP_NE2A2_7" + ], + [ + "CMT_FIFO_ER1BEG3_2", + "CMT_TOP_ER1BEG3_2" + ], + [ + "CMT_FIFO_WW2A1_0", + "CMT_TOP_WW2A1_0" + ], + [ + "CMT_FIFO_WL1END0_11", + "CMT_TOP_WL1END0_11" + ], + [ + "CMT_FIFO_NE4BEG1_9", + "CMT_TOP_NE4BEG1_9" + ], + [ + "CMT_FIFO_SW4A3_10", + "CMT_TOP_SW4A3_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_7", + "CMT_TOP_LOGIC_OUTS_L_B12_7" + ], + [ + "CMT_FIFO_WW4B3_1", + "CMT_TOP_WW4B3_1" + ], + [ + "CMT_FIFO_NW4END0_5", + "CMT_TOP_NW4END0_5" + ], + [ + "CMT_FIFO_L_BYP7_5", + "CMT_TOP_BYP7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_8", + "CMT_TOP_LOGIC_OUTS_L_B16_8" + ], + [ + "CMT_FIFO_SE4C1_6", + "CMT_TOP_SE4C1_6" + ], + [ + "CMT_FIFO_WW4B2_3", + "CMT_TOP_WW4B2_3" + ], + [ + "CMT_FIFO_L_IMUX3_1", + "CMT_TOP_IMUX3_1" + ], + [ + "CMT_FIFO_L_FAN4_5", + "CMT_TOP_FAN4_5" + ], + [ + "CMT_FIFO_L_IMUX32_8", + "CMT_TOP_IMUX32_8" + ], + [ + "CMT_FIFO_L_IMUX36_7", + "CMT_TOP_IMUX36_7" + ], + [ + "CMT_FIFO_EE4A0_8", + "CMT_TOP_EE4A0_8" + ], + [ + "CMT_FIFO_EE4C0_11", + "CMT_TOP_EE4C0_11" + ], + [ + "CMT_FIFO_NW2A0_5", + "CMT_TOP_NW2A0_5" + ], + [ + "CMT_FIFO_L_CLK0_10", + "CMT_TOP_CLK0_10" + ], + [ + "CMT_FIFO_EE4B3_5", + "CMT_TOP_EE4B3_5" + ], + [ + "CMT_FIFO_EE4BEG0_6", + "CMT_TOP_EE4BEG0_6" + ], + [ + "CMT_FIFO_L_IMUX1_0", + "CMT_TOP_IMUX1_0" + ], + [ + "CMT_FIFO_L_IMUX12_11", + "CMT_TOP_IMUX12_11" + ], + [ + "CMT_FIFO_L_IMUX14_8", + "CMT_TOP_IMUX14_8" + ], + [ + "CMT_FIFO_NW4A1_3", + "CMT_TOP_NW4A1_3" + ], + [ + "CMT_FIFO_L_IMUX17_11", + "CMT_TOP_IMUX17_11" + ], + [ + "CMT_FIFO_SE4BEG1_8", + "CMT_TOP_SE4BEG1_8" + ], + [ + "CMT_FIFO_L_IMUX5_10", + "CMT_TOP_IMUX5_10" + ], + [ + "CMT_FIFO_NE2A3_2", + "CMT_TOP_NE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX0_4", + "CMT_TOP_IMUX0_4" + ], + [ + "CMT_FIFO_NE4C3_2", + "CMT_TOP_NE4C3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_8", + "CMT_TOP_LOGIC_OUTS_L_B2_8" + ], + [ + "CMT_FIFO_LH4_6", + "CMT_TOP_LH4_6" + ], + [ + "CMT_FIFO_L_IMUX27_5", + "CMT_TOP_IMUX27_5" + ], + [ + "CMT_FIFO_LH5_0", + "CMT_TOP_LH5_0" + ], + [ + "CMT_FIFO_EE4B3_10", + "CMT_TOP_EE4B3_10" + ], + [ + "CMT_FIFO_NW4A3_8", + "CMT_TOP_NW4A3_8" + ], + [ + "CMT_FIFO_L_BYP0_3", + "CMT_TOP_BYP0_3" + ], + [ + "CMT_FIFO_L_IMUX24_8", + "CMT_TOP_IMUX24_8" + ], + [ + "CMT_FIFO_L_IMUX30_3", + "CMT_TOP_IMUX30_3" + ], + [ + "CMT_FIFO_L_FAN7_9", + "CMT_TOP_FAN7_9" + ], + [ + "CMT_FIFO_EE4B2_6", + "CMT_TOP_EE4B2_6" + ], + [ + "CMT_FIFO_L_IMUX14_4", + "CMT_TOP_IMUX14_4" + ], + [ + "CMT_FIFO_LH10_6", + "CMT_TOP_LH10_6" + ], + [ + "CMT_FIFO_WW4A0_2", + "CMT_TOP_WW4A0_2" + ], + [ + "CMT_FIFO_L_BYP0_10", + "CMT_TOP_BYP0_10" + ], + [ + "CMT_FIFO_L_IMUX36_2", + "CMT_TOP_IMUX36_2" + ], + [ + "CMT_FIFO_L_IMUX13_7", + "CMT_TOP_IMUX13_7" + ], + [ + "CMT_FIFO_SE2A1_11", + "CMT_TOP_SE2A1_11" + ], + [ + "CMT_FIFO_L_CTRL0_8", + "CMT_TOP_CTRL0_8" + ], + [ + "CMT_FIFO_SE4C2_1", + "CMT_TOP_SE4C2_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_7", + "CMT_TOP_LOGIC_OUTS_L_B17_7" + ], + [ + "CMT_FIFO_L_IMUX5_2", + "CMT_TOP_IMUX5_2" + ], + [ + "CMT_FIFO_EE4BEG0_5", + "CMT_TOP_EE4BEG0_5" + ], + [ + "CMT_FIFO_EE4B0_2", + "CMT_TOP_EE4B0_2" + ], + [ + "CMT_FIFO_L_BYP4_1", + "CMT_TOP_BYP4_1" + ], + [ + "CMT_FIFO_L_FAN1_7", + "CMT_TOP_FAN1_7" + ], + [ + "CMT_FIFO_L_IMUX28_6", + "CMT_TOP_IMUX28_6" + ], + [ + "CMT_FIFO_NE2A2_4", + "CMT_TOP_NE2A2_4" + ], + [ + "CMT_FIFO_WW2A1_9", + "CMT_TOP_WW2A1_9" + ], + [ + "CMT_FIFO_L_FAN1_6", + "CMT_TOP_FAN1_6" + ], + [ + "CMT_FIFO_L_IMUX13_5", + "CMT_TOP_IMUX13_5" + ], + [ + "CMT_FIFO_L_IMUX27_2", + "CMT_TOP_IMUX27_2" + ], + [ + "CMT_FIFO_L_IMUX8_4", + "CMT_TOP_IMUX8_4" + ], + [ + "CMT_FIFO_NE4C0_0", + "CMT_TOP_NE4C0_0" + ], + [ + "CMT_FIFO_NW4END1_11", + "CMT_TOP_NW4END1_11" + ], + [ + "CMT_FIFO_LH8_1", + "CMT_TOP_LH8_1" + ], + [ + "CMT_FIFO_L_IMUX30_7", + "CMT_TOP_IMUX30_7" + ], + [ + "CMT_FIFO_WW2A0_5", + "CMT_TOP_WW2A0_5" + ], + [ + "CMT_FIFO_LH6_4", + "CMT_TOP_LH6_4" + ], + [ + "CMT_FIFO_L_IMUX14_7", + "CMT_TOP_IMUX14_7" + ], + [ + "CMT_FIFO_L_IMUX11_6", + "CMT_TOP_IMUX11_6" + ], + [ + "CMT_FIFO_L_CLK1_9", + "CMT_TOP_CLK1_9" + ], + [ + "CMT_FIFO_L_IMUX13_1", + "CMT_TOP_IMUX13_1" + ], + [ + "CMT_FIFO_SE4C1_7", + "CMT_TOP_SE4C1_7" + ], + [ + "CMT_FIFO_LH9_6", + "CMT_TOP_LH9_6" + ], + [ + "CMT_FIFO_L_IMUX24_7", + "CMT_TOP_IMUX24_7" + ], + [ + "CMT_FIFO_L_IMUX41_10", + "CMT_TOP_IMUX41_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_4", + "CMT_TOP_LOGIC_OUTS_L_B11_4" + ], + [ + "CMT_FIFO_LH3_9", + "CMT_TOP_LH3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_9", + "CMT_TOP_LOGIC_OUTS_L_B20_9" + ], + [ + "CMT_FIFO_L_IMUX20_5", + "CMT_TOP_IMUX20_5" + ], + [ + "CMT_FIFO_EE4A2_6", + "CMT_TOP_EE4A2_6" + ], + [ + "CMT_FIFO_WR1END2_5", + "CMT_TOP_WR1END2_5" + ], + [ + "CMT_FIFO_LH1_7", + "CMT_TOP_LH1_7" + ], + [ + "CMT_FIFO_L_IMUX34_5", + "CMT_TOP_IMUX34_5" + ], + [ + "CMT_FIFO_EE4A0_4", + "CMT_TOP_EE4A0_4" + ], + [ + "CMT_FIFO_L_IMUX26_8", + "CMT_TOP_IMUX26_8" + ], + [ + "CMT_FIFO_LH8_8", + "CMT_TOP_LH8_8" + ], + [ + "CMT_FIFO_LH11_3", + "CMT_TOP_LH11_3" + ], + [ + "CMT_FIFO_EE2BEG0_4", + "CMT_TOP_EE2BEG0_4" + ], + [ + "CMT_FIFO_L_IMUX39_6", + "CMT_TOP_IMUX39_6" + ], + [ + "CMT_FIFO_WW4C1_5", + "CMT_TOP_WW4C1_5" + ], + [ + "CMT_FIFO_WW4END1_7", + "CMT_TOP_WW4END1_7" + ], + [ + "CMT_FIFO_L_BYP2_5", + "CMT_TOP_BYP2_5" + ], + [ + "CMT_FIFO_MONITOR_P_4", + "CMT_TOP_MONITOR_P_4" + ], + [ + "CMT_FIFO_L_IMUX4_1", + "CMT_TOP_IMUX4_1" + ], + [ + "CMT_FIFO_NW4END3_0", + "CMT_TOP_NW4END3_0" + ], + [ + "CMT_FIFO_ER1BEG3_10", + "CMT_TOP_ER1BEG3_10" + ], + [ + "CMT_FIFO_L_IMUX12_5", + "CMT_TOP_IMUX12_5" + ], + [ + "CMT_FIFO_L_IMUX1_2", + "CMT_TOP_IMUX1_2" + ], + [ + "CMT_FIFO_L_IMUX7_11", + "CMT_TOP_IMUX7_11" + ], + [ + "CMT_FIFO_L_IMUX28_11", + "CMT_TOP_IMUX28_11" + ], + [ + "CMT_FIFO_L_IMUX9_2", + "CMT_TOP_IMUX9_2" + ], + [ + "CMT_FIFO_L_BYP3_11", + "CMT_TOP_BYP3_11" + ], + [ + "CMT_FIFO_NW4A3_1", + "CMT_TOP_NW4A3_1" + ], + [ + "CMT_FIFO_L_CTRL1_2", + "CMT_TOP_CTRL1_2" + ], + [ + "CMT_FIFO_LH12_0", + "CMT_TOP_LH12_0" + ], + [ + "CMT_FIFO_L_IMUX23_5", + "CMT_TOP_IMUX23_5" + ], + [ + "CMT_FIFO_LH12_3", + "CMT_TOP_LH12_3" + ], + [ + "CMT_FIFO_L_IMUX16_4", + "CMT_TOP_IMUX16_4" + ], + [ + "CMT_FIFO_WR1END1_10", + "CMT_TOP_WR1END1_10" + ], + [ + "CMT_FIFO_L_IMUX11_4", + "CMT_TOP_IMUX11_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_3", + "CMT_TOP_LOGIC_OUTS_L_B20_3" + ], + [ + "CMT_FIFO_L_IMUX13_8", + "CMT_TOP_IMUX13_8" + ], + [ + "CMT_FIFO_L_IMUX34_7", + "CMT_TOP_IMUX34_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_10", + "CMT_TOP_LOGIC_OUTS_L_B5_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_7", + "CMT_TOP_LOGIC_OUTS_L_B10_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_2", + "CMT_TOP_LOGIC_OUTS_L_B15_2" + ], + [ + "CMT_FIFO_L_IMUX10_4", + "CMT_TOP_IMUX10_4" + ], + [ + "CMT_FIFO_L_IMUX34_4", + "CMT_TOP_IMUX34_4" + ], + [ + "CMT_FIFO_NW4A2_5", + "CMT_TOP_NW4A2_5" + ], + [ + "CMT_FIFO_L_IMUX27_6", + "CMT_TOP_IMUX27_6" + ], + [ + "CMT_FIFO_L_IMUX42_8", + "CMT_TOP_IMUX42_8" + ], + [ + "CMT_FIFO_L_IMUX31_1", + "CMT_TOP_IMUX31_1" + ], + [ + "CMT_FIFO_WW4END2_0", + "CMT_TOP_WW4END2_0" + ], + [ + "CMT_FIFO_SW4A0_10", + "CMT_TOP_SW4A0_10" + ], + [ + "CMT_FIFO_LH12_11", + "CMT_TOP_LH12_11" + ], + [ + "CMT_FIFO_NW4END2_4", + "CMT_TOP_NW4END2_4" + ], + [ + "CMT_FIFO_SE2A2_0", + "CMT_TOP_SE2A2_0" + ], + [ + "CMT_FIFO_SE2A3_5", + "CMT_TOP_SE2A3_5" + ], + [ + "CMT_FIFO_L_IMUX7_5", + "CMT_TOP_IMUX7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_7", + "CMT_TOP_LOGIC_OUTS_L_B9_7" + ], + [ + "CMT_FIFO_L_FAN3_6", + "CMT_TOP_FAN3_6" + ], + [ + "CMT_FIFO_EE4A2_2", + "CMT_TOP_EE4A2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_2", + "CMT_TOP_LOGIC_OUTS_L_B17_2" + ], + [ + "CMT_FIFO_L_IMUX22_10", + "CMT_TOP_IMUX22_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_9", + "CMT_TOP_LOGIC_OUTS_L_B22_9" + ], + [ + "CMT_FIFO_L_IMUX4_10", + "CMT_TOP_IMUX4_10" + ], + [ + "CMT_FIFO_L_BYP7_3", + "CMT_TOP_BYP7_3" + ], + [ + "CMT_FIFO_NE4BEG3_6", + "CMT_TOP_NE4BEG3_6" + ], + [ + "CMT_FIFO_L_CTRL0_10", + "CMT_TOP_CTRL0_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_5", + "CMT_TOP_LOGIC_OUTS_L_B13_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_11", + "CMT_TOP_LOGIC_OUTS_L_B19_11" + ], + [ + "CMT_FIFO_L_IMUX41_8", + "CMT_TOP_IMUX41_8" + ], + [ + "CMT_FIFO_SE2A1_0", + "CMT_TOP_SE2A1_0" + ], + [ + "CMT_FIFO_SW4END2_11", + "CMT_TOP_SW4END2_11" + ], + [ + "CMT_FIFO_L_PHASER_WRENABLE", + "CMT_PLL_PHASER_WRENABLE_TOFIFO" + ], + [ + "CMT_FIFO_WL1END0_3", + "CMT_TOP_WL1END0_3" + ], + [ + "CMT_FIFO_L_IMUX37_5", + "CMT_TOP_IMUX37_5" + ], + [ + "CMT_FIFO_LH12_8", + "CMT_TOP_LH12_8" + ], + [ + "CMT_FIFO_SW4END3_3", + "CMT_TOP_SW4END3_3" + ], + [ + "CMT_FIFO_NW4A1_5", + "CMT_TOP_NW4A1_5" + ], + [ + "CMT_FIFO_WW4END3_5", + "CMT_TOP_WW4END3_5" + ], + [ + "CMT_FIFO_L_BYP7_4", + "CMT_TOP_BYP7_4" + ], + [ + "CMT_FIFO_L_IMUX10_0", + "CMT_TOP_IMUX10_0" + ], + [ + "CMT_FIFO_EE4BEG0_2", + "CMT_TOP_EE4BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX33_0", + "CMT_TOP_IMUX33_0" + ], + [ + "CMT_FIFO_EL1BEG0_7", + "CMT_TOP_EL1BEG0_7" + ], + [ + "CMT_FIFO_SE2A2_5", + "CMT_TOP_SE2A2_5" + ], + [ + "CMT_FIFO_ER1BEG2_0", + "CMT_TOP_ER1BEG2_0" + ], + [ + "CMT_FIFO_L_CLK0_11", + "CMT_TOP_CLK0_11" + ], + [ + "CMT_FIFO_L_IMUX13_4", + "CMT_TOP_IMUX13_4" + ], + [ + "CMT_FIFO_L_BYP5_9", + "CMT_TOP_BYP5_9" + ], + [ + "CMT_FIFO_LH10_2", + "CMT_TOP_LH10_2" + ], + [ + "CMT_FIFO_L_IMUX33_4", + "CMT_TOP_IMUX33_4" + ], + [ + "CMT_FIFO_SW4END0_8", + "CMT_TOP_SW4END0_8" + ], + [ + "CMT_FIFO_L_IMUX11_11", + "CMT_TOP_IMUX11_11" + ], + [ + "CMT_FIFO_SW4END0_1", + "CMT_TOP_SW4END0_1" + ], + [ + "CMT_FIFO_L_IMUX14_0", + "CMT_TOP_IMUX14_0" + ], + [ + "CMT_FIFO_NW4END3_11", + "CMT_TOP_NW4END3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_6", + "CMT_TOP_LOGIC_OUTS_L_B21_6" + ], + [ + "CMT_FIFO_L_FAN7_8", + "CMT_TOP_FAN7_8" + ], + [ + "CMT_FIFO_EE4BEG1_7", + "CMT_TOP_EE4BEG1_7" + ], + [ + "CMT_FIFO_L_BYP3_7", + "CMT_TOP_BYP3_7" + ], + [ + "CMT_FIFO_L_IMUX26_0", + "CMT_TOP_IMUX26_0" + ], + [ + "CMT_FIFO_LH8_5", + "CMT_TOP_LH8_5" + ], + [ + "CMT_FIFO_WL1END0_7", + "CMT_TOP_WL1END0_7" + ], + [ + "CMT_FIFO_L_IMUX11_9", + "CMT_TOP_IMUX11_9" + ], + [ + "CMT_FIFO_WR1END0_4", + "CMT_TOP_WR1END0_4" + ], + [ + "CMT_FIFO_L_IMUX36_10", + "CMT_TOP_IMUX36_10" + ], + [ + "CMT_FIFO_EL1BEG1_1", + "CMT_TOP_EL1BEG1_1" + ], + [ + "CMT_FIFO_SE4C1_10", + "CMT_TOP_SE4C1_10" + ], + [ + "CMT_FIFO_NW4END0_10", + "CMT_TOP_NW4END0_10" + ], + [ + "CMT_FIFO_WW2END0_9", + "CMT_TOP_WW2END0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_6", + "CMT_TOP_LOGIC_OUTS_L_B1_6" + ], + [ + "CMT_FIFO_ER1BEG2_2", + "CMT_TOP_ER1BEG2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_9", + "CMT_TOP_LOGIC_OUTS_L_B19_9" + ], + [ + "CMT_FIFO_NE4C0_9", + "CMT_TOP_NE4C0_9" + ], + [ + "CMT_FIFO_SE2A0_4", + "CMT_TOP_SE2A0_4" + ], + [ + "CMT_FIFO_WW2A3_9", + "CMT_TOP_WW2A3_9" + ], + [ + "CMT_FIFO_L_IMUX21_9", + "CMT_TOP_IMUX21_9" + ], + [ + "CMT_FIFO_NE2A3_5", + "CMT_TOP_NE2A3_5" + ], + [ + "CMT_FIFO_NW2A0_7", + "CMT_TOP_NW2A0_7" + ], + [ + "CMT_FIFO_L_IMUX40_10", + "CMT_TOP_IMUX40_10" + ], + [ + "CMT_FIFO_L_IMUX6_9", + "CMT_TOP_IMUX6_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_4", + "CMT_TOP_LOGIC_OUTS_L_B8_4" + ], + [ + "CMT_FIFO_ER1BEG1_5", + "CMT_TOP_ER1BEG1_5" + ], + [ + "CMT_FIFO_WW4A2_1", + "CMT_TOP_WW4A2_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "CMT_TOP_OCLKDIV_6" + ], + [ + "CMT_FIFO_LH3_5", + "CMT_TOP_LH3_5" + ], + [ + "CMT_FIFO_SW4END0_9", + "CMT_TOP_SW4END0_9" + ], + [ + "CMT_FIFO_SE4BEG0_9", + "CMT_TOP_SE4BEG0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_3", + "CMT_TOP_LOGIC_OUTS_L_B9_3" + ], + [ + "CMT_FIFO_ER1BEG1_1", + "CMT_TOP_ER1BEG1_1" + ], + [ + "CMT_FIFO_EE2A2_0", + "CMT_TOP_EE2A2_0" + ], + [ + "CMT_FIFO_L_IMUX40_2", + "CMT_TOP_IMUX40_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_2", + "CMT_TOP_LOGIC_OUTS_L_B13_2" + ], + [ + "CMT_FIFO_L_IMUX22_9", + "CMT_TOP_IMUX22_9" + ], + [ + "CMT_FIFO_LH9_11", + "CMT_TOP_LH9_11" + ], + [ + "CMT_FIFO_WL1END3_3", + "CMT_TOP_WL1END3_3" + ], + [ + "CMT_FIFO_EE2A1_9", + "CMT_TOP_EE2A1_9" + ], + [ + "CMT_FIFO_LH4_9", + "CMT_TOP_LH4_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_3", + "CMT_TOP_LOGIC_OUTS_L_B12_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_9", + "CMT_TOP_LOGIC_OUTS_L_B21_9" + ], + [ + "CMT_FIFO_NW4END0_3", + "CMT_TOP_NW4END0_3" + ], + [ + "CMT_FIFO_SW4A3_1", + "CMT_TOP_SW4A3_1" + ], + [ + "CMT_FIFO_SW4END2_10", + "CMT_TOP_SW4END2_10" + ], + [ + "CMT_FIFO_SW4END0_7", + "CMT_TOP_SW4END0_7" + ], + [ + "CMT_FIFO_L_IMUX11_5", + "CMT_TOP_IMUX11_5" + ], + [ + "CMT_FIFO_ER1BEG3_7", + "CMT_TOP_ER1BEG3_7" + ], + [ + "CMT_FIFO_EE2BEG2_9", + "CMT_TOP_EE2BEG2_9" + ], + [ + "CMT_FIFO_EE4C0_10", + "CMT_TOP_EE4C0_10" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "CMT_TOP_L_UPPER_T" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "DSP_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "DSP_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "DSP_LH6_0", + "VBRK_LH6" + ], + [ + "DSP_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "DSP_LH2_0", + "VBRK_LH2" + ], + [ + "DSP_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "DSP_LH12_0", + "VBRK_LH12" + ], + [ + "DSP_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "DSP_LH4_0", + "VBRK_LH4" + ], + [ + "DSP_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "DSP_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "DSP_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "DSP_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "DSP_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "DSP_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "DSP_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "DSP_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "DSP_MONITOR_N_0", + "VBRK_MONITOR_N" + ], + [ + "DSP_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "DSP_SW4A1_0", + "VBRK_SW4A1" + ], + [ + "DSP_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "DSP_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "DSP_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "DSP_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "DSP_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "DSP_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "DSP_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "DSP_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "DSP_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "DSP_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "DSP_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "DSP_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "DSP_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "DSP_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "DSP_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "DSP_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "DSP_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "DSP_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "DSP_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "DSP_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "DSP_LH3_0", + "VBRK_LH3" + ], + [ + "DSP_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "DSP_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "DSP_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "DSP_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "DSP_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "DSP_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "DSP_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "DSP_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "DSP_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "DSP_LH10_0", + "VBRK_LH10" + ], + [ + "DSP_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "DSP_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "DSP_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "DSP_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "DSP_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "DSP_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "DSP_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "DSP_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "DSP_LH1_0", + "VBRK_LH1" + ], + [ + "DSP_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "DSP_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "DSP_LH11_0", + "VBRK_LH11" + ], + [ + "DSP_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "DSP_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "DSP_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "DSP_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "DSP_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "DSP_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "DSP_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "DSP_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "DSP_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "DSP_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "DSP_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "DSP_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "DSP_LH5_0", + "VBRK_LH5" + ], + [ + "DSP_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "DSP_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "DSP_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "DSP_LH9_0", + "VBRK_LH9" + ], + [ + "DSP_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "DSP_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "DSP_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "DSP_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "DSP_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "DSP_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "DSP_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "DSP_MONITOR_P_0", + "VBRK_MONITOR_P" + ], + [ + "DSP_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "DSP_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "DSP_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "DSP_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "DSP_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "DSP_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "DSP_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "DSP_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "DSP_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "DSP_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "DSP_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "DSP_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "DSP_LH7_0", + "VBRK_LH7" + ], + [ + "DSP_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "DSP_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "DSP_LH8_0", + "VBRK_LH8" + ], + [ + "DSP_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "DSP_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "DSP_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "DSP_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "DSP_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "DSP_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "DSP_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "DSP_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "DSP_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "DSP_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "DSP_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "DSP_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "DSP_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "DSP_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "DSP_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "DSP_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "DSP_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "DSP_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "DSP_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "DSP_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "DSP_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "DSP_WW4C0_0", + "VBRK_WW4C0" + ] + ], + "tile_types": [ + "DSP_L", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "CFG_CENTER_NE2A3_3", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_EL1BEG3_3", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_NW4A1_3", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_EE4BEG3_3", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_NE2A0_3", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EE4BEG1_3", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_LH3_3", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_WR1END3_3", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_WW4B3_3", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_ER1BEG3_3", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW4END0_3", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EL1BEG2_3", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_SW4END0_3", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_NE4BEG2_3", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_ER1BEG0_3", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_EE4C1_3", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE4A0_3", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_LH2_3", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_EE4B1_3", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EE2A0_3", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_EE4A1_3", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_SE4BEG2_3", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW4END1_3", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_LH7_3", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4A0_3", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SW2A0_3", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_SW4A0_3", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WL1END1_3", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_EE2BEG2_3", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NE4C0_3", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_NE4C3_3", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_EE4A2_3", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SE4C3_3", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WW4A1_3", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_LH9_3", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NE2A2_3", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE4BEG0_3", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WW2END3_3", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_NE4C1_3", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW4A2_3", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE2A3_3", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW2A2_3", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4C2_3", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW4C0_3", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_SW4A2_3", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NW4END3_3", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_LH11_3", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW2END1_3", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE4B0_3", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_SE2A0_3", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_LH6_3", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WW4C2_3", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_EE2BEG0_3", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_SW4END1_3", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EE4B2_3", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_WW4C1_3", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SE4C2_3", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_LH8_3", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_NE4BEG0_3", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NW4A3_3", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_NW2A2_3", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_NW4END1_3", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_NW2A0_3", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WR1END0_3", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_SE2A1_3", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_SW2A1_3", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4C2_3", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NE2A1_3", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_ER1BEG2_3", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_EL1BEG0_3", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_ER1BEG1_3", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SE4C0_3", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_LH4_3", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE2BEG3_3", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_WW4B2_3", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_LH1_3", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_SE4BEG3_3", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_WW2END2_3", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_WW4A3_3", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_SW4END2_3", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SW2A3_3", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_EE4C0_3", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_SE4BEG0_3", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_EE2A2_3", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_SW4A1_3", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NW2A1_3", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SW4A3_3", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE4B3_3", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NE4BEG3_3", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_SE2A3_3", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_NE4BEG1_3", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_EE2BEG1_3", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_LH12_3", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW4END2_3", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_WW2A1_3", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WL1END0_3", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SE4BEG1_3", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_NW4END2_3", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_NW4END0_3", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_WW4END3_3", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_SE2A2_3", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_WR1END2_3", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_WL1END3_3", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_SE4C1_3", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_LH5_3", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_LH10_3", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_NW4A0_3", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_EE4C3_3", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_SW4END3_3", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_SW2A2_3", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WW2A0_3", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_EL1BEG1_3", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW2A3_3", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WR1END1_3", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WW4C3_3", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE4A3_3", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_NW2A3_3", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_EE4BEG2_3", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WW4B0_3", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_NW4A2_3", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WL1END2_3", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_EE2A1_3", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_WW4B1_3", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW2END0_3", + "INT_FEEDTHRU_2_WW2END0" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "BRAM_LH2_4", + "VBRK_LH2" + ], + [ + "BRAM_LH12_4", + "VBRK_LH12" + ], + [ + "BRAM_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "BRAM_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "BRAM_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "BRAM_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "BRAM_MONITOR_N_4", + "VBRK_MONITOR_N" + ], + [ + "BRAM_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "BRAM_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "BRAM_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "BRAM_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "BRAM_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "BRAM_LH11_4", + "VBRK_LH11" + ], + [ + "BRAM_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "BRAM_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "BRAM_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "BRAM_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "BRAM_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "BRAM_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "BRAM_LH1_4", + "VBRK_LH1" + ], + [ + "BRAM_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "BRAM_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "BRAM_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "BRAM_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "BRAM_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "BRAM_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "BRAM_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "BRAM_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "BRAM_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "BRAM_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "BRAM_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "BRAM_LH9_4", + "VBRK_LH9" + ], + [ + "BRAM_LH4_4", + "VBRK_LH4" + ], + [ + "BRAM_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "BRAM_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "BRAM_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "BRAM_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "BRAM_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "BRAM_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "BRAM_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "BRAM_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "BRAM_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "BRAM_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "BRAM_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "BRAM_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "BRAM_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "BRAM_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "BRAM_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "BRAM_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "BRAM_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "BRAM_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "BRAM_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "BRAM_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "BRAM_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "BRAM_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "BRAM_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "BRAM_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "BRAM_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "BRAM_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "BRAM_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "BRAM_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "BRAM_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "BRAM_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "BRAM_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "BRAM_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "BRAM_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "BRAM_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "BRAM_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "BRAM_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "BRAM_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "BRAM_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "BRAM_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "BRAM_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "BRAM_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "BRAM_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "BRAM_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "BRAM_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "BRAM_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "BRAM_LH3_4", + "VBRK_LH3" + ], + [ + "BRAM_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "BRAM_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "BRAM_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "BRAM_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "BRAM_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "BRAM_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "BRAM_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "BRAM_MONITOR_P_4", + "VBRK_MONITOR_P" + ], + [ + "BRAM_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "BRAM_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "BRAM_LH5_4", + "VBRK_LH5" + ], + [ + "BRAM_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "BRAM_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "BRAM_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "BRAM_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "BRAM_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "BRAM_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "BRAM_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "BRAM_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "BRAM_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "BRAM_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "BRAM_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "BRAM_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "BRAM_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "BRAM_LH6_4", + "VBRK_LH6" + ], + [ + "BRAM_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "BRAM_LH7_4", + "VBRK_LH7" + ], + [ + "BRAM_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "BRAM_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "BRAM_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "BRAM_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "BRAM_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "BRAM_LH10_4", + "VBRK_LH10" + ], + [ + "BRAM_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "BRAM_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "BRAM_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "BRAM_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "BRAM_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "BRAM_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "BRAM_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "BRAM_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "BRAM_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "BRAM_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "BRAM_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "BRAM_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "BRAM_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "BRAM_LH8_4", + "VBRK_LH8" + ] + ], + "tile_types": [ + "BRAM_L", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "MONITOR_EL1BEG1_3", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_EE4A0_3", + "VFRAME_EE4A0" + ], + [ + "MONITOR_SW2A0_3", + "VFRAME_SW2A0" + ], + [ + "MONITOR_WL1END2_3", + "VFRAME_WL1END2" + ], + [ + "MONITOR_EE2BEG1_3", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_NW4A0_3", + "VFRAME_NW4A0" + ], + [ + "MONITOR_BYP5_3", + "VFRAME_BYP5" + ], + [ + "MONITOR_LOGIC_OUTS_B15_3", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "MONITOR_WL1END3_3", + "VFRAME_WL1END3" + ], + [ + "MONITOR_IMUX8_3", + "VFRAME_IMUX8" + ], + [ + "MONITOR_FAN6_3", + "VFRAME_FAN6" + ], + [ + "MONITOR_CLK1_3", + "VFRAME_CLK1" + ], + [ + "MONITOR_IMUX23_3", + "VFRAME_IMUX23" + ], + [ + "MONITOR_EE4BEG2_3", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_SE4C3_3", + "VFRAME_SE4C3" + ], + [ + "MONITOR_IMUX35_3", + "VFRAME_IMUX35" + ], + [ + "MONITOR_FAN2_3", + "VFRAME_FAN2" + ], + [ + "MONITOR_NE4BEG0_3", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_WW4C1_3", + "VFRAME_WW4C1" + ], + [ + "MONITOR_IMUX29_3", + "VFRAME_IMUX29" + ], + [ + "MONITOR_IMUX28_3", + "VFRAME_IMUX28" + ], + [ + "MONITOR_IMUX0_3", + "VFRAME_IMUX0" + ], + [ + "MONITOR_LH9_3", + "VFRAME_LH9" + ], + [ + "MONITOR_SW4END2_3", + "VFRAME_SW4END2" + ], + [ + "MONITOR_LOGIC_OUTS_B17_3", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "MONITOR_IMUX16_3", + "VFRAME_IMUX16" + ], + [ + "MONITOR_SW4A3_3", + "VFRAME_SW4A3" + ], + [ + "MONITOR_LH1_3", + "VFRAME_LH1" + ], + [ + "MONITOR_EE4B0_3", + "VFRAME_EE4B0" + ], + [ + "MONITOR_IMUX44_3", + "VFRAME_IMUX44" + ], + [ + "MONITOR_FAN4_3", + "VFRAME_FAN4" + ], + [ + "MONITOR_IMUX45_3", + "VFRAME_IMUX45" + ], + [ + "MONITOR_IMUX18_3", + "VFRAME_IMUX18" + ], + [ + "MONITOR_IMUX2_3", + "VFRAME_IMUX2" + ], + [ + "MONITOR_IMUX6_3", + "VFRAME_IMUX6" + ], + [ + "MONITOR_IMUX30_3", + "VFRAME_IMUX30" + ], + [ + "MONITOR_IMUX22_3", + "VFRAME_IMUX22" + ], + [ + "MONITOR_FAN1_3", + "VFRAME_FAN1" + ], + [ + "MONITOR_NE4BEG3_3", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_ER1BEG0_3", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_EE4B2_3", + "VFRAME_EE4B2" + ], + [ + "MONITOR_SW2A1_3", + "VFRAME_SW2A1" + ], + [ + "MONITOR_LH5_3", + "VFRAME_LH5" + ], + [ + "MONITOR_IMUX7_3", + "VFRAME_IMUX7" + ], + [ + "MONITOR_LOGIC_OUTS_B16_3", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "MONITOR_WR1END3_3", + "VFRAME_WR1END3" + ], + [ + "MONITOR_LOGIC_OUTS_B19_3", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "MONITOR_BYP4_3", + "VFRAME_BYP4" + ], + [ + "MONITOR_WW4A2_3", + "VFRAME_WW4A2" + ], + [ + "MONITOR_SE2A0_3", + "VFRAME_SE2A0" + ], + [ + "MONITOR_SW4END1_3", + "VFRAME_SW4END1" + ], + [ + "MONITOR_LOGIC_OUTS_B18_3", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "MONITOR_IMUX33_3", + "VFRAME_IMUX33" + ], + [ + "MONITOR_WW4A0_3", + "VFRAME_WW4A0" + ], + [ + "MONITOR_WW2END3_3", + "VFRAME_WW2END3" + ], + [ + "MONITOR_IMUX10_3", + "VFRAME_IMUX10" + ], + [ + "MONITOR_WW2A0_3", + "VFRAME_WW2A0" + ], + [ + "MONITOR_BYP3_3", + "VFRAME_BYP3" + ], + [ + "MONITOR_IMUX39_3", + "VFRAME_IMUX39" + ], + [ + "MONITOR_EL1BEG2_3", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_EE2A0_3", + "VFRAME_EE2A0" + ], + [ + "MONITOR_IMUX24_3", + "VFRAME_IMUX24" + ], + [ + "MONITOR_LOGIC_OUTS_B20_3", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "MONITOR_NE2A0_3", + "VFRAME_NE2A0" + ], + [ + "MONITOR_IMUX5_3", + "VFRAME_IMUX5" + ], + [ + "MONITOR_NE4C3_3", + "VFRAME_NE4C3" + ], + [ + "MONITOR_SE2A2_3", + "VFRAME_SE2A2" + ], + [ + "MONITOR_IMUX46_3", + "VFRAME_IMUX46" + ], + [ + "MONITOR_NW2A1_3", + "VFRAME_NW2A1" + ], + [ + "MONITOR_IMUX37_3", + "VFRAME_IMUX37" + ], + [ + "MONITOR_NW4A3_3", + "VFRAME_NW4A3" + ], + [ + "MONITOR_LOGIC_OUTS_B21_3", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "MONITOR_SW4A0_3", + "VFRAME_SW4A0" + ], + [ + "MONITOR_WW4END1_3", + "VFRAME_WW4END1" + ], + [ + "MONITOR_FAN0_3", + "VFRAME_FAN0" + ], + [ + "MONITOR_SE2A3_3", + "VFRAME_SE2A3" + ], + [ + "MONITOR_SW4A2_3", + "VFRAME_SW4A2" + ], + [ + "MONITOR_WW4B1_3", + "VFRAME_WW4B1" + ], + [ + "MONITOR_NE2A3_3", + "VFRAME_NE2A3" + ], + [ + "MONITOR_IMUX26_3", + "VFRAME_IMUX26" + ], + [ + "MONITOR_IMUX31_3", + "VFRAME_IMUX31" + ], + [ + "MONITOR_NE4C2_3", + "VFRAME_NE4C2" + ], + [ + "MONITOR_NE4BEG1_3", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_NW2A3_3", + "VFRAME_NW2A3" + ], + [ + "MONITOR_BYP1_3", + "VFRAME_BYP1" + ], + [ + "MONITOR_CLK0_3", + "VFRAME_CLK0" + ], + [ + "MONITOR_IMUX12_3", + "VFRAME_IMUX12" + ], + [ + "MONITOR_WW4A1_3", + "VFRAME_WW4A1" + ], + [ + "MONITOR_LH10_3", + "VFRAME_LH10" + ], + [ + "MONITOR_WW2END2_3", + "VFRAME_WW2END2" + ], + [ + "MONITOR_WW2END0_3", + "VFRAME_WW2END0" + ], + [ + "MONITOR_NE4C1_3", + "VFRAME_NE4C1" + ], + [ + "MONITOR_NE4BEG2_3", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_EE4B3_3", + "VFRAME_EE4B3" + ], + [ + "MONITOR_LOGIC_OUTS_B14_3", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "MONITOR_FAN5_3", + "VFRAME_FAN5" + ], + [ + "MONITOR_IMUX17_3", + "VFRAME_IMUX17" + ], + [ + "MONITOR_NE4C0_3", + "VFRAME_NE4C0" + ], + [ + "MONITOR_NW4END1_3", + "VFRAME_NW4END1" + ], + [ + "MONITOR_CTRL0_3", + "VFRAME_CTRL0" + ], + [ + "MONITOR_NW2A0_3", + "VFRAME_NW2A0" + ], + [ + "MONITOR_IMUX25_3", + "VFRAME_IMUX25" + ], + [ + "MONITOR_LH2_3", + "VFRAME_LH2" + ], + [ + "MONITOR_IMUX1_3", + "VFRAME_IMUX1" + ], + [ + "MONITOR_LH11_3", + "VFRAME_LH11" + ], + [ + "MONITOR_NW4END0_3", + "VFRAME_NW4END0" + ], + [ + "MONITOR_IMUX40_3", + "VFRAME_IMUX40" + ], + [ + "MONITOR_ER1BEG2_3", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_IMUX3_3", + "VFRAME_IMUX3" + ], + [ + "MONITOR_NE2A1_3", + "VFRAME_NE2A1" + ], + [ + "MONITOR_SE4BEG1_3", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_BYP7_3", + "VFRAME_BYP7" + ], + [ + "MONITOR_EE4A1_3", + "VFRAME_EE4A1" + ], + [ + "MONITOR_SW2A3_3", + "VFRAME_SW2A3" + ], + [ + "MONITOR_IMUX38_3", + "VFRAME_IMUX38" + ], + [ + "MONITOR_NW4END3_3", + "VFRAME_NW4END3" + ], + [ + "MONITOR_SW4END0_3", + "VFRAME_SW4END0" + ], + [ + "MONITOR_WW4END0_3", + "VFRAME_WW4END0" + ], + [ + "MONITOR_SW4END3_3", + "VFRAME_SW4END3" + ], + [ + "MONITOR_FAN7_3", + "VFRAME_FAN7" + ], + [ + "MONITOR_ER1BEG3_3", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_SE4C0_3", + "VFRAME_SE4C0" + ], + [ + "MONITOR_WW2A3_3", + "VFRAME_WW2A3" + ], + [ + "MONITOR_EL1BEG3_3", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_IMUX32_3", + "VFRAME_IMUX32" + ], + [ + "MONITOR_EE2A2_3", + "VFRAME_EE2A2" + ], + [ + "MONITOR_NW2A2_3", + "VFRAME_NW2A2" + ], + [ + "MONITOR_SE4BEG3_3", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_EE4A2_3", + "VFRAME_EE4A2" + ], + [ + "MONITOR_NE2A2_3", + "VFRAME_NE2A2" + ], + [ + "MONITOR_IMUX19_3", + "VFRAME_IMUX19" + ], + [ + "MONITOR_IMUX11_3", + "VFRAME_IMUX11" + ], + [ + "MONITOR_IMUX20_3", + "VFRAME_IMUX20" + ], + [ + "MONITOR_IMUX42_3", + "VFRAME_IMUX42" + ], + [ + "MONITOR_WW4B2_3", + "VFRAME_WW4B2" + ], + [ + "MONITOR_IMUX9_3", + "VFRAME_IMUX9" + ], + [ + "MONITOR_SW2A2_3", + "VFRAME_SW2A2" + ], + [ + "MONITOR_LH4_3", + "VFRAME_LH4" + ], + [ + "MONITOR_SE4C1_3", + "VFRAME_SE4C1" + ], + [ + "MONITOR_WW4END2_3", + "VFRAME_WW4END2" + ], + [ + "MONITOR_CTRL1_3", + "VFRAME_CTRL1" + ], + [ + "MONITOR_WW4A3_3", + "VFRAME_WW4A3" + ], + [ + "MONITOR_BYP0_3", + "VFRAME_BYP0" + ], + [ + "MONITOR_EE4BEG1_3", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX15_3", + "VFRAME_IMUX15" + ], + [ + "MONITOR_FAN3_3", + "VFRAME_FAN3" + ], + [ + "MONITOR_WW4C0_3", + "VFRAME_WW4C0" + ], + [ + "MONITOR_LOGIC_OUTS_B22_3", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "MONITOR_WL1END0_3", + "VFRAME_WL1END0" + ], + [ + "MONITOR_WW2END1_3", + "VFRAME_WW2END1" + ], + [ + "MONITOR_WW2A2_3", + "VFRAME_WW2A2" + ], + [ + "MONITOR_EE2A3_3", + "VFRAME_EE2A3" + ], + [ + "MONITOR_IMUX27_3", + "VFRAME_IMUX27" + ], + [ + "MONITOR_WR1END2_3", + "VFRAME_WR1END2" + ], + [ + "MONITOR_EL1BEG0_3", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_WW4C2_3", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE2BEG3_3", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_LOGIC_OUTS_B23_3", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "MONITOR_BYP2_3", + "VFRAME_BYP2" + ], + [ + "MONITOR_EE2BEG2_3", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_WW4B0_3", + "VFRAME_WW4B0" + ], + [ + "MONITOR_SE2A1_3", + "VFRAME_SE2A1" + ], + [ + "MONITOR_IMUX36_3", + "VFRAME_IMUX36" + ], + [ + "MONITOR_SE4BEG2_3", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_IMUX34_3", + "VFRAME_IMUX34" + ], + [ + "MONITOR_WR1END0_3", + "VFRAME_WR1END0" + ], + [ + "MONITOR_ER1BEG1_3", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_BYP6_3", + "VFRAME_BYP6" + ], + [ + "MONITOR_NW4END2_3", + "VFRAME_NW4END2" + ], + [ + "MONITOR_WL1END1_3", + "VFRAME_WL1END1" + ], + [ + "MONITOR_SE4C2_3", + "VFRAME_SE4C2" + ], + [ + "MONITOR_EE4BEG0_3", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_LH7_3", + "VFRAME_LH7" + ], + [ + "MONITOR_LH12_3", + "VFRAME_LH12" + ], + [ + "MONITOR_SW4A1_3", + "VFRAME_SW4A1" + ], + [ + "MONITOR_NW4A1_3", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WW4B3_3", + "VFRAME_WW4B3" + ], + [ + "MONITOR_WR1END1_3", + "VFRAME_WR1END1" + ], + [ + "MONITOR_EE4BEG3_3", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_IMUX47_3", + "VFRAME_IMUX47" + ], + [ + "MONITOR_EE2A1_3", + "VFRAME_EE2A1" + ], + [ + "MONITOR_LH8_3", + "VFRAME_LH8" + ], + [ + "MONITOR_WW4C3_3", + "VFRAME_WW4C3" + ], + [ + "MONITOR_WW4END3_3", + "VFRAME_WW4END3" + ], + [ + "MONITOR_EE4B1_3", + "VFRAME_EE4B1" + ], + [ + "MONITOR_LH3_3", + "VFRAME_LH3" + ], + [ + "MONITOR_LH6_3", + "VFRAME_LH6" + ], + [ + "MONITOR_EE4C3_3", + "VFRAME_EE4C3" + ], + [ + "MONITOR_EE4C1_3", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX21_3", + "VFRAME_IMUX21" + ], + [ + "MONITOR_EE4A3_3", + "VFRAME_EE4A3" + ], + [ + "MONITOR_EE4C0_3", + "VFRAME_EE4C0" + ], + [ + "MONITOR_IMUX14_3", + "VFRAME_IMUX14" + ], + [ + "MONITOR_EE2BEG0_3", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_IMUX4_3", + "VFRAME_IMUX4" + ], + [ + "MONITOR_IMUX43_3", + "VFRAME_IMUX43" + ], + [ + "MONITOR_EE4C2_3", + "VFRAME_EE4C2" + ], + [ + "MONITOR_IMUX13_3", + "VFRAME_IMUX13" + ], + [ + "MONITOR_SE4BEG0_3", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_NW4A2_3", + "VFRAME_NW4A2" + ], + [ + "MONITOR_IMUX41_3", + "VFRAME_IMUX41" + ], + [ + "MONITOR_WW2A1_3", + "VFRAME_WW2A1" + ] + ], + "tile_types": [ + "MONITOR_BOT_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + -8 + ], + "wire_pairs": [ + [ + "MONITOR_NE4BEG0_8", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_IMUX20_8", + "VFRAME_IMUX20" + ], + [ + "MONITOR_WW4A2_8", + "VFRAME_WW4A2" + ], + [ + "MONITOR_WR1END3_8", + "VFRAME_WR1END3" + ], + [ + "MONITOR_FAN0_8", + "VFRAME_FAN0" + ], + [ + "MONITOR_ER1BEG0_8", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_IMUX25_8", + "VFRAME_IMUX25" + ], + [ + "MONITOR_EE2BEG2_8", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_IMUX42_8", + "VFRAME_IMUX42" + ], + [ + "MONITOR_WW4B1_8", + "VFRAME_WW4B1" + ], + [ + "MONITOR_SW2A2_8", + "VFRAME_SW2A2" + ], + [ + "MONITOR_WW4C0_8", + "VFRAME_WW4C0" + ], + [ + "MONITOR_EE2A3_8", + "VFRAME_EE2A3" + ], + [ + "MONITOR_EE4B3_8", + "VFRAME_EE4B3" + ], + [ + "MONITOR_EE2A0_8", + "VFRAME_EE2A0" + ], + [ + "MONITOR_IMUX44_8", + "VFRAME_IMUX44" + ], + [ + "MONITOR_LH1_8", + "VFRAME_LH1" + ], + [ + "MONITOR_WL1END1_8", + "VFRAME_WL1END1" + ], + [ + "MONITOR_SW2A0_8", + "VFRAME_SW2A0" + ], + [ + "MONITOR_IMUX15_8", + "VFRAME_IMUX15" + ], + [ + "MONITOR_IMUX46_8", + "VFRAME_IMUX46" + ], + [ + "MONITOR_IMUX34_8", + "VFRAME_IMUX34" + ], + [ + "MONITOR_SE4BEG1_8", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_FAN6_8", + "VFRAME_FAN6" + ], + [ + "MONITOR_IMUX16_8", + "VFRAME_IMUX16" + ], + [ + "MONITOR_IMUX1_8", + "VFRAME_IMUX1" + ], + [ + "MONITOR_CTRL1_8", + "VFRAME_CTRL1" + ], + [ + "MONITOR_FAN2_8", + "VFRAME_FAN2" + ], + [ + "MONITOR_IMUX12_8", + "VFRAME_IMUX12" + ], + [ + "MONITOR_BYP0_8", + "VFRAME_BYP0" + ], + [ + "MONITOR_IMUX4_8", + "VFRAME_IMUX4" + ], + [ + "MONITOR_EE4BEG3_8", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_WR1END2_8", + "VFRAME_WR1END2" + ], + [ + "MONITOR_NE2A1_8", + "VFRAME_NE2A1" + ], + [ + "MONITOR_WW2END3_8", + "VFRAME_WW2END3" + ], + [ + "MONITOR_NE4C1_8", + "VFRAME_NE4C1" + ], + [ + "MONITOR_SE2A0_8", + "VFRAME_SE2A0" + ], + [ + "MONITOR_BYP4_8", + "VFRAME_BYP4" + ], + [ + "MONITOR_IMUX37_8", + "VFRAME_IMUX37" + ], + [ + "MONITOR_SE4C2_8", + "VFRAME_SE4C2" + ], + [ + "MONITOR_EE4A3_8", + "VFRAME_EE4A3" + ], + [ + "MONITOR_IMUX8_8", + "VFRAME_IMUX8" + ], + [ + "MONITOR_NW2A3_8", + "VFRAME_NW2A3" + ], + [ + "MONITOR_NW4END0_8", + "VFRAME_NW4END0" + ], + [ + "MONITOR_EE4A0_8", + "VFRAME_EE4A0" + ], + [ + "MONITOR_WW2A0_8", + "VFRAME_WW2A0" + ], + [ + "MONITOR_FAN7_8", + "VFRAME_FAN7" + ], + [ + "MONITOR_BYP1_8", + "VFRAME_BYP1" + ], + [ + "MONITOR_NE4C0_8", + "VFRAME_NE4C0" + ], + [ + "MONITOR_EL1BEG0_8", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_ER1BEG1_8", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_EE2A1_8", + "VFRAME_EE2A1" + ], + [ + "MONITOR_SW4A2_8", + "VFRAME_SW4A2" + ], + [ + "MONITOR_EE4B2_8", + "VFRAME_EE4B2" + ], + [ + "MONITOR_IMUX9_8", + "VFRAME_IMUX9" + ], + [ + "MONITOR_IMUX38_8", + "VFRAME_IMUX38" + ], + [ + "MONITOR_IMUX32_8", + "VFRAME_IMUX32" + ], + [ + "MONITOR_WW4END1_8", + "VFRAME_WW4END1" + ], + [ + "MONITOR_IMUX33_8", + "VFRAME_IMUX33" + ], + [ + "MONITOR_EE2BEG1_8", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_LH2_8", + "VFRAME_LH2" + ], + [ + "MONITOR_IMUX6_8", + "VFRAME_IMUX6" + ], + [ + "MONITOR_SE4BEG0_8", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_IMUX22_8", + "VFRAME_IMUX22" + ], + [ + "MONITOR_NE4BEG3_8", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_EE4B1_8", + "VFRAME_EE4B1" + ], + [ + "MONITOR_EE4C3_8", + "VFRAME_EE4C3" + ], + [ + "MONITOR_IMUX2_8", + "VFRAME_IMUX2" + ], + [ + "MONITOR_IMUX40_8", + "VFRAME_IMUX40" + ], + [ + "MONITOR_IMUX45_8", + "VFRAME_IMUX45" + ], + [ + "MONITOR_SW2A3_8", + "VFRAME_SW2A3" + ], + [ + "MONITOR_WL1END0_8", + "VFRAME_WL1END0" + ], + [ + "MONITOR_NW2A0_8", + "VFRAME_NW2A0" + ], + [ + "MONITOR_LH5_8", + "VFRAME_LH5" + ], + [ + "MONITOR_EL1BEG1_8", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_CTRL0_8", + "VFRAME_CTRL0" + ], + [ + "MONITOR_NW4END1_8", + "VFRAME_NW4END1" + ], + [ + "MONITOR_SE4C0_8", + "VFRAME_SE4C0" + ], + [ + "MONITOR_SE4BEG2_8", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_IMUX35_8", + "VFRAME_IMUX35" + ], + [ + "MONITOR_ER1BEG2_8", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_WW4END2_8", + "VFRAME_WW4END2" + ], + [ + "MONITOR_CLK1_8", + "VFRAME_CLK1" + ], + [ + "MONITOR_NE2A3_8", + "VFRAME_NE2A3" + ], + [ + "MONITOR_EE4BEG2_8", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_IMUX41_8", + "VFRAME_IMUX41" + ], + [ + "MONITOR_NE4C2_8", + "VFRAME_NE4C2" + ], + [ + "MONITOR_NE4BEG2_8", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_WW4C3_8", + "VFRAME_WW4C3" + ], + [ + "MONITOR_WL1END2_8", + "VFRAME_WL1END2" + ], + [ + "MONITOR_EL1BEG2_8", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_IMUX3_8", + "VFRAME_IMUX3" + ], + [ + "MONITOR_WW4B2_8", + "VFRAME_WW4B2" + ], + [ + "MONITOR_LH6_8", + "VFRAME_LH6" + ], + [ + "MONITOR_SE2A2_8", + "VFRAME_SE2A2" + ], + [ + "MONITOR_EE2BEG0_8", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_IMUX28_8", + "VFRAME_IMUX28" + ], + [ + "MONITOR_IMUX21_8", + "VFRAME_IMUX21" + ], + [ + "MONITOR_WW2END1_8", + "VFRAME_WW2END1" + ], + [ + "MONITOR_WW4B0_8", + "VFRAME_WW4B0" + ], + [ + "MONITOR_NE4BEG1_8", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_IMUX14_8", + "VFRAME_IMUX14" + ], + [ + "MONITOR_LH4_8", + "VFRAME_LH4" + ], + [ + "MONITOR_WW2END2_8", + "VFRAME_WW2END2" + ], + [ + "MONITOR_BYP5_8", + "VFRAME_BYP5" + ], + [ + "MONITOR_SW2A1_8", + "VFRAME_SW2A1" + ], + [ + "MONITOR_EE4B0_8", + "VFRAME_EE4B0" + ], + [ + "MONITOR_SE4BEG3_8", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_FAN1_8", + "VFRAME_FAN1" + ], + [ + "MONITOR_IMUX31_8", + "VFRAME_IMUX31" + ], + [ + "MONITOR_SE2A3_8", + "VFRAME_SE2A3" + ], + [ + "MONITOR_EE2BEG3_8", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_SE2A1_8", + "VFRAME_SE2A1" + ], + [ + "MONITOR_IMUX7_8", + "VFRAME_IMUX7" + ], + [ + "MONITOR_LH9_8", + "VFRAME_LH9" + ], + [ + "MONITOR_SW4END3_8", + "VFRAME_SW4END3" + ], + [ + "MONITOR_IMUX13_8", + "VFRAME_IMUX13" + ], + [ + "MONITOR_IMUX47_8", + "VFRAME_IMUX47" + ], + [ + "MONITOR_WW4B3_8", + "VFRAME_WW4B3" + ], + [ + "MONITOR_WW2A3_8", + "VFRAME_WW2A3" + ], + [ + "MONITOR_FAN5_8", + "VFRAME_FAN5" + ], + [ + "MONITOR_SE4C1_8", + "VFRAME_SE4C1" + ], + [ + "MONITOR_EE2A2_8", + "VFRAME_EE2A2" + ], + [ + "MONITOR_EE4C0_8", + "VFRAME_EE4C0" + ], + [ + "MONITOR_EE4BEG0_8", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_IMUX24_8", + "VFRAME_IMUX24" + ], + [ + "MONITOR_NW4END2_8", + "VFRAME_NW4END2" + ], + [ + "MONITOR_IMUX10_8", + "VFRAME_IMUX10" + ], + [ + "MONITOR_WW4END0_8", + "VFRAME_WW4END0" + ], + [ + "MONITOR_NW4END3_8", + "VFRAME_NW4END3" + ], + [ + "MONITOR_EL1BEG3_8", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_SW4END0_8", + "VFRAME_SW4END0" + ], + [ + "MONITOR_WW2A2_8", + "VFRAME_WW2A2" + ], + [ + "MONITOR_NW4A1_8", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WW4END3_8", + "VFRAME_WW4END3" + ], + [ + "MONITOR_SW4END1_8", + "VFRAME_SW4END1" + ], + [ + "MONITOR_LH10_8", + "VFRAME_LH10" + ], + [ + "MONITOR_WL1END3_8", + "VFRAME_WL1END3" + ], + [ + "MONITOR_BYP7_8", + "VFRAME_BYP7" + ], + [ + "MONITOR_CLK0_8", + "VFRAME_CLK0" + ], + [ + "MONITOR_WW4C2_8", + "VFRAME_WW4C2" + ], + [ + "MONITOR_WW4C1_8", + "VFRAME_WW4C1" + ], + [ + "MONITOR_SW4END2_8", + "VFRAME_SW4END2" + ], + [ + "MONITOR_NW2A1_8", + "VFRAME_NW2A1" + ], + [ + "MONITOR_IMUX26_8", + "VFRAME_IMUX26" + ], + [ + "MONITOR_FAN3_8", + "VFRAME_FAN3" + ], + [ + "MONITOR_WW4A3_8", + "VFRAME_WW4A3" + ], + [ + "MONITOR_BYP3_8", + "VFRAME_BYP3" + ], + [ + "MONITOR_LH11_8", + "VFRAME_LH11" + ], + [ + "MONITOR_IMUX29_8", + "VFRAME_IMUX29" + ], + [ + "MONITOR_ER1BEG3_8", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_LH3_8", + "VFRAME_LH3" + ], + [ + "MONITOR_NW4A2_8", + "VFRAME_NW4A2" + ], + [ + "MONITOR_BYP6_8", + "VFRAME_BYP6" + ], + [ + "MONITOR_IMUX39_8", + "VFRAME_IMUX39" + ], + [ + "MONITOR_IMUX17_8", + "VFRAME_IMUX17" + ], + [ + "MONITOR_NW4A3_8", + "VFRAME_NW4A3" + ], + [ + "MONITOR_WR1END1_8", + "VFRAME_WR1END1" + ], + [ + "MONITOR_EE4BEG1_8", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX30_8", + "VFRAME_IMUX30" + ], + [ + "MONITOR_FAN4_8", + "VFRAME_FAN4" + ], + [ + "MONITOR_WW2A1_8", + "VFRAME_WW2A1" + ], + [ + "MONITOR_SW4A1_8", + "VFRAME_SW4A1" + ], + [ + "MONITOR_LH8_8", + "VFRAME_LH8" + ], + [ + "MONITOR_LH12_8", + "VFRAME_LH12" + ], + [ + "MONITOR_LH7_8", + "VFRAME_LH7" + ], + [ + "MONITOR_IMUX19_8", + "VFRAME_IMUX19" + ], + [ + "MONITOR_IMUX11_8", + "VFRAME_IMUX11" + ], + [ + "MONITOR_IMUX5_8", + "VFRAME_IMUX5" + ], + [ + "MONITOR_NE2A2_8", + "VFRAME_NE2A2" + ], + [ + "MONITOR_IMUX36_8", + "VFRAME_IMUX36" + ], + [ + "MONITOR_WW2END0_8", + "VFRAME_WW2END0" + ], + [ + "MONITOR_WR1END0_8", + "VFRAME_WR1END0" + ], + [ + "MONITOR_NW2A2_8", + "VFRAME_NW2A2" + ], + [ + "MONITOR_NE4C3_8", + "VFRAME_NE4C3" + ], + [ + "MONITOR_SW4A0_8", + "VFRAME_SW4A0" + ], + [ + "MONITOR_IMUX43_8", + "VFRAME_IMUX43" + ], + [ + "MONITOR_NW4A0_8", + "VFRAME_NW4A0" + ], + [ + "MONITOR_EE4A1_8", + "VFRAME_EE4A1" + ], + [ + "MONITOR_SE4C3_8", + "VFRAME_SE4C3" + ], + [ + "MONITOR_NE2A0_8", + "VFRAME_NE2A0" + ], + [ + "MONITOR_IMUX0_8", + "VFRAME_IMUX0" + ], + [ + "MONITOR_WW4A0_8", + "VFRAME_WW4A0" + ], + [ + "MONITOR_IMUX23_8", + "VFRAME_IMUX23" + ], + [ + "MONITOR_EE4A2_8", + "VFRAME_EE4A2" + ], + [ + "MONITOR_IMUX18_8", + "VFRAME_IMUX18" + ], + [ + "MONITOR_BYP2_8", + "VFRAME_BYP2" + ], + [ + "MONITOR_SW4A3_8", + "VFRAME_SW4A3" + ], + [ + "MONITOR_EE4C1_8", + "VFRAME_EE4C1" + ], + [ + "MONITOR_EE4C2_8", + "VFRAME_EE4C2" + ], + [ + "MONITOR_IMUX27_8", + "VFRAME_IMUX27" + ], + [ + "MONITOR_WW4A1_8", + "VFRAME_WW4A1" + ] + ], + "tile_types": [ + "MONITOR_BOT_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + -2 + ], + "wire_pairs": [ + [ + "IOI_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1_1" + ], + [ + "IOI_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0_1" + ] + ], + "tile_types": [ + "RIOI", + "RIOI" + ] + }, + { + "grid_deltas": [ + 0, + -2 + ], + "wire_pairs": [ + [ + "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", + "CLK_FEED_R_CK_GCLK4" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ] + ], + "tile_types": [ + "CLK_BUFG_REBUF", + "CLK_FEED" + ] + }, + { + "grid_deltas": [ + -1, + 5 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX5_0", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_FAN1_0", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX11_0", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP5_0", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_FAN5_0", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX6_0", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX0_0", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX23_0", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX40_0", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_CTRL0_0", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX25_0", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B17_0", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B10_0", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_BYP4_0", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX4_0", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX3_0", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_FAN2_0", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX7_0", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX18_0", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX31_0", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX46_0", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX45_0", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_BYP3_0", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX14_0", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX24_0", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_FAN3_0", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN6_0", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_LOGIC_OUTS_B3_0", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_LOGIC_OUTS_B13_0", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B9_0", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX26_0", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX1_0", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX27_0", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX47_0", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX44_0", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_CLK1_0", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX39_0", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B7_0", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_FAN0_0", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX30_0", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_CTRL1_0", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX12_0", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B4_0", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_IMUX19_0", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX38_0", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_BYP2_0", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX22_0", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B5_0", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_FAN4_0", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX20_0", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX42_0", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_BYP7_0", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_BYP0_0", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX33_0", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX43_0", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_LOGIC_OUTS_B20_0", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX13_0", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_CLK0_0", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX21_0", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX35_0", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_LOGIC_OUTS_B6_0", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX36_0", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX41_0", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX28_0", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX10_0", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX9_0", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX32_0", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B16_0", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_BYP6_0", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX8_0", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_BYP1_0", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX15_0", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_LOGIC_OUTS_B19_0", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX17_0", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX29_0", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_LOGIC_OUTS_B1_0", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_FAN7_0", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B0_0", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX2_0", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX16_0", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX37_0", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX34_0", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_LOGIC_OUTS_B2_0", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_LOGIC_OUTS_B11_0", + "VBRK_EXT_LOGIC_OUTS_B11" + ] + ], + "tile_types": [ + "GTX_CHANNEL_0", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 0, + -9 + ], + "wire_pairs": [ + [ + "CMT_MMCM_PHASER_OUT_B_OCLK", + "CMT_PHASER_B_TOMMCM_OCLK" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM1", + "CMT_LR_LOWER_T_CLK_MMCM1" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM2", + "CMT_LR_LOWER_T_CLK_MMCM2" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM11", + "CMT_LR_LOWER_T_CLK_MMCM11" + ], + [ + "CMT_L_LOWER_B_CLK_PERF1", + "CMT_LR_LOWER_T_CLK_PERF1" + ], + [ + "CMT_MMCM_PHASERREF0", + "CMT_PHASER_DOWN_PHASERREF0" + ], + [ + "CMT_MMCM_PHASERREF_ABOVE1", + "CMT_PHASER_DOWN_PHASERREF_ABOVE1" + ], + [ + "MMCM_CLK_FREQ_BB_NS0", + "MMCM_CLK_FREQBB_REBUFOUT0" + ], + [ + "CMT_MMCM_PHASERA_DQSBUS1", + "CMT_PHASERA_DQSBUS1" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM12", + "CMT_LR_LOWER_T_CLK_MMCM12" + ], + [ + "CMT_MMCM_PHASER_IN_B_ICLK", + "CMT_PHASER_B_TOMMCM_ICLK" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM5", + "CMT_LR_LOWER_T_CLK_MMCM5" + ], + [ + "CMT_MMCM_A_WREN_TOFIFO", + "CMT_PHASER_IN_A_WREN_TOFIFO" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM4", + "CMT_LR_LOWER_T_CLK_MMCM4" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM0", + "CMT_LR_LOWER_T_CLK_MMCM0" + ], + [ + "MMCMOUT_CLK_FREQ_BB_1", + "MMCMOUT_CLK_FREQ_BB_REBUFIN1" + ], + [ + "MMCMOUT_CLK_FREQ_BB_2", + "MMCMOUT_CLK_FREQ_BB_REBUFIN2" + ], + [ + "CMT_MMCM_A_RDEN_TOFIFO", + "CMT_PHASER_OUT_A_RDEN_TOFIFO" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM3", + "CMT_LR_LOWER_T_CLK_MMCM3" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM9", + "CMT_LR_LOWER_T_CLK_MMCM9" + ], + [ + "CMT_MMCM_PHASERA_DQSBUS0", + "CMT_PHASERA_DQSBUS0" + ], + [ + "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "CMT_PHASER_B_TOMMCM_ICLKDIV" + ], + [ + "MMCMOUT_CLK_FREQ_BB_3", + "MMCMOUT_CLK_FREQ_BB_REBUFIN3" + ], + [ + "CMT_MMCM_PHASER_IN_A_ICLKDIV", + "CMT_PHASER_IN_A_ICLKDIV" + ], + [ + "CMT_MMCM_A_WRCLK_TOFIFO", + "CMT_PHASER_IN_A_WRCLK_TOFIFO" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM13", + "CMT_LR_LOWER_T_CLK_MMCM13" + ], + [ + "CMT_MMCM_PHASERA_CTSBUS0", + "CMT_PHASERA_CTSBUS0" + ], + [ + "MMCM_CLK_FREQ_BB_NS1", + "MMCM_CLK_FREQBB_REBUFOUT1" + ], + [ + "CMT_L_LOWER_B_CLK_IN1_HCLK", + "CMT_LR_LOWER_T_CLK_IN1_HCLK" + ], + [ + "CMT_MMCM_PHASERREF_ABOVE0", + "CMT_PHASER_DOWN_PHASERREF_ABOVE0" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM10", + "CMT_LR_LOWER_T_CLK_MMCM10" + ], + [ + "CMT_L_LOWER_B_CLK_PERF0", + "CMT_LR_LOWER_T_CLK_PERF0" + ], + [ + "CMT_MMCM_PHASER_OUT_A_OCLKDIV", + "CMT_PHASER_OUT_A_OCLKDIV" + ], + [ + "CMT_MMCM_PHASERREF1", + "CMT_PHASER_DOWN_PHASERREF1" + ], + [ + "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "CMT_PHASER_B_TOMMCM_OCLKDIV" + ], + [ + "MMCM_CLK_FREQ_BB_NS2", + "MMCM_CLK_FREQBB_REBUFOUT2" + ], + [ + "CMT_MMCM_PHASER_OUT_A_OCLK", + "CMT_PHASER_OUT_A_OCLK" + ], + [ + "CMT_L_LOWER_B_CLK_PERF2", + "CMT_LR_LOWER_T_CLK_PERF2" + ], + [ + "CMT_MMCM_PHASER_IN_A_ICLK", + "CMT_PHASER_IN_A_ICLK" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM6", + "CMT_LR_LOWER_T_CLK_MMCM6" + ], + [ + "CMT_L_LOWER_B_CLK_IN3_HCLK", + "CMT_LR_LOWER_T_CLK_IN3_HCLK" + ], + [ + "CMT_MMCM_PHASERA_DTSBUS0", + "CMT_PHASERA_DTSBUS0" + ], + [ + "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", + "CMT_PHASER_OUT_A_OCLK1X_90" + ], + [ + "CMT_MMCM_PHYCTRL_SYNC_BB_UP", + "CMT_PHASER_BOT_SYNC_BB" + ], + [ + "CMT_MMCM_PHASERA_CTSBUS1", + "CMT_PHASERA_CTSBUS1" + ], + [ + "CMT_L_LOWER_B_CLK_PERF3", + "CMT_LR_LOWER_T_CLK_PERF3" + ], + [ + "CMT_MMCM_PHASERREF_BELOW1", + "CMT_PHASER_DOWN_PHASERREF_BELOW1" + ], + [ + "MMCM_CLK_FREQ_BB_NS3", + "MMCM_CLK_FREQBB_REBUFOUT3" + ], + [ + "CMT_L_LOWER_B_CLK_IN2_HCLK", + "CMT_LR_LOWER_T_CLK_IN2_HCLK" + ], + [ + "MMCMOUT_CLK_FREQ_BB_0", + "MMCMOUT_CLK_FREQ_BB_REBUFIN0" + ], + [ + "CMT_MMCM_PHASERA_DTSBUS1", + "CMT_PHASERA_DTSBUS1" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM7", + "CMT_LR_LOWER_T_CLK_MMCM7" + ], + [ + "CMT_L_LOWER_B_CLK_MMCM8", + "CMT_LR_LOWER_T_CLK_MMCM8" + ], + [ + "CMT_MMCM_PHASERREF_BELOW0", + "CMT_PHASER_DOWN_PHASERREF_BELOW0" + ], + [ + "CMT_MMCM_A_RDCLK_TOFIFO", + "CMT_PHASER_OUT_A_RDCLK_TOFIFO" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "CMT_TOP_L_LOWER_T" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "CFG_CENTER_LH3_12", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_FAN6_12", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_SE2A2_12", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_BYP0_12", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX2_12", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_NE2A3_12", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX23_12", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW2A0_12", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_EE4B2_12", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_SW4A1_12", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_LH4_12", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_SW4END2_12", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_IMUX1_12", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_ER1BEG1_12", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_WL1END2_12", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_EL1BEG0_12", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_WW4B1_12", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_IMUX18_12", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX41_12", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX0_12", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_EE4BEG0_12", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_EE4C0_12", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_SW4A2_12", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_ER1BEG2_12", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX39_12", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_IMUX3_12", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_EE4A3_12", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX4_12", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_EE4B1_12", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_IMUX47_12", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_SW4A3_12", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_IMUX25_12", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_FAN2_12", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_LH11_12", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_FAN5_12", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_WW4C3_12", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_SE2A0_12", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_SW2A2_12", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_SE2A1_12", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NW4END3_12", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_NE4BEG2_12", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW4A3_12", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW2A1_12", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_WW4A2_12", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_IMUX36_12", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_NW4A1_12", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_WW2END3_12", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_IMUX10_12", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_NW2A1_12", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_IMUX9_12", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_SE2A3_12", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_WL1END3_12", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_LH9_12", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EE2BEG3_12", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_EE2A2_12", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_NE4BEG3_12", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_BYP5_12", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_IMUX32_12", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_FAN4_12", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_IMUX7_12", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_EL1BEG3_12", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_SE4BEG1_12", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_IMUX13_12", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_WW4END2_12", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX40_12", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_EE4C2_12", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX12_12", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_WR1END2_12", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_NE4C1_12", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_NW2A3_12", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_EE4C3_12", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_IMUX11_12", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_NW4A3_12", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_LH5_12", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX34_12", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_IMUX16_12", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_SW2A1_12", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_IMUX30_12", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_SE4C1_12", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_BYP3_12", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_EE2BEG0_12", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_WL1END1_12", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_WW2A3_12", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX15_12", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_BYP7_12", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_CTRL1_12", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_SE4C2_12", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_NW4A2_12", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_WW4A0_12", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_EE2A1_12", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_EE2BEG2_12", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_ER1BEG3_12", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_NE4C0_12", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_BYP1_12", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW4B2_12", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_NW2A2_12", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW2END0_12", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WW4A1_12", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_SE4C3_12", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_WW4END0_12", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_NE4C3_12", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_EE4C1_12", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_EE2BEG1_12", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_NE2A0_12", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX29_12", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_EL1BEG2_12", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_BYP2_12", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_SW2A3_12", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_EE2A3_12", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_IMUX28_12", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_EE4BEG3_12", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_EE4A1_12", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_NE4BEG1_12", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_EE4A2_12", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX17_12", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX14_12", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_EE4B0_12", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WR1END1_12", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NE2A2_12", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_NW4END1_12", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_IMUX38_12", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX27_12", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX5_12", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX6_12", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_SE4BEG3_12", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_EE4A0_12", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_LH7_12", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_EE4B3_12", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_SE4BEG0_12", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_FAN3_12", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_LH1_12", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_SW4END1_12", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_IMUX35_12", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_SW4A0_12", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_WW4B3_12", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_IMUX26_12", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_FAN1_12", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_LH10_12", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW4C0_12", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_WW4END3_12", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_SE4C0_12", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_WW2A2_12", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_IMUX21_12", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_WW4C2_12", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WR1END0_12", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_NW4A0_12", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_BYP6_12", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX42_12", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_EE2A0_12", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_IMUX45_12", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX31_12", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_IMUX46_12", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_CTRL0_12", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX20_12", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SW2A0_12", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_LH12_12", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_NE2A1_12", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_FAN7_12", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_LH2_12", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX33_12", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_FAN0_12", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_NW4END2_12", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_NW2A0_12", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_EE4BEG1_12", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_SW4END3_12", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX43_12", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_EL1BEG1_12", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_CLK1_12", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_WR1END3_12", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_WW4C1_12", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_IMUX8_12", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW2END2_12", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_LH6_12", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_BYP4_12", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WL1END0_12", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_WW4B0_12", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_CLK0_12", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_NE4C2_12", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_WW2END1_12", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_IMUX22_12", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX37_12", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_NE4BEG0_12", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_NW4END0_12", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX44_12", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WW4END1_12", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_SE4BEG2_12", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE4BEG2_12", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX19_12", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_LH8_12", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_SW4END0_12", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_ER1BEG0_12", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_IMUX24_12", + "VFRAME_IMUX24" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "BRKH_DSP_ACIN20", + "DSP_0_ACIN20" + ], + [ + "BRKH_DSP_ACIN13", + "DSP_0_ACIN13" + ], + [ + "BRKH_DSP_BCIN0", + "DSP_0_BCIN0" + ], + [ + "BRKH_DSP_PCIN42", + "DSP_0_PCIN42" + ], + [ + "BRKH_DSP_PCIN3", + "DSP_0_PCIN3" + ], + [ + "BRKH_DSP_PCIN7", + "DSP_0_PCIN7" + ], + [ + "BRKH_DSP_PCIN37", + "DSP_0_PCIN37" + ], + [ + "BRKH_DSP_ACIN24", + "DSP_0_ACIN24" + ], + [ + "BRKH_DSP_PCIN31", + "DSP_0_PCIN31" + ], + [ + "BRKH_DSP_ACIN25", + "DSP_0_ACIN25" + ], + [ + "BRKH_DSP_PCIN40", + "DSP_0_PCIN40" + ], + [ + "BRKH_DSP_BCIN7", + "DSP_0_BCIN7" + ], + [ + "BRKH_DSP_ACIN15", + "DSP_0_ACIN15" + ], + [ + "BRKH_DSP_BCIN4", + "DSP_0_BCIN4" + ], + [ + "BRKH_DSP_ACIN23", + "DSP_0_ACIN23" + ], + [ + "BRKH_DSP_ACIN6", + "DSP_0_ACIN6" + ], + [ + "BRKH_DSP_BCIN14", + "DSP_0_BCIN14" + ], + [ + "BRKH_DSP_PCIN16", + "DSP_0_PCIN16" + ], + [ + "BRKH_DSP_PCIN24", + "DSP_0_PCIN24" + ], + [ + "BRKH_DSP_BCIN8", + "DSP_0_BCIN8" + ], + [ + "BRKH_DSP_PCIN45", + "DSP_0_PCIN45" + ], + [ + "BRKH_DSP_BCIN15", + "DSP_0_BCIN15" + ], + [ + "BRKH_DSP_ACIN26", + "DSP_0_ACIN26" + ], + [ + "BRKH_DSP_PCIN41", + "DSP_0_PCIN41" + ], + [ + "BRKH_DSP_ACIN2", + "DSP_0_ACIN2" + ], + [ + "BRKH_DSP_PCIN5", + "DSP_0_PCIN5" + ], + [ + "BRKH_DSP_ACIN4", + "DSP_0_ACIN4" + ], + [ + "BRKH_DSP_BCIN10", + "DSP_0_BCIN10" + ], + [ + "BRKH_DSP_BCIN16", + "DSP_0_BCIN16" + ], + [ + "BRKH_DSP_ACIN8", + "DSP_0_ACIN8" + ], + [ + "BRKH_DSP_ACIN7", + "DSP_0_ACIN7" + ], + [ + "BRKH_DSP_ACIN16", + "DSP_0_ACIN16" + ], + [ + "BRKH_DSP_PCIN15", + "DSP_0_PCIN15" + ], + [ + "BRKH_DSP_MULTSIGNIN", + "DSP_0_MULTSIGNIN" + ], + [ + "BRKH_DSP_PCIN13", + "DSP_0_PCIN13" + ], + [ + "BRKH_DSP_ACIN27", + "DSP_0_ACIN27" + ], + [ + "BRKH_DSP_PCIN19", + "DSP_0_PCIN19" + ], + [ + "BRKH_DSP_PCIN38", + "DSP_0_PCIN38" + ], + [ + "BRKH_DSP_ACIN1", + "DSP_0_ACIN1" + ], + [ + "BRKH_DSP_ACIN17", + "DSP_0_ACIN17" + ], + [ + "BRKH_DSP_ACIN10", + "DSP_0_ACIN10" + ], + [ + "BRKH_DSP_BCIN13", + "DSP_0_BCIN13" + ], + [ + "BRKH_DSP_PCIN43", + "DSP_0_PCIN43" + ], + [ + "BRKH_DSP_PCIN1", + "DSP_0_PCIN1" + ], + [ + "BRKH_DSP_PCIN25", + "DSP_0_PCIN25" + ], + [ + "BRKH_DSP_BCIN6", + "DSP_0_BCIN6" + ], + [ + "BRKH_DSP_ACIN29", + "DSP_0_ACIN29" + ], + [ + "BRKH_DSP_PCIN6", + "DSP_0_PCIN6" + ], + [ + "BRKH_DSP_PCIN20", + "DSP_0_PCIN20" + ], + [ + "BRKH_DSP_PCIN12", + "DSP_0_PCIN12" + ], + [ + "BRKH_DSP_BCIN3", + "DSP_0_BCIN3" + ], + [ + "BRKH_DSP_BCIN11", + "DSP_0_BCIN11" + ], + [ + "BRKH_DSP_BCIN17", + "DSP_0_BCIN17" + ], + [ + "BRKH_DSP_PCIN35", + "DSP_0_PCIN35" + ], + [ + "BRKH_DSP_PCIN14", + "DSP_0_PCIN14" + ], + [ + "BRKH_DSP_PCIN28", + "DSP_0_PCIN28" + ], + [ + "BRKH_DSP_ACIN3", + "DSP_0_ACIN3" + ], + [ + "BRKH_DSP_PCIN46", + "DSP_0_PCIN46" + ], + [ + "BRKH_DSP_PCIN21", + "DSP_0_PCIN21" + ], + [ + "BRKH_DSP_PCIN36", + "DSP_0_PCIN36" + ], + [ + "BRKH_DSP_ACIN21", + "DSP_0_ACIN21" + ], + [ + "BRKH_DSP_ACIN28", + "DSP_0_ACIN28" + ], + [ + "BRKH_DSP_PCIN34", + "DSP_0_PCIN34" + ], + [ + "BRKH_DSP_BCIN5", + "DSP_0_BCIN5" + ], + [ + "BRKH_DSP_ACIN18", + "DSP_0_ACIN18" + ], + [ + "BRKH_DSP_BCIN2", + "DSP_0_BCIN2" + ], + [ + "BRKH_DSP_PCIN8", + "DSP_0_PCIN8" + ], + [ + "BRKH_DSP_BCIN9", + "DSP_0_BCIN9" + ], + [ + "BRKH_DSP_PCIN23", + "DSP_0_PCIN23" + ], + [ + "BRKH_DSP_ACIN22", + "DSP_0_ACIN22" + ], + [ + "BRKH_DSP_PCIN44", + "DSP_0_PCIN44" + ], + [ + "BRKH_DSP_BCIN12", + "DSP_0_BCIN12" + ], + [ + "BRKH_DSP_ACIN19", + "DSP_0_ACIN19" + ], + [ + "BRKH_DSP_PCIN17", + "DSP_0_PCIN17" + ], + [ + "BRKH_DSP_BCIN1", + "DSP_0_BCIN1" + ], + [ + "BRKH_DSP_CARRYCASCIN", + "DSP_0_CARRYCASCIN" + ], + [ + "BRKH_DSP_PCIN11", + "DSP_0_PCIN11" + ], + [ + "BRKH_DSP_ACIN0", + "DSP_0_ACIN0" + ], + [ + "BRKH_DSP_PCIN30", + "DSP_0_PCIN30" + ], + [ + "BRKH_DSP_PCIN10", + "DSP_0_PCIN10" + ], + [ + "BRKH_DSP_ACIN5", + "DSP_0_ACIN5" + ], + [ + "BRKH_DSP_ACIN9", + "DSP_0_ACIN9" + ], + [ + "BRKH_DSP_PCIN26", + "DSP_0_PCIN26" + ], + [ + "BRKH_DSP_PCIN32", + "DSP_0_PCIN32" + ], + [ + "BRKH_DSP_PCIN0", + "DSP_0_PCIN0" + ], + [ + "BRKH_DSP_ACIN11", + "DSP_0_ACIN11" + ], + [ + "BRKH_DSP_PCIN4", + "DSP_0_PCIN4" + ], + [ + "BRKH_DSP_PCIN39", + "DSP_0_PCIN39" + ], + [ + "BRKH_DSP_PCIN18", + "DSP_0_PCIN18" + ], + [ + "BRKH_DSP_PCIN22", + "DSP_0_PCIN22" + ], + [ + "BRKH_DSP_PCIN29", + "DSP_0_PCIN29" + ], + [ + "BRKH_DSP_ACIN12", + "DSP_0_ACIN12" + ], + [ + "BRKH_DSP_ACIN14", + "DSP_0_ACIN14" + ], + [ + "BRKH_DSP_PCIN33", + "DSP_0_PCIN33" + ], + [ + "BRKH_DSP_PCIN2", + "DSP_0_PCIN2" + ], + [ + "BRKH_DSP_PCIN9", + "DSP_0_PCIN9" + ], + [ + "BRKH_DSP_PCIN47", + "DSP_0_PCIN47" + ], + [ + "BRKH_DSP_PCIN27", + "DSP_0_PCIN27" + ] + ], + "tile_types": [ + "BRKH_DSP_L", + "DSP_L" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "CFG_CENTER_LH7_14", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_SE4BEG1_14", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SW2A1_14", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4B2_14", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_NE2A3_14", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_EE4B0_14", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_ER1BEG3_14", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_SE4BEG3_14", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_NE4BEG1_14", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WW4B2_14", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE4A3_14", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE4BEG1_14", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_NE4C3_14", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_EE4BEG3_14", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_EE4C3_14", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW2END0_14", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WW4B0_14", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_SW4END0_14", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_ER1BEG1_14", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_SE4C3_14", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_NE2A0_14", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EE2BEG0_14", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4C1_14", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SW4END3_14", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_SW2A2_14", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_SW4A3_14", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_SE2A1_14", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_EE4C2_14", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW4A0_14", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_EL1BEG2_14", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_ER1BEG0_14", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NE4BEG2_14", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_LH6_14", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_SE4BEG0_14", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_NE4C1_14", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_SE4C1_14", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_EE4B1_14", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EL1BEG0_14", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_WW4A0_14", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EL1BEG3_14", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_ER1BEG2_14", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_NW4A3_14", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WR1END1_14", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SW4A1_14", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_EE2BEG1_14", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_EL1BEG1_14", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_SE4BEG2_14", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_SE2A2_14", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_NW2A2_14", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_WW4END1_14", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_SW4END2_14", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WW4A3_14", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NW4END3_14", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_EE2A2_14", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_NW2A1_14", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4A0_14", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_SW2A3_14", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_WW2A2_14", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_SE4C2_14", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_WW2END1_14", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE2A3_14", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_SE2A3_14", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_WR1END2_14", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_WL1END3_14", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_SW2A0_14", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WL1END0_14", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_NW4A2_14", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WW4A1_14", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_SW4END1_14", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_LH5_14", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_LH10_14", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_EE4BEG0_14", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WR1END3_14", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE4C0_14", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_NE2A2_14", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_LH3_14", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_EE4BEG2_14", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WW4B3_14", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_NE4BEG3_14", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW2A3_14", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_SE2A0_14", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_NW2A0_14", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_SW4A2_14", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NW4END2_14", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_EE2A1_14", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_WW4C0_14", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NW2A3_14", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NW4END1_14", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_WL1END1_14", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_WW4C2_14", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_EE4B3_14", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_LH1_14", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_LH2_14", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_WR1END0_14", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH9_14", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_WW4A2_14", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WW2END2_14", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_WW4END3_14", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW4END0_14", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EE2BEG3_14", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_WW4END2_14", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_EE4C1_14", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_NE4C0_14", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_NW4END0_14", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SE4C0_14", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_EE2BEG2_14", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WL1END2_14", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_LH11_14", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW2END3_14", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_WW4B1_14", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_SW4A0_14", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE4A2_14", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_NE4BEG0_14", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_LH4_14", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE4A1_14", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_WW2A0_14", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_NW4A1_14", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_LH12_14", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_NE4C2_14", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW4C3_14", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_LH8_14", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_EE2A0_14", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW2A1_14", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_NE2A1_14", + "INT_FEEDTHRU_2_NE2A1" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -5, + 1 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_LH12", + "PCIE_LH12_1" + ], + [ + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_1" + ], + [ + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_1" + ], + [ + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT33", + "PCIE_IMUX33_L_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "PCIE_LOGIC_OUTS_B23_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT26", + "PCIE_IMUX26_L_1" + ], + [ + "INT_INTERFACE_BYP5", + "PCIE_BYP5_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT0", + "PCIE_IMUX0_L_1" + ], + [ + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_1" + ], + [ + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_1" + ], + [ + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT36", + "PCIE_IMUX36_L_1" + ], + [ + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_1" + ], + [ + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_1" + ], + [ + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "PCIE_LOGIC_OUTS_B19_L_1" + ], + [ + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_1" + ], + [ + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_1" + ], + [ + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_1" + ], + [ + "INT_INTERFACE_EL1BEG3", + "PCIE_EL1BEG3_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "PCIE_LOGIC_OUTS_B3_L_1" + ], + [ + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_1" + ], + [ + "INT_INTERFACE_EE4A0", + "PCIE_EE4A0_1" + ], + [ + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_1" + ], + [ + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT1", + "PCIE_IMUX1_L_1" + ], + [ + "INT_INTERFACE_EE4B0", + "PCIE_EE4B0_1" + ], + [ + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT17", + "PCIE_IMUX17_L_1" + ], + [ + "INT_INTERFACE_LH7", + "PCIE_LH7_1" + ], + [ + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_1" + ], + [ + "INT_INTERFACE_CTRL1", + "PCIE_CTRL1_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT37", + "PCIE_IMUX37_L_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "PCIE_LOGIC_OUTS_B10_L_1" + ], + [ + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_1" + ], + [ + "INT_INTERFACE_LH3", + "PCIE_LH3_1" + ], + [ + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_1" + ], + [ + "INT_INTERFACE_EE4C0", + "PCIE_EE4C0_1" + ], + [ + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_1" + ], + [ + "INT_INTERFACE_CLK0", + "PCIE_CLK0_L_1" + ], + [ + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_1" + ], + [ + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_1" + ], + [ + "INT_INTERFACE_LH11", + "PCIE_LH11_1" + ], + [ + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_1" + ], + [ + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_1" + ], + [ + "INT_INTERFACE_BYP4", + "PCIE_BYP4_L_1" + ], + [ + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "PCIE_LOGIC_OUTS_B21_L_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "PCIE_LOGIC_OUTS_B15_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT46", + "PCIE_IMUX46_L_1" + ], + [ + "INT_INTERFACE_EE2A3", + "PCIE_EE2A3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT34", + "PCIE_IMUX34_L_1" + ], + [ + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT13", + "PCIE_IMUX13_L_1" + ], + [ + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_1" + ], + [ + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "PCIE_LOGIC_OUTS_B18_L_1" + ], + [ + "INT_INTERFACE_LH9", + "PCIE_LH9_1" + ], + [ + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_1" + ], + [ + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_1" + ], + [ + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_1" + ], + [ + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_1" + ], + [ + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT11", + "PCIE_IMUX11_L_1" + ], + [ + "INT_INTERFACE_ER1BEG0", + "PCIE_ER1BEG0_1" + ], + [ + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_1" + ], + [ + "INT_INTERFACE_MONITOR_N", + "PCIE_MONITOR_N_1" + ], + [ + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_1" + ], + [ + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_1" + ], + [ + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_1" + ], + [ + "INT_INTERFACE_LH2", + "PCIE_LH2_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT15", + "PCIE_IMUX15_L_1" + ], + [ + "INT_INTERFACE_FAN6", + "PCIE_FAN6_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT5", + "PCIE_IMUX5_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT40", + "PCIE_IMUX40_L_1" + ], + [ + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT22", + "PCIE_IMUX22_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT23", + "PCIE_IMUX23_L_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "PCIE_LOGIC_OUTS_B7_L_1" + ], + [ + "INT_INTERFACE_EE2A1", + "PCIE_EE2A1_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT8", + "PCIE_IMUX8_L_1" + ], + [ + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT32", + "PCIE_IMUX32_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT20", + "PCIE_IMUX20_L_1" + ], + [ + "INT_INTERFACE_BYP6", + "PCIE_BYP6_L_1" + ], + [ + "INT_INTERFACE_FAN5", + "PCIE_FAN5_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT38", + "PCIE_IMUX38_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT30", + "PCIE_IMUX30_L_1" + ], + [ + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_1" + ], + [ + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_1" + ], + [ + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_1" + ], + [ + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_1" + ], + [ + "INT_INTERFACE_CTRL0", + "PCIE_CTRL0_L_1" + ], + [ + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT24", + "PCIE_IMUX24_L_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "PCIE_LOGIC_OUTS_B14_L_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "PCIE_LOGIC_OUTS_B12_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT27", + "PCIE_IMUX27_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT12", + "PCIE_IMUX12_L_1" + ], + [ + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_1" + ], + [ + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT31", + "PCIE_IMUX31_L_1" + ], + [ + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_1" + ], + [ + "INT_INTERFACE_FAN4", + "PCIE_FAN4_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT45", + "PCIE_IMUX45_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT28", + "PCIE_IMUX28_L_1" + ], + [ + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT7", + "PCIE_IMUX7_L_1" + ], + [ + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "PCIE_LOGIC_OUTS_B17_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT42", + "PCIE_IMUX42_L_1" + ], + [ + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT6", + "PCIE_IMUX6_L_1" + ], + [ + "INT_INTERFACE_FAN2", + "PCIE_FAN2_L_1" + ], + [ + "INT_INTERFACE_BYP2", + "PCIE_BYP2_L_1" + ], + [ + "INT_INTERFACE_EE2A2", + "PCIE_EE2A2_1" + ], + [ + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT25", + "PCIE_IMUX25_L_1" + ], + [ + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_1" + ], + [ + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "PCIE_LOGIC_OUTS_B5_L_1" + ], + [ + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_1" + ], + [ + "INT_INTERFACE_LH5", + "PCIE_LH5_1" + ], + [ + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_1" + ], + [ + "INT_INTERFACE_EE2BEG0", + "PCIE_EE2BEG0_1" + ], + [ + "INT_INTERFACE_EE4C2", + "PCIE_EE4C2_1" + ], + [ + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_1" + ], + [ + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_1" + ], + [ + "INT_INTERFACE_CLK1", + "PCIE_CLK1_L_1" + ], + [ + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_1" + ], + [ + "INT_INTERFACE_EE2BEG1", + "PCIE_EE2BEG1_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT39", + "PCIE_IMUX39_L_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "PCIE_LOGIC_OUTS_B2_L_1" + ], + [ + "INT_INTERFACE_BYP3", + "PCIE_BYP3_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT21", + "PCIE_IMUX21_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT2", + "PCIE_IMUX2_L_1" + ], + [ + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT18", + "PCIE_IMUX18_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT41", + "PCIE_IMUX41_L_1" + ], + [ + "INT_INTERFACE_BYP0", + "PCIE_BYP0_L_1" + ], + [ + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_1" + ], + [ + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_1" + ], + [ + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_1" + ], + [ + "INT_INTERFACE_LH8", + "PCIE_LH8_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "PCIE_LOGIC_OUTS_B16_L_1" + ], + [ + "INT_INTERFACE_EE4C1", + "PCIE_EE4C1_1" + ], + [ + "INT_INTERFACE_FAN1", + "PCIE_FAN1_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT14", + "PCIE_IMUX14_L_1" + ], + [ + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_1" + ], + [ + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_1" + ], + [ + "INT_INTERFACE_BYP1", + "PCIE_BYP1_L_1" + ], + [ + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_1" + ], + [ + "INT_INTERFACE_EE2BEG3", + "PCIE_EE2BEG3_1" + ], + [ + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT35", + "PCIE_IMUX35_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT43", + "PCIE_IMUX43_L_1" + ], + [ + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_1" + ], + [ + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "PCIE_LOGIC_OUTS_B8_L_1" + ], + [ + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_1" + ], + [ + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_1" + ], + [ + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_1" + ], + [ + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "PCIE_LOGIC_OUTS_B4_L_1" + ], + [ + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "PCIE_LOGIC_OUTS_B0_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT16", + "PCIE_IMUX16_L_1" + ], + [ + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_1" + ], + [ + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "PCIE_LOGIC_OUTS_B22_L_1" + ], + [ + "INT_INTERFACE_LH6", + "PCIE_LH6_1" + ], + [ + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_1" + ], + [ + "INT_INTERFACE_LH4", + "PCIE_LH4_1" + ], + [ + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_1" + ], + [ + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_1" + ], + [ + "INT_INTERFACE_LH1", + "PCIE_LH1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "PCIE_LOGIC_OUTS_B11_L_1" + ], + [ + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "PCIE_LOGIC_OUTS_B20_L_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "PCIE_LOGIC_OUTS_B9_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT3", + "PCIE_IMUX3_L_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "PCIE_LOGIC_OUTS_B1_L_1" + ], + [ + "INT_INTERFACE_EE2BEG2", + "PCIE_EE2BEG2_1" + ], + [ + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_1" + ], + [ + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_1" + ], + [ + "INT_INTERFACE_FAN3", + "PCIE_FAN3_L_1" + ], + [ + "INT_INTERFACE_EE4A1", + "PCIE_EE4A1_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT44", + "PCIE_IMUX44_L_1" + ], + [ + "INT_INTERFACE_LH10", + "PCIE_LH10_1" + ], + [ + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_1" + ], + [ + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_1" + ], + [ + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_1" + ], + [ + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "PCIE_LOGIC_OUTS_B6_L_1" + ], + [ + "INT_INTERFACE_EE4A3", + "PCIE_EE4A3_1" + ], + [ + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_1" + ], + [ + "INT_INTERFACE_MONITOR_P", + "PCIE_MONITOR_P_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT19", + "PCIE_IMUX19_L_1" + ], + [ + "INT_INTERFACE_BYP7", + "PCIE_BYP7_L_1" + ], + [ + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_1" + ], + [ + "INT_INTERFACE_FAN0", + "PCIE_FAN0_L_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "PCIE_LOGIC_OUTS_B13_L_1" + ], + [ + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_1" + ], + [ + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT29", + "PCIE_IMUX29_L_1" + ], + [ + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_1" + ], + [ + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_1" + ], + [ + "INT_INTERFACE_FAN7", + "PCIE_FAN7_L_1" + ], + [ + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_1" + ], + [ + "INT_INTERFACE_EE2A0", + "PCIE_EE2A0_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT10", + "PCIE_IMUX10_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT4", + "PCIE_IMUX4_L_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT47", + "PCIE_IMUX47_L_1" + ], + [ + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_1" + ], + [ + "PCIE_INT_INTERFACE_IMUX_L_OUT9", + "PCIE_IMUX9_L_1" + ], + [ + "INT_INTERFACE_EE4A2", + "PCIE_EE4A2_1" + ], + [ + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_1" + ] + ], + "tile_types": [ + "PCIE_INT_INTERFACE_L", + "PCIE_TOP" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CMT_TOP_EE2BEG2_9", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NE4C0_9", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EE2A0_9", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_9", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SE4BEG2_9", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_NE2A2_9", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW2A2_9", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_LH6_9", + "VBRK_LH6" + ], + [ + "CMT_TOP_EE4B1_9", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW4A1_9", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SW4A2_9", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WR1END2_9", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH8_9", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A3_9", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4BEG3_9", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WW2END2_9", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2A1_9", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4A0_9", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4C1_9", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NE4C3_9", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW2A0_9", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_9", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2END0_9", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4C2_9", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A3_9", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_ER1BEG0_9", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EL1BEG1_9", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG0_9", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH3_9", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END2_9", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH2_9", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW4A3_9", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_MONITOR_N_9", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_SW2A2_9", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4A2_9", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END3_9", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE2A3_9", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4BEG2_9", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4END0_9", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SW4A0_9", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4C1_9", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A1_9", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4END2_9", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EL1BEG3_9", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_9", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW2A0_9", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4B0_9", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE4C0_9", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE4B3_9", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW4A1_9", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_LH4_9", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW4C1_9", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_EE2BEG1_9", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4A0_9", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4BEG0_9", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_9", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2A2_9", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EE4A1_9", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4END0_9", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW4B1_9", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4A3_9", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END3_9", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH11_9", + "VBRK_LH11" + ], + [ + "CMT_TOP_SW4END3_9", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_9", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END1_9", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_LH12_9", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C1_9", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE4C3_9", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_SE2A1_9", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE4A0_9", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_EE2BEG3_9", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END1_9", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A1_9", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE2BEG0_9", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE2A2_9", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END3_9", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_ER1BEG3_9", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NE2A3_9", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW2A3_9", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_9", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_MONITOR_P_9", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_LH9_9", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4B0_9", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A0_9", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NE4BEG2_9", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A2_9", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_WW4C0_9", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SW2A1_9", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH5_9", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END0_9", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NE4BEG1_9", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_9", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A2_9", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4BEG1_9", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C0_9", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_WW4END2_9", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_WW4END1_9", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NW2A0_9", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4C2_9", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_WW4B3_9", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WR1END0_9", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW2A3_9", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW2A2_9", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_EE4BEG3_9", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C2_9", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_SE4BEG1_9", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_9", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_NE2A0_9", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4B2_9", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WL1END2_9", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG0_9", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG2_9", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4C3_9", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4A1_9", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH1_9", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW4END0_9", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_EE4A3_9", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_LH10_9", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW2END1_9", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WL1END3_9", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_EE2A1_9", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4C3_9", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WR1END3_9", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SW2A3_9", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH7_9", + "VBRK_LH7" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 4 + ], + "wire_pairs": [ + [ + "CLK_HROW_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_SW4A1_0", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_MONITOR_P_0", + "VBRK_MONITOR_P" + ], + [ + "CLK_HROW_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_LH4_0", + "VBRK_LH4" + ], + [ + "CLK_HROW_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_LH11_0", + "VBRK_LH11" + ], + [ + "CLK_HROW_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_MONITOR_N_0", + "VBRK_MONITOR_N" + ], + [ + "CLK_HROW_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_LH6_0", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_LH1_0", + "VBRK_LH1" + ], + [ + "CLK_HROW_LH10_0", + "VBRK_LH10" + ], + [ + "CLK_HROW_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_LH5_0", + "VBRK_LH5" + ], + [ + "CLK_HROW_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_LH8_0", + "VBRK_LH8" + ], + [ + "CLK_HROW_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_LH2_0", + "VBRK_LH2" + ], + [ + "CLK_HROW_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_LH12_0", + "VBRK_LH12" + ], + [ + "CLK_HROW_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_LH3_0", + "VBRK_LH3" + ], + [ + "CLK_HROW_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_LH7_0", + "VBRK_LH7" + ], + [ + "CLK_HROW_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_LH9_0", + "VBRK_LH9" + ], + [ + "CLK_HROW_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_WW4C2_0", + "VBRK_WW4C2" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "DSP_WW4C0_1", + "INT_INTERFACE_WW4C0" + ], + [ + "DSP_SW4A2_1", + "INT_INTERFACE_SW4A2" + ], + [ + "DSP_WW4A1_1", + "INT_INTERFACE_WW4A1" + ], + [ + "DSP_IMUX39_1", + "INT_INTERFACE_IMUX39" + ], + [ + "DSP_LOGIC_OUTS_B21_1", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "DSP_NW4END2_1", + "INT_INTERFACE_NW4END2" + ], + [ + "DSP_NE4BEG2_1", + "INT_INTERFACE_NE4BEG2" + ], + [ + "DSP_BYP5_1", + "INT_INTERFACE_BYP5" + ], + [ + "DSP_EE2BEG3_1", + "INT_INTERFACE_EE2BEG3" + ], + [ + "DSP_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "DSP_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "DSP_EE4C3_1", + "INT_INTERFACE_EE4C3" + ], + [ + "DSP_BYP4_1", + "INT_INTERFACE_BYP4" + ], + [ + "DSP_SW4END3_1", + "INT_INTERFACE_SW4END3" + ], + [ + "DSP_EE4C2_1", + "INT_INTERFACE_EE4C2" + ], + [ + "DSP_ER1BEG3_1", + "INT_INTERFACE_ER1BEG3" + ], + [ + "DSP_NE4BEG0_1", + "INT_INTERFACE_NE4BEG0" + ], + [ + "DSP_IMUX6_1", + "INT_INTERFACE_IMUX6" + ], + [ + "DSP_IMUX44_1", + "INT_INTERFACE_IMUX44" + ], + [ + "DSP_IMUX15_1", + "INT_INTERFACE_IMUX15" + ], + [ + "DSP_LOGIC_OUTS_B2_1", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "DSP_FAN3_1", + "INT_INTERFACE_FAN3" + ], + [ + "DSP_WL1END2_1", + "INT_INTERFACE_WL1END2" + ], + [ + "DSP_IMUX8_1", + "INT_INTERFACE_IMUX8" + ], + [ + "DSP_IMUX2_1", + "INT_INTERFACE_IMUX2" + ], + [ + "DSP_NW4END0_1", + "INT_INTERFACE_NW4END0" + ], + [ + "DSP_BYP3_1", + "INT_INTERFACE_BYP3" + ], + [ + "DSP_SE4BEG0_1", + "INT_INTERFACE_SE4BEG0" + ], + [ + "DSP_WR1END2_1", + "INT_INTERFACE_WR1END2" + ], + [ + "DSP_FAN0_1", + "INT_INTERFACE_FAN0" + ], + [ + "DSP_EE4C0_1", + "INT_INTERFACE_EE4C0" + ], + [ + "DSP_BYP1_1", + "INT_INTERFACE_BYP1" + ], + [ + "DSP_WW4A0_1", + "INT_INTERFACE_WW4A0" + ], + [ + "DSP_EE2A3_1", + "INT_INTERFACE_EE2A3" + ], + [ + "DSP_EE4A2_1", + "INT_INTERFACE_EE4A2" + ], + [ + "DSP_IMUX3_1", + "INT_INTERFACE_IMUX3" + ], + [ + "DSP_NE4BEG3_1", + "INT_INTERFACE_NE4BEG3" + ], + [ + "DSP_LH12_1", + "INT_INTERFACE_LH12" + ], + [ + "DSP_WW4C1_1", + "INT_INTERFACE_WW4C1" + ], + [ + "DSP_IMUX1_1", + "INT_INTERFACE_IMUX1" + ], + [ + "DSP_NW4A1_1", + "INT_INTERFACE_NW4A1" + ], + [ + "DSP_EE4C1_1", + "INT_INTERFACE_EE4C1" + ], + [ + "DSP_WL1END1_1", + "INT_INTERFACE_WL1END1" + ], + [ + "DSP_SW4A1_1", + "INT_INTERFACE_SW4A1" + ], + [ + "DSP_SE2A3_1", + "INT_INTERFACE_SE2A3" + ], + [ + "DSP_IMUX29_1", + "INT_INTERFACE_IMUX29" + ], + [ + "DSP_EE4B3_1", + "INT_INTERFACE_EE4B3" + ], + [ + "DSP_IMUX38_1", + "INT_INTERFACE_IMUX38" + ], + [ + "DSP_SE4BEG2_1", + "INT_INTERFACE_SE4BEG2" + ], + [ + "DSP_NE2A0_1", + "INT_INTERFACE_NE2A0" + ], + [ + "DSP_EE2BEG1_1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "DSP_IMUX12_1", + "INT_INTERFACE_IMUX12" + ], + [ + "DSP_FAN2_1", + "INT_INTERFACE_FAN2" + ], + [ + "DSP_IMUX46_1", + "INT_INTERFACE_IMUX46" + ], + [ + "DSP_NE2A1_1", + "INT_INTERFACE_NE2A1" + ], + [ + "DSP_WR1END0_1", + "INT_INTERFACE_WR1END0" + ], + [ + "DSP_SW2A2_1", + "INT_INTERFACE_SW2A2" + ], + [ + "DSP_LH8_1", + "INT_INTERFACE_LH8" + ], + [ + "DSP_WW4B1_1", + "INT_INTERFACE_WW4B1" + ], + [ + "DSP_LOGIC_OUTS_B18_1", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "DSP_LOGIC_OUTS_B12_1", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "DSP_NE4BEG1_1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "DSP_IMUX18_1", + "INT_INTERFACE_IMUX18" + ], + [ + "DSP_SW2A0_1", + "INT_INTERFACE_SW2A0" + ], + [ + "DSP_MONITOR_P_1", + "INT_INTERFACE_MONITOR_P" + ], + [ + "DSP_IMUX31_1", + "INT_INTERFACE_IMUX31" + ], + [ + "DSP_SE4BEG1_1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "DSP_NW2A1_1", + "INT_INTERFACE_NW2A1" + ], + [ + "DSP_IMUX28_1", + "INT_INTERFACE_IMUX28" + ], + [ + "DSP_NE4C1_1", + "INT_INTERFACE_NE4C1" + ], + [ + "DSP_SE4C2_1", + "INT_INTERFACE_SE4C2" + ], + [ + "DSP_IMUX27_1", + "INT_INTERFACE_IMUX27" + ], + [ + "DSP_IMUX24_1", + "INT_INTERFACE_IMUX24" + ], + [ + "DSP_WW2END3_1", + "INT_INTERFACE_WW2END3" + ], + [ + "DSP_LH11_1", + "INT_INTERFACE_LH11" + ], + [ + "DSP_IMUX22_1", + "INT_INTERFACE_IMUX22" + ], + [ + "DSP_SE2A0_1", + "INT_INTERFACE_SE2A0" + ], + [ + "DSP_CTRL0_1", + "INT_INTERFACE_CTRL0" + ], + [ + "DSP_WW4B2_1", + "INT_INTERFACE_WW4B2" + ], + [ + "DSP_SW4A3_1", + "INT_INTERFACE_SW4A3" + ], + [ + "DSP_IMUX41_1", + "INT_INTERFACE_IMUX41" + ], + [ + "DSP_LH7_1", + "INT_INTERFACE_LH7" + ], + [ + "DSP_EE4BEG2_1", + "INT_INTERFACE_EE4BEG2" + ], + [ + "DSP_LOGIC_OUTS_B23_1", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "DSP_MONITOR_N_1", + "INT_INTERFACE_MONITOR_N" + ], + [ + "DSP_IMUX13_1", + "INT_INTERFACE_IMUX13" + ], + [ + "DSP_WW4C2_1", + "INT_INTERFACE_WW4C2" + ], + [ + "DSP_IMUX10_1", + "INT_INTERFACE_IMUX10" + ], + [ + "DSP_CLK0_1", + "INT_INTERFACE_CLK0" + ], + [ + "DSP_WW4C3_1", + "INT_INTERFACE_WW4C3" + ], + [ + "DSP_IMUX34_1", + "INT_INTERFACE_IMUX34" + ], + [ + "DSP_IMUX37_1", + "INT_INTERFACE_IMUX37" + ], + [ + "DSP_IMUX16_1", + "INT_INTERFACE_IMUX16" + ], + [ + "DSP_EL1BEG1_1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "DSP_IMUX45_1", + "INT_INTERFACE_IMUX45" + ], + [ + "DSP_LH5_1", + "INT_INTERFACE_LH5" + ], + [ + "DSP_LOGIC_OUTS_B3_1", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "DSP_WW4B3_1", + "INT_INTERFACE_WW4B3" + ], + [ + "DSP_SW2A1_1", + "INT_INTERFACE_SW2A1" + ], + [ + "DSP_LOGIC_OUTS_B22_1", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "DSP_EE4B2_1", + "INT_INTERFACE_EE4B2" + ], + [ + "DSP_NW4END1_1", + "INT_INTERFACE_NW4END1" + ], + [ + "DSP_WR1END1_1", + "INT_INTERFACE_WR1END1" + ], + [ + "DSP_EE4A0_1", + "INT_INTERFACE_EE4A0" + ], + [ + "DSP_WL1END0_1", + "INT_INTERFACE_WL1END0" + ], + [ + "DSP_LOGIC_OUTS_B4_1", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "DSP_LH4_1", + "INT_INTERFACE_LH4" + ], + [ + "DSP_ER1BEG2_1", + "INT_INTERFACE_ER1BEG2" + ], + [ + "DSP_CLK1_1", + "INT_INTERFACE_CLK1" + ], + [ + "DSP_SE4BEG3_1", + "INT_INTERFACE_SE4BEG3" + ], + [ + "DSP_SE4C0_1", + "INT_INTERFACE_SE4C0" + ], + [ + "DSP_EE4B1_1", + "INT_INTERFACE_EE4B1" + ], + [ + "DSP_LOGIC_OUTS_B13_1", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "DSP_EE4BEG1_1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "DSP_EE2A2_1", + "INT_INTERFACE_EE2A2" + ], + [ + "DSP_WW4END3_1", + "INT_INTERFACE_WW4END3" + ], + [ + "DSP_LOGIC_OUTS_B16_1", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "DSP_LOGIC_OUTS_B5_1", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "DSP_SW4A0_1", + "INT_INTERFACE_SW4A0" + ], + [ + "DSP_LOGIC_OUTS_B1_1", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "DSP_WR1END3_1", + "INT_INTERFACE_WR1END3" + ], + [ + "DSP_SE2A1_1", + "INT_INTERFACE_SE2A1" + ], + [ + "DSP_IMUX36_1", + "INT_INTERFACE_IMUX36" + ], + [ + "DSP_SW4END1_1", + "INT_INTERFACE_SW4END1" + ], + [ + "DSP_IMUX0_1", + "INT_INTERFACE_IMUX0" + ], + [ + "DSP_FAN6_1", + "INT_INTERFACE_FAN6" + ], + [ + "DSP_SE2A2_1", + "INT_INTERFACE_SE2A2" + ], + [ + "DSP_LH6_1", + "INT_INTERFACE_LH6" + ], + [ + "DSP_EE4A1_1", + "INT_INTERFACE_EE4A1" + ], + [ + "DSP_EE2BEG2_1", + "INT_INTERFACE_EE2BEG2" + ], + [ + "DSP_ER1BEG1_1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "DSP_NE2A3_1", + "INT_INTERFACE_NE2A3" + ], + [ + "DSP_EE4A3_1", + "INT_INTERFACE_EE4A3" + ], + [ + "DSP_WW4B0_1", + "INT_INTERFACE_WW4B0" + ], + [ + "DSP_NE2A2_1", + "INT_INTERFACE_NE2A2" + ], + [ + "DSP_NW4A3_1", + "INT_INTERFACE_NW4A3" + ], + [ + "DSP_LOGIC_OUTS_B11_1", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "DSP_SW4END0_1", + "INT_INTERFACE_SW4END0" + ], + [ + "DSP_LH9_1", + "INT_INTERFACE_LH9" + ], + [ + "DSP_SW4END2_1", + "INT_INTERFACE_SW4END2" + ], + [ + "DSP_IMUX30_1", + "INT_INTERFACE_IMUX30" + ], + [ + "DSP_FAN5_1", + "INT_INTERFACE_FAN5" + ], + [ + "DSP_WW2A0_1", + "INT_INTERFACE_WW2A0" + ], + [ + "DSP_EE2BEG0_1", + "INT_INTERFACE_EE2BEG0" + ], + [ + "DSP_EE4B0_1", + "INT_INTERFACE_EE4B0" + ], + [ + "DSP_CTRL1_1", + "INT_INTERFACE_CTRL1" + ], + [ + "DSP_IMUX9_1", + "INT_INTERFACE_IMUX9" + ], + [ + "DSP_IMUX14_1", + "INT_INTERFACE_IMUX14" + ], + [ + "DSP_EE4BEG0_1", + "INT_INTERFACE_EE4BEG0" + ], + [ + "DSP_LOGIC_OUTS_B0_1", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "DSP_EE4BEG3_1", + "INT_INTERFACE_EE4BEG3" + ], + [ + "DSP_WW2END1_1", + "INT_INTERFACE_WW2END1" + ], + [ + "DSP_WW4END1_1", + "INT_INTERFACE_WW4END1" + ], + [ + "DSP_BYP2_1", + "INT_INTERFACE_BYP2" + ], + [ + "DSP_IMUX35_1", + "INT_INTERFACE_IMUX35" + ], + [ + "DSP_LOGIC_OUTS_B19_1", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "DSP_NW4A0_1", + "INT_INTERFACE_NW4A0" + ], + [ + "DSP_IMUX32_1", + "INT_INTERFACE_IMUX32" + ], + [ + "DSP_IMUX17_1", + "INT_INTERFACE_IMUX17" + ], + [ + "DSP_BYP0_1", + "INT_INTERFACE_BYP0" + ], + [ + "DSP_NW2A2_1", + "INT_INTERFACE_NW2A2" + ], + [ + "DSP_IMUX11_1", + "INT_INTERFACE_IMUX11" + ], + [ + "DSP_EL1BEG3_1", + "INT_INTERFACE_EL1BEG3" + ], + [ + "DSP_LH10_1", + "INT_INTERFACE_LH10" + ], + [ + "DSP_EE2A1_1", + "INT_INTERFACE_EE2A1" + ], + [ + "DSP_IMUX47_1", + "INT_INTERFACE_IMUX47" + ], + [ + "DSP_BYP6_1", + "INT_INTERFACE_BYP6" + ], + [ + "DSP_FAN4_1", + "INT_INTERFACE_FAN4" + ], + [ + "DSP_ER1BEG0_1", + "INT_INTERFACE_ER1BEG0" + ], + [ + "DSP_IMUX4_1", + "INT_INTERFACE_IMUX4" + ], + [ + "DSP_LOGIC_OUTS_B7_1", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "DSP_FAN1_1", + "INT_INTERFACE_FAN1" + ], + [ + "DSP_IMUX26_1", + "INT_INTERFACE_IMUX26" + ], + [ + "DSP_LOGIC_OUTS_B17_1", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "DSP_IMUX7_1", + "INT_INTERFACE_IMUX7" + ], + [ + "DSP_SE4C3_1", + "INT_INTERFACE_SE4C3" + ], + [ + "DSP_IMUX33_1", + "INT_INTERFACE_IMUX33" + ], + [ + "DSP_IMUX43_1", + "INT_INTERFACE_IMUX43" + ], + [ + "DSP_FAN7_1", + "INT_INTERFACE_FAN7" + ], + [ + "DSP_WW4END0_1", + "INT_INTERFACE_WW4END0" + ], + [ + "DSP_NW2A0_1", + "INT_INTERFACE_NW2A0" + ], + [ + "DSP_EL1BEG2_1", + "INT_INTERFACE_EL1BEG2" + ], + [ + "DSP_WW2END0_1", + "INT_INTERFACE_WW2END0" + ], + [ + "DSP_EE2A0_1", + "INT_INTERFACE_EE2A0" + ], + [ + "DSP_IMUX42_1", + "INT_INTERFACE_IMUX42" + ], + [ + "DSP_IMUX25_1", + "INT_INTERFACE_IMUX25" + ], + [ + "DSP_NE4C3_1", + "INT_INTERFACE_NE4C3" + ], + [ + "DSP_LH1_1", + "INT_INTERFACE_LH1" + ], + [ + "DSP_LOGIC_OUTS_B20_1", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "DSP_LH2_1", + "INT_INTERFACE_LH2" + ], + [ + "DSP_NE4C2_1", + "INT_INTERFACE_NE4C2" + ], + [ + "DSP_IMUX23_1", + "INT_INTERFACE_IMUX23" + ], + [ + "DSP_WL1END3_1", + "INT_INTERFACE_WL1END3" + ], + [ + "DSP_BYP7_1", + "INT_INTERFACE_BYP7" + ], + [ + "DSP_NE4C0_1", + "INT_INTERFACE_NE4C0" + ], + [ + "DSP_SE4C1_1", + "INT_INTERFACE_SE4C1" + ], + [ + "DSP_IMUX5_1", + "INT_INTERFACE_IMUX5" + ], + [ + "DSP_EL1BEG0_1", + "INT_INTERFACE_EL1BEG0" + ], + [ + "DSP_IMUX20_1", + "INT_INTERFACE_IMUX20" + ], + [ + "DSP_LOGIC_OUTS_B6_1", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "DSP_WW2A3_1", + "INT_INTERFACE_WW2A3" + ], + [ + "DSP_WW4A3_1", + "INT_INTERFACE_WW4A3" + ], + [ + "DSP_IMUX21_1", + "INT_INTERFACE_IMUX21" + ], + [ + "DSP_IMUX40_1", + "INT_INTERFACE_IMUX40" + ], + [ + "DSP_WW4END2_1", + "INT_INTERFACE_WW4END2" + ], + [ + "DSP_SW2A3_1", + "INT_INTERFACE_SW2A3" + ], + [ + "DSP_IMUX19_1", + "INT_INTERFACE_IMUX19" + ], + [ + "DSP_NW2A3_1", + "INT_INTERFACE_NW2A3" + ], + [ + "DSP_NW4END3_1", + "INT_INTERFACE_NW4END3" + ], + [ + "DSP_WW2END2_1", + "INT_INTERFACE_WW2END2" + ], + [ + "DSP_LH3_1", + "INT_INTERFACE_LH3" + ], + [ + "DSP_WW4A2_1", + "INT_INTERFACE_WW4A2" + ], + [ + "DSP_LOGIC_OUTS_B10_1", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "DSP_NW4A2_1", + "INT_INTERFACE_NW4A2" + ] + ], + "tile_types": [ + "DSP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "IOI_BLOCK_OUTS1_1", + "TERM_INT_BLOCK_OUTS_L_B1" + ], + [ + "IOI_CLK1_1", + "TERM_INT_CLK1" + ], + [ + "IOI_IMUX29_1", + "TERM_INT_IMUX29" + ], + [ + "IOI_BYP0_1", + "TERM_INT_BYP0" + ], + [ + "IOI_IMUX44_1", + "TERM_INT_IMUX44" + ], + [ + "IOI_IMUX28_1", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX5_1", + "TERM_INT_IMUX5" + ], + [ + "IOI_LOGIC_OUTS0_1", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_IMUX30_1", + "TERM_INT_IMUX30" + ], + [ + "IOI_CTRL1_1", + "TERM_INT_CTRL1" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_PHASER_TO_IO_ICLK_0", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_IMUX43_1", + "TERM_INT_IMUX43" + ], + [ + "IOI_LOGIC_OUTS21_1", + "TERM_INT_LOGIC_OUTS_L_B21" + ], + [ + "IOI_IMUX23_1", + "TERM_INT_IMUX23" + ], + [ + "IOI_IMUX18_1", + "TERM_INT_IMUX18" + ], + [ + "IOI_IMUX37_1", + "TERM_INT_IMUX37" + ], + [ + "IOI_IMUX33_1", + "TERM_INT_IMUX33" + ], + [ + "IOI_LOGIC_OUTS7_1", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_LOGIC_OUTS18_1", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_BYP4_1", + "TERM_INT_BYP4" + ], + [ + "IOI_IMUX47_1", + "TERM_INT_IMUX47" + ], + [ + "IOI_LOGIC_OUTS1_1", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX34_1", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX39_1", + "TERM_INT_IMUX39" + ], + [ + "IOI_LOGIC_OUTS4_1", + "TERM_INT_LOGIC_OUTS_L_B4" + ], + [ + "IOI_BYP1_1", + "TERM_INT_BYP1" + ], + [ + "IOI_FAN6_1", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX38_1", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX3_1", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX21_1", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX22_1", + "TERM_INT_IMUX22" + ], + [ + "IOI_PHASER_TO_IO_OCLK_0", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_IMUX26_1", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX11_1", + "TERM_INT_IMUX11" + ], + [ + "IOI_CLK0_1", + "TERM_INT_CLK0" + ], + [ + "IOI_LOGIC_OUTS20_1", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_BYP2_1", + "TERM_INT_BYP2" + ], + [ + "IOI_IMUX8_1", + "TERM_INT_IMUX8" + ], + [ + "IOI_LOGIC_OUTS6_1", + "TERM_INT_LOGIC_OUTS_L_B6" + ], + [ + "IOI_IMUX19_1", + "TERM_INT_IMUX19" + ], + [ + "IOI_LOGIC_OUTS2_1", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_FAN2_1", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX14_1", + "TERM_INT_IMUX14" + ], + [ + "IOI_IMUX7_1", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX40_1", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX25_1", + "TERM_INT_IMUX25" + ], + [ + "IOI_IMUX15_1", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX24_1", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX6_1", + "TERM_INT_IMUX6" + ], + [ + "IOI_IMUX4_1", + "TERM_INT_IMUX4" + ], + [ + "IOI_LOGIC_OUTS15_1", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX41_1", + "TERM_INT_IMUX41" + ], + [ + "IOI_LOGIC_OUTS17_1", + "TERM_INT_LOGIC_OUTS_L_B17" + ], + [ + "IOI_BYP6_1", + "TERM_INT_BYP6" + ], + [ + "IOI_FAN4_1", + "TERM_INT_FAN4" + ], + [ + "IOI_FAN1_1", + "TERM_INT_FAN1" + ], + [ + "IOI_IMUX32_1", + "TERM_INT_IMUX32" + ], + [ + "IOI_IMUX45_1", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX20_1", + "TERM_INT_IMUX20" + ], + [ + "IOI_IMUX46_1", + "TERM_INT_IMUX46" + ], + [ + "IOI_LOGIC_OUTS12_1", + "TERM_INT_LOGIC_OUTS_L_B12" + ], + [ + "IOI_IMUX31_1", + "TERM_INT_IMUX31" + ], + [ + "IOI_FAN0_1", + "TERM_INT_FAN0" + ], + [ + "IOI_IMUX35_1", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP7_1", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_1", + "TERM_INT_IMUX2" + ], + [ + "IOI_IMUX9_1", + "TERM_INT_IMUX9" + ], + [ + "IOI_BYP5_1", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS19_1", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_FAN3_1", + "TERM_INT_FAN3" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_IMUX36_1", + "TERM_INT_IMUX36" + ], + [ + "IOI_BLOCK_OUTS2_1", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "IOI_FAN7_1", + "TERM_INT_FAN7" + ], + [ + "IOI_LOGIC_OUTS5_1", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_LOGIC_OUTS11_1", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_IMUX27_1", + "TERM_INT_IMUX27" + ], + [ + "IOI_LOGIC_OUTS8_1", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_IMUX12_1", + "TERM_INT_IMUX12" + ], + [ + "IOI_LOGIC_OUTS3_1", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_IMUX16_1", + "TERM_INT_IMUX16" + ], + [ + "IOI_LOGIC_OUTS14_1", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_LOGIC_OUTS9_1", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_FAN5_1", + "TERM_INT_FAN5" + ], + [ + "IOI_IMUX1_1", + "TERM_INT_IMUX1" + ], + [ + "IOI_IMUX42_1", + "TERM_INT_IMUX42" + ], + [ + "IOI_IMUX10_1", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX13_1", + "TERM_INT_IMUX13" + ], + [ + "IOI_BLOCK_OUTS0_1", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_CTRL0_1", + "TERM_INT_CTRL0" + ], + [ + "IOI_LOGIC_OUTS23_1", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_IMUX17_1", + "TERM_INT_IMUX17" + ], + [ + "IOI_BYP3_1", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX0_1", + "TERM_INT_IMUX0" + ], + [ + "IOI_LOGIC_OUTS10_1", + "TERM_INT_LOGIC_OUTS_L_B10" + ] + ], + "tile_types": [ + "RIOI_TBYTETERM", + "R_TERM_INT" + ] + }, + { + "grid_deltas": [ + -1, + -7 + ], + "wire_pairs": [ + [ + "PCIE_IMUX6_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_LH6_17", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_WL1END0_17", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_EE4BEG0_17", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_BYP1_R_17", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_WW4END0_17", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_WR1END3_17", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_EE4C3_17", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_SE2A2_17", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_17", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_IMUX46_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_EE2BEG3_17", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_WW4A2_17", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_NW4A1_17", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_IMUX13_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_WW4C1_17", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_IMUX22_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_SE4C0_17", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_EE2A2_17", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_IMUX18_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_CTRL0_R_17", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_BYP4_R_17", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_SE4BEG2_17", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_IMUX4_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_17", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_17", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_CTRL1_R_17", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_WW2A1_17", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_IMUX26_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_NW4END0_17", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_SW2A2_17", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_EE4B0_17", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_SE4C3_17", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_SW2A3_17", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX38_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_SW4A3_17", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_17", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_LH5_17", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_IMUX20_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_NW4END3_17", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_IMUX7_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_NW2A0_17", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_IMUX9_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_NE4BEG3_17", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_WW2END3_17", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_WW4B1_17", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_17", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_WW4A3_17", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_EE4C2_17", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_WR1END2_17", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_17", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_BYP6_R_17", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_FAN6_R_17", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_IMUX3_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_NE4C3_17", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_17", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_WL1END2_17", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_NW2A3_17", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_LH1_17", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_SE2A1_17", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_NE2A1_17", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_NE4C0_17", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_IMUX30_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_EE4A1_17", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_IMUX37_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_LH12_17", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_17", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_LH3_17", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_ER1BEG0_17", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_FAN3_R_17", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_WW2A0_17", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_EE2BEG0_17", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_17", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_FAN0_R_17", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_ER1BEG1_17", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_SE4C1_17", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_NE4BEG2_17", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_IMUX32_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_SW4A0_17", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_EE4A3_17", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_IMUX27_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_SE2A0_17", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_CLK1_R_17", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_WW2END0_17", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_EE2BEG1_17", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX35_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_WW2END2_17", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_IMUX11_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_IMUX24_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_IMUX16_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_EL1BEG0_17", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_17", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_LH2_17", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_SW4A1_17", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_WW2A2_17", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_SE4BEG3_17", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_IMUX0_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_IMUX39_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_SW4END3_17", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_IMUX5_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_NW4END1_17", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_SE2A3_17", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_17", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_17", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_EE2BEG2_17", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_NE4C1_17", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_LH10_17", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_SE4C2_17", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_BYP7_R_17", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_IMUX44_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_WL1END1_17", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_17", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_EE4C1_17", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_SW4END2_17", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_MONITOR_N_17", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_17", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_SE4BEG0_17", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_IMUX47_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_WW4A0_17", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_WW4B2_17", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_WW4C0_17", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_NE2A0_17", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_BYP0_R_17", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_BYP2_R_17", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_IMUX23_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_IMUX21_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_IMUX40_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_EE4B2_17", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_IMUX43_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_EE2A3_17", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_IMUX12_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_ER1BEG2_17", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_IMUX17_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_IMUX41_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_SW4END1_17", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_WW4END3_17", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_EE4BEG3_17", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_17", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_ER1BEG3_17", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_SW2A1_17", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_EE4BEG2_17", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_NE2A2_17", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_WW4B3_17", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_LH9_17", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_WL1END3_17", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_17", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_WW4C3_17", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_CLK0_R_17", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_IMUX19_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_IMUX28_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_IMUX25_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_WW4A1_17", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_NE4BEG0_17", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_EE2A1_17", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_MONITOR_P_17", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_17", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_NW4END2_17", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_IMUX8_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_FAN5_R_17", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_NW4A2_17", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_WW2A3_17", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_17", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_NW2A1_17", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_NE2A3_17", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_WW4END1_17", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_17", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_LH11_17", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_EE4C0_17", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX1_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_LH4_17", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_IMUX33_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_FAN1_R_17", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_EE4A0_17", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_EL1BEG2_17", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_WW4B0_17", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_IMUX31_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_WR1END0_17", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_IMUX36_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_IMUX45_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_SE4BEG1_17", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_BYP5_R_17", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_SW4A2_17", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_17", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_IMUX14_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_EL1BEG1_17", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_IMUX29_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_FAN4_R_17", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_NW4A3_17", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_17", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_IMUX10_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_EE4BEG1_17", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_NW2A2_17", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_EE4B1_17", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_NW4A0_17", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WW4END2_17", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_17", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_EL1BEG3_17", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_NE4C2_17", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_IMUX15_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_LH7_17", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_SW4END0_17", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_IMUX34_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_FAN2_R_17", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_WR1END1_17", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_NE4BEG1_17", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX2_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_WW2END1_17", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_LH8_17", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4A2_17", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_EE2A0_17", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_17", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_SW2A0_17", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX42_R_17", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_EE4B3_17", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_BYP3_R_17", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_WW4C2_17", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_17", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_FAN7_R_17", + "INT_INTERFACE_FAN7" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "LIOB_IN_TERM0", + "LIOI_DCI_T_TERM0" + ], + [ + "IOB_PD_INT_EN_0", + "LIOI_PD_INT_EN_0" + ], + [ + "IOB_KEEPER_INT_EN_0", + "LIOI_KEEPER_INT_EN_0" + ], + [ + "IOB_O0", + "LIOI_O0" + ], + [ + "IOB_IBUF0", + "LIOI_IBUF0" + ], + [ + "IOB_KEEPER_INT_EN_1", + "LIOI_KEEPER_INT_EN_1" + ], + [ + "IOB_PU_INT_EN_1", + "LIOI_PU_INT_EN_1" + ], + [ + "IOB_T1", + "LIOI_T1" + ], + [ + "LIOB_IN_TERM1", + "LIOI_DCI_T_TERM1" + ], + [ + "IOB_PU_INT_EN_0", + "LIOI_PU_INT_EN_0" + ], + [ + "LIOB_MONITOR_P", + "IOI_MONITOR_P" + ], + [ + "IOB_O1", + "LIOI_O1" + ], + [ + "IOB_PD_INT_EN_1", + "LIOI_PD_INT_EN_1" + ], + [ + "IOB_T0", + "LIOI_T0" + ], + [ + "IOB_IBUF1", + "LIOI_IBUF1" + ], + [ + "IOB_IBUF_DISABLE1", + "LIOI_IBUF_DISABLE1" + ], + [ + "IOB_IBUF_DISABLE0", + "LIOI_IBUF_DISABLE0" + ], + [ + "LIOB_MONITOR_N", + "IOI_MONITOR_N" + ], + [ + "IOB_DIFF_TERM_INT_EN", + "LIOI_DIFF_TERM_INT_EN" + ] + ], + "tile_types": [ + "LIOB33", + "LIOI3" + ] + }, + { + "grid_deltas": [ + -1, + -7 + ], + "wire_pairs": [ + [ + "CFG_CENTER_LH5_17", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_NE4BEG0_17", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_LH2_17", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_EE4A3_17", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_ER1BEG2_17", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_SE4C2_17", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_SE2A2_17", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_NE4C0_17", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_WW4B0_17", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_EE4BEG1_17", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_SW2A2_17", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_LH8_17", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_SW4END3_17", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_EE4B2_17", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_NW4A2_17", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WW4B1_17", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_NW2A2_17", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_ER1BEG3_17", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_EL1BEG0_17", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_NE4C3_17", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_ER1BEG0_17", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_LH1_17", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_EE4A2_17", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4B1_17", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_WW4A0_17", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SW2A0_17", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_LH3_17", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SW4A3_17", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_LH6_17", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_NE4BEG2_17", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_WW4END1_17", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE4C0_17", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_SE4C1_17", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_SW4END2_17", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SE2A0_17", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_WW4END0_17", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EE4BEG2_17", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SE4BEG2_17", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_SW2A1_17", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE2BEG3_17", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_EE2A3_17", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_EE2A2_17", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_NW4END3_17", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_EE4C1_17", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_WR1END2_17", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_SW2A3_17", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_LH4_17", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_SE4C3_17", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_WW2END3_17", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_EE4A0_17", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_WW4C2_17", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NW2A0_17", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_NW4END0_17", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_WL1END1_17", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_LH7_17", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_EE4B0_17", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH12_17", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_NW2A3_17", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_WL1END3_17", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_WW2END1_17", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_SW4A2_17", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NW4END2_17", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_LH9_17", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_EE2A0_17", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW2END0_17", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_EE2BEG0_17", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4C1_17", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_WW4A1_17", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_SW4A1_17", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NE2A2_17", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_NE4BEG1_17", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_WW4END3_17", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WW2A1_17", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_ER1BEG1_17", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_NE4BEG3_17", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG2_17", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_WL1END0_17", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SW4END0_17", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EL1BEG3_17", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_NW4A3_17", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WR1END1_17", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WR1END3_17", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE2A1_17", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_NW4A1_17", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WW2A2_17", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WW4END2_17", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_WW4A2_17", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE4A1_17", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EE4BEG0_17", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WW2END2_17", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SE2A3_17", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_NW2A1_17", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SW4A0_17", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WW4C3_17", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_SE2A1_17", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW2A0_17", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_EE2BEG2_17", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW2A3_17", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WL1END2_17", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_NE2A1_17", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_LH10_17", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_SW4END1_17", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_NW4A0_17", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SE4C0_17", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_SE4BEG0_17", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_WW4C0_17", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_EE4C3_17", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_NW4END1_17", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_EE4B3_17", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_NE4C1_17", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE2A0_17", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_SE4BEG1_17", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_LH11_17", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EL1BEG1_17", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NE2A3_17", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_WR1END0_17", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_NE4C2_17", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW4A3_17", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_SE4BEG3_17", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_WW4B3_17", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_EE2BEG1_17", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_EE4BEG3_17", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WW4B2_17", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_EE4C2_17", + "INT_FEEDTHRU_2_EE4C2" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -8 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SE4BEG2_18", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_WR1END0_18", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_IMUX37_18", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_IMUX38_18", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_BYP1_18", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SE4BEG0_18", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_SW4A3_18", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_WW2A2_18", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_SE4C3_18", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX30_18", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_EE4B1_18", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_SE2A0_18", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_WW2A3_18", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_EE4BEG0_18", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_NW4A2_18", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_EE2A1_18", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_WW4END1_18", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_EL1BEG0_18", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_NE2A3_18", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_WW2A0_18", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_EE2A3_18", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NW2A3_18", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NW4END3_18", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_FAN7_18", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX15_18", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_SW4END1_18", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_SW4A0_18", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_NW2A1_18", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_EE2BEG3_18", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_BYP0_18", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_EE4A3_18", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_NW2A2_18", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_IMUX1_18", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_ER1BEG0_18", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_LH8_18", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_NE2A0_18", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_SW4A1_18", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_EE2A0_18", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_IMUX18_18", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_SE4BEG1_18", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_ER1BEG1_18", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_IMUX34_18", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_CLK1_18", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX41_18", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_WL1END3_18", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_FAN5_18", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SW2A1_18", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_CLK0_18", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_NE4BEG2_18", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG1_18", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_WW4C0_18", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_WW2A1_18", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_LH10_18", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_BYP4_18", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_NW4A3_18", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_IMUX6_18", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX33_18", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_NE4BEG3_18", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_FAN2_18", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_EE2A2_18", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_WL1END1_18", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_LH12_18", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_WW4B3_18", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_IMUX27_18", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_BYP5_18", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_LH11_18", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_WL1END0_18", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_LH1_18", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_EE4BEG2_18", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE4A2_18", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_WW2END0_18", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WL1END2_18", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_IMUX12_18", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_SE4BEG3_18", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX14_18", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_SW2A0_18", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_BYP6_18", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_WW4C1_18", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_FAN3_18", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_BYP7_18", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_LH2_18", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX21_18", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_IMUX23_18", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_CTRL0_18", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_EE2BEG2_18", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX36_18", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_IMUX39_18", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_NW4END1_18", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SW4A2_18", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_IMUX2_18", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_IMUX43_18", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_WW4END2_18", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX25_18", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_EE4B2_18", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_LH5_18", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX0_18", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_ER1BEG2_18", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_ER1BEG3_18", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_IMUX4_18", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_WW4B0_18", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_FAN0_18", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_WW4B2_18", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_FAN6_18", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_WW2END1_18", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_WW4C3_18", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NE2A2_18", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_SW4END2_18", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_IMUX20_18", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_IMUX17_18", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_WW4C2_18", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_LH9_18", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_IMUX5_18", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WW4A2_18", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_EE4B0_18", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_SW2A3_18", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_LH6_18", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_LH7_18", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_WW2END3_18", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_IMUX47_18", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX42_18", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_BYP2_18", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_WW4END3_18", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX28_18", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_WW4A1_18", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_NE2A1_18", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_NE4BEG0_18", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX44_18", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WR1END3_18", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_EE4A0_18", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_WR1END1_18", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_EE2BEG0_18", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_WR1END2_18", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SE4C2_18", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_IMUX40_18", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_IMUX31_18", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_NW2A0_18", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_IMUX19_18", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_LH4_18", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_IMUX29_18", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX22_18", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX11_18", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_NW4A1_18", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SE4C0_18", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_EE4A1_18", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_SW4END0_18", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_WW2END2_18", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_WW4END0_18", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_WW4A0_18", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_FAN1_18", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_BYP3_18", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_IMUX9_18", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX32_18", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_SE4C1_18", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX13_18", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_CTRL1_18", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_NE4C2_18", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_EE4BEG1_18", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_IMUX24_18", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_NE4BEG1_18", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX46_18", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_EE4C0_18", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_NW4END0_18", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX35_18", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_SW4END3_18", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX45_18", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_NE4C0_18", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE4C2_18", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_EE4C1_18", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_EE4BEG3_18", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG2_18", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_SE2A1_18", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_IMUX7_18", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_LH3_18", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX16_18", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX8_18", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_NW4END2_18", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_SW2A2_18", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_SE2A2_18", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_EE2BEG1_18", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX26_18", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_EL1BEG3_18", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_IMUX3_18", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_NE4C1_18", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_EE4C3_18", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE4B3_18", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_NW4A0_18", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX10_18", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SE2A3_18", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_NE4C3_18", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_WW4A3_18", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_FAN4_18", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW4B1_18", + "VFRAME_WW4B1" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SW4A3_2", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_CLK0_2", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_EE4BEG2_2", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX32_2", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_EL1BEG2_2", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_FAN7_2", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_EE4BEG0_2", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_IMUX14_2", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_EE2BEG0_2", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_LH12_2", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX43_2", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_SW2A0_2", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_EE4C0_2", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_FAN6_2", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_WR1END1_2", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_LH9_2", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_WW4END0_2", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX10_2", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_EL1BEG0_2", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_IMUX31_2", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_EE2A2_2", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_SE2A2_2", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX18_2", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_EE2BEG3_2", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_EE2A3_2", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_IMUX45_2", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX26_2", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX21_2", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_SE4C2_2", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WW4B2_2", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_WL1END3_2", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_IMUX0_2", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_IMUX35_2", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_IMUX25_2", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_WW4B1_2", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_WW2END2_2", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_IMUX3_2", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_EE4B1_2", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_EE2A0_2", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_IMUX37_2", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_LH2_2", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EE4A3_2", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_BYP5_2", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_IMUX36_2", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW2A1_2", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_SW4END1_2", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_SE2A3_2", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_WW4END2_2", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX33_2", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_WR1END2_2", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SE4BEG0_2", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_CTRL0_2", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_LH8_2", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_SW2A2_2", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_WW2A3_2", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_BYP3_2", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_EE4A2_2", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_FAN4_2", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_NE4C2_2", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_NW4END3_2", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_IMUX8_2", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_NE4BEG3_2", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NE2A0_2", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX44_2", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_BYP4_2", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_NE4BEG0_2", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX27_2", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX38_2", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_NW4END1_2", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SE2A0_2", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_BYP0_2", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX29_2", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_WW4A2_2", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_LH6_2", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_NW4A1_2", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_FAN0_2", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_WL1END2_2", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_SE2A1_2", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_IMUX30_2", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_2", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_WW4A0_2", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_WW4END1_2", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_SW4A1_2", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_2", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_NE4BEG2_2", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_IMUX15_2", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_EE4BEG3_2", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_WW2A1_2", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_FAN5_2", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_IMUX41_2", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_EE4A1_2", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_LH3_2", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_2", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_IMUX47_2", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_SE4C1_2", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_WW4A3_2", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW4B3_2", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_EL1BEG1_2", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_FAN1_2", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_BYP6_2", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX20_2", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_LH11_2", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_WR1END0_2", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_NW2A3_2", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_BYP2_2", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_WW4C2_2", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_EL1BEG3_2", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_BYP1_2", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SW4A2_2", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_IMUX7_2", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_NW4END0_2", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX6_2", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX28_2", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX19_2", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_EE4C2_2", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_LH1_2", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NE2A1_2", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_NW4A3_2", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_LH7_2", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_NE4C1_2", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_WW2END3_2", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_EE2BEG2_2", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_NE4C0_2", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_NW2A0_2", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_WW2END1_2", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_WW2A0_2", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_IMUX4_2", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_EE4C1_2", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX22_2", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX12_2", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_NE4C3_2", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_WW4END3_2", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX17_2", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX13_2", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_EE4BEG1_2", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_WW4C0_2", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX9_2", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX40_2", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_SE4BEG1_2", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE4B0_2", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WW4B0_2", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_WL1END0_2", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_SE4C0_2", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_SE4BEG3_2", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_SE4BEG2_2", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_SW4END3_2", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_ER1BEG1_2", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_IMUX24_2", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_EE4A0_2", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_NW4A0_2", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_CTRL1_2", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_WW4C1_2", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_IMUX34_2", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_FAN3_2", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_NE2A3_2", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX2_2", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_IMUX39_2", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_LH10_2", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_ER1BEG0_2", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_IMUX5_2", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WL1END1_2", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_2", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_IMUX1_2", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX16_2", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WR1END3_2", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_EE4B3_2", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_EE4C3_2", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE2A1_2", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_SW4A0_2", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_NW2A2_2", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_NE2A2_2", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_SW2A3_2", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_ER1BEG2_2", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_ER1BEG3_2", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_FAN2_2", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_SE4C3_2", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_LH4_2", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_NW4END2_2", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_NE4BEG1_2", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_WW2END0_2", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_EE4B2_2", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_WW4C3_2", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX46_2", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_SW4END0_2", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX23_2", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW2A2_2", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_IMUX42_2", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_NW4A2_2", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_BYP7_2", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_CLK1_2", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_SW4END2_2", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_LH5_2", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_WW4A1_2", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_EE2BEG1_2", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_NW2A1_2", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_IMUX11_2", + "VFRAME_IMUX11" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CLK_HROW_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_LH2_1", + "VBRK_LH2" + ], + [ + "CLK_HROW_LH4_1", + "VBRK_LH4" + ], + [ + "CLK_HROW_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_MONITOR_P_1", + "VBRK_MONITOR_P" + ], + [ + "CLK_HROW_LH10_1", + "VBRK_LH10" + ], + [ + "CLK_HROW_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_LH3_1", + "VBRK_LH3" + ], + [ + "CLK_HROW_LH9_1", + "VBRK_LH9" + ], + [ + "CLK_HROW_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_LH7_1", + "VBRK_LH7" + ], + [ + "CLK_HROW_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_MONITOR_N_1", + "VBRK_MONITOR_N" + ], + [ + "CLK_HROW_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_LH11_1", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH12_1", + "VBRK_LH12" + ], + [ + "CLK_HROW_LH8_1", + "VBRK_LH8" + ], + [ + "CLK_HROW_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_LH5_1", + "VBRK_LH5" + ], + [ + "CLK_HROW_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_LH1_1", + "VBRK_LH1" + ], + [ + "CLK_HROW_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_LH6_1", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_WW2END2_1", + "VBRK_WW2END2" + ] + ], + "tile_types": [ + "CLK_BUFG_TOP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH3_4", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_LH4_4", + "VBRK_LH4" + ], + [ + "CMT_TOP_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH12_4", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH11_4", + "VBRK_LH11" + ], + [ + "CMT_TOP_LH9_4", + "VBRK_LH9" + ], + [ + "CMT_TOP_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH1_4", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_MONITOR_N_4", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_LH10_4", + "VBRK_LH10" + ], + [ + "CMT_TOP_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH2_4", + "VBRK_LH2" + ], + [ + "CMT_TOP_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_MONITOR_P_4", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_LH8_4", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_LH7_4", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH5_4", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH6_4", + "VBRK_LH6" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 4 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_LOGIC_OUTS_B9", + "PCIE_LOGIC_OUTS_B9_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT42", + "PCIE_IMUX42_R_4" + ], + [ + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_4" + ], + [ + "INT_INTERFACE_EE4C1", + "PCIE_EE4C1_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT24", + "PCIE_IMUX24_R_4" + ], + [ + "INT_INTERFACE_EE2A2", + "PCIE_EE2A2_4" + ], + [ + "INT_INTERFACE_LH1", + "PCIE_LH1_4" + ], + [ + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B10", + "PCIE_LOGIC_OUTS_B10_R_4" + ], + [ + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_4" + ], + [ + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_4" + ], + [ + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B23", + "PCIE_LOGIC_OUTS_B23_R_4" + ], + [ + "INT_INTERFACE_CTRL0", + "PCIE_CTRL0_R_4" + ], + [ + "INT_INTERFACE_FAN3", + "PCIE_FAN3_R_4" + ], + [ + "INT_INTERFACE_FAN7", + "PCIE_FAN7_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT10", + "PCIE_IMUX10_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT2", + "PCIE_IMUX2_R_4" + ], + [ + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT1", + "PCIE_IMUX1_R_4" + ], + [ + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_4" + ], + [ + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_4" + ], + [ + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_4" + ], + [ + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_4" + ], + [ + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT11", + "PCIE_IMUX11_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT36", + "PCIE_IMUX36_R_4" + ], + [ + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_4" + ], + [ + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_4" + ], + [ + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_4" + ], + [ + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_4" + ], + [ + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_4" + ], + [ + "INT_INTERFACE_EE4C0", + "PCIE_EE4C0_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT9", + "PCIE_IMUX9_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT33", + "PCIE_IMUX33_R_4" + ], + [ + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT0", + "PCIE_IMUX0_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT39", + "PCIE_IMUX39_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT32", + "PCIE_IMUX32_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B21", + "PCIE_LOGIC_OUTS_B21_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B8", + "PCIE_LOGIC_OUTS_B8_R_4" + ], + [ + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT15", + "PCIE_IMUX15_R_4" + ], + [ + "INT_INTERFACE_EE2BEG3", + "PCIE_EE2BEG3_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT6", + "PCIE_IMUX6_R_4" + ], + [ + "INT_INTERFACE_LH9", + "PCIE_LH9_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT8", + "PCIE_IMUX8_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT13", + "PCIE_IMUX13_R_4" + ], + [ + "INT_INTERFACE_EE4B0", + "PCIE_EE4B0_4" + ], + [ + "INT_INTERFACE_LH12", + "PCIE_LH12_4" + ], + [ + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT44", + "PCIE_IMUX44_R_4" + ], + [ + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_4" + ], + [ + "INT_INTERFACE_EE2BEG1", + "PCIE_EE2BEG1_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT26", + "PCIE_IMUX26_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B17", + "PCIE_LOGIC_OUTS_B17_R_4" + ], + [ + "INT_INTERFACE_EE2A3", + "PCIE_EE2A3_4" + ], + [ + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B12", + "PCIE_LOGIC_OUTS_B12_R_4" + ], + [ + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_4" + ], + [ + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT31", + "PCIE_IMUX31_R_4" + ], + [ + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_4" + ], + [ + "INT_INTERFACE_EE2A1", + "PCIE_EE2A1_4" + ], + [ + "INT_INTERFACE_BYP7", + "PCIE_BYP7_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B20", + "PCIE_LOGIC_OUTS_B20_R_4" + ], + [ + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B18", + "PCIE_LOGIC_OUTS_B18_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B15", + "PCIE_LOGIC_OUTS_B15_R_4" + ], + [ + "INT_INTERFACE_BYP1", + "PCIE_BYP1_R_4" + ], + [ + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_4" + ], + [ + "INT_INTERFACE_BYP6", + "PCIE_BYP6_R_4" + ], + [ + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_4" + ], + [ + "INT_INTERFACE_LH8", + "PCIE_LH8_4" + ], + [ + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B1", + "PCIE_LOGIC_OUTS_B1_R_4" + ], + [ + "INT_INTERFACE_CLK1", + "PCIE_CLK1_R_4" + ], + [ + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_4" + ], + [ + "INT_INTERFACE_ER1BEG0", + "PCIE_ER1BEG0_4" + ], + [ + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_4" + ], + [ + "INT_INTERFACE_EE4A2", + "PCIE_EE4A2_4" + ], + [ + "INT_INTERFACE_BYP5", + "PCIE_BYP5_R_4" + ], + [ + "INT_INTERFACE_LH11", + "PCIE_LH11_4" + ], + [ + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_4" + ], + [ + "INT_INTERFACE_LH5", + "PCIE_LH5_4" + ], + [ + "INT_INTERFACE_EL1BEG3", + "PCIE_EL1BEG3_4" + ], + [ + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_4" + ], + [ + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_4" + ], + [ + "INT_INTERFACE_BYP3", + "PCIE_BYP3_R_4" + ], + [ + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_4" + ], + [ + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_4" + ], + [ + "INT_INTERFACE_LH4", + "PCIE_LH4_4" + ], + [ + "INT_INTERFACE_FAN1", + "PCIE_FAN1_R_4" + ], + [ + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT16", + "PCIE_IMUX16_R_4" + ], + [ + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_4" + ], + [ + "INT_INTERFACE_LH10", + "PCIE_LH10_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT12", + "PCIE_IMUX12_R_4" + ], + [ + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_4" + ], + [ + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B19", + "PCIE_LOGIC_OUTS_B19_R_4" + ], + [ + "INT_INTERFACE_BYP2", + "PCIE_BYP2_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B5", + "PCIE_LOGIC_OUTS_B5_R_4" + ], + [ + "INT_INTERFACE_BYP0", + "PCIE_BYP0_R_4" + ], + [ + "INT_INTERFACE_FAN5", + "PCIE_FAN5_R_4" + ], + [ + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_4" + ], + [ + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B2", + "PCIE_LOGIC_OUTS_B2_R_4" + ], + [ + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_4" + ], + [ + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT28", + "PCIE_IMUX28_R_4" + ], + [ + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT27", + "PCIE_IMUX27_R_4" + ], + [ + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_4" + ], + [ + "INT_INTERFACE_FAN2", + "PCIE_FAN2_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B7", + "PCIE_LOGIC_OUTS_B7_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT46", + "PCIE_IMUX46_R_4" + ], + [ + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_4" + ], + [ + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_4" + ], + [ + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_4" + ], + [ + "INT_INTERFACE_FAN6", + "PCIE_FAN6_R_4" + ], + [ + "INT_INTERFACE_LH6", + "PCIE_LH6_4" + ], + [ + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_4" + ], + [ + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_4" + ], + [ + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_4" + ], + [ + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_4" + ], + [ + "INT_INTERFACE_EE4A0", + "PCIE_EE4A0_4" + ], + [ + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_4" + ], + [ + "INT_INTERFACE_FAN4", + "PCIE_FAN4_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT4", + "PCIE_IMUX4_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT35", + "PCIE_IMUX35_R_4" + ], + [ + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_4" + ], + [ + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_4" + ], + [ + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B3", + "PCIE_LOGIC_OUTS_B3_R_4" + ], + [ + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_4" + ], + [ + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_4" + ], + [ + "INT_INTERFACE_EE2BEG2", + "PCIE_EE2BEG2_4" + ], + [ + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_4" + ], + [ + "INT_INTERFACE_LH7", + "PCIE_LH7_4" + ], + [ + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_4" + ], + [ + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_4" + ], + [ + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_4" + ], + [ + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_4" + ], + [ + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_4" + ], + [ + "INT_INTERFACE_EE2BEG0", + "PCIE_EE2BEG0_4" + ], + [ + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B22", + "PCIE_LOGIC_OUTS_B22_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT20", + "PCIE_IMUX20_R_4" + ], + [ + "INT_INTERFACE_CTRL1", + "PCIE_CTRL1_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT21", + "PCIE_IMUX21_R_4" + ], + [ + "INT_INTERFACE_EE2A0", + "PCIE_EE2A0_4" + ], + [ + "INT_INTERFACE_BYP4", + "PCIE_BYP4_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT29", + "PCIE_IMUX29_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT45", + "PCIE_IMUX45_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B13", + "PCIE_LOGIC_OUTS_B13_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT40", + "PCIE_IMUX40_R_4" + ], + [ + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT19", + "PCIE_IMUX19_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT23", + "PCIE_IMUX23_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT43", + "PCIE_IMUX43_R_4" + ], + [ + "INT_INTERFACE_FAN0", + "PCIE_FAN0_R_4" + ], + [ + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT17", + "PCIE_IMUX17_R_4" + ], + [ + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_4" + ], + [ + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_4" + ], + [ + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B14", + "PCIE_LOGIC_OUTS_B14_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT18", + "PCIE_IMUX18_R_4" + ], + [ + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B0", + "PCIE_LOGIC_OUTS_B0_R_4" + ], + [ + "INT_INTERFACE_LH2", + "PCIE_LH2_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT38", + "PCIE_IMUX38_R_4" + ], + [ + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_4" + ], + [ + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_4" + ], + [ + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_4" + ], + [ + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT14", + "PCIE_IMUX14_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B11", + "PCIE_LOGIC_OUTS_B11_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT22", + "PCIE_IMUX22_R_4" + ], + [ + "INT_INTERFACE_EE4A1", + "PCIE_EE4A1_4" + ], + [ + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_4" + ], + [ + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT47", + "PCIE_IMUX47_R_4" + ], + [ + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT34", + "PCIE_IMUX34_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B6", + "PCIE_LOGIC_OUTS_B6_R_4" + ], + [ + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT30", + "PCIE_IMUX30_R_4" + ], + [ + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_4" + ], + [ + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_4" + ], + [ + "INT_INTERFACE_EE4A3", + "PCIE_EE4A3_4" + ], + [ + "INT_INTERFACE_CLK0", + "PCIE_CLK0_R_4" + ], + [ + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_4" + ], + [ + "INT_INTERFACE_EE4C2", + "PCIE_EE4C2_4" + ], + [ + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_4" + ], + [ + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_4" + ], + [ + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_4" + ], + [ + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B16", + "PCIE_LOGIC_OUTS_B16_R_4" + ], + [ + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_4" + ], + [ + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B4", + "PCIE_LOGIC_OUTS_B4_R_4" + ], + [ + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_4" + ], + [ + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_4" + ], + [ + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_4" + ], + [ + "INT_INTERFACE_LH3", + "PCIE_LH3_4" + ], + [ + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_4" + ], + [ + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT37", + "PCIE_IMUX37_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT25", + "PCIE_IMUX25_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT5", + "PCIE_IMUX5_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT3", + "PCIE_IMUX3_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT41", + "PCIE_IMUX41_R_4" + ], + [ + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT7", + "PCIE_IMUX7_R_4" + ] + ], + "tile_types": [ + "PCIE_INT_INTERFACE_R", + "PCIE_TOP" + ] + }, + { + "grid_deltas": [ + 0, + -11 + ], + "wire_pairs": [ + [ + "GTXE2_CHANNEL_RXOUTCLK_1", + "GTXE2_CHANNEL_RXOUTCLK_1" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_0", + "GTXE2_CHANNEL_TXOUTCLK_0" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_3", + "GTXE2_CHANNEL_TXOUTCLK_3" + ], + [ + "GTXE2_CHANNEL_RXOUTCLK_2", + "GTXE2_CHANNEL_RXOUTCLK_2" + ], + [ + "GTXE2_CHANNEL_QPLLREFCLK", + "GTXE2_CHANNEL_QPLLREFCLK" + ], + [ + "GTXE2_CHANNEL_RXOUTCLK_3", + "GTXE2_CHANNEL_RXOUTCLK_3" + ], + [ + "GTXE2_CHANNEL_QPLLCLK", + "GTXE2_CHANNEL_QPLLCLK" + ], + [ + "GTXE2_CHANNEL_REFCLK1", + "GTXE2_CHANNEL_REFCLK1" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_2", + "GTXE2_CHANNEL_TXOUTCLK_2" + ], + [ + "GTXE2_CHANNEL_NORTHREFCLK1", + "GTXE2_CHANNEL_NORTHREFCLK1" + ], + [ + "GTXE2_CHANNEL_NORTHREFCLK0", + "GTXE2_CHANNEL_NORTHREFCLK0" + ], + [ + "GTXE2_CHANNEL_SOUTHREFCLK0", + "GTXE2_CHANNEL_SOUTHREFCLK0" + ], + [ + "GTXE2_CHANNEL_SOUTHREFCLK1", + "GTXE2_CHANNEL_SOUTHREFCLK1" + ], + [ + "GTXE2_CHANNEL_REFCLK0", + "GTXE2_CHANNEL_REFCLK0" + ], + [ + "GTXE2_CHANNEL_RXOUTCLK_0", + "GTXE2_CHANNEL_RXOUTCLK_0" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_1", + "GTXE2_CHANNEL_TXOUTCLK_1" + ] + ], + "tile_types": [ + "GTX_CHANNEL_2", + "GTX_CHANNEL_3" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_NE4C2", + "VFRAME_NE4C2" + ], + [ + "INT_INTERFACE_IMUX15", + "VFRAME_IMUX15" + ], + [ + "INT_INTERFACE_WW4A1", + "VFRAME_WW4A1" + ], + [ + "INT_INTERFACE_ER1BEG1", + "VFRAME_ER1BEG1" + ], + [ + "INT_INTERFACE_IMUX23", + "VFRAME_IMUX23" + ], + [ + "INT_INTERFACE_NE4BEG1", + "VFRAME_NE4BEG1" + ], + [ + "INT_INTERFACE_BYP1", + "VFRAME_BYP1" + ], + [ + "INT_INTERFACE_WW4C2", + "VFRAME_WW4C2" + ], + [ + "INT_INTERFACE_WW4END1", + "VFRAME_WW4END1" + ], + [ + "INT_INTERFACE_IMUX28", + "VFRAME_IMUX28" + ], + [ + "INT_INTERFACE_IMUX3", + "VFRAME_IMUX3" + ], + [ + "INT_INTERFACE_NW2A1", + "VFRAME_NW2A1" + ], + [ + "INT_INTERFACE_WR1END3", + "VFRAME_WR1END3" + ], + [ + "INT_INTERFACE_IMUX46", + "VFRAME_IMUX46" + ], + [ + "INT_INTERFACE_IMUX47", + "VFRAME_IMUX47" + ], + [ + "INT_INTERFACE_FAN3", + "VFRAME_FAN3" + ], + [ + "INT_INTERFACE_IMUX25", + "VFRAME_IMUX25" + ], + [ + "INT_INTERFACE_SE4C1", + "VFRAME_SE4C1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "INT_INTERFACE_FAN6", + "VFRAME_FAN6" + ], + [ + "INT_INTERFACE_NW2A0", + "VFRAME_NW2A0" + ], + [ + "INT_INTERFACE_WL1END3", + "VFRAME_WL1END3" + ], + [ + "INT_INTERFACE_EE4BEG2", + "VFRAME_EE4BEG2" + ], + [ + "INT_INTERFACE_SW4A1", + "VFRAME_SW4A1" + ], + [ + "INT_INTERFACE_IMUX18", + "VFRAME_IMUX18" + ], + [ + "INT_INTERFACE_WW2A2", + "VFRAME_WW2A2" + ], + [ + "INT_INTERFACE_NW4A0", + "VFRAME_NW4A0" + ], + [ + "INT_INTERFACE_WR1END0", + "VFRAME_WR1END0" + ], + [ + "INT_INTERFACE_WW2A0", + "VFRAME_WW2A0" + ], + [ + "INT_INTERFACE_EL1BEG1", + "VFRAME_EL1BEG1" + ], + [ + "INT_INTERFACE_FAN5", + "VFRAME_FAN5" + ], + [ + "INT_INTERFACE_IMUX2", + "VFRAME_IMUX2" + ], + [ + "INT_INTERFACE_NW4END1", + "VFRAME_NW4END1" + ], + [ + "INT_INTERFACE_EE4B0", + "VFRAME_EE4B0" + ], + [ + "INT_INTERFACE_IMUX41", + "VFRAME_IMUX41" + ], + [ + "INT_INTERFACE_BYP0", + "VFRAME_BYP0" + ], + [ + "INT_INTERFACE_NE4BEG0", + "VFRAME_NE4BEG0" + ], + [ + "INT_INTERFACE_EE4A3", + "VFRAME_EE4A3" + ], + [ + "INT_INTERFACE_EE4B1", + "VFRAME_EE4B1" + ], + [ + "INT_INTERFACE_FAN1", + "VFRAME_FAN1" + ], + [ + "INT_INTERFACE_IMUX45", + "VFRAME_IMUX45" + ], + [ + "INT_INTERFACE_WW4A2", + "VFRAME_WW4A2" + ], + [ + "INT_INTERFACE_WW4C3", + "VFRAME_WW4C3" + ], + [ + "INT_INTERFACE_LH7", + "VFRAME_LH7" + ], + [ + "INT_INTERFACE_SW2A3", + "VFRAME_SW2A3" + ], + [ + "INT_INTERFACE_LH5", + "VFRAME_LH5" + ], + [ + "INT_INTERFACE_EE4A2", + "VFRAME_EE4A2" + ], + [ + "INT_INTERFACE_WW2END3", + "VFRAME_WW2END3" + ], + [ + "INT_INTERFACE_ER1BEG0", + "VFRAME_ER1BEG0" + ], + [ + "INT_INTERFACE_EE4C2", + "VFRAME_EE4C2" + ], + [ + "INT_INTERFACE_IMUX37", + "VFRAME_IMUX37" + ], + [ + "INT_INTERFACE_IMUX14", + "VFRAME_IMUX14" + ], + [ + "INT_INTERFACE_IMUX21", + "VFRAME_IMUX21" + ], + [ + "INT_INTERFACE_IMUX12", + "VFRAME_IMUX12" + ], + [ + "INT_INTERFACE_CLK1", + "VFRAME_CLK1" + ], + [ + "INT_INTERFACE_EE4C0", + "VFRAME_EE4C0" + ], + [ + "INT_INTERFACE_IMUX38", + "VFRAME_IMUX38" + ], + [ + "INT_INTERFACE_EE2A3", + "VFRAME_EE2A3" + ], + [ + "INT_INTERFACE_IMUX33", + "VFRAME_IMUX33" + ], + [ + "INT_INTERFACE_SE2A1", + "VFRAME_SE2A1" + ], + [ + "INT_INTERFACE_WR1END1", + "VFRAME_WR1END1" + ], + [ + "INT_INTERFACE_LH12", + "VFRAME_LH12" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "INT_INTERFACE_IMUX10", + "VFRAME_IMUX10" + ], + [ + "INT_INTERFACE_SW4END3", + "VFRAME_SW4END3" + ], + [ + "INT_INTERFACE_SE2A3", + "VFRAME_SE2A3" + ], + [ + "INT_INTERFACE_SE2A0", + "VFRAME_SE2A0" + ], + [ + "INT_INTERFACE_BYP2", + "VFRAME_BYP2" + ], + [ + "INT_INTERFACE_LH3", + "VFRAME_LH3" + ], + [ + "INT_INTERFACE_IMUX17", + "VFRAME_IMUX17" + ], + [ + "INT_INTERFACE_NE4C1", + "VFRAME_NE4C1" + ], + [ + "INT_INTERFACE_NW4END2", + "VFRAME_NW4END2" + ], + [ + "INT_INTERFACE_NE2A2", + "VFRAME_NE2A2" + ], + [ + "INT_INTERFACE_IMUX11", + "VFRAME_IMUX11" + ], + [ + "INT_INTERFACE_IMUX9", + "VFRAME_IMUX9" + ], + [ + "INT_INTERFACE_EE4C1", + "VFRAME_EE4C1" + ], + [ + "INT_INTERFACE_SW4END0", + "VFRAME_SW4END0" + ], + [ + "INT_INTERFACE_IMUX20", + "VFRAME_IMUX20" + ], + [ + "INT_INTERFACE_SE4C3", + "VFRAME_SE4C3" + ], + [ + "INT_INTERFACE_NE2A1", + "VFRAME_NE2A1" + ], + [ + "INT_INTERFACE_WW4C0", + "VFRAME_WW4C0" + ], + [ + "INT_INTERFACE_LH1", + "VFRAME_LH1" + ], + [ + "INT_INTERFACE_SW4END1", + "VFRAME_SW4END1" + ], + [ + "INT_INTERFACE_EE2A1", + "VFRAME_EE2A1" + ], + [ + "INT_INTERFACE_EL1BEG0", + "VFRAME_EL1BEG0" + ], + [ + "INT_INTERFACE_EE4A0", + "VFRAME_EE4A0" + ], + [ + "INT_INTERFACE_NW2A3", + "VFRAME_NW2A3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "INT_INTERFACE_FAN4", + "VFRAME_FAN4" + ], + [ + "INT_INTERFACE_WW4END2", + "VFRAME_WW4END2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "INT_INTERFACE_CLK0", + "VFRAME_CLK0" + ], + [ + "INT_INTERFACE_IMUX42", + "VFRAME_IMUX42" + ], + [ + "INT_INTERFACE_WW4END3", + "VFRAME_WW4END3" + ], + [ + "INT_INTERFACE_MONITOR_N", + "VFRAME_MONITOR_N" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "INT_INTERFACE_WW2END0", + "VFRAME_WW2END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "INT_INTERFACE_NW4A2", + "VFRAME_NW4A2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "INT_INTERFACE_WW2A1", + "VFRAME_WW2A1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "INT_INTERFACE_IMUX6", + "VFRAME_IMUX6" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "INT_INTERFACE_EE4BEG0", + "VFRAME_EE4BEG0" + ], + [ + "INT_INTERFACE_EE4BEG1", + "VFRAME_EE4BEG1" + ], + [ + "INT_INTERFACE_SW4A3", + "VFRAME_SW4A3" + ], + [ + "INT_INTERFACE_NW4A1", + "VFRAME_NW4A1" + ], + [ + "INT_INTERFACE_EL1BEG3", + "VFRAME_EL1BEG3" + ], + [ + "INT_INTERFACE_FAN2", + "VFRAME_FAN2" + ], + [ + "INT_INTERFACE_EE2BEG1", + "VFRAME_EE2BEG1" + ], + [ + "INT_INTERFACE_EE2BEG2", + "VFRAME_EE2BEG2" + ], + [ + "INT_INTERFACE_NE4BEG2", + "VFRAME_NE4BEG2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "INT_INTERFACE_WR1END2", + "VFRAME_WR1END2" + ], + [ + "INT_INTERFACE_LH4", + "VFRAME_LH4" + ], + [ + "INT_INTERFACE_EE2BEG3", + "VFRAME_EE2BEG3" + ], + [ + "INT_INTERFACE_LH6", + "VFRAME_LH6" + ], + [ + "INT_INTERFACE_IMUX24", + "VFRAME_IMUX24" + ], + [ + "INT_INTERFACE_WW2END2", + "VFRAME_WW2END2" + ], + [ + "INT_INTERFACE_CTRL0", + "VFRAME_CTRL0" + ], + [ + "INT_INTERFACE_EE4C3", + "VFRAME_EE4C3" + ], + [ + "INT_INTERFACE_SE2A2", + "VFRAME_SE2A2" + ], + [ + "INT_INTERFACE_EE2BEG0", + "VFRAME_EE2BEG0" + ], + [ + "INT_INTERFACE_SE4BEG3", + "VFRAME_SE4BEG3" + ], + [ + "INT_INTERFACE_NW2A2", + "VFRAME_NW2A2" + ], + [ + "INT_INTERFACE_LH8", + "VFRAME_LH8" + ], + [ + "INT_INTERFACE_IMUX43", + "VFRAME_IMUX43" + ], + [ + "INT_INTERFACE_EE2A0", + "VFRAME_EE2A0" + ], + [ + "INT_INTERFACE_WL1END1", + "VFRAME_WL1END1" + ], + [ + "INT_INTERFACE_IMUX13", + "VFRAME_IMUX13" + ], + [ + "INT_INTERFACE_FAN0", + "VFRAME_FAN0" + ], + [ + "INT_INTERFACE_WW4B3", + "VFRAME_WW4B3" + ], + [ + "INT_INTERFACE_ER1BEG3", + "VFRAME_ER1BEG3" + ], + [ + "INT_INTERFACE_NE4C3", + "VFRAME_NE4C3" + ], + [ + "INT_INTERFACE_NE4C0", + "VFRAME_NE4C0" + ], + [ + "INT_INTERFACE_LH9", + "VFRAME_LH9" + ], + [ + "INT_INTERFACE_IMUX31", + "VFRAME_IMUX31" + ], + [ + "INT_INTERFACE_IMUX22", + "VFRAME_IMUX22" + ], + [ + "INT_INTERFACE_IMUX27", + "VFRAME_IMUX27" + ], + [ + "INT_INTERFACE_SW2A0", + "VFRAME_SW2A0" + ], + [ + "INT_INTERFACE_WW4B0", + "VFRAME_WW4B0" + ], + [ + "INT_INTERFACE_WW4C1", + "VFRAME_WW4C1" + ], + [ + "INT_INTERFACE_SE4C2", + "VFRAME_SE4C2" + ], + [ + "INT_INTERFACE_NE2A3", + "VFRAME_NE2A3" + ], + [ + "INT_INTERFACE_IMUX32", + "VFRAME_IMUX32" + ], + [ + "INT_INTERFACE_WW2END1", + "VFRAME_WW2END1" + ], + [ + "INT_INTERFACE_LH10", + "VFRAME_LH10" + ], + [ + "INT_INTERFACE_SE4BEG0", + "VFRAME_SE4BEG0" + ], + [ + "INT_INTERFACE_IMUX19", + "VFRAME_IMUX19" + ], + [ + "INT_INTERFACE_IMUX34", + "VFRAME_IMUX34" + ], + [ + "INT_INTERFACE_IMUX39", + "VFRAME_IMUX39" + ], + [ + "INT_INTERFACE_WL1END2", + "VFRAME_WL1END2" + ], + [ + "INT_INTERFACE_IMUX1", + "VFRAME_IMUX1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "INT_INTERFACE_IMUX7", + "VFRAME_IMUX7" + ], + [ + "INT_INTERFACE_IMUX16", + "VFRAME_IMUX16" + ], + [ + "INT_INTERFACE_IMUX29", + "VFRAME_IMUX29" + ], + [ + "INT_INTERFACE_WW4END0", + "VFRAME_WW4END0" + ], + [ + "INT_INTERFACE_SW4END2", + "VFRAME_SW4END2" + ], + [ + "INT_INTERFACE_BYP3", + "VFRAME_BYP3" + ], + [ + "INT_INTERFACE_IMUX8", + "VFRAME_IMUX8" + ], + [ + "INT_INTERFACE_WW4A0", + "VFRAME_WW4A0" + ], + [ + "INT_INTERFACE_FAN7", + "VFRAME_FAN7" + ], + [ + "INT_INTERFACE_EE4B2", + "VFRAME_EE4B2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "VFRAME_LOGIC_OUTS_B8" + ], + [ + "INT_INTERFACE_WW4A3", + "VFRAME_WW4A3" + ], + [ + "INT_INTERFACE_SE4C0", + "VFRAME_SE4C0" + ], + [ + "INT_INTERFACE_NW4END3", + "VFRAME_NW4END3" + ], + [ + "INT_INTERFACE_NE2A0", + "VFRAME_NE2A0" + ], + [ + "INT_INTERFACE_IMUX5", + "VFRAME_IMUX5" + ], + [ + "INT_INTERFACE_BYP7", + "VFRAME_BYP7" + ], + [ + "INT_INTERFACE_IMUX30", + "VFRAME_IMUX30" + ], + [ + "INT_INTERFACE_LH11", + "VFRAME_LH11" + ], + [ + "INT_INTERFACE_SW4A0", + "VFRAME_SW4A0" + ], + [ + "INT_INTERFACE_NE4BEG3", + "VFRAME_NE4BEG3" + ], + [ + "INT_INTERFACE_IMUX26", + "VFRAME_IMUX26" + ], + [ + "INT_INTERFACE_BYP4", + "VFRAME_BYP4" + ], + [ + "INT_INTERFACE_EE2A2", + "VFRAME_EE2A2" + ], + [ + "INT_INTERFACE_CTRL1", + "VFRAME_CTRL1" + ], + [ + "INT_INTERFACE_EE4BEG3", + "VFRAME_EE4BEG3" + ], + [ + "INT_INTERFACE_SW2A1", + "VFRAME_SW2A1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "INT_INTERFACE_WW4B1", + "VFRAME_WW4B1" + ], + [ + "INT_INTERFACE_NW4END0", + "VFRAME_NW4END0" + ], + [ + "INT_INTERFACE_EE4B3", + "VFRAME_EE4B3" + ], + [ + "INT_INTERFACE_MONITOR_P", + "VFRAME_MONITOR_P" + ], + [ + "INT_INTERFACE_LH2", + "VFRAME_LH2" + ], + [ + "INT_INTERFACE_SE4BEG2", + "VFRAME_SE4BEG2" + ], + [ + "INT_INTERFACE_IMUX35", + "VFRAME_IMUX35" + ], + [ + "INT_INTERFACE_BYP6", + "VFRAME_BYP6" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "VFRAME_LOGIC_OUTS_B9" + ], + [ + "INT_INTERFACE_ER1BEG2", + "VFRAME_ER1BEG2" + ], + [ + "INT_INTERFACE_BYP5", + "VFRAME_BYP5" + ], + [ + "INT_INTERFACE_WW2A3", + "VFRAME_WW2A3" + ], + [ + "INT_INTERFACE_IMUX0", + "VFRAME_IMUX0" + ], + [ + "INT_INTERFACE_IMUX4", + "VFRAME_IMUX4" + ], + [ + "INT_INTERFACE_WW4B2", + "VFRAME_WW4B2" + ], + [ + "INT_INTERFACE_NW4A3", + "VFRAME_NW4A3" + ], + [ + "INT_INTERFACE_SE4BEG1", + "VFRAME_SE4BEG1" + ], + [ + "INT_INTERFACE_SW4A2", + "VFRAME_SW4A2" + ], + [ + "INT_INTERFACE_IMUX44", + "VFRAME_IMUX44" + ], + [ + "INT_INTERFACE_EE4A1", + "VFRAME_EE4A1" + ], + [ + "INT_INTERFACE_EL1BEG2", + "VFRAME_EL1BEG2" + ], + [ + "INT_INTERFACE_WL1END0", + "VFRAME_WL1END0" + ], + [ + "INT_INTERFACE_IMUX40", + "VFRAME_IMUX40" + ], + [ + "INT_INTERFACE_IMUX36", + "VFRAME_IMUX36" + ], + [ + "INT_INTERFACE_SW2A2", + "VFRAME_SW2A2" + ] + ], + "tile_types": [ + "INT_INTERFACE_L", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_1" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_1" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_1" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_1" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_1" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_1" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_1" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_1" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_1" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_1" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_1" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_1" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_1" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_1" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_1" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_1" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_1" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_1" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_1" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_1" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_1" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_1" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_1" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_1" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_1" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_1" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_1" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_1" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_1" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_1" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_1" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_1" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_1" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_1" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_1" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_1" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_1" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_1" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_1" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_1" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_1" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_1" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_1" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_1" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_1" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_1" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_1" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_1" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_1" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_1" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_1" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_1" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_1" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_1" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_1" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_1" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_1" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_1" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_1" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_1" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_1" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_1" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_1" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_1" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_1" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_1" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_1" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_1" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_1" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_1" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_1" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_1" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_1" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_1" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_1" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_1" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_1" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_1" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_1" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_1" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_1" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_1" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_1" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_1" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_1" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_1" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_1" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_1" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_1" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_1" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_1" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_1" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_1" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_1" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_1" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_1" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_1" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_1" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_1" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_1" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_1" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_1" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_1" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_1" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_1" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_1" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_1" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_1" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_1" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_1" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_1" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_1" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_1" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_1" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_1" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_1" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_1" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_1" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_1" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_1" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_TOP_FUJI2" + ] + }, + { + "grid_deltas": [ + 1, + 9 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SW4A3_2", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_2", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_CLK0_2", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_2", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_EE4BEG2_2", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX32_2", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_EL1BEG2_2", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_2", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_FAN7_2", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_EE4BEG0_2", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_IMUX14_2", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_EE2BEG0_2", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_LH12_2", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX43_2", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_SW2A0_2", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_EE4C0_2", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_FAN6_2", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_WR1END1_2", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_LH9_2", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_WW4END0_2", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX10_2", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_EL1BEG0_2", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_IMUX31_2", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_EE2A2_2", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_SE2A2_2", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX18_2", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_EE2BEG3_2", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_EE2A3_2", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_IMUX45_2", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX26_2", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX21_2", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_SE4C2_2", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WW4B2_2", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_WL1END3_2", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_IMUX0_2", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_IMUX35_2", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_IMUX25_2", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_WW4B1_2", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_WW2END2_2", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_EE4B1_2", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_EE2A0_2", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_IMUX3_2", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_IMUX37_2", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_LH2_2", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EE4A3_2", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B10_2", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "CFG_CENTER_BYP5_2", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_IMUX36_2", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW2A1_2", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_SW4END1_2", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_SE2A3_2", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_WW4END2_2", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX33_2", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_WR1END2_2", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SE4BEG0_2", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_CTRL0_2", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_LH8_2", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_SW2A2_2", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_WW2A3_2", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_BYP3_2", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_EE4A2_2", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_FAN4_2", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_NE4C2_2", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_NW4END3_2", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_IMUX8_2", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_NE4BEG3_2", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NE2A0_2", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX44_2", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_2", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_BYP4_2", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_NE4BEG0_2", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX27_2", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX38_2", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_NW4END1_2", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SE2A0_2", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_2", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_BYP0_2", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX29_2", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_WW4A2_2", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_LH6_2", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_NW4A1_2", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_FAN0_2", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_WL1END2_2", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_SE2A1_2", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_2", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_IMUX30_2", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_WW4A0_2", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_WW4END1_2", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_SW4A1_2", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_2", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_NE4BEG2_2", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_IMUX15_2", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_EE4BEG3_2", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B8_2", + "VFRAME_LOGIC_OUTS_B8" + ], + [ + "CFG_CENTER_WW2A1_2", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_FAN5_2", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_IMUX41_2", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_EE4A1_2", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_LH3_2", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_2", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_IMUX47_2", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_SE4C1_2", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_WW4A3_2", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW4B3_2", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_EL1BEG1_2", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_FAN1_2", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_BYP6_2", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX20_2", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_LH11_2", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_WR1END0_2", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_NW2A3_2", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_BYP2_2", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_WW4C2_2", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_EL1BEG3_2", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_BYP1_2", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SW4A2_2", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_IMUX7_2", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_NW4END0_2", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX6_2", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX28_2", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX19_2", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_EE4C2_2", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_LH1_2", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NE2A1_2", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_NW4A3_2", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_LH7_2", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_NE4C1_2", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_WW2END3_2", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_EE2BEG2_2", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_NE4C0_2", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_NW2A0_2", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_WW2END1_2", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_WW2A0_2", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_IMUX4_2", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_EE4C1_2", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX22_2", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX12_2", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_NE4C3_2", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_WW4END3_2", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX17_2", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX13_2", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_EE4BEG1_2", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_WW4C0_2", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX9_2", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX40_2", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_SE4BEG1_2", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE4B0_2", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WW4B0_2", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_WL1END0_2", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_SE4C0_2", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_SE4BEG3_2", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_SE4BEG2_2", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_SW4END3_2", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_ER1BEG1_2", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_IMUX24_2", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_EE4A0_2", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_NW4A0_2", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B9_2", + "VFRAME_LOGIC_OUTS_B9" + ], + [ + "CFG_CENTER_CTRL1_2", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_WW4C1_2", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_IMUX34_2", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_FAN3_2", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_NE2A3_2", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX2_2", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_IMUX39_2", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_LH10_2", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_ER1BEG0_2", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_IMUX5_2", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_2", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_WL1END1_2", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_IMUX1_2", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX16_2", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WR1END3_2", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_EE4B3_2", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_EE4C3_2", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE2A1_2", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_SW4A0_2", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_2", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B11_2", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "CFG_CENTER_NW2A2_2", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_NE2A2_2", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_SW2A3_2", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_ER1BEG2_2", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_ER1BEG3_2", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_FAN2_2", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_SE4C3_2", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_LH4_2", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_NW4END2_2", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_NE4BEG1_2", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_WW2END0_2", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_EE4B2_2", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_WW4C3_2", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX46_2", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_SW4END0_2", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX23_2", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW2A2_2", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_IMUX42_2", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_NW4A2_2", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_BYP7_2", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_2", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_CLK1_2", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_SW4END2_2", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_LH5_2", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_WW4A1_2", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_2", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_EE2BEG1_2", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_NW2A1_2", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_IMUX11_2", + "VFRAME_IMUX11" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + 5 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_HROW_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_HROW_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_HROW_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_HROW_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_HROW_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_HROW_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_HROW_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_HROW_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_HROW_R_CK_GCLK4" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_HROW_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_HROW_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_HROW_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_HROW_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_HROW_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_HROW_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_HROW_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_HROW_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + ], + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_HROW_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_HROW_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_HROW_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_HROW_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_HROW_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_HROW_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_HROW_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_HROW_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_HROW_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_HROW_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_HROW_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_HROW_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_HROW_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_HROW_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_HROW_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_HROW_BOT_R" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "SE6B3", + "SE6C3" + ], + [ + "SS6D3", + "SS6E3" + ], + [ + "NN6A1", + "NN6BEG1" + ], + [ + "SW6A1", + "SW6B1" + ], + [ + "GCLK_B1", + "GCLK_B1" + ], + [ + "FAN_BOUNCE2", + "FAN_BOUNCE_S3_2" + ], + [ + "SW6D1", + "SW6E1" + ], + [ + "SW6B1", + "SW6C1" + ], + [ + "SE6D2", + "SE6E2" + ], + [ + "SW6C0", + "SW6D0" + ], + [ + "WW4END0", + "WW4END_S0_0" + ], + [ + "SS6E0", + "SS6END0" + ], + [ + "SR1BEG2", + "SR1END2" + ], + [ + "SW6B0", + "SW6C0" + ], + [ + "SS6E1", + "SS6END1" + ], + [ + "NE2A2", + "NE2BEG2" + ], + [ + "WR1BEG0", + "WR1BEG_S0" + ], + [ + "NW2A3", + "NW2BEG3" + ], + [ + "SW6D2", + "SW6E2" + ], + [ + "SS6C1", + "SS6D1" + ], + [ + "NN2A0", + "NN2BEG0" + ], + [ + "SS6E2", + "SS6END2" + ], + [ + "SE6D0", + "SE6E0" + ], + [ + "GCLK_B4", + "GCLK_B4" + ], + [ + "SW6D0", + "SW6E0" + ], + [ + "NN6A2", + "NN6BEG2" + ], + [ + "SS6B2", + "SS6C2" + ], + [ + "SS2A1", + "SS2END1" + ], + [ + "SE6A3", + "SE6B3" + ], + [ + "SS6C0", + "SS6D0" + ], + [ + "SE6A0", + "SE6B0" + ], + [ + "GCLK_B2", + "GCLK_B2" + ], + [ + "SS2A3", + "SS2END3" + ], + [ + "SE6C2", + "SE6D2" + ], + [ + "SE6D1", + "SE6E1" + ], + [ + "GCLK_B5", + "GCLK_B5" + ], + [ + "GCLK_B0", + "GCLK_B0" + ], + [ + "SE6B0", + "SE6C0" + ], + [ + "NN2A1", + "NN2BEG1" + ], + [ + "NN2A2", + "NN2BEG2" + ], + [ + "NW2A2", + "NW2BEG2" + ], + [ + "SE6C0", + "SE6D0" + ], + [ + "LVB10", + "LVB9" + ], + [ + "SW6A3", + "SW6B3" + ], + [ + "SW6B2", + "SW6C2" + ], + [ + "NE2END0", + "NE2END_S3_0" + ], + [ + "SS6C2", + "SS6D2" + ], + [ + "NE2A0", + "NE2BEG0" + ], + [ + "NW6END0", + "NW6END_S0_0" + ], + [ + "NE2A1", + "NE2BEG1" + ], + [ + "SW6C1", + "SW6D1" + ], + [ + "FAN_BOUNCE6", + "FAN_BOUNCE_S3_6" + ], + [ + "NN2END0", + "NN2END_S2_0" + ], + [ + "SS6A1", + "SS6B1" + ], + [ + "SW6A0", + "SW6B0" + ], + [ + "SW6A2", + "SW6B2" + ], + [ + "SE6D3", + "SE6E3" + ], + [ + "SS6B3", + "SS6C3" + ], + [ + "SL1BEG1", + "SL1END1" + ], + [ + "EL1END0", + "EL1END_S3_0" + ], + [ + "LV10", + "LV9" + ], + [ + "NE2A3", + "NE2BEG3" + ], + [ + "SS6D0", + "SS6E0" + ], + [ + "NN2A3", + "NN2BEG3" + ], + [ + "SW6C3", + "SW6D3" + ], + [ + "FAN_BOUNCE0", + "FAN_BOUNCE_S3_0" + ], + [ + "SS6C3", + "SS6D3" + ], + [ + "SS6E3", + "SS6END3" + ], + [ + "SW6C2", + "SW6D2" + ], + [ + "SS6B1", + "SS6C1" + ], + [ + "NW2A1", + "NW2BEG1" + ], + [ + "SS6B0", + "SS6C0" + ], + [ + "NN6END0", + "NN6END_S1_0" + ], + [ + "NN6A3", + "NN6BEG3" + ], + [ + "SS2A2", + "SS2END2" + ], + [ + "GCLK_B3", + "GCLK_B3" + ], + [ + "SW6B3", + "SW6C3" + ], + [ + "SS6A3", + "SS6B3" + ], + [ + "SS6D2", + "SS6E2" + ], + [ + "SE6B2", + "SE6C2" + ], + [ + "SE6A2", + "SE6B2" + ], + [ + "SE6C3", + "SE6D3" + ], + [ + "SL1BEG0", + "SL1END0" + ], + [ + "ER1BEG0", + "ER1BEG_S0" + ], + [ + "SR1BEG3", + "SR1END3" + ], + [ + "SL1BEG3", + "SL1END3" + ], + [ + "SR1BEG1", + "SR1END1" + ], + [ + "SE6B1", + "SE6C1" + ], + [ + "NN6A0", + "NN6BEG0" + ], + [ + "SW6D3", + "SW6E3" + ], + [ + "SS2A0", + "SS2END0" + ], + [ + "SE6C1", + "SE6D1" + ], + [ + "SE6A1", + "SE6B1" + ], + [ + "NW2A0", + "NW2BEG0" + ], + [ + "NL1END0", + "NL1END_S3_0" + ], + [ + "WR1END0", + "WR1END_S1_0" + ], + [ + "FAN_BOUNCE4", + "FAN_BOUNCE_S3_4" + ], + [ + "SS6A0", + "SS6B0" + ], + [ + "SS6D1", + "SS6E1" + ], + [ + "SL1BEG2", + "SL1END2" + ], + [ + "SS6A2", + "SS6B2" + ], + [ + "NW2END0", + "NW2END_S0_0" + ] + ], + "tile_types": [ + "INT_R", + "INT_R" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "DSP_NW2A0_2", + "INT_INTERFACE_NW2A0" + ], + [ + "DSP_IMUX29_2", + "INT_INTERFACE_IMUX29" + ], + [ + "DSP_LH12_2", + "INT_INTERFACE_LH12" + ], + [ + "DSP_LOGIC_OUTS_B7_2", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "DSP_IMUX15_2", + "INT_INTERFACE_IMUX15" + ], + [ + "DSP_WW4B2_2", + "INT_INTERFACE_WW4B2" + ], + [ + "DSP_WW2END0_2", + "INT_INTERFACE_WW2END0" + ], + [ + "DSP_SE4BEG1_2", + "INT_INTERFACE_SE4BEG1" + ], + [ + "DSP_SW2A3_2", + "INT_INTERFACE_SW2A3" + ], + [ + "DSP_LOGIC_OUTS_B2_2", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "DSP_BYP4_2", + "INT_INTERFACE_BYP4" + ], + [ + "DSP_WW4A1_2", + "INT_INTERFACE_WW4A1" + ], + [ + "DSP_IMUX41_2", + "INT_INTERFACE_IMUX41" + ], + [ + "DSP_NW4END3_2", + "INT_INTERFACE_NW4END3" + ], + [ + "DSP_EL1BEG1_2", + "INT_INTERFACE_EL1BEG1" + ], + [ + "DSP_LOGIC_OUTS_B8_2", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "DSP_NE4C3_2", + "INT_INTERFACE_NE4C3" + ], + [ + "DSP_IMUX4_2", + "INT_INTERFACE_IMUX4" + ], + [ + "DSP_IMUX25_2", + "INT_INTERFACE_IMUX25" + ], + [ + "DSP_WW2A3_2", + "INT_INTERFACE_WW2A3" + ], + [ + "DSP_EE4C3_2", + "INT_INTERFACE_EE4C3" + ], + [ + "DSP_LH6_2", + "INT_INTERFACE_LH6" + ], + [ + "DSP_IMUX35_2", + "INT_INTERFACE_IMUX35" + ], + [ + "DSP_CLK1_2", + "INT_INTERFACE_CLK1" + ], + [ + "DSP_LOGIC_OUTS_B11_2", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "DSP_WW4B0_2", + "INT_INTERFACE_WW4B0" + ], + [ + "DSP_IMUX1_2", + "INT_INTERFACE_IMUX1" + ], + [ + "DSP_IMUX42_2", + "INT_INTERFACE_IMUX42" + ], + [ + "DSP_SE4BEG3_2", + "INT_INTERFACE_SE4BEG3" + ], + [ + "DSP_LH11_2", + "INT_INTERFACE_LH11" + ], + [ + "DSP_IMUX47_2", + "INT_INTERFACE_IMUX47" + ], + [ + "DSP_IMUX46_2", + "INT_INTERFACE_IMUX46" + ], + [ + "DSP_IMUX3_2", + "INT_INTERFACE_IMUX3" + ], + [ + "DSP_BYP6_2", + "INT_INTERFACE_BYP6" + ], + [ + "DSP_WW2END3_2", + "INT_INTERFACE_WW2END3" + ], + [ + "DSP_SE4BEG2_2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "DSP_NE4C1_2", + "INT_INTERFACE_NE4C1" + ], + [ + "DSP_IMUX34_2", + "INT_INTERFACE_IMUX34" + ], + [ + "DSP_IMUX23_2", + "INT_INTERFACE_IMUX23" + ], + [ + "DSP_NW4A2_2", + "INT_INTERFACE_NW4A2" + ], + [ + "DSP_IMUX6_2", + "INT_INTERFACE_IMUX6" + ], + [ + "DSP_WW4C3_2", + "INT_INTERFACE_WW4C3" + ], + [ + "DSP_SE2A2_2", + "INT_INTERFACE_SE2A2" + ], + [ + "DSP_IMUX10_2", + "INT_INTERFACE_IMUX10" + ], + [ + "DSP_SW4END0_2", + "INT_INTERFACE_SW4END0" + ], + [ + "DSP_EE2BEG1_2", + "INT_INTERFACE_EE2BEG1" + ], + [ + "DSP_WR1END1_2", + "INT_INTERFACE_WR1END1" + ], + [ + "DSP_IMUX5_2", + "INT_INTERFACE_IMUX5" + ], + [ + "DSP_NW4A0_2", + "INT_INTERFACE_NW4A0" + ], + [ + "DSP_LOGIC_OUTS_B15_2", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "DSP_NE4C0_2", + "INT_INTERFACE_NE4C0" + ], + [ + "DSP_NW4END2_2", + "INT_INTERFACE_NW4END2" + ], + [ + "DSP_NW2A1_2", + "INT_INTERFACE_NW2A1" + ], + [ + "DSP_NE4C2_2", + "INT_INTERFACE_NE4C2" + ], + [ + "DSP_IMUX24_2", + "INT_INTERFACE_IMUX24" + ], + [ + "DSP_SW4A2_2", + "INT_INTERFACE_SW4A2" + ], + [ + "DSP_EL1BEG2_2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "DSP_LH2_2", + "INT_INTERFACE_LH2" + ], + [ + "DSP_WW4A3_2", + "INT_INTERFACE_WW4A3" + ], + [ + "DSP_CTRL0_2", + "INT_INTERFACE_CTRL0" + ], + [ + "DSP_EE4A3_2", + "INT_INTERFACE_EE4A3" + ], + [ + "DSP_LH8_2", + "INT_INTERFACE_LH8" + ], + [ + "DSP_IMUX38_2", + "INT_INTERFACE_IMUX38" + ], + [ + "DSP_EL1BEG3_2", + "INT_INTERFACE_EL1BEG3" + ], + [ + "DSP_LOGIC_OUTS_B16_2", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "DSP_IMUX28_2", + "INT_INTERFACE_IMUX28" + ], + [ + "DSP_SW4A3_2", + "INT_INTERFACE_SW4A3" + ], + [ + "DSP_NE2A2_2", + "INT_INTERFACE_NE2A2" + ], + [ + "DSP_WR1END0_2", + "INT_INTERFACE_WR1END0" + ], + [ + "DSP_BYP2_2", + "INT_INTERFACE_BYP2" + ], + [ + "DSP_FAN5_2", + "INT_INTERFACE_FAN5" + ], + [ + "DSP_LOGIC_OUTS_B18_2", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "DSP_BYP7_2", + "INT_INTERFACE_BYP7" + ], + [ + "DSP_IMUX11_2", + "INT_INTERFACE_IMUX11" + ], + [ + "DSP_LOGIC_OUTS_B9_2", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "DSP_FAN3_2", + "INT_INTERFACE_FAN3" + ], + [ + "DSP_WW4C0_2", + "INT_INTERFACE_WW4C0" + ], + [ + "DSP_LOGIC_OUTS_B5_2", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "DSP_LOGIC_OUTS_B23_2", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "DSP_NE4BEG2_2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "DSP_SE2A3_2", + "INT_INTERFACE_SE2A3" + ], + [ + "DSP_EE4B2_2", + "INT_INTERFACE_EE4B2" + ], + [ + "DSP_LOGIC_OUTS_B1_2", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "DSP_IMUX31_2", + "INT_INTERFACE_IMUX31" + ], + [ + "DSP_IMUX45_2", + "INT_INTERFACE_IMUX45" + ], + [ + "DSP_EE4A0_2", + "INT_INTERFACE_EE4A0" + ], + [ + "DSP_LOGIC_OUTS_B22_2", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "DSP_EE2A1_2", + "INT_INTERFACE_EE2A1" + ], + [ + "DSP_EE2BEG2_2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "DSP_WR1END2_2", + "INT_INTERFACE_WR1END2" + ], + [ + "DSP_WW2A0_2", + "INT_INTERFACE_WW2A0" + ], + [ + "DSP_LOGIC_OUTS_B17_2", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "DSP_IMUX12_2", + "INT_INTERFACE_IMUX12" + ], + [ + "DSP_WL1END1_2", + "INT_INTERFACE_WL1END1" + ], + [ + "DSP_IMUX8_2", + "INT_INTERFACE_IMUX8" + ], + [ + "DSP_IMUX14_2", + "INT_INTERFACE_IMUX14" + ], + [ + "DSP_BYP5_2", + "INT_INTERFACE_BYP5" + ], + [ + "DSP_SE4C1_2", + "INT_INTERFACE_SE4C1" + ], + [ + "DSP_IMUX9_2", + "INT_INTERFACE_IMUX9" + ], + [ + "DSP_IMUX13_2", + "INT_INTERFACE_IMUX13" + ], + [ + "DSP_FAN1_2", + "INT_INTERFACE_FAN1" + ], + [ + "DSP_EE2BEG3_2", + "INT_INTERFACE_EE2BEG3" + ], + [ + "DSP_NW2A3_2", + "INT_INTERFACE_NW2A3" + ], + [ + "DSP_CTRL1_2", + "INT_INTERFACE_CTRL1" + ], + [ + "DSP_FAN6_2", + "INT_INTERFACE_FAN6" + ], + [ + "DSP_NW2A2_2", + "INT_INTERFACE_NW2A2" + ], + [ + "DSP_LH5_2", + "INT_INTERFACE_LH5" + ], + [ + "DSP_IMUX32_2", + "INT_INTERFACE_IMUX32" + ], + [ + "DSP_IMUX40_2", + "INT_INTERFACE_IMUX40" + ], + [ + "DSP_MONITOR_P_2", + "INT_INTERFACE_MONITOR_P" + ], + [ + "DSP_ER1BEG2_2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "DSP_FAN0_2", + "INT_INTERFACE_FAN0" + ], + [ + "DSP_SE4C0_2", + "INT_INTERFACE_SE4C0" + ], + [ + "DSP_IMUX2_2", + "INT_INTERFACE_IMUX2" + ], + [ + "DSP_WW4END2_2", + "INT_INTERFACE_WW4END2" + ], + [ + "DSP_IMUX17_2", + "INT_INTERFACE_IMUX17" + ], + [ + "DSP_EE2A2_2", + "INT_INTERFACE_EE2A2" + ], + [ + "DSP_SE4C3_2", + "INT_INTERFACE_SE4C3" + ], + [ + "DSP_SW2A0_2", + "INT_INTERFACE_SW2A0" + ], + [ + "DSP_NE4BEG1_2", + "INT_INTERFACE_NE4BEG1" + ], + [ + "DSP_EE4BEG1_2", + "INT_INTERFACE_EE4BEG1" + ], + [ + "DSP_WW2END1_2", + "INT_INTERFACE_WW2END1" + ], + [ + "DSP_IMUX16_2", + "INT_INTERFACE_IMUX16" + ], + [ + "DSP_LOGIC_OUTS_B21_2", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "DSP_SE4BEG0_2", + "INT_INTERFACE_SE4BEG0" + ], + [ + "DSP_LH4_2", + "INT_INTERFACE_LH4" + ], + [ + "DSP_IMUX43_2", + "INT_INTERFACE_IMUX43" + ], + [ + "DSP_IMUX30_2", + "INT_INTERFACE_IMUX30" + ], + [ + "DSP_WW4END0_2", + "INT_INTERFACE_WW4END0" + ], + [ + "DSP_NE2A1_2", + "INT_INTERFACE_NE2A1" + ], + [ + "DSP_LH3_2", + "INT_INTERFACE_LH3" + ], + [ + "DSP_SW4END3_2", + "INT_INTERFACE_SW4END3" + ], + [ + "DSP_WR1END3_2", + "INT_INTERFACE_WR1END3" + ], + [ + "DSP_IMUX18_2", + "INT_INTERFACE_IMUX18" + ], + [ + "DSP_LOGIC_OUTS_B0_2", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "DSP_FAN7_2", + "INT_INTERFACE_FAN7" + ], + [ + "DSP_WW4B3_2", + "INT_INTERFACE_WW4B3" + ], + [ + "DSP_FAN4_2", + "INT_INTERFACE_FAN4" + ], + [ + "DSP_SW4END1_2", + "INT_INTERFACE_SW4END1" + ], + [ + "DSP_LOGIC_OUTS_B19_2", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "DSP_EE4B0_2", + "INT_INTERFACE_EE4B0" + ], + [ + "DSP_EE4BEG2_2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "DSP_IMUX44_2", + "INT_INTERFACE_IMUX44" + ], + [ + "DSP_WW4END3_2", + "INT_INTERFACE_WW4END3" + ], + [ + "DSP_SE2A1_2", + "INT_INTERFACE_SE2A1" + ], + [ + "DSP_LOGIC_OUTS_B20_2", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "DSP_SW4END2_2", + "INT_INTERFACE_SW4END2" + ], + [ + "DSP_LH7_2", + "INT_INTERFACE_LH7" + ], + [ + "DSP_BYP1_2", + "INT_INTERFACE_BYP1" + ], + [ + "DSP_IMUX37_2", + "INT_INTERFACE_IMUX37" + ], + [ + "DSP_SE2A0_2", + "INT_INTERFACE_SE2A0" + ], + [ + "DSP_WL1END3_2", + "INT_INTERFACE_WL1END3" + ], + [ + "DSP_EE2A0_2", + "INT_INTERFACE_EE2A0" + ], + [ + "DSP_EE4A2_2", + "INT_INTERFACE_EE4A2" + ], + [ + "DSP_LOGIC_OUTS_B3_2", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "DSP_SE4C2_2", + "INT_INTERFACE_SE4C2" + ], + [ + "DSP_NW4A1_2", + "INT_INTERFACE_NW4A1" + ], + [ + "DSP_LOGIC_OUTS_B4_2", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "DSP_NE2A0_2", + "INT_INTERFACE_NE2A0" + ], + [ + "DSP_EE2A3_2", + "INT_INTERFACE_EE2A3" + ], + [ + "DSP_NW4END0_2", + "INT_INTERFACE_NW4END0" + ], + [ + "DSP_IMUX20_2", + "INT_INTERFACE_IMUX20" + ], + [ + "DSP_FAN2_2", + "INT_INTERFACE_FAN2" + ], + [ + "DSP_IMUX22_2", + "INT_INTERFACE_IMUX22" + ], + [ + "DSP_CLK0_2", + "INT_INTERFACE_CLK0" + ], + [ + "DSP_IMUX33_2", + "INT_INTERFACE_IMUX33" + ], + [ + "DSP_IMUX39_2", + "INT_INTERFACE_IMUX39" + ], + [ + "DSP_SW4A1_2", + "INT_INTERFACE_SW4A1" + ], + [ + "DSP_IMUX19_2", + "INT_INTERFACE_IMUX19" + ], + [ + "DSP_WW4C2_2", + "INT_INTERFACE_WW4C2" + ], + [ + "DSP_NE2A3_2", + "INT_INTERFACE_NE2A3" + ], + [ + "DSP_WW4A0_2", + "INT_INTERFACE_WW4A0" + ], + [ + "DSP_EE4C0_2", + "INT_INTERFACE_EE4C0" + ], + [ + "DSP_NW4A3_2", + "INT_INTERFACE_NW4A3" + ], + [ + "DSP_WL1END0_2", + "INT_INTERFACE_WL1END0" + ], + [ + "DSP_LH9_2", + "INT_INTERFACE_LH9" + ], + [ + "DSP_NW4END1_2", + "INT_INTERFACE_NW4END1" + ], + [ + "DSP_LOGIC_OUTS_B6_2", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "DSP_WL1END2_2", + "INT_INTERFACE_WL1END2" + ], + [ + "DSP_LH1_2", + "INT_INTERFACE_LH1" + ], + [ + "DSP_WW4B1_2", + "INT_INTERFACE_WW4B1" + ], + [ + "DSP_IMUX21_2", + "INT_INTERFACE_IMUX21" + ], + [ + "DSP_WW2END2_2", + "INT_INTERFACE_WW2END2" + ], + [ + "DSP_EE4B1_2", + "INT_INTERFACE_EE4B1" + ], + [ + "DSP_EL1BEG0_2", + "INT_INTERFACE_EL1BEG0" + ], + [ + "DSP_LOGIC_OUTS_B14_2", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "DSP_MONITOR_N_2", + "INT_INTERFACE_MONITOR_N" + ], + [ + "DSP_BYP0_2", + "INT_INTERFACE_BYP0" + ], + [ + "DSP_EE2BEG0_2", + "INT_INTERFACE_EE2BEG0" + ], + [ + "DSP_ER1BEG3_2", + "INT_INTERFACE_ER1BEG3" + ], + [ + "DSP_EE4C1_2", + "INT_INTERFACE_EE4C1" + ], + [ + "DSP_WW4A2_2", + "INT_INTERFACE_WW4A2" + ], + [ + "DSP_EE4C2_2", + "INT_INTERFACE_EE4C2" + ], + [ + "DSP_WW4C1_2", + "INT_INTERFACE_WW4C1" + ], + [ + "DSP_BYP3_2", + "INT_INTERFACE_BYP3" + ], + [ + "DSP_IMUX27_2", + "INT_INTERFACE_IMUX27" + ], + [ + "DSP_LOGIC_OUTS_B10_2", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "DSP_EE4BEG3_2", + "INT_INTERFACE_EE4BEG3" + ], + [ + "DSP_LOGIC_OUTS_B13_2", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "DSP_EE4BEG0_2", + "INT_INTERFACE_EE4BEG0" + ], + [ + "DSP_WW2A1_2", + "INT_INTERFACE_WW2A1" + ], + [ + "DSP_EE4B3_2", + "INT_INTERFACE_EE4B3" + ], + [ + "DSP_IMUX7_2", + "INT_INTERFACE_IMUX7" + ], + [ + "DSP_NE4BEG3_2", + "INT_INTERFACE_NE4BEG3" + ], + [ + "DSP_EE4A1_2", + "INT_INTERFACE_EE4A1" + ], + [ + "DSP_NE4BEG0_2", + "INT_INTERFACE_NE4BEG0" + ], + [ + "DSP_ER1BEG0_2", + "INT_INTERFACE_ER1BEG0" + ], + [ + "DSP_ER1BEG1_2", + "INT_INTERFACE_ER1BEG1" + ], + [ + "DSP_SW2A2_2", + "INT_INTERFACE_SW2A2" + ], + [ + "DSP_LH10_2", + "INT_INTERFACE_LH10" + ], + [ + "DSP_IMUX26_2", + "INT_INTERFACE_IMUX26" + ], + [ + "DSP_WW2A2_2", + "INT_INTERFACE_WW2A2" + ], + [ + "DSP_WW4END1_2", + "INT_INTERFACE_WW4END1" + ], + [ + "DSP_IMUX36_2", + "INT_INTERFACE_IMUX36" + ], + [ + "DSP_IMUX0_2", + "INT_INTERFACE_IMUX0" + ], + [ + "DSP_SW4A0_2", + "INT_INTERFACE_SW4A0" + ], + [ + "DSP_SW2A1_2", + "INT_INTERFACE_SW2A1" + ] + ], + "tile_types": [ + "DSP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + 5 + ], + "wire_pairs": [ + [ + "CMT_R_TOP_UPPER_B_CLKPLL3", + "HCLK_CMT_MUX_CLK_PLL3" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT2", + "HCLK_CMT_FREQ_REF_NS2" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL7", + "HCLK_CMT_MUX_CLK_PLL7" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT0", + "HCLK_CMT_FREQ_REF_NS0" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL1", + "HCLK_CMT_MUX_CLK_PLL1" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT3", + "HCLK_CMT_FREQ_REF_NS3" + ], + [ + "CMT_FREQ_PHASER_REFMUX_0", + "HCLK_CMT_FREQ_PHASER_REFMUX_0" + ], + [ + "CMT_FREQ_PHASER_REFMUX_2", + "HCLK_CMT_FREQ_PHASER_REFMUX_2" + ], + [ + "CMT_PHY_CONTROL_IBURSTPENDING0", + "HCLK_CMT_IBURSTPENDING0" + ], + [ + "CMT_L_TOP_UPPER_B_CLKINT_3", + "HCLK_CMT_MUX_CLKINT_3" + ], + [ + "CMT_PHASER_IN_D_RCLK3", + "HCLK_CMT_PHASERIN_RCLK3" + ], + [ + "CMT_R_TOP_UPPER_B_CLKIN1", + "HCLK_CMT_MUX_PLLE2_CLKIN1" + ], + [ + "CMT_PHY_CONTROL_IRANKB0", + "HCLK_CMT_PHY_CONTROL_IRANKB0" + ], + [ + "CMT_R_TOP_UPPER_B_CLKIN2", + "HCLK_CMT_MUX_PLLE2_CLKIN2" + ], + [ + "CMT_FREQ_PHASER_REFMUX_1", + "HCLK_CMT_FREQ_PHASER_REFMUX_1" + ], + [ + "CMT_PHY_CONTROL_OBURSTPENDING0", + "HCLK_CMT_OBURSTPENDING0" + ], + [ + "CMT_PHASER_REF_TMUXOUT_TOHCLK", + "HCLK_CMT_PREF_TMUXOUT" + ], + [ + "CMT_PHASER_REF_CLKOUT_TOHCLK", + "HCLK_CMT_PREF_CLKOUT" + ], + [ + "CMT_L_TOP_UPPER_B_CLKINT_2", + "HCLK_CMT_MUX_CLKINT_2" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL0", + "HCLK_CMT_MUX_CLK_PLL0" + ], + [ + "CMT_PHY_CONTROL_IRANKA1", + "HCLK_CMT_PHY_CONTROL_IRANKA1" + ], + [ + "CMT_PHASER_UP_PHASERREF_ABOVE1", + "HCLK_CMT_PHASEREF_ABOVE1" + ], + [ + "CMT_PHASER_UP_PHASERREF0", + "HCLK_CMT_BUFMR_PHASEREF0" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL2", + "HCLK_CMT_MUX_CLK_PLL2" + ], + [ + "CMT_PHASER_UP_BUFMRCE_CE0", + "HCLK_CMT_BUFMR_CE0" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL6", + "HCLK_CMT_MUX_CLK_PLL6" + ], + [ + "CMT_PHASER_TOP_SYNC_BB", + "HCLK_CMT_PHY_SYNC_BB" + ], + [ + "CMT_PHY_CONTROL_IBURSTPENDING1", + "HCLK_CMT_IBURSTPENDING1" + ], + [ + "CMT_PHY_CONTROL_OBURSTPENDING1", + "HCLK_CMT_OBURSTPENDING1" + ], + [ + "CMT_PHASER_UP_BUFMRCE_CE1", + "HCLK_CMT_BUFMR_CE1" + ], + [ + "CMT_PHY_CONTROL_IRANKB1", + "HCLK_CMT_PHY_CONTROL_IRANKB1" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL4", + "HCLK_CMT_MUX_CLK_PLL4" + ], + [ + "CMT_PHASER_IN_C_RCLK2", + "HCLK_CMT_PHASERIN_RCLK2" + ], + [ + "CMT_PHASER_UP_PHASERREF_BELOW1", + "HCLK_CMT_PHASEREF_BELOW1" + ], + [ + "CMT_PHASER_UP_PHASERREF_BELOW0", + "HCLK_CMT_PHASEREF_BELOW0" + ], + [ + "CMT_R_TOP_UPPER_B_CLKPLL5", + "HCLK_CMT_MUX_CLK_PLL5" + ], + [ + "CMT_PHY_CONTROL_ECALIB0", + "HCLK_CMT_ECALIB0" + ], + [ + "CMT_PHY_CONTROL_IRANKA0", + "HCLK_CMT_PHY_CONTROL_IRANKA0" + ], + [ + "CMT_PHY_CONTROL_ECALIB1", + "HCLK_CMT_ECALIB1" + ], + [ + "PLL_CLK_FREQBB_REBUFOUT1", + "HCLK_CMT_FREQ_REF_NS1" + ], + [ + "CMT_PHASER_UP_PHASERREF_ABOVE0", + "HCLK_CMT_PHASEREF_ABOVE0" + ], + [ + "CMT_R_TOP_UPPER_B_CLKFBIN", + "HCLK_CMT_MUX_PLLE2_CLKFBIN" + ], + [ + "CMT_PHASER_UP_PHASERREF1", + "HCLK_CMT_BUFMR_PHASEREF1" + ] + ], + "tile_types": [ + "CMT_TOP_L_UPPER_B", + "HCLK_CMT_L" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "CLK_HROW_WW2END0_5", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_WL1END3_5", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_SW4END1_5", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_WW2END2_5", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_WW4B0_5", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_WW4C2_5", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_ER1BEG1_5", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_EE4C2_5", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_WR1END3_5", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_EE4C1_5", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_EE4BEG2_5", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_LH11_5", + "VBRK_LH11" + ], + [ + "CLK_HROW_NW4A0_5", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_WL1END0_5", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_NE4C2_5", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_NW2A0_5", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_NE2A0_5", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_SW2A2_5", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_EE4B0_5", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_SW2A3_5", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_EE4A2_5", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_SW4END0_5", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_WL1END1_5", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_WW4END1_5", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_EL1BEG3_5", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_SE4C3_5", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_WW2END1_5", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_NE4BEG3_5", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_NW2A1_5", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_EE4C0_5", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_NW4A2_5", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_ER1BEG2_5", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_EE2A3_5", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_NE4BEG2_5", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WW4END3_5", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_LH7_5", + "VBRK_LH7" + ], + [ + "CLK_HROW_EE2BEG1_5", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_SW4END2_5", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_EL1BEG1_5", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_NE4C1_5", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_LH2_5", + "VBRK_LH2" + ], + [ + "CLK_HROW_SE4C0_5", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_WW4END0_5", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_NE4C0_5", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_EE4A0_5", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SE2A3_5", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_EE2BEG2_5", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_NW4END3_5", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_WL1END2_5", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_EE4A3_5", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_WW4B2_5", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_WR1END0_5", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_WW4B3_5", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_SE4BEG2_5", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_EE4BEG1_5", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WW4C1_5", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_SE4BEG3_5", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_SE2A1_5", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_LH12_5", + "VBRK_LH12" + ], + [ + "CLK_HROW_SE4C2_5", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_EE4B2_5", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_WW2A1_5", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_NW4END0_5", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW4C0_5", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_ER1BEG0_5", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_EE4C3_5", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_WW2A0_5", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_SW2A0_5", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_LH3_5", + "VBRK_LH3" + ], + [ + "CLK_HROW_WW4END2_5", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_EE2BEG3_5", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_NW4A3_5", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_NW4END1_5", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_WW4B1_5", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_NW2A3_5", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_LH5_5", + "VBRK_LH5" + ], + [ + "CLK_HROW_EE2A1_5", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_NW4A1_5", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_SE2A2_5", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_LH1_5", + "VBRK_LH1" + ], + [ + "CLK_HROW_NW2A2_5", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_SE4C1_5", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_WR1END2_5", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_SW4A2_5", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_WW2A3_5", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_EE4BEG0_5", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_WW2A2_5", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_NE4BEG1_5", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_EE4A1_5", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_WW4C3_5", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_LH4_5", + "VBRK_LH4" + ], + [ + "CLK_HROW_SE4BEG1_5", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_WW4A1_5", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_NE2A3_5", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_WW4A0_5", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_EE2A0_5", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_EE2A2_5", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_NW4END2_5", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_SW4A0_5", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_LH8_5", + "VBRK_LH8" + ], + [ + "CLK_HROW_EE2BEG0_5", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_EE4B3_5", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_WR1END1_5", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_SW4END3_5", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_WW2END3_5", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_NE4C3_5", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_EL1BEG0_5", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_NE4BEG0_5", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_EL1BEG2_5", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WW4A3_5", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_SE2A0_5", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_SW2A1_5", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_LH6_5", + "VBRK_LH6" + ], + [ + "CLK_HROW_NE2A1_5", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_WW4A2_5", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_LH10_5", + "VBRK_LH10" + ], + [ + "CLK_HROW_SW4A1_5", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_NE2A2_5", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_EE4B1_5", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_LH9_5", + "VBRK_LH9" + ], + [ + "CLK_HROW_EE4BEG3_5", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_SE4BEG0_5", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_SW4A3_5", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_ER1BEG3_5", + "VBRK_ER1BEG3" + ] + ], + "tile_types": [ + "CLK_HROW_TOP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CMT_FIFO_LH7_6", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_NW4END3_6", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_NW4A2_6", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_LH6_6", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_SW4A2_6", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_L_FAN1_6", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_WW4C1_6", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_SW4A3_6", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_L_CTRL0_6", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_SE2A3_6", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_WL1END1_6", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_EE4B3_6", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_EE4A2_6", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_IMUX28_6", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_6", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CMT_FIFO_L_IMUX0_6", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_EE4C0_6", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_L_CTRL1_6", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_L_FAN5_6", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_WW4A3_6", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_L_IMUX46_6", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_L_IMUX9_6", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_ER1BEG3_6", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_WW2A3_6", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_EE4C3_6", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_L_BYP6_6", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_EE4A3_6", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_NW4A3_6", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_WW4A2_6", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_WW2END1_6", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_NE4C0_6", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_NE4C1_6", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_L_IMUX39_6", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_L_IMUX4_6", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_SE4BEG3_6", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_WR1END3_6", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_NE4BEG2_6", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_6", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "CMT_FIFO_L_IMUX18_6", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_NE2A1_6", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_SW4A0_6", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_6", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CMT_FIFO_L_IMUX8_6", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_EE2A1_6", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_SW4END3_6", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_EE2A3_6", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_L_IMUX25_6", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_L_FAN7_6", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_SW4END1_6", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_L_FAN2_6", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_L_BYP5_6", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_L_IMUX40_6", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_EE2A2_6", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_EL1BEG3_6", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_NW4END0_6", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_MONITOR_N_6", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CMT_FIFO_SE4C1_6", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_L_IMUX33_6", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_L_BYP4_6", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_NE2A0_6", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_IMUX29_6", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_NW2A2_6", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_EL1BEG0_6", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_WR1END0_6", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_L_BYP1_6", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_NE4BEG3_6", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_EL1BEG2_6", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_WW2END0_6", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_L_IMUX13_6", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_WW2A2_6", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_WL1END3_6", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_6", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CMT_FIFO_WW4B2_6", + "INT_INTERFACE_WW4B2" + ], + [ + "FIFO_DQS_IOTOPHASER_1", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "CMT_FIFO_L_IMUX15_6", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_CLK1_6", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_EE4B1_6", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_NE4BEG0_6", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_6", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "CMT_FIFO_WW4END3_6", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_SE4BEG0_6", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_EL1BEG1_6", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_6", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CMT_FIFO_ER1BEG2_6", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_IMUX35_6", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_NE4C2_6", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_LH3_6", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_L_IMUX2_6", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_L_IMUX36_6", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_L_IMUX31_6", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_WW4B3_6", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_WW2END2_6", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_L_IMUX38_6", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_L_BYP0_6", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_NW2A3_6", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_L_IMUX30_6", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_SE2A2_6", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_6", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CMT_FIFO_SW2A0_6", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_L_IMUX3_6", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_6", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_6", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CMT_FIFO_L_FAN3_6", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_SW4END2_6", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_EE2BEG1_6", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_L_BYP2_6", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_L_IMUX17_6", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_NE4BEG1_6", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_6", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "CMT_FIFO_WW4C0_6", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_EE4B0_6", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_L_IMUX7_6", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_EE4BEG3_6", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_MONITOR_P_6", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CMT_FIFO_L_IMUX22_6", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_6", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_6", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CMT_FIFO_SE4C3_6", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_L_BYP7_6", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_6", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CMT_FIFO_L_IMUX47_6", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_LH1_6", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_L_IMUX37_6", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_NW4A1_6", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_WW4END0_6", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_LH8_6", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_6", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "CMT_FIFO_LH2_6", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_NW2A1_6", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_L_IMUX24_6", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_6", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "CMT_FIFO_L_IMUX44_6", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_IMUX21_6", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_L_FAN4_6", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_L_FAN0_6", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_L_IMUX27_6", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_SW2A3_6", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_NW4A0_6", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_ER1BEG0_6", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_EE4A0_6", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_WW4END2_6", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_6", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "CMT_FIFO_NW4END2_6", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_6", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "CMT_FIFO_SW4A1_6", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_L_IMUX19_6", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_WW2A1_6", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_SW2A1_6", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_L_IMUX11_6", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_SE4C2_6", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_EE2BEG0_6", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_NE4C3_6", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_6", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_EE4C2_6", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_SE4C0_6", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_EE2BEG3_6", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_WW4B0_6", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_LH12_6", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_LH11_6", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_L_IMUX5_6", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_WL1END0_6", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_6", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CMT_FIFO_SE2A1_6", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_SW2A2_6", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_WW4C3_6", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_WW4C2_6", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_IMUX34_6", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_WW2END3_6", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_SW4END0_6", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_WL1END2_6", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_L_IMUX10_6", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_EE4BEG1_6", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_LH4_6", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_EE2BEG2_6", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_L_IMUX23_6", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_WR1END1_6", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_L_IMUX45_6", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_SE2A0_6", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_EE4A1_6", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_L_IMUX41_6", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_FAN6_6", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_WW4END1_6", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_6", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "CMT_FIFO_NW4END1_6", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_LH10_6", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_6", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CMT_FIFO_L_BYP3_6", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_SE4BEG2_6", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX20_6", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_ER1BEG1_6", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_NW2A0_6", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_6", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "CMT_FIFO_L_IMUX14_6", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_WW4A0_6", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_L_IMUX12_6", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_L_IMUX42_6", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_LH5_6", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_L_IMUX26_6", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_6", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "CMT_FIFO_L_IMUX1_6", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_NE2A2_6", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_L_IMUX43_6", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_EE4C1_6", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_EE4BEG0_6", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_EE2A0_6", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_WW4B1_6", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_EE4B2_6", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_6", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "CMT_FIFO_L_IMUX6_6", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_L_CLK0_6", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_WW2A0_6", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_SE4BEG1_6", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_WW4A1_6", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_WR1END2_6", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_LH9_6", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_NE2A3_6", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_L_IMUX32_6", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_EE4BEG2_6", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX16_6", + "INT_INTERFACE_IMUX16" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "CLK_HROW_SE2A0_2", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_WW2A0_2", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4C1_2", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_EE4BEG0_2", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_NE4BEG3_2", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_SE2A1_2", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_WW4END3_2", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_SW2A1_2", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_BUFG_IMUX44_2", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_EE4A2_2", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_WW4B0_2", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_EE4C2_2", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_BUFG_IMUX15_2", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_NW2A2_2", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_LH8_2", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_EE4B1_2", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_WL1END2_2", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_SE4BEG1_2", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_BUFG_IMUX16_2", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_NW4A3_2", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WW2END2_2", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_BUFG_IMUX10_2", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_BUFG_IMUX37_2", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_BUFG_IMUX14_2", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_BUFG_IMUX28_2", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_WW4END1_2", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_LH12_2", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_EE2BEG3_2", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_BUFG_IMUX3_2", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_BUFG_IMUX25_2", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_NE4C0_2", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_WW4B2_2", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_SE4C2_2", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_SW4END3_2", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_FAN7_2", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_BUFG_IMUX17_2", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_BUFG_IMUX20_2", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_NW4END3_2", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_BUFG_IMUX19_2", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_BUFG_IMUX30_2", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_LH10_2", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_SW4END1_2", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_WW2A3_2", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_BYP4_2", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_FAN2_2", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_BUFG_IMUX2_2", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_LH1_2", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_NE2A3_2", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_BYP0_2", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_EE4BEG2_2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_WW4B3_2", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B7_2", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CLK_HROW_WR1END2_2", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_BUFG_IMUX36_2", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_ER1BEG3_2", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_BYP5_2", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_SW4END0_2", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_SE4C0_2", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_NE4BEG2_2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_LH2_2", + "INT_INTERFACE_LH2" + ], + [ + "CLK_BUFG_IMUX42_2", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_WW4END2_2", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_NW4END0_2", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_NW4A1_2", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B0_2", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CLK_HROW_WW4C3_2", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_BYP1_2", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_NE2A1_2", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_ER1BEG1_2", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B3_2", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CLK_HROW_SE2A2_2", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_BUFG_IMUX13_2", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_EL1BEG1_2", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_NW2A0_2", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_SW2A2_2", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_EE4A1_2", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_NE4BEG1_2", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_BUFG_IMUX18_2", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B1_2", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CLK_HROW_WW4B1_2", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_NE2A2_2", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_SE4BEG2_2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_BUFG_IMUX39_2", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_BUFG_IMUX1_2", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_WW4A0_2", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_BYP7_2", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_WW2END3_2", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_WW4A3_2", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_SW4END2_2", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_WW2END0_2", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_BUFG_IMUX23_2", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_EE2BEG2_2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_WW4A1_2", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_NW4A2_2", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_BYP3_2", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_LH6_2", + "INT_INTERFACE_LH6" + ], + [ + "CLK_BUFG_IMUX33_2", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_BUFG_IMUX43_2", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_NW2A3_2", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_EE2A1_2", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_LH9_2", + "INT_INTERFACE_LH9" + ], + [ + "CLK_BUFG_IMUX45_2", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_BUFG_IMUX31_2", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_EE4BEG1_2", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_WR1END3_2", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_WL1END0_2", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_CLK0_2", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_WR1END1_2", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_FAN5_2", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_WW4C0_2", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_BUFG_IMUX46_2", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_SE4C3_2", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_NW4END1_2", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_LH3_2", + "INT_INTERFACE_LH3" + ], + [ + "CLK_BUFG_IMUX47_2", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_WW2A1_2", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_SE4C1_2", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_CTRL0_2", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_FAN1_2", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_EL1BEG0_2", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_NE4C1_2", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_BUFG_IMUX5_2", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_BYP6_2", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_NE4BEG0_2", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_FAN6_2", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_SW2A3_2", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_BUFG_IMUX40_2", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_EL1BEG3_2", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_NE4C3_2", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_BYP2_2", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_SW4A1_2", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_WW4C1_2", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_NW2A1_2", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_LH11_2", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_SW4A3_2", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_BUFG_IMUX32_2", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_EE2A2_2", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_BUFG_IMUX24_2", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_FAN3_2", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_SW2A0_2", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE2A0_2", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_SW4A0_2", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_BUFG_IMUX29_2", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_WW4END0_2", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_LH7_2", + "INT_INTERFACE_LH7" + ], + [ + "CLK_BUFG_IMUX12_2", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_SE4BEG0_2", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_EE2A3_2", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B2_2", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CLK_HROW_SE4BEG3_2", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_WW2END1_2", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_BUFG_IMUX9_2", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_BUFG_IMUX27_2", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_EE4B3_2", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_BUFG_IMUX11_2", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_EE2BEG0_2", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_CTRL1_2", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_EE4A0_2", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_BUFG_IMUX4_2", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_NW4END2_2", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_SE2A3_2", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_FAN4_2", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_EE2BEG1_2", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_BUFG_IMUX22_2", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_NE2A0_2", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_EE4BEG3_2", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_WR1END0_2", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_ER1BEG0_2", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B5_2", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CLK_BUFG_IMUX7_2", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_WW4A2_2", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_BUFG_IMUX35_2", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_SW4A2_2", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_BUFG_IMUX34_2", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_WW2A2_2", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_EE4C0_2", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_BUFG_IMUX8_2", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_BUFG_IMUX26_2", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_BUFG_IMUX21_2", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_BUFG_IMUX0_2", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_EE4B2_2", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_CLK1_2", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_EL1BEG2_2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_WW4C2_2", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_EE4A3_2", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_EE4B0_2", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_FAN0_2", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B4_2", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CLK_HROW_ER1BEG2_2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_WL1END3_2", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_WL1END1_2", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_BUFG_IMUX41_2", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_NE4C2_2", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_LH4_2", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_NW4A0_2", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_BUFG_IMUX38_2", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_LH5_2", + "INT_INTERFACE_LH5" + ], + [ + "CLK_BUFG_IMUX6_2", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B6_2", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CLK_HROW_EE4C3_2", + "INT_INTERFACE_EE4C3" + ] + ], + "tile_types": [ + "CLK_BUFG_TOP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "FAN_BOUNCE4" + ], + [ + "B_TERM_UTURN_INT_SW6B0", + "NW6C3" + ], + [ + "B_TERM_UTURN_INT_SS6B1", + "NN6C2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG0", + "SL1BEG0" + ], + [ + "B_TERM_UTURN_INT_LVB1", + "LVB11" + ], + [ + "B_TERM_UTURN_INT_SS6C2", + "SS6C2" + ], + [ + "B_TERM_UTURN_INT_LV6", + "LV6" + ], + [ + "B_TERM_UTURN_INT_SS6E0", + "SS6E0" + ], + [ + "B_TERM_UTURN_INT_SW6A3", + "NW6B0" + ], + [ + "B_TERM_UTURN_INT_SW6B0", + "SW6B0" + ], + [ + "B_TERM_UTURN_INT_SS6BEG0", + "NN6A3" + ], + [ + "B_TERM_UTURN_INT_LV8", + "LV11" + ], + [ + "B_TERM_UTURN_INT_LV6", + "LV13" + ], + [ + "B_TERM_UTURN_INT_SS6C2", + "NN6D1" + ], + [ + "B_TERM_UTURN_INT_SS6A2", + "NN6B1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG0", + "SS2BEG0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG1", + "NL1END2" + ], + [ + "B_TERM_UTURN_INT_SW6B1", + "NW6C2" + ], + [ + "B_TERM_UTURN_INT_SS6C3", + "SS6C3" + ], + [ + "B_TERM_UTURN_INT_ER1END_N3_3", + "ER1END_N3_3" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "FAN_BOUNCE0" + ], + [ + "B_TERM_UTURN_INT_SS6A3", + "NN6B0" + ], + [ + "B_TERM_UTURN_INT_SE6D1", + "NE6E2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG1", + "NR1END2" + ], + [ + "B_TERM_UTURN_INT_LV3", + "LV3" + ], + [ + "B_TERM_UTURN_INT_SW6C0", + "SW6C0" + ], + [ + "B_TERM_UTURN_INT_SE6A0", + "SE6A0" + ], + [ + "B_TERM_UTURN_INT_LV9", + "LV10" + ], + [ + "B_TERM_UTURN_INT_SW6A0", + "NW6B3" + ], + [ + "B_TERM_UTURN_INT_LV18", + "LV18" + ], + [ + "B_TERM_UTURN_INT_SS6E0", + "NN6END3" + ], + [ + "B_TERM_UTURN_INT_WR1END0", + "WR1END0" + ], + [ + "B_TERM_UTURN_INT_SE6A2", + "SE6A2" + ], + [ + "B_TERM_UTURN_INT_SS6D1", + "SS6D1" + ], + [ + "B_TERM_UTURN_INT_SE6B0", + "SE6B0" + ], + [ + "B_TERM_UTURN_INT_LV7", + "LV7" + ], + [ + "B_TERM_UTURN_INT_LV8", + "LV8" + ], + [ + "B_TERM_UTURN_INT_LV4", + "LV15" + ], + [ + "B_TERM_UTURN_INT_SS6A3", + "SS6A3" + ], + [ + "B_TERM_UTURN_INT_SW6B3", + "NW6C0" + ], + [ + "B_TERM_UTURN_INT_ER1BEG0", + "EL1BEG_N3" + ], + [ + "B_TERM_UTURN_INT_SE6B2", + "SE6B2" + ], + [ + "B_TERM_UTURN_INT_SE6C2", + "SE6C2" + ], + [ + "B_TERM_UTURN_INT_SE6B0", + "NE6C3" + ], + [ + "B_TERM_UTURN_INT_SE6D0", + "NE6E3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG3", + "NN6A0" + ], + [ + "B_TERM_UTURN_INT_SW6D3", + "NW6E0" + ], + [ + "B_TERM_UTURN_INT_LVB1", + "LVB2" + ], + [ + "B_TERM_UTURN_INT_SS6BEG0", + "SS6BEG0" + ], + [ + "B_TERM_UTURN_INT_SE6D2", + "NE6E1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG1", + "NN2A2" + ], + [ + "B_TERM_UTURN_INT_SS6D1", + "NN6E2" + ], + [ + "B_TERM_UTURN_INT_SE6C3", + "SE6C3" + ], + [ + "B_TERM_UTURN_INT_SS2A2", + "NN2END1" + ], + [ + "B_TERM_UTURN_INT_SE6D1", + "SE6D1" + ], + [ + "B_TERM_UTURN_INT_SS6D0", + "NN6E3" + ], + [ + "B_TERM_UTURN_INT_SS6B3", + "NN6C0" + ], + [ + "B_TERM_UTURN_INT_SE6A1", + "NE6B2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG2", + "SL1BEG2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "FAN_BOUNCE6" + ], + [ + "B_TERM_UTURN_INT_LVB3", + "LVB4" + ], + [ + "B_TERM_UTURN_INT_SE6C3", + "NE6D0" + ], + [ + "B_TERM_UTURN_INT_SE6A2", + "NE6B1" + ], + [ + "B_TERM_UTURN_INT_SE6A0", + "NE6B3" + ], + [ + "B_TERM_UTURN_INT_SS6E3", + "SS6E3" + ], + [ + "B_TERM_UTURN_INT_SS2A0", + "SS2A0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG2", + "SS2BEG2" + ], + [ + "B_TERM_UTURN_INT_ER1BEG0", + "ER1BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG3", + "NR1END0" + ], + [ + "B_TERM_UTURN_INT_SW6A3", + "SW6A3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG3", + "NW2A0" + ], + [ + "B_TERM_UTURN_INT_SS6C1", + "NN6D2" + ], + [ + "B_TERM_UTURN_INT_SE6C0", + "NE6D3" + ], + [ + "B_TERM_UTURN_INT_SW6C0", + "NW6D3" + ], + [ + "B_TERM_UTURN_INT_SW6B2", + "SW6B2" + ], + [ + "B_TERM_UTURN_INT_SS6C1", + "SS6C1" + ], + [ + "B_TERM_UTURN_INT_SS6D3", + "SS6D3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG1", + "SE2BEG1" + ], + [ + "B_TERM_UTURN_INT_SS6B1", + "SS6B1" + ], + [ + "B_TERM_UTURN_INT_LV4", + "LV4" + ], + [ + "B_TERM_UTURN_INT_SW6D0", + "NW6E3" + ], + [ + "B_TERM_UTURN_INT_SS6B0", + "SS6B0" + ], + [ + "B_TERM_UTURN_INT_LV5", + "LV14" + ], + [ + "B_TERM_UTURN_INT_SE2BEG1", + "NE2A2" + ], + [ + "HCLK_LEAF_CLK_B_TOP1", + "GCLK_B1" + ], + [ + "B_TERM_UTURN_INT_SW6D2", + "NW6E1" + ], + [ + "B_TERM_UTURN_INT_SS6BEG3", + "SS6BEG3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG0", + "SE2BEG0" + ], + [ + "B_TERM_UTURN_INT_SW6B3", + "SW6B3" + ], + [ + "B_TERM_UTURN_INT_SW6C1", + "SW6C1" + ], + [ + "B_TERM_UTURN_INT_SE6C1", + "NE6D2" + ], + [ + "B_TERM_UTURN_INT_LV3", + "LV16" + ], + [ + "B_TERM_UTURN_INT_SW6A2", + "NW6B1" + ], + [ + "B_TERM_UTURN_INT_SE6D3", + "SE6D3" + ], + [ + "B_TERM_UTURN_INT_SW6D2", + "SW6D2" + ], + [ + "B_TERM_UTURN_INT_SR1BEG2", + "NL1END1" + ], + [ + "B_TERM_UTURN_INT_SS2A3", + "SS2A3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG2", + "SS6BEG2" + ], + [ + "B_TERM_UTURN_INT_SS6E2", + "SS6E2" + ], + [ + "B_TERM_UTURN_INT_SW6C1", + "NW6D2" + ], + [ + "B_TERM_UTURN_INT_SS6E1", + "SS6E1" + ], + [ + "B_TERM_UTURN_INT_SS6E3", + "NN6END0" + ], + [ + "B_TERM_UTURN_INT_LVB0", + "LVB1" + ], + [ + "B_TERM_UTURN_INT_SE6D0", + "SE6D0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG2", + "SR1BEG2" + ], + [ + "B_TERM_UTURN_INT_SS6B2", + "SS6B2" + ], + [ + "HCLK_LEAF_CLK_B_TOP3", + "GCLK_B3" + ], + [ + "B_TERM_UTURN_INT_SS6A1", + "SS6A1" + ], + [ + "B_TERM_UTURN_INT_WR1BEG0", + "WL1BEG_N3" + ], + [ + "B_TERM_UTURN_INT_SW6D1", + "SW6D1" + ], + [ + "B_TERM_UTURN_INT_SS6B0", + "NN6C3" + ], + [ + "B_TERM_UTURN_INT_SS6C0", + "SS6C0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG3", + "SS2BEG3" + ], + [ + "B_TERM_UTURN_INT_SS2BEG1", + "SS2BEG1" + ], + [ + "HCLK_LEAF_CLK_B_TOP0", + "GCLK_B0" + ], + [ + "B_TERM_UTURN_INT_SW6C2", + "SW6C2" + ], + [ + "B_TERM_UTURN_INT_SW2BEG0", + "SW2BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG1", + "SL1BEG1" + ], + [ + "B_TERM_UTURN_INT_LV18", + "LV1" + ], + [ + "B_TERM_UTURN_INT_SS6D3", + "NN6E0" + ], + [ + "B_TERM_UTURN_INT_LVB5", + "LVB7" + ], + [ + "B_TERM_UTURN_INT_SS6A0", + "NN6B3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG1", + "SW2BEG1" + ], + [ + "B_TERM_UTURN_INT_LVB4", + "LVB8" + ], + [ + "B_TERM_UTURN_INT_SW6A1", + "NW6B2" + ], + [ + "B_TERM_UTURN_INT_SS6C3", + "NN6D0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG2", + "NE2A1" + ], + [ + "B_TERM_UTURN_INT_SS6A0", + "SS6A0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG1", + "SR1BEG1" + ], + [ + "B_TERM_UTURN_INT_SW6C2", + "NW6D1" + ], + [ + "B_TERM_UTURN_INT_LV7", + "LV12" + ], + [ + "B_TERM_UTURN_INT_LVB3", + "LVB9" + ], + [ + "B_TERM_UTURN_INT_SW6C3", + "SW6C3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG1", + "SS6BEG1" + ], + [ + "B_TERM_UTURN_INT_SR1BEG3", + "SR1BEG3" + ], + [ + "B_TERM_UTURN_INT_SE6D3", + "NE6E0" + ], + [ + "B_TERM_UTURN_INT_SE6B3", + "SE6B3" + ], + [ + "B_TERM_UTURN_INT_WR1END0", + "WL1END_N1_3" + ], + [ + "B_TERM_UTURN_INT_SW6D0", + "SW6D0" + ], + [ + "HCLK_LEAF_CLK_B_TOP2", + "GCLK_B2" + ], + [ + "B_TERM_UTURN_INT_LV2", + "LV17" + ], + [ + "B_TERM_UTURN_INT_SW2BEG0", + "NW2A3" + ], + [ + "B_TERM_UTURN_INT_SW6A2", + "SW6A2" + ], + [ + "B_TERM_UTURN_INT_LVB0", + "LVB12" + ], + [ + "B_TERM_UTURN_INT_SR1BEG3", + "NL1END0" + ], + [ + "HCLK_LEAF_CLK_B_TOP4", + "GCLK_B4" + ], + [ + "B_TERM_UTURN_INT_LVB2", + "LVB10" + ], + [ + "B_TERM_UTURN_INT_SS6E1", + "NN6END2" + ], + [ + "B_TERM_UTURN_INT_SS2A0", + "NN2END3" + ], + [ + "B_TERM_UTURN_INT_SW6C3", + "NW6D0" + ], + [ + "B_TERM_UTURN_INT_SE6B2", + "NE6C1" + ], + [ + "B_TERM_UTURN_INT_SW2BEG1", + "NW2A2" + ], + [ + "B_TERM_UTURN_INT_SS6C0", + "NN6D3" + ], + [ + "B_TERM_UTURN_INT_SS6A1", + "NN6B2" + ], + [ + "B_TERM_UTURN_INT_SS6A2", + "SS6A2" + ], + [ + "B_TERM_UTURN_INT_SS6E2", + "NN6END1" + ], + [ + "B_TERM_UTURN_INT_SS6D2", + "SS6D2" + ], + [ + "B_TERM_UTURN_INT_SS6B2", + "NN6C1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "BYP_BOUNCE_N3_7" + ], + [ + "B_TERM_UTURN_INT_SW6D1", + "NW6E2" + ], + [ + "B_TERM_UTURN_INT_ER1END_N3_3", + "EL1END0" + ], + [ + "B_TERM_UTURN_INT_SS2A3", + "NN2END0" + ], + [ + "B_TERM_UTURN_INT_LV9", + "LV9" + ], + [ + "B_TERM_UTURN_INT_SS6D2", + "NN6E1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "BYP_BOUNCE_N3_6" + ], + [ + "B_TERM_UTURN_INT_SS2BEG2", + "NN2A1" + ], + [ + "HCLK_LEAF_CLK_B_TOP5", + "GCLK_B5" + ], + [ + "B_TERM_UTURN_INT_SE6B1", + "SE6B1" + ], + [ + "B_TERM_UTURN_INT_SW2BEG3", + "SW2BEG3" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "BYP_BOUNCE_N3_2" + ], + [ + "B_TERM_UTURN_INT_SE6C1", + "SE6C1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "BYP_BOUNCE_N3_3" + ], + [ + "B_TERM_UTURN_INT_SS6D0", + "SS6D0" + ], + [ + "B_TERM_UTURN_INT_SW2BEG2", + "NW2A1" + ], + [ + "B_TERM_UTURN_INT_LV2", + "LV2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "FAN_BOUNCE2" + ], + [ + "B_TERM_UTURN_INT_SS6BEG2", + "NN6A1" + ], + [ + "B_TERM_UTURN_INT_SS2A1", + "NN2END2" + ], + [ + "B_TERM_UTURN_INT_SE6B3", + "NE6C0" + ], + [ + "B_TERM_UTURN_INT_LV5", + "LV5" + ], + [ + "B_TERM_UTURN_INT_SE2BEG3", + "NE2A0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG3", + "NN2A0" + ], + [ + "B_TERM_UTURN_INT_SW6B2", + "NW6C1" + ], + [ + "B_TERM_UTURN_INT_SW6A0", + "SW6A0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG2", + "NR1END1" + ], + [ + "B_TERM_UTURN_INT_SE2BEG0", + "NE2A3" + ], + [ + "B_TERM_UTURN_INT_SW6B1", + "SW6B1" + ], + [ + "B_TERM_UTURN_INT_SS2A2", + "SS2A2" + ], + [ + "B_TERM_UTURN_INT_SS6B3", + "SS6B3" + ], + [ + "B_TERM_UTURN_INT_SE6D2", + "SE6D2" + ], + [ + "B_TERM_UTURN_INT_LVB2", + "LVB3" + ], + [ + "B_TERM_UTURN_INT_SW6END_N0_3", + "SW6END_N0_3" + ], + [ + "B_TERM_UTURN_INT_SE6A3", + "SE6A3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG2", + "SW2BEG2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG0", + "NR1END3" + ], + [ + "B_TERM_UTURN_INT_SE6C2", + "NE6D1" + ], + [ + "B_TERM_UTURN_INT_WR1BEG0", + "WR1BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG3", + "SL1BEG3" + ], + [ + "B_TERM_UTURN_INT_SE6C0", + "SE6C0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG0", + "NN2A3" + ], + [ + "B_TERM_UTURN_INT_SW6END_N0_3", + "NW6END0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG3", + "SE2BEG3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG1", + "NN6A2" + ], + [ + "B_TERM_UTURN_INT_LVB4", + "LVB5" + ], + [ + "B_TERM_UTURN_INT_SE2BEG2", + "SE2BEG2" + ], + [ + "B_TERM_UTURN_INT_SE6A1", + "SE6A1" + ], + [ + "B_TERM_UTURN_INT_SE6B1", + "NE6C2" + ], + [ + "B_TERM_UTURN_INT_SW6D3", + "SW6D3" + ], + [ + "B_TERM_UTURN_INT_LVB5", + "LVB6" + ], + [ + "B_TERM_UTURN_INT_SE6A3", + "NE6B0" + ], + [ + "B_TERM_UTURN_INT_SW6A1", + "SW6A1" + ], + [ + "B_TERM_UTURN_INT_SS2A1", + "SS2A1" + ] + ], + "tile_types": [ + "HCLK_R_BOT_UTURN", + "INT_R" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B5_7", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX47_7", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_LOGIC_OUTS_B14_7", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX41_7", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX20_7", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_BYP2_7", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_FAN3_7", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN2_7", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_BYP4_7", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_CTRL0_7", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX7_7", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX30_7", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX29_7", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_FAN4_7", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX8_7", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_LOGIC_OUTS_B23_7", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX35_7", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_BYP3_7", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B0_7", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_LOGIC_OUTS_B1_7", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX1_7", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX9_7", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX21_7", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX10_7", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B12_7", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_LOGIC_OUTS_B15_7", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_BYP7_7", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX40_7", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX28_7", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_FAN1_7", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B6_7", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_BYP1_7", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX22_7", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B13_7", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B19_7", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B4_7", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_IMUX34_7", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX18_7", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_LOGIC_OUTS_B16_7", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B9_7", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX16_7", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX0_7", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX32_7", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_CTRL1_7", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_FAN5_7", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_FAN7_7", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX43_7", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_LOGIC_OUTS_B18_7", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX3_7", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_FAN0_7", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX23_7", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX19_7", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX25_7", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX33_7", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_CLK1_7", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX14_7", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_BYP0_7", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_LOGIC_OUTS_B3_7", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX4_7", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX2_7", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX36_7", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX15_7", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_LOGIC_OUTS_B7_7", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_IMUX12_7", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX38_7", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX11_7", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_CLK0_7", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX24_7", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX39_7", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX5_7", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX13_7", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP5_7", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B8_7", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX45_7", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_FAN6_7", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_BYP6_7", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_LOGIC_OUTS_B10_7", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX26_7", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX31_7", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B20_7", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX37_7", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX6_7", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX42_7", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_LOGIC_OUTS_B2_7", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX17_7", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_LOGIC_OUTS_B22_7", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX46_7", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX44_7", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX27_7", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B11_7", + "VBRK_EXT_LOGIC_OUTS_B11" + ] + ], + "tile_types": [ + "GTX_CHANNEL_1", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B5_7", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX47_7", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_LOGIC_OUTS_B14_7", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX41_7", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX20_7", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_BYP2_7", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_FAN3_7", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_BYP4_7", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_FAN2_7", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_CTRL0_7", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX7_7", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX30_7", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX29_7", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_FAN4_7", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX8_7", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_LOGIC_OUTS_B23_7", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX35_7", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_BYP3_7", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B0_7", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_LOGIC_OUTS_B1_7", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX1_7", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX9_7", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX21_7", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX10_7", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B12_7", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_LOGIC_OUTS_B15_7", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_BYP7_7", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX40_7", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX28_7", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_FAN1_7", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B6_7", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_BYP1_7", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX22_7", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B13_7", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B19_7", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B4_7", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_IMUX34_7", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX18_7", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_LOGIC_OUTS_B16_7", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B9_7", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX16_7", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX0_7", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX32_7", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_CTRL1_7", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_FAN5_7", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_FAN7_7", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX43_7", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_LOGIC_OUTS_B18_7", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX3_7", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_FAN0_7", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX23_7", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX19_7", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX25_7", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX33_7", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_CLK1_7", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX14_7", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_BYP0_7", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_LOGIC_OUTS_B3_7", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX4_7", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX2_7", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX36_7", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX15_7", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_LOGIC_OUTS_B7_7", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_IMUX12_7", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX38_7", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX11_7", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_CLK0_7", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX24_7", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX39_7", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX5_7", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX13_7", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP5_7", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B8_7", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX45_7", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_FAN6_7", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_BYP6_7", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_LOGIC_OUTS_B10_7", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX26_7", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX31_7", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B20_7", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX37_7", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX6_7", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX42_7", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_LOGIC_OUTS_B2_7", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX17_7", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_LOGIC_OUTS_B22_7", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX46_7", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX44_7", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX27_7", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B11_7", + "VBRK_EXT_LOGIC_OUTS_B11" + ] + ], + "tile_types": [ + "GTX_CHANNEL_3", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "CLK_HROW_WW2END0_5", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_WL1END3_5", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_SW4END1_5", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_WW2END2_5", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_WW4B0_5", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_WW4C2_5", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_ER1BEG1_5", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_EE4C2_5", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_WR1END3_5", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_EE4C1_5", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_EE4BEG2_5", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_LH11_5", + "VBRK_LH11" + ], + [ + "CLK_HROW_NW4A0_5", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_WL1END0_5", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_NE4C2_5", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_NW2A0_5", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_NE2A0_5", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_SW2A2_5", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_EE4B0_5", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_SW2A3_5", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_EE4A2_5", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_SW4END0_5", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_WL1END1_5", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_WW4END1_5", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_EL1BEG3_5", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_SE4C3_5", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_WW2END1_5", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_NE4BEG3_5", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_NW2A1_5", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_EE4C0_5", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_NW4A2_5", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_ER1BEG2_5", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_EE2A3_5", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_NE4BEG2_5", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WW4END3_5", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_LH7_5", + "VBRK_LH7" + ], + [ + "CLK_HROW_EE2BEG1_5", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_SW4END2_5", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_EL1BEG1_5", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_NE4C1_5", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_LH2_5", + "VBRK_LH2" + ], + [ + "CLK_HROW_SE4C0_5", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_WW4END0_5", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_NE4C0_5", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_EE4A0_5", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SE2A3_5", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_EE2BEG2_5", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_NW4END3_5", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_WL1END2_5", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_EE4A3_5", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_WW4B2_5", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_WR1END0_5", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_WW4B3_5", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_SE4BEG2_5", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_EE4BEG1_5", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WW4C1_5", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_SE4BEG3_5", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_SE2A1_5", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_LH12_5", + "VBRK_LH12" + ], + [ + "CLK_HROW_SE4C2_5", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_EE4B2_5", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_WW2A1_5", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_NW4END0_5", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW4C0_5", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_ER1BEG0_5", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_EE4C3_5", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_WW2A0_5", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_SW2A0_5", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_LH3_5", + "VBRK_LH3" + ], + [ + "CLK_HROW_WW4END2_5", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_EE2BEG3_5", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_NW4A3_5", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_NW4END1_5", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_WW4B1_5", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_NW2A3_5", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_LH5_5", + "VBRK_LH5" + ], + [ + "CLK_HROW_EE2A1_5", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_NW4A1_5", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_SE2A2_5", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_LH1_5", + "VBRK_LH1" + ], + [ + "CLK_HROW_NW2A2_5", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_SE4C1_5", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_WR1END2_5", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_SW4A2_5", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_WW2A3_5", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_EE4BEG0_5", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_WW2A2_5", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_NE4BEG1_5", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_EE4A1_5", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_WW4C3_5", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_LH4_5", + "VBRK_LH4" + ], + [ + "CLK_HROW_SE4BEG1_5", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_WW4A1_5", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_NE2A3_5", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_WW4A0_5", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_EE2A0_5", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_EE2A2_5", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_NW4END2_5", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_SW4A0_5", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_LH8_5", + "VBRK_LH8" + ], + [ + "CLK_HROW_EE2BEG0_5", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_EE4B3_5", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_WR1END1_5", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_SW4END3_5", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_WW2END3_5", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_NE4C3_5", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_EL1BEG0_5", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_NE4BEG0_5", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_EL1BEG2_5", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WW4A3_5", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_SE2A0_5", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_SW2A1_5", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_LH6_5", + "VBRK_LH6" + ], + [ + "CLK_HROW_NE2A1_5", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_WW4A2_5", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_LH10_5", + "VBRK_LH10" + ], + [ + "CLK_HROW_SW4A1_5", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_NE2A2_5", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_EE4B1_5", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_LH9_5", + "VBRK_LH9" + ], + [ + "CLK_HROW_EE4BEG3_5", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_SE4BEG0_5", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_SW4A3_5", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_ER1BEG3_5", + "VBRK_ER1BEG3" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX15_8", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX45_8", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX12_8", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B4_8", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B2_8", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_FAN2_8", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_LOGIC_OUTS_B0_8", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_BYP5_8", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX39_8", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX40_8", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B9_8", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX16_8", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX0_8", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX13_8", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX14_8", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX10_8", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX20_8", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX38_8", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_FAN5_8", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX46_8", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP6_8", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX2_8", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_LOGIC_OUTS_B10_8", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX5_8", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX19_8", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX41_8", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B15_8", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_LOGIC_OUTS_B7_8", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B20_8", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_FAN6_8", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX23_8", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX44_8", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_LOGIC_OUTS_B6_8", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX28_8", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX22_8", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX47_8", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX21_8", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX1_8", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX27_8", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_FAN0_8", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX9_8", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_BYP7_8", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B8_8", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_FAN1_8", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX18_8", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_BYP3_8", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B11_8", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_LOGIC_OUTS_B22_8", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B23_8", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX8_8", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX4_8", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_CLK1_8", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX24_8", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B1_8", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX7_8", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX31_8", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX6_8", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B18_8", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX32_8", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B16_8", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_FAN7_8", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX30_8", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX34_8", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX26_8", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_LOGIC_OUTS_B21_8", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_CLK0_8", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX17_8", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX35_8", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_LOGIC_OUTS_B13_8", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_BYP4_8", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_LOGIC_OUTS_B19_8", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX11_8", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP0_8", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX36_8", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX25_8", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B3_8", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX29_8", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_CTRL1_8", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX43_8", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_BYP2_8", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX33_8", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_CTRL0_8", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX42_8", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_FAN3_8", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_LOGIC_OUTS_B14_8", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_LOGIC_OUTS_B17_8", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B5_8", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX3_8", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX37_8", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_BYP1_8", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B12_8", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_FAN4_8", + "VBRK_EXT_FAN4" + ] + ], + "tile_types": [ + "GTX_CHANNEL_0", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_PMV2" + ] + }, + { + "grid_deltas": [ + 1, + 6 + ], + "wire_pairs": [ + [ + "CFG_CENTER_CK_IN6", + "HCLK_VFRAME_CK_IN6" + ], + [ + "CFG_CENTER_CK_BUFHCLK3", + "HCLK_VFRAME_CK_BUFHCLK3" + ], + [ + "CFG_CENTER_CK_BUFHCLK11", + "HCLK_VFRAME_CK_BUFHCLK11" + ], + [ + "CFG_CENTER_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFRCLK0" + ], + [ + "CFG_CENTER_CK_IN0", + "HCLK_VFRAME_CK_IN0" + ], + [ + "CFG_CENTER_CK_BUFHCLK8", + "HCLK_VFRAME_CK_BUFHCLK8" + ], + [ + "CFG_CENTER_CK_BUFHCLK0", + "HCLK_VFRAME_CK_BUFHCLK0" + ], + [ + "CFG_CENTER_CK_IN11", + "HCLK_VFRAME_CK_IN11" + ], + [ + "CFG_CENTER_CK_IN8", + "HCLK_VFRAME_CK_IN8" + ], + [ + "CFG_CENTER_CK_BUFRCLK2", + "HCLK_VFRAME_CK_BUFRCLK2" + ], + [ + "CFG_CENTER_CK_IN12", + "HCLK_VFRAME_CK_IN12" + ], + [ + "CFG_CENTER_CK_IN3", + "HCLK_VFRAME_CK_IN3" + ], + [ + "CFG_CENTER_CK_IN7", + "HCLK_VFRAME_CK_IN7" + ], + [ + "CFG_CENTER_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK7" + ], + [ + "CFG_CENTER_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK5" + ], + [ + "CFG_CENTER_CK_BUFHCLK4", + "HCLK_VFRAME_CK_BUFHCLK4" + ], + [ + "CFG_CENTER_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFRCLK1" + ], + [ + "CFG_CENTER_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK3" + ], + [ + "CFG_CENTER_CK_IN2", + "HCLK_VFRAME_CK_IN2" + ], + [ + "CFG_CENTER_CK_IN10", + "HCLK_VFRAME_CK_IN10" + ], + [ + "CFG_CENTER_CK_IN9", + "HCLK_VFRAME_CK_IN9" + ], + [ + "CFG_CENTER_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK10" + ], + [ + "CFG_CENTER_CK_IN13", + "HCLK_VFRAME_CK_IN13" + ], + [ + "CFG_CENTER_CK_BUFHCLK2", + "HCLK_VFRAME_CK_BUFHCLK2" + ], + [ + "CFG_CENTER_CK_BUFHCLK1", + "HCLK_VFRAME_CK_BUFHCLK1" + ], + [ + "CFG_CENTER_CK_IN5", + "HCLK_VFRAME_CK_IN5" + ], + [ + "CFG_CENTER_CK_IN1", + "HCLK_VFRAME_CK_IN1" + ], + [ + "CFG_CENTER_CK_BUFHCLK6", + "HCLK_VFRAME_CK_BUFHCLK6" + ], + [ + "CFG_CENTER_CK_IN4", + "HCLK_VFRAME_CK_IN4" + ], + [ + "CFG_CENTER_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK9" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "HCLK_VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_BRAM_UTURN_IMUX1", + "BRAM_IMUX1_UTURN_2" + ], + [ + "INT_INTERFACE_FAN7", + "BRAM_FAN7_2" + ], + [ + "INT_INTERFACE_WW4B0", + "BRAM_WW4B0_2" + ], + [ + "INT_INTERFACE_SW4A0", + "BRAM_SW4A0_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "BRAM_LOGIC_OUTS_B5_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "BRAM_LOGIC_OUTS_B4_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "BRAM_LOGIC_OUTS_B14_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX45", + "BRAM_IMUX45_2" + ], + [ + "INT_INTERFACE_WR1END0", + "BRAM_WR1END0_2" + ], + [ + "INT_INTERFACE_EE4BEG3", + "BRAM_EE4BEG3_2" + ], + [ + "INT_INTERFACE_LH9", + "BRAM_LH9_2" + ], + [ + "INT_INTERFACE_WR1END3", + "BRAM_WR1END3_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX46", + "BRAM_IMUX46_UTURN_2" + ], + [ + "INT_INTERFACE_WW2END0", + "BRAM_WW2END0_2" + ], + [ + "INT_INTERFACE_SW4A2", + "BRAM_SW4A2_2" + ], + [ + "INT_INTERFACE_EE2A3", + "BRAM_EE2A3_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX18", + "BRAM_IMUX18_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX25", + "BRAM_IMUX25_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX6", + "BRAM_IMUX6_UTURN_2" + ], + [ + "INT_INTERFACE_SW2A1", + "BRAM_SW2A1_2" + ], + [ + "INT_INTERFACE_NE4C3", + "BRAM_NE4C3_2" + ], + [ + "INT_INTERFACE_WW4C1", + "BRAM_WW4C1_2" + ], + [ + "INT_INTERFACE_WW2END1", + "BRAM_WW2END1_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX12", + "BRAM_IMUX12_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX7", + "BRAM_IMUX7_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX4", + "BRAM_IMUX4_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX21", + "BRAM_IMUX21_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX16", + "BRAM_IMUX16_UTURN_2" + ], + [ + "INT_INTERFACE_SE4C2", + "BRAM_SE4C2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX32", + "BRAM_IMUX32_UTURN_2" + ], + [ + "INT_INTERFACE_SW4END3", + "BRAM_SW4END3_2" + ], + [ + "INT_INTERFACE_EE4A1", + "BRAM_EE4A1_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_2" + ], + [ + "INT_INTERFACE_WR1END2", + "BRAM_WR1END2_2" + ], + [ + "INT_INTERFACE_BYP3", + "BRAM_BYP3_2" + ], + [ + "INT_INTERFACE_BYP7", + "BRAM_BYP7_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX37", + "BRAM_IMUX37_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX23", + "BRAM_IMUX23_2" + ], + [ + "INT_INTERFACE_CLK1", + "BRAM_CLK1_2" + ], + [ + "INT_INTERFACE_WW4B3", + "BRAM_WW4B3_2" + ], + [ + "INT_INTERFACE_EE4B1", + "BRAM_EE4B1_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX27", + "BRAM_IMUX27_2" + ], + [ + "INT_INTERFACE_FAN3", + "BRAM_FAN3_2" + ], + [ + "INT_INTERFACE_ER1BEG0", + "BRAM_ER1BEG0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX43", + "BRAM_IMUX43_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX40", + "BRAM_IMUX40_2" + ], + [ + "INT_INTERFACE_EE4C0", + "BRAM_EE4C0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX10", + "BRAM_IMUX10_UTURN_2" + ], + [ + "INT_INTERFACE_MONITOR_N", + "BRAM_MONITOR_N_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_2" + ], + [ + "INT_INTERFACE_SE2A0", + "BRAM_SE2A0_2" + ], + [ + "INT_INTERFACE_EL1BEG0", + "BRAM_EL1BEG0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_2" + ], + [ + "INT_INTERFACE_NE4BEG3", + "BRAM_NE4BEG3_2" + ], + [ + "INT_INTERFACE_CLK0", + "BRAM_CLK0_2" + ], + [ + "INT_INTERFACE_SE2A1", + "BRAM_SE2A1_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX30", + "BRAM_IMUX30_2" + ], + [ + "INT_INTERFACE_MONITOR_P", + "BRAM_MONITOR_P_2" + ], + [ + "INT_INTERFACE_CTRL1", + "BRAM_CTRL1_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_2" + ], + [ + "INT_INTERFACE_EL1BEG2", + "BRAM_EL1BEG2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "BRAM_LOGIC_OUTS_B15_2" + ], + [ + "INT_INTERFACE_FAN1", + "BRAM_FAN1_2" + ], + [ + "INT_INTERFACE_ER1BEG1", + "BRAM_ER1BEG1_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "BRAM_LOGIC_OUTS_B1_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX21", + "BRAM_IMUX21_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX29", + "BRAM_IMUX29_UTURN_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "BRAM_LOGIC_OUTS_B19_2" + ], + [ + "INT_INTERFACE_WW4A0", + "BRAM_WW4A0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX35", + "BRAM_IMUX35_2" + ], + [ + "INT_INTERFACE_BYP2", + "BRAM_BYP2_2" + ], + [ + "INT_INTERFACE_NW4A0", + "BRAM_NW4A0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX26", + "BRAM_IMUX26_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX27", + "BRAM_IMUX27_UTURN_2" + ], + [ + "INT_INTERFACE_WW4A1", + "BRAM_WW4A1_2" + ], + [ + "INT_INTERFACE_SW4A3", + "BRAM_SW4A3_2" + ], + [ + "INT_INTERFACE_SE4BEG1", + "BRAM_SE4BEG1_2" + ], + [ + "INT_INTERFACE_WW4C3", + "BRAM_WW4C3_2" + ], + [ + "INT_INTERFACE_ER1BEG2", + "BRAM_ER1BEG2_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX31", + "BRAM_IMUX31_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX22", + "BRAM_IMUX22_UTURN_2" + ], + [ + "INT_INTERFACE_FAN5", + "BRAM_FAN5_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX11", + "BRAM_IMUX11_UTURN_2" + ], + [ + "INT_INTERFACE_WW4B2", + "BRAM_WW4B2_2" + ], + [ + "INT_INTERFACE_WW2END2", + "BRAM_WW2END2_2" + ], + [ + "INT_INTERFACE_WL1END2", + "BRAM_WL1END2_2" + ], + [ + "INT_INTERFACE_NE4BEG0", + "BRAM_NE4BEG0_2" + ], + [ + "INT_INTERFACE_NE2A3", + "BRAM_NE2A3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX2", + "BRAM_IMUX2_UTURN_2" + ], + [ + "INT_INTERFACE_EE2BEG0", + "BRAM_EE2BEG0_2" + ], + [ + "INT_INTERFACE_SE4C3", + "BRAM_SE4C3_2" + ], + [ + "INT_INTERFACE_SW2A0", + "BRAM_SW2A0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX47", + "BRAM_IMUX47_2" + ], + [ + "INT_INTERFACE_NW4A2", + "BRAM_NW4A2_2" + ], + [ + "INT_INTERFACE_EE2A0", + "BRAM_EE2A0_2" + ], + [ + "INT_INTERFACE_LH10", + "BRAM_LH10_2" + ], + [ + "INT_INTERFACE_LH2", + "BRAM_LH2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "BRAM_LOGIC_OUTS_B6_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "BRAM_LOGIC_OUTS_B0_2" + ], + [ + "INT_INTERFACE_EE2A1", + "BRAM_EE2A1_2" + ], + [ + "INT_INTERFACE_SE4C0", + "BRAM_SE4C0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX33", + "BRAM_IMUX33_UTURN_2" + ], + [ + "INT_INTERFACE_NW4END1", + "BRAM_NW4END1_2" + ], + [ + "INT_INTERFACE_EE4A3", + "BRAM_EE4A3_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX17", + "BRAM_IMUX17_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX8", + "BRAM_IMUX8_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX29", + "BRAM_IMUX29_2" + ], + [ + "INT_INTERFACE_NW4A3", + "BRAM_NW4A3_2" + ], + [ + "INT_INTERFACE_LH1", + "BRAM_LH1_2" + ], + [ + "INT_INTERFACE_EE4C1", + "BRAM_EE4C1_2" + ], + [ + "INT_INTERFACE_BYP1", + "BRAM_BYP1_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX9", + "BRAM_IMUX9_UTURN_2" + ], + [ + "INT_INTERFACE_NE2A1", + "BRAM_NE2A1_2" + ], + [ + "INT_INTERFACE_SW4END1", + "BRAM_SW4END1_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX42", + "BRAM_IMUX42_UTURN_2" + ], + [ + "INT_INTERFACE_WW2A1", + "BRAM_WW2A1_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX47", + "BRAM_IMUX47_UTURN_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "BRAM_LOGIC_OUTS_B13_2" + ], + [ + "INT_INTERFACE_NE4C0", + "BRAM_NE4C0_2" + ], + [ + "INT_INTERFACE_SE4BEG3", + "BRAM_SE4BEG3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX30", + "BRAM_IMUX30_UTURN_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "BRAM_LOGIC_OUTS_B20_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX20", + "BRAM_IMUX20_UTURN_2" + ], + [ + "INT_INTERFACE_NE2A2", + "BRAM_NE2A2_2" + ], + [ + "INT_INTERFACE_BYP5", + "BRAM_BYP5_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "BRAM_LOGIC_OUTS_B11_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX28", + "BRAM_IMUX28_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "BRAM_LOGIC_OUTS_B16_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX36", + "BRAM_IMUX36_2" + ], + [ + "INT_INTERFACE_LH12", + "BRAM_LH12_2" + ], + [ + "INT_INTERFACE_EL1BEG3", + "BRAM_EL1BEG3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX25", + "BRAM_IMUX25_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "BRAM_LOGIC_OUTS_B9_2" + ], + [ + "INT_INTERFACE_SW2A2", + "BRAM_SW2A2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX13", + "BRAM_IMUX13_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_2" + ], + [ + "INT_INTERFACE_SE4BEG2", + "BRAM_SE4BEG2_2" + ], + [ + "INT_INTERFACE_SW2A3", + "BRAM_SW2A3_2" + ], + [ + "INT_INTERFACE_NW2A1", + "BRAM_NW2A1_2" + ], + [ + "INT_INTERFACE_SE4BEG0", + "BRAM_SE4BEG0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_2" + ], + [ + "INT_INTERFACE_SW4END0", + "BRAM_SW4END0_2" + ], + [ + "INT_INTERFACE_NE4C1", + "BRAM_NE4C1_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX42", + "BRAM_IMUX42_2" + ], + [ + "INT_INTERFACE_EE4B3", + "BRAM_EE4B3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX34", + "BRAM_IMUX34_2" + ], + [ + "INT_INTERFACE_LH4", + "BRAM_LH4_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX44", + "BRAM_IMUX44_UTURN_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "BRAM_LOGIC_OUTS_B8_2" + ], + [ + "INT_INTERFACE_EE4B0", + "BRAM_EE4B0_2" + ], + [ + "INT_INTERFACE_EE2BEG1", + "BRAM_EE2BEG1_2" + ], + [ + "INT_INTERFACE_BYP0", + "BRAM_BYP0_2" + ], + [ + "INT_INTERFACE_SE4C1", + "BRAM_SE4C1_2" + ], + [ + "INT_INTERFACE_NW2A3", + "BRAM_NW2A3_2" + ], + [ + "INT_INTERFACE_EE4A2", + "BRAM_EE4A2_2" + ], + [ + "INT_INTERFACE_NW2A0", + "BRAM_NW2A0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX41", + "BRAM_IMUX41_UTURN_2" + ], + [ + "INT_INTERFACE_EE2BEG2", + "BRAM_EE2BEG2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX43", + "BRAM_IMUX43_UTURN_2" + ], + [ + "INT_INTERFACE_NW4A1", + "BRAM_NW4A1_2" + ], + [ + "INT_INTERFACE_WW4C0", + "BRAM_WW4C0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX26", + "BRAM_IMUX26_2" + ], + [ + "INT_INTERFACE_NE4BEG2", + "BRAM_NE4BEG2_2" + ], + [ + "INT_INTERFACE_WW2A3", + "BRAM_WW2A3_2" + ], + [ + "INT_INTERFACE_FAN6", + "BRAM_FAN6_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX15", + "BRAM_IMUX15_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX24", + "BRAM_IMUX24_UTURN_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "BRAM_LOGIC_OUTS_B10_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX3", + "BRAM_IMUX3_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX0", + "BRAM_IMUX0_UTURN_2" + ], + [ + "INT_INTERFACE_EE4C2", + "BRAM_EE4C2_2" + ], + [ + "INT_INTERFACE_NE4BEG1", + "BRAM_NE4BEG1_2" + ], + [ + "INT_INTERFACE_NW4END2", + "BRAM_NW4END2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX40", + "BRAM_IMUX40_UTURN_2" + ], + [ + "INT_INTERFACE_WL1END0", + "BRAM_WL1END0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX14", + "BRAM_IMUX14_UTURN_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "BRAM_LOGIC_OUTS_B7_2" + ], + [ + "INT_INTERFACE_EE4BEG1", + "BRAM_EE4BEG1_2" + ], + [ + "INT_INTERFACE_FAN2", + "BRAM_FAN2_2" + ], + [ + "INT_INTERFACE_SW4A1", + "BRAM_SW4A1_2" + ], + [ + "INT_INTERFACE_WW4END1", + "BRAM_WW4END1_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX34", + "BRAM_IMUX34_UTURN_2" + ], + [ + "INT_INTERFACE_LH6", + "BRAM_LH6_2" + ], + [ + "INT_INTERFACE_WW4END0", + "BRAM_WW4END0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX37", + "BRAM_IMUX37_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "BRAM_LOGIC_OUTS_B22_2" + ], + [ + "INT_INTERFACE_BYP4", + "BRAM_BYP4_2" + ], + [ + "INT_INTERFACE_SE2A3", + "BRAM_SE2A3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_2" + ], + [ + "INT_INTERFACE_EE4A0", + "BRAM_EE4A0_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_2" + ], + [ + "INT_INTERFACE_FAN4", + "BRAM_FAN4_2" + ], + [ + "INT_INTERFACE_WW2END3", + "BRAM_WW2END3_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX31", + "BRAM_IMUX31_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX45", + "BRAM_IMUX45_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX46", + "BRAM_IMUX46_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX39", + "BRAM_IMUX39_2" + ], + [ + "INT_INTERFACE_NE2A0", + "BRAM_NE2A0_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "BRAM_LOGIC_OUTS_B2_2" + ], + [ + "INT_INTERFACE_EE4B2", + "BRAM_EE4B2_2" + ], + [ + "INT_INTERFACE_LH11", + "BRAM_LH11_2" + ], + [ + "INT_INTERFACE_EE4BEG2", + "BRAM_EE4BEG2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "BRAM_LOGIC_OUTS_B21_2" + ], + [ + "INT_INTERFACE_NE4C2", + "BRAM_NE4C2_2" + ], + [ + "INT_INTERFACE_WL1END1", + "BRAM_WL1END1_2" + ], + [ + "INT_INTERFACE_ER1BEG3", + "BRAM_ER1BEG3_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX28", + "BRAM_IMUX28_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_2" + ], + [ + "INT_INTERFACE_WW4A2", + "BRAM_WW4A2_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX38", + "BRAM_IMUX38_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_2" + ], + [ + "INT_INTERFACE_BYP6", + "BRAM_BYP6_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "BRAM_LOGIC_OUTS_B18_2" + ], + [ + "INT_INTERFACE_EE4C3", + "BRAM_EE4C3_2" + ], + [ + "INT_INTERFACE_SE2A2", + "BRAM_SE2A2_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "BRAM_LOGIC_OUTS_B3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "BRAM_LOGIC_OUTS_B12_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "BRAM_LOGIC_OUTS_B17_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX44", + "BRAM_IMUX44_2" + ], + [ + "INT_INTERFACE_LH5", + "BRAM_LH5_2" + ], + [ + "INT_INTERFACE_WW4END3", + "BRAM_WW4END3_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX23", + "BRAM_IMUX23_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX5", + "BRAM_IMUX5_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX41", + "BRAM_IMUX41_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX32", + "BRAM_IMUX32_2" + ], + [ + "INT_INTERFACE_EE2BEG3", + "BRAM_EE2BEG3_2" + ], + [ + "INT_INTERFACE_WW4C2", + "BRAM_WW4C2_2" + ], + [ + "INT_INTERFACE_FAN0", + "BRAM_FAN0_2" + ], + [ + "INT_INTERFACE_WL1END3", + "BRAM_WL1END3_2" + ], + [ + "INT_INTERFACE_WW2A2", + "BRAM_WW2A2_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX22", + "BRAM_IMUX22_2" + ], + [ + "INT_INTERFACE_SW4END2", + "BRAM_SW4END2_2" + ], + [ + "INT_INTERFACE_WW4A3", + "BRAM_WW4A3_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX24", + "BRAM_IMUX24_2" + ], + [ + "INT_INTERFACE_CTRL0", + "BRAM_CTRL0_2" + ], + [ + "INT_INTERFACE_WW4B1", + "BRAM_WW4B1_2" + ], + [ + "INT_INTERFACE_NW2A2", + "BRAM_NW2A2_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX36", + "BRAM_IMUX36_UTURN_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX19", + "BRAM_IMUX19_UTURN_2" + ], + [ + "INT_INTERFACE_LH3", + "BRAM_LH3_2" + ], + [ + "INT_INTERFACE_LH8", + "BRAM_LH8_2" + ], + [ + "INT_INTERFACE_EE4BEG0", + "BRAM_EE4BEG0_2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "BRAM_LOGIC_OUTS_B23_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX35", + "BRAM_IMUX35_UTURN_2" + ], + [ + "INT_INTERFACE_EE2A2", + "BRAM_EE2A2_2" + ], + [ + "INT_INTERFACE_WR1END1", + "BRAM_WR1END1_2" + ], + [ + "INT_INTERFACE_WW4END2", + "BRAM_WW4END2_2" + ], + [ + "INT_INTERFACE_WW2A0", + "BRAM_WW2A0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX38", + "BRAM_IMUX38_UTURN_2" + ], + [ + "INT_INTERFACE_NW4END0", + "BRAM_NW4END0_2" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX39", + "BRAM_IMUX39_UTURN_2" + ], + [ + "INT_INTERFACE_EL1BEG1", + "BRAM_EL1BEG1_2" + ], + [ + "INT_INTERFACE_LH7", + "BRAM_LH7_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_2" + ], + [ + "INT_INTERFACE_BRAM_IMUX33", + "BRAM_IMUX33_2" + ], + [ + "INT_INTERFACE_NW4END3", + "BRAM_NW4END3_2" + ] + ], + "tile_types": [ + "BRAM_INT_INTERFACE_L", + "BRAM_L" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW4C0_6", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4END2_6", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW2A3_6", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4BEG0_6", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_6", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_6", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A3_6", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4A1_6", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4B0_6", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SW4A3_6", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_NE4BEG2_6", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE4B0_6", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE4C1_6", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A1_6", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END1_6", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_6", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_6", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_6", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C1_6", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW4A1_6", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_ER1BEG0_6", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_6", + "VBRK_LH1" + ], + [ + "CMT_TOP_EE4BEG2_6", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG2_6", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SE2A0_6", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WL1END2_6", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A1_6", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WR1END3_6", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NE2A2_6", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_LH4_6", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END1_6", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH8_6", + "VBRK_LH8" + ], + [ + "CMT_TOP_SE4BEG2_6", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4END2_6", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH6_6", + "VBRK_LH6" + ], + [ + "CMT_TOP_MONITOR_N_6", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_LH3_6", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C2_6", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NE2A3_6", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE4C3_6", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4A0_6", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C3_6", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_ER1BEG3_6", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_6", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WR1END2_6", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END0_6", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4C0_6", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SE4C0_6", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SE2A3_6", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW2END1_6", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH2_6", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW2END3_6", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE2A0_6", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NE4C0_6", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WW4C3_6", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END1_6", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4BEG3_6", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A1_6", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4B3_6", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4B1_6", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A1_6", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WL1END3_6", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH7_6", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW2A0_6", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A0_6", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NW2A1_6", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2BEG0_6", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_6", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE2BEG1_6", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4END3_6", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NW4END3_6", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4BEG1_6", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_6", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_SW4END2_6", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NW4A3_6", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4BEG0_6", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SW4A2_6", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4C1_6", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2A0_6", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4END0_6", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_ER1BEG2_6", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2A3_6", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW2A0_6", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_LH11_6", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE2BEG3_6", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH9_6", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4A3_6", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4A0_6", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE2A0_6", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NW2A2_6", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_6", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C3_6", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4A1_6", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WR1END0_6", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4C2_6", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_MONITOR_P_6", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_EE4C1_6", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG3_6", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW4B3_6", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END2_6", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A2_6", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4B2_6", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW4A0_6", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW2A1_6", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH5_6", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4B1_6", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_NE4BEG1_6", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH10_6", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_6", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4A2_6", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG1_6", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE2A1_6", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C2_6", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END0_6", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SE4BEG0_6", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_6", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE4A2_6", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4END0_6", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4BEG3_6", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A3_6", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_6", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_6", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A2_6", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NW2A3_6", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_6", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE4C2_6", + "VBRK_SE4C2" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "CMT_TOP_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH6_3", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_LH1_3", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_LH12_3", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_LH7_3", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_3", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH3_3", + "VBRK_LH3" + ], + [ + "CMT_TOP_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_LH2_3", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_LH9_3", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH5_3", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH11_3", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_LH10_3", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH8_3", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EL1BEG1_3", + "VBRK_EL1BEG1" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "wire_pairs": [ + [ + "IOI_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2_1" + ], + [ + "IOI_IMUX_RC0", + "IOI_IMUX_RC2" + ], + [ + "IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_LEAF_GCLK3" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_LEAF_GCLK1" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_LEAF_GCLK0" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_RCLK_FORIO1" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_RCLK_FORIO0" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_RCLK_FORIO3" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_LEAF_GCLK5" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_RCLK_FORIO2" + ], + [ + "IOI_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3_1" + ], + [ + "IOI_TBYTEIN", + "IOI_TBYTEIN_TERM" + ], + [ + "IOI_IMUX_RC1", + "IOI_IMUX_RC3" + ], + [ + "IOI_RCLK_DIV_CLR1_1", + "IOI_RCLK_DIV_CLR1" + ], + [ + "IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "IOI_RCLK_DIV_CLR0_1", + "IOI_RCLK_DIV_CLR0" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_LEAF_GCLK4" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_LEAF_GCLK2" + ] + ], + "tile_types": [ + "LIOI3", + "LIOI3_TBYTETERM" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "DSP_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "DSP_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "DSP_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "DSP_LH3_4", + "VBRK_LH3" + ], + [ + "DSP_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "DSP_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "DSP_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "DSP_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "DSP_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "DSP_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "DSP_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "DSP_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "DSP_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "DSP_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "DSP_LH6_4", + "VBRK_LH6" + ], + [ + "DSP_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "DSP_LH8_4", + "VBRK_LH8" + ], + [ + "DSP_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "DSP_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "DSP_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "DSP_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "DSP_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "DSP_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "DSP_LH1_4", + "VBRK_LH1" + ], + [ + "DSP_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "DSP_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "DSP_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "DSP_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "DSP_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "DSP_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "DSP_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "DSP_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "DSP_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "DSP_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "DSP_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "DSP_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "DSP_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "DSP_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "DSP_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "DSP_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "DSP_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "DSP_LH2_4", + "VBRK_LH2" + ], + [ + "DSP_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "DSP_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "DSP_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "DSP_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "DSP_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "DSP_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "DSP_LH10_4", + "VBRK_LH10" + ], + [ + "DSP_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "DSP_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "DSP_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "DSP_LH5_4", + "VBRK_LH5" + ], + [ + "DSP_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "DSP_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "DSP_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "DSP_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "DSP_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "DSP_LH4_4", + "VBRK_LH4" + ], + [ + "DSP_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "DSP_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "DSP_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "DSP_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "DSP_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "DSP_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "DSP_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "DSP_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "DSP_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "DSP_LH9_4", + "VBRK_LH9" + ], + [ + "DSP_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "DSP_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "DSP_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "DSP_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "DSP_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "DSP_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "DSP_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "DSP_MONITOR_N_4", + "VBRK_MONITOR_N" + ], + [ + "DSP_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "DSP_LH7_4", + "VBRK_LH7" + ], + [ + "DSP_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "DSP_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "DSP_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "DSP_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "DSP_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "DSP_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "DSP_LH11_4", + "VBRK_LH11" + ], + [ + "DSP_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "DSP_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "DSP_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "DSP_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "DSP_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "DSP_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "DSP_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "DSP_MONITOR_P_4", + "VBRK_MONITOR_P" + ], + [ + "DSP_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "DSP_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "DSP_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "DSP_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "DSP_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "DSP_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "DSP_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "DSP_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "DSP_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "DSP_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "DSP_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "DSP_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "DSP_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "DSP_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "DSP_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "DSP_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "DSP_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "DSP_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "DSP_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "DSP_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "DSP_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "DSP_LH12_4", + "VBRK_LH12" + ], + [ + "DSP_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "DSP_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "DSP_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "DSP_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "DSP_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "DSP_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "DSP_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "DSP_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "DSP_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "DSP_SW4A2_4", + "VBRK_SW4A2" + ] + ], + "tile_types": [ + "DSP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_0" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_0" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_0" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_0" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_0" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_0" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_0" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_0" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_0" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_0" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_0" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_0" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_0" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_0" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_0" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_0" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_0" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_0" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_0" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_0" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_0" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_0" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_0" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_0" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_0" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_0" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_0" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_0" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_0" + ], + [ + "INT_FEEDTHRU_2_MONITOR_N", + "MONITOR_HORIZ_VAUXN8" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_0" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_0" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_0" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_0" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_0" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_0" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_0" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_0" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_0" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_0" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_0" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_0" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_0" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_0" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_0" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_0" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_0" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_0" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_0" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_0" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_0" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_0" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_0" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_0" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_0" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_0" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_0" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_0" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_0" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_0" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_0" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_0" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_0" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_0" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_0" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_0" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_0" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_0" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_0" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_0" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_0" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_0" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_0" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_0" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_0" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_0" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_0" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_0" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_0" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_0" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_0" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_0" + ], + [ + "INT_FEEDTHRU_2_MONITOR_P", + "MONITOR_HORIZ_VAUXP8" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_0" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_0" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_0" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_0" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_0" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_0" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_0" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_0" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_0" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_0" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_0" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_0" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_0" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_0" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_0" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_0" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_0" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_0" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_0" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_0" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_0" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_0" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_0" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_0" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_0" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_0" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_0" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_0" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_0" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_0" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_0" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_0" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_0" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_0" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_0" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_0" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_0" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_0" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_0" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_0" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_0" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_0" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_0" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_TOP_FUJI2" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "DSP_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "DSP_LH11_2", + "VBRK_LH11" + ], + [ + "DSP_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "DSP_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "DSP_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "DSP_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "DSP_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "DSP_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "DSP_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "DSP_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "DSP_LH4_2", + "VBRK_LH4" + ], + [ + "DSP_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "DSP_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "DSP_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "DSP_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "DSP_LH8_2", + "VBRK_LH8" + ], + [ + "DSP_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "DSP_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "DSP_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "DSP_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "DSP_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "DSP_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "DSP_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "DSP_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "DSP_MONITOR_N_2", + "VBRK_MONITOR_N" + ], + [ + "DSP_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "DSP_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "DSP_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "DSP_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "DSP_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "DSP_LH2_2", + "VBRK_LH2" + ], + [ + "DSP_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "DSP_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "DSP_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "DSP_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "DSP_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "DSP_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "DSP_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "DSP_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "DSP_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "DSP_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "DSP_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "DSP_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "DSP_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "DSP_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "DSP_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "DSP_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "DSP_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "DSP_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "DSP_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "DSP_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "DSP_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "DSP_LH6_2", + "VBRK_LH6" + ], + [ + "DSP_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "DSP_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "DSP_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "DSP_LH5_2", + "VBRK_LH5" + ], + [ + "DSP_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "DSP_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "DSP_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "DSP_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "DSP_LH3_2", + "VBRK_LH3" + ], + [ + "DSP_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "DSP_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "DSP_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "DSP_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "DSP_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "DSP_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "DSP_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "DSP_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "DSP_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "DSP_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "DSP_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "DSP_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "DSP_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "DSP_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "DSP_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "DSP_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "DSP_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "DSP_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "DSP_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "DSP_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "DSP_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "DSP_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "DSP_LH7_2", + "VBRK_LH7" + ], + [ + "DSP_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "DSP_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "DSP_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "DSP_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "DSP_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "DSP_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "DSP_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "DSP_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "DSP_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "DSP_MONITOR_P_2", + "VBRK_MONITOR_P" + ], + [ + "DSP_EE4B3_2", + "VBRK_EE4B3" + ], + [ + "DSP_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "DSP_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "DSP_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "DSP_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "DSP_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "DSP_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "DSP_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "DSP_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "DSP_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "DSP_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "DSP_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "DSP_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "DSP_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "DSP_NW2A2_2", + "VBRK_NW2A2" + ], + [ + "DSP_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "DSP_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "DSP_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "DSP_LH1_2", + "VBRK_LH1" + ], + [ + "DSP_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "DSP_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "DSP_LH9_2", + "VBRK_LH9" + ], + [ + "DSP_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "DSP_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "DSP_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "DSP_LH10_2", + "VBRK_LH10" + ], + [ + "DSP_LH12_2", + "VBRK_LH12" + ], + [ + "DSP_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "DSP_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "DSP_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "DSP_NE4BEG0_2", + "VBRK_NE4BEG0" + ] + ], + "tile_types": [ + "DSP_L", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "PCIE_IMUX38_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_EL1BEG1_10", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_IMUX36_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_SW4END3_10", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_WW2A2_10", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_10", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_SE4C1_10", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_NE4C3_10", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_SW2A2_10", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_IMUX34_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_SE4BEG3_10", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_SE2A0_10", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_WW2A3_10", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_WL1END0_10", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_NW2A1_10", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_10", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_EE4A2_10", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_SW4A1_10", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_WW2A0_10", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_CTRL0_R_10", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_IMUX30_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_NE2A0_10", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_BYP6_R_10", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_SE4BEG2_10", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_WW2A1_10", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_EE4C1_10", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_BYP1_R_10", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_EE4BEG1_10", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_NW2A2_10", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_WW4END1_10", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_ER1BEG0_10", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_EE4B1_10", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_LH6_10", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_IMUX21_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_EE4B2_10", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_LH10_10", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_IMUX47_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_NW4A3_10", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_LH11_10", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_EE4B3_10", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_IMUX40_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_10", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_EL1BEG3_10", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_IMUX6_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_CTRL1_R_10", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_SW2A1_10", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_WW4A0_10", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_IMUX5_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_IMUX45_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_LH1_10", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_10", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_NW4A1_10", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_10", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_SW4A2_10", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_SE2A3_10", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_SE2A1_10", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_FAN4_R_10", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_EL1BEG2_10", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_IMUX35_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_WR1END2_10", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_LH4_10", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_WW4C1_10", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_EE2A0_10", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_EE2A3_10", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_NE4BEG0_10", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_EE2A1_10", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_BYP3_R_10", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_IMUX29_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_NE4BEG1_10", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_SW4END2_10", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_FAN5_R_10", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_FAN2_R_10", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_IMUX33_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_WL1END2_10", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_WW4END2_10", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_LH9_10", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_EE2BEG3_10", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_10", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_FAN3_R_10", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_WW4A3_10", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_NW2A3_10", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_EE2BEG0_10", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_EE4A0_10", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_EE4C3_10", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_IMUX37_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_WL1END3_10", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_IMUX22_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_SE4C0_10", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_10", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_10", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_IMUX3_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_FAN6_R_10", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_WW4A2_10", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_NW4A2_10", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_WW2END2_10", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_WW4C0_10", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_10", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_NE2A1_10", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_LH5_10", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_EE2A2_10", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_SW4A3_10", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_NW4END0_10", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_10", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_IMUX42_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_WW4C3_10", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_10", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_CLK0_R_10", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_BYP0_R_10", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_EE4C2_10", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_IMUX17_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_IMUX44_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_NW4END1_10", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_10", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_EE4B0_10", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_SE4BEG0_10", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_EE4C0_10", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_10", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_WW4B2_10", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_WW2END3_10", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_WW4C2_10", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_IMUX14_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_SW2A0_10", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_IMUX16_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_WW4B0_10", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_IMUX11_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_FAN7_R_10", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_10", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_EE2BEG2_10", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_IMUX10_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_NE4C2_10", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_IMUX19_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_IMUX24_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_SE4BEG1_10", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_IMUX8_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_NW4END3_10", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_10", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_SW2A3_10", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_WW2END0_10", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_SE2A2_10", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_10", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_LH2_10", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_WL1END1_10", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_WW4B1_10", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_NE4C1_10", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_IMUX23_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_IMUX0_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_NW4A0_10", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WW4B3_10", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_EE4BEG2_10", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX41_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_IMUX32_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_ER1BEG2_10", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_EE4BEG3_10", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_SW4END0_10", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_FAN1_R_10", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_IMUX1_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_IMUX18_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_ER1BEG1_10", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_LH12_10", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_EL1BEG0_10", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_10", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_IMUX20_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_WR1END1_10", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_BYP4_R_10", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_IMUX25_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_SE4C2_10", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_NE4BEG3_10", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_IMUX27_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_LH8_10", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_IMUX39_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_IMUX28_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_IMUX26_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_IMUX13_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_10", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_NE2A2_10", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_NW4END2_10", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_10", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_BYP7_R_10", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_SW4END1_10", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_WW4END0_10", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_IMUX7_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_10", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_IMUX9_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_10", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_WW2END1_10", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_EE4A1_10", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_WW4A1_10", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_IMUX12_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_FAN0_R_10", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_LH7_10", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_IMUX2_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_NW2A0_10", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_BYP2_R_10", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_IMUX46_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_WR1END0_10", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_BYP5_R_10", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_ER1BEG3_10", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_NE2A3_10", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_IMUX31_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_10", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_LH3_10", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_10", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_CLK1_R_10", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_NE4BEG2_10", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_IMUX15_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_NE4C0_10", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_IMUX43_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_EE4BEG0_10", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_EE4A3_10", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_WW4END3_10", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_10", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_SW4A0_10", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_WR1END3_10", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_EE2BEG1_10", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_IMUX4_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_SE4C3_10", + "INT_INTERFACE_SE4C3" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CMT_FIFO_WW4B0_3", + "CMT_TOP_WW4B0_4" + ], + [ + "CMT_FIFO_ER1BEG2_7", + "CMT_TOP_ER1BEG2_8" + ], + [ + "CMT_FIFO_L_IMUX36_7", + "CMT_TOP_IMUX36_8" + ], + [ + "CMT_FIFO_EL1BEG0_0", + "CMT_TOP_EL1BEG0_1" + ], + [ + "CMT_FIFO_SE4BEG2_0", + "CMT_TOP_SE4BEG2_1" + ], + [ + "CMT_FIFO_L_CTRL1_3", + "CMT_TOP_CTRL1_4" + ], + [ + "CMT_FIFO_EE2A0_7", + "CMT_TOP_EE2A0_8" + ], + [ + "CMT_FIFO_L_IMUX3_4", + "CMT_TOP_IMUX3_5" + ], + [ + "CMT_FIFO_L_FAN1_10", + "CMT_TOP_FAN1_11" + ], + [ + "CMT_FIFO_NW4END3_5", + "CMT_TOP_NW4END3_6" + ], + [ + "CMT_FIFO_L_IMUX22_0", + "CMT_TOP_IMUX22_1" + ], + [ + "CMT_FIFO_LH2_0", + "CMT_TOP_LH2_1" + ], + [ + "CMT_FIFO_L_IMUX44_8", + "CMT_TOP_IMUX44_9" + ], + [ + "CMT_FIFO_L_IMUX42_11", + "CMT_TOP_IMUX42_12" + ], + [ + "CMT_FIFO_EE2A0_0", + "CMT_TOP_EE2A0_1" + ], + [ + "CMT_FIFO_LH7_11", + "CMT_TOP_LH7_12" + ], + [ + "CMT_FIFO_SW4A3_10", + "CMT_TOP_SW4A3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_1", + "CMT_TOP_LOGIC_OUTS_L_B5_2" + ], + [ + "CMT_FIFO_WW4A3_1", + "CMT_TOP_WW4A3_2" + ], + [ + "CMT_FIFO_WR1END2_0", + "CMT_TOP_WR1END2_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "CMT_TOP_ICLKDIV_3" + ], + [ + "CMT_FIFO_EE2BEG2_4", + "CMT_TOP_EE2BEG2_5" + ], + [ + "CMT_FIFO_WW2END0_6", + "CMT_TOP_WW2END0_7" + ], + [ + "CMT_FIFO_SE2A3_3", + "CMT_TOP_SE2A3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_1", + "CMT_TOP_LOGIC_OUTS_L_B0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_2", + "CMT_TOP_LOGIC_OUTS_L_B22_3" + ], + [ + "CMT_FIFO_SW4END2_7", + "CMT_TOP_SW4END2_8" + ], + [ + "CMT_FIFO_MONITOR_N_4", + "CMT_TOP_MONITOR_N_5" + ], + [ + "CMT_FIFO_SE2A3_7", + "CMT_TOP_SE2A3_8" + ], + [ + "CMT_FIFO_NW2A0_7", + "CMT_TOP_NW2A0_8" + ], + [ + "CMT_FIFO_L_IMUX6_4", + "CMT_TOP_IMUX6_5" + ], + [ + "CMT_FIFO_LH3_5", + "CMT_TOP_LH3_6" + ], + [ + "CMT_FIFO_L_CTRL0_10", + "CMT_TOP_CTRL0_11" + ], + [ + "CMT_FIFO_SW4END1_1", + "CMT_TOP_SW4END1_2" + ], + [ + "CMT_FIFO_L_CTRL0_5", + "CMT_TOP_CTRL0_6" + ], + [ + "CMT_FIFO_WW2A3_4", + "CMT_TOP_WW2A3_5" + ], + [ + "CMT_FIFO_L_IMUX37_5", + "CMT_TOP_IMUX37_6" + ], + [ + "CMT_FIFO_NW2A2_4", + "CMT_TOP_NW2A2_5" + ], + [ + "CMT_FIFO_L_IMUX45_4", + "CMT_TOP_IMUX45_5" + ], + [ + "CMT_FIFO_LH7_0", + "CMT_TOP_LH7_1" + ], + [ + "CMT_FIFO_LH9_1", + "CMT_TOP_LH9_2" + ], + [ + "CMT_FIFO_SW4END1_3", + "CMT_TOP_SW4END1_4" + ], + [ + "CMT_FIFO_EL1BEG1_2", + "CMT_TOP_EL1BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX38_11", + "CMT_TOP_IMUX38_12" + ], + [ + "CMT_FIFO_SE2A0_9", + "CMT_TOP_SE2A0_10" + ], + [ + "CMT_FIFO_EE4C0_5", + "CMT_TOP_EE4C0_6" + ], + [ + "CMT_FIFO_WW4A2_8", + "CMT_TOP_WW4A2_9" + ], + [ + "CMT_FIFO_WW4C3_0", + "CMT_TOP_WW4C3_1" + ], + [ + "CMT_FIFO_LH12_10", + "CMT_TOP_LH12_11" + ], + [ + "CMT_FIFO_L_IMUX15_1", + "CMT_TOP_IMUX15_2" + ], + [ + "CMT_FIFO_EL1BEG1_11", + "CMT_TOP_EL1BEG1_12" + ], + [ + "CMT_FIFO_L_IMUX46_4", + "CMT_TOP_IMUX46_5" + ], + [ + "CMT_FIFO_NW4A1_11", + "CMT_TOP_NW4A1_12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "CMT_TOP_OCLK_6" + ], + [ + "CMT_FIFO_LH11_7", + "CMT_TOP_LH11_8" + ], + [ + "CMT_FIFO_L_FAN6_3", + "CMT_TOP_FAN6_4" + ], + [ + "CMT_FIFO_EE4BEG0_7", + "CMT_TOP_EE4BEG0_8" + ], + [ + "CMT_FIFO_SE4C2_2", + "CMT_TOP_SE4C2_3" + ], + [ + "CMT_FIFO_EE4BEG0_9", + "CMT_TOP_EE4BEG0_10" + ], + [ + "CMT_FIFO_NE2A0_8", + "CMT_TOP_NE2A0_9" + ], + [ + "CMT_FIFO_L_IMUX5_6", + "CMT_TOP_IMUX5_7" + ], + [ + "CMT_FIFO_L_IMUX9_10", + "CMT_TOP_IMUX9_11" + ], + [ + "CMT_FIFO_L_IMUX2_3", + "CMT_TOP_IMUX2_4" + ], + [ + "CMT_FIFO_L_IMUX42_1", + "CMT_TOP_IMUX42_2" + ], + [ + "CMT_FIFO_WW2A0_9", + "CMT_TOP_WW2A0_10" + ], + [ + "CMT_FIFO_SE2A1_1", + "CMT_TOP_SE2A1_2" + ], + [ + "CMT_FIFO_WL1END2_4", + "CMT_TOP_WL1END2_5" + ], + [ + "CMT_FIFO_MONITOR_P_10", + "CMT_TOP_MONITOR_P_11" + ], + [ + "CMT_FIFO_WW4A3_0", + "CMT_TOP_WW4A3_1" + ], + [ + "CMT_FIFO_WL1END2_5", + "CMT_TOP_WL1END2_6" + ], + [ + "CMT_FIFO_L_IMUX3_0", + "CMT_TOP_IMUX3_1" + ], + [ + "CMT_FIFO_EE2A3_6", + "CMT_TOP_EE2A3_7" + ], + [ + "CMT_FIFO_L_FAN0_2", + "CMT_TOP_FAN0_3" + ], + [ + "CMT_FIFO_WW4C2_11", + "CMT_TOP_WW4C2_12" + ], + [ + "CMT_FIFO_NE4BEG1_9", + "CMT_TOP_NE4BEG1_10" + ], + [ + "CMT_FIFO_WW4A1_11", + "CMT_TOP_WW4A1_12" + ], + [ + "CMT_FIFO_EE4BEG1_6", + "CMT_TOP_EE4BEG1_7" + ], + [ + "CMT_FIFO_SE4C0_3", + "CMT_TOP_SE4C0_4" + ], + [ + "CMT_FIFO_L_IMUX31_4", + "CMT_TOP_IMUX31_5" + ], + [ + "CMT_FIFO_EE4BEG3_11", + "CMT_TOP_EE4BEG3_12" + ], + [ + "CMT_FIFO_NE4C2_2", + "CMT_TOP_NE4C2_3" + ], + [ + "CMT_FIFO_EE2A0_2", + "CMT_TOP_EE2A0_3" + ], + [ + "CMT_FIFO_L_IMUX8_1", + "CMT_TOP_IMUX8_2" + ], + [ + "CMT_FIFO_L_IMUX47_8", + "CMT_TOP_IMUX47_9" + ], + [ + "CMT_FIFO_WW2A0_3", + "CMT_TOP_WW2A0_4" + ], + [ + "CMT_FIFO_WW4C1_11", + "CMT_TOP_WW4C1_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_4", + "CMT_TOP_LOGIC_OUTS_L_B21_5" + ], + [ + "CMT_FIFO_L_IMUX14_6", + "CMT_TOP_IMUX14_7" + ], + [ + "CMT_FIFO_WR1END3_4", + "CMT_TOP_WR1END3_5" + ], + [ + "CMT_FIFO_SW2A3_4", + "CMT_TOP_SW2A3_5" + ], + [ + "CMT_FIFO_EE2A3_11", + "CMT_TOP_EE2A3_12" + ], + [ + "CMT_FIFO_SW4END2_2", + "CMT_TOP_SW4END2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_11", + "CMT_TOP_LOGIC_OUTS_L_B20_12" + ], + [ + "CMT_FIFO_L_FAN1_11", + "CMT_TOP_FAN1_12" + ], + [ + "CMT_FIFO_L_IMUX36_9", + "CMT_TOP_IMUX36_10" + ], + [ + "CMT_FIFO_WW4C3_3", + "CMT_TOP_WW4C3_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "CMT_TOP_ICLKDIV_10" + ], + [ + "CMT_FIFO_L_IMUX30_7", + "CMT_TOP_IMUX30_8" + ], + [ + "CMT_FIFO_EE4A3_9", + "CMT_TOP_EE4A3_10" + ], + [ + "CMT_FIFO_L_CLK0_10", + "CMT_TOP_CLK0_11" + ], + [ + "CMT_FIFO_L_IMUX20_1", + "CMT_TOP_IMUX20_2" + ], + [ + "CMT_FIFO_L_IMUX24_11", + "CMT_TOP_IMUX24_12" + ], + [ + "CMT_FIFO_NW4END2_8", + "CMT_TOP_NW4END2_9" + ], + [ + "CMT_FIFO_SW4A2_6", + "CMT_TOP_SW4A2_7" + ], + [ + "CMT_FIFO_WW2END3_3", + "CMT_TOP_WW2END3_4" + ], + [ + "CMT_FIFO_L_IMUX20_4", + "CMT_TOP_IMUX20_5" + ], + [ + "CMT_FIFO_WW4C1_3", + "CMT_TOP_WW4C1_4" + ], + [ + "CMT_FIFO_WW4B0_5", + "CMT_TOP_WW4B0_6" + ], + [ + "CMT_FIFO_L_IMUX28_10", + "CMT_TOP_IMUX28_11" + ], + [ + "CMT_FIFO_WR1END3_7", + "CMT_TOP_WR1END3_8" + ], + [ + "CMT_FIFO_WW4A1_6", + "CMT_TOP_WW4A1_7" + ], + [ + "CMT_FIFO_LH10_7", + "CMT_TOP_LH10_8" + ], + [ + "CMT_FIFO_EE2A2_5", + "CMT_TOP_EE2A2_6" + ], + [ + "CMT_FIFO_L_IMUX19_11", + "CMT_TOP_IMUX19_12" + ], + [ + "CMT_FIFO_L_IMUX3_6", + "CMT_TOP_IMUX3_7" + ], + [ + "CMT_FIFO_NW2A0_1", + "CMT_TOP_NW2A0_2" + ], + [ + "CMT_FIFO_WW4B3_6", + "CMT_TOP_WW4B3_7" + ], + [ + "CMT_FIFO_SW4A2_3", + "CMT_TOP_SW4A2_4" + ], + [ + "CMT_FIFO_NE4C0_5", + "CMT_TOP_NE4C0_6" + ], + [ + "CMT_FIFO_SE2A3_10", + "CMT_TOP_SE2A3_11" + ], + [ + "CMT_FIFO_WL1END3_8", + "CMT_TOP_WL1END3_9" + ], + [ + "CMT_FIFO_EE4BEG3_5", + "CMT_TOP_EE4BEG3_6" + ], + [ + "CMT_FIFO_WL1END0_4", + "CMT_TOP_WL1END0_5" + ], + [ + "CMT_FIFO_L_CLK1_8", + "CMT_TOP_CLK1_9" + ], + [ + "CMT_FIFO_LH6_0", + "CMT_TOP_LH6_1" + ], + [ + "CMT_FIFO_L_IMUX35_2", + "CMT_TOP_IMUX35_3" + ], + [ + "CMT_FIFO_SW4END0_8", + "CMT_TOP_SW4END0_9" + ], + [ + "CMT_FIFO_SE2A0_6", + "CMT_TOP_SE2A0_7" + ], + [ + "CMT_FIFO_L_IMUX33_0", + "CMT_TOP_IMUX33_1" + ], + [ + "CMT_FIFO_LH12_11", + "CMT_TOP_LH12_12" + ], + [ + "CMT_FIFO_WW2END2_10", + "CMT_TOP_WW2END2_11" + ], + [ + "CMT_FIFO_WR1END1_1", + "CMT_TOP_WR1END1_2" + ], + [ + "CMT_FIFO_WW4END2_1", + "CMT_TOP_WW4END2_2" + ], + [ + "CMT_FIFO_L_BYP3_8", + "CMT_TOP_BYP3_9" + ], + [ + "CMT_FIFO_L_IMUX15_11", + "CMT_TOP_IMUX15_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_2", + "CMT_TOP_LOGIC_OUTS_L_B2_3" + ], + [ + "CMT_FIFO_L_CLK0_1", + "CMT_TOP_CLK0_2" + ], + [ + "CMT_FIFO_WW2END0_3", + "CMT_TOP_WW2END0_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "CMT_TOP_OCLKDIV_2" + ], + [ + "CMT_FIFO_L_IMUX6_9", + "CMT_TOP_IMUX6_10" + ], + [ + "CMT_FIFO_L_IMUX36_2", + "CMT_TOP_IMUX36_3" + ], + [ + "CMT_FIFO_NE4C3_11", + "CMT_TOP_NE4C3_12" + ], + [ + "CMT_FIFO_WW4C2_9", + "CMT_TOP_WW4C2_10" + ], + [ + "CMT_FIFO_SW4END3_2", + "CMT_TOP_SW4END3_3" + ], + [ + "CMT_FIFO_LH7_7", + "CMT_TOP_LH7_8" + ], + [ + "CMT_FIFO_L_IMUX25_8", + "CMT_TOP_IMUX25_9" + ], + [ + "CMT_FIFO_EE2A2_2", + "CMT_TOP_EE2A2_3" + ], + [ + "CMT_FIFO_L_BYP4_6", + "CMT_TOP_BYP4_7" + ], + [ + "CMT_FIFO_SW4END1_10", + "CMT_TOP_SW4END1_11" + ], + [ + "CMT_FIFO_SE2A2_7", + "CMT_TOP_SE2A2_8" + ], + [ + "CMT_FIFO_WW4B2_4", + "CMT_TOP_WW4B2_5" + ], + [ + "CMT_FIFO_L_IMUX27_2", + "CMT_TOP_IMUX27_3" + ], + [ + "CMT_FIFO_NE4C1_5", + "CMT_TOP_NE4C1_6" + ], + [ + "CMT_FIFO_L_IMUX43_1", + "CMT_TOP_IMUX43_2" + ], + [ + "CMT_FIFO_LH4_4", + "CMT_TOP_LH4_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "CMT_TOP_ICLKDIV_11" + ], + [ + "CMT_FIFO_EE4BEG2_7", + "CMT_TOP_EE4BEG2_8" + ], + [ + "CMT_FIFO_L_CTRL0_7", + "CMT_TOP_CTRL0_8" + ], + [ + "CMT_FIFO_NW2A3_0", + "CMT_TOP_NW2A3_1" + ], + [ + "CMT_FIFO_EE4BEG1_8", + "CMT_TOP_EE4BEG1_9" + ], + [ + "CMT_FIFO_NW4A0_0", + "CMT_TOP_NW4A0_1" + ], + [ + "CMT_FIFO_EE2A1_6", + "CMT_TOP_EE2A1_7" + ], + [ + "CMT_FIFO_EE2BEG1_5", + "CMT_TOP_EE2BEG1_6" + ], + [ + "CMT_FIFO_L_IMUX33_7", + "CMT_TOP_IMUX33_8" + ], + [ + "CMT_FIFO_WW2END3_2", + "CMT_TOP_WW2END3_3" + ], + [ + "CMT_FIFO_LH5_7", + "CMT_TOP_LH5_8" + ], + [ + "CMT_FIFO_L_FAN2_9", + "CMT_TOP_FAN2_10" + ], + [ + "CMT_FIFO_NE4BEG2_5", + "CMT_TOP_NE4BEG2_6" + ], + [ + "CMT_FIFO_L_IMUX1_4", + "CMT_TOP_IMUX1_5" + ], + [ + "CMT_FIFO_SE4BEG3_2", + "CMT_TOP_SE4BEG3_3" + ], + [ + "CMT_FIFO_NW4END2_11", + "CMT_TOP_NW4END2_12" + ], + [ + "CMT_FIFO_SW4END0_11", + "CMT_TOP_SW4END0_12" + ], + [ + "CMT_FIFO_L_IMUX38_7", + "CMT_TOP_IMUX38_8" + ], + [ + "CMT_FIFO_WW2END3_8", + "CMT_TOP_WW2END3_9" + ], + [ + "CMT_FIFO_SW4END1_8", + "CMT_TOP_SW4END1_9" + ], + [ + "CMT_FIFO_SW4A1_0", + "CMT_TOP_SW4A1_1" + ], + [ + "CMT_FIFO_NW4END2_9", + "CMT_TOP_NW4END2_10" + ], + [ + "CMT_FIFO_EE2BEG1_11", + "CMT_TOP_EE2BEG1_12" + ], + [ + "CMT_FIFO_L_IMUX37_1", + "CMT_TOP_IMUX37_2" + ], + [ + "CMT_FIFO_SW2A1_9", + "CMT_TOP_SW2A1_10" + ], + [ + "CMT_FIFO_L_IMUX17_9", + "CMT_TOP_IMUX17_10" + ], + [ + "CMT_FIFO_L_IMUX23_8", + "CMT_TOP_IMUX23_9" + ], + [ + "CMT_FIFO_SW4END3_8", + "CMT_TOP_SW4END3_9" + ], + [ + "CMT_FIFO_L_IMUX30_3", + "CMT_TOP_IMUX30_4" + ], + [ + "CMT_FIFO_WW2END2_4", + "CMT_TOP_WW2END2_5" + ], + [ + "CMT_FIFO_LH10_4", + "CMT_TOP_LH10_5" + ], + [ + "CMT_FIFO_L_IMUX23_7", + "CMT_TOP_IMUX23_8" + ], + [ + "CMT_FIFO_L_IMUX9_9", + "CMT_TOP_IMUX9_10" + ], + [ + "CMT_FIFO_SE2A1_3", + "CMT_TOP_SE2A1_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "CMT_TOP_ICLKDIV_8" + ], + [ + "CMT_FIFO_NW2A3_2", + "CMT_TOP_NW2A3_3" + ], + [ + "CMT_FIFO_L_IMUX43_6", + "CMT_TOP_IMUX43_7" + ], + [ + "CMT_FIFO_L_CTRL1_4", + "CMT_TOP_CTRL1_5" + ], + [ + "CMT_FIFO_WW2END2_0", + "CMT_TOP_WW2END2_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_2", + "CMT_TOP_LOGIC_OUTS_L_B8_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_6", + "CMT_TOP_LOGIC_OUTS_L_B23_7" + ], + [ + "CMT_FIFO_NE4BEG1_4", + "CMT_TOP_NE4BEG1_5" + ], + [ + "CMT_FIFO_WL1END1_1", + "CMT_TOP_WL1END1_2" + ], + [ + "CMT_FIFO_L_IMUX38_1", + "CMT_TOP_IMUX38_2" + ], + [ + "CMT_FIFO_EE4B1_10", + "CMT_TOP_EE4B1_11" + ], + [ + "CMT_FIFO_L_IMUX46_11", + "CMT_TOP_IMUX46_12" + ], + [ + "CMT_FIFO_L_BYP2_10", + "CMT_TOP_BYP2_11" + ], + [ + "CMT_FIFO_NE4C3_10", + "CMT_TOP_NE4C3_11" + ], + [ + "CMT_FIFO_WW2END3_1", + "CMT_TOP_WW2END3_2" + ], + [ + "CMT_FIFO_L_IMUX30_0", + "CMT_TOP_IMUX30_1" + ], + [ + "CMT_FIFO_WR1END0_6", + "CMT_TOP_WR1END0_7" + ], + [ + "CMT_FIFO_L_IMUX27_9", + "CMT_TOP_IMUX27_10" + ], + [ + "CMT_FIFO_EL1BEG3_8", + "CMT_TOP_EL1BEG3_9" + ], + [ + "CMT_FIFO_WW4END0_5", + "CMT_TOP_WW4END0_6" + ], + [ + "CMT_FIFO_L_FAN3_8", + "CMT_TOP_FAN3_9" + ], + [ + "CMT_FIFO_WW4END1_0", + "CMT_TOP_WW4END1_1" + ], + [ + "CMT_FIFO_L_IMUX37_10", + "CMT_TOP_IMUX37_11" + ], + [ + "CMT_FIFO_SE4BEG2_1", + "CMT_TOP_SE4BEG2_2" + ], + [ + "CMT_FIFO_L_BYP3_10", + "CMT_TOP_BYP3_11" + ], + [ + "CMT_FIFO_LH4_7", + "CMT_TOP_LH4_8" + ], + [ + "CMT_FIFO_L_IMUX35_9", + "CMT_TOP_IMUX35_10" + ], + [ + "CMT_FIFO_L_CLK0_2", + "CMT_TOP_CLK0_3" + ], + [ + "CMT_FIFO_L_IMUX8_6", + "CMT_TOP_IMUX8_7" + ], + [ + "CMT_FIFO_SE4C2_9", + "CMT_TOP_SE4C2_10" + ], + [ + "CMT_FIFO_NW4A1_5", + "CMT_TOP_NW4A1_6" + ], + [ + "CMT_FIFO_L_IMUX33_5", + "CMT_TOP_IMUX33_6" + ], + [ + "CMT_FIFO_SW2A0_0", + "CMT_TOP_SW2A0_1" + ], + [ + "CMT_FIFO_WW2END0_11", + "CMT_TOP_WW2END0_12" + ], + [ + "CMT_FIFO_L_BYP4_3", + "CMT_TOP_BYP4_4" + ], + [ + "CMT_FIFO_LH6_3", + "CMT_TOP_LH6_4" + ], + [ + "CMT_FIFO_WW4C0_8", + "CMT_TOP_WW4C0_9" + ], + [ + "CMT_FIFO_WW2A3_8", + "CMT_TOP_WW2A3_9" + ], + [ + "CMT_FIFO_NE4C0_2", + "CMT_TOP_NE4C0_3" + ], + [ + "CMT_FIFO_SE4C1_8", + "CMT_TOP_SE4C1_9" + ], + [ + "CMT_FIFO_SE4BEG0_10", + "CMT_TOP_SE4BEG0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_9", + "CMT_TOP_LOGIC_OUTS_L_B17_10" + ], + [ + "CMT_FIFO_L_FAN5_5", + "CMT_TOP_FAN5_6" + ], + [ + "CMT_FIFO_L_IMUX0_4", + "CMT_TOP_IMUX0_5" + ], + [ + "CMT_FIFO_L_IMUX10_2", + "CMT_TOP_IMUX10_3" + ], + [ + "CMT_FIFO_MONITOR_P_8", + "CMT_TOP_MONITOR_P_9" + ], + [ + "CMT_FIFO_L_FAN7_7", + "CMT_TOP_FAN7_8" + ], + [ + "CMT_FIFO_SE2A1_0", + "CMT_TOP_SE2A1_1" + ], + [ + "CMT_FIFO_SW4END2_10", + "CMT_TOP_SW4END2_11" + ], + [ + "CMT_FIFO_WW4END2_9", + "CMT_TOP_WW4END2_10" + ], + [ + "CMT_FIFO_WW4END1_9", + "CMT_TOP_WW4END1_10" + ], + [ + "CMT_FIFO_EE4BEG2_1", + "CMT_TOP_EE4BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX44_3", + "CMT_TOP_IMUX44_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_10", + "CMT_TOP_LOGIC_OUTS_L_B8_11" + ], + [ + "CMT_FIFO_L_FAN7_0", + "CMT_TOP_FAN7_1" + ], + [ + "CMT_FIFO_EE4B0_6", + "CMT_TOP_EE4B0_7" + ], + [ + "CMT_FIFO_L_IMUX43_3", + "CMT_TOP_IMUX43_4" + ], + [ + "CMT_FIFO_LH6_10", + "CMT_TOP_LH6_11" + ], + [ + "CMT_FIFO_WR1END3_5", + "CMT_TOP_WR1END3_6" + ], + [ + "CMT_FIFO_NE4C0_0", + "CMT_TOP_NE4C0_1" + ], + [ + "CMT_FIFO_L_FAN6_7", + "CMT_TOP_FAN6_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_9", + "CMT_TOP_LOGIC_OUTS_L_B0_10" + ], + [ + "CMT_FIFO_L_IMUX37_8", + "CMT_TOP_IMUX37_9" + ], + [ + "CMT_FIFO_L_IMUX29_4", + "CMT_TOP_IMUX29_5" + ], + [ + "CMT_FIFO_SW2A1_5", + "CMT_TOP_SW2A1_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "CMT_TOP_OCLK_8" + ], + [ + "CMT_FIFO_ER1BEG0_5", + "CMT_TOP_ER1BEG0_6" + ], + [ + "CMT_FIFO_L_IMUX30_9", + "CMT_TOP_IMUX30_10" + ], + [ + "CMT_FIFO_SE2A2_8", + "CMT_TOP_SE2A2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_10", + "CMT_TOP_LOGIC_OUTS_L_B13_11" + ], + [ + "CMT_FIFO_L_IMUX40_1", + "CMT_TOP_IMUX40_2" + ], + [ + "CMT_FIFO_WW2END0_0", + "CMT_TOP_WW2END0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_4", + "CMT_TOP_LOGIC_OUTS_L_B22_5" + ], + [ + "CMT_FIFO_L_BYP0_0", + "CMT_TOP_BYP0_1" + ], + [ + "CMT_FIFO_EL1BEG2_9", + "CMT_TOP_EL1BEG2_10" + ], + [ + "CMT_FIFO_NE4BEG2_0", + "CMT_TOP_NE4BEG2_1" + ], + [ + "CMT_FIFO_L_CLK0_6", + "CMT_TOP_CLK0_7" + ], + [ + "CMT_FIFO_WW2A3_7", + "CMT_TOP_WW2A3_8" + ], + [ + "CMT_FIFO_ER1BEG2_4", + "CMT_TOP_ER1BEG2_5" + ], + [ + "CMT_FIFO_EE2A1_0", + "CMT_TOP_EE2A1_1" + ], + [ + "CMT_FIFO_L_IMUX11_0", + "CMT_TOP_IMUX11_1" + ], + [ + "CMT_FIFO_L_IMUX22_7", + "CMT_TOP_IMUX22_8" + ], + [ + "CMT_FIFO_WW4A1_9", + "CMT_TOP_WW4A1_10" + ], + [ + "CMT_FIFO_ER1BEG2_2", + "CMT_TOP_ER1BEG2_3" + ], + [ + "CMT_FIFO_NE2A2_5", + "CMT_TOP_NE2A2_6" + ], + [ + "CMT_FIFO_L_CLK1_0", + "CMT_TOP_CLK1_1" + ], + [ + "CMT_FIFO_WR1END3_8", + "CMT_TOP_WR1END3_9" + ], + [ + "CMT_FIFO_SE2A1_11", + "CMT_TOP_SE2A1_12" + ], + [ + "CMT_FIFO_WW2A3_2", + "CMT_TOP_WW2A3_3" + ], + [ + "CMT_FIFO_WW4END2_10", + "CMT_TOP_WW4END2_11" + ], + [ + "CMT_FIFO_L_FAN1_0", + "CMT_TOP_FAN1_1" + ], + [ + "CMT_FIFO_L_IMUX4_9", + "CMT_TOP_IMUX4_10" + ], + [ + "CMT_FIFO_LH6_2", + "CMT_TOP_LH6_3" + ], + [ + "CMT_FIFO_LH5_5", + "CMT_TOP_LH5_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_2", + "CMT_TOP_LOGIC_OUTS_L_B20_3" + ], + [ + "CMT_FIFO_WW4B3_0", + "CMT_TOP_WW4B3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_1", + "CMT_TOP_LOGIC_OUTS_L_B16_2" + ], + [ + "CMT_FIFO_WW4C0_4", + "CMT_TOP_WW4C0_5" + ], + [ + "CMT_FIFO_NE4BEG3_6", + "CMT_TOP_NE4BEG3_7" + ], + [ + "CMT_FIFO_WW2A0_1", + "CMT_TOP_WW2A0_2" + ], + [ + "CMT_FIFO_NW4A2_4", + "CMT_TOP_NW4A2_5" + ], + [ + "CMT_FIFO_L_IMUX11_5", + "CMT_TOP_IMUX11_6" + ], + [ + "CMT_FIFO_NW4END1_3", + "CMT_TOP_NW4END1_4" + ], + [ + "CMT_FIFO_SW2A2_9", + "CMT_TOP_SW2A2_10" + ], + [ + "CMT_FIFO_EL1BEG3_4", + "CMT_TOP_EL1BEG3_5" + ], + [ + "CMT_FIFO_WW2A0_8", + "CMT_TOP_WW2A0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_8", + "CMT_TOP_LOGIC_OUTS_L_B17_9" + ], + [ + "CMT_FIFO_WW4A3_2", + "CMT_TOP_WW4A3_3" + ], + [ + "CMT_FIFO_NW4END2_4", + "CMT_TOP_NW4END2_5" + ], + [ + "CMT_FIFO_WW4C3_11", + "CMT_TOP_WW4C3_12" + ], + [ + "CMT_FIFO_NE4BEG2_8", + "CMT_TOP_NE4BEG2_9" + ], + [ + "CMT_FIFO_L_IMUX1_5", + "CMT_TOP_IMUX1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_0", + "CMT_TOP_LOGIC_OUTS_L_B16_1" + ], + [ + "CMT_FIFO_ER1BEG3_10", + "CMT_TOP_ER1BEG3_11" + ], + [ + "CMT_FIFO_EE2BEG1_8", + "CMT_TOP_EE2BEG1_9" + ], + [ + "CMT_FIFO_L_IMUX23_4", + "CMT_TOP_IMUX23_5" + ], + [ + "CMT_FIFO_L_IMUX6_3", + "CMT_TOP_IMUX6_4" + ], + [ + "CMT_FIFO_SE2A0_10", + "CMT_TOP_SE2A0_11" + ], + [ + "CMT_FIFO_WW2A3_1", + "CMT_TOP_WW2A3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_7", + "CMT_TOP_LOGIC_OUTS_L_B19_8" + ], + [ + "CMT_FIFO_L_IMUX19_6", + "CMT_TOP_IMUX19_7" + ], + [ + "CMT_FIFO_L_IMUX2_1", + "CMT_TOP_IMUX2_2" + ], + [ + "CMT_FIFO_LH10_6", + "CMT_TOP_LH10_7" + ], + [ + "CMT_FIFO_L_IMUX29_11", + "CMT_TOP_IMUX29_12" + ], + [ + "CMT_FIFO_NW2A1_8", + "CMT_TOP_NW2A1_9" + ], + [ + "CMT_FIFO_L_CLK0_4", + "CMT_TOP_CLK0_5" + ], + [ + "CMT_FIFO_NW4END0_6", + "CMT_TOP_NW4END0_7" + ], + [ + "CMT_FIFO_EE4A3_1", + "CMT_TOP_EE4A3_2" + ], + [ + "CMT_FIFO_L_IMUX30_11", + "CMT_TOP_IMUX30_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_6", + "CMT_TOP_LOGIC_OUTS_L_B9_7" + ], + [ + "CMT_FIFO_WW4B1_6", + "CMT_TOP_WW4B1_7" + ], + [ + "CMT_FIFO_L_IMUX16_7", + "CMT_TOP_IMUX16_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_7", + "CMT_TOP_LOGIC_OUTS_L_B11_8" + ], + [ + "CMT_FIFO_LH11_11", + "CMT_TOP_LH11_12" + ], + [ + "CMT_FIFO_EE4A1_6", + "CMT_TOP_EE4A1_7" + ], + [ + "CMT_FIFO_WW4A0_1", + "CMT_TOP_WW4A0_2" + ], + [ + "CMT_FIFO_SE2A0_0", + "CMT_TOP_SE2A0_1" + ], + [ + "CMT_FIFO_SE4C0_4", + "CMT_TOP_SE4C0_5" + ], + [ + "CMT_FIFO_ER1BEG2_10", + "CMT_TOP_ER1BEG2_11" + ], + [ + "CMT_FIFO_L_IMUX39_10", + "CMT_TOP_IMUX39_11" + ], + [ + "CMT_FIFO_L_FAN3_6", + "CMT_TOP_FAN3_7" + ], + [ + "CMT_FIFO_L_IMUX45_6", + "CMT_TOP_IMUX45_7" + ], + [ + "CMT_FIFO_WR1END0_7", + "CMT_TOP_WR1END0_8" + ], + [ + "CMT_FIFO_L_IMUX26_1", + "CMT_TOP_IMUX26_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "CMT_TOP_OCLKDIV_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_7", + "CMT_TOP_LOGIC_OUTS_L_B13_8" + ], + [ + "CMT_FIFO_L_BYP4_1", + "CMT_TOP_BYP4_2" + ], + [ + "CMT_FIFO_WW4END3_1", + "CMT_TOP_WW4END3_2" + ], + [ + "CMT_FIFO_L_FAN3_3", + "CMT_TOP_FAN3_4" + ], + [ + "CMT_FIFO_L_IMUX36_8", + "CMT_TOP_IMUX36_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_6", + "CMT_TOP_LOGIC_OUTS_L_B8_7" + ], + [ + "CMT_FIFO_LH12_2", + "CMT_TOP_LH12_3" + ], + [ + "CMT_FIFO_EE4B1_5", + "CMT_TOP_EE4B1_6" + ], + [ + "CMT_FIFO_SE4BEG0_5", + "CMT_TOP_SE4BEG0_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "CMT_TOP_OCLK_4" + ], + [ + "CMT_FIFO_L_IMUX16_0", + "CMT_TOP_IMUX16_1" + ], + [ + "CMT_FIFO_EE4BEG3_0", + "CMT_TOP_EE4BEG3_1" + ], + [ + "CMT_FIFO_L_IMUX36_4", + "CMT_TOP_IMUX36_5" + ], + [ + "CMT_FIFO_L_IMUX1_3", + "CMT_TOP_IMUX1_4" + ], + [ + "CMT_FIFO_EL1BEG1_9", + "CMT_TOP_EL1BEG1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_6", + "CMT_TOP_LOGIC_OUTS_L_B16_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_4", + "CMT_TOP_LOGIC_OUTS_L_B19_5" + ], + [ + "CMT_FIFO_NW4END3_4", + "CMT_TOP_NW4END3_5" + ], + [ + "CMT_FIFO_SW4A2_4", + "CMT_TOP_SW4A2_5" + ], + [ + "CMT_FIFO_LH2_1", + "CMT_TOP_LH2_2" + ], + [ + "CMT_FIFO_L_IMUX30_5", + "CMT_TOP_IMUX30_6" + ], + [ + "CMT_FIFO_L_IMUX42_5", + "CMT_TOP_IMUX42_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_6", + "CMT_TOP_LOGIC_OUTS_L_B19_7" + ], + [ + "CMT_FIFO_L_IMUX40_6", + "CMT_TOP_IMUX40_7" + ], + [ + "CMT_FIFO_WW4B2_8", + "CMT_TOP_WW4B2_9" + ], + [ + "CMT_FIFO_L_IMUX9_5", + "CMT_TOP_IMUX9_6" + ], + [ + "CMT_FIFO_L_IMUX41_4", + "CMT_TOP_IMUX41_5" + ], + [ + "CMT_FIFO_EE4B2_11", + "CMT_TOP_EE4B2_12" + ], + [ + "CMT_FIFO_EL1BEG0_6", + "CMT_TOP_EL1BEG0_7" + ], + [ + "CMT_FIFO_SW4A3_3", + "CMT_TOP_SW4A3_4" + ], + [ + "CMT_FIFO_SE4C3_10", + "CMT_TOP_SE4C3_11" + ], + [ + "CMT_FIFO_L_IMUX41_7", + "CMT_TOP_IMUX41_8" + ], + [ + "CMT_FIFO_L_IMUX14_11", + "CMT_TOP_IMUX14_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_4", + "CMT_TOP_LOGIC_OUTS_L_B11_5" + ], + [ + "CMT_FIFO_NE2A1_2", + "CMT_TOP_NE2A1_3" + ], + [ + "CMT_FIFO_NW4END2_2", + "CMT_TOP_NW4END2_3" + ], + [ + "CMT_FIFO_NE2A0_7", + "CMT_TOP_NE2A0_8" + ], + [ + "CMT_FIFO_WW2END1_1", + "CMT_TOP_WW2END1_2" + ], + [ + "CMT_FIFO_SW2A2_6", + "CMT_TOP_SW2A2_7" + ], + [ + "CMT_FIFO_EE4B0_2", + "CMT_TOP_EE4B0_3" + ], + [ + "CMT_FIFO_L_IMUX26_8", + "CMT_TOP_IMUX26_9" + ], + [ + "CMT_FIFO_SW2A0_9", + "CMT_TOP_SW2A0_10" + ], + [ + "CMT_FIFO_L_IMUX8_10", + "CMT_TOP_IMUX8_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "CMT_TOP_ICLKDIV_2" + ], + [ + "CMT_FIFO_SW4A2_0", + "CMT_TOP_SW4A2_1" + ], + [ + "CMT_FIFO_L_FAN2_11", + "CMT_TOP_FAN2_12" + ], + [ + "CMT_FIFO_L_IMUX30_4", + "CMT_TOP_IMUX30_5" + ], + [ + "CMT_FIFO_NE2A3_5", + "CMT_TOP_NE2A3_6" + ], + [ + "CMT_FIFO_WW2A1_9", + "CMT_TOP_WW2A1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_8" + ], + [ + "CMT_FIFO_L_IMUX41_0", + "CMT_TOP_IMUX41_1" + ], + [ + "CMT_FIFO_L_FAN5_1", + "CMT_TOP_FAN5_2" + ], + [ + "CMT_FIFO_EE2A1_11", + "CMT_TOP_EE2A1_12" + ], + [ + "CMT_FIFO_L_CLK1_7", + "CMT_TOP_CLK1_8" + ], + [ + "CMT_FIFO_EE4B0_8", + "CMT_TOP_EE4B0_9" + ], + [ + "CMT_FIFO_L_BYP5_8", + "CMT_TOP_BYP5_9" + ], + [ + "CMT_FIFO_LH9_2", + "CMT_TOP_LH9_3" + ], + [ + "CMT_FIFO_SE4BEG1_1", + "CMT_TOP_SE4BEG1_2" + ], + [ + "CMT_FIFO_L_IMUX29_0", + "CMT_TOP_IMUX29_1" + ], + [ + "CMT_FIFO_L_FAN0_8", + "CMT_TOP_FAN0_9" + ], + [ + "CMT_FIFO_SE4C3_1", + "CMT_TOP_SE4C3_2" + ], + [ + "CMT_FIFO_LH6_4", + "CMT_TOP_LH6_5" + ], + [ + "CMT_FIFO_SW4END3_11", + "CMT_TOP_SW4END3_12" + ], + [ + "CMT_FIFO_SE4BEG1_4", + "CMT_TOP_SE4BEG1_5" + ], + [ + "CMT_FIFO_SE2A0_2", + "CMT_TOP_SE2A0_3" + ], + [ + "CMT_FIFO_WW4A1_0", + "CMT_TOP_WW4A1_1" + ], + [ + "CMT_FIFO_EE4C1_10", + "CMT_TOP_EE4C1_11" + ], + [ + "CMT_FIFO_WW2A1_8", + "CMT_TOP_WW2A1_9" + ], + [ + "CMT_FIFO_L_CTRL1_8", + "CMT_TOP_CTRL1_9" + ], + [ + "CMT_FIFO_L_FAN5_0", + "CMT_TOP_FAN5_1" + ], + [ + "CMT_FIFO_SE4C3_0", + "CMT_TOP_SE4C3_1" + ], + [ + "CMT_FIFO_WR1END3_10", + "CMT_TOP_WR1END3_11" + ], + [ + "CMT_FIFO_L_FAN7_11", + "CMT_TOP_FAN7_12" + ], + [ + "CMT_FIFO_L_IMUX39_11", + "CMT_TOP_IMUX39_12" + ], + [ + "CMT_FIFO_SW2A3_2", + "CMT_TOP_SW2A3_3" + ], + [ + "CMT_FIFO_WW4A2_11", + "CMT_TOP_WW4A2_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_8", + "CMT_TOP_LOGIC_OUTS_L_B0_9" + ], + [ + "CMT_FIFO_WW4END2_4", + "CMT_TOP_WW4END2_5" + ], + [ + "CMT_FIFO_NE2A1_0", + "CMT_TOP_NE2A1_1" + ], + [ + "CMT_FIFO_SE4C2_10", + "CMT_TOP_SE4C2_11" + ], + [ + "CMT_FIFO_ER1BEG0_0", + "CMT_TOP_ER1BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_5", + "CMT_TOP_LOGIC_OUTS_L_B15_6" + ], + [ + "CMT_FIFO_L_IMUX9_7", + "CMT_TOP_IMUX9_8" + ], + [ + "CMT_FIFO_L_IMUX7_1", + "CMT_TOP_IMUX7_2" + ], + [ + "CMT_FIFO_NE2A3_6", + "CMT_TOP_NE2A3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_2", + "CMT_TOP_LOGIC_OUTS_L_B18_3" + ], + [ + "CMT_FIFO_NE4C0_3", + "CMT_TOP_NE4C0_4" + ], + [ + "CMT_FIFO_SE4C1_11", + "CMT_TOP_SE4C1_12" + ], + [ + "CMT_FIFO_SW2A2_10", + "CMT_TOP_SW2A2_11" + ], + [ + "CMT_FIFO_SW2A1_7", + "CMT_TOP_SW2A1_8" + ], + [ + "CMT_FIFO_EE4B1_7", + "CMT_TOP_EE4B1_8" + ], + [ + "CMT_FIFO_NW2A1_7", + "CMT_TOP_NW2A1_8" + ], + [ + "CMT_FIFO_SE4C3_3", + "CMT_TOP_SE4C3_4" + ], + [ + "CMT_FIFO_L_IMUX6_0", + "CMT_TOP_IMUX6_1" + ], + [ + "CMT_FIFO_L_CTRL1_6", + "CMT_TOP_CTRL1_7" + ], + [ + "CMT_FIFO_LH5_6", + "CMT_TOP_LH5_7" + ], + [ + "CMT_FIFO_SW2A3_6", + "CMT_TOP_SW2A3_7" + ], + [ + "CMT_FIFO_EE4BEG3_2", + "CMT_TOP_EE4BEG3_3" + ], + [ + "CMT_FIFO_NW2A0_5", + "CMT_TOP_NW2A0_6" + ], + [ + "CMT_FIFO_WL1END3_10", + "CMT_TOP_WL1END3_11" + ], + [ + "CMT_FIFO_EE2A0_10", + "CMT_TOP_EE2A0_11" + ], + [ + "CMT_FIFO_L_CLK1_11", + "CMT_TOP_CLK1_12" + ], + [ + "CMT_FIFO_L_FAN0_1", + "CMT_TOP_FAN0_2" + ], + [ + "CMT_FIFO_NE4C0_8", + "CMT_TOP_NE4C0_9" + ], + [ + "CMT_FIFO_LH7_4", + "CMT_TOP_LH7_5" + ], + [ + "CMT_FIFO_NW4END3_1", + "CMT_TOP_NW4END3_2" + ], + [ + "CMT_FIFO_NW2A1_9", + "CMT_TOP_NW2A1_10" + ], + [ + "CMT_FIFO_LH5_8", + "CMT_TOP_LH5_9" + ], + [ + "CMT_FIFO_SW4A1_6", + "CMT_TOP_SW4A1_7" + ], + [ + "CMT_FIFO_SE4BEG0_11", + "CMT_TOP_SE4BEG0_12" + ], + [ + "CMT_FIFO_EE4A0_3", + "CMT_TOP_EE4A0_4" + ], + [ + "CMT_FIFO_L_FAN5_10", + "CMT_TOP_FAN5_11" + ], + [ + "CMT_FIFO_WW4END3_9", + "CMT_TOP_WW4END3_10" + ], + [ + "CMT_FIFO_SW4END0_4", + "CMT_TOP_SW4END0_5" + ], + [ + "CMT_FIFO_EE4C3_11", + "CMT_TOP_EE4C3_12" + ], + [ + "CMT_FIFO_L_FAN3_0", + "CMT_TOP_FAN3_1" + ], + [ + "CMT_FIFO_WW2END0_2", + "CMT_TOP_WW2END0_3" + ], + [ + "CMT_FIFO_EE4B3_7", + "CMT_TOP_EE4B3_8" + ], + [ + "CMT_FIFO_L_CTRL0_11", + "CMT_TOP_CTRL0_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_11", + "CMT_TOP_LOGIC_OUTS_L_B19_12" + ], + [ + "CMT_FIFO_SW4A2_1", + "CMT_TOP_SW4A2_2" + ], + [ + "CMT_FIFO_WW2A0_4", + "CMT_TOP_WW2A0_5" + ], + [ + "CMT_FIFO_EE2A1_4", + "CMT_TOP_EE2A1_5" + ], + [ + "CMT_FIFO_WW4B2_7", + "CMT_TOP_WW4B2_8" + ], + [ + "CMT_FIFO_L_CTRL1_1", + "CMT_TOP_CTRL1_2" + ], + [ + "CMT_FIFO_ER1BEG1_8", + "CMT_TOP_ER1BEG1_9" + ], + [ + "CMT_FIFO_EL1BEG2_4", + "CMT_TOP_EL1BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX12_0", + "CMT_TOP_IMUX12_1" + ], + [ + "CMT_FIFO_L_IMUX28_8", + "CMT_TOP_IMUX28_9" + ], + [ + "CMT_FIFO_NE2A0_6", + "CMT_TOP_NE2A0_7" + ], + [ + "CMT_FIFO_L_IMUX32_5", + "CMT_TOP_IMUX32_6" + ], + [ + "CMT_FIFO_L_IMUX42_6", + "CMT_TOP_IMUX42_7" + ], + [ + "CMT_FIFO_L_BYP3_9", + "CMT_TOP_BYP3_10" + ], + [ + "CMT_FIFO_L_IMUX5_1", + "CMT_TOP_IMUX5_2" + ], + [ + "CMT_FIFO_LH9_11", + "CMT_TOP_LH9_12" + ], + [ + "CMT_FIFO_WW2A3_10", + "CMT_TOP_WW2A3_11" + ], + [ + "CMT_FIFO_NW4END1_1", + "CMT_TOP_NW4END1_2" + ], + [ + "CMT_FIFO_WL1END3_1", + "CMT_TOP_WL1END3_2" + ], + [ + "CMT_FIFO_NW2A2_7", + "CMT_TOP_NW2A2_8" + ], + [ + "CMT_FIFO_L_IMUX28_0", + "CMT_TOP_IMUX28_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_7", + "CMT_TOP_LOGIC_OUTS_L_B23_8" + ], + [ + "CMT_FIFO_NE4C2_5", + "CMT_TOP_NE4C2_6" + ], + [ + "CMT_FIFO_L_IMUX8_11", + "CMT_TOP_IMUX8_12" + ], + [ + "CMT_FIFO_L_FAN4_11", + "CMT_TOP_FAN4_12" + ], + [ + "CMT_FIFO_L_IMUX40_4", + "CMT_TOP_IMUX40_5" + ], + [ + "CMT_FIFO_L_IMUX11_8", + "CMT_TOP_IMUX11_9" + ], + [ + "CMT_FIFO_L_IMUX27_0", + "CMT_TOP_IMUX27_1" + ], + [ + "CMT_FIFO_L_IMUX3_10", + "CMT_TOP_IMUX3_11" + ], + [ + "CMT_FIFO_L_IMUX12_7", + "CMT_TOP_IMUX12_8" + ], + [ + "CMT_FIFO_L_IMUX35_3", + "CMT_TOP_IMUX35_4" + ], + [ + "CMT_FIFO_L_IMUX23_0", + "CMT_TOP_IMUX23_1" + ], + [ + "CMT_FIFO_L_IMUX20_7", + "CMT_TOP_IMUX20_8" + ], + [ + "CMT_FIFO_SE4C3_9", + "CMT_TOP_SE4C3_10" + ], + [ + "CMT_FIFO_L_IMUX42_9", + "CMT_TOP_IMUX42_10" + ], + [ + "CMT_FIFO_WW2A1_3", + "CMT_TOP_WW2A1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_2", + "CMT_TOP_LOGIC_OUTS_L_B9_3" + ], + [ + "CMT_FIFO_NE4BEG1_8", + "CMT_TOP_NE4BEG1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_3", + "CMT_TOP_LOGIC_OUTS_L_B19_4" + ], + [ + "CMT_FIFO_L_IMUX22_3", + "CMT_TOP_IMUX22_4" + ], + [ + "CMT_FIFO_L_IMUX46_1", + "CMT_TOP_IMUX46_2" + ], + [ + "CMT_FIFO_L_IMUX25_9", + "CMT_TOP_IMUX25_10" + ], + [ + "CMT_FIFO_SE2A0_7", + "CMT_TOP_SE2A0_8" + ], + [ + "CMT_FIFO_L_BYP3_4", + "CMT_TOP_BYP3_5" + ], + [ + "CMT_FIFO_WW2END1_2", + "CMT_TOP_WW2END1_3" + ], + [ + "CMT_FIFO_WW4C1_9", + "CMT_TOP_WW4C1_10" + ], + [ + "CMT_FIFO_NW4END1_4", + "CMT_TOP_NW4END1_5" + ], + [ + "CMT_FIFO_WW4END3_5", + "CMT_TOP_WW4END3_6" + ], + [ + "CMT_FIFO_EL1BEG2_3", + "CMT_TOP_EL1BEG2_4" + ], + [ + "CMT_FIFO_L_IMUX7_5", + "CMT_TOP_IMUX7_6" + ], + [ + "CMT_FIFO_L_FAN0_5", + "CMT_TOP_FAN0_6" + ], + [ + "CMT_FIFO_L_IMUX31_2", + "CMT_TOP_IMUX31_3" + ], + [ + "CMT_FIFO_WW4A2_5", + "CMT_TOP_WW4A2_6" + ], + [ + "CMT_FIFO_L_BYP4_10", + "CMT_TOP_BYP4_11" + ], + [ + "CMT_FIFO_EE2BEG3_7", + "CMT_TOP_EE2BEG3_8" + ], + [ + "CMT_FIFO_WW4END3_4", + "CMT_TOP_WW4END3_5" + ], + [ + "CMT_FIFO_WR1END0_3", + "CMT_TOP_WR1END0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_6", + "CMT_TOP_LOGIC_OUTS_L_B11_7" + ], + [ + "CMT_FIFO_EE4B3_8", + "CMT_TOP_EE4B3_9" + ], + [ + "CMT_FIFO_NE4BEG0_11", + "CMT_TOP_NE4BEG0_12" + ], + [ + "CMT_FIFO_L_FAN2_5", + "CMT_TOP_FAN2_6" + ], + [ + "CMT_FIFO_L_BYP4_9", + "CMT_TOP_BYP4_10" + ], + [ + "CMT_FIFO_SE4BEG3_10", + "CMT_TOP_SE4BEG3_11" + ], + [ + "CMT_FIFO_L_BYP6_3", + "CMT_TOP_BYP6_4" + ], + [ + "CMT_FIFO_WW4B0_9", + "CMT_TOP_WW4B0_10" + ], + [ + "CMT_FIFO_SE4BEG2_10", + "CMT_TOP_SE4BEG2_11" + ], + [ + "CMT_FIFO_WW2A1_0", + "CMT_TOP_WW2A1_1" + ], + [ + "CMT_FIFO_EE4BEG3_4", + "CMT_TOP_EE4BEG3_5" + ], + [ + "CMT_FIFO_WW4A0_5", + "CMT_TOP_WW4A0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_5", + "CMT_TOP_LOGIC_OUTS_L_B23_6" + ], + [ + "CMT_FIFO_EE4B0_7", + "CMT_TOP_EE4B0_8" + ], + [ + "CMT_FIFO_LH11_8", + "CMT_TOP_LH11_9" + ], + [ + "CMT_FIFO_NW4END2_0", + "CMT_TOP_NW4END2_1" + ], + [ + "CMT_FIFO_WW4A2_0", + "CMT_TOP_WW4A2_1" + ], + [ + "CMT_FIFO_SW4END2_9", + "CMT_TOP_SW4END2_10" + ], + [ + "CMT_FIFO_EE2BEG2_11", + "CMT_TOP_EE2BEG2_12" + ], + [ + "CMT_FIFO_NE4BEG3_7", + "CMT_TOP_NE4BEG3_8" + ], + [ + "CMT_FIFO_WW4C0_6", + "CMT_TOP_WW4C0_7" + ], + [ + "CMT_FIFO_LH9_4", + "CMT_TOP_LH9_5" + ], + [ + "CMT_FIFO_SE2A1_6", + "CMT_TOP_SE2A1_7" + ], + [ + "CMT_FIFO_NE4C3_8", + "CMT_TOP_NE4C3_9" + ], + [ + "CMT_FIFO_L_IMUX6_2", + "CMT_TOP_IMUX6_3" + ], + [ + "CMT_FIFO_L_IMUX28_6", + "CMT_TOP_IMUX28_7" + ], + [ + "CMT_FIFO_NW4END1_6", + "CMT_TOP_NW4END1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_0", + "CMT_TOP_LOGIC_OUTS_L_B22_1" + ], + [ + "CMT_FIFO_L_IMUX33_9", + "CMT_TOP_IMUX33_10" + ], + [ + "CMT_FIFO_WW4A0_11", + "CMT_TOP_WW4A0_12" + ], + [ + "CMT_FIFO_NW4A0_8", + "CMT_TOP_NW4A0_9" + ], + [ + "CMT_FIFO_WW2A3_3", + "CMT_TOP_WW2A3_4" + ], + [ + "CMT_FIFO_WW2END1_11", + "CMT_TOP_WW2END1_12" + ], + [ + "CMT_FIFO_WW2A2_5", + "CMT_TOP_WW2A2_6" + ], + [ + "CMT_FIFO_L_IMUX47_9", + "CMT_TOP_IMUX47_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_5", + "CMT_TOP_LOGIC_OUTS_L_B10_6" + ], + [ + "CMT_FIFO_NE2A1_9", + "CMT_TOP_NE2A1_10" + ], + [ + "CMT_FIFO_NE4BEG3_10", + "CMT_TOP_NE4BEG3_11" + ], + [ + "CMT_FIFO_NE4BEG0_6", + "CMT_TOP_NE4BEG0_7" + ], + [ + "CMT_FIFO_WL1END0_6", + "CMT_TOP_WL1END0_7" + ], + [ + "CMT_FIFO_SW2A0_8", + "CMT_TOP_SW2A0_9" + ], + [ + "CMT_FIFO_WW4C3_8", + "CMT_TOP_WW4C3_9" + ], + [ + "CMT_FIFO_SE4BEG2_9", + "CMT_TOP_SE4BEG2_10" + ], + [ + "CMT_FIFO_EL1BEG3_7", + "CMT_TOP_EL1BEG3_8" + ], + [ + "CMT_FIFO_SE2A2_11", + "CMT_TOP_SE2A2_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_6", + "CMT_TOP_LOGIC_OUTS_L_B17_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_1" + ], + [ + "CMT_FIFO_EE4BEG0_4", + "CMT_TOP_EE4BEG0_5" + ], + [ + "CMT_FIFO_L_IMUX24_0", + "CMT_TOP_IMUX24_1" + ], + [ + "CMT_FIFO_EE4A1_4", + "CMT_TOP_EE4A1_5" + ], + [ + "CMT_FIFO_SE4BEG3_7", + "CMT_TOP_SE4BEG3_8" + ], + [ + "CMT_FIFO_SW4A1_7", + "CMT_TOP_SW4A1_8" + ], + [ + "CMT_FIFO_L_IMUX6_10", + "CMT_TOP_IMUX6_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_4", + "CMT_TOP_LOGIC_OUTS_L_B12_5" + ], + [ + "CMT_FIFO_EE2BEG2_8", + "CMT_TOP_EE2BEG2_9" + ], + [ + "CMT_FIFO_L_IMUX39_5", + "CMT_TOP_IMUX39_6" + ], + [ + "CMT_FIFO_SW4A3_6", + "CMT_TOP_SW4A3_7" + ], + [ + "CMT_FIFO_NE4BEG2_10", + "CMT_TOP_NE4BEG2_11" + ], + [ + "CMT_FIFO_SE2A1_10", + "CMT_TOP_SE2A1_11" + ], + [ + "CMT_FIFO_SW4END1_2", + "CMT_TOP_SW4END1_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "CMT_TOP_OCLKDIV_8" + ], + [ + "CMT_FIFO_WW2END2_7", + "CMT_TOP_WW2END2_8" + ], + [ + "CMT_FIFO_L_BYP4_4", + "CMT_TOP_BYP4_5" + ], + [ + "CMT_FIFO_NW2A2_6", + "CMT_TOP_NW2A2_7" + ], + [ + "CMT_FIFO_NE2A3_9", + "CMT_TOP_NE2A3_10" + ], + [ + "CMT_FIFO_EE2A0_4", + "CMT_TOP_EE2A0_5" + ], + [ + "CMT_FIFO_NW4END1_0", + "CMT_TOP_NW4END1_1" + ], + [ + "CMT_FIFO_L_IMUX42_4", + "CMT_TOP_IMUX42_5" + ], + [ + "CMT_FIFO_L_IMUX0_8", + "CMT_TOP_IMUX0_9" + ], + [ + "CMT_FIFO_L_IMUX19_3", + "CMT_TOP_IMUX19_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "CMT_TOP_OCLKDIV_12" + ], + [ + "CMT_FIFO_LH11_6", + "CMT_TOP_LH11_7" + ], + [ + "CMT_FIFO_WW4B0_11", + "CMT_TOP_WW4B0_12" + ], + [ + "CMT_FIFO_L_CTRL1_7", + "CMT_TOP_CTRL1_8" + ], + [ + "CMT_FIFO_SW4A0_9", + "CMT_TOP_SW4A0_10" + ], + [ + "CMT_FIFO_L_FAN3_1", + "CMT_TOP_FAN3_2" + ], + [ + "CMT_FIFO_L_IMUX24_5", + "CMT_TOP_IMUX24_6" + ], + [ + "CMT_FIFO_WW2A0_11", + "CMT_TOP_WW2A0_12" + ], + [ + "CMT_FIFO_NW4END2_1", + "CMT_TOP_NW4END2_2" + ], + [ + "CMT_FIFO_SE4BEG0_7", + "CMT_TOP_SE4BEG0_8" + ], + [ + "CMT_FIFO_LH2_2", + "CMT_TOP_LH2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_9", + "CMT_TOP_LOGIC_OUTS_L_B21_10" + ], + [ + "CMT_FIFO_LH8_10", + "CMT_TOP_LH8_11" + ], + [ + "CMT_FIFO_L_IMUX16_5", + "CMT_TOP_IMUX16_6" + ], + [ + "CMT_FIFO_NW4END0_2", + "CMT_TOP_NW4END0_3" + ], + [ + "CMT_FIFO_WL1END0_10", + "CMT_TOP_WL1END0_11" + ], + [ + "CMT_FIFO_L_CTRL1_9", + "CMT_TOP_CTRL1_10" + ], + [ + "CMT_FIFO_LH9_6", + "CMT_TOP_LH9_7" + ], + [ + "CMT_FIFO_WW2A2_2", + "CMT_TOP_WW2A2_3" + ], + [ + "CMT_FIFO_L_IMUX9_6", + "CMT_TOP_IMUX9_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_11" + ], + [ + "CMT_FIFO_NE2A1_10", + "CMT_TOP_NE2A1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_2", + "CMT_TOP_LOGIC_OUTS_L_B15_3" + ], + [ + "CMT_FIFO_WW4A1_4", + "CMT_TOP_WW4A1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8" + ], + [ + "CMT_FIFO_WL1END2_2", + "CMT_TOP_WL1END2_3" + ], + [ + "CMT_FIFO_ER1BEG2_0", + "CMT_TOP_ER1BEG2_1" + ], + [ + "CMT_FIFO_WW4A2_9", + "CMT_TOP_WW4A2_10" + ], + [ + "CMT_FIFO_L_CLK0_8", + "CMT_TOP_CLK0_9" + ], + [ + "CMT_FIFO_L_IMUX0_11", + "CMT_TOP_IMUX0_12" + ], + [ + "CMT_FIFO_WW4END3_11", + "CMT_TOP_WW4END3_12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "CMT_TOP_OCLKDIV_1" + ], + [ + "CMT_FIFO_L_BYP2_11", + "CMT_TOP_BYP2_12" + ], + [ + "CMT_FIFO_EE4A0_2", + "CMT_TOP_EE4A0_3" + ], + [ + "CMT_FIFO_L_IMUX20_2", + "CMT_TOP_IMUX20_3" + ], + [ + "CMT_FIFO_SE4BEG1_3", + "CMT_TOP_SE4BEG1_4" + ], + [ + "CMT_FIFO_L_FAN5_4", + "CMT_TOP_FAN5_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_9", + "CMT_TOP_LOGIC_OUTS_L_B1_10" + ], + [ + "CMT_FIFO_WW4END0_7", + "CMT_TOP_WW4END0_8" + ], + [ + "CMT_FIFO_L_IMUX10_1", + "CMT_TOP_IMUX10_2" + ], + [ + "CMT_FIFO_EE4B1_8", + "CMT_TOP_EE4B1_9" + ], + [ + "CMT_FIFO_WW4A0_8", + "CMT_TOP_WW4A0_9" + ], + [ + "CMT_FIFO_L_IMUX47_3", + "CMT_TOP_IMUX47_4" + ], + [ + "CMT_FIFO_EE2A3_8", + "CMT_TOP_EE2A3_9" + ], + [ + "CMT_FIFO_ER1BEG3_2", + "CMT_TOP_ER1BEG3_3" + ], + [ + "CMT_FIFO_L_FAN0_7", + "CMT_TOP_FAN0_8" + ], + [ + "CMT_FIFO_L_FAN6_6", + "CMT_TOP_FAN6_7" + ], + [ + "CMT_FIFO_L_IMUX3_2", + "CMT_TOP_IMUX3_3" + ], + [ + "CMT_FIFO_L_IMUX42_0", + "CMT_TOP_IMUX42_1" + ], + [ + "CMT_FIFO_L_FAN4_6", + "CMT_TOP_FAN4_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_11", + "CMT_TOP_LOGIC_OUTS_L_B12_12" + ], + [ + "CMT_FIFO_ER1BEG0_1", + "CMT_TOP_ER1BEG0_2" + ], + [ + "CMT_FIFO_WW2END3_10", + "CMT_TOP_WW2END3_11" + ], + [ + "CMT_FIFO_L_IMUX8_3", + "CMT_TOP_IMUX8_4" + ], + [ + "CMT_FIFO_SE2A2_3", + "CMT_TOP_SE2A2_4" + ], + [ + "CMT_FIFO_SE2A1_2", + "CMT_TOP_SE2A1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_3", + "CMT_TOP_LOGIC_OUTS_L_B15_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_10", + "CMT_TOP_LOGIC_OUTS_L_B4_11" + ], + [ + "CMT_FIFO_SE4BEG0_1", + "CMT_TOP_SE4BEG0_2" + ], + [ + "CMT_FIFO_SW4END0_6", + "CMT_TOP_SW4END0_7" + ], + [ + "CMT_FIFO_NE4C2_7", + "CMT_TOP_NE4C2_8" + ], + [ + "CMT_FIFO_WL1END1_3", + "CMT_TOP_WL1END1_4" + ], + [ + "CMT_FIFO_EL1BEG3_10", + "CMT_TOP_EL1BEG3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_8", + "CMT_TOP_LOGIC_OUTS_L_B23_9" + ], + [ + "CMT_FIFO_L_IMUX23_1", + "CMT_TOP_IMUX23_2" + ], + [ + "CMT_FIFO_SW2A2_4", + "CMT_TOP_SW2A2_5" + ], + [ + "CMT_FIFO_L_IMUX1_9", + "CMT_TOP_IMUX1_10" + ], + [ + "CMT_FIFO_L_IMUX22_5", + "CMT_TOP_IMUX22_6" + ], + [ + "CMT_FIFO_L_FAN5_9", + "CMT_TOP_FAN5_10" + ], + [ + "CMT_FIFO_L_IMUX45_8", + "CMT_TOP_IMUX45_9" + ], + [ + "CMT_FIFO_L_BYP1_7", + "CMT_TOP_BYP1_8" + ], + [ + "CMT_FIFO_WR1END0_1", + "CMT_TOP_WR1END0_2" + ], + [ + "CMT_FIFO_NE4C0_6", + "CMT_TOP_NE4C0_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_9", + "CMT_TOP_LOGIC_OUTS_L_B8_10" + ], + [ + "CMT_FIFO_L_IMUX14_7", + "CMT_TOP_IMUX14_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_3", + "CMT_TOP_LOGIC_OUTS_L_B11_4" + ], + [ + "CMT_FIFO_L_IMUX33_8", + "CMT_TOP_IMUX33_9" + ], + [ + "CMT_FIFO_L_BYP7_2", + "CMT_TOP_BYP7_3" + ], + [ + "CMT_FIFO_NW4END3_6", + "CMT_TOP_NW4END3_7" + ], + [ + "CMT_FIFO_L_IMUX20_0", + "CMT_TOP_IMUX20_1" + ], + [ + "CMT_FIFO_WW2END3_4", + "CMT_TOP_WW2END3_5" + ], + [ + "CMT_FIFO_L_BYP0_5", + "CMT_TOP_BYP0_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "CMT_TOP_ICLK_3" + ], + [ + "CMT_FIFO_EE2BEG0_2", + "CMT_TOP_EE2BEG0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_4", + "CMT_TOP_LOGIC_OUTS_L_B10_5" + ], + [ + "CMT_FIFO_ER1BEG3_4", + "CMT_TOP_ER1BEG3_5" + ], + [ + "CMT_FIFO_NW2A2_5", + "CMT_TOP_NW2A2_6" + ], + [ + "CMT_FIFO_NE4C3_4", + "CMT_TOP_NE4C3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_10", + "CMT_TOP_LOGIC_OUTS_L_B20_11" + ], + [ + "CMT_FIFO_EE4B3_3", + "CMT_TOP_EE4B3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_3", + "CMT_TOP_LOGIC_OUTS_L_B8_4" + ], + [ + "CMT_FIFO_NW2A0_3", + "CMT_TOP_NW2A0_4" + ], + [ + "CMT_FIFO_L_BYP2_2", + "CMT_TOP_BYP2_3" + ], + [ + "CMT_FIFO_WW2END2_9", + "CMT_TOP_WW2END2_10" + ], + [ + "CMT_FIFO_NW4END0_8", + "CMT_TOP_NW4END0_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "CMT_TOP_ICLKDIV_7" + ], + [ + "CMT_FIFO_SE4C3_6", + "CMT_TOP_SE4C3_7" + ], + [ + "CMT_FIFO_SW4A1_5", + "CMT_TOP_SW4A1_6" + ], + [ + "CMT_FIFO_WW2END0_7", + "CMT_TOP_WW2END0_8" + ], + [ + "CMT_FIFO_SE4C2_5", + "CMT_TOP_SE4C2_6" + ], + [ + "CMT_FIFO_SE4BEG1_10", + "CMT_TOP_SE4BEG1_11" + ], + [ + "CMT_FIFO_NW4A2_6", + "CMT_TOP_NW4A2_7" + ], + [ + "CMT_FIFO_EE4A1_5", + "CMT_TOP_EE4A1_6" + ], + [ + "CMT_FIFO_NW4A3_6", + "CMT_TOP_NW4A3_7" + ], + [ + "CMT_FIFO_SW4END1_0", + "CMT_TOP_SW4END1_1" + ], + [ + "CMT_FIFO_L_IMUX4_10", + "CMT_TOP_IMUX4_11" + ], + [ + "CMT_FIFO_WR1END2_2", + "CMT_TOP_WR1END2_3" + ], + [ + "CMT_FIFO_NE4C1_1", + "CMT_TOP_NE4C1_2" + ], + [ + "CMT_FIFO_WW4B2_6", + "CMT_TOP_WW4B2_7" + ], + [ + "CMT_FIFO_L_BYP0_4", + "CMT_TOP_BYP0_5" + ], + [ + "CMT_FIFO_NW4END3_11", + "CMT_TOP_NW4END3_12" + ], + [ + "CMT_FIFO_EE4C2_4", + "CMT_TOP_EE4C2_5" + ], + [ + "CMT_FIFO_L_IMUX8_4", + "CMT_TOP_IMUX8_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "CMT_TOP_ICLK_9" + ], + [ + "CMT_FIFO_SE4C0_8", + "CMT_TOP_SE4C0_9" + ], + [ + "CMT_FIFO_NW2A2_10", + "CMT_TOP_NW2A2_11" + ], + [ + "CMT_FIFO_EE4A0_4", + "CMT_TOP_EE4A0_5" + ], + [ + "CMT_FIFO_L_BYP4_0", + "CMT_TOP_BYP4_1" + ], + [ + "CMT_FIFO_NW2A3_8", + "CMT_TOP_NW2A3_9" + ], + [ + "CMT_FIFO_EE2BEG3_9", + "CMT_TOP_EE2BEG3_10" + ], + [ + "CMT_FIFO_SE4C3_11", + "CMT_TOP_SE4C3_12" + ], + [ + "CMT_FIFO_WW4END3_10", + "CMT_TOP_WW4END3_11" + ], + [ + "CMT_FIFO_ER1BEG2_1", + "CMT_TOP_ER1BEG2_2" + ], + [ + "CMT_FIFO_NW4A2_10", + "CMT_TOP_NW4A2_11" + ], + [ + "CMT_FIFO_EE4BEG0_6", + "CMT_TOP_EE4BEG0_7" + ], + [ + "CMT_FIFO_L_IMUX30_10", + "CMT_TOP_IMUX30_11" + ], + [ + "CMT_FIFO_EE4B2_9", + "CMT_TOP_EE4B2_10" + ], + [ + "CMT_FIFO_SW4A2_8", + "CMT_TOP_SW4A2_9" + ], + [ + "CMT_FIFO_WW4A3_10", + "CMT_TOP_WW4A3_11" + ], + [ + "CMT_FIFO_NE4BEG1_6", + "CMT_TOP_NE4BEG1_7" + ], + [ + "CMT_FIFO_WR1END1_7", + "CMT_TOP_WR1END1_8" + ], + [ + "CMT_FIFO_L_BYP2_5", + "CMT_TOP_BYP2_6" + ], + [ + "CMT_FIFO_L_IMUX0_5", + "CMT_TOP_IMUX0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_6" + ], + [ + "CMT_FIFO_EE4C2_1", + "CMT_TOP_EE4C2_2" + ], + [ + "CMT_FIFO_EE4B1_1", + "CMT_TOP_EE4B1_2" + ], + [ + "CMT_FIFO_NW4A3_9", + "CMT_TOP_NW4A3_10" + ], + [ + "CMT_FIFO_SW4END3_6", + "CMT_TOP_SW4END3_7" + ], + [ + "CMT_FIFO_EE4A1_1", + "CMT_TOP_EE4A1_2" + ], + [ + "CMT_FIFO_EL1BEG0_1", + "CMT_TOP_EL1BEG0_2" + ], + [ + "CMT_FIFO_EE4A2_4", + "CMT_TOP_EE4A2_5" + ], + [ + "CMT_FIFO_L_IMUX32_0", + "CMT_TOP_IMUX32_1" + ], + [ + "CMT_FIFO_SE2A2_2", + "CMT_TOP_SE2A2_3" + ], + [ + "CMT_FIFO_L_IMUX14_2", + "CMT_TOP_IMUX14_3" + ], + [ + "CMT_FIFO_NE2A2_9", + "CMT_TOP_NE2A2_10" + ], + [ + "CMT_FIFO_EE4C0_8", + "CMT_TOP_EE4C0_9" + ], + [ + "CMT_FIFO_L_IMUX22_4", + "CMT_TOP_IMUX22_5" + ], + [ + "CMT_FIFO_WW4B1_9", + "CMT_TOP_WW4B1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_6", + "CMT_TOP_LOGIC_OUTS_L_B20_7" + ], + [ + "CMT_FIFO_NE4C3_1", + "CMT_TOP_NE4C3_2" + ], + [ + "CMT_FIFO_L_IMUX47_6", + "CMT_TOP_IMUX47_7" + ], + [ + "CMT_FIFO_L_IMUX45_7", + "CMT_TOP_IMUX45_8" + ], + [ + "CMT_FIFO_LH12_7", + "CMT_TOP_LH12_8" + ], + [ + "CMT_FIFO_EE2A2_11", + "CMT_TOP_EE2A2_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_4", + "CMT_TOP_LOGIC_OUTS_L_B4_5" + ], + [ + "CMT_FIFO_WW2A0_5", + "CMT_TOP_WW2A0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_0", + "CMT_TOP_LOGIC_OUTS_L_B9_1" + ], + [ + "CMT_FIFO_L_PHASER_RDENABLE", + "CMT_MMCM_A_RDEN_TOFIFO" + ], + [ + "CMT_FIFO_WW2END3_5", + "CMT_TOP_WW2END3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_7", + "CMT_TOP_LOGIC_OUTS_L_B5_8" + ], + [ + "CMT_FIFO_L_IMUX4_7", + "CMT_TOP_IMUX4_8" + ], + [ + "CMT_FIFO_L_FAN0_11", + "CMT_TOP_FAN0_12" + ], + [ + "CMT_FIFO_EE4A0_5", + "CMT_TOP_EE4A0_6" + ], + [ + "CMT_FIFO_L_IMUX23_5", + "CMT_TOP_IMUX23_6" + ], + [ + "CMT_FIFO_NW2A0_2", + "CMT_TOP_NW2A0_3" + ], + [ + "CMT_FIFO_EE2BEG0_1", + "CMT_TOP_EE2BEG0_2" + ], + [ + "CMT_FIFO_NE4BEG0_8", + "CMT_TOP_NE4BEG0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_7", + "CMT_TOP_LOGIC_OUTS_L_B20_8" + ], + [ + "CMT_FIFO_NW4A3_5", + "CMT_TOP_NW4A3_6" + ], + [ + "CMT_FIFO_NE4C3_7", + "CMT_TOP_NE4C3_8" + ], + [ + "CMT_FIFO_L_BYP6_10", + "CMT_TOP_BYP6_11" + ], + [ + "CMT_FIFO_L_IMUX46_5", + "CMT_TOP_IMUX46_6" + ], + [ + "CMT_FIFO_WW4END3_8", + "CMT_TOP_WW4END3_9" + ], + [ + "CMT_FIFO_NW4END3_2", + "CMT_TOP_NW4END3_3" + ], + [ + "CMT_FIFO_WW2END1_10", + "CMT_TOP_WW2END1_11" + ], + [ + "CMT_FIFO_ER1BEG2_8", + "CMT_TOP_ER1BEG2_9" + ], + [ + "CMT_FIFO_L_IMUX0_7", + "CMT_TOP_IMUX0_8" + ], + [ + "CMT_FIFO_L_IMUX40_10", + "CMT_TOP_IMUX40_11" + ], + [ + "CMT_FIFO_L_IMUX5_2", + "CMT_TOP_IMUX5_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "CMT_TOP_OCLKDIV_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_6", + "CMT_TOP_LOGIC_OUTS_L_B21_7" + ], + [ + "CMT_FIFO_EE4A3_6", + "CMT_TOP_EE4A3_7" + ], + [ + "CMT_FIFO_SE4BEG2_2", + "CMT_TOP_SE4BEG2_3" + ], + [ + "CMT_FIFO_L_IMUX38_9", + "CMT_TOP_IMUX38_10" + ], + [ + "CMT_FIFO_SW4A3_5", + "CMT_TOP_SW4A3_6" + ], + [ + "CMT_FIFO_SE4C3_7", + "CMT_TOP_SE4C3_8" + ], + [ + "CMT_FIFO_L_FAN4_9", + "CMT_TOP_FAN4_10" + ], + [ + "CMT_FIFO_WW2END0_4", + "CMT_TOP_WW2END0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_7", + "CMT_TOP_LOGIC_OUTS_L_B7_8" + ], + [ + "CMT_FIFO_L_IMUX31_6", + "CMT_TOP_IMUX31_7" + ], + [ + "CMT_FIFO_L_IMUX18_11", + "CMT_TOP_IMUX18_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_9", + "CMT_TOP_LOGIC_OUTS_L_B12_10" + ], + [ + "CMT_FIFO_LH1_0", + "CMT_TOP_LH1_1" + ], + [ + "CMT_FIFO_WW4END2_2", + "CMT_TOP_WW4END2_3" + ], + [ + "CMT_FIFO_L_IMUX45_9", + "CMT_TOP_IMUX45_10" + ], + [ + "CMT_FIFO_L_IMUX34_1", + "CMT_TOP_IMUX34_2" + ], + [ + "CMT_FIFO_L_FAN0_6", + "CMT_TOP_FAN0_7" + ], + [ + "CMT_FIFO_L_BYP3_11", + "CMT_TOP_BYP3_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_3", + "CMT_TOP_LOGIC_OUTS_L_B13_4" + ], + [ + "CMT_FIFO_WR1END1_6", + "CMT_TOP_WR1END1_7" + ], + [ + "CMT_FIFO_SE4BEG1_2", + "CMT_TOP_SE4BEG1_3" + ], + [ + "CMT_FIFO_WW4A0_7", + "CMT_TOP_WW4A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_5", + "CMT_TOP_LOGIC_OUTS_L_B20_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "CMT_TOP_OCLK_9" + ], + [ + "CMT_FIFO_L_IMUX19_8", + "CMT_TOP_IMUX19_9" + ], + [ + "CMT_FIFO_NE2A3_0", + "CMT_TOP_NE2A3_1" + ], + [ + "CMT_FIFO_SW4END2_4", + "CMT_TOP_SW4END2_5" + ], + [ + "CMT_FIFO_NW4END1_8", + "CMT_TOP_NW4END1_9" + ], + [ + "CMT_FIFO_SE2A1_9", + "CMT_TOP_SE2A1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_9", + "CMT_TOP_LOGIC_OUTS_L_B9_10" + ], + [ + "CMT_FIFO_WW2A1_11", + "CMT_TOP_WW2A1_12" + ], + [ + "CMT_FIFO_LH12_9", + "CMT_TOP_LH12_10" + ], + [ + "CMT_FIFO_LH8_2", + "CMT_TOP_LH8_3" + ], + [ + "CMT_FIFO_L_IMUX31_5", + "CMT_TOP_IMUX31_6" + ], + [ + "CMT_FIFO_L_BYP3_2", + "CMT_TOP_BYP3_3" + ], + [ + "CMT_FIFO_NE4C2_6", + "CMT_TOP_NE4C2_7" + ], + [ + "CMT_FIFO_LH9_0", + "CMT_TOP_LH9_1" + ], + [ + "CMT_FIFO_SW2A3_5", + "CMT_TOP_SW2A3_6" + ], + [ + "CMT_FIFO_L_IMUX11_11", + "CMT_TOP_IMUX11_12" + ], + [ + "CMT_FIFO_WW4C3_4", + "CMT_TOP_WW4C3_5" + ], + [ + "CMT_FIFO_WW4C3_10", + "CMT_TOP_WW4C3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_5", + "CMT_TOP_LOGIC_OUTS_L_B4_6" + ], + [ + "CMT_FIFO_LH6_9", + "CMT_TOP_LH6_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_4", + "CMT_TOP_LOGIC_OUTS_L_B23_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_2", + "CMT_TOP_LOGIC_OUTS_L_B5_3" + ], + [ + "CMT_FIFO_NE2A0_2", + "CMT_TOP_NE2A0_3" + ], + [ + "CMT_FIFO_NE4C0_9", + "CMT_TOP_NE4C0_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_8", + "CMT_TOP_LOGIC_OUTS_L_B10_9" + ], + [ + "CMT_FIFO_L_IMUX10_10", + "CMT_TOP_IMUX10_11" + ], + [ + "CMT_FIFO_SW4END1_9", + "CMT_TOP_SW4END1_10" + ], + [ + "CMT_FIFO_L_IMUX7_10", + "CMT_TOP_IMUX7_11" + ], + [ + "CMT_FIFO_L_IMUX20_3", + "CMT_TOP_IMUX20_4" + ], + [ + "CMT_FIFO_EE4BEG1_5", + "CMT_TOP_EE4BEG1_6" + ], + [ + "CMT_FIFO_NW2A1_2", + "CMT_TOP_NW2A1_3" + ], + [ + "CMT_FIFO_WW4B3_9", + "CMT_TOP_WW4B3_10" + ], + [ + "CMT_FIFO_LH10_3", + "CMT_TOP_LH10_4" + ], + [ + "CMT_FIFO_NE4C3_9", + "CMT_TOP_NE4C3_10" + ], + [ + "CMT_FIFO_EL1BEG0_5", + "CMT_TOP_EL1BEG0_6" + ], + [ + "CMT_FIFO_SW2A1_4", + "CMT_TOP_SW2A1_5" + ], + [ + "CMT_FIFO_L_IMUX43_7", + "CMT_TOP_IMUX43_8" + ], + [ + "CMT_FIFO_L_BYP6_2", + "CMT_TOP_BYP6_3" + ], + [ + "CMT_FIFO_WR1END3_0", + "CMT_TOP_WR1END3_1" + ], + [ + "CMT_FIFO_EE4C1_0", + "CMT_TOP_EE4C1_1" + ], + [ + "CMT_FIFO_LH6_11", + "CMT_TOP_LH6_12" + ], + [ + "CMT_FIFO_SE2A2_9", + "CMT_TOP_SE2A2_10" + ], + [ + "FIFO_DQS_IOTOPHASER_1", + "CMT_MMCM_DQS_TO_PHASERA" + ], + [ + "CMT_FIFO_L_IMUX0_3", + "CMT_TOP_IMUX0_4" + ], + [ + "CMT_FIFO_LH11_3", + "CMT_TOP_LH11_4" + ], + [ + "CMT_FIFO_LH2_10", + "CMT_TOP_LH2_11" + ], + [ + "CMT_FIFO_L_IMUX10_8", + "CMT_TOP_IMUX10_9" + ], + [ + "CMT_FIFO_WL1END1_9", + "CMT_TOP_WL1END1_10" + ], + [ + "CMT_FIFO_WW4C3_2", + "CMT_TOP_WW4C3_3" + ], + [ + "CMT_FIFO_L_IMUX37_6", + "CMT_TOP_IMUX37_7" + ], + [ + "CMT_FIFO_L_IMUX44_1", + "CMT_TOP_IMUX44_2" + ], + [ + "CMT_FIFO_EE2BEG2_7", + "CMT_TOP_EE2BEG2_8" + ], + [ + "CMT_FIFO_NE2A0_11", + "CMT_TOP_NE2A0_12" + ], + [ + "CMT_FIFO_L_IMUX41_6", + "CMT_TOP_IMUX41_7" + ], + [ + "CMT_FIFO_SE4BEG3_4", + "CMT_TOP_SE4BEG3_5" + ], + [ + "CMT_FIFO_L_IMUX26_7", + "CMT_TOP_IMUX26_8" + ], + [ + "CMT_FIFO_NE4BEG3_11", + "CMT_TOP_NE4BEG3_12" + ], + [ + "CMT_FIFO_L_IMUX12_11", + "CMT_TOP_IMUX12_12" + ], + [ + "CMT_FIFO_SW2A0_6", + "CMT_TOP_SW2A0_7" + ], + [ + "CMT_FIFO_EE4B3_5", + "CMT_TOP_EE4B3_6" + ], + [ + "CMT_FIFO_L_IMUX33_3", + "CMT_TOP_IMUX33_4" + ], + [ + "CMT_FIFO_EE2A2_4", + "CMT_TOP_EE2A2_5" + ], + [ + "CMT_FIFO_L_IMUX32_1", + "CMT_TOP_IMUX32_2" + ], + [ + "CMT_FIFO_WW4B3_1", + "CMT_TOP_WW4B3_2" + ], + [ + "CMT_FIFO_L_IMUX9_1", + "CMT_TOP_IMUX9_2" + ], + [ + "CMT_FIFO_SW4END2_8", + "CMT_TOP_SW4END2_9" + ], + [ + "CMT_FIFO_NW2A3_9", + "CMT_TOP_NW2A3_10" + ], + [ + "CMT_FIFO_WW4C2_4", + "CMT_TOP_WW4C2_5" + ], + [ + "CMT_FIFO_WW2END1_4", + "CMT_TOP_WW2END1_5" + ], + [ + "CMT_FIFO_SE4C0_6", + "CMT_TOP_SE4C0_7" + ], + [ + "CMT_FIFO_LH4_8", + "CMT_TOP_LH4_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_10", + "CMT_TOP_LOGIC_OUTS_L_B19_11" + ], + [ + "CMT_FIFO_EE4BEG2_5", + "CMT_TOP_EE4BEG2_6" + ], + [ + "CMT_FIFO_L_IMUX17_3", + "CMT_TOP_IMUX17_4" + ], + [ + "CMT_FIFO_WW4END3_7", + "CMT_TOP_WW4END3_8" + ], + [ + "CMT_FIFO_SE4C2_6", + "CMT_TOP_SE4C2_7" + ], + [ + "CMT_FIFO_L_IMUX47_10", + "CMT_TOP_IMUX47_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_6", + "CMT_TOP_LOGIC_OUTS_L_B10_7" + ], + [ + "CMT_FIFO_L_IMUX13_7", + "CMT_TOP_IMUX13_8" + ], + [ + "CMT_FIFO_ER1BEG0_10", + "CMT_TOP_ER1BEG0_11" + ], + [ + "CMT_FIFO_LH9_3", + "CMT_TOP_LH9_4" + ], + [ + "CMT_FIFO_L_IMUX45_11", + "CMT_TOP_IMUX45_12" + ], + [ + "CMT_FIFO_L_BYP6_8", + "CMT_TOP_BYP6_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_8", + "CMT_TOP_LOGIC_OUTS_L_B9_9" + ], + [ + "CMT_FIFO_WW4B3_8", + "CMT_TOP_WW4B3_9" + ], + [ + "CMT_FIFO_L_IMUX29_7", + "CMT_TOP_IMUX29_8" + ], + [ + "CMT_FIFO_ER1BEG3_5", + "CMT_TOP_ER1BEG3_6" + ], + [ + "CMT_FIFO_NW2A1_4", + "CMT_TOP_NW2A1_5" + ], + [ + "CMT_FIFO_L_IMUX35_7", + "CMT_TOP_IMUX35_8" + ], + [ + "CMT_FIFO_WW4A2_2", + "CMT_TOP_WW4A2_3" + ], + [ + "CMT_FIFO_L_IMUX10_9", + "CMT_TOP_IMUX10_10" + ], + [ + "CMT_FIFO_WL1END2_3", + "CMT_TOP_WL1END2_4" + ], + [ + "CMT_FIFO_WR1END1_0", + "CMT_TOP_WR1END1_1" + ], + [ + "CMT_FIFO_NE4C0_11", + "CMT_TOP_NE4C0_12" + ], + [ + "CMT_FIFO_ER1BEG0_8", + "CMT_TOP_ER1BEG0_9" + ], + [ + "CMT_FIFO_NW2A1_0", + "CMT_TOP_NW2A1_1" + ], + [ + "CMT_FIFO_L_IMUX19_2", + "CMT_TOP_IMUX19_3" + ], + [ + "CMT_FIFO_LH12_1", + "CMT_TOP_LH12_2" + ], + [ + "CMT_FIFO_WW2END2_1", + "CMT_TOP_WW2END2_2" + ], + [ + "CMT_FIFO_L_CLK0_0", + "CMT_TOP_CLK0_1" + ], + [ + "CMT_FIFO_L_IMUX21_11", + "CMT_TOP_IMUX21_12" + ], + [ + "CMT_FIFO_LH8_11", + "CMT_TOP_LH8_12" + ], + [ + "CMT_FIFO_L_IMUX32_9", + "CMT_TOP_IMUX32_10" + ], + [ + "CMT_FIFO_WW4B1_8", + "CMT_TOP_WW4B1_9" + ], + [ + "CMT_FIFO_NE2A2_10", + "CMT_TOP_NE2A2_11" + ], + [ + "CMT_FIFO_EE4BEG3_1", + "CMT_TOP_EE4BEG3_2" + ], + [ + "CMT_FIFO_L_BYP2_9", + "CMT_TOP_BYP2_10" + ], + [ + "CMT_FIFO_L_IMUX41_8", + "CMT_TOP_IMUX41_9" + ], + [ + "CMT_FIFO_L_IMUX24_7", + "CMT_TOP_IMUX24_8" + ], + [ + "CMT_FIFO_ER1BEG1_3", + "CMT_TOP_ER1BEG1_4" + ], + [ + "CMT_FIFO_L_FAN7_2", + "CMT_TOP_FAN7_3" + ], + [ + "CMT_FIFO_SW4A3_7", + "CMT_TOP_SW4A3_8" + ], + [ + "CMT_FIFO_L_IMUX5_0", + "CMT_TOP_IMUX5_1" + ], + [ + "CMT_FIFO_WW4END1_5", + "CMT_TOP_WW4END1_6" + ], + [ + "CMT_FIFO_SE4BEG2_11", + "CMT_TOP_SE4BEG2_12" + ], + [ + "CMT_FIFO_WW2END2_8", + "CMT_TOP_WW2END2_9" + ], + [ + "CMT_FIFO_WW4B0_1", + "CMT_TOP_WW4B0_2" + ], + [ + "CMT_FIFO_EE2A2_3", + "CMT_TOP_EE2A2_4" + ], + [ + "CMT_FIFO_EE4A2_0", + "CMT_TOP_EE4A2_1" + ], + [ + "CMT_FIFO_SW4END2_0", + "CMT_TOP_SW4END2_1" + ], + [ + "CMT_FIFO_SE4C0_11", + "CMT_TOP_SE4C0_12" + ], + [ + "CMT_FIFO_EE4A0_10", + "CMT_TOP_EE4A0_11" + ], + [ + "CMT_FIFO_L_IMUX3_5", + "CMT_TOP_IMUX3_6" + ], + [ + "CMT_FIFO_NW4A1_2", + "CMT_TOP_NW4A1_3" + ], + [ + "CMT_FIFO_WR1END2_9", + "CMT_TOP_WR1END2_10" + ], + [ + "CMT_FIFO_SE4C1_1", + "CMT_TOP_SE4C1_2" + ], + [ + "CMT_FIFO_L_IMUX23_2", + "CMT_TOP_IMUX23_3" + ], + [ + "CMT_FIFO_WW2A0_10", + "CMT_TOP_WW2A0_11" + ], + [ + "CMT_FIFO_ER1BEG2_11", + "CMT_TOP_ER1BEG2_12" + ], + [ + "CMT_FIFO_EE4BEG3_7", + "CMT_TOP_EE4BEG3_8" + ], + [ + "CMT_FIFO_WW4B0_10", + "CMT_TOP_WW4B0_11" + ], + [ + "CMT_FIFO_SE4BEG3_5", + "CMT_TOP_SE4BEG3_6" + ], + [ + "CMT_FIFO_EE2A1_5", + "CMT_TOP_EE2A1_6" + ], + [ + "CMT_FIFO_EE4A0_7", + "CMT_TOP_EE4A0_8" + ], + [ + "CMT_FIFO_L_IMUX14_0", + "CMT_TOP_IMUX14_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "CMT_TOP_ICLK_10" + ], + [ + "CMT_FIFO_L_IMUX46_3", + "CMT_TOP_IMUX46_4" + ], + [ + "CMT_FIFO_ER1BEG1_10", + "CMT_TOP_ER1BEG1_11" + ], + [ + "CMT_FIFO_EL1BEG2_1", + "CMT_TOP_EL1BEG2_2" + ], + [ + "CMT_FIFO_LH2_4", + "CMT_TOP_LH2_5" + ], + [ + "CMT_FIFO_L_BYP3_7", + "CMT_TOP_BYP3_8" + ], + [ + "CMT_FIFO_L_BYP7_0", + "CMT_TOP_BYP7_1" + ], + [ + "CMT_FIFO_WR1END2_1", + "CMT_TOP_WR1END2_2" + ], + [ + "CMT_FIFO_SE2A3_4", + "CMT_TOP_SE2A3_5" + ], + [ + "CMT_FIFO_EE2BEG0_4", + "CMT_TOP_EE2BEG0_5" + ], + [ + "CMT_FIFO_L_FAN1_2", + "CMT_TOP_FAN1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_3", + "CMT_TOP_LOGIC_OUTS_L_B20_4" + ], + [ + "CMT_FIFO_L_IMUX16_2", + "CMT_TOP_IMUX16_3" + ], + [ + "CMT_FIFO_EE4BEG3_10", + "CMT_TOP_EE4BEG3_11" + ], + [ + "CMT_FIFO_NW2A1_3", + "CMT_TOP_NW2A1_4" + ], + [ + "CMT_FIFO_L_IMUX2_4", + "CMT_TOP_IMUX2_5" + ], + [ + "CMT_FIFO_L_IMUX12_9", + "CMT_TOP_IMUX12_10" + ], + [ + "CMT_FIFO_ER1BEG0_4", + "CMT_TOP_ER1BEG0_5" + ], + [ + "CMT_FIFO_L_BYP0_8", + "CMT_TOP_BYP0_9" + ], + [ + "CMT_FIFO_L_CTRL0_1", + "CMT_TOP_CTRL0_2" + ], + [ + "CMT_FIFO_L_FAN0_9", + "CMT_TOP_FAN0_10" + ], + [ + "CMT_FIFO_EE4B1_11", + "CMT_TOP_EE4B1_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_9", + "CMT_TOP_LOGIC_OUTS_L_B19_10" + ], + [ + "CMT_FIFO_L_IMUX34_5", + "CMT_TOP_IMUX34_6" + ], + [ + "CMT_FIFO_L_IMUX41_10", + "CMT_TOP_IMUX41_11" + ], + [ + "CMT_FIFO_LH5_10", + "CMT_TOP_LH5_11" + ], + [ + "CMT_FIFO_ER1BEG2_6", + "CMT_TOP_ER1BEG2_7" + ], + [ + "CMT_FIFO_L_IMUX27_8", + "CMT_TOP_IMUX27_9" + ], + [ + "CMT_FIFO_WW2A1_2", + "CMT_TOP_WW2A1_3" + ], + [ + "CMT_FIFO_NE4BEG1_11", + "CMT_TOP_NE4BEG1_12" + ], + [ + "CMT_FIFO_MONITOR_N_10", + "CMT_TOP_MONITOR_N_11" + ], + [ + "CMT_FIFO_L_CLK1_10", + "CMT_TOP_CLK1_11" + ], + [ + "CMT_FIFO_L_IMUX15_2", + "CMT_TOP_IMUX15_3" + ], + [ + "CMT_FIFO_EL1BEG0_7", + "CMT_TOP_EL1BEG0_8" + ], + [ + "CMT_FIFO_EE4BEG0_0", + "CMT_TOP_EE4BEG0_1" + ], + [ + "CMT_FIFO_L_BYP1_3", + "CMT_TOP_BYP1_4" + ], + [ + "CMT_FIFO_WW2A1_5", + "CMT_TOP_WW2A1_6" + ], + [ + "CMT_FIFO_EE4A2_10", + "CMT_TOP_EE4A2_11" + ], + [ + "CMT_FIFO_SE4BEG1_0", + "CMT_TOP_SE4BEG1_1" + ], + [ + "CMT_FIFO_L_FAN4_4", + "CMT_TOP_FAN4_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_5", + "CMT_TOP_LOGIC_OUTS_L_B8_6" + ], + [ + "CMT_FIFO_EE4A3_4", + "CMT_TOP_EE4A3_5" + ], + [ + "CMT_FIFO_L_FAN5_3", + "CMT_TOP_FAN5_4" + ], + [ + "CMT_FIFO_LH11_0", + "CMT_TOP_LH11_1" + ], + [ + "CMT_FIFO_L_IMUX3_9", + "CMT_TOP_IMUX3_10" + ], + [ + "CMT_FIFO_EE4BEG3_8", + "CMT_TOP_EE4BEG3_9" + ], + [ + "CMT_FIFO_L_IMUX22_8", + "CMT_TOP_IMUX22_9" + ], + [ + "CMT_FIFO_LH6_7", + "CMT_TOP_LH6_8" + ], + [ + "CMT_FIFO_L_FAN6_11", + "CMT_TOP_FAN6_12" + ], + [ + "CMT_FIFO_WW4B0_4", + "CMT_TOP_WW4B0_5" + ], + [ + "CMT_FIFO_L_IMUX10_0", + "CMT_TOP_IMUX10_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_9", + "CMT_TOP_LOGIC_OUTS_L_B5_10" + ], + [ + "CMT_FIFO_EE4A3_5", + "CMT_TOP_EE4A3_6" + ], + [ + "CMT_FIFO_ER1BEG1_0", + "CMT_TOP_ER1BEG1_1" + ], + [ + "CMT_FIFO_WW4C0_5", + "CMT_TOP_WW4C0_6" + ], + [ + "CMT_FIFO_L_IMUX14_1", + "CMT_TOP_IMUX14_2" + ], + [ + "CMT_FIFO_NE4C3_6", + "CMT_TOP_NE4C3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_8", + "CMT_TOP_LOGIC_OUTS_L_B15_9" + ], + [ + "CMT_FIFO_WW2END2_2", + "CMT_TOP_WW2END2_3" + ], + [ + "CMT_FIFO_EE2BEG3_1", + "CMT_TOP_EE2BEG3_2" + ], + [ + "CMT_FIFO_NE4C0_4", + "CMT_TOP_NE4C0_5" + ], + [ + "CMT_FIFO_NW4A0_10", + "CMT_TOP_NW4A0_11" + ], + [ + "CMT_FIFO_L_IMUX27_11", + "CMT_TOP_IMUX27_12" + ], + [ + "CMT_FIFO_NW4END0_7", + "CMT_TOP_NW4END0_8" + ], + [ + "CMT_FIFO_SE4BEG0_9", + "CMT_TOP_SE4BEG0_10" + ], + [ + "CMT_FIFO_WW2A2_11", + "CMT_TOP_WW2A2_12" + ], + [ + "CMT_FIFO_L_BYP3_0", + "CMT_TOP_BYP3_1" + ], + [ + "CMT_FIFO_L_IMUX17_4", + "CMT_TOP_IMUX17_5" + ], + [ + "CMT_FIFO_LH8_3", + "CMT_TOP_LH8_4" + ], + [ + "CMT_FIFO_SW4END0_3", + "CMT_TOP_SW4END0_4" + ], + [ + "CMT_FIFO_NW2A3_1", + "CMT_TOP_NW2A3_2" + ], + [ + "CMT_FIFO_L_IMUX27_7", + "CMT_TOP_IMUX27_8" + ], + [ + "CMT_FIFO_EE4A1_0", + "CMT_TOP_EE4A1_1" + ], + [ + "CMT_FIFO_WW4A2_3", + "CMT_TOP_WW4A2_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "CMT_TOP_ICLK_7" + ], + [ + "CMT_FIFO_L_IMUX0_2", + "CMT_TOP_IMUX0_3" + ], + [ + "CMT_FIFO_WW4C1_2", + "CMT_TOP_WW4C1_3" + ], + [ + "CMT_FIFO_EE4B1_4", + "CMT_TOP_EE4B1_5" + ], + [ + "CMT_FIFO_WW2A1_10", + "CMT_TOP_WW2A1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_4", + "CMT_TOP_LOGIC_OUTS_L_B13_5" + ], + [ + "CMT_FIFO_SE2A1_5", + "CMT_TOP_SE2A1_6" + ], + [ + "CMT_FIFO_NE4BEG0_10", + "CMT_TOP_NE4BEG0_11" + ], + [ + "CMT_FIFO_EE4C1_9", + "CMT_TOP_EE4C1_10" + ], + [ + "CMT_FIFO_LH11_4", + "CMT_TOP_LH11_5" + ], + [ + "CMT_FIFO_WW4END0_1", + "CMT_TOP_WW4END0_2" + ], + [ + "CMT_FIFO_EL1BEG0_10", + "CMT_TOP_EL1BEG0_11" + ], + [ + "CMT_FIFO_EE4C2_2", + "CMT_TOP_EE4C2_3" + ], + [ + "CMT_FIFO_L_FAN3_11", + "CMT_TOP_FAN3_12" + ], + [ + "CMT_FIFO_L_BYP0_11", + "CMT_TOP_BYP0_12" + ], + [ + "CMT_FIFO_L_IMUX38_4", + "CMT_TOP_IMUX38_5" + ], + [ + "CMT_FIFO_NE2A0_3", + "CMT_TOP_NE2A0_4" + ], + [ + "CMT_FIFO_LH5_3", + "CMT_TOP_LH5_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_4" + ], + [ + "CMT_FIFO_NE2A2_1", + "CMT_TOP_NE2A2_2" + ], + [ + "CMT_FIFO_LH2_11", + "CMT_TOP_LH2_12" + ], + [ + "CMT_FIFO_L_FAN6_4", + "CMT_TOP_FAN6_5" + ], + [ + "CMT_FIFO_EE4B3_4", + "CMT_TOP_EE4B3_5" + ], + [ + "CMT_FIFO_SW4END2_3", + "CMT_TOP_SW4END2_4" + ], + [ + "CMT_FIFO_L_CLK0_11", + "CMT_TOP_CLK0_12" + ], + [ + "CMT_FIFO_EE4B1_3", + "CMT_TOP_EE4B1_4" + ], + [ + "CMT_FIFO_L_FAN3_2", + "CMT_TOP_FAN3_3" + ], + [ + "CMT_FIFO_SW4A1_8", + "CMT_TOP_SW4A1_9" + ], + [ + "CMT_FIFO_LH8_9", + "CMT_TOP_LH8_10" + ], + [ + "CMT_FIFO_L_BYP4_11", + "CMT_TOP_BYP4_12" + ], + [ + "CMT_FIFO_NE2A1_1", + "CMT_TOP_NE2A1_2" + ], + [ + "CMT_FIFO_EE2BEG2_6", + "CMT_TOP_EE2BEG2_7" + ], + [ + "CMT_FIFO_WW2A2_4", + "CMT_TOP_WW2A2_5" + ], + [ + "CMT_FIFO_WW2END1_7", + "CMT_TOP_WW2END1_8" + ], + [ + "CMT_FIFO_L_BYP0_7", + "CMT_TOP_BYP0_8" + ], + [ + "CMT_FIFO_SW4END2_11", + "CMT_TOP_SW4END2_12" + ], + [ + "CMT_FIFO_NE4C2_10", + "CMT_TOP_NE4C2_11" + ], + [ + "CMT_FIFO_L_FAN5_11", + "CMT_TOP_FAN5_12" + ], + [ + "CMT_FIFO_SW2A1_1", + "CMT_TOP_SW2A1_2" + ], + [ + "CMT_FIFO_WW4END0_11", + "CMT_TOP_WW4END0_12" + ], + [ + "CMT_FIFO_SE4C1_3", + "CMT_TOP_SE4C1_4" + ], + [ + "CMT_FIFO_NE4BEG1_7", + "CMT_TOP_NE4BEG1_8" + ], + [ + "CMT_FIFO_NE2A0_4", + "CMT_TOP_NE2A0_5" + ], + [ + "CMT_FIFO_NE2A1_6", + "CMT_TOP_NE2A1_7" + ], + [ + "CMT_FIFO_WW2A2_3", + "CMT_TOP_WW2A2_4" + ], + [ + "CMT_FIFO_WL1END3_9", + "CMT_TOP_WL1END3_10" + ], + [ + "CMT_FIFO_L_IMUX27_5", + "CMT_TOP_IMUX27_6" + ], + [ + "CMT_FIFO_L_IMUX38_8", + "CMT_TOP_IMUX38_9" + ], + [ + "CMT_FIFO_WW4C3_9", + "CMT_TOP_WW4C3_10" + ], + [ + "CMT_FIFO_EL1BEG2_2", + "CMT_TOP_EL1BEG2_3" + ], + [ + "CMT_FIFO_SE4C0_7", + "CMT_TOP_SE4C0_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "CMT_TOP_ICLK_12" + ], + [ + "CMT_FIFO_EE4BEG2_3", + "CMT_TOP_EE4BEG2_4" + ], + [ + "CMT_FIFO_L_IMUX39_8", + "CMT_TOP_IMUX39_9" + ], + [ + "CMT_FIFO_WW4A1_10", + "CMT_TOP_WW4A1_11" + ], + [ + "CMT_FIFO_L_IMUX1_7", + "CMT_TOP_IMUX1_8" + ], + [ + "CMT_FIFO_WW4C2_0", + "CMT_TOP_WW4C2_1" + ], + [ + "CMT_FIFO_EE2A2_6", + "CMT_TOP_EE2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_0", + "CMT_TOP_LOGIC_OUTS_L_B20_1" + ], + [ + "CMT_FIFO_L_IMUX11_4", + "CMT_TOP_IMUX11_5" + ], + [ + "CMT_FIFO_L_IMUX29_8", + "CMT_TOP_IMUX29_9" + ], + [ + "CMT_FIFO_L_BYP5_1", + "CMT_TOP_BYP5_2" + ], + [ + "CMT_FIFO_L_IMUX23_11", + "CMT_TOP_IMUX23_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_5", + "CMT_TOP_LOGIC_OUTS_L_B12_6" + ], + [ + "CMT_FIFO_LH4_1", + "CMT_TOP_LH4_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_7", + "CMT_TOP_LOGIC_OUTS_L_B16_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_0", + "CMT_TOP_LOGIC_OUTS_L_B21_1" + ], + [ + "CMT_FIFO_EE4A0_8", + "CMT_TOP_EE4A0_9" + ], + [ + "CMT_FIFO_L_IMUX17_0", + "CMT_TOP_IMUX17_1" + ], + [ + "CMT_FIFO_NE4BEG3_2", + "CMT_TOP_NE4BEG3_3" + ], + [ + "CMT_FIFO_WW2A0_2", + "CMT_TOP_WW2A0_3" + ], + [ + "CMT_FIFO_WW4B1_10", + "CMT_TOP_WW4B1_11" + ], + [ + "CMT_FIFO_LH12_4", + "CMT_TOP_LH12_5" + ], + [ + "CMT_FIFO_EE4B0_5", + "CMT_TOP_EE4B0_6" + ], + [ + "CMT_FIFO_L_IMUX25_11", + "CMT_TOP_IMUX25_12" + ], + [ + "CMT_FIFO_NE2A2_6", + "CMT_TOP_NE2A2_7" + ], + [ + "CMT_FIFO_WW4C2_1", + "CMT_TOP_WW4C2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_3", + "CMT_TOP_LOGIC_OUTS_L_B17_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_6", + "CMT_TOP_LOGIC_OUTS_L_B3_7" + ], + [ + "CMT_FIFO_WW4B0_0", + "CMT_TOP_WW4B0_1" + ], + [ + "CMT_FIFO_EE4C1_7", + "CMT_TOP_EE4C1_8" + ], + [ + "CMT_FIFO_L_IMUX5_3", + "CMT_TOP_IMUX5_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_8", + "CMT_TOP_LOGIC_OUTS_L_B18_9" + ], + [ + "CMT_FIFO_ER1BEG2_3", + "CMT_TOP_ER1BEG2_4" + ], + [ + "CMT_FIFO_EL1BEG0_8", + "CMT_TOP_EL1BEG0_9" + ], + [ + "CMT_FIFO_WR1END0_9", + "CMT_TOP_WR1END0_10" + ], + [ + "CMT_FIFO_WW2A0_7", + "CMT_TOP_WW2A0_8" + ], + [ + "CMT_FIFO_ER1BEG0_6", + "CMT_TOP_ER1BEG0_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "CMT_TOP_OCLKDIV_5" + ], + [ + "CMT_FIFO_L_BYP1_5", + "CMT_TOP_BYP1_6" + ], + [ + "CMT_FIFO_L_IMUX14_5", + "CMT_TOP_IMUX14_6" + ], + [ + "CMT_FIFO_WR1END0_4", + "CMT_TOP_WR1END0_5" + ], + [ + "CMT_FIFO_L_IMUX16_4", + "CMT_TOP_IMUX16_5" + ], + [ + "CMT_FIFO_LH9_9", + "CMT_TOP_LH9_10" + ], + [ + "CMT_FIFO_L_IMUX19_10", + "CMT_TOP_IMUX19_11" + ], + [ + "CMT_FIFO_EE4A3_7", + "CMT_TOP_EE4A3_8" + ], + [ + "CMT_FIFO_L_FAN7_8", + "CMT_TOP_FAN7_9" + ], + [ + "CMT_FIFO_L_IMUX7_9", + "CMT_TOP_IMUX7_10" + ], + [ + "CMT_FIFO_L_IMUX15_4", + "CMT_TOP_IMUX15_5" + ], + [ + "CMT_FIFO_WW4B1_3", + "CMT_TOP_WW4B1_4" + ], + [ + "CMT_FIFO_EE2A0_9", + "CMT_TOP_EE2A0_10" + ], + [ + "CMT_FIFO_L_FAN7_10", + "CMT_TOP_FAN7_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_2", + "CMT_TOP_LOGIC_OUTS_L_B0_3" + ], + [ + "CMT_FIFO_WW2END0_9", + "CMT_TOP_WW2END0_10" + ], + [ + "CMT_FIFO_WW4C0_0", + "CMT_TOP_WW4C0_1" + ], + [ + "CMT_FIFO_L_IMUX9_0", + "CMT_TOP_IMUX9_1" + ], + [ + "CMT_FIFO_NE4C1_11", + "CMT_TOP_NE4C1_12" + ], + [ + "CMT_FIFO_L_FAN0_10", + "CMT_TOP_FAN0_11" + ], + [ + "CMT_FIFO_L_BYP1_11", + "CMT_TOP_BYP1_12" + ], + [ + "CMT_FIFO_NE4BEG1_1", + "CMT_TOP_NE4BEG1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_0", + "CMT_TOP_LOGIC_OUTS_L_B18_1" + ], + [ + "CMT_FIFO_NW2A1_10", + "CMT_TOP_NW2A1_11" + ], + [ + "CMT_FIFO_EE2A1_8", + "CMT_TOP_EE2A1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_6", + "CMT_TOP_LOGIC_OUTS_L_B15_7" + ], + [ + "CMT_FIFO_L_FAN4_3", + "CMT_TOP_FAN4_4" + ], + [ + "CMT_FIFO_WL1END0_0", + "CMT_TOP_WL1END0_1" + ], + [ + "CMT_FIFO_ER1BEG1_9", + "CMT_TOP_ER1BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX44_6", + "CMT_TOP_IMUX44_7" + ], + [ + "CMT_FIFO_EE2BEG3_2", + "CMT_TOP_EE2BEG3_3" + ], + [ + "CMT_FIFO_L_BYP1_8", + "CMT_TOP_BYP1_9" + ], + [ + "CMT_FIFO_NW4END1_10", + "CMT_TOP_NW4END1_11" + ], + [ + "CMT_FIFO_WR1END0_10", + "CMT_TOP_WR1END0_11" + ], + [ + "CMT_FIFO_L_IMUX2_5", + "CMT_TOP_IMUX2_6" + ], + [ + "CMT_FIFO_L_CTRL1_0", + "CMT_TOP_CTRL1_1" + ], + [ + "CMT_FIFO_WW4B1_7", + "CMT_TOP_WW4B1_8" + ], + [ + "CMT_FIFO_L_BYP7_5", + "CMT_TOP_BYP7_6" + ], + [ + "CMT_FIFO_SE2A3_0", + "CMT_TOP_SE2A3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_1", + "CMT_TOP_LOGIC_OUTS_L_B20_2" + ], + [ + "CMT_FIFO_EE2BEG3_0", + "CMT_TOP_EE2BEG3_1" + ], + [ + "CMT_FIFO_WR1END3_3", + "CMT_TOP_WR1END3_4" + ], + [ + "CMT_FIFO_L_IMUX16_6", + "CMT_TOP_IMUX16_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_0", + "CMT_TOP_LOGIC_OUTS_L_B12_1" + ], + [ + "CMT_FIFO_L_FAN4_8", + "CMT_TOP_FAN4_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_0", + "CMT_TOP_LOGIC_OUTS_L_B8_1" + ], + [ + "CMT_FIFO_EE4C1_3", + "CMT_TOP_EE4C1_4" + ], + [ + "CMT_FIFO_WL1END3_11", + "CMT_TOP_WL1END3_12" + ], + [ + "CMT_FIFO_LH2_5", + "CMT_TOP_LH2_6" + ], + [ + "CMT_FIFO_NE4BEG0_5", + "CMT_TOP_NE4BEG0_6" + ], + [ + "CMT_FIFO_EE2BEG2_2", + "CMT_TOP_EE2BEG2_3" + ], + [ + "CMT_FIFO_WL1END1_2", + "CMT_TOP_WL1END1_3" + ], + [ + "CMT_FIFO_EL1BEG3_9", + "CMT_TOP_EL1BEG3_10" + ], + [ + "CMT_FIFO_NW4A1_4", + "CMT_TOP_NW4A1_5" + ], + [ + "CMT_FIFO_L_CLK0_5", + "CMT_TOP_CLK0_6" + ], + [ + "CMT_FIFO_EE2BEG1_3", + "CMT_TOP_EE2BEG1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_2", + "CMT_TOP_LOGIC_OUTS_L_B11_3" + ], + [ + "CMT_FIFO_L_FAN3_9", + "CMT_TOP_FAN3_10" + ], + [ + "CMT_FIFO_L_CLK1_1", + "CMT_TOP_CLK1_2" + ], + [ + "CMT_FIFO_EE4C1_8", + "CMT_TOP_EE4C1_9" + ], + [ + "CMT_FIFO_L_IMUX7_2", + "CMT_TOP_IMUX7_3" + ], + [ + "CMT_FIFO_L_IMUX10_7", + "CMT_TOP_IMUX10_8" + ], + [ + "CMT_FIFO_WW4END3_6", + "CMT_TOP_WW4END3_7" + ], + [ + "CMT_FIFO_L_IMUX24_2", + "CMT_TOP_IMUX24_3" + ], + [ + "CMT_FIFO_NE4C1_7", + "CMT_TOP_NE4C1_8" + ], + [ + "CMT_FIFO_L_IMUX12_6", + "CMT_TOP_IMUX12_7" + ], + [ + "CMT_FIFO_L_IMUX26_6", + "CMT_TOP_IMUX26_7" + ], + [ + "CMT_FIFO_L_IMUX21_1", + "CMT_TOP_IMUX21_2" + ], + [ + "CMT_FIFO_L_IMUX12_10", + "CMT_TOP_IMUX12_11" + ], + [ + "CMT_FIFO_EE4BEG2_9", + "CMT_TOP_EE4BEG2_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_0", + "CMT_TOP_LOGIC_OUTS_L_B19_1" + ], + [ + "CMT_FIFO_NW4A0_2", + "CMT_TOP_NW4A0_3" + ], + [ + "CMT_FIFO_NE4C1_4", + "CMT_TOP_NE4C1_5" + ], + [ + "CMT_FIFO_EE4B2_1", + "CMT_TOP_EE4B2_2" + ], + [ + "CMT_FIFO_EE4B3_2", + "CMT_TOP_EE4B3_3" + ], + [ + "CMT_FIFO_L_BYP7_3", + "CMT_TOP_BYP7_4" + ], + [ + "CMT_FIFO_L_IMUX31_11", + "CMT_TOP_IMUX31_12" + ], + [ + "CMT_FIFO_EL1BEG1_0", + "CMT_TOP_EL1BEG1_1" + ], + [ + "CMT_FIFO_SW2A0_5", + "CMT_TOP_SW2A0_6" + ], + [ + "CMT_FIFO_NW4END0_1", + "CMT_TOP_NW4END0_2" + ], + [ + "CMT_FIFO_NE2A3_1", + "CMT_TOP_NE2A3_2" + ], + [ + "CMT_FIFO_WW4A2_1", + "CMT_TOP_WW4A2_2" + ], + [ + "CMT_FIFO_LH9_7", + "CMT_TOP_LH9_8" + ], + [ + "CMT_FIFO_NE4BEG0_3", + "CMT_TOP_NE4BEG0_4" + ], + [ + "CMT_FIFO_WR1END3_11", + "CMT_TOP_WR1END3_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_4", + "CMT_TOP_LOGIC_OUTS_L_B0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_7", + "CMT_TOP_LOGIC_OUTS_L_B1_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "CMT_TOP_OCLKDIV_4" + ], + [ + "CMT_FIFO_L_IMUX20_5", + "CMT_TOP_IMUX20_6" + ], + [ + "CMT_FIFO_WW4B1_1", + "CMT_TOP_WW4B1_2" + ], + [ + "CMT_FIFO_L_IMUX25_3", + "CMT_TOP_IMUX25_4" + ], + [ + "CMT_FIFO_L_BYP1_2", + "CMT_TOP_BYP1_3" + ], + [ + "CMT_FIFO_SW4END0_9", + "CMT_TOP_SW4END0_10" + ], + [ + "CMT_FIFO_WW4C1_4", + "CMT_TOP_WW4C1_5" + ], + [ + "CMT_FIFO_NW4A0_11", + "CMT_TOP_NW4A0_12" + ], + [ + "CMT_FIFO_L_IMUX10_6", + "CMT_TOP_IMUX10_7" + ], + [ + "CMT_FIFO_LH11_2", + "CMT_TOP_LH11_3" + ], + [ + "CMT_FIFO_SE4BEG0_0", + "CMT_TOP_SE4BEG0_1" + ], + [ + "CMT_FIFO_L_BYP2_7", + "CMT_TOP_BYP2_8" + ], + [ + "CMT_FIFO_LH4_0", + "CMT_TOP_LH4_1" + ], + [ + "CMT_FIFO_L_FAN2_3", + "CMT_TOP_FAN2_4" + ], + [ + "CMT_FIFO_L_IMUX3_11", + "CMT_TOP_IMUX3_12" + ], + [ + "CMT_FIFO_L_IMUX14_4", + "CMT_TOP_IMUX14_5" + ], + [ + "CMT_FIFO_L_IMUX35_11", + "CMT_TOP_IMUX35_12" + ], + [ + "CMT_FIFO_L_IMUX2_0", + "CMT_TOP_IMUX2_1" + ], + [ + "CMT_FIFO_NE4BEG2_6", + "CMT_TOP_NE4BEG2_7" + ], + [ + "CMT_FIFO_EE2BEG3_3", + "CMT_TOP_EE2BEG3_4" + ], + [ + "CMT_FIFO_WR1END1_3", + "CMT_TOP_WR1END1_4" + ], + [ + "CMT_FIFO_WR1END1_11", + "CMT_TOP_WR1END1_12" + ], + [ + "CMT_FIFO_L_FAN2_7", + "CMT_TOP_FAN2_8" + ], + [ + "CMT_FIFO_WR1END2_10", + "CMT_TOP_WR1END2_11" + ], + [ + "CMT_FIFO_L_IMUX28_4", + "CMT_TOP_IMUX28_5" + ], + [ + "CMT_FIFO_LH3_7", + "CMT_TOP_LH3_8" + ], + [ + "CMT_FIFO_L_IMUX4_4", + "CMT_TOP_IMUX4_5" + ], + [ + "CMT_FIFO_EE4BEG0_3", + "CMT_TOP_EE4BEG0_4" + ], + [ + "CMT_FIFO_L_IMUX28_9", + "CMT_TOP_IMUX28_10" + ], + [ + "CMT_FIFO_L_BYP7_1", + "CMT_TOP_BYP7_2" + ], + [ + "CMT_FIFO_WW2END3_0", + "CMT_TOP_WW2END3_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "CMT_TOP_ICLK_1" + ], + [ + "CMT_FIFO_L_BYP6_7", + "CMT_TOP_BYP6_8" + ], + [ + "CMT_FIFO_L_IMUX38_0", + "CMT_TOP_IMUX38_1" + ], + [ + "CMT_FIFO_LH10_8", + "CMT_TOP_LH10_9" + ], + [ + "CMT_FIFO_NW4A1_6", + "CMT_TOP_NW4A1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_3", + "CMT_TOP_LOGIC_OUTS_L_B21_4" + ], + [ + "CMT_FIFO_L_FAN7_5", + "CMT_TOP_FAN7_6" + ], + [ + "CMT_FIFO_SW2A3_9", + "CMT_TOP_SW2A3_10" + ], + [ + "CMT_FIFO_WW4B0_2", + "CMT_TOP_WW4B0_3" + ], + [ + "CMT_FIFO_L_IMUX15_7", + "CMT_TOP_IMUX15_8" + ], + [ + "CMT_FIFO_LH12_5", + "CMT_TOP_LH12_6" + ], + [ + "CMT_FIFO_WW4A0_3", + "CMT_TOP_WW4A0_4" + ], + [ + "CMT_FIFO_EE4C1_2", + "CMT_TOP_EE4C1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_5", + "CMT_TOP_LOGIC_OUTS_L_B17_6" + ], + [ + "CMT_FIFO_WW4B0_7", + "CMT_TOP_WW4B0_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "CMT_TOP_OCLKDIV_7" + ], + [ + "CMT_FIFO_NE4BEG3_4", + "CMT_TOP_NE4BEG3_5" + ], + [ + "CMT_FIFO_WW4B1_2", + "CMT_TOP_WW4B1_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "CMT_TOP_OCLK_2" + ], + [ + "CMT_FIFO_EE4A2_1", + "CMT_TOP_EE4A2_2" + ], + [ + "CMT_FIFO_EE2BEG3_8", + "CMT_TOP_EE2BEG3_9" + ], + [ + "CMT_FIFO_EE2A0_11", + "CMT_TOP_EE2A0_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_10", + "CMT_TOP_LOGIC_OUTS_L_B5_11" + ], + [ + "CMT_FIFO_SE4C1_6", + "CMT_TOP_SE4C1_7" + ], + [ + "CMT_FIFO_EE2A2_8", + "CMT_TOP_EE2A2_9" + ], + [ + "CMT_FIFO_WW4A3_4", + "CMT_TOP_WW4A3_5" + ], + [ + "CMT_FIFO_WW4C1_1", + "CMT_TOP_WW4C1_2" + ], + [ + "CMT_FIFO_L_CTRL0_2", + "CMT_TOP_CTRL0_3" + ], + [ + "CMT_FIFO_EE4B2_7", + "CMT_TOP_EE4B2_8" + ], + [ + "CMT_FIFO_WW4A3_7", + "CMT_TOP_WW4A3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_4", + "CMT_TOP_LOGIC_OUTS_L_B20_5" + ], + [ + "CMT_FIFO_SE4C3_2", + "CMT_TOP_SE4C3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_2", + "CMT_TOP_LOGIC_OUTS_L_B10_3" + ], + [ + "CMT_FIFO_WW4END1_2", + "CMT_TOP_WW4END1_3" + ], + [ + "CMT_FIFO_L_BYP3_1", + "CMT_TOP_BYP3_2" + ], + [ + "CMT_FIFO_WW4A1_7", + "CMT_TOP_WW4A1_8" + ], + [ + "CMT_FIFO_L_IMUX17_5", + "CMT_TOP_IMUX17_6" + ], + [ + "CMT_FIFO_WW4B3_5", + "CMT_TOP_WW4B3_6" + ], + [ + "CMT_FIFO_L_IMUX20_6", + "CMT_TOP_IMUX20_7" + ], + [ + "CMT_FIFO_EE4C0_9", + "CMT_TOP_EE4C0_10" + ], + [ + "CMT_FIFO_NE4BEG0_7", + "CMT_TOP_NE4BEG0_8" + ], + [ + "CMT_FIFO_WW4A1_3", + "CMT_TOP_WW4A1_4" + ], + [ + "CMT_FIFO_L_BYP6_11", + "CMT_TOP_BYP6_12" + ], + [ + "CMT_FIFO_NE2A2_2", + "CMT_TOP_NE2A2_3" + ], + [ + "CMT_FIFO_L_FAN2_6", + "CMT_TOP_FAN2_7" + ], + [ + "CMT_FIFO_L_IMUX4_5", + "CMT_TOP_IMUX4_6" + ], + [ + "CMT_FIFO_NE4C2_9", + "CMT_TOP_NE4C2_10" + ], + [ + "CMT_FIFO_LH4_5", + "CMT_TOP_LH4_6" + ], + [ + "CMT_FIFO_WW4B2_11", + "CMT_TOP_WW4B2_12" + ], + [ + "CMT_FIFO_SW4A0_4", + "CMT_TOP_SW4A0_5" + ], + [ + "CMT_FIFO_L_BYP1_0", + "CMT_TOP_BYP1_1" + ], + [ + "CMT_FIFO_NW4A1_0", + "CMT_TOP_NW4A1_1" + ], + [ + "CMT_FIFO_WL1END1_8", + "CMT_TOP_WL1END1_9" + ], + [ + "CMT_FIFO_L_IMUX2_10", + "CMT_TOP_IMUX2_11" + ], + [ + "CMT_FIFO_L_BYP0_2", + "CMT_TOP_BYP0_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "CMT_TOP_ICLK_5" + ], + [ + "CMT_FIFO_L_IMUX23_3", + "CMT_TOP_IMUX23_4" + ], + [ + "CMT_FIFO_NE2A1_11", + "CMT_TOP_NE2A1_12" + ], + [ + "CMT_FIFO_EE4B1_9", + "CMT_TOP_EE4B1_10" + ], + [ + "CMT_FIFO_L_CLK1_6", + "CMT_TOP_CLK1_7" + ], + [ + "CMT_FIFO_WR1END3_6", + "CMT_TOP_WR1END3_7" + ], + [ + "CMT_FIFO_ER1BEG3_8", + "CMT_TOP_ER1BEG3_9" + ], + [ + "CMT_FIFO_EE2A3_1", + "CMT_TOP_EE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX2_8", + "CMT_TOP_IMUX2_9" + ], + [ + "CMT_FIFO_NE2A2_8", + "CMT_TOP_NE2A2_9" + ], + [ + "CMT_FIFO_L_IMUX44_9", + "CMT_TOP_IMUX44_10" + ], + [ + "CMT_FIFO_EE4C1_6", + "CMT_TOP_EE4C1_7" + ], + [ + "CMT_FIFO_L_IMUX44_0", + "CMT_TOP_IMUX44_1" + ], + [ + "CMT_FIFO_L_CTRL1_11", + "CMT_TOP_CTRL1_12" + ], + [ + "CMT_FIFO_SW2A1_3", + "CMT_TOP_SW2A1_4" + ], + [ + "CMT_FIFO_L_IMUX28_1", + "CMT_TOP_IMUX28_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_5", + "CMT_TOP_LOGIC_OUTS_L_B18_6" + ], + [ + "CMT_FIFO_L_BYP0_3", + "CMT_TOP_BYP0_4" + ], + [ + "CMT_FIFO_NE2A3_2", + "CMT_TOP_NE2A3_3" + ], + [ + "CMT_FIFO_SE4C1_5", + "CMT_TOP_SE4C1_6" + ], + [ + "CMT_FIFO_NW4A3_8", + "CMT_TOP_NW4A3_9" + ], + [ + "CMT_FIFO_SW4END2_1", + "CMT_TOP_SW4END2_2" + ], + [ + "CMT_FIFO_WW4END1_7", + "CMT_TOP_WW4END1_8" + ], + [ + "CMT_FIFO_L_IMUX5_11", + "CMT_TOP_IMUX5_12" + ], + [ + "CMT_FIFO_LH4_10", + "CMT_TOP_LH4_11" + ], + [ + "CMT_FIFO_L_IMUX35_8", + "CMT_TOP_IMUX35_9" + ], + [ + "CMT_FIFO_EE2BEG1_2", + "CMT_TOP_EE2BEG1_3" + ], + [ + "CMT_FIFO_EL1BEG1_6", + "CMT_TOP_EL1BEG1_7" + ], + [ + "CMT_FIFO_SW4END2_6", + "CMT_TOP_SW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX39_2", + "CMT_TOP_IMUX39_3" + ], + [ + "CMT_FIFO_EE2A0_6", + "CMT_TOP_EE2A0_7" + ], + [ + "CMT_FIFO_L_IMUX7_0", + "CMT_TOP_IMUX7_1" + ], + [ + "CMT_FIFO_EL1BEG1_10", + "CMT_TOP_EL1BEG1_11" + ], + [ + "CMT_FIFO_EE4A3_2", + "CMT_TOP_EE4A3_3" + ], + [ + "CMT_FIFO_NW4A0_1", + "CMT_TOP_NW4A0_2" + ], + [ + "CMT_FIFO_L_IMUX7_6", + "CMT_TOP_IMUX7_7" + ], + [ + "CMT_FIFO_SW4A0_5", + "CMT_TOP_SW4A0_6" + ], + [ + "CMT_FIFO_L_IMUX31_1", + "CMT_TOP_IMUX31_2" + ], + [ + "CMT_FIFO_L_IMUX13_11", + "CMT_TOP_IMUX13_12" + ], + [ + "CMT_FIFO_SW4A0_11", + "CMT_TOP_SW4A0_12" + ], + [ + "CMT_FIFO_EE4C2_6", + "CMT_TOP_EE4C2_7" + ], + [ + "CMT_FIFO_SE4C2_3", + "CMT_TOP_SE4C2_4" + ], + [ + "CMT_FIFO_L_IMUX36_5", + "CMT_TOP_IMUX36_6" + ], + [ + "CMT_FIFO_L_IMUX47_7", + "CMT_TOP_IMUX47_8" + ], + [ + "CMT_FIFO_EE2BEG1_10", + "CMT_TOP_EE2BEG1_11" + ], + [ + "CMT_FIFO_L_IMUX2_11", + "CMT_TOP_IMUX2_12" + ], + [ + "CMT_FIFO_NW4END3_8", + "CMT_TOP_NW4END3_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "CMT_TOP_ICLKDIV_4" + ], + [ + "CMT_FIFO_L_IMUX11_1", + "CMT_TOP_IMUX11_2" + ], + [ + "CMT_FIFO_SW4END3_3", + "CMT_TOP_SW4END3_4" + ], + [ + "CMT_FIFO_L_IMUX44_4", + "CMT_TOP_IMUX44_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_4", + "CMT_TOP_LOGIC_OUTS_L_B8_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_3", + "CMT_TOP_LOGIC_OUTS_L_B18_4" + ], + [ + "CMT_FIFO_NW4END0_0", + "CMT_TOP_NW4END0_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "CMT_TOP_ICLKDIV_6" + ], + [ + "CMT_FIFO_WW2END1_8", + "CMT_TOP_WW2END1_9" + ], + [ + "CMT_FIFO_NW4END0_10", + "CMT_TOP_NW4END0_11" + ], + [ + "CMT_FIFO_L_IMUX18_2", + "CMT_TOP_IMUX18_3" + ], + [ + "CMT_FIFO_WL1END0_9", + "CMT_TOP_WL1END0_10" + ], + [ + "CMT_FIFO_NW4END2_6", + "CMT_TOP_NW4END2_7" + ], + [ + "CMT_FIFO_NW2A2_3", + "CMT_TOP_NW2A2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_11", + "CMT_TOP_LOGIC_OUTS_L_B5_12" + ], + [ + "CMT_FIFO_L_IMUX5_4", + "CMT_TOP_IMUX5_5" + ], + [ + "CMT_FIFO_L_IMUX21_5", + "CMT_TOP_IMUX21_6" + ], + [ + "CMT_FIFO_WW4B2_2", + "CMT_TOP_WW4B2_3" + ], + [ + "CMT_FIFO_WW4A3_11", + "CMT_TOP_WW4A3_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_6", + "CMT_TOP_LOGIC_OUTS_L_B18_7" + ], + [ + "CMT_FIFO_L_IMUX39_6", + "CMT_TOP_IMUX39_7" + ], + [ + "CMT_FIFO_L_IMUX37_3", + "CMT_TOP_IMUX37_4" + ], + [ + "CMT_FIFO_SW2A2_1", + "CMT_TOP_SW2A2_2" + ], + [ + "CMT_FIFO_WW4B2_5", + "CMT_TOP_WW4B2_6" + ], + [ + "CMT_FIFO_EE4BEG3_6", + "CMT_TOP_EE4BEG3_7" + ], + [ + "CMT_FIFO_EE4BEG0_2", + "CMT_TOP_EE4BEG0_3" + ], + [ + "CMT_FIFO_EL1BEG0_11", + "CMT_TOP_EL1BEG0_12" + ], + [ + "CMT_FIFO_L_IMUX6_7", + "CMT_TOP_IMUX6_8" + ], + [ + "CMT_FIFO_EE4C2_7", + "CMT_TOP_EE4C2_8" + ], + [ + "CMT_FIFO_L_IMUX41_3", + "CMT_TOP_IMUX41_4" + ], + [ + "CMT_FIFO_WW2A1_7", + "CMT_TOP_WW2A1_8" + ], + [ + "CMT_FIFO_ER1BEG2_5", + "CMT_TOP_ER1BEG2_6" + ], + [ + "CMT_FIFO_SE4C3_5", + "CMT_TOP_SE4C3_6" + ], + [ + "CMT_FIFO_SW4A0_3", + "CMT_TOP_SW4A0_4" + ], + [ + "CMT_FIFO_L_IMUX46_9", + "CMT_TOP_IMUX46_10" + ], + [ + "CMT_FIFO_ER1BEG0_2", + "CMT_TOP_ER1BEG0_3" + ], + [ + "CMT_FIFO_L_IMUX31_8", + "CMT_TOP_IMUX31_9" + ], + [ + "CMT_FIFO_SW2A1_8", + "CMT_TOP_SW2A1_9" + ], + [ + "CMT_FIFO_L_IMUX34_4", + "CMT_TOP_IMUX34_5" + ], + [ + "CMT_FIFO_EE2A2_7", + "CMT_TOP_EE2A2_8" + ], + [ + "CMT_FIFO_NE4C0_1", + "CMT_TOP_NE4C0_2" + ], + [ + "CMT_FIFO_NE4C2_8", + "CMT_TOP_NE4C2_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "CMT_TOP_ICLK_6" + ], + [ + "CMT_FIFO_L_BYP1_4", + "CMT_TOP_BYP1_5" + ], + [ + "CMT_FIFO_EE4C2_5", + "CMT_TOP_EE4C2_6" + ], + [ + "CMT_FIFO_L_IMUX11_9", + "CMT_TOP_IMUX11_10" + ], + [ + "CMT_FIFO_L_IMUX28_11", + "CMT_TOP_IMUX28_12" + ], + [ + "CMT_FIFO_MONITOR_P_6", + "CMT_TOP_MONITOR_P_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_9", + "CMT_TOP_LOGIC_OUTS_L_B10_10" + ], + [ + "CMT_FIFO_WW4B3_4", + "CMT_TOP_WW4B3_5" + ], + [ + "CMT_FIFO_SE4BEG2_7", + "CMT_TOP_SE4BEG2_8" + ], + [ + "CMT_FIFO_SW2A0_10", + "CMT_TOP_SW2A0_11" + ], + [ + "CMT_FIFO_NW4A2_9", + "CMT_TOP_NW4A2_10" + ], + [ + "CMT_FIFO_EL1BEG2_5", + "CMT_TOP_EL1BEG2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_7", + "CMT_TOP_LOGIC_OUTS_L_B15_8" + ], + [ + "CMT_FIFO_L_IMUX32_11", + "CMT_TOP_IMUX32_12" + ], + [ + "CMT_FIFO_EE4BEG2_11", + "CMT_TOP_EE4BEG2_12" + ], + [ + "CMT_FIFO_NW4A3_1", + "CMT_TOP_NW4A3_2" + ], + [ + "CMT_FIFO_WW4B3_11", + "CMT_TOP_WW4B3_12" + ], + [ + "CMT_FIFO_NW2A3_10", + "CMT_TOP_NW2A3_11" + ], + [ + "CMT_FIFO_L_IMUX8_9", + "CMT_TOP_IMUX8_10" + ], + [ + "CMT_FIFO_LH2_9", + "CMT_TOP_LH2_10" + ], + [ + "CMT_FIFO_SE2A0_5", + "CMT_TOP_SE2A0_6" + ], + [ + "CMT_FIFO_WL1END0_1", + "CMT_TOP_WL1END0_2" + ], + [ + "CMT_FIFO_WW4A1_5", + "CMT_TOP_WW4A1_6" + ], + [ + "CMT_FIFO_LH1_3", + "CMT_TOP_LH1_4" + ], + [ + "CMT_FIFO_EE2A3_2", + "CMT_TOP_EE2A3_3" + ], + [ + "CMT_FIFO_L_IMUX40_0", + "CMT_TOP_IMUX40_1" + ], + [ + "CMT_FIFO_SE4C3_8", + "CMT_TOP_SE4C3_9" + ], + [ + "CMT_FIFO_WL1END0_5", + "CMT_TOP_WL1END0_6" + ], + [ + "CMT_FIFO_NW2A0_4", + "CMT_TOP_NW2A0_5" + ], + [ + "CMT_FIFO_L_BYP5_2", + "CMT_TOP_BYP5_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_4", + "CMT_TOP_LOGIC_OUTS_L_B9_5" + ], + [ + "CMT_FIFO_LH3_9", + "CMT_TOP_LH3_10" + ], + [ + "CMT_FIFO_L_IMUX4_2", + "CMT_TOP_IMUX4_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_11", + "CMT_TOP_LOGIC_OUTS_L_B11_12" + ], + [ + "CMT_FIFO_EE2A1_3", + "CMT_TOP_EE2A1_4" + ], + [ + "CMT_FIFO_NE4BEG0_2", + "CMT_TOP_NE4BEG0_3" + ], + [ + "CMT_FIFO_WW2A2_9", + "CMT_TOP_WW2A2_10" + ], + [ + "CMT_FIFO_WW4C2_5", + "CMT_TOP_WW4C2_6" + ], + [ + "CMT_FIFO_WW4A0_0", + "CMT_TOP_WW4A0_1" + ], + [ + "CMT_FIFO_EL1BEG3_2", + "CMT_TOP_EL1BEG3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_11", + "CMT_TOP_LOGIC_OUTS_L_B4_12" + ], + [ + "CMT_FIFO_L_CTRL1_10", + "CMT_TOP_CTRL1_11" + ], + [ + "CMT_FIFO_NW4A1_7", + "CMT_TOP_NW4A1_8" + ], + [ + "CMT_FIFO_EE4B2_5", + "CMT_TOP_EE4B2_6" + ], + [ + "CMT_FIFO_L_FAN3_7", + "CMT_TOP_FAN3_8" + ], + [ + "CMT_FIFO_WW2A2_10", + "CMT_TOP_WW2A2_11" + ], + [ + "CMT_FIFO_L_IMUX26_2", + "CMT_TOP_IMUX26_3" + ], + [ + "CMT_FIFO_L_IMUX42_7", + "CMT_TOP_IMUX42_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_8", + "CMT_TOP_LOGIC_OUTS_L_B11_9" + ], + [ + "CMT_FIFO_WW2A2_0", + "CMT_TOP_WW2A2_1" + ], + [ + "CMT_FIFO_SE4C2_1", + "CMT_TOP_SE4C2_2" + ], + [ + "CMT_FIFO_WL1END3_2", + "CMT_TOP_WL1END3_3" + ], + [ + "CMT_FIFO_ER1BEG1_5", + "CMT_TOP_ER1BEG1_6" + ], + [ + "CMT_FIFO_LH5_9", + "CMT_TOP_LH5_10" + ], + [ + "CMT_FIFO_NW2A0_11", + "CMT_TOP_NW2A0_12" + ], + [ + "CMT_FIFO_EE4BEG0_1", + "CMT_TOP_EE4BEG0_2" + ], + [ + "CMT_FIFO_NW4A2_11", + "CMT_TOP_NW4A2_12" + ], + [ + "CMT_FIFO_EE4BEG1_10", + "CMT_TOP_EE4BEG1_11" + ], + [ + "CMT_FIFO_WW4B2_3", + "CMT_TOP_WW4B2_4" + ], + [ + "CMT_FIFO_WW4C2_2", + "CMT_TOP_WW4C2_3" + ], + [ + "CMT_FIFO_L_BYP6_9", + "CMT_TOP_BYP6_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "CMT_TOP_OCLKDIV_3" + ], + [ + "CMT_FIFO_L_IMUX18_7", + "CMT_TOP_IMUX18_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_7", + "CMT_TOP_LOGIC_OUTS_L_B17_8" + ], + [ + "CMT_FIFO_NW2A3_3", + "CMT_TOP_NW2A3_4" + ], + [ + "CMT_FIFO_EE4BEG1_7", + "CMT_TOP_EE4BEG1_8" + ], + [ + "CMT_FIFO_NW4A0_7", + "CMT_TOP_NW4A0_8" + ], + [ + "CMT_FIFO_MONITOR_N_2", + "CMT_TOP_MONITOR_N_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_9", + "CMT_TOP_LOGIC_OUTS_L_B7_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_1", + "CMT_TOP_LOGIC_OUTS_L_B12_2" + ], + [ + "CMT_FIFO_L_BYP3_3", + "CMT_TOP_BYP3_4" + ], + [ + "CMT_FIFO_L_IMUX16_9", + "CMT_TOP_IMUX16_10" + ], + [ + "CMT_FIFO_EE4A3_3", + "CMT_TOP_EE4A3_4" + ], + [ + "CMT_FIFO_L_IMUX34_8", + "CMT_TOP_IMUX34_9" + ], + [ + "CMT_FIFO_L_CTRL0_8", + "CMT_TOP_CTRL0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_7", + "CMT_TOP_LOGIC_OUTS_L_B22_8" + ], + [ + "CMT_FIFO_NE4C1_2", + "CMT_TOP_NE4C1_3" + ], + [ + "CMT_FIFO_WW2END1_9", + "CMT_TOP_WW2END1_10" + ], + [ + "CMT_FIFO_L_BYP0_9", + "CMT_TOP_BYP0_10" + ], + [ + "CMT_FIFO_L_IMUX20_11", + "CMT_TOP_IMUX20_12" + ], + [ + "CMT_FIFO_SW2A0_4", + "CMT_TOP_SW2A0_5" + ], + [ + "CMT_FIFO_SE4BEG1_11", + "CMT_TOP_SE4BEG1_12" + ], + [ + "CMT_FIFO_NE2A1_3", + "CMT_TOP_NE2A1_4" + ], + [ + "CMT_FIFO_LH3_10", + "CMT_TOP_LH3_11" + ], + [ + "CMT_FIFO_NE2A3_4", + "CMT_TOP_NE2A3_5" + ], + [ + "CMT_FIFO_WR1END1_2", + "CMT_TOP_WR1END1_3" + ], + [ + "CMT_FIFO_LH10_9", + "CMT_TOP_LH10_10" + ], + [ + "CMT_FIFO_L_FAN0_0", + "CMT_TOP_FAN0_1" + ], + [ + "CMT_FIFO_EE2A2_9", + "CMT_TOP_EE2A2_10" + ], + [ + "CMT_FIFO_L_IMUX15_3", + "CMT_TOP_IMUX15_4" + ], + [ + "CMT_FIFO_L_IMUX10_3", + "CMT_TOP_IMUX10_4" + ], + [ + "CMT_FIFO_LH12_8", + "CMT_TOP_LH12_9" + ], + [ + "CMT_FIFO_L_IMUX6_8", + "CMT_TOP_IMUX6_9" + ], + [ + "CMT_FIFO_WW4A0_4", + "CMT_TOP_WW4A0_5" + ], + [ + "CMT_FIFO_EE4C0_3", + "CMT_TOP_EE4C0_4" + ], + [ + "CMT_FIFO_EE2BEG1_9", + "CMT_TOP_EE2BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX42_2", + "CMT_TOP_IMUX42_3" + ], + [ + "CMT_FIFO_L_CLK1_4", + "CMT_TOP_CLK1_5" + ], + [ + "CMT_FIFO_EE4C1_4", + "CMT_TOP_EE4C1_5" + ], + [ + "CMT_FIFO_EE4C2_3", + "CMT_TOP_EE4C2_4" + ], + [ + "CMT_FIFO_L_BYP6_4", + "CMT_TOP_BYP6_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_5", + "CMT_TOP_LOGIC_OUTS_L_B11_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_4", + "CMT_TOP_LOGIC_OUTS_L_B5_5" + ], + [ + "CMT_FIFO_L_IMUX26_10", + "CMT_TOP_IMUX26_11" + ], + [ + "CMT_FIFO_WW4B3_7", + "CMT_TOP_WW4B3_8" + ], + [ + "CMT_FIFO_NW4END3_3", + "CMT_TOP_NW4END3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_6", + "CMT_TOP_LOGIC_OUTS_L_B13_7" + ], + [ + "CMT_FIFO_NW4END0_3", + "CMT_TOP_NW4END0_4" + ], + [ + "CMT_FIFO_LH12_0", + "CMT_TOP_LH12_1" + ], + [ + "CMT_FIFO_L_IMUX17_6", + "CMT_TOP_IMUX17_7" + ], + [ + "CMT_FIFO_LH2_6", + "CMT_TOP_LH2_7" + ], + [ + "CMT_FIFO_L_IMUX46_8", + "CMT_TOP_IMUX46_9" + ], + [ + "CMT_FIFO_L_IMUX28_7", + "CMT_TOP_IMUX28_8" + ], + [ + "CMT_FIFO_LH9_8", + "CMT_TOP_LH9_9" + ], + [ + "CMT_FIFO_NE4BEG2_3", + "CMT_TOP_NE4BEG2_4" + ], + [ + "CMT_FIFO_L_IMUX6_6", + "CMT_TOP_IMUX6_7" + ], + [ + "CMT_FIFO_NE4C3_2", + "CMT_TOP_NE4C3_3" + ], + [ + "CMT_FIFO_L_IMUX5_5", + "CMT_TOP_IMUX5_6" + ], + [ + "CMT_FIFO_NE4BEG3_0", + "CMT_TOP_NE4BEG3_1" + ], + [ + "CMT_FIFO_NW4END1_5", + "CMT_TOP_NW4END1_6" + ], + [ + "CMT_FIFO_L_IMUX25_1", + "CMT_TOP_IMUX25_2" + ], + [ + "CMT_FIFO_NW2A2_2", + "CMT_TOP_NW2A2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_3", + "CMT_TOP_LOGIC_OUTS_L_B9_4" + ], + [ + "CMT_FIFO_L_IMUX13_9", + "CMT_TOP_IMUX13_10" + ], + [ + "CMT_FIFO_LH1_4", + "CMT_TOP_LH1_5" + ], + [ + "CMT_FIFO_L_IMUX44_5", + "CMT_TOP_IMUX44_6" + ], + [ + "CMT_FIFO_MONITOR_P_2", + "CMT_TOP_MONITOR_P_3" + ], + [ + "CMT_FIFO_EE2BEG2_3", + "CMT_TOP_EE2BEG2_4" + ], + [ + "CMT_FIFO_WL1END1_6", + "CMT_TOP_WL1END1_7" + ], + [ + "CMT_FIFO_L_BYP3_5", + "CMT_TOP_BYP3_6" + ], + [ + "CMT_FIFO_L_IMUX21_6", + "CMT_TOP_IMUX21_7" + ], + [ + "CMT_FIFO_L_FAN2_4", + "CMT_TOP_FAN2_5" + ], + [ + "CMT_FIFO_NW4A1_1", + "CMT_TOP_NW4A1_2" + ], + [ + "CMT_FIFO_NW4END0_4", + "CMT_TOP_NW4END0_5" + ], + [ + "CMT_FIFO_NE2A3_3", + "CMT_TOP_NE2A3_4" + ], + [ + "CMT_FIFO_L_BYP4_2", + "CMT_TOP_BYP4_3" + ], + [ + "CMT_FIFO_L_BYP6_5", + "CMT_TOP_BYP6_6" + ], + [ + "CMT_FIFO_NE4C3_3", + "CMT_TOP_NE4C3_4" + ], + [ + "CMT_FIFO_L_IMUX4_6", + "CMT_TOP_IMUX4_7" + ], + [ + "CMT_FIFO_LH1_10", + "CMT_TOP_LH1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_11", + "CMT_TOP_LOGIC_OUTS_L_B22_12" + ], + [ + "CMT_FIFO_WW4A3_5", + "CMT_TOP_WW4A3_6" + ], + [ + "CMT_FIFO_LH10_1", + "CMT_TOP_LH10_2" + ], + [ + "CMT_FIFO_WW4END3_2", + "CMT_TOP_WW4END3_3" + ], + [ + "CMT_FIFO_SW2A2_0", + "CMT_TOP_SW2A2_1" + ], + [ + "CMT_FIFO_NW2A0_10", + "CMT_TOP_NW2A0_11" + ], + [ + "CMT_FIFO_EE4C3_10", + "CMT_TOP_EE4C3_11" + ], + [ + "CMT_FIFO_SE4C1_7", + "CMT_TOP_SE4C1_8" + ], + [ + "CMT_FIFO_EE4C0_11", + "CMT_TOP_EE4C0_12" + ], + [ + "CMT_FIFO_L_IMUX25_2", + "CMT_TOP_IMUX25_3" + ], + [ + "CMT_FIFO_L_FAN2_2", + "CMT_TOP_FAN2_3" + ], + [ + "CMT_FIFO_L_IMUX44_7", + "CMT_TOP_IMUX44_8" + ], + [ + "CMT_FIFO_SW4A3_8", + "CMT_TOP_SW4A3_9" + ], + [ + "CMT_FIFO_SE2A2_4", + "CMT_TOP_SE2A2_5" + ], + [ + "CMT_FIFO_WW4A0_9", + "CMT_TOP_WW4A0_10" + ], + [ + "CMT_FIFO_L_IMUX47_2", + "CMT_TOP_IMUX47_3" + ], + [ + "CMT_FIFO_SW4A0_0", + "CMT_TOP_SW4A0_1" + ], + [ + "CMT_FIFO_L_IMUX26_11", + "CMT_TOP_IMUX26_12" + ], + [ + "CMT_FIFO_L_IMUX23_6", + "CMT_TOP_IMUX23_7" + ], + [ + "CMT_FIFO_SW2A1_0", + "CMT_TOP_SW2A1_1" + ], + [ + "CMT_FIFO_WW4B2_1", + "CMT_TOP_WW4B2_2" + ], + [ + "CMT_FIFO_L_IMUX40_2", + "CMT_TOP_IMUX40_3" + ], + [ + "CMT_FIFO_WW2END1_0", + "CMT_TOP_WW2END1_1" + ], + [ + "CMT_FIFO_EE4C0_0", + "CMT_TOP_EE4C0_1" + ], + [ + "CMT_FIFO_EE4C3_5", + "CMT_TOP_EE4C3_6" + ], + [ + "CMT_FIFO_WW4A1_1", + "CMT_TOP_WW4A1_2" + ], + [ + "CMT_FIFO_L_BYP5_10", + "CMT_TOP_BYP5_11" + ], + [ + "CMT_FIFO_NE2A0_5", + "CMT_TOP_NE2A0_6" + ], + [ + "CMT_FIFO_L_FAN6_10", + "CMT_TOP_FAN6_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_11", + "CMT_TOP_LOGIC_OUTS_L_B1_12" + ], + [ + "CMT_FIFO_LH3_3", + "CMT_TOP_LH3_4" + ], + [ + "CMT_FIFO_NW4A2_0", + "CMT_TOP_NW4A2_1" + ], + [ + "CMT_FIFO_NW2A0_9", + "CMT_TOP_NW2A0_10" + ], + [ + "CMT_FIFO_L_IMUX17_7", + "CMT_TOP_IMUX17_8" + ], + [ + "CMT_FIFO_L_IMUX47_0", + "CMT_TOP_IMUX47_1" + ], + [ + "CMT_FIFO_EL1BEG3_0", + "CMT_TOP_EL1BEG3_1" + ], + [ + "CMT_FIFO_EE2BEG0_0", + "CMT_TOP_EE2BEG0_1" + ], + [ + "CMT_FIFO_EE4BEG1_3", + "CMT_TOP_EE4BEG1_4" + ], + [ + "CMT_FIFO_SW2A1_2", + "CMT_TOP_SW2A1_3" + ], + [ + "CMT_FIFO_LH8_8", + "CMT_TOP_LH8_9" + ], + [ + "CMT_FIFO_NE4BEG2_7", + "CMT_TOP_NE4BEG2_8" + ], + [ + "CMT_FIFO_L_IMUX29_9", + "CMT_TOP_IMUX29_10" + ], + [ + "CMT_FIFO_SW4A2_5", + "CMT_TOP_SW4A2_6" + ], + [ + "CMT_FIFO_L_IMUX40_9", + "CMT_TOP_IMUX40_10" + ], + [ + "CMT_FIFO_L_FAN4_0", + "CMT_TOP_FAN4_1" + ], + [ + "CMT_FIFO_L_IMUX21_7", + "CMT_TOP_IMUX21_8" + ], + [ + "CMT_FIFO_NW2A1_11", + "CMT_TOP_NW2A1_12" + ], + [ + "CMT_FIFO_EE2BEG0_8", + "CMT_TOP_EE2BEG0_9" + ], + [ + "CMT_FIFO_WW4B1_11", + "CMT_TOP_WW4B1_12" + ], + [ + "CMT_FIFO_WR1END2_8", + "CMT_TOP_WR1END2_9" + ], + [ + "CMT_FIFO_WW4END1_6", + "CMT_TOP_WW4END1_7" + ], + [ + "CMT_FIFO_L_IMUX14_3", + "CMT_TOP_IMUX14_4" + ], + [ + "CMT_FIFO_WW2END1_3", + "CMT_TOP_WW2END1_4" + ], + [ + "CMT_FIFO_WW4END0_6", + "CMT_TOP_WW4END0_7" + ], + [ + "CMT_FIFO_EE4C1_1", + "CMT_TOP_EE4C1_2" + ], + [ + "CMT_FIFO_SW4A0_10", + "CMT_TOP_SW4A0_11" + ], + [ + "CMT_FIFO_EE4A1_3", + "CMT_TOP_EE4A1_4" + ], + [ + "CMT_FIFO_L_IMUX41_2", + "CMT_TOP_IMUX41_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_2", + "CMT_TOP_LOGIC_OUTS_L_B1_3" + ], + [ + "CMT_FIFO_LH11_10", + "CMT_TOP_LH11_11" + ], + [ + "CMT_FIFO_L_IMUX0_0", + "CMT_TOP_IMUX0_1" + ], + [ + "CMT_FIFO_WW4C3_1", + "CMT_TOP_WW4C3_2" + ], + [ + "CMT_FIFO_EE4BEG3_9", + "CMT_TOP_EE4BEG3_10" + ], + [ + "CMT_FIFO_L_IMUX26_4", + "CMT_TOP_IMUX26_5" + ], + [ + "CMT_FIFO_L_BYP2_1", + "CMT_TOP_BYP2_2" + ], + [ + "CMT_FIFO_NW4END1_11", + "CMT_TOP_NW4END1_12" + ], + [ + "CMT_FIFO_L_BYP2_0", + "CMT_TOP_BYP2_1" + ], + [ + "CMT_FIFO_L_IMUX27_3", + "CMT_TOP_IMUX27_4" + ], + [ + "CMT_FIFO_L_IMUX32_8", + "CMT_TOP_IMUX32_9" + ], + [ + "CMT_FIFO_LH4_9", + "CMT_TOP_LH4_10" + ], + [ + "CMT_FIFO_L_IMUX33_1", + "CMT_TOP_IMUX33_2" + ], + [ + "CMT_FIFO_WL1END3_0", + "CMT_TOP_WL1END3_1" + ], + [ + "CMT_FIFO_SW4END1_5", + "CMT_TOP_SW4END1_6" + ], + [ + "CMT_FIFO_LH9_5", + "CMT_TOP_LH9_6" + ], + [ + "CMT_FIFO_L_IMUX34_7", + "CMT_TOP_IMUX34_8" + ], + [ + "CMT_FIFO_WW4C3_6", + "CMT_TOP_WW4C3_7" + ], + [ + "CMT_FIFO_L_IMUX31_7", + "CMT_TOP_IMUX31_8" + ], + [ + "CMT_FIFO_SE4C2_0", + "CMT_TOP_SE4C2_1" + ], + [ + "CMT_FIFO_L_IMUX9_4", + "CMT_TOP_IMUX9_5" + ], + [ + "CMT_FIFO_LH7_8", + "CMT_TOP_LH7_9" + ], + [ + "CMT_FIFO_WR1END3_9", + "CMT_TOP_WR1END3_10" + ], + [ + "CMT_FIFO_L_IMUX13_8", + "CMT_TOP_IMUX13_9" + ], + [ + "CMT_FIFO_L_IMUX23_9", + "CMT_TOP_IMUX23_10" + ], + [ + "CMT_FIFO_NW4A3_3", + "CMT_TOP_NW4A3_4" + ], + [ + "CMT_FIFO_L_IMUX4_1", + "CMT_TOP_IMUX4_2" + ], + [ + "CMT_FIFO_L_BYP5_0", + "CMT_TOP_BYP5_1" + ], + [ + "CMT_FIFO_L_IMUX32_10", + "CMT_TOP_IMUX32_11" + ], + [ + "CMT_FIFO_LH4_2", + "CMT_TOP_LH4_3" + ], + [ + "CMT_FIFO_LH9_10", + "CMT_TOP_LH9_11" + ], + [ + "CMT_FIFO_NE2A3_10", + "CMT_TOP_NE2A3_11" + ], + [ + "CMT_FIFO_L_IMUX44_10", + "CMT_TOP_IMUX44_11" + ], + [ + "CMT_FIFO_L_IMUX25_4", + "CMT_TOP_IMUX25_5" + ], + [ + "CMT_FIFO_L_IMUX7_3", + "CMT_TOP_IMUX7_4" + ], + [ + "CMT_FIFO_EE4C3_1", + "CMT_TOP_EE4C3_2" + ], + [ + "CMT_FIFO_EE2BEG2_0", + "CMT_TOP_EE2BEG2_1" + ], + [ + "CMT_FIFO_L_IMUX33_6", + "CMT_TOP_IMUX33_7" + ], + [ + "CMT_FIFO_WR1END3_2", + "CMT_TOP_WR1END3_3" + ], + [ + "CMT_FIFO_L_BYP1_10", + "CMT_TOP_BYP1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_7", + "CMT_TOP_LOGIC_OUTS_L_B6_8" + ], + [ + "CMT_FIFO_L_IMUX27_1", + "CMT_TOP_IMUX27_2" + ], + [ + "CMT_FIFO_NW4A1_9", + "CMT_TOP_NW4A1_10" + ], + [ + "CMT_FIFO_L_IMUX18_6", + "CMT_TOP_IMUX18_7" + ], + [ + "CMT_FIFO_EE4B0_3", + "CMT_TOP_EE4B0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_2", + "CMT_TOP_LOGIC_OUTS_L_B7_3" + ], + [ + "CMT_FIFO_SW4END1_7", + "CMT_TOP_SW4END1_8" + ], + [ + "CMT_FIFO_L_FAN6_9", + "CMT_TOP_FAN6_10" + ], + [ + "CMT_FIFO_L_IMUX13_5", + "CMT_TOP_IMUX13_6" + ], + [ + "CMT_FIFO_L_IMUX26_5", + "CMT_TOP_IMUX26_6" + ], + [ + "CMT_FIFO_L_IMUX9_11", + "CMT_TOP_IMUX9_12" + ], + [ + "CMT_FIFO_NW4A0_4", + "CMT_TOP_NW4A0_5" + ], + [ + "CMT_FIFO_NW4A2_7", + "CMT_TOP_NW4A2_8" + ], + [ + "CMT_FIFO_L_FAN2_8", + "CMT_TOP_FAN2_9" + ], + [ + "CMT_FIFO_NE2A3_8", + "CMT_TOP_NE2A3_9" + ], + [ + "CMT_FIFO_L_IMUX37_7", + "CMT_TOP_IMUX37_8" + ], + [ + "CMT_FIFO_WW2A1_4", + "CMT_TOP_WW2A1_5" + ], + [ + "CMT_FIFO_WW4C2_8", + "CMT_TOP_WW4C2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_10", + "CMT_TOP_LOGIC_OUTS_L_B9_11" + ], + [ + "CMT_FIFO_EE4C2_9", + "CMT_TOP_EE4C2_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "CMT_TOP_ICLK_2" + ], + [ + "CMT_FIFO_WL1END1_7", + "CMT_TOP_WL1END1_8" + ], + [ + "CMT_FIFO_EE4C3_0", + "CMT_TOP_EE4C3_1" + ], + [ + "CMT_FIFO_L_BYP6_0", + "CMT_TOP_BYP6_1" + ], + [ + "CMT_FIFO_L_FAN6_8", + "CMT_TOP_FAN6_9" + ], + [ + "CMT_FIFO_LH6_8", + "CMT_TOP_LH6_9" + ], + [ + "CMT_FIFO_LH3_1", + "CMT_TOP_LH3_2" + ], + [ + "CMT_FIFO_WW2A1_1", + "CMT_TOP_WW2A1_2" + ], + [ + "CMT_FIFO_SE2A3_6", + "CMT_TOP_SE2A3_7" + ], + [ + "CMT_FIFO_NE4C0_10", + "CMT_TOP_NE4C0_11" + ], + [ + "CMT_FIFO_L_IMUX38_5", + "CMT_TOP_IMUX38_6" + ], + [ + "CMT_FIFO_WR1END2_5", + "CMT_TOP_WR1END2_6" + ], + [ + "CMT_FIFO_LH8_5", + "CMT_TOP_LH8_6" + ], + [ + "CMT_FIFO_L_IMUX47_1", + "CMT_TOP_IMUX47_2" + ], + [ + "CMT_FIFO_NE2A0_0", + "CMT_TOP_NE2A0_1" + ], + [ + "CMT_FIFO_L_BYP1_9", + "CMT_TOP_BYP1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_7", + "CMT_TOP_LOGIC_OUTS_L_B2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_3", + "CMT_TOP_LOGIC_OUTS_L_B10_4" + ], + [ + "CMT_FIFO_NW2A1_6", + "CMT_TOP_NW2A1_7" + ], + [ + "CMT_FIFO_L_IMUX19_4", + "CMT_TOP_IMUX19_5" + ], + [ + "CMT_FIFO_L_IMUX14_9", + "CMT_TOP_IMUX14_10" + ], + [ + "CMT_FIFO_LH10_11", + "CMT_TOP_LH10_12" + ], + [ + "CMT_FIFO_WW4A3_3", + "CMT_TOP_WW4A3_4" + ], + [ + "CMT_FIFO_L_IMUX21_0", + "CMT_TOP_IMUX21_1" + ], + [ + "CMT_FIFO_L_IMUX42_3", + "CMT_TOP_IMUX42_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_8", + "CMT_TOP_LOGIC_OUTS_L_B5_9" + ], + [ + "CMT_FIFO_L_IMUX20_9", + "CMT_TOP_IMUX20_10" + ], + [ + "CMT_FIFO_L_IMUX1_6", + "CMT_TOP_IMUX1_7" + ], + [ + "CMT_FIFO_WW4END3_3", + "CMT_TOP_WW4END3_4" + ], + [ + "CMT_FIFO_WL1END2_11", + "CMT_TOP_WL1END2_12" + ], + [ + "CMT_FIFO_WW4END2_11", + "CMT_TOP_WW4END2_12" + ], + [ + "CMT_FIFO_L_IMUX22_6", + "CMT_TOP_IMUX22_7" + ], + [ + "CMT_FIFO_LH5_4", + "CMT_TOP_LH5_5" + ], + [ + "CMT_FIFO_NE2A2_0", + "CMT_TOP_NE2A2_1" + ], + [ + "CMT_FIFO_L_IMUX26_0", + "CMT_TOP_IMUX26_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_1", + "CMT_TOP_LOGIC_OUTS_L_B22_2" + ], + [ + "CMT_FIFO_L_IMUX37_0", + "CMT_TOP_IMUX37_1" + ], + [ + "CMT_FIFO_NE4C1_6", + "CMT_TOP_NE4C1_7" + ], + [ + "CMT_FIFO_EE2A2_10", + "CMT_TOP_EE2A2_11" + ], + [ + "CMT_FIFO_WW4A2_7", + "CMT_TOP_WW4A2_8" + ], + [ + "CMT_FIFO_ER1BEG1_2", + "CMT_TOP_ER1BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX17_10", + "CMT_TOP_IMUX17_11" + ], + [ + "CMT_FIFO_L_IMUX13_10", + "CMT_TOP_IMUX13_11" + ], + [ + "CMT_FIFO_WW4END0_3", + "CMT_TOP_WW4END0_4" + ], + [ + "CMT_FIFO_L_IMUX5_8", + "CMT_TOP_IMUX5_9" + ], + [ + "CMT_FIFO_WW4C1_0", + "CMT_TOP_WW4C1_1" + ], + [ + "CMT_FIFO_SW2A0_1", + "CMT_TOP_SW2A0_2" + ], + [ + "CMT_FIFO_NW4A3_11", + "CMT_TOP_NW4A3_12" + ], + [ + "CMT_FIFO_LH12_3", + "CMT_TOP_LH12_4" + ], + [ + "CMT_FIFO_L_IMUX22_11", + "CMT_TOP_IMUX22_12" + ], + [ + "CMT_FIFO_EE4B1_2", + "CMT_TOP_EE4B1_3" + ], + [ + "CMT_FIFO_SE4BEG0_8", + "CMT_TOP_SE4BEG0_9" + ], + [ + "CMT_FIFO_WW4B2_9", + "CMT_TOP_WW4B2_10" + ], + [ + "CMT_FIFO_LH5_1", + "CMT_TOP_LH5_2" + ], + [ + "CMT_FIFO_WW4C0_3", + "CMT_TOP_WW4C0_4" + ], + [ + "CMT_FIFO_WW4END1_4", + "CMT_TOP_WW4END1_5" + ], + [ + "CMT_FIFO_WW4A3_6", + "CMT_TOP_WW4A3_7" + ], + [ + "CMT_FIFO_L_IMUX36_6", + "CMT_TOP_IMUX36_7" + ], + [ + "CMT_FIFO_EE4BEG0_5", + "CMT_TOP_EE4BEG0_6" + ], + [ + "CMT_FIFO_EE2A0_3", + "CMT_TOP_EE2A0_4" + ], + [ + "CMT_FIFO_SE4BEG3_9", + "CMT_TOP_SE4BEG3_10" + ], + [ + "CMT_FIFO_L_IMUX18_9", + "CMT_TOP_IMUX18_10" + ], + [ + "CMT_FIFO_L_CTRL0_4", + "CMT_TOP_CTRL0_5" + ], + [ + "CMT_FIFO_NW2A3_7", + "CMT_TOP_NW2A3_8" + ], + [ + "CMT_FIFO_SE4BEG0_4", + "CMT_TOP_SE4BEG0_5" + ], + [ + "CMT_FIFO_EE4A2_6", + "CMT_TOP_EE4A2_7" + ], + [ + "CMT_FIFO_EE4B0_11", + "CMT_TOP_EE4B0_12" + ], + [ + "CMT_FIFO_L_FAN1_1", + "CMT_TOP_FAN1_2" + ], + [ + "CMT_FIFO_EE4B2_2", + "CMT_TOP_EE4B2_3" + ], + [ + "CMT_FIFO_EE2BEG3_4", + "CMT_TOP_EE2BEG3_5" + ], + [ + "CMT_FIFO_WW2A2_6", + "CMT_TOP_WW2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_1", + "CMT_TOP_LOGIC_OUTS_L_B19_2" + ], + [ + "CMT_FIFO_L_IMUX0_1", + "CMT_TOP_IMUX0_2" + ], + [ + "CMT_FIFO_SW4A3_0", + "CMT_TOP_SW4A3_1" + ], + [ + "CMT_FIFO_SE2A0_8", + "CMT_TOP_SE2A0_9" + ], + [ + "CMT_FIFO_L_CLK0_7", + "CMT_TOP_CLK0_8" + ], + [ + "CMT_FIFO_SE4C3_4", + "CMT_TOP_SE4C3_5" + ], + [ + "CMT_FIFO_EE2BEG0_7", + "CMT_TOP_EE2BEG0_8" + ], + [ + "CMT_FIFO_WW4B3_10", + "CMT_TOP_WW4B3_11" + ], + [ + "CMT_FIFO_L_BYP5_7", + "CMT_TOP_BYP5_8" + ], + [ + "CMT_FIFO_L_IMUX1_0", + "CMT_TOP_IMUX1_1" + ], + [ + "CMT_FIFO_EE4B0_4", + "CMT_TOP_EE4B0_5" + ], + [ + "CMT_FIFO_NW4END0_11", + "CMT_TOP_NW4END0_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_6", + "CMT_TOP_LOGIC_OUTS_L_B2_7" + ], + [ + "CMT_FIFO_NE2A2_3", + "CMT_TOP_NE2A2_4" + ], + [ + "CMT_FIFO_EL1BEG2_8", + "CMT_TOP_EL1BEG2_9" + ], + [ + "CMT_FIFO_L_IMUX0_9", + "CMT_TOP_IMUX0_10" + ], + [ + "CMT_FIFO_SW4END1_11", + "CMT_TOP_SW4END1_12" + ], + [ + "CMT_FIFO_L_IMUX3_1", + "CMT_TOP_IMUX3_2" + ], + [ + "CMT_FIFO_L_IMUX12_1", + "CMT_TOP_IMUX12_2" + ], + [ + "CMT_FIFO_ER1BEG3_9", + "CMT_TOP_ER1BEG3_10" + ], + [ + "CMT_FIFO_SE4BEG2_5", + "CMT_TOP_SE4BEG2_6" + ], + [ + "CMT_FIFO_SE4C2_8", + "CMT_TOP_SE4C2_9" + ], + [ + "CMT_FIFO_ER1BEG3_1", + "CMT_TOP_ER1BEG3_2" + ], + [ + "CMT_FIFO_EE4B1_6", + "CMT_TOP_EE4B1_7" + ], + [ + "CMT_FIFO_WW4END2_6", + "CMT_TOP_WW4END2_7" + ], + [ + "CMT_FIFO_L_FAN1_6", + "CMT_TOP_FAN1_7" + ], + [ + "CMT_FIFO_L_IMUX47_5", + "CMT_TOP_IMUX47_6" + ], + [ + "CMT_FIFO_NW2A3_5", + "CMT_TOP_NW2A3_6" + ], + [ + "CMT_FIFO_EE2BEG3_6", + "CMT_TOP_EE2BEG3_7" + ], + [ + "CMT_FIFO_WW2A2_7", + "CMT_TOP_WW2A2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_11" + ], + [ + "CMT_FIFO_L_IMUX1_8", + "CMT_TOP_IMUX1_9" + ], + [ + "CMT_FIFO_SW4END0_10", + "CMT_TOP_SW4END0_11" + ], + [ + "CMT_FIFO_WW4B0_8", + "CMT_TOP_WW4B0_9" + ], + [ + "CMT_FIFO_SW4A0_2", + "CMT_TOP_SW4A0_3" + ], + [ + "CMT_FIFO_SE4BEG1_6", + "CMT_TOP_SE4BEG1_7" + ], + [ + "CMT_FIFO_L_IMUX45_0", + "CMT_TOP_IMUX45_1" + ], + [ + "CMT_FIFO_L_BYP4_5", + "CMT_TOP_BYP4_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_9", + "CMT_TOP_LOGIC_OUTS_L_B18_10" + ], + [ + "CMT_FIFO_EL1BEG1_4", + "CMT_TOP_EL1BEG1_5" + ], + [ + "CMT_FIFO_SE4BEG2_3", + "CMT_TOP_SE4BEG2_4" + ], + [ + "CMT_FIFO_L_CLK1_3", + "CMT_TOP_CLK1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_7", + "CMT_TOP_LOGIC_OUTS_L_B8_8" + ], + [ + "CMT_FIFO_L_IMUX46_10", + "CMT_TOP_IMUX46_11" + ], + [ + "CMT_FIFO_SE2A2_10", + "CMT_TOP_SE2A2_11" + ], + [ + "CMT_FIFO_SE4C1_0", + "CMT_TOP_SE4C1_1" + ], + [ + "CMT_FIFO_SW4A1_2", + "CMT_TOP_SW4A1_3" + ], + [ + "CMT_FIFO_WW2END0_10", + "CMT_TOP_WW2END0_11" + ], + [ + "CMT_FIFO_L_IMUX10_11", + "CMT_TOP_IMUX10_12" + ], + [ + "CMT_FIFO_L_IMUX15_10", + "CMT_TOP_IMUX15_11" + ], + [ + "CMT_FIFO_ER1BEG3_6", + "CMT_TOP_ER1BEG3_7" + ], + [ + "CMT_FIFO_L_FAN1_4", + "CMT_TOP_FAN1_5" + ], + [ + "CMT_FIFO_LH1_6", + "CMT_TOP_LH1_7" + ], + [ + "CMT_FIFO_NW4A2_2", + "CMT_TOP_NW4A2_3" + ], + [ + "CMT_FIFO_NW2A3_4", + "CMT_TOP_NW2A3_5" + ], + [ + "CMT_FIFO_L_IMUX19_0", + "CMT_TOP_IMUX19_1" + ], + [ + "CMT_FIFO_SE4BEG0_6", + "CMT_TOP_SE4BEG0_7" + ], + [ + "CMT_FIFO_NE4BEG1_3", + "CMT_TOP_NE4BEG1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_5", + "CMT_TOP_LOGIC_OUTS_L_B5_6" + ], + [ + "CMT_FIFO_NE4C1_8", + "CMT_TOP_NE4C1_9" + ], + [ + "CMT_FIFO_L_FAN7_3", + "CMT_TOP_FAN7_4" + ], + [ + "CMT_FIFO_L_IMUX4_8", + "CMT_TOP_IMUX4_9" + ], + [ + "CMT_FIFO_NE4BEG2_1", + "CMT_TOP_NE4BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX28_2", + "CMT_TOP_IMUX28_3" + ], + [ + "CMT_FIFO_WR1END0_0", + "CMT_TOP_WR1END0_1" + ], + [ + "CMT_FIFO_L_IMUX36_1", + "CMT_TOP_IMUX36_2" + ], + [ + "CMT_FIFO_SW4A1_1", + "CMT_TOP_SW4A1_2" + ], + [ + "CMT_FIFO_WW4END1_3", + "CMT_TOP_WW4END1_4" + ], + [ + "CMT_FIFO_L_FAN1_9", + "CMT_TOP_FAN1_10" + ], + [ + "CMT_FIFO_WR1END2_6", + "CMT_TOP_WR1END2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_8", + "CMT_TOP_LOGIC_OUTS_L_B2_9" + ], + [ + "CMT_FIFO_SE4C1_9", + "CMT_TOP_SE4C1_10" + ], + [ + "CMT_FIFO_L_IMUX7_4", + "CMT_TOP_IMUX7_5" + ], + [ + "CMT_FIFO_EE4C3_2", + "CMT_TOP_EE4C3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_8", + "CMT_TOP_LOGIC_OUTS_L_B7_9" + ], + [ + "CMT_FIFO_LH10_0", + "CMT_TOP_LH10_1" + ], + [ + "CMT_FIFO_EE4C3_4", + "CMT_TOP_EE4C3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_7", + "CMT_TOP_LOGIC_OUTS_L_B10_8" + ], + [ + "CMT_FIFO_WL1END3_4", + "CMT_TOP_WL1END3_5" + ], + [ + "CMT_FIFO_L_IMUX33_2", + "CMT_TOP_IMUX33_3" + ], + [ + "CMT_FIFO_L_IMUX18_8", + "CMT_TOP_IMUX18_9" + ], + [ + "CMT_FIFO_WW4C0_9", + "CMT_TOP_WW4C0_10" + ], + [ + "CMT_FIFO_L_IMUX32_3", + "CMT_TOP_IMUX32_4" + ], + [ + "CMT_FIFO_LH12_6", + "CMT_TOP_LH12_7" + ], + [ + "CMT_FIFO_WW4C1_8", + "CMT_TOP_WW4C1_9" + ], + [ + "CMT_FIFO_L_FAN6_0", + "CMT_TOP_FAN6_1" + ], + [ + "CMT_FIFO_L_IMUX10_5", + "CMT_TOP_IMUX10_6" + ], + [ + "CMT_FIFO_WL1END2_1", + "CMT_TOP_WL1END2_2" + ], + [ + "CMT_FIFO_L_IMUX21_8", + "CMT_TOP_IMUX21_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_0", + "CMT_TOP_LOGIC_OUTS_L_B5_1" + ], + [ + "CMT_FIFO_SE2A2_1", + "CMT_TOP_SE2A2_2" + ], + [ + "CMT_FIFO_LH3_11", + "CMT_TOP_LH3_12" + ], + [ + "CMT_FIFO_SW4A3_11", + "CMT_TOP_SW4A3_12" + ], + [ + "CMT_FIFO_NE2A1_7", + "CMT_TOP_NE2A1_8" + ], + [ + "CMT_FIFO_LH1_1", + "CMT_TOP_LH1_2" + ], + [ + "CMT_FIFO_L_IMUX29_1", + "CMT_TOP_IMUX29_2" + ], + [ + "CMT_FIFO_L_FAN6_1", + "CMT_TOP_FAN6_2" + ], + [ + "CMT_FIFO_EE2BEG2_10", + "CMT_TOP_EE2BEG2_11" + ], + [ + "CMT_FIFO_NW4END2_7", + "CMT_TOP_NW4END2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_11", + "CMT_TOP_LOGIC_OUTS_L_B13_12" + ], + [ + "CMT_FIFO_L_BYP0_1", + "CMT_TOP_BYP0_2" + ], + [ + "CMT_FIFO_EE4A1_11", + "CMT_TOP_EE4A1_12" + ], + [ + "CMT_FIFO_L_IMUX30_8", + "CMT_TOP_IMUX30_9" + ], + [ + "CMT_FIFO_WL1END3_5", + "CMT_TOP_WL1END3_6" + ], + [ + "CMT_FIFO_L_IMUX45_2", + "CMT_TOP_IMUX45_3" + ], + [ + "CMT_FIFO_L_FAN6_5", + "CMT_TOP_FAN6_6" + ], + [ + "CMT_FIFO_WL1END2_8", + "CMT_TOP_WL1END2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_1", + "CMT_TOP_LOGIC_OUTS_L_B4_2" + ], + [ + "CMT_FIFO_EE4A2_5", + "CMT_TOP_EE4A2_6" + ], + [ + "CMT_FIFO_WL1END2_10", + "CMT_TOP_WL1END2_11" + ], + [ + "CMT_FIFO_L_IMUX24_8", + "CMT_TOP_IMUX24_9" + ], + [ + "CMT_FIFO_LH11_5", + "CMT_TOP_LH11_6" + ], + [ + "CMT_FIFO_NW2A2_1", + "CMT_TOP_NW2A2_2" + ], + [ + "CMT_FIFO_L_BYP6_1", + "CMT_TOP_BYP6_2" + ], + [ + "CMT_FIFO_SE2A0_1", + "CMT_TOP_SE2A0_2" + ], + [ + "CMT_FIFO_SE2A3_9", + "CMT_TOP_SE2A3_10" + ], + [ + "CMT_FIFO_L_IMUX47_11", + "CMT_TOP_IMUX47_12" + ], + [ + "CMT_FIFO_EE4A2_8", + "CMT_TOP_EE4A2_9" + ], + [ + "CMT_FIFO_L_BYP2_4", + "CMT_TOP_BYP2_5" + ], + [ + "CMT_FIFO_L_BYP2_8", + "CMT_TOP_BYP2_9" + ], + [ + "CMT_FIFO_L_IMUX41_11", + "CMT_TOP_IMUX41_12" + ], + [ + "CMT_FIFO_L_IMUX35_6", + "CMT_TOP_IMUX35_7" + ], + [ + "CMT_FIFO_SE2A2_5", + "CMT_TOP_SE2A2_6" + ], + [ + "CMT_FIFO_L_FAN7_6", + "CMT_TOP_FAN7_7" + ], + [ + "CMT_FIFO_L_BYP7_8", + "CMT_TOP_BYP7_9" + ], + [ + "CMT_FIFO_SE4C0_9", + "CMT_TOP_SE4C0_10" + ], + [ + "CMT_FIFO_EE4C3_6", + "CMT_TOP_EE4C3_7" + ], + [ + "CMT_FIFO_EL1BEG1_3", + "CMT_TOP_EL1BEG1_4" + ], + [ + "CMT_FIFO_SE4BEG2_4", + "CMT_TOP_SE4BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX25_0", + "CMT_TOP_IMUX25_1" + ], + [ + "CMT_FIFO_L_IMUX29_6", + "CMT_TOP_IMUX29_7" + ], + [ + "CMT_FIFO_L_BYP6_6", + "CMT_TOP_BYP6_7" + ], + [ + "CMT_FIFO_L_IMUX1_10", + "CMT_TOP_IMUX1_11" + ], + [ + "CMT_FIFO_L_IMUX35_4", + "CMT_TOP_IMUX35_5" + ], + [ + "CMT_FIFO_EL1BEG1_5", + "CMT_TOP_EL1BEG1_6" + ], + [ + "CMT_FIFO_L_CLK1_5", + "CMT_TOP_CLK1_6" + ], + [ + "CMT_FIFO_L_BYP5_5", + "CMT_TOP_BYP5_6" + ], + [ + "CMT_FIFO_EE2BEG1_6", + "CMT_TOP_EE2BEG1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_9", + "CMT_TOP_LOGIC_OUTS_L_B4_10" + ], + [ + "CMT_FIFO_WW4B2_0", + "CMT_TOP_WW4B2_1" + ], + [ + "CMT_FIFO_SW4A3_1", + "CMT_TOP_SW4A3_2" + ], + [ + "CMT_FIFO_L_PHASER_WRENABLE", + "CMT_MMCM_A_WREN_TOFIFO" + ], + [ + "CMT_FIFO_NE4BEG2_9", + "CMT_TOP_NE4BEG2_10" + ], + [ + "CMT_FIFO_WW4A2_4", + "CMT_TOP_WW4A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_0", + "CMT_TOP_LOGIC_OUTS_L_B13_1" + ], + [ + "CMT_FIFO_SW4A2_11", + "CMT_TOP_SW4A2_12" + ], + [ + "CMT_FIFO_EE4BEG2_8", + "CMT_TOP_EE4BEG2_9" + ], + [ + "CMT_FIFO_L_FAN4_10", + "CMT_TOP_FAN4_11" + ], + [ + "CMT_FIFO_EE4C0_2", + "CMT_TOP_EE4C0_3" + ], + [ + "CMT_FIFO_L_IMUX39_0", + "CMT_TOP_IMUX39_1" + ], + [ + "CMT_FIFO_EE4BEG1_11", + "CMT_TOP_EE4BEG1_12" + ], + [ + "CMT_FIFO_SE2A3_8", + "CMT_TOP_SE2A3_9" + ], + [ + "CMT_FIFO_WW4C1_6", + "CMT_TOP_WW4C1_7" + ], + [ + "CMT_FIFO_EE4C2_0", + "CMT_TOP_EE4C2_1" + ], + [ + "CMT_FIFO_SW2A2_8", + "CMT_TOP_SW2A2_9" + ], + [ + "CMT_FIFO_EE2A3_9", + "CMT_TOP_EE2A3_10" + ], + [ + "CMT_FIFO_L_IMUX29_2", + "CMT_TOP_IMUX29_3" + ], + [ + "CMT_FIFO_L_IMUX41_9", + "CMT_TOP_IMUX41_10" + ], + [ + "CMT_FIFO_LH1_2", + "CMT_TOP_LH1_3" + ], + [ + "CMT_FIFO_NW4END3_10", + "CMT_TOP_NW4END3_11" + ], + [ + "CMT_FIFO_L_IMUX13_0", + "CMT_TOP_IMUX13_1" + ], + [ + "CMT_FIFO_SW2A2_2", + "CMT_TOP_SW2A2_3" + ], + [ + "CMT_FIFO_L_IMUX33_10", + "CMT_TOP_IMUX33_11" + ], + [ + "CMT_FIFO_SE4C0_5", + "CMT_TOP_SE4C0_6" + ], + [ + "CMT_FIFO_SW4END0_7", + "CMT_TOP_SW4END0_8" + ], + [ + "CMT_FIFO_L_IMUX16_3", + "CMT_TOP_IMUX16_4" + ], + [ + "CMT_FIFO_WW2A0_0", + "CMT_TOP_WW2A0_1" + ], + [ + "CMT_FIFO_L_IMUX21_2", + "CMT_TOP_IMUX21_3" + ], + [ + "CMT_FIFO_EL1BEG1_8", + "CMT_TOP_EL1BEG1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_4", + "CMT_TOP_LOGIC_OUTS_L_B1_5" + ], + [ + "CMT_FIFO_L_IMUX1_11", + "CMT_TOP_IMUX1_12" + ], + [ + "CMT_FIFO_L_IMUX41_1", + "CMT_TOP_IMUX41_2" + ], + [ + "CMT_FIFO_SW2A3_0", + "CMT_TOP_SW2A3_1" + ], + [ + "CMT_FIFO_L_PHASER_RDCLK", + "CMT_MMCM_A_RDCLK_TOFIFO" + ], + [ + "CMT_FIFO_SE4BEG0_2", + "CMT_TOP_SE4BEG0_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "CMT_TOP_OCLKDIV_9" + ], + [ + "CMT_FIFO_L_BYP7_11", + "CMT_TOP_BYP7_12" + ], + [ + "CMT_FIFO_WL1END0_7", + "CMT_TOP_WL1END0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_0", + "CMT_TOP_LOGIC_OUTS_L_B1_1" + ], + [ + "CMT_FIFO_L_IMUX33_4", + "CMT_TOP_IMUX33_5" + ], + [ + "CMT_FIFO_WL1END2_9", + "CMT_TOP_WL1END2_10" + ], + [ + "CMT_FIFO_WW2END0_8", + "CMT_TOP_WW2END0_9" + ], + [ + "CMT_FIFO_WW4A0_6", + "CMT_TOP_WW4A0_7" + ], + [ + "CMT_FIFO_L_CTRL0_3", + "CMT_TOP_CTRL0_4" + ], + [ + "CMT_FIFO_L_IMUX6_11", + "CMT_TOP_IMUX6_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_8", + "CMT_TOP_LOGIC_OUTS_L_B19_9" + ], + [ + "CMT_FIFO_NE4C1_9", + "CMT_TOP_NE4C1_10" + ], + [ + "CMT_FIFO_EE4A2_2", + "CMT_TOP_EE4A2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_5", + "CMT_TOP_LOGIC_OUTS_L_B7_6" + ], + [ + "CMT_FIFO_L_FAN2_0", + "CMT_TOP_FAN2_1" + ], + [ + "CMT_FIFO_SW4A1_4", + "CMT_TOP_SW4A1_5" + ], + [ + "CMT_FIFO_L_IMUX43_9", + "CMT_TOP_IMUX43_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_8", + "CMT_TOP_LOGIC_OUTS_L_B20_9" + ], + [ + "CMT_FIFO_L_IMUX34_6", + "CMT_TOP_IMUX34_7" + ], + [ + "CMT_FIFO_L_IMUX46_2", + "CMT_TOP_IMUX46_3" + ], + [ + "CMT_FIFO_L_IMUX47_4", + "CMT_TOP_IMUX47_5" + ], + [ + "CMT_FIFO_LH3_8", + "CMT_TOP_LH3_9" + ], + [ + "CMT_FIFO_L_IMUX2_6", + "CMT_TOP_IMUX2_7" + ], + [ + "CMT_FIFO_L_FAN2_10", + "CMT_TOP_FAN2_11" + ], + [ + "CMT_FIFO_WW4END0_10", + "CMT_TOP_WW4END0_11" + ], + [ + "CMT_FIFO_SE4C1_2", + "CMT_TOP_SE4C1_3" + ], + [ + "CMT_FIFO_L_IMUX42_10", + "CMT_TOP_IMUX42_11" + ], + [ + "CMT_FIFO_SW4END1_6", + "CMT_TOP_SW4END1_7" + ], + [ + "CMT_FIFO_L_BYP7_6", + "CMT_TOP_BYP7_7" + ], + [ + "CMT_FIFO_NE4C3_0", + "CMT_TOP_NE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX45_5", + "CMT_TOP_IMUX45_6" + ], + [ + "CMT_FIFO_L_IMUX39_3", + "CMT_TOP_IMUX39_4" + ], + [ + "CMT_FIFO_L_IMUX30_1", + "CMT_TOP_IMUX30_2" + ], + [ + "CMT_FIFO_EL1BEG2_11", + "CMT_TOP_EL1BEG2_12" + ], + [ + "CMT_FIFO_L_IMUX31_10", + "CMT_TOP_IMUX31_11" + ], + [ + "CMT_FIFO_L_IMUX31_9", + "CMT_TOP_IMUX31_10" + ], + [ + "CMT_FIFO_L_IMUX6_1", + "CMT_TOP_IMUX6_2" + ], + [ + "CMT_FIFO_SW2A2_11", + "CMT_TOP_SW2A2_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_1", + "CMT_TOP_LOGIC_OUTS_L_B11_2" + ], + [ + "CMT_FIFO_L_IMUX11_7", + "CMT_TOP_IMUX11_8" + ], + [ + "CMT_FIFO_L_IMUX37_4", + "CMT_TOP_IMUX37_5" + ], + [ + "CMT_FIFO_EL1BEG1_1", + "CMT_TOP_EL1BEG1_2" + ], + [ + "CMT_FIFO_LH7_10", + "CMT_TOP_LH7_11" + ], + [ + "CMT_FIFO_EE2A1_7", + "CMT_TOP_EE2A1_8" + ], + [ + "CMT_FIFO_EE4BEG2_0", + "CMT_TOP_EE4BEG2_1" + ], + [ + "CMT_FIFO_EE2BEG1_1", + "CMT_TOP_EE2BEG1_2" + ], + [ + "CMT_FIFO_L_IMUX24_6", + "CMT_TOP_IMUX24_7" + ], + [ + "CMT_FIFO_EE4BEG0_10", + "CMT_TOP_EE4BEG0_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "CMT_TOP_OCLKDIV_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "CMT_TOP_ICLKDIV_5" + ], + [ + "CMT_FIFO_L_IMUX20_8", + "CMT_TOP_IMUX20_9" + ], + [ + "CMT_FIFO_LH3_0", + "CMT_TOP_LH3_1" + ], + [ + "CMT_FIFO_SW2A0_2", + "CMT_TOP_SW2A0_3" + ], + [ + "CMT_FIFO_WW2A3_6", + "CMT_TOP_WW2A3_7" + ], + [ + "CMT_FIFO_L_IMUX22_1", + "CMT_TOP_IMUX22_2" + ], + [ + "CMT_FIFO_LH8_7", + "CMT_TOP_LH8_8" + ], + [ + "CMT_FIFO_L_IMUX45_1", + "CMT_TOP_IMUX45_2" + ], + [ + "CMT_FIFO_EE4A0_1", + "CMT_TOP_EE4A0_2" + ], + [ + "CMT_FIFO_WW2END1_5", + "CMT_TOP_WW2END1_6" + ], + [ + "CMT_FIFO_L_BYP1_6", + "CMT_TOP_BYP1_7" + ], + [ + "CMT_FIFO_SW4A3_4", + "CMT_TOP_SW4A3_5" + ], + [ + "CMT_FIFO_L_CLK0_3", + "CMT_TOP_CLK0_4" + ], + [ + "CMT_FIFO_ER1BEG2_9", + "CMT_TOP_ER1BEG2_10" + ], + [ + "CMT_FIFO_NE4BEG2_4", + "CMT_TOP_NE4BEG2_5" + ], + [ + "CMT_FIFO_SW4END0_5", + "CMT_TOP_SW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX0_10", + "CMT_TOP_IMUX0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_3", + "CMT_TOP_LOGIC_OUTS_L_B23_4" + ], + [ + "CMT_FIFO_L_IMUX26_9", + "CMT_TOP_IMUX26_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_10", + "CMT_TOP_LOGIC_OUTS_L_B11_11" + ], + [ + "CMT_FIFO_EE4B0_1", + "CMT_TOP_EE4B0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_8", + "CMT_TOP_LOGIC_OUTS_L_B13_9" + ], + [ + "CMT_FIFO_EE4B2_10", + "CMT_TOP_EE4B2_11" + ], + [ + "CMT_FIFO_L_IMUX4_11", + "CMT_TOP_IMUX4_12" + ], + [ + "CMT_FIFO_NW2A1_5", + "CMT_TOP_NW2A1_6" + ], + [ + "CMT_FIFO_L_IMUX17_8", + "CMT_TOP_IMUX17_9" + ], + [ + "CMT_FIFO_EL1BEG3_1", + "CMT_TOP_EL1BEG3_2" + ], + [ + "CMT_FIFO_L_BYP1_1", + "CMT_TOP_BYP1_2" + ], + [ + "CMT_FIFO_L_IMUX38_3", + "CMT_TOP_IMUX38_4" + ], + [ + "CMT_FIFO_WW4END1_10", + "CMT_TOP_WW4END1_11" + ], + [ + "CMT_FIFO_SW4A0_8", + "CMT_TOP_SW4A0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_6", + "CMT_TOP_LOGIC_OUTS_L_B6_7" + ], + [ + "CMT_FIFO_L_IMUX40_5", + "CMT_TOP_IMUX40_6" + ], + [ + "CMT_FIFO_WW2A0_6", + "CMT_TOP_WW2A0_7" + ], + [ + "CMT_FIFO_LH1_7", + "CMT_TOP_LH1_8" + ], + [ + "CMT_FIFO_L_IMUX17_1", + "CMT_TOP_IMUX17_2" + ], + [ + "CMT_FIFO_L_IMUX43_2", + "CMT_TOP_IMUX43_3" + ], + [ + "CMT_FIFO_L_BYP2_6", + "CMT_TOP_BYP2_7" + ], + [ + "CMT_FIFO_SW2A0_3", + "CMT_TOP_SW2A0_4" + ], + [ + "CMT_FIFO_L_IMUX16_8", + "CMT_TOP_IMUX16_9" + ], + [ + "CMT_FIFO_EE4C3_7", + "CMT_TOP_EE4C3_8" + ], + [ + "CMT_FIFO_SE4C1_4", + "CMT_TOP_SE4C1_5" + ], + [ + "CMT_FIFO_EE2A1_1", + "CMT_TOP_EE2A1_2" + ], + [ + "CMT_FIFO_L_IMUX17_11", + "CMT_TOP_IMUX17_12" + ], + [ + "CMT_FIFO_NW2A3_11", + "CMT_TOP_NW2A3_12" + ], + [ + "CMT_FIFO_L_IMUX44_11", + "CMT_TOP_IMUX44_12" + ], + [ + "CMT_FIFO_WW2END3_7", + "CMT_TOP_WW2END3_8" + ], + [ + "CMT_FIFO_NW2A2_9", + "CMT_TOP_NW2A2_10" + ], + [ + "CMT_FIFO_WR1END2_3", + "CMT_TOP_WR1END2_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "CMT_TOP_ICLK_4" + ], + [ + "CMT_FIFO_WW4A2_10", + "CMT_TOP_WW4A2_11" + ], + [ + "CMT_FIFO_EL1BEG0_4", + "CMT_TOP_EL1BEG0_5" + ], + [ + "CMT_FIFO_WR1END3_1", + "CMT_TOP_WR1END3_2" + ], + [ + "CMT_FIFO_WW4C1_10", + "CMT_TOP_WW4C1_11" + ], + [ + "CMT_FIFO_LH8_0", + "CMT_TOP_LH8_1" + ], + [ + "CMT_FIFO_ER1BEG1_4", + "CMT_TOP_ER1BEG1_5" + ], + [ + "CMT_FIFO_WR1END0_2", + "CMT_TOP_WR1END0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_2", + "CMT_TOP_LOGIC_OUTS_L_B23_3" + ], + [ + "CMT_FIFO_SW4A2_9", + "CMT_TOP_SW4A2_10" + ], + [ + "CMT_FIFO_L_FAN0_3", + "CMT_TOP_FAN0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_2", + "CMT_TOP_LOGIC_OUTS_L_B12_3" + ], + [ + "CMT_FIFO_SW4A2_10", + "CMT_TOP_SW4A2_11" + ], + [ + "CMT_FIFO_L_IMUX37_9", + "CMT_TOP_IMUX37_10" + ], + [ + "CMT_FIFO_L_IMUX5_10", + "CMT_TOP_IMUX5_11" + ], + [ + "CMT_FIFO_L_IMUX6_5", + "CMT_TOP_IMUX6_6" + ], + [ + "CMT_FIFO_SE4C2_4", + "CMT_TOP_SE4C2_5" + ], + [ + "CMT_FIFO_WR1END1_5", + "CMT_TOP_WR1END1_6" + ], + [ + "CMT_FIFO_NE4BEG0_9", + "CMT_TOP_NE4BEG0_10" + ], + [ + "CMT_FIFO_L_IMUX35_0", + "CMT_TOP_IMUX35_1" + ], + [ + "CMT_FIFO_L_CTRL0_6", + "CMT_TOP_CTRL0_7" + ], + [ + "CMT_FIFO_WW4END3_0", + "CMT_TOP_WW4END3_1" + ], + [ + "CMT_FIFO_WW2END2_5", + "CMT_TOP_WW2END2_6" + ], + [ + "CMT_FIFO_LH10_5", + "CMT_TOP_LH10_6" + ], + [ + "CMT_FIFO_L_CTRL0_9", + "CMT_TOP_CTRL0_10" + ], + [ + "CMT_FIFO_L_IMUX23_10", + "CMT_TOP_IMUX23_11" + ], + [ + "CMT_FIFO_L_IMUX15_9", + "CMT_TOP_IMUX15_10" + ], + [ + "CMT_FIFO_NE2A1_8", + "CMT_TOP_NE2A1_9" + ], + [ + "CMT_FIFO_SE2A1_8", + "CMT_TOP_SE2A1_9" + ], + [ + "CMT_FIFO_L_FAN7_4", + "CMT_TOP_FAN7_5" + ], + [ + "CMT_FIFO_L_IMUX7_8", + "CMT_TOP_IMUX7_9" + ], + [ + "CMT_FIFO_L_BYP7_7", + "CMT_TOP_BYP7_8" + ], + [ + "CMT_FIFO_WW4C3_5", + "CMT_TOP_WW4C3_6" + ], + [ + "CMT_FIFO_L_IMUX13_3", + "CMT_TOP_IMUX13_4" + ], + [ + "CMT_FIFO_L_IMUX18_0", + "CMT_TOP_IMUX18_1" + ], + [ + "CMT_FIFO_SE4C0_0", + "CMT_TOP_SE4C0_1" + ], + [ + "CMT_FIFO_WW2END2_11", + "CMT_TOP_WW2END2_12" + ], + [ + "CMT_FIFO_L_IMUX24_9", + "CMT_TOP_IMUX24_10" + ], + [ + "CMT_FIFO_NW4A0_9", + "CMT_TOP_NW4A0_10" + ], + [ + "CMT_FIFO_LH6_6", + "CMT_TOP_LH6_7" + ], + [ + "CMT_FIFO_EL1BEG1_7", + "CMT_TOP_EL1BEG1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_4", + "CMT_TOP_LOGIC_OUTS_L_B7_5" + ], + [ + "CMT_FIFO_NE4BEG0_4", + "CMT_TOP_NE4BEG0_5" + ], + [ + "CMT_FIFO_WW4A3_8", + "CMT_TOP_WW4A3_9" + ], + [ + "CMT_FIFO_LH1_8", + "CMT_TOP_LH1_9" + ], + [ + "CMT_FIFO_L_FAN5_2", + "CMT_TOP_FAN5_3" + ], + [ + "CMT_FIFO_L_CTRL1_2", + "CMT_TOP_CTRL1_3" + ], + [ + "CMT_FIFO_EE4A1_7", + "CMT_TOP_EE4A1_8" + ], + [ + "CMT_FIFO_NE4BEG1_10", + "CMT_TOP_NE4BEG1_11" + ], + [ + "CMT_FIFO_SE4C0_10", + "CMT_TOP_SE4C0_11" + ], + [ + "CMT_FIFO_LH7_3", + "CMT_TOP_LH7_4" + ], + [ + "CMT_FIFO_WL1END0_8", + "CMT_TOP_WL1END0_9" + ], + [ + "CMT_FIFO_SW4A3_2", + "CMT_TOP_SW4A3_3" + ], + [ + "CMT_FIFO_L_BYP5_6", + "CMT_TOP_BYP5_7" + ], + [ + "CMT_FIFO_L_BYP5_9", + "CMT_TOP_BYP5_10" + ], + [ + "CMT_FIFO_L_IMUX5_9", + "CMT_TOP_IMUX5_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_3", + "CMT_TOP_LOGIC_OUTS_L_B4_4" + ], + [ + "CMT_FIFO_NW4END3_7", + "CMT_TOP_NW4END3_8" + ], + [ + "CMT_FIFO_NE4BEG3_5", + "CMT_TOP_NE4BEG3_6" + ], + [ + "CMT_FIFO_MONITOR_N_8", + "CMT_TOP_MONITOR_N_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_0", + "CMT_TOP_LOGIC_OUTS_L_B11_1" + ], + [ + "CMT_FIFO_LH6_5", + "CMT_TOP_LH6_6" + ], + [ + "CMT_FIFO_WL1END0_11", + "CMT_TOP_WL1END0_12" + ], + [ + "CMT_FIFO_L_IMUX18_3", + "CMT_TOP_IMUX18_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_4" + ], + [ + "CMT_FIFO_LH2_3", + "CMT_TOP_LH2_4" + ], + [ + "CMT_FIFO_EE4B3_1", + "CMT_TOP_EE4B3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_9", + "CMT_TOP_LOGIC_OUTS_L_B11_10" + ], + [ + "CMT_FIFO_NE4C2_1", + "CMT_TOP_NE4C2_2" + ], + [ + "CMT_FIFO_L_IMUX8_7", + "CMT_TOP_IMUX8_8" + ], + [ + "CMT_FIFO_WR1END1_8", + "CMT_TOP_WR1END1_9" + ], + [ + "CMT_FIFO_WW4A1_8", + "CMT_TOP_WW4A1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_3", + "CMT_TOP_LOGIC_OUTS_L_B12_4" + ], + [ + "CMT_FIFO_EE2BEG3_5", + "CMT_TOP_EE2BEG3_6" + ], + [ + "CMT_FIFO_EE4C0_6", + "CMT_TOP_EE4C0_7" + ], + [ + "CMT_FIFO_ER1BEG3_3", + "CMT_TOP_ER1BEG3_4" + ], + [ + "CMT_FIFO_L_IMUX31_0", + "CMT_TOP_IMUX31_1" + ], + [ + "CMT_FIFO_WW4B0_6", + "CMT_TOP_WW4B0_7" + ], + [ + "CMT_FIFO_NE4BEG3_1", + "CMT_TOP_NE4BEG3_2" + ], + [ + "CMT_FIFO_LH8_1", + "CMT_TOP_LH8_2" + ], + [ + "CMT_FIFO_EE4B3_9", + "CMT_TOP_EE4B3_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "CMT_TOP_OCLK_1" + ], + [ + "CMT_FIFO_L_IMUX45_3", + "CMT_TOP_IMUX45_4" + ], + [ + "CMT_FIFO_L_IMUX37_11", + "CMT_TOP_IMUX37_12" + ], + [ + "CMT_FIFO_ER1BEG0_11", + "CMT_TOP_ER1BEG0_12" + ], + [ + "CMT_FIFO_WW2END3_9", + "CMT_TOP_WW2END3_10" + ], + [ + "CMT_FIFO_EE4B3_11", + "CMT_TOP_EE4B3_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_3", + "CMT_TOP_LOGIC_OUTS_L_B2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_9", + "CMT_TOP_LOGIC_OUTS_L_B15_10" + ], + [ + "CMT_FIFO_L_CLK0_9", + "CMT_TOP_CLK0_10" + ], + [ + "CMT_FIFO_NW4END1_2", + "CMT_TOP_NW4END1_3" + ], + [ + "CMT_FIFO_WW4A3_9", + "CMT_TOP_WW4A3_10" + ], + [ + "CMT_FIFO_NE4BEG0_0", + "CMT_TOP_NE4BEG0_1" + ], + [ + "CMT_FIFO_L_IMUX20_10", + "CMT_TOP_IMUX20_11" + ], + [ + "CMT_FIFO_L_IMUX34_3", + "CMT_TOP_IMUX34_4" + ], + [ + "CMT_FIFO_L_IMUX27_6", + "CMT_TOP_IMUX27_7" + ], + [ + "CMT_FIFO_WL1END1_4", + "CMT_TOP_WL1END1_5" + ], + [ + "CMT_FIFO_EE4C3_9", + "CMT_TOP_EE4C3_10" + ], + [ + "CMT_FIFO_NE4C2_11", + "CMT_TOP_NE4C2_12" + ], + [ + "CMT_FIFO_WL1END2_6", + "CMT_TOP_WL1END2_7" + ], + [ + "CMT_FIFO_EE4C0_7", + "CMT_TOP_EE4C0_8" + ], + [ + "CMT_FIFO_WR1END2_7", + "CMT_TOP_WR1END2_8" + ], + [ + "CMT_FIFO_L_IMUX40_8", + "CMT_TOP_IMUX40_9" + ], + [ + "CMT_FIFO_EE4C1_5", + "CMT_TOP_EE4C1_6" + ], + [ + "CMT_FIFO_L_IMUX34_11", + "CMT_TOP_IMUX34_12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "CMT_TOP_OCLK_11" + ], + [ + "CMT_FIFO_EE4B3_0", + "CMT_TOP_EE4B3_1" + ], + [ + "CMT_FIFO_L_IMUX7_11", + "CMT_TOP_IMUX7_12" + ], + [ + "CMT_FIFO_L_CLK1_2", + "CMT_TOP_CLK1_3" + ], + [ + "CMT_FIFO_L_IMUX34_0", + "CMT_TOP_IMUX34_1" + ], + [ + "CMT_FIFO_LH11_1", + "CMT_TOP_LH11_2" + ], + [ + "CMT_FIFO_NW4A3_10", + "CMT_TOP_NW4A3_11" + ], + [ + "CMT_FIFO_WL1END2_7", + "CMT_TOP_WL1END2_8" + ], + [ + "CMT_FIFO_SE2A2_6", + "CMT_TOP_SE2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_2", + "CMT_TOP_LOGIC_OUTS_L_B17_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_5", + "CMT_TOP_LOGIC_OUTS_L_B19_6" + ], + [ + "CMT_FIFO_L_IMUX25_6", + "CMT_TOP_IMUX25_7" + ], + [ + "CMT_FIFO_EE4B0_10", + "CMT_TOP_EE4B0_11" + ], + [ + "CMT_FIFO_NE4C1_10", + "CMT_TOP_NE4C1_11" + ], + [ + "CMT_FIFO_L_FAN1_7", + "CMT_TOP_FAN1_8" + ], + [ + "CMT_FIFO_WW4END2_5", + "CMT_TOP_WW4END2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_10", + "CMT_TOP_LOGIC_OUTS_L_B22_11" + ], + [ + "CMT_FIFO_L_IMUX25_5", + "CMT_TOP_IMUX25_6" + ], + [ + "CMT_FIFO_NW4A2_8", + "CMT_TOP_NW4A2_9" + ], + [ + "CMT_FIFO_L_BYP5_4", + "CMT_TOP_BYP5_5" + ], + [ + "CMT_FIFO_L_FAN7_1", + "CMT_TOP_FAN7_2" + ], + [ + "CMT_FIFO_NW4END0_9", + "CMT_TOP_NW4END0_10" + ], + [ + "CMT_FIFO_NW2A0_0", + "CMT_TOP_NW2A0_1" + ], + [ + "CMT_FIFO_WL1END2_0", + "CMT_TOP_WL1END2_1" + ], + [ + "CMT_FIFO_SE4BEG1_7", + "CMT_TOP_SE4BEG1_8" + ], + [ + "CMT_FIFO_L_BYP2_3", + "CMT_TOP_BYP2_4" + ], + [ + "CMT_FIFO_NW4A0_5", + "CMT_TOP_NW4A0_6" + ], + [ + "CMT_FIFO_L_IMUX18_4", + "CMT_TOP_IMUX18_5" + ], + [ + "CMT_FIFO_L_IMUX22_9", + "CMT_TOP_IMUX22_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "CMT_TOP_ICLKDIV_9" + ], + [ + "CMT_FIFO_SE4C0_2", + "CMT_TOP_SE4C0_3" + ], + [ + "CMT_FIFO_EE4A3_0", + "CMT_TOP_EE4A3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_3", + "CMT_TOP_LOGIC_OUTS_L_B5_4" + ], + [ + "CMT_FIFO_LH3_6", + "CMT_TOP_LH3_7" + ], + [ + "CMT_FIFO_LH5_11", + "CMT_TOP_LH5_12" + ], + [ + "CMT_FIFO_L_IMUX7_7", + "CMT_TOP_IMUX7_8" + ], + [ + "CMT_FIFO_L_IMUX38_6", + "CMT_TOP_IMUX38_7" + ], + [ + "CMT_FIFO_L_IMUX18_5", + "CMT_TOP_IMUX18_6" + ], + [ + "CMT_FIFO_L_BYP7_4", + "CMT_TOP_BYP7_5" + ], + [ + "CMT_FIFO_LH3_4", + "CMT_TOP_LH3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_7", + "CMT_TOP_LOGIC_OUTS_L_B3_8" + ], + [ + "CMT_FIFO_EE4B2_8", + "CMT_TOP_EE4B2_9" + ], + [ + "CMT_FIFO_WL1END1_5", + "CMT_TOP_WL1END1_6" + ], + [ + "CMT_FIFO_WW4END2_0", + "CMT_TOP_WW4END2_1" + ], + [ + "CMT_FIFO_WW4END0_8", + "CMT_TOP_WW4END0_9" + ], + [ + "CMT_FIFO_L_IMUX35_1", + "CMT_TOP_IMUX35_2" + ], + [ + "CMT_FIFO_L_IMUX15_6", + "CMT_TOP_IMUX15_7" + ], + [ + "CMT_FIFO_EE4A1_10", + "CMT_TOP_EE4A1_11" + ], + [ + "CMT_FIFO_SW4A2_7", + "CMT_TOP_SW4A2_8" + ], + [ + "CMT_FIFO_L_IMUX12_2", + "CMT_TOP_IMUX12_3" + ], + [ + "CMT_FIFO_WL1END3_7", + "CMT_TOP_WL1END3_8" + ], + [ + "CMT_FIFO_EE2BEG0_3", + "CMT_TOP_EE2BEG0_4" + ], + [ + "CMT_FIFO_EE4B0_0", + "CMT_TOP_EE4B0_1" + ], + [ + "CMT_FIFO_EL1BEG3_5", + "CMT_TOP_EL1BEG3_6" + ], + [ + "CMT_FIFO_L_IMUX29_10", + "CMT_TOP_IMUX29_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_5", + "CMT_TOP_LOGIC_OUTS_L_B13_6" + ], + [ + "CMT_FIFO_NW2A2_0", + "CMT_TOP_NW2A2_1" + ], + [ + "CMT_FIFO_LH6_1", + "CMT_TOP_LH6_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_8", + "CMT_TOP_LOGIC_OUTS_L_B1_9" + ], + [ + "CMT_FIFO_NE4BEG3_9", + "CMT_TOP_NE4BEG3_10" + ], + [ + "CMT_FIFO_NW4END1_9", + "CMT_TOP_NW4END1_10" + ], + [ + "CMT_FIFO_L_IMUX40_3", + "CMT_TOP_IMUX40_4" + ], + [ + "CMT_FIFO_EE2A0_5", + "CMT_TOP_EE2A0_6" + ], + [ + "CMT_FIFO_SW2A3_8", + "CMT_TOP_SW2A3_9" + ], + [ + "CMT_FIFO_LH7_2", + "CMT_TOP_LH7_3" + ], + [ + "CMT_FIFO_SE4BEG1_9", + "CMT_TOP_SE4BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX3_7", + "CMT_TOP_IMUX3_8" + ], + [ + "CMT_FIFO_L_IMUX32_4", + "CMT_TOP_IMUX32_5" + ], + [ + "CMT_FIFO_ER1BEG0_7", + "CMT_TOP_ER1BEG0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_4", + "CMT_TOP_LOGIC_OUTS_L_B15_5" + ], + [ + "CMT_FIFO_SE4BEG2_8", + "CMT_TOP_SE4BEG2_9" + ], + [ + "CMT_FIFO_L_IMUX8_5", + "CMT_TOP_IMUX8_6" + ], + [ + "CMT_FIFO_EL1BEG3_11", + "CMT_TOP_EL1BEG3_12" + ], + [ + "CMT_FIFO_SW2A3_7", + "CMT_TOP_SW2A3_8" + ], + [ + "CMT_FIFO_L_IMUX44_2", + "CMT_TOP_IMUX44_3" + ], + [ + "CMT_FIFO_SW4END0_1", + "CMT_TOP_SW4END0_2" + ], + [ + "CMT_FIFO_L_IMUX38_2", + "CMT_TOP_IMUX38_3" + ], + [ + "CMT_FIFO_EE2BEG0_9", + "CMT_TOP_EE2BEG0_10" + ], + [ + "CMT_FIFO_EL1BEG2_6", + "CMT_TOP_EL1BEG2_7" + ], + [ + "CMT_FIFO_WW4A0_2", + "CMT_TOP_WW4A0_3" + ], + [ + "CMT_FIFO_LH5_0", + "CMT_TOP_LH5_1" + ], + [ + "CMT_FIFO_NE4BEG1_2", + "CMT_TOP_NE4BEG1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_1", + "CMT_TOP_LOGIC_OUTS_L_B13_2" + ], + [ + "CMT_FIFO_L_IMUX21_4", + "CMT_TOP_IMUX21_5" + ], + [ + "CMT_FIFO_SW4A3_9", + "CMT_TOP_SW4A3_10" + ], + [ + "CMT_FIFO_L_FAN2_1", + "CMT_TOP_FAN2_2" + ], + [ + "CMT_FIFO_LH11_9", + "CMT_TOP_LH11_10" + ], + [ + "CMT_FIFO_SE4BEG3_8", + "CMT_TOP_SE4BEG3_9" + ], + [ + "CMT_FIFO_L_FAN6_2", + "CMT_TOP_FAN6_3" + ], + [ + "CMT_FIFO_WW4END0_9", + "CMT_TOP_WW4END0_10" + ], + [ + "CMT_FIFO_L_IMUX43_10", + "CMT_TOP_IMUX43_11" + ], + [ + "CMT_FIFO_EE4BEG1_9", + "CMT_TOP_EE4BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX18_1", + "CMT_TOP_IMUX18_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_5" + ], + [ + "CMT_FIFO_SE4BEG3_11", + "CMT_TOP_SE4BEG3_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_9", + "CMT_TOP_LOGIC_OUTS_L_B20_10" + ], + [ + "CMT_FIFO_NE2A3_11", + "CMT_TOP_NE2A3_12" + ], + [ + "CMT_FIFO_MONITOR_N_6", + "CMT_TOP_MONITOR_N_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_8", + "CMT_TOP_LOGIC_OUTS_L_B4_9" + ], + [ + "CMT_FIFO_ER1BEG1_1", + "CMT_TOP_ER1BEG1_2" + ], + [ + "CMT_FIFO_L_IMUX13_4", + "CMT_TOP_IMUX13_5" + ], + [ + "CMT_FIFO_SW4END3_10", + "CMT_TOP_SW4END3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_5", + "CMT_TOP_LOGIC_OUTS_L_B1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_8", + "CMT_TOP_LOGIC_OUTS_L_B8_9" + ], + [ + "CMT_FIFO_SE4BEG3_6", + "CMT_TOP_SE4BEG3_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "CMT_TOP_OCLK_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_8", + "CMT_TOP_LOGIC_OUTS_L_B21_9" + ], + [ + "CMT_FIFO_EE4B0_9", + "CMT_TOP_EE4B0_10" + ], + [ + "CMT_FIFO_L_IMUX45_10", + "CMT_TOP_IMUX45_11" + ], + [ + "CMT_FIFO_SW4END3_9", + "CMT_TOP_SW4END3_10" + ], + [ + "CMT_FIFO_L_IMUX35_10", + "CMT_TOP_IMUX35_11" + ], + [ + "CMT_FIFO_SW4A0_7", + "CMT_TOP_SW4A0_8" + ], + [ + "CMT_FIFO_SW2A3_1", + "CMT_TOP_SW2A3_2" + ], + [ + "CMT_FIFO_SE2A0_11", + "CMT_TOP_SE2A0_12" + ], + [ + "CMT_FIFO_EE4BEG2_2", + "CMT_TOP_EE4BEG2_3" + ], + [ + "CMT_FIFO_SW4A1_3", + "CMT_TOP_SW4A1_4" + ], + [ + "CMT_FIFO_WW4C1_5", + "CMT_TOP_WW4C1_6" + ], + [ + "CMT_FIFO_WW2END1_6", + "CMT_TOP_WW2END1_7" + ], + [ + "CMT_FIFO_ER1BEG3_7", + "CMT_TOP_ER1BEG3_8" + ], + [ + "CMT_FIFO_WW4A0_10", + "CMT_TOP_WW4A0_11" + ], + [ + "CMT_FIFO_EE4B2_3", + "CMT_TOP_EE4B2_4" + ], + [ + "CMT_FIFO_L_FAN1_5", + "CMT_TOP_FAN1_6" + ], + [ + "CMT_FIFO_MONITOR_P_4", + "CMT_TOP_MONITOR_P_5" + ], + [ + "CMT_FIFO_NW4A0_3", + "CMT_TOP_NW4A0_4" + ], + [ + "CMT_FIFO_EE4A2_11", + "CMT_TOP_EE4A2_12" + ], + [ + "CMT_FIFO_LH1_11", + "CMT_TOP_LH1_12" + ], + [ + "CMT_FIFO_WR1END1_4", + "CMT_TOP_WR1END1_5" + ], + [ + "CMT_FIFO_SW4A0_6", + "CMT_TOP_SW4A0_7" + ], + [ + "CMT_FIFO_WW2END3_6", + "CMT_TOP_WW2END3_7" + ], + [ + "CMT_FIFO_MONITOR_N_0", + "CMT_TOP_MONITOR_N_1" + ], + [ + "CMT_FIFO_LH4_3", + "CMT_TOP_LH4_4" + ], + [ + "CMT_FIFO_EE2BEG2_1", + "CMT_TOP_EE2BEG2_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "CMT_TOP_ICLK_8" + ], + [ + "CMT_FIFO_NW4END2_5", + "CMT_TOP_NW4END2_6" + ], + [ + "CMT_FIFO_LH7_5", + "CMT_TOP_LH7_6" + ], + [ + "CMT_FIFO_WW2A3_0", + "CMT_TOP_WW2A3_1" + ], + [ + "CMT_FIFO_EE4C1_11", + "CMT_TOP_EE4C1_12" + ], + [ + "CMT_FIFO_L_IMUX30_2", + "CMT_TOP_IMUX30_3" + ], + [ + "CMT_FIFO_L_FAN4_5", + "CMT_TOP_FAN4_6" + ], + [ + "CMT_FIFO_WR1END2_4", + "CMT_TOP_WR1END2_5" + ], + [ + "CMT_FIFO_SE2A3_5", + "CMT_TOP_SE2A3_6" + ], + [ + "CMT_FIFO_L_IMUX26_3", + "CMT_TOP_IMUX26_4" + ], + [ + "CMT_FIFO_L_IMUX34_9", + "CMT_TOP_IMUX34_10" + ], + [ + "CMT_FIFO_EE4A1_9", + "CMT_TOP_EE4A1_10" + ], + [ + "CMT_FIFO_ER1BEG3_11", + "CMT_TOP_ER1BEG3_12" + ], + [ + "CMT_FIFO_WW4C1_7", + "CMT_TOP_WW4C1_8" + ], + [ + "CMT_FIFO_NE4C2_3", + "CMT_TOP_NE4C2_4" + ], + [ + "CMT_FIFO_SW4A1_11", + "CMT_TOP_SW4A1_12" + ], + [ + "CMT_FIFO_EE4BEG1_4", + "CMT_TOP_EE4BEG1_5" + ], + [ + "CMT_FIFO_L_IMUX16_11", + "CMT_TOP_IMUX16_12" + ], + [ + "CMT_FIFO_L_IMUX8_8", + "CMT_TOP_IMUX8_9" + ], + [ + "CMT_FIFO_LH7_9", + "CMT_TOP_LH7_10" + ], + [ + "CMT_FIFO_L_IMUX39_7", + "CMT_TOP_IMUX39_8" + ], + [ + "CMT_FIFO_SE2A1_7", + "CMT_TOP_SE2A1_8" + ], + [ + "CMT_FIFO_LH1_5", + "CMT_TOP_LH1_6" + ], + [ + "CMT_FIFO_L_IMUX43_0", + "CMT_TOP_IMUX43_1" + ], + [ + "CMT_FIFO_EE2BEG3_10", + "CMT_TOP_EE2BEG3_11" + ], + [ + "CMT_FIFO_L_IMUX8_2", + "CMT_TOP_IMUX8_3" + ], + [ + "CMT_FIFO_EE4C0_4", + "CMT_TOP_EE4C0_5" + ], + [ + "CMT_FIFO_L_FAN5_7", + "CMT_TOP_FAN5_8" + ], + [ + "CMT_FIFO_L_IMUX11_6", + "CMT_TOP_IMUX11_7" + ], + [ + "CMT_FIFO_NW4A2_1", + "CMT_TOP_NW4A2_2" + ], + [ + "CMT_FIFO_WW4C2_6", + "CMT_TOP_WW4C2_7" + ], + [ + "CMT_FIFO_L_FAN3_5", + "CMT_TOP_FAN3_6" + ], + [ + "CMT_FIFO_EE4BEG2_10", + "CMT_TOP_EE4BEG2_11" + ], + [ + "CMT_FIFO_L_BYP0_10", + "CMT_TOP_BYP0_11" + ], + [ + "CMT_FIFO_NE4C2_0", + "CMT_TOP_NE4C2_1" + ], + [ + "CMT_FIFO_NW4A3_0", + "CMT_TOP_NW4A3_1" + ], + [ + "CMT_FIFO_EL1BEG0_2", + "CMT_TOP_EL1BEG0_3" + ], + [ + "CMT_FIFO_NE4BEG3_8", + "CMT_TOP_NE4BEG3_9" + ], + [ + "CMT_FIFO_WW4A2_6", + "CMT_TOP_WW4A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_6", + "CMT_TOP_LOGIC_OUTS_L_B7_7" + ], + [ + "CMT_FIFO_EE2A0_1", + "CMT_TOP_EE2A0_2" + ], + [ + "CMT_FIFO_WW4C0_1", + "CMT_TOP_WW4C0_2" + ], + [ + "CMT_FIFO_WW4END2_3", + "CMT_TOP_WW4END2_4" + ], + [ + "CMT_FIFO_WW2A2_8", + "CMT_TOP_WW2A2_9" + ], + [ + "CMT_FIFO_LH2_8", + "CMT_TOP_LH2_9" + ], + [ + "CMT_FIFO_SW4A2_2", + "CMT_TOP_SW4A2_3" + ], + [ + "CMT_FIFO_L_IMUX11_10", + "CMT_TOP_IMUX11_11" + ], + [ + "CMT_FIFO_EE4A2_7", + "CMT_TOP_EE4A2_8" + ], + [ + "CMT_FIFO_WW4B3_3", + "CMT_TOP_WW4B3_4" + ], + [ + "CMT_FIFO_L_IMUX4_3", + "CMT_TOP_IMUX4_4" + ], + [ + "CMT_FIFO_WW2A3_11", + "CMT_TOP_WW2A3_12" + ], + [ + "CMT_FIFO_NW2A0_6", + "CMT_TOP_NW2A0_7" + ], + [ + "CMT_FIFO_WW4B3_2", + "CMT_TOP_WW4B3_3" + ], + [ + "CMT_FIFO_L_IMUX28_5", + "CMT_TOP_IMUX28_6" + ], + [ + "CMT_FIFO_L_IMUX42_8", + "CMT_TOP_IMUX42_9" + ], + [ + "CMT_FIFO_SW4END3_0", + "CMT_TOP_SW4END3_1" + ], + [ + "CMT_FIFO_SW2A1_10", + "CMT_TOP_SW2A1_11" + ], + [ + "CMT_FIFO_EE4A0_6", + "CMT_TOP_EE4A0_7" + ], + [ + "CMT_FIFO_SW4END1_4", + "CMT_TOP_SW4END1_5" + ], + [ + "CMT_FIFO_WW2END0_5", + "CMT_TOP_WW2END0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_5", + "CMT_TOP_LOGIC_OUTS_L_B22_6" + ], + [ + "CMT_FIFO_WW2END3_11", + "CMT_TOP_WW2END3_12" + ], + [ + "CMT_FIFO_L_IMUX12_5", + "CMT_TOP_IMUX12_6" + ], + [ + "CMT_FIFO_EE4BEG2_4", + "CMT_TOP_EE4BEG2_5" + ], + [ + "CMT_FIFO_EE2BEG0_10", + "CMT_TOP_EE2BEG0_11" + ], + [ + "CMT_FIFO_EE2BEG1_7", + "CMT_TOP_EE2BEG1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_4", + "CMT_TOP_LOGIC_OUTS_L_B17_5" + ], + [ + "CMT_FIFO_NW4END3_9", + "CMT_TOP_NW4END3_10" + ], + [ + "CMT_FIFO_EE4BEG1_2", + "CMT_TOP_EE4BEG1_3" + ], + [ + "CMT_FIFO_LH7_1", + "CMT_TOP_LH7_2" + ], + [ + "CMT_FIFO_EE4A1_8", + "CMT_TOP_EE4A1_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "CMT_TOP_ICLKDIV_12" + ], + [ + "CMT_FIFO_ER1BEG3_0", + "CMT_TOP_ER1BEG3_1" + ], + [ + "CMT_FIFO_L_IMUX37_2", + "CMT_TOP_IMUX37_3" + ], + [ + "CMT_FIFO_L_IMUX24_4", + "CMT_TOP_IMUX24_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_9", + "CMT_TOP_LOGIC_OUTS_L_B22_10" + ], + [ + "CMT_FIFO_L_IMUX24_3", + "CMT_TOP_IMUX24_4" + ], + [ + "CMT_FIFO_EE2BEG0_11", + "CMT_TOP_EE2BEG0_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_2", + "CMT_TOP_LOGIC_OUTS_L_B21_3" + ], + [ + "CMT_FIFO_WW4C3_7", + "CMT_TOP_WW4C3_8" + ], + [ + "CMT_FIFO_NW4A0_6", + "CMT_TOP_NW4A0_7" + ], + [ + "CMT_FIFO_SW4A1_9", + "CMT_TOP_SW4A1_10" + ], + [ + "CMT_FIFO_NE2A0_1", + "CMT_TOP_NE2A0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_1", + "CMT_TOP_LOGIC_OUTS_L_B18_2" + ], + [ + "CMT_FIFO_NE2A1_5", + "CMT_TOP_NE2A1_6" + ], + [ + "CMT_FIFO_L_IMUX3_8", + "CMT_TOP_IMUX3_9" + ], + [ + "CMT_FIFO_SW4END2_5", + "CMT_TOP_SW4END2_6" + ], + [ + "CMT_FIFO_L_FAN4_7", + "CMT_TOP_FAN4_8" + ], + [ + "CMT_FIFO_EL1BEG3_6", + "CMT_TOP_EL1BEG3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_0", + "CMT_TOP_LOGIC_OUTS_L_B4_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_7", + "CMT_TOP_LOGIC_OUTS_L_B9_8" + ], + [ + "CMT_FIFO_NW4A2_3", + "CMT_TOP_NW4A2_4" + ], + [ + "CMT_FIFO_L_IMUX32_6", + "CMT_TOP_IMUX32_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_7", + "CMT_TOP_LOGIC_OUTS_L_B4_8" + ], + [ + "CMT_FIFO_NE4BEG1_5", + "CMT_TOP_NE4BEG1_6" + ], + [ + "CMT_FIFO_SE4C0_1", + "CMT_TOP_SE4C0_2" + ], + [ + "CMT_FIFO_L_IMUX28_3", + "CMT_TOP_IMUX28_4" + ], + [ + "CMT_FIFO_EE4C3_3", + "CMT_TOP_EE4C3_4" + ], + [ + "CMT_FIFO_SE4C2_11", + "CMT_TOP_SE4C2_12" + ], + [ + "CMT_FIFO_NE4BEG2_11", + "CMT_TOP_NE4BEG2_12" + ], + [ + "CMT_FIFO_NE2A2_4", + "CMT_TOP_NE2A2_5" + ], + [ + "CMT_FIFO_NW4END3_0", + "CMT_TOP_NW4END3_1" + ], + [ + "CMT_FIFO_EE2A3_5", + "CMT_TOP_EE2A3_6" + ], + [ + "CMT_FIFO_SW4END3_1", + "CMT_TOP_SW4END3_2" + ], + [ + "CMT_FIFO_L_IMUX4_0", + "CMT_TOP_IMUX4_1" + ], + [ + "CMT_FIFO_SW4END3_4", + "CMT_TOP_SW4END3_5" + ], + [ + "CMT_FIFO_L_IMUX15_5", + "CMT_TOP_IMUX15_6" + ], + [ + "CMT_FIFO_L_IMUX22_10", + "CMT_TOP_IMUX22_11" + ], + [ + "CMT_FIFO_SW2A1_6", + "CMT_TOP_SW2A1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_1", + "CMT_TOP_LOGIC_OUTS_L_B1_2" + ], + [ + "CMT_FIFO_WL1END1_11", + "CMT_TOP_WL1END1_12" + ], + [ + "CMT_FIFO_SW2A2_7", + "CMT_TOP_SW2A2_8" + ], + [ + "CMT_FIFO_NE2A0_10", + "CMT_TOP_NE2A0_11" + ], + [ + "CMT_FIFO_EE2A3_7", + "CMT_TOP_EE2A3_8" + ], + [ + "CMT_FIFO_L_BYP5_3", + "CMT_TOP_BYP5_4" + ], + [ + "CMT_FIFO_L_IMUX25_7", + "CMT_TOP_IMUX25_8" + ], + [ + "CMT_FIFO_L_IMUX35_5", + "CMT_TOP_IMUX35_6" + ], + [ + "CMT_FIFO_L_BYP4_8", + "CMT_TOP_BYP4_9" + ], + [ + "CMT_FIFO_EE4B1_0", + "CMT_TOP_EE4B1_1" + ], + [ + "CMT_FIFO_WW2A3_9", + "CMT_TOP_WW2A3_10" + ], + [ + "CMT_FIFO_L_IMUX2_2", + "CMT_TOP_IMUX2_3" + ], + [ + "CMT_FIFO_L_BYP7_10", + "CMT_TOP_BYP7_11" + ], + [ + "CMT_FIFO_L_IMUX46_7", + "CMT_TOP_IMUX46_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_7", + "CMT_TOP_LOGIC_OUTS_L_B18_8" + ], + [ + "CMT_FIFO_EL1BEG2_7", + "CMT_TOP_EL1BEG2_8" + ], + [ + "CMT_FIFO_EE2A2_0", + "CMT_TOP_EE2A2_1" + ], + [ + "CMT_FIFO_L_IMUX29_3", + "CMT_TOP_IMUX29_4" + ], + [ + "CMT_FIFO_EE2BEG0_5", + "CMT_TOP_EE2BEG0_6" + ], + [ + "CMT_FIFO_L_IMUX22_2", + "CMT_TOP_IMUX22_3" + ], + [ + "CMT_FIFO_L_IMUX15_0", + "CMT_TOP_IMUX15_1" + ], + [ + "CMT_FIFO_WW4B1_4", + "CMT_TOP_WW4B1_5" + ], + [ + "CMT_FIFO_WR1END1_9", + "CMT_TOP_WR1END1_10" + ], + [ + "CMT_FIFO_WW4C0_2", + "CMT_TOP_WW4C0_3" + ], + [ + "CMT_FIFO_NW4A1_10", + "CMT_TOP_NW4A1_11" + ], + [ + "CMT_FIFO_NW4A3_7", + "CMT_TOP_NW4A3_8" + ], + [ + "CMT_FIFO_WR1END0_5", + "CMT_TOP_WR1END0_6" + ], + [ + "CMT_FIFO_EE4A0_0", + "CMT_TOP_EE4A0_1" + ], + [ + "CMT_FIFO_WW4C2_7", + "CMT_TOP_WW4C2_8" + ], + [ + "CMT_FIFO_EE4BEG2_6", + "CMT_TOP_EE4BEG2_7" + ], + [ + "CMT_FIFO_L_IMUX29_5", + "CMT_TOP_IMUX29_6" + ], + [ + "CMT_FIFO_L_IMUX3_3", + "CMT_TOP_IMUX3_4" + ], + [ + "CMT_FIFO_L_IMUX13_2", + "CMT_TOP_IMUX13_3" + ], + [ + "CMT_FIFO_L_IMUX43_8", + "CMT_TOP_IMUX43_9" + ], + [ + "CMT_FIFO_NW4END2_10", + "CMT_TOP_NW4END2_11" + ], + [ + "CMT_FIFO_L_IMUX36_10", + "CMT_TOP_IMUX36_11" + ], + [ + "CMT_FIFO_SW4END0_2", + "CMT_TOP_SW4END0_3" + ], + [ + "CMT_FIFO_L_IMUX27_4", + "CMT_TOP_IMUX27_5" + ], + [ + "CMT_FIFO_WW4B2_10", + "CMT_TOP_WW4B2_11" + ], + [ + "CMT_FIFO_EE2A3_0", + "CMT_TOP_EE2A3_1" + ], + [ + "CMT_FIFO_L_FAN7_9", + "CMT_TOP_FAN7_10" + ], + [ + "CMT_FIFO_ER1BEG1_7", + "CMT_TOP_ER1BEG1_8" + ], + [ + "CMT_FIFO_NW4A3_4", + "CMT_TOP_NW4A3_5" + ], + [ + "CMT_FIFO_L_IMUX12_4", + "CMT_TOP_IMUX12_5" + ], + [ + "CMT_FIFO_ER1BEG1_11", + "CMT_TOP_ER1BEG1_12" + ], + [ + "CMT_FIFO_EE4A2_9", + "CMT_TOP_EE4A2_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_7", + "CMT_TOP_LOGIC_OUTS_L_B12_8" + ], + [ + "CMT_FIFO_EE2BEG2_5", + "CMT_TOP_EE2BEG2_6" + ], + [ + "CMT_FIFO_L_IMUX39_4", + "CMT_TOP_IMUX39_5" + ], + [ + "CMT_FIFO_MONITOR_P_0", + "CMT_TOP_MONITOR_P_1" + ], + [ + "CMT_FIFO_SE2A3_11", + "CMT_TOP_SE2A3_12" + ], + [ + "CMT_FIFO_EE2A3_10", + "CMT_TOP_EE2A3_11" + ], + [ + "CMT_FIFO_L_IMUX32_2", + "CMT_TOP_IMUX32_3" + ], + [ + "CMT_FIFO_L_IMUX9_8", + "CMT_TOP_IMUX9_9" + ], + [ + "CMT_FIFO_SE4C1_10", + "CMT_TOP_SE4C1_11" + ], + [ + "CMT_FIFO_L_CTRL1_5", + "CMT_TOP_CTRL1_6" + ], + [ + "CMT_FIFO_SE4BEG0_3", + "CMT_TOP_SE4BEG0_4" + ], + [ + "CMT_FIFO_WW4END1_8", + "CMT_TOP_WW4END1_9" + ], + [ + "CMT_FIFO_EE4A0_9", + "CMT_TOP_EE4A0_10" + ], + [ + "CMT_FIFO_NW2A2_8", + "CMT_TOP_NW2A2_9" + ], + [ + "CMT_FIFO_L_IMUX19_5", + "CMT_TOP_IMUX19_6" + ], + [ + "CMT_FIFO_EE4A0_11", + "CMT_TOP_EE4A0_12" + ], + [ + "CMT_FIFO_SE2A2_0", + "CMT_TOP_SE2A2_1" + ], + [ + "CMT_FIFO_L_IMUX17_2", + "CMT_TOP_IMUX17_3" + ], + [ + "CMT_FIFO_L_IMUX33_11", + "CMT_TOP_IMUX33_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_1", + "CMT_TOP_LOGIC_OUTS_L_B8_2" + ], + [ + "CMT_FIFO_SW4END3_7", + "CMT_TOP_SW4END3_8" + ], + [ + "CMT_FIFO_WW4END2_7", + "CMT_TOP_WW4END2_8" + ], + [ + "CMT_FIFO_LH2_7", + "CMT_TOP_LH2_8" + ], + [ + "CMT_FIFO_WW4C0_7", + "CMT_TOP_WW4C0_8" + ], + [ + "CMT_FIFO_EL1BEG2_0", + "CMT_TOP_EL1BEG2_1" + ], + [ + "CMT_FIFO_EE2BEG1_0", + "CMT_TOP_EE2BEG1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_1", + "CMT_TOP_LOGIC_OUTS_L_B9_2" + ], + [ + "CMT_FIFO_EE4A1_2", + "CMT_TOP_EE4A1_3" + ], + [ + "CMT_FIFO_NE4BEG0_1", + "CMT_TOP_NE4BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX46_0", + "CMT_TOP_IMUX46_1" + ], + [ + "CMT_FIFO_EE2A1_9", + "CMT_TOP_EE2A1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_2", + "CMT_TOP_LOGIC_OUTS_L_B13_3" + ], + [ + "CMT_FIFO_L_IMUX36_0", + "CMT_TOP_IMUX36_1" + ], + [ + "CMT_FIFO_SW4END0_0", + "CMT_TOP_SW4END0_1" + ], + [ + "CMT_FIFO_NE4C1_3", + "CMT_TOP_NE4C1_4" + ], + [ + "CMT_FIFO_WL1END3_3", + "CMT_TOP_WL1END3_4" + ], + [ + "CMT_FIFO_WW4B1_5", + "CMT_TOP_WW4B1_6" + ], + [ + "CMT_FIFO_L_IMUX38_10", + "CMT_TOP_IMUX38_11" + ], + [ + "CMT_FIFO_L_IMUX27_10", + "CMT_TOP_IMUX27_11" + ], + [ + "CMT_FIFO_L_IMUX40_11", + "CMT_TOP_IMUX40_12" + ], + [ + "CMT_FIFO_L_IMUX36_3", + "CMT_TOP_IMUX36_4" + ], + [ + "CMT_FIFO_SE4C2_7", + "CMT_TOP_SE4C2_8" + ], + [ + "CMT_FIFO_EE4A2_3", + "CMT_TOP_EE4A2_4" + ], + [ + "CMT_FIFO_L_IMUX14_8", + "CMT_TOP_IMUX14_9" + ], + [ + "CMT_FIFO_EE4A3_10", + "CMT_TOP_EE4A3_11" + ], + [ + "CMT_FIFO_WL1END1_0", + "CMT_TOP_WL1END1_1" + ], + [ + "CMT_FIFO_EE4B3_6", + "CMT_TOP_EE4B3_7" + ], + [ + "CMT_FIFO_WW2END2_6", + "CMT_TOP_WW2END2_7" + ], + [ + "CMT_FIFO_EE4B2_0", + "CMT_TOP_EE4B2_1" + ], + [ + "CMT_FIFO_NE4C2_4", + "CMT_TOP_NE4C2_5" + ], + [ + "CMT_FIFO_LH1_9", + "CMT_TOP_LH1_10" + ], + [ + "CMT_FIFO_L_IMUX19_9", + "CMT_TOP_IMUX19_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_5", + "CMT_TOP_LOGIC_OUTS_L_B9_6" + ], + [ + "CMT_FIFO_WW4END1_11", + "CMT_TOP_WW4END1_12" + ], + [ + "CMT_FIFO_L_CLK1_9", + "CMT_TOP_CLK1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_9", + "CMT_TOP_LOGIC_OUTS_L_B13_10" + ], + [ + "CMT_FIFO_EE2A1_2", + "CMT_TOP_EE2A1_3" + ], + [ + "CMT_FIFO_L_IMUX25_10", + "CMT_TOP_IMUX25_11" + ], + [ + "CMT_FIFO_WW2A3_5", + "CMT_TOP_WW2A3_6" + ], + [ + "CMT_FIFO_WW4C0_11", + "CMT_TOP_WW4C0_12" + ], + [ + "CMT_FIFO_L_IMUX40_7", + "CMT_TOP_IMUX40_8" + ], + [ + "CMT_FIFO_L_BYP3_6", + "CMT_TOP_BYP3_7" + ], + [ + "CMT_FIFO_WW4B1_0", + "CMT_TOP_WW4B1_1" + ], + [ + "CMT_FIFO_ER1BEG0_3", + "CMT_TOP_ER1BEG0_4" + ], + [ + "CMT_FIFO_WW4C2_3", + "CMT_TOP_WW4C2_4" + ], + [ + "CMT_FIFO_SW2A0_7", + "CMT_TOP_SW2A0_8" + ], + [ + "CMT_FIFO_L_IMUX12_3", + "CMT_TOP_IMUX12_4" + ], + [ + "CMT_FIFO_EE4B2_4", + "CMT_TOP_EE4B2_5" + ], + [ + "CMT_FIFO_L_IMUX10_4", + "CMT_TOP_IMUX10_5" + ], + [ + "CMT_FIFO_NW4A3_2", + "CMT_TOP_NW4A3_3" + ], + [ + "CMT_FIFO_EE4C2_8", + "CMT_TOP_EE4C2_9" + ], + [ + "CMT_FIFO_NW2A1_1", + "CMT_TOP_NW2A1_2" + ], + [ + "CMT_FIFO_EL1BEG0_9", + "CMT_TOP_EL1BEG0_10" + ], + [ + "CMT_FIFO_WW4END2_8", + "CMT_TOP_WW4END2_9" + ], + [ + "CMT_FIFO_L_FAN3_10", + "CMT_TOP_FAN3_11" + ], + [ + "CMT_FIFO_ER1BEG0_9", + "CMT_TOP_ER1BEG0_10" + ], + [ + "CMT_FIFO_EE2BEG2_9", + "CMT_TOP_EE2BEG2_10" + ], + [ + "CMT_FIFO_NW4END1_7", + "CMT_TOP_NW4END1_8" + ], + [ + "CMT_FIFO_L_IMUX43_4", + "CMT_TOP_IMUX43_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_9", + "CMT_TOP_LOGIC_OUTS_L_B23_10" + ], + [ + "CMT_FIFO_EE4BEG3_3", + "CMT_TOP_EE4BEG3_4" + ], + [ + "CMT_FIFO_NW4END2_3", + "CMT_TOP_NW4END2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_4", + "CMT_TOP_LOGIC_OUTS_L_B18_5" + ], + [ + "CMT_FIFO_SE2A1_4", + "CMT_TOP_SE2A1_5" + ], + [ + "CMT_FIFO_EE4B3_10", + "CMT_TOP_EE4B3_11" + ], + [ + "CMT_FIFO_WL1END3_6", + "CMT_TOP_WL1END3_7" + ], + [ + "CMT_FIFO_NW4A1_3", + "CMT_TOP_NW4A1_4" + ], + [ + "CMT_FIFO_L_IMUX46_6", + "CMT_TOP_IMUX46_7" + ], + [ + "CMT_FIFO_EE4B2_6", + "CMT_TOP_EE4B2_7" + ], + [ + "CMT_FIFO_EE4BEG0_8", + "CMT_TOP_EE4BEG0_9" + ], + [ + "CMT_FIFO_NE2A2_11", + "CMT_TOP_NE2A2_12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "CMT_TOP_ICLKDIV_1" + ], + [ + "CMT_FIFO_EL1BEG3_3", + "CMT_TOP_EL1BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_6", + "CMT_TOP_LOGIC_OUTS_L_B14_7" + ], + [ + "CMT_FIFO_SE2A3_1", + "CMT_TOP_SE2A3_2" + ], + [ + "CMT_FIFO_SW4A0_1", + "CMT_TOP_SW4A0_2" + ], + [ + "CMT_FIFO_L_FAN4_1", + "CMT_TOP_FAN4_2" + ], + [ + "CMT_FIFO_SW2A3_11", + "CMT_TOP_SW2A3_12" + ], + [ + "CMT_FIFO_SE4BEG3_0", + "CMT_TOP_SE4BEG3_1" + ], + [ + "CMT_FIFO_NW2A2_11", + "CMT_TOP_NW2A2_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_11", + "CMT_TOP_LOGIC_OUTS_L_B0_12" + ], + [ + "CMT_FIFO_SW2A3_3", + "CMT_TOP_SW2A3_4" + ], + [ + "CMT_FIFO_WW4C0_10", + "CMT_TOP_WW4C0_11" + ], + [ + "CMT_FIFO_EE4C2_10", + "CMT_TOP_EE4C2_11" + ], + [ + "CMT_FIFO_LH10_2", + "CMT_TOP_LH10_3" + ], + [ + "CMT_FIFO_WR1END2_11", + "CMT_TOP_WR1END2_12" + ], + [ + "CMT_FIFO_L_IMUX0_6", + "CMT_TOP_IMUX0_7" + ], + [ + "CMT_FIFO_L_FAN3_4", + "CMT_TOP_FAN3_5" + ], + [ + "CMT_FIFO_NE4BEG1_0", + "CMT_TOP_NE4BEG1_1" + ], + [ + "CMT_FIFO_L_IMUX43_11", + "CMT_TOP_IMUX43_12" + ], + [ + "CMT_FIFO_EE4C3_8", + "CMT_TOP_EE4C3_9" + ], + [ + "CMT_FIFO_LH7_6", + "CMT_TOP_LH7_7" + ], + [ + "CMT_FIFO_EE2A1_10", + "CMT_TOP_EE2A1_11" + ], + [ + "CMT_FIFO_L_IMUX14_10", + "CMT_TOP_IMUX14_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_5", + "CMT_TOP_LOGIC_OUTS_L_B2_6" + ], + [ + "CMT_FIFO_SE2A0_4", + "CMT_TOP_SE2A0_5" + ], + [ + "CMT_FIFO_L_IMUX19_7", + "CMT_TOP_IMUX19_8" + ], + [ + "CMT_FIFO_NE2A0_9", + "CMT_TOP_NE2A0_10" + ], + [ + "CMT_FIFO_WW4END0_4", + "CMT_TOP_WW4END0_5" + ], + [ + "CMT_FIFO_EE4BEG0_11", + "CMT_TOP_EE4BEG0_12" + ], + [ + "CMT_FIFO_SW2A3_10", + "CMT_TOP_SW2A3_11" + ], + [ + "CMT_FIFO_L_IMUX18_10", + "CMT_TOP_IMUX18_11" + ], + [ + "CMT_FIFO_L_IMUX13_1", + "CMT_TOP_IMUX13_2" + ], + [ + "CMT_FIFO_NE4C1_0", + "CMT_TOP_NE4C1_1" + ], + [ + "CMT_FIFO_L_IMUX1_1", + "CMT_TOP_IMUX1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_7", + "CMT_TOP_LOGIC_OUTS_L_B21_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_3", + "CMT_TOP_LOGIC_OUTS_L_B7_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_6", + "CMT_TOP_LOGIC_OUTS_L_B22_7" + ], + [ + "CMT_FIFO_EE2A3_3", + "CMT_TOP_EE2A3_4" + ], + [ + "CMT_FIFO_L_IMUX16_10", + "CMT_TOP_IMUX16_11" + ], + [ + "CMT_FIFO_SE2A3_2", + "CMT_TOP_SE2A3_3" + ], + [ + "CMT_FIFO_L_IMUX31_3", + "CMT_TOP_IMUX31_4" + ], + [ + "CMT_FIFO_WL1END0_3", + "CMT_TOP_WL1END0_4" + ], + [ + "CMT_FIFO_L_IMUX11_2", + "CMT_TOP_IMUX11_3" + ], + [ + "CMT_FIFO_EE4BEG1_0", + "CMT_TOP_EE4BEG1_1" + ], + [ + "CMT_FIFO_NE4C0_7", + "CMT_TOP_NE4C0_8" + ], + [ + "CMT_FIFO_NW2A0_8", + "CMT_TOP_NW2A0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_5", + "CMT_TOP_LOGIC_OUTS_L_B21_6" + ], + [ + "CMT_FIFO_NE4BEG3_3", + "CMT_TOP_NE4BEG3_4" + ], + [ + "CMT_FIFO_EE2BEG3_11", + "CMT_TOP_EE2BEG3_12" + ], + [ + "CMT_FIFO_L_BYP7_9", + "CMT_TOP_BYP7_10" + ], + [ + "CMT_FIFO_SE4BEG3_1", + "CMT_TOP_SE4BEG3_2" + ], + [ + "CMT_FIFO_NE2A3_7", + "CMT_TOP_NE2A3_8" + ], + [ + "CMT_FIFO_LH4_11", + "CMT_TOP_LH4_12" + ], + [ + "CMT_FIFO_EE4BEG1_1", + "CMT_TOP_EE4BEG1_2" + ], + [ + "CMT_FIFO_WR1END1_10", + "CMT_TOP_WR1END1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_11", + "CMT_TOP_LOGIC_OUTS_L_B8_12" + ], + [ + "CMT_FIFO_WW2END0_1", + "CMT_TOP_WW2END0_2" + ], + [ + "CMT_FIFO_EL1BEG2_10", + "CMT_TOP_EL1BEG2_11" + ], + [ + "CMT_FIFO_L_IMUX24_10", + "CMT_TOP_IMUX24_11" + ], + [ + "CMT_FIFO_EE4C0_10", + "CMT_TOP_EE4C0_11" + ], + [ + "CMT_FIFO_NE2A2_7", + "CMT_TOP_NE2A2_8" + ], + [ + "CMT_FIFO_WW2A1_6", + "CMT_TOP_WW2A1_7" + ], + [ + "CMT_FIFO_NW4A2_5", + "CMT_TOP_NW4A2_6" + ], + [ + "CMT_FIFO_SW2A2_5", + "CMT_TOP_SW2A2_6" + ], + [ + "CMT_FIFO_L_IMUX11_3", + "CMT_TOP_IMUX11_4" + ], + [ + "CMT_FIFO_L_IMUX36_11", + "CMT_TOP_IMUX36_12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "CMT_TOP_OCLK_12" + ], + [ + "CMT_FIFO_LH8_6", + "CMT_TOP_LH8_7" + ], + [ + "CMT_FIFO_WW4END0_0", + "CMT_TOP_WW4END0_1" + ], + [ + "CMT_FIFO_L_FAN1_8", + "CMT_TOP_FAN1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_11", + "CMT_TOP_LOGIC_OUTS_L_B9_12" + ], + [ + "CMT_FIFO_NE2A1_4", + "CMT_TOP_NE2A1_5" + ], + [ + "CMT_FIFO_EE2A2_1", + "CMT_TOP_EE2A2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_10", + "CMT_TOP_LOGIC_OUTS_L_B12_11" + ], + [ + "CMT_FIFO_L_BYP4_7", + "CMT_TOP_BYP4_8" + ], + [ + "CMT_FIFO_L_IMUX8_0", + "CMT_TOP_IMUX8_1" + ], + [ + "CMT_FIFO_L_BYP0_6", + "CMT_TOP_BYP0_7" + ], + [ + "CMT_FIFO_L_IMUX15_8", + "CMT_TOP_IMUX15_9" + ], + [ + "CMT_FIFO_L_IMUX2_7", + "CMT_TOP_IMUX2_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "CMT_TOP_OCLK_10" + ], + [ + "CMT_FIFO_EE2A0_8", + "CMT_TOP_EE2A0_9" + ], + [ + "CMT_FIFO_SW4A1_10", + "CMT_TOP_SW4A1_11" + ], + [ + "CMT_FIFO_LH3_2", + "CMT_TOP_LH3_3" + ], + [ + "CMT_FIFO_NW2A3_6", + "CMT_TOP_NW2A3_7" + ], + [ + "CMT_FIFO_WR1END0_8", + "CMT_TOP_WR1END0_9" + ], + [ + "CMT_FIFO_LH10_10", + "CMT_TOP_LH10_11" + ], + [ + "CMT_FIFO_NE4C3_5", + "CMT_TOP_NE4C3_6" + ], + [ + "CMT_FIFO_L_BYP5_11", + "CMT_TOP_BYP5_12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_6", + "CMT_TOP_LOGIC_OUTS_L_B1_7" + ], + [ + "CMT_FIFO_NE4BEG2_2", + "CMT_TOP_NE4BEG2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_6", + "CMT_TOP_LOGIC_OUTS_L_B12_7" + ], + [ + "CMT_FIFO_L_IMUX21_10", + "CMT_TOP_IMUX21_11" + ], + [ + "CMT_FIFO_WL1END1_10", + "CMT_TOP_WL1END1_11" + ], + [ + "CMT_FIFO_L_IMUX2_9", + "CMT_TOP_IMUX2_10" + ], + [ + "CMT_FIFO_L_FAN4_2", + "CMT_TOP_FAN4_3" + ], + [ + "CMT_FIFO_L_IMUX43_5", + "CMT_TOP_IMUX43_6" + ], + [ + "CMT_FIFO_WW4END1_1", + "CMT_TOP_WW4END1_2" + ], + [ + "CMT_FIFO_L_FAN0_4", + "CMT_TOP_FAN0_5" + ], + [ + "CMT_FIFO_L_IMUX13_6", + "CMT_TOP_IMUX13_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "CMT_TOP_ICLK_11" + ], + [ + "CMT_FIFO_SE4BEG1_8", + "CMT_TOP_SE4BEG1_9" + ], + [ + "CMT_FIFO_EE2BEG0_6", + "CMT_TOP_EE2BEG0_7" + ], + [ + "CMT_FIFO_SE4BEG3_3", + "CMT_TOP_SE4BEG3_4" + ], + [ + "CMT_FIFO_WL1END0_2", + "CMT_TOP_WL1END0_3" + ], + [ + "CMT_FIFO_L_IMUX9_2", + "CMT_TOP_IMUX9_3" + ], + [ + "CMT_FIFO_SW2A2_3", + "CMT_TOP_SW2A2_4" + ], + [ + "CMT_FIFO_EE4C2_11", + "CMT_TOP_EE4C2_12" + ], + [ + "CMT_FIFO_ER1BEG1_6", + "CMT_TOP_ER1BEG1_7" + ], + [ + "CMT_FIFO_SW4END3_5", + "CMT_TOP_SW4END3_6" + ], + [ + "CMT_FIFO_L_IMUX9_3", + "CMT_TOP_IMUX9_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_9", + "CMT_TOP_LOGIC_OUTS_L_B2_10" + ], + [ + "CMT_FIFO_WW4END0_2", + "CMT_TOP_WW4END0_3" + ], + [ + "CMT_FIFO_L_PHASER_WRCLK", + "CMT_MMCM_A_WRCLK_TOFIFO" + ], + [ + "CMT_FIFO_WW4C2_10", + "CMT_TOP_WW4C2_11" + ], + [ + "CMT_FIFO_L_IMUX5_7", + "CMT_TOP_IMUX5_8" + ], + [ + "CMT_FIFO_L_FAN5_8", + "CMT_TOP_FAN5_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_8", + "CMT_TOP_LOGIC_OUTS_L_B12_9" + ], + [ + "CMT_FIFO_L_FAN1_3", + "CMT_TOP_FAN1_4" + ], + [ + "CMT_FIFO_L_IMUX30_6", + "CMT_TOP_IMUX30_7" + ], + [ + "CMT_FIFO_EE4A3_8", + "CMT_TOP_EE4A3_9" + ], + [ + "CMT_FIFO_L_IMUX41_5", + "CMT_TOP_IMUX41_6" + ], + [ + "CMT_FIFO_SE4BEG2_6", + "CMT_TOP_SE4BEG2_7" + ], + [ + "CMT_FIFO_L_FAN5_6", + "CMT_TOP_FAN5_7" + ], + [ + "CMT_FIFO_NW4END0_5", + "CMT_TOP_NW4END0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_2", + "CMT_TOP_LOGIC_OUTS_L_B19_3" + ], + [ + "CMT_FIFO_WW2END2_3", + "CMT_TOP_WW2END2_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "CMT_TOP_OCLK_7" + ], + [ + "CMT_FIFO_L_IMUX34_2", + "CMT_TOP_IMUX34_3" + ], + [ + "CMT_FIFO_EE4C0_1", + "CMT_TOP_EE4C0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_6", + "CMT_TOP_LOGIC_OUTS_L_B5_7" + ], + [ + "CMT_FIFO_LH5_2", + "CMT_TOP_LH5_3" + ], + [ + "CMT_FIFO_SW2A1_11", + "CMT_TOP_SW2A1_12" + ], + [ + "CMT_FIFO_L_IMUX16_1", + "CMT_TOP_IMUX16_2" + ], + [ + "CMT_FIFO_NW4A1_8", + "CMT_TOP_NW4A1_9" + ], + [ + "CMT_FIFO_SE2A0_3", + "CMT_TOP_SE2A0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_8", + "CMT_TOP_LOGIC_OUTS_L_B22_9" + ], + [ + "CMT_FIFO_L_IMUX39_1", + "CMT_TOP_IMUX39_2" + ], + [ + "CMT_FIFO_L_IMUX12_8", + "CMT_TOP_IMUX12_9" + ], + [ + "CMT_FIFO_EE2A3_4", + "CMT_TOP_EE2A3_5" + ], + [ + "CMT_FIFO_EE4A3_11", + "CMT_TOP_EE4A3_12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "CMT_TOP_OCLK_5" + ], + [ + "CMT_FIFO_WW2A2_1", + "CMT_TOP_WW2A2_2" + ], + [ + "CMT_FIFO_L_IMUX32_7", + "CMT_TOP_IMUX32_8" + ], + [ + "CMT_FIFO_LH4_6", + "CMT_TOP_LH4_7" + ], + [ + "CMT_FIFO_L_IMUX1_2", + "CMT_TOP_IMUX1_3" + ], + [ + "CMT_FIFO_SW2A0_11", + "CMT_TOP_SW2A0_12" + ], + [ + "CMT_FIFO_L_IMUX24_1", + "CMT_TOP_IMUX24_2" + ], + [ + "CMT_FIFO_L_IMUX21_9", + "CMT_TOP_IMUX21_10" + ], + [ + "CMT_FIFO_EL1BEG0_3", + "CMT_TOP_EL1BEG0_4" + ], + [ + "CMT_FIFO_WR1END0_11", + "CMT_TOP_WR1END0_12" + ], + [ + "CMT_FIFO_LH8_4", + "CMT_TOP_LH8_5" + ], + [ + "CMT_FIFO_L_CTRL0_0", + "CMT_TOP_CTRL0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "CMT_TOP_OCLK1X_90_8" + ], + [ + "CMT_FIFO_EE2BEG1_4", + "CMT_TOP_EE2BEG1_5" + ], + [ + "CMT_FIFO_L_IMUX21_3", + "CMT_TOP_IMUX21_4" + ], + [ + "CMT_FIFO_L_IMUX34_10", + "CMT_TOP_IMUX34_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_3" + ], + [ + "CMT_FIFO_L_IMUX19_1", + "CMT_TOP_IMUX19_2" + ], + [ + "CMT_FIFO_WW4A1_2", + "CMT_TOP_WW4A1_3" + ], + [ + "CMT_FIFO_SE4BEG1_5", + "CMT_TOP_SE4BEG1_6" + ], + [ + "CMT_FIFO_L_IMUX39_9", + "CMT_TOP_IMUX39_10" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "CMT_TOP_R_LOWER_B" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLBLM_WW2END2", + "DSP_WW2END2_0" + ], + [ + "CLBLM_EE2A2", + "DSP_EE2A2_0" + ], + [ + "CLBLM_NW2A0", + "DSP_NW2A0_0" + ], + [ + "CLBLM_SW4END1", + "DSP_SW4END1_0" + ], + [ + "CLBLM_WW4C3", + "DSP_WW4C3_0" + ], + [ + "CLBLM_WW2END3", + "DSP_WW2END3_0" + ], + [ + "CLBLM_WW4C2", + "DSP_WW4C2_0" + ], + [ + "CLBLM_EE4A1", + "DSP_EE4A1_0" + ], + [ + "CLBLM_LH12", + "DSP_LH12_0" + ], + [ + "CLBLM_WW2A3", + "DSP_WW2A3_0" + ], + [ + "CLBLM_WW4C0", + "DSP_WW4C0_0" + ], + [ + "CLBLM_EL1BEG1", + "DSP_EL1BEG1_0" + ], + [ + "CLBLM_WW4A1", + "DSP_WW4A1_0" + ], + [ + "CLBLM_EE2BEG1", + "DSP_EE2BEG1_0" + ], + [ + "CLBLM_SW2A0", + "DSP_SW2A0_0" + ], + [ + "CLBLM_EE4C2", + "DSP_EE4C2_0" + ], + [ + "CLBLM_SW4A2", + "DSP_SW4A2_0" + ], + [ + "CLBLM_WW4END3", + "DSP_WW4END3_0" + ], + [ + "CLBLM_WW4END0", + "DSP_WW4END0_0" + ], + [ + "CLBLM_NW4END1", + "DSP_NW4END1_0" + ], + [ + "CLBLM_LH6", + "DSP_LH6_0" + ], + [ + "CLBLM_SE4BEG2", + "DSP_SE4BEG2_0" + ], + [ + "CLBLM_NE4BEG0", + "DSP_NE4BEG0_0" + ], + [ + "CLBLM_NE4C2", + "DSP_NE4C2_0" + ], + [ + "CLBLM_LH8", + "DSP_LH8_0" + ], + [ + "CLBLM_SE4C1", + "DSP_SE4C1_0" + ], + [ + "CLBLM_SW4A3", + "DSP_SW4A3_0" + ], + [ + "CLBLM_NW4A3", + "DSP_NW4A3_0" + ], + [ + "CLBLM_NW4A2", + "DSP_NW4A2_0" + ], + [ + "CLBLM_LH11", + "DSP_LH11_0" + ], + [ + "CLBLM_SW4END0", + "DSP_SW4END0_0" + ], + [ + "CLBLM_WR1END2", + "DSP_WR1END2_0" + ], + [ + "CLBLM_WL1END1", + "DSP_WL1END1_0" + ], + [ + "CLBLM_NE4BEG3", + "DSP_NE4BEG3_0" + ], + [ + "CLBLM_EE2A1", + "DSP_EE2A1_0" + ], + [ + "CLBLM_EE4A3", + "DSP_EE4A3_0" + ], + [ + "CLBLM_WL1END0", + "DSP_WL1END0_0" + ], + [ + "CLBLM_SE4C2", + "DSP_SE4C2_0" + ], + [ + "CLBLM_NE4C1", + "DSP_NE4C1_0" + ], + [ + "CLBLM_NE4C0", + "DSP_NE4C0_0" + ], + [ + "CLBLM_EE4BEG2", + "DSP_EE4BEG2_0" + ], + [ + "CLBLM_ER1BEG1", + "DSP_ER1BEG1_0" + ], + [ + "CLBLM_EE4B3", + "DSP_EE4B3_0" + ], + [ + "CLBLM_WW4C1", + "DSP_WW4C1_0" + ], + [ + "CLBLM_WL1END3", + "DSP_WL1END3_0" + ], + [ + "CLBLM_EE4C0", + "DSP_EE4C0_0" + ], + [ + "CLBLM_LH9", + "DSP_LH9_0" + ], + [ + "CLBLM_SE4C0", + "DSP_SE4C0_0" + ], + [ + "CLBLM_WW2END0", + "DSP_WW2END0_0" + ], + [ + "CLBLM_SE4C3", + "DSP_SE4C3_0" + ], + [ + "CLBLM_WW4END2", + "DSP_WW4END2_0" + ], + [ + "CLBLM_WR1END0", + "DSP_WR1END0_0" + ], + [ + "CLBLM_EE4C1", + "DSP_EE4C1_0" + ], + [ + "CLBLM_WW4END1", + "DSP_WW4END1_0" + ], + [ + "CLBLM_ER1BEG0", + "DSP_ER1BEG0_0" + ], + [ + "CLBLM_LH4", + "DSP_LH4_0" + ], + [ + "CLBLM_MONITOR_N", + "DSP_MONITOR_N_0" + ], + [ + "CLBLM_SE4BEG0", + "DSP_SE4BEG0_0" + ], + [ + "CLBLM_ER1BEG3", + "DSP_ER1BEG3_0" + ], + [ + "CLBLM_MONITOR_P", + "DSP_MONITOR_P_0" + ], + [ + "CLBLM_EL1BEG3", + "DSP_EL1BEG3_0" + ], + [ + "CLBLM_NE4BEG1", + "DSP_NE4BEG1_0" + ], + [ + "CLBLM_LH3", + "DSP_LH3_0" + ], + [ + "CLBLM_WW2A2", + "DSP_WW2A2_0" + ], + [ + "CLBLM_SE2A2", + "DSP_SE2A2_0" + ], + [ + "CLBLM_SW4END2", + "DSP_SW4END2_0" + ], + [ + "CLBLM_WW4A2", + "DSP_WW4A2_0" + ], + [ + "CLBLM_NW4END2", + "DSP_NW4END2_0" + ], + [ + "CLBLM_NE2A3", + "DSP_NE2A3_0" + ], + [ + "CLBLM_ER1BEG2", + "DSP_ER1BEG2_0" + ], + [ + "CLBLM_EE4B0", + "DSP_EE4B0_0" + ], + [ + "CLBLM_WW2A0", + "DSP_WW2A0_0" + ], + [ + "CLBLM_EE2BEG2", + "DSP_EE2BEG2_0" + ], + [ + "CLBLM_EE2A0", + "DSP_EE2A0_0" + ], + [ + "CLBLM_SE4BEG1", + "DSP_SE4BEG1_0" + ], + [ + "CLBLM_NW2A2", + "DSP_NW2A2_0" + ], + [ + "CLBLM_SE4BEG3", + "DSP_SE4BEG3_0" + ], + [ + "CLBLM_EE2BEG3", + "DSP_EE2BEG3_0" + ], + [ + "CLBLM_NE4BEG2", + "DSP_NE4BEG2_0" + ], + [ + "CLBLM_SE2A3", + "DSP_SE2A3_0" + ], + [ + "CLBLM_SE2A1", + "DSP_SE2A1_0" + ], + [ + "CLBLM_WW4B1", + "DSP_WW4B1_0" + ], + [ + "CLBLM_SW2A2", + "DSP_SW2A2_0" + ], + [ + "CLBLM_WR1END3", + "DSP_WR1END3_0" + ], + [ + "CLBLM_EL1BEG2", + "DSP_EL1BEG2_0" + ], + [ + "CLBLM_LH7", + "DSP_LH7_0" + ], + [ + "CLBLM_NE4C3", + "DSP_NE4C3_0" + ], + [ + "CLBLM_SW4A0", + "DSP_SW4A0_0" + ], + [ + "CLBLM_WW4B2", + "DSP_WW4B2_0" + ], + [ + "CLBLM_WR1END1", + "DSP_WR1END1_0" + ], + [ + "CLBLM_NW4A0", + "DSP_NW4A0_0" + ], + [ + "CLBLM_EE2BEG0", + "DSP_EE2BEG0_0" + ], + [ + "CLBLM_SW4A1", + "DSP_SW4A1_0" + ], + [ + "CLBLM_WL1END2", + "DSP_WL1END2_0" + ], + [ + "CLBLM_SW2A3", + "DSP_SW2A3_0" + ], + [ + "CLBLM_NW4END0", + "DSP_NW4END0_0" + ], + [ + "CLBLM_WW4A3", + "DSP_WW4A3_0" + ], + [ + "CLBLM_LH1", + "DSP_LH1_0" + ], + [ + "CLBLM_EE4B2", + "DSP_EE4B2_0" + ], + [ + "CLBLM_EE4A2", + "DSP_EE4A2_0" + ], + [ + "CLBLM_LH2", + "DSP_LH2_0" + ], + [ + "CLBLM_NE2A0", + "DSP_NE2A0_0" + ], + [ + "CLBLM_NE2A1", + "DSP_NE2A1_0" + ], + [ + "CLBLM_WW2A1", + "DSP_WW2A1_0" + ], + [ + "CLBLM_LH5", + "DSP_LH5_0" + ], + [ + "CLBLM_EE4BEG3", + "DSP_EE4BEG3_0" + ], + [ + "CLBLM_EE4A0", + "DSP_EE4A0_0" + ], + [ + "CLBLM_NW2A3", + "DSP_NW2A3_0" + ], + [ + "CLBLM_EE4B1", + "DSP_EE4B1_0" + ], + [ + "CLBLM_WW4B0", + "DSP_WW4B0_0" + ], + [ + "CLBLM_NE2A2", + "DSP_NE2A2_0" + ], + [ + "CLBLM_EE4BEG1", + "DSP_EE4BEG1_0" + ], + [ + "CLBLM_SW4END3", + "DSP_SW4END3_0" + ], + [ + "CLBLM_WW4B3", + "DSP_WW4B3_0" + ], + [ + "CLBLM_WW2END1", + "DSP_WW2END1_0" + ], + [ + "CLBLM_SW2A1", + "DSP_SW2A1_0" + ], + [ + "CLBLM_EL1BEG0", + "DSP_EL1BEG0_0" + ], + [ + "CLBLM_EE4BEG0", + "DSP_EE4BEG0_0" + ], + [ + "CLBLM_NW4A1", + "DSP_NW4A1_0" + ], + [ + "CLBLM_NW4END3", + "DSP_NW4END3_0" + ], + [ + "CLBLM_SE2A0", + "DSP_SE2A0_0" + ], + [ + "CLBLM_EE4C3", + "DSP_EE4C3_0" + ], + [ + "CLBLM_NW2A1", + "DSP_NW2A1_0" + ], + [ + "CLBLM_EE2A3", + "DSP_EE2A3_0" + ], + [ + "CLBLM_LH10", + "DSP_LH10_0" + ], + [ + "CLBLM_WW4A0", + "DSP_WW4A0_0" + ] + ], + "tile_types": [ + "CLBLM_L", + "DSP_R" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "BRAM_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "BRAM_LH2_1", + "VBRK_LH2" + ], + [ + "BRAM_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "BRAM_LH5_1", + "VBRK_LH5" + ], + [ + "BRAM_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "BRAM_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "BRAM_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "BRAM_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "BRAM_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "BRAM_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "BRAM_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "BRAM_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "BRAM_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "BRAM_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "BRAM_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "BRAM_MONITOR_N_1", + "VBRK_MONITOR_N" + ], + [ + "BRAM_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "BRAM_LH3_1", + "VBRK_LH3" + ], + [ + "BRAM_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "BRAM_LH9_1", + "VBRK_LH9" + ], + [ + "BRAM_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "BRAM_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "BRAM_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "BRAM_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "BRAM_MONITOR_P_1", + "VBRK_MONITOR_P" + ], + [ + "BRAM_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "BRAM_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "BRAM_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "BRAM_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "BRAM_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "BRAM_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "BRAM_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "BRAM_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "BRAM_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "BRAM_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "BRAM_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "BRAM_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "BRAM_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "BRAM_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "BRAM_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "BRAM_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "BRAM_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "BRAM_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "BRAM_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "BRAM_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "BRAM_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "BRAM_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "BRAM_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "BRAM_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "BRAM_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "BRAM_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "BRAM_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "BRAM_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "BRAM_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "BRAM_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "BRAM_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "BRAM_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "BRAM_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "BRAM_LH10_1", + "VBRK_LH10" + ], + [ + "BRAM_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "BRAM_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "BRAM_LH7_1", + "VBRK_LH7" + ], + [ + "BRAM_LH11_1", + "VBRK_LH11" + ], + [ + "BRAM_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "BRAM_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "BRAM_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "BRAM_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "BRAM_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "BRAM_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "BRAM_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "BRAM_LH12_1", + "VBRK_LH12" + ], + [ + "BRAM_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "BRAM_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "BRAM_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "BRAM_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "BRAM_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "BRAM_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "BRAM_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "BRAM_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "BRAM_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "BRAM_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "BRAM_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "BRAM_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "BRAM_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "BRAM_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "BRAM_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "BRAM_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "BRAM_LH4_1", + "VBRK_LH4" + ], + [ + "BRAM_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "BRAM_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "BRAM_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "BRAM_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "BRAM_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "BRAM_LH8_1", + "VBRK_LH8" + ], + [ + "BRAM_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "BRAM_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "BRAM_LH1_1", + "VBRK_LH1" + ], + [ + "BRAM_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "BRAM_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "BRAM_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "BRAM_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "BRAM_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "BRAM_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "BRAM_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "BRAM_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "BRAM_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "BRAM_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "BRAM_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "BRAM_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "BRAM_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "BRAM_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "BRAM_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "BRAM_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "BRAM_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "BRAM_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "BRAM_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "BRAM_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "BRAM_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "BRAM_LH6_1", + "VBRK_LH6" + ], + [ + "BRAM_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "BRAM_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "BRAM_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "BRAM_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "BRAM_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "BRAM_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "BRAM_SW4A1_1", + "VBRK_SW4A1" + ] + ], + "tile_types": [ + "BRAM_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B23_9", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_LOGIC_OUTS_B4_9", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B7_9", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B8_9", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX0_9", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX42_9", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX38_9", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_LOGIC_OUTS_B3_9", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX13_9", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX10_9", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B15_9", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_FAN2_9", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_BYP4_9", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX27_9", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_FAN1_9", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_BYP2_9", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX40_9", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX44_9", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_CLK1_9", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_LOGIC_OUTS_B2_9", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX14_9", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX11_9", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX3_9", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX47_9", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_LOGIC_OUTS_B11_9", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_FAN3_9", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX33_9", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_FAN5_9", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_BYP1_9", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B20_9", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX8_9", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX20_9", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX34_9", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX18_9", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX1_9", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_LOGIC_OUTS_B18_9", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX5_9", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B19_9", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_BYP3_9", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B14_9", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX30_9", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX15_9", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_BYP6_9", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX43_9", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX23_9", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX7_9", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX26_9", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX9_9", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX46_9", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_LOGIC_OUTS_B0_9", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX29_9", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX4_9", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX6_9", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX22_9", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B9_9", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_LOGIC_OUTS_B10_9", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX21_9", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_FAN6_9", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_BYP0_9", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX39_9", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX16_9", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX35_9", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_FAN0_9", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_LOGIC_OUTS_B16_9", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B6_9", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_LOGIC_OUTS_B21_9", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_LOGIC_OUTS_B13_9", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_CTRL0_9", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX28_9", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_LOGIC_OUTS_B17_9", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_CLK0_9", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_FAN4_9", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_FAN7_9", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX45_9", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX36_9", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX2_9", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_BYP5_9", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX41_9", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B5_9", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_LOGIC_OUTS_B12_9", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX31_9", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B1_9", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_CTRL1_9", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX17_9", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX24_9", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX12_9", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX32_9", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B22_9", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_BYP7_9", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX25_9", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX19_9", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX37_9", + "VBRK_EXT_IMUX37" + ] + ], + "tile_types": [ + "GTX_CHANNEL_0", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + 9 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW2END1_1", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE4BEG0_1", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_LH9_1", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NW4A1_1", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WW2END3_1", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_SW4A3_1", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_WW4B3_1", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SE2A3_1", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_LH5_1", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_LH2_1", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_ER1BEG3_1", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_LH6_1", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_WL1END0_1", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_WW4A0_1", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE2BEG2_1", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_NE4BEG0_1", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_NW4END1_1", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_EE4B0_1", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_SW4A1_1", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_NW4END0_1", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_LH7_1", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_LH11_1", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_LH10_1", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WW4A3_1", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NE4BEG3_1", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW2END2_1", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_WR1END3_1", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_SW4A0_1", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_SW2A1_1", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_EE4B3_1", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SE2A0_1", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE2A3_1", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_SE4C3_1", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_NW2A1_1", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_NW2A0_1", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_WW4C0_1", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NW4A0_1", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_WW2END0_1", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_NW4END3_1", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WL1END1_1", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_NW2A2_1", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_EL1BEG2_1", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_NE4C2_1", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WR1END2_1", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_SE4C2_1", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_EE2A1_1", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_EE4C2_1", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_WW4B1_1", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_SW4A2_1", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_LH8_1", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_WW4A1_1", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_NE4BEG1_1", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_EE4B1_1", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EE4BEG2_1", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_WW2A1_1", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_LH1_1", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_WW2A2_1", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_EE4B2_1", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_WW4B0_1", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_LH3_1", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_EE2A0_1", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_EE4A3_1", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_WW4A2_1", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EL1BEG1_1", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NW2A3_1", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE2A0_1", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_SW4END1_1", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_NE2A3_1", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_SE4BEG3_1", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EE4BEG1_1", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG0_1", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SE4C0_1", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_NE2A1_1", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_WW4C2_1", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NW4END2_1", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_EE4C1_1", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE2BEG0_1", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4END1_1", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE2BEG1_1", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_SW4END2_1", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_NE2A2_1", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE4C3_1", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW4C1_1", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_EL1BEG3_1", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_SE2A1_1", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_SE2A2_1", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_WL1END2_1", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_LH12_1", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_NE4C0_1", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_WW4END0_1", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_NE4C3_1", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_EE4A1_1", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EL1BEG0_1", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_SW2A2_1", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_EE4A2_1", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_WW4C3_1", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_LH4_1", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_EE2A2_1", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WL1END3_1", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4C0_1", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_SE4BEG2_1", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_EE2BEG3_1", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NE4C1_1", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE4BEG2_1", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_ER1BEG0_1", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NW4A2_1", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_EE4A0_1", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_ER1BEG2_1", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_SW2A3_1", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_ER1BEG1_1", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WW4END3_1", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_WR1END0_1", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_SW4END0_1", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_WW2A3_1", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_EE4BEG3_1", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_SW4END3_1", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_WW2A0_1", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_SW2A0_1", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WW4END2_1", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_NW4A3_1", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_SE4BEG1_1", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_WW4B2_1", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_WR1END1_1", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SE4C1_1", + "INT_FEEDTHRU_2_SE4C1" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + -6 + ], + "wire_pairs": [ + [ + "MONITOR_SE4C2_6", + "VFRAME_SE4C2" + ], + [ + "MONITOR_LH4_6", + "VFRAME_LH4" + ], + [ + "MONITOR_NW4A3_6", + "VFRAME_NW4A3" + ], + [ + "MONITOR_SW4A2_6", + "VFRAME_SW4A2" + ], + [ + "MONITOR_SW2A2_6", + "VFRAME_SW2A2" + ], + [ + "MONITOR_SE4C1_6", + "VFRAME_SE4C1" + ], + [ + "MONITOR_IMUX21_6", + "VFRAME_IMUX21" + ], + [ + "MONITOR_IMUX19_6", + "VFRAME_IMUX19" + ], + [ + "MONITOR_WR1END1_6", + "VFRAME_WR1END1" + ], + [ + "MONITOR_EE4A2_6", + "VFRAME_EE4A2" + ], + [ + "MONITOR_WW4A0_6", + "VFRAME_WW4A0" + ], + [ + "MONITOR_SW4A0_6", + "VFRAME_SW4A0" + ], + [ + "MONITOR_WW2END3_6", + "VFRAME_WW2END3" + ], + [ + "MONITOR_IMUX7_6", + "VFRAME_IMUX7" + ], + [ + "MONITOR_WW4B3_6", + "VFRAME_WW4B3" + ], + [ + "MONITOR_EE4BEG0_6", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_IMUX27_6", + "VFRAME_IMUX27" + ], + [ + "MONITOR_EE2A0_6", + "VFRAME_EE2A0" + ], + [ + "MONITOR_IMUX44_6", + "VFRAME_IMUX44" + ], + [ + "MONITOR_NW4END0_6", + "VFRAME_NW4END0" + ], + [ + "MONITOR_IMUX14_6", + "VFRAME_IMUX14" + ], + [ + "MONITOR_IMUX12_6", + "VFRAME_IMUX12" + ], + [ + "MONITOR_WW4C1_6", + "VFRAME_WW4C1" + ], + [ + "MONITOR_IMUX9_6", + "VFRAME_IMUX9" + ], + [ + "MONITOR_WR1END2_6", + "VFRAME_WR1END2" + ], + [ + "MONITOR_IMUX39_6", + "VFRAME_IMUX39" + ], + [ + "MONITOR_SW2A3_6", + "VFRAME_SW2A3" + ], + [ + "MONITOR_WW2A1_6", + "VFRAME_WW2A1" + ], + [ + "MONITOR_IMUX35_6", + "VFRAME_IMUX35" + ], + [ + "MONITOR_WW4END0_6", + "VFRAME_WW4END0" + ], + [ + "MONITOR_FAN4_6", + "VFRAME_FAN4" + ], + [ + "MONITOR_SW2A0_6", + "VFRAME_SW2A0" + ], + [ + "MONITOR_IMUX30_6", + "VFRAME_IMUX30" + ], + [ + "MONITOR_BYP1_6", + "VFRAME_BYP1" + ], + [ + "MONITOR_IMUX40_6", + "VFRAME_IMUX40" + ], + [ + "MONITOR_IMUX17_6", + "VFRAME_IMUX17" + ], + [ + "MONITOR_EE4B2_6", + "VFRAME_EE4B2" + ], + [ + "MONITOR_SW4A3_6", + "VFRAME_SW4A3" + ], + [ + "MONITOR_ER1BEG0_6", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_IMUX43_6", + "VFRAME_IMUX43" + ], + [ + "MONITOR_IMUX32_6", + "VFRAME_IMUX32" + ], + [ + "MONITOR_IMUX24_6", + "VFRAME_IMUX24" + ], + [ + "MONITOR_SE2A2_6", + "VFRAME_SE2A2" + ], + [ + "MONITOR_SW4END2_6", + "VFRAME_SW4END2" + ], + [ + "MONITOR_FAN3_6", + "VFRAME_FAN3" + ], + [ + "MONITOR_WW2A2_6", + "VFRAME_WW2A2" + ], + [ + "MONITOR_CTRL1_6", + "VFRAME_CTRL1" + ], + [ + "MONITOR_SE2A3_6", + "VFRAME_SE2A3" + ], + [ + "MONITOR_SW4A1_6", + "VFRAME_SW4A1" + ], + [ + "MONITOR_NE4BEG0_6", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_BYP6_6", + "VFRAME_BYP6" + ], + [ + "MONITOR_WL1END2_6", + "VFRAME_WL1END2" + ], + [ + "MONITOR_SE4BEG0_6", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_IMUX46_6", + "VFRAME_IMUX46" + ], + [ + "MONITOR_WW2A0_6", + "VFRAME_WW2A0" + ], + [ + "MONITOR_IMUX1_6", + "VFRAME_IMUX1" + ], + [ + "MONITOR_LH3_6", + "VFRAME_LH3" + ], + [ + "MONITOR_NW4END2_6", + "VFRAME_NW4END2" + ], + [ + "MONITOR_IMUX37_6", + "VFRAME_IMUX37" + ], + [ + "MONITOR_FAN2_6", + "VFRAME_FAN2" + ], + [ + "MONITOR_EE4BEG1_6", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_SW4END0_6", + "VFRAME_SW4END0" + ], + [ + "MONITOR_LH1_6", + "VFRAME_LH1" + ], + [ + "MONITOR_SW2A1_6", + "VFRAME_SW2A1" + ], + [ + "MONITOR_EE4C2_6", + "VFRAME_EE4C2" + ], + [ + "MONITOR_IMUX3_6", + "VFRAME_IMUX3" + ], + [ + "MONITOR_NE4C1_6", + "VFRAME_NE4C1" + ], + [ + "MONITOR_IMUX47_6", + "VFRAME_IMUX47" + ], + [ + "MONITOR_NE4C2_6", + "VFRAME_NE4C2" + ], + [ + "MONITOR_IMUX13_6", + "VFRAME_IMUX13" + ], + [ + "MONITOR_WW4A3_6", + "VFRAME_WW4A3" + ], + [ + "MONITOR_BYP0_6", + "VFRAME_BYP0" + ], + [ + "MONITOR_IMUX6_6", + "VFRAME_IMUX6" + ], + [ + "MONITOR_EE4A3_6", + "VFRAME_EE4A3" + ], + [ + "MONITOR_LH9_6", + "VFRAME_LH9" + ], + [ + "MONITOR_NE4BEG1_6", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_CTRL0_6", + "VFRAME_CTRL0" + ], + [ + "MONITOR_CLK1_6", + "VFRAME_CLK1" + ], + [ + "MONITOR_NE4BEG3_6", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_WW4C2_6", + "VFRAME_WW4C2" + ], + [ + "MONITOR_NW4A2_6", + "VFRAME_NW4A2" + ], + [ + "MONITOR_LH8_6", + "VFRAME_LH8" + ], + [ + "MONITOR_IMUX10_6", + "VFRAME_IMUX10" + ], + [ + "MONITOR_NE4C0_6", + "VFRAME_NE4C0" + ], + [ + "MONITOR_NE2A3_6", + "VFRAME_NE2A3" + ], + [ + "MONITOR_EE2A2_6", + "VFRAME_EE2A2" + ], + [ + "MONITOR_WW2END2_6", + "VFRAME_WW2END2" + ], + [ + "MONITOR_BYP5_6", + "VFRAME_BYP5" + ], + [ + "MONITOR_IMUX29_6", + "VFRAME_IMUX29" + ], + [ + "MONITOR_WW4B1_6", + "VFRAME_WW4B1" + ], + [ + "MONITOR_IMUX34_6", + "VFRAME_IMUX34" + ], + [ + "MONITOR_EE4C1_6", + "VFRAME_EE4C1" + ], + [ + "MONITOR_EE2A3_6", + "VFRAME_EE2A3" + ], + [ + "MONITOR_IMUX2_6", + "VFRAME_IMUX2" + ], + [ + "MONITOR_LH6_6", + "VFRAME_LH6" + ], + [ + "MONITOR_IMUX18_6", + "VFRAME_IMUX18" + ], + [ + "MONITOR_IMUX26_6", + "VFRAME_IMUX26" + ], + [ + "MONITOR_CLK0_6", + "VFRAME_CLK0" + ], + [ + "MONITOR_WR1END0_6", + "VFRAME_WR1END0" + ], + [ + "MONITOR_SW4END1_6", + "VFRAME_SW4END1" + ], + [ + "MONITOR_IMUX33_6", + "VFRAME_IMUX33" + ], + [ + "MONITOR_EE4A0_6", + "VFRAME_EE4A0" + ], + [ + "MONITOR_IMUX5_6", + "VFRAME_IMUX5" + ], + [ + "MONITOR_EE4C0_6", + "VFRAME_EE4C0" + ], + [ + "MONITOR_LH2_6", + "VFRAME_LH2" + ], + [ + "MONITOR_IMUX23_6", + "VFRAME_IMUX23" + ], + [ + "MONITOR_SE2A0_6", + "VFRAME_SE2A0" + ], + [ + "MONITOR_EE4B3_6", + "VFRAME_EE4B3" + ], + [ + "MONITOR_EE4A1_6", + "VFRAME_EE4A1" + ], + [ + "MONITOR_ER1BEG1_6", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_WR1END3_6", + "VFRAME_WR1END3" + ], + [ + "MONITOR_WW4END3_6", + "VFRAME_WW4END3" + ], + [ + "MONITOR_IMUX0_6", + "VFRAME_IMUX0" + ], + [ + "MONITOR_IMUX28_6", + "VFRAME_IMUX28" + ], + [ + "MONITOR_WL1END1_6", + "VFRAME_WL1END1" + ], + [ + "MONITOR_NE2A0_6", + "VFRAME_NE2A0" + ], + [ + "MONITOR_IMUX11_6", + "VFRAME_IMUX11" + ], + [ + "MONITOR_EE4BEG2_6", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_LH5_6", + "VFRAME_LH5" + ], + [ + "MONITOR_FAN5_6", + "VFRAME_FAN5" + ], + [ + "MONITOR_EL1BEG1_6", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_IMUX38_6", + "VFRAME_IMUX38" + ], + [ + "MONITOR_SE2A1_6", + "VFRAME_SE2A1" + ], + [ + "MONITOR_WW2END1_6", + "VFRAME_WW2END1" + ], + [ + "MONITOR_IMUX31_6", + "VFRAME_IMUX31" + ], + [ + "MONITOR_IMUX45_6", + "VFRAME_IMUX45" + ], + [ + "MONITOR_SE4BEG2_6", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_FAN0_6", + "VFRAME_FAN0" + ], + [ + "MONITOR_EE2BEG2_6", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_LH7_6", + "VFRAME_LH7" + ], + [ + "MONITOR_EE4B0_6", + "VFRAME_EE4B0" + ], + [ + "MONITOR_EL1BEG0_6", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_WL1END0_6", + "VFRAME_WL1END0" + ], + [ + "MONITOR_BYP3_6", + "VFRAME_BYP3" + ], + [ + "MONITOR_IMUX16_6", + "VFRAME_IMUX16" + ], + [ + "MONITOR_ER1BEG3_6", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_WW4END2_6", + "VFRAME_WW4END2" + ], + [ + "MONITOR_EE4B1_6", + "VFRAME_EE4B1" + ], + [ + "MONITOR_LH10_6", + "VFRAME_LH10" + ], + [ + "MONITOR_IMUX20_6", + "VFRAME_IMUX20" + ], + [ + "MONITOR_NW4A1_6", + "VFRAME_NW4A1" + ], + [ + "MONITOR_IMUX36_6", + "VFRAME_IMUX36" + ], + [ + "MONITOR_NE4BEG2_6", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_WL1END3_6", + "VFRAME_WL1END3" + ], + [ + "MONITOR_EE4C3_6", + "VFRAME_EE4C3" + ], + [ + "MONITOR_SE4BEG3_6", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_IMUX42_6", + "VFRAME_IMUX42" + ], + [ + "MONITOR_IMUX22_6", + "VFRAME_IMUX22" + ], + [ + "MONITOR_WW2END0_6", + "VFRAME_WW2END0" + ], + [ + "MONITOR_WW2A3_6", + "VFRAME_WW2A3" + ], + [ + "MONITOR_ER1BEG2_6", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_NW2A2_6", + "VFRAME_NW2A2" + ], + [ + "MONITOR_LH11_6", + "VFRAME_LH11" + ], + [ + "MONITOR_WW4A2_6", + "VFRAME_WW4A2" + ], + [ + "MONITOR_BYP7_6", + "VFRAME_BYP7" + ], + [ + "MONITOR_NW2A0_6", + "VFRAME_NW2A0" + ], + [ + "MONITOR_FAN7_6", + "VFRAME_FAN7" + ], + [ + "MONITOR_IMUX8_6", + "VFRAME_IMUX8" + ], + [ + "MONITOR_IMUX15_6", + "VFRAME_IMUX15" + ], + [ + "MONITOR_EL1BEG2_6", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_IMUX25_6", + "VFRAME_IMUX25" + ], + [ + "MONITOR_SW4END3_6", + "VFRAME_SW4END3" + ], + [ + "MONITOR_EL1BEG3_6", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_NW4END1_6", + "VFRAME_NW4END1" + ], + [ + "MONITOR_EE2BEG1_6", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_SE4C0_6", + "VFRAME_SE4C0" + ], + [ + "MONITOR_IMUX4_6", + "VFRAME_IMUX4" + ], + [ + "MONITOR_FAN1_6", + "VFRAME_FAN1" + ], + [ + "MONITOR_NW4A0_6", + "VFRAME_NW4A0" + ], + [ + "MONITOR_WW4B2_6", + "VFRAME_WW4B2" + ], + [ + "MONITOR_NW2A3_6", + "VFRAME_NW2A3" + ], + [ + "MONITOR_NE4C3_6", + "VFRAME_NE4C3" + ], + [ + "MONITOR_WW4C3_6", + "VFRAME_WW4C3" + ], + [ + "MONITOR_EE2BEG0_6", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_NE2A2_6", + "VFRAME_NE2A2" + ], + [ + "MONITOR_SE4BEG1_6", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_NE2A1_6", + "VFRAME_NE2A1" + ], + [ + "MONITOR_LH12_6", + "VFRAME_LH12" + ], + [ + "MONITOR_EE4BEG3_6", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_NW4END3_6", + "VFRAME_NW4END3" + ], + [ + "MONITOR_BYP4_6", + "VFRAME_BYP4" + ], + [ + "MONITOR_WW4END1_6", + "VFRAME_WW4END1" + ], + [ + "MONITOR_EE2A1_6", + "VFRAME_EE2A1" + ], + [ + "MONITOR_NW2A1_6", + "VFRAME_NW2A1" + ], + [ + "MONITOR_FAN6_6", + "VFRAME_FAN6" + ], + [ + "MONITOR_SE4C3_6", + "VFRAME_SE4C3" + ], + [ + "MONITOR_BYP2_6", + "VFRAME_BYP2" + ], + [ + "MONITOR_EE2BEG3_6", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_IMUX41_6", + "VFRAME_IMUX41" + ], + [ + "MONITOR_WW4A1_6", + "VFRAME_WW4A1" + ], + [ + "MONITOR_WW4C0_6", + "VFRAME_WW4C0" + ], + [ + "MONITOR_WW4B0_6", + "VFRAME_WW4B0" + ] + ], + "tile_types": [ + "MONITOR_BOT_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "CLK_PMV_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "CLK_PMV_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "CLK_PMV_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "CLK_PMV_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "CLK_PMV_LH10_4", + "VBRK_LH10" + ], + [ + "CLK_PMV_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "CLK_PMV_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "CLK_PMV_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "CLK_PMV_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "CLK_PMV_LH12_4", + "VBRK_LH12" + ], + [ + "CLK_PMV_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "CLK_PMV_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "CLK_PMV_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "CLK_PMV_EE2A2_4", + "VBRK_EE2A2" + ], + [ + "CLK_PMV_LH3_4", + "VBRK_LH3" + ], + [ + "CLK_PMV_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "CLK_PMV_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "CLK_PMV_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "CLK_PMV_LH6_4", + "VBRK_LH6" + ], + [ + "CLK_PMV_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "CLK_PMV_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "CLK_PMV_LH1_4", + "VBRK_LH1" + ], + [ + "CLK_PMV_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "CLK_PMV_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "CLK_PMV_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "CLK_PMV_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "CLK_PMV_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "CLK_PMV_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "CLK_PMV_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "CLK_PMV_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "CLK_PMV_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "CLK_PMV_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "CLK_PMV_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "CLK_PMV_EE2A1_4", + "VBRK_EE2A1" + ], + [ + "CLK_PMV_EE2A0_4", + "VBRK_EE2A0" + ], + [ + "CLK_PMV_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "CLK_PMV_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "CLK_PMV_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "CLK_PMV_LH9_4", + "VBRK_LH9" + ], + [ + "CLK_PMV_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "CLK_PMV_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "CLK_PMV_LH11_4", + "VBRK_LH11" + ], + [ + "CLK_PMV_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "CLK_PMV_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "CLK_PMV_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "CLK_PMV_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "CLK_PMV_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "CLK_PMV_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "CLK_PMV_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "CLK_PMV_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "CLK_PMV_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "CLK_PMV_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "CLK_PMV_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "CLK_PMV_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "CLK_PMV_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "CLK_PMV_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "CLK_PMV_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "CLK_PMV_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "CLK_PMV_LH4_4", + "VBRK_LH4" + ], + [ + "CLK_PMV_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "CLK_PMV_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "CLK_PMV_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "CLK_PMV_MONITOR_N_4", + "VBRK_MONITOR_N" + ], + [ + "CLK_PMV_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "CLK_PMV_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "CLK_PMV_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "CLK_PMV_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "CLK_PMV_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "CLK_PMV_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "CLK_PMV_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "CLK_PMV_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "CLK_PMV_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "CLK_PMV_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "CLK_PMV_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "CLK_PMV_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "CLK_PMV_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "CLK_PMV_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "CLK_PMV_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "CLK_PMV_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "CLK_PMV_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "CLK_PMV_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "CLK_PMV_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "CLK_PMV_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "CLK_PMV_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "CLK_PMV_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "CLK_PMV_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "CLK_PMV_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "CLK_PMV_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "CLK_PMV_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "CLK_PMV_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "CLK_PMV_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "CLK_PMV_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "CLK_PMV_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "CLK_PMV_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "CLK_PMV_LH7_4", + "VBRK_LH7" + ], + [ + "CLK_PMV_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "CLK_PMV_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "CLK_PMV_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "CLK_PMV_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "CLK_PMV_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "CLK_PMV_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "CLK_PMV_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "CLK_PMV_MONITOR_P_4", + "VBRK_MONITOR_P" + ], + [ + "CLK_PMV_LH2_4", + "VBRK_LH2" + ], + [ + "CLK_PMV_LH8_4", + "VBRK_LH8" + ], + [ + "CLK_PMV_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "CLK_PMV_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "CLK_PMV_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "CLK_PMV_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "CLK_PMV_LH5_4", + "VBRK_LH5" + ], + [ + "CLK_PMV_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "CLK_PMV_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "CLK_PMV_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "CLK_PMV_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "CLK_PMV_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "CLK_PMV_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "CLK_PMV_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "CLK_PMV_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "CLK_PMV_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "CLK_PMV_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "CLK_PMV_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "CLK_PMV_WW4B3_4", + "VBRK_WW4B3" + ], + [ + "CLK_PMV_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "CLK_PMV_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "CLK_PMV_WW4END3_4", + "VBRK_WW4END3" + ], + [ + "CLK_PMV_WW2END1_4", + "VBRK_WW2END1" + ] + ], + "tile_types": [ + "CLK_PMV", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CMT_TOP_EE2BEG2_9", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NE4C0_9", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EE2A0_9", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_9", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SE4BEG2_9", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_NE2A2_9", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW2A2_9", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_LH6_9", + "VBRK_LH6" + ], + [ + "CMT_TOP_EE4B1_9", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW4A1_9", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SW4A2_9", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WR1END2_9", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH8_9", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A3_9", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4BEG3_9", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WW2END2_9", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2A1_9", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4A0_9", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4C1_9", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NE4C3_9", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW2A0_9", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_9", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2END0_9", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4C2_9", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A3_9", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_ER1BEG0_9", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EL1BEG1_9", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG0_9", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH3_9", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END2_9", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH2_9", + "VBRK_LH2" + ], + [ + "CMT_TOP_MONITOR_N_9", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW4A3_9", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW2A2_9", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4A2_9", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END3_9", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE2A3_9", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4BEG2_9", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4END0_9", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SW4A0_9", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4C1_9", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A1_9", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4END2_9", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EL1BEG3_9", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_9", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW2A0_9", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4B0_9", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE4C0_9", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE4B3_9", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW4A1_9", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4C1_9", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_LH4_9", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2BEG1_9", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4A0_9", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4BEG0_9", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_9", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2A2_9", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EE4A1_9", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4END0_9", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW4B1_9", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4A3_9", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END3_9", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH11_9", + "VBRK_LH11" + ], + [ + "CMT_TOP_SW4END3_9", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_9", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END1_9", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_LH12_9", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C1_9", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE4C3_9", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_SE2A1_9", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE4A0_9", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_EE2BEG3_9", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END1_9", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A1_9", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE2BEG0_9", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE2A2_9", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END3_9", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_ER1BEG3_9", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NE2A3_9", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW2A3_9", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_9", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_MONITOR_P_9", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_LH9_9", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4B0_9", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A0_9", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NE4BEG2_9", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A2_9", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_WW4C0_9", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SW2A1_9", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH5_9", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END0_9", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NE4BEG1_9", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_9", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A2_9", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4BEG1_9", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C0_9", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_WW4END2_9", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_WW4END1_9", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NW2A0_9", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4C2_9", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_WW4B3_9", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WR1END0_9", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW2A3_9", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW2A2_9", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_EE4BEG3_9", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C2_9", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_SE4BEG1_9", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_9", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_NE2A0_9", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4B2_9", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WL1END2_9", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG0_9", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG2_9", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4C3_9", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4A1_9", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH1_9", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW4END0_9", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_EE4A3_9", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_LH10_9", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW2END1_9", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WL1END3_9", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_EE2A1_9", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4C3_9", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WR1END3_9", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SW2A3_9", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH7_9", + "VBRK_LH7" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "BRKH_CLB_COUT1_R", + "CLBLM_M_COUT_N" + ], + [ + "BRKH_CLB_COUT0_R", + "CLBLM_L_COUT_N" + ] + ], + "tile_types": [ + "BRKH_CLB", + "CLBLM_R" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW2A2_5", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A0_5", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END2_5", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SE4C1_5", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SW4END3_5", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NW4END0_5", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW2A0_5", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WL1END3_5", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SE2A2_5", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4B3_5", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE2A2_5", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_5", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_LH3_5", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE4C2_5", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2A0_5", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG1_5", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A1_5", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4A2_5", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END1_5", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW4C0_5", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_5", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4END3_5", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4BEG0_5", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_EL1BEG1_5", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH6_5", + "VBRK_LH6" + ], + [ + "CMT_TOP_EE4A1_5", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NW4A2_5", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4A3_5", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NE4BEG0_5", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW2A2_5", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C3_5", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH7_5", + "VBRK_LH7" + ], + [ + "CMT_TOP_WW4B2_5", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH5_5", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4A1_5", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4A0_5", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C1_5", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW2A0_5", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WL1END2_5", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_SE4C0_5", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SW4END2_5", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END1_5", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG0_5", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_WR1END1_5", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EE4C1_5", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG0_5", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NW4END2_5", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_EE2BEG2_5", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4B1_5", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_ER1BEG3_5", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NW2A1_5", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B0_5", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END2_5", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A1_5", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE2A3_5", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_LH11_5", + "VBRK_LH11" + ], + [ + "CMT_TOP_WL1END0_5", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SW4END0_5", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4BEG3_5", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C3_5", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_SE4BEG1_5", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NE2A2_5", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B0_5", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_ER1BEG2_5", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_5", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NE2A0_5", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4BEG1_5", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE2A3_5", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG2_5", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_LH9_5", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4END2_5", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4BEG2_5", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2END0_5", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_ER1BEG0_5", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE2A1_5", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH4_5", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2BEG1_5", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_NE4BEG3_5", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C0_5", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH8_5", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4A3_5", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2BEG0_5", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_NE2A1_5", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C3_5", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WL1END1_5", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW4A1_5", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_5", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4A0_5", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4END1_5", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH2_5", + "VBRK_LH2" + ], + [ + "CMT_TOP_NE2A3_5", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW4A0_5", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4A3_5", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4C0_5", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_LH12_5", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH1_5", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_5", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_ER1BEG1_5", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2BEG3_5", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH10_5", + "VBRK_LH10" + ], + [ + "CMT_TOP_SW2A2_5", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WR1END3_5", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NW4END1_5", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NW4A1_5", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WW4C2_5", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WR1END0_5", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4END3_5", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW4A3_5", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW2A3_5", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4END0_5", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4C2_5", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG3_5", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW2A3_5", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4A2_5", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4BEG3_5", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE4B2_5", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW2A0_5", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SE2A0_5", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SE4BEG2_5", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B1_5", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4C1_5", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C2_5", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4C3_5", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_EL1BEG2_5", + "VBRK_EL1BEG2" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "CMT_FIFO_LH9_8", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_LH7_8", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_NW2A0_8", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_WW2END2_8", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_WW4C0_8", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_NE4C2_8", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_EE4B1_8", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_NW2A3_8", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_L_IMUX29_8", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_SW4A2_8", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_NE4C3_8", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_EE4BEG1_8", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_8", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "CMT_FIFO_WW2A0_8", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_WW4B3_8", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_EE4C2_8", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_8", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_8", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "CMT_FIFO_L_IMUX17_8", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_L_IMUX31_8", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_NE2A3_8", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_L_IMUX44_8", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_SE2A0_8", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_NE2A2_8", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_L_BYP6_8", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_NW4A0_8", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_WW4C1_8", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_L_IMUX25_8", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_L_IMUX26_8", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_IMUX21_8", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_LH10_8", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_L_IMUX22_8", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_WW2A1_8", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_SW4A0_8", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_SW4A1_8", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_MONITOR_N_8", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CMT_FIFO_L_BYP5_8", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_EE2BEG2_8", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_WW4END3_8", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_EL1BEG1_8", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_NE4BEG2_8", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX46_8", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_L_IMUX33_8", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_WW4B0_8", + "INT_INTERFACE_WW4B0" + ], + [ + "FIFO_DQS_IOTOPHASER_3", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "CMT_FIFO_WL1END3_8", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_L_IMUX4_8", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_8", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_8", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "CMT_FIFO_L_IMUX42_8", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_8", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "CMT_FIFO_WW4C2_8", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_IMUX43_8", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_L_FAN2_8", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_WW4C3_8", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_8", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "CMT_FIFO_SE4C2_8", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_EE4A0_8", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_L_CTRL1_8", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_L_IMUX18_8", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_WW4A3_8", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_L_IMUX30_8", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_L_IMUX12_8", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_L_BYP3_8", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_LH5_8", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_EE2A3_8", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_WW4END0_8", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_ER1BEG0_8", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_L_FAN4_8", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_SW4END1_8", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_L_CLK1_8", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_EL1BEG2_8", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_LH3_8", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_L_IMUX16_8", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_SW4END3_8", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_WR1END2_8", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_L_IMUX0_8", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_NE2A0_8", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_8", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "CMT_FIFO_WL1END0_8", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_SW2A3_8", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_L_IMUX8_8", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_NE4C0_8", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_L_IMUX39_8", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_L_IMUX5_8", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_LH12_8", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_EE4B3_8", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_8", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "CMT_FIFO_WW4B1_8", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_NW2A2_8", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_EE2A2_8", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_WR1END0_8", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_WW2END1_8", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_LH4_8", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_MONITOR_P_8", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CMT_FIFO_WW4A2_8", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_L_FAN5_8", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_L_CLK0_8", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_NW4END0_8", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_NW4END1_8", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_SE4BEG3_8", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_ER1BEG3_8", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_8", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "CMT_FIFO_L_CTRL0_8", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_NW4END2_8", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_WW4B2_8", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_8", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "CMT_FIFO_L_IMUX10_8", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_8", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "CMT_FIFO_SE4BEG2_8", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_WW2END3_8", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_EE4A1_8", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_SE4C1_8", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_EE4BEG2_8", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_L_FAN7_8", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_EE4B2_8", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_NW4A1_8", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_L_FAN6_8", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_8", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_8", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_8", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_8", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "CMT_FIFO_NW4A3_8", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_NE2A1_8", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_NW2A1_8", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_8", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_8", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "CMT_FIFO_WW4END1_8", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_L_BYP1_8", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_WW4END2_8", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_WW2A3_8", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_WR1END3_8", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_EE2A0_8", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_BYP0_8", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_EE4C0_8", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_EE4A3_8", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_IMUX3_8", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_L_IMUX27_8", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_L_BYP7_8", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_ER1BEG1_8", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_NE4C1_8", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_SE4BEG1_8", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX34_8", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_WL1END2_8", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_WL1END1_8", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_L_IMUX6_8", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_EE4BEG0_8", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX40_8", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_SW4END2_8", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_L_IMUX47_8", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_L_IMUX1_8", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_IMUX20_8", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_L_IMUX28_8", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_8", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "CMT_FIFO_EE4C1_8", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_NW4A2_8", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_LH1_8", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_WW2END0_8", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_NW4END3_8", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_L_IMUX45_8", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_SE4C0_8", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_8", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "CMT_FIFO_WR1END1_8", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_EE2BEG0_8", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_EE4BEG3_8", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX23_8", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_L_BYP4_8", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_SW2A1_8", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_SE2A3_8", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_L_FAN0_8", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_LH11_8", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_WW4A1_8", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_L_IMUX38_8", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_NE4BEG3_8", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX15_8", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_8", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "CMT_FIFO_SE4BEG0_8", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_LH6_8", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_EE2BEG3_8", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_WW4A0_8", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_L_IMUX11_8", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_8", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "CMT_FIFO_EE4B0_8", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_L_IMUX36_8", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_L_FAN3_8", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_L_FAN1_8", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_SW4A3_8", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_NE4BEG1_8", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_SE2A1_8", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_L_IMUX35_8", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_8", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "CMT_FIFO_L_IMUX41_8", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_SE2A2_8", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_EE2BEG1_8", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_L_IMUX7_8", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_WW2A2_8", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_EE4C3_8", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_L_IMUX32_8", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_NE4BEG0_8", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_EL1BEG0_8", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_8", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "CMT_FIFO_LH2_8", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_LH8_8", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_EE4A2_8", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_IMUX19_8", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_EL1BEG3_8", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_L_IMUX9_8", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX14_8", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_L_IMUX37_8", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_L_BYP2_8", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_SW2A2_8", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_L_IMUX2_8", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_EE2A1_8", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_ER1BEG2_8", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_IMUX13_8", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_SW4END0_8", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_SW2A0_8", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_L_IMUX24_8", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_SE4C3_8", + "INT_INTERFACE_SE4C3" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 0, + 5 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN19" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN29" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_HROW_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_HROW_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_HROW_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN8" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_HROW_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_HROW_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN4" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_HROW_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_HROW_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN1" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_HROW_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_HROW_R_CK_GCLK4" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_HROW_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_HROW_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_HROW_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN14" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_HROW_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_HROW_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN30" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_HROW_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN24" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_HROW_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_HROW_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_HROW_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_HROW_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN31" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_HROW_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_HROW_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN5" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_HROW_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN16" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_HROW_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN21" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_HROW_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_HROW_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN28" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_HROW_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN10" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_HROW_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN6" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN23" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN22" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_HROW_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_HROW_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN9" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN27" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_HROW_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_HROW_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN7" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_HROW_R_CK_GCLK16" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_HROW_TOP_R" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B11_6", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_LOGIC_OUTS_B2_6", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX5_6", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_CLK1_6", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX6_6", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX3_6", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_LOGIC_OUTS_B20_6", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX22_6", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B0_6", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX21_6", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_CLK0_6", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_LOGIC_OUTS_B14_6", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX24_6", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX39_6", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B9_6", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_LOGIC_OUTS_B5_6", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX46_6", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP3_6", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_FAN1_6", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B3_6", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX30_6", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_FAN4_6", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_LOGIC_OUTS_B10_6", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX42_6", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_LOGIC_OUTS_B6_6", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX28_6", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX8_6", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX45_6", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX10_6", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B16_6", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX36_6", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX44_6", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX33_6", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_BYP7_6", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX15_6", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX41_6", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX25_6", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_CTRL1_6", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_6", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX12_6", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B22_6", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX19_6", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_BYP6_6", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX40_6", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX32_6", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN0_6", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX27_6", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX37_6", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX0_6", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX35_6", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_BYP2_6", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_BYP0_6", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX31_6", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX13_6", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_FAN2_6", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX2_6", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_LOGIC_OUTS_B12_6", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_BYP5_6", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_CTRL0_6", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_LOGIC_OUTS_B17_6", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX9_6", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX29_6", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX16_6", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_LOGIC_OUTS_B1_6", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_FAN5_6", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX18_6", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX43_6", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX4_6", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_LOGIC_OUTS_B8_6", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_LOGIC_OUTS_B15_6", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_LOGIC_OUTS_B13_6", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_IMUX38_6", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX7_6", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_BYP1_6", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B23_6", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX23_6", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_FAN7_6", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B7_6", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B4_6", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_IMUX26_6", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX20_6", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN3_6", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX34_6", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX47_6", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_BYP4_6", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX11_6", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_FAN6_6", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX14_6", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX1_6", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX17_6", + "VBRK_EXT_IMUX17" + ] + ], + "tile_types": [ + "GTX_CHANNEL_2", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "CLK_HROW_WW2END2_6", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_NE4C3_6", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_LH10_6", + "VBRK_LH10" + ], + [ + "CLK_HROW_NE4C0_6", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_WR1END2_6", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_SE4BEG1_6", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_SW4A2_6", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_SW4A0_6", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_WW4C3_6", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_SE4C0_6", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_EE2A2_6", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_EE4B3_6", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_NW2A3_6", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_SE4BEG0_6", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_SE2A2_6", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE4C1_6", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_SE4C2_6", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_NE4C1_6", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_WW4C0_6", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_EE2A1_6", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_EE4A3_6", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_MONITOR_P_6", + "VBRK_MONITOR_P" + ], + [ + "CLK_HROW_SW2A3_6", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_EL1BEG1_6", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_WW4B3_6", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_NE2A2_6", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_SW2A0_6", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_LH1_6", + "VBRK_LH1" + ], + [ + "CLK_HROW_LH11_6", + "VBRK_LH11" + ], + [ + "CLK_HROW_EE4A1_6", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_WW2A3_6", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_SW2A1_6", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_EE4B2_6", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_WW4A0_6", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_NE2A0_6", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_WL1END2_6", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_EL1BEG2_6", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WW4C2_6", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_WW2END0_6", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_EE4A0_6", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_EE4BEG0_6", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_ER1BEG2_6", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_NW4A0_6", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_NE4BEG1_6", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_SW4END2_6", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_SW4END3_6", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_NE2A1_6", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_WR1END0_6", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_EE2BEG3_6", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_EE2A0_6", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_SW4A3_6", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_SE4C1_6", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_LH6_6", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE2BEG2_6", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_EE4B0_6", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_LH4_6", + "VBRK_LH4" + ], + [ + "CLK_HROW_EE4BEG2_6", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_SE2A0_6", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_WR1END1_6", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_EE4A2_6", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_WW4END1_6", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_NE2A3_6", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_NE4BEG0_6", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_NW4END0_6", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_NE4BEG2_6", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_WW4C1_6", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_WL1END3_6", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_SE2A3_6", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_ER1BEG1_6", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_EE4C2_6", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_LH5_6", + "VBRK_LH5" + ], + [ + "CLK_HROW_WW4A3_6", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_SW4A1_6", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_WW4END3_6", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_LH12_6", + "VBRK_LH12" + ], + [ + "CLK_HROW_WW2A1_6", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_WW4B0_6", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EE2BEG1_6", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_SE4BEG2_6", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_EL1BEG0_6", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_ER1BEG0_6", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4B2_6", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_EE4BEG3_6", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NW4END1_6", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_SE2A1_6", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_LH8_6", + "VBRK_LH8" + ], + [ + "CLK_HROW_MONITOR_N_6", + "VBRK_MONITOR_N" + ], + [ + "CLK_HROW_NW2A1_6", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_NW4END2_6", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_WW2A2_6", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_WW2END1_6", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_SW2A2_6", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_LH3_6", + "VBRK_LH3" + ], + [ + "CLK_HROW_NW4A2_6", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_WR1END3_6", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_SE4BEG3_6", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_SW4END1_6", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_LH7_6", + "VBRK_LH7" + ], + [ + "CLK_HROW_NE4C2_6", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_WW4END0_6", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_NW2A2_6", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_NW2A0_6", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_EE2A3_6", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_EE2BEG0_6", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_SW4END0_6", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_NE4BEG3_6", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_WW4A1_6", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_NW4A1_6", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_EE4BEG1_6", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WL1END1_6", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_LH9_6", + "VBRK_LH9" + ], + [ + "CLK_HROW_WL1END0_6", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_EE4B1_6", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_NW4END3_6", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_WW2END3_6", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_WW4A2_6", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_ER1BEG3_6", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_EL1BEG3_6", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_EE4C3_6", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_EE4C0_6", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_WW4END2_6", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_SE4C3_6", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_WW4B1_6", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_LH2_6", + "VBRK_LH2" + ], + [ + "CLK_HROW_NW4A3_6", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_WW2A0_6", + "VBRK_WW2A0" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "DSP_0_PCIN21", + "HCLK_DSP_PCIN21" + ], + [ + "DSP_0_BCIN15", + "HCLK_DSP_BCIN15" + ], + [ + "DSP_0_BCIN14", + "HCLK_DSP_BCIN14" + ], + [ + "DSP_0_ACIN23", + "HCLK_DSP_ACIN23" + ], + [ + "DSP_0_BCIN12", + "HCLK_DSP_BCIN12" + ], + [ + "DSP_0_ACIN5", + "HCLK_DSP_ACIN5" + ], + [ + "DSP_0_PCIN28", + "HCLK_DSP_PCIN28" + ], + [ + "DSP_0_BCIN2", + "HCLK_DSP_BCIN2" + ], + [ + "DSP_0_ACIN1", + "HCLK_DSP_ACIN1" + ], + [ + "DSP_0_PCIN47", + "HCLK_DSP_PCIN47" + ], + [ + "DSP_0_PCIN39", + "HCLK_DSP_PCIN39" + ], + [ + "DSP_0_ACIN14", + "HCLK_DSP_ACIN14" + ], + [ + "DSP_0_ACIN12", + "HCLK_DSP_ACIN12" + ], + [ + "DSP_0_ACIN10", + "HCLK_DSP_ACIN10" + ], + [ + "DSP_0_BCIN8", + "HCLK_DSP_BCIN8" + ], + [ + "DSP_0_PCIN6", + "HCLK_DSP_PCIN6" + ], + [ + "DSP_0_BCIN11", + "HCLK_DSP_BCIN11" + ], + [ + "DSP_0_PCIN46", + "HCLK_DSP_PCIN46" + ], + [ + "DSP_0_ACIN13", + "HCLK_DSP_ACIN13" + ], + [ + "DSP_0_PCIN24", + "HCLK_DSP_PCIN24" + ], + [ + "DSP_0_ACIN21", + "HCLK_DSP_ACIN21" + ], + [ + "DSP_0_PCIN9", + "HCLK_DSP_PCIN9" + ], + [ + "DSP_0_PCIN22", + "HCLK_DSP_PCIN22" + ], + [ + "DSP_0_PCIN16", + "HCLK_DSP_PCIN16" + ], + [ + "DSP_0_ACIN3", + "HCLK_DSP_ACIN3" + ], + [ + "DSP_0_ACIN2", + "HCLK_DSP_ACIN2" + ], + [ + "DSP_0_ACIN22", + "HCLK_DSP_ACIN22" + ], + [ + "DSP_0_PCIN40", + "HCLK_DSP_PCIN40" + ], + [ + "DSP_0_PCIN45", + "HCLK_DSP_PCIN45" + ], + [ + "DSP_0_PCIN19", + "HCLK_DSP_PCIN19" + ], + [ + "DSP_0_PCIN38", + "HCLK_DSP_PCIN38" + ], + [ + "DSP_0_ACIN24", + "HCLK_DSP_ACIN24" + ], + [ + "DSP_0_ACIN20", + "HCLK_DSP_ACIN20" + ], + [ + "DSP_0_ACIN7", + "HCLK_DSP_ACIN7" + ], + [ + "DSP_0_BCIN13", + "HCLK_DSP_BCIN13" + ], + [ + "DSP_0_PCIN11", + "HCLK_DSP_PCIN11" + ], + [ + "DSP_0_PCIN0", + "HCLK_DSP_PCIN0" + ], + [ + "DSP_0_ACIN11", + "HCLK_DSP_ACIN11" + ], + [ + "DSP_0_PCIN3", + "HCLK_DSP_PCIN3" + ], + [ + "DSP_0_ACIN9", + "HCLK_DSP_ACIN9" + ], + [ + "DSP_0_ACIN17", + "HCLK_DSP_ACIN17" + ], + [ + "DSP_0_PCIN17", + "HCLK_DSP_PCIN17" + ], + [ + "DSP_0_BCIN16", + "HCLK_DSP_BCIN16" + ], + [ + "DSP_0_BCIN0", + "HCLK_DSP_BCIN0" + ], + [ + "DSP_0_ACIN6", + "HCLK_DSP_ACIN6" + ], + [ + "DSP_0_PCIN33", + "HCLK_DSP_PCIN33" + ], + [ + "DSP_0_ACIN15", + "HCLK_DSP_ACIN15" + ], + [ + "DSP_0_BCIN10", + "HCLK_DSP_BCIN10" + ], + [ + "DSP_0_PCIN2", + "HCLK_DSP_PCIN2" + ], + [ + "DSP_0_PCIN4", + "HCLK_DSP_PCIN4" + ], + [ + "DSP_0_ACIN27", + "HCLK_DSP_ACIN27" + ], + [ + "DSP_0_ACIN16", + "HCLK_DSP_ACIN16" + ], + [ + "DSP_0_PCIN20", + "HCLK_DSP_PCIN20" + ], + [ + "DSP_0_ACIN19", + "HCLK_DSP_ACIN19" + ], + [ + "DSP_0_MULTSIGNIN", + "HCLK_DSP_MULTSIGNIN" + ], + [ + "DSP_0_PCIN25", + "HCLK_DSP_PCIN25" + ], + [ + "DSP_0_BCIN9", + "HCLK_DSP_BCIN9" + ], + [ + "DSP_0_PCIN41", + "HCLK_DSP_PCIN41" + ], + [ + "DSP_0_PCIN12", + "HCLK_DSP_PCIN12" + ], + [ + "DSP_0_BCIN1", + "HCLK_DSP_BCIN1" + ], + [ + "DSP_0_PCIN34", + "HCLK_DSP_PCIN34" + ], + [ + "DSP_0_BCIN17", + "HCLK_DSP_BCIN17" + ], + [ + "DSP_0_ACIN26", + "HCLK_DSP_ACIN26" + ], + [ + "DSP_0_PCIN35", + "HCLK_DSP_PCIN35" + ], + [ + "DSP_0_ACIN28", + "HCLK_DSP_ACIN28" + ], + [ + "DSP_0_PCIN18", + "HCLK_DSP_PCIN18" + ], + [ + "DSP_0_PCIN44", + "HCLK_DSP_PCIN44" + ], + [ + "DSP_0_ACIN29", + "HCLK_DSP_ACIN29" + ], + [ + "DSP_0_PCIN31", + "HCLK_DSP_PCIN31" + ], + [ + "DSP_0_PCIN15", + "HCLK_DSP_PCIN15" + ], + [ + "DSP_0_ACIN8", + "HCLK_DSP_ACIN8" + ], + [ + "DSP_0_PCIN32", + "HCLK_DSP_PCIN32" + ], + [ + "DSP_0_PCIN27", + "HCLK_DSP_PCIN27" + ], + [ + "DSP_0_PCIN1", + "HCLK_DSP_PCIN1" + ], + [ + "DSP_0_ACIN25", + "HCLK_DSP_ACIN25" + ], + [ + "DSP_0_BCIN4", + "HCLK_DSP_BCIN4" + ], + [ + "DSP_0_PCIN8", + "HCLK_DSP_PCIN8" + ], + [ + "DSP_0_BCIN5", + "HCLK_DSP_BCIN5" + ], + [ + "DSP_0_PCIN30", + "HCLK_DSP_PCIN30" + ], + [ + "DSP_0_BCIN3", + "HCLK_DSP_BCIN3" + ], + [ + "DSP_0_PCIN37", + "HCLK_DSP_PCIN37" + ], + [ + "DSP_0_PCIN29", + "HCLK_DSP_PCIN29" + ], + [ + "DSP_0_PCIN43", + "HCLK_DSP_PCIN43" + ], + [ + "DSP_0_PCIN14", + "HCLK_DSP_PCIN14" + ], + [ + "DSP_0_BCIN7", + "HCLK_DSP_BCIN7" + ], + [ + "DSP_0_PCIN13", + "HCLK_DSP_PCIN13" + ], + [ + "DSP_0_PCIN23", + "HCLK_DSP_PCIN23" + ], + [ + "DSP_0_PCIN36", + "HCLK_DSP_PCIN36" + ], + [ + "DSP_0_PCIN5", + "HCLK_DSP_PCIN5" + ], + [ + "DSP_0_PCIN42", + "HCLK_DSP_PCIN42" + ], + [ + "DSP_0_PCIN7", + "HCLK_DSP_PCIN7" + ], + [ + "DSP_0_ACIN0", + "HCLK_DSP_ACIN0" + ], + [ + "DSP_0_PCIN26", + "HCLK_DSP_PCIN26" + ], + [ + "DSP_0_PCIN10", + "HCLK_DSP_PCIN10" + ], + [ + "DSP_0_BCIN6", + "HCLK_DSP_BCIN6" + ], + [ + "DSP_0_ACIN4", + "HCLK_DSP_ACIN4" + ], + [ + "DSP_0_ACIN18", + "HCLK_DSP_ACIN18" + ], + [ + "DSP_0_CARRYCASCIN", + "HCLK_DSP_CARRYCASCIN" + ] + ], + "tile_types": [ + "DSP_L", + "HCLK_DSP_L" + ] + }, + { + "grid_deltas": [ + 1, + 5 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4BEG2_5", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE2A2_5", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_IMUX6_5", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_EL1BEG1_5", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_WW4B1_5", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_BYP2_5", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_FAN4_5", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_SW4END2_5", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_EE2A3_5", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EE2BEG0_5", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX0_5", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_EE2BEG1_5", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX47_5", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX28_5", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_NW4END2_5", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_WW4B2_5", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_LH4_5", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_LH8_5", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_EE2BEG2_5", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_EE4B0_5", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_NW2A1_5", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_WL1END3_5", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_BYP6_5", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX44_5", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_NE4BEG1_5", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_NE2A0_5", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_EE4A2_5", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX2_5", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_SW2A1_5", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_SW4END0_5", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX26_5", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_WW4B3_5", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_FAN1_5", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_WR1END2_5", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_WR1END3_5", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX32_5", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_NE2A1_5", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_WW2END3_5", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW2END2_5", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_FAN6_5", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_FAN0_5", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_NE2A3_5", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_EE4BEG3_5", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_SE4BEG3_5", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_ER1BEG1_5", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_WR1END0_5", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_5", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_EE4C0_5", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_IMUX41_5", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX19_5", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_IMUX24_5", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_WW4END1_5", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_WW4A3_5", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_SW4A3_5", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EL1BEG2_5", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NW4A3_5", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SE4C2_5", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_LH5_5", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_ER1BEG0_5", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_IMUX45_5", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_LH3_5", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX36_5", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_5", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_NE4BEG0_5", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX3_5", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B9_5", + "VFRAME_LOGIC_OUTS_B9" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_5", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_EL1BEG0_5", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_SW2A0_5", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_LH2_5", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_WL1END2_5", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_5", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_WW4END0_5", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_SE2A1_5", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NW4A0_5", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NW4END3_5", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_NW2A3_5", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_SW4A2_5", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_IMUX4_5", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX5_5", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_NW4A1_5", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_EE4B3_5", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_IMUX33_5", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_EE4C1_5", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_WW4B0_5", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_5", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_SW4END3_5", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX7_5", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_WW4C2_5", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX22_5", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW2A1_5", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_IMUX9_5", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_WL1END0_5", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B10_5", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "CFG_CENTER_SE4C1_5", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX14_5", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_IMUX30_5", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_ER1BEG2_5", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX38_5", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX1_5", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_5", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_IMUX43_5", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_SW4A1_5", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_BYP4_5", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_EE4A0_5", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_NE4C0_5", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_BYP1_5", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW4END2_5", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_BYP0_5", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B11_5", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "CFG_CENTER_NW4A2_5", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_EE4BEG0_5", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_IMUX18_5", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX8_5", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_LH1_5", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_NE4BEG3_5", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX25_5", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_SW4A0_5", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_CLK1_5", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_NW2A2_5", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW4A2_5", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_WW4C1_5", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_CTRL1_5", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_EE4B2_5", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_5", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_IMUX37_5", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_FAN2_5", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_SE4C0_5", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_5", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_WW4C0_5", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX11_5", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_LH7_5", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_IMUX16_5", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_NE4C1_5", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_LH12_5", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_SE2A3_5", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SE4BEG0_5", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_IMUX39_5", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_5", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_WL1END1_5", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_SW2A2_5", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_SE4BEG1_5", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_IMUX17_5", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_EE4C2_5", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_WW2A0_5", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_WW2END0_5", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_NE2A2_5", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_IMUX34_5", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_EE4BEG1_5", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_SW2A3_5", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_IMUX10_5", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SE4C3_5", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_BYP7_5", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_EE4C3_5", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE4A3_5", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_WW2A3_5", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_NW4END0_5", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX35_5", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_IMUX31_5", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_BYP5_5", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_EE2A1_5", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX13_5", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_IMUX12_5", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX42_5", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_BYP3_5", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_NE4C2_5", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_WW4A1_5", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_WR1END1_5", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_FAN3_5", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_SW4END1_5", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_SE2A2_5", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_FAN5_5", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_NE4C3_5", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_IMUX20_5", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_WW4END3_5", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_EE2A0_5", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_EE4A1_5", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX23_5", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_SE4BEG2_5", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE4B1_5", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_IMUX40_5", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_FAN7_5", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_LH6_5", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_WW2END1_5", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_NW4END1_5", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SE2A0_5", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_LH11_5", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_IMUX27_5", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX21_5", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_LH9_5", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EL1BEG3_5", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_NE4BEG2_5", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW4C3_5", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NW2A0_5", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_IMUX46_5", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_5", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_CTRL0_5", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_EE2BEG3_5", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_CLK0_5", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX29_5", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX15_5", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_WW2A2_5", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_LH10_5", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_ER1BEG3_5", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_WW4A0_5", + "VFRAME_WW4A0" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 3 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_3" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_3" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_3" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_3" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_3" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_3" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_3" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_3" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_3" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_3" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_3" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_3" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_3" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_3" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_3" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_3" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_3" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_3" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_3" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_3" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_3" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_3" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_3" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_3" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_3" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_3" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_3" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_3" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_3" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_3" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_3" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_3" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_3" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_3" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_3" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_3" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_3" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_3" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_3" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_3" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_3" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_3" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_3" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_3" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_3" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_3" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_3" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_3" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_3" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_3" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_3" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_3" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_3" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_3" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_3" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_3" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_3" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_3" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_3" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_3" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_3" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_3" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_3" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_3" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_3" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_3" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_3" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_3" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_3" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_3" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_3" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_3" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_3" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_3" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_3" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_3" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_3" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_3" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_3" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_3" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_3" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_3" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_3" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_3" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_3" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_3" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_3" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_3" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_3" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_3" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_3" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_3" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_3" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_3" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_3" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_3" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_3" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_3" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_3" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_3" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_3" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_3" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_3" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_3" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_3" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_3" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_3" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_3" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_3" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_3" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_3" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_3" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_3" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_3" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_3" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_3" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_3" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_3" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_3" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_3" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_3" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_BOT_FUJI2" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "NE6C3", + "T_TERM_UTURN_INT_SE6D0" + ], + [ + "LVB_L0", + "T_TERM_UTURN_INT_LVB_L0" + ], + [ + "SS6D3", + "T_TERM_UTURN_INT_SS6D3" + ], + [ + "LV_L3", + "T_TERM_UTURN_INT_LV_L3" + ], + [ + "SS6END2", + "T_TERM_UTURN_INT_SS6END2" + ], + [ + "SE6D3", + "T_TERM_UTURN_INT_SE6D3" + ], + [ + "LV_L9", + "T_TERM_UTURN_INT_LV_L9" + ], + [ + "SL1END0", + "T_TERM_UTURN_INT_SL1END0" + ], + [ + "SS2A0", + "T_TERM_UTURN_INT_SS2A0" + ], + [ + "WL1BEG3", + "T_TERM_UTURN_INT_WR1BEG_S0" + ], + [ + "NE2BEG2", + "T_TERM_UTURN_INT_SE2A1" + ], + [ + "SS6B0", + "T_TERM_UTURN_INT_SS6B0" + ], + [ + "LV_L6", + "T_TERM_UTURN_INT_LV_L6" + ], + [ + "NE6B1", + "T_TERM_UTURN_INT_SE6C2" + ], + [ + "LVB_L6", + "T_TERM_UTURN_INT_LVB_L5" + ], + [ + "SW6C3", + "T_TERM_UTURN_INT_SW6C3" + ], + [ + "SW6E2", + "T_TERM_UTURN_INT_SW6E2" + ], + [ + "SS6D2", + "T_TERM_UTURN_INT_SS6D2" + ], + [ + "SE2A1", + "T_TERM_UTURN_INT_SE2A1" + ], + [ + "SW2A2", + "T_TERM_UTURN_INT_SW2A2" + ], + [ + "NW6D3", + "T_TERM_UTURN_INT_SW6E0" + ], + [ + "SE2A2", + "T_TERM_UTURN_INT_SE2A2" + ], + [ + "NN6C2", + "T_TERM_UTURN_INT_SS6D1" + ], + [ + "SS2END1", + "T_TERM_UTURN_INT_SS2END1" + ], + [ + "NE6D2", + "T_TERM_UTURN_INT_SE6E1" + ], + [ + "LV_L12", + "T_TERM_UTURN_INT_LV_L5" + ], + [ + "SE2A3", + "T_TERM_UTURN_INT_SE2A3" + ], + [ + "SS6END1", + "T_TERM_UTURN_INT_SS6END1" + ], + [ + "SS6B3", + "T_TERM_UTURN_INT_SS6B3" + ], + [ + "NN2BEG1", + "T_TERM_UTURN_INT_SS2A2" + ], + [ + "SE6B1", + "T_TERM_UTURN_INT_SE6B1" + ], + [ + "NN6A1", + "T_TERM_UTURN_INT_SS6B2" + ], + [ + "SS6E0", + "T_TERM_UTURN_INT_SS6E0" + ], + [ + "BYP_BOUNCE7", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0" + ], + [ + "NW6C1", + "T_TERM_UTURN_INT_SW6D2" + ], + [ + "NN6B3", + "T_TERM_UTURN_INT_SS6C0" + ], + [ + "NW2BEG1", + "T_TERM_UTURN_INT_SW2A2" + ], + [ + "SS6END0", + "T_TERM_UTURN_INT_SS6END0" + ], + [ + "NW2BEG2", + "T_TERM_UTURN_INT_SW2A1" + ], + [ + "NE6B0", + "T_TERM_UTURN_INT_SE6C3" + ], + [ + "SW6B1", + "T_TERM_UTURN_INT_SW6B1" + ], + [ + "NW6A2", + "T_TERM_UTURN_INT_SW6B1" + ], + [ + "NN2A0", + "T_TERM_UTURN_INT_SS2END3" + ], + [ + "WL1END3", + "T_TERM_UTURN_INT_WR1END_S1_0" + ], + [ + "SW6B3", + "T_TERM_UTURN_INT_SW6B3" + ], + [ + "NN6E0", + "T_TERM_UTURN_INT_SS6END3" + ], + [ + "NE6A0", + "T_TERM_UTURN_INT_SE6B3" + ], + [ + "NW6A3", + "T_TERM_UTURN_INT_SW6B0" + ], + [ + "NW6A0", + "T_TERM_UTURN_INT_SW6B3" + ], + [ + "SR1END1", + "T_TERM_UTURN_INT_SR1END1" + ], + [ + "NE6C1", + "T_TERM_UTURN_INT_SE6D2" + ], + [ + "SS6E3", + "T_TERM_UTURN_INT_SS6E3" + ], + [ + "NE2BEG3", + "T_TERM_UTURN_INT_SE2A0" + ], + [ + "SR1END3", + "T_TERM_UTURN_INT_SR1END3" + ], + [ + "SW6D0", + "T_TERM_UTURN_INT_SW6D0" + ], + [ + "SS6D1", + "T_TERM_UTURN_INT_SS6D1" + ], + [ + "NR1BEG1", + "T_TERM_UTURN_INT_SL1END2" + ], + [ + "LV_L13", + "T_TERM_UTURN_INT_LV_L4" + ], + [ + "SE6B0", + "T_TERM_UTURN_INT_SE6B0" + ], + [ + "SW6C1", + "T_TERM_UTURN_INT_SW6C1" + ], + [ + "SW2A0", + "T_TERM_UTURN_INT_SW2A0" + ], + [ + "SE6D1", + "T_TERM_UTURN_INT_SE6D1" + ], + [ + "LV_L4", + "T_TERM_UTURN_INT_LV_L4" + ], + [ + "FAN_BOUNCE_S3_6", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6" + ], + [ + "NW6C3", + "T_TERM_UTURN_INT_SW6D0" + ], + [ + "EL1END_S3_0", + "T_TERM_UTURN_INT_ER1END3" + ], + [ + "LVB_L10", + "T_TERM_UTURN_INT_LVB_L1" + ], + [ + "LV_L1", + "T_TERM_UTURN_INT_LV_L16" + ], + [ + "SS6A2", + "T_TERM_UTURN_INT_SS6A2" + ], + [ + "LVB_L5", + "T_TERM_UTURN_INT_LVB_L5" + ], + [ + "NN6D2", + "T_TERM_UTURN_INT_SS6E1" + ], + [ + "LV_L17", + "T_TERM_UTURN_INT_LV_L17" + ], + [ + "SW6E1", + "T_TERM_UTURN_INT_SW6E1" + ], + [ + "NW2BEG0", + "T_TERM_UTURN_INT_SW2A3" + ], + [ + "SR1END2", + "T_TERM_UTURN_INT_SR1END2" + ], + [ + "SE6C3", + "T_TERM_UTURN_INT_SE6C3" + ], + [ + "NN6BEG1", + "T_TERM_UTURN_INT_SS6A2" + ], + [ + "NE6C0", + "T_TERM_UTURN_INT_SE6D3" + ], + [ + "SE6D0", + "T_TERM_UTURN_INT_SE6D0" + ], + [ + "SE6E0", + "T_TERM_UTURN_INT_SE6E0" + ], + [ + "SW6E0", + "T_TERM_UTURN_INT_SW6E0" + ], + [ + "SL1END3", + "T_TERM_UTURN_INT_SL1END3" + ], + [ + "NN2A2", + "T_TERM_UTURN_INT_SS2END1" + ], + [ + "NE2BEG1", + "T_TERM_UTURN_INT_SE2A2" + ], + [ + "SS2A1", + "T_TERM_UTURN_INT_SS2A1" + ], + [ + "EL1BEG3", + "T_TERM_UTURN_INT_ER1BEG_S0" + ], + [ + "BYP_BOUNCE3", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2" + ], + [ + "NN6B2", + "T_TERM_UTURN_INT_SS6C1" + ], + [ + "NE6A2", + "T_TERM_UTURN_INT_SE6B1" + ], + [ + "NE6D1", + "T_TERM_UTURN_INT_SE6E2" + ], + [ + "NN6D3", + "T_TERM_UTURN_INT_SS6E0" + ], + [ + "WR1BEG_S0", + "T_TERM_UTURN_INT_WR1BEG_S0" + ], + [ + "SE6C1", + "T_TERM_UTURN_INT_SE6C1" + ], + [ + "WR1END_S1_0", + "T_TERM_UTURN_INT_WR1END_S1_0" + ], + [ + "LV_L7", + "T_TERM_UTURN_INT_LV_L7" + ], + [ + "NN2BEG2", + "T_TERM_UTURN_INT_SS2A1" + ], + [ + "NN6C3", + "T_TERM_UTURN_INT_SS6D0" + ], + [ + "NW6B2", + "T_TERM_UTURN_INT_SW6C1" + ], + [ + "SE2A0", + "T_TERM_UTURN_INT_SE2A0" + ], + [ + "SE6E1", + "T_TERM_UTURN_INT_SE6E1" + ], + [ + "LV_L2", + "T_TERM_UTURN_INT_LV_L2" + ], + [ + "NN6E3", + "T_TERM_UTURN_INT_SS6END0" + ], + [ + "SS6A3", + "T_TERM_UTURN_INT_SS6A3" + ], + [ + "NW6C0", + "T_TERM_UTURN_INT_SW6D3" + ], + [ + "NW6D2", + "T_TERM_UTURN_INT_SW6E1" + ], + [ + "SE6B3", + "T_TERM_UTURN_INT_SE6B3" + ], + [ + "SW2A3", + "T_TERM_UTURN_INT_SW2A3" + ], + [ + "NL1BEG0", + "T_TERM_UTURN_INT_SR1END3" + ], + [ + "SL1END2", + "T_TERM_UTURN_INT_SL1END2" + ], + [ + "SS6C2", + "T_TERM_UTURN_INT_SS6C2" + ], + [ + "SE6D2", + "T_TERM_UTURN_INT_SE6D2" + ], + [ + "SE6B2", + "T_TERM_UTURN_INT_SE6B2" + ], + [ + "NW6D1", + "T_TERM_UTURN_INT_SW6E2" + ], + [ + "NN6E1", + "T_TERM_UTURN_INT_SS6END2" + ], + [ + "SE6C0", + "T_TERM_UTURN_INT_SE6C0" + ], + [ + "SS6C3", + "T_TERM_UTURN_INT_SS6C3" + ], + [ + "NW6C2", + "T_TERM_UTURN_INT_SW6D1" + ], + [ + "LVB_L1", + "T_TERM_UTURN_INT_LVB_L1" + ], + [ + "FAN_BOUNCE_S3_0", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0" + ], + [ + "NN6B0", + "T_TERM_UTURN_INT_SS6C3" + ], + [ + "SW6D2", + "T_TERM_UTURN_INT_SW6D2" + ], + [ + "NN6C0", + "T_TERM_UTURN_INT_SS6D3" + ], + [ + "LVB_L8", + "T_TERM_UTURN_INT_LVB_L3" + ], + [ + "NN2A3", + "T_TERM_UTURN_INT_SS2END0" + ], + [ + "SE6C2", + "T_TERM_UTURN_INT_SE6C2" + ], + [ + "NN6D1", + "T_TERM_UTURN_INT_SS6E2" + ], + [ + "LVB_L7", + "T_TERM_UTURN_INT_LVB_L4" + ], + [ + "NN6BEG2", + "T_TERM_UTURN_INT_SS6A1" + ], + [ + "SS2A2", + "T_TERM_UTURN_INT_SS2A2" + ], + [ + "NW6B3", + "T_TERM_UTURN_INT_SW6C0" + ], + [ + "NN6D0", + "T_TERM_UTURN_INT_SS6E3" + ], + [ + "SS6D0", + "T_TERM_UTURN_INT_SS6D0" + ], + [ + "FAN_BOUNCE_S3_4", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4" + ], + [ + "SE6E2", + "T_TERM_UTURN_INT_SE6E2" + ], + [ + "LVB_L3", + "T_TERM_UTURN_INT_LVB_L3" + ], + [ + "SS6END3", + "T_TERM_UTURN_INT_SS6END3" + ], + [ + "BYP_BOUNCE2", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6" + ], + [ + "NW6B0", + "T_TERM_UTURN_INT_SW6C3" + ], + [ + "NN6A0", + "T_TERM_UTURN_INT_SS6B3" + ], + [ + "SS2END0", + "T_TERM_UTURN_INT_SS2END0" + ], + [ + "NR1BEG0", + "T_TERM_UTURN_INT_SL1END3" + ], + [ + "ER1BEG_S0", + "T_TERM_UTURN_INT_ER1BEG_S0" + ], + [ + "SS6A1", + "T_TERM_UTURN_INT_SS6A1" + ], + [ + "LV_L0", + "T_TERM_UTURN_INT_LV_L17" + ], + [ + "SS6B2", + "T_TERM_UTURN_INT_SS6B2" + ], + [ + "SW6B2", + "T_TERM_UTURN_INT_SW6B2" + ], + [ + "NW6A1", + "T_TERM_UTURN_INT_SW6B2" + ], + [ + "SW6C2", + "T_TERM_UTURN_INT_SW6C2" + ], + [ + "LV_L5", + "T_TERM_UTURN_INT_LV_L5" + ], + [ + "SW6E3", + "T_TERM_UTURN_INT_SW6E3" + ], + [ + "LVB_L2", + "T_TERM_UTURN_INT_LVB_L2" + ], + [ + "SS6C1", + "T_TERM_UTURN_INT_SS6C1" + ], + [ + "LV_L14", + "T_TERM_UTURN_INT_LV_L3" + ], + [ + "NN6B1", + "T_TERM_UTURN_INT_SS6C2" + ], + [ + "NW2BEG3", + "T_TERM_UTURN_INT_SW2A0" + ], + [ + "NW6D0", + "T_TERM_UTURN_INT_SW6E3" + ], + [ + "LVB_L11", + "T_TERM_UTURN_INT_LVB_L0" + ], + [ + "NE6B3", + "T_TERM_UTURN_INT_SE6C0" + ], + [ + "NN2A1", + "T_TERM_UTURN_INT_SS2END2" + ], + [ + "NN6A2", + "T_TERM_UTURN_INT_SS6B1" + ], + [ + "SW6C0", + "T_TERM_UTURN_INT_SW6C0" + ], + [ + "NN2BEG0", + "T_TERM_UTURN_INT_SS2A3" + ], + [ + "NN6A3", + "T_TERM_UTURN_INT_SS6B0" + ], + [ + "NE6D3", + "T_TERM_UTURN_INT_SE6E0" + ], + [ + "SS6E1", + "T_TERM_UTURN_INT_SS6E1" + ], + [ + "NR1BEG3", + "T_TERM_UTURN_INT_SL1END0" + ], + [ + "NW6B1", + "T_TERM_UTURN_INT_SW6C2" + ], + [ + "LVB_L4", + "T_TERM_UTURN_INT_LVB_L4" + ], + [ + "SS6C0", + "T_TERM_UTURN_INT_SS6C0" + ], + [ + "LVB_L9", + "T_TERM_UTURN_INT_LVB_L2" + ], + [ + "NN2BEG3", + "T_TERM_UTURN_INT_SS2A0" + ], + [ + "ER1END3", + "T_TERM_UTURN_INT_ER1END3" + ], + [ + "SW6D1", + "T_TERM_UTURN_INT_SW6D1" + ], + [ + "NN6BEG3", + "T_TERM_UTURN_INT_SS6A0" + ], + [ + "SS2END2", + "T_TERM_UTURN_INT_SS2END2" + ], + [ + "FAN_BOUNCE_S3_2", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2" + ], + [ + "NE6A3", + "T_TERM_UTURN_INT_SE6B0" + ], + [ + "NE6B2", + "T_TERM_UTURN_INT_SE6C1" + ], + [ + "NN6BEG0", + "T_TERM_UTURN_INT_SS6A3" + ], + [ + "SS2A3", + "T_TERM_UTURN_INT_SS2A3" + ], + [ + "NL1BEG2", + "T_TERM_UTURN_INT_SR1END1" + ], + [ + "SW6B0", + "T_TERM_UTURN_INT_SW6B0" + ], + [ + "SS2END3", + "T_TERM_UTURN_INT_SS2END3" + ], + [ + "SS6A0", + "T_TERM_UTURN_INT_SS6A0" + ], + [ + "SS6B1", + "T_TERM_UTURN_INT_SS6B1" + ], + [ + "NE6A1", + "T_TERM_UTURN_INT_SE6B2" + ], + [ + "SW6D3", + "T_TERM_UTURN_INT_SW6D3" + ], + [ + "SW2A1", + "T_TERM_UTURN_INT_SW2A1" + ], + [ + "SE6E3", + "T_TERM_UTURN_INT_SE6E3" + ], + [ + "SS6E2", + "T_TERM_UTURN_INT_SS6E2" + ], + [ + "NE2BEG0", + "T_TERM_UTURN_INT_SE2A3" + ], + [ + "BYP_BOUNCE6", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4" + ], + [ + "SL1END1", + "T_TERM_UTURN_INT_SL1END1" + ], + [ + "LV_L15", + "T_TERM_UTURN_INT_LV_L2" + ], + [ + "NN6E2", + "T_TERM_UTURN_INT_SS6END1" + ], + [ + "NL1BEG1", + "T_TERM_UTURN_INT_SR1END2" + ], + [ + "LV_L11", + "T_TERM_UTURN_INT_LV_L6" + ], + [ + "LV_L16", + "T_TERM_UTURN_INT_LV_L16" + ], + [ + "NE6D0", + "T_TERM_UTURN_INT_SE6E3" + ], + [ + "LV_L10", + "T_TERM_UTURN_INT_LV_L7" + ], + [ + "NE6C2", + "T_TERM_UTURN_INT_SE6D1" + ], + [ + "LV_L8", + "T_TERM_UTURN_INT_LV_L9" + ], + [ + "NN6C1", + "T_TERM_UTURN_INT_SS6D2" + ], + [ + "NR1BEG2", + "T_TERM_UTURN_INT_SL1END1" + ] + ], + "tile_types": [ + "INT_L", + "T_TERM_INT" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "IOI_BLOCK_OUTS1_1", + "TERM_INT_BLOCK_OUTS_L_B1" + ], + [ + "IOI_CLK1_1", + "TERM_INT_CLK1" + ], + [ + "IOI_IMUX29_1", + "TERM_INT_IMUX29" + ], + [ + "IOI_BYP0_1", + "TERM_INT_BYP0" + ], + [ + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90" + ], + [ + "IOI_IMUX44_1", + "TERM_INT_IMUX44" + ], + [ + "IOI_IMUX28_1", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX5_1", + "TERM_INT_IMUX5" + ], + [ + "IOI_LOGIC_OUTS0_1", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_IMUX30_1", + "TERM_INT_IMUX30" + ], + [ + "IOI_CTRL1_1", + "TERM_INT_CTRL1" + ], + [ + "IOI_PHASER_TO_IO_ICLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "IOI_PHASER_TO_IO_ICLK_0", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_IMUX43_1", + "TERM_INT_IMUX43" + ], + [ + "IOI_LOGIC_OUTS21_1", + "TERM_INT_LOGIC_OUTS_L_B21" + ], + [ + "IOI_IMUX23_1", + "TERM_INT_IMUX23" + ], + [ + "IOI_IMUX18_1", + "TERM_INT_IMUX18" + ], + [ + "IOI_IMUX37_1", + "TERM_INT_IMUX37" + ], + [ + "IOI_IMUX33_1", + "TERM_INT_IMUX33" + ], + [ + "IOI_LOGIC_OUTS7_1", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "IOI_LOGIC_OUTS18_1", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "IOI_BYP4_1", + "TERM_INT_BYP4" + ], + [ + "IOI_IMUX47_1", + "TERM_INT_IMUX47" + ], + [ + "IOI_LOGIC_OUTS1_1", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "IOI_IMUX34_1", + "TERM_INT_IMUX34" + ], + [ + "IOI_IMUX39_1", + "TERM_INT_IMUX39" + ], + [ + "IOI_LOGIC_OUTS4_1", + "TERM_INT_LOGIC_OUTS_L_B4" + ], + [ + "IOI_BYP1_1", + "TERM_INT_BYP1" + ], + [ + "IOI_FAN6_1", + "TERM_INT_FAN6" + ], + [ + "IOI_IMUX38_1", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX3_1", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX21_1", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX22_1", + "TERM_INT_IMUX22" + ], + [ + "IOI_PHASER_TO_IO_OCLK_0", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "IOI_IMUX26_1", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX11_1", + "TERM_INT_IMUX11" + ], + [ + "IOI_CLK0_1", + "TERM_INT_CLK0" + ], + [ + "IOI_LOGIC_OUTS20_1", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_BYP2_1", + "TERM_INT_BYP2" + ], + [ + "IOI_IMUX8_1", + "TERM_INT_IMUX8" + ], + [ + "IOI_LOGIC_OUTS6_1", + "TERM_INT_LOGIC_OUTS_L_B6" + ], + [ + "IOI_IMUX19_1", + "TERM_INT_IMUX19" + ], + [ + "IOI_LOGIC_OUTS2_1", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_FAN2_1", + "TERM_INT_FAN2" + ], + [ + "IOI_IMUX14_1", + "TERM_INT_IMUX14" + ], + [ + "IOI_IMUX7_1", + "TERM_INT_IMUX7" + ], + [ + "IOI_IMUX40_1", + "TERM_INT_IMUX40" + ], + [ + "IOI_IMUX25_1", + "TERM_INT_IMUX25" + ], + [ + "IOI_IMUX15_1", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX24_1", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX6_1", + "TERM_INT_IMUX6" + ], + [ + "IOI_IMUX4_1", + "TERM_INT_IMUX4" + ], + [ + "IOI_LOGIC_OUTS15_1", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX41_1", + "TERM_INT_IMUX41" + ], + [ + "IOI_LOGIC_OUTS17_1", + "TERM_INT_LOGIC_OUTS_L_B17" + ], + [ + "IOI_BYP6_1", + "TERM_INT_BYP6" + ], + [ + "IOI_FAN4_1", + "TERM_INT_FAN4" + ], + [ + "IOI_FAN1_1", + "TERM_INT_FAN1" + ], + [ + "IOI_IMUX32_1", + "TERM_INT_IMUX32" + ], + [ + "IOI_IMUX45_1", + "TERM_INT_IMUX45" + ], + [ + "IOI_IMUX20_1", + "TERM_INT_IMUX20" + ], + [ + "IOI_IMUX46_1", + "TERM_INT_IMUX46" + ], + [ + "IOI_LOGIC_OUTS12_1", + "TERM_INT_LOGIC_OUTS_L_B12" + ], + [ + "IOI_IMUX31_1", + "TERM_INT_IMUX31" + ], + [ + "IOI_FAN0_1", + "TERM_INT_FAN0" + ], + [ + "IOI_IMUX35_1", + "TERM_INT_IMUX35" + ], + [ + "IOI_BYP7_1", + "TERM_INT_BYP7" + ], + [ + "IOI_IMUX2_1", + "TERM_INT_IMUX2" + ], + [ + "IOI_IMUX9_1", + "TERM_INT_IMUX9" + ], + [ + "IOI_BYP5_1", + "TERM_INT_BYP5" + ], + [ + "IOI_LOGIC_OUTS19_1", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "IOI_FAN3_1", + "TERM_INT_FAN3" + ], + [ + "IOI_PHASER_TO_IO_OCLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "IOI_IMUX36_1", + "TERM_INT_IMUX36" + ], + [ + "IOI_BLOCK_OUTS2_1", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "IOI_FAN7_1", + "TERM_INT_FAN7" + ], + [ + "IOI_LOGIC_OUTS5_1", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "IOI_LOGIC_OUTS11_1", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_IMUX27_1", + "TERM_INT_IMUX27" + ], + [ + "IOI_LOGIC_OUTS8_1", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "IOI_IMUX12_1", + "TERM_INT_IMUX12" + ], + [ + "IOI_LOGIC_OUTS3_1", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_IMUX16_1", + "TERM_INT_IMUX16" + ], + [ + "IOI_LOGIC_OUTS14_1", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "IOI_LOGIC_OUTS9_1", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_FAN5_1", + "TERM_INT_FAN5" + ], + [ + "IOI_IMUX1_1", + "TERM_INT_IMUX1" + ], + [ + "IOI_IMUX42_1", + "TERM_INT_IMUX42" + ], + [ + "IOI_IMUX10_1", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX13_1", + "TERM_INT_IMUX13" + ], + [ + "IOI_BLOCK_OUTS0_1", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_CTRL0_1", + "TERM_INT_CTRL0" + ], + [ + "IOI_LOGIC_OUTS23_1", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_IMUX17_1", + "TERM_INT_IMUX17" + ], + [ + "IOI_BYP3_1", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX0_1", + "TERM_INT_IMUX0" + ], + [ + "IOI_LOGIC_OUTS10_1", + "TERM_INT_LOGIC_OUTS_L_B10" + ] + ], + "tile_types": [ + "RIOI_TBYTESRC", + "R_TERM_INT" + ] + }, + { + "grid_deltas": [ + 1, + 3 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_3" + ], + [ + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_3" + ], + [ + "INT_INTERFACE_CLK0", + "PCIE_CLK0_R_3" + ], + [ + "INT_INTERFACE_BYP0", + "PCIE_BYP0_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT5", + "PCIE_IMUX5_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT36", + "PCIE_IMUX36_R_3" + ], + [ + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_3" + ], + [ + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT43", + "PCIE_IMUX43_R_3" + ], + [ + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_3" + ], + [ + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_3" + ], + [ + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_3" + ], + [ + "INT_INTERFACE_EE4A2", + "PCIE_EE4A2_3" + ], + [ + "INT_INTERFACE_FAN2", + "PCIE_FAN2_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT8", + "PCIE_IMUX8_R_3" + ], + [ + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_3" + ], + [ + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B15", + "PCIE_LOGIC_OUTS_B15_R_3" + ], + [ + "INT_INTERFACE_FAN3", + "PCIE_FAN3_R_3" + ], + [ + "INT_INTERFACE_EE2A2", + "PCIE_EE2A2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT27", + "PCIE_IMUX27_R_3" + ], + [ + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_3" + ], + [ + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_3" + ], + [ + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_3" + ], + [ + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B5", + "PCIE_LOGIC_OUTS_B5_R_3" + ], + [ + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_3" + ], + [ + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_3" + ], + [ + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_3" + ], + [ + "INT_INTERFACE_CTRL1", + "PCIE_CTRL1_R_3" + ], + [ + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_3" + ], + [ + "INT_INTERFACE_EE2A1", + "PCIE_EE2A1_3" + ], + [ + "INT_INTERFACE_EE4A3", + "PCIE_EE4A3_3" + ], + [ + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B9", + "PCIE_LOGIC_OUTS_B9_R_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B12", + "PCIE_LOGIC_OUTS_B12_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT20", + "PCIE_IMUX20_R_3" + ], + [ + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_3" + ], + [ + "INT_INTERFACE_LH12", + "PCIE_LH12_3" + ], + [ + "INT_INTERFACE_FAN0", + "PCIE_FAN0_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT9", + "PCIE_IMUX9_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT22", + "PCIE_IMUX22_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT3", + "PCIE_IMUX3_R_3" + ], + [ + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_3" + ], + [ + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT34", + "PCIE_IMUX34_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT19", + "PCIE_IMUX19_R_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B16", + "PCIE_LOGIC_OUTS_B16_R_3" + ], + [ + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_3" + ], + [ + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT13", + "PCIE_IMUX13_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT18", + "PCIE_IMUX18_R_3" + ], + [ + "INT_INTERFACE_BYP3", + "PCIE_BYP3_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT7", + "PCIE_IMUX7_R_3" + ], + [ + "INT_INTERFACE_FAN5", + "PCIE_FAN5_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT11", + "PCIE_IMUX11_R_3" + ], + [ + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_3" + ], + [ + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B17", + "PCIE_LOGIC_OUTS_B17_R_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B11", + "PCIE_LOGIC_OUTS_B11_R_3" + ], + [ + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_3" + ], + [ + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT42", + "PCIE_IMUX42_R_3" + ], + [ + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT15", + "PCIE_IMUX15_R_3" + ], + [ + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B19", + "PCIE_LOGIC_OUTS_B19_R_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B20", + "PCIE_LOGIC_OUTS_B20_R_3" + ], + [ + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT28", + "PCIE_IMUX28_R_3" + ], + [ + "INT_INTERFACE_BYP1", + "PCIE_BYP1_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT44", + "PCIE_IMUX44_R_3" + ], + [ + "INT_INTERFACE_EE2BEG2", + "PCIE_EE2BEG2_3" + ], + [ + "INT_INTERFACE_LH5", + "PCIE_LH5_3" + ], + [ + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_3" + ], + [ + "INT_INTERFACE_LH7", + "PCIE_LH7_3" + ], + [ + "INT_INTERFACE_CLK1", + "PCIE_CLK1_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT16", + "PCIE_IMUX16_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT24", + "PCIE_IMUX24_R_3" + ], + [ + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_3" + ], + [ + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_3" + ], + [ + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_3" + ], + [ + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_3" + ], + [ + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B2", + "PCIE_LOGIC_OUTS_B2_R_3" + ], + [ + "INT_INTERFACE_BYP2", + "PCIE_BYP2_R_3" + ], + [ + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_3" + ], + [ + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_3" + ], + [ + "INT_INTERFACE_ER1BEG0", + "PCIE_ER1BEG0_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT39", + "PCIE_IMUX39_R_3" + ], + [ + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT26", + "PCIE_IMUX26_R_3" + ], + [ + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_3" + ], + [ + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B6", + "PCIE_LOGIC_OUTS_B6_R_3" + ], + [ + "INT_INTERFACE_BYP5", + "PCIE_BYP5_R_3" + ], + [ + "INT_INTERFACE_CTRL0", + "PCIE_CTRL0_R_3" + ], + [ + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_3" + ], + [ + "INT_INTERFACE_EE2BEG3", + "PCIE_EE2BEG3_3" + ], + [ + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_3" + ], + [ + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_3" + ], + [ + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B23", + "PCIE_LOGIC_OUTS_B23_R_3" + ], + [ + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_3" + ], + [ + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT6", + "PCIE_IMUX6_R_3" + ], + [ + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT17", + "PCIE_IMUX17_R_3" + ], + [ + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_3" + ], + [ + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_3" + ], + [ + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_3" + ], + [ + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B1", + "PCIE_LOGIC_OUTS_B1_R_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B7", + "PCIE_LOGIC_OUTS_B7_R_3" + ], + [ + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_3" + ], + [ + "INT_INTERFACE_BYP7", + "PCIE_BYP7_R_3" + ], + [ + "INT_INTERFACE_EE4C0", + "PCIE_EE4C0_3" + ], + [ + "INT_INTERFACE_LH2", + "PCIE_LH2_3" + ], + [ + "INT_INTERFACE_BYP6", + "PCIE_BYP6_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT32", + "PCIE_IMUX32_R_3" + ], + [ + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_3" + ], + [ + "INT_INTERFACE_EE2BEG1", + "PCIE_EE2BEG1_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT47", + "PCIE_IMUX47_R_3" + ], + [ + "INT_INTERFACE_FAN4", + "PCIE_FAN4_R_3" + ], + [ + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_3" + ], + [ + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_3" + ], + [ + "INT_INTERFACE_MONITOR_P", + "PCIE_MONITOR_P_3" + ], + [ + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_3" + ], + [ + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_3" + ], + [ + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_3" + ], + [ + "INT_INTERFACE_LH8", + "PCIE_LH8_3" + ], + [ + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT35", + "PCIE_IMUX35_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT30", + "PCIE_IMUX30_R_3" + ], + [ + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_3" + ], + [ + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_3" + ], + [ + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_3" + ], + [ + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_3" + ], + [ + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_3" + ], + [ + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT10", + "PCIE_IMUX10_R_3" + ], + [ + "INT_INTERFACE_LH9", + "PCIE_LH9_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B14", + "PCIE_LOGIC_OUTS_B14_R_3" + ], + [ + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_3" + ], + [ + "INT_INTERFACE_LH4", + "PCIE_LH4_3" + ], + [ + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_3" + ], + [ + "INT_INTERFACE_EE4C1", + "PCIE_EE4C1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B10", + "PCIE_LOGIC_OUTS_B10_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT38", + "PCIE_IMUX38_R_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B0", + "PCIE_LOGIC_OUTS_B0_R_3" + ], + [ + "INT_INTERFACE_EL1BEG3", + "PCIE_EL1BEG3_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT37", + "PCIE_IMUX37_R_3" + ], + [ + "INT_INTERFACE_EE2A0", + "PCIE_EE2A0_3" + ], + [ + "INT_INTERFACE_EE2A3", + "PCIE_EE2A3_3" + ], + [ + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_3" + ], + [ + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT21", + "PCIE_IMUX21_R_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B21", + "PCIE_LOGIC_OUTS_B21_R_3" + ], + [ + "INT_INTERFACE_LH10", + "PCIE_LH10_3" + ], + [ + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_3" + ], + [ + "INT_INTERFACE_EE2BEG0", + "PCIE_EE2BEG0_3" + ], + [ + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT45", + "PCIE_IMUX45_R_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B3", + "PCIE_LOGIC_OUTS_B3_R_3" + ], + [ + "INT_INTERFACE_MONITOR_N", + "PCIE_MONITOR_N_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B13", + "PCIE_LOGIC_OUTS_B13_R_3" + ], + [ + "INT_INTERFACE_FAN6", + "PCIE_FAN6_R_3" + ], + [ + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_3" + ], + [ + "INT_INTERFACE_LH1", + "PCIE_LH1_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT46", + "PCIE_IMUX46_R_3" + ], + [ + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B4", + "PCIE_LOGIC_OUTS_B4_R_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B18", + "PCIE_LOGIC_OUTS_B18_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT40", + "PCIE_IMUX40_R_3" + ], + [ + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT1", + "PCIE_IMUX1_R_3" + ], + [ + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_3" + ], + [ + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_3" + ], + [ + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT2", + "PCIE_IMUX2_R_3" + ], + [ + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_3" + ], + [ + "INT_INTERFACE_LH3", + "PCIE_LH3_3" + ], + [ + "INT_INTERFACE_EE4C2", + "PCIE_EE4C2_3" + ], + [ + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_3" + ], + [ + "INT_INTERFACE_EE4B0", + "PCIE_EE4B0_3" + ], + [ + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_3" + ], + [ + "INT_INTERFACE_EE4A1", + "PCIE_EE4A1_3" + ], + [ + "INT_INTERFACE_LH11", + "PCIE_LH11_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT23", + "PCIE_IMUX23_R_3" + ], + [ + "INT_INTERFACE_FAN7", + "PCIE_FAN7_R_3" + ], + [ + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_3" + ], + [ + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_3" + ], + [ + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT41", + "PCIE_IMUX41_R_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B8", + "PCIE_LOGIC_OUTS_B8_R_3" + ], + [ + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_3" + ], + [ + "INT_INTERFACE_EE4A0", + "PCIE_EE4A0_3" + ], + [ + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT31", + "PCIE_IMUX31_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT4", + "PCIE_IMUX4_R_3" + ], + [ + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT29", + "PCIE_IMUX29_R_3" + ], + [ + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT14", + "PCIE_IMUX14_R_3" + ], + [ + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_3" + ], + [ + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_3" + ], + [ + "INT_INTERFACE_FAN1", + "PCIE_FAN1_R_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT33", + "PCIE_IMUX33_R_3" + ], + [ + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_3" + ], + [ + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT0", + "PCIE_IMUX0_R_3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B22", + "PCIE_LOGIC_OUTS_B22_R_3" + ], + [ + "INT_INTERFACE_LH6", + "PCIE_LH6_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT25", + "PCIE_IMUX25_R_3" + ], + [ + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_3" + ], + [ + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_3" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT12", + "PCIE_IMUX12_R_3" + ], + [ + "INT_INTERFACE_BYP4", + "PCIE_BYP4_R_3" + ] + ], + "tile_types": [ + "PCIE_INT_INTERFACE_R", + "PCIE_TOP" + ] + }, + { + "grid_deltas": [ + 1, + 4 + ], + "wire_pairs": [ + [ + "CFG_CENTER_IMUX3_6", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_WW4B0_6", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_EE4BEG1_6", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_NW2A2_6", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_BYP0_6", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_FAN7_6", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX38_6", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_SW4A2_6", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_BYP6_6", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_NE4C3_6", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_IMUX24_6", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_NW4A0_6", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_WW4A2_6", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_WW2A0_6", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_LH6_6", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX18_6", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX1_6", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_SW2A2_6", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_NW4END0_6", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_EE2A1_6", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_WR1END0_6", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_SE4BEG0_6", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_SW4END3_6", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_BYP1_6", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_NW2A1_6", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_IMUX19_6", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_IMUX36_6", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_WL1END0_6", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_NW4A1_6", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_LH2_6", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_EE4BEG3_6", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX37_6", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_EE4B0_6", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_IMUX45_6", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_SW2A3_6", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_BYP2_6", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_EL1BEG0_6", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_FAN1_6", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_LH10_6", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW4END1_6", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_NW4END2_6", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_WW4B3_6", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_LH5_6", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_BYP5_6", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_SE2A2_6", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX17_6", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX4_6", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX2_6", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_FAN3_6", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_IMUX27_6", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_SW4A1_6", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_LH7_6", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_FAN0_6", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_EE4A0_6", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_IMUX9_6", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX13_6", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_SW2A1_6", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_ER1BEG0_6", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_LH12_6", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_WW4C3_6", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX5_6", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX42_6", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_WR1END3_6", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX41_6", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX32_6", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_WW2END3_6", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_IMUX35_6", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_CLK1_6", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX16_6", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WW4A1_6", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_EE4C3_6", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_SE4C2_6", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_SW4END2_6", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_EE2BEG3_6", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX28_6", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_EE4A1_6", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_NE4BEG2_6", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_FAN4_6", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_CLK0_6", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_FAN5_6", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_WW4C2_6", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_BYP4_6", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_EE4BEG0_6", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_FAN2_6", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_NE4BEG1_6", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX8_6", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_SE4BEG3_6", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX29_6", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_EE2A2_6", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_SE4BEG1_6", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_BYP3_6", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_SW4END0_6", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_EE4C0_6", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_EE4C2_6", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_WW2END1_6", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_EE4B2_6", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_LH1_6", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_IMUX23_6", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW4A0_6", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX20_6", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_IMUX7_6", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_SW4END1_6", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_EE2A0_6", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_SE4C3_6", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_WW4END3_6", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX39_6", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_IMUX31_6", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_EE4A2_6", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX44_6", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WW2END2_6", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_EE2BEG2_6", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX30_6", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_EE2BEG1_6", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX15_6", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_CTRL0_6", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_EL1BEG3_6", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_IMUX11_6", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_WW2A2_6", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_WW4C1_6", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_LH8_6", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_NE4BEG3_6", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NE4C2_6", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_IMUX47_6", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_NW4A2_6", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_IMUX21_6", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_SE4C1_6", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_EE4B1_6", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_WW2A1_6", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_WW4B1_6", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_IMUX12_6", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_ER1BEG1_6", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_NW4END1_6", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_NE4BEG0_6", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_EE4C1_6", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_WR1END2_6", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_IMUX46_6", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_IMUX0_6", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WL1END2_6", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_LH3_6", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_SW2A0_6", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_SE4C0_6", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_NW2A0_6", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_NW4A3_6", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_LH9_6", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_IMUX14_6", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_SW4A3_6", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_LH11_6", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_IMUX34_6", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_FAN6_6", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX26_6", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX25_6", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_NE2A3_6", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_EL1BEG2_6", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_SW4A0_6", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_CTRL1_6", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_NE2A2_6", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WL1END3_6", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_ER1BEG3_6", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_NE4C1_6", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_IMUX22_6", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WW4END2_6", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_WR1END1_6", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NW4END3_6", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_WW4B2_6", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_IMUX6_6", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_NE2A0_6", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX40_6", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_ER1BEG2_6", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_SE2A0_6", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_IMUX10_6", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_EE4A3_6", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_EE2A3_6", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NW2A3_6", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NE4C0_6", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_WL1END1_6", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_EE4BEG2_6", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE4B3_6", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_SE4BEG2_6", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_WW2END0_6", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_SE2A3_6", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_EE2BEG0_6", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_SE2A1_6", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_EL1BEG1_6", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_WW4END0_6", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX33_6", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_BYP7_6", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_WW4C0_6", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_NE2A1_6", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_WW2A3_6", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_WW4A3_6", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_IMUX43_6", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_LH4_6", + "VFRAME_LH4" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 5 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_IMUX25_1", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_SW4END3_1", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_WW2END2_1", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_NE4C2_1", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_NW4END0_1", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_LH6_1", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_WW2END3_1", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_SE4C0_1", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_EE4B0_1", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_L_BYP3_1", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_EE2A3_1", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_ER1BEG2_1", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_SW4A2_1", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_NE4BEG0_1", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_L_CTRL1_1", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_SE2A2_1", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_1", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "CMT_FIFO_L_FAN1_1", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_LH8_1", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_1", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "CMT_FIFO_SW4A0_1", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_L_IMUX15_1", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_FAN6_1", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_1", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_1", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "CMT_FIFO_L_IMUX40_1", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_NE4C3_1", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_EE2BEG1_1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_SE4BEG2_1", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_SW4END2_1", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_L_BYP7_1", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_NW2A0_1", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_L_IMUX2_1", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_L_CLK0_1", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_SW2A2_1", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_WW4END3_1", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_NE4C1_1", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_L_IMUX30_1", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_WW4C0_1", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_L_IMUX21_1", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_ER1BEG0_1", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_L_IMUX45_1", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_WW2END1_1", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_L_IMUX16_1", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_1", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "CMT_FIFO_SE4C3_1", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_LH12_1", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_L_IMUX43_1", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_L_IMUX10_1", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_EE2BEG0_1", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_IMUX34_1", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_NW4A2_1", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_L_IMUX3_1", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_SE4C2_1", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_L_FAN7_1", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_L_IMUX5_1", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_EL1BEG1_1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_SW4END0_1", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_EE4B3_1", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_WW4END1_1", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_WL1END3_1", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_L_IMUX14_1", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_SW2A0_1", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_NW4END2_1", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_BYP0_1", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_L_IMUX9_1", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX20_1", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_EE2A2_1", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_WW2A0_1", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_1", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "CMT_FIFO_WL1END0_1", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_BYP5_1", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_L_FAN0_1", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_1", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "CMT_FIFO_WW4B2_1", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_L_IMUX38_1", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_NW2A1_1", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_EE4BEG2_1", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX11_1", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_WR1END3_1", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_L_CTRL0_1", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_L_IMUX32_1", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_EE4C2_1", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_WW4C2_1", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_1", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "CMT_FIFO_LH11_1", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_L_IMUX4_1", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_1", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "CMT_FIFO_NE4BEG2_1", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_WW4C3_1", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_L_IMUX39_1", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_EE2BEG2_1", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_NE2A3_1", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_NE4BEG3_1", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX46_1", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_L_BYP4_1", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_L_IMUX6_1", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_L_IMUX44_1", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_IMUX23_1", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_EE2A0_1", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_1", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_1", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "CMT_FIFO_EE4A1_1", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_L_FAN2_1", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_L_IMUX41_1", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_IMUX28_1", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_WR1END2_1", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_LH9_1", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_LH3_1", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_SE2A0_1", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_WW4B1_1", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_SW4END1_1", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_WL1END2_1", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_L_BYP1_1", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_L_IMUX24_1", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_LH10_1", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_WW4END0_1", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_IMUX1_1", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_FAN4_1", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_WW4B3_1", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_SE4BEG0_1", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX8_1", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_WW4A3_1", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_L_IMUX47_1", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_L_IMUX29_1", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_SW4A3_1", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_1", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "CMT_FIFO_EE4BEG0_1", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_EE4A3_1", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_LH2_1", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_NE2A2_1", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_NW4A3_1", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_WR1END1_1", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_EE4C3_1", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_WW2END0_1", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_WW4A2_1", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_LH5_1", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_L_IMUX19_1", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_EE2A1_1", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_LH7_1", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_NE2A1_1", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_L_IMUX7_1", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_WW4B0_1", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_EE2BEG3_1", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_1", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "CMT_FIFO_SW2A3_1", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_SE2A3_1", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_WR1END0_1", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_L_IMUX18_1", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_L_BYP2_1", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_L_FAN5_1", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_1", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "CMT_FIFO_SE4C1_1", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_LH1_1", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_SE4BEG1_1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_SE4BEG3_1", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_1", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "CMT_FIFO_SE2A1_1", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_EL1BEG3_1", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_NW4A0_1", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_L_BYP6_1", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_NW2A3_1", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_L_IMUX26_1", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_1", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "CMT_FIFO_EE4C1_1", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_EE4B2_1", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_NE4C0_1", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_ER1BEG3_1", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_EE4C0_1", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_EL1BEG0_1", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_EE4BEG3_1", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_NW4A1_1", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_NW4END3_1", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_EE4A2_1", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_IMUX31_1", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_L_IMUX12_1", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_WW4C1_1", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_L_IMUX42_1", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_IMUX33_1", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_SW4A1_1", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_L_IMUX35_1", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_L_IMUX22_1", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_EE4A0_1", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_1", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "CMT_FIFO_WW4A0_1", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_WW4A1_1", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_L_IMUX37_1", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_ER1BEG1_1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_IMUX17_1", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_1", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "CMT_FIFO_EE4BEG1_1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_L_CLK1_1", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_WL1END1_1", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_NE4BEG1_1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX36_1", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_NW2A2_1", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_1", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "CMT_FIFO_L_IMUX13_1", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_1", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "CMT_FIFO_NE2A0_1", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_IMUX0_1", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_LH4_1", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_L_IMUX27_1", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_EE4B1_1", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_1", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "CMT_FIFO_L_FAN3_1", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_NW4END1_1", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_EL1BEG2_1", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_1", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_1", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "CMT_FIFO_WW4END2_1", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_SW2A1_1", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_WW2A3_1", + "INT_INTERFACE_WW2A3" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLK_PMV_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CLK_PMV_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CLK_PMV_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CLK_PMV_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CLK_PMV_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CLK_PMV_LH8_0", + "VBRK_LH8" + ], + [ + "CLK_PMV_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CLK_PMV_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CLK_PMV_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CLK_PMV_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CLK_PMV_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CLK_PMV_LH1_0", + "VBRK_LH1" + ], + [ + "CLK_PMV_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CLK_PMV_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CLK_PMV_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CLK_PMV_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CLK_PMV_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CLK_PMV_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CLK_PMV_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CLK_PMV_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CLK_PMV_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CLK_PMV_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CLK_PMV_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CLK_PMV_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CLK_PMV_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CLK_PMV_LH9_0", + "VBRK_LH9" + ], + [ + "CLK_PMV_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CLK_PMV_LH10_0", + "VBRK_LH10" + ], + [ + "CLK_PMV_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CLK_PMV_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CLK_PMV_LH6_0", + "VBRK_LH6" + ], + [ + "CLK_PMV_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CLK_PMV_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CLK_PMV_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CLK_PMV_LH12_0", + "VBRK_LH12" + ], + [ + "CLK_PMV_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CLK_PMV_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CLK_PMV_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CLK_PMV_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CLK_PMV_LH5_0", + "VBRK_LH5" + ], + [ + "CLK_PMV_MONITOR_N_0", + "VBRK_MONITOR_N" + ], + [ + "CLK_PMV_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CLK_PMV_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CLK_PMV_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CLK_PMV_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CLK_PMV_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CLK_PMV_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CLK_PMV_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CLK_PMV_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CLK_PMV_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CLK_PMV_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CLK_PMV_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CLK_PMV_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CLK_PMV_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CLK_PMV_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CLK_PMV_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CLK_PMV_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CLK_PMV_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CLK_PMV_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CLK_PMV_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CLK_PMV_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CLK_PMV_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CLK_PMV_SW4A1_0", + "VBRK_SW4A1" + ], + [ + "CLK_PMV_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CLK_PMV_LH2_0", + "VBRK_LH2" + ], + [ + "CLK_PMV_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CLK_PMV_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CLK_PMV_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CLK_PMV_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CLK_PMV_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CLK_PMV_MONITOR_P_0", + "VBRK_MONITOR_P" + ], + [ + "CLK_PMV_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CLK_PMV_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CLK_PMV_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CLK_PMV_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CLK_PMV_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CLK_PMV_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CLK_PMV_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CLK_PMV_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CLK_PMV_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CLK_PMV_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CLK_PMV_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CLK_PMV_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CLK_PMV_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CLK_PMV_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CLK_PMV_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CLK_PMV_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CLK_PMV_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CLK_PMV_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CLK_PMV_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CLK_PMV_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CLK_PMV_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CLK_PMV_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CLK_PMV_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CLK_PMV_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CLK_PMV_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CLK_PMV_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CLK_PMV_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CLK_PMV_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CLK_PMV_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CLK_PMV_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CLK_PMV_LH4_0", + "VBRK_LH4" + ], + [ + "CLK_PMV_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CLK_PMV_LH11_0", + "VBRK_LH11" + ], + [ + "CLK_PMV_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CLK_PMV_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CLK_PMV_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CLK_PMV_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CLK_PMV_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CLK_PMV_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CLK_PMV_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CLK_PMV_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "CLK_PMV_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CLK_PMV_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CLK_PMV_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CLK_PMV_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CLK_PMV_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CLK_PMV_LH3_0", + "VBRK_LH3" + ], + [ + "CLK_PMV_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CLK_PMV_LH7_0", + "VBRK_LH7" + ], + [ + "CLK_PMV_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CLK_PMV_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CLK_PMV_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CLK_PMV_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CLK_PMV_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CLK_PMV_WL1END0_0", + "VBRK_WL1END0" + ] + ], + "tile_types": [ + "CLK_PMV", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + -11 + ], + "wire_pairs": [ + [ + "GTXE2_CHANNEL_RXOUTCLK_1", + "GTXE2_CHANNEL_RXOUTCLK_1" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_0", + "GTXE2_CHANNEL_TXOUTCLK_0" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_3", + "GTXE2_CHANNEL_TXOUTCLK_3" + ], + [ + "GTXE2_CHANNEL_RXOUTCLK_2", + "GTXE2_CHANNEL_RXOUTCLK_2" + ], + [ + "GTXE2_CHANNEL_QPLLREFCLK", + "GTXE2_CHANNEL_QPLLREFCLK" + ], + [ + "GTXE2_CHANNEL_RXOUTCLK_3", + "GTXE2_CHANNEL_RXOUTCLK_3" + ], + [ + "GTXE2_CHANNEL_QPLLCLK", + "GTXE2_CHANNEL_QPLLCLK" + ], + [ + "GTXE2_CHANNEL_REFCLK1", + "GTXE2_CHANNEL_REFCLK1" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_2", + "GTXE2_CHANNEL_TXOUTCLK_2" + ], + [ + "GTXE2_CHANNEL_NORTHREFCLK1", + "GTXE2_CHANNEL_NORTHREFCLK1" + ], + [ + "GTXE2_CHANNEL_NORTHREFCLK0", + "GTXE2_CHANNEL_NORTHREFCLK0" + ], + [ + "GTXE2_CHANNEL_SOUTHREFCLK0", + "GTXE2_CHANNEL_SOUTHREFCLK0" + ], + [ + "GTXE2_CHANNEL_SOUTHREFCLK1", + "GTXE2_CHANNEL_SOUTHREFCLK1" + ], + [ + "GTXE2_CHANNEL_REFCLK0", + "GTXE2_CHANNEL_REFCLK0" + ], + [ + "GTXE2_CHANNEL_RXOUTCLK_0", + "GTXE2_CHANNEL_RXOUTCLK_0" + ], + [ + "GTXE2_CHANNEL_TXOUTCLK_1", + "GTXE2_CHANNEL_TXOUTCLK_1" + ] + ], + "tile_types": [ + "GTX_CHANNEL_0", + "GTX_CHANNEL_1" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "BRKH_INT_SR1END2_SLOW", + "SR1BEG2" + ], + [ + "BRKH_INT_SE6D0", + "SE6C0" + ], + [ + "BRKH_INT_NN6D2", + "NN6E2" + ], + [ + "BRKH_INT_SW6C1", + "SW6B1" + ], + [ + "BRKH_INT_NW6A3", + "NW6B3" + ], + [ + "BRKH_INT_SE6C1", + "SE6B1" + ], + [ + "BRKH_INT_NN6A3", + "NN6B3" + ], + [ + "BRKH_INT_SE6C0", + "SE6B0" + ], + [ + "BRKH_INT_L_LV11", + "LV_L12" + ], + [ + "BRKH_INT_SW6D0", + "SW6C0" + ], + [ + "BRKH_INT_SE6D1", + "SE6C1" + ], + [ + "BRKH_INT_SS2END3", + "SS2A3" + ], + [ + "BRKH_INT_SE2A3", + "SE2BEG3" + ], + [ + "BRKH_INT_SS6B0", + "SS6A0" + ], + [ + "BRKH_INT_ER1BEG_S0", + "ER1BEG0" + ], + [ + "BRKH_INT_L_LV15", + "LV_L16" + ], + [ + "BRKH_INT_WW2END3", + "WW2END_N0_3" + ], + [ + "BRKH_INT_SS6END_N0_3", + "SS6END_N0_3" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_4", + "FAN_BOUNCE4" + ], + [ + "BRKH_INT_NE6D2", + "NE6E2" + ], + [ + "BRKH_INT_SW2A1", + "SW2BEG1" + ], + [ + "BRKH_INT_SR1END_N3_3", + "SR1END_N3_3" + ], + [ + "BRKH_INT_LVB_L8", + "LVB_L8" + ], + [ + "BRKH_INT_SS6C0", + "SS6B0" + ], + [ + "BRKH_INT_NE2BEG1", + "NE2A1" + ], + [ + "BRKH_INT_SL1END2_SLOW", + "SL1BEG2" + ], + [ + "BRKH_INT_L_LV13", + "LV_L14" + ], + [ + "BRKH_INT_NR1BEG1_SLOW", + "NR1END1" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_6", + "FAN_BOUNCE6" + ], + [ + "BRKH_INT_NN6A0", + "NN6B0" + ], + [ + "BRKH_INT_SE2A1", + "SE2BEG1" + ], + [ + "BRKH_INT_NN2BEG2", + "NN2A2" + ], + [ + "BRKH_INT_NW6C0", + "NW6D0" + ], + [ + "BRKH_INT_NN6BEG2", + "NN6A2" + ], + [ + "BRKH_INT_SE6C2", + "SE6B2" + ], + [ + "BRKH_INT_SS2END1", + "SS2A1" + ], + [ + "BRKH_INT_NW2BEG0", + "NW2A0" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_0", + "FAN_BOUNCE0" + ], + [ + "BRKH_INT_NE6A0", + "NE6B0" + ], + [ + "BRKH_INT_SW6C0", + "SW6B0" + ], + [ + "BRKH_INT_NE2END_S3_0", + "NE2END0" + ], + [ + "BRKH_INT_NE2BEG0", + "NE2A0" + ], + [ + "BRKH_INT_SW6E3", + "SW6D3" + ], + [ + "BRKH_INT_NW6END_S0_0", + "NW6END0" + ], + [ + "BRKH_INT_BYP_BOUNCE7", + "BYP_BOUNCE_N3_7" + ], + [ + "BRKH_INT_NE6B0", + "NE6C0" + ], + [ + "BRKH_INT_NW6B2", + "NW6C2" + ], + [ + "BRKH_INT_SS6D2", + "SS6C2" + ], + [ + "BRKH_INT_NE6C0", + "NE6D0" + ], + [ + "BRKH_INT_L_LV16", + "LV_L17" + ], + [ + "BRKH_INT_LVB_L4", + "LVB_L4" + ], + [ + "BRKH_INT_SS6A2", + "SS6BEG2" + ], + [ + "BRKH_INT_SS2A3", + "SS2BEG3" + ], + [ + "BRKH_INT_SS2A2", + "SS2BEG2" + ], + [ + "BRKH_INT_NN2BEG3", + "NN2A3" + ], + [ + "BRKH_INT_SW6E1", + "SW6D1" + ], + [ + "BRKH_INT_NE2BEG2", + "NE2A2" + ], + [ + "BRKH_INT_EL1BEG3", + "EL1BEG_N3" + ], + [ + "BRKH_INT_NE6D1", + "NE6E1" + ], + [ + "BRKH_INT_SW6E2", + "SW6D2" + ], + [ + "BRKH_INT_NN6E3", + "NN6END3" + ], + [ + "BRKH_INT_NE6C2", + "NE6D2" + ], + [ + "BRKH_INT_LVB_L9", + "LVB_L9" + ], + [ + "BRKH_INT_SW6B3", + "SW6A3" + ], + [ + "BRKH_INT_NE6C3", + "NE6D3" + ], + [ + "BRKH_INT_SE6B3", + "SE6A3" + ], + [ + "BRKH_INT_NN6E2", + "NN6END2" + ], + [ + "BRKH_INT_NE6A1", + "NE6B1" + ], + [ + "BRKH_INT_SW6B0", + "SW6A0" + ], + [ + "BRKH_INT_NN6END_S1_0", + "NN6END0" + ], + [ + "BRKH_INT_BYP_BOUNCE6", + "BYP_BOUNCE_N3_6" + ], + [ + "BRKH_INT_SW6D3", + "SW6C3" + ], + [ + "BRKH_INT_NN2END_S2_0", + "NN2END0" + ], + [ + "BRKH_INT_NN6BEG3", + "NN6A3" + ], + [ + "BRKH_INT_LVB_L6", + "LVB_L6" + ], + [ + "BRKH_INT_SS6C1", + "SS6B1" + ], + [ + "BRKH_INT_SS6END1", + "SS6E1" + ], + [ + "BRKH_INT_NW6D3", + "NW6E3" + ], + [ + "BRKH_INT_L_LV17", + "LV_L18" + ], + [ + "BRKH_INT_SL1END1_SLOW", + "SL1BEG1" + ], + [ + "BRKH_INT_SE6C3", + "SE6B3" + ], + [ + "BRKH_INT_SS2A0", + "SS2BEG0" + ], + [ + "BRKH_INT_NN6E1", + "NN6END1" + ], + [ + "BRKH_INT_NN6C0", + "NN6D0" + ], + [ + "BRKH_INT_NN6D1", + "NN6E1" + ], + [ + "BRKH_INT_L_LV12", + "LV_L13" + ], + [ + "BRKH_INT_NN6D3", + "NN6E3" + ], + [ + "BRKH_INT_SE6E1", + "SE6D1" + ], + [ + "BRKH_INT_SS2END2", + "SS2A2" + ], + [ + "BRKH_INT_NN6B2", + "NN6C2" + ], + [ + "BRKH_INT_SS2A1", + "SS2BEG1" + ], + [ + "BRKH_INT_NR1BEG3_SLOW", + "NR1END3" + ], + [ + "BRKH_INT_NN6B0", + "NN6C0" + ], + [ + "BRKH_INT_NW2BEG2", + "NW2A2" + ], + [ + "BRKH_INT_NE6D0", + "NE6E0" + ], + [ + "BRKH_INT_NL1BEG1_SLOW", + "NL1END1" + ], + [ + "BRKH_INT_NW6D0", + "NW6E0" + ], + [ + "BRKH_INT_SS6C3", + "SS6B3" + ], + [ + "BRKH_INT_NE6B3", + "NE6C3" + ], + [ + "BRKH_INT_SW6C2", + "SW6B2" + ], + [ + "BRKH_INT_SW6D2", + "SW6C2" + ], + [ + "BRKH_INT_SS6A0", + "SS6BEG0" + ], + [ + "BRKH_INT_BYP_BOUNCE3", + "BYP_BOUNCE_N3_3" + ], + [ + "BRKH_INT_SS2END0", + "SS2A0" + ], + [ + "BRKH_INT_SE6D2", + "SE6C2" + ], + [ + "BRKH_INT_NN6A1", + "NN6B1" + ], + [ + "BRKH_INT_NW6C2", + "NW6D2" + ], + [ + "BRKH_INT_NW6A1", + "NW6B1" + ], + [ + "BRKH_INT_NW6B1", + "NW6C1" + ], + [ + "BRKH_INT_SS6E3", + "SS6D3" + ], + [ + "BRKH_INT_L_LV2", + "LV_L3" + ], + [ + "BRKH_INT_L_LV5", + "LV_L6" + ], + [ + "BRKH_INT_NN6C3", + "NN6D3" + ], + [ + "BRKH_INT_SE6D3", + "SE6C3" + ], + [ + "BRKH_INT_LVB_L11", + "LVB_L11" + ], + [ + "BRKH_INT_WW4END_S0_0", + "WW4END0" + ], + [ + "BRKH_INT_NN2BEG0", + "NN2A0" + ], + [ + "BRKH_INT_LVB_L2", + "LVB_L2" + ], + [ + "BRKH_INT_L_LV14", + "LV_L15" + ], + [ + "BRKH_INT_NE6B1", + "NE6C1" + ], + [ + "BRKH_INT_SS6D0", + "SS6C0" + ], + [ + "BRKH_INT_SS6END2", + "SS6E2" + ], + [ + "BRKH_INT_NW6C1", + "NW6D1" + ], + [ + "BRKH_INT_NN6E0", + "NN6END0" + ], + [ + "BRKH_INT_NN6B3", + "NN6C3" + ], + [ + "BRKH_INT_NE6D3", + "NE6E3" + ], + [ + "BRKH_INT_L_LV7", + "LV_L8" + ], + [ + "BRKH_INT_NW2END_S0_0", + "NW2END0" + ], + [ + "BRKH_INT_LVB_L3", + "LVB_L3" + ], + [ + "BRKH_INT_L_LV8", + "LV_L9" + ], + [ + "BRKH_INT_NE6A2", + "NE6B2" + ], + [ + "BRKH_INT_NW6B0", + "NW6C0" + ], + [ + "BRKH_INT_WL1BEG3", + "WL1BEG_N3" + ], + [ + "BRKH_INT_SW2A0", + "SW2BEG0" + ], + [ + "BRKH_INT_SW6END3", + "SW6END_N0_3" + ], + [ + "BRKH_INT_NN2A0", + "NN2END0" + ], + [ + "BRKH_INT_NN6C2", + "NN6D2" + ], + [ + "BRKH_INT_SS6A1", + "SS6BEG1" + ], + [ + "BRKH_INT_NR1BEG0_SLOW", + "NR1END0" + ], + [ + "BRKH_INT_SE6E3", + "SE6D3" + ], + [ + "BRKH_INT_SW2END3", + "SW2END_N0_3" + ], + [ + "BRKH_INT_SW6B2", + "SW6A2" + ], + [ + "BRKH_INT_SE6B1", + "SE6A1" + ], + [ + "BRKH_INT_NN2A3", + "NN2END3" + ], + [ + "BRKH_INT_NW6D1", + "NW6E1" + ], + [ + "BRKH_INT_SW6D1", + "SW6C1" + ], + [ + "BRKH_INT_WR1END_S1_0", + "WR1END0" + ], + [ + "BRKH_INT_SS6B1", + "SS6A1" + ], + [ + "BRKH_INT_SS2END_N0_3", + "SS2END_N0_3" + ], + [ + "BRKH_INT_SE2A0", + "SE2BEG0" + ], + [ + "BRKH_INT_ER1END3", + "ER1END_N3_3" + ], + [ + "BRKH_INT_LVB_L10", + "LVB_L10" + ], + [ + "BRKH_INT_NW6C3", + "NW6D3" + ], + [ + "BRKH_INT_NW6D2", + "NW6E2" + ], + [ + "BRKH_INT_SS6END3", + "SS6E3" + ], + [ + "BRKH_INT_NN2BEG1", + "NN2A1" + ], + [ + "BRKH_INT_SR1END1_SLOW", + "SR1BEG1" + ], + [ + "BRKH_INT_WR1BEG_S0", + "WR1BEG0" + ], + [ + "BRKH_INT_SW6C3", + "SW6B3" + ], + [ + "BRKH_INT_L_LV0", + "LV_L1" + ], + [ + "BRKH_INT_NN6BEG1", + "NN6A1" + ], + [ + "BRKH_INT_NL1BEG0_SLOW", + "NL1END0" + ], + [ + "BRKH_INT_SW2A3", + "SW2BEG3" + ], + [ + "BRKH_INT_SS6B3", + "SS6A3" + ], + [ + "BRKH_INT_SE2A2", + "SE2BEG2" + ], + [ + "BRKH_INT_NW2BEG3", + "NW2A3" + ], + [ + "BRKH_INT_NW6A0", + "NW6B0" + ], + [ + "BRKH_INT_LVB_L5", + "LVB_L5" + ], + [ + "BRKH_INT_SS6B2", + "SS6A2" + ], + [ + "BRKH_INT_NN2A1", + "NN2END1" + ], + [ + "BRKH_INT_SR1END3_SLOW", + "SR1BEG3" + ], + [ + "BRKH_INT_NN6C1", + "NN6D1" + ], + [ + "BRKH_INT_LVB_L7", + "LVB_L7" + ], + [ + "BRKH_INT_SE6B2", + "SE6A2" + ], + [ + "BRKH_INT_SS6C2", + "SS6B2" + ], + [ + "BRKH_INT_L_LV9", + "LV_L10" + ], + [ + "BRKH_INT_SW2A2", + "SW2BEG2" + ], + [ + "BRKH_INT_SS6E0", + "SS6D0" + ], + [ + "BRKH_INT_SS6E2", + "SS6D2" + ], + [ + "BRKH_INT_EL1END_S3_0", + "EL1END0" + ], + [ + "BRKH_INT_NW2BEG1", + "NW2A1" + ], + [ + "BRKH_INT_NW6A2", + "NW6B2" + ], + [ + "BRKH_INT_SS6END0", + "SS6E0" + ], + [ + "BRKH_INT_NN6BEG0", + "NN6A0" + ], + [ + "BRKH_INT_NR1BEG2_SLOW", + "NR1END2" + ], + [ + "BRKH_INT_NN6A2", + "NN6B2" + ], + [ + "BRKH_INT_L_LV10", + "LV_L11" + ], + [ + "BRKH_INT_NW6B3", + "NW6C3" + ], + [ + "BRKH_INT_SW6B1", + "SW6A1" + ], + [ + "BRKH_INT_SS6E1", + "SS6D1" + ], + [ + "BRKH_INT_NE6C1", + "NE6D1" + ], + [ + "BRKH_INT_WL1END3", + "WL1END_N1_3" + ], + [ + "BRKH_INT_NN6D0", + "NN6E0" + ], + [ + "BRKH_INT_SE6E2", + "SE6D2" + ], + [ + "BRKH_INT_NE6A3", + "NE6B3" + ], + [ + "BRKH_INT_L_LV1", + "LV_L2" + ], + [ + "BRKH_INT_NL1BEG2_SLOW", + "NL1END2" + ], + [ + "BRKH_INT_BYP_BOUNCE2", + "BYP_BOUNCE_N3_2" + ], + [ + "BRKH_INT_L_LV4", + "LV_L5" + ], + [ + "BRKH_INT_SS6D3", + "SS6C3" + ], + [ + "BRKH_INT_NL1END_S3_0", + "NL1END0" + ], + [ + "BRKH_INT_L_LV6", + "LV_L7" + ], + [ + "BRKH_INT_SS6D1", + "SS6C1" + ], + [ + "BRKH_INT_NN2A2", + "NN2END2" + ], + [ + "BRKH_INT_NE6B2", + "NE6C2" + ], + [ + "BRKH_INT_FAN_BOUNCE_S3_2", + "FAN_BOUNCE2" + ], + [ + "BRKH_INT_LVB_L12", + "LVB_L12" + ], + [ + "BRKH_INT_L_LV3", + "LV_L4" + ], + [ + "BRKH_INT_SL1END3_SLOW", + "SL1BEG3" + ], + [ + "BRKH_INT_SE6E0", + "SE6D0" + ], + [ + "BRKH_INT_SW6E0", + "SW6D0" + ], + [ + "BRKH_INT_SL1END0_SLOW", + "SL1BEG0" + ], + [ + "BRKH_INT_SE6B0", + "SE6A0" + ], + [ + "BRKH_INT_NE2BEG3", + "NE2A3" + ], + [ + "BRKH_INT_NN6B1", + "NN6C1" + ], + [ + "BRKH_INT_SS6A3", + "SS6BEG3" + ], + [ + "BRKH_INT_LVB_L1", + "LVB_L1" + ] + ], + "tile_types": [ + "BRKH_INT", + "INT_L" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_LOGIC_OUTS5_8", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CMT_FIFO_LH9_8", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_LH7_8", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_NW2A0_8", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_WW2END2_8", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_WW4C0_8", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_NE4C2_8", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_EE4B1_8", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_NW2A3_8", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_L_IMUX29_8", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_SW4A2_8", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_NE4C3_8", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_EE4BEG1_8", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_WW2A0_8", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_WW4B3_8", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_EE4C2_8", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_L_IMUX31_8", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_L_IMUX17_8", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_NE2A3_8", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_8", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "CMT_FIFO_L_IMUX44_8", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_SE2A0_8", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_NE2A2_8", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_L_BYP6_8", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_NW4A0_8", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_8", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "CMT_FIFO_WW4C1_8", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_L_IMUX25_8", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_L_IMUX26_8", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_IMUX21_8", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_LH10_8", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_L_IMUX22_8", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_WW2A1_8", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_MONITOR_N_8", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CMT_FIFO_SW4A1_8", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_SW4A0_8", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_8", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "CMT_FIFO_L_BYP5_8", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_EE2BEG2_8", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_WW4END3_8", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_L_IMUX46_8", + "INT_INTERFACE_IMUX46" + ], + [ + "FIFO_DQS_IOTOPHASER_3", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "CMT_FIFO_L_IMUX33_8", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_NE4BEG2_8", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_EL1BEG1_8", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_WW4B0_8", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_WL1END3_8", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_L_IMUX4_8", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_L_IMUX42_8", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_WW4C2_8", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_IMUX43_8", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_L_FAN2_8", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_WW4C3_8", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_SE4C2_8", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_EE4A0_8", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_L_CTRL1_8", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_L_IMUX18_8", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_WW4A3_8", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_L_IMUX30_8", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_L_IMUX12_8", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_L_BYP3_8", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_EE2A3_8", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_LH5_8", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_WW4END0_8", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_ER1BEG0_8", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_L_FAN4_8", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_SW4END1_8", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_L_CLK1_8", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_EL1BEG2_8", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_LH3_8", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_L_IMUX16_8", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_SW4END3_8", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_WR1END2_8", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_NW4END1_8", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_L_IMUX0_8", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_NE2A0_8", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_WL1END0_8", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_8", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CMT_FIFO_SW2A3_8", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_L_IMUX8_8", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_8", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CMT_FIFO_NE4C0_8", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_8", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_8", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "CMT_FIFO_L_IMUX39_8", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_L_IMUX5_8", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_LH12_8", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_EE4B3_8", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_WW4B1_8", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_8", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "CMT_FIFO_NW2A2_8", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_EE2A2_8", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_WR1END0_8", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_WW2END1_8", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_LH4_8", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_MONITOR_P_8", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CMT_FIFO_WW4A2_8", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_L_FAN5_8", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_L_CLK0_8", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_8", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CMT_FIFO_NW4END0_8", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_SE4BEG3_8", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_ER1BEG3_8", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_8", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CMT_FIFO_L_CTRL0_8", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_NW4END2_8", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_WW4B2_8", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_L_IMUX10_8", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_SE4BEG2_8", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_WW2END3_8", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_8", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "CMT_FIFO_EE4A1_8", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_SE4C1_8", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_EE4BEG2_8", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_L_FAN7_8", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_EE4B2_8", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_NW4A1_8", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_L_FAN6_8", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_8", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CMT_FIFO_NW4A3_8", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_NE2A1_8", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_NW2A1_8", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_L_BYP1_8", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_WW4END1_8", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_WW4END2_8", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_WW2A3_8", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_WR1END3_8", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_EE2A0_8", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_8", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CMT_FIFO_L_BYP0_8", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_L_IMUX27_8", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_EE4A3_8", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_IMUX3_8", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_EE4C0_8", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_L_BYP7_8", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_ER1BEG1_8", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_8", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "CMT_FIFO_NE4C1_8", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_SE4BEG1_8", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX34_8", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_WL1END2_8", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_WL1END1_8", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_L_IMUX6_8", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_L_IMUX40_8", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_EE4BEG0_8", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_SW4END2_8", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_8", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_8", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "CMT_FIFO_L_IMUX47_8", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_L_IMUX1_8", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_IMUX28_8", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_L_IMUX20_8", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_8", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CMT_FIFO_EE4C1_8", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_NW4A2_8", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_LH1_8", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_WW2END0_8", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_NW4END3_8", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_8", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CMT_FIFO_L_IMUX45_8", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_SE4C0_8", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_WR1END1_8", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_L_IMUX23_8", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_EE2BEG0_8", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_EE4BEG3_8", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_8", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CMT_FIFO_L_BYP4_8", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_8", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "CMT_FIFO_SW2A1_8", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_SE2A3_8", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_L_FAN0_8", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_LH11_8", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_WW4A1_8", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_8", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "CMT_FIFO_L_IMUX38_8", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_NE4BEG3_8", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX15_8", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_SE4BEG0_8", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_EE2BEG3_8", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_WW4A0_8", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_LH6_8", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_L_IMUX11_8", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_EE4B0_8", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_L_IMUX36_8", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_L_FAN3_8", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_L_FAN1_8", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_SW4A3_8", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_NE4BEG1_8", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_SE2A1_8", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_L_IMUX35_8", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_L_IMUX41_8", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_SE2A2_8", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_EE2BEG1_8", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_L_IMUX7_8", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_WW2A2_8", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_L_IMUX32_8", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_EE4C3_8", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_NE4BEG0_8", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_EL1BEG0_8", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_LH2_8", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_LH8_8", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_IMUX19_8", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_EE4A2_8", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_L_IMUX37_8", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_EL1BEG3_8", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_L_IMUX9_8", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX14_8", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_L_BYP2_8", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_SW2A2_8", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_8", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CMT_FIFO_L_IMUX2_8", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_8", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "CMT_FIFO_EE2A1_8", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_ER1BEG2_8", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_IMUX13_8", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_SW4END0_8", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_SW2A0_8", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_L_IMUX24_8", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_SE4C3_8", + "INT_INTERFACE_SE4C3" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX21_2", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX41_2", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_BYP5_2", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX20_2", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX39_2", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B4_2", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_FAN4_2", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX31_2", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX2_2", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_FAN0_2", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_LOGIC_OUTS_B18_2", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX26_2", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX6_2", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B2_2", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX3_2", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_FAN5_2", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_LOGIC_OUTS_B22_2", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B3_2", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_LOGIC_OUTS_B6_2", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_LOGIC_OUTS_B8_2", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX16_2", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX32_2", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B9_2", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_BYP3_2", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX17_2", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX30_2", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_LOGIC_OUTS_B23_2", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX13_2", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_LOGIC_OUTS_B0_2", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX9_2", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX1_2", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_FAN3_2", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN6_2", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX18_2", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX27_2", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B7_2", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_BYP6_2", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX46_2", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP7_2", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX36_2", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_LOGIC_OUTS_B13_2", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B21_2", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_IMUX33_2", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX34_2", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX35_2", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_CTRL0_2", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX37_2", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_BYP4_2", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX5_2", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX44_2", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_FAN1_2", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_BYP1_2", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX12_2", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX0_2", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX29_2", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_CLK0_2", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_LOGIC_OUTS_B16_2", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B11_2", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_IMUX45_2", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX10_2", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B5_2", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_LOGIC_OUTS_B17_2", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX23_2", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_LOGIC_OUTS_B20_2", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX7_2", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX24_2", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX47_2", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX28_2", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX4_2", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX11_2", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP0_2", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_CTRL1_2", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX8_2", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX22_2", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX14_2", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_LOGIC_OUTS_B10_2", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_FAN2_2", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX43_2", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_FAN7_2", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX42_2", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_CLK1_2", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_BYP2_2", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX38_2", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX40_2", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX15_2", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX19_2", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX25_2", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B1_2", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_2", + "VBRK_EXT_LOGIC_OUTS_B19" + ] + ], + "tile_types": [ + "GTX_CHANNEL_0", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4C1_13", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX8_13", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW4END3_13", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_CTRL0_13", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_NE2A0_13", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_LH4_13", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_LH5_13", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_NW4A1_13", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_NE2A1_13", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_FAN0_13", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX31_13", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_IMUX47_13", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_13", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_IMUX45_13", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_SE2A0_13", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_WW4B1_13", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_FAN6_13", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_LH3_13", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_WW4C0_13", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_SE4BEG0_13", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_CLK1_13", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX40_13", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_NE4BEG0_13", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_13", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_BYP0_13", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_WW2END2_13", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_IMUX38_13", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX22_13", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX25_13", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_SW4END3_13", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_WW2END0_13", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WW4END2_13", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_FAN7_13", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_NW4END1_13", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_13", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_EE4A3_13", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_SW4END0_13", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_IMUX43_13", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_SE4BEG3_13", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG3_13", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW4C1_13", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_SE4C3_13", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_EE4C2_13", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX41_13", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_FAN2_13", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_WW4END1_13", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_WW4A1_13", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_IMUX46_13", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WL1END2_13", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_IMUX18_13", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX12_13", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX26_13", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_NE4BEG3_13", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NW4A0_13", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX3_13", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_BYP5_13", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_LH2_13", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_BYP3_13", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_EL1BEG1_13", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_FAN1_13", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_SW2A1_13", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WW4B3_13", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_EE4BEG2_13", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX27_13", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_SE4BEG2_13", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE2BEG3_13", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX20_13", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_EE4C3_13", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_SE2A2_13", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_EE2BEG1_13", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_13", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_WL1END3_13", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_EE4B1_13", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_LH11_13", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_IMUX2_13", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_BYP6_13", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_SW4A2_13", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_LH6_13", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_EE4BEG0_13", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_EE4A0_13", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_SW2A2_13", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_EE2A0_13", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WL1END1_13", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_IMUX1_13", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_SW4A3_13", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_LH7_13", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_IMUX23_13", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NW4END3_13", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_WW4A3_13", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_IMUX4_13", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_SW2A0_13", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_IMUX30_13", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_SW4END1_13", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_IMUX13_13", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_EE4C0_13", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_IMUX33_13", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_ER1BEG1_13", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_LH1_13", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_IMUX16_13", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_LH9_13", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_WR1END2_13", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_13", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_SW2A3_13", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_SW4A0_13", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_NE4BEG1_13", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_NW2A0_13", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_IMUX37_13", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SE4C1_13", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_NE4C0_13", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE2BEG2_13", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX15_13", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_IMUX34_13", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_BYP1_13", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_IMUX0_13", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW4B2_13", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_FAN4_13", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_NW4A2_13", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_WW4C2_13", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_CLK0_13", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_WR1END3_13", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_ER1BEG3_13", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_NE4C2_13", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_13", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_13", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_SE2A1_13", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NW2A1_13", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_BYP7_13", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_WR1END0_13", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EL1BEG0_13", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_NE4C1_13", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_IMUX39_13", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_EE4A1_13", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_WW4B0_13", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_IMUX28_13", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_FAN5_13", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_NW4A3_13", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_13", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_IMUX6_13", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_EE4BEG1_13", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_WW4A2_13", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_IMUX36_13", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_EE4B3_13", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_NE4BEG2_13", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_IMUX32_13", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_FAN3_13", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_WW2A2_13", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_SW4END2_13", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_WW2A1_13", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_BYP4_13", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_EE2BEG0_13", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX5_13", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WW4END0_13", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_WW2END3_13", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW2A3_13", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_EE4A2_13", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX42_13", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_SW4A1_13", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_EL1BEG2_13", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX24_13", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_LH8_13", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_SE2A3_13", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_NW2A3_13", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_BYP2_13", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_ER1BEG2_13", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_WW4C3_13", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NE2A2_13", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WR1END1_13", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_IMUX17_13", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX21_13", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_WW4A0_13", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX35_13", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_WW2A0_13", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_CTRL1_13", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_EE4BEG3_13", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX10_13", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_IMUX11_13", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX44_13", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_EE2A2_13", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_EE2A3_13", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EE4B2_13", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_LH12_13", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX14_13", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_13", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_IMUX7_13", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_NE2A3_13", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_IMUX29_13", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_SE4C2_13", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_NW2A2_13", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_SE4BEG1_13", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_SE4C0_13", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_NW4END0_13", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_NW4END2_13", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_IMUX9_13", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_NE4C3_13", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_13", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_ER1BEG0_13", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_EE2A1_13", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_13", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_IMUX19_13", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_WW2END1_13", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_LH10_13", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_EE4B0_13", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WL1END0_13", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_13", + "VFRAME_LOGIC_OUTS_B17" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLBLM_SW4A0", + "VBRK_SW4A0" + ], + [ + "CLBLM_SE4BEG2", + "VBRK_SE4BEG2" + ], + [ + "CLBLM_EE2BEG2", + "VBRK_EE2BEG2" + ], + [ + "CLBLM_NW4END3", + "VBRK_NW4END3" + ], + [ + "CLBLM_EE4C2", + "VBRK_EE4C2" + ], + [ + "CLBLM_EL1BEG0", + "VBRK_EL1BEG0" + ], + [ + "CLBLM_SE4C1", + "VBRK_SE4C1" + ], + [ + "CLBLM_NE4C2", + "VBRK_NE4C2" + ], + [ + "CLBLM_EE4A1", + "VBRK_EE4A1" + ], + [ + "CLBLM_WW4A2", + "VBRK_WW4A2" + ], + [ + "CLBLM_EE4A3", + "VBRK_EE4A3" + ], + [ + "CLBLM_EE4B3", + "VBRK_EE4B3" + ], + [ + "CLBLM_NW4A3", + "VBRK_NW4A3" + ], + [ + "CLBLM_NE2A3", + "VBRK_NE2A3" + ], + [ + "CLBLM_NW2A1", + "VBRK_NW2A1" + ], + [ + "CLBLM_LH9", + "VBRK_LH9" + ], + [ + "CLBLM_MONITOR_P", + "VBRK_MONITOR_P" + ], + [ + "CLBLM_EE2A0", + "VBRK_EE2A0" + ], + [ + "CLBLM_EE2A1", + "VBRK_EE2A1" + ], + [ + "CLBLM_EE4B0", + "VBRK_EE4B0" + ], + [ + "CLBLM_SE4BEG1", + "VBRK_SE4BEG1" + ], + [ + "CLBLM_WW4END2", + "VBRK_WW4END2" + ], + [ + "CLBLM_EE4BEG3", + "VBRK_EE4BEG3" + ], + [ + "CLBLM_EE4C0", + "VBRK_EE4C0" + ], + [ + "CLBLM_WW4C3", + "VBRK_WW4C3" + ], + [ + "CLBLM_EE2BEG0", + "VBRK_EE2BEG0" + ], + [ + "CLBLM_NE4C3", + "VBRK_NE4C3" + ], + [ + "CLBLM_NW2A0", + "VBRK_NW2A0" + ], + [ + "CLBLM_WL1END2", + "VBRK_WL1END2" + ], + [ + "CLBLM_EE4B1", + "VBRK_EE4B1" + ], + [ + "CLBLM_NE4C1", + "VBRK_NE4C1" + ], + [ + "CLBLM_WR1END2", + "VBRK_WR1END2" + ], + [ + "CLBLM_EE4C3", + "VBRK_EE4C3" + ], + [ + "CLBLM_NE2A0", + "VBRK_NE2A0" + ], + [ + "CLBLM_WW4B3", + "VBRK_WW4B3" + ], + [ + "CLBLM_SW4END3", + "VBRK_SW4END3" + ], + [ + "CLBLM_WL1END1", + "VBRK_WL1END1" + ], + [ + "CLBLM_SW4END0", + "VBRK_SW4END0" + ], + [ + "CLBLM_SE2A3", + "VBRK_SE2A3" + ], + [ + "CLBLM_NE2A2", + "VBRK_NE2A2" + ], + [ + "CLBLM_LH6", + "VBRK_LH6" + ], + [ + "CLBLM_LH2", + "VBRK_LH2" + ], + [ + "CLBLM_EE4B2", + "VBRK_EE4B2" + ], + [ + "CLBLM_SE4C0", + "VBRK_SE4C0" + ], + [ + "CLBLM_NW2A2", + "VBRK_NW2A2" + ], + [ + "CLBLM_MONITOR_N", + "VBRK_MONITOR_N" + ], + [ + "CLBLM_WW2A1", + "VBRK_WW2A1" + ], + [ + "CLBLM_LH3", + "VBRK_LH3" + ], + [ + "CLBLM_LH7", + "VBRK_LH7" + ], + [ + "CLBLM_WW4B0", + "VBRK_WW4B0" + ], + [ + "CLBLM_WW4B2", + "VBRK_WW4B2" + ], + [ + "CLBLM_EE4C1", + "VBRK_EE4C1" + ], + [ + "CLBLM_SE2A1", + "VBRK_SE2A1" + ], + [ + "CLBLM_EE2A3", + "VBRK_EE2A3" + ], + [ + "CLBLM_EE2BEG3", + "VBRK_EE2BEG3" + ], + [ + "CLBLM_WW4END0", + "VBRK_WW4END0" + ], + [ + "CLBLM_LH1", + "VBRK_LH1" + ], + [ + "CLBLM_WW2A2", + "VBRK_WW2A2" + ], + [ + "CLBLM_WR1END0", + "VBRK_WR1END0" + ], + [ + "CLBLM_NE4BEG1", + "VBRK_NE4BEG1" + ], + [ + "CLBLM_SW2A3", + "VBRK_SW2A3" + ], + [ + "CLBLM_WW4END1", + "VBRK_WW4END1" + ], + [ + "CLBLM_SE4BEG3", + "VBRK_SE4BEG3" + ], + [ + "CLBLM_WW4C2", + "VBRK_WW4C2" + ], + [ + "CLBLM_NE4C0", + "VBRK_NE4C0" + ], + [ + "CLBLM_SE2A0", + "VBRK_SE2A0" + ], + [ + "CLBLM_SW4A3", + "VBRK_SW4A3" + ], + [ + "CLBLM_SE4BEG0", + "VBRK_SE4BEG0" + ], + [ + "CLBLM_SW2A1", + "VBRK_SW2A1" + ], + [ + "CLBLM_EE2A2", + "VBRK_EE2A2" + ], + [ + "CLBLM_WW4A0", + "VBRK_WW4A0" + ], + [ + "CLBLM_WW2A0", + "VBRK_WW2A0" + ], + [ + "CLBLM_SW4A2", + "VBRK_SW4A2" + ], + [ + "CLBLM_WW2END0", + "VBRK_WW2END0" + ], + [ + "CLBLM_ER1BEG2", + "VBRK_ER1BEG2" + ], + [ + "CLBLM_SW4END2", + "VBRK_SW4END2" + ], + [ + "CLBLM_EE4BEG2", + "VBRK_EE4BEG2" + ], + [ + "CLBLM_WW2END2", + "VBRK_WW2END2" + ], + [ + "CLBLM_LH11", + "VBRK_LH11" + ], + [ + "CLBLM_SE4C3", + "VBRK_SE4C3" + ], + [ + "CLBLM_LH8", + "VBRK_LH8" + ], + [ + "CLBLM_ER1BEG0", + "VBRK_ER1BEG0" + ], + [ + "CLBLM_EE4A0", + "VBRK_EE4A0" + ], + [ + "CLBLM_WL1END0", + "VBRK_WL1END0" + ], + [ + "CLBLM_NE2A1", + "VBRK_NE2A1" + ], + [ + "CLBLM_ER1BEG3", + "VBRK_ER1BEG3" + ], + [ + "CLBLM_SE2A2", + "VBRK_SE2A2" + ], + [ + "CLBLM_WW2A3", + "VBRK_WW2A3" + ], + [ + "CLBLM_EL1BEG1", + "VBRK_EL1BEG1" + ], + [ + "CLBLM_WW2END1", + "VBRK_WW2END1" + ], + [ + "CLBLM_NW4A0", + "VBRK_NW4A0" + ], + [ + "CLBLM_WL1END3", + "VBRK_WL1END3" + ], + [ + "CLBLM_SW4A1", + "VBRK_SW4A1" + ], + [ + "CLBLM_EE4BEG1", + "VBRK_EE4BEG1" + ], + [ + "CLBLM_LH5", + "VBRK_LH5" + ], + [ + "CLBLM_NW4A2", + "VBRK_NW4A2" + ], + [ + "CLBLM_SW2A2", + "VBRK_SW2A2" + ], + [ + "CLBLM_NE4BEG0", + "VBRK_NE4BEG0" + ], + [ + "CLBLM_LH10", + "VBRK_LH10" + ], + [ + "CLBLM_LH4", + "VBRK_LH4" + ], + [ + "CLBLM_NW4END2", + "VBRK_NW4END2" + ], + [ + "CLBLM_WW2END3", + "VBRK_WW2END3" + ], + [ + "CLBLM_EL1BEG2", + "VBRK_EL1BEG2" + ], + [ + "CLBLM_NW2A3", + "VBRK_NW2A3" + ], + [ + "CLBLM_WW4C0", + "VBRK_WW4C0" + ], + [ + "CLBLM_NW4END0", + "VBRK_NW4END0" + ], + [ + "CLBLM_WW4END3", + "VBRK_WW4END3" + ], + [ + "CLBLM_EE2BEG1", + "VBRK_EE2BEG1" + ], + [ + "CLBLM_SE4C2", + "VBRK_SE4C2" + ], + [ + "CLBLM_EE4BEG0", + "VBRK_EE4BEG0" + ], + [ + "CLBLM_WW4A3", + "VBRK_WW4A3" + ], + [ + "CLBLM_NW4END1", + "VBRK_NW4END1" + ], + [ + "CLBLM_WR1END1", + "VBRK_WR1END1" + ], + [ + "CLBLM_ER1BEG1", + "VBRK_ER1BEG1" + ], + [ + "CLBLM_WR1END3", + "VBRK_WR1END3" + ], + [ + "CLBLM_WW4B1", + "VBRK_WW4B1" + ], + [ + "CLBLM_EL1BEG3", + "VBRK_EL1BEG3" + ], + [ + "CLBLM_SW4END1", + "VBRK_SW4END1" + ], + [ + "CLBLM_LH12", + "VBRK_LH12" + ], + [ + "CLBLM_WW4C1", + "VBRK_WW4C1" + ], + [ + "CLBLM_WW4A1", + "VBRK_WW4A1" + ], + [ + "CLBLM_NE4BEG2", + "VBRK_NE4BEG2" + ], + [ + "CLBLM_NE4BEG3", + "VBRK_NE4BEG3" + ], + [ + "CLBLM_EE4A2", + "VBRK_EE4A2" + ], + [ + "CLBLM_SW2A0", + "VBRK_SW2A0" + ], + [ + "CLBLM_NW4A1", + "VBRK_NW4A1" + ] + ], + "tile_types": [ + "CLBLM_L", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLK_BUFG_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_BUFG_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_BUFG_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ], + [ + "CLK_BUFG_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_BUFG_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_BUFG_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_BUFG_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_BUFG_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_BUFG_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_BUFG_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_BUFG_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_BUFG_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_BUFG_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_BUFG_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_BUFG_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_BUFG_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_BUFG_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_BUFG_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_BUFG_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_BUFG_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_BUFG_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_BUFG_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_BUFG_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_BUFG_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_BUFG_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_BUFG_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_BUFG_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_BUFG_BOT_R_CK_MUXED25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_BUFG_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_BUFG_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_BUFG_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_BUFG_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_BUFG_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ] + ], + "tile_types": [ + "CLK_BUFG_BOT_R", + "CLK_MTBF2" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX5_0", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_FAN1_0", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX11_0", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_FAN5_0", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_BYP5_0", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX6_0", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX0_0", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX40_0", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_CTRL0_0", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX25_0", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX31_0", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B10_0", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_BYP4_0", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX4_0", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX3_0", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_FAN2_0", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX7_0", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX18_0", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX46_0", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX45_0", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX42_0", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_BYP3_0", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX14_0", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX24_0", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B11_0", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_FAN3_0", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN6_0", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX47_0", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX27_0", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B13_0", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_IMUX26_0", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX1_0", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX44_0", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_LOGIC_OUTS_B9_0", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_CLK1_0", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX39_0", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_FAN0_0", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX30_0", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_CTRL1_0", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX12_0", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX19_0", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX38_0", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_BYP2_0", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX22_0", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_FAN4_0", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX20_0", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_LOGIC_OUTS_B15_0", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_BYP7_0", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_BYP0_0", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_LOGIC_OUTS_B14_0", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX43_0", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_LOGIC_OUTS_B12_0", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX13_0", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX21_0", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_CLK0_0", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX35_0", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX36_0", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX41_0", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX28_0", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX10_0", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX9_0", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX32_0", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B8_0", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_BYP6_0", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX8_0", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_BYP1_0", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX15_0", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX17_0", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX29_0", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_FAN7_0", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX2_0", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX16_0", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX33_0", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX37_0", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX34_0", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_LOGIC_OUTS_B21_0", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_IMUX23_0", + "VBRK_EXT_IMUX23" + ] + ], + "tile_types": [ + "GTX_COMMON", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "wire_pairs": [ + [ + "IOI_LEAF_GCLK1", + "IOI_LEAF_GCLK1" + ], + [ + "IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_RCLK_FORIO2" + ], + [ + "IOI_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3_1" + ], + [ + "IOI_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2_1" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_LEAF_GCLK0" + ], + [ + "IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_RCLK_FORIO1" + ], + [ + "IOI_TBYTEIN", + "IOI_TBYTEIN_TERM" + ], + [ + "IOI_IMUX_RC1", + "IOI_IMUX_RC3" + ], + [ + "IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_LEAF_GCLK2" + ], + [ + "IOI_DCI_TSTRST", + "IOI_DCI_TSTRST0" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_LEAF_GCLK3" + ], + [ + "IOI_IMUX_RC0", + "IOI_IMUX_RC2" + ], + [ + "IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_LEAF_GCLK5" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_RCLK_FORIO3" + ], + [ + "IOI_RCLK_DIV_CLR1_1", + "IOI_RCLK_DIV_CLR1" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_RCLK_FORIO0" + ], + [ + "IOI_RCLK_DIV_CLR0_1", + "IOI_RCLK_DIV_CLR0" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_LEAF_GCLK4" + ] + ], + "tile_types": [ + "RIOI", + "RIOI_TBYTETERM" + ] + }, + { + "grid_deltas": [ + 1, + 1 + ], + "wire_pairs": [ + [ + "CFG_CENTER_IMUX2_9", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_EE4A0_9", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_WL1END3_9", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_EE4BEG1_9", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_EE4C2_9", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX10_9", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_ER1BEG3_9", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_WR1END2_9", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SE2A3_9", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SE4BEG0_9", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_NW2A3_9", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NE4C2_9", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_IMUX27_9", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_SW2A2_9", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_IMUX15_9", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_LH3_9", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_EE4B0_9", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_EE2BEG0_9", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_ER1BEG2_9", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_SW4END0_9", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_NW4A3_9", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SW2A1_9", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_SW4A3_9", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EE2A1_9", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_SW4END1_9", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_NW4END2_9", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_IMUX38_9", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_EE4A3_9", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX19_9", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_NE4BEG1_9", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX4_9", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_WW4C2_9", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_NW4A2_9", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_NE2A0_9", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX5_9", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_LH8_9", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_LH11_9", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_NW2A2_9", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_IMUX37_9", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_EL1BEG3_9", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_BYP1_9", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_LH1_9", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_IMUX34_9", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_IMUX45_9", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX42_9", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_EE4BEG2_9", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_SW4END2_9", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_BYP6_9", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_EE4A2_9", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX16_9", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX24_9", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_IMUX46_9", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW4C1_9", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_IMUX41_9", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX26_9", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_LH6_9", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_SW2A3_9", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_EE4BEG3_9", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX28_9", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_FAN3_9", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_BYP4_9", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_CTRL1_9", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_WR1END3_9", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_SE2A0_9", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_FAN7_9", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_NW4A0_9", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_EL1BEG1_9", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_EL1BEG0_9", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_IMUX35_9", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_WW2A0_9", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_WW2END1_9", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_WL1END1_9", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_CLK1_9", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX18_9", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX3_9", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_SE4C1_9", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_EE4BEG0_9", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_FAN2_9", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_EE4B1_9", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_BYP7_9", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_IMUX32_9", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_WW4B0_9", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_IMUX9_9", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_NW2A0_9", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_BYP2_9", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_WW4END3_9", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_CTRL0_9", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_SE4C2_9", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WW4B3_9", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_IMUX17_9", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX33_9", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_SW2A0_9", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_WW4A2_9", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_LH4_9", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_WR1END0_9", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EE2A3_9", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_IMUX11_9", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_NE4C0_9", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_WW4A0_9", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_SE4BEG1_9", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE2A0_9", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_NE2A2_9", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE4A1_9", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_EE4C3_9", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_NE4BEG0_9", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_LH2_9", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_NE4BEG2_9", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW2END2_9", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_NW4A1_9", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_SE4C3_9", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_SE4BEG3_9", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX25_9", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_WL1END2_9", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_FAN0_9", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_LH12_9", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX0_9", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW2A1_9", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_IMUX29_9", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX43_9", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_EL1BEG2_9", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NE4C3_9", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_WW4B1_9", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_EE4B2_9", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX21_9", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_NW2A1_9", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_WL1END0_9", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_IMUX20_9", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_IMUX14_9", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_IMUX12_9", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_WW4END0_9", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_NW4END3_9", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_WW4A3_9", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW4A1_9", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_IMUX13_9", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_FAN4_9", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW4B2_9", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_NW4END1_9", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_EE2A2_9", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_CLK0_9", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX36_9", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW4A2_9", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_IMUX39_9", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_LH5_9", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_WR1END1_9", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_IMUX22_9", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_SW4A1_9", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_FAN1_9", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_NE2A1_9", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX31_9", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_WW2A2_9", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_WW4C3_9", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_LH10_9", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_NW4END0_9", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_WW2A3_9", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_NE4BEG3_9", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_FAN5_9", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_IMUX8_9", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW4END1_9", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX40_9", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_BYP5_9", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_NE4C1_9", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_WW4END2_9", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_EE4C0_9", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_SE4BEG2_9", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_BYP0_9", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX7_9", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_EE4B3_9", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_LH9_9", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_SW4END3_9", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_LH7_9", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_BYP3_9", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_WW2END0_9", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_IMUX23_9", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW4C0_9", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_ER1BEG1_9", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SE2A2_9", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_EE2BEG3_9", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_SE2A1_9", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_WW2END3_9", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_EE4C1_9", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX1_9", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_NE2A3_9", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_FAN6_9", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX44_9", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_ER1BEG0_9", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_EE2BEG1_9", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_SW4A0_9", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_SE4C0_9", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_EE2BEG2_9", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX47_9", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX30_9", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_IMUX6_9", + "VFRAME_IMUX6" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW4END1_2", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE4B0_2", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WW2END0_2", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_LH2_2", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_EE4A1_2", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EE2BEG2_2", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW4A0_2", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_SW4A1_2", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_WW4B2_2", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_SE2A3_2", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_SE4BEG3_2", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EE4C1_2", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_WR1END2_2", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_WW4END2_2", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_NE2A0_2", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EE4BEG1_2", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_WR1END1_2", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_WW4C0_2", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_LH4_2", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_NW4END3_2", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW4C3_2", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4A2_2", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_EE2A3_2", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_WW4A1_2", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EE2BEG3_2", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_NW4END0_2", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SW2A2_2", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WW4END0_2", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EE4B1_2", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NE2A3_2", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_LH12_2", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_LH7_2", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_LH3_2", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_NW4A0_2", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_SW2A0_2", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_WR1END3_2", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_EE4BEG0_2", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_WW4B1_2", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW4A3_2", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NW2A2_2", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_LH10_2", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_LH1_2", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_WW4C2_2", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NW2A3_2", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE4C3_2", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_ER1BEG2_2", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_NW4END1_2", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_LH11_2", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_WW4B3_2", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_NE4C0_2", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_NE4C1_2", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_EE4BEG2_2", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_NE2A2_2", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_NW4END2_2", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WL1END2_2", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_WW2A3_2", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_WW2END2_2", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_NE4BEG2_2", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG0_2", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_SE4BEG0_2", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SE2A0_2", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_SW2A3_2", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_EL1BEG2_2", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_LH9_2", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_SE4C1_2", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_WW2A1_2", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_SE4BEG1_2", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_SE2A2_2", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_EE4C2_2", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_ER1BEG0_2", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_SW4A2_2", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_SE4C3_2", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_EE2BEG1_2", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_WW4B0_2", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_NE2A1_2", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_SE2A1_2", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_EE4C0_2", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WW2END1_2", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_WW4C1_2", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_NW4A1_2", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_SW4END3_2", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NW4A2_2", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_WW2A0_2", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_SW4A0_2", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE2A2_2", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_EE4B2_2", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_SW4END2_2", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_NE4BEG1_2", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_EE4BEG3_2", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WL1END0_2", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SW4END0_2", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EE2BEG0_2", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_SE4C2_2", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_NW2A0_2", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_EE2A1_2", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_WL1END1_2", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_ER1BEG1_2", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WL1END3_2", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_EE4A0_2", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4A3_2", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_WW2END3_2", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_SW4END1_2", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_LH6_2", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_LH8_2", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_EL1BEG1_2", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NW4A3_2", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_NE4BEG3_2", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_EE4B3_2", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_ER1BEG3_2", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_NW2A1_2", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C3_2", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW2A2_2", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_WR1END0_2", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_EL1BEG3_2", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_EE2A0_2", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_LH5_2", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_SW4A3_2", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_WW4END3_2", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_NE4BEG0_2", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_SE4C0_2", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_SW2A1_2", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_NE4C2_2", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE4A2_2", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SE4BEG2_2", + "INT_FEEDTHRU_2_SE4BEG2" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "B_TERM_UTURN_INT_LVB_L1", + "LVB_L11" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "FAN_BOUNCE4" + ], + [ + "B_TERM_UTURN_INT_SW6B0", + "NW6C3" + ], + [ + "B_TERM_UTURN_INT_SS6B1", + "NN6C2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG0", + "SL1BEG0" + ], + [ + "B_TERM_UTURN_INT_LV_L2", + "LV_L2" + ], + [ + "B_TERM_UTURN_INT_SS6C2", + "SS6C2" + ], + [ + "B_TERM_UTURN_INT_SS6E0", + "SS6E0" + ], + [ + "B_TERM_UTURN_INT_SW6A3", + "NW6B0" + ], + [ + "B_TERM_UTURN_INT_SW6B0", + "SW6B0" + ], + [ + "B_TERM_UTURN_INT_SS6BEG0", + "NN6A3" + ], + [ + "B_TERM_UTURN_INT_SS6A2", + "NN6B1" + ], + [ + "B_TERM_UTURN_INT_SS6C2", + "NN6D1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG0", + "SS2BEG0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG1", + "NL1END2" + ], + [ + "B_TERM_UTURN_INT_SW6B1", + "NW6C2" + ], + [ + "B_TERM_UTURN_INT_SS6C3", + "SS6C3" + ], + [ + "B_TERM_UTURN_INT_ER1END_N3_3", + "ER1END_N3_3" + ], + [ + "B_TERM_UTURN_INT_LV_L3", + "LV_L3" + ], + [ + "B_TERM_UTURN_INT_LV_L6", + "LV_L13" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "FAN_BOUNCE0" + ], + [ + "B_TERM_UTURN_INT_SS6A3", + "NN6B0" + ], + [ + "B_TERM_UTURN_INT_SE6D1", + "NE6E2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG1", + "NR1END2" + ], + [ + "B_TERM_UTURN_INT_SW6C0", + "SW6C0" + ], + [ + "B_TERM_UTURN_INT_SE6A0", + "SE6A0" + ], + [ + "B_TERM_UTURN_INT_LVB_L0", + "LVB_L1" + ], + [ + "B_TERM_UTURN_INT_LV_L18", + "LV_L18" + ], + [ + "B_TERM_UTURN_INT_SW6A0", + "NW6B3" + ], + [ + "B_TERM_UTURN_INT_SS6E0", + "NN6END3" + ], + [ + "B_TERM_UTURN_INT_WR1END0", + "WR1END0" + ], + [ + "B_TERM_UTURN_INT_SE6A2", + "SE6A2" + ], + [ + "B_TERM_UTURN_INT_SS6D1", + "SS6D1" + ], + [ + "B_TERM_UTURN_INT_LVB_L2", + "LVB_L10" + ], + [ + "B_TERM_UTURN_INT_LV_L6", + "LV_L6" + ], + [ + "B_TERM_UTURN_INT_SE6B0", + "SE6B0" + ], + [ + "B_TERM_UTURN_INT_LV_L5", + "LV_L5" + ], + [ + "B_TERM_UTURN_INT_SS6A3", + "SS6A3" + ], + [ + "B_TERM_UTURN_INT_ER1BEG0", + "EL1BEG_N3" + ], + [ + "B_TERM_UTURN_INT_SW6B3", + "NW6C0" + ], + [ + "B_TERM_UTURN_INT_LV_L9", + "LV_L10" + ], + [ + "B_TERM_UTURN_INT_LV_L7", + "LV_L7" + ], + [ + "B_TERM_UTURN_INT_SE6C2", + "SE6C2" + ], + [ + "B_TERM_UTURN_INT_SE6B2", + "SE6B2" + ], + [ + "B_TERM_UTURN_INT_SE6B0", + "NE6C3" + ], + [ + "B_TERM_UTURN_INT_SE6D0", + "NE6E3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG3", + "NN6A0" + ], + [ + "B_TERM_UTURN_INT_SW6D3", + "NW6E0" + ], + [ + "B_TERM_UTURN_INT_SS6BEG0", + "SS6BEG0" + ], + [ + "B_TERM_UTURN_INT_SE6D2", + "NE6E1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG1", + "NN2A2" + ], + [ + "B_TERM_UTURN_INT_SS6D1", + "NN6E2" + ], + [ + "B_TERM_UTURN_INT_SE6C3", + "SE6C3" + ], + [ + "B_TERM_UTURN_INT_SS2A2", + "NN2END1" + ], + [ + "B_TERM_UTURN_INT_SE6D1", + "SE6D1" + ], + [ + "B_TERM_UTURN_INT_SS6D0", + "NN6E3" + ], + [ + "B_TERM_UTURN_INT_SS6B3", + "NN6C0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG2", + "SL1BEG2" + ], + [ + "B_TERM_UTURN_INT_SE6A1", + "NE6B2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "FAN_BOUNCE6" + ], + [ + "B_TERM_UTURN_INT_SE6C3", + "NE6D0" + ], + [ + "B_TERM_UTURN_INT_SE6A0", + "NE6B3" + ], + [ + "B_TERM_UTURN_INT_SE6A2", + "NE6B1" + ], + [ + "B_TERM_UTURN_INT_SS6E3", + "SS6E3" + ], + [ + "B_TERM_UTURN_INT_SS2A0", + "SS2A0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG2", + "SS2BEG2" + ], + [ + "B_TERM_UTURN_INT_ER1BEG0", + "ER1BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG3", + "NR1END0" + ], + [ + "B_TERM_UTURN_INT_SW6A3", + "SW6A3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG3", + "NW2A0" + ], + [ + "B_TERM_UTURN_INT_SS6C1", + "NN6D2" + ], + [ + "B_TERM_UTURN_INT_SE6C0", + "NE6D3" + ], + [ + "B_TERM_UTURN_INT_SW6C0", + "NW6D3" + ], + [ + "B_TERM_UTURN_INT_SW6B2", + "SW6B2" + ], + [ + "B_TERM_UTURN_INT_SS6C1", + "SS6C1" + ], + [ + "B_TERM_UTURN_INT_SS6D3", + "SS6D3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG1", + "SE2BEG1" + ], + [ + "B_TERM_UTURN_INT_SS6B1", + "SS6B1" + ], + [ + "B_TERM_UTURN_INT_SW6D0", + "NW6E3" + ], + [ + "B_TERM_UTURN_INT_SS6B0", + "SS6B0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG1", + "NE2A2" + ], + [ + "B_TERM_UTURN_INT_LV_L2", + "LV_L17" + ], + [ + "B_TERM_UTURN_INT_LV_L18", + "LV_L1" + ], + [ + "B_TERM_UTURN_INT_SW6D2", + "NW6E1" + ], + [ + "B_TERM_UTURN_INT_SS6BEG3", + "SS6BEG3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG0", + "SE2BEG0" + ], + [ + "B_TERM_UTURN_INT_SW6B3", + "SW6B3" + ], + [ + "B_TERM_UTURN_INT_SW6C1", + "SW6C1" + ], + [ + "B_TERM_UTURN_INT_SE6C1", + "NE6D2" + ], + [ + "B_TERM_UTURN_INT_SW6A2", + "NW6B1" + ], + [ + "B_TERM_UTURN_INT_SE6D3", + "SE6D3" + ], + [ + "B_TERM_UTURN_INT_LVB_L4", + "LVB_L8" + ], + [ + "B_TERM_UTURN_INT_SW6D2", + "SW6D2" + ], + [ + "B_TERM_UTURN_INT_LVB_L5", + "LVB_L7" + ], + [ + "B_TERM_UTURN_INT_LV_L4", + "LV_L4" + ], + [ + "B_TERM_UTURN_INT_SR1BEG2", + "NL1END1" + ], + [ + "B_TERM_UTURN_INT_SS2A3", + "SS2A3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG2", + "SS6BEG2" + ], + [ + "B_TERM_UTURN_INT_SS6E2", + "SS6E2" + ], + [ + "B_TERM_UTURN_INT_SW6C1", + "NW6D2" + ], + [ + "B_TERM_UTURN_INT_SS6E3", + "NN6END0" + ], + [ + "B_TERM_UTURN_INT_SS6E1", + "SS6E1" + ], + [ + "B_TERM_UTURN_INT_SE6D0", + "SE6D0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG2", + "SR1BEG2" + ], + [ + "B_TERM_UTURN_INT_LVB_L2", + "LVB_L3" + ], + [ + "B_TERM_UTURN_INT_SS6B2", + "SS6B2" + ], + [ + "B_TERM_UTURN_INT_SS6A1", + "SS6A1" + ], + [ + "B_TERM_UTURN_INT_WR1BEG0", + "WL1BEG_N3" + ], + [ + "B_TERM_UTURN_INT_SW6D1", + "SW6D1" + ], + [ + "B_TERM_UTURN_INT_SS6B0", + "NN6C3" + ], + [ + "B_TERM_UTURN_INT_SS6C0", + "SS6C0" + ], + [ + "B_TERM_UTURN_INT_LV_L3", + "LV_L16" + ], + [ + "B_TERM_UTURN_INT_SS2BEG3", + "SS2BEG3" + ], + [ + "B_TERM_UTURN_INT_SS2BEG1", + "SS2BEG1" + ], + [ + "B_TERM_UTURN_INT_SW6C2", + "SW6C2" + ], + [ + "B_TERM_UTURN_INT_LV_L8", + "LV_L11" + ], + [ + "B_TERM_UTURN_INT_SW2BEG0", + "SW2BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG1", + "SL1BEG1" + ], + [ + "B_TERM_UTURN_INT_SS6D3", + "NN6E0" + ], + [ + "B_TERM_UTURN_INT_LVB_L4", + "LVB_L5" + ], + [ + "B_TERM_UTURN_INT_SS6A0", + "NN6B3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG1", + "SW2BEG1" + ], + [ + "B_TERM_UTURN_INT_SW6A1", + "NW6B2" + ], + [ + "B_TERM_UTURN_INT_SS6C3", + "NN6D0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG2", + "NE2A1" + ], + [ + "B_TERM_UTURN_INT_LVB_L0", + "LVB_L12" + ], + [ + "B_TERM_UTURN_INT_SS6A0", + "SS6A0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG1", + "SR1BEG1" + ], + [ + "B_TERM_UTURN_INT_SW6C2", + "NW6D1" + ], + [ + "B_TERM_UTURN_INT_SW6C3", + "SW6C3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG1", + "SS6BEG1" + ], + [ + "B_TERM_UTURN_INT_SR1BEG3", + "SR1BEG3" + ], + [ + "B_TERM_UTURN_INT_LV_L9", + "LV_L9" + ], + [ + "B_TERM_UTURN_INT_SE6D3", + "NE6E0" + ], + [ + "B_TERM_UTURN_INT_SE6B3", + "SE6B3" + ], + [ + "B_TERM_UTURN_INT_WR1END0", + "WL1END_N1_3" + ], + [ + "B_TERM_UTURN_INT_SW6D0", + "SW6D0" + ], + [ + "B_TERM_UTURN_INT_SW6A2", + "SW6A2" + ], + [ + "B_TERM_UTURN_INT_SW2BEG0", + "NW2A3" + ], + [ + "B_TERM_UTURN_INT_LV_L4", + "LV_L15" + ], + [ + "B_TERM_UTURN_INT_SR1BEG3", + "NL1END0" + ], + [ + "B_TERM_UTURN_INT_SS6E1", + "NN6END2" + ], + [ + "B_TERM_UTURN_INT_SS2A0", + "NN2END3" + ], + [ + "B_TERM_UTURN_INT_SW6C3", + "NW6D0" + ], + [ + "B_TERM_UTURN_INT_SE6B2", + "NE6C1" + ], + [ + "B_TERM_UTURN_INT_SW2BEG1", + "NW2A2" + ], + [ + "B_TERM_UTURN_INT_SS6C0", + "NN6D3" + ], + [ + "B_TERM_UTURN_INT_SS6A1", + "NN6B2" + ], + [ + "B_TERM_UTURN_INT_SS6A2", + "SS6A2" + ], + [ + "B_TERM_UTURN_INT_SS6E2", + "NN6END1" + ], + [ + "B_TERM_UTURN_INT_SS6D2", + "SS6D2" + ], + [ + "B_TERM_UTURN_INT_SS6B2", + "NN6C1" + ], + [ + "B_TERM_UTURN_INT_LVB_L5", + "LVB_L6" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "BYP_BOUNCE_N3_7" + ], + [ + "B_TERM_UTURN_INT_SW6D1", + "NW6E2" + ], + [ + "B_TERM_UTURN_INT_ER1END_N3_3", + "EL1END0" + ], + [ + "B_TERM_UTURN_INT_SS2A3", + "NN2END0" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "BYP_BOUNCE_N3_6" + ], + [ + "B_TERM_UTURN_INT_SS6D2", + "NN6E1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG2", + "NN2A1" + ], + [ + "B_TERM_UTURN_INT_LV_L5", + "LV_L14" + ], + [ + "B_TERM_UTURN_INT_SE6B1", + "SE6B1" + ], + [ + "B_TERM_UTURN_INT_SW2BEG3", + "SW2BEG3" + ], + [ + "B_TERM_UTURN_INT_SE6C1", + "SE6C1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "BYP_BOUNCE_N3_2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "BYP_BOUNCE_N3_3" + ], + [ + "B_TERM_UTURN_INT_SS6D0", + "SS6D0" + ], + [ + "B_TERM_UTURN_INT_SW2BEG2", + "NW2A1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "FAN_BOUNCE2" + ], + [ + "B_TERM_UTURN_INT_SS6BEG2", + "NN6A1" + ], + [ + "B_TERM_UTURN_INT_SS2A1", + "NN2END2" + ], + [ + "B_TERM_UTURN_INT_SE6B3", + "NE6C0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG3", + "NE2A0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG3", + "NN2A0" + ], + [ + "B_TERM_UTURN_INT_SW6B2", + "NW6C1" + ], + [ + "B_TERM_UTURN_INT_SW6A0", + "SW6A0" + ], + [ + "B_TERM_UTURN_INT_LV_L8", + "LV_L8" + ], + [ + "B_TERM_UTURN_INT_SL1BEG2", + "NR1END1" + ], + [ + "B_TERM_UTURN_INT_SE2BEG0", + "NE2A3" + ], + [ + "B_TERM_UTURN_INT_SW6B1", + "SW6B1" + ], + [ + "B_TERM_UTURN_INT_SS2A2", + "SS2A2" + ], + [ + "B_TERM_UTURN_INT_LVB_L1", + "LVB_L2" + ], + [ + "B_TERM_UTURN_INT_SS6B3", + "SS6B3" + ], + [ + "B_TERM_UTURN_INT_SE6D2", + "SE6D2" + ], + [ + "B_TERM_UTURN_INT_SW6END_N0_3", + "SW6END_N0_3" + ], + [ + "B_TERM_UTURN_INT_SE6A3", + "SE6A3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG2", + "SW2BEG2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG0", + "NR1END3" + ], + [ + "B_TERM_UTURN_INT_LVB_L3", + "LVB_L4" + ], + [ + "B_TERM_UTURN_INT_SE6C2", + "NE6D1" + ], + [ + "B_TERM_UTURN_INT_WR1BEG0", + "WR1BEG0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG0", + "NN2A3" + ], + [ + "B_TERM_UTURN_INT_SE6C0", + "SE6C0" + ], + [ + "B_TERM_UTURN_INT_LV_L7", + "LV_L12" + ], + [ + "B_TERM_UTURN_INT_SW6END_N0_3", + "NW6END0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG3", + "SL1BEG3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG3", + "SE2BEG3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG1", + "NN6A2" + ], + [ + "B_TERM_UTURN_INT_SE2BEG2", + "SE2BEG2" + ], + [ + "B_TERM_UTURN_INT_SE6A1", + "SE6A1" + ], + [ + "B_TERM_UTURN_INT_SE6B1", + "NE6C2" + ], + [ + "B_TERM_UTURN_INT_SW6D3", + "SW6D3" + ], + [ + "B_TERM_UTURN_INT_SE6A3", + "NE6B0" + ], + [ + "B_TERM_UTURN_INT_SW6A1", + "SW6A1" + ], + [ + "B_TERM_UTURN_INT_SS2A1", + "SS2A1" + ], + [ + "B_TERM_UTURN_INT_LVB_L3", + "LVB_L9" + ] + ], + "tile_types": [ + "B_TERM_INT", + "INT_L" + ] + }, + { + "grid_deltas": [ + -1, + 6 + ], + "wire_pairs": [ + [ + "CMT_FIFO_NE4BEG0_0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_L_CLK1_0", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_WW4A0_0", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_WW4B0_0", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_L_IMUX11_0", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_0", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "CMT_FIFO_LH7_0", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_L_BYP1_0", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_L_IMUX12_0", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_L_IMUX16_0", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_EE4C2_0", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_NE2A0_0", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_SW4A2_0", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_SW4END1_0", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_EE4B2_0", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_NE2A1_0", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_SW2A0_0", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_EE2A0_0", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_L_FAN2_0", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_EE2BEG3_0", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_ER1BEG3_0", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_WL1END0_0", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_L_FAN0_0", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_WR1END0_0", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_NW4END2_0", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_IMUX20_0", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_0", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CMT_FIFO_MONITOR_P_0", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CMT_FIFO_EE2BEG2_0", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_NE4BEG1_0", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_0", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "FIFO_DQS_IOTOPHASER_66", + "L_INT_INTER_DQS_IOTOPHASER" + ], + [ + "CMT_FIFO_LH6_0", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_SE4C3_0", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_WW2END2_0", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_0", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CMT_FIFO_NW2A2_0", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_LH2_0", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_SE4BEG3_0", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX18_0", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_L_IMUX44_0", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_IMUX22_0", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_L_IMUX40_0", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_SE2A1_0", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_L_IMUX26_0", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_NE4C2_0", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_WR1END1_0", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_WW2A0_0", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_ER1BEG0_0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_L_IMUX14_0", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_LH4_0", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_WW2END3_0", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_EE2A2_0", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_NW4END3_0", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_L_IMUX29_0", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_0", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_0", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "CMT_FIFO_SE2A2_0", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_EE4BEG1_0", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_SW4A3_0", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_NW4A0_0", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_NE4C0_0", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_0", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_0", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "CMT_FIFO_WL1END3_0", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_SW4A1_0", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_L_IMUX39_0", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_WL1END2_0", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_L_IMUX23_0", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_EE4A2_0", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_WL1END1_0", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_L_IMUX46_0", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_EE4C0_0", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_L_FAN6_0", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_L_BYP5_0", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_L_IMUX36_0", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_WW4B3_0", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_SE4BEG1_0", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX9_0", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_LH12_0", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_L_FAN1_0", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_L_IMUX1_0", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_CTRL0_0", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_L_IMUX32_0", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_SW4END2_0", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_L_IMUX25_0", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_0", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "CMT_FIFO_SW4END3_0", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_WW2A3_0", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_0", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CMT_FIFO_EE2BEG1_0", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_WW2A1_0", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_EL1BEG0_0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_L_IMUX45_0", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_WW2END0_0", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_NE4C1_0", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_L_CLK0_0", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_EE4C3_0", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_L_IMUX35_0", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_SW2A1_0", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_L_IMUX31_0", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_L_BYP7_0", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_WW4C3_0", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_WW4END3_0", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_NW2A1_0", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_EE4BEG2_0", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_NW4A3_0", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_SW4END0_0", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_SW2A3_0", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_NW4A1_0", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_WR1END3_0", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_EE4A1_0", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_L_IMUX2_0", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_L_IMUX42_0", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_0", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CMT_FIFO_NW2A3_0", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_NW4END1_0", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_WW4A3_0", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_SW4A0_0", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_WW4C0_0", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_NE4C3_0", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_0", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "CMT_FIFO_SE2A0_0", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_L_CTRL1_0", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_WW4B2_0", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_0", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "CMT_FIFO_L_IMUX4_0", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_L_IMUX34_0", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_0", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "CMT_FIFO_SE4C0_0", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_EE2BEG0_0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_0", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CMT_FIFO_WW4C2_0", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_EE4B0_0", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_LH1_0", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_0", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CMT_FIFO_NE2A3_0", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_L_IMUX7_0", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_NE2A2_0", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_FIFO_L_BYP6_0", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_L_IMUX0_0", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_EE4C1_0", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_0", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "CMT_FIFO_L_IMUX5_0", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_L_IMUX27_0", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_SW2A2_0", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_NW4END0_0", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_SE4C2_0", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_L_IMUX8_0", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_IMUX38_0", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_EE4BEG3_0", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_LH5_0", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_WW4END0_0", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_IMUX43_0", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_LH11_0", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_EE4BEG0_0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX24_0", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_0", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "CMT_FIFO_WW4B1_0", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_0", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CMT_FIFO_WW4END1_0", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_WW4END2_0", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_EE4A0_0", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_LH9_0", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_L_BYP3_0", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_L_IMUX13_0", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_L_BYP0_0", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_L_IMUX6_0", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_WW2A2_0", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_MONITOR_N_0", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CMT_FIFO_L_IMUX15_0", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_FAN7_0", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_L_BYP2_0", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_0", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_0", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CMT_FIFO_SE4BEG2_0", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_EL1BEG2_0", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_WR1END2_0", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_EL1BEG1_0", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_LH10_0", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_L_IMUX21_0", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_WW2END1_0", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_WW4C1_0", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_EE2A3_0", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_SE2A3_0", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_LH8_0", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_IMUX30_0", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_L_FAN5_0", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_L_FAN4_0", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_L_IMUX28_0", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_EE4B1_0", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_NE4BEG3_0", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX33_0", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_L_IMUX41_0", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_IMUX10_0", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_ER1BEG2_0", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_IMUX3_0", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_NW2A0_0", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_ER1BEG1_0", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_EE2A1_0", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_SE4C1_0", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_L_IMUX19_0", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_WW4A1_0", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_L_IMUX17_0", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_EE4B3_0", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_EE4A3_0", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_NW4A2_0", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_L_IMUX47_0", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_EL1BEG3_0", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_0", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CMT_FIFO_L_IMUX37_0", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_L_FAN3_0", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_0", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CMT_FIFO_LH3_0", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_0", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "CMT_FIFO_WW4A2_0", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_L_BYP4_0", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_SE4BEG0_0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_NE4BEG2_0", + "INT_INTERFACE_NE4BEG2" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "wire_pairs": [ + [ + "IOI_LEAF_GCLK1", + "IOI_LEAF_GCLK1" + ], + [ + "IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "IOI_TBYTEIN", + "IOI_TBYTEIN" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_RCLK_FORIO2" + ], + [ + "IOI_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3_1" + ], + [ + "IOI_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2_1" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_LEAF_GCLK0" + ], + [ + "IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_RCLK_FORIO1" + ], + [ + "IOI_IMUX_RC1", + "IOI_IMUX_RC3" + ], + [ + "IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_LEAF_GCLK2" + ], + [ + "IOI_DCI_TSTRST", + "IOI_DCI_TSTRST0" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_LEAF_GCLK3" + ], + [ + "IOI_IMUX_RC0", + "IOI_IMUX_RC2" + ], + [ + "IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_LEAF_GCLK5" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_RCLK_FORIO3" + ], + [ + "IOI_RCLK_DIV_CLR1_1", + "IOI_RCLK_DIV_CLR1" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_RCLK_FORIO0" + ], + [ + "IOI_RCLK_DIV_CLR0_1", + "IOI_RCLK_DIV_CLR0" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_LEAF_GCLK4" + ] + ], + "tile_types": [ + "RIOI", + "RIOI_TBYTESRC" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CLK_HROW_SW4A2_4", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_IMUX28_4", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_IMUX43_4", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_IMUX4_4", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_SE4C3_4", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_IMUX14_4", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_EL1BEG3_4", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_NW4A0_4", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_IMUX5_4", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_SW4END0_4", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_IMUX35_4", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_LH3_4", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_NE4BEG1_4", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_EE4B0_4", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_WW2END0_4", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_NE4BEG2_4", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_EE4B1_4", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_EE4A0_4", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_FAN0_4", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_WW4B3_4", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_EE4C0_4", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_EE4A3_4", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_WR1END1_4", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_EE4A2_4", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_IMUX0_4", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_WL1END2_4", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_LH10_4", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_EE2BEG1_4", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_SW2A0_4", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_NE4C3_4", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_WW4C1_4", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_WW4C2_4", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_IMUX8_4", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_HROW_EE4BEG0_4", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_NW4END1_4", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_HROW_IMUX41_4", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_EL1BEG2_4", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_EE2A0_4", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_SE4BEG1_4", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_ER1BEG0_4", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_IMUX3_4", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_HROW_SE4BEG2_4", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_EE2BEG3_4", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_FAN5_4", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_SW2A3_4", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_LH5_4", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_IMUX23_4", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_CTRL1_4", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_WW4C3_4", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_EE2BEG2_4", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_WW2A1_4", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_WW2END2_4", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_IMUX30_4", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_BYP0_4", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_EE4BEG3_4", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_NE2A1_4", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_IMUX26_4", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_FAN1_4", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_IMUX13_4", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_IMUX7_4", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_HROW_MONITOR_P_4", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_HROW_WW4A3_4", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_HROW_EE4A1_4", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_ER1BEG1_4", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_NW4END2_4", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_WW4END0_4", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_WR1END3_4", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_IMUX29_4", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_WW4B0_4", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_SE2A3_4", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_IMUX19_4", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_LH11_4", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_BYP2_4", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_SW4A0_4", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_SE4C2_4", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_BYP3_4", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_NE4C1_4", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_NE2A0_4", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_WL1END1_4", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_LH2_4", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_NW4A1_4", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_IMUX1_4", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_IMUX31_4", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_HROW_FAN4_4", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_HROW_FAN3_4", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_SW4END3_4", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_IMUX2_4", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_NE2A3_4", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_MONITOR_N_4", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_HROW_LH8_4", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_CLK1_4", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_IMUX27_4", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_IMUX21_4", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_EL1BEG1_4", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_SE4C1_4", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_HROW_EL1BEG0_4", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_WW4A1_4", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_EE4B3_4", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_HROW_BYP7_4", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_SW2A2_4", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_IMUX37_4", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_IMUX34_4", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_BYP4_4", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_WW2A0_4", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_IMUX10_4", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_SE2A2_4", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_EE4C3_4", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_LH12_4", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_FAN2_4", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_HROW_EE2A1_4", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_BYP5_4", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_LH6_4", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_IMUX25_4", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_LH7_4", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_EE4C1_4", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_WW4END3_4", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_HROW_SW2A1_4", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_NE2A2_4", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_IMUX32_4", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_NW4END3_4", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_IMUX45_4", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_IMUX11_4", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_WL1END0_4", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_IMUX42_4", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_WW4B2_4", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_CTRL0_4", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_EE4BEG2_4", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_IMUX39_4", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_IMUX33_4", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_FAN6_4", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_NW2A3_4", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_LH4_4", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_IMUX24_4", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_WW4END1_4", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_SW4A3_4", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_LH1_4", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_WR1END2_4", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_SE2A0_4", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_WR1END0_4", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_ER1BEG3_4", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_IMUX46_4", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_ER1BEG2_4", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_LH9_4", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_EE2A2_4", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_NW2A0_4", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_IMUX47_4", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_NW2A2_4", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_WW4C0_4", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_CLK0_4", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_EE2A3_4", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_FAN7_4", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_IMUX44_4", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_HROW_SW4A1_4", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_IMUX38_4", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_IMUX12_4", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_WW2A3_4", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_EE4B2_4", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_HROW_IMUX16_4", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_SE4BEG3_4", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_SE4BEG0_4", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_BYP1_4", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_IMUX36_4", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_IMUX40_4", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_WW4A2_4", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_NE4C0_4", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_BYP6_4", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_SE4C0_4", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_IMUX18_4", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_NW4A3_4", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_WL1END3_4", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_IMUX22_4", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_NE4BEG0_4", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_WW4A0_4", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_WW2A2_4", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_IMUX9_4", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_WW2END3_4", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_WW2END1_4", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_IMUX15_4", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_NE4BEG3_4", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_NW4END0_4", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_SW4END1_4", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_HROW_IMUX20_4", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_EE2BEG0_4", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_SW4END2_4", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_IMUX6_4", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_NW2A1_4", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_WW4B1_4", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_NE4C2_4", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_EE4BEG1_4", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_IMUX17_4", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_NW4A2_4", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_EE4C2_4", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_SE2A1_4", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_WW4END2_4", + "INT_INTERFACE_WW4END2" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW4C0_6", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4END2_6", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW2A3_6", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4BEG0_6", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_6", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_6", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A3_6", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4A1_6", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4B0_6", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SW4A3_6", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_NE4BEG2_6", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE4B0_6", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE4C1_6", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A1_6", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END1_6", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_6", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_6", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_6", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C1_6", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW4A1_6", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_ER1BEG0_6", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_6", + "VBRK_LH1" + ], + [ + "CMT_TOP_EE4BEG2_6", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG2_6", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SE2A0_6", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WL1END2_6", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A1_6", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WR1END3_6", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NE2A2_6", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_LH4_6", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END1_6", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH8_6", + "VBRK_LH8" + ], + [ + "CMT_TOP_SE4BEG2_6", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4END2_6", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH6_6", + "VBRK_LH6" + ], + [ + "CMT_TOP_MONITOR_N_6", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_LH3_6", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C2_6", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NE2A3_6", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE4C3_6", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4A0_6", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C3_6", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_ER1BEG3_6", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_6", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WR1END2_6", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END0_6", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4C0_6", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SE4C0_6", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SE2A3_6", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW2END1_6", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH2_6", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW2END3_6", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE2A0_6", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NE4C0_6", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WW4C3_6", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END1_6", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4BEG3_6", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A1_6", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4B3_6", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4B1_6", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A1_6", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WL1END3_6", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH7_6", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW2A0_6", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A0_6", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NW2A1_6", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2BEG0_6", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_6", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE2BEG1_6", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4END3_6", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NW4END3_6", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4BEG1_6", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_6", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_SW4END2_6", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NW4A3_6", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4BEG0_6", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SW4A2_6", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4C1_6", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2A0_6", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4END0_6", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_ER1BEG2_6", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2A3_6", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW2A0_6", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_LH11_6", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE2BEG3_6", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH9_6", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4A3_6", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4A0_6", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE2A0_6", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NW2A2_6", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_6", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C3_6", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4A1_6", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WR1END0_6", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4C2_6", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_MONITOR_P_6", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_EE4C1_6", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG3_6", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW4B3_6", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END2_6", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A2_6", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4B2_6", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW4A0_6", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW2A1_6", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH5_6", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4B1_6", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_NE4BEG1_6", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH10_6", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_6", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4A2_6", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG1_6", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE2A1_6", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C2_6", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END0_6", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SE4BEG0_6", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_6", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE4A2_6", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4END0_6", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4BEG3_6", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A3_6", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_6", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_6", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A2_6", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NW2A3_6", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_6", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE4C2_6", + "VBRK_SE4C2" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "GTXE2_BYP3_1", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX31_1", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX35_1", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX17_1", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX28_1", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_FAN7_1", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX21_1", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_FAN6_1", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX12_1", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B18_1", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX40_1", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B14_1", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX8_1", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX0_1", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX6_1", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX44_1", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_FAN3_1", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX7_1", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX37_1", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_BYP6_1", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX10_1", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX20_1", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN1_1", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_1", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B6_1", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_FAN2_1", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX41_1", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B13_1", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_CLK0_1", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX5_1", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX24_1", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_CLK1_1", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_CTRL0_1", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_CTRL1_1", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX9_1", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_LOGIC_OUTS_B16_1", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX34_1", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_LOGIC_OUTS_B3_1", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX45_1", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX43_1", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX19_1", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_LOGIC_OUTS_B4_1", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B1_1", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX29_1", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_BYP1_1", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX15_1", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_LOGIC_OUTS_B15_1", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX39_1", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B17_1", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX27_1", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B10_1", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX47_1", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX46_1", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX36_1", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_LOGIC_OUTS_B2_1", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_FAN5_1", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_BYP0_1", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_FAN4_1", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_BYP5_1", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX3_1", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX22_1", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX38_1", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_LOGIC_OUTS_B0_1", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_LOGIC_OUTS_B5_1", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX30_1", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_BYP4_1", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX42_1", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX13_1", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP7_1", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX25_1", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B9_1", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX18_1", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_LOGIC_OUTS_B7_1", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_IMUX32_1", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN0_1", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_LOGIC_OUTS_B22_1", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B20_1", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_LOGIC_OUTS_B11_1", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_LOGIC_OUTS_B8_1", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_BYP2_1", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX26_1", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX33_1", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX2_1", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX11_1", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX16_1", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX4_1", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX23_1", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX14_1", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX1_1", + "VBRK_EXT_IMUX1" + ] + ], + "tile_types": [ + "GTX_CHANNEL_1", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CLK_PMV_LH10_1", + "VBRK_LH10" + ], + [ + "CLK_PMV_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CLK_PMV_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CLK_PMV_NE4C2_1", + "VBRK_NE4C2" + ], + [ + "CLK_PMV_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "CLK_PMV_WW4END3_1", + "VBRK_WW4END3" + ], + [ + "CLK_PMV_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "CLK_PMV_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "CLK_PMV_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "CLK_PMV_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "CLK_PMV_WW4C0_1", + "VBRK_WW4C0" + ], + [ + "CLK_PMV_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CLK_PMV_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "CLK_PMV_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "CLK_PMV_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "CLK_PMV_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "CLK_PMV_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CLK_PMV_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "CLK_PMV_LH2_1", + "VBRK_LH2" + ], + [ + "CLK_PMV_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CLK_PMV_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "CLK_PMV_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "CLK_PMV_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CLK_PMV_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "CLK_PMV_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "CLK_PMV_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CLK_PMV_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "CLK_PMV_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CLK_PMV_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "CLK_PMV_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "CLK_PMV_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CLK_PMV_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "CLK_PMV_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "CLK_PMV_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CLK_PMV_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "CLK_PMV_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CLK_PMV_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "CLK_PMV_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CLK_PMV_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "CLK_PMV_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CLK_PMV_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "CLK_PMV_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "CLK_PMV_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "CLK_PMV_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CLK_PMV_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CLK_PMV_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CLK_PMV_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CLK_PMV_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "CLK_PMV_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "CLK_PMV_WW4END2_1", + "VBRK_WW4END2" + ], + [ + "CLK_PMV_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CLK_PMV_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CLK_PMV_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "CLK_PMV_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "CLK_PMV_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CLK_PMV_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CLK_PMV_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "CLK_PMV_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CLK_PMV_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "CLK_PMV_LH8_1", + "VBRK_LH8" + ], + [ + "CLK_PMV_EE2BEG0_1", + "VBRK_EE2BEG0" + ], + [ + "CLK_PMV_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "CLK_PMV_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "CLK_PMV_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CLK_PMV_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "CLK_PMV_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "CLK_PMV_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CLK_PMV_NE4C3_1", + "VBRK_NE4C3" + ], + [ + "CLK_PMV_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "CLK_PMV_LH3_1", + "VBRK_LH3" + ], + [ + "CLK_PMV_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CLK_PMV_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CLK_PMV_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "CLK_PMV_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CLK_PMV_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CLK_PMV_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "CLK_PMV_LH12_1", + "VBRK_LH12" + ], + [ + "CLK_PMV_WW4END1_1", + "VBRK_WW4END1" + ], + [ + "CLK_PMV_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "CLK_PMV_LH7_1", + "VBRK_LH7" + ], + [ + "CLK_PMV_EE2A1_1", + "VBRK_EE2A1" + ], + [ + "CLK_PMV_LH5_1", + "VBRK_LH5" + ], + [ + "CLK_PMV_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CLK_PMV_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CLK_PMV_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "CLK_PMV_LH4_1", + "VBRK_LH4" + ], + [ + "CLK_PMV_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "CLK_PMV_NW2A0_1", + "VBRK_NW2A0" + ], + [ + "CLK_PMV_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "CLK_PMV_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CLK_PMV_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "CLK_PMV_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "CLK_PMV_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CLK_PMV_EE2BEG1_1", + "VBRK_EE2BEG1" + ], + [ + "CLK_PMV_LH1_1", + "VBRK_LH1" + ], + [ + "CLK_PMV_WW4C1_1", + "VBRK_WW4C1" + ], + [ + "CLK_PMV_WW4C3_1", + "VBRK_WW4C3" + ], + [ + "CLK_PMV_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "CLK_PMV_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CLK_PMV_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "CLK_PMV_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "CLK_PMV_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CLK_PMV_LH9_1", + "VBRK_LH9" + ], + [ + "CLK_PMV_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CLK_PMV_LH6_1", + "VBRK_LH6" + ], + [ + "CLK_PMV_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CLK_PMV_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "CLK_PMV_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CLK_PMV_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CLK_PMV_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "CLK_PMV_LH11_1", + "VBRK_LH11" + ], + [ + "CLK_PMV_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "CLK_PMV_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CLK_PMV_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "CLK_PMV_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CLK_PMV_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CLK_PMV_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CLK_PMV_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "CLK_PMV_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "CLK_PMV_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CLK_PMV_EE2A0_1", + "VBRK_EE2A0" + ], + [ + "CLK_PMV_EE2A2_1", + "VBRK_EE2A2" + ], + [ + "CLK_PMV_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "CLK_PMV_ER1BEG2_1", + "VBRK_ER1BEG2" + ] + ], + "tile_types": [ + "CLK_PMV", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "T_TERM_UTURN_INT_SL1END3_SLOW", + "NR1BEG0" + ], + [ + "T_TERM_UTURN_INT_SS6END1", + "NN6E2" + ], + [ + "T_TERM_INT_UTURN_LV_R7", + "LV7" + ], + [ + "T_TERM_UTURN_INT_WR1END_S1_0", + "WL1END3" + ], + [ + "T_TERM_UTURN_INT_SS6D0", + "SS6D0" + ], + [ + "T_TERM_UTURN_INT_LVB0", + "LVB11" + ], + [ + "T_TERM_UTURN_INT_SS6B1", + "NN6A2" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", + "BYP_BOUNCE7" + ], + [ + "T_TERM_UTURN_INT_SS2A2", + "NN2BEG1" + ], + [ + "T_TERM_UTURN_INT_SW6B0", + "NW6A3" + ], + [ + "T_TERM_UTURN_INT_SS6B2", + "NN6A1" + ], + [ + "T_TERM_UTURN_INT_SE6E0", + "NE6D3" + ], + [ + "T_TERM_UTURN_INT_SS2END0", + "NN2A3" + ], + [ + "T_TERM_UTURN_INT_SS6A2", + "SS6A2" + ], + [ + "T_TERM_UTURN_INT_LVB5", + "LVB6" + ], + [ + "T_TERM_UTURN_INT_SS6C0", + "SS6C0" + ], + [ + "T_TERM_UTURN_INT_SR1END1_SLOW", + "SR1END1" + ], + [ + "T_TERM_UTURN_INT_SS6B2", + "SS6B2" + ], + [ + "T_TERM_UTURN_INT_SS2END3", + "SS2END3" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", + "FAN_BOUNCE_S3_0" + ], + [ + "T_TERM_UTURN_INT_SW6C0", + "SW6C0" + ], + [ + "T_TERM_UTURN_INT_SE6B3", + "SE6B3" + ], + [ + "T_TERM_UTURN_INT_LVB0", + "LVB0" + ], + [ + "T_TERM_UTURN_INT_SS6A3", + "NN6BEG0" + ], + [ + "T_TERM_UTURN_INT_ER1BEG_S0", + "ER1BEG_S0" + ], + [ + "T_TERM_UTURN_INT_SE6C1", + "NE6B2" + ], + [ + "T_TERM_UTURN_INT_LVB1", + "LVB1" + ], + [ + "T_TERM_UTURN_INT_SS6A1", + "NN6BEG2" + ], + [ + "T_TERM_UTURN_INT_SS6C0", + "NN6B3" + ], + [ + "T_TERM_UTURN_INT_SW6B1", + "SW6B1" + ], + [ + "T_TERM_UTURN_INT_SE2A2", + "NE2BEG1" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", + "BYP_BOUNCE2" + ], + [ + "T_TERM_UTURN_INT_LVB3", + "LVB3" + ], + [ + "T_TERM_UTURN_INT_SW6E3", + "NW6D0" + ], + [ + "T_TERM_UTURN_INT_SW6C0", + "NW6B3" + ], + [ + "T_TERM_UTURN_INT_SW6E2", + "SW6E2" + ], + [ + "T_TERM_UTURN_INT_SS6D3", + "NN6C0" + ], + [ + "T_TERM_UTURN_INT_SS6B0", + "NN6A3" + ], + [ + "T_TERM_UTURN_INT_SW6C1", + "NW6B2" + ], + [ + "T_TERM_UTURN_INT_SS6E3", + "NN6D0" + ], + [ + "T_TERM_UTURN_INT_SE6D2", + "NE6C1" + ], + [ + "T_TERM_UTURN_INT_SW6B1", + "NW6A2" + ], + [ + "T_TERM_UTURN_INT_SW2A2", + "SW2A2" + ], + [ + "T_TERM_UTURN_INT_SE6D1", + "SE6D1" + ], + [ + "T_TERM_UTURN_INT_SW6C3", + "SW6C3" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", + "FAN_BOUNCE_S3_4" + ], + [ + "T_TERM_UTURN_INT_SS6B1", + "SS6B1" + ], + [ + "T_TERM_UTURN_INT_SW6D0", + "NW6C3" + ], + [ + "T_TERM_UTURN_INT_SS6B0", + "SS6B0" + ], + [ + "T_TERM_UTURN_INT_SS6E3", + "SS6E3" + ], + [ + "T_TERM_UTURN_INT_SW6E3", + "SW6E3" + ], + [ + "T_TERM_UTURN_INT_SS6END3", + "NN6E0" + ], + [ + "T_TERM_UTURN_INT_SR1END3_SLOW", + "NL1BEG0" + ], + [ + "T_TERM_UTURN_INT_SW6E2", + "NW6D1" + ], + [ + "T_TERM_UTURN_INT_SL1END1_SLOW", + "NR1BEG2" + ], + [ + "T_TERM_UTURN_INT_SE2A1", + "NE2BEG2" + ], + [ + "T_TERM_UTURN_INT_SE6B1", + "NE6A2" + ], + [ + "T_TERM_UTURN_INT_SE6C3", + "SE6C3" + ], + [ + "T_TERM_UTURN_INT_SE6D0", + "NE6C3" + ], + [ + "T_TERM_UTURN_INT_SW6E0", + "SW6E0" + ], + [ + "T_TERM_UTURN_INT_SW6D2", + "SW6D2" + ], + [ + "T_TERM_UTURN_INT_SS6A0", + "NN6BEG3" + ], + [ + "T_TERM_UTURN_INT_SS6C3", + "SS6C3" + ], + [ + "T_TERM_UTURN_INT_SW6B2", + "NW6A1" + ], + [ + "T_TERM_UTURN_INT_SL1END1_SLOW", + "SL1END1" + ], + [ + "T_TERM_UTURN_INT_SW6D3", + "SW6D3" + ], + [ + "T_TERM_UTURN_INT_SE6B0", + "NE6A3" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", + "FAN_BOUNCE_S3_2" + ], + [ + "T_TERM_UTURN_INT_SW6E0", + "NW6D3" + ], + [ + "T_TERM_UTURN_INT_SS6C2", + "NN6B1" + ], + [ + "T_TERM_UTURN_INT_SW2A3", + "NW2BEG0" + ], + [ + "T_TERM_UTURN_INT_LVB4", + "LVB4" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", + "FAN_BOUNCE_S3_6" + ], + [ + "T_TERM_INT_UTURN_LV_R6", + "LV6" + ], + [ + "T_TERM_UTURN_INT_SS6E0", + "NN6D3" + ], + [ + "T_TERM_UTURN_INT_SW6D1", + "NW6C2" + ], + [ + "T_TERM_UTURN_INT_LVB5", + "LVB5" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", + "BYP_BOUNCE6" + ], + [ + "T_TERM_UTURN_INT_SW6D1", + "SW6D1" + ], + [ + "T_TERM_UTURN_INT_SS2A0", + "NN2BEG3" + ], + [ + "T_TERM_UTURN_INT_SE2A2", + "SE2A2" + ], + [ + "T_TERM_UTURN_INT_SE6E0", + "SE6E0" + ], + [ + "T_TERM_UTURN_INT_SW6C2", + "SW6C2" + ], + [ + "T_TERM_UTURN_INT_SW2A1", + "SW2A1" + ], + [ + "T_TERM_INT_UTURN_LV_R16", + "LV16" + ], + [ + "T_TERM_UTURN_INT_SS6END0", + "NN6E3" + ], + [ + "T_TERM_UTURN_INT_SE6B2", + "NE6A1" + ], + [ + "T_TERM_UTURN_INT_SS6D2", + "NN6C1" + ], + [ + "T_TERM_UTURN_INT_SL1END0_SLOW", + "SL1END0" + ], + [ + "T_TERM_UTURN_INT_SL1END0_SLOW", + "NR1BEG3" + ], + [ + "T_TERM_UTURN_INT_SS6D3", + "SS6D3" + ], + [ + "T_TERM_UTURN_INT_SW2A3", + "SW2A3" + ], + [ + "T_TERM_UTURN_INT_SW2A0", + "NW2BEG3" + ], + [ + "T_TERM_UTURN_INT_SS6A0", + "SS6A0" + ], + [ + "T_TERM_UTURN_INT_SS2END0", + "SS2END0" + ], + [ + "T_TERM_UTURN_INT_SS6E0", + "SS6E0" + ], + [ + "T_TERM_UTURN_INT_LVB1", + "LVB10" + ], + [ + "T_TERM_UTURN_INT_SS2END3", + "NN2A0" + ], + [ + "T_TERM_UTURN_INT_LVB2", + "LVB2" + ], + [ + "T_TERM_INT_UTURN_LV_R17", + "LV0" + ], + [ + "T_TERM_UTURN_INT_SS2A3", + "NN2BEG0" + ], + [ + "T_TERM_UTURN_INT_SE6D1", + "NE6C2" + ], + [ + "T_TERM_UTURN_INT_SS6END2", + "SS6END2" + ], + [ + "T_TERM_UTURN_INT_SS6END3", + "SS6END3" + ], + [ + "T_TERM_INT_UTURN_LV_R5", + "LV5" + ], + [ + "T_TERM_INT_UTURN_LV_R5", + "LV12" + ], + [ + "T_TERM_UTURN_INT_SS6A1", + "SS6A1" + ], + [ + "T_TERM_UTURN_INT_SS6A2", + "NN6BEG1" + ], + [ + "T_TERM_UTURN_INT_SW2A2", + "NW2BEG1" + ], + [ + "T_TERM_UTURN_INT_SE2A0", + "SE2A0" + ], + [ + "T_TERM_UTURN_INT_SE6C2", + "NE6B1" + ], + [ + "T_TERM_UTURN_INT_SS6B3", + "NN6A0" + ], + [ + "T_TERM_UTURN_INT_WR1BEG_S0", + "WL1BEG3" + ], + [ + "T_TERM_UTURN_INT_SS2END2", + "SS2END2" + ], + [ + "T_TERM_INT_UTURN_LV_R17", + "LV17" + ], + [ + "T_TERM_UTURN_INT_SS6D1", + "SS6D1" + ], + [ + "T_TERM_UTURN_INT_SR1END1_SLOW", + "NL1BEG2" + ], + [ + "T_TERM_UTURN_INT_ER1END3", + "EL1END_S3_0" + ], + [ + "T_TERM_UTURN_INT_SE6C3", + "NE6B0" + ], + [ + "T_TERM_UTURN_INT_SE6B0", + "SE6B0" + ], + [ + "T_TERM_UTURN_INT_ER1END3", + "ER1END3" + ], + [ + "T_TERM_UTURN_INT_SS2A3", + "SS2A3" + ], + [ + "T_TERM_UTURN_INT_SE6E3", + "NE6D0" + ], + [ + "T_TERM_UTURN_INT_SW6D3", + "NW6C0" + ], + [ + "T_TERM_UTURN_INT_SS6C2", + "SS6C2" + ], + [ + "T_TERM_INT_UTURN_LV_R3", + "LV14" + ], + [ + "T_TERM_UTURN_INT_SS6B3", + "SS6B3" + ], + [ + "T_TERM_INT_UTURN_LV_R4", + "LV13" + ], + [ + "T_TERM_INT_UTURN_LV_R4", + "LV4" + ], + [ + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", + "BYP_BOUNCE3" + ], + [ + "T_TERM_UTURN_INT_LVB4", + "LVB7" + ], + [ + "T_TERM_UTURN_INT_SS6C1", + "SS6C1" + ], + [ + "T_TERM_UTURN_INT_SE6B2", + "SE6B2" + ], + [ + "T_TERM_UTURN_INT_SE2A0", + "NE2BEG3" + ], + [ + "T_TERM_UTURN_INT_SS6E1", + "NN6D2" + ], + [ + "T_TERM_UTURN_INT_SE2A3", + "NE2BEG0" + ], + [ + "T_TERM_UTURN_INT_SE6B3", + "NE6A0" + ], + [ + "T_TERM_UTURN_INT_SS6END1", + "SS6END1" + ], + [ + "T_TERM_UTURN_INT_SS2A1", + "NN2BEG2" + ], + [ + "T_TERM_UTURN_INT_SE2A3", + "SE2A3" + ], + [ + "T_TERM_UTURN_INT_SW6C3", + "NW6B0" + ], + [ + "T_TERM_UTURN_INT_SS6E2", + "NN6D1" + ], + [ + "T_TERM_UTURN_INT_SW6E1", + "NW6D2" + ], + [ + "T_TERM_UTURN_INT_ER1BEG_S0", + "EL1BEG3" + ], + [ + "T_TERM_INT_UTURN_LV_R9", + "LV9" + ], + [ + "T_TERM_INT_UTURN_LV_R9", + "LV8" + ], + [ + "T_TERM_INT_UTURN_LV_R2", + "LV2" + ], + [ + "T_TERM_INT_UTURN_LV_R3", + "LV3" + ], + [ + "T_TERM_UTURN_INT_SW6E1", + "SW6E1" + ], + [ + "T_TERM_INT_UTURN_LV_R7", + "LV10" + ], + [ + "T_TERM_UTURN_INT_SS6C1", + "NN6B2" + ], + [ + "T_TERM_UTURN_INT_SS6C3", + "NN6B0" + ], + [ + "T_TERM_UTURN_INT_SS2END1", + "NN2A2" + ], + [ + "T_TERM_UTURN_INT_SW6B3", + "NW6A0" + ], + [ + "T_TERM_UTURN_INT_SE6D2", + "SE6D2" + ], + [ + "T_TERM_UTURN_INT_SL1END2_SLOW", + "NR1BEG1" + ], + [ + "T_TERM_UTURN_INT_SE6C0", + "SE6C0" + ], + [ + "T_TERM_UTURN_INT_SE2A1", + "SE2A1" + ], + [ + "T_TERM_UTURN_INT_SE6D3", + "NE6C0" + ], + [ + "T_TERM_UTURN_INT_SS6E1", + "SS6E1" + ], + [ + "T_TERM_UTURN_INT_SE6B1", + "SE6B1" + ], + [ + "T_TERM_UTURN_INT_SE6E2", + "SE6E2" + ], + [ + "T_TERM_INT_UTURN_LV_R2", + "LV15" + ], + [ + "T_TERM_UTURN_INT_SW6B0", + "SW6B0" + ], + [ + "T_TERM_UTURN_INT_SS2A2", + "SS2A2" + ], + [ + "T_TERM_UTURN_INT_SS2END2", + "NN2A1" + ], + [ + "T_TERM_UTURN_INT_SS6D2", + "SS6D2" + ], + [ + "T_TERM_UTURN_INT_SR1END2_SLOW", + "SR1END2" + ], + [ + "T_TERM_UTURN_INT_SE6C2", + "SE6C2" + ], + [ + "T_TERM_UTURN_INT_WR1END_S1_0", + "WR1END_S1_0" + ], + [ + "T_TERM_UTURN_INT_SS6D1", + "NN6C2" + ], + [ + "T_TERM_UTURN_INT_SE6C0", + "NE6B3" + ], + [ + "T_TERM_UTURN_INT_SE6C1", + "SE6C1" + ], + [ + "T_TERM_UTURN_INT_SW6D2", + "NW6C1" + ], + [ + "T_TERM_UTURN_INT_SE6E2", + "NE6D1" + ], + [ + "T_TERM_UTURN_INT_WR1BEG_S0", + "WR1BEG_S0" + ], + [ + "T_TERM_UTURN_INT_SS6A3", + "SS6A3" + ], + [ + "T_TERM_UTURN_INT_SS2A0", + "SS2A0" + ], + [ + "T_TERM_UTURN_INT_SR1END3_SLOW", + "SR1END3" + ], + [ + "T_TERM_UTURN_INT_LVB2", + "LVB9" + ], + [ + "T_TERM_UTURN_INT_SW6D0", + "SW6D0" + ], + [ + "T_TERM_UTURN_INT_SR1END2_SLOW", + "NL1BEG1" + ], + [ + "T_TERM_UTURN_INT_SL1END2_SLOW", + "SL1END2" + ], + [ + "T_TERM_UTURN_INT_SE6E1", + "NE6D2" + ], + [ + "T_TERM_UTURN_INT_SS6END2", + "NN6E1" + ], + [ + "T_TERM_INT_UTURN_LV_R6", + "LV11" + ], + [ + "T_TERM_UTURN_INT_SE6E3", + "SE6E3" + ], + [ + "T_TERM_UTURN_INT_SS6D0", + "NN6C3" + ], + [ + "T_TERM_UTURN_INT_SS2END1", + "SS2END1" + ], + [ + "T_TERM_UTURN_INT_SS6END0", + "SS6END0" + ], + [ + "T_TERM_UTURN_INT_SW6C1", + "SW6C1" + ], + [ + "T_TERM_UTURN_INT_SW6B3", + "SW6B3" + ], + [ + "T_TERM_UTURN_INT_SE6D0", + "SE6D0" + ], + [ + "T_TERM_UTURN_INT_SW2A0", + "SW2A0" + ], + [ + "T_TERM_UTURN_INT_SW2A1", + "NW2BEG2" + ], + [ + "T_TERM_UTURN_INT_SS6E2", + "SS6E2" + ], + [ + "T_TERM_UTURN_INT_SW6C2", + "NW6B1" + ], + [ + "T_TERM_UTURN_INT_SL1END3_SLOW", + "SL1END3" + ], + [ + "T_TERM_UTURN_INT_SW6B2", + "SW6B2" + ], + [ + "T_TERM_INT_UTURN_LV_R16", + "LV1" + ], + [ + "T_TERM_UTURN_INT_SE6D3", + "SE6D3" + ], + [ + "T_TERM_UTURN_INT_SE6E1", + "SE6E1" + ], + [ + "T_TERM_UTURN_INT_SS2A1", + "SS2A1" + ], + [ + "T_TERM_UTURN_INT_LVB3", + "LVB8" + ] + ], + "tile_types": [ + "BRKH_TERM_INT", + "INT_R" + ] + }, + { + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "GTXE2_BYP3_1", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX31_1", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX35_1", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX17_1", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX28_1", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_FAN7_1", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX21_1", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_FAN6_1", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX12_1", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B18_1", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX40_1", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B14_1", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX8_1", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX0_1", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX6_1", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX44_1", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_FAN3_1", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX7_1", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX37_1", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_BYP6_1", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX10_1", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX20_1", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN1_1", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_1", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B6_1", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_FAN2_1", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX41_1", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B13_1", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_CLK0_1", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX5_1", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX24_1", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_CLK1_1", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_CTRL0_1", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_CTRL1_1", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX9_1", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_LOGIC_OUTS_B16_1", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX34_1", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_LOGIC_OUTS_B3_1", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX45_1", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX43_1", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX19_1", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_LOGIC_OUTS_B4_1", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B1_1", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX29_1", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_BYP1_1", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX15_1", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_LOGIC_OUTS_B15_1", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX39_1", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B17_1", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX27_1", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_LOGIC_OUTS_B10_1", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX47_1", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX46_1", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX36_1", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_LOGIC_OUTS_B2_1", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_FAN5_1", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_BYP0_1", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_FAN4_1", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_BYP5_1", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX3_1", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX22_1", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX38_1", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_LOGIC_OUTS_B0_1", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_LOGIC_OUTS_B5_1", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX30_1", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_BYP4_1", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX42_1", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX13_1", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_BYP7_1", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX25_1", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B9_1", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX18_1", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_LOGIC_OUTS_B7_1", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_IMUX32_1", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN0_1", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_LOGIC_OUTS_B22_1", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B20_1", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_LOGIC_OUTS_B11_1", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_LOGIC_OUTS_B8_1", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_BYP2_1", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX26_1", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX33_1", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX2_1", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX11_1", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX16_1", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX4_1", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX23_1", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX14_1", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX1_1", + "VBRK_EXT_IMUX1" + ] + ], + "tile_types": [ + "GTX_CHANNEL_2", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + -9 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE2BEG2_19", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_SW2A3_19", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_WW2A0_19", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_EE2A2_19", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WR1END2_19", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_ER1BEG2_19", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_SW4A0_19", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_LH2_19", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_NW4END0_19", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SW2A0_19", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_NW4A0_19", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_NE2A0_19", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_SW4A1_19", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_WL1END0_19", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_NE4BEG0_19", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_WW4END0_19", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WW4END2_19", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_EE4A2_19", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SW4A3_19", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_NE4C2_19", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE2A0_19", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_ER1BEG0_19", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_EL1BEG0_19", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_LH9_19", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NE4C1_19", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WW4A1_19", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EE4A1_19", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_WW4C0_19", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NE4C0_19", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_NW4END2_19", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_SE2A1_19", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_SE4BEG3_19", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG1_19", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_EE4B3_19", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_LH1_19", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_WW4A0_19", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_EE4BEG3_19", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_NE4BEG3_19", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_NE2A1_19", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_EE4BEG0_19", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE4BEG2_19", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_EE4C0_19", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_WW2A1_19", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_SW4END1_19", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_EL1BEG3_19", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WW4B0_19", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_SW2A1_19", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_WR1END0_19", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_NW4END1_19", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_WW4C3_19", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_EE2A3_19", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_LH6_19", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_SE4C2_19", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_EL1BEG2_19", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_EE2BEG3_19", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_SE2A0_19", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_LH4_19", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_ER1BEG1_19", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WW4END3_19", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_NW4A3_19", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_WW4B2_19", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_WW4END1_19", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EE2BEG1_19", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NW4A2_19", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_SE4BEG0_19", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_WW4B3_19", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_NE4C3_19", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_LH5_19", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_WW4A2_19", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_NE4BEG2_19", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_NW2A3_19", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_LH7_19", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_EE4B0_19", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WL1END2_19", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SE4C3_19", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_SE2A2_19", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_WW4A3_19", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_EE4C1_19", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_SW4A2_19", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_EE2A1_19", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_WR1END1_19", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SE4C0_19", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_WW4B1_19", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_WW2END3_19", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_EE4B2_19", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_NW2A0_19", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_SW4END0_19", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_LH8_19", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_SW4END3_19", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_SW2A2_19", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WW4C2_19", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_NE2A2_19", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_LH10_19", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_EE4A3_19", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_NE2A3_19", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_ER1BEG3_19", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WR1END3_19", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_SW4END2_19", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_WL1END1_19", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_NW2A1_19", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_LH11_19", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EE2BEG0_19", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4C1_19", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SE2A3_19", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_NW4END3_19", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW2END1_19", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE4BEG1_19", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_EE4C3_19", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW2END2_19", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_SE4BEG1_19", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_LH12_19", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW2A3_19", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_LH3_19", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SE4C1_19", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_EE4C2_19", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_EE4B1_19", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_NW2A2_19", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_WW2END0_19", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_WW2A2_19", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_NE4BEG1_19", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_NW4A1_19", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WL1END3_19", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_SE4BEG2_19", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_EE4A0_19", + "INT_FEEDTHRU_2_EE4A0" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CMT_PMV_NE4C0", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_PMV_BYP3", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_PMV_NW2A3", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_PMV_EE4B3", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_PMV_WW4B2", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_PMV_LH2", + "INT_INTERFACE_LH2" + ], + [ + "CMT_PMV_WW4C3", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_PMV_SE2A0", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_PMV_NE2A1", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_PMV_IMUX30", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_PMV_IMUX24", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_PMV_SW4A3", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_PMV_EE4BEG0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "L_TERM_INT_PHASER_TO_IO_OCLK", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_PMV_IMUX15", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_PMV_SW4END3", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_PMV_SW4A0", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_PMV_SE4C2", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_PMV_FAN5", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_PMV_FAN4", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_PMV_EE4B2", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_PMV_NW4END2", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_PMV_IMUX2", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_PMV_EE2A1", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_PMV_EE4BEG3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_PMV_SW4A2", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_PMV_WW2END2", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_PMV_SE2A1", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_PMV_WR1END0", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_PMV_EE4A1", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_PMV_NE4BEG1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "L_TERM_INT_PHASER_TO_IO_ICLK", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_PMV_IMUX27", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_PMV_IMUX28", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_PMV_EL1BEG1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_PMV_FAN3", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_PMV_SW2A3", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_PMV_IMUX44", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_PMV_IMUX0", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_PMV_IMUX8", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_PMV_SW4A1", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_PMV_FAN1", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_PMV_IMUX34", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_PMV_SW2A1", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_PMV_WW2END1", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_PMV_LOGIC_OUTS8", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "CMT_PMV_NE4BEG2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_PMV_WW2A0", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_PMV_EE4BEG2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_PMV_NE2A3", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_PMV_WW4B3", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_PMV_NE2A0", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_PMV_WW4B0", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_PMV_SE4C1", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_PMV_EE2A0", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_PMV_LOGIC_OUTS17", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "CMT_PMV_LOGIC_OUTS10", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CMT_PMV_IMUX22", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_PMV_CLK0", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_PMV_LOGIC_OUTS23", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "CMT_PMV_FAN6", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_PMV_IMUX16", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_PMV_IMUX20", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_PMV_BYP6", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_PMV_IMUX36", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_PMV_EE4B1", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_PMV_NW2A1", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_PMV_WW2A3", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_PMV_LOGIC_OUTS15", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "CMT_PMV_WW4C2", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_PMV_WR1END2", + "INT_INTERFACE_WR1END2" + ], + [ + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_PMV_IMUX43", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_PMV_NW4A1", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_PMV_WR1END3", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_PMV_IMUX35", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_PMV_LOGIC_OUTS19", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CMT_PMV_WL1END2", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_PMV_BYP0", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_PMV_EE4C2", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_PMV_IMUX23", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_PMV_EE2A2", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_PMV_SW2A0", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_PMV_BYP2", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_PMV_BYP4", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_PMV_SW4END0", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_PMV_IMUX18", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_PMV_WW2A2", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_PMV_IMUX41", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_PMV_SE2A2", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_PMV_IMUX13", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_PMV_LH3", + "INT_INTERFACE_LH3" + ], + [ + "CMT_PMV_SE4C3", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_PMV_BYP5", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_PMV_IMUX5", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_PMV_EE2A3", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_PMV_WW4A1", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_PMV_CTRL1", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_PMV_EE4C3", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_PMV_WW4A3", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_PMV_ER1BEG3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_PMV_LH11", + "INT_INTERFACE_LH11" + ], + [ + "CMT_PMV_IMUX1", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_PMV_LOGIC_OUTS13", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "CMT_PMV_IMUX10", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_PMV_IMUX14", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_PMV_LOGIC_OUTS7", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CMT_PMV_LOGIC_OUTS2", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CMT_PMV_SE4BEG1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_PMV_IMUX37", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_PMV_SE4BEG3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_PMV_IMUX31", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_PMV_LH12", + "INT_INTERFACE_LH12" + ], + [ + "CMT_PMV_LOGIC_OUTS0", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CMT_PMV_NW4END1", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_PMV_EL1BEG2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_PMV_NW4A2", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_PMV_IMUX40", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_PMV_EE2BEG2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_PMV_WW2A1", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_PMV_SW4END1", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_PMV_WW4END0", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_PMV_EE4C0", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_PMV_SE2A3", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_PMV_IMUX32", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_PMV_LH9", + "INT_INTERFACE_LH9" + ], + [ + "CMT_PMV_LOGIC_OUTS5", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CMT_PMV_WL1END0", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_PMV_WW4B1", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_PMV_IMUX29", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_PMV_WW4END3", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_PMV_EE4B0", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_PMV_IMUX39", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_PMV_SW4END2", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_PMV_IMUX17", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_PMV_WW2END3", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_PMV_EE4C1", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_PMV_BYP7", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_PMV_IMUX47", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_PMV_WL1END3", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_PMV_FAN2", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_PMV_ER1BEG1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_PMV_NW2A0", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_PMV_NW4A3", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_PMV_WW4A2", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_PMV_IMUX46", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_PMV_IMUX45", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_PMV_FAN0", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_PMV_LH10", + "INT_INTERFACE_LH10" + ], + [ + "CMT_PMV_WR1END1", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_PMV_WW2END0", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_PMV_LOGIC_OUTS21", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "CMT_PMV_LH7", + "INT_INTERFACE_LH7" + ], + [ + "CMT_PMV_EE2BEG1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_PMV_CTRL0", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_PMV_CLK1", + "INT_INTERFACE_CLK1" + ], + [ + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_PMV_IMUX19", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_PMV_SE4BEG0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_PMV_WW4C1", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_PMV_EE2BEG0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_PMV_WW4A0", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_PMV_NW2A2", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_PMV_NE2A2", + "INT_INTERFACE_NE2A2" + ], + [ + "CMT_PMV_EE4A3", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_PMV_NW4END3", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_PMV_IMUX6", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_PMV_EE4A2", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_PMV_NW4END0", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_PMV_NE4C1", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_PMV_NE4C3", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_PMV_IMUX21", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_PMV_IMUX7", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_PMV_LOGIC_OUTS18", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "CMT_PMV_LOGIC_OUTS22", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "CMT_PMV_EE2BEG3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_PMV_IMUX25", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_PMV_LH6", + "INT_INTERFACE_LH6" + ], + [ + "CMT_PMV_ER1BEG0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_PMV_EE4A0", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_PMV_LH8", + "INT_INTERFACE_LH8" + ], + [ + "CMT_PMV_LH4", + "INT_INTERFACE_LH4" + ], + [ + "CMT_PMV_IMUX3", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_PMV_ER1BEG2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_PMV_NE4BEG0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_PMV_EL1BEG3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_PMV_IMUX38", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_PMV_LOGIC_OUTS20", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "CMT_PMV_IMUX11", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_PMV_SE4BEG2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_PMV_WL1END1", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_PMV_IMUX26", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_PMV_FAN7", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_PMV_IMUX33", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_PMV_LH1", + "INT_INTERFACE_LH1" + ], + [ + "CMT_PMV_WW4END2", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_PMV_IMUX12", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_PMV_NE4C2", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_PMV_NE4BEG3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_PMV_SW2A2", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_PMV_IMUX42", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_PMV_LOGIC_OUTS16", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CMT_PMV_LH5", + "INT_INTERFACE_LH5" + ], + [ + "CMT_PMV_EE4BEG1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_PMV_SE4C0", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_PMV_WW4C0", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_PMV_WW4END1", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_PMV_IMUX9", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_PMV_EL1BEG0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_PMV_IMUX4", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_PMV_NW4A0", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_PMV_BYP1", + "INT_INTERFACE_BYP1" + ] + ], + "tile_types": [ + "CMT_PMV", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "CLK_PMV_IMUX25_0", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_PMV_IMUX14_0", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_PMV_LH2_0", + "INT_INTERFACE_LH2" + ], + [ + "CLK_PMV_IMUX6_0", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_PMV_IMUX46_0", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_PMV_SW4A1_0", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_PMV_IMUX34_0", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_PMV_LH12_0", + "INT_INTERFACE_LH12" + ], + [ + "CLK_PMV_IMUX7_0", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_PMV_IMUX28_0", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_PMV_IMUX11_0", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_PMV_WW4END0_0", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_PMV_IMUX8_0", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_PMV_IMUX37_0", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_PMV_IMUX19_0", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_PMV_SW4A0_0", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_PMV_NE4C1_0", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_PMV_ER1BEG0_0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_PMV_WW2A1_0", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_PMV_IMUX3_0", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_PMV_FAN0_0", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_PMV_WW4C2_0", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_PMV_IMUX10_0", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_PMV_WW4B3_0", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_PMV_NW2A0_0", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_PMV_SW4END2_0", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_PMV_EE2A3_0", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_PMV_IMUX45_0", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_PMV_ER1BEG2_0", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_PMV_NW4A1_0", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_PMV_SE4C2_0", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_PMV_IMUX18_0", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_PMV_WW4B2_0", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_PMV_NW4END0_0", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_PMV_WW4B1_0", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_PMV_BYP1_0", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_PMV_IMUX39_0", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_PMV_FAN7_0", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_PMV_IMUX17_0", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_PMV_SE4BEG1_0", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_PMV_EE2A1_0", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_PMV_IMUX29_0", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_PMV_EE2BEG1_0", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_PMV_SW2A1_0", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_PMV_WW4A1_0", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_PMV_WL1END0_0", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_PMV_SE4C3_0", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_PMV_WW4END2_0", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_PMV_NE4C2_0", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_PMV_SE4BEG2_0", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_PMV_IMUX35_0", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_PMV_LH9_0", + "INT_INTERFACE_LH9" + ], + [ + "CLK_PMV_WW4C3_0", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_PMV_SE4C1_0", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_PMV_BYP4_0", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_PMV_IMUX27_0", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_PMV_IMUX22_0", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_PMV_EE4BEG3_0", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_PMV_IMUX1_0", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_PMV_NE4BEG3_0", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_PMV_NW4A0_0", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_PMV_FAN5_0", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_PMV_IMUX40_0", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_PMV_EE4C1_0", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_PMV_WL1END3_0", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_PMV_EE2BEG0_0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_PMV_SW2A2_0", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_PMV_SW4A2_0", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_PMV_SE2A2_0", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_PMV_BYP2_0", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_PMV_EE4A0_0", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_PMV_EE4BEG1_0", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_PMV_IMUX38_0", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_PMV_NW4END3_0", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_PMV_BYP7_0", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_PMV_WW4B0_0", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_PMV_NE2A1_0", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_PMV_LH6_0", + "INT_INTERFACE_LH6" + ], + [ + "CLK_PMV_EE2BEG2_0", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_PMV_BYP5_0", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_PMV_NE4BEG2_0", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_PMV_NW4A2_0", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_PMV_EE2A2_0", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_PMV_IMUX21_0", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_PMV_EE4A2_0", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_PMV_LH1_0", + "INT_INTERFACE_LH1" + ], + [ + "CLK_PMV_IMUX26_0", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_PMV_MONITOR_N_0", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_PMV_BYP6_0", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_PMV_NE2A2_0", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_PMV_EE4B2_0", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_PMV_WR1END1_0", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_PMV_NW2A3_0", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_PMV_IMUX43_0", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_PMV_SW2A0_0", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_PMV_CTRL0_0", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_PMV_SE4BEG3_0", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_PMV_NE2A3_0", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_PMV_WW4END1_0", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_PMV_EE4C2_0", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_PMV_NW2A2_0", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_PMV_FAN1_0", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_PMV_EE4C0_0", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_PMV_IMUX0_0", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_PMV_IMUX9_0", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_PMV_BYP3_0", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_PMV_NE2A0_0", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_PMV_WW4C0_0", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_PMV_IMUX30_0", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_PMV_EL1BEG1_0", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_PMV_LH3_0", + "INT_INTERFACE_LH3" + ], + [ + "CLK_PMV_EL1BEG3_0", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_PMV_EL1BEG2_0", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_PMV_WW4A3_0", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_PMV_SE2A1_0", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_PMV_NE4BEG1_0", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_PMV_WW2END0_0", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_PMV_SE4C0_0", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_PMV_WW2END1_0", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_PMV_EE4B3_0", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_PMV_EE4C3_0", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_PMV_LH11_0", + "INT_INTERFACE_LH11" + ], + [ + "CLK_PMV_WR1END0_0", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_PMV_NW2A1_0", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_PMV_IMUX23_0", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_PMV_LH8_0", + "INT_INTERFACE_LH8" + ], + [ + "CLK_PMV_EE2A0_0", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_PMV_SE2A0_0", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_PMV_IMUX31_0", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_PMV_SW4A3_0", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_PMV_NW4A3_0", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_PMV_WW2A3_0", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_PMV_IMUX20_0", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_PMV_IMUX47_0", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_PMV_IMUX24_0", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_PMV_FAN3_0", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_PMV_EE4A3_0", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_PMV_SW4END1_0", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_PMV_WW4A0_0", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_PMV_NW4END2_0", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_PMV_IMUX15_0", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_PMV_IMUX41_0", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_PMV_WL1END2_0", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_PMV_EE4A1_0", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_PMV_WW4END3_0", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_PMV_MONITOR_P_0", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_PMV_EE2BEG3_0", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_PMV_EE4B0_0", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_PMV_CLK0_0", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_PMV_FAN2_0", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_PMV_LH5_0", + "INT_INTERFACE_LH5" + ], + [ + "CLK_PMV_FAN4_0", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_PMV_IMUX13_0", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_PMV_NE4BEG0_0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_PMV_CLK1_0", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_PMV_WW2END3_0", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_PMV_EE4B1_0", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_PMV_IMUX2_0", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_PMV_FAN6_0", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_PMV_SE4BEG0_0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_PMV_SW4END0_0", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_PMV_IMUX12_0", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_PMV_WW2A2_0", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_PMV_IMUX5_0", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_PMV_IMUX32_0", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_PMV_LH4_0", + "INT_INTERFACE_LH4" + ], + [ + "CLK_PMV_IMUX42_0", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_PMV_EE4BEG2_0", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_PMV_WW4A2_0", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_PMV_ER1BEG3_0", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_PMV_NE4C0_0", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_PMV_CTRL1_0", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_PMV_LH10_0", + "INT_INTERFACE_LH10" + ], + [ + "CLK_PMV_IMUX36_0", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_PMV_IMUX16_0", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_PMV_BYP0_0", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_PMV_WR1END2_0", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_PMV_NW4END1_0", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_PMV_WR1END3_0", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_PMV_SW4END3_0", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_PMV_SW2A3_0", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_PMV_EE4BEG0_0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_PMV_WL1END1_0", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_PMV_SE2A3_0", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_PMV_IMUX33_0", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_PMV_WW2A0_0", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_PMV_IMUX44_0", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_PMV_WW4C1_0", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_PMV_NE4C3_0", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_PMV_WW2END2_0", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_PMV_EL1BEG0_0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_PMV_ER1BEG1_0", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_PMV_LH7_0", + "INT_INTERFACE_LH7" + ], + [ + "CLK_PMV_IMUX4_0", + "INT_INTERFACE_IMUX4" + ] + ], + "tile_types": [ + "CLK_PMV", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 3 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW4C0_7", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_WL1END1_7", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_WW4A0_7", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_NW4A3_7", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_NW4END2_7", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_SW4END0_7", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_EE4C0_7", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EL1BEG1_7", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_NE4BEG0_7", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_SW4A2_7", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_NW4A2_7", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_SW2A3_7", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_WW4C3_7", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_NE4C0_7", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_LH6_7", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_EE4B3_7", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SE4C0_7", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_NW2A0_7", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_EE4C2_7", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_NW2A2_7", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_EE4B1_7", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EE2A2_7", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_NE4BEG3_7", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_LH9_7", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_LH8_7", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_LH2_7", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_EL1BEG0_7", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_WW2A3_7", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_SW2A2_7", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WW2END2_7", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_NW4A1_7", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_EE2BEG0_7", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_SE4BEG2_7", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_NW4END1_7", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_WW4END3_7", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_SW4END1_7", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_WW4END1_7", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_EL1BEG3_7", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_WL1END2_7", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_SE2A1_7", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW4END0_7", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_WW4B1_7", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_EE4BEG0_7", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE4C1_7", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_ER1BEG0_7", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_WL1END0_7", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SW2A0_7", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_EE4B0_7", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_WW4A1_7", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EE4C3_7", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_WW4C1_7", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SE4BEG1_7", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_NW2A1_7", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_SE2A3_7", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_EE2A3_7", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_EE4A1_7", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_NE2A2_7", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_WR1END1_7", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SW4A3_7", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_EE4A3_7", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_SW4A0_7", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_WR1END3_7", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_LH1_7", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_NE2A3_7", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_LH4_7", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_WW2A2_7", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_SE2A2_7", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_WW4C2_7", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_LH5_7", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_NE4BEG1_7", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_ER1BEG3_7", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_WW4B0_7", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_SW4END3_7", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_NE2A0_7", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_EE2A1_7", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_NE4C1_7", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_SE4C1_7", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_NE4BEG2_7", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG2_7", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_WW2END0_7", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_LH10_7", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_WL1END3_7", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_LH11_7", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_LH3_7", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_SE2A0_7", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE4A2_7", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4A0_7", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE2BEG1_7", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_EE2A0_7", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_NW4A0_7", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_WW4A3_7", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_NW2A3_7", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NW4END0_7", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_SE4BEG0_7", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_ER1BEG2_7", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_SE4C2_7", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_ER1BEG1_7", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_WR1END0_7", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_EE4BEG1_7", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_EE2BEG3_7", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_EE4BEG3_7", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_WW4END2_7", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_SW4A1_7", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_SE4BEG3_7", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_EE4B2_7", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_LH7_7", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WW4A2_7", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WW4B2_7", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_NE4C2_7", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_WW2A0_7", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_NE4C3_7", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_WW2END3_7", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_WW4B3_7", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_SW4END2_7", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SE4C3_7", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_NW4END3_7", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_EE4BEG2_7", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_LH12_7", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_WW2END1_7", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_EE2BEG2_7", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW2A1_7", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_NE2A1_7", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_SW2A1_7", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_WR1END2_7", + "INT_FEEDTHRU_2_WR1END2" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_SW4END3", + "R_TERM_INT_SW4END3" + ], + [ + "INT_INTERFACE_NW4END1", + "R_TERM_INT_NW4END1" + ], + [ + "INT_INTERFACE_WW4A0", + "R_TERM_INT_WW4A0" + ], + [ + "INT_INTERFACE_EE4BEG3", + "R_TERM_INT_WW4A3" + ], + [ + "INT_INTERFACE_NW2A1", + "R_TERM_INT_NW2A1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT16", + "R_TERM_INT_GTX_IMUX16" + ], + [ + "INT_INTERFACE_WW4END1", + "R_TERM_INT_WW4END1" + ], + [ + "INT_INTERFACE_WW2END3", + "R_TERM_INT_WW2END3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT13", + "R_TERM_INT_GTX_IMUX13" + ], + [ + "INT_INTERFACE_WW4B2", + "R_TERM_INT_WW4B2" + ], + [ + "INT_INTERFACE_SE4C1", + "R_TERM_INT_SW4END1" + ], + [ + "INT_INTERFACE_EE4A2", + "R_TERM_INT_WW4B2" + ], + [ + "INT_INTERFACE_EE4C2", + "R_TERM_INT_WW4END2" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT46", + "R_TERM_INT_GTX_IMUX46" + ], + [ + "INT_INTERFACE_WW4B1", + "R_TERM_INT_WW4B1" + ], + [ + "INT_INTERFACE_NW4A3", + "R_TERM_INT_NW4A3" + ], + [ + "INT_INTERFACE_LH11", + "R_TERM_INT_LH1" + ], + [ + "INT_INTERFACE_SW2A1", + "R_TERM_INT_SW2A1" + ], + [ + "INT_INTERFACE_LH3", + "R_TERM_INT_LH2" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT7", + "R_TERM_INT_GTX_IMUX7" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT24", + "R_TERM_INT_GTX_IMUX24" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT29", + "R_TERM_INT_GTX_IMUX29" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT21", + "R_TERM_INT_GTX_IMUX21" + ], + [ + "INT_INTERFACE_WW4C2", + "R_TERM_INT_WW4C2" + ], + [ + "INT_INTERFACE_NE4C1", + "R_TERM_INT_NW4END1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B12", + "R_TERM_INT_GTX_LOGIC_OUTS_B12" + ], + [ + "INT_INTERFACE_SW4END1", + "R_TERM_INT_SW4END1" + ], + [ + "INT_INTERFACE_SE4BEG1", + "R_TERM_INT_SW4A1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT27", + "R_TERM_INT_GTX_IMUX27" + ], + [ + "INT_INTERFACE_FAN1", + "R_TERM_INT_GTX_FAN1" + ], + [ + "INT_INTERFACE_WW4A2", + "R_TERM_INT_WW4A2" + ], + [ + "INT_INTERFACE_SW4A2", + "R_TERM_INT_SW4A2" + ], + [ + "INT_INTERFACE_SE2A2", + "R_TERM_INT_SW2A2" + ], + [ + "INT_INTERFACE_SE4BEG3", + "R_TERM_INT_SW4A3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B13", + "R_TERM_INT_GTX_LOGIC_OUTS_B13" + ], + [ + "INT_INTERFACE_WR1END1", + "R_TERM_INT_WR1END1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT39", + "R_TERM_INT_GTX_IMUX39" + ], + [ + "INT_INTERFACE_FAN0", + "R_TERM_INT_GTX_FAN0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT32", + "R_TERM_INT_GTX_IMUX32" + ], + [ + "INT_INTERFACE_EE4A0", + "R_TERM_INT_WW4B0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT34", + "R_TERM_INT_GTX_IMUX34" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B8", + "R_TERM_INT_GTX_LOGIC_OUTS_B8" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B23", + "R_TERM_INT_GTX_LOGIC_OUTS_B23" + ], + [ + "INT_INTERFACE_BYP0", + "R_TERM_INT_GTX_BYP0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B6", + "R_TERM_INT_GTX_LOGIC_OUTS_B6" + ], + [ + "INT_INTERFACE_EE2BEG0", + "R_TERM_INT_WW2A0" + ], + [ + "INT_INTERFACE_ER1BEG0", + "R_TERM_INT_WR1END0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT5", + "R_TERM_INT_GTX_IMUX5" + ], + [ + "INT_INTERFACE_WW2A1", + "R_TERM_INT_WW2A1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT15", + "R_TERM_INT_GTX_IMUX15" + ], + [ + "INT_INTERFACE_EE2A3", + "R_TERM_INT_WW2END3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT22", + "R_TERM_INT_GTX_IMUX22" + ], + [ + "INT_INTERFACE_WW4END2", + "R_TERM_INT_WW4END2" + ], + [ + "INT_INTERFACE_SE4BEG2", + "R_TERM_INT_SW4A2" + ], + [ + "INT_INTERFACE_BYP6", + "R_TERM_INT_GTX_BYP6" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT30", + "R_TERM_INT_GTX_IMUX30" + ], + [ + "INT_INTERFACE_EL1BEG3", + "R_TERM_INT_WL1END3" + ], + [ + "INT_INTERFACE_WL1END2", + "R_TERM_INT_WL1END2" + ], + [ + "INT_INTERFACE_NW2A3", + "R_TERM_INT_NW2A3" + ], + [ + "INT_INTERFACE_EE4B0", + "R_TERM_INT_WW4C0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT23", + "R_TERM_INT_GTX_IMUX23" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B21", + "R_TERM_INT_GTX_LOGIC_OUTS_B21" + ], + [ + "INT_INTERFACE_SW2A2", + "R_TERM_INT_SW2A2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B2", + "R_TERM_INT_GTX_LOGIC_OUTS_B2" + ], + [ + "INT_INTERFACE_EE4BEG1", + "R_TERM_INT_WW4A1" + ], + [ + "INT_INTERFACE_NE4BEG1", + "R_TERM_INT_NW4A1" + ], + [ + "INT_INTERFACE_EE4B1", + "R_TERM_INT_WW4C1" + ], + [ + "INT_INTERFACE_FAN2", + "R_TERM_INT_GTX_FAN2" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT38", + "R_TERM_INT_GTX_IMUX38" + ], + [ + "INT_INTERFACE_ER1BEG1", + "R_TERM_INT_WR1END1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT9", + "R_TERM_INT_GTX_IMUX9" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT11", + "R_TERM_INT_GTX_IMUX11" + ], + [ + "INT_INTERFACE_NE4C2", + "R_TERM_INT_NW4END2" + ], + [ + "INT_INTERFACE_WR1END3", + "R_TERM_INT_WR1END3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT17", + "R_TERM_INT_GTX_IMUX17" + ], + [ + "INT_INTERFACE_SW2A0", + "R_TERM_INT_SW2A0" + ], + [ + "INT_INTERFACE_NE4BEG0", + "R_TERM_INT_NW4A0" + ], + [ + "INT_INTERFACE_CTRL0", + "R_TERM_INT_GTX_CTRL0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B17", + "R_TERM_INT_GTX_LOGIC_OUTS_B17" + ], + [ + "INT_INTERFACE_WW4END0", + "R_TERM_INT_WW4END0" + ], + [ + "INT_INTERFACE_SE4BEG0", + "R_TERM_INT_SW4A0" + ], + [ + "INT_INTERFACE_EE4BEG2", + "R_TERM_INT_WW4A2" + ], + [ + "INT_INTERFACE_WW4A1", + "R_TERM_INT_WW4A1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT8", + "R_TERM_INT_GTX_IMUX8" + ], + [ + "INT_INTERFACE_NW4END0", + "R_TERM_INT_NW4END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B16", + "R_TERM_INT_GTX_LOGIC_OUTS_B16" + ], + [ + "INT_INTERFACE_NE4BEG3", + "R_TERM_INT_NW4A3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT1", + "R_TERM_INT_GTX_IMUX1" + ], + [ + "INT_INTERFACE_EE2BEG3", + "R_TERM_INT_WW2A3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT28", + "R_TERM_INT_GTX_IMUX28" + ], + [ + "INT_INTERFACE_NW4A0", + "R_TERM_INT_NW4A0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT18", + "R_TERM_INT_GTX_IMUX18" + ], + [ + "INT_INTERFACE_SW4END0", + "R_TERM_INT_SW4END0" + ], + [ + "INT_INTERFACE_WW4C0", + "R_TERM_INT_WW4C0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT14", + "R_TERM_INT_GTX_IMUX14" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT2", + "R_TERM_INT_GTX_IMUX2" + ], + [ + "INT_INTERFACE_WR1END2", + "R_TERM_INT_WR1END2" + ], + [ + "INT_INTERFACE_SW4A0", + "R_TERM_INT_SW4A0" + ], + [ + "INT_INTERFACE_BYP7", + "R_TERM_INT_GTX_BYP7" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT44", + "R_TERM_INT_GTX_IMUX44" + ], + [ + "INT_INTERFACE_SW4A3", + "R_TERM_INT_SW4A3" + ], + [ + "INT_INTERFACE_WW2END1", + "R_TERM_INT_WW2END1" + ], + [ + "INT_INTERFACE_NW4END3", + "R_TERM_INT_NW4END3" + ], + [ + "INT_INTERFACE_NE2A3", + "R_TERM_INT_NW2A3" + ], + [ + "INT_INTERFACE_NE2A1", + "R_TERM_INT_NW2A1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT3", + "R_TERM_INT_GTX_IMUX3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT12", + "R_TERM_INT_GTX_IMUX12" + ], + [ + "INT_INTERFACE_SW2A3", + "R_TERM_INT_SW2A3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT42", + "R_TERM_INT_GTX_IMUX42" + ], + [ + "INT_INTERFACE_BYP4", + "R_TERM_INT_GTX_BYP4" + ], + [ + "INT_INTERFACE_FAN3", + "R_TERM_INT_GTX_FAN3" + ], + [ + "INT_INTERFACE_EE2A2", + "R_TERM_INT_WW2END2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B5", + "R_TERM_INT_GTX_LOGIC_OUTS_B5" + ], + [ + "INT_INTERFACE_WW4C1", + "R_TERM_INT_WW4C1" + ], + [ + "INT_INTERFACE_LH10", + "R_TERM_INT_LH2" + ], + [ + "INT_INTERFACE_EE4C3", + "R_TERM_INT_WW4END3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT26", + "R_TERM_INT_GTX_IMUX26" + ], + [ + "INT_INTERFACE_WL1END1", + "R_TERM_INT_WL1END1" + ], + [ + "INT_INTERFACE_WW2A3", + "R_TERM_INT_WW2A3" + ], + [ + "INT_INTERFACE_EE2A0", + "R_TERM_INT_WW2END0" + ], + [ + "INT_INTERFACE_WL1END3", + "R_TERM_INT_WL1END3" + ], + [ + "INT_INTERFACE_SW4END2", + "R_TERM_INT_SW4END2" + ], + [ + "INT_INTERFACE_CLK0", + "R_TERM_INT_GTX_CLK0" + ], + [ + "INT_INTERFACE_WW2END2", + "R_TERM_INT_WW2END2" + ], + [ + "INT_INTERFACE_NE4BEG2", + "R_TERM_INT_NW4A2" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT19", + "R_TERM_INT_GTX_IMUX19" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT36", + "R_TERM_INT_GTX_IMUX36" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B20", + "R_TERM_INT_GTX_LOGIC_OUTS_B20" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT35", + "R_TERM_INT_GTX_IMUX35" + ], + [ + "INT_INTERFACE_WW2A0", + "R_TERM_INT_WW2A0" + ], + [ + "INT_INTERFACE_NE4C0", + "R_TERM_INT_NW4END0" + ], + [ + "INT_INTERFACE_NW4A1", + "R_TERM_INT_NW4A1" + ], + [ + "INT_INTERFACE_NE4C3", + "R_TERM_INT_NW4END3" + ], + [ + "INT_INTERFACE_EE4C0", + "R_TERM_INT_WW4END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B11", + "R_TERM_INT_GTX_LOGIC_OUTS_B11" + ], + [ + "INT_INTERFACE_EE4C1", + "R_TERM_INT_WW4END1" + ], + [ + "INT_INTERFACE_EL1BEG0", + "R_TERM_INT_WL1END0" + ], + [ + "INT_INTERFACE_BYP3", + "R_TERM_INT_GTX_BYP3" + ], + [ + "INT_INTERFACE_WW2A2", + "R_TERM_INT_WW2A2" + ], + [ + "INT_INTERFACE_FAN5", + "R_TERM_INT_GTX_FAN5" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT37", + "R_TERM_INT_GTX_IMUX37" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B1", + "R_TERM_INT_GTX_LOGIC_OUTS_B1" + ], + [ + "INT_INTERFACE_NE2A2", + "R_TERM_INT_NW2A2" + ], + [ + "INT_INTERFACE_EE4A3", + "R_TERM_INT_WW4B3" + ], + [ + "INT_INTERFACE_FAN7", + "R_TERM_INT_GTX_FAN7" + ], + [ + "INT_INTERFACE_EE4A1", + "R_TERM_INT_WW4B1" + ], + [ + "INT_INTERFACE_WR1END0", + "R_TERM_INT_WR1END0" + ], + [ + "INT_INTERFACE_LH4", + "R_TERM_INT_LH3" + ], + [ + "INT_INTERFACE_FAN4", + "R_TERM_INT_GTX_FAN4" + ], + [ + "INT_INTERFACE_ER1BEG2", + "R_TERM_INT_WR1END2" + ], + [ + "INT_INTERFACE_CTRL1", + "R_TERM_INT_GTX_CTRL1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B18", + "R_TERM_INT_GTX_LOGIC_OUTS_B18" + ], + [ + "INT_INTERFACE_WL1END0", + "R_TERM_INT_WL1END0" + ], + [ + "INT_INTERFACE_FAN6", + "R_TERM_INT_GTX_FAN6" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT4", + "R_TERM_INT_GTX_IMUX4" + ], + [ + "INT_INTERFACE_EE4BEG0", + "R_TERM_INT_WW4A0" + ], + [ + "INT_INTERFACE_NW4END2", + "R_TERM_INT_NW4END2" + ], + [ + "INT_INTERFACE_WW4B3", + "R_TERM_INT_WW4B3" + ], + [ + "INT_INTERFACE_EE2A1", + "R_TERM_INT_WW2END1" + ], + [ + "INT_INTERFACE_WW4C3", + "R_TERM_INT_WW4C3" + ], + [ + "INT_INTERFACE_EE2BEG1", + "R_TERM_INT_WW2A1" + ], + [ + "INT_INTERFACE_NW4A2", + "R_TERM_INT_NW4A2" + ], + [ + "INT_INTERFACE_SE4C0", + "R_TERM_INT_SW4END0" + ], + [ + "INT_INTERFACE_WW2END0", + "R_TERM_INT_WW2END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B22", + "R_TERM_INT_GTX_LOGIC_OUTS_B22" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT10", + "R_TERM_INT_GTX_IMUX10" + ], + [ + "INT_INTERFACE_SE2A1", + "R_TERM_INT_SW2A1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT20", + "R_TERM_INT_GTX_IMUX20" + ], + [ + "INT_INTERFACE_EE2BEG2", + "R_TERM_INT_WW2A2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B15", + "R_TERM_INT_GTX_LOGIC_OUTS_B15" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT43", + "R_TERM_INT_GTX_IMUX43" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT31", + "R_TERM_INT_GTX_IMUX31" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B10", + "R_TERM_INT_GTX_LOGIC_OUTS_B10" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B3", + "R_TERM_INT_GTX_LOGIC_OUTS_B3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B4", + "R_TERM_INT_GTX_LOGIC_OUTS_B4" + ], + [ + "INT_INTERFACE_LH8", + "R_TERM_INT_LH4" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT33", + "R_TERM_INT_GTX_IMUX33" + ], + [ + "INT_INTERFACE_BYP2", + "R_TERM_INT_GTX_BYP2" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT41", + "R_TERM_INT_GTX_IMUX41" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B14", + "R_TERM_INT_GTX_LOGIC_OUTS_B14" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT45", + "R_TERM_INT_GTX_IMUX45" + ], + [ + "INT_INTERFACE_LH6", + "R_TERM_INT_LH5" + ], + [ + "INT_INTERFACE_LH2", + "R_TERM_INT_LH1" + ], + [ + "INT_INTERFACE_NW2A0", + "R_TERM_INT_NW2A0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B0", + "R_TERM_INT_GTX_LOGIC_OUTS_B0" + ], + [ + "INT_INTERFACE_WW4END3", + "R_TERM_INT_WW4END3" + ], + [ + "INT_INTERFACE_EL1BEG2", + "R_TERM_INT_WL1END2" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT25", + "R_TERM_INT_GTX_IMUX25" + ], + [ + "INT_INTERFACE_EE4B3", + "R_TERM_INT_WW4C3" + ], + [ + "INT_INTERFACE_WW4B0", + "R_TERM_INT_WW4B0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT0", + "R_TERM_INT_GTX_IMUX0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT47", + "R_TERM_INT_GTX_IMUX47" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B19", + "R_TERM_INT_GTX_LOGIC_OUTS_B19" + ], + [ + "INT_INTERFACE_CLK1", + "R_TERM_INT_GTX_CLK1" + ], + [ + "INT_INTERFACE_SE2A3", + "R_TERM_INT_SW2A3" + ], + [ + "INT_INTERFACE_BYP1", + "R_TERM_INT_GTX_BYP1" + ], + [ + "INT_INTERFACE_EL1BEG1", + "R_TERM_INT_WL1END1" + ], + [ + "INT_INTERFACE_SW4A1", + "R_TERM_INT_SW4A1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT40", + "R_TERM_INT_GTX_IMUX40" + ], + [ + "INT_INTERFACE_SE4C2", + "R_TERM_INT_SW4END2" + ], + [ + "INT_INTERFACE_SE4C3", + "R_TERM_INT_SW4END3" + ], + [ + "INT_INTERFACE_LH9", + "R_TERM_INT_LH3" + ], + [ + "INT_INTERFACE_LH1", + "R_TERM_INT_LH0" + ], + [ + "INT_INTERFACE_LH7", + "R_TERM_INT_LH5" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B9", + "R_TERM_INT_GTX_LOGIC_OUTS_B9" + ], + [ + "INT_INTERFACE_EE4B2", + "R_TERM_INT_WW4C2" + ], + [ + "INT_INTERFACE_NE2A0", + "R_TERM_INT_NW2A0" + ], + [ + "INT_INTERFACE_SE2A0", + "R_TERM_INT_SW2A0" + ], + [ + "INT_INTERFACE_NW2A2", + "R_TERM_INT_NW2A2" + ], + [ + "INT_INTERFACE_BYP5", + "R_TERM_INT_GTX_BYP5" + ], + [ + "GTXE2_INT_INTERFACE_IMUX_OUT6", + "R_TERM_INT_GTX_IMUX6" + ], + [ + "INT_INTERFACE_WW4A3", + "R_TERM_INT_WW4A3" + ], + [ + "INT_INTERFACE_LH12", + "R_TERM_INT_LH0" + ], + [ + "INT_INTERFACE_ER1BEG3", + "R_TERM_INT_WR1END3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B7", + "R_TERM_INT_GTX_LOGIC_OUTS_B7" + ], + [ + "INT_INTERFACE_LH5", + "R_TERM_INT_LH4" + ] + ], + "tile_types": [ + "GTX_INT_INTERFACE", + "R_TERM_INT_GTX" + ] + }, + { + "grid_deltas": [ + -1, + 5 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX5_0", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_FAN1_0", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX11_0", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_FAN5_0", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_BYP5_0", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX6_0", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX0_0", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX40_0", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX23_0", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_CTRL0_0", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX25_0", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B17_0", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B10_0", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_BYP4_0", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX46_0", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX45_0", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_FAN2_0", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX42_0", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX39_0", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX7_0", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX4_0", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX3_0", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_BYP3_0", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_IMUX14_0", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX24_0", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_FAN3_0", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_FAN6_0", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_LOGIC_OUTS_B3_0", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_LOGIC_OUTS_B13_0", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B9_0", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX44_0", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX1_0", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX26_0", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX27_0", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX47_0", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_CLK1_0", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_LOGIC_OUTS_B7_0", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_FAN0_0", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX18_0", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX30_0", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_CTRL1_0", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX12_0", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B4_0", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_IMUX38_0", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX19_0", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_BYP2_0", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX22_0", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B5_0", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_FAN4_0", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX20_0", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_BYP7_0", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_BYP0_0", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX33_0", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX43_0", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_LOGIC_OUTS_B20_0", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX36_0", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_CLK0_0", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX13_0", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX21_0", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_LOGIC_OUTS_B6_0", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX35_0", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX41_0", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX28_0", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX10_0", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX9_0", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX32_0", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B16_0", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_BYP6_0", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX8_0", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX31_0", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_BYP1_0", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_IMUX15_0", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_LOGIC_OUTS_B19_0", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX17_0", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX37_0", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_LOGIC_OUTS_B1_0", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_FAN7_0", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B0_0", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX2_0", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX16_0", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX29_0", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX34_0", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_LOGIC_OUTS_B2_0", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_LOGIC_OUTS_B11_0", + "VBRK_EXT_LOGIC_OUTS_B11" + ] + ], + "tile_types": [ + "GTX_CHANNEL_1", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX27_5", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX13_5", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_LOGIC_OUTS_B4_5", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B22_5", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX30_5", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_LOGIC_OUTS_B14_5", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX0_5", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_BYP4_5", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX18_5", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_LOGIC_OUTS_B8_5", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX16_5", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX42_5", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX46_5", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX11_5", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX6_5", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B9_5", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX7_5", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX45_5", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_BYP0_5", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX38_5", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX33_5", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_LOGIC_OUTS_B11_5", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_BYP2_5", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX23_5", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_LOGIC_OUTS_B6_5", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_LOGIC_OUTS_B2_5", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX41_5", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B5_5", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX12_5", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX14_5", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX22_5", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_CLK0_5", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX43_5", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX37_5", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX9_5", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX29_5", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_BYP1_5", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_CTRL1_5", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_CLK1_5", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_CTRL0_5", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX28_5", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX32_5", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX17_5", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_FAN6_5", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_BYP5_5", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B7_5", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B17_5", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX1_5", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX26_5", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_FAN0_5", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX8_5", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_LOGIC_OUTS_B16_5", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX4_5", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_BYP7_5", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B3_5", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX39_5", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX35_5", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_LOGIC_OUTS_B18_5", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_LOGIC_OUTS_B12_5", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX19_5", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_FAN7_5", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B13_5", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B23_5", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_LOGIC_OUTS_B0_5", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX36_5", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX2_5", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX40_5", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_FAN3_5", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX3_5", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX10_5", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_FAN5_5", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX34_5", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX20_5", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN4_5", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX24_5", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B10_5", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_BYP3_5", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B15_5", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX31_5", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_FAN1_5", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_FAN2_5", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_LOGIC_OUTS_B20_5", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX5_5", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_BYP6_5", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX47_5", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX15_5", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX25_5", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX21_5", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX44_5", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_LOGIC_OUTS_B19_5", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B1_5", + "VBRK_EXT_LOGIC_OUTS_B1" + ] + ], + "tile_types": [ + "GTX_CHANNEL_2", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CFG_CENTER_SW4A3_11", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_SE4C3_11", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_BYP7_11", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_IMUX37_11", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_EE4BEG0_11", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_SE2A1_11", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_CTRL1_11", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_IMUX4_11", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX23_11", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_IMUX13_11", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_IMUX2_11", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_NW2A3_11", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NE2A1_11", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_LH7_11", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_WW2A0_11", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_IMUX30_11", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_IMUX39_11", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_IMUX27_11", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_SW2A2_11", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_IMUX3_11", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_CLK0_11", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX17_11", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_WL1END0_11", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_EE4B1_11", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_EE4A1_11", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_WW4C1_11", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_ER1BEG1_11", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SW2A1_11", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WW4B2_11", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_WW2END2_11", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_BYP5_11", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_WW4END2_11", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_IMUX20_11", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_ER1BEG2_11", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_SE4C0_11", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_IMUX32_11", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_SW4A2_11", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NW4END0_11", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX18_11", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_EL1BEG0_11", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_WL1END3_11", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_LH9_11", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_WL1END1_11", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_WW2END0_11", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_IMUX1_11", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_WW4END0_11", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_SW4END0_11", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_ER1BEG0_11", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_IMUX44_11", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_EE4A3_11", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_SE4C2_11", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_BYP6_11", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_IMUX31_11", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_CLK1_11", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX0_11", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_IMUX22_11", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_WR1END1_11", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NW4A3_11", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_EE4B2_11", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_NW4A1_11", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_BYP1_11", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW2A2_11", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_IMUX41_11", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_LH12_11", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX42_11", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_SE4BEG0_11", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_EE2BEG1_11", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_EE2A1_11", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_EE2BEG0_11", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_WL1END2_11", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WW4B3_11", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_IMUX29_11", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_WW4END3_11", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX43_11", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX21_11", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_EE4A2_11", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_EE4C1_11", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_EL1BEG2_11", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX36_11", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_EE4BEG3_11", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX33_11", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_NE4C2_11", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_FAN5_11", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_FAN0_11", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_SE2A3_11", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_WR1END0_11", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_SE4BEG3_11", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_LH6_11", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_NE2A0_11", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_SE2A0_11", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_NE4C3_11", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_BYP3_11", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_IMUX40_11", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_NW2A0_11", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_NE4BEG0_11", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX45_11", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_WW4B0_11", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_NE4C0_11", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE4B0_11", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_SW2A0_11", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_SE4BEG2_11", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE4C2_11", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_NW4A0_11", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_BYP0_11", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_WW4C0_11", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_EE2A3_11", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EL1BEG3_11", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_IMUX46_11", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_LH8_11", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_WW4C3_11", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX6_11", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_EE4A0_11", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_IMUX47_11", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_WW4A2_11", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_EE2A2_11", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_IMUX14_11", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_LH4_11", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_WW2A3_11", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_LH2_11", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX5_11", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_EE4B3_11", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_BYP2_11", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_FAN2_11", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_IMUX25_11", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_FAN6_11", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX10_11", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_SE2A2_11", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_EE4C0_11", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_EE4BEG2_11", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_WW2A1_11", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_LH11_11", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_SW4END2_11", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_NW4A2_11", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_BYP4_11", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_NW2A2_11", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_NE2A2_11", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE2BEG2_11", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_SW2A3_11", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_IMUX8_11", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_FAN3_11", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_IMUX24_11", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_WW2END3_11", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_IMUX28_11", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_LH5_11", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX16_11", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_FAN4_11", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_NE4C1_11", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_IMUX7_11", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_EE2BEG3_11", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX38_11", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_CTRL0_11", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_WW4END1_11", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_NW4END3_11", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_NW2A1_11", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_WR1END3_11", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_NE4BEG3_11", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NE4BEG1_11", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX35_11", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_NE2A3_11", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_EE4C3_11", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_WW4A3_11", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_SW4A0_11", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_NW4END2_11", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_FAN1_11", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_WW4A0_11", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_SW4END3_11", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX26_11", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_LH1_11", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_IMUX15_11", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_ER1BEG3_11", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_EE4BEG1_11", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_WW4A1_11", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_SE4BEG1_11", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE2A0_11", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_IMUX19_11", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_IMUX11_11", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_WW4C2_11", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX12_11", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_WW2END1_11", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_WW4B1_11", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_IMUX9_11", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_SW4A1_11", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_LH3_11", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_NE4BEG2_11", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_EL1BEG1_11", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_FAN7_11", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_LH10_11", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_NW4END1_11", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SW4END1_11", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_WR1END2_11", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SE4C1_11", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX34_11", + "VFRAME_IMUX34" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ] + ], + "tile_types": [ + "CLK_FEED", + "CLK_FEED" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_IMUX47_6", + "CMT_TOP_IMUX47_6" + ], + [ + "CMT_FIFO_L_IMUX45_6", + "CMT_TOP_IMUX45_6" + ], + [ + "CMT_FIFO_WW4B2_7", + "CMT_TOP_WW4B2_7" + ], + [ + "CMT_FIFO_SE4BEG3_3", + "CMT_TOP_SE4BEG3_3" + ], + [ + "CMT_FIFO_SW4END2_3", + "CMT_TOP_SW4END2_3" + ], + [ + "CMT_FIFO_L_BYP4_6", + "CMT_TOP_BYP4_6" + ], + [ + "CMT_FIFO_LH11_10", + "CMT_TOP_LH11_10" + ], + [ + "CMT_FIFO_L_IMUX22_4", + "CMT_TOP_IMUX22_4" + ], + [ + "CMT_FIFO_L_IMUX12_3", + "CMT_TOP_IMUX12_3" + ], + [ + "CMT_FIFO_SE2A3_1", + "CMT_TOP_SE2A3_1" + ], + [ + "CMT_FIFO_SW4A0_2", + "CMT_TOP_SW4A0_2" + ], + [ + "CMT_FIFO_LH3_2", + "CMT_TOP_LH3_2" + ], + [ + "CMT_FIFO_SW4END1_9", + "CMT_TOP_SW4END1_9" + ], + [ + "CMT_FIFO_L_IMUX8_9", + "CMT_TOP_IMUX8_9" + ], + [ + "CMT_FIFO_EE4A3_7", + "CMT_TOP_EE4A3_7" + ], + [ + "CMT_FIFO_SW4END3_11", + "CMT_TOP_SW4END3_11" + ], + [ + "CMT_FIFO_SE4C3_9", + "CMT_TOP_SE4C3_9" + ], + [ + "CMT_FIFO_NE4C0_10", + "CMT_TOP_NE4C0_10" + ], + [ + "CMT_FIFO_NE2A1_6", + "CMT_TOP_NE2A1_6" + ], + [ + "CMT_FIFO_WW2A0_8", + "CMT_TOP_WW2A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_1", + "CMT_TOP_LOGIC_OUTS_L_B23_1" + ], + [ + "CMT_FIFO_L_FAN3_4", + "CMT_TOP_FAN3_4" + ], + [ + "CMT_FIFO_NW4END3_6", + "CMT_TOP_NW4END3_6" + ], + [ + "CMT_FIFO_NW2A2_6", + "CMT_TOP_NW2A2_6" + ], + [ + "CMT_FIFO_SW4END1_8", + "CMT_TOP_SW4END1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_2", + "CMT_TOP_LOGIC_OUTS_L_B21_2" + ], + [ + "CMT_FIFO_WW2END1_5", + "CMT_TOP_WW2END1_5" + ], + [ + "CMT_FIFO_L_BYP6_2", + "CMT_TOP_BYP6_2" + ], + [ + "CMT_FIFO_NE4C0_8", + "CMT_TOP_NE4C0_8" + ], + [ + "CMT_FIFO_EE4A2_1", + "CMT_TOP_EE4A2_1" + ], + [ + "CMT_FIFO_EL1BEG0_9", + "CMT_TOP_EL1BEG0_9" + ], + [ + "CMT_FIFO_LH1_9", + "CMT_TOP_LH1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_10", + "CMT_TOP_LOGIC_OUTS_L_B21_10" + ], + [ + "CMT_FIFO_WL1END1_11", + "CMT_TOP_WL1END1_11" + ], + [ + "CMT_FIFO_WW4C0_9", + "CMT_TOP_WW4C0_9" + ], + [ + "CMT_FIFO_WW2A2_7", + "CMT_TOP_WW2A2_7" + ], + [ + "CMT_FIFO_NW2A0_6", + "CMT_TOP_NW2A0_6" + ], + [ + "CMT_FIFO_NW4END3_7", + "CMT_TOP_NW4END3_7" + ], + [ + "CMT_FIFO_NE2A3_10", + "CMT_TOP_NE2A3_10" + ], + [ + "CMT_FIFO_EE2A0_9", + "CMT_TOP_EE2A0_9" + ], + [ + "CMT_FIFO_ER1BEG0_11", + "CMT_TOP_ER1BEG0_11" + ], + [ + "CMT_FIFO_ER1BEG2_7", + "CMT_TOP_ER1BEG2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_4", + "CMT_TOP_LOGIC_OUTS_L_B17_4" + ], + [ + "CMT_FIFO_LH3_8", + "CMT_TOP_LH3_8" + ], + [ + "CMT_FIFO_L_FAN5_2", + "CMT_TOP_FAN5_2" + ], + [ + "CMT_FIFO_L_BYP7_0", + "CMT_TOP_BYP7_0" + ], + [ + "CMT_FIFO_L_IMUX43_10", + "CMT_TOP_IMUX43_10" + ], + [ + "CMT_FIFO_L_IMUX5_9", + "CMT_TOP_IMUX5_9" + ], + [ + "CMT_FIFO_WW4C3_8", + "CMT_TOP_WW4C3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_8", + "CMT_TOP_LOGIC_OUTS_L_B15_8" + ], + [ + "CMT_FIFO_WW2A3_11", + "CMT_TOP_WW2A3_11" + ], + [ + "CMT_FIFO_WW4A0_8", + "CMT_TOP_WW4A0_8" + ], + [ + "CMT_FIFO_WW4END1_0", + "CMT_TOP_WW4END1_0" + ], + [ + "CMT_FIFO_WW4END2_2", + "CMT_TOP_WW4END2_2" + ], + [ + "CMT_FIFO_WW4END3_4", + "CMT_TOP_WW4END3_4" + ], + [ + "CMT_FIFO_EE4BEG3_9", + "CMT_TOP_EE4BEG3_9" + ], + [ + "CMT_FIFO_SW4A1_3", + "CMT_TOP_SW4A1_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_4", + "CMT_TOP_LOGIC_OUTS_L_B9_4" + ], + [ + "CMT_FIFO_L_FAN6_1", + "CMT_TOP_FAN6_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_11", + "CMT_TOP_LOGIC_OUTS_L_B1_11" + ], + [ + "CMT_FIFO_L_IMUX14_1", + "CMT_TOP_IMUX14_1" + ], + [ + "CMT_FIFO_EL1BEG2_8", + "CMT_TOP_EL1BEG2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0" + ], + [ + "CMT_FIFO_SW4A2_5", + "CMT_TOP_SW4A2_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "CMT_TOP_ICLK_1" + ], + [ + "CMT_FIFO_L_BYP6_8", + "CMT_TOP_BYP6_8" + ], + [ + "CMT_FIFO_EE4BEG3_0", + "CMT_TOP_EE4BEG3_0" + ], + [ + "CMT_FIFO_L_CTRL0_2", + "CMT_TOP_CTRL0_2" + ], + [ + "CMT_FIFO_WL1END3_4", + "CMT_TOP_WL1END3_4" + ], + [ + "CMT_FIFO_L_IMUX9_7", + "CMT_TOP_IMUX9_7" + ], + [ + "CMT_FIFO_L_BYP6_1", + "CMT_TOP_BYP6_1" + ], + [ + "CMT_FIFO_L_IMUX18_2", + "CMT_TOP_IMUX18_2" + ], + [ + "CMT_FIFO_EL1BEG2_7", + "CMT_TOP_EL1BEG2_7" + ], + [ + "CMT_FIFO_L_IMUX16_5", + "CMT_TOP_IMUX16_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_1", + "CMT_TOP_LOGIC_OUTS_L_B11_1" + ], + [ + "CMT_FIFO_LH2_6", + "CMT_TOP_LH2_6" + ], + [ + "CMT_FIFO_NE4C1_2", + "CMT_TOP_NE4C1_2" + ], + [ + "CMT_FIFO_NE2A0_2", + "CMT_TOP_NE2A0_2" + ], + [ + "CMT_FIFO_SW4END3_9", + "CMT_TOP_SW4END3_9" + ], + [ + "CMT_FIFO_SW4A0_7", + "CMT_TOP_SW4A0_7" + ], + [ + "CMT_FIFO_ER1BEG2_10", + "CMT_TOP_ER1BEG2_10" + ], + [ + "CMT_FIFO_EL1BEG0_10", + "CMT_TOP_EL1BEG0_10" + ], + [ + "CMT_FIFO_WW4C1_9", + "CMT_TOP_WW4C1_9" + ], + [ + "CMT_FIFO_LH7_0", + "CMT_TOP_LH7_0" + ], + [ + "CMT_FIFO_WW2A0_9", + "CMT_TOP_WW2A0_9" + ], + [ + "CMT_FIFO_NE2A2_0", + "CMT_TOP_NE2A2_0" + ], + [ + "CMT_FIFO_L_IMUX0_5", + "CMT_TOP_IMUX0_5" + ], + [ + "CMT_FIFO_L_IMUX24_10", + "CMT_TOP_IMUX24_10" + ], + [ + "CMT_FIFO_ER1BEG3_3", + "CMT_TOP_ER1BEG3_3" + ], + [ + "CMT_FIFO_L_FAN4_4", + "CMT_TOP_FAN4_4" + ], + [ + "CMT_FIFO_LH12_6", + "CMT_TOP_LH12_6" + ], + [ + "CMT_FIFO_SW2A0_10", + "CMT_TOP_SW2A0_10" + ], + [ + "CMT_FIFO_L_IMUX24_1", + "CMT_TOP_IMUX24_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "CMT_TOP_ICLKDIV_2" + ], + [ + "CMT_FIFO_L_IMUX47_8", + "CMT_TOP_IMUX47_8" + ], + [ + "CMT_FIFO_SW2A3_2", + "CMT_TOP_SW2A3_2" + ], + [ + "CMT_FIFO_L_IMUX26_6", + "CMT_TOP_IMUX26_6" + ], + [ + "CMT_FIFO_WW4C0_11", + "CMT_TOP_WW4C0_11" + ], + [ + "CMT_FIFO_L_FAN3_8", + "CMT_TOP_FAN3_8" + ], + [ + "CMT_FIFO_SW2A3_9", + "CMT_TOP_SW2A3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_10", + "CMT_TOP_LOGIC_OUTS_L_B20_10" + ], + [ + "CMT_FIFO_L_BYP5_1", + "CMT_TOP_BYP5_1" + ], + [ + "CMT_FIFO_SE4C3_8", + "CMT_TOP_SE4C3_8" + ], + [ + "CMT_FIFO_WW4B1_10", + "CMT_TOP_WW4B1_10" + ], + [ + "CMT_FIFO_WW2A3_7", + "CMT_TOP_WW2A3_7" + ], + [ + "CMT_FIFO_L_BYP0_0", + "CMT_TOP_BYP0_0" + ], + [ + "CMT_FIFO_L_IMUX36_5", + "CMT_TOP_IMUX36_5" + ], + [ + "CMT_FIFO_L_FAN6_6", + "CMT_TOP_FAN6_6" + ], + [ + "CMT_FIFO_WW4A3_3", + "CMT_TOP_WW4A3_3" + ], + [ + "CMT_FIFO_L_IMUX31_5", + "CMT_TOP_IMUX31_5" + ], + [ + "CMT_FIFO_L_FAN1_4", + "CMT_TOP_FAN1_4" + ], + [ + "CMT_FIFO_WW2END3_11", + "CMT_TOP_WW2END3_11" + ], + [ + "CMT_FIFO_L_CLK1_10", + "CMT_TOP_CLK1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_3", + "CMT_TOP_LOGIC_OUTS_L_B15_3" + ], + [ + "CMT_FIFO_ER1BEG3_6", + "CMT_TOP_ER1BEG3_6" + ], + [ + "CMT_FIFO_NW4END3_3", + "CMT_TOP_NW4END3_3" + ], + [ + "CMT_FIFO_WR1END1_8", + "CMT_TOP_WR1END1_8" + ], + [ + "CMT_FIFO_WW4B2_6", + "CMT_TOP_WW4B2_6" + ], + [ + "CMT_FIFO_L_FAN5_6", + "CMT_TOP_FAN5_6" + ], + [ + "CMT_FIFO_NW4END2_9", + "CMT_TOP_NW4END2_9" + ], + [ + "CMT_FIFO_WW2A2_8", + "CMT_TOP_WW2A2_8" + ], + [ + "CMT_FIFO_NE2A0_8", + "CMT_TOP_NE2A0_8" + ], + [ + "CMT_FIFO_EE4C0_4", + "CMT_TOP_EE4C0_4" + ], + [ + "CMT_FIFO_LH9_2", + "CMT_TOP_LH9_2" + ], + [ + "CMT_FIFO_EL1BEG1_11", + "CMT_TOP_EL1BEG1_11" + ], + [ + "CMT_FIFO_L_IMUX5_7", + "CMT_TOP_IMUX5_7" + ], + [ + "CMT_FIFO_L_IMUX5_3", + "CMT_TOP_IMUX5_3" + ], + [ + "CMT_FIFO_LH2_3", + "CMT_TOP_LH2_3" + ], + [ + "CMT_FIFO_EE2A3_4", + "CMT_TOP_EE2A3_4" + ], + [ + "CMT_FIFO_EL1BEG3_6", + "CMT_TOP_EL1BEG3_6" + ], + [ + "CMT_FIFO_L_BYP5_3", + "CMT_TOP_BYP5_3" + ], + [ + "CMT_FIFO_L_IMUX7_8", + "CMT_TOP_IMUX7_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_7", + "CMT_TOP_LOGIC_OUTS_L_B2_7" + ], + [ + "CMT_FIFO_EE4A0_7", + "CMT_TOP_EE4A0_7" + ], + [ + "CMT_FIFO_L_IMUX30_10", + "CMT_TOP_IMUX30_10" + ], + [ + "CMT_FIFO_WW2END1_4", + "CMT_TOP_WW2END1_4" + ], + [ + "CMT_FIFO_WW4END2_4", + "CMT_TOP_WW4END2_4" + ], + [ + "CMT_FIFO_L_FAN5_10", + "CMT_TOP_FAN5_10" + ], + [ + "CMT_FIFO_NE2A2_1", + "CMT_TOP_NE2A2_1" + ], + [ + "CMT_FIFO_WL1END1_2", + "CMT_TOP_WL1END1_2" + ], + [ + "CMT_FIFO_L_IMUX9_0", + "CMT_TOP_IMUX9_0" + ], + [ + "CMT_FIFO_L_FAN6_8", + "CMT_TOP_FAN6_8" + ], + [ + "CMT_FIFO_L_IMUX21_3", + "CMT_TOP_IMUX21_3" + ], + [ + "CMT_FIFO_WW2END0_1", + "CMT_TOP_WW2END0_1" + ], + [ + "CMT_FIFO_LH2_8", + "CMT_TOP_LH2_8" + ], + [ + "CMT_FIFO_L_IMUX27_9", + "CMT_TOP_IMUX27_9" + ], + [ + "CMT_FIFO_SW4END1_1", + "CMT_TOP_SW4END1_1" + ], + [ + "CMT_FIFO_EE2A0_4", + "CMT_TOP_EE2A0_4" + ], + [ + "CMT_FIFO_WW4END0_10", + "CMT_TOP_WW4END0_10" + ], + [ + "CMT_FIFO_L_IMUX7_2", + "CMT_TOP_IMUX7_2" + ], + [ + "CMT_FIFO_NW4A0_6", + "CMT_TOP_NW4A0_6" + ], + [ + "CMT_FIFO_L_IMUX42_0", + "CMT_TOP_IMUX42_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_10" + ], + [ + "CMT_FIFO_L_BYP4_4", + "CMT_TOP_BYP4_4" + ], + [ + "CMT_FIFO_SE2A2_3", + "CMT_TOP_SE2A2_3" + ], + [ + "CMT_FIFO_NE2A1_9", + "CMT_TOP_NE2A1_9" + ], + [ + "CMT_FIFO_WW2A0_3", + "CMT_TOP_WW2A0_3" + ], + [ + "CMT_FIFO_L_IMUX9_5", + "CMT_TOP_IMUX9_5" + ], + [ + "CMT_FIFO_NE4C1_8", + "CMT_TOP_NE4C1_8" + ], + [ + "CMT_FIFO_WL1END0_2", + "CMT_TOP_WL1END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_3", + "CMT_TOP_LOGIC_OUTS_L_B4_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_2", + "CMT_TOP_LOGIC_OUTS_L_B8_2" + ], + [ + "CMT_FIFO_L_FAN4_6", + "CMT_TOP_FAN4_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_3", + "CMT_TOP_LOGIC_OUTS_L_B23_3" + ], + [ + "CMT_FIFO_L_IMUX16_9", + "CMT_TOP_IMUX16_9" + ], + [ + "CMT_FIFO_SE2A1_9", + "CMT_TOP_SE2A1_9" + ], + [ + "CMT_FIFO_NW4END1_7", + "CMT_TOP_NW4END1_7" + ], + [ + "CMT_FIFO_SE2A2_10", + "CMT_TOP_SE2A2_10" + ], + [ + "CMT_FIFO_L_IMUX25_10", + "CMT_TOP_IMUX25_10" + ], + [ + "CMT_FIFO_L_BYP4_9", + "CMT_TOP_BYP4_9" + ], + [ + "CMT_FIFO_EE2BEG2_11", + "CMT_TOP_EE2BEG2_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_6", + "CMT_TOP_LOGIC_OUTS_L_B6_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_8", + "CMT_TOP_LOGIC_OUTS_L_B14_8" + ], + [ + "CMT_FIFO_WW2END1_1", + "CMT_TOP_WW2END1_1" + ], + [ + "CMT_FIFO_WW2END3_6", + "CMT_TOP_WW2END3_6" + ], + [ + "CMT_FIFO_L_CLK1_7", + "CMT_TOP_CLK1_7" + ], + [ + "CMT_FIFO_SE4BEG3_10", + "CMT_TOP_SE4BEG3_10" + ], + [ + "CMT_FIFO_SW4A1_1", + "CMT_TOP_SW4A1_1" + ], + [ + "CMT_FIFO_LH8_3", + "CMT_TOP_LH8_3" + ], + [ + "CMT_FIFO_WW4A1_9", + "CMT_TOP_WW4A1_9" + ], + [ + "CMT_FIFO_L_IMUX45_1", + "CMT_TOP_IMUX45_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_2", + "CMT_TOP_LOGIC_OUTS_L_B18_2" + ], + [ + "CMT_FIFO_L_IMUX28_10", + "CMT_TOP_IMUX28_10" + ], + [ + "CMT_FIFO_SE4C0_0", + "CMT_TOP_SE4C0_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "CMT_TOP_OCLK_2" + ], + [ + "CMT_FIFO_L_IMUX21_11", + "CMT_TOP_IMUX21_11" + ], + [ + "CMT_FIFO_NE4BEG1_0", + "CMT_TOP_NE4BEG1_0" + ], + [ + "CMT_FIFO_SW4END1_11", + "CMT_TOP_SW4END1_11" + ], + [ + "CMT_FIFO_NE4C2_7", + "CMT_TOP_NE4C2_7" + ], + [ + "CMT_FIFO_SE4C2_4", + "CMT_TOP_SE4C2_4" + ], + [ + "CMT_FIFO_SW4A3_4", + "CMT_TOP_SW4A3_4" + ], + [ + "CMT_FIFO_ER1BEG1_0", + "CMT_TOP_ER1BEG1_0" + ], + [ + "CMT_FIFO_NW4A2_3", + "CMT_TOP_NW4A2_3" + ], + [ + "CMT_FIFO_WW4A1_0", + "CMT_TOP_WW4A1_0" + ], + [ + "CMT_FIFO_EL1BEG1_9", + "CMT_TOP_EL1BEG1_9" + ], + [ + "CMT_FIFO_L_IMUX34_11", + "CMT_TOP_IMUX34_11" + ], + [ + "CMT_FIFO_SW2A0_0", + "CMT_TOP_SW2A0_0" + ], + [ + "CMT_FIFO_SE4BEG1_5", + "CMT_TOP_SE4BEG1_5" + ], + [ + "CMT_FIFO_NW4END0_6", + "CMT_TOP_NW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX23_2", + "CMT_TOP_IMUX23_2" + ], + [ + "CMT_FIFO_L_IMUX1_11", + "CMT_TOP_IMUX1_11" + ], + [ + "CMT_FIFO_WW4END1_1", + "CMT_TOP_WW4END1_1" + ], + [ + "CMT_FIFO_EE2BEG3_7", + "CMT_TOP_EE2BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX33_5", + "CMT_TOP_IMUX33_5" + ], + [ + "CMT_FIFO_WW4B3_3", + "CMT_TOP_WW4B3_3" + ], + [ + "CMT_FIFO_L_FAN5_0", + "CMT_TOP_FAN5_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_6", + "CMT_TOP_LOGIC_OUTS_L_B17_6" + ], + [ + "CMT_FIFO_WW4END2_8", + "CMT_TOP_WW4END2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_0", + "CMT_TOP_LOGIC_OUTS_L_B21_0" + ], + [ + "CMT_FIFO_L_BYP0_1", + "CMT_TOP_BYP0_1" + ], + [ + "CMT_FIFO_WL1END3_7", + "CMT_TOP_WL1END3_7" + ], + [ + "CMT_FIFO_L_IMUX39_9", + "CMT_TOP_IMUX39_9" + ], + [ + "CMT_FIFO_WR1END3_6", + "CMT_TOP_WR1END3_6" + ], + [ + "CMT_FIFO_SE4C3_1", + "CMT_TOP_SE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX33_7", + "CMT_TOP_IMUX33_7" + ], + [ + "CMT_FIFO_L_BYP4_11", + "CMT_TOP_BYP4_11" + ], + [ + "CMT_FIFO_L_IMUX32_6", + "CMT_TOP_IMUX32_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "CMT_TOP_OCLKDIV_2" + ], + [ + "CMT_FIFO_L_IMUX33_11", + "CMT_TOP_IMUX33_11" + ], + [ + "CMT_FIFO_SE2A3_4", + "CMT_TOP_SE2A3_4" + ], + [ + "CMT_FIFO_L_IMUX44_2", + "CMT_TOP_IMUX44_2" + ], + [ + "CMT_FIFO_NE4C3_5", + "CMT_TOP_NE4C3_5" + ], + [ + "CMT_FIFO_EE4B1_4", + "CMT_TOP_EE4B1_4" + ], + [ + "CMT_FIFO_SW2A2_11", + "CMT_TOP_SW2A2_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_0", + "CMT_TOP_LOGIC_OUTS_L_B22_0" + ], + [ + "CMT_FIFO_WW4C3_9", + "CMT_TOP_WW4C3_9" + ], + [ + "CMT_FIFO_EE2BEG0_11", + "CMT_TOP_EE2BEG0_11" + ], + [ + "CMT_FIFO_ER1BEG0_0", + "CMT_TOP_ER1BEG0_0" + ], + [ + "CMT_FIFO_NW4END2_8", + "CMT_TOP_NW4END2_8" + ], + [ + "CMT_FIFO_L_IMUX25_3", + "CMT_TOP_IMUX25_3" + ], + [ + "CMT_FIFO_NW4A0_2", + "CMT_TOP_NW4A0_2" + ], + [ + "CMT_FIFO_SE4C1_0", + "CMT_TOP_SE4C1_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_8", + "CMT_TOP_LOGIC_OUTS_L_B1_8" + ], + [ + "CMT_FIFO_WW4A1_7", + "CMT_TOP_WW4A1_7" + ], + [ + "CMT_FIFO_L_IMUX21_1", + "CMT_TOP_IMUX21_1" + ], + [ + "CMT_FIFO_LH11_2", + "CMT_TOP_LH11_2" + ], + [ + "CMT_FIFO_SE2A1_8", + "CMT_TOP_SE2A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_4", + "CMT_TOP_LOGIC_OUTS_L_B13_4" + ], + [ + "CMT_FIFO_WW4END3_1", + "CMT_TOP_WW4END3_1" + ], + [ + "CMT_FIFO_L_BYP1_6", + "CMT_TOP_BYP1_6" + ], + [ + "CMT_FIFO_LH7_7", + "CMT_TOP_LH7_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_3", + "CMT_TOP_LOGIC_OUTS_L_B6_3" + ], + [ + "CMT_FIFO_EE4BEG0_0", + "CMT_TOP_EE4BEG0_0" + ], + [ + "CMT_FIFO_NE4BEG2_11", + "CMT_TOP_NE4BEG2_11" + ], + [ + "CMT_FIFO_WW4A2_9", + "CMT_TOP_WW4A2_9" + ], + [ + "CMT_FIFO_L_IMUX29_6", + "CMT_TOP_IMUX29_6" + ], + [ + "CMT_FIFO_WW2A2_2", + "CMT_TOP_WW2A2_2" + ], + [ + "CMT_FIFO_L_BYP0_2", + "CMT_TOP_BYP0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_10", + "CMT_TOP_LOGIC_OUTS_L_B6_10" + ], + [ + "CMT_FIFO_NE4BEG1_6", + "CMT_TOP_NE4BEG1_6" + ], + [ + "CMT_FIFO_NW2A1_4", + "CMT_TOP_NW2A1_4" + ], + [ + "CMT_FIFO_L_IMUX2_11", + "CMT_TOP_IMUX2_11" + ], + [ + "CMT_FIFO_WW4A3_9", + "CMT_TOP_WW4A3_9" + ], + [ + "CMT_FIFO_SW2A0_7", + "CMT_TOP_SW2A0_7" + ], + [ + "CMT_FIFO_L_FAN0_8", + "CMT_TOP_FAN0_8" + ], + [ + "CMT_FIFO_NE4BEG3_5", + "CMT_TOP_NE4BEG3_5" + ], + [ + "CMT_FIFO_LH5_1", + "CMT_TOP_LH5_1" + ], + [ + "CMT_FIFO_SE4BEG0_4", + "CMT_TOP_SE4BEG0_4" + ], + [ + "CMT_FIFO_WW4END1_3", + "CMT_TOP_WW4END1_3" + ], + [ + "CMT_FIFO_NE2A1_8", + "CMT_TOP_NE2A1_8" + ], + [ + "CMT_FIFO_L_IMUX8_2", + "CMT_TOP_IMUX8_2" + ], + [ + "CMT_FIFO_SE2A0_8", + "CMT_TOP_SE2A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_6", + "CMT_TOP_LOGIC_OUTS_L_B8_6" + ], + [ + "CMT_FIFO_L_BYP3_0", + "CMT_TOP_BYP3_0" + ], + [ + "CMT_FIFO_EE2BEG0_6", + "CMT_TOP_EE2BEG0_6" + ], + [ + "CMT_FIFO_EL1BEG2_9", + "CMT_TOP_EL1BEG2_9" + ], + [ + "CMT_FIFO_EE4B2_9", + "CMT_TOP_EE4B2_9" + ], + [ + "CMT_FIFO_SE4C3_4", + "CMT_TOP_SE4C3_4" + ], + [ + "CMT_FIFO_L_IMUX30_1", + "CMT_TOP_IMUX30_1" + ], + [ + "CMT_FIFO_L_BYP4_0", + "CMT_TOP_BYP4_0" + ], + [ + "CMT_FIFO_L_IMUX34_10", + "CMT_TOP_IMUX34_10" + ], + [ + "CMT_FIFO_SW2A0_6", + "CMT_TOP_SW2A0_6" + ], + [ + "CMT_FIFO_NW4A3_4", + "CMT_TOP_NW4A3_4" + ], + [ + "CMT_FIFO_L_IMUX17_3", + "CMT_TOP_IMUX17_3" + ], + [ + "CMT_FIFO_WW2END0_5", + "CMT_TOP_WW2END0_5" + ], + [ + "CMT_FIFO_EE2BEG2_0", + "CMT_TOP_EE2BEG2_0" + ], + [ + "CMT_FIFO_WR1END3_10", + "CMT_TOP_WR1END3_10" + ], + [ + "CMT_FIFO_L_IMUX41_1", + "CMT_TOP_IMUX41_1" + ], + [ + "CMT_FIFO_EE4A0_10", + "CMT_TOP_EE4A0_10" + ], + [ + "CMT_FIFO_EE4B1_9", + "CMT_TOP_EE4B1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_3", + "CMT_TOP_LOGIC_OUTS_L_B11_3" + ], + [ + "CMT_FIFO_NW2A0_0", + "CMT_TOP_NW2A0_0" + ], + [ + "CMT_FIFO_L_IMUX26_11", + "CMT_TOP_IMUX26_11" + ], + [ + "CMT_FIFO_L_IMUX2_10", + "CMT_TOP_IMUX2_10" + ], + [ + "CMT_FIFO_L_IMUX5_4", + "CMT_TOP_IMUX5_4" + ], + [ + "CMT_FIFO_SW4END3_10", + "CMT_TOP_SW4END3_10" + ], + [ + "CMT_FIFO_WW4C2_2", + "CMT_TOP_WW4C2_2" + ], + [ + "CMT_FIFO_SE4BEG1_7", + "CMT_TOP_SE4BEG1_7" + ], + [ + "CMT_FIFO_SW4A1_5", + "CMT_TOP_SW4A1_5" + ], + [ + "CMT_FIFO_SW2A0_11", + "CMT_TOP_SW2A0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_3", + "CMT_TOP_LOGIC_OUTS_L_B13_3" + ], + [ + "CMT_FIFO_L_IMUX29_5", + "CMT_TOP_IMUX29_5" + ], + [ + "CMT_FIFO_L_FAN6_3", + "CMT_TOP_FAN6_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_4", + "CMT_TOP_LOGIC_OUTS_L_B23_4" + ], + [ + "CMT_FIFO_L_IMUX25_5", + "CMT_TOP_IMUX25_5" + ], + [ + "CMT_FIFO_SE4C0_2", + "CMT_TOP_SE4C0_2" + ], + [ + "CMT_FIFO_WW2A2_10", + "CMT_TOP_WW2A2_10" + ], + [ + "CMT_FIFO_L_CLK1_1", + "CMT_TOP_CLK1_1" + ], + [ + "CMT_FIFO_L_IMUX0_0", + "CMT_TOP_IMUX0_0" + ], + [ + "CMT_FIFO_L_IMUX29_11", + "CMT_TOP_IMUX29_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "CMT_TOP_ICLKDIV_7" + ], + [ + "CMT_FIFO_L_FAN6_4", + "CMT_TOP_FAN6_4" + ], + [ + "CMT_FIFO_NE4BEG1_10", + "CMT_TOP_NE4BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX0_8", + "CMT_TOP_IMUX0_8" + ], + [ + "CMT_FIFO_L_IMUX34_1", + "CMT_TOP_IMUX34_1" + ], + [ + "CMT_FIFO_EL1BEG2_3", + "CMT_TOP_EL1BEG2_3" + ], + [ + "CMT_FIFO_SW2A0_9", + "CMT_TOP_SW2A0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_1", + "CMT_TOP_LOGIC_OUTS_L_B0_1" + ], + [ + "CMT_FIFO_WW4A2_11", + "CMT_TOP_WW4A2_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "CMT_TOP_OCLKDIV_0" + ], + [ + "CMT_FIFO_NW4A1_10", + "CMT_TOP_NW4A1_10" + ], + [ + "CMT_FIFO_LH11_7", + "CMT_TOP_LH11_7" + ], + [ + "CMT_FIFO_NE4C3_11", + "CMT_TOP_NE4C3_11" + ], + [ + "CMT_FIFO_L_IMUX23_0", + "CMT_TOP_IMUX23_0" + ], + [ + "CMT_FIFO_NW4A3_6", + "CMT_TOP_NW4A3_6" + ], + [ + "CMT_FIFO_SW2A2_9", + "CMT_TOP_SW2A2_9" + ], + [ + "CMT_FIFO_L_FAN3_2", + "CMT_TOP_FAN3_2" + ], + [ + "CMT_FIFO_WL1END1_3", + "CMT_TOP_WL1END1_3" + ], + [ + "CMT_FIFO_L_IMUX12_0", + "CMT_TOP_IMUX12_0" + ], + [ + "CMT_FIFO_WW4C0_2", + "CMT_TOP_WW4C0_2" + ], + [ + "CMT_FIFO_NW4A2_7", + "CMT_TOP_NW4A2_7" + ], + [ + "CMT_FIFO_ER1BEG1_3", + "CMT_TOP_ER1BEG1_3" + ], + [ + "CMT_FIFO_WW4C1_4", + "CMT_TOP_WW4C1_4" + ], + [ + "CMT_FIFO_WW4END3_3", + "CMT_TOP_WW4END3_3" + ], + [ + "CMT_FIFO_EE4A1_5", + "CMT_TOP_EE4A1_5" + ], + [ + "CMT_FIFO_SE2A2_7", + "CMT_TOP_SE2A2_7" + ], + [ + "CMT_FIFO_NW2A1_0", + "CMT_TOP_NW2A1_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "CMT_TOP_OCLK1X_90_7" + ], + [ + "CMT_FIFO_L_CTRL1_5", + "CMT_TOP_CTRL1_5" + ], + [ + "CMT_FIFO_WW4B0_11", + "CMT_TOP_WW4B0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_6", + "CMT_TOP_LOGIC_OUTS_L_B7_6" + ], + [ + "CMT_FIFO_L_IMUX34_3", + "CMT_TOP_IMUX34_3" + ], + [ + "CMT_FIFO_WW2A1_3", + "CMT_TOP_WW2A1_3" + ], + [ + "CMT_FIFO_EL1BEG3_7", + "CMT_TOP_EL1BEG3_7" + ], + [ + "CMT_FIFO_EE2BEG2_4", + "CMT_TOP_EE2BEG2_4" + ], + [ + "CMT_FIFO_LH10_11", + "CMT_TOP_LH10_11" + ], + [ + "CMT_FIFO_SW2A1_0", + "CMT_TOP_SW2A1_0" + ], + [ + "CMT_FIFO_L_IMUX15_9", + "CMT_TOP_IMUX15_9" + ], + [ + "CMT_FIFO_L_IMUX1_4", + "CMT_TOP_IMUX1_4" + ], + [ + "CMT_FIFO_L_IMUX22_7", + "CMT_TOP_IMUX22_7" + ], + [ + "CMT_FIFO_EE4A0_11", + "CMT_TOP_EE4A0_11" + ], + [ + "CMT_FIFO_WL1END2_3", + "CMT_TOP_WL1END2_3" + ], + [ + "CMT_FIFO_EE2BEG3_1", + "CMT_TOP_EE2BEG3_1" + ], + [ + "CMT_FIFO_EE2A2_1", + "CMT_TOP_EE2A2_1" + ], + [ + "CMT_FIFO_NW4END2_1", + "CMT_TOP_NW4END2_1" + ], + [ + "CMT_FIFO_L_IMUX16_7", + "CMT_TOP_IMUX16_7" + ], + [ + "CMT_FIFO_SW4A2_2", + "CMT_TOP_SW4A2_2" + ], + [ + "CMT_FIFO_LH11_9", + "CMT_TOP_LH11_9" + ], + [ + "CMT_FIFO_ER1BEG2_9", + "CMT_TOP_ER1BEG2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_5", + "CMT_TOP_LOGIC_OUTS_L_B14_5" + ], + [ + "CMT_FIFO_LH6_2", + "CMT_TOP_LH6_2" + ], + [ + "CMT_FIFO_SE4C1_5", + "CMT_TOP_SE4C1_5" + ], + [ + "CMT_FIFO_L_IMUX2_2", + "CMT_TOP_IMUX2_2" + ], + [ + "CMT_FIFO_NE4C3_8", + "CMT_TOP_NE4C3_8" + ], + [ + "CMT_FIFO_WR1END0_11", + "CMT_TOP_WR1END0_11" + ], + [ + "CMT_FIFO_L_IMUX25_2", + "CMT_TOP_IMUX25_2" + ], + [ + "CMT_FIFO_SW4END0_2", + "CMT_TOP_SW4END0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_7", + "CMT_TOP_LOGIC_OUTS_L_B5_7" + ], + [ + "CMT_FIFO_L_IMUX32_1", + "CMT_TOP_IMUX32_1" + ], + [ + "CMT_FIFO_L_IMUX41_5", + "CMT_TOP_IMUX41_5" + ], + [ + "CMT_FIFO_EE4C1_0", + "CMT_TOP_EE4C1_0" + ], + [ + "CMT_FIFO_EE4C0_6", + "CMT_TOP_EE4C0_6" + ], + [ + "CMT_FIFO_WW2A3_1", + "CMT_TOP_WW2A3_1" + ], + [ + "CMT_FIFO_NE4C2_1", + "CMT_TOP_NE4C2_1" + ], + [ + "CMT_FIFO_NW2A3_0", + "CMT_TOP_NW2A3_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "CMT_TOP_OCLK_7" + ], + [ + "CMT_FIFO_L_IMUX15_6", + "CMT_TOP_IMUX15_6" + ], + [ + "CMT_FIFO_EE2A0_3", + "CMT_TOP_EE2A0_3" + ], + [ + "CMT_FIFO_EE4BEG1_11", + "CMT_TOP_EE4BEG1_11" + ], + [ + "CMT_FIFO_LH7_5", + "CMT_TOP_LH7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_7", + "CMT_TOP_LOGIC_OUTS_L_B20_7" + ], + [ + "CMT_FIFO_SE4BEG0_8", + "CMT_TOP_SE4BEG0_8" + ], + [ + "CMT_FIFO_EE4C1_4", + "CMT_TOP_EE4C1_4" + ], + [ + "CMT_FIFO_NW2A2_1", + "CMT_TOP_NW2A2_1" + ], + [ + "CMT_FIFO_ER1BEG3_9", + "CMT_TOP_ER1BEG3_9" + ], + [ + "CMT_FIFO_EE4A3_0", + "CMT_TOP_EE4A3_0" + ], + [ + "CMT_FIFO_L_IMUX3_9", + "CMT_TOP_IMUX3_9" + ], + [ + "CMT_FIFO_EE4C0_7", + "CMT_TOP_EE4C0_7" + ], + [ + "CMT_FIFO_L_BYP1_1", + "CMT_TOP_BYP1_1" + ], + [ + "CMT_FIFO_SE4BEG3_0", + "CMT_TOP_SE4BEG3_0" + ], + [ + "CMT_FIFO_L_IMUX31_2", + "CMT_TOP_IMUX31_2" + ], + [ + "CMT_FIFO_WW2END3_5", + "CMT_TOP_WW2END3_5" + ], + [ + "CMT_FIFO_L_IMUX1_10", + "CMT_TOP_IMUX1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_1", + "CMT_TOP_LOGIC_OUTS_L_B20_1" + ], + [ + "CMT_FIFO_EE4BEG2_3", + "CMT_TOP_EE4BEG2_3" + ], + [ + "CMT_FIFO_L_FAN1_5", + "CMT_TOP_FAN1_5" + ], + [ + "CMT_FIFO_L_IMUX34_0", + "CMT_TOP_IMUX34_0" + ], + [ + "CMT_FIFO_L_IMUX23_3", + "CMT_TOP_IMUX23_3" + ], + [ + "CMT_FIFO_L_IMUX27_8", + "CMT_TOP_IMUX27_8" + ], + [ + "CMT_FIFO_WW4C1_1", + "CMT_TOP_WW4C1_1" + ], + [ + "CMT_FIFO_NE4BEG1_5", + "CMT_TOP_NE4BEG1_5" + ], + [ + "CMT_FIFO_NE4BEG2_4", + "CMT_TOP_NE4BEG2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_5", + "CMT_TOP_LOGIC_OUTS_L_B5_5" + ], + [ + "CMT_FIFO_WW4A0_1", + "CMT_TOP_WW4A0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_1", + "CMT_TOP_LOGIC_OUTS_L_B4_1" + ], + [ + "CMT_FIFO_WW2A3_5", + "CMT_TOP_WW2A3_5" + ], + [ + "CMT_FIFO_WW4A0_6", + "CMT_TOP_WW4A0_6" + ], + [ + "CMT_FIFO_WW4C0_6", + "CMT_TOP_WW4C0_6" + ], + [ + "CMT_FIFO_SW4END1_4", + "CMT_TOP_SW4END1_4" + ], + [ + "CMT_FIFO_EE4A1_1", + "CMT_TOP_EE4A1_1" + ], + [ + "CMT_FIFO_LH4_7", + "CMT_TOP_LH4_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_7", + "CMT_TOP_LOGIC_OUTS_L_B7_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_9", + "CMT_TOP_LOGIC_OUTS_L_B23_9" + ], + [ + "CMT_FIFO_SE4C2_3", + "CMT_TOP_SE4C2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_1", + "CMT_TOP_LOGIC_OUTS_L_B14_1" + ], + [ + "CMT_FIFO_NW4END1_1", + "CMT_TOP_NW4END1_1" + ], + [ + "CMT_FIFO_WW2END3_8", + "CMT_TOP_WW2END3_8" + ], + [ + "CMT_FIFO_NW2A2_4", + "CMT_TOP_NW2A2_4" + ], + [ + "CMT_FIFO_EE4BEG2_8", + "CMT_TOP_EE4BEG2_8" + ], + [ + "CMT_FIFO_NW2A3_5", + "CMT_TOP_NW2A3_5" + ], + [ + "CMT_FIFO_L_IMUX11_3", + "CMT_TOP_IMUX11_3" + ], + [ + "CMT_FIFO_WW4A0_0", + "CMT_TOP_WW4A0_0" + ], + [ + "CMT_FIFO_WW4END0_4", + "CMT_TOP_WW4END0_4" + ], + [ + "CMT_FIFO_L_IMUX39_4", + "CMT_TOP_IMUX39_4" + ], + [ + "CMT_FIFO_SE4C3_10", + "CMT_TOP_SE4C3_10" + ], + [ + "CMT_FIFO_L_IMUX22_8", + "CMT_TOP_IMUX22_8" + ], + [ + "CMT_FIFO_L_IMUX42_11", + "CMT_TOP_IMUX42_11" + ], + [ + "CMT_FIFO_WW2END3_1", + "CMT_TOP_WW2END3_1" + ], + [ + "CMT_FIFO_L_IMUX2_4", + "CMT_TOP_IMUX2_4" + ], + [ + "CMT_FIFO_L_BYP6_3", + "CMT_TOP_BYP6_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_4", + "CMT_TOP_LOGIC_OUTS_L_B7_4" + ], + [ + "CMT_FIFO_WW4A3_4", + "CMT_TOP_WW4A3_4" + ], + [ + "CMT_FIFO_L_IMUX7_3", + "CMT_TOP_IMUX7_3" + ], + [ + "CMT_FIFO_SW2A1_9", + "CMT_TOP_SW2A1_9" + ], + [ + "CMT_FIFO_L_IMUX18_6", + "CMT_TOP_IMUX18_6" + ], + [ + "CMT_FIFO_L_IMUX12_2", + "CMT_TOP_IMUX12_2" + ], + [ + "CMT_FIFO_LH12_2", + "CMT_TOP_LH12_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_3", + "CMT_TOP_LOGIC_OUTS_L_B8_3" + ], + [ + "CMT_FIFO_WW2END0_4", + "CMT_TOP_WW2END0_4" + ], + [ + "CMT_FIFO_L_IMUX22_3", + "CMT_TOP_IMUX22_3" + ], + [ + "CMT_FIFO_NE4BEG3_10", + "CMT_TOP_NE4BEG3_10" + ], + [ + "CMT_FIFO_LH11_5", + "CMT_TOP_LH11_5" + ], + [ + "CMT_FIFO_L_IMUX10_3", + "CMT_TOP_IMUX10_3" + ], + [ + "CMT_FIFO_LH3_10", + "CMT_TOP_LH3_10" + ], + [ + "CMT_FIFO_LH9_8", + "CMT_TOP_LH9_8" + ], + [ + "CMT_FIFO_NW4END2_11", + "CMT_TOP_NW4END2_11" + ], + [ + "CMT_FIFO_L_IMUX15_3", + "CMT_TOP_IMUX15_3" + ], + [ + "CMT_FIFO_L_IMUX47_11", + "CMT_TOP_IMUX47_11" + ], + [ + "CMT_FIFO_SE2A2_11", + "CMT_TOP_SE2A2_11" + ], + [ + "CMT_FIFO_EE4B1_5", + "CMT_TOP_EE4B1_5" + ], + [ + "CMT_FIFO_SE4BEG1_6", + "CMT_TOP_SE4BEG1_6" + ], + [ + "CMT_FIFO_LH6_6", + "CMT_TOP_LH6_6" + ], + [ + "CMT_FIFO_NE2A3_0", + "CMT_TOP_NE2A3_0" + ], + [ + "CMT_FIFO_L_BYP0_4", + "CMT_TOP_BYP0_4" + ], + [ + "CMT_FIFO_WW2END2_5", + "CMT_TOP_WW2END2_5" + ], + [ + "CMT_FIFO_EE4B3_6", + "CMT_TOP_EE4B3_6" + ], + [ + "CMT_FIFO_L_IMUX39_3", + "CMT_TOP_IMUX39_3" + ], + [ + "CMT_FIFO_L_FAN7_5", + "CMT_TOP_FAN7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_6", + "CMT_TOP_LOGIC_OUTS_L_B2_6" + ], + [ + "CMT_FIFO_WW2END0_2", + "CMT_TOP_WW2END0_2" + ], + [ + "CMT_FIFO_SE4C3_3", + "CMT_TOP_SE4C3_3" + ], + [ + "CMT_FIFO_NE4C3_1", + "CMT_TOP_NE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX40_3", + "CMT_TOP_IMUX40_3" + ], + [ + "CMT_FIFO_WW4A3_0", + "CMT_TOP_WW4A3_0" + ], + [ + "CMT_FIFO_L_IMUX37_10", + "CMT_TOP_IMUX37_10" + ], + [ + "CMT_FIFO_L_IMUX21_4", + "CMT_TOP_IMUX21_4" + ], + [ + "CMT_FIFO_SE4BEG0_11", + "CMT_TOP_SE4BEG0_11" + ], + [ + "CMT_FIFO_WW4B2_10", + "CMT_TOP_WW4B2_10" + ], + [ + "CMT_FIFO_EE4B1_11", + "CMT_TOP_EE4B1_11" + ], + [ + "CMT_FIFO_WW2A1_6", + "CMT_TOP_WW2A1_6" + ], + [ + "CMT_FIFO_NE2A0_10", + "CMT_TOP_NE2A0_10" + ], + [ + "CMT_FIFO_EE4B2_7", + "CMT_TOP_EE4B2_7" + ], + [ + "CMT_FIFO_SE4C0_10", + "CMT_TOP_SE4C0_10" + ], + [ + "CMT_FIFO_SE2A0_2", + "CMT_TOP_SE2A0_2" + ], + [ + "CMT_FIFO_NE4C1_4", + "CMT_TOP_NE4C1_4" + ], + [ + "CMT_FIFO_L_IMUX4_5", + "CMT_TOP_IMUX4_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_10", + "CMT_TOP_LOGIC_OUTS_L_B0_10" + ], + [ + "CMT_FIFO_L_IMUX26_5", + "CMT_TOP_IMUX26_5" + ], + [ + "CMT_FIFO_EE4A3_8", + "CMT_TOP_EE4A3_8" + ], + [ + "CMT_FIFO_L_IMUX38_7", + "CMT_TOP_IMUX38_7" + ], + [ + "CMT_FIFO_EL1BEG0_1", + "CMT_TOP_EL1BEG0_1" + ], + [ + "CMT_FIFO_L_IMUX33_10", + "CMT_TOP_IMUX33_10" + ], + [ + "CMT_FIFO_LH4_11", + "CMT_TOP_LH4_11" + ], + [ + "CMT_FIFO_L_IMUX37_6", + "CMT_TOP_IMUX37_6" + ], + [ + "CMT_FIFO_L_IMUX15_10", + "CMT_TOP_IMUX15_10" + ], + [ + "CMT_FIFO_EL1BEG1_8", + "CMT_TOP_EL1BEG1_8" + ], + [ + "CMT_FIFO_NE2A2_5", + "CMT_TOP_NE2A2_5" + ], + [ + "CMT_FIFO_SW2A2_4", + "CMT_TOP_SW2A2_4" + ], + [ + "CMT_FIFO_SW4END3_2", + "CMT_TOP_SW4END3_2" + ], + [ + "CMT_FIFO_L_IMUX31_9", + "CMT_TOP_IMUX31_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "CMT_TOP_OCLKDIV_7" + ], + [ + "CMT_FIFO_L_IMUX23_8", + "CMT_TOP_IMUX23_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_10", + "CMT_TOP_LOGIC_OUTS_L_B7_10" + ], + [ + "CMT_FIFO_EE4A2_3", + "CMT_TOP_EE4A2_3" + ], + [ + "CMT_FIFO_L_IMUX46_10", + "CMT_TOP_IMUX46_10" + ], + [ + "CMT_FIFO_MONITOR_N_4", + "CMT_TOP_MONITOR_N_4" + ], + [ + "CMT_FIFO_WW4A3_10", + "CMT_TOP_WW4A3_10" + ], + [ + "CMT_FIFO_LH3_11", + "CMT_TOP_LH3_11" + ], + [ + "CMT_FIFO_SW4A2_11", + "CMT_TOP_SW4A2_11" + ], + [ + "CMT_FIFO_L_IMUX33_3", + "CMT_TOP_IMUX33_3" + ], + [ + "CMT_FIFO_WR1END3_3", + "CMT_TOP_WR1END3_3" + ], + [ + "CMT_FIFO_WR1END2_4", + "CMT_TOP_WR1END2_4" + ], + [ + "CMT_FIFO_WW4B2_5", + "CMT_TOP_WW4B2_5" + ], + [ + "CMT_FIFO_L_FAN7_2", + "CMT_TOP_FAN7_2" + ], + [ + "CMT_FIFO_NW2A1_1", + "CMT_TOP_NW2A1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_1", + "CMT_TOP_LOGIC_OUTS_L_B12_1" + ], + [ + "CMT_FIFO_NW4A2_10", + "CMT_TOP_NW4A2_10" + ], + [ + "CMT_FIFO_WL1END2_5", + "CMT_TOP_WL1END2_5" + ], + [ + "CMT_FIFO_L_CLK0_7", + "CMT_TOP_CLK0_7" + ], + [ + "CMT_FIFO_L_IMUX28_2", + "CMT_TOP_IMUX28_2" + ], + [ + "CMT_FIFO_EL1BEG2_11", + "CMT_TOP_EL1BEG2_11" + ], + [ + "CMT_FIFO_WW4END3_10", + "CMT_TOP_WW4END3_10" + ], + [ + "CMT_FIFO_EE2BEG3_10", + "CMT_TOP_EE2BEG3_10" + ], + [ + "CMT_FIFO_ER1BEG2_4", + "CMT_TOP_ER1BEG2_4" + ], + [ + "CMT_FIFO_WW4END1_2", + "CMT_TOP_WW4END1_2" + ], + [ + "CMT_FIFO_L_FAN1_3", + "CMT_TOP_FAN1_3" + ], + [ + "CMT_FIFO_L_BYP6_9", + "CMT_TOP_BYP6_9" + ], + [ + "CMT_FIFO_L_BYP7_9", + "CMT_TOP_BYP7_9" + ], + [ + "CMT_FIFO_SW4A0_6", + "CMT_TOP_SW4A0_6" + ], + [ + "CMT_FIFO_L_FAN0_4", + "CMT_TOP_FAN0_4" + ], + [ + "CMT_FIFO_SW4A1_7", + "CMT_TOP_SW4A1_7" + ], + [ + "CMT_FIFO_L_IMUX11_2", + "CMT_TOP_IMUX11_2" + ], + [ + "CMT_FIFO_EE2A1_0", + "CMT_TOP_EE2A1_0" + ], + [ + "CMT_FIFO_LH12_9", + "CMT_TOP_LH12_9" + ], + [ + "CMT_FIFO_LH10_10", + "CMT_TOP_LH10_10" + ], + [ + "CMT_FIFO_L_IMUX39_7", + "CMT_TOP_IMUX39_7" + ], + [ + "CMT_FIFO_L_IMUX9_9", + "CMT_TOP_IMUX9_9" + ], + [ + "CMT_FIFO_NW2A0_10", + "CMT_TOP_NW2A0_10" + ], + [ + "CMT_FIFO_WW2A1_2", + "CMT_TOP_WW2A1_2" + ], + [ + "CMT_FIFO_SE4C1_8", + "CMT_TOP_SE4C1_8" + ], + [ + "CMT_FIFO_L_IMUX45_2", + "CMT_TOP_IMUX45_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_5", + "CMT_TOP_LOGIC_OUTS_L_B18_5" + ], + [ + "CMT_FIFO_SW4END2_7", + "CMT_TOP_SW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX31_8", + "CMT_TOP_IMUX31_8" + ], + [ + "CMT_FIFO_L_FAN2_11", + "CMT_TOP_FAN2_11" + ], + [ + "CMT_FIFO_NW4END1_8", + "CMT_TOP_NW4END1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_3", + "CMT_TOP_LOGIC_OUTS_L_B1_3" + ], + [ + "CMT_FIFO_L_IMUX0_3", + "CMT_TOP_IMUX0_3" + ], + [ + "CMT_FIFO_SE4BEG3_9", + "CMT_TOP_SE4BEG3_9" + ], + [ + "CMT_FIFO_ER1BEG0_1", + "CMT_TOP_ER1BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_9", + "CMT_TOP_LOGIC_OUTS_L_B2_9" + ], + [ + "CMT_FIFO_NE4C2_3", + "CMT_TOP_NE4C2_3" + ], + [ + "CMT_FIFO_LH1_6", + "CMT_TOP_LH1_6" + ], + [ + "CMT_FIFO_L_IMUX21_7", + "CMT_TOP_IMUX21_7" + ], + [ + "CMT_FIFO_SE2A2_8", + "CMT_TOP_SE2A2_8" + ], + [ + "CMT_FIFO_WW4A2_3", + "CMT_TOP_WW4A2_3" + ], + [ + "CMT_FIFO_SE4BEG1_0", + "CMT_TOP_SE4BEG1_0" + ], + [ + "CMT_FIFO_WR1END1_5", + "CMT_TOP_WR1END1_5" + ], + [ + "CMT_FIFO_WW2END2_7", + "CMT_TOP_WW2END2_7" + ], + [ + "CMT_FIFO_L_IMUX38_8", + "CMT_TOP_IMUX38_8" + ], + [ + "CMT_FIFO_LH5_9", + "CMT_TOP_LH5_9" + ], + [ + "CMT_FIFO_L_FAN4_10", + "CMT_TOP_FAN4_10" + ], + [ + "CMT_FIFO_NW4END1_5", + "CMT_TOP_NW4END1_5" + ], + [ + "CMT_FIFO_EE2A2_11", + "CMT_TOP_EE2A2_11" + ], + [ + "CMT_FIFO_SE2A0_9", + "CMT_TOP_SE2A0_9" + ], + [ + "CMT_FIFO_WW4B3_7", + "CMT_TOP_WW4B3_7" + ], + [ + "CMT_FIFO_L_FAN3_11", + "CMT_TOP_FAN3_11" + ], + [ + "CMT_FIFO_LH5_2", + "CMT_TOP_LH5_2" + ], + [ + "CMT_FIFO_SE4BEG1_1", + "CMT_TOP_SE4BEG1_1" + ], + [ + "CMT_FIFO_LH1_4", + "CMT_TOP_LH1_4" + ], + [ + "CMT_FIFO_EL1BEG0_4", + "CMT_TOP_EL1BEG0_4" + ], + [ + "CMT_FIFO_WW4B1_5", + "CMT_TOP_WW4B1_5" + ], + [ + "CMT_FIFO_LH7_2", + "CMT_TOP_LH7_2" + ], + [ + "CMT_FIFO_L_IMUX5_11", + "CMT_TOP_IMUX5_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_5", + "CMT_TOP_LOGIC_OUTS_L_B12_5" + ], + [ + "CMT_FIFO_EE4B0_4", + "CMT_TOP_EE4B0_4" + ], + [ + "CMT_FIFO_EE2BEG0_2", + "CMT_TOP_EE2BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX44_1", + "CMT_TOP_IMUX44_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_8", + "CMT_TOP_LOGIC_OUTS_L_B0_8" + ], + [ + "CMT_FIFO_L_IMUX13_10", + "CMT_TOP_IMUX13_10" + ], + [ + "CMT_FIFO_NE2A3_4", + "CMT_TOP_NE2A3_4" + ], + [ + "CMT_FIFO_ER1BEG2_5", + "CMT_TOP_ER1BEG2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_3", + "CMT_TOP_LOGIC_OUTS_L_B22_3" + ], + [ + "CMT_FIFO_EE4A3_6", + "CMT_TOP_EE4A3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_2", + "CMT_TOP_LOGIC_OUTS_L_B3_2" + ], + [ + "CMT_FIFO_L_FAN1_2", + "CMT_TOP_FAN1_2" + ], + [ + "CMT_FIFO_L_PHASER_RDCLK", + "CMT_R_PHASER_OUT_C_RDCLK_FIFO" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "CMT_TOP_OCLKDIV_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_8", + "CMT_TOP_LOGIC_OUTS_L_B10_8" + ], + [ + "CMT_FIFO_WW2END2_0", + "CMT_TOP_WW2END2_0" + ], + [ + "CMT_FIFO_NE4C2_8", + "CMT_TOP_NE4C2_8" + ], + [ + "CMT_FIFO_LH1_5", + "CMT_TOP_LH1_5" + ], + [ + "CMT_FIFO_NW2A3_9", + "CMT_TOP_NW2A3_9" + ], + [ + "CMT_FIFO_SE4BEG0_0", + "CMT_TOP_SE4BEG0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_9", + "CMT_TOP_LOGIC_OUTS_L_B9_9" + ], + [ + "CMT_FIFO_L_BYP0_5", + "CMT_TOP_BYP0_5" + ], + [ + "CMT_FIFO_L_IMUX27_3", + "CMT_TOP_IMUX27_3" + ], + [ + "CMT_FIFO_L_IMUX16_0", + "CMT_TOP_IMUX16_0" + ], + [ + "CMT_FIFO_NW4END2_2", + "CMT_TOP_NW4END2_2" + ], + [ + "CMT_FIFO_SW4A1_4", + "CMT_TOP_SW4A1_4" + ], + [ + "CMT_FIFO_WW4B3_11", + "CMT_TOP_WW4B3_11" + ], + [ + "CMT_FIFO_L_IMUX15_4", + "CMT_TOP_IMUX15_4" + ], + [ + "CMT_FIFO_WR1END2_3", + "CMT_TOP_WR1END2_3" + ], + [ + "CMT_FIFO_NW4END2_10", + "CMT_TOP_NW4END2_10" + ], + [ + "CMT_FIFO_WW4END3_9", + "CMT_TOP_WW4END3_9" + ], + [ + "CMT_FIFO_L_IMUX18_8", + "CMT_TOP_IMUX18_8" + ], + [ + "CMT_FIFO_L_FAN4_8", + "CMT_TOP_FAN4_8" + ], + [ + "CMT_FIFO_WW4A2_8", + "CMT_TOP_WW4A2_8" + ], + [ + "CMT_FIFO_L_IMUX35_4", + "CMT_TOP_IMUX35_4" + ], + [ + "CMT_FIFO_L_IMUX19_10", + "CMT_TOP_IMUX19_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_1", + "CMT_TOP_LOGIC_OUTS_L_B7_1" + ], + [ + "CMT_FIFO_L_IMUX22_0", + "CMT_TOP_IMUX22_0" + ], + [ + "CMT_FIFO_EE4B1_3", + "CMT_TOP_EE4B1_3" + ], + [ + "CMT_FIFO_NW2A1_10", + "CMT_TOP_NW2A1_10" + ], + [ + "CMT_FIFO_SE2A3_0", + "CMT_TOP_SE2A3_0" + ], + [ + "CMT_FIFO_SW4A0_9", + "CMT_TOP_SW4A0_9" + ], + [ + "CMT_FIFO_EE4A2_4", + "CMT_TOP_EE4A2_4" + ], + [ + "CMT_FIFO_EE2BEG0_7", + "CMT_TOP_EE2BEG0_7" + ], + [ + "CMT_FIFO_LH4_1", + "CMT_TOP_LH4_1" + ], + [ + "CMT_FIFO_L_IMUX8_6", + "CMT_TOP_IMUX8_6" + ], + [ + "CMT_FIFO_L_BYP1_3", + "CMT_TOP_BYP1_3" + ], + [ + "CMT_FIFO_L_FAN0_5", + "CMT_TOP_FAN0_5" + ], + [ + "CMT_FIFO_L_IMUX23_9", + "CMT_TOP_IMUX23_9" + ], + [ + "CMT_FIFO_EE4C2_6", + "CMT_TOP_EE4C2_6" + ], + [ + "CMT_FIFO_NW4END2_7", + "CMT_TOP_NW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX22_5", + "CMT_TOP_IMUX22_5" + ], + [ + "CMT_FIFO_EE2BEG0_9", + "CMT_TOP_EE2BEG0_9" + ], + [ + "CMT_FIFO_EE4B3_0", + "CMT_TOP_EE4B3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_5", + "CMT_TOP_LOGIC_OUTS_L_B7_5" + ], + [ + "CMT_FIFO_L_IMUX15_8", + "CMT_TOP_IMUX15_8" + ], + [ + "CMT_FIFO_NE4C1_3", + "CMT_TOP_NE4C1_3" + ], + [ + "CMT_FIFO_NE4BEG1_2", + "CMT_TOP_NE4BEG1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_7", + "CMT_TOP_LOGIC_OUTS_L_B19_7" + ], + [ + "CMT_FIFO_NW2A2_9", + "CMT_TOP_NW2A2_9" + ], + [ + "CMT_FIFO_L_PHASER_WRENABLE", + "CMT_PHASER_IN_C_WRENABLE_FIFO" + ], + [ + "CMT_FIFO_SW2A1_7", + "CMT_TOP_SW2A1_7" + ], + [ + "CMT_FIFO_L_IMUX1_8", + "CMT_TOP_IMUX1_8" + ], + [ + "CMT_FIFO_L_IMUX30_5", + "CMT_TOP_IMUX30_5" + ], + [ + "CMT_FIFO_L_IMUX39_11", + "CMT_TOP_IMUX39_11" + ], + [ + "CMT_FIFO_SE4BEG2_6", + "CMT_TOP_SE4BEG2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_2", + "CMT_TOP_LOGIC_OUTS_L_B1_2" + ], + [ + "CMT_FIFO_LH7_9", + "CMT_TOP_LH7_9" + ], + [ + "CMT_FIFO_EE4C0_2", + "CMT_TOP_EE4C0_2" + ], + [ + "CMT_FIFO_L_IMUX46_1", + "CMT_TOP_IMUX46_1" + ], + [ + "CMT_FIFO_SW2A3_6", + "CMT_TOP_SW2A3_6" + ], + [ + "CMT_FIFO_NW4END3_4", + "CMT_TOP_NW4END3_4" + ], + [ + "CMT_FIFO_L_BYP2_6", + "CMT_TOP_BYP2_6" + ], + [ + "CMT_FIFO_L_CLK1_3", + "CMT_TOP_CLK1_3" + ], + [ + "CMT_FIFO_L_CLK0_8", + "CMT_TOP_CLK0_8" + ], + [ + "CMT_FIFO_SW2A1_8", + "CMT_TOP_SW2A1_8" + ], + [ + "CMT_FIFO_WW2END1_3", + "CMT_TOP_WW2END1_3" + ], + [ + "CMT_FIFO_EE4BEG1_10", + "CMT_TOP_EE4BEG1_10" + ], + [ + "CMT_FIFO_WW2END1_10", + "CMT_TOP_WW2END1_10" + ], + [ + "CMT_FIFO_SE2A0_7", + "CMT_TOP_SE2A0_7" + ], + [ + "CMT_FIFO_NE4C3_4", + "CMT_TOP_NE4C3_4" + ], + [ + "CMT_FIFO_SW4END1_6", + "CMT_TOP_SW4END1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_0", + "CMT_TOP_LOGIC_OUTS_L_B18_0" + ], + [ + "CMT_FIFO_WW2END3_2", + "CMT_TOP_WW2END3_2" + ], + [ + "CMT_FIFO_EE2A1_1", + "CMT_TOP_EE2A1_1" + ], + [ + "CMT_FIFO_L_FAN1_1", + "CMT_TOP_FAN1_1" + ], + [ + "CMT_FIFO_LH9_10", + "CMT_TOP_LH9_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_7", + "CMT_TOP_LOGIC_OUTS_L_B13_7" + ], + [ + "CMT_FIFO_L_IMUX18_10", + "CMT_TOP_IMUX18_10" + ], + [ + "CMT_FIFO_L_IMUX10_9", + "CMT_TOP_IMUX10_9" + ], + [ + "CMT_FIFO_WW4B2_9", + "CMT_TOP_WW4B2_9" + ], + [ + "CMT_FIFO_L_BYP7_6", + "CMT_TOP_BYP7_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_8", + "CMT_TOP_LOGIC_OUTS_L_B22_8" + ], + [ + "CMT_FIFO_SE4BEG0_3", + "CMT_TOP_SE4BEG0_3" + ], + [ + "CMT_FIFO_LH7_1", + "CMT_TOP_LH7_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_8", + "CMT_TOP_LOGIC_OUTS_L_B4_8" + ], + [ + "CMT_FIFO_L_IMUX29_2", + "CMT_TOP_IMUX29_2" + ], + [ + "CMT_FIFO_NE4BEG1_4", + "CMT_TOP_NE4BEG1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_1", + "CMT_TOP_LOGIC_OUTS_L_B16_1" + ], + [ + "CMT_FIFO_WW4END0_0", + "CMT_TOP_WW4END0_0" + ], + [ + "CMT_FIFO_NW4END1_6", + "CMT_TOP_NW4END1_6" + ], + [ + "CMT_FIFO_LH8_2", + "CMT_TOP_LH8_2" + ], + [ + "CMT_FIFO_NW4A1_2", + "CMT_TOP_NW4A1_2" + ], + [ + "CMT_FIFO_WL1END0_5", + "CMT_TOP_WL1END0_5" + ], + [ + "CMT_FIFO_SE2A2_1", + "CMT_TOP_SE2A2_1" + ], + [ + "CMT_FIFO_NE2A0_4", + "CMT_TOP_NE2A0_4" + ], + [ + "CMT_FIFO_L_IMUX18_11", + "CMT_TOP_IMUX18_11" + ], + [ + "CMT_FIFO_L_IMUX25_7", + "CMT_TOP_IMUX25_7" + ], + [ + "CMT_FIFO_NW4END0_4", + "CMT_TOP_NW4END0_4" + ], + [ + "CMT_FIFO_WL1END1_8", + "CMT_TOP_WL1END1_8" + ], + [ + "CMT_FIFO_EE4B2_5", + "CMT_TOP_EE4B2_5" + ], + [ + "CMT_FIFO_NE4BEG0_0", + "CMT_TOP_NE4BEG0_0" + ], + [ + "CMT_FIFO_SW4END1_7", + "CMT_TOP_SW4END1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_6", + "CMT_TOP_LOGIC_OUTS_L_B10_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_6", + "CMT_TOP_LOGIC_OUTS_L_B14_6" + ], + [ + "CMT_FIFO_NE4BEG1_3", + "CMT_TOP_NE4BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX20_2", + "CMT_TOP_IMUX20_2" + ], + [ + "CMT_FIFO_SE4BEG0_5", + "CMT_TOP_SE4BEG0_5" + ], + [ + "CMT_FIFO_NW4END0_2", + "CMT_TOP_NW4END0_2" + ], + [ + "CMT_FIFO_NW4A2_6", + "CMT_TOP_NW4A2_6" + ], + [ + "CMT_FIFO_WW2A3_10", + "CMT_TOP_WW2A3_10" + ], + [ + "CMT_FIFO_L_IMUX40_7", + "CMT_TOP_IMUX40_7" + ], + [ + "CMT_FIFO_LH8_11", + "CMT_TOP_LH8_11" + ], + [ + "CMT_FIFO_L_IMUX19_2", + "CMT_TOP_IMUX19_2" + ], + [ + "CMT_FIFO_WL1END3_6", + "CMT_TOP_WL1END3_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "CMT_TOP_OCLK_5" + ], + [ + "CMT_FIFO_L_IMUX16_8", + "CMT_TOP_IMUX16_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_8", + "CMT_TOP_LOGIC_OUTS_L_B12_8" + ], + [ + "CMT_FIFO_EE4BEG0_1", + "CMT_TOP_EE4BEG0_1" + ], + [ + "CMT_FIFO_WR1END1_6", + "CMT_TOP_WR1END1_6" + ], + [ + "CMT_FIFO_NE2A2_3", + "CMT_TOP_NE2A2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_6", + "CMT_TOP_LOGIC_OUTS_L_B4_6" + ], + [ + "CMT_FIFO_WW4END1_5", + "CMT_TOP_WW4END1_5" + ], + [ + "CMT_FIFO_L_IMUX2_8", + "CMT_TOP_IMUX2_8" + ], + [ + "CMT_FIFO_NW4A2_9", + "CMT_TOP_NW4A2_9" + ], + [ + "CMT_FIFO_EL1BEG2_2", + "CMT_TOP_EL1BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX4_0", + "CMT_TOP_IMUX4_0" + ], + [ + "CMT_FIFO_EE4A1_7", + "CMT_TOP_EE4A1_7" + ], + [ + "CMT_FIFO_L_IMUX35_1", + "CMT_TOP_IMUX35_1" + ], + [ + "CMT_FIFO_WL1END2_7", + "CMT_TOP_WL1END2_7" + ], + [ + "CMT_FIFO_LH1_3", + "CMT_TOP_LH1_3" + ], + [ + "CMT_FIFO_L_FAN5_3", + "CMT_TOP_FAN5_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_1", + "CMT_TOP_LOGIC_OUTS_L_B2_1" + ], + [ + "CMT_FIFO_L_IMUX11_8", + "CMT_TOP_IMUX11_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "CMT_TOP_ICLKDIV_4" + ], + [ + "CMT_FIFO_EE4B0_7", + "CMT_TOP_EE4B0_7" + ], + [ + "CMT_FIFO_WW4A0_9", + "CMT_TOP_WW4A0_9" + ], + [ + "CMT_FIFO_L_IMUX40_0", + "CMT_TOP_IMUX40_0" + ], + [ + "CMT_FIFO_L_CTRL0_5", + "CMT_TOP_CTRL0_5" + ], + [ + "CMT_FIFO_L_BYP2_2", + "CMT_TOP_BYP2_2" + ], + [ + "CMT_FIFO_L_IMUX19_0", + "CMT_TOP_IMUX19_0" + ], + [ + "CMT_FIFO_WR1END3_0", + "CMT_TOP_WR1END3_0" + ], + [ + "CMT_FIFO_EL1BEG0_5", + "CMT_TOP_EL1BEG0_5" + ], + [ + "CMT_FIFO_EE4B1_10", + "CMT_TOP_EE4B1_10" + ], + [ + "CMT_FIFO_EE4A1_3", + "CMT_TOP_EE4A1_3" + ], + [ + "CMT_FIFO_EE4BEG3_10", + "CMT_TOP_EE4BEG3_10" + ], + [ + "CMT_FIFO_L_PHASER_WRCLK", + "CMT_R_PHASER_IN_C_WRCLK_FIFO" + ], + [ + "CMT_FIFO_EE2A1_3", + "CMT_TOP_EE2A1_3" + ], + [ + "CMT_FIFO_L_BYP6_0", + "CMT_TOP_BYP6_0" + ], + [ + "CMT_FIFO_NE4BEG2_9", + "CMT_TOP_NE4BEG2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_11", + "CMT_TOP_LOGIC_OUTS_L_B0_11" + ], + [ + "CMT_FIFO_SW4END2_0", + "CMT_TOP_SW4END2_0" + ], + [ + "CMT_FIFO_L_IMUX33_8", + "CMT_TOP_IMUX33_8" + ], + [ + "CMT_FIFO_SW4END3_5", + "CMT_TOP_SW4END3_5" + ], + [ + "CMT_FIFO_L_IMUX24_9", + "CMT_TOP_IMUX24_9" + ], + [ + "CMT_FIFO_SW2A3_11", + "CMT_TOP_SW2A3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_10", + "CMT_TOP_LOGIC_OUTS_L_B3_10" + ], + [ + "CMT_FIFO_L_IMUX37_4", + "CMT_TOP_IMUX37_4" + ], + [ + "CMT_FIFO_NW4A0_0", + "CMT_TOP_NW4A0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_8", + "CMT_TOP_LOGIC_OUTS_L_B9_8" + ], + [ + "CMT_FIFO_LH8_10", + "CMT_TOP_LH8_10" + ], + [ + "CMT_FIFO_NE4C2_11", + "CMT_TOP_NE4C2_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "CMT_TOP_ICLKDIV_8" + ], + [ + "CMT_FIFO_WW4B1_3", + "CMT_TOP_WW4B1_3" + ], + [ + "CMT_FIFO_WW4B0_1", + "CMT_TOP_WW4B0_1" + ], + [ + "CMT_FIFO_L_IMUX6_1", + "CMT_TOP_IMUX6_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_11", + "CMT_TOP_LOGIC_OUTS_L_B8_11" + ], + [ + "CMT_FIFO_WL1END1_9", + "CMT_TOP_WL1END1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_5", + "CMT_TOP_LOGIC_OUTS_L_B6_5" + ], + [ + "CMT_FIFO_L_IMUX20_1", + "CMT_TOP_IMUX20_1" + ], + [ + "CMT_FIFO_L_IMUX43_3", + "CMT_TOP_IMUX43_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_3", + "CMT_TOP_LOGIC_OUTS_L_B2_3" + ], + [ + "CMT_FIFO_L_FAN7_0", + "CMT_TOP_FAN7_0" + ], + [ + "CMT_FIFO_L_BYP6_10", + "CMT_TOP_BYP6_10" + ], + [ + "CMT_FIFO_EE4B0_6", + "CMT_TOP_EE4B0_6" + ], + [ + "CMT_FIFO_EE4BEG1_6", + "CMT_TOP_EE4BEG1_6" + ], + [ + "CMT_FIFO_EE2A2_10", + "CMT_TOP_EE2A2_10" + ], + [ + "CMT_FIFO_L_IMUX28_5", + "CMT_TOP_IMUX28_5" + ], + [ + "CMT_FIFO_L_IMUX20_3", + "CMT_TOP_IMUX20_3" + ], + [ + "CMT_FIFO_SE4BEG2_3", + "CMT_TOP_SE4BEG2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_1", + "CMT_TOP_LOGIC_OUTS_L_B6_1" + ], + [ + "CMT_FIFO_L_CLK0_2", + "CMT_TOP_CLK0_2" + ], + [ + "CMT_FIFO_SW4END2_1", + "CMT_TOP_SW4END2_1" + ], + [ + "CMT_FIFO_EE4A3_11", + "CMT_TOP_EE4A3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_7", + "CMT_TOP_LOGIC_OUTS_L_B6_7" + ], + [ + "CMT_FIFO_WL1END1_10", + "CMT_TOP_WL1END1_10" + ], + [ + "CMT_FIFO_LH2_11", + "CMT_TOP_LH2_11" + ], + [ + "CMT_FIFO_EL1BEG1_6", + "CMT_TOP_EL1BEG1_6" + ], + [ + "CMT_FIFO_NE4C1_10", + "CMT_TOP_NE4C1_10" + ], + [ + "CMT_FIFO_NE4C2_4", + "CMT_TOP_NE4C2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_4", + "CMT_TOP_LOGIC_OUTS_L_B3_4" + ], + [ + "CMT_FIFO_L_IMUX24_11", + "CMT_TOP_IMUX24_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_0", + "CMT_TOP_LOGIC_OUTS_L_B23_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_3", + "CMT_TOP_LOGIC_OUTS_L_B14_3" + ], + [ + "CMT_FIFO_L_IMUX27_10", + "CMT_TOP_IMUX27_10" + ], + [ + "CMT_FIFO_EE4A2_7", + "CMT_TOP_EE4A2_7" + ], + [ + "CMT_FIFO_EE4BEG2_9", + "CMT_TOP_EE4BEG2_9" + ], + [ + "CMT_FIFO_LH9_9", + "CMT_TOP_LH9_9" + ], + [ + "CMT_FIFO_WR1END0_2", + "CMT_TOP_WR1END0_2" + ], + [ + "CMT_FIFO_L_IMUX9_11", + "CMT_TOP_IMUX9_11" + ], + [ + "CMT_FIFO_WW4B1_7", + "CMT_TOP_WW4B1_7" + ], + [ + "CMT_FIFO_L_CLK0_1", + "CMT_TOP_CLK0_1" + ], + [ + "CMT_FIFO_WW2END2_9", + "CMT_TOP_WW2END2_9" + ], + [ + "CMT_FIFO_NE4BEG3_8", + "CMT_TOP_NE4BEG3_8" + ], + [ + "CMT_FIFO_WW4A2_0", + "CMT_TOP_WW4A2_0" + ], + [ + "CMT_FIFO_WL1END2_0", + "CMT_TOP_WL1END2_0" + ], + [ + "CMT_FIFO_EE2BEG2_7", + "CMT_TOP_EE2BEG2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_9", + "CMT_TOP_LOGIC_OUTS_L_B18_9" + ], + [ + "CMT_FIFO_WW2END1_9", + "CMT_TOP_WW2END1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_10", + "CMT_TOP_LOGIC_OUTS_L_B12_10" + ], + [ + "CMT_FIFO_WW4C2_11", + "CMT_TOP_WW4C2_11" + ], + [ + "CMT_FIFO_SE4C1_9", + "CMT_TOP_SE4C1_9" + ], + [ + "CMT_FIFO_WL1END2_9", + "CMT_TOP_WL1END2_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "CMT_TOP_OCLKDIV_10" + ], + [ + "CMT_FIFO_EE2BEG1_3", + "CMT_TOP_EE2BEG1_3" + ], + [ + "CMT_FIFO_WW2END2_1", + "CMT_TOP_WW2END2_1" + ], + [ + "CMT_FIFO_L_BYP5_0", + "CMT_TOP_BYP5_0" + ], + [ + "CMT_FIFO_NE4C2_10", + "CMT_TOP_NE4C2_10" + ], + [ + "CMT_FIFO_NE4BEG0_11", + "CMT_TOP_NE4BEG0_11" + ], + [ + "CMT_FIFO_NE4C2_0", + "CMT_TOP_NE4C2_0" + ], + [ + "CMT_FIFO_SW4A2_7", + "CMT_TOP_SW4A2_7" + ], + [ + "CMT_FIFO_SW4END1_3", + "CMT_TOP_SW4END1_3" + ], + [ + "CMT_FIFO_L_IMUX9_3", + "CMT_TOP_IMUX9_3" + ], + [ + "CMT_FIFO_LH2_0", + "CMT_TOP_LH2_0" + ], + [ + "CMT_FIFO_EL1BEG2_1", + "CMT_TOP_EL1BEG2_1" + ], + [ + "CMT_FIFO_WL1END2_1", + "CMT_TOP_WL1END2_1" + ], + [ + "CMT_FIFO_EE4C3_3", + "CMT_TOP_EE4C3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_6", + "CMT_TOP_LOGIC_OUTS_L_B15_6" + ], + [ + "CMT_FIFO_L_IMUX22_1", + "CMT_TOP_IMUX22_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_5", + "CMT_TOP_LOGIC_OUTS_L_B21_5" + ], + [ + "CMT_FIFO_SW4END1_0", + "CMT_TOP_SW4END1_0" + ], + [ + "CMT_FIFO_SE4C3_5", + "CMT_TOP_SE4C3_5" + ], + [ + "CMT_FIFO_EE4BEG0_8", + "CMT_TOP_EE4BEG0_8" + ], + [ + "CMT_FIFO_L_IMUX27_7", + "CMT_TOP_IMUX27_7" + ], + [ + "CMT_FIFO_NW4END0_8", + "CMT_TOP_NW4END0_8" + ], + [ + "CMT_FIFO_L_IMUX33_1", + "CMT_TOP_IMUX33_1" + ], + [ + "CMT_FIFO_L_IMUX11_0", + "CMT_TOP_IMUX11_0" + ], + [ + "CMT_FIFO_L_FAN0_0", + "CMT_TOP_FAN0_0" + ], + [ + "CMT_FIFO_SW4END2_9", + "CMT_TOP_SW4END2_9" + ], + [ + "CMT_FIFO_L_IMUX35_10", + "CMT_TOP_IMUX35_10" + ], + [ + "CMT_FIFO_WW2END3_7", + "CMT_TOP_WW2END3_7" + ], + [ + "CMT_FIFO_EE4BEG1_3", + "CMT_TOP_EE4BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX19_3", + "CMT_TOP_IMUX19_3" + ], + [ + "CMT_FIFO_EE4B3_9", + "CMT_TOP_EE4B3_9" + ], + [ + "CMT_FIFO_LH3_3", + "CMT_TOP_LH3_3" + ], + [ + "CMT_FIFO_EE2A1_5", + "CMT_TOP_EE2A1_5" + ], + [ + "CMT_FIFO_NW2A1_5", + "CMT_TOP_NW2A1_5" + ], + [ + "CMT_FIFO_EE2A0_2", + "CMT_TOP_EE2A0_2" + ], + [ + "CMT_FIFO_SW4A2_10", + "CMT_TOP_SW4A2_10" + ], + [ + "CMT_FIFO_EE4C2_2", + "CMT_TOP_EE4C2_2" + ], + [ + "CMT_FIFO_LH2_7", + "CMT_TOP_LH2_7" + ], + [ + "CMT_FIFO_EE4BEG3_6", + "CMT_TOP_EE4BEG3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_0", + "CMT_TOP_LOGIC_OUTS_L_B17_0" + ], + [ + "CMT_FIFO_L_IMUX44_8", + "CMT_TOP_IMUX44_8" + ], + [ + "CMT_FIFO_L_IMUX23_4", + "CMT_TOP_IMUX23_4" + ], + [ + "CMT_FIFO_SE4BEG2_10", + "CMT_TOP_SE4BEG2_10" + ], + [ + "CMT_FIFO_L_IMUX30_6", + "CMT_TOP_IMUX30_6" + ], + [ + "CMT_FIFO_L_CTRL0_3", + "CMT_TOP_CTRL0_3" + ], + [ + "CMT_FIFO_WR1END3_2", + "CMT_TOP_WR1END3_2" + ], + [ + "CMT_FIFO_SW4A0_3", + "CMT_TOP_SW4A0_3" + ], + [ + "CMT_FIFO_L_IMUX22_11", + "CMT_TOP_IMUX22_11" + ], + [ + "CMT_FIFO_LH9_3", + "CMT_TOP_LH9_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_11", + "CMT_TOP_LOGIC_OUTS_L_B11_11" + ], + [ + "CMT_FIFO_L_IMUX24_5", + "CMT_TOP_IMUX24_5" + ], + [ + "CMT_FIFO_WR1END1_11", + "CMT_TOP_WR1END1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_4", + "CMT_TOP_LOGIC_OUTS_L_B10_4" + ], + [ + "CMT_FIFO_SE4C0_6", + "CMT_TOP_SE4C0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_10", + "CMT_TOP_LOGIC_OUTS_L_B9_10" + ], + [ + "CMT_FIFO_LH4_10", + "CMT_TOP_LH4_10" + ], + [ + "CMT_FIFO_L_IMUX2_1", + "CMT_TOP_IMUX2_1" + ], + [ + "CMT_FIFO_LH7_6", + "CMT_TOP_LH7_6" + ], + [ + "CMT_FIFO_L_BYP5_7", + "CMT_TOP_BYP5_7" + ], + [ + "CMT_FIFO_L_IMUX4_11", + "CMT_TOP_IMUX4_11" + ], + [ + "CMT_FIFO_L_IMUX43_5", + "CMT_TOP_IMUX43_5" + ], + [ + "CMT_FIFO_L_IMUX18_5", + "CMT_TOP_IMUX18_5" + ], + [ + "CMT_FIFO_WW4END1_9", + "CMT_TOP_WW4END1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_1", + "CMT_TOP_LOGIC_OUTS_L_B9_1" + ], + [ + "CMT_FIFO_NE4BEG2_2", + "CMT_TOP_NE4BEG2_2" + ], + [ + "CMT_FIFO_WW2A3_8", + "CMT_TOP_WW2A3_8" + ], + [ + "CMT_FIFO_EL1BEG1_4", + "CMT_TOP_EL1BEG1_4" + ], + [ + "CMT_FIFO_SE2A1_7", + "CMT_TOP_SE2A1_7" + ], + [ + "CMT_FIFO_WW2A0_1", + "CMT_TOP_WW2A0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_6", + "CMT_TOP_LOGIC_OUTS_L_B0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_10", + "CMT_TOP_LOGIC_OUTS_L_B19_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "CMT_TOP_ICLK_7" + ], + [ + "CMT_FIFO_NW4END1_3", + "CMT_TOP_NW4END1_3" + ], + [ + "CMT_FIFO_WW4C2_8", + "CMT_TOP_WW4C2_8" + ], + [ + "CMT_FIFO_NE4BEG1_11", + "CMT_TOP_NE4BEG1_11" + ], + [ + "CMT_FIFO_NE2A1_4", + "CMT_TOP_NE2A1_4" + ], + [ + "CMT_FIFO_NE4BEG0_10", + "CMT_TOP_NE4BEG0_10" + ], + [ + "CMT_FIFO_L_BYP1_4", + "CMT_TOP_BYP1_4" + ], + [ + "CMT_FIFO_EL1BEG3_3", + "CMT_TOP_EL1BEG3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_7" + ], + [ + "CMT_FIFO_NW2A2_10", + "CMT_TOP_NW2A2_10" + ], + [ + "CMT_FIFO_L_IMUX32_0", + "CMT_TOP_IMUX32_0" + ], + [ + "CMT_FIFO_SE4C0_4", + "CMT_TOP_SE4C0_4" + ], + [ + "CMT_FIFO_L_IMUX1_1", + "CMT_TOP_IMUX1_1" + ], + [ + "CMT_FIFO_L_IMUX39_10", + "CMT_TOP_IMUX39_10" + ], + [ + "CMT_FIFO_EE4C1_10", + "CMT_TOP_EE4C1_10" + ], + [ + "CMT_FIFO_L_BYP1_10", + "CMT_TOP_BYP1_10" + ], + [ + "CMT_FIFO_SE4BEG3_11", + "CMT_TOP_SE4BEG3_11" + ], + [ + "CMT_FIFO_L_IMUX47_9", + "CMT_TOP_IMUX47_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_4", + "CMT_TOP_LOGIC_OUTS_L_B4_4" + ], + [ + "CMT_FIFO_WL1END3_8", + "CMT_TOP_WL1END3_8" + ], + [ + "CMT_FIFO_L_IMUX13_11", + "CMT_TOP_IMUX13_11" + ], + [ + "CMT_FIFO_L_BYP5_8", + "CMT_TOP_BYP5_8" + ], + [ + "CMT_FIFO_NE4C3_9", + "CMT_TOP_NE4C3_9" + ], + [ + "CMT_FIFO_NE4C3_10", + "CMT_TOP_NE4C3_10" + ], + [ + "CMT_FIFO_L_IMUX26_10", + "CMT_TOP_IMUX26_10" + ], + [ + "CMT_FIFO_L_IMUX17_0", + "CMT_TOP_IMUX17_0" + ], + [ + "CMT_FIFO_L_IMUX25_9", + "CMT_TOP_IMUX25_9" + ], + [ + "CMT_FIFO_NW2A1_2", + "CMT_TOP_NW2A1_2" + ], + [ + "CMT_FIFO_L_IMUX45_11", + "CMT_TOP_IMUX45_11" + ], + [ + "CMT_FIFO_WW4C3_5", + "CMT_TOP_WW4C3_5" + ], + [ + "CMT_FIFO_WW4END2_10", + "CMT_TOP_WW4END2_10" + ], + [ + "CMT_FIFO_EE2A0_10", + "CMT_TOP_EE2A0_10" + ], + [ + "CMT_FIFO_ER1BEG0_7", + "CMT_TOP_ER1BEG0_7" + ], + [ + "CMT_FIFO_EE4BEG3_3", + "CMT_TOP_EE4BEG3_3" + ], + [ + "CMT_FIFO_L_IMUX42_1", + "CMT_TOP_IMUX42_1" + ], + [ + "CMT_FIFO_NE2A1_5", + "CMT_TOP_NE2A1_5" + ], + [ + "CMT_FIFO_L_IMUX22_2", + "CMT_TOP_IMUX22_2" + ], + [ + "CMT_FIFO_WR1END1_1", + "CMT_TOP_WR1END1_1" + ], + [ + "CMT_FIFO_EE2BEG1_8", + "CMT_TOP_EE2BEG1_8" + ], + [ + "CMT_FIFO_EL1BEG3_8", + "CMT_TOP_EL1BEG3_8" + ], + [ + "CMT_FIFO_L_IMUX19_9", + "CMT_TOP_IMUX19_9" + ], + [ + "CMT_FIFO_ER1BEG1_6", + "CMT_TOP_ER1BEG1_6" + ], + [ + "CMT_FIFO_SW2A3_5", + "CMT_TOP_SW2A3_5" + ], + [ + "CMT_FIFO_L_BYP3_6", + "CMT_TOP_BYP3_6" + ], + [ + "CMT_FIFO_ER1BEG3_1", + "CMT_TOP_ER1BEG3_1" + ], + [ + "CMT_FIFO_L_BYP4_10", + "CMT_TOP_BYP4_10" + ], + [ + "CMT_FIFO_SW4A3_9", + "CMT_TOP_SW4A3_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "CMT_TOP_OCLK_3" + ], + [ + "CMT_FIFO_L_IMUX20_10", + "CMT_TOP_IMUX20_10" + ], + [ + "CMT_FIFO_NW2A2_11", + "CMT_TOP_NW2A2_11" + ], + [ + "CMT_FIFO_L_FAN2_8", + "CMT_TOP_FAN2_8" + ], + [ + "CMT_FIFO_L_FAN0_6", + "CMT_TOP_FAN0_6" + ], + [ + "CMT_FIFO_WW2A0_11", + "CMT_TOP_WW2A0_11" + ], + [ + "CMT_FIFO_WW4A1_3", + "CMT_TOP_WW4A1_3" + ], + [ + "CMT_FIFO_L_IMUX40_4", + "CMT_TOP_IMUX40_4" + ], + [ + "CMT_FIFO_L_IMUX46_2", + "CMT_TOP_IMUX46_2" + ], + [ + "CMT_FIFO_NW4END3_9", + "CMT_TOP_NW4END3_9" + ], + [ + "CMT_FIFO_ER1BEG2_6", + "CMT_TOP_ER1BEG2_6" + ], + [ + "CMT_FIFO_EE4A3_4", + "CMT_TOP_EE4A3_4" + ], + [ + "CMT_FIFO_EE4BEG2_1", + "CMT_TOP_EE4BEG2_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_11", + "CMT_TOP_LOGIC_OUTS_L_B17_11" + ], + [ + "CMT_FIFO_WW2A3_6", + "CMT_TOP_WW2A3_6" + ], + [ + "CMT_FIFO_WW4B0_9", + "CMT_TOP_WW4B0_9" + ], + [ + "CMT_FIFO_L_IMUX43_1", + "CMT_TOP_IMUX43_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_9", + "CMT_TOP_LOGIC_OUTS_L_B11_9" + ], + [ + "CMT_FIFO_L_IMUX16_6", + "CMT_TOP_IMUX16_6" + ], + [ + "CMT_FIFO_L_IMUX44_10", + "CMT_TOP_IMUX44_10" + ], + [ + "CMT_FIFO_EE4BEG1_8", + "CMT_TOP_EE4BEG1_8" + ], + [ + "CMT_FIFO_L_IMUX4_8", + "CMT_TOP_IMUX4_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_5", + "CMT_TOP_LOGIC_OUTS_L_B0_5" + ], + [ + "CMT_FIFO_WW4A0_3", + "CMT_TOP_WW4A0_3" + ], + [ + "CMT_FIFO_ER1BEG2_11", + "CMT_TOP_ER1BEG2_11" + ], + [ + "CMT_FIFO_EE2A0_6", + "CMT_TOP_EE2A0_6" + ], + [ + "CMT_FIFO_EE4BEG2_4", + "CMT_TOP_EE4BEG2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_10", + "CMT_TOP_LOGIC_OUTS_L_B16_10" + ], + [ + "CMT_FIFO_LH2_1", + "CMT_TOP_LH2_1" + ], + [ + "CMT_FIFO_L_IMUX37_1", + "CMT_TOP_IMUX37_1" + ], + [ + "CMT_FIFO_WW4B1_1", + "CMT_TOP_WW4B1_1" + ], + [ + "CMT_FIFO_WW4B1_0", + "CMT_TOP_WW4B1_0" + ], + [ + "CMT_FIFO_NW2A3_8", + "CMT_TOP_NW2A3_8" + ], + [ + "CMT_FIFO_NW4A1_11", + "CMT_TOP_NW4A1_11" + ], + [ + "CMT_FIFO_EE4A1_10", + "CMT_TOP_EE4A1_10" + ], + [ + "CMT_FIFO_WR1END1_2", + "CMT_TOP_WR1END1_2" + ], + [ + "CMT_FIFO_WW4B0_0", + "CMT_TOP_WW4B0_0" + ], + [ + "CMT_FIFO_L_IMUX29_10", + "CMT_TOP_IMUX29_10" + ], + [ + "CMT_FIFO_WW2END1_11", + "CMT_TOP_WW2END1_11" + ], + [ + "CMT_FIFO_L_BYP2_4", + "CMT_TOP_BYP2_4" + ], + [ + "CMT_FIFO_WW4C2_6", + "CMT_TOP_WW4C2_6" + ], + [ + "CMT_FIFO_L_BYP7_2", + "CMT_TOP_BYP7_2" + ], + [ + "CMT_FIFO_L_IMUX45_0", + "CMT_TOP_IMUX45_0" + ], + [ + "CMT_FIFO_L_IMUX42_10", + "CMT_TOP_IMUX42_10" + ], + [ + "CMT_FIFO_L_CLK0_6", + "CMT_TOP_CLK0_6" + ], + [ + "CMT_FIFO_SW2A3_8", + "CMT_TOP_SW2A3_8" + ], + [ + "CMT_FIFO_NW4END1_4", + "CMT_TOP_NW4END1_4" + ], + [ + "CMT_FIFO_L_CLK1_2", + "CMT_TOP_CLK1_2" + ], + [ + "CMT_FIFO_EE2BEG3_2", + "CMT_TOP_EE2BEG3_2" + ], + [ + "CMT_FIFO_L_IMUX3_3", + "CMT_TOP_IMUX3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_9", + "CMT_TOP_LOGIC_OUTS_L_B3_9" + ], + [ + "CMT_FIFO_WW4C0_1", + "CMT_TOP_WW4C0_1" + ], + [ + "CMT_FIFO_NE2A1_1", + "CMT_TOP_NE2A1_1" + ], + [ + "CMT_FIFO_L_BYP2_9", + "CMT_TOP_BYP2_9" + ], + [ + "CMT_FIFO_WW2A1_1", + "CMT_TOP_WW2A1_1" + ], + [ + "CMT_FIFO_L_FAN0_2", + "CMT_TOP_FAN0_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "CMT_TOP_OCLK_9" + ], + [ + "CMT_FIFO_SW2A2_6", + "CMT_TOP_SW2A2_6" + ], + [ + "CMT_FIFO_L_IMUX1_7", + "CMT_TOP_IMUX1_7" + ], + [ + "CMT_FIFO_SE4BEG2_4", + "CMT_TOP_SE4BEG2_4" + ], + [ + "CMT_FIFO_NW4A2_11", + "CMT_TOP_NW4A2_11" + ], + [ + "CMT_FIFO_EE4B0_11", + "CMT_TOP_EE4B0_11" + ], + [ + "CMT_FIFO_SW4A2_8", + "CMT_TOP_SW4A2_8" + ], + [ + "CMT_FIFO_WR1END3_1", + "CMT_TOP_WR1END3_1" + ], + [ + "CMT_FIFO_L_IMUX34_8", + "CMT_TOP_IMUX34_8" + ], + [ + "CMT_FIFO_L_IMUX47_3", + "CMT_TOP_IMUX47_3" + ], + [ + "CMT_FIFO_EE4A3_5", + "CMT_TOP_EE4A3_5" + ], + [ + "CMT_FIFO_EE4A0_0", + "CMT_TOP_EE4A0_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_8", + "CMT_TOP_LOGIC_OUTS_L_B6_8" + ], + [ + "CMT_FIFO_SE4BEG1_10", + "CMT_TOP_SE4BEG1_10" + ], + [ + "CMT_FIFO_LH2_10", + "CMT_TOP_LH2_10" + ], + [ + "CMT_FIFO_SE4C2_7", + "CMT_TOP_SE4C2_7" + ], + [ + "CMT_FIFO_L_IMUX15_5", + "CMT_TOP_IMUX15_5" + ], + [ + "CMT_FIFO_EE4C3_6", + "CMT_TOP_EE4C3_6" + ], + [ + "CMT_FIFO_L_IMUX44_5", + "CMT_TOP_IMUX44_5" + ], + [ + "CMT_FIFO_WW4C0_5", + "CMT_TOP_WW4C0_5" + ], + [ + "CMT_FIFO_L_IMUX31_10", + "CMT_TOP_IMUX31_10" + ], + [ + "CMT_FIFO_EL1BEG2_0", + "CMT_TOP_EL1BEG2_0" + ], + [ + "CMT_FIFO_SE4BEG0_7", + "CMT_TOP_SE4BEG0_7" + ], + [ + "CMT_FIFO_WW4END0_3", + "CMT_TOP_WW4END0_3" + ], + [ + "CMT_FIFO_WL1END1_7", + "CMT_TOP_WL1END1_7" + ], + [ + "CMT_FIFO_MONITOR_N_2", + "CMT_TOP_MONITOR_N_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_10", + "CMT_TOP_LOGIC_OUTS_L_B14_10" + ], + [ + "CMT_FIFO_NE4BEG0_4", + "CMT_TOP_NE4BEG0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_11", + "CMT_TOP_LOGIC_OUTS_L_B12_11" + ], + [ + "CMT_FIFO_SE4BEG2_5", + "CMT_TOP_SE4BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX17_2", + "CMT_TOP_IMUX17_2" + ], + [ + "CMT_FIFO_L_IMUX16_2", + "CMT_TOP_IMUX16_2" + ], + [ + "CMT_FIFO_WW4END1_8", + "CMT_TOP_WW4END1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_0", + "CMT_TOP_LOGIC_OUTS_L_B10_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_7", + "CMT_TOP_LOGIC_OUTS_L_B1_7" + ], + [ + "CMT_FIFO_L_IMUX20_0", + "CMT_TOP_IMUX20_0" + ], + [ + "CMT_FIFO_SE2A3_9", + "CMT_TOP_SE2A3_9" + ], + [ + "CMT_FIFO_EE4C2_0", + "CMT_TOP_EE4C2_0" + ], + [ + "CMT_FIFO_L_FAN3_5", + "CMT_TOP_FAN3_5" + ], + [ + "CMT_FIFO_WW4B0_2", + "CMT_TOP_WW4B0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_2", + "CMT_TOP_LOGIC_OUTS_L_B9_2" + ], + [ + "CMT_FIFO_L_IMUX26_1", + "CMT_TOP_IMUX26_1" + ], + [ + "CMT_FIFO_EE4C3_1", + "CMT_TOP_EE4C3_1" + ], + [ + "CMT_FIFO_L_IMUX38_3", + "CMT_TOP_IMUX38_3" + ], + [ + "CMT_FIFO_L_IMUX36_9", + "CMT_TOP_IMUX36_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_5", + "CMT_TOP_LOGIC_OUTS_L_B1_5" + ], + [ + "CMT_FIFO_EE4C0_1", + "CMT_TOP_EE4C0_1" + ], + [ + "CMT_FIFO_L_IMUX2_7", + "CMT_TOP_IMUX2_7" + ], + [ + "CMT_FIFO_NE4BEG1_8", + "CMT_TOP_NE4BEG1_8" + ], + [ + "CMT_FIFO_WW2A1_11", + "CMT_TOP_WW2A1_11" + ], + [ + "CMT_FIFO_L_CLK1_5", + "CMT_TOP_CLK1_5" + ], + [ + "CMT_FIFO_L_FAN0_3", + "CMT_TOP_FAN0_3" + ], + [ + "CMT_FIFO_WW4C3_7", + "CMT_TOP_WW4C3_7" + ], + [ + "CMT_FIFO_EE2BEG2_10", + "CMT_TOP_EE2BEG2_10" + ], + [ + "CMT_FIFO_SE4C2_5", + "CMT_TOP_SE4C2_5" + ], + [ + "CMT_FIFO_SW2A0_4", + "CMT_TOP_SW2A0_4" + ], + [ + "CMT_FIFO_L_IMUX2_3", + "CMT_TOP_IMUX2_3" + ], + [ + "CMT_FIFO_WR1END2_8", + "CMT_TOP_WR1END2_8" + ], + [ + "CMT_FIFO_L_IMUX8_0", + "CMT_TOP_IMUX8_0" + ], + [ + "CMT_FIFO_EE2BEG1_2", + "CMT_TOP_EE2BEG1_2" + ], + [ + "CMT_FIFO_WW2END0_3", + "CMT_TOP_WW2END0_3" + ], + [ + "CMT_FIFO_EE4A0_2", + "CMT_TOP_EE4A0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_2", + "CMT_TOP_LOGIC_OUTS_L_B10_2" + ], + [ + "CMT_FIFO_WW2END0_8", + "CMT_TOP_WW2END0_8" + ], + [ + "CMT_FIFO_L_FAN1_8", + "CMT_TOP_FAN1_8" + ], + [ + "CMT_FIFO_L_IMUX40_9", + "CMT_TOP_IMUX40_9" + ], + [ + "CMT_FIFO_WW2END3_9", + "CMT_TOP_WW2END3_9" + ], + [ + "CMT_FIFO_EE4C1_6", + "CMT_TOP_EE4C1_6" + ], + [ + "CMT_FIFO_L_BYP5_5", + "CMT_TOP_BYP5_5" + ], + [ + "CMT_FIFO_LH5_8", + "CMT_TOP_LH5_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_9", + "CMT_TOP_LOGIC_OUTS_L_B14_9" + ], + [ + "CMT_FIFO_L_FAN6_11", + "CMT_TOP_FAN6_11" + ], + [ + "CMT_FIFO_WW2A2_3", + "CMT_TOP_WW2A2_3" + ], + [ + "CMT_FIFO_WW2A3_3", + "CMT_TOP_WW2A3_3" + ], + [ + "CMT_FIFO_L_IMUX4_2", + "CMT_TOP_IMUX4_2" + ], + [ + "CMT_FIFO_L_IMUX36_4", + "CMT_TOP_IMUX36_4" + ], + [ + "CMT_FIFO_LH1_11", + "CMT_TOP_LH1_11" + ], + [ + "CMT_FIFO_WW4B3_0", + "CMT_TOP_WW4B3_0" + ], + [ + "CMT_FIFO_EE4B3_7", + "CMT_TOP_EE4B3_7" + ], + [ + "CMT_FIFO_LH5_11", + "CMT_TOP_LH5_11" + ], + [ + "CMT_FIFO_NW2A1_11", + "CMT_TOP_NW2A1_11" + ], + [ + "CMT_FIFO_SE4C2_9", + "CMT_TOP_SE4C2_9" + ], + [ + "CMT_FIFO_L_CTRL1_11", + "CMT_TOP_CTRL1_11" + ], + [ + "CMT_FIFO_SW2A0_5", + "CMT_TOP_SW2A0_5" + ], + [ + "CMT_FIFO_LH7_10", + "CMT_TOP_LH7_10" + ], + [ + "CMT_FIFO_L_IMUX25_0", + "CMT_TOP_IMUX25_0" + ], + [ + "CMT_FIFO_L_FAN2_5", + "CMT_TOP_FAN2_5" + ], + [ + "CMT_FIFO_NE4BEG3_2", + "CMT_TOP_NE4BEG3_2" + ], + [ + "CMT_FIFO_EE4B2_4", + "CMT_TOP_EE4B2_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_4", + "CMT_TOP_LOGIC_OUTS_L_B19_4" + ], + [ + "CMT_FIFO_NE2A1_0", + "CMT_TOP_NE2A1_0" + ], + [ + "CMT_FIFO_WW2A0_6", + "CMT_TOP_WW2A0_6" + ], + [ + "CMT_FIFO_L_IMUX19_11", + "CMT_TOP_IMUX19_11" + ], + [ + "CMT_FIFO_L_IMUX3_5", + "CMT_TOP_IMUX3_5" + ], + [ + "CMT_FIFO_L_BYP7_1", + "CMT_TOP_BYP7_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_8", + "CMT_TOP_LOGIC_OUTS_L_B7_8" + ], + [ + "CMT_FIFO_WW4C3_2", + "CMT_TOP_WW4C3_2" + ], + [ + "CMT_FIFO_L_IMUX18_0", + "CMT_TOP_IMUX18_0" + ], + [ + "CMT_FIFO_LH2_9", + "CMT_TOP_LH2_9" + ], + [ + "CMT_FIFO_L_IMUX46_6", + "CMT_TOP_IMUX46_6" + ], + [ + "CMT_FIFO_L_IMUX29_9", + "CMT_TOP_IMUX29_9" + ], + [ + "CMT_FIFO_SE4C1_2", + "CMT_TOP_SE4C1_2" + ], + [ + "CMT_FIFO_L_IMUX24_6", + "CMT_TOP_IMUX24_6" + ], + [ + "CMT_FIFO_EE4A0_9", + "CMT_TOP_EE4A0_9" + ], + [ + "CMT_FIFO_SE2A3_3", + "CMT_TOP_SE2A3_3" + ], + [ + "CMT_FIFO_L_IMUX46_9", + "CMT_TOP_IMUX46_9" + ], + [ + "CMT_FIFO_NE4C0_5", + "CMT_TOP_NE4C0_5" + ], + [ + "CMT_FIFO_WW2A0_4", + "CMT_TOP_WW2A0_4" + ], + [ + "CMT_FIFO_L_FAN7_6", + "CMT_TOP_FAN7_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_8", + "CMT_TOP_LOGIC_OUTS_L_B13_8" + ], + [ + "CMT_FIFO_L_IMUX6_10", + "CMT_TOP_IMUX6_10" + ], + [ + "CMT_FIFO_SW2A1_4", + "CMT_TOP_SW2A1_4" + ], + [ + "CMT_FIFO_NE4BEG2_1", + "CMT_TOP_NE4BEG2_1" + ], + [ + "CMT_FIFO_ER1BEG0_8", + "CMT_TOP_ER1BEG0_8" + ], + [ + "CMT_FIFO_L_BYP1_9", + "CMT_TOP_BYP1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_2", + "CMT_TOP_LOGIC_OUTS_L_B22_2" + ], + [ + "CMT_FIFO_L_IMUX26_9", + "CMT_TOP_IMUX26_9" + ], + [ + "CMT_FIFO_WW4B1_8", + "CMT_TOP_WW4B1_8" + ], + [ + "CMT_FIFO_L_FAN6_0", + "CMT_TOP_FAN6_0" + ], + [ + "CMT_FIFO_L_IMUX20_4", + "CMT_TOP_IMUX20_4" + ], + [ + "CMT_FIFO_NW2A3_2", + "CMT_TOP_NW2A3_2" + ], + [ + "CMT_FIFO_NE4C1_11", + "CMT_TOP_NE4C1_11" + ], + [ + "CMT_FIFO_L_FAN1_11", + "CMT_TOP_FAN1_11" + ], + [ + "CMT_FIFO_LH10_3", + "CMT_TOP_LH10_3" + ], + [ + "CMT_FIFO_SE4C0_11", + "CMT_TOP_SE4C0_11" + ], + [ + "CMT_FIFO_L_FAN4_7", + "CMT_TOP_FAN4_7" + ], + [ + "CMT_FIFO_L_FAN2_3", + "CMT_TOP_FAN2_3" + ], + [ + "CMT_FIFO_NW4END3_2", + "CMT_TOP_NW4END3_2" + ], + [ + "CMT_FIFO_WW4A3_11", + "CMT_TOP_WW4A3_11" + ], + [ + "CMT_FIFO_L_IMUX25_8", + "CMT_TOP_IMUX25_8" + ], + [ + "CMT_FIFO_L_BYP5_2", + "CMT_TOP_BYP5_2" + ], + [ + "CMT_FIFO_EE4A1_9", + "CMT_TOP_EE4A1_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "CMT_TOP_OCLKDIV_3" + ], + [ + "CMT_FIFO_SE2A0_0", + "CMT_TOP_SE2A0_0" + ], + [ + "CMT_FIFO_L_CLK0_4", + "CMT_TOP_CLK0_4" + ], + [ + "CMT_FIFO_L_IMUX19_8", + "CMT_TOP_IMUX19_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_9", + "CMT_TOP_LOGIC_OUTS_L_B1_9" + ], + [ + "CMT_FIFO_NW2A0_4", + "CMT_TOP_NW2A0_4" + ], + [ + "CMT_FIFO_SE4C3_2", + "CMT_TOP_SE4C3_2" + ], + [ + "CMT_FIFO_SE2A1_5", + "CMT_TOP_SE2A1_5" + ], + [ + "CMT_FIFO_EE4BEG1_0", + "CMT_TOP_EE4BEG1_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_8", + "CMT_TOP_LOGIC_OUTS_L_B20_8" + ], + [ + "CMT_FIFO_L_IMUX45_5", + "CMT_TOP_IMUX45_5" + ], + [ + "CMT_FIFO_EL1BEG1_2", + "CMT_TOP_EL1BEG1_2" + ], + [ + "CMT_FIFO_L_FAN0_7", + "CMT_TOP_FAN0_7" + ], + [ + "CMT_FIFO_EE4B1_1", + "CMT_TOP_EE4B1_1" + ], + [ + "CMT_FIFO_L_IMUX21_5", + "CMT_TOP_IMUX21_5" + ], + [ + "CMT_FIFO_EL1BEG3_5", + "CMT_TOP_EL1BEG3_5" + ], + [ + "CMT_FIFO_EE4BEG1_2", + "CMT_TOP_EE4BEG1_2" + ], + [ + "CMT_FIFO_EE4BEG2_2", + "CMT_TOP_EE4BEG2_2" + ], + [ + "CMT_FIFO_LH8_6", + "CMT_TOP_LH8_6" + ], + [ + "CMT_FIFO_L_IMUX24_2", + "CMT_TOP_IMUX24_2" + ], + [ + "CMT_FIFO_L_IMUX32_4", + "CMT_TOP_IMUX32_4" + ], + [ + "CMT_FIFO_ER1BEG0_2", + "CMT_TOP_ER1BEG0_2" + ], + [ + "CMT_FIFO_EE4C3_5", + "CMT_TOP_EE4C3_5" + ], + [ + "CMT_FIFO_L_IMUX41_11", + "CMT_TOP_IMUX41_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_10", + "CMT_TOP_LOGIC_OUTS_L_B8_10" + ], + [ + "CMT_FIFO_WW4B3_6", + "CMT_TOP_WW4B3_6" + ], + [ + "CMT_FIFO_NW2A1_6", + "CMT_TOP_NW2A1_6" + ], + [ + "CMT_FIFO_L_BYP1_11", + "CMT_TOP_BYP1_11" + ], + [ + "CMT_FIFO_WW2A3_2", + "CMT_TOP_WW2A3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_2", + "CMT_TOP_LOGIC_OUTS_L_B11_2" + ], + [ + "CMT_FIFO_L_IMUX45_8", + "CMT_TOP_IMUX45_8" + ], + [ + "CMT_FIFO_WW2A1_10", + "CMT_TOP_WW2A1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_9", + "CMT_TOP_LOGIC_OUTS_L_B10_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_7", + "CMT_TOP_LOGIC_OUTS_L_B4_7" + ], + [ + "CMT_FIFO_L_IMUX6_6", + "CMT_TOP_IMUX6_6" + ], + [ + "CMT_FIFO_L_IMUX12_10", + "CMT_TOP_IMUX12_10" + ], + [ + "CMT_FIFO_L_CTRL0_0", + "CMT_TOP_CTRL0_0" + ], + [ + "CMT_FIFO_SW4A0_11", + "CMT_TOP_SW4A0_11" + ], + [ + "CMT_FIFO_L_FAN5_4", + "CMT_TOP_FAN5_4" + ], + [ + "CMT_FIFO_WW2END1_7", + "CMT_TOP_WW2END1_7" + ], + [ + "CMT_FIFO_WW2END0_0", + "CMT_TOP_WW2END0_0" + ], + [ + "CMT_FIFO_EE4B0_0", + "CMT_TOP_EE4B0_0" + ], + [ + "CMT_FIFO_NW4A1_6", + "CMT_TOP_NW4A1_6" + ], + [ + "CMT_FIFO_EE2BEG0_5", + "CMT_TOP_EE2BEG0_5" + ], + [ + "CMT_FIFO_SW4END0_5", + "CMT_TOP_SW4END0_5" + ], + [ + "CMT_FIFO_SE4BEG2_7", + "CMT_TOP_SE4BEG2_7" + ], + [ + "CMT_FIFO_L_CTRL1_7", + "CMT_TOP_CTRL1_7" + ], + [ + "CMT_FIFO_SW4END3_0", + "CMT_TOP_SW4END3_0" + ], + [ + "CMT_FIFO_SW4A2_1", + "CMT_TOP_SW4A2_1" + ], + [ + "CMT_FIFO_EL1BEG3_2", + "CMT_TOP_EL1BEG3_2" + ], + [ + "CMT_FIFO_SE4BEG1_11", + "CMT_TOP_SE4BEG1_11" + ], + [ + "CMT_FIFO_NW4END3_5", + "CMT_TOP_NW4END3_5" + ], + [ + "CMT_FIFO_L_IMUX16_1", + "CMT_TOP_IMUX16_1" + ], + [ + "CMT_FIFO_WW4C3_4", + "CMT_TOP_WW4C3_4" + ], + [ + "CMT_FIFO_L_FAN0_10", + "CMT_TOP_FAN0_10" + ], + [ + "CMT_FIFO_L_FAN2_1", + "CMT_TOP_FAN2_1" + ], + [ + "CMT_FIFO_L_BYP3_8", + "CMT_TOP_BYP3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_11", + "CMT_TOP_LOGIC_OUTS_L_B20_11" + ], + [ + "CMT_FIFO_L_CLK0_3", + "CMT_TOP_CLK0_3" + ], + [ + "CMT_FIFO_WW4C0_8", + "CMT_TOP_WW4C0_8" + ], + [ + "CMT_FIFO_L_IMUX31_4", + "CMT_TOP_IMUX31_4" + ], + [ + "CMT_FIFO_L_IMUX43_7", + "CMT_TOP_IMUX43_7" + ], + [ + "CMT_FIFO_SE4C0_1", + "CMT_TOP_SE4C0_1" + ], + [ + "CMT_FIFO_EE4C3_8", + "CMT_TOP_EE4C3_8" + ], + [ + "CMT_FIFO_L_IMUX31_11", + "CMT_TOP_IMUX31_11" + ], + [ + "CMT_FIFO_NW4END0_0", + "CMT_TOP_NW4END0_0" + ], + [ + "CMT_FIFO_EE4C3_10", + "CMT_TOP_EE4C3_10" + ], + [ + "CMT_FIFO_NW4A1_1", + "CMT_TOP_NW4A1_1" + ], + [ + "CMT_FIFO_LH1_8", + "CMT_TOP_LH1_8" + ], + [ + "CMT_FIFO_L_IMUX3_11", + "CMT_TOP_IMUX3_11" + ], + [ + "CMT_FIFO_WW2A0_10", + "CMT_TOP_WW2A0_10" + ], + [ + "CMT_FIFO_L_FAN4_0", + "CMT_TOP_FAN4_0" + ], + [ + "CMT_FIFO_WW2A2_6", + "CMT_TOP_WW2A2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_0", + "CMT_TOP_LOGIC_OUTS_L_B16_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_1", + "CMT_TOP_LOGIC_OUTS_L_B18_1" + ], + [ + "CMT_FIFO_L_IMUX42_6", + "CMT_TOP_IMUX42_6" + ], + [ + "CMT_FIFO_L_IMUX37_2", + "CMT_TOP_IMUX37_2" + ], + [ + "CMT_FIFO_EE4C2_11", + "CMT_TOP_EE4C2_11" + ], + [ + "CMT_FIFO_LH5_4", + "CMT_TOP_LH5_4" + ], + [ + "CMT_FIFO_EE2BEG1_0", + "CMT_TOP_EE2BEG1_0" + ], + [ + "CMT_FIFO_L_IMUX38_6", + "CMT_TOP_IMUX38_6" + ], + [ + "CMT_FIFO_EE4C2_8", + "CMT_TOP_EE4C2_8" + ], + [ + "CMT_FIFO_EE4BEG2_5", + "CMT_TOP_EE4BEG2_5" + ], + [ + "CMT_FIFO_WW4C1_7", + "CMT_TOP_WW4C1_7" + ], + [ + "CMT_FIFO_WW4C2_7", + "CMT_TOP_WW4C2_7" + ], + [ + "CMT_FIFO_L_BYP3_9", + "CMT_TOP_BYP3_9" + ], + [ + "CMT_FIFO_L_FAN4_11", + "CMT_TOP_FAN4_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_0", + "CMT_TOP_LOGIC_OUTS_L_B19_0" + ], + [ + "CMT_FIFO_SW4END0_4", + "CMT_TOP_SW4END0_4" + ], + [ + "CMT_FIFO_L_IMUX35_2", + "CMT_TOP_IMUX35_2" + ], + [ + "CMT_FIFO_WW4C1_10", + "CMT_TOP_WW4C1_10" + ], + [ + "CMT_FIFO_EE2A2_6", + "CMT_TOP_EE2A2_6" + ], + [ + "CMT_FIFO_EE4C3_11", + "CMT_TOP_EE4C3_11" + ], + [ + "CMT_FIFO_L_BYP7_10", + "CMT_TOP_BYP7_10" + ], + [ + "CMT_FIFO_L_IMUX29_8", + "CMT_TOP_IMUX29_8" + ], + [ + "CMT_FIFO_NE2A0_0", + "CMT_TOP_NE2A0_0" + ], + [ + "CMT_FIFO_NE2A0_9", + "CMT_TOP_NE2A0_9" + ], + [ + "CMT_FIFO_L_IMUX9_10", + "CMT_TOP_IMUX9_10" + ], + [ + "CMT_FIFO_WW2END1_0", + "CMT_TOP_WW2END1_0" + ], + [ + "CMT_FIFO_SE2A1_10", + "CMT_TOP_SE2A1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_5", + "CMT_TOP_LOGIC_OUTS_L_B16_5" + ], + [ + "CMT_FIFO_L_IMUX34_6", + "CMT_TOP_IMUX34_6" + ], + [ + "CMT_FIFO_L_IMUX43_11", + "CMT_TOP_IMUX43_11" + ], + [ + "CMT_FIFO_EL1BEG2_10", + "CMT_TOP_EL1BEG2_10" + ], + [ + "CMT_FIFO_WW2END3_3", + "CMT_TOP_WW2END3_3" + ], + [ + "CMT_FIFO_L_IMUX15_2", + "CMT_TOP_IMUX15_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "CMT_TOP_OCLK_4" + ], + [ + "CMT_FIFO_EE4A3_1", + "CMT_TOP_EE4A3_1" + ], + [ + "CMT_FIFO_L_IMUX33_6", + "CMT_TOP_IMUX33_6" + ], + [ + "CMT_FIFO_WL1END3_5", + "CMT_TOP_WL1END3_5" + ], + [ + "CMT_FIFO_NE4C1_1", + "CMT_TOP_NE4C1_1" + ], + [ + "CMT_FIFO_ER1BEG0_3", + "CMT_TOP_ER1BEG0_3" + ], + [ + "CMT_FIFO_LH4_5", + "CMT_TOP_LH4_5" + ], + [ + "CMT_FIFO_L_IMUX16_3", + "CMT_TOP_IMUX16_3" + ], + [ + "CMT_FIFO_NE2A3_9", + "CMT_TOP_NE2A3_9" + ], + [ + "CMT_FIFO_NE4BEG2_10", + "CMT_TOP_NE4BEG2_10" + ], + [ + "CMT_FIFO_L_BYP3_1", + "CMT_TOP_BYP3_1" + ], + [ + "CMT_FIFO_WW4C3_11", + "CMT_TOP_WW4C3_11" + ], + [ + "CMT_FIFO_EL1BEG1_0", + "CMT_TOP_EL1BEG1_0" + ], + [ + "CMT_FIFO_L_CTRL0_11", + "CMT_TOP_CTRL0_11" + ], + [ + "CMT_FIFO_L_IMUX18_1", + "CMT_TOP_IMUX18_1" + ], + [ + "CMT_FIFO_SE4BEG0_2", + "CMT_TOP_SE4BEG0_2" + ], + [ + "CMT_FIFO_EE2BEG1_7", + "CMT_TOP_EE2BEG1_7" + ], + [ + "CMT_FIFO_EL1BEG1_7", + "CMT_TOP_EL1BEG1_7" + ], + [ + "CMT_FIFO_LH12_10", + "CMT_TOP_LH12_10" + ], + [ + "CMT_FIFO_ER1BEG0_6", + "CMT_TOP_ER1BEG0_6" + ], + [ + "CMT_FIFO_LH11_11", + "CMT_TOP_LH11_11" + ], + [ + "CMT_FIFO_L_IMUX5_6", + "CMT_TOP_IMUX5_6" + ], + [ + "CMT_FIFO_WW2END1_6", + "CMT_TOP_WW2END1_6" + ], + [ + "CMT_FIFO_WW4A2_6", + "CMT_TOP_WW4A2_6" + ], + [ + "CMT_FIFO_L_FAN4_2", + "CMT_TOP_FAN4_2" + ], + [ + "CMT_FIFO_WL1END0_6", + "CMT_TOP_WL1END0_6" + ], + [ + "CMT_FIFO_WW4END0_9", + "CMT_TOP_WW4END0_9" + ], + [ + "CMT_FIFO_WW4A0_11", + "CMT_TOP_WW4A0_11" + ], + [ + "CMT_FIFO_EE4B3_1", + "CMT_TOP_EE4B3_1" + ], + [ + "CMT_FIFO_L_IMUX19_1", + "CMT_TOP_IMUX19_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_3", + "CMT_TOP_LOGIC_OUTS_L_B3_3" + ], + [ + "CMT_FIFO_NW4A2_2", + "CMT_TOP_NW4A2_2" + ], + [ + "CMT_FIFO_L_IMUX3_10", + "CMT_TOP_IMUX3_10" + ], + [ + "CMT_FIFO_EE4C3_9", + "CMT_TOP_EE4C3_9" + ], + [ + "CMT_FIFO_SW4END2_8", + "CMT_TOP_SW4END2_8" + ], + [ + "CMT_FIFO_SE4C2_2", + "CMT_TOP_SE4C2_2" + ], + [ + "CMT_FIFO_NE2A2_11", + "CMT_TOP_NE2A2_11" + ], + [ + "CMT_FIFO_L_IMUX36_8", + "CMT_TOP_IMUX36_8" + ], + [ + "CMT_FIFO_L_IMUX44_11", + "CMT_TOP_IMUX44_11" + ], + [ + "CMT_FIFO_LH11_4", + "CMT_TOP_LH11_4" + ], + [ + "CMT_FIFO_L_BYP7_11", + "CMT_TOP_BYP7_11" + ], + [ + "CMT_FIFO_LH1_1", + "CMT_TOP_LH1_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "CMT_TOP_OCLKDIV_5" + ], + [ + "CMT_FIFO_LH6_3", + "CMT_TOP_LH6_3" + ], + [ + "CMT_FIFO_WW4C2_3", + "CMT_TOP_WW4C2_3" + ], + [ + "CMT_FIFO_NE4BEG3_9", + "CMT_TOP_NE4BEG3_9" + ], + [ + "CMT_FIFO_LH7_3", + "CMT_TOP_LH7_3" + ], + [ + "CMT_FIFO_L_IMUX1_5", + "CMT_TOP_IMUX1_5" + ], + [ + "CMT_FIFO_SW4A1_10", + "CMT_TOP_SW4A1_10" + ], + [ + "CMT_FIFO_L_FAN0_11", + "CMT_TOP_FAN0_11" + ], + [ + "CMT_FIFO_EE2BEG1_10", + "CMT_TOP_EE2BEG1_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_5", + "CMT_TOP_LOGIC_OUTS_L_B3_5" + ], + [ + "FIFO_DQS_IOTOPHASER_1", + "CMT_PHASER_UP_DQS_TO_PHASER_C" + ], + [ + "CMT_FIFO_L_IMUX45_10", + "CMT_TOP_IMUX45_10" + ], + [ + "CMT_FIFO_NW4END0_7", + "CMT_TOP_NW4END0_7" + ], + [ + "CMT_FIFO_L_IMUX41_2", + "CMT_TOP_IMUX41_2" + ], + [ + "CMT_FIFO_EE4A1_4", + "CMT_TOP_EE4A1_4" + ], + [ + "CMT_FIFO_NE2A3_7", + "CMT_TOP_NE2A3_7" + ], + [ + "CMT_FIFO_L_IMUX19_5", + "CMT_TOP_IMUX19_5" + ], + [ + "CMT_FIFO_NE4C2_6", + "CMT_TOP_NE4C2_6" + ], + [ + "CMT_FIFO_L_IMUX12_6", + "CMT_TOP_IMUX12_6" + ], + [ + "CMT_FIFO_SE4C3_6", + "CMT_TOP_SE4C3_6" + ], + [ + "CMT_FIFO_L_IMUX0_6", + "CMT_TOP_IMUX0_6" + ], + [ + "CMT_FIFO_SE4C0_8", + "CMT_TOP_SE4C0_8" + ], + [ + "CMT_FIFO_L_IMUX38_4", + "CMT_TOP_IMUX38_4" + ], + [ + "CMT_FIFO_EE4C2_9", + "CMT_TOP_EE4C2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_9", + "CMT_TOP_LOGIC_OUTS_L_B13_9" + ], + [ + "CMT_FIFO_L_IMUX16_11", + "CMT_TOP_IMUX16_11" + ], + [ + "CMT_FIFO_L_IMUX28_7", + "CMT_TOP_IMUX28_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_1", + "CMT_TOP_LOGIC_OUTS_L_B21_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_5", + "CMT_TOP_LOGIC_OUTS_L_B11_5" + ], + [ + "CMT_FIFO_L_IMUX7_1", + "CMT_TOP_IMUX7_1" + ], + [ + "CMT_FIFO_MONITOR_N_8", + "CMT_TOP_MONITOR_N_8" + ], + [ + "CMT_FIFO_L_IMUX47_1", + "CMT_TOP_IMUX47_1" + ], + [ + "CMT_FIFO_L_FAN2_9", + "CMT_TOP_FAN2_9" + ], + [ + "CMT_FIFO_SE2A2_4", + "CMT_TOP_SE2A2_4" + ], + [ + "CMT_FIFO_LH4_3", + "CMT_TOP_LH4_3" + ], + [ + "CMT_FIFO_EE4A0_5", + "CMT_TOP_EE4A0_5" + ], + [ + "CMT_FIFO_L_CLK1_4", + "CMT_TOP_CLK1_4" + ], + [ + "CMT_FIFO_LH5_3", + "CMT_TOP_LH5_3" + ], + [ + "CMT_FIFO_LH10_0", + "CMT_TOP_LH10_0" + ], + [ + "CMT_FIFO_L_IMUX21_6", + "CMT_TOP_IMUX21_6" + ], + [ + "CMT_FIFO_NW4A3_10", + "CMT_TOP_NW4A3_10" + ], + [ + "CMT_FIFO_L_IMUX18_4", + "CMT_TOP_IMUX18_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_6", + "CMT_TOP_LOGIC_OUTS_L_B23_6" + ], + [ + "CMT_FIFO_NW2A0_8", + "CMT_TOP_NW2A0_8" + ], + [ + "CMT_FIFO_EE4A1_0", + "CMT_TOP_EE4A1_0" + ], + [ + "CMT_FIFO_SE4C2_10", + "CMT_TOP_SE4C2_10" + ], + [ + "CMT_FIFO_WW4END0_5", + "CMT_TOP_WW4END0_5" + ], + [ + "CMT_FIFO_SW4END3_4", + "CMT_TOP_SW4END3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_10", + "CMT_TOP_LOGIC_OUTS_L_B13_10" + ], + [ + "CMT_FIFO_WW4A1_1", + "CMT_TOP_WW4A1_1" + ], + [ + "CMT_FIFO_WW4END1_6", + "CMT_TOP_WW4END1_6" + ], + [ + "CMT_FIFO_SW2A1_1", + "CMT_TOP_SW2A1_1" + ], + [ + "CMT_FIFO_NW4A3_3", + "CMT_TOP_NW4A3_3" + ], + [ + "CMT_FIFO_L_FAN7_7", + "CMT_TOP_FAN7_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "CMT_TOP_ICLKDIV_6" + ], + [ + "CMT_FIFO_L_IMUX32_10", + "CMT_TOP_IMUX32_10" + ], + [ + "CMT_FIFO_L_IMUX0_7", + "CMT_TOP_IMUX0_7" + ], + [ + "CMT_FIFO_WR1END0_6", + "CMT_TOP_WR1END0_6" + ], + [ + "CMT_FIFO_EE4C0_5", + "CMT_TOP_EE4C0_5" + ], + [ + "CMT_FIFO_L_BYP3_5", + "CMT_TOP_BYP3_5" + ], + [ + "CMT_FIFO_SE4BEG1_2", + "CMT_TOP_SE4BEG1_2" + ], + [ + "CMT_FIFO_NW2A1_3", + "CMT_TOP_NW2A1_3" + ], + [ + "CMT_FIFO_L_IMUX10_5", + "CMT_TOP_IMUX10_5" + ], + [ + "CMT_FIFO_L_IMUX45_4", + "CMT_TOP_IMUX45_4" + ], + [ + "CMT_FIFO_EE4C3_2", + "CMT_TOP_EE4C3_2" + ], + [ + "CMT_FIFO_SE4BEG3_4", + "CMT_TOP_SE4BEG3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_2", + "CMT_TOP_LOGIC_OUTS_L_B23_2" + ], + [ + "CMT_FIFO_ER1BEG0_10", + "CMT_TOP_ER1BEG0_10" + ], + [ + "CMT_FIFO_NW4A3_5", + "CMT_TOP_NW4A3_5" + ], + [ + "CMT_FIFO_LH9_0", + "CMT_TOP_LH9_0" + ], + [ + "CMT_FIFO_SW4A3_5", + "CMT_TOP_SW4A3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_8", + "CMT_TOP_LOGIC_OUTS_L_B21_8" + ], + [ + "CMT_FIFO_WW4A3_6", + "CMT_TOP_WW4A3_6" + ], + [ + "CMT_FIFO_SE2A1_1", + "CMT_TOP_SE2A1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_1", + "CMT_TOP_LOGIC_OUTS_L_B19_1" + ], + [ + "CMT_FIFO_L_FAN5_9", + "CMT_TOP_FAN5_9" + ], + [ + "CMT_FIFO_NE4C3_7", + "CMT_TOP_NE4C3_7" + ], + [ + "CMT_FIFO_NW2A3_11", + "CMT_TOP_NW2A3_11" + ], + [ + "CMT_FIFO_WW4END2_3", + "CMT_TOP_WW4END2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_1", + "CMT_TOP_LOGIC_OUTS_L_B3_1" + ], + [ + "CMT_FIFO_LH1_2", + "CMT_TOP_LH1_2" + ], + [ + "CMT_FIFO_SW4END2_2", + "CMT_TOP_SW4END2_2" + ], + [ + "CMT_FIFO_L_IMUX23_10", + "CMT_TOP_IMUX23_10" + ], + [ + "CMT_FIFO_WR1END3_9", + "CMT_TOP_WR1END3_9" + ], + [ + "CMT_FIFO_L_IMUX42_5", + "CMT_TOP_IMUX42_5" + ], + [ + "CMT_FIFO_NE4C1_7", + "CMT_TOP_NE4C1_7" + ], + [ + "CMT_FIFO_LH7_11", + "CMT_TOP_LH7_11" + ], + [ + "CMT_FIFO_L_BYP5_11", + "CMT_TOP_BYP5_11" + ], + [ + "CMT_FIFO_MONITOR_P_8", + "CMT_TOP_MONITOR_P_8" + ], + [ + "CMT_FIFO_SE4C0_9", + "CMT_TOP_SE4C0_9" + ], + [ + "CMT_FIFO_L_IMUX46_8", + "CMT_TOP_IMUX46_8" + ], + [ + "CMT_FIFO_L_IMUX10_10", + "CMT_TOP_IMUX10_10" + ], + [ + "CMT_FIFO_MONITOR_P_10", + "CMT_TOP_MONITOR_P_10" + ], + [ + "CMT_FIFO_L_IMUX4_9", + "CMT_TOP_IMUX4_9" + ], + [ + "CMT_FIFO_SW2A2_3", + "CMT_TOP_SW2A2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_5", + "CMT_TOP_LOGIC_OUTS_L_B15_5" + ], + [ + "CMT_FIFO_EE4B2_8", + "CMT_TOP_EE4B2_8" + ], + [ + "CMT_FIFO_L_IMUX17_6", + "CMT_TOP_IMUX17_6" + ], + [ + "CMT_FIFO_EL1BEG3_1", + "CMT_TOP_EL1BEG3_1" + ], + [ + "CMT_FIFO_L_IMUX34_9", + "CMT_TOP_IMUX34_9" + ], + [ + "CMT_FIFO_EL1BEG2_6", + "CMT_TOP_EL1BEG2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_10", + "CMT_TOP_LOGIC_OUTS_L_B4_10" + ], + [ + "CMT_FIFO_L_IMUX44_7", + "CMT_TOP_IMUX44_7" + ], + [ + "CMT_FIFO_SW4A3_11", + "CMT_TOP_SW4A3_11" + ], + [ + "CMT_FIFO_NW4A2_0", + "CMT_TOP_NW4A2_0" + ], + [ + "CMT_FIFO_LH7_8", + "CMT_TOP_LH7_8" + ], + [ + "CMT_FIFO_EE2BEG2_6", + "CMT_TOP_EE2BEG2_6" + ], + [ + "CMT_FIFO_SE4BEG0_1", + "CMT_TOP_SE4BEG0_1" + ], + [ + "CMT_FIFO_WW4B1_4", + "CMT_TOP_WW4B1_4" + ], + [ + "CMT_FIFO_L_CTRL0_9", + "CMT_TOP_CTRL0_9" + ], + [ + "CMT_FIFO_SE4C1_3", + "CMT_TOP_SE4C1_3" + ], + [ + "CMT_FIFO_WW2END2_11", + "CMT_TOP_WW2END2_11" + ], + [ + "CMT_FIFO_WR1END3_7", + "CMT_TOP_WR1END3_7" + ], + [ + "CMT_FIFO_WW4B2_2", + "CMT_TOP_WW4B2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_6", + "CMT_TOP_LOGIC_OUTS_L_B18_6" + ], + [ + "CMT_FIFO_LH3_6", + "CMT_TOP_LH3_6" + ], + [ + "CMT_FIFO_LH7_4", + "CMT_TOP_LH7_4" + ], + [ + "CMT_FIFO_LH12_1", + "CMT_TOP_LH12_1" + ], + [ + "CMT_FIFO_WW2A2_4", + "CMT_TOP_WW2A2_4" + ], + [ + "CMT_FIFO_ER1BEG2_1", + "CMT_TOP_ER1BEG2_1" + ], + [ + "CMT_FIFO_WW4A3_1", + "CMT_TOP_WW4A3_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_10", + "CMT_TOP_LOGIC_OUTS_L_B22_10" + ], + [ + "CMT_FIFO_SW4END1_10", + "CMT_TOP_SW4END1_10" + ], + [ + "CMT_FIFO_L_IMUX30_9", + "CMT_TOP_IMUX30_9" + ], + [ + "CMT_FIFO_EE4C1_1", + "CMT_TOP_EE4C1_1" + ], + [ + "CMT_FIFO_NW2A2_7", + "CMT_TOP_NW2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_4", + "CMT_TOP_LOGIC_OUTS_L_B1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_6", + "CMT_TOP_LOGIC_OUTS_L_B9_6" + ], + [ + "CMT_FIFO_NE2A3_6", + "CMT_TOP_NE2A3_6" + ], + [ + "CMT_FIFO_L_IMUX30_8", + "CMT_TOP_IMUX30_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "CMT_TOP_ICLKDIV_10" + ], + [ + "CMT_FIFO_NW4END3_8", + "CMT_TOP_NW4END3_8" + ], + [ + "CMT_FIFO_EE2BEG3_8", + "CMT_TOP_EE2BEG3_8" + ], + [ + "CMT_FIFO_NW2A0_3", + "CMT_TOP_NW2A0_3" + ], + [ + "CMT_FIFO_WR1END0_10", + "CMT_TOP_WR1END0_10" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "CMT_TOP_ICLKDIV_11" + ], + [ + "CMT_FIFO_L_BYP2_0", + "CMT_TOP_BYP2_0" + ], + [ + "CMT_FIFO_L_IMUX2_5", + "CMT_TOP_IMUX2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_11", + "CMT_TOP_LOGIC_OUTS_L_B9_11" + ], + [ + "CMT_FIFO_NW2A2_5", + "CMT_TOP_NW2A2_5" + ], + [ + "CMT_FIFO_NW2A2_3", + "CMT_TOP_NW2A2_3" + ], + [ + "CMT_FIFO_NW4A0_9", + "CMT_TOP_NW4A0_9" + ], + [ + "CMT_FIFO_SW2A1_5", + "CMT_TOP_SW2A1_5" + ], + [ + "CMT_FIFO_SE2A3_10", + "CMT_TOP_SE2A3_10" + ], + [ + "CMT_FIFO_EE2BEG2_1", + "CMT_TOP_EE2BEG2_1" + ], + [ + "CMT_FIFO_L_CTRL1_1", + "CMT_TOP_CTRL1_1" + ], + [ + "CMT_FIFO_NE2A3_8", + "CMT_TOP_NE2A3_8" + ], + [ + "CMT_FIFO_L_IMUX30_4", + "CMT_TOP_IMUX30_4" + ], + [ + "CMT_FIFO_L_BYP3_4", + "CMT_TOP_BYP3_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_5", + "CMT_TOP_LOGIC_OUTS_L_B17_5" + ], + [ + "CMT_FIFO_WW4B3_5", + "CMT_TOP_WW4B3_5" + ], + [ + "CMT_FIFO_EE4B1_7", + "CMT_TOP_EE4B1_7" + ], + [ + "CMT_FIFO_EE4C0_9", + "CMT_TOP_EE4C0_9" + ], + [ + "CMT_FIFO_EE2BEG0_0", + "CMT_TOP_EE2BEG0_0" + ], + [ + "CMT_FIFO_LH8_0", + "CMT_TOP_LH8_0" + ], + [ + "CMT_FIFO_WR1END1_9", + "CMT_TOP_WR1END1_9" + ], + [ + "CMT_FIFO_EE2BEG3_5", + "CMT_TOP_EE2BEG3_5" + ], + [ + "CMT_FIFO_SE2A1_4", + "CMT_TOP_SE2A1_4" + ], + [ + "CMT_FIFO_L_IMUX32_3", + "CMT_TOP_IMUX32_3" + ], + [ + "CMT_FIFO_L_BYP5_10", + "CMT_TOP_BYP5_10" + ], + [ + "CMT_FIFO_EE4B3_11", + "CMT_TOP_EE4B3_11" + ], + [ + "CMT_FIFO_NW2A3_1", + "CMT_TOP_NW2A3_1" + ], + [ + "CMT_FIFO_SE4C1_1", + "CMT_TOP_SE4C1_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_9", + "CMT_TOP_LOGIC_OUTS_L_B6_9" + ], + [ + "CMT_FIFO_L_IMUX46_4", + "CMT_TOP_IMUX46_4" + ], + [ + "CMT_FIFO_EE4B2_2", + "CMT_TOP_EE4B2_2" + ], + [ + "CMT_FIFO_SW4END3_1", + "CMT_TOP_SW4END3_1" + ], + [ + "CMT_FIFO_WW2A1_7", + "CMT_TOP_WW2A1_7" + ], + [ + "CMT_FIFO_EL1BEG0_6", + "CMT_TOP_EL1BEG0_6" + ], + [ + "CMT_FIFO_EE2A2_2", + "CMT_TOP_EE2A2_2" + ], + [ + "CMT_FIFO_WR1END3_5", + "CMT_TOP_WR1END3_5" + ], + [ + "CMT_FIFO_L_BYP5_6", + "CMT_TOP_BYP5_6" + ], + [ + "CMT_FIFO_L_IMUX30_11", + "CMT_TOP_IMUX30_11" + ], + [ + "CMT_FIFO_L_IMUX4_4", + "CMT_TOP_IMUX4_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_6", + "CMT_TOP_LOGIC_OUTS_L_B3_6" + ], + [ + "CMT_FIFO_L_IMUX44_9", + "CMT_TOP_IMUX44_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_6", + "CMT_TOP_LOGIC_OUTS_L_B20_6" + ], + [ + "CMT_FIFO_EE4B1_0", + "CMT_TOP_EE4B1_0" + ], + [ + "CMT_FIFO_L_IMUX26_4", + "CMT_TOP_IMUX26_4" + ], + [ + "CMT_FIFO_L_IMUX39_0", + "CMT_TOP_IMUX39_0" + ], + [ + "CMT_FIFO_NW4A0_11", + "CMT_TOP_NW4A0_11" + ], + [ + "CMT_FIFO_WW4C0_10", + "CMT_TOP_WW4C0_10" + ], + [ + "CMT_FIFO_L_IMUX45_9", + "CMT_TOP_IMUX45_9" + ], + [ + "CMT_FIFO_NE4C1_0", + "CMT_TOP_NE4C1_0" + ], + [ + "CMT_FIFO_EE4A2_9", + "CMT_TOP_EE4A2_9" + ], + [ + "CMT_FIFO_L_FAN1_10", + "CMT_TOP_FAN1_10" + ], + [ + "CMT_FIFO_ER1BEG3_11", + "CMT_TOP_ER1BEG3_11" + ], + [ + "CMT_FIFO_NW4END3_10", + "CMT_TOP_NW4END3_10" + ], + [ + "CMT_FIFO_L_IMUX28_8", + "CMT_TOP_IMUX28_8" + ], + [ + "CMT_FIFO_L_IMUX38_5", + "CMT_TOP_IMUX38_5" + ], + [ + "CMT_FIFO_L_IMUX38_2", + "CMT_TOP_IMUX38_2" + ], + [ + "CMT_FIFO_ER1BEG0_4", + "CMT_TOP_ER1BEG0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_3", + "CMT_TOP_LOGIC_OUTS_L_B5_3" + ], + [ + "CMT_FIFO_L_BYP2_8", + "CMT_TOP_BYP2_8" + ], + [ + "CMT_FIFO_SW2A3_0", + "CMT_TOP_SW2A3_0" + ], + [ + "CMT_FIFO_WW4C1_11", + "CMT_TOP_WW4C1_11" + ], + [ + "CMT_FIFO_NE2A2_2", + "CMT_TOP_NE2A2_2" + ], + [ + "CMT_FIFO_L_IMUX25_6", + "CMT_TOP_IMUX25_6" + ], + [ + "CMT_FIFO_L_IMUX15_11", + "CMT_TOP_IMUX15_11" + ], + [ + "CMT_FIFO_L_IMUX10_8", + "CMT_TOP_IMUX10_8" + ], + [ + "CMT_FIFO_L_IMUX38_11", + "CMT_TOP_IMUX38_11" + ], + [ + "CMT_FIFO_EE4B0_10", + "CMT_TOP_EE4B0_10" + ], + [ + "CMT_FIFO_WW4END2_9", + "CMT_TOP_WW4END2_9" + ], + [ + "CMT_FIFO_L_IMUX31_6", + "CMT_TOP_IMUX31_6" + ], + [ + "CMT_FIFO_L_IMUX35_3", + "CMT_TOP_IMUX35_3" + ], + [ + "CMT_FIFO_SW2A2_0", + "CMT_TOP_SW2A2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_0", + "CMT_TOP_LOGIC_OUTS_L_B11_0" + ], + [ + "CMT_FIFO_NW4A0_5", + "CMT_TOP_NW4A0_5" + ], + [ + "CMT_FIFO_L_IMUX14_10", + "CMT_TOP_IMUX14_10" + ], + [ + "CMT_FIFO_NE4C3_6", + "CMT_TOP_NE4C3_6" + ], + [ + "CMT_FIFO_L_IMUX31_3", + "CMT_TOP_IMUX31_3" + ], + [ + "CMT_FIFO_WW4B0_10", + "CMT_TOP_WW4B0_10" + ], + [ + "CMT_FIFO_L_CLK1_8", + "CMT_TOP_CLK1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_8", + "CMT_TOP_LOGIC_OUTS_L_B17_8" + ], + [ + "CMT_FIFO_L_FAN6_7", + "CMT_TOP_FAN6_7" + ], + [ + "CMT_FIFO_LH6_1", + "CMT_TOP_LH6_1" + ], + [ + "CMT_FIFO_L_FAN3_0", + "CMT_TOP_FAN3_0" + ], + [ + "CMT_FIFO_WW4C3_10", + "CMT_TOP_WW4C3_10" + ], + [ + "CMT_FIFO_EE2A3_6", + "CMT_TOP_EE2A3_6" + ], + [ + "CMT_FIFO_EL1BEG0_0", + "CMT_TOP_EL1BEG0_0" + ], + [ + "CMT_FIFO_EE4BEG2_11", + "CMT_TOP_EE4BEG2_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "CMT_TOP_ICLK_11" + ], + [ + "CMT_FIFO_SE2A2_9", + "CMT_TOP_SE2A2_9" + ], + [ + "CMT_FIFO_L_IMUX43_8", + "CMT_TOP_IMUX43_8" + ], + [ + "CMT_FIFO_EE4C2_7", + "CMT_TOP_EE4C2_7" + ], + [ + "CMT_FIFO_EE2BEG3_6", + "CMT_TOP_EE2BEG3_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_7", + "CMT_TOP_LOGIC_OUTS_L_B23_7" + ], + [ + "CMT_FIFO_NE4BEG0_1", + "CMT_TOP_NE4BEG0_1" + ], + [ + "CMT_FIFO_NW4A0_8", + "CMT_TOP_NW4A0_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_7", + "CMT_TOP_LOGIC_OUTS_L_B21_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_3", + "CMT_TOP_LOGIC_OUTS_L_B19_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_8", + "CMT_TOP_LOGIC_OUTS_L_B23_8" + ], + [ + "CMT_FIFO_L_FAN7_4", + "CMT_TOP_FAN7_4" + ], + [ + "CMT_FIFO_WW4A2_2", + "CMT_TOP_WW4A2_2" + ], + [ + "CMT_FIFO_SE4C2_11", + "CMT_TOP_SE4C2_11" + ], + [ + "CMT_FIFO_L_IMUX27_1", + "CMT_TOP_IMUX27_1" + ], + [ + "CMT_FIFO_ER1BEG1_4", + "CMT_TOP_ER1BEG1_4" + ], + [ + "CMT_FIFO_L_FAN2_10", + "CMT_TOP_FAN2_10" + ], + [ + "CMT_FIFO_WW2END2_8", + "CMT_TOP_WW2END2_8" + ], + [ + "CMT_FIFO_L_IMUX23_11", + "CMT_TOP_IMUX23_11" + ], + [ + "CMT_FIFO_EE4C3_4", + "CMT_TOP_EE4C3_4" + ], + [ + "CMT_FIFO_L_IMUX41_0", + "CMT_TOP_IMUX41_0" + ], + [ + "CMT_FIFO_ER1BEG1_11", + "CMT_TOP_ER1BEG1_11" + ], + [ + "CMT_FIFO_SE4C3_7", + "CMT_TOP_SE4C3_7" + ], + [ + "CMT_FIFO_L_IMUX7_10", + "CMT_TOP_IMUX7_10" + ], + [ + "CMT_FIFO_L_FAN4_3", + "CMT_TOP_FAN4_3" + ], + [ + "CMT_FIFO_L_IMUX35_5", + "CMT_TOP_IMUX35_5" + ], + [ + "CMT_FIFO_WW4A0_5", + "CMT_TOP_WW4A0_5" + ], + [ + "CMT_FIFO_L_IMUX47_0", + "CMT_TOP_IMUX47_0" + ], + [ + "CMT_FIFO_WW4B3_2", + "CMT_TOP_WW4B3_2" + ], + [ + "CMT_FIFO_L_IMUX6_7", + "CMT_TOP_IMUX6_7" + ], + [ + "CMT_FIFO_L_IMUX28_0", + "CMT_TOP_IMUX28_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_5", + "CMT_TOP_LOGIC_OUTS_L_B23_5" + ], + [ + "CMT_FIFO_LH2_2", + "CMT_TOP_LH2_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "CMT_TOP_OCLKDIV_11" + ], + [ + "CMT_FIFO_WW4B1_11", + "CMT_TOP_WW4B1_11" + ], + [ + "CMT_FIFO_MONITOR_N_0", + "CMT_TOP_MONITOR_N_0" + ], + [ + "CMT_FIFO_WW4A2_5", + "CMT_TOP_WW4A2_5" + ], + [ + "CMT_FIFO_SE4BEG2_9", + "CMT_TOP_SE4BEG2_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_0", + "CMT_TOP_LOGIC_OUTS_L_B5_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_5", + "CMT_TOP_LOGIC_OUTS_L_B20_5" + ], + [ + "CMT_FIFO_SE4C1_11", + "CMT_TOP_SE4C1_11" + ], + [ + "CMT_FIFO_EE4C2_1", + "CMT_TOP_EE4C2_1" + ], + [ + "CMT_FIFO_EE4B3_8", + "CMT_TOP_EE4B3_8" + ], + [ + "CMT_FIFO_L_IMUX37_8", + "CMT_TOP_IMUX37_8" + ], + [ + "CMT_FIFO_LH3_7", + "CMT_TOP_LH3_7" + ], + [ + "CMT_FIFO_SE2A0_5", + "CMT_TOP_SE2A0_5" + ], + [ + "CMT_FIFO_L_IMUX22_6", + "CMT_TOP_IMUX22_6" + ], + [ + "CMT_FIFO_L_BYP4_2", + "CMT_TOP_BYP4_2" + ], + [ + "CMT_FIFO_MONITOR_P_6", + "CMT_TOP_MONITOR_P_6" + ], + [ + "CMT_FIFO_WW4END2_11", + "CMT_TOP_WW4END2_11" + ], + [ + "CMT_FIFO_SE4BEG3_8", + "CMT_TOP_SE4BEG3_8" + ], + [ + "CMT_FIFO_NW2A3_10", + "CMT_TOP_NW2A3_10" + ], + [ + "CMT_FIFO_L_IMUX32_5", + "CMT_TOP_IMUX32_5" + ], + [ + "CMT_FIFO_L_IMUX17_7", + "CMT_TOP_IMUX17_7" + ], + [ + "CMT_FIFO_SE2A3_2", + "CMT_TOP_SE2A3_2" + ], + [ + "CMT_FIFO_WW4END3_11", + "CMT_TOP_WW4END3_11" + ], + [ + "CMT_FIFO_L_IMUX42_7", + "CMT_TOP_IMUX42_7" + ], + [ + "CMT_FIFO_L_IMUX32_7", + "CMT_TOP_IMUX32_7" + ], + [ + "CMT_FIFO_L_IMUX0_2", + "CMT_TOP_IMUX0_2" + ], + [ + "CMT_FIFO_L_IMUX46_7", + "CMT_TOP_IMUX46_7" + ], + [ + "CMT_FIFO_L_IMUX31_7", + "CMT_TOP_IMUX31_7" + ], + [ + "CMT_FIFO_WL1END3_1", + "CMT_TOP_WL1END3_1" + ], + [ + "CMT_FIFO_WW4B1_2", + "CMT_TOP_WW4B1_2" + ], + [ + "CMT_FIFO_LH5_5", + "CMT_TOP_LH5_5" + ], + [ + "CMT_FIFO_LH10_1", + "CMT_TOP_LH10_1" + ], + [ + "CMT_FIFO_NE2A1_7", + "CMT_TOP_NE2A1_7" + ], + [ + "CMT_FIFO_L_IMUX0_10", + "CMT_TOP_IMUX0_10" + ], + [ + "CMT_FIFO_L_BYP2_10", + "CMT_TOP_BYP2_10" + ], + [ + "CMT_FIFO_L_CTRL1_6", + "CMT_TOP_CTRL1_6" + ], + [ + "CMT_FIFO_WR1END0_9", + "CMT_TOP_WR1END0_9" + ], + [ + "CMT_FIFO_L_BYP1_7", + "CMT_TOP_BYP1_7" + ], + [ + "CMT_FIFO_L_FAN1_9", + "CMT_TOP_FAN1_9" + ], + [ + "CMT_FIFO_WW4C2_5", + "CMT_TOP_WW4C2_5" + ], + [ + "CMT_FIFO_WL1END2_11", + "CMT_TOP_WL1END2_11" + ], + [ + "CMT_FIFO_NW4A3_11", + "CMT_TOP_NW4A3_11" + ], + [ + "CMT_FIFO_L_BYP6_5", + "CMT_TOP_BYP6_5" + ], + [ + "CMT_FIFO_EE4BEG3_1", + "CMT_TOP_EE4BEG3_1" + ], + [ + "CMT_FIFO_L_IMUX17_8", + "CMT_TOP_IMUX17_8" + ], + [ + "CMT_FIFO_WW2END3_0", + "CMT_TOP_WW2END3_0" + ], + [ + "CMT_FIFO_L_IMUX42_4", + "CMT_TOP_IMUX42_4" + ], + [ + "CMT_FIFO_NE4BEG3_3", + "CMT_TOP_NE4BEG3_3" + ], + [ + "CMT_FIFO_SE4C2_0", + "CMT_TOP_SE4C2_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_6", + "CMT_TOP_LOGIC_OUTS_L_B5_6" + ], + [ + "CMT_FIFO_L_PHASER_RDENABLE", + "CMT_R_PHASER_OUT_C_RDENABLE_FIFO" + ], + [ + "CMT_FIFO_WW4C2_9", + "CMT_TOP_WW4C2_9" + ], + [ + "CMT_FIFO_WW2END2_4", + "CMT_TOP_WW2END2_4" + ], + [ + "CMT_FIFO_SW2A0_2", + "CMT_TOP_SW2A0_2" + ], + [ + "CMT_FIFO_EE4BEG2_6", + "CMT_TOP_EE4BEG2_6" + ], + [ + "CMT_FIFO_EE2BEG0_3", + "CMT_TOP_EE2BEG0_3" + ], + [ + "CMT_FIFO_L_IMUX47_4", + "CMT_TOP_IMUX47_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_6", + "CMT_TOP_LOGIC_OUTS_L_B11_6" + ], + [ + "CMT_FIFO_L_FAN6_5", + "CMT_TOP_FAN6_5" + ], + [ + "CMT_FIFO_EE2BEG3_3", + "CMT_TOP_EE2BEG3_3" + ], + [ + "CMT_FIFO_L_IMUX31_0", + "CMT_TOP_IMUX31_0" + ], + [ + "CMT_FIFO_WR1END1_3", + "CMT_TOP_WR1END1_3" + ], + [ + "CMT_FIFO_NW2A1_8", + "CMT_TOP_NW2A1_8" + ], + [ + "CMT_FIFO_L_IMUX42_3", + "CMT_TOP_IMUX42_3" + ], + [ + "CMT_FIFO_NW2A2_0", + "CMT_TOP_NW2A2_0" + ], + [ + "CMT_FIFO_L_BYP1_0", + "CMT_TOP_BYP1_0" + ], + [ + "CMT_FIFO_EE2BEG3_11", + "CMT_TOP_EE2BEG3_11" + ], + [ + "CMT_FIFO_L_FAN5_1", + "CMT_TOP_FAN5_1" + ], + [ + "CMT_FIFO_SW2A1_6", + "CMT_TOP_SW2A1_6" + ], + [ + "CMT_FIFO_NW2A3_7", + "CMT_TOP_NW2A3_7" + ], + [ + "CMT_FIFO_EE4C1_9", + "CMT_TOP_EE4C1_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_11", + "CMT_TOP_LOGIC_OUTS_L_B22_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_2", + "CMT_TOP_LOGIC_OUTS_L_B5_2" + ], + [ + "CMT_FIFO_WW4B2_8", + "CMT_TOP_WW4B2_8" + ], + [ + "CMT_FIFO_EE4A0_1", + "CMT_TOP_EE4A0_1" + ], + [ + "CMT_FIFO_WW4END2_1", + "CMT_TOP_WW4END2_1" + ], + [ + "CMT_FIFO_WL1END2_10", + "CMT_TOP_WL1END2_10" + ], + [ + "CMT_FIFO_L_IMUX12_7", + "CMT_TOP_IMUX12_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_0", + "CMT_TOP_LOGIC_OUTS_L_B13_0" + ], + [ + "CMT_FIFO_SW4A2_3", + "CMT_TOP_SW4A2_3" + ], + [ + "CMT_FIFO_WL1END3_0", + "CMT_TOP_WL1END3_0" + ], + [ + "CMT_FIFO_SW4END2_6", + "CMT_TOP_SW4END2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_0", + "CMT_TOP_LOGIC_OUTS_L_B8_0" + ], + [ + "CMT_FIFO_SW4A0_1", + "CMT_TOP_SW4A0_1" + ], + [ + "CMT_FIFO_WW4END3_7", + "CMT_TOP_WW4END3_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "CMT_TOP_OCLKDIV_1" + ], + [ + "CMT_FIFO_EE4BEG0_9", + "CMT_TOP_EE4BEG0_9" + ], + [ + "CMT_FIFO_SE4BEG3_2", + "CMT_TOP_SE4BEG3_2" + ], + [ + "CMT_FIFO_NW4A0_10", + "CMT_TOP_NW4A0_10" + ], + [ + "CMT_FIFO_ER1BEG3_8", + "CMT_TOP_ER1BEG3_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_5", + "CMT_TOP_LOGIC_OUTS_L_B10_5" + ], + [ + "CMT_FIFO_SW2A2_10", + "CMT_TOP_SW2A2_10" + ], + [ + "CMT_FIFO_L_BYP2_3", + "CMT_TOP_BYP2_3" + ], + [ + "CMT_FIFO_WW4C0_7", + "CMT_TOP_WW4C0_7" + ], + [ + "CMT_FIFO_L_IMUX9_8", + "CMT_TOP_IMUX9_8" + ], + [ + "CMT_FIFO_NW4END2_5", + "CMT_TOP_NW4END2_5" + ], + [ + "CMT_FIFO_L_IMUX30_2", + "CMT_TOP_IMUX30_2" + ], + [ + "CMT_FIFO_L_BYP7_8", + "CMT_TOP_BYP7_8" + ], + [ + "CMT_FIFO_WL1END3_10", + "CMT_TOP_WL1END3_10" + ], + [ + "CMT_FIFO_L_IMUX11_10", + "CMT_TOP_IMUX11_10" + ], + [ + "CMT_FIFO_L_FAN5_11", + "CMT_TOP_FAN5_11" + ], + [ + "CMT_FIFO_NE4BEG3_0", + "CMT_TOP_NE4BEG3_0" + ], + [ + "CMT_FIFO_EE2A2_7", + "CMT_TOP_EE2A2_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_5", + "CMT_TOP_LOGIC_OUTS_L_B8_5" + ], + [ + "CMT_FIFO_WW4A2_10", + "CMT_TOP_WW4A2_10" + ], + [ + "CMT_FIFO_EE4C2_10", + "CMT_TOP_EE4C2_10" + ], + [ + "CMT_FIFO_L_IMUX8_10", + "CMT_TOP_IMUX8_10" + ], + [ + "CMT_FIFO_SW4A1_8", + "CMT_TOP_SW4A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_9", + "CMT_TOP_LOGIC_OUTS_L_B15_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_3", + "CMT_TOP_LOGIC_OUTS_L_B10_3" + ], + [ + "CMT_FIFO_EL1BEG1_3", + "CMT_TOP_EL1BEG1_3" + ], + [ + "CMT_FIFO_L_IMUX7_0", + "CMT_TOP_IMUX7_0" + ], + [ + "CMT_FIFO_L_IMUX29_0", + "CMT_TOP_IMUX29_0" + ], + [ + "CMT_FIFO_WW4B0_8", + "CMT_TOP_WW4B0_8" + ], + [ + "CMT_FIFO_NE4BEG2_6", + "CMT_TOP_NE4BEG2_6" + ], + [ + "CMT_FIFO_L_FAN1_0", + "CMT_TOP_FAN1_0" + ], + [ + "CMT_FIFO_WW2END0_11", + "CMT_TOP_WW2END0_11" + ], + [ + "CMT_FIFO_L_FAN3_1", + "CMT_TOP_FAN3_1" + ], + [ + "CMT_FIFO_LH12_7", + "CMT_TOP_LH12_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_3", + "CMT_TOP_LOGIC_OUTS_L_B18_3" + ], + [ + "CMT_FIFO_ER1BEG0_9", + "CMT_TOP_ER1BEG0_9" + ], + [ + "CMT_FIFO_SW4END1_5", + "CMT_TOP_SW4END1_5" + ], + [ + "CMT_FIFO_EE2BEG1_5", + "CMT_TOP_EE2BEG1_5" + ], + [ + "CMT_FIFO_EE2BEG2_5", + "CMT_TOP_EE2BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX14_5", + "CMT_TOP_IMUX14_5" + ], + [ + "CMT_FIFO_WW4A0_7", + "CMT_TOP_WW4A0_7" + ], + [ + "CMT_FIFO_L_IMUX23_6", + "CMT_TOP_IMUX23_6" + ], + [ + "CMT_FIFO_SW4END3_7", + "CMT_TOP_SW4END3_7" + ], + [ + "CMT_FIFO_L_IMUX46_3", + "CMT_TOP_IMUX46_3" + ], + [ + "CMT_FIFO_WR1END0_1", + "CMT_TOP_WR1END0_1" + ], + [ + "CMT_FIFO_SE4BEG2_2", + "CMT_TOP_SE4BEG2_2" + ], + [ + "CMT_FIFO_WW4END3_6", + "CMT_TOP_WW4END3_6" + ], + [ + "CMT_FIFO_SW4END2_4", + "CMT_TOP_SW4END2_4" + ], + [ + "CMT_FIFO_WW2A2_11", + "CMT_TOP_WW2A2_11" + ], + [ + "CMT_FIFO_WW2A2_0", + "CMT_TOP_WW2A2_0" + ], + [ + "CMT_FIFO_SE4C2_6", + "CMT_TOP_SE4C2_6" + ], + [ + "CMT_FIFO_SW2A3_1", + "CMT_TOP_SW2A3_1" + ], + [ + "CMT_FIFO_EE4C3_7", + "CMT_TOP_EE4C3_7" + ], + [ + "CMT_FIFO_EE4A2_8", + "CMT_TOP_EE4A2_8" + ], + [ + "CMT_FIFO_NE4BEG2_0", + "CMT_TOP_NE4BEG2_0" + ], + [ + "CMT_FIFO_NE4C1_6", + "CMT_TOP_NE4C1_6" + ], + [ + "CMT_FIFO_NE4C0_4", + "CMT_TOP_NE4C0_4" + ], + [ + "CMT_FIFO_L_IMUX13_6", + "CMT_TOP_IMUX13_6" + ], + [ + "CMT_FIFO_LH2_4", + "CMT_TOP_LH2_4" + ], + [ + "CMT_FIFO_LH1_10", + "CMT_TOP_LH1_10" + ], + [ + "CMT_FIFO_WW2END0_10", + "CMT_TOP_WW2END0_10" + ], + [ + "CMT_FIFO_L_IMUX7_9", + "CMT_TOP_IMUX7_9" + ], + [ + "CMT_FIFO_L_IMUX20_7", + "CMT_TOP_IMUX20_7" + ], + [ + "CMT_FIFO_NW2A3_6", + "CMT_TOP_NW2A3_6" + ], + [ + "CMT_FIFO_ER1BEG1_8", + "CMT_TOP_ER1BEG1_8" + ], + [ + "CMT_FIFO_SE2A0_6", + "CMT_TOP_SE2A0_6" + ], + [ + "CMT_FIFO_NW4A1_7", + "CMT_TOP_NW4A1_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "CMT_TOP_ICLK_2" + ], + [ + "CMT_FIFO_L_IMUX10_7", + "CMT_TOP_IMUX10_7" + ], + [ + "CMT_FIFO_EE4B0_3", + "CMT_TOP_EE4B0_3" + ], + [ + "CMT_FIFO_NE4C2_2", + "CMT_TOP_NE4C2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_8", + "CMT_TOP_LOGIC_OUTS_L_B19_8" + ], + [ + "CMT_FIFO_L_IMUX47_2", + "CMT_TOP_IMUX47_2" + ], + [ + "CMT_FIFO_EE4B0_9", + "CMT_TOP_EE4B0_9" + ], + [ + "CMT_FIFO_NW4A3_0", + "CMT_TOP_NW4A3_0" + ], + [ + "CMT_FIFO_NW4A0_7", + "CMT_TOP_NW4A0_7" + ], + [ + "CMT_FIFO_NE4C0_2", + "CMT_TOP_NE4C0_2" + ], + [ + "CMT_FIFO_WW2A2_5", + "CMT_TOP_WW2A2_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_5", + "CMT_TOP_LOGIC_OUTS_L_B2_5" + ], + [ + "CMT_FIFO_WW4B2_1", + "CMT_TOP_WW4B2_1" + ], + [ + "CMT_FIFO_WW2END1_8", + "CMT_TOP_WW2END1_8" + ], + [ + "CMT_FIFO_L_IMUX38_0", + "CMT_TOP_IMUX38_0" + ], + [ + "CMT_FIFO_L_IMUX14_11", + "CMT_TOP_IMUX14_11" + ], + [ + "CMT_FIFO_SE4BEG2_1", + "CMT_TOP_SE4BEG2_1" + ], + [ + "CMT_FIFO_L_IMUX36_6", + "CMT_TOP_IMUX36_6" + ], + [ + "CMT_FIFO_L_IMUX37_11", + "CMT_TOP_IMUX37_11" + ], + [ + "CMT_FIFO_EE4BEG3_11", + "CMT_TOP_EE4BEG3_11" + ], + [ + "CMT_FIFO_WW4A0_4", + "CMT_TOP_WW4A0_4" + ], + [ + "CMT_FIFO_EE4BEG1_5", + "CMT_TOP_EE4BEG1_5" + ], + [ + "CMT_FIFO_EE4BEG2_10", + "CMT_TOP_EE4BEG2_10" + ], + [ + "CMT_FIFO_NE2A0_3", + "CMT_TOP_NE2A0_3" + ], + [ + "CMT_FIFO_NE2A0_1", + "CMT_TOP_NE2A0_1" + ], + [ + "CMT_FIFO_EE4A1_6", + "CMT_TOP_EE4A1_6" + ], + [ + "CMT_FIFO_L_FAN7_10", + "CMT_TOP_FAN7_10" + ], + [ + "CMT_FIFO_L_IMUX37_0", + "CMT_TOP_IMUX37_0" + ], + [ + "CMT_FIFO_SW4A3_7", + "CMT_TOP_SW4A3_7" + ], + [ + "CMT_FIFO_LH11_8", + "CMT_TOP_LH11_8" + ], + [ + "CMT_FIFO_L_BYP5_4", + "CMT_TOP_BYP5_4" + ], + [ + "CMT_FIFO_WL1END0_4", + "CMT_TOP_WL1END0_4" + ], + [ + "CMT_FIFO_L_IMUX40_8", + "CMT_TOP_IMUX40_8" + ], + [ + "CMT_FIFO_LH8_4", + "CMT_TOP_LH8_4" + ], + [ + "CMT_FIFO_EL1BEG2_4", + "CMT_TOP_EL1BEG2_4" + ], + [ + "CMT_FIFO_EE2A3_7", + "CMT_TOP_EE2A3_7" + ], + [ + "CMT_FIFO_NE4C0_11", + "CMT_TOP_NE4C0_11" + ], + [ + "CMT_FIFO_WW2A0_2", + "CMT_TOP_WW2A0_2" + ], + [ + "CMT_FIFO_WW2A3_0", + "CMT_TOP_WW2A3_0" + ], + [ + "CMT_FIFO_WW4A3_7", + "CMT_TOP_WW4A3_7" + ], + [ + "CMT_FIFO_SE2A0_1", + "CMT_TOP_SE2A0_1" + ], + [ + "CMT_FIFO_WW4C1_8", + "CMT_TOP_WW4C1_8" + ], + [ + "CMT_FIFO_NW4END3_1", + "CMT_TOP_NW4END3_1" + ], + [ + "CMT_FIFO_L_IMUX11_7", + "CMT_TOP_IMUX11_7" + ], + [ + "CMT_FIFO_NE4C1_5", + "CMT_TOP_NE4C1_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_7", + "CMT_TOP_LOGIC_OUTS_L_B8_7" + ], + [ + "CMT_FIFO_L_IMUX41_6", + "CMT_TOP_IMUX41_6" + ], + [ + "CMT_FIFO_SE4BEG3_5", + "CMT_TOP_SE4BEG3_5" + ], + [ + "CMT_FIFO_L_IMUX6_2", + "CMT_TOP_IMUX6_2" + ], + [ + "CMT_FIFO_L_IMUX12_8", + "CMT_TOP_IMUX12_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_4", + "CMT_TOP_LOGIC_OUTS_L_B22_4" + ], + [ + "CMT_FIFO_SW4A1_11", + "CMT_TOP_SW4A1_11" + ], + [ + "CMT_FIFO_L_FAN5_7", + "CMT_TOP_FAN5_7" + ], + [ + "CMT_FIFO_L_CLK0_0", + "CMT_TOP_CLK0_0" + ], + [ + "CMT_FIFO_L_IMUX20_9", + "CMT_TOP_IMUX20_9" + ], + [ + "CMT_FIFO_L_BYP6_11", + "CMT_TOP_BYP6_11" + ], + [ + "CMT_FIFO_SW4A0_4", + "CMT_TOP_SW4A0_4" + ], + [ + "CMT_FIFO_EE2BEG0_8", + "CMT_TOP_EE2BEG0_8" + ], + [ + "CMT_FIFO_NE4BEG0_8", + "CMT_TOP_NE4BEG0_8" + ], + [ + "CMT_FIFO_LH4_4", + "CMT_TOP_LH4_4" + ], + [ + "CMT_FIFO_L_IMUX34_2", + "CMT_TOP_IMUX34_2" + ], + [ + "CMT_FIFO_L_IMUX0_1", + "CMT_TOP_IMUX0_1" + ], + [ + "CMT_FIFO_NW2A2_8", + "CMT_TOP_NW2A2_8" + ], + [ + "CMT_FIFO_L_IMUX10_2", + "CMT_TOP_IMUX10_2" + ], + [ + "CMT_FIFO_L_FAN0_1", + "CMT_TOP_FAN0_1" + ], + [ + "CMT_FIFO_LH12_4", + "CMT_TOP_LH12_4" + ], + [ + "CMT_FIFO_EL1BEG3_4", + "CMT_TOP_EL1BEG3_4" + ], + [ + "CMT_FIFO_WW4END0_11", + "CMT_TOP_WW4END0_11" + ], + [ + "CMT_FIFO_EE2A3_0", + "CMT_TOP_EE2A3_0" + ], + [ + "CMT_FIFO_L_IMUX12_9", + "CMT_TOP_IMUX12_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_4", + "CMT_TOP_LOGIC_OUTS_L_B18_4" + ], + [ + "CMT_FIFO_EE4C3_0", + "CMT_TOP_EE4C3_0" + ], + [ + "CMT_FIFO_NW4END1_0", + "CMT_TOP_NW4END1_0" + ], + [ + "CMT_FIFO_SE4C0_3", + "CMT_TOP_SE4C0_3" + ], + [ + "CMT_FIFO_L_IMUX2_6", + "CMT_TOP_IMUX2_6" + ], + [ + "CMT_FIFO_WW4END0_6", + "CMT_TOP_WW4END0_6" + ], + [ + "CMT_FIFO_L_FAN6_10", + "CMT_TOP_FAN6_10" + ], + [ + "CMT_FIFO_L_IMUX9_4", + "CMT_TOP_IMUX9_4" + ], + [ + "CMT_FIFO_EE4BEG1_1", + "CMT_TOP_EE4BEG1_1" + ], + [ + "CMT_FIFO_L_IMUX32_9", + "CMT_TOP_IMUX32_9" + ], + [ + "CMT_FIFO_EE2A1_4", + "CMT_TOP_EE2A1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_8", + "CMT_TOP_LOGIC_OUTS_L_B11_8" + ], + [ + "CMT_FIFO_L_IMUX43_4", + "CMT_TOP_IMUX43_4" + ], + [ + "CMT_FIFO_NW4A0_3", + "CMT_TOP_NW4A0_3" + ], + [ + "CMT_FIFO_WW4END3_2", + "CMT_TOP_WW4END3_2" + ], + [ + "CMT_FIFO_NW4END1_2", + "CMT_TOP_NW4END1_2" + ], + [ + "CMT_FIFO_EL1BEG3_9", + "CMT_TOP_EL1BEG3_9" + ], + [ + "CMT_FIFO_L_FAN3_9", + "CMT_TOP_FAN3_9" + ], + [ + "CMT_FIFO_EE4B2_3", + "CMT_TOP_EE4B2_3" + ], + [ + "CMT_FIFO_WW4A1_2", + "CMT_TOP_WW4A1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_11", + "CMT_TOP_LOGIC_OUTS_L_B13_11" + ], + [ + "CMT_FIFO_LH5_10", + "CMT_TOP_LH5_10" + ], + [ + "CMT_FIFO_EE4BEG0_11", + "CMT_TOP_EE4BEG0_11" + ], + [ + "CMT_FIFO_EE4A0_6", + "CMT_TOP_EE4A0_6" + ], + [ + "CMT_FIFO_LH10_5", + "CMT_TOP_LH10_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_6", + "CMT_TOP_LOGIC_OUTS_L_B13_6" + ], + [ + "CMT_FIFO_EE4BEG3_8", + "CMT_TOP_EE4BEG3_8" + ], + [ + "CMT_FIFO_L_IMUX17_4", + "CMT_TOP_IMUX17_4" + ], + [ + "CMT_FIFO_L_IMUX6_4", + "CMT_TOP_IMUX6_4" + ], + [ + "CMT_FIFO_LH11_0", + "CMT_TOP_LH11_0" + ], + [ + "CMT_FIFO_L_IMUX30_0", + "CMT_TOP_IMUX30_0" + ], + [ + "CMT_FIFO_L_FAN6_9", + "CMT_TOP_FAN6_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "CMT_TOP_ICLK_5" + ], + [ + "CMT_FIFO_L_IMUX36_1", + "CMT_TOP_IMUX36_1" + ], + [ + "CMT_FIFO_L_IMUX3_0", + "CMT_TOP_IMUX3_0" + ], + [ + "CMT_FIFO_L_IMUX41_7", + "CMT_TOP_IMUX41_7" + ], + [ + "CMT_FIFO_L_IMUX6_3", + "CMT_TOP_IMUX6_3" + ], + [ + "CMT_FIFO_NE2A3_1", + "CMT_TOP_NE2A3_1" + ], + [ + "CMT_FIFO_ER1BEG3_4", + "CMT_TOP_ER1BEG3_4" + ], + [ + "CMT_FIFO_L_IMUX8_1", + "CMT_TOP_IMUX8_1" + ], + [ + "CMT_FIFO_SE2A0_3", + "CMT_TOP_SE2A0_3" + ], + [ + "CMT_FIFO_EE4B3_2", + "CMT_TOP_EE4B3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_8", + "CMT_TOP_LOGIC_OUTS_L_B5_8" + ], + [ + "CMT_FIFO_NW4END0_1", + "CMT_TOP_NW4END0_1" + ], + [ + "CMT_FIFO_EL1BEG1_10", + "CMT_TOP_EL1BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX5_5", + "CMT_TOP_IMUX5_5" + ], + [ + "CMT_FIFO_L_FAN2_0", + "CMT_TOP_FAN2_0" + ], + [ + "CMT_FIFO_EE4B0_5", + "CMT_TOP_EE4B0_5" + ], + [ + "CMT_FIFO_NW4A2_4", + "CMT_TOP_NW4A2_4" + ], + [ + "CMT_FIFO_NW4END2_0", + "CMT_TOP_NW4END2_0" + ], + [ + "CMT_FIFO_WW4END3_8", + "CMT_TOP_WW4END3_8" + ], + [ + "CMT_FIFO_LH9_4", + "CMT_TOP_LH9_4" + ], + [ + "CMT_FIFO_NE4BEG1_7", + "CMT_TOP_NE4BEG1_7" + ], + [ + "CMT_FIFO_SW4A1_9", + "CMT_TOP_SW4A1_9" + ], + [ + "CMT_FIFO_SE4BEG1_4", + "CMT_TOP_SE4BEG1_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_2", + "CMT_TOP_LOGIC_OUTS_L_B7_2" + ], + [ + "CMT_FIFO_L_CTRL1_9", + "CMT_TOP_CTRL1_9" + ], + [ + "CMT_FIFO_L_IMUX13_2", + "CMT_TOP_IMUX13_2" + ], + [ + "CMT_FIFO_WW4A1_11", + "CMT_TOP_WW4A1_11" + ], + [ + "CMT_FIFO_L_IMUX25_1", + "CMT_TOP_IMUX25_1" + ], + [ + "CMT_FIFO_L_FAN4_9", + "CMT_TOP_FAN4_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_0", + "CMT_TOP_LOGIC_OUTS_L_B15_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "CMT_TOP_ICLK_4" + ], + [ + "CMT_FIFO_SW2A1_11", + "CMT_TOP_SW2A1_11" + ], + [ + "CMT_FIFO_EE4BEG3_7", + "CMT_TOP_EE4BEG3_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_2", + "CMT_TOP_LOGIC_OUTS_L_B6_2" + ], + [ + "CMT_FIFO_SE4BEG1_9", + "CMT_TOP_SE4BEG1_9" + ], + [ + "CMT_FIFO_WW4C0_3", + "CMT_TOP_WW4C0_3" + ], + [ + "CMT_FIFO_SW2A1_3", + "CMT_TOP_SW2A1_3" + ], + [ + "CMT_FIFO_SE4C0_5", + "CMT_TOP_SE4C0_5" + ], + [ + "CMT_FIFO_EE2A0_5", + "CMT_TOP_EE2A0_5" + ], + [ + "CMT_FIFO_SE4C1_4", + "CMT_TOP_SE4C1_4" + ], + [ + "CMT_FIFO_EL1BEG0_8", + "CMT_TOP_EL1BEG0_8" + ], + [ + "CMT_FIFO_WW4A1_8", + "CMT_TOP_WW4A1_8" + ], + [ + "CMT_FIFO_NW2A1_7", + "CMT_TOP_NW2A1_7" + ], + [ + "CMT_FIFO_NE2A1_2", + "CMT_TOP_NE2A1_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_8", + "CMT_TOP_LOGIC_OUTS_L_B8_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_0", + "CMT_TOP_LOGIC_OUTS_L_B12_0" + ], + [ + "CMT_FIFO_SW4A3_2", + "CMT_TOP_SW4A3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_9", + "CMT_TOP_LOGIC_OUTS_L_B5_9" + ], + [ + "CMT_FIFO_L_CTRL1_3", + "CMT_TOP_CTRL1_3" + ], + [ + "CMT_FIFO_L_IMUX20_11", + "CMT_TOP_IMUX20_11" + ], + [ + "CMT_FIFO_ER1BEG3_0", + "CMT_TOP_ER1BEG3_0" + ], + [ + "CMT_FIFO_NW4A2_8", + "CMT_TOP_NW4A2_8" + ], + [ + "CMT_FIFO_NE4BEG0_2", + "CMT_TOP_NE4BEG0_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_7", + "CMT_TOP_LOGIC_OUTS_L_B22_7" + ], + [ + "CMT_FIFO_SW4END0_10", + "CMT_TOP_SW4END0_10" + ], + [ + "CMT_FIFO_EE2A1_7", + "CMT_TOP_EE2A1_7" + ], + [ + "CMT_FIFO_LH9_5", + "CMT_TOP_LH9_5" + ], + [ + "CMT_FIFO_NE4BEG0_6", + "CMT_TOP_NE4BEG0_6" + ], + [ + "CMT_FIFO_EE2BEG2_3", + "CMT_TOP_EE2BEG2_3" + ], + [ + "CMT_FIFO_L_IMUX40_6", + "CMT_TOP_IMUX40_6" + ], + [ + "CMT_FIFO_WW4END1_4", + "CMT_TOP_WW4END1_4" + ], + [ + "CMT_FIFO_NE2A2_9", + "CMT_TOP_NE2A2_9" + ], + [ + "CMT_FIFO_SW2A1_2", + "CMT_TOP_SW2A1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "CMT_TOP_OCLK_8" + ], + [ + "CMT_FIFO_EE2A0_7", + "CMT_TOP_EE2A0_7" + ], + [ + "CMT_FIFO_WW4B0_7", + "CMT_TOP_WW4B0_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "CMT_TOP_OCLKDIV_9" + ], + [ + "CMT_FIFO_L_CTRL1_4", + "CMT_TOP_CTRL1_4" + ], + [ + "CMT_FIFO_L_IMUX37_7", + "CMT_TOP_IMUX37_7" + ], + [ + "CMT_FIFO_WW4A2_4", + "CMT_TOP_WW4A2_4" + ], + [ + "CMT_FIFO_MONITOR_N_6", + "CMT_TOP_MONITOR_N_6" + ], + [ + "CMT_FIFO_WR1END0_8", + "CMT_TOP_WR1END0_8" + ], + [ + "CMT_FIFO_WW2END3_4", + "CMT_TOP_WW2END3_4" + ], + [ + "CMT_FIFO_L_BYP1_2", + "CMT_TOP_BYP1_2" + ], + [ + "CMT_FIFO_L_IMUX46_11", + "CMT_TOP_IMUX46_11" + ], + [ + "CMT_FIFO_EE4BEG0_3", + "CMT_TOP_EE4BEG0_3" + ], + [ + "CMT_FIFO_L_BYP0_9", + "CMT_TOP_BYP0_9" + ], + [ + "CMT_FIFO_EE4BEG0_7", + "CMT_TOP_EE4BEG0_7" + ], + [ + "CMT_FIFO_SE4BEG0_6", + "CMT_TOP_SE4BEG0_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_8", + "CMT_TOP_LOGIC_OUTS_L_B18_8" + ], + [ + "CMT_FIFO_L_IMUX27_11", + "CMT_TOP_IMUX27_11" + ], + [ + "CMT_FIFO_SE2A1_6", + "CMT_TOP_SE2A1_6" + ], + [ + "CMT_FIFO_NW4A0_4", + "CMT_TOP_NW4A0_4" + ], + [ + "CMT_FIFO_L_IMUX39_1", + "CMT_TOP_IMUX39_1" + ], + [ + "CMT_FIFO_EE4C2_4", + "CMT_TOP_EE4C2_4" + ], + [ + "CMT_FIFO_NE2A0_5", + "CMT_TOP_NE2A0_5" + ], + [ + "CMT_FIFO_L_CLK0_5", + "CMT_TOP_CLK0_5" + ], + [ + "CMT_FIFO_L_IMUX24_0", + "CMT_TOP_IMUX24_0" + ], + [ + "CMT_FIFO_EE4A2_5", + "CMT_TOP_EE4A2_5" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "CMT_TOP_OCLK_6" + ], + [ + "CMT_FIFO_L_IMUX8_7", + "CMT_TOP_IMUX8_7" + ], + [ + "CMT_FIFO_L_IMUX36_0", + "CMT_TOP_IMUX36_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_10", + "CMT_TOP_LOGIC_OUTS_L_B11_10" + ], + [ + "CMT_FIFO_L_IMUX39_2", + "CMT_TOP_IMUX39_2" + ], + [ + "CMT_FIFO_L_IMUX9_6", + "CMT_TOP_IMUX9_6" + ], + [ + "CMT_FIFO_NW4A1_4", + "CMT_TOP_NW4A1_4" + ], + [ + "CMT_FIFO_EE4C1_2", + "CMT_TOP_EE4C1_2" + ], + [ + "CMT_FIFO_L_IMUX44_0", + "CMT_TOP_IMUX44_0" + ], + [ + "CMT_FIFO_L_IMUX14_6", + "CMT_TOP_IMUX14_6" + ], + [ + "CMT_FIFO_L_IMUX16_10", + "CMT_TOP_IMUX16_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_5", + "CMT_TOP_LOGIC_OUTS_L_B19_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_4", + "CMT_TOP_LOGIC_OUTS_L_B15_4" + ], + [ + "CMT_FIFO_EE4A0_3", + "CMT_TOP_EE4A0_3" + ], + [ + "CMT_FIFO_L_FAN6_2", + "CMT_TOP_FAN6_2" + ], + [ + "CMT_FIFO_WW4B2_11", + "CMT_TOP_WW4B2_11" + ], + [ + "CMT_FIFO_L_BYP0_11", + "CMT_TOP_BYP0_11" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "CMT_TOP_ICLKDIV_0" + ], + [ + "CMT_FIFO_WW4C2_0", + "CMT_TOP_WW4C2_0" + ], + [ + "CMT_FIFO_L_IMUX28_1", + "CMT_TOP_IMUX28_1" + ], + [ + "CMT_FIFO_WW4B1_6", + "CMT_TOP_WW4B1_6" + ], + [ + "CMT_FIFO_EE4BEG0_4", + "CMT_TOP_EE4BEG0_4" + ], + [ + "CMT_FIFO_EE2A2_3", + "CMT_TOP_EE2A2_3" + ], + [ + "CMT_FIFO_EE4BEG1_9", + "CMT_TOP_EE4BEG1_9" + ], + [ + "CMT_FIFO_SE2A1_2", + "CMT_TOP_SE2A1_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "CMT_TOP_ICLK_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_1", + "CMT_TOP_LOGIC_OUTS_L_B1_1" + ], + [ + "CMT_FIFO_WR1END2_6", + "CMT_TOP_WR1END2_6" + ], + [ + "CMT_FIFO_NW4END0_9", + "CMT_TOP_NW4END0_9" + ], + [ + "CMT_FIFO_EE4C2_3", + "CMT_TOP_EE4C2_3" + ], + [ + "CMT_FIFO_SE4C0_7", + "CMT_TOP_SE4C0_7" + ], + [ + "CMT_FIFO_SW4A3_6", + "CMT_TOP_SW4A3_6" + ], + [ + "CMT_FIFO_L_IMUX15_7", + "CMT_TOP_IMUX15_7" + ], + [ + "CMT_FIFO_L_FAN0_9", + "CMT_TOP_FAN0_9" + ], + [ + "CMT_FIFO_L_IMUX35_7", + "CMT_TOP_IMUX35_7" + ], + [ + "CMT_FIFO_ER1BEG0_5", + "CMT_TOP_ER1BEG0_5" + ], + [ + "CMT_FIFO_L_IMUX6_0", + "CMT_TOP_IMUX6_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_4", + "CMT_TOP_LOGIC_OUTS_L_B0_4" + ], + [ + "CMT_FIFO_NE4C0_6", + "CMT_TOP_NE4C0_6" + ], + [ + "CMT_FIFO_EE2A0_8", + "CMT_TOP_EE2A0_8" + ], + [ + "CMT_FIFO_EE4BEG3_4", + "CMT_TOP_EE4BEG3_4" + ], + [ + "CMT_FIFO_NE2A3_3", + "CMT_TOP_NE2A3_3" + ], + [ + "CMT_FIFO_SW2A3_4", + "CMT_TOP_SW2A3_4" + ], + [ + "CMT_FIFO_LH6_0", + "CMT_TOP_LH6_0" + ], + [ + "CMT_FIFO_EE2BEG3_0", + "CMT_TOP_EE2BEG3_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_0", + "CMT_TOP_LOGIC_OUTS_L_B1_0" + ], + [ + "CMT_FIFO_SW2A2_7", + "CMT_TOP_SW2A2_7" + ], + [ + "CMT_FIFO_EE4B2_11", + "CMT_TOP_EE4B2_11" + ], + [ + "CMT_FIFO_WW4END2_6", + "CMT_TOP_WW4END2_6" + ], + [ + "CMT_FIFO_WW4B3_10", + "CMT_TOP_WW4B3_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_1", + "CMT_TOP_LOGIC_OUTS_L_B5_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_5", + "CMT_TOP_LOGIC_OUTS_L_B9_5" + ], + [ + "CMT_FIFO_SW2A2_1", + "CMT_TOP_SW2A2_1" + ], + [ + "CMT_FIFO_EE2A1_11", + "CMT_TOP_EE2A1_11" + ], + [ + "CMT_FIFO_L_IMUX3_6", + "CMT_TOP_IMUX3_6" + ], + [ + "CMT_FIFO_NE4BEG2_5", + "CMT_TOP_NE4BEG2_5" + ], + [ + "CMT_FIFO_L_FAN5_5", + "CMT_TOP_FAN5_5" + ], + [ + "CMT_FIFO_NE4BEG0_7", + "CMT_TOP_NE4BEG0_7" + ], + [ + "CMT_FIFO_L_IMUX14_3", + "CMT_TOP_IMUX14_3" + ], + [ + "CMT_FIFO_EE2BEG0_10", + "CMT_TOP_EE2BEG0_10" + ], + [ + "CMT_FIFO_L_BYP1_8", + "CMT_TOP_BYP1_8" + ], + [ + "CMT_FIFO_L_IMUX19_4", + "CMT_TOP_IMUX19_4" + ], + [ + "CMT_FIFO_LH4_2", + "CMT_TOP_LH4_2" + ], + [ + "CMT_FIFO_WW2A1_8", + "CMT_TOP_WW2A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6" + ], + [ + "CMT_FIFO_WL1END3_2", + "CMT_TOP_WL1END3_2" + ], + [ + "CMT_FIFO_L_IMUX29_1", + "CMT_TOP_IMUX29_1" + ], + [ + "CMT_FIFO_SW4A1_0", + "CMT_TOP_SW4A1_0" + ], + [ + "CMT_FIFO_EE2A3_8", + "CMT_TOP_EE2A3_8" + ], + [ + "CMT_FIFO_L_CLK1_0", + "CMT_TOP_CLK1_0" + ], + [ + "CMT_FIFO_L_IMUX26_7", + "CMT_TOP_IMUX26_7" + ], + [ + "CMT_FIFO_EE4C1_11", + "CMT_TOP_EE4C1_11" + ], + [ + "CMT_FIFO_NE2A0_7", + "CMT_TOP_NE2A0_7" + ], + [ + "CMT_FIFO_LH6_9", + "CMT_TOP_LH6_9" + ], + [ + "CMT_FIFO_NW2A3_4", + "CMT_TOP_NW2A3_4" + ], + [ + "CMT_FIFO_EE2A3_11", + "CMT_TOP_EE2A3_11" + ], + [ + "CMT_FIFO_L_IMUX3_8", + "CMT_TOP_IMUX3_8" + ], + [ + "CMT_FIFO_NE4C2_5", + "CMT_TOP_NE4C2_5" + ], + [ + "CMT_FIFO_L_BYP2_1", + "CMT_TOP_BYP2_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "CMT_TOP_OCLK_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_2", + "CMT_TOP_LOGIC_OUTS_L_B0_2" + ], + [ + "CMT_FIFO_L_IMUX28_9", + "CMT_TOP_IMUX28_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_2", + "CMT_TOP_LOGIC_OUTS_L_B14_2" + ], + [ + "CMT_FIFO_L_IMUX27_4", + "CMT_TOP_IMUX27_4" + ], + [ + "CMT_FIFO_SE4BEG3_1", + "CMT_TOP_SE4BEG3_1" + ], + [ + "CMT_FIFO_NE4C2_9", + "CMT_TOP_NE4C2_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "CMT_TOP_OCLK_1" + ], + [ + "CMT_FIFO_NE4BEG3_11", + "CMT_TOP_NE4BEG3_11" + ], + [ + "CMT_FIFO_ER1BEG1_9", + "CMT_TOP_ER1BEG1_9" + ], + [ + "CMT_FIFO_LH3_4", + "CMT_TOP_LH3_4" + ], + [ + "CMT_FIFO_LH5_7", + "CMT_TOP_LH5_7" + ], + [ + "CMT_FIFO_L_FAN2_7", + "CMT_TOP_FAN2_7" + ], + [ + "CMT_FIFO_WW2END2_3", + "CMT_TOP_WW2END2_3" + ], + [ + "CMT_FIFO_L_IMUX25_4", + "CMT_TOP_IMUX25_4" + ], + [ + "CMT_FIFO_L_IMUX40_1", + "CMT_TOP_IMUX40_1" + ], + [ + "CMT_FIFO_WL1END0_0", + "CMT_TOP_WL1END0_0" + ], + [ + "CMT_FIFO_L_BYP2_7", + "CMT_TOP_BYP2_7" + ], + [ + "CMT_FIFO_L_CTRL1_8", + "CMT_TOP_CTRL1_8" + ], + [ + "CMT_FIFO_EE4B3_3", + "CMT_TOP_EE4B3_3" + ], + [ + "CMT_FIFO_L_IMUX0_11", + "CMT_TOP_IMUX0_11" + ], + [ + "CMT_FIFO_WW2A1_5", + "CMT_TOP_WW2A1_5" + ], + [ + "CMT_FIFO_WL1END0_1", + "CMT_TOP_WL1END0_1" + ], + [ + "CMT_FIFO_L_BYP4_8", + "CMT_TOP_BYP4_8" + ], + [ + "CMT_FIFO_NW4A1_9", + "CMT_TOP_NW4A1_9" + ], + [ + "CMT_FIFO_NW4END1_9", + "CMT_TOP_NW4END1_9" + ], + [ + "CMT_FIFO_WR1END2_1", + "CMT_TOP_WR1END2_1" + ], + [ + "CMT_FIFO_EE4A3_3", + "CMT_TOP_EE4A3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_0", + "CMT_TOP_LOGIC_OUTS_L_B20_0" + ], + [ + "CMT_FIFO_SE2A2_6", + "CMT_TOP_SE2A2_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_1", + "CMT_TOP_LOGIC_OUTS_L_B13_1" + ], + [ + "CMT_FIFO_L_IMUX6_5", + "CMT_TOP_IMUX6_5" + ], + [ + "CMT_FIFO_WR1END2_10", + "CMT_TOP_WR1END2_10" + ], + [ + "CMT_FIFO_LH9_1", + "CMT_TOP_LH9_1" + ], + [ + "CMT_FIFO_NW4A3_9", + "CMT_TOP_NW4A3_9" + ], + [ + "CMT_FIFO_SE2A3_6", + "CMT_TOP_SE2A3_6" + ], + [ + "CMT_FIFO_L_IMUX44_4", + "CMT_TOP_IMUX44_4" + ], + [ + "CMT_FIFO_L_IMUX35_6", + "CMT_TOP_IMUX35_6" + ], + [ + "CMT_FIFO_WR1END3_8", + "CMT_TOP_WR1END3_8" + ], + [ + "CMT_FIFO_NW2A0_11", + "CMT_TOP_NW2A0_11" + ], + [ + "CMT_FIFO_L_IMUX33_9", + "CMT_TOP_IMUX33_9" + ], + [ + "CMT_FIFO_EE2BEG1_9", + "CMT_TOP_EE2BEG1_9" + ], + [ + "CMT_FIFO_SE2A3_7", + "CMT_TOP_SE2A3_7" + ], + [ + "CMT_FIFO_EE4B3_4", + "CMT_TOP_EE4B3_4" + ], + [ + "CMT_FIFO_L_IMUX19_7", + "CMT_TOP_IMUX19_7" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "CMT_TOP_OCLK_0" + ], + [ + "CMT_FIFO_L_IMUX6_8", + "CMT_TOP_IMUX6_8" + ], + [ + "CMT_FIFO_L_CTRL0_4", + "CMT_TOP_CTRL0_4" + ], + [ + "CMT_FIFO_L_IMUX29_4", + "CMT_TOP_IMUX29_4" + ], + [ + "CMT_FIFO_WW4A1_10", + "CMT_TOP_WW4A1_10" + ], + [ + "CMT_FIFO_NE2A1_3", + "CMT_TOP_NE2A1_3" + ], + [ + "CMT_FIFO_L_IMUX46_0", + "CMT_TOP_IMUX46_0" + ], + [ + "CMT_FIFO_WW4B3_8", + "CMT_TOP_WW4B3_8" + ], + [ + "CMT_FIFO_L_IMUX35_8", + "CMT_TOP_IMUX35_8" + ], + [ + "CMT_FIFO_SW4END0_0", + "CMT_TOP_SW4END0_0" + ], + [ + "CMT_FIFO_EE4BEG2_0", + "CMT_TOP_EE4BEG2_0" + ], + [ + "CMT_FIFO_MONITOR_N_10", + "CMT_TOP_MONITOR_N_10" + ], + [ + "CMT_FIFO_L_FAN3_7", + "CMT_TOP_FAN3_7" + ], + [ + "CMT_FIFO_WW2END2_2", + "CMT_TOP_WW2END2_2" + ], + [ + "CMT_FIFO_EE4A1_8", + "CMT_TOP_EE4A1_8" + ], + [ + "CMT_FIFO_NW4END2_6", + "CMT_TOP_NW4END2_6" + ], + [ + "CMT_FIFO_EE2A0_11", + "CMT_TOP_EE2A0_11" + ], + [ + "CMT_FIFO_EE4B1_8", + "CMT_TOP_EE4B1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_1", + "CMT_TOP_LOGIC_OUTS_L_B22_1" + ], + [ + "CMT_FIFO_LH2_5", + "CMT_TOP_LH2_5" + ], + [ + "CMT_FIFO_L_IMUX39_5", + "CMT_TOP_IMUX39_5" + ], + [ + "CMT_FIFO_SW2A3_10", + "CMT_TOP_SW2A3_10" + ], + [ + "CMT_FIFO_WW4END0_8", + "CMT_TOP_WW4END0_8" + ], + [ + "CMT_FIFO_SE2A3_8", + "CMT_TOP_SE2A3_8" + ], + [ + "CMT_FIFO_L_IMUX29_7", + "CMT_TOP_IMUX29_7" + ], + [ + "CMT_FIFO_L_CTRL0_7", + "CMT_TOP_CTRL0_7" + ], + [ + "CMT_FIFO_L_BYP1_5", + "CMT_TOP_BYP1_5" + ], + [ + "CMT_FIFO_NE2A0_11", + "CMT_TOP_NE2A0_11" + ], + [ + "CMT_FIFO_L_IMUX20_8", + "CMT_TOP_IMUX20_8" + ], + [ + "CMT_FIFO_WR1END1_0", + "CMT_TOP_WR1END1_0" + ], + [ + "CMT_FIFO_EE4BEG1_4", + "CMT_TOP_EE4BEG1_4" + ], + [ + "CMT_FIFO_WW2END2_10", + "CMT_TOP_WW2END2_10" + ], + [ + "CMT_FIFO_L_CTRL0_6", + "CMT_TOP_CTRL0_6" + ], + [ + "CMT_FIFO_WW4C0_4", + "CMT_TOP_WW4C0_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_0", + "CMT_TOP_LOGIC_OUTS_L_B2_0" + ], + [ + "CMT_FIFO_NE2A2_8", + "CMT_TOP_NE2A2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_0", + "CMT_TOP_LOGIC_OUTS_L_B4_0" + ], + [ + "CMT_FIFO_SW4END0_3", + "CMT_TOP_SW4END0_3" + ], + [ + "CMT_FIFO_L_IMUX4_6", + "CMT_TOP_IMUX4_6" + ], + [ + "CMT_FIFO_SW4END0_11", + "CMT_TOP_SW4END0_11" + ], + [ + "CMT_FIFO_EE2A0_1", + "CMT_TOP_EE2A0_1" + ], + [ + "CMT_FIFO_EE4B1_2", + "CMT_TOP_EE4B1_2" + ], + [ + "CMT_FIFO_NE4C3_0", + "CMT_TOP_NE4C3_0" + ], + [ + "CMT_FIFO_L_IMUX40_5", + "CMT_TOP_IMUX40_5" + ], + [ + "CMT_FIFO_WW2END1_2", + "CMT_TOP_WW2END1_2" + ], + [ + "CMT_FIFO_WW2A0_0", + "CMT_TOP_WW2A0_0" + ], + [ + "CMT_FIFO_EE2BEG1_11", + "CMT_TOP_EE2BEG1_11" + ], + [ + "CMT_FIFO_EE4A1_2", + "CMT_TOP_EE4A1_2" + ], + [ + "CMT_FIFO_ER1BEG2_3", + "CMT_TOP_ER1BEG2_3" + ], + [ + "CMT_FIFO_L_IMUX33_2", + "CMT_TOP_IMUX33_2" + ], + [ + "CMT_FIFO_SW2A2_8", + "CMT_TOP_SW2A2_8" + ], + [ + "CMT_FIFO_L_IMUX13_0", + "CMT_TOP_IMUX13_0" + ], + [ + "CMT_FIFO_EE2BEG1_1", + "CMT_TOP_EE2BEG1_1" + ], + [ + "CMT_FIFO_WW4C3_0", + "CMT_TOP_WW4C3_0" + ], + [ + "CMT_FIFO_WL1END1_1", + "CMT_TOP_WL1END1_1" + ], + [ + "CMT_FIFO_L_IMUX18_3", + "CMT_TOP_IMUX18_3" + ], + [ + "CMT_FIFO_WL1END0_9", + "CMT_TOP_WL1END0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_11", + "CMT_TOP_LOGIC_OUTS_L_B4_11" + ], + [ + "CMT_FIFO_L_IMUX44_3", + "CMT_TOP_IMUX44_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_2", + "CMT_TOP_LOGIC_OUTS_L_B19_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5" + ], + [ + "CMT_FIFO_L_IMUX23_7", + "CMT_TOP_IMUX23_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_6", + "CMT_TOP_LOGIC_OUTS_L_B19_6" + ], + [ + "CMT_FIFO_L_IMUX2_0", + "CMT_TOP_IMUX2_0" + ], + [ + "CMT_FIFO_L_IMUX35_9", + "CMT_TOP_IMUX35_9" + ], + [ + "CMT_FIFO_WR1END1_7", + "CMT_TOP_WR1END1_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_4", + "CMT_TOP_LOGIC_OUTS_L_B6_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_9", + "CMT_TOP_LOGIC_OUTS_L_B17_9" + ], + [ + "CMT_FIFO_L_IMUX39_8", + "CMT_TOP_IMUX39_8" + ], + [ + "CMT_FIFO_WR1END3_4", + "CMT_TOP_WR1END3_4" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "CMT_TOP_ICLKDIV_9" + ], + [ + "CMT_FIFO_NE4BEG3_1", + "CMT_TOP_NE4BEG3_1" + ], + [ + "CMT_FIFO_WL1END2_6", + "CMT_TOP_WL1END2_6" + ], + [ + "CMT_FIFO_SE2A3_11", + "CMT_TOP_SE2A3_11" + ], + [ + "CMT_FIFO_NW4A3_7", + "CMT_TOP_NW4A3_7" + ], + [ + "CMT_FIFO_L_BYP0_7", + "CMT_TOP_BYP0_7" + ], + [ + "CMT_FIFO_SW2A0_3", + "CMT_TOP_SW2A0_3" + ], + [ + "CMT_FIFO_EE2BEG2_8", + "CMT_TOP_EE2BEG2_8" + ], + [ + "CMT_FIFO_EE2A1_6", + "CMT_TOP_EE2A1_6" + ], + [ + "CMT_FIFO_EE4C1_7", + "CMT_TOP_EE4C1_7" + ], + [ + "CMT_FIFO_WW4A0_10", + "CMT_TOP_WW4A0_10" + ], + [ + "CMT_FIFO_WR1END2_9", + "CMT_TOP_WR1END2_9" + ], + [ + "CMT_FIFO_WW4C3_6", + "CMT_TOP_WW4C3_6" + ], + [ + "CMT_FIFO_WW4END2_7", + "CMT_TOP_WW4END2_7" + ], + [ + "CMT_FIFO_L_IMUX6_11", + "CMT_TOP_IMUX6_11" + ], + [ + "CMT_FIFO_L_IMUX10_6", + "CMT_TOP_IMUX10_6" + ], + [ + "CMT_FIFO_LH9_7", + "CMT_TOP_LH9_7" + ], + [ + "CMT_FIFO_L_CTRL1_0", + "CMT_TOP_CTRL1_0" + ], + [ + "CMT_FIFO_L_IMUX1_3", + "CMT_TOP_IMUX1_3" + ], + [ + "CMT_FIFO_WW2END3_10", + "CMT_TOP_WW2END3_10" + ], + [ + "CMT_FIFO_WW2A2_1", + "CMT_TOP_WW2A2_1" + ], + [ + "CMT_FIFO_L_CLK1_6", + "CMT_TOP_CLK1_6" + ], + [ + "CMT_FIFO_LH8_9", + "CMT_TOP_LH8_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_8", + "CMT_TOP_LOGIC_OUTS_L_B3_8" + ], + [ + "CMT_FIFO_L_IMUX46_5", + "CMT_TOP_IMUX46_5" + ], + [ + "CMT_FIFO_WW4A1_4", + "CMT_TOP_WW4A1_4" + ], + [ + "CMT_FIFO_L_IMUX25_11", + "CMT_TOP_IMUX25_11" + ], + [ + "CMT_FIFO_L_IMUX2_9", + "CMT_TOP_IMUX2_9" + ], + [ + "CMT_FIFO_SE4C3_0", + "CMT_TOP_SE4C3_0" + ], + [ + "CMT_FIFO_WW4C2_4", + "CMT_TOP_WW4C2_4" + ], + [ + "CMT_FIFO_WW4C1_6", + "CMT_TOP_WW4C1_6" + ], + [ + "CMT_FIFO_L_IMUX38_1", + "CMT_TOP_IMUX38_1" + ], + [ + "CMT_FIFO_MONITOR_P_0", + "CMT_TOP_MONITOR_P_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_0" + ], + [ + "CMT_FIFO_WL1END1_4", + "CMT_TOP_WL1END1_4" + ], + [ + "CMT_FIFO_EE4A2_0", + "CMT_TOP_EE4A2_0" + ], + [ + "CMT_FIFO_EL1BEG3_10", + "CMT_TOP_EL1BEG3_10" + ], + [ + "CMT_FIFO_L_IMUX27_0", + "CMT_TOP_IMUX27_0" + ], + [ + "CMT_FIFO_NE4C0_7", + "CMT_TOP_NE4C0_7" + ], + [ + "CMT_FIFO_ER1BEG1_2", + "CMT_TOP_ER1BEG1_2" + ], + [ + "CMT_FIFO_NE2A1_10", + "CMT_TOP_NE2A1_10" + ], + [ + "CMT_FIFO_SE4BEG3_6", + "CMT_TOP_SE4BEG3_6" + ], + [ + "CMT_FIFO_WL1END3_11", + "CMT_TOP_WL1END3_11" + ], + [ + "CMT_FIFO_SW4A1_6", + "CMT_TOP_SW4A1_6" + ], + [ + "CMT_FIFO_EE4A3_9", + "CMT_TOP_EE4A3_9" + ], + [ + "CMT_FIFO_EL1BEG0_2", + "CMT_TOP_EL1BEG0_2" + ], + [ + "CMT_FIFO_WW4C3_3", + "CMT_TOP_WW4C3_3" + ], + [ + "CMT_FIFO_SW4END0_6", + "CMT_TOP_SW4END0_6" + ], + [ + "CMT_FIFO_L_IMUX41_4", + "CMT_TOP_IMUX41_4" + ], + [ + "CMT_FIFO_L_FAN3_3", + "CMT_TOP_FAN3_3" + ], + [ + "CMT_FIFO_WW4C2_1", + "CMT_TOP_WW4C2_1" + ], + [ + "CMT_FIFO_L_BYP3_2", + "CMT_TOP_BYP3_2" + ], + [ + "CMT_FIFO_L_IMUX8_3", + "CMT_TOP_IMUX8_3" + ], + [ + "CMT_FIFO_LH6_11", + "CMT_TOP_LH6_11" + ], + [ + "CMT_FIFO_EE2A2_9", + "CMT_TOP_EE2A2_9" + ], + [ + "CMT_FIFO_WW2A0_7", + "CMT_TOP_WW2A0_7" + ], + [ + "CMT_FIFO_WW4END2_5", + "CMT_TOP_WW4END2_5" + ], + [ + "CMT_FIFO_WW2END0_7", + "CMT_TOP_WW2END0_7" + ], + [ + "CMT_FIFO_EE4B0_1", + "CMT_TOP_EE4B0_1" + ], + [ + "CMT_FIFO_L_IMUX38_10", + "CMT_TOP_IMUX38_10" + ], + [ + "CMT_FIFO_NE2A2_10", + "CMT_TOP_NE2A2_10" + ], + [ + "CMT_FIFO_EE2A3_2", + "CMT_TOP_EE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX4_3", + "CMT_TOP_IMUX4_3" + ], + [ + "CMT_FIFO_L_FAN2_6", + "CMT_TOP_FAN2_6" + ], + [ + "CMT_FIFO_WW4END0_2", + "CMT_TOP_WW4END0_2" + ], + [ + "CMT_FIFO_NE4BEG0_3", + "CMT_TOP_NE4BEG0_3" + ], + [ + "CMT_FIFO_SW4END3_8", + "CMT_TOP_SW4END3_8" + ], + [ + "CMT_FIFO_LH6_7", + "CMT_TOP_LH6_7" + ], + [ + "CMT_FIFO_WW2END0_6", + "CMT_TOP_WW2END0_6" + ], + [ + "CMT_FIFO_NW4A2_1", + "CMT_TOP_NW4A2_1" + ], + [ + "CMT_FIFO_WW2A3_4", + "CMT_TOP_WW2A3_4" + ], + [ + "CMT_FIFO_SW4A0_8", + "CMT_TOP_SW4A0_8" + ], + [ + "CMT_FIFO_L_IMUX19_6", + "CMT_TOP_IMUX19_6" + ], + [ + "CMT_FIFO_EL1BEG3_0", + "CMT_TOP_EL1BEG3_0" + ], + [ + "CMT_FIFO_LH3_1", + "CMT_TOP_LH3_1" + ], + [ + "CMT_FIFO_L_IMUX10_1", + "CMT_TOP_IMUX10_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_3", + "CMT_TOP_LOGIC_OUTS_L_B16_3" + ], + [ + "CMT_FIFO_WW4END1_10", + "CMT_TOP_WW4END1_10" + ], + [ + "CMT_FIFO_L_IMUX43_6", + "CMT_TOP_IMUX43_6" + ], + [ + "CMT_FIFO_L_FAN2_4", + "CMT_TOP_FAN2_4" + ], + [ + "CMT_FIFO_WR1END2_11", + "CMT_TOP_WR1END2_11" + ], + [ + "CMT_FIFO_NW4END0_11", + "CMT_TOP_NW4END0_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_2", + "CMT_TOP_LOGIC_OUTS_L_B2_2" + ], + [ + "CMT_FIFO_SE4BEG2_11", + "CMT_TOP_SE4BEG2_11" + ], + [ + "CMT_FIFO_EE2A3_3", + "CMT_TOP_EE2A3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_5", + "CMT_TOP_LOGIC_OUTS_L_B22_5" + ], + [ + "CMT_FIFO_SW4A0_0", + "CMT_TOP_SW4A0_0" + ], + [ + "CMT_FIFO_NE4BEG3_7", + "CMT_TOP_NE4BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX9_1", + "CMT_TOP_IMUX9_1" + ], + [ + "CMT_FIFO_NW4A3_2", + "CMT_TOP_NW4A3_2" + ], + [ + "CMT_FIFO_NW4A0_1", + "CMT_TOP_NW4A0_1" + ], + [ + "CMT_FIFO_WW4END0_1", + "CMT_TOP_WW4END0_1" + ], + [ + "CMT_FIFO_L_IMUX37_9", + "CMT_TOP_IMUX37_9" + ], + [ + "CMT_FIFO_L_IMUX7_7", + "CMT_TOP_IMUX7_7" + ], + [ + "CMT_FIFO_NE2A2_6", + "CMT_TOP_NE2A2_6" + ], + [ + "CMT_FIFO_EE2A1_10", + "CMT_TOP_EE2A1_10" + ], + [ + "CMT_FIFO_NE4BEG2_3", + "CMT_TOP_NE4BEG2_3" + ], + [ + "CMT_FIFO_WW2END2_6", + "CMT_TOP_WW2END2_6" + ], + [ + "CMT_FIFO_SW4A2_9", + "CMT_TOP_SW4A2_9" + ], + [ + "CMT_FIFO_L_IMUX1_6", + "CMT_TOP_IMUX1_6" + ], + [ + "CMT_FIFO_L_IMUX18_7", + "CMT_TOP_IMUX18_7" + ], + [ + "CMT_FIFO_WR1END2_2", + "CMT_TOP_WR1END2_2" + ], + [ + "CMT_FIFO_L_IMUX41_3", + "CMT_TOP_IMUX41_3" + ], + [ + "CMT_FIFO_L_IMUX17_9", + "CMT_TOP_IMUX17_9" + ], + [ + "CMT_FIFO_EE4BEG3_5", + "CMT_TOP_EE4BEG3_5" + ], + [ + "CMT_FIFO_NW2A0_1", + "CMT_TOP_NW2A0_1" + ], + [ + "CMT_FIFO_EE4A1_11", + "CMT_TOP_EE4A1_11" + ], + [ + "CMT_FIFO_SE2A0_11", + "CMT_TOP_SE2A0_11" + ], + [ + "CMT_FIFO_L_IMUX10_11", + "CMT_TOP_IMUX10_11" + ], + [ + "CMT_FIFO_L_IMUX47_5", + "CMT_TOP_IMUX47_5" + ], + [ + "CMT_FIFO_L_IMUX42_2", + "CMT_TOP_IMUX42_2" + ], + [ + "CMT_FIFO_L_IMUX36_11", + "CMT_TOP_IMUX36_11" + ], + [ + "CMT_FIFO_LH1_0", + "CMT_TOP_LH1_0" + ], + [ + "CMT_FIFO_L_IMUX5_0", + "CMT_TOP_IMUX5_0" + ], + [ + "CMT_FIFO_L_IMUX17_10", + "CMT_TOP_IMUX17_10" + ], + [ + "CMT_FIFO_WW4C1_2", + "CMT_TOP_WW4C1_2" + ], + [ + "CMT_FIFO_WR1END1_4", + "CMT_TOP_WR1END1_4" + ], + [ + "CMT_FIFO_WW4C3_1", + "CMT_TOP_WW4C3_1" + ], + [ + "CMT_FIFO_EE4C1_5", + "CMT_TOP_EE4C1_5" + ], + [ + "CMT_FIFO_LH5_6", + "CMT_TOP_LH5_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_9", + "CMT_TOP_LOGIC_OUTS_L_B16_9" + ], + [ + "CMT_FIFO_EL1BEG2_5", + "CMT_TOP_EL1BEG2_5" + ], + [ + "CMT_FIFO_L_IMUX3_4", + "CMT_TOP_IMUX3_4" + ], + [ + "CMT_FIFO_L_IMUX21_8", + "CMT_TOP_IMUX21_8" + ], + [ + "CMT_FIFO_L_FAN2_2", + "CMT_TOP_FAN2_2" + ], + [ + "CMT_FIFO_L_IMUX44_6", + "CMT_TOP_IMUX44_6" + ], + [ + "CMT_FIFO_L_BYP3_10", + "CMT_TOP_BYP3_10" + ], + [ + "CMT_FIFO_LH11_6", + "CMT_TOP_LH11_6" + ], + [ + "CMT_FIFO_NE4BEG0_9", + "CMT_TOP_NE4BEG0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_9", + "CMT_TOP_LOGIC_OUTS_L_B12_9" + ], + [ + "CMT_FIFO_L_IMUX7_6", + "CMT_TOP_IMUX7_6" + ], + [ + "CMT_FIFO_EE2A2_5", + "CMT_TOP_EE2A2_5" + ], + [ + "CMT_FIFO_LH11_1", + "CMT_TOP_LH11_1" + ], + [ + "CMT_FIFO_NW2A2_2", + "CMT_TOP_NW2A2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_0" + ], + [ + "CMT_FIFO_SW4A1_2", + "CMT_TOP_SW4A1_2" + ], + [ + "CMT_FIFO_EE4C0_0", + "CMT_TOP_EE4C0_0" + ], + [ + "CMT_FIFO_L_IMUX35_0", + "CMT_TOP_IMUX35_0" + ], + [ + "CMT_FIFO_EE2A3_9", + "CMT_TOP_EE2A3_9" + ], + [ + "CMT_FIFO_L_FAN3_10", + "CMT_TOP_FAN3_10" + ], + [ + "CMT_FIFO_L_BYP4_7", + "CMT_TOP_BYP4_7" + ], + [ + "CMT_FIFO_L_IMUX28_3", + "CMT_TOP_IMUX28_3" + ], + [ + "CMT_FIFO_EE2A0_0", + "CMT_TOP_EE2A0_0" + ], + [ + "CMT_FIFO_L_IMUX21_10", + "CMT_TOP_IMUX21_10" + ], + [ + "CMT_FIFO_SW4END2_5", + "CMT_TOP_SW4END2_5" + ], + [ + "CMT_FIFO_MONITOR_P_2", + "CMT_TOP_MONITOR_P_2" + ], + [ + "CMT_FIFO_SW2A0_8", + "CMT_TOP_SW2A0_8" + ], + [ + "CMT_FIFO_L_IMUX45_7", + "CMT_TOP_IMUX45_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_9", + "CMT_TOP_LOGIC_OUTS_L_B4_9" + ], + [ + "CMT_FIFO_SE4BEG1_3", + "CMT_TOP_SE4BEG1_3" + ], + [ + "CMT_FIFO_WR1END2_0", + "CMT_TOP_WR1END2_0" + ], + [ + "CMT_FIFO_L_CLK1_11", + "CMT_TOP_CLK1_11" + ], + [ + "CMT_FIFO_EE4A3_10", + "CMT_TOP_EE4A3_10" + ], + [ + "CMT_FIFO_SE4BEG2_8", + "CMT_TOP_SE4BEG2_8" + ], + [ + "CMT_FIFO_L_IMUX24_3", + "CMT_TOP_IMUX24_3" + ], + [ + "CMT_FIFO_EE2BEG1_4", + "CMT_TOP_EE2BEG1_4" + ], + [ + "CMT_FIFO_WW4B2_0", + "CMT_TOP_WW4B2_0" + ], + [ + "CMT_FIFO_NE4C0_3", + "CMT_TOP_NE4C0_3" + ], + [ + "CMT_FIFO_L_BYP7_7", + "CMT_TOP_BYP7_7" + ], + [ + "CMT_FIFO_L_FAN7_1", + "CMT_TOP_FAN7_1" + ], + [ + "CMT_FIFO_SW4A3_8", + "CMT_TOP_SW4A3_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "CMT_TOP_ICLK_8" + ], + [ + "CMT_FIFO_EE2A2_4", + "CMT_TOP_EE2A2_4" + ], + [ + "CMT_FIFO_LH6_10", + "CMT_TOP_LH6_10" + ], + [ + "CMT_FIFO_NE2A1_11", + "CMT_TOP_NE2A1_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_4", + "CMT_TOP_LOGIC_OUTS_L_B2_4" + ], + [ + "CMT_FIFO_L_IMUX20_6", + "CMT_TOP_IMUX20_6" + ], + [ + "CMT_FIFO_L_IMUX14_9", + "CMT_TOP_IMUX14_9" + ], + [ + "CMT_FIFO_NW2A1_9", + "CMT_TOP_NW2A1_9" + ], + [ + "CMT_FIFO_SW4END3_6", + "CMT_TOP_SW4END3_6" + ], + [ + "CMT_FIFO_L_BYP6_4", + "CMT_TOP_BYP6_4" + ], + [ + "CMT_FIFO_L_IMUX37_3", + "CMT_TOP_IMUX37_3" + ], + [ + "CMT_FIFO_L_IMUX32_11", + "CMT_TOP_IMUX32_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_2", + "CMT_TOP_LOGIC_OUTS_L_B20_2" + ], + [ + "CMT_FIFO_EL1BEG0_3", + "CMT_TOP_EL1BEG0_3" + ], + [ + "CMT_FIFO_L_IMUX40_11", + "CMT_TOP_IMUX40_11" + ], + [ + "CMT_FIFO_WW4END1_11", + "CMT_TOP_WW4END1_11" + ], + [ + "CMT_FIFO_L_IMUX17_1", + "CMT_TOP_IMUX17_1" + ], + [ + "CMT_FIFO_L_IMUX29_3", + "CMT_TOP_IMUX29_3" + ], + [ + "CMT_FIFO_NW4A1_0", + "CMT_TOP_NW4A1_0" + ], + [ + "CMT_FIFO_SW4A2_6", + "CMT_TOP_SW4A2_6" + ], + [ + "CMT_FIFO_EE4B0_8", + "CMT_TOP_EE4B0_8" + ], + [ + "CMT_FIFO_EE2BEG3_4", + "CMT_TOP_EE2BEG3_4" + ], + [ + "CMT_FIFO_ER1BEG1_10", + "CMT_TOP_ER1BEG1_10" + ], + [ + "CMT_FIFO_L_IMUX43_9", + "CMT_TOP_IMUX43_9" + ], + [ + "CMT_FIFO_LH8_7", + "CMT_TOP_LH8_7" + ], + [ + "CMT_FIFO_EE4B2_1", + "CMT_TOP_EE4B2_1" + ], + [ + "CMT_FIFO_NW4END2_3", + "CMT_TOP_NW4END2_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_0", + "CMT_TOP_LOGIC_OUTS_L_B14_0" + ], + [ + "CMT_FIFO_WW4A3_5", + "CMT_TOP_WW4A3_5" + ], + [ + "CMT_FIFO_L_BYP6_6", + "CMT_TOP_BYP6_6" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "CMT_TOP_ICLKDIV_5" + ], + [ + "CMT_FIFO_L_IMUX3_7", + "CMT_TOP_IMUX3_7" + ], + [ + "CMT_FIFO_WW2A1_4", + "CMT_TOP_WW2A1_4" + ], + [ + "CMT_FIFO_EE4B1_6", + "CMT_TOP_EE4B1_6" + ], + [ + "CMT_FIFO_LH10_4", + "CMT_TOP_LH10_4" + ], + [ + "CMT_FIFO_L_IMUX45_3", + "CMT_TOP_IMUX45_3" + ], + [ + "CMT_FIFO_LH4_0", + "CMT_TOP_LH4_0" + ], + [ + "CMT_FIFO_EE2A1_8", + "CMT_TOP_EE2A1_8" + ], + [ + "CMT_FIFO_EE4C1_8", + "CMT_TOP_EE4C1_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "CMT_TOP_ICLKDIV_1" + ], + [ + "CMT_FIFO_L_IMUX8_11", + "CMT_TOP_IMUX8_11" + ], + [ + "CMT_FIFO_L_IMUX36_3", + "CMT_TOP_IMUX36_3" + ], + [ + "CMT_FIFO_SW4A2_0", + "CMT_TOP_SW4A2_0" + ], + [ + "CMT_FIFO_EE2A3_1", + "CMT_TOP_EE2A3_1" + ], + [ + "CMT_FIFO_WL1END2_8", + "CMT_TOP_WL1END2_8" + ], + [ + "CMT_FIFO_SW4A2_4", + "CMT_TOP_SW4A2_4" + ], + [ + "CMT_FIFO_EE4BEG0_10", + "CMT_TOP_EE4BEG0_10" + ], + [ + "CMT_FIFO_EE4C0_3", + "CMT_TOP_EE4C0_3" + ], + [ + "CMT_FIFO_NE4BEG2_8", + "CMT_TOP_NE4BEG2_8" + ], + [ + "CMT_FIFO_EE2A2_8", + "CMT_TOP_EE2A2_8" + ], + [ + "CMT_FIFO_SW2A3_7", + "CMT_TOP_SW2A3_7" + ], + [ + "CMT_FIFO_WW2A2_9", + "CMT_TOP_WW2A2_9" + ], + [ + "CMT_FIFO_SW4A3_3", + "CMT_TOP_SW4A3_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_4", + "CMT_TOP_LOGIC_OUTS_L_B20_4" + ], + [ + "CMT_FIFO_NE4C3_3", + "CMT_TOP_NE4C3_3" + ], + [ + "CMT_FIFO_WL1END0_10", + "CMT_TOP_WL1END0_10" + ], + [ + "CMT_FIFO_L_IMUX8_5", + "CMT_TOP_IMUX8_5" + ], + [ + "CMT_FIFO_WW4B1_9", + "CMT_TOP_WW4B1_9" + ], + [ + "CMT_FIFO_NW2A0_9", + "CMT_TOP_NW2A0_9" + ], + [ + "CMT_FIFO_EE2A1_2", + "CMT_TOP_EE2A1_2" + ], + [ + "CMT_FIFO_WW4C0_0", + "CMT_TOP_WW4C0_0" + ], + [ + "CMT_FIFO_WW4B0_4", + "CMT_TOP_WW4B0_4" + ], + [ + "CMT_FIFO_NW2A3_3", + "CMT_TOP_NW2A3_3" + ], + [ + "CMT_FIFO_ER1BEG2_8", + "CMT_TOP_ER1BEG2_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "CMT_TOP_OCLKDIV_4" + ], + [ + "CMT_FIFO_WW4C2_10", + "CMT_TOP_WW4C2_10" + ], + [ + "CMT_FIFO_L_CTRL0_1", + "CMT_TOP_CTRL0_1" + ], + [ + "CMT_FIFO_SW2A0_1", + "CMT_TOP_SW2A0_1" + ], + [ + "CMT_FIFO_EE2BEG0_1", + "CMT_TOP_EE2BEG0_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_7", + "CMT_TOP_LOGIC_OUTS_L_B14_7" + ], + [ + "CMT_FIFO_EE2BEG1_6", + "CMT_TOP_EE2BEG1_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_7", + "CMT_TOP_LOGIC_OUTS_L_B11_7" + ], + [ + "CMT_FIFO_L_IMUX12_4", + "CMT_TOP_IMUX12_4" + ], + [ + "CMT_FIFO_EE4B2_0", + "CMT_TOP_EE4B2_0" + ], + [ + "CMT_FIFO_SE4C3_11", + "CMT_TOP_SE4C3_11" + ], + [ + "CMT_FIFO_LH10_7", + "CMT_TOP_LH10_7" + ], + [ + "CMT_FIFO_EE2BEG2_2", + "CMT_TOP_EE2BEG2_2" + ], + [ + "CMT_FIFO_L_IMUX23_1", + "CMT_TOP_IMUX23_1" + ], + [ + "CMT_FIFO_WW4A1_5", + "CMT_TOP_WW4A1_5" + ], + [ + "CMT_FIFO_WR1END0_0", + "CMT_TOP_WR1END0_0" + ], + [ + "CMT_FIFO_ER1BEG1_7", + "CMT_TOP_ER1BEG1_7" + ], + [ + "CMT_FIFO_EE4B2_10", + "CMT_TOP_EE4B2_10" + ], + [ + "CMT_FIFO_WW4A1_6", + "CMT_TOP_WW4A1_6" + ], + [ + "CMT_FIFO_L_IMUX42_9", + "CMT_TOP_IMUX42_9" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "CMT_TOP_ICLK_0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_1", + "CMT_TOP_LOGIC_OUTS_L_B8_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_0", + "CMT_TOP_LOGIC_OUTS_L_B6_0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "CMT_TOP_ICLK_9" + ], + [ + "CMT_FIFO_NE4BEG3_4", + "CMT_TOP_NE4BEG3_4" + ], + [ + "CMT_FIFO_EE2BEG3_9", + "CMT_TOP_EE2BEG3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_6", + "CMT_TOP_LOGIC_OUTS_L_B12_6" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_1", + "CMT_TOP_LOGIC_OUTS_L_B10_1" + ], + [ + "CMT_FIFO_NE2A0_6", + "CMT_TOP_NE2A0_6" + ], + [ + "CMT_FIFO_EE4BEG2_7", + "CMT_TOP_EE4BEG2_7" + ], + [ + "CMT_FIFO_NE4BEG1_1", + "CMT_TOP_NE4BEG1_1" + ], + [ + "CMT_FIFO_EE4C2_5", + "CMT_TOP_EE4C2_5" + ], + [ + "CMT_FIFO_WW4C1_3", + "CMT_TOP_WW4C1_3" + ], + [ + "CMT_FIFO_LH10_8", + "CMT_TOP_LH10_8" + ], + [ + "CMT_FIFO_L_IMUX15_0", + "CMT_TOP_IMUX15_0" + ], + [ + "CMT_FIFO_L_FAN7_3", + "CMT_TOP_FAN7_3" + ], + [ + "CMT_FIFO_L_CLK0_9", + "CMT_TOP_CLK0_9" + ], + [ + "CMT_FIFO_NE4BEG0_5", + "CMT_TOP_NE4BEG0_5" + ], + [ + "CMT_FIFO_WR1END0_5", + "CMT_TOP_WR1END0_5" + ], + [ + "CMT_FIFO_SE4BEG3_7", + "CMT_TOP_SE4BEG3_7" + ], + [ + "CMT_FIFO_L_IMUX38_9", + "CMT_TOP_IMUX38_9" + ], + [ + "CMT_FIFO_EE4C1_3", + "CMT_TOP_EE4C1_3" + ], + [ + "CMT_FIFO_SE4C2_8", + "CMT_TOP_SE4C2_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_2", + "CMT_TOP_LOGIC_OUTS_L_B12_2" + ], + [ + "CMT_FIFO_L_IMUX43_0", + "CMT_TOP_IMUX43_0" + ], + [ + "CMT_FIFO_L_IMUX15_1", + "CMT_TOP_IMUX15_1" + ], + [ + "CMT_FIFO_ER1BEG3_5", + "CMT_TOP_ER1BEG3_5" + ], + [ + "CMT_FIFO_L_BYP6_7", + "CMT_TOP_BYP6_7" + ], + [ + "CMT_FIFO_L_BYP3_3", + "CMT_TOP_BYP3_3" + ], + [ + "CMT_FIFO_NE2A3_11", + "CMT_TOP_NE2A3_11" + ], + [ + "CMT_FIFO_WL1END1_0", + "CMT_TOP_WL1END1_0" + ], + [ + "CMT_FIFO_L_IMUX21_0", + "CMT_TOP_IMUX21_0" + ], + [ + "CMT_FIFO_WL1END1_6", + "CMT_TOP_WL1END1_6" + ], + [ + "CMT_FIFO_L_IMUX26_2", + "CMT_TOP_IMUX26_2" + ], + [ + "CMT_FIFO_WL1END2_4", + "CMT_TOP_WL1END2_4" + ], + [ + "CMT_FIFO_WW4B0_5", + "CMT_TOP_WW4B0_5" + ], + [ + "CMT_FIFO_EE2A3_10", + "CMT_TOP_EE2A3_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_9", + "CMT_TOP_LOGIC_OUTS_L_B8_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_1", + "CMT_TOP_LOGIC_OUTS_L_B15_1" + ], + [ + "CMT_FIFO_WR1END0_7", + "CMT_TOP_WR1END0_7" + ], + [ + "CMT_FIFO_WW4END0_7", + "CMT_TOP_WW4END0_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_10", + "CMT_TOP_LOGIC_OUTS_L_B2_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_11", + "CMT_TOP_LOGIC_OUTS_L_B5_11" + ], + [ + "CMT_FIFO_L_IMUX24_4", + "CMT_TOP_IMUX24_4" + ], + [ + "CMT_FIFO_SE4BEG2_0", + "CMT_TOP_SE4BEG2_0" + ], + [ + "CMT_FIFO_SW2A2_5", + "CMT_TOP_SW2A2_5" + ], + [ + "CMT_FIFO_L_CTRL1_10", + "CMT_TOP_CTRL1_10" + ], + [ + "CMT_FIFO_L_IMUX7_4", + "CMT_TOP_IMUX7_4" + ], + [ + "CMT_FIFO_WW4C1_0", + "CMT_TOP_WW4C1_0" + ], + [ + "CMT_FIFO_L_IMUX47_7", + "CMT_TOP_IMUX47_7" + ], + [ + "CMT_FIFO_EE4A3_2", + "CMT_TOP_EE4A3_2" + ], + [ + "CMT_FIFO_WW4B3_4", + "CMT_TOP_WW4B3_4" + ], + [ + "CMT_FIFO_L_IMUX0_9", + "CMT_TOP_IMUX0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_9", + "CMT_TOP_LOGIC_OUTS_L_B0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_7", + "CMT_TOP_LOGIC_OUTS_L_B18_7" + ], + [ + "CMT_FIFO_WW4A3_2", + "CMT_TOP_WW4A3_2" + ], + [ + "CMT_FIFO_WW4A3_8", + "CMT_TOP_WW4A3_8" + ], + [ + "CMT_FIFO_L_BYP2_11", + "CMT_TOP_BYP2_11" + ], + [ + "CMT_FIFO_L_IMUX5_1", + "CMT_TOP_IMUX5_1" + ], + [ + "CMT_FIFO_L_IMUX5_8", + "CMT_TOP_IMUX5_8" + ], + [ + "CMT_FIFO_EL1BEG3_11", + "CMT_TOP_EL1BEG3_11" + ], + [ + "CMT_FIFO_NW4A1_8", + "CMT_TOP_NW4A1_8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_4", + "CMT_TOP_LOGIC_OUTS_L_B21_4" + ], + [ + "CMT_FIFO_NE4C0_1", + "CMT_TOP_NE4C0_1" + ], + [ + "CMT_FIFO_WW4B0_3", + "CMT_TOP_WW4B0_3" + ], + [ + "CMT_FIFO_SW4A3_0", + "CMT_TOP_SW4A3_0" + ], + [ + "CMT_FIFO_LH10_9", + "CMT_TOP_LH10_9" + ], + [ + "CMT_FIFO_L_IMUX13_3", + "CMT_TOP_IMUX13_3" + ], + [ + "CMT_FIFO_NE4BEG2_7", + "CMT_TOP_NE4BEG2_7" + ], + [ + "CMT_FIFO_L_BYP0_6", + "CMT_TOP_BYP0_6" + ], + [ + "CMT_FIFO_EL1BEG0_11", + "CMT_TOP_EL1BEG0_11" + ], + [ + "CMT_FIFO_LH6_8", + "CMT_TOP_LH6_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "CMT_TOP_ICLK_3" + ], + [ + "CMT_FIFO_L_IMUX28_4", + "CMT_TOP_IMUX28_4" + ], + [ + "CMT_FIFO_WL1END3_9", + "CMT_TOP_WL1END3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_10", + "CMT_TOP_LOGIC_OUTS_L_B15_10" + ], + [ + "CMT_FIFO_SE2A1_3", + "CMT_TOP_SE2A1_3" + ], + [ + "CMT_FIFO_L_IMUX47_10", + "CMT_TOP_IMUX47_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_7", + "CMT_TOP_LOGIC_OUTS_L_B3_7" + ], + [ + "CMT_FIFO_SW2A2_2", + "CMT_TOP_SW2A2_2" + ], + [ + "CMT_FIFO_SW2A3_3", + "CMT_TOP_SW2A3_3" + ], + [ + "CMT_FIFO_EE4A2_10", + "CMT_TOP_EE4A2_10" + ], + [ + "CMT_FIFO_WL1END1_5", + "CMT_TOP_WL1END1_5" + ], + [ + "CMT_FIFO_L_FAN4_1", + "CMT_TOP_FAN4_1" + ], + [ + "CMT_FIFO_L_IMUX21_2", + "CMT_TOP_IMUX21_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_4", + "CMT_TOP_LOGIC_OUTS_L_B12_4" + ], + [ + "CMT_FIFO_LH6_5", + "CMT_TOP_LH6_5" + ], + [ + "CMT_FIFO_L_IMUX43_2", + "CMT_TOP_IMUX43_2" + ], + [ + "CMT_FIFO_WL1END0_8", + "CMT_TOP_WL1END0_8" + ], + [ + "CMT_FIFO_SE2A2_2", + "CMT_TOP_SE2A2_2" + ], + [ + "CMT_FIFO_EL1BEG1_5", + "CMT_TOP_EL1BEG1_5" + ], + [ + "CMT_FIFO_EE4A2_11", + "CMT_TOP_EE4A2_11" + ], + [ + "CMT_FIFO_EE4BEG3_2", + "CMT_TOP_EE4BEG3_2" + ], + [ + "CMT_FIFO_WW4A2_7", + "CMT_TOP_WW4A2_7" + ], + [ + "CMT_FIFO_L_IMUX32_2", + "CMT_TOP_IMUX32_2" + ], + [ + "CMT_FIFO_LH4_8", + "CMT_TOP_LH4_8" + ], + [ + "CMT_FIFO_LH12_5", + "CMT_TOP_LH12_5" + ], + [ + "CMT_FIFO_L_IMUX18_9", + "CMT_TOP_IMUX18_9" + ], + [ + "CMT_FIFO_L_IMUX1_9", + "CMT_TOP_IMUX1_9" + ], + [ + "CMT_FIFO_WW4B0_6", + "CMT_TOP_WW4B0_6" + ], + [ + "CMT_FIFO_L_FAN5_8", + "CMT_TOP_FAN5_8" + ], + [ + "CMT_FIFO_SW4END1_2", + "CMT_TOP_SW4END1_2" + ], + [ + "CMT_FIFO_L_IMUX35_11", + "CMT_TOP_IMUX35_11" + ], + [ + "CMT_FIFO_NW4END1_10", + "CMT_TOP_NW4END1_10" + ], + [ + "CMT_FIFO_WR1END3_11", + "CMT_TOP_WR1END3_11" + ], + [ + "CMT_FIFO_L_IMUX14_2", + "CMT_TOP_IMUX14_2" + ], + [ + "CMT_FIFO_L_IMUX4_7", + "CMT_TOP_IMUX4_7" + ], + [ + "CMT_FIFO_WW4END3_0", + "CMT_TOP_WW4END3_0" + ], + [ + "CMT_FIFO_L_IMUX13_9", + "CMT_TOP_IMUX13_9" + ], + [ + "CMT_FIFO_L_IMUX17_5", + "CMT_TOP_IMUX17_5" + ], + [ + "CMT_FIFO_SE2A0_10", + "CMT_TOP_SE2A0_10" + ], + [ + "CMT_FIFO_L_IMUX26_3", + "CMT_TOP_IMUX26_3" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "CMT_TOP_ICLKDIV_3" + ], + [ + "CMT_FIFO_NE4C1_9", + "CMT_TOP_NE4C1_9" + ], + [ + "CMT_FIFO_L_BYP4_5", + "CMT_TOP_BYP4_5" + ], + [ + "CMT_FIFO_SW4A0_5", + "CMT_TOP_SW4A0_5" + ], + [ + "CMT_FIFO_L_BYP4_3", + "CMT_TOP_BYP4_3" + ], + [ + "CMT_FIFO_NW2A0_2", + "CMT_TOP_NW2A0_2" + ], + [ + "CMT_FIFO_SW2A1_10", + "CMT_TOP_SW2A1_10" + ], + [ + "CMT_FIFO_EE4C0_8", + "CMT_TOP_EE4C0_8" + ], + [ + "CMT_FIFO_L_BYP0_8", + "CMT_TOP_BYP0_8" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "CMT_TOP_ICLK_10" + ], + [ + "CMT_FIFO_WL1END2_2", + "CMT_TOP_WL1END2_2" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "CMT_TOP_OCLK_11" + ], + [ + "CMT_FIFO_L_IMUX12_1", + "CMT_TOP_IMUX12_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_9", + "CMT_TOP_LOGIC_OUTS_L_B7_9" + ], + [ + "CMT_FIFO_L_IMUX41_9", + "CMT_TOP_IMUX41_9" + ], + [ + "CMT_FIFO_L_FAN7_11", + "CMT_TOP_FAN7_11" + ], + [ + "CMT_FIFO_EE2A3_5", + "CMT_TOP_EE2A3_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_3", + "CMT_TOP_LOGIC_OUTS_L_B21_3" + ], + [ + "CMT_FIFO_WW4B2_4", + "CMT_TOP_WW4B2_4" + ], + [ + "CMT_FIFO_L_IMUX3_2", + "CMT_TOP_IMUX3_2" + ], + [ + "CMT_FIFO_WR1END0_3", + "CMT_TOP_WR1END0_3" + ], + [ + "CMT_FIFO_SE4BEG0_10", + "CMT_TOP_SE4BEG0_10" + ], + [ + "CMT_FIFO_L_IMUX8_8", + "CMT_TOP_IMUX8_8" + ], + [ + "CMT_FIFO_WW4B3_9", + "CMT_TOP_WW4B3_9" + ], + [ + "CMT_FIFO_L_IMUX11_1", + "CMT_TOP_IMUX11_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_4", + "CMT_TOP_LOGIC_OUTS_L_B5_4" + ], + [ + "CMT_FIFO_LH3_0", + "CMT_TOP_LH3_0" + ], + [ + "CMT_FIFO_WR1END2_7", + "CMT_TOP_WR1END2_7" + ], + [ + "CMT_FIFO_NE2A2_7", + "CMT_TOP_NE2A2_7" + ], + [ + "CMT_FIFO_ER1BEG3_2", + "CMT_TOP_ER1BEG3_2" + ], + [ + "CMT_FIFO_WW2A1_0", + "CMT_TOP_WW2A1_0" + ], + [ + "CMT_FIFO_WL1END0_11", + "CMT_TOP_WL1END0_11" + ], + [ + "CMT_FIFO_NE4BEG1_9", + "CMT_TOP_NE4BEG1_9" + ], + [ + "CMT_FIFO_SW4A3_10", + "CMT_TOP_SW4A3_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_7", + "CMT_TOP_LOGIC_OUTS_L_B12_7" + ], + [ + "CMT_FIFO_WW4B3_1", + "CMT_TOP_WW4B3_1" + ], + [ + "CMT_FIFO_NW4END0_5", + "CMT_TOP_NW4END0_5" + ], + [ + "CMT_FIFO_L_BYP7_5", + "CMT_TOP_BYP7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_8", + "CMT_TOP_LOGIC_OUTS_L_B16_8" + ], + [ + "CMT_FIFO_SE4C1_6", + "CMT_TOP_SE4C1_6" + ], + [ + "CMT_FIFO_WW4B2_3", + "CMT_TOP_WW4B2_3" + ], + [ + "CMT_FIFO_L_IMUX3_1", + "CMT_TOP_IMUX3_1" + ], + [ + "CMT_FIFO_L_FAN4_5", + "CMT_TOP_FAN4_5" + ], + [ + "CMT_FIFO_L_IMUX32_8", + "CMT_TOP_IMUX32_8" + ], + [ + "CMT_FIFO_L_IMUX36_7", + "CMT_TOP_IMUX36_7" + ], + [ + "CMT_FIFO_EE4A0_8", + "CMT_TOP_EE4A0_8" + ], + [ + "CMT_FIFO_EE4C0_11", + "CMT_TOP_EE4C0_11" + ], + [ + "CMT_FIFO_NW2A0_5", + "CMT_TOP_NW2A0_5" + ], + [ + "CMT_FIFO_L_CLK0_10", + "CMT_TOP_CLK0_10" + ], + [ + "CMT_FIFO_EE4B3_5", + "CMT_TOP_EE4B3_5" + ], + [ + "CMT_FIFO_EE4BEG0_6", + "CMT_TOP_EE4BEG0_6" + ], + [ + "CMT_FIFO_L_IMUX1_0", + "CMT_TOP_IMUX1_0" + ], + [ + "CMT_FIFO_L_IMUX12_11", + "CMT_TOP_IMUX12_11" + ], + [ + "CMT_FIFO_L_IMUX14_8", + "CMT_TOP_IMUX14_8" + ], + [ + "CMT_FIFO_NW4A1_3", + "CMT_TOP_NW4A1_3" + ], + [ + "CMT_FIFO_L_IMUX17_11", + "CMT_TOP_IMUX17_11" + ], + [ + "CMT_FIFO_SE4BEG1_8", + "CMT_TOP_SE4BEG1_8" + ], + [ + "CMT_FIFO_L_IMUX5_10", + "CMT_TOP_IMUX5_10" + ], + [ + "CMT_FIFO_NE2A3_2", + "CMT_TOP_NE2A3_2" + ], + [ + "CMT_FIFO_L_IMUX0_4", + "CMT_TOP_IMUX0_4" + ], + [ + "CMT_FIFO_NE4C3_2", + "CMT_TOP_NE4C3_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_8", + "CMT_TOP_LOGIC_OUTS_L_B2_8" + ], + [ + "CMT_FIFO_LH4_6", + "CMT_TOP_LH4_6" + ], + [ + "CMT_FIFO_L_IMUX27_5", + "CMT_TOP_IMUX27_5" + ], + [ + "CMT_FIFO_LH5_0", + "CMT_TOP_LH5_0" + ], + [ + "CMT_FIFO_EE4B3_10", + "CMT_TOP_EE4B3_10" + ], + [ + "CMT_FIFO_NW4A3_8", + "CMT_TOP_NW4A3_8" + ], + [ + "CMT_FIFO_L_BYP0_3", + "CMT_TOP_BYP0_3" + ], + [ + "CMT_FIFO_L_IMUX24_8", + "CMT_TOP_IMUX24_8" + ], + [ + "CMT_FIFO_L_IMUX30_3", + "CMT_TOP_IMUX30_3" + ], + [ + "CMT_FIFO_L_FAN7_9", + "CMT_TOP_FAN7_9" + ], + [ + "CMT_FIFO_EE4B2_6", + "CMT_TOP_EE4B2_6" + ], + [ + "CMT_FIFO_L_IMUX14_4", + "CMT_TOP_IMUX14_4" + ], + [ + "CMT_FIFO_LH10_6", + "CMT_TOP_LH10_6" + ], + [ + "CMT_FIFO_WW4A0_2", + "CMT_TOP_WW4A0_2" + ], + [ + "CMT_FIFO_L_BYP0_10", + "CMT_TOP_BYP0_10" + ], + [ + "CMT_FIFO_L_IMUX36_2", + "CMT_TOP_IMUX36_2" + ], + [ + "CMT_FIFO_L_IMUX13_7", + "CMT_TOP_IMUX13_7" + ], + [ + "CMT_FIFO_SE2A1_11", + "CMT_TOP_SE2A1_11" + ], + [ + "CMT_FIFO_L_CTRL0_8", + "CMT_TOP_CTRL0_8" + ], + [ + "CMT_FIFO_SE4C2_1", + "CMT_TOP_SE4C2_1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_7", + "CMT_TOP_LOGIC_OUTS_L_B17_7" + ], + [ + "CMT_FIFO_L_IMUX5_2", + "CMT_TOP_IMUX5_2" + ], + [ + "CMT_FIFO_EE4BEG0_5", + "CMT_TOP_EE4BEG0_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_0", + "CMT_TOP_LOGIC_OUTS_L_B7_0" + ], + [ + "CMT_FIFO_EE4B0_2", + "CMT_TOP_EE4B0_2" + ], + [ + "CMT_FIFO_L_BYP4_1", + "CMT_TOP_BYP4_1" + ], + [ + "CMT_FIFO_L_FAN1_7", + "CMT_TOP_FAN1_7" + ], + [ + "CMT_FIFO_L_IMUX28_6", + "CMT_TOP_IMUX28_6" + ], + [ + "CMT_FIFO_NE2A2_4", + "CMT_TOP_NE2A2_4" + ], + [ + "CMT_FIFO_WW2A1_9", + "CMT_TOP_WW2A1_9" + ], + [ + "CMT_FIFO_L_FAN1_6", + "CMT_TOP_FAN1_6" + ], + [ + "CMT_FIFO_L_IMUX13_5", + "CMT_TOP_IMUX13_5" + ], + [ + "CMT_FIFO_L_IMUX27_2", + "CMT_TOP_IMUX27_2" + ], + [ + "CMT_FIFO_L_IMUX8_4", + "CMT_TOP_IMUX8_4" + ], + [ + "CMT_FIFO_NE4C0_0", + "CMT_TOP_NE4C0_0" + ], + [ + "CMT_FIFO_NW4END1_11", + "CMT_TOP_NW4END1_11" + ], + [ + "CMT_FIFO_LH8_1", + "CMT_TOP_LH8_1" + ], + [ + "CMT_FIFO_L_IMUX30_7", + "CMT_TOP_IMUX30_7" + ], + [ + "CMT_FIFO_WW2A0_5", + "CMT_TOP_WW2A0_5" + ], + [ + "CMT_FIFO_LH6_4", + "CMT_TOP_LH6_4" + ], + [ + "CMT_FIFO_L_IMUX14_7", + "CMT_TOP_IMUX14_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_2", + "CMT_TOP_LOGIC_OUTS_L_B16_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_10", + "CMT_TOP_LOGIC_OUTS_L_B17_10" + ], + [ + "CMT_FIFO_L_IMUX11_6", + "CMT_TOP_IMUX11_6" + ], + [ + "CMT_FIFO_L_CLK1_9", + "CMT_TOP_CLK1_9" + ], + [ + "CMT_FIFO_L_IMUX13_1", + "CMT_TOP_IMUX13_1" + ], + [ + "CMT_FIFO_SE4C1_7", + "CMT_TOP_SE4C1_7" + ], + [ + "CMT_FIFO_LH9_6", + "CMT_TOP_LH9_6" + ], + [ + "CMT_FIFO_L_IMUX24_7", + "CMT_TOP_IMUX24_7" + ], + [ + "CMT_FIFO_L_IMUX41_10", + "CMT_TOP_IMUX41_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_4", + "CMT_TOP_LOGIC_OUTS_L_B11_4" + ], + [ + "CMT_FIFO_LH3_9", + "CMT_TOP_LH3_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_9", + "CMT_TOP_LOGIC_OUTS_L_B20_9" + ], + [ + "CMT_FIFO_L_IMUX20_5", + "CMT_TOP_IMUX20_5" + ], + [ + "CMT_FIFO_EE4A2_6", + "CMT_TOP_EE4A2_6" + ], + [ + "CMT_FIFO_WR1END2_5", + "CMT_TOP_WR1END2_5" + ], + [ + "CMT_FIFO_LH1_7", + "CMT_TOP_LH1_7" + ], + [ + "CMT_FIFO_L_IMUX34_5", + "CMT_TOP_IMUX34_5" + ], + [ + "CMT_FIFO_EE4A0_4", + "CMT_TOP_EE4A0_4" + ], + [ + "CMT_FIFO_L_IMUX26_8", + "CMT_TOP_IMUX26_8" + ], + [ + "CMT_FIFO_LH8_8", + "CMT_TOP_LH8_8" + ], + [ + "CMT_FIFO_LH11_3", + "CMT_TOP_LH11_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_4", + "CMT_TOP_LOGIC_OUTS_L_B14_4" + ], + [ + "CMT_FIFO_EE2BEG0_4", + "CMT_TOP_EE2BEG0_4" + ], + [ + "CMT_FIFO_L_IMUX39_6", + "CMT_TOP_IMUX39_6" + ], + [ + "CMT_FIFO_WW4C1_5", + "CMT_TOP_WW4C1_5" + ], + [ + "CMT_FIFO_WW4END1_7", + "CMT_TOP_WW4END1_7" + ], + [ + "CMT_FIFO_L_BYP2_5", + "CMT_TOP_BYP2_5" + ], + [ + "CMT_FIFO_MONITOR_P_4", + "CMT_TOP_MONITOR_P_4" + ], + [ + "CMT_FIFO_L_IMUX4_1", + "CMT_TOP_IMUX4_1" + ], + [ + "CMT_FIFO_NW4END3_0", + "CMT_TOP_NW4END3_0" + ], + [ + "CMT_FIFO_ER1BEG3_10", + "CMT_TOP_ER1BEG3_10" + ], + [ + "CMT_FIFO_L_IMUX12_5", + "CMT_TOP_IMUX12_5" + ], + [ + "CMT_FIFO_L_IMUX1_2", + "CMT_TOP_IMUX1_2" + ], + [ + "CMT_FIFO_L_IMUX7_11", + "CMT_TOP_IMUX7_11" + ], + [ + "CMT_FIFO_L_IMUX28_11", + "CMT_TOP_IMUX28_11" + ], + [ + "CMT_FIFO_L_IMUX9_2", + "CMT_TOP_IMUX9_2" + ], + [ + "CMT_FIFO_L_BYP3_11", + "CMT_TOP_BYP3_11" + ], + [ + "CMT_FIFO_NW4A3_1", + "CMT_TOP_NW4A3_1" + ], + [ + "CMT_FIFO_L_CTRL1_2", + "CMT_TOP_CTRL1_2" + ], + [ + "CMT_FIFO_LH12_0", + "CMT_TOP_LH12_0" + ], + [ + "CMT_FIFO_L_IMUX23_5", + "CMT_TOP_IMUX23_5" + ], + [ + "CMT_FIFO_LH12_3", + "CMT_TOP_LH12_3" + ], + [ + "CMT_FIFO_L_IMUX16_4", + "CMT_TOP_IMUX16_4" + ], + [ + "CMT_FIFO_WR1END1_10", + "CMT_TOP_WR1END1_10" + ], + [ + "CMT_FIFO_L_IMUX11_4", + "CMT_TOP_IMUX11_4" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_3", + "CMT_TOP_LOGIC_OUTS_L_B20_3" + ], + [ + "CMT_FIFO_L_IMUX13_8", + "CMT_TOP_IMUX13_8" + ], + [ + "CMT_FIFO_L_IMUX34_7", + "CMT_TOP_IMUX34_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_10", + "CMT_TOP_LOGIC_OUTS_L_B5_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_7", + "CMT_TOP_LOGIC_OUTS_L_B10_7" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_2", + "CMT_TOP_LOGIC_OUTS_L_B15_2" + ], + [ + "CMT_FIFO_L_IMUX10_4", + "CMT_TOP_IMUX10_4" + ], + [ + "CMT_FIFO_L_IMUX34_4", + "CMT_TOP_IMUX34_4" + ], + [ + "CMT_FIFO_NW4A2_5", + "CMT_TOP_NW4A2_5" + ], + [ + "CMT_FIFO_L_IMUX27_6", + "CMT_TOP_IMUX27_6" + ], + [ + "CMT_FIFO_L_IMUX42_8", + "CMT_TOP_IMUX42_8" + ], + [ + "CMT_FIFO_L_IMUX31_1", + "CMT_TOP_IMUX31_1" + ], + [ + "CMT_FIFO_WW4END2_0", + "CMT_TOP_WW4END2_0" + ], + [ + "CMT_FIFO_SW4A0_10", + "CMT_TOP_SW4A0_10" + ], + [ + "CMT_FIFO_LH12_11", + "CMT_TOP_LH12_11" + ], + [ + "CMT_FIFO_NW4END2_4", + "CMT_TOP_NW4END2_4" + ], + [ + "CMT_FIFO_SE2A2_0", + "CMT_TOP_SE2A2_0" + ], + [ + "CMT_FIFO_SE2A3_5", + "CMT_TOP_SE2A3_5" + ], + [ + "CMT_FIFO_L_IMUX7_5", + "CMT_TOP_IMUX7_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_7", + "CMT_TOP_LOGIC_OUTS_L_B9_7" + ], + [ + "CMT_FIFO_L_FAN3_6", + "CMT_TOP_FAN3_6" + ], + [ + "CMT_FIFO_EE4A2_2", + "CMT_TOP_EE4A2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_2", + "CMT_TOP_LOGIC_OUTS_L_B17_2" + ], + [ + "CMT_FIFO_L_IMUX22_10", + "CMT_TOP_IMUX22_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_9", + "CMT_TOP_LOGIC_OUTS_L_B22_9" + ], + [ + "CMT_FIFO_L_IMUX4_10", + "CMT_TOP_IMUX4_10" + ], + [ + "CMT_FIFO_L_BYP7_3", + "CMT_TOP_BYP7_3" + ], + [ + "CMT_FIFO_NE4BEG3_6", + "CMT_TOP_NE4BEG3_6" + ], + [ + "CMT_FIFO_L_CTRL0_10", + "CMT_TOP_CTRL0_10" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_5", + "CMT_TOP_LOGIC_OUTS_L_B13_5" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_11", + "CMT_TOP_LOGIC_OUTS_L_B19_11" + ], + [ + "CMT_FIFO_L_IMUX41_8", + "CMT_TOP_IMUX41_8" + ], + [ + "CMT_FIFO_SE2A1_0", + "CMT_TOP_SE2A1_0" + ], + [ + "CMT_FIFO_SW4END2_11", + "CMT_TOP_SW4END2_11" + ], + [ + "CMT_FIFO_WL1END0_3", + "CMT_TOP_WL1END0_3" + ], + [ + "CMT_FIFO_L_IMUX37_5", + "CMT_TOP_IMUX37_5" + ], + [ + "CMT_FIFO_LH12_8", + "CMT_TOP_LH12_8" + ], + [ + "CMT_FIFO_SW4END3_3", + "CMT_TOP_SW4END3_3" + ], + [ + "CMT_FIFO_NW4A1_5", + "CMT_TOP_NW4A1_5" + ], + [ + "CMT_FIFO_WW4END3_5", + "CMT_TOP_WW4END3_5" + ], + [ + "CMT_FIFO_L_BYP7_4", + "CMT_TOP_BYP7_4" + ], + [ + "CMT_FIFO_L_IMUX10_0", + "CMT_TOP_IMUX10_0" + ], + [ + "CMT_FIFO_EE4BEG0_2", + "CMT_TOP_EE4BEG0_2" + ], + [ + "CMT_FIFO_L_IMUX33_0", + "CMT_TOP_IMUX33_0" + ], + [ + "CMT_FIFO_EL1BEG0_7", + "CMT_TOP_EL1BEG0_7" + ], + [ + "CMT_FIFO_SE2A2_5", + "CMT_TOP_SE2A2_5" + ], + [ + "CMT_FIFO_ER1BEG2_0", + "CMT_TOP_ER1BEG2_0" + ], + [ + "CMT_FIFO_L_CLK0_11", + "CMT_TOP_CLK0_11" + ], + [ + "CMT_FIFO_L_IMUX13_4", + "CMT_TOP_IMUX13_4" + ], + [ + "CMT_FIFO_L_BYP5_9", + "CMT_TOP_BYP5_9" + ], + [ + "CMT_FIFO_LH10_2", + "CMT_TOP_LH10_2" + ], + [ + "CMT_FIFO_L_IMUX33_4", + "CMT_TOP_IMUX33_4" + ], + [ + "CMT_FIFO_SW4END0_8", + "CMT_TOP_SW4END0_8" + ], + [ + "CMT_FIFO_L_IMUX11_11", + "CMT_TOP_IMUX11_11" + ], + [ + "CMT_FIFO_SW4END0_1", + "CMT_TOP_SW4END0_1" + ], + [ + "CMT_FIFO_L_IMUX14_0", + "CMT_TOP_IMUX14_0" + ], + [ + "CMT_FIFO_NW4END3_11", + "CMT_TOP_NW4END3_11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_6", + "CMT_TOP_LOGIC_OUTS_L_B21_6" + ], + [ + "CMT_FIFO_L_FAN7_8", + "CMT_TOP_FAN7_8" + ], + [ + "CMT_FIFO_EE4BEG1_7", + "CMT_TOP_EE4BEG1_7" + ], + [ + "CMT_FIFO_L_BYP3_7", + "CMT_TOP_BYP3_7" + ], + [ + "CMT_FIFO_L_IMUX26_0", + "CMT_TOP_IMUX26_0" + ], + [ + "CMT_FIFO_LH8_5", + "CMT_TOP_LH8_5" + ], + [ + "CMT_FIFO_WL1END0_7", + "CMT_TOP_WL1END0_7" + ], + [ + "CMT_FIFO_L_IMUX11_9", + "CMT_TOP_IMUX11_9" + ], + [ + "CMT_FIFO_WR1END0_4", + "CMT_TOP_WR1END0_4" + ], + [ + "CMT_FIFO_L_IMUX36_10", + "CMT_TOP_IMUX36_10" + ], + [ + "CMT_FIFO_EL1BEG1_1", + "CMT_TOP_EL1BEG1_1" + ], + [ + "CMT_FIFO_SE4C1_10", + "CMT_TOP_SE4C1_10" + ], + [ + "CMT_FIFO_NW4END0_10", + "CMT_TOP_NW4END0_10" + ], + [ + "CMT_FIFO_WW2END0_9", + "CMT_TOP_WW2END0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_6", + "CMT_TOP_LOGIC_OUTS_L_B1_6" + ], + [ + "CMT_FIFO_ER1BEG2_2", + "CMT_TOP_ER1BEG2_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_9", + "CMT_TOP_LOGIC_OUTS_L_B19_9" + ], + [ + "CMT_FIFO_NE4C0_9", + "CMT_TOP_NE4C0_9" + ], + [ + "CMT_FIFO_SE2A0_4", + "CMT_TOP_SE2A0_4" + ], + [ + "CMT_FIFO_WW2A3_9", + "CMT_TOP_WW2A3_9" + ], + [ + "CMT_FIFO_L_IMUX21_9", + "CMT_TOP_IMUX21_9" + ], + [ + "CMT_FIFO_NE2A3_5", + "CMT_TOP_NE2A3_5" + ], + [ + "CMT_FIFO_NW2A0_7", + "CMT_TOP_NW2A0_7" + ], + [ + "CMT_FIFO_L_IMUX40_10", + "CMT_TOP_IMUX40_10" + ], + [ + "CMT_FIFO_L_IMUX6_9", + "CMT_TOP_IMUX6_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_4", + "CMT_TOP_LOGIC_OUTS_L_B8_4" + ], + [ + "CMT_FIFO_ER1BEG1_5", + "CMT_TOP_ER1BEG1_5" + ], + [ + "CMT_FIFO_WW4A2_1", + "CMT_TOP_WW4A2_1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "CMT_TOP_OCLKDIV_6" + ], + [ + "CMT_FIFO_LH3_5", + "CMT_TOP_LH3_5" + ], + [ + "CMT_FIFO_SW4END0_9", + "CMT_TOP_SW4END0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_4", + "CMT_TOP_LOGIC_OUTS_L_B16_4" + ], + [ + "CMT_FIFO_SE4BEG0_9", + "CMT_TOP_SE4BEG0_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_3", + "CMT_TOP_LOGIC_OUTS_L_B9_3" + ], + [ + "CMT_FIFO_ER1BEG1_1", + "CMT_TOP_ER1BEG1_1" + ], + [ + "CMT_FIFO_EE2A2_0", + "CMT_TOP_EE2A2_0" + ], + [ + "CMT_FIFO_L_IMUX40_2", + "CMT_TOP_IMUX40_2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_2", + "CMT_TOP_LOGIC_OUTS_L_B13_2" + ], + [ + "CMT_FIFO_L_IMUX22_9", + "CMT_TOP_IMUX22_9" + ], + [ + "CMT_FIFO_LH9_11", + "CMT_TOP_LH9_11" + ], + [ + "CMT_FIFO_WL1END3_3", + "CMT_TOP_WL1END3_3" + ], + [ + "CMT_FIFO_EE2A1_9", + "CMT_TOP_EE2A1_9" + ], + [ + "CMT_FIFO_LH4_9", + "CMT_TOP_LH4_9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_3", + "CMT_TOP_LOGIC_OUTS_L_B12_3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_9", + "CMT_TOP_LOGIC_OUTS_L_B21_9" + ], + [ + "CMT_FIFO_NW4END0_3", + "CMT_TOP_NW4END0_3" + ], + [ + "CMT_FIFO_SW4A3_1", + "CMT_TOP_SW4A3_1" + ], + [ + "CMT_FIFO_SW4END2_10", + "CMT_TOP_SW4END2_10" + ], + [ + "CMT_FIFO_SW4END0_7", + "CMT_TOP_SW4END0_7" + ], + [ + "CMT_FIFO_L_IMUX11_5", + "CMT_TOP_IMUX11_5" + ], + [ + "CMT_FIFO_ER1BEG3_7", + "CMT_TOP_ER1BEG3_7" + ], + [ + "CMT_FIFO_EE2BEG2_9", + "CMT_TOP_EE2BEG2_9" + ], + [ + "CMT_FIFO_EE4C0_10", + "CMT_TOP_EE4C0_10" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "CMT_TOP_L_UPPER_B" + ] + }, + { + "grid_deltas": [ + 1, + 4 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH12_0", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH9_0", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_LH1_0", + "VBRK_LH1" + ], + [ + "CMT_TOP_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_LH8_0", + "VBRK_LH8" + ], + [ + "CMT_TOP_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH5_0", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH4_0", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH3_0", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_LH10_0", + "VBRK_LH10" + ], + [ + "CMT_TOP_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH11_0", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_MONITOR_N_0", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH7_0", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE2BEG3_0", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH2_0", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH6_0", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_MONITOR_P_0", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG0_0", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE2BEG0_0", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE4B0_0", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SW4A1_0", + "VBRK_SW4A1" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLBLM_M_CIN", + "CLBLM_M_COUT_N" + ], + [ + "CLBLM_L_CIN", + "CLBLM_L_COUT_N" + ] + ], + "tile_types": [ + "CLBLM_L", + "CLBLM_L" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "DSP_NW2A0_2", + "INT_INTERFACE_NW2A0" + ], + [ + "DSP_LOGIC_OUTS_B17_2", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "DSP_LH12_2", + "INT_INTERFACE_LH12" + ], + [ + "DSP_IMUX29_2", + "INT_INTERFACE_IMUX29" + ], + [ + "DSP_IMUX15_2", + "INT_INTERFACE_IMUX15" + ], + [ + "DSP_WW4B2_2", + "INT_INTERFACE_WW4B2" + ], + [ + "DSP_LOGIC_OUTS_B19_2", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "DSP_WW2END0_2", + "INT_INTERFACE_WW2END0" + ], + [ + "DSP_SE4BEG1_2", + "INT_INTERFACE_SE4BEG1" + ], + [ + "DSP_SW2A3_2", + "INT_INTERFACE_SW2A3" + ], + [ + "DSP_BYP4_2", + "INT_INTERFACE_BYP4" + ], + [ + "DSP_WW4A1_2", + "INT_INTERFACE_WW4A1" + ], + [ + "DSP_IMUX41_2", + "INT_INTERFACE_IMUX41" + ], + [ + "DSP_NW4END3_2", + "INT_INTERFACE_NW4END3" + ], + [ + "DSP_EL1BEG1_2", + "INT_INTERFACE_EL1BEG1" + ], + [ + "DSP_NE4C3_2", + "INT_INTERFACE_NE4C3" + ], + [ + "DSP_IMUX4_2", + "INT_INTERFACE_IMUX4" + ], + [ + "DSP_IMUX25_2", + "INT_INTERFACE_IMUX25" + ], + [ + "DSP_WW2A3_2", + "INT_INTERFACE_WW2A3" + ], + [ + "DSP_EE4C3_2", + "INT_INTERFACE_EE4C3" + ], + [ + "DSP_LH6_2", + "INT_INTERFACE_LH6" + ], + [ + "DSP_IMUX35_2", + "INT_INTERFACE_IMUX35" + ], + [ + "DSP_CLK1_2", + "INT_INTERFACE_CLK1" + ], + [ + "DSP_WW4B0_2", + "INT_INTERFACE_WW4B0" + ], + [ + "DSP_IMUX1_2", + "INT_INTERFACE_IMUX1" + ], + [ + "DSP_IMUX42_2", + "INT_INTERFACE_IMUX42" + ], + [ + "DSP_SE4BEG3_2", + "INT_INTERFACE_SE4BEG3" + ], + [ + "DSP_LOGIC_OUTS_B13_2", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "DSP_LH11_2", + "INT_INTERFACE_LH11" + ], + [ + "DSP_IMUX47_2", + "INT_INTERFACE_IMUX47" + ], + [ + "DSP_IMUX46_2", + "INT_INTERFACE_IMUX46" + ], + [ + "DSP_IMUX3_2", + "INT_INTERFACE_IMUX3" + ], + [ + "DSP_LOGIC_OUTS_B9_2", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "DSP_BYP6_2", + "INT_INTERFACE_BYP6" + ], + [ + "DSP_WW2END3_2", + "INT_INTERFACE_WW2END3" + ], + [ + "DSP_SE4BEG2_2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "DSP_NE4C1_2", + "INT_INTERFACE_NE4C1" + ], + [ + "DSP_IMUX34_2", + "INT_INTERFACE_IMUX34" + ], + [ + "DSP_LOGIC_OUTS_B14_2", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "DSP_IMUX23_2", + "INT_INTERFACE_IMUX23" + ], + [ + "DSP_NW4A2_2", + "INT_INTERFACE_NW4A2" + ], + [ + "DSP_IMUX6_2", + "INT_INTERFACE_IMUX6" + ], + [ + "DSP_LOGIC_OUTS_B15_2", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "DSP_WW4C3_2", + "INT_INTERFACE_WW4C3" + ], + [ + "DSP_LOGIC_OUTS_B20_2", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "DSP_SE2A2_2", + "INT_INTERFACE_SE2A2" + ], + [ + "DSP_IMUX10_2", + "INT_INTERFACE_IMUX10" + ], + [ + "DSP_SW4END0_2", + "INT_INTERFACE_SW4END0" + ], + [ + "DSP_EE2BEG1_2", + "INT_INTERFACE_EE2BEG1" + ], + [ + "DSP_WR1END1_2", + "INT_INTERFACE_WR1END1" + ], + [ + "DSP_IMUX5_2", + "INT_INTERFACE_IMUX5" + ], + [ + "DSP_NW4A0_2", + "INT_INTERFACE_NW4A0" + ], + [ + "DSP_LOGIC_OUTS_B8_2", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "DSP_LOGIC_OUTS_B3_2", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "DSP_NE4C0_2", + "INT_INTERFACE_NE4C0" + ], + [ + "DSP_NW2A1_2", + "INT_INTERFACE_NW2A1" + ], + [ + "DSP_NW4END2_2", + "INT_INTERFACE_NW4END2" + ], + [ + "DSP_NE4C2_2", + "INT_INTERFACE_NE4C2" + ], + [ + "DSP_IMUX24_2", + "INT_INTERFACE_IMUX24" + ], + [ + "DSP_SW4A2_2", + "INT_INTERFACE_SW4A2" + ], + [ + "DSP_EL1BEG2_2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "DSP_LH2_2", + "INT_INTERFACE_LH2" + ], + [ + "DSP_WW4A3_2", + "INT_INTERFACE_WW4A3" + ], + [ + "DSP_LOGIC_OUTS_B2_2", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "DSP_CTRL0_2", + "INT_INTERFACE_CTRL0" + ], + [ + "DSP_EE4A3_2", + "INT_INTERFACE_EE4A3" + ], + [ + "DSP_LH8_2", + "INT_INTERFACE_LH8" + ], + [ + "DSP_IMUX38_2", + "INT_INTERFACE_IMUX38" + ], + [ + "DSP_EL1BEG3_2", + "INT_INTERFACE_EL1BEG3" + ], + [ + "DSP_IMUX28_2", + "INT_INTERFACE_IMUX28" + ], + [ + "DSP_SW4A3_2", + "INT_INTERFACE_SW4A3" + ], + [ + "DSP_LOGIC_OUTS_B21_2", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "DSP_NE2A2_2", + "INT_INTERFACE_NE2A2" + ], + [ + "DSP_WR1END0_2", + "INT_INTERFACE_WR1END0" + ], + [ + "DSP_BYP2_2", + "INT_INTERFACE_BYP2" + ], + [ + "DSP_FAN5_2", + "INT_INTERFACE_FAN5" + ], + [ + "DSP_BYP7_2", + "INT_INTERFACE_BYP7" + ], + [ + "DSP_LOGIC_OUTS_B1_2", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "DSP_IMUX11_2", + "INT_INTERFACE_IMUX11" + ], + [ + "DSP_FAN3_2", + "INT_INTERFACE_FAN3" + ], + [ + "DSP_WW4C0_2", + "INT_INTERFACE_WW4C0" + ], + [ + "DSP_NE4BEG2_2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "DSP_LOGIC_OUTS_B5_2", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "DSP_SE2A3_2", + "INT_INTERFACE_SE2A3" + ], + [ + "DSP_EE4B2_2", + "INT_INTERFACE_EE4B2" + ], + [ + "DSP_IMUX45_2", + "INT_INTERFACE_IMUX45" + ], + [ + "DSP_IMUX31_2", + "INT_INTERFACE_IMUX31" + ], + [ + "DSP_EE4A0_2", + "INT_INTERFACE_EE4A0" + ], + [ + "DSP_EE2A1_2", + "INT_INTERFACE_EE2A1" + ], + [ + "DSP_EE2BEG2_2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "DSP_WR1END2_2", + "INT_INTERFACE_WR1END2" + ], + [ + "DSP_WW2A0_2", + "INT_INTERFACE_WW2A0" + ], + [ + "DSP_IMUX12_2", + "INT_INTERFACE_IMUX12" + ], + [ + "DSP_WL1END1_2", + "INT_INTERFACE_WL1END1" + ], + [ + "DSP_IMUX8_2", + "INT_INTERFACE_IMUX8" + ], + [ + "DSP_IMUX14_2", + "INT_INTERFACE_IMUX14" + ], + [ + "DSP_BYP5_2", + "INT_INTERFACE_BYP5" + ], + [ + "DSP_SE4C1_2", + "INT_INTERFACE_SE4C1" + ], + [ + "DSP_IMUX9_2", + "INT_INTERFACE_IMUX9" + ], + [ + "DSP_FAN1_2", + "INT_INTERFACE_FAN1" + ], + [ + "DSP_LOGIC_OUTS_B4_2", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "DSP_EE2BEG3_2", + "INT_INTERFACE_EE2BEG3" + ], + [ + "DSP_NW2A3_2", + "INT_INTERFACE_NW2A3" + ], + [ + "DSP_FAN6_2", + "INT_INTERFACE_FAN6" + ], + [ + "DSP_CTRL1_2", + "INT_INTERFACE_CTRL1" + ], + [ + "DSP_NW2A2_2", + "INT_INTERFACE_NW2A2" + ], + [ + "DSP_LH5_2", + "INT_INTERFACE_LH5" + ], + [ + "DSP_IMUX32_2", + "INT_INTERFACE_IMUX32" + ], + [ + "DSP_IMUX40_2", + "INT_INTERFACE_IMUX40" + ], + [ + "DSP_MONITOR_P_2", + "INT_INTERFACE_MONITOR_P" + ], + [ + "DSP_LOGIC_OUTS_B0_2", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "DSP_ER1BEG2_2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "DSP_FAN0_2", + "INT_INTERFACE_FAN0" + ], + [ + "DSP_LOGIC_OUTS_B16_2", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "DSP_SE4C0_2", + "INT_INTERFACE_SE4C0" + ], + [ + "DSP_IMUX2_2", + "INT_INTERFACE_IMUX2" + ], + [ + "DSP_WW4END2_2", + "INT_INTERFACE_WW4END2" + ], + [ + "DSP_IMUX17_2", + "INT_INTERFACE_IMUX17" + ], + [ + "DSP_EE2A2_2", + "INT_INTERFACE_EE2A2" + ], + [ + "DSP_SE4C3_2", + "INT_INTERFACE_SE4C3" + ], + [ + "DSP_SW2A0_2", + "INT_INTERFACE_SW2A0" + ], + [ + "DSP_NE4BEG1_2", + "INT_INTERFACE_NE4BEG1" + ], + [ + "DSP_EE4BEG1_2", + "INT_INTERFACE_EE4BEG1" + ], + [ + "DSP_WW2END1_2", + "INT_INTERFACE_WW2END1" + ], + [ + "DSP_IMUX16_2", + "INT_INTERFACE_IMUX16" + ], + [ + "DSP_SE4BEG0_2", + "INT_INTERFACE_SE4BEG0" + ], + [ + "DSP_LH4_2", + "INT_INTERFACE_LH4" + ], + [ + "DSP_IMUX43_2", + "INT_INTERFACE_IMUX43" + ], + [ + "DSP_IMUX30_2", + "INT_INTERFACE_IMUX30" + ], + [ + "DSP_WW4END0_2", + "INT_INTERFACE_WW4END0" + ], + [ + "DSP_NE2A1_2", + "INT_INTERFACE_NE2A1" + ], + [ + "DSP_LH3_2", + "INT_INTERFACE_LH3" + ], + [ + "DSP_SW4END3_2", + "INT_INTERFACE_SW4END3" + ], + [ + "DSP_WR1END3_2", + "INT_INTERFACE_WR1END3" + ], + [ + "DSP_IMUX18_2", + "INT_INTERFACE_IMUX18" + ], + [ + "DSP_LOGIC_OUTS_B6_2", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "DSP_FAN7_2", + "INT_INTERFACE_FAN7" + ], + [ + "DSP_WW4B3_2", + "INT_INTERFACE_WW4B3" + ], + [ + "DSP_LOGIC_OUTS_B23_2", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "DSP_FAN4_2", + "INT_INTERFACE_FAN4" + ], + [ + "DSP_SW4END1_2", + "INT_INTERFACE_SW4END1" + ], + [ + "DSP_IMUX36_2", + "INT_INTERFACE_IMUX36" + ], + [ + "DSP_EE4B0_2", + "INT_INTERFACE_EE4B0" + ], + [ + "DSP_EE4BEG2_2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "DSP_IMUX44_2", + "INT_INTERFACE_IMUX44" + ], + [ + "DSP_WW4END3_2", + "INT_INTERFACE_WW4END3" + ], + [ + "DSP_SE2A1_2", + "INT_INTERFACE_SE2A1" + ], + [ + "DSP_SW4END2_2", + "INT_INTERFACE_SW4END2" + ], + [ + "DSP_LH7_2", + "INT_INTERFACE_LH7" + ], + [ + "DSP_BYP1_2", + "INT_INTERFACE_BYP1" + ], + [ + "DSP_IMUX37_2", + "INT_INTERFACE_IMUX37" + ], + [ + "DSP_LOGIC_OUTS_B11_2", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "DSP_SE2A0_2", + "INT_INTERFACE_SE2A0" + ], + [ + "DSP_WL1END3_2", + "INT_INTERFACE_WL1END3" + ], + [ + "DSP_EE2A0_2", + "INT_INTERFACE_EE2A0" + ], + [ + "DSP_EE4A2_2", + "INT_INTERFACE_EE4A2" + ], + [ + "DSP_LOGIC_OUTS_B22_2", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "DSP_SE4C2_2", + "INT_INTERFACE_SE4C2" + ], + [ + "DSP_NW4A1_2", + "INT_INTERFACE_NW4A1" + ], + [ + "DSP_NE2A0_2", + "INT_INTERFACE_NE2A0" + ], + [ + "DSP_EE2A3_2", + "INT_INTERFACE_EE2A3" + ], + [ + "DSP_LOGIC_OUTS_B10_2", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "DSP_NW4END0_2", + "INT_INTERFACE_NW4END0" + ], + [ + "DSP_IMUX20_2", + "INT_INTERFACE_IMUX20" + ], + [ + "DSP_FAN2_2", + "INT_INTERFACE_FAN2" + ], + [ + "DSP_IMUX22_2", + "INT_INTERFACE_IMUX22" + ], + [ + "DSP_CLK0_2", + "INT_INTERFACE_CLK0" + ], + [ + "DSP_IMUX39_2", + "INT_INTERFACE_IMUX39" + ], + [ + "DSP_IMUX33_2", + "INT_INTERFACE_IMUX33" + ], + [ + "DSP_SW4A1_2", + "INT_INTERFACE_SW4A1" + ], + [ + "DSP_IMUX19_2", + "INT_INTERFACE_IMUX19" + ], + [ + "DSP_WW4C2_2", + "INT_INTERFACE_WW4C2" + ], + [ + "DSP_NE2A3_2", + "INT_INTERFACE_NE2A3" + ], + [ + "DSP_WW4A0_2", + "INT_INTERFACE_WW4A0" + ], + [ + "DSP_EE4C0_2", + "INT_INTERFACE_EE4C0" + ], + [ + "DSP_NW4A3_2", + "INT_INTERFACE_NW4A3" + ], + [ + "DSP_WL1END0_2", + "INT_INTERFACE_WL1END0" + ], + [ + "DSP_LH9_2", + "INT_INTERFACE_LH9" + ], + [ + "DSP_NW4END1_2", + "INT_INTERFACE_NW4END1" + ], + [ + "DSP_WL1END2_2", + "INT_INTERFACE_WL1END2" + ], + [ + "DSP_LH1_2", + "INT_INTERFACE_LH1" + ], + [ + "DSP_WW4B1_2", + "INT_INTERFACE_WW4B1" + ], + [ + "DSP_IMUX21_2", + "INT_INTERFACE_IMUX21" + ], + [ + "DSP_WW2END2_2", + "INT_INTERFACE_WW2END2" + ], + [ + "DSP_EE4B1_2", + "INT_INTERFACE_EE4B1" + ], + [ + "DSP_EL1BEG0_2", + "INT_INTERFACE_EL1BEG0" + ], + [ + "DSP_MONITOR_N_2", + "INT_INTERFACE_MONITOR_N" + ], + [ + "DSP_BYP0_2", + "INT_INTERFACE_BYP0" + ], + [ + "DSP_EE2BEG0_2", + "INT_INTERFACE_EE2BEG0" + ], + [ + "DSP_ER1BEG3_2", + "INT_INTERFACE_ER1BEG3" + ], + [ + "DSP_EE4C1_2", + "INT_INTERFACE_EE4C1" + ], + [ + "DSP_WW4A2_2", + "INT_INTERFACE_WW4A2" + ], + [ + "DSP_EE4C2_2", + "INT_INTERFACE_EE4C2" + ], + [ + "DSP_WW4C1_2", + "INT_INTERFACE_WW4C1" + ], + [ + "DSP_BYP3_2", + "INT_INTERFACE_BYP3" + ], + [ + "DSP_IMUX27_2", + "INT_INTERFACE_IMUX27" + ], + [ + "DSP_LOGIC_OUTS_B7_2", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "DSP_EE4BEG3_2", + "INT_INTERFACE_EE4BEG3" + ], + [ + "DSP_LOGIC_OUTS_B18_2", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "DSP_EE4BEG0_2", + "INT_INTERFACE_EE4BEG0" + ], + [ + "DSP_WW2A1_2", + "INT_INTERFACE_WW2A1" + ], + [ + "DSP_EE4B3_2", + "INT_INTERFACE_EE4B3" + ], + [ + "DSP_IMUX7_2", + "INT_INTERFACE_IMUX7" + ], + [ + "DSP_NE4BEG3_2", + "INT_INTERFACE_NE4BEG3" + ], + [ + "DSP_EE4A1_2", + "INT_INTERFACE_EE4A1" + ], + [ + "DSP_NE4BEG0_2", + "INT_INTERFACE_NE4BEG0" + ], + [ + "DSP_ER1BEG0_2", + "INT_INTERFACE_ER1BEG0" + ], + [ + "DSP_ER1BEG1_2", + "INT_INTERFACE_ER1BEG1" + ], + [ + "DSP_SW2A2_2", + "INT_INTERFACE_SW2A2" + ], + [ + "DSP_LH10_2", + "INT_INTERFACE_LH10" + ], + [ + "DSP_IMUX26_2", + "INT_INTERFACE_IMUX26" + ], + [ + "DSP_WW2A2_2", + "INT_INTERFACE_WW2A2" + ], + [ + "DSP_WW4END1_2", + "INT_INTERFACE_WW4END1" + ], + [ + "DSP_IMUX13_2", + "INT_INTERFACE_IMUX13" + ], + [ + "DSP_IMUX0_2", + "INT_INTERFACE_IMUX0" + ], + [ + "DSP_SW4A0_2", + "INT_INTERFACE_SW4A0" + ], + [ + "DSP_SW2A1_2", + "INT_INTERFACE_SW2A1" + ] + ], + "tile_types": [ + "DSP_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + -2 + ], + "wire_pairs": [ + [ + "MONITOR_IMUX46_2", + "VFRAME_IMUX46" + ], + [ + "MONITOR_IMUX44_2", + "VFRAME_IMUX44" + ], + [ + "MONITOR_IMUX7_2", + "VFRAME_IMUX7" + ], + [ + "MONITOR_IMUX23_2", + "VFRAME_IMUX23" + ], + [ + "MONITOR_NE4BEG1_2", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_SW4END3_2", + "VFRAME_SW4END3" + ], + [ + "MONITOR_BYP4_2", + "VFRAME_BYP4" + ], + [ + "MONITOR_IMUX34_2", + "VFRAME_IMUX34" + ], + [ + "MONITOR_SE4C0_2", + "VFRAME_SE4C0" + ], + [ + "MONITOR_IMUX13_2", + "VFRAME_IMUX13" + ], + [ + "MONITOR_IMUX6_2", + "VFRAME_IMUX6" + ], + [ + "MONITOR_EE4BEG2_2", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_IMUX19_2", + "VFRAME_IMUX19" + ], + [ + "MONITOR_NW4A2_2", + "VFRAME_NW4A2" + ], + [ + "MONITOR_IMUX9_2", + "VFRAME_IMUX9" + ], + [ + "MONITOR_NE4C2_2", + "VFRAME_NE4C2" + ], + [ + "MONITOR_EE4C1_2", + "VFRAME_EE4C1" + ], + [ + "MONITOR_SE2A2_2", + "VFRAME_SE2A2" + ], + [ + "MONITOR_LH3_2", + "VFRAME_LH3" + ], + [ + "MONITOR_IMUX42_2", + "VFRAME_IMUX42" + ], + [ + "MONITOR_IMUX17_2", + "VFRAME_IMUX17" + ], + [ + "MONITOR_SE2A0_2", + "VFRAME_SE2A0" + ], + [ + "MONITOR_BYP2_2", + "VFRAME_BYP2" + ], + [ + "MONITOR_LH2_2", + "VFRAME_LH2" + ], + [ + "MONITOR_NE2A2_2", + "VFRAME_NE2A2" + ], + [ + "MONITOR_WW4B1_2", + "VFRAME_WW4B1" + ], + [ + "MONITOR_EE4BEG0_2", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_FAN2_2", + "VFRAME_FAN2" + ], + [ + "MONITOR_EE4B0_2", + "VFRAME_EE4B0" + ], + [ + "MONITOR_WW2END0_2", + "VFRAME_WW2END0" + ], + [ + "MONITOR_SE4BEG0_2", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_FAN3_2", + "VFRAME_FAN3" + ], + [ + "MONITOR_BYP5_2", + "VFRAME_BYP5" + ], + [ + "MONITOR_BYP0_2", + "VFRAME_BYP0" + ], + [ + "MONITOR_WW4C1_2", + "VFRAME_WW4C1" + ], + [ + "MONITOR_SE4C3_2", + "VFRAME_SE4C3" + ], + [ + "MONITOR_EE4B1_2", + "VFRAME_EE4B1" + ], + [ + "MONITOR_IMUX33_2", + "VFRAME_IMUX33" + ], + [ + "MONITOR_IMUX14_2", + "VFRAME_IMUX14" + ], + [ + "MONITOR_NE4BEG2_2", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_IMUX16_2", + "VFRAME_IMUX16" + ], + [ + "MONITOR_WW4A1_2", + "VFRAME_WW4A1" + ], + [ + "MONITOR_WR1END1_2", + "VFRAME_WR1END1" + ], + [ + "MONITOR_WW4C0_2", + "VFRAME_WW4C0" + ], + [ + "MONITOR_LH11_2", + "VFRAME_LH11" + ], + [ + "MONITOR_NW2A1_2", + "VFRAME_NW2A1" + ], + [ + "MONITOR_SW2A0_2", + "VFRAME_SW2A0" + ], + [ + "MONITOR_WW4C2_2", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE4C3_2", + "VFRAME_EE4C3" + ], + [ + "MONITOR_WW4A3_2", + "VFRAME_WW4A3" + ], + [ + "MONITOR_EE4B3_2", + "VFRAME_EE4B3" + ], + [ + "MONITOR_EE2BEG0_2", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_EE4BEG1_2", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX8_2", + "VFRAME_IMUX8" + ], + [ + "MONITOR_LH10_2", + "VFRAME_LH10" + ], + [ + "MONITOR_WW4END3_2", + "VFRAME_WW4END3" + ], + [ + "MONITOR_LH4_2", + "VFRAME_LH4" + ], + [ + "MONITOR_LH6_2", + "VFRAME_LH6" + ], + [ + "MONITOR_IMUX47_2", + "VFRAME_IMUX47" + ], + [ + "MONITOR_BYP1_2", + "VFRAME_BYP1" + ], + [ + "MONITOR_SW4A2_2", + "VFRAME_SW4A2" + ], + [ + "MONITOR_NW4END1_2", + "VFRAME_NW4END1" + ], + [ + "MONITOR_SE2A3_2", + "VFRAME_SE2A3" + ], + [ + "MONITOR_IMUX21_2", + "VFRAME_IMUX21" + ], + [ + "MONITOR_SE4C1_2", + "VFRAME_SE4C1" + ], + [ + "MONITOR_BYP6_2", + "VFRAME_BYP6" + ], + [ + "MONITOR_WW4B3_2", + "VFRAME_WW4B3" + ], + [ + "MONITOR_EE2A2_2", + "VFRAME_EE2A2" + ], + [ + "MONITOR_ER1BEG0_2", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_IMUX45_2", + "VFRAME_IMUX45" + ], + [ + "MONITOR_WR1END2_2", + "VFRAME_WR1END2" + ], + [ + "MONITOR_EE2A3_2", + "VFRAME_EE2A3" + ], + [ + "MONITOR_SW4END2_2", + "VFRAME_SW4END2" + ], + [ + "MONITOR_WL1END2_2", + "VFRAME_WL1END2" + ], + [ + "MONITOR_WR1END3_2", + "VFRAME_WR1END3" + ], + [ + "MONITOR_IMUX24_2", + "VFRAME_IMUX24" + ], + [ + "MONITOR_IMUX37_2", + "VFRAME_IMUX37" + ], + [ + "MONITOR_WW2A0_2", + "VFRAME_WW2A0" + ], + [ + "MONITOR_WR1END0_2", + "VFRAME_WR1END0" + ], + [ + "MONITOR_CLK1_2", + "VFRAME_CLK1" + ], + [ + "MONITOR_NW4A0_2", + "VFRAME_NW4A0" + ], + [ + "MONITOR_SW2A3_2", + "VFRAME_SW2A3" + ], + [ + "MONITOR_SE4BEG3_2", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_IMUX31_2", + "VFRAME_IMUX31" + ], + [ + "MONITOR_WW2END1_2", + "VFRAME_WW2END1" + ], + [ + "MONITOR_BYP3_2", + "VFRAME_BYP3" + ], + [ + "MONITOR_NE2A0_2", + "VFRAME_NE2A0" + ], + [ + "MONITOR_IMUX38_2", + "VFRAME_IMUX38" + ], + [ + "MONITOR_IMUX29_2", + "VFRAME_IMUX29" + ], + [ + "MONITOR_SE4C2_2", + "VFRAME_SE4C2" + ], + [ + "MONITOR_WW4A2_2", + "VFRAME_WW4A2" + ], + [ + "MONITOR_NW4END2_2", + "VFRAME_NW4END2" + ], + [ + "MONITOR_EE2BEG3_2", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_BYP7_2", + "VFRAME_BYP7" + ], + [ + "MONITOR_EE2A1_2", + "VFRAME_EE2A1" + ], + [ + "MONITOR_FAN4_2", + "VFRAME_FAN4" + ], + [ + "MONITOR_EE2BEG2_2", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_ER1BEG3_2", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_SE4BEG2_2", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_WW2A2_2", + "VFRAME_WW2A2" + ], + [ + "MONITOR_LH1_2", + "VFRAME_LH1" + ], + [ + "MONITOR_IMUX12_2", + "VFRAME_IMUX12" + ], + [ + "MONITOR_IMUX2_2", + "VFRAME_IMUX2" + ], + [ + "MONITOR_IMUX30_2", + "VFRAME_IMUX30" + ], + [ + "MONITOR_CTRL0_2", + "VFRAME_CTRL0" + ], + [ + "MONITOR_EE4BEG3_2", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_FAN5_2", + "VFRAME_FAN5" + ], + [ + "MONITOR_IMUX1_2", + "VFRAME_IMUX1" + ], + [ + "MONITOR_EL1BEG0_2", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_SW4A1_2", + "VFRAME_SW4A1" + ], + [ + "MONITOR_LH9_2", + "VFRAME_LH9" + ], + [ + "MONITOR_SW2A1_2", + "VFRAME_SW2A1" + ], + [ + "MONITOR_EE4B2_2", + "VFRAME_EE4B2" + ], + [ + "MONITOR_IMUX3_2", + "VFRAME_IMUX3" + ], + [ + "MONITOR_IMUX27_2", + "VFRAME_IMUX27" + ], + [ + "MONITOR_SE2A1_2", + "VFRAME_SE2A1" + ], + [ + "MONITOR_IMUX36_2", + "VFRAME_IMUX36" + ], + [ + "MONITOR_WW2A1_2", + "VFRAME_WW2A1" + ], + [ + "MONITOR_EL1BEG2_2", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_IMUX35_2", + "VFRAME_IMUX35" + ], + [ + "MONITOR_IMUX26_2", + "VFRAME_IMUX26" + ], + [ + "MONITOR_SW2A2_2", + "VFRAME_SW2A2" + ], + [ + "MONITOR_LH8_2", + "VFRAME_LH8" + ], + [ + "MONITOR_IMUX40_2", + "VFRAME_IMUX40" + ], + [ + "MONITOR_NE2A3_2", + "VFRAME_NE2A3" + ], + [ + "MONITOR_WL1END0_2", + "VFRAME_WL1END0" + ], + [ + "MONITOR_NW2A3_2", + "VFRAME_NW2A3" + ], + [ + "MONITOR_WL1END1_2", + "VFRAME_WL1END1" + ], + [ + "MONITOR_NE4C3_2", + "VFRAME_NE4C3" + ], + [ + "MONITOR_LH12_2", + "VFRAME_LH12" + ], + [ + "MONITOR_NW2A2_2", + "VFRAME_NW2A2" + ], + [ + "MONITOR_EE4A2_2", + "VFRAME_EE4A2" + ], + [ + "MONITOR_WL1END3_2", + "VFRAME_WL1END3" + ], + [ + "MONITOR_WW2END3_2", + "VFRAME_WW2END3" + ], + [ + "MONITOR_IMUX20_2", + "VFRAME_IMUX20" + ], + [ + "MONITOR_LH7_2", + "VFRAME_LH7" + ], + [ + "MONITOR_IMUX15_2", + "VFRAME_IMUX15" + ], + [ + "MONITOR_EL1BEG1_2", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_IMUX39_2", + "VFRAME_IMUX39" + ], + [ + "MONITOR_NW2A0_2", + "VFRAME_NW2A0" + ], + [ + "MONITOR_IMUX11_2", + "VFRAME_IMUX11" + ], + [ + "MONITOR_NE2A1_2", + "VFRAME_NE2A1" + ], + [ + "MONITOR_ER1BEG1_2", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_WW4END2_2", + "VFRAME_WW4END2" + ], + [ + "MONITOR_WW4END1_2", + "VFRAME_WW4END1" + ], + [ + "MONITOR_NW4END3_2", + "VFRAME_NW4END3" + ], + [ + "MONITOR_SW4END1_2", + "VFRAME_SW4END1" + ], + [ + "MONITOR_SW4END0_2", + "VFRAME_SW4END0" + ], + [ + "MONITOR_NE4C1_2", + "VFRAME_NE4C1" + ], + [ + "MONITOR_IMUX5_2", + "VFRAME_IMUX5" + ], + [ + "MONITOR_EE4C0_2", + "VFRAME_EE4C0" + ], + [ + "MONITOR_SW4A3_2", + "VFRAME_SW4A3" + ], + [ + "MONITOR_IMUX41_2", + "VFRAME_IMUX41" + ], + [ + "MONITOR_IMUX10_2", + "VFRAME_IMUX10" + ], + [ + "MONITOR_LH5_2", + "VFRAME_LH5" + ], + [ + "MONITOR_IMUX4_2", + "VFRAME_IMUX4" + ], + [ + "MONITOR_EL1BEG3_2", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_EE4A1_2", + "VFRAME_EE4A1" + ], + [ + "MONITOR_FAN6_2", + "VFRAME_FAN6" + ], + [ + "MONITOR_EE2BEG1_2", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_IMUX22_2", + "VFRAME_IMUX22" + ], + [ + "MONITOR_ER1BEG2_2", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_EE4C2_2", + "VFRAME_EE4C2" + ], + [ + "MONITOR_WW4B2_2", + "VFRAME_WW4B2" + ], + [ + "MONITOR_IMUX32_2", + "VFRAME_IMUX32" + ], + [ + "MONITOR_FAN7_2", + "VFRAME_FAN7" + ], + [ + "MONITOR_CLK0_2", + "VFRAME_CLK0" + ], + [ + "MONITOR_NE4C0_2", + "VFRAME_NE4C0" + ], + [ + "MONITOR_WW4END0_2", + "VFRAME_WW4END0" + ], + [ + "MONITOR_IMUX25_2", + "VFRAME_IMUX25" + ], + [ + "MONITOR_NW4A3_2", + "VFRAME_NW4A3" + ], + [ + "MONITOR_WW4B0_2", + "VFRAME_WW4B0" + ], + [ + "MONITOR_SE4BEG1_2", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_EE4A3_2", + "VFRAME_EE4A3" + ], + [ + "MONITOR_NE4BEG3_2", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_FAN1_2", + "VFRAME_FAN1" + ], + [ + "MONITOR_NW4END0_2", + "VFRAME_NW4END0" + ], + [ + "MONITOR_IMUX28_2", + "VFRAME_IMUX28" + ], + [ + "MONITOR_IMUX43_2", + "VFRAME_IMUX43" + ], + [ + "MONITOR_EE2A0_2", + "VFRAME_EE2A0" + ], + [ + "MONITOR_SW4A0_2", + "VFRAME_SW4A0" + ], + [ + "MONITOR_IMUX18_2", + "VFRAME_IMUX18" + ], + [ + "MONITOR_WW4A0_2", + "VFRAME_WW4A0" + ], + [ + "MONITOR_WW2A3_2", + "VFRAME_WW2A3" + ], + [ + "MONITOR_WW2END2_2", + "VFRAME_WW2END2" + ], + [ + "MONITOR_NE4BEG0_2", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_IMUX0_2", + "VFRAME_IMUX0" + ], + [ + "MONITOR_FAN0_2", + "VFRAME_FAN0" + ], + [ + "MONITOR_WW4C3_2", + "VFRAME_WW4C3" + ], + [ + "MONITOR_NW4A1_2", + "VFRAME_NW4A1" + ], + [ + "MONITOR_EE4A0_2", + "VFRAME_EE4A0" + ], + [ + "MONITOR_CTRL1_2", + "VFRAME_CTRL1" + ] + ], + "tile_types": [ + "MONITOR_MID_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_WW4END3", + "WW4C3" + ], + [ + "INT_INTERFACE_WW2END0", + "WW2A0" + ], + [ + "INT_INTERFACE_EL1BEG2", + "EL1END2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L21", + "LOGIC_OUTS_L21" + ], + [ + "INT_INTERFACE_NE4BEG0", + "NE6A0" + ], + [ + "INT_INTERFACE_EE4A3", + "EE4B3" + ], + [ + "INT_INTERFACE_BRAM_IMUX38", + "IMUX_L38" + ], + [ + "INT_INTERFACE_BYP1", + "BYP_L1" + ], + [ + "INT_INTERFACE_EL1BEG1", + "EL1END1" + ], + [ + "INT_INTERFACE_SW4A3", + "SW6BEG3" + ], + [ + "INT_INTERFACE_WL1END1", + "WL1BEG1" + ], + [ + "INT_INTERFACE_BRAM_IMUX30", + "IMUX_L30" + ], + [ + "INT_INTERFACE_NW2A3", + "NW2A3" + ], + [ + "INT_INTERFACE_SE4BEG3", + "SE6A3" + ], + [ + "INT_INTERFACE_BRAM_IMUX3", + "IMUX_L3" + ], + [ + "INT_INTERFACE_BRAM_IMUX16", + "IMUX_L16" + ], + [ + "INT_INTERFACE_BRAM_IMUX15", + "IMUX_L15" + ], + [ + "INT_INTERFACE_BRAM_IMUX17", + "IMUX_L17" + ], + [ + "INT_INTERFACE_ER1BEG1", + "ER1END1" + ], + [ + "INT_INTERFACE_BRAM_IMUX26", + "IMUX_L26" + ], + [ + "INT_INTERFACE_NW4A1", + "NW6BEG1" + ], + [ + "INT_INTERFACE_SW4A0", + "SW6BEG0" + ], + [ + "INT_INTERFACE_FAN5", + "FAN_L5" + ], + [ + "INT_INTERFACE_BRAM_IMUX23", + "IMUX_L23" + ], + [ + "INT_INTERFACE_BRAM_IMUX45", + "IMUX_L45" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L20", + "LOGIC_OUTS_L20" + ], + [ + "INT_INTERFACE_CLK0", + "CLK_L0" + ], + [ + "INT_INTERFACE_BRAM_IMUX18", + "IMUX_L18" + ], + [ + "INT_INTERFACE_BRAM_IMUX8", + "IMUX_L8" + ], + [ + "INT_INTERFACE_BRAM_IMUX2", + "IMUX_L2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L14", + "LOGIC_OUTS_L14" + ], + [ + "INT_INTERFACE_NW4END2", + "NW6E2" + ], + [ + "INT_INTERFACE_LH11", + "LH10" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L19", + "LOGIC_OUTS_L19" + ], + [ + "INT_INTERFACE_WW4A0", + "WW4BEG0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L2", + "LOGIC_OUTS_L2" + ], + [ + "INT_INTERFACE_NW2A0", + "NW2A0" + ], + [ + "INT_INTERFACE_WW2END3", + "WW2A3" + ], + [ + "INT_INTERFACE_EE4BEG1", + "EE4A1" + ], + [ + "INT_INTERFACE_NW4A2", + "NW6BEG2" + ], + [ + "INT_INTERFACE_BRAM_IMUX32", + "IMUX_L32" + ], + [ + "INT_INTERFACE_EE4B0", + "EE4C0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L17", + "LOGIC_OUTS_L17" + ], + [ + "INT_INTERFACE_WR1END1", + "WR1BEG1" + ], + [ + "INT_INTERFACE_SE4C2", + "SE6END2" + ], + [ + "INT_INTERFACE_CLK1", + "CLK_L1" + ], + [ + "INT_INTERFACE_NE4C1", + "NE6END1" + ], + [ + "INT_INTERFACE_ER1BEG0", + "ER1END0" + ], + [ + "INT_INTERFACE_BRAM_IMUX24", + "IMUX_L24" + ], + [ + "INT_INTERFACE_SW4END3", + "SW6E3" + ], + [ + "INT_INTERFACE_WW4C2", + "WW4B2" + ], + [ + "INT_INTERFACE_NE2A1", + "NE2END1" + ], + [ + "INT_INTERFACE_NW2A1", + "NW2A1" + ], + [ + "INT_INTERFACE_EE4A2", + "EE4B2" + ], + [ + "INT_INTERFACE_SE4BEG1", + "SE6A1" + ], + [ + "INT_INTERFACE_EE2A2", + "EE2END2" + ], + [ + "INT_INTERFACE_BRAM_IMUX20", + "IMUX_L20" + ], + [ + "INT_INTERFACE_WR1END0", + "WR1BEG0" + ], + [ + "INT_INTERFACE_SW2A3", + "SW2A3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L11", + "LOGIC_OUTS_L11" + ], + [ + "INT_INTERFACE_WW2END2", + "WW2A2" + ], + [ + "INT_INTERFACE_SE2A3", + "SE2END3" + ], + [ + "INT_INTERFACE_BYP3", + "BYP_L3" + ], + [ + "INT_INTERFACE_EL1BEG0", + "EL1END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L7", + "LOGIC_OUTS_L7" + ], + [ + "INT_INTERFACE_BRAM_IMUX39", + "IMUX_L39" + ], + [ + "INT_INTERFACE_BRAM_IMUX10", + "IMUX_L10" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L5", + "LOGIC_OUTS_L5" + ], + [ + "INT_INTERFACE_ER1BEG3", + "ER1END3" + ], + [ + "INT_INTERFACE_BRAM_IMUX27", + "IMUX_L27" + ], + [ + "INT_INTERFACE_EE4A0", + "EE4B0" + ], + [ + "INT_INTERFACE_WW4A2", + "WW4BEG2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L10", + "LOGIC_OUTS_L10" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L16", + "LOGIC_OUTS_L16" + ], + [ + "INT_INTERFACE_SE4BEG2", + "SE6A2" + ], + [ + "INT_INTERFACE_SE4C0", + "SE6END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L15", + "LOGIC_OUTS_L15" + ], + [ + "INT_INTERFACE_EL1BEG3", + "EL1END3" + ], + [ + "INT_INTERFACE_FAN0", + "FAN_L0" + ], + [ + "INT_INTERFACE_BRAM_IMUX13", + "IMUX_L13" + ], + [ + "INT_INTERFACE_NW4END3", + "NW6E3" + ], + [ + "INT_INTERFACE_FAN6", + "FAN_L6" + ], + [ + "INT_INTERFACE_BRAM_IMUX25", + "IMUX_L25" + ], + [ + "INT_INTERFACE_BRAM_IMUX21", + "IMUX_L21" + ], + [ + "INT_INTERFACE_FAN2", + "FAN_L2" + ], + [ + "INT_INTERFACE_NE2A0", + "NE2END0" + ], + [ + "INT_INTERFACE_WW4A1", + "WW4BEG1" + ], + [ + "INT_INTERFACE_NW4END1", + "NW6E1" + ], + [ + "INT_INTERFACE_NE4BEG1", + "NE6A1" + ], + [ + "INT_INTERFACE_BRAM_IMUX28", + "IMUX_L28" + ], + [ + "INT_INTERFACE_BRAM_IMUX36", + "IMUX_L36" + ], + [ + "INT_INTERFACE_NE4C3", + "NE6END3" + ], + [ + "INT_INTERFACE_ER1BEG2", + "ER1END2" + ], + [ + "INT_INTERFACE_EE4C1", + "EE4END1" + ], + [ + "INT_INTERFACE_BYP4", + "BYP_L4" + ], + [ + "INT_INTERFACE_BRAM_IMUX19", + "IMUX_L19" + ], + [ + "INT_INTERFACE_NE4BEG3", + "NE6A3" + ], + [ + "INT_INTERFACE_BRAM_IMUX0", + "IMUX_L0" + ], + [ + "INT_INTERFACE_SW4A1", + "SW6BEG1" + ], + [ + "INT_INTERFACE_BYP5", + "BYP_L5" + ], + [ + "INT_INTERFACE_EE2BEG0", + "EE2A0" + ], + [ + "INT_INTERFACE_SE4BEG0", + "SE6A0" + ], + [ + "INT_INTERFACE_LH4", + "LH3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L22", + "LOGIC_OUTS_L22" + ], + [ + "INT_INTERFACE_BRAM_IMUX9", + "IMUX_L9" + ], + [ + "INT_INTERFACE_SE2A0", + "SE2END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L0", + "LOGIC_OUTS_L0" + ], + [ + "INT_INTERFACE_EE2BEG2", + "EE2A2" + ], + [ + "INT_INTERFACE_BYP2", + "BYP_L2" + ], + [ + "INT_INTERFACE_EE4C3", + "EE4END3" + ], + [ + "INT_INTERFACE_WW4B2", + "WW4A2" + ], + [ + "INT_INTERFACE_EE2A3", + "EE2END3" + ], + [ + "INT_INTERFACE_SE2A1", + "SE2END1" + ], + [ + "INT_INTERFACE_LH9", + "LH8" + ], + [ + "INT_INTERFACE_BRAM_IMUX12", + "IMUX_L12" + ], + [ + "INT_INTERFACE_BRAM_IMUX42", + "IMUX_L42" + ], + [ + "INT_INTERFACE_CTRL1", + "CTRL_L1" + ], + [ + "INT_INTERFACE_LH12", + "LH11" + ], + [ + "INT_INTERFACE_NE4C2", + "NE6END2" + ], + [ + "INT_INTERFACE_WW4A3", + "WW4BEG3" + ], + [ + "INT_INTERFACE_EE4B3", + "EE4C3" + ], + [ + "INT_INTERFACE_EE2BEG1", + "EE2A1" + ], + [ + "INT_INTERFACE_WW2A1", + "WW2BEG1" + ], + [ + "INT_INTERFACE_LH3", + "LH2" + ], + [ + "INT_INTERFACE_BYP7", + "BYP_L7" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L1", + "LOGIC_OUTS_L1" + ], + [ + "INT_INTERFACE_BRAM_IMUX46", + "IMUX_L46" + ], + [ + "INT_INTERFACE_EE4C0", + "EE4END0" + ], + [ + "INT_INTERFACE_LH6", + "LH5" + ], + [ + "INT_INTERFACE_BRAM_IMUX22", + "IMUX_L22" + ], + [ + "INT_INTERFACE_BRAM_IMUX41", + "IMUX_L41" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L6", + "LOGIC_OUTS_L6" + ], + [ + "INT_INTERFACE_BRAM_IMUX44", + "IMUX_L44" + ], + [ + "INT_INTERFACE_BRAM_IMUX29", + "IMUX_L29" + ], + [ + "INT_INTERFACE_WL1END0", + "WL1BEG0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L8", + "LOGIC_OUTS_L8" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L13", + "LOGIC_OUTS_L13" + ], + [ + "INT_INTERFACE_BRAM_IMUX5", + "IMUX_L5" + ], + [ + "INT_INTERFACE_WL1END3", + "WL1BEG3" + ], + [ + "INT_INTERFACE_BRAM_IMUX6", + "IMUX_L6" + ], + [ + "INT_INTERFACE_EE2A0", + "EE2END0" + ], + [ + "INT_INTERFACE_MONITOR_P", + "MONITOR_P" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L23", + "LOGIC_OUTS_L23" + ], + [ + "INT_INTERFACE_BRAM_IMUX14", + "IMUX_L14" + ], + [ + "INT_INTERFACE_BRAM_IMUX40", + "IMUX_L40" + ], + [ + "INT_INTERFACE_SW4END0", + "SW6E0" + ], + [ + "INT_INTERFACE_WW4B1", + "WW4A1" + ], + [ + "INT_INTERFACE_WW4C3", + "WW4B3" + ], + [ + "INT_INTERFACE_WW4C1", + "WW4B1" + ], + [ + "INT_INTERFACE_NW2A2", + "NW2A2" + ], + [ + "INT_INTERFACE_EE4BEG2", + "EE4A2" + ], + [ + "INT_INTERFACE_EE2A1", + "EE2END1" + ], + [ + "INT_INTERFACE_WW2A0", + "WW2BEG0" + ], + [ + "INT_INTERFACE_WW2A3", + "WW2BEG3" + ], + [ + "INT_INTERFACE_SW2A2", + "SW2A2" + ], + [ + "INT_INTERFACE_NW4END0", + "NW6E0" + ], + [ + "INT_INTERFACE_BRAM_IMUX33", + "IMUX_L33" + ], + [ + "INT_INTERFACE_EE4A1", + "EE4B1" + ], + [ + "INT_INTERFACE_BYP0", + "BYP_L0" + ], + [ + "INT_INTERFACE_SW4END1", + "SW6E1" + ], + [ + "INT_INTERFACE_SE4C3", + "SE6END3" + ], + [ + "INT_INTERFACE_LH10", + "LH9" + ], + [ + "INT_INTERFACE_WR1END2", + "WR1BEG2" + ], + [ + "INT_INTERFACE_EE2BEG3", + "EE2A3" + ], + [ + "INT_INTERFACE_WW4B0", + "WW4A0" + ], + [ + "INT_INTERFACE_BRAM_IMUX1", + "IMUX_L1" + ], + [ + "INT_INTERFACE_LH1", + "LH0" + ], + [ + "INT_INTERFACE_LH2", + "LH1" + ], + [ + "INT_INTERFACE_BRAM_IMUX37", + "IMUX_L37" + ], + [ + "INT_INTERFACE_WL1END2", + "WL1BEG2" + ], + [ + "INT_INTERFACE_BRAM_IMUX47", + "IMUX_L47" + ], + [ + "INT_INTERFACE_LH5", + "LH4" + ], + [ + "INT_INTERFACE_FAN7", + "FAN_L7" + ], + [ + "INT_INTERFACE_BRAM_IMUX34", + "IMUX_L34" + ], + [ + "INT_INTERFACE_SW2A0", + "SW2A0" + ], + [ + "INT_INTERFACE_SE2A2", + "SE2END2" + ], + [ + "INT_INTERFACE_EE4B2", + "EE4C2" + ], + [ + "INT_INTERFACE_EE4BEG3", + "EE4A3" + ], + [ + "INT_INTERFACE_LH7", + "LH6" + ], + [ + "INT_INTERFACE_WR1END3", + "WR1BEG3" + ], + [ + "INT_INTERFACE_WW4B3", + "WW4A3" + ], + [ + "INT_INTERFACE_LH8", + "LH7" + ], + [ + "INT_INTERFACE_WW4END2", + "WW4C2" + ], + [ + "INT_INTERFACE_BRAM_IMUX4", + "IMUX_L4" + ], + [ + "INT_INTERFACE_SE4C1", + "SE6END1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L3", + "LOGIC_OUTS_L3" + ], + [ + "INT_INTERFACE_NE2A3", + "NE2END3" + ], + [ + "INT_INTERFACE_NE4BEG2", + "NE6A2" + ], + [ + "INT_INTERFACE_FAN1", + "FAN_L1" + ], + [ + "INT_INTERFACE_NW4A0", + "NW6BEG0" + ], + [ + "INT_INTERFACE_BRAM_IMUX7", + "IMUX_L7" + ], + [ + "INT_INTERFACE_WW4C0", + "WW4B0" + ], + [ + "INT_INTERFACE_BRAM_IMUX43", + "IMUX_L43" + ], + [ + "INT_INTERFACE_BRAM_IMUX11", + "IMUX_L11" + ], + [ + "INT_INTERFACE_NE2A2", + "NE2END2" + ], + [ + "INT_INTERFACE_SW4END2", + "SW6E2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L18", + "LOGIC_OUTS_L18" + ], + [ + "INT_INTERFACE_MONITOR_N", + "MONITOR_N" + ], + [ + "INT_INTERFACE_BRAM_IMUX31", + "IMUX_L31" + ], + [ + "INT_INTERFACE_WW4END1", + "WW4C1" + ], + [ + "INT_INTERFACE_EE4B1", + "EE4C1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L12", + "LOGIC_OUTS_L12" + ], + [ + "INT_INTERFACE_FAN4", + "FAN_L4" + ], + [ + "INT_INTERFACE_WW4END0", + "WW4C0" + ], + [ + "INT_INTERFACE_EE4BEG0", + "EE4A0" + ], + [ + "INT_INTERFACE_BYP6", + "BYP_L6" + ], + [ + "INT_INTERFACE_WW2A2", + "WW2BEG2" + ], + [ + "INT_INTERFACE_NW4A3", + "NW6BEG3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L4", + "LOGIC_OUTS_L4" + ], + [ + "INT_INTERFACE_FAN3", + "FAN_L3" + ], + [ + "INT_INTERFACE_EE4C2", + "EE4END2" + ], + [ + "INT_INTERFACE_SW4A2", + "SW6BEG2" + ], + [ + "INT_INTERFACE_WW2END1", + "WW2A1" + ], + [ + "INT_INTERFACE_BRAM_IMUX35", + "IMUX_L35" + ], + [ + "INT_INTERFACE_SW2A1", + "SW2A1" + ], + [ + "INT_INTERFACE_NE4C0", + "NE6END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L9", + "LOGIC_OUTS_L9" + ], + [ + "INT_INTERFACE_CTRL0", + "CTRL_L0" + ] + ], + "tile_types": [ + "BRAM_INT_INTERFACE_L", + "INT_L" + ] + }, + { + "grid_deltas": [ + -1, + 6 + ], + "wire_pairs": [ + [ + "CMT_TOP_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH1_2", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH2_2", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_LH6_2", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_LH7_2", + "VBRK_LH7" + ], + [ + "CMT_TOP_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH12_2", + "VBRK_LH12" + ], + [ + "CMT_TOP_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_LH11_2", + "VBRK_LH11" + ], + [ + "CMT_TOP_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE4B3_2", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH4_2", + "VBRK_LH4" + ], + [ + "CMT_TOP_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_LH5_2", + "VBRK_LH5" + ], + [ + "CMT_TOP_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH3_2", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH10_2", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_LH8_2", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_LH9_2", + "VBRK_LH9" + ], + [ + "CMT_TOP_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW2A2_2", + "VBRK_NW2A2" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "CLK_HROW_LH10_2", + "VBRK_LH10" + ], + [ + "CLK_HROW_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_LH11_2", + "VBRK_LH11" + ], + [ + "CLK_HROW_LH7_2", + "VBRK_LH7" + ], + [ + "CLK_HROW_NW4A1_2", + "VBRK_NW4A1" + ], + [ + "CLK_HROW_MONITOR_N_2", + "VBRK_MONITOR_N" + ], + [ + "CLK_HROW_WW4END3_2", + "VBRK_WW4END3" + ], + [ + "CLK_HROW_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_WW4END1_2", + "VBRK_WW4END1" + ], + [ + "CLK_HROW_SW4END1_2", + "VBRK_SW4END1" + ], + [ + "CLK_HROW_WW2END3_2", + "VBRK_WW2END3" + ], + [ + "CLK_HROW_NW4A3_2", + "VBRK_NW4A3" + ], + [ + "CLK_HROW_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_LH1_2", + "VBRK_LH1" + ], + [ + "CLK_HROW_WL1END3_2", + "VBRK_WL1END3" + ], + [ + "CLK_HROW_EL1BEG1_2", + "VBRK_EL1BEG1" + ], + [ + "CLK_HROW_SW4A2_2", + "VBRK_SW4A2" + ], + [ + "CLK_HROW_WW4END2_2", + "VBRK_WW4END2" + ], + [ + "CLK_HROW_NE2A0_2", + "VBRK_NE2A0" + ], + [ + "CLK_HROW_EE4B2_2", + "VBRK_EE4B2" + ], + [ + "CLK_HROW_EE4A3_2", + "VBRK_EE4A3" + ], + [ + "CLK_HROW_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "CLK_HROW_WW4B1_2", + "VBRK_WW4B1" + ], + [ + "CLK_HROW_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "CLK_HROW_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "CLK_HROW_LH8_2", + "VBRK_LH8" + ], + [ + "CLK_HROW_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "CLK_HROW_EE2A0_2", + "VBRK_EE2A0" + ], + [ + "CLK_HROW_NE4BEG1_2", + "VBRK_NE4BEG1" + ], + [ + "CLK_HROW_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_LH12_2", + "VBRK_LH12" + ], + [ + "CLK_HROW_ER1BEG0_2", + "VBRK_ER1BEG0" + ], + [ + "CLK_HROW_WW4C0_2", + "VBRK_WW4C0" + ], + [ + "CLK_HROW_EE2A3_2", + "VBRK_EE2A3" + ], + [ + "CLK_HROW_LH4_2", + "VBRK_LH4" + ], + [ + "CLK_HROW_EE2BEG0_2", + "VBRK_EE2BEG0" + ], + [ + "CLK_HROW_NW2A1_2", + "VBRK_NW2A1" + ], + [ + "CLK_HROW_EE2A2_2", + "VBRK_EE2A2" + ], + [ + "CLK_HROW_WR1END0_2", + "VBRK_WR1END0" + ], + [ + "CLK_HROW_WL1END0_2", + "VBRK_WL1END0" + ], + [ + "CLK_HROW_EE2BEG3_2", + "VBRK_EE2BEG3" + ], + [ + "CLK_HROW_WL1END1_2", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_LH5_2", + "VBRK_LH5" + ], + [ + "CLK_HROW_EE4B0_2", + "VBRK_EE4B0" + ], + [ + "CLK_HROW_WR1END1_2", + "VBRK_WR1END1" + ], + [ + "CLK_HROW_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "CLK_HROW_SW4END2_2", + "VBRK_SW4END2" + ], + [ + "CLK_HROW_NE4BEG0_2", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_NE4BEG2_2", + "VBRK_NE4BEG2" + ], + [ + "CLK_HROW_NW2A2_2", + "VBRK_NW2A2" + ], + [ + "CLK_HROW_LH9_2", + "VBRK_LH9" + ], + [ + "CLK_HROW_ER1BEG1_2", + "VBRK_ER1BEG1" + ], + [ + "CLK_HROW_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "CLK_HROW_NE4C0_2", + "VBRK_NE4C0" + ], + [ + "CLK_HROW_EE4C2_2", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_WW4C2_2", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "CLK_HROW_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "CLK_HROW_EL1BEG2_2", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_WW2A1_2", + "VBRK_WW2A1" + ], + [ + "CLK_HROW_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_WW4A1_2", + "VBRK_WW4A1" + ], + [ + "CLK_HROW_NE2A2_2", + "VBRK_NE2A2" + ], + [ + "CLK_HROW_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "CLK_HROW_EE4C1_2", + "VBRK_EE4C1" + ], + [ + "CLK_HROW_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "CLK_HROW_EE4C0_2", + "VBRK_EE4C0" + ], + [ + "CLK_HROW_EE2A1_2", + "VBRK_EE2A1" + ], + [ + "CLK_HROW_WW4A0_2", + "VBRK_WW4A0" + ], + [ + "CLK_HROW_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_EE4BEG0_2", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_LH2_2", + "VBRK_LH2" + ], + [ + "CLK_HROW_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "CLK_HROW_NW4A2_2", + "VBRK_NW4A2" + ], + [ + "CLK_HROW_NE4C2_2", + "VBRK_NE4C2" + ], + [ + "CLK_HROW_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "CLK_HROW_EE2BEG1_2", + "VBRK_EE2BEG1" + ], + [ + "CLK_HROW_EE4BEG1_2", + "VBRK_EE4BEG1" + ], + [ + "CLK_HROW_WW4C3_2", + "VBRK_WW4C3" + ], + [ + "CLK_HROW_WL1END2_2", + "VBRK_WL1END2" + ], + [ + "CLK_HROW_NE4C3_2", + "VBRK_NE4C3" + ], + [ + "CLK_HROW_WW4END0_2", + "VBRK_WW4END0" + ], + [ + "CLK_HROW_SW4END3_2", + "VBRK_SW4END3" + ], + [ + "CLK_HROW_SW4END0_2", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_NE2A3_2", + "VBRK_NE2A3" + ], + [ + "CLK_HROW_EE2BEG2_2", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_WW2END0_2", + "VBRK_WW2END0" + ], + [ + "CLK_HROW_EE4BEG2_2", + "VBRK_EE4BEG2" + ], + [ + "CLK_HROW_WW4A2_2", + "VBRK_WW4A2" + ], + [ + "CLK_HROW_EL1BEG3_2", + "VBRK_EL1BEG3" + ], + [ + "CLK_HROW_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "CLK_HROW_WW2END1_2", + "VBRK_WW2END1" + ], + [ + "CLK_HROW_NW4A0_2", + "VBRK_NW4A0" + ], + [ + "CLK_HROW_EE4A1_2", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_EE4C3_2", + "VBRK_EE4C3" + ], + [ + "CLK_HROW_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "CLK_HROW_WW4B3_2", + "VBRK_WW4B3" + ], + [ + "CLK_HROW_WW2A2_2", + "VBRK_WW2A2" + ], + [ + "CLK_HROW_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_ER1BEG3_2", + "VBRK_ER1BEG3" + ], + [ + "CLK_HROW_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "CLK_HROW_ER1BEG2_2", + "VBRK_ER1BEG2" + ], + [ + "CLK_HROW_WW4A3_2", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_WW2A3_2", + "VBRK_WW2A3" + ], + [ + "CLK_HROW_SW4A3_2", + "VBRK_SW4A3" + ], + [ + "CLK_HROW_WW2END2_2", + "VBRK_WW2END2" + ], + [ + "CLK_HROW_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_NE2A1_2", + "VBRK_NE2A1" + ], + [ + "CLK_HROW_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_EL1BEG0_2", + "VBRK_EL1BEG0" + ], + [ + "CLK_HROW_NW2A3_2", + "VBRK_NW2A3" + ], + [ + "CLK_HROW_NW2A0_2", + "VBRK_NW2A0" + ], + [ + "CLK_HROW_LH3_2", + "VBRK_LH3" + ], + [ + "CLK_HROW_WW4C1_2", + "VBRK_WW4C1" + ], + [ + "CLK_HROW_WW2A0_2", + "VBRK_WW2A0" + ], + [ + "CLK_HROW_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_MONITOR_P_2", + "VBRK_MONITOR_P" + ], + [ + "CLK_HROW_WR1END3_2", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_NE4C1_2", + "VBRK_NE4C1" + ], + [ + "CLK_HROW_EE4B1_2", + "VBRK_EE4B1" + ], + [ + "CLK_HROW_LH6_2", + "VBRK_LH6" + ], + [ + "CLK_HROW_EE4B3_2", + "VBRK_EE4B3" + ] + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_BRAM_CK_IN1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_BRAM_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_BRAM_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_BRAM_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_BRAM_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_BRAM_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_BRAM_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "HCLK_BRAM_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_BRAM_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "HCLK_BRAM_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_BRAM_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ], + [ + "HCLK_BRAM_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "HCLK_BRAM_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_BRAM_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ] + ], + "tile_types": [ + "HCLK_BRAM", + "HCLK_INT_INTERFACE" + ] + }, + { + "grid_deltas": [ + -1, + -9 + ], + "wire_pairs": [ + [ + "PCIE_LH5_19", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_MONITOR_N_19", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_19", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_WW4C2_19", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_SW4END2_19", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_IMUX18_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_WW4END3_19", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_LH3_19", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_EE4BEG1_19", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LH7_19", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_IMUX0_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_IMUX31_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_19", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_SW2A1_19", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_SW4A2_19", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_IMUX35_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_EE4C1_19", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_IMUX11_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_IMUX7_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_NW2A2_19", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_19", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_19", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_NE4BEG0_19", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_IMUX26_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_CTRL1_R_19", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_MONITOR_P_19", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_LH2_19", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_19", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_19", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_IMUX34_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_IMUX43_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_IMUX12_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_EL1BEG1_19", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_IMUX21_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_19", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_NE4BEG1_19", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_FAN0_R_19", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_19", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_ER1BEG3_19", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_IMUX2_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_WW4C3_19", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_EE4A2_19", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_19", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_NE2A0_19", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_EE4A0_19", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_SE4C2_19", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_SE2A2_19", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_NE4C2_19", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_LH4_19", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_CTRL0_R_19", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_IMUX9_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_19", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_WW2A0_19", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_ER1BEG2_19", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_IMUX20_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_IMUX13_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_IMUX42_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_WL1END2_19", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_CLK0_R_19", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_19", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_NE4C1_19", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_NW2A3_19", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_FAN6_R_19", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_EL1BEG3_19", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_LH9_19", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_IMUX39_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_SW4A0_19", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_EE4BEG2_19", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX37_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_SE2A3_19", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_IMUX4_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_SE4BEG3_19", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_SE2A1_19", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_WW2END3_19", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_NW4END3_19", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_LH12_19", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_IMUX10_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_19", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_LH11_19", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_IMUX27_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_IMUX36_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_19", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_19", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_NE2A3_19", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_IMUX1_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_IMUX29_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_EE4C0_19", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_IMUX40_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_SE4C1_19", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_WW4C1_19", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_NE4BEG3_19", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_EE2A2_19", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_FAN7_R_19", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_IMUX25_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_SW4A3_19", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_19", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_WR1END2_19", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_WW4B2_19", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_IMUX3_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_FAN1_R_19", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_IMUX16_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_19", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_WR1END3_19", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_SW2A2_19", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_SW2A3_19", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_WW4END2_19", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_SW4A1_19", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_NE2A2_19", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_FAN4_R_19", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_SW4END0_19", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_SW4END1_19", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_IMUX44_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_WR1END1_19", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_FAN3_R_19", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX47_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_WW4A3_19", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_IMUX38_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_NE2A1_19", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_FAN5_R_19", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_19", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_NE4C3_19", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_CLK1_R_19", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_WW2END1_19", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_WW4A0_19", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_WW4END0_19", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_19", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_IMUX41_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_WW4END1_19", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_SE4C3_19", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_WW2END0_19", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_19", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_WW4B3_19", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_BYP5_R_19", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_IMUX5_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_NW2A0_19", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_FAN2_R_19", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_NW4A2_19", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_WW2A2_19", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_IMUX46_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_BYP3_R_19", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_WW4B0_19", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_EE4B1_19", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_BYP7_R_19", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_WL1END3_19", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_WR1END0_19", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_IMUX8_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_IMUX32_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_19", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_NW4A1_19", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_EE4B2_19", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_19", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_BYP6_R_19", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_EE4A1_19", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_IMUX17_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_19", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_IMUX33_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_WW2A1_19", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_WW4B1_19", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_LH6_19", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_IMUX22_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_NW4END2_19", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_NW4A0_19", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WW4A1_19", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_SE4BEG1_19", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_EE4B3_19", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_IMUX19_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_EE2BEG2_19", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_EE4C3_19", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_EE2BEG0_19", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_ER1BEG1_19", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_EE2BEG1_19", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_EL1BEG2_19", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_BYP2_R_19", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_IMUX28_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_BYP0_R_19", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_19", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_NE4C0_19", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_IMUX14_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_EE2BEG3_19", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_ER1BEG0_19", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_SW4END3_19", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_WL1END1_19", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_LH1_19", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_BYP1_R_19", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_EE4BEG3_19", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_WW2A3_19", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_SE4C0_19", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_NW4END0_19", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_IMUX24_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_IMUX30_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_NW4END1_19", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_SE2A0_19", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_SE4BEG2_19", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_WW4A2_19", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_LH10_19", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_EE4A3_19", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_IMUX45_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_WW4C0_19", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_NW4A3_19", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_WW2END2_19", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_EE2A1_19", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_EE2A3_19", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_SE4BEG0_19", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_WL1END0_19", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_SW2A0_19", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_EE4C2_19", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_LH8_19", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4BEG0_19", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_EE4B0_19", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_EL1BEG0_19", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_IMUX6_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_NW2A1_19", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_IMUX23_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_NE4BEG2_19", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_EE2A0_19", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_IMUX15_R_19", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_19", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_BYP4_R_19", + "INT_INTERFACE_BYP4" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "CLK_PMV_IMUX2_2", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_PMV_EE4A1_2", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_PMV_EE2BEG2_2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_PMV_EE4BEG1_2", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_PMV_NW2A1_2", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_PMV_EE4C0_2", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_PMV_EL1BEG0_2", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_PMV_CTRL1_2", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_PMV_IMUX6_2", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_PMV_CLK1_2", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_PMV_IMUX41_2", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_PMV_NW4END3_2", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_PMV_BYP5_2", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_PMV_NE4C2_2", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_PMV_WW4C0_2", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_PMV_LH2_2", + "INT_INTERFACE_LH2" + ], + [ + "CLK_PMV_FAN2_2", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_PMV_NW4A1_2", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_PMV_BYP0_2", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_PMV_IMUX25_2", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_PMV_IMUX42_2", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_PMV_BYP7_2", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_PMV_FAN1_2", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_PMV_CTRL0_2", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_PMV_NW4A3_2", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_PMV_IMUX43_2", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_PMV_LH8_2", + "INT_INTERFACE_LH8" + ], + [ + "CLK_PMV_ER1BEG2_2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_PMV_NW2A2_2", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_PMV_EE2BEG1_2", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_PMV_WR1END0_2", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_PMV_LH5_2", + "INT_INTERFACE_LH5" + ], + [ + "CLK_PMV_BYP3_2", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_PMV_IMUX13_2", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_PMV_IMUX40_2", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_PMV_WW4A3_2", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_PMV_EE4BEG0_2", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_PMV_EE2A2_2", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_PMV_SW4END2_2", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_PMV_LH1_2", + "INT_INTERFACE_LH1" + ], + [ + "CLK_PMV_ER1BEG0_2", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_PMV_IMUX8_2", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_PMV_IMUX44_2", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_PMV_SE4BEG2_2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_PMV_WW4A0_2", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_PMV_SE4C2_2", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_PMV_EL1BEG1_2", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_PMV_SW4A1_2", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_PMV_IMUX11_2", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_PMV_WW2A0_2", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_PMV_IMUX27_2", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_PMV_NE2A2_2", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_PMV_EE4B2_2", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_PMV_SE2A3_2", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_PMV_NE4C0_2", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_PMV_IMUX32_2", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_PMV_WW4B3_2", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_PMV_SE4C3_2", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_PMV_NW4A2_2", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_PMV_WL1END1_2", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_PMV_NE4BEG3_2", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_PMV_EE4BEG3_2", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_PMV_FAN0_2", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_PMV_FAN7_2", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_PMV_WL1END3_2", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_PMV_WL1END2_2", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_PMV_WW4END0_2", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_PMV_WW4B0_2", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_PMV_WW2END2_2", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_PMV_EE4A0_2", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_PMV_FAN6_2", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_PMV_EE4B1_2", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_PMV_LH4_2", + "INT_INTERFACE_LH4" + ], + [ + "CLK_PMV_IMUX28_2", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_PMV_IMUX39_2", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_PMV_ER1BEG1_2", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_PMV_NE2A1_2", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_PMV_IMUX21_2", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_PMV_NE2A3_2", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_PMV_EL1BEG3_2", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_PMV_WW2END0_2", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_PMV_EE2A1_2", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_PMV_IMUX10_2", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_PMV_BYP2_2", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_PMV_IMUX34_2", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_PMV_WW4A1_2", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_PMV_EE2BEG3_2", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_PMV_WW4B2_2", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_PMV_SE4BEG1_2", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_PMV_WW4B1_2", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_PMV_NW4END1_2", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_PMV_NE4C1_2", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_PMV_FAN5_2", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_PMV_SW4A0_2", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_PMV_WR1END2_2", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_PMV_IMUX35_2", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_PMV_SE4C1_2", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_PMV_LH9_2", + "INT_INTERFACE_LH9" + ], + [ + "CLK_PMV_BYP1_2", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_PMV_IMUX16_2", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_PMV_NE4BEG0_2", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_PMV_WW4C2_2", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_PMV_WW4END2_2", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_PMV_EE4A2_2", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_PMV_EE4BEG2_2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_PMV_FAN4_2", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_PMV_IMUX36_2", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_PMV_EE4C2_2", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_PMV_IMUX1_2", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_PMV_WW4END3_2", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_PMV_EE4C1_2", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_PMV_EE2A0_2", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_PMV_NW4END0_2", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_PMV_NE4BEG1_2", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_PMV_WW4A2_2", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_PMV_IMUX47_2", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_PMV_IMUX29_2", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_PMV_EE4B3_2", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_PMV_IMUX33_2", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_PMV_EE4B0_2", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_PMV_SW2A2_2", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_PMV_SW4END3_2", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_PMV_SW2A1_2", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_PMV_IMUX4_2", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_PMV_IMUX20_2", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_PMV_SE2A0_2", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_PMV_WW2A1_2", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_PMV_EE4A3_2", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_PMV_IMUX17_2", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_PMV_SE2A2_2", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_PMV_IMUX0_2", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_PMV_NW4A0_2", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_PMV_WR1END3_2", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_PMV_NW4END2_2", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_PMV_LH11_2", + "INT_INTERFACE_LH11" + ], + [ + "CLK_PMV_IMUX7_2", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_PMV_SE4BEG3_2", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_PMV_EL1BEG2_2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_PMV_EE2BEG0_2", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_PMV_FAN3_2", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_PMV_WW4C1_2", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_PMV_MONITOR_P_2", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_PMV_LH7_2", + "INT_INTERFACE_LH7" + ], + [ + "CLK_PMV_SE2A1_2", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_PMV_SW2A3_2", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_PMV_NE2A0_2", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_PMV_NE4BEG2_2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_PMV_WW2END3_2", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_PMV_IMUX14_2", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_PMV_BYP4_2", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_PMV_IMUX37_2", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_PMV_WW2A2_2", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_PMV_SE4C0_2", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_PMV_CLK0_2", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_PMV_IMUX38_2", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_PMV_IMUX3_2", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_PMV_IMUX46_2", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_PMV_WL1END0_2", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_PMV_SW4END1_2", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_PMV_IMUX18_2", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_PMV_IMUX26_2", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_PMV_IMUX45_2", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_PMV_LH3_2", + "INT_INTERFACE_LH3" + ], + [ + "CLK_PMV_IMUX5_2", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_PMV_IMUX9_2", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_PMV_SE4BEG0_2", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_PMV_NW2A0_2", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_PMV_BYP6_2", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_PMV_SW4END0_2", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_PMV_EE2A3_2", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_PMV_LH10_2", + "INT_INTERFACE_LH10" + ], + [ + "CLK_PMV_SW2A0_2", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_PMV_IMUX30_2", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_PMV_WW4C3_2", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_PMV_IMUX23_2", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_PMV_EE4C3_2", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_PMV_ER1BEG3_2", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_PMV_WW4END1_2", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_PMV_WW2END1_2", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_PMV_LH12_2", + "INT_INTERFACE_LH12" + ], + [ + "CLK_PMV_IMUX15_2", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_PMV_IMUX24_2", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_PMV_NW2A3_2", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_PMV_SW4A2_2", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_PMV_WW2A3_2", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_PMV_WR1END1_2", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_PMV_LH6_2", + "INT_INTERFACE_LH6" + ], + [ + "CLK_PMV_SW4A3_2", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_PMV_NE4C3_2", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_PMV_IMUX19_2", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_PMV_IMUX22_2", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_PMV_MONITOR_N_2", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_PMV_IMUX12_2", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_PMV_IMUX31_2", + "INT_INTERFACE_IMUX31" + ] + ], + "tile_types": [ + "CLK_PMV", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "wire_pairs": [ + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IDELAYCTRL_RDY", + "IOI_IDELAYCTRL_RDY" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_RCLK_DIV_CLR3", + "IOI_RCLK_DIV_CLR3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK_IMUX3", + "IOI_IMUX_RC3" + ], + [ + "HCLK_IOI_I2IOCLK_BOT0", + "LIOI_I2GCLK_BOT1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN1", + "IOI_IDELAYCTRL_OUTN1" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_RCLK_IMUX2", + "IOI_IMUX_RC2" + ], + [ + "HCLK_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "LIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_RCLK_DIV_CLR2", + "IOI_RCLK_DIV_CLR2" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN65", + "IOI_IDELAYCTRL_OUTN65" + ] + ], + "tile_types": [ + "HCLK_IOI3", + "LIOI3" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "CMT_TOP_EE2BEG2_9", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NE4C0_9", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_EE2A0_9", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG3_9", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SE4BEG2_9", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_NE2A2_9", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW2A2_9", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_LH6_9", + "VBRK_LH6" + ], + [ + "CMT_TOP_EE4B1_9", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NW4A1_9", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SW4A2_9", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WR1END2_9", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_LH8_9", + "VBRK_LH8" + ], + [ + "CMT_TOP_EE2A3_9", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4BEG3_9", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WW2END2_9", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2A1_9", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4A0_9", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_NE4C1_9", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NE4C3_9", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_WW2A0_9", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_NW4END1_9", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_WW2END0_9", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW4C2_9", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW4A3_9", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_ER1BEG0_9", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EL1BEG1_9", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG0_9", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_LH3_9", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END2_9", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_LH2_9", + "VBRK_LH2" + ], + [ + "CMT_TOP_NW4A3_9", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW2A2_9", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE4A2_9", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END3_9", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE2A3_9", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_EE4BEG2_9", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_SW4END0_9", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SW4A0_9", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_EE4C1_9", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_NW2A1_9", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4END2_9", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EL1BEG3_9", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_9", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW2A0_9", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE4B0_9", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_EE4C0_9", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE4B3_9", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW4A1_9", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4C1_9", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_LH4_9", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2BEG1_9", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4A0_9", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4BEG0_9", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_9", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2A2_9", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EE4A1_9", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WW4END0_9", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW4B1_9", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4A3_9", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4END3_9", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH11_9", + "VBRK_LH11" + ], + [ + "CMT_TOP_SW4END3_9", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C2_9", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END1_9", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_LH12_9", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C1_9", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE4C3_9", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_SE2A1_9", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE4A0_9", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_EE2BEG3_9", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_WR1END1_9", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NE2A1_9", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE2BEG0_9", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SE2A2_9", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW2END3_9", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_ER1BEG3_9", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NE2A3_9", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW2A3_9", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_9", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH9_9", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4B0_9", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A0_9", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_NE4BEG2_9", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4A2_9", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_WW4C0_9", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SW2A1_9", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_LH5_9", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END0_9", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NE4BEG1_9", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_9", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A2_9", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EE4BEG1_9", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4C0_9", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_WW4END2_9", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_WW4END1_9", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NW2A0_9", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4C2_9", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_WW4B3_9", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WR1END0_9", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW2A3_9", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW2A2_9", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_EE4BEG3_9", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_SE4C2_9", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_SE4BEG1_9", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_9", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_NE2A0_9", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_WW4B2_9", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WL1END2_9", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4BEG0_9", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG2_9", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WW4C3_9", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4A1_9", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_LH1_9", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW4END0_9", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_EE4A3_9", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_LH10_9", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW2END1_9", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WL1END3_9", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_EE2A1_9", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4C3_9", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WR1END3_9", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SW2A3_9", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_LH7_9", + "VBRK_LH7" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "CLK_BUFG_IMUX27_3", + "INT_INTERFACE_IMUX27" + ], + [ + "CLK_HROW_SW4END2_3", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_HROW_CTRL1_3", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_WW4C2_3", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_HROW_EE4A3_3", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B2_3", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CLK_HROW_CLK0_3", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_BUFG_IMUX9_3", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_FAN2_3", + "INT_INTERFACE_FAN2" + ], + [ + "CLK_BUFG_IMUX45_3", + "INT_INTERFACE_IMUX45" + ], + [ + "CLK_HROW_SE4BEG2_3", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_EE4C1_3", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_BUFG_IMUX36_3", + "INT_INTERFACE_IMUX36" + ], + [ + "CLK_HROW_NE2A1_3", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_FAN0_3", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_WW2A3_3", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_FAN4_3", + "INT_INTERFACE_FAN4" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B6_3", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CLK_HROW_EE2BEG3_3", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_WW4A3_3", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_BUFG_IMUX14_3", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_HROW_SE4BEG3_3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_BUFG_IMUX3_3", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_BUFG_IMUX22_3", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_NW2A2_3", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B3_3", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CLK_BUFG_IMUX15_3", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B7_3", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CLK_HROW_WW4END1_3", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_HROW_SW2A1_3", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_SE4C3_3", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_BUFG_IMUX34_3", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_EE4BEG0_3", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_SE4BEG0_3", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_BUFG_IMUX8_3", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_BUFG_IMUX30_3", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_EL1BEG3_3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_HROW_WR1END0_3", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_NW4A1_3", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_WL1END0_3", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_WL1END1_3", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_HROW_SE2A1_3", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_BUFG_IMUX12_3", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_BUFG_IMUX47_3", + "INT_INTERFACE_IMUX47" + ], + [ + "CLK_HROW_NW4END1_3", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_BUFG_IMUX28_3", + "INT_INTERFACE_IMUX28" + ], + [ + "CLK_HROW_SW4END1_3", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_BUFG_IMUX46_3", + "INT_INTERFACE_IMUX46" + ], + [ + "CLK_HROW_NW2A1_3", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_ER1BEG2_3", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_BUFG_IMUX7_3", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_BUFG_IMUX21_3", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_EE2BEG0_3", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_BUFG_IMUX0_3", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_SW4END3_3", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_WW2END0_3", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_NE4C2_3", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_BUFG_IMUX5_3", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_BUFG_IMUX40_3", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_BYP6_3", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_EE2A0_3", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_WL1END3_3", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_WW4B2_3", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_LH9_3", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_BYP4_3", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_WW4A1_3", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_HROW_LH12_3", + "INT_INTERFACE_LH12" + ], + [ + "CLK_BUFG_IMUX23_3", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_SW2A3_3", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_NE2A0_3", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_EE2BEG2_3", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_ER1BEG0_3", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_LH4_3", + "INT_INTERFACE_LH4" + ], + [ + "CLK_HROW_WW2A2_3", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_ER1BEG1_3", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_SE2A3_3", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_HROW_EE4B3_3", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_BUFG_IMUX1_3", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_HROW_WW4END3_3", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_BUFG_IMUX44_3", + "INT_INTERFACE_IMUX44" + ], + [ + "CLK_BUFG_IMUX10_3", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_LH1_3", + "INT_INTERFACE_LH1" + ], + [ + "CLK_HROW_EE2A1_3", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_EE4B2_3", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_BUFG_IMUX37_3", + "INT_INTERFACE_IMUX37" + ], + [ + "CLK_HROW_BYP5_3", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_BYP2_3", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_NW4END2_3", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_WW2END1_3", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_HROW_SE4C1_3", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_BUFG_IMUX11_3", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_HROW_EE2BEG1_3", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_BUFG_IMUX42_3", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_WW4A2_3", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_EE4A0_3", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_EE4C3_3", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_NE4BEG1_3", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_WW2END2_3", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_HROW_WW4C0_3", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_EE2A3_3", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_EL1BEG2_3", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_SW4A2_3", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_WW2A1_3", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_WW4END0_3", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_CTRL0_3", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_SW4A0_3", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_BUFG_IMUX24_3", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_EL1BEG1_3", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_SE2A0_3", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_LH6_3", + "INT_INTERFACE_LH6" + ], + [ + "CLK_HROW_EE4C0_3", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_HROW_EE4B0_3", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_NE4C0_3", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_BUFG_IMUX32_3", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_BYP1_3", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_FAN5_3", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_EE4C2_3", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_EE2A2_3", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_BUFG_IMUX43_3", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_WW4B3_3", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_HROW_LH2_3", + "INT_INTERFACE_LH2" + ], + [ + "CLK_BUFG_IMUX6_3", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_NW2A0_3", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_HROW_BYP7_3", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_SE4C0_3", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_HROW_NE4C1_3", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_HROW_WW2END3_3", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_BUFG_IMUX20_3", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_HROW_SE2A2_3", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_HROW_NE4C3_3", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_HROW_WL1END2_3", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_BUFG_IMUX38_3", + "INT_INTERFACE_IMUX38" + ], + [ + "CLK_HROW_SW4END0_3", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_SW2A2_3", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_WR1END2_3", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_HROW_NE2A3_3", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B1_3", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CLK_HROW_SW4A3_3", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_NW4A0_3", + "INT_INTERFACE_NW4A0" + ], + [ + "CLK_HROW_NW4A2_3", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_HROW_FAN7_3", + "INT_INTERFACE_FAN7" + ], + [ + "CLK_HROW_WW4B0_3", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_BUFG_IMUX33_3", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_MONITOR_N_3", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_BUFG_IMUX13_3", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_BYP0_3", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_CLK1_3", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_BUFG_IMUX25_3", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_HROW_SW2A0_3", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_HROW_EE4A2_3", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_ER1BEG3_3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_LH5_3", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_NW2A3_3", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_NE2A2_3", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_WW2A0_3", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_NE4BEG3_3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B5_3", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CLK_HROW_FAN6_3", + "INT_INTERFACE_FAN6" + ], + [ + "CLK_HROW_FAN1_3", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_BUFG_IMUX39_3", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_BYP3_3", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_WW4END2_3", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_WW4A0_3", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_HROW_SE4BEG1_3", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_HROW_NW4A3_3", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_BUFG_IMUX16_3", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_HROW_EE4BEG2_3", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_BUFG_IMUX19_3", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_EL1BEG0_3", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_MONITOR_P_3", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_HROW_LH10_3", + "INT_INTERFACE_LH10" + ], + [ + "CLK_HROW_FAN3_3", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_BUFG_IMUX17_3", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_WW4B1_3", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_HROW_NW4END0_3", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_LH7_3", + "INT_INTERFACE_LH7" + ], + [ + "CLK_BUFG_IMUX31_3", + "INT_INTERFACE_IMUX31" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B4_3", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CLK_HROW_LH8_3", + "INT_INTERFACE_LH8" + ], + [ + "CLK_HROW_EE4A1_3", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_BUFG_IMUX35_3", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_EE4BEG3_3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_BUFG_LOGIC_OUTS_B0_3", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CLK_BUFG_IMUX29_3", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_SW4A1_3", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_LH11_3", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_WR1END1_3", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_HROW_WW4C3_3", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_NE4BEG2_3", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_LH3_3", + "INT_INTERFACE_LH3" + ], + [ + "CLK_BUFG_IMUX41_3", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_BUFG_IMUX2_3", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_BUFG_IMUX18_3", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_HROW_EE4BEG1_3", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_HROW_EE4B1_3", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_HROW_SE4C2_3", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_BUFG_IMUX26_3", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_BUFG_IMUX4_3", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_HROW_NE4BEG0_3", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_HROW_NW4END3_3", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_WW4C1_3", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_WR1END3_3", + "INT_INTERFACE_WR1END3" + ] + ], + "tile_types": [ + "CLK_BUFG_TOP_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "CLBLM_NE2A2", + "DSP_NE2A2_2" + ], + [ + "CLBLM_WR1END0", + "DSP_WR1END0_2" + ], + [ + "CLBLM_EE2A0", + "DSP_EE2A0_2" + ], + [ + "CLBLM_EE4C1", + "DSP_EE4C1_2" + ], + [ + "CLBLM_EE4B2", + "DSP_EE4B2_2" + ], + [ + "CLBLM_WW4A3", + "DSP_WW4A3_2" + ], + [ + "CLBLM_NE4C0", + "DSP_NE4C0_2" + ], + [ + "CLBLM_SW4A2", + "DSP_SW4A2_2" + ], + [ + "CLBLM_LH1", + "DSP_LH1_2" + ], + [ + "CLBLM_LH4", + "DSP_LH4_2" + ], + [ + "CLBLM_SE4BEG1", + "DSP_SE4BEG1_2" + ], + [ + "CLBLM_MONITOR_N", + "DSP_MONITOR_N_2" + ], + [ + "CLBLM_EE4BEG0", + "DSP_EE4BEG0_2" + ], + [ + "CLBLM_WW4END1", + "DSP_WW4END1_2" + ], + [ + "CLBLM_EE4BEG1", + "DSP_EE4BEG1_2" + ], + [ + "CLBLM_WW4B3", + "DSP_WW4B3_2" + ], + [ + "CLBLM_SE4BEG2", + "DSP_SE4BEG2_2" + ], + [ + "CLBLM_SE4C0", + "DSP_SE4C0_2" + ], + [ + "CLBLM_NE4C1", + "DSP_NE4C1_2" + ], + [ + "CLBLM_SW4A1", + "DSP_SW4A1_2" + ], + [ + "CLBLM_EE2BEG1", + "DSP_EE2BEG1_2" + ], + [ + "CLBLM_EE2A2", + "DSP_EE2A2_2" + ], + [ + "CLBLM_NW4END0", + "DSP_NW4END0_2" + ], + [ + "CLBLM_NE4BEG1", + "DSP_NE4BEG1_2" + ], + [ + "CLBLM_NE4BEG2", + "DSP_NE4BEG2_2" + ], + [ + "CLBLM_LH7", + "DSP_LH7_2" + ], + [ + "CLBLM_ER1BEG0", + "DSP_ER1BEG0_2" + ], + [ + "CLBLM_NE2A1", + "DSP_NE2A1_2" + ], + [ + "CLBLM_ER1BEG3", + "DSP_ER1BEG3_2" + ], + [ + "CLBLM_NW2A2", + "DSP_NW2A2_2" + ], + [ + "CLBLM_NW4A2", + "DSP_NW4A2_2" + ], + [ + "CLBLM_SE4C2", + "DSP_SE4C2_2" + ], + [ + "CLBLM_SW2A1", + "DSP_SW2A1_2" + ], + [ + "CLBLM_SW4END0", + "DSP_SW4END0_2" + ], + [ + "CLBLM_WR1END1", + "DSP_WR1END1_2" + ], + [ + "CLBLM_EE4BEG3", + "DSP_EE4BEG3_2" + ], + [ + "CLBLM_SE2A1", + "DSP_SE2A1_2" + ], + [ + "CLBLM_NE2A3", + "DSP_NE2A3_2" + ], + [ + "CLBLM_LH11", + "DSP_LH11_2" + ], + [ + "CLBLM_EE4A3", + "DSP_EE4A3_2" + ], + [ + "CLBLM_WW2A0", + "DSP_WW2A0_2" + ], + [ + "CLBLM_NW4END1", + "DSP_NW4END1_2" + ], + [ + "CLBLM_WW4A2", + "DSP_WW4A2_2" + ], + [ + "CLBLM_LH6", + "DSP_LH6_2" + ], + [ + "CLBLM_NW4A1", + "DSP_NW4A1_2" + ], + [ + "CLBLM_WL1END2", + "DSP_WL1END2_2" + ], + [ + "CLBLM_WW2A3", + "DSP_WW2A3_2" + ], + [ + "CLBLM_SE2A0", + "DSP_SE2A0_2" + ], + [ + "CLBLM_EE4C3", + "DSP_EE4C3_2" + ], + [ + "CLBLM_NW2A3", + "DSP_NW2A3_2" + ], + [ + "CLBLM_NE2A0", + "DSP_NE2A0_2" + ], + [ + "CLBLM_SW4END3", + "DSP_SW4END3_2" + ], + [ + "CLBLM_LH5", + "DSP_LH5_2" + ], + [ + "CLBLM_EE2A3", + "DSP_EE2A3_2" + ], + [ + "CLBLM_WW4END0", + "DSP_WW4END0_2" + ], + [ + "CLBLM_SW4A0", + "DSP_SW4A0_2" + ], + [ + "CLBLM_EE2BEG2", + "DSP_EE2BEG2_2" + ], + [ + "CLBLM_WW4B0", + "DSP_WW4B0_2" + ], + [ + "CLBLM_LH9", + "DSP_LH9_2" + ], + [ + "CLBLM_EE2BEG0", + "DSP_EE2BEG0_2" + ], + [ + "CLBLM_WW4B1", + "DSP_WW4B1_2" + ], + [ + "CLBLM_NW4END3", + "DSP_NW4END3_2" + ], + [ + "CLBLM_SW2A3", + "DSP_SW2A3_2" + ], + [ + "CLBLM_NE4C2", + "DSP_NE4C2_2" + ], + [ + "CLBLM_EE4A1", + "DSP_EE4A1_2" + ], + [ + "CLBLM_NW2A0", + "DSP_NW2A0_2" + ], + [ + "CLBLM_EE4B1", + "DSP_EE4B1_2" + ], + [ + "CLBLM_WW2END0", + "DSP_WW2END0_2" + ], + [ + "CLBLM_LH2", + "DSP_LH2_2" + ], + [ + "CLBLM_SE4C3", + "DSP_SE4C3_2" + ], + [ + "CLBLM_WW2END1", + "DSP_WW2END1_2" + ], + [ + "CLBLM_EL1BEG0", + "DSP_EL1BEG0_2" + ], + [ + "CLBLM_EL1BEG2", + "DSP_EL1BEG2_2" + ], + [ + "CLBLM_SE4BEG0", + "DSP_SE4BEG0_2" + ], + [ + "CLBLM_NE4BEG0", + "DSP_NE4BEG0_2" + ], + [ + "CLBLM_NE4C3", + "DSP_NE4C3_2" + ], + [ + "CLBLM_EE4B3", + "DSP_EE4B3_2" + ], + [ + "CLBLM_EE4A0", + "DSP_EE4A0_2" + ], + [ + "CLBLM_LH10", + "DSP_LH10_2" + ], + [ + "CLBLM_NW4A3", + "DSP_NW4A3_2" + ], + [ + "CLBLM_EE4C0", + "DSP_EE4C0_2" + ], + [ + "CLBLM_WW4END2", + "DSP_WW4END2_2" + ], + [ + "CLBLM_WW2A1", + "DSP_WW2A1_2" + ], + [ + "CLBLM_WW4A0", + "DSP_WW4A0_2" + ], + [ + "CLBLM_WL1END3", + "DSP_WL1END3_2" + ], + [ + "CLBLM_EE2A1", + "DSP_EE2A1_2" + ], + [ + "CLBLM_LH12", + "DSP_LH12_2" + ], + [ + "CLBLM_SW2A2", + "DSP_SW2A2_2" + ], + [ + "CLBLM_WW4C2", + "DSP_WW4C2_2" + ], + [ + "CLBLM_LH3", + "DSP_LH3_2" + ], + [ + "CLBLM_WW4END3", + "DSP_WW4END3_2" + ], + [ + "CLBLM_WW4C3", + "DSP_WW4C3_2" + ], + [ + "CLBLM_EE4A2", + "DSP_EE4A2_2" + ], + [ + "CLBLM_ER1BEG1", + "DSP_ER1BEG1_2" + ], + [ + "CLBLM_LH8", + "DSP_LH8_2" + ], + [ + "CLBLM_EE4B0", + "DSP_EE4B0_2" + ], + [ + "CLBLM_SW4A3", + "DSP_SW4A3_2" + ], + [ + "CLBLM_WW4C1", + "DSP_WW4C1_2" + ], + [ + "CLBLM_WR1END3", + "DSP_WR1END3_2" + ], + [ + "CLBLM_NE4BEG3", + "DSP_NE4BEG3_2" + ], + [ + "CLBLM_SW4END2", + "DSP_SW4END2_2" + ], + [ + "CLBLM_NW2A1", + "DSP_NW2A1_2" + ], + [ + "CLBLM_WW4B2", + "DSP_WW4B2_2" + ], + [ + "CLBLM_SW2A0", + "DSP_SW2A0_2" + ], + [ + "CLBLM_EL1BEG3", + "DSP_EL1BEG3_2" + ], + [ + "CLBLM_WW2A2", + "DSP_WW2A2_2" + ], + [ + "CLBLM_NW4END2", + "DSP_NW4END2_2" + ], + [ + "CLBLM_WW2END3", + "DSP_WW2END3_2" + ], + [ + "CLBLM_WW4A1", + "DSP_WW4A1_2" + ], + [ + "CLBLM_SE4C1", + "DSP_SE4C1_2" + ], + [ + "CLBLM_ER1BEG2", + "DSP_ER1BEG2_2" + ], + [ + "CLBLM_WW4C0", + "DSP_WW4C0_2" + ], + [ + "CLBLM_MONITOR_P", + "DSP_MONITOR_P_2" + ], + [ + "CLBLM_WR1END2", + "DSP_WR1END2_2" + ], + [ + "CLBLM_EE4C2", + "DSP_EE4C2_2" + ], + [ + "CLBLM_EL1BEG1", + "DSP_EL1BEG1_2" + ], + [ + "CLBLM_SE2A2", + "DSP_SE2A2_2" + ], + [ + "CLBLM_NW4A0", + "DSP_NW4A0_2" + ], + [ + "CLBLM_WL1END1", + "DSP_WL1END1_2" + ], + [ + "CLBLM_SW4END1", + "DSP_SW4END1_2" + ], + [ + "CLBLM_SE4BEG3", + "DSP_SE4BEG3_2" + ], + [ + "CLBLM_EE4BEG2", + "DSP_EE4BEG2_2" + ], + [ + "CLBLM_WL1END0", + "DSP_WL1END0_2" + ], + [ + "CLBLM_WW2END2", + "DSP_WW2END2_2" + ], + [ + "CLBLM_EE2BEG3", + "DSP_EE2BEG3_2" + ], + [ + "CLBLM_SE2A3", + "DSP_SE2A3_2" + ] + ], + "tile_types": [ + "CLBLM_L", + "DSP_R" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX15_8", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX45_8", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX12_8", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B4_8", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B2_8", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_FAN2_8", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_LOGIC_OUTS_B0_8", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_BYP5_8", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX39_8", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX40_8", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_LOGIC_OUTS_B9_8", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX16_8", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX0_8", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX13_8", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX14_8", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX10_8", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_IMUX20_8", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX38_8", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_FAN5_8", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX46_8", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP6_8", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX2_8", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_LOGIC_OUTS_B10_8", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX5_8", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_IMUX19_8", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX41_8", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B15_8", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_LOGIC_OUTS_B7_8", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B20_8", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_FAN6_8", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX23_8", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX44_8", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_LOGIC_OUTS_B6_8", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX28_8", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX22_8", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_IMUX47_8", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX21_8", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX1_8", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX27_8", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_FAN0_8", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX9_8", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_BYP7_8", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B8_8", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_FAN1_8", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_IMUX18_8", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_BYP3_8", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B11_8", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_LOGIC_OUTS_B22_8", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_LOGIC_OUTS_B23_8", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX8_8", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX4_8", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_CLK1_8", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX24_8", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B1_8", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_IMUX7_8", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX31_8", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX6_8", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B18_8", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX32_8", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B16_8", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_FAN7_8", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX30_8", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX34_8", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX26_8", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_LOGIC_OUTS_B21_8", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_CLK0_8", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX17_8", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX35_8", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_LOGIC_OUTS_B13_8", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_BYP4_8", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_LOGIC_OUTS_B19_8", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX11_8", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_BYP0_8", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX36_8", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX25_8", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_LOGIC_OUTS_B3_8", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX29_8", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_CTRL1_8", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX43_8", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_BYP2_8", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX33_8", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_CTRL0_8", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX42_8", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_FAN3_8", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_LOGIC_OUTS_B14_8", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_LOGIC_OUTS_B17_8", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_LOGIC_OUTS_B5_8", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX3_8", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX37_8", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_BYP1_8", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B12_8", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_FAN4_8", + "VBRK_EXT_FAN4" + ] + ], + "tile_types": [ + "GTX_CHANNEL_3", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "CMT_TOP_WW4C0_6", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_NW4END2_6", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW2A3_6", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE4BEG0_6", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_LH12_6", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_6", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A3_6", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_SW4A1_6", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4B0_6", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SW4A3_6", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_NE4BEG2_6", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE4B0_6", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SE4C1_6", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A1_6", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WL1END1_6", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE4BEG1_6", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_SW4END1_6", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_6", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C1_6", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW4A1_6", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_ER1BEG0_6", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_6", + "VBRK_LH1" + ], + [ + "CMT_TOP_EE4BEG2_6", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG2_6", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_SE2A0_6", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WL1END2_6", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A1_6", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WR1END3_6", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NE2A2_6", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_LH4_6", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END1_6", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH8_6", + "VBRK_LH8" + ], + [ + "CMT_TOP_SE4BEG2_6", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4END2_6", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH6_6", + "VBRK_LH6" + ], + [ + "CMT_TOP_LH3_6", + "VBRK_LH3" + ], + [ + "CMT_TOP_NE4C2_6", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NE2A3_6", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE4C3_6", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4A0_6", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C3_6", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_ER1BEG3_6", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EL1BEG2_6", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WR1END2_6", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END0_6", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE4C0_6", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SE4C0_6", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SE2A3_6", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW2END1_6", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH2_6", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW2END3_6", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_NE2A0_6", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NE4C0_6", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WW4C3_6", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END1_6", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4BEG3_6", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2A1_6", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4B3_6", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4B1_6", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_SW2A1_6", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WL1END3_6", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH7_6", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW2A0_6", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_SW4A0_6", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NW2A1_6", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2BEG0_6", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_SW2A2_6", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EE2BEG1_6", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4END3_6", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NW4END3_6", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE4BEG1_6", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_EL1BEG0_6", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_SW4END2_6", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_NW4A3_6", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4BEG0_6", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SW4A2_6", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4C1_6", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2A0_6", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4END0_6", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_ER1BEG2_6", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EE2A3_6", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW2A0_6", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_LH11_6", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE2BEG3_6", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH9_6", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4A3_6", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4A0_6", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE2A0_6", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NW2A2_6", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_6", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SE4C3_6", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4A1_6", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_WR1END0_6", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4C2_6", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EE4C1_6", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EL1BEG3_6", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW4B3_6", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW2END2_6", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A2_6", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4B2_6", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW4A0_6", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_WW2A1_6", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_LH5_6", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4B1_6", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_NE4BEG1_6", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_LH10_6", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE2A2_6", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4A2_6", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG1_6", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE2A1_6", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C2_6", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WL1END0_6", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SE4BEG0_6", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_ER1BEG1_6", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE4A2_6", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4END0_6", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4BEG3_6", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_SW2A3_6", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NW4A2_6", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4END0_6", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2A2_6", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NW2A3_6", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_EE4B2_6", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE4C2_6", + "VBRK_SE4C2" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 3 + ], + "wire_pairs": [ + [ + "CFG_CENTER_LH4_7", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_EE2BEG2_7", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX46_7", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW4C2_7", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WW4A1_7", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_LH11_7", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_CTRL0_7", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX16_7", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX7_7", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_CLK1_7", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_NW2A1_7", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_BYP3_7", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_BYP6_7", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_SE2A3_7", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_WW2END3_7", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_IMUX37_7", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SW4A1_7", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_NW4A0_7", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NW4A1_7", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_LH12_7", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX2_7", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_IMUX40_7", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_NW4A2_7", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_WL1END2_7", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_EE4C0_7", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_IMUX8_7", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_EE2A2_7", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_CTRL1_7", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_7", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_ER1BEG0_7", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_SW2A0_7", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_EE4BEG2_7", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX34_7", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_NE4C2_7", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_NW4END3_7", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_WR1END0_7", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EE4C1_7", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_LH10_7", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_WW4END1_7", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX27_7", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_WW2A2_7", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_WW4B1_7", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_SE2A1_7", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_IMUX39_7", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_WR1END3_7", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX21_7", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_EE4A0_7", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_SW2A1_7", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_EE4BEG0_7", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_EE2BEG1_7", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B8_7", + "VFRAME_LOGIC_OUTS_B8" + ], + [ + "CFG_CENTER_IMUX41_7", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_LH1_7", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_SW2A2_7", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_EE4B0_7", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_EE2BEG0_7", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_NE4BEG2_7", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_FAN5_7", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SE4BEG1_7", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_WW4B2_7", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_7", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_IMUX44_7", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WW4END0_7", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_IMUX22_7", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_SW4A0_7", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_NW4END1_7", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SW4A3_7", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_WW4C3_7", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_SE4BEG0_7", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_SW2A3_7", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_IMUX45_7", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_EE4A1_7", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX1_7", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_NE2A0_7", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_FAN4_7", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_LH5_7", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_SE4BEG3_7", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX47_7", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_FAN1_7", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_NW4A3_7", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SW4END2_7", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_EL1BEG0_7", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_BYP4_7", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WW2END2_7", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_WW4A0_7", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_EE2A0_7", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WW2A1_7", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_7", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_EE4B2_7", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_SE2A0_7", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_LH3_7", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_7", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_7", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_IMUX38_7", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX25_7", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_EE4BEG1_7", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_7", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_IMUX30_7", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_EE4BEG3_7", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_NE4BEG1_7", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_7", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_IMUX42_7", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX4_7", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B9_7", + "VFRAME_LOGIC_OUTS_B9" + ], + [ + "CFG_CENTER_IMUX32_7", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_WL1END1_7", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_NW4END2_7", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_NE4BEG0_7", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX3_7", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_WL1END0_7", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_SE2A2_7", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX28_7", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX10_7", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_BYP0_7", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_LH6_7", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX11_7", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX43_7", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_NE2A3_7", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_EL1BEG3_7", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW4C1_7", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_EE4A2_7", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX31_7", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_NW4END0_7", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_SW4END3_7", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX5_7", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_ER1BEG2_7", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_LH8_7", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_NE4C0_7", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_IMUX15_7", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_IMUX9_7", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_EL1BEG2_7", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX17_7", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_NW2A3_7", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_IMUX12_7", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_FAN6_7", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX23_7", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WL1END3_7", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_NW2A2_7", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW4B0_7", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_CLK0_7", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_WW2A0_7", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_EE4C3_7", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_WW2A3_7", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX18_7", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_EE4B1_7", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_SW4END0_7", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_NE4BEG3_7", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B11_7", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "CFG_CENTER_EE2BEG3_7", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX36_7", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_FAN0_7", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX6_7", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_WW4C0_7", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX19_7", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_WW2END1_7", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_NE4C3_7", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_FAN3_7", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_7", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_SE4C3_7", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_NE4C1_7", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_ER1BEG1_7", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SE4C2_7", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WW4END2_7", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_7", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_WW2END0_7", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_LH7_7", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_BYP2_7", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_BYP7_7", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_SE4C1_7", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_EE4C2_7", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_EE4A3_7", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_SW4A2_7", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NW2A0_7", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_LH9_7", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_7", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_SW4END1_7", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_IMUX33_7", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_WW4A3_7", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_7", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_LH2_7", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_IMUX35_7", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_BYP5_7", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_EE4B3_7", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_IMUX0_7", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW4END3_7", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_EE2A1_7", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX13_7", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_SE4C0_7", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_WW4B3_7", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_WR1END2_7", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_ER1BEG3_7", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_BYP1_7", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_EE2A3_7", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EL1BEG1_7", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_IMUX14_7", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_FAN7_7", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX24_7", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_7", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B10_7", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "CFG_CENTER_SE4BEG2_7", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_WW4A2_7", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_NE2A2_7", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_WR1END1_7", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NE2A1_7", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX29_7", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX20_7", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_IMUX26_7", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_FAN2_7", + "VFRAME_FAN2" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "wire_pairs": [ + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "FAN_BOUNCE4" + ], + [ + "B_TERM_UTURN_INT_SW6B0", + "NW6C3" + ], + [ + "B_TERM_UTURN_INT_SS6B1", + "NN6C2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG0", + "SL1BEG0" + ], + [ + "B_TERM_UTURN_INT_LVB1", + "LVB11" + ], + [ + "B_TERM_UTURN_INT_SS6C2", + "SS6C2" + ], + [ + "B_TERM_UTURN_INT_LV6", + "LV6" + ], + [ + "B_TERM_UTURN_INT_SS6E0", + "SS6E0" + ], + [ + "B_TERM_UTURN_INT_SW6A3", + "NW6B0" + ], + [ + "B_TERM_UTURN_INT_SW6B0", + "SW6B0" + ], + [ + "B_TERM_UTURN_INT_SS6BEG0", + "NN6A3" + ], + [ + "B_TERM_UTURN_INT_LV8", + "LV11" + ], + [ + "B_TERM_UTURN_INT_LV6", + "LV13" + ], + [ + "B_TERM_UTURN_INT_SS6C2", + "NN6D1" + ], + [ + "B_TERM_UTURN_INT_SS6A2", + "NN6B1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG0", + "SS2BEG0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG1", + "NL1END2" + ], + [ + "B_TERM_UTURN_INT_SW6B1", + "NW6C2" + ], + [ + "B_TERM_UTURN_INT_SS6C3", + "SS6C3" + ], + [ + "B_TERM_UTURN_INT_ER1END_N3_3", + "ER1END_N3_3" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "FAN_BOUNCE0" + ], + [ + "B_TERM_UTURN_INT_SS6A3", + "NN6B0" + ], + [ + "B_TERM_UTURN_INT_SE6D1", + "NE6E2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG1", + "NR1END2" + ], + [ + "B_TERM_UTURN_INT_LV3", + "LV3" + ], + [ + "B_TERM_UTURN_INT_SW6C0", + "SW6C0" + ], + [ + "B_TERM_UTURN_INT_SE6A0", + "SE6A0" + ], + [ + "B_TERM_UTURN_INT_LV9", + "LV10" + ], + [ + "B_TERM_UTURN_INT_SW6A0", + "NW6B3" + ], + [ + "B_TERM_UTURN_INT_LV18", + "LV18" + ], + [ + "B_TERM_UTURN_INT_SS6E0", + "NN6END3" + ], + [ + "B_TERM_UTURN_INT_WR1END0", + "WR1END0" + ], + [ + "B_TERM_UTURN_INT_SE6A2", + "SE6A2" + ], + [ + "B_TERM_UTURN_INT_SS6D1", + "SS6D1" + ], + [ + "B_TERM_UTURN_INT_SE6B0", + "SE6B0" + ], + [ + "B_TERM_UTURN_INT_LV7", + "LV7" + ], + [ + "B_TERM_UTURN_INT_LV8", + "LV8" + ], + [ + "B_TERM_UTURN_INT_LV4", + "LV15" + ], + [ + "B_TERM_UTURN_INT_SS6A3", + "SS6A3" + ], + [ + "B_TERM_UTURN_INT_SW6B3", + "NW6C0" + ], + [ + "B_TERM_UTURN_INT_ER1BEG0", + "EL1BEG_N3" + ], + [ + "B_TERM_UTURN_INT_SE6B2", + "SE6B2" + ], + [ + "B_TERM_UTURN_INT_SE6C2", + "SE6C2" + ], + [ + "B_TERM_UTURN_INT_SE6B0", + "NE6C3" + ], + [ + "B_TERM_UTURN_INT_SE6D0", + "NE6E3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG3", + "NN6A0" + ], + [ + "B_TERM_UTURN_INT_SW6D3", + "NW6E0" + ], + [ + "B_TERM_UTURN_INT_LVB1", + "LVB2" + ], + [ + "B_TERM_UTURN_INT_SS6BEG0", + "SS6BEG0" + ], + [ + "B_TERM_UTURN_INT_SE6D2", + "NE6E1" + ], + [ + "B_TERM_UTURN_INT_SS2BEG1", + "NN2A2" + ], + [ + "B_TERM_UTURN_INT_SS6D1", + "NN6E2" + ], + [ + "B_TERM_UTURN_INT_SE6C3", + "SE6C3" + ], + [ + "B_TERM_UTURN_INT_SS2A2", + "NN2END1" + ], + [ + "B_TERM_UTURN_INT_SE6D1", + "SE6D1" + ], + [ + "B_TERM_UTURN_INT_SS6D0", + "NN6E3" + ], + [ + "B_TERM_UTURN_INT_SS6B3", + "NN6C0" + ], + [ + "B_TERM_UTURN_INT_SE6A1", + "NE6B2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG2", + "SL1BEG2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "FAN_BOUNCE6" + ], + [ + "B_TERM_UTURN_INT_LVB3", + "LVB4" + ], + [ + "B_TERM_UTURN_INT_SE6C3", + "NE6D0" + ], + [ + "B_TERM_UTURN_INT_SE6A0", + "NE6B3" + ], + [ + "B_TERM_UTURN_INT_SE6A2", + "NE6B1" + ], + [ + "B_TERM_UTURN_INT_SS6E3", + "SS6E3" + ], + [ + "B_TERM_UTURN_INT_SS2A0", + "SS2A0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG2", + "SS2BEG2" + ], + [ + "B_TERM_UTURN_INT_ER1BEG0", + "ER1BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG3", + "NR1END0" + ], + [ + "B_TERM_UTURN_INT_SW6A3", + "SW6A3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG3", + "NW2A0" + ], + [ + "B_TERM_UTURN_INT_SS6C1", + "NN6D2" + ], + [ + "B_TERM_UTURN_INT_SE6C0", + "NE6D3" + ], + [ + "B_TERM_UTURN_INT_SW6C0", + "NW6D3" + ], + [ + "B_TERM_UTURN_INT_SW6B2", + "SW6B2" + ], + [ + "B_TERM_UTURN_INT_SS6C1", + "SS6C1" + ], + [ + "B_TERM_UTURN_INT_SS6D3", + "SS6D3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG1", + "SE2BEG1" + ], + [ + "B_TERM_UTURN_INT_SS6B1", + "SS6B1" + ], + [ + "B_TERM_UTURN_INT_LV4", + "LV4" + ], + [ + "B_TERM_UTURN_INT_SW6D0", + "NW6E3" + ], + [ + "B_TERM_UTURN_INT_SS6B0", + "SS6B0" + ], + [ + "B_TERM_UTURN_INT_LV5", + "LV14" + ], + [ + "B_TERM_UTURN_INT_SE2BEG1", + "NE2A2" + ], + [ + "B_TERM_UTURN_INT_SW6D2", + "NW6E1" + ], + [ + "B_TERM_UTURN_INT_SS6BEG3", + "SS6BEG3" + ], + [ + "B_TERM_UTURN_INT_SE2BEG0", + "SE2BEG0" + ], + [ + "B_TERM_UTURN_INT_SW6B3", + "SW6B3" + ], + [ + "B_TERM_UTURN_INT_SW6C1", + "SW6C1" + ], + [ + "B_TERM_UTURN_INT_SE6C1", + "NE6D2" + ], + [ + "B_TERM_UTURN_INT_LV3", + "LV16" + ], + [ + "B_TERM_UTURN_INT_SW6A2", + "NW6B1" + ], + [ + "B_TERM_UTURN_INT_SE6D3", + "SE6D3" + ], + [ + "B_TERM_UTURN_INT_SW6D2", + "SW6D2" + ], + [ + "B_TERM_UTURN_INT_SR1BEG2", + "NL1END1" + ], + [ + "B_TERM_UTURN_INT_SS2A3", + "SS2A3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG2", + "SS6BEG2" + ], + [ + "B_TERM_UTURN_INT_SS6E2", + "SS6E2" + ], + [ + "B_TERM_UTURN_INT_SW6C1", + "NW6D2" + ], + [ + "B_TERM_UTURN_INT_SS6E1", + "SS6E1" + ], + [ + "B_TERM_UTURN_INT_SS6E3", + "NN6END0" + ], + [ + "B_TERM_UTURN_INT_LVB0", + "LVB1" + ], + [ + "B_TERM_UTURN_INT_SE6D0", + "SE6D0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG2", + "SR1BEG2" + ], + [ + "B_TERM_UTURN_INT_SS6B2", + "SS6B2" + ], + [ + "B_TERM_UTURN_INT_SS6A1", + "SS6A1" + ], + [ + "B_TERM_UTURN_INT_WR1BEG0", + "WL1BEG_N3" + ], + [ + "B_TERM_UTURN_INT_SW6D1", + "SW6D1" + ], + [ + "B_TERM_UTURN_INT_SS6B0", + "NN6C3" + ], + [ + "B_TERM_UTURN_INT_SS6C0", + "SS6C0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG3", + "SS2BEG3" + ], + [ + "B_TERM_UTURN_INT_SS2BEG1", + "SS2BEG1" + ], + [ + "B_TERM_UTURN_INT_SW6C2", + "SW6C2" + ], + [ + "B_TERM_UTURN_INT_SW2BEG0", + "SW2BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG1", + "SL1BEG1" + ], + [ + "B_TERM_UTURN_INT_LV18", + "LV1" + ], + [ + "B_TERM_UTURN_INT_SS6D3", + "NN6E0" + ], + [ + "B_TERM_UTURN_INT_LVB5", + "LVB7" + ], + [ + "B_TERM_UTURN_INT_SS6A0", + "NN6B3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG1", + "SW2BEG1" + ], + [ + "B_TERM_UTURN_INT_LVB4", + "LVB8" + ], + [ + "B_TERM_UTURN_INT_SW6A1", + "NW6B2" + ], + [ + "B_TERM_UTURN_INT_SS6C3", + "NN6D0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG2", + "NE2A1" + ], + [ + "B_TERM_UTURN_INT_SS6A0", + "SS6A0" + ], + [ + "B_TERM_UTURN_INT_SR1BEG1", + "SR1BEG1" + ], + [ + "B_TERM_UTURN_INT_SW6C2", + "NW6D1" + ], + [ + "B_TERM_UTURN_INT_LV7", + "LV12" + ], + [ + "B_TERM_UTURN_INT_LVB3", + "LVB9" + ], + [ + "B_TERM_UTURN_INT_SW6C3", + "SW6C3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG1", + "SS6BEG1" + ], + [ + "B_TERM_UTURN_INT_SR1BEG3", + "SR1BEG3" + ], + [ + "B_TERM_UTURN_INT_SE6D3", + "NE6E0" + ], + [ + "B_TERM_UTURN_INT_SE6B3", + "SE6B3" + ], + [ + "B_TERM_UTURN_INT_WR1END0", + "WL1END_N1_3" + ], + [ + "B_TERM_UTURN_INT_SW6D0", + "SW6D0" + ], + [ + "B_TERM_UTURN_INT_LV2", + "LV17" + ], + [ + "B_TERM_UTURN_INT_SW2BEG0", + "NW2A3" + ], + [ + "B_TERM_UTURN_INT_SW6A2", + "SW6A2" + ], + [ + "B_TERM_UTURN_INT_LVB0", + "LVB12" + ], + [ + "B_TERM_UTURN_INT_SR1BEG3", + "NL1END0" + ], + [ + "B_TERM_UTURN_INT_LVB2", + "LVB10" + ], + [ + "B_TERM_UTURN_INT_SS6E1", + "NN6END2" + ], + [ + "B_TERM_UTURN_INT_SS2A0", + "NN2END3" + ], + [ + "B_TERM_UTURN_INT_SW6C3", + "NW6D0" + ], + [ + "B_TERM_UTURN_INT_SE6B2", + "NE6C1" + ], + [ + "B_TERM_UTURN_INT_SW2BEG1", + "NW2A2" + ], + [ + "B_TERM_UTURN_INT_SS6C0", + "NN6D3" + ], + [ + "B_TERM_UTURN_INT_SS6A1", + "NN6B2" + ], + [ + "B_TERM_UTURN_INT_SS6A2", + "SS6A2" + ], + [ + "B_TERM_UTURN_INT_SS6E2", + "NN6END1" + ], + [ + "B_TERM_UTURN_INT_SS6D2", + "SS6D2" + ], + [ + "B_TERM_UTURN_INT_SS6B2", + "NN6C1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "BYP_BOUNCE_N3_7" + ], + [ + "B_TERM_UTURN_INT_SW6D1", + "NW6E2" + ], + [ + "B_TERM_UTURN_INT_ER1END_N3_3", + "EL1END0" + ], + [ + "B_TERM_UTURN_INT_SS2A3", + "NN2END0" + ], + [ + "B_TERM_UTURN_INT_LV9", + "LV9" + ], + [ + "B_TERM_UTURN_INT_SS6D2", + "NN6E1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "BYP_BOUNCE_N3_6" + ], + [ + "B_TERM_UTURN_INT_SS2BEG2", + "NN2A1" + ], + [ + "B_TERM_UTURN_INT_SE6B1", + "SE6B1" + ], + [ + "B_TERM_UTURN_INT_SW2BEG3", + "SW2BEG3" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "BYP_BOUNCE_N3_2" + ], + [ + "B_TERM_UTURN_INT_SE6C1", + "SE6C1" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "BYP_BOUNCE_N3_3" + ], + [ + "B_TERM_UTURN_INT_SS6D0", + "SS6D0" + ], + [ + "B_TERM_UTURN_INT_SW2BEG2", + "NW2A1" + ], + [ + "B_TERM_UTURN_INT_LV2", + "LV2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "FAN_BOUNCE2" + ], + [ + "B_TERM_UTURN_INT_SS6BEG2", + "NN6A1" + ], + [ + "B_TERM_UTURN_INT_SS2A1", + "NN2END2" + ], + [ + "B_TERM_UTURN_INT_SE6B3", + "NE6C0" + ], + [ + "B_TERM_UTURN_INT_LV5", + "LV5" + ], + [ + "B_TERM_UTURN_INT_SE2BEG3", + "NE2A0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG3", + "NN2A0" + ], + [ + "B_TERM_UTURN_INT_SW6B2", + "NW6C1" + ], + [ + "B_TERM_UTURN_INT_SW6A0", + "SW6A0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG2", + "NR1END1" + ], + [ + "B_TERM_UTURN_INT_SE2BEG0", + "NE2A3" + ], + [ + "B_TERM_UTURN_INT_SW6B1", + "SW6B1" + ], + [ + "B_TERM_UTURN_INT_SS2A2", + "SS2A2" + ], + [ + "B_TERM_UTURN_INT_SS6B3", + "SS6B3" + ], + [ + "B_TERM_UTURN_INT_SE6D2", + "SE6D2" + ], + [ + "B_TERM_UTURN_INT_LVB2", + "LVB3" + ], + [ + "B_TERM_UTURN_INT_SW6END_N0_3", + "SW6END_N0_3" + ], + [ + "B_TERM_UTURN_INT_SE6A3", + "SE6A3" + ], + [ + "B_TERM_UTURN_INT_SW2BEG2", + "SW2BEG2" + ], + [ + "B_TERM_UTURN_INT_SL1BEG0", + "NR1END3" + ], + [ + "B_TERM_UTURN_INT_SE6C2", + "NE6D1" + ], + [ + "B_TERM_UTURN_INT_WR1BEG0", + "WR1BEG0" + ], + [ + "B_TERM_UTURN_INT_SL1BEG3", + "SL1BEG3" + ], + [ + "B_TERM_UTURN_INT_SE6C0", + "SE6C0" + ], + [ + "B_TERM_UTURN_INT_SS2BEG0", + "NN2A3" + ], + [ + "B_TERM_UTURN_INT_SW6END_N0_3", + "NW6END0" + ], + [ + "B_TERM_UTURN_INT_SE2BEG3", + "SE2BEG3" + ], + [ + "B_TERM_UTURN_INT_SS6BEG1", + "NN6A2" + ], + [ + "B_TERM_UTURN_INT_LVB4", + "LVB5" + ], + [ + "B_TERM_UTURN_INT_SE2BEG2", + "SE2BEG2" + ], + [ + "B_TERM_UTURN_INT_SE6A1", + "SE6A1" + ], + [ + "B_TERM_UTURN_INT_SE6B1", + "NE6C2" + ], + [ + "B_TERM_UTURN_INT_SW6D3", + "SW6D3" + ], + [ + "B_TERM_UTURN_INT_LVB5", + "LVB6" + ], + [ + "B_TERM_UTURN_INT_SE6A3", + "NE6B0" + ], + [ + "B_TERM_UTURN_INT_SW6A1", + "SW6A1" + ], + [ + "B_TERM_UTURN_INT_SS2A1", + "SS2A1" + ] + ], + "tile_types": [ + "B_TERM_INT", + "INT_R" + ] + }, + { + "grid_deltas": [ + -1, + 5 + ], + "wire_pairs": [ + [ + "CMT_TOP_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH6_3", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_LH1_3", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_LH12_3", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_LH7_3", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_3", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH3_3", + "VBRK_LH3" + ], + [ + "CMT_TOP_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_MONITOR_P_3", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_LH2_3", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_MONITOR_N_3", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH9_3", + "VBRK_LH9" + ], + [ + "CMT_TOP_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH5_3", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH11_3", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_LH10_3", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH8_3", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EL1BEG1_3", + "VBRK_EL1BEG1" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B11_6", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_LOGIC_OUTS_B2_6", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX5_6", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_CLK1_6", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_IMUX6_6", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX3_6", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_LOGIC_OUTS_B20_6", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX22_6", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B0_6", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX21_6", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_CLK0_6", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_LOGIC_OUTS_B14_6", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX24_6", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX39_6", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B9_6", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_LOGIC_OUTS_B5_6", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX46_6", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_BYP3_6", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_FAN1_6", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_LOGIC_OUTS_B3_6", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX30_6", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_FAN4_6", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_LOGIC_OUTS_B10_6", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX42_6", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_LOGIC_OUTS_B6_6", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_IMUX28_6", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX8_6", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX45_6", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX10_6", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B16_6", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX36_6", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX44_6", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_IMUX33_6", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_BYP7_6", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX15_6", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX41_6", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_IMUX25_6", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_CTRL1_6", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_LOGIC_OUTS_B19_6", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_IMUX12_6", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_LOGIC_OUTS_B22_6", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX19_6", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_BYP6_6", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX40_6", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX32_6", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_FAN0_6", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX27_6", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX37_6", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX0_6", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX35_6", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_BYP2_6", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_BYP0_6", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX31_6", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_IMUX13_6", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_FAN2_6", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_IMUX2_6", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_LOGIC_OUTS_B12_6", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_BYP5_6", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_CTRL0_6", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_LOGIC_OUTS_B17_6", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX9_6", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX29_6", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX16_6", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_LOGIC_OUTS_B1_6", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_FAN5_6", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX18_6", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX43_6", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX4_6", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_LOGIC_OUTS_B8_6", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_LOGIC_OUTS_B15_6", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_LOGIC_OUTS_B13_6", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_IMUX38_6", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_IMUX7_6", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_BYP1_6", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B23_6", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_IMUX23_6", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_FAN7_6", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B7_6", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B4_6", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_IMUX26_6", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX20_6", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN3_6", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX34_6", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX47_6", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_BYP4_6", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX11_6", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_FAN6_6", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_IMUX14_6", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX1_6", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX17_6", + "VBRK_EXT_IMUX17" + ] + ], + "tile_types": [ + "GTX_CHANNEL_0", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 5, + -5 + ], + "wire_pairs": [ + [ + "PCIE_SW4END1_15", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_SE4BEG1_15", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_EE4A0_15", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_NE4C3_15", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_NE2A2_15", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_IMUX0_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_IMUX14_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_IMUX44_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_ER1BEG0_15", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_SW4END3_15", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_IMUX8_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_WW4B2_15", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_LH9_15", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_BYP2_L_15", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_BYP4_L_15", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_WW4B3_15", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_WW4END2_15", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_NE4BEG3_15", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_IMUX42_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_IMUX46_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_IMUX20_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_WW2END1_15", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_SW2A0_15", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_EE4A3_15", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_IMUX36_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_NW4A2_15", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_NW4END0_15", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_WW4C2_15", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_NE4BEG1_15", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX43_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_IMUX25_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_BYP7_L_15", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_WW2END2_15", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_ER1BEG2_15", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_SE4C0_15", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_SE4C1_15", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_SW2A3_15", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_WW2A3_15", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_NW4A0_15", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_EE2A0_15", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_IMUX22_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_EE2BEG2_15", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_IMUX10_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_IMUX39_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_IMUX11_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_SE2A2_15", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_NW2A1_15", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_IMUX29_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_IMUX21_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_IMUX28_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_BYP5_L_15", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_IMUX34_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_IMUX30_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_WW4C3_15", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_CLK0_L_15", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_BYP6_L_15", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_SE4BEG2_15", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_EE4BEG3_15", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_WR1END3_15", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_WW4B0_15", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_NW2A3_15", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_SW4END0_15", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_EE4C3_15", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_FAN3_L_15", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX1_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_WW2A2_15", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_IMUX26_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_IMUX3_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_WW4C1_15", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_EL1BEG3_15", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_EE4BEG0_15", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX31_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_IMUX35_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_NW2A0_15", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_NW4A3_15", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_WW4END3_15", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_SE2A3_15", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_EE4B0_15", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX6_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_SW4A0_15", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_WW2END0_15", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_WW4A1_15", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_LH2_15", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_NE4C0_15", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_IMUX40_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_FAN1_L_15", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_WR1END2_15", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_NW4END3_15", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_WW2END3_15", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_EE4A2_15", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_WW4END0_15", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_LH10_15", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_WL1END3_15", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_WW2A1_15", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_EE4B3_15", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_EL1BEG2_15", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_WL1END2_15", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_IMUX17_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_LH4_15", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_IMUX32_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_WL1END1_15", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_WW4END1_15", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_EE4C1_15", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_NW4END1_15", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_IMUX37_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_FAN7_L_15", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_LH11_15", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_BYP3_L_15", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_WW2A0_15", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_LH6_15", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_CLK1_L_15", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_SW4END2_15", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_EE2A2_15", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_CTRL0_L_15", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_EE4BEG1_15", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_SE4BEG3_15", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_NE2A0_15", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_EE4BEG2_15", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_SE2A0_15", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_WR1END1_15", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_IMUX41_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_IMUX24_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_EE4A1_15", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_IMUX4_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_EE4C2_15", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_NE2A1_15", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_EE4B1_15", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_FAN5_L_15", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_NE4BEG2_15", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_FAN6_L_15", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_ER1BEG3_15", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_ER1BEG1_15", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_FAN2_L_15", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_IMUX27_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_WL1END0_15", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_IMUX7_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_LH8_15", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_LH1_15", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_WW4A2_15", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_SW4A2_15", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_SW2A2_15", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_EE2BEG3_15", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_EL1BEG1_15", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_LH3_15", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_IMUX19_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_WW4A0_15", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_FAN4_L_15", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_EE2BEG1_15", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_NE4C1_15", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_EE2A3_15", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_SE4BEG0_15", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_IMUX12_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_LH12_15", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_EE4B2_15", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_BYP1_L_15", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_WW4C0_15", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_FAN0_L_15", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_EE2A1_15", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_LH5_15", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_SW2A1_15", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_IMUX16_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_IMUX23_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_NW4A1_15", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_NE2A3_15", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_IMUX18_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_LH7_15", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_SW4A1_15", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_WW4A3_15", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_IMUX9_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_EE2BEG0_15", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_NW4END2_15", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_IMUX47_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_IMUX2_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_SW4A3_15", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_SE2A1_15", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_NW2A2_15", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_15", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_SE4C2_15", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_WW4B1_15", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_MONITOR_N_15", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_EL1BEG0_15", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_WR1END0_15", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_EE4C0_15", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_NE4BEG0_15", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_IMUX45_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_NE4C2_15", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_IMUX13_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_IMUX15_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_MONITOR_P_15", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_CTRL1_L_15", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_IMUX38_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_SE4C3_15", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_BYP0_L_15", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_IMUX5_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_IMUX33_L_15", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_IMUX18_7", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_SE4C0_7", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_L_IMUX45_7", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_SW4A3_7", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_EE4C0_7", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_WW4A2_7", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_7", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "CMT_FIFO_SW2A1_7", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_L_IMUX17_7", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_SW2A2_7", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_SE4BEG3_7", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_L_IMUX13_7", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_WL1END0_7", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_EE2BEG3_7", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_7", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "CMT_FIFO_L_BYP3_7", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_7", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "CMT_FIFO_NE4C2_7", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_NW2A3_7", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_L_IMUX34_7", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_L_FAN4_7", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_WR1END0_7", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_SE4BEG1_7", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX23_7", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_7", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_7", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "CMT_FIFO_WL1END1_7", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_WL1END2_7", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_SE4BEG0_7", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_WW2A3_7", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_LH3_7", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_EE2A1_7", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_7", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "CMT_FIFO_L_IMUX29_7", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_WW4B1_7", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_L_IMUX39_7", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_WW4A0_7", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_7", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "CMT_FIFO_NE4C1_7", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_EE4BEG0_7", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_L_FAN1_7", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_LH8_7", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_BYP2_7", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_NW4A3_7", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_NW4A1_7", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_L_FAN0_7", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_7", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "CMT_FIFO_LH7_7", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_WW4C2_7", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_EE4A0_7", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_SW2A3_7", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_L_BYP5_7", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_EE2A2_7", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_L_IMUX8_7", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_L_BYP7_7", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_EE4A1_7", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_SW4A2_7", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_SE4C3_7", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_EL1BEG1_7", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_L_IMUX3_7", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_NE2A3_7", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_NE2A1_7", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_L_IMUX26_7", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_WW4END2_7", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_EE4C3_7", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_EE4BEG1_7", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_7", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "CMT_FIFO_L_IMUX33_7", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_EL1BEG3_7", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_SE4C1_7", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_NW4A0_7", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_7", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "CMT_FIFO_EE4BEG2_7", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_WW4END0_7", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_EE4B2_7", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_L_IMUX42_7", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_CTRL0_7", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_L_IMUX1_7", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_7", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "CMT_FIFO_EE4A3_7", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_IMUX12_7", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_EE4BEG3_7", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_WR1END3_7", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_WW4C1_7", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_SE2A0_7", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_WW4B2_7", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_EE4B3_7", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_EL1BEG2_7", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_WW4C3_7", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_L_FAN7_7", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_L_CTRL1_7", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_NW4END1_7", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_L_IMUX35_7", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_WW4END3_7", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_EE4B1_7", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_NW2A1_7", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_WR1END1_7", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_SE2A1_7", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_WW4B0_7", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_WW4C0_7", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_WL1END3_7", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_7", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_7", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "CMT_FIFO_L_IMUX47_7", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_7", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "CMT_FIFO_L_IMUX7_7", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_L_IMUX5_7", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_L_IMUX40_7", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_L_IMUX21_7", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_WW4A3_7", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_SW4A1_7", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_NW2A2_7", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_L_IMUX37_7", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_EE4C1_7", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_EE4C2_7", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_SE4BEG2_7", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_LH12_7", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_7", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "CMT_FIFO_NW4END0_7", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_WW4END1_7", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_L_IMUX25_7", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_L_IMUX22_7", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_L_IMUX15_7", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_IMUX46_7", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_7", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "CMT_FIFO_NE4BEG2_7", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_NW2A0_7", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_L_IMUX19_7", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_L_IMUX0_7", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_L_BYP0_7", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_LH5_7", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_SW4END2_7", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_WW2A1_7", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90" + ], + [ + "CMT_FIFO_L_FAN6_7", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_NW4A2_7", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_L_FAN5_7", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_L_IMUX41_7", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_EE2A0_7", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_ER1BEG3_7", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_LH9_7", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_L_BYP6_7", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_ER1BEG2_7", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_L_IMUX4_7", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_LH6_7", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_WW2A0_7", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_WR1END2_7", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_7", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "CMT_FIFO_EE2BEG0_7", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_IMUX28_7", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_LH4_7", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_L_IMUX44_7", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_IMUX38_7", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_L_IMUX30_7", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_SW4END1_7", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_SW2A0_7", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_NE4BEG1_7", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_ER1BEG0_7", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_ER1BEG1_7", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_IMUX32_7", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_L_FAN3_7", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_L_CLK1_7", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_WW2END1_7", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_7", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "CMT_FIFO_L_IMUX20_7", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_SE2A3_7", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_EE2BEG1_7", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_SW4END0_7", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_LH2_7", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_SW4A0_7", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_WW4B3_7", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_EE4B0_7", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_7", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_7", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "CMT_FIFO_L_BYP1_7", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_EE2BEG2_7", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_WW2END3_7", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_L_IMUX6_7", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_SW4END3_7", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_L_IMUX31_7", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_WW2A2_7", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_L_IMUX36_7", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_LH11_7", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_L_FAN2_7", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_7", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_7", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "CMT_FIFO_NE2A0_7", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_IMUX14_7", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_NE4C0_7", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_L_IMUX43_7", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_L_CLK0_7", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_SE2A2_7", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_L_IMUX10_7", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_L_BYP4_7", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_WW2END2_7", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_NE4C3_7", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_L_IMUX27_7", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_L_IMUX24_7", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_EE4A2_7", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_SE4C2_7", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_7", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "CMT_FIFO_WW2END0_7", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_L_IMUX9_7", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX11_7", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_7", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "CMT_FIFO_L_IMUX2_7", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_LH1_7", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_NW4END3_7", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_WW4A1_7", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_NW4END2_7", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_EL1BEG0_7", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_NE4BEG3_7", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_NE4BEG0_7", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX16_7", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_LH10_7", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_EE2A3_7", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_NE2A2_7", + "INT_INTERFACE_NE2A2" + ] + ], + "tile_types": [ + "CMT_FIFO_L", + "INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + 8 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_8" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_8" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_8" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_8" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_8" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_8" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_8" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_8" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_8" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_8" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_8" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_8" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_8" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_8" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_8" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_8" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_8" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_8" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_8" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_8" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_8" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_8" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_8" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_8" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_8" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_8" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_8" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_8" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_8" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_8" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_8" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_8" + ], + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_8" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_8" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_8" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_8" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_8" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_8" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_8" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_8" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_8" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_8" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_8" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_8" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_8" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_8" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_8" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_8" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_8" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_8" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_8" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_8" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_8" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_8" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_8" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_8" + ], + [ + "INT_FEEDTHRU_2_MONITOR_N", + "MONITOR_HORIZ_VAUXN1" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_8" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_8" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_8" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_8" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_8" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_8" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_8" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_8" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_8" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_8" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_8" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_8" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_8" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_8" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_8" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_8" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_8" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_8" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_8" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_8" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_8" + ], + [ + "INT_FEEDTHRU_2_MONITOR_P", + "MONITOR_HORIZ_VAUXP1" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_8" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_8" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_8" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_8" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_8" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_8" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_8" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_8" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_8" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_8" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_8" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_8" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_8" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_8" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_8" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_8" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_8" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_8" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_8" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_8" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_8" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_8" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_8" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_8" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_8" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_8" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_8" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_8" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_8" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_8" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_8" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_8" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_8" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_8" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_8" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_8" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_8" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_8" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_8" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_8" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_8" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_8" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_8" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_8" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_8" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_8" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_8" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_MID_FUJI2" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "R_TERM_INT_GTX_IMUX38", + "VBRK_EXT_IMUX38" + ], + [ + "R_TERM_INT_GTX_BYP1", + "VBRK_EXT_BYP1" + ], + [ + "R_TERM_INT_GTX_IMUX4", + "VBRK_EXT_IMUX4" + ], + [ + "R_TERM_INT_GTX_IMUX26", + "VBRK_EXT_IMUX26" + ], + [ + "R_TERM_INT_GTX_IMUX22", + "VBRK_EXT_IMUX22" + ], + [ + "R_TERM_INT_GTX_FAN3", + "VBRK_EXT_FAN3" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B20", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "R_TERM_INT_GTX_IMUX18", + "VBRK_EXT_IMUX18" + ], + [ + "R_TERM_INT_GTX_IMUX2", + "VBRK_EXT_IMUX2" + ], + [ + "R_TERM_INT_GTX_IMUX43", + "VBRK_EXT_IMUX43" + ], + [ + "R_TERM_INT_GTX_CTRL1", + "VBRK_EXT_CTRL1" + ], + [ + "R_TERM_INT_GTX_IMUX12", + "VBRK_EXT_IMUX12" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B21", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "R_TERM_INT_GTX_IMUX24", + "VBRK_EXT_IMUX24" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B11", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "R_TERM_INT_GTX_FAN1", + "VBRK_EXT_FAN1" + ], + [ + "R_TERM_INT_GTX_IMUX23", + "VBRK_EXT_IMUX23" + ], + [ + "R_TERM_INT_GTX_IMUX27", + "VBRK_EXT_IMUX27" + ], + [ + "R_TERM_INT_GTX_FAN7", + "VBRK_EXT_FAN7" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B7", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B18", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "R_TERM_INT_GTX_IMUX9", + "VBRK_EXT_IMUX9" + ], + [ + "R_TERM_INT_GTX_BYP4", + "VBRK_EXT_BYP4" + ], + [ + "R_TERM_INT_GTX_IMUX15", + "VBRK_EXT_IMUX15" + ], + [ + "R_TERM_INT_GTX_BYP3", + "VBRK_EXT_BYP3" + ], + [ + "R_TERM_INT_GTX_IMUX20", + "VBRK_EXT_IMUX20" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B19", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "R_TERM_INT_GTX_IMUX47", + "VBRK_EXT_IMUX47" + ], + [ + "R_TERM_INT_GTX_IMUX35", + "VBRK_EXT_IMUX35" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B5", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B9", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B23", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "R_TERM_INT_GTX_FAN5", + "VBRK_EXT_FAN5" + ], + [ + "R_TERM_INT_GTX_FAN6", + "VBRK_EXT_FAN6" + ], + [ + "R_TERM_INT_GTX_BYP0", + "VBRK_EXT_BYP0" + ], + [ + "R_TERM_INT_GTX_IMUX34", + "VBRK_EXT_IMUX34" + ], + [ + "R_TERM_INT_GTX_IMUX31", + "VBRK_EXT_IMUX31" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B0", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "R_TERM_INT_GTX_IMUX39", + "VBRK_EXT_IMUX39" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B6", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "R_TERM_INT_GTX_IMUX10", + "VBRK_EXT_IMUX10" + ], + [ + "R_TERM_INT_GTX_IMUX13", + "VBRK_EXT_IMUX13" + ], + [ + "R_TERM_INT_GTX_IMUX25", + "VBRK_EXT_IMUX25" + ], + [ + "R_TERM_INT_GTX_IMUX5", + "VBRK_EXT_IMUX5" + ], + [ + "R_TERM_INT_GTX_IMUX6", + "VBRK_EXT_IMUX6" + ], + [ + "R_TERM_INT_GTX_IMUX14", + "VBRK_EXT_IMUX14" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B8", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "R_TERM_INT_GTX_FAN0", + "VBRK_EXT_FAN0" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B17", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B10", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "R_TERM_INT_GTX_FAN2", + "VBRK_EXT_FAN2" + ], + [ + "R_TERM_INT_GTX_BYP7", + "VBRK_EXT_BYP7" + ], + [ + "R_TERM_INT_GTX_IMUX3", + "VBRK_EXT_IMUX3" + ], + [ + "R_TERM_INT_GTX_IMUX0", + "VBRK_EXT_IMUX0" + ], + [ + "R_TERM_INT_GTX_FAN4", + "VBRK_EXT_FAN4" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B22", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "R_TERM_INT_GTX_IMUX45", + "VBRK_EXT_IMUX45" + ], + [ + "R_TERM_INT_GTX_IMUX28", + "VBRK_EXT_IMUX28" + ], + [ + "R_TERM_INT_GTX_IMUX30", + "VBRK_EXT_IMUX30" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B16", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "R_TERM_INT_GTX_IMUX1", + "VBRK_EXT_IMUX1" + ], + [ + "R_TERM_INT_GTX_BYP2", + "VBRK_EXT_BYP2" + ], + [ + "R_TERM_INT_GTX_BYP5", + "VBRK_EXT_BYP5" + ], + [ + "R_TERM_INT_GTX_CLK0", + "VBRK_EXT_CLK0" + ], + [ + "R_TERM_INT_GTX_IMUX42", + "VBRK_EXT_IMUX42" + ], + [ + "R_TERM_INT_GTX_IMUX33", + "VBRK_EXT_IMUX33" + ], + [ + "R_TERM_INT_GTX_IMUX41", + "VBRK_EXT_IMUX41" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B12", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "R_TERM_INT_GTX_CTRL0", + "VBRK_EXT_CTRL0" + ], + [ + "R_TERM_INT_GTX_CLK1", + "VBRK_EXT_CLK1" + ], + [ + "R_TERM_INT_GTX_IMUX40", + "VBRK_EXT_IMUX40" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B2", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "R_TERM_INT_GTX_IMUX8", + "VBRK_EXT_IMUX8" + ], + [ + "R_TERM_INT_GTX_IMUX32", + "VBRK_EXT_IMUX32" + ], + [ + "R_TERM_INT_GTX_IMUX17", + "VBRK_EXT_IMUX17" + ], + [ + "R_TERM_INT_GTX_IMUX16", + "VBRK_EXT_IMUX16" + ], + [ + "R_TERM_INT_GTX_IMUX36", + "VBRK_EXT_IMUX36" + ], + [ + "R_TERM_INT_GTX_IMUX11", + "VBRK_EXT_IMUX11" + ], + [ + "R_TERM_INT_GTX_IMUX37", + "VBRK_EXT_IMUX37" + ], + [ + "R_TERM_INT_GTX_IMUX7", + "VBRK_EXT_IMUX7" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B15", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "R_TERM_INT_GTX_IMUX21", + "VBRK_EXT_IMUX21" + ], + [ + "R_TERM_INT_GTX_IMUX19", + "VBRK_EXT_IMUX19" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B1", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "R_TERM_INT_GTX_BYP6", + "VBRK_EXT_BYP6" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B3", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "R_TERM_INT_GTX_IMUX44", + "VBRK_EXT_IMUX44" + ], + [ + "R_TERM_INT_GTX_IMUX29", + "VBRK_EXT_IMUX29" + ], + [ + "R_TERM_INT_GTX_IMUX46", + "VBRK_EXT_IMUX46" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B13", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B4", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B14", + "VBRK_EXT_LOGIC_OUTS_B14" + ] + ], + "tile_types": [ + "R_TERM_INT_GTX", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_IMUX19", + "TERM_INT_IMUX19" + ], + [ + "INT_INTERFACE_FAN3", + "TERM_INT_FAN3" + ], + [ + "INT_INTERFACE_EL1BEG1", + "L_TERM_INT_WL1BEG1" + ], + [ + "INT_INTERFACE_WW4END3", + "L_TERM_INT_WW4C3" + ], + [ + "INT_INTERFACE_LH9", + "L_TERM_INT_LH3" + ], + [ + "INT_INTERFACE_NE4C2", + "L_TERM_INT_NW4C2" + ], + [ + "INT_INTERFACE_CLK0", + "TERM_INT_CLK0" + ], + [ + "INT_INTERFACE_NE4C3", + "L_TERM_INT_NW4C3" + ], + [ + "INT_INTERFACE_IMUX38", + "TERM_INT_IMUX38" + ], + [ + "INT_INTERFACE_NW4END3", + "L_TERM_INT_NW4C3" + ], + [ + "INT_INTERFACE_SW4A2", + "L_TERM_INT_SW4BEG2" + ], + [ + "INT_INTERFACE_WW4A2", + "L_TERM_INT_WW4BEG2" + ], + [ + "INT_INTERFACE_EE4B0", + "L_TERM_INT_WW4B0" + ], + [ + "INT_INTERFACE_FAN1", + "TERM_INT_FAN1" + ], + [ + "INT_INTERFACE_IMUX12", + "TERM_INT_IMUX12" + ], + [ + "INT_INTERFACE_WW2A1", + "L_TERM_INT_WW2BEG1" + ], + [ + "INT_INTERFACE_ER1BEG3", + "L_TERM_INT_WL1BEG3" + ], + [ + "INT_INTERFACE_ER1BEG2", + "L_TERM_INT_WR1BEG3" + ], + [ + "INT_INTERFACE_EE4C0", + "L_TERM_INT_WW4C0" + ], + [ + "INT_INTERFACE_IMUX3", + "TERM_INT_IMUX3" + ], + [ + "INT_INTERFACE_EL1BEG0", + "L_TERM_INT_WL1BEG0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "TERM_INT_LOGIC_OUTS_L_B7" + ], + [ + "INT_INTERFACE_SW2A3", + "L_TERM_INT_SW2BEG3" + ], + [ + "INT_INTERFACE_WW4B2", + "L_TERM_INT_WW4A2" + ], + [ + "INT_INTERFACE_SE2A1", + "L_TERM_INT_SW2BEG1" + ], + [ + "INT_INTERFACE_EE4BEG2", + "L_TERM_INT_WW4BEG2" + ], + [ + "INT_INTERFACE_EE4A1", + "L_TERM_INT_WW4A1" + ], + [ + "INT_INTERFACE_EE4A0", + "L_TERM_INT_WW4A0" + ], + [ + "INT_INTERFACE_BYP7", + "TERM_INT_BYP7" + ], + [ + "INT_INTERFACE_IMUX28", + "TERM_INT_IMUX28" + ], + [ + "INT_INTERFACE_NW4END2", + "L_TERM_INT_NW4C2" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "L_TERM_INT_PHASER_TO_IO_OCLK" + ], + [ + "INT_INTERFACE_SE4BEG2", + "L_TERM_INT_SW4BEG2" + ], + [ + "INT_INTERFACE_WR1END0", + "L_TERM_INT_WR1BEG0" + ], + [ + "INT_INTERFACE_LH12", + "L_TERM_INT_LH0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "TERM_INT_LOGIC_OUTS_L_B13" + ], + [ + "INT_INTERFACE_IMUX23", + "TERM_INT_IMUX23" + ], + [ + "INT_INTERFACE_LH10", + "L_TERM_INT_LH2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "TERM_INT_LOGIC_OUTS_L_B10" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "INT_INTERFACE_IMUX7", + "TERM_INT_IMUX7" + ], + [ + "INT_INTERFACE_SW4A1", + "L_TERM_INT_SW4BEG1" + ], + [ + "INT_INTERFACE_WL1END0", + "L_TERM_INT_WL1BEG0" + ], + [ + "INT_INTERFACE_LH7", + "L_TERM_INT_LH5" + ], + [ + "INT_INTERFACE_IMUX13", + "TERM_INT_IMUX13" + ], + [ + "INT_INTERFACE_IMUX5", + "TERM_INT_IMUX5" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "INT_INTERFACE_IMUX21", + "TERM_INT_IMUX21" + ], + [ + "INT_INTERFACE_WW4A1", + "L_TERM_INT_WW4BEG1" + ], + [ + "INT_INTERFACE_EE4BEG0", + "L_TERM_INT_WW4BEG0" + ], + [ + "INT_INTERFACE_BYP2", + "TERM_INT_BYP2" + ], + [ + "INT_INTERFACE_BYP6", + "TERM_INT_BYP6" + ], + [ + "INT_INTERFACE_WW4C2", + "L_TERM_INT_WW4B2" + ], + [ + "INT_INTERFACE_BYP3", + "TERM_INT_BYP3" + ], + [ + "INT_INTERFACE_IMUX37", + "TERM_INT_IMUX37" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "INT_INTERFACE_IMUX25", + "TERM_INT_IMUX25" + ], + [ + "INT_INTERFACE_WW4C0", + "L_TERM_INT_WW4B0" + ], + [ + "INT_INTERFACE_WL1END1", + "L_TERM_INT_WL1BEG1" + ], + [ + "INT_INTERFACE_EL1BEG3", + "L_TERM_INT_WR1BEG2" + ], + [ + "INT_INTERFACE_SE4C1", + "L_TERM_INT_SW4C1" + ], + [ + "INT_INTERFACE_LH4", + "L_TERM_INT_LH3" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "INT_INTERFACE_IMUX20", + "TERM_INT_IMUX20" + ], + [ + "INT_INTERFACE_EE4BEG3", + "L_TERM_INT_WW4BEG3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "INT_INTERFACE_EL1BEG2", + "L_TERM_INT_WL1BEG2" + ], + [ + "INT_INTERFACE_IMUX0", + "TERM_INT_IMUX0" + ], + [ + "INT_INTERFACE_IMUX8", + "TERM_INT_IMUX8" + ], + [ + "INT_INTERFACE_IMUX4", + "TERM_INT_IMUX4" + ], + [ + "INT_INTERFACE_EE2A3", + "L_TERM_INT_WW2A3" + ], + [ + "INT_INTERFACE_WL1END3", + "L_TERM_INT_WR1BEG2" + ], + [ + "INT_INTERFACE_EE4B3", + "L_TERM_INT_WW4B3" + ], + [ + "INT_INTERFACE_BYP5", + "TERM_INT_BYP5" + ], + [ + "INT_INTERFACE_SE4BEG1", + "L_TERM_INT_SW4BEG1" + ], + [ + "INT_INTERFACE_SE2A3", + "L_TERM_INT_SW2BEG3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "INT_INTERFACE_WW4B0", + "L_TERM_INT_WW4A0" + ], + [ + "INT_INTERFACE_EE4C3", + "L_TERM_INT_WW4C3" + ], + [ + "INT_INTERFACE_SW4END2", + "L_TERM_INT_SW4C2" + ], + [ + "INT_INTERFACE_NW4A0", + "L_TERM_INT_NW4BEG0" + ], + [ + "INT_INTERFACE_IMUX45", + "TERM_INT_IMUX45" + ], + [ + "INT_INTERFACE_IMUX32", + "TERM_INT_IMUX32" + ], + [ + "INT_INTERFACE_FAN2", + "TERM_INT_FAN2" + ], + [ + "INT_INTERFACE_SW4A3", + "L_TERM_INT_SW4BEG3" + ], + [ + "INT_INTERFACE_WR1END3", + "L_TERM_INT_WL1BEG3" + ], + [ + "INT_INTERFACE_IMUX36", + "TERM_INT_IMUX36" + ], + [ + "INT_INTERFACE_NW2A0", + "L_TERM_INT_NW2BEG0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "TERM_INT_LOGIC_OUTS_L_B22" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "TERM_INT_LOGIC_OUTS_L_B18" + ], + [ + "INT_INTERFACE_IMUX31", + "TERM_INT_IMUX31" + ], + [ + "INT_INTERFACE_WW4END2", + "L_TERM_INT_WW4C2" + ], + [ + "INT_INTERFACE_IMUX14", + "TERM_INT_IMUX14" + ], + [ + "INT_INTERFACE_WL1END2", + "L_TERM_INT_WL1BEG2" + ], + [ + "INT_INTERFACE_BLOCK_OUTS_L_B0", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "INT_INTERFACE_WW2A2", + "L_TERM_INT_WW2BEG2" + ], + [ + "INT_INTERFACE_WW4C1", + "L_TERM_INT_WW4B1" + ], + [ + "INT_INTERFACE_IMUX10", + "TERM_INT_IMUX10" + ], + [ + "INT_INTERFACE_NE2A0", + "L_TERM_INT_NW2BEG0" + ], + [ + "INT_INTERFACE_NE4C0", + "L_TERM_INT_NW4C0" + ], + [ + "INT_INTERFACE_NW4A1", + "L_TERM_INT_NW4BEG1" + ], + [ + "INT_INTERFACE_FAN0", + "TERM_INT_FAN0" + ], + [ + "INT_INTERFACE_IMUX16", + "TERM_INT_IMUX16" + ], + [ + "INT_INTERFACE_EE2BEG0", + "L_TERM_INT_WW2BEG0" + ], + [ + "INT_INTERFACE_EE2BEG3", + "L_TERM_INT_WW2BEG3" + ], + [ + "INT_INTERFACE_NW2A1", + "L_TERM_INT_NW2BEG1" + ], + [ + "INT_INTERFACE_IMUX2", + "TERM_INT_IMUX2" + ], + [ + "INT_INTERFACE_WW4B1", + "L_TERM_INT_WW4A1" + ], + [ + "INT_INTERFACE_LH2", + "L_TERM_INT_LH1" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "INT_INTERFACE_IMUX9", + "TERM_INT_IMUX9" + ], + [ + "INT_INTERFACE_NE4C1", + "L_TERM_INT_NW4C1" + ], + [ + "INT_INTERFACE_IMUX29", + "TERM_INT_IMUX29" + ], + [ + "INT_INTERFACE_CTRL1", + "TERM_INT_CTRL1" + ], + [ + "INT_INTERFACE_ER1BEG1", + "L_TERM_INT_WR1BEG1" + ], + [ + "INT_INTERFACE_BYP4", + "TERM_INT_BYP4" + ], + [ + "INT_INTERFACE_BYP0", + "TERM_INT_BYP0" + ], + [ + "INT_INTERFACE_IMUX35", + "TERM_INT_IMUX35" + ], + [ + "INT_INTERFACE_SW4END3", + "L_TERM_INT_SW4C3" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90" + ], + [ + "INT_INTERFACE_EE2A2", + "L_TERM_INT_WW2A2" + ], + [ + "INT_INTERFACE_CTRL0", + "TERM_INT_CTRL0" + ], + [ + "INT_INTERFACE_WW2END1", + "L_TERM_INT_WW2A1" + ], + [ + "INT_INTERFACE_NE4BEG3", + "L_TERM_INT_NW4BEG3" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "INT_INTERFACE_NW4A2", + "L_TERM_INT_NW4BEG2" + ], + [ + "INT_INTERFACE_BYP1", + "TERM_INT_BYP1" + ], + [ + "INT_INTERFACE_WW2END2", + "L_TERM_INT_WW2A2" + ], + [ + "INT_INTERFACE_NW4END1", + "L_TERM_INT_NW4C1" + ], + [ + "INT_INTERFACE_IMUX17", + "TERM_INT_IMUX17" + ], + [ + "INT_INTERFACE_EE4A3", + "L_TERM_INT_WW4A3" + ], + [ + "INT_INTERFACE_IMUX43", + "TERM_INT_IMUX43" + ], + [ + "INT_INTERFACE_LH6", + "L_TERM_INT_LH5" + ], + [ + "INT_INTERFACE_IMUX34", + "TERM_INT_IMUX34" + ], + [ + "INT_INTERFACE_IMUX1", + "TERM_INT_IMUX1" + ], + [ + "INT_INTERFACE_IMUX27", + "TERM_INT_IMUX27" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "TERM_INT_LOGIC_OUTS_L_B8" + ], + [ + "INT_INTERFACE_LH11", + "L_TERM_INT_LH1" + ], + [ + "INT_INTERFACE_IMUX11", + "TERM_INT_IMUX11" + ], + [ + "INT_INTERFACE_LH5", + "L_TERM_INT_LH4" + ], + [ + "INT_INTERFACE_BLOCK_OUTS_L_B2", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "INT_INTERFACE_NW4A3", + "L_TERM_INT_NW4BEG3" + ], + [ + "INT_INTERFACE_SE2A0", + "L_TERM_INT_SW2BEG0" + ], + [ + "INT_INTERFACE_LH1", + "L_TERM_INT_LH0" + ], + [ + "INT_INTERFACE_WR1END2", + "L_TERM_INT_WR1BEG3" + ], + [ + "INT_INTERFACE_EE2A1", + "L_TERM_INT_WW2A1" + ], + [ + "INT_INTERFACE_EE4BEG1", + "L_TERM_INT_WW4BEG1" + ], + [ + "INT_INTERFACE_EE4B1", + "L_TERM_INT_WW4B1" + ], + [ + "INT_INTERFACE_WW4A3", + "L_TERM_INT_WW4BEG3" + ], + [ + "INT_INTERFACE_EE2BEG1", + "L_TERM_INT_WW2BEG1" + ], + [ + "INT_INTERFACE_SE2A2", + "L_TERM_INT_SW2BEG2" + ], + [ + "INT_INTERFACE_WW4B3", + "L_TERM_INT_WW4A3" + ], + [ + "INT_INTERFACE_IMUX22", + "TERM_INT_IMUX22" + ], + [ + "INT_INTERFACE_WW4A0", + "L_TERM_INT_WW4BEG0" + ], + [ + "INT_INTERFACE_NE4BEG2", + "L_TERM_INT_NW4BEG2" + ], + [ + "INT_INTERFACE_IMUX30", + "TERM_INT_IMUX30" + ], + [ + "INT_INTERFACE_SE4BEG0", + "L_TERM_INT_SW4BEG0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "TERM_INT_LOGIC_OUTS_L_B19" + ], + [ + "INT_INTERFACE_NE2A2", + "L_TERM_INT_NW2BEG2" + ], + [ + "INT_INTERFACE_MONITOR_P", + "TERM_INT_MONITOR_P" + ], + [ + "INT_INTERFACE_NE4BEG0", + "L_TERM_INT_NW4BEG0" + ], + [ + "INT_INTERFACE_ER1BEG0", + "L_TERM_INT_WR1BEG0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "TERM_INT_LOGIC_OUTS_L_B1" + ], + [ + "INT_INTERFACE_IMUX18", + "TERM_INT_IMUX18" + ], + [ + "INT_INTERFACE_FAN6", + "TERM_INT_FAN6" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "TERM_INT_LOGIC_OUTS_L_B16" + ], + [ + "INT_INTERFACE_IMUX42", + "TERM_INT_IMUX42" + ], + [ + "INT_INTERFACE_WW2A0", + "L_TERM_INT_WW2BEG0" + ], + [ + "INT_INTERFACE_IMUX46", + "TERM_INT_IMUX46" + ], + [ + "INT_INTERFACE_SW2A0", + "L_TERM_INT_SW2BEG0" + ], + [ + "INT_INTERFACE_SW2A1", + "L_TERM_INT_SW2BEG1" + ], + [ + "INT_INTERFACE_FAN5", + "TERM_INT_FAN5" + ], + [ + "INT_INTERFACE_SW2A2", + "L_TERM_INT_SW2BEG2" + ], + [ + "INT_INTERFACE_IMUX24", + "TERM_INT_IMUX24" + ], + [ + "L_INT_INTER_DQS_IOTOPHASER", + "L_TERM_INT_DQS_IOTOPHASER" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "INT_INTERFACE_IMUX6", + "TERM_INT_IMUX6" + ], + [ + "INT_INTERFACE_SW4A0", + "L_TERM_INT_SW4BEG0" + ], + [ + "INT_INTERFACE_IMUX44", + "TERM_INT_IMUX44" + ], + [ + "INT_INTERFACE_SW4END0", + "L_TERM_INT_SW4C0" + ], + [ + "INT_INTERFACE_EE2A0", + "L_TERM_INT_WW2A0" + ], + [ + "INT_INTERFACE_SE4BEG3", + "L_TERM_INT_SW4BEG3" + ], + [ + "INT_INTERFACE_WW4END1", + "L_TERM_INT_WW4C1" + ], + [ + "INT_INTERFACE_IMUX41", + "TERM_INT_IMUX41" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "TERM_INT_LOGIC_OUTS_L_B14" + ], + [ + "INT_INTERFACE_LH3", + "L_TERM_INT_LH2" + ], + [ + "INT_INTERFACE_WW4END0", + "L_TERM_INT_WW4C0" + ], + [ + "INT_INTERFACE_LH8", + "L_TERM_INT_LH4" + ], + [ + "INT_INTERFACE_SE4C3", + "L_TERM_INT_SW4C3" + ], + [ + "INT_INTERFACE_EE4C2", + "L_TERM_INT_WW4C2" + ], + [ + "INT_INTERFACE_NE2A1", + "L_TERM_INT_NW2BEG1" + ], + [ + "INT_INTERFACE_IMUX26", + "TERM_INT_IMUX26" + ], + [ + "INT_INTERFACE_FAN4", + "TERM_INT_FAN4" + ], + [ + "INT_INTERFACE_IMUX40", + "TERM_INT_IMUX40" + ], + [ + "INT_INTERFACE_SE4C0", + "L_TERM_INT_SW4C0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "INT_INTERFACE_IMUX33", + "TERM_INT_IMUX33" + ], + [ + "INT_INTERFACE_NE4BEG1", + "L_TERM_INT_NW4BEG1" + ], + [ + "INT_INTERFACE_WR1END1", + "L_TERM_INT_WR1BEG1" + ], + [ + "INT_INTERFACE_SW4END1", + "L_TERM_INT_SW4C1" + ], + [ + "INT_INTERFACE_EE2BEG2", + "L_TERM_INT_WW2BEG2" + ], + [ + "INT_INTERFACE_NE2A3", + "L_TERM_INT_NW2BEG3" + ], + [ + "INT_INTERFACE_WW2A3", + "L_TERM_INT_WW2BEG3" + ], + [ + "INT_INTERFACE_IMUX15", + "TERM_INT_IMUX15" + ], + [ + "INT_INTERFACE_CLK1", + "TERM_INT_CLK1" + ], + [ + "INT_INTERFACE_FAN7", + "TERM_INT_FAN7" + ], + [ + "INT_INTERFACE_WW2END3", + "L_TERM_INT_WW2A3" + ], + [ + "INT_INTERFACE_WW4C3", + "L_TERM_INT_WW4B3" + ], + [ + "INT_INTERFACE_MONITOR_N", + "TERM_INT_MONITOR_N" + ], + [ + "INT_INTERFACE_IMUX47", + "TERM_INT_IMUX47" + ], + [ + "INT_INTERFACE_NW2A3", + "L_TERM_INT_NW2BEG3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "TERM_INT_LOGIC_OUTS_L_B5" + ], + [ + "INT_INTERFACE_SE4C2", + "L_TERM_INT_SW4C2" + ], + [ + "INT_INTERFACE_NW4END0", + "L_TERM_INT_NW4C0" + ], + [ + "INT_INTERFACE_EE4A2", + "L_TERM_INT_WW4A2" + ], + [ + "INT_INTERFACE_EE4B2", + "L_TERM_INT_WW4B2" + ], + [ + "INT_INTERFACE_NW2A2", + "L_TERM_INT_NW2BEG2" + ], + [ + "INT_INTERFACE_EE4C1", + "L_TERM_INT_WW4C1" + ], + [ + "INT_INTERFACE_IMUX39", + "TERM_INT_IMUX39" + ], + [ + "INT_INTERFACE_WW2END0", + "L_TERM_INT_WW2A0" + ] + ], + "tile_types": [ + "IO_INT_INTERFACE_L", + "L_TERM_INT" + ] + }, + { + "grid_deltas": [ + 1, + -6 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW4A3_10", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SE2A3_10", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG0_10", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NW4END2_10", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_WW4C2_10", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_LH8_10", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4B2_10", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_WW4A1_10", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_WW4C0_10", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WL1END3_10", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_WL1END0_10", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_NW2A0_10", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW2END0_10", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE4C3_10", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE2BEG1_10", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_LH7_10", + "VBRK_LH7" + ], + [ + "CMT_TOP_EL1BEG1_10", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_NE4C2_10", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH10_10", + "VBRK_LH10" + ], + [ + "CMT_TOP_EE4B1_10", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_NE4C0_10", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH12_10", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4END1_10", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4BEG3_10", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WW2END2_10", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW4A2_10", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EL1BEG3_10", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_EE4A1_10", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_SW2A0_10", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_EE2BEG0_10", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_EE2A0_10", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH5_10", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW2A3_10", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW2A1_10", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WR1END2_10", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SW4END1_10", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW2A3_10", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SW4END2_10", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EL1BEG0_10", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_LH3_10", + "VBRK_LH3" + ], + [ + "CMT_TOP_NW4END0_10", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW4A1_10", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_SE4BEG2_10", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_EE4C2_10", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WR1END3_10", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WR1END1_10", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_NW4A0_10", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_10", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW4B1_10", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SE4C2_10", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_NE4BEG3_10", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4BEG1_10", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_EE4C1_10", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG2_10", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE2BEG3_10", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_SE4BEG3_10", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE2A1_10", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4A3_10", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_LH11_10", + "VBRK_LH11" + ], + [ + "CMT_TOP_SE4C1_10", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WL1END1_10", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW4B0_10", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2A2_10", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4BEG1_10", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WW4A0_10", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WW4END1_10", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_ER1BEG3_10", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WW4END2_10", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_ER1BEG0_10", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_LH1_10", + "VBRK_LH1" + ], + [ + "CMT_TOP_WW4C3_10", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_WW4END0_10", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NW4END3_10", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_LH9_10", + "VBRK_LH9" + ], + [ + "CMT_TOP_NW2A2_10", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SW4END3_10", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_LH6_10", + "VBRK_LH6" + ], + [ + "CMT_TOP_SW4A0_10", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_NE2A2_10", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2BEG2_10", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW2END1_10", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_EE4B0_10", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4C1_10", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SW2A2_10", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_EL1BEG2_10", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_NE2A0_10", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE2A1_10", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_10", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_WW2A0_10", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW4A2_10", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_SW4A1_10", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WR1END0_10", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_EE4B2_10", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW4END0_10", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4C0_10", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_10", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE4B3_10", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE4A0_10", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END3_10", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_WL1END2_10", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4A2_10", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4B3_10", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NE4C1_10", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_NW2A1_10", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2A2_10", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_EE4C3_10", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_MONITOR_N_10", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW4A2_10", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NE4BEG2_10", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_SW2A1_10", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4BEG0_10", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SE2A0_10", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4BEG1_10", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE4BEG0_10", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_10", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_SE2A2_10", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4END3_10", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SE4C3_10", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WW4A3_10", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_ER1BEG2_10", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_LH2_10", + "VBRK_LH2" + ], + [ + "CMT_TOP_NE2A3_10", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_EE2A3_10", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SE4C0_10", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_ER1BEG1_10", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_MONITOR_P_10", + "VBRK_MONITOR_P" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -9 + ], + "wire_pairs": [ + [ + "CFG_CENTER_IMUX2_9", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_EE4A0_9", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_WL1END3_9", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_EE4BEG1_9", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_EE4C2_9", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_IMUX10_9", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_ER1BEG3_9", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_WR1END2_9", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_SE2A3_9", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SE4BEG0_9", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_NW2A3_9", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NE4C2_9", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_IMUX27_9", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_SW2A2_9", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_IMUX15_9", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_9", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_LH3_9", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_EE4B0_9", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_EE2BEG0_9", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_ER1BEG2_9", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_SW4END0_9", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_NW4A3_9", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SW2A1_9", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_SW4A3_9", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EE2A1_9", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_SW4END1_9", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_NW4END2_9", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_IMUX38_9", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_EE4A3_9", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX19_9", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_9", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_9", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_NE4BEG1_9", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX4_9", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_WW4C2_9", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_NW4A2_9", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_NE2A0_9", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_IMUX5_9", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_LH8_9", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_LH11_9", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_NW2A2_9", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_IMUX37_9", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_EL1BEG3_9", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_BYP1_9", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_LH1_9", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_IMUX34_9", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_IMUX45_9", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX42_9", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_EE4BEG2_9", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_SW4END2_9", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_BYP6_9", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_EE4A2_9", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_IMUX16_9", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_IMUX24_9", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_IMUX46_9", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW4C1_9", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_IMUX41_9", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_IMUX26_9", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_LH6_9", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_SW2A3_9", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_EE4BEG3_9", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX28_9", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_FAN3_9", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_BYP4_9", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_CTRL1_9", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_WR1END3_9", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_SE2A0_9", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_FAN7_9", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_NW4A0_9", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_EL1BEG1_9", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_EL1BEG0_9", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_IMUX35_9", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_WW2A0_9", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_WW2END1_9", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_WL1END1_9", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_CLK1_9", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX18_9", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX3_9", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_SE4C1_9", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_EE4BEG0_9", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_FAN2_9", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_EE4B1_9", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_BYP7_9", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_IMUX32_9", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_WW4B0_9", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_IMUX9_9", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_NW2A0_9", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_BYP2_9", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_WW4END3_9", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_CTRL0_9", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_SE4C2_9", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_WW4B3_9", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_IMUX17_9", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX33_9", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_SW2A0_9", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_WW4A2_9", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_LH4_9", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_WR1END0_9", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EE2A3_9", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_IMUX11_9", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_NE4C0_9", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_WW4A0_9", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_SE4BEG1_9", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE2A0_9", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_NE2A2_9", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE4A1_9", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_EE4C3_9", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_NE4BEG0_9", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_LH2_9", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_NE4BEG2_9", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW2END2_9", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_NW4A1_9", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_9", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_SE4C3_9", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_SE4BEG3_9", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_IMUX25_9", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_WL1END2_9", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_FAN0_9", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_LH12_9", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_IMUX0_9", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW2A1_9", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_IMUX29_9", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX43_9", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_EL1BEG2_9", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NE4C3_9", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_WW4B1_9", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_EE4B2_9", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX21_9", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_NW2A1_9", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_WL1END0_9", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_IMUX20_9", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_9", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_IMUX12_9", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX14_9", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_WW4END0_9", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_NW4END3_9", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_WW4A3_9", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW4A1_9", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_IMUX13_9", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_FAN4_9", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW4B2_9", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_NW4END1_9", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_EE2A2_9", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_CLK0_9", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_IMUX36_9", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW4A2_9", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_IMUX39_9", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_LH5_9", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_WR1END1_9", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_IMUX22_9", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_SW4A1_9", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_FAN1_9", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_NE2A1_9", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX31_9", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_WW2A2_9", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_WW4C3_9", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_LH10_9", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_NW4END0_9", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_WW2A3_9", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_NE4BEG3_9", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_9", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_FAN5_9", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_IMUX8_9", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_WW4END1_9", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX40_9", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_BYP5_9", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_NE4C1_9", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_WW4END2_9", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_9", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_EE4C0_9", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_SE4BEG2_9", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_BYP0_9", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX7_9", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_EE4B3_9", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_LH9_9", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_SW4END3_9", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_LH7_9", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_BYP3_9", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_WW2END0_9", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_IMUX23_9", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WW4C0_9", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_ER1BEG1_9", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SE2A2_9", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_EE2BEG3_9", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_SE2A1_9", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_WW2END3_9", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_EE4C1_9", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX1_9", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_NE2A3_9", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_FAN6_9", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX44_9", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_ER1BEG0_9", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_EE2BEG1_9", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_SW4A0_9", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_SE4C0_9", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_EE2BEG2_9", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX47_9", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_9", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_IMUX30_9", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_IMUX6_9", + "VFRAME_IMUX6" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "CMT_TOP_EL1BEG1_8", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE4BEG1_8", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NW4A0_8", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4B0_8", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_WW4END0_8", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW2A0_8", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_SW2A0_8", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4BEG2_8", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_MONITOR_P_8", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_NE4C0_8", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_ER1BEG2_8", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_8", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_LH12_8", + "VBRK_LH12" + ], + [ + "CMT_TOP_EL1BEG2_8", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_LH1_8", + "VBRK_LH1" + ], + [ + "CMT_TOP_LH10_8", + "VBRK_LH10" + ], + [ + "CMT_TOP_WW4B1_8", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_EE4BEG2_8", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW4A3_8", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4C3_8", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_MONITOR_N_8", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_NW2A0_8", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NW4END0_8", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_SE2A2_8", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4C1_8", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW4C2_8", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_NW4A1_8", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NW2A1_8", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SE4BEG0_8", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_SE2A1_8", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_LH3_8", + "VBRK_LH3" + ], + [ + "CMT_TOP_WR1END2_8", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_NE2A0_8", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4A2_8", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_NW4END1_8", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_SE2A0_8", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE4A1_8", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EL1BEG0_8", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_EE4A3_8", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_NE4C3_8", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_EE4A0_8", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW2END1_8", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_LH4_8", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2A0_8", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_LH2_8", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW4C1_8", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_NE2A2_8", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE2A3_8", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_NW4A3_8", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_SW4END2_8", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_EE2A1_8", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_WW2END2_8", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_WW2END0_8", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_EE2BEG0_8", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW4C0_8", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_ER1BEG0_8", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_WR1END0_8", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_SE4C2_8", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4END1_8", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_NE2A1_8", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4B3_8", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_SW2A1_8", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4C2_8", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE4B1_8", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WW2A3_8", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_SE4C1_8", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_WR1END3_8", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_WW2A2_8", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C0_8", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NE4C1_8", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_LH11_8", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4B2_8", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_NW2A3_8", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NW4END2_8", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SW4A0_8", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WR1END1_8", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_LH5_8", + "VBRK_LH5" + ], + [ + "CMT_TOP_WL1END3_8", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_LH6_8", + "VBRK_LH6" + ], + [ + "CMT_TOP_NE4BEG3_8", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_LH8_8", + "VBRK_LH8" + ], + [ + "CMT_TOP_SW4A1_8", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_EE2BEG2_8", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4C3_8", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_NW2A2_8", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4END3_8", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_NE2A3_8", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_ER1BEG1_8", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_SW4END0_8", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_NE4BEG1_8", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_WW4A2_8", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_NE4BEG0_8", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_NE4C2_8", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_SE4BEG3_8", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_EE4C0_8", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_SW4A3_8", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2BEG3_8", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH9_8", + "VBRK_LH9" + ], + [ + "CMT_TOP_EE4B2_8", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_WL1END0_8", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_WW2END3_8", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EL1BEG3_8", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_ER1BEG3_8", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_EE4BEG3_8", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_WL1END1_8", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_WW2A1_8", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_SE4BEG2_8", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_SW2A3_8", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SE4C3_8", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE2A2_8", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_8", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_WW4A1_8", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NW4A2_8", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_SW2A2_8", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_NW4END3_8", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SW4END1_8", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4END3_8", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4BEG1_8", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WW4END2_8", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_LH7_8", + "VBRK_LH7" + ], + [ + "CMT_TOP_EE4BEG0_8", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_EE2BEG1_8", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_WW4B0_8", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_SE2A3_8", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WL1END2_8", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_WW4A0_8", + "VBRK_WW4A0" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -5 + ], + "wire_pairs": [ + [ + "CFG_CENTER_EE4A1_15", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_WL1END0_15", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_WW2A3_15", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_IMUX7_15", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_IMUX32_15", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_LH6_15", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_IMUX16_15", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WW4END2_15", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_15", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_WR1END3_15", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX38_15", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_WR1END2_15", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_EE4B3_15", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_LH5_15", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX6_15", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_WL1END2_15", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_BYP2_15", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_IMUX35_15", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_WW4A1_15", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_IMUX36_15", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW4END3_15", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_CTRL0_15", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_SE4BEG3_15", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_WW4C3_15", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NE2A0_15", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_15", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_NE4BEG3_15", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_SE2A0_15", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_EE4B0_15", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_NE4BEG1_15", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_FAN0_15", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_WR1END1_15", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_EE2A1_15", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX27_15", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_WW2A2_15", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_IMUX12_15", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX45_15", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_WW4END0_15", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_EL1BEG2_15", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_NE4C0_15", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_SE4C2_15", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_SW4A3_15", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_SW4END0_15", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_FAN2_15", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_BYP1_15", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_IMUX1_15", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX31_15", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_WW2END3_15", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WL1END1_15", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_WW2A1_15", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_NW4END2_15", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_NE4BEG0_15", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_IMUX24_15", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_WW4B0_15", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_WL1END3_15", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_SW2A3_15", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_SE4BEG1_15", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_EE4A0_15", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_SE4BEG2_15", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_SE4C3_15", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX18_15", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX0_15", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_LH7_15", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_FAN5_15", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_WW4B2_15", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_IMUX43_15", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_NE2A1_15", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX15_15", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_BYP6_15", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_EE4BEG0_15", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_NW4END3_15", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_SW2A0_15", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_IMUX14_15", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_WW4A3_15", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_IMUX3_15", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_EE4BEG3_15", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_IMUX25_15", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_NE4C1_15", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_WW4A0_15", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_NW2A0_15", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_SE4C0_15", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_EE2BEG1_15", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_EE4A2_15", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_NW4END1_15", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_LH10_15", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_NW4A3_15", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_IMUX8_15", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_SW2A1_15", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_WW4END1_15", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX41_15", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_EE2BEG3_15", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_ER1BEG3_15", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_WW4B1_15", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_15", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_IMUX30_15", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_IMUX37_15", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_SE2A1_15", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_IMUX39_15", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_LH9_15", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EE4B1_15", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_EE4C1_15", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX28_15", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_15", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_NW4END0_15", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_FAN7_15", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX44_15", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_IMUX21_15", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_15", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_SE4C1_15", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_LH8_15", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_WW4A2_15", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_CTRL1_15", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_IMUX11_15", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_WW4B3_15", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_FAN4_15", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_LH1_15", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_LH4_15", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_NW4A2_15", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_15", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_EE2A3_15", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_EE4A3_15", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_15", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_NW2A2_15", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_NE2A3_15", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_SW2A2_15", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_IMUX42_15", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_EE4BEG2_15", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_WW4C2_15", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_15", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_SW4END1_15", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_NW4A0_15", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX40_15", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_EL1BEG3_15", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_NE2A2_15", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_FAN1_15", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX26_15", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_SW4A1_15", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_IMUX20_15", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SW4A0_15", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_WW2A0_15", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_FAN6_15", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_IMUX23_15", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_LH2_15", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_WW4C0_15", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_WW2END1_15", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_BYP5_15", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_IMUX2_15", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_NE4C2_15", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_IMUX29_15", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_EE4C0_15", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_15", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_IMUX22_15", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX17_15", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_SE4BEG0_15", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_EL1BEG0_15", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_LH12_15", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_EL1BEG1_15", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_15", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_15", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_IMUX9_15", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX4_15", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_ER1BEG2_15", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_EE4BEG1_15", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_IMUX33_15", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_BYP3_15", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_IMUX46_15", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW2END2_15", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_SE2A2_15", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_EE2A2_15", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_NE4C3_15", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_EE2BEG0_15", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_EE2BEG2_15", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_WW2END0_15", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_IMUX10_15", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_IMUX19_15", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_IMUX34_15", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_LH11_15", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_WR1END0_15", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_NW2A1_15", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_WW4END3_15", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX13_15", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_SW4END2_15", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_EE4B2_15", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_CLK0_15", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_BYP0_15", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_BYP4_15", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_FAN3_15", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_15", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_NW4A1_15", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_IMUX5_15", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX47_15", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_SW4A2_15", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_BYP7_15", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_EE2A0_15", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WW4C1_15", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_EE4C3_15", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_NE4BEG2_15", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_NW2A3_15", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_CLK1_15", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_ER1BEG1_15", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_LH3_15", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_SE2A3_15", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_ER1BEG0_15", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_EE4C2_15", + "VFRAME_EE4C2" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CMT_TOP_NW2A2_5", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW4A0_5", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_WR1END2_5", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_SE4C1_5", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SW4END3_5", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_NW4END0_5", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NW2A0_5", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WL1END3_5", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SE2A2_5", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_EE4B3_5", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_EE2A2_5", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_WW4B3_5", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_LH3_5", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE4C2_5", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_EE2A0_5", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_NE4BEG1_5", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A1_5", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4A2_5", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW2END1_5", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_WW4C0_5", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_WW2A1_5", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_NW4END3_5", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE4BEG0_5", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_EL1BEG1_5", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_LH6_5", + "VBRK_LH6" + ], + [ + "CMT_TOP_EE4A1_5", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_NW4A2_5", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_NW4A3_5", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_NE4BEG0_5", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW2A2_5", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SE4C3_5", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_LH7_5", + "VBRK_LH7" + ], + [ + "CMT_TOP_WW4B2_5", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_LH5_5", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4A1_5", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4A0_5", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_NE4C1_5", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW2A0_5", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_WL1END2_5", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_SE4C0_5", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SW4END2_5", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4END1_5", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_EL1BEG0_5", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_WR1END1_5", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_EE4C1_5", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_EE4BEG0_5", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_NW4END2_5", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_EE2BEG2_5", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_EE4B1_5", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_ER1BEG3_5", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_NW2A1_5", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_WW4B0_5", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_WW2END2_5", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_SE2A1_5", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE2A3_5", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_LH11_5", + "VBRK_LH11" + ], + [ + "CMT_TOP_WL1END0_5", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SW4END0_5", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4BEG3_5", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_NE4C3_5", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_SE4BEG1_5", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NE2A2_5", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_EE4B0_5", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_ER1BEG2_5", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_SW4A2_5", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_NE2A0_5", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_EE4BEG1_5", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SE2A3_5", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NE4BEG2_5", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_LH9_5", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4END2_5", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EE4BEG2_5", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2END0_5", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_ER1BEG0_5", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE2A1_5", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_LH4_5", + "VBRK_LH4" + ], + [ + "CMT_TOP_EE2BEG1_5", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_NE4BEG3_5", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C0_5", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_LH8_5", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4A3_5", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_EE2BEG0_5", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_NE2A1_5", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_EE4C3_5", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_WL1END1_5", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW4A1_5", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW2END3_5", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4A0_5", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4END1_5", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH2_5", + "VBRK_LH2" + ], + [ + "CMT_TOP_NE2A3_5", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_NW4A0_5", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EE4A3_5", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4C0_5", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_LH12_5", + "VBRK_LH12" + ], + [ + "CMT_TOP_LH1_5", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW2A3_5", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_ER1BEG1_5", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE2BEG3_5", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH10_5", + "VBRK_LH10" + ], + [ + "CMT_TOP_SW2A2_5", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WR1END3_5", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NW4END1_5", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_NW4A1_5", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_WW4C2_5", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WR1END0_5", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_WW4END3_5", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_SW4A3_5", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WW2A3_5", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_WW4END0_5", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_NE4C2_5", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_EL1BEG3_5", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_SW2A3_5", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_WW4A2_5", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE4BEG3_5", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE4B2_5", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SW2A0_5", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_SE2A0_5", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_SE4BEG2_5", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4B1_5", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_WW4C1_5", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_SE4C2_5", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WW4C3_5", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_EL1BEG2_5", + "VBRK_EL1BEG2" + ] + ], + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CLK_BUFG_REBUF_EE2A1_1", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_BUFG_REBUF_SW4END0_1", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_BUFG_REBUF_EL1BEG2_1", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_BUFG_REBUF_WW4C0_1", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_BUFG_REBUF_SE4BEG2_1", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_BUFG_REBUF_EE4C3_1", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_BUFG_REBUF_NE4BEG2_1", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_BUFG_REBUF_NE4BEG1_1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_BUFG_REBUF_NW2A1_1", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_BUFG_REBUF_WR1END2_1", + "INT_INTERFACE_WR1END2" + ], + [ + "CLK_BUFG_REBUF_WW4C2_1", + "INT_INTERFACE_WW4C2" + ], + [ + "CLK_BUFG_REBUF_NE2A2_1", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_BUFG_REBUF_WW4B1_1", + "INT_INTERFACE_WW4B1" + ], + [ + "CLK_BUFG_REBUF_ER1BEG3_1", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_BUFG_REBUF_WW4END0_1", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_BUFG_REBUF_EE4C0_1", + "INT_INTERFACE_EE4C0" + ], + [ + "CLK_BUFG_REBUF_EE4A3_1", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_BUFG_REBUF_ER1BEG2_1", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_BUFG_REBUF_WR1END0_1", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_BUFG_REBUF_EE2BEG3_1", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_BUFG_REBUF_LH12_1", + "INT_INTERFACE_LH12" + ], + [ + "CLK_BUFG_REBUF_EE2BEG0_1", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_BUFG_REBUF_NE4C3_1", + "INT_INTERFACE_NE4C3" + ], + [ + "CLK_BUFG_REBUF_NW4A2_1", + "INT_INTERFACE_NW4A2" + ], + [ + "CLK_BUFG_REBUF_LH2_1", + "INT_INTERFACE_LH2" + ], + [ + "CLK_BUFG_REBUF_NW4A3_1", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_BUFG_REBUF_SE4BEG0_1", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_BUFG_REBUF_EE4BEG3_1", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_BUFG_REBUF_SW4END2_1", + "INT_INTERFACE_SW4END2" + ], + [ + "CLK_BUFG_REBUF_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_BUFG_REBUF_WW4C1_1", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_BUFG_REBUF_WW4END1_1", + "INT_INTERFACE_WW4END1" + ], + [ + "CLK_BUFG_REBUF_LH11_1", + "INT_INTERFACE_LH11" + ], + [ + "CLK_BUFG_REBUF_WW4A1_1", + "INT_INTERFACE_WW4A1" + ], + [ + "CLK_BUFG_REBUF_WW2END0_1", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_BUFG_REBUF_SE4C0_1", + "INT_INTERFACE_SE4C0" + ], + [ + "CLK_BUFG_REBUF_WR1END3_1", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_BUFG_REBUF_NE4C1_1", + "INT_INTERFACE_NE4C1" + ], + [ + "CLK_BUFG_REBUF_LH6_1", + "INT_INTERFACE_LH6" + ], + [ + "CLK_BUFG_REBUF_WW4A2_1", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_BUFG_REBUF_NW4END1_1", + "INT_INTERFACE_NW4END1" + ], + [ + "CLK_BUFG_REBUF_SE2A2_1", + "INT_INTERFACE_SE2A2" + ], + [ + "CLK_BUFG_REBUF_MONITOR_P_1", + "INT_INTERFACE_MONITOR_P" + ], + [ + "CLK_BUFG_REBUF_WW2END3_1", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_BUFG_REBUF_LH5_1", + "INT_INTERFACE_LH5" + ], + [ + "CLK_BUFG_REBUF_SE4C2_1", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_BUFG_REBUF_EE4A2_1", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_BUFG_REBUF_SE4C3_1", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_BUFG_REBUF_SW4A0_1", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_BUFG_REBUF_SW4A1_1", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_BUFG_REBUF_SW4END3_1", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_BUFG_REBUF_NW4A1_1", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_BUFG_REBUF_SW2A1_1", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_BUFG_REBUF_WW4B0_1", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_BUFG_REBUF_SE2A1_1", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_BUFG_REBUF_NE4BEG3_1", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_BUFG_REBUF_EE4B3_1", + "INT_INTERFACE_EE4B3" + ], + [ + "CLK_BUFG_REBUF_NW2A0_1", + "INT_INTERFACE_NW2A0" + ], + [ + "CLK_BUFG_REBUF_SW2A0_1", + "INT_INTERFACE_SW2A0" + ], + [ + "CLK_BUFG_REBUF_EL1BEG3_1", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_BUFG_REBUF_SW4A3_1", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_BUFG_REBUF_WL1END0_1", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_BUFG_REBUF_WW4B3_1", + "INT_INTERFACE_WW4B3" + ], + [ + "CLK_BUFG_REBUF_WW2A0_1", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_BUFG_REBUF_EE4BEG1_1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CLK_BUFG_REBUF_EE4BEG0_1", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_BUFG_REBUF_EE2BEG2_1", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_BUFG_REBUF_LH3_1", + "INT_INTERFACE_LH3" + ], + [ + "CLK_BUFG_REBUF_NW4END2_1", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_BUFG_REBUF_WL1END3_1", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_BUFG_REBUF_EE4B1_1", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_BUFG_REBUF_LH8_1", + "INT_INTERFACE_LH8" + ], + [ + "CLK_BUFG_REBUF_EL1BEG0_1", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_BUFG_REBUF_WW4A3_1", + "INT_INTERFACE_WW4A3" + ], + [ + "CLK_BUFG_REBUF_LH9_1", + "INT_INTERFACE_LH9" + ], + [ + "CLK_BUFG_REBUF_ER1BEG0_1", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_BUFG_REBUF_NE2A1_1", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_BUFG_REBUF_WW4C3_1", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_BUFG_REBUF_LH4_1", + "INT_INTERFACE_LH4" + ], + [ + "CLK_BUFG_REBUF_NE2A3_1", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_BUFG_REBUF_EE2A2_1", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_BUFG_REBUF_EE4C1_1", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_BUFG_REBUF_WW2END2_1", + "INT_INTERFACE_WW2END2" + ], + [ + "CLK_BUFG_REBUF_WW2END1_1", + "INT_INTERFACE_WW2END1" + ], + [ + "CLK_BUFG_REBUF_NE4C0_1", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_BUFG_REBUF_LH7_1", + "INT_INTERFACE_LH7" + ], + [ + "CLK_BUFG_REBUF_SE4C1_1", + "INT_INTERFACE_SE4C1" + ], + [ + "CLK_BUFG_REBUF_SW4A2_1", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_BUFG_REBUF_WR1END1_1", + "INT_INTERFACE_WR1END1" + ], + [ + "CLK_BUFG_REBUF_WW4END3_1", + "INT_INTERFACE_WW4END3" + ], + [ + "CLK_BUFG_REBUF_NW4END3_1", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_BUFG_REBUF_WW2A3_1", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_BUFG_REBUF_SE2A3_1", + "INT_INTERFACE_SE2A3" + ], + [ + "CLK_BUFG_REBUF_EL1BEG1_1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_BUFG_REBUF_NE4C2_1", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_BUFG_REBUF_WW4A0_1", + "INT_INTERFACE_WW4A0" + ], + [ + "CLK_BUFG_REBUF_EE2BEG1_1", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_BUFG_REBUF_EE4B0_1", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_BUFG_REBUF_LH10_1", + "INT_INTERFACE_LH10" + ], + [ + "CLK_BUFG_REBUF_EE2A0_1", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_BUFG_REBUF_LH1_1", + "INT_INTERFACE_LH1" + ], + [ + "CLK_BUFG_REBUF_SW4END1_1", + "INT_INTERFACE_SW4END1" + ], + [ + "CLK_BUFG_REBUF_WL1END2_1", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_BUFG_REBUF_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_BUFG_REBUF_EE4C2_1", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_BUFG_REBUF_SE4BEG1_1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CLK_BUFG_REBUF_EE4BEG2_1", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_BUFG_REBUF_WW4B2_1", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_BUFG_REBUF_SW2A3_1", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_BUFG_REBUF_EE4A0_1", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_BUFG_REBUF_NE4BEG0_1", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CLK_BUFG_REBUF_SW2A2_1", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_BUFG_REBUF_EE4B2_1", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_BUFG_REBUF_SE2A0_1", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_BUFG_REBUF_WW4END2_1", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_BUFG_REBUF_NE2A0_1", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_BUFG_REBUF_ER1BEG1_1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_BUFG_REBUF_MONITOR_N_1", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_BUFG_REBUF_EE4A1_1", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_BUFG_REBUF_EE2A3_1", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_BUFG_REBUF_NW4END0_1", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_BUFG_REBUF_SE4BEG3_1", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_BUFG_REBUF_NW2A3_1", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_BUFG_REBUF_WL1END1_1", + "INT_INTERFACE_WL1END1" + ], + [ + "CLK_BUFG_REBUF_NW2A2_1", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_BUFG_REBUF_NW4A0_1", + "INT_INTERFACE_NW4A0" + ] + ], + "tile_types": [ + "CLK_BUFG_REBUF", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + -1, + 1 + ], + "wire_pairs": [ + [ + "PCIE_LH10_9", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_IMUX47_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_NW4A3_9", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_WW4END0_9", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_SE4C3_9", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_IMUX34_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT34" + ], + [ + "PCIE_SW4A2_9", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_NW4A0_9", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_9", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_IMUX17_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT17" + ], + [ + "PCIE_WR1END2_9", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_WW2END2_9", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_SW2A1_9", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_LH4_9", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_BYP6_R_9", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_IMUX25_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT25" + ], + [ + "PCIE_WL1END3_9", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_BYP5_R_9", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_NE2A3_9", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_LH8_9", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4BEG1_9", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_BYP0_R_9", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_LH12_9", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_WL1END2_9", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_LH5_9", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_IMUX38_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_IMUX7_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT7" + ], + [ + "PCIE_IMUX35_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT35" + ], + [ + "PCIE_IMUX0_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT0" + ], + [ + "PCIE_IMUX24_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT24" + ], + [ + "PCIE_WW4C0_9", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_NW2A0_9", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_IMUX42_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_9", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_WW4END3_9", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_BYP2_R_9", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_9", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_EL1BEG2_9", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_9", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_WR1END1_9", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_FAN0_R_9", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_EE4BEG2_9", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX39_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_WW4A3_9", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_9", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_NE4BEG2_9", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_ER1BEG2_9", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_NW4END1_9", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_IMUX20_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT20" + ], + [ + "PCIE_EE4C3_9", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_IMUX29_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT29" + ], + [ + "PCIE_SW2A2_9", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_EE2A1_9", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_IMUX16_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT16" + ], + [ + "PCIE_EE4C0_9", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_EE4B0_9", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_IMUX5_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT5" + ], + [ + "PCIE_WW4A0_9", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_LH11_9", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_IMUX3_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT3" + ], + [ + "PCIE_IMUX8_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT8" + ], + [ + "PCIE_NE4C2_9", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_9", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_IMUX30_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT30" + ], + [ + "PCIE_SW2A0_9", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_LH1_9", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_IMUX23_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT23" + ], + [ + "PCIE_IMUX1_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT1" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_9", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_FAN4_R_9", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_9", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_IMUX9_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT9" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_9", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_WW4A1_9", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_IMUX43_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_LH3_9", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_WR1END3_9", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_WW4B0_9", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_SE2A2_9", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_EL1BEG0_9", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_ER1BEG0_9", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_SW4END3_9", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_NW4END3_9", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_EE2BEG0_9", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_CTRL1_R_9", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_NE2A0_9", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_ER1BEG1_9", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_EE4A2_9", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_SE4BEG1_9", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_LH7_9", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_WW2END1_9", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_SE4C0_9", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_NE4BEG1_9", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_IMUX32_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT32" + ], + [ + "PCIE_IMUX12_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT12" + ], + [ + "PCIE_IMUX26_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT26" + ], + [ + "PCIE_IMUX27_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT27" + ], + [ + "PCIE_NW4A2_9", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_IMUX6_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT6" + ], + [ + "PCIE_NW2A1_9", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_FAN6_R_9", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_FAN7_R_9", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_IMUX28_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT28" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_9", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_IMUX33_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT33" + ], + [ + "PCIE_SE4C2_9", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_EE2A3_9", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_WR1END0_9", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_SE4BEG0_9", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_EL1BEG3_9", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_9", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_EE2A0_9", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_IMUX11_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT11" + ], + [ + "PCIE_NE4C1_9", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_IMUX2_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT2" + ], + [ + "PCIE_IMUX36_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT36" + ], + [ + "PCIE_IMUX21_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT21" + ], + [ + "PCIE_CLK1_R_9", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_NW4END0_9", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_9", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_IMUX15_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT15" + ], + [ + "PCIE_SE4BEG2_9", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_FAN1_R_9", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_WW4B2_9", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_EE4BEG0_9", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_WW2A3_9", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_BYP1_R_9", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_EE4A0_9", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_SW4A3_9", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_EE2BEG3_9", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_9", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_MONITOR_N_9", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_9", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_NE4C0_9", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_LH2_9", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_SW4A1_9", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_WL1END1_9", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_IMUX4_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT4" + ], + [ + "PCIE_NW2A3_9", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_IMUX45_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_9", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_SE2A3_9", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_EE2BEG2_9", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_SW4A0_9", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_9", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_SW4END1_9", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_EE2BEG1_9", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_9", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_9", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_NW2A2_9", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_EE4C1_9", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_WW4END2_9", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_NW4A1_9", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_BYP4_R_9", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_NW4END2_9", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_IMUX22_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT22" + ], + [ + "PCIE_LH9_9", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_NE2A1_9", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_SE2A0_9", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_EE4BEG3_9", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_WW2END3_9", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_IMUX19_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT19" + ], + [ + "PCIE_FAN3_R_9", + "INT_INTERFACE_FAN3" + ], + [ + "PCIE_IMUX10_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT10" + ], + [ + "PCIE_FAN5_R_9", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_IMUX44_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_WW4A2_9", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_NE2A2_9", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_SW2A3_9", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_IMUX41_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_9", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_SW4END2_9", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_SE2A1_9", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_MONITOR_P_9", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_EL1BEG1_9", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_EE4A1_9", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_BYP7_R_9", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_9", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_9", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_WW2END0_9", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_WW4C3_9", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_SE4C1_9", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_SW4END0_9", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_EE4B1_9", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_BYP3_R_9", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_IMUX13_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT13" + ], + [ + "PCIE_EE4B2_9", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_IMUX40_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_IMUX18_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT18" + ], + [ + "PCIE_CLK0_R_9", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_FAN2_R_9", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_9", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_EE4C2_9", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_9", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_NE4BEG0_9", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_LH6_9", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_IMUX37_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_WW4C2_9", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_WW4B1_9", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_ER1BEG3_9", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_NE4C3_9", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_NE4BEG3_9", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_9", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_EE4B3_9", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_EE4A3_9", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_WW2A0_9", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_WW4B3_9", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_WW4END1_9", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_IMUX46_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_CTRL0_R_9", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_WW2A2_9", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_EE2A2_9", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_WL1END0_9", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_WW4C1_9", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_WW2A1_9", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_SE4BEG3_9", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_IMUX14_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT14" + ], + [ + "PCIE_IMUX31_R_9", + "PCIE_INT_INTERFACE_IMUX_OUT31" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + 4 + ], + "wire_pairs": [ + [ + "INT_FEEDTHRU_2_SW2A2", + "MONITOR_SW2A2_4" + ], + [ + "INT_FEEDTHRU_2_EE2BEG3", + "MONITOR_EE2BEG3_4" + ], + [ + "INT_FEEDTHRU_2_EE2A1", + "MONITOR_EE2A1_4" + ], + [ + "INT_FEEDTHRU_2_NW4END3", + "MONITOR_NW4END3_4" + ], + [ + "INT_FEEDTHRU_2_LH3", + "MONITOR_LH3_4" + ], + [ + "INT_FEEDTHRU_2_WR1END1", + "MONITOR_WR1END1_4" + ], + [ + "INT_FEEDTHRU_2_EE4A3", + "MONITOR_EE4A3_4" + ], + [ + "INT_FEEDTHRU_2_WW4END0", + "MONITOR_WW4END0_4" + ], + [ + "INT_FEEDTHRU_2_WW4A3", + "MONITOR_WW4A3_4" + ], + [ + "INT_FEEDTHRU_2_NE4BEG2", + "MONITOR_NE4BEG2_4" + ], + [ + "INT_FEEDTHRU_2_LH7", + "MONITOR_LH7_4" + ], + [ + "INT_FEEDTHRU_2_WL1END3", + "MONITOR_WL1END3_4" + ], + [ + "INT_FEEDTHRU_2_LH2", + "MONITOR_LH2_4" + ], + [ + "INT_FEEDTHRU_2_WW4B1", + "MONITOR_WW4B1_4" + ], + [ + "INT_FEEDTHRU_2_NE4BEG3", + "MONITOR_NE4BEG3_4" + ], + [ + "INT_FEEDTHRU_2_NW4A3", + "MONITOR_NW4A3_4" + ], + [ + "INT_FEEDTHRU_2_NE4C1", + "MONITOR_NE4C1_4" + ], + [ + "INT_FEEDTHRU_2_WW4A2", + "MONITOR_WW4A2_4" + ], + [ + "INT_FEEDTHRU_2_SW4A0", + "MONITOR_SW4A0_4" + ], + [ + "INT_FEEDTHRU_2_WW4END1", + "MONITOR_WW4END1_4" + ], + [ + "INT_FEEDTHRU_2_EE4BEG1", + "MONITOR_EE4BEG1_4" + ], + [ + "INT_FEEDTHRU_2_SE4C0", + "MONITOR_SE4C0_4" + ], + [ + "INT_FEEDTHRU_2_SE4BEG2", + "MONITOR_SE4BEG2_4" + ], + [ + "INT_FEEDTHRU_2_LH11", + "MONITOR_LH11_4" + ], + [ + "INT_FEEDTHRU_2_LH12", + "MONITOR_LH12_4" + ], + [ + "INT_FEEDTHRU_2_WW4C3", + "MONITOR_WW4C3_4" + ], + [ + "INT_FEEDTHRU_2_NE2A0", + "MONITOR_NE2A0_4" + ], + [ + "INT_FEEDTHRU_2_WW4END2", + "MONITOR_WW4END2_4" + ], + [ + "INT_FEEDTHRU_2_ER1BEG0", + "MONITOR_ER1BEG0_4" + ], + [ + "INT_FEEDTHRU_2_ER1BEG1", + "MONITOR_ER1BEG1_4" + ], + [ + "INT_FEEDTHRU_2_NW4END2", + "MONITOR_NW4END2_4" + ], + [ + "INT_FEEDTHRU_2_SW2A3", + "MONITOR_SW2A3_4" + ], + [ + "INT_FEEDTHRU_2_NW2A3", + "MONITOR_NW2A3_4" + ], + [ + "INT_FEEDTHRU_2_WW2END2", + "MONITOR_WW2END2_4" + ], + [ + "INT_FEEDTHRU_2_NW4A1", + "MONITOR_NW4A1_4" + ], + [ + "INT_FEEDTHRU_2_EE4A1", + "MONITOR_EE4A1_4" + ], + [ + "INT_FEEDTHRU_2_WW2A0", + "MONITOR_WW2A0_4" + ], + [ + "INT_FEEDTHRU_2_EE4C2", + "MONITOR_EE4C2_4" + ], + [ + "INT_FEEDTHRU_2_EE4BEG3", + "MONITOR_EE4BEG3_4" + ], + [ + "INT_FEEDTHRU_2_WL1END0", + "MONITOR_WL1END0_4" + ], + [ + "INT_FEEDTHRU_2_SW2A0", + "MONITOR_SW2A0_4" + ], + [ + "INT_FEEDTHRU_2_EE2BEG1", + "MONITOR_EE2BEG1_4" + ], + [ + "INT_FEEDTHRU_2_EE4BEG2", + "MONITOR_EE4BEG2_4" + ], + [ + "INT_FEEDTHRU_2_NW2A2", + "MONITOR_NW2A2_4" + ], + [ + "INT_FEEDTHRU_2_SE4C3", + "MONITOR_SE4C3_4" + ], + [ + "INT_FEEDTHRU_2_SW4END2", + "MONITOR_SW4END2_4" + ], + [ + "INT_FEEDTHRU_2_LH4", + "MONITOR_LH4_4" + ], + [ + "INT_FEEDTHRU_2_NE4C0", + "MONITOR_NE4C0_4" + ], + [ + "INT_FEEDTHRU_2_SE4C2", + "MONITOR_SE4C2_4" + ], + [ + "INT_FEEDTHRU_2_EE4C0", + "MONITOR_EE4C0_4" + ], + [ + "INT_FEEDTHRU_2_WW4B3", + "MONITOR_WW4B3_4" + ], + [ + "INT_FEEDTHRU_2_NE2A1", + "MONITOR_NE2A1_4" + ], + [ + "INT_FEEDTHRU_2_EE4BEG0", + "MONITOR_EE4BEG0_4" + ], + [ + "INT_FEEDTHRU_2_WL1END2", + "MONITOR_WL1END2_4" + ], + [ + "INT_FEEDTHRU_2_SW2A1", + "MONITOR_SW2A1_4" + ], + [ + "INT_FEEDTHRU_2_NE4C2", + "MONITOR_NE4C2_4" + ], + [ + "INT_FEEDTHRU_2_EE2BEG2", + "MONITOR_EE2BEG2_4" + ], + [ + "INT_FEEDTHRU_2_WW2A3", + "MONITOR_WW2A3_4" + ], + [ + "INT_FEEDTHRU_2_SW4END0", + "MONITOR_SW4END0_4" + ], + [ + "INT_FEEDTHRU_2_LH8", + "MONITOR_LH8_4" + ], + [ + "INT_FEEDTHRU_2_SE4C1", + "MONITOR_SE4C1_4" + ], + [ + "INT_FEEDTHRU_2_WW4A0", + "MONITOR_WW4A0_4" + ], + [ + "INT_FEEDTHRU_2_EE4C1", + "MONITOR_EE4C1_4" + ], + [ + "INT_FEEDTHRU_2_LH9", + "MONITOR_LH9_4" + ], + [ + "INT_FEEDTHRU_2_WW2A2", + "MONITOR_WW2A2_4" + ], + [ + "INT_FEEDTHRU_2_EE4A2", + "MONITOR_EE4A2_4" + ], + [ + "INT_FEEDTHRU_2_WW4B0", + "MONITOR_WW4B0_4" + ], + [ + "INT_FEEDTHRU_2_SE4BEG0", + "MONITOR_SE4BEG0_4" + ], + [ + "INT_FEEDTHRU_2_WW4C1", + "MONITOR_WW4C1_4" + ], + [ + "INT_FEEDTHRU_2_NW4END0", + "MONITOR_NW4END0_4" + ], + [ + "INT_FEEDTHRU_2_EE2A2", + "MONITOR_EE2A2_4" + ], + [ + "INT_FEEDTHRU_2_SW4A1", + "MONITOR_SW4A1_4" + ], + [ + "INT_FEEDTHRU_2_SW4END3", + "MONITOR_SW4END3_4" + ], + [ + "INT_FEEDTHRU_2_WW2END1", + "MONITOR_WW2END1_4" + ], + [ + "INT_FEEDTHRU_2_EE4B2", + "MONITOR_EE4B2_4" + ], + [ + "INT_FEEDTHRU_2_EL1BEG2", + "MONITOR_EL1BEG2_4" + ], + [ + "INT_FEEDTHRU_2_NW4A2", + "MONITOR_NW4A2_4" + ], + [ + "INT_FEEDTHRU_2_NE4BEG1", + "MONITOR_NE4BEG1_4" + ], + [ + "INT_FEEDTHRU_2_WW2END3", + "MONITOR_WW2END3_4" + ], + [ + "INT_FEEDTHRU_2_SW4A2", + "MONITOR_SW4A2_4" + ], + [ + "INT_FEEDTHRU_2_WW2END0", + "MONITOR_WW2END0_4" + ], + [ + "INT_FEEDTHRU_2_NE2A3", + "MONITOR_NE2A3_4" + ], + [ + "INT_FEEDTHRU_2_ER1BEG2", + "MONITOR_ER1BEG2_4" + ], + [ + "INT_FEEDTHRU_2_NW4END1", + "MONITOR_NW4END1_4" + ], + [ + "INT_FEEDTHRU_2_WR1END3", + "MONITOR_WR1END3_4" + ], + [ + "INT_FEEDTHRU_2_EE4B3", + "MONITOR_EE4B3_4" + ], + [ + "INT_FEEDTHRU_2_SW4END1", + "MONITOR_SW4END1_4" + ], + [ + "INT_FEEDTHRU_2_NE4C3", + "MONITOR_NE4C3_4" + ], + [ + "INT_FEEDTHRU_2_EE2A3", + "MONITOR_EE2A3_4" + ], + [ + "INT_FEEDTHRU_2_SE2A0", + "MONITOR_SE2A0_4" + ], + [ + "INT_FEEDTHRU_2_LH1", + "MONITOR_LH1_4" + ], + [ + "INT_FEEDTHRU_2_EL1BEG3", + "MONITOR_EL1BEG3_4" + ], + [ + "INT_FEEDTHRU_2_ER1BEG3", + "MONITOR_ER1BEG3_4" + ], + [ + "INT_FEEDTHRU_2_LH6", + "MONITOR_LH6_4" + ], + [ + "INT_FEEDTHRU_2_WW4B2", + "MONITOR_WW4B2_4" + ], + [ + "INT_FEEDTHRU_2_SE4BEG3", + "MONITOR_SE4BEG3_4" + ], + [ + "INT_FEEDTHRU_2_LH5", + "MONITOR_LH5_4" + ], + [ + "INT_FEEDTHRU_2_SW4A3", + "MONITOR_SW4A3_4" + ], + [ + "INT_FEEDTHRU_2_SE2A1", + "MONITOR_SE2A1_4" + ], + [ + "INT_FEEDTHRU_2_EE4A0", + "MONITOR_EE4A0_4" + ], + [ + "INT_FEEDTHRU_2_WL1END1", + "MONITOR_WL1END1_4" + ], + [ + "INT_FEEDTHRU_2_WW4END3", + "MONITOR_WW4END3_4" + ], + [ + "INT_FEEDTHRU_2_SE4BEG1", + "MONITOR_SE4BEG1_4" + ], + [ + "INT_FEEDTHRU_2_WW4C0", + "MONITOR_WW4C0_4" + ], + [ + "INT_FEEDTHRU_2_NW2A1", + "MONITOR_NW2A1_4" + ], + [ + "INT_FEEDTHRU_2_NE2A2", + "MONITOR_NE2A2_4" + ], + [ + "INT_FEEDTHRU_2_EL1BEG0", + "MONITOR_EL1BEG0_4" + ], + [ + "INT_FEEDTHRU_2_WR1END0", + "MONITOR_WR1END0_4" + ], + [ + "INT_FEEDTHRU_2_EE4B0", + "MONITOR_EE4B0_4" + ], + [ + "INT_FEEDTHRU_2_WW2A1", + "MONITOR_WW2A1_4" + ], + [ + "INT_FEEDTHRU_2_NE4BEG0", + "MONITOR_NE4BEG0_4" + ], + [ + "INT_FEEDTHRU_2_LH10", + "MONITOR_LH10_4" + ], + [ + "INT_FEEDTHRU_2_WW4C2", + "MONITOR_WW4C2_4" + ], + [ + "INT_FEEDTHRU_2_EE2A0", + "MONITOR_EE2A0_4" + ], + [ + "INT_FEEDTHRU_2_WR1END2", + "MONITOR_WR1END2_4" + ], + [ + "INT_FEEDTHRU_2_WW4A1", + "MONITOR_WW4A1_4" + ], + [ + "INT_FEEDTHRU_2_SE2A3", + "MONITOR_SE2A3_4" + ], + [ + "INT_FEEDTHRU_2_EL1BEG1", + "MONITOR_EL1BEG1_4" + ], + [ + "INT_FEEDTHRU_2_SE2A2", + "MONITOR_SE2A2_4" + ], + [ + "INT_FEEDTHRU_2_EE4C3", + "MONITOR_EE4C3_4" + ], + [ + "INT_FEEDTHRU_2_EE2BEG0", + "MONITOR_EE2BEG0_4" + ], + [ + "INT_FEEDTHRU_2_NW4A0", + "MONITOR_NW4A0_4" + ], + [ + "INT_FEEDTHRU_2_NW2A0", + "MONITOR_NW2A0_4" + ], + [ + "INT_FEEDTHRU_2_EE4B1", + "MONITOR_EE4B1_4" + ] + ], + "tile_types": [ + "INT_FEEDTHRU_2", + "MONITOR_TOP_FUJI2" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "BRAM_CASCINBOT_ADDRARDADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" + ], + [ + "BRAM_FIFO36_CASCADEINA", + "HCLK_BRAM_CASCADEA_L" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" + ], + [ + "BRAM_PMVBRAM_SELECT1", + "HCLK_BRAM_PMVBRAM_SELECT1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" + ], + [ + "BRAM_PMVBRAM_SELECT3", + "HCLK_BRAM_PMVBRAM_SELECT3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" + ], + [ + "BRAM_PMVBRAM_SELECT4", + "HCLK_BRAM_PMVBRAM_SELECT4" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_PMVBRAM_SELECT2", + "HCLK_BRAM_PMVBRAM_SELECT2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" + ], + [ + "BRAM_FIFO36_CASCADEINB", + "HCLK_BRAM_CASCADEB_L" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" + ], + [ + "BRAM_PMVBRAM_ODIV4", + "HCLK_BRAM_PMVBRAM_ODIV4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" + ], + [ + "BRAM_PMVBRAM_ODIV2", + "HCLK_BRAM_PMVBRAM_ODIV2" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" + ], + [ + "BRAM_PMVBRAM_O", + "HCLK_BRAM_PMVBRAM_O" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" + ] + ], + "tile_types": [ + "BRAM_L", + "HCLK_BRAM" + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "wire_pairs": [ + [ + "GTXE2_LOGIC_OUTS_B23_9", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_LOGIC_OUTS_B4_9", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B7_9", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B8_9", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX0_9", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_IMUX42_9", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX38_9", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_LOGIC_OUTS_B3_9", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX13_9", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_IMUX10_9", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_LOGIC_OUTS_B15_9", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_FAN2_9", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_BYP4_9", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX27_9", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_FAN1_9", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_BYP2_9", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX40_9", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_IMUX44_9", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_CLK1_9", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_LOGIC_OUTS_B2_9", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX14_9", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX11_9", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX3_9", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX47_9", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_LOGIC_OUTS_B11_9", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_FAN3_9", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX33_9", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_FAN5_9", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_BYP1_9", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_LOGIC_OUTS_B20_9", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX8_9", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_IMUX20_9", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_IMUX34_9", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX18_9", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_IMUX1_9", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_LOGIC_OUTS_B18_9", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_IMUX5_9", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_LOGIC_OUTS_B19_9", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_BYP3_9", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B14_9", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX30_9", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_IMUX15_9", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_BYP6_9", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX43_9", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX23_9", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_IMUX7_9", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX26_9", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_IMUX9_9", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX46_9", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_LOGIC_OUTS_B0_9", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX29_9", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_IMUX4_9", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_IMUX6_9", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_IMUX22_9", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_LOGIC_OUTS_B9_9", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_LOGIC_OUTS_B10_9", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_IMUX21_9", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_FAN6_9", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_BYP0_9", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX39_9", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_IMUX16_9", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX35_9", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_FAN0_9", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_LOGIC_OUTS_B16_9", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_LOGIC_OUTS_B6_9", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_LOGIC_OUTS_B21_9", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTXE2_LOGIC_OUTS_B13_9", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_CTRL0_9", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX28_9", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_LOGIC_OUTS_B17_9", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_CLK0_9", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_FAN4_9", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_FAN7_9", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_IMUX45_9", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_IMUX36_9", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX2_9", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_BYP5_9", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_IMUX41_9", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B5_9", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_LOGIC_OUTS_B12_9", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX31_9", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_LOGIC_OUTS_B1_9", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTXE2_CTRL1_9", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_IMUX17_9", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_IMUX24_9", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_IMUX12_9", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX32_9", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_LOGIC_OUTS_B22_9", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_BYP7_9", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_IMUX25_9", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX19_9", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_IMUX37_9", + "VBRK_EXT_IMUX37" + ] + ], + "tile_types": [ + "GTX_CHANNEL_1", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CLK_FEED_EE4B1", + "VBRK_EE4B1" + ], + [ + "CLK_FEED_SE4C1", + "VBRK_SE4C1" + ], + [ + "CLK_FEED_EE2BEG0", + "VBRK_EE2BEG0" + ], + [ + "CLK_FEED_SW2A1", + "VBRK_SW2A1" + ], + [ + "CLK_FEED_WR1END1", + "VBRK_WR1END1" + ], + [ + "CLK_FEED_WL1END3", + "VBRK_WL1END3" + ], + [ + "CLK_FEED_NE2A2", + "VBRK_NE2A2" + ], + [ + "CLK_FEED_WW2END0", + "VBRK_WW2END0" + ], + [ + "CLK_FEED_LH9", + "VBRK_LH9" + ], + [ + "CLK_FEED_EE4C1", + "VBRK_EE4C1" + ], + [ + "CLK_FEED_NW2A0", + "VBRK_NW2A0" + ], + [ + "CLK_FEED_WW4A1", + "VBRK_WW4A1" + ], + [ + "CLK_FEED_NE2A1", + "VBRK_NE2A1" + ], + [ + "CLK_FEED_WW4A3", + "VBRK_WW4A3" + ], + [ + "CLK_FEED_WW2END1", + "VBRK_WW2END1" + ], + [ + "CLK_FEED_WW4C3", + "VBRK_WW4C3" + ], + [ + "CLK_FEED_LH5", + "VBRK_LH5" + ], + [ + "CLK_FEED_LH10", + "VBRK_LH10" + ], + [ + "CLK_FEED_LH12", + "VBRK_LH12" + ], + [ + "CLK_FEED_EE4B0", + "VBRK_EE4B0" + ], + [ + "CLK_FEED_EE4A2", + "VBRK_EE4A2" + ], + [ + "CLK_FEED_WW4END2", + "VBRK_WW4END2" + ], + [ + "CLK_FEED_NE4C2", + "VBRK_NE4C2" + ], + [ + "CLK_FEED_NW4A1", + "VBRK_NW4A1" + ], + [ + "CLK_FEED_SW4A2", + "VBRK_SW4A2" + ], + [ + "CLK_FEED_NW4END0", + "VBRK_NW4END0" + ], + [ + "CLK_FEED_WW2END3", + "VBRK_WW2END3" + ], + [ + "CLK_FEED_WW4C1", + "VBRK_WW4C1" + ], + [ + "CLK_FEED_SW2A0", + "VBRK_SW2A0" + ], + [ + "CLK_FEED_SW4A0", + "VBRK_SW4A0" + ], + [ + "CLK_FEED_NE4BEG3", + "VBRK_NE4BEG3" + ], + [ + "CLK_FEED_ER1BEG0", + "VBRK_ER1BEG0" + ], + [ + "CLK_FEED_EE2BEG2", + "VBRK_EE2BEG2" + ], + [ + "CLK_FEED_WW4B3", + "VBRK_WW4B3" + ], + [ + "CLK_FEED_WW2A3", + "VBRK_WW2A3" + ], + [ + "CLK_FEED_WW4C2", + "VBRK_WW4C2" + ], + [ + "CLK_FEED_LH8", + "VBRK_LH8" + ], + [ + "CLK_FEED_NE4C0", + "VBRK_NE4C0" + ], + [ + "CLK_FEED_EL1BEG3", + "VBRK_EL1BEG3" + ], + [ + "CLK_FEED_LH1", + "VBRK_LH1" + ], + [ + "CLK_FEED_EL1BEG0", + "VBRK_EL1BEG0" + ], + [ + "CLK_FEED_EE4A1", + "VBRK_EE4A1" + ], + [ + "CLK_FEED_SW2A2", + "VBRK_SW2A2" + ], + [ + "CLK_FEED_SE4C3", + "VBRK_SE4C3" + ], + [ + "CLK_FEED_EE4BEG0", + "VBRK_EE4BEG0" + ], + [ + "CLK_FEED_LH4", + "VBRK_LH4" + ], + [ + "CLK_FEED_NW4A2", + "VBRK_NW4A2" + ], + [ + "CLK_FEED_EE2BEG3", + "VBRK_EE2BEG3" + ], + [ + "CLK_FEED_SE4BEG0", + "VBRK_SE4BEG0" + ], + [ + "CLK_FEED_SE4BEG3", + "VBRK_SE4BEG3" + ], + [ + "CLK_FEED_WW4END0", + "VBRK_WW4END0" + ], + [ + "CLK_FEED_EE4B3", + "VBRK_EE4B3" + ], + [ + "CLK_FEED_WL1END0", + "VBRK_WL1END0" + ], + [ + "CLK_FEED_SW4A3", + "VBRK_SW4A3" + ], + [ + "CLK_FEED_WW2A1", + "VBRK_WW2A1" + ], + [ + "CLK_FEED_NE4C1", + "VBRK_NE4C1" + ], + [ + "CLK_FEED_WW2END2", + "VBRK_WW2END2" + ], + [ + "CLK_FEED_EE2A0", + "VBRK_EE2A0" + ], + [ + "CLK_FEED_SE4C2", + "VBRK_SE4C2" + ], + [ + "CLK_FEED_SW4END1", + "VBRK_SW4END1" + ], + [ + "CLK_FEED_EE4BEG2", + "VBRK_EE4BEG2" + ], + [ + "CLK_FEED_WL1END2", + "VBRK_WL1END2" + ], + [ + "CLK_FEED_EL1BEG2", + "VBRK_EL1BEG2" + ], + [ + "CLK_FEED_EE4BEG1", + "VBRK_EE4BEG1" + ], + [ + "CLK_FEED_WR1END3", + "VBRK_WR1END3" + ], + [ + "CLK_FEED_EE4C2", + "VBRK_EE4C2" + ], + [ + "CLK_FEED_NW4A3", + "VBRK_NW4A3" + ], + [ + "CLK_FEED_SW4END0", + "VBRK_SW4END0" + ], + [ + "CLK_FEED_WR1END0", + "VBRK_WR1END0" + ], + [ + "CLK_FEED_SE2A1", + "VBRK_SE2A1" + ], + [ + "CLK_FEED_WW4END3", + "VBRK_WW4END3" + ], + [ + "CLK_FEED_NW2A3", + "VBRK_NW2A3" + ], + [ + "CLK_FEED_WR1END2", + "VBRK_WR1END2" + ], + [ + "CLK_FEED_NW4END1", + "VBRK_NW4END1" + ], + [ + "CLK_FEED_LH11", + "VBRK_LH11" + ], + [ + "CLK_FEED_WW4B0", + "VBRK_WW4B0" + ], + [ + "CLK_FEED_NW4A0", + "VBRK_NW4A0" + ], + [ + "CLK_FEED_MONITOR_P", + "VBRK_MONITOR_P" + ], + [ + "CLK_FEED_NW2A1", + "VBRK_NW2A1" + ], + [ + "CLK_FEED_EE4A0", + "VBRK_EE4A0" + ], + [ + "CLK_FEED_NE4C3", + "VBRK_NE4C3" + ], + [ + "CLK_FEED_EE2A1", + "VBRK_EE2A1" + ], + [ + "CLK_FEED_LH6", + "VBRK_LH6" + ], + [ + "CLK_FEED_LH7", + "VBRK_LH7" + ], + [ + "CLK_FEED_WW4B2", + "VBRK_WW4B2" + ], + [ + "CLK_FEED_SW4END2", + "VBRK_SW4END2" + ], + [ + "CLK_FEED_WW4B1", + "VBRK_WW4B1" + ], + [ + "CLK_FEED_NW4END2", + "VBRK_NW4END2" + ], + [ + "CLK_FEED_WL1END1", + "VBRK_WL1END1" + ], + [ + "CLK_FEED_SW4A1", + "VBRK_SW4A1" + ], + [ + "CLK_FEED_NE2A0", + "VBRK_NE2A0" + ], + [ + "CLK_FEED_NW2A2", + "VBRK_NW2A2" + ], + [ + "CLK_FEED_WW2A0", + "VBRK_WW2A0" + ], + [ + "CLK_FEED_EE2A3", + "VBRK_EE2A3" + ], + [ + "CLK_FEED_WW2A2", + "VBRK_WW2A2" + ], + [ + "CLK_FEED_LH2", + "VBRK_LH2" + ], + [ + "CLK_FEED_EE4C3", + "VBRK_EE4C3" + ], + [ + "CLK_FEED_WW4END1", + "VBRK_WW4END1" + ], + [ + "CLK_FEED_NE4BEG0", + "VBRK_NE4BEG0" + ], + [ + "CLK_FEED_NW4END3", + "VBRK_NW4END3" + ], + [ + "CLK_FEED_SW2A3", + "VBRK_SW2A3" + ], + [ + "CLK_FEED_EE2A2", + "VBRK_EE2A2" + ], + [ + "CLK_FEED_EE4B2", + "VBRK_EE4B2" + ], + [ + "CLK_FEED_WW4A2", + "VBRK_WW4A2" + ], + [ + "CLK_FEED_ER1BEG2", + "VBRK_ER1BEG2" + ], + [ + "CLK_FEED_EE4BEG3", + "VBRK_EE4BEG3" + ], + [ + "CLK_FEED_EE4C0", + "VBRK_EE4C0" + ], + [ + "CLK_FEED_MONITOR_N", + "VBRK_MONITOR_N" + ], + [ + "CLK_FEED_NE4BEG2", + "VBRK_NE4BEG2" + ], + [ + "CLK_FEED_SW4END3", + "VBRK_SW4END3" + ], + [ + "CLK_FEED_WW4A0", + "VBRK_WW4A0" + ], + [ + "CLK_FEED_NE4BEG1", + "VBRK_NE4BEG1" + ], + [ + "CLK_FEED_SE2A0", + "VBRK_SE2A0" + ], + [ + "CLK_FEED_EE2BEG1", + "VBRK_EE2BEG1" + ], + [ + "CLK_FEED_ER1BEG3", + "VBRK_ER1BEG3" + ], + [ + "CLK_FEED_LH3", + "VBRK_LH3" + ], + [ + "CLK_FEED_ER1BEG1", + "VBRK_ER1BEG1" + ], + [ + "CLK_FEED_EL1BEG1", + "VBRK_EL1BEG1" + ], + [ + "CLK_FEED_SE4C0", + "VBRK_SE4C0" + ], + [ + "CLK_FEED_SE4BEG1", + "VBRK_SE4BEG1" + ], + [ + "CLK_FEED_SE2A2", + "VBRK_SE2A2" + ], + [ + "CLK_FEED_EE4A3", + "VBRK_EE4A3" + ], + [ + "CLK_FEED_SE2A3", + "VBRK_SE2A3" + ], + [ + "CLK_FEED_WW4C0", + "VBRK_WW4C0" + ], + [ + "CLK_FEED_SE4BEG2", + "VBRK_SE4BEG2" + ], + [ + "CLK_FEED_NE2A3", + "VBRK_NE2A3" + ] + ], + "tile_types": [ + "CLK_PMVIOB", + "VBRK" + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "wire_pairs": [ + [ + "CFG_CENTER_NW4A1_13", + "INT_FEEDTHRU_2_NW4A1" + ], + [ + "CFG_CENTER_WW4B2_13", + "INT_FEEDTHRU_2_WW4B2" + ], + [ + "CFG_CENTER_WW2END1_13", + "INT_FEEDTHRU_2_WW2END1" + ], + [ + "CFG_CENTER_NE4C3_13", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_NE2A0_13", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_NW4END3_13", + "INT_FEEDTHRU_2_NW4END3" + ], + [ + "CFG_CENTER_WW4END1_13", + "INT_FEEDTHRU_2_WW4END1" + ], + [ + "CFG_CENTER_SW2A1_13", + "INT_FEEDTHRU_2_SW2A1" + ], + [ + "CFG_CENTER_NE2A1_13", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_EL1BEG3_13", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_LH7_13", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_WL1END2_13", + "INT_FEEDTHRU_2_WL1END2" + ], + [ + "CFG_CENTER_EE4BEG3_13", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_EL1BEG1_13", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_WW4B0_13", + "INT_FEEDTHRU_2_WW4B0" + ], + [ + "CFG_CENTER_SW4A1_13", + "INT_FEEDTHRU_2_SW4A1" + ], + [ + "CFG_CENTER_WW4B3_13", + "INT_FEEDTHRU_2_WW4B3" + ], + [ + "CFG_CENTER_WW4A0_13", + "INT_FEEDTHRU_2_WW4A0" + ], + [ + "CFG_CENTER_WW4A3_13", + "INT_FEEDTHRU_2_WW4A3" + ], + [ + "CFG_CENTER_ER1BEG2_13", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_EL1BEG0_13", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_NW4A3_13", + "INT_FEEDTHRU_2_NW4A3" + ], + [ + "CFG_CENTER_EL1BEG2_13", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_NW4END1_13", + "INT_FEEDTHRU_2_NW4END1" + ], + [ + "CFG_CENTER_EE2BEG2_13", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_WW4C1_13", + "INT_FEEDTHRU_2_WW4C1" + ], + [ + "CFG_CENTER_SE4BEG1_13", + "INT_FEEDTHRU_2_SE4BEG1" + ], + [ + "CFG_CENTER_NW4A2_13", + "INT_FEEDTHRU_2_NW4A2" + ], + [ + "CFG_CENTER_NW2A0_13", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_SW4END0_13", + "INT_FEEDTHRU_2_SW4END0" + ], + [ + "CFG_CENTER_SW2A2_13", + "INT_FEEDTHRU_2_SW2A2" + ], + [ + "CFG_CENTER_WR1END3_13", + "INT_FEEDTHRU_2_WR1END3" + ], + [ + "CFG_CENTER_WW4END2_13", + "INT_FEEDTHRU_2_WW4END2" + ], + [ + "CFG_CENTER_LH4_13", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_WL1END0_13", + "INT_FEEDTHRU_2_WL1END0" + ], + [ + "CFG_CENTER_SE4C1_13", + "INT_FEEDTHRU_2_SE4C1" + ], + [ + "CFG_CENTER_LH9_13", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_NE4C0_13", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_NW4A0_13", + "INT_FEEDTHRU_2_NW4A0" + ], + [ + "CFG_CENTER_WR1END1_13", + "INT_FEEDTHRU_2_WR1END1" + ], + [ + "CFG_CENTER_SE2A0_13", + "INT_FEEDTHRU_2_SE2A0" + ], + [ + "CFG_CENTER_EE4A0_13", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4B1_13", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EE4C3_13", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_SW2A0_13", + "INT_FEEDTHRU_2_SW2A0" + ], + [ + "CFG_CENTER_EE2A2_13", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_WW2END2_13", + "INT_FEEDTHRU_2_WW2END2" + ], + [ + "CFG_CENTER_LH10_13", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_EE4B2_13", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_ER1BEG0_13", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_NW2A2_13", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_WW4END3_13", + "INT_FEEDTHRU_2_WW4END3" + ], + [ + "CFG_CENTER_ER1BEG1_13", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_EE4A1_13", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_SE4BEG3_13", + "INT_FEEDTHRU_2_SE4BEG3" + ], + [ + "CFG_CENTER_WL1END1_13", + "INT_FEEDTHRU_2_WL1END1" + ], + [ + "CFG_CENTER_SE4BEG0_13", + "INT_FEEDTHRU_2_SE4BEG0" + ], + [ + "CFG_CENTER_SW4END3_13", + "INT_FEEDTHRU_2_SW4END3" + ], + [ + "CFG_CENTER_WW2A3_13", + "INT_FEEDTHRU_2_WW2A3" + ], + [ + "CFG_CENTER_LH12_13", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_LH8_13", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_SE4C2_13", + "INT_FEEDTHRU_2_SE4C2" + ], + [ + "CFG_CENTER_NE4BEG1_13", + "INT_FEEDTHRU_2_NE4BEG1" + ], + [ + "CFG_CENTER_EE4A3_13", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_NE2A2_13", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_EE4C1_13", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_LH2_13", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_EE4BEG2_13", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_SW4A3_13", + "INT_FEEDTHRU_2_SW4A3" + ], + [ + "CFG_CENTER_WW2A2_13", + "INT_FEEDTHRU_2_WW2A2" + ], + [ + "CFG_CENTER_EE2A0_13", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_WW4C3_13", + "INT_FEEDTHRU_2_WW4C3" + ], + [ + "CFG_CENTER_WW4C0_13", + "INT_FEEDTHRU_2_WW4C0" + ], + [ + "CFG_CENTER_NW2A3_13", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NE4C1_13", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_WR1END0_13", + "INT_FEEDTHRU_2_WR1END0" + ], + [ + "CFG_CENTER_LH6_13", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_EE2BEG1_13", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_NW4END0_13", + "INT_FEEDTHRU_2_NW4END0" + ], + [ + "CFG_CENTER_NE4BEG0_13", + "INT_FEEDTHRU_2_NE4BEG0" + ], + [ + "CFG_CENTER_SE2A2_13", + "INT_FEEDTHRU_2_SE2A2" + ], + [ + "CFG_CENTER_NW4END2_13", + "INT_FEEDTHRU_2_NW4END2" + ], + [ + "CFG_CENTER_WL1END3_13", + "INT_FEEDTHRU_2_WL1END3" + ], + [ + "CFG_CENTER_LH3_13", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_NE4BEG2_13", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_WW2A0_13", + "INT_FEEDTHRU_2_WW2A0" + ], + [ + "CFG_CENTER_WW2END3_13", + "INT_FEEDTHRU_2_WW2END3" + ], + [ + "CFG_CENTER_EE4B0_13", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_LH11_13", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_EE4C2_13", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_SE4BEG2_13", + "INT_FEEDTHRU_2_SE4BEG2" + ], + [ + "CFG_CENTER_WW4C2_13", + "INT_FEEDTHRU_2_WW4C2" + ], + [ + "CFG_CENTER_SW4END1_13", + "INT_FEEDTHRU_2_SW4END1" + ], + [ + "CFG_CENTER_SW4END2_13", + "INT_FEEDTHRU_2_SW4END2" + ], + [ + "CFG_CENTER_SE2A1_13", + "INT_FEEDTHRU_2_SE2A1" + ], + [ + "CFG_CENTER_WW4B1_13", + "INT_FEEDTHRU_2_WW4B1" + ], + [ + "CFG_CENTER_NE4BEG3_13", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_WW2A1_13", + "INT_FEEDTHRU_2_WW2A1" + ], + [ + "CFG_CENTER_WW2END0_13", + "INT_FEEDTHRU_2_WW2END0" + ], + [ + "CFG_CENTER_SW2A3_13", + "INT_FEEDTHRU_2_SW2A3" + ], + [ + "CFG_CENTER_WW4END0_13", + "INT_FEEDTHRU_2_WW4END0" + ], + [ + "CFG_CENTER_EE2BEG3_13", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_LH5_13", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_EE4BEG0_13", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_NE2A3_13", + "INT_FEEDTHRU_2_NE2A3" + ], + [ + "CFG_CENTER_SW4A0_13", + "INT_FEEDTHRU_2_SW4A0" + ], + [ + "CFG_CENTER_EE2A1_13", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_SE4C0_13", + "INT_FEEDTHRU_2_SE4C0" + ], + [ + "CFG_CENTER_NE4C2_13", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_EE2BEG0_13", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_WW4A2_13", + "INT_FEEDTHRU_2_WW4A2" + ], + [ + "CFG_CENTER_WR1END2_13", + "INT_FEEDTHRU_2_WR1END2" + ], + [ + "CFG_CENTER_EE2A3_13", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_NW2A1_13", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_EE4C0_13", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EE4A2_13", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_SE4C3_13", + "INT_FEEDTHRU_2_SE4C3" + ], + [ + "CFG_CENTER_EE4B3_13", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_SE2A3_13", + "INT_FEEDTHRU_2_SE2A3" + ], + [ + "CFG_CENTER_ER1BEG3_13", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_SW4A2_13", + "INT_FEEDTHRU_2_SW4A2" + ], + [ + "CFG_CENTER_LH1_13", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_WW4A1_13", + "INT_FEEDTHRU_2_WW4A1" + ], + [ + "CFG_CENTER_EE4BEG1_13", + "INT_FEEDTHRU_2_EE4BEG1" + ] + ], + "tile_types": [ + "CFG_CENTER_MID", + "INT_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "wire_pairs": [ + [ + "CMT_TOP_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH6_3", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_LH1_3", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_LH12_3", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_LH7_3", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_3", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH3_3", + "VBRK_LH3" + ], + [ + "CMT_TOP_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_MONITOR_P_3", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_LH2_3", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_MONITOR_N_3", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_LH9_3", + "VBRK_LH9" + ], + [ + "CMT_TOP_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH5_3", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH11_3", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_LH10_3", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH8_3", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EL1BEG1_3", + "VBRK_EL1BEG1" + ] + ], + "tile_types": [ + "CMT_TOP_L_LOWER_T", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -3 + ], + "wire_pairs": [ + [ + "DSP_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "DSP_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "DSP_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "DSP_LH4_3", + "VBRK_LH4" + ], + [ + "DSP_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "DSP_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "DSP_LH7_3", + "VBRK_LH7" + ], + [ + "DSP_LH5_3", + "VBRK_LH5" + ], + [ + "DSP_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "DSP_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "DSP_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "DSP_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "DSP_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "DSP_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "DSP_LH3_3", + "VBRK_LH3" + ], + [ + "DSP_LH1_3", + "VBRK_LH1" + ], + [ + "DSP_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "DSP_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "DSP_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "DSP_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "DSP_EL1BEG1_3", + "VBRK_EL1BEG1" + ], + [ + "DSP_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "DSP_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "DSP_LH12_3", + "VBRK_LH12" + ], + [ + "DSP_LH2_3", + "VBRK_LH2" + ], + [ + "DSP_LH9_3", + "VBRK_LH9" + ], + [ + "DSP_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "DSP_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "DSP_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "DSP_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "DSP_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "DSP_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "DSP_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "DSP_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "DSP_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "DSP_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "DSP_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "DSP_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "DSP_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "DSP_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "DSP_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "DSP_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "DSP_LH8_3", + "VBRK_LH8" + ], + [ + "DSP_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "DSP_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "DSP_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "DSP_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "DSP_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "DSP_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "DSP_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "DSP_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "DSP_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "DSP_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "DSP_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "DSP_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "DSP_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "DSP_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "DSP_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "DSP_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "DSP_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "DSP_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "DSP_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "DSP_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "DSP_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "DSP_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "DSP_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "DSP_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "DSP_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "DSP_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "DSP_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "DSP_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "DSP_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "DSP_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "DSP_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "DSP_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "DSP_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "DSP_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "DSP_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "DSP_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "DSP_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "DSP_MONITOR_N_3", + "VBRK_MONITOR_N" + ], + [ + "DSP_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "DSP_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "DSP_LH11_3", + "VBRK_LH11" + ], + [ + "DSP_LH6_3", + "VBRK_LH6" + ], + [ + "DSP_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "DSP_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "DSP_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "DSP_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "DSP_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "DSP_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "DSP_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "DSP_MONITOR_P_3", + "VBRK_MONITOR_P" + ], + [ + "DSP_LH10_3", + "VBRK_LH10" + ], + [ + "DSP_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "DSP_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "DSP_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "DSP_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "DSP_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "DSP_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "DSP_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "DSP_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "DSP_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "DSP_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "DSP_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "DSP_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "DSP_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "DSP_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "DSP_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "DSP_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "DSP_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "DSP_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "DSP_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "DSP_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "DSP_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "DSP_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "DSP_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "DSP_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "DSP_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "DSP_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "DSP_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "DSP_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "DSP_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "DSP_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "DSP_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "DSP_WR1END0_3", + "VBRK_WR1END0" + ] + ], + "tile_types": [ + "DSP_R", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + 5 + ], + "wire_pairs": [ + [ + "CMT_TOP_SW4END0_3", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_SE4C1_3", + "VBRK_SE4C1" + ], + [ + "CMT_TOP_SE2A0_3", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_EE2A3_3", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE2BEG2_3", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NW2A2_3", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_NW2A0_3", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW2A0_3", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_WW2END1_3", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SW2A2_3", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WW2A2_3", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_SW4END1_3", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SE4BEG3_3", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_LH6_3", + "VBRK_LH6" + ], + [ + "CMT_TOP_WW4B2_3", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_ER1BEG3_3", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END3_3", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_SW4END3_3", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_EE2A2_3", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NW4A1_3", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_SW4A2_3", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_WW4END3_3", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4END0_3", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_LH1_3", + "VBRK_LH1" + ], + [ + "CMT_TOP_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SE4BEG2_3", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WW4A1_3", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_NW2A1_3", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_SW4A3_3", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_EE2A1_3", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_NW2A3_3", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_LH12_3", + "VBRK_LH12" + ], + [ + "CMT_TOP_SE4C0_3", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NW4END2_3", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_SE2A2_3", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WW4C0_3", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SE4C2_3", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_WL1END2_3", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4B1_3", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END2_3", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WW2END2_3", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW4END1_3", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_EE2BEG0_3", + "VBRK_EE2BEG0" + ], + [ + "CMT_TOP_LH7_3", + "VBRK_LH7" + ], + [ + "CMT_TOP_NW4A3_3", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_EE4B0_3", + "VBRK_EE4B0" + ], + [ + "CMT_TOP_SW4A0_3", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_WW4B0_3", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_SW2A1_3", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_WW4END2_3", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW4A0_3", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_LH4_3", + "VBRK_LH4" + ], + [ + "CMT_TOP_WR1END0_3", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_LH3_3", + "VBRK_LH3" + ], + [ + "CMT_TOP_WW4A3_3", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_WW4B3_3", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_SE4BEG0_3", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4C1_3", + "VBRK_WW4C1" + ], + [ + "CMT_TOP_WW2END3_3", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_SW4END2_3", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_SW4A1_3", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_MONITOR_P_3", + "VBRK_MONITOR_P" + ], + [ + "CMT_TOP_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE2A3_3", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_NW4END3_3", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_EE2BEG1_3", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_LH2_3", + "VBRK_LH2" + ], + [ + "CMT_TOP_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_SW2A3_3", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_WR1END3_3", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_SE4BEG1_3", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_MONITOR_N_3", + "VBRK_MONITOR_N" + ], + [ + "CMT_TOP_WL1END1_3", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_ER1BEG2_3", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_WR1END1_3", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW4B1_3", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_ER1BEG1_3", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_LH9_3", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4A0_3", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_NE4C3_3", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW4END1_3", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_LH5_3", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C2_3", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_WW2A0_3", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH11_3", + "VBRK_LH11" + ], + [ + "CMT_TOP_WW4A2_3", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_LH10_3", + "VBRK_LH10" + ], + [ + "CMT_TOP_SE2A1_3", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_WW2END0_3", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_WW2A1_3", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WL1END0_3", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_EE2A0_3", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_LH8_3", + "VBRK_LH8" + ], + [ + "CMT_TOP_WW4C3_3", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_NW4A2_3", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SE4C3_3", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_WW2A3_3", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_WW4END0_3", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_EL1BEG1_3", + "VBRK_EL1BEG1" + ] + ], + "tile_types": [ + "CMT_TOP_R_LOWER_B", + "VBRK" + ] + }, + { + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CFG_CENTER_NW4A1_1", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_WW4A1_1", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_IMUX3_1", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_SW4END0_1", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_WW2A3_1", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_BYP1_1", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_WW2END3_1", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_SE2A2_1", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_LH4_1", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_CTRL0_1", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_IMUX10_1", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_FAN2_1", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_EE4B2_1", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_IMUX31_1", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_EE4C3_1", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_WW4B2_1", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_LH3_1", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX46_1", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW2A2_1", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_EE4A1_1", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_WW2END0_1", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_NW4END3_1", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_EE2BEG3_1", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX33_1", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_WW2END1_1", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_ER1BEG2_1", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX5_1", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_WR1END3_1", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_IMUX32_1", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_IMUX17_1", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_NW4END2_1", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_IMUX22_1", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_IMUX24_1", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_BYP2_1", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_IMUX38_1", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_IMUX21_1", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_WL1END3_1", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_NE2A1_1", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_BYP6_1", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_LH7_1", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_SE2A3_1", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_FAN5_1", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_IMUX37_1", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_IMUX42_1", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX13_1", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_FAN7_1", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_ER1BEG1_1", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_SW2A1_1", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_LH2_1", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_SW4A0_1", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_EE4BEG1_1", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG0_1", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_SW4END1_1", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_IMUX23_1", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_WR1END0_1", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_WR1END1_1", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_NE4BEG0_1", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_SW2A2_1", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_WW4B0_1", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_LH9_1", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_NE4C0_1", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_SE2A0_1", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_SE4BEG2_1", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_EE2A3_1", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NW2A0_1", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_NE4C1_1", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_BYP4_1", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WW4END2_1", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_WW4C1_1", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_SW4A1_1", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_IMUX41_1", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_NW4A2_1", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_EE2A2_1", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_IMUX35_1", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_NE2A2_1", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE4BEG0_1", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_NW2A3_1", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NE2A0_1", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_BYP0_1", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX34_1", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_WW4C2_1", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_IMUX18_1", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_EL1BEG0_1", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_LH11_1", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_WW4END1_1", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_EE4A0_1", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_IMUX47_1", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX43_1", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_WL1END1_1", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_SW4A2_1", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NW4A0_1", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX20_1", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_SE4BEG1_1", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_BYP5_1", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_SE4BEG3_1", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_WW4A0_1", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_IMUX12_1", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX4_1", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_EE4B0_1", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_CLK1_1", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX7_1", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_IMUX6_1", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_NE4BEG2_1", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW4END3_1", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX2_1", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_WW4C3_1", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_WR1END2_1", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_EE4C0_1", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_WW4END0_1", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_FAN1_1", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX1_1", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX36_1", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_SW4A3_1", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_EE4A2_1", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_SE4C0_1", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_NW2A1_1", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_ER1BEG3_1", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_SW4END2_1", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_WL1END0_1", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_SW2A3_1", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_EE2BEG2_1", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_EE2BEG0_1", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_IMUX9_1", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_EL1BEG3_1", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW4A3_1", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_IMUX11_1", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_NE4BEG1_1", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_IMUX29_1", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_FAN6_1", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_EE4A3_1", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_NE4C2_1", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_BYP3_1", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_IMUX14_1", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_IMUX0_1", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_EE4BEG3_1", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_SW4END3_1", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_NE4BEG3_1", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX25_1", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_FAN3_1", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_EE2A0_1", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_ER1BEG0_1", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_WL1END2_1", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WW2A1_1", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_SE4C2_1", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_LH10_1", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_FAN0_1", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_EE4C1_1", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX16_1", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_WW4A2_1", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_NW4END1_1", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_SE4C1_1", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX39_1", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_CTRL1_1", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_LH6_1", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_EL1BEG1_1", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_IMUX28_1", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_IMUX44_1", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_EE4B1_1", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_WW2END2_1", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_WW4C0_1", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_EE2A1_1", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_IMUX15_1", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_NW4A3_1", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_SE2A1_1", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_SW2A0_1", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_LH5_1", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX45_1", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX27_1", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_NW4END0_1", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_BYP7_1", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_IMUX26_1", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_CLK0_1", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_WW4B3_1", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_IMUX30_1", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_IMUX40_1", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_EE2BEG1_1", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_NE4C3_1", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_LH12_1", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_LH8_1", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_NE2A3_1", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_NW2A2_1", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WW4B1_1", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_LH1_1", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_EE4C2_1", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_EL1BEG2_1", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_FAN4_1", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_WW2A0_1", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_IMUX8_1", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_SE4C3_1", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX19_1", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_EE4BEG2_1", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_EE4B3_1", + "VFRAME_EE4B3" + ] + ], + "tile_types": [ + "CFG_CENTER_TOP", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "INT_INTERFACE_LOGIC_OUTS4", + "LOGIC_OUTS4" + ], + [ + "GTXE2_INT_INTERFACE_IMUX21", + "IMUX21" + ], + [ + "INT_INTERFACE_FAN4", + "FAN4" + ], + [ + "INT_INTERFACE_NW4END3", + "NW6END3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX13", + "IMUX13" + ], + [ + "INT_INTERFACE_WW2A2", + "WW2A2" + ], + [ + "GTXE2_INT_INTERFACE_IMUX35", + "IMUX35" + ], + [ + "GTXE2_INT_INTERFACE_IMUX8", + "IMUX8" + ], + [ + "INT_INTERFACE_NW4A0", + "NW6A0" + ], + [ + "INT_INTERFACE_SE4BEG3", + "SE6BEG3" + ], + [ + "INT_INTERFACE_SE4C0", + "SE6E0" + ], + [ + "INT_INTERFACE_SW4A0", + "SW6A0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX37", + "IMUX37" + ], + [ + "GTXE2_INT_INTERFACE_IMUX33", + "IMUX33" + ], + [ + "INT_INTERFACE_EE4BEG3", + "EE4BEG3" + ], + [ + "INT_INTERFACE_WW4END3", + "WW4END3" + ], + [ + "INT_INTERFACE_CLK1", + "CLK1" + ], + [ + "INT_INTERFACE_WR1END0", + "WR1END0" + ], + [ + "INT_INTERFACE_WW2END1", + "WW2END1" + ], + [ + "INT_INTERFACE_FAN7", + "FAN7" + ], + [ + "INT_INTERFACE_LH5", + "LH5" + ], + [ + "GTXE2_INT_INTERFACE_IMUX44", + "IMUX44" + ], + [ + "INT_INTERFACE_SE4C2", + "SE6E2" + ], + [ + "INT_INTERFACE_EE2BEG0", + "EE2BEG0" + ], + [ + "INT_INTERFACE_SE2A2", + "SE2A2" + ], + [ + "INT_INTERFACE_BYP0", + "BYP0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX43", + "IMUX43" + ], + [ + "INT_INTERFACE_BYP5", + "BYP5" + ], + [ + "INT_INTERFACE_WL1END0", + "WL1END0" + ], + [ + "INT_INTERFACE_WW4A3", + "WW4A3" + ], + [ + "INT_INTERFACE_LH4", + "LH4" + ], + [ + "INT_INTERFACE_WW4C3", + "WW4C3" + ], + [ + "INT_INTERFACE_SW2A2", + "SW2END2" + ], + [ + "GTXE2_INT_INTERFACE_IMUX3", + "IMUX3" + ], + [ + "INT_INTERFACE_EE2BEG3", + "EE2BEG3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX24", + "IMUX24" + ], + [ + "INT_INTERFACE_LH11", + "LH11" + ], + [ + "INT_INTERFACE_LOGIC_OUTS12", + "LOGIC_OUTS12" + ], + [ + "INT_INTERFACE_WW2A3", + "WW2A3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX15", + "IMUX15" + ], + [ + "INT_INTERFACE_NE2A0", + "NE2A0" + ], + [ + "INT_INTERFACE_NE4BEG3", + "NE6BEG3" + ], + [ + "INT_INTERFACE_SE4C3", + "SE6E3" + ], + [ + "INT_INTERFACE_SE2A3", + "SE2A3" + ], + [ + "INT_INTERFACE_ER1BEG3", + "ER1BEG3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX41", + "IMUX41" + ], + [ + "INT_INTERFACE_WW4END0", + "WW4END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS2", + "LOGIC_OUTS2" + ], + [ + "GTXE2_INT_INTERFACE_IMUX16", + "IMUX16" + ], + [ + "GTXE2_INT_INTERFACE_IMUX42", + "IMUX42" + ], + [ + "GTXE2_INT_INTERFACE_IMUX9", + "IMUX9" + ], + [ + "INT_INTERFACE_EE4A2", + "EE4A2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS14", + "LOGIC_OUTS14" + ], + [ + "GTXE2_INT_INTERFACE_IMUX5", + "IMUX5" + ], + [ + "INT_INTERFACE_WW2END2", + "WW2END2" + ], + [ + "INT_INTERFACE_WW4END2", + "WW4END2" + ], + [ + "INT_INTERFACE_NW4END2", + "NW6END2" + ], + [ + "INT_INTERFACE_SW2A0", + "SW2END0" + ], + [ + "INT_INTERFACE_EE4C1", + "EE4C1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX1", + "IMUX1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX36", + "IMUX36" + ], + [ + "GTXE2_INT_INTERFACE_IMUX34", + "IMUX34" + ], + [ + "INT_INTERFACE_EE2BEG2", + "EE2BEG2" + ], + [ + "INT_INTERFACE_NE4BEG2", + "NE6BEG2" + ], + [ + "INT_INTERFACE_WW4A2", + "WW4A2" + ], + [ + "GTXE2_INT_INTERFACE_IMUX46", + "IMUX46" + ], + [ + "GTXE2_INT_INTERFACE_IMUX17", + "IMUX17" + ], + [ + "INT_INTERFACE_WL1END2", + "WL1END2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS6", + "LOGIC_OUTS6" + ], + [ + "INT_INTERFACE_NW2A1", + "NW2END1" + ], + [ + "INT_INTERFACE_SW4END3", + "SW6END3" + ], + [ + "INT_INTERFACE_NW2A0", + "NW2END0" + ], + [ + "INT_INTERFACE_EE4B2", + "EE4B2" + ], + [ + "GTXE2_INT_INTERFACE_IMUX2", + "IMUX2" + ], + [ + "GTXE2_INT_INTERFACE_IMUX38", + "IMUX38" + ], + [ + "GTXE2_INT_INTERFACE_IMUX30", + "IMUX30" + ], + [ + "GTXE2_INT_INTERFACE_IMUX11", + "IMUX11" + ], + [ + "INT_INTERFACE_EE4C2", + "EE4C2" + ], + [ + "INT_INTERFACE_ER1BEG0", + "ER1BEG0" + ], + [ + "INT_INTERFACE_EE2A1", + "EE2A1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS15", + "LOGIC_OUTS15" + ], + [ + "INT_INTERFACE_WW4C0", + "WW4C0" + ], + [ + "INT_INTERFACE_WW2END0", + "WW2END0" + ], + [ + "INT_INTERFACE_NE2A2", + "NE2A2" + ], + [ + "INT_INTERFACE_LH3", + "LH3" + ], + [ + "INT_INTERFACE_EE4B1", + "EE4B1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX10", + "IMUX10" + ], + [ + "INT_INTERFACE_BYP4", + "BYP4" + ], + [ + "INT_INTERFACE_SE4BEG0", + "SE6BEG0" + ], + [ + "INT_INTERFACE_NW2A3", + "NW2END3" + ], + [ + "INT_INTERFACE_CTRL0", + "CTRL0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX7", + "IMUX7" + ], + [ + "INT_INTERFACE_LOGIC_OUTS23", + "LOGIC_OUTS23" + ], + [ + "INT_INTERFACE_LH8", + "LH8" + ], + [ + "INT_INTERFACE_LOGIC_OUTS21", + "LOGIC_OUTS21" + ], + [ + "INT_INTERFACE_ER1BEG2", + "ER1BEG2" + ], + [ + "INT_INTERFACE_FAN5", + "FAN5" + ], + [ + "GTXE2_INT_INTERFACE_IMUX25", + "IMUX25" + ], + [ + "GTXE2_INT_INTERFACE_IMUX6", + "IMUX6" + ], + [ + "INT_INTERFACE_LH6", + "LH6" + ], + [ + "INT_INTERFACE_CTRL1", + "CTRL1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX4", + "IMUX4" + ], + [ + "INT_INTERFACE_BYP7", + "BYP7" + ], + [ + "INT_INTERFACE_SW4END2", + "SW6END2" + ], + [ + "INT_INTERFACE_WW4B3", + "WW4B3" + ], + [ + "INT_INTERFACE_WR1END3", + "WR1END3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX18", + "IMUX18" + ], + [ + "INT_INTERFACE_SE2A1", + "SE2A1" + ], + [ + "INT_INTERFACE_SW4A2", + "SW6A2" + ], + [ + "INT_INTERFACE_SW2A3", + "SW2END3" + ], + [ + "INT_INTERFACE_WW2A1", + "WW2A1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS10", + "LOGIC_OUTS10" + ], + [ + "INT_INTERFACE_EE4C3", + "EE4C3" + ], + [ + "INT_INTERFACE_SE4C1", + "SE6E1" + ], + [ + "INT_INTERFACE_EE4A1", + "EE4A1" + ], + [ + "INT_INTERFACE_EE4B3", + "EE4B3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS18", + "LOGIC_OUTS18" + ], + [ + "INT_INTERFACE_FAN2", + "FAN2" + ], + [ + "INT_INTERFACE_EL1BEG0", + "EL1BEG0" + ], + [ + "INT_INTERFACE_WL1END3", + "WL1END3" + ], + [ + "INT_INTERFACE_BYP1", + "BYP1" + ], + [ + "INT_INTERFACE_WR1END2", + "WR1END2" + ], + [ + "INT_INTERFACE_WW4B1", + "WW4B1" + ], + [ + "INT_INTERFACE_EE2A3", + "EE2A3" + ], + [ + "INT_INTERFACE_WW4A1", + "WW4A1" + ], + [ + "INT_INTERFACE_EE4B0", + "EE4B0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS3", + "LOGIC_OUTS3" + ], + [ + "INT_INTERFACE_NW4A2", + "NW6A2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS5", + "LOGIC_OUTS5" + ], + [ + "INT_INTERFACE_EL1BEG3", + "EL1BEG3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX39", + "IMUX39" + ], + [ + "INT_INTERFACE_FAN6", + "FAN6" + ], + [ + "INT_INTERFACE_NE4C2", + "NE6E2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS8", + "LOGIC_OUTS8" + ], + [ + "INT_INTERFACE_NW2A2", + "NW2END2" + ], + [ + "INT_INTERFACE_SE4BEG1", + "SE6BEG1" + ], + [ + "INT_INTERFACE_SW4A1", + "SW6A1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX47", + "IMUX47" + ], + [ + "INT_INTERFACE_SW2A1", + "SW2END1" + ], + [ + "INT_INTERFACE_SE4BEG2", + "SE6BEG2" + ], + [ + "INT_INTERFACE_FAN3", + "FAN3" + ], + [ + "INT_INTERFACE_ER1BEG1", + "ER1BEG1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX28", + "IMUX28" + ], + [ + "INT_INTERFACE_EE4A0", + "EE4A0" + ], + [ + "INT_INTERFACE_NW4A1", + "NW6A1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX26", + "IMUX26" + ], + [ + "INT_INTERFACE_WW4A0", + "WW4A0" + ], + [ + "INT_INTERFACE_WW4B0", + "WW4B0" + ], + [ + "INT_INTERFACE_SW4END1", + "SW6END1" + ], + [ + "INT_INTERFACE_WW4C1", + "WW4C1" + ], + [ + "INT_INTERFACE_NE4C3", + "NE6E3" + ], + [ + "INT_INTERFACE_BYP3", + "BYP3" + ], + [ + "INT_INTERFACE_EE4BEG0", + "EE4BEG0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX31", + "IMUX31" + ], + [ + "GTXE2_INT_INTERFACE_IMUX27", + "IMUX27" + ], + [ + "INT_INTERFACE_MONITOR_P", + "MONITOR_P" + ], + [ + "INT_INTERFACE_WW4END1", + "WW4END1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS17", + "LOGIC_OUTS17" + ], + [ + "INT_INTERFACE_NE4C1", + "NE6E1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX22", + "IMUX22" + ], + [ + "INT_INTERFACE_LOGIC_OUTS13", + "LOGIC_OUTS13" + ], + [ + "INT_INTERFACE_WW2END3", + "WW2END3" + ], + [ + "INT_INTERFACE_NW4A3", + "NW6A3" + ], + [ + "INT_INTERFACE_EL1BEG1", + "EL1BEG1" + ], + [ + "INT_INTERFACE_SW4A3", + "SW6A3" + ], + [ + "GTXE2_INT_INTERFACE_IMUX0", + "IMUX0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX14", + "IMUX14" + ], + [ + "INT_INTERFACE_NE4BEG0", + "NE6BEG0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX32", + "IMUX32" + ], + [ + "INT_INTERFACE_CLK0", + "CLK0" + ], + [ + "INT_INTERFACE_EE2A0", + "EE2A0" + ], + [ + "INT_INTERFACE_NE4BEG1", + "NE6BEG1" + ], + [ + "INT_INTERFACE_LH2", + "LH2" + ], + [ + "INT_INTERFACE_SW4END0", + "SW6END0" + ], + [ + "GTXE2_INT_INTERFACE_IMUX29", + "IMUX29" + ], + [ + "GTXE2_INT_INTERFACE_IMUX23", + "IMUX23" + ], + [ + "INT_INTERFACE_NE2A3", + "NE2A3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS9", + "LOGIC_OUTS9" + ], + [ + "INT_INTERFACE_NE2A1", + "NE2A1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX20", + "IMUX20" + ], + [ + "GTXE2_INT_INTERFACE_IMUX12", + "IMUX12" + ], + [ + "INT_INTERFACE_BYP2", + "BYP2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS11", + "LOGIC_OUTS11" + ], + [ + "GTXE2_INT_INTERFACE_IMUX45", + "IMUX45" + ], + [ + "INT_INTERFACE_WL1END1", + "WL1END1" + ], + [ + "INT_INTERFACE_WW2A0", + "WW2A0" + ], + [ + "INT_INTERFACE_EE4BEG1", + "EE4BEG1" + ], + [ + "INT_INTERFACE_WR1END1", + "WR1END1" + ], + [ + "INT_INTERFACE_EL1BEG2", + "EL1BEG2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS19", + "LOGIC_OUTS19" + ], + [ + "INT_INTERFACE_WW4B2", + "WW4B2" + ], + [ + "INT_INTERFACE_EE2BEG1", + "EE2BEG1" + ], + [ + "INT_INTERFACE_FAN0", + "FAN0" + ], + [ + "INT_INTERFACE_LH10", + "LH10" + ], + [ + "INT_INTERFACE_MONITOR_N", + "MONITOR_N" + ], + [ + "INT_INTERFACE_LH7", + "LH7" + ], + [ + "INT_INTERFACE_LH9", + "LH9" + ], + [ + "INT_INTERFACE_EE4A3", + "EE4A3" + ], + [ + "INT_INTERFACE_EE4BEG2", + "EE4BEG2" + ], + [ + "GTXE2_INT_INTERFACE_IMUX19", + "IMUX19" + ], + [ + "INT_INTERFACE_LOGIC_OUTS22", + "LOGIC_OUTS22" + ], + [ + "INT_INTERFACE_LOGIC_OUTS16", + "LOGIC_OUTS16" + ], + [ + "INT_INTERFACE_WW4C2", + "WW4C2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS20", + "LOGIC_OUTS20" + ], + [ + "INT_INTERFACE_NW4END0", + "NW6END0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS0", + "LOGIC_OUTS0" + ], + [ + "INT_INTERFACE_EE2A2", + "EE2A2" + ], + [ + "INT_INTERFACE_BYP6", + "BYP6" + ], + [ + "INT_INTERFACE_EE4C0", + "EE4C0" + ], + [ + "INT_INTERFACE_LH12", + "LH12" + ], + [ + "INT_INTERFACE_LH1", + "LH1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS1", + "LOGIC_OUTS1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS7", + "LOGIC_OUTS7" + ], + [ + "INT_INTERFACE_SE2A0", + "SE2A0" + ], + [ + "INT_INTERFACE_NW4END1", + "NW6END1" + ], + [ + "INT_INTERFACE_NE4C0", + "NE6E0" + ], + [ + "INT_INTERFACE_FAN1", + "FAN1" + ], + [ + "GTXE2_INT_INTERFACE_IMUX40", + "IMUX40" + ] + ], + "tile_types": [ + "GTX_INT_INTERFACE", + "INT_R" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "MONITOR_EE2A1_0", + "VFRAME_EE2A1" + ], + [ + "MONITOR_IMUX27_0", + "VFRAME_IMUX27" + ], + [ + "MONITOR_ER1BEG2_0", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_NW4END0_0", + "VFRAME_NW4END0" + ], + [ + "MONITOR_EE4A3_0", + "VFRAME_EE4A3" + ], + [ + "MONITOR_IMUX11_0", + "VFRAME_IMUX11" + ], + [ + "MONITOR_BYP1_0", + "VFRAME_BYP1" + ], + [ + "MONITOR_FAN3_0", + "VFRAME_FAN3" + ], + [ + "MONITOR_LH2_0", + "VFRAME_LH2" + ], + [ + "MONITOR_SW2A0_0", + "VFRAME_SW2A0" + ], + [ + "MONITOR_LH10_0", + "VFRAME_LH10" + ], + [ + "MONITOR_IMUX26_0", + "VFRAME_IMUX26" + ], + [ + "MONITOR_IMUX9_0", + "VFRAME_IMUX9" + ], + [ + "MONITOR_SW2A2_0", + "VFRAME_SW2A2" + ], + [ + "MONITOR_IMUX8_0", + "VFRAME_IMUX8" + ], + [ + "MONITOR_EE4BEG2_0", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_WW2END0_0", + "VFRAME_WW2END0" + ], + [ + "MONITOR_FAN6_0", + "VFRAME_FAN6" + ], + [ + "MONITOR_SW2A1_0", + "VFRAME_SW2A1" + ], + [ + "MONITOR_SW4A1_0", + "VFRAME_SW4A1" + ], + [ + "MONITOR_EE4BEG3_0", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_IMUX44_0", + "VFRAME_IMUX44" + ], + [ + "MONITOR_IMUX22_0", + "VFRAME_IMUX22" + ], + [ + "MONITOR_FAN2_0", + "VFRAME_FAN2" + ], + [ + "MONITOR_WW4A3_0", + "VFRAME_WW4A3" + ], + [ + "MONITOR_NW2A3_0", + "VFRAME_NW2A3" + ], + [ + "MONITOR_IMUX46_0", + "VFRAME_IMUX46" + ], + [ + "MONITOR_LOGIC_OUTS_B16_0", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "MONITOR_SW4END1_0", + "VFRAME_SW4END1" + ], + [ + "MONITOR_NE4BEG1_0", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_SE4BEG0_0", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_IMUX41_0", + "VFRAME_IMUX41" + ], + [ + "MONITOR_SW4END0_0", + "VFRAME_SW4END0" + ], + [ + "MONITOR_IMUX2_0", + "VFRAME_IMUX2" + ], + [ + "MONITOR_SW4END2_0", + "VFRAME_SW4END2" + ], + [ + "MONITOR_SE4BEG1_0", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_EE4C1_0", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX15_0", + "VFRAME_IMUX15" + ], + [ + "MONITOR_NE2A0_0", + "VFRAME_NE2A0" + ], + [ + "MONITOR_ER1BEG0_0", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_IMUX36_0", + "VFRAME_IMUX36" + ], + [ + "MONITOR_LOGIC_OUTS_B15_0", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "MONITOR_WW4B1_0", + "VFRAME_WW4B1" + ], + [ + "MONITOR_NW4END1_0", + "VFRAME_NW4END1" + ], + [ + "MONITOR_EE4A0_0", + "VFRAME_EE4A0" + ], + [ + "MONITOR_LH1_0", + "VFRAME_LH1" + ], + [ + "MONITOR_SE4C2_0", + "VFRAME_SE4C2" + ], + [ + "MONITOR_LH6_0", + "VFRAME_LH6" + ], + [ + "MONITOR_IMUX10_0", + "VFRAME_IMUX10" + ], + [ + "MONITOR_IMUX23_0", + "VFRAME_IMUX23" + ], + [ + "MONITOR_SE4C3_0", + "VFRAME_SE4C3" + ], + [ + "MONITOR_SW4END3_0", + "VFRAME_SW4END3" + ], + [ + "MONITOR_EE4A2_0", + "VFRAME_EE4A2" + ], + [ + "MONITOR_IMUX5_0", + "VFRAME_IMUX5" + ], + [ + "MONITOR_NE4BEG3_0", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_IMUX35_0", + "VFRAME_IMUX35" + ], + [ + "MONITOR_LOGIC_OUTS_B10_0", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "MONITOR_CLK0_0", + "VFRAME_CLK0" + ], + [ + "MONITOR_IMUX21_0", + "VFRAME_IMUX21" + ], + [ + "MONITOR_NE4C1_0", + "VFRAME_NE4C1" + ], + [ + "MONITOR_IMUX14_0", + "VFRAME_IMUX14" + ], + [ + "MONITOR_LH12_0", + "VFRAME_LH12" + ], + [ + "MONITOR_WW2A1_0", + "VFRAME_WW2A1" + ], + [ + "MONITOR_IMUX34_0", + "VFRAME_IMUX34" + ], + [ + "MONITOR_EE2A2_0", + "VFRAME_EE2A2" + ], + [ + "MONITOR_EE2BEG2_0", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_WL1END3_0", + "VFRAME_WL1END3" + ], + [ + "MONITOR_IMUX45_0", + "VFRAME_IMUX45" + ], + [ + "MONITOR_LOGIC_OUTS_B11_0", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "MONITOR_IMUX0_0", + "VFRAME_IMUX0" + ], + [ + "MONITOR_WW2END1_0", + "VFRAME_WW2END1" + ], + [ + "MONITOR_LOGIC_OUTS_B9_0", + "VFRAME_LOGIC_OUTS_B9" + ], + [ + "MONITOR_IMUX40_0", + "VFRAME_IMUX40" + ], + [ + "MONITOR_ER1BEG1_0", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_IMUX6_0", + "VFRAME_IMUX6" + ], + [ + "MONITOR_EE4C2_0", + "VFRAME_EE4C2" + ], + [ + "MONITOR_LOGIC_OUTS_B13_0", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "MONITOR_WW4END1_0", + "VFRAME_WW4END1" + ], + [ + "MONITOR_NW4A2_0", + "VFRAME_NW4A2" + ], + [ + "MONITOR_FAN0_0", + "VFRAME_FAN0" + ], + [ + "MONITOR_WW4C0_0", + "VFRAME_WW4C0" + ], + [ + "MONITOR_IMUX13_0", + "VFRAME_IMUX13" + ], + [ + "MONITOR_LOGIC_OUTS_B18_0", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "MONITOR_LOGIC_OUTS_B20_0", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "MONITOR_LOGIC_OUTS_B22_0", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "MONITOR_EE2A3_0", + "VFRAME_EE2A3" + ], + [ + "MONITOR_IMUX29_0", + "VFRAME_IMUX29" + ], + [ + "MONITOR_WW2A0_0", + "VFRAME_WW2A0" + ], + [ + "MONITOR_ER1BEG3_0", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_WW4C2_0", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE4A1_0", + "VFRAME_EE4A1" + ], + [ + "MONITOR_BYP3_0", + "VFRAME_BYP3" + ], + [ + "MONITOR_EE4BEG1_0", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_SW4A2_0", + "VFRAME_SW4A2" + ], + [ + "MONITOR_IMUX43_0", + "VFRAME_IMUX43" + ], + [ + "MONITOR_IMUX24_0", + "VFRAME_IMUX24" + ], + [ + "MONITOR_CTRL1_0", + "VFRAME_CTRL1" + ], + [ + "MONITOR_IMUX28_0", + "VFRAME_IMUX28" + ], + [ + "MONITOR_FAN5_0", + "VFRAME_FAN5" + ], + [ + "MONITOR_SE2A0_0", + "VFRAME_SE2A0" + ], + [ + "MONITOR_IMUX31_0", + "VFRAME_IMUX31" + ], + [ + "MONITOR_WW4B3_0", + "VFRAME_WW4B3" + ], + [ + "MONITOR_WW2A2_0", + "VFRAME_WW2A2" + ], + [ + "MONITOR_FAN7_0", + "VFRAME_FAN7" + ], + [ + "MONITOR_IMUX19_0", + "VFRAME_IMUX19" + ], + [ + "MONITOR_EE2BEG1_0", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_EE4C3_0", + "VFRAME_EE4C3" + ], + [ + "MONITOR_FAN4_0", + "VFRAME_FAN4" + ], + [ + "MONITOR_LOGIC_OUTS_B19_0", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "MONITOR_SE2A2_0", + "VFRAME_SE2A2" + ], + [ + "MONITOR_IMUX47_0", + "VFRAME_IMUX47" + ], + [ + "MONITOR_NE4C3_0", + "VFRAME_NE4C3" + ], + [ + "MONITOR_IMUX17_0", + "VFRAME_IMUX17" + ], + [ + "MONITOR_WL1END1_0", + "VFRAME_WL1END1" + ], + [ + "MONITOR_IMUX37_0", + "VFRAME_IMUX37" + ], + [ + "MONITOR_IMUX30_0", + "VFRAME_IMUX30" + ], + [ + "MONITOR_SW4A0_0", + "VFRAME_SW4A0" + ], + [ + "MONITOR_EE2BEG3_0", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_IMUX33_0", + "VFRAME_IMUX33" + ], + [ + "MONITOR_NW2A0_0", + "VFRAME_NW2A0" + ], + [ + "MONITOR_EE4BEG0_0", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_NW4A3_0", + "VFRAME_NW4A3" + ], + [ + "MONITOR_WR1END2_0", + "VFRAME_WR1END2" + ], + [ + "MONITOR_WW4END0_0", + "VFRAME_WW4END0" + ], + [ + "MONITOR_SW2A3_0", + "VFRAME_SW2A3" + ], + [ + "MONITOR_NW4END2_0", + "VFRAME_NW4END2" + ], + [ + "MONITOR_WW2A3_0", + "VFRAME_WW2A3" + ], + [ + "MONITOR_LH3_0", + "VFRAME_LH3" + ], + [ + "MONITOR_IMUX3_0", + "VFRAME_IMUX3" + ], + [ + "MONITOR_EL1BEG0_0", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_LOGIC_OUTS_B8_0", + "VFRAME_LOGIC_OUTS_B8" + ], + [ + "MONITOR_EE4C0_0", + "VFRAME_EE4C0" + ], + [ + "MONITOR_NE4BEG2_0", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_LOGIC_OUTS_B23_0", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "MONITOR_BYP0_0", + "VFRAME_BYP0" + ], + [ + "MONITOR_WW4A0_0", + "VFRAME_WW4A0" + ], + [ + "MONITOR_NE4C2_0", + "VFRAME_NE4C2" + ], + [ + "MONITOR_LOGIC_OUTS_B14_0", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "MONITOR_NE4BEG0_0", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_SE4BEG3_0", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_NE4C0_0", + "VFRAME_NE4C0" + ], + [ + "MONITOR_NW2A1_0", + "VFRAME_NW2A1" + ], + [ + "MONITOR_SE4C1_0", + "VFRAME_SE4C1" + ], + [ + "MONITOR_IMUX32_0", + "VFRAME_IMUX32" + ], + [ + "MONITOR_EE4B1_0", + "VFRAME_EE4B1" + ], + [ + "MONITOR_BYP7_0", + "VFRAME_BYP7" + ], + [ + "MONITOR_IMUX7_0", + "VFRAME_IMUX7" + ], + [ + "MONITOR_IMUX18_0", + "VFRAME_IMUX18" + ], + [ + "MONITOR_NW2A2_0", + "VFRAME_NW2A2" + ], + [ + "MONITOR_BYP4_0", + "VFRAME_BYP4" + ], + [ + "MONITOR_IMUX25_0", + "VFRAME_IMUX25" + ], + [ + "MONITOR_WW4B0_0", + "VFRAME_WW4B0" + ], + [ + "MONITOR_NE2A1_0", + "VFRAME_NE2A1" + ], + [ + "MONITOR_WW4C3_0", + "VFRAME_WW4C3" + ], + [ + "MONITOR_IMUX4_0", + "VFRAME_IMUX4" + ], + [ + "MONITOR_EE4B3_0", + "VFRAME_EE4B3" + ], + [ + "MONITOR_LH7_0", + "VFRAME_LH7" + ], + [ + "MONITOR_SE4BEG2_0", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_IMUX1_0", + "VFRAME_IMUX1" + ], + [ + "MONITOR_NW4A0_0", + "VFRAME_NW4A0" + ], + [ + "MONITOR_LH9_0", + "VFRAME_LH9" + ], + [ + "MONITOR_WL1END2_0", + "VFRAME_WL1END2" + ], + [ + "MONITOR_BYP5_0", + "VFRAME_BYP5" + ], + [ + "MONITOR_IMUX20_0", + "VFRAME_IMUX20" + ], + [ + "MONITOR_LOGIC_OUTS_B17_0", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "MONITOR_SE2A1_0", + "VFRAME_SE2A1" + ], + [ + "MONITOR_EE4B0_0", + "VFRAME_EE4B0" + ], + [ + "MONITOR_NE2A3_0", + "VFRAME_NE2A3" + ], + [ + "MONITOR_LH5_0", + "VFRAME_LH5" + ], + [ + "MONITOR_NE2A2_0", + "VFRAME_NE2A2" + ], + [ + "MONITOR_IMUX39_0", + "VFRAME_IMUX39" + ], + [ + "MONITOR_BYP6_0", + "VFRAME_BYP6" + ], + [ + "MONITOR_IMUX42_0", + "VFRAME_IMUX42" + ], + [ + "MONITOR_EE2BEG0_0", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_WW4A1_0", + "VFRAME_WW4A1" + ], + [ + "MONITOR_SW4A3_0", + "VFRAME_SW4A3" + ], + [ + "MONITOR_NW4A1_0", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WR1END3_0", + "VFRAME_WR1END3" + ], + [ + "MONITOR_EL1BEG3_0", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_WW4C1_0", + "VFRAME_WW4C1" + ], + [ + "MONITOR_IMUX12_0", + "VFRAME_IMUX12" + ], + [ + "MONITOR_WR1END1_0", + "VFRAME_WR1END1" + ], + [ + "MONITOR_IMUX38_0", + "VFRAME_IMUX38" + ], + [ + "MONITOR_SE2A3_0", + "VFRAME_SE2A3" + ], + [ + "MONITOR_LOGIC_OUTS_B21_0", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "MONITOR_LH4_0", + "VFRAME_LH4" + ], + [ + "MONITOR_FAN1_0", + "VFRAME_FAN1" + ], + [ + "MONITOR_NW4END3_0", + "VFRAME_NW4END3" + ], + [ + "MONITOR_EE4B2_0", + "VFRAME_EE4B2" + ], + [ + "MONITOR_LOGIC_OUTS_B12_0", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "MONITOR_BYP2_0", + "VFRAME_BYP2" + ], + [ + "MONITOR_LH11_0", + "VFRAME_LH11" + ], + [ + "MONITOR_CLK1_0", + "VFRAME_CLK1" + ], + [ + "MONITOR_CTRL0_0", + "VFRAME_CTRL0" + ], + [ + "MONITOR_LH8_0", + "VFRAME_LH8" + ], + [ + "MONITOR_WW4A2_0", + "VFRAME_WW4A2" + ], + [ + "MONITOR_WW4END3_0", + "VFRAME_WW4END3" + ], + [ + "MONITOR_EL1BEG1_0", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_WL1END0_0", + "VFRAME_WL1END0" + ], + [ + "MONITOR_SE4C0_0", + "VFRAME_SE4C0" + ], + [ + "MONITOR_WW4END2_0", + "VFRAME_WW4END2" + ], + [ + "MONITOR_IMUX16_0", + "VFRAME_IMUX16" + ], + [ + "MONITOR_WW2END3_0", + "VFRAME_WW2END3" + ], + [ + "MONITOR_WR1END0_0", + "VFRAME_WR1END0" + ], + [ + "MONITOR_EL1BEG2_0", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_WW2END2_0", + "VFRAME_WW2END2" + ], + [ + "MONITOR_WW4B2_0", + "VFRAME_WW4B2" + ], + [ + "MONITOR_EE2A0_0", + "VFRAME_EE2A0" + ] + ], + "tile_types": [ + "MONITOR_BOT_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "GTXE2_IMUX27_5", + "VBRK_EXT_IMUX27" + ], + [ + "GTXE2_IMUX13_5", + "VBRK_EXT_IMUX13" + ], + [ + "GTXE2_LOGIC_OUTS_B4_5", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTXE2_LOGIC_OUTS_B22_5", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTXE2_IMUX30_5", + "VBRK_EXT_IMUX30" + ], + [ + "GTXE2_LOGIC_OUTS_B14_5", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTXE2_IMUX0_5", + "VBRK_EXT_IMUX0" + ], + [ + "GTXE2_BYP4_5", + "VBRK_EXT_BYP4" + ], + [ + "GTXE2_IMUX18_5", + "VBRK_EXT_IMUX18" + ], + [ + "GTXE2_LOGIC_OUTS_B8_5", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTXE2_IMUX16_5", + "VBRK_EXT_IMUX16" + ], + [ + "GTXE2_IMUX42_5", + "VBRK_EXT_IMUX42" + ], + [ + "GTXE2_IMUX46_5", + "VBRK_EXT_IMUX46" + ], + [ + "GTXE2_IMUX11_5", + "VBRK_EXT_IMUX11" + ], + [ + "GTXE2_IMUX6_5", + "VBRK_EXT_IMUX6" + ], + [ + "GTXE2_LOGIC_OUTS_B9_5", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTXE2_IMUX7_5", + "VBRK_EXT_IMUX7" + ], + [ + "GTXE2_IMUX45_5", + "VBRK_EXT_IMUX45" + ], + [ + "GTXE2_BYP0_5", + "VBRK_EXT_BYP0" + ], + [ + "GTXE2_IMUX33_5", + "VBRK_EXT_IMUX33" + ], + [ + "GTXE2_IMUX38_5", + "VBRK_EXT_IMUX38" + ], + [ + "GTXE2_LOGIC_OUTS_B11_5", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTXE2_BYP2_5", + "VBRK_EXT_BYP2" + ], + [ + "GTXE2_IMUX23_5", + "VBRK_EXT_IMUX23" + ], + [ + "GTXE2_LOGIC_OUTS_B6_5", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTXE2_LOGIC_OUTS_B2_5", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTXE2_IMUX41_5", + "VBRK_EXT_IMUX41" + ], + [ + "GTXE2_LOGIC_OUTS_B5_5", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTXE2_IMUX12_5", + "VBRK_EXT_IMUX12" + ], + [ + "GTXE2_IMUX14_5", + "VBRK_EXT_IMUX14" + ], + [ + "GTXE2_IMUX22_5", + "VBRK_EXT_IMUX22" + ], + [ + "GTXE2_CLK0_5", + "VBRK_EXT_CLK0" + ], + [ + "GTXE2_IMUX43_5", + "VBRK_EXT_IMUX43" + ], + [ + "GTXE2_IMUX37_5", + "VBRK_EXT_IMUX37" + ], + [ + "GTXE2_IMUX9_5", + "VBRK_EXT_IMUX9" + ], + [ + "GTXE2_IMUX29_5", + "VBRK_EXT_IMUX29" + ], + [ + "GTXE2_BYP1_5", + "VBRK_EXT_BYP1" + ], + [ + "GTXE2_CTRL1_5", + "VBRK_EXT_CTRL1" + ], + [ + "GTXE2_CLK1_5", + "VBRK_EXT_CLK1" + ], + [ + "GTXE2_CTRL0_5", + "VBRK_EXT_CTRL0" + ], + [ + "GTXE2_IMUX28_5", + "VBRK_EXT_IMUX28" + ], + [ + "GTXE2_IMUX32_5", + "VBRK_EXT_IMUX32" + ], + [ + "GTXE2_IMUX17_5", + "VBRK_EXT_IMUX17" + ], + [ + "GTXE2_FAN6_5", + "VBRK_EXT_FAN6" + ], + [ + "GTXE2_BYP5_5", + "VBRK_EXT_BYP5" + ], + [ + "GTXE2_LOGIC_OUTS_B7_5", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTXE2_LOGIC_OUTS_B17_5", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTXE2_IMUX1_5", + "VBRK_EXT_IMUX1" + ], + [ + "GTXE2_IMUX26_5", + "VBRK_EXT_IMUX26" + ], + [ + "GTXE2_FAN0_5", + "VBRK_EXT_FAN0" + ], + [ + "GTXE2_IMUX8_5", + "VBRK_EXT_IMUX8" + ], + [ + "GTXE2_LOGIC_OUTS_B16_5", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTXE2_IMUX4_5", + "VBRK_EXT_IMUX4" + ], + [ + "GTXE2_BYP7_5", + "VBRK_EXT_BYP7" + ], + [ + "GTXE2_LOGIC_OUTS_B3_5", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTXE2_IMUX35_5", + "VBRK_EXT_IMUX35" + ], + [ + "GTXE2_IMUX39_5", + "VBRK_EXT_IMUX39" + ], + [ + "GTXE2_LOGIC_OUTS_B18_5", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTXE2_LOGIC_OUTS_B12_5", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTXE2_IMUX19_5", + "VBRK_EXT_IMUX19" + ], + [ + "GTXE2_FAN7_5", + "VBRK_EXT_FAN7" + ], + [ + "GTXE2_LOGIC_OUTS_B13_5", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTXE2_LOGIC_OUTS_B23_5", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTXE2_LOGIC_OUTS_B0_5", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTXE2_IMUX36_5", + "VBRK_EXT_IMUX36" + ], + [ + "GTXE2_IMUX2_5", + "VBRK_EXT_IMUX2" + ], + [ + "GTXE2_IMUX40_5", + "VBRK_EXT_IMUX40" + ], + [ + "GTXE2_FAN3_5", + "VBRK_EXT_FAN3" + ], + [ + "GTXE2_IMUX3_5", + "VBRK_EXT_IMUX3" + ], + [ + "GTXE2_IMUX10_5", + "VBRK_EXT_IMUX10" + ], + [ + "GTXE2_FAN5_5", + "VBRK_EXT_FAN5" + ], + [ + "GTXE2_IMUX34_5", + "VBRK_EXT_IMUX34" + ], + [ + "GTXE2_IMUX20_5", + "VBRK_EXT_IMUX20" + ], + [ + "GTXE2_FAN4_5", + "VBRK_EXT_FAN4" + ], + [ + "GTXE2_IMUX24_5", + "VBRK_EXT_IMUX24" + ], + [ + "GTXE2_LOGIC_OUTS_B10_5", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTXE2_BYP3_5", + "VBRK_EXT_BYP3" + ], + [ + "GTXE2_LOGIC_OUTS_B15_5", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTXE2_IMUX31_5", + "VBRK_EXT_IMUX31" + ], + [ + "GTXE2_FAN1_5", + "VBRK_EXT_FAN1" + ], + [ + "GTXE2_FAN2_5", + "VBRK_EXT_FAN2" + ], + [ + "GTXE2_LOGIC_OUTS_B20_5", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTXE2_IMUX5_5", + "VBRK_EXT_IMUX5" + ], + [ + "GTXE2_BYP6_5", + "VBRK_EXT_BYP6" + ], + [ + "GTXE2_IMUX47_5", + "VBRK_EXT_IMUX47" + ], + [ + "GTXE2_IMUX15_5", + "VBRK_EXT_IMUX15" + ], + [ + "GTXE2_IMUX25_5", + "VBRK_EXT_IMUX25" + ], + [ + "GTXE2_IMUX21_5", + "VBRK_EXT_IMUX21" + ], + [ + "GTXE2_IMUX44_5", + "VBRK_EXT_IMUX44" + ], + [ + "GTXE2_LOGIC_OUTS_B19_5", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTXE2_LOGIC_OUTS_B1_5", + "VBRK_EXT_LOGIC_OUTS_B1" + ] + ], + "tile_types": [ + "GTX_CHANNEL_1", + "VBRK_EXT" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "CMT_FIFO_L_IMUX18_7", + "INT_INTERFACE_IMUX18" + ], + [ + "CMT_FIFO_SE4C0_7", + "INT_INTERFACE_SE4C0" + ], + [ + "CMT_FIFO_L_IMUX45_7", + "INT_INTERFACE_IMUX45" + ], + [ + "CMT_FIFO_SW4A3_7", + "INT_INTERFACE_SW4A3" + ], + [ + "CMT_FIFO_EE4C0_7", + "INT_INTERFACE_EE4C0" + ], + [ + "CMT_FIFO_WW4A2_7", + "INT_INTERFACE_WW4A2" + ], + [ + "CMT_FIFO_SW2A1_7", + "INT_INTERFACE_SW2A1" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS4_7", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "CMT_FIFO_L_IMUX17_7", + "INT_INTERFACE_IMUX17" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS21_7", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "INT_INTERFACE_PHASER_TO_IO_OCLK" + ], + [ + "CMT_FIFO_SW2A2_7", + "INT_INTERFACE_SW2A2" + ], + [ + "CMT_FIFO_L_IMUX13_7", + "INT_INTERFACE_IMUX13" + ], + [ + "CMT_FIFO_SE4BEG3_7", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CMT_FIFO_WL1END0_7", + "INT_INTERFACE_WL1END0" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "CMT_FIFO_EE2BEG3_7", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CMT_FIFO_L_BYP3_7", + "INT_INTERFACE_BYP3" + ], + [ + "CMT_FIFO_NE4C2_7", + "INT_INTERFACE_NE4C2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS10_7", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "CMT_FIFO_NW2A3_7", + "INT_INTERFACE_NW2A3" + ], + [ + "CMT_FIFO_L_IMUX34_7", + "INT_INTERFACE_IMUX34" + ], + [ + "CMT_FIFO_L_FAN4_7", + "INT_INTERFACE_FAN4" + ], + [ + "CMT_FIFO_WR1END0_7", + "INT_INTERFACE_WR1END0" + ], + [ + "CMT_FIFO_SE4BEG1_7", + "INT_INTERFACE_SE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX23_7", + "INT_INTERFACE_IMUX23" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS11_7", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS12_7", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "CMT_FIFO_WL1END1_7", + "INT_INTERFACE_WL1END1" + ], + [ + "CMT_FIFO_WL1END2_7", + "INT_INTERFACE_WL1END2" + ], + [ + "CMT_FIFO_SE4BEG0_7", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CMT_FIFO_WW2A3_7", + "INT_INTERFACE_WW2A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS9_7", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "CMT_FIFO_LH3_7", + "INT_INTERFACE_LH3" + ], + [ + "CMT_FIFO_EE2A1_7", + "INT_INTERFACE_EE2A1" + ], + [ + "CMT_FIFO_L_IMUX29_7", + "INT_INTERFACE_IMUX29" + ], + [ + "CMT_FIFO_WW4B1_7", + "INT_INTERFACE_WW4B1" + ], + [ + "CMT_FIFO_L_IMUX39_7", + "INT_INTERFACE_IMUX39" + ], + [ + "CMT_FIFO_WW4A0_7", + "INT_INTERFACE_WW4A0" + ], + [ + "CMT_FIFO_NE4C1_7", + "INT_INTERFACE_NE4C1" + ], + [ + "CMT_FIFO_EE4BEG0_7", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CMT_FIFO_L_FAN1_7", + "INT_INTERFACE_FAN1" + ], + [ + "CMT_FIFO_LH8_7", + "INT_INTERFACE_LH8" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS17_7", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "CMT_FIFO_L_BYP2_7", + "INT_INTERFACE_BYP2" + ], + [ + "CMT_FIFO_NW4A3_7", + "INT_INTERFACE_NW4A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS1_7", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "CMT_FIFO_NW4A1_7", + "INT_INTERFACE_NW4A1" + ], + [ + "CMT_FIFO_L_FAN0_7", + "INT_INTERFACE_FAN0" + ], + [ + "CMT_FIFO_LH7_7", + "INT_INTERFACE_LH7" + ], + [ + "CMT_FIFO_WW4C2_7", + "INT_INTERFACE_WW4C2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS16_7", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "CMT_FIFO_EE4A0_7", + "INT_INTERFACE_EE4A0" + ], + [ + "CMT_FIFO_SW2A3_7", + "INT_INTERFACE_SW2A3" + ], + [ + "CMT_FIFO_L_BYP5_7", + "INT_INTERFACE_BYP5" + ], + [ + "CMT_FIFO_L_IMUX8_7", + "INT_INTERFACE_IMUX8" + ], + [ + "CMT_FIFO_EE2A2_7", + "INT_INTERFACE_EE2A2" + ], + [ + "CMT_FIFO_L_BYP7_7", + "INT_INTERFACE_BYP7" + ], + [ + "CMT_FIFO_EE4A1_7", + "INT_INTERFACE_EE4A1" + ], + [ + "CMT_FIFO_SW4A2_7", + "INT_INTERFACE_SW4A2" + ], + [ + "CMT_FIFO_SE4C3_7", + "INT_INTERFACE_SE4C3" + ], + [ + "CMT_FIFO_EL1BEG1_7", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CMT_FIFO_L_IMUX3_7", + "INT_INTERFACE_IMUX3" + ], + [ + "CMT_FIFO_NE2A3_7", + "INT_INTERFACE_NE2A3" + ], + [ + "CMT_FIFO_NE2A1_7", + "INT_INTERFACE_NE2A1" + ], + [ + "CMT_FIFO_L_IMUX26_7", + "INT_INTERFACE_IMUX26" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS8_7", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "CMT_FIFO_WW4END2_7", + "INT_INTERFACE_WW4END2" + ], + [ + "CMT_FIFO_EE4C3_7", + "INT_INTERFACE_EE4C3" + ], + [ + "CMT_FIFO_EE4BEG1_7", + "INT_INTERFACE_EE4BEG1" + ], + [ + "CMT_FIFO_L_IMUX33_7", + "INT_INTERFACE_IMUX33" + ], + [ + "CMT_FIFO_EL1BEG3_7", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CMT_FIFO_SE4C1_7", + "INT_INTERFACE_SE4C1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + ], + [ + "CMT_FIFO_NW4A0_7", + "INT_INTERFACE_NW4A0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS7_7", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "CMT_FIFO_EE4BEG2_7", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CMT_FIFO_WW4END0_7", + "INT_INTERFACE_WW4END0" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS22_7", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "CMT_FIFO_EE4B2_7", + "INT_INTERFACE_EE4B2" + ], + [ + "CMT_FIFO_L_IMUX42_7", + "INT_INTERFACE_IMUX42" + ], + [ + "CMT_FIFO_L_CTRL0_7", + "INT_INTERFACE_CTRL0" + ], + [ + "CMT_FIFO_L_IMUX1_7", + "INT_INTERFACE_IMUX1" + ], + [ + "CMT_FIFO_EE4A3_7", + "INT_INTERFACE_EE4A3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS23_7", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "CMT_FIFO_L_IMUX12_7", + "INT_INTERFACE_IMUX12" + ], + [ + "CMT_FIFO_EE4BEG3_7", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CMT_FIFO_WR1END3_7", + "INT_INTERFACE_WR1END3" + ], + [ + "CMT_FIFO_WW4C1_7", + "INT_INTERFACE_WW4C1" + ], + [ + "CMT_FIFO_SE2A0_7", + "INT_INTERFACE_SE2A0" + ], + [ + "CMT_FIFO_WW4B2_7", + "INT_INTERFACE_WW4B2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS5_7", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "CMT_FIFO_EE4B3_7", + "INT_INTERFACE_EE4B3" + ], + [ + "CMT_FIFO_EL1BEG2_7", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CMT_FIFO_WW4C3_7", + "INT_INTERFACE_WW4C3" + ], + [ + "CMT_FIFO_L_CTRL1_7", + "INT_INTERFACE_CTRL1" + ], + [ + "CMT_FIFO_L_FAN7_7", + "INT_INTERFACE_FAN7" + ], + [ + "CMT_FIFO_NW4END1_7", + "INT_INTERFACE_NW4END1" + ], + [ + "CMT_FIFO_L_IMUX35_7", + "INT_INTERFACE_IMUX35" + ], + [ + "CMT_FIFO_WW4END3_7", + "INT_INTERFACE_WW4END3" + ], + [ + "CMT_FIFO_EE4B1_7", + "INT_INTERFACE_EE4B1" + ], + [ + "CMT_FIFO_NW2A1_7", + "INT_INTERFACE_NW2A1" + ], + [ + "CMT_FIFO_WR1END1_7", + "INT_INTERFACE_WR1END1" + ], + [ + "CMT_FIFO_SE2A1_7", + "INT_INTERFACE_SE2A1" + ], + [ + "CMT_FIFO_WW4B0_7", + "INT_INTERFACE_WW4B0" + ], + [ + "CMT_FIFO_WW4C0_7", + "INT_INTERFACE_WW4C0" + ], + [ + "CMT_FIFO_WL1END3_7", + "INT_INTERFACE_WL1END3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS14_7", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "CMT_FIFO_L_IMUX47_7", + "INT_INTERFACE_IMUX47" + ], + [ + "CMT_FIFO_L_IMUX7_7", + "INT_INTERFACE_IMUX7" + ], + [ + "CMT_FIFO_L_IMUX5_7", + "INT_INTERFACE_IMUX5" + ], + [ + "CMT_FIFO_L_IMUX40_7", + "INT_INTERFACE_IMUX40" + ], + [ + "CMT_FIFO_L_IMUX21_7", + "INT_INTERFACE_IMUX21" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS13_7", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "CMT_FIFO_WW4A3_7", + "INT_INTERFACE_WW4A3" + ], + [ + "CMT_FIFO_SW4A1_7", + "INT_INTERFACE_SW4A1" + ], + [ + "CMT_FIFO_NW2A2_7", + "INT_INTERFACE_NW2A2" + ], + [ + "CMT_FIFO_L_IMUX37_7", + "INT_INTERFACE_IMUX37" + ], + [ + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "INT_INTERFACE_PHASER_TO_IO_ICLK" + ], + [ + "CMT_FIFO_EE4C2_7", + "INT_INTERFACE_EE4C2" + ], + [ + "CMT_FIFO_EE4C1_7", + "INT_INTERFACE_EE4C1" + ], + [ + "CMT_FIFO_SE4BEG2_7", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CMT_FIFO_LH12_7", + "INT_INTERFACE_LH12" + ], + [ + "CMT_FIFO_NW4END0_7", + "INT_INTERFACE_NW4END0" + ], + [ + "CMT_FIFO_WW4END1_7", + "INT_INTERFACE_WW4END1" + ], + [ + "CMT_FIFO_L_IMUX25_7", + "INT_INTERFACE_IMUX25" + ], + [ + "CMT_FIFO_L_IMUX22_7", + "INT_INTERFACE_IMUX22" + ], + [ + "CMT_FIFO_L_IMUX15_7", + "INT_INTERFACE_IMUX15" + ], + [ + "CMT_FIFO_L_IMUX46_7", + "INT_INTERFACE_IMUX46" + ], + [ + "CMT_FIFO_NW2A0_7", + "INT_INTERFACE_NW2A0" + ], + [ + "CMT_FIFO_NE4BEG2_7", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CMT_FIFO_L_IMUX0_7", + "INT_INTERFACE_IMUX0" + ], + [ + "CMT_FIFO_L_IMUX19_7", + "INT_INTERFACE_IMUX19" + ], + [ + "CMT_FIFO_L_BYP0_7", + "INT_INTERFACE_BYP0" + ], + [ + "CMT_FIFO_LH5_7", + "INT_INTERFACE_LH5" + ], + [ + "CMT_FIFO_SW4END2_7", + "INT_INTERFACE_SW4END2" + ], + [ + "CMT_FIFO_WW2A1_7", + "INT_INTERFACE_WW2A1" + ], + [ + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90" + ], + [ + "CMT_FIFO_L_FAN6_7", + "INT_INTERFACE_FAN6" + ], + [ + "CMT_FIFO_NW4A2_7", + "INT_INTERFACE_NW4A2" + ], + [ + "CMT_FIFO_L_FAN5_7", + "INT_INTERFACE_FAN5" + ], + [ + "CMT_FIFO_L_IMUX41_7", + "INT_INTERFACE_IMUX41" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS0_7", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "CMT_FIFO_EE2A0_7", + "INT_INTERFACE_EE2A0" + ], + [ + "CMT_FIFO_ER1BEG3_7", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CMT_FIFO_LH9_7", + "INT_INTERFACE_LH9" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS20_7", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "CMT_FIFO_L_BYP6_7", + "INT_INTERFACE_BYP6" + ], + [ + "CMT_FIFO_L_IMUX4_7", + "INT_INTERFACE_IMUX4" + ], + [ + "CMT_FIFO_ER1BEG2_7", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CMT_FIFO_LH6_7", + "INT_INTERFACE_LH6" + ], + [ + "CMT_FIFO_WW2A0_7", + "INT_INTERFACE_WW2A0" + ], + [ + "CMT_FIFO_WR1END2_7", + "INT_INTERFACE_WR1END2" + ], + [ + "CMT_FIFO_EE2BEG0_7", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CMT_FIFO_L_IMUX28_7", + "INT_INTERFACE_IMUX28" + ], + [ + "CMT_FIFO_LH4_7", + "INT_INTERFACE_LH4" + ], + [ + "CMT_FIFO_L_IMUX44_7", + "INT_INTERFACE_IMUX44" + ], + [ + "CMT_FIFO_L_IMUX38_7", + "INT_INTERFACE_IMUX38" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS3_7", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "CMT_FIFO_L_IMUX30_7", + "INT_INTERFACE_IMUX30" + ], + [ + "CMT_FIFO_SW4END1_7", + "INT_INTERFACE_SW4END1" + ], + [ + "CMT_FIFO_SW2A0_7", + "INT_INTERFACE_SW2A0" + ], + [ + "CMT_FIFO_NE4BEG1_7", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CMT_FIFO_ER1BEG0_7", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CMT_FIFO_ER1BEG1_7", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CMT_FIFO_L_IMUX32_7", + "INT_INTERFACE_IMUX32" + ], + [ + "CMT_FIFO_L_CLK1_7", + "INT_INTERFACE_CLK1" + ], + [ + "CMT_FIFO_L_FAN3_7", + "INT_INTERFACE_FAN3" + ], + [ + "CMT_FIFO_WW2END1_7", + "INT_INTERFACE_WW2END1" + ], + [ + "CMT_FIFO_L_IMUX20_7", + "INT_INTERFACE_IMUX20" + ], + [ + "CMT_FIFO_SE2A3_7", + "INT_INTERFACE_SE2A3" + ], + [ + "CMT_FIFO_EE2BEG1_7", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CMT_FIFO_SW4END0_7", + "INT_INTERFACE_SW4END0" + ], + [ + "CMT_FIFO_SW4A0_7", + "INT_INTERFACE_SW4A0" + ], + [ + "CMT_FIFO_LH2_7", + "INT_INTERFACE_LH2" + ], + [ + "CMT_FIFO_WW4B3_7", + "INT_INTERFACE_WW4B3" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS19_7", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "CMT_FIFO_EE4B0_7", + "INT_INTERFACE_EE4B0" + ], + [ + "CMT_FIFO_L_BYP1_7", + "INT_INTERFACE_BYP1" + ], + [ + "CMT_FIFO_EE2BEG2_7", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CMT_FIFO_WW2END3_7", + "INT_INTERFACE_WW2END3" + ], + [ + "CMT_FIFO_L_IMUX6_7", + "INT_INTERFACE_IMUX6" + ], + [ + "CMT_FIFO_SW4END3_7", + "INT_INTERFACE_SW4END3" + ], + [ + "CMT_FIFO_L_IMUX31_7", + "INT_INTERFACE_IMUX31" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS6_7", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "CMT_FIFO_WW2A2_7", + "INT_INTERFACE_WW2A2" + ], + [ + "CMT_FIFO_L_IMUX36_7", + "INT_INTERFACE_IMUX36" + ], + [ + "CMT_FIFO_LH11_7", + "INT_INTERFACE_LH11" + ], + [ + "CMT_FIFO_L_FAN2_7", + "INT_INTERFACE_FAN2" + ], + [ + "CMT_FIFO_NE2A0_7", + "INT_INTERFACE_NE2A0" + ], + [ + "CMT_FIFO_L_IMUX14_7", + "INT_INTERFACE_IMUX14" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS18_7", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "CMT_FIFO_L_IMUX43_7", + "INT_INTERFACE_IMUX43" + ], + [ + "CMT_FIFO_NE4C0_7", + "INT_INTERFACE_NE4C0" + ], + [ + "CMT_FIFO_L_CLK0_7", + "INT_INTERFACE_CLK0" + ], + [ + "CMT_FIFO_SE2A2_7", + "INT_INTERFACE_SE2A2" + ], + [ + "CMT_FIFO_L_IMUX10_7", + "INT_INTERFACE_IMUX10" + ], + [ + "CMT_FIFO_L_BYP4_7", + "INT_INTERFACE_BYP4" + ], + [ + "CMT_FIFO_WW2END2_7", + "INT_INTERFACE_WW2END2" + ], + [ + "CMT_FIFO_NE4C3_7", + "INT_INTERFACE_NE4C3" + ], + [ + "CMT_FIFO_L_IMUX27_7", + "INT_INTERFACE_IMUX27" + ], + [ + "CMT_FIFO_L_IMUX24_7", + "INT_INTERFACE_IMUX24" + ], + [ + "CMT_FIFO_EE4A2_7", + "INT_INTERFACE_EE4A2" + ], + [ + "CMT_FIFO_SE4C2_7", + "INT_INTERFACE_SE4C2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS15_7", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "CMT_FIFO_WW2END0_7", + "INT_INTERFACE_WW2END0" + ], + [ + "CMT_FIFO_L_IMUX9_7", + "INT_INTERFACE_IMUX9" + ], + [ + "CMT_FIFO_L_IMUX11_7", + "INT_INTERFACE_IMUX11" + ], + [ + "CMT_FIFO_L_IMUX2_7", + "INT_INTERFACE_IMUX2" + ], + [ + "CMT_FIFO_LH1_7", + "INT_INTERFACE_LH1" + ], + [ + "CMT_FIFO_NW4END3_7", + "INT_INTERFACE_NW4END3" + ], + [ + "CMT_FIFO_WW4A1_7", + "INT_INTERFACE_WW4A1" + ], + [ + "CMT_FIFO_NW4END2_7", + "INT_INTERFACE_NW4END2" + ], + [ + "CMT_FIFO_L_LOGIC_OUTS2_7", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "CMT_FIFO_EL1BEG0_7", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CMT_FIFO_NE4BEG3_7", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CMT_FIFO_NE4BEG0_7", + "INT_INTERFACE_NE4BEG0" + ], + [ + "CMT_FIFO_L_IMUX16_7", + "INT_INTERFACE_IMUX16" + ], + [ + "CMT_FIFO_LH10_7", + "INT_INTERFACE_LH10" + ], + [ + "CMT_FIFO_EE2A3_7", + "INT_INTERFACE_EE2A3" + ], + [ + "CMT_FIFO_NE2A2_7", + "INT_INTERFACE_NE2A2" + ] + ], + "tile_types": [ + "CMT_FIFO_R", + "INT_INTERFACE_R" + ] + }, + { + "grid_deltas": [ + 1, + -7 + ], + "wire_pairs": [ + [ + "MONITOR_NW4A0_7", + "VFRAME_NW4A0" + ], + [ + "MONITOR_IMUX25_7", + "VFRAME_IMUX25" + ], + [ + "MONITOR_EE4A2_7", + "VFRAME_EE4A2" + ], + [ + "MONITOR_FAN6_7", + "VFRAME_FAN6" + ], + [ + "MONITOR_SE4BEG1_7", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_LH1_7", + "VFRAME_LH1" + ], + [ + "MONITOR_IMUX20_7", + "VFRAME_IMUX20" + ], + [ + "MONITOR_WW2A3_7", + "VFRAME_WW2A3" + ], + [ + "MONITOR_BYP1_7", + "VFRAME_BYP1" + ], + [ + "MONITOR_WW4B1_7", + "VFRAME_WW4B1" + ], + [ + "MONITOR_NE2A3_7", + "VFRAME_NE2A3" + ], + [ + "MONITOR_NW2A2_7", + "VFRAME_NW2A2" + ], + [ + "MONITOR_EE2BEG1_7", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_EE4BEG3_7", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_IMUX43_7", + "VFRAME_IMUX43" + ], + [ + "MONITOR_LH5_7", + "VFRAME_LH5" + ], + [ + "MONITOR_IMUX24_7", + "VFRAME_IMUX24" + ], + [ + "MONITOR_SE4C0_7", + "VFRAME_SE4C0" + ], + [ + "MONITOR_ER1BEG1_7", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_EE4B0_7", + "VFRAME_EE4B0" + ], + [ + "MONITOR_IMUX35_7", + "VFRAME_IMUX35" + ], + [ + "MONITOR_CTRL1_7", + "VFRAME_CTRL1" + ], + [ + "MONITOR_SE4BEG0_7", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_IMUX22_7", + "VFRAME_IMUX22" + ], + [ + "MONITOR_NW2A0_7", + "VFRAME_NW2A0" + ], + [ + "MONITOR_EE4B2_7", + "VFRAME_EE4B2" + ], + [ + "MONITOR_EL1BEG1_7", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_SE4BEG2_7", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_IMUX42_7", + "VFRAME_IMUX42" + ], + [ + "MONITOR_WL1END2_7", + "VFRAME_WL1END2" + ], + [ + "MONITOR_EE4B3_7", + "VFRAME_EE4B3" + ], + [ + "MONITOR_SW2A3_7", + "VFRAME_SW2A3" + ], + [ + "MONITOR_LH10_7", + "VFRAME_LH10" + ], + [ + "MONITOR_LH12_7", + "VFRAME_LH12" + ], + [ + "MONITOR_CTRL0_7", + "VFRAME_CTRL0" + ], + [ + "MONITOR_IMUX7_7", + "VFRAME_IMUX7" + ], + [ + "MONITOR_EE2BEG0_7", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_NE2A2_7", + "VFRAME_NE2A2" + ], + [ + "MONITOR_BYP5_7", + "VFRAME_BYP5" + ], + [ + "MONITOR_EE2A1_7", + "VFRAME_EE2A1" + ], + [ + "MONITOR_NE4C1_7", + "VFRAME_NE4C1" + ], + [ + "MONITOR_WW4B3_7", + "VFRAME_WW4B3" + ], + [ + "MONITOR_IMUX14_7", + "VFRAME_IMUX14" + ], + [ + "MONITOR_IMUX36_7", + "VFRAME_IMUX36" + ], + [ + "MONITOR_EE4C0_7", + "VFRAME_EE4C0" + ], + [ + "MONITOR_SE2A0_7", + "VFRAME_SE2A0" + ], + [ + "MONITOR_IMUX32_7", + "VFRAME_IMUX32" + ], + [ + "MONITOR_SE2A1_7", + "VFRAME_SE2A1" + ], + [ + "MONITOR_NE4BEG0_7", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_BYP6_7", + "VFRAME_BYP6" + ], + [ + "MONITOR_IMUX15_7", + "VFRAME_IMUX15" + ], + [ + "MONITOR_EE4BEG2_7", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_IMUX18_7", + "VFRAME_IMUX18" + ], + [ + "MONITOR_NE2A1_7", + "VFRAME_NE2A1" + ], + [ + "MONITOR_NW4A1_7", + "VFRAME_NW4A1" + ], + [ + "MONITOR_WR1END0_7", + "VFRAME_WR1END0" + ], + [ + "MONITOR_WW4A3_7", + "VFRAME_WW4A3" + ], + [ + "MONITOR_WW4END3_7", + "VFRAME_WW4END3" + ], + [ + "MONITOR_NW4END0_7", + "VFRAME_NW4END0" + ], + [ + "MONITOR_IMUX23_7", + "VFRAME_IMUX23" + ], + [ + "MONITOR_SW4END3_7", + "VFRAME_SW4END3" + ], + [ + "MONITOR_NW4A2_7", + "VFRAME_NW4A2" + ], + [ + "MONITOR_IMUX26_7", + "VFRAME_IMUX26" + ], + [ + "MONITOR_IMUX46_7", + "VFRAME_IMUX46" + ], + [ + "MONITOR_WW2END3_7", + "VFRAME_WW2END3" + ], + [ + "MONITOR_NW4END1_7", + "VFRAME_NW4END1" + ], + [ + "MONITOR_IMUX30_7", + "VFRAME_IMUX30" + ], + [ + "MONITOR_SW4END0_7", + "VFRAME_SW4END0" + ], + [ + "MONITOR_WW4B2_7", + "VFRAME_WW4B2" + ], + [ + "MONITOR_WW4A1_7", + "VFRAME_WW4A1" + ], + [ + "MONITOR_EE2A3_7", + "VFRAME_EE2A3" + ], + [ + "MONITOR_EE4BEG1_7", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_NE4BEG3_7", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_NE4BEG2_7", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_SE2A2_7", + "VFRAME_SE2A2" + ], + [ + "MONITOR_WL1END0_7", + "VFRAME_WL1END0" + ], + [ + "MONITOR_IMUX12_7", + "VFRAME_IMUX12" + ], + [ + "MONITOR_IMUX16_7", + "VFRAME_IMUX16" + ], + [ + "MONITOR_IMUX37_7", + "VFRAME_IMUX37" + ], + [ + "MONITOR_WW4A0_7", + "VFRAME_WW4A0" + ], + [ + "MONITOR_SW4A0_7", + "VFRAME_SW4A0" + ], + [ + "MONITOR_EE4B1_7", + "VFRAME_EE4B1" + ], + [ + "MONITOR_CLK1_7", + "VFRAME_CLK1" + ], + [ + "MONITOR_WW4C1_7", + "VFRAME_WW4C1" + ], + [ + "MONITOR_IMUX27_7", + "VFRAME_IMUX27" + ], + [ + "MONITOR_NE4C3_7", + "VFRAME_NE4C3" + ], + [ + "MONITOR_BYP2_7", + "VFRAME_BYP2" + ], + [ + "MONITOR_WW4C2_7", + "VFRAME_WW4C2" + ], + [ + "MONITOR_IMUX29_7", + "VFRAME_IMUX29" + ], + [ + "MONITOR_EE4C3_7", + "VFRAME_EE4C3" + ], + [ + "MONITOR_FAN2_7", + "VFRAME_FAN2" + ], + [ + "MONITOR_EE4A1_7", + "VFRAME_EE4A1" + ], + [ + "MONITOR_SW2A0_7", + "VFRAME_SW2A0" + ], + [ + "MONITOR_FAN7_7", + "VFRAME_FAN7" + ], + [ + "MONITOR_FAN5_7", + "VFRAME_FAN5" + ], + [ + "MONITOR_ER1BEG3_7", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_CLK0_7", + "VFRAME_CLK0" + ], + [ + "MONITOR_BYP0_7", + "VFRAME_BYP0" + ], + [ + "MONITOR_WR1END3_7", + "VFRAME_WR1END3" + ], + [ + "MONITOR_SE4C3_7", + "VFRAME_SE4C3" + ], + [ + "MONITOR_IMUX11_7", + "VFRAME_IMUX11" + ], + [ + "MONITOR_LH6_7", + "VFRAME_LH6" + ], + [ + "MONITOR_IMUX38_7", + "VFRAME_IMUX38" + ], + [ + "MONITOR_IMUX17_7", + "VFRAME_IMUX17" + ], + [ + "MONITOR_EL1BEG2_7", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_IMUX28_7", + "VFRAME_IMUX28" + ], + [ + "MONITOR_WW4END0_7", + "VFRAME_WW4END0" + ], + [ + "MONITOR_NW4END2_7", + "VFRAME_NW4END2" + ], + [ + "MONITOR_IMUX31_7", + "VFRAME_IMUX31" + ], + [ + "MONITOR_IMUX39_7", + "VFRAME_IMUX39" + ], + [ + "MONITOR_NE4C2_7", + "VFRAME_NE4C2" + ], + [ + "MONITOR_EL1BEG3_7", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_FAN3_7", + "VFRAME_FAN3" + ], + [ + "MONITOR_SW4A2_7", + "VFRAME_SW4A2" + ], + [ + "MONITOR_IMUX8_7", + "VFRAME_IMUX8" + ], + [ + "MONITOR_FAN4_7", + "VFRAME_FAN4" + ], + [ + "MONITOR_IMUX1_7", + "VFRAME_IMUX1" + ], + [ + "MONITOR_WW4C3_7", + "VFRAME_WW4C3" + ], + [ + "MONITOR_SE4C1_7", + "VFRAME_SE4C1" + ], + [ + "MONITOR_EE2A0_7", + "VFRAME_EE2A0" + ], + [ + "MONITOR_WW2A0_7", + "VFRAME_WW2A0" + ], + [ + "MONITOR_WW2END1_7", + "VFRAME_WW2END1" + ], + [ + "MONITOR_WW4C0_7", + "VFRAME_WW4C0" + ], + [ + "MONITOR_IMUX6_7", + "VFRAME_IMUX6" + ], + [ + "MONITOR_LH4_7", + "VFRAME_LH4" + ], + [ + "MONITOR_IMUX0_7", + "VFRAME_IMUX0" + ], + [ + "MONITOR_LH11_7", + "VFRAME_LH11" + ], + [ + "MONITOR_BYP3_7", + "VFRAME_BYP3" + ], + [ + "MONITOR_IMUX10_7", + "VFRAME_IMUX10" + ], + [ + "MONITOR_IMUX19_7", + "VFRAME_IMUX19" + ], + [ + "MONITOR_IMUX3_7", + "VFRAME_IMUX3" + ], + [ + "MONITOR_WW2A1_7", + "VFRAME_WW2A1" + ], + [ + "MONITOR_SW4END2_7", + "VFRAME_SW4END2" + ], + [ + "MONITOR_EE4BEG0_7", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_SW4END1_7", + "VFRAME_SW4END1" + ], + [ + "MONITOR_SW4A1_7", + "VFRAME_SW4A1" + ], + [ + "MONITOR_WW4END2_7", + "VFRAME_WW4END2" + ], + [ + "MONITOR_NE4C0_7", + "VFRAME_NE4C0" + ], + [ + "MONITOR_LH8_7", + "VFRAME_LH8" + ], + [ + "MONITOR_WR1END2_7", + "VFRAME_WR1END2" + ], + [ + "MONITOR_SW2A1_7", + "VFRAME_SW2A1" + ], + [ + "MONITOR_EE2BEG3_7", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_IMUX34_7", + "VFRAME_IMUX34" + ], + [ + "MONITOR_IMUX5_7", + "VFRAME_IMUX5" + ], + [ + "MONITOR_LH7_7", + "VFRAME_LH7" + ], + [ + "MONITOR_IMUX2_7", + "VFRAME_IMUX2" + ], + [ + "MONITOR_NE4BEG1_7", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_BYP7_7", + "VFRAME_BYP7" + ], + [ + "MONITOR_WW4END1_7", + "VFRAME_WW4END1" + ], + [ + "MONITOR_IMUX4_7", + "VFRAME_IMUX4" + ], + [ + "MONITOR_WW4B0_7", + "VFRAME_WW4B0" + ], + [ + "MONITOR_EE4A0_7", + "VFRAME_EE4A0" + ], + [ + "MONITOR_NW4END3_7", + "VFRAME_NW4END3" + ], + [ + "MONITOR_LH9_7", + "VFRAME_LH9" + ], + [ + "MONITOR_WW2A2_7", + "VFRAME_WW2A2" + ], + [ + "MONITOR_SE4C2_7", + "VFRAME_SE4C2" + ], + [ + "MONITOR_BYP4_7", + "VFRAME_BYP4" + ], + [ + "MONITOR_IMUX9_7", + "VFRAME_IMUX9" + ], + [ + "MONITOR_IMUX33_7", + "VFRAME_IMUX33" + ], + [ + "MONITOR_EL1BEG0_7", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_IMUX13_7", + "VFRAME_IMUX13" + ], + [ + "MONITOR_WL1END3_7", + "VFRAME_WL1END3" + ], + [ + "MONITOR_LH2_7", + "VFRAME_LH2" + ], + [ + "MONITOR_SW2A2_7", + "VFRAME_SW2A2" + ], + [ + "MONITOR_IMUX41_7", + "VFRAME_IMUX41" + ], + [ + "MONITOR_EE4C1_7", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX45_7", + "VFRAME_IMUX45" + ], + [ + "MONITOR_FAN1_7", + "VFRAME_FAN1" + ], + [ + "MONITOR_FAN0_7", + "VFRAME_FAN0" + ], + [ + "MONITOR_WL1END1_7", + "VFRAME_WL1END1" + ], + [ + "MONITOR_IMUX44_7", + "VFRAME_IMUX44" + ], + [ + "MONITOR_ER1BEG0_7", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_SE2A3_7", + "VFRAME_SE2A3" + ], + [ + "MONITOR_IMUX40_7", + "VFRAME_IMUX40" + ], + [ + "MONITOR_WR1END1_7", + "VFRAME_WR1END1" + ], + [ + "MONITOR_NW2A1_7", + "VFRAME_NW2A1" + ], + [ + "MONITOR_WW2END2_7", + "VFRAME_WW2END2" + ], + [ + "MONITOR_NW4A3_7", + "VFRAME_NW4A3" + ], + [ + "MONITOR_SW4A3_7", + "VFRAME_SW4A3" + ], + [ + "MONITOR_ER1BEG2_7", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_EE2A2_7", + "VFRAME_EE2A2" + ], + [ + "MONITOR_EE4C2_7", + "VFRAME_EE4C2" + ], + [ + "MONITOR_NE2A0_7", + "VFRAME_NE2A0" + ], + [ + "MONITOR_WW4A2_7", + "VFRAME_WW4A2" + ], + [ + "MONITOR_EE4A3_7", + "VFRAME_EE4A3" + ], + [ + "MONITOR_SE4BEG3_7", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_IMUX47_7", + "VFRAME_IMUX47" + ], + [ + "MONITOR_WW2END0_7", + "VFRAME_WW2END0" + ], + [ + "MONITOR_IMUX21_7", + "VFRAME_IMUX21" + ], + [ + "MONITOR_NW2A3_7", + "VFRAME_NW2A3" + ], + [ + "MONITOR_LH3_7", + "VFRAME_LH3" + ], + [ + "MONITOR_EE2BEG2_7", + "VFRAME_EE2BEG2" + ] + ], + "tile_types": [ + "MONITOR_BOT_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_FEEDTHRU_1_CK_IN13", + "HCLK_FEEDTHRU_1_CK_IN13" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN6", + "HCLK_FEEDTHRU_1_CK_IN6" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN3", + "HCLK_FEEDTHRU_1_CK_IN3" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN7", + "HCLK_FEEDTHRU_1_CK_IN7" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN0", + "HCLK_FEEDTHRU_1_CK_IN0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK2", + "HCLK_FEEDTHRU_1_CK_BUFHCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN11", + "HCLK_FEEDTHRU_1_CK_IN11" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK8", + "HCLK_FEEDTHRU_1_CK_BUFHCLK8" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK1", + "HCLK_FEEDTHRU_1_CK_BUFRCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK5", + "HCLK_FEEDTHRU_1_CK_BUFHCLK5" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK9", + "HCLK_FEEDTHRU_1_CK_BUFHCLK9" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK4", + "HCLK_FEEDTHRU_1_CK_BUFHCLK4" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK1", + "HCLK_FEEDTHRU_1_CK_BUFHCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN4", + "HCLK_FEEDTHRU_1_CK_IN4" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN8", + "HCLK_FEEDTHRU_1_CK_IN8" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN1", + "HCLK_FEEDTHRU_1_CK_IN1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK3", + "HCLK_FEEDTHRU_1_CK_BUFHCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK3", + "HCLK_FEEDTHRU_1_CK_BUFRCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN2", + "HCLK_FEEDTHRU_1_CK_IN2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK0", + "HCLK_FEEDTHRU_1_CK_BUFHCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK6", + "HCLK_FEEDTHRU_1_CK_BUFHCLK6" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK2", + "HCLK_FEEDTHRU_1_CK_BUFRCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN12", + "HCLK_FEEDTHRU_1_CK_IN12" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN9", + "HCLK_FEEDTHRU_1_CK_IN9" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK7", + "HCLK_FEEDTHRU_1_CK_BUFHCLK7" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK10", + "HCLK_FEEDTHRU_1_CK_BUFHCLK10" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK11", + "HCLK_FEEDTHRU_1_CK_BUFHCLK11" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK0", + "HCLK_FEEDTHRU_1_CK_BUFRCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN5", + "HCLK_FEEDTHRU_1_CK_IN5" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN10", + "HCLK_FEEDTHRU_1_CK_IN10" + ] + ], + "tile_types": [ + "HCLK_FEEDTHRU_1", + "HCLK_FEEDTHRU_1" + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "wire_pairs": [ + [ + "BRAM_EE4C3_1", + "CLBLM_EE4C3" + ], + [ + "BRAM_SW2A3_1", + "CLBLM_SW2A3" + ], + [ + "BRAM_WW4B1_1", + "CLBLM_WW4B1" + ], + [ + "BRAM_NW4A2_1", + "CLBLM_NW4A2" + ], + [ + "BRAM_SW4A0_1", + "CLBLM_SW4A0" + ], + [ + "BRAM_NE4BEG1_1", + "CLBLM_NE4BEG1" + ], + [ + "BRAM_NW4END3_1", + "CLBLM_NW4END3" + ], + [ + "BRAM_LH4_1", + "CLBLM_LH4" + ], + [ + "BRAM_EE4C0_1", + "CLBLM_EE4C0" + ], + [ + "BRAM_WL1END0_1", + "CLBLM_WL1END0" + ], + [ + "BRAM_EE4B1_1", + "CLBLM_EE4B1" + ], + [ + "BRAM_NE4BEG0_1", + "CLBLM_NE4BEG0" + ], + [ + "BRAM_NE2A3_1", + "CLBLM_NE2A3" + ], + [ + "BRAM_MONITOR_N_1", + "CLBLM_MONITOR_N" + ], + [ + "BRAM_WL1END2_1", + "CLBLM_WL1END2" + ], + [ + "BRAM_WW4END2_1", + "CLBLM_WW4END2" + ], + [ + "BRAM_WW4END3_1", + "CLBLM_WW4END3" + ], + [ + "BRAM_LH5_1", + "CLBLM_LH5" + ], + [ + "BRAM_SW4END2_1", + "CLBLM_SW4END2" + ], + [ + "BRAM_NE2A1_1", + "CLBLM_NE2A1" + ], + [ + "BRAM_EE4BEG0_1", + "CLBLM_EE4BEG0" + ], + [ + "BRAM_WW2END0_1", + "CLBLM_WW2END0" + ], + [ + "BRAM_EE2BEG0_1", + "CLBLM_EE2BEG0" + ], + [ + "BRAM_WR1END3_1", + "CLBLM_WR1END3" + ], + [ + "BRAM_LH12_1", + "CLBLM_LH12" + ], + [ + "BRAM_SE2A2_1", + "CLBLM_SE2A2" + ], + [ + "BRAM_WW2END3_1", + "CLBLM_WW2END3" + ], + [ + "BRAM_EE2A1_1", + "CLBLM_EE2A1" + ], + [ + "BRAM_EE2BEG2_1", + "CLBLM_EE2BEG2" + ], + [ + "BRAM_EE2A3_1", + "CLBLM_EE2A3" + ], + [ + "BRAM_EL1BEG2_1", + "CLBLM_EL1BEG2" + ], + [ + "BRAM_ER1BEG2_1", + "CLBLM_ER1BEG2" + ], + [ + "BRAM_WW4A2_1", + "CLBLM_WW4A2" + ], + [ + "BRAM_SE4C2_1", + "CLBLM_SE4C2" + ], + [ + "BRAM_EE4C1_1", + "CLBLM_EE4C1" + ], + [ + "BRAM_NW2A1_1", + "CLBLM_NW2A1" + ], + [ + "BRAM_WR1END0_1", + "CLBLM_WR1END0" + ], + [ + "BRAM_WR1END2_1", + "CLBLM_WR1END2" + ], + [ + "BRAM_LH9_1", + "CLBLM_LH9" + ], + [ + "BRAM_SW4A3_1", + "CLBLM_SW4A3" + ], + [ + "BRAM_EE4A3_1", + "CLBLM_EE4A3" + ], + [ + "BRAM_MONITOR_P_1", + "CLBLM_MONITOR_P" + ], + [ + "BRAM_LH2_1", + "CLBLM_LH2" + ], + [ + "BRAM_NW2A0_1", + "CLBLM_NW2A0" + ], + [ + "BRAM_WL1END3_1", + "CLBLM_WL1END3" + ], + [ + "BRAM_SW2A0_1", + "CLBLM_SW2A0" + ], + [ + "BRAM_SE4C1_1", + "CLBLM_SE4C1" + ], + [ + "BRAM_EE4B3_1", + "CLBLM_EE4B3" + ], + [ + "BRAM_EE4BEG3_1", + "CLBLM_EE4BEG3" + ], + [ + "BRAM_ER1BEG0_1", + "CLBLM_ER1BEG0" + ], + [ + "BRAM_SE4BEG1_1", + "CLBLM_SE4BEG1" + ], + [ + "BRAM_SW2A1_1", + "CLBLM_SW2A1" + ], + [ + "BRAM_EE2A0_1", + "CLBLM_EE2A0" + ], + [ + "BRAM_SW4END3_1", + "CLBLM_SW4END3" + ], + [ + "BRAM_LH1_1", + "CLBLM_LH1" + ], + [ + "BRAM_WW2A1_1", + "CLBLM_WW2A1" + ], + [ + "BRAM_WW4C3_1", + "CLBLM_WW4C3" + ], + [ + "BRAM_EL1BEG1_1", + "CLBLM_EL1BEG1" + ], + [ + "BRAM_NW2A2_1", + "CLBLM_NW2A2" + ], + [ + "BRAM_NE4C1_1", + "CLBLM_NE4C1" + ], + [ + "BRAM_SW4A1_1", + "CLBLM_SW4A1" + ], + [ + "BRAM_SE4BEG0_1", + "CLBLM_SE4BEG0" + ], + [ + "BRAM_EE4C2_1", + "CLBLM_EE4C2" + ], + [ + "BRAM_EE4B0_1", + "CLBLM_EE4B0" + ], + [ + "BRAM_NW4END1_1", + "CLBLM_NW4END1" + ], + [ + "BRAM_WW4A1_1", + "CLBLM_WW4A1" + ], + [ + "BRAM_SW4A2_1", + "CLBLM_SW4A2" + ], + [ + "BRAM_NE4BEG2_1", + "CLBLM_NE4BEG2" + ], + [ + "BRAM_SE4BEG2_1", + "CLBLM_SE4BEG2" + ], + [ + "BRAM_WW4END1_1", + "CLBLM_WW4END1" + ], + [ + "BRAM_WR1END1_1", + "CLBLM_WR1END1" + ], + [ + "BRAM_WW4B3_1", + "CLBLM_WW4B3" + ], + [ + "BRAM_WW4B0_1", + "CLBLM_WW4B0" + ], + [ + "BRAM_LH7_1", + "CLBLM_LH7" + ], + [ + "BRAM_WL1END1_1", + "CLBLM_WL1END1" + ], + [ + "BRAM_EE2BEG1_1", + "CLBLM_EE2BEG1" + ], + [ + "BRAM_EE4BEG1_1", + "CLBLM_EE4BEG1" + ], + [ + "BRAM_NE2A0_1", + "CLBLM_NE2A0" + ], + [ + "BRAM_LH10_1", + "CLBLM_LH10" + ], + [ + "BRAM_SE4C0_1", + "CLBLM_SE4C0" + ], + [ + "BRAM_ER1BEG1_1", + "CLBLM_ER1BEG1" + ], + [ + "BRAM_LH8_1", + "CLBLM_LH8" + ], + [ + "BRAM_EE2A2_1", + "CLBLM_EE2A2" + ], + [ + "BRAM_NE4C0_1", + "CLBLM_NE4C0" + ], + [ + "BRAM_NW4END0_1", + "CLBLM_NW4END0" + ], + [ + "BRAM_EE4BEG2_1", + "CLBLM_EE4BEG2" + ], + [ + "BRAM_WW4C2_1", + "CLBLM_WW4C2" + ], + [ + "BRAM_WW4C1_1", + "CLBLM_WW4C1" + ], + [ + "BRAM_LH11_1", + "CLBLM_LH11" + ], + [ + "BRAM_SE4BEG3_1", + "CLBLM_SE4BEG3" + ], + [ + "BRAM_ER1BEG3_1", + "CLBLM_ER1BEG3" + ], + [ + "BRAM_WW2A3_1", + "CLBLM_WW2A3" + ], + [ + "BRAM_WW4END0_1", + "CLBLM_WW4END0" + ], + [ + "BRAM_NE2A2_1", + "CLBLM_NE2A2" + ], + [ + "BRAM_NW4END2_1", + "CLBLM_NW4END2" + ], + [ + "BRAM_NE4C3_1", + "CLBLM_NE4C3" + ], + [ + "BRAM_LH6_1", + "CLBLM_LH6" + ], + [ + "BRAM_EL1BEG0_1", + "CLBLM_EL1BEG0" + ], + [ + "BRAM_SE2A0_1", + "CLBLM_SE2A0" + ], + [ + "BRAM_NW4A1_1", + "CLBLM_NW4A1" + ], + [ + "BRAM_NW2A3_1", + "CLBLM_NW2A3" + ], + [ + "BRAM_SE2A1_1", + "CLBLM_SE2A1" + ], + [ + "BRAM_LH3_1", + "CLBLM_LH3" + ], + [ + "BRAM_SE2A3_1", + "CLBLM_SE2A3" + ], + [ + "BRAM_WW2END1_1", + "CLBLM_WW2END1" + ], + [ + "BRAM_WW2A2_1", + "CLBLM_WW2A2" + ], + [ + "BRAM_EE4B2_1", + "CLBLM_EE4B2" + ], + [ + "BRAM_WW2A0_1", + "CLBLM_WW2A0" + ], + [ + "BRAM_SW2A2_1", + "CLBLM_SW2A2" + ], + [ + "BRAM_WW2END2_1", + "CLBLM_WW2END2" + ], + [ + "BRAM_NW4A3_1", + "CLBLM_NW4A3" + ], + [ + "BRAM_NW4A0_1", + "CLBLM_NW4A0" + ], + [ + "BRAM_NE4C2_1", + "CLBLM_NE4C2" + ], + [ + "BRAM_EE4A0_1", + "CLBLM_EE4A0" + ], + [ + "BRAM_SE4C3_1", + "CLBLM_SE4C3" + ], + [ + "BRAM_WW4C0_1", + "CLBLM_WW4C0" + ], + [ + "BRAM_WW4A0_1", + "CLBLM_WW4A0" + ], + [ + "BRAM_EL1BEG3_1", + "CLBLM_EL1BEG3" + ], + [ + "BRAM_SW4END1_1", + "CLBLM_SW4END1" + ], + [ + "BRAM_SW4END0_1", + "CLBLM_SW4END0" + ], + [ + "BRAM_EE4A2_1", + "CLBLM_EE4A2" + ], + [ + "BRAM_NE4BEG3_1", + "CLBLM_NE4BEG3" + ], + [ + "BRAM_WW4B2_1", + "CLBLM_WW4B2" + ], + [ + "BRAM_EE4A1_1", + "CLBLM_EE4A1" + ], + [ + "BRAM_WW4A3_1", + "CLBLM_WW4A3" + ], + [ + "BRAM_EE2BEG3_1", + "CLBLM_EE2BEG3" + ] + ], + "tile_types": [ + "BRAM_L", + "CLBLM_R" + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "wire_pairs": [ + [ + "IOI_LEAF_GCLK1", + "IOI_LEAF_GCLK1" + ], + [ + "IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "IOI_TBYTEIN", + "IOI_TBYTEIN" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_RCLK_FORIO2" + ], + [ + "IOI_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3_1" + ], + [ + "IOI_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2_1" + ], + [ + "RIOI_I2GCLK_BOT1", + "RIOI_I2GCLK_TOP0" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_LEAF_GCLK0" + ], + [ + "IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_RCLK_FORIO1" + ], + [ + "IOI_IMUX_RC1", + "IOI_IMUX_RC3" + ], + [ + "IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_LEAF_GCLK2" + ], + [ + "IOI_DCI_TSTRST", + "IOI_DCI_TSTRST0" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_LEAF_GCLK3" + ], + [ + "IOI_IMUX_RC0", + "IOI_IMUX_RC2" + ], + [ + "IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_LEAF_GCLK5" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_RCLK_FORIO3" + ], + [ + "RIOI_I2GCLK_TOP0", + "RIOI_I2GCLK_TOP1" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_RCLK_FORIO0" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_LEAF_GCLK4" + ] + ], + "tile_types": [ + "RIOI", + "RIOI" + ] + }, + { + "grid_deltas": [ + 1, + -9 + ], + "wire_pairs": [ + [ + "CFG_CENTER_WW4B2_19", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_IMUX0_19", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_WW2A1_19", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_WW2A3_19", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_WW4B0_19", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_IMUX10_19", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_NW4END1_19", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B23_19", + "VFRAME_LOGIC_OUTS_B23" + ], + [ + "CFG_CENTER_EE4B3_19", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_NW4END3_19", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_IMUX32_19", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_WR1END3_19", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_BYP2_19", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_EE4BEG0_19", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_NW4A2_19", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_SW4END1_19", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_WW4A0_19", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_EL1BEG1_19", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_LH11_19", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_EE4BEG2_19", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_IMUX46_19", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_FAN6_19", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_EE2A1_19", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_SW2A2_19", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_NE4C0_19", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE4C3_19", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_EE4B0_19", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_WW2END3_19", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW4END3_19", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_WW4C1_19", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_EE4BEG1_19", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_NE4BEG1_19", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_SE4C1_19", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX16_19", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_NE2A0_19", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_WW4A3_19", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_LH8_19", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_CLK0_19", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_NE4C3_19", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_SW2A0_19", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_WW4END2_19", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_WW4B1_19", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_CTRL0_19", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_SE4BEG0_19", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_CTRL1_19", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_LH10_19", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_IMUX9_19", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_IMUX37_19", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_EE4C2_19", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_SW4A0_19", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B13_19", + "VFRAME_LOGIC_OUTS_B13" + ], + [ + "CFG_CENTER_IMUX40_19", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_BYP4_19", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_NW4A1_19", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_BYP7_19", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_NE2A3_19", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_NW4A3_19", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B16_19", + "VFRAME_LOGIC_OUTS_B16" + ], + [ + "CFG_CENTER_FAN4_19", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_CLK1_19", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX19_19", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_IMUX20_19", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_LH4_19", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_ER1BEG2_19", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX30_19", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_LH3_19", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX21_19", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_SW4END2_19", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_BYP1_19", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_BYP3_19", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_IMUX38_19", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_SE2A1_19", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_EE2BEG0_19", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_WW2A2_19", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_SE4C0_19", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_WL1END3_19", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_EE4B2_19", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_LH7_19", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_LH5_19", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX14_19", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_IMUX25_19", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_NW2A3_19", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NW2A2_19", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_WR1END2_19", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_NE4BEG3_19", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX24_19", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_SW2A3_19", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_EL1BEG3_19", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW4A1_19", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_IMUX17_19", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_BYP5_19", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_NE4BEG2_19", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_WW2END0_19", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_LH1_19", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_EE4C0_19", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B10_19", + "VFRAME_LOGIC_OUTS_B10" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B15_19", + "VFRAME_LOGIC_OUTS_B15" + ], + [ + "CFG_CENTER_EE4A3_19", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_IMUX8_19", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_IMUX15_19", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_BYP6_19", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_LH2_19", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B11_19", + "VFRAME_LOGIC_OUTS_B11" + ], + [ + "CFG_CENTER_FAN2_19", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_LH9_19", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_EL1BEG2_19", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX2_19", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B20_19", + "VFRAME_LOGIC_OUTS_B20" + ], + [ + "CFG_CENTER_SE4BEG1_19", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG3_19", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_WR1END1_19", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_IMUX7_19", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_IMUX28_19", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_FAN7_19", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B22_19", + "VFRAME_LOGIC_OUTS_B22" + ], + [ + "CFG_CENTER_EE2BEG2_19", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_IMUX3_19", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_FAN1_19", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_IMUX13_19", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_EE4B1_19", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_IMUX12_19", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX23_19", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_NW4END2_19", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_IMUX44_19", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_WW4B3_19", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_EE2BEG1_19", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_EE4A2_19", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_SW4A3_19", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_SW4END3_19", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_ER1BEG0_19", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_EE2A0_19", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_BYP0_19", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_IMUX36_19", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_NW2A0_19", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_EE4A0_19", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_WW4C3_19", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_NW4A0_19", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_IMUX29_19", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_NE4BEG0_19", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_WW2END2_19", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B19_19", + "VFRAME_LOGIC_OUTS_B19" + ], + [ + "CFG_CENTER_NW4END0_19", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX42_19", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_LH12_19", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_SE2A3_19", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_NE4C1_19", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_SE4BEG2_19", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_IMUX1_19", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_IMUX4_19", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_IMUX39_19", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_WW4A2_19", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_IMUX26_19", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_IMUX27_19", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_LH6_19", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_SW4A1_19", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_IMUX35_19", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_WW2END1_19", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_WW4C0_19", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_IMUX18_19", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_SE2A0_19", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_IMUX22_19", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_FAN5_19", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B12_19", + "VFRAME_LOGIC_OUTS_B12" + ], + [ + "CFG_CENTER_EE4A1_19", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX47_19", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_IMUX11_19", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX33_19", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_WL1END0_19", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_SE2A2_19", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_WL1END2_19", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_IMUX41_19", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_WW4END1_19", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_NW2A1_19", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_ER1BEG1_19", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B14_19", + "VFRAME_LOGIC_OUTS_B14" + ], + [ + "CFG_CENTER_NE2A1_19", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_ER1BEG3_19", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B21_19", + "VFRAME_LOGIC_OUTS_B21" + ], + [ + "CFG_CENTER_NE2A2_19", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_EE2BEG3_19", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B17_19", + "VFRAME_LOGIC_OUTS_B17" + ], + [ + "CFG_CENTER_IMUX45_19", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX31_19", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_WW2A0_19", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_SW4A2_19", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_NE4C2_19", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_SE4C3_19", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_IMUX5_19", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX6_19", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_EE2A3_19", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_FAN3_19", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_IMUX43_19", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_SW2A1_19", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_FAN0_19", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_EL1BEG0_19", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_SE4C2_19", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_IMUX34_19", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_WR1END0_19", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_LOGIC_OUTS_B18_19", + "VFRAME_LOGIC_OUTS_B18" + ], + [ + "CFG_CENTER_EE4BEG3_19", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_SW4END0_19", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_WW4END0_19", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_WL1END1_19", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_EE4C1_19", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_EE2A2_19", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_WW4C2_19", + "VFRAME_WW4C2" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "CFG_CENTER_IMUX7_10", + "VFRAME_IMUX7" + ], + [ + "CFG_CENTER_WR1END1_10", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_BYP0_10", + "VFRAME_BYP0" + ], + [ + "CFG_CENTER_FAN7_10", + "VFRAME_FAN7" + ], + [ + "CFG_CENTER_IMUX37_10", + "VFRAME_IMUX37" + ], + [ + "CFG_CENTER_LH5_10", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_IMUX5_10", + "VFRAME_IMUX5" + ], + [ + "CFG_CENTER_IMUX24_10", + "VFRAME_IMUX24" + ], + [ + "CFG_CENTER_WW4A1_10", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_LH10_10", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_IMUX21_10", + "VFRAME_IMUX21" + ], + [ + "CFG_CENTER_EL1BEG0_10", + "VFRAME_EL1BEG0" + ], + [ + "CFG_CENTER_IMUX36_10", + "VFRAME_IMUX36" + ], + [ + "CFG_CENTER_CTRL0_10", + "VFRAME_CTRL0" + ], + [ + "CFG_CENTER_SE2A2_10", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_IMUX31_10", + "VFRAME_IMUX31" + ], + [ + "CFG_CENTER_EE2A3_10", + "VFRAME_EE2A3" + ], + [ + "CFG_CENTER_NE4C3_10", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_EE4B3_10", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_EE2BEG1_10", + "VFRAME_EE2BEG1" + ], + [ + "CFG_CENTER_IMUX34_10", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_SE4BEG2_10", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_NW2A0_10", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_WW2A1_10", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_EL1BEG1_10", + "VFRAME_EL1BEG1" + ], + [ + "CFG_CENTER_EE4A1_10", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_IMUX23_10", + "VFRAME_IMUX23" + ], + [ + "CFG_CENTER_IMUX46_10", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_WW4A2_10", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_LH4_10", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_WW2A0_10", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_BYP7_10", + "VFRAME_BYP7" + ], + [ + "CFG_CENTER_EL1BEG3_10", + "VFRAME_EL1BEG3" + ], + [ + "CFG_CENTER_WW4B2_10", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_WW4END3_10", + "VFRAME_WW4END3" + ], + [ + "CFG_CENTER_IMUX15_10", + "VFRAME_IMUX15" + ], + [ + "CFG_CENTER_FAN0_10", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_WW4A0_10", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_BYP1_10", + "VFRAME_BYP1" + ], + [ + "CFG_CENTER_SW4A3_10", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_IMUX27_10", + "VFRAME_IMUX27" + ], + [ + "CFG_CENTER_IMUX8_10", + "VFRAME_IMUX8" + ], + [ + "CFG_CENTER_IMUX3_10", + "VFRAME_IMUX3" + ], + [ + "CFG_CENTER_BYP5_10", + "VFRAME_BYP5" + ], + [ + "CFG_CENTER_WW4C1_10", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_NE2A1_10", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX30_10", + "VFRAME_IMUX30" + ], + [ + "CFG_CENTER_CLK0_10", + "VFRAME_CLK0" + ], + [ + "CFG_CENTER_WW2END1_10", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_ER1BEG2_10", + "VFRAME_ER1BEG2" + ], + [ + "CFG_CENTER_IMUX14_10", + "VFRAME_IMUX14" + ], + [ + "CFG_CENTER_WW2END3_10", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_IMUX13_10", + "VFRAME_IMUX13" + ], + [ + "CFG_CENTER_IMUX6_10", + "VFRAME_IMUX6" + ], + [ + "CFG_CENTER_IMUX0_10", + "VFRAME_IMUX0" + ], + [ + "CFG_CENTER_NW2A3_10", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_WL1END0_10", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_IMUX45_10", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX38_10", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_SW4END0_10", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_LH3_10", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX4_10", + "VFRAME_IMUX4" + ], + [ + "CFG_CENTER_SW4A1_10", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_NE2A3_10", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_SE4BEG1_10", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_IMUX42_10", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_SW2A0_10", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_WL1END3_10", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_WW2A2_10", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_NW4END1_10", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_EL1BEG2_10", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_IMUX16_10", + "VFRAME_IMUX16" + ], + [ + "CFG_CENTER_SW2A3_10", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_NW2A2_10", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_ER1BEG1_10", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_EE4B2_10", + "VFRAME_EE4B2" + ], + [ + "CFG_CENTER_EE2A2_10", + "VFRAME_EE2A2" + ], + [ + "CFG_CENTER_EE4A3_10", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_SW2A2_10", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_NW4A0_10", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_SW4END1_10", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_ER1BEG3_10", + "VFRAME_ER1BEG3" + ], + [ + "CFG_CENTER_IMUX47_10", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_EE4A0_10", + "VFRAME_EE4A0" + ], + [ + "CFG_CENTER_SE4C1_10", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_IMUX18_10", + "VFRAME_IMUX18" + ], + [ + "CFG_CENTER_IMUX1_10", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_BYP2_10", + "VFRAME_BYP2" + ], + [ + "CFG_CENTER_NE4BEG2_10", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_IMUX40_10", + "VFRAME_IMUX40" + ], + [ + "CFG_CENTER_FAN6_10", + "VFRAME_FAN6" + ], + [ + "CFG_CENTER_EE4A2_10", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_EE4BEG2_10", + "VFRAME_EE4BEG2" + ], + [ + "CFG_CENTER_SW4A2_10", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_SW4END3_10", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_IMUX32_10", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_SW4END2_10", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_SE4C3_10", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_NW4A2_10", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_IMUX25_10", + "VFRAME_IMUX25" + ], + [ + "CFG_CENTER_IMUX12_10", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_IMUX35_10", + "VFRAME_IMUX35" + ], + [ + "CFG_CENTER_LH2_10", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_FAN2_10", + "VFRAME_FAN2" + ], + [ + "CFG_CENTER_EE4B1_10", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_NW4END3_10", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_NW4END2_10", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_EE2BEG2_10", + "VFRAME_EE2BEG2" + ], + [ + "CFG_CENTER_SW4A0_10", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_IMUX22_10", + "VFRAME_IMUX22" + ], + [ + "CFG_CENTER_NW4A1_10", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_IMUX41_10", + "VFRAME_IMUX41" + ], + [ + "CFG_CENTER_WW2END2_10", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_NW4A3_10", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_WW4A3_10", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_BYP6_10", + "VFRAME_BYP6" + ], + [ + "CFG_CENTER_WL1END1_10", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_EE4C0_10", + "VFRAME_EE4C0" + ], + [ + "CFG_CENTER_NW2A1_10", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_WW4B0_10", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_WW4B1_10", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_NE2A2_10", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_NE4C0_10", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE4C3_10", + "VFRAME_EE4C3" + ], + [ + "CFG_CENTER_FAN3_10", + "VFRAME_FAN3" + ], + [ + "CFG_CENTER_FAN1_10", + "VFRAME_FAN1" + ], + [ + "CFG_CENTER_EE4B0_10", + "VFRAME_EE4B0" + ], + [ + "CFG_CENTER_IMUX19_10", + "VFRAME_IMUX19" + ], + [ + "CFG_CENTER_WL1END2_10", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_EE2BEG3_10", + "VFRAME_EE2BEG3" + ], + [ + "CFG_CENTER_IMUX28_10", + "VFRAME_IMUX28" + ], + [ + "CFG_CENTER_SE4BEG0_10", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_WR1END2_10", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_FAN5_10", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_NE2A0_10", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_WW4C3_10", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_IMUX9_10", + "VFRAME_IMUX9" + ], + [ + "CFG_CENTER_WW2A3_10", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_WW4C2_10", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_BYP4_10", + "VFRAME_BYP4" + ], + [ + "CFG_CENTER_WW4END2_10", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_ER1BEG0_10", + "VFRAME_ER1BEG0" + ], + [ + "CFG_CENTER_SE4C0_10", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_WR1END3_10", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_LH1_10", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_WW4END1_10", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_IMUX10_10", + "VFRAME_IMUX10" + ], + [ + "CFG_CENTER_WW4B3_10", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_WW4C0_10", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_EE4C2_10", + "VFRAME_EE4C2" + ], + [ + "CFG_CENTER_SW2A1_10", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_CLK1_10", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_EE4BEG0_10", + "VFRAME_EE4BEG0" + ], + [ + "CFG_CENTER_EE4BEG1_10", + "VFRAME_EE4BEG1" + ], + [ + "CFG_CENTER_IMUX11_10", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_IMUX2_10", + "VFRAME_IMUX2" + ], + [ + "CFG_CENTER_SE2A3_10", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_IMUX29_10", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_IMUX44_10", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_CTRL1_10", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_NE4C1_10", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_LH12_10", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_EE2A0_10", + "VFRAME_EE2A0" + ], + [ + "CFG_CENTER_WR1END0_10", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_EE2A1_10", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_EE4C1_10", + "VFRAME_EE4C1" + ], + [ + "CFG_CENTER_IMUX33_10", + "VFRAME_IMUX33" + ], + [ + "CFG_CENTER_WW2END0_10", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_NE4BEG0_10", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_BYP3_10", + "VFRAME_BYP3" + ], + [ + "CFG_CENTER_SE2A0_10", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_NE4C2_10", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_LH7_10", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_LH11_10", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_SE4C2_10", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_LH6_10", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_FAN4_10", + "VFRAME_FAN4" + ], + [ + "CFG_CENTER_NE4BEG3_10", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX43_10", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX26_10", + "VFRAME_IMUX26" + ], + [ + "CFG_CENTER_LH8_10", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_IMUX17_10", + "VFRAME_IMUX17" + ], + [ + "CFG_CENTER_IMUX20_10", + "VFRAME_IMUX20" + ], + [ + "CFG_CENTER_EE4BEG3_10", + "VFRAME_EE4BEG3" + ], + [ + "CFG_CENTER_NW4END0_10", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_IMUX39_10", + "VFRAME_IMUX39" + ], + [ + "CFG_CENTER_SE4BEG3_10", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_WW4END0_10", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_EE2BEG0_10", + "VFRAME_EE2BEG0" + ], + [ + "CFG_CENTER_LH9_10", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_SE2A1_10", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_NE4BEG1_10", + "VFRAME_NE4BEG1" + ] + ], + "tile_types": [ + "CFG_CENTER_BOT", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 5, + -9 + ], + "wire_pairs": [ + [ + "PCIE_LH5_19", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_MONITOR_N_19", + "INT_INTERFACE_MONITOR_N" + ], + [ + "PCIE_IMUX16_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT16" + ], + [ + "PCIE_SW4END2_19", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_WW4C2_19", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_WW4END3_19", + "INT_INTERFACE_WW4END3" + ], + [ + "PCIE_LH3_19", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_EE4BEG1_19", + "INT_INTERFACE_EE4BEG1" + ], + [ + "PCIE_LH7_19", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_IMUX30_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT30" + ], + [ + "PCIE_SW2A1_19", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_CLK0_L_19", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_SW4A2_19", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_EE4C1_19", + "INT_INTERFACE_EE4C1" + ], + [ + "PCIE_IMUX6_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT6" + ], + [ + "PCIE_NW2A2_19", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_NE4BEG0_19", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_BYP6_L_19", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_MONITOR_P_19", + "INT_INTERFACE_MONITOR_P" + ], + [ + "PCIE_LH2_19", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_IMUX9_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT9" + ], + [ + "PCIE_IMUX35_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT35" + ], + [ + "PCIE_CLK1_L_19", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_IMUX21_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT21" + ], + [ + "PCIE_IMUX18_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT18" + ], + [ + "PCIE_EL1BEG1_19", + "INT_INTERFACE_EL1BEG1" + ], + [ + "PCIE_NE4BEG1_19", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_ER1BEG3_19", + "INT_INTERFACE_ER1BEG3" + ], + [ + "PCIE_WW4C3_19", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_LOGIC_OUTS_B5_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B5" + ], + [ + "PCIE_IMUX20_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT20" + ], + [ + "PCIE_EE4A2_19", + "INT_INTERFACE_EE4A2" + ], + [ + "PCIE_FAN6_L_19", + "INT_INTERFACE_FAN6" + ], + [ + "PCIE_NE2A0_19", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_EE4A0_19", + "INT_INTERFACE_EE4A0" + ], + [ + "PCIE_IMUX0_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT0" + ], + [ + "PCIE_SE4C2_19", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_LOGIC_OUTS_B12_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B12" + ], + [ + "PCIE_SE2A2_19", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_NE4C2_19", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_LH4_19", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_IMUX39_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT39" + ], + [ + "PCIE_IMUX24_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT24" + ], + [ + "PCIE_WW2A0_19", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_ER1BEG2_19", + "INT_INTERFACE_ER1BEG2" + ], + [ + "PCIE_BYP1_L_19", + "INT_INTERFACE_BYP1" + ], + [ + "PCIE_IMUX38_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT38" + ], + [ + "PCIE_WL1END2_19", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_NE4C1_19", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_NW2A3_19", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_SW4A0_19", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_EL1BEG3_19", + "INT_INTERFACE_EL1BEG3" + ], + [ + "PCIE_LH9_19", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_LOGIC_OUTS_B7_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B7" + ], + [ + "PCIE_EE4BEG2_19", + "INT_INTERFACE_EE4BEG2" + ], + [ + "PCIE_IMUX26_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT26" + ], + [ + "PCIE_SE2A3_19", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_SE4BEG3_19", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_SE2A1_19", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_IMUX44_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT44" + ], + [ + "PCIE_WW2END3_19", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_LH12_19", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_NW4END3_19", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_LOGIC_OUTS_B17_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B17" + ], + [ + "PCIE_IMUX25_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT25" + ], + [ + "PCIE_LOGIC_OUTS_B2_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B2" + ], + [ + "PCIE_LOGIC_OUTS_B0_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "PCIE_LH11_19", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_FAN4_L_19", + "INT_INTERFACE_FAN4" + ], + [ + "PCIE_IMUX40_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT40" + ], + [ + "PCIE_CTRL1_L_19", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_IMUX2_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT2" + ], + [ + "PCIE_IMUX27_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT27" + ], + [ + "PCIE_NE2A3_19", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_IMUX7_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT7" + ], + [ + "PCIE_FAN7_L_19", + "INT_INTERFACE_FAN7" + ], + [ + "PCIE_EE4C0_19", + "INT_INTERFACE_EE4C0" + ], + [ + "PCIE_SE4C1_19", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_WW4C1_19", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_IMUX15_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT15" + ], + [ + "PCIE_LOGIC_OUTS_B13_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B13" + ], + [ + "PCIE_IMUX47_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT47" + ], + [ + "PCIE_NE4BEG3_19", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_EE2A2_19", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_IMUX29_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT29" + ], + [ + "PCIE_SW4A3_19", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_IMUX13_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT13" + ], + [ + "PCIE_IMUX12_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT12" + ], + [ + "PCIE_WR1END2_19", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_WW4B2_19", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_IMUX42_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT42" + ], + [ + "PCIE_LOGIC_OUTS_B21_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + [ + "PCIE_IMUX28_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT28" + ], + [ + "PCIE_WR1END3_19", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_SW2A2_19", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_IMUX23_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT23" + ], + [ + "PCIE_SW2A3_19", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_LOGIC_OUTS_B22_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "PCIE_WW4END2_19", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_SW4A1_19", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_NE2A2_19", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_LOGIC_OUTS_B9_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B9" + ], + [ + "PCIE_BYP7_L_19", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_SW4END0_19", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_SW4END1_19", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_WR1END1_19", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_IMUX46_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT46" + ], + [ + "PCIE_WW4A3_19", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_IMUX3_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT3" + ], + [ + "PCIE_NE2A1_19", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_LOGIC_OUTS_B1_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B1" + ], + [ + "PCIE_LOGIC_OUTS_B8_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B8" + ], + [ + "PCIE_FAN5_L_19", + "INT_INTERFACE_FAN5" + ], + [ + "PCIE_NE4C3_19", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_IMUX10_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT10" + ], + [ + "PCIE_IMUX1_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT1" + ], + [ + "PCIE_WW2END1_19", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_WW4END0_19", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_WW4A0_19", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_LOGIC_OUTS_B18_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B18" + ], + [ + "PCIE_LOGIC_OUTS_B23_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B23" + ], + [ + "PCIE_WW4END1_19", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_SE4C3_19", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_WW2END0_19", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_WW4B3_19", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_IMUX36_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT36" + ], + [ + "PCIE_NW2A0_19", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_LOGIC_OUTS_B19_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B19" + ], + [ + "PCIE_NW4A2_19", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_WW2A2_19", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_CTRL0_L_19", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_WW4B0_19", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_EE4B1_19", + "INT_INTERFACE_EE4B1" + ], + [ + "PCIE_LOGIC_OUTS_B14_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B14" + ], + [ + "PCIE_WL1END3_19", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_IMUX17_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT17" + ], + [ + "PCIE_WR1END0_19", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_IMUX8_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT8" + ], + [ + "PCIE_IMUX37_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT37" + ], + [ + "PCIE_NW4A1_19", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_EE4B2_19", + "INT_INTERFACE_EE4B2" + ], + [ + "PCIE_IMUX19_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT19" + ], + [ + "PCIE_IMUX22_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT22" + ], + [ + "PCIE_LOGIC_OUTS_B4_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B4" + ], + [ + "PCIE_EE4A1_19", + "INT_INTERFACE_EE4A1" + ], + [ + "PCIE_WW2A1_19", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_WW4B1_19", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_BYP0_L_19", + "INT_INTERFACE_BYP0" + ], + [ + "PCIE_LOGIC_OUTS_B16_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B16" + ], + [ + "PCIE_LH6_19", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_IMUX5_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT5" + ], + [ + "PCIE_NW4END2_19", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_IMUX14_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT14" + ], + [ + "PCIE_NW4A0_19", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_WW4A1_19", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_SE4BEG1_19", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_BYP5_L_19", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_EE4B3_19", + "INT_INTERFACE_EE4B3" + ], + [ + "PCIE_EE2BEG2_19", + "INT_INTERFACE_EE2BEG2" + ], + [ + "PCIE_EE4C3_19", + "INT_INTERFACE_EE4C3" + ], + [ + "PCIE_EE2BEG0_19", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_ER1BEG1_19", + "INT_INTERFACE_ER1BEG1" + ], + [ + "PCIE_EE2BEG1_19", + "INT_INTERFACE_EE2BEG1" + ], + [ + "PCIE_EL1BEG2_19", + "INT_INTERFACE_EL1BEG2" + ], + [ + "PCIE_IMUX41_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT41" + ], + [ + "PCIE_IMUX34_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT34" + ], + [ + "PCIE_LOGIC_OUTS_B11_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B11" + ], + [ + "PCIE_BYP4_L_19", + "INT_INTERFACE_BYP4" + ], + [ + "PCIE_IMUX43_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT43" + ], + [ + "PCIE_NE4C0_19", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_EE2BEG3_19", + "INT_INTERFACE_EE2BEG3" + ], + [ + "PCIE_ER1BEG0_19", + "INT_INTERFACE_ER1BEG0" + ], + [ + "PCIE_SW4END3_19", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_WL1END1_19", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_LH1_19", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_IMUX31_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT31" + ], + [ + "PCIE_EE4BEG3_19", + "INT_INTERFACE_EE4BEG3" + ], + [ + "PCIE_WW2A3_19", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_IMUX11_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT11" + ], + [ + "PCIE_SE4C0_19", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_NW4END0_19", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_LOGIC_OUTS_B6_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B6" + ], + [ + "PCIE_BYP2_L_19", + "INT_INTERFACE_BYP2" + ], + [ + "PCIE_NW4END1_19", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_SE2A0_19", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_SE4BEG2_19", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_WW4A2_19", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_LH10_19", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_EE4A3_19", + "INT_INTERFACE_EE4A3" + ], + [ + "PCIE_WW4C0_19", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_NW4A3_19", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_WW2END2_19", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_EE2A1_19", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_IMUX32_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT32" + ], + [ + "PCIE_FAN1_L_19", + "INT_INTERFACE_FAN1" + ], + [ + "PCIE_IMUX45_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT45" + ], + [ + "PCIE_EE2A3_19", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_SE4BEG0_19", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_LOGIC_OUTS_B15_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B15" + ], + [ + "PCIE_WL1END0_19", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_LOGIC_OUTS_B10_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B10" + ], + [ + "PCIE_SW2A0_19", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_EE4C2_19", + "INT_INTERFACE_EE4C2" + ], + [ + "PCIE_LH8_19", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_EE4BEG0_19", + "INT_INTERFACE_EE4BEG0" + ], + [ + "PCIE_IMUX33_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT33" + ], + [ + "PCIE_FAN2_L_19", + "INT_INTERFACE_FAN2" + ], + [ + "PCIE_FAN0_L_19", + "INT_INTERFACE_FAN0" + ], + [ + "PCIE_EE4B0_19", + "INT_INTERFACE_EE4B0" + ], + [ + "PCIE_LOGIC_OUTS_B20_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B20" + ], + [ + "PCIE_EL1BEG0_19", + "INT_INTERFACE_EL1BEG0" + ], + [ + "PCIE_IMUX4_L_19", + "PCIE_INT_INTERFACE_IMUX_L_OUT4" + ], + [ + "PCIE_NW2A1_19", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_BYP3_L_19", + "INT_INTERFACE_BYP3" + ], + [ + "PCIE_NE4BEG2_19", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_EE2A0_19", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_LOGIC_OUTS_B3_L_19", + "INT_INTERFACE_LOGIC_OUTS_L_B3" + ], + [ + "PCIE_FAN3_L_19", + "INT_INTERFACE_FAN3" + ] + ], + "tile_types": [ + "PCIE_BOT", + "PCIE_INT_INTERFACE_L" + ] + }, + { + "grid_deltas": [ + 1, + -4 + ], + "wire_pairs": [ + [ + "MONITOR_WW4A2_4", + "VFRAME_WW4A2" + ], + [ + "MONITOR_NW4A0_4", + "VFRAME_NW4A0" + ], + [ + "MONITOR_LH11_4", + "VFRAME_LH11" + ], + [ + "MONITOR_FAN0_4", + "VFRAME_FAN0" + ], + [ + "MONITOR_NW4END0_4", + "VFRAME_NW4END0" + ], + [ + "MONITOR_NW4END3_4", + "VFRAME_NW4END3" + ], + [ + "MONITOR_BYP7_4", + "VFRAME_BYP7" + ], + [ + "MONITOR_EE4A2_4", + "VFRAME_EE4A2" + ], + [ + "MONITOR_ER1BEG2_4", + "VFRAME_ER1BEG2" + ], + [ + "MONITOR_CLK1_4", + "VFRAME_CLK1" + ], + [ + "MONITOR_EE2BEG0_4", + "VFRAME_EE2BEG0" + ], + [ + "MONITOR_EE2BEG2_4", + "VFRAME_EE2BEG2" + ], + [ + "MONITOR_IMUX11_4", + "VFRAME_IMUX11" + ], + [ + "MONITOR_IMUX40_4", + "VFRAME_IMUX40" + ], + [ + "MONITOR_IMUX16_4", + "VFRAME_IMUX16" + ], + [ + "MONITOR_FAN4_4", + "VFRAME_FAN4" + ], + [ + "MONITOR_BYP4_4", + "VFRAME_BYP4" + ], + [ + "MONITOR_IMUX8_4", + "VFRAME_IMUX8" + ], + [ + "MONITOR_SW4END0_4", + "VFRAME_SW4END0" + ], + [ + "MONITOR_SW4A3_4", + "VFRAME_SW4A3" + ], + [ + "MONITOR_IMUX36_4", + "VFRAME_IMUX36" + ], + [ + "MONITOR_BYP6_4", + "VFRAME_BYP6" + ], + [ + "MONITOR_IMUX4_4", + "VFRAME_IMUX4" + ], + [ + "MONITOR_NW4A3_4", + "VFRAME_NW4A3" + ], + [ + "MONITOR_NE4BEG3_4", + "VFRAME_NE4BEG3" + ], + [ + "MONITOR_IMUX27_4", + "VFRAME_IMUX27" + ], + [ + "MONITOR_NE4C3_4", + "VFRAME_NE4C3" + ], + [ + "MONITOR_LH9_4", + "VFRAME_LH9" + ], + [ + "MONITOR_IMUX2_4", + "VFRAME_IMUX2" + ], + [ + "MONITOR_SE4BEG1_4", + "VFRAME_SE4BEG1" + ], + [ + "MONITOR_LH3_4", + "VFRAME_LH3" + ], + [ + "MONITOR_EE2A0_4", + "VFRAME_EE2A0" + ], + [ + "MONITOR_EE4C1_4", + "VFRAME_EE4C1" + ], + [ + "MONITOR_IMUX7_4", + "VFRAME_IMUX7" + ], + [ + "MONITOR_LH10_4", + "VFRAME_LH10" + ], + [ + "MONITOR_IMUX28_4", + "VFRAME_IMUX28" + ], + [ + "MONITOR_IMUX24_4", + "VFRAME_IMUX24" + ], + [ + "MONITOR_IMUX33_4", + "VFRAME_IMUX33" + ], + [ + "MONITOR_IMUX30_4", + "VFRAME_IMUX30" + ], + [ + "MONITOR_SW2A3_4", + "VFRAME_SW2A3" + ], + [ + "MONITOR_WR1END3_4", + "VFRAME_WR1END3" + ], + [ + "MONITOR_IMUX31_4", + "VFRAME_IMUX31" + ], + [ + "MONITOR_WW4A3_4", + "VFRAME_WW4A3" + ], + [ + "MONITOR_IMUX22_4", + "VFRAME_IMUX22" + ], + [ + "MONITOR_SW4END2_4", + "VFRAME_SW4END2" + ], + [ + "MONITOR_IMUX10_4", + "VFRAME_IMUX10" + ], + [ + "MONITOR_IMUX25_4", + "VFRAME_IMUX25" + ], + [ + "MONITOR_IMUX45_4", + "VFRAME_IMUX45" + ], + [ + "MONITOR_NW4END1_4", + "VFRAME_NW4END1" + ], + [ + "MONITOR_EE4BEG0_4", + "VFRAME_EE4BEG0" + ], + [ + "MONITOR_FAN3_4", + "VFRAME_FAN3" + ], + [ + "MONITOR_BYP5_4", + "VFRAME_BYP5" + ], + [ + "MONITOR_WW4C2_4", + "VFRAME_WW4C2" + ], + [ + "MONITOR_EE4B3_4", + "VFRAME_EE4B3" + ], + [ + "MONITOR_EE4C3_4", + "VFRAME_EE4C3" + ], + [ + "MONITOR_EE4A0_4", + "VFRAME_EE4A0" + ], + [ + "MONITOR_WW4A1_4", + "VFRAME_WW4A1" + ], + [ + "MONITOR_IMUX14_4", + "VFRAME_IMUX14" + ], + [ + "MONITOR_WW4B2_4", + "VFRAME_WW4B2" + ], + [ + "MONITOR_IMUX17_4", + "VFRAME_IMUX17" + ], + [ + "MONITOR_IMUX19_4", + "VFRAME_IMUX19" + ], + [ + "MONITOR_SE2A2_4", + "VFRAME_SE2A2" + ], + [ + "MONITOR_EE4C2_4", + "VFRAME_EE4C2" + ], + [ + "MONITOR_EE4BEG3_4", + "VFRAME_EE4BEG3" + ], + [ + "MONITOR_SE4BEG2_4", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_LH7_4", + "VFRAME_LH7" + ], + [ + "MONITOR_IMUX21_4", + "VFRAME_IMUX21" + ], + [ + "MONITOR_WW4B0_4", + "VFRAME_WW4B0" + ], + [ + "MONITOR_SW4END1_4", + "VFRAME_SW4END1" + ], + [ + "MONITOR_EE4B1_4", + "VFRAME_EE4B1" + ], + [ + "MONITOR_NE2A1_4", + "VFRAME_NE2A1" + ], + [ + "MONITOR_WW2A0_4", + "VFRAME_WW2A0" + ], + [ + "MONITOR_EE4A3_4", + "VFRAME_EE4A3" + ], + [ + "MONITOR_NE4BEG0_4", + "VFRAME_NE4BEG0" + ], + [ + "MONITOR_WW4B3_4", + "VFRAME_WW4B3" + ], + [ + "MONITOR_IMUX42_4", + "VFRAME_IMUX42" + ], + [ + "MONITOR_CLK0_4", + "VFRAME_CLK0" + ], + [ + "MONITOR_IMUX26_4", + "VFRAME_IMUX26" + ], + [ + "MONITOR_SE4C1_4", + "VFRAME_SE4C1" + ], + [ + "MONITOR_WW2A3_4", + "VFRAME_WW2A3" + ], + [ + "MONITOR_LH5_4", + "VFRAME_LH5" + ], + [ + "MONITOR_SW4A1_4", + "VFRAME_SW4A1" + ], + [ + "MONITOR_FAN2_4", + "VFRAME_FAN2" + ], + [ + "MONITOR_WL1END3_4", + "VFRAME_WL1END3" + ], + [ + "MONITOR_CTRL1_4", + "VFRAME_CTRL1" + ], + [ + "MONITOR_WW4C1_4", + "VFRAME_WW4C1" + ], + [ + "MONITOR_WW4END0_4", + "VFRAME_WW4END0" + ], + [ + "MONITOR_WW4C3_4", + "VFRAME_WW4C3" + ], + [ + "MONITOR_WR1END0_4", + "VFRAME_WR1END0" + ], + [ + "MONITOR_EE4B0_4", + "VFRAME_EE4B0" + ], + [ + "MONITOR_EL1BEG0_4", + "VFRAME_EL1BEG0" + ], + [ + "MONITOR_SE4BEG3_4", + "VFRAME_SE4BEG3" + ], + [ + "MONITOR_SW2A0_4", + "VFRAME_SW2A0" + ], + [ + "MONITOR_FAN1_4", + "VFRAME_FAN1" + ], + [ + "MONITOR_EE2BEG3_4", + "VFRAME_EE2BEG3" + ], + [ + "MONITOR_WW4END2_4", + "VFRAME_WW4END2" + ], + [ + "MONITOR_BYP3_4", + "VFRAME_BYP3" + ], + [ + "MONITOR_EE2A2_4", + "VFRAME_EE2A2" + ], + [ + "MONITOR_WR1END1_4", + "VFRAME_WR1END1" + ], + [ + "MONITOR_NE2A2_4", + "VFRAME_NE2A2" + ], + [ + "MONITOR_SW2A1_4", + "VFRAME_SW2A1" + ], + [ + "MONITOR_IMUX44_4", + "VFRAME_IMUX44" + ], + [ + "MONITOR_SE4C0_4", + "VFRAME_SE4C0" + ], + [ + "MONITOR_EE4BEG2_4", + "VFRAME_EE4BEG2" + ], + [ + "MONITOR_SE2A3_4", + "VFRAME_SE2A3" + ], + [ + "MONITOR_IMUX39_4", + "VFRAME_IMUX39" + ], + [ + "MONITOR_NW2A2_4", + "VFRAME_NW2A2" + ], + [ + "MONITOR_IMUX35_4", + "VFRAME_IMUX35" + ], + [ + "MONITOR_EE4BEG1_4", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX6_4", + "VFRAME_IMUX6" + ], + [ + "MONITOR_BYP2_4", + "VFRAME_BYP2" + ], + [ + "MONITOR_NE4C1_4", + "VFRAME_NE4C1" + ], + [ + "MONITOR_LH12_4", + "VFRAME_LH12" + ], + [ + "MONITOR_NW4END2_4", + "VFRAME_NW4END2" + ], + [ + "MONITOR_SE4C2_4", + "VFRAME_SE4C2" + ], + [ + "MONITOR_NW2A3_4", + "VFRAME_NW2A3" + ], + [ + "MONITOR_IMUX34_4", + "VFRAME_IMUX34" + ], + [ + "MONITOR_LH6_4", + "VFRAME_LH6" + ], + [ + "MONITOR_WW4C0_4", + "VFRAME_WW4C0" + ], + [ + "MONITOR_ER1BEG0_4", + "VFRAME_ER1BEG0" + ], + [ + "MONITOR_NW4A1_4", + "VFRAME_NW4A1" + ], + [ + "MONITOR_IMUX47_4", + "VFRAME_IMUX47" + ], + [ + "MONITOR_LH4_4", + "VFRAME_LH4" + ], + [ + "MONITOR_WW4END1_4", + "VFRAME_WW4END1" + ], + [ + "MONITOR_ER1BEG1_4", + "VFRAME_ER1BEG1" + ], + [ + "MONITOR_IMUX32_4", + "VFRAME_IMUX32" + ], + [ + "MONITOR_FAN5_4", + "VFRAME_FAN5" + ], + [ + "MONITOR_EE4A1_4", + "VFRAME_EE4A1" + ], + [ + "MONITOR_IMUX3_4", + "VFRAME_IMUX3" + ], + [ + "MONITOR_BYP0_4", + "VFRAME_BYP0" + ], + [ + "MONITOR_WW4B1_4", + "VFRAME_WW4B1" + ], + [ + "MONITOR_IMUX43_4", + "VFRAME_IMUX43" + ], + [ + "MONITOR_WW2END3_4", + "VFRAME_WW2END3" + ], + [ + "MONITOR_WL1END2_4", + "VFRAME_WL1END2" + ], + [ + "MONITOR_SW4END3_4", + "VFRAME_SW4END3" + ], + [ + "MONITOR_FAN7_4", + "VFRAME_FAN7" + ], + [ + "MONITOR_WW2A1_4", + "VFRAME_WW2A1" + ], + [ + "MONITOR_NW4A2_4", + "VFRAME_NW4A2" + ], + [ + "MONITOR_SW2A2_4", + "VFRAME_SW2A2" + ], + [ + "MONITOR_IMUX37_4", + "VFRAME_IMUX37" + ], + [ + "MONITOR_NE4C2_4", + "VFRAME_NE4C2" + ], + [ + "MONITOR_EL1BEG1_4", + "VFRAME_EL1BEG1" + ], + [ + "MONITOR_FAN6_4", + "VFRAME_FAN6" + ], + [ + "MONITOR_WW2END1_4", + "VFRAME_WW2END1" + ], + [ + "MONITOR_NE4C0_4", + "VFRAME_NE4C0" + ], + [ + "MONITOR_IMUX0_4", + "VFRAME_IMUX0" + ], + [ + "MONITOR_SW4A2_4", + "VFRAME_SW4A2" + ], + [ + "MONITOR_IMUX46_4", + "VFRAME_IMUX46" + ], + [ + "MONITOR_IMUX13_4", + "VFRAME_IMUX13" + ], + [ + "MONITOR_WL1END1_4", + "VFRAME_WL1END1" + ], + [ + "MONITOR_NE2A0_4", + "VFRAME_NE2A0" + ], + [ + "MONITOR_LH1_4", + "VFRAME_LH1" + ], + [ + "MONITOR_EL1BEG3_4", + "VFRAME_EL1BEG3" + ], + [ + "MONITOR_EE4C0_4", + "VFRAME_EE4C0" + ], + [ + "MONITOR_NE4BEG1_4", + "VFRAME_NE4BEG1" + ], + [ + "MONITOR_WW4A0_4", + "VFRAME_WW4A0" + ], + [ + "MONITOR_SE4BEG0_4", + "VFRAME_SE4BEG0" + ], + [ + "MONITOR_WL1END0_4", + "VFRAME_WL1END0" + ], + [ + "MONITOR_IMUX12_4", + "VFRAME_IMUX12" + ], + [ + "MONITOR_EL1BEG2_4", + "VFRAME_EL1BEG2" + ], + [ + "MONITOR_SE4C3_4", + "VFRAME_SE4C3" + ], + [ + "MONITOR_IMUX41_4", + "VFRAME_IMUX41" + ], + [ + "MONITOR_WW2A2_4", + "VFRAME_WW2A2" + ], + [ + "MONITOR_WW2END2_4", + "VFRAME_WW2END2" + ], + [ + "MONITOR_LH2_4", + "VFRAME_LH2" + ], + [ + "MONITOR_IMUX23_4", + "VFRAME_IMUX23" + ], + [ + "MONITOR_LH8_4", + "VFRAME_LH8" + ], + [ + "MONITOR_IMUX20_4", + "VFRAME_IMUX20" + ], + [ + "MONITOR_IMUX5_4", + "VFRAME_IMUX5" + ], + [ + "MONITOR_WW2END0_4", + "VFRAME_WW2END0" + ], + [ + "MONITOR_BYP1_4", + "VFRAME_BYP1" + ], + [ + "MONITOR_SE2A1_4", + "VFRAME_SE2A1" + ], + [ + "MONITOR_CTRL0_4", + "VFRAME_CTRL0" + ], + [ + "MONITOR_WW4END3_4", + "VFRAME_WW4END3" + ], + [ + "MONITOR_EE4B2_4", + "VFRAME_EE4B2" + ], + [ + "MONITOR_ER1BEG3_4", + "VFRAME_ER1BEG3" + ], + [ + "MONITOR_IMUX1_4", + "VFRAME_IMUX1" + ], + [ + "MONITOR_SE2A0_4", + "VFRAME_SE2A0" + ], + [ + "MONITOR_EE2A3_4", + "VFRAME_EE2A3" + ], + [ + "MONITOR_IMUX18_4", + "VFRAME_IMUX18" + ], + [ + "MONITOR_IMUX15_4", + "VFRAME_IMUX15" + ], + [ + "MONITOR_WR1END2_4", + "VFRAME_WR1END2" + ], + [ + "MONITOR_NW2A0_4", + "VFRAME_NW2A0" + ], + [ + "MONITOR_NW2A1_4", + "VFRAME_NW2A1" + ], + [ + "MONITOR_IMUX29_4", + "VFRAME_IMUX29" + ], + [ + "MONITOR_NE2A3_4", + "VFRAME_NE2A3" + ], + [ + "MONITOR_EE2A1_4", + "VFRAME_EE2A1" + ], + [ + "MONITOR_EE2BEG1_4", + "VFRAME_EE2BEG1" + ], + [ + "MONITOR_NE4BEG2_4", + "VFRAME_NE4BEG2" + ], + [ + "MONITOR_IMUX9_4", + "VFRAME_IMUX9" + ], + [ + "MONITOR_IMUX38_4", + "VFRAME_IMUX38" + ], + [ + "MONITOR_SW4A0_4", + "VFRAME_SW4A0" + ] + ], + "tile_types": [ + "MONITOR_TOP_FUJI2", + "VFRAME" + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "HCLK_SS2END_N0_3", + "SS2END3" + ], + [ + "HCLK_NN6C3", + "NN6C3" + ], + [ + "HCLK_SS2A1", + "SS2A1" + ], + [ + "HCLK_FAN_BOUNCE_S3_6", + "FAN_BOUNCE_S3_6" + ], + [ + "HCLK_NN6E0", + "NN6E0" + ], + [ + "HCLK_NN6D3", + "NN6D3" + ], + [ + "HCLK_SW6C0", + "SW6C0" + ], + [ + "HCLK_NE6B2", + "NE6B2" + ], + [ + "HCLK_SE6E2", + "SE6E2" + ], + [ + "HCLK_NN6D1", + "NN6D1" + ], + [ + "HCLK_SS6A1", + "SS6A1" + ], + [ + "HCLK_NE2BEG3", + "NE2BEG3" + ], + [ + "HCLK_SE6C2", + "SE6C2" + ], + [ + "HCLK_SE6E3", + "SE6E3" + ], + [ + "HCLK_SW6C1", + "SW6C1" + ], + [ + "HCLK_SL1END2", + "SL1END2" + ], + [ + "HCLK_NW2END_S0_0", + "NW2END_S0_0" + ], + [ + "HCLK_SS6END2", + "SS6END2" + ], + [ + "HCLK_NN6END_S1_0", + "NN6END_S1_0" + ], + [ + "HCLK_LV4", + "LV_L4" + ], + [ + "HCLK_SE6C3", + "SE6C3" + ], + [ + "HCLK_NR1BEG1", + "NR1BEG1" + ], + [ + "HCLK_LV15", + "LV_L15" + ], + [ + "HCLK_SE6C0", + "SE6C0" + ], + [ + "HCLK_SS6B1", + "SS6B1" + ], + [ + "HCLK_NE6C0", + "NE6C0" + ], + [ + "HCLK_NE6D3", + "NE6D3" + ], + [ + "HCLK_SW6B2", + "SW6B2" + ], + [ + "HCLK_SW6E1", + "SW6E1" + ], + [ + "HCLK_SS6C0", + "SS6C0" + ], + [ + "HCLK_NE6C3", + "NE6C3" + ], + [ + "HCLK_SW6D0", + "SW6D0" + ], + [ + "HCLK_LEAF_CLK_B_BOTL2", + "GCLK_L_B8" + ], + [ + "HCLK_LVB3", + "LVB_L2" + ], + [ + "HCLK_SS6A0", + "SS6A0" + ], + [ + "HCLK_SS6END1", + "SS6END1" + ], + [ + "HCLK_NR1BEG0", + "NR1BEG0" + ], + [ + "HCLK_NN2BEG0", + "NN2BEG0" + ], + [ + "HCLK_NW2A2", + "NW2BEG2" + ], + [ + "HCLK_SW2END0", + "SW2A0" + ], + [ + "HCLK_NN6A3", + "NN6A3" + ], + [ + "HCLK_SE6E1", + "SE6E1" + ], + [ + "HCLK_SE6D0", + "SE6D0" + ], + [ + "HCLK_LEAF_CLK_B_BOTL5", + "GCLK_L_B11" + ], + [ + "HCLK_NN2BEG3", + "NN2BEG3" + ], + [ + "HCLK_NW6A0", + "NW6A0" + ], + [ + "HCLK_NR1BEG2", + "NR1BEG2" + ], + [ + "HCLK_LV9", + "LV_L9" + ], + [ + "HCLK_NL1BEG1", + "NL1BEG1" + ], + [ + "HCLK_SE6B3", + "SE6B3" + ], + [ + "HCLK_SS6E1", + "SS6E1" + ], + [ + "HCLK_SR1BEG3", + "SR1END3" + ], + [ + "HCLK_SS6C1", + "SS6C1" + ], + [ + "HCLK_LV16", + "LV_L16" + ], + [ + "HCLK_SE6B0", + "SE6B0" + ], + [ + "HCLK_LEAF_CLK_B_BOTL4", + "GCLK_L_B10" + ], + [ + "HCLK_LV7", + "LV_L7" + ], + [ + "HCLK_SE6D3", + "SE6D3" + ], + [ + "HCLK_NE6A0", + "NE6A0" + ], + [ + "HCLK_NE6D2", + "NE6D2" + ], + [ + "HCLK_SE2A1", + "SE2A1" + ], + [ + "HCLK_SS6C3", + "SS6C3" + ], + [ + "HCLK_NL1BEG0", + "NL1BEG0" + ], + [ + "HCLK_LV1", + "LV_L1" + ], + [ + "HCLK_SS6A2", + "SS6A2" + ], + [ + "HCLK_SE2A2", + "SE2A2" + ], + [ + "HCLK_NN2A1", + "NN2A1" + ], + [ + "HCLK_LV12", + "LV_L12" + ], + [ + "HCLK_NN6A2", + "NN6A2" + ], + [ + "HCLK_LVB11", + "LVB_L10" + ], + [ + "HCLK_NN2A3", + "NN2A3" + ], + [ + "HCLK_WR1END_S1_0", + "WR1END_S1_0" + ], + [ + "HCLK_SE6D1", + "SE6D1" + ], + [ + "HCLK_NN2BEG1", + "NN2BEG1" + ], + [ + "HCLK_NW6C2", + "NW6C2" + ], + [ + "HCLK_NW6D3", + "NW6D3" + ], + [ + "HCLK_SR1END2", + "SR1END2" + ], + [ + "HCLK_NN6A0", + "NN6A0" + ], + [ + "HCLK_SS6END0", + "SS6END0" + ], + [ + "HCLK_SE6E0", + "SE6E0" + ], + [ + "HCLK_SE2A0", + "SE2A0" + ], + [ + "HCLK_SS6E2", + "SS6E2" + ], + [ + "HCLK_LVB1", + "LVB_L0" + ], + [ + "HCLK_NE6B3", + "NE6B3" + ], + [ + "HCLK_SE6B1", + "SE6B1" + ], + [ + "HCLK_SW6C3", + "SW6C3" + ], + [ + "HCLK_NW6D0", + "NW6D0" + ], + [ + "HCLK_LVB6", + "LVB_L5" + ], + [ + "HCLK_WL1BEG3", + "WL1BEG3" + ], + [ + "HCLK_LEAF_CLK_B_BOTL0", + "GCLK_L_B6" + ], + [ + "HCLK_WL1END3", + "WL1END3" + ], + [ + "HCLK_SS6B0", + "SS6B0" + ], + [ + "HCLK_SS2END0", + "SS2END0" + ], + [ + "HCLK_SW2END_N0_3", + "SW2END3" + ], + [ + "HCLK_NW6A3", + "NW6A3" + ], + [ + "HCLK_SW6B0", + "SW6B0" + ], + [ + "HCLK_SW6E3", + "SW6E3" + ], + [ + "HCLK_SW6B1", + "SW6B1" + ], + [ + "HCLK_NN2A0", + "NN2A0" + ], + [ + "HCLK_NE6B0", + "NE6B0" + ], + [ + "HCLK_LVB10", + "LVB_L9" + ], + [ + "HCLK_LVB12", + "LVB_L11" + ], + [ + "HCLK_LV11", + "LV_L11" + ], + [ + "HCLK_NW6C3", + "NW6C3" + ], + [ + "HCLK_ER1BEG_S0", + "ER1BEG_S0" + ], + [ + "HCLK_LV6", + "LV_L6" + ], + [ + "HCLK_SW6D3", + "SW6D3" + ], + [ + "HCLK_NN6D0", + "NN6D0" + ], + [ + "HCLK_NE2BEG0", + "NE2BEG0" + ], + [ + "HCLK_NW6C1", + "NW6C1" + ], + [ + "HCLK_SS2END1", + "SS2END1" + ], + [ + "HCLK_NN6BEG0", + "NN6BEG0" + ], + [ + "HCLK_SS6B2", + "SS6B2" + ], + [ + "HCLK_NN6BEG3", + "NN6BEG3" + ], + [ + "HCLK_NN6C2", + "NN6C2" + ], + [ + "HCLK_SR1END1", + "SR1END1" + ], + [ + "HCLK_NW6B1", + "NW6B1" + ], + [ + "HCLK_ER1END3", + "ER1END3" + ], + [ + "HCLK_SW2END2", + "SW2A2" + ], + [ + "HCLK_LVB5", + "LVB_L4" + ], + [ + "HCLK_SR1END_N3_3", + "SR1END3" + ], + [ + "HCLK_NE6C1", + "NE6C1" + ], + [ + "HCLK_SE2A3", + "SE2A3" + ], + [ + "HCLK_EL1END_S3_0", + "EL1END_S3_0" + ], + [ + "HCLK_FAN_BOUNCE_S3_2", + "FAN_BOUNCE_S3_2" + ], + [ + "HCLK_NE6A3", + "NE6A3" + ], + [ + "HCLK_LV17", + "LV_L17" + ], + [ + "HCLK_SS6D2", + "SS6D2" + ], + [ + "HCLK_NE6A1", + "NE6A1" + ], + [ + "HCLK_NW6B3", + "NW6B3" + ], + [ + "HCLK_NN6E1", + "NN6E1" + ], + [ + "HCLK_BYP_BOUNCE6", + "BYP_BOUNCE6" + ], + [ + "HCLK_LV13", + "LV_L13" + ], + [ + "HCLK_NN2BEG2", + "NN2BEG2" + ], + [ + "HCLK_NW6B0", + "NW6B0" + ], + [ + "HCLK_SS6D0", + "SS6D0" + ], + [ + "HCLK_FAN_BOUNCE_S3_4", + "FAN_BOUNCE_S3_4" + ], + [ + "HCLK_WW4END_S0_0", + "WW4END_S0_0" + ], + [ + "HCLK_SS6END_N0_3", + "SS6END3" + ], + [ + "HCLK_NN6BEG1", + "NN6BEG1" + ], + [ + "HCLK_SW6E0", + "SW6E0" + ], + [ + "HCLK_LVB4", + "LVB_L3" + ], + [ + "HCLK_NW2A1", + "NW2BEG1" + ], + [ + "HCLK_LVB9", + "LVB_L8" + ], + [ + "HCLK_SL1END1", + "SL1END1" + ], + [ + "HCLK_SS6E0", + "SS6E0" + ], + [ + "HCLK_LVB8", + "LVB_L7" + ], + [ + "HCLK_WR1BEG_S0", + "WR1BEG_S0" + ], + [ + "HCLK_SS2BEG3", + "SS2A3" + ], + [ + "HCLK_NE6B1", + "NE6B1" + ], + [ + "HCLK_NN6C1", + "NN6C1" + ], + [ + "HCLK_SS6C2", + "SS6C2" + ], + [ + "HCLK_WW2END3", + "WW2END3" + ], + [ + "HCLK_SW2END1", + "SW2A1" + ], + [ + "HCLK_NN6E2", + "NN6E2" + ], + [ + "HCLK_SS6D3", + "SS6D3" + ], + [ + "HCLK_LV3", + "LV_L3" + ], + [ + "HCLK_NW6END_S0_0", + "NW6END_S0_0" + ], + [ + "HCLK_NW6D1", + "NW6D1" + ], + [ + "HCLK_NW2A3", + "NW2BEG3" + ], + [ + "HCLK_SE6B2", + "SE6B2" + ], + [ + "HCLK_NE2BEG1", + "NE2BEG1" + ], + [ + "HCLK_NN6D2", + "NN6D2" + ], + [ + "HCLK_SS2A3", + "SS2END3" + ], + [ + "HCLK_SW6END3", + "SW6END3" + ], + [ + "HCLK_SW6D1", + "SW6D1" + ], + [ + "HCLK_SW6D2", + "SW6D2" + ], + [ + "HCLK_NW6B2", + "NW6B2" + ], + [ + "HCLK_LV0", + "LV_L0" + ], + [ + "HCLK_LV5", + "LV_L5" + ], + [ + "HCLK_SS6B3", + "SS6B3" + ], + [ + "HCLK_SW6E2", + "SW6E2" + ], + [ + "HCLK_NN6B0", + "NN6B0" + ], + [ + "HCLK_LV14", + "LV_L14" + ], + [ + "HCLK_SW6C2", + "SW6C2" + ], + [ + "HCLK_LV10", + "LV_L10" + ], + [ + "HCLK_NN6E3", + "NN6E3" + ], + [ + "HCLK_NE6C2", + "NE6C2" + ], + [ + "HCLK_BYP_BOUNCE2", + "BYP_BOUNCE2" + ], + [ + "HCLK_SS2A0", + "SS2A0" + ], + [ + "HCLK_SW6B3", + "SW6B3" + ], + [ + "HCLK_SS2END2", + "SS2END2" + ], + [ + "HCLK_NL1END_S3_0", + "NL1END_S3_0" + ], + [ + "HCLK_NN6BEG2", + "NN6BEG2" + ], + [ + "HCLK_NW6C0", + "NW6C0" + ], + [ + "HCLK_SE6C1", + "SE6C1" + ], + [ + "HCLK_NN6C0", + "NN6C0" + ], + [ + "HCLK_SE6D2", + "SE6D2" + ], + [ + "HCLK_SS6A3", + "SS6A3" + ], + [ + "HCLK_NR1BEG3", + "NR1BEG3" + ], + [ + "HCLK_LVB7", + "LVB_L6" + ], + [ + "HCLK_SS2A2", + "SS2A2" + ], + [ + "HCLK_NE6A2", + "NE6A2" + ], + [ + "HCLK_SW2A3", + "SW2A3" + ], + [ + "HCLK_NN6B1", + "NN6B1" + ], + [ + "HCLK_NW6A2", + "NW6A2" + ], + [ + "HCLK_NN2END_S2_0", + "NN2END_S2_0" + ], + [ + "HCLK_SS6END3", + "SS6END3" + ], + [ + "HCLK_BYP_BOUNCE7", + "BYP_BOUNCE7" + ], + [ + "HCLK_SL1END3", + "SL1END3" + ], + [ + "HCLK_NE2END_S3_0", + "NE2END_S3_0" + ], + [ + "HCLK_LVB2", + "LVB_L1" + ], + [ + "HCLK_NW6D2", + "NW6D2" + ], + [ + "HCLK_LEAF_CLK_B_BOTL1", + "GCLK_L_B7" + ], + [ + "HCLK_BYP_BOUNCE3", + "BYP_BOUNCE3" + ], + [ + "HCLK_SS6D1", + "SS6D1" + ], + [ + "HCLK_FAN_BOUNCE_S3_0", + "FAN_BOUNCE_S3_0" + ], + [ + "HCLK_EL1BEG3", + "EL1BEG3" + ], + [ + "HCLK_NN6A1", + "NN6A1" + ], + [ + "HCLK_NN2A2", + "NN2A2" + ], + [ + "HCLK_NN6B3", + "NN6B3" + ], + [ + "HCLK_SS6E3", + "SS6E3" + ], + [ + "HCLK_NE6D1", + "NE6D1" + ], + [ + "HCLK_NW2A0", + "NW2BEG0" + ], + [ + "HCLK_NE6D0", + "NE6D0" + ], + [ + "HCLK_LV8", + "LV_L8" + ], + [ + "HCLK_NW6A1", + "NW6A1" + ], + [ + "HCLK_SL1END0", + "SL1END0" + ], + [ + "HCLK_NL1BEG2", + "NL1BEG2" + ], + [ + "HCLK_NN6B2", + "NN6B2" + ], + [ + "HCLK_LEAF_CLK_B_BOTL3", + "GCLK_L_B9" + ], + [ + "HCLK_NE2BEG2", + "NE2BEG2" + ], + [ + "HCLK_LV2", + "LV_L2" + ] + ], + "tile_types": [ + "HCLK_L", + "INT_L" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_FEEDTHRU_2_CK_BUFHCLK5", + "HCLK_FEEDTHRU_2_CK_BUFHCLK5" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN0", + "HCLK_FEEDTHRU_2_CK_IN0" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFHCLK6", + "HCLK_FEEDTHRU_2_CK_BUFHCLK6" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFHCLK9", + "HCLK_FEEDTHRU_2_CK_BUFHCLK9" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFHCLK11", + "HCLK_FEEDTHRU_2_CK_BUFHCLK11" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFHCLK1", + "HCLK_FEEDTHRU_2_CK_BUFHCLK1" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN13", + "HCLK_FEEDTHRU_2_CK_IN13" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN3", + "HCLK_FEEDTHRU_2_CK_IN3" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFHCLK7", + "HCLK_FEEDTHRU_2_CK_BUFHCLK7" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN11", + "HCLK_FEEDTHRU_2_CK_IN11" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN4", + "HCLK_FEEDTHRU_2_CK_IN4" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN9", + "HCLK_FEEDTHRU_2_CK_IN9" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFHCLK8", + "HCLK_FEEDTHRU_2_CK_BUFHCLK8" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN7", + "HCLK_FEEDTHRU_2_CK_IN7" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFHCLK2", + "HCLK_FEEDTHRU_2_CK_BUFHCLK2" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFRCLK2", + "HCLK_FEEDTHRU_2_CK_BUFRCLK2" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFRCLK1", + "HCLK_FEEDTHRU_2_CK_BUFRCLK1" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFHCLK10", + "HCLK_FEEDTHRU_2_CK_BUFHCLK10" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN12", + "HCLK_FEEDTHRU_2_CK_IN12" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFHCLK3", + "HCLK_FEEDTHRU_2_CK_BUFHCLK3" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFHCLK4", + "HCLK_FEEDTHRU_2_CK_BUFHCLK4" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFRCLK3", + "HCLK_FEEDTHRU_2_CK_BUFRCLK3" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN10", + "HCLK_FEEDTHRU_2_CK_IN10" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN2", + "HCLK_FEEDTHRU_2_CK_IN2" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN1", + "HCLK_FEEDTHRU_2_CK_IN1" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN8", + "HCLK_FEEDTHRU_2_CK_IN8" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFHCLK0", + "HCLK_FEEDTHRU_2_CK_BUFHCLK0" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN5", + "HCLK_FEEDTHRU_2_CK_IN5" + ], + [ + "HCLK_FEEDTHRU_2_CK_IN6", + "HCLK_FEEDTHRU_2_CK_IN6" + ], + [ + "HCLK_FEEDTHRU_2_CK_BUFRCLK0", + "HCLK_FEEDTHRU_2_CK_BUFRCLK0" + ] + ], + "tile_types": [ + "HCLK_FEEDTHRU_2", + "HCLK_FEEDTHRU_2" + ] + }, + { + "grid_deltas": [ + 0, + -5 + ], + "wire_pairs": [ + [ + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" + ], + [ + "BRAM_FIFO36_CASCADEOUTB_1", + "HCLK_BRAM_CASCADEB_L" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" + ], + [ + "BRAM_FIFO36_CASCADEOUTA_1", + "HCLK_BRAM_CASCADEA_L" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" + ] + ], + "tile_types": [ + "BRAM_L", + "HCLK_BRAM" + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CK_INOUT_L6", + "HCLK_CK_OUTIN_R2" + ], + [ + "HCLK_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CK_INOUT_L4", + "HCLK_CK_OUTIN_R0" + ], + [ + "HCLK_CK_INOUT_L5", + "HCLK_CK_OUTIN_R1" + ], + [ + "HCLK_CK_INOUT_L0", + "HCLK_CK_OUTIN_R4" + ], + [ + "HCLK_CK_INOUT_L3", + "HCLK_CK_OUTIN_R7" + ], + [ + "HCLK_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CK_INOUT_L7", + "HCLK_CK_OUTIN_R3" + ], + [ + "HCLK_CK_OUTIN_L1", + "HCLK_CK_INOUT_R1" + ], + [ + "HCLK_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CK_OUTIN_L2", + "HCLK_CK_INOUT_R2" + ], + [ + "HCLK_CK_INOUT_L1", + "HCLK_CK_OUTIN_R5" + ], + [ + "HCLK_CK_OUTIN_L4", + "HCLK_CK_INOUT_R4" + ], + [ + "HCLK_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CK_OUTIN_L7", + "HCLK_CK_INOUT_R7" + ], + [ + "HCLK_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CK_OUTIN_L0", + "HCLK_CK_INOUT_R0" + ], + [ + "HCLK_CK_OUTIN_L3", + "HCLK_CK_INOUT_R3" + ], + [ + "HCLK_CK_OUTIN_L5", + "HCLK_CK_INOUT_R5" + ], + [ + "HCLK_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CK_INOUT_L2", + "HCLK_CK_OUTIN_R6" + ], + [ + "HCLK_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CK_OUTIN_L6", + "HCLK_CK_INOUT_R6" + ] + ], + "tile_types": [ + "HCLK_L_BOT_UTURN", + "HCLK_R_BOT_UTURN" + ] + } +] \ No newline at end of file diff --git a/kintex7/tilegrid.json b/kintex7/tilegrid.json index 5df726c..a725942 100644 --- a/kintex7/tilegrid.json +++ b/kintex7/tilegrid.json @@ -1,21522 +1,241013 @@ { - "segments": { - "SEG_BRAM0_L_X6Y50": { - "baseaddr": [ - "0x00400300", - 0 - ], - "frames": 28, - "tiles": [ - "BRAM_L_X6Y50", - "BRAM_INT_INTERFACE_L_X6Y50", - "INT_L_X6Y50" - ], - "type": "bram0_l", - "words": 2 - }, - "SEG_BRAM0_L_X6Y55": { - "baseaddr": [ - "0x00400300", - 10 - ], - "frames": 28, - "tiles": [ - "BRAM_L_X6Y55", - "BRAM_INT_INTERFACE_L_X6Y55", - "INT_L_X6Y55" - ], - "type": "bram0_l", - "words": 2 - }, - "SEG_BRAM0_L_X6Y60": { - "baseaddr": [ - "0x00400300", - 20 - ], - "frames": 28, - "tiles": [ - "BRAM_L_X6Y60", - "BRAM_INT_INTERFACE_L_X6Y60", - "INT_L_X6Y60" - ], - "type": "bram0_l", - "words": 2 - }, - "SEG_BRAM0_L_X6Y65": { - "baseaddr": [ - "0x00400300", - 30 - ], - "frames": 28, - "tiles": [ - "BRAM_L_X6Y65", - "BRAM_INT_INTERFACE_L_X6Y65", - "INT_L_X6Y65" - ], - "type": "bram0_l", - "words": 2 - }, - "SEG_BRAM0_L_X6Y70": { - "baseaddr": [ - "0x00400300", - 40 - ], - "frames": 28, - "tiles": [ - "BRAM_L_X6Y70", - "BRAM_INT_INTERFACE_L_X6Y70", - "INT_L_X6Y70" - ], - "type": "bram0_l", - "words": 2 - }, - "SEG_BRAM0_L_X6Y75": { - "baseaddr": [ - "0x00400300", - 51 - ], - "frames": 28, - "tiles": [ - "BRAM_L_X6Y75", - "BRAM_INT_INTERFACE_L_X6Y75", - "INT_L_X6Y75" - ], - "type": "bram0_l", - "words": 2 - }, - "SEG_BRAM0_L_X6Y80": { - "baseaddr": [ - "0x00400300", - 61 - ], - "frames": 28, - "tiles": [ - "BRAM_L_X6Y80", - "BRAM_INT_INTERFACE_L_X6Y80", - "INT_L_X6Y80" - ], - "type": "bram0_l", - "words": 2 - }, - "SEG_BRAM0_L_X6Y85": { - "baseaddr": [ - "0x00400300", - 71 - ], - "frames": 28, - "tiles": [ - "BRAM_L_X6Y85", - "BRAM_INT_INTERFACE_L_X6Y85", - "INT_L_X6Y85" - ], - "type": "bram0_l", - "words": 2 - }, - "SEG_BRAM0_L_X6Y90": { - "baseaddr": [ - "0x00400300", - 81 - ], - "frames": 28, - "tiles": [ - "BRAM_L_X6Y90", - "BRAM_INT_INTERFACE_L_X6Y90", - "INT_L_X6Y90" - ], - "type": "bram0_l", - "words": 2 - }, - "SEG_BRAM0_L_X6Y95": { - "baseaddr": [ - "0x00400300", - 91 - ], - "frames": 28, - "tiles": [ - "BRAM_L_X6Y95", - "BRAM_INT_INTERFACE_L_X6Y95", - "INT_L_X6Y95" - ], - "type": "bram0_l", - "words": 2 - }, - "SEG_BRAM1_L_X6Y50": { - "baseaddr": [ - "0x00400300", - 2 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y51", - "INT_L_X6Y51" - ], - "type": "bram1_l", - "words": 2 - }, - "SEG_BRAM1_L_X6Y55": { - "baseaddr": [ - "0x00400300", - 12 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y56", - "INT_L_X6Y56" - ], - "type": "bram1_l", - "words": 2 - }, - "SEG_BRAM1_L_X6Y60": { - "baseaddr": [ - "0x00400300", - 22 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y61", - "INT_L_X6Y61" - ], - "type": "bram1_l", - "words": 2 - }, - "SEG_BRAM1_L_X6Y65": { - "baseaddr": [ - "0x00400300", - 32 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y66", - "INT_L_X6Y66" - ], - "type": "bram1_l", - "words": 2 - }, - "SEG_BRAM1_L_X6Y70": { - "baseaddr": [ - "0x00400300", - 42 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y71", - "INT_L_X6Y71" - ], - "type": "bram1_l", - "words": 2 - }, - "SEG_BRAM1_L_X6Y75": { - "baseaddr": [ - "0x00400300", - 53 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y76", - "INT_L_X6Y76" - ], - "type": "bram1_l", - "words": 2 - }, - "SEG_BRAM1_L_X6Y80": { - "baseaddr": [ - "0x00400300", - 63 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y81", - "INT_L_X6Y81" - ], - "type": "bram1_l", - "words": 2 - }, - "SEG_BRAM1_L_X6Y85": { - "baseaddr": [ - "0x00400300", - 73 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y86", - "INT_L_X6Y86" - ], - "type": "bram1_l", - "words": 2 - }, - "SEG_BRAM1_L_X6Y90": { - "baseaddr": [ - "0x00400300", - 83 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y91", - "INT_L_X6Y91" - ], - "type": "bram1_l", - "words": 2 - }, - "SEG_BRAM1_L_X6Y95": { - "baseaddr": [ - "0x00400300", - 93 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y96", - "INT_L_X6Y96" - ], - "type": "bram1_l", - "words": 2 - }, - "SEG_BRAM2_L_X6Y50": { - "baseaddr": [ - "0x00400300", - 4 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y52", - "INT_L_X6Y52" - ], - "type": "bram2_l", - "words": 2 - }, - "SEG_BRAM2_L_X6Y55": { - "baseaddr": [ - "0x00400300", - 14 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y57", - "INT_L_X6Y57" - ], - "type": "bram2_l", - "words": 2 - }, - "SEG_BRAM2_L_X6Y60": { - "baseaddr": [ - "0x00400300", - 24 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y62", - "INT_L_X6Y62" - ], - "type": "bram2_l", - "words": 2 - }, - "SEG_BRAM2_L_X6Y65": { - "baseaddr": [ - "0x00400300", - 34 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y67", - "INT_L_X6Y67" - ], - "type": "bram2_l", - "words": 2 - }, - "SEG_BRAM2_L_X6Y70": { - "baseaddr": [ - "0x00400300", - 44 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y72", - "INT_L_X6Y72" - ], - "type": "bram2_l", - "words": 2 - }, - "SEG_BRAM2_L_X6Y75": { - "baseaddr": [ - "0x00400300", - 55 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y77", - "INT_L_X6Y77" - ], - "type": "bram2_l", - "words": 2 - }, - "SEG_BRAM2_L_X6Y80": { - "baseaddr": [ - "0x00400300", - 65 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y82", - "INT_L_X6Y82" - ], - "type": "bram2_l", - "words": 2 - }, - "SEG_BRAM2_L_X6Y85": { - "baseaddr": [ - "0x00400300", - 75 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y87", - "INT_L_X6Y87" - ], - "type": "bram2_l", - "words": 2 - }, - "SEG_BRAM2_L_X6Y90": { - "baseaddr": [ - "0x00400300", - 85 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y92", - "INT_L_X6Y92" - ], - "type": "bram2_l", - "words": 2 - }, - "SEG_BRAM2_L_X6Y95": { - "baseaddr": [ - "0x00400300", - 95 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y97", - "INT_L_X6Y97" - ], - "type": "bram2_l", - "words": 2 - }, - "SEG_BRAM3_L_X6Y50": { - "baseaddr": [ - "0x00400300", - 6 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y53", - "INT_L_X6Y53" - ], - "type": "bram3_l", - "words": 2 - }, - "SEG_BRAM3_L_X6Y55": { - "baseaddr": [ - "0x00400300", - 16 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y58", - "INT_L_X6Y58" - ], - "type": "bram3_l", - "words": 2 - }, - "SEG_BRAM3_L_X6Y60": { - "baseaddr": [ - "0x00400300", - 26 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y63", - "INT_L_X6Y63" - ], - "type": "bram3_l", - "words": 2 - }, - "SEG_BRAM3_L_X6Y65": { - "baseaddr": [ - "0x00400300", - 36 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y68", - "INT_L_X6Y68" - ], - "type": "bram3_l", - "words": 2 - }, - "SEG_BRAM3_L_X6Y70": { - "baseaddr": [ - "0x00400300", - 46 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y73", - "INT_L_X6Y73" - ], - "type": "bram3_l", - "words": 2 - }, - "SEG_BRAM3_L_X6Y75": { - "baseaddr": [ - "0x00400300", - 57 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y78", - "INT_L_X6Y78" - ], - "type": "bram3_l", - "words": 2 - }, - "SEG_BRAM3_L_X6Y80": { - "baseaddr": [ - "0x00400300", - 67 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y83", - "INT_L_X6Y83" - ], - "type": "bram3_l", - "words": 2 - }, - "SEG_BRAM3_L_X6Y85": { - "baseaddr": [ - "0x00400300", - 77 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y88", - "INT_L_X6Y88" - ], - "type": "bram3_l", - "words": 2 - }, - "SEG_BRAM3_L_X6Y90": { - "baseaddr": [ - "0x00400300", - 87 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y93", - "INT_L_X6Y93" - ], - "type": "bram3_l", - "words": 2 - }, - "SEG_BRAM3_L_X6Y95": { - "baseaddr": [ - "0x00400300", - 97 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y98", - "INT_L_X6Y98" - ], - "type": "bram3_l", - "words": 2 - }, - "SEG_BRAM4_L_X6Y50": { - "baseaddr": [ - "0x00400300", - 8 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y54", - "INT_L_X6Y54" - ], - "type": "bram4_l", - "words": 2 - }, - "SEG_BRAM4_L_X6Y55": { - "baseaddr": [ - "0x00400300", - 18 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y59", - "INT_L_X6Y59" - ], - "type": "bram4_l", - "words": 2 - }, - "SEG_BRAM4_L_X6Y60": { - "baseaddr": [ - "0x00400300", - 28 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y64", - "INT_L_X6Y64" - ], - "type": "bram4_l", - "words": 2 - }, - "SEG_BRAM4_L_X6Y65": { - "baseaddr": [ - "0x00400300", - 38 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y69", - "INT_L_X6Y69" - ], - "type": "bram4_l", - "words": 2 - }, - "SEG_BRAM4_L_X6Y70": { - "baseaddr": [ - "0x00400300", - 48 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y74", - "INT_L_X6Y74" - ], - "type": "bram4_l", - "words": 2 - }, - "SEG_BRAM4_L_X6Y75": { - "baseaddr": [ - "0x00400300", - 59 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y79", - "INT_L_X6Y79" - ], - "type": "bram4_l", - "words": 2 - }, - "SEG_BRAM4_L_X6Y80": { - "baseaddr": [ - "0x00400300", - 69 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y84", - "INT_L_X6Y84" - ], - "type": "bram4_l", - "words": 2 - }, - "SEG_BRAM4_L_X6Y85": { - "baseaddr": [ - "0x00400300", - 79 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y89", - "INT_L_X6Y89" - ], - "type": "bram4_l", - "words": 2 - }, - "SEG_BRAM4_L_X6Y90": { - "baseaddr": [ - "0x00400300", - 89 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y94", - "INT_L_X6Y94" - ], - "type": "bram4_l", - "words": 2 - }, - "SEG_BRAM4_L_X6Y95": { - "baseaddr": [ - "0x00400300", - 99 - ], - "frames": 28, - "tiles": [ - "BRAM_INT_INTERFACE_L_X6Y99", - "INT_L_X6Y99" - ], - "type": "bram4_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y50": { - "baseaddr": [ - "0x00400100", - 0 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y50", - "INT_L_X2Y50" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y51": { - "baseaddr": [ - "0x00400100", - 2 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y51", - "INT_L_X2Y51" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y52": { - "baseaddr": [ - "0x00400100", - 4 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y52", - "INT_L_X2Y52" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y53": { - "baseaddr": [ - "0x00400100", - 6 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y53", - "INT_L_X2Y53" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y54": { - "baseaddr": [ - "0x00400100", - 8 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y54", - "INT_L_X2Y54" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y55": { - "baseaddr": [ - "0x00400100", - 10 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y55", - "INT_L_X2Y55" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y56": { - "baseaddr": [ - "0x00400100", - 12 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y56", - "INT_L_X2Y56" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y57": { - "baseaddr": [ - "0x00400100", - 14 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y57", - "INT_L_X2Y57" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y58": { - "baseaddr": [ - "0x00400100", - 16 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y58", - "INT_L_X2Y58" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y59": { - "baseaddr": [ - "0x00400100", - 18 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y59", - "INT_L_X2Y59" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y60": { - "baseaddr": [ - "0x00400100", - 20 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y60", - "INT_L_X2Y60" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y61": { - "baseaddr": [ - "0x00400100", - 22 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y61", - "INT_L_X2Y61" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y62": { - "baseaddr": [ - "0x00400100", - 24 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y62", - "INT_L_X2Y62" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y63": { - "baseaddr": [ - "0x00400100", - 26 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y63", - "INT_L_X2Y63" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y64": { - "baseaddr": [ - "0x00400100", - 28 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y64", - "INT_L_X2Y64" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y65": { - "baseaddr": [ - "0x00400100", - 30 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y65", - "INT_L_X2Y65" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y66": { - "baseaddr": [ - "0x00400100", - 32 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y66", - "INT_L_X2Y66" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y67": { - "baseaddr": [ - "0x00400100", - 34 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y67", - "INT_L_X2Y67" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y68": { - "baseaddr": [ - "0x00400100", - 36 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y68", - "INT_L_X2Y68" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y69": { - "baseaddr": [ - "0x00400100", - 38 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y69", - "INT_L_X2Y69" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y70": { - "baseaddr": [ - "0x00400100", - 40 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y70", - "INT_L_X2Y70" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y71": { - "baseaddr": [ - "0x00400100", - 42 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y71", - "INT_L_X2Y71" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y72": { - "baseaddr": [ - "0x00400100", - 44 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y72", - "INT_L_X2Y72" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y73": { - "baseaddr": [ - "0x00400100", - 46 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y73", - "INT_L_X2Y73" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y74": { - "baseaddr": [ - "0x00400100", - 48 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y74", - "INT_L_X2Y74" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y75": { - "baseaddr": [ - "0x00400100", - 51 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y75", - "INT_L_X2Y75" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y76": { - "baseaddr": [ - "0x00400100", - 53 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y76", - "INT_L_X2Y76" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y77": { - "baseaddr": [ - "0x00400100", - 55 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y77", - "INT_L_X2Y77" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y78": { - "baseaddr": [ - "0x00400100", - 57 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y78", - "INT_L_X2Y78" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y79": { - "baseaddr": [ - "0x00400100", - 59 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y79", - "INT_L_X2Y79" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y80": { - "baseaddr": [ - "0x00400100", - 61 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y80", - "INT_L_X2Y80" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y81": { - "baseaddr": [ - "0x00400100", - 63 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y81", - "INT_L_X2Y81" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y82": { - "baseaddr": [ - "0x00400100", - 65 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y82", - "INT_L_X2Y82" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y83": { - "baseaddr": [ - "0x00400100", - 67 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y83", - "INT_L_X2Y83" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y84": { - "baseaddr": [ - "0x00400100", - 69 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y84", - "INT_L_X2Y84" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y85": { - "baseaddr": [ - "0x00400100", - 71 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y85", - "INT_L_X2Y85" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y86": { - "baseaddr": [ - "0x00400100", - 73 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y86", - "INT_L_X2Y86" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y87": { - "baseaddr": [ - "0x00400100", - 75 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y87", - "INT_L_X2Y87" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y88": { - "baseaddr": [ - "0x00400100", - 77 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y88", - "INT_L_X2Y88" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y89": { - "baseaddr": [ - "0x00400100", - 79 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y89", - "INT_L_X2Y89" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y90": { - "baseaddr": [ - "0x00400100", - 81 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y90", - "INT_L_X2Y90" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y91": { - "baseaddr": [ - "0x00400100", - 83 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y91", - "INT_L_X2Y91" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y92": { - "baseaddr": [ - "0x00400100", - 85 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y92", - "INT_L_X2Y92" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y93": { - "baseaddr": [ - "0x00400100", - 87 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y93", - "INT_L_X2Y93" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y94": { - "baseaddr": [ - "0x00400100", - 89 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y94", - "INT_L_X2Y94" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y95": { - "baseaddr": [ - "0x00400100", - 91 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y95", - "INT_L_X2Y95" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y96": { - "baseaddr": [ - "0x00400100", - 93 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y96", - "INT_L_X2Y96" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y97": { - "baseaddr": [ - "0x00400100", - 95 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y97", - "INT_L_X2Y97" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y98": { - "baseaddr": [ - "0x00400100", - 97 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y98", - "INT_L_X2Y98" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X2Y99": { - "baseaddr": [ - "0x00400100", - 99 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X2Y99", - "INT_L_X2Y99" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y50": { - "baseaddr": [ - "0x00400200", - 0 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y50", - "INT_L_X4Y50" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y51": { - "baseaddr": [ - "0x00400200", - 2 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y51", - "INT_L_X4Y51" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y52": { - "baseaddr": [ - "0x00400200", - 4 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y52", - "INT_L_X4Y52" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y53": { - "baseaddr": [ - "0x00400200", - 6 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y53", - "INT_L_X4Y53" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y54": { - "baseaddr": [ - "0x00400200", - 8 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y54", - "INT_L_X4Y54" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y55": { - "baseaddr": [ - "0x00400200", - 10 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y55", - "INT_L_X4Y55" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y56": { - "baseaddr": [ - "0x00400200", - 12 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y56", - "INT_L_X4Y56" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y57": { - "baseaddr": [ - "0x00400200", - 14 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y57", - "INT_L_X4Y57" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y58": { - "baseaddr": [ - "0x00400200", - 16 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y58", - "INT_L_X4Y58" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y59": { - "baseaddr": [ - "0x00400200", - 18 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y59", - "INT_L_X4Y59" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y60": { - "baseaddr": [ - "0x00400200", - 20 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y60", - "INT_L_X4Y60" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y61": { - "baseaddr": [ - "0x00400200", - 22 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y61", - "INT_L_X4Y61" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y62": { - "baseaddr": [ - "0x00400200", - 24 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y62", - "INT_L_X4Y62" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y63": { - "baseaddr": [ - "0x00400200", - 26 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y63", - "INT_L_X4Y63" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y64": { - "baseaddr": [ - "0x00400200", - 28 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y64", - "INT_L_X4Y64" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y65": { - "baseaddr": [ - "0x00400200", - 30 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y65", - "INT_L_X4Y65" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y66": { - "baseaddr": [ - "0x00400200", - 32 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y66", - "INT_L_X4Y66" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y67": { - "baseaddr": [ - "0x00400200", - 34 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y67", - "INT_L_X4Y67" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y68": { - "baseaddr": [ - "0x00400200", - 36 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y68", - "INT_L_X4Y68" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y69": { - "baseaddr": [ - "0x00400200", - 38 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y69", - "INT_L_X4Y69" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y70": { - "baseaddr": [ - "0x00400200", - 40 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y70", - "INT_L_X4Y70" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y71": { - "baseaddr": [ - "0x00400200", - 42 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y71", - "INT_L_X4Y71" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y72": { - "baseaddr": [ - "0x00400200", - 44 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y72", - "INT_L_X4Y72" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y73": { - "baseaddr": [ - "0x00400200", - 46 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y73", - "INT_L_X4Y73" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y74": { - "baseaddr": [ - "0x00400200", - 48 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y74", - "INT_L_X4Y74" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y75": { - "baseaddr": [ - "0x00400200", - 51 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y75", - "INT_L_X4Y75" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y76": { - "baseaddr": [ - "0x00400200", - 53 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y76", - "INT_L_X4Y76" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y77": { - "baseaddr": [ - "0x00400200", - 55 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y77", - "INT_L_X4Y77" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y78": { - "baseaddr": [ - "0x00400200", - 57 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y78", - "INT_L_X4Y78" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y79": { - "baseaddr": [ - "0x00400200", - 59 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y79", - "INT_L_X4Y79" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y80": { - "baseaddr": [ - "0x00400200", - 61 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y80", - "INT_L_X4Y80" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y81": { - "baseaddr": [ - "0x00400200", - 63 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y81", - "INT_L_X4Y81" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y82": { - "baseaddr": [ - "0x00400200", - 65 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y82", - "INT_L_X4Y82" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y83": { - "baseaddr": [ - "0x00400200", - 67 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y83", - "INT_L_X4Y83" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y84": { - "baseaddr": [ - "0x00400200", - 69 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y84", - "INT_L_X4Y84" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y85": { - "baseaddr": [ - "0x00400200", - 71 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y85", - "INT_L_X4Y85" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y86": { - "baseaddr": [ - "0x00400200", - 73 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y86", - "INT_L_X4Y86" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y87": { - "baseaddr": [ - "0x00400200", - 75 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y87", - "INT_L_X4Y87" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y88": { - "baseaddr": [ - "0x00400200", - 77 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y88", - "INT_L_X4Y88" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y89": { - "baseaddr": [ - "0x00400200", - 79 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y89", - "INT_L_X4Y89" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y90": { - "baseaddr": [ - "0x00400200", - 81 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y90", - "INT_L_X4Y90" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y91": { - "baseaddr": [ - "0x00400200", - 83 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y91", - "INT_L_X4Y91" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y92": { - "baseaddr": [ - "0x00400200", - 85 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y92", - "INT_L_X4Y92" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y93": { - "baseaddr": [ - "0x00400200", - 87 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y93", - "INT_L_X4Y93" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y94": { - "baseaddr": [ - "0x00400200", - 89 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y94", - "INT_L_X4Y94" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y95": { - "baseaddr": [ - "0x00400200", - 91 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y95", - "INT_L_X4Y95" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y96": { - "baseaddr": [ - "0x00400200", - 93 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y96", - "INT_L_X4Y96" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y97": { - "baseaddr": [ - "0x00400200", - 95 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y97", - "INT_L_X4Y97" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y98": { - "baseaddr": [ - "0x00400200", - 97 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y98", - "INT_L_X4Y98" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLL_L_X4Y99": { - "baseaddr": [ - "0x00400200", - 99 - ], - "frames": 36, - "tiles": [ - "CLBLL_L_X4Y99", - "INT_L_X4Y99" - ], - "type": "clbll_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y50": { - "baseaddr": [ - "0x00400500", - 0 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y50", - "INT_L_X10Y50" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y51": { - "baseaddr": [ - "0x00400500", - 2 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y51", - "INT_L_X10Y51" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y52": { - "baseaddr": [ - "0x00400500", - 4 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y52", - "INT_L_X10Y52" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y53": { - "baseaddr": [ - "0x00400500", - 6 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y53", - "INT_L_X10Y53" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y54": { - "baseaddr": [ - "0x00400500", - 8 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y54", - "INT_L_X10Y54" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y55": { - "baseaddr": [ - "0x00400500", - 10 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y55", - "INT_L_X10Y55" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y56": { - "baseaddr": [ - "0x00400500", - 12 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y56", - "INT_L_X10Y56" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y57": { - "baseaddr": [ - "0x00400500", - 14 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y57", - "INT_L_X10Y57" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y58": { - "baseaddr": [ - "0x00400500", - 16 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y58", - "INT_L_X10Y58" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y59": { - "baseaddr": [ - "0x00400500", - 18 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y59", - "INT_L_X10Y59" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y60": { - "baseaddr": [ - "0x00400500", - 20 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y60", - "INT_L_X10Y60" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y61": { - "baseaddr": [ - "0x00400500", - 22 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y61", - "INT_L_X10Y61" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y62": { - "baseaddr": [ - "0x00400500", - 24 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y62", - "INT_L_X10Y62" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y63": { - "baseaddr": [ - "0x00400500", - 26 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y63", - "INT_L_X10Y63" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y64": { - "baseaddr": [ - "0x00400500", - 28 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y64", - "INT_L_X10Y64" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y65": { - "baseaddr": [ - "0x00400500", - 30 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y65", - "INT_L_X10Y65" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y66": { - "baseaddr": [ - "0x00400500", - 32 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y66", - "INT_L_X10Y66" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y67": { - "baseaddr": [ - "0x00400500", - 34 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y67", - "INT_L_X10Y67" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y68": { - "baseaddr": [ - "0x00400500", - 36 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y68", - "INT_L_X10Y68" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y69": { - "baseaddr": [ - "0x00400500", - 38 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y69", - "INT_L_X10Y69" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y70": { - "baseaddr": [ - "0x00400500", - 40 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y70", - "INT_L_X10Y70" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y71": { - "baseaddr": [ - "0x00400500", - 42 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y71", - "INT_L_X10Y71" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y72": { - "baseaddr": [ - "0x00400500", - 44 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y72", - "INT_L_X10Y72" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y73": { - "baseaddr": [ - "0x00400500", - 46 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y73", - "INT_L_X10Y73" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y74": { - "baseaddr": [ - "0x00400500", - 48 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y74", - "INT_L_X10Y74" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y75": { - "baseaddr": [ - "0x00400500", - 51 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y75", - "INT_L_X10Y75" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y76": { - "baseaddr": [ - "0x00400500", - 53 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y76", - "INT_L_X10Y76" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y77": { - "baseaddr": [ - "0x00400500", - 55 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y77", - "INT_L_X10Y77" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y78": { - "baseaddr": [ - "0x00400500", - 57 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y78", - "INT_L_X10Y78" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y79": { - "baseaddr": [ - "0x00400500", - 59 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y79", - "INT_L_X10Y79" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y80": { - "baseaddr": [ - "0x00400500", - 61 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y80", - "INT_L_X10Y80" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y81": { - "baseaddr": [ - "0x00400500", - 63 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y81", - "INT_L_X10Y81" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y82": { - "baseaddr": [ - "0x00400500", - 65 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y82", - "INT_L_X10Y82" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y83": { - "baseaddr": [ - "0x00400500", - 67 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y83", - "INT_L_X10Y83" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y84": { - "baseaddr": [ - "0x00400500", - 69 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y84", - "INT_L_X10Y84" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y85": { - "baseaddr": [ - "0x00400500", - 71 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y85", - "INT_L_X10Y85" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y86": { - "baseaddr": [ - "0x00400500", - 73 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y86", - "INT_L_X10Y86" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y87": { - "baseaddr": [ - "0x00400500", - 75 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y87", - "INT_L_X10Y87" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y88": { - "baseaddr": [ - "0x00400500", - 77 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y88", - "INT_L_X10Y88" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y89": { - "baseaddr": [ - "0x00400500", - 79 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y89", - "INT_L_X10Y89" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y90": { - "baseaddr": [ - "0x00400500", - 81 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y90", - "INT_L_X10Y90" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y91": { - "baseaddr": [ - "0x00400500", - 83 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y91", - "INT_L_X10Y91" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y92": { - "baseaddr": [ - "0x00400500", - 85 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y92", - "INT_L_X10Y92" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y93": { - "baseaddr": [ - "0x00400500", - 87 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y93", - "INT_L_X10Y93" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y94": { - "baseaddr": [ - "0x00400500", - 89 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y94", - "INT_L_X10Y94" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y95": { - "baseaddr": [ - "0x00400500", - 91 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y95", - "INT_L_X10Y95" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y96": { - "baseaddr": [ - "0x00400500", - 93 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y96", - "INT_L_X10Y96" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y97": { - "baseaddr": [ - "0x00400500", - 95 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y97", - "INT_L_X10Y97" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y98": { - "baseaddr": [ - "0x00400500", - 97 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y98", - "INT_L_X10Y98" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X10Y99": { - "baseaddr": [ - "0x00400500", - 99 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X10Y99", - "INT_L_X10Y99" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y50": { - "baseaddr": [ - "0x00400600", - 0 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y50", - "INT_L_X12Y50" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y51": { - "baseaddr": [ - "0x00400600", - 2 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y51", - "INT_L_X12Y51" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y52": { - "baseaddr": [ - "0x00400600", - 4 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y52", - "INT_L_X12Y52" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y53": { - "baseaddr": [ - "0x00400600", - 6 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y53", - "INT_L_X12Y53" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y54": { - "baseaddr": [ - "0x00400600", - 8 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y54", - "INT_L_X12Y54" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y55": { - "baseaddr": [ - "0x00400600", - 10 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y55", - "INT_L_X12Y55" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y56": { - "baseaddr": [ - "0x00400600", - 12 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y56", - "INT_L_X12Y56" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y57": { - "baseaddr": [ - "0x00400600", - 14 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y57", - "INT_L_X12Y57" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y58": { - "baseaddr": [ - "0x00400600", - 16 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y58", - "INT_L_X12Y58" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y59": { - "baseaddr": [ - "0x00400600", - 18 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y59", - "INT_L_X12Y59" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y60": { - "baseaddr": [ - "0x00400600", - 20 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y60", - "INT_L_X12Y60" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y61": { - "baseaddr": [ - "0x00400600", - 22 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y61", - "INT_L_X12Y61" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y62": { - "baseaddr": [ - "0x00400600", - 24 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y62", - "INT_L_X12Y62" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y63": { - "baseaddr": [ - "0x00400600", - 26 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y63", - "INT_L_X12Y63" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y64": { - "baseaddr": [ - "0x00400600", - 28 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y64", - "INT_L_X12Y64" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y65": { - "baseaddr": [ - "0x00400600", - 30 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y65", - "INT_L_X12Y65" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y66": { - "baseaddr": [ - "0x00400600", - 32 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y66", - "INT_L_X12Y66" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y67": { - "baseaddr": [ - "0x00400600", - 34 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y67", - "INT_L_X12Y67" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y68": { - "baseaddr": [ - "0x00400600", - 36 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y68", - "INT_L_X12Y68" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y69": { - "baseaddr": [ - "0x00400600", - 38 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y69", - "INT_L_X12Y69" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y70": { - "baseaddr": [ - "0x00400600", - 40 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y70", - "INT_L_X12Y70" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y71": { - "baseaddr": [ - "0x00400600", - 42 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y71", - "INT_L_X12Y71" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y72": { - "baseaddr": [ - "0x00400600", - 44 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y72", - "INT_L_X12Y72" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y73": { - "baseaddr": [ - "0x00400600", - 46 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y73", - "INT_L_X12Y73" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y74": { - "baseaddr": [ - "0x00400600", - 48 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y74", - "INT_L_X12Y74" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y75": { - "baseaddr": [ - "0x00400600", - 51 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y75", - "INT_L_X12Y75" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y76": { - "baseaddr": [ - "0x00400600", - 53 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y76", - "INT_L_X12Y76" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y77": { - "baseaddr": [ - "0x00400600", - 55 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y77", - "INT_L_X12Y77" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y78": { - "baseaddr": [ - "0x00400600", - 57 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y78", - "INT_L_X12Y78" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y79": { - "baseaddr": [ - "0x00400600", - 59 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y79", - "INT_L_X12Y79" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y80": { - "baseaddr": [ - "0x00400600", - 61 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y80", - "INT_L_X12Y80" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y81": { - "baseaddr": [ - "0x00400600", - 63 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y81", - "INT_L_X12Y81" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y82": { - "baseaddr": [ - "0x00400600", - 65 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y82", - "INT_L_X12Y82" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y83": { - "baseaddr": [ - "0x00400600", - 67 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y83", - "INT_L_X12Y83" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y84": { - "baseaddr": [ - "0x00400600", - 69 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y84", - "INT_L_X12Y84" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y85": { - "baseaddr": [ - "0x00400600", - 71 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y85", - "INT_L_X12Y85" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y86": { - "baseaddr": [ - "0x00400600", - 73 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y86", - "INT_L_X12Y86" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y87": { - "baseaddr": [ - "0x00400600", - 75 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y87", - "INT_L_X12Y87" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y88": { - "baseaddr": [ - "0x00400600", - 77 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y88", - "INT_L_X12Y88" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y89": { - "baseaddr": [ - "0x00400600", - 79 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y89", - "INT_L_X12Y89" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y90": { - "baseaddr": [ - "0x00400600", - 81 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y90", - "INT_L_X12Y90" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y91": { - "baseaddr": [ - "0x00400600", - 83 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y91", - "INT_L_X12Y91" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y92": { - "baseaddr": [ - "0x00400600", - 85 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y92", - "INT_L_X12Y92" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y93": { - "baseaddr": [ - "0x00400600", - 87 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y93", - "INT_L_X12Y93" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y94": { - "baseaddr": [ - "0x00400600", - 89 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y94", - "INT_L_X12Y94" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y95": { - "baseaddr": [ - "0x00400600", - 91 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y95", - "INT_L_X12Y95" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y96": { - "baseaddr": [ - "0x00400600", - 93 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y96", - "INT_L_X12Y96" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y97": { - "baseaddr": [ - "0x00400600", - 95 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y97", - "INT_L_X12Y97" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y98": { - "baseaddr": [ - "0x00400600", - 97 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y98", - "INT_L_X12Y98" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X12Y99": { - "baseaddr": [ - "0x00400600", - 99 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X12Y99", - "INT_L_X12Y99" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y50": { - "baseaddr": [ - "0x00400400", - 0 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y50", - "INT_L_X8Y50" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y51": { - "baseaddr": [ - "0x00400400", - 2 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y51", - "INT_L_X8Y51" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y52": { - "baseaddr": [ - "0x00400400", - 4 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y52", - "INT_L_X8Y52" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y53": { - "baseaddr": [ - "0x00400400", - 6 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y53", - "INT_L_X8Y53" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y54": { - "baseaddr": [ - "0x00400400", - 8 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y54", - "INT_L_X8Y54" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y55": { - "baseaddr": [ - "0x00400400", - 10 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y55", - "INT_L_X8Y55" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y56": { - "baseaddr": [ - "0x00400400", - 12 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y56", - "INT_L_X8Y56" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y57": { - "baseaddr": [ - "0x00400400", - 14 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y57", - "INT_L_X8Y57" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y58": { - "baseaddr": [ - "0x00400400", - 16 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y58", - "INT_L_X8Y58" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y59": { - "baseaddr": [ - "0x00400400", - 18 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y59", - "INT_L_X8Y59" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y60": { - "baseaddr": [ - "0x00400400", - 20 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y60", - "INT_L_X8Y60" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y61": { - "baseaddr": [ - "0x00400400", - 22 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y61", - "INT_L_X8Y61" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y62": { - "baseaddr": [ - "0x00400400", - 24 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y62", - "INT_L_X8Y62" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y63": { - "baseaddr": [ - "0x00400400", - 26 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y63", - "INT_L_X8Y63" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y64": { - "baseaddr": [ - "0x00400400", - 28 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y64", - "INT_L_X8Y64" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y65": { - "baseaddr": [ - "0x00400400", - 30 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y65", - "INT_L_X8Y65" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y66": { - "baseaddr": [ - "0x00400400", - 32 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y66", - "INT_L_X8Y66" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y67": { - "baseaddr": [ - "0x00400400", - 34 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y67", - "INT_L_X8Y67" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y68": { - "baseaddr": [ - "0x00400400", - 36 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y68", - "INT_L_X8Y68" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y69": { - "baseaddr": [ - "0x00400400", - 38 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y69", - "INT_L_X8Y69" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y70": { - "baseaddr": [ - "0x00400400", - 40 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y70", - "INT_L_X8Y70" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y71": { - "baseaddr": [ - "0x00400400", - 42 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y71", - "INT_L_X8Y71" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y72": { - "baseaddr": [ - "0x00400400", - 44 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y72", - "INT_L_X8Y72" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y73": { - "baseaddr": [ - "0x00400400", - 46 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y73", - "INT_L_X8Y73" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y74": { - "baseaddr": [ - "0x00400400", - 48 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y74", - "INT_L_X8Y74" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y75": { - "baseaddr": [ - "0x00400400", - 51 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y75", - "INT_L_X8Y75" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y76": { - "baseaddr": [ - "0x00400400", - 53 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y76", - "INT_L_X8Y76" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y77": { - "baseaddr": [ - "0x00400400", - 55 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y77", - "INT_L_X8Y77" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y78": { - "baseaddr": [ - "0x00400400", - 57 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y78", - "INT_L_X8Y78" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y79": { - "baseaddr": [ - "0x00400400", - 59 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y79", - "INT_L_X8Y79" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y80": { - "baseaddr": [ - "0x00400400", - 61 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y80", - "INT_L_X8Y80" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y81": { - "baseaddr": [ - "0x00400400", - 63 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y81", - "INT_L_X8Y81" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y82": { - "baseaddr": [ - "0x00400400", - 65 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y82", - "INT_L_X8Y82" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y83": { - "baseaddr": [ - "0x00400400", - 67 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y83", - "INT_L_X8Y83" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y84": { - "baseaddr": [ - "0x00400400", - 69 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y84", - "INT_L_X8Y84" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y85": { - "baseaddr": [ - "0x00400400", - 71 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y85", - "INT_L_X8Y85" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y86": { - "baseaddr": [ - "0x00400400", - 73 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y86", - "INT_L_X8Y86" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y87": { - "baseaddr": [ - "0x00400400", - 75 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y87", - "INT_L_X8Y87" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y88": { - "baseaddr": [ - "0x00400400", - 77 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y88", - "INT_L_X8Y88" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y89": { - "baseaddr": [ - "0x00400400", - 79 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y89", - "INT_L_X8Y89" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y90": { - "baseaddr": [ - "0x00400400", - 81 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y90", - "INT_L_X8Y90" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y91": { - "baseaddr": [ - "0x00400400", - 83 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y91", - "INT_L_X8Y91" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y92": { - "baseaddr": [ - "0x00400400", - 85 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y92", - "INT_L_X8Y92" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y93": { - "baseaddr": [ - "0x00400400", - 87 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y93", - "INT_L_X8Y93" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y94": { - "baseaddr": [ - "0x00400400", - 89 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y94", - "INT_L_X8Y94" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y95": { - "baseaddr": [ - "0x00400400", - 91 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y95", - "INT_L_X8Y95" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y96": { - "baseaddr": [ - "0x00400400", - 93 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y96", - "INT_L_X8Y96" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y97": { - "baseaddr": [ - "0x00400400", - 95 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y97", - "INT_L_X8Y97" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y98": { - "baseaddr": [ - "0x00400400", - 97 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y98", - "INT_L_X8Y98" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_L_X8Y99": { - "baseaddr": [ - "0x00400400", - 99 - ], - "frames": 36, - "tiles": [ - "CLBLM_L_X8Y99", - "INT_L_X8Y99" - ], - "type": "clblm_l", - "words": 2 - }, - "SEG_CLBLM_R_X11Y50": { - "baseaddr": [ - "0x00400580", - 0 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y50", - "INT_R_X11Y50" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y51": { - "baseaddr": [ - "0x00400580", - 2 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y51", - "INT_R_X11Y51" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y52": { - "baseaddr": [ - "0x00400580", - 4 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y52", - "INT_R_X11Y52" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y53": { - "baseaddr": [ - "0x00400580", - 6 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y53", - "INT_R_X11Y53" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y54": { - "baseaddr": [ - "0x00400580", - 8 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y54", - "INT_R_X11Y54" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y55": { - "baseaddr": [ - "0x00400580", - 10 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y55", - "INT_R_X11Y55" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y56": { - "baseaddr": [ - "0x00400580", - 12 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y56", - "INT_R_X11Y56" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y57": { - "baseaddr": [ - "0x00400580", - 14 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y57", - "INT_R_X11Y57" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y58": { - "baseaddr": [ - "0x00400580", - 16 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y58", - "INT_R_X11Y58" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y59": { - "baseaddr": [ - "0x00400580", - 18 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y59", - "INT_R_X11Y59" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y60": { - "baseaddr": [ - "0x00400580", - 20 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y60", - "INT_R_X11Y60" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y61": { - "baseaddr": [ - "0x00400580", - 22 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y61", - "INT_R_X11Y61" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y62": { - "baseaddr": [ - "0x00400580", - 24 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y62", - "INT_R_X11Y62" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y63": { - "baseaddr": [ - "0x00400580", - 26 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y63", - "INT_R_X11Y63" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y64": { - "baseaddr": [ - "0x00400580", - 28 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y64", - "INT_R_X11Y64" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y65": { - "baseaddr": [ - "0x00400580", - 30 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y65", - "INT_R_X11Y65" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y66": { - "baseaddr": [ - "0x00400580", - 32 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y66", - "INT_R_X11Y66" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y67": { - "baseaddr": [ - "0x00400580", - 34 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y67", - "INT_R_X11Y67" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y68": { - "baseaddr": [ - "0x00400580", - 36 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y68", - "INT_R_X11Y68" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y69": { - "baseaddr": [ - "0x00400580", - 38 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y69", - "INT_R_X11Y69" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y70": { - "baseaddr": [ - "0x00400580", - 40 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y70", - "INT_R_X11Y70" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y71": { - "baseaddr": [ - "0x00400580", - 42 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y71", - "INT_R_X11Y71" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y72": { - "baseaddr": [ - "0x00400580", - 44 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y72", - "INT_R_X11Y72" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y73": { - "baseaddr": [ - "0x00400580", - 46 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y73", - "INT_R_X11Y73" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y74": { - "baseaddr": [ - "0x00400580", - 48 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y74", - "INT_R_X11Y74" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y75": { - "baseaddr": [ - "0x00400580", - 51 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y75", - "INT_R_X11Y75" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y76": { - "baseaddr": [ - "0x00400580", - 53 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y76", - "INT_R_X11Y76" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y77": { - "baseaddr": [ - "0x00400580", - 55 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y77", - "INT_R_X11Y77" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y78": { - "baseaddr": [ - "0x00400580", - 57 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y78", - "INT_R_X11Y78" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y79": { - "baseaddr": [ - "0x00400580", - 59 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y79", - "INT_R_X11Y79" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y80": { - "baseaddr": [ - "0x00400580", - 61 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y80", - "INT_R_X11Y80" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y81": { - "baseaddr": [ - "0x00400580", - 63 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y81", - "INT_R_X11Y81" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y82": { - "baseaddr": [ - "0x00400580", - 65 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y82", - "INT_R_X11Y82" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y83": { - "baseaddr": [ - "0x00400580", - 67 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y83", - "INT_R_X11Y83" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y84": { - "baseaddr": [ - "0x00400580", - 69 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y84", - "INT_R_X11Y84" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y85": { - "baseaddr": [ - "0x00400580", - 71 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y85", - "INT_R_X11Y85" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y86": { - "baseaddr": [ - "0x00400580", - 73 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y86", - "INT_R_X11Y86" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y87": { - "baseaddr": [ - "0x00400580", - 75 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y87", - "INT_R_X11Y87" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y88": { - "baseaddr": [ - "0x00400580", - 77 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y88", - "INT_R_X11Y88" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y89": { - "baseaddr": [ - "0x00400580", - 79 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y89", - "INT_R_X11Y89" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y90": { - "baseaddr": [ - "0x00400580", - 81 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y90", - "INT_R_X11Y90" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y91": { - "baseaddr": [ - "0x00400580", - 83 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y91", - "INT_R_X11Y91" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y92": { - "baseaddr": [ - "0x00400580", - 85 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y92", - "INT_R_X11Y92" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y93": { - "baseaddr": [ - "0x00400580", - 87 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y93", - "INT_R_X11Y93" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y94": { - "baseaddr": [ - "0x00400580", - 89 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y94", - "INT_R_X11Y94" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y95": { - "baseaddr": [ - "0x00400580", - 91 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y95", - "INT_R_X11Y95" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y96": { - "baseaddr": [ - "0x00400580", - 93 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y96", - "INT_R_X11Y96" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y97": { - "baseaddr": [ - "0x00400580", - 95 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y97", - "INT_R_X11Y97" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y98": { - "baseaddr": [ - "0x00400580", - 97 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y98", - "INT_R_X11Y98" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X11Y99": { - "baseaddr": [ - "0x00400580", - 99 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X11Y99", - "INT_R_X11Y99" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y50": { - "baseaddr": [ - "0x00400680", - 0 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y50", - "INT_R_X13Y50" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y51": { - "baseaddr": [ - "0x00400680", - 2 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y51", - "INT_R_X13Y51" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y52": { - "baseaddr": [ - "0x00400680", - 4 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y52", - "INT_R_X13Y52" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y53": { - "baseaddr": [ - "0x00400680", - 6 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y53", - "INT_R_X13Y53" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y54": { - "baseaddr": [ - "0x00400680", - 8 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y54", - "INT_R_X13Y54" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y55": { - "baseaddr": [ - "0x00400680", - 10 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y55", - "INT_R_X13Y55" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y56": { - "baseaddr": [ - "0x00400680", - 12 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y56", - "INT_R_X13Y56" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y57": { - "baseaddr": [ - "0x00400680", - 14 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y57", - "INT_R_X13Y57" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y58": { - "baseaddr": [ - "0x00400680", - 16 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y58", - "INT_R_X13Y58" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y59": { - "baseaddr": [ - "0x00400680", - 18 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y59", - "INT_R_X13Y59" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y60": { - "baseaddr": [ - "0x00400680", - 20 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y60", - "INT_R_X13Y60" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y61": { - "baseaddr": [ - "0x00400680", - 22 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y61", - "INT_R_X13Y61" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y62": { - "baseaddr": [ - "0x00400680", - 24 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y62", - "INT_R_X13Y62" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y63": { - "baseaddr": [ - "0x00400680", - 26 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y63", - "INT_R_X13Y63" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y64": { - "baseaddr": [ - "0x00400680", - 28 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y64", - "INT_R_X13Y64" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y65": { - "baseaddr": [ - "0x00400680", - 30 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y65", - "INT_R_X13Y65" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y66": { - "baseaddr": [ - "0x00400680", - 32 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y66", - "INT_R_X13Y66" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y67": { - "baseaddr": [ - "0x00400680", - 34 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y67", - "INT_R_X13Y67" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y68": { - "baseaddr": [ - "0x00400680", - 36 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y68", - "INT_R_X13Y68" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y69": { - "baseaddr": [ - "0x00400680", - 38 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y69", - "INT_R_X13Y69" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y70": { - "baseaddr": [ - "0x00400680", - 40 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y70", - "INT_R_X13Y70" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y71": { - "baseaddr": [ - "0x00400680", - 42 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y71", - "INT_R_X13Y71" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y72": { - "baseaddr": [ - "0x00400680", - 44 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y72", - "INT_R_X13Y72" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y73": { - "baseaddr": [ - "0x00400680", - 46 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y73", - "INT_R_X13Y73" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y74": { - "baseaddr": [ - "0x00400680", - 48 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y74", - "INT_R_X13Y74" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y75": { - "baseaddr": [ - "0x00400680", - 51 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y75", - "INT_R_X13Y75" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y76": { - "baseaddr": [ - "0x00400680", - 53 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y76", - "INT_R_X13Y76" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y77": { - "baseaddr": [ - "0x00400680", - 55 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y77", - "INT_R_X13Y77" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y78": { - "baseaddr": [ - "0x00400680", - 57 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y78", - "INT_R_X13Y78" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y79": { - "baseaddr": [ - "0x00400680", - 59 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y79", - "INT_R_X13Y79" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y80": { - "baseaddr": [ - "0x00400680", - 61 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y80", - "INT_R_X13Y80" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y81": { - "baseaddr": [ - "0x00400680", - 63 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y81", - "INT_R_X13Y81" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y82": { - "baseaddr": [ - "0x00400680", - 65 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y82", - "INT_R_X13Y82" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y83": { - "baseaddr": [ - "0x00400680", - 67 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y83", - "INT_R_X13Y83" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y84": { - "baseaddr": [ - "0x00400680", - 69 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y84", - "INT_R_X13Y84" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y85": { - "baseaddr": [ - "0x00400680", - 71 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y85", - "INT_R_X13Y85" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y86": { - "baseaddr": [ - "0x00400680", - 73 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y86", - "INT_R_X13Y86" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y87": { - "baseaddr": [ - "0x00400680", - 75 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y87", - "INT_R_X13Y87" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y88": { - "baseaddr": [ - "0x00400680", - 77 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y88", - "INT_R_X13Y88" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y89": { - "baseaddr": [ - "0x00400680", - 79 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y89", - "INT_R_X13Y89" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y90": { - "baseaddr": [ - "0x00400680", - 81 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y90", - "INT_R_X13Y90" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y91": { - "baseaddr": [ - "0x00400680", - 83 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y91", - "INT_R_X13Y91" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y92": { - "baseaddr": [ - "0x00400680", - 85 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y92", - "INT_R_X13Y92" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y93": { - "baseaddr": [ - "0x00400680", - 87 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y93", - "INT_R_X13Y93" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y94": { - "baseaddr": [ - "0x00400680", - 89 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y94", - "INT_R_X13Y94" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y95": { - "baseaddr": [ - "0x00400680", - 91 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y95", - "INT_R_X13Y95" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y96": { - "baseaddr": [ - "0x00400680", - 93 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y96", - "INT_R_X13Y96" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y97": { - "baseaddr": [ - "0x00400680", - 95 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y97", - "INT_R_X13Y97" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y98": { - "baseaddr": [ - "0x00400680", - 97 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y98", - "INT_R_X13Y98" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X13Y99": { - "baseaddr": [ - "0x00400680", - 99 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X13Y99", - "INT_R_X13Y99" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y50": { - "baseaddr": [ - "0x00400180", - 0 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y50", - "INT_R_X3Y50" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y51": { - "baseaddr": [ - "0x00400180", - 2 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y51", - "INT_R_X3Y51" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y52": { - "baseaddr": [ - "0x00400180", - 4 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y52", - "INT_R_X3Y52" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y53": { - "baseaddr": [ - "0x00400180", - 6 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y53", - "INT_R_X3Y53" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y54": { - "baseaddr": [ - "0x00400180", - 8 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y54", - "INT_R_X3Y54" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y55": { - "baseaddr": [ - "0x00400180", - 10 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y55", - "INT_R_X3Y55" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y56": { - "baseaddr": [ - "0x00400180", - 12 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y56", - "INT_R_X3Y56" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y57": { - "baseaddr": [ - "0x00400180", - 14 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y57", - "INT_R_X3Y57" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y58": { - "baseaddr": [ - "0x00400180", - 16 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y58", - "INT_R_X3Y58" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y59": { - "baseaddr": [ - "0x00400180", - 18 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y59", - "INT_R_X3Y59" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y60": { - "baseaddr": [ - "0x00400180", - 20 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y60", - "INT_R_X3Y60" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y61": { - "baseaddr": [ - "0x00400180", - 22 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y61", - "INT_R_X3Y61" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y62": { - "baseaddr": [ - "0x00400180", - 24 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y62", - "INT_R_X3Y62" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y63": { - "baseaddr": [ - "0x00400180", - 26 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y63", - "INT_R_X3Y63" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y64": { - "baseaddr": [ - "0x00400180", - 28 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y64", - "INT_R_X3Y64" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y65": { - "baseaddr": [ - "0x00400180", - 30 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y65", - "INT_R_X3Y65" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y66": { - "baseaddr": [ - "0x00400180", - 32 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y66", - "INT_R_X3Y66" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y67": { - "baseaddr": [ - "0x00400180", - 34 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y67", - "INT_R_X3Y67" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y68": { - "baseaddr": [ - "0x00400180", - 36 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y68", - "INT_R_X3Y68" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y69": { - "baseaddr": [ - "0x00400180", - 38 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y69", - "INT_R_X3Y69" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y70": { - "baseaddr": [ - "0x00400180", - 40 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y70", - "INT_R_X3Y70" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y71": { - "baseaddr": [ - "0x00400180", - 42 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y71", - "INT_R_X3Y71" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y72": { - "baseaddr": [ - "0x00400180", - 44 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y72", - "INT_R_X3Y72" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y73": { - "baseaddr": [ - "0x00400180", - 46 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y73", - "INT_R_X3Y73" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y74": { - "baseaddr": [ - "0x00400180", - 48 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y74", - "INT_R_X3Y74" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y75": { - "baseaddr": [ - "0x00400180", - 51 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y75", - "INT_R_X3Y75" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y76": { - "baseaddr": [ - "0x00400180", - 53 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y76", - "INT_R_X3Y76" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y77": { - "baseaddr": [ - "0x00400180", - 55 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y77", - "INT_R_X3Y77" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y78": { - "baseaddr": [ - "0x00400180", - 57 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y78", - "INT_R_X3Y78" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y79": { - "baseaddr": [ - "0x00400180", - 59 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y79", - "INT_R_X3Y79" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y80": { - "baseaddr": [ - "0x00400180", - 61 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y80", - "INT_R_X3Y80" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y81": { - "baseaddr": [ - "0x00400180", - 63 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y81", - "INT_R_X3Y81" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y82": { - "baseaddr": [ - "0x00400180", - 65 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y82", - "INT_R_X3Y82" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y83": { - "baseaddr": [ - "0x00400180", - 67 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y83", - "INT_R_X3Y83" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y84": { - "baseaddr": [ - "0x00400180", - 69 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y84", - "INT_R_X3Y84" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y85": { - "baseaddr": [ - "0x00400180", - 71 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y85", - "INT_R_X3Y85" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y86": { - "baseaddr": [ - "0x00400180", - 73 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y86", - "INT_R_X3Y86" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y87": { - "baseaddr": [ - "0x00400180", - 75 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y87", - "INT_R_X3Y87" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y88": { - "baseaddr": [ - "0x00400180", - 77 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y88", - "INT_R_X3Y88" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y89": { - "baseaddr": [ - "0x00400180", - 79 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y89", - "INT_R_X3Y89" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y90": { - "baseaddr": [ - "0x00400180", - 81 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y90", - "INT_R_X3Y90" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y91": { - "baseaddr": [ - "0x00400180", - 83 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y91", - "INT_R_X3Y91" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y92": { - "baseaddr": [ - "0x00400180", - 85 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y92", - "INT_R_X3Y92" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y93": { - "baseaddr": [ - "0x00400180", - 87 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y93", - "INT_R_X3Y93" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y94": { - "baseaddr": [ - "0x00400180", - 89 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y94", - "INT_R_X3Y94" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y95": { - "baseaddr": [ - "0x00400180", - 91 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y95", - "INT_R_X3Y95" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y96": { - "baseaddr": [ - "0x00400180", - 93 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y96", - "INT_R_X3Y96" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y97": { - "baseaddr": [ - "0x00400180", - 95 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y97", - "INT_R_X3Y97" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y98": { - "baseaddr": [ - "0x00400180", - 97 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y98", - "INT_R_X3Y98" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X3Y99": { - "baseaddr": [ - "0x00400180", - 99 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X3Y99", - "INT_R_X3Y99" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y50": { - "baseaddr": [ - "0x00400280", - 0 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y50", - "INT_R_X5Y50" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y51": { - "baseaddr": [ - "0x00400280", - 2 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y51", - "INT_R_X5Y51" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y52": { - "baseaddr": [ - "0x00400280", - 4 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y52", - "INT_R_X5Y52" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y53": { - "baseaddr": [ - "0x00400280", - 6 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y53", - "INT_R_X5Y53" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y54": { - "baseaddr": [ - "0x00400280", - 8 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y54", - "INT_R_X5Y54" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y55": { - "baseaddr": [ - "0x00400280", - 10 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y55", - "INT_R_X5Y55" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y56": { - "baseaddr": [ - "0x00400280", - 12 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y56", - "INT_R_X5Y56" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y57": { - "baseaddr": [ - "0x00400280", - 14 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y57", - "INT_R_X5Y57" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y58": { - "baseaddr": [ - "0x00400280", - 16 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y58", - "INT_R_X5Y58" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y59": { - "baseaddr": [ - "0x00400280", - 18 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y59", - "INT_R_X5Y59" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y60": { - "baseaddr": [ - "0x00400280", - 20 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y60", - "INT_R_X5Y60" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y61": { - "baseaddr": [ - "0x00400280", - 22 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y61", - "INT_R_X5Y61" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y62": { - "baseaddr": [ - "0x00400280", - 24 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y62", - "INT_R_X5Y62" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y63": { - "baseaddr": [ - "0x00400280", - 26 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y63", - "INT_R_X5Y63" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y64": { - "baseaddr": [ - "0x00400280", - 28 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y64", - "INT_R_X5Y64" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y65": { - "baseaddr": [ - "0x00400280", - 30 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y65", - "INT_R_X5Y65" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y66": { - "baseaddr": [ - "0x00400280", - 32 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y66", - "INT_R_X5Y66" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y67": { - "baseaddr": [ - "0x00400280", - 34 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y67", - "INT_R_X5Y67" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y68": { - "baseaddr": [ - "0x00400280", - 36 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y68", - "INT_R_X5Y68" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y69": { - "baseaddr": [ - "0x00400280", - 38 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y69", - "INT_R_X5Y69" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y70": { - "baseaddr": [ - "0x00400280", - 40 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y70", - "INT_R_X5Y70" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y71": { - "baseaddr": [ - "0x00400280", - 42 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y71", - "INT_R_X5Y71" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y72": { - "baseaddr": [ - "0x00400280", - 44 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y72", - "INT_R_X5Y72" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y73": { - "baseaddr": [ - "0x00400280", - 46 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y73", - "INT_R_X5Y73" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y74": { - "baseaddr": [ - "0x00400280", - 48 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y74", - "INT_R_X5Y74" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y75": { - "baseaddr": [ - "0x00400280", - 51 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y75", - "INT_R_X5Y75" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y76": { - "baseaddr": [ - "0x00400280", - 53 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y76", - "INT_R_X5Y76" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y77": { - "baseaddr": [ - "0x00400280", - 55 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y77", - "INT_R_X5Y77" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y78": { - "baseaddr": [ - "0x00400280", - 57 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y78", - "INT_R_X5Y78" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y79": { - "baseaddr": [ - "0x00400280", - 59 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y79", - "INT_R_X5Y79" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y80": { - "baseaddr": [ - "0x00400280", - 61 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y80", - "INT_R_X5Y80" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y81": { - "baseaddr": [ - "0x00400280", - 63 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y81", - "INT_R_X5Y81" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y82": { - "baseaddr": [ - "0x00400280", - 65 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y82", - "INT_R_X5Y82" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y83": { - "baseaddr": [ - "0x00400280", - 67 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y83", - "INT_R_X5Y83" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y84": { - "baseaddr": [ - "0x00400280", - 69 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y84", - "INT_R_X5Y84" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y85": { - "baseaddr": [ - "0x00400280", - 71 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y85", - "INT_R_X5Y85" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y86": { - "baseaddr": [ - "0x00400280", - 73 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y86", - "INT_R_X5Y86" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y87": { - "baseaddr": [ - "0x00400280", - 75 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y87", - "INT_R_X5Y87" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y88": { - "baseaddr": [ - "0x00400280", - 77 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y88", - "INT_R_X5Y88" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y89": { - "baseaddr": [ - "0x00400280", - 79 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y89", - "INT_R_X5Y89" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y90": { - "baseaddr": [ - "0x00400280", - 81 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y90", - "INT_R_X5Y90" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y91": { - "baseaddr": [ - "0x00400280", - 83 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y91", - "INT_R_X5Y91" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y92": { - "baseaddr": [ - "0x00400280", - 85 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y92", - "INT_R_X5Y92" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y93": { - "baseaddr": [ - "0x00400280", - 87 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y93", - "INT_R_X5Y93" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y94": { - "baseaddr": [ - "0x00400280", - 89 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y94", - "INT_R_X5Y94" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y95": { - "baseaddr": [ - "0x00400280", - 91 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y95", - "INT_R_X5Y95" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y96": { - "baseaddr": [ - "0x00400280", - 93 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y96", - "INT_R_X5Y96" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y97": { - "baseaddr": [ - "0x00400280", - 95 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y97", - "INT_R_X5Y97" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y98": { - "baseaddr": [ - "0x00400280", - 97 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y98", - "INT_R_X5Y98" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X5Y99": { - "baseaddr": [ - "0x00400280", - 99 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X5Y99", - "INT_R_X5Y99" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y50": { - "baseaddr": [ - "0x00400380", - 0 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y50", - "INT_R_X7Y50" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y51": { - "baseaddr": [ - "0x00400380", - 2 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y51", - "INT_R_X7Y51" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y52": { - "baseaddr": [ - "0x00400380", - 4 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y52", - "INT_R_X7Y52" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y53": { - "baseaddr": [ - "0x00400380", - 6 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y53", - "INT_R_X7Y53" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y54": { - "baseaddr": [ - "0x00400380", - 8 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y54", - "INT_R_X7Y54" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y55": { - "baseaddr": [ - "0x00400380", - 10 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y55", - "INT_R_X7Y55" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y56": { - "baseaddr": [ - "0x00400380", - 12 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y56", - "INT_R_X7Y56" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y57": { - "baseaddr": [ - "0x00400380", - 14 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y57", - "INT_R_X7Y57" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y58": { - "baseaddr": [ - "0x00400380", - 16 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y58", - "INT_R_X7Y58" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y59": { - "baseaddr": [ - "0x00400380", - 18 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y59", - "INT_R_X7Y59" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y60": { - "baseaddr": [ - "0x00400380", - 20 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y60", - "INT_R_X7Y60" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y61": { - "baseaddr": [ - "0x00400380", - 22 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y61", - "INT_R_X7Y61" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y62": { - "baseaddr": [ - "0x00400380", - 24 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y62", - "INT_R_X7Y62" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y63": { - "baseaddr": [ - "0x00400380", - 26 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y63", - "INT_R_X7Y63" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y64": { - "baseaddr": [ - "0x00400380", - 28 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y64", - "INT_R_X7Y64" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y65": { - "baseaddr": [ - "0x00400380", - 30 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y65", - "INT_R_X7Y65" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y66": { - "baseaddr": [ - "0x00400380", - 32 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y66", - "INT_R_X7Y66" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y67": { - "baseaddr": [ - "0x00400380", - 34 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y67", - "INT_R_X7Y67" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y68": { - "baseaddr": [ - "0x00400380", - 36 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y68", - "INT_R_X7Y68" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y69": { - "baseaddr": [ - "0x00400380", - 38 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y69", - "INT_R_X7Y69" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y70": { - "baseaddr": [ - "0x00400380", - 40 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y70", - "INT_R_X7Y70" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y71": { - "baseaddr": [ - "0x00400380", - 42 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y71", - "INT_R_X7Y71" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y72": { - "baseaddr": [ - "0x00400380", - 44 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y72", - "INT_R_X7Y72" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y73": { - "baseaddr": [ - "0x00400380", - 46 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y73", - "INT_R_X7Y73" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y74": { - "baseaddr": [ - "0x00400380", - 48 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y74", - "INT_R_X7Y74" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y75": { - "baseaddr": [ - "0x00400380", - 51 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y75", - "INT_R_X7Y75" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y76": { - "baseaddr": [ - "0x00400380", - 53 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y76", - "INT_R_X7Y76" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y77": { - "baseaddr": [ - "0x00400380", - 55 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y77", - "INT_R_X7Y77" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y78": { - "baseaddr": [ - "0x00400380", - 57 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y78", - "INT_R_X7Y78" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y79": { - "baseaddr": [ - "0x00400380", - 59 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y79", - "INT_R_X7Y79" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y80": { - "baseaddr": [ - "0x00400380", - 61 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y80", - "INT_R_X7Y80" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y81": { - "baseaddr": [ - "0x00400380", - 63 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y81", - "INT_R_X7Y81" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y82": { - "baseaddr": [ - "0x00400380", - 65 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y82", - "INT_R_X7Y82" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y83": { - "baseaddr": [ - "0x00400380", - 67 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y83", - "INT_R_X7Y83" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y84": { - "baseaddr": [ - "0x00400380", - 69 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y84", - "INT_R_X7Y84" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y85": { - "baseaddr": [ - "0x00400380", - 71 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y85", - "INT_R_X7Y85" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y86": { - "baseaddr": [ - "0x00400380", - 73 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y86", - "INT_R_X7Y86" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y87": { - "baseaddr": [ - "0x00400380", - 75 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y87", - "INT_R_X7Y87" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y88": { - "baseaddr": [ - "0x00400380", - 77 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y88", - "INT_R_X7Y88" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y89": { - "baseaddr": [ - "0x00400380", - 79 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y89", - "INT_R_X7Y89" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y90": { - "baseaddr": [ - "0x00400380", - 81 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y90", - "INT_R_X7Y90" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y91": { - "baseaddr": [ - "0x00400380", - 83 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y91", - "INT_R_X7Y91" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y92": { - "baseaddr": [ - "0x00400380", - 85 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y92", - "INT_R_X7Y92" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y93": { - "baseaddr": [ - "0x00400380", - 87 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y93", - "INT_R_X7Y93" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y94": { - "baseaddr": [ - "0x00400380", - 89 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y94", - "INT_R_X7Y94" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y95": { - "baseaddr": [ - "0x00400380", - 91 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y95", - "INT_R_X7Y95" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y96": { - "baseaddr": [ - "0x00400380", - 93 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y96", - "INT_R_X7Y96" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y97": { - "baseaddr": [ - "0x00400380", - 95 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y97", - "INT_R_X7Y97" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y98": { - "baseaddr": [ - "0x00400380", - 97 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y98", - "INT_R_X7Y98" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_CLBLM_R_X7Y99": { - "baseaddr": [ - "0x00400380", - 99 - ], - "frames": 36, - "tiles": [ - "CLBLM_R_X7Y99", - "INT_R_X7Y99" - ], - "type": "clblm_r", - "words": 2 - }, - "SEG_DSP0_R_X9Y50": { - "baseaddr": [ - "0x00400480", - 0 - ], - "frames": 28, - "tiles": [ - "DSP_R_X9Y50", - "INT_INTERFACE_R_X9Y50", - "INT_R_X9Y50" - ], - "type": "dsp0_r", - "words": 2 - }, - "SEG_DSP0_R_X9Y55": { - "baseaddr": [ - "0x00400480", - 10 - ], - "frames": 28, - "tiles": [ - "DSP_R_X9Y55", - "INT_INTERFACE_R_X9Y55", - "INT_R_X9Y55" - ], - "type": "dsp0_r", - "words": 2 - }, - "SEG_DSP0_R_X9Y60": { - "baseaddr": [ - "0x00400480", - 20 - ], - "frames": 28, - "tiles": [ - "DSP_R_X9Y60", - "INT_INTERFACE_R_X9Y60", - "INT_R_X9Y60" - ], - "type": "dsp0_r", - "words": 2 - }, - "SEG_DSP0_R_X9Y65": { - "baseaddr": [ - "0x00400480", - 30 - ], - "frames": 28, - "tiles": [ - "DSP_R_X9Y65", - "INT_INTERFACE_R_X9Y65", - "INT_R_X9Y65" - ], - "type": "dsp0_r", - "words": 2 - }, - "SEG_DSP0_R_X9Y70": { - "baseaddr": [ - "0x00400480", - 40 - ], - "frames": 28, - "tiles": [ - "DSP_R_X9Y70", - "INT_INTERFACE_R_X9Y70", - "INT_R_X9Y70" - ], - "type": "dsp0_r", - "words": 2 - }, - "SEG_DSP0_R_X9Y75": { - "baseaddr": [ - "0x00400480", - 51 - ], - "frames": 28, - "tiles": [ - "DSP_R_X9Y75", - "INT_INTERFACE_R_X9Y75", - "INT_R_X9Y75" - ], - "type": "dsp0_r", - "words": 2 - }, - "SEG_DSP0_R_X9Y80": { - "baseaddr": [ - "0x00400480", - 61 - ], - "frames": 28, - "tiles": [ - "DSP_R_X9Y80", - "INT_INTERFACE_R_X9Y80", - "INT_R_X9Y80" - ], - "type": "dsp0_r", - "words": 2 - }, - "SEG_DSP0_R_X9Y85": { - "baseaddr": [ - "0x00400480", - 71 - ], - "frames": 28, - "tiles": [ - "DSP_R_X9Y85", - "INT_INTERFACE_R_X9Y85", - "INT_R_X9Y85" - ], - "type": "dsp0_r", - "words": 2 - }, - "SEG_DSP0_R_X9Y90": { - "baseaddr": [ - "0x00400480", - 81 - ], - "frames": 28, - "tiles": [ - "DSP_R_X9Y90", - "INT_INTERFACE_R_X9Y90", - "INT_R_X9Y90" - ], - "type": "dsp0_r", - "words": 2 - }, - "SEG_DSP0_R_X9Y95": { - "baseaddr": [ - "0x00400480", - 91 - ], - "frames": 28, - "tiles": [ - "DSP_R_X9Y95", - "INT_INTERFACE_R_X9Y95", - "INT_R_X9Y95" - ], - "type": "dsp0_r", - "words": 2 - }, - "SEG_DSP1_R_X9Y50": { - "baseaddr": [ - "0x00400480", - 2 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y51", - "INT_R_X9Y51" - ], - "type": "dsp1_r", - "words": 2 - }, - "SEG_DSP1_R_X9Y55": { - "baseaddr": [ - "0x00400480", - 12 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y56", - "INT_R_X9Y56" - ], - "type": "dsp1_r", - "words": 2 - }, - "SEG_DSP1_R_X9Y60": { - "baseaddr": [ - "0x00400480", - 22 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y61", - "INT_R_X9Y61" - ], - "type": "dsp1_r", - "words": 2 - }, - "SEG_DSP1_R_X9Y65": { - "baseaddr": [ - "0x00400480", - 32 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y66", - "INT_R_X9Y66" - ], - "type": "dsp1_r", - "words": 2 - }, - "SEG_DSP1_R_X9Y70": { - "baseaddr": [ - "0x00400480", - 42 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y71", - "INT_R_X9Y71" - ], - "type": "dsp1_r", - "words": 2 - }, - "SEG_DSP1_R_X9Y75": { - "baseaddr": [ - "0x00400480", - 53 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y76", - "INT_R_X9Y76" - ], - "type": "dsp1_r", - "words": 2 - }, - "SEG_DSP1_R_X9Y80": { - "baseaddr": [ - "0x00400480", - 63 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y81", - "INT_R_X9Y81" - ], - "type": "dsp1_r", - "words": 2 - }, - "SEG_DSP1_R_X9Y85": { - "baseaddr": [ - "0x00400480", - 73 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y86", - "INT_R_X9Y86" - ], - "type": "dsp1_r", - "words": 2 - }, - "SEG_DSP1_R_X9Y90": { - "baseaddr": [ - "0x00400480", - 83 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y91", - "INT_R_X9Y91" - ], - "type": "dsp1_r", - "words": 2 - }, - "SEG_DSP1_R_X9Y95": { - "baseaddr": [ - "0x00400480", - 93 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y96", - "INT_R_X9Y96" - ], - "type": "dsp1_r", - "words": 2 - }, - "SEG_DSP2_R_X9Y50": { - "baseaddr": [ - "0x00400480", - 4 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y52", - "INT_R_X9Y52" - ], - "type": "dsp2_r", - "words": 2 - }, - "SEG_DSP2_R_X9Y55": { - "baseaddr": [ - "0x00400480", - 14 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y57", - "INT_R_X9Y57" - ], - "type": "dsp2_r", - "words": 2 - }, - "SEG_DSP2_R_X9Y60": { - "baseaddr": [ - "0x00400480", - 24 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y62", - "INT_R_X9Y62" - ], - "type": "dsp2_r", - "words": 2 - }, - "SEG_DSP2_R_X9Y65": { - "baseaddr": [ - "0x00400480", - 34 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y67", - "INT_R_X9Y67" - ], - "type": "dsp2_r", - "words": 2 - }, - "SEG_DSP2_R_X9Y70": { - "baseaddr": [ - "0x00400480", - 44 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y72", - "INT_R_X9Y72" - ], - "type": "dsp2_r", - "words": 2 - }, - "SEG_DSP2_R_X9Y75": { - "baseaddr": [ - "0x00400480", - 55 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y77", - "INT_R_X9Y77" - ], - "type": "dsp2_r", - "words": 2 - }, - "SEG_DSP2_R_X9Y80": { - "baseaddr": [ - "0x00400480", - 65 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y82", - "INT_R_X9Y82" - ], - "type": "dsp2_r", - "words": 2 - }, - "SEG_DSP2_R_X9Y85": { - "baseaddr": [ - "0x00400480", - 75 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y87", - "INT_R_X9Y87" - ], - "type": "dsp2_r", - "words": 2 - }, - "SEG_DSP2_R_X9Y90": { - "baseaddr": [ - "0x00400480", - 85 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y92", - "INT_R_X9Y92" - ], - "type": "dsp2_r", - "words": 2 - }, - "SEG_DSP2_R_X9Y95": { - "baseaddr": [ - "0x00400480", - 95 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y97", - "INT_R_X9Y97" - ], - "type": "dsp2_r", - "words": 2 - }, - "SEG_DSP3_R_X9Y50": { - "baseaddr": [ - "0x00400480", - 6 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y53", - "INT_R_X9Y53" - ], - "type": "dsp3_r", - "words": 2 - }, - "SEG_DSP3_R_X9Y55": { - "baseaddr": [ - "0x00400480", - 16 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y58", - "INT_R_X9Y58" - ], - "type": "dsp3_r", - "words": 2 - }, - "SEG_DSP3_R_X9Y60": { - "baseaddr": [ - "0x00400480", - 26 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y63", - "INT_R_X9Y63" - ], - "type": "dsp3_r", - "words": 2 - }, - "SEG_DSP3_R_X9Y65": { - "baseaddr": [ - "0x00400480", - 36 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y68", - "INT_R_X9Y68" - ], - "type": "dsp3_r", - "words": 2 - }, - "SEG_DSP3_R_X9Y70": { - "baseaddr": [ - "0x00400480", - 46 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y73", - "INT_R_X9Y73" - ], - "type": "dsp3_r", - "words": 2 - }, - "SEG_DSP3_R_X9Y75": { - "baseaddr": [ - "0x00400480", - 57 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y78", - "INT_R_X9Y78" - ], - "type": "dsp3_r", - "words": 2 - }, - "SEG_DSP3_R_X9Y80": { - "baseaddr": [ - "0x00400480", - 67 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y83", - "INT_R_X9Y83" - ], - "type": "dsp3_r", - "words": 2 - }, - "SEG_DSP3_R_X9Y85": { - "baseaddr": [ - "0x00400480", - 77 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y88", - "INT_R_X9Y88" - ], - "type": "dsp3_r", - "words": 2 - }, - "SEG_DSP3_R_X9Y90": { - "baseaddr": [ - "0x00400480", - 87 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y93", - "INT_R_X9Y93" - ], - "type": "dsp3_r", - "words": 2 - }, - "SEG_DSP3_R_X9Y95": { - "baseaddr": [ - "0x00400480", - 97 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y98", - "INT_R_X9Y98" - ], - "type": "dsp3_r", - "words": 2 - }, - "SEG_DSP4_R_X9Y50": { - "baseaddr": [ - "0x00400480", - 8 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y54", - "INT_R_X9Y54" - ], - "type": "dsp4_r", - "words": 2 - }, - "SEG_DSP4_R_X9Y55": { - "baseaddr": [ - "0x00400480", - 18 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y59", - "INT_R_X9Y59" - ], - "type": "dsp4_r", - "words": 2 - }, - "SEG_DSP4_R_X9Y60": { - "baseaddr": [ - "0x00400480", - 28 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y64", - "INT_R_X9Y64" - ], - "type": "dsp4_r", - "words": 2 - }, - "SEG_DSP4_R_X9Y65": { - "baseaddr": [ - "0x00400480", - 38 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y69", - "INT_R_X9Y69" - ], - "type": "dsp4_r", - "words": 2 - }, - "SEG_DSP4_R_X9Y70": { - "baseaddr": [ - "0x00400480", - 48 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y74", - "INT_R_X9Y74" - ], - "type": "dsp4_r", - "words": 2 - }, - "SEG_DSP4_R_X9Y75": { - "baseaddr": [ - "0x00400480", - 59 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y79", - "INT_R_X9Y79" - ], - "type": "dsp4_r", - "words": 2 - }, - "SEG_DSP4_R_X9Y80": { - "baseaddr": [ - "0x00400480", - 69 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y84", - "INT_R_X9Y84" - ], - "type": "dsp4_r", - "words": 2 - }, - "SEG_DSP4_R_X9Y85": { - "baseaddr": [ - "0x00400480", - 79 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y89", - "INT_R_X9Y89" - ], - "type": "dsp4_r", - "words": 2 - }, - "SEG_DSP4_R_X9Y90": { - "baseaddr": [ - "0x00400480", - 89 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y94", - "INT_R_X9Y94" - ], - "type": "dsp4_r", - "words": 2 - }, - "SEG_DSP4_R_X9Y95": { - "baseaddr": [ - "0x00400480", - 99 - ], - "frames": 28, - "tiles": [ - "INT_INTERFACE_R_X9Y99", - "INT_R_X9Y99" - ], - "type": "dsp4_r", - "words": 2 - }, - "SEG_HCLK_L_X11Y78": { - "baseaddr": [ - "0x00400100", - 50 - ], - "frames": 26, - "tiles": [ - "HCLK_L_X11Y78" - ], - "type": "hclk_l", - "words": 1 - }, - "SEG_HCLK_L_X15Y78": { - "baseaddr": [ - "0x00400200", - 50 - ], - "frames": 26, - "tiles": [ - "HCLK_L_X15Y78" - ], - "type": "hclk_l", - "words": 1 - }, - "SEG_HCLK_L_X21Y78": { - "baseaddr": [ - "0x00400300", - 50 - ], - "frames": 26, - "tiles": [ - "HCLK_L_X21Y78" - ], - "type": "hclk_l", - "words": 1 - }, - "SEG_HCLK_L_X25Y78": { - "baseaddr": [ - "0x00400400", - 50 - ], - "frames": 26, - "tiles": [ - "HCLK_L_X25Y78" - ], - "type": "hclk_l", - "words": 1 - }, - "SEG_HCLK_L_X31Y78": { - "baseaddr": [ - "0x00400500", - 50 - ], - "frames": 26, - "tiles": [ - "HCLK_L_X31Y78" - ], - "type": "hclk_l", - "words": 1 - }, - "SEG_HCLK_L_X35Y78": { - "baseaddr": [ - "0x00400600", - 50 - ], - "frames": 26, - "tiles": [ - "HCLK_L_X35Y78" - ], - "type": "hclk_l", - "words": 1 - }, - "SEG_HCLK_R_X12Y78": { - "baseaddr": [ - "0x00400180", - 50 - ], - "frames": 26, - "tiles": [ - "HCLK_R_X12Y78" - ], - "type": "hclk_r", - "words": 1 - }, - "SEG_HCLK_R_X16Y78": { - "baseaddr": [ - "0x00400280", - 50 - ], - "frames": 26, - "tiles": [ - "HCLK_R_X16Y78" - ], - "type": "hclk_r", - "words": 1 - }, - "SEG_HCLK_R_X22Y78": { - "baseaddr": [ - "0x00400380", - 50 - ], - "frames": 26, - "tiles": [ - "HCLK_R_X22Y78" - ], - "type": "hclk_r", - "words": 1 - }, - "SEG_HCLK_R_X26Y78": { - "baseaddr": [ - "0x00400480", - 50 - ], - "frames": 26, - "tiles": [ - "HCLK_R_X26Y78" - ], - "type": "hclk_r", - "words": 1 - }, - "SEG_HCLK_R_X32Y78": { - "baseaddr": [ - "0x00400580", - 50 - ], - "frames": 26, - "tiles": [ - "HCLK_R_X32Y78" - ], - "type": "hclk_r", - "words": 1 - }, - "SEG_HCLK_R_X36Y78": { - "baseaddr": [ - "0x00400680", - 50 - ], - "frames": 26, - "tiles": [ - "HCLK_R_X36Y78" - ], - "type": "hclk_r", - "words": 1 - } - }, - "tiles": { - "BRAM_INT_INTERFACE_L_X6Y50": { - "grid_x": 20, - "grid_y": 155, - "segment": "SEG_BRAM0_L_X6Y50", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y51": { - "grid_x": 20, - "grid_y": 154, - "segment": "SEG_BRAM1_L_X6Y50", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y52": { - "grid_x": 20, - "grid_y": 153, - "segment": "SEG_BRAM2_L_X6Y50", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y53": { - "grid_x": 20, - "grid_y": 152, - "segment": "SEG_BRAM3_L_X6Y50", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y54": { - "grid_x": 20, - "grid_y": 151, - "segment": "SEG_BRAM4_L_X6Y50", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y55": { - "grid_x": 20, - "grid_y": 150, - "segment": "SEG_BRAM0_L_X6Y55", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y56": { - "grid_x": 20, - "grid_y": 149, - "segment": "SEG_BRAM1_L_X6Y55", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y57": { - "grid_x": 20, - "grid_y": 148, - "segment": "SEG_BRAM2_L_X6Y55", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y58": { - "grid_x": 20, - "grid_y": 147, - "segment": "SEG_BRAM3_L_X6Y55", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y59": { - "grid_x": 20, - "grid_y": 146, - "segment": "SEG_BRAM4_L_X6Y55", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y60": { - "grid_x": 20, - "grid_y": 145, - "segment": "SEG_BRAM0_L_X6Y60", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y61": { - "grid_x": 20, - "grid_y": 144, - "segment": "SEG_BRAM1_L_X6Y60", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y62": { - "grid_x": 20, - "grid_y": 143, - "segment": "SEG_BRAM2_L_X6Y60", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y63": { - "grid_x": 20, - "grid_y": 142, - "segment": "SEG_BRAM3_L_X6Y60", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y64": { - "grid_x": 20, - "grid_y": 141, - "segment": "SEG_BRAM4_L_X6Y60", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y65": { - "grid_x": 20, - "grid_y": 140, - "segment": "SEG_BRAM0_L_X6Y65", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y66": { - "grid_x": 20, - "grid_y": 139, - "segment": "SEG_BRAM1_L_X6Y65", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y67": { - "grid_x": 20, - "grid_y": 138, - "segment": "SEG_BRAM2_L_X6Y65", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y68": { - "grid_x": 20, - "grid_y": 137, - "segment": "SEG_BRAM3_L_X6Y65", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y69": { - "grid_x": 20, - "grid_y": 136, - "segment": "SEG_BRAM4_L_X6Y65", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y70": { - "grid_x": 20, - "grid_y": 135, - "segment": "SEG_BRAM0_L_X6Y70", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y71": { - "grid_x": 20, - "grid_y": 134, - "segment": "SEG_BRAM1_L_X6Y70", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y72": { - "grid_x": 20, - "grid_y": 133, - "segment": "SEG_BRAM2_L_X6Y70", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y73": { - "grid_x": 20, - "grid_y": 132, - "segment": "SEG_BRAM3_L_X6Y70", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y74": { - "grid_x": 20, - "grid_y": 131, - "segment": "SEG_BRAM4_L_X6Y70", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y75": { - "grid_x": 20, - "grid_y": 129, - "segment": "SEG_BRAM0_L_X6Y75", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y76": { - "grid_x": 20, - "grid_y": 128, - "segment": "SEG_BRAM1_L_X6Y75", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y77": { - "grid_x": 20, - "grid_y": 127, - "segment": "SEG_BRAM2_L_X6Y75", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y78": { - "grid_x": 20, - "grid_y": 126, - "segment": "SEG_BRAM3_L_X6Y75", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y79": { - "grid_x": 20, - "grid_y": 125, - "segment": "SEG_BRAM4_L_X6Y75", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y80": { - "grid_x": 20, - "grid_y": 124, - "segment": "SEG_BRAM0_L_X6Y80", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y81": { - "grid_x": 20, - "grid_y": 123, - "segment": "SEG_BRAM1_L_X6Y80", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y82": { - "grid_x": 20, - "grid_y": 122, - "segment": "SEG_BRAM2_L_X6Y80", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y83": { - "grid_x": 20, - "grid_y": 121, - "segment": "SEG_BRAM3_L_X6Y80", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y84": { - "grid_x": 20, - "grid_y": 120, - "segment": "SEG_BRAM4_L_X6Y80", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y85": { - "grid_x": 20, - "grid_y": 119, - "segment": "SEG_BRAM0_L_X6Y85", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y86": { - "grid_x": 20, - "grid_y": 118, - "segment": "SEG_BRAM1_L_X6Y85", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y87": { - "grid_x": 20, - "grid_y": 117, - "segment": "SEG_BRAM2_L_X6Y85", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y88": { - "grid_x": 20, - "grid_y": 116, - "segment": "SEG_BRAM3_L_X6Y85", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y89": { - "grid_x": 20, - "grid_y": 115, - "segment": "SEG_BRAM4_L_X6Y85", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y90": { - "grid_x": 20, - "grid_y": 114, - "segment": "SEG_BRAM0_L_X6Y90", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y91": { - "grid_x": 20, - "grid_y": 113, - "segment": "SEG_BRAM1_L_X6Y90", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y92": { - "grid_x": 20, - "grid_y": 112, - "segment": "SEG_BRAM2_L_X6Y90", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y93": { - "grid_x": 20, - "grid_y": 111, - "segment": "SEG_BRAM3_L_X6Y90", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y94": { - "grid_x": 20, - "grid_y": 110, - "segment": "SEG_BRAM4_L_X6Y90", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y95": { - "grid_x": 20, - "grid_y": 109, - "segment": "SEG_BRAM0_L_X6Y95", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y96": { - "grid_x": 20, - "grid_y": 108, - "segment": "SEG_BRAM1_L_X6Y95", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y97": { - "grid_x": 20, - "grid_y": 107, - "segment": "SEG_BRAM2_L_X6Y95", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y98": { - "grid_x": 20, - "grid_y": 106, - "segment": "SEG_BRAM3_L_X6Y95", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_INT_INTERFACE_L_X6Y99": { - "grid_x": 20, - "grid_y": 105, - "segment": "SEG_BRAM4_L_X6Y95", - "sites": {}, - "type": "BRAM_INT_INTERFACE_L" - }, - "BRAM_L_X6Y50": { - "grid_x": 19, - "grid_y": 155, - "segment": "SEG_BRAM0_L_X6Y50", - "sites": { - "RAMB18_X0Y20": "FIFO18E1", - "RAMB18_X0Y21": "RAMB18E1", - "RAMB36_X0Y10": "RAMBFIFO36E1" - }, - "type": "BRAM_L" - }, - "BRAM_L_X6Y55": { - "grid_x": 19, - "grid_y": 150, - "segment": "SEG_BRAM0_L_X6Y55", - "sites": { - "RAMB18_X0Y22": "FIFO18E1", - "RAMB18_X0Y23": "RAMB18E1", - "RAMB36_X0Y11": "RAMBFIFO36E1" - }, - "type": "BRAM_L" - }, - "BRAM_L_X6Y60": { - "grid_x": 19, - "grid_y": 145, - "segment": "SEG_BRAM0_L_X6Y60", - "sites": { - "RAMB18_X0Y24": "FIFO18E1", - "RAMB18_X0Y25": "RAMB18E1", - "RAMB36_X0Y12": "RAMBFIFO36E1" - }, - "type": "BRAM_L" - }, - "BRAM_L_X6Y65": { - "grid_x": 19, - "grid_y": 140, - "segment": "SEG_BRAM0_L_X6Y65", - "sites": { - "RAMB18_X0Y26": "FIFO18E1", - "RAMB18_X0Y27": "RAMB18E1", - "RAMB36_X0Y13": "RAMBFIFO36E1" - }, - "type": "BRAM_L" - }, - "BRAM_L_X6Y70": { - "grid_x": 19, - "grid_y": 135, - "segment": "SEG_BRAM0_L_X6Y70", - "sites": { - "RAMB18_X0Y28": "FIFO18E1", - "RAMB18_X0Y29": "RAMB18E1", - "RAMB36_X0Y14": "RAMBFIFO36E1" - }, - "type": "BRAM_L" - }, - "BRAM_L_X6Y75": { - "grid_x": 19, - "grid_y": 129, - "segment": "SEG_BRAM0_L_X6Y75", - "sites": { - "RAMB18_X0Y30": "FIFO18E1", - "RAMB18_X0Y31": "RAMB18E1", - "RAMB36_X0Y15": "RAMBFIFO36E1" - }, - "type": "BRAM_L" - }, - "BRAM_L_X6Y80": { - "grid_x": 19, - "grid_y": 124, - "segment": "SEG_BRAM0_L_X6Y80", - "sites": { - "RAMB18_X0Y32": "FIFO18E1", - "RAMB18_X0Y33": "RAMB18E1", - "RAMB36_X0Y16": "RAMBFIFO36E1" - }, - "type": "BRAM_L" - }, - "BRAM_L_X6Y85": { - "grid_x": 19, - "grid_y": 119, - "segment": "SEG_BRAM0_L_X6Y85", - "sites": { - "RAMB18_X0Y34": "FIFO18E1", - "RAMB18_X0Y35": "RAMB18E1", - "RAMB36_X0Y17": "RAMBFIFO36E1" - }, - "type": "BRAM_L" - }, - "BRAM_L_X6Y90": { - "grid_x": 19, - "grid_y": 114, - "segment": "SEG_BRAM0_L_X6Y90", - "sites": { - "RAMB18_X0Y36": "FIFO18E1", - "RAMB18_X0Y37": "RAMB18E1", - "RAMB36_X0Y18": "RAMBFIFO36E1" - }, - "type": "BRAM_L" - }, - "BRAM_L_X6Y95": { - "grid_x": 19, - "grid_y": 109, - "segment": "SEG_BRAM0_L_X6Y95", - "sites": { - "RAMB18_X0Y38": "FIFO18E1", - "RAMB18_X0Y39": "RAMB18E1", - "RAMB36_X0Y19": "RAMBFIFO36E1" - }, - "type": "BRAM_L" - }, - "BRKH_BRAM_X19Y104": { - "grid_x": 19, - "grid_y": 104, - "sites": {}, - "type": "BRKH_BRAM" - }, - "BRKH_BRAM_X19Y52": { - "grid_x": 19, - "grid_y": 156, - "sites": {}, - "type": "BRKH_BRAM" - }, - "BRKH_CLB_X10Y49": { - "grid_x": 30, - "grid_y": 156, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X10Y99": { - "grid_x": 30, - "grid_y": 104, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X11Y49": { - "grid_x": 33, - "grid_y": 156, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X11Y99": { - "grid_x": 33, - "grid_y": 104, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X12Y49": { - "grid_x": 34, - "grid_y": 156, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X12Y99": { - "grid_x": 34, - "grid_y": 104, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X13Y49": { - "grid_x": 37, - "grid_y": 156, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X13Y99": { - "grid_x": 37, - "grid_y": 104, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X2Y49": { - "grid_x": 10, - "grid_y": 156, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X2Y99": { - "grid_x": 10, - "grid_y": 104, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X3Y49": { - "grid_x": 13, - "grid_y": 156, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X3Y99": { - "grid_x": 13, - "grid_y": 104, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X4Y49": { - "grid_x": 14, - "grid_y": 156, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X4Y99": { - "grid_x": 14, - "grid_y": 104, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X5Y49": { - "grid_x": 17, - "grid_y": 156, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X5Y99": { - "grid_x": 17, - "grid_y": 104, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X7Y49": { - "grid_x": 23, - "grid_y": 156, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X7Y99": { - "grid_x": 23, - "grid_y": 104, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X8Y49": { - "grid_x": 24, - "grid_y": 156, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_CLB_X8Y99": { - "grid_x": 24, - "grid_y": 104, - "sites": {}, - "type": "BRKH_CLB" - }, - "BRKH_DSP_R_X28Y104": { - "grid_x": 28, - "grid_y": 104, - "sites": {}, - "type": "BRKH_DSP_R" - }, - "BRKH_DSP_R_X28Y52": { - "grid_x": 28, - "grid_y": 156, - "sites": {}, - "type": "BRKH_DSP_R" - }, - "BRKH_INT_X10Y49": { - "grid_x": 31, - "grid_y": 156, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X10Y99": { - "grid_x": 31, - "grid_y": 104, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X11Y49": { - "grid_x": 32, - "grid_y": 156, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X11Y99": { - "grid_x": 32, - "grid_y": 104, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X12Y49": { - "grid_x": 35, - "grid_y": 156, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X12Y99": { - "grid_x": 35, - "grid_y": 104, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X13Y49": { - "grid_x": 36, - "grid_y": 156, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X13Y99": { - "grid_x": 36, - "grid_y": 104, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X2Y49": { - "grid_x": 11, - "grid_y": 156, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X2Y99": { - "grid_x": 11, - "grid_y": 104, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X3Y49": { - "grid_x": 12, - "grid_y": 156, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X3Y99": { - "grid_x": 12, - "grid_y": 104, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X4Y49": { - "grid_x": 15, - "grid_y": 156, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X4Y99": { - "grid_x": 15, - "grid_y": 104, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X5Y49": { - "grid_x": 16, - "grid_y": 156, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X5Y99": { - "grid_x": 16, - "grid_y": 104, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X6Y49": { - "grid_x": 21, - "grid_y": 156, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X6Y99": { - "grid_x": 21, - "grid_y": 104, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X7Y49": { - "grid_x": 22, - "grid_y": 156, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X7Y99": { - "grid_x": 22, - "grid_y": 104, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X8Y49": { - "grid_x": 25, - "grid_y": 156, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X8Y99": { - "grid_x": 25, - "grid_y": 104, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X9Y49": { - "grid_x": 26, - "grid_y": 156, - "sites": {}, - "type": "BRKH_INT" - }, - "BRKH_INT_X9Y99": { - "grid_x": 26, - "grid_y": 104, - "sites": {}, - "type": "BRKH_INT" - }, - "CLBLL_L_X2Y50": { - "grid_x": 10, - "grid_y": 155, - "segment": "SEG_CLBLL_L_X2Y50", - "sites": { - "SLICE_X0Y50": "SLICEL", - "SLICE_X1Y50": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y51": { - "grid_x": 10, - "grid_y": 154, - "segment": "SEG_CLBLL_L_X2Y51", - "sites": { - "SLICE_X0Y51": "SLICEL", - "SLICE_X1Y51": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y52": { - "grid_x": 10, - "grid_y": 153, - "segment": "SEG_CLBLL_L_X2Y52", - "sites": { - "SLICE_X0Y52": "SLICEL", - "SLICE_X1Y52": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y53": { - "grid_x": 10, - "grid_y": 152, - "segment": "SEG_CLBLL_L_X2Y53", - "sites": { - "SLICE_X0Y53": "SLICEL", - "SLICE_X1Y53": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y54": { - "grid_x": 10, - "grid_y": 151, - "segment": "SEG_CLBLL_L_X2Y54", - "sites": { - "SLICE_X0Y54": "SLICEL", - "SLICE_X1Y54": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y55": { - "grid_x": 10, - "grid_y": 150, - "segment": "SEG_CLBLL_L_X2Y55", - "sites": { - "SLICE_X0Y55": "SLICEL", - "SLICE_X1Y55": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y56": { - "grid_x": 10, - "grid_y": 149, - "segment": "SEG_CLBLL_L_X2Y56", - "sites": { - "SLICE_X0Y56": "SLICEL", - "SLICE_X1Y56": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y57": { - "grid_x": 10, - "grid_y": 148, - "segment": "SEG_CLBLL_L_X2Y57", - "sites": { - "SLICE_X0Y57": "SLICEL", - "SLICE_X1Y57": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y58": { - "grid_x": 10, - "grid_y": 147, - "segment": "SEG_CLBLL_L_X2Y58", - "sites": { - "SLICE_X0Y58": "SLICEL", - "SLICE_X1Y58": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y59": { - "grid_x": 10, - "grid_y": 146, - "segment": "SEG_CLBLL_L_X2Y59", - "sites": { - "SLICE_X0Y59": "SLICEL", - "SLICE_X1Y59": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y60": { - "grid_x": 10, - "grid_y": 145, - "segment": "SEG_CLBLL_L_X2Y60", - "sites": { - "SLICE_X0Y60": "SLICEL", - "SLICE_X1Y60": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y61": { - "grid_x": 10, - "grid_y": 144, - "segment": "SEG_CLBLL_L_X2Y61", - "sites": { - "SLICE_X0Y61": "SLICEL", - "SLICE_X1Y61": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y62": { - "grid_x": 10, - "grid_y": 143, - "segment": "SEG_CLBLL_L_X2Y62", - "sites": { - "SLICE_X0Y62": "SLICEL", - "SLICE_X1Y62": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y63": { - "grid_x": 10, - "grid_y": 142, - "segment": "SEG_CLBLL_L_X2Y63", - "sites": { - "SLICE_X0Y63": "SLICEL", - "SLICE_X1Y63": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y64": { - "grid_x": 10, - "grid_y": 141, - "segment": "SEG_CLBLL_L_X2Y64", - "sites": { - "SLICE_X0Y64": "SLICEL", - "SLICE_X1Y64": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y65": { - "grid_x": 10, - "grid_y": 140, - "segment": "SEG_CLBLL_L_X2Y65", - "sites": { - "SLICE_X0Y65": "SLICEL", - "SLICE_X1Y65": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y66": { - "grid_x": 10, - "grid_y": 139, - "segment": "SEG_CLBLL_L_X2Y66", - "sites": { - "SLICE_X0Y66": "SLICEL", - "SLICE_X1Y66": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y67": { - "grid_x": 10, - "grid_y": 138, - "segment": "SEG_CLBLL_L_X2Y67", - "sites": { - "SLICE_X0Y67": "SLICEL", - "SLICE_X1Y67": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y68": { - "grid_x": 10, - "grid_y": 137, - "segment": "SEG_CLBLL_L_X2Y68", - "sites": { - "SLICE_X0Y68": "SLICEL", - "SLICE_X1Y68": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y69": { - "grid_x": 10, - "grid_y": 136, - "segment": "SEG_CLBLL_L_X2Y69", - "sites": { - "SLICE_X0Y69": "SLICEL", - "SLICE_X1Y69": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y70": { - "grid_x": 10, - "grid_y": 135, - "segment": "SEG_CLBLL_L_X2Y70", - "sites": { - "SLICE_X0Y70": "SLICEL", - "SLICE_X1Y70": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y71": { - "grid_x": 10, - "grid_y": 134, - "segment": "SEG_CLBLL_L_X2Y71", - "sites": { - "SLICE_X0Y71": "SLICEL", - "SLICE_X1Y71": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y72": { - "grid_x": 10, - "grid_y": 133, - "segment": "SEG_CLBLL_L_X2Y72", - "sites": { - "SLICE_X0Y72": "SLICEL", - "SLICE_X1Y72": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y73": { - "grid_x": 10, - "grid_y": 132, - "segment": "SEG_CLBLL_L_X2Y73", - "sites": { - "SLICE_X0Y73": "SLICEL", - "SLICE_X1Y73": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y74": { - "grid_x": 10, - "grid_y": 131, - "segment": "SEG_CLBLL_L_X2Y74", - "sites": { - "SLICE_X0Y74": "SLICEL", - "SLICE_X1Y74": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y75": { - "grid_x": 10, - "grid_y": 129, - "segment": "SEG_CLBLL_L_X2Y75", - "sites": { - "SLICE_X0Y75": "SLICEL", - "SLICE_X1Y75": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y76": { - "grid_x": 10, - "grid_y": 128, - "segment": "SEG_CLBLL_L_X2Y76", - "sites": { - "SLICE_X0Y76": "SLICEL", - "SLICE_X1Y76": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y77": { - "grid_x": 10, - "grid_y": 127, - "segment": "SEG_CLBLL_L_X2Y77", - "sites": { - "SLICE_X0Y77": "SLICEL", - "SLICE_X1Y77": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y78": { - "grid_x": 10, - "grid_y": 126, - "segment": "SEG_CLBLL_L_X2Y78", - "sites": { - "SLICE_X0Y78": "SLICEL", - "SLICE_X1Y78": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y79": { - "grid_x": 10, - "grid_y": 125, - "segment": "SEG_CLBLL_L_X2Y79", - "sites": { - "SLICE_X0Y79": "SLICEL", - "SLICE_X1Y79": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y80": { - "grid_x": 10, - "grid_y": 124, - "segment": "SEG_CLBLL_L_X2Y80", - "sites": { - "SLICE_X0Y80": "SLICEL", - "SLICE_X1Y80": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y81": { - "grid_x": 10, - "grid_y": 123, - "segment": "SEG_CLBLL_L_X2Y81", - "sites": { - "SLICE_X0Y81": "SLICEL", - "SLICE_X1Y81": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y82": { - "grid_x": 10, - "grid_y": 122, - "segment": "SEG_CLBLL_L_X2Y82", - "sites": { - "SLICE_X0Y82": "SLICEL", - "SLICE_X1Y82": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y83": { - "grid_x": 10, - "grid_y": 121, - "segment": "SEG_CLBLL_L_X2Y83", - "sites": { - "SLICE_X0Y83": "SLICEL", - "SLICE_X1Y83": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y84": { - "grid_x": 10, - "grid_y": 120, - "segment": "SEG_CLBLL_L_X2Y84", - "sites": { - "SLICE_X0Y84": "SLICEL", - "SLICE_X1Y84": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y85": { - "grid_x": 10, - "grid_y": 119, - "segment": "SEG_CLBLL_L_X2Y85", - "sites": { - "SLICE_X0Y85": "SLICEL", - "SLICE_X1Y85": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y86": { - "grid_x": 10, - "grid_y": 118, - "segment": "SEG_CLBLL_L_X2Y86", - "sites": { - "SLICE_X0Y86": "SLICEL", - "SLICE_X1Y86": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y87": { - "grid_x": 10, - "grid_y": 117, - "segment": "SEG_CLBLL_L_X2Y87", - "sites": { - "SLICE_X0Y87": "SLICEL", - "SLICE_X1Y87": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y88": { - "grid_x": 10, - "grid_y": 116, - "segment": "SEG_CLBLL_L_X2Y88", - "sites": { - "SLICE_X0Y88": "SLICEL", - "SLICE_X1Y88": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y89": { - "grid_x": 10, - "grid_y": 115, - "segment": "SEG_CLBLL_L_X2Y89", - "sites": { - "SLICE_X0Y89": "SLICEL", - "SLICE_X1Y89": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y90": { - "grid_x": 10, - "grid_y": 114, - "segment": "SEG_CLBLL_L_X2Y90", - "sites": { - "SLICE_X0Y90": "SLICEL", - "SLICE_X1Y90": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y91": { - "grid_x": 10, - "grid_y": 113, - "segment": "SEG_CLBLL_L_X2Y91", - "sites": { - "SLICE_X0Y91": "SLICEL", - "SLICE_X1Y91": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y92": { - "grid_x": 10, - "grid_y": 112, - "segment": "SEG_CLBLL_L_X2Y92", - "sites": { - "SLICE_X0Y92": "SLICEL", - "SLICE_X1Y92": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y93": { - "grid_x": 10, - "grid_y": 111, - "segment": "SEG_CLBLL_L_X2Y93", - "sites": { - "SLICE_X0Y93": "SLICEL", - "SLICE_X1Y93": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y94": { - "grid_x": 10, - "grid_y": 110, - "segment": "SEG_CLBLL_L_X2Y94", - "sites": { - "SLICE_X0Y94": "SLICEL", - "SLICE_X1Y94": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y95": { - "grid_x": 10, - "grid_y": 109, - "segment": "SEG_CLBLL_L_X2Y95", - "sites": { - "SLICE_X0Y95": "SLICEL", - "SLICE_X1Y95": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y96": { - "grid_x": 10, - "grid_y": 108, - "segment": "SEG_CLBLL_L_X2Y96", - "sites": { - "SLICE_X0Y96": "SLICEL", - "SLICE_X1Y96": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y97": { - "grid_x": 10, - "grid_y": 107, - "segment": "SEG_CLBLL_L_X2Y97", - "sites": { - "SLICE_X0Y97": "SLICEL", - "SLICE_X1Y97": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y98": { - "grid_x": 10, - "grid_y": 106, - "segment": "SEG_CLBLL_L_X2Y98", - "sites": { - "SLICE_X0Y98": "SLICEL", - "SLICE_X1Y98": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X2Y99": { - "grid_x": 10, - "grid_y": 105, - "segment": "SEG_CLBLL_L_X2Y99", - "sites": { - "SLICE_X0Y99": "SLICEL", - "SLICE_X1Y99": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y50": { - "grid_x": 14, - "grid_y": 155, - "segment": "SEG_CLBLL_L_X4Y50", - "sites": { - "SLICE_X4Y50": "SLICEL", - "SLICE_X5Y50": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y51": { - "grid_x": 14, - "grid_y": 154, - "segment": "SEG_CLBLL_L_X4Y51", - "sites": { - "SLICE_X4Y51": "SLICEL", - "SLICE_X5Y51": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y52": { - "grid_x": 14, - "grid_y": 153, - "segment": "SEG_CLBLL_L_X4Y52", - "sites": { - "SLICE_X4Y52": "SLICEL", - "SLICE_X5Y52": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y53": { - "grid_x": 14, - "grid_y": 152, - "segment": "SEG_CLBLL_L_X4Y53", - "sites": { - "SLICE_X4Y53": "SLICEL", - "SLICE_X5Y53": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y54": { - "grid_x": 14, - "grid_y": 151, - "segment": "SEG_CLBLL_L_X4Y54", - "sites": { - "SLICE_X4Y54": "SLICEL", - "SLICE_X5Y54": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y55": { - "grid_x": 14, - "grid_y": 150, - "segment": "SEG_CLBLL_L_X4Y55", - "sites": { - "SLICE_X4Y55": "SLICEL", - "SLICE_X5Y55": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y56": { - "grid_x": 14, - "grid_y": 149, - "segment": "SEG_CLBLL_L_X4Y56", - "sites": { - "SLICE_X4Y56": "SLICEL", - "SLICE_X5Y56": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y57": { - "grid_x": 14, - "grid_y": 148, - "segment": "SEG_CLBLL_L_X4Y57", - "sites": { - "SLICE_X4Y57": "SLICEL", - "SLICE_X5Y57": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y58": { - "grid_x": 14, - "grid_y": 147, - "segment": "SEG_CLBLL_L_X4Y58", - "sites": { - "SLICE_X4Y58": "SLICEL", - "SLICE_X5Y58": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y59": { - "grid_x": 14, - "grid_y": 146, - "segment": "SEG_CLBLL_L_X4Y59", - "sites": { - "SLICE_X4Y59": "SLICEL", - "SLICE_X5Y59": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y60": { - "grid_x": 14, - "grid_y": 145, - "segment": "SEG_CLBLL_L_X4Y60", - "sites": { - "SLICE_X4Y60": "SLICEL", - "SLICE_X5Y60": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y61": { - "grid_x": 14, - "grid_y": 144, - "segment": "SEG_CLBLL_L_X4Y61", - "sites": { - "SLICE_X4Y61": "SLICEL", - "SLICE_X5Y61": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y62": { - "grid_x": 14, - "grid_y": 143, - "segment": "SEG_CLBLL_L_X4Y62", - "sites": { - "SLICE_X4Y62": "SLICEL", - "SLICE_X5Y62": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y63": { - "grid_x": 14, - "grid_y": 142, - "segment": "SEG_CLBLL_L_X4Y63", - "sites": { - "SLICE_X4Y63": "SLICEL", - "SLICE_X5Y63": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y64": { - "grid_x": 14, - "grid_y": 141, - "segment": "SEG_CLBLL_L_X4Y64", - "sites": { - "SLICE_X4Y64": "SLICEL", - "SLICE_X5Y64": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y65": { - "grid_x": 14, - "grid_y": 140, - "segment": "SEG_CLBLL_L_X4Y65", - "sites": { - "SLICE_X4Y65": "SLICEL", - "SLICE_X5Y65": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y66": { - "grid_x": 14, - "grid_y": 139, - "segment": "SEG_CLBLL_L_X4Y66", - "sites": { - "SLICE_X4Y66": "SLICEL", - "SLICE_X5Y66": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y67": { - "grid_x": 14, - "grid_y": 138, - "segment": "SEG_CLBLL_L_X4Y67", - "sites": { - "SLICE_X4Y67": "SLICEL", - "SLICE_X5Y67": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y68": { - "grid_x": 14, - "grid_y": 137, - "segment": "SEG_CLBLL_L_X4Y68", - "sites": { - "SLICE_X4Y68": "SLICEL", - "SLICE_X5Y68": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y69": { - "grid_x": 14, - "grid_y": 136, - "segment": "SEG_CLBLL_L_X4Y69", - "sites": { - "SLICE_X4Y69": "SLICEL", - "SLICE_X5Y69": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y70": { - "grid_x": 14, - "grid_y": 135, - "segment": "SEG_CLBLL_L_X4Y70", - "sites": { - "SLICE_X4Y70": "SLICEL", - "SLICE_X5Y70": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y71": { - "grid_x": 14, - "grid_y": 134, - "segment": "SEG_CLBLL_L_X4Y71", - "sites": { - "SLICE_X4Y71": "SLICEL", - "SLICE_X5Y71": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y72": { - "grid_x": 14, - "grid_y": 133, - "segment": "SEG_CLBLL_L_X4Y72", - "sites": { - "SLICE_X4Y72": "SLICEL", - "SLICE_X5Y72": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y73": { - "grid_x": 14, - "grid_y": 132, - "segment": "SEG_CLBLL_L_X4Y73", - "sites": { - "SLICE_X4Y73": "SLICEL", - "SLICE_X5Y73": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y74": { - "grid_x": 14, - "grid_y": 131, - "segment": "SEG_CLBLL_L_X4Y74", - "sites": { - "SLICE_X4Y74": "SLICEL", - "SLICE_X5Y74": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y75": { - "grid_x": 14, - "grid_y": 129, - "segment": "SEG_CLBLL_L_X4Y75", - "sites": { - "SLICE_X4Y75": "SLICEL", - "SLICE_X5Y75": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y76": { - "grid_x": 14, - "grid_y": 128, - "segment": "SEG_CLBLL_L_X4Y76", - "sites": { - "SLICE_X4Y76": "SLICEL", - "SLICE_X5Y76": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y77": { - "grid_x": 14, - "grid_y": 127, - "segment": "SEG_CLBLL_L_X4Y77", - "sites": { - "SLICE_X4Y77": "SLICEL", - "SLICE_X5Y77": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y78": { - "grid_x": 14, - "grid_y": 126, - "segment": "SEG_CLBLL_L_X4Y78", - "sites": { - "SLICE_X4Y78": "SLICEL", - "SLICE_X5Y78": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y79": { - "grid_x": 14, - "grid_y": 125, - "segment": "SEG_CLBLL_L_X4Y79", - "sites": { - "SLICE_X4Y79": "SLICEL", - "SLICE_X5Y79": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y80": { - "grid_x": 14, - "grid_y": 124, - "segment": "SEG_CLBLL_L_X4Y80", - "sites": { - "SLICE_X4Y80": "SLICEL", - "SLICE_X5Y80": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y81": { - "grid_x": 14, - "grid_y": 123, - "segment": "SEG_CLBLL_L_X4Y81", - "sites": { - "SLICE_X4Y81": "SLICEL", - "SLICE_X5Y81": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y82": { - "grid_x": 14, - "grid_y": 122, - "segment": "SEG_CLBLL_L_X4Y82", - "sites": { - "SLICE_X4Y82": "SLICEL", - "SLICE_X5Y82": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y83": { - "grid_x": 14, - "grid_y": 121, - "segment": "SEG_CLBLL_L_X4Y83", - "sites": { - "SLICE_X4Y83": "SLICEL", - "SLICE_X5Y83": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y84": { - "grid_x": 14, - "grid_y": 120, - "segment": "SEG_CLBLL_L_X4Y84", - "sites": { - "SLICE_X4Y84": "SLICEL", - "SLICE_X5Y84": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y85": { - "grid_x": 14, - "grid_y": 119, - "segment": "SEG_CLBLL_L_X4Y85", - "sites": { - "SLICE_X4Y85": "SLICEL", - "SLICE_X5Y85": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y86": { - "grid_x": 14, - "grid_y": 118, - "segment": "SEG_CLBLL_L_X4Y86", - "sites": { - "SLICE_X4Y86": "SLICEL", - "SLICE_X5Y86": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y87": { - "grid_x": 14, - "grid_y": 117, - "segment": "SEG_CLBLL_L_X4Y87", - "sites": { - "SLICE_X4Y87": "SLICEL", - "SLICE_X5Y87": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y88": { - "grid_x": 14, - "grid_y": 116, - "segment": "SEG_CLBLL_L_X4Y88", - "sites": { - "SLICE_X4Y88": "SLICEL", - "SLICE_X5Y88": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y89": { - "grid_x": 14, - "grid_y": 115, - "segment": "SEG_CLBLL_L_X4Y89", - "sites": { - "SLICE_X4Y89": "SLICEL", - "SLICE_X5Y89": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y90": { - "grid_x": 14, - "grid_y": 114, - "segment": "SEG_CLBLL_L_X4Y90", - "sites": { - "SLICE_X4Y90": "SLICEL", - "SLICE_X5Y90": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y91": { - "grid_x": 14, - "grid_y": 113, - "segment": "SEG_CLBLL_L_X4Y91", - "sites": { - "SLICE_X4Y91": "SLICEL", - "SLICE_X5Y91": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y92": { - "grid_x": 14, - "grid_y": 112, - "segment": "SEG_CLBLL_L_X4Y92", - "sites": { - "SLICE_X4Y92": "SLICEL", - "SLICE_X5Y92": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y93": { - "grid_x": 14, - "grid_y": 111, - "segment": "SEG_CLBLL_L_X4Y93", - "sites": { - "SLICE_X4Y93": "SLICEL", - "SLICE_X5Y93": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y94": { - "grid_x": 14, - "grid_y": 110, - "segment": "SEG_CLBLL_L_X4Y94", - "sites": { - "SLICE_X4Y94": "SLICEL", - "SLICE_X5Y94": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y95": { - "grid_x": 14, - "grid_y": 109, - "segment": "SEG_CLBLL_L_X4Y95", - "sites": { - "SLICE_X4Y95": "SLICEL", - "SLICE_X5Y95": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y96": { - "grid_x": 14, - "grid_y": 108, - "segment": "SEG_CLBLL_L_X4Y96", - "sites": { - "SLICE_X4Y96": "SLICEL", - "SLICE_X5Y96": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y97": { - "grid_x": 14, - "grid_y": 107, - "segment": "SEG_CLBLL_L_X4Y97", - "sites": { - "SLICE_X4Y97": "SLICEL", - "SLICE_X5Y97": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y98": { - "grid_x": 14, - "grid_y": 106, - "segment": "SEG_CLBLL_L_X4Y98", - "sites": { - "SLICE_X4Y98": "SLICEL", - "SLICE_X5Y98": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLL_L_X4Y99": { - "grid_x": 14, - "grid_y": 105, - "segment": "SEG_CLBLL_L_X4Y99", - "sites": { - "SLICE_X4Y99": "SLICEL", - "SLICE_X5Y99": "SLICEL" - }, - "type": "CLBLL_L" - }, - "CLBLM_L_X10Y50": { - "grid_x": 30, - "grid_y": 155, - "segment": "SEG_CLBLM_L_X10Y50", - "sites": { - "SLICE_X12Y50": "SLICEM", - "SLICE_X13Y50": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y51": { - "grid_x": 30, - "grid_y": 154, - "segment": "SEG_CLBLM_L_X10Y51", - "sites": { - "SLICE_X12Y51": "SLICEM", - "SLICE_X13Y51": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y52": { - "grid_x": 30, - "grid_y": 153, - "segment": "SEG_CLBLM_L_X10Y52", - "sites": { - "SLICE_X12Y52": "SLICEM", - "SLICE_X13Y52": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y53": { - "grid_x": 30, - "grid_y": 152, - "segment": "SEG_CLBLM_L_X10Y53", - "sites": { - "SLICE_X12Y53": "SLICEM", - "SLICE_X13Y53": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y54": { - "grid_x": 30, - "grid_y": 151, - "segment": "SEG_CLBLM_L_X10Y54", - "sites": { - "SLICE_X12Y54": "SLICEM", - "SLICE_X13Y54": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y55": { - "grid_x": 30, - "grid_y": 150, - "segment": "SEG_CLBLM_L_X10Y55", - "sites": { - "SLICE_X12Y55": "SLICEM", - "SLICE_X13Y55": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y56": { - "grid_x": 30, - "grid_y": 149, - "segment": "SEG_CLBLM_L_X10Y56", - "sites": { - "SLICE_X12Y56": "SLICEM", - "SLICE_X13Y56": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y57": { - "grid_x": 30, - "grid_y": 148, - "segment": "SEG_CLBLM_L_X10Y57", - "sites": { - "SLICE_X12Y57": "SLICEM", - "SLICE_X13Y57": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y58": { - "grid_x": 30, - "grid_y": 147, - "segment": "SEG_CLBLM_L_X10Y58", - "sites": { - "SLICE_X12Y58": "SLICEM", - "SLICE_X13Y58": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y59": { - "grid_x": 30, - "grid_y": 146, - "segment": "SEG_CLBLM_L_X10Y59", - "sites": { - "SLICE_X12Y59": "SLICEM", - "SLICE_X13Y59": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y60": { - "grid_x": 30, - "grid_y": 145, - "segment": "SEG_CLBLM_L_X10Y60", - "sites": { - "SLICE_X12Y60": "SLICEM", - "SLICE_X13Y60": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y61": { - "grid_x": 30, - "grid_y": 144, - "segment": "SEG_CLBLM_L_X10Y61", - "sites": { - "SLICE_X12Y61": "SLICEM", - "SLICE_X13Y61": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y62": { - "grid_x": 30, - "grid_y": 143, - "segment": "SEG_CLBLM_L_X10Y62", - "sites": { - "SLICE_X12Y62": "SLICEM", - "SLICE_X13Y62": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y63": { - "grid_x": 30, - "grid_y": 142, - "segment": "SEG_CLBLM_L_X10Y63", - "sites": { - "SLICE_X12Y63": "SLICEM", - "SLICE_X13Y63": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y64": { - "grid_x": 30, - "grid_y": 141, - "segment": "SEG_CLBLM_L_X10Y64", - "sites": { - "SLICE_X12Y64": "SLICEM", - "SLICE_X13Y64": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y65": { - "grid_x": 30, - "grid_y": 140, - "segment": "SEG_CLBLM_L_X10Y65", - "sites": { - "SLICE_X12Y65": "SLICEM", - "SLICE_X13Y65": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y66": { - "grid_x": 30, - "grid_y": 139, - "segment": "SEG_CLBLM_L_X10Y66", - "sites": { - "SLICE_X12Y66": "SLICEM", - "SLICE_X13Y66": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y67": { - "grid_x": 30, - "grid_y": 138, - "segment": "SEG_CLBLM_L_X10Y67", - "sites": { - "SLICE_X12Y67": "SLICEM", - "SLICE_X13Y67": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y68": { - "grid_x": 30, - "grid_y": 137, - "segment": "SEG_CLBLM_L_X10Y68", - "sites": { - "SLICE_X12Y68": "SLICEM", - "SLICE_X13Y68": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y69": { - "grid_x": 30, - "grid_y": 136, - "segment": "SEG_CLBLM_L_X10Y69", - "sites": { - "SLICE_X12Y69": "SLICEM", - "SLICE_X13Y69": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y70": { - "grid_x": 30, - "grid_y": 135, - "segment": "SEG_CLBLM_L_X10Y70", - "sites": { - "SLICE_X12Y70": "SLICEM", - "SLICE_X13Y70": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y71": { - "grid_x": 30, - "grid_y": 134, - "segment": "SEG_CLBLM_L_X10Y71", - "sites": { - "SLICE_X12Y71": "SLICEM", - "SLICE_X13Y71": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y72": { - "grid_x": 30, - "grid_y": 133, - "segment": "SEG_CLBLM_L_X10Y72", - "sites": { - "SLICE_X12Y72": "SLICEM", - "SLICE_X13Y72": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y73": { - "grid_x": 30, - "grid_y": 132, - "segment": "SEG_CLBLM_L_X10Y73", - "sites": { - "SLICE_X12Y73": "SLICEM", - "SLICE_X13Y73": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y74": { - "grid_x": 30, - "grid_y": 131, - "segment": "SEG_CLBLM_L_X10Y74", - "sites": { - "SLICE_X12Y74": "SLICEM", - "SLICE_X13Y74": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y75": { - "grid_x": 30, - "grid_y": 129, - "segment": "SEG_CLBLM_L_X10Y75", - "sites": { - "SLICE_X12Y75": "SLICEM", - "SLICE_X13Y75": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y76": { - "grid_x": 30, - "grid_y": 128, - "segment": "SEG_CLBLM_L_X10Y76", - "sites": { - "SLICE_X12Y76": "SLICEM", - "SLICE_X13Y76": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y77": { - "grid_x": 30, - "grid_y": 127, - "segment": "SEG_CLBLM_L_X10Y77", - "sites": { - "SLICE_X12Y77": "SLICEM", - "SLICE_X13Y77": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y78": { - "grid_x": 30, - "grid_y": 126, - "segment": "SEG_CLBLM_L_X10Y78", - "sites": { - "SLICE_X12Y78": "SLICEM", - "SLICE_X13Y78": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y79": { - "grid_x": 30, - "grid_y": 125, - "segment": "SEG_CLBLM_L_X10Y79", - "sites": { - "SLICE_X12Y79": "SLICEM", - "SLICE_X13Y79": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y80": { - "grid_x": 30, - "grid_y": 124, - "segment": "SEG_CLBLM_L_X10Y80", - "sites": { - "SLICE_X12Y80": "SLICEM", - "SLICE_X13Y80": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y81": { - "grid_x": 30, - "grid_y": 123, - "segment": "SEG_CLBLM_L_X10Y81", - "sites": { - "SLICE_X12Y81": "SLICEM", - "SLICE_X13Y81": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y82": { - "grid_x": 30, - "grid_y": 122, - "segment": "SEG_CLBLM_L_X10Y82", - "sites": { - "SLICE_X12Y82": "SLICEM", - "SLICE_X13Y82": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y83": { - "grid_x": 30, - "grid_y": 121, - "segment": "SEG_CLBLM_L_X10Y83", - "sites": { - "SLICE_X12Y83": "SLICEM", - "SLICE_X13Y83": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y84": { - "grid_x": 30, - "grid_y": 120, - "segment": "SEG_CLBLM_L_X10Y84", - "sites": { - "SLICE_X12Y84": "SLICEM", - "SLICE_X13Y84": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y85": { - "grid_x": 30, - "grid_y": 119, - "segment": "SEG_CLBLM_L_X10Y85", - "sites": { - "SLICE_X12Y85": "SLICEM", - "SLICE_X13Y85": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y86": { - "grid_x": 30, - "grid_y": 118, - "segment": "SEG_CLBLM_L_X10Y86", - "sites": { - "SLICE_X12Y86": "SLICEM", - "SLICE_X13Y86": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y87": { - "grid_x": 30, - "grid_y": 117, - "segment": "SEG_CLBLM_L_X10Y87", - "sites": { - "SLICE_X12Y87": "SLICEM", - "SLICE_X13Y87": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y88": { - "grid_x": 30, - "grid_y": 116, - "segment": "SEG_CLBLM_L_X10Y88", - "sites": { - "SLICE_X12Y88": "SLICEM", - "SLICE_X13Y88": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y89": { - "grid_x": 30, - "grid_y": 115, - "segment": "SEG_CLBLM_L_X10Y89", - "sites": { - "SLICE_X12Y89": "SLICEM", - "SLICE_X13Y89": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y90": { - "grid_x": 30, - "grid_y": 114, - "segment": "SEG_CLBLM_L_X10Y90", - "sites": { - "SLICE_X12Y90": "SLICEM", - "SLICE_X13Y90": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y91": { - "grid_x": 30, - "grid_y": 113, - "segment": "SEG_CLBLM_L_X10Y91", - "sites": { - "SLICE_X12Y91": "SLICEM", - "SLICE_X13Y91": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y92": { - "grid_x": 30, - "grid_y": 112, - "segment": "SEG_CLBLM_L_X10Y92", - "sites": { - "SLICE_X12Y92": "SLICEM", - "SLICE_X13Y92": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y93": { - "grid_x": 30, - "grid_y": 111, - "segment": "SEG_CLBLM_L_X10Y93", - "sites": { - "SLICE_X12Y93": "SLICEM", - "SLICE_X13Y93": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y94": { - "grid_x": 30, - "grid_y": 110, - "segment": "SEG_CLBLM_L_X10Y94", - "sites": { - "SLICE_X12Y94": "SLICEM", - "SLICE_X13Y94": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y95": { - "grid_x": 30, - "grid_y": 109, - "segment": "SEG_CLBLM_L_X10Y95", - "sites": { - "SLICE_X12Y95": "SLICEM", - "SLICE_X13Y95": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y96": { - "grid_x": 30, - "grid_y": 108, - "segment": "SEG_CLBLM_L_X10Y96", - "sites": { - "SLICE_X12Y96": "SLICEM", - "SLICE_X13Y96": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y97": { - "grid_x": 30, - "grid_y": 107, - "segment": "SEG_CLBLM_L_X10Y97", - "sites": { - "SLICE_X12Y97": "SLICEM", - "SLICE_X13Y97": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y98": { - "grid_x": 30, - "grid_y": 106, - "segment": "SEG_CLBLM_L_X10Y98", - "sites": { - "SLICE_X12Y98": "SLICEM", - "SLICE_X13Y98": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X10Y99": { - "grid_x": 30, - "grid_y": 105, - "segment": "SEG_CLBLM_L_X10Y99", - "sites": { - "SLICE_X12Y99": "SLICEM", - "SLICE_X13Y99": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y50": { - "grid_x": 34, - "grid_y": 155, - "segment": "SEG_CLBLM_L_X12Y50", - "sites": { - "SLICE_X16Y50": "SLICEM", - "SLICE_X17Y50": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y51": { - "grid_x": 34, - "grid_y": 154, - "segment": "SEG_CLBLM_L_X12Y51", - "sites": { - "SLICE_X16Y51": "SLICEM", - "SLICE_X17Y51": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y52": { - "grid_x": 34, - "grid_y": 153, - "segment": "SEG_CLBLM_L_X12Y52", - "sites": { - "SLICE_X16Y52": "SLICEM", - "SLICE_X17Y52": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y53": { - "grid_x": 34, - "grid_y": 152, - "segment": "SEG_CLBLM_L_X12Y53", - "sites": { - "SLICE_X16Y53": "SLICEM", - "SLICE_X17Y53": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y54": { - "grid_x": 34, - "grid_y": 151, - "segment": "SEG_CLBLM_L_X12Y54", - "sites": { - "SLICE_X16Y54": "SLICEM", - "SLICE_X17Y54": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y55": { - "grid_x": 34, - "grid_y": 150, - "segment": "SEG_CLBLM_L_X12Y55", - "sites": { - "SLICE_X16Y55": "SLICEM", - "SLICE_X17Y55": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y56": { - "grid_x": 34, - "grid_y": 149, - "segment": "SEG_CLBLM_L_X12Y56", - "sites": { - "SLICE_X16Y56": "SLICEM", - "SLICE_X17Y56": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y57": { - "grid_x": 34, - "grid_y": 148, - "segment": "SEG_CLBLM_L_X12Y57", - "sites": { - "SLICE_X16Y57": "SLICEM", - "SLICE_X17Y57": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y58": { - "grid_x": 34, - "grid_y": 147, - "segment": "SEG_CLBLM_L_X12Y58", - "sites": { - "SLICE_X16Y58": "SLICEM", - "SLICE_X17Y58": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y59": { - "grid_x": 34, - "grid_y": 146, - "segment": "SEG_CLBLM_L_X12Y59", - "sites": { - "SLICE_X16Y59": "SLICEM", - "SLICE_X17Y59": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y60": { - "grid_x": 34, - "grid_y": 145, - "segment": "SEG_CLBLM_L_X12Y60", - "sites": { - "SLICE_X16Y60": "SLICEM", - "SLICE_X17Y60": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y61": { - "grid_x": 34, - "grid_y": 144, - "segment": "SEG_CLBLM_L_X12Y61", - "sites": { - "SLICE_X16Y61": "SLICEM", - "SLICE_X17Y61": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y62": { - "grid_x": 34, - "grid_y": 143, - "segment": "SEG_CLBLM_L_X12Y62", - "sites": { - "SLICE_X16Y62": "SLICEM", - "SLICE_X17Y62": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y63": { - "grid_x": 34, - "grid_y": 142, - "segment": "SEG_CLBLM_L_X12Y63", - "sites": { - "SLICE_X16Y63": "SLICEM", - "SLICE_X17Y63": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y64": { - "grid_x": 34, - "grid_y": 141, - "segment": "SEG_CLBLM_L_X12Y64", - "sites": { - "SLICE_X16Y64": "SLICEM", - "SLICE_X17Y64": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y65": { - "grid_x": 34, - "grid_y": 140, - "segment": "SEG_CLBLM_L_X12Y65", - "sites": { - "SLICE_X16Y65": "SLICEM", - "SLICE_X17Y65": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y66": { - "grid_x": 34, - "grid_y": 139, - "segment": "SEG_CLBLM_L_X12Y66", - "sites": { - "SLICE_X16Y66": "SLICEM", - "SLICE_X17Y66": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y67": { - "grid_x": 34, - "grid_y": 138, - "segment": "SEG_CLBLM_L_X12Y67", - "sites": { - "SLICE_X16Y67": "SLICEM", - "SLICE_X17Y67": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y68": { - "grid_x": 34, - "grid_y": 137, - "segment": "SEG_CLBLM_L_X12Y68", - "sites": { - "SLICE_X16Y68": "SLICEM", - "SLICE_X17Y68": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y69": { - "grid_x": 34, - "grid_y": 136, - "segment": "SEG_CLBLM_L_X12Y69", - "sites": { - "SLICE_X16Y69": "SLICEM", - "SLICE_X17Y69": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y70": { - "grid_x": 34, - "grid_y": 135, - "segment": "SEG_CLBLM_L_X12Y70", - "sites": { - "SLICE_X16Y70": "SLICEM", - "SLICE_X17Y70": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y71": { - "grid_x": 34, - "grid_y": 134, - "segment": "SEG_CLBLM_L_X12Y71", - "sites": { - "SLICE_X16Y71": "SLICEM", - "SLICE_X17Y71": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y72": { - "grid_x": 34, - "grid_y": 133, - "segment": "SEG_CLBLM_L_X12Y72", - "sites": { - "SLICE_X16Y72": "SLICEM", - "SLICE_X17Y72": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y73": { - "grid_x": 34, - "grid_y": 132, - "segment": "SEG_CLBLM_L_X12Y73", - "sites": { - "SLICE_X16Y73": "SLICEM", - "SLICE_X17Y73": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y74": { - "grid_x": 34, - "grid_y": 131, - "segment": "SEG_CLBLM_L_X12Y74", - "sites": { - "SLICE_X16Y74": "SLICEM", - "SLICE_X17Y74": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y75": { - "grid_x": 34, - "grid_y": 129, - "segment": "SEG_CLBLM_L_X12Y75", - "sites": { - "SLICE_X16Y75": "SLICEM", - "SLICE_X17Y75": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y76": { - "grid_x": 34, - "grid_y": 128, - "segment": "SEG_CLBLM_L_X12Y76", - "sites": { - "SLICE_X16Y76": "SLICEM", - "SLICE_X17Y76": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y77": { - "grid_x": 34, - "grid_y": 127, - "segment": "SEG_CLBLM_L_X12Y77", - "sites": { - "SLICE_X16Y77": "SLICEM", - "SLICE_X17Y77": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y78": { - "grid_x": 34, - "grid_y": 126, - "segment": "SEG_CLBLM_L_X12Y78", - "sites": { - "SLICE_X16Y78": "SLICEM", - "SLICE_X17Y78": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y79": { - "grid_x": 34, - "grid_y": 125, - "segment": "SEG_CLBLM_L_X12Y79", - "sites": { - "SLICE_X16Y79": "SLICEM", - "SLICE_X17Y79": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y80": { - "grid_x": 34, - "grid_y": 124, - "segment": "SEG_CLBLM_L_X12Y80", - "sites": { - "SLICE_X16Y80": "SLICEM", - "SLICE_X17Y80": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y81": { - "grid_x": 34, - "grid_y": 123, - "segment": "SEG_CLBLM_L_X12Y81", - "sites": { - "SLICE_X16Y81": "SLICEM", - "SLICE_X17Y81": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y82": { - "grid_x": 34, - "grid_y": 122, - "segment": "SEG_CLBLM_L_X12Y82", - "sites": { - "SLICE_X16Y82": "SLICEM", - "SLICE_X17Y82": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y83": { - "grid_x": 34, - "grid_y": 121, - "segment": "SEG_CLBLM_L_X12Y83", - "sites": { - "SLICE_X16Y83": "SLICEM", - "SLICE_X17Y83": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y84": { - "grid_x": 34, - "grid_y": 120, - "segment": "SEG_CLBLM_L_X12Y84", - "sites": { - "SLICE_X16Y84": "SLICEM", - "SLICE_X17Y84": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y85": { - "grid_x": 34, - "grid_y": 119, - "segment": "SEG_CLBLM_L_X12Y85", - "sites": { - "SLICE_X16Y85": "SLICEM", - "SLICE_X17Y85": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y86": { - "grid_x": 34, - "grid_y": 118, - "segment": "SEG_CLBLM_L_X12Y86", - "sites": { - "SLICE_X16Y86": "SLICEM", - "SLICE_X17Y86": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y87": { - "grid_x": 34, - "grid_y": 117, - "segment": "SEG_CLBLM_L_X12Y87", - "sites": { - "SLICE_X16Y87": "SLICEM", - "SLICE_X17Y87": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y88": { - "grid_x": 34, - "grid_y": 116, - "segment": "SEG_CLBLM_L_X12Y88", - "sites": { - "SLICE_X16Y88": "SLICEM", - "SLICE_X17Y88": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y89": { - "grid_x": 34, - "grid_y": 115, - "segment": "SEG_CLBLM_L_X12Y89", - "sites": { - "SLICE_X16Y89": "SLICEM", - "SLICE_X17Y89": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y90": { - "grid_x": 34, - "grid_y": 114, - "segment": "SEG_CLBLM_L_X12Y90", - "sites": { - "SLICE_X16Y90": "SLICEM", - "SLICE_X17Y90": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y91": { - "grid_x": 34, - "grid_y": 113, - "segment": "SEG_CLBLM_L_X12Y91", - "sites": { - "SLICE_X16Y91": "SLICEM", - "SLICE_X17Y91": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y92": { - "grid_x": 34, - "grid_y": 112, - "segment": "SEG_CLBLM_L_X12Y92", - "sites": { - "SLICE_X16Y92": "SLICEM", - "SLICE_X17Y92": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y93": { - "grid_x": 34, - "grid_y": 111, - "segment": "SEG_CLBLM_L_X12Y93", - "sites": { - "SLICE_X16Y93": "SLICEM", - "SLICE_X17Y93": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y94": { - "grid_x": 34, - "grid_y": 110, - "segment": "SEG_CLBLM_L_X12Y94", - "sites": { - "SLICE_X16Y94": "SLICEM", - "SLICE_X17Y94": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y95": { - "grid_x": 34, - "grid_y": 109, - "segment": "SEG_CLBLM_L_X12Y95", - "sites": { - "SLICE_X16Y95": "SLICEM", - "SLICE_X17Y95": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y96": { - "grid_x": 34, - "grid_y": 108, - "segment": "SEG_CLBLM_L_X12Y96", - "sites": { - "SLICE_X16Y96": "SLICEM", - "SLICE_X17Y96": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y97": { - "grid_x": 34, - "grid_y": 107, - "segment": "SEG_CLBLM_L_X12Y97", - "sites": { - "SLICE_X16Y97": "SLICEM", - "SLICE_X17Y97": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y98": { - "grid_x": 34, - "grid_y": 106, - "segment": "SEG_CLBLM_L_X12Y98", - "sites": { - "SLICE_X16Y98": "SLICEM", - "SLICE_X17Y98": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X12Y99": { - "grid_x": 34, - "grid_y": 105, - "segment": "SEG_CLBLM_L_X12Y99", - "sites": { - "SLICE_X16Y99": "SLICEM", - "SLICE_X17Y99": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y50": { - "grid_x": 24, - "grid_y": 155, - "segment": "SEG_CLBLM_L_X8Y50", - "sites": { - "SLICE_X10Y50": "SLICEM", - "SLICE_X11Y50": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y51": { - "grid_x": 24, - "grid_y": 154, - "segment": "SEG_CLBLM_L_X8Y51", - "sites": { - "SLICE_X10Y51": "SLICEM", - "SLICE_X11Y51": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y52": { - "grid_x": 24, - "grid_y": 153, - "segment": "SEG_CLBLM_L_X8Y52", - "sites": { - "SLICE_X10Y52": "SLICEM", - "SLICE_X11Y52": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y53": { - "grid_x": 24, - "grid_y": 152, - "segment": "SEG_CLBLM_L_X8Y53", - "sites": { - "SLICE_X10Y53": "SLICEM", - "SLICE_X11Y53": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y54": { - "grid_x": 24, - "grid_y": 151, - "segment": "SEG_CLBLM_L_X8Y54", - "sites": { - "SLICE_X10Y54": "SLICEM", - "SLICE_X11Y54": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y55": { - "grid_x": 24, - "grid_y": 150, - "segment": "SEG_CLBLM_L_X8Y55", - "sites": { - "SLICE_X10Y55": "SLICEM", - "SLICE_X11Y55": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y56": { - "grid_x": 24, - "grid_y": 149, - "segment": "SEG_CLBLM_L_X8Y56", - "sites": { - "SLICE_X10Y56": "SLICEM", - "SLICE_X11Y56": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y57": { - "grid_x": 24, - "grid_y": 148, - "segment": "SEG_CLBLM_L_X8Y57", - "sites": { - "SLICE_X10Y57": "SLICEM", - "SLICE_X11Y57": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y58": { - "grid_x": 24, - "grid_y": 147, - "segment": "SEG_CLBLM_L_X8Y58", - "sites": { - "SLICE_X10Y58": "SLICEM", - "SLICE_X11Y58": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y59": { - "grid_x": 24, - "grid_y": 146, - "segment": "SEG_CLBLM_L_X8Y59", - "sites": { - "SLICE_X10Y59": "SLICEM", - "SLICE_X11Y59": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y60": { - "grid_x": 24, - "grid_y": 145, - "segment": "SEG_CLBLM_L_X8Y60", - "sites": { - "SLICE_X10Y60": "SLICEM", - "SLICE_X11Y60": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y61": { - "grid_x": 24, - "grid_y": 144, - "segment": "SEG_CLBLM_L_X8Y61", - "sites": { - "SLICE_X10Y61": "SLICEM", - "SLICE_X11Y61": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y62": { - "grid_x": 24, - "grid_y": 143, - "segment": "SEG_CLBLM_L_X8Y62", - "sites": { - "SLICE_X10Y62": "SLICEM", - "SLICE_X11Y62": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y63": { - "grid_x": 24, - "grid_y": 142, - "segment": "SEG_CLBLM_L_X8Y63", - "sites": { - "SLICE_X10Y63": "SLICEM", - "SLICE_X11Y63": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y64": { - "grid_x": 24, - "grid_y": 141, - "segment": "SEG_CLBLM_L_X8Y64", - "sites": { - "SLICE_X10Y64": "SLICEM", - "SLICE_X11Y64": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y65": { - "grid_x": 24, - "grid_y": 140, - "segment": "SEG_CLBLM_L_X8Y65", - "sites": { - "SLICE_X10Y65": "SLICEM", - "SLICE_X11Y65": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y66": { - "grid_x": 24, - "grid_y": 139, - "segment": "SEG_CLBLM_L_X8Y66", - "sites": { - "SLICE_X10Y66": "SLICEM", - "SLICE_X11Y66": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y67": { - "grid_x": 24, - "grid_y": 138, - "segment": "SEG_CLBLM_L_X8Y67", - "sites": { - "SLICE_X10Y67": "SLICEM", - "SLICE_X11Y67": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y68": { - "grid_x": 24, - "grid_y": 137, - "segment": "SEG_CLBLM_L_X8Y68", - "sites": { - "SLICE_X10Y68": "SLICEM", - "SLICE_X11Y68": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y69": { - "grid_x": 24, - "grid_y": 136, - "segment": "SEG_CLBLM_L_X8Y69", - "sites": { - "SLICE_X10Y69": "SLICEM", - "SLICE_X11Y69": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y70": { - "grid_x": 24, - "grid_y": 135, - "segment": "SEG_CLBLM_L_X8Y70", - "sites": { - "SLICE_X10Y70": "SLICEM", - "SLICE_X11Y70": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y71": { - "grid_x": 24, - "grid_y": 134, - "segment": "SEG_CLBLM_L_X8Y71", - "sites": { - "SLICE_X10Y71": "SLICEM", - "SLICE_X11Y71": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y72": { - "grid_x": 24, - "grid_y": 133, - "segment": "SEG_CLBLM_L_X8Y72", - "sites": { - "SLICE_X10Y72": "SLICEM", - "SLICE_X11Y72": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y73": { - "grid_x": 24, - "grid_y": 132, - "segment": "SEG_CLBLM_L_X8Y73", - "sites": { - "SLICE_X10Y73": "SLICEM", - "SLICE_X11Y73": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y74": { - "grid_x": 24, - "grid_y": 131, - "segment": "SEG_CLBLM_L_X8Y74", - "sites": { - "SLICE_X10Y74": "SLICEM", - "SLICE_X11Y74": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y75": { - "grid_x": 24, - "grid_y": 129, - "segment": "SEG_CLBLM_L_X8Y75", - "sites": { - "SLICE_X10Y75": "SLICEM", - "SLICE_X11Y75": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y76": { - "grid_x": 24, - "grid_y": 128, - "segment": "SEG_CLBLM_L_X8Y76", - "sites": { - "SLICE_X10Y76": "SLICEM", - "SLICE_X11Y76": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y77": { - "grid_x": 24, - "grid_y": 127, - "segment": "SEG_CLBLM_L_X8Y77", - "sites": { - "SLICE_X10Y77": "SLICEM", - "SLICE_X11Y77": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y78": { - "grid_x": 24, - "grid_y": 126, - "segment": "SEG_CLBLM_L_X8Y78", - "sites": { - "SLICE_X10Y78": "SLICEM", - "SLICE_X11Y78": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y79": { - "grid_x": 24, - "grid_y": 125, - "segment": "SEG_CLBLM_L_X8Y79", - "sites": { - "SLICE_X10Y79": "SLICEM", - "SLICE_X11Y79": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y80": { - "grid_x": 24, - "grid_y": 124, - "segment": "SEG_CLBLM_L_X8Y80", - "sites": { - "SLICE_X10Y80": "SLICEM", - "SLICE_X11Y80": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y81": { - "grid_x": 24, - "grid_y": 123, - "segment": "SEG_CLBLM_L_X8Y81", - "sites": { - "SLICE_X10Y81": "SLICEM", - "SLICE_X11Y81": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y82": { - "grid_x": 24, - "grid_y": 122, - "segment": "SEG_CLBLM_L_X8Y82", - "sites": { - "SLICE_X10Y82": "SLICEM", - "SLICE_X11Y82": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y83": { - "grid_x": 24, - "grid_y": 121, - "segment": "SEG_CLBLM_L_X8Y83", - "sites": { - "SLICE_X10Y83": "SLICEM", - "SLICE_X11Y83": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y84": { - "grid_x": 24, - "grid_y": 120, - "segment": "SEG_CLBLM_L_X8Y84", - "sites": { - "SLICE_X10Y84": "SLICEM", - "SLICE_X11Y84": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y85": { - "grid_x": 24, - "grid_y": 119, - "segment": "SEG_CLBLM_L_X8Y85", - "sites": { - "SLICE_X10Y85": "SLICEM", - "SLICE_X11Y85": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y86": { - "grid_x": 24, - "grid_y": 118, - "segment": "SEG_CLBLM_L_X8Y86", - "sites": { - "SLICE_X10Y86": "SLICEM", - "SLICE_X11Y86": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y87": { - "grid_x": 24, - "grid_y": 117, - "segment": "SEG_CLBLM_L_X8Y87", - "sites": { - "SLICE_X10Y87": "SLICEM", - "SLICE_X11Y87": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y88": { - "grid_x": 24, - "grid_y": 116, - "segment": "SEG_CLBLM_L_X8Y88", - "sites": { - "SLICE_X10Y88": "SLICEM", - "SLICE_X11Y88": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y89": { - "grid_x": 24, - "grid_y": 115, - "segment": "SEG_CLBLM_L_X8Y89", - "sites": { - "SLICE_X10Y89": "SLICEM", - "SLICE_X11Y89": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y90": { - "grid_x": 24, - "grid_y": 114, - "segment": "SEG_CLBLM_L_X8Y90", - "sites": { - "SLICE_X10Y90": "SLICEM", - "SLICE_X11Y90": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y91": { - "grid_x": 24, - "grid_y": 113, - "segment": "SEG_CLBLM_L_X8Y91", - "sites": { - "SLICE_X10Y91": "SLICEM", - "SLICE_X11Y91": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y92": { - "grid_x": 24, - "grid_y": 112, - "segment": "SEG_CLBLM_L_X8Y92", - "sites": { - "SLICE_X10Y92": "SLICEM", - "SLICE_X11Y92": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y93": { - "grid_x": 24, - "grid_y": 111, - "segment": "SEG_CLBLM_L_X8Y93", - "sites": { - "SLICE_X10Y93": "SLICEM", - "SLICE_X11Y93": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y94": { - "grid_x": 24, - "grid_y": 110, - "segment": "SEG_CLBLM_L_X8Y94", - "sites": { - "SLICE_X10Y94": "SLICEM", - "SLICE_X11Y94": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y95": { - "grid_x": 24, - "grid_y": 109, - "segment": "SEG_CLBLM_L_X8Y95", - "sites": { - "SLICE_X10Y95": "SLICEM", - "SLICE_X11Y95": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y96": { - "grid_x": 24, - "grid_y": 108, - "segment": "SEG_CLBLM_L_X8Y96", - "sites": { - "SLICE_X10Y96": "SLICEM", - "SLICE_X11Y96": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y97": { - "grid_x": 24, - "grid_y": 107, - "segment": "SEG_CLBLM_L_X8Y97", - "sites": { - "SLICE_X10Y97": "SLICEM", - "SLICE_X11Y97": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y98": { - "grid_x": 24, - "grid_y": 106, - "segment": "SEG_CLBLM_L_X8Y98", - "sites": { - "SLICE_X10Y98": "SLICEM", - "SLICE_X11Y98": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_L_X8Y99": { - "grid_x": 24, - "grid_y": 105, - "segment": "SEG_CLBLM_L_X8Y99", - "sites": { - "SLICE_X10Y99": "SLICEM", - "SLICE_X11Y99": "SLICEL" - }, - "type": "CLBLM_L" - }, - "CLBLM_R_X11Y50": { - "grid_x": 33, - "grid_y": 155, - "segment": "SEG_CLBLM_R_X11Y50", - "sites": { - "SLICE_X14Y50": "SLICEM", - "SLICE_X15Y50": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y51": { - "grid_x": 33, - "grid_y": 154, - "segment": "SEG_CLBLM_R_X11Y51", - "sites": { - "SLICE_X14Y51": "SLICEM", - "SLICE_X15Y51": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y52": { - "grid_x": 33, - "grid_y": 153, - "segment": "SEG_CLBLM_R_X11Y52", - "sites": { - "SLICE_X14Y52": "SLICEM", - "SLICE_X15Y52": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y53": { - "grid_x": 33, - "grid_y": 152, - "segment": "SEG_CLBLM_R_X11Y53", - "sites": { - "SLICE_X14Y53": "SLICEM", - "SLICE_X15Y53": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y54": { - "grid_x": 33, - "grid_y": 151, - "segment": "SEG_CLBLM_R_X11Y54", - "sites": { - "SLICE_X14Y54": "SLICEM", - "SLICE_X15Y54": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y55": { - "grid_x": 33, - "grid_y": 150, - "segment": "SEG_CLBLM_R_X11Y55", - "sites": { - "SLICE_X14Y55": "SLICEM", - "SLICE_X15Y55": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y56": { - "grid_x": 33, - "grid_y": 149, - "segment": "SEG_CLBLM_R_X11Y56", - "sites": { - "SLICE_X14Y56": "SLICEM", - "SLICE_X15Y56": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y57": { - "grid_x": 33, - "grid_y": 148, - "segment": "SEG_CLBLM_R_X11Y57", - "sites": { - "SLICE_X14Y57": "SLICEM", - "SLICE_X15Y57": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y58": { - "grid_x": 33, - "grid_y": 147, - "segment": "SEG_CLBLM_R_X11Y58", - "sites": { - "SLICE_X14Y58": "SLICEM", - "SLICE_X15Y58": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y59": { - "grid_x": 33, - "grid_y": 146, - "segment": "SEG_CLBLM_R_X11Y59", - "sites": { - "SLICE_X14Y59": "SLICEM", - "SLICE_X15Y59": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y60": { - "grid_x": 33, - "grid_y": 145, - "segment": "SEG_CLBLM_R_X11Y60", - "sites": { - "SLICE_X14Y60": "SLICEM", - "SLICE_X15Y60": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y61": { - "grid_x": 33, - "grid_y": 144, - "segment": "SEG_CLBLM_R_X11Y61", - "sites": { - "SLICE_X14Y61": "SLICEM", - "SLICE_X15Y61": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y62": { - "grid_x": 33, - "grid_y": 143, - "segment": "SEG_CLBLM_R_X11Y62", - "sites": { - "SLICE_X14Y62": "SLICEM", - "SLICE_X15Y62": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y63": { - "grid_x": 33, - "grid_y": 142, - "segment": "SEG_CLBLM_R_X11Y63", - "sites": { - "SLICE_X14Y63": "SLICEM", - "SLICE_X15Y63": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y64": { - "grid_x": 33, - "grid_y": 141, - "segment": "SEG_CLBLM_R_X11Y64", - "sites": { - "SLICE_X14Y64": "SLICEM", - "SLICE_X15Y64": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y65": { - "grid_x": 33, - "grid_y": 140, - "segment": "SEG_CLBLM_R_X11Y65", - "sites": { - "SLICE_X14Y65": "SLICEM", - "SLICE_X15Y65": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y66": { - "grid_x": 33, - "grid_y": 139, - "segment": "SEG_CLBLM_R_X11Y66", - "sites": { - "SLICE_X14Y66": "SLICEM", - "SLICE_X15Y66": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y67": { - "grid_x": 33, - "grid_y": 138, - "segment": "SEG_CLBLM_R_X11Y67", - "sites": { - "SLICE_X14Y67": "SLICEM", - "SLICE_X15Y67": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y68": { - "grid_x": 33, - "grid_y": 137, - "segment": "SEG_CLBLM_R_X11Y68", - "sites": { - "SLICE_X14Y68": "SLICEM", - "SLICE_X15Y68": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y69": { - "grid_x": 33, - "grid_y": 136, - "segment": "SEG_CLBLM_R_X11Y69", - "sites": { - "SLICE_X14Y69": "SLICEM", - "SLICE_X15Y69": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y70": { - "grid_x": 33, - "grid_y": 135, - "segment": "SEG_CLBLM_R_X11Y70", - "sites": { - "SLICE_X14Y70": "SLICEM", - "SLICE_X15Y70": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y71": { - "grid_x": 33, - "grid_y": 134, - "segment": "SEG_CLBLM_R_X11Y71", - "sites": { - "SLICE_X14Y71": "SLICEM", - "SLICE_X15Y71": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y72": { - "grid_x": 33, - "grid_y": 133, - "segment": "SEG_CLBLM_R_X11Y72", - "sites": { - "SLICE_X14Y72": "SLICEM", - "SLICE_X15Y72": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y73": { - "grid_x": 33, - "grid_y": 132, - "segment": "SEG_CLBLM_R_X11Y73", - "sites": { - "SLICE_X14Y73": "SLICEM", - "SLICE_X15Y73": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y74": { - "grid_x": 33, - "grid_y": 131, - "segment": "SEG_CLBLM_R_X11Y74", - "sites": { - "SLICE_X14Y74": "SLICEM", - "SLICE_X15Y74": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y75": { - "grid_x": 33, - "grid_y": 129, - "segment": "SEG_CLBLM_R_X11Y75", - "sites": { - "SLICE_X14Y75": "SLICEM", - "SLICE_X15Y75": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y76": { - "grid_x": 33, - "grid_y": 128, - "segment": "SEG_CLBLM_R_X11Y76", - "sites": { - "SLICE_X14Y76": "SLICEM", - "SLICE_X15Y76": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y77": { - "grid_x": 33, - "grid_y": 127, - "segment": "SEG_CLBLM_R_X11Y77", - "sites": { - "SLICE_X14Y77": "SLICEM", - "SLICE_X15Y77": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y78": { - "grid_x": 33, - "grid_y": 126, - "segment": "SEG_CLBLM_R_X11Y78", - "sites": { - "SLICE_X14Y78": "SLICEM", - "SLICE_X15Y78": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y79": { - "grid_x": 33, - "grid_y": 125, - "segment": "SEG_CLBLM_R_X11Y79", - "sites": { - "SLICE_X14Y79": "SLICEM", - "SLICE_X15Y79": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y80": { - "grid_x": 33, - "grid_y": 124, - "segment": "SEG_CLBLM_R_X11Y80", - "sites": { - "SLICE_X14Y80": "SLICEM", - "SLICE_X15Y80": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y81": { - "grid_x": 33, - "grid_y": 123, - "segment": "SEG_CLBLM_R_X11Y81", - "sites": { - "SLICE_X14Y81": "SLICEM", - "SLICE_X15Y81": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y82": { - "grid_x": 33, - "grid_y": 122, - "segment": "SEG_CLBLM_R_X11Y82", - "sites": { - "SLICE_X14Y82": "SLICEM", - "SLICE_X15Y82": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y83": { - "grid_x": 33, - "grid_y": 121, - "segment": "SEG_CLBLM_R_X11Y83", - "sites": { - "SLICE_X14Y83": "SLICEM", - "SLICE_X15Y83": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y84": { - "grid_x": 33, - "grid_y": 120, - "segment": "SEG_CLBLM_R_X11Y84", - "sites": { - "SLICE_X14Y84": "SLICEM", - "SLICE_X15Y84": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y85": { - "grid_x": 33, - "grid_y": 119, - "segment": "SEG_CLBLM_R_X11Y85", - "sites": { - "SLICE_X14Y85": "SLICEM", - "SLICE_X15Y85": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y86": { - "grid_x": 33, - "grid_y": 118, - "segment": "SEG_CLBLM_R_X11Y86", - "sites": { - "SLICE_X14Y86": "SLICEM", - "SLICE_X15Y86": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y87": { - "grid_x": 33, - "grid_y": 117, - "segment": "SEG_CLBLM_R_X11Y87", - "sites": { - "SLICE_X14Y87": "SLICEM", - "SLICE_X15Y87": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y88": { - "grid_x": 33, - "grid_y": 116, - "segment": "SEG_CLBLM_R_X11Y88", - "sites": { - "SLICE_X14Y88": "SLICEM", - "SLICE_X15Y88": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y89": { - "grid_x": 33, - "grid_y": 115, - "segment": "SEG_CLBLM_R_X11Y89", - "sites": { - "SLICE_X14Y89": "SLICEM", - "SLICE_X15Y89": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y90": { - "grid_x": 33, - "grid_y": 114, - "segment": "SEG_CLBLM_R_X11Y90", - "sites": { - "SLICE_X14Y90": "SLICEM", - "SLICE_X15Y90": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y91": { - "grid_x": 33, - "grid_y": 113, - "segment": "SEG_CLBLM_R_X11Y91", - "sites": { - "SLICE_X14Y91": "SLICEM", - "SLICE_X15Y91": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y92": { - "grid_x": 33, - "grid_y": 112, - "segment": "SEG_CLBLM_R_X11Y92", - "sites": { - "SLICE_X14Y92": "SLICEM", - "SLICE_X15Y92": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y93": { - "grid_x": 33, - "grid_y": 111, - "segment": "SEG_CLBLM_R_X11Y93", - "sites": { - "SLICE_X14Y93": "SLICEM", - "SLICE_X15Y93": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y94": { - "grid_x": 33, - "grid_y": 110, - "segment": "SEG_CLBLM_R_X11Y94", - "sites": { - "SLICE_X14Y94": "SLICEM", - "SLICE_X15Y94": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y95": { - "grid_x": 33, - "grid_y": 109, - "segment": "SEG_CLBLM_R_X11Y95", - "sites": { - "SLICE_X14Y95": "SLICEM", - "SLICE_X15Y95": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y96": { - "grid_x": 33, - "grid_y": 108, - "segment": "SEG_CLBLM_R_X11Y96", - "sites": { - "SLICE_X14Y96": "SLICEM", - "SLICE_X15Y96": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y97": { - "grid_x": 33, - "grid_y": 107, - "segment": "SEG_CLBLM_R_X11Y97", - "sites": { - "SLICE_X14Y97": "SLICEM", - "SLICE_X15Y97": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y98": { - "grid_x": 33, - "grid_y": 106, - "segment": "SEG_CLBLM_R_X11Y98", - "sites": { - "SLICE_X14Y98": "SLICEM", - "SLICE_X15Y98": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X11Y99": { - "grid_x": 33, - "grid_y": 105, - "segment": "SEG_CLBLM_R_X11Y99", - "sites": { - "SLICE_X14Y99": "SLICEM", - "SLICE_X15Y99": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y50": { - "grid_x": 37, - "grid_y": 155, - "segment": "SEG_CLBLM_R_X13Y50", - "sites": { - "SLICE_X18Y50": "SLICEM", - "SLICE_X19Y50": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y51": { - "grid_x": 37, - "grid_y": 154, - "segment": "SEG_CLBLM_R_X13Y51", - "sites": { - "SLICE_X18Y51": "SLICEM", - "SLICE_X19Y51": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y52": { - "grid_x": 37, - "grid_y": 153, - "segment": "SEG_CLBLM_R_X13Y52", - "sites": { - "SLICE_X18Y52": "SLICEM", - "SLICE_X19Y52": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y53": { - "grid_x": 37, - "grid_y": 152, - "segment": "SEG_CLBLM_R_X13Y53", - "sites": { - "SLICE_X18Y53": "SLICEM", - "SLICE_X19Y53": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y54": { - "grid_x": 37, - "grid_y": 151, - "segment": "SEG_CLBLM_R_X13Y54", - "sites": { - "SLICE_X18Y54": "SLICEM", - "SLICE_X19Y54": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y55": { - "grid_x": 37, - "grid_y": 150, - "segment": "SEG_CLBLM_R_X13Y55", - "sites": { - "SLICE_X18Y55": "SLICEM", - "SLICE_X19Y55": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y56": { - "grid_x": 37, - "grid_y": 149, - "segment": "SEG_CLBLM_R_X13Y56", - "sites": { - "SLICE_X18Y56": "SLICEM", - "SLICE_X19Y56": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y57": { - "grid_x": 37, - "grid_y": 148, - "segment": "SEG_CLBLM_R_X13Y57", - "sites": { - "SLICE_X18Y57": "SLICEM", - "SLICE_X19Y57": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y58": { - "grid_x": 37, - "grid_y": 147, - "segment": "SEG_CLBLM_R_X13Y58", - "sites": { - "SLICE_X18Y58": "SLICEM", - "SLICE_X19Y58": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y59": { - "grid_x": 37, - "grid_y": 146, - "segment": "SEG_CLBLM_R_X13Y59", - "sites": { - "SLICE_X18Y59": "SLICEM", - "SLICE_X19Y59": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y60": { - "grid_x": 37, - "grid_y": 145, - "segment": "SEG_CLBLM_R_X13Y60", - "sites": { - "SLICE_X18Y60": "SLICEM", - "SLICE_X19Y60": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y61": { - "grid_x": 37, - "grid_y": 144, - "segment": "SEG_CLBLM_R_X13Y61", - "sites": { - "SLICE_X18Y61": "SLICEM", - "SLICE_X19Y61": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y62": { - "grid_x": 37, - "grid_y": 143, - "segment": "SEG_CLBLM_R_X13Y62", - "sites": { - "SLICE_X18Y62": "SLICEM", - "SLICE_X19Y62": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y63": { - "grid_x": 37, - "grid_y": 142, - "segment": "SEG_CLBLM_R_X13Y63", - "sites": { - "SLICE_X18Y63": "SLICEM", - "SLICE_X19Y63": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y64": { - "grid_x": 37, - "grid_y": 141, - "segment": "SEG_CLBLM_R_X13Y64", - "sites": { - "SLICE_X18Y64": "SLICEM", - "SLICE_X19Y64": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y65": { - "grid_x": 37, - "grid_y": 140, - "segment": "SEG_CLBLM_R_X13Y65", - "sites": { - "SLICE_X18Y65": "SLICEM", - "SLICE_X19Y65": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y66": { - "grid_x": 37, - "grid_y": 139, - "segment": "SEG_CLBLM_R_X13Y66", - "sites": { - "SLICE_X18Y66": "SLICEM", - "SLICE_X19Y66": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y67": { - "grid_x": 37, - "grid_y": 138, - "segment": "SEG_CLBLM_R_X13Y67", - "sites": { - "SLICE_X18Y67": "SLICEM", - "SLICE_X19Y67": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y68": { - "grid_x": 37, - "grid_y": 137, - "segment": "SEG_CLBLM_R_X13Y68", - "sites": { - "SLICE_X18Y68": "SLICEM", - "SLICE_X19Y68": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y69": { - "grid_x": 37, - "grid_y": 136, - "segment": "SEG_CLBLM_R_X13Y69", - "sites": { - "SLICE_X18Y69": "SLICEM", - "SLICE_X19Y69": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y70": { - "grid_x": 37, - "grid_y": 135, - "segment": "SEG_CLBLM_R_X13Y70", - "sites": { - "SLICE_X18Y70": "SLICEM", - "SLICE_X19Y70": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y71": { - "grid_x": 37, - "grid_y": 134, - "segment": "SEG_CLBLM_R_X13Y71", - "sites": { - "SLICE_X18Y71": "SLICEM", - "SLICE_X19Y71": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y72": { - "grid_x": 37, - "grid_y": 133, - "segment": "SEG_CLBLM_R_X13Y72", - "sites": { - "SLICE_X18Y72": "SLICEM", - "SLICE_X19Y72": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y73": { - "grid_x": 37, - "grid_y": 132, - "segment": "SEG_CLBLM_R_X13Y73", - "sites": { - "SLICE_X18Y73": "SLICEM", - "SLICE_X19Y73": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y74": { - "grid_x": 37, - "grid_y": 131, - "segment": "SEG_CLBLM_R_X13Y74", - "sites": { - "SLICE_X18Y74": "SLICEM", - "SLICE_X19Y74": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y75": { - "grid_x": 37, - "grid_y": 129, - "segment": "SEG_CLBLM_R_X13Y75", - "sites": { - "SLICE_X18Y75": "SLICEM", - "SLICE_X19Y75": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y76": { - "grid_x": 37, - "grid_y": 128, - "segment": "SEG_CLBLM_R_X13Y76", - "sites": { - "SLICE_X18Y76": "SLICEM", - "SLICE_X19Y76": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y77": { - "grid_x": 37, - "grid_y": 127, - "segment": "SEG_CLBLM_R_X13Y77", - "sites": { - "SLICE_X18Y77": "SLICEM", - "SLICE_X19Y77": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y78": { - "grid_x": 37, - "grid_y": 126, - "segment": "SEG_CLBLM_R_X13Y78", - "sites": { - "SLICE_X18Y78": "SLICEM", - "SLICE_X19Y78": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y79": { - "grid_x": 37, - "grid_y": 125, - "segment": "SEG_CLBLM_R_X13Y79", - "sites": { - "SLICE_X18Y79": "SLICEM", - "SLICE_X19Y79": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y80": { - "grid_x": 37, - "grid_y": 124, - "segment": "SEG_CLBLM_R_X13Y80", - "sites": { - "SLICE_X18Y80": "SLICEM", - "SLICE_X19Y80": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y81": { - "grid_x": 37, - "grid_y": 123, - "segment": "SEG_CLBLM_R_X13Y81", - "sites": { - "SLICE_X18Y81": "SLICEM", - "SLICE_X19Y81": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y82": { - "grid_x": 37, - "grid_y": 122, - "segment": "SEG_CLBLM_R_X13Y82", - "sites": { - "SLICE_X18Y82": "SLICEM", - "SLICE_X19Y82": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y83": { - "grid_x": 37, - "grid_y": 121, - "segment": "SEG_CLBLM_R_X13Y83", - "sites": { - "SLICE_X18Y83": "SLICEM", - "SLICE_X19Y83": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y84": { - "grid_x": 37, - "grid_y": 120, - "segment": "SEG_CLBLM_R_X13Y84", - "sites": { - "SLICE_X18Y84": "SLICEM", - "SLICE_X19Y84": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y85": { - "grid_x": 37, - "grid_y": 119, - "segment": "SEG_CLBLM_R_X13Y85", - "sites": { - "SLICE_X18Y85": "SLICEM", - "SLICE_X19Y85": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y86": { - "grid_x": 37, - "grid_y": 118, - "segment": "SEG_CLBLM_R_X13Y86", - "sites": { - "SLICE_X18Y86": "SLICEM", - "SLICE_X19Y86": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y87": { - "grid_x": 37, - "grid_y": 117, - "segment": "SEG_CLBLM_R_X13Y87", - "sites": { - "SLICE_X18Y87": "SLICEM", - "SLICE_X19Y87": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y88": { - "grid_x": 37, - "grid_y": 116, - "segment": "SEG_CLBLM_R_X13Y88", - "sites": { - "SLICE_X18Y88": "SLICEM", - "SLICE_X19Y88": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y89": { - "grid_x": 37, - "grid_y": 115, - "segment": "SEG_CLBLM_R_X13Y89", - "sites": { - "SLICE_X18Y89": "SLICEM", - "SLICE_X19Y89": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y90": { - "grid_x": 37, - "grid_y": 114, - "segment": "SEG_CLBLM_R_X13Y90", - "sites": { - "SLICE_X18Y90": "SLICEM", - "SLICE_X19Y90": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y91": { - "grid_x": 37, - "grid_y": 113, - "segment": "SEG_CLBLM_R_X13Y91", - "sites": { - "SLICE_X18Y91": "SLICEM", - "SLICE_X19Y91": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y92": { - "grid_x": 37, - "grid_y": 112, - "segment": "SEG_CLBLM_R_X13Y92", - "sites": { - "SLICE_X18Y92": "SLICEM", - "SLICE_X19Y92": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y93": { - "grid_x": 37, - "grid_y": 111, - "segment": "SEG_CLBLM_R_X13Y93", - "sites": { - "SLICE_X18Y93": "SLICEM", - "SLICE_X19Y93": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y94": { - "grid_x": 37, - "grid_y": 110, - "segment": "SEG_CLBLM_R_X13Y94", - "sites": { - "SLICE_X18Y94": "SLICEM", - "SLICE_X19Y94": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y95": { - "grid_x": 37, - "grid_y": 109, - "segment": "SEG_CLBLM_R_X13Y95", - "sites": { - "SLICE_X18Y95": "SLICEM", - "SLICE_X19Y95": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y96": { - "grid_x": 37, - "grid_y": 108, - "segment": "SEG_CLBLM_R_X13Y96", - "sites": { - "SLICE_X18Y96": "SLICEM", - "SLICE_X19Y96": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y97": { - "grid_x": 37, - "grid_y": 107, - "segment": "SEG_CLBLM_R_X13Y97", - "sites": { - "SLICE_X18Y97": "SLICEM", - "SLICE_X19Y97": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y98": { - "grid_x": 37, - "grid_y": 106, - "segment": "SEG_CLBLM_R_X13Y98", - "sites": { - "SLICE_X18Y98": "SLICEM", - "SLICE_X19Y98": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X13Y99": { - "grid_x": 37, - "grid_y": 105, - "segment": "SEG_CLBLM_R_X13Y99", - "sites": { - "SLICE_X18Y99": "SLICEM", - "SLICE_X19Y99": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y50": { - "grid_x": 13, - "grid_y": 155, - "segment": "SEG_CLBLM_R_X3Y50", - "sites": { - "SLICE_X2Y50": "SLICEM", - "SLICE_X3Y50": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y51": { - "grid_x": 13, - "grid_y": 154, - "segment": "SEG_CLBLM_R_X3Y51", - "sites": { - "SLICE_X2Y51": "SLICEM", - "SLICE_X3Y51": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y52": { - "grid_x": 13, - "grid_y": 153, - "segment": "SEG_CLBLM_R_X3Y52", - "sites": { - "SLICE_X2Y52": "SLICEM", - "SLICE_X3Y52": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y53": { - "grid_x": 13, - "grid_y": 152, - "segment": "SEG_CLBLM_R_X3Y53", - "sites": { - "SLICE_X2Y53": "SLICEM", - "SLICE_X3Y53": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y54": { - "grid_x": 13, - "grid_y": 151, - "segment": "SEG_CLBLM_R_X3Y54", - "sites": { - "SLICE_X2Y54": "SLICEM", - "SLICE_X3Y54": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y55": { - "grid_x": 13, - "grid_y": 150, - "segment": "SEG_CLBLM_R_X3Y55", - "sites": { - "SLICE_X2Y55": "SLICEM", - "SLICE_X3Y55": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y56": { - "grid_x": 13, - "grid_y": 149, - "segment": "SEG_CLBLM_R_X3Y56", - "sites": { - "SLICE_X2Y56": "SLICEM", - "SLICE_X3Y56": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y57": { - "grid_x": 13, - "grid_y": 148, - "segment": "SEG_CLBLM_R_X3Y57", - "sites": { - "SLICE_X2Y57": "SLICEM", - "SLICE_X3Y57": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y58": { - "grid_x": 13, - "grid_y": 147, - "segment": "SEG_CLBLM_R_X3Y58", - "sites": { - "SLICE_X2Y58": "SLICEM", - "SLICE_X3Y58": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y59": { - "grid_x": 13, - "grid_y": 146, - "segment": "SEG_CLBLM_R_X3Y59", - "sites": { - "SLICE_X2Y59": "SLICEM", - "SLICE_X3Y59": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y60": { - "grid_x": 13, - "grid_y": 145, - "segment": "SEG_CLBLM_R_X3Y60", - "sites": { - "SLICE_X2Y60": "SLICEM", - "SLICE_X3Y60": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y61": { - "grid_x": 13, - "grid_y": 144, - "segment": "SEG_CLBLM_R_X3Y61", - "sites": { - "SLICE_X2Y61": "SLICEM", - "SLICE_X3Y61": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y62": { - "grid_x": 13, - "grid_y": 143, - "segment": "SEG_CLBLM_R_X3Y62", - "sites": { - "SLICE_X2Y62": "SLICEM", - "SLICE_X3Y62": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y63": { - "grid_x": 13, - "grid_y": 142, - "segment": "SEG_CLBLM_R_X3Y63", - "sites": { - "SLICE_X2Y63": "SLICEM", - "SLICE_X3Y63": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y64": { - "grid_x": 13, - "grid_y": 141, - "segment": "SEG_CLBLM_R_X3Y64", - "sites": { - "SLICE_X2Y64": "SLICEM", - "SLICE_X3Y64": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y65": { - "grid_x": 13, - "grid_y": 140, - "segment": "SEG_CLBLM_R_X3Y65", - "sites": { - "SLICE_X2Y65": "SLICEM", - "SLICE_X3Y65": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y66": { - "grid_x": 13, - "grid_y": 139, - "segment": "SEG_CLBLM_R_X3Y66", - "sites": { - "SLICE_X2Y66": "SLICEM", - "SLICE_X3Y66": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y67": { - "grid_x": 13, - "grid_y": 138, - "segment": "SEG_CLBLM_R_X3Y67", - "sites": { - "SLICE_X2Y67": "SLICEM", - "SLICE_X3Y67": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y68": { - "grid_x": 13, - "grid_y": 137, - "segment": "SEG_CLBLM_R_X3Y68", - "sites": { - "SLICE_X2Y68": "SLICEM", - "SLICE_X3Y68": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y69": { - "grid_x": 13, - "grid_y": 136, - "segment": "SEG_CLBLM_R_X3Y69", - "sites": { - "SLICE_X2Y69": "SLICEM", - "SLICE_X3Y69": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y70": { - "grid_x": 13, - "grid_y": 135, - "segment": "SEG_CLBLM_R_X3Y70", - "sites": { - "SLICE_X2Y70": "SLICEM", - "SLICE_X3Y70": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y71": { - "grid_x": 13, - "grid_y": 134, - "segment": "SEG_CLBLM_R_X3Y71", - "sites": { - "SLICE_X2Y71": "SLICEM", - "SLICE_X3Y71": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y72": { - "grid_x": 13, - "grid_y": 133, - "segment": "SEG_CLBLM_R_X3Y72", - "sites": { - "SLICE_X2Y72": "SLICEM", - "SLICE_X3Y72": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y73": { - "grid_x": 13, - "grid_y": 132, - "segment": "SEG_CLBLM_R_X3Y73", - "sites": { - "SLICE_X2Y73": "SLICEM", - "SLICE_X3Y73": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y74": { - "grid_x": 13, - "grid_y": 131, - "segment": "SEG_CLBLM_R_X3Y74", - "sites": { - "SLICE_X2Y74": "SLICEM", - "SLICE_X3Y74": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y75": { - "grid_x": 13, - "grid_y": 129, - "segment": "SEG_CLBLM_R_X3Y75", - "sites": { - "SLICE_X2Y75": "SLICEM", - "SLICE_X3Y75": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y76": { - "grid_x": 13, - "grid_y": 128, - "segment": "SEG_CLBLM_R_X3Y76", - "sites": { - "SLICE_X2Y76": "SLICEM", - "SLICE_X3Y76": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y77": { - "grid_x": 13, - "grid_y": 127, - "segment": "SEG_CLBLM_R_X3Y77", - "sites": { - "SLICE_X2Y77": "SLICEM", - "SLICE_X3Y77": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y78": { - "grid_x": 13, - "grid_y": 126, - "segment": "SEG_CLBLM_R_X3Y78", - "sites": { - "SLICE_X2Y78": "SLICEM", - "SLICE_X3Y78": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y79": { - "grid_x": 13, - "grid_y": 125, - "segment": "SEG_CLBLM_R_X3Y79", - "sites": { - "SLICE_X2Y79": "SLICEM", - "SLICE_X3Y79": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y80": { - "grid_x": 13, - "grid_y": 124, - "segment": "SEG_CLBLM_R_X3Y80", - "sites": { - "SLICE_X2Y80": "SLICEM", - "SLICE_X3Y80": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y81": { - "grid_x": 13, - "grid_y": 123, - "segment": "SEG_CLBLM_R_X3Y81", - "sites": { - "SLICE_X2Y81": "SLICEM", - "SLICE_X3Y81": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y82": { - "grid_x": 13, - "grid_y": 122, - "segment": "SEG_CLBLM_R_X3Y82", - "sites": { - "SLICE_X2Y82": "SLICEM", - "SLICE_X3Y82": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y83": { - "grid_x": 13, - "grid_y": 121, - "segment": "SEG_CLBLM_R_X3Y83", - "sites": { - "SLICE_X2Y83": "SLICEM", - "SLICE_X3Y83": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y84": { - "grid_x": 13, - "grid_y": 120, - "segment": "SEG_CLBLM_R_X3Y84", - "sites": { - "SLICE_X2Y84": "SLICEM", - "SLICE_X3Y84": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y85": { - "grid_x": 13, - "grid_y": 119, - "segment": "SEG_CLBLM_R_X3Y85", - "sites": { - "SLICE_X2Y85": "SLICEM", - "SLICE_X3Y85": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y86": { - "grid_x": 13, - "grid_y": 118, - "segment": "SEG_CLBLM_R_X3Y86", - "sites": { - "SLICE_X2Y86": "SLICEM", - "SLICE_X3Y86": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y87": { - "grid_x": 13, - "grid_y": 117, - "segment": "SEG_CLBLM_R_X3Y87", - "sites": { - "SLICE_X2Y87": "SLICEM", - "SLICE_X3Y87": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y88": { - "grid_x": 13, - "grid_y": 116, - "segment": "SEG_CLBLM_R_X3Y88", - "sites": { - "SLICE_X2Y88": "SLICEM", - "SLICE_X3Y88": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y89": { - "grid_x": 13, - "grid_y": 115, - "segment": "SEG_CLBLM_R_X3Y89", - "sites": { - "SLICE_X2Y89": "SLICEM", - "SLICE_X3Y89": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y90": { - "grid_x": 13, - "grid_y": 114, - "segment": "SEG_CLBLM_R_X3Y90", - "sites": { - "SLICE_X2Y90": "SLICEM", - "SLICE_X3Y90": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y91": { - "grid_x": 13, - "grid_y": 113, - "segment": "SEG_CLBLM_R_X3Y91", - "sites": { - "SLICE_X2Y91": "SLICEM", - "SLICE_X3Y91": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y92": { - "grid_x": 13, - "grid_y": 112, - "segment": "SEG_CLBLM_R_X3Y92", - "sites": { - "SLICE_X2Y92": "SLICEM", - "SLICE_X3Y92": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y93": { - "grid_x": 13, - "grid_y": 111, - "segment": "SEG_CLBLM_R_X3Y93", - "sites": { - "SLICE_X2Y93": "SLICEM", - "SLICE_X3Y93": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y94": { - "grid_x": 13, - "grid_y": 110, - "segment": "SEG_CLBLM_R_X3Y94", - "sites": { - "SLICE_X2Y94": "SLICEM", - "SLICE_X3Y94": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y95": { - "grid_x": 13, - "grid_y": 109, - "segment": "SEG_CLBLM_R_X3Y95", - "sites": { - "SLICE_X2Y95": "SLICEM", - "SLICE_X3Y95": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y96": { - "grid_x": 13, - "grid_y": 108, - "segment": "SEG_CLBLM_R_X3Y96", - "sites": { - "SLICE_X2Y96": "SLICEM", - "SLICE_X3Y96": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y97": { - "grid_x": 13, - "grid_y": 107, - "segment": "SEG_CLBLM_R_X3Y97", - "sites": { - "SLICE_X2Y97": "SLICEM", - "SLICE_X3Y97": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y98": { - "grid_x": 13, - "grid_y": 106, - "segment": "SEG_CLBLM_R_X3Y98", - "sites": { - "SLICE_X2Y98": "SLICEM", - "SLICE_X3Y98": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X3Y99": { - "grid_x": 13, - "grid_y": 105, - "segment": "SEG_CLBLM_R_X3Y99", - "sites": { - "SLICE_X2Y99": "SLICEM", - "SLICE_X3Y99": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y50": { - "grid_x": 17, - "grid_y": 155, - "segment": "SEG_CLBLM_R_X5Y50", - "sites": { - "SLICE_X6Y50": "SLICEM", - "SLICE_X7Y50": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y51": { - "grid_x": 17, - "grid_y": 154, - "segment": "SEG_CLBLM_R_X5Y51", - "sites": { - "SLICE_X6Y51": "SLICEM", - "SLICE_X7Y51": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y52": { - "grid_x": 17, - "grid_y": 153, - "segment": "SEG_CLBLM_R_X5Y52", - "sites": { - "SLICE_X6Y52": "SLICEM", - "SLICE_X7Y52": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y53": { - "grid_x": 17, - "grid_y": 152, - "segment": "SEG_CLBLM_R_X5Y53", - "sites": { - "SLICE_X6Y53": "SLICEM", - "SLICE_X7Y53": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y54": { - "grid_x": 17, - "grid_y": 151, - "segment": "SEG_CLBLM_R_X5Y54", - "sites": { - "SLICE_X6Y54": "SLICEM", - "SLICE_X7Y54": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y55": { - "grid_x": 17, - "grid_y": 150, - "segment": "SEG_CLBLM_R_X5Y55", - "sites": { - "SLICE_X6Y55": "SLICEM", - "SLICE_X7Y55": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y56": { - "grid_x": 17, - "grid_y": 149, - "segment": "SEG_CLBLM_R_X5Y56", - "sites": { - "SLICE_X6Y56": "SLICEM", - "SLICE_X7Y56": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y57": { - "grid_x": 17, - "grid_y": 148, - "segment": "SEG_CLBLM_R_X5Y57", - "sites": { - "SLICE_X6Y57": "SLICEM", - "SLICE_X7Y57": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y58": { - "grid_x": 17, - "grid_y": 147, - "segment": "SEG_CLBLM_R_X5Y58", - "sites": { - "SLICE_X6Y58": "SLICEM", - "SLICE_X7Y58": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y59": { - "grid_x": 17, - "grid_y": 146, - "segment": "SEG_CLBLM_R_X5Y59", - "sites": { - "SLICE_X6Y59": "SLICEM", - "SLICE_X7Y59": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y60": { - "grid_x": 17, - "grid_y": 145, - "segment": "SEG_CLBLM_R_X5Y60", - "sites": { - "SLICE_X6Y60": "SLICEM", - "SLICE_X7Y60": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y61": { - "grid_x": 17, - "grid_y": 144, - "segment": "SEG_CLBLM_R_X5Y61", - "sites": { - "SLICE_X6Y61": "SLICEM", - "SLICE_X7Y61": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y62": { - "grid_x": 17, - "grid_y": 143, - "segment": "SEG_CLBLM_R_X5Y62", - "sites": { - "SLICE_X6Y62": "SLICEM", - "SLICE_X7Y62": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y63": { - "grid_x": 17, - "grid_y": 142, - "segment": "SEG_CLBLM_R_X5Y63", - "sites": { - "SLICE_X6Y63": "SLICEM", - "SLICE_X7Y63": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y64": { - "grid_x": 17, - "grid_y": 141, - "segment": "SEG_CLBLM_R_X5Y64", - "sites": { - "SLICE_X6Y64": "SLICEM", - "SLICE_X7Y64": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y65": { - "grid_x": 17, - "grid_y": 140, - "segment": "SEG_CLBLM_R_X5Y65", - "sites": { - "SLICE_X6Y65": "SLICEM", - "SLICE_X7Y65": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y66": { - "grid_x": 17, - "grid_y": 139, - "segment": "SEG_CLBLM_R_X5Y66", - "sites": { - "SLICE_X6Y66": "SLICEM", - "SLICE_X7Y66": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y67": { - "grid_x": 17, - "grid_y": 138, - "segment": "SEG_CLBLM_R_X5Y67", - "sites": { - "SLICE_X6Y67": "SLICEM", - "SLICE_X7Y67": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y68": { - "grid_x": 17, - "grid_y": 137, - "segment": "SEG_CLBLM_R_X5Y68", - "sites": { - "SLICE_X6Y68": "SLICEM", - "SLICE_X7Y68": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y69": { - "grid_x": 17, - "grid_y": 136, - "segment": "SEG_CLBLM_R_X5Y69", - "sites": { - "SLICE_X6Y69": "SLICEM", - "SLICE_X7Y69": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y70": { - "grid_x": 17, - "grid_y": 135, - "segment": "SEG_CLBLM_R_X5Y70", - "sites": { - "SLICE_X6Y70": "SLICEM", - "SLICE_X7Y70": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y71": { - "grid_x": 17, - "grid_y": 134, - "segment": "SEG_CLBLM_R_X5Y71", - "sites": { - "SLICE_X6Y71": "SLICEM", - "SLICE_X7Y71": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y72": { - "grid_x": 17, - "grid_y": 133, - "segment": "SEG_CLBLM_R_X5Y72", - "sites": { - "SLICE_X6Y72": "SLICEM", - "SLICE_X7Y72": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y73": { - "grid_x": 17, - "grid_y": 132, - "segment": "SEG_CLBLM_R_X5Y73", - "sites": { - "SLICE_X6Y73": "SLICEM", - "SLICE_X7Y73": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y74": { - "grid_x": 17, - "grid_y": 131, - "segment": "SEG_CLBLM_R_X5Y74", - "sites": { - "SLICE_X6Y74": "SLICEM", - "SLICE_X7Y74": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y75": { - "grid_x": 17, - "grid_y": 129, - "segment": "SEG_CLBLM_R_X5Y75", - "sites": { - "SLICE_X6Y75": "SLICEM", - "SLICE_X7Y75": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y76": { - "grid_x": 17, - "grid_y": 128, - "segment": "SEG_CLBLM_R_X5Y76", - "sites": { - "SLICE_X6Y76": "SLICEM", - "SLICE_X7Y76": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y77": { - "grid_x": 17, - "grid_y": 127, - "segment": "SEG_CLBLM_R_X5Y77", - "sites": { - "SLICE_X6Y77": "SLICEM", - "SLICE_X7Y77": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y78": { - "grid_x": 17, - "grid_y": 126, - "segment": "SEG_CLBLM_R_X5Y78", - "sites": { - "SLICE_X6Y78": "SLICEM", - "SLICE_X7Y78": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y79": { - "grid_x": 17, - "grid_y": 125, - "segment": "SEG_CLBLM_R_X5Y79", - "sites": { - "SLICE_X6Y79": "SLICEM", - "SLICE_X7Y79": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y80": { - "grid_x": 17, - "grid_y": 124, - "segment": "SEG_CLBLM_R_X5Y80", - "sites": { - "SLICE_X6Y80": "SLICEM", - "SLICE_X7Y80": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y81": { - "grid_x": 17, - "grid_y": 123, - "segment": "SEG_CLBLM_R_X5Y81", - "sites": { - "SLICE_X6Y81": "SLICEM", - "SLICE_X7Y81": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y82": { - "grid_x": 17, - "grid_y": 122, - "segment": "SEG_CLBLM_R_X5Y82", - "sites": { - "SLICE_X6Y82": "SLICEM", - "SLICE_X7Y82": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y83": { - "grid_x": 17, - "grid_y": 121, - "segment": "SEG_CLBLM_R_X5Y83", - "sites": { - "SLICE_X6Y83": "SLICEM", - "SLICE_X7Y83": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y84": { - "grid_x": 17, - "grid_y": 120, - "segment": "SEG_CLBLM_R_X5Y84", - "sites": { - "SLICE_X6Y84": "SLICEM", - "SLICE_X7Y84": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y85": { - "grid_x": 17, - "grid_y": 119, - "segment": "SEG_CLBLM_R_X5Y85", - "sites": { - "SLICE_X6Y85": "SLICEM", - "SLICE_X7Y85": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y86": { - "grid_x": 17, - "grid_y": 118, - "segment": "SEG_CLBLM_R_X5Y86", - "sites": { - "SLICE_X6Y86": "SLICEM", - "SLICE_X7Y86": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y87": { - "grid_x": 17, - "grid_y": 117, - "segment": "SEG_CLBLM_R_X5Y87", - "sites": { - "SLICE_X6Y87": "SLICEM", - "SLICE_X7Y87": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y88": { - "grid_x": 17, - "grid_y": 116, - "segment": "SEG_CLBLM_R_X5Y88", - "sites": { - "SLICE_X6Y88": "SLICEM", - "SLICE_X7Y88": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y89": { - "grid_x": 17, - "grid_y": 115, - "segment": "SEG_CLBLM_R_X5Y89", - "sites": { - "SLICE_X6Y89": "SLICEM", - "SLICE_X7Y89": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y90": { - "grid_x": 17, - "grid_y": 114, - "segment": "SEG_CLBLM_R_X5Y90", - "sites": { - "SLICE_X6Y90": "SLICEM", - "SLICE_X7Y90": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y91": { - "grid_x": 17, - "grid_y": 113, - "segment": "SEG_CLBLM_R_X5Y91", - "sites": { - "SLICE_X6Y91": "SLICEM", - "SLICE_X7Y91": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y92": { - "grid_x": 17, - "grid_y": 112, - "segment": "SEG_CLBLM_R_X5Y92", - "sites": { - "SLICE_X6Y92": "SLICEM", - "SLICE_X7Y92": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y93": { - "grid_x": 17, - "grid_y": 111, - "segment": "SEG_CLBLM_R_X5Y93", - "sites": { - "SLICE_X6Y93": "SLICEM", - "SLICE_X7Y93": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y94": { - "grid_x": 17, - "grid_y": 110, - "segment": "SEG_CLBLM_R_X5Y94", - "sites": { - "SLICE_X6Y94": "SLICEM", - "SLICE_X7Y94": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y95": { - "grid_x": 17, - "grid_y": 109, - "segment": "SEG_CLBLM_R_X5Y95", - "sites": { - "SLICE_X6Y95": "SLICEM", - "SLICE_X7Y95": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y96": { - "grid_x": 17, - "grid_y": 108, - "segment": "SEG_CLBLM_R_X5Y96", - "sites": { - "SLICE_X6Y96": "SLICEM", - "SLICE_X7Y96": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y97": { - "grid_x": 17, - "grid_y": 107, - "segment": "SEG_CLBLM_R_X5Y97", - "sites": { - "SLICE_X6Y97": "SLICEM", - "SLICE_X7Y97": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y98": { - "grid_x": 17, - "grid_y": 106, - "segment": "SEG_CLBLM_R_X5Y98", - "sites": { - "SLICE_X6Y98": "SLICEM", - "SLICE_X7Y98": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X5Y99": { - "grid_x": 17, - "grid_y": 105, - "segment": "SEG_CLBLM_R_X5Y99", - "sites": { - "SLICE_X6Y99": "SLICEM", - "SLICE_X7Y99": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y50": { - "grid_x": 23, - "grid_y": 155, - "segment": "SEG_CLBLM_R_X7Y50", - "sites": { - "SLICE_X8Y50": "SLICEM", - "SLICE_X9Y50": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y51": { - "grid_x": 23, - "grid_y": 154, - "segment": "SEG_CLBLM_R_X7Y51", - "sites": { - "SLICE_X8Y51": "SLICEM", - "SLICE_X9Y51": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y52": { - "grid_x": 23, - "grid_y": 153, - "segment": "SEG_CLBLM_R_X7Y52", - "sites": { - "SLICE_X8Y52": "SLICEM", - "SLICE_X9Y52": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y53": { - "grid_x": 23, - "grid_y": 152, - "segment": "SEG_CLBLM_R_X7Y53", - "sites": { - "SLICE_X8Y53": "SLICEM", - "SLICE_X9Y53": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y54": { - "grid_x": 23, - "grid_y": 151, - "segment": "SEG_CLBLM_R_X7Y54", - "sites": { - "SLICE_X8Y54": "SLICEM", - "SLICE_X9Y54": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y55": { - "grid_x": 23, - "grid_y": 150, - "segment": "SEG_CLBLM_R_X7Y55", - "sites": { - "SLICE_X8Y55": "SLICEM", - "SLICE_X9Y55": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y56": { - "grid_x": 23, - "grid_y": 149, - "segment": "SEG_CLBLM_R_X7Y56", - "sites": { - "SLICE_X8Y56": "SLICEM", - "SLICE_X9Y56": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y57": { - "grid_x": 23, - "grid_y": 148, - "segment": "SEG_CLBLM_R_X7Y57", - "sites": { - "SLICE_X8Y57": "SLICEM", - "SLICE_X9Y57": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y58": { - "grid_x": 23, - "grid_y": 147, - "segment": "SEG_CLBLM_R_X7Y58", - "sites": { - "SLICE_X8Y58": "SLICEM", - "SLICE_X9Y58": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y59": { - "grid_x": 23, - "grid_y": 146, - "segment": "SEG_CLBLM_R_X7Y59", - "sites": { - "SLICE_X8Y59": "SLICEM", - "SLICE_X9Y59": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y60": { - "grid_x": 23, - "grid_y": 145, - "segment": "SEG_CLBLM_R_X7Y60", - "sites": { - "SLICE_X8Y60": "SLICEM", - "SLICE_X9Y60": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y61": { - "grid_x": 23, - "grid_y": 144, - "segment": "SEG_CLBLM_R_X7Y61", - "sites": { - "SLICE_X8Y61": "SLICEM", - "SLICE_X9Y61": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y62": { - "grid_x": 23, - "grid_y": 143, - "segment": "SEG_CLBLM_R_X7Y62", - "sites": { - "SLICE_X8Y62": "SLICEM", - "SLICE_X9Y62": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y63": { - "grid_x": 23, - "grid_y": 142, - "segment": "SEG_CLBLM_R_X7Y63", - "sites": { - "SLICE_X8Y63": "SLICEM", - "SLICE_X9Y63": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y64": { - "grid_x": 23, - "grid_y": 141, - "segment": "SEG_CLBLM_R_X7Y64", - "sites": { - "SLICE_X8Y64": "SLICEM", - "SLICE_X9Y64": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y65": { - "grid_x": 23, - "grid_y": 140, - "segment": "SEG_CLBLM_R_X7Y65", - "sites": { - "SLICE_X8Y65": "SLICEM", - "SLICE_X9Y65": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y66": { - "grid_x": 23, - "grid_y": 139, - "segment": "SEG_CLBLM_R_X7Y66", - "sites": { - "SLICE_X8Y66": "SLICEM", - "SLICE_X9Y66": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y67": { - "grid_x": 23, - "grid_y": 138, - "segment": "SEG_CLBLM_R_X7Y67", - "sites": { - "SLICE_X8Y67": "SLICEM", - "SLICE_X9Y67": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y68": { - "grid_x": 23, - "grid_y": 137, - "segment": "SEG_CLBLM_R_X7Y68", - "sites": { - "SLICE_X8Y68": "SLICEM", - "SLICE_X9Y68": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y69": { - "grid_x": 23, - "grid_y": 136, - "segment": "SEG_CLBLM_R_X7Y69", - "sites": { - "SLICE_X8Y69": "SLICEM", - "SLICE_X9Y69": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y70": { - "grid_x": 23, - "grid_y": 135, - "segment": "SEG_CLBLM_R_X7Y70", - "sites": { - "SLICE_X8Y70": "SLICEM", - "SLICE_X9Y70": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y71": { - "grid_x": 23, - "grid_y": 134, - "segment": "SEG_CLBLM_R_X7Y71", - "sites": { - "SLICE_X8Y71": "SLICEM", - "SLICE_X9Y71": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y72": { - "grid_x": 23, - "grid_y": 133, - "segment": "SEG_CLBLM_R_X7Y72", - "sites": { - "SLICE_X8Y72": "SLICEM", - "SLICE_X9Y72": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y73": { - "grid_x": 23, - "grid_y": 132, - "segment": "SEG_CLBLM_R_X7Y73", - "sites": { - "SLICE_X8Y73": "SLICEM", - "SLICE_X9Y73": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y74": { - "grid_x": 23, - "grid_y": 131, - "segment": "SEG_CLBLM_R_X7Y74", - "sites": { - "SLICE_X8Y74": "SLICEM", - "SLICE_X9Y74": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y75": { - "grid_x": 23, - "grid_y": 129, - "segment": "SEG_CLBLM_R_X7Y75", - "sites": { - "SLICE_X8Y75": "SLICEM", - "SLICE_X9Y75": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y76": { - "grid_x": 23, - "grid_y": 128, - "segment": "SEG_CLBLM_R_X7Y76", - "sites": { - "SLICE_X8Y76": "SLICEM", - "SLICE_X9Y76": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y77": { - "grid_x": 23, - "grid_y": 127, - "segment": "SEG_CLBLM_R_X7Y77", - "sites": { - "SLICE_X8Y77": "SLICEM", - "SLICE_X9Y77": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y78": { - "grid_x": 23, - "grid_y": 126, - "segment": "SEG_CLBLM_R_X7Y78", - "sites": { - "SLICE_X8Y78": "SLICEM", - "SLICE_X9Y78": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y79": { - "grid_x": 23, - "grid_y": 125, - "segment": "SEG_CLBLM_R_X7Y79", - "sites": { - "SLICE_X8Y79": "SLICEM", - "SLICE_X9Y79": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y80": { - "grid_x": 23, - "grid_y": 124, - "segment": "SEG_CLBLM_R_X7Y80", - "sites": { - "SLICE_X8Y80": "SLICEM", - "SLICE_X9Y80": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y81": { - "grid_x": 23, - "grid_y": 123, - "segment": "SEG_CLBLM_R_X7Y81", - "sites": { - "SLICE_X8Y81": "SLICEM", - "SLICE_X9Y81": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y82": { - "grid_x": 23, - "grid_y": 122, - "segment": "SEG_CLBLM_R_X7Y82", - "sites": { - "SLICE_X8Y82": "SLICEM", - "SLICE_X9Y82": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y83": { - "grid_x": 23, - "grid_y": 121, - "segment": "SEG_CLBLM_R_X7Y83", - "sites": { - "SLICE_X8Y83": "SLICEM", - "SLICE_X9Y83": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y84": { - "grid_x": 23, - "grid_y": 120, - "segment": "SEG_CLBLM_R_X7Y84", - "sites": { - "SLICE_X8Y84": "SLICEM", - "SLICE_X9Y84": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y85": { - "grid_x": 23, - "grid_y": 119, - "segment": "SEG_CLBLM_R_X7Y85", - "sites": { - "SLICE_X8Y85": "SLICEM", - "SLICE_X9Y85": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y86": { - "grid_x": 23, - "grid_y": 118, - "segment": "SEG_CLBLM_R_X7Y86", - "sites": { - "SLICE_X8Y86": "SLICEM", - "SLICE_X9Y86": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y87": { - "grid_x": 23, - "grid_y": 117, - "segment": "SEG_CLBLM_R_X7Y87", - "sites": { - "SLICE_X8Y87": "SLICEM", - "SLICE_X9Y87": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y88": { - "grid_x": 23, - "grid_y": 116, - "segment": "SEG_CLBLM_R_X7Y88", - "sites": { - "SLICE_X8Y88": "SLICEM", - "SLICE_X9Y88": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y89": { - "grid_x": 23, - "grid_y": 115, - "segment": "SEG_CLBLM_R_X7Y89", - "sites": { - "SLICE_X8Y89": "SLICEM", - "SLICE_X9Y89": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y90": { - "grid_x": 23, - "grid_y": 114, - "segment": "SEG_CLBLM_R_X7Y90", - "sites": { - "SLICE_X8Y90": "SLICEM", - "SLICE_X9Y90": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y91": { - "grid_x": 23, - "grid_y": 113, - "segment": "SEG_CLBLM_R_X7Y91", - "sites": { - "SLICE_X8Y91": "SLICEM", - "SLICE_X9Y91": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y92": { - "grid_x": 23, - "grid_y": 112, - "segment": "SEG_CLBLM_R_X7Y92", - "sites": { - "SLICE_X8Y92": "SLICEM", - "SLICE_X9Y92": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y93": { - "grid_x": 23, - "grid_y": 111, - "segment": "SEG_CLBLM_R_X7Y93", - "sites": { - "SLICE_X8Y93": "SLICEM", - "SLICE_X9Y93": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y94": { - "grid_x": 23, - "grid_y": 110, - "segment": "SEG_CLBLM_R_X7Y94", - "sites": { - "SLICE_X8Y94": "SLICEM", - "SLICE_X9Y94": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y95": { - "grid_x": 23, - "grid_y": 109, - "segment": "SEG_CLBLM_R_X7Y95", - "sites": { - "SLICE_X8Y95": "SLICEM", - "SLICE_X9Y95": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y96": { - "grid_x": 23, - "grid_y": 108, - "segment": "SEG_CLBLM_R_X7Y96", - "sites": { - "SLICE_X8Y96": "SLICEM", - "SLICE_X9Y96": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y97": { - "grid_x": 23, - "grid_y": 107, - "segment": "SEG_CLBLM_R_X7Y97", - "sites": { - "SLICE_X8Y97": "SLICEM", - "SLICE_X9Y97": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y98": { - "grid_x": 23, - "grid_y": 106, - "segment": "SEG_CLBLM_R_X7Y98", - "sites": { - "SLICE_X8Y98": "SLICEM", - "SLICE_X9Y98": "SLICEL" - }, - "type": "CLBLM_R" - }, - "CLBLM_R_X7Y99": { - "grid_x": 23, - "grid_y": 105, - "segment": "SEG_CLBLM_R_X7Y99", - "sites": { - "SLICE_X8Y99": "SLICEM", - "SLICE_X9Y99": "SLICEL" - }, - "type": "CLBLM_R" - }, - "DSP_R_X9Y50": { - "grid_x": 28, - "grid_y": 155, - "segment": "SEG_DSP0_R_X9Y50", - "sites": { - "DSP48_X0Y20": "DSP48E1", - "DSP48_X0Y21": "DSP48E1", - "TIEOFF_X10Y50": "TIEOFF" - }, - "type": "DSP_R" - }, - "DSP_R_X9Y55": { - "grid_x": 28, - "grid_y": 150, - "segment": "SEG_DSP0_R_X9Y55", - "sites": { - "DSP48_X0Y22": "DSP48E1", - "DSP48_X0Y23": "DSP48E1", - "TIEOFF_X10Y55": "TIEOFF" - }, - "type": "DSP_R" - }, - "DSP_R_X9Y60": { - "grid_x": 28, - "grid_y": 145, - "segment": "SEG_DSP0_R_X9Y60", - "sites": { - "DSP48_X0Y24": "DSP48E1", - "DSP48_X0Y25": "DSP48E1", - "TIEOFF_X10Y60": "TIEOFF" - }, - "type": "DSP_R" - }, - "DSP_R_X9Y65": { - "grid_x": 28, - "grid_y": 140, - "segment": "SEG_DSP0_R_X9Y65", - "sites": { - "DSP48_X0Y26": "DSP48E1", - "DSP48_X0Y27": "DSP48E1", - "TIEOFF_X10Y65": "TIEOFF" - }, - "type": "DSP_R" - }, - "DSP_R_X9Y70": { - "grid_x": 28, - "grid_y": 135, - "segment": "SEG_DSP0_R_X9Y70", - "sites": { - "DSP48_X0Y28": "DSP48E1", - "DSP48_X0Y29": "DSP48E1", - "TIEOFF_X10Y70": "TIEOFF" - }, - "type": "DSP_R" - }, - "DSP_R_X9Y75": { - "grid_x": 28, - "grid_y": 129, - "segment": "SEG_DSP0_R_X9Y75", - "sites": { - "DSP48_X0Y30": "DSP48E1", - "DSP48_X0Y31": "DSP48E1", - "TIEOFF_X10Y75": "TIEOFF" - }, - "type": "DSP_R" - }, - "DSP_R_X9Y80": { - "grid_x": 28, - "grid_y": 124, - "segment": "SEG_DSP0_R_X9Y80", - "sites": { - "DSP48_X0Y32": "DSP48E1", - "DSP48_X0Y33": "DSP48E1", - "TIEOFF_X10Y80": "TIEOFF" - }, - "type": "DSP_R" - }, - "DSP_R_X9Y85": { - "grid_x": 28, - "grid_y": 119, - "segment": "SEG_DSP0_R_X9Y85", - "sites": { - "DSP48_X0Y34": "DSP48E1", - "DSP48_X0Y35": "DSP48E1", - "TIEOFF_X10Y85": "TIEOFF" - }, - "type": "DSP_R" - }, - "DSP_R_X9Y90": { - "grid_x": 28, - "grid_y": 114, - "segment": "SEG_DSP0_R_X9Y90", - "sites": { - "DSP48_X0Y36": "DSP48E1", - "DSP48_X0Y37": "DSP48E1", - "TIEOFF_X10Y90": "TIEOFF" - }, - "type": "DSP_R" - }, - "DSP_R_X9Y95": { - "grid_x": 28, - "grid_y": 109, - "segment": "SEG_DSP0_R_X9Y95", - "sites": { - "DSP48_X0Y38": "DSP48E1", - "DSP48_X0Y39": "DSP48E1", - "TIEOFF_X10Y95": "TIEOFF" - }, - "type": "DSP_R" - }, - "HCLK_BRAM_X19Y78": { - "grid_x": 19, - "grid_y": 130, - "sites": {}, - "type": "HCLK_BRAM" - }, - "HCLK_CLB_X10Y78": { - "grid_x": 10, - "grid_y": 130, - "sites": {}, - "type": "HCLK_CLB" - }, - "HCLK_CLB_X13Y78": { - "grid_x": 13, - "grid_y": 130, - "sites": {}, - "type": "HCLK_CLB" - }, - "HCLK_CLB_X14Y78": { - "grid_x": 14, - "grid_y": 130, - "sites": {}, - "type": "HCLK_CLB" - }, - "HCLK_CLB_X17Y78": { - "grid_x": 17, - "grid_y": 130, - "sites": {}, - "type": "HCLK_CLB" - }, - "HCLK_CLB_X23Y78": { - "grid_x": 23, - "grid_y": 130, - "sites": {}, - "type": "HCLK_CLB" - }, - "HCLK_CLB_X24Y78": { - "grid_x": 24, - "grid_y": 130, - "sites": {}, - "type": "HCLK_CLB" - }, - "HCLK_CLB_X30Y78": { - "grid_x": 30, - "grid_y": 130, - "sites": {}, - "type": "HCLK_CLB" - }, - "HCLK_CLB_X33Y78": { - "grid_x": 33, - "grid_y": 130, - "sites": {}, - "type": "HCLK_CLB" - }, - "HCLK_CLB_X34Y78": { - "grid_x": 34, - "grid_y": 130, - "sites": {}, - "type": "HCLK_CLB" - }, - "HCLK_CLB_X37Y78": { - "grid_x": 37, - "grid_y": 130, - "sites": {}, - "type": "HCLK_CLB" - }, - "HCLK_DSP_R_X28Y78": { - "grid_x": 28, - "grid_y": 130, - "sites": {}, - "type": "HCLK_DSP_R" - }, - "HCLK_INT_INTERFACE_X20Y78": { - "grid_x": 20, - "grid_y": 130, - "sites": {}, - "type": "HCLK_INT_INTERFACE" - }, - "HCLK_INT_INTERFACE_X27Y78": { - "grid_x": 27, - "grid_y": 130, - "sites": {}, - "type": "HCLK_INT_INTERFACE" - }, - "HCLK_L_X11Y78": { - "grid_x": 11, - "grid_y": 130, - "segment": "SEG_HCLK_L_X11Y78", - "sites": {}, - "type": "HCLK_L" - }, - "HCLK_L_X15Y78": { - "grid_x": 15, - "grid_y": 130, - "segment": "SEG_HCLK_L_X15Y78", - "sites": {}, - "type": "HCLK_L" - }, - "HCLK_L_X21Y78": { - "grid_x": 21, - "grid_y": 130, - "segment": "SEG_HCLK_L_X21Y78", - "sites": {}, - "type": "HCLK_L" - }, - "HCLK_L_X25Y78": { - "grid_x": 25, - "grid_y": 130, - "segment": "SEG_HCLK_L_X25Y78", - "sites": {}, - "type": "HCLK_L" - }, - "HCLK_L_X31Y78": { - "grid_x": 31, - "grid_y": 130, - "segment": "SEG_HCLK_L_X31Y78", - "sites": {}, - "type": "HCLK_L" - }, - "HCLK_L_X35Y78": { - "grid_x": 35, - "grid_y": 130, - "segment": "SEG_HCLK_L_X35Y78", - "sites": {}, - "type": "HCLK_L" - }, - "HCLK_R_X12Y78": { - "grid_x": 12, - "grid_y": 130, - "segment": "SEG_HCLK_R_X12Y78", - "sites": {}, - "type": "HCLK_R" - }, - "HCLK_R_X16Y78": { - "grid_x": 16, - "grid_y": 130, - "segment": "SEG_HCLK_R_X16Y78", - "sites": {}, - "type": "HCLK_R" - }, - "HCLK_R_X22Y78": { - "grid_x": 22, - "grid_y": 130, - "segment": "SEG_HCLK_R_X22Y78", - "sites": {}, - "type": "HCLK_R" - }, - "HCLK_R_X26Y78": { - "grid_x": 26, - "grid_y": 130, - "segment": "SEG_HCLK_R_X26Y78", - "sites": {}, - "type": "HCLK_R" - }, - "HCLK_R_X32Y78": { - "grid_x": 32, - "grid_y": 130, - "segment": "SEG_HCLK_R_X32Y78", - "sites": {}, - "type": "HCLK_R" - }, - "HCLK_R_X36Y78": { - "grid_x": 36, - "grid_y": 130, - "segment": "SEG_HCLK_R_X36Y78", - "sites": {}, - "type": "HCLK_R" - }, - "HCLK_VBRK_X18Y78": { - "grid_x": 18, - "grid_y": 130, - "sites": {}, - "type": "HCLK_VBRK" - }, - "HCLK_VBRK_X29Y78": { - "grid_x": 29, - "grid_y": 130, - "sites": {}, - "type": "HCLK_VBRK" - }, - "HCLK_VBRK_X38Y78": { - "grid_x": 38, - "grid_y": 130, - "sites": {}, - "type": "HCLK_VBRK" - }, - "HCLK_VBRK_X9Y78": { - "grid_x": 9, - "grid_y": 130, - "sites": {}, - "type": "HCLK_VBRK" - }, - "INT_INTERFACE_R_X9Y50": { - "grid_x": 27, - "grid_y": 155, - "segment": "SEG_DSP0_R_X9Y50", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y51": { - "grid_x": 27, - "grid_y": 154, - "segment": "SEG_DSP1_R_X9Y50", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y52": { - "grid_x": 27, - "grid_y": 153, - "segment": "SEG_DSP2_R_X9Y50", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y53": { - "grid_x": 27, - "grid_y": 152, - "segment": "SEG_DSP3_R_X9Y50", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y54": { - "grid_x": 27, - "grid_y": 151, - "segment": "SEG_DSP4_R_X9Y50", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y55": { - "grid_x": 27, - "grid_y": 150, - "segment": "SEG_DSP0_R_X9Y55", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y56": { - "grid_x": 27, - "grid_y": 149, - "segment": "SEG_DSP1_R_X9Y55", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y57": { - "grid_x": 27, - "grid_y": 148, - "segment": "SEG_DSP2_R_X9Y55", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y58": { - "grid_x": 27, - "grid_y": 147, - "segment": "SEG_DSP3_R_X9Y55", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y59": { - "grid_x": 27, - "grid_y": 146, - "segment": "SEG_DSP4_R_X9Y55", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y60": { - "grid_x": 27, - "grid_y": 145, - "segment": "SEG_DSP0_R_X9Y60", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y61": { - "grid_x": 27, - "grid_y": 144, - "segment": "SEG_DSP1_R_X9Y60", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y62": { - "grid_x": 27, - "grid_y": 143, - "segment": "SEG_DSP2_R_X9Y60", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y63": { - "grid_x": 27, - "grid_y": 142, - "segment": "SEG_DSP3_R_X9Y60", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y64": { - "grid_x": 27, - "grid_y": 141, - "segment": "SEG_DSP4_R_X9Y60", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y65": { - "grid_x": 27, - "grid_y": 140, - "segment": "SEG_DSP0_R_X9Y65", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y66": { - "grid_x": 27, - "grid_y": 139, - "segment": "SEG_DSP1_R_X9Y65", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y67": { - "grid_x": 27, - "grid_y": 138, - "segment": "SEG_DSP2_R_X9Y65", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y68": { - "grid_x": 27, - "grid_y": 137, - "segment": "SEG_DSP3_R_X9Y65", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y69": { - "grid_x": 27, - "grid_y": 136, - "segment": "SEG_DSP4_R_X9Y65", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y70": { - "grid_x": 27, - "grid_y": 135, - "segment": "SEG_DSP0_R_X9Y70", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y71": { - "grid_x": 27, - "grid_y": 134, - "segment": "SEG_DSP1_R_X9Y70", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y72": { - "grid_x": 27, - "grid_y": 133, - "segment": "SEG_DSP2_R_X9Y70", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y73": { - "grid_x": 27, - "grid_y": 132, - "segment": "SEG_DSP3_R_X9Y70", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y74": { - "grid_x": 27, - "grid_y": 131, - "segment": "SEG_DSP4_R_X9Y70", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y75": { - "grid_x": 27, - "grid_y": 129, - "segment": "SEG_DSP0_R_X9Y75", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y76": { - "grid_x": 27, - "grid_y": 128, - "segment": "SEG_DSP1_R_X9Y75", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y77": { - "grid_x": 27, - "grid_y": 127, - "segment": "SEG_DSP2_R_X9Y75", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y78": { - "grid_x": 27, - "grid_y": 126, - "segment": "SEG_DSP3_R_X9Y75", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y79": { - "grid_x": 27, - "grid_y": 125, - "segment": "SEG_DSP4_R_X9Y75", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y80": { - "grid_x": 27, - "grid_y": 124, - "segment": "SEG_DSP0_R_X9Y80", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y81": { - "grid_x": 27, - "grid_y": 123, - "segment": "SEG_DSP1_R_X9Y80", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y82": { - "grid_x": 27, - "grid_y": 122, - "segment": "SEG_DSP2_R_X9Y80", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y83": { - "grid_x": 27, - "grid_y": 121, - "segment": "SEG_DSP3_R_X9Y80", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y84": { - "grid_x": 27, - "grid_y": 120, - "segment": "SEG_DSP4_R_X9Y80", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y85": { - "grid_x": 27, - "grid_y": 119, - "segment": "SEG_DSP0_R_X9Y85", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y86": { - "grid_x": 27, - "grid_y": 118, - "segment": "SEG_DSP1_R_X9Y85", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y87": { - "grid_x": 27, - "grid_y": 117, - "segment": "SEG_DSP2_R_X9Y85", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y88": { - "grid_x": 27, - "grid_y": 116, - "segment": "SEG_DSP3_R_X9Y85", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y89": { - "grid_x": 27, - "grid_y": 115, - "segment": "SEG_DSP4_R_X9Y85", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y90": { - "grid_x": 27, - "grid_y": 114, - "segment": "SEG_DSP0_R_X9Y90", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y91": { - "grid_x": 27, - "grid_y": 113, - "segment": "SEG_DSP1_R_X9Y90", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y92": { - "grid_x": 27, - "grid_y": 112, - "segment": "SEG_DSP2_R_X9Y90", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y93": { - "grid_x": 27, - "grid_y": 111, - "segment": "SEG_DSP3_R_X9Y90", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y94": { - "grid_x": 27, - "grid_y": 110, - "segment": "SEG_DSP4_R_X9Y90", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y95": { - "grid_x": 27, - "grid_y": 109, - "segment": "SEG_DSP0_R_X9Y95", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y96": { - "grid_x": 27, - "grid_y": 108, - "segment": "SEG_DSP1_R_X9Y95", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y97": { - "grid_x": 27, - "grid_y": 107, - "segment": "SEG_DSP2_R_X9Y95", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y98": { - "grid_x": 27, - "grid_y": 106, - "segment": "SEG_DSP3_R_X9Y95", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_INTERFACE_R_X9Y99": { - "grid_x": 27, - "grid_y": 105, - "segment": "SEG_DSP4_R_X9Y95", - "sites": {}, - "type": "INT_INTERFACE_R" - }, - "INT_L_X10Y50": { - "grid_x": 31, - "grid_y": 155, - "segment": "SEG_CLBLM_L_X10Y50", - "sites": { - "TIEOFF_X11Y50": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y51": { - "grid_x": 31, - "grid_y": 154, - "segment": "SEG_CLBLM_L_X10Y51", - "sites": { - "TIEOFF_X11Y51": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y52": { - "grid_x": 31, - "grid_y": 153, - "segment": "SEG_CLBLM_L_X10Y52", - "sites": { - "TIEOFF_X11Y52": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y53": { - "grid_x": 31, - "grid_y": 152, - "segment": "SEG_CLBLM_L_X10Y53", - "sites": { - "TIEOFF_X11Y53": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y54": { - "grid_x": 31, - "grid_y": 151, - "segment": "SEG_CLBLM_L_X10Y54", - "sites": { - "TIEOFF_X11Y54": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y55": { - "grid_x": 31, - "grid_y": 150, - "segment": "SEG_CLBLM_L_X10Y55", - "sites": { - "TIEOFF_X11Y55": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y56": { - "grid_x": 31, - "grid_y": 149, - "segment": "SEG_CLBLM_L_X10Y56", - "sites": { - "TIEOFF_X11Y56": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y57": { - "grid_x": 31, - "grid_y": 148, - "segment": "SEG_CLBLM_L_X10Y57", - "sites": { - "TIEOFF_X11Y57": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y58": { - "grid_x": 31, - "grid_y": 147, - "segment": "SEG_CLBLM_L_X10Y58", - "sites": { - "TIEOFF_X11Y58": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y59": { - "grid_x": 31, - "grid_y": 146, - "segment": "SEG_CLBLM_L_X10Y59", - "sites": { - "TIEOFF_X11Y59": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y60": { - "grid_x": 31, - "grid_y": 145, - "segment": "SEG_CLBLM_L_X10Y60", - "sites": { - "TIEOFF_X11Y60": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y61": { - "grid_x": 31, - "grid_y": 144, - "segment": "SEG_CLBLM_L_X10Y61", - "sites": { - "TIEOFF_X11Y61": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y62": { - "grid_x": 31, - "grid_y": 143, - "segment": "SEG_CLBLM_L_X10Y62", - "sites": { - "TIEOFF_X11Y62": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y63": { - "grid_x": 31, - "grid_y": 142, - "segment": "SEG_CLBLM_L_X10Y63", - "sites": { - "TIEOFF_X11Y63": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y64": { - "grid_x": 31, - "grid_y": 141, - "segment": "SEG_CLBLM_L_X10Y64", - "sites": { - "TIEOFF_X11Y64": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y65": { - "grid_x": 31, - "grid_y": 140, - "segment": "SEG_CLBLM_L_X10Y65", - "sites": { - "TIEOFF_X11Y65": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y66": { - "grid_x": 31, - "grid_y": 139, - "segment": "SEG_CLBLM_L_X10Y66", - "sites": { - "TIEOFF_X11Y66": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y67": { - "grid_x": 31, - "grid_y": 138, - "segment": "SEG_CLBLM_L_X10Y67", - "sites": { - "TIEOFF_X11Y67": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y68": { - "grid_x": 31, - "grid_y": 137, - "segment": "SEG_CLBLM_L_X10Y68", - "sites": { - "TIEOFF_X11Y68": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y69": { - "grid_x": 31, - "grid_y": 136, - "segment": "SEG_CLBLM_L_X10Y69", - "sites": { - "TIEOFF_X11Y69": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y70": { - "grid_x": 31, - "grid_y": 135, - "segment": "SEG_CLBLM_L_X10Y70", - "sites": { - "TIEOFF_X11Y70": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y71": { - "grid_x": 31, - "grid_y": 134, - "segment": "SEG_CLBLM_L_X10Y71", - "sites": { - "TIEOFF_X11Y71": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y72": { - "grid_x": 31, - "grid_y": 133, - "segment": "SEG_CLBLM_L_X10Y72", - "sites": { - "TIEOFF_X11Y72": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y73": { - "grid_x": 31, - "grid_y": 132, - "segment": "SEG_CLBLM_L_X10Y73", - "sites": { - "TIEOFF_X11Y73": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y74": { - "grid_x": 31, - "grid_y": 131, - "segment": "SEG_CLBLM_L_X10Y74", - "sites": { - "TIEOFF_X11Y74": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y75": { - "grid_x": 31, - "grid_y": 129, - "segment": "SEG_CLBLM_L_X10Y75", - "sites": { - "TIEOFF_X11Y75": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y76": { - "grid_x": 31, - "grid_y": 128, - "segment": "SEG_CLBLM_L_X10Y76", - "sites": { - "TIEOFF_X11Y76": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y77": { - "grid_x": 31, - "grid_y": 127, - "segment": "SEG_CLBLM_L_X10Y77", - "sites": { - "TIEOFF_X11Y77": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y78": { - "grid_x": 31, - "grid_y": 126, - "segment": "SEG_CLBLM_L_X10Y78", - "sites": { - "TIEOFF_X11Y78": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y79": { - "grid_x": 31, - "grid_y": 125, - "segment": "SEG_CLBLM_L_X10Y79", - "sites": { - "TIEOFF_X11Y79": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y80": { - "grid_x": 31, - "grid_y": 124, - "segment": "SEG_CLBLM_L_X10Y80", - "sites": { - "TIEOFF_X11Y80": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y81": { - "grid_x": 31, - "grid_y": 123, - "segment": "SEG_CLBLM_L_X10Y81", - "sites": { - "TIEOFF_X11Y81": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y82": { - "grid_x": 31, - "grid_y": 122, - "segment": "SEG_CLBLM_L_X10Y82", - "sites": { - "TIEOFF_X11Y82": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y83": { - "grid_x": 31, - "grid_y": 121, - "segment": "SEG_CLBLM_L_X10Y83", - "sites": { - "TIEOFF_X11Y83": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y84": { - "grid_x": 31, - "grid_y": 120, - "segment": "SEG_CLBLM_L_X10Y84", - "sites": { - "TIEOFF_X11Y84": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y85": { - "grid_x": 31, - "grid_y": 119, - "segment": "SEG_CLBLM_L_X10Y85", - "sites": { - "TIEOFF_X11Y85": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y86": { - "grid_x": 31, - "grid_y": 118, - "segment": "SEG_CLBLM_L_X10Y86", - "sites": { - "TIEOFF_X11Y86": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y87": { - "grid_x": 31, - "grid_y": 117, - "segment": "SEG_CLBLM_L_X10Y87", - "sites": { - "TIEOFF_X11Y87": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y88": { - "grid_x": 31, - "grid_y": 116, - "segment": "SEG_CLBLM_L_X10Y88", - "sites": { - "TIEOFF_X11Y88": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y89": { - "grid_x": 31, - "grid_y": 115, - "segment": "SEG_CLBLM_L_X10Y89", - "sites": { - "TIEOFF_X11Y89": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y90": { - "grid_x": 31, - "grid_y": 114, - "segment": "SEG_CLBLM_L_X10Y90", - "sites": { - "TIEOFF_X11Y90": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y91": { - "grid_x": 31, - "grid_y": 113, - "segment": "SEG_CLBLM_L_X10Y91", - "sites": { - "TIEOFF_X11Y91": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y92": { - "grid_x": 31, - "grid_y": 112, - "segment": "SEG_CLBLM_L_X10Y92", - "sites": { - "TIEOFF_X11Y92": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y93": { - "grid_x": 31, - "grid_y": 111, - "segment": "SEG_CLBLM_L_X10Y93", - "sites": { - "TIEOFF_X11Y93": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y94": { - "grid_x": 31, - "grid_y": 110, - "segment": "SEG_CLBLM_L_X10Y94", - "sites": { - "TIEOFF_X11Y94": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y95": { - "grid_x": 31, - "grid_y": 109, - "segment": "SEG_CLBLM_L_X10Y95", - "sites": { - "TIEOFF_X11Y95": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y96": { - "grid_x": 31, - "grid_y": 108, - "segment": "SEG_CLBLM_L_X10Y96", - "sites": { - "TIEOFF_X11Y96": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y97": { - "grid_x": 31, - "grid_y": 107, - "segment": "SEG_CLBLM_L_X10Y97", - "sites": { - "TIEOFF_X11Y97": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y98": { - "grid_x": 31, - "grid_y": 106, - "segment": "SEG_CLBLM_L_X10Y98", - "sites": { - "TIEOFF_X11Y98": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X10Y99": { - "grid_x": 31, - "grid_y": 105, - "segment": "SEG_CLBLM_L_X10Y99", - "sites": { - "TIEOFF_X11Y99": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y50": { - "grid_x": 35, - "grid_y": 155, - "segment": "SEG_CLBLM_L_X12Y50", - "sites": { - "TIEOFF_X13Y50": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y51": { - "grid_x": 35, - "grid_y": 154, - "segment": "SEG_CLBLM_L_X12Y51", - "sites": { - "TIEOFF_X13Y51": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y52": { - "grid_x": 35, - "grid_y": 153, - "segment": "SEG_CLBLM_L_X12Y52", - "sites": { - "TIEOFF_X13Y52": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y53": { - "grid_x": 35, - "grid_y": 152, - "segment": "SEG_CLBLM_L_X12Y53", - "sites": { - "TIEOFF_X13Y53": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y54": { - "grid_x": 35, - "grid_y": 151, - "segment": "SEG_CLBLM_L_X12Y54", - "sites": { - "TIEOFF_X13Y54": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y55": { - "grid_x": 35, - "grid_y": 150, - "segment": "SEG_CLBLM_L_X12Y55", - "sites": { - "TIEOFF_X13Y55": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y56": { - "grid_x": 35, - "grid_y": 149, - "segment": "SEG_CLBLM_L_X12Y56", - "sites": { - "TIEOFF_X13Y56": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y57": { - "grid_x": 35, - "grid_y": 148, - "segment": "SEG_CLBLM_L_X12Y57", - "sites": { - "TIEOFF_X13Y57": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y58": { - "grid_x": 35, - "grid_y": 147, - "segment": "SEG_CLBLM_L_X12Y58", - "sites": { - "TIEOFF_X13Y58": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y59": { - "grid_x": 35, - "grid_y": 146, - "segment": "SEG_CLBLM_L_X12Y59", - "sites": { - "TIEOFF_X13Y59": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y60": { - "grid_x": 35, - "grid_y": 145, - "segment": "SEG_CLBLM_L_X12Y60", - "sites": { - "TIEOFF_X13Y60": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y61": { - "grid_x": 35, - "grid_y": 144, - "segment": "SEG_CLBLM_L_X12Y61", - "sites": { - "TIEOFF_X13Y61": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y62": { - "grid_x": 35, - "grid_y": 143, - "segment": "SEG_CLBLM_L_X12Y62", - "sites": { - "TIEOFF_X13Y62": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y63": { - "grid_x": 35, - "grid_y": 142, - "segment": "SEG_CLBLM_L_X12Y63", - "sites": { - "TIEOFF_X13Y63": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y64": { - "grid_x": 35, - "grid_y": 141, - "segment": "SEG_CLBLM_L_X12Y64", - "sites": { - "TIEOFF_X13Y64": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y65": { - "grid_x": 35, - "grid_y": 140, - "segment": "SEG_CLBLM_L_X12Y65", - "sites": { - "TIEOFF_X13Y65": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y66": { - "grid_x": 35, - "grid_y": 139, - "segment": "SEG_CLBLM_L_X12Y66", - "sites": { - "TIEOFF_X13Y66": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y67": { - "grid_x": 35, - "grid_y": 138, - "segment": "SEG_CLBLM_L_X12Y67", - "sites": { - "TIEOFF_X13Y67": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y68": { - "grid_x": 35, - "grid_y": 137, - "segment": "SEG_CLBLM_L_X12Y68", - "sites": { - "TIEOFF_X13Y68": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y69": { - "grid_x": 35, - "grid_y": 136, - "segment": "SEG_CLBLM_L_X12Y69", - "sites": { - "TIEOFF_X13Y69": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y70": { - "grid_x": 35, - "grid_y": 135, - "segment": "SEG_CLBLM_L_X12Y70", - "sites": { - "TIEOFF_X13Y70": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y71": { - "grid_x": 35, - "grid_y": 134, - "segment": "SEG_CLBLM_L_X12Y71", - "sites": { - "TIEOFF_X13Y71": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y72": { - "grid_x": 35, - "grid_y": 133, - "segment": "SEG_CLBLM_L_X12Y72", - "sites": { - "TIEOFF_X13Y72": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y73": { - "grid_x": 35, - "grid_y": 132, - "segment": "SEG_CLBLM_L_X12Y73", - "sites": { - "TIEOFF_X13Y73": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y74": { - "grid_x": 35, - "grid_y": 131, - "segment": "SEG_CLBLM_L_X12Y74", - "sites": { - "TIEOFF_X13Y74": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y75": { - "grid_x": 35, - "grid_y": 129, - "segment": "SEG_CLBLM_L_X12Y75", - "sites": { - "TIEOFF_X13Y75": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y76": { - "grid_x": 35, - "grid_y": 128, - "segment": "SEG_CLBLM_L_X12Y76", - "sites": { - "TIEOFF_X13Y76": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y77": { - "grid_x": 35, - "grid_y": 127, - "segment": "SEG_CLBLM_L_X12Y77", - "sites": { - "TIEOFF_X13Y77": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y78": { - "grid_x": 35, - "grid_y": 126, - "segment": "SEG_CLBLM_L_X12Y78", - "sites": { - "TIEOFF_X13Y78": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y79": { - "grid_x": 35, - "grid_y": 125, - "segment": "SEG_CLBLM_L_X12Y79", - "sites": { - "TIEOFF_X13Y79": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y80": { - "grid_x": 35, - "grid_y": 124, - "segment": "SEG_CLBLM_L_X12Y80", - "sites": { - "TIEOFF_X13Y80": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y81": { - "grid_x": 35, - "grid_y": 123, - "segment": "SEG_CLBLM_L_X12Y81", - "sites": { - "TIEOFF_X13Y81": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y82": { - "grid_x": 35, - "grid_y": 122, - "segment": "SEG_CLBLM_L_X12Y82", - "sites": { - "TIEOFF_X13Y82": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y83": { - "grid_x": 35, - "grid_y": 121, - "segment": "SEG_CLBLM_L_X12Y83", - "sites": { - "TIEOFF_X13Y83": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y84": { - "grid_x": 35, - "grid_y": 120, - "segment": "SEG_CLBLM_L_X12Y84", - "sites": { - "TIEOFF_X13Y84": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y85": { - "grid_x": 35, - "grid_y": 119, - "segment": "SEG_CLBLM_L_X12Y85", - "sites": { - "TIEOFF_X13Y85": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y86": { - "grid_x": 35, - "grid_y": 118, - "segment": "SEG_CLBLM_L_X12Y86", - "sites": { - "TIEOFF_X13Y86": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y87": { - "grid_x": 35, - "grid_y": 117, - "segment": "SEG_CLBLM_L_X12Y87", - "sites": { - "TIEOFF_X13Y87": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y88": { - "grid_x": 35, - "grid_y": 116, - "segment": "SEG_CLBLM_L_X12Y88", - "sites": { - "TIEOFF_X13Y88": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y89": { - "grid_x": 35, - "grid_y": 115, - "segment": "SEG_CLBLM_L_X12Y89", - "sites": { - "TIEOFF_X13Y89": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y90": { - "grid_x": 35, - "grid_y": 114, - "segment": "SEG_CLBLM_L_X12Y90", - "sites": { - "TIEOFF_X13Y90": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y91": { - "grid_x": 35, - "grid_y": 113, - "segment": "SEG_CLBLM_L_X12Y91", - "sites": { - "TIEOFF_X13Y91": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y92": { - "grid_x": 35, - "grid_y": 112, - "segment": "SEG_CLBLM_L_X12Y92", - "sites": { - "TIEOFF_X13Y92": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y93": { - "grid_x": 35, - "grid_y": 111, - "segment": "SEG_CLBLM_L_X12Y93", - "sites": { - "TIEOFF_X13Y93": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y94": { - "grid_x": 35, - "grid_y": 110, - "segment": "SEG_CLBLM_L_X12Y94", - "sites": { - "TIEOFF_X13Y94": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y95": { - "grid_x": 35, - "grid_y": 109, - "segment": "SEG_CLBLM_L_X12Y95", - "sites": { - "TIEOFF_X13Y95": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y96": { - "grid_x": 35, - "grid_y": 108, - "segment": "SEG_CLBLM_L_X12Y96", - "sites": { - "TIEOFF_X13Y96": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y97": { - "grid_x": 35, - "grid_y": 107, - "segment": "SEG_CLBLM_L_X12Y97", - "sites": { - "TIEOFF_X13Y97": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y98": { - "grid_x": 35, - "grid_y": 106, - "segment": "SEG_CLBLM_L_X12Y98", - "sites": { - "TIEOFF_X13Y98": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X12Y99": { - "grid_x": 35, - "grid_y": 105, - "segment": "SEG_CLBLM_L_X12Y99", - "sites": { - "TIEOFF_X13Y99": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y50": { - "grid_x": 11, - "grid_y": 155, - "segment": "SEG_CLBLL_L_X2Y50", - "sites": { - "TIEOFF_X2Y50": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y51": { - "grid_x": 11, - "grid_y": 154, - "segment": "SEG_CLBLL_L_X2Y51", - "sites": { - "TIEOFF_X2Y51": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y52": { - "grid_x": 11, - "grid_y": 153, - "segment": "SEG_CLBLL_L_X2Y52", - "sites": { - "TIEOFF_X2Y52": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y53": { - "grid_x": 11, - "grid_y": 152, - "segment": "SEG_CLBLL_L_X2Y53", - "sites": { - "TIEOFF_X2Y53": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y54": { - "grid_x": 11, - "grid_y": 151, - "segment": "SEG_CLBLL_L_X2Y54", - "sites": { - "TIEOFF_X2Y54": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y55": { - "grid_x": 11, - "grid_y": 150, - "segment": "SEG_CLBLL_L_X2Y55", - "sites": { - "TIEOFF_X2Y55": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y56": { - "grid_x": 11, - "grid_y": 149, - "segment": "SEG_CLBLL_L_X2Y56", - "sites": { - "TIEOFF_X2Y56": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y57": { - "grid_x": 11, - "grid_y": 148, - "segment": "SEG_CLBLL_L_X2Y57", - "sites": { - "TIEOFF_X2Y57": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y58": { - "grid_x": 11, - "grid_y": 147, - "segment": "SEG_CLBLL_L_X2Y58", - "sites": { - "TIEOFF_X2Y58": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y59": { - "grid_x": 11, - "grid_y": 146, - "segment": "SEG_CLBLL_L_X2Y59", - "sites": { - "TIEOFF_X2Y59": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y60": { - "grid_x": 11, - "grid_y": 145, - "segment": "SEG_CLBLL_L_X2Y60", - "sites": { - "TIEOFF_X2Y60": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y61": { - "grid_x": 11, - "grid_y": 144, - "segment": "SEG_CLBLL_L_X2Y61", - "sites": { - "TIEOFF_X2Y61": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y62": { - "grid_x": 11, - "grid_y": 143, - "segment": "SEG_CLBLL_L_X2Y62", - "sites": { - "TIEOFF_X2Y62": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y63": { - "grid_x": 11, - "grid_y": 142, - "segment": "SEG_CLBLL_L_X2Y63", - "sites": { - "TIEOFF_X2Y63": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y64": { - "grid_x": 11, - "grid_y": 141, - "segment": "SEG_CLBLL_L_X2Y64", - "sites": { - "TIEOFF_X2Y64": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y65": { - "grid_x": 11, - "grid_y": 140, - "segment": "SEG_CLBLL_L_X2Y65", - "sites": { - "TIEOFF_X2Y65": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y66": { - "grid_x": 11, - "grid_y": 139, - "segment": "SEG_CLBLL_L_X2Y66", - "sites": { - "TIEOFF_X2Y66": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y67": { - "grid_x": 11, - "grid_y": 138, - "segment": "SEG_CLBLL_L_X2Y67", - "sites": { - "TIEOFF_X2Y67": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y68": { - "grid_x": 11, - "grid_y": 137, - "segment": "SEG_CLBLL_L_X2Y68", - "sites": { - "TIEOFF_X2Y68": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y69": { - "grid_x": 11, - "grid_y": 136, - "segment": "SEG_CLBLL_L_X2Y69", - "sites": { - "TIEOFF_X2Y69": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y70": { - "grid_x": 11, - "grid_y": 135, - "segment": "SEG_CLBLL_L_X2Y70", - "sites": { - "TIEOFF_X2Y70": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y71": { - "grid_x": 11, - "grid_y": 134, - "segment": "SEG_CLBLL_L_X2Y71", - "sites": { - "TIEOFF_X2Y71": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y72": { - "grid_x": 11, - "grid_y": 133, - "segment": "SEG_CLBLL_L_X2Y72", - "sites": { - "TIEOFF_X2Y72": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y73": { - "grid_x": 11, - "grid_y": 132, - "segment": "SEG_CLBLL_L_X2Y73", - "sites": { - "TIEOFF_X2Y73": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y74": { - "grid_x": 11, - "grid_y": 131, - "segment": "SEG_CLBLL_L_X2Y74", - "sites": { - "TIEOFF_X2Y74": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y75": { - "grid_x": 11, - "grid_y": 129, - "segment": "SEG_CLBLL_L_X2Y75", - "sites": { - "TIEOFF_X2Y75": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y76": { - "grid_x": 11, - "grid_y": 128, - "segment": "SEG_CLBLL_L_X2Y76", - "sites": { - "TIEOFF_X2Y76": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y77": { - "grid_x": 11, - "grid_y": 127, - "segment": "SEG_CLBLL_L_X2Y77", - "sites": { - "TIEOFF_X2Y77": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y78": { - "grid_x": 11, - "grid_y": 126, - "segment": "SEG_CLBLL_L_X2Y78", - "sites": { - "TIEOFF_X2Y78": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y79": { - "grid_x": 11, - "grid_y": 125, - "segment": "SEG_CLBLL_L_X2Y79", - "sites": { - "TIEOFF_X2Y79": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y80": { - "grid_x": 11, - "grid_y": 124, - "segment": "SEG_CLBLL_L_X2Y80", - "sites": { - "TIEOFF_X2Y80": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y81": { - "grid_x": 11, - "grid_y": 123, - "segment": "SEG_CLBLL_L_X2Y81", - "sites": { - "TIEOFF_X2Y81": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y82": { - "grid_x": 11, - "grid_y": 122, - "segment": "SEG_CLBLL_L_X2Y82", - "sites": { - "TIEOFF_X2Y82": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y83": { - "grid_x": 11, - "grid_y": 121, - "segment": "SEG_CLBLL_L_X2Y83", - "sites": { - "TIEOFF_X2Y83": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y84": { - "grid_x": 11, - "grid_y": 120, - "segment": "SEG_CLBLL_L_X2Y84", - "sites": { - "TIEOFF_X2Y84": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y85": { - "grid_x": 11, - "grid_y": 119, - "segment": "SEG_CLBLL_L_X2Y85", - "sites": { - "TIEOFF_X2Y85": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y86": { - "grid_x": 11, - "grid_y": 118, - "segment": "SEG_CLBLL_L_X2Y86", - "sites": { - "TIEOFF_X2Y86": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y87": { - "grid_x": 11, - "grid_y": 117, - "segment": "SEG_CLBLL_L_X2Y87", - "sites": { - "TIEOFF_X2Y87": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y88": { - "grid_x": 11, - "grid_y": 116, - "segment": "SEG_CLBLL_L_X2Y88", - "sites": { - "TIEOFF_X2Y88": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y89": { - "grid_x": 11, - "grid_y": 115, - "segment": "SEG_CLBLL_L_X2Y89", - "sites": { - "TIEOFF_X2Y89": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y90": { - "grid_x": 11, - "grid_y": 114, - "segment": "SEG_CLBLL_L_X2Y90", - "sites": { - "TIEOFF_X2Y90": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y91": { - "grid_x": 11, - "grid_y": 113, - "segment": "SEG_CLBLL_L_X2Y91", - "sites": { - "TIEOFF_X2Y91": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y92": { - "grid_x": 11, - "grid_y": 112, - "segment": "SEG_CLBLL_L_X2Y92", - "sites": { - "TIEOFF_X2Y92": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y93": { - "grid_x": 11, - "grid_y": 111, - "segment": "SEG_CLBLL_L_X2Y93", - "sites": { - "TIEOFF_X2Y93": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y94": { - "grid_x": 11, - "grid_y": 110, - "segment": "SEG_CLBLL_L_X2Y94", - "sites": { - "TIEOFF_X2Y94": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y95": { - "grid_x": 11, - "grid_y": 109, - "segment": "SEG_CLBLL_L_X2Y95", - "sites": { - "TIEOFF_X2Y95": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y96": { - "grid_x": 11, - "grid_y": 108, - "segment": "SEG_CLBLL_L_X2Y96", - "sites": { - "TIEOFF_X2Y96": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y97": { - "grid_x": 11, - "grid_y": 107, - "segment": "SEG_CLBLL_L_X2Y97", - "sites": { - "TIEOFF_X2Y97": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y98": { - "grid_x": 11, - "grid_y": 106, - "segment": "SEG_CLBLL_L_X2Y98", - "sites": { - "TIEOFF_X2Y98": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X2Y99": { - "grid_x": 11, - "grid_y": 105, - "segment": "SEG_CLBLL_L_X2Y99", - "sites": { - "TIEOFF_X2Y99": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y50": { - "grid_x": 15, - "grid_y": 155, - "segment": "SEG_CLBLL_L_X4Y50", - "sites": { - "TIEOFF_X4Y50": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y51": { - "grid_x": 15, - "grid_y": 154, - "segment": "SEG_CLBLL_L_X4Y51", - "sites": { - "TIEOFF_X4Y51": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y52": { - "grid_x": 15, - "grid_y": 153, - "segment": "SEG_CLBLL_L_X4Y52", - "sites": { - "TIEOFF_X4Y52": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y53": { - "grid_x": 15, - "grid_y": 152, - "segment": "SEG_CLBLL_L_X4Y53", - "sites": { - "TIEOFF_X4Y53": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y54": { - "grid_x": 15, - "grid_y": 151, - "segment": "SEG_CLBLL_L_X4Y54", - "sites": { - "TIEOFF_X4Y54": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y55": { - "grid_x": 15, - "grid_y": 150, - "segment": "SEG_CLBLL_L_X4Y55", - "sites": { - "TIEOFF_X4Y55": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y56": { - "grid_x": 15, - "grid_y": 149, - "segment": "SEG_CLBLL_L_X4Y56", - "sites": { - "TIEOFF_X4Y56": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y57": { - "grid_x": 15, - "grid_y": 148, - "segment": "SEG_CLBLL_L_X4Y57", - "sites": { - "TIEOFF_X4Y57": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y58": { - "grid_x": 15, - "grid_y": 147, - "segment": "SEG_CLBLL_L_X4Y58", - "sites": { - "TIEOFF_X4Y58": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y59": { - "grid_x": 15, - "grid_y": 146, - "segment": "SEG_CLBLL_L_X4Y59", - "sites": { - "TIEOFF_X4Y59": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y60": { - "grid_x": 15, - "grid_y": 145, - "segment": "SEG_CLBLL_L_X4Y60", - "sites": { - "TIEOFF_X4Y60": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y61": { - "grid_x": 15, - "grid_y": 144, - "segment": "SEG_CLBLL_L_X4Y61", - "sites": { - "TIEOFF_X4Y61": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y62": { - "grid_x": 15, - "grid_y": 143, - "segment": "SEG_CLBLL_L_X4Y62", - "sites": { - "TIEOFF_X4Y62": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y63": { - "grid_x": 15, - "grid_y": 142, - "segment": "SEG_CLBLL_L_X4Y63", - "sites": { - "TIEOFF_X4Y63": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y64": { - "grid_x": 15, - "grid_y": 141, - "segment": "SEG_CLBLL_L_X4Y64", - "sites": { - "TIEOFF_X4Y64": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y65": { - "grid_x": 15, - "grid_y": 140, - "segment": "SEG_CLBLL_L_X4Y65", - "sites": { - "TIEOFF_X4Y65": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y66": { - "grid_x": 15, - "grid_y": 139, - "segment": "SEG_CLBLL_L_X4Y66", - "sites": { - "TIEOFF_X4Y66": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y67": { - "grid_x": 15, - "grid_y": 138, - "segment": "SEG_CLBLL_L_X4Y67", - "sites": { - "TIEOFF_X4Y67": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y68": { - "grid_x": 15, - "grid_y": 137, - "segment": "SEG_CLBLL_L_X4Y68", - "sites": { - "TIEOFF_X4Y68": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y69": { - "grid_x": 15, - "grid_y": 136, - "segment": "SEG_CLBLL_L_X4Y69", - "sites": { - "TIEOFF_X4Y69": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y70": { - "grid_x": 15, - "grid_y": 135, - "segment": "SEG_CLBLL_L_X4Y70", - "sites": { - "TIEOFF_X4Y70": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y71": { - "grid_x": 15, - "grid_y": 134, - "segment": "SEG_CLBLL_L_X4Y71", - "sites": { - "TIEOFF_X4Y71": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y72": { - "grid_x": 15, - "grid_y": 133, - "segment": "SEG_CLBLL_L_X4Y72", - "sites": { - "TIEOFF_X4Y72": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y73": { - "grid_x": 15, - "grid_y": 132, - "segment": "SEG_CLBLL_L_X4Y73", - "sites": { - "TIEOFF_X4Y73": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y74": { - "grid_x": 15, - "grid_y": 131, - "segment": "SEG_CLBLL_L_X4Y74", - "sites": { - "TIEOFF_X4Y74": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y75": { - "grid_x": 15, - "grid_y": 129, - "segment": "SEG_CLBLL_L_X4Y75", - "sites": { - "TIEOFF_X4Y75": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y76": { - "grid_x": 15, - "grid_y": 128, - "segment": "SEG_CLBLL_L_X4Y76", - "sites": { - "TIEOFF_X4Y76": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y77": { - "grid_x": 15, - "grid_y": 127, - "segment": "SEG_CLBLL_L_X4Y77", - "sites": { - "TIEOFF_X4Y77": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y78": { - "grid_x": 15, - "grid_y": 126, - "segment": "SEG_CLBLL_L_X4Y78", - "sites": { - "TIEOFF_X4Y78": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y79": { - "grid_x": 15, - "grid_y": 125, - "segment": "SEG_CLBLL_L_X4Y79", - "sites": { - "TIEOFF_X4Y79": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y80": { - "grid_x": 15, - "grid_y": 124, - "segment": "SEG_CLBLL_L_X4Y80", - "sites": { - "TIEOFF_X4Y80": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y81": { - "grid_x": 15, - "grid_y": 123, - "segment": "SEG_CLBLL_L_X4Y81", - "sites": { - "TIEOFF_X4Y81": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y82": { - "grid_x": 15, - "grid_y": 122, - "segment": "SEG_CLBLL_L_X4Y82", - "sites": { - "TIEOFF_X4Y82": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y83": { - "grid_x": 15, - "grid_y": 121, - "segment": "SEG_CLBLL_L_X4Y83", - "sites": { - "TIEOFF_X4Y83": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y84": { - "grid_x": 15, - "grid_y": 120, - "segment": "SEG_CLBLL_L_X4Y84", - "sites": { - "TIEOFF_X4Y84": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y85": { - "grid_x": 15, - "grid_y": 119, - "segment": "SEG_CLBLL_L_X4Y85", - "sites": { - "TIEOFF_X4Y85": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y86": { - "grid_x": 15, - "grid_y": 118, - "segment": "SEG_CLBLL_L_X4Y86", - "sites": { - "TIEOFF_X4Y86": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y87": { - "grid_x": 15, - "grid_y": 117, - "segment": "SEG_CLBLL_L_X4Y87", - "sites": { - "TIEOFF_X4Y87": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y88": { - "grid_x": 15, - "grid_y": 116, - "segment": "SEG_CLBLL_L_X4Y88", - "sites": { - "TIEOFF_X4Y88": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y89": { - "grid_x": 15, - "grid_y": 115, - "segment": "SEG_CLBLL_L_X4Y89", - "sites": { - "TIEOFF_X4Y89": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y90": { - "grid_x": 15, - "grid_y": 114, - "segment": "SEG_CLBLL_L_X4Y90", - "sites": { - "TIEOFF_X4Y90": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y91": { - "grid_x": 15, - "grid_y": 113, - "segment": "SEG_CLBLL_L_X4Y91", - "sites": { - "TIEOFF_X4Y91": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y92": { - "grid_x": 15, - "grid_y": 112, - "segment": "SEG_CLBLL_L_X4Y92", - "sites": { - "TIEOFF_X4Y92": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y93": { - "grid_x": 15, - "grid_y": 111, - "segment": "SEG_CLBLL_L_X4Y93", - "sites": { - "TIEOFF_X4Y93": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y94": { - "grid_x": 15, - "grid_y": 110, - "segment": "SEG_CLBLL_L_X4Y94", - "sites": { - "TIEOFF_X4Y94": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y95": { - "grid_x": 15, - "grid_y": 109, - "segment": "SEG_CLBLL_L_X4Y95", - "sites": { - "TIEOFF_X4Y95": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y96": { - "grid_x": 15, - "grid_y": 108, - "segment": "SEG_CLBLL_L_X4Y96", - "sites": { - "TIEOFF_X4Y96": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y97": { - "grid_x": 15, - "grid_y": 107, - "segment": "SEG_CLBLL_L_X4Y97", - "sites": { - "TIEOFF_X4Y97": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y98": { - "grid_x": 15, - "grid_y": 106, - "segment": "SEG_CLBLL_L_X4Y98", - "sites": { - "TIEOFF_X4Y98": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X4Y99": { - "grid_x": 15, - "grid_y": 105, - "segment": "SEG_CLBLL_L_X4Y99", - "sites": { - "TIEOFF_X4Y99": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y50": { - "grid_x": 21, - "grid_y": 155, - "segment": "SEG_BRAM0_L_X6Y50", - "sites": { - "TIEOFF_X6Y50": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y51": { - "grid_x": 21, - "grid_y": 154, - "segment": "SEG_BRAM1_L_X6Y50", - "sites": { - "TIEOFF_X6Y51": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y52": { - "grid_x": 21, - "grid_y": 153, - "segment": "SEG_BRAM2_L_X6Y50", - "sites": { - "TIEOFF_X6Y52": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y53": { - "grid_x": 21, - "grid_y": 152, - "segment": "SEG_BRAM3_L_X6Y50", - "sites": { - "TIEOFF_X6Y53": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y54": { - "grid_x": 21, - "grid_y": 151, - "segment": "SEG_BRAM4_L_X6Y50", - "sites": { - "TIEOFF_X6Y54": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y55": { - "grid_x": 21, - "grid_y": 150, - "segment": "SEG_BRAM0_L_X6Y55", - "sites": { - "TIEOFF_X6Y55": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y56": { - "grid_x": 21, - "grid_y": 149, - "segment": "SEG_BRAM1_L_X6Y55", - "sites": { - "TIEOFF_X6Y56": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y57": { - "grid_x": 21, - "grid_y": 148, - "segment": "SEG_BRAM2_L_X6Y55", - "sites": { - "TIEOFF_X6Y57": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y58": { - "grid_x": 21, - "grid_y": 147, - "segment": "SEG_BRAM3_L_X6Y55", - "sites": { - "TIEOFF_X6Y58": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y59": { - "grid_x": 21, - "grid_y": 146, - "segment": "SEG_BRAM4_L_X6Y55", - "sites": { - "TIEOFF_X6Y59": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y60": { - "grid_x": 21, - "grid_y": 145, - "segment": "SEG_BRAM0_L_X6Y60", - "sites": { - "TIEOFF_X6Y60": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y61": { - "grid_x": 21, - "grid_y": 144, - "segment": "SEG_BRAM1_L_X6Y60", - "sites": { - "TIEOFF_X6Y61": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y62": { - "grid_x": 21, - "grid_y": 143, - "segment": "SEG_BRAM2_L_X6Y60", - "sites": { - "TIEOFF_X6Y62": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y63": { - "grid_x": 21, - "grid_y": 142, - "segment": "SEG_BRAM3_L_X6Y60", - "sites": { - "TIEOFF_X6Y63": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y64": { - "grid_x": 21, - "grid_y": 141, - "segment": "SEG_BRAM4_L_X6Y60", - "sites": { - "TIEOFF_X6Y64": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y65": { - "grid_x": 21, - "grid_y": 140, - "segment": "SEG_BRAM0_L_X6Y65", - "sites": { - "TIEOFF_X6Y65": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y66": { - "grid_x": 21, - "grid_y": 139, - "segment": "SEG_BRAM1_L_X6Y65", - "sites": { - "TIEOFF_X6Y66": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y67": { - "grid_x": 21, - "grid_y": 138, - "segment": "SEG_BRAM2_L_X6Y65", - "sites": { - "TIEOFF_X6Y67": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y68": { - "grid_x": 21, - "grid_y": 137, - "segment": "SEG_BRAM3_L_X6Y65", - "sites": { - "TIEOFF_X6Y68": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y69": { - "grid_x": 21, - "grid_y": 136, - "segment": "SEG_BRAM4_L_X6Y65", - "sites": { - "TIEOFF_X6Y69": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y70": { - "grid_x": 21, - "grid_y": 135, - "segment": "SEG_BRAM0_L_X6Y70", - "sites": { - "TIEOFF_X6Y70": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y71": { - "grid_x": 21, - "grid_y": 134, - "segment": "SEG_BRAM1_L_X6Y70", - "sites": { - "TIEOFF_X6Y71": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y72": { - "grid_x": 21, - "grid_y": 133, - "segment": "SEG_BRAM2_L_X6Y70", - "sites": { - "TIEOFF_X6Y72": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y73": { - "grid_x": 21, - "grid_y": 132, - "segment": "SEG_BRAM3_L_X6Y70", - "sites": { - "TIEOFF_X6Y73": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y74": { - "grid_x": 21, - "grid_y": 131, - "segment": "SEG_BRAM4_L_X6Y70", - "sites": { - "TIEOFF_X6Y74": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y75": { - "grid_x": 21, - "grid_y": 129, - "segment": "SEG_BRAM0_L_X6Y75", - "sites": { - "TIEOFF_X6Y75": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y76": { - "grid_x": 21, - "grid_y": 128, - "segment": "SEG_BRAM1_L_X6Y75", - "sites": { - "TIEOFF_X6Y76": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y77": { - "grid_x": 21, - "grid_y": 127, - "segment": "SEG_BRAM2_L_X6Y75", - "sites": { - "TIEOFF_X6Y77": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y78": { - "grid_x": 21, - "grid_y": 126, - "segment": "SEG_BRAM3_L_X6Y75", - "sites": { - "TIEOFF_X6Y78": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y79": { - "grid_x": 21, - "grid_y": 125, - "segment": "SEG_BRAM4_L_X6Y75", - "sites": { - "TIEOFF_X6Y79": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y80": { - "grid_x": 21, - "grid_y": 124, - "segment": "SEG_BRAM0_L_X6Y80", - "sites": { - "TIEOFF_X6Y80": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y81": { - "grid_x": 21, - "grid_y": 123, - "segment": "SEG_BRAM1_L_X6Y80", - "sites": { - "TIEOFF_X6Y81": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y82": { - "grid_x": 21, - "grid_y": 122, - "segment": "SEG_BRAM2_L_X6Y80", - "sites": { - "TIEOFF_X6Y82": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y83": { - "grid_x": 21, - "grid_y": 121, - "segment": "SEG_BRAM3_L_X6Y80", - "sites": { - "TIEOFF_X6Y83": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y84": { - "grid_x": 21, - "grid_y": 120, - "segment": "SEG_BRAM4_L_X6Y80", - "sites": { - "TIEOFF_X6Y84": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y85": { - "grid_x": 21, - "grid_y": 119, - "segment": "SEG_BRAM0_L_X6Y85", - "sites": { - "TIEOFF_X6Y85": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y86": { - "grid_x": 21, - "grid_y": 118, - "segment": "SEG_BRAM1_L_X6Y85", - "sites": { - "TIEOFF_X6Y86": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y87": { - "grid_x": 21, - "grid_y": 117, - "segment": "SEG_BRAM2_L_X6Y85", - "sites": { - "TIEOFF_X6Y87": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y88": { - "grid_x": 21, - "grid_y": 116, - "segment": "SEG_BRAM3_L_X6Y85", - "sites": { - "TIEOFF_X6Y88": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y89": { - "grid_x": 21, - "grid_y": 115, - "segment": "SEG_BRAM4_L_X6Y85", - "sites": { - "TIEOFF_X6Y89": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y90": { - "grid_x": 21, - "grid_y": 114, - "segment": "SEG_BRAM0_L_X6Y90", - "sites": { - "TIEOFF_X6Y90": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y91": { - "grid_x": 21, - "grid_y": 113, - "segment": "SEG_BRAM1_L_X6Y90", - "sites": { - "TIEOFF_X6Y91": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y92": { - "grid_x": 21, - "grid_y": 112, - "segment": "SEG_BRAM2_L_X6Y90", - "sites": { - "TIEOFF_X6Y92": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y93": { - "grid_x": 21, - "grid_y": 111, - "segment": "SEG_BRAM3_L_X6Y90", - "sites": { - "TIEOFF_X6Y93": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y94": { - "grid_x": 21, - "grid_y": 110, - "segment": "SEG_BRAM4_L_X6Y90", - "sites": { - "TIEOFF_X6Y94": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y95": { - "grid_x": 21, - "grid_y": 109, - "segment": "SEG_BRAM0_L_X6Y95", - "sites": { - "TIEOFF_X6Y95": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y96": { - "grid_x": 21, - "grid_y": 108, - "segment": "SEG_BRAM1_L_X6Y95", - "sites": { - "TIEOFF_X6Y96": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y97": { - "grid_x": 21, - "grid_y": 107, - "segment": "SEG_BRAM2_L_X6Y95", - "sites": { - "TIEOFF_X6Y97": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y98": { - "grid_x": 21, - "grid_y": 106, - "segment": "SEG_BRAM3_L_X6Y95", - "sites": { - "TIEOFF_X6Y98": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X6Y99": { - "grid_x": 21, - "grid_y": 105, - "segment": "SEG_BRAM4_L_X6Y95", - "sites": { - "TIEOFF_X6Y99": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y50": { - "grid_x": 25, - "grid_y": 155, - "segment": "SEG_CLBLM_L_X8Y50", - "sites": { - "TIEOFF_X8Y50": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y51": { - "grid_x": 25, - "grid_y": 154, - "segment": "SEG_CLBLM_L_X8Y51", - "sites": { - "TIEOFF_X8Y51": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y52": { - "grid_x": 25, - "grid_y": 153, - "segment": "SEG_CLBLM_L_X8Y52", - "sites": { - "TIEOFF_X8Y52": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y53": { - "grid_x": 25, - "grid_y": 152, - "segment": "SEG_CLBLM_L_X8Y53", - "sites": { - "TIEOFF_X8Y53": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y54": { - "grid_x": 25, - "grid_y": 151, - "segment": "SEG_CLBLM_L_X8Y54", - "sites": { - "TIEOFF_X8Y54": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y55": { - "grid_x": 25, - "grid_y": 150, - "segment": "SEG_CLBLM_L_X8Y55", - "sites": { - "TIEOFF_X8Y55": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y56": { - "grid_x": 25, - "grid_y": 149, - "segment": "SEG_CLBLM_L_X8Y56", - "sites": { - "TIEOFF_X8Y56": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y57": { - "grid_x": 25, - "grid_y": 148, - "segment": "SEG_CLBLM_L_X8Y57", - "sites": { - "TIEOFF_X8Y57": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y58": { - "grid_x": 25, - "grid_y": 147, - "segment": "SEG_CLBLM_L_X8Y58", - "sites": { - "TIEOFF_X8Y58": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y59": { - "grid_x": 25, - "grid_y": 146, - "segment": "SEG_CLBLM_L_X8Y59", - "sites": { - "TIEOFF_X8Y59": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y60": { - "grid_x": 25, - "grid_y": 145, - "segment": "SEG_CLBLM_L_X8Y60", - "sites": { - "TIEOFF_X8Y60": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y61": { - "grid_x": 25, - "grid_y": 144, - "segment": "SEG_CLBLM_L_X8Y61", - "sites": { - "TIEOFF_X8Y61": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y62": { - "grid_x": 25, - "grid_y": 143, - "segment": "SEG_CLBLM_L_X8Y62", - "sites": { - "TIEOFF_X8Y62": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y63": { - "grid_x": 25, - "grid_y": 142, - "segment": "SEG_CLBLM_L_X8Y63", - "sites": { - "TIEOFF_X8Y63": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y64": { - "grid_x": 25, - "grid_y": 141, - "segment": "SEG_CLBLM_L_X8Y64", - "sites": { - "TIEOFF_X8Y64": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y65": { - "grid_x": 25, - "grid_y": 140, - "segment": "SEG_CLBLM_L_X8Y65", - "sites": { - "TIEOFF_X8Y65": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y66": { - "grid_x": 25, - "grid_y": 139, - "segment": "SEG_CLBLM_L_X8Y66", - "sites": { - "TIEOFF_X8Y66": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y67": { - "grid_x": 25, - "grid_y": 138, - "segment": "SEG_CLBLM_L_X8Y67", - "sites": { - "TIEOFF_X8Y67": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y68": { - "grid_x": 25, - "grid_y": 137, - "segment": "SEG_CLBLM_L_X8Y68", - "sites": { - "TIEOFF_X8Y68": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y69": { - "grid_x": 25, - "grid_y": 136, - "segment": "SEG_CLBLM_L_X8Y69", - "sites": { - "TIEOFF_X8Y69": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y70": { - "grid_x": 25, - "grid_y": 135, - "segment": "SEG_CLBLM_L_X8Y70", - "sites": { - "TIEOFF_X8Y70": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y71": { - "grid_x": 25, - "grid_y": 134, - "segment": "SEG_CLBLM_L_X8Y71", - "sites": { - "TIEOFF_X8Y71": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y72": { - "grid_x": 25, - "grid_y": 133, - "segment": "SEG_CLBLM_L_X8Y72", - "sites": { - "TIEOFF_X8Y72": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y73": { - "grid_x": 25, - "grid_y": 132, - "segment": "SEG_CLBLM_L_X8Y73", - "sites": { - "TIEOFF_X8Y73": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y74": { - "grid_x": 25, - "grid_y": 131, - "segment": "SEG_CLBLM_L_X8Y74", - "sites": { - "TIEOFF_X8Y74": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y75": { - "grid_x": 25, - "grid_y": 129, - "segment": "SEG_CLBLM_L_X8Y75", - "sites": { - "TIEOFF_X8Y75": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y76": { - "grid_x": 25, - "grid_y": 128, - "segment": "SEG_CLBLM_L_X8Y76", - "sites": { - "TIEOFF_X8Y76": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y77": { - "grid_x": 25, - "grid_y": 127, - "segment": "SEG_CLBLM_L_X8Y77", - "sites": { - "TIEOFF_X8Y77": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y78": { - "grid_x": 25, - "grid_y": 126, - "segment": "SEG_CLBLM_L_X8Y78", - "sites": { - "TIEOFF_X8Y78": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y79": { - "grid_x": 25, - "grid_y": 125, - "segment": "SEG_CLBLM_L_X8Y79", - "sites": { - "TIEOFF_X8Y79": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y80": { - "grid_x": 25, - "grid_y": 124, - "segment": "SEG_CLBLM_L_X8Y80", - "sites": { - "TIEOFF_X8Y80": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y81": { - "grid_x": 25, - "grid_y": 123, - "segment": "SEG_CLBLM_L_X8Y81", - "sites": { - "TIEOFF_X8Y81": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y82": { - "grid_x": 25, - "grid_y": 122, - "segment": "SEG_CLBLM_L_X8Y82", - "sites": { - "TIEOFF_X8Y82": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y83": { - "grid_x": 25, - "grid_y": 121, - "segment": "SEG_CLBLM_L_X8Y83", - "sites": { - "TIEOFF_X8Y83": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y84": { - "grid_x": 25, - "grid_y": 120, - "segment": "SEG_CLBLM_L_X8Y84", - "sites": { - "TIEOFF_X8Y84": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y85": { - "grid_x": 25, - "grid_y": 119, - "segment": "SEG_CLBLM_L_X8Y85", - "sites": { - "TIEOFF_X8Y85": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y86": { - "grid_x": 25, - "grid_y": 118, - "segment": "SEG_CLBLM_L_X8Y86", - "sites": { - "TIEOFF_X8Y86": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y87": { - "grid_x": 25, - "grid_y": 117, - "segment": "SEG_CLBLM_L_X8Y87", - "sites": { - "TIEOFF_X8Y87": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y88": { - "grid_x": 25, - "grid_y": 116, - "segment": "SEG_CLBLM_L_X8Y88", - "sites": { - "TIEOFF_X8Y88": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y89": { - "grid_x": 25, - "grid_y": 115, - "segment": "SEG_CLBLM_L_X8Y89", - "sites": { - "TIEOFF_X8Y89": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y90": { - "grid_x": 25, - "grid_y": 114, - "segment": "SEG_CLBLM_L_X8Y90", - "sites": { - "TIEOFF_X8Y90": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y91": { - "grid_x": 25, - "grid_y": 113, - "segment": "SEG_CLBLM_L_X8Y91", - "sites": { - "TIEOFF_X8Y91": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y92": { - "grid_x": 25, - "grid_y": 112, - "segment": "SEG_CLBLM_L_X8Y92", - "sites": { - "TIEOFF_X8Y92": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y93": { - "grid_x": 25, - "grid_y": 111, - "segment": "SEG_CLBLM_L_X8Y93", - "sites": { - "TIEOFF_X8Y93": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y94": { - "grid_x": 25, - "grid_y": 110, - "segment": "SEG_CLBLM_L_X8Y94", - "sites": { - "TIEOFF_X8Y94": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y95": { - "grid_x": 25, - "grid_y": 109, - "segment": "SEG_CLBLM_L_X8Y95", - "sites": { - "TIEOFF_X8Y95": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y96": { - "grid_x": 25, - "grid_y": 108, - "segment": "SEG_CLBLM_L_X8Y96", - "sites": { - "TIEOFF_X8Y96": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y97": { - "grid_x": 25, - "grid_y": 107, - "segment": "SEG_CLBLM_L_X8Y97", - "sites": { - "TIEOFF_X8Y97": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y98": { - "grid_x": 25, - "grid_y": 106, - "segment": "SEG_CLBLM_L_X8Y98", - "sites": { - "TIEOFF_X8Y98": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_L_X8Y99": { - "grid_x": 25, - "grid_y": 105, - "segment": "SEG_CLBLM_L_X8Y99", - "sites": { - "TIEOFF_X8Y99": "TIEOFF" - }, - "type": "INT_L" - }, - "INT_R_X11Y50": { - "grid_x": 32, - "grid_y": 155, - "segment": "SEG_CLBLM_R_X11Y50", - "sites": { - "TIEOFF_X12Y50": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y51": { - "grid_x": 32, - "grid_y": 154, - "segment": "SEG_CLBLM_R_X11Y51", - "sites": { - "TIEOFF_X12Y51": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y52": { - "grid_x": 32, - "grid_y": 153, - "segment": "SEG_CLBLM_R_X11Y52", - "sites": { - "TIEOFF_X12Y52": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y53": { - "grid_x": 32, - "grid_y": 152, - "segment": "SEG_CLBLM_R_X11Y53", - "sites": { - "TIEOFF_X12Y53": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y54": { - "grid_x": 32, - "grid_y": 151, - "segment": "SEG_CLBLM_R_X11Y54", - "sites": { - "TIEOFF_X12Y54": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y55": { - "grid_x": 32, - "grid_y": 150, - "segment": "SEG_CLBLM_R_X11Y55", - "sites": { - "TIEOFF_X12Y55": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y56": { - "grid_x": 32, - "grid_y": 149, - "segment": "SEG_CLBLM_R_X11Y56", - "sites": { - "TIEOFF_X12Y56": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y57": { - "grid_x": 32, - "grid_y": 148, - "segment": "SEG_CLBLM_R_X11Y57", - "sites": { - "TIEOFF_X12Y57": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y58": { - "grid_x": 32, - "grid_y": 147, - "segment": "SEG_CLBLM_R_X11Y58", - "sites": { - "TIEOFF_X12Y58": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y59": { - "grid_x": 32, - "grid_y": 146, - "segment": "SEG_CLBLM_R_X11Y59", - "sites": { - "TIEOFF_X12Y59": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y60": { - "grid_x": 32, - "grid_y": 145, - "segment": "SEG_CLBLM_R_X11Y60", - "sites": { - "TIEOFF_X12Y60": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y61": { - "grid_x": 32, - "grid_y": 144, - "segment": "SEG_CLBLM_R_X11Y61", - "sites": { - "TIEOFF_X12Y61": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y62": { - "grid_x": 32, - "grid_y": 143, - "segment": "SEG_CLBLM_R_X11Y62", - "sites": { - "TIEOFF_X12Y62": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y63": { - "grid_x": 32, - "grid_y": 142, - "segment": "SEG_CLBLM_R_X11Y63", - "sites": { - "TIEOFF_X12Y63": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y64": { - "grid_x": 32, - "grid_y": 141, - "segment": "SEG_CLBLM_R_X11Y64", - "sites": { - "TIEOFF_X12Y64": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y65": { - "grid_x": 32, - "grid_y": 140, - "segment": "SEG_CLBLM_R_X11Y65", - "sites": { - "TIEOFF_X12Y65": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y66": { - "grid_x": 32, - "grid_y": 139, - "segment": "SEG_CLBLM_R_X11Y66", - "sites": { - "TIEOFF_X12Y66": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y67": { - "grid_x": 32, - "grid_y": 138, - "segment": "SEG_CLBLM_R_X11Y67", - "sites": { - "TIEOFF_X12Y67": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y68": { - "grid_x": 32, - "grid_y": 137, - "segment": "SEG_CLBLM_R_X11Y68", - "sites": { - "TIEOFF_X12Y68": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y69": { - "grid_x": 32, - "grid_y": 136, - "segment": "SEG_CLBLM_R_X11Y69", - "sites": { - "TIEOFF_X12Y69": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y70": { - "grid_x": 32, - "grid_y": 135, - "segment": "SEG_CLBLM_R_X11Y70", - "sites": { - "TIEOFF_X12Y70": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y71": { - "grid_x": 32, - "grid_y": 134, - "segment": "SEG_CLBLM_R_X11Y71", - "sites": { - "TIEOFF_X12Y71": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y72": { - "grid_x": 32, - "grid_y": 133, - "segment": "SEG_CLBLM_R_X11Y72", - "sites": { - "TIEOFF_X12Y72": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y73": { - "grid_x": 32, - "grid_y": 132, - "segment": "SEG_CLBLM_R_X11Y73", - "sites": { - "TIEOFF_X12Y73": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y74": { - "grid_x": 32, - "grid_y": 131, - "segment": "SEG_CLBLM_R_X11Y74", - "sites": { - "TIEOFF_X12Y74": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y75": { - "grid_x": 32, - "grid_y": 129, - "segment": "SEG_CLBLM_R_X11Y75", - "sites": { - "TIEOFF_X12Y75": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y76": { - "grid_x": 32, - "grid_y": 128, - "segment": "SEG_CLBLM_R_X11Y76", - "sites": { - "TIEOFF_X12Y76": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y77": { - "grid_x": 32, - "grid_y": 127, - "segment": "SEG_CLBLM_R_X11Y77", - "sites": { - "TIEOFF_X12Y77": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y78": { - "grid_x": 32, - "grid_y": 126, - "segment": "SEG_CLBLM_R_X11Y78", - "sites": { - "TIEOFF_X12Y78": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y79": { - "grid_x": 32, - "grid_y": 125, - "segment": "SEG_CLBLM_R_X11Y79", - "sites": { - "TIEOFF_X12Y79": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y80": { - "grid_x": 32, - "grid_y": 124, - "segment": "SEG_CLBLM_R_X11Y80", - "sites": { - "TIEOFF_X12Y80": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y81": { - "grid_x": 32, - "grid_y": 123, - "segment": "SEG_CLBLM_R_X11Y81", - "sites": { - "TIEOFF_X12Y81": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y82": { - "grid_x": 32, - "grid_y": 122, - "segment": "SEG_CLBLM_R_X11Y82", - "sites": { - "TIEOFF_X12Y82": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y83": { - "grid_x": 32, - "grid_y": 121, - "segment": "SEG_CLBLM_R_X11Y83", - "sites": { - "TIEOFF_X12Y83": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y84": { - "grid_x": 32, - "grid_y": 120, - "segment": "SEG_CLBLM_R_X11Y84", - "sites": { - "TIEOFF_X12Y84": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y85": { - "grid_x": 32, - "grid_y": 119, - "segment": "SEG_CLBLM_R_X11Y85", - "sites": { - "TIEOFF_X12Y85": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y86": { - "grid_x": 32, - "grid_y": 118, - "segment": "SEG_CLBLM_R_X11Y86", - "sites": { - "TIEOFF_X12Y86": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y87": { - "grid_x": 32, - "grid_y": 117, - "segment": "SEG_CLBLM_R_X11Y87", - "sites": { - "TIEOFF_X12Y87": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y88": { - "grid_x": 32, - "grid_y": 116, - "segment": "SEG_CLBLM_R_X11Y88", - "sites": { - "TIEOFF_X12Y88": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y89": { - "grid_x": 32, - "grid_y": 115, - "segment": "SEG_CLBLM_R_X11Y89", - "sites": { - "TIEOFF_X12Y89": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y90": { - "grid_x": 32, - "grid_y": 114, - "segment": "SEG_CLBLM_R_X11Y90", - "sites": { - "TIEOFF_X12Y90": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y91": { - "grid_x": 32, - "grid_y": 113, - "segment": "SEG_CLBLM_R_X11Y91", - "sites": { - "TIEOFF_X12Y91": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y92": { - "grid_x": 32, - "grid_y": 112, - "segment": "SEG_CLBLM_R_X11Y92", - "sites": { - "TIEOFF_X12Y92": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y93": { - "grid_x": 32, - "grid_y": 111, - "segment": "SEG_CLBLM_R_X11Y93", - "sites": { - "TIEOFF_X12Y93": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y94": { - "grid_x": 32, - "grid_y": 110, - "segment": "SEG_CLBLM_R_X11Y94", - "sites": { - "TIEOFF_X12Y94": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y95": { - "grid_x": 32, - "grid_y": 109, - "segment": "SEG_CLBLM_R_X11Y95", - "sites": { - "TIEOFF_X12Y95": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y96": { - "grid_x": 32, - "grid_y": 108, - "segment": "SEG_CLBLM_R_X11Y96", - "sites": { - "TIEOFF_X12Y96": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y97": { - "grid_x": 32, - "grid_y": 107, - "segment": "SEG_CLBLM_R_X11Y97", - "sites": { - "TIEOFF_X12Y97": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y98": { - "grid_x": 32, - "grid_y": 106, - "segment": "SEG_CLBLM_R_X11Y98", - "sites": { - "TIEOFF_X12Y98": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X11Y99": { - "grid_x": 32, - "grid_y": 105, - "segment": "SEG_CLBLM_R_X11Y99", - "sites": { - "TIEOFF_X12Y99": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y50": { - "grid_x": 36, - "grid_y": 155, - "segment": "SEG_CLBLM_R_X13Y50", - "sites": { - "TIEOFF_X14Y50": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y51": { - "grid_x": 36, - "grid_y": 154, - "segment": "SEG_CLBLM_R_X13Y51", - "sites": { - "TIEOFF_X14Y51": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y52": { - "grid_x": 36, - "grid_y": 153, - "segment": "SEG_CLBLM_R_X13Y52", - "sites": { - "TIEOFF_X14Y52": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y53": { - "grid_x": 36, - "grid_y": 152, - "segment": "SEG_CLBLM_R_X13Y53", - "sites": { - "TIEOFF_X14Y53": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y54": { - "grid_x": 36, - "grid_y": 151, - "segment": "SEG_CLBLM_R_X13Y54", - "sites": { - "TIEOFF_X14Y54": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y55": { - "grid_x": 36, - "grid_y": 150, - "segment": "SEG_CLBLM_R_X13Y55", - "sites": { - "TIEOFF_X14Y55": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y56": { - "grid_x": 36, - "grid_y": 149, - "segment": "SEG_CLBLM_R_X13Y56", - "sites": { - "TIEOFF_X14Y56": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y57": { - "grid_x": 36, - "grid_y": 148, - "segment": "SEG_CLBLM_R_X13Y57", - "sites": { - "TIEOFF_X14Y57": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y58": { - "grid_x": 36, - "grid_y": 147, - "segment": "SEG_CLBLM_R_X13Y58", - "sites": { - "TIEOFF_X14Y58": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y59": { - "grid_x": 36, - "grid_y": 146, - "segment": "SEG_CLBLM_R_X13Y59", - "sites": { - "TIEOFF_X14Y59": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y60": { - "grid_x": 36, - "grid_y": 145, - "segment": "SEG_CLBLM_R_X13Y60", - "sites": { - "TIEOFF_X14Y60": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y61": { - "grid_x": 36, - "grid_y": 144, - "segment": "SEG_CLBLM_R_X13Y61", - "sites": { - "TIEOFF_X14Y61": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y62": { - "grid_x": 36, - "grid_y": 143, - "segment": "SEG_CLBLM_R_X13Y62", - "sites": { - "TIEOFF_X14Y62": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y63": { - "grid_x": 36, - "grid_y": 142, - "segment": "SEG_CLBLM_R_X13Y63", - "sites": { - "TIEOFF_X14Y63": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y64": { - "grid_x": 36, - "grid_y": 141, - "segment": "SEG_CLBLM_R_X13Y64", - "sites": { - "TIEOFF_X14Y64": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y65": { - "grid_x": 36, - "grid_y": 140, - "segment": "SEG_CLBLM_R_X13Y65", - "sites": { - "TIEOFF_X14Y65": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y66": { - "grid_x": 36, - "grid_y": 139, - "segment": "SEG_CLBLM_R_X13Y66", - "sites": { - "TIEOFF_X14Y66": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y67": { - "grid_x": 36, - "grid_y": 138, - "segment": "SEG_CLBLM_R_X13Y67", - "sites": { - "TIEOFF_X14Y67": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y68": { - "grid_x": 36, - "grid_y": 137, - "segment": "SEG_CLBLM_R_X13Y68", - "sites": { - "TIEOFF_X14Y68": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y69": { - "grid_x": 36, - "grid_y": 136, - "segment": "SEG_CLBLM_R_X13Y69", - "sites": { - "TIEOFF_X14Y69": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y70": { - "grid_x": 36, - "grid_y": 135, - "segment": "SEG_CLBLM_R_X13Y70", - "sites": { - "TIEOFF_X14Y70": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y71": { - "grid_x": 36, - "grid_y": 134, - "segment": "SEG_CLBLM_R_X13Y71", - "sites": { - "TIEOFF_X14Y71": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y72": { - "grid_x": 36, - "grid_y": 133, - "segment": "SEG_CLBLM_R_X13Y72", - "sites": { - "TIEOFF_X14Y72": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y73": { - "grid_x": 36, - "grid_y": 132, - "segment": "SEG_CLBLM_R_X13Y73", - "sites": { - "TIEOFF_X14Y73": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y74": { - "grid_x": 36, - "grid_y": 131, - "segment": "SEG_CLBLM_R_X13Y74", - "sites": { - "TIEOFF_X14Y74": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y75": { - "grid_x": 36, - "grid_y": 129, - "segment": "SEG_CLBLM_R_X13Y75", - "sites": { - "TIEOFF_X14Y75": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y76": { - "grid_x": 36, - "grid_y": 128, - "segment": "SEG_CLBLM_R_X13Y76", - "sites": { - "TIEOFF_X14Y76": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y77": { - "grid_x": 36, - "grid_y": 127, - "segment": "SEG_CLBLM_R_X13Y77", - "sites": { - "TIEOFF_X14Y77": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y78": { - "grid_x": 36, - "grid_y": 126, - "segment": "SEG_CLBLM_R_X13Y78", - "sites": { - "TIEOFF_X14Y78": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y79": { - "grid_x": 36, - "grid_y": 125, - "segment": "SEG_CLBLM_R_X13Y79", - "sites": { - "TIEOFF_X14Y79": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y80": { - "grid_x": 36, - "grid_y": 124, - "segment": "SEG_CLBLM_R_X13Y80", - "sites": { - "TIEOFF_X14Y80": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y81": { - "grid_x": 36, - "grid_y": 123, - "segment": "SEG_CLBLM_R_X13Y81", - "sites": { - "TIEOFF_X14Y81": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y82": { - "grid_x": 36, - "grid_y": 122, - "segment": "SEG_CLBLM_R_X13Y82", - "sites": { - "TIEOFF_X14Y82": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y83": { - "grid_x": 36, - "grid_y": 121, - "segment": "SEG_CLBLM_R_X13Y83", - "sites": { - "TIEOFF_X14Y83": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y84": { - "grid_x": 36, - "grid_y": 120, - "segment": "SEG_CLBLM_R_X13Y84", - "sites": { - "TIEOFF_X14Y84": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y85": { - "grid_x": 36, - "grid_y": 119, - "segment": "SEG_CLBLM_R_X13Y85", - "sites": { - "TIEOFF_X14Y85": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y86": { - "grid_x": 36, - "grid_y": 118, - "segment": "SEG_CLBLM_R_X13Y86", - "sites": { - "TIEOFF_X14Y86": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y87": { - "grid_x": 36, - "grid_y": 117, - "segment": "SEG_CLBLM_R_X13Y87", - "sites": { - "TIEOFF_X14Y87": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y88": { - "grid_x": 36, - "grid_y": 116, - "segment": "SEG_CLBLM_R_X13Y88", - "sites": { - "TIEOFF_X14Y88": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y89": { - "grid_x": 36, - "grid_y": 115, - "segment": "SEG_CLBLM_R_X13Y89", - "sites": { - "TIEOFF_X14Y89": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y90": { - "grid_x": 36, - "grid_y": 114, - "segment": "SEG_CLBLM_R_X13Y90", - "sites": { - "TIEOFF_X14Y90": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y91": { - "grid_x": 36, - "grid_y": 113, - "segment": "SEG_CLBLM_R_X13Y91", - "sites": { - "TIEOFF_X14Y91": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y92": { - "grid_x": 36, - "grid_y": 112, - "segment": "SEG_CLBLM_R_X13Y92", - "sites": { - "TIEOFF_X14Y92": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y93": { - "grid_x": 36, - "grid_y": 111, - "segment": "SEG_CLBLM_R_X13Y93", - "sites": { - "TIEOFF_X14Y93": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y94": { - "grid_x": 36, - "grid_y": 110, - "segment": "SEG_CLBLM_R_X13Y94", - "sites": { - "TIEOFF_X14Y94": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y95": { - "grid_x": 36, - "grid_y": 109, - "segment": "SEG_CLBLM_R_X13Y95", - "sites": { - "TIEOFF_X14Y95": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y96": { - "grid_x": 36, - "grid_y": 108, - "segment": "SEG_CLBLM_R_X13Y96", - "sites": { - "TIEOFF_X14Y96": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y97": { - "grid_x": 36, - "grid_y": 107, - "segment": "SEG_CLBLM_R_X13Y97", - "sites": { - "TIEOFF_X14Y97": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y98": { - "grid_x": 36, - "grid_y": 106, - "segment": "SEG_CLBLM_R_X13Y98", - "sites": { - "TIEOFF_X14Y98": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X13Y99": { - "grid_x": 36, - "grid_y": 105, - "segment": "SEG_CLBLM_R_X13Y99", - "sites": { - "TIEOFF_X14Y99": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y50": { - "grid_x": 12, - "grid_y": 155, - "segment": "SEG_CLBLM_R_X3Y50", - "sites": { - "TIEOFF_X3Y50": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y51": { - "grid_x": 12, - "grid_y": 154, - "segment": "SEG_CLBLM_R_X3Y51", - "sites": { - "TIEOFF_X3Y51": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y52": { - "grid_x": 12, - "grid_y": 153, - "segment": "SEG_CLBLM_R_X3Y52", - "sites": { - "TIEOFF_X3Y52": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y53": { - "grid_x": 12, - "grid_y": 152, - "segment": "SEG_CLBLM_R_X3Y53", - "sites": { - "TIEOFF_X3Y53": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y54": { - "grid_x": 12, - "grid_y": 151, - "segment": "SEG_CLBLM_R_X3Y54", - "sites": { - "TIEOFF_X3Y54": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y55": { - "grid_x": 12, - "grid_y": 150, - "segment": "SEG_CLBLM_R_X3Y55", - "sites": { - "TIEOFF_X3Y55": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y56": { - "grid_x": 12, - "grid_y": 149, - "segment": "SEG_CLBLM_R_X3Y56", - "sites": { - "TIEOFF_X3Y56": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y57": { - "grid_x": 12, - "grid_y": 148, - "segment": "SEG_CLBLM_R_X3Y57", - "sites": { - "TIEOFF_X3Y57": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y58": { - "grid_x": 12, - "grid_y": 147, - "segment": "SEG_CLBLM_R_X3Y58", - "sites": { - "TIEOFF_X3Y58": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y59": { - "grid_x": 12, - "grid_y": 146, - "segment": "SEG_CLBLM_R_X3Y59", - "sites": { - "TIEOFF_X3Y59": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y60": { - "grid_x": 12, - "grid_y": 145, - "segment": "SEG_CLBLM_R_X3Y60", - "sites": { - "TIEOFF_X3Y60": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y61": { - "grid_x": 12, - "grid_y": 144, - "segment": "SEG_CLBLM_R_X3Y61", - "sites": { - "TIEOFF_X3Y61": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y62": { - "grid_x": 12, - "grid_y": 143, - "segment": "SEG_CLBLM_R_X3Y62", - "sites": { - "TIEOFF_X3Y62": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y63": { - "grid_x": 12, - "grid_y": 142, - "segment": "SEG_CLBLM_R_X3Y63", - "sites": { - "TIEOFF_X3Y63": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y64": { - "grid_x": 12, - "grid_y": 141, - "segment": "SEG_CLBLM_R_X3Y64", - "sites": { - "TIEOFF_X3Y64": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y65": { - "grid_x": 12, - "grid_y": 140, - "segment": "SEG_CLBLM_R_X3Y65", - "sites": { - "TIEOFF_X3Y65": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y66": { - "grid_x": 12, - "grid_y": 139, - "segment": "SEG_CLBLM_R_X3Y66", - "sites": { - "TIEOFF_X3Y66": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y67": { - "grid_x": 12, - "grid_y": 138, - "segment": "SEG_CLBLM_R_X3Y67", - "sites": { - "TIEOFF_X3Y67": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y68": { - "grid_x": 12, - "grid_y": 137, - "segment": "SEG_CLBLM_R_X3Y68", - "sites": { - "TIEOFF_X3Y68": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y69": { - "grid_x": 12, - "grid_y": 136, - "segment": "SEG_CLBLM_R_X3Y69", - "sites": { - "TIEOFF_X3Y69": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y70": { - "grid_x": 12, - "grid_y": 135, - "segment": "SEG_CLBLM_R_X3Y70", - "sites": { - "TIEOFF_X3Y70": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y71": { - "grid_x": 12, - "grid_y": 134, - "segment": "SEG_CLBLM_R_X3Y71", - "sites": { - "TIEOFF_X3Y71": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y72": { - "grid_x": 12, - "grid_y": 133, - "segment": "SEG_CLBLM_R_X3Y72", - "sites": { - "TIEOFF_X3Y72": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y73": { - "grid_x": 12, - "grid_y": 132, - "segment": "SEG_CLBLM_R_X3Y73", - "sites": { - "TIEOFF_X3Y73": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y74": { - "grid_x": 12, - "grid_y": 131, - "segment": "SEG_CLBLM_R_X3Y74", - "sites": { - "TIEOFF_X3Y74": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y75": { - "grid_x": 12, - "grid_y": 129, - "segment": "SEG_CLBLM_R_X3Y75", - "sites": { - "TIEOFF_X3Y75": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y76": { - "grid_x": 12, - "grid_y": 128, - "segment": "SEG_CLBLM_R_X3Y76", - "sites": { - "TIEOFF_X3Y76": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y77": { - "grid_x": 12, - "grid_y": 127, - "segment": "SEG_CLBLM_R_X3Y77", - "sites": { - "TIEOFF_X3Y77": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y78": { - "grid_x": 12, - "grid_y": 126, - "segment": "SEG_CLBLM_R_X3Y78", - "sites": { - "TIEOFF_X3Y78": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y79": { - "grid_x": 12, - "grid_y": 125, - "segment": "SEG_CLBLM_R_X3Y79", - "sites": { - "TIEOFF_X3Y79": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y80": { - "grid_x": 12, - "grid_y": 124, - "segment": "SEG_CLBLM_R_X3Y80", - "sites": { - "TIEOFF_X3Y80": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y81": { - "grid_x": 12, - "grid_y": 123, - "segment": "SEG_CLBLM_R_X3Y81", - "sites": { - "TIEOFF_X3Y81": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y82": { - "grid_x": 12, - "grid_y": 122, - "segment": "SEG_CLBLM_R_X3Y82", - "sites": { - "TIEOFF_X3Y82": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y83": { - "grid_x": 12, - "grid_y": 121, - "segment": "SEG_CLBLM_R_X3Y83", - "sites": { - "TIEOFF_X3Y83": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y84": { - "grid_x": 12, - "grid_y": 120, - "segment": "SEG_CLBLM_R_X3Y84", - "sites": { - "TIEOFF_X3Y84": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y85": { - "grid_x": 12, - "grid_y": 119, - "segment": "SEG_CLBLM_R_X3Y85", - "sites": { - "TIEOFF_X3Y85": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y86": { - "grid_x": 12, - "grid_y": 118, - "segment": "SEG_CLBLM_R_X3Y86", - "sites": { - "TIEOFF_X3Y86": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y87": { - "grid_x": 12, - "grid_y": 117, - "segment": "SEG_CLBLM_R_X3Y87", - "sites": { - "TIEOFF_X3Y87": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y88": { - "grid_x": 12, - "grid_y": 116, - "segment": "SEG_CLBLM_R_X3Y88", - "sites": { - "TIEOFF_X3Y88": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y89": { - "grid_x": 12, - "grid_y": 115, - "segment": "SEG_CLBLM_R_X3Y89", - "sites": { - "TIEOFF_X3Y89": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y90": { - "grid_x": 12, - "grid_y": 114, - "segment": "SEG_CLBLM_R_X3Y90", - "sites": { - "TIEOFF_X3Y90": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y91": { - "grid_x": 12, - "grid_y": 113, - "segment": "SEG_CLBLM_R_X3Y91", - "sites": { - "TIEOFF_X3Y91": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y92": { - "grid_x": 12, - "grid_y": 112, - "segment": "SEG_CLBLM_R_X3Y92", - "sites": { - "TIEOFF_X3Y92": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y93": { - "grid_x": 12, - "grid_y": 111, - "segment": "SEG_CLBLM_R_X3Y93", - "sites": { - "TIEOFF_X3Y93": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y94": { - "grid_x": 12, - "grid_y": 110, - "segment": "SEG_CLBLM_R_X3Y94", - "sites": { - "TIEOFF_X3Y94": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y95": { - "grid_x": 12, - "grid_y": 109, - "segment": "SEG_CLBLM_R_X3Y95", - "sites": { - "TIEOFF_X3Y95": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y96": { - "grid_x": 12, - "grid_y": 108, - "segment": "SEG_CLBLM_R_X3Y96", - "sites": { - "TIEOFF_X3Y96": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y97": { - "grid_x": 12, - "grid_y": 107, - "segment": "SEG_CLBLM_R_X3Y97", - "sites": { - "TIEOFF_X3Y97": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y98": { - "grid_x": 12, - "grid_y": 106, - "segment": "SEG_CLBLM_R_X3Y98", - "sites": { - "TIEOFF_X3Y98": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X3Y99": { - "grid_x": 12, - "grid_y": 105, - "segment": "SEG_CLBLM_R_X3Y99", - "sites": { - "TIEOFF_X3Y99": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y50": { - "grid_x": 16, - "grid_y": 155, - "segment": "SEG_CLBLM_R_X5Y50", - "sites": { - "TIEOFF_X5Y50": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y51": { - "grid_x": 16, - "grid_y": 154, - "segment": "SEG_CLBLM_R_X5Y51", - "sites": { - "TIEOFF_X5Y51": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y52": { - "grid_x": 16, - "grid_y": 153, - "segment": "SEG_CLBLM_R_X5Y52", - "sites": { - "TIEOFF_X5Y52": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y53": { - "grid_x": 16, - "grid_y": 152, - "segment": "SEG_CLBLM_R_X5Y53", - "sites": { - "TIEOFF_X5Y53": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y54": { - "grid_x": 16, - "grid_y": 151, - "segment": "SEG_CLBLM_R_X5Y54", - "sites": { - "TIEOFF_X5Y54": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y55": { - "grid_x": 16, - "grid_y": 150, - "segment": "SEG_CLBLM_R_X5Y55", - "sites": { - "TIEOFF_X5Y55": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y56": { - "grid_x": 16, - "grid_y": 149, - "segment": "SEG_CLBLM_R_X5Y56", - "sites": { - "TIEOFF_X5Y56": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y57": { - "grid_x": 16, - "grid_y": 148, - "segment": "SEG_CLBLM_R_X5Y57", - "sites": { - "TIEOFF_X5Y57": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y58": { - "grid_x": 16, - "grid_y": 147, - "segment": "SEG_CLBLM_R_X5Y58", - "sites": { - "TIEOFF_X5Y58": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y59": { - "grid_x": 16, - "grid_y": 146, - "segment": "SEG_CLBLM_R_X5Y59", - "sites": { - "TIEOFF_X5Y59": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y60": { - "grid_x": 16, - "grid_y": 145, - "segment": "SEG_CLBLM_R_X5Y60", - "sites": { - "TIEOFF_X5Y60": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y61": { - "grid_x": 16, - "grid_y": 144, - "segment": "SEG_CLBLM_R_X5Y61", - "sites": { - "TIEOFF_X5Y61": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y62": { - "grid_x": 16, - "grid_y": 143, - "segment": "SEG_CLBLM_R_X5Y62", - "sites": { - "TIEOFF_X5Y62": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y63": { - "grid_x": 16, - "grid_y": 142, - "segment": "SEG_CLBLM_R_X5Y63", - "sites": { - "TIEOFF_X5Y63": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y64": { - "grid_x": 16, - "grid_y": 141, - "segment": "SEG_CLBLM_R_X5Y64", - "sites": { - "TIEOFF_X5Y64": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y65": { - "grid_x": 16, - "grid_y": 140, - "segment": "SEG_CLBLM_R_X5Y65", - "sites": { - "TIEOFF_X5Y65": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y66": { - "grid_x": 16, - "grid_y": 139, - "segment": "SEG_CLBLM_R_X5Y66", - "sites": { - "TIEOFF_X5Y66": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y67": { - "grid_x": 16, - "grid_y": 138, - "segment": "SEG_CLBLM_R_X5Y67", - "sites": { - "TIEOFF_X5Y67": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y68": { - "grid_x": 16, - "grid_y": 137, - "segment": "SEG_CLBLM_R_X5Y68", - "sites": { - "TIEOFF_X5Y68": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y69": { - "grid_x": 16, - "grid_y": 136, - "segment": "SEG_CLBLM_R_X5Y69", - "sites": { - "TIEOFF_X5Y69": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y70": { - "grid_x": 16, - "grid_y": 135, - "segment": "SEG_CLBLM_R_X5Y70", - "sites": { - "TIEOFF_X5Y70": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y71": { - "grid_x": 16, - "grid_y": 134, - "segment": "SEG_CLBLM_R_X5Y71", - "sites": { - "TIEOFF_X5Y71": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y72": { - "grid_x": 16, - "grid_y": 133, - "segment": "SEG_CLBLM_R_X5Y72", - "sites": { - "TIEOFF_X5Y72": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y73": { - "grid_x": 16, - "grid_y": 132, - "segment": "SEG_CLBLM_R_X5Y73", - "sites": { - "TIEOFF_X5Y73": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y74": { - "grid_x": 16, - "grid_y": 131, - "segment": "SEG_CLBLM_R_X5Y74", - "sites": { - "TIEOFF_X5Y74": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y75": { - "grid_x": 16, - "grid_y": 129, - "segment": "SEG_CLBLM_R_X5Y75", - "sites": { - "TIEOFF_X5Y75": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y76": { - "grid_x": 16, - "grid_y": 128, - "segment": "SEG_CLBLM_R_X5Y76", - "sites": { - "TIEOFF_X5Y76": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y77": { - "grid_x": 16, - "grid_y": 127, - "segment": "SEG_CLBLM_R_X5Y77", - "sites": { - "TIEOFF_X5Y77": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y78": { - "grid_x": 16, - "grid_y": 126, - "segment": "SEG_CLBLM_R_X5Y78", - "sites": { - "TIEOFF_X5Y78": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y79": { - "grid_x": 16, - "grid_y": 125, - "segment": "SEG_CLBLM_R_X5Y79", - "sites": { - "TIEOFF_X5Y79": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y80": { - "grid_x": 16, - "grid_y": 124, - "segment": "SEG_CLBLM_R_X5Y80", - "sites": { - "TIEOFF_X5Y80": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y81": { - "grid_x": 16, - "grid_y": 123, - "segment": "SEG_CLBLM_R_X5Y81", - "sites": { - "TIEOFF_X5Y81": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y82": { - "grid_x": 16, - "grid_y": 122, - "segment": "SEG_CLBLM_R_X5Y82", - "sites": { - "TIEOFF_X5Y82": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y83": { - "grid_x": 16, - "grid_y": 121, - "segment": "SEG_CLBLM_R_X5Y83", - "sites": { - "TIEOFF_X5Y83": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y84": { - "grid_x": 16, - "grid_y": 120, - "segment": "SEG_CLBLM_R_X5Y84", - "sites": { - "TIEOFF_X5Y84": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y85": { - "grid_x": 16, - "grid_y": 119, - "segment": "SEG_CLBLM_R_X5Y85", - "sites": { - "TIEOFF_X5Y85": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y86": { - "grid_x": 16, - "grid_y": 118, - "segment": "SEG_CLBLM_R_X5Y86", - "sites": { - "TIEOFF_X5Y86": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y87": { - "grid_x": 16, - "grid_y": 117, - "segment": "SEG_CLBLM_R_X5Y87", - "sites": { - "TIEOFF_X5Y87": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y88": { - "grid_x": 16, - "grid_y": 116, - "segment": "SEG_CLBLM_R_X5Y88", - "sites": { - "TIEOFF_X5Y88": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y89": { - "grid_x": 16, - "grid_y": 115, - "segment": "SEG_CLBLM_R_X5Y89", - "sites": { - "TIEOFF_X5Y89": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y90": { - "grid_x": 16, - "grid_y": 114, - "segment": "SEG_CLBLM_R_X5Y90", - "sites": { - "TIEOFF_X5Y90": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y91": { - "grid_x": 16, - "grid_y": 113, - "segment": "SEG_CLBLM_R_X5Y91", - "sites": { - "TIEOFF_X5Y91": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y92": { - "grid_x": 16, - "grid_y": 112, - "segment": "SEG_CLBLM_R_X5Y92", - "sites": { - "TIEOFF_X5Y92": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y93": { - "grid_x": 16, - "grid_y": 111, - "segment": "SEG_CLBLM_R_X5Y93", - "sites": { - "TIEOFF_X5Y93": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y94": { - "grid_x": 16, - "grid_y": 110, - "segment": "SEG_CLBLM_R_X5Y94", - "sites": { - "TIEOFF_X5Y94": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y95": { - "grid_x": 16, - "grid_y": 109, - "segment": "SEG_CLBLM_R_X5Y95", - "sites": { - "TIEOFF_X5Y95": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y96": { - "grid_x": 16, - "grid_y": 108, - "segment": "SEG_CLBLM_R_X5Y96", - "sites": { - "TIEOFF_X5Y96": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y97": { - "grid_x": 16, - "grid_y": 107, - "segment": "SEG_CLBLM_R_X5Y97", - "sites": { - "TIEOFF_X5Y97": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y98": { - "grid_x": 16, - "grid_y": 106, - "segment": "SEG_CLBLM_R_X5Y98", - "sites": { - "TIEOFF_X5Y98": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X5Y99": { - "grid_x": 16, - "grid_y": 105, - "segment": "SEG_CLBLM_R_X5Y99", - "sites": { - "TIEOFF_X5Y99": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y50": { - "grid_x": 22, - "grid_y": 155, - "segment": "SEG_CLBLM_R_X7Y50", - "sites": { - "TIEOFF_X7Y50": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y51": { - "grid_x": 22, - "grid_y": 154, - "segment": "SEG_CLBLM_R_X7Y51", - "sites": { - "TIEOFF_X7Y51": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y52": { - "grid_x": 22, - "grid_y": 153, - "segment": "SEG_CLBLM_R_X7Y52", - "sites": { - "TIEOFF_X7Y52": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y53": { - "grid_x": 22, - "grid_y": 152, - "segment": "SEG_CLBLM_R_X7Y53", - "sites": { - "TIEOFF_X7Y53": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y54": { - "grid_x": 22, - "grid_y": 151, - "segment": "SEG_CLBLM_R_X7Y54", - "sites": { - "TIEOFF_X7Y54": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y55": { - "grid_x": 22, - "grid_y": 150, - "segment": "SEG_CLBLM_R_X7Y55", - "sites": { - "TIEOFF_X7Y55": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y56": { - "grid_x": 22, - "grid_y": 149, - "segment": "SEG_CLBLM_R_X7Y56", - "sites": { - "TIEOFF_X7Y56": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y57": { - "grid_x": 22, - "grid_y": 148, - "segment": "SEG_CLBLM_R_X7Y57", - "sites": { - "TIEOFF_X7Y57": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y58": { - "grid_x": 22, - "grid_y": 147, - "segment": "SEG_CLBLM_R_X7Y58", - "sites": { - "TIEOFF_X7Y58": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y59": { - "grid_x": 22, - "grid_y": 146, - "segment": "SEG_CLBLM_R_X7Y59", - "sites": { - "TIEOFF_X7Y59": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y60": { - "grid_x": 22, - "grid_y": 145, - "segment": "SEG_CLBLM_R_X7Y60", - "sites": { - "TIEOFF_X7Y60": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y61": { - "grid_x": 22, - "grid_y": 144, - "segment": "SEG_CLBLM_R_X7Y61", - "sites": { - "TIEOFF_X7Y61": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y62": { - "grid_x": 22, - "grid_y": 143, - "segment": "SEG_CLBLM_R_X7Y62", - "sites": { - "TIEOFF_X7Y62": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y63": { - "grid_x": 22, - "grid_y": 142, - "segment": "SEG_CLBLM_R_X7Y63", - "sites": { - "TIEOFF_X7Y63": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y64": { - "grid_x": 22, - "grid_y": 141, - "segment": "SEG_CLBLM_R_X7Y64", - "sites": { - "TIEOFF_X7Y64": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y65": { - "grid_x": 22, - "grid_y": 140, - "segment": "SEG_CLBLM_R_X7Y65", - "sites": { - "TIEOFF_X7Y65": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y66": { - "grid_x": 22, - "grid_y": 139, - "segment": "SEG_CLBLM_R_X7Y66", - "sites": { - "TIEOFF_X7Y66": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y67": { - "grid_x": 22, - "grid_y": 138, - "segment": "SEG_CLBLM_R_X7Y67", - "sites": { - "TIEOFF_X7Y67": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y68": { - "grid_x": 22, - "grid_y": 137, - "segment": "SEG_CLBLM_R_X7Y68", - "sites": { - "TIEOFF_X7Y68": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y69": { - "grid_x": 22, - "grid_y": 136, - "segment": "SEG_CLBLM_R_X7Y69", - "sites": { - "TIEOFF_X7Y69": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y70": { - "grid_x": 22, - "grid_y": 135, - "segment": "SEG_CLBLM_R_X7Y70", - "sites": { - "TIEOFF_X7Y70": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y71": { - "grid_x": 22, - "grid_y": 134, - "segment": "SEG_CLBLM_R_X7Y71", - "sites": { - "TIEOFF_X7Y71": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y72": { - "grid_x": 22, - "grid_y": 133, - "segment": "SEG_CLBLM_R_X7Y72", - "sites": { - "TIEOFF_X7Y72": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y73": { - "grid_x": 22, - "grid_y": 132, - "segment": "SEG_CLBLM_R_X7Y73", - "sites": { - "TIEOFF_X7Y73": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y74": { - "grid_x": 22, - "grid_y": 131, - "segment": "SEG_CLBLM_R_X7Y74", - "sites": { - "TIEOFF_X7Y74": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y75": { - "grid_x": 22, - "grid_y": 129, - "segment": "SEG_CLBLM_R_X7Y75", - "sites": { - "TIEOFF_X7Y75": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y76": { - "grid_x": 22, - "grid_y": 128, - "segment": "SEG_CLBLM_R_X7Y76", - "sites": { - "TIEOFF_X7Y76": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y77": { - "grid_x": 22, - "grid_y": 127, - "segment": "SEG_CLBLM_R_X7Y77", - "sites": { - "TIEOFF_X7Y77": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y78": { - "grid_x": 22, - "grid_y": 126, - "segment": "SEG_CLBLM_R_X7Y78", - "sites": { - "TIEOFF_X7Y78": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y79": { - "grid_x": 22, - "grid_y": 125, - "segment": "SEG_CLBLM_R_X7Y79", - "sites": { - "TIEOFF_X7Y79": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y80": { - "grid_x": 22, - "grid_y": 124, - "segment": "SEG_CLBLM_R_X7Y80", - "sites": { - "TIEOFF_X7Y80": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y81": { - "grid_x": 22, - "grid_y": 123, - "segment": "SEG_CLBLM_R_X7Y81", - "sites": { - "TIEOFF_X7Y81": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y82": { - "grid_x": 22, - "grid_y": 122, - "segment": "SEG_CLBLM_R_X7Y82", - "sites": { - "TIEOFF_X7Y82": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y83": { - "grid_x": 22, - "grid_y": 121, - "segment": "SEG_CLBLM_R_X7Y83", - "sites": { - "TIEOFF_X7Y83": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y84": { - "grid_x": 22, - "grid_y": 120, - "segment": "SEG_CLBLM_R_X7Y84", - "sites": { - "TIEOFF_X7Y84": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y85": { - "grid_x": 22, - "grid_y": 119, - "segment": "SEG_CLBLM_R_X7Y85", - "sites": { - "TIEOFF_X7Y85": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y86": { - "grid_x": 22, - "grid_y": 118, - "segment": "SEG_CLBLM_R_X7Y86", - "sites": { - "TIEOFF_X7Y86": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y87": { - "grid_x": 22, - "grid_y": 117, - "segment": "SEG_CLBLM_R_X7Y87", - "sites": { - "TIEOFF_X7Y87": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y88": { - "grid_x": 22, - "grid_y": 116, - "segment": "SEG_CLBLM_R_X7Y88", - "sites": { - "TIEOFF_X7Y88": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y89": { - "grid_x": 22, - "grid_y": 115, - "segment": "SEG_CLBLM_R_X7Y89", - "sites": { - "TIEOFF_X7Y89": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y90": { - "grid_x": 22, - "grid_y": 114, - "segment": "SEG_CLBLM_R_X7Y90", - "sites": { - "TIEOFF_X7Y90": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y91": { - "grid_x": 22, - "grid_y": 113, - "segment": "SEG_CLBLM_R_X7Y91", - "sites": { - "TIEOFF_X7Y91": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y92": { - "grid_x": 22, - "grid_y": 112, - "segment": "SEG_CLBLM_R_X7Y92", - "sites": { - "TIEOFF_X7Y92": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y93": { - "grid_x": 22, - "grid_y": 111, - "segment": "SEG_CLBLM_R_X7Y93", - "sites": { - "TIEOFF_X7Y93": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y94": { - "grid_x": 22, - "grid_y": 110, - "segment": "SEG_CLBLM_R_X7Y94", - "sites": { - "TIEOFF_X7Y94": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y95": { - "grid_x": 22, - "grid_y": 109, - "segment": "SEG_CLBLM_R_X7Y95", - "sites": { - "TIEOFF_X7Y95": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y96": { - "grid_x": 22, - "grid_y": 108, - "segment": "SEG_CLBLM_R_X7Y96", - "sites": { - "TIEOFF_X7Y96": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y97": { - "grid_x": 22, - "grid_y": 107, - "segment": "SEG_CLBLM_R_X7Y97", - "sites": { - "TIEOFF_X7Y97": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y98": { - "grid_x": 22, - "grid_y": 106, - "segment": "SEG_CLBLM_R_X7Y98", - "sites": { - "TIEOFF_X7Y98": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X7Y99": { - "grid_x": 22, - "grid_y": 105, - "segment": "SEG_CLBLM_R_X7Y99", - "sites": { - "TIEOFF_X7Y99": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y50": { - "grid_x": 26, - "grid_y": 155, - "segment": "SEG_DSP0_R_X9Y50", - "sites": { - "TIEOFF_X9Y50": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y51": { - "grid_x": 26, - "grid_y": 154, - "segment": "SEG_DSP1_R_X9Y50", - "sites": { - "TIEOFF_X9Y51": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y52": { - "grid_x": 26, - "grid_y": 153, - "segment": "SEG_DSP2_R_X9Y50", - "sites": { - "TIEOFF_X9Y52": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y53": { - "grid_x": 26, - "grid_y": 152, - "segment": "SEG_DSP3_R_X9Y50", - "sites": { - "TIEOFF_X9Y53": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y54": { - "grid_x": 26, - "grid_y": 151, - "segment": "SEG_DSP4_R_X9Y50", - "sites": { - "TIEOFF_X9Y54": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y55": { - "grid_x": 26, - "grid_y": 150, - "segment": "SEG_DSP0_R_X9Y55", - "sites": { - "TIEOFF_X9Y55": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y56": { - "grid_x": 26, - "grid_y": 149, - "segment": "SEG_DSP1_R_X9Y55", - "sites": { - "TIEOFF_X9Y56": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y57": { - "grid_x": 26, - "grid_y": 148, - "segment": "SEG_DSP2_R_X9Y55", - "sites": { - "TIEOFF_X9Y57": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y58": { - "grid_x": 26, - "grid_y": 147, - "segment": "SEG_DSP3_R_X9Y55", - "sites": { - "TIEOFF_X9Y58": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y59": { - "grid_x": 26, - "grid_y": 146, - "segment": "SEG_DSP4_R_X9Y55", - "sites": { - "TIEOFF_X9Y59": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y60": { - "grid_x": 26, - "grid_y": 145, - "segment": "SEG_DSP0_R_X9Y60", - "sites": { - "TIEOFF_X9Y60": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y61": { - "grid_x": 26, - "grid_y": 144, - "segment": "SEG_DSP1_R_X9Y60", - "sites": { - "TIEOFF_X9Y61": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y62": { - "grid_x": 26, - "grid_y": 143, - "segment": "SEG_DSP2_R_X9Y60", - "sites": { - "TIEOFF_X9Y62": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y63": { - "grid_x": 26, - "grid_y": 142, - "segment": "SEG_DSP3_R_X9Y60", - "sites": { - "TIEOFF_X9Y63": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y64": { - "grid_x": 26, - "grid_y": 141, - "segment": "SEG_DSP4_R_X9Y60", - "sites": { - "TIEOFF_X9Y64": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y65": { - "grid_x": 26, - "grid_y": 140, - "segment": "SEG_DSP0_R_X9Y65", - "sites": { - "TIEOFF_X9Y65": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y66": { - "grid_x": 26, - "grid_y": 139, - "segment": "SEG_DSP1_R_X9Y65", - "sites": { - "TIEOFF_X9Y66": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y67": { - "grid_x": 26, - "grid_y": 138, - "segment": "SEG_DSP2_R_X9Y65", - "sites": { - "TIEOFF_X9Y67": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y68": { - "grid_x": 26, - "grid_y": 137, - "segment": "SEG_DSP3_R_X9Y65", - "sites": { - "TIEOFF_X9Y68": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y69": { - "grid_x": 26, - "grid_y": 136, - "segment": "SEG_DSP4_R_X9Y65", - "sites": { - "TIEOFF_X9Y69": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y70": { - "grid_x": 26, - "grid_y": 135, - "segment": "SEG_DSP0_R_X9Y70", - "sites": { - "TIEOFF_X9Y70": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y71": { - "grid_x": 26, - "grid_y": 134, - "segment": "SEG_DSP1_R_X9Y70", - "sites": { - "TIEOFF_X9Y71": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y72": { - "grid_x": 26, - "grid_y": 133, - "segment": "SEG_DSP2_R_X9Y70", - "sites": { - "TIEOFF_X9Y72": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y73": { - "grid_x": 26, - "grid_y": 132, - "segment": "SEG_DSP3_R_X9Y70", - "sites": { - "TIEOFF_X9Y73": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y74": { - "grid_x": 26, - "grid_y": 131, - "segment": "SEG_DSP4_R_X9Y70", - "sites": { - "TIEOFF_X9Y74": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y75": { - "grid_x": 26, - "grid_y": 129, - "segment": "SEG_DSP0_R_X9Y75", - "sites": { - "TIEOFF_X9Y75": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y76": { - "grid_x": 26, - "grid_y": 128, - "segment": "SEG_DSP1_R_X9Y75", - "sites": { - "TIEOFF_X9Y76": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y77": { - "grid_x": 26, - "grid_y": 127, - "segment": "SEG_DSP2_R_X9Y75", - "sites": { - "TIEOFF_X9Y77": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y78": { - "grid_x": 26, - "grid_y": 126, - "segment": "SEG_DSP3_R_X9Y75", - "sites": { - "TIEOFF_X9Y78": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y79": { - "grid_x": 26, - "grid_y": 125, - "segment": "SEG_DSP4_R_X9Y75", - "sites": { - "TIEOFF_X9Y79": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y80": { - "grid_x": 26, - "grid_y": 124, - "segment": "SEG_DSP0_R_X9Y80", - "sites": { - "TIEOFF_X9Y80": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y81": { - "grid_x": 26, - "grid_y": 123, - "segment": "SEG_DSP1_R_X9Y80", - "sites": { - "TIEOFF_X9Y81": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y82": { - "grid_x": 26, - "grid_y": 122, - "segment": "SEG_DSP2_R_X9Y80", - "sites": { - "TIEOFF_X9Y82": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y83": { - "grid_x": 26, - "grid_y": 121, - "segment": "SEG_DSP3_R_X9Y80", - "sites": { - "TIEOFF_X9Y83": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y84": { - "grid_x": 26, - "grid_y": 120, - "segment": "SEG_DSP4_R_X9Y80", - "sites": { - "TIEOFF_X9Y84": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y85": { - "grid_x": 26, - "grid_y": 119, - "segment": "SEG_DSP0_R_X9Y85", - "sites": { - "TIEOFF_X9Y85": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y86": { - "grid_x": 26, - "grid_y": 118, - "segment": "SEG_DSP1_R_X9Y85", - "sites": { - "TIEOFF_X9Y86": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y87": { - "grid_x": 26, - "grid_y": 117, - "segment": "SEG_DSP2_R_X9Y85", - "sites": { - "TIEOFF_X9Y87": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y88": { - "grid_x": 26, - "grid_y": 116, - "segment": "SEG_DSP3_R_X9Y85", - "sites": { - "TIEOFF_X9Y88": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y89": { - "grid_x": 26, - "grid_y": 115, - "segment": "SEG_DSP4_R_X9Y85", - "sites": { - "TIEOFF_X9Y89": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y90": { - "grid_x": 26, - "grid_y": 114, - "segment": "SEG_DSP0_R_X9Y90", - "sites": { - "TIEOFF_X9Y90": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y91": { - "grid_x": 26, - "grid_y": 113, - "segment": "SEG_DSP1_R_X9Y90", - "sites": { - "TIEOFF_X9Y91": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y92": { - "grid_x": 26, - "grid_y": 112, - "segment": "SEG_DSP2_R_X9Y90", - "sites": { - "TIEOFF_X9Y92": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y93": { - "grid_x": 26, - "grid_y": 111, - "segment": "SEG_DSP3_R_X9Y90", - "sites": { - "TIEOFF_X9Y93": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y94": { - "grid_x": 26, - "grid_y": 110, - "segment": "SEG_DSP4_R_X9Y90", - "sites": { - "TIEOFF_X9Y94": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y95": { - "grid_x": 26, - "grid_y": 109, - "segment": "SEG_DSP0_R_X9Y95", - "sites": { - "TIEOFF_X9Y95": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y96": { - "grid_x": 26, - "grid_y": 108, - "segment": "SEG_DSP1_R_X9Y95", - "sites": { - "TIEOFF_X9Y96": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y97": { - "grid_x": 26, - "grid_y": 107, - "segment": "SEG_DSP2_R_X9Y95", - "sites": { - "TIEOFF_X9Y97": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y98": { - "grid_x": 26, - "grid_y": 106, - "segment": "SEG_DSP3_R_X9Y95", - "sites": { - "TIEOFF_X9Y98": "TIEOFF" - }, - "type": "INT_R" - }, - "INT_R_X9Y99": { - "grid_x": 26, - "grid_y": 105, - "segment": "SEG_DSP4_R_X9Y95", - "sites": { - "TIEOFF_X9Y99": "TIEOFF" - }, - "type": "INT_R" - }, - "NULL_X18Y104": { - "grid_x": 18, - "grid_y": 104, - "sites": {}, - "type": "NULL" - }, - "NULL_X18Y52": { - "grid_x": 18, - "grid_y": 156, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y100": { - "grid_x": 19, - "grid_y": 108, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y101": { - "grid_x": 19, - "grid_y": 107, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y102": { - "grid_x": 19, - "grid_y": 106, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y103": { - "grid_x": 19, - "grid_y": 105, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y54": { - "grid_x": 19, - "grid_y": 154, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y55": { - "grid_x": 19, - "grid_y": 153, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y56": { - "grid_x": 19, - "grid_y": 152, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y57": { - "grid_x": 19, - "grid_y": 151, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y59": { - "grid_x": 19, - "grid_y": 149, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y60": { - "grid_x": 19, - "grid_y": 148, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y61": { - "grid_x": 19, - "grid_y": 147, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y62": { - "grid_x": 19, - "grid_y": 146, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y64": { - "grid_x": 19, - "grid_y": 144, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y65": { - "grid_x": 19, - "grid_y": 143, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y66": { - "grid_x": 19, - "grid_y": 142, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y67": { - "grid_x": 19, - "grid_y": 141, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y69": { - "grid_x": 19, - "grid_y": 139, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y70": { - "grid_x": 19, - "grid_y": 138, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y71": { - "grid_x": 19, - "grid_y": 137, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y72": { - "grid_x": 19, - "grid_y": 136, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y74": { - "grid_x": 19, - "grid_y": 134, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y75": { - "grid_x": 19, - "grid_y": 133, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y76": { - "grid_x": 19, - "grid_y": 132, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y77": { - "grid_x": 19, - "grid_y": 131, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y80": { - "grid_x": 19, - "grid_y": 128, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y81": { - "grid_x": 19, - "grid_y": 127, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y82": { - "grid_x": 19, - "grid_y": 126, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y83": { - "grid_x": 19, - "grid_y": 125, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y85": { - "grid_x": 19, - "grid_y": 123, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y86": { - "grid_x": 19, - "grid_y": 122, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y87": { - "grid_x": 19, - "grid_y": 121, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y88": { - "grid_x": 19, - "grid_y": 120, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y90": { - "grid_x": 19, - "grid_y": 118, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y91": { - "grid_x": 19, - "grid_y": 117, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y92": { - "grid_x": 19, - "grid_y": 116, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y93": { - "grid_x": 19, - "grid_y": 115, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y95": { - "grid_x": 19, - "grid_y": 113, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y96": { - "grid_x": 19, - "grid_y": 112, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y97": { - "grid_x": 19, - "grid_y": 111, - "sites": {}, - "type": "NULL" - }, - "NULL_X19Y98": { - "grid_x": 19, - "grid_y": 110, - "sites": {}, - "type": "NULL" - }, - "NULL_X20Y104": { - "grid_x": 20, - "grid_y": 104, - "sites": {}, - "type": "NULL" - }, - "NULL_X20Y52": { - "grid_x": 20, - "grid_y": 156, - "sites": {}, - "type": "NULL" - }, - "NULL_X27Y104": { - "grid_x": 27, - "grid_y": 104, - "sites": {}, - "type": "NULL" - }, - "NULL_X27Y52": { - "grid_x": 27, - "grid_y": 156, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y100": { - "grid_x": 28, - "grid_y": 108, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y101": { - "grid_x": 28, - "grid_y": 107, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y102": { - "grid_x": 28, - "grid_y": 106, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y103": { - "grid_x": 28, - "grid_y": 105, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y54": { - "grid_x": 28, - "grid_y": 154, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y55": { - "grid_x": 28, - "grid_y": 153, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y56": { - "grid_x": 28, - "grid_y": 152, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y57": { - "grid_x": 28, - "grid_y": 151, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y59": { - "grid_x": 28, - "grid_y": 149, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y60": { - "grid_x": 28, - "grid_y": 148, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y61": { - "grid_x": 28, - "grid_y": 147, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y62": { - "grid_x": 28, - "grid_y": 146, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y64": { - "grid_x": 28, - "grid_y": 144, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y65": { - "grid_x": 28, - "grid_y": 143, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y66": { - "grid_x": 28, - "grid_y": 142, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y67": { - "grid_x": 28, - "grid_y": 141, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y69": { - "grid_x": 28, - "grid_y": 139, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y70": { - "grid_x": 28, - "grid_y": 138, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y71": { - "grid_x": 28, - "grid_y": 137, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y72": { - "grid_x": 28, - "grid_y": 136, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y74": { - "grid_x": 28, - "grid_y": 134, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y75": { - "grid_x": 28, - "grid_y": 133, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y76": { - "grid_x": 28, - "grid_y": 132, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y77": { - "grid_x": 28, - "grid_y": 131, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y80": { - "grid_x": 28, - "grid_y": 128, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y81": { - "grid_x": 28, - "grid_y": 127, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y82": { - "grid_x": 28, - "grid_y": 126, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y83": { - "grid_x": 28, - "grid_y": 125, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y85": { - "grid_x": 28, - "grid_y": 123, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y86": { - "grid_x": 28, - "grid_y": 122, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y87": { - "grid_x": 28, - "grid_y": 121, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y88": { - "grid_x": 28, - "grid_y": 120, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y90": { - "grid_x": 28, - "grid_y": 118, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y91": { - "grid_x": 28, - "grid_y": 117, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y92": { - "grid_x": 28, - "grid_y": 116, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y93": { - "grid_x": 28, - "grid_y": 115, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y95": { - "grid_x": 28, - "grid_y": 113, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y96": { - "grid_x": 28, - "grid_y": 112, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y97": { - "grid_x": 28, - "grid_y": 111, - "sites": {}, - "type": "NULL" - }, - "NULL_X28Y98": { - "grid_x": 28, - "grid_y": 110, - "sites": {}, - "type": "NULL" - }, - "NULL_X29Y104": { - "grid_x": 29, - "grid_y": 104, - "sites": {}, - "type": "NULL" - }, - "NULL_X29Y52": { - "grid_x": 29, - "grid_y": 156, - "sites": {}, - "type": "NULL" - }, - "NULL_X38Y104": { - "grid_x": 38, - "grid_y": 104, - "sites": {}, - "type": "NULL" - }, - "NULL_X38Y52": { - "grid_x": 38, - "grid_y": 156, - "sites": {}, - "type": "NULL" - }, - "NULL_X9Y104": { - "grid_x": 9, - "grid_y": 104, - "sites": {}, - "type": "NULL" - }, - "NULL_X9Y52": { - "grid_x": 9, - "grid_y": 156, - "sites": {}, - "type": "NULL" - }, - "VBRK_X18Y100": { - "grid_x": 18, - "grid_y": 108, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y101": { - "grid_x": 18, - "grid_y": 107, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y102": { - "grid_x": 18, - "grid_y": 106, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y103": { - "grid_x": 18, - "grid_y": 105, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y53": { - "grid_x": 18, - "grid_y": 155, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y54": { - "grid_x": 18, - "grid_y": 154, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y55": { - "grid_x": 18, - "grid_y": 153, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y56": { - "grid_x": 18, - "grid_y": 152, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y57": { - "grid_x": 18, - "grid_y": 151, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y58": { - "grid_x": 18, - "grid_y": 150, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y59": { - "grid_x": 18, - "grid_y": 149, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y60": { - "grid_x": 18, - "grid_y": 148, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y61": { - "grid_x": 18, - "grid_y": 147, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y62": { - "grid_x": 18, - "grid_y": 146, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y63": { - "grid_x": 18, - "grid_y": 145, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y64": { - "grid_x": 18, - "grid_y": 144, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y65": { - "grid_x": 18, - "grid_y": 143, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y66": { - "grid_x": 18, - "grid_y": 142, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y67": { - "grid_x": 18, - "grid_y": 141, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y68": { - "grid_x": 18, - "grid_y": 140, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y69": { - "grid_x": 18, - "grid_y": 139, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y70": { - "grid_x": 18, - "grid_y": 138, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y71": { - "grid_x": 18, - "grid_y": 137, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y72": { - "grid_x": 18, - "grid_y": 136, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y73": { - "grid_x": 18, - "grid_y": 135, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y74": { - "grid_x": 18, - "grid_y": 134, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y75": { - "grid_x": 18, - "grid_y": 133, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y76": { - "grid_x": 18, - "grid_y": 132, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y77": { - "grid_x": 18, - "grid_y": 131, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y79": { - "grid_x": 18, - "grid_y": 129, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y80": { - "grid_x": 18, - "grid_y": 128, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y81": { - "grid_x": 18, - "grid_y": 127, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y82": { - "grid_x": 18, - "grid_y": 126, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y83": { - "grid_x": 18, - "grid_y": 125, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y84": { - "grid_x": 18, - "grid_y": 124, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y85": { - "grid_x": 18, - "grid_y": 123, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y86": { - "grid_x": 18, - "grid_y": 122, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y87": { - "grid_x": 18, - "grid_y": 121, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y88": { - "grid_x": 18, - "grid_y": 120, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y89": { - "grid_x": 18, - "grid_y": 119, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y90": { - "grid_x": 18, - "grid_y": 118, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y91": { - "grid_x": 18, - "grid_y": 117, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y92": { - "grid_x": 18, - "grid_y": 116, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y93": { - "grid_x": 18, - "grid_y": 115, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y94": { - "grid_x": 18, - "grid_y": 114, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y95": { - "grid_x": 18, - "grid_y": 113, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y96": { - "grid_x": 18, - "grid_y": 112, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y97": { - "grid_x": 18, - "grid_y": 111, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y98": { - "grid_x": 18, - "grid_y": 110, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X18Y99": { - "grid_x": 18, - "grid_y": 109, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y100": { - "grid_x": 29, - "grid_y": 108, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y101": { - "grid_x": 29, - "grid_y": 107, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y102": { - "grid_x": 29, - "grid_y": 106, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y103": { - "grid_x": 29, - "grid_y": 105, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y53": { - "grid_x": 29, - "grid_y": 155, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y54": { - "grid_x": 29, - "grid_y": 154, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y55": { - "grid_x": 29, - "grid_y": 153, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y56": { - "grid_x": 29, - "grid_y": 152, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y57": { - "grid_x": 29, - "grid_y": 151, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y58": { - "grid_x": 29, - "grid_y": 150, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y59": { - "grid_x": 29, - "grid_y": 149, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y60": { - "grid_x": 29, - "grid_y": 148, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y61": { - "grid_x": 29, - "grid_y": 147, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y62": { - "grid_x": 29, - "grid_y": 146, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y63": { - "grid_x": 29, - "grid_y": 145, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y64": { - "grid_x": 29, - "grid_y": 144, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y65": { - "grid_x": 29, - "grid_y": 143, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y66": { - "grid_x": 29, - "grid_y": 142, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y67": { - "grid_x": 29, - "grid_y": 141, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y68": { - "grid_x": 29, - "grid_y": 140, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y69": { - "grid_x": 29, - "grid_y": 139, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y70": { - "grid_x": 29, - "grid_y": 138, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y71": { - "grid_x": 29, - "grid_y": 137, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y72": { - "grid_x": 29, - "grid_y": 136, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y73": { - "grid_x": 29, - "grid_y": 135, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y74": { - "grid_x": 29, - "grid_y": 134, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y75": { - "grid_x": 29, - "grid_y": 133, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y76": { - "grid_x": 29, - "grid_y": 132, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y77": { - "grid_x": 29, - "grid_y": 131, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y79": { - "grid_x": 29, - "grid_y": 129, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y80": { - "grid_x": 29, - "grid_y": 128, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y81": { - "grid_x": 29, - "grid_y": 127, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y82": { - "grid_x": 29, - "grid_y": 126, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y83": { - "grid_x": 29, - "grid_y": 125, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y84": { - "grid_x": 29, - "grid_y": 124, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y85": { - "grid_x": 29, - "grid_y": 123, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y86": { - "grid_x": 29, - "grid_y": 122, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y87": { - "grid_x": 29, - "grid_y": 121, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y88": { - "grid_x": 29, - "grid_y": 120, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y89": { - "grid_x": 29, - "grid_y": 119, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y90": { - "grid_x": 29, - "grid_y": 118, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y91": { - "grid_x": 29, - "grid_y": 117, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y92": { - "grid_x": 29, - "grid_y": 116, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y93": { - "grid_x": 29, - "grid_y": 115, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y94": { - "grid_x": 29, - "grid_y": 114, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y95": { - "grid_x": 29, - "grid_y": 113, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y96": { - "grid_x": 29, - "grid_y": 112, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y97": { - "grid_x": 29, - "grid_y": 111, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y98": { - "grid_x": 29, - "grid_y": 110, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X29Y99": { - "grid_x": 29, - "grid_y": 109, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y100": { - "grid_x": 38, - "grid_y": 108, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y101": { - "grid_x": 38, - "grid_y": 107, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y102": { - "grid_x": 38, - "grid_y": 106, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y103": { - "grid_x": 38, - "grid_y": 105, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y53": { - "grid_x": 38, - "grid_y": 155, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y54": { - "grid_x": 38, - "grid_y": 154, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y55": { - "grid_x": 38, - "grid_y": 153, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y56": { - "grid_x": 38, - "grid_y": 152, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y57": { - "grid_x": 38, - "grid_y": 151, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y58": { - "grid_x": 38, - "grid_y": 150, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y59": { - "grid_x": 38, - "grid_y": 149, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y60": { - "grid_x": 38, - "grid_y": 148, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y61": { - "grid_x": 38, - "grid_y": 147, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y62": { - "grid_x": 38, - "grid_y": 146, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y63": { - "grid_x": 38, - "grid_y": 145, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y64": { - "grid_x": 38, - "grid_y": 144, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y65": { - "grid_x": 38, - "grid_y": 143, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y66": { - "grid_x": 38, - "grid_y": 142, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y67": { - "grid_x": 38, - "grid_y": 141, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y68": { - "grid_x": 38, - "grid_y": 140, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y69": { - "grid_x": 38, - "grid_y": 139, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y70": { - "grid_x": 38, - "grid_y": 138, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y71": { - "grid_x": 38, - "grid_y": 137, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y72": { - "grid_x": 38, - "grid_y": 136, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y73": { - "grid_x": 38, - "grid_y": 135, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y74": { - "grid_x": 38, - "grid_y": 134, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y75": { - "grid_x": 38, - "grid_y": 133, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y76": { - "grid_x": 38, - "grid_y": 132, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y77": { - "grid_x": 38, - "grid_y": 131, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y79": { - "grid_x": 38, - "grid_y": 129, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y80": { - "grid_x": 38, - "grid_y": 128, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y81": { - "grid_x": 38, - "grid_y": 127, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y82": { - "grid_x": 38, - "grid_y": 126, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y83": { - "grid_x": 38, - "grid_y": 125, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y84": { - "grid_x": 38, - "grid_y": 124, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y85": { - "grid_x": 38, - "grid_y": 123, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y86": { - "grid_x": 38, - "grid_y": 122, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y87": { - "grid_x": 38, - "grid_y": 121, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y88": { - "grid_x": 38, - "grid_y": 120, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y89": { - "grid_x": 38, - "grid_y": 119, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y90": { - "grid_x": 38, - "grid_y": 118, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y91": { - "grid_x": 38, - "grid_y": 117, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y92": { - "grid_x": 38, - "grid_y": 116, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y93": { - "grid_x": 38, - "grid_y": 115, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y94": { - "grid_x": 38, - "grid_y": 114, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y95": { - "grid_x": 38, - "grid_y": 113, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y96": { - "grid_x": 38, - "grid_y": 112, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y97": { - "grid_x": 38, - "grid_y": 111, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y98": { - "grid_x": 38, - "grid_y": 110, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X38Y99": { - "grid_x": 38, - "grid_y": 109, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y100": { - "grid_x": 9, - "grid_y": 108, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y101": { - "grid_x": 9, - "grid_y": 107, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y102": { - "grid_x": 9, - "grid_y": 106, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y103": { - "grid_x": 9, - "grid_y": 105, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y53": { - "grid_x": 9, - "grid_y": 155, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y54": { - "grid_x": 9, - "grid_y": 154, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y55": { - "grid_x": 9, - "grid_y": 153, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y56": { - "grid_x": 9, - "grid_y": 152, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y57": { - "grid_x": 9, - "grid_y": 151, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y58": { - "grid_x": 9, - "grid_y": 150, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y59": { - "grid_x": 9, - "grid_y": 149, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y60": { - "grid_x": 9, - "grid_y": 148, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y61": { - "grid_x": 9, - "grid_y": 147, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y62": { - "grid_x": 9, - "grid_y": 146, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y63": { - "grid_x": 9, - "grid_y": 145, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y64": { - "grid_x": 9, - "grid_y": 144, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y65": { - "grid_x": 9, - "grid_y": 143, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y66": { - "grid_x": 9, - "grid_y": 142, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y67": { - "grid_x": 9, - "grid_y": 141, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y68": { - "grid_x": 9, - "grid_y": 140, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y69": { - "grid_x": 9, - "grid_y": 139, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y70": { - "grid_x": 9, - "grid_y": 138, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y71": { - "grid_x": 9, - "grid_y": 137, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y72": { - "grid_x": 9, - "grid_y": 136, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y73": { - "grid_x": 9, - "grid_y": 135, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y74": { - "grid_x": 9, - "grid_y": 134, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y75": { - "grid_x": 9, - "grid_y": 133, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y76": { - "grid_x": 9, - "grid_y": 132, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y77": { - "grid_x": 9, - "grid_y": 131, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y79": { - "grid_x": 9, - "grid_y": 129, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y80": { - "grid_x": 9, - "grid_y": 128, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y81": { - "grid_x": 9, - "grid_y": 127, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y82": { - "grid_x": 9, - "grid_y": 126, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y83": { - "grid_x": 9, - "grid_y": 125, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y84": { - "grid_x": 9, - "grid_y": 124, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y85": { - "grid_x": 9, - "grid_y": 123, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y86": { - "grid_x": 9, - "grid_y": 122, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y87": { - "grid_x": 9, - "grid_y": 121, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y88": { - "grid_x": 9, - "grid_y": 120, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y89": { - "grid_x": 9, - "grid_y": 119, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y90": { - "grid_x": 9, - "grid_y": 118, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y91": { - "grid_x": 9, - "grid_y": 117, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y92": { - "grid_x": 9, - "grid_y": 116, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y93": { - "grid_x": 9, - "grid_y": 115, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y94": { - "grid_x": 9, - "grid_y": 114, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y95": { - "grid_x": 9, - "grid_y": 113, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y96": { - "grid_x": 9, - "grid_y": 112, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y97": { - "grid_x": 9, - "grid_y": 111, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y98": { - "grid_x": 9, - "grid_y": 110, - "sites": {}, - "type": "VBRK" - }, - "VBRK_X9Y99": { - "grid_x": 9, - "grid_y": 109, - "sites": {}, - "type": "VBRK" - } - } -} + "BRAM_INT_INTERFACE_L_X30Y0": { + "bits": {}, + "grid_x": 78, + "grid_y": 207, + "segment": "SEG_BRAM0_L_X30Y0", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y1": { + "bits": {}, + "grid_x": 78, + "grid_y": 206, + "segment": "SEG_BRAM1_L_X30Y0", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y10": { + "bits": {}, + "grid_x": 78, + "grid_y": 197, + "segment": "SEG_BRAM0_L_X30Y10", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y11": { + "bits": {}, + "grid_x": 78, + "grid_y": 196, + "segment": "SEG_BRAM1_L_X30Y10", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y12": { + "bits": {}, + "grid_x": 78, + "grid_y": 195, + "segment": "SEG_BRAM2_L_X30Y10", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y125": { + "bits": {}, + "grid_x": 78, + "grid_y": 77, + "segment": "SEG_BRAM0_L_X30Y125", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y126": { + "bits": {}, + "grid_x": 78, + "grid_y": 76, + "segment": "SEG_BRAM1_L_X30Y125", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y127": { + "bits": {}, + "grid_x": 78, + "grid_y": 75, + "segment": "SEG_BRAM2_L_X30Y125", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y128": { + "bits": {}, + "grid_x": 78, + "grid_y": 74, + "segment": "SEG_BRAM3_L_X30Y125", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y129": { + "bits": {}, + "grid_x": 78, + "grid_y": 73, + "segment": "SEG_BRAM4_L_X30Y125", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y13": { + "bits": {}, + "grid_x": 78, + "grid_y": 194, + "segment": "SEG_BRAM3_L_X30Y10", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y130": { + "bits": {}, + "grid_x": 78, + "grid_y": 72, + "segment": "SEG_BRAM0_L_X30Y130", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y131": { + "bits": {}, + "grid_x": 78, + "grid_y": 71, + "segment": "SEG_BRAM1_L_X30Y130", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y132": { + "bits": {}, + "grid_x": 78, + "grid_y": 70, + "segment": "SEG_BRAM2_L_X30Y130", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y133": { + "bits": {}, + "grid_x": 78, + "grid_y": 69, + "segment": "SEG_BRAM3_L_X30Y130", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y134": { + "bits": {}, + "grid_x": 78, + "grid_y": 68, + "segment": "SEG_BRAM4_L_X30Y130", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y135": { + "bits": {}, + "grid_x": 78, + "grid_y": 67, + "segment": "SEG_BRAM0_L_X30Y135", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y136": { + "bits": {}, + "grid_x": 78, + "grid_y": 66, + "segment": "SEG_BRAM1_L_X30Y135", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y137": { + "bits": {}, + "grid_x": 78, + "grid_y": 65, + "segment": "SEG_BRAM2_L_X30Y135", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y138": { + "bits": {}, + "grid_x": 78, + "grid_y": 64, + "segment": "SEG_BRAM3_L_X30Y135", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y139": { + "bits": {}, + "grid_x": 78, + "grid_y": 63, + "segment": "SEG_BRAM4_L_X30Y135", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y14": { + "bits": {}, + "grid_x": 78, + "grid_y": 193, + "segment": "SEG_BRAM4_L_X30Y10", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y140": { + "bits": {}, + "grid_x": 78, + "grid_y": 62, + "segment": "SEG_BRAM0_L_X30Y140", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y141": { + "bits": {}, + "grid_x": 78, + "grid_y": 61, + "segment": "SEG_BRAM1_L_X30Y140", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y142": { + "bits": {}, + "grid_x": 78, + "grid_y": 60, + "segment": "SEG_BRAM2_L_X30Y140", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y143": { + "bits": {}, + "grid_x": 78, + "grid_y": 59, + "segment": "SEG_BRAM3_L_X30Y140", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y144": { + "bits": {}, + "grid_x": 78, + "grid_y": 58, + "segment": "SEG_BRAM4_L_X30Y140", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y145": { + "bits": {}, + "grid_x": 78, + "grid_y": 57, + "segment": "SEG_BRAM0_L_X30Y145", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y146": { + "bits": {}, + "grid_x": 78, + "grid_y": 56, + "segment": "SEG_BRAM1_L_X30Y145", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y147": { + "bits": {}, + "grid_x": 78, + "grid_y": 55, + "segment": "SEG_BRAM2_L_X30Y145", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y148": { + "bits": {}, + "grid_x": 78, + "grid_y": 54, + "segment": "SEG_BRAM3_L_X30Y145", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y149": { + "bits": {}, + "grid_x": 78, + "grid_y": 53, + "segment": "SEG_BRAM4_L_X30Y145", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y15": { + "bits": {}, + "grid_x": 78, + "grid_y": 192, + "segment": "SEG_BRAM0_L_X30Y15", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y150": { + "bits": {}, + "grid_x": 78, + "grid_y": 51, + "segment": "SEG_BRAM0_L_X30Y150", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y151": { + "bits": {}, + "grid_x": 78, + "grid_y": 50, + "segment": "SEG_BRAM1_L_X30Y150", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y152": { + "bits": {}, + "grid_x": 78, + "grid_y": 49, + "segment": "SEG_BRAM2_L_X30Y150", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y153": { + "bits": {}, + "grid_x": 78, + "grid_y": 48, + "segment": "SEG_BRAM3_L_X30Y150", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y154": { + "bits": {}, + "grid_x": 78, + "grid_y": 47, + "segment": "SEG_BRAM4_L_X30Y150", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y155": { + "bits": {}, + "grid_x": 78, + "grid_y": 46, + "segment": "SEG_BRAM0_L_X30Y155", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y156": { + "bits": {}, + "grid_x": 78, + "grid_y": 45, + "segment": "SEG_BRAM1_L_X30Y155", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y157": { + "bits": {}, + "grid_x": 78, + "grid_y": 44, + "segment": "SEG_BRAM2_L_X30Y155", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y158": { + "bits": {}, + "grid_x": 78, + "grid_y": 43, + "segment": "SEG_BRAM3_L_X30Y155", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y159": { + "bits": {}, + "grid_x": 78, + "grid_y": 42, + "segment": "SEG_BRAM4_L_X30Y155", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y16": { + "bits": {}, + "grid_x": 78, + "grid_y": 191, + "segment": "SEG_BRAM1_L_X30Y15", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y160": { + "bits": {}, + "grid_x": 78, + "grid_y": 41, + "segment": "SEG_BRAM0_L_X30Y160", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y161": { + "bits": {}, + "grid_x": 78, + "grid_y": 40, + "segment": "SEG_BRAM1_L_X30Y160", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y162": { + "bits": {}, + "grid_x": 78, + "grid_y": 39, + "segment": "SEG_BRAM2_L_X30Y160", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y163": { + "bits": {}, + "grid_x": 78, + "grid_y": 38, + "segment": "SEG_BRAM3_L_X30Y160", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y164": { + "bits": {}, + "grid_x": 78, + "grid_y": 37, + "segment": "SEG_BRAM4_L_X30Y160", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y165": { + "bits": {}, + "grid_x": 78, + "grid_y": 36, + "segment": "SEG_BRAM0_L_X30Y165", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y166": { + "bits": {}, + "grid_x": 78, + "grid_y": 35, + "segment": "SEG_BRAM1_L_X30Y165", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y167": { + "bits": {}, + "grid_x": 78, + "grid_y": 34, + "segment": "SEG_BRAM2_L_X30Y165", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y168": { + "bits": {}, + "grid_x": 78, + "grid_y": 33, + "segment": "SEG_BRAM3_L_X30Y165", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y169": { + "bits": {}, + "grid_x": 78, + "grid_y": 32, + "segment": "SEG_BRAM4_L_X30Y165", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y17": { + "bits": {}, + "grid_x": 78, + "grid_y": 190, + "segment": "SEG_BRAM2_L_X30Y15", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y170": { + "bits": {}, + "grid_x": 78, + "grid_y": 31, + "segment": "SEG_BRAM0_L_X30Y170", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y171": { + "bits": {}, + "grid_x": 78, + "grid_y": 30, + "segment": "SEG_BRAM1_L_X30Y170", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y172": { + "bits": {}, + "grid_x": 78, + "grid_y": 29, + "segment": "SEG_BRAM2_L_X30Y170", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y173": { + "bits": {}, + "grid_x": 78, + "grid_y": 28, + "segment": "SEG_BRAM3_L_X30Y170", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y174": { + "bits": {}, + "grid_x": 78, + "grid_y": 27, + "segment": "SEG_BRAM4_L_X30Y170", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y175": { + "bits": {}, + "grid_x": 78, + "grid_y": 25, + "segment": "SEG_BRAM0_L_X30Y175", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y176": { + "bits": {}, + "grid_x": 78, + "grid_y": 24, + "segment": "SEG_BRAM1_L_X30Y175", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y177": { + "bits": {}, + "grid_x": 78, + "grid_y": 23, + "segment": "SEG_BRAM2_L_X30Y175", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y178": { + "bits": {}, + "grid_x": 78, + "grid_y": 22, + "segment": "SEG_BRAM3_L_X30Y175", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y179": { + "bits": {}, + "grid_x": 78, + "grid_y": 21, + "segment": "SEG_BRAM4_L_X30Y175", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y18": { + "bits": {}, + "grid_x": 78, + "grid_y": 189, + "segment": "SEG_BRAM3_L_X30Y15", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y180": { + "bits": {}, + "grid_x": 78, + "grid_y": 20, + "segment": "SEG_BRAM0_L_X30Y180", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y181": { + "bits": {}, + "grid_x": 78, + "grid_y": 19, + "segment": "SEG_BRAM1_L_X30Y180", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y182": { + "bits": {}, + "grid_x": 78, + "grid_y": 18, + "segment": "SEG_BRAM2_L_X30Y180", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y183": { + "bits": {}, + "grid_x": 78, + "grid_y": 17, + "segment": "SEG_BRAM3_L_X30Y180", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y184": { + "bits": {}, + "grid_x": 78, + "grid_y": 16, + "segment": "SEG_BRAM4_L_X30Y180", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y185": { + "bits": {}, + "grid_x": 78, + "grid_y": 15, + "segment": "SEG_BRAM0_L_X30Y185", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y186": { + "bits": {}, + "grid_x": 78, + "grid_y": 14, + "segment": "SEG_BRAM1_L_X30Y185", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y187": { + "bits": {}, + "grid_x": 78, + "grid_y": 13, + "segment": "SEG_BRAM2_L_X30Y185", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y188": { + "bits": {}, + "grid_x": 78, + "grid_y": 12, + "segment": "SEG_BRAM3_L_X30Y185", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y189": { + "bits": {}, + "grid_x": 78, + "grid_y": 11, + "segment": "SEG_BRAM4_L_X30Y185", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y19": { + "bits": {}, + "grid_x": 78, + "grid_y": 188, + "segment": "SEG_BRAM4_L_X30Y15", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y190": { + "bits": {}, + "grid_x": 78, + "grid_y": 10, + "segment": "SEG_BRAM0_L_X30Y190", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y191": { + "bits": {}, + "grid_x": 78, + "grid_y": 9, + "segment": "SEG_BRAM1_L_X30Y190", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y192": { + "bits": {}, + "grid_x": 78, + "grid_y": 8, + "segment": "SEG_BRAM2_L_X30Y190", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y193": { + "bits": {}, + "grid_x": 78, + "grid_y": 7, + "segment": "SEG_BRAM3_L_X30Y190", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y194": { + "bits": {}, + "grid_x": 78, + "grid_y": 6, + "segment": "SEG_BRAM4_L_X30Y190", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y195": { + "bits": {}, + "grid_x": 78, + "grid_y": 5, + "segment": "SEG_BRAM0_L_X30Y195", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y196": { + "bits": {}, + "grid_x": 78, + "grid_y": 4, + "segment": "SEG_BRAM1_L_X30Y195", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y197": { + "bits": {}, + "grid_x": 78, + "grid_y": 3, + "segment": "SEG_BRAM2_L_X30Y195", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y198": { + "bits": {}, + "grid_x": 78, + "grid_y": 2, + "segment": "SEG_BRAM3_L_X30Y195", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y199": { + "bits": {}, + "grid_x": 78, + "grid_y": 1, + "segment": "SEG_BRAM4_L_X30Y195", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y2": { + "bits": {}, + "grid_x": 78, + "grid_y": 205, + "segment": "SEG_BRAM2_L_X30Y0", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y20": { + "bits": {}, + "grid_x": 78, + "grid_y": 187, + "segment": "SEG_BRAM0_L_X30Y20", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y21": { + "bits": {}, + "grid_x": 78, + "grid_y": 186, + "segment": "SEG_BRAM1_L_X30Y20", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y22": { + "bits": {}, + "grid_x": 78, + "grid_y": 185, + "segment": "SEG_BRAM2_L_X30Y20", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y23": { + "bits": {}, + "grid_x": 78, + "grid_y": 184, + "segment": "SEG_BRAM3_L_X30Y20", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y24": { + "bits": {}, + "grid_x": 78, + "grid_y": 183, + "segment": "SEG_BRAM4_L_X30Y20", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y25": { + "bits": {}, + "grid_x": 78, + "grid_y": 181, + "segment": "SEG_BRAM0_L_X30Y25", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y26": { + "bits": {}, + "grid_x": 78, + "grid_y": 180, + "segment": "SEG_BRAM1_L_X30Y25", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y27": { + "bits": {}, + "grid_x": 78, + "grid_y": 179, + "segment": "SEG_BRAM2_L_X30Y25", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y28": { + "bits": {}, + "grid_x": 78, + "grid_y": 178, + "segment": "SEG_BRAM3_L_X30Y25", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y29": { + "bits": {}, + "grid_x": 78, + "grid_y": 177, + "segment": "SEG_BRAM4_L_X30Y25", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y3": { + "bits": {}, + "grid_x": 78, + "grid_y": 204, + "segment": "SEG_BRAM3_L_X30Y0", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y30": { + "bits": {}, + "grid_x": 78, + "grid_y": 176, + "segment": "SEG_BRAM0_L_X30Y30", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y31": { + "bits": {}, + "grid_x": 78, + "grid_y": 175, + "segment": "SEG_BRAM1_L_X30Y30", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y32": { + "bits": {}, + "grid_x": 78, + "grid_y": 174, + "segment": "SEG_BRAM2_L_X30Y30", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y33": { + "bits": {}, + "grid_x": 78, + "grid_y": 173, + "segment": "SEG_BRAM3_L_X30Y30", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y34": { + "bits": {}, + "grid_x": 78, + "grid_y": 172, + "segment": "SEG_BRAM4_L_X30Y30", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y35": { + "bits": {}, + "grid_x": 78, + "grid_y": 171, + "segment": "SEG_BRAM0_L_X30Y35", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y36": { + "bits": {}, + "grid_x": 78, + "grid_y": 170, + "segment": "SEG_BRAM1_L_X30Y35", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y37": { + "bits": {}, + "grid_x": 78, + "grid_y": 169, + "segment": "SEG_BRAM2_L_X30Y35", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y38": { + "bits": {}, + "grid_x": 78, + "grid_y": 168, + "segment": "SEG_BRAM3_L_X30Y35", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y39": { + "bits": {}, + "grid_x": 78, + "grid_y": 167, + "segment": "SEG_BRAM4_L_X30Y35", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y4": { + "bits": {}, + "grid_x": 78, + "grid_y": 203, + "segment": "SEG_BRAM4_L_X30Y0", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y40": { + "bits": {}, + "grid_x": 78, + "grid_y": 166, + "segment": "SEG_BRAM0_L_X30Y40", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y41": { + "bits": {}, + "grid_x": 78, + "grid_y": 165, + "segment": "SEG_BRAM1_L_X30Y40", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y42": { + "bits": {}, + "grid_x": 78, + "grid_y": 164, + "segment": "SEG_BRAM2_L_X30Y40", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y43": { + "bits": {}, + "grid_x": 78, + "grid_y": 163, + "segment": "SEG_BRAM3_L_X30Y40", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y44": { + "bits": {}, + "grid_x": 78, + "grid_y": 162, + "segment": "SEG_BRAM4_L_X30Y40", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y45": { + "bits": {}, + "grid_x": 78, + "grid_y": 161, + "segment": "SEG_BRAM0_L_X30Y45", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y46": { + "bits": {}, + "grid_x": 78, + "grid_y": 160, + "segment": "SEG_BRAM1_L_X30Y45", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y47": { + "bits": {}, + "grid_x": 78, + "grid_y": 159, + "segment": "SEG_BRAM2_L_X30Y45", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y48": { + "bits": {}, + "grid_x": 78, + "grid_y": 158, + "segment": "SEG_BRAM3_L_X30Y45", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y49": { + "bits": {}, + "grid_x": 78, + "grid_y": 157, + "segment": "SEG_BRAM4_L_X30Y45", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y5": { + "bits": {}, + "grid_x": 78, + "grid_y": 202, + "segment": "SEG_BRAM0_L_X30Y5", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y50": { + "bits": {}, + "grid_x": 78, + "grid_y": 155, + "segment": "SEG_BRAM0_L_X30Y50", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y51": { + "bits": {}, + "grid_x": 78, + "grid_y": 154, + "segment": "SEG_BRAM1_L_X30Y50", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y52": { + "bits": {}, + "grid_x": 78, + "grid_y": 153, + "segment": "SEG_BRAM2_L_X30Y50", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y53": { + "bits": {}, + "grid_x": 78, + "grid_y": 152, + "segment": "SEG_BRAM3_L_X30Y50", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y54": { + "bits": {}, + "grid_x": 78, + "grid_y": 151, + "segment": "SEG_BRAM4_L_X30Y50", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y55": { + "bits": {}, + "grid_x": 78, + "grid_y": 150, + "segment": "SEG_BRAM0_L_X30Y55", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y56": { + "bits": {}, + "grid_x": 78, + "grid_y": 149, + "segment": "SEG_BRAM1_L_X30Y55", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y57": { + "bits": {}, + "grid_x": 78, + "grid_y": 148, + "segment": "SEG_BRAM2_L_X30Y55", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y58": { + "bits": {}, + "grid_x": 78, + "grid_y": 147, + "segment": "SEG_BRAM3_L_X30Y55", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y59": { + "bits": {}, + "grid_x": 78, + "grid_y": 146, + "segment": "SEG_BRAM4_L_X30Y55", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y6": { + "bits": {}, + "grid_x": 78, + "grid_y": 201, + "segment": "SEG_BRAM1_L_X30Y5", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y60": { + "bits": {}, + "grid_x": 78, + "grid_y": 145, + "segment": "SEG_BRAM0_L_X30Y60", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y61": { + "bits": {}, + "grid_x": 78, + "grid_y": 144, + "segment": "SEG_BRAM1_L_X30Y60", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y62": { + "bits": {}, + "grid_x": 78, + "grid_y": 143, + "segment": "SEG_BRAM2_L_X30Y60", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y63": { + "bits": {}, + "grid_x": 78, + "grid_y": 142, + "segment": "SEG_BRAM3_L_X30Y60", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y64": { + "bits": {}, + "grid_x": 78, + "grid_y": 141, + "segment": "SEG_BRAM4_L_X30Y60", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y65": { + "bits": {}, + "grid_x": 78, + "grid_y": 140, + "segment": "SEG_BRAM0_L_X30Y65", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y66": { + "bits": {}, + "grid_x": 78, + "grid_y": 139, + "segment": "SEG_BRAM1_L_X30Y65", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y67": { + "bits": {}, + "grid_x": 78, + "grid_y": 138, + "segment": "SEG_BRAM2_L_X30Y65", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y68": { + "bits": {}, + "grid_x": 78, + "grid_y": 137, + "segment": "SEG_BRAM3_L_X30Y65", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y69": { + "bits": {}, + "grid_x": 78, + "grid_y": 136, + "segment": "SEG_BRAM4_L_X30Y65", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y7": { + "bits": {}, + "grid_x": 78, + "grid_y": 200, + "segment": "SEG_BRAM2_L_X30Y5", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y70": { + "bits": {}, + "grid_x": 78, + "grid_y": 135, + "segment": "SEG_BRAM0_L_X30Y70", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y71": { + "bits": {}, + "grid_x": 78, + "grid_y": 134, + "segment": "SEG_BRAM1_L_X30Y70", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y72": { + "bits": {}, + "grid_x": 78, + "grid_y": 133, + "segment": "SEG_BRAM2_L_X30Y70", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y73": { + "bits": {}, + "grid_x": 78, + "grid_y": 132, + "segment": "SEG_BRAM3_L_X30Y70", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y74": { + "bits": {}, + "grid_x": 78, + "grid_y": 131, + "segment": "SEG_BRAM4_L_X30Y70", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y75": { + "bits": {}, + "grid_x": 78, + "grid_y": 129, + "segment": "SEG_BRAM0_L_X30Y75", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y76": { + "bits": {}, + "grid_x": 78, + "grid_y": 128, + "segment": "SEG_BRAM1_L_X30Y75", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y77": { + "bits": {}, + "grid_x": 78, + "grid_y": 127, + "segment": "SEG_BRAM2_L_X30Y75", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y78": { + "bits": {}, + "grid_x": 78, + "grid_y": 126, + "segment": "SEG_BRAM3_L_X30Y75", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y79": { + "bits": {}, + "grid_x": 78, + "grid_y": 125, + "segment": "SEG_BRAM4_L_X30Y75", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y8": { + "bits": {}, + "grid_x": 78, + "grid_y": 199, + "segment": "SEG_BRAM3_L_X30Y5", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y80": { + "bits": {}, + "grid_x": 78, + "grid_y": 124, + "segment": "SEG_BRAM0_L_X30Y80", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y81": { + "bits": {}, + "grid_x": 78, + "grid_y": 123, + "segment": "SEG_BRAM1_L_X30Y80", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y82": { + "bits": {}, + "grid_x": 78, + "grid_y": 122, + "segment": "SEG_BRAM2_L_X30Y80", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y83": { + "bits": {}, + "grid_x": 78, + "grid_y": 121, + "segment": "SEG_BRAM3_L_X30Y80", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y84": { + "bits": {}, + "grid_x": 78, + "grid_y": 120, + "segment": "SEG_BRAM4_L_X30Y80", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y85": { + "bits": {}, + "grid_x": 78, + "grid_y": 119, + "segment": "SEG_BRAM0_L_X30Y85", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y86": { + "bits": {}, + "grid_x": 78, + "grid_y": 118, + "segment": "SEG_BRAM1_L_X30Y85", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y87": { + "bits": {}, + "grid_x": 78, + "grid_y": 117, + "segment": "SEG_BRAM2_L_X30Y85", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y88": { + "bits": {}, + "grid_x": 78, + "grid_y": 116, + "segment": "SEG_BRAM3_L_X30Y85", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y89": { + "bits": {}, + "grid_x": 78, + "grid_y": 115, + "segment": "SEG_BRAM4_L_X30Y85", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y9": { + "bits": {}, + "grid_x": 78, + "grid_y": 198, + "segment": "SEG_BRAM4_L_X30Y5", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y90": { + "bits": {}, + "grid_x": 78, + "grid_y": 114, + "segment": "SEG_BRAM0_L_X30Y90", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y91": { + "bits": {}, + "grid_x": 78, + "grid_y": 113, + "segment": "SEG_BRAM1_L_X30Y90", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y92": { + "bits": {}, + "grid_x": 78, + "grid_y": 112, + "segment": "SEG_BRAM2_L_X30Y90", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y93": { + "bits": {}, + "grid_x": 78, + "grid_y": 111, + "segment": "SEG_BRAM3_L_X30Y90", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y94": { + "bits": {}, + "grid_x": 78, + "grid_y": 110, + "segment": "SEG_BRAM4_L_X30Y90", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y95": { + "bits": {}, + "grid_x": 78, + "grid_y": 109, + "segment": "SEG_BRAM0_L_X30Y95", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y96": { + "bits": {}, + "grid_x": 78, + "grid_y": 108, + "segment": "SEG_BRAM1_L_X30Y95", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y97": { + "bits": {}, + "grid_x": 78, + "grid_y": 107, + "segment": "SEG_BRAM2_L_X30Y95", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y98": { + "bits": {}, + "grid_x": 78, + "grid_y": 106, + "segment": "SEG_BRAM3_L_X30Y95", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X30Y99": { + "bits": {}, + "grid_x": 78, + "grid_y": 105, + "segment": "SEG_BRAM4_L_X30Y95", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y0": { + "bits": {}, + "grid_x": 20, + "grid_y": 207, + "segment": "SEG_BRAM0_L_X6Y0", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y1": { + "bits": {}, + "grid_x": 20, + "grid_y": 206, + "segment": "SEG_BRAM1_L_X6Y0", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y10": { + "bits": {}, + "grid_x": 20, + "grid_y": 197, + "segment": "SEG_BRAM0_L_X6Y10", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y100": { + "bits": {}, + "grid_x": 20, + "grid_y": 103, + "segment": "SEG_BRAM0_L_X6Y100", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y101": { + "bits": {}, + "grid_x": 20, + "grid_y": 102, + "segment": "SEG_BRAM1_L_X6Y100", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y102": { + "bits": {}, + "grid_x": 20, + "grid_y": 101, + "segment": "SEG_BRAM2_L_X6Y100", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y103": { + "bits": {}, + "grid_x": 20, + "grid_y": 100, + "segment": "SEG_BRAM3_L_X6Y100", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y104": { + "bits": {}, + "grid_x": 20, + "grid_y": 99, + "segment": "SEG_BRAM4_L_X6Y100", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y105": { + "bits": {}, + "grid_x": 20, + "grid_y": 98, + "segment": "SEG_BRAM0_L_X6Y105", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y106": { + "bits": {}, + "grid_x": 20, + "grid_y": 97, + "segment": "SEG_BRAM1_L_X6Y105", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y107": { + "bits": {}, + "grid_x": 20, + "grid_y": 96, + "segment": "SEG_BRAM2_L_X6Y105", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y108": { + "bits": {}, + "grid_x": 20, + "grid_y": 95, + "segment": "SEG_BRAM3_L_X6Y105", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y109": { + "bits": {}, + "grid_x": 20, + "grid_y": 94, + "segment": "SEG_BRAM4_L_X6Y105", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y11": { + "bits": {}, + "grid_x": 20, + "grid_y": 196, + "segment": "SEG_BRAM1_L_X6Y10", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y110": { + "bits": {}, + "grid_x": 20, + "grid_y": 93, + "segment": "SEG_BRAM0_L_X6Y110", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y111": { + "bits": {}, + "grid_x": 20, + "grid_y": 92, + "segment": "SEG_BRAM1_L_X6Y110", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y112": { + "bits": {}, + "grid_x": 20, + "grid_y": 91, + "segment": "SEG_BRAM2_L_X6Y110", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y113": { + "bits": {}, + "grid_x": 20, + "grid_y": 90, + "segment": "SEG_BRAM3_L_X6Y110", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y114": { + "bits": {}, + "grid_x": 20, + "grid_y": 89, + "segment": "SEG_BRAM4_L_X6Y110", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y115": { + "bits": {}, + "grid_x": 20, + "grid_y": 88, + "segment": "SEG_BRAM0_L_X6Y115", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y116": { + "bits": {}, + "grid_x": 20, + "grid_y": 87, + "segment": "SEG_BRAM1_L_X6Y115", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y117": { + "bits": {}, + "grid_x": 20, + "grid_y": 86, + "segment": "SEG_BRAM2_L_X6Y115", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y118": { + "bits": {}, + "grid_x": 20, + "grid_y": 85, + "segment": "SEG_BRAM3_L_X6Y115", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y119": { + "bits": {}, + "grid_x": 20, + "grid_y": 84, + "segment": "SEG_BRAM4_L_X6Y115", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y12": { + "bits": {}, + "grid_x": 20, + "grid_y": 195, + "segment": "SEG_BRAM2_L_X6Y10", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y120": { + "bits": {}, + "grid_x": 20, + "grid_y": 83, + "segment": "SEG_BRAM0_L_X6Y120", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y121": { + "bits": {}, + "grid_x": 20, + "grid_y": 82, + "segment": "SEG_BRAM1_L_X6Y120", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y122": { + "bits": {}, + "grid_x": 20, + "grid_y": 81, + "segment": "SEG_BRAM2_L_X6Y120", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y123": { + "bits": {}, + "grid_x": 20, + "grid_y": 80, + "segment": "SEG_BRAM3_L_X6Y120", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y124": { + "bits": {}, + "grid_x": 20, + "grid_y": 79, + "segment": "SEG_BRAM4_L_X6Y120", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y125": { + "bits": {}, + "grid_x": 20, + "grid_y": 77, + "segment": "SEG_BRAM0_L_X6Y125", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y126": { + "bits": {}, + "grid_x": 20, + "grid_y": 76, + "segment": "SEG_BRAM1_L_X6Y125", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y127": { + "bits": {}, + "grid_x": 20, + "grid_y": 75, + "segment": "SEG_BRAM2_L_X6Y125", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y128": { + "bits": {}, + "grid_x": 20, + "grid_y": 74, + "segment": "SEG_BRAM3_L_X6Y125", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y129": { + "bits": {}, + "grid_x": 20, + "grid_y": 73, + "segment": "SEG_BRAM4_L_X6Y125", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y13": { + "bits": {}, + "grid_x": 20, + "grid_y": 194, + "segment": "SEG_BRAM3_L_X6Y10", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y130": { + "bits": {}, + "grid_x": 20, + "grid_y": 72, + "segment": "SEG_BRAM0_L_X6Y130", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y131": { + "bits": {}, + "grid_x": 20, + "grid_y": 71, + "segment": "SEG_BRAM1_L_X6Y130", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y132": { + "bits": {}, + "grid_x": 20, + "grid_y": 70, + "segment": "SEG_BRAM2_L_X6Y130", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y133": { + "bits": {}, + "grid_x": 20, + "grid_y": 69, + "segment": "SEG_BRAM3_L_X6Y130", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y134": { + "bits": {}, + "grid_x": 20, + "grid_y": 68, + "segment": "SEG_BRAM4_L_X6Y130", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y135": { + "bits": {}, + "grid_x": 20, + "grid_y": 67, + "segment": "SEG_BRAM0_L_X6Y135", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y136": { + "bits": {}, + "grid_x": 20, + "grid_y": 66, + "segment": "SEG_BRAM1_L_X6Y135", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y137": { + "bits": {}, + "grid_x": 20, + "grid_y": 65, + "segment": "SEG_BRAM2_L_X6Y135", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y138": { + "bits": {}, + "grid_x": 20, + "grid_y": 64, + "segment": "SEG_BRAM3_L_X6Y135", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y139": { + "bits": {}, + "grid_x": 20, + "grid_y": 63, + "segment": "SEG_BRAM4_L_X6Y135", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y14": { + "bits": {}, + "grid_x": 20, + "grid_y": 193, + "segment": "SEG_BRAM4_L_X6Y10", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y140": { + "bits": {}, + "grid_x": 20, + "grid_y": 62, + "segment": "SEG_BRAM0_L_X6Y140", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y141": { + "bits": {}, + "grid_x": 20, + "grid_y": 61, + "segment": "SEG_BRAM1_L_X6Y140", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y142": { + "bits": {}, + "grid_x": 20, + "grid_y": 60, + "segment": "SEG_BRAM2_L_X6Y140", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y143": { + "bits": {}, + "grid_x": 20, + "grid_y": 59, + "segment": "SEG_BRAM3_L_X6Y140", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y144": { + "bits": {}, + "grid_x": 20, + "grid_y": 58, + "segment": "SEG_BRAM4_L_X6Y140", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y145": { + "bits": {}, + "grid_x": 20, + "grid_y": 57, + "segment": "SEG_BRAM0_L_X6Y145", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y146": { + "bits": {}, + "grid_x": 20, + "grid_y": 56, + "segment": "SEG_BRAM1_L_X6Y145", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y147": { + "bits": {}, + "grid_x": 20, + "grid_y": 55, + "segment": "SEG_BRAM2_L_X6Y145", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y148": { + "bits": {}, + "grid_x": 20, + "grid_y": 54, + "segment": "SEG_BRAM3_L_X6Y145", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y149": { + "bits": {}, + "grid_x": 20, + "grid_y": 53, + "segment": "SEG_BRAM4_L_X6Y145", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y15": { + "bits": {}, + "grid_x": 20, + "grid_y": 192, + "segment": "SEG_BRAM0_L_X6Y15", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y150": { + "bits": {}, + "grid_x": 20, + "grid_y": 51, + "segment": "SEG_BRAM0_L_X6Y150", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y151": { + "bits": {}, + "grid_x": 20, + "grid_y": 50, + "segment": "SEG_BRAM1_L_X6Y150", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y152": { + "bits": {}, + "grid_x": 20, + "grid_y": 49, + "segment": "SEG_BRAM2_L_X6Y150", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y153": { + "bits": {}, + "grid_x": 20, + "grid_y": 48, + "segment": "SEG_BRAM3_L_X6Y150", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y154": { + "bits": {}, + "grid_x": 20, + "grid_y": 47, + "segment": "SEG_BRAM4_L_X6Y150", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y155": { + "bits": {}, + "grid_x": 20, + "grid_y": 46, + "segment": "SEG_BRAM0_L_X6Y155", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y156": { + "bits": {}, + "grid_x": 20, + "grid_y": 45, + "segment": "SEG_BRAM1_L_X6Y155", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y157": { + "bits": {}, + "grid_x": 20, + "grid_y": 44, + "segment": "SEG_BRAM2_L_X6Y155", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y158": { + "bits": {}, + "grid_x": 20, + "grid_y": 43, + "segment": "SEG_BRAM3_L_X6Y155", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y159": { + "bits": {}, + "grid_x": 20, + "grid_y": 42, + "segment": "SEG_BRAM4_L_X6Y155", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y16": { + "bits": {}, + "grid_x": 20, + "grid_y": 191, + "segment": "SEG_BRAM1_L_X6Y15", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y160": { + "bits": {}, + "grid_x": 20, + "grid_y": 41, + "segment": "SEG_BRAM0_L_X6Y160", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y161": { + "bits": {}, + "grid_x": 20, + "grid_y": 40, + "segment": "SEG_BRAM1_L_X6Y160", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y162": { + "bits": {}, + "grid_x": 20, + "grid_y": 39, + "segment": "SEG_BRAM2_L_X6Y160", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y163": { + "bits": {}, + "grid_x": 20, + "grid_y": 38, + "segment": "SEG_BRAM3_L_X6Y160", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y164": { + "bits": {}, + "grid_x": 20, + "grid_y": 37, + "segment": "SEG_BRAM4_L_X6Y160", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y165": { + "bits": {}, + "grid_x": 20, + "grid_y": 36, + "segment": "SEG_BRAM0_L_X6Y165", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y166": { + "bits": {}, + "grid_x": 20, + "grid_y": 35, + "segment": "SEG_BRAM1_L_X6Y165", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y167": { + "bits": {}, + "grid_x": 20, + "grid_y": 34, + "segment": "SEG_BRAM2_L_X6Y165", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y168": { + "bits": {}, + "grid_x": 20, + "grid_y": 33, + "segment": "SEG_BRAM3_L_X6Y165", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y169": { + "bits": {}, + "grid_x": 20, + "grid_y": 32, + "segment": "SEG_BRAM4_L_X6Y165", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y17": { + "bits": {}, + "grid_x": 20, + "grid_y": 190, + "segment": "SEG_BRAM2_L_X6Y15", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y170": { + "bits": {}, + "grid_x": 20, + "grid_y": 31, + "segment": "SEG_BRAM0_L_X6Y170", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y171": { + "bits": {}, + "grid_x": 20, + "grid_y": 30, + "segment": "SEG_BRAM1_L_X6Y170", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y172": { + "bits": {}, + "grid_x": 20, + "grid_y": 29, + "segment": "SEG_BRAM2_L_X6Y170", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y173": { + "bits": {}, + "grid_x": 20, + "grid_y": 28, + "segment": "SEG_BRAM3_L_X6Y170", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y174": { + "bits": {}, + "grid_x": 20, + "grid_y": 27, + "segment": "SEG_BRAM4_L_X6Y170", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y175": { + "bits": {}, + "grid_x": 20, + "grid_y": 25, + "segment": "SEG_BRAM0_L_X6Y175", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y176": { + "bits": {}, + "grid_x": 20, + "grid_y": 24, + "segment": "SEG_BRAM1_L_X6Y175", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y177": { + "bits": {}, + "grid_x": 20, + "grid_y": 23, + "segment": "SEG_BRAM2_L_X6Y175", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y178": { + "bits": {}, + "grid_x": 20, + "grid_y": 22, + "segment": "SEG_BRAM3_L_X6Y175", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y179": { + "bits": {}, + "grid_x": 20, + "grid_y": 21, + "segment": "SEG_BRAM4_L_X6Y175", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y18": { + "bits": {}, + "grid_x": 20, + "grid_y": 189, + "segment": "SEG_BRAM3_L_X6Y15", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y180": { + "bits": {}, + "grid_x": 20, + "grid_y": 20, + "segment": "SEG_BRAM0_L_X6Y180", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y181": { + "bits": {}, + "grid_x": 20, + "grid_y": 19, + "segment": "SEG_BRAM1_L_X6Y180", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y182": { + "bits": {}, + "grid_x": 20, + "grid_y": 18, + "segment": "SEG_BRAM2_L_X6Y180", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y183": { + "bits": {}, + "grid_x": 20, + "grid_y": 17, + "segment": "SEG_BRAM3_L_X6Y180", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y184": { + "bits": {}, + "grid_x": 20, + "grid_y": 16, + "segment": "SEG_BRAM4_L_X6Y180", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y185": { + "bits": {}, + "grid_x": 20, + "grid_y": 15, + "segment": "SEG_BRAM0_L_X6Y185", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y186": { + "bits": {}, + "grid_x": 20, + "grid_y": 14, + "segment": "SEG_BRAM1_L_X6Y185", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y187": { + "bits": {}, + "grid_x": 20, + "grid_y": 13, + "segment": "SEG_BRAM2_L_X6Y185", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y188": { + "bits": {}, + "grid_x": 20, + "grid_y": 12, + "segment": "SEG_BRAM3_L_X6Y185", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y189": { + "bits": {}, + "grid_x": 20, + "grid_y": 11, + "segment": "SEG_BRAM4_L_X6Y185", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y19": { + "bits": {}, + "grid_x": 20, + "grid_y": 188, + "segment": "SEG_BRAM4_L_X6Y15", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y190": { + "bits": {}, + "grid_x": 20, + "grid_y": 10, + "segment": "SEG_BRAM0_L_X6Y190", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y191": { + "bits": {}, + "grid_x": 20, + "grid_y": 9, + "segment": "SEG_BRAM1_L_X6Y190", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y192": { + "bits": {}, + "grid_x": 20, + "grid_y": 8, + "segment": "SEG_BRAM2_L_X6Y190", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y193": { + "bits": {}, + "grid_x": 20, + "grid_y": 7, + "segment": "SEG_BRAM3_L_X6Y190", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y194": { + "bits": {}, + "grid_x": 20, + "grid_y": 6, + "segment": "SEG_BRAM4_L_X6Y190", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y195": { + "bits": {}, + "grid_x": 20, + "grid_y": 5, + "segment": "SEG_BRAM0_L_X6Y195", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y196": { + "bits": {}, + "grid_x": 20, + "grid_y": 4, + "segment": "SEG_BRAM1_L_X6Y195", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y197": { + "bits": {}, + "grid_x": 20, + "grid_y": 3, + "segment": "SEG_BRAM2_L_X6Y195", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y198": { + "bits": {}, + "grid_x": 20, + "grid_y": 2, + "segment": "SEG_BRAM3_L_X6Y195", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y199": { + "bits": {}, + "grid_x": 20, + "grid_y": 1, + "segment": "SEG_BRAM4_L_X6Y195", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y2": { + "bits": {}, + "grid_x": 20, + "grid_y": 205, + "segment": "SEG_BRAM2_L_X6Y0", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y20": { + "bits": {}, + "grid_x": 20, + "grid_y": 187, + "segment": "SEG_BRAM0_L_X6Y20", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y21": { + "bits": {}, + "grid_x": 20, + "grid_y": 186, + "segment": "SEG_BRAM1_L_X6Y20", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y22": { + "bits": {}, + "grid_x": 20, + "grid_y": 185, + "segment": "SEG_BRAM2_L_X6Y20", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y23": { + "bits": {}, + "grid_x": 20, + "grid_y": 184, + "segment": "SEG_BRAM3_L_X6Y20", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y24": { + "bits": {}, + "grid_x": 20, + "grid_y": 183, + "segment": "SEG_BRAM4_L_X6Y20", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y25": { + "bits": {}, + "grid_x": 20, + "grid_y": 181, + "segment": "SEG_BRAM0_L_X6Y25", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y26": { + "bits": {}, + "grid_x": 20, + "grid_y": 180, + "segment": "SEG_BRAM1_L_X6Y25", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y27": { + "bits": {}, + "grid_x": 20, + "grid_y": 179, + "segment": "SEG_BRAM2_L_X6Y25", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y28": { + "bits": {}, + "grid_x": 20, + "grid_y": 178, + "segment": "SEG_BRAM3_L_X6Y25", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y29": { + "bits": {}, + "grid_x": 20, + "grid_y": 177, + "segment": "SEG_BRAM4_L_X6Y25", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y3": { + "bits": {}, + "grid_x": 20, + "grid_y": 204, + "segment": "SEG_BRAM3_L_X6Y0", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y30": { + "bits": {}, + "grid_x": 20, + "grid_y": 176, + "segment": "SEG_BRAM0_L_X6Y30", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y31": { + "bits": {}, + "grid_x": 20, + "grid_y": 175, + "segment": "SEG_BRAM1_L_X6Y30", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y32": { + "bits": {}, + "grid_x": 20, + "grid_y": 174, + "segment": "SEG_BRAM2_L_X6Y30", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y33": { + "bits": {}, + "grid_x": 20, + "grid_y": 173, + "segment": "SEG_BRAM3_L_X6Y30", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y34": { + "bits": {}, + "grid_x": 20, + "grid_y": 172, + "segment": "SEG_BRAM4_L_X6Y30", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y35": { + "bits": {}, + "grid_x": 20, + "grid_y": 171, + "segment": "SEG_BRAM0_L_X6Y35", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y36": { + "bits": {}, + "grid_x": 20, + "grid_y": 170, + "segment": "SEG_BRAM1_L_X6Y35", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y37": { + "bits": {}, + "grid_x": 20, + "grid_y": 169, + "segment": "SEG_BRAM2_L_X6Y35", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y38": { + "bits": {}, + "grid_x": 20, + "grid_y": 168, + "segment": "SEG_BRAM3_L_X6Y35", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y39": { + "bits": {}, + "grid_x": 20, + "grid_y": 167, + "segment": "SEG_BRAM4_L_X6Y35", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y4": { + "bits": {}, + "grid_x": 20, + "grid_y": 203, + "segment": "SEG_BRAM4_L_X6Y0", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y40": { + "bits": {}, + "grid_x": 20, + "grid_y": 166, + "segment": "SEG_BRAM0_L_X6Y40", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y41": { + "bits": {}, + "grid_x": 20, + "grid_y": 165, + "segment": "SEG_BRAM1_L_X6Y40", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y42": { + "bits": {}, + "grid_x": 20, + "grid_y": 164, + "segment": "SEG_BRAM2_L_X6Y40", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y43": { + "bits": {}, + "grid_x": 20, + "grid_y": 163, + "segment": "SEG_BRAM3_L_X6Y40", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y44": { + "bits": {}, + "grid_x": 20, + "grid_y": 162, + "segment": "SEG_BRAM4_L_X6Y40", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y45": { + "bits": {}, + "grid_x": 20, + "grid_y": 161, + "segment": "SEG_BRAM0_L_X6Y45", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y46": { + "bits": {}, + "grid_x": 20, + "grid_y": 160, + "segment": "SEG_BRAM1_L_X6Y45", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y47": { + "bits": {}, + "grid_x": 20, + "grid_y": 159, + "segment": "SEG_BRAM2_L_X6Y45", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y48": { + "bits": {}, + "grid_x": 20, + "grid_y": 158, + "segment": "SEG_BRAM3_L_X6Y45", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y49": { + "bits": {}, + "grid_x": 20, + "grid_y": 157, + "segment": "SEG_BRAM4_L_X6Y45", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y5": { + "bits": {}, + "grid_x": 20, + "grid_y": 202, + "segment": "SEG_BRAM0_L_X6Y5", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 155, + "segment": "SEG_BRAM0_L_X6Y50", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 154, + "segment": "SEG_BRAM1_L_X6Y50", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 153, + "segment": "SEG_BRAM2_L_X6Y50", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 152, + "segment": "SEG_BRAM3_L_X6Y50", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 151, + "segment": "SEG_BRAM4_L_X6Y50", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 150, + "segment": "SEG_BRAM0_L_X6Y55", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 149, + "segment": "SEG_BRAM1_L_X6Y55", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 148, + "segment": "SEG_BRAM2_L_X6Y55", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 147, + "segment": "SEG_BRAM3_L_X6Y55", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 146, + "segment": "SEG_BRAM4_L_X6Y55", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y6": { + "bits": {}, + "grid_x": 20, + "grid_y": 201, + "segment": "SEG_BRAM1_L_X6Y5", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 145, + "segment": "SEG_BRAM0_L_X6Y60", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 144, + "segment": "SEG_BRAM1_L_X6Y60", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 143, + "segment": "SEG_BRAM2_L_X6Y60", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 142, + "segment": "SEG_BRAM3_L_X6Y60", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 141, + "segment": "SEG_BRAM4_L_X6Y60", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 140, + "segment": "SEG_BRAM0_L_X6Y65", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 139, + "segment": "SEG_BRAM1_L_X6Y65", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 138, + "segment": "SEG_BRAM2_L_X6Y65", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 137, + "segment": "SEG_BRAM3_L_X6Y65", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 136, + "segment": "SEG_BRAM4_L_X6Y65", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y7": { + "bits": {}, + "grid_x": 20, + "grid_y": 200, + "segment": "SEG_BRAM2_L_X6Y5", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 135, + "segment": "SEG_BRAM0_L_X6Y70", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 134, + "segment": "SEG_BRAM1_L_X6Y70", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 133, + "segment": "SEG_BRAM2_L_X6Y70", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 132, + "segment": "SEG_BRAM3_L_X6Y70", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 131, + "segment": "SEG_BRAM4_L_X6Y70", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 129, + "segment": "SEG_BRAM0_L_X6Y75", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 128, + "segment": "SEG_BRAM1_L_X6Y75", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 127, + "segment": "SEG_BRAM2_L_X6Y75", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 126, + "segment": "SEG_BRAM3_L_X6Y75", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 125, + "segment": "SEG_BRAM4_L_X6Y75", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y8": { + "bits": {}, + "grid_x": 20, + "grid_y": 199, + "segment": "SEG_BRAM3_L_X6Y5", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 124, + "segment": "SEG_BRAM0_L_X6Y80", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 123, + "segment": "SEG_BRAM1_L_X6Y80", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 122, + "segment": "SEG_BRAM2_L_X6Y80", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 121, + "segment": "SEG_BRAM3_L_X6Y80", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 120, + "segment": "SEG_BRAM4_L_X6Y80", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 119, + "segment": "SEG_BRAM0_L_X6Y85", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 118, + "segment": "SEG_BRAM1_L_X6Y85", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 117, + "segment": "SEG_BRAM2_L_X6Y85", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 116, + "segment": "SEG_BRAM3_L_X6Y85", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 115, + "segment": "SEG_BRAM4_L_X6Y85", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y9": { + "bits": {}, + "grid_x": 20, + "grid_y": 198, + "segment": "SEG_BRAM4_L_X6Y5", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 114, + "segment": "SEG_BRAM0_L_X6Y90", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 113, + "segment": "SEG_BRAM1_L_X6Y90", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 112, + "segment": "SEG_BRAM2_L_X6Y90", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 111, + "segment": "SEG_BRAM3_L_X6Y90", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 110, + "segment": "SEG_BRAM4_L_X6Y90", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 109, + "segment": "SEG_BRAM0_L_X6Y95", + "segment_type": "bram0_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 108, + "segment": "SEG_BRAM1_L_X6Y95", + "segment_type": "bram1_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 107, + "segment": "SEG_BRAM2_L_X6Y95", + "segment_type": "bram2_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 106, + "segment": "SEG_BRAM3_L_X6Y95", + "segment_type": "bram3_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_L_X6Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 20, + "grid_y": 105, + "segment": "SEG_BRAM4_L_X6Y95", + "segment_type": "bram4_l", + "sites": {}, + "type": "BRAM_INT_INTERFACE_L" + }, + "BRAM_INT_INTERFACE_R_X17Y0": { + "bits": {}, + "grid_x": 47, + "grid_y": 207, + "segment": "SEG_BRAM0_R_X17Y0", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y1": { + "bits": {}, + "grid_x": 47, + "grid_y": 206, + "segment": "SEG_BRAM1_R_X17Y0", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y10": { + "bits": {}, + "grid_x": 47, + "grid_y": 197, + "segment": "SEG_BRAM0_R_X17Y10", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y100": { + "bits": {}, + "grid_x": 47, + "grid_y": 103, + "segment": "SEG_BRAM0_R_X17Y100", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y101": { + "bits": {}, + "grid_x": 47, + "grid_y": 102, + "segment": "SEG_BRAM1_R_X17Y100", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y102": { + "bits": {}, + "grid_x": 47, + "grid_y": 101, + "segment": "SEG_BRAM2_R_X17Y100", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y103": { + "bits": {}, + "grid_x": 47, + "grid_y": 100, + "segment": "SEG_BRAM3_R_X17Y100", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y104": { + "bits": {}, + "grid_x": 47, + "grid_y": 99, + "segment": "SEG_BRAM4_R_X17Y100", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y105": { + "bits": {}, + "grid_x": 47, + "grid_y": 98, + "segment": "SEG_BRAM0_R_X17Y105", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y106": { + "bits": {}, + "grid_x": 47, + "grid_y": 97, + "segment": "SEG_BRAM1_R_X17Y105", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y107": { + "bits": {}, + "grid_x": 47, + "grid_y": 96, + "segment": "SEG_BRAM2_R_X17Y105", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y108": { + "bits": {}, + "grid_x": 47, + "grid_y": 95, + "segment": "SEG_BRAM3_R_X17Y105", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y109": { + "bits": {}, + "grid_x": 47, + "grid_y": 94, + "segment": "SEG_BRAM4_R_X17Y105", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y11": { + "bits": {}, + "grid_x": 47, + "grid_y": 196, + "segment": "SEG_BRAM1_R_X17Y10", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y110": { + "bits": {}, + "grid_x": 47, + "grid_y": 93, + "segment": "SEG_BRAM0_R_X17Y110", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y111": { + "bits": {}, + "grid_x": 47, + "grid_y": 92, + "segment": "SEG_BRAM1_R_X17Y110", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y112": { + "bits": {}, + "grid_x": 47, + "grid_y": 91, + "segment": "SEG_BRAM2_R_X17Y110", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y113": { + "bits": {}, + "grid_x": 47, + "grid_y": 90, + "segment": "SEG_BRAM3_R_X17Y110", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y114": { + "bits": {}, + "grid_x": 47, + "grid_y": 89, + "segment": "SEG_BRAM4_R_X17Y110", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y115": { + "bits": {}, + "grid_x": 47, + "grid_y": 88, + "segment": "SEG_BRAM0_R_X17Y115", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y116": { + "bits": {}, + "grid_x": 47, + "grid_y": 87, + "segment": "SEG_BRAM1_R_X17Y115", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y117": { + "bits": {}, + "grid_x": 47, + "grid_y": 86, + "segment": "SEG_BRAM2_R_X17Y115", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y118": { + "bits": {}, + "grid_x": 47, + "grid_y": 85, + "segment": "SEG_BRAM3_R_X17Y115", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y119": { + "bits": {}, + "grid_x": 47, + "grid_y": 84, + "segment": "SEG_BRAM4_R_X17Y115", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y12": { + "bits": {}, + "grid_x": 47, + "grid_y": 195, + "segment": "SEG_BRAM2_R_X17Y10", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y120": { + "bits": {}, + "grid_x": 47, + "grid_y": 83, + "segment": "SEG_BRAM0_R_X17Y120", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y121": { + "bits": {}, + "grid_x": 47, + "grid_y": 82, + "segment": "SEG_BRAM1_R_X17Y120", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y122": { + "bits": {}, + "grid_x": 47, + "grid_y": 81, + "segment": "SEG_BRAM2_R_X17Y120", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y123": { + "bits": {}, + "grid_x": 47, + "grid_y": 80, + "segment": "SEG_BRAM3_R_X17Y120", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y124": { + "bits": {}, + "grid_x": 47, + "grid_y": 79, + "segment": "SEG_BRAM4_R_X17Y120", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y125": { + "bits": {}, + "grid_x": 47, + "grid_y": 77, + "segment": "SEG_BRAM0_R_X17Y125", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y126": { + "bits": {}, + "grid_x": 47, + "grid_y": 76, + "segment": "SEG_BRAM1_R_X17Y125", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y127": { + "bits": {}, + "grid_x": 47, + "grid_y": 75, + "segment": "SEG_BRAM2_R_X17Y125", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y128": { + "bits": {}, + "grid_x": 47, + "grid_y": 74, + "segment": "SEG_BRAM3_R_X17Y125", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y129": { + "bits": {}, + "grid_x": 47, + "grid_y": 73, + "segment": "SEG_BRAM4_R_X17Y125", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y13": { + "bits": {}, + "grid_x": 47, + "grid_y": 194, + "segment": "SEG_BRAM3_R_X17Y10", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y130": { + "bits": {}, + "grid_x": 47, + "grid_y": 72, + "segment": "SEG_BRAM0_R_X17Y130", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y131": { + "bits": {}, + "grid_x": 47, + "grid_y": 71, + "segment": "SEG_BRAM1_R_X17Y130", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y132": { + "bits": {}, + "grid_x": 47, + "grid_y": 70, + "segment": "SEG_BRAM2_R_X17Y130", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y133": { + "bits": {}, + "grid_x": 47, + "grid_y": 69, + "segment": "SEG_BRAM3_R_X17Y130", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y134": { + "bits": {}, + "grid_x": 47, + "grid_y": 68, + "segment": "SEG_BRAM4_R_X17Y130", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y135": { + "bits": {}, + "grid_x": 47, + "grid_y": 67, + "segment": "SEG_BRAM0_R_X17Y135", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y136": { + "bits": {}, + "grid_x": 47, + "grid_y": 66, + "segment": "SEG_BRAM1_R_X17Y135", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y137": { + "bits": {}, + "grid_x": 47, + "grid_y": 65, + "segment": "SEG_BRAM2_R_X17Y135", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y138": { + "bits": {}, + "grid_x": 47, + "grid_y": 64, + "segment": "SEG_BRAM3_R_X17Y135", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y139": { + "bits": {}, + "grid_x": 47, + "grid_y": 63, + "segment": "SEG_BRAM4_R_X17Y135", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y14": { + "bits": {}, + "grid_x": 47, + "grid_y": 193, + "segment": "SEG_BRAM4_R_X17Y10", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y140": { + "bits": {}, + "grid_x": 47, + "grid_y": 62, + "segment": "SEG_BRAM0_R_X17Y140", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y141": { + "bits": {}, + "grid_x": 47, + "grid_y": 61, + "segment": "SEG_BRAM1_R_X17Y140", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y142": { + "bits": {}, + "grid_x": 47, + "grid_y": 60, + "segment": "SEG_BRAM2_R_X17Y140", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y143": { + "bits": {}, + "grid_x": 47, + "grid_y": 59, + "segment": "SEG_BRAM3_R_X17Y140", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y144": { + "bits": {}, + "grid_x": 47, + "grid_y": 58, + "segment": "SEG_BRAM4_R_X17Y140", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y145": { + "bits": {}, + "grid_x": 47, + "grid_y": 57, + "segment": "SEG_BRAM0_R_X17Y145", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y146": { + "bits": {}, + "grid_x": 47, + "grid_y": 56, + "segment": "SEG_BRAM1_R_X17Y145", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y147": { + "bits": {}, + "grid_x": 47, + "grid_y": 55, + "segment": "SEG_BRAM2_R_X17Y145", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y148": { + "bits": {}, + "grid_x": 47, + "grid_y": 54, + "segment": "SEG_BRAM3_R_X17Y145", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y149": { + "bits": {}, + "grid_x": 47, + "grid_y": 53, + "segment": "SEG_BRAM4_R_X17Y145", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y15": { + "bits": {}, + "grid_x": 47, + "grid_y": 192, + "segment": "SEG_BRAM0_R_X17Y15", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y150": { + "bits": {}, + "grid_x": 47, + "grid_y": 51, + "segment": "SEG_BRAM0_R_X17Y150", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y151": { + "bits": {}, + "grid_x": 47, + "grid_y": 50, + "segment": "SEG_BRAM1_R_X17Y150", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y152": { + "bits": {}, + "grid_x": 47, + "grid_y": 49, + "segment": "SEG_BRAM2_R_X17Y150", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y153": { + "bits": {}, + "grid_x": 47, + "grid_y": 48, + "segment": "SEG_BRAM3_R_X17Y150", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y154": { + "bits": {}, + "grid_x": 47, + "grid_y": 47, + "segment": "SEG_BRAM4_R_X17Y150", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y155": { + "bits": {}, + "grid_x": 47, + "grid_y": 46, + "segment": "SEG_BRAM0_R_X17Y155", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y156": { + "bits": {}, + "grid_x": 47, + "grid_y": 45, + "segment": "SEG_BRAM1_R_X17Y155", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y157": { + "bits": {}, + "grid_x": 47, + "grid_y": 44, + "segment": "SEG_BRAM2_R_X17Y155", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y158": { + "bits": {}, + "grid_x": 47, + "grid_y": 43, + "segment": "SEG_BRAM3_R_X17Y155", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y159": { + "bits": {}, + "grid_x": 47, + "grid_y": 42, + "segment": "SEG_BRAM4_R_X17Y155", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y16": { + "bits": {}, + "grid_x": 47, + "grid_y": 191, + "segment": "SEG_BRAM1_R_X17Y15", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y160": { + "bits": {}, + "grid_x": 47, + "grid_y": 41, + "segment": "SEG_BRAM0_R_X17Y160", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y161": { + "bits": {}, + "grid_x": 47, + "grid_y": 40, + "segment": "SEG_BRAM1_R_X17Y160", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y162": { + "bits": {}, + "grid_x": 47, + "grid_y": 39, + "segment": "SEG_BRAM2_R_X17Y160", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y163": { + "bits": {}, + "grid_x": 47, + "grid_y": 38, + "segment": "SEG_BRAM3_R_X17Y160", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y164": { + "bits": {}, + "grid_x": 47, + "grid_y": 37, + "segment": "SEG_BRAM4_R_X17Y160", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y165": { + "bits": {}, + "grid_x": 47, + "grid_y": 36, + "segment": "SEG_BRAM0_R_X17Y165", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y166": { + "bits": {}, + "grid_x": 47, + "grid_y": 35, + "segment": "SEG_BRAM1_R_X17Y165", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y167": { + "bits": {}, + "grid_x": 47, + "grid_y": 34, + "segment": "SEG_BRAM2_R_X17Y165", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y168": { + "bits": {}, + "grid_x": 47, + "grid_y": 33, + "segment": "SEG_BRAM3_R_X17Y165", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y169": { + "bits": {}, + "grid_x": 47, + "grid_y": 32, + "segment": "SEG_BRAM4_R_X17Y165", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y17": { + "bits": {}, + "grid_x": 47, + "grid_y": 190, + "segment": "SEG_BRAM2_R_X17Y15", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y170": { + "bits": {}, + "grid_x": 47, + "grid_y": 31, + "segment": "SEG_BRAM0_R_X17Y170", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y171": { + "bits": {}, + "grid_x": 47, + "grid_y": 30, + "segment": "SEG_BRAM1_R_X17Y170", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y172": { + "bits": {}, + "grid_x": 47, + "grid_y": 29, + "segment": "SEG_BRAM2_R_X17Y170", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y173": { + "bits": {}, + "grid_x": 47, + "grid_y": 28, + "segment": "SEG_BRAM3_R_X17Y170", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y174": { + "bits": {}, + "grid_x": 47, + "grid_y": 27, + "segment": "SEG_BRAM4_R_X17Y170", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y175": { + "bits": {}, + "grid_x": 47, + "grid_y": 25, + "segment": "SEG_BRAM0_R_X17Y175", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y176": { + "bits": {}, + "grid_x": 47, + "grid_y": 24, + "segment": "SEG_BRAM1_R_X17Y175", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y177": { + "bits": {}, + "grid_x": 47, + "grid_y": 23, + "segment": "SEG_BRAM2_R_X17Y175", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y178": { + "bits": {}, + "grid_x": 47, + "grid_y": 22, + "segment": "SEG_BRAM3_R_X17Y175", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y179": { + "bits": {}, + "grid_x": 47, + "grid_y": 21, + "segment": "SEG_BRAM4_R_X17Y175", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y18": { + "bits": {}, + "grid_x": 47, + "grid_y": 189, + "segment": "SEG_BRAM3_R_X17Y15", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y180": { + "bits": {}, + "grid_x": 47, + "grid_y": 20, + "segment": "SEG_BRAM0_R_X17Y180", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y181": { + "bits": {}, + "grid_x": 47, + "grid_y": 19, + "segment": "SEG_BRAM1_R_X17Y180", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y182": { + "bits": {}, + "grid_x": 47, + "grid_y": 18, + "segment": "SEG_BRAM2_R_X17Y180", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y183": { + "bits": {}, + "grid_x": 47, + "grid_y": 17, + "segment": "SEG_BRAM3_R_X17Y180", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y184": { + "bits": {}, + "grid_x": 47, + "grid_y": 16, + "segment": "SEG_BRAM4_R_X17Y180", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y185": { + "bits": {}, + "grid_x": 47, + "grid_y": 15, + "segment": "SEG_BRAM0_R_X17Y185", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y186": { + "bits": {}, + "grid_x": 47, + "grid_y": 14, + "segment": "SEG_BRAM1_R_X17Y185", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y187": { + "bits": {}, + "grid_x": 47, + "grid_y": 13, + "segment": "SEG_BRAM2_R_X17Y185", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y188": { + "bits": {}, + "grid_x": 47, + "grid_y": 12, + "segment": "SEG_BRAM3_R_X17Y185", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y189": { + "bits": {}, + "grid_x": 47, + "grid_y": 11, + "segment": "SEG_BRAM4_R_X17Y185", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y19": { + "bits": {}, + "grid_x": 47, + "grid_y": 188, + "segment": "SEG_BRAM4_R_X17Y15", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y190": { + "bits": {}, + "grid_x": 47, + "grid_y": 10, + "segment": "SEG_BRAM0_R_X17Y190", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y191": { + "bits": {}, + "grid_x": 47, + "grid_y": 9, + "segment": "SEG_BRAM1_R_X17Y190", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y192": { + "bits": {}, + "grid_x": 47, + "grid_y": 8, + "segment": "SEG_BRAM2_R_X17Y190", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y193": { + "bits": {}, + "grid_x": 47, + "grid_y": 7, + "segment": "SEG_BRAM3_R_X17Y190", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y194": { + "bits": {}, + "grid_x": 47, + "grid_y": 6, + "segment": "SEG_BRAM4_R_X17Y190", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y195": { + "bits": {}, + "grid_x": 47, + "grid_y": 5, + "segment": "SEG_BRAM0_R_X17Y195", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y196": { + "bits": {}, + "grid_x": 47, + "grid_y": 4, + "segment": "SEG_BRAM1_R_X17Y195", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y197": { + "bits": {}, + "grid_x": 47, + "grid_y": 3, + "segment": "SEG_BRAM2_R_X17Y195", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y198": { + "bits": {}, + "grid_x": 47, + "grid_y": 2, + "segment": "SEG_BRAM3_R_X17Y195", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y199": { + "bits": {}, + "grid_x": 47, + "grid_y": 1, + "segment": "SEG_BRAM4_R_X17Y195", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y2": { + "bits": {}, + "grid_x": 47, + "grid_y": 205, + "segment": "SEG_BRAM2_R_X17Y0", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y20": { + "bits": {}, + "grid_x": 47, + "grid_y": 187, + "segment": "SEG_BRAM0_R_X17Y20", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y21": { + "bits": {}, + "grid_x": 47, + "grid_y": 186, + "segment": "SEG_BRAM1_R_X17Y20", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y22": { + "bits": {}, + "grid_x": 47, + "grid_y": 185, + "segment": "SEG_BRAM2_R_X17Y20", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y23": { + "bits": {}, + "grid_x": 47, + "grid_y": 184, + "segment": "SEG_BRAM3_R_X17Y20", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y24": { + "bits": {}, + "grid_x": 47, + "grid_y": 183, + "segment": "SEG_BRAM4_R_X17Y20", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y25": { + "bits": {}, + "grid_x": 47, + "grid_y": 181, + "segment": "SEG_BRAM0_R_X17Y25", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y26": { + "bits": {}, + "grid_x": 47, + "grid_y": 180, + "segment": "SEG_BRAM1_R_X17Y25", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y27": { + "bits": {}, + "grid_x": 47, + "grid_y": 179, + "segment": "SEG_BRAM2_R_X17Y25", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y28": { + "bits": {}, + "grid_x": 47, + "grid_y": 178, + "segment": "SEG_BRAM3_R_X17Y25", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y29": { + "bits": {}, + "grid_x": 47, + "grid_y": 177, + "segment": "SEG_BRAM4_R_X17Y25", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y3": { + "bits": {}, + "grid_x": 47, + "grid_y": 204, + "segment": "SEG_BRAM3_R_X17Y0", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y30": { + "bits": {}, + "grid_x": 47, + "grid_y": 176, + "segment": "SEG_BRAM0_R_X17Y30", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y31": { + "bits": {}, + "grid_x": 47, + "grid_y": 175, + "segment": "SEG_BRAM1_R_X17Y30", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y32": { + "bits": {}, + "grid_x": 47, + "grid_y": 174, + "segment": "SEG_BRAM2_R_X17Y30", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y33": { + "bits": {}, + "grid_x": 47, + "grid_y": 173, + "segment": "SEG_BRAM3_R_X17Y30", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y34": { + "bits": {}, + "grid_x": 47, + "grid_y": 172, + "segment": "SEG_BRAM4_R_X17Y30", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y35": { + "bits": {}, + "grid_x": 47, + "grid_y": 171, + "segment": "SEG_BRAM0_R_X17Y35", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y36": { + "bits": {}, + "grid_x": 47, + "grid_y": 170, + "segment": "SEG_BRAM1_R_X17Y35", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y37": { + "bits": {}, + "grid_x": 47, + "grid_y": 169, + "segment": "SEG_BRAM2_R_X17Y35", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y38": { + "bits": {}, + "grid_x": 47, + "grid_y": 168, + "segment": "SEG_BRAM3_R_X17Y35", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y39": { + "bits": {}, + "grid_x": 47, + "grid_y": 167, + "segment": "SEG_BRAM4_R_X17Y35", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y4": { + "bits": {}, + "grid_x": 47, + "grid_y": 203, + "segment": "SEG_BRAM4_R_X17Y0", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y40": { + "bits": {}, + "grid_x": 47, + "grid_y": 166, + "segment": "SEG_BRAM0_R_X17Y40", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y41": { + "bits": {}, + "grid_x": 47, + "grid_y": 165, + "segment": "SEG_BRAM1_R_X17Y40", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y42": { + "bits": {}, + "grid_x": 47, + "grid_y": 164, + "segment": "SEG_BRAM2_R_X17Y40", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y43": { + "bits": {}, + "grid_x": 47, + "grid_y": 163, + "segment": "SEG_BRAM3_R_X17Y40", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y44": { + "bits": {}, + "grid_x": 47, + "grid_y": 162, + "segment": "SEG_BRAM4_R_X17Y40", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y45": { + "bits": {}, + "grid_x": 47, + "grid_y": 161, + "segment": "SEG_BRAM0_R_X17Y45", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y46": { + "bits": {}, + "grid_x": 47, + "grid_y": 160, + "segment": "SEG_BRAM1_R_X17Y45", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y47": { + "bits": {}, + "grid_x": 47, + "grid_y": 159, + "segment": "SEG_BRAM2_R_X17Y45", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y48": { + "bits": {}, + "grid_x": 47, + "grid_y": 158, + "segment": "SEG_BRAM3_R_X17Y45", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y49": { + "bits": {}, + "grid_x": 47, + "grid_y": 157, + "segment": "SEG_BRAM4_R_X17Y45", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y5": { + "bits": {}, + "grid_x": 47, + "grid_y": 202, + "segment": "SEG_BRAM0_R_X17Y5", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y50": { + "bits": {}, + "grid_x": 47, + "grid_y": 155, + "segment": "SEG_BRAM0_R_X17Y50", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y51": { + "bits": {}, + "grid_x": 47, + "grid_y": 154, + "segment": "SEG_BRAM1_R_X17Y50", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y52": { + "bits": {}, + "grid_x": 47, + "grid_y": 153, + "segment": "SEG_BRAM2_R_X17Y50", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y53": { + "bits": {}, + "grid_x": 47, + "grid_y": 152, + "segment": "SEG_BRAM3_R_X17Y50", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y54": { + "bits": {}, + "grid_x": 47, + "grid_y": 151, + "segment": "SEG_BRAM4_R_X17Y50", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y55": { + "bits": {}, + "grid_x": 47, + "grid_y": 150, + "segment": "SEG_BRAM0_R_X17Y55", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y56": { + "bits": {}, + "grid_x": 47, + "grid_y": 149, + "segment": "SEG_BRAM1_R_X17Y55", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y57": { + "bits": {}, + "grid_x": 47, + "grid_y": 148, + "segment": "SEG_BRAM2_R_X17Y55", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y58": { + "bits": {}, + "grid_x": 47, + "grid_y": 147, + "segment": "SEG_BRAM3_R_X17Y55", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y59": { + "bits": {}, + "grid_x": 47, + "grid_y": 146, + "segment": "SEG_BRAM4_R_X17Y55", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y6": { + "bits": {}, + "grid_x": 47, + "grid_y": 201, + "segment": "SEG_BRAM1_R_X17Y5", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y60": { + "bits": {}, + "grid_x": 47, + "grid_y": 145, + "segment": "SEG_BRAM0_R_X17Y60", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y61": { + "bits": {}, + "grid_x": 47, + "grid_y": 144, + "segment": "SEG_BRAM1_R_X17Y60", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y62": { + "bits": {}, + "grid_x": 47, + "grid_y": 143, + "segment": "SEG_BRAM2_R_X17Y60", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y63": { + "bits": {}, + "grid_x": 47, + "grid_y": 142, + "segment": "SEG_BRAM3_R_X17Y60", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y64": { + "bits": {}, + "grid_x": 47, + "grid_y": 141, + "segment": "SEG_BRAM4_R_X17Y60", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y65": { + "bits": {}, + "grid_x": 47, + "grid_y": 140, + "segment": "SEG_BRAM0_R_X17Y65", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y66": { + "bits": {}, + "grid_x": 47, + "grid_y": 139, + "segment": "SEG_BRAM1_R_X17Y65", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y67": { + "bits": {}, + "grid_x": 47, + "grid_y": 138, + "segment": "SEG_BRAM2_R_X17Y65", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y68": { + "bits": {}, + "grid_x": 47, + "grid_y": 137, + "segment": "SEG_BRAM3_R_X17Y65", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y69": { + "bits": {}, + "grid_x": 47, + "grid_y": 136, + "segment": "SEG_BRAM4_R_X17Y65", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y7": { + "bits": {}, + "grid_x": 47, + "grid_y": 200, + "segment": "SEG_BRAM2_R_X17Y5", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y70": { + "bits": {}, + "grid_x": 47, + "grid_y": 135, + "segment": "SEG_BRAM0_R_X17Y70", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y71": { + "bits": {}, + "grid_x": 47, + "grid_y": 134, + "segment": "SEG_BRAM1_R_X17Y70", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y72": { + "bits": {}, + "grid_x": 47, + "grid_y": 133, + "segment": "SEG_BRAM2_R_X17Y70", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y73": { + "bits": {}, + "grid_x": 47, + "grid_y": 132, + "segment": "SEG_BRAM3_R_X17Y70", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y74": { + "bits": {}, + "grid_x": 47, + "grid_y": 131, + "segment": "SEG_BRAM4_R_X17Y70", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y75": { + "bits": {}, + "grid_x": 47, + "grid_y": 129, + "segment": "SEG_BRAM0_R_X17Y75", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y76": { + "bits": {}, + "grid_x": 47, + "grid_y": 128, + "segment": "SEG_BRAM1_R_X17Y75", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y77": { + "bits": {}, + "grid_x": 47, + "grid_y": 127, + "segment": "SEG_BRAM2_R_X17Y75", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y78": { + "bits": {}, + "grid_x": 47, + "grid_y": 126, + "segment": "SEG_BRAM3_R_X17Y75", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y79": { + "bits": {}, + "grid_x": 47, + "grid_y": 125, + "segment": "SEG_BRAM4_R_X17Y75", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y8": { + "bits": {}, + "grid_x": 47, + "grid_y": 199, + "segment": "SEG_BRAM3_R_X17Y5", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y80": { + "bits": {}, + "grid_x": 47, + "grid_y": 124, + "segment": "SEG_BRAM0_R_X17Y80", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y81": { + "bits": {}, + "grid_x": 47, + "grid_y": 123, + "segment": "SEG_BRAM1_R_X17Y80", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y82": { + "bits": {}, + "grid_x": 47, + "grid_y": 122, + "segment": "SEG_BRAM2_R_X17Y80", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y83": { + "bits": {}, + "grid_x": 47, + "grid_y": 121, + "segment": "SEG_BRAM3_R_X17Y80", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y84": { + "bits": {}, + "grid_x": 47, + "grid_y": 120, + "segment": "SEG_BRAM4_R_X17Y80", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y85": { + "bits": {}, + "grid_x": 47, + "grid_y": 119, + "segment": "SEG_BRAM0_R_X17Y85", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y86": { + "bits": {}, + "grid_x": 47, + "grid_y": 118, + "segment": "SEG_BRAM1_R_X17Y85", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y87": { + "bits": {}, + "grid_x": 47, + "grid_y": 117, + "segment": "SEG_BRAM2_R_X17Y85", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y88": { + "bits": {}, + "grid_x": 47, + "grid_y": 116, + "segment": "SEG_BRAM3_R_X17Y85", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y89": { + "bits": {}, + "grid_x": 47, + "grid_y": 115, + "segment": "SEG_BRAM4_R_X17Y85", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y9": { + "bits": {}, + "grid_x": 47, + "grid_y": 198, + "segment": "SEG_BRAM4_R_X17Y5", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y90": { + "bits": {}, + "grid_x": 47, + "grid_y": 114, + "segment": "SEG_BRAM0_R_X17Y90", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y91": { + "bits": {}, + "grid_x": 47, + "grid_y": 113, + "segment": "SEG_BRAM1_R_X17Y90", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y92": { + "bits": {}, + "grid_x": 47, + "grid_y": 112, + "segment": "SEG_BRAM2_R_X17Y90", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y93": { + "bits": {}, + "grid_x": 47, + "grid_y": 111, + "segment": "SEG_BRAM3_R_X17Y90", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y94": { + "bits": {}, + "grid_x": 47, + "grid_y": 110, + "segment": "SEG_BRAM4_R_X17Y90", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y95": { + "bits": {}, + "grid_x": 47, + "grid_y": 109, + "segment": "SEG_BRAM0_R_X17Y95", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y96": { + "bits": {}, + "grid_x": 47, + "grid_y": 108, + "segment": "SEG_BRAM1_R_X17Y95", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y97": { + "bits": {}, + "grid_x": 47, + "grid_y": 107, + "segment": "SEG_BRAM2_R_X17Y95", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y98": { + "bits": {}, + "grid_x": 47, + "grid_y": 106, + "segment": "SEG_BRAM3_R_X17Y95", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X17Y99": { + "bits": {}, + "grid_x": 47, + "grid_y": 105, + "segment": "SEG_BRAM4_R_X17Y95", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y0": { + "bits": {}, + "grid_x": 96, + "grid_y": 207, + "segment": "SEG_BRAM0_R_X37Y0", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y1": { + "bits": {}, + "grid_x": 96, + "grid_y": 206, + "segment": "SEG_BRAM1_R_X37Y0", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y10": { + "bits": {}, + "grid_x": 96, + "grid_y": 197, + "segment": "SEG_BRAM0_R_X37Y10", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y11": { + "bits": {}, + "grid_x": 96, + "grid_y": 196, + "segment": "SEG_BRAM1_R_X37Y10", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y12": { + "bits": {}, + "grid_x": 96, + "grid_y": 195, + "segment": "SEG_BRAM2_R_X37Y10", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y13": { + "bits": {}, + "grid_x": 96, + "grid_y": 194, + "segment": "SEG_BRAM3_R_X37Y10", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y14": { + "bits": {}, + "grid_x": 96, + "grid_y": 193, + "segment": "SEG_BRAM4_R_X37Y10", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y15": { + "bits": {}, + "grid_x": 96, + "grid_y": 192, + "segment": "SEG_BRAM0_R_X37Y15", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y16": { + "bits": {}, + "grid_x": 96, + "grid_y": 191, + "segment": "SEG_BRAM1_R_X37Y15", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y17": { + "bits": {}, + "grid_x": 96, + "grid_y": 190, + "segment": "SEG_BRAM2_R_X37Y15", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y18": { + "bits": {}, + "grid_x": 96, + "grid_y": 189, + "segment": "SEG_BRAM3_R_X37Y15", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y19": { + "bits": {}, + "grid_x": 96, + "grid_y": 188, + "segment": "SEG_BRAM4_R_X37Y15", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y2": { + "bits": {}, + "grid_x": 96, + "grid_y": 205, + "segment": "SEG_BRAM2_R_X37Y0", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y20": { + "bits": {}, + "grid_x": 96, + "grid_y": 187, + "segment": "SEG_BRAM0_R_X37Y20", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y21": { + "bits": {}, + "grid_x": 96, + "grid_y": 186, + "segment": "SEG_BRAM1_R_X37Y20", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y22": { + "bits": {}, + "grid_x": 96, + "grid_y": 185, + "segment": "SEG_BRAM2_R_X37Y20", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y23": { + "bits": {}, + "grid_x": 96, + "grid_y": 184, + "segment": "SEG_BRAM3_R_X37Y20", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y24": { + "bits": {}, + "grid_x": 96, + "grid_y": 183, + "segment": "SEG_BRAM4_R_X37Y20", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y25": { + "bits": {}, + "grid_x": 96, + "grid_y": 181, + "segment": "SEG_BRAM0_R_X37Y25", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y26": { + "bits": {}, + "grid_x": 96, + "grid_y": 180, + "segment": "SEG_BRAM1_R_X37Y25", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y27": { + "bits": {}, + "grid_x": 96, + "grid_y": 179, + "segment": "SEG_BRAM2_R_X37Y25", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y28": { + "bits": {}, + "grid_x": 96, + "grid_y": 178, + "segment": "SEG_BRAM3_R_X37Y25", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y29": { + "bits": {}, + "grid_x": 96, + "grid_y": 177, + "segment": "SEG_BRAM4_R_X37Y25", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y3": { + "bits": {}, + "grid_x": 96, + "grid_y": 204, + "segment": "SEG_BRAM3_R_X37Y0", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y30": { + "bits": {}, + "grid_x": 96, + "grid_y": 176, + "segment": "SEG_BRAM0_R_X37Y30", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y31": { + "bits": {}, + "grid_x": 96, + "grid_y": 175, + "segment": "SEG_BRAM1_R_X37Y30", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y32": { + "bits": {}, + "grid_x": 96, + "grid_y": 174, + "segment": "SEG_BRAM2_R_X37Y30", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y33": { + "bits": {}, + "grid_x": 96, + "grid_y": 173, + "segment": "SEG_BRAM3_R_X37Y30", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y34": { + "bits": {}, + "grid_x": 96, + "grid_y": 172, + "segment": "SEG_BRAM4_R_X37Y30", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y35": { + "bits": {}, + "grid_x": 96, + "grid_y": 171, + "segment": "SEG_BRAM0_R_X37Y35", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y36": { + "bits": {}, + "grid_x": 96, + "grid_y": 170, + "segment": "SEG_BRAM1_R_X37Y35", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y37": { + "bits": {}, + "grid_x": 96, + "grid_y": 169, + "segment": "SEG_BRAM2_R_X37Y35", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y38": { + "bits": {}, + "grid_x": 96, + "grid_y": 168, + "segment": "SEG_BRAM3_R_X37Y35", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y39": { + "bits": {}, + "grid_x": 96, + "grid_y": 167, + "segment": "SEG_BRAM4_R_X37Y35", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y4": { + "bits": {}, + "grid_x": 96, + "grid_y": 203, + "segment": "SEG_BRAM4_R_X37Y0", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y40": { + "bits": {}, + "grid_x": 96, + "grid_y": 166, + "segment": "SEG_BRAM0_R_X37Y40", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y41": { + "bits": {}, + "grid_x": 96, + "grid_y": 165, + "segment": "SEG_BRAM1_R_X37Y40", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y42": { + "bits": {}, + "grid_x": 96, + "grid_y": 164, + "segment": "SEG_BRAM2_R_X37Y40", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y43": { + "bits": {}, + "grid_x": 96, + "grid_y": 163, + "segment": "SEG_BRAM3_R_X37Y40", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y44": { + "bits": {}, + "grid_x": 96, + "grid_y": 162, + "segment": "SEG_BRAM4_R_X37Y40", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y45": { + "bits": {}, + "grid_x": 96, + "grid_y": 161, + "segment": "SEG_BRAM0_R_X37Y45", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y46": { + "bits": {}, + "grid_x": 96, + "grid_y": 160, + "segment": "SEG_BRAM1_R_X37Y45", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y47": { + "bits": {}, + "grid_x": 96, + "grid_y": 159, + "segment": "SEG_BRAM2_R_X37Y45", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y48": { + "bits": {}, + "grid_x": 96, + "grid_y": 158, + "segment": "SEG_BRAM3_R_X37Y45", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y49": { + "bits": {}, + "grid_x": 96, + "grid_y": 157, + "segment": "SEG_BRAM4_R_X37Y45", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y5": { + "bits": {}, + "grid_x": 96, + "grid_y": 202, + "segment": "SEG_BRAM0_R_X37Y5", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y50": { + "bits": {}, + "grid_x": 96, + "grid_y": 155, + "segment": "SEG_BRAM0_R_X37Y50", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y51": { + "bits": {}, + "grid_x": 96, + "grid_y": 154, + "segment": "SEG_BRAM1_R_X37Y50", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y52": { + "bits": {}, + "grid_x": 96, + "grid_y": 153, + "segment": "SEG_BRAM2_R_X37Y50", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y53": { + "bits": {}, + "grid_x": 96, + "grid_y": 152, + "segment": "SEG_BRAM3_R_X37Y50", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y54": { + "bits": {}, + "grid_x": 96, + "grid_y": 151, + "segment": "SEG_BRAM4_R_X37Y50", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y55": { + "bits": {}, + "grid_x": 96, + "grid_y": 150, + "segment": "SEG_BRAM0_R_X37Y55", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y56": { + "bits": {}, + "grid_x": 96, + "grid_y": 149, + "segment": "SEG_BRAM1_R_X37Y55", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y57": { + "bits": {}, + "grid_x": 96, + "grid_y": 148, + "segment": "SEG_BRAM2_R_X37Y55", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y58": { + "bits": {}, + "grid_x": 96, + "grid_y": 147, + "segment": "SEG_BRAM3_R_X37Y55", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y59": { + "bits": {}, + "grid_x": 96, + "grid_y": 146, + "segment": "SEG_BRAM4_R_X37Y55", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y6": { + "bits": {}, + "grid_x": 96, + "grid_y": 201, + "segment": "SEG_BRAM1_R_X37Y5", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y60": { + "bits": {}, + "grid_x": 96, + "grid_y": 145, + "segment": "SEG_BRAM0_R_X37Y60", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y61": { + "bits": {}, + "grid_x": 96, + "grid_y": 144, + "segment": "SEG_BRAM1_R_X37Y60", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y62": { + "bits": {}, + "grid_x": 96, + "grid_y": 143, + "segment": "SEG_BRAM2_R_X37Y60", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y63": { + "bits": {}, + "grid_x": 96, + "grid_y": 142, + "segment": "SEG_BRAM3_R_X37Y60", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y64": { + "bits": {}, + "grid_x": 96, + "grid_y": 141, + "segment": "SEG_BRAM4_R_X37Y60", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y65": { + "bits": {}, + "grid_x": 96, + "grid_y": 140, + "segment": "SEG_BRAM0_R_X37Y65", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y66": { + "bits": {}, + "grid_x": 96, + "grid_y": 139, + "segment": "SEG_BRAM1_R_X37Y65", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y67": { + "bits": {}, + "grid_x": 96, + "grid_y": 138, + "segment": "SEG_BRAM2_R_X37Y65", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y68": { + "bits": {}, + "grid_x": 96, + "grid_y": 137, + "segment": "SEG_BRAM3_R_X37Y65", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y69": { + "bits": {}, + "grid_x": 96, + "grid_y": 136, + "segment": "SEG_BRAM4_R_X37Y65", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y7": { + "bits": {}, + "grid_x": 96, + "grid_y": 200, + "segment": "SEG_BRAM2_R_X37Y5", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y70": { + "bits": {}, + "grid_x": 96, + "grid_y": 135, + "segment": "SEG_BRAM0_R_X37Y70", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y71": { + "bits": {}, + "grid_x": 96, + "grid_y": 134, + "segment": "SEG_BRAM1_R_X37Y70", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y72": { + "bits": {}, + "grid_x": 96, + "grid_y": 133, + "segment": "SEG_BRAM2_R_X37Y70", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y73": { + "bits": {}, + "grid_x": 96, + "grid_y": 132, + "segment": "SEG_BRAM3_R_X37Y70", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y74": { + "bits": {}, + "grid_x": 96, + "grid_y": 131, + "segment": "SEG_BRAM4_R_X37Y70", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y75": { + "bits": {}, + "grid_x": 96, + "grid_y": 129, + "segment": "SEG_BRAM0_R_X37Y75", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y76": { + "bits": {}, + "grid_x": 96, + "grid_y": 128, + "segment": "SEG_BRAM1_R_X37Y75", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y77": { + "bits": {}, + "grid_x": 96, + "grid_y": 127, + "segment": "SEG_BRAM2_R_X37Y75", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y78": { + "bits": {}, + "grid_x": 96, + "grid_y": 126, + "segment": "SEG_BRAM3_R_X37Y75", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y79": { + "bits": {}, + "grid_x": 96, + "grid_y": 125, + "segment": "SEG_BRAM4_R_X37Y75", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y8": { + "bits": {}, + "grid_x": 96, + "grid_y": 199, + "segment": "SEG_BRAM3_R_X37Y5", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y80": { + "bits": {}, + "grid_x": 96, + "grid_y": 124, + "segment": "SEG_BRAM0_R_X37Y80", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y81": { + "bits": {}, + "grid_x": 96, + "grid_y": 123, + "segment": "SEG_BRAM1_R_X37Y80", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y82": { + "bits": {}, + "grid_x": 96, + "grid_y": 122, + "segment": "SEG_BRAM2_R_X37Y80", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y83": { + "bits": {}, + "grid_x": 96, + "grid_y": 121, + "segment": "SEG_BRAM3_R_X37Y80", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y84": { + "bits": {}, + "grid_x": 96, + "grid_y": 120, + "segment": "SEG_BRAM4_R_X37Y80", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y85": { + "bits": {}, + "grid_x": 96, + "grid_y": 119, + "segment": "SEG_BRAM0_R_X37Y85", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y86": { + "bits": {}, + "grid_x": 96, + "grid_y": 118, + "segment": "SEG_BRAM1_R_X37Y85", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y87": { + "bits": {}, + "grid_x": 96, + "grid_y": 117, + "segment": "SEG_BRAM2_R_X37Y85", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y88": { + "bits": {}, + "grid_x": 96, + "grid_y": 116, + "segment": "SEG_BRAM3_R_X37Y85", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y89": { + "bits": {}, + "grid_x": 96, + "grid_y": 115, + "segment": "SEG_BRAM4_R_X37Y85", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y9": { + "bits": {}, + "grid_x": 96, + "grid_y": 198, + "segment": "SEG_BRAM4_R_X37Y5", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y90": { + "bits": {}, + "grid_x": 96, + "grid_y": 114, + "segment": "SEG_BRAM0_R_X37Y90", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y91": { + "bits": {}, + "grid_x": 96, + "grid_y": 113, + "segment": "SEG_BRAM1_R_X37Y90", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y92": { + "bits": {}, + "grid_x": 96, + "grid_y": 112, + "segment": "SEG_BRAM2_R_X37Y90", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y93": { + "bits": {}, + "grid_x": 96, + "grid_y": 111, + "segment": "SEG_BRAM3_R_X37Y90", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y94": { + "bits": {}, + "grid_x": 96, + "grid_y": 110, + "segment": "SEG_BRAM4_R_X37Y90", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y95": { + "bits": {}, + "grid_x": 96, + "grid_y": 109, + "segment": "SEG_BRAM0_R_X37Y95", + "segment_type": "bram0_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y96": { + "bits": {}, + "grid_x": 96, + "grid_y": 108, + "segment": "SEG_BRAM1_R_X37Y95", + "segment_type": "bram1_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y97": { + "bits": {}, + "grid_x": 96, + "grid_y": 107, + "segment": "SEG_BRAM2_R_X37Y95", + "segment_type": "bram2_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y98": { + "bits": {}, + "grid_x": 96, + "grid_y": 106, + "segment": "SEG_BRAM3_R_X37Y95", + "segment_type": "bram3_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_INT_INTERFACE_R_X37Y99": { + "bits": {}, + "grid_x": 96, + "grid_y": 105, + "segment": "SEG_BRAM4_R_X37Y95", + "segment_type": "bram4_r", + "sites": {}, + "type": "BRAM_INT_INTERFACE_R" + }, + "BRAM_L_X30Y0": { + "bits": {}, + "grid_x": 77, + "grid_y": 207, + "segment": "SEG_BRAM0_L_X30Y0", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y0": "FIFO18E1", + "RAMB18_X2Y1": "RAMB18E1", + "RAMB36_X2Y0": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y10": { + "bits": {}, + "grid_x": 77, + "grid_y": 197, + "segment": "SEG_BRAM0_L_X30Y10", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y4": "FIFO18E1", + "RAMB18_X2Y5": "RAMB18E1", + "RAMB36_X2Y2": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y125": { + "bits": {}, + "grid_x": 77, + "grid_y": 77, + "segment": "SEG_BRAM0_L_X30Y125", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y50": "FIFO18E1", + "RAMB18_X2Y51": "RAMB18E1", + "RAMB36_X2Y25": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y130": { + "bits": {}, + "grid_x": 77, + "grid_y": 72, + "segment": "SEG_BRAM0_L_X30Y130", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y52": "FIFO18E1", + "RAMB18_X2Y53": "RAMB18E1", + "RAMB36_X2Y26": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y135": { + "bits": {}, + "grid_x": 77, + "grid_y": 67, + "segment": "SEG_BRAM0_L_X30Y135", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y54": "FIFO18E1", + "RAMB18_X2Y55": "RAMB18E1", + "RAMB36_X2Y27": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y140": { + "bits": {}, + "grid_x": 77, + "grid_y": 62, + "segment": "SEG_BRAM0_L_X30Y140", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y56": "FIFO18E1", + "RAMB18_X2Y57": "RAMB18E1", + "RAMB36_X2Y28": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y145": { + "bits": {}, + "grid_x": 77, + "grid_y": 57, + "segment": "SEG_BRAM0_L_X30Y145", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y58": "FIFO18E1", + "RAMB18_X2Y59": "RAMB18E1", + "RAMB36_X2Y29": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y15": { + "bits": {}, + "grid_x": 77, + "grid_y": 192, + "segment": "SEG_BRAM0_L_X30Y15", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y6": "FIFO18E1", + "RAMB18_X2Y7": "RAMB18E1", + "RAMB36_X2Y3": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y150": { + "bits": {}, + "grid_x": 77, + "grid_y": 51, + "segment": "SEG_BRAM0_L_X30Y150", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y60": "FIFO18E1", + "RAMB18_X2Y61": "RAMB18E1", + "RAMB36_X2Y30": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y155": { + "bits": {}, + "grid_x": 77, + "grid_y": 46, + "segment": "SEG_BRAM0_L_X30Y155", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y62": "FIFO18E1", + "RAMB18_X2Y63": "RAMB18E1", + "RAMB36_X2Y31": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y160": { + "bits": {}, + "grid_x": 77, + "grid_y": 41, + "segment": "SEG_BRAM0_L_X30Y160", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y64": "FIFO18E1", + "RAMB18_X2Y65": "RAMB18E1", + "RAMB36_X2Y32": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y165": { + "bits": {}, + "grid_x": 77, + "grid_y": 36, + "segment": "SEG_BRAM0_L_X30Y165", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y66": "FIFO18E1", + "RAMB18_X2Y67": "RAMB18E1", + "RAMB36_X2Y33": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y170": { + "bits": {}, + "grid_x": 77, + "grid_y": 31, + "segment": "SEG_BRAM0_L_X30Y170", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y68": "FIFO18E1", + "RAMB18_X2Y69": "RAMB18E1", + "RAMB36_X2Y34": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y175": { + "bits": {}, + "grid_x": 77, + "grid_y": 25, + "segment": "SEG_BRAM0_L_X30Y175", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y70": "FIFO18E1", + "RAMB18_X2Y71": "RAMB18E1", + "RAMB36_X2Y35": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y180": { + "bits": {}, + "grid_x": 77, + "grid_y": 20, + "segment": "SEG_BRAM0_L_X30Y180", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y72": "FIFO18E1", + "RAMB18_X2Y73": "RAMB18E1", + "RAMB36_X2Y36": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y185": { + "bits": {}, + "grid_x": 77, + "grid_y": 15, + "segment": "SEG_BRAM0_L_X30Y185", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y74": "FIFO18E1", + "RAMB18_X2Y75": "RAMB18E1", + "RAMB36_X2Y37": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y190": { + "bits": {}, + "grid_x": 77, + "grid_y": 10, + "segment": "SEG_BRAM0_L_X30Y190", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y76": "FIFO18E1", + "RAMB18_X2Y77": "RAMB18E1", + "RAMB36_X2Y38": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y195": { + "bits": {}, + "grid_x": 77, + "grid_y": 5, + "segment": "SEG_BRAM0_L_X30Y195", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y78": "FIFO18E1", + "RAMB18_X2Y79": "RAMB18E1", + "RAMB36_X2Y39": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y20": { + "bits": {}, + "grid_x": 77, + "grid_y": 187, + "segment": "SEG_BRAM0_L_X30Y20", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y8": "FIFO18E1", + "RAMB18_X2Y9": "RAMB18E1", + "RAMB36_X2Y4": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y25": { + "bits": {}, + "grid_x": 77, + "grid_y": 181, + "segment": "SEG_BRAM0_L_X30Y25", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y10": "FIFO18E1", + "RAMB18_X2Y11": "RAMB18E1", + "RAMB36_X2Y5": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y30": { + "bits": {}, + "grid_x": 77, + "grid_y": 176, + "segment": "SEG_BRAM0_L_X30Y30", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y12": "FIFO18E1", + "RAMB18_X2Y13": "RAMB18E1", + "RAMB36_X2Y6": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y35": { + "bits": {}, + "grid_x": 77, + "grid_y": 171, + "segment": "SEG_BRAM0_L_X30Y35", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y14": "FIFO18E1", + "RAMB18_X2Y15": "RAMB18E1", + "RAMB36_X2Y7": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y40": { + "bits": {}, + "grid_x": 77, + "grid_y": 166, + "segment": "SEG_BRAM0_L_X30Y40", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y16": "FIFO18E1", + "RAMB18_X2Y17": "RAMB18E1", + "RAMB36_X2Y8": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y45": { + "bits": {}, + "grid_x": 77, + "grid_y": 161, + "segment": "SEG_BRAM0_L_X30Y45", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y18": "FIFO18E1", + "RAMB18_X2Y19": "RAMB18E1", + "RAMB36_X2Y9": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y5": { + "bits": {}, + "grid_x": 77, + "grid_y": 202, + "segment": "SEG_BRAM0_L_X30Y5", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y2": "FIFO18E1", + "RAMB18_X2Y3": "RAMB18E1", + "RAMB36_X2Y1": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y50": { + "bits": {}, + "grid_x": 77, + "grid_y": 155, + "segment": "SEG_BRAM0_L_X30Y50", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y20": "FIFO18E1", + "RAMB18_X2Y21": "RAMB18E1", + "RAMB36_X2Y10": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y55": { + "bits": {}, + "grid_x": 77, + "grid_y": 150, + "segment": "SEG_BRAM0_L_X30Y55", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y22": "FIFO18E1", + "RAMB18_X2Y23": "RAMB18E1", + "RAMB36_X2Y11": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y60": { + "bits": {}, + "grid_x": 77, + "grid_y": 145, + "segment": "SEG_BRAM0_L_X30Y60", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y24": "FIFO18E1", + "RAMB18_X2Y25": "RAMB18E1", + "RAMB36_X2Y12": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y65": { + "bits": {}, + "grid_x": 77, + "grid_y": 140, + "segment": "SEG_BRAM0_L_X30Y65", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y26": "FIFO18E1", + "RAMB18_X2Y27": "RAMB18E1", + "RAMB36_X2Y13": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y70": { + "bits": {}, + "grid_x": 77, + "grid_y": 135, + "segment": "SEG_BRAM0_L_X30Y70", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y28": "FIFO18E1", + "RAMB18_X2Y29": "RAMB18E1", + "RAMB36_X2Y14": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y75": { + "bits": {}, + "grid_x": 77, + "grid_y": 129, + "segment": "SEG_BRAM0_L_X30Y75", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y30": "FIFO18E1", + "RAMB18_X2Y31": "RAMB18E1", + "RAMB36_X2Y15": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y80": { + "bits": {}, + "grid_x": 77, + "grid_y": 124, + "segment": "SEG_BRAM0_L_X30Y80", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y32": "FIFO18E1", + "RAMB18_X2Y33": "RAMB18E1", + "RAMB36_X2Y16": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y85": { + "bits": {}, + "grid_x": 77, + "grid_y": 119, + "segment": "SEG_BRAM0_L_X30Y85", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y34": "FIFO18E1", + "RAMB18_X2Y35": "RAMB18E1", + "RAMB36_X2Y17": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y90": { + "bits": {}, + "grid_x": 77, + "grid_y": 114, + "segment": "SEG_BRAM0_L_X30Y90", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y36": "FIFO18E1", + "RAMB18_X2Y37": "RAMB18E1", + "RAMB36_X2Y18": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X30Y95": { + "bits": {}, + "grid_x": 77, + "grid_y": 109, + "segment": "SEG_BRAM0_L_X30Y95", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X2Y38": "FIFO18E1", + "RAMB18_X2Y39": "RAMB18E1", + "RAMB36_X2Y19": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y0": { + "bits": {}, + "grid_x": 19, + "grid_y": 207, + "segment": "SEG_BRAM0_L_X6Y0", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y0": "FIFO18E1", + "RAMB18_X0Y1": "RAMB18E1", + "RAMB36_X0Y0": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y10": { + "bits": {}, + "grid_x": 19, + "grid_y": 197, + "segment": "SEG_BRAM0_L_X6Y10", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y4": "FIFO18E1", + "RAMB18_X0Y5": "RAMB18E1", + "RAMB36_X0Y2": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y100": { + "bits": {}, + "grid_x": 19, + "grid_y": 103, + "segment": "SEG_BRAM0_L_X6Y100", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y40": "FIFO18E1", + "RAMB18_X0Y41": "RAMB18E1", + "RAMB36_X0Y20": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y105": { + "bits": {}, + "grid_x": 19, + "grid_y": 98, + "segment": "SEG_BRAM0_L_X6Y105", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y42": "FIFO18E1", + "RAMB18_X0Y43": "RAMB18E1", + "RAMB36_X0Y21": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y110": { + "bits": {}, + "grid_x": 19, + "grid_y": 93, + "segment": "SEG_BRAM0_L_X6Y110", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y44": "FIFO18E1", + "RAMB18_X0Y45": "RAMB18E1", + "RAMB36_X0Y22": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y115": { + "bits": {}, + "grid_x": 19, + "grid_y": 88, + "segment": "SEG_BRAM0_L_X6Y115", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y46": "FIFO18E1", + "RAMB18_X0Y47": "RAMB18E1", + "RAMB36_X0Y23": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y120": { + "bits": {}, + "grid_x": 19, + "grid_y": 83, + "segment": "SEG_BRAM0_L_X6Y120", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y48": "FIFO18E1", + "RAMB18_X0Y49": "RAMB18E1", + "RAMB36_X0Y24": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y125": { + "bits": {}, + "grid_x": 19, + "grid_y": 77, + "segment": "SEG_BRAM0_L_X6Y125", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y50": "FIFO18E1", + "RAMB18_X0Y51": "RAMB18E1", + "RAMB36_X0Y25": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y130": { + "bits": {}, + "grid_x": 19, + "grid_y": 72, + "segment": "SEG_BRAM0_L_X6Y130", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y52": "FIFO18E1", + "RAMB18_X0Y53": "RAMB18E1", + "RAMB36_X0Y26": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y135": { + "bits": {}, + "grid_x": 19, + "grid_y": 67, + "segment": "SEG_BRAM0_L_X6Y135", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y54": "FIFO18E1", + "RAMB18_X0Y55": "RAMB18E1", + "RAMB36_X0Y27": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y140": { + "bits": {}, + "grid_x": 19, + "grid_y": 62, + "segment": "SEG_BRAM0_L_X6Y140", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y56": "FIFO18E1", + "RAMB18_X0Y57": "RAMB18E1", + "RAMB36_X0Y28": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y145": { + "bits": {}, + "grid_x": 19, + "grid_y": 57, + "segment": "SEG_BRAM0_L_X6Y145", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y58": "FIFO18E1", + "RAMB18_X0Y59": "RAMB18E1", + "RAMB36_X0Y29": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y15": { + "bits": {}, + "grid_x": 19, + "grid_y": 192, + "segment": "SEG_BRAM0_L_X6Y15", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y6": "FIFO18E1", + "RAMB18_X0Y7": "RAMB18E1", + "RAMB36_X0Y3": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y150": { + "bits": {}, + "grid_x": 19, + "grid_y": 51, + "segment": "SEG_BRAM0_L_X6Y150", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y60": "FIFO18E1", + "RAMB18_X0Y61": "RAMB18E1", + "RAMB36_X0Y30": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y155": { + "bits": {}, + "grid_x": 19, + "grid_y": 46, + "segment": "SEG_BRAM0_L_X6Y155", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y62": "FIFO18E1", + "RAMB18_X0Y63": "RAMB18E1", + "RAMB36_X0Y31": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y160": { + "bits": {}, + "grid_x": 19, + "grid_y": 41, + "segment": "SEG_BRAM0_L_X6Y160", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y64": "FIFO18E1", + "RAMB18_X0Y65": "RAMB18E1", + "RAMB36_X0Y32": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y165": { + "bits": {}, + "grid_x": 19, + "grid_y": 36, + "segment": "SEG_BRAM0_L_X6Y165", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y66": "FIFO18E1", + "RAMB18_X0Y67": "RAMB18E1", + "RAMB36_X0Y33": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y170": { + "bits": {}, + "grid_x": 19, + "grid_y": 31, + "segment": "SEG_BRAM0_L_X6Y170", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y68": "FIFO18E1", + "RAMB18_X0Y69": "RAMB18E1", + "RAMB36_X0Y34": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y175": { + "bits": {}, + "grid_x": 19, + "grid_y": 25, + "segment": "SEG_BRAM0_L_X6Y175", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y70": "FIFO18E1", + "RAMB18_X0Y71": "RAMB18E1", + "RAMB36_X0Y35": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y180": { + "bits": {}, + "grid_x": 19, + "grid_y": 20, + "segment": "SEG_BRAM0_L_X6Y180", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y72": "FIFO18E1", + "RAMB18_X0Y73": "RAMB18E1", + "RAMB36_X0Y36": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y185": { + "bits": {}, + "grid_x": 19, + "grid_y": 15, + "segment": "SEG_BRAM0_L_X6Y185", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y74": "FIFO18E1", + "RAMB18_X0Y75": "RAMB18E1", + "RAMB36_X0Y37": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y190": { + "bits": {}, + "grid_x": 19, + "grid_y": 10, + "segment": "SEG_BRAM0_L_X6Y190", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y76": "FIFO18E1", + "RAMB18_X0Y77": "RAMB18E1", + "RAMB36_X0Y38": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y195": { + "bits": {}, + "grid_x": 19, + "grid_y": 5, + "segment": "SEG_BRAM0_L_X6Y195", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y78": "FIFO18E1", + "RAMB18_X0Y79": "RAMB18E1", + "RAMB36_X0Y39": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y20": { + "bits": {}, + "grid_x": 19, + "grid_y": 187, + "segment": "SEG_BRAM0_L_X6Y20", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y8": "FIFO18E1", + "RAMB18_X0Y9": "RAMB18E1", + "RAMB36_X0Y4": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y25": { + "bits": {}, + "grid_x": 19, + "grid_y": 181, + "segment": "SEG_BRAM0_L_X6Y25", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y10": "FIFO18E1", + "RAMB18_X0Y11": "RAMB18E1", + "RAMB36_X0Y5": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y30": { + "bits": {}, + "grid_x": 19, + "grid_y": 176, + "segment": "SEG_BRAM0_L_X6Y30", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y12": "FIFO18E1", + "RAMB18_X0Y13": "RAMB18E1", + "RAMB36_X0Y6": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y35": { + "bits": {}, + "grid_x": 19, + "grid_y": 171, + "segment": "SEG_BRAM0_L_X6Y35", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y14": "FIFO18E1", + "RAMB18_X0Y15": "RAMB18E1", + "RAMB36_X0Y7": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y40": { + "bits": {}, + "grid_x": 19, + "grid_y": 166, + "segment": "SEG_BRAM0_L_X6Y40", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y16": "FIFO18E1", + "RAMB18_X0Y17": "RAMB18E1", + "RAMB36_X0Y8": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y45": { + "bits": {}, + "grid_x": 19, + "grid_y": 161, + "segment": "SEG_BRAM0_L_X6Y45", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y18": "FIFO18E1", + "RAMB18_X0Y19": "RAMB18E1", + "RAMB36_X0Y9": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y5": { + "bits": {}, + "grid_x": 19, + "grid_y": 202, + "segment": "SEG_BRAM0_L_X6Y5", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y2": "FIFO18E1", + "RAMB18_X0Y3": "RAMB18E1", + "RAMB36_X0Y1": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 10, + "offset": 0, + "words": 10 + } + }, + "grid_x": 19, + "grid_y": 155, + "segment": "SEG_BRAM0_L_X6Y50", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y20": "FIFO18E1", + "RAMB18_X0Y21": "RAMB18E1", + "RAMB36_X0Y10": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 10, + "offset": 10, + "words": 10 + } + }, + "grid_x": 19, + "grid_y": 150, + "segment": "SEG_BRAM0_L_X6Y55", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y22": "FIFO18E1", + "RAMB18_X0Y23": "RAMB18E1", + "RAMB36_X0Y11": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 10, + "offset": 20, + "words": 10 + } + }, + "grid_x": 19, + "grid_y": 145, + "segment": "SEG_BRAM0_L_X6Y60", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y24": "FIFO18E1", + "RAMB18_X0Y25": "RAMB18E1", + "RAMB36_X0Y12": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 10, + "offset": 30, + "words": 10 + } + }, + "grid_x": 19, + "grid_y": 140, + "segment": "SEG_BRAM0_L_X6Y65", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y26": "FIFO18E1", + "RAMB18_X0Y27": "RAMB18E1", + "RAMB36_X0Y13": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 10, + "offset": 40, + "words": 10 + } + }, + "grid_x": 19, + "grid_y": 135, + "segment": "SEG_BRAM0_L_X6Y70", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y28": "FIFO18E1", + "RAMB18_X0Y29": "RAMB18E1", + "RAMB36_X0Y14": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 10, + "offset": 51, + "words": 10 + } + }, + "grid_x": 19, + "grid_y": 129, + "segment": "SEG_BRAM0_L_X6Y75", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y30": "FIFO18E1", + "RAMB18_X0Y31": "RAMB18E1", + "RAMB36_X0Y15": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 10, + "offset": 61, + "words": 10 + } + }, + "grid_x": 19, + "grid_y": 124, + "segment": "SEG_BRAM0_L_X6Y80", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y32": "FIFO18E1", + "RAMB18_X0Y33": "RAMB18E1", + "RAMB36_X0Y16": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 10, + "offset": 71, + "words": 10 + } + }, + "grid_x": 19, + "grid_y": 119, + "segment": "SEG_BRAM0_L_X6Y85", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y34": "FIFO18E1", + "RAMB18_X0Y35": "RAMB18E1", + "RAMB36_X0Y17": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 10, + "offset": 81, + "words": 10 + } + }, + "grid_x": 19, + "grid_y": 114, + "segment": "SEG_BRAM0_L_X6Y90", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y36": "FIFO18E1", + "RAMB18_X0Y37": "RAMB18E1", + "RAMB36_X0Y18": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_L_X6Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 10, + "offset": 91, + "words": 10 + } + }, + "grid_x": 19, + "grid_y": 109, + "segment": "SEG_BRAM0_L_X6Y95", + "segment_type": "bram0_l", + "sites": { + "RAMB18_X0Y38": "FIFO18E1", + "RAMB18_X0Y39": "RAMB18E1", + "RAMB36_X0Y19": "RAMBFIFO36E1" + }, + "type": "BRAM_L" + }, + "BRAM_R_X17Y0": { + "bits": {}, + "grid_x": 48, + "grid_y": 207, + "segment": "SEG_BRAM0_R_X17Y0", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y0": "FIFO18E1", + "RAMB18_X1Y1": "RAMB18E1", + "RAMB36_X1Y0": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y10": { + "bits": {}, + "grid_x": 48, + "grid_y": 197, + "segment": "SEG_BRAM0_R_X17Y10", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y4": "FIFO18E1", + "RAMB18_X1Y5": "RAMB18E1", + "RAMB36_X1Y2": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y100": { + "bits": {}, + "grid_x": 48, + "grid_y": 103, + "segment": "SEG_BRAM0_R_X17Y100", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y40": "FIFO18E1", + "RAMB18_X1Y41": "RAMB18E1", + "RAMB36_X1Y20": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y105": { + "bits": {}, + "grid_x": 48, + "grid_y": 98, + "segment": "SEG_BRAM0_R_X17Y105", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y42": "FIFO18E1", + "RAMB18_X1Y43": "RAMB18E1", + "RAMB36_X1Y21": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y110": { + "bits": {}, + "grid_x": 48, + "grid_y": 93, + "segment": "SEG_BRAM0_R_X17Y110", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y44": "FIFO18E1", + "RAMB18_X1Y45": "RAMB18E1", + "RAMB36_X1Y22": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y115": { + "bits": {}, + "grid_x": 48, + "grid_y": 88, + "segment": "SEG_BRAM0_R_X17Y115", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y46": "FIFO18E1", + "RAMB18_X1Y47": "RAMB18E1", + "RAMB36_X1Y23": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y120": { + "bits": {}, + "grid_x": 48, + "grid_y": 83, + "segment": "SEG_BRAM0_R_X17Y120", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y48": "FIFO18E1", + "RAMB18_X1Y49": "RAMB18E1", + "RAMB36_X1Y24": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y125": { + "bits": {}, + "grid_x": 48, + "grid_y": 77, + "segment": "SEG_BRAM0_R_X17Y125", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y50": "FIFO18E1", + "RAMB18_X1Y51": "RAMB18E1", + "RAMB36_X1Y25": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y130": { + "bits": {}, + "grid_x": 48, + "grid_y": 72, + "segment": "SEG_BRAM0_R_X17Y130", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y52": "FIFO18E1", + "RAMB18_X1Y53": "RAMB18E1", + "RAMB36_X1Y26": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y135": { + "bits": {}, + "grid_x": 48, + "grid_y": 67, + "segment": "SEG_BRAM0_R_X17Y135", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y54": "FIFO18E1", + "RAMB18_X1Y55": "RAMB18E1", + "RAMB36_X1Y27": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y140": { + "bits": {}, + "grid_x": 48, + "grid_y": 62, + "segment": "SEG_BRAM0_R_X17Y140", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y56": "FIFO18E1", + "RAMB18_X1Y57": "RAMB18E1", + "RAMB36_X1Y28": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y145": { + "bits": {}, + "grid_x": 48, + "grid_y": 57, + "segment": "SEG_BRAM0_R_X17Y145", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y58": "FIFO18E1", + "RAMB18_X1Y59": "RAMB18E1", + "RAMB36_X1Y29": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y15": { + "bits": {}, + "grid_x": 48, + "grid_y": 192, + "segment": "SEG_BRAM0_R_X17Y15", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y6": "FIFO18E1", + "RAMB18_X1Y7": "RAMB18E1", + "RAMB36_X1Y3": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y150": { + "bits": {}, + "grid_x": 48, + "grid_y": 51, + "segment": "SEG_BRAM0_R_X17Y150", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y60": "FIFO18E1", + "RAMB18_X1Y61": "RAMB18E1", + "RAMB36_X1Y30": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y155": { + "bits": {}, + "grid_x": 48, + "grid_y": 46, + "segment": "SEG_BRAM0_R_X17Y155", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y62": "FIFO18E1", + "RAMB18_X1Y63": "RAMB18E1", + "RAMB36_X1Y31": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y160": { + "bits": {}, + "grid_x": 48, + "grid_y": 41, + "segment": "SEG_BRAM0_R_X17Y160", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y64": "FIFO18E1", + "RAMB18_X1Y65": "RAMB18E1", + "RAMB36_X1Y32": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y165": { + "bits": {}, + "grid_x": 48, + "grid_y": 36, + "segment": "SEG_BRAM0_R_X17Y165", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y66": "FIFO18E1", + "RAMB18_X1Y67": "RAMB18E1", + "RAMB36_X1Y33": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y170": { + "bits": {}, + "grid_x": 48, + "grid_y": 31, + "segment": "SEG_BRAM0_R_X17Y170", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y68": "FIFO18E1", + "RAMB18_X1Y69": "RAMB18E1", + "RAMB36_X1Y34": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y175": { + "bits": {}, + "grid_x": 48, + "grid_y": 25, + "segment": "SEG_BRAM0_R_X17Y175", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y70": "FIFO18E1", + "RAMB18_X1Y71": "RAMB18E1", + "RAMB36_X1Y35": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y180": { + "bits": {}, + "grid_x": 48, + "grid_y": 20, + "segment": "SEG_BRAM0_R_X17Y180", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y72": "FIFO18E1", + "RAMB18_X1Y73": "RAMB18E1", + "RAMB36_X1Y36": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y185": { + "bits": {}, + "grid_x": 48, + "grid_y": 15, + "segment": "SEG_BRAM0_R_X17Y185", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y74": "FIFO18E1", + "RAMB18_X1Y75": "RAMB18E1", + "RAMB36_X1Y37": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y190": { + "bits": {}, + "grid_x": 48, + "grid_y": 10, + "segment": "SEG_BRAM0_R_X17Y190", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y76": "FIFO18E1", + "RAMB18_X1Y77": "RAMB18E1", + "RAMB36_X1Y38": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y195": { + "bits": {}, + "grid_x": 48, + "grid_y": 5, + "segment": "SEG_BRAM0_R_X17Y195", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y78": "FIFO18E1", + "RAMB18_X1Y79": "RAMB18E1", + "RAMB36_X1Y39": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y20": { + "bits": {}, + "grid_x": 48, + "grid_y": 187, + "segment": "SEG_BRAM0_R_X17Y20", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y8": "FIFO18E1", + "RAMB18_X1Y9": "RAMB18E1", + "RAMB36_X1Y4": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y25": { + "bits": {}, + "grid_x": 48, + "grid_y": 181, + "segment": "SEG_BRAM0_R_X17Y25", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y10": "FIFO18E1", + "RAMB18_X1Y11": "RAMB18E1", + "RAMB36_X1Y5": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y30": { + "bits": {}, + "grid_x": 48, + "grid_y": 176, + "segment": "SEG_BRAM0_R_X17Y30", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y12": "FIFO18E1", + "RAMB18_X1Y13": "RAMB18E1", + "RAMB36_X1Y6": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y35": { + "bits": {}, + "grid_x": 48, + "grid_y": 171, + "segment": "SEG_BRAM0_R_X17Y35", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y14": "FIFO18E1", + "RAMB18_X1Y15": "RAMB18E1", + "RAMB36_X1Y7": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y40": { + "bits": {}, + "grid_x": 48, + "grid_y": 166, + "segment": "SEG_BRAM0_R_X17Y40", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y16": "FIFO18E1", + "RAMB18_X1Y17": "RAMB18E1", + "RAMB36_X1Y8": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y45": { + "bits": {}, + "grid_x": 48, + "grid_y": 161, + "segment": "SEG_BRAM0_R_X17Y45", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y18": "FIFO18E1", + "RAMB18_X1Y19": "RAMB18E1", + "RAMB36_X1Y9": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y5": { + "bits": {}, + "grid_x": 48, + "grid_y": 202, + "segment": "SEG_BRAM0_R_X17Y5", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y2": "FIFO18E1", + "RAMB18_X1Y3": "RAMB18E1", + "RAMB36_X1Y1": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y50": { + "bits": {}, + "grid_x": 48, + "grid_y": 155, + "segment": "SEG_BRAM0_R_X17Y50", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y20": "FIFO18E1", + "RAMB18_X1Y21": "RAMB18E1", + "RAMB36_X1Y10": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y55": { + "bits": {}, + "grid_x": 48, + "grid_y": 150, + "segment": "SEG_BRAM0_R_X17Y55", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y22": "FIFO18E1", + "RAMB18_X1Y23": "RAMB18E1", + "RAMB36_X1Y11": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y60": { + "bits": {}, + "grid_x": 48, + "grid_y": 145, + "segment": "SEG_BRAM0_R_X17Y60", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y24": "FIFO18E1", + "RAMB18_X1Y25": "RAMB18E1", + "RAMB36_X1Y12": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y65": { + "bits": {}, + "grid_x": 48, + "grid_y": 140, + "segment": "SEG_BRAM0_R_X17Y65", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y26": "FIFO18E1", + "RAMB18_X1Y27": "RAMB18E1", + "RAMB36_X1Y13": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y70": { + "bits": {}, + "grid_x": 48, + "grid_y": 135, + "segment": "SEG_BRAM0_R_X17Y70", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y28": "FIFO18E1", + "RAMB18_X1Y29": "RAMB18E1", + "RAMB36_X1Y14": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y75": { + "bits": {}, + "grid_x": 48, + "grid_y": 129, + "segment": "SEG_BRAM0_R_X17Y75", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y30": "FIFO18E1", + "RAMB18_X1Y31": "RAMB18E1", + "RAMB36_X1Y15": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y80": { + "bits": {}, + "grid_x": 48, + "grid_y": 124, + "segment": "SEG_BRAM0_R_X17Y80", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y32": "FIFO18E1", + "RAMB18_X1Y33": "RAMB18E1", + "RAMB36_X1Y16": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y85": { + "bits": {}, + "grid_x": 48, + "grid_y": 119, + "segment": "SEG_BRAM0_R_X17Y85", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y34": "FIFO18E1", + "RAMB18_X1Y35": "RAMB18E1", + "RAMB36_X1Y17": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y90": { + "bits": {}, + "grid_x": 48, + "grid_y": 114, + "segment": "SEG_BRAM0_R_X17Y90", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y36": "FIFO18E1", + "RAMB18_X1Y37": "RAMB18E1", + "RAMB36_X1Y18": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X17Y95": { + "bits": {}, + "grid_x": 48, + "grid_y": 109, + "segment": "SEG_BRAM0_R_X17Y95", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X1Y38": "FIFO18E1", + "RAMB18_X1Y39": "RAMB18E1", + "RAMB36_X1Y19": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y0": { + "bits": {}, + "grid_x": 97, + "grid_y": 207, + "segment": "SEG_BRAM0_R_X37Y0", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y0": "FIFO18E1", + "RAMB18_X3Y1": "RAMB18E1", + "RAMB36_X3Y0": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y10": { + "bits": {}, + "grid_x": 97, + "grid_y": 197, + "segment": "SEG_BRAM0_R_X37Y10", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y4": "FIFO18E1", + "RAMB18_X3Y5": "RAMB18E1", + "RAMB36_X3Y2": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y15": { + "bits": {}, + "grid_x": 97, + "grid_y": 192, + "segment": "SEG_BRAM0_R_X37Y15", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y6": "FIFO18E1", + "RAMB18_X3Y7": "RAMB18E1", + "RAMB36_X3Y3": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y20": { + "bits": {}, + "grid_x": 97, + "grid_y": 187, + "segment": "SEG_BRAM0_R_X37Y20", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y8": "FIFO18E1", + "RAMB18_X3Y9": "RAMB18E1", + "RAMB36_X3Y4": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y25": { + "bits": {}, + "grid_x": 97, + "grid_y": 181, + "segment": "SEG_BRAM0_R_X37Y25", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y10": "FIFO18E1", + "RAMB18_X3Y11": "RAMB18E1", + "RAMB36_X3Y5": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y30": { + "bits": {}, + "grid_x": 97, + "grid_y": 176, + "segment": "SEG_BRAM0_R_X37Y30", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y12": "FIFO18E1", + "RAMB18_X3Y13": "RAMB18E1", + "RAMB36_X3Y6": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y35": { + "bits": {}, + "grid_x": 97, + "grid_y": 171, + "segment": "SEG_BRAM0_R_X37Y35", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y14": "FIFO18E1", + "RAMB18_X3Y15": "RAMB18E1", + "RAMB36_X3Y7": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y40": { + "bits": {}, + "grid_x": 97, + "grid_y": 166, + "segment": "SEG_BRAM0_R_X37Y40", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y16": "FIFO18E1", + "RAMB18_X3Y17": "RAMB18E1", + "RAMB36_X3Y8": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y45": { + "bits": {}, + "grid_x": 97, + "grid_y": 161, + "segment": "SEG_BRAM0_R_X37Y45", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y18": "FIFO18E1", + "RAMB18_X3Y19": "RAMB18E1", + "RAMB36_X3Y9": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y5": { + "bits": {}, + "grid_x": 97, + "grid_y": 202, + "segment": "SEG_BRAM0_R_X37Y5", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y2": "FIFO18E1", + "RAMB18_X3Y3": "RAMB18E1", + "RAMB36_X3Y1": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y50": { + "bits": {}, + "grid_x": 97, + "grid_y": 155, + "segment": "SEG_BRAM0_R_X37Y50", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y20": "FIFO18E1", + "RAMB18_X3Y21": "RAMB18E1", + "RAMB36_X3Y10": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y55": { + "bits": {}, + "grid_x": 97, + "grid_y": 150, + "segment": "SEG_BRAM0_R_X37Y55", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y22": "FIFO18E1", + "RAMB18_X3Y23": "RAMB18E1", + "RAMB36_X3Y11": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y60": { + "bits": {}, + "grid_x": 97, + "grid_y": 145, + "segment": "SEG_BRAM0_R_X37Y60", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y24": "FIFO18E1", + "RAMB18_X3Y25": "RAMB18E1", + "RAMB36_X3Y12": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y65": { + "bits": {}, + "grid_x": 97, + "grid_y": 140, + "segment": "SEG_BRAM0_R_X37Y65", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y26": "FIFO18E1", + "RAMB18_X3Y27": "RAMB18E1", + "RAMB36_X3Y13": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y70": { + "bits": {}, + "grid_x": 97, + "grid_y": 135, + "segment": "SEG_BRAM0_R_X37Y70", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y28": "FIFO18E1", + "RAMB18_X3Y29": "RAMB18E1", + "RAMB36_X3Y14": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y75": { + "bits": {}, + "grid_x": 97, + "grid_y": 129, + "segment": "SEG_BRAM0_R_X37Y75", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y30": "FIFO18E1", + "RAMB18_X3Y31": "RAMB18E1", + "RAMB36_X3Y15": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y80": { + "bits": {}, + "grid_x": 97, + "grid_y": 124, + "segment": "SEG_BRAM0_R_X37Y80", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y32": "FIFO18E1", + "RAMB18_X3Y33": "RAMB18E1", + "RAMB36_X3Y16": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y85": { + "bits": {}, + "grid_x": 97, + "grid_y": 119, + "segment": "SEG_BRAM0_R_X37Y85", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y34": "FIFO18E1", + "RAMB18_X3Y35": "RAMB18E1", + "RAMB36_X3Y17": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y90": { + "bits": {}, + "grid_x": 97, + "grid_y": 114, + "segment": "SEG_BRAM0_R_X37Y90", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y36": "FIFO18E1", + "RAMB18_X3Y37": "RAMB18E1", + "RAMB36_X3Y18": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRAM_R_X37Y95": { + "bits": {}, + "grid_x": 97, + "grid_y": 109, + "segment": "SEG_BRAM0_R_X37Y95", + "segment_type": "bram0_r", + "sites": { + "RAMB18_X3Y38": "FIFO18E1", + "RAMB18_X3Y39": "RAMB18E1", + "RAMB36_X3Y19": "RAMBFIFO36E1" + }, + "type": "BRAM_R" + }, + "BRKH_BRAM_X19Y104": { + "bits": {}, + "grid_x": 19, + "grid_y": 104, + "sites": {}, + "type": "BRKH_BRAM" + }, + "BRKH_BRAM_X19Y156": { + "bits": {}, + "grid_x": 19, + "grid_y": 52, + "sites": {}, + "type": "BRKH_BRAM" + }, + "BRKH_BRAM_X19Y52": { + "bits": {}, + "grid_x": 19, + "grid_y": 156, + "sites": {}, + "type": "BRKH_BRAM" + }, + "BRKH_BRAM_X48Y104": { + "bits": {}, + "grid_x": 48, + "grid_y": 104, + "sites": {}, + "type": "BRKH_BRAM" + }, + "BRKH_BRAM_X48Y156": { + "bits": {}, + "grid_x": 48, + "grid_y": 52, + "sites": {}, + "type": "BRKH_BRAM" + }, + "BRKH_BRAM_X48Y52": { + "bits": {}, + "grid_x": 48, + "grid_y": 156, + "sites": {}, + "type": "BRKH_BRAM" + }, + "BRKH_BRAM_X77Y156": { + "bits": {}, + "grid_x": 77, + "grid_y": 52, + "sites": {}, + "type": "BRKH_BRAM" + }, + "BRKH_BRAM_X77Y52": { + "bits": {}, + "grid_x": 77, + "grid_y": 156, + "sites": {}, + "type": "BRKH_BRAM" + }, + "BRKH_BRAM_X97Y52": { + "bits": {}, + "grid_x": 97, + "grid_y": 156, + "sites": {}, + "type": "BRKH_BRAM" + }, + "BRKH_B_TERM_INT_X51Y156": { + "bits": {}, + "grid_x": 51, + "grid_y": 52, + "sites": {}, + "type": "BRKH_B_TERM_INT" + }, + "BRKH_B_TERM_INT_X52Y156": { + "bits": {}, + "grid_x": 52, + "grid_y": 52, + "sites": {}, + "type": "BRKH_B_TERM_INT" + }, + "BRKH_B_TERM_INT_X55Y156": { + "bits": {}, + "grid_x": 55, + "grid_y": 52, + "sites": {}, + "type": "BRKH_B_TERM_INT" + }, + "BRKH_B_TERM_INT_X56Y156": { + "bits": {}, + "grid_x": 56, + "grid_y": 52, + "sites": {}, + "type": "BRKH_B_TERM_INT" + }, + "BRKH_B_TERM_INT_X59Y156": { + "bits": {}, + "grid_x": 59, + "grid_y": 52, + "sites": {}, + "type": "BRKH_B_TERM_INT" + }, + "BRKH_B_TERM_INT_X60Y156": { + "bits": {}, + "grid_x": 60, + "grid_y": 52, + "sites": {}, + "type": "BRKH_B_TERM_INT" + }, + "BRKH_CLB_X10Y149": { + "bits": {}, + "grid_x": 30, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X10Y49": { + "bits": {}, + "grid_x": 30, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X10Y99": { + "bits": {}, + "grid_x": 30, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X11Y149": { + "bits": {}, + "grid_x": 33, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X11Y49": { + "bits": {}, + "grid_x": 33, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X11Y99": { + "bits": {}, + "grid_x": 33, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X12Y149": { + "bits": {}, + "grid_x": 34, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X12Y49": { + "bits": {}, + "grid_x": 34, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X12Y99": { + "bits": {}, + "grid_x": 34, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X13Y149": { + "bits": {}, + "grid_x": 37, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X13Y49": { + "bits": {}, + "grid_x": 37, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X13Y99": { + "bits": {}, + "grid_x": 37, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X15Y149": { + "bits": {}, + "grid_x": 43, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X15Y49": { + "bits": {}, + "grid_x": 43, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X15Y99": { + "bits": {}, + "grid_x": 43, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X16Y149": { + "bits": {}, + "grid_x": 44, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X16Y49": { + "bits": {}, + "grid_x": 44, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X16Y99": { + "bits": {}, + "grid_x": 44, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X26Y149": { + "bits": {}, + "grid_x": 69, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X26Y49": { + "bits": {}, + "grid_x": 69, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X26Y99": { + "bits": {}, + "grid_x": 69, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X27Y149": { + "bits": {}, + "grid_x": 72, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X27Y49": { + "bits": {}, + "grid_x": 72, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X28Y149": { + "bits": {}, + "grid_x": 73, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X28Y49": { + "bits": {}, + "grid_x": 73, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X29Y149": { + "bits": {}, + "grid_x": 76, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X29Y49": { + "bits": {}, + "grid_x": 76, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X2Y149": { + "bits": {}, + "grid_x": 10, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X2Y49": { + "bits": {}, + "grid_x": 10, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X2Y99": { + "bits": {}, + "grid_x": 10, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X31Y149": { + "bits": {}, + "grid_x": 81, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X31Y49": { + "bits": {}, + "grid_x": 81, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X31Y99": { + "bits": {}, + "grid_x": 81, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X32Y149": { + "bits": {}, + "grid_x": 83, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X32Y49": { + "bits": {}, + "grid_x": 83, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X32Y99": { + "bits": {}, + "grid_x": 83, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X34Y149": { + "bits": {}, + "grid_x": 88, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X34Y49": { + "bits": {}, + "grid_x": 88, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X34Y99": { + "bits": {}, + "grid_x": 88, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X35Y149": { + "bits": {}, + "grid_x": 91, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X35Y49": { + "bits": {}, + "grid_x": 91, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X35Y99": { + "bits": {}, + "grid_x": 91, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X36Y149": { + "bits": {}, + "grid_x": 93, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X36Y49": { + "bits": {}, + "grid_x": 93, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X36Y99": { + "bits": {}, + "grid_x": 93, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X38Y49": { + "bits": {}, + "grid_x": 99, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X39Y49": { + "bits": {}, + "grid_x": 102, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X3Y149": { + "bits": {}, + "grid_x": 13, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X3Y49": { + "bits": {}, + "grid_x": 13, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X3Y99": { + "bits": {}, + "grid_x": 13, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X40Y49": { + "bits": {}, + "grid_x": 103, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X41Y49": { + "bits": {}, + "grid_x": 106, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X4Y149": { + "bits": {}, + "grid_x": 14, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X4Y49": { + "bits": {}, + "grid_x": 14, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X4Y99": { + "bits": {}, + "grid_x": 14, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X5Y149": { + "bits": {}, + "grid_x": 17, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X5Y49": { + "bits": {}, + "grid_x": 17, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X5Y99": { + "bits": {}, + "grid_x": 17, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X7Y149": { + "bits": {}, + "grid_x": 23, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X7Y49": { + "bits": {}, + "grid_x": 23, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X7Y99": { + "bits": {}, + "grid_x": 23, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X8Y149": { + "bits": {}, + "grid_x": 24, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X8Y49": { + "bits": {}, + "grid_x": 24, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLB_X8Y99": { + "bits": {}, + "grid_x": 24, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLB" + }, + "BRKH_CLK_X67Y104": { + "bits": {}, + "grid_x": 67, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CLK" + }, + "BRKH_CLK_X67Y156": { + "bits": {}, + "grid_x": 67, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CLK" + }, + "BRKH_CLK_X67Y52": { + "bits": {}, + "grid_x": 67, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CLK" + }, + "BRKH_CMT_X108Y52": { + "bits": {}, + "grid_x": 108, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CMT" + }, + "BRKH_CMT_X8Y104": { + "bits": {}, + "grid_x": 8, + "grid_y": 104, + "sites": {}, + "type": "BRKH_CMT" + }, + "BRKH_CMT_X8Y156": { + "bits": {}, + "grid_x": 8, + "grid_y": 52, + "sites": {}, + "type": "BRKH_CMT" + }, + "BRKH_CMT_X8Y52": { + "bits": {}, + "grid_x": 8, + "grid_y": 156, + "sites": {}, + "type": "BRKH_CMT" + }, + "BRKH_DSP_L_X39Y104": { + "bits": {}, + "grid_x": 39, + "grid_y": 104, + "sites": {}, + "type": "BRKH_DSP_L" + }, + "BRKH_DSP_L_X39Y156": { + "bits": {}, + "grid_x": 39, + "grid_y": 52, + "sites": {}, + "type": "BRKH_DSP_L" + }, + "BRKH_DSP_L_X39Y52": { + "bits": {}, + "grid_x": 39, + "grid_y": 156, + "sites": {}, + "type": "BRKH_DSP_L" + }, + "BRKH_DSP_R_X28Y104": { + "bits": {}, + "grid_x": 28, + "grid_y": 104, + "sites": {}, + "type": "BRKH_DSP_R" + }, + "BRKH_DSP_R_X28Y156": { + "bits": {}, + "grid_x": 28, + "grid_y": 52, + "sites": {}, + "type": "BRKH_DSP_R" + }, + "BRKH_DSP_R_X28Y52": { + "bits": {}, + "grid_x": 28, + "grid_y": 156, + "sites": {}, + "type": "BRKH_DSP_R" + }, + "BRKH_DSP_R_X87Y104": { + "bits": {}, + "grid_x": 87, + "grid_y": 104, + "sites": {}, + "type": "BRKH_DSP_R" + }, + "BRKH_DSP_R_X87Y156": { + "bits": {}, + "grid_x": 87, + "grid_y": 52, + "sites": {}, + "type": "BRKH_DSP_R" + }, + "BRKH_DSP_R_X87Y52": { + "bits": {}, + "grid_x": 87, + "grid_y": 156, + "sites": {}, + "type": "BRKH_DSP_R" + }, + "BRKH_GTX_X38Y99": { + "bits": {}, + "grid_x": 99, + "grid_y": 104, + "sites": {}, + "type": "BRKH_GTX" + }, + "BRKH_GTX_X99Y156": { + "bits": {}, + "grid_x": 99, + "grid_y": 52, + "sites": {}, + "type": "BRKH_GTX" + }, + "BRKH_INT_X0Y149": { + "bits": {}, + "grid_x": 4, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X0Y49": { + "bits": {}, + "grid_x": 4, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X0Y99": { + "bits": {}, + "grid_x": 4, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X10Y149": { + "bits": {}, + "grid_x": 31, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X10Y49": { + "bits": {}, + "grid_x": 31, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X10Y99": { + "bits": {}, + "grid_x": 31, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X11Y149": { + "bits": {}, + "grid_x": 32, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X11Y49": { + "bits": {}, + "grid_x": 32, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X11Y99": { + "bits": {}, + "grid_x": 32, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X12Y149": { + "bits": {}, + "grid_x": 35, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X12Y49": { + "bits": {}, + "grid_x": 35, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X12Y99": { + "bits": {}, + "grid_x": 35, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X13Y149": { + "bits": {}, + "grid_x": 36, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X13Y49": { + "bits": {}, + "grid_x": 36, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X13Y99": { + "bits": {}, + "grid_x": 36, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X14Y149": { + "bits": {}, + "grid_x": 41, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X14Y49": { + "bits": {}, + "grid_x": 41, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X14Y99": { + "bits": {}, + "grid_x": 41, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X15Y149": { + "bits": {}, + "grid_x": 42, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X15Y49": { + "bits": {}, + "grid_x": 42, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X15Y99": { + "bits": {}, + "grid_x": 42, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X16Y149": { + "bits": {}, + "grid_x": 45, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X16Y49": { + "bits": {}, + "grid_x": 45, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X16Y99": { + "bits": {}, + "grid_x": 45, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X17Y149": { + "bits": {}, + "grid_x": 46, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X17Y49": { + "bits": {}, + "grid_x": 46, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X17Y99": { + "bits": {}, + "grid_x": 46, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X1Y149": { + "bits": {}, + "grid_x": 5, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X1Y49": { + "bits": {}, + "grid_x": 5, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X1Y99": { + "bits": {}, + "grid_x": 5, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X24Y149": { + "bits": {}, + "grid_x": 64, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X24Y49": { + "bits": {}, + "grid_x": 64, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X24Y99": { + "bits": {}, + "grid_x": 64, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X25Y149": { + "bits": {}, + "grid_x": 65, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X25Y49": { + "bits": {}, + "grid_x": 65, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X25Y99": { + "bits": {}, + "grid_x": 65, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X26Y149": { + "bits": {}, + "grid_x": 70, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X26Y49": { + "bits": {}, + "grid_x": 70, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X26Y99": { + "bits": {}, + "grid_x": 70, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X27Y149": { + "bits": {}, + "grid_x": 71, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X27Y49": { + "bits": {}, + "grid_x": 71, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X27Y99": { + "bits": {}, + "grid_x": 71, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X28Y149": { + "bits": {}, + "grid_x": 74, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X28Y49": { + "bits": {}, + "grid_x": 74, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X29Y149": { + "bits": {}, + "grid_x": 75, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X29Y49": { + "bits": {}, + "grid_x": 75, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X2Y149": { + "bits": {}, + "grid_x": 11, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X2Y49": { + "bits": {}, + "grid_x": 11, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X2Y99": { + "bits": {}, + "grid_x": 11, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X30Y149": { + "bits": {}, + "grid_x": 79, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X30Y49": { + "bits": {}, + "grid_x": 79, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X30Y99": { + "bits": {}, + "grid_x": 79, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X31Y149": { + "bits": {}, + "grid_x": 80, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X31Y49": { + "bits": {}, + "grid_x": 80, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X31Y99": { + "bits": {}, + "grid_x": 80, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X32Y149": { + "bits": {}, + "grid_x": 84, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X32Y49": { + "bits": {}, + "grid_x": 84, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X32Y99": { + "bits": {}, + "grid_x": 84, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X33Y149": { + "bits": {}, + "grid_x": 85, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X33Y49": { + "bits": {}, + "grid_x": 85, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X33Y99": { + "bits": {}, + "grid_x": 85, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X34Y149": { + "bits": {}, + "grid_x": 89, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X34Y49": { + "bits": {}, + "grid_x": 89, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X34Y99": { + "bits": {}, + "grid_x": 89, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X35Y149": { + "bits": {}, + "grid_x": 90, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X35Y49": { + "bits": {}, + "grid_x": 90, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X35Y99": { + "bits": {}, + "grid_x": 90, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X36Y149": { + "bits": {}, + "grid_x": 94, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X36Y49": { + "bits": {}, + "grid_x": 94, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X36Y99": { + "bits": {}, + "grid_x": 94, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X37Y149": { + "bits": {}, + "grid_x": 95, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X37Y49": { + "bits": {}, + "grid_x": 95, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X37Y99": { + "bits": {}, + "grid_x": 95, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X38Y49": { + "bits": {}, + "grid_x": 100, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X39Y49": { + "bits": {}, + "grid_x": 101, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X3Y149": { + "bits": {}, + "grid_x": 12, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X3Y49": { + "bits": {}, + "grid_x": 12, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X3Y99": { + "bits": {}, + "grid_x": 12, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X40Y49": { + "bits": {}, + "grid_x": 104, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X41Y49": { + "bits": {}, + "grid_x": 105, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X42Y49": { + "bits": {}, + "grid_x": 111, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X43Y49": { + "bits": {}, + "grid_x": 112, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X4Y149": { + "bits": {}, + "grid_x": 15, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X4Y49": { + "bits": {}, + "grid_x": 15, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X4Y99": { + "bits": {}, + "grid_x": 15, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X5Y149": { + "bits": {}, + "grid_x": 16, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X5Y49": { + "bits": {}, + "grid_x": 16, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X5Y99": { + "bits": {}, + "grid_x": 16, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X6Y149": { + "bits": {}, + "grid_x": 21, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X6Y49": { + "bits": {}, + "grid_x": 21, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X6Y99": { + "bits": {}, + "grid_x": 21, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X7Y149": { + "bits": {}, + "grid_x": 22, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X7Y49": { + "bits": {}, + "grid_x": 22, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X7Y99": { + "bits": {}, + "grid_x": 22, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X8Y149": { + "bits": {}, + "grid_x": 25, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X8Y49": { + "bits": {}, + "grid_x": 25, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X8Y99": { + "bits": {}, + "grid_x": 25, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X9Y149": { + "bits": {}, + "grid_x": 26, + "grid_y": 52, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X9Y49": { + "bits": {}, + "grid_x": 26, + "grid_y": 156, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_INT_X9Y99": { + "bits": {}, + "grid_x": 26, + "grid_y": 104, + "sites": {}, + "type": "BRKH_INT" + }, + "BRKH_TERM_INT_X18Y49": { + "bits": {}, + "grid_x": 51, + "grid_y": 156, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "BRKH_TERM_INT_X19Y49": { + "bits": {}, + "grid_x": 52, + "grid_y": 156, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "BRKH_TERM_INT_X20Y49": { + "bits": {}, + "grid_x": 55, + "grid_y": 156, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "BRKH_TERM_INT_X21Y49": { + "bits": {}, + "grid_x": 56, + "grid_y": 156, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "BRKH_TERM_INT_X22Y49": { + "bits": {}, + "grid_x": 59, + "grid_y": 156, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "BRKH_TERM_INT_X23Y49": { + "bits": {}, + "grid_x": 60, + "grid_y": 156, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "BRKH_TERM_INT_X28Y99": { + "bits": {}, + "grid_x": 74, + "grid_y": 104, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "BRKH_TERM_INT_X29Y99": { + "bits": {}, + "grid_x": 75, + "grid_y": 104, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "BRKH_TERM_INT_X38Y99": { + "bits": {}, + "grid_x": 100, + "grid_y": 104, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "BRKH_TERM_INT_X39Y99": { + "bits": {}, + "grid_x": 101, + "grid_y": 104, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "BRKH_TERM_INT_X40Y99": { + "bits": {}, + "grid_x": 104, + "grid_y": 104, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "BRKH_TERM_INT_X41Y99": { + "bits": {}, + "grid_x": 105, + "grid_y": 104, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "BRKH_TERM_INT_X42Y99": { + "bits": {}, + "grid_x": 111, + "grid_y": 104, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "BRKH_TERM_INT_X43Y99": { + "bits": {}, + "grid_x": 112, + "grid_y": 104, + "sites": {}, + "type": "BRKH_TERM_INT" + }, + "B_TERM_INT_X100Y0": { + "bits": {}, + "grid_x": 100, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X101Y0": { + "bits": {}, + "grid_x": 101, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X104Y0": { + "bits": {}, + "grid_x": 104, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X105Y0": { + "bits": {}, + "grid_x": 105, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X111Y0": { + "bits": {}, + "grid_x": 111, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X112Y0": { + "bits": {}, + "grid_x": 112, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X11Y0": { + "bits": {}, + "grid_x": 11, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X12Y0": { + "bits": {}, + "grid_x": 12, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X15Y0": { + "bits": {}, + "grid_x": 15, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X16Y0": { + "bits": {}, + "grid_x": 16, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X21Y0": { + "bits": {}, + "grid_x": 21, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X22Y0": { + "bits": {}, + "grid_x": 22, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X25Y0": { + "bits": {}, + "grid_x": 25, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X26Y0": { + "bits": {}, + "grid_x": 26, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X31Y0": { + "bits": {}, + "grid_x": 31, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X32Y0": { + "bits": {}, + "grid_x": 32, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X35Y0": { + "bits": {}, + "grid_x": 35, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X36Y0": { + "bits": {}, + "grid_x": 36, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X41Y0": { + "bits": {}, + "grid_x": 41, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X42Y0": { + "bits": {}, + "grid_x": 42, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X45Y0": { + "bits": {}, + "grid_x": 45, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X46Y0": { + "bits": {}, + "grid_x": 46, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X4Y0": { + "bits": {}, + "grid_x": 4, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X51Y0": { + "bits": {}, + "grid_x": 51, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X52Y0": { + "bits": {}, + "grid_x": 52, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X55Y0": { + "bits": {}, + "grid_x": 55, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X56Y0": { + "bits": {}, + "grid_x": 56, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X59Y0": { + "bits": {}, + "grid_x": 59, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X5Y0": { + "bits": {}, + "grid_x": 5, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X60Y0": { + "bits": {}, + "grid_x": 60, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X64Y0": { + "bits": {}, + "grid_x": 64, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X65Y0": { + "bits": {}, + "grid_x": 65, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X70Y0": { + "bits": {}, + "grid_x": 70, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X71Y0": { + "bits": {}, + "grid_x": 71, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X74Y0": { + "bits": {}, + "grid_x": 74, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X75Y0": { + "bits": {}, + "grid_x": 75, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X79Y0": { + "bits": {}, + "grid_x": 79, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X80Y0": { + "bits": {}, + "grid_x": 80, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X84Y0": { + "bits": {}, + "grid_x": 84, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X85Y0": { + "bits": {}, + "grid_x": 85, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X89Y0": { + "bits": {}, + "grid_x": 89, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X90Y0": { + "bits": {}, + "grid_x": 90, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X94Y0": { + "bits": {}, + "grid_x": 94, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "B_TERM_INT_X95Y0": { + "bits": {}, + "grid_x": 95, + "grid_y": 208, + "sites": {}, + "type": "B_TERM_INT" + }, + "CFG_CENTER_BOT_X61Y63": { + "bits": {}, + "grid_x": 61, + "grid_y": 145, + "sites": {}, + "type": "CFG_CENTER_BOT" + }, + "CFG_CENTER_MID_X61Y84": { + "bits": {}, + "grid_x": 61, + "grid_y": 124, + "sites": { + "BSCAN_X0Y0": "BSCAN", + "BSCAN_X0Y1": "BSCAN", + "BSCAN_X0Y2": "BSCAN", + "BSCAN_X0Y3": "BSCAN", + "CAPTURE_X0Y0": "CAPTURE", + "DCIRESET_X0Y0": "DCIRESET", + "FRAME_ECC_X0Y0": "FRAME_ECC", + "ICAP_X0Y0": "ICAP", + "ICAP_X0Y1": "ICAP", + "STARTUP_X0Y0": "STARTUP", + "USR_ACCESS_X0Y0": "USR_ACCESS" + }, + "type": "CFG_CENTER_MID" + }, + "CFG_CENTER_TOP_X61Y94": { + "bits": {}, + "grid_x": 61, + "grid_y": 114, + "sites": { + "DNA_PORT_X0Y0": "DNA_PORT", + "EFUSE_USR_X0Y0": "EFUSE_USR" + }, + "type": "CFG_CENTER_TOP" + }, + "CLBLL_L_X18Y0": { + "bits": {}, + "grid_x": 50, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X18Y0", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y0": "SLICEL", + "SLICE_X25Y0": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y1": { + "bits": {}, + "grid_x": 50, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X18Y1", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y1": "SLICEL", + "SLICE_X25Y1": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y10": { + "bits": {}, + "grid_x": 50, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X18Y10", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y10": "SLICEL", + "SLICE_X25Y10": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y11": { + "bits": {}, + "grid_x": 50, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X18Y11", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y11": "SLICEL", + "SLICE_X25Y11": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y12": { + "bits": {}, + "grid_x": 50, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X18Y12", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y12": "SLICEL", + "SLICE_X25Y12": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y13": { + "bits": {}, + "grid_x": 50, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X18Y13", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y13": "SLICEL", + "SLICE_X25Y13": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y14": { + "bits": {}, + "grid_x": 50, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X18Y14", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y14": "SLICEL", + "SLICE_X25Y14": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y15": { + "bits": {}, + "grid_x": 50, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X18Y15", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y15": "SLICEL", + "SLICE_X25Y15": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y150": { + "bits": {}, + "grid_x": 50, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X18Y150", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y150": "SLICEL", + "SLICE_X25Y150": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y151": { + "bits": {}, + "grid_x": 50, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X18Y151", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y151": "SLICEL", + "SLICE_X25Y151": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y152": { + "bits": {}, + "grid_x": 50, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X18Y152", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y152": "SLICEL", + "SLICE_X25Y152": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y153": { + "bits": {}, + "grid_x": 50, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X18Y153", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y153": "SLICEL", + "SLICE_X25Y153": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y154": { + "bits": {}, + "grid_x": 50, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X18Y154", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y154": "SLICEL", + "SLICE_X25Y154": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y155": { + "bits": {}, + "grid_x": 50, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X18Y155", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y155": "SLICEL", + "SLICE_X25Y155": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y156": { + "bits": {}, + "grid_x": 50, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X18Y156", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y156": "SLICEL", + "SLICE_X25Y156": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y157": { + "bits": {}, + "grid_x": 50, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X18Y157", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y157": "SLICEL", + "SLICE_X25Y157": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y158": { + "bits": {}, + "grid_x": 50, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X18Y158", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y158": "SLICEL", + "SLICE_X25Y158": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y159": { + "bits": {}, + "grid_x": 50, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X18Y159", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y159": "SLICEL", + "SLICE_X25Y159": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y16": { + "bits": {}, + "grid_x": 50, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X18Y16", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y16": "SLICEL", + "SLICE_X25Y16": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y160": { + "bits": {}, + "grid_x": 50, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X18Y160", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y160": "SLICEL", + "SLICE_X25Y160": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y161": { + "bits": {}, + "grid_x": 50, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X18Y161", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y161": "SLICEL", + "SLICE_X25Y161": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y162": { + "bits": {}, + "grid_x": 50, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X18Y162", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y162": "SLICEL", + "SLICE_X25Y162": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y163": { + "bits": {}, + "grid_x": 50, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X18Y163", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y163": "SLICEL", + "SLICE_X25Y163": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y164": { + "bits": {}, + "grid_x": 50, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X18Y164", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y164": "SLICEL", + "SLICE_X25Y164": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y165": { + "bits": {}, + "grid_x": 50, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X18Y165", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y165": "SLICEL", + "SLICE_X25Y165": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y166": { + "bits": {}, + "grid_x": 50, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X18Y166", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y166": "SLICEL", + "SLICE_X25Y166": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y167": { + "bits": {}, + "grid_x": 50, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X18Y167", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y167": "SLICEL", + "SLICE_X25Y167": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y168": { + "bits": {}, + "grid_x": 50, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X18Y168", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y168": "SLICEL", + "SLICE_X25Y168": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y169": { + "bits": {}, + "grid_x": 50, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X18Y169", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y169": "SLICEL", + "SLICE_X25Y169": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y17": { + "bits": {}, + "grid_x": 50, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X18Y17", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y17": "SLICEL", + "SLICE_X25Y17": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y170": { + "bits": {}, + "grid_x": 50, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X18Y170", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y170": "SLICEL", + "SLICE_X25Y170": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y171": { + "bits": {}, + "grid_x": 50, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X18Y171", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y171": "SLICEL", + "SLICE_X25Y171": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y172": { + "bits": {}, + "grid_x": 50, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X18Y172", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y172": "SLICEL", + "SLICE_X25Y172": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y173": { + "bits": {}, + "grid_x": 50, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X18Y173", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y173": "SLICEL", + "SLICE_X25Y173": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y174": { + "bits": {}, + "grid_x": 50, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X18Y174", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y174": "SLICEL", + "SLICE_X25Y174": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y175": { + "bits": {}, + "grid_x": 50, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X18Y175", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y175": "SLICEL", + "SLICE_X25Y175": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y176": { + "bits": {}, + "grid_x": 50, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X18Y176", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y176": "SLICEL", + "SLICE_X25Y176": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y177": { + "bits": {}, + "grid_x": 50, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X18Y177", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y177": "SLICEL", + "SLICE_X25Y177": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y178": { + "bits": {}, + "grid_x": 50, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X18Y178", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y178": "SLICEL", + "SLICE_X25Y178": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y179": { + "bits": {}, + "grid_x": 50, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X18Y179", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y179": "SLICEL", + "SLICE_X25Y179": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y18": { + "bits": {}, + "grid_x": 50, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X18Y18", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y18": "SLICEL", + "SLICE_X25Y18": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y180": { + "bits": {}, + "grid_x": 50, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X18Y180", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y180": "SLICEL", + "SLICE_X25Y180": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y181": { + "bits": {}, + "grid_x": 50, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X18Y181", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y181": "SLICEL", + "SLICE_X25Y181": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y182": { + "bits": {}, + "grid_x": 50, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X18Y182", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y182": "SLICEL", + "SLICE_X25Y182": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y183": { + "bits": {}, + "grid_x": 50, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X18Y183", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y183": "SLICEL", + "SLICE_X25Y183": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y184": { + "bits": {}, + "grid_x": 50, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X18Y184", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y184": "SLICEL", + "SLICE_X25Y184": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y185": { + "bits": {}, + "grid_x": 50, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X18Y185", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y185": "SLICEL", + "SLICE_X25Y185": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y186": { + "bits": {}, + "grid_x": 50, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X18Y186", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y186": "SLICEL", + "SLICE_X25Y186": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y187": { + "bits": {}, + "grid_x": 50, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X18Y187", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y187": "SLICEL", + "SLICE_X25Y187": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y188": { + "bits": {}, + "grid_x": 50, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X18Y188", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y188": "SLICEL", + "SLICE_X25Y188": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y189": { + "bits": {}, + "grid_x": 50, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X18Y189", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y189": "SLICEL", + "SLICE_X25Y189": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y19": { + "bits": {}, + "grid_x": 50, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X18Y19", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y19": "SLICEL", + "SLICE_X25Y19": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y190": { + "bits": {}, + "grid_x": 50, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X18Y190", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y190": "SLICEL", + "SLICE_X25Y190": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y191": { + "bits": {}, + "grid_x": 50, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X18Y191", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y191": "SLICEL", + "SLICE_X25Y191": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y192": { + "bits": {}, + "grid_x": 50, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X18Y192", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y192": "SLICEL", + "SLICE_X25Y192": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y193": { + "bits": {}, + "grid_x": 50, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X18Y193", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y193": "SLICEL", + "SLICE_X25Y193": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y194": { + "bits": {}, + "grid_x": 50, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X18Y194", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y194": "SLICEL", + "SLICE_X25Y194": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y195": { + "bits": {}, + "grid_x": 50, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X18Y195", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y195": "SLICEL", + "SLICE_X25Y195": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y196": { + "bits": {}, + "grid_x": 50, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X18Y196", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y196": "SLICEL", + "SLICE_X25Y196": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y197": { + "bits": {}, + "grid_x": 50, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X18Y197", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y197": "SLICEL", + "SLICE_X25Y197": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y198": { + "bits": {}, + "grid_x": 50, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X18Y198", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y198": "SLICEL", + "SLICE_X25Y198": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y199": { + "bits": {}, + "grid_x": 50, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X18Y199", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y199": "SLICEL", + "SLICE_X25Y199": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y2": { + "bits": {}, + "grid_x": 50, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X18Y2", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y2": "SLICEL", + "SLICE_X25Y2": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y20": { + "bits": {}, + "grid_x": 50, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X18Y20", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y20": "SLICEL", + "SLICE_X25Y20": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y21": { + "bits": {}, + "grid_x": 50, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X18Y21", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y21": "SLICEL", + "SLICE_X25Y21": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y22": { + "bits": {}, + "grid_x": 50, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X18Y22", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y22": "SLICEL", + "SLICE_X25Y22": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y23": { + "bits": {}, + "grid_x": 50, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X18Y23", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y23": "SLICEL", + "SLICE_X25Y23": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y24": { + "bits": {}, + "grid_x": 50, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X18Y24", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y24": "SLICEL", + "SLICE_X25Y24": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y25": { + "bits": {}, + "grid_x": 50, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X18Y25", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y25": "SLICEL", + "SLICE_X25Y25": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y26": { + "bits": {}, + "grid_x": 50, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X18Y26", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y26": "SLICEL", + "SLICE_X25Y26": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y27": { + "bits": {}, + "grid_x": 50, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X18Y27", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y27": "SLICEL", + "SLICE_X25Y27": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y28": { + "bits": {}, + "grid_x": 50, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X18Y28", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y28": "SLICEL", + "SLICE_X25Y28": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y29": { + "bits": {}, + "grid_x": 50, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X18Y29", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y29": "SLICEL", + "SLICE_X25Y29": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y3": { + "bits": {}, + "grid_x": 50, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X18Y3", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y3": "SLICEL", + "SLICE_X25Y3": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y30": { + "bits": {}, + "grid_x": 50, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X18Y30", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y30": "SLICEL", + "SLICE_X25Y30": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y31": { + "bits": {}, + "grid_x": 50, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X18Y31", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y31": "SLICEL", + "SLICE_X25Y31": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y32": { + "bits": {}, + "grid_x": 50, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X18Y32", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y32": "SLICEL", + "SLICE_X25Y32": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y33": { + "bits": {}, + "grid_x": 50, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X18Y33", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y33": "SLICEL", + "SLICE_X25Y33": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y34": { + "bits": {}, + "grid_x": 50, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X18Y34", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y34": "SLICEL", + "SLICE_X25Y34": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y35": { + "bits": {}, + "grid_x": 50, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X18Y35", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y35": "SLICEL", + "SLICE_X25Y35": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y36": { + "bits": {}, + "grid_x": 50, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X18Y36", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y36": "SLICEL", + "SLICE_X25Y36": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y37": { + "bits": {}, + "grid_x": 50, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X18Y37", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y37": "SLICEL", + "SLICE_X25Y37": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y38": { + "bits": {}, + "grid_x": 50, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X18Y38", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y38": "SLICEL", + "SLICE_X25Y38": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y39": { + "bits": {}, + "grid_x": 50, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X18Y39", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y39": "SLICEL", + "SLICE_X25Y39": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y4": { + "bits": {}, + "grid_x": 50, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X18Y4", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y4": "SLICEL", + "SLICE_X25Y4": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y40": { + "bits": {}, + "grid_x": 50, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X18Y40", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y40": "SLICEL", + "SLICE_X25Y40": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y41": { + "bits": {}, + "grid_x": 50, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X18Y41", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y41": "SLICEL", + "SLICE_X25Y41": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y42": { + "bits": {}, + "grid_x": 50, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X18Y42", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y42": "SLICEL", + "SLICE_X25Y42": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y43": { + "bits": {}, + "grid_x": 50, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X18Y43", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y43": "SLICEL", + "SLICE_X25Y43": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y44": { + "bits": {}, + "grid_x": 50, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X18Y44", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y44": "SLICEL", + "SLICE_X25Y44": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y45": { + "bits": {}, + "grid_x": 50, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X18Y45", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y45": "SLICEL", + "SLICE_X25Y45": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y46": { + "bits": {}, + "grid_x": 50, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X18Y46", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y46": "SLICEL", + "SLICE_X25Y46": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y47": { + "bits": {}, + "grid_x": 50, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X18Y47", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y47": "SLICEL", + "SLICE_X25Y47": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y48": { + "bits": {}, + "grid_x": 50, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X18Y48", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y48": "SLICEL", + "SLICE_X25Y48": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y49": { + "bits": {}, + "grid_x": 50, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X18Y49", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y49": "SLICEL", + "SLICE_X25Y49": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y5": { + "bits": {}, + "grid_x": 50, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X18Y5", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y5": "SLICEL", + "SLICE_X25Y5": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y6": { + "bits": {}, + "grid_x": 50, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X18Y6", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y6": "SLICEL", + "SLICE_X25Y6": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y7": { + "bits": {}, + "grid_x": 50, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X18Y7", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y7": "SLICEL", + "SLICE_X25Y7": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y8": { + "bits": {}, + "grid_x": 50, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X18Y8", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y8": "SLICEL", + "SLICE_X25Y8": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X18Y9": { + "bits": {}, + "grid_x": 50, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X18Y9", + "segment_type": "clbll_l", + "sites": { + "SLICE_X24Y9": "SLICEL", + "SLICE_X25Y9": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y0": { + "bits": {}, + "grid_x": 54, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X20Y0", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y0": "SLICEL", + "SLICE_X29Y0": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y1": { + "bits": {}, + "grid_x": 54, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X20Y1", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y1": "SLICEL", + "SLICE_X29Y1": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y10": { + "bits": {}, + "grid_x": 54, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X20Y10", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y10": "SLICEL", + "SLICE_X29Y10": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y11": { + "bits": {}, + "grid_x": 54, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X20Y11", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y11": "SLICEL", + "SLICE_X29Y11": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y12": { + "bits": {}, + "grid_x": 54, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X20Y12", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y12": "SLICEL", + "SLICE_X29Y12": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y13": { + "bits": {}, + "grid_x": 54, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X20Y13", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y13": "SLICEL", + "SLICE_X29Y13": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y14": { + "bits": {}, + "grid_x": 54, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X20Y14", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y14": "SLICEL", + "SLICE_X29Y14": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y15": { + "bits": {}, + "grid_x": 54, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X20Y15", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y15": "SLICEL", + "SLICE_X29Y15": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y150": { + "bits": {}, + "grid_x": 54, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X20Y150", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y150": "SLICEL", + "SLICE_X29Y150": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y151": { + "bits": {}, + "grid_x": 54, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X20Y151", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y151": "SLICEL", + "SLICE_X29Y151": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y152": { + "bits": {}, + "grid_x": 54, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X20Y152", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y152": "SLICEL", + "SLICE_X29Y152": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y153": { + "bits": {}, + "grid_x": 54, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X20Y153", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y153": "SLICEL", + "SLICE_X29Y153": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y154": { + "bits": {}, + "grid_x": 54, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X20Y154", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y154": "SLICEL", + "SLICE_X29Y154": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y155": { + "bits": {}, + "grid_x": 54, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X20Y155", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y155": "SLICEL", + "SLICE_X29Y155": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y156": { + "bits": {}, + "grid_x": 54, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X20Y156", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y156": "SLICEL", + "SLICE_X29Y156": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y157": { + "bits": {}, + "grid_x": 54, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X20Y157", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y157": "SLICEL", + "SLICE_X29Y157": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y158": { + "bits": {}, + "grid_x": 54, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X20Y158", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y158": "SLICEL", + "SLICE_X29Y158": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y159": { + "bits": {}, + "grid_x": 54, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X20Y159", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y159": "SLICEL", + "SLICE_X29Y159": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y16": { + "bits": {}, + "grid_x": 54, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X20Y16", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y16": "SLICEL", + "SLICE_X29Y16": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y160": { + "bits": {}, + "grid_x": 54, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X20Y160", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y160": "SLICEL", + "SLICE_X29Y160": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y161": { + "bits": {}, + "grid_x": 54, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X20Y161", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y161": "SLICEL", + "SLICE_X29Y161": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y162": { + "bits": {}, + "grid_x": 54, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X20Y162", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y162": "SLICEL", + "SLICE_X29Y162": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y163": { + "bits": {}, + "grid_x": 54, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X20Y163", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y163": "SLICEL", + "SLICE_X29Y163": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y164": { + "bits": {}, + "grid_x": 54, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X20Y164", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y164": "SLICEL", + "SLICE_X29Y164": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y165": { + "bits": {}, + "grid_x": 54, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X20Y165", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y165": "SLICEL", + "SLICE_X29Y165": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y166": { + "bits": {}, + "grid_x": 54, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X20Y166", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y166": "SLICEL", + "SLICE_X29Y166": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y167": { + "bits": {}, + "grid_x": 54, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X20Y167", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y167": "SLICEL", + "SLICE_X29Y167": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y168": { + "bits": {}, + "grid_x": 54, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X20Y168", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y168": "SLICEL", + "SLICE_X29Y168": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y169": { + "bits": {}, + "grid_x": 54, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X20Y169", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y169": "SLICEL", + "SLICE_X29Y169": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y17": { + "bits": {}, + "grid_x": 54, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X20Y17", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y17": "SLICEL", + "SLICE_X29Y17": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y170": { + "bits": {}, + "grid_x": 54, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X20Y170", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y170": "SLICEL", + "SLICE_X29Y170": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y171": { + "bits": {}, + "grid_x": 54, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X20Y171", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y171": "SLICEL", + "SLICE_X29Y171": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y172": { + "bits": {}, + "grid_x": 54, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X20Y172", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y172": "SLICEL", + "SLICE_X29Y172": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y173": { + "bits": {}, + "grid_x": 54, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X20Y173", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y173": "SLICEL", + "SLICE_X29Y173": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y174": { + "bits": {}, + "grid_x": 54, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X20Y174", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y174": "SLICEL", + "SLICE_X29Y174": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y175": { + "bits": {}, + "grid_x": 54, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X20Y175", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y175": "SLICEL", + "SLICE_X29Y175": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y176": { + "bits": {}, + "grid_x": 54, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X20Y176", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y176": "SLICEL", + "SLICE_X29Y176": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y177": { + "bits": {}, + "grid_x": 54, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X20Y177", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y177": "SLICEL", + "SLICE_X29Y177": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y178": { + "bits": {}, + "grid_x": 54, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X20Y178", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y178": "SLICEL", + "SLICE_X29Y178": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y179": { + "bits": {}, + "grid_x": 54, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X20Y179", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y179": "SLICEL", + "SLICE_X29Y179": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y18": { + "bits": {}, + "grid_x": 54, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X20Y18", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y18": "SLICEL", + "SLICE_X29Y18": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y180": { + "bits": {}, + "grid_x": 54, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X20Y180", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y180": "SLICEL", + "SLICE_X29Y180": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y181": { + "bits": {}, + "grid_x": 54, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X20Y181", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y181": "SLICEL", + "SLICE_X29Y181": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y182": { + "bits": {}, + "grid_x": 54, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X20Y182", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y182": "SLICEL", + "SLICE_X29Y182": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y183": { + "bits": {}, + "grid_x": 54, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X20Y183", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y183": "SLICEL", + "SLICE_X29Y183": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y184": { + "bits": {}, + "grid_x": 54, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X20Y184", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y184": "SLICEL", + "SLICE_X29Y184": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y185": { + "bits": {}, + "grid_x": 54, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X20Y185", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y185": "SLICEL", + "SLICE_X29Y185": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y186": { + "bits": {}, + "grid_x": 54, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X20Y186", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y186": "SLICEL", + "SLICE_X29Y186": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y187": { + "bits": {}, + "grid_x": 54, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X20Y187", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y187": "SLICEL", + "SLICE_X29Y187": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y188": { + "bits": {}, + "grid_x": 54, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X20Y188", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y188": "SLICEL", + "SLICE_X29Y188": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y189": { + "bits": {}, + "grid_x": 54, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X20Y189", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y189": "SLICEL", + "SLICE_X29Y189": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y19": { + "bits": {}, + "grid_x": 54, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X20Y19", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y19": "SLICEL", + "SLICE_X29Y19": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y190": { + "bits": {}, + "grid_x": 54, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X20Y190", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y190": "SLICEL", + "SLICE_X29Y190": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y191": { + "bits": {}, + "grid_x": 54, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X20Y191", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y191": "SLICEL", + "SLICE_X29Y191": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y192": { + "bits": {}, + "grid_x": 54, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X20Y192", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y192": "SLICEL", + "SLICE_X29Y192": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y193": { + "bits": {}, + "grid_x": 54, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X20Y193", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y193": "SLICEL", + "SLICE_X29Y193": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y194": { + "bits": {}, + "grid_x": 54, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X20Y194", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y194": "SLICEL", + "SLICE_X29Y194": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y195": { + "bits": {}, + "grid_x": 54, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X20Y195", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y195": "SLICEL", + "SLICE_X29Y195": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y196": { + "bits": {}, + "grid_x": 54, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X20Y196", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y196": "SLICEL", + "SLICE_X29Y196": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y197": { + "bits": {}, + "grid_x": 54, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X20Y197", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y197": "SLICEL", + "SLICE_X29Y197": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y198": { + "bits": {}, + "grid_x": 54, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X20Y198", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y198": "SLICEL", + "SLICE_X29Y198": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y199": { + "bits": {}, + "grid_x": 54, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X20Y199", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y199": "SLICEL", + "SLICE_X29Y199": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y2": { + "bits": {}, + "grid_x": 54, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X20Y2", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y2": "SLICEL", + "SLICE_X29Y2": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y20": { + "bits": {}, + "grid_x": 54, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X20Y20", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y20": "SLICEL", + "SLICE_X29Y20": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y21": { + "bits": {}, + "grid_x": 54, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X20Y21", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y21": "SLICEL", + "SLICE_X29Y21": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y22": { + "bits": {}, + "grid_x": 54, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X20Y22", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y22": "SLICEL", + "SLICE_X29Y22": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y23": { + "bits": {}, + "grid_x": 54, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X20Y23", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y23": "SLICEL", + "SLICE_X29Y23": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y24": { + "bits": {}, + "grid_x": 54, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X20Y24", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y24": "SLICEL", + "SLICE_X29Y24": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y25": { + "bits": {}, + "grid_x": 54, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X20Y25", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y25": "SLICEL", + "SLICE_X29Y25": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y26": { + "bits": {}, + "grid_x": 54, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X20Y26", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y26": "SLICEL", + "SLICE_X29Y26": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y27": { + "bits": {}, + "grid_x": 54, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X20Y27", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y27": "SLICEL", + "SLICE_X29Y27": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y28": { + "bits": {}, + "grid_x": 54, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X20Y28", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y28": "SLICEL", + "SLICE_X29Y28": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y29": { + "bits": {}, + "grid_x": 54, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X20Y29", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y29": "SLICEL", + "SLICE_X29Y29": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y3": { + "bits": {}, + "grid_x": 54, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X20Y3", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y3": "SLICEL", + "SLICE_X29Y3": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y30": { + "bits": {}, + "grid_x": 54, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X20Y30", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y30": "SLICEL", + "SLICE_X29Y30": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y31": { + "bits": {}, + "grid_x": 54, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X20Y31", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y31": "SLICEL", + "SLICE_X29Y31": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y32": { + "bits": {}, + "grid_x": 54, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X20Y32", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y32": "SLICEL", + "SLICE_X29Y32": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y33": { + "bits": {}, + "grid_x": 54, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X20Y33", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y33": "SLICEL", + "SLICE_X29Y33": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y34": { + "bits": {}, + "grid_x": 54, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X20Y34", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y34": "SLICEL", + "SLICE_X29Y34": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y35": { + "bits": {}, + "grid_x": 54, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X20Y35", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y35": "SLICEL", + "SLICE_X29Y35": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y36": { + "bits": {}, + "grid_x": 54, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X20Y36", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y36": "SLICEL", + "SLICE_X29Y36": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y37": { + "bits": {}, + "grid_x": 54, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X20Y37", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y37": "SLICEL", + "SLICE_X29Y37": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y38": { + "bits": {}, + "grid_x": 54, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X20Y38", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y38": "SLICEL", + "SLICE_X29Y38": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y39": { + "bits": {}, + "grid_x": 54, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X20Y39", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y39": "SLICEL", + "SLICE_X29Y39": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y4": { + "bits": {}, + "grid_x": 54, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X20Y4", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y4": "SLICEL", + "SLICE_X29Y4": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y40": { + "bits": {}, + "grid_x": 54, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X20Y40", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y40": "SLICEL", + "SLICE_X29Y40": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y41": { + "bits": {}, + "grid_x": 54, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X20Y41", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y41": "SLICEL", + "SLICE_X29Y41": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y42": { + "bits": {}, + "grid_x": 54, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X20Y42", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y42": "SLICEL", + "SLICE_X29Y42": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y43": { + "bits": {}, + "grid_x": 54, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X20Y43", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y43": "SLICEL", + "SLICE_X29Y43": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y44": { + "bits": {}, + "grid_x": 54, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X20Y44", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y44": "SLICEL", + "SLICE_X29Y44": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y45": { + "bits": {}, + "grid_x": 54, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X20Y45", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y45": "SLICEL", + "SLICE_X29Y45": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y46": { + "bits": {}, + "grid_x": 54, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X20Y46", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y46": "SLICEL", + "SLICE_X29Y46": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y47": { + "bits": {}, + "grid_x": 54, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X20Y47", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y47": "SLICEL", + "SLICE_X29Y47": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y48": { + "bits": {}, + "grid_x": 54, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X20Y48", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y48": "SLICEL", + "SLICE_X29Y48": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y49": { + "bits": {}, + "grid_x": 54, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X20Y49", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y49": "SLICEL", + "SLICE_X29Y49": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y5": { + "bits": {}, + "grid_x": 54, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X20Y5", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y5": "SLICEL", + "SLICE_X29Y5": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y6": { + "bits": {}, + "grid_x": 54, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X20Y6", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y6": "SLICEL", + "SLICE_X29Y6": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y7": { + "bits": {}, + "grid_x": 54, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X20Y7", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y7": "SLICEL", + "SLICE_X29Y7": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y8": { + "bits": {}, + "grid_x": 54, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X20Y8", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y8": "SLICEL", + "SLICE_X29Y8": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X20Y9": { + "bits": {}, + "grid_x": 54, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X20Y9", + "segment_type": "clbll_l", + "sites": { + "SLICE_X28Y9": "SLICEL", + "SLICE_X29Y9": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y0": { + "bits": {}, + "grid_x": 58, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X22Y0", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y0": "SLICEL", + "SLICE_X33Y0": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y1": { + "bits": {}, + "grid_x": 58, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X22Y1", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y1": "SLICEL", + "SLICE_X33Y1": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y10": { + "bits": {}, + "grid_x": 58, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X22Y10", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y10": "SLICEL", + "SLICE_X33Y10": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y11": { + "bits": {}, + "grid_x": 58, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X22Y11", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y11": "SLICEL", + "SLICE_X33Y11": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y12": { + "bits": {}, + "grid_x": 58, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X22Y12", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y12": "SLICEL", + "SLICE_X33Y12": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y13": { + "bits": {}, + "grid_x": 58, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X22Y13", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y13": "SLICEL", + "SLICE_X33Y13": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y14": { + "bits": {}, + "grid_x": 58, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X22Y14", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y14": "SLICEL", + "SLICE_X33Y14": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y15": { + "bits": {}, + "grid_x": 58, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X22Y15", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y15": "SLICEL", + "SLICE_X33Y15": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y150": { + "bits": {}, + "grid_x": 58, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X22Y150", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y150": "SLICEL", + "SLICE_X33Y150": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y151": { + "bits": {}, + "grid_x": 58, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X22Y151", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y151": "SLICEL", + "SLICE_X33Y151": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y152": { + "bits": {}, + "grid_x": 58, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X22Y152", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y152": "SLICEL", + "SLICE_X33Y152": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y153": { + "bits": {}, + "grid_x": 58, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X22Y153", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y153": "SLICEL", + "SLICE_X33Y153": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y154": { + "bits": {}, + "grid_x": 58, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X22Y154", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y154": "SLICEL", + "SLICE_X33Y154": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y155": { + "bits": {}, + "grid_x": 58, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X22Y155", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y155": "SLICEL", + "SLICE_X33Y155": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y156": { + "bits": {}, + "grid_x": 58, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X22Y156", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y156": "SLICEL", + "SLICE_X33Y156": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y157": { + "bits": {}, + "grid_x": 58, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X22Y157", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y157": "SLICEL", + "SLICE_X33Y157": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y158": { + "bits": {}, + "grid_x": 58, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X22Y158", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y158": "SLICEL", + "SLICE_X33Y158": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y159": { + "bits": {}, + "grid_x": 58, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X22Y159", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y159": "SLICEL", + "SLICE_X33Y159": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y16": { + "bits": {}, + "grid_x": 58, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X22Y16", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y16": "SLICEL", + "SLICE_X33Y16": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y160": { + "bits": {}, + "grid_x": 58, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X22Y160", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y160": "SLICEL", + "SLICE_X33Y160": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y161": { + "bits": {}, + "grid_x": 58, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X22Y161", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y161": "SLICEL", + "SLICE_X33Y161": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y162": { + "bits": {}, + "grid_x": 58, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X22Y162", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y162": "SLICEL", + "SLICE_X33Y162": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y163": { + "bits": {}, + "grid_x": 58, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X22Y163", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y163": "SLICEL", + "SLICE_X33Y163": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y164": { + "bits": {}, + "grid_x": 58, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X22Y164", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y164": "SLICEL", + "SLICE_X33Y164": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y165": { + "bits": {}, + "grid_x": 58, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X22Y165", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y165": "SLICEL", + "SLICE_X33Y165": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y166": { + "bits": {}, + "grid_x": 58, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X22Y166", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y166": "SLICEL", + "SLICE_X33Y166": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y167": { + "bits": {}, + "grid_x": 58, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X22Y167", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y167": "SLICEL", + "SLICE_X33Y167": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y168": { + "bits": {}, + "grid_x": 58, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X22Y168", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y168": "SLICEL", + "SLICE_X33Y168": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y169": { + "bits": {}, + "grid_x": 58, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X22Y169", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y169": "SLICEL", + "SLICE_X33Y169": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y17": { + "bits": {}, + "grid_x": 58, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X22Y17", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y17": "SLICEL", + "SLICE_X33Y17": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y170": { + "bits": {}, + "grid_x": 58, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X22Y170", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y170": "SLICEL", + "SLICE_X33Y170": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y171": { + "bits": {}, + "grid_x": 58, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X22Y171", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y171": "SLICEL", + "SLICE_X33Y171": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y172": { + "bits": {}, + "grid_x": 58, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X22Y172", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y172": "SLICEL", + "SLICE_X33Y172": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y173": { + "bits": {}, + "grid_x": 58, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X22Y173", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y173": "SLICEL", + "SLICE_X33Y173": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y174": { + "bits": {}, + "grid_x": 58, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X22Y174", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y174": "SLICEL", + "SLICE_X33Y174": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y175": { + "bits": {}, + "grid_x": 58, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X22Y175", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y175": "SLICEL", + "SLICE_X33Y175": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y176": { + "bits": {}, + "grid_x": 58, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X22Y176", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y176": "SLICEL", + "SLICE_X33Y176": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y177": { + "bits": {}, + "grid_x": 58, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X22Y177", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y177": "SLICEL", + "SLICE_X33Y177": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y178": { + "bits": {}, + "grid_x": 58, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X22Y178", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y178": "SLICEL", + "SLICE_X33Y178": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y179": { + "bits": {}, + "grid_x": 58, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X22Y179", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y179": "SLICEL", + "SLICE_X33Y179": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y18": { + "bits": {}, + "grid_x": 58, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X22Y18", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y18": "SLICEL", + "SLICE_X33Y18": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y180": { + "bits": {}, + "grid_x": 58, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X22Y180", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y180": "SLICEL", + "SLICE_X33Y180": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y181": { + "bits": {}, + "grid_x": 58, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X22Y181", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y181": "SLICEL", + "SLICE_X33Y181": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y182": { + "bits": {}, + "grid_x": 58, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X22Y182", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y182": "SLICEL", + "SLICE_X33Y182": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y183": { + "bits": {}, + "grid_x": 58, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X22Y183", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y183": "SLICEL", + "SLICE_X33Y183": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y184": { + "bits": {}, + "grid_x": 58, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X22Y184", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y184": "SLICEL", + "SLICE_X33Y184": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y185": { + "bits": {}, + "grid_x": 58, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X22Y185", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y185": "SLICEL", + "SLICE_X33Y185": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y186": { + "bits": {}, + "grid_x": 58, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X22Y186", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y186": "SLICEL", + "SLICE_X33Y186": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y187": { + "bits": {}, + "grid_x": 58, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X22Y187", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y187": "SLICEL", + "SLICE_X33Y187": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y188": { + "bits": {}, + "grid_x": 58, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X22Y188", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y188": "SLICEL", + "SLICE_X33Y188": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y189": { + "bits": {}, + "grid_x": 58, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X22Y189", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y189": "SLICEL", + "SLICE_X33Y189": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y19": { + "bits": {}, + "grid_x": 58, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X22Y19", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y19": "SLICEL", + "SLICE_X33Y19": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y190": { + "bits": {}, + "grid_x": 58, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X22Y190", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y190": "SLICEL", + "SLICE_X33Y190": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y191": { + "bits": {}, + "grid_x": 58, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X22Y191", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y191": "SLICEL", + "SLICE_X33Y191": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y192": { + "bits": {}, + "grid_x": 58, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X22Y192", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y192": "SLICEL", + "SLICE_X33Y192": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y193": { + "bits": {}, + "grid_x": 58, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X22Y193", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y193": "SLICEL", + "SLICE_X33Y193": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y194": { + "bits": {}, + "grid_x": 58, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X22Y194", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y194": "SLICEL", + "SLICE_X33Y194": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y195": { + "bits": {}, + "grid_x": 58, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X22Y195", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y195": "SLICEL", + "SLICE_X33Y195": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y196": { + "bits": {}, + "grid_x": 58, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X22Y196", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y196": "SLICEL", + "SLICE_X33Y196": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y197": { + "bits": {}, + "grid_x": 58, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X22Y197", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y197": "SLICEL", + "SLICE_X33Y197": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y198": { + "bits": {}, + "grid_x": 58, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X22Y198", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y198": "SLICEL", + "SLICE_X33Y198": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y199": { + "bits": {}, + "grid_x": 58, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X22Y199", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y199": "SLICEL", + "SLICE_X33Y199": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y2": { + "bits": {}, + "grid_x": 58, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X22Y2", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y2": "SLICEL", + "SLICE_X33Y2": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y20": { + "bits": {}, + "grid_x": 58, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X22Y20", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y20": "SLICEL", + "SLICE_X33Y20": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y21": { + "bits": {}, + "grid_x": 58, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X22Y21", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y21": "SLICEL", + "SLICE_X33Y21": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y22": { + "bits": {}, + "grid_x": 58, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X22Y22", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y22": "SLICEL", + "SLICE_X33Y22": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y23": { + "bits": {}, + "grid_x": 58, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X22Y23", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y23": "SLICEL", + "SLICE_X33Y23": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y24": { + "bits": {}, + "grid_x": 58, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X22Y24", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y24": "SLICEL", + "SLICE_X33Y24": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y25": { + "bits": {}, + "grid_x": 58, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X22Y25", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y25": "SLICEL", + "SLICE_X33Y25": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y26": { + "bits": {}, + "grid_x": 58, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X22Y26", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y26": "SLICEL", + "SLICE_X33Y26": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y27": { + "bits": {}, + "grid_x": 58, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X22Y27", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y27": "SLICEL", + "SLICE_X33Y27": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y28": { + "bits": {}, + "grid_x": 58, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X22Y28", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y28": "SLICEL", + "SLICE_X33Y28": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y29": { + "bits": {}, + "grid_x": 58, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X22Y29", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y29": "SLICEL", + "SLICE_X33Y29": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y3": { + "bits": {}, + "grid_x": 58, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X22Y3", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y3": "SLICEL", + "SLICE_X33Y3": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y30": { + "bits": {}, + "grid_x": 58, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X22Y30", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y30": "SLICEL", + "SLICE_X33Y30": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y31": { + "bits": {}, + "grid_x": 58, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X22Y31", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y31": "SLICEL", + "SLICE_X33Y31": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y32": { + "bits": {}, + "grid_x": 58, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X22Y32", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y32": "SLICEL", + "SLICE_X33Y32": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y33": { + "bits": {}, + "grid_x": 58, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X22Y33", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y33": "SLICEL", + "SLICE_X33Y33": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y34": { + "bits": {}, + "grid_x": 58, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X22Y34", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y34": "SLICEL", + "SLICE_X33Y34": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y35": { + "bits": {}, + "grid_x": 58, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X22Y35", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y35": "SLICEL", + "SLICE_X33Y35": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y36": { + "bits": {}, + "grid_x": 58, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X22Y36", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y36": "SLICEL", + "SLICE_X33Y36": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y37": { + "bits": {}, + "grid_x": 58, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X22Y37", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y37": "SLICEL", + "SLICE_X33Y37": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y38": { + "bits": {}, + "grid_x": 58, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X22Y38", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y38": "SLICEL", + "SLICE_X33Y38": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y39": { + "bits": {}, + "grid_x": 58, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X22Y39", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y39": "SLICEL", + "SLICE_X33Y39": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y4": { + "bits": {}, + "grid_x": 58, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X22Y4", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y4": "SLICEL", + "SLICE_X33Y4": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y40": { + "bits": {}, + "grid_x": 58, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X22Y40", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y40": "SLICEL", + "SLICE_X33Y40": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y41": { + "bits": {}, + "grid_x": 58, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X22Y41", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y41": "SLICEL", + "SLICE_X33Y41": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y42": { + "bits": {}, + "grid_x": 58, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X22Y42", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y42": "SLICEL", + "SLICE_X33Y42": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y43": { + "bits": {}, + "grid_x": 58, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X22Y43", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y43": "SLICEL", + "SLICE_X33Y43": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y44": { + "bits": {}, + "grid_x": 58, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X22Y44", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y44": "SLICEL", + "SLICE_X33Y44": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y45": { + "bits": {}, + "grid_x": 58, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X22Y45", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y45": "SLICEL", + "SLICE_X33Y45": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y46": { + "bits": {}, + "grid_x": 58, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X22Y46", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y46": "SLICEL", + "SLICE_X33Y46": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y47": { + "bits": {}, + "grid_x": 58, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X22Y47", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y47": "SLICEL", + "SLICE_X33Y47": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y48": { + "bits": {}, + "grid_x": 58, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X22Y48", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y48": "SLICEL", + "SLICE_X33Y48": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y49": { + "bits": {}, + "grid_x": 58, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X22Y49", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y49": "SLICEL", + "SLICE_X33Y49": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y5": { + "bits": {}, + "grid_x": 58, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X22Y5", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y5": "SLICEL", + "SLICE_X33Y5": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y6": { + "bits": {}, + "grid_x": 58, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X22Y6", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y6": "SLICEL", + "SLICE_X33Y6": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y7": { + "bits": {}, + "grid_x": 58, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X22Y7", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y7": "SLICEL", + "SLICE_X33Y7": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y8": { + "bits": {}, + "grid_x": 58, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X22Y8", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y8": "SLICEL", + "SLICE_X33Y8": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X22Y9": { + "bits": {}, + "grid_x": 58, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X22Y9", + "segment_type": "clbll_l", + "sites": { + "SLICE_X32Y9": "SLICEL", + "SLICE_X33Y9": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y0": { + "bits": {}, + "grid_x": 69, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X26Y0", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y0": "SLICEL", + "SLICE_X37Y0": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y1": { + "bits": {}, + "grid_x": 69, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X26Y1", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y1": "SLICEL", + "SLICE_X37Y1": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y10": { + "bits": {}, + "grid_x": 69, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X26Y10", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y10": "SLICEL", + "SLICE_X37Y10": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y100": { + "bits": {}, + "grid_x": 69, + "grid_y": 103, + "segment": "SEG_CLBLL_L_X26Y100", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y100": "SLICEL", + "SLICE_X37Y100": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y101": { + "bits": {}, + "grid_x": 69, + "grid_y": 102, + "segment": "SEG_CLBLL_L_X26Y101", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y101": "SLICEL", + "SLICE_X37Y101": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y102": { + "bits": {}, + "grid_x": 69, + "grid_y": 101, + "segment": "SEG_CLBLL_L_X26Y102", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y102": "SLICEL", + "SLICE_X37Y102": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y103": { + "bits": {}, + "grid_x": 69, + "grid_y": 100, + "segment": "SEG_CLBLL_L_X26Y103", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y103": "SLICEL", + "SLICE_X37Y103": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y104": { + "bits": {}, + "grid_x": 69, + "grid_y": 99, + "segment": "SEG_CLBLL_L_X26Y104", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y104": "SLICEL", + "SLICE_X37Y104": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y105": { + "bits": {}, + "grid_x": 69, + "grid_y": 98, + "segment": "SEG_CLBLL_L_X26Y105", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y105": "SLICEL", + "SLICE_X37Y105": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y106": { + "bits": {}, + "grid_x": 69, + "grid_y": 97, + "segment": "SEG_CLBLL_L_X26Y106", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y106": "SLICEL", + "SLICE_X37Y106": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y107": { + "bits": {}, + "grid_x": 69, + "grid_y": 96, + "segment": "SEG_CLBLL_L_X26Y107", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y107": "SLICEL", + "SLICE_X37Y107": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y108": { + "bits": {}, + "grid_x": 69, + "grid_y": 95, + "segment": "SEG_CLBLL_L_X26Y108", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y108": "SLICEL", + "SLICE_X37Y108": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y109": { + "bits": {}, + "grid_x": 69, + "grid_y": 94, + "segment": "SEG_CLBLL_L_X26Y109", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y109": "SLICEL", + "SLICE_X37Y109": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y11": { + "bits": {}, + "grid_x": 69, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X26Y11", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y11": "SLICEL", + "SLICE_X37Y11": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y110": { + "bits": {}, + "grid_x": 69, + "grid_y": 93, + "segment": "SEG_CLBLL_L_X26Y110", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y110": "SLICEL", + "SLICE_X37Y110": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y111": { + "bits": {}, + "grid_x": 69, + "grid_y": 92, + "segment": "SEG_CLBLL_L_X26Y111", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y111": "SLICEL", + "SLICE_X37Y111": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y112": { + "bits": {}, + "grid_x": 69, + "grid_y": 91, + "segment": "SEG_CLBLL_L_X26Y112", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y112": "SLICEL", + "SLICE_X37Y112": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y113": { + "bits": {}, + "grid_x": 69, + "grid_y": 90, + "segment": "SEG_CLBLL_L_X26Y113", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y113": "SLICEL", + "SLICE_X37Y113": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y114": { + "bits": {}, + "grid_x": 69, + "grid_y": 89, + "segment": "SEG_CLBLL_L_X26Y114", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y114": "SLICEL", + "SLICE_X37Y114": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y115": { + "bits": {}, + "grid_x": 69, + "grid_y": 88, + "segment": "SEG_CLBLL_L_X26Y115", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y115": "SLICEL", + "SLICE_X37Y115": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y116": { + "bits": {}, + "grid_x": 69, + "grid_y": 87, + "segment": "SEG_CLBLL_L_X26Y116", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y116": "SLICEL", + "SLICE_X37Y116": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y117": { + "bits": {}, + "grid_x": 69, + "grid_y": 86, + "segment": "SEG_CLBLL_L_X26Y117", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y117": "SLICEL", + "SLICE_X37Y117": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y118": { + "bits": {}, + "grid_x": 69, + "grid_y": 85, + "segment": "SEG_CLBLL_L_X26Y118", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y118": "SLICEL", + "SLICE_X37Y118": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y119": { + "bits": {}, + "grid_x": 69, + "grid_y": 84, + "segment": "SEG_CLBLL_L_X26Y119", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y119": "SLICEL", + "SLICE_X37Y119": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y12": { + "bits": {}, + "grid_x": 69, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X26Y12", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y12": "SLICEL", + "SLICE_X37Y12": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y120": { + "bits": {}, + "grid_x": 69, + "grid_y": 83, + "segment": "SEG_CLBLL_L_X26Y120", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y120": "SLICEL", + "SLICE_X37Y120": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y121": { + "bits": {}, + "grid_x": 69, + "grid_y": 82, + "segment": "SEG_CLBLL_L_X26Y121", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y121": "SLICEL", + "SLICE_X37Y121": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y122": { + "bits": {}, + "grid_x": 69, + "grid_y": 81, + "segment": "SEG_CLBLL_L_X26Y122", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y122": "SLICEL", + "SLICE_X37Y122": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y123": { + "bits": {}, + "grid_x": 69, + "grid_y": 80, + "segment": "SEG_CLBLL_L_X26Y123", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y123": "SLICEL", + "SLICE_X37Y123": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y124": { + "bits": {}, + "grid_x": 69, + "grid_y": 79, + "segment": "SEG_CLBLL_L_X26Y124", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y124": "SLICEL", + "SLICE_X37Y124": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y125": { + "bits": {}, + "grid_x": 69, + "grid_y": 77, + "segment": "SEG_CLBLL_L_X26Y125", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y125": "SLICEL", + "SLICE_X37Y125": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y126": { + "bits": {}, + "grid_x": 69, + "grid_y": 76, + "segment": "SEG_CLBLL_L_X26Y126", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y126": "SLICEL", + "SLICE_X37Y126": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y127": { + "bits": {}, + "grid_x": 69, + "grid_y": 75, + "segment": "SEG_CLBLL_L_X26Y127", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y127": "SLICEL", + "SLICE_X37Y127": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y128": { + "bits": {}, + "grid_x": 69, + "grid_y": 74, + "segment": "SEG_CLBLL_L_X26Y128", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y128": "SLICEL", + "SLICE_X37Y128": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y129": { + "bits": {}, + "grid_x": 69, + "grid_y": 73, + "segment": "SEG_CLBLL_L_X26Y129", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y129": "SLICEL", + "SLICE_X37Y129": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y13": { + "bits": {}, + "grid_x": 69, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X26Y13", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y13": "SLICEL", + "SLICE_X37Y13": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y130": { + "bits": {}, + "grid_x": 69, + "grid_y": 72, + "segment": "SEG_CLBLL_L_X26Y130", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y130": "SLICEL", + "SLICE_X37Y130": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y131": { + "bits": {}, + "grid_x": 69, + "grid_y": 71, + "segment": "SEG_CLBLL_L_X26Y131", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y131": "SLICEL", + "SLICE_X37Y131": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y132": { + "bits": {}, + "grid_x": 69, + "grid_y": 70, + "segment": "SEG_CLBLL_L_X26Y132", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y132": "SLICEL", + "SLICE_X37Y132": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y133": { + "bits": {}, + "grid_x": 69, + "grid_y": 69, + "segment": "SEG_CLBLL_L_X26Y133", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y133": "SLICEL", + "SLICE_X37Y133": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y134": { + "bits": {}, + "grid_x": 69, + "grid_y": 68, + "segment": "SEG_CLBLL_L_X26Y134", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y134": "SLICEL", + "SLICE_X37Y134": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y135": { + "bits": {}, + "grid_x": 69, + "grid_y": 67, + "segment": "SEG_CLBLL_L_X26Y135", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y135": "SLICEL", + "SLICE_X37Y135": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y136": { + "bits": {}, + "grid_x": 69, + "grid_y": 66, + "segment": "SEG_CLBLL_L_X26Y136", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y136": "SLICEL", + "SLICE_X37Y136": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y137": { + "bits": {}, + "grid_x": 69, + "grid_y": 65, + "segment": "SEG_CLBLL_L_X26Y137", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y137": "SLICEL", + "SLICE_X37Y137": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y138": { + "bits": {}, + "grid_x": 69, + "grid_y": 64, + "segment": "SEG_CLBLL_L_X26Y138", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y138": "SLICEL", + "SLICE_X37Y138": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y139": { + "bits": {}, + "grid_x": 69, + "grid_y": 63, + "segment": "SEG_CLBLL_L_X26Y139", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y139": "SLICEL", + "SLICE_X37Y139": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y14": { + "bits": {}, + "grid_x": 69, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X26Y14", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y14": "SLICEL", + "SLICE_X37Y14": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y140": { + "bits": {}, + "grid_x": 69, + "grid_y": 62, + "segment": "SEG_CLBLL_L_X26Y140", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y140": "SLICEL", + "SLICE_X37Y140": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y141": { + "bits": {}, + "grid_x": 69, + "grid_y": 61, + "segment": "SEG_CLBLL_L_X26Y141", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y141": "SLICEL", + "SLICE_X37Y141": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y142": { + "bits": {}, + "grid_x": 69, + "grid_y": 60, + "segment": "SEG_CLBLL_L_X26Y142", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y142": "SLICEL", + "SLICE_X37Y142": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y143": { + "bits": {}, + "grid_x": 69, + "grid_y": 59, + "segment": "SEG_CLBLL_L_X26Y143", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y143": "SLICEL", + "SLICE_X37Y143": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y144": { + "bits": {}, + "grid_x": 69, + "grid_y": 58, + "segment": "SEG_CLBLL_L_X26Y144", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y144": "SLICEL", + "SLICE_X37Y144": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y145": { + "bits": {}, + "grid_x": 69, + "grid_y": 57, + "segment": "SEG_CLBLL_L_X26Y145", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y145": "SLICEL", + "SLICE_X37Y145": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y146": { + "bits": {}, + "grid_x": 69, + "grid_y": 56, + "segment": "SEG_CLBLL_L_X26Y146", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y146": "SLICEL", + "SLICE_X37Y146": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y147": { + "bits": {}, + "grid_x": 69, + "grid_y": 55, + "segment": "SEG_CLBLL_L_X26Y147", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y147": "SLICEL", + "SLICE_X37Y147": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y148": { + "bits": {}, + "grid_x": 69, + "grid_y": 54, + "segment": "SEG_CLBLL_L_X26Y148", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y148": "SLICEL", + "SLICE_X37Y148": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y149": { + "bits": {}, + "grid_x": 69, + "grid_y": 53, + "segment": "SEG_CLBLL_L_X26Y149", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y149": "SLICEL", + "SLICE_X37Y149": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y15": { + "bits": {}, + "grid_x": 69, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X26Y15", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y15": "SLICEL", + "SLICE_X37Y15": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y150": { + "bits": {}, + "grid_x": 69, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X26Y150", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y150": "SLICEL", + "SLICE_X37Y150": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y151": { + "bits": {}, + "grid_x": 69, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X26Y151", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y151": "SLICEL", + "SLICE_X37Y151": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y152": { + "bits": {}, + "grid_x": 69, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X26Y152", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y152": "SLICEL", + "SLICE_X37Y152": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y153": { + "bits": {}, + "grid_x": 69, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X26Y153", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y153": "SLICEL", + "SLICE_X37Y153": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y154": { + "bits": {}, + "grid_x": 69, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X26Y154", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y154": "SLICEL", + "SLICE_X37Y154": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y155": { + "bits": {}, + "grid_x": 69, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X26Y155", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y155": "SLICEL", + "SLICE_X37Y155": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y156": { + "bits": {}, + "grid_x": 69, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X26Y156", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y156": "SLICEL", + "SLICE_X37Y156": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y157": { + "bits": {}, + "grid_x": 69, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X26Y157", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y157": "SLICEL", + "SLICE_X37Y157": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y158": { + "bits": {}, + "grid_x": 69, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X26Y158", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y158": "SLICEL", + "SLICE_X37Y158": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y159": { + "bits": {}, + "grid_x": 69, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X26Y159", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y159": "SLICEL", + "SLICE_X37Y159": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y16": { + "bits": {}, + "grid_x": 69, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X26Y16", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y16": "SLICEL", + "SLICE_X37Y16": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y160": { + "bits": {}, + "grid_x": 69, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X26Y160", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y160": "SLICEL", + "SLICE_X37Y160": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y161": { + "bits": {}, + "grid_x": 69, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X26Y161", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y161": "SLICEL", + "SLICE_X37Y161": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y162": { + "bits": {}, + "grid_x": 69, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X26Y162", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y162": "SLICEL", + "SLICE_X37Y162": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y163": { + "bits": {}, + "grid_x": 69, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X26Y163", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y163": "SLICEL", + "SLICE_X37Y163": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y164": { + "bits": {}, + "grid_x": 69, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X26Y164", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y164": "SLICEL", + "SLICE_X37Y164": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y165": { + "bits": {}, + "grid_x": 69, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X26Y165", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y165": "SLICEL", + "SLICE_X37Y165": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y166": { + "bits": {}, + "grid_x": 69, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X26Y166", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y166": "SLICEL", + "SLICE_X37Y166": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y167": { + "bits": {}, + "grid_x": 69, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X26Y167", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y167": "SLICEL", + "SLICE_X37Y167": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y168": { + "bits": {}, + "grid_x": 69, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X26Y168", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y168": "SLICEL", + "SLICE_X37Y168": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y169": { + "bits": {}, + "grid_x": 69, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X26Y169", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y169": "SLICEL", + "SLICE_X37Y169": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y17": { + "bits": {}, + "grid_x": 69, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X26Y17", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y17": "SLICEL", + "SLICE_X37Y17": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y170": { + "bits": {}, + "grid_x": 69, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X26Y170", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y170": "SLICEL", + "SLICE_X37Y170": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y171": { + "bits": {}, + "grid_x": 69, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X26Y171", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y171": "SLICEL", + "SLICE_X37Y171": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y172": { + "bits": {}, + "grid_x": 69, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X26Y172", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y172": "SLICEL", + "SLICE_X37Y172": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y173": { + "bits": {}, + "grid_x": 69, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X26Y173", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y173": "SLICEL", + "SLICE_X37Y173": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y174": { + "bits": {}, + "grid_x": 69, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X26Y174", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y174": "SLICEL", + "SLICE_X37Y174": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y175": { + "bits": {}, + "grid_x": 69, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X26Y175", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y175": "SLICEL", + "SLICE_X37Y175": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y176": { + "bits": {}, + "grid_x": 69, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X26Y176", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y176": "SLICEL", + "SLICE_X37Y176": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y177": { + "bits": {}, + "grid_x": 69, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X26Y177", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y177": "SLICEL", + "SLICE_X37Y177": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y178": { + "bits": {}, + "grid_x": 69, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X26Y178", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y178": "SLICEL", + "SLICE_X37Y178": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y179": { + "bits": {}, + "grid_x": 69, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X26Y179", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y179": "SLICEL", + "SLICE_X37Y179": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y18": { + "bits": {}, + "grid_x": 69, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X26Y18", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y18": "SLICEL", + "SLICE_X37Y18": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y180": { + "bits": {}, + "grid_x": 69, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X26Y180", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y180": "SLICEL", + "SLICE_X37Y180": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y181": { + "bits": {}, + "grid_x": 69, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X26Y181", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y181": "SLICEL", + "SLICE_X37Y181": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y182": { + "bits": {}, + "grid_x": 69, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X26Y182", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y182": "SLICEL", + "SLICE_X37Y182": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y183": { + "bits": {}, + "grid_x": 69, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X26Y183", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y183": "SLICEL", + "SLICE_X37Y183": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y184": { + "bits": {}, + "grid_x": 69, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X26Y184", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y184": "SLICEL", + "SLICE_X37Y184": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y185": { + "bits": {}, + "grid_x": 69, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X26Y185", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y185": "SLICEL", + "SLICE_X37Y185": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y186": { + "bits": {}, + "grid_x": 69, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X26Y186", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y186": "SLICEL", + "SLICE_X37Y186": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y187": { + "bits": {}, + "grid_x": 69, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X26Y187", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y187": "SLICEL", + "SLICE_X37Y187": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y188": { + "bits": {}, + "grid_x": 69, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X26Y188", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y188": "SLICEL", + "SLICE_X37Y188": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y189": { + "bits": {}, + "grid_x": 69, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X26Y189", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y189": "SLICEL", + "SLICE_X37Y189": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y19": { + "bits": {}, + "grid_x": 69, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X26Y19", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y19": "SLICEL", + "SLICE_X37Y19": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y190": { + "bits": {}, + "grid_x": 69, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X26Y190", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y190": "SLICEL", + "SLICE_X37Y190": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y191": { + "bits": {}, + "grid_x": 69, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X26Y191", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y191": "SLICEL", + "SLICE_X37Y191": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y192": { + "bits": {}, + "grid_x": 69, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X26Y192", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y192": "SLICEL", + "SLICE_X37Y192": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y193": { + "bits": {}, + "grid_x": 69, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X26Y193", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y193": "SLICEL", + "SLICE_X37Y193": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y194": { + "bits": {}, + "grid_x": 69, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X26Y194", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y194": "SLICEL", + "SLICE_X37Y194": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y195": { + "bits": {}, + "grid_x": 69, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X26Y195", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y195": "SLICEL", + "SLICE_X37Y195": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y196": { + "bits": {}, + "grid_x": 69, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X26Y196", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y196": "SLICEL", + "SLICE_X37Y196": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y197": { + "bits": {}, + "grid_x": 69, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X26Y197", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y197": "SLICEL", + "SLICE_X37Y197": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y198": { + "bits": {}, + "grid_x": 69, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X26Y198", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y198": "SLICEL", + "SLICE_X37Y198": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y199": { + "bits": {}, + "grid_x": 69, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X26Y199", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y199": "SLICEL", + "SLICE_X37Y199": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y2": { + "bits": {}, + "grid_x": 69, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X26Y2", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y2": "SLICEL", + "SLICE_X37Y2": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y20": { + "bits": {}, + "grid_x": 69, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X26Y20", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y20": "SLICEL", + "SLICE_X37Y20": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y21": { + "bits": {}, + "grid_x": 69, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X26Y21", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y21": "SLICEL", + "SLICE_X37Y21": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y22": { + "bits": {}, + "grid_x": 69, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X26Y22", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y22": "SLICEL", + "SLICE_X37Y22": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y23": { + "bits": {}, + "grid_x": 69, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X26Y23", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y23": "SLICEL", + "SLICE_X37Y23": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y24": { + "bits": {}, + "grid_x": 69, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X26Y24", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y24": "SLICEL", + "SLICE_X37Y24": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y25": { + "bits": {}, + "grid_x": 69, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X26Y25", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y25": "SLICEL", + "SLICE_X37Y25": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y26": { + "bits": {}, + "grid_x": 69, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X26Y26", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y26": "SLICEL", + "SLICE_X37Y26": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y27": { + "bits": {}, + "grid_x": 69, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X26Y27", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y27": "SLICEL", + "SLICE_X37Y27": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y28": { + "bits": {}, + "grid_x": 69, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X26Y28", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y28": "SLICEL", + "SLICE_X37Y28": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y29": { + "bits": {}, + "grid_x": 69, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X26Y29", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y29": "SLICEL", + "SLICE_X37Y29": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y3": { + "bits": {}, + "grid_x": 69, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X26Y3", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y3": "SLICEL", + "SLICE_X37Y3": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y30": { + "bits": {}, + "grid_x": 69, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X26Y30", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y30": "SLICEL", + "SLICE_X37Y30": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y31": { + "bits": {}, + "grid_x": 69, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X26Y31", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y31": "SLICEL", + "SLICE_X37Y31": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y32": { + "bits": {}, + "grid_x": 69, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X26Y32", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y32": "SLICEL", + "SLICE_X37Y32": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y33": { + "bits": {}, + "grid_x": 69, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X26Y33", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y33": "SLICEL", + "SLICE_X37Y33": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y34": { + "bits": {}, + "grid_x": 69, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X26Y34", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y34": "SLICEL", + "SLICE_X37Y34": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y35": { + "bits": {}, + "grid_x": 69, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X26Y35", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y35": "SLICEL", + "SLICE_X37Y35": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y36": { + "bits": {}, + "grid_x": 69, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X26Y36", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y36": "SLICEL", + "SLICE_X37Y36": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y37": { + "bits": {}, + "grid_x": 69, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X26Y37", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y37": "SLICEL", + "SLICE_X37Y37": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y38": { + "bits": {}, + "grid_x": 69, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X26Y38", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y38": "SLICEL", + "SLICE_X37Y38": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y39": { + "bits": {}, + "grid_x": 69, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X26Y39", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y39": "SLICEL", + "SLICE_X37Y39": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y4": { + "bits": {}, + "grid_x": 69, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X26Y4", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y4": "SLICEL", + "SLICE_X37Y4": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y40": { + "bits": {}, + "grid_x": 69, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X26Y40", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y40": "SLICEL", + "SLICE_X37Y40": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y41": { + "bits": {}, + "grid_x": 69, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X26Y41", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y41": "SLICEL", + "SLICE_X37Y41": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y42": { + "bits": {}, + "grid_x": 69, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X26Y42", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y42": "SLICEL", + "SLICE_X37Y42": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y43": { + "bits": {}, + "grid_x": 69, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X26Y43", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y43": "SLICEL", + "SLICE_X37Y43": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y44": { + "bits": {}, + "grid_x": 69, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X26Y44", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y44": "SLICEL", + "SLICE_X37Y44": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y45": { + "bits": {}, + "grid_x": 69, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X26Y45", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y45": "SLICEL", + "SLICE_X37Y45": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y46": { + "bits": {}, + "grid_x": 69, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X26Y46", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y46": "SLICEL", + "SLICE_X37Y46": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y47": { + "bits": {}, + "grid_x": 69, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X26Y47", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y47": "SLICEL", + "SLICE_X37Y47": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y48": { + "bits": {}, + "grid_x": 69, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X26Y48", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y48": "SLICEL", + "SLICE_X37Y48": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y49": { + "bits": {}, + "grid_x": 69, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X26Y49", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y49": "SLICEL", + "SLICE_X37Y49": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y5": { + "bits": {}, + "grid_x": 69, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X26Y5", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y5": "SLICEL", + "SLICE_X37Y5": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y50": { + "bits": {}, + "grid_x": 69, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X26Y50", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y50": "SLICEL", + "SLICE_X37Y50": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y51": { + "bits": {}, + "grid_x": 69, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X26Y51", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y51": "SLICEL", + "SLICE_X37Y51": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y52": { + "bits": {}, + "grid_x": 69, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X26Y52", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y52": "SLICEL", + "SLICE_X37Y52": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y53": { + "bits": {}, + "grid_x": 69, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X26Y53", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y53": "SLICEL", + "SLICE_X37Y53": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y54": { + "bits": {}, + "grid_x": 69, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X26Y54", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y54": "SLICEL", + "SLICE_X37Y54": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y55": { + "bits": {}, + "grid_x": 69, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X26Y55", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y55": "SLICEL", + "SLICE_X37Y55": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y56": { + "bits": {}, + "grid_x": 69, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X26Y56", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y56": "SLICEL", + "SLICE_X37Y56": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y57": { + "bits": {}, + "grid_x": 69, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X26Y57", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y57": "SLICEL", + "SLICE_X37Y57": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y58": { + "bits": {}, + "grid_x": 69, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X26Y58", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y58": "SLICEL", + "SLICE_X37Y58": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y59": { + "bits": {}, + "grid_x": 69, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X26Y59", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y59": "SLICEL", + "SLICE_X37Y59": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y6": { + "bits": {}, + "grid_x": 69, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X26Y6", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y6": "SLICEL", + "SLICE_X37Y6": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y60": { + "bits": {}, + "grid_x": 69, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X26Y60", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y60": "SLICEL", + "SLICE_X37Y60": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y61": { + "bits": {}, + "grid_x": 69, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X26Y61", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y61": "SLICEL", + "SLICE_X37Y61": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y62": { + "bits": {}, + "grid_x": 69, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X26Y62", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y62": "SLICEL", + "SLICE_X37Y62": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y63": { + "bits": {}, + "grid_x": 69, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X26Y63", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y63": "SLICEL", + "SLICE_X37Y63": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y64": { + "bits": {}, + "grid_x": 69, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X26Y64", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y64": "SLICEL", + "SLICE_X37Y64": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y65": { + "bits": {}, + "grid_x": 69, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X26Y65", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y65": "SLICEL", + "SLICE_X37Y65": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y66": { + "bits": {}, + "grid_x": 69, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X26Y66", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y66": "SLICEL", + "SLICE_X37Y66": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y67": { + "bits": {}, + "grid_x": 69, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X26Y67", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y67": "SLICEL", + "SLICE_X37Y67": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y68": { + "bits": {}, + "grid_x": 69, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X26Y68", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y68": "SLICEL", + "SLICE_X37Y68": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y69": { + "bits": {}, + "grid_x": 69, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X26Y69", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y69": "SLICEL", + "SLICE_X37Y69": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y7": { + "bits": {}, + "grid_x": 69, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X26Y7", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y7": "SLICEL", + "SLICE_X37Y7": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y70": { + "bits": {}, + "grid_x": 69, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X26Y70", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y70": "SLICEL", + "SLICE_X37Y70": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y71": { + "bits": {}, + "grid_x": 69, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X26Y71", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y71": "SLICEL", + "SLICE_X37Y71": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y72": { + "bits": {}, + "grid_x": 69, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X26Y72", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y72": "SLICEL", + "SLICE_X37Y72": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y73": { + "bits": {}, + "grid_x": 69, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X26Y73", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y73": "SLICEL", + "SLICE_X37Y73": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y74": { + "bits": {}, + "grid_x": 69, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X26Y74", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y74": "SLICEL", + "SLICE_X37Y74": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y75": { + "bits": {}, + "grid_x": 69, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X26Y75", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y75": "SLICEL", + "SLICE_X37Y75": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y76": { + "bits": {}, + "grid_x": 69, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X26Y76", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y76": "SLICEL", + "SLICE_X37Y76": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y77": { + "bits": {}, + "grid_x": 69, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X26Y77", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y77": "SLICEL", + "SLICE_X37Y77": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y78": { + "bits": {}, + "grid_x": 69, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X26Y78", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y78": "SLICEL", + "SLICE_X37Y78": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y79": { + "bits": {}, + "grid_x": 69, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X26Y79", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y79": "SLICEL", + "SLICE_X37Y79": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y8": { + "bits": {}, + "grid_x": 69, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X26Y8", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y8": "SLICEL", + "SLICE_X37Y8": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y80": { + "bits": {}, + "grid_x": 69, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X26Y80", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y80": "SLICEL", + "SLICE_X37Y80": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y81": { + "bits": {}, + "grid_x": 69, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X26Y81", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y81": "SLICEL", + "SLICE_X37Y81": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y82": { + "bits": {}, + "grid_x": 69, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X26Y82", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y82": "SLICEL", + "SLICE_X37Y82": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y83": { + "bits": {}, + "grid_x": 69, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X26Y83", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y83": "SLICEL", + "SLICE_X37Y83": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y84": { + "bits": {}, + "grid_x": 69, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X26Y84", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y84": "SLICEL", + "SLICE_X37Y84": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y85": { + "bits": {}, + "grid_x": 69, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X26Y85", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y85": "SLICEL", + "SLICE_X37Y85": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y86": { + "bits": {}, + "grid_x": 69, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X26Y86", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y86": "SLICEL", + "SLICE_X37Y86": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y87": { + "bits": {}, + "grid_x": 69, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X26Y87", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y87": "SLICEL", + "SLICE_X37Y87": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y88": { + "bits": {}, + "grid_x": 69, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X26Y88", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y88": "SLICEL", + "SLICE_X37Y88": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y89": { + "bits": {}, + "grid_x": 69, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X26Y89", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y89": "SLICEL", + "SLICE_X37Y89": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y9": { + "bits": {}, + "grid_x": 69, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X26Y9", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y9": "SLICEL", + "SLICE_X37Y9": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y90": { + "bits": {}, + "grid_x": 69, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X26Y90", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y90": "SLICEL", + "SLICE_X37Y90": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y91": { + "bits": {}, + "grid_x": 69, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X26Y91", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y91": "SLICEL", + "SLICE_X37Y91": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y92": { + "bits": {}, + "grid_x": 69, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X26Y92", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y92": "SLICEL", + "SLICE_X37Y92": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y93": { + "bits": {}, + "grid_x": 69, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X26Y93", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y93": "SLICEL", + "SLICE_X37Y93": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y94": { + "bits": {}, + "grid_x": 69, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X26Y94", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y94": "SLICEL", + "SLICE_X37Y94": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y95": { + "bits": {}, + "grid_x": 69, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X26Y95", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y95": "SLICEL", + "SLICE_X37Y95": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y96": { + "bits": {}, + "grid_x": 69, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X26Y96", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y96": "SLICEL", + "SLICE_X37Y96": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y97": { + "bits": {}, + "grid_x": 69, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X26Y97", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y97": "SLICEL", + "SLICE_X37Y97": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y98": { + "bits": {}, + "grid_x": 69, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X26Y98", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y98": "SLICEL", + "SLICE_X37Y98": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X26Y99": { + "bits": {}, + "grid_x": 69, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X26Y99", + "segment_type": "clbll_l", + "sites": { + "SLICE_X36Y99": "SLICEL", + "SLICE_X37Y99": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y0": { + "bits": {}, + "grid_x": 73, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X28Y0", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y0": "SLICEL", + "SLICE_X41Y0": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y1": { + "bits": {}, + "grid_x": 73, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X28Y1", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y1": "SLICEL", + "SLICE_X41Y1": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y10": { + "bits": {}, + "grid_x": 73, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X28Y10", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y10": "SLICEL", + "SLICE_X41Y10": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y11": { + "bits": {}, + "grid_x": 73, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X28Y11", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y11": "SLICEL", + "SLICE_X41Y11": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y12": { + "bits": {}, + "grid_x": 73, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X28Y12", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y12": "SLICEL", + "SLICE_X41Y12": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y125": { + "bits": {}, + "grid_x": 73, + "grid_y": 77, + "segment": "SEG_CLBLL_L_X28Y125", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y125": "SLICEL", + "SLICE_X41Y125": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y126": { + "bits": {}, + "grid_x": 73, + "grid_y": 76, + "segment": "SEG_CLBLL_L_X28Y126", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y126": "SLICEL", + "SLICE_X41Y126": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y127": { + "bits": {}, + "grid_x": 73, + "grid_y": 75, + "segment": "SEG_CLBLL_L_X28Y127", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y127": "SLICEL", + "SLICE_X41Y127": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y128": { + "bits": {}, + "grid_x": 73, + "grid_y": 74, + "segment": "SEG_CLBLL_L_X28Y128", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y128": "SLICEL", + "SLICE_X41Y128": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y129": { + "bits": {}, + "grid_x": 73, + "grid_y": 73, + "segment": "SEG_CLBLL_L_X28Y129", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y129": "SLICEL", + "SLICE_X41Y129": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y13": { + "bits": {}, + "grid_x": 73, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X28Y13", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y13": "SLICEL", + "SLICE_X41Y13": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y130": { + "bits": {}, + "grid_x": 73, + "grid_y": 72, + "segment": "SEG_CLBLL_L_X28Y130", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y130": "SLICEL", + "SLICE_X41Y130": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y131": { + "bits": {}, + "grid_x": 73, + "grid_y": 71, + "segment": "SEG_CLBLL_L_X28Y131", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y131": "SLICEL", + "SLICE_X41Y131": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y132": { + "bits": {}, + "grid_x": 73, + "grid_y": 70, + "segment": "SEG_CLBLL_L_X28Y132", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y132": "SLICEL", + "SLICE_X41Y132": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y133": { + "bits": {}, + "grid_x": 73, + "grid_y": 69, + "segment": "SEG_CLBLL_L_X28Y133", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y133": "SLICEL", + "SLICE_X41Y133": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y134": { + "bits": {}, + "grid_x": 73, + "grid_y": 68, + "segment": "SEG_CLBLL_L_X28Y134", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y134": "SLICEL", + "SLICE_X41Y134": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y135": { + "bits": {}, + "grid_x": 73, + "grid_y": 67, + "segment": "SEG_CLBLL_L_X28Y135", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y135": "SLICEL", + "SLICE_X41Y135": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y136": { + "bits": {}, + "grid_x": 73, + "grid_y": 66, + "segment": "SEG_CLBLL_L_X28Y136", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y136": "SLICEL", + "SLICE_X41Y136": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y137": { + "bits": {}, + "grid_x": 73, + "grid_y": 65, + "segment": "SEG_CLBLL_L_X28Y137", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y137": "SLICEL", + "SLICE_X41Y137": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y138": { + "bits": {}, + "grid_x": 73, + "grid_y": 64, + "segment": "SEG_CLBLL_L_X28Y138", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y138": "SLICEL", + "SLICE_X41Y138": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y139": { + "bits": {}, + "grid_x": 73, + "grid_y": 63, + "segment": "SEG_CLBLL_L_X28Y139", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y139": "SLICEL", + "SLICE_X41Y139": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y14": { + "bits": {}, + "grid_x": 73, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X28Y14", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y14": "SLICEL", + "SLICE_X41Y14": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y140": { + "bits": {}, + "grid_x": 73, + "grid_y": 62, + "segment": "SEG_CLBLL_L_X28Y140", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y140": "SLICEL", + "SLICE_X41Y140": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y141": { + "bits": {}, + "grid_x": 73, + "grid_y": 61, + "segment": "SEG_CLBLL_L_X28Y141", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y141": "SLICEL", + "SLICE_X41Y141": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y142": { + "bits": {}, + "grid_x": 73, + "grid_y": 60, + "segment": "SEG_CLBLL_L_X28Y142", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y142": "SLICEL", + "SLICE_X41Y142": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y143": { + "bits": {}, + "grid_x": 73, + "grid_y": 59, + "segment": "SEG_CLBLL_L_X28Y143", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y143": "SLICEL", + "SLICE_X41Y143": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y144": { + "bits": {}, + "grid_x": 73, + "grid_y": 58, + "segment": "SEG_CLBLL_L_X28Y144", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y144": "SLICEL", + "SLICE_X41Y144": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y145": { + "bits": {}, + "grid_x": 73, + "grid_y": 57, + "segment": "SEG_CLBLL_L_X28Y145", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y145": "SLICEL", + "SLICE_X41Y145": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y146": { + "bits": {}, + "grid_x": 73, + "grid_y": 56, + "segment": "SEG_CLBLL_L_X28Y146", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y146": "SLICEL", + "SLICE_X41Y146": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y147": { + "bits": {}, + "grid_x": 73, + "grid_y": 55, + "segment": "SEG_CLBLL_L_X28Y147", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y147": "SLICEL", + "SLICE_X41Y147": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y148": { + "bits": {}, + "grid_x": 73, + "grid_y": 54, + "segment": "SEG_CLBLL_L_X28Y148", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y148": "SLICEL", + "SLICE_X41Y148": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y149": { + "bits": {}, + "grid_x": 73, + "grid_y": 53, + "segment": "SEG_CLBLL_L_X28Y149", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y149": "SLICEL", + "SLICE_X41Y149": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y15": { + "bits": {}, + "grid_x": 73, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X28Y15", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y15": "SLICEL", + "SLICE_X41Y15": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y150": { + "bits": {}, + "grid_x": 73, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X28Y150", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y150": "SLICEL", + "SLICE_X41Y150": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y151": { + "bits": {}, + "grid_x": 73, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X28Y151", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y151": "SLICEL", + "SLICE_X41Y151": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y152": { + "bits": {}, + "grid_x": 73, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X28Y152", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y152": "SLICEL", + "SLICE_X41Y152": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y153": { + "bits": {}, + "grid_x": 73, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X28Y153", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y153": "SLICEL", + "SLICE_X41Y153": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y154": { + "bits": {}, + "grid_x": 73, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X28Y154", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y154": "SLICEL", + "SLICE_X41Y154": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y155": { + "bits": {}, + "grid_x": 73, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X28Y155", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y155": "SLICEL", + "SLICE_X41Y155": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y156": { + "bits": {}, + "grid_x": 73, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X28Y156", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y156": "SLICEL", + "SLICE_X41Y156": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y157": { + "bits": {}, + "grid_x": 73, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X28Y157", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y157": "SLICEL", + "SLICE_X41Y157": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y158": { + "bits": {}, + "grid_x": 73, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X28Y158", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y158": "SLICEL", + "SLICE_X41Y158": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y159": { + "bits": {}, + "grid_x": 73, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X28Y159", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y159": "SLICEL", + "SLICE_X41Y159": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y16": { + "bits": {}, + "grid_x": 73, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X28Y16", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y16": "SLICEL", + "SLICE_X41Y16": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y160": { + "bits": {}, + "grid_x": 73, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X28Y160", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y160": "SLICEL", + "SLICE_X41Y160": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y161": { + "bits": {}, + "grid_x": 73, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X28Y161", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y161": "SLICEL", + "SLICE_X41Y161": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y162": { + "bits": {}, + "grid_x": 73, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X28Y162", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y162": "SLICEL", + "SLICE_X41Y162": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y163": { + "bits": {}, + "grid_x": 73, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X28Y163", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y163": "SLICEL", + "SLICE_X41Y163": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y164": { + "bits": {}, + "grid_x": 73, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X28Y164", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y164": "SLICEL", + "SLICE_X41Y164": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y165": { + "bits": {}, + "grid_x": 73, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X28Y165", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y165": "SLICEL", + "SLICE_X41Y165": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y166": { + "bits": {}, + "grid_x": 73, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X28Y166", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y166": "SLICEL", + "SLICE_X41Y166": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y167": { + "bits": {}, + "grid_x": 73, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X28Y167", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y167": "SLICEL", + "SLICE_X41Y167": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y168": { + "bits": {}, + "grid_x": 73, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X28Y168", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y168": "SLICEL", + "SLICE_X41Y168": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y169": { + "bits": {}, + "grid_x": 73, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X28Y169", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y169": "SLICEL", + "SLICE_X41Y169": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y17": { + "bits": {}, + "grid_x": 73, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X28Y17", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y17": "SLICEL", + "SLICE_X41Y17": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y170": { + "bits": {}, + "grid_x": 73, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X28Y170", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y170": "SLICEL", + "SLICE_X41Y170": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y171": { + "bits": {}, + "grid_x": 73, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X28Y171", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y171": "SLICEL", + "SLICE_X41Y171": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y172": { + "bits": {}, + "grid_x": 73, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X28Y172", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y172": "SLICEL", + "SLICE_X41Y172": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y173": { + "bits": {}, + "grid_x": 73, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X28Y173", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y173": "SLICEL", + "SLICE_X41Y173": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y174": { + "bits": {}, + "grid_x": 73, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X28Y174", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y174": "SLICEL", + "SLICE_X41Y174": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y175": { + "bits": {}, + "grid_x": 73, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X28Y175", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y175": "SLICEL", + "SLICE_X41Y175": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y176": { + "bits": {}, + "grid_x": 73, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X28Y176", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y176": "SLICEL", + "SLICE_X41Y176": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y177": { + "bits": {}, + "grid_x": 73, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X28Y177", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y177": "SLICEL", + "SLICE_X41Y177": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y178": { + "bits": {}, + "grid_x": 73, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X28Y178", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y178": "SLICEL", + "SLICE_X41Y178": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y179": { + "bits": {}, + "grid_x": 73, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X28Y179", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y179": "SLICEL", + "SLICE_X41Y179": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y18": { + "bits": {}, + "grid_x": 73, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X28Y18", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y18": "SLICEL", + "SLICE_X41Y18": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y180": { + "bits": {}, + "grid_x": 73, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X28Y180", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y180": "SLICEL", + "SLICE_X41Y180": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y181": { + "bits": {}, + "grid_x": 73, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X28Y181", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y181": "SLICEL", + "SLICE_X41Y181": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y182": { + "bits": {}, + "grid_x": 73, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X28Y182", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y182": "SLICEL", + "SLICE_X41Y182": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y183": { + "bits": {}, + "grid_x": 73, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X28Y183", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y183": "SLICEL", + "SLICE_X41Y183": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y184": { + "bits": {}, + "grid_x": 73, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X28Y184", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y184": "SLICEL", + "SLICE_X41Y184": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y185": { + "bits": {}, + "grid_x": 73, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X28Y185", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y185": "SLICEL", + "SLICE_X41Y185": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y186": { + "bits": {}, + "grid_x": 73, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X28Y186", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y186": "SLICEL", + "SLICE_X41Y186": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y187": { + "bits": {}, + "grid_x": 73, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X28Y187", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y187": "SLICEL", + "SLICE_X41Y187": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y188": { + "bits": {}, + "grid_x": 73, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X28Y188", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y188": "SLICEL", + "SLICE_X41Y188": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y189": { + "bits": {}, + "grid_x": 73, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X28Y189", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y189": "SLICEL", + "SLICE_X41Y189": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y19": { + "bits": {}, + "grid_x": 73, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X28Y19", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y19": "SLICEL", + "SLICE_X41Y19": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y190": { + "bits": {}, + "grid_x": 73, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X28Y190", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y190": "SLICEL", + "SLICE_X41Y190": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y191": { + "bits": {}, + "grid_x": 73, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X28Y191", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y191": "SLICEL", + "SLICE_X41Y191": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y192": { + "bits": {}, + "grid_x": 73, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X28Y192", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y192": "SLICEL", + "SLICE_X41Y192": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y193": { + "bits": {}, + "grid_x": 73, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X28Y193", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y193": "SLICEL", + "SLICE_X41Y193": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y194": { + "bits": {}, + "grid_x": 73, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X28Y194", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y194": "SLICEL", + "SLICE_X41Y194": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y195": { + "bits": {}, + "grid_x": 73, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X28Y195", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y195": "SLICEL", + "SLICE_X41Y195": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y196": { + "bits": {}, + "grid_x": 73, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X28Y196", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y196": "SLICEL", + "SLICE_X41Y196": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y197": { + "bits": {}, + "grid_x": 73, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X28Y197", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y197": "SLICEL", + "SLICE_X41Y197": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y198": { + "bits": {}, + "grid_x": 73, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X28Y198", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y198": "SLICEL", + "SLICE_X41Y198": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y199": { + "bits": {}, + "grid_x": 73, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X28Y199", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y199": "SLICEL", + "SLICE_X41Y199": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y2": { + "bits": {}, + "grid_x": 73, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X28Y2", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y2": "SLICEL", + "SLICE_X41Y2": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y20": { + "bits": {}, + "grid_x": 73, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X28Y20", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y20": "SLICEL", + "SLICE_X41Y20": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y21": { + "bits": {}, + "grid_x": 73, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X28Y21", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y21": "SLICEL", + "SLICE_X41Y21": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y22": { + "bits": {}, + "grid_x": 73, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X28Y22", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y22": "SLICEL", + "SLICE_X41Y22": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y23": { + "bits": {}, + "grid_x": 73, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X28Y23", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y23": "SLICEL", + "SLICE_X41Y23": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y24": { + "bits": {}, + "grid_x": 73, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X28Y24", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y24": "SLICEL", + "SLICE_X41Y24": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y25": { + "bits": {}, + "grid_x": 73, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X28Y25", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y25": "SLICEL", + "SLICE_X41Y25": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y26": { + "bits": {}, + "grid_x": 73, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X28Y26", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y26": "SLICEL", + "SLICE_X41Y26": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y27": { + "bits": {}, + "grid_x": 73, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X28Y27", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y27": "SLICEL", + "SLICE_X41Y27": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y28": { + "bits": {}, + "grid_x": 73, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X28Y28", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y28": "SLICEL", + "SLICE_X41Y28": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y29": { + "bits": {}, + "grid_x": 73, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X28Y29", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y29": "SLICEL", + "SLICE_X41Y29": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y3": { + "bits": {}, + "grid_x": 73, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X28Y3", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y3": "SLICEL", + "SLICE_X41Y3": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y30": { + "bits": {}, + "grid_x": 73, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X28Y30", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y30": "SLICEL", + "SLICE_X41Y30": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y31": { + "bits": {}, + "grid_x": 73, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X28Y31", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y31": "SLICEL", + "SLICE_X41Y31": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y32": { + "bits": {}, + "grid_x": 73, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X28Y32", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y32": "SLICEL", + "SLICE_X41Y32": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y33": { + "bits": {}, + "grid_x": 73, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X28Y33", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y33": "SLICEL", + "SLICE_X41Y33": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y34": { + "bits": {}, + "grid_x": 73, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X28Y34", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y34": "SLICEL", + "SLICE_X41Y34": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y35": { + "bits": {}, + "grid_x": 73, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X28Y35", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y35": "SLICEL", + "SLICE_X41Y35": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y36": { + "bits": {}, + "grid_x": 73, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X28Y36", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y36": "SLICEL", + "SLICE_X41Y36": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y37": { + "bits": {}, + "grid_x": 73, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X28Y37", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y37": "SLICEL", + "SLICE_X41Y37": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y38": { + "bits": {}, + "grid_x": 73, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X28Y38", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y38": "SLICEL", + "SLICE_X41Y38": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y39": { + "bits": {}, + "grid_x": 73, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X28Y39", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y39": "SLICEL", + "SLICE_X41Y39": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y4": { + "bits": {}, + "grid_x": 73, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X28Y4", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y4": "SLICEL", + "SLICE_X41Y4": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y40": { + "bits": {}, + "grid_x": 73, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X28Y40", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y40": "SLICEL", + "SLICE_X41Y40": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y41": { + "bits": {}, + "grid_x": 73, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X28Y41", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y41": "SLICEL", + "SLICE_X41Y41": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y42": { + "bits": {}, + "grid_x": 73, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X28Y42", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y42": "SLICEL", + "SLICE_X41Y42": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y43": { + "bits": {}, + "grid_x": 73, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X28Y43", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y43": "SLICEL", + "SLICE_X41Y43": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y44": { + "bits": {}, + "grid_x": 73, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X28Y44", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y44": "SLICEL", + "SLICE_X41Y44": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y45": { + "bits": {}, + "grid_x": 73, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X28Y45", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y45": "SLICEL", + "SLICE_X41Y45": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y46": { + "bits": {}, + "grid_x": 73, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X28Y46", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y46": "SLICEL", + "SLICE_X41Y46": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y47": { + "bits": {}, + "grid_x": 73, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X28Y47", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y47": "SLICEL", + "SLICE_X41Y47": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y48": { + "bits": {}, + "grid_x": 73, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X28Y48", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y48": "SLICEL", + "SLICE_X41Y48": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y49": { + "bits": {}, + "grid_x": 73, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X28Y49", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y49": "SLICEL", + "SLICE_X41Y49": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y5": { + "bits": {}, + "grid_x": 73, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X28Y5", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y5": "SLICEL", + "SLICE_X41Y5": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y50": { + "bits": {}, + "grid_x": 73, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X28Y50", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y50": "SLICEL", + "SLICE_X41Y50": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y51": { + "bits": {}, + "grid_x": 73, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X28Y51", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y51": "SLICEL", + "SLICE_X41Y51": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y52": { + "bits": {}, + "grid_x": 73, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X28Y52", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y52": "SLICEL", + "SLICE_X41Y52": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y53": { + "bits": {}, + "grid_x": 73, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X28Y53", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y53": "SLICEL", + "SLICE_X41Y53": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y54": { + "bits": {}, + "grid_x": 73, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X28Y54", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y54": "SLICEL", + "SLICE_X41Y54": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y55": { + "bits": {}, + "grid_x": 73, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X28Y55", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y55": "SLICEL", + "SLICE_X41Y55": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y56": { + "bits": {}, + "grid_x": 73, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X28Y56", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y56": "SLICEL", + "SLICE_X41Y56": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y57": { + "bits": {}, + "grid_x": 73, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X28Y57", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y57": "SLICEL", + "SLICE_X41Y57": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y58": { + "bits": {}, + "grid_x": 73, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X28Y58", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y58": "SLICEL", + "SLICE_X41Y58": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y59": { + "bits": {}, + "grid_x": 73, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X28Y59", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y59": "SLICEL", + "SLICE_X41Y59": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y6": { + "bits": {}, + "grid_x": 73, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X28Y6", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y6": "SLICEL", + "SLICE_X41Y6": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y60": { + "bits": {}, + "grid_x": 73, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X28Y60", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y60": "SLICEL", + "SLICE_X41Y60": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y61": { + "bits": {}, + "grid_x": 73, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X28Y61", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y61": "SLICEL", + "SLICE_X41Y61": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y62": { + "bits": {}, + "grid_x": 73, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X28Y62", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y62": "SLICEL", + "SLICE_X41Y62": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y63": { + "bits": {}, + "grid_x": 73, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X28Y63", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y63": "SLICEL", + "SLICE_X41Y63": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y64": { + "bits": {}, + "grid_x": 73, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X28Y64", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y64": "SLICEL", + "SLICE_X41Y64": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y65": { + "bits": {}, + "grid_x": 73, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X28Y65", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y65": "SLICEL", + "SLICE_X41Y65": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y66": { + "bits": {}, + "grid_x": 73, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X28Y66", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y66": "SLICEL", + "SLICE_X41Y66": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y67": { + "bits": {}, + "grid_x": 73, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X28Y67", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y67": "SLICEL", + "SLICE_X41Y67": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y68": { + "bits": {}, + "grid_x": 73, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X28Y68", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y68": "SLICEL", + "SLICE_X41Y68": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y69": { + "bits": {}, + "grid_x": 73, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X28Y69", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y69": "SLICEL", + "SLICE_X41Y69": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y7": { + "bits": {}, + "grid_x": 73, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X28Y7", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y7": "SLICEL", + "SLICE_X41Y7": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y70": { + "bits": {}, + "grid_x": 73, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X28Y70", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y70": "SLICEL", + "SLICE_X41Y70": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y71": { + "bits": {}, + "grid_x": 73, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X28Y71", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y71": "SLICEL", + "SLICE_X41Y71": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y72": { + "bits": {}, + "grid_x": 73, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X28Y72", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y72": "SLICEL", + "SLICE_X41Y72": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y73": { + "bits": {}, + "grid_x": 73, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X28Y73", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y73": "SLICEL", + "SLICE_X41Y73": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y74": { + "bits": {}, + "grid_x": 73, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X28Y74", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y74": "SLICEL", + "SLICE_X41Y74": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y75": { + "bits": {}, + "grid_x": 73, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X28Y75", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y75": "SLICEL", + "SLICE_X41Y75": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y76": { + "bits": {}, + "grid_x": 73, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X28Y76", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y76": "SLICEL", + "SLICE_X41Y76": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y77": { + "bits": {}, + "grid_x": 73, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X28Y77", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y77": "SLICEL", + "SLICE_X41Y77": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y78": { + "bits": {}, + "grid_x": 73, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X28Y78", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y78": "SLICEL", + "SLICE_X41Y78": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y79": { + "bits": {}, + "grid_x": 73, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X28Y79", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y79": "SLICEL", + "SLICE_X41Y79": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y8": { + "bits": {}, + "grid_x": 73, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X28Y8", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y8": "SLICEL", + "SLICE_X41Y8": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y80": { + "bits": {}, + "grid_x": 73, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X28Y80", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y80": "SLICEL", + "SLICE_X41Y80": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y81": { + "bits": {}, + "grid_x": 73, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X28Y81", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y81": "SLICEL", + "SLICE_X41Y81": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y82": { + "bits": {}, + "grid_x": 73, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X28Y82", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y82": "SLICEL", + "SLICE_X41Y82": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y83": { + "bits": {}, + "grid_x": 73, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X28Y83", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y83": "SLICEL", + "SLICE_X41Y83": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y84": { + "bits": {}, + "grid_x": 73, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X28Y84", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y84": "SLICEL", + "SLICE_X41Y84": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y85": { + "bits": {}, + "grid_x": 73, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X28Y85", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y85": "SLICEL", + "SLICE_X41Y85": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y86": { + "bits": {}, + "grid_x": 73, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X28Y86", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y86": "SLICEL", + "SLICE_X41Y86": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y87": { + "bits": {}, + "grid_x": 73, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X28Y87", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y87": "SLICEL", + "SLICE_X41Y87": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y88": { + "bits": {}, + "grid_x": 73, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X28Y88", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y88": "SLICEL", + "SLICE_X41Y88": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y89": { + "bits": {}, + "grid_x": 73, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X28Y89", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y89": "SLICEL", + "SLICE_X41Y89": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y9": { + "bits": {}, + "grid_x": 73, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X28Y9", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y9": "SLICEL", + "SLICE_X41Y9": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y90": { + "bits": {}, + "grid_x": 73, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X28Y90", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y90": "SLICEL", + "SLICE_X41Y90": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y91": { + "bits": {}, + "grid_x": 73, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X28Y91", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y91": "SLICEL", + "SLICE_X41Y91": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y92": { + "bits": {}, + "grid_x": 73, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X28Y92", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y92": "SLICEL", + "SLICE_X41Y92": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y93": { + "bits": {}, + "grid_x": 73, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X28Y93", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y93": "SLICEL", + "SLICE_X41Y93": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y94": { + "bits": {}, + "grid_x": 73, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X28Y94", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y94": "SLICEL", + "SLICE_X41Y94": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y95": { + "bits": {}, + "grid_x": 73, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X28Y95", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y95": "SLICEL", + "SLICE_X41Y95": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y96": { + "bits": {}, + "grid_x": 73, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X28Y96", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y96": "SLICEL", + "SLICE_X41Y96": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y97": { + "bits": {}, + "grid_x": 73, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X28Y97", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y97": "SLICEL", + "SLICE_X41Y97": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y98": { + "bits": {}, + "grid_x": 73, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X28Y98", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y98": "SLICEL", + "SLICE_X41Y98": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X28Y99": { + "bits": {}, + "grid_x": 73, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X28Y99", + "segment_type": "clbll_l", + "sites": { + "SLICE_X40Y99": "SLICEL", + "SLICE_X41Y99": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y0": { + "bits": {}, + "grid_x": 10, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X2Y0", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y0": "SLICEL", + "SLICE_X1Y0": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y1": { + "bits": {}, + "grid_x": 10, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X2Y1", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y1": "SLICEL", + "SLICE_X1Y1": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y10": { + "bits": {}, + "grid_x": 10, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X2Y10", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y10": "SLICEL", + "SLICE_X1Y10": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y100": { + "bits": {}, + "grid_x": 10, + "grid_y": 103, + "segment": "SEG_CLBLL_L_X2Y100", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y100": "SLICEL", + "SLICE_X1Y100": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y101": { + "bits": {}, + "grid_x": 10, + "grid_y": 102, + "segment": "SEG_CLBLL_L_X2Y101", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y101": "SLICEL", + "SLICE_X1Y101": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y102": { + "bits": {}, + "grid_x": 10, + "grid_y": 101, + "segment": "SEG_CLBLL_L_X2Y102", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y102": "SLICEL", + "SLICE_X1Y102": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y103": { + "bits": {}, + "grid_x": 10, + "grid_y": 100, + "segment": "SEG_CLBLL_L_X2Y103", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y103": "SLICEL", + "SLICE_X1Y103": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y104": { + "bits": {}, + "grid_x": 10, + "grid_y": 99, + "segment": "SEG_CLBLL_L_X2Y104", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y104": "SLICEL", + "SLICE_X1Y104": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y105": { + "bits": {}, + "grid_x": 10, + "grid_y": 98, + "segment": "SEG_CLBLL_L_X2Y105", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y105": "SLICEL", + "SLICE_X1Y105": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y106": { + "bits": {}, + "grid_x": 10, + "grid_y": 97, + "segment": "SEG_CLBLL_L_X2Y106", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y106": "SLICEL", + "SLICE_X1Y106": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y107": { + "bits": {}, + "grid_x": 10, + "grid_y": 96, + "segment": "SEG_CLBLL_L_X2Y107", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y107": "SLICEL", + "SLICE_X1Y107": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y108": { + "bits": {}, + "grid_x": 10, + "grid_y": 95, + "segment": "SEG_CLBLL_L_X2Y108", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y108": "SLICEL", + "SLICE_X1Y108": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y109": { + "bits": {}, + "grid_x": 10, + "grid_y": 94, + "segment": "SEG_CLBLL_L_X2Y109", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y109": "SLICEL", + "SLICE_X1Y109": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y11": { + "bits": {}, + "grid_x": 10, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X2Y11", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y11": "SLICEL", + "SLICE_X1Y11": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y110": { + "bits": {}, + "grid_x": 10, + "grid_y": 93, + "segment": "SEG_CLBLL_L_X2Y110", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y110": "SLICEL", + "SLICE_X1Y110": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y111": { + "bits": {}, + "grid_x": 10, + "grid_y": 92, + "segment": "SEG_CLBLL_L_X2Y111", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y111": "SLICEL", + "SLICE_X1Y111": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y112": { + "bits": {}, + "grid_x": 10, + "grid_y": 91, + "segment": "SEG_CLBLL_L_X2Y112", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y112": "SLICEL", + "SLICE_X1Y112": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y113": { + "bits": {}, + "grid_x": 10, + "grid_y": 90, + "segment": "SEG_CLBLL_L_X2Y113", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y113": "SLICEL", + "SLICE_X1Y113": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y114": { + "bits": {}, + "grid_x": 10, + "grid_y": 89, + "segment": "SEG_CLBLL_L_X2Y114", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y114": "SLICEL", + "SLICE_X1Y114": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y115": { + "bits": {}, + "grid_x": 10, + "grid_y": 88, + "segment": "SEG_CLBLL_L_X2Y115", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y115": "SLICEL", + "SLICE_X1Y115": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y116": { + "bits": {}, + "grid_x": 10, + "grid_y": 87, + "segment": "SEG_CLBLL_L_X2Y116", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y116": "SLICEL", + "SLICE_X1Y116": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y117": { + "bits": {}, + "grid_x": 10, + "grid_y": 86, + "segment": "SEG_CLBLL_L_X2Y117", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y117": "SLICEL", + "SLICE_X1Y117": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y118": { + "bits": {}, + "grid_x": 10, + "grid_y": 85, + "segment": "SEG_CLBLL_L_X2Y118", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y118": "SLICEL", + "SLICE_X1Y118": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y119": { + "bits": {}, + "grid_x": 10, + "grid_y": 84, + "segment": "SEG_CLBLL_L_X2Y119", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y119": "SLICEL", + "SLICE_X1Y119": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y12": { + "bits": {}, + "grid_x": 10, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X2Y12", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y12": "SLICEL", + "SLICE_X1Y12": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y120": { + "bits": {}, + "grid_x": 10, + "grid_y": 83, + "segment": "SEG_CLBLL_L_X2Y120", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y120": "SLICEL", + "SLICE_X1Y120": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y121": { + "bits": {}, + "grid_x": 10, + "grid_y": 82, + "segment": "SEG_CLBLL_L_X2Y121", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y121": "SLICEL", + "SLICE_X1Y121": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y122": { + "bits": {}, + "grid_x": 10, + "grid_y": 81, + "segment": "SEG_CLBLL_L_X2Y122", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y122": "SLICEL", + "SLICE_X1Y122": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y123": { + "bits": {}, + "grid_x": 10, + "grid_y": 80, + "segment": "SEG_CLBLL_L_X2Y123", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y123": "SLICEL", + "SLICE_X1Y123": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y124": { + "bits": {}, + "grid_x": 10, + "grid_y": 79, + "segment": "SEG_CLBLL_L_X2Y124", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y124": "SLICEL", + "SLICE_X1Y124": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y125": { + "bits": {}, + "grid_x": 10, + "grid_y": 77, + "segment": "SEG_CLBLL_L_X2Y125", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y125": "SLICEL", + "SLICE_X1Y125": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y126": { + "bits": {}, + "grid_x": 10, + "grid_y": 76, + "segment": "SEG_CLBLL_L_X2Y126", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y126": "SLICEL", + "SLICE_X1Y126": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y127": { + "bits": {}, + "grid_x": 10, + "grid_y": 75, + "segment": "SEG_CLBLL_L_X2Y127", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y127": "SLICEL", + "SLICE_X1Y127": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y128": { + "bits": {}, + "grid_x": 10, + "grid_y": 74, + "segment": "SEG_CLBLL_L_X2Y128", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y128": "SLICEL", + "SLICE_X1Y128": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y129": { + "bits": {}, + "grid_x": 10, + "grid_y": 73, + "segment": "SEG_CLBLL_L_X2Y129", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y129": "SLICEL", + "SLICE_X1Y129": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y13": { + "bits": {}, + "grid_x": 10, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X2Y13", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y13": "SLICEL", + "SLICE_X1Y13": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y130": { + "bits": {}, + "grid_x": 10, + "grid_y": 72, + "segment": "SEG_CLBLL_L_X2Y130", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y130": "SLICEL", + "SLICE_X1Y130": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y131": { + "bits": {}, + "grid_x": 10, + "grid_y": 71, + "segment": "SEG_CLBLL_L_X2Y131", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y131": "SLICEL", + "SLICE_X1Y131": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y132": { + "bits": {}, + "grid_x": 10, + "grid_y": 70, + "segment": "SEG_CLBLL_L_X2Y132", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y132": "SLICEL", + "SLICE_X1Y132": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y133": { + "bits": {}, + "grid_x": 10, + "grid_y": 69, + "segment": "SEG_CLBLL_L_X2Y133", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y133": "SLICEL", + "SLICE_X1Y133": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y134": { + "bits": {}, + "grid_x": 10, + "grid_y": 68, + "segment": "SEG_CLBLL_L_X2Y134", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y134": "SLICEL", + "SLICE_X1Y134": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y135": { + "bits": {}, + "grid_x": 10, + "grid_y": 67, + "segment": "SEG_CLBLL_L_X2Y135", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y135": "SLICEL", + "SLICE_X1Y135": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y136": { + "bits": {}, + "grid_x": 10, + "grid_y": 66, + "segment": "SEG_CLBLL_L_X2Y136", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y136": "SLICEL", + "SLICE_X1Y136": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y137": { + "bits": {}, + "grid_x": 10, + "grid_y": 65, + "segment": "SEG_CLBLL_L_X2Y137", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y137": "SLICEL", + "SLICE_X1Y137": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y138": { + "bits": {}, + "grid_x": 10, + "grid_y": 64, + "segment": "SEG_CLBLL_L_X2Y138", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y138": "SLICEL", + "SLICE_X1Y138": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y139": { + "bits": {}, + "grid_x": 10, + "grid_y": 63, + "segment": "SEG_CLBLL_L_X2Y139", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y139": "SLICEL", + "SLICE_X1Y139": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y14": { + "bits": {}, + "grid_x": 10, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X2Y14", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y14": "SLICEL", + "SLICE_X1Y14": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y140": { + "bits": {}, + "grid_x": 10, + "grid_y": 62, + "segment": "SEG_CLBLL_L_X2Y140", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y140": "SLICEL", + "SLICE_X1Y140": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y141": { + "bits": {}, + "grid_x": 10, + "grid_y": 61, + "segment": "SEG_CLBLL_L_X2Y141", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y141": "SLICEL", + "SLICE_X1Y141": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y142": { + "bits": {}, + "grid_x": 10, + "grid_y": 60, + "segment": "SEG_CLBLL_L_X2Y142", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y142": "SLICEL", + "SLICE_X1Y142": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y143": { + "bits": {}, + "grid_x": 10, + "grid_y": 59, + "segment": "SEG_CLBLL_L_X2Y143", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y143": "SLICEL", + "SLICE_X1Y143": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y144": { + "bits": {}, + "grid_x": 10, + "grid_y": 58, + "segment": "SEG_CLBLL_L_X2Y144", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y144": "SLICEL", + "SLICE_X1Y144": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y145": { + "bits": {}, + "grid_x": 10, + "grid_y": 57, + "segment": "SEG_CLBLL_L_X2Y145", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y145": "SLICEL", + "SLICE_X1Y145": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y146": { + "bits": {}, + "grid_x": 10, + "grid_y": 56, + "segment": "SEG_CLBLL_L_X2Y146", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y146": "SLICEL", + "SLICE_X1Y146": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y147": { + "bits": {}, + "grid_x": 10, + "grid_y": 55, + "segment": "SEG_CLBLL_L_X2Y147", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y147": "SLICEL", + "SLICE_X1Y147": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y148": { + "bits": {}, + "grid_x": 10, + "grid_y": 54, + "segment": "SEG_CLBLL_L_X2Y148", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y148": "SLICEL", + "SLICE_X1Y148": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y149": { + "bits": {}, + "grid_x": 10, + "grid_y": 53, + "segment": "SEG_CLBLL_L_X2Y149", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y149": "SLICEL", + "SLICE_X1Y149": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y15": { + "bits": {}, + "grid_x": 10, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X2Y15", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y15": "SLICEL", + "SLICE_X1Y15": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y150": { + "bits": {}, + "grid_x": 10, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X2Y150", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y150": "SLICEL", + "SLICE_X1Y150": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y151": { + "bits": {}, + "grid_x": 10, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X2Y151", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y151": "SLICEL", + "SLICE_X1Y151": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y152": { + "bits": {}, + "grid_x": 10, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X2Y152", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y152": "SLICEL", + "SLICE_X1Y152": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y153": { + "bits": {}, + "grid_x": 10, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X2Y153", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y153": "SLICEL", + "SLICE_X1Y153": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y154": { + "bits": {}, + "grid_x": 10, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X2Y154", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y154": "SLICEL", + "SLICE_X1Y154": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y155": { + "bits": {}, + "grid_x": 10, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X2Y155", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y155": "SLICEL", + "SLICE_X1Y155": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y156": { + "bits": {}, + "grid_x": 10, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X2Y156", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y156": "SLICEL", + "SLICE_X1Y156": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y157": { + "bits": {}, + "grid_x": 10, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X2Y157", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y157": "SLICEL", + "SLICE_X1Y157": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y158": { + "bits": {}, + "grid_x": 10, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X2Y158", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y158": "SLICEL", + "SLICE_X1Y158": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y159": { + "bits": {}, + "grid_x": 10, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X2Y159", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y159": "SLICEL", + "SLICE_X1Y159": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y16": { + "bits": {}, + "grid_x": 10, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X2Y16", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y16": "SLICEL", + "SLICE_X1Y16": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y160": { + "bits": {}, + "grid_x": 10, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X2Y160", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y160": "SLICEL", + "SLICE_X1Y160": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y161": { + "bits": {}, + "grid_x": 10, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X2Y161", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y161": "SLICEL", + "SLICE_X1Y161": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y162": { + "bits": {}, + "grid_x": 10, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X2Y162", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y162": "SLICEL", + "SLICE_X1Y162": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y163": { + "bits": {}, + "grid_x": 10, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X2Y163", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y163": "SLICEL", + "SLICE_X1Y163": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y164": { + "bits": {}, + "grid_x": 10, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X2Y164", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y164": "SLICEL", + "SLICE_X1Y164": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y165": { + "bits": {}, + "grid_x": 10, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X2Y165", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y165": "SLICEL", + "SLICE_X1Y165": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y166": { + "bits": {}, + "grid_x": 10, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X2Y166", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y166": "SLICEL", + "SLICE_X1Y166": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y167": { + "bits": {}, + "grid_x": 10, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X2Y167", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y167": "SLICEL", + "SLICE_X1Y167": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y168": { + "bits": {}, + "grid_x": 10, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X2Y168", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y168": "SLICEL", + "SLICE_X1Y168": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y169": { + "bits": {}, + "grid_x": 10, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X2Y169", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y169": "SLICEL", + "SLICE_X1Y169": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y17": { + "bits": {}, + "grid_x": 10, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X2Y17", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y17": "SLICEL", + "SLICE_X1Y17": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y170": { + "bits": {}, + "grid_x": 10, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X2Y170", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y170": "SLICEL", + "SLICE_X1Y170": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y171": { + "bits": {}, + "grid_x": 10, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X2Y171", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y171": "SLICEL", + "SLICE_X1Y171": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y172": { + "bits": {}, + "grid_x": 10, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X2Y172", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y172": "SLICEL", + "SLICE_X1Y172": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y173": { + "bits": {}, + "grid_x": 10, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X2Y173", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y173": "SLICEL", + "SLICE_X1Y173": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y174": { + "bits": {}, + "grid_x": 10, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X2Y174", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y174": "SLICEL", + "SLICE_X1Y174": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y175": { + "bits": {}, + "grid_x": 10, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X2Y175", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y175": "SLICEL", + "SLICE_X1Y175": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y176": { + "bits": {}, + "grid_x": 10, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X2Y176", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y176": "SLICEL", + "SLICE_X1Y176": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y177": { + "bits": {}, + "grid_x": 10, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X2Y177", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y177": "SLICEL", + "SLICE_X1Y177": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y178": { + "bits": {}, + "grid_x": 10, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X2Y178", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y178": "SLICEL", + "SLICE_X1Y178": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y179": { + "bits": {}, + "grid_x": 10, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X2Y179", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y179": "SLICEL", + "SLICE_X1Y179": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y18": { + "bits": {}, + "grid_x": 10, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X2Y18", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y18": "SLICEL", + "SLICE_X1Y18": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y180": { + "bits": {}, + "grid_x": 10, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X2Y180", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y180": "SLICEL", + "SLICE_X1Y180": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y181": { + "bits": {}, + "grid_x": 10, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X2Y181", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y181": "SLICEL", + "SLICE_X1Y181": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y182": { + "bits": {}, + "grid_x": 10, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X2Y182", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y182": "SLICEL", + "SLICE_X1Y182": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y183": { + "bits": {}, + "grid_x": 10, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X2Y183", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y183": "SLICEL", + "SLICE_X1Y183": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y184": { + "bits": {}, + "grid_x": 10, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X2Y184", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y184": "SLICEL", + "SLICE_X1Y184": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y185": { + "bits": {}, + "grid_x": 10, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X2Y185", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y185": "SLICEL", + "SLICE_X1Y185": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y186": { + "bits": {}, + "grid_x": 10, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X2Y186", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y186": "SLICEL", + "SLICE_X1Y186": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y187": { + "bits": {}, + "grid_x": 10, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X2Y187", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y187": "SLICEL", + "SLICE_X1Y187": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y188": { + "bits": {}, + "grid_x": 10, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X2Y188", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y188": "SLICEL", + "SLICE_X1Y188": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y189": { + "bits": {}, + "grid_x": 10, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X2Y189", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y189": "SLICEL", + "SLICE_X1Y189": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y19": { + "bits": {}, + "grid_x": 10, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X2Y19", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y19": "SLICEL", + "SLICE_X1Y19": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y190": { + "bits": {}, + "grid_x": 10, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X2Y190", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y190": "SLICEL", + "SLICE_X1Y190": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y191": { + "bits": {}, + "grid_x": 10, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X2Y191", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y191": "SLICEL", + "SLICE_X1Y191": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y192": { + "bits": {}, + "grid_x": 10, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X2Y192", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y192": "SLICEL", + "SLICE_X1Y192": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y193": { + "bits": {}, + "grid_x": 10, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X2Y193", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y193": "SLICEL", + "SLICE_X1Y193": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y194": { + "bits": {}, + "grid_x": 10, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X2Y194", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y194": "SLICEL", + "SLICE_X1Y194": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y195": { + "bits": {}, + "grid_x": 10, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X2Y195", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y195": "SLICEL", + "SLICE_X1Y195": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y196": { + "bits": {}, + "grid_x": 10, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X2Y196", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y196": "SLICEL", + "SLICE_X1Y196": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y197": { + "bits": {}, + "grid_x": 10, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X2Y197", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y197": "SLICEL", + "SLICE_X1Y197": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y198": { + "bits": {}, + "grid_x": 10, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X2Y198", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y198": "SLICEL", + "SLICE_X1Y198": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y199": { + "bits": {}, + "grid_x": 10, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X2Y199", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y199": "SLICEL", + "SLICE_X1Y199": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y2": { + "bits": {}, + "grid_x": 10, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X2Y2", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y2": "SLICEL", + "SLICE_X1Y2": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y20": { + "bits": {}, + "grid_x": 10, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X2Y20", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y20": "SLICEL", + "SLICE_X1Y20": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y21": { + "bits": {}, + "grid_x": 10, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X2Y21", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y21": "SLICEL", + "SLICE_X1Y21": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y22": { + "bits": {}, + "grid_x": 10, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X2Y22", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y22": "SLICEL", + "SLICE_X1Y22": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y23": { + "bits": {}, + "grid_x": 10, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X2Y23", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y23": "SLICEL", + "SLICE_X1Y23": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y24": { + "bits": {}, + "grid_x": 10, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X2Y24", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y24": "SLICEL", + "SLICE_X1Y24": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y25": { + "bits": {}, + "grid_x": 10, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X2Y25", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y25": "SLICEL", + "SLICE_X1Y25": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y26": { + "bits": {}, + "grid_x": 10, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X2Y26", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y26": "SLICEL", + "SLICE_X1Y26": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y27": { + "bits": {}, + "grid_x": 10, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X2Y27", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y27": "SLICEL", + "SLICE_X1Y27": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y28": { + "bits": {}, + "grid_x": 10, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X2Y28", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y28": "SLICEL", + "SLICE_X1Y28": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y29": { + "bits": {}, + "grid_x": 10, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X2Y29", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y29": "SLICEL", + "SLICE_X1Y29": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y3": { + "bits": {}, + "grid_x": 10, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X2Y3", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y3": "SLICEL", + "SLICE_X1Y3": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y30": { + "bits": {}, + "grid_x": 10, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X2Y30", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y30": "SLICEL", + "SLICE_X1Y30": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y31": { + "bits": {}, + "grid_x": 10, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X2Y31", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y31": "SLICEL", + "SLICE_X1Y31": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y32": { + "bits": {}, + "grid_x": 10, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X2Y32", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y32": "SLICEL", + "SLICE_X1Y32": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y33": { + "bits": {}, + "grid_x": 10, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X2Y33", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y33": "SLICEL", + "SLICE_X1Y33": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y34": { + "bits": {}, + "grid_x": 10, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X2Y34", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y34": "SLICEL", + "SLICE_X1Y34": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y35": { + "bits": {}, + "grid_x": 10, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X2Y35", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y35": "SLICEL", + "SLICE_X1Y35": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y36": { + "bits": {}, + "grid_x": 10, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X2Y36", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y36": "SLICEL", + "SLICE_X1Y36": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y37": { + "bits": {}, + "grid_x": 10, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X2Y37", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y37": "SLICEL", + "SLICE_X1Y37": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y38": { + "bits": {}, + "grid_x": 10, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X2Y38", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y38": "SLICEL", + "SLICE_X1Y38": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y39": { + "bits": {}, + "grid_x": 10, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X2Y39", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y39": "SLICEL", + "SLICE_X1Y39": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y4": { + "bits": {}, + "grid_x": 10, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X2Y4", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y4": "SLICEL", + "SLICE_X1Y4": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y40": { + "bits": {}, + "grid_x": 10, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X2Y40", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y40": "SLICEL", + "SLICE_X1Y40": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y41": { + "bits": {}, + "grid_x": 10, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X2Y41", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y41": "SLICEL", + "SLICE_X1Y41": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y42": { + "bits": {}, + "grid_x": 10, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X2Y42", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y42": "SLICEL", + "SLICE_X1Y42": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y43": { + "bits": {}, + "grid_x": 10, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X2Y43", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y43": "SLICEL", + "SLICE_X1Y43": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y44": { + "bits": {}, + "grid_x": 10, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X2Y44", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y44": "SLICEL", + "SLICE_X1Y44": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y45": { + "bits": {}, + "grid_x": 10, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X2Y45", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y45": "SLICEL", + "SLICE_X1Y45": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y46": { + "bits": {}, + "grid_x": 10, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X2Y46", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y46": "SLICEL", + "SLICE_X1Y46": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y47": { + "bits": {}, + "grid_x": 10, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X2Y47", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y47": "SLICEL", + "SLICE_X1Y47": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y48": { + "bits": {}, + "grid_x": 10, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X2Y48", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y48": "SLICEL", + "SLICE_X1Y48": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y49": { + "bits": {}, + "grid_x": 10, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X2Y49", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y49": "SLICEL", + "SLICE_X1Y49": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y5": { + "bits": {}, + "grid_x": 10, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X2Y5", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y5": "SLICEL", + "SLICE_X1Y5": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X2Y50", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y50": "SLICEL", + "SLICE_X1Y50": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X2Y51", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y51": "SLICEL", + "SLICE_X1Y51": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X2Y52", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y52": "SLICEL", + "SLICE_X1Y52": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X2Y53", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y53": "SLICEL", + "SLICE_X1Y53": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X2Y54", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y54": "SLICEL", + "SLICE_X1Y54": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X2Y55", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y55": "SLICEL", + "SLICE_X1Y55": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X2Y56", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y56": "SLICEL", + "SLICE_X1Y56": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X2Y57", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y57": "SLICEL", + "SLICE_X1Y57": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X2Y58", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y58": "SLICEL", + "SLICE_X1Y58": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X2Y59", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y59": "SLICEL", + "SLICE_X1Y59": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y6": { + "bits": {}, + "grid_x": 10, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X2Y6", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y6": "SLICEL", + "SLICE_X1Y6": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X2Y60", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y60": "SLICEL", + "SLICE_X1Y60": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X2Y61", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y61": "SLICEL", + "SLICE_X1Y61": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X2Y62", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y62": "SLICEL", + "SLICE_X1Y62": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X2Y63", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y63": "SLICEL", + "SLICE_X1Y63": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X2Y64", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y64": "SLICEL", + "SLICE_X1Y64": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X2Y65", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y65": "SLICEL", + "SLICE_X1Y65": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X2Y66", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y66": "SLICEL", + "SLICE_X1Y66": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X2Y67", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y67": "SLICEL", + "SLICE_X1Y67": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X2Y68", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y68": "SLICEL", + "SLICE_X1Y68": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X2Y69", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y69": "SLICEL", + "SLICE_X1Y69": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y7": { + "bits": {}, + "grid_x": 10, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X2Y7", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y7": "SLICEL", + "SLICE_X1Y7": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X2Y70", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y70": "SLICEL", + "SLICE_X1Y70": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X2Y71", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y71": "SLICEL", + "SLICE_X1Y71": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X2Y72", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y72": "SLICEL", + "SLICE_X1Y72": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X2Y73", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y73": "SLICEL", + "SLICE_X1Y73": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X2Y74", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y74": "SLICEL", + "SLICE_X1Y74": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X2Y75", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y75": "SLICEL", + "SLICE_X1Y75": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X2Y76", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y76": "SLICEL", + "SLICE_X1Y76": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X2Y77", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y77": "SLICEL", + "SLICE_X1Y77": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X2Y78", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y78": "SLICEL", + "SLICE_X1Y78": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X2Y79", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y79": "SLICEL", + "SLICE_X1Y79": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y8": { + "bits": {}, + "grid_x": 10, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X2Y8", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y8": "SLICEL", + "SLICE_X1Y8": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X2Y80", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y80": "SLICEL", + "SLICE_X1Y80": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X2Y81", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y81": "SLICEL", + "SLICE_X1Y81": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X2Y82", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y82": "SLICEL", + "SLICE_X1Y82": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X2Y83", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y83": "SLICEL", + "SLICE_X1Y83": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X2Y84", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y84": "SLICEL", + "SLICE_X1Y84": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X2Y85", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y85": "SLICEL", + "SLICE_X1Y85": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X2Y86", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y86": "SLICEL", + "SLICE_X1Y86": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X2Y87", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y87": "SLICEL", + "SLICE_X1Y87": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X2Y88", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y88": "SLICEL", + "SLICE_X1Y88": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X2Y89", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y89": "SLICEL", + "SLICE_X1Y89": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y9": { + "bits": {}, + "grid_x": 10, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X2Y9", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y9": "SLICEL", + "SLICE_X1Y9": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X2Y90", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y90": "SLICEL", + "SLICE_X1Y90": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X2Y91", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y91": "SLICEL", + "SLICE_X1Y91": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X2Y92", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y92": "SLICEL", + "SLICE_X1Y92": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X2Y93", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y93": "SLICEL", + "SLICE_X1Y93": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X2Y94", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y94": "SLICEL", + "SLICE_X1Y94": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X2Y95", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y95": "SLICEL", + "SLICE_X1Y95": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X2Y96", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y96": "SLICEL", + "SLICE_X1Y96": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X2Y97", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y97": "SLICEL", + "SLICE_X1Y97": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X2Y98", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y98": "SLICEL", + "SLICE_X1Y98": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X2Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 36, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 10, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X2Y99", + "segment_type": "clbll_l", + "sites": { + "SLICE_X0Y99": "SLICEL", + "SLICE_X1Y99": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y0": { + "bits": {}, + "grid_x": 93, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X36Y0", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y0": "SLICEL", + "SLICE_X53Y0": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y1": { + "bits": {}, + "grid_x": 93, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X36Y1", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y1": "SLICEL", + "SLICE_X53Y1": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y10": { + "bits": {}, + "grid_x": 93, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X36Y10", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y10": "SLICEL", + "SLICE_X53Y10": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y100": { + "bits": {}, + "grid_x": 93, + "grid_y": 103, + "segment": "SEG_CLBLL_L_X36Y100", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y100": "SLICEL", + "SLICE_X53Y100": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y101": { + "bits": {}, + "grid_x": 93, + "grid_y": 102, + "segment": "SEG_CLBLL_L_X36Y101", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y101": "SLICEL", + "SLICE_X53Y101": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y102": { + "bits": {}, + "grid_x": 93, + "grid_y": 101, + "segment": "SEG_CLBLL_L_X36Y102", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y102": "SLICEL", + "SLICE_X53Y102": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y103": { + "bits": {}, + "grid_x": 93, + "grid_y": 100, + "segment": "SEG_CLBLL_L_X36Y103", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y103": "SLICEL", + "SLICE_X53Y103": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y104": { + "bits": {}, + "grid_x": 93, + "grid_y": 99, + "segment": "SEG_CLBLL_L_X36Y104", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y104": "SLICEL", + "SLICE_X53Y104": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y105": { + "bits": {}, + "grid_x": 93, + "grid_y": 98, + "segment": "SEG_CLBLL_L_X36Y105", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y105": "SLICEL", + "SLICE_X53Y105": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y106": { + "bits": {}, + "grid_x": 93, + "grid_y": 97, + "segment": "SEG_CLBLL_L_X36Y106", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y106": "SLICEL", + "SLICE_X53Y106": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y107": { + "bits": {}, + "grid_x": 93, + "grid_y": 96, + "segment": "SEG_CLBLL_L_X36Y107", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y107": "SLICEL", + "SLICE_X53Y107": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y108": { + "bits": {}, + "grid_x": 93, + "grid_y": 95, + "segment": "SEG_CLBLL_L_X36Y108", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y108": "SLICEL", + "SLICE_X53Y108": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y109": { + "bits": {}, + "grid_x": 93, + "grid_y": 94, + "segment": "SEG_CLBLL_L_X36Y109", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y109": "SLICEL", + "SLICE_X53Y109": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y11": { + "bits": {}, + "grid_x": 93, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X36Y11", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y11": "SLICEL", + "SLICE_X53Y11": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y110": { + "bits": {}, + "grid_x": 93, + "grid_y": 93, + "segment": "SEG_CLBLL_L_X36Y110", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y110": "SLICEL", + "SLICE_X53Y110": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y111": { + "bits": {}, + "grid_x": 93, + "grid_y": 92, + "segment": "SEG_CLBLL_L_X36Y111", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y111": "SLICEL", + "SLICE_X53Y111": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y112": { + "bits": {}, + "grid_x": 93, + "grid_y": 91, + "segment": "SEG_CLBLL_L_X36Y112", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y112": "SLICEL", + "SLICE_X53Y112": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y113": { + "bits": {}, + "grid_x": 93, + "grid_y": 90, + "segment": "SEG_CLBLL_L_X36Y113", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y113": "SLICEL", + "SLICE_X53Y113": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y114": { + "bits": {}, + "grid_x": 93, + "grid_y": 89, + "segment": "SEG_CLBLL_L_X36Y114", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y114": "SLICEL", + "SLICE_X53Y114": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y115": { + "bits": {}, + "grid_x": 93, + "grid_y": 88, + "segment": "SEG_CLBLL_L_X36Y115", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y115": "SLICEL", + "SLICE_X53Y115": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y116": { + "bits": {}, + "grid_x": 93, + "grid_y": 87, + "segment": "SEG_CLBLL_L_X36Y116", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y116": "SLICEL", + "SLICE_X53Y116": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y117": { + "bits": {}, + "grid_x": 93, + "grid_y": 86, + "segment": "SEG_CLBLL_L_X36Y117", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y117": "SLICEL", + "SLICE_X53Y117": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y118": { + "bits": {}, + "grid_x": 93, + "grid_y": 85, + "segment": "SEG_CLBLL_L_X36Y118", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y118": "SLICEL", + "SLICE_X53Y118": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y119": { + "bits": {}, + "grid_x": 93, + "grid_y": 84, + "segment": "SEG_CLBLL_L_X36Y119", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y119": "SLICEL", + "SLICE_X53Y119": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y12": { + "bits": {}, + "grid_x": 93, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X36Y12", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y12": "SLICEL", + "SLICE_X53Y12": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y120": { + "bits": {}, + "grid_x": 93, + "grid_y": 83, + "segment": "SEG_CLBLL_L_X36Y120", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y120": "SLICEL", + "SLICE_X53Y120": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y121": { + "bits": {}, + "grid_x": 93, + "grid_y": 82, + "segment": "SEG_CLBLL_L_X36Y121", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y121": "SLICEL", + "SLICE_X53Y121": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y122": { + "bits": {}, + "grid_x": 93, + "grid_y": 81, + "segment": "SEG_CLBLL_L_X36Y122", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y122": "SLICEL", + "SLICE_X53Y122": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y123": { + "bits": {}, + "grid_x": 93, + "grid_y": 80, + "segment": "SEG_CLBLL_L_X36Y123", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y123": "SLICEL", + "SLICE_X53Y123": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y124": { + "bits": {}, + "grid_x": 93, + "grid_y": 79, + "segment": "SEG_CLBLL_L_X36Y124", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y124": "SLICEL", + "SLICE_X53Y124": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y125": { + "bits": {}, + "grid_x": 93, + "grid_y": 77, + "segment": "SEG_CLBLL_L_X36Y125", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y125": "SLICEL", + "SLICE_X53Y125": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y126": { + "bits": {}, + "grid_x": 93, + "grid_y": 76, + "segment": "SEG_CLBLL_L_X36Y126", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y126": "SLICEL", + "SLICE_X53Y126": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y127": { + "bits": {}, + "grid_x": 93, + "grid_y": 75, + "segment": "SEG_CLBLL_L_X36Y127", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y127": "SLICEL", + "SLICE_X53Y127": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y128": { + "bits": {}, + "grid_x": 93, + "grid_y": 74, + "segment": "SEG_CLBLL_L_X36Y128", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y128": "SLICEL", + "SLICE_X53Y128": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y129": { + "bits": {}, + "grid_x": 93, + "grid_y": 73, + "segment": "SEG_CLBLL_L_X36Y129", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y129": "SLICEL", + "SLICE_X53Y129": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y13": { + "bits": {}, + "grid_x": 93, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X36Y13", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y13": "SLICEL", + "SLICE_X53Y13": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y130": { + "bits": {}, + "grid_x": 93, + "grid_y": 72, + "segment": "SEG_CLBLL_L_X36Y130", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y130": "SLICEL", + "SLICE_X53Y130": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y131": { + "bits": {}, + "grid_x": 93, + "grid_y": 71, + "segment": "SEG_CLBLL_L_X36Y131", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y131": "SLICEL", + "SLICE_X53Y131": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y132": { + "bits": {}, + "grid_x": 93, + "grid_y": 70, + "segment": "SEG_CLBLL_L_X36Y132", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y132": "SLICEL", + "SLICE_X53Y132": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y133": { + "bits": {}, + "grid_x": 93, + "grid_y": 69, + "segment": "SEG_CLBLL_L_X36Y133", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y133": "SLICEL", + "SLICE_X53Y133": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y134": { + "bits": {}, + "grid_x": 93, + "grid_y": 68, + "segment": "SEG_CLBLL_L_X36Y134", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y134": "SLICEL", + "SLICE_X53Y134": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y135": { + "bits": {}, + "grid_x": 93, + "grid_y": 67, + "segment": "SEG_CLBLL_L_X36Y135", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y135": "SLICEL", + "SLICE_X53Y135": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y136": { + "bits": {}, + "grid_x": 93, + "grid_y": 66, + "segment": "SEG_CLBLL_L_X36Y136", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y136": "SLICEL", + "SLICE_X53Y136": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y137": { + "bits": {}, + "grid_x": 93, + "grid_y": 65, + "segment": "SEG_CLBLL_L_X36Y137", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y137": "SLICEL", + "SLICE_X53Y137": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y138": { + "bits": {}, + "grid_x": 93, + "grid_y": 64, + "segment": "SEG_CLBLL_L_X36Y138", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y138": "SLICEL", + "SLICE_X53Y138": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y139": { + "bits": {}, + "grid_x": 93, + "grid_y": 63, + "segment": "SEG_CLBLL_L_X36Y139", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y139": "SLICEL", + "SLICE_X53Y139": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y14": { + "bits": {}, + "grid_x": 93, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X36Y14", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y14": "SLICEL", + "SLICE_X53Y14": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y140": { + "bits": {}, + "grid_x": 93, + "grid_y": 62, + "segment": "SEG_CLBLL_L_X36Y140", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y140": "SLICEL", + "SLICE_X53Y140": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y141": { + "bits": {}, + "grid_x": 93, + "grid_y": 61, + "segment": "SEG_CLBLL_L_X36Y141", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y141": "SLICEL", + "SLICE_X53Y141": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y142": { + "bits": {}, + "grid_x": 93, + "grid_y": 60, + "segment": "SEG_CLBLL_L_X36Y142", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y142": "SLICEL", + "SLICE_X53Y142": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y143": { + "bits": {}, + "grid_x": 93, + "grid_y": 59, + "segment": "SEG_CLBLL_L_X36Y143", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y143": "SLICEL", + "SLICE_X53Y143": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y144": { + "bits": {}, + "grid_x": 93, + "grid_y": 58, + "segment": "SEG_CLBLL_L_X36Y144", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y144": "SLICEL", + "SLICE_X53Y144": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y145": { + "bits": {}, + "grid_x": 93, + "grid_y": 57, + "segment": "SEG_CLBLL_L_X36Y145", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y145": "SLICEL", + "SLICE_X53Y145": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y146": { + "bits": {}, + "grid_x": 93, + "grid_y": 56, + "segment": "SEG_CLBLL_L_X36Y146", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y146": "SLICEL", + "SLICE_X53Y146": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y147": { + "bits": {}, + "grid_x": 93, + "grid_y": 55, + "segment": "SEG_CLBLL_L_X36Y147", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y147": "SLICEL", + "SLICE_X53Y147": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y148": { + "bits": {}, + "grid_x": 93, + "grid_y": 54, + "segment": "SEG_CLBLL_L_X36Y148", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y148": "SLICEL", + "SLICE_X53Y148": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y149": { + "bits": {}, + "grid_x": 93, + "grid_y": 53, + "segment": "SEG_CLBLL_L_X36Y149", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y149": "SLICEL", + "SLICE_X53Y149": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y15": { + "bits": {}, + "grid_x": 93, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X36Y15", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y15": "SLICEL", + "SLICE_X53Y15": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y150": { + "bits": {}, + "grid_x": 93, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X36Y150", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y150": "SLICEL", + "SLICE_X53Y150": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y151": { + "bits": {}, + "grid_x": 93, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X36Y151", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y151": "SLICEL", + "SLICE_X53Y151": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y152": { + "bits": {}, + "grid_x": 93, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X36Y152", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y152": "SLICEL", + "SLICE_X53Y152": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y153": { + "bits": {}, + "grid_x": 93, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X36Y153", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y153": "SLICEL", + "SLICE_X53Y153": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y154": { + "bits": {}, + "grid_x": 93, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X36Y154", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y154": "SLICEL", + "SLICE_X53Y154": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y155": { + "bits": {}, + "grid_x": 93, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X36Y155", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y155": "SLICEL", + "SLICE_X53Y155": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y156": { + "bits": {}, + "grid_x": 93, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X36Y156", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y156": "SLICEL", + "SLICE_X53Y156": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y157": { + "bits": {}, + "grid_x": 93, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X36Y157", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y157": "SLICEL", + "SLICE_X53Y157": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y158": { + "bits": {}, + "grid_x": 93, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X36Y158", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y158": "SLICEL", + "SLICE_X53Y158": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y159": { + "bits": {}, + "grid_x": 93, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X36Y159", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y159": "SLICEL", + "SLICE_X53Y159": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y16": { + "bits": {}, + "grid_x": 93, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X36Y16", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y16": "SLICEL", + "SLICE_X53Y16": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y160": { + "bits": {}, + "grid_x": 93, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X36Y160", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y160": "SLICEL", + "SLICE_X53Y160": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y161": { + "bits": {}, + "grid_x": 93, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X36Y161", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y161": "SLICEL", + "SLICE_X53Y161": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y162": { + "bits": {}, + "grid_x": 93, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X36Y162", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y162": "SLICEL", + "SLICE_X53Y162": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y163": { + "bits": {}, + "grid_x": 93, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X36Y163", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y163": "SLICEL", + "SLICE_X53Y163": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y164": { + "bits": {}, + "grid_x": 93, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X36Y164", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y164": "SLICEL", + "SLICE_X53Y164": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y165": { + "bits": {}, + "grid_x": 93, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X36Y165", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y165": "SLICEL", + "SLICE_X53Y165": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y166": { + "bits": {}, + "grid_x": 93, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X36Y166", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y166": "SLICEL", + "SLICE_X53Y166": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y167": { + "bits": {}, + "grid_x": 93, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X36Y167", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y167": "SLICEL", + "SLICE_X53Y167": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y168": { + "bits": {}, + "grid_x": 93, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X36Y168", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y168": "SLICEL", + "SLICE_X53Y168": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y169": { + "bits": {}, + "grid_x": 93, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X36Y169", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y169": "SLICEL", + "SLICE_X53Y169": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y17": { + "bits": {}, + "grid_x": 93, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X36Y17", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y17": "SLICEL", + "SLICE_X53Y17": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y170": { + "bits": {}, + "grid_x": 93, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X36Y170", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y170": "SLICEL", + "SLICE_X53Y170": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y171": { + "bits": {}, + "grid_x": 93, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X36Y171", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y171": "SLICEL", + "SLICE_X53Y171": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y172": { + "bits": {}, + "grid_x": 93, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X36Y172", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y172": "SLICEL", + "SLICE_X53Y172": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y173": { + "bits": {}, + "grid_x": 93, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X36Y173", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y173": "SLICEL", + "SLICE_X53Y173": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y174": { + "bits": {}, + "grid_x": 93, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X36Y174", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y174": "SLICEL", + "SLICE_X53Y174": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y175": { + "bits": {}, + "grid_x": 93, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X36Y175", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y175": "SLICEL", + "SLICE_X53Y175": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y176": { + "bits": {}, + "grid_x": 93, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X36Y176", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y176": "SLICEL", + "SLICE_X53Y176": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y177": { + "bits": {}, + "grid_x": 93, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X36Y177", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y177": "SLICEL", + "SLICE_X53Y177": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y178": { + "bits": {}, + "grid_x": 93, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X36Y178", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y178": "SLICEL", + "SLICE_X53Y178": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y179": { + "bits": {}, + "grid_x": 93, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X36Y179", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y179": "SLICEL", + "SLICE_X53Y179": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y18": { + "bits": {}, + "grid_x": 93, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X36Y18", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y18": "SLICEL", + "SLICE_X53Y18": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y180": { + "bits": {}, + "grid_x": 93, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X36Y180", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y180": "SLICEL", + "SLICE_X53Y180": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y181": { + "bits": {}, + "grid_x": 93, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X36Y181", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y181": "SLICEL", + "SLICE_X53Y181": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y182": { + "bits": {}, + "grid_x": 93, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X36Y182", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y182": "SLICEL", + "SLICE_X53Y182": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y183": { + "bits": {}, + "grid_x": 93, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X36Y183", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y183": "SLICEL", + "SLICE_X53Y183": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y184": { + "bits": {}, + "grid_x": 93, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X36Y184", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y184": "SLICEL", + "SLICE_X53Y184": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y185": { + "bits": {}, + "grid_x": 93, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X36Y185", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y185": "SLICEL", + "SLICE_X53Y185": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y186": { + "bits": {}, + "grid_x": 93, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X36Y186", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y186": "SLICEL", + "SLICE_X53Y186": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y187": { + "bits": {}, + "grid_x": 93, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X36Y187", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y187": "SLICEL", + "SLICE_X53Y187": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y188": { + "bits": {}, + "grid_x": 93, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X36Y188", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y188": "SLICEL", + "SLICE_X53Y188": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y189": { + "bits": {}, + "grid_x": 93, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X36Y189", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y189": "SLICEL", + "SLICE_X53Y189": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y19": { + "bits": {}, + "grid_x": 93, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X36Y19", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y19": "SLICEL", + "SLICE_X53Y19": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y190": { + "bits": {}, + "grid_x": 93, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X36Y190", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y190": "SLICEL", + "SLICE_X53Y190": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y191": { + "bits": {}, + "grid_x": 93, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X36Y191", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y191": "SLICEL", + "SLICE_X53Y191": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y192": { + "bits": {}, + "grid_x": 93, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X36Y192", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y192": "SLICEL", + "SLICE_X53Y192": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y193": { + "bits": {}, + "grid_x": 93, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X36Y193", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y193": "SLICEL", + "SLICE_X53Y193": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y194": { + "bits": {}, + "grid_x": 93, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X36Y194", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y194": "SLICEL", + "SLICE_X53Y194": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y195": { + "bits": {}, + "grid_x": 93, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X36Y195", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y195": "SLICEL", + "SLICE_X53Y195": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y196": { + "bits": {}, + "grid_x": 93, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X36Y196", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y196": "SLICEL", + "SLICE_X53Y196": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y197": { + "bits": {}, + "grid_x": 93, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X36Y197", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y197": "SLICEL", + "SLICE_X53Y197": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y198": { + "bits": {}, + "grid_x": 93, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X36Y198", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y198": "SLICEL", + "SLICE_X53Y198": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y199": { + "bits": {}, + "grid_x": 93, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X36Y199", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y199": "SLICEL", + "SLICE_X53Y199": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y2": { + "bits": {}, + "grid_x": 93, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X36Y2", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y2": "SLICEL", + "SLICE_X53Y2": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y20": { + "bits": {}, + "grid_x": 93, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X36Y20", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y20": "SLICEL", + "SLICE_X53Y20": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y21": { + "bits": {}, + "grid_x": 93, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X36Y21", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y21": "SLICEL", + "SLICE_X53Y21": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y22": { + "bits": {}, + "grid_x": 93, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X36Y22", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y22": "SLICEL", + "SLICE_X53Y22": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y23": { + "bits": {}, + "grid_x": 93, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X36Y23", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y23": "SLICEL", + "SLICE_X53Y23": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y24": { + "bits": {}, + "grid_x": 93, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X36Y24", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y24": "SLICEL", + "SLICE_X53Y24": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y25": { + "bits": {}, + "grid_x": 93, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X36Y25", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y25": "SLICEL", + "SLICE_X53Y25": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y26": { + "bits": {}, + "grid_x": 93, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X36Y26", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y26": "SLICEL", + "SLICE_X53Y26": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y27": { + "bits": {}, + "grid_x": 93, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X36Y27", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y27": "SLICEL", + "SLICE_X53Y27": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y28": { + "bits": {}, + "grid_x": 93, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X36Y28", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y28": "SLICEL", + "SLICE_X53Y28": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y29": { + "bits": {}, + "grid_x": 93, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X36Y29", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y29": "SLICEL", + "SLICE_X53Y29": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y3": { + "bits": {}, + "grid_x": 93, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X36Y3", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y3": "SLICEL", + "SLICE_X53Y3": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y30": { + "bits": {}, + "grid_x": 93, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X36Y30", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y30": "SLICEL", + "SLICE_X53Y30": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y31": { + "bits": {}, + "grid_x": 93, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X36Y31", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y31": "SLICEL", + "SLICE_X53Y31": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y32": { + "bits": {}, + "grid_x": 93, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X36Y32", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y32": "SLICEL", + "SLICE_X53Y32": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y33": { + "bits": {}, + "grid_x": 93, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X36Y33", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y33": "SLICEL", + "SLICE_X53Y33": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y34": { + "bits": {}, + "grid_x": 93, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X36Y34", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y34": "SLICEL", + "SLICE_X53Y34": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y35": { + "bits": {}, + "grid_x": 93, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X36Y35", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y35": "SLICEL", + "SLICE_X53Y35": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y36": { + "bits": {}, + "grid_x": 93, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X36Y36", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y36": "SLICEL", + "SLICE_X53Y36": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y37": { + "bits": {}, + "grid_x": 93, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X36Y37", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y37": "SLICEL", + "SLICE_X53Y37": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y38": { + "bits": {}, + "grid_x": 93, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X36Y38", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y38": "SLICEL", + "SLICE_X53Y38": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y39": { + "bits": {}, + "grid_x": 93, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X36Y39", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y39": "SLICEL", + "SLICE_X53Y39": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y4": { + "bits": {}, + "grid_x": 93, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X36Y4", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y4": "SLICEL", + "SLICE_X53Y4": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y40": { + "bits": {}, + "grid_x": 93, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X36Y40", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y40": "SLICEL", + "SLICE_X53Y40": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y41": { + "bits": {}, + "grid_x": 93, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X36Y41", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y41": "SLICEL", + "SLICE_X53Y41": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y42": { + "bits": {}, + "grid_x": 93, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X36Y42", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y42": "SLICEL", + "SLICE_X53Y42": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y43": { + "bits": {}, + "grid_x": 93, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X36Y43", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y43": "SLICEL", + "SLICE_X53Y43": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y44": { + "bits": {}, + "grid_x": 93, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X36Y44", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y44": "SLICEL", + "SLICE_X53Y44": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y45": { + "bits": {}, + "grid_x": 93, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X36Y45", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y45": "SLICEL", + "SLICE_X53Y45": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y46": { + "bits": {}, + "grid_x": 93, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X36Y46", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y46": "SLICEL", + "SLICE_X53Y46": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y47": { + "bits": {}, + "grid_x": 93, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X36Y47", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y47": "SLICEL", + "SLICE_X53Y47": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y48": { + "bits": {}, + "grid_x": 93, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X36Y48", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y48": "SLICEL", + "SLICE_X53Y48": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y49": { + "bits": {}, + "grid_x": 93, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X36Y49", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y49": "SLICEL", + "SLICE_X53Y49": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y5": { + "bits": {}, + "grid_x": 93, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X36Y5", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y5": "SLICEL", + "SLICE_X53Y5": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y50": { + "bits": {}, + "grid_x": 93, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X36Y50", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y50": "SLICEL", + "SLICE_X53Y50": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y51": { + "bits": {}, + "grid_x": 93, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X36Y51", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y51": "SLICEL", + "SLICE_X53Y51": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y52": { + "bits": {}, + "grid_x": 93, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X36Y52", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y52": "SLICEL", + "SLICE_X53Y52": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y53": { + "bits": {}, + "grid_x": 93, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X36Y53", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y53": "SLICEL", + "SLICE_X53Y53": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y54": { + "bits": {}, + "grid_x": 93, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X36Y54", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y54": "SLICEL", + "SLICE_X53Y54": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y55": { + "bits": {}, + "grid_x": 93, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X36Y55", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y55": "SLICEL", + "SLICE_X53Y55": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y56": { + "bits": {}, + "grid_x": 93, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X36Y56", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y56": "SLICEL", + "SLICE_X53Y56": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y57": { + "bits": {}, + "grid_x": 93, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X36Y57", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y57": "SLICEL", + "SLICE_X53Y57": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y58": { + "bits": {}, + "grid_x": 93, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X36Y58", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y58": "SLICEL", + "SLICE_X53Y58": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y59": { + "bits": {}, + "grid_x": 93, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X36Y59", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y59": "SLICEL", + "SLICE_X53Y59": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y6": { + "bits": {}, + "grid_x": 93, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X36Y6", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y6": "SLICEL", + "SLICE_X53Y6": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y60": { + "bits": {}, + "grid_x": 93, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X36Y60", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y60": "SLICEL", + "SLICE_X53Y60": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y61": { + "bits": {}, + "grid_x": 93, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X36Y61", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y61": "SLICEL", + "SLICE_X53Y61": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y62": { + "bits": {}, + "grid_x": 93, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X36Y62", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y62": "SLICEL", + "SLICE_X53Y62": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y63": { + "bits": {}, + "grid_x": 93, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X36Y63", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y63": "SLICEL", + "SLICE_X53Y63": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y64": { + "bits": {}, + "grid_x": 93, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X36Y64", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y64": "SLICEL", + "SLICE_X53Y64": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y65": { + "bits": {}, + "grid_x": 93, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X36Y65", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y65": "SLICEL", + "SLICE_X53Y65": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y66": { + "bits": {}, + "grid_x": 93, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X36Y66", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y66": "SLICEL", + "SLICE_X53Y66": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y67": { + "bits": {}, + "grid_x": 93, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X36Y67", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y67": "SLICEL", + "SLICE_X53Y67": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y68": { + "bits": {}, + "grid_x": 93, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X36Y68", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y68": "SLICEL", + "SLICE_X53Y68": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y69": { + "bits": {}, + "grid_x": 93, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X36Y69", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y69": "SLICEL", + "SLICE_X53Y69": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y7": { + "bits": {}, + "grid_x": 93, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X36Y7", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y7": "SLICEL", + "SLICE_X53Y7": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y70": { + "bits": {}, + "grid_x": 93, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X36Y70", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y70": "SLICEL", + "SLICE_X53Y70": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y71": { + "bits": {}, + "grid_x": 93, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X36Y71", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y71": "SLICEL", + "SLICE_X53Y71": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y72": { + "bits": {}, + "grid_x": 93, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X36Y72", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y72": "SLICEL", + "SLICE_X53Y72": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y73": { + "bits": {}, + "grid_x": 93, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X36Y73", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y73": "SLICEL", + "SLICE_X53Y73": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y74": { + "bits": {}, + "grid_x": 93, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X36Y74", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y74": "SLICEL", + "SLICE_X53Y74": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y75": { + "bits": {}, + "grid_x": 93, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X36Y75", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y75": "SLICEL", + "SLICE_X53Y75": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y76": { + "bits": {}, + "grid_x": 93, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X36Y76", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y76": "SLICEL", + "SLICE_X53Y76": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y77": { + "bits": {}, + "grid_x": 93, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X36Y77", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y77": "SLICEL", + "SLICE_X53Y77": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y78": { + "bits": {}, + "grid_x": 93, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X36Y78", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y78": "SLICEL", + "SLICE_X53Y78": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y79": { + "bits": {}, + "grid_x": 93, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X36Y79", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y79": "SLICEL", + "SLICE_X53Y79": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y8": { + "bits": {}, + "grid_x": 93, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X36Y8", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y8": "SLICEL", + "SLICE_X53Y8": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y80": { + "bits": {}, + "grid_x": 93, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X36Y80", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y80": "SLICEL", + "SLICE_X53Y80": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y81": { + "bits": {}, + "grid_x": 93, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X36Y81", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y81": "SLICEL", + "SLICE_X53Y81": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y82": { + "bits": {}, + "grid_x": 93, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X36Y82", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y82": "SLICEL", + "SLICE_X53Y82": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y83": { + "bits": {}, + "grid_x": 93, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X36Y83", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y83": "SLICEL", + "SLICE_X53Y83": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y84": { + "bits": {}, + "grid_x": 93, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X36Y84", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y84": "SLICEL", + "SLICE_X53Y84": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y85": { + "bits": {}, + "grid_x": 93, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X36Y85", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y85": "SLICEL", + "SLICE_X53Y85": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y86": { + "bits": {}, + "grid_x": 93, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X36Y86", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y86": "SLICEL", + "SLICE_X53Y86": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y87": { + "bits": {}, + "grid_x": 93, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X36Y87", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y87": "SLICEL", + "SLICE_X53Y87": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y88": { + "bits": {}, + "grid_x": 93, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X36Y88", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y88": "SLICEL", + "SLICE_X53Y88": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y89": { + "bits": {}, + "grid_x": 93, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X36Y89", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y89": "SLICEL", + "SLICE_X53Y89": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y9": { + "bits": {}, + "grid_x": 93, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X36Y9", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y9": "SLICEL", + "SLICE_X53Y9": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y90": { + "bits": {}, + "grid_x": 93, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X36Y90", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y90": "SLICEL", + "SLICE_X53Y90": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y91": { + "bits": {}, + "grid_x": 93, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X36Y91", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y91": "SLICEL", + "SLICE_X53Y91": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y92": { + "bits": {}, + "grid_x": 93, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X36Y92", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y92": "SLICEL", + "SLICE_X53Y92": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y93": { + "bits": {}, + "grid_x": 93, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X36Y93", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y93": "SLICEL", + "SLICE_X53Y93": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y94": { + "bits": {}, + "grid_x": 93, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X36Y94", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y94": "SLICEL", + "SLICE_X53Y94": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y95": { + "bits": {}, + "grid_x": 93, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X36Y95", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y95": "SLICEL", + "SLICE_X53Y95": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y96": { + "bits": {}, + "grid_x": 93, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X36Y96", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y96": "SLICEL", + "SLICE_X53Y96": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y97": { + "bits": {}, + "grid_x": 93, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X36Y97", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y97": "SLICEL", + "SLICE_X53Y97": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y98": { + "bits": {}, + "grid_x": 93, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X36Y98", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y98": "SLICEL", + "SLICE_X53Y98": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X36Y99": { + "bits": {}, + "grid_x": 93, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X36Y99", + "segment_type": "clbll_l", + "sites": { + "SLICE_X52Y99": "SLICEL", + "SLICE_X53Y99": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y0": { + "bits": {}, + "grid_x": 99, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X38Y0", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y0": "SLICEL", + "SLICE_X55Y0": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y1": { + "bits": {}, + "grid_x": 99, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X38Y1", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y1": "SLICEL", + "SLICE_X55Y1": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y10": { + "bits": {}, + "grid_x": 99, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X38Y10", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y10": "SLICEL", + "SLICE_X55Y10": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y11": { + "bits": {}, + "grid_x": 99, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X38Y11", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y11": "SLICEL", + "SLICE_X55Y11": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y12": { + "bits": {}, + "grid_x": 99, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X38Y12", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y12": "SLICEL", + "SLICE_X55Y12": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y13": { + "bits": {}, + "grid_x": 99, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X38Y13", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y13": "SLICEL", + "SLICE_X55Y13": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y14": { + "bits": {}, + "grid_x": 99, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X38Y14", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y14": "SLICEL", + "SLICE_X55Y14": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y15": { + "bits": {}, + "grid_x": 99, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X38Y15", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y15": "SLICEL", + "SLICE_X55Y15": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y16": { + "bits": {}, + "grid_x": 99, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X38Y16", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y16": "SLICEL", + "SLICE_X55Y16": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y17": { + "bits": {}, + "grid_x": 99, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X38Y17", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y17": "SLICEL", + "SLICE_X55Y17": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y18": { + "bits": {}, + "grid_x": 99, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X38Y18", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y18": "SLICEL", + "SLICE_X55Y18": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y19": { + "bits": {}, + "grid_x": 99, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X38Y19", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y19": "SLICEL", + "SLICE_X55Y19": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y2": { + "bits": {}, + "grid_x": 99, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X38Y2", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y2": "SLICEL", + "SLICE_X55Y2": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y20": { + "bits": {}, + "grid_x": 99, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X38Y20", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y20": "SLICEL", + "SLICE_X55Y20": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y21": { + "bits": {}, + "grid_x": 99, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X38Y21", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y21": "SLICEL", + "SLICE_X55Y21": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y22": { + "bits": {}, + "grid_x": 99, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X38Y22", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y22": "SLICEL", + "SLICE_X55Y22": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y23": { + "bits": {}, + "grid_x": 99, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X38Y23", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y23": "SLICEL", + "SLICE_X55Y23": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y24": { + "bits": {}, + "grid_x": 99, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X38Y24", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y24": "SLICEL", + "SLICE_X55Y24": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y25": { + "bits": {}, + "grid_x": 99, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X38Y25", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y25": "SLICEL", + "SLICE_X55Y25": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y26": { + "bits": {}, + "grid_x": 99, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X38Y26", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y26": "SLICEL", + "SLICE_X55Y26": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y27": { + "bits": {}, + "grid_x": 99, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X38Y27", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y27": "SLICEL", + "SLICE_X55Y27": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y28": { + "bits": {}, + "grid_x": 99, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X38Y28", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y28": "SLICEL", + "SLICE_X55Y28": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y29": { + "bits": {}, + "grid_x": 99, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X38Y29", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y29": "SLICEL", + "SLICE_X55Y29": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y3": { + "bits": {}, + "grid_x": 99, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X38Y3", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y3": "SLICEL", + "SLICE_X55Y3": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y30": { + "bits": {}, + "grid_x": 99, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X38Y30", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y30": "SLICEL", + "SLICE_X55Y30": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y31": { + "bits": {}, + "grid_x": 99, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X38Y31", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y31": "SLICEL", + "SLICE_X55Y31": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y32": { + "bits": {}, + "grid_x": 99, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X38Y32", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y32": "SLICEL", + "SLICE_X55Y32": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y33": { + "bits": {}, + "grid_x": 99, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X38Y33", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y33": "SLICEL", + "SLICE_X55Y33": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y34": { + "bits": {}, + "grid_x": 99, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X38Y34", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y34": "SLICEL", + "SLICE_X55Y34": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y35": { + "bits": {}, + "grid_x": 99, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X38Y35", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y35": "SLICEL", + "SLICE_X55Y35": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y36": { + "bits": {}, + "grid_x": 99, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X38Y36", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y36": "SLICEL", + "SLICE_X55Y36": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y37": { + "bits": {}, + "grid_x": 99, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X38Y37", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y37": "SLICEL", + "SLICE_X55Y37": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y38": { + "bits": {}, + "grid_x": 99, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X38Y38", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y38": "SLICEL", + "SLICE_X55Y38": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y39": { + "bits": {}, + "grid_x": 99, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X38Y39", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y39": "SLICEL", + "SLICE_X55Y39": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y4": { + "bits": {}, + "grid_x": 99, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X38Y4", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y4": "SLICEL", + "SLICE_X55Y4": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y40": { + "bits": {}, + "grid_x": 99, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X38Y40", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y40": "SLICEL", + "SLICE_X55Y40": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y41": { + "bits": {}, + "grid_x": 99, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X38Y41", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y41": "SLICEL", + "SLICE_X55Y41": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y42": { + "bits": {}, + "grid_x": 99, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X38Y42", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y42": "SLICEL", + "SLICE_X55Y42": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y43": { + "bits": {}, + "grid_x": 99, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X38Y43", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y43": "SLICEL", + "SLICE_X55Y43": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y44": { + "bits": {}, + "grid_x": 99, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X38Y44", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y44": "SLICEL", + "SLICE_X55Y44": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y45": { + "bits": {}, + "grid_x": 99, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X38Y45", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y45": "SLICEL", + "SLICE_X55Y45": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y46": { + "bits": {}, + "grid_x": 99, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X38Y46", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y46": "SLICEL", + "SLICE_X55Y46": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y47": { + "bits": {}, + "grid_x": 99, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X38Y47", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y47": "SLICEL", + "SLICE_X55Y47": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y48": { + "bits": {}, + "grid_x": 99, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X38Y48", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y48": "SLICEL", + "SLICE_X55Y48": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y49": { + "bits": {}, + "grid_x": 99, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X38Y49", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y49": "SLICEL", + "SLICE_X55Y49": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y5": { + "bits": {}, + "grid_x": 99, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X38Y5", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y5": "SLICEL", + "SLICE_X55Y5": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y50": { + "bits": {}, + "grid_x": 99, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X38Y50", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y50": "SLICEL", + "SLICE_X55Y50": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y51": { + "bits": {}, + "grid_x": 99, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X38Y51", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y51": "SLICEL", + "SLICE_X55Y51": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y52": { + "bits": {}, + "grid_x": 99, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X38Y52", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y52": "SLICEL", + "SLICE_X55Y52": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y53": { + "bits": {}, + "grid_x": 99, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X38Y53", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y53": "SLICEL", + "SLICE_X55Y53": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y54": { + "bits": {}, + "grid_x": 99, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X38Y54", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y54": "SLICEL", + "SLICE_X55Y54": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y55": { + "bits": {}, + "grid_x": 99, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X38Y55", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y55": "SLICEL", + "SLICE_X55Y55": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y56": { + "bits": {}, + "grid_x": 99, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X38Y56", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y56": "SLICEL", + "SLICE_X55Y56": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y57": { + "bits": {}, + "grid_x": 99, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X38Y57", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y57": "SLICEL", + "SLICE_X55Y57": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y58": { + "bits": {}, + "grid_x": 99, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X38Y58", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y58": "SLICEL", + "SLICE_X55Y58": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y59": { + "bits": {}, + "grid_x": 99, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X38Y59", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y59": "SLICEL", + "SLICE_X55Y59": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y6": { + "bits": {}, + "grid_x": 99, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X38Y6", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y6": "SLICEL", + "SLICE_X55Y6": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y60": { + "bits": {}, + "grid_x": 99, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X38Y60", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y60": "SLICEL", + "SLICE_X55Y60": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y61": { + "bits": {}, + "grid_x": 99, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X38Y61", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y61": "SLICEL", + "SLICE_X55Y61": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y62": { + "bits": {}, + "grid_x": 99, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X38Y62", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y62": "SLICEL", + "SLICE_X55Y62": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y63": { + "bits": {}, + "grid_x": 99, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X38Y63", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y63": "SLICEL", + "SLICE_X55Y63": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y64": { + "bits": {}, + "grid_x": 99, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X38Y64", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y64": "SLICEL", + "SLICE_X55Y64": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y65": { + "bits": {}, + "grid_x": 99, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X38Y65", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y65": "SLICEL", + "SLICE_X55Y65": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y66": { + "bits": {}, + "grid_x": 99, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X38Y66", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y66": "SLICEL", + "SLICE_X55Y66": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y67": { + "bits": {}, + "grid_x": 99, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X38Y67", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y67": "SLICEL", + "SLICE_X55Y67": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y68": { + "bits": {}, + "grid_x": 99, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X38Y68", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y68": "SLICEL", + "SLICE_X55Y68": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y69": { + "bits": {}, + "grid_x": 99, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X38Y69", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y69": "SLICEL", + "SLICE_X55Y69": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y7": { + "bits": {}, + "grid_x": 99, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X38Y7", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y7": "SLICEL", + "SLICE_X55Y7": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y70": { + "bits": {}, + "grid_x": 99, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X38Y70", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y70": "SLICEL", + "SLICE_X55Y70": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y71": { + "bits": {}, + "grid_x": 99, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X38Y71", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y71": "SLICEL", + "SLICE_X55Y71": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y72": { + "bits": {}, + "grid_x": 99, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X38Y72", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y72": "SLICEL", + "SLICE_X55Y72": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y73": { + "bits": {}, + "grid_x": 99, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X38Y73", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y73": "SLICEL", + "SLICE_X55Y73": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y74": { + "bits": {}, + "grid_x": 99, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X38Y74", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y74": "SLICEL", + "SLICE_X55Y74": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y75": { + "bits": {}, + "grid_x": 99, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X38Y75", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y75": "SLICEL", + "SLICE_X55Y75": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y76": { + "bits": {}, + "grid_x": 99, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X38Y76", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y76": "SLICEL", + "SLICE_X55Y76": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y77": { + "bits": {}, + "grid_x": 99, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X38Y77", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y77": "SLICEL", + "SLICE_X55Y77": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y78": { + "bits": {}, + "grid_x": 99, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X38Y78", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y78": "SLICEL", + "SLICE_X55Y78": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y79": { + "bits": {}, + "grid_x": 99, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X38Y79", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y79": "SLICEL", + "SLICE_X55Y79": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y8": { + "bits": {}, + "grid_x": 99, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X38Y8", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y8": "SLICEL", + "SLICE_X55Y8": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y80": { + "bits": {}, + "grid_x": 99, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X38Y80", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y80": "SLICEL", + "SLICE_X55Y80": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y81": { + "bits": {}, + "grid_x": 99, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X38Y81", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y81": "SLICEL", + "SLICE_X55Y81": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y82": { + "bits": {}, + "grid_x": 99, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X38Y82", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y82": "SLICEL", + "SLICE_X55Y82": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y83": { + "bits": {}, + "grid_x": 99, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X38Y83", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y83": "SLICEL", + "SLICE_X55Y83": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y84": { + "bits": {}, + "grid_x": 99, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X38Y84", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y84": "SLICEL", + "SLICE_X55Y84": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y85": { + "bits": {}, + "grid_x": 99, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X38Y85", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y85": "SLICEL", + "SLICE_X55Y85": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y86": { + "bits": {}, + "grid_x": 99, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X38Y86", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y86": "SLICEL", + "SLICE_X55Y86": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y87": { + "bits": {}, + "grid_x": 99, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X38Y87", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y87": "SLICEL", + "SLICE_X55Y87": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y88": { + "bits": {}, + "grid_x": 99, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X38Y88", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y88": "SLICEL", + "SLICE_X55Y88": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y89": { + "bits": {}, + "grid_x": 99, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X38Y89", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y89": "SLICEL", + "SLICE_X55Y89": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y9": { + "bits": {}, + "grid_x": 99, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X38Y9", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y9": "SLICEL", + "SLICE_X55Y9": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y90": { + "bits": {}, + "grid_x": 99, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X38Y90", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y90": "SLICEL", + "SLICE_X55Y90": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y91": { + "bits": {}, + "grid_x": 99, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X38Y91", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y91": "SLICEL", + "SLICE_X55Y91": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y92": { + "bits": {}, + "grid_x": 99, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X38Y92", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y92": "SLICEL", + "SLICE_X55Y92": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y93": { + "bits": {}, + "grid_x": 99, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X38Y93", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y93": "SLICEL", + "SLICE_X55Y93": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y94": { + "bits": {}, + "grid_x": 99, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X38Y94", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y94": "SLICEL", + "SLICE_X55Y94": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y95": { + "bits": {}, + "grid_x": 99, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X38Y95", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y95": "SLICEL", + "SLICE_X55Y95": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y96": { + "bits": {}, + "grid_x": 99, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X38Y96", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y96": "SLICEL", + "SLICE_X55Y96": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y97": { + "bits": {}, + "grid_x": 99, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X38Y97", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y97": "SLICEL", + "SLICE_X55Y97": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y98": { + "bits": {}, + "grid_x": 99, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X38Y98", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y98": "SLICEL", + "SLICE_X55Y98": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X38Y99": { + "bits": {}, + "grid_x": 99, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X38Y99", + "segment_type": "clbll_l", + "sites": { + "SLICE_X54Y99": "SLICEL", + "SLICE_X55Y99": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y0": { + "bits": {}, + "grid_x": 103, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X40Y0", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y0": "SLICEL", + "SLICE_X59Y0": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y1": { + "bits": {}, + "grid_x": 103, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X40Y1", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y1": "SLICEL", + "SLICE_X59Y1": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y10": { + "bits": {}, + "grid_x": 103, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X40Y10", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y10": "SLICEL", + "SLICE_X59Y10": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y11": { + "bits": {}, + "grid_x": 103, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X40Y11", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y11": "SLICEL", + "SLICE_X59Y11": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y12": { + "bits": {}, + "grid_x": 103, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X40Y12", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y12": "SLICEL", + "SLICE_X59Y12": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y13": { + "bits": {}, + "grid_x": 103, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X40Y13", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y13": "SLICEL", + "SLICE_X59Y13": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y14": { + "bits": {}, + "grid_x": 103, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X40Y14", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y14": "SLICEL", + "SLICE_X59Y14": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y15": { + "bits": {}, + "grid_x": 103, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X40Y15", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y15": "SLICEL", + "SLICE_X59Y15": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y16": { + "bits": {}, + "grid_x": 103, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X40Y16", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y16": "SLICEL", + "SLICE_X59Y16": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y17": { + "bits": {}, + "grid_x": 103, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X40Y17", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y17": "SLICEL", + "SLICE_X59Y17": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y18": { + "bits": {}, + "grid_x": 103, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X40Y18", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y18": "SLICEL", + "SLICE_X59Y18": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y19": { + "bits": {}, + "grid_x": 103, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X40Y19", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y19": "SLICEL", + "SLICE_X59Y19": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y2": { + "bits": {}, + "grid_x": 103, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X40Y2", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y2": "SLICEL", + "SLICE_X59Y2": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y20": { + "bits": {}, + "grid_x": 103, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X40Y20", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y20": "SLICEL", + "SLICE_X59Y20": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y21": { + "bits": {}, + "grid_x": 103, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X40Y21", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y21": "SLICEL", + "SLICE_X59Y21": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y22": { + "bits": {}, + "grid_x": 103, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X40Y22", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y22": "SLICEL", + "SLICE_X59Y22": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y23": { + "bits": {}, + "grid_x": 103, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X40Y23", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y23": "SLICEL", + "SLICE_X59Y23": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y24": { + "bits": {}, + "grid_x": 103, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X40Y24", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y24": "SLICEL", + "SLICE_X59Y24": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y25": { + "bits": {}, + "grid_x": 103, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X40Y25", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y25": "SLICEL", + "SLICE_X59Y25": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y26": { + "bits": {}, + "grid_x": 103, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X40Y26", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y26": "SLICEL", + "SLICE_X59Y26": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y27": { + "bits": {}, + "grid_x": 103, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X40Y27", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y27": "SLICEL", + "SLICE_X59Y27": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y28": { + "bits": {}, + "grid_x": 103, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X40Y28", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y28": "SLICEL", + "SLICE_X59Y28": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y29": { + "bits": {}, + "grid_x": 103, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X40Y29", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y29": "SLICEL", + "SLICE_X59Y29": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y3": { + "bits": {}, + "grid_x": 103, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X40Y3", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y3": "SLICEL", + "SLICE_X59Y3": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y30": { + "bits": {}, + "grid_x": 103, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X40Y30", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y30": "SLICEL", + "SLICE_X59Y30": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y31": { + "bits": {}, + "grid_x": 103, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X40Y31", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y31": "SLICEL", + "SLICE_X59Y31": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y32": { + "bits": {}, + "grid_x": 103, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X40Y32", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y32": "SLICEL", + "SLICE_X59Y32": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y33": { + "bits": {}, + "grid_x": 103, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X40Y33", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y33": "SLICEL", + "SLICE_X59Y33": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y34": { + "bits": {}, + "grid_x": 103, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X40Y34", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y34": "SLICEL", + "SLICE_X59Y34": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y35": { + "bits": {}, + "grid_x": 103, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X40Y35", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y35": "SLICEL", + "SLICE_X59Y35": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y36": { + "bits": {}, + "grid_x": 103, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X40Y36", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y36": "SLICEL", + "SLICE_X59Y36": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y37": { + "bits": {}, + "grid_x": 103, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X40Y37", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y37": "SLICEL", + "SLICE_X59Y37": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y38": { + "bits": {}, + "grid_x": 103, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X40Y38", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y38": "SLICEL", + "SLICE_X59Y38": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y39": { + "bits": {}, + "grid_x": 103, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X40Y39", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y39": "SLICEL", + "SLICE_X59Y39": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y4": { + "bits": {}, + "grid_x": 103, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X40Y4", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y4": "SLICEL", + "SLICE_X59Y4": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y40": { + "bits": {}, + "grid_x": 103, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X40Y40", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y40": "SLICEL", + "SLICE_X59Y40": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y41": { + "bits": {}, + "grid_x": 103, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X40Y41", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y41": "SLICEL", + "SLICE_X59Y41": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y42": { + "bits": {}, + "grid_x": 103, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X40Y42", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y42": "SLICEL", + "SLICE_X59Y42": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y43": { + "bits": {}, + "grid_x": 103, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X40Y43", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y43": "SLICEL", + "SLICE_X59Y43": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y44": { + "bits": {}, + "grid_x": 103, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X40Y44", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y44": "SLICEL", + "SLICE_X59Y44": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y45": { + "bits": {}, + "grid_x": 103, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X40Y45", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y45": "SLICEL", + "SLICE_X59Y45": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y46": { + "bits": {}, + "grid_x": 103, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X40Y46", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y46": "SLICEL", + "SLICE_X59Y46": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y47": { + "bits": {}, + "grid_x": 103, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X40Y47", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y47": "SLICEL", + "SLICE_X59Y47": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y48": { + "bits": {}, + "grid_x": 103, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X40Y48", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y48": "SLICEL", + "SLICE_X59Y48": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y49": { + "bits": {}, + "grid_x": 103, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X40Y49", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y49": "SLICEL", + "SLICE_X59Y49": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y5": { + "bits": {}, + "grid_x": 103, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X40Y5", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y5": "SLICEL", + "SLICE_X59Y5": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y50": { + "bits": {}, + "grid_x": 103, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X40Y50", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y50": "SLICEL", + "SLICE_X59Y50": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y51": { + "bits": {}, + "grid_x": 103, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X40Y51", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y51": "SLICEL", + "SLICE_X59Y51": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y52": { + "bits": {}, + "grid_x": 103, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X40Y52", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y52": "SLICEL", + "SLICE_X59Y52": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y53": { + "bits": {}, + "grid_x": 103, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X40Y53", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y53": "SLICEL", + "SLICE_X59Y53": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y54": { + "bits": {}, + "grid_x": 103, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X40Y54", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y54": "SLICEL", + "SLICE_X59Y54": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y55": { + "bits": {}, + "grid_x": 103, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X40Y55", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y55": "SLICEL", + "SLICE_X59Y55": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y56": { + "bits": {}, + "grid_x": 103, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X40Y56", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y56": "SLICEL", + "SLICE_X59Y56": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y57": { + "bits": {}, + "grid_x": 103, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X40Y57", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y57": "SLICEL", + "SLICE_X59Y57": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y58": { + "bits": {}, + "grid_x": 103, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X40Y58", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y58": "SLICEL", + "SLICE_X59Y58": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y59": { + "bits": {}, + "grid_x": 103, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X40Y59", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y59": "SLICEL", + "SLICE_X59Y59": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y6": { + "bits": {}, + "grid_x": 103, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X40Y6", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y6": "SLICEL", + "SLICE_X59Y6": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y60": { + "bits": {}, + "grid_x": 103, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X40Y60", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y60": "SLICEL", + "SLICE_X59Y60": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y61": { + "bits": {}, + "grid_x": 103, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X40Y61", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y61": "SLICEL", + "SLICE_X59Y61": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y62": { + "bits": {}, + "grid_x": 103, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X40Y62", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y62": "SLICEL", + "SLICE_X59Y62": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y63": { + "bits": {}, + "grid_x": 103, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X40Y63", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y63": "SLICEL", + "SLICE_X59Y63": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y64": { + "bits": {}, + "grid_x": 103, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X40Y64", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y64": "SLICEL", + "SLICE_X59Y64": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y65": { + "bits": {}, + "grid_x": 103, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X40Y65", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y65": "SLICEL", + "SLICE_X59Y65": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y66": { + "bits": {}, + "grid_x": 103, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X40Y66", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y66": "SLICEL", + "SLICE_X59Y66": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y67": { + "bits": {}, + "grid_x": 103, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X40Y67", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y67": "SLICEL", + "SLICE_X59Y67": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y68": { + "bits": {}, + "grid_x": 103, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X40Y68", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y68": "SLICEL", + "SLICE_X59Y68": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y69": { + "bits": {}, + "grid_x": 103, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X40Y69", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y69": "SLICEL", + "SLICE_X59Y69": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y7": { + "bits": {}, + "grid_x": 103, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X40Y7", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y7": "SLICEL", + "SLICE_X59Y7": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y70": { + "bits": {}, + "grid_x": 103, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X40Y70", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y70": "SLICEL", + "SLICE_X59Y70": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y71": { + "bits": {}, + "grid_x": 103, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X40Y71", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y71": "SLICEL", + "SLICE_X59Y71": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y72": { + "bits": {}, + "grid_x": 103, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X40Y72", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y72": "SLICEL", + "SLICE_X59Y72": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y73": { + "bits": {}, + "grid_x": 103, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X40Y73", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y73": "SLICEL", + "SLICE_X59Y73": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y74": { + "bits": {}, + "grid_x": 103, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X40Y74", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y74": "SLICEL", + "SLICE_X59Y74": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y75": { + "bits": {}, + "grid_x": 103, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X40Y75", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y75": "SLICEL", + "SLICE_X59Y75": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y76": { + "bits": {}, + "grid_x": 103, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X40Y76", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y76": "SLICEL", + "SLICE_X59Y76": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y77": { + "bits": {}, + "grid_x": 103, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X40Y77", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y77": "SLICEL", + "SLICE_X59Y77": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y78": { + "bits": {}, + "grid_x": 103, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X40Y78", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y78": "SLICEL", + "SLICE_X59Y78": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y79": { + "bits": {}, + "grid_x": 103, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X40Y79", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y79": "SLICEL", + "SLICE_X59Y79": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y8": { + "bits": {}, + "grid_x": 103, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X40Y8", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y8": "SLICEL", + "SLICE_X59Y8": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y80": { + "bits": {}, + "grid_x": 103, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X40Y80", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y80": "SLICEL", + "SLICE_X59Y80": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y81": { + "bits": {}, + "grid_x": 103, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X40Y81", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y81": "SLICEL", + "SLICE_X59Y81": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y82": { + "bits": {}, + "grid_x": 103, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X40Y82", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y82": "SLICEL", + "SLICE_X59Y82": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y83": { + "bits": {}, + "grid_x": 103, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X40Y83", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y83": "SLICEL", + "SLICE_X59Y83": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y84": { + "bits": {}, + "grid_x": 103, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X40Y84", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y84": "SLICEL", + "SLICE_X59Y84": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y85": { + "bits": {}, + "grid_x": 103, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X40Y85", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y85": "SLICEL", + "SLICE_X59Y85": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y86": { + "bits": {}, + "grid_x": 103, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X40Y86", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y86": "SLICEL", + "SLICE_X59Y86": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y87": { + "bits": {}, + "grid_x": 103, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X40Y87", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y87": "SLICEL", + "SLICE_X59Y87": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y88": { + "bits": {}, + "grid_x": 103, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X40Y88", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y88": "SLICEL", + "SLICE_X59Y88": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y89": { + "bits": {}, + "grid_x": 103, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X40Y89", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y89": "SLICEL", + "SLICE_X59Y89": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y9": { + "bits": {}, + "grid_x": 103, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X40Y9", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y9": "SLICEL", + "SLICE_X59Y9": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y90": { + "bits": {}, + "grid_x": 103, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X40Y90", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y90": "SLICEL", + "SLICE_X59Y90": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y91": { + "bits": {}, + "grid_x": 103, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X40Y91", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y91": "SLICEL", + "SLICE_X59Y91": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y92": { + "bits": {}, + "grid_x": 103, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X40Y92", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y92": "SLICEL", + "SLICE_X59Y92": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y93": { + "bits": {}, + "grid_x": 103, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X40Y93", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y93": "SLICEL", + "SLICE_X59Y93": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y94": { + "bits": {}, + "grid_x": 103, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X40Y94", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y94": "SLICEL", + "SLICE_X59Y94": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y95": { + "bits": {}, + "grid_x": 103, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X40Y95", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y95": "SLICEL", + "SLICE_X59Y95": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y96": { + "bits": {}, + "grid_x": 103, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X40Y96", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y96": "SLICEL", + "SLICE_X59Y96": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y97": { + "bits": {}, + "grid_x": 103, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X40Y97", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y97": "SLICEL", + "SLICE_X59Y97": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y98": { + "bits": {}, + "grid_x": 103, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X40Y98", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y98": "SLICEL", + "SLICE_X59Y98": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X40Y99": { + "bits": {}, + "grid_x": 103, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X40Y99", + "segment_type": "clbll_l", + "sites": { + "SLICE_X58Y99": "SLICEL", + "SLICE_X59Y99": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y0": { + "bits": {}, + "grid_x": 14, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X4Y0", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y0": "SLICEL", + "SLICE_X5Y0": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y1": { + "bits": {}, + "grid_x": 14, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X4Y1", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y1": "SLICEL", + "SLICE_X5Y1": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y10": { + "bits": {}, + "grid_x": 14, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X4Y10", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y10": "SLICEL", + "SLICE_X5Y10": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y100": { + "bits": {}, + "grid_x": 14, + "grid_y": 103, + "segment": "SEG_CLBLL_L_X4Y100", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y100": "SLICEL", + "SLICE_X5Y100": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y101": { + "bits": {}, + "grid_x": 14, + "grid_y": 102, + "segment": "SEG_CLBLL_L_X4Y101", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y101": "SLICEL", + "SLICE_X5Y101": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y102": { + "bits": {}, + "grid_x": 14, + "grid_y": 101, + "segment": "SEG_CLBLL_L_X4Y102", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y102": "SLICEL", + "SLICE_X5Y102": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y103": { + "bits": {}, + "grid_x": 14, + "grid_y": 100, + "segment": "SEG_CLBLL_L_X4Y103", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y103": "SLICEL", + "SLICE_X5Y103": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y104": { + "bits": {}, + "grid_x": 14, + "grid_y": 99, + "segment": "SEG_CLBLL_L_X4Y104", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y104": "SLICEL", + "SLICE_X5Y104": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y105": { + "bits": {}, + "grid_x": 14, + "grid_y": 98, + "segment": "SEG_CLBLL_L_X4Y105", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y105": "SLICEL", + "SLICE_X5Y105": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y106": { + "bits": {}, + "grid_x": 14, + "grid_y": 97, + "segment": "SEG_CLBLL_L_X4Y106", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y106": "SLICEL", + "SLICE_X5Y106": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y107": { + "bits": {}, + "grid_x": 14, + "grid_y": 96, + "segment": "SEG_CLBLL_L_X4Y107", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y107": "SLICEL", + "SLICE_X5Y107": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y108": { + "bits": {}, + "grid_x": 14, + "grid_y": 95, + "segment": "SEG_CLBLL_L_X4Y108", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y108": "SLICEL", + "SLICE_X5Y108": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y109": { + "bits": {}, + "grid_x": 14, + "grid_y": 94, + "segment": "SEG_CLBLL_L_X4Y109", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y109": "SLICEL", + "SLICE_X5Y109": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y11": { + "bits": {}, + "grid_x": 14, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X4Y11", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y11": "SLICEL", + "SLICE_X5Y11": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y110": { + "bits": {}, + "grid_x": 14, + "grid_y": 93, + "segment": "SEG_CLBLL_L_X4Y110", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y110": "SLICEL", + "SLICE_X5Y110": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y111": { + "bits": {}, + "grid_x": 14, + "grid_y": 92, + "segment": "SEG_CLBLL_L_X4Y111", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y111": "SLICEL", + "SLICE_X5Y111": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y112": { + "bits": {}, + "grid_x": 14, + "grid_y": 91, + "segment": "SEG_CLBLL_L_X4Y112", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y112": "SLICEL", + "SLICE_X5Y112": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y113": { + "bits": {}, + "grid_x": 14, + "grid_y": 90, + "segment": "SEG_CLBLL_L_X4Y113", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y113": "SLICEL", + "SLICE_X5Y113": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y114": { + "bits": {}, + "grid_x": 14, + "grid_y": 89, + "segment": "SEG_CLBLL_L_X4Y114", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y114": "SLICEL", + "SLICE_X5Y114": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y115": { + "bits": {}, + "grid_x": 14, + "grid_y": 88, + "segment": "SEG_CLBLL_L_X4Y115", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y115": "SLICEL", + "SLICE_X5Y115": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y116": { + "bits": {}, + "grid_x": 14, + "grid_y": 87, + "segment": "SEG_CLBLL_L_X4Y116", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y116": "SLICEL", + "SLICE_X5Y116": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y117": { + "bits": {}, + "grid_x": 14, + "grid_y": 86, + "segment": "SEG_CLBLL_L_X4Y117", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y117": "SLICEL", + "SLICE_X5Y117": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y118": { + "bits": {}, + "grid_x": 14, + "grid_y": 85, + "segment": "SEG_CLBLL_L_X4Y118", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y118": "SLICEL", + "SLICE_X5Y118": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y119": { + "bits": {}, + "grid_x": 14, + "grid_y": 84, + "segment": "SEG_CLBLL_L_X4Y119", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y119": "SLICEL", + "SLICE_X5Y119": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y12": { + "bits": {}, + "grid_x": 14, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X4Y12", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y12": "SLICEL", + "SLICE_X5Y12": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y120": { + "bits": {}, + "grid_x": 14, + "grid_y": 83, + "segment": "SEG_CLBLL_L_X4Y120", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y120": "SLICEL", + "SLICE_X5Y120": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y121": { + "bits": {}, + "grid_x": 14, + "grid_y": 82, + "segment": "SEG_CLBLL_L_X4Y121", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y121": "SLICEL", + "SLICE_X5Y121": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y122": { + "bits": {}, + "grid_x": 14, + "grid_y": 81, + "segment": "SEG_CLBLL_L_X4Y122", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y122": "SLICEL", + "SLICE_X5Y122": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y123": { + "bits": {}, + "grid_x": 14, + "grid_y": 80, + "segment": "SEG_CLBLL_L_X4Y123", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y123": "SLICEL", + "SLICE_X5Y123": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y124": { + "bits": {}, + "grid_x": 14, + "grid_y": 79, + "segment": "SEG_CLBLL_L_X4Y124", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y124": "SLICEL", + "SLICE_X5Y124": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y125": { + "bits": {}, + "grid_x": 14, + "grid_y": 77, + "segment": "SEG_CLBLL_L_X4Y125", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y125": "SLICEL", + "SLICE_X5Y125": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y126": { + "bits": {}, + "grid_x": 14, + "grid_y": 76, + "segment": "SEG_CLBLL_L_X4Y126", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y126": "SLICEL", + "SLICE_X5Y126": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y127": { + "bits": {}, + "grid_x": 14, + "grid_y": 75, + "segment": "SEG_CLBLL_L_X4Y127", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y127": "SLICEL", + "SLICE_X5Y127": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y128": { + "bits": {}, + "grid_x": 14, + "grid_y": 74, + "segment": "SEG_CLBLL_L_X4Y128", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y128": "SLICEL", + "SLICE_X5Y128": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y129": { + "bits": {}, + "grid_x": 14, + "grid_y": 73, + "segment": "SEG_CLBLL_L_X4Y129", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y129": "SLICEL", + "SLICE_X5Y129": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y13": { + "bits": {}, + "grid_x": 14, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X4Y13", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y13": "SLICEL", + "SLICE_X5Y13": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y130": { + "bits": {}, + "grid_x": 14, + "grid_y": 72, + "segment": "SEG_CLBLL_L_X4Y130", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y130": "SLICEL", + "SLICE_X5Y130": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y131": { + "bits": {}, + "grid_x": 14, + "grid_y": 71, + "segment": "SEG_CLBLL_L_X4Y131", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y131": "SLICEL", + "SLICE_X5Y131": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y132": { + "bits": {}, + "grid_x": 14, + "grid_y": 70, + "segment": "SEG_CLBLL_L_X4Y132", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y132": "SLICEL", + "SLICE_X5Y132": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y133": { + "bits": {}, + "grid_x": 14, + "grid_y": 69, + "segment": "SEG_CLBLL_L_X4Y133", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y133": "SLICEL", + "SLICE_X5Y133": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y134": { + "bits": {}, + "grid_x": 14, + "grid_y": 68, + "segment": "SEG_CLBLL_L_X4Y134", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y134": "SLICEL", + "SLICE_X5Y134": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y135": { + "bits": {}, + "grid_x": 14, + "grid_y": 67, + "segment": "SEG_CLBLL_L_X4Y135", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y135": "SLICEL", + "SLICE_X5Y135": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y136": { + "bits": {}, + "grid_x": 14, + "grid_y": 66, + "segment": "SEG_CLBLL_L_X4Y136", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y136": "SLICEL", + "SLICE_X5Y136": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y137": { + "bits": {}, + "grid_x": 14, + "grid_y": 65, + "segment": "SEG_CLBLL_L_X4Y137", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y137": "SLICEL", + "SLICE_X5Y137": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y138": { + "bits": {}, + "grid_x": 14, + "grid_y": 64, + "segment": "SEG_CLBLL_L_X4Y138", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y138": "SLICEL", + "SLICE_X5Y138": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y139": { + "bits": {}, + "grid_x": 14, + "grid_y": 63, + "segment": "SEG_CLBLL_L_X4Y139", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y139": "SLICEL", + "SLICE_X5Y139": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y14": { + "bits": {}, + "grid_x": 14, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X4Y14", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y14": "SLICEL", + "SLICE_X5Y14": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y140": { + "bits": {}, + "grid_x": 14, + "grid_y": 62, + "segment": "SEG_CLBLL_L_X4Y140", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y140": "SLICEL", + "SLICE_X5Y140": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y141": { + "bits": {}, + "grid_x": 14, + "grid_y": 61, + "segment": "SEG_CLBLL_L_X4Y141", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y141": "SLICEL", + "SLICE_X5Y141": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y142": { + "bits": {}, + "grid_x": 14, + "grid_y": 60, + "segment": "SEG_CLBLL_L_X4Y142", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y142": "SLICEL", + "SLICE_X5Y142": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y143": { + "bits": {}, + "grid_x": 14, + "grid_y": 59, + "segment": "SEG_CLBLL_L_X4Y143", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y143": "SLICEL", + "SLICE_X5Y143": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y144": { + "bits": {}, + "grid_x": 14, + "grid_y": 58, + "segment": "SEG_CLBLL_L_X4Y144", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y144": "SLICEL", + "SLICE_X5Y144": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y145": { + "bits": {}, + "grid_x": 14, + "grid_y": 57, + "segment": "SEG_CLBLL_L_X4Y145", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y145": "SLICEL", + "SLICE_X5Y145": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y146": { + "bits": {}, + "grid_x": 14, + "grid_y": 56, + "segment": "SEG_CLBLL_L_X4Y146", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y146": "SLICEL", + "SLICE_X5Y146": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y147": { + "bits": {}, + "grid_x": 14, + "grid_y": 55, + "segment": "SEG_CLBLL_L_X4Y147", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y147": "SLICEL", + "SLICE_X5Y147": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y148": { + "bits": {}, + "grid_x": 14, + "grid_y": 54, + "segment": "SEG_CLBLL_L_X4Y148", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y148": "SLICEL", + "SLICE_X5Y148": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y149": { + "bits": {}, + "grid_x": 14, + "grid_y": 53, + "segment": "SEG_CLBLL_L_X4Y149", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y149": "SLICEL", + "SLICE_X5Y149": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y15": { + "bits": {}, + "grid_x": 14, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X4Y15", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y15": "SLICEL", + "SLICE_X5Y15": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y150": { + "bits": {}, + "grid_x": 14, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X4Y150", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y150": "SLICEL", + "SLICE_X5Y150": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y151": { + "bits": {}, + "grid_x": 14, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X4Y151", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y151": "SLICEL", + "SLICE_X5Y151": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y152": { + "bits": {}, + "grid_x": 14, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X4Y152", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y152": "SLICEL", + "SLICE_X5Y152": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y153": { + "bits": {}, + "grid_x": 14, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X4Y153", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y153": "SLICEL", + "SLICE_X5Y153": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y154": { + "bits": {}, + "grid_x": 14, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X4Y154", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y154": "SLICEL", + "SLICE_X5Y154": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y155": { + "bits": {}, + "grid_x": 14, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X4Y155", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y155": "SLICEL", + "SLICE_X5Y155": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y156": { + "bits": {}, + "grid_x": 14, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X4Y156", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y156": "SLICEL", + "SLICE_X5Y156": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y157": { + "bits": {}, + "grid_x": 14, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X4Y157", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y157": "SLICEL", + "SLICE_X5Y157": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y158": { + "bits": {}, + "grid_x": 14, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X4Y158", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y158": "SLICEL", + "SLICE_X5Y158": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y159": { + "bits": {}, + "grid_x": 14, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X4Y159", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y159": "SLICEL", + "SLICE_X5Y159": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y16": { + "bits": {}, + "grid_x": 14, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X4Y16", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y16": "SLICEL", + "SLICE_X5Y16": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y160": { + "bits": {}, + "grid_x": 14, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X4Y160", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y160": "SLICEL", + "SLICE_X5Y160": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y161": { + "bits": {}, + "grid_x": 14, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X4Y161", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y161": "SLICEL", + "SLICE_X5Y161": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y162": { + "bits": {}, + "grid_x": 14, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X4Y162", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y162": "SLICEL", + "SLICE_X5Y162": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y163": { + "bits": {}, + "grid_x": 14, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X4Y163", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y163": "SLICEL", + "SLICE_X5Y163": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y164": { + "bits": {}, + "grid_x": 14, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X4Y164", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y164": "SLICEL", + "SLICE_X5Y164": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y165": { + "bits": {}, + "grid_x": 14, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X4Y165", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y165": "SLICEL", + "SLICE_X5Y165": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y166": { + "bits": {}, + "grid_x": 14, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X4Y166", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y166": "SLICEL", + "SLICE_X5Y166": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y167": { + "bits": {}, + "grid_x": 14, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X4Y167", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y167": "SLICEL", + "SLICE_X5Y167": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y168": { + "bits": {}, + "grid_x": 14, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X4Y168", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y168": "SLICEL", + "SLICE_X5Y168": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y169": { + "bits": {}, + "grid_x": 14, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X4Y169", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y169": "SLICEL", + "SLICE_X5Y169": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y17": { + "bits": {}, + "grid_x": 14, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X4Y17", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y17": "SLICEL", + "SLICE_X5Y17": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y170": { + "bits": {}, + "grid_x": 14, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X4Y170", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y170": "SLICEL", + "SLICE_X5Y170": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y171": { + "bits": {}, + "grid_x": 14, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X4Y171", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y171": "SLICEL", + "SLICE_X5Y171": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y172": { + "bits": {}, + "grid_x": 14, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X4Y172", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y172": "SLICEL", + "SLICE_X5Y172": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y173": { + "bits": {}, + "grid_x": 14, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X4Y173", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y173": "SLICEL", + "SLICE_X5Y173": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y174": { + "bits": {}, + "grid_x": 14, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X4Y174", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y174": "SLICEL", + "SLICE_X5Y174": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y175": { + "bits": {}, + "grid_x": 14, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X4Y175", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y175": "SLICEL", + "SLICE_X5Y175": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y176": { + "bits": {}, + "grid_x": 14, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X4Y176", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y176": "SLICEL", + "SLICE_X5Y176": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y177": { + "bits": {}, + "grid_x": 14, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X4Y177", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y177": "SLICEL", + "SLICE_X5Y177": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y178": { + "bits": {}, + "grid_x": 14, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X4Y178", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y178": "SLICEL", + "SLICE_X5Y178": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y179": { + "bits": {}, + "grid_x": 14, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X4Y179", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y179": "SLICEL", + "SLICE_X5Y179": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y18": { + "bits": {}, + "grid_x": 14, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X4Y18", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y18": "SLICEL", + "SLICE_X5Y18": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y180": { + "bits": {}, + "grid_x": 14, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X4Y180", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y180": "SLICEL", + "SLICE_X5Y180": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y181": { + "bits": {}, + "grid_x": 14, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X4Y181", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y181": "SLICEL", + "SLICE_X5Y181": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y182": { + "bits": {}, + "grid_x": 14, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X4Y182", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y182": "SLICEL", + "SLICE_X5Y182": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y183": { + "bits": {}, + "grid_x": 14, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X4Y183", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y183": "SLICEL", + "SLICE_X5Y183": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y184": { + "bits": {}, + "grid_x": 14, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X4Y184", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y184": "SLICEL", + "SLICE_X5Y184": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y185": { + "bits": {}, + "grid_x": 14, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X4Y185", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y185": "SLICEL", + "SLICE_X5Y185": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y186": { + "bits": {}, + "grid_x": 14, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X4Y186", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y186": "SLICEL", + "SLICE_X5Y186": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y187": { + "bits": {}, + "grid_x": 14, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X4Y187", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y187": "SLICEL", + "SLICE_X5Y187": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y188": { + "bits": {}, + "grid_x": 14, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X4Y188", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y188": "SLICEL", + "SLICE_X5Y188": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y189": { + "bits": {}, + "grid_x": 14, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X4Y189", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y189": "SLICEL", + "SLICE_X5Y189": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y19": { + "bits": {}, + "grid_x": 14, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X4Y19", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y19": "SLICEL", + "SLICE_X5Y19": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y190": { + "bits": {}, + "grid_x": 14, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X4Y190", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y190": "SLICEL", + "SLICE_X5Y190": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y191": { + "bits": {}, + "grid_x": 14, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X4Y191", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y191": "SLICEL", + "SLICE_X5Y191": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y192": { + "bits": {}, + "grid_x": 14, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X4Y192", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y192": "SLICEL", + "SLICE_X5Y192": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y193": { + "bits": {}, + "grid_x": 14, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X4Y193", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y193": "SLICEL", + "SLICE_X5Y193": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y194": { + "bits": {}, + "grid_x": 14, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X4Y194", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y194": "SLICEL", + "SLICE_X5Y194": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y195": { + "bits": {}, + "grid_x": 14, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X4Y195", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y195": "SLICEL", + "SLICE_X5Y195": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y196": { + "bits": {}, + "grid_x": 14, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X4Y196", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y196": "SLICEL", + "SLICE_X5Y196": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y197": { + "bits": {}, + "grid_x": 14, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X4Y197", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y197": "SLICEL", + "SLICE_X5Y197": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y198": { + "bits": {}, + "grid_x": 14, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X4Y198", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y198": "SLICEL", + "SLICE_X5Y198": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y199": { + "bits": {}, + "grid_x": 14, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X4Y199", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y199": "SLICEL", + "SLICE_X5Y199": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y2": { + "bits": {}, + "grid_x": 14, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X4Y2", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y2": "SLICEL", + "SLICE_X5Y2": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y20": { + "bits": {}, + "grid_x": 14, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X4Y20", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y20": "SLICEL", + "SLICE_X5Y20": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y21": { + "bits": {}, + "grid_x": 14, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X4Y21", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y21": "SLICEL", + "SLICE_X5Y21": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y22": { + "bits": {}, + "grid_x": 14, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X4Y22", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y22": "SLICEL", + "SLICE_X5Y22": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y23": { + "bits": {}, + "grid_x": 14, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X4Y23", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y23": "SLICEL", + "SLICE_X5Y23": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y24": { + "bits": {}, + "grid_x": 14, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X4Y24", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y24": "SLICEL", + "SLICE_X5Y24": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y25": { + "bits": {}, + "grid_x": 14, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X4Y25", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y25": "SLICEL", + "SLICE_X5Y25": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y26": { + "bits": {}, + "grid_x": 14, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X4Y26", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y26": "SLICEL", + "SLICE_X5Y26": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y27": { + "bits": {}, + "grid_x": 14, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X4Y27", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y27": "SLICEL", + "SLICE_X5Y27": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y28": { + "bits": {}, + "grid_x": 14, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X4Y28", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y28": "SLICEL", + "SLICE_X5Y28": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y29": { + "bits": {}, + "grid_x": 14, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X4Y29", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y29": "SLICEL", + "SLICE_X5Y29": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y3": { + "bits": {}, + "grid_x": 14, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X4Y3", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y3": "SLICEL", + "SLICE_X5Y3": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y30": { + "bits": {}, + "grid_x": 14, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X4Y30", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y30": "SLICEL", + "SLICE_X5Y30": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y31": { + "bits": {}, + "grid_x": 14, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X4Y31", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y31": "SLICEL", + "SLICE_X5Y31": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y32": { + "bits": {}, + "grid_x": 14, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X4Y32", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y32": "SLICEL", + "SLICE_X5Y32": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y33": { + "bits": {}, + "grid_x": 14, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X4Y33", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y33": "SLICEL", + "SLICE_X5Y33": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y34": { + "bits": {}, + "grid_x": 14, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X4Y34", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y34": "SLICEL", + "SLICE_X5Y34": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y35": { + "bits": {}, + "grid_x": 14, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X4Y35", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y35": "SLICEL", + "SLICE_X5Y35": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y36": { + "bits": {}, + "grid_x": 14, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X4Y36", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y36": "SLICEL", + "SLICE_X5Y36": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y37": { + "bits": {}, + "grid_x": 14, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X4Y37", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y37": "SLICEL", + "SLICE_X5Y37": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y38": { + "bits": {}, + "grid_x": 14, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X4Y38", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y38": "SLICEL", + "SLICE_X5Y38": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y39": { + "bits": {}, + "grid_x": 14, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X4Y39", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y39": "SLICEL", + "SLICE_X5Y39": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y4": { + "bits": {}, + "grid_x": 14, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X4Y4", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y4": "SLICEL", + "SLICE_X5Y4": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y40": { + "bits": {}, + "grid_x": 14, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X4Y40", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y40": "SLICEL", + "SLICE_X5Y40": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y41": { + "bits": {}, + "grid_x": 14, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X4Y41", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y41": "SLICEL", + "SLICE_X5Y41": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y42": { + "bits": {}, + "grid_x": 14, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X4Y42", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y42": "SLICEL", + "SLICE_X5Y42": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y43": { + "bits": {}, + "grid_x": 14, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X4Y43", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y43": "SLICEL", + "SLICE_X5Y43": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y44": { + "bits": {}, + "grid_x": 14, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X4Y44", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y44": "SLICEL", + "SLICE_X5Y44": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y45": { + "bits": {}, + "grid_x": 14, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X4Y45", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y45": "SLICEL", + "SLICE_X5Y45": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y46": { + "bits": {}, + "grid_x": 14, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X4Y46", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y46": "SLICEL", + "SLICE_X5Y46": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y47": { + "bits": {}, + "grid_x": 14, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X4Y47", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y47": "SLICEL", + "SLICE_X5Y47": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y48": { + "bits": {}, + "grid_x": 14, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X4Y48", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y48": "SLICEL", + "SLICE_X5Y48": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y49": { + "bits": {}, + "grid_x": 14, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X4Y49", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y49": "SLICEL", + "SLICE_X5Y49": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y5": { + "bits": {}, + "grid_x": 14, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X4Y5", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y5": "SLICEL", + "SLICE_X5Y5": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X4Y50", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y50": "SLICEL", + "SLICE_X5Y50": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X4Y51", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y51": "SLICEL", + "SLICE_X5Y51": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X4Y52", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y52": "SLICEL", + "SLICE_X5Y52": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X4Y53", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y53": "SLICEL", + "SLICE_X5Y53": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X4Y54", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y54": "SLICEL", + "SLICE_X5Y54": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X4Y55", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y55": "SLICEL", + "SLICE_X5Y55": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X4Y56", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y56": "SLICEL", + "SLICE_X5Y56": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X4Y57", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y57": "SLICEL", + "SLICE_X5Y57": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X4Y58", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y58": "SLICEL", + "SLICE_X5Y58": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X4Y59", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y59": "SLICEL", + "SLICE_X5Y59": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y6": { + "bits": {}, + "grid_x": 14, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X4Y6", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y6": "SLICEL", + "SLICE_X5Y6": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X4Y60", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y60": "SLICEL", + "SLICE_X5Y60": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X4Y61", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y61": "SLICEL", + "SLICE_X5Y61": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X4Y62", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y62": "SLICEL", + "SLICE_X5Y62": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X4Y63", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y63": "SLICEL", + "SLICE_X5Y63": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X4Y64", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y64": "SLICEL", + "SLICE_X5Y64": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X4Y65", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y65": "SLICEL", + "SLICE_X5Y65": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X4Y66", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y66": "SLICEL", + "SLICE_X5Y66": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X4Y67", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y67": "SLICEL", + "SLICE_X5Y67": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X4Y68", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y68": "SLICEL", + "SLICE_X5Y68": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X4Y69", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y69": "SLICEL", + "SLICE_X5Y69": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y7": { + "bits": {}, + "grid_x": 14, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X4Y7", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y7": "SLICEL", + "SLICE_X5Y7": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X4Y70", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y70": "SLICEL", + "SLICE_X5Y70": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X4Y71", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y71": "SLICEL", + "SLICE_X5Y71": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X4Y72", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y72": "SLICEL", + "SLICE_X5Y72": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X4Y73", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y73": "SLICEL", + "SLICE_X5Y73": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X4Y74", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y74": "SLICEL", + "SLICE_X5Y74": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X4Y75", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y75": "SLICEL", + "SLICE_X5Y75": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X4Y76", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y76": "SLICEL", + "SLICE_X5Y76": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X4Y77", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y77": "SLICEL", + "SLICE_X5Y77": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X4Y78", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y78": "SLICEL", + "SLICE_X5Y78": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X4Y79", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y79": "SLICEL", + "SLICE_X5Y79": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y8": { + "bits": {}, + "grid_x": 14, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X4Y8", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y8": "SLICEL", + "SLICE_X5Y8": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X4Y80", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y80": "SLICEL", + "SLICE_X5Y80": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X4Y81", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y81": "SLICEL", + "SLICE_X5Y81": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X4Y82", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y82": "SLICEL", + "SLICE_X5Y82": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X4Y83", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y83": "SLICEL", + "SLICE_X5Y83": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X4Y84", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y84": "SLICEL", + "SLICE_X5Y84": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X4Y85", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y85": "SLICEL", + "SLICE_X5Y85": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X4Y86", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y86": "SLICEL", + "SLICE_X5Y86": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X4Y87", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y87": "SLICEL", + "SLICE_X5Y87": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X4Y88", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y88": "SLICEL", + "SLICE_X5Y88": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X4Y89", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y89": "SLICEL", + "SLICE_X5Y89": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y9": { + "bits": {}, + "grid_x": 14, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X4Y9", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y9": "SLICEL", + "SLICE_X5Y9": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X4Y90", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y90": "SLICEL", + "SLICE_X5Y90": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X4Y91", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y91": "SLICEL", + "SLICE_X5Y91": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X4Y92", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y92": "SLICEL", + "SLICE_X5Y92": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X4Y93", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y93": "SLICEL", + "SLICE_X5Y93": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X4Y94", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y94": "SLICEL", + "SLICE_X5Y94": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X4Y95", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y95": "SLICEL", + "SLICE_X5Y95": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X4Y96", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y96": "SLICEL", + "SLICE_X5Y96": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X4Y97", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y97": "SLICEL", + "SLICE_X5Y97": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X4Y98", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y98": "SLICEL", + "SLICE_X5Y98": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_L_X4Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 36, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 14, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X4Y99", + "segment_type": "clbll_l", + "sites": { + "SLICE_X4Y99": "SLICEL", + "SLICE_X5Y99": "SLICEL" + }, + "type": "CLBLL_L" + }, + "CLBLL_R_X19Y0": { + "bits": {}, + "grid_x": 53, + "grid_y": 207, + "segment": "SEG_CLBLL_R_X19Y0", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y0": "SLICEL", + "SLICE_X27Y0": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y1": { + "bits": {}, + "grid_x": 53, + "grid_y": 206, + "segment": "SEG_CLBLL_R_X19Y1", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y1": "SLICEL", + "SLICE_X27Y1": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y10": { + "bits": {}, + "grid_x": 53, + "grid_y": 197, + "segment": "SEG_CLBLL_R_X19Y10", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y10": "SLICEL", + "SLICE_X27Y10": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y11": { + "bits": {}, + "grid_x": 53, + "grid_y": 196, + "segment": "SEG_CLBLL_R_X19Y11", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y11": "SLICEL", + "SLICE_X27Y11": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y12": { + "bits": {}, + "grid_x": 53, + "grid_y": 195, + "segment": "SEG_CLBLL_R_X19Y12", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y12": "SLICEL", + "SLICE_X27Y12": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y13": { + "bits": {}, + "grid_x": 53, + "grid_y": 194, + "segment": "SEG_CLBLL_R_X19Y13", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y13": "SLICEL", + "SLICE_X27Y13": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y14": { + "bits": {}, + "grid_x": 53, + "grid_y": 193, + "segment": "SEG_CLBLL_R_X19Y14", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y14": "SLICEL", + "SLICE_X27Y14": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y15": { + "bits": {}, + "grid_x": 53, + "grid_y": 192, + "segment": "SEG_CLBLL_R_X19Y15", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y15": "SLICEL", + "SLICE_X27Y15": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y150": { + "bits": {}, + "grid_x": 53, + "grid_y": 51, + "segment": "SEG_CLBLL_R_X19Y150", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y150": "SLICEL", + "SLICE_X27Y150": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y151": { + "bits": {}, + "grid_x": 53, + "grid_y": 50, + "segment": "SEG_CLBLL_R_X19Y151", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y151": "SLICEL", + "SLICE_X27Y151": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y152": { + "bits": {}, + "grid_x": 53, + "grid_y": 49, + "segment": "SEG_CLBLL_R_X19Y152", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y152": "SLICEL", + "SLICE_X27Y152": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y153": { + "bits": {}, + "grid_x": 53, + "grid_y": 48, + "segment": "SEG_CLBLL_R_X19Y153", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y153": "SLICEL", + "SLICE_X27Y153": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y154": { + "bits": {}, + "grid_x": 53, + "grid_y": 47, + "segment": "SEG_CLBLL_R_X19Y154", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y154": "SLICEL", + "SLICE_X27Y154": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y155": { + "bits": {}, + "grid_x": 53, + "grid_y": 46, + "segment": "SEG_CLBLL_R_X19Y155", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y155": "SLICEL", + "SLICE_X27Y155": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y156": { + "bits": {}, + "grid_x": 53, + "grid_y": 45, + "segment": "SEG_CLBLL_R_X19Y156", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y156": "SLICEL", + "SLICE_X27Y156": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y157": { + "bits": {}, + "grid_x": 53, + "grid_y": 44, + "segment": "SEG_CLBLL_R_X19Y157", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y157": "SLICEL", + "SLICE_X27Y157": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y158": { + "bits": {}, + "grid_x": 53, + "grid_y": 43, + "segment": "SEG_CLBLL_R_X19Y158", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y158": "SLICEL", + "SLICE_X27Y158": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y159": { + "bits": {}, + "grid_x": 53, + "grid_y": 42, + "segment": "SEG_CLBLL_R_X19Y159", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y159": "SLICEL", + "SLICE_X27Y159": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y16": { + "bits": {}, + "grid_x": 53, + "grid_y": 191, + "segment": "SEG_CLBLL_R_X19Y16", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y16": "SLICEL", + "SLICE_X27Y16": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y160": { + "bits": {}, + "grid_x": 53, + "grid_y": 41, + "segment": "SEG_CLBLL_R_X19Y160", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y160": "SLICEL", + "SLICE_X27Y160": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y161": { + "bits": {}, + "grid_x": 53, + "grid_y": 40, + "segment": "SEG_CLBLL_R_X19Y161", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y161": "SLICEL", + "SLICE_X27Y161": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y162": { + "bits": {}, + "grid_x": 53, + "grid_y": 39, + "segment": "SEG_CLBLL_R_X19Y162", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y162": "SLICEL", + "SLICE_X27Y162": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y163": { + "bits": {}, + "grid_x": 53, + "grid_y": 38, + "segment": "SEG_CLBLL_R_X19Y163", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y163": "SLICEL", + "SLICE_X27Y163": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y164": { + "bits": {}, + "grid_x": 53, + "grid_y": 37, + "segment": "SEG_CLBLL_R_X19Y164", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y164": "SLICEL", + "SLICE_X27Y164": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y165": { + "bits": {}, + "grid_x": 53, + "grid_y": 36, + "segment": "SEG_CLBLL_R_X19Y165", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y165": "SLICEL", + "SLICE_X27Y165": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y166": { + "bits": {}, + "grid_x": 53, + "grid_y": 35, + "segment": "SEG_CLBLL_R_X19Y166", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y166": "SLICEL", + "SLICE_X27Y166": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y167": { + "bits": {}, + "grid_x": 53, + "grid_y": 34, + "segment": "SEG_CLBLL_R_X19Y167", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y167": "SLICEL", + "SLICE_X27Y167": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y168": { + "bits": {}, + "grid_x": 53, + "grid_y": 33, + "segment": "SEG_CLBLL_R_X19Y168", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y168": "SLICEL", + "SLICE_X27Y168": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y169": { + "bits": {}, + "grid_x": 53, + "grid_y": 32, + "segment": "SEG_CLBLL_R_X19Y169", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y169": "SLICEL", + "SLICE_X27Y169": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y17": { + "bits": {}, + "grid_x": 53, + "grid_y": 190, + "segment": "SEG_CLBLL_R_X19Y17", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y17": "SLICEL", + "SLICE_X27Y17": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y170": { + "bits": {}, + "grid_x": 53, + "grid_y": 31, + "segment": "SEG_CLBLL_R_X19Y170", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y170": "SLICEL", + "SLICE_X27Y170": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y171": { + "bits": {}, + "grid_x": 53, + "grid_y": 30, + "segment": "SEG_CLBLL_R_X19Y171", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y171": "SLICEL", + "SLICE_X27Y171": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y172": { + "bits": {}, + "grid_x": 53, + "grid_y": 29, + "segment": "SEG_CLBLL_R_X19Y172", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y172": "SLICEL", + "SLICE_X27Y172": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y173": { + "bits": {}, + "grid_x": 53, + "grid_y": 28, + "segment": "SEG_CLBLL_R_X19Y173", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y173": "SLICEL", + "SLICE_X27Y173": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y174": { + "bits": {}, + "grid_x": 53, + "grid_y": 27, + "segment": "SEG_CLBLL_R_X19Y174", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y174": "SLICEL", + "SLICE_X27Y174": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y175": { + "bits": {}, + "grid_x": 53, + "grid_y": 25, + "segment": "SEG_CLBLL_R_X19Y175", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y175": "SLICEL", + "SLICE_X27Y175": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y176": { + "bits": {}, + "grid_x": 53, + "grid_y": 24, + "segment": "SEG_CLBLL_R_X19Y176", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y176": "SLICEL", + "SLICE_X27Y176": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y177": { + "bits": {}, + "grid_x": 53, + "grid_y": 23, + "segment": "SEG_CLBLL_R_X19Y177", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y177": "SLICEL", + "SLICE_X27Y177": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y178": { + "bits": {}, + "grid_x": 53, + "grid_y": 22, + "segment": "SEG_CLBLL_R_X19Y178", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y178": "SLICEL", + "SLICE_X27Y178": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y179": { + "bits": {}, + "grid_x": 53, + "grid_y": 21, + "segment": "SEG_CLBLL_R_X19Y179", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y179": "SLICEL", + "SLICE_X27Y179": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y18": { + "bits": {}, + "grid_x": 53, + "grid_y": 189, + "segment": "SEG_CLBLL_R_X19Y18", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y18": "SLICEL", + "SLICE_X27Y18": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y180": { + "bits": {}, + "grid_x": 53, + "grid_y": 20, + "segment": "SEG_CLBLL_R_X19Y180", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y180": "SLICEL", + "SLICE_X27Y180": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y181": { + "bits": {}, + "grid_x": 53, + "grid_y": 19, + "segment": "SEG_CLBLL_R_X19Y181", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y181": "SLICEL", + "SLICE_X27Y181": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y182": { + "bits": {}, + "grid_x": 53, + "grid_y": 18, + "segment": "SEG_CLBLL_R_X19Y182", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y182": "SLICEL", + "SLICE_X27Y182": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y183": { + "bits": {}, + "grid_x": 53, + "grid_y": 17, + "segment": "SEG_CLBLL_R_X19Y183", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y183": "SLICEL", + "SLICE_X27Y183": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y184": { + "bits": {}, + "grid_x": 53, + "grid_y": 16, + "segment": "SEG_CLBLL_R_X19Y184", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y184": "SLICEL", + "SLICE_X27Y184": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y185": { + "bits": {}, + "grid_x": 53, + "grid_y": 15, + "segment": "SEG_CLBLL_R_X19Y185", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y185": "SLICEL", + "SLICE_X27Y185": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y186": { + "bits": {}, + "grid_x": 53, + "grid_y": 14, + "segment": "SEG_CLBLL_R_X19Y186", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y186": "SLICEL", + "SLICE_X27Y186": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y187": { + "bits": {}, + "grid_x": 53, + "grid_y": 13, + "segment": "SEG_CLBLL_R_X19Y187", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y187": "SLICEL", + "SLICE_X27Y187": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y188": { + "bits": {}, + "grid_x": 53, + "grid_y": 12, + "segment": "SEG_CLBLL_R_X19Y188", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y188": "SLICEL", + "SLICE_X27Y188": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y189": { + "bits": {}, + "grid_x": 53, + "grid_y": 11, + "segment": "SEG_CLBLL_R_X19Y189", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y189": "SLICEL", + "SLICE_X27Y189": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y19": { + "bits": {}, + "grid_x": 53, + "grid_y": 188, + "segment": "SEG_CLBLL_R_X19Y19", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y19": "SLICEL", + "SLICE_X27Y19": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y190": { + "bits": {}, + "grid_x": 53, + "grid_y": 10, + "segment": "SEG_CLBLL_R_X19Y190", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y190": "SLICEL", + "SLICE_X27Y190": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y191": { + "bits": {}, + "grid_x": 53, + "grid_y": 9, + "segment": "SEG_CLBLL_R_X19Y191", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y191": "SLICEL", + "SLICE_X27Y191": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y192": { + "bits": {}, + "grid_x": 53, + "grid_y": 8, + "segment": "SEG_CLBLL_R_X19Y192", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y192": "SLICEL", + "SLICE_X27Y192": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y193": { + "bits": {}, + "grid_x": 53, + "grid_y": 7, + "segment": "SEG_CLBLL_R_X19Y193", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y193": "SLICEL", + "SLICE_X27Y193": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y194": { + "bits": {}, + "grid_x": 53, + "grid_y": 6, + "segment": "SEG_CLBLL_R_X19Y194", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y194": "SLICEL", + "SLICE_X27Y194": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y195": { + "bits": {}, + "grid_x": 53, + "grid_y": 5, + "segment": "SEG_CLBLL_R_X19Y195", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y195": "SLICEL", + "SLICE_X27Y195": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y196": { + "bits": {}, + "grid_x": 53, + "grid_y": 4, + "segment": "SEG_CLBLL_R_X19Y196", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y196": "SLICEL", + "SLICE_X27Y196": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y197": { + "bits": {}, + "grid_x": 53, + "grid_y": 3, + "segment": "SEG_CLBLL_R_X19Y197", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y197": "SLICEL", + "SLICE_X27Y197": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y198": { + "bits": {}, + "grid_x": 53, + "grid_y": 2, + "segment": "SEG_CLBLL_R_X19Y198", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y198": "SLICEL", + "SLICE_X27Y198": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y199": { + "bits": {}, + "grid_x": 53, + "grid_y": 1, + "segment": "SEG_CLBLL_R_X19Y199", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y199": "SLICEL", + "SLICE_X27Y199": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y2": { + "bits": {}, + "grid_x": 53, + "grid_y": 205, + "segment": "SEG_CLBLL_R_X19Y2", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y2": "SLICEL", + "SLICE_X27Y2": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y20": { + "bits": {}, + "grid_x": 53, + "grid_y": 187, + "segment": "SEG_CLBLL_R_X19Y20", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y20": "SLICEL", + "SLICE_X27Y20": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y21": { + "bits": {}, + "grid_x": 53, + "grid_y": 186, + "segment": "SEG_CLBLL_R_X19Y21", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y21": "SLICEL", + "SLICE_X27Y21": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y22": { + "bits": {}, + "grid_x": 53, + "grid_y": 185, + "segment": "SEG_CLBLL_R_X19Y22", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y22": "SLICEL", + "SLICE_X27Y22": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y23": { + "bits": {}, + "grid_x": 53, + "grid_y": 184, + "segment": "SEG_CLBLL_R_X19Y23", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y23": "SLICEL", + "SLICE_X27Y23": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y24": { + "bits": {}, + "grid_x": 53, + "grid_y": 183, + "segment": "SEG_CLBLL_R_X19Y24", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y24": "SLICEL", + "SLICE_X27Y24": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y25": { + "bits": {}, + "grid_x": 53, + "grid_y": 181, + "segment": "SEG_CLBLL_R_X19Y25", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y25": "SLICEL", + "SLICE_X27Y25": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y26": { + "bits": {}, + "grid_x": 53, + "grid_y": 180, + "segment": "SEG_CLBLL_R_X19Y26", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y26": "SLICEL", + "SLICE_X27Y26": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y27": { + "bits": {}, + "grid_x": 53, + "grid_y": 179, + "segment": "SEG_CLBLL_R_X19Y27", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y27": "SLICEL", + "SLICE_X27Y27": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y28": { + "bits": {}, + "grid_x": 53, + "grid_y": 178, + "segment": "SEG_CLBLL_R_X19Y28", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y28": "SLICEL", + "SLICE_X27Y28": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y29": { + "bits": {}, + "grid_x": 53, + "grid_y": 177, + "segment": "SEG_CLBLL_R_X19Y29", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y29": "SLICEL", + "SLICE_X27Y29": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y3": { + "bits": {}, + "grid_x": 53, + "grid_y": 204, + "segment": "SEG_CLBLL_R_X19Y3", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y3": "SLICEL", + "SLICE_X27Y3": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y30": { + "bits": {}, + "grid_x": 53, + "grid_y": 176, + "segment": "SEG_CLBLL_R_X19Y30", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y30": "SLICEL", + "SLICE_X27Y30": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y31": { + "bits": {}, + "grid_x": 53, + "grid_y": 175, + "segment": "SEG_CLBLL_R_X19Y31", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y31": "SLICEL", + "SLICE_X27Y31": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y32": { + "bits": {}, + "grid_x": 53, + "grid_y": 174, + "segment": "SEG_CLBLL_R_X19Y32", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y32": "SLICEL", + "SLICE_X27Y32": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y33": { + "bits": {}, + "grid_x": 53, + "grid_y": 173, + "segment": "SEG_CLBLL_R_X19Y33", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y33": "SLICEL", + "SLICE_X27Y33": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y34": { + "bits": {}, + "grid_x": 53, + "grid_y": 172, + "segment": "SEG_CLBLL_R_X19Y34", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y34": "SLICEL", + "SLICE_X27Y34": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y35": { + "bits": {}, + "grid_x": 53, + "grid_y": 171, + "segment": "SEG_CLBLL_R_X19Y35", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y35": "SLICEL", + "SLICE_X27Y35": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y36": { + "bits": {}, + "grid_x": 53, + "grid_y": 170, + "segment": "SEG_CLBLL_R_X19Y36", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y36": "SLICEL", + "SLICE_X27Y36": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y37": { + "bits": {}, + "grid_x": 53, + "grid_y": 169, + "segment": "SEG_CLBLL_R_X19Y37", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y37": "SLICEL", + "SLICE_X27Y37": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y38": { + "bits": {}, + "grid_x": 53, + "grid_y": 168, + "segment": "SEG_CLBLL_R_X19Y38", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y38": "SLICEL", + "SLICE_X27Y38": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y39": { + "bits": {}, + "grid_x": 53, + "grid_y": 167, + "segment": "SEG_CLBLL_R_X19Y39", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y39": "SLICEL", + "SLICE_X27Y39": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y4": { + "bits": {}, + "grid_x": 53, + "grid_y": 203, + "segment": "SEG_CLBLL_R_X19Y4", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y4": "SLICEL", + "SLICE_X27Y4": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y40": { + "bits": {}, + "grid_x": 53, + "grid_y": 166, + "segment": "SEG_CLBLL_R_X19Y40", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y40": "SLICEL", + "SLICE_X27Y40": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y41": { + "bits": {}, + "grid_x": 53, + "grid_y": 165, + "segment": "SEG_CLBLL_R_X19Y41", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y41": "SLICEL", + "SLICE_X27Y41": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y42": { + "bits": {}, + "grid_x": 53, + "grid_y": 164, + "segment": "SEG_CLBLL_R_X19Y42", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y42": "SLICEL", + "SLICE_X27Y42": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y43": { + "bits": {}, + "grid_x": 53, + "grid_y": 163, + "segment": "SEG_CLBLL_R_X19Y43", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y43": "SLICEL", + "SLICE_X27Y43": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y44": { + "bits": {}, + "grid_x": 53, + "grid_y": 162, + "segment": "SEG_CLBLL_R_X19Y44", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y44": "SLICEL", + "SLICE_X27Y44": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y45": { + "bits": {}, + "grid_x": 53, + "grid_y": 161, + "segment": "SEG_CLBLL_R_X19Y45", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y45": "SLICEL", + "SLICE_X27Y45": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y46": { + "bits": {}, + "grid_x": 53, + "grid_y": 160, + "segment": "SEG_CLBLL_R_X19Y46", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y46": "SLICEL", + "SLICE_X27Y46": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y47": { + "bits": {}, + "grid_x": 53, + "grid_y": 159, + "segment": "SEG_CLBLL_R_X19Y47", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y47": "SLICEL", + "SLICE_X27Y47": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y48": { + "bits": {}, + "grid_x": 53, + "grid_y": 158, + "segment": "SEG_CLBLL_R_X19Y48", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y48": "SLICEL", + "SLICE_X27Y48": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y49": { + "bits": {}, + "grid_x": 53, + "grid_y": 157, + "segment": "SEG_CLBLL_R_X19Y49", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y49": "SLICEL", + "SLICE_X27Y49": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y5": { + "bits": {}, + "grid_x": 53, + "grid_y": 202, + "segment": "SEG_CLBLL_R_X19Y5", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y5": "SLICEL", + "SLICE_X27Y5": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y6": { + "bits": {}, + "grid_x": 53, + "grid_y": 201, + "segment": "SEG_CLBLL_R_X19Y6", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y6": "SLICEL", + "SLICE_X27Y6": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y7": { + "bits": {}, + "grid_x": 53, + "grid_y": 200, + "segment": "SEG_CLBLL_R_X19Y7", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y7": "SLICEL", + "SLICE_X27Y7": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y8": { + "bits": {}, + "grid_x": 53, + "grid_y": 199, + "segment": "SEG_CLBLL_R_X19Y8", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y8": "SLICEL", + "SLICE_X27Y8": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X19Y9": { + "bits": {}, + "grid_x": 53, + "grid_y": 198, + "segment": "SEG_CLBLL_R_X19Y9", + "segment_type": "clbll_r", + "sites": { + "SLICE_X26Y9": "SLICEL", + "SLICE_X27Y9": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y0": { + "bits": {}, + "grid_x": 57, + "grid_y": 207, + "segment": "SEG_CLBLL_R_X21Y0", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y0": "SLICEL", + "SLICE_X31Y0": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y1": { + "bits": {}, + "grid_x": 57, + "grid_y": 206, + "segment": "SEG_CLBLL_R_X21Y1", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y1": "SLICEL", + "SLICE_X31Y1": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y10": { + "bits": {}, + "grid_x": 57, + "grid_y": 197, + "segment": "SEG_CLBLL_R_X21Y10", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y10": "SLICEL", + "SLICE_X31Y10": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y11": { + "bits": {}, + "grid_x": 57, + "grid_y": 196, + "segment": "SEG_CLBLL_R_X21Y11", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y11": "SLICEL", + "SLICE_X31Y11": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y12": { + "bits": {}, + "grid_x": 57, + "grid_y": 195, + "segment": "SEG_CLBLL_R_X21Y12", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y12": "SLICEL", + "SLICE_X31Y12": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y13": { + "bits": {}, + "grid_x": 57, + "grid_y": 194, + "segment": "SEG_CLBLL_R_X21Y13", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y13": "SLICEL", + "SLICE_X31Y13": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y14": { + "bits": {}, + "grid_x": 57, + "grid_y": 193, + "segment": "SEG_CLBLL_R_X21Y14", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y14": "SLICEL", + "SLICE_X31Y14": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y15": { + "bits": {}, + "grid_x": 57, + "grid_y": 192, + "segment": "SEG_CLBLL_R_X21Y15", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y15": "SLICEL", + "SLICE_X31Y15": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y150": { + "bits": {}, + "grid_x": 57, + "grid_y": 51, + "segment": "SEG_CLBLL_R_X21Y150", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y150": "SLICEL", + "SLICE_X31Y150": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y151": { + "bits": {}, + "grid_x": 57, + "grid_y": 50, + "segment": "SEG_CLBLL_R_X21Y151", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y151": "SLICEL", + "SLICE_X31Y151": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y152": { + "bits": {}, + "grid_x": 57, + "grid_y": 49, + "segment": "SEG_CLBLL_R_X21Y152", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y152": "SLICEL", + "SLICE_X31Y152": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y153": { + "bits": {}, + "grid_x": 57, + "grid_y": 48, + "segment": "SEG_CLBLL_R_X21Y153", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y153": "SLICEL", + "SLICE_X31Y153": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y154": { + "bits": {}, + "grid_x": 57, + "grid_y": 47, + "segment": "SEG_CLBLL_R_X21Y154", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y154": "SLICEL", + "SLICE_X31Y154": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y155": { + "bits": {}, + "grid_x": 57, + "grid_y": 46, + "segment": "SEG_CLBLL_R_X21Y155", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y155": "SLICEL", + "SLICE_X31Y155": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y156": { + "bits": {}, + "grid_x": 57, + "grid_y": 45, + "segment": "SEG_CLBLL_R_X21Y156", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y156": "SLICEL", + "SLICE_X31Y156": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y157": { + "bits": {}, + "grid_x": 57, + "grid_y": 44, + "segment": "SEG_CLBLL_R_X21Y157", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y157": "SLICEL", + "SLICE_X31Y157": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y158": { + "bits": {}, + "grid_x": 57, + "grid_y": 43, + "segment": "SEG_CLBLL_R_X21Y158", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y158": "SLICEL", + "SLICE_X31Y158": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y159": { + "bits": {}, + "grid_x": 57, + "grid_y": 42, + "segment": "SEG_CLBLL_R_X21Y159", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y159": "SLICEL", + "SLICE_X31Y159": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y16": { + "bits": {}, + "grid_x": 57, + "grid_y": 191, + "segment": "SEG_CLBLL_R_X21Y16", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y16": "SLICEL", + "SLICE_X31Y16": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y160": { + "bits": {}, + "grid_x": 57, + "grid_y": 41, + "segment": "SEG_CLBLL_R_X21Y160", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y160": "SLICEL", + "SLICE_X31Y160": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y161": { + "bits": {}, + "grid_x": 57, + "grid_y": 40, + "segment": "SEG_CLBLL_R_X21Y161", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y161": "SLICEL", + "SLICE_X31Y161": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y162": { + "bits": {}, + "grid_x": 57, + "grid_y": 39, + "segment": "SEG_CLBLL_R_X21Y162", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y162": "SLICEL", + "SLICE_X31Y162": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y163": { + "bits": {}, + "grid_x": 57, + "grid_y": 38, + "segment": "SEG_CLBLL_R_X21Y163", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y163": "SLICEL", + "SLICE_X31Y163": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y164": { + "bits": {}, + "grid_x": 57, + "grid_y": 37, + "segment": "SEG_CLBLL_R_X21Y164", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y164": "SLICEL", + "SLICE_X31Y164": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y165": { + "bits": {}, + "grid_x": 57, + "grid_y": 36, + "segment": "SEG_CLBLL_R_X21Y165", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y165": "SLICEL", + "SLICE_X31Y165": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y166": { + "bits": {}, + "grid_x": 57, + "grid_y": 35, + "segment": "SEG_CLBLL_R_X21Y166", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y166": "SLICEL", + "SLICE_X31Y166": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y167": { + "bits": {}, + "grid_x": 57, + "grid_y": 34, + "segment": "SEG_CLBLL_R_X21Y167", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y167": "SLICEL", + "SLICE_X31Y167": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y168": { + "bits": {}, + "grid_x": 57, + "grid_y": 33, + "segment": "SEG_CLBLL_R_X21Y168", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y168": "SLICEL", + "SLICE_X31Y168": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y169": { + "bits": {}, + "grid_x": 57, + "grid_y": 32, + "segment": "SEG_CLBLL_R_X21Y169", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y169": "SLICEL", + "SLICE_X31Y169": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y17": { + "bits": {}, + "grid_x": 57, + "grid_y": 190, + "segment": "SEG_CLBLL_R_X21Y17", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y17": "SLICEL", + "SLICE_X31Y17": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y170": { + "bits": {}, + "grid_x": 57, + "grid_y": 31, + "segment": "SEG_CLBLL_R_X21Y170", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y170": "SLICEL", + "SLICE_X31Y170": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y171": { + "bits": {}, + "grid_x": 57, + "grid_y": 30, + "segment": "SEG_CLBLL_R_X21Y171", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y171": "SLICEL", + "SLICE_X31Y171": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y172": { + "bits": {}, + "grid_x": 57, + "grid_y": 29, + "segment": "SEG_CLBLL_R_X21Y172", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y172": "SLICEL", + "SLICE_X31Y172": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y173": { + "bits": {}, + "grid_x": 57, + "grid_y": 28, + "segment": "SEG_CLBLL_R_X21Y173", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y173": "SLICEL", + "SLICE_X31Y173": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y174": { + "bits": {}, + "grid_x": 57, + "grid_y": 27, + "segment": "SEG_CLBLL_R_X21Y174", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y174": "SLICEL", + "SLICE_X31Y174": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y175": { + "bits": {}, + "grid_x": 57, + "grid_y": 25, + "segment": "SEG_CLBLL_R_X21Y175", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y175": "SLICEL", + "SLICE_X31Y175": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y176": { + "bits": {}, + "grid_x": 57, + "grid_y": 24, + "segment": "SEG_CLBLL_R_X21Y176", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y176": "SLICEL", + "SLICE_X31Y176": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y177": { + "bits": {}, + "grid_x": 57, + "grid_y": 23, + "segment": "SEG_CLBLL_R_X21Y177", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y177": "SLICEL", + "SLICE_X31Y177": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y178": { + "bits": {}, + "grid_x": 57, + "grid_y": 22, + "segment": "SEG_CLBLL_R_X21Y178", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y178": "SLICEL", + "SLICE_X31Y178": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y179": { + "bits": {}, + "grid_x": 57, + "grid_y": 21, + "segment": "SEG_CLBLL_R_X21Y179", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y179": "SLICEL", + "SLICE_X31Y179": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y18": { + "bits": {}, + "grid_x": 57, + "grid_y": 189, + "segment": "SEG_CLBLL_R_X21Y18", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y18": "SLICEL", + "SLICE_X31Y18": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y180": { + "bits": {}, + "grid_x": 57, + "grid_y": 20, + "segment": "SEG_CLBLL_R_X21Y180", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y180": "SLICEL", + "SLICE_X31Y180": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y181": { + "bits": {}, + "grid_x": 57, + "grid_y": 19, + "segment": "SEG_CLBLL_R_X21Y181", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y181": "SLICEL", + "SLICE_X31Y181": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y182": { + "bits": {}, + "grid_x": 57, + "grid_y": 18, + "segment": "SEG_CLBLL_R_X21Y182", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y182": "SLICEL", + "SLICE_X31Y182": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y183": { + "bits": {}, + "grid_x": 57, + "grid_y": 17, + "segment": "SEG_CLBLL_R_X21Y183", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y183": "SLICEL", + "SLICE_X31Y183": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y184": { + "bits": {}, + "grid_x": 57, + "grid_y": 16, + "segment": "SEG_CLBLL_R_X21Y184", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y184": "SLICEL", + "SLICE_X31Y184": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y185": { + "bits": {}, + "grid_x": 57, + "grid_y": 15, + "segment": "SEG_CLBLL_R_X21Y185", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y185": "SLICEL", + "SLICE_X31Y185": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y186": { + "bits": {}, + "grid_x": 57, + "grid_y": 14, + "segment": "SEG_CLBLL_R_X21Y186", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y186": "SLICEL", + "SLICE_X31Y186": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y187": { + "bits": {}, + "grid_x": 57, + "grid_y": 13, + "segment": "SEG_CLBLL_R_X21Y187", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y187": "SLICEL", + "SLICE_X31Y187": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y188": { + "bits": {}, + "grid_x": 57, + "grid_y": 12, + "segment": "SEG_CLBLL_R_X21Y188", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y188": "SLICEL", + "SLICE_X31Y188": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y189": { + "bits": {}, + "grid_x": 57, + "grid_y": 11, + "segment": "SEG_CLBLL_R_X21Y189", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y189": "SLICEL", + "SLICE_X31Y189": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y19": { + "bits": {}, + "grid_x": 57, + "grid_y": 188, + "segment": "SEG_CLBLL_R_X21Y19", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y19": "SLICEL", + "SLICE_X31Y19": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y190": { + "bits": {}, + "grid_x": 57, + "grid_y": 10, + "segment": "SEG_CLBLL_R_X21Y190", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y190": "SLICEL", + "SLICE_X31Y190": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y191": { + "bits": {}, + "grid_x": 57, + "grid_y": 9, + "segment": "SEG_CLBLL_R_X21Y191", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y191": "SLICEL", + "SLICE_X31Y191": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y192": { + "bits": {}, + "grid_x": 57, + "grid_y": 8, + "segment": "SEG_CLBLL_R_X21Y192", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y192": "SLICEL", + "SLICE_X31Y192": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y193": { + "bits": {}, + "grid_x": 57, + "grid_y": 7, + "segment": "SEG_CLBLL_R_X21Y193", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y193": "SLICEL", + "SLICE_X31Y193": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y194": { + "bits": {}, + "grid_x": 57, + "grid_y": 6, + "segment": "SEG_CLBLL_R_X21Y194", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y194": "SLICEL", + "SLICE_X31Y194": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y195": { + "bits": {}, + "grid_x": 57, + "grid_y": 5, + "segment": "SEG_CLBLL_R_X21Y195", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y195": "SLICEL", + "SLICE_X31Y195": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y196": { + "bits": {}, + "grid_x": 57, + "grid_y": 4, + "segment": "SEG_CLBLL_R_X21Y196", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y196": "SLICEL", + "SLICE_X31Y196": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y197": { + "bits": {}, + "grid_x": 57, + "grid_y": 3, + "segment": "SEG_CLBLL_R_X21Y197", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y197": "SLICEL", + "SLICE_X31Y197": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y198": { + "bits": {}, + "grid_x": 57, + "grid_y": 2, + "segment": "SEG_CLBLL_R_X21Y198", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y198": "SLICEL", + "SLICE_X31Y198": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y199": { + "bits": {}, + "grid_x": 57, + "grid_y": 1, + "segment": "SEG_CLBLL_R_X21Y199", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y199": "SLICEL", + "SLICE_X31Y199": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y2": { + "bits": {}, + "grid_x": 57, + "grid_y": 205, + "segment": "SEG_CLBLL_R_X21Y2", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y2": "SLICEL", + "SLICE_X31Y2": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y20": { + "bits": {}, + "grid_x": 57, + "grid_y": 187, + "segment": "SEG_CLBLL_R_X21Y20", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y20": "SLICEL", + "SLICE_X31Y20": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y21": { + "bits": {}, + "grid_x": 57, + "grid_y": 186, + "segment": "SEG_CLBLL_R_X21Y21", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y21": "SLICEL", + "SLICE_X31Y21": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y22": { + "bits": {}, + "grid_x": 57, + "grid_y": 185, + "segment": "SEG_CLBLL_R_X21Y22", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y22": "SLICEL", + "SLICE_X31Y22": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y23": { + "bits": {}, + "grid_x": 57, + "grid_y": 184, + "segment": "SEG_CLBLL_R_X21Y23", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y23": "SLICEL", + "SLICE_X31Y23": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y24": { + "bits": {}, + "grid_x": 57, + "grid_y": 183, + "segment": "SEG_CLBLL_R_X21Y24", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y24": "SLICEL", + "SLICE_X31Y24": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y25": { + "bits": {}, + "grid_x": 57, + "grid_y": 181, + "segment": "SEG_CLBLL_R_X21Y25", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y25": "SLICEL", + "SLICE_X31Y25": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y26": { + "bits": {}, + "grid_x": 57, + "grid_y": 180, + "segment": "SEG_CLBLL_R_X21Y26", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y26": "SLICEL", + "SLICE_X31Y26": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y27": { + "bits": {}, + "grid_x": 57, + "grid_y": 179, + "segment": "SEG_CLBLL_R_X21Y27", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y27": "SLICEL", + "SLICE_X31Y27": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y28": { + "bits": {}, + "grid_x": 57, + "grid_y": 178, + "segment": "SEG_CLBLL_R_X21Y28", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y28": "SLICEL", + "SLICE_X31Y28": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y29": { + "bits": {}, + "grid_x": 57, + "grid_y": 177, + "segment": "SEG_CLBLL_R_X21Y29", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y29": "SLICEL", + "SLICE_X31Y29": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y3": { + "bits": {}, + "grid_x": 57, + "grid_y": 204, + "segment": "SEG_CLBLL_R_X21Y3", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y3": "SLICEL", + "SLICE_X31Y3": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y30": { + "bits": {}, + "grid_x": 57, + "grid_y": 176, + "segment": "SEG_CLBLL_R_X21Y30", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y30": "SLICEL", + "SLICE_X31Y30": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y31": { + "bits": {}, + "grid_x": 57, + "grid_y": 175, + "segment": "SEG_CLBLL_R_X21Y31", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y31": "SLICEL", + "SLICE_X31Y31": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y32": { + "bits": {}, + "grid_x": 57, + "grid_y": 174, + "segment": "SEG_CLBLL_R_X21Y32", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y32": "SLICEL", + "SLICE_X31Y32": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y33": { + "bits": {}, + "grid_x": 57, + "grid_y": 173, + "segment": "SEG_CLBLL_R_X21Y33", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y33": "SLICEL", + "SLICE_X31Y33": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y34": { + "bits": {}, + "grid_x": 57, + "grid_y": 172, + "segment": "SEG_CLBLL_R_X21Y34", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y34": "SLICEL", + "SLICE_X31Y34": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y35": { + "bits": {}, + "grid_x": 57, + "grid_y": 171, + "segment": "SEG_CLBLL_R_X21Y35", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y35": "SLICEL", + "SLICE_X31Y35": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y36": { + "bits": {}, + "grid_x": 57, + "grid_y": 170, + "segment": "SEG_CLBLL_R_X21Y36", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y36": "SLICEL", + "SLICE_X31Y36": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y37": { + "bits": {}, + "grid_x": 57, + "grid_y": 169, + "segment": "SEG_CLBLL_R_X21Y37", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y37": "SLICEL", + "SLICE_X31Y37": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y38": { + "bits": {}, + "grid_x": 57, + "grid_y": 168, + "segment": "SEG_CLBLL_R_X21Y38", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y38": "SLICEL", + "SLICE_X31Y38": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y39": { + "bits": {}, + "grid_x": 57, + "grid_y": 167, + "segment": "SEG_CLBLL_R_X21Y39", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y39": "SLICEL", + "SLICE_X31Y39": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y4": { + "bits": {}, + "grid_x": 57, + "grid_y": 203, + "segment": "SEG_CLBLL_R_X21Y4", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y4": "SLICEL", + "SLICE_X31Y4": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y40": { + "bits": {}, + "grid_x": 57, + "grid_y": 166, + "segment": "SEG_CLBLL_R_X21Y40", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y40": "SLICEL", + "SLICE_X31Y40": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y41": { + "bits": {}, + "grid_x": 57, + "grid_y": 165, + "segment": "SEG_CLBLL_R_X21Y41", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y41": "SLICEL", + "SLICE_X31Y41": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y42": { + "bits": {}, + "grid_x": 57, + "grid_y": 164, + "segment": "SEG_CLBLL_R_X21Y42", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y42": "SLICEL", + "SLICE_X31Y42": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y43": { + "bits": {}, + "grid_x": 57, + "grid_y": 163, + "segment": "SEG_CLBLL_R_X21Y43", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y43": "SLICEL", + "SLICE_X31Y43": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y44": { + "bits": {}, + "grid_x": 57, + "grid_y": 162, + "segment": "SEG_CLBLL_R_X21Y44", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y44": "SLICEL", + "SLICE_X31Y44": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y45": { + "bits": {}, + "grid_x": 57, + "grid_y": 161, + "segment": "SEG_CLBLL_R_X21Y45", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y45": "SLICEL", + "SLICE_X31Y45": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y46": { + "bits": {}, + "grid_x": 57, + "grid_y": 160, + "segment": "SEG_CLBLL_R_X21Y46", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y46": "SLICEL", + "SLICE_X31Y46": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y47": { + "bits": {}, + "grid_x": 57, + "grid_y": 159, + "segment": "SEG_CLBLL_R_X21Y47", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y47": "SLICEL", + "SLICE_X31Y47": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y48": { + "bits": {}, + "grid_x": 57, + "grid_y": 158, + "segment": "SEG_CLBLL_R_X21Y48", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y48": "SLICEL", + "SLICE_X31Y48": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y49": { + "bits": {}, + "grid_x": 57, + "grid_y": 157, + "segment": "SEG_CLBLL_R_X21Y49", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y49": "SLICEL", + "SLICE_X31Y49": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y5": { + "bits": {}, + "grid_x": 57, + "grid_y": 202, + "segment": "SEG_CLBLL_R_X21Y5", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y5": "SLICEL", + "SLICE_X31Y5": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y6": { + "bits": {}, + "grid_x": 57, + "grid_y": 201, + "segment": "SEG_CLBLL_R_X21Y6", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y6": "SLICEL", + "SLICE_X31Y6": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y7": { + "bits": {}, + "grid_x": 57, + "grid_y": 200, + "segment": "SEG_CLBLL_R_X21Y7", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y7": "SLICEL", + "SLICE_X31Y7": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y8": { + "bits": {}, + "grid_x": 57, + "grid_y": 199, + "segment": "SEG_CLBLL_R_X21Y8", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y8": "SLICEL", + "SLICE_X31Y8": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X21Y9": { + "bits": {}, + "grid_x": 57, + "grid_y": 198, + "segment": "SEG_CLBLL_R_X21Y9", + "segment_type": "clbll_r", + "sites": { + "SLICE_X30Y9": "SLICEL", + "SLICE_X31Y9": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y0": { + "bits": {}, + "grid_x": 61, + "grid_y": 207, + "segment": "SEG_CLBLL_R_X23Y0", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y0": "SLICEL", + "SLICE_X35Y0": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y1": { + "bits": {}, + "grid_x": 61, + "grid_y": 206, + "segment": "SEG_CLBLL_R_X23Y1", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y1": "SLICEL", + "SLICE_X35Y1": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y10": { + "bits": {}, + "grid_x": 61, + "grid_y": 197, + "segment": "SEG_CLBLL_R_X23Y10", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y10": "SLICEL", + "SLICE_X35Y10": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y11": { + "bits": {}, + "grid_x": 61, + "grid_y": 196, + "segment": "SEG_CLBLL_R_X23Y11", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y11": "SLICEL", + "SLICE_X35Y11": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y12": { + "bits": {}, + "grid_x": 61, + "grid_y": 195, + "segment": "SEG_CLBLL_R_X23Y12", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y12": "SLICEL", + "SLICE_X35Y12": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y13": { + "bits": {}, + "grid_x": 61, + "grid_y": 194, + "segment": "SEG_CLBLL_R_X23Y13", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y13": "SLICEL", + "SLICE_X35Y13": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y14": { + "bits": {}, + "grid_x": 61, + "grid_y": 193, + "segment": "SEG_CLBLL_R_X23Y14", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y14": "SLICEL", + "SLICE_X35Y14": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y15": { + "bits": {}, + "grid_x": 61, + "grid_y": 192, + "segment": "SEG_CLBLL_R_X23Y15", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y15": "SLICEL", + "SLICE_X35Y15": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y150": { + "bits": {}, + "grid_x": 61, + "grid_y": 51, + "segment": "SEG_CLBLL_R_X23Y150", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y150": "SLICEL", + "SLICE_X35Y150": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y151": { + "bits": {}, + "grid_x": 61, + "grid_y": 50, + "segment": "SEG_CLBLL_R_X23Y151", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y151": "SLICEL", + "SLICE_X35Y151": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y152": { + "bits": {}, + "grid_x": 61, + "grid_y": 49, + "segment": "SEG_CLBLL_R_X23Y152", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y152": "SLICEL", + "SLICE_X35Y152": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y153": { + "bits": {}, + "grid_x": 61, + "grid_y": 48, + "segment": "SEG_CLBLL_R_X23Y153", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y153": "SLICEL", + "SLICE_X35Y153": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y154": { + "bits": {}, + "grid_x": 61, + "grid_y": 47, + "segment": "SEG_CLBLL_R_X23Y154", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y154": "SLICEL", + "SLICE_X35Y154": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y155": { + "bits": {}, + "grid_x": 61, + "grid_y": 46, + "segment": "SEG_CLBLL_R_X23Y155", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y155": "SLICEL", + "SLICE_X35Y155": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y156": { + "bits": {}, + "grid_x": 61, + "grid_y": 45, + "segment": "SEG_CLBLL_R_X23Y156", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y156": "SLICEL", + "SLICE_X35Y156": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y157": { + "bits": {}, + "grid_x": 61, + "grid_y": 44, + "segment": "SEG_CLBLL_R_X23Y157", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y157": "SLICEL", + "SLICE_X35Y157": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y158": { + "bits": {}, + "grid_x": 61, + "grid_y": 43, + "segment": "SEG_CLBLL_R_X23Y158", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y158": "SLICEL", + "SLICE_X35Y158": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y159": { + "bits": {}, + "grid_x": 61, + "grid_y": 42, + "segment": "SEG_CLBLL_R_X23Y159", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y159": "SLICEL", + "SLICE_X35Y159": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y16": { + "bits": {}, + "grid_x": 61, + "grid_y": 191, + "segment": "SEG_CLBLL_R_X23Y16", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y16": "SLICEL", + "SLICE_X35Y16": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y160": { + "bits": {}, + "grid_x": 61, + "grid_y": 41, + "segment": "SEG_CLBLL_R_X23Y160", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y160": "SLICEL", + "SLICE_X35Y160": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y161": { + "bits": {}, + "grid_x": 61, + "grid_y": 40, + "segment": "SEG_CLBLL_R_X23Y161", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y161": "SLICEL", + "SLICE_X35Y161": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y162": { + "bits": {}, + "grid_x": 61, + "grid_y": 39, + "segment": "SEG_CLBLL_R_X23Y162", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y162": "SLICEL", + "SLICE_X35Y162": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y163": { + "bits": {}, + "grid_x": 61, + "grid_y": 38, + "segment": "SEG_CLBLL_R_X23Y163", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y163": "SLICEL", + "SLICE_X35Y163": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y164": { + "bits": {}, + "grid_x": 61, + "grid_y": 37, + "segment": "SEG_CLBLL_R_X23Y164", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y164": "SLICEL", + "SLICE_X35Y164": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y165": { + "bits": {}, + "grid_x": 61, + "grid_y": 36, + "segment": "SEG_CLBLL_R_X23Y165", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y165": "SLICEL", + "SLICE_X35Y165": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y166": { + "bits": {}, + "grid_x": 61, + "grid_y": 35, + "segment": "SEG_CLBLL_R_X23Y166", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y166": "SLICEL", + "SLICE_X35Y166": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y167": { + "bits": {}, + "grid_x": 61, + "grid_y": 34, + "segment": "SEG_CLBLL_R_X23Y167", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y167": "SLICEL", + "SLICE_X35Y167": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y168": { + "bits": {}, + "grid_x": 61, + "grid_y": 33, + "segment": "SEG_CLBLL_R_X23Y168", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y168": "SLICEL", + "SLICE_X35Y168": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y169": { + "bits": {}, + "grid_x": 61, + "grid_y": 32, + "segment": "SEG_CLBLL_R_X23Y169", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y169": "SLICEL", + "SLICE_X35Y169": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y17": { + "bits": {}, + "grid_x": 61, + "grid_y": 190, + "segment": "SEG_CLBLL_R_X23Y17", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y17": "SLICEL", + "SLICE_X35Y17": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y170": { + "bits": {}, + "grid_x": 61, + "grid_y": 31, + "segment": "SEG_CLBLL_R_X23Y170", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y170": "SLICEL", + "SLICE_X35Y170": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y171": { + "bits": {}, + "grid_x": 61, + "grid_y": 30, + "segment": "SEG_CLBLL_R_X23Y171", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y171": "SLICEL", + "SLICE_X35Y171": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y172": { + "bits": {}, + "grid_x": 61, + "grid_y": 29, + "segment": "SEG_CLBLL_R_X23Y172", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y172": "SLICEL", + "SLICE_X35Y172": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y173": { + "bits": {}, + "grid_x": 61, + "grid_y": 28, + "segment": "SEG_CLBLL_R_X23Y173", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y173": "SLICEL", + "SLICE_X35Y173": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y174": { + "bits": {}, + "grid_x": 61, + "grid_y": 27, + "segment": "SEG_CLBLL_R_X23Y174", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y174": "SLICEL", + "SLICE_X35Y174": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y175": { + "bits": {}, + "grid_x": 61, + "grid_y": 25, + "segment": "SEG_CLBLL_R_X23Y175", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y175": "SLICEL", + "SLICE_X35Y175": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y176": { + "bits": {}, + "grid_x": 61, + "grid_y": 24, + "segment": "SEG_CLBLL_R_X23Y176", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y176": "SLICEL", + "SLICE_X35Y176": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y177": { + "bits": {}, + "grid_x": 61, + "grid_y": 23, + "segment": "SEG_CLBLL_R_X23Y177", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y177": "SLICEL", + "SLICE_X35Y177": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y178": { + "bits": {}, + "grid_x": 61, + "grid_y": 22, + "segment": "SEG_CLBLL_R_X23Y178", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y178": "SLICEL", + "SLICE_X35Y178": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y179": { + "bits": {}, + "grid_x": 61, + "grid_y": 21, + "segment": "SEG_CLBLL_R_X23Y179", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y179": "SLICEL", + "SLICE_X35Y179": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y18": { + "bits": {}, + "grid_x": 61, + "grid_y": 189, + "segment": "SEG_CLBLL_R_X23Y18", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y18": "SLICEL", + "SLICE_X35Y18": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y180": { + "bits": {}, + "grid_x": 61, + "grid_y": 20, + "segment": "SEG_CLBLL_R_X23Y180", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y180": "SLICEL", + "SLICE_X35Y180": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y181": { + "bits": {}, + "grid_x": 61, + "grid_y": 19, + "segment": "SEG_CLBLL_R_X23Y181", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y181": "SLICEL", + "SLICE_X35Y181": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y182": { + "bits": {}, + "grid_x": 61, + "grid_y": 18, + "segment": "SEG_CLBLL_R_X23Y182", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y182": "SLICEL", + "SLICE_X35Y182": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y183": { + "bits": {}, + "grid_x": 61, + "grid_y": 17, + "segment": "SEG_CLBLL_R_X23Y183", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y183": "SLICEL", + "SLICE_X35Y183": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y184": { + "bits": {}, + "grid_x": 61, + "grid_y": 16, + "segment": "SEG_CLBLL_R_X23Y184", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y184": "SLICEL", + "SLICE_X35Y184": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y185": { + "bits": {}, + "grid_x": 61, + "grid_y": 15, + "segment": "SEG_CLBLL_R_X23Y185", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y185": "SLICEL", + "SLICE_X35Y185": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y186": { + "bits": {}, + "grid_x": 61, + "grid_y": 14, + "segment": "SEG_CLBLL_R_X23Y186", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y186": "SLICEL", + "SLICE_X35Y186": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y187": { + "bits": {}, + "grid_x": 61, + "grid_y": 13, + "segment": "SEG_CLBLL_R_X23Y187", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y187": "SLICEL", + "SLICE_X35Y187": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y188": { + "bits": {}, + "grid_x": 61, + "grid_y": 12, + "segment": "SEG_CLBLL_R_X23Y188", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y188": "SLICEL", + "SLICE_X35Y188": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y189": { + "bits": {}, + "grid_x": 61, + "grid_y": 11, + "segment": "SEG_CLBLL_R_X23Y189", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y189": "SLICEL", + "SLICE_X35Y189": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y19": { + "bits": {}, + "grid_x": 61, + "grid_y": 188, + "segment": "SEG_CLBLL_R_X23Y19", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y19": "SLICEL", + "SLICE_X35Y19": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y190": { + "bits": {}, + "grid_x": 61, + "grid_y": 10, + "segment": "SEG_CLBLL_R_X23Y190", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y190": "SLICEL", + "SLICE_X35Y190": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y191": { + "bits": {}, + "grid_x": 61, + "grid_y": 9, + "segment": "SEG_CLBLL_R_X23Y191", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y191": "SLICEL", + "SLICE_X35Y191": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y192": { + "bits": {}, + "grid_x": 61, + "grid_y": 8, + "segment": "SEG_CLBLL_R_X23Y192", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y192": "SLICEL", + "SLICE_X35Y192": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y193": { + "bits": {}, + "grid_x": 61, + "grid_y": 7, + "segment": "SEG_CLBLL_R_X23Y193", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y193": "SLICEL", + "SLICE_X35Y193": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y194": { + "bits": {}, + "grid_x": 61, + "grid_y": 6, + "segment": "SEG_CLBLL_R_X23Y194", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y194": "SLICEL", + "SLICE_X35Y194": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y195": { + "bits": {}, + "grid_x": 61, + "grid_y": 5, + "segment": "SEG_CLBLL_R_X23Y195", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y195": "SLICEL", + "SLICE_X35Y195": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y196": { + "bits": {}, + "grid_x": 61, + "grid_y": 4, + "segment": "SEG_CLBLL_R_X23Y196", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y196": "SLICEL", + "SLICE_X35Y196": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y197": { + "bits": {}, + "grid_x": 61, + "grid_y": 3, + "segment": "SEG_CLBLL_R_X23Y197", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y197": "SLICEL", + "SLICE_X35Y197": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y198": { + "bits": {}, + "grid_x": 61, + "grid_y": 2, + "segment": "SEG_CLBLL_R_X23Y198", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y198": "SLICEL", + "SLICE_X35Y198": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y199": { + "bits": {}, + "grid_x": 61, + "grid_y": 1, + "segment": "SEG_CLBLL_R_X23Y199", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y199": "SLICEL", + "SLICE_X35Y199": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y2": { + "bits": {}, + "grid_x": 61, + "grid_y": 205, + "segment": "SEG_CLBLL_R_X23Y2", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y2": "SLICEL", + "SLICE_X35Y2": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y20": { + "bits": {}, + "grid_x": 61, + "grid_y": 187, + "segment": "SEG_CLBLL_R_X23Y20", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y20": "SLICEL", + "SLICE_X35Y20": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y21": { + "bits": {}, + "grid_x": 61, + "grid_y": 186, + "segment": "SEG_CLBLL_R_X23Y21", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y21": "SLICEL", + "SLICE_X35Y21": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y22": { + "bits": {}, + "grid_x": 61, + "grid_y": 185, + "segment": "SEG_CLBLL_R_X23Y22", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y22": "SLICEL", + "SLICE_X35Y22": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y23": { + "bits": {}, + "grid_x": 61, + "grid_y": 184, + "segment": "SEG_CLBLL_R_X23Y23", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y23": "SLICEL", + "SLICE_X35Y23": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y24": { + "bits": {}, + "grid_x": 61, + "grid_y": 183, + "segment": "SEG_CLBLL_R_X23Y24", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y24": "SLICEL", + "SLICE_X35Y24": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y25": { + "bits": {}, + "grid_x": 61, + "grid_y": 181, + "segment": "SEG_CLBLL_R_X23Y25", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y25": "SLICEL", + "SLICE_X35Y25": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y26": { + "bits": {}, + "grid_x": 61, + "grid_y": 180, + "segment": "SEG_CLBLL_R_X23Y26", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y26": "SLICEL", + "SLICE_X35Y26": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y27": { + "bits": {}, + "grid_x": 61, + "grid_y": 179, + "segment": "SEG_CLBLL_R_X23Y27", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y27": "SLICEL", + "SLICE_X35Y27": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y28": { + "bits": {}, + "grid_x": 61, + "grid_y": 178, + "segment": "SEG_CLBLL_R_X23Y28", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y28": "SLICEL", + "SLICE_X35Y28": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y29": { + "bits": {}, + "grid_x": 61, + "grid_y": 177, + "segment": "SEG_CLBLL_R_X23Y29", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y29": "SLICEL", + "SLICE_X35Y29": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y3": { + "bits": {}, + "grid_x": 61, + "grid_y": 204, + "segment": "SEG_CLBLL_R_X23Y3", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y3": "SLICEL", + "SLICE_X35Y3": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y30": { + "bits": {}, + "grid_x": 61, + "grid_y": 176, + "segment": "SEG_CLBLL_R_X23Y30", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y30": "SLICEL", + "SLICE_X35Y30": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y31": { + "bits": {}, + "grid_x": 61, + "grid_y": 175, + "segment": "SEG_CLBLL_R_X23Y31", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y31": "SLICEL", + "SLICE_X35Y31": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y32": { + "bits": {}, + "grid_x": 61, + "grid_y": 174, + "segment": "SEG_CLBLL_R_X23Y32", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y32": "SLICEL", + "SLICE_X35Y32": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y33": { + "bits": {}, + "grid_x": 61, + "grid_y": 173, + "segment": "SEG_CLBLL_R_X23Y33", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y33": "SLICEL", + "SLICE_X35Y33": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y34": { + "bits": {}, + "grid_x": 61, + "grid_y": 172, + "segment": "SEG_CLBLL_R_X23Y34", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y34": "SLICEL", + "SLICE_X35Y34": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y35": { + "bits": {}, + "grid_x": 61, + "grid_y": 171, + "segment": "SEG_CLBLL_R_X23Y35", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y35": "SLICEL", + "SLICE_X35Y35": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y36": { + "bits": {}, + "grid_x": 61, + "grid_y": 170, + "segment": "SEG_CLBLL_R_X23Y36", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y36": "SLICEL", + "SLICE_X35Y36": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y37": { + "bits": {}, + "grid_x": 61, + "grid_y": 169, + "segment": "SEG_CLBLL_R_X23Y37", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y37": "SLICEL", + "SLICE_X35Y37": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y38": { + "bits": {}, + "grid_x": 61, + "grid_y": 168, + "segment": "SEG_CLBLL_R_X23Y38", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y38": "SLICEL", + "SLICE_X35Y38": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y39": { + "bits": {}, + "grid_x": 61, + "grid_y": 167, + "segment": "SEG_CLBLL_R_X23Y39", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y39": "SLICEL", + "SLICE_X35Y39": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y4": { + "bits": {}, + "grid_x": 61, + "grid_y": 203, + "segment": "SEG_CLBLL_R_X23Y4", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y4": "SLICEL", + "SLICE_X35Y4": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y40": { + "bits": {}, + "grid_x": 61, + "grid_y": 166, + "segment": "SEG_CLBLL_R_X23Y40", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y40": "SLICEL", + "SLICE_X35Y40": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y41": { + "bits": {}, + "grid_x": 61, + "grid_y": 165, + "segment": "SEG_CLBLL_R_X23Y41", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y41": "SLICEL", + "SLICE_X35Y41": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y42": { + "bits": {}, + "grid_x": 61, + "grid_y": 164, + "segment": "SEG_CLBLL_R_X23Y42", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y42": "SLICEL", + "SLICE_X35Y42": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y43": { + "bits": {}, + "grid_x": 61, + "grid_y": 163, + "segment": "SEG_CLBLL_R_X23Y43", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y43": "SLICEL", + "SLICE_X35Y43": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y44": { + "bits": {}, + "grid_x": 61, + "grid_y": 162, + "segment": "SEG_CLBLL_R_X23Y44", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y44": "SLICEL", + "SLICE_X35Y44": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y45": { + "bits": {}, + "grid_x": 61, + "grid_y": 161, + "segment": "SEG_CLBLL_R_X23Y45", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y45": "SLICEL", + "SLICE_X35Y45": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y46": { + "bits": {}, + "grid_x": 61, + "grid_y": 160, + "segment": "SEG_CLBLL_R_X23Y46", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y46": "SLICEL", + "SLICE_X35Y46": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y47": { + "bits": {}, + "grid_x": 61, + "grid_y": 159, + "segment": "SEG_CLBLL_R_X23Y47", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y47": "SLICEL", + "SLICE_X35Y47": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y48": { + "bits": {}, + "grid_x": 61, + "grid_y": 158, + "segment": "SEG_CLBLL_R_X23Y48", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y48": "SLICEL", + "SLICE_X35Y48": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y49": { + "bits": {}, + "grid_x": 61, + "grid_y": 157, + "segment": "SEG_CLBLL_R_X23Y49", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y49": "SLICEL", + "SLICE_X35Y49": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y5": { + "bits": {}, + "grid_x": 61, + "grid_y": 202, + "segment": "SEG_CLBLL_R_X23Y5", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y5": "SLICEL", + "SLICE_X35Y5": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y6": { + "bits": {}, + "grid_x": 61, + "grid_y": 201, + "segment": "SEG_CLBLL_R_X23Y6", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y6": "SLICEL", + "SLICE_X35Y6": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y7": { + "bits": {}, + "grid_x": 61, + "grid_y": 200, + "segment": "SEG_CLBLL_R_X23Y7", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y7": "SLICEL", + "SLICE_X35Y7": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y8": { + "bits": {}, + "grid_x": 61, + "grid_y": 199, + "segment": "SEG_CLBLL_R_X23Y8", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y8": "SLICEL", + "SLICE_X35Y8": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLL_R_X23Y9": { + "bits": {}, + "grid_x": 61, + "grid_y": 198, + "segment": "SEG_CLBLL_R_X23Y9", + "segment_type": "clbll_r", + "sites": { + "SLICE_X34Y9": "SLICEL", + "SLICE_X35Y9": "SLICEL" + }, + "type": "CLBLL_R" + }, + "CLBLM_L_X10Y0": { + "bits": {}, + "grid_x": 30, + "grid_y": 207, + "segment": "SEG_CLBLM_L_X10Y0", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y0": "SLICEM", + "SLICE_X13Y0": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y1": { + "bits": {}, + "grid_x": 30, + "grid_y": 206, + "segment": "SEG_CLBLM_L_X10Y1", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y1": "SLICEM", + "SLICE_X13Y1": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y10": { + "bits": {}, + "grid_x": 30, + "grid_y": 197, + "segment": "SEG_CLBLM_L_X10Y10", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y10": "SLICEM", + "SLICE_X13Y10": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y100": { + "bits": {}, + "grid_x": 30, + "grid_y": 103, + "segment": "SEG_CLBLM_L_X10Y100", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y100": "SLICEM", + "SLICE_X13Y100": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y101": { + "bits": {}, + "grid_x": 30, + "grid_y": 102, + "segment": "SEG_CLBLM_L_X10Y101", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y101": "SLICEM", + "SLICE_X13Y101": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y102": { + "bits": {}, + "grid_x": 30, + "grid_y": 101, + "segment": "SEG_CLBLM_L_X10Y102", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y102": "SLICEM", + "SLICE_X13Y102": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y103": { + "bits": {}, + "grid_x": 30, + "grid_y": 100, + "segment": "SEG_CLBLM_L_X10Y103", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y103": "SLICEM", + "SLICE_X13Y103": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y104": { + "bits": {}, + "grid_x": 30, + "grid_y": 99, + "segment": "SEG_CLBLM_L_X10Y104", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y104": "SLICEM", + "SLICE_X13Y104": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y105": { + "bits": {}, + "grid_x": 30, + "grid_y": 98, + "segment": "SEG_CLBLM_L_X10Y105", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y105": "SLICEM", + "SLICE_X13Y105": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y106": { + "bits": {}, + "grid_x": 30, + "grid_y": 97, + "segment": "SEG_CLBLM_L_X10Y106", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y106": "SLICEM", + "SLICE_X13Y106": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y107": { + "bits": {}, + "grid_x": 30, + "grid_y": 96, + "segment": "SEG_CLBLM_L_X10Y107", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y107": "SLICEM", + "SLICE_X13Y107": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y108": { + "bits": {}, + "grid_x": 30, + "grid_y": 95, + "segment": "SEG_CLBLM_L_X10Y108", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y108": "SLICEM", + "SLICE_X13Y108": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y109": { + "bits": {}, + "grid_x": 30, + "grid_y": 94, + "segment": "SEG_CLBLM_L_X10Y109", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y109": "SLICEM", + "SLICE_X13Y109": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y11": { + "bits": {}, + "grid_x": 30, + "grid_y": 196, + "segment": "SEG_CLBLM_L_X10Y11", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y11": "SLICEM", + "SLICE_X13Y11": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y110": { + "bits": {}, + "grid_x": 30, + "grid_y": 93, + "segment": "SEG_CLBLM_L_X10Y110", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y110": "SLICEM", + "SLICE_X13Y110": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y111": { + "bits": {}, + "grid_x": 30, + "grid_y": 92, + "segment": "SEG_CLBLM_L_X10Y111", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y111": "SLICEM", + "SLICE_X13Y111": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y112": { + "bits": {}, + "grid_x": 30, + "grid_y": 91, + "segment": "SEG_CLBLM_L_X10Y112", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y112": "SLICEM", + "SLICE_X13Y112": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y113": { + "bits": {}, + "grid_x": 30, + "grid_y": 90, + "segment": "SEG_CLBLM_L_X10Y113", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y113": "SLICEM", + "SLICE_X13Y113": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y114": { + "bits": {}, + "grid_x": 30, + "grid_y": 89, + "segment": "SEG_CLBLM_L_X10Y114", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y114": "SLICEM", + "SLICE_X13Y114": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y115": { + "bits": {}, + "grid_x": 30, + "grid_y": 88, + "segment": "SEG_CLBLM_L_X10Y115", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y115": "SLICEM", + "SLICE_X13Y115": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y116": { + "bits": {}, + "grid_x": 30, + "grid_y": 87, + "segment": "SEG_CLBLM_L_X10Y116", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y116": "SLICEM", + "SLICE_X13Y116": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y117": { + "bits": {}, + "grid_x": 30, + "grid_y": 86, + "segment": "SEG_CLBLM_L_X10Y117", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y117": "SLICEM", + "SLICE_X13Y117": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y118": { + "bits": {}, + "grid_x": 30, + "grid_y": 85, + "segment": "SEG_CLBLM_L_X10Y118", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y118": "SLICEM", + "SLICE_X13Y118": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y119": { + "bits": {}, + "grid_x": 30, + "grid_y": 84, + "segment": "SEG_CLBLM_L_X10Y119", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y119": "SLICEM", + "SLICE_X13Y119": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y12": { + "bits": {}, + "grid_x": 30, + "grid_y": 195, + "segment": "SEG_CLBLM_L_X10Y12", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y12": "SLICEM", + "SLICE_X13Y12": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y120": { + "bits": {}, + "grid_x": 30, + "grid_y": 83, + "segment": "SEG_CLBLM_L_X10Y120", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y120": "SLICEM", + "SLICE_X13Y120": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y121": { + "bits": {}, + "grid_x": 30, + "grid_y": 82, + "segment": "SEG_CLBLM_L_X10Y121", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y121": "SLICEM", + "SLICE_X13Y121": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y122": { + "bits": {}, + "grid_x": 30, + "grid_y": 81, + "segment": "SEG_CLBLM_L_X10Y122", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y122": "SLICEM", + "SLICE_X13Y122": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y123": { + "bits": {}, + "grid_x": 30, + "grid_y": 80, + "segment": "SEG_CLBLM_L_X10Y123", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y123": "SLICEM", + "SLICE_X13Y123": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y124": { + "bits": {}, + "grid_x": 30, + "grid_y": 79, + "segment": "SEG_CLBLM_L_X10Y124", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y124": "SLICEM", + "SLICE_X13Y124": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y125": { + "bits": {}, + "grid_x": 30, + "grid_y": 77, + "segment": "SEG_CLBLM_L_X10Y125", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y125": "SLICEM", + "SLICE_X13Y125": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y126": { + "bits": {}, + "grid_x": 30, + "grid_y": 76, + "segment": "SEG_CLBLM_L_X10Y126", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y126": "SLICEM", + "SLICE_X13Y126": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y127": { + "bits": {}, + "grid_x": 30, + "grid_y": 75, + "segment": "SEG_CLBLM_L_X10Y127", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y127": "SLICEM", + "SLICE_X13Y127": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y128": { + "bits": {}, + "grid_x": 30, + "grid_y": 74, + "segment": "SEG_CLBLM_L_X10Y128", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y128": "SLICEM", + "SLICE_X13Y128": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y129": { + "bits": {}, + "grid_x": 30, + "grid_y": 73, + "segment": "SEG_CLBLM_L_X10Y129", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y129": "SLICEM", + "SLICE_X13Y129": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y13": { + "bits": {}, + "grid_x": 30, + "grid_y": 194, + "segment": "SEG_CLBLM_L_X10Y13", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y13": "SLICEM", + "SLICE_X13Y13": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y130": { + "bits": {}, + "grid_x": 30, + "grid_y": 72, + "segment": "SEG_CLBLM_L_X10Y130", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y130": "SLICEM", + "SLICE_X13Y130": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y131": { + "bits": {}, + "grid_x": 30, + "grid_y": 71, + "segment": "SEG_CLBLM_L_X10Y131", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y131": "SLICEM", + "SLICE_X13Y131": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y132": { + "bits": {}, + "grid_x": 30, + "grid_y": 70, + "segment": "SEG_CLBLM_L_X10Y132", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y132": "SLICEM", + "SLICE_X13Y132": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y133": { + "bits": {}, + "grid_x": 30, + "grid_y": 69, + "segment": "SEG_CLBLM_L_X10Y133", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y133": "SLICEM", + "SLICE_X13Y133": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y134": { + "bits": {}, + "grid_x": 30, + "grid_y": 68, + "segment": "SEG_CLBLM_L_X10Y134", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y134": "SLICEM", + "SLICE_X13Y134": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y135": { + "bits": {}, + "grid_x": 30, + "grid_y": 67, + "segment": "SEG_CLBLM_L_X10Y135", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y135": "SLICEM", + "SLICE_X13Y135": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y136": { + "bits": {}, + "grid_x": 30, + "grid_y": 66, + "segment": "SEG_CLBLM_L_X10Y136", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y136": "SLICEM", + "SLICE_X13Y136": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y137": { + "bits": {}, + "grid_x": 30, + "grid_y": 65, + "segment": "SEG_CLBLM_L_X10Y137", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y137": "SLICEM", + "SLICE_X13Y137": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y138": { + "bits": {}, + "grid_x": 30, + "grid_y": 64, + "segment": "SEG_CLBLM_L_X10Y138", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y138": "SLICEM", + "SLICE_X13Y138": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y139": { + "bits": {}, + "grid_x": 30, + "grid_y": 63, + "segment": "SEG_CLBLM_L_X10Y139", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y139": "SLICEM", + "SLICE_X13Y139": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y14": { + "bits": {}, + "grid_x": 30, + "grid_y": 193, + "segment": "SEG_CLBLM_L_X10Y14", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y14": "SLICEM", + "SLICE_X13Y14": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y140": { + "bits": {}, + "grid_x": 30, + "grid_y": 62, + "segment": "SEG_CLBLM_L_X10Y140", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y140": "SLICEM", + "SLICE_X13Y140": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y141": { + "bits": {}, + "grid_x": 30, + "grid_y": 61, + "segment": "SEG_CLBLM_L_X10Y141", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y141": "SLICEM", + "SLICE_X13Y141": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y142": { + "bits": {}, + "grid_x": 30, + "grid_y": 60, + "segment": "SEG_CLBLM_L_X10Y142", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y142": "SLICEM", + "SLICE_X13Y142": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y143": { + "bits": {}, + "grid_x": 30, + "grid_y": 59, + "segment": "SEG_CLBLM_L_X10Y143", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y143": "SLICEM", + "SLICE_X13Y143": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y144": { + "bits": {}, + "grid_x": 30, + "grid_y": 58, + "segment": "SEG_CLBLM_L_X10Y144", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y144": "SLICEM", + "SLICE_X13Y144": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y145": { + "bits": {}, + "grid_x": 30, + "grid_y": 57, + "segment": "SEG_CLBLM_L_X10Y145", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y145": "SLICEM", + "SLICE_X13Y145": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y146": { + "bits": {}, + "grid_x": 30, + "grid_y": 56, + "segment": "SEG_CLBLM_L_X10Y146", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y146": "SLICEM", + "SLICE_X13Y146": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y147": { + "bits": {}, + "grid_x": 30, + "grid_y": 55, + "segment": "SEG_CLBLM_L_X10Y147", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y147": "SLICEM", + "SLICE_X13Y147": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y148": { + "bits": {}, + "grid_x": 30, + "grid_y": 54, + "segment": "SEG_CLBLM_L_X10Y148", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y148": "SLICEM", + "SLICE_X13Y148": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y149": { + "bits": {}, + "grid_x": 30, + "grid_y": 53, + "segment": "SEG_CLBLM_L_X10Y149", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y149": "SLICEM", + "SLICE_X13Y149": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y15": { + "bits": {}, + "grid_x": 30, + "grid_y": 192, + "segment": "SEG_CLBLM_L_X10Y15", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y15": "SLICEM", + "SLICE_X13Y15": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y150": { + "bits": {}, + "grid_x": 30, + "grid_y": 51, + "segment": "SEG_CLBLM_L_X10Y150", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y150": "SLICEM", + "SLICE_X13Y150": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y151": { + "bits": {}, + "grid_x": 30, + "grid_y": 50, + "segment": "SEG_CLBLM_L_X10Y151", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y151": "SLICEM", + "SLICE_X13Y151": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y152": { + "bits": {}, + "grid_x": 30, + "grid_y": 49, + "segment": "SEG_CLBLM_L_X10Y152", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y152": "SLICEM", + "SLICE_X13Y152": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y153": { + "bits": {}, + "grid_x": 30, + "grid_y": 48, + "segment": "SEG_CLBLM_L_X10Y153", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y153": "SLICEM", + "SLICE_X13Y153": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y154": { + "bits": {}, + "grid_x": 30, + "grid_y": 47, + "segment": "SEG_CLBLM_L_X10Y154", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y154": "SLICEM", + "SLICE_X13Y154": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y155": { + "bits": {}, + "grid_x": 30, + "grid_y": 46, + "segment": "SEG_CLBLM_L_X10Y155", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y155": "SLICEM", + "SLICE_X13Y155": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y156": { + "bits": {}, + "grid_x": 30, + "grid_y": 45, + "segment": "SEG_CLBLM_L_X10Y156", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y156": "SLICEM", + "SLICE_X13Y156": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y157": { + "bits": {}, + "grid_x": 30, + "grid_y": 44, + "segment": "SEG_CLBLM_L_X10Y157", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y157": "SLICEM", + "SLICE_X13Y157": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y158": { + "bits": {}, + "grid_x": 30, + "grid_y": 43, + "segment": "SEG_CLBLM_L_X10Y158", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y158": "SLICEM", + "SLICE_X13Y158": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y159": { + "bits": {}, + "grid_x": 30, + "grid_y": 42, + "segment": "SEG_CLBLM_L_X10Y159", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y159": "SLICEM", + "SLICE_X13Y159": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y16": { + "bits": {}, + "grid_x": 30, + "grid_y": 191, + "segment": "SEG_CLBLM_L_X10Y16", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y16": "SLICEM", + "SLICE_X13Y16": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y160": { + "bits": {}, + "grid_x": 30, + "grid_y": 41, + "segment": "SEG_CLBLM_L_X10Y160", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y160": "SLICEM", + "SLICE_X13Y160": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y161": { + "bits": {}, + "grid_x": 30, + "grid_y": 40, + "segment": "SEG_CLBLM_L_X10Y161", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y161": "SLICEM", + "SLICE_X13Y161": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y162": { + "bits": {}, + "grid_x": 30, + "grid_y": 39, + "segment": "SEG_CLBLM_L_X10Y162", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y162": "SLICEM", + "SLICE_X13Y162": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y163": { + "bits": {}, + "grid_x": 30, + "grid_y": 38, + "segment": "SEG_CLBLM_L_X10Y163", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y163": "SLICEM", + "SLICE_X13Y163": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y164": { + "bits": {}, + "grid_x": 30, + "grid_y": 37, + "segment": "SEG_CLBLM_L_X10Y164", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y164": "SLICEM", + "SLICE_X13Y164": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y165": { + "bits": {}, + "grid_x": 30, + "grid_y": 36, + "segment": "SEG_CLBLM_L_X10Y165", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y165": "SLICEM", + "SLICE_X13Y165": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y166": { + "bits": {}, + "grid_x": 30, + "grid_y": 35, + "segment": "SEG_CLBLM_L_X10Y166", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y166": "SLICEM", + "SLICE_X13Y166": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y167": { + "bits": {}, + "grid_x": 30, + "grid_y": 34, + "segment": "SEG_CLBLM_L_X10Y167", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y167": "SLICEM", + "SLICE_X13Y167": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y168": { + "bits": {}, + "grid_x": 30, + "grid_y": 33, + "segment": "SEG_CLBLM_L_X10Y168", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y168": "SLICEM", + "SLICE_X13Y168": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y169": { + "bits": {}, + "grid_x": 30, + "grid_y": 32, + "segment": "SEG_CLBLM_L_X10Y169", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y169": "SLICEM", + "SLICE_X13Y169": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y17": { + "bits": {}, + "grid_x": 30, + "grid_y": 190, + "segment": "SEG_CLBLM_L_X10Y17", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y17": "SLICEM", + "SLICE_X13Y17": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y170": { + "bits": {}, + "grid_x": 30, + "grid_y": 31, + "segment": "SEG_CLBLM_L_X10Y170", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y170": "SLICEM", + "SLICE_X13Y170": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y171": { + "bits": {}, + "grid_x": 30, + "grid_y": 30, + "segment": "SEG_CLBLM_L_X10Y171", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y171": "SLICEM", + "SLICE_X13Y171": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y172": { + "bits": {}, + "grid_x": 30, + "grid_y": 29, + "segment": "SEG_CLBLM_L_X10Y172", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y172": "SLICEM", + "SLICE_X13Y172": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y173": { + "bits": {}, + "grid_x": 30, + "grid_y": 28, + "segment": "SEG_CLBLM_L_X10Y173", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y173": "SLICEM", + "SLICE_X13Y173": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y174": { + "bits": {}, + "grid_x": 30, + "grid_y": 27, + "segment": "SEG_CLBLM_L_X10Y174", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y174": "SLICEM", + "SLICE_X13Y174": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y175": { + "bits": {}, + "grid_x": 30, + "grid_y": 25, + "segment": "SEG_CLBLM_L_X10Y175", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y175": "SLICEM", + "SLICE_X13Y175": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y176": { + "bits": {}, + "grid_x": 30, + "grid_y": 24, + "segment": "SEG_CLBLM_L_X10Y176", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y176": "SLICEM", + "SLICE_X13Y176": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y177": { + "bits": {}, + "grid_x": 30, + "grid_y": 23, + "segment": "SEG_CLBLM_L_X10Y177", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y177": "SLICEM", + "SLICE_X13Y177": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y178": { + "bits": {}, + "grid_x": 30, + "grid_y": 22, + "segment": "SEG_CLBLM_L_X10Y178", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y178": "SLICEM", + "SLICE_X13Y178": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y179": { + "bits": {}, + "grid_x": 30, + "grid_y": 21, + "segment": "SEG_CLBLM_L_X10Y179", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y179": "SLICEM", + "SLICE_X13Y179": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y18": { + "bits": {}, + "grid_x": 30, + "grid_y": 189, + "segment": "SEG_CLBLM_L_X10Y18", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y18": "SLICEM", + "SLICE_X13Y18": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y180": { + "bits": {}, + "grid_x": 30, + "grid_y": 20, + "segment": "SEG_CLBLM_L_X10Y180", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y180": "SLICEM", + "SLICE_X13Y180": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y181": { + "bits": {}, + "grid_x": 30, + "grid_y": 19, + "segment": "SEG_CLBLM_L_X10Y181", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y181": "SLICEM", + "SLICE_X13Y181": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y182": { + "bits": {}, + "grid_x": 30, + "grid_y": 18, + "segment": "SEG_CLBLM_L_X10Y182", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y182": "SLICEM", + "SLICE_X13Y182": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y183": { + "bits": {}, + "grid_x": 30, + "grid_y": 17, + "segment": "SEG_CLBLM_L_X10Y183", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y183": "SLICEM", + "SLICE_X13Y183": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y184": { + "bits": {}, + "grid_x": 30, + "grid_y": 16, + "segment": "SEG_CLBLM_L_X10Y184", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y184": "SLICEM", + "SLICE_X13Y184": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y185": { + "bits": {}, + "grid_x": 30, + "grid_y": 15, + "segment": "SEG_CLBLM_L_X10Y185", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y185": "SLICEM", + "SLICE_X13Y185": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y186": { + "bits": {}, + "grid_x": 30, + "grid_y": 14, + "segment": "SEG_CLBLM_L_X10Y186", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y186": "SLICEM", + "SLICE_X13Y186": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y187": { + "bits": {}, + "grid_x": 30, + "grid_y": 13, + "segment": "SEG_CLBLM_L_X10Y187", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y187": "SLICEM", + "SLICE_X13Y187": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y188": { + "bits": {}, + "grid_x": 30, + "grid_y": 12, + "segment": "SEG_CLBLM_L_X10Y188", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y188": "SLICEM", + "SLICE_X13Y188": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y189": { + "bits": {}, + "grid_x": 30, + "grid_y": 11, + "segment": "SEG_CLBLM_L_X10Y189", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y189": "SLICEM", + "SLICE_X13Y189": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y19": { + "bits": {}, + "grid_x": 30, + "grid_y": 188, + "segment": "SEG_CLBLM_L_X10Y19", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y19": "SLICEM", + "SLICE_X13Y19": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y190": { + "bits": {}, + "grid_x": 30, + "grid_y": 10, + "segment": "SEG_CLBLM_L_X10Y190", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y190": "SLICEM", + "SLICE_X13Y190": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y191": { + "bits": {}, + "grid_x": 30, + "grid_y": 9, + "segment": "SEG_CLBLM_L_X10Y191", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y191": "SLICEM", + "SLICE_X13Y191": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y192": { + "bits": {}, + "grid_x": 30, + "grid_y": 8, + "segment": "SEG_CLBLM_L_X10Y192", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y192": "SLICEM", + "SLICE_X13Y192": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y193": { + "bits": {}, + "grid_x": 30, + "grid_y": 7, + "segment": "SEG_CLBLM_L_X10Y193", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y193": "SLICEM", + "SLICE_X13Y193": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y194": { + "bits": {}, + "grid_x": 30, + "grid_y": 6, + "segment": "SEG_CLBLM_L_X10Y194", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y194": "SLICEM", + "SLICE_X13Y194": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y195": { + "bits": {}, + "grid_x": 30, + "grid_y": 5, + "segment": "SEG_CLBLM_L_X10Y195", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y195": "SLICEM", + "SLICE_X13Y195": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y196": { + "bits": {}, + "grid_x": 30, + "grid_y": 4, + "segment": "SEG_CLBLM_L_X10Y196", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y196": "SLICEM", + "SLICE_X13Y196": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y197": { + "bits": {}, + "grid_x": 30, + "grid_y": 3, + "segment": "SEG_CLBLM_L_X10Y197", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y197": "SLICEM", + "SLICE_X13Y197": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y198": { + "bits": {}, + "grid_x": 30, + "grid_y": 2, + "segment": "SEG_CLBLM_L_X10Y198", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y198": "SLICEM", + "SLICE_X13Y198": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y199": { + "bits": {}, + "grid_x": 30, + "grid_y": 1, + "segment": "SEG_CLBLM_L_X10Y199", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y199": "SLICEM", + "SLICE_X13Y199": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y2": { + "bits": {}, + "grid_x": 30, + "grid_y": 205, + "segment": "SEG_CLBLM_L_X10Y2", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y2": "SLICEM", + "SLICE_X13Y2": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y20": { + "bits": {}, + "grid_x": 30, + "grid_y": 187, + "segment": "SEG_CLBLM_L_X10Y20", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y20": "SLICEM", + "SLICE_X13Y20": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y21": { + "bits": {}, + "grid_x": 30, + "grid_y": 186, + "segment": "SEG_CLBLM_L_X10Y21", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y21": "SLICEM", + "SLICE_X13Y21": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y22": { + "bits": {}, + "grid_x": 30, + "grid_y": 185, + "segment": "SEG_CLBLM_L_X10Y22", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y22": "SLICEM", + "SLICE_X13Y22": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y23": { + "bits": {}, + "grid_x": 30, + "grid_y": 184, + "segment": "SEG_CLBLM_L_X10Y23", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y23": "SLICEM", + "SLICE_X13Y23": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y24": { + "bits": {}, + "grid_x": 30, + "grid_y": 183, + "segment": "SEG_CLBLM_L_X10Y24", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y24": "SLICEM", + "SLICE_X13Y24": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y25": { + "bits": {}, + "grid_x": 30, + "grid_y": 181, + "segment": "SEG_CLBLM_L_X10Y25", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y25": "SLICEM", + "SLICE_X13Y25": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y26": { + "bits": {}, + "grid_x": 30, + "grid_y": 180, + "segment": "SEG_CLBLM_L_X10Y26", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y26": "SLICEM", + "SLICE_X13Y26": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y27": { + "bits": {}, + "grid_x": 30, + "grid_y": 179, + "segment": "SEG_CLBLM_L_X10Y27", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y27": "SLICEM", + "SLICE_X13Y27": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y28": { + "bits": {}, + "grid_x": 30, + "grid_y": 178, + "segment": "SEG_CLBLM_L_X10Y28", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y28": "SLICEM", + "SLICE_X13Y28": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y29": { + "bits": {}, + "grid_x": 30, + "grid_y": 177, + "segment": "SEG_CLBLM_L_X10Y29", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y29": "SLICEM", + "SLICE_X13Y29": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y3": { + "bits": {}, + "grid_x": 30, + "grid_y": 204, + "segment": "SEG_CLBLM_L_X10Y3", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y3": "SLICEM", + "SLICE_X13Y3": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y30": { + "bits": {}, + "grid_x": 30, + "grid_y": 176, + "segment": "SEG_CLBLM_L_X10Y30", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y30": "SLICEM", + "SLICE_X13Y30": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y31": { + "bits": {}, + "grid_x": 30, + "grid_y": 175, + "segment": "SEG_CLBLM_L_X10Y31", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y31": "SLICEM", + "SLICE_X13Y31": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y32": { + "bits": {}, + "grid_x": 30, + "grid_y": 174, + "segment": "SEG_CLBLM_L_X10Y32", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y32": "SLICEM", + "SLICE_X13Y32": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y33": { + "bits": {}, + "grid_x": 30, + "grid_y": 173, + "segment": "SEG_CLBLM_L_X10Y33", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y33": "SLICEM", + "SLICE_X13Y33": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y34": { + "bits": {}, + "grid_x": 30, + "grid_y": 172, + "segment": "SEG_CLBLM_L_X10Y34", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y34": "SLICEM", + "SLICE_X13Y34": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y35": { + "bits": {}, + "grid_x": 30, + "grid_y": 171, + "segment": "SEG_CLBLM_L_X10Y35", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y35": "SLICEM", + "SLICE_X13Y35": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y36": { + "bits": {}, + "grid_x": 30, + "grid_y": 170, + "segment": "SEG_CLBLM_L_X10Y36", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y36": "SLICEM", + "SLICE_X13Y36": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y37": { + "bits": {}, + "grid_x": 30, + "grid_y": 169, + "segment": "SEG_CLBLM_L_X10Y37", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y37": "SLICEM", + "SLICE_X13Y37": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y38": { + "bits": {}, + "grid_x": 30, + "grid_y": 168, + "segment": "SEG_CLBLM_L_X10Y38", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y38": "SLICEM", + "SLICE_X13Y38": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y39": { + "bits": {}, + "grid_x": 30, + "grid_y": 167, + "segment": "SEG_CLBLM_L_X10Y39", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y39": "SLICEM", + "SLICE_X13Y39": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y4": { + "bits": {}, + "grid_x": 30, + "grid_y": 203, + "segment": "SEG_CLBLM_L_X10Y4", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y4": "SLICEM", + "SLICE_X13Y4": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y40": { + "bits": {}, + "grid_x": 30, + "grid_y": 166, + "segment": "SEG_CLBLM_L_X10Y40", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y40": "SLICEM", + "SLICE_X13Y40": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y41": { + "bits": {}, + "grid_x": 30, + "grid_y": 165, + "segment": "SEG_CLBLM_L_X10Y41", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y41": "SLICEM", + "SLICE_X13Y41": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y42": { + "bits": {}, + "grid_x": 30, + "grid_y": 164, + "segment": "SEG_CLBLM_L_X10Y42", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y42": "SLICEM", + "SLICE_X13Y42": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y43": { + "bits": {}, + "grid_x": 30, + "grid_y": 163, + "segment": "SEG_CLBLM_L_X10Y43", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y43": "SLICEM", + "SLICE_X13Y43": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y44": { + "bits": {}, + "grid_x": 30, + "grid_y": 162, + "segment": "SEG_CLBLM_L_X10Y44", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y44": "SLICEM", + "SLICE_X13Y44": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y45": { + "bits": {}, + "grid_x": 30, + "grid_y": 161, + "segment": "SEG_CLBLM_L_X10Y45", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y45": "SLICEM", + "SLICE_X13Y45": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y46": { + "bits": {}, + "grid_x": 30, + "grid_y": 160, + "segment": "SEG_CLBLM_L_X10Y46", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y46": "SLICEM", + "SLICE_X13Y46": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y47": { + "bits": {}, + "grid_x": 30, + "grid_y": 159, + "segment": "SEG_CLBLM_L_X10Y47", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y47": "SLICEM", + "SLICE_X13Y47": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y48": { + "bits": {}, + "grid_x": 30, + "grid_y": 158, + "segment": "SEG_CLBLM_L_X10Y48", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y48": "SLICEM", + "SLICE_X13Y48": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y49": { + "bits": {}, + "grid_x": 30, + "grid_y": 157, + "segment": "SEG_CLBLM_L_X10Y49", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y49": "SLICEM", + "SLICE_X13Y49": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y5": { + "bits": {}, + "grid_x": 30, + "grid_y": 202, + "segment": "SEG_CLBLM_L_X10Y5", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y5": "SLICEM", + "SLICE_X13Y5": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 155, + "segment": "SEG_CLBLM_L_X10Y50", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y50": "SLICEM", + "SLICE_X13Y50": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 154, + "segment": "SEG_CLBLM_L_X10Y51", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y51": "SLICEM", + "SLICE_X13Y51": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 153, + "segment": "SEG_CLBLM_L_X10Y52", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y52": "SLICEM", + "SLICE_X13Y52": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 152, + "segment": "SEG_CLBLM_L_X10Y53", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y53": "SLICEM", + "SLICE_X13Y53": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 151, + "segment": "SEG_CLBLM_L_X10Y54", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y54": "SLICEM", + "SLICE_X13Y54": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 150, + "segment": "SEG_CLBLM_L_X10Y55", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y55": "SLICEM", + "SLICE_X13Y55": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 149, + "segment": "SEG_CLBLM_L_X10Y56", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y56": "SLICEM", + "SLICE_X13Y56": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 148, + "segment": "SEG_CLBLM_L_X10Y57", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y57": "SLICEM", + "SLICE_X13Y57": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 147, + "segment": "SEG_CLBLM_L_X10Y58", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y58": "SLICEM", + "SLICE_X13Y58": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 146, + "segment": "SEG_CLBLM_L_X10Y59", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y59": "SLICEM", + "SLICE_X13Y59": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y6": { + "bits": {}, + "grid_x": 30, + "grid_y": 201, + "segment": "SEG_CLBLM_L_X10Y6", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y6": "SLICEM", + "SLICE_X13Y6": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 145, + "segment": "SEG_CLBLM_L_X10Y60", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y60": "SLICEM", + "SLICE_X13Y60": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 144, + "segment": "SEG_CLBLM_L_X10Y61", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y61": "SLICEM", + "SLICE_X13Y61": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 143, + "segment": "SEG_CLBLM_L_X10Y62", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y62": "SLICEM", + "SLICE_X13Y62": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 142, + "segment": "SEG_CLBLM_L_X10Y63", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y63": "SLICEM", + "SLICE_X13Y63": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 141, + "segment": "SEG_CLBLM_L_X10Y64", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y64": "SLICEM", + "SLICE_X13Y64": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 140, + "segment": "SEG_CLBLM_L_X10Y65", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y65": "SLICEM", + "SLICE_X13Y65": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 139, + "segment": "SEG_CLBLM_L_X10Y66", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y66": "SLICEM", + "SLICE_X13Y66": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 138, + "segment": "SEG_CLBLM_L_X10Y67", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y67": "SLICEM", + "SLICE_X13Y67": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 137, + "segment": "SEG_CLBLM_L_X10Y68", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y68": "SLICEM", + "SLICE_X13Y68": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 136, + "segment": "SEG_CLBLM_L_X10Y69", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y69": "SLICEM", + "SLICE_X13Y69": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y7": { + "bits": {}, + "grid_x": 30, + "grid_y": 200, + "segment": "SEG_CLBLM_L_X10Y7", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y7": "SLICEM", + "SLICE_X13Y7": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 135, + "segment": "SEG_CLBLM_L_X10Y70", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y70": "SLICEM", + "SLICE_X13Y70": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 134, + "segment": "SEG_CLBLM_L_X10Y71", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y71": "SLICEM", + "SLICE_X13Y71": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 133, + "segment": "SEG_CLBLM_L_X10Y72", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y72": "SLICEM", + "SLICE_X13Y72": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 132, + "segment": "SEG_CLBLM_L_X10Y73", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y73": "SLICEM", + "SLICE_X13Y73": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 131, + "segment": "SEG_CLBLM_L_X10Y74", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y74": "SLICEM", + "SLICE_X13Y74": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 129, + "segment": "SEG_CLBLM_L_X10Y75", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y75": "SLICEM", + "SLICE_X13Y75": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 128, + "segment": "SEG_CLBLM_L_X10Y76", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y76": "SLICEM", + "SLICE_X13Y76": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 127, + "segment": "SEG_CLBLM_L_X10Y77", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y77": "SLICEM", + "SLICE_X13Y77": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 126, + "segment": "SEG_CLBLM_L_X10Y78", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y78": "SLICEM", + "SLICE_X13Y78": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 125, + "segment": "SEG_CLBLM_L_X10Y79", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y79": "SLICEM", + "SLICE_X13Y79": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y8": { + "bits": {}, + "grid_x": 30, + "grid_y": 199, + "segment": "SEG_CLBLM_L_X10Y8", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y8": "SLICEM", + "SLICE_X13Y8": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 124, + "segment": "SEG_CLBLM_L_X10Y80", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y80": "SLICEM", + "SLICE_X13Y80": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 123, + "segment": "SEG_CLBLM_L_X10Y81", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y81": "SLICEM", + "SLICE_X13Y81": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 122, + "segment": "SEG_CLBLM_L_X10Y82", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y82": "SLICEM", + "SLICE_X13Y82": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 121, + "segment": "SEG_CLBLM_L_X10Y83", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y83": "SLICEM", + "SLICE_X13Y83": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 120, + "segment": "SEG_CLBLM_L_X10Y84", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y84": "SLICEM", + "SLICE_X13Y84": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 119, + "segment": "SEG_CLBLM_L_X10Y85", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y85": "SLICEM", + "SLICE_X13Y85": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 118, + "segment": "SEG_CLBLM_L_X10Y86", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y86": "SLICEM", + "SLICE_X13Y86": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 117, + "segment": "SEG_CLBLM_L_X10Y87", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y87": "SLICEM", + "SLICE_X13Y87": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 116, + "segment": "SEG_CLBLM_L_X10Y88", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y88": "SLICEM", + "SLICE_X13Y88": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 115, + "segment": "SEG_CLBLM_L_X10Y89", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y89": "SLICEM", + "SLICE_X13Y89": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y9": { + "bits": {}, + "grid_x": 30, + "grid_y": 198, + "segment": "SEG_CLBLM_L_X10Y9", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y9": "SLICEM", + "SLICE_X13Y9": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 114, + "segment": "SEG_CLBLM_L_X10Y90", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y90": "SLICEM", + "SLICE_X13Y90": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 113, + "segment": "SEG_CLBLM_L_X10Y91", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y91": "SLICEM", + "SLICE_X13Y91": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 112, + "segment": "SEG_CLBLM_L_X10Y92", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y92": "SLICEM", + "SLICE_X13Y92": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 111, + "segment": "SEG_CLBLM_L_X10Y93", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y93": "SLICEM", + "SLICE_X13Y93": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 110, + "segment": "SEG_CLBLM_L_X10Y94", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y94": "SLICEM", + "SLICE_X13Y94": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 109, + "segment": "SEG_CLBLM_L_X10Y95", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y95": "SLICEM", + "SLICE_X13Y95": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 108, + "segment": "SEG_CLBLM_L_X10Y96", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y96": "SLICEM", + "SLICE_X13Y96": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 107, + "segment": "SEG_CLBLM_L_X10Y97", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y97": "SLICEM", + "SLICE_X13Y97": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 106, + "segment": "SEG_CLBLM_L_X10Y98", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y98": "SLICEM", + "SLICE_X13Y98": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X10Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 36, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 30, + "grid_y": 105, + "segment": "SEG_CLBLM_L_X10Y99", + "segment_type": "clblm_l", + "sites": { + "SLICE_X12Y99": "SLICEM", + "SLICE_X13Y99": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y0": { + "bits": {}, + "grid_x": 34, + "grid_y": 207, + "segment": "SEG_CLBLM_L_X12Y0", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y0": "SLICEM", + "SLICE_X17Y0": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y1": { + "bits": {}, + "grid_x": 34, + "grid_y": 206, + "segment": "SEG_CLBLM_L_X12Y1", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y1": "SLICEM", + "SLICE_X17Y1": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y10": { + "bits": {}, + "grid_x": 34, + "grid_y": 197, + "segment": "SEG_CLBLM_L_X12Y10", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y10": "SLICEM", + "SLICE_X17Y10": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y100": { + "bits": {}, + "grid_x": 34, + "grid_y": 103, + "segment": "SEG_CLBLM_L_X12Y100", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y100": "SLICEM", + "SLICE_X17Y100": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y101": { + "bits": {}, + "grid_x": 34, + "grid_y": 102, + "segment": "SEG_CLBLM_L_X12Y101", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y101": "SLICEM", + "SLICE_X17Y101": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y102": { + "bits": {}, + "grid_x": 34, + "grid_y": 101, + "segment": "SEG_CLBLM_L_X12Y102", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y102": "SLICEM", + "SLICE_X17Y102": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y103": { + "bits": {}, + "grid_x": 34, + "grid_y": 100, + "segment": "SEG_CLBLM_L_X12Y103", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y103": "SLICEM", + "SLICE_X17Y103": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y104": { + "bits": {}, + "grid_x": 34, + "grid_y": 99, + "segment": "SEG_CLBLM_L_X12Y104", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y104": "SLICEM", + "SLICE_X17Y104": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y105": { + "bits": {}, + "grid_x": 34, + "grid_y": 98, + "segment": "SEG_CLBLM_L_X12Y105", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y105": "SLICEM", + "SLICE_X17Y105": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y106": { + "bits": {}, + "grid_x": 34, + "grid_y": 97, + "segment": "SEG_CLBLM_L_X12Y106", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y106": "SLICEM", + "SLICE_X17Y106": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y107": { + "bits": {}, + "grid_x": 34, + "grid_y": 96, + "segment": "SEG_CLBLM_L_X12Y107", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y107": "SLICEM", + "SLICE_X17Y107": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y108": { + "bits": {}, + "grid_x": 34, + "grid_y": 95, + "segment": "SEG_CLBLM_L_X12Y108", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y108": "SLICEM", + "SLICE_X17Y108": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y109": { + "bits": {}, + "grid_x": 34, + "grid_y": 94, + "segment": "SEG_CLBLM_L_X12Y109", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y109": "SLICEM", + "SLICE_X17Y109": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y11": { + "bits": {}, + "grid_x": 34, + "grid_y": 196, + "segment": "SEG_CLBLM_L_X12Y11", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y11": "SLICEM", + "SLICE_X17Y11": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y110": { + "bits": {}, + "grid_x": 34, + "grid_y": 93, + "segment": "SEG_CLBLM_L_X12Y110", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y110": "SLICEM", + "SLICE_X17Y110": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y111": { + "bits": {}, + "grid_x": 34, + "grid_y": 92, + "segment": "SEG_CLBLM_L_X12Y111", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y111": "SLICEM", + "SLICE_X17Y111": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y112": { + "bits": {}, + "grid_x": 34, + "grid_y": 91, + "segment": "SEG_CLBLM_L_X12Y112", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y112": "SLICEM", + "SLICE_X17Y112": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y113": { + "bits": {}, + "grid_x": 34, + "grid_y": 90, + "segment": "SEG_CLBLM_L_X12Y113", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y113": "SLICEM", + "SLICE_X17Y113": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y114": { + "bits": {}, + "grid_x": 34, + "grid_y": 89, + "segment": "SEG_CLBLM_L_X12Y114", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y114": "SLICEM", + "SLICE_X17Y114": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y115": { + "bits": {}, + "grid_x": 34, + "grid_y": 88, + "segment": "SEG_CLBLM_L_X12Y115", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y115": "SLICEM", + "SLICE_X17Y115": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y116": { + "bits": {}, + "grid_x": 34, + "grid_y": 87, + "segment": "SEG_CLBLM_L_X12Y116", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y116": "SLICEM", + "SLICE_X17Y116": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y117": { + "bits": {}, + "grid_x": 34, + "grid_y": 86, + "segment": "SEG_CLBLM_L_X12Y117", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y117": "SLICEM", + "SLICE_X17Y117": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y118": { + "bits": {}, + "grid_x": 34, + "grid_y": 85, + "segment": "SEG_CLBLM_L_X12Y118", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y118": "SLICEM", + "SLICE_X17Y118": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y119": { + "bits": {}, + "grid_x": 34, + "grid_y": 84, + "segment": "SEG_CLBLM_L_X12Y119", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y119": "SLICEM", + "SLICE_X17Y119": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y12": { + "bits": {}, + "grid_x": 34, + "grid_y": 195, + "segment": "SEG_CLBLM_L_X12Y12", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y12": "SLICEM", + "SLICE_X17Y12": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y120": { + "bits": {}, + "grid_x": 34, + "grid_y": 83, + "segment": "SEG_CLBLM_L_X12Y120", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y120": "SLICEM", + "SLICE_X17Y120": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y121": { + "bits": {}, + "grid_x": 34, + "grid_y": 82, + "segment": "SEG_CLBLM_L_X12Y121", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y121": "SLICEM", + "SLICE_X17Y121": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y122": { + "bits": {}, + "grid_x": 34, + "grid_y": 81, + "segment": "SEG_CLBLM_L_X12Y122", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y122": "SLICEM", + "SLICE_X17Y122": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y123": { + "bits": {}, + "grid_x": 34, + "grid_y": 80, + "segment": "SEG_CLBLM_L_X12Y123", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y123": "SLICEM", + "SLICE_X17Y123": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y124": { + "bits": {}, + "grid_x": 34, + "grid_y": 79, + "segment": "SEG_CLBLM_L_X12Y124", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y124": "SLICEM", + "SLICE_X17Y124": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y125": { + "bits": {}, + "grid_x": 34, + "grid_y": 77, + "segment": "SEG_CLBLM_L_X12Y125", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y125": "SLICEM", + "SLICE_X17Y125": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y126": { + "bits": {}, + "grid_x": 34, + "grid_y": 76, + "segment": "SEG_CLBLM_L_X12Y126", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y126": "SLICEM", + "SLICE_X17Y126": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y127": { + "bits": {}, + "grid_x": 34, + "grid_y": 75, + "segment": "SEG_CLBLM_L_X12Y127", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y127": "SLICEM", + "SLICE_X17Y127": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y128": { + "bits": {}, + "grid_x": 34, + "grid_y": 74, + "segment": "SEG_CLBLM_L_X12Y128", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y128": "SLICEM", + "SLICE_X17Y128": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y129": { + "bits": {}, + "grid_x": 34, + "grid_y": 73, + "segment": "SEG_CLBLM_L_X12Y129", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y129": "SLICEM", + "SLICE_X17Y129": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y13": { + "bits": {}, + "grid_x": 34, + "grid_y": 194, + "segment": "SEG_CLBLM_L_X12Y13", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y13": "SLICEM", + "SLICE_X17Y13": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y130": { + "bits": {}, + "grid_x": 34, + "grid_y": 72, + "segment": "SEG_CLBLM_L_X12Y130", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y130": "SLICEM", + "SLICE_X17Y130": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y131": { + "bits": {}, + "grid_x": 34, + "grid_y": 71, + "segment": "SEG_CLBLM_L_X12Y131", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y131": "SLICEM", + "SLICE_X17Y131": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y132": { + "bits": {}, + "grid_x": 34, + "grid_y": 70, + "segment": "SEG_CLBLM_L_X12Y132", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y132": "SLICEM", + "SLICE_X17Y132": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y133": { + "bits": {}, + "grid_x": 34, + "grid_y": 69, + "segment": "SEG_CLBLM_L_X12Y133", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y133": "SLICEM", + "SLICE_X17Y133": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y134": { + "bits": {}, + "grid_x": 34, + "grid_y": 68, + "segment": "SEG_CLBLM_L_X12Y134", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y134": "SLICEM", + "SLICE_X17Y134": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y135": { + "bits": {}, + "grid_x": 34, + "grid_y": 67, + "segment": "SEG_CLBLM_L_X12Y135", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y135": "SLICEM", + "SLICE_X17Y135": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y136": { + "bits": {}, + "grid_x": 34, + "grid_y": 66, + "segment": "SEG_CLBLM_L_X12Y136", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y136": "SLICEM", + "SLICE_X17Y136": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y137": { + "bits": {}, + "grid_x": 34, + "grid_y": 65, + "segment": "SEG_CLBLM_L_X12Y137", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y137": "SLICEM", + "SLICE_X17Y137": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y138": { + "bits": {}, + "grid_x": 34, + "grid_y": 64, + "segment": "SEG_CLBLM_L_X12Y138", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y138": "SLICEM", + "SLICE_X17Y138": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y139": { + "bits": {}, + "grid_x": 34, + "grid_y": 63, + "segment": "SEG_CLBLM_L_X12Y139", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y139": "SLICEM", + "SLICE_X17Y139": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y14": { + "bits": {}, + "grid_x": 34, + "grid_y": 193, + "segment": "SEG_CLBLM_L_X12Y14", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y14": "SLICEM", + "SLICE_X17Y14": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y140": { + "bits": {}, + "grid_x": 34, + "grid_y": 62, + "segment": "SEG_CLBLM_L_X12Y140", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y140": "SLICEM", + "SLICE_X17Y140": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y141": { + "bits": {}, + "grid_x": 34, + "grid_y": 61, + "segment": "SEG_CLBLM_L_X12Y141", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y141": "SLICEM", + "SLICE_X17Y141": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y142": { + "bits": {}, + "grid_x": 34, + "grid_y": 60, + "segment": "SEG_CLBLM_L_X12Y142", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y142": "SLICEM", + "SLICE_X17Y142": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y143": { + "bits": {}, + "grid_x": 34, + "grid_y": 59, + "segment": "SEG_CLBLM_L_X12Y143", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y143": "SLICEM", + "SLICE_X17Y143": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y144": { + "bits": {}, + "grid_x": 34, + "grid_y": 58, + "segment": "SEG_CLBLM_L_X12Y144", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y144": "SLICEM", + "SLICE_X17Y144": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y145": { + "bits": {}, + "grid_x": 34, + "grid_y": 57, + "segment": "SEG_CLBLM_L_X12Y145", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y145": "SLICEM", + "SLICE_X17Y145": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y146": { + "bits": {}, + "grid_x": 34, + "grid_y": 56, + "segment": "SEG_CLBLM_L_X12Y146", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y146": "SLICEM", + "SLICE_X17Y146": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y147": { + "bits": {}, + "grid_x": 34, + "grid_y": 55, + "segment": "SEG_CLBLM_L_X12Y147", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y147": "SLICEM", + "SLICE_X17Y147": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y148": { + "bits": {}, + "grid_x": 34, + "grid_y": 54, + "segment": "SEG_CLBLM_L_X12Y148", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y148": "SLICEM", + "SLICE_X17Y148": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y149": { + "bits": {}, + "grid_x": 34, + "grid_y": 53, + "segment": "SEG_CLBLM_L_X12Y149", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y149": "SLICEM", + "SLICE_X17Y149": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y15": { + "bits": {}, + "grid_x": 34, + "grid_y": 192, + "segment": "SEG_CLBLM_L_X12Y15", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y15": "SLICEM", + "SLICE_X17Y15": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y150": { + "bits": {}, + "grid_x": 34, + "grid_y": 51, + "segment": "SEG_CLBLM_L_X12Y150", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y150": "SLICEM", + "SLICE_X17Y150": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y151": { + "bits": {}, + "grid_x": 34, + "grid_y": 50, + "segment": "SEG_CLBLM_L_X12Y151", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y151": "SLICEM", + "SLICE_X17Y151": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y152": { + "bits": {}, + "grid_x": 34, + "grid_y": 49, + "segment": "SEG_CLBLM_L_X12Y152", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y152": "SLICEM", + "SLICE_X17Y152": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y153": { + "bits": {}, + "grid_x": 34, + "grid_y": 48, + "segment": "SEG_CLBLM_L_X12Y153", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y153": "SLICEM", + "SLICE_X17Y153": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y154": { + "bits": {}, + "grid_x": 34, + "grid_y": 47, + "segment": "SEG_CLBLM_L_X12Y154", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y154": "SLICEM", + "SLICE_X17Y154": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y155": { + "bits": {}, + "grid_x": 34, + "grid_y": 46, + "segment": "SEG_CLBLM_L_X12Y155", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y155": "SLICEM", + "SLICE_X17Y155": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y156": { + "bits": {}, + "grid_x": 34, + "grid_y": 45, + "segment": "SEG_CLBLM_L_X12Y156", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y156": "SLICEM", + "SLICE_X17Y156": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y157": { + "bits": {}, + "grid_x": 34, + "grid_y": 44, + "segment": "SEG_CLBLM_L_X12Y157", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y157": "SLICEM", + "SLICE_X17Y157": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y158": { + "bits": {}, + "grid_x": 34, + "grid_y": 43, + "segment": "SEG_CLBLM_L_X12Y158", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y158": "SLICEM", + "SLICE_X17Y158": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y159": { + "bits": {}, + "grid_x": 34, + "grid_y": 42, + "segment": "SEG_CLBLM_L_X12Y159", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y159": "SLICEM", + "SLICE_X17Y159": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y16": { + "bits": {}, + "grid_x": 34, + "grid_y": 191, + "segment": "SEG_CLBLM_L_X12Y16", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y16": "SLICEM", + "SLICE_X17Y16": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y160": { + "bits": {}, + "grid_x": 34, + "grid_y": 41, + "segment": "SEG_CLBLM_L_X12Y160", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y160": "SLICEM", + "SLICE_X17Y160": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y161": { + "bits": {}, + "grid_x": 34, + "grid_y": 40, + "segment": "SEG_CLBLM_L_X12Y161", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y161": "SLICEM", + "SLICE_X17Y161": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y162": { + "bits": {}, + "grid_x": 34, + "grid_y": 39, + "segment": "SEG_CLBLM_L_X12Y162", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y162": "SLICEM", + "SLICE_X17Y162": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y163": { + "bits": {}, + "grid_x": 34, + "grid_y": 38, + "segment": "SEG_CLBLM_L_X12Y163", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y163": "SLICEM", + "SLICE_X17Y163": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y164": { + "bits": {}, + "grid_x": 34, + "grid_y": 37, + "segment": "SEG_CLBLM_L_X12Y164", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y164": "SLICEM", + "SLICE_X17Y164": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y165": { + "bits": {}, + "grid_x": 34, + "grid_y": 36, + "segment": "SEG_CLBLM_L_X12Y165", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y165": "SLICEM", + "SLICE_X17Y165": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y166": { + "bits": {}, + "grid_x": 34, + "grid_y": 35, + "segment": "SEG_CLBLM_L_X12Y166", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y166": "SLICEM", + "SLICE_X17Y166": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y167": { + "bits": {}, + "grid_x": 34, + "grid_y": 34, + "segment": "SEG_CLBLM_L_X12Y167", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y167": "SLICEM", + "SLICE_X17Y167": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y168": { + "bits": {}, + "grid_x": 34, + "grid_y": 33, + "segment": "SEG_CLBLM_L_X12Y168", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y168": "SLICEM", + "SLICE_X17Y168": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y169": { + "bits": {}, + "grid_x": 34, + "grid_y": 32, + "segment": "SEG_CLBLM_L_X12Y169", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y169": "SLICEM", + "SLICE_X17Y169": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y17": { + "bits": {}, + "grid_x": 34, + "grid_y": 190, + "segment": "SEG_CLBLM_L_X12Y17", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y17": "SLICEM", + "SLICE_X17Y17": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y170": { + "bits": {}, + "grid_x": 34, + "grid_y": 31, + "segment": "SEG_CLBLM_L_X12Y170", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y170": "SLICEM", + "SLICE_X17Y170": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y171": { + "bits": {}, + "grid_x": 34, + "grid_y": 30, + "segment": "SEG_CLBLM_L_X12Y171", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y171": "SLICEM", + "SLICE_X17Y171": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y172": { + "bits": {}, + "grid_x": 34, + "grid_y": 29, + "segment": "SEG_CLBLM_L_X12Y172", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y172": "SLICEM", + "SLICE_X17Y172": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y173": { + "bits": {}, + "grid_x": 34, + "grid_y": 28, + "segment": "SEG_CLBLM_L_X12Y173", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y173": "SLICEM", + "SLICE_X17Y173": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y174": { + "bits": {}, + "grid_x": 34, + "grid_y": 27, + "segment": "SEG_CLBLM_L_X12Y174", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y174": "SLICEM", + "SLICE_X17Y174": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y175": { + "bits": {}, + "grid_x": 34, + "grid_y": 25, + "segment": "SEG_CLBLM_L_X12Y175", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y175": "SLICEM", + "SLICE_X17Y175": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y176": { + "bits": {}, + "grid_x": 34, + "grid_y": 24, + "segment": "SEG_CLBLM_L_X12Y176", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y176": "SLICEM", + "SLICE_X17Y176": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y177": { + "bits": {}, + "grid_x": 34, + "grid_y": 23, + "segment": "SEG_CLBLM_L_X12Y177", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y177": "SLICEM", + "SLICE_X17Y177": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y178": { + "bits": {}, + "grid_x": 34, + "grid_y": 22, + "segment": "SEG_CLBLM_L_X12Y178", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y178": "SLICEM", + "SLICE_X17Y178": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y179": { + "bits": {}, + "grid_x": 34, + "grid_y": 21, + "segment": "SEG_CLBLM_L_X12Y179", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y179": "SLICEM", + "SLICE_X17Y179": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y18": { + "bits": {}, + "grid_x": 34, + "grid_y": 189, + "segment": "SEG_CLBLM_L_X12Y18", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y18": "SLICEM", + "SLICE_X17Y18": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y180": { + "bits": {}, + "grid_x": 34, + "grid_y": 20, + "segment": "SEG_CLBLM_L_X12Y180", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y180": "SLICEM", + "SLICE_X17Y180": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y181": { + "bits": {}, + "grid_x": 34, + "grid_y": 19, + "segment": "SEG_CLBLM_L_X12Y181", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y181": "SLICEM", + "SLICE_X17Y181": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y182": { + "bits": {}, + "grid_x": 34, + "grid_y": 18, + "segment": "SEG_CLBLM_L_X12Y182", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y182": "SLICEM", + "SLICE_X17Y182": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y183": { + "bits": {}, + "grid_x": 34, + "grid_y": 17, + "segment": "SEG_CLBLM_L_X12Y183", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y183": "SLICEM", + "SLICE_X17Y183": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y184": { + "bits": {}, + "grid_x": 34, + "grid_y": 16, + "segment": "SEG_CLBLM_L_X12Y184", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y184": "SLICEM", + "SLICE_X17Y184": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y185": { + "bits": {}, + "grid_x": 34, + "grid_y": 15, + "segment": "SEG_CLBLM_L_X12Y185", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y185": "SLICEM", + "SLICE_X17Y185": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y186": { + "bits": {}, + "grid_x": 34, + "grid_y": 14, + "segment": "SEG_CLBLM_L_X12Y186", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y186": "SLICEM", + "SLICE_X17Y186": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y187": { + "bits": {}, + "grid_x": 34, + "grid_y": 13, + "segment": "SEG_CLBLM_L_X12Y187", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y187": "SLICEM", + "SLICE_X17Y187": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y188": { + "bits": {}, + "grid_x": 34, + "grid_y": 12, + "segment": "SEG_CLBLM_L_X12Y188", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y188": "SLICEM", + "SLICE_X17Y188": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y189": { + "bits": {}, + "grid_x": 34, + "grid_y": 11, + "segment": "SEG_CLBLM_L_X12Y189", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y189": "SLICEM", + "SLICE_X17Y189": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y19": { + "bits": {}, + "grid_x": 34, + "grid_y": 188, + "segment": "SEG_CLBLM_L_X12Y19", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y19": "SLICEM", + "SLICE_X17Y19": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y190": { + "bits": {}, + "grid_x": 34, + "grid_y": 10, + "segment": "SEG_CLBLM_L_X12Y190", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y190": "SLICEM", + "SLICE_X17Y190": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y191": { + "bits": {}, + "grid_x": 34, + "grid_y": 9, + "segment": "SEG_CLBLM_L_X12Y191", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y191": "SLICEM", + "SLICE_X17Y191": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y192": { + "bits": {}, + "grid_x": 34, + "grid_y": 8, + "segment": "SEG_CLBLM_L_X12Y192", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y192": "SLICEM", + "SLICE_X17Y192": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y193": { + "bits": {}, + "grid_x": 34, + "grid_y": 7, + "segment": "SEG_CLBLM_L_X12Y193", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y193": "SLICEM", + "SLICE_X17Y193": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y194": { + "bits": {}, + "grid_x": 34, + "grid_y": 6, + "segment": "SEG_CLBLM_L_X12Y194", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y194": "SLICEM", + "SLICE_X17Y194": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y195": { + "bits": {}, + "grid_x": 34, + "grid_y": 5, + "segment": "SEG_CLBLM_L_X12Y195", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y195": "SLICEM", + "SLICE_X17Y195": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y196": { + "bits": {}, + "grid_x": 34, + "grid_y": 4, + "segment": "SEG_CLBLM_L_X12Y196", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y196": "SLICEM", + "SLICE_X17Y196": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y197": { + "bits": {}, + "grid_x": 34, + "grid_y": 3, + "segment": "SEG_CLBLM_L_X12Y197", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y197": "SLICEM", + "SLICE_X17Y197": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y198": { + "bits": {}, + "grid_x": 34, + "grid_y": 2, + "segment": "SEG_CLBLM_L_X12Y198", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y198": "SLICEM", + "SLICE_X17Y198": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y199": { + "bits": {}, + "grid_x": 34, + "grid_y": 1, + "segment": "SEG_CLBLM_L_X12Y199", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y199": "SLICEM", + "SLICE_X17Y199": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y2": { + "bits": {}, + "grid_x": 34, + "grid_y": 205, + "segment": "SEG_CLBLM_L_X12Y2", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y2": "SLICEM", + "SLICE_X17Y2": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y20": { + "bits": {}, + "grid_x": 34, + "grid_y": 187, + "segment": "SEG_CLBLM_L_X12Y20", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y20": "SLICEM", + "SLICE_X17Y20": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y21": { + "bits": {}, + "grid_x": 34, + "grid_y": 186, + "segment": "SEG_CLBLM_L_X12Y21", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y21": "SLICEM", + "SLICE_X17Y21": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y22": { + "bits": {}, + "grid_x": 34, + "grid_y": 185, + "segment": "SEG_CLBLM_L_X12Y22", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y22": "SLICEM", + "SLICE_X17Y22": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y23": { + "bits": {}, + "grid_x": 34, + "grid_y": 184, + "segment": "SEG_CLBLM_L_X12Y23", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y23": "SLICEM", + "SLICE_X17Y23": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y24": { + "bits": {}, + "grid_x": 34, + "grid_y": 183, + "segment": "SEG_CLBLM_L_X12Y24", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y24": "SLICEM", + "SLICE_X17Y24": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y25": { + "bits": {}, + "grid_x": 34, + "grid_y": 181, + "segment": "SEG_CLBLM_L_X12Y25", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y25": "SLICEM", + "SLICE_X17Y25": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y26": { + "bits": {}, + "grid_x": 34, + "grid_y": 180, + "segment": "SEG_CLBLM_L_X12Y26", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y26": "SLICEM", + "SLICE_X17Y26": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y27": { + "bits": {}, + "grid_x": 34, + "grid_y": 179, + "segment": "SEG_CLBLM_L_X12Y27", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y27": "SLICEM", + "SLICE_X17Y27": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y28": { + "bits": {}, + "grid_x": 34, + "grid_y": 178, + "segment": "SEG_CLBLM_L_X12Y28", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y28": "SLICEM", + "SLICE_X17Y28": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y29": { + "bits": {}, + "grid_x": 34, + "grid_y": 177, + "segment": "SEG_CLBLM_L_X12Y29", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y29": "SLICEM", + "SLICE_X17Y29": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y3": { + "bits": {}, + "grid_x": 34, + "grid_y": 204, + "segment": "SEG_CLBLM_L_X12Y3", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y3": "SLICEM", + "SLICE_X17Y3": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y30": { + "bits": {}, + "grid_x": 34, + "grid_y": 176, + "segment": "SEG_CLBLM_L_X12Y30", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y30": "SLICEM", + "SLICE_X17Y30": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y31": { + "bits": {}, + "grid_x": 34, + "grid_y": 175, + "segment": "SEG_CLBLM_L_X12Y31", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y31": "SLICEM", + "SLICE_X17Y31": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y32": { + "bits": {}, + "grid_x": 34, + "grid_y": 174, + "segment": "SEG_CLBLM_L_X12Y32", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y32": "SLICEM", + "SLICE_X17Y32": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y33": { + "bits": {}, + "grid_x": 34, + "grid_y": 173, + "segment": "SEG_CLBLM_L_X12Y33", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y33": "SLICEM", + "SLICE_X17Y33": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y34": { + "bits": {}, + "grid_x": 34, + "grid_y": 172, + "segment": "SEG_CLBLM_L_X12Y34", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y34": "SLICEM", + "SLICE_X17Y34": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y35": { + "bits": {}, + "grid_x": 34, + "grid_y": 171, + "segment": "SEG_CLBLM_L_X12Y35", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y35": "SLICEM", + "SLICE_X17Y35": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y36": { + "bits": {}, + "grid_x": 34, + "grid_y": 170, + "segment": "SEG_CLBLM_L_X12Y36", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y36": "SLICEM", + "SLICE_X17Y36": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y37": { + "bits": {}, + "grid_x": 34, + "grid_y": 169, + "segment": "SEG_CLBLM_L_X12Y37", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y37": "SLICEM", + "SLICE_X17Y37": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y38": { + "bits": {}, + "grid_x": 34, + "grid_y": 168, + "segment": "SEG_CLBLM_L_X12Y38", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y38": "SLICEM", + "SLICE_X17Y38": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y39": { + "bits": {}, + "grid_x": 34, + "grid_y": 167, + "segment": "SEG_CLBLM_L_X12Y39", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y39": "SLICEM", + "SLICE_X17Y39": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y4": { + "bits": {}, + "grid_x": 34, + "grid_y": 203, + "segment": "SEG_CLBLM_L_X12Y4", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y4": "SLICEM", + "SLICE_X17Y4": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y40": { + "bits": {}, + "grid_x": 34, + "grid_y": 166, + "segment": "SEG_CLBLM_L_X12Y40", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y40": "SLICEM", + "SLICE_X17Y40": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y41": { + "bits": {}, + "grid_x": 34, + "grid_y": 165, + "segment": "SEG_CLBLM_L_X12Y41", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y41": "SLICEM", + "SLICE_X17Y41": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y42": { + "bits": {}, + "grid_x": 34, + "grid_y": 164, + "segment": "SEG_CLBLM_L_X12Y42", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y42": "SLICEM", + "SLICE_X17Y42": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y43": { + "bits": {}, + "grid_x": 34, + "grid_y": 163, + "segment": "SEG_CLBLM_L_X12Y43", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y43": "SLICEM", + "SLICE_X17Y43": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y44": { + "bits": {}, + "grid_x": 34, + "grid_y": 162, + "segment": "SEG_CLBLM_L_X12Y44", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y44": "SLICEM", + "SLICE_X17Y44": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y45": { + "bits": {}, + "grid_x": 34, + "grid_y": 161, + "segment": "SEG_CLBLM_L_X12Y45", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y45": "SLICEM", + "SLICE_X17Y45": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y46": { + "bits": {}, + "grid_x": 34, + "grid_y": 160, + "segment": "SEG_CLBLM_L_X12Y46", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y46": "SLICEM", + "SLICE_X17Y46": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y47": { + "bits": {}, + "grid_x": 34, + "grid_y": 159, + "segment": "SEG_CLBLM_L_X12Y47", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y47": "SLICEM", + "SLICE_X17Y47": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y48": { + "bits": {}, + "grid_x": 34, + "grid_y": 158, + "segment": "SEG_CLBLM_L_X12Y48", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y48": "SLICEM", + "SLICE_X17Y48": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y49": { + "bits": {}, + "grid_x": 34, + "grid_y": 157, + "segment": "SEG_CLBLM_L_X12Y49", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y49": "SLICEM", + "SLICE_X17Y49": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y5": { + "bits": {}, + "grid_x": 34, + "grid_y": 202, + "segment": "SEG_CLBLM_L_X12Y5", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y5": "SLICEM", + "SLICE_X17Y5": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 155, + "segment": "SEG_CLBLM_L_X12Y50", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y50": "SLICEM", + "SLICE_X17Y50": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 154, + "segment": "SEG_CLBLM_L_X12Y51", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y51": "SLICEM", + "SLICE_X17Y51": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 153, + "segment": "SEG_CLBLM_L_X12Y52", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y52": "SLICEM", + "SLICE_X17Y52": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 152, + "segment": "SEG_CLBLM_L_X12Y53", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y53": "SLICEM", + "SLICE_X17Y53": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 151, + "segment": "SEG_CLBLM_L_X12Y54", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y54": "SLICEM", + "SLICE_X17Y54": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 150, + "segment": "SEG_CLBLM_L_X12Y55", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y55": "SLICEM", + "SLICE_X17Y55": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 149, + "segment": "SEG_CLBLM_L_X12Y56", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y56": "SLICEM", + "SLICE_X17Y56": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 148, + "segment": "SEG_CLBLM_L_X12Y57", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y57": "SLICEM", + "SLICE_X17Y57": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 147, + "segment": "SEG_CLBLM_L_X12Y58", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y58": "SLICEM", + "SLICE_X17Y58": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 146, + "segment": "SEG_CLBLM_L_X12Y59", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y59": "SLICEM", + "SLICE_X17Y59": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y6": { + "bits": {}, + "grid_x": 34, + "grid_y": 201, + "segment": "SEG_CLBLM_L_X12Y6", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y6": "SLICEM", + "SLICE_X17Y6": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 145, + "segment": "SEG_CLBLM_L_X12Y60", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y60": "SLICEM", + "SLICE_X17Y60": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 144, + "segment": "SEG_CLBLM_L_X12Y61", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y61": "SLICEM", + "SLICE_X17Y61": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 143, + "segment": "SEG_CLBLM_L_X12Y62", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y62": "SLICEM", + "SLICE_X17Y62": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 142, + "segment": "SEG_CLBLM_L_X12Y63", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y63": "SLICEM", + "SLICE_X17Y63": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 141, + "segment": "SEG_CLBLM_L_X12Y64", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y64": "SLICEM", + "SLICE_X17Y64": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 140, + "segment": "SEG_CLBLM_L_X12Y65", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y65": "SLICEM", + "SLICE_X17Y65": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 139, + "segment": "SEG_CLBLM_L_X12Y66", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y66": "SLICEM", + "SLICE_X17Y66": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 138, + "segment": "SEG_CLBLM_L_X12Y67", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y67": "SLICEM", + "SLICE_X17Y67": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 137, + "segment": "SEG_CLBLM_L_X12Y68", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y68": "SLICEM", + "SLICE_X17Y68": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 136, + "segment": "SEG_CLBLM_L_X12Y69", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y69": "SLICEM", + "SLICE_X17Y69": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y7": { + "bits": {}, + "grid_x": 34, + "grid_y": 200, + "segment": "SEG_CLBLM_L_X12Y7", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y7": "SLICEM", + "SLICE_X17Y7": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 135, + "segment": "SEG_CLBLM_L_X12Y70", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y70": "SLICEM", + "SLICE_X17Y70": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 134, + "segment": "SEG_CLBLM_L_X12Y71", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y71": "SLICEM", + "SLICE_X17Y71": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 133, + "segment": "SEG_CLBLM_L_X12Y72", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y72": "SLICEM", + "SLICE_X17Y72": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 132, + "segment": "SEG_CLBLM_L_X12Y73", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y73": "SLICEM", + "SLICE_X17Y73": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 131, + "segment": "SEG_CLBLM_L_X12Y74", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y74": "SLICEM", + "SLICE_X17Y74": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 129, + "segment": "SEG_CLBLM_L_X12Y75", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y75": "SLICEM", + "SLICE_X17Y75": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 128, + "segment": "SEG_CLBLM_L_X12Y76", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y76": "SLICEM", + "SLICE_X17Y76": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 127, + "segment": "SEG_CLBLM_L_X12Y77", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y77": "SLICEM", + "SLICE_X17Y77": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 126, + "segment": "SEG_CLBLM_L_X12Y78", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y78": "SLICEM", + "SLICE_X17Y78": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 125, + "segment": "SEG_CLBLM_L_X12Y79", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y79": "SLICEM", + "SLICE_X17Y79": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y8": { + "bits": {}, + "grid_x": 34, + "grid_y": 199, + "segment": "SEG_CLBLM_L_X12Y8", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y8": "SLICEM", + "SLICE_X17Y8": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 124, + "segment": "SEG_CLBLM_L_X12Y80", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y80": "SLICEM", + "SLICE_X17Y80": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 123, + "segment": "SEG_CLBLM_L_X12Y81", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y81": "SLICEM", + "SLICE_X17Y81": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 122, + "segment": "SEG_CLBLM_L_X12Y82", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y82": "SLICEM", + "SLICE_X17Y82": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 121, + "segment": "SEG_CLBLM_L_X12Y83", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y83": "SLICEM", + "SLICE_X17Y83": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 120, + "segment": "SEG_CLBLM_L_X12Y84", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y84": "SLICEM", + "SLICE_X17Y84": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 119, + "segment": "SEG_CLBLM_L_X12Y85", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y85": "SLICEM", + "SLICE_X17Y85": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 118, + "segment": "SEG_CLBLM_L_X12Y86", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y86": "SLICEM", + "SLICE_X17Y86": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 117, + "segment": "SEG_CLBLM_L_X12Y87", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y87": "SLICEM", + "SLICE_X17Y87": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 116, + "segment": "SEG_CLBLM_L_X12Y88", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y88": "SLICEM", + "SLICE_X17Y88": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 115, + "segment": "SEG_CLBLM_L_X12Y89", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y89": "SLICEM", + "SLICE_X17Y89": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y9": { + "bits": {}, + "grid_x": 34, + "grid_y": 198, + "segment": "SEG_CLBLM_L_X12Y9", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y9": "SLICEM", + "SLICE_X17Y9": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 114, + "segment": "SEG_CLBLM_L_X12Y90", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y90": "SLICEM", + "SLICE_X17Y90": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 113, + "segment": "SEG_CLBLM_L_X12Y91", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y91": "SLICEM", + "SLICE_X17Y91": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 112, + "segment": "SEG_CLBLM_L_X12Y92", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y92": "SLICEM", + "SLICE_X17Y92": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 111, + "segment": "SEG_CLBLM_L_X12Y93", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y93": "SLICEM", + "SLICE_X17Y93": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 110, + "segment": "SEG_CLBLM_L_X12Y94", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y94": "SLICEM", + "SLICE_X17Y94": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 109, + "segment": "SEG_CLBLM_L_X12Y95", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y95": "SLICEM", + "SLICE_X17Y95": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 108, + "segment": "SEG_CLBLM_L_X12Y96", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y96": "SLICEM", + "SLICE_X17Y96": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 107, + "segment": "SEG_CLBLM_L_X12Y97", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y97": "SLICEM", + "SLICE_X17Y97": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 106, + "segment": "SEG_CLBLM_L_X12Y98", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y98": "SLICEM", + "SLICE_X17Y98": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X12Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 36, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 34, + "grid_y": 105, + "segment": "SEG_CLBLM_L_X12Y99", + "segment_type": "clblm_l", + "sites": { + "SLICE_X16Y99": "SLICEM", + "SLICE_X17Y99": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y0": { + "bits": {}, + "grid_x": 44, + "grid_y": 207, + "segment": "SEG_CLBLM_L_X16Y0", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y0": "SLICEM", + "SLICE_X23Y0": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y1": { + "bits": {}, + "grid_x": 44, + "grid_y": 206, + "segment": "SEG_CLBLM_L_X16Y1", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y1": "SLICEM", + "SLICE_X23Y1": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y10": { + "bits": {}, + "grid_x": 44, + "grid_y": 197, + "segment": "SEG_CLBLM_L_X16Y10", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y10": "SLICEM", + "SLICE_X23Y10": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y100": { + "bits": {}, + "grid_x": 44, + "grid_y": 103, + "segment": "SEG_CLBLM_L_X16Y100", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y100": "SLICEM", + "SLICE_X23Y100": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y101": { + "bits": {}, + "grid_x": 44, + "grid_y": 102, + "segment": "SEG_CLBLM_L_X16Y101", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y101": "SLICEM", + "SLICE_X23Y101": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y102": { + "bits": {}, + "grid_x": 44, + "grid_y": 101, + "segment": "SEG_CLBLM_L_X16Y102", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y102": "SLICEM", + "SLICE_X23Y102": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y103": { + "bits": {}, + "grid_x": 44, + "grid_y": 100, + "segment": "SEG_CLBLM_L_X16Y103", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y103": "SLICEM", + "SLICE_X23Y103": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y104": { + "bits": {}, + "grid_x": 44, + "grid_y": 99, + "segment": "SEG_CLBLM_L_X16Y104", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y104": "SLICEM", + "SLICE_X23Y104": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y105": { + "bits": {}, + "grid_x": 44, + "grid_y": 98, + "segment": "SEG_CLBLM_L_X16Y105", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y105": "SLICEM", + "SLICE_X23Y105": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y106": { + "bits": {}, + "grid_x": 44, + "grid_y": 97, + "segment": "SEG_CLBLM_L_X16Y106", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y106": "SLICEM", + "SLICE_X23Y106": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y107": { + "bits": {}, + "grid_x": 44, + "grid_y": 96, + "segment": "SEG_CLBLM_L_X16Y107", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y107": "SLICEM", + "SLICE_X23Y107": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y108": { + "bits": {}, + "grid_x": 44, + "grid_y": 95, + "segment": "SEG_CLBLM_L_X16Y108", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y108": "SLICEM", + "SLICE_X23Y108": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y109": { + "bits": {}, + "grid_x": 44, + "grid_y": 94, + "segment": "SEG_CLBLM_L_X16Y109", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y109": "SLICEM", + "SLICE_X23Y109": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y11": { + "bits": {}, + "grid_x": 44, + "grid_y": 196, + "segment": "SEG_CLBLM_L_X16Y11", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y11": "SLICEM", + "SLICE_X23Y11": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y110": { + "bits": {}, + "grid_x": 44, + "grid_y": 93, + "segment": "SEG_CLBLM_L_X16Y110", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y110": "SLICEM", + "SLICE_X23Y110": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y111": { + "bits": {}, + "grid_x": 44, + "grid_y": 92, + "segment": "SEG_CLBLM_L_X16Y111", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y111": "SLICEM", + "SLICE_X23Y111": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y112": { + "bits": {}, + "grid_x": 44, + "grid_y": 91, + "segment": "SEG_CLBLM_L_X16Y112", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y112": "SLICEM", + "SLICE_X23Y112": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y113": { + "bits": {}, + "grid_x": 44, + "grid_y": 90, + "segment": "SEG_CLBLM_L_X16Y113", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y113": "SLICEM", + "SLICE_X23Y113": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y114": { + "bits": {}, + "grid_x": 44, + "grid_y": 89, + "segment": "SEG_CLBLM_L_X16Y114", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y114": "SLICEM", + "SLICE_X23Y114": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y115": { + "bits": {}, + "grid_x": 44, + "grid_y": 88, + "segment": "SEG_CLBLM_L_X16Y115", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y115": "SLICEM", + "SLICE_X23Y115": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y116": { + "bits": {}, + "grid_x": 44, + "grid_y": 87, + "segment": "SEG_CLBLM_L_X16Y116", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y116": "SLICEM", + "SLICE_X23Y116": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y117": { + "bits": {}, + "grid_x": 44, + "grid_y": 86, + "segment": "SEG_CLBLM_L_X16Y117", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y117": "SLICEM", + "SLICE_X23Y117": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y118": { + "bits": {}, + "grid_x": 44, + "grid_y": 85, + "segment": "SEG_CLBLM_L_X16Y118", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y118": "SLICEM", + "SLICE_X23Y118": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y119": { + "bits": {}, + "grid_x": 44, + "grid_y": 84, + "segment": "SEG_CLBLM_L_X16Y119", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y119": "SLICEM", + "SLICE_X23Y119": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y12": { + "bits": {}, + "grid_x": 44, + "grid_y": 195, + "segment": "SEG_CLBLM_L_X16Y12", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y12": "SLICEM", + "SLICE_X23Y12": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y120": { + "bits": {}, + "grid_x": 44, + "grid_y": 83, + "segment": "SEG_CLBLM_L_X16Y120", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y120": "SLICEM", + "SLICE_X23Y120": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y121": { + "bits": {}, + "grid_x": 44, + "grid_y": 82, + "segment": "SEG_CLBLM_L_X16Y121", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y121": "SLICEM", + "SLICE_X23Y121": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y122": { + "bits": {}, + "grid_x": 44, + "grid_y": 81, + "segment": "SEG_CLBLM_L_X16Y122", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y122": "SLICEM", + "SLICE_X23Y122": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y123": { + "bits": {}, + "grid_x": 44, + "grid_y": 80, + "segment": "SEG_CLBLM_L_X16Y123", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y123": "SLICEM", + "SLICE_X23Y123": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y124": { + "bits": {}, + "grid_x": 44, + "grid_y": 79, + "segment": "SEG_CLBLM_L_X16Y124", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y124": "SLICEM", + "SLICE_X23Y124": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y125": { + "bits": {}, + "grid_x": 44, + "grid_y": 77, + "segment": "SEG_CLBLM_L_X16Y125", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y125": "SLICEM", + "SLICE_X23Y125": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y126": { + "bits": {}, + "grid_x": 44, + "grid_y": 76, + "segment": "SEG_CLBLM_L_X16Y126", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y126": "SLICEM", + "SLICE_X23Y126": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y127": { + "bits": {}, + "grid_x": 44, + "grid_y": 75, + "segment": "SEG_CLBLM_L_X16Y127", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y127": "SLICEM", + "SLICE_X23Y127": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y128": { + "bits": {}, + "grid_x": 44, + "grid_y": 74, + "segment": "SEG_CLBLM_L_X16Y128", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y128": "SLICEM", + "SLICE_X23Y128": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y129": { + "bits": {}, + "grid_x": 44, + "grid_y": 73, + "segment": "SEG_CLBLM_L_X16Y129", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y129": "SLICEM", + "SLICE_X23Y129": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y13": { + "bits": {}, + "grid_x": 44, + "grid_y": 194, + "segment": "SEG_CLBLM_L_X16Y13", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y13": "SLICEM", + "SLICE_X23Y13": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y130": { + "bits": {}, + "grid_x": 44, + "grid_y": 72, + "segment": "SEG_CLBLM_L_X16Y130", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y130": "SLICEM", + "SLICE_X23Y130": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y131": { + "bits": {}, + "grid_x": 44, + "grid_y": 71, + "segment": "SEG_CLBLM_L_X16Y131", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y131": "SLICEM", + "SLICE_X23Y131": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y132": { + "bits": {}, + "grid_x": 44, + "grid_y": 70, + "segment": "SEG_CLBLM_L_X16Y132", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y132": "SLICEM", + "SLICE_X23Y132": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y133": { + "bits": {}, + "grid_x": 44, + "grid_y": 69, + "segment": "SEG_CLBLM_L_X16Y133", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y133": "SLICEM", + "SLICE_X23Y133": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y134": { + "bits": {}, + "grid_x": 44, + "grid_y": 68, + "segment": "SEG_CLBLM_L_X16Y134", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y134": "SLICEM", + "SLICE_X23Y134": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y135": { + "bits": {}, + "grid_x": 44, + "grid_y": 67, + "segment": "SEG_CLBLM_L_X16Y135", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y135": "SLICEM", + "SLICE_X23Y135": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y136": { + "bits": {}, + "grid_x": 44, + "grid_y": 66, + "segment": "SEG_CLBLM_L_X16Y136", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y136": "SLICEM", + "SLICE_X23Y136": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y137": { + "bits": {}, + "grid_x": 44, + "grid_y": 65, + "segment": "SEG_CLBLM_L_X16Y137", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y137": "SLICEM", + "SLICE_X23Y137": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y138": { + "bits": {}, + "grid_x": 44, + "grid_y": 64, + "segment": "SEG_CLBLM_L_X16Y138", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y138": "SLICEM", + "SLICE_X23Y138": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y139": { + "bits": {}, + "grid_x": 44, + "grid_y": 63, + "segment": "SEG_CLBLM_L_X16Y139", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y139": "SLICEM", + "SLICE_X23Y139": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y14": { + "bits": {}, + "grid_x": 44, + "grid_y": 193, + "segment": "SEG_CLBLM_L_X16Y14", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y14": "SLICEM", + "SLICE_X23Y14": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y140": { + "bits": {}, + "grid_x": 44, + "grid_y": 62, + "segment": "SEG_CLBLM_L_X16Y140", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y140": "SLICEM", + "SLICE_X23Y140": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y141": { + "bits": {}, + "grid_x": 44, + "grid_y": 61, + "segment": "SEG_CLBLM_L_X16Y141", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y141": "SLICEM", + "SLICE_X23Y141": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y142": { + "bits": {}, + "grid_x": 44, + "grid_y": 60, + "segment": "SEG_CLBLM_L_X16Y142", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y142": "SLICEM", + "SLICE_X23Y142": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y143": { + "bits": {}, + "grid_x": 44, + "grid_y": 59, + "segment": "SEG_CLBLM_L_X16Y143", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y143": "SLICEM", + "SLICE_X23Y143": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y144": { + "bits": {}, + "grid_x": 44, + "grid_y": 58, + "segment": "SEG_CLBLM_L_X16Y144", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y144": "SLICEM", + "SLICE_X23Y144": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y145": { + "bits": {}, + "grid_x": 44, + "grid_y": 57, + "segment": "SEG_CLBLM_L_X16Y145", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y145": "SLICEM", + "SLICE_X23Y145": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y146": { + "bits": {}, + "grid_x": 44, + "grid_y": 56, + "segment": "SEG_CLBLM_L_X16Y146", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y146": "SLICEM", + "SLICE_X23Y146": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y147": { + "bits": {}, + "grid_x": 44, + "grid_y": 55, + "segment": "SEG_CLBLM_L_X16Y147", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y147": "SLICEM", + "SLICE_X23Y147": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y148": { + "bits": {}, + "grid_x": 44, + "grid_y": 54, + "segment": "SEG_CLBLM_L_X16Y148", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y148": "SLICEM", + "SLICE_X23Y148": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y149": { + "bits": {}, + "grid_x": 44, + "grid_y": 53, + "segment": "SEG_CLBLM_L_X16Y149", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y149": "SLICEM", + "SLICE_X23Y149": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y15": { + "bits": {}, + "grid_x": 44, + "grid_y": 192, + "segment": "SEG_CLBLM_L_X16Y15", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y15": "SLICEM", + "SLICE_X23Y15": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y150": { + "bits": {}, + "grid_x": 44, + "grid_y": 51, + "segment": "SEG_CLBLM_L_X16Y150", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y150": "SLICEM", + "SLICE_X23Y150": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y151": { + "bits": {}, + "grid_x": 44, + "grid_y": 50, + "segment": "SEG_CLBLM_L_X16Y151", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y151": "SLICEM", + "SLICE_X23Y151": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y152": { + "bits": {}, + "grid_x": 44, + "grid_y": 49, + "segment": "SEG_CLBLM_L_X16Y152", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y152": "SLICEM", + "SLICE_X23Y152": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y153": { + "bits": {}, + "grid_x": 44, + "grid_y": 48, + "segment": "SEG_CLBLM_L_X16Y153", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y153": "SLICEM", + "SLICE_X23Y153": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y154": { + "bits": {}, + "grid_x": 44, + "grid_y": 47, + "segment": "SEG_CLBLM_L_X16Y154", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y154": "SLICEM", + "SLICE_X23Y154": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y155": { + "bits": {}, + "grid_x": 44, + "grid_y": 46, + "segment": "SEG_CLBLM_L_X16Y155", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y155": "SLICEM", + "SLICE_X23Y155": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y156": { + "bits": {}, + "grid_x": 44, + "grid_y": 45, + "segment": "SEG_CLBLM_L_X16Y156", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y156": "SLICEM", + "SLICE_X23Y156": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y157": { + "bits": {}, + "grid_x": 44, + "grid_y": 44, + "segment": "SEG_CLBLM_L_X16Y157", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y157": "SLICEM", + "SLICE_X23Y157": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y158": { + "bits": {}, + "grid_x": 44, + "grid_y": 43, + "segment": "SEG_CLBLM_L_X16Y158", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y158": "SLICEM", + "SLICE_X23Y158": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y159": { + "bits": {}, + "grid_x": 44, + "grid_y": 42, + "segment": "SEG_CLBLM_L_X16Y159", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y159": "SLICEM", + "SLICE_X23Y159": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y16": { + "bits": {}, + "grid_x": 44, + "grid_y": 191, + "segment": "SEG_CLBLM_L_X16Y16", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y16": "SLICEM", + "SLICE_X23Y16": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y160": { + "bits": {}, + "grid_x": 44, + "grid_y": 41, + "segment": "SEG_CLBLM_L_X16Y160", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y160": "SLICEM", + "SLICE_X23Y160": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y161": { + "bits": {}, + "grid_x": 44, + "grid_y": 40, + "segment": "SEG_CLBLM_L_X16Y161", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y161": "SLICEM", + "SLICE_X23Y161": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y162": { + "bits": {}, + "grid_x": 44, + "grid_y": 39, + "segment": "SEG_CLBLM_L_X16Y162", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y162": "SLICEM", + "SLICE_X23Y162": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y163": { + "bits": {}, + "grid_x": 44, + "grid_y": 38, + "segment": "SEG_CLBLM_L_X16Y163", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y163": "SLICEM", + "SLICE_X23Y163": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y164": { + "bits": {}, + "grid_x": 44, + "grid_y": 37, + "segment": "SEG_CLBLM_L_X16Y164", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y164": "SLICEM", + "SLICE_X23Y164": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y165": { + "bits": {}, + "grid_x": 44, + "grid_y": 36, + "segment": "SEG_CLBLM_L_X16Y165", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y165": "SLICEM", + "SLICE_X23Y165": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y166": { + "bits": {}, + "grid_x": 44, + "grid_y": 35, + "segment": "SEG_CLBLM_L_X16Y166", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y166": "SLICEM", + "SLICE_X23Y166": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y167": { + "bits": {}, + "grid_x": 44, + "grid_y": 34, + "segment": "SEG_CLBLM_L_X16Y167", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y167": "SLICEM", + "SLICE_X23Y167": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y168": { + "bits": {}, + "grid_x": 44, + "grid_y": 33, + "segment": "SEG_CLBLM_L_X16Y168", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y168": "SLICEM", + "SLICE_X23Y168": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y169": { + "bits": {}, + "grid_x": 44, + "grid_y": 32, + "segment": "SEG_CLBLM_L_X16Y169", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y169": "SLICEM", + "SLICE_X23Y169": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y17": { + "bits": {}, + "grid_x": 44, + "grid_y": 190, + "segment": "SEG_CLBLM_L_X16Y17", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y17": "SLICEM", + "SLICE_X23Y17": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y170": { + "bits": {}, + "grid_x": 44, + "grid_y": 31, + "segment": "SEG_CLBLM_L_X16Y170", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y170": "SLICEM", + "SLICE_X23Y170": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y171": { + "bits": {}, + "grid_x": 44, + "grid_y": 30, + "segment": "SEG_CLBLM_L_X16Y171", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y171": "SLICEM", + "SLICE_X23Y171": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y172": { + "bits": {}, + "grid_x": 44, + "grid_y": 29, + "segment": "SEG_CLBLM_L_X16Y172", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y172": "SLICEM", + "SLICE_X23Y172": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y173": { + "bits": {}, + "grid_x": 44, + "grid_y": 28, + "segment": "SEG_CLBLM_L_X16Y173", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y173": "SLICEM", + "SLICE_X23Y173": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y174": { + "bits": {}, + "grid_x": 44, + "grid_y": 27, + "segment": "SEG_CLBLM_L_X16Y174", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y174": "SLICEM", + "SLICE_X23Y174": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y175": { + "bits": {}, + "grid_x": 44, + "grid_y": 25, + "segment": "SEG_CLBLM_L_X16Y175", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y175": "SLICEM", + "SLICE_X23Y175": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y176": { + "bits": {}, + "grid_x": 44, + "grid_y": 24, + "segment": "SEG_CLBLM_L_X16Y176", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y176": "SLICEM", + "SLICE_X23Y176": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y177": { + "bits": {}, + "grid_x": 44, + "grid_y": 23, + "segment": "SEG_CLBLM_L_X16Y177", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y177": "SLICEM", + "SLICE_X23Y177": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y178": { + "bits": {}, + "grid_x": 44, + "grid_y": 22, + "segment": "SEG_CLBLM_L_X16Y178", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y178": "SLICEM", + "SLICE_X23Y178": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y179": { + "bits": {}, + "grid_x": 44, + "grid_y": 21, + "segment": "SEG_CLBLM_L_X16Y179", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y179": "SLICEM", + "SLICE_X23Y179": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y18": { + "bits": {}, + "grid_x": 44, + "grid_y": 189, + "segment": "SEG_CLBLM_L_X16Y18", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y18": "SLICEM", + "SLICE_X23Y18": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y180": { + "bits": {}, + "grid_x": 44, + "grid_y": 20, + "segment": "SEG_CLBLM_L_X16Y180", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y180": "SLICEM", + "SLICE_X23Y180": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y181": { + "bits": {}, + "grid_x": 44, + "grid_y": 19, + "segment": "SEG_CLBLM_L_X16Y181", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y181": "SLICEM", + "SLICE_X23Y181": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y182": { + "bits": {}, + "grid_x": 44, + "grid_y": 18, + "segment": "SEG_CLBLM_L_X16Y182", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y182": "SLICEM", + "SLICE_X23Y182": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y183": { + "bits": {}, + "grid_x": 44, + "grid_y": 17, + "segment": "SEG_CLBLM_L_X16Y183", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y183": "SLICEM", + "SLICE_X23Y183": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y184": { + "bits": {}, + "grid_x": 44, + "grid_y": 16, + "segment": "SEG_CLBLM_L_X16Y184", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y184": "SLICEM", + "SLICE_X23Y184": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y185": { + "bits": {}, + "grid_x": 44, + "grid_y": 15, + "segment": "SEG_CLBLM_L_X16Y185", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y185": "SLICEM", + "SLICE_X23Y185": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y186": { + "bits": {}, + "grid_x": 44, + "grid_y": 14, + "segment": "SEG_CLBLM_L_X16Y186", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y186": "SLICEM", + "SLICE_X23Y186": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y187": { + "bits": {}, + "grid_x": 44, + "grid_y": 13, + "segment": "SEG_CLBLM_L_X16Y187", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y187": "SLICEM", + "SLICE_X23Y187": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y188": { + "bits": {}, + "grid_x": 44, + "grid_y": 12, + "segment": "SEG_CLBLM_L_X16Y188", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y188": "SLICEM", + "SLICE_X23Y188": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y189": { + "bits": {}, + "grid_x": 44, + "grid_y": 11, + "segment": "SEG_CLBLM_L_X16Y189", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y189": "SLICEM", + "SLICE_X23Y189": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y19": { + "bits": {}, + "grid_x": 44, + "grid_y": 188, + "segment": "SEG_CLBLM_L_X16Y19", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y19": "SLICEM", + "SLICE_X23Y19": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y190": { + "bits": {}, + "grid_x": 44, + "grid_y": 10, + "segment": "SEG_CLBLM_L_X16Y190", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y190": "SLICEM", + "SLICE_X23Y190": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y191": { + "bits": {}, + "grid_x": 44, + "grid_y": 9, + "segment": "SEG_CLBLM_L_X16Y191", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y191": "SLICEM", + "SLICE_X23Y191": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y192": { + "bits": {}, + "grid_x": 44, + "grid_y": 8, + "segment": "SEG_CLBLM_L_X16Y192", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y192": "SLICEM", + "SLICE_X23Y192": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y193": { + "bits": {}, + "grid_x": 44, + "grid_y": 7, + "segment": "SEG_CLBLM_L_X16Y193", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y193": "SLICEM", + "SLICE_X23Y193": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y194": { + "bits": {}, + "grid_x": 44, + "grid_y": 6, + "segment": "SEG_CLBLM_L_X16Y194", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y194": "SLICEM", + "SLICE_X23Y194": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y195": { + "bits": {}, + "grid_x": 44, + "grid_y": 5, + "segment": "SEG_CLBLM_L_X16Y195", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y195": "SLICEM", + "SLICE_X23Y195": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y196": { + "bits": {}, + "grid_x": 44, + "grid_y": 4, + "segment": "SEG_CLBLM_L_X16Y196", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y196": "SLICEM", + "SLICE_X23Y196": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y197": { + "bits": {}, + "grid_x": 44, + "grid_y": 3, + "segment": "SEG_CLBLM_L_X16Y197", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y197": "SLICEM", + "SLICE_X23Y197": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y198": { + "bits": {}, + "grid_x": 44, + "grid_y": 2, + "segment": "SEG_CLBLM_L_X16Y198", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y198": "SLICEM", + "SLICE_X23Y198": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y199": { + "bits": {}, + "grid_x": 44, + "grid_y": 1, + "segment": "SEG_CLBLM_L_X16Y199", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y199": "SLICEM", + "SLICE_X23Y199": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y2": { + "bits": {}, + "grid_x": 44, + "grid_y": 205, + "segment": "SEG_CLBLM_L_X16Y2", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y2": "SLICEM", + "SLICE_X23Y2": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y20": { + "bits": {}, + "grid_x": 44, + "grid_y": 187, + "segment": "SEG_CLBLM_L_X16Y20", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y20": "SLICEM", + "SLICE_X23Y20": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y21": { + "bits": {}, + "grid_x": 44, + "grid_y": 186, + "segment": "SEG_CLBLM_L_X16Y21", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y21": "SLICEM", + "SLICE_X23Y21": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y22": { + "bits": {}, + "grid_x": 44, + "grid_y": 185, + "segment": "SEG_CLBLM_L_X16Y22", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y22": "SLICEM", + "SLICE_X23Y22": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y23": { + "bits": {}, + "grid_x": 44, + "grid_y": 184, + "segment": "SEG_CLBLM_L_X16Y23", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y23": "SLICEM", + "SLICE_X23Y23": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y24": { + "bits": {}, + "grid_x": 44, + "grid_y": 183, + "segment": "SEG_CLBLM_L_X16Y24", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y24": "SLICEM", + "SLICE_X23Y24": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y25": { + "bits": {}, + "grid_x": 44, + "grid_y": 181, + "segment": "SEG_CLBLM_L_X16Y25", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y25": "SLICEM", + "SLICE_X23Y25": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y26": { + "bits": {}, + "grid_x": 44, + "grid_y": 180, + "segment": "SEG_CLBLM_L_X16Y26", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y26": "SLICEM", + "SLICE_X23Y26": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y27": { + "bits": {}, + "grid_x": 44, + "grid_y": 179, + "segment": "SEG_CLBLM_L_X16Y27", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y27": "SLICEM", + "SLICE_X23Y27": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y28": { + "bits": {}, + "grid_x": 44, + "grid_y": 178, + "segment": "SEG_CLBLM_L_X16Y28", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y28": "SLICEM", + "SLICE_X23Y28": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y29": { + "bits": {}, + "grid_x": 44, + "grid_y": 177, + "segment": "SEG_CLBLM_L_X16Y29", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y29": "SLICEM", + "SLICE_X23Y29": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y3": { + "bits": {}, + "grid_x": 44, + "grid_y": 204, + "segment": "SEG_CLBLM_L_X16Y3", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y3": "SLICEM", + "SLICE_X23Y3": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y30": { + "bits": {}, + "grid_x": 44, + "grid_y": 176, + "segment": "SEG_CLBLM_L_X16Y30", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y30": "SLICEM", + "SLICE_X23Y30": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y31": { + "bits": {}, + "grid_x": 44, + "grid_y": 175, + "segment": "SEG_CLBLM_L_X16Y31", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y31": "SLICEM", + "SLICE_X23Y31": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y32": { + "bits": {}, + "grid_x": 44, + "grid_y": 174, + "segment": "SEG_CLBLM_L_X16Y32", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y32": "SLICEM", + "SLICE_X23Y32": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y33": { + "bits": {}, + "grid_x": 44, + "grid_y": 173, + "segment": "SEG_CLBLM_L_X16Y33", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y33": "SLICEM", + "SLICE_X23Y33": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y34": { + "bits": {}, + "grid_x": 44, + "grid_y": 172, + "segment": "SEG_CLBLM_L_X16Y34", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y34": "SLICEM", + "SLICE_X23Y34": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y35": { + "bits": {}, + "grid_x": 44, + "grid_y": 171, + "segment": "SEG_CLBLM_L_X16Y35", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y35": "SLICEM", + "SLICE_X23Y35": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y36": { + "bits": {}, + "grid_x": 44, + "grid_y": 170, + "segment": "SEG_CLBLM_L_X16Y36", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y36": "SLICEM", + "SLICE_X23Y36": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y37": { + "bits": {}, + "grid_x": 44, + "grid_y": 169, + "segment": "SEG_CLBLM_L_X16Y37", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y37": "SLICEM", + "SLICE_X23Y37": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y38": { + "bits": {}, + "grid_x": 44, + "grid_y": 168, + "segment": "SEG_CLBLM_L_X16Y38", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y38": "SLICEM", + "SLICE_X23Y38": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y39": { + "bits": {}, + "grid_x": 44, + "grid_y": 167, + "segment": "SEG_CLBLM_L_X16Y39", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y39": "SLICEM", + "SLICE_X23Y39": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y4": { + "bits": {}, + "grid_x": 44, + "grid_y": 203, + "segment": "SEG_CLBLM_L_X16Y4", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y4": "SLICEM", + "SLICE_X23Y4": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y40": { + "bits": {}, + "grid_x": 44, + "grid_y": 166, + "segment": "SEG_CLBLM_L_X16Y40", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y40": "SLICEM", + "SLICE_X23Y40": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y41": { + "bits": {}, + "grid_x": 44, + "grid_y": 165, + "segment": "SEG_CLBLM_L_X16Y41", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y41": "SLICEM", + "SLICE_X23Y41": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y42": { + "bits": {}, + "grid_x": 44, + "grid_y": 164, + "segment": "SEG_CLBLM_L_X16Y42", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y42": "SLICEM", + "SLICE_X23Y42": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y43": { + "bits": {}, + "grid_x": 44, + "grid_y": 163, + "segment": "SEG_CLBLM_L_X16Y43", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y43": "SLICEM", + "SLICE_X23Y43": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y44": { + "bits": {}, + "grid_x": 44, + "grid_y": 162, + "segment": "SEG_CLBLM_L_X16Y44", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y44": "SLICEM", + "SLICE_X23Y44": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y45": { + "bits": {}, + "grid_x": 44, + "grid_y": 161, + "segment": "SEG_CLBLM_L_X16Y45", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y45": "SLICEM", + "SLICE_X23Y45": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y46": { + "bits": {}, + "grid_x": 44, + "grid_y": 160, + "segment": "SEG_CLBLM_L_X16Y46", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y46": "SLICEM", + "SLICE_X23Y46": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y47": { + "bits": {}, + "grid_x": 44, + "grid_y": 159, + "segment": "SEG_CLBLM_L_X16Y47", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y47": "SLICEM", + "SLICE_X23Y47": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y48": { + "bits": {}, + "grid_x": 44, + "grid_y": 158, + "segment": "SEG_CLBLM_L_X16Y48", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y48": "SLICEM", + "SLICE_X23Y48": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y49": { + "bits": {}, + "grid_x": 44, + "grid_y": 157, + "segment": "SEG_CLBLM_L_X16Y49", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y49": "SLICEM", + "SLICE_X23Y49": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y5": { + "bits": {}, + "grid_x": 44, + "grid_y": 202, + "segment": "SEG_CLBLM_L_X16Y5", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y5": "SLICEM", + "SLICE_X23Y5": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y50": { + "bits": {}, + "grid_x": 44, + "grid_y": 155, + "segment": "SEG_CLBLM_L_X16Y50", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y50": "SLICEM", + "SLICE_X23Y50": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y51": { + "bits": {}, + "grid_x": 44, + "grid_y": 154, + "segment": "SEG_CLBLM_L_X16Y51", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y51": "SLICEM", + "SLICE_X23Y51": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y52": { + "bits": {}, + "grid_x": 44, + "grid_y": 153, + "segment": "SEG_CLBLM_L_X16Y52", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y52": "SLICEM", + "SLICE_X23Y52": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y53": { + "bits": {}, + "grid_x": 44, + "grid_y": 152, + "segment": "SEG_CLBLM_L_X16Y53", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y53": "SLICEM", + "SLICE_X23Y53": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y54": { + "bits": {}, + "grid_x": 44, + "grid_y": 151, + "segment": "SEG_CLBLM_L_X16Y54", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y54": "SLICEM", + "SLICE_X23Y54": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y55": { + "bits": {}, + "grid_x": 44, + "grid_y": 150, + "segment": "SEG_CLBLM_L_X16Y55", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y55": "SLICEM", + "SLICE_X23Y55": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y56": { + "bits": {}, + "grid_x": 44, + "grid_y": 149, + "segment": "SEG_CLBLM_L_X16Y56", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y56": "SLICEM", + "SLICE_X23Y56": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y57": { + "bits": {}, + "grid_x": 44, + "grid_y": 148, + "segment": "SEG_CLBLM_L_X16Y57", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y57": "SLICEM", + "SLICE_X23Y57": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y58": { + "bits": {}, + "grid_x": 44, + "grid_y": 147, + "segment": "SEG_CLBLM_L_X16Y58", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y58": "SLICEM", + "SLICE_X23Y58": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y59": { + "bits": {}, + "grid_x": 44, + "grid_y": 146, + "segment": "SEG_CLBLM_L_X16Y59", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y59": "SLICEM", + "SLICE_X23Y59": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y6": { + "bits": {}, + "grid_x": 44, + "grid_y": 201, + "segment": "SEG_CLBLM_L_X16Y6", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y6": "SLICEM", + "SLICE_X23Y6": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y60": { + "bits": {}, + "grid_x": 44, + "grid_y": 145, + "segment": "SEG_CLBLM_L_X16Y60", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y60": "SLICEM", + "SLICE_X23Y60": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y61": { + "bits": {}, + "grid_x": 44, + "grid_y": 144, + "segment": "SEG_CLBLM_L_X16Y61", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y61": "SLICEM", + "SLICE_X23Y61": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y62": { + "bits": {}, + "grid_x": 44, + "grid_y": 143, + "segment": "SEG_CLBLM_L_X16Y62", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y62": "SLICEM", + "SLICE_X23Y62": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y63": { + "bits": {}, + "grid_x": 44, + "grid_y": 142, + "segment": "SEG_CLBLM_L_X16Y63", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y63": "SLICEM", + "SLICE_X23Y63": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y64": { + "bits": {}, + "grid_x": 44, + "grid_y": 141, + "segment": "SEG_CLBLM_L_X16Y64", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y64": "SLICEM", + "SLICE_X23Y64": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y65": { + "bits": {}, + "grid_x": 44, + "grid_y": 140, + "segment": "SEG_CLBLM_L_X16Y65", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y65": "SLICEM", + "SLICE_X23Y65": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y66": { + "bits": {}, + "grid_x": 44, + "grid_y": 139, + "segment": "SEG_CLBLM_L_X16Y66", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y66": "SLICEM", + "SLICE_X23Y66": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y67": { + "bits": {}, + "grid_x": 44, + "grid_y": 138, + "segment": "SEG_CLBLM_L_X16Y67", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y67": "SLICEM", + "SLICE_X23Y67": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y68": { + "bits": {}, + "grid_x": 44, + "grid_y": 137, + "segment": "SEG_CLBLM_L_X16Y68", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y68": "SLICEM", + "SLICE_X23Y68": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y69": { + "bits": {}, + "grid_x": 44, + "grid_y": 136, + "segment": "SEG_CLBLM_L_X16Y69", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y69": "SLICEM", + "SLICE_X23Y69": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y7": { + "bits": {}, + "grid_x": 44, + "grid_y": 200, + "segment": "SEG_CLBLM_L_X16Y7", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y7": "SLICEM", + "SLICE_X23Y7": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y70": { + "bits": {}, + "grid_x": 44, + "grid_y": 135, + "segment": "SEG_CLBLM_L_X16Y70", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y70": "SLICEM", + "SLICE_X23Y70": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y71": { + "bits": {}, + "grid_x": 44, + "grid_y": 134, + "segment": "SEG_CLBLM_L_X16Y71", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y71": "SLICEM", + "SLICE_X23Y71": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y72": { + "bits": {}, + "grid_x": 44, + "grid_y": 133, + "segment": "SEG_CLBLM_L_X16Y72", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y72": "SLICEM", + "SLICE_X23Y72": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y73": { + "bits": {}, + "grid_x": 44, + "grid_y": 132, + "segment": "SEG_CLBLM_L_X16Y73", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y73": "SLICEM", + "SLICE_X23Y73": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y74": { + "bits": {}, + "grid_x": 44, + "grid_y": 131, + "segment": "SEG_CLBLM_L_X16Y74", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y74": "SLICEM", + "SLICE_X23Y74": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y75": { + "bits": {}, + "grid_x": 44, + "grid_y": 129, + "segment": "SEG_CLBLM_L_X16Y75", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y75": "SLICEM", + "SLICE_X23Y75": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y76": { + "bits": {}, + "grid_x": 44, + "grid_y": 128, + "segment": "SEG_CLBLM_L_X16Y76", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y76": "SLICEM", + "SLICE_X23Y76": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y77": { + "bits": {}, + "grid_x": 44, + "grid_y": 127, + "segment": "SEG_CLBLM_L_X16Y77", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y77": "SLICEM", + "SLICE_X23Y77": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y78": { + "bits": {}, + "grid_x": 44, + "grid_y": 126, + "segment": "SEG_CLBLM_L_X16Y78", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y78": "SLICEM", + "SLICE_X23Y78": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y79": { + "bits": {}, + "grid_x": 44, + "grid_y": 125, + "segment": "SEG_CLBLM_L_X16Y79", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y79": "SLICEM", + "SLICE_X23Y79": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y8": { + "bits": {}, + "grid_x": 44, + "grid_y": 199, + "segment": "SEG_CLBLM_L_X16Y8", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y8": "SLICEM", + "SLICE_X23Y8": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y80": { + "bits": {}, + "grid_x": 44, + "grid_y": 124, + "segment": "SEG_CLBLM_L_X16Y80", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y80": "SLICEM", + "SLICE_X23Y80": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y81": { + "bits": {}, + "grid_x": 44, + "grid_y": 123, + "segment": "SEG_CLBLM_L_X16Y81", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y81": "SLICEM", + "SLICE_X23Y81": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y82": { + "bits": {}, + "grid_x": 44, + "grid_y": 122, + "segment": "SEG_CLBLM_L_X16Y82", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y82": "SLICEM", + "SLICE_X23Y82": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y83": { + "bits": {}, + "grid_x": 44, + "grid_y": 121, + "segment": "SEG_CLBLM_L_X16Y83", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y83": "SLICEM", + "SLICE_X23Y83": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y84": { + "bits": {}, + "grid_x": 44, + "grid_y": 120, + "segment": "SEG_CLBLM_L_X16Y84", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y84": "SLICEM", + "SLICE_X23Y84": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y85": { + "bits": {}, + "grid_x": 44, + "grid_y": 119, + "segment": "SEG_CLBLM_L_X16Y85", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y85": "SLICEM", + "SLICE_X23Y85": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y86": { + "bits": {}, + "grid_x": 44, + "grid_y": 118, + "segment": "SEG_CLBLM_L_X16Y86", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y86": "SLICEM", + "SLICE_X23Y86": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y87": { + "bits": {}, + "grid_x": 44, + "grid_y": 117, + "segment": "SEG_CLBLM_L_X16Y87", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y87": "SLICEM", + "SLICE_X23Y87": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y88": { + "bits": {}, + "grid_x": 44, + "grid_y": 116, + "segment": "SEG_CLBLM_L_X16Y88", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y88": "SLICEM", + "SLICE_X23Y88": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y89": { + "bits": {}, + "grid_x": 44, + "grid_y": 115, + "segment": "SEG_CLBLM_L_X16Y89", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y89": "SLICEM", + "SLICE_X23Y89": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y9": { + "bits": {}, + "grid_x": 44, + "grid_y": 198, + "segment": "SEG_CLBLM_L_X16Y9", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y9": "SLICEM", + "SLICE_X23Y9": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y90": { + "bits": {}, + "grid_x": 44, + "grid_y": 114, + "segment": "SEG_CLBLM_L_X16Y90", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y90": "SLICEM", + "SLICE_X23Y90": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y91": { + "bits": {}, + "grid_x": 44, + "grid_y": 113, + "segment": "SEG_CLBLM_L_X16Y91", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y91": "SLICEM", + "SLICE_X23Y91": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y92": { + "bits": {}, + "grid_x": 44, + "grid_y": 112, + "segment": "SEG_CLBLM_L_X16Y92", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y92": "SLICEM", + "SLICE_X23Y92": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y93": { + "bits": {}, + "grid_x": 44, + "grid_y": 111, + "segment": "SEG_CLBLM_L_X16Y93", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y93": "SLICEM", + "SLICE_X23Y93": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y94": { + "bits": {}, + "grid_x": 44, + "grid_y": 110, + "segment": "SEG_CLBLM_L_X16Y94", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y94": "SLICEM", + "SLICE_X23Y94": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y95": { + "bits": {}, + "grid_x": 44, + "grid_y": 109, + "segment": "SEG_CLBLM_L_X16Y95", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y95": "SLICEM", + "SLICE_X23Y95": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y96": { + "bits": {}, + "grid_x": 44, + "grid_y": 108, + "segment": "SEG_CLBLM_L_X16Y96", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y96": "SLICEM", + "SLICE_X23Y96": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y97": { + "bits": {}, + "grid_x": 44, + "grid_y": 107, + "segment": "SEG_CLBLM_L_X16Y97", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y97": "SLICEM", + "SLICE_X23Y97": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y98": { + "bits": {}, + "grid_x": 44, + "grid_y": 106, + "segment": "SEG_CLBLM_L_X16Y98", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y98": "SLICEM", + "SLICE_X23Y98": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X16Y99": { + "bits": {}, + "grid_x": 44, + "grid_y": 105, + "segment": "SEG_CLBLM_L_X16Y99", + "segment_type": "clblm_l", + "sites": { + "SLICE_X22Y99": "SLICEM", + "SLICE_X23Y99": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y0": { + "bits": {}, + "grid_x": 83, + "grid_y": 207, + "segment": "SEG_CLBLM_L_X32Y0", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y0": "SLICEM", + "SLICE_X47Y0": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y1": { + "bits": {}, + "grid_x": 83, + "grid_y": 206, + "segment": "SEG_CLBLM_L_X32Y1", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y1": "SLICEM", + "SLICE_X47Y1": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y10": { + "bits": {}, + "grid_x": 83, + "grid_y": 197, + "segment": "SEG_CLBLM_L_X32Y10", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y10": "SLICEM", + "SLICE_X47Y10": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y100": { + "bits": {}, + "grid_x": 83, + "grid_y": 103, + "segment": "SEG_CLBLM_L_X32Y100", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y100": "SLICEM", + "SLICE_X47Y100": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y101": { + "bits": {}, + "grid_x": 83, + "grid_y": 102, + "segment": "SEG_CLBLM_L_X32Y101", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y101": "SLICEM", + "SLICE_X47Y101": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y102": { + "bits": {}, + "grid_x": 83, + "grid_y": 101, + "segment": "SEG_CLBLM_L_X32Y102", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y102": "SLICEM", + "SLICE_X47Y102": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y103": { + "bits": {}, + "grid_x": 83, + "grid_y": 100, + "segment": "SEG_CLBLM_L_X32Y103", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y103": "SLICEM", + "SLICE_X47Y103": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y104": { + "bits": {}, + "grid_x": 83, + "grid_y": 99, + "segment": "SEG_CLBLM_L_X32Y104", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y104": "SLICEM", + "SLICE_X47Y104": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y105": { + "bits": {}, + "grid_x": 83, + "grid_y": 98, + "segment": "SEG_CLBLM_L_X32Y105", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y105": "SLICEM", + "SLICE_X47Y105": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y106": { + "bits": {}, + "grid_x": 83, + "grid_y": 97, + "segment": "SEG_CLBLM_L_X32Y106", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y106": "SLICEM", + "SLICE_X47Y106": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y107": { + "bits": {}, + "grid_x": 83, + "grid_y": 96, + "segment": "SEG_CLBLM_L_X32Y107", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y107": "SLICEM", + "SLICE_X47Y107": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y108": { + "bits": {}, + "grid_x": 83, + "grid_y": 95, + "segment": "SEG_CLBLM_L_X32Y108", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y108": "SLICEM", + "SLICE_X47Y108": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y109": { + "bits": {}, + "grid_x": 83, + "grid_y": 94, + "segment": "SEG_CLBLM_L_X32Y109", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y109": "SLICEM", + "SLICE_X47Y109": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y11": { + "bits": {}, + "grid_x": 83, + "grid_y": 196, + "segment": "SEG_CLBLM_L_X32Y11", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y11": "SLICEM", + "SLICE_X47Y11": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y110": { + "bits": {}, + "grid_x": 83, + "grid_y": 93, + "segment": "SEG_CLBLM_L_X32Y110", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y110": "SLICEM", + "SLICE_X47Y110": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y111": { + "bits": {}, + "grid_x": 83, + "grid_y": 92, + "segment": "SEG_CLBLM_L_X32Y111", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y111": "SLICEM", + "SLICE_X47Y111": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y112": { + "bits": {}, + "grid_x": 83, + "grid_y": 91, + "segment": "SEG_CLBLM_L_X32Y112", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y112": "SLICEM", + "SLICE_X47Y112": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y113": { + "bits": {}, + "grid_x": 83, + "grid_y": 90, + "segment": "SEG_CLBLM_L_X32Y113", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y113": "SLICEM", + "SLICE_X47Y113": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y114": { + "bits": {}, + "grid_x": 83, + "grid_y": 89, + "segment": "SEG_CLBLM_L_X32Y114", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y114": "SLICEM", + "SLICE_X47Y114": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y115": { + "bits": {}, + "grid_x": 83, + "grid_y": 88, + "segment": "SEG_CLBLM_L_X32Y115", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y115": "SLICEM", + "SLICE_X47Y115": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y116": { + "bits": {}, + "grid_x": 83, + "grid_y": 87, + "segment": "SEG_CLBLM_L_X32Y116", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y116": "SLICEM", + "SLICE_X47Y116": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y117": { + "bits": {}, + "grid_x": 83, + "grid_y": 86, + "segment": "SEG_CLBLM_L_X32Y117", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y117": "SLICEM", + "SLICE_X47Y117": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y118": { + "bits": {}, + "grid_x": 83, + "grid_y": 85, + "segment": "SEG_CLBLM_L_X32Y118", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y118": "SLICEM", + "SLICE_X47Y118": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y119": { + "bits": {}, + "grid_x": 83, + "grid_y": 84, + "segment": "SEG_CLBLM_L_X32Y119", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y119": "SLICEM", + "SLICE_X47Y119": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y12": { + "bits": {}, + "grid_x": 83, + "grid_y": 195, + "segment": "SEG_CLBLM_L_X32Y12", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y12": "SLICEM", + "SLICE_X47Y12": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y120": { + "bits": {}, + "grid_x": 83, + "grid_y": 83, + "segment": "SEG_CLBLM_L_X32Y120", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y120": "SLICEM", + "SLICE_X47Y120": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y121": { + "bits": {}, + "grid_x": 83, + "grid_y": 82, + "segment": "SEG_CLBLM_L_X32Y121", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y121": "SLICEM", + "SLICE_X47Y121": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y122": { + "bits": {}, + "grid_x": 83, + "grid_y": 81, + "segment": "SEG_CLBLM_L_X32Y122", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y122": "SLICEM", + "SLICE_X47Y122": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y123": { + "bits": {}, + "grid_x": 83, + "grid_y": 80, + "segment": "SEG_CLBLM_L_X32Y123", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y123": "SLICEM", + "SLICE_X47Y123": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y124": { + "bits": {}, + "grid_x": 83, + "grid_y": 79, + "segment": "SEG_CLBLM_L_X32Y124", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y124": "SLICEM", + "SLICE_X47Y124": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y125": { + "bits": {}, + "grid_x": 83, + "grid_y": 77, + "segment": "SEG_CLBLM_L_X32Y125", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y125": "SLICEM", + "SLICE_X47Y125": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y126": { + "bits": {}, + "grid_x": 83, + "grid_y": 76, + "segment": "SEG_CLBLM_L_X32Y126", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y126": "SLICEM", + "SLICE_X47Y126": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y127": { + "bits": {}, + "grid_x": 83, + "grid_y": 75, + "segment": "SEG_CLBLM_L_X32Y127", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y127": "SLICEM", + "SLICE_X47Y127": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y128": { + "bits": {}, + "grid_x": 83, + "grid_y": 74, + "segment": "SEG_CLBLM_L_X32Y128", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y128": "SLICEM", + "SLICE_X47Y128": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y129": { + "bits": {}, + "grid_x": 83, + "grid_y": 73, + "segment": "SEG_CLBLM_L_X32Y129", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y129": "SLICEM", + "SLICE_X47Y129": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y13": { + "bits": {}, + "grid_x": 83, + "grid_y": 194, + "segment": "SEG_CLBLM_L_X32Y13", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y13": "SLICEM", + "SLICE_X47Y13": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y130": { + "bits": {}, + "grid_x": 83, + "grid_y": 72, + "segment": "SEG_CLBLM_L_X32Y130", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y130": "SLICEM", + "SLICE_X47Y130": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y131": { + "bits": {}, + "grid_x": 83, + "grid_y": 71, + "segment": "SEG_CLBLM_L_X32Y131", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y131": "SLICEM", + "SLICE_X47Y131": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y132": { + "bits": {}, + "grid_x": 83, + "grid_y": 70, + "segment": "SEG_CLBLM_L_X32Y132", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y132": "SLICEM", + "SLICE_X47Y132": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y133": { + "bits": {}, + "grid_x": 83, + "grid_y": 69, + "segment": "SEG_CLBLM_L_X32Y133", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y133": "SLICEM", + "SLICE_X47Y133": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y134": { + "bits": {}, + "grid_x": 83, + "grid_y": 68, + "segment": "SEG_CLBLM_L_X32Y134", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y134": "SLICEM", + "SLICE_X47Y134": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y135": { + "bits": {}, + "grid_x": 83, + "grid_y": 67, + "segment": "SEG_CLBLM_L_X32Y135", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y135": "SLICEM", + "SLICE_X47Y135": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y136": { + "bits": {}, + "grid_x": 83, + "grid_y": 66, + "segment": "SEG_CLBLM_L_X32Y136", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y136": "SLICEM", + "SLICE_X47Y136": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y137": { + "bits": {}, + "grid_x": 83, + "grid_y": 65, + "segment": "SEG_CLBLM_L_X32Y137", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y137": "SLICEM", + "SLICE_X47Y137": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y138": { + "bits": {}, + "grid_x": 83, + "grid_y": 64, + "segment": "SEG_CLBLM_L_X32Y138", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y138": "SLICEM", + "SLICE_X47Y138": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y139": { + "bits": {}, + "grid_x": 83, + "grid_y": 63, + "segment": "SEG_CLBLM_L_X32Y139", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y139": "SLICEM", + "SLICE_X47Y139": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y14": { + "bits": {}, + "grid_x": 83, + "grid_y": 193, + "segment": "SEG_CLBLM_L_X32Y14", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y14": "SLICEM", + "SLICE_X47Y14": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y140": { + "bits": {}, + "grid_x": 83, + "grid_y": 62, + "segment": "SEG_CLBLM_L_X32Y140", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y140": "SLICEM", + "SLICE_X47Y140": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y141": { + "bits": {}, + "grid_x": 83, + "grid_y": 61, + "segment": "SEG_CLBLM_L_X32Y141", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y141": "SLICEM", + "SLICE_X47Y141": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y142": { + "bits": {}, + "grid_x": 83, + "grid_y": 60, + "segment": "SEG_CLBLM_L_X32Y142", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y142": "SLICEM", + "SLICE_X47Y142": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y143": { + "bits": {}, + "grid_x": 83, + "grid_y": 59, + "segment": "SEG_CLBLM_L_X32Y143", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y143": "SLICEM", + "SLICE_X47Y143": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y144": { + "bits": {}, + "grid_x": 83, + "grid_y": 58, + "segment": "SEG_CLBLM_L_X32Y144", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y144": "SLICEM", + "SLICE_X47Y144": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y145": { + "bits": {}, + "grid_x": 83, + "grid_y": 57, + "segment": "SEG_CLBLM_L_X32Y145", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y145": "SLICEM", + "SLICE_X47Y145": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y146": { + "bits": {}, + "grid_x": 83, + "grid_y": 56, + "segment": "SEG_CLBLM_L_X32Y146", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y146": "SLICEM", + "SLICE_X47Y146": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y147": { + "bits": {}, + "grid_x": 83, + "grid_y": 55, + "segment": "SEG_CLBLM_L_X32Y147", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y147": "SLICEM", + "SLICE_X47Y147": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y148": { + "bits": {}, + "grid_x": 83, + "grid_y": 54, + "segment": "SEG_CLBLM_L_X32Y148", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y148": "SLICEM", + "SLICE_X47Y148": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y149": { + "bits": {}, + "grid_x": 83, + "grid_y": 53, + "segment": "SEG_CLBLM_L_X32Y149", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y149": "SLICEM", + "SLICE_X47Y149": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y15": { + "bits": {}, + "grid_x": 83, + "grid_y": 192, + "segment": "SEG_CLBLM_L_X32Y15", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y15": "SLICEM", + "SLICE_X47Y15": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y150": { + "bits": {}, + "grid_x": 83, + "grid_y": 51, + "segment": "SEG_CLBLM_L_X32Y150", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y150": "SLICEM", + "SLICE_X47Y150": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y151": { + "bits": {}, + "grid_x": 83, + "grid_y": 50, + "segment": "SEG_CLBLM_L_X32Y151", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y151": "SLICEM", + "SLICE_X47Y151": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y152": { + "bits": {}, + "grid_x": 83, + "grid_y": 49, + "segment": "SEG_CLBLM_L_X32Y152", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y152": "SLICEM", + "SLICE_X47Y152": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y153": { + "bits": {}, + "grid_x": 83, + "grid_y": 48, + "segment": "SEG_CLBLM_L_X32Y153", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y153": "SLICEM", + "SLICE_X47Y153": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y154": { + "bits": {}, + "grid_x": 83, + "grid_y": 47, + "segment": "SEG_CLBLM_L_X32Y154", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y154": "SLICEM", + "SLICE_X47Y154": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y155": { + "bits": {}, + "grid_x": 83, + "grid_y": 46, + "segment": "SEG_CLBLM_L_X32Y155", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y155": "SLICEM", + "SLICE_X47Y155": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y156": { + "bits": {}, + "grid_x": 83, + "grid_y": 45, + "segment": "SEG_CLBLM_L_X32Y156", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y156": "SLICEM", + "SLICE_X47Y156": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y157": { + "bits": {}, + "grid_x": 83, + "grid_y": 44, + "segment": "SEG_CLBLM_L_X32Y157", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y157": "SLICEM", + "SLICE_X47Y157": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y158": { + "bits": {}, + "grid_x": 83, + "grid_y": 43, + "segment": "SEG_CLBLM_L_X32Y158", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y158": "SLICEM", + "SLICE_X47Y158": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y159": { + "bits": {}, + "grid_x": 83, + "grid_y": 42, + "segment": "SEG_CLBLM_L_X32Y159", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y159": "SLICEM", + "SLICE_X47Y159": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y16": { + "bits": {}, + "grid_x": 83, + "grid_y": 191, + "segment": "SEG_CLBLM_L_X32Y16", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y16": "SLICEM", + "SLICE_X47Y16": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y160": { + "bits": {}, + "grid_x": 83, + "grid_y": 41, + "segment": "SEG_CLBLM_L_X32Y160", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y160": "SLICEM", + "SLICE_X47Y160": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y161": { + "bits": {}, + "grid_x": 83, + "grid_y": 40, + "segment": "SEG_CLBLM_L_X32Y161", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y161": "SLICEM", + "SLICE_X47Y161": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y162": { + "bits": {}, + "grid_x": 83, + "grid_y": 39, + "segment": "SEG_CLBLM_L_X32Y162", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y162": "SLICEM", + "SLICE_X47Y162": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y163": { + "bits": {}, + "grid_x": 83, + "grid_y": 38, + "segment": "SEG_CLBLM_L_X32Y163", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y163": "SLICEM", + "SLICE_X47Y163": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y164": { + "bits": {}, + "grid_x": 83, + "grid_y": 37, + "segment": "SEG_CLBLM_L_X32Y164", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y164": "SLICEM", + "SLICE_X47Y164": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y165": { + "bits": {}, + "grid_x": 83, + "grid_y": 36, + "segment": "SEG_CLBLM_L_X32Y165", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y165": "SLICEM", + "SLICE_X47Y165": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y166": { + "bits": {}, + "grid_x": 83, + "grid_y": 35, + "segment": "SEG_CLBLM_L_X32Y166", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y166": "SLICEM", + "SLICE_X47Y166": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y167": { + "bits": {}, + "grid_x": 83, + "grid_y": 34, + "segment": "SEG_CLBLM_L_X32Y167", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y167": "SLICEM", + "SLICE_X47Y167": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y168": { + "bits": {}, + "grid_x": 83, + "grid_y": 33, + "segment": "SEG_CLBLM_L_X32Y168", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y168": "SLICEM", + "SLICE_X47Y168": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y169": { + "bits": {}, + "grid_x": 83, + "grid_y": 32, + "segment": "SEG_CLBLM_L_X32Y169", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y169": "SLICEM", + "SLICE_X47Y169": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y17": { + "bits": {}, + "grid_x": 83, + "grid_y": 190, + "segment": "SEG_CLBLM_L_X32Y17", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y17": "SLICEM", + "SLICE_X47Y17": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y170": { + "bits": {}, + "grid_x": 83, + "grid_y": 31, + "segment": "SEG_CLBLM_L_X32Y170", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y170": "SLICEM", + "SLICE_X47Y170": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y171": { + "bits": {}, + "grid_x": 83, + "grid_y": 30, + "segment": "SEG_CLBLM_L_X32Y171", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y171": "SLICEM", + "SLICE_X47Y171": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y172": { + "bits": {}, + "grid_x": 83, + "grid_y": 29, + "segment": "SEG_CLBLM_L_X32Y172", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y172": "SLICEM", + "SLICE_X47Y172": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y173": { + "bits": {}, + "grid_x": 83, + "grid_y": 28, + "segment": "SEG_CLBLM_L_X32Y173", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y173": "SLICEM", + "SLICE_X47Y173": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y174": { + "bits": {}, + "grid_x": 83, + "grid_y": 27, + "segment": "SEG_CLBLM_L_X32Y174", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y174": "SLICEM", + "SLICE_X47Y174": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y175": { + "bits": {}, + "grid_x": 83, + "grid_y": 25, + "segment": "SEG_CLBLM_L_X32Y175", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y175": "SLICEM", + "SLICE_X47Y175": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y176": { + "bits": {}, + "grid_x": 83, + "grid_y": 24, + "segment": "SEG_CLBLM_L_X32Y176", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y176": "SLICEM", + "SLICE_X47Y176": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y177": { + "bits": {}, + "grid_x": 83, + "grid_y": 23, + "segment": "SEG_CLBLM_L_X32Y177", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y177": "SLICEM", + "SLICE_X47Y177": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y178": { + "bits": {}, + "grid_x": 83, + "grid_y": 22, + "segment": "SEG_CLBLM_L_X32Y178", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y178": "SLICEM", + "SLICE_X47Y178": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y179": { + "bits": {}, + "grid_x": 83, + "grid_y": 21, + "segment": "SEG_CLBLM_L_X32Y179", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y179": "SLICEM", + "SLICE_X47Y179": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y18": { + "bits": {}, + "grid_x": 83, + "grid_y": 189, + "segment": "SEG_CLBLM_L_X32Y18", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y18": "SLICEM", + "SLICE_X47Y18": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y180": { + "bits": {}, + "grid_x": 83, + "grid_y": 20, + "segment": "SEG_CLBLM_L_X32Y180", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y180": "SLICEM", + "SLICE_X47Y180": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y181": { + "bits": {}, + "grid_x": 83, + "grid_y": 19, + "segment": "SEG_CLBLM_L_X32Y181", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y181": "SLICEM", + "SLICE_X47Y181": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y182": { + "bits": {}, + "grid_x": 83, + "grid_y": 18, + "segment": "SEG_CLBLM_L_X32Y182", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y182": "SLICEM", + "SLICE_X47Y182": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y183": { + "bits": {}, + "grid_x": 83, + "grid_y": 17, + "segment": "SEG_CLBLM_L_X32Y183", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y183": "SLICEM", + "SLICE_X47Y183": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y184": { + "bits": {}, + "grid_x": 83, + "grid_y": 16, + "segment": "SEG_CLBLM_L_X32Y184", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y184": "SLICEM", + "SLICE_X47Y184": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y185": { + "bits": {}, + "grid_x": 83, + "grid_y": 15, + "segment": "SEG_CLBLM_L_X32Y185", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y185": "SLICEM", + "SLICE_X47Y185": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y186": { + "bits": {}, + "grid_x": 83, + "grid_y": 14, + "segment": "SEG_CLBLM_L_X32Y186", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y186": "SLICEM", + "SLICE_X47Y186": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y187": { + "bits": {}, + "grid_x": 83, + "grid_y": 13, + "segment": "SEG_CLBLM_L_X32Y187", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y187": "SLICEM", + "SLICE_X47Y187": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y188": { + "bits": {}, + "grid_x": 83, + "grid_y": 12, + "segment": "SEG_CLBLM_L_X32Y188", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y188": "SLICEM", + "SLICE_X47Y188": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y189": { + "bits": {}, + "grid_x": 83, + "grid_y": 11, + "segment": "SEG_CLBLM_L_X32Y189", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y189": "SLICEM", + "SLICE_X47Y189": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y19": { + "bits": {}, + "grid_x": 83, + "grid_y": 188, + "segment": "SEG_CLBLM_L_X32Y19", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y19": "SLICEM", + "SLICE_X47Y19": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y190": { + "bits": {}, + "grid_x": 83, + "grid_y": 10, + "segment": "SEG_CLBLM_L_X32Y190", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y190": "SLICEM", + "SLICE_X47Y190": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y191": { + "bits": {}, + "grid_x": 83, + "grid_y": 9, + "segment": "SEG_CLBLM_L_X32Y191", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y191": "SLICEM", + "SLICE_X47Y191": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y192": { + "bits": {}, + "grid_x": 83, + "grid_y": 8, + "segment": "SEG_CLBLM_L_X32Y192", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y192": "SLICEM", + "SLICE_X47Y192": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y193": { + "bits": {}, + "grid_x": 83, + "grid_y": 7, + "segment": "SEG_CLBLM_L_X32Y193", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y193": "SLICEM", + "SLICE_X47Y193": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y194": { + "bits": {}, + "grid_x": 83, + "grid_y": 6, + "segment": "SEG_CLBLM_L_X32Y194", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y194": "SLICEM", + "SLICE_X47Y194": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y195": { + "bits": {}, + "grid_x": 83, + "grid_y": 5, + "segment": "SEG_CLBLM_L_X32Y195", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y195": "SLICEM", + "SLICE_X47Y195": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y196": { + "bits": {}, + "grid_x": 83, + "grid_y": 4, + "segment": "SEG_CLBLM_L_X32Y196", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y196": "SLICEM", + "SLICE_X47Y196": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y197": { + "bits": {}, + "grid_x": 83, + "grid_y": 3, + "segment": "SEG_CLBLM_L_X32Y197", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y197": "SLICEM", + "SLICE_X47Y197": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y198": { + "bits": {}, + "grid_x": 83, + "grid_y": 2, + "segment": "SEG_CLBLM_L_X32Y198", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y198": "SLICEM", + "SLICE_X47Y198": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y199": { + "bits": {}, + "grid_x": 83, + "grid_y": 1, + "segment": "SEG_CLBLM_L_X32Y199", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y199": "SLICEM", + "SLICE_X47Y199": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y2": { + "bits": {}, + "grid_x": 83, + "grid_y": 205, + "segment": "SEG_CLBLM_L_X32Y2", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y2": "SLICEM", + "SLICE_X47Y2": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y20": { + "bits": {}, + "grid_x": 83, + "grid_y": 187, + "segment": "SEG_CLBLM_L_X32Y20", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y20": "SLICEM", + "SLICE_X47Y20": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y21": { + "bits": {}, + "grid_x": 83, + "grid_y": 186, + "segment": "SEG_CLBLM_L_X32Y21", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y21": "SLICEM", + "SLICE_X47Y21": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y22": { + "bits": {}, + "grid_x": 83, + "grid_y": 185, + "segment": "SEG_CLBLM_L_X32Y22", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y22": "SLICEM", + "SLICE_X47Y22": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y23": { + "bits": {}, + "grid_x": 83, + "grid_y": 184, + "segment": "SEG_CLBLM_L_X32Y23", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y23": "SLICEM", + "SLICE_X47Y23": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y24": { + "bits": {}, + "grid_x": 83, + "grid_y": 183, + "segment": "SEG_CLBLM_L_X32Y24", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y24": "SLICEM", + "SLICE_X47Y24": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y25": { + "bits": {}, + "grid_x": 83, + "grid_y": 181, + "segment": "SEG_CLBLM_L_X32Y25", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y25": "SLICEM", + "SLICE_X47Y25": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y26": { + "bits": {}, + "grid_x": 83, + "grid_y": 180, + "segment": "SEG_CLBLM_L_X32Y26", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y26": "SLICEM", + "SLICE_X47Y26": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y27": { + "bits": {}, + "grid_x": 83, + "grid_y": 179, + "segment": "SEG_CLBLM_L_X32Y27", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y27": "SLICEM", + "SLICE_X47Y27": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y28": { + "bits": {}, + "grid_x": 83, + "grid_y": 178, + "segment": "SEG_CLBLM_L_X32Y28", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y28": "SLICEM", + "SLICE_X47Y28": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y29": { + "bits": {}, + "grid_x": 83, + "grid_y": 177, + "segment": "SEG_CLBLM_L_X32Y29", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y29": "SLICEM", + "SLICE_X47Y29": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y3": { + "bits": {}, + "grid_x": 83, + "grid_y": 204, + "segment": "SEG_CLBLM_L_X32Y3", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y3": "SLICEM", + "SLICE_X47Y3": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y30": { + "bits": {}, + "grid_x": 83, + "grid_y": 176, + "segment": "SEG_CLBLM_L_X32Y30", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y30": "SLICEM", + "SLICE_X47Y30": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y31": { + "bits": {}, + "grid_x": 83, + "grid_y": 175, + "segment": "SEG_CLBLM_L_X32Y31", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y31": "SLICEM", + "SLICE_X47Y31": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y32": { + "bits": {}, + "grid_x": 83, + "grid_y": 174, + "segment": "SEG_CLBLM_L_X32Y32", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y32": "SLICEM", + "SLICE_X47Y32": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y33": { + "bits": {}, + "grid_x": 83, + "grid_y": 173, + "segment": "SEG_CLBLM_L_X32Y33", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y33": "SLICEM", + "SLICE_X47Y33": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y34": { + "bits": {}, + "grid_x": 83, + "grid_y": 172, + "segment": "SEG_CLBLM_L_X32Y34", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y34": "SLICEM", + "SLICE_X47Y34": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y35": { + "bits": {}, + "grid_x": 83, + "grid_y": 171, + "segment": "SEG_CLBLM_L_X32Y35", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y35": "SLICEM", + "SLICE_X47Y35": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y36": { + "bits": {}, + "grid_x": 83, + "grid_y": 170, + "segment": "SEG_CLBLM_L_X32Y36", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y36": "SLICEM", + "SLICE_X47Y36": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y37": { + "bits": {}, + "grid_x": 83, + "grid_y": 169, + "segment": "SEG_CLBLM_L_X32Y37", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y37": "SLICEM", + "SLICE_X47Y37": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y38": { + "bits": {}, + "grid_x": 83, + "grid_y": 168, + "segment": "SEG_CLBLM_L_X32Y38", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y38": "SLICEM", + "SLICE_X47Y38": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y39": { + "bits": {}, + "grid_x": 83, + "grid_y": 167, + "segment": "SEG_CLBLM_L_X32Y39", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y39": "SLICEM", + "SLICE_X47Y39": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y4": { + "bits": {}, + "grid_x": 83, + "grid_y": 203, + "segment": "SEG_CLBLM_L_X32Y4", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y4": "SLICEM", + "SLICE_X47Y4": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y40": { + "bits": {}, + "grid_x": 83, + "grid_y": 166, + "segment": "SEG_CLBLM_L_X32Y40", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y40": "SLICEM", + "SLICE_X47Y40": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y41": { + "bits": {}, + "grid_x": 83, + "grid_y": 165, + "segment": "SEG_CLBLM_L_X32Y41", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y41": "SLICEM", + "SLICE_X47Y41": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y42": { + "bits": {}, + "grid_x": 83, + "grid_y": 164, + "segment": "SEG_CLBLM_L_X32Y42", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y42": "SLICEM", + "SLICE_X47Y42": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y43": { + "bits": {}, + "grid_x": 83, + "grid_y": 163, + "segment": "SEG_CLBLM_L_X32Y43", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y43": "SLICEM", + "SLICE_X47Y43": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y44": { + "bits": {}, + "grid_x": 83, + "grid_y": 162, + "segment": "SEG_CLBLM_L_X32Y44", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y44": "SLICEM", + "SLICE_X47Y44": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y45": { + "bits": {}, + "grid_x": 83, + "grid_y": 161, + "segment": "SEG_CLBLM_L_X32Y45", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y45": "SLICEM", + "SLICE_X47Y45": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y46": { + "bits": {}, + "grid_x": 83, + "grid_y": 160, + "segment": "SEG_CLBLM_L_X32Y46", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y46": "SLICEM", + "SLICE_X47Y46": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y47": { + "bits": {}, + "grid_x": 83, + "grid_y": 159, + "segment": "SEG_CLBLM_L_X32Y47", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y47": "SLICEM", + "SLICE_X47Y47": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y48": { + "bits": {}, + "grid_x": 83, + "grid_y": 158, + "segment": "SEG_CLBLM_L_X32Y48", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y48": "SLICEM", + "SLICE_X47Y48": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y49": { + "bits": {}, + "grid_x": 83, + "grid_y": 157, + "segment": "SEG_CLBLM_L_X32Y49", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y49": "SLICEM", + "SLICE_X47Y49": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y5": { + "bits": {}, + "grid_x": 83, + "grid_y": 202, + "segment": "SEG_CLBLM_L_X32Y5", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y5": "SLICEM", + "SLICE_X47Y5": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y50": { + "bits": {}, + "grid_x": 83, + "grid_y": 155, + "segment": "SEG_CLBLM_L_X32Y50", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y50": "SLICEM", + "SLICE_X47Y50": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y51": { + "bits": {}, + "grid_x": 83, + "grid_y": 154, + "segment": "SEG_CLBLM_L_X32Y51", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y51": "SLICEM", + "SLICE_X47Y51": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y52": { + "bits": {}, + "grid_x": 83, + "grid_y": 153, + "segment": "SEG_CLBLM_L_X32Y52", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y52": "SLICEM", + "SLICE_X47Y52": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y53": { + "bits": {}, + "grid_x": 83, + "grid_y": 152, + "segment": "SEG_CLBLM_L_X32Y53", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y53": "SLICEM", + "SLICE_X47Y53": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y54": { + "bits": {}, + "grid_x": 83, + "grid_y": 151, + "segment": "SEG_CLBLM_L_X32Y54", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y54": "SLICEM", + "SLICE_X47Y54": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y55": { + "bits": {}, + "grid_x": 83, + "grid_y": 150, + "segment": "SEG_CLBLM_L_X32Y55", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y55": "SLICEM", + "SLICE_X47Y55": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y56": { + "bits": {}, + "grid_x": 83, + "grid_y": 149, + "segment": "SEG_CLBLM_L_X32Y56", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y56": "SLICEM", + "SLICE_X47Y56": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y57": { + "bits": {}, + "grid_x": 83, + "grid_y": 148, + "segment": "SEG_CLBLM_L_X32Y57", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y57": "SLICEM", + "SLICE_X47Y57": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y58": { + "bits": {}, + "grid_x": 83, + "grid_y": 147, + "segment": "SEG_CLBLM_L_X32Y58", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y58": "SLICEM", + "SLICE_X47Y58": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y59": { + "bits": {}, + "grid_x": 83, + "grid_y": 146, + "segment": "SEG_CLBLM_L_X32Y59", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y59": "SLICEM", + "SLICE_X47Y59": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y6": { + "bits": {}, + "grid_x": 83, + "grid_y": 201, + "segment": "SEG_CLBLM_L_X32Y6", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y6": "SLICEM", + "SLICE_X47Y6": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y60": { + "bits": {}, + "grid_x": 83, + "grid_y": 145, + "segment": "SEG_CLBLM_L_X32Y60", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y60": "SLICEM", + "SLICE_X47Y60": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y61": { + "bits": {}, + "grid_x": 83, + "grid_y": 144, + "segment": "SEG_CLBLM_L_X32Y61", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y61": "SLICEM", + "SLICE_X47Y61": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y62": { + "bits": {}, + "grid_x": 83, + "grid_y": 143, + "segment": "SEG_CLBLM_L_X32Y62", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y62": "SLICEM", + "SLICE_X47Y62": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y63": { + "bits": {}, + "grid_x": 83, + "grid_y": 142, + "segment": "SEG_CLBLM_L_X32Y63", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y63": "SLICEM", + "SLICE_X47Y63": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y64": { + "bits": {}, + "grid_x": 83, + "grid_y": 141, + "segment": "SEG_CLBLM_L_X32Y64", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y64": "SLICEM", + "SLICE_X47Y64": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y65": { + "bits": {}, + "grid_x": 83, + "grid_y": 140, + "segment": "SEG_CLBLM_L_X32Y65", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y65": "SLICEM", + "SLICE_X47Y65": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y66": { + "bits": {}, + "grid_x": 83, + "grid_y": 139, + "segment": "SEG_CLBLM_L_X32Y66", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y66": "SLICEM", + "SLICE_X47Y66": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y67": { + "bits": {}, + "grid_x": 83, + "grid_y": 138, + "segment": "SEG_CLBLM_L_X32Y67", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y67": "SLICEM", + "SLICE_X47Y67": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y68": { + "bits": {}, + "grid_x": 83, + "grid_y": 137, + "segment": "SEG_CLBLM_L_X32Y68", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y68": "SLICEM", + "SLICE_X47Y68": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y69": { + "bits": {}, + "grid_x": 83, + "grid_y": 136, + "segment": "SEG_CLBLM_L_X32Y69", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y69": "SLICEM", + "SLICE_X47Y69": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y7": { + "bits": {}, + "grid_x": 83, + "grid_y": 200, + "segment": "SEG_CLBLM_L_X32Y7", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y7": "SLICEM", + "SLICE_X47Y7": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y70": { + "bits": {}, + "grid_x": 83, + "grid_y": 135, + "segment": "SEG_CLBLM_L_X32Y70", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y70": "SLICEM", + "SLICE_X47Y70": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y71": { + "bits": {}, + "grid_x": 83, + "grid_y": 134, + "segment": "SEG_CLBLM_L_X32Y71", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y71": "SLICEM", + "SLICE_X47Y71": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y72": { + "bits": {}, + "grid_x": 83, + "grid_y": 133, + "segment": "SEG_CLBLM_L_X32Y72", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y72": "SLICEM", + "SLICE_X47Y72": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y73": { + "bits": {}, + "grid_x": 83, + "grid_y": 132, + "segment": "SEG_CLBLM_L_X32Y73", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y73": "SLICEM", + "SLICE_X47Y73": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y74": { + "bits": {}, + "grid_x": 83, + "grid_y": 131, + "segment": "SEG_CLBLM_L_X32Y74", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y74": "SLICEM", + "SLICE_X47Y74": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y75": { + "bits": {}, + "grid_x": 83, + "grid_y": 129, + "segment": "SEG_CLBLM_L_X32Y75", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y75": "SLICEM", + "SLICE_X47Y75": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y76": { + "bits": {}, + "grid_x": 83, + "grid_y": 128, + "segment": "SEG_CLBLM_L_X32Y76", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y76": "SLICEM", + "SLICE_X47Y76": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y77": { + "bits": {}, + "grid_x": 83, + "grid_y": 127, + "segment": "SEG_CLBLM_L_X32Y77", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y77": "SLICEM", + "SLICE_X47Y77": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y78": { + "bits": {}, + "grid_x": 83, + "grid_y": 126, + "segment": "SEG_CLBLM_L_X32Y78", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y78": "SLICEM", + "SLICE_X47Y78": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y79": { + "bits": {}, + "grid_x": 83, + "grid_y": 125, + "segment": "SEG_CLBLM_L_X32Y79", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y79": "SLICEM", + "SLICE_X47Y79": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y8": { + "bits": {}, + "grid_x": 83, + "grid_y": 199, + "segment": "SEG_CLBLM_L_X32Y8", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y8": "SLICEM", + "SLICE_X47Y8": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y80": { + "bits": {}, + "grid_x": 83, + "grid_y": 124, + "segment": "SEG_CLBLM_L_X32Y80", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y80": "SLICEM", + "SLICE_X47Y80": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y81": { + "bits": {}, + "grid_x": 83, + "grid_y": 123, + "segment": "SEG_CLBLM_L_X32Y81", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y81": "SLICEM", + "SLICE_X47Y81": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y82": { + "bits": {}, + "grid_x": 83, + "grid_y": 122, + "segment": "SEG_CLBLM_L_X32Y82", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y82": "SLICEM", + "SLICE_X47Y82": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y83": { + "bits": {}, + "grid_x": 83, + "grid_y": 121, + "segment": "SEG_CLBLM_L_X32Y83", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y83": "SLICEM", + "SLICE_X47Y83": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y84": { + "bits": {}, + "grid_x": 83, + "grid_y": 120, + "segment": "SEG_CLBLM_L_X32Y84", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y84": "SLICEM", + "SLICE_X47Y84": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y85": { + "bits": {}, + "grid_x": 83, + "grid_y": 119, + "segment": "SEG_CLBLM_L_X32Y85", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y85": "SLICEM", + "SLICE_X47Y85": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y86": { + "bits": {}, + "grid_x": 83, + "grid_y": 118, + "segment": "SEG_CLBLM_L_X32Y86", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y86": "SLICEM", + "SLICE_X47Y86": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y87": { + "bits": {}, + "grid_x": 83, + "grid_y": 117, + "segment": "SEG_CLBLM_L_X32Y87", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y87": "SLICEM", + "SLICE_X47Y87": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y88": { + "bits": {}, + "grid_x": 83, + "grid_y": 116, + "segment": "SEG_CLBLM_L_X32Y88", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y88": "SLICEM", + "SLICE_X47Y88": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y89": { + "bits": {}, + "grid_x": 83, + "grid_y": 115, + "segment": "SEG_CLBLM_L_X32Y89", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y89": "SLICEM", + "SLICE_X47Y89": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y9": { + "bits": {}, + "grid_x": 83, + "grid_y": 198, + "segment": "SEG_CLBLM_L_X32Y9", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y9": "SLICEM", + "SLICE_X47Y9": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y90": { + "bits": {}, + "grid_x": 83, + "grid_y": 114, + "segment": "SEG_CLBLM_L_X32Y90", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y90": "SLICEM", + "SLICE_X47Y90": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y91": { + "bits": {}, + "grid_x": 83, + "grid_y": 113, + "segment": "SEG_CLBLM_L_X32Y91", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y91": "SLICEM", + "SLICE_X47Y91": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y92": { + "bits": {}, + "grid_x": 83, + "grid_y": 112, + "segment": "SEG_CLBLM_L_X32Y92", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y92": "SLICEM", + "SLICE_X47Y92": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y93": { + "bits": {}, + "grid_x": 83, + "grid_y": 111, + "segment": "SEG_CLBLM_L_X32Y93", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y93": "SLICEM", + "SLICE_X47Y93": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y94": { + "bits": {}, + "grid_x": 83, + "grid_y": 110, + "segment": "SEG_CLBLM_L_X32Y94", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y94": "SLICEM", + "SLICE_X47Y94": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y95": { + "bits": {}, + "grid_x": 83, + "grid_y": 109, + "segment": "SEG_CLBLM_L_X32Y95", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y95": "SLICEM", + "SLICE_X47Y95": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y96": { + "bits": {}, + "grid_x": 83, + "grid_y": 108, + "segment": "SEG_CLBLM_L_X32Y96", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y96": "SLICEM", + "SLICE_X47Y96": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y97": { + "bits": {}, + "grid_x": 83, + "grid_y": 107, + "segment": "SEG_CLBLM_L_X32Y97", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y97": "SLICEM", + "SLICE_X47Y97": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y98": { + "bits": {}, + "grid_x": 83, + "grid_y": 106, + "segment": "SEG_CLBLM_L_X32Y98", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y98": "SLICEM", + "SLICE_X47Y98": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X32Y99": { + "bits": {}, + "grid_x": 83, + "grid_y": 105, + "segment": "SEG_CLBLM_L_X32Y99", + "segment_type": "clblm_l", + "sites": { + "SLICE_X46Y99": "SLICEM", + "SLICE_X47Y99": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y0": { + "bits": {}, + "grid_x": 88, + "grid_y": 207, + "segment": "SEG_CLBLM_L_X34Y0", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y0": "SLICEM", + "SLICE_X49Y0": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y1": { + "bits": {}, + "grid_x": 88, + "grid_y": 206, + "segment": "SEG_CLBLM_L_X34Y1", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y1": "SLICEM", + "SLICE_X49Y1": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y10": { + "bits": {}, + "grid_x": 88, + "grid_y": 197, + "segment": "SEG_CLBLM_L_X34Y10", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y10": "SLICEM", + "SLICE_X49Y10": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y100": { + "bits": {}, + "grid_x": 88, + "grid_y": 103, + "segment": "SEG_CLBLM_L_X34Y100", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y100": "SLICEM", + "SLICE_X49Y100": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y101": { + "bits": {}, + "grid_x": 88, + "grid_y": 102, + "segment": "SEG_CLBLM_L_X34Y101", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y101": "SLICEM", + "SLICE_X49Y101": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y102": { + "bits": {}, + "grid_x": 88, + "grid_y": 101, + "segment": "SEG_CLBLM_L_X34Y102", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y102": "SLICEM", + "SLICE_X49Y102": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y103": { + "bits": {}, + "grid_x": 88, + "grid_y": 100, + "segment": "SEG_CLBLM_L_X34Y103", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y103": "SLICEM", + "SLICE_X49Y103": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y104": { + "bits": {}, + "grid_x": 88, + "grid_y": 99, + "segment": "SEG_CLBLM_L_X34Y104", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y104": "SLICEM", + "SLICE_X49Y104": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y105": { + "bits": {}, + "grid_x": 88, + "grid_y": 98, + "segment": "SEG_CLBLM_L_X34Y105", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y105": "SLICEM", + "SLICE_X49Y105": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y106": { + "bits": {}, + "grid_x": 88, + "grid_y": 97, + "segment": "SEG_CLBLM_L_X34Y106", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y106": "SLICEM", + "SLICE_X49Y106": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y107": { + "bits": {}, + "grid_x": 88, + "grid_y": 96, + "segment": "SEG_CLBLM_L_X34Y107", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y107": "SLICEM", + "SLICE_X49Y107": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y108": { + "bits": {}, + "grid_x": 88, + "grid_y": 95, + "segment": "SEG_CLBLM_L_X34Y108", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y108": "SLICEM", + "SLICE_X49Y108": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y109": { + "bits": {}, + "grid_x": 88, + "grid_y": 94, + "segment": "SEG_CLBLM_L_X34Y109", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y109": "SLICEM", + "SLICE_X49Y109": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y11": { + "bits": {}, + "grid_x": 88, + "grid_y": 196, + "segment": "SEG_CLBLM_L_X34Y11", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y11": "SLICEM", + "SLICE_X49Y11": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y110": { + "bits": {}, + "grid_x": 88, + "grid_y": 93, + "segment": "SEG_CLBLM_L_X34Y110", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y110": "SLICEM", + "SLICE_X49Y110": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y111": { + "bits": {}, + "grid_x": 88, + "grid_y": 92, + "segment": "SEG_CLBLM_L_X34Y111", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y111": "SLICEM", + "SLICE_X49Y111": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y112": { + "bits": {}, + "grid_x": 88, + "grid_y": 91, + "segment": "SEG_CLBLM_L_X34Y112", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y112": "SLICEM", + "SLICE_X49Y112": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y113": { + "bits": {}, + "grid_x": 88, + "grid_y": 90, + "segment": "SEG_CLBLM_L_X34Y113", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y113": "SLICEM", + "SLICE_X49Y113": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y114": { + "bits": {}, + "grid_x": 88, + "grid_y": 89, + "segment": "SEG_CLBLM_L_X34Y114", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y114": "SLICEM", + "SLICE_X49Y114": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y115": { + "bits": {}, + "grid_x": 88, + "grid_y": 88, + "segment": "SEG_CLBLM_L_X34Y115", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y115": "SLICEM", + "SLICE_X49Y115": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y116": { + "bits": {}, + "grid_x": 88, + "grid_y": 87, + "segment": "SEG_CLBLM_L_X34Y116", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y116": "SLICEM", + "SLICE_X49Y116": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y117": { + "bits": {}, + "grid_x": 88, + "grid_y": 86, + "segment": "SEG_CLBLM_L_X34Y117", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y117": "SLICEM", + "SLICE_X49Y117": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y118": { + "bits": {}, + "grid_x": 88, + "grid_y": 85, + "segment": "SEG_CLBLM_L_X34Y118", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y118": "SLICEM", + "SLICE_X49Y118": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y119": { + "bits": {}, + "grid_x": 88, + "grid_y": 84, + "segment": "SEG_CLBLM_L_X34Y119", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y119": "SLICEM", + "SLICE_X49Y119": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y12": { + "bits": {}, + "grid_x": 88, + "grid_y": 195, + "segment": "SEG_CLBLM_L_X34Y12", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y12": "SLICEM", + "SLICE_X49Y12": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y120": { + "bits": {}, + "grid_x": 88, + "grid_y": 83, + "segment": "SEG_CLBLM_L_X34Y120", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y120": "SLICEM", + "SLICE_X49Y120": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y121": { + "bits": {}, + "grid_x": 88, + "grid_y": 82, + "segment": "SEG_CLBLM_L_X34Y121", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y121": "SLICEM", + "SLICE_X49Y121": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y122": { + "bits": {}, + "grid_x": 88, + "grid_y": 81, + "segment": "SEG_CLBLM_L_X34Y122", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y122": "SLICEM", + "SLICE_X49Y122": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y123": { + "bits": {}, + "grid_x": 88, + "grid_y": 80, + "segment": "SEG_CLBLM_L_X34Y123", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y123": "SLICEM", + "SLICE_X49Y123": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y124": { + "bits": {}, + "grid_x": 88, + "grid_y": 79, + "segment": "SEG_CLBLM_L_X34Y124", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y124": "SLICEM", + "SLICE_X49Y124": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y125": { + "bits": {}, + "grid_x": 88, + "grid_y": 77, + "segment": "SEG_CLBLM_L_X34Y125", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y125": "SLICEM", + "SLICE_X49Y125": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y126": { + "bits": {}, + "grid_x": 88, + "grid_y": 76, + "segment": "SEG_CLBLM_L_X34Y126", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y126": "SLICEM", + "SLICE_X49Y126": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y127": { + "bits": {}, + "grid_x": 88, + "grid_y": 75, + "segment": "SEG_CLBLM_L_X34Y127", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y127": "SLICEM", + "SLICE_X49Y127": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y128": { + "bits": {}, + "grid_x": 88, + "grid_y": 74, + "segment": "SEG_CLBLM_L_X34Y128", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y128": "SLICEM", + "SLICE_X49Y128": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y129": { + "bits": {}, + "grid_x": 88, + "grid_y": 73, + "segment": "SEG_CLBLM_L_X34Y129", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y129": "SLICEM", + "SLICE_X49Y129": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y13": { + "bits": {}, + "grid_x": 88, + "grid_y": 194, + "segment": "SEG_CLBLM_L_X34Y13", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y13": "SLICEM", + "SLICE_X49Y13": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y130": { + "bits": {}, + "grid_x": 88, + "grid_y": 72, + "segment": "SEG_CLBLM_L_X34Y130", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y130": "SLICEM", + "SLICE_X49Y130": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y131": { + "bits": {}, + "grid_x": 88, + "grid_y": 71, + "segment": "SEG_CLBLM_L_X34Y131", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y131": "SLICEM", + "SLICE_X49Y131": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y132": { + "bits": {}, + "grid_x": 88, + "grid_y": 70, + "segment": "SEG_CLBLM_L_X34Y132", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y132": "SLICEM", + "SLICE_X49Y132": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y133": { + "bits": {}, + "grid_x": 88, + "grid_y": 69, + "segment": "SEG_CLBLM_L_X34Y133", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y133": "SLICEM", + "SLICE_X49Y133": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y134": { + "bits": {}, + "grid_x": 88, + "grid_y": 68, + "segment": "SEG_CLBLM_L_X34Y134", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y134": "SLICEM", + "SLICE_X49Y134": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y135": { + "bits": {}, + "grid_x": 88, + "grid_y": 67, + "segment": "SEG_CLBLM_L_X34Y135", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y135": "SLICEM", + "SLICE_X49Y135": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y136": { + "bits": {}, + "grid_x": 88, + "grid_y": 66, + "segment": "SEG_CLBLM_L_X34Y136", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y136": "SLICEM", + "SLICE_X49Y136": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y137": { + "bits": {}, + "grid_x": 88, + "grid_y": 65, + "segment": "SEG_CLBLM_L_X34Y137", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y137": "SLICEM", + "SLICE_X49Y137": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y138": { + "bits": {}, + "grid_x": 88, + "grid_y": 64, + "segment": "SEG_CLBLM_L_X34Y138", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y138": "SLICEM", + "SLICE_X49Y138": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y139": { + "bits": {}, + "grid_x": 88, + "grid_y": 63, + "segment": "SEG_CLBLM_L_X34Y139", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y139": "SLICEM", + "SLICE_X49Y139": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y14": { + "bits": {}, + "grid_x": 88, + "grid_y": 193, + "segment": "SEG_CLBLM_L_X34Y14", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y14": "SLICEM", + "SLICE_X49Y14": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y140": { + "bits": {}, + "grid_x": 88, + "grid_y": 62, + "segment": "SEG_CLBLM_L_X34Y140", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y140": "SLICEM", + "SLICE_X49Y140": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y141": { + "bits": {}, + "grid_x": 88, + "grid_y": 61, + "segment": "SEG_CLBLM_L_X34Y141", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y141": "SLICEM", + "SLICE_X49Y141": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y142": { + "bits": {}, + "grid_x": 88, + "grid_y": 60, + "segment": "SEG_CLBLM_L_X34Y142", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y142": "SLICEM", + "SLICE_X49Y142": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y143": { + "bits": {}, + "grid_x": 88, + "grid_y": 59, + "segment": "SEG_CLBLM_L_X34Y143", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y143": "SLICEM", + "SLICE_X49Y143": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y144": { + "bits": {}, + "grid_x": 88, + "grid_y": 58, + "segment": "SEG_CLBLM_L_X34Y144", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y144": "SLICEM", + "SLICE_X49Y144": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y145": { + "bits": {}, + "grid_x": 88, + "grid_y": 57, + "segment": "SEG_CLBLM_L_X34Y145", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y145": "SLICEM", + "SLICE_X49Y145": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y146": { + "bits": {}, + "grid_x": 88, + "grid_y": 56, + "segment": "SEG_CLBLM_L_X34Y146", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y146": "SLICEM", + "SLICE_X49Y146": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y147": { + "bits": {}, + "grid_x": 88, + "grid_y": 55, + "segment": "SEG_CLBLM_L_X34Y147", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y147": "SLICEM", + "SLICE_X49Y147": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y148": { + "bits": {}, + "grid_x": 88, + "grid_y": 54, + "segment": "SEG_CLBLM_L_X34Y148", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y148": "SLICEM", + "SLICE_X49Y148": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y149": { + "bits": {}, + "grid_x": 88, + "grid_y": 53, + "segment": "SEG_CLBLM_L_X34Y149", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y149": "SLICEM", + "SLICE_X49Y149": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y15": { + "bits": {}, + "grid_x": 88, + "grid_y": 192, + "segment": "SEG_CLBLM_L_X34Y15", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y15": "SLICEM", + "SLICE_X49Y15": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y150": { + "bits": {}, + "grid_x": 88, + "grid_y": 51, + "segment": "SEG_CLBLM_L_X34Y150", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y150": "SLICEM", + "SLICE_X49Y150": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y151": { + "bits": {}, + "grid_x": 88, + "grid_y": 50, + "segment": "SEG_CLBLM_L_X34Y151", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y151": "SLICEM", + "SLICE_X49Y151": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y152": { + "bits": {}, + "grid_x": 88, + "grid_y": 49, + "segment": "SEG_CLBLM_L_X34Y152", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y152": "SLICEM", + "SLICE_X49Y152": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y153": { + "bits": {}, + "grid_x": 88, + "grid_y": 48, + "segment": "SEG_CLBLM_L_X34Y153", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y153": "SLICEM", + "SLICE_X49Y153": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y154": { + "bits": {}, + "grid_x": 88, + "grid_y": 47, + "segment": "SEG_CLBLM_L_X34Y154", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y154": "SLICEM", + "SLICE_X49Y154": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y155": { + "bits": {}, + "grid_x": 88, + "grid_y": 46, + "segment": "SEG_CLBLM_L_X34Y155", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y155": "SLICEM", + "SLICE_X49Y155": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y156": { + "bits": {}, + "grid_x": 88, + "grid_y": 45, + "segment": "SEG_CLBLM_L_X34Y156", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y156": "SLICEM", + "SLICE_X49Y156": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y157": { + "bits": {}, + "grid_x": 88, + "grid_y": 44, + "segment": "SEG_CLBLM_L_X34Y157", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y157": "SLICEM", + "SLICE_X49Y157": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y158": { + "bits": {}, + "grid_x": 88, + "grid_y": 43, + "segment": "SEG_CLBLM_L_X34Y158", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y158": "SLICEM", + "SLICE_X49Y158": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y159": { + "bits": {}, + "grid_x": 88, + "grid_y": 42, + "segment": "SEG_CLBLM_L_X34Y159", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y159": "SLICEM", + "SLICE_X49Y159": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y16": { + "bits": {}, + "grid_x": 88, + "grid_y": 191, + "segment": "SEG_CLBLM_L_X34Y16", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y16": "SLICEM", + "SLICE_X49Y16": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y160": { + "bits": {}, + "grid_x": 88, + "grid_y": 41, + "segment": "SEG_CLBLM_L_X34Y160", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y160": "SLICEM", + "SLICE_X49Y160": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y161": { + "bits": {}, + "grid_x": 88, + "grid_y": 40, + "segment": "SEG_CLBLM_L_X34Y161", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y161": "SLICEM", + "SLICE_X49Y161": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y162": { + "bits": {}, + "grid_x": 88, + "grid_y": 39, + "segment": "SEG_CLBLM_L_X34Y162", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y162": "SLICEM", + "SLICE_X49Y162": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y163": { + "bits": {}, + "grid_x": 88, + "grid_y": 38, + "segment": "SEG_CLBLM_L_X34Y163", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y163": "SLICEM", + "SLICE_X49Y163": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y164": { + "bits": {}, + "grid_x": 88, + "grid_y": 37, + "segment": "SEG_CLBLM_L_X34Y164", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y164": "SLICEM", + "SLICE_X49Y164": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y165": { + "bits": {}, + "grid_x": 88, + "grid_y": 36, + "segment": "SEG_CLBLM_L_X34Y165", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y165": "SLICEM", + "SLICE_X49Y165": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y166": { + "bits": {}, + "grid_x": 88, + "grid_y": 35, + "segment": "SEG_CLBLM_L_X34Y166", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y166": "SLICEM", + "SLICE_X49Y166": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y167": { + "bits": {}, + "grid_x": 88, + "grid_y": 34, + "segment": "SEG_CLBLM_L_X34Y167", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y167": "SLICEM", + "SLICE_X49Y167": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y168": { + "bits": {}, + "grid_x": 88, + "grid_y": 33, + "segment": "SEG_CLBLM_L_X34Y168", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y168": "SLICEM", + "SLICE_X49Y168": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y169": { + "bits": {}, + "grid_x": 88, + "grid_y": 32, + "segment": "SEG_CLBLM_L_X34Y169", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y169": "SLICEM", + "SLICE_X49Y169": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y17": { + "bits": {}, + "grid_x": 88, + "grid_y": 190, + "segment": "SEG_CLBLM_L_X34Y17", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y17": "SLICEM", + "SLICE_X49Y17": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y170": { + "bits": {}, + "grid_x": 88, + "grid_y": 31, + "segment": "SEG_CLBLM_L_X34Y170", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y170": "SLICEM", + "SLICE_X49Y170": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y171": { + "bits": {}, + "grid_x": 88, + "grid_y": 30, + "segment": "SEG_CLBLM_L_X34Y171", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y171": "SLICEM", + "SLICE_X49Y171": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y172": { + "bits": {}, + "grid_x": 88, + "grid_y": 29, + "segment": "SEG_CLBLM_L_X34Y172", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y172": "SLICEM", + "SLICE_X49Y172": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y173": { + "bits": {}, + "grid_x": 88, + "grid_y": 28, + "segment": "SEG_CLBLM_L_X34Y173", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y173": "SLICEM", + "SLICE_X49Y173": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y174": { + "bits": {}, + "grid_x": 88, + "grid_y": 27, + "segment": "SEG_CLBLM_L_X34Y174", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y174": "SLICEM", + "SLICE_X49Y174": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y175": { + "bits": {}, + "grid_x": 88, + "grid_y": 25, + "segment": "SEG_CLBLM_L_X34Y175", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y175": "SLICEM", + "SLICE_X49Y175": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y176": { + "bits": {}, + "grid_x": 88, + "grid_y": 24, + "segment": "SEG_CLBLM_L_X34Y176", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y176": "SLICEM", + "SLICE_X49Y176": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y177": { + "bits": {}, + "grid_x": 88, + "grid_y": 23, + "segment": "SEG_CLBLM_L_X34Y177", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y177": "SLICEM", + "SLICE_X49Y177": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y178": { + "bits": {}, + "grid_x": 88, + "grid_y": 22, + "segment": "SEG_CLBLM_L_X34Y178", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y178": "SLICEM", + "SLICE_X49Y178": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y179": { + "bits": {}, + "grid_x": 88, + "grid_y": 21, + "segment": "SEG_CLBLM_L_X34Y179", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y179": "SLICEM", + "SLICE_X49Y179": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y18": { + "bits": {}, + "grid_x": 88, + "grid_y": 189, + "segment": "SEG_CLBLM_L_X34Y18", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y18": "SLICEM", + "SLICE_X49Y18": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y180": { + "bits": {}, + "grid_x": 88, + "grid_y": 20, + "segment": "SEG_CLBLM_L_X34Y180", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y180": "SLICEM", + "SLICE_X49Y180": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y181": { + "bits": {}, + "grid_x": 88, + "grid_y": 19, + "segment": "SEG_CLBLM_L_X34Y181", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y181": "SLICEM", + "SLICE_X49Y181": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y182": { + "bits": {}, + "grid_x": 88, + "grid_y": 18, + "segment": "SEG_CLBLM_L_X34Y182", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y182": "SLICEM", + "SLICE_X49Y182": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y183": { + "bits": {}, + "grid_x": 88, + "grid_y": 17, + "segment": "SEG_CLBLM_L_X34Y183", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y183": "SLICEM", + "SLICE_X49Y183": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y184": { + "bits": {}, + "grid_x": 88, + "grid_y": 16, + "segment": "SEG_CLBLM_L_X34Y184", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y184": "SLICEM", + "SLICE_X49Y184": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y185": { + "bits": {}, + "grid_x": 88, + "grid_y": 15, + "segment": "SEG_CLBLM_L_X34Y185", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y185": "SLICEM", + "SLICE_X49Y185": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y186": { + "bits": {}, + "grid_x": 88, + "grid_y": 14, + "segment": "SEG_CLBLM_L_X34Y186", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y186": "SLICEM", + "SLICE_X49Y186": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y187": { + "bits": {}, + "grid_x": 88, + "grid_y": 13, + "segment": "SEG_CLBLM_L_X34Y187", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y187": "SLICEM", + "SLICE_X49Y187": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y188": { + "bits": {}, + "grid_x": 88, + "grid_y": 12, + "segment": "SEG_CLBLM_L_X34Y188", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y188": "SLICEM", + "SLICE_X49Y188": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y189": { + "bits": {}, + "grid_x": 88, + "grid_y": 11, + "segment": "SEG_CLBLM_L_X34Y189", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y189": "SLICEM", + "SLICE_X49Y189": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y19": { + "bits": {}, + "grid_x": 88, + "grid_y": 188, + "segment": "SEG_CLBLM_L_X34Y19", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y19": "SLICEM", + "SLICE_X49Y19": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y190": { + "bits": {}, + "grid_x": 88, + "grid_y": 10, + "segment": "SEG_CLBLM_L_X34Y190", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y190": "SLICEM", + "SLICE_X49Y190": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y191": { + "bits": {}, + "grid_x": 88, + "grid_y": 9, + "segment": "SEG_CLBLM_L_X34Y191", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y191": "SLICEM", + "SLICE_X49Y191": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y192": { + "bits": {}, + "grid_x": 88, + "grid_y": 8, + "segment": "SEG_CLBLM_L_X34Y192", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y192": "SLICEM", + "SLICE_X49Y192": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y193": { + "bits": {}, + "grid_x": 88, + "grid_y": 7, + "segment": "SEG_CLBLM_L_X34Y193", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y193": "SLICEM", + "SLICE_X49Y193": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y194": { + "bits": {}, + "grid_x": 88, + "grid_y": 6, + "segment": "SEG_CLBLM_L_X34Y194", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y194": "SLICEM", + "SLICE_X49Y194": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y195": { + "bits": {}, + "grid_x": 88, + "grid_y": 5, + "segment": "SEG_CLBLM_L_X34Y195", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y195": "SLICEM", + "SLICE_X49Y195": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y196": { + "bits": {}, + "grid_x": 88, + "grid_y": 4, + "segment": "SEG_CLBLM_L_X34Y196", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y196": "SLICEM", + "SLICE_X49Y196": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y197": { + "bits": {}, + "grid_x": 88, + "grid_y": 3, + "segment": "SEG_CLBLM_L_X34Y197", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y197": "SLICEM", + "SLICE_X49Y197": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y198": { + "bits": {}, + "grid_x": 88, + "grid_y": 2, + "segment": "SEG_CLBLM_L_X34Y198", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y198": "SLICEM", + "SLICE_X49Y198": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y199": { + "bits": {}, + "grid_x": 88, + "grid_y": 1, + "segment": "SEG_CLBLM_L_X34Y199", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y199": "SLICEM", + "SLICE_X49Y199": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y2": { + "bits": {}, + "grid_x": 88, + "grid_y": 205, + "segment": "SEG_CLBLM_L_X34Y2", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y2": "SLICEM", + "SLICE_X49Y2": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y20": { + "bits": {}, + "grid_x": 88, + "grid_y": 187, + "segment": "SEG_CLBLM_L_X34Y20", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y20": "SLICEM", + "SLICE_X49Y20": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y21": { + "bits": {}, + "grid_x": 88, + "grid_y": 186, + "segment": "SEG_CLBLM_L_X34Y21", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y21": "SLICEM", + "SLICE_X49Y21": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y22": { + "bits": {}, + "grid_x": 88, + "grid_y": 185, + "segment": "SEG_CLBLM_L_X34Y22", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y22": "SLICEM", + "SLICE_X49Y22": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y23": { + "bits": {}, + "grid_x": 88, + "grid_y": 184, + "segment": "SEG_CLBLM_L_X34Y23", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y23": "SLICEM", + "SLICE_X49Y23": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y24": { + "bits": {}, + "grid_x": 88, + "grid_y": 183, + "segment": "SEG_CLBLM_L_X34Y24", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y24": "SLICEM", + "SLICE_X49Y24": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y25": { + "bits": {}, + "grid_x": 88, + "grid_y": 181, + "segment": "SEG_CLBLM_L_X34Y25", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y25": "SLICEM", + "SLICE_X49Y25": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y26": { + "bits": {}, + "grid_x": 88, + "grid_y": 180, + "segment": "SEG_CLBLM_L_X34Y26", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y26": "SLICEM", + "SLICE_X49Y26": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y27": { + "bits": {}, + "grid_x": 88, + "grid_y": 179, + "segment": "SEG_CLBLM_L_X34Y27", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y27": "SLICEM", + "SLICE_X49Y27": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y28": { + "bits": {}, + "grid_x": 88, + "grid_y": 178, + "segment": "SEG_CLBLM_L_X34Y28", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y28": "SLICEM", + "SLICE_X49Y28": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y29": { + "bits": {}, + "grid_x": 88, + "grid_y": 177, + "segment": "SEG_CLBLM_L_X34Y29", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y29": "SLICEM", + "SLICE_X49Y29": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y3": { + "bits": {}, + "grid_x": 88, + "grid_y": 204, + "segment": "SEG_CLBLM_L_X34Y3", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y3": "SLICEM", + "SLICE_X49Y3": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y30": { + "bits": {}, + "grid_x": 88, + "grid_y": 176, + "segment": "SEG_CLBLM_L_X34Y30", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y30": "SLICEM", + "SLICE_X49Y30": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y31": { + "bits": {}, + "grid_x": 88, + "grid_y": 175, + "segment": "SEG_CLBLM_L_X34Y31", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y31": "SLICEM", + "SLICE_X49Y31": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y32": { + "bits": {}, + "grid_x": 88, + "grid_y": 174, + "segment": "SEG_CLBLM_L_X34Y32", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y32": "SLICEM", + "SLICE_X49Y32": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y33": { + "bits": {}, + "grid_x": 88, + "grid_y": 173, + "segment": "SEG_CLBLM_L_X34Y33", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y33": "SLICEM", + "SLICE_X49Y33": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y34": { + "bits": {}, + "grid_x": 88, + "grid_y": 172, + "segment": "SEG_CLBLM_L_X34Y34", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y34": "SLICEM", + "SLICE_X49Y34": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y35": { + "bits": {}, + "grid_x": 88, + "grid_y": 171, + "segment": "SEG_CLBLM_L_X34Y35", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y35": "SLICEM", + "SLICE_X49Y35": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y36": { + "bits": {}, + "grid_x": 88, + "grid_y": 170, + "segment": "SEG_CLBLM_L_X34Y36", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y36": "SLICEM", + "SLICE_X49Y36": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y37": { + "bits": {}, + "grid_x": 88, + "grid_y": 169, + "segment": "SEG_CLBLM_L_X34Y37", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y37": "SLICEM", + "SLICE_X49Y37": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y38": { + "bits": {}, + "grid_x": 88, + "grid_y": 168, + "segment": "SEG_CLBLM_L_X34Y38", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y38": "SLICEM", + "SLICE_X49Y38": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y39": { + "bits": {}, + "grid_x": 88, + "grid_y": 167, + "segment": "SEG_CLBLM_L_X34Y39", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y39": "SLICEM", + "SLICE_X49Y39": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y4": { + "bits": {}, + "grid_x": 88, + "grid_y": 203, + "segment": "SEG_CLBLM_L_X34Y4", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y4": "SLICEM", + "SLICE_X49Y4": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y40": { + "bits": {}, + "grid_x": 88, + "grid_y": 166, + "segment": "SEG_CLBLM_L_X34Y40", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y40": "SLICEM", + "SLICE_X49Y40": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y41": { + "bits": {}, + "grid_x": 88, + "grid_y": 165, + "segment": "SEG_CLBLM_L_X34Y41", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y41": "SLICEM", + "SLICE_X49Y41": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y42": { + "bits": {}, + "grid_x": 88, + "grid_y": 164, + "segment": "SEG_CLBLM_L_X34Y42", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y42": "SLICEM", + "SLICE_X49Y42": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y43": { + "bits": {}, + "grid_x": 88, + "grid_y": 163, + "segment": "SEG_CLBLM_L_X34Y43", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y43": "SLICEM", + "SLICE_X49Y43": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y44": { + "bits": {}, + "grid_x": 88, + "grid_y": 162, + "segment": "SEG_CLBLM_L_X34Y44", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y44": "SLICEM", + "SLICE_X49Y44": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y45": { + "bits": {}, + "grid_x": 88, + "grid_y": 161, + "segment": "SEG_CLBLM_L_X34Y45", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y45": "SLICEM", + "SLICE_X49Y45": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y46": { + "bits": {}, + "grid_x": 88, + "grid_y": 160, + "segment": "SEG_CLBLM_L_X34Y46", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y46": "SLICEM", + "SLICE_X49Y46": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y47": { + "bits": {}, + "grid_x": 88, + "grid_y": 159, + "segment": "SEG_CLBLM_L_X34Y47", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y47": "SLICEM", + "SLICE_X49Y47": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y48": { + "bits": {}, + "grid_x": 88, + "grid_y": 158, + "segment": "SEG_CLBLM_L_X34Y48", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y48": "SLICEM", + "SLICE_X49Y48": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y49": { + "bits": {}, + "grid_x": 88, + "grid_y": 157, + "segment": "SEG_CLBLM_L_X34Y49", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y49": "SLICEM", + "SLICE_X49Y49": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y5": { + "bits": {}, + "grid_x": 88, + "grid_y": 202, + "segment": "SEG_CLBLM_L_X34Y5", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y5": "SLICEM", + "SLICE_X49Y5": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y50": { + "bits": {}, + "grid_x": 88, + "grid_y": 155, + "segment": "SEG_CLBLM_L_X34Y50", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y50": "SLICEM", + "SLICE_X49Y50": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y51": { + "bits": {}, + "grid_x": 88, + "grid_y": 154, + "segment": "SEG_CLBLM_L_X34Y51", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y51": "SLICEM", + "SLICE_X49Y51": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y52": { + "bits": {}, + "grid_x": 88, + "grid_y": 153, + "segment": "SEG_CLBLM_L_X34Y52", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y52": "SLICEM", + "SLICE_X49Y52": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y53": { + "bits": {}, + "grid_x": 88, + "grid_y": 152, + "segment": "SEG_CLBLM_L_X34Y53", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y53": "SLICEM", + "SLICE_X49Y53": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y54": { + "bits": {}, + "grid_x": 88, + "grid_y": 151, + "segment": "SEG_CLBLM_L_X34Y54", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y54": "SLICEM", + "SLICE_X49Y54": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y55": { + "bits": {}, + "grid_x": 88, + "grid_y": 150, + "segment": "SEG_CLBLM_L_X34Y55", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y55": "SLICEM", + "SLICE_X49Y55": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y56": { + "bits": {}, + "grid_x": 88, + "grid_y": 149, + "segment": "SEG_CLBLM_L_X34Y56", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y56": "SLICEM", + "SLICE_X49Y56": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y57": { + "bits": {}, + "grid_x": 88, + "grid_y": 148, + "segment": "SEG_CLBLM_L_X34Y57", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y57": "SLICEM", + "SLICE_X49Y57": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y58": { + "bits": {}, + "grid_x": 88, + "grid_y": 147, + "segment": "SEG_CLBLM_L_X34Y58", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y58": "SLICEM", + "SLICE_X49Y58": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y59": { + "bits": {}, + "grid_x": 88, + "grid_y": 146, + "segment": "SEG_CLBLM_L_X34Y59", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y59": "SLICEM", + "SLICE_X49Y59": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y6": { + "bits": {}, + "grid_x": 88, + "grid_y": 201, + "segment": "SEG_CLBLM_L_X34Y6", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y6": "SLICEM", + "SLICE_X49Y6": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y60": { + "bits": {}, + "grid_x": 88, + "grid_y": 145, + "segment": "SEG_CLBLM_L_X34Y60", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y60": "SLICEM", + "SLICE_X49Y60": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y61": { + "bits": {}, + "grid_x": 88, + "grid_y": 144, + "segment": "SEG_CLBLM_L_X34Y61", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y61": "SLICEM", + "SLICE_X49Y61": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y62": { + "bits": {}, + "grid_x": 88, + "grid_y": 143, + "segment": "SEG_CLBLM_L_X34Y62", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y62": "SLICEM", + "SLICE_X49Y62": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y63": { + "bits": {}, + "grid_x": 88, + "grid_y": 142, + "segment": "SEG_CLBLM_L_X34Y63", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y63": "SLICEM", + "SLICE_X49Y63": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y64": { + "bits": {}, + "grid_x": 88, + "grid_y": 141, + "segment": "SEG_CLBLM_L_X34Y64", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y64": "SLICEM", + "SLICE_X49Y64": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y65": { + "bits": {}, + "grid_x": 88, + "grid_y": 140, + "segment": "SEG_CLBLM_L_X34Y65", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y65": "SLICEM", + "SLICE_X49Y65": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y66": { + "bits": {}, + "grid_x": 88, + "grid_y": 139, + "segment": "SEG_CLBLM_L_X34Y66", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y66": "SLICEM", + "SLICE_X49Y66": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y67": { + "bits": {}, + "grid_x": 88, + "grid_y": 138, + "segment": "SEG_CLBLM_L_X34Y67", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y67": "SLICEM", + "SLICE_X49Y67": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y68": { + "bits": {}, + "grid_x": 88, + "grid_y": 137, + "segment": "SEG_CLBLM_L_X34Y68", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y68": "SLICEM", + "SLICE_X49Y68": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y69": { + "bits": {}, + "grid_x": 88, + "grid_y": 136, + "segment": "SEG_CLBLM_L_X34Y69", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y69": "SLICEM", + "SLICE_X49Y69": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y7": { + "bits": {}, + "grid_x": 88, + "grid_y": 200, + "segment": "SEG_CLBLM_L_X34Y7", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y7": "SLICEM", + "SLICE_X49Y7": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y70": { + "bits": {}, + "grid_x": 88, + "grid_y": 135, + "segment": "SEG_CLBLM_L_X34Y70", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y70": "SLICEM", + "SLICE_X49Y70": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y71": { + "bits": {}, + "grid_x": 88, + "grid_y": 134, + "segment": "SEG_CLBLM_L_X34Y71", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y71": "SLICEM", + "SLICE_X49Y71": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y72": { + "bits": {}, + "grid_x": 88, + "grid_y": 133, + "segment": "SEG_CLBLM_L_X34Y72", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y72": "SLICEM", + "SLICE_X49Y72": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y73": { + "bits": {}, + "grid_x": 88, + "grid_y": 132, + "segment": "SEG_CLBLM_L_X34Y73", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y73": "SLICEM", + "SLICE_X49Y73": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y74": { + "bits": {}, + "grid_x": 88, + "grid_y": 131, + "segment": "SEG_CLBLM_L_X34Y74", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y74": "SLICEM", + "SLICE_X49Y74": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y75": { + "bits": {}, + "grid_x": 88, + "grid_y": 129, + "segment": "SEG_CLBLM_L_X34Y75", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y75": "SLICEM", + "SLICE_X49Y75": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y76": { + "bits": {}, + "grid_x": 88, + "grid_y": 128, + "segment": "SEG_CLBLM_L_X34Y76", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y76": "SLICEM", + "SLICE_X49Y76": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y77": { + "bits": {}, + "grid_x": 88, + "grid_y": 127, + "segment": "SEG_CLBLM_L_X34Y77", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y77": "SLICEM", + "SLICE_X49Y77": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y78": { + "bits": {}, + "grid_x": 88, + "grid_y": 126, + "segment": "SEG_CLBLM_L_X34Y78", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y78": "SLICEM", + "SLICE_X49Y78": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y79": { + "bits": {}, + "grid_x": 88, + "grid_y": 125, + "segment": "SEG_CLBLM_L_X34Y79", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y79": "SLICEM", + "SLICE_X49Y79": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y8": { + "bits": {}, + "grid_x": 88, + "grid_y": 199, + "segment": "SEG_CLBLM_L_X34Y8", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y8": "SLICEM", + "SLICE_X49Y8": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y80": { + "bits": {}, + "grid_x": 88, + "grid_y": 124, + "segment": "SEG_CLBLM_L_X34Y80", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y80": "SLICEM", + "SLICE_X49Y80": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y81": { + "bits": {}, + "grid_x": 88, + "grid_y": 123, + "segment": "SEG_CLBLM_L_X34Y81", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y81": "SLICEM", + "SLICE_X49Y81": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y82": { + "bits": {}, + "grid_x": 88, + "grid_y": 122, + "segment": "SEG_CLBLM_L_X34Y82", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y82": "SLICEM", + "SLICE_X49Y82": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y83": { + "bits": {}, + "grid_x": 88, + "grid_y": 121, + "segment": "SEG_CLBLM_L_X34Y83", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y83": "SLICEM", + "SLICE_X49Y83": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y84": { + "bits": {}, + "grid_x": 88, + "grid_y": 120, + "segment": "SEG_CLBLM_L_X34Y84", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y84": "SLICEM", + "SLICE_X49Y84": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y85": { + "bits": {}, + "grid_x": 88, + "grid_y": 119, + "segment": "SEG_CLBLM_L_X34Y85", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y85": "SLICEM", + "SLICE_X49Y85": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y86": { + "bits": {}, + "grid_x": 88, + "grid_y": 118, + "segment": "SEG_CLBLM_L_X34Y86", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y86": "SLICEM", + "SLICE_X49Y86": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y87": { + "bits": {}, + "grid_x": 88, + "grid_y": 117, + "segment": "SEG_CLBLM_L_X34Y87", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y87": "SLICEM", + "SLICE_X49Y87": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y88": { + "bits": {}, + "grid_x": 88, + "grid_y": 116, + "segment": "SEG_CLBLM_L_X34Y88", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y88": "SLICEM", + "SLICE_X49Y88": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y89": { + "bits": {}, + "grid_x": 88, + "grid_y": 115, + "segment": "SEG_CLBLM_L_X34Y89", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y89": "SLICEM", + "SLICE_X49Y89": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y9": { + "bits": {}, + "grid_x": 88, + "grid_y": 198, + "segment": "SEG_CLBLM_L_X34Y9", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y9": "SLICEM", + "SLICE_X49Y9": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y90": { + "bits": {}, + "grid_x": 88, + "grid_y": 114, + "segment": "SEG_CLBLM_L_X34Y90", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y90": "SLICEM", + "SLICE_X49Y90": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y91": { + "bits": {}, + "grid_x": 88, + "grid_y": 113, + "segment": "SEG_CLBLM_L_X34Y91", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y91": "SLICEM", + "SLICE_X49Y91": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y92": { + "bits": {}, + "grid_x": 88, + "grid_y": 112, + "segment": "SEG_CLBLM_L_X34Y92", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y92": "SLICEM", + "SLICE_X49Y92": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y93": { + "bits": {}, + "grid_x": 88, + "grid_y": 111, + "segment": "SEG_CLBLM_L_X34Y93", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y93": "SLICEM", + "SLICE_X49Y93": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y94": { + "bits": {}, + "grid_x": 88, + "grid_y": 110, + "segment": "SEG_CLBLM_L_X34Y94", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y94": "SLICEM", + "SLICE_X49Y94": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y95": { + "bits": {}, + "grid_x": 88, + "grid_y": 109, + "segment": "SEG_CLBLM_L_X34Y95", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y95": "SLICEM", + "SLICE_X49Y95": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y96": { + "bits": {}, + "grid_x": 88, + "grid_y": 108, + "segment": "SEG_CLBLM_L_X34Y96", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y96": "SLICEM", + "SLICE_X49Y96": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y97": { + "bits": {}, + "grid_x": 88, + "grid_y": 107, + "segment": "SEG_CLBLM_L_X34Y97", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y97": "SLICEM", + "SLICE_X49Y97": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y98": { + "bits": {}, + "grid_x": 88, + "grid_y": 106, + "segment": "SEG_CLBLM_L_X34Y98", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y98": "SLICEM", + "SLICE_X49Y98": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X34Y99": { + "bits": {}, + "grid_x": 88, + "grid_y": 105, + "segment": "SEG_CLBLM_L_X34Y99", + "segment_type": "clblm_l", + "sites": { + "SLICE_X48Y99": "SLICEM", + "SLICE_X49Y99": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y0": { + "bits": {}, + "grid_x": 24, + "grid_y": 207, + "segment": "SEG_CLBLM_L_X8Y0", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y0": "SLICEM", + "SLICE_X11Y0": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y1": { + "bits": {}, + "grid_x": 24, + "grid_y": 206, + "segment": "SEG_CLBLM_L_X8Y1", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y1": "SLICEM", + "SLICE_X11Y1": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y10": { + "bits": {}, + "grid_x": 24, + "grid_y": 197, + "segment": "SEG_CLBLM_L_X8Y10", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y10": "SLICEM", + "SLICE_X11Y10": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y100": { + "bits": {}, + "grid_x": 24, + "grid_y": 103, + "segment": "SEG_CLBLM_L_X8Y100", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y100": "SLICEM", + "SLICE_X11Y100": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y101": { + "bits": {}, + "grid_x": 24, + "grid_y": 102, + "segment": "SEG_CLBLM_L_X8Y101", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y101": "SLICEM", + "SLICE_X11Y101": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y102": { + "bits": {}, + "grid_x": 24, + "grid_y": 101, + "segment": "SEG_CLBLM_L_X8Y102", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y102": "SLICEM", + "SLICE_X11Y102": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y103": { + "bits": {}, + "grid_x": 24, + "grid_y": 100, + "segment": "SEG_CLBLM_L_X8Y103", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y103": "SLICEM", + "SLICE_X11Y103": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y104": { + "bits": {}, + "grid_x": 24, + "grid_y": 99, + "segment": "SEG_CLBLM_L_X8Y104", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y104": "SLICEM", + "SLICE_X11Y104": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y105": { + "bits": {}, + "grid_x": 24, + "grid_y": 98, + "segment": "SEG_CLBLM_L_X8Y105", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y105": "SLICEM", + "SLICE_X11Y105": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y106": { + "bits": {}, + "grid_x": 24, + "grid_y": 97, + "segment": "SEG_CLBLM_L_X8Y106", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y106": "SLICEM", + "SLICE_X11Y106": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y107": { + "bits": {}, + "grid_x": 24, + "grid_y": 96, + "segment": "SEG_CLBLM_L_X8Y107", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y107": "SLICEM", + "SLICE_X11Y107": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y108": { + "bits": {}, + "grid_x": 24, + "grid_y": 95, + "segment": "SEG_CLBLM_L_X8Y108", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y108": "SLICEM", + "SLICE_X11Y108": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y109": { + "bits": {}, + "grid_x": 24, + "grid_y": 94, + "segment": "SEG_CLBLM_L_X8Y109", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y109": "SLICEM", + "SLICE_X11Y109": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y11": { + "bits": {}, + "grid_x": 24, + "grid_y": 196, + "segment": "SEG_CLBLM_L_X8Y11", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y11": "SLICEM", + "SLICE_X11Y11": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y110": { + "bits": {}, + "grid_x": 24, + "grid_y": 93, + "segment": "SEG_CLBLM_L_X8Y110", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y110": "SLICEM", + "SLICE_X11Y110": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y111": { + "bits": {}, + "grid_x": 24, + "grid_y": 92, + "segment": "SEG_CLBLM_L_X8Y111", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y111": "SLICEM", + "SLICE_X11Y111": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y112": { + "bits": {}, + "grid_x": 24, + "grid_y": 91, + "segment": "SEG_CLBLM_L_X8Y112", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y112": "SLICEM", + "SLICE_X11Y112": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y113": { + "bits": {}, + "grid_x": 24, + "grid_y": 90, + "segment": "SEG_CLBLM_L_X8Y113", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y113": "SLICEM", + "SLICE_X11Y113": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y114": { + "bits": {}, + "grid_x": 24, + "grid_y": 89, + "segment": "SEG_CLBLM_L_X8Y114", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y114": "SLICEM", + "SLICE_X11Y114": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y115": { + "bits": {}, + "grid_x": 24, + "grid_y": 88, + "segment": "SEG_CLBLM_L_X8Y115", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y115": "SLICEM", + "SLICE_X11Y115": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y116": { + "bits": {}, + "grid_x": 24, + "grid_y": 87, + "segment": "SEG_CLBLM_L_X8Y116", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y116": "SLICEM", + "SLICE_X11Y116": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y117": { + "bits": {}, + "grid_x": 24, + "grid_y": 86, + "segment": "SEG_CLBLM_L_X8Y117", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y117": "SLICEM", + "SLICE_X11Y117": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y118": { + "bits": {}, + "grid_x": 24, + "grid_y": 85, + "segment": "SEG_CLBLM_L_X8Y118", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y118": "SLICEM", + "SLICE_X11Y118": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y119": { + "bits": {}, + "grid_x": 24, + "grid_y": 84, + "segment": "SEG_CLBLM_L_X8Y119", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y119": "SLICEM", + "SLICE_X11Y119": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y12": { + "bits": {}, + "grid_x": 24, + "grid_y": 195, + "segment": "SEG_CLBLM_L_X8Y12", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y12": "SLICEM", + "SLICE_X11Y12": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y120": { + "bits": {}, + "grid_x": 24, + "grid_y": 83, + "segment": "SEG_CLBLM_L_X8Y120", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y120": "SLICEM", + "SLICE_X11Y120": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y121": { + "bits": {}, + "grid_x": 24, + "grid_y": 82, + "segment": "SEG_CLBLM_L_X8Y121", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y121": "SLICEM", + "SLICE_X11Y121": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y122": { + "bits": {}, + "grid_x": 24, + "grid_y": 81, + "segment": "SEG_CLBLM_L_X8Y122", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y122": "SLICEM", + "SLICE_X11Y122": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y123": { + "bits": {}, + "grid_x": 24, + "grid_y": 80, + "segment": "SEG_CLBLM_L_X8Y123", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y123": "SLICEM", + "SLICE_X11Y123": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y124": { + "bits": {}, + "grid_x": 24, + "grid_y": 79, + "segment": "SEG_CLBLM_L_X8Y124", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y124": "SLICEM", + "SLICE_X11Y124": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y125": { + "bits": {}, + "grid_x": 24, + "grid_y": 77, + "segment": "SEG_CLBLM_L_X8Y125", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y125": "SLICEM", + "SLICE_X11Y125": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y126": { + "bits": {}, + "grid_x": 24, + "grid_y": 76, + "segment": "SEG_CLBLM_L_X8Y126", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y126": "SLICEM", + "SLICE_X11Y126": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y127": { + "bits": {}, + "grid_x": 24, + "grid_y": 75, + "segment": "SEG_CLBLM_L_X8Y127", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y127": "SLICEM", + "SLICE_X11Y127": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y128": { + "bits": {}, + "grid_x": 24, + "grid_y": 74, + "segment": "SEG_CLBLM_L_X8Y128", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y128": "SLICEM", + "SLICE_X11Y128": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y129": { + "bits": {}, + "grid_x": 24, + "grid_y": 73, + "segment": "SEG_CLBLM_L_X8Y129", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y129": "SLICEM", + "SLICE_X11Y129": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y13": { + "bits": {}, + "grid_x": 24, + "grid_y": 194, + "segment": "SEG_CLBLM_L_X8Y13", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y13": "SLICEM", + "SLICE_X11Y13": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y130": { + "bits": {}, + "grid_x": 24, + "grid_y": 72, + "segment": "SEG_CLBLM_L_X8Y130", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y130": "SLICEM", + "SLICE_X11Y130": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y131": { + "bits": {}, + "grid_x": 24, + "grid_y": 71, + "segment": "SEG_CLBLM_L_X8Y131", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y131": "SLICEM", + "SLICE_X11Y131": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y132": { + "bits": {}, + "grid_x": 24, + "grid_y": 70, + "segment": "SEG_CLBLM_L_X8Y132", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y132": "SLICEM", + "SLICE_X11Y132": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y133": { + "bits": {}, + "grid_x": 24, + "grid_y": 69, + "segment": "SEG_CLBLM_L_X8Y133", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y133": "SLICEM", + "SLICE_X11Y133": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y134": { + "bits": {}, + "grid_x": 24, + "grid_y": 68, + "segment": "SEG_CLBLM_L_X8Y134", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y134": "SLICEM", + "SLICE_X11Y134": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y135": { + "bits": {}, + "grid_x": 24, + "grid_y": 67, + "segment": "SEG_CLBLM_L_X8Y135", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y135": "SLICEM", + "SLICE_X11Y135": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y136": { + "bits": {}, + "grid_x": 24, + "grid_y": 66, + "segment": "SEG_CLBLM_L_X8Y136", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y136": "SLICEM", + "SLICE_X11Y136": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y137": { + "bits": {}, + "grid_x": 24, + "grid_y": 65, + "segment": "SEG_CLBLM_L_X8Y137", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y137": "SLICEM", + "SLICE_X11Y137": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y138": { + "bits": {}, + "grid_x": 24, + "grid_y": 64, + "segment": "SEG_CLBLM_L_X8Y138", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y138": "SLICEM", + "SLICE_X11Y138": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y139": { + "bits": {}, + "grid_x": 24, + "grid_y": 63, + "segment": "SEG_CLBLM_L_X8Y139", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y139": "SLICEM", + "SLICE_X11Y139": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y14": { + "bits": {}, + "grid_x": 24, + "grid_y": 193, + "segment": "SEG_CLBLM_L_X8Y14", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y14": "SLICEM", + "SLICE_X11Y14": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y140": { + "bits": {}, + "grid_x": 24, + "grid_y": 62, + "segment": "SEG_CLBLM_L_X8Y140", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y140": "SLICEM", + "SLICE_X11Y140": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y141": { + "bits": {}, + "grid_x": 24, + "grid_y": 61, + "segment": "SEG_CLBLM_L_X8Y141", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y141": "SLICEM", + "SLICE_X11Y141": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y142": { + "bits": {}, + "grid_x": 24, + "grid_y": 60, + "segment": "SEG_CLBLM_L_X8Y142", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y142": "SLICEM", + "SLICE_X11Y142": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y143": { + "bits": {}, + "grid_x": 24, + "grid_y": 59, + "segment": "SEG_CLBLM_L_X8Y143", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y143": "SLICEM", + "SLICE_X11Y143": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y144": { + "bits": {}, + "grid_x": 24, + "grid_y": 58, + "segment": "SEG_CLBLM_L_X8Y144", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y144": "SLICEM", + "SLICE_X11Y144": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y145": { + "bits": {}, + "grid_x": 24, + "grid_y": 57, + "segment": "SEG_CLBLM_L_X8Y145", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y145": "SLICEM", + "SLICE_X11Y145": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y146": { + "bits": {}, + "grid_x": 24, + "grid_y": 56, + "segment": "SEG_CLBLM_L_X8Y146", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y146": "SLICEM", + "SLICE_X11Y146": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y147": { + "bits": {}, + "grid_x": 24, + "grid_y": 55, + "segment": "SEG_CLBLM_L_X8Y147", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y147": "SLICEM", + "SLICE_X11Y147": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y148": { + "bits": {}, + "grid_x": 24, + "grid_y": 54, + "segment": "SEG_CLBLM_L_X8Y148", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y148": "SLICEM", + "SLICE_X11Y148": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y149": { + "bits": {}, + "grid_x": 24, + "grid_y": 53, + "segment": "SEG_CLBLM_L_X8Y149", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y149": "SLICEM", + "SLICE_X11Y149": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y15": { + "bits": {}, + "grid_x": 24, + "grid_y": 192, + "segment": "SEG_CLBLM_L_X8Y15", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y15": "SLICEM", + "SLICE_X11Y15": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y150": { + "bits": {}, + "grid_x": 24, + "grid_y": 51, + "segment": "SEG_CLBLM_L_X8Y150", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y150": "SLICEM", + "SLICE_X11Y150": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y151": { + "bits": {}, + "grid_x": 24, + "grid_y": 50, + "segment": "SEG_CLBLM_L_X8Y151", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y151": "SLICEM", + "SLICE_X11Y151": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y152": { + "bits": {}, + "grid_x": 24, + "grid_y": 49, + "segment": "SEG_CLBLM_L_X8Y152", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y152": "SLICEM", + "SLICE_X11Y152": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y153": { + "bits": {}, + "grid_x": 24, + "grid_y": 48, + "segment": "SEG_CLBLM_L_X8Y153", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y153": "SLICEM", + "SLICE_X11Y153": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y154": { + "bits": {}, + "grid_x": 24, + "grid_y": 47, + "segment": "SEG_CLBLM_L_X8Y154", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y154": "SLICEM", + "SLICE_X11Y154": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y155": { + "bits": {}, + "grid_x": 24, + "grid_y": 46, + "segment": "SEG_CLBLM_L_X8Y155", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y155": "SLICEM", + "SLICE_X11Y155": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y156": { + "bits": {}, + "grid_x": 24, + "grid_y": 45, + "segment": "SEG_CLBLM_L_X8Y156", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y156": "SLICEM", + "SLICE_X11Y156": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y157": { + "bits": {}, + "grid_x": 24, + "grid_y": 44, + "segment": "SEG_CLBLM_L_X8Y157", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y157": "SLICEM", + "SLICE_X11Y157": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y158": { + "bits": {}, + "grid_x": 24, + "grid_y": 43, + "segment": "SEG_CLBLM_L_X8Y158", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y158": "SLICEM", + "SLICE_X11Y158": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y159": { + "bits": {}, + "grid_x": 24, + "grid_y": 42, + "segment": "SEG_CLBLM_L_X8Y159", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y159": "SLICEM", + "SLICE_X11Y159": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y16": { + "bits": {}, + "grid_x": 24, + "grid_y": 191, + "segment": "SEG_CLBLM_L_X8Y16", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y16": "SLICEM", + "SLICE_X11Y16": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y160": { + "bits": {}, + "grid_x": 24, + "grid_y": 41, + "segment": "SEG_CLBLM_L_X8Y160", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y160": "SLICEM", + "SLICE_X11Y160": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y161": { + "bits": {}, + "grid_x": 24, + "grid_y": 40, + "segment": "SEG_CLBLM_L_X8Y161", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y161": "SLICEM", + "SLICE_X11Y161": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y162": { + "bits": {}, + "grid_x": 24, + "grid_y": 39, + "segment": "SEG_CLBLM_L_X8Y162", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y162": "SLICEM", + "SLICE_X11Y162": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y163": { + "bits": {}, + "grid_x": 24, + "grid_y": 38, + "segment": "SEG_CLBLM_L_X8Y163", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y163": "SLICEM", + "SLICE_X11Y163": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y164": { + "bits": {}, + "grid_x": 24, + "grid_y": 37, + "segment": "SEG_CLBLM_L_X8Y164", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y164": "SLICEM", + "SLICE_X11Y164": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y165": { + "bits": {}, + "grid_x": 24, + "grid_y": 36, + "segment": "SEG_CLBLM_L_X8Y165", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y165": "SLICEM", + "SLICE_X11Y165": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y166": { + "bits": {}, + "grid_x": 24, + "grid_y": 35, + "segment": "SEG_CLBLM_L_X8Y166", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y166": "SLICEM", + "SLICE_X11Y166": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y167": { + "bits": {}, + "grid_x": 24, + "grid_y": 34, + "segment": "SEG_CLBLM_L_X8Y167", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y167": "SLICEM", + "SLICE_X11Y167": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y168": { + "bits": {}, + "grid_x": 24, + "grid_y": 33, + "segment": "SEG_CLBLM_L_X8Y168", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y168": "SLICEM", + "SLICE_X11Y168": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y169": { + "bits": {}, + "grid_x": 24, + "grid_y": 32, + "segment": "SEG_CLBLM_L_X8Y169", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y169": "SLICEM", + "SLICE_X11Y169": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y17": { + "bits": {}, + "grid_x": 24, + "grid_y": 190, + "segment": "SEG_CLBLM_L_X8Y17", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y17": "SLICEM", + "SLICE_X11Y17": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y170": { + "bits": {}, + "grid_x": 24, + "grid_y": 31, + "segment": "SEG_CLBLM_L_X8Y170", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y170": "SLICEM", + "SLICE_X11Y170": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y171": { + "bits": {}, + "grid_x": 24, + "grid_y": 30, + "segment": "SEG_CLBLM_L_X8Y171", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y171": "SLICEM", + "SLICE_X11Y171": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y172": { + "bits": {}, + "grid_x": 24, + "grid_y": 29, + "segment": "SEG_CLBLM_L_X8Y172", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y172": "SLICEM", + "SLICE_X11Y172": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y173": { + "bits": {}, + "grid_x": 24, + "grid_y": 28, + "segment": "SEG_CLBLM_L_X8Y173", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y173": "SLICEM", + "SLICE_X11Y173": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y174": { + "bits": {}, + "grid_x": 24, + "grid_y": 27, + "segment": "SEG_CLBLM_L_X8Y174", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y174": "SLICEM", + "SLICE_X11Y174": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y175": { + "bits": {}, + "grid_x": 24, + "grid_y": 25, + "segment": "SEG_CLBLM_L_X8Y175", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y175": "SLICEM", + "SLICE_X11Y175": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y176": { + "bits": {}, + "grid_x": 24, + "grid_y": 24, + "segment": "SEG_CLBLM_L_X8Y176", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y176": "SLICEM", + "SLICE_X11Y176": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y177": { + "bits": {}, + "grid_x": 24, + "grid_y": 23, + "segment": "SEG_CLBLM_L_X8Y177", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y177": "SLICEM", + "SLICE_X11Y177": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y178": { + "bits": {}, + "grid_x": 24, + "grid_y": 22, + "segment": "SEG_CLBLM_L_X8Y178", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y178": "SLICEM", + "SLICE_X11Y178": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y179": { + "bits": {}, + "grid_x": 24, + "grid_y": 21, + "segment": "SEG_CLBLM_L_X8Y179", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y179": "SLICEM", + "SLICE_X11Y179": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y18": { + "bits": {}, + "grid_x": 24, + "grid_y": 189, + "segment": "SEG_CLBLM_L_X8Y18", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y18": "SLICEM", + "SLICE_X11Y18": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y180": { + "bits": {}, + "grid_x": 24, + "grid_y": 20, + "segment": "SEG_CLBLM_L_X8Y180", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y180": "SLICEM", + "SLICE_X11Y180": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y181": { + "bits": {}, + "grid_x": 24, + "grid_y": 19, + "segment": "SEG_CLBLM_L_X8Y181", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y181": "SLICEM", + "SLICE_X11Y181": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y182": { + "bits": {}, + "grid_x": 24, + "grid_y": 18, + "segment": "SEG_CLBLM_L_X8Y182", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y182": "SLICEM", + "SLICE_X11Y182": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y183": { + "bits": {}, + "grid_x": 24, + "grid_y": 17, + "segment": "SEG_CLBLM_L_X8Y183", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y183": "SLICEM", + "SLICE_X11Y183": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y184": { + "bits": {}, + "grid_x": 24, + "grid_y": 16, + "segment": "SEG_CLBLM_L_X8Y184", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y184": "SLICEM", + "SLICE_X11Y184": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y185": { + "bits": {}, + "grid_x": 24, + "grid_y": 15, + "segment": "SEG_CLBLM_L_X8Y185", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y185": "SLICEM", + "SLICE_X11Y185": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y186": { + "bits": {}, + "grid_x": 24, + "grid_y": 14, + "segment": "SEG_CLBLM_L_X8Y186", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y186": "SLICEM", + "SLICE_X11Y186": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y187": { + "bits": {}, + "grid_x": 24, + "grid_y": 13, + "segment": "SEG_CLBLM_L_X8Y187", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y187": "SLICEM", + "SLICE_X11Y187": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y188": { + "bits": {}, + "grid_x": 24, + "grid_y": 12, + "segment": "SEG_CLBLM_L_X8Y188", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y188": "SLICEM", + "SLICE_X11Y188": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y189": { + "bits": {}, + "grid_x": 24, + "grid_y": 11, + "segment": "SEG_CLBLM_L_X8Y189", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y189": "SLICEM", + "SLICE_X11Y189": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y19": { + "bits": {}, + "grid_x": 24, + "grid_y": 188, + "segment": "SEG_CLBLM_L_X8Y19", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y19": "SLICEM", + "SLICE_X11Y19": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y190": { + "bits": {}, + "grid_x": 24, + "grid_y": 10, + "segment": "SEG_CLBLM_L_X8Y190", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y190": "SLICEM", + "SLICE_X11Y190": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y191": { + "bits": {}, + "grid_x": 24, + "grid_y": 9, + "segment": "SEG_CLBLM_L_X8Y191", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y191": "SLICEM", + "SLICE_X11Y191": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y192": { + "bits": {}, + "grid_x": 24, + "grid_y": 8, + "segment": "SEG_CLBLM_L_X8Y192", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y192": "SLICEM", + "SLICE_X11Y192": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y193": { + "bits": {}, + "grid_x": 24, + "grid_y": 7, + "segment": "SEG_CLBLM_L_X8Y193", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y193": "SLICEM", + "SLICE_X11Y193": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y194": { + "bits": {}, + "grid_x": 24, + "grid_y": 6, + "segment": "SEG_CLBLM_L_X8Y194", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y194": "SLICEM", + "SLICE_X11Y194": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y195": { + "bits": {}, + "grid_x": 24, + "grid_y": 5, + "segment": "SEG_CLBLM_L_X8Y195", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y195": "SLICEM", + "SLICE_X11Y195": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y196": { + "bits": {}, + "grid_x": 24, + "grid_y": 4, + "segment": "SEG_CLBLM_L_X8Y196", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y196": "SLICEM", + "SLICE_X11Y196": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y197": { + "bits": {}, + "grid_x": 24, + "grid_y": 3, + "segment": "SEG_CLBLM_L_X8Y197", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y197": "SLICEM", + "SLICE_X11Y197": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y198": { + "bits": {}, + "grid_x": 24, + "grid_y": 2, + "segment": "SEG_CLBLM_L_X8Y198", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y198": "SLICEM", + "SLICE_X11Y198": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y199": { + "bits": {}, + "grid_x": 24, + "grid_y": 1, + "segment": "SEG_CLBLM_L_X8Y199", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y199": "SLICEM", + "SLICE_X11Y199": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y2": { + "bits": {}, + "grid_x": 24, + "grid_y": 205, + "segment": "SEG_CLBLM_L_X8Y2", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y2": "SLICEM", + "SLICE_X11Y2": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y20": { + "bits": {}, + "grid_x": 24, + "grid_y": 187, + "segment": "SEG_CLBLM_L_X8Y20", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y20": "SLICEM", + "SLICE_X11Y20": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y21": { + "bits": {}, + "grid_x": 24, + "grid_y": 186, + "segment": "SEG_CLBLM_L_X8Y21", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y21": "SLICEM", + "SLICE_X11Y21": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y22": { + "bits": {}, + "grid_x": 24, + "grid_y": 185, + "segment": "SEG_CLBLM_L_X8Y22", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y22": "SLICEM", + "SLICE_X11Y22": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y23": { + "bits": {}, + "grid_x": 24, + "grid_y": 184, + "segment": "SEG_CLBLM_L_X8Y23", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y23": "SLICEM", + "SLICE_X11Y23": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y24": { + "bits": {}, + "grid_x": 24, + "grid_y": 183, + "segment": "SEG_CLBLM_L_X8Y24", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y24": "SLICEM", + "SLICE_X11Y24": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y25": { + "bits": {}, + "grid_x": 24, + "grid_y": 181, + "segment": "SEG_CLBLM_L_X8Y25", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y25": "SLICEM", + "SLICE_X11Y25": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y26": { + "bits": {}, + "grid_x": 24, + "grid_y": 180, + "segment": "SEG_CLBLM_L_X8Y26", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y26": "SLICEM", + "SLICE_X11Y26": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y27": { + "bits": {}, + "grid_x": 24, + "grid_y": 179, + "segment": "SEG_CLBLM_L_X8Y27", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y27": "SLICEM", + "SLICE_X11Y27": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y28": { + "bits": {}, + "grid_x": 24, + "grid_y": 178, + "segment": "SEG_CLBLM_L_X8Y28", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y28": "SLICEM", + "SLICE_X11Y28": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y29": { + "bits": {}, + "grid_x": 24, + "grid_y": 177, + "segment": "SEG_CLBLM_L_X8Y29", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y29": "SLICEM", + "SLICE_X11Y29": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y3": { + "bits": {}, + "grid_x": 24, + "grid_y": 204, + "segment": "SEG_CLBLM_L_X8Y3", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y3": "SLICEM", + "SLICE_X11Y3": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y30": { + "bits": {}, + "grid_x": 24, + "grid_y": 176, + "segment": "SEG_CLBLM_L_X8Y30", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y30": "SLICEM", + "SLICE_X11Y30": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y31": { + "bits": {}, + "grid_x": 24, + "grid_y": 175, + "segment": "SEG_CLBLM_L_X8Y31", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y31": "SLICEM", + "SLICE_X11Y31": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y32": { + "bits": {}, + "grid_x": 24, + "grid_y": 174, + "segment": "SEG_CLBLM_L_X8Y32", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y32": "SLICEM", + "SLICE_X11Y32": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y33": { + "bits": {}, + "grid_x": 24, + "grid_y": 173, + "segment": "SEG_CLBLM_L_X8Y33", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y33": "SLICEM", + "SLICE_X11Y33": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y34": { + "bits": {}, + "grid_x": 24, + "grid_y": 172, + "segment": "SEG_CLBLM_L_X8Y34", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y34": "SLICEM", + "SLICE_X11Y34": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y35": { + "bits": {}, + "grid_x": 24, + "grid_y": 171, + "segment": "SEG_CLBLM_L_X8Y35", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y35": "SLICEM", + "SLICE_X11Y35": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y36": { + "bits": {}, + "grid_x": 24, + "grid_y": 170, + "segment": "SEG_CLBLM_L_X8Y36", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y36": "SLICEM", + "SLICE_X11Y36": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y37": { + "bits": {}, + "grid_x": 24, + "grid_y": 169, + "segment": "SEG_CLBLM_L_X8Y37", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y37": "SLICEM", + "SLICE_X11Y37": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y38": { + "bits": {}, + "grid_x": 24, + "grid_y": 168, + "segment": "SEG_CLBLM_L_X8Y38", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y38": "SLICEM", + "SLICE_X11Y38": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y39": { + "bits": {}, + "grid_x": 24, + "grid_y": 167, + "segment": "SEG_CLBLM_L_X8Y39", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y39": "SLICEM", + "SLICE_X11Y39": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y4": { + "bits": {}, + "grid_x": 24, + "grid_y": 203, + "segment": "SEG_CLBLM_L_X8Y4", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y4": "SLICEM", + "SLICE_X11Y4": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y40": { + "bits": {}, + "grid_x": 24, + "grid_y": 166, + "segment": "SEG_CLBLM_L_X8Y40", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y40": "SLICEM", + "SLICE_X11Y40": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y41": { + "bits": {}, + "grid_x": 24, + "grid_y": 165, + "segment": "SEG_CLBLM_L_X8Y41", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y41": "SLICEM", + "SLICE_X11Y41": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y42": { + "bits": {}, + "grid_x": 24, + "grid_y": 164, + "segment": "SEG_CLBLM_L_X8Y42", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y42": "SLICEM", + "SLICE_X11Y42": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y43": { + "bits": {}, + "grid_x": 24, + "grid_y": 163, + "segment": "SEG_CLBLM_L_X8Y43", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y43": "SLICEM", + "SLICE_X11Y43": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y44": { + "bits": {}, + "grid_x": 24, + "grid_y": 162, + "segment": "SEG_CLBLM_L_X8Y44", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y44": "SLICEM", + "SLICE_X11Y44": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y45": { + "bits": {}, + "grid_x": 24, + "grid_y": 161, + "segment": "SEG_CLBLM_L_X8Y45", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y45": "SLICEM", + "SLICE_X11Y45": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y46": { + "bits": {}, + "grid_x": 24, + "grid_y": 160, + "segment": "SEG_CLBLM_L_X8Y46", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y46": "SLICEM", + "SLICE_X11Y46": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y47": { + "bits": {}, + "grid_x": 24, + "grid_y": 159, + "segment": "SEG_CLBLM_L_X8Y47", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y47": "SLICEM", + "SLICE_X11Y47": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y48": { + "bits": {}, + "grid_x": 24, + "grid_y": 158, + "segment": "SEG_CLBLM_L_X8Y48", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y48": "SLICEM", + "SLICE_X11Y48": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y49": { + "bits": {}, + "grid_x": 24, + "grid_y": 157, + "segment": "SEG_CLBLM_L_X8Y49", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y49": "SLICEM", + "SLICE_X11Y49": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y5": { + "bits": {}, + "grid_x": 24, + "grid_y": 202, + "segment": "SEG_CLBLM_L_X8Y5", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y5": "SLICEM", + "SLICE_X11Y5": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 155, + "segment": "SEG_CLBLM_L_X8Y50", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y50": "SLICEM", + "SLICE_X11Y50": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 154, + "segment": "SEG_CLBLM_L_X8Y51", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y51": "SLICEM", + "SLICE_X11Y51": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 153, + "segment": "SEG_CLBLM_L_X8Y52", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y52": "SLICEM", + "SLICE_X11Y52": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 152, + "segment": "SEG_CLBLM_L_X8Y53", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y53": "SLICEM", + "SLICE_X11Y53": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 151, + "segment": "SEG_CLBLM_L_X8Y54", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y54": "SLICEM", + "SLICE_X11Y54": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 150, + "segment": "SEG_CLBLM_L_X8Y55", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y55": "SLICEM", + "SLICE_X11Y55": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 149, + "segment": "SEG_CLBLM_L_X8Y56", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y56": "SLICEM", + "SLICE_X11Y56": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 148, + "segment": "SEG_CLBLM_L_X8Y57", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y57": "SLICEM", + "SLICE_X11Y57": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 147, + "segment": "SEG_CLBLM_L_X8Y58", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y58": "SLICEM", + "SLICE_X11Y58": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 146, + "segment": "SEG_CLBLM_L_X8Y59", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y59": "SLICEM", + "SLICE_X11Y59": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y6": { + "bits": {}, + "grid_x": 24, + "grid_y": 201, + "segment": "SEG_CLBLM_L_X8Y6", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y6": "SLICEM", + "SLICE_X11Y6": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 145, + "segment": "SEG_CLBLM_L_X8Y60", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y60": "SLICEM", + "SLICE_X11Y60": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 144, + "segment": "SEG_CLBLM_L_X8Y61", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y61": "SLICEM", + "SLICE_X11Y61": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 143, + "segment": "SEG_CLBLM_L_X8Y62", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y62": "SLICEM", + "SLICE_X11Y62": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 142, + "segment": "SEG_CLBLM_L_X8Y63", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y63": "SLICEM", + "SLICE_X11Y63": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 141, + "segment": "SEG_CLBLM_L_X8Y64", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y64": "SLICEM", + "SLICE_X11Y64": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 140, + "segment": "SEG_CLBLM_L_X8Y65", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y65": "SLICEM", + "SLICE_X11Y65": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 139, + "segment": "SEG_CLBLM_L_X8Y66", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y66": "SLICEM", + "SLICE_X11Y66": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 138, + "segment": "SEG_CLBLM_L_X8Y67", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y67": "SLICEM", + "SLICE_X11Y67": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 137, + "segment": "SEG_CLBLM_L_X8Y68", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y68": "SLICEM", + "SLICE_X11Y68": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 136, + "segment": "SEG_CLBLM_L_X8Y69", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y69": "SLICEM", + "SLICE_X11Y69": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y7": { + "bits": {}, + "grid_x": 24, + "grid_y": 200, + "segment": "SEG_CLBLM_L_X8Y7", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y7": "SLICEM", + "SLICE_X11Y7": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 135, + "segment": "SEG_CLBLM_L_X8Y70", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y70": "SLICEM", + "SLICE_X11Y70": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 134, + "segment": "SEG_CLBLM_L_X8Y71", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y71": "SLICEM", + "SLICE_X11Y71": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 133, + "segment": "SEG_CLBLM_L_X8Y72", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y72": "SLICEM", + "SLICE_X11Y72": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 132, + "segment": "SEG_CLBLM_L_X8Y73", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y73": "SLICEM", + "SLICE_X11Y73": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 131, + "segment": "SEG_CLBLM_L_X8Y74", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y74": "SLICEM", + "SLICE_X11Y74": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 129, + "segment": "SEG_CLBLM_L_X8Y75", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y75": "SLICEM", + "SLICE_X11Y75": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 128, + "segment": "SEG_CLBLM_L_X8Y76", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y76": "SLICEM", + "SLICE_X11Y76": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 127, + "segment": "SEG_CLBLM_L_X8Y77", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y77": "SLICEM", + "SLICE_X11Y77": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 126, + "segment": "SEG_CLBLM_L_X8Y78", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y78": "SLICEM", + "SLICE_X11Y78": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 125, + "segment": "SEG_CLBLM_L_X8Y79", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y79": "SLICEM", + "SLICE_X11Y79": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y8": { + "bits": {}, + "grid_x": 24, + "grid_y": 199, + "segment": "SEG_CLBLM_L_X8Y8", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y8": "SLICEM", + "SLICE_X11Y8": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 124, + "segment": "SEG_CLBLM_L_X8Y80", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y80": "SLICEM", + "SLICE_X11Y80": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 123, + "segment": "SEG_CLBLM_L_X8Y81", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y81": "SLICEM", + "SLICE_X11Y81": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 122, + "segment": "SEG_CLBLM_L_X8Y82", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y82": "SLICEM", + "SLICE_X11Y82": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 121, + "segment": "SEG_CLBLM_L_X8Y83", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y83": "SLICEM", + "SLICE_X11Y83": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 120, + "segment": "SEG_CLBLM_L_X8Y84", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y84": "SLICEM", + "SLICE_X11Y84": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 119, + "segment": "SEG_CLBLM_L_X8Y85", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y85": "SLICEM", + "SLICE_X11Y85": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 118, + "segment": "SEG_CLBLM_L_X8Y86", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y86": "SLICEM", + "SLICE_X11Y86": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 117, + "segment": "SEG_CLBLM_L_X8Y87", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y87": "SLICEM", + "SLICE_X11Y87": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 116, + "segment": "SEG_CLBLM_L_X8Y88", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y88": "SLICEM", + "SLICE_X11Y88": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 115, + "segment": "SEG_CLBLM_L_X8Y89", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y89": "SLICEM", + "SLICE_X11Y89": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y9": { + "bits": {}, + "grid_x": 24, + "grid_y": 198, + "segment": "SEG_CLBLM_L_X8Y9", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y9": "SLICEM", + "SLICE_X11Y9": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 114, + "segment": "SEG_CLBLM_L_X8Y90", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y90": "SLICEM", + "SLICE_X11Y90": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 113, + "segment": "SEG_CLBLM_L_X8Y91", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y91": "SLICEM", + "SLICE_X11Y91": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 112, + "segment": "SEG_CLBLM_L_X8Y92", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y92": "SLICEM", + "SLICE_X11Y92": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 111, + "segment": "SEG_CLBLM_L_X8Y93", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y93": "SLICEM", + "SLICE_X11Y93": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 110, + "segment": "SEG_CLBLM_L_X8Y94", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y94": "SLICEM", + "SLICE_X11Y94": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 109, + "segment": "SEG_CLBLM_L_X8Y95", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y95": "SLICEM", + "SLICE_X11Y95": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 108, + "segment": "SEG_CLBLM_L_X8Y96", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y96": "SLICEM", + "SLICE_X11Y96": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 107, + "segment": "SEG_CLBLM_L_X8Y97", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y97": "SLICEM", + "SLICE_X11Y97": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 106, + "segment": "SEG_CLBLM_L_X8Y98", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y98": "SLICEM", + "SLICE_X11Y98": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_L_X8Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 36, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 24, + "grid_y": 105, + "segment": "SEG_CLBLM_L_X8Y99", + "segment_type": "clblm_l", + "sites": { + "SLICE_X10Y99": "SLICEM", + "SLICE_X11Y99": "SLICEL" + }, + "type": "CLBLM_L" + }, + "CLBLM_R_X11Y0": { + "bits": {}, + "grid_x": 33, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X11Y0", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y0": "SLICEM", + "SLICE_X15Y0": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y1": { + "bits": {}, + "grid_x": 33, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X11Y1", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y1": "SLICEM", + "SLICE_X15Y1": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y10": { + "bits": {}, + "grid_x": 33, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X11Y10", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y10": "SLICEM", + "SLICE_X15Y10": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y100": { + "bits": {}, + "grid_x": 33, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X11Y100", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y100": "SLICEM", + "SLICE_X15Y100": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y101": { + "bits": {}, + "grid_x": 33, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X11Y101", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y101": "SLICEM", + "SLICE_X15Y101": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y102": { + "bits": {}, + "grid_x": 33, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X11Y102", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y102": "SLICEM", + "SLICE_X15Y102": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y103": { + "bits": {}, + "grid_x": 33, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X11Y103", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y103": "SLICEM", + "SLICE_X15Y103": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y104": { + "bits": {}, + "grid_x": 33, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X11Y104", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y104": "SLICEM", + "SLICE_X15Y104": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y105": { + "bits": {}, + "grid_x": 33, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X11Y105", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y105": "SLICEM", + "SLICE_X15Y105": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y106": { + "bits": {}, + "grid_x": 33, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X11Y106", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y106": "SLICEM", + "SLICE_X15Y106": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y107": { + "bits": {}, + "grid_x": 33, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X11Y107", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y107": "SLICEM", + "SLICE_X15Y107": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y108": { + "bits": {}, + "grid_x": 33, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X11Y108", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y108": "SLICEM", + "SLICE_X15Y108": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y109": { + "bits": {}, + "grid_x": 33, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X11Y109", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y109": "SLICEM", + "SLICE_X15Y109": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y11": { + "bits": {}, + "grid_x": 33, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X11Y11", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y11": "SLICEM", + "SLICE_X15Y11": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y110": { + "bits": {}, + "grid_x": 33, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X11Y110", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y110": "SLICEM", + "SLICE_X15Y110": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y111": { + "bits": {}, + "grid_x": 33, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X11Y111", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y111": "SLICEM", + "SLICE_X15Y111": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y112": { + "bits": {}, + "grid_x": 33, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X11Y112", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y112": "SLICEM", + "SLICE_X15Y112": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y113": { + "bits": {}, + "grid_x": 33, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X11Y113", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y113": "SLICEM", + "SLICE_X15Y113": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y114": { + "bits": {}, + "grid_x": 33, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X11Y114", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y114": "SLICEM", + "SLICE_X15Y114": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y115": { + "bits": {}, + "grid_x": 33, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X11Y115", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y115": "SLICEM", + "SLICE_X15Y115": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y116": { + "bits": {}, + "grid_x": 33, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X11Y116", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y116": "SLICEM", + "SLICE_X15Y116": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y117": { + "bits": {}, + "grid_x": 33, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X11Y117", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y117": "SLICEM", + "SLICE_X15Y117": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y118": { + "bits": {}, + "grid_x": 33, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X11Y118", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y118": "SLICEM", + "SLICE_X15Y118": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y119": { + "bits": {}, + "grid_x": 33, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X11Y119", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y119": "SLICEM", + "SLICE_X15Y119": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y12": { + "bits": {}, + "grid_x": 33, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X11Y12", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y12": "SLICEM", + "SLICE_X15Y12": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y120": { + "bits": {}, + "grid_x": 33, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X11Y120", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y120": "SLICEM", + "SLICE_X15Y120": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y121": { + "bits": {}, + "grid_x": 33, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X11Y121", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y121": "SLICEM", + "SLICE_X15Y121": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y122": { + "bits": {}, + "grid_x": 33, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X11Y122", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y122": "SLICEM", + "SLICE_X15Y122": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y123": { + "bits": {}, + "grid_x": 33, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X11Y123", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y123": "SLICEM", + "SLICE_X15Y123": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y124": { + "bits": {}, + "grid_x": 33, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X11Y124", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y124": "SLICEM", + "SLICE_X15Y124": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y125": { + "bits": {}, + "grid_x": 33, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X11Y125", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y125": "SLICEM", + "SLICE_X15Y125": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y126": { + "bits": {}, + "grid_x": 33, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X11Y126", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y126": "SLICEM", + "SLICE_X15Y126": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y127": { + "bits": {}, + "grid_x": 33, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X11Y127", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y127": "SLICEM", + "SLICE_X15Y127": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y128": { + "bits": {}, + "grid_x": 33, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X11Y128", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y128": "SLICEM", + "SLICE_X15Y128": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y129": { + "bits": {}, + "grid_x": 33, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X11Y129", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y129": "SLICEM", + "SLICE_X15Y129": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y13": { + "bits": {}, + "grid_x": 33, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X11Y13", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y13": "SLICEM", + "SLICE_X15Y13": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y130": { + "bits": {}, + "grid_x": 33, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X11Y130", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y130": "SLICEM", + "SLICE_X15Y130": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y131": { + "bits": {}, + "grid_x": 33, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X11Y131", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y131": "SLICEM", + "SLICE_X15Y131": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y132": { + "bits": {}, + "grid_x": 33, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X11Y132", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y132": "SLICEM", + "SLICE_X15Y132": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y133": { + "bits": {}, + "grid_x": 33, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X11Y133", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y133": "SLICEM", + "SLICE_X15Y133": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y134": { + "bits": {}, + "grid_x": 33, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X11Y134", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y134": "SLICEM", + "SLICE_X15Y134": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y135": { + "bits": {}, + "grid_x": 33, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X11Y135", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y135": "SLICEM", + "SLICE_X15Y135": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y136": { + "bits": {}, + "grid_x": 33, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X11Y136", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y136": "SLICEM", + "SLICE_X15Y136": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y137": { + "bits": {}, + "grid_x": 33, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X11Y137", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y137": "SLICEM", + "SLICE_X15Y137": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y138": { + "bits": {}, + "grid_x": 33, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X11Y138", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y138": "SLICEM", + "SLICE_X15Y138": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y139": { + "bits": {}, + "grid_x": 33, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X11Y139", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y139": "SLICEM", + "SLICE_X15Y139": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y14": { + "bits": {}, + "grid_x": 33, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X11Y14", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y14": "SLICEM", + "SLICE_X15Y14": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y140": { + "bits": {}, + "grid_x": 33, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X11Y140", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y140": "SLICEM", + "SLICE_X15Y140": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y141": { + "bits": {}, + "grid_x": 33, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X11Y141", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y141": "SLICEM", + "SLICE_X15Y141": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y142": { + "bits": {}, + "grid_x": 33, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X11Y142", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y142": "SLICEM", + "SLICE_X15Y142": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y143": { + "bits": {}, + "grid_x": 33, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X11Y143", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y143": "SLICEM", + "SLICE_X15Y143": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y144": { + "bits": {}, + "grid_x": 33, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X11Y144", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y144": "SLICEM", + "SLICE_X15Y144": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y145": { + "bits": {}, + "grid_x": 33, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X11Y145", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y145": "SLICEM", + "SLICE_X15Y145": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y146": { + "bits": {}, + "grid_x": 33, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X11Y146", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y146": "SLICEM", + "SLICE_X15Y146": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y147": { + "bits": {}, + "grid_x": 33, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X11Y147", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y147": "SLICEM", + "SLICE_X15Y147": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y148": { + "bits": {}, + "grid_x": 33, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X11Y148", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y148": "SLICEM", + "SLICE_X15Y148": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y149": { + "bits": {}, + "grid_x": 33, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X11Y149", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y149": "SLICEM", + "SLICE_X15Y149": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y15": { + "bits": {}, + "grid_x": 33, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X11Y15", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y15": "SLICEM", + "SLICE_X15Y15": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y150": { + "bits": {}, + "grid_x": 33, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X11Y150", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y150": "SLICEM", + "SLICE_X15Y150": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y151": { + "bits": {}, + "grid_x": 33, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X11Y151", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y151": "SLICEM", + "SLICE_X15Y151": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y152": { + "bits": {}, + "grid_x": 33, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X11Y152", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y152": "SLICEM", + "SLICE_X15Y152": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y153": { + "bits": {}, + "grid_x": 33, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X11Y153", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y153": "SLICEM", + "SLICE_X15Y153": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y154": { + "bits": {}, + "grid_x": 33, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X11Y154", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y154": "SLICEM", + "SLICE_X15Y154": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y155": { + "bits": {}, + "grid_x": 33, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X11Y155", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y155": "SLICEM", + "SLICE_X15Y155": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y156": { + "bits": {}, + "grid_x": 33, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X11Y156", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y156": "SLICEM", + "SLICE_X15Y156": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y157": { + "bits": {}, + "grid_x": 33, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X11Y157", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y157": "SLICEM", + "SLICE_X15Y157": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y158": { + "bits": {}, + "grid_x": 33, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X11Y158", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y158": "SLICEM", + "SLICE_X15Y158": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y159": { + "bits": {}, + "grid_x": 33, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X11Y159", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y159": "SLICEM", + "SLICE_X15Y159": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y16": { + "bits": {}, + "grid_x": 33, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X11Y16", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y16": "SLICEM", + "SLICE_X15Y16": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y160": { + "bits": {}, + "grid_x": 33, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X11Y160", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y160": "SLICEM", + "SLICE_X15Y160": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y161": { + "bits": {}, + "grid_x": 33, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X11Y161", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y161": "SLICEM", + "SLICE_X15Y161": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y162": { + "bits": {}, + "grid_x": 33, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X11Y162", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y162": "SLICEM", + "SLICE_X15Y162": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y163": { + "bits": {}, + "grid_x": 33, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X11Y163", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y163": "SLICEM", + "SLICE_X15Y163": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y164": { + "bits": {}, + "grid_x": 33, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X11Y164", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y164": "SLICEM", + "SLICE_X15Y164": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y165": { + "bits": {}, + "grid_x": 33, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X11Y165", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y165": "SLICEM", + "SLICE_X15Y165": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y166": { + "bits": {}, + "grid_x": 33, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X11Y166", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y166": "SLICEM", + "SLICE_X15Y166": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y167": { + "bits": {}, + "grid_x": 33, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X11Y167", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y167": "SLICEM", + "SLICE_X15Y167": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y168": { + "bits": {}, + "grid_x": 33, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X11Y168", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y168": "SLICEM", + "SLICE_X15Y168": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y169": { + "bits": {}, + "grid_x": 33, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X11Y169", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y169": "SLICEM", + "SLICE_X15Y169": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y17": { + "bits": {}, + "grid_x": 33, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X11Y17", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y17": "SLICEM", + "SLICE_X15Y17": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y170": { + "bits": {}, + "grid_x": 33, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X11Y170", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y170": "SLICEM", + "SLICE_X15Y170": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y171": { + "bits": {}, + "grid_x": 33, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X11Y171", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y171": "SLICEM", + "SLICE_X15Y171": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y172": { + "bits": {}, + "grid_x": 33, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X11Y172", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y172": "SLICEM", + "SLICE_X15Y172": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y173": { + "bits": {}, + "grid_x": 33, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X11Y173", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y173": "SLICEM", + "SLICE_X15Y173": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y174": { + "bits": {}, + "grid_x": 33, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X11Y174", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y174": "SLICEM", + "SLICE_X15Y174": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y175": { + "bits": {}, + "grid_x": 33, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X11Y175", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y175": "SLICEM", + "SLICE_X15Y175": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y176": { + "bits": {}, + "grid_x": 33, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X11Y176", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y176": "SLICEM", + "SLICE_X15Y176": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y177": { + "bits": {}, + "grid_x": 33, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X11Y177", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y177": "SLICEM", + "SLICE_X15Y177": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y178": { + "bits": {}, + "grid_x": 33, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X11Y178", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y178": "SLICEM", + "SLICE_X15Y178": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y179": { + "bits": {}, + "grid_x": 33, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X11Y179", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y179": "SLICEM", + "SLICE_X15Y179": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y18": { + "bits": {}, + "grid_x": 33, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X11Y18", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y18": "SLICEM", + "SLICE_X15Y18": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y180": { + "bits": {}, + "grid_x": 33, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X11Y180", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y180": "SLICEM", + "SLICE_X15Y180": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y181": { + "bits": {}, + "grid_x": 33, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X11Y181", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y181": "SLICEM", + "SLICE_X15Y181": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y182": { + "bits": {}, + "grid_x": 33, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X11Y182", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y182": "SLICEM", + "SLICE_X15Y182": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y183": { + "bits": {}, + "grid_x": 33, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X11Y183", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y183": "SLICEM", + "SLICE_X15Y183": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y184": { + "bits": {}, + "grid_x": 33, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X11Y184", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y184": "SLICEM", + "SLICE_X15Y184": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y185": { + "bits": {}, + "grid_x": 33, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X11Y185", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y185": "SLICEM", + "SLICE_X15Y185": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y186": { + "bits": {}, + "grid_x": 33, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X11Y186", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y186": "SLICEM", + "SLICE_X15Y186": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y187": { + "bits": {}, + "grid_x": 33, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X11Y187", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y187": "SLICEM", + "SLICE_X15Y187": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y188": { + "bits": {}, + "grid_x": 33, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X11Y188", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y188": "SLICEM", + "SLICE_X15Y188": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y189": { + "bits": {}, + "grid_x": 33, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X11Y189", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y189": "SLICEM", + "SLICE_X15Y189": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y19": { + "bits": {}, + "grid_x": 33, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X11Y19", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y19": "SLICEM", + "SLICE_X15Y19": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y190": { + "bits": {}, + "grid_x": 33, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X11Y190", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y190": "SLICEM", + "SLICE_X15Y190": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y191": { + "bits": {}, + "grid_x": 33, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X11Y191", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y191": "SLICEM", + "SLICE_X15Y191": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y192": { + "bits": {}, + "grid_x": 33, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X11Y192", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y192": "SLICEM", + "SLICE_X15Y192": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y193": { + "bits": {}, + "grid_x": 33, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X11Y193", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y193": "SLICEM", + "SLICE_X15Y193": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y194": { + "bits": {}, + "grid_x": 33, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X11Y194", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y194": "SLICEM", + "SLICE_X15Y194": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y195": { + "bits": {}, + "grid_x": 33, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X11Y195", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y195": "SLICEM", + "SLICE_X15Y195": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y196": { + "bits": {}, + "grid_x": 33, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X11Y196", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y196": "SLICEM", + "SLICE_X15Y196": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y197": { + "bits": {}, + "grid_x": 33, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X11Y197", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y197": "SLICEM", + "SLICE_X15Y197": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y198": { + "bits": {}, + "grid_x": 33, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X11Y198", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y198": "SLICEM", + "SLICE_X15Y198": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y199": { + "bits": {}, + "grid_x": 33, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X11Y199", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y199": "SLICEM", + "SLICE_X15Y199": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y2": { + "bits": {}, + "grid_x": 33, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X11Y2", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y2": "SLICEM", + "SLICE_X15Y2": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y20": { + "bits": {}, + "grid_x": 33, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X11Y20", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y20": "SLICEM", + "SLICE_X15Y20": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y21": { + "bits": {}, + "grid_x": 33, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X11Y21", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y21": "SLICEM", + "SLICE_X15Y21": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y22": { + "bits": {}, + "grid_x": 33, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X11Y22", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y22": "SLICEM", + "SLICE_X15Y22": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y23": { + "bits": {}, + "grid_x": 33, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X11Y23", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y23": "SLICEM", + "SLICE_X15Y23": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y24": { + "bits": {}, + "grid_x": 33, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X11Y24", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y24": "SLICEM", + "SLICE_X15Y24": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y25": { + "bits": {}, + "grid_x": 33, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X11Y25", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y25": "SLICEM", + "SLICE_X15Y25": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y26": { + "bits": {}, + "grid_x": 33, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X11Y26", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y26": "SLICEM", + "SLICE_X15Y26": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y27": { + "bits": {}, + "grid_x": 33, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X11Y27", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y27": "SLICEM", + "SLICE_X15Y27": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y28": { + "bits": {}, + "grid_x": 33, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X11Y28", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y28": "SLICEM", + "SLICE_X15Y28": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y29": { + "bits": {}, + "grid_x": 33, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X11Y29", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y29": "SLICEM", + "SLICE_X15Y29": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y3": { + "bits": {}, + "grid_x": 33, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X11Y3", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y3": "SLICEM", + "SLICE_X15Y3": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y30": { + "bits": {}, + "grid_x": 33, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X11Y30", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y30": "SLICEM", + "SLICE_X15Y30": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y31": { + "bits": {}, + "grid_x": 33, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X11Y31", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y31": "SLICEM", + "SLICE_X15Y31": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y32": { + "bits": {}, + "grid_x": 33, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X11Y32", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y32": "SLICEM", + "SLICE_X15Y32": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y33": { + "bits": {}, + "grid_x": 33, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X11Y33", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y33": "SLICEM", + "SLICE_X15Y33": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y34": { + "bits": {}, + "grid_x": 33, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X11Y34", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y34": "SLICEM", + "SLICE_X15Y34": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y35": { + "bits": {}, + "grid_x": 33, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X11Y35", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y35": "SLICEM", + "SLICE_X15Y35": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y36": { + "bits": {}, + "grid_x": 33, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X11Y36", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y36": "SLICEM", + "SLICE_X15Y36": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y37": { + "bits": {}, + "grid_x": 33, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X11Y37", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y37": "SLICEM", + "SLICE_X15Y37": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y38": { + "bits": {}, + "grid_x": 33, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X11Y38", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y38": "SLICEM", + "SLICE_X15Y38": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y39": { + "bits": {}, + "grid_x": 33, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X11Y39", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y39": "SLICEM", + "SLICE_X15Y39": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y4": { + "bits": {}, + "grid_x": 33, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X11Y4", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y4": "SLICEM", + "SLICE_X15Y4": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y40": { + "bits": {}, + "grid_x": 33, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X11Y40", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y40": "SLICEM", + "SLICE_X15Y40": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y41": { + "bits": {}, + "grid_x": 33, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X11Y41", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y41": "SLICEM", + "SLICE_X15Y41": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y42": { + "bits": {}, + "grid_x": 33, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X11Y42", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y42": "SLICEM", + "SLICE_X15Y42": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y43": { + "bits": {}, + "grid_x": 33, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X11Y43", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y43": "SLICEM", + "SLICE_X15Y43": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y44": { + "bits": {}, + "grid_x": 33, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X11Y44", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y44": "SLICEM", + "SLICE_X15Y44": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y45": { + "bits": {}, + "grid_x": 33, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X11Y45", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y45": "SLICEM", + "SLICE_X15Y45": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y46": { + "bits": {}, + "grid_x": 33, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X11Y46", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y46": "SLICEM", + "SLICE_X15Y46": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y47": { + "bits": {}, + "grid_x": 33, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X11Y47", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y47": "SLICEM", + "SLICE_X15Y47": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y48": { + "bits": {}, + "grid_x": 33, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X11Y48", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y48": "SLICEM", + "SLICE_X15Y48": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y49": { + "bits": {}, + "grid_x": 33, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X11Y49", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y49": "SLICEM", + "SLICE_X15Y49": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y5": { + "bits": {}, + "grid_x": 33, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X11Y5", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y5": "SLICEM", + "SLICE_X15Y5": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X11Y50", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y50": "SLICEM", + "SLICE_X15Y50": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X11Y51", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y51": "SLICEM", + "SLICE_X15Y51": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X11Y52", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y52": "SLICEM", + "SLICE_X15Y52": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X11Y53", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y53": "SLICEM", + "SLICE_X15Y53": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X11Y54", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y54": "SLICEM", + "SLICE_X15Y54": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X11Y55", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y55": "SLICEM", + "SLICE_X15Y55": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X11Y56", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y56": "SLICEM", + "SLICE_X15Y56": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X11Y57", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y57": "SLICEM", + "SLICE_X15Y57": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X11Y58", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y58": "SLICEM", + "SLICE_X15Y58": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X11Y59", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y59": "SLICEM", + "SLICE_X15Y59": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y6": { + "bits": {}, + "grid_x": 33, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X11Y6", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y6": "SLICEM", + "SLICE_X15Y6": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X11Y60", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y60": "SLICEM", + "SLICE_X15Y60": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X11Y61", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y61": "SLICEM", + "SLICE_X15Y61": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X11Y62", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y62": "SLICEM", + "SLICE_X15Y62": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X11Y63", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y63": "SLICEM", + "SLICE_X15Y63": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X11Y64", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y64": "SLICEM", + "SLICE_X15Y64": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X11Y65", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y65": "SLICEM", + "SLICE_X15Y65": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X11Y66", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y66": "SLICEM", + "SLICE_X15Y66": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X11Y67", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y67": "SLICEM", + "SLICE_X15Y67": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X11Y68", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y68": "SLICEM", + "SLICE_X15Y68": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X11Y69", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y69": "SLICEM", + "SLICE_X15Y69": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y7": { + "bits": {}, + "grid_x": 33, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X11Y7", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y7": "SLICEM", + "SLICE_X15Y7": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X11Y70", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y70": "SLICEM", + "SLICE_X15Y70": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X11Y71", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y71": "SLICEM", + "SLICE_X15Y71": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X11Y72", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y72": "SLICEM", + "SLICE_X15Y72": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X11Y73", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y73": "SLICEM", + "SLICE_X15Y73": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X11Y74", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y74": "SLICEM", + "SLICE_X15Y74": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X11Y75", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y75": "SLICEM", + "SLICE_X15Y75": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X11Y76", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y76": "SLICEM", + "SLICE_X15Y76": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X11Y77", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y77": "SLICEM", + "SLICE_X15Y77": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X11Y78", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y78": "SLICEM", + "SLICE_X15Y78": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X11Y79", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y79": "SLICEM", + "SLICE_X15Y79": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y8": { + "bits": {}, + "grid_x": 33, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X11Y8", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y8": "SLICEM", + "SLICE_X15Y8": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X11Y80", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y80": "SLICEM", + "SLICE_X15Y80": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X11Y81", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y81": "SLICEM", + "SLICE_X15Y81": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X11Y82", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y82": "SLICEM", + "SLICE_X15Y82": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X11Y83", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y83": "SLICEM", + "SLICE_X15Y83": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X11Y84", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y84": "SLICEM", + "SLICE_X15Y84": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X11Y85", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y85": "SLICEM", + "SLICE_X15Y85": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X11Y86", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y86": "SLICEM", + "SLICE_X15Y86": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X11Y87", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y87": "SLICEM", + "SLICE_X15Y87": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X11Y88", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y88": "SLICEM", + "SLICE_X15Y88": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X11Y89", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y89": "SLICEM", + "SLICE_X15Y89": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y9": { + "bits": {}, + "grid_x": 33, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X11Y9", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y9": "SLICEM", + "SLICE_X15Y9": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X11Y90", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y90": "SLICEM", + "SLICE_X15Y90": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X11Y91", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y91": "SLICEM", + "SLICE_X15Y91": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X11Y92", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y92": "SLICEM", + "SLICE_X15Y92": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X11Y93", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y93": "SLICEM", + "SLICE_X15Y93": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X11Y94", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y94": "SLICEM", + "SLICE_X15Y94": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X11Y95", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y95": "SLICEM", + "SLICE_X15Y95": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X11Y96", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y96": "SLICEM", + "SLICE_X15Y96": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X11Y97", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y97": "SLICEM", + "SLICE_X15Y97": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X11Y98", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y98": "SLICEM", + "SLICE_X15Y98": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X11Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 36, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 33, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X11Y99", + "segment_type": "clblm_r", + "sites": { + "SLICE_X14Y99": "SLICEM", + "SLICE_X15Y99": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y0": { + "bits": {}, + "grid_x": 37, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X13Y0", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y0": "SLICEM", + "SLICE_X19Y0": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y1": { + "bits": {}, + "grid_x": 37, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X13Y1", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y1": "SLICEM", + "SLICE_X19Y1": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y10": { + "bits": {}, + "grid_x": 37, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X13Y10", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y10": "SLICEM", + "SLICE_X19Y10": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y100": { + "bits": {}, + "grid_x": 37, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X13Y100", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y100": "SLICEM", + "SLICE_X19Y100": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y101": { + "bits": {}, + "grid_x": 37, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X13Y101", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y101": "SLICEM", + "SLICE_X19Y101": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y102": { + "bits": {}, + "grid_x": 37, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X13Y102", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y102": "SLICEM", + "SLICE_X19Y102": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y103": { + "bits": {}, + "grid_x": 37, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X13Y103", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y103": "SLICEM", + "SLICE_X19Y103": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y104": { + "bits": {}, + "grid_x": 37, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X13Y104", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y104": "SLICEM", + "SLICE_X19Y104": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y105": { + "bits": {}, + "grid_x": 37, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X13Y105", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y105": "SLICEM", + "SLICE_X19Y105": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y106": { + "bits": {}, + "grid_x": 37, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X13Y106", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y106": "SLICEM", + "SLICE_X19Y106": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y107": { + "bits": {}, + "grid_x": 37, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X13Y107", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y107": "SLICEM", + "SLICE_X19Y107": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y108": { + "bits": {}, + "grid_x": 37, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X13Y108", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y108": "SLICEM", + "SLICE_X19Y108": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y109": { + "bits": {}, + "grid_x": 37, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X13Y109", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y109": "SLICEM", + "SLICE_X19Y109": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y11": { + "bits": {}, + "grid_x": 37, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X13Y11", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y11": "SLICEM", + "SLICE_X19Y11": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y110": { + "bits": {}, + "grid_x": 37, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X13Y110", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y110": "SLICEM", + "SLICE_X19Y110": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y111": { + "bits": {}, + "grid_x": 37, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X13Y111", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y111": "SLICEM", + "SLICE_X19Y111": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y112": { + "bits": {}, + "grid_x": 37, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X13Y112", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y112": "SLICEM", + "SLICE_X19Y112": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y113": { + "bits": {}, + "grid_x": 37, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X13Y113", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y113": "SLICEM", + "SLICE_X19Y113": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y114": { + "bits": {}, + "grid_x": 37, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X13Y114", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y114": "SLICEM", + "SLICE_X19Y114": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y115": { + "bits": {}, + "grid_x": 37, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X13Y115", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y115": "SLICEM", + "SLICE_X19Y115": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y116": { + "bits": {}, + "grid_x": 37, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X13Y116", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y116": "SLICEM", + "SLICE_X19Y116": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y117": { + "bits": {}, + "grid_x": 37, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X13Y117", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y117": "SLICEM", + "SLICE_X19Y117": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y118": { + "bits": {}, + "grid_x": 37, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X13Y118", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y118": "SLICEM", + "SLICE_X19Y118": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y119": { + "bits": {}, + "grid_x": 37, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X13Y119", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y119": "SLICEM", + "SLICE_X19Y119": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y12": { + "bits": {}, + "grid_x": 37, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X13Y12", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y12": "SLICEM", + "SLICE_X19Y12": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y120": { + "bits": {}, + "grid_x": 37, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X13Y120", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y120": "SLICEM", + "SLICE_X19Y120": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y121": { + "bits": {}, + "grid_x": 37, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X13Y121", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y121": "SLICEM", + "SLICE_X19Y121": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y122": { + "bits": {}, + "grid_x": 37, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X13Y122", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y122": "SLICEM", + "SLICE_X19Y122": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y123": { + "bits": {}, + "grid_x": 37, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X13Y123", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y123": "SLICEM", + "SLICE_X19Y123": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y124": { + "bits": {}, + "grid_x": 37, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X13Y124", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y124": "SLICEM", + "SLICE_X19Y124": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y125": { + "bits": {}, + "grid_x": 37, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X13Y125", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y125": "SLICEM", + "SLICE_X19Y125": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y126": { + "bits": {}, + "grid_x": 37, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X13Y126", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y126": "SLICEM", + "SLICE_X19Y126": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y127": { + "bits": {}, + "grid_x": 37, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X13Y127", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y127": "SLICEM", + "SLICE_X19Y127": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y128": { + "bits": {}, + "grid_x": 37, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X13Y128", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y128": "SLICEM", + "SLICE_X19Y128": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y129": { + "bits": {}, + "grid_x": 37, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X13Y129", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y129": "SLICEM", + "SLICE_X19Y129": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y13": { + "bits": {}, + "grid_x": 37, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X13Y13", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y13": "SLICEM", + "SLICE_X19Y13": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y130": { + "bits": {}, + "grid_x": 37, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X13Y130", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y130": "SLICEM", + "SLICE_X19Y130": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y131": { + "bits": {}, + "grid_x": 37, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X13Y131", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y131": "SLICEM", + "SLICE_X19Y131": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y132": { + "bits": {}, + "grid_x": 37, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X13Y132", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y132": "SLICEM", + "SLICE_X19Y132": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y133": { + "bits": {}, + "grid_x": 37, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X13Y133", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y133": "SLICEM", + "SLICE_X19Y133": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y134": { + "bits": {}, + "grid_x": 37, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X13Y134", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y134": "SLICEM", + "SLICE_X19Y134": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y135": { + "bits": {}, + "grid_x": 37, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X13Y135", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y135": "SLICEM", + "SLICE_X19Y135": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y136": { + "bits": {}, + "grid_x": 37, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X13Y136", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y136": "SLICEM", + "SLICE_X19Y136": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y137": { + "bits": {}, + "grid_x": 37, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X13Y137", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y137": "SLICEM", + "SLICE_X19Y137": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y138": { + "bits": {}, + "grid_x": 37, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X13Y138", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y138": "SLICEM", + "SLICE_X19Y138": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y139": { + "bits": {}, + "grid_x": 37, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X13Y139", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y139": "SLICEM", + "SLICE_X19Y139": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y14": { + "bits": {}, + "grid_x": 37, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X13Y14", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y14": "SLICEM", + "SLICE_X19Y14": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y140": { + "bits": {}, + "grid_x": 37, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X13Y140", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y140": "SLICEM", + "SLICE_X19Y140": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y141": { + "bits": {}, + "grid_x": 37, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X13Y141", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y141": "SLICEM", + "SLICE_X19Y141": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y142": { + "bits": {}, + "grid_x": 37, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X13Y142", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y142": "SLICEM", + "SLICE_X19Y142": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y143": { + "bits": {}, + "grid_x": 37, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X13Y143", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y143": "SLICEM", + "SLICE_X19Y143": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y144": { + "bits": {}, + "grid_x": 37, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X13Y144", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y144": "SLICEM", + "SLICE_X19Y144": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y145": { + "bits": {}, + "grid_x": 37, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X13Y145", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y145": "SLICEM", + "SLICE_X19Y145": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y146": { + "bits": {}, + "grid_x": 37, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X13Y146", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y146": "SLICEM", + "SLICE_X19Y146": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y147": { + "bits": {}, + "grid_x": 37, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X13Y147", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y147": "SLICEM", + "SLICE_X19Y147": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y148": { + "bits": {}, + "grid_x": 37, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X13Y148", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y148": "SLICEM", + "SLICE_X19Y148": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y149": { + "bits": {}, + "grid_x": 37, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X13Y149", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y149": "SLICEM", + "SLICE_X19Y149": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y15": { + "bits": {}, + "grid_x": 37, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X13Y15", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y15": "SLICEM", + "SLICE_X19Y15": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y150": { + "bits": {}, + "grid_x": 37, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X13Y150", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y150": "SLICEM", + "SLICE_X19Y150": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y151": { + "bits": {}, + "grid_x": 37, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X13Y151", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y151": "SLICEM", + "SLICE_X19Y151": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y152": { + "bits": {}, + "grid_x": 37, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X13Y152", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y152": "SLICEM", + "SLICE_X19Y152": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y153": { + "bits": {}, + "grid_x": 37, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X13Y153", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y153": "SLICEM", + "SLICE_X19Y153": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y154": { + "bits": {}, + "grid_x": 37, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X13Y154", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y154": "SLICEM", + "SLICE_X19Y154": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y155": { + "bits": {}, + "grid_x": 37, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X13Y155", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y155": "SLICEM", + "SLICE_X19Y155": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y156": { + "bits": {}, + "grid_x": 37, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X13Y156", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y156": "SLICEM", + "SLICE_X19Y156": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y157": { + "bits": {}, + "grid_x": 37, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X13Y157", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y157": "SLICEM", + "SLICE_X19Y157": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y158": { + "bits": {}, + "grid_x": 37, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X13Y158", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y158": "SLICEM", + "SLICE_X19Y158": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y159": { + "bits": {}, + "grid_x": 37, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X13Y159", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y159": "SLICEM", + "SLICE_X19Y159": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y16": { + "bits": {}, + "grid_x": 37, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X13Y16", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y16": "SLICEM", + "SLICE_X19Y16": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y160": { + "bits": {}, + "grid_x": 37, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X13Y160", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y160": "SLICEM", + "SLICE_X19Y160": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y161": { + "bits": {}, + "grid_x": 37, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X13Y161", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y161": "SLICEM", + "SLICE_X19Y161": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y162": { + "bits": {}, + "grid_x": 37, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X13Y162", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y162": "SLICEM", + "SLICE_X19Y162": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y163": { + "bits": {}, + "grid_x": 37, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X13Y163", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y163": "SLICEM", + "SLICE_X19Y163": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y164": { + "bits": {}, + "grid_x": 37, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X13Y164", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y164": "SLICEM", + "SLICE_X19Y164": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y165": { + "bits": {}, + "grid_x": 37, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X13Y165", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y165": "SLICEM", + "SLICE_X19Y165": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y166": { + "bits": {}, + "grid_x": 37, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X13Y166", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y166": "SLICEM", + "SLICE_X19Y166": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y167": { + "bits": {}, + "grid_x": 37, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X13Y167", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y167": "SLICEM", + "SLICE_X19Y167": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y168": { + "bits": {}, + "grid_x": 37, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X13Y168", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y168": "SLICEM", + "SLICE_X19Y168": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y169": { + "bits": {}, + "grid_x": 37, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X13Y169", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y169": "SLICEM", + "SLICE_X19Y169": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y17": { + "bits": {}, + "grid_x": 37, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X13Y17", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y17": "SLICEM", + "SLICE_X19Y17": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y170": { + "bits": {}, + "grid_x": 37, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X13Y170", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y170": "SLICEM", + "SLICE_X19Y170": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y171": { + "bits": {}, + "grid_x": 37, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X13Y171", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y171": "SLICEM", + "SLICE_X19Y171": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y172": { + "bits": {}, + "grid_x": 37, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X13Y172", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y172": "SLICEM", + "SLICE_X19Y172": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y173": { + "bits": {}, + "grid_x": 37, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X13Y173", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y173": "SLICEM", + "SLICE_X19Y173": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y174": { + "bits": {}, + "grid_x": 37, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X13Y174", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y174": "SLICEM", + "SLICE_X19Y174": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y175": { + "bits": {}, + "grid_x": 37, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X13Y175", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y175": "SLICEM", + "SLICE_X19Y175": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y176": { + "bits": {}, + "grid_x": 37, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X13Y176", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y176": "SLICEM", + "SLICE_X19Y176": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y177": { + "bits": {}, + "grid_x": 37, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X13Y177", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y177": "SLICEM", + "SLICE_X19Y177": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y178": { + "bits": {}, + "grid_x": 37, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X13Y178", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y178": "SLICEM", + "SLICE_X19Y178": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y179": { + "bits": {}, + "grid_x": 37, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X13Y179", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y179": "SLICEM", + "SLICE_X19Y179": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y18": { + "bits": {}, + "grid_x": 37, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X13Y18", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y18": "SLICEM", + "SLICE_X19Y18": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y180": { + "bits": {}, + "grid_x": 37, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X13Y180", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y180": "SLICEM", + "SLICE_X19Y180": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y181": { + "bits": {}, + "grid_x": 37, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X13Y181", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y181": "SLICEM", + "SLICE_X19Y181": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y182": { + "bits": {}, + "grid_x": 37, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X13Y182", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y182": "SLICEM", + "SLICE_X19Y182": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y183": { + "bits": {}, + "grid_x": 37, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X13Y183", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y183": "SLICEM", + "SLICE_X19Y183": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y184": { + "bits": {}, + "grid_x": 37, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X13Y184", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y184": "SLICEM", + "SLICE_X19Y184": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y185": { + "bits": {}, + "grid_x": 37, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X13Y185", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y185": "SLICEM", + "SLICE_X19Y185": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y186": { + "bits": {}, + "grid_x": 37, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X13Y186", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y186": "SLICEM", + "SLICE_X19Y186": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y187": { + "bits": {}, + "grid_x": 37, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X13Y187", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y187": "SLICEM", + "SLICE_X19Y187": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y188": { + "bits": {}, + "grid_x": 37, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X13Y188", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y188": "SLICEM", + "SLICE_X19Y188": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y189": { + "bits": {}, + "grid_x": 37, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X13Y189", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y189": "SLICEM", + "SLICE_X19Y189": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y19": { + "bits": {}, + "grid_x": 37, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X13Y19", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y19": "SLICEM", + "SLICE_X19Y19": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y190": { + "bits": {}, + "grid_x": 37, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X13Y190", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y190": "SLICEM", + "SLICE_X19Y190": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y191": { + "bits": {}, + "grid_x": 37, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X13Y191", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y191": "SLICEM", + "SLICE_X19Y191": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y192": { + "bits": {}, + "grid_x": 37, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X13Y192", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y192": "SLICEM", + "SLICE_X19Y192": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y193": { + "bits": {}, + "grid_x": 37, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X13Y193", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y193": "SLICEM", + "SLICE_X19Y193": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y194": { + "bits": {}, + "grid_x": 37, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X13Y194", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y194": "SLICEM", + "SLICE_X19Y194": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y195": { + "bits": {}, + "grid_x": 37, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X13Y195", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y195": "SLICEM", + "SLICE_X19Y195": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y196": { + "bits": {}, + "grid_x": 37, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X13Y196", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y196": "SLICEM", + "SLICE_X19Y196": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y197": { + "bits": {}, + "grid_x": 37, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X13Y197", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y197": "SLICEM", + "SLICE_X19Y197": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y198": { + "bits": {}, + "grid_x": 37, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X13Y198", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y198": "SLICEM", + "SLICE_X19Y198": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y199": { + "bits": {}, + "grid_x": 37, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X13Y199", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y199": "SLICEM", + "SLICE_X19Y199": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y2": { + "bits": {}, + "grid_x": 37, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X13Y2", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y2": "SLICEM", + "SLICE_X19Y2": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y20": { + "bits": {}, + "grid_x": 37, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X13Y20", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y20": "SLICEM", + "SLICE_X19Y20": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y21": { + "bits": {}, + "grid_x": 37, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X13Y21", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y21": "SLICEM", + "SLICE_X19Y21": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y22": { + "bits": {}, + "grid_x": 37, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X13Y22", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y22": "SLICEM", + "SLICE_X19Y22": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y23": { + "bits": {}, + "grid_x": 37, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X13Y23", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y23": "SLICEM", + "SLICE_X19Y23": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y24": { + "bits": {}, + "grid_x": 37, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X13Y24", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y24": "SLICEM", + "SLICE_X19Y24": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y25": { + "bits": {}, + "grid_x": 37, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X13Y25", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y25": "SLICEM", + "SLICE_X19Y25": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y26": { + "bits": {}, + "grid_x": 37, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X13Y26", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y26": "SLICEM", + "SLICE_X19Y26": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y27": { + "bits": {}, + "grid_x": 37, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X13Y27", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y27": "SLICEM", + "SLICE_X19Y27": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y28": { + "bits": {}, + "grid_x": 37, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X13Y28", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y28": "SLICEM", + "SLICE_X19Y28": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y29": { + "bits": {}, + "grid_x": 37, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X13Y29", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y29": "SLICEM", + "SLICE_X19Y29": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y3": { + "bits": {}, + "grid_x": 37, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X13Y3", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y3": "SLICEM", + "SLICE_X19Y3": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y30": { + "bits": {}, + "grid_x": 37, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X13Y30", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y30": "SLICEM", + "SLICE_X19Y30": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y31": { + "bits": {}, + "grid_x": 37, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X13Y31", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y31": "SLICEM", + "SLICE_X19Y31": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y32": { + "bits": {}, + "grid_x": 37, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X13Y32", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y32": "SLICEM", + "SLICE_X19Y32": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y33": { + "bits": {}, + "grid_x": 37, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X13Y33", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y33": "SLICEM", + "SLICE_X19Y33": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y34": { + "bits": {}, + "grid_x": 37, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X13Y34", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y34": "SLICEM", + "SLICE_X19Y34": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y35": { + "bits": {}, + "grid_x": 37, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X13Y35", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y35": "SLICEM", + "SLICE_X19Y35": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y36": { + "bits": {}, + "grid_x": 37, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X13Y36", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y36": "SLICEM", + "SLICE_X19Y36": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y37": { + "bits": {}, + "grid_x": 37, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X13Y37", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y37": "SLICEM", + "SLICE_X19Y37": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y38": { + "bits": {}, + "grid_x": 37, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X13Y38", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y38": "SLICEM", + "SLICE_X19Y38": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y39": { + "bits": {}, + "grid_x": 37, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X13Y39", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y39": "SLICEM", + "SLICE_X19Y39": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y4": { + "bits": {}, + "grid_x": 37, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X13Y4", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y4": "SLICEM", + "SLICE_X19Y4": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y40": { + "bits": {}, + "grid_x": 37, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X13Y40", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y40": "SLICEM", + "SLICE_X19Y40": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y41": { + "bits": {}, + "grid_x": 37, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X13Y41", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y41": "SLICEM", + "SLICE_X19Y41": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y42": { + "bits": {}, + "grid_x": 37, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X13Y42", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y42": "SLICEM", + "SLICE_X19Y42": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y43": { + "bits": {}, + "grid_x": 37, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X13Y43", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y43": "SLICEM", + "SLICE_X19Y43": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y44": { + "bits": {}, + "grid_x": 37, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X13Y44", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y44": "SLICEM", + "SLICE_X19Y44": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y45": { + "bits": {}, + "grid_x": 37, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X13Y45", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y45": "SLICEM", + "SLICE_X19Y45": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y46": { + "bits": {}, + "grid_x": 37, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X13Y46", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y46": "SLICEM", + "SLICE_X19Y46": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y47": { + "bits": {}, + "grid_x": 37, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X13Y47", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y47": "SLICEM", + "SLICE_X19Y47": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y48": { + "bits": {}, + "grid_x": 37, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X13Y48", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y48": "SLICEM", + "SLICE_X19Y48": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y49": { + "bits": {}, + "grid_x": 37, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X13Y49", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y49": "SLICEM", + "SLICE_X19Y49": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y5": { + "bits": {}, + "grid_x": 37, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X13Y5", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y5": "SLICEM", + "SLICE_X19Y5": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X13Y50", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y50": "SLICEM", + "SLICE_X19Y50": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X13Y51", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y51": "SLICEM", + "SLICE_X19Y51": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X13Y52", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y52": "SLICEM", + "SLICE_X19Y52": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X13Y53", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y53": "SLICEM", + "SLICE_X19Y53": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X13Y54", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y54": "SLICEM", + "SLICE_X19Y54": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X13Y55", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y55": "SLICEM", + "SLICE_X19Y55": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X13Y56", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y56": "SLICEM", + "SLICE_X19Y56": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X13Y57", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y57": "SLICEM", + "SLICE_X19Y57": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X13Y58", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y58": "SLICEM", + "SLICE_X19Y58": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X13Y59", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y59": "SLICEM", + "SLICE_X19Y59": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y6": { + "bits": {}, + "grid_x": 37, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X13Y6", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y6": "SLICEM", + "SLICE_X19Y6": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X13Y60", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y60": "SLICEM", + "SLICE_X19Y60": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X13Y61", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y61": "SLICEM", + "SLICE_X19Y61": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X13Y62", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y62": "SLICEM", + "SLICE_X19Y62": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X13Y63", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y63": "SLICEM", + "SLICE_X19Y63": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X13Y64", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y64": "SLICEM", + "SLICE_X19Y64": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X13Y65", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y65": "SLICEM", + "SLICE_X19Y65": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X13Y66", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y66": "SLICEM", + "SLICE_X19Y66": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X13Y67", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y67": "SLICEM", + "SLICE_X19Y67": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X13Y68", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y68": "SLICEM", + "SLICE_X19Y68": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X13Y69", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y69": "SLICEM", + "SLICE_X19Y69": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y7": { + "bits": {}, + "grid_x": 37, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X13Y7", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y7": "SLICEM", + "SLICE_X19Y7": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X13Y70", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y70": "SLICEM", + "SLICE_X19Y70": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X13Y71", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y71": "SLICEM", + "SLICE_X19Y71": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X13Y72", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y72": "SLICEM", + "SLICE_X19Y72": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X13Y73", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y73": "SLICEM", + "SLICE_X19Y73": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X13Y74", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y74": "SLICEM", + "SLICE_X19Y74": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X13Y75", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y75": "SLICEM", + "SLICE_X19Y75": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X13Y76", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y76": "SLICEM", + "SLICE_X19Y76": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X13Y77", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y77": "SLICEM", + "SLICE_X19Y77": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X13Y78", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y78": "SLICEM", + "SLICE_X19Y78": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X13Y79", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y79": "SLICEM", + "SLICE_X19Y79": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y8": { + "bits": {}, + "grid_x": 37, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X13Y8", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y8": "SLICEM", + "SLICE_X19Y8": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X13Y80", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y80": "SLICEM", + "SLICE_X19Y80": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X13Y81", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y81": "SLICEM", + "SLICE_X19Y81": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X13Y82", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y82": "SLICEM", + "SLICE_X19Y82": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X13Y83", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y83": "SLICEM", + "SLICE_X19Y83": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X13Y84", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y84": "SLICEM", + "SLICE_X19Y84": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X13Y85", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y85": "SLICEM", + "SLICE_X19Y85": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X13Y86", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y86": "SLICEM", + "SLICE_X19Y86": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X13Y87", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y87": "SLICEM", + "SLICE_X19Y87": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X13Y88", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y88": "SLICEM", + "SLICE_X19Y88": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X13Y89", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y89": "SLICEM", + "SLICE_X19Y89": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y9": { + "bits": {}, + "grid_x": 37, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X13Y9", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y9": "SLICEM", + "SLICE_X19Y9": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X13Y90", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y90": "SLICEM", + "SLICE_X19Y90": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X13Y91", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y91": "SLICEM", + "SLICE_X19Y91": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X13Y92", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y92": "SLICEM", + "SLICE_X19Y92": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X13Y93", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y93": "SLICEM", + "SLICE_X19Y93": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X13Y94", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y94": "SLICEM", + "SLICE_X19Y94": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X13Y95", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y95": "SLICEM", + "SLICE_X19Y95": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X13Y96", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y96": "SLICEM", + "SLICE_X19Y96": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X13Y97", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y97": "SLICEM", + "SLICE_X19Y97": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X13Y98", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y98": "SLICEM", + "SLICE_X19Y98": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X13Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 36, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 37, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X13Y99", + "segment_type": "clblm_r", + "sites": { + "SLICE_X18Y99": "SLICEM", + "SLICE_X19Y99": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y0": { + "bits": {}, + "grid_x": 43, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X15Y0", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y0": "SLICEM", + "SLICE_X21Y0": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y1": { + "bits": {}, + "grid_x": 43, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X15Y1", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y1": "SLICEM", + "SLICE_X21Y1": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y10": { + "bits": {}, + "grid_x": 43, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X15Y10", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y10": "SLICEM", + "SLICE_X21Y10": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y100": { + "bits": {}, + "grid_x": 43, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X15Y100", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y100": "SLICEM", + "SLICE_X21Y100": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y101": { + "bits": {}, + "grid_x": 43, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X15Y101", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y101": "SLICEM", + "SLICE_X21Y101": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y102": { + "bits": {}, + "grid_x": 43, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X15Y102", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y102": "SLICEM", + "SLICE_X21Y102": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y103": { + "bits": {}, + "grid_x": 43, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X15Y103", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y103": "SLICEM", + "SLICE_X21Y103": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y104": { + "bits": {}, + "grid_x": 43, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X15Y104", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y104": "SLICEM", + "SLICE_X21Y104": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y105": { + "bits": {}, + "grid_x": 43, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X15Y105", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y105": "SLICEM", + "SLICE_X21Y105": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y106": { + "bits": {}, + "grid_x": 43, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X15Y106", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y106": "SLICEM", + "SLICE_X21Y106": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y107": { + "bits": {}, + "grid_x": 43, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X15Y107", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y107": "SLICEM", + "SLICE_X21Y107": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y108": { + "bits": {}, + "grid_x": 43, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X15Y108", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y108": "SLICEM", + "SLICE_X21Y108": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y109": { + "bits": {}, + "grid_x": 43, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X15Y109", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y109": "SLICEM", + "SLICE_X21Y109": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y11": { + "bits": {}, + "grid_x": 43, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X15Y11", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y11": "SLICEM", + "SLICE_X21Y11": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y110": { + "bits": {}, + "grid_x": 43, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X15Y110", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y110": "SLICEM", + "SLICE_X21Y110": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y111": { + "bits": {}, + "grid_x": 43, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X15Y111", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y111": "SLICEM", + "SLICE_X21Y111": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y112": { + "bits": {}, + "grid_x": 43, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X15Y112", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y112": "SLICEM", + "SLICE_X21Y112": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y113": { + "bits": {}, + "grid_x": 43, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X15Y113", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y113": "SLICEM", + "SLICE_X21Y113": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y114": { + "bits": {}, + "grid_x": 43, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X15Y114", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y114": "SLICEM", + "SLICE_X21Y114": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y115": { + "bits": {}, + "grid_x": 43, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X15Y115", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y115": "SLICEM", + "SLICE_X21Y115": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y116": { + "bits": {}, + "grid_x": 43, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X15Y116", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y116": "SLICEM", + "SLICE_X21Y116": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y117": { + "bits": {}, + "grid_x": 43, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X15Y117", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y117": "SLICEM", + "SLICE_X21Y117": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y118": { + "bits": {}, + "grid_x": 43, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X15Y118", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y118": "SLICEM", + "SLICE_X21Y118": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y119": { + "bits": {}, + "grid_x": 43, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X15Y119", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y119": "SLICEM", + "SLICE_X21Y119": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y12": { + "bits": {}, + "grid_x": 43, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X15Y12", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y12": "SLICEM", + "SLICE_X21Y12": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y120": { + "bits": {}, + "grid_x": 43, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X15Y120", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y120": "SLICEM", + "SLICE_X21Y120": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y121": { + "bits": {}, + "grid_x": 43, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X15Y121", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y121": "SLICEM", + "SLICE_X21Y121": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y122": { + "bits": {}, + "grid_x": 43, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X15Y122", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y122": "SLICEM", + "SLICE_X21Y122": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y123": { + "bits": {}, + "grid_x": 43, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X15Y123", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y123": "SLICEM", + "SLICE_X21Y123": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y124": { + "bits": {}, + "grid_x": 43, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X15Y124", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y124": "SLICEM", + "SLICE_X21Y124": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y125": { + "bits": {}, + "grid_x": 43, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X15Y125", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y125": "SLICEM", + "SLICE_X21Y125": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y126": { + "bits": {}, + "grid_x": 43, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X15Y126", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y126": "SLICEM", + "SLICE_X21Y126": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y127": { + "bits": {}, + "grid_x": 43, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X15Y127", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y127": "SLICEM", + "SLICE_X21Y127": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y128": { + "bits": {}, + "grid_x": 43, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X15Y128", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y128": "SLICEM", + "SLICE_X21Y128": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y129": { + "bits": {}, + "grid_x": 43, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X15Y129", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y129": "SLICEM", + "SLICE_X21Y129": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y13": { + "bits": {}, + "grid_x": 43, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X15Y13", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y13": "SLICEM", + "SLICE_X21Y13": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y130": { + "bits": {}, + "grid_x": 43, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X15Y130", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y130": "SLICEM", + "SLICE_X21Y130": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y131": { + "bits": {}, + "grid_x": 43, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X15Y131", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y131": "SLICEM", + "SLICE_X21Y131": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y132": { + "bits": {}, + "grid_x": 43, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X15Y132", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y132": "SLICEM", + "SLICE_X21Y132": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y133": { + "bits": {}, + "grid_x": 43, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X15Y133", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y133": "SLICEM", + "SLICE_X21Y133": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y134": { + "bits": {}, + "grid_x": 43, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X15Y134", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y134": "SLICEM", + "SLICE_X21Y134": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y135": { + "bits": {}, + "grid_x": 43, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X15Y135", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y135": "SLICEM", + "SLICE_X21Y135": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y136": { + "bits": {}, + "grid_x": 43, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X15Y136", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y136": "SLICEM", + "SLICE_X21Y136": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y137": { + "bits": {}, + "grid_x": 43, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X15Y137", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y137": "SLICEM", + "SLICE_X21Y137": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y138": { + "bits": {}, + "grid_x": 43, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X15Y138", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y138": "SLICEM", + "SLICE_X21Y138": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y139": { + "bits": {}, + "grid_x": 43, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X15Y139", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y139": "SLICEM", + "SLICE_X21Y139": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y14": { + "bits": {}, + "grid_x": 43, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X15Y14", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y14": "SLICEM", + "SLICE_X21Y14": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y140": { + "bits": {}, + "grid_x": 43, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X15Y140", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y140": "SLICEM", + "SLICE_X21Y140": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y141": { + "bits": {}, + "grid_x": 43, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X15Y141", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y141": "SLICEM", + "SLICE_X21Y141": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y142": { + "bits": {}, + "grid_x": 43, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X15Y142", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y142": "SLICEM", + "SLICE_X21Y142": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y143": { + "bits": {}, + "grid_x": 43, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X15Y143", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y143": "SLICEM", + "SLICE_X21Y143": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y144": { + "bits": {}, + "grid_x": 43, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X15Y144", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y144": "SLICEM", + "SLICE_X21Y144": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y145": { + "bits": {}, + "grid_x": 43, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X15Y145", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y145": "SLICEM", + "SLICE_X21Y145": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y146": { + "bits": {}, + "grid_x": 43, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X15Y146", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y146": "SLICEM", + "SLICE_X21Y146": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y147": { + "bits": {}, + "grid_x": 43, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X15Y147", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y147": "SLICEM", + "SLICE_X21Y147": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y148": { + "bits": {}, + "grid_x": 43, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X15Y148", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y148": "SLICEM", + "SLICE_X21Y148": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y149": { + "bits": {}, + "grid_x": 43, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X15Y149", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y149": "SLICEM", + "SLICE_X21Y149": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y15": { + "bits": {}, + "grid_x": 43, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X15Y15", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y15": "SLICEM", + "SLICE_X21Y15": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y150": { + "bits": {}, + "grid_x": 43, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X15Y150", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y150": "SLICEM", + "SLICE_X21Y150": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y151": { + "bits": {}, + "grid_x": 43, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X15Y151", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y151": "SLICEM", + "SLICE_X21Y151": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y152": { + "bits": {}, + "grid_x": 43, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X15Y152", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y152": "SLICEM", + "SLICE_X21Y152": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y153": { + "bits": {}, + "grid_x": 43, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X15Y153", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y153": "SLICEM", + "SLICE_X21Y153": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y154": { + "bits": {}, + "grid_x": 43, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X15Y154", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y154": "SLICEM", + "SLICE_X21Y154": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y155": { + "bits": {}, + "grid_x": 43, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X15Y155", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y155": "SLICEM", + "SLICE_X21Y155": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y156": { + "bits": {}, + "grid_x": 43, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X15Y156", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y156": "SLICEM", + "SLICE_X21Y156": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y157": { + "bits": {}, + "grid_x": 43, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X15Y157", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y157": "SLICEM", + "SLICE_X21Y157": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y158": { + "bits": {}, + "grid_x": 43, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X15Y158", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y158": "SLICEM", + "SLICE_X21Y158": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y159": { + "bits": {}, + "grid_x": 43, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X15Y159", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y159": "SLICEM", + "SLICE_X21Y159": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y16": { + "bits": {}, + "grid_x": 43, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X15Y16", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y16": "SLICEM", + "SLICE_X21Y16": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y160": { + "bits": {}, + "grid_x": 43, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X15Y160", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y160": "SLICEM", + "SLICE_X21Y160": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y161": { + "bits": {}, + "grid_x": 43, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X15Y161", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y161": "SLICEM", + "SLICE_X21Y161": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y162": { + "bits": {}, + "grid_x": 43, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X15Y162", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y162": "SLICEM", + "SLICE_X21Y162": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y163": { + "bits": {}, + "grid_x": 43, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X15Y163", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y163": "SLICEM", + "SLICE_X21Y163": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y164": { + "bits": {}, + "grid_x": 43, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X15Y164", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y164": "SLICEM", + "SLICE_X21Y164": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y165": { + "bits": {}, + "grid_x": 43, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X15Y165", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y165": "SLICEM", + "SLICE_X21Y165": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y166": { + "bits": {}, + "grid_x": 43, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X15Y166", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y166": "SLICEM", + "SLICE_X21Y166": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y167": { + "bits": {}, + "grid_x": 43, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X15Y167", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y167": "SLICEM", + "SLICE_X21Y167": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y168": { + "bits": {}, + "grid_x": 43, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X15Y168", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y168": "SLICEM", + "SLICE_X21Y168": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y169": { + "bits": {}, + "grid_x": 43, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X15Y169", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y169": "SLICEM", + "SLICE_X21Y169": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y17": { + "bits": {}, + "grid_x": 43, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X15Y17", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y17": "SLICEM", + "SLICE_X21Y17": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y170": { + "bits": {}, + "grid_x": 43, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X15Y170", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y170": "SLICEM", + "SLICE_X21Y170": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y171": { + "bits": {}, + "grid_x": 43, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X15Y171", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y171": "SLICEM", + "SLICE_X21Y171": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y172": { + "bits": {}, + "grid_x": 43, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X15Y172", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y172": "SLICEM", + "SLICE_X21Y172": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y173": { + "bits": {}, + "grid_x": 43, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X15Y173", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y173": "SLICEM", + "SLICE_X21Y173": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y174": { + "bits": {}, + "grid_x": 43, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X15Y174", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y174": "SLICEM", + "SLICE_X21Y174": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y175": { + "bits": {}, + "grid_x": 43, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X15Y175", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y175": "SLICEM", + "SLICE_X21Y175": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y176": { + "bits": {}, + "grid_x": 43, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X15Y176", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y176": "SLICEM", + "SLICE_X21Y176": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y177": { + "bits": {}, + "grid_x": 43, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X15Y177", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y177": "SLICEM", + "SLICE_X21Y177": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y178": { + "bits": {}, + "grid_x": 43, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X15Y178", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y178": "SLICEM", + "SLICE_X21Y178": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y179": { + "bits": {}, + "grid_x": 43, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X15Y179", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y179": "SLICEM", + "SLICE_X21Y179": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y18": { + "bits": {}, + "grid_x": 43, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X15Y18", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y18": "SLICEM", + "SLICE_X21Y18": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y180": { + "bits": {}, + "grid_x": 43, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X15Y180", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y180": "SLICEM", + "SLICE_X21Y180": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y181": { + "bits": {}, + "grid_x": 43, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X15Y181", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y181": "SLICEM", + "SLICE_X21Y181": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y182": { + "bits": {}, + "grid_x": 43, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X15Y182", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y182": "SLICEM", + "SLICE_X21Y182": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y183": { + "bits": {}, + "grid_x": 43, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X15Y183", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y183": "SLICEM", + "SLICE_X21Y183": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y184": { + "bits": {}, + "grid_x": 43, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X15Y184", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y184": "SLICEM", + "SLICE_X21Y184": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y185": { + "bits": {}, + "grid_x": 43, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X15Y185", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y185": "SLICEM", + "SLICE_X21Y185": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y186": { + "bits": {}, + "grid_x": 43, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X15Y186", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y186": "SLICEM", + "SLICE_X21Y186": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y187": { + "bits": {}, + "grid_x": 43, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X15Y187", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y187": "SLICEM", + "SLICE_X21Y187": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y188": { + "bits": {}, + "grid_x": 43, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X15Y188", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y188": "SLICEM", + "SLICE_X21Y188": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y189": { + "bits": {}, + "grid_x": 43, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X15Y189", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y189": "SLICEM", + "SLICE_X21Y189": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y19": { + "bits": {}, + "grid_x": 43, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X15Y19", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y19": "SLICEM", + "SLICE_X21Y19": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y190": { + "bits": {}, + "grid_x": 43, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X15Y190", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y190": "SLICEM", + "SLICE_X21Y190": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y191": { + "bits": {}, + "grid_x": 43, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X15Y191", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y191": "SLICEM", + "SLICE_X21Y191": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y192": { + "bits": {}, + "grid_x": 43, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X15Y192", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y192": "SLICEM", + "SLICE_X21Y192": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y193": { + "bits": {}, + "grid_x": 43, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X15Y193", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y193": "SLICEM", + "SLICE_X21Y193": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y194": { + "bits": {}, + "grid_x": 43, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X15Y194", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y194": "SLICEM", + "SLICE_X21Y194": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y195": { + "bits": {}, + "grid_x": 43, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X15Y195", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y195": "SLICEM", + "SLICE_X21Y195": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y196": { + "bits": {}, + "grid_x": 43, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X15Y196", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y196": "SLICEM", + "SLICE_X21Y196": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y197": { + "bits": {}, + "grid_x": 43, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X15Y197", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y197": "SLICEM", + "SLICE_X21Y197": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y198": { + "bits": {}, + "grid_x": 43, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X15Y198", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y198": "SLICEM", + "SLICE_X21Y198": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y199": { + "bits": {}, + "grid_x": 43, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X15Y199", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y199": "SLICEM", + "SLICE_X21Y199": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y2": { + "bits": {}, + "grid_x": 43, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X15Y2", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y2": "SLICEM", + "SLICE_X21Y2": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y20": { + "bits": {}, + "grid_x": 43, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X15Y20", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y20": "SLICEM", + "SLICE_X21Y20": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y21": { + "bits": {}, + "grid_x": 43, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X15Y21", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y21": "SLICEM", + "SLICE_X21Y21": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y22": { + "bits": {}, + "grid_x": 43, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X15Y22", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y22": "SLICEM", + "SLICE_X21Y22": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y23": { + "bits": {}, + "grid_x": 43, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X15Y23", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y23": "SLICEM", + "SLICE_X21Y23": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y24": { + "bits": {}, + "grid_x": 43, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X15Y24", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y24": "SLICEM", + "SLICE_X21Y24": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y25": { + "bits": {}, + "grid_x": 43, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X15Y25", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y25": "SLICEM", + "SLICE_X21Y25": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y26": { + "bits": {}, + "grid_x": 43, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X15Y26", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y26": "SLICEM", + "SLICE_X21Y26": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y27": { + "bits": {}, + "grid_x": 43, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X15Y27", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y27": "SLICEM", + "SLICE_X21Y27": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y28": { + "bits": {}, + "grid_x": 43, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X15Y28", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y28": "SLICEM", + "SLICE_X21Y28": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y29": { + "bits": {}, + "grid_x": 43, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X15Y29", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y29": "SLICEM", + "SLICE_X21Y29": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y3": { + "bits": {}, + "grid_x": 43, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X15Y3", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y3": "SLICEM", + "SLICE_X21Y3": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y30": { + "bits": {}, + "grid_x": 43, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X15Y30", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y30": "SLICEM", + "SLICE_X21Y30": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y31": { + "bits": {}, + "grid_x": 43, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X15Y31", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y31": "SLICEM", + "SLICE_X21Y31": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y32": { + "bits": {}, + "grid_x": 43, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X15Y32", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y32": "SLICEM", + "SLICE_X21Y32": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y33": { + "bits": {}, + "grid_x": 43, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X15Y33", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y33": "SLICEM", + "SLICE_X21Y33": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y34": { + "bits": {}, + "grid_x": 43, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X15Y34", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y34": "SLICEM", + "SLICE_X21Y34": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y35": { + "bits": {}, + "grid_x": 43, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X15Y35", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y35": "SLICEM", + "SLICE_X21Y35": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y36": { + "bits": {}, + "grid_x": 43, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X15Y36", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y36": "SLICEM", + "SLICE_X21Y36": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y37": { + "bits": {}, + "grid_x": 43, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X15Y37", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y37": "SLICEM", + "SLICE_X21Y37": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y38": { + "bits": {}, + "grid_x": 43, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X15Y38", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y38": "SLICEM", + "SLICE_X21Y38": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y39": { + "bits": {}, + "grid_x": 43, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X15Y39", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y39": "SLICEM", + "SLICE_X21Y39": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y4": { + "bits": {}, + "grid_x": 43, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X15Y4", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y4": "SLICEM", + "SLICE_X21Y4": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y40": { + "bits": {}, + "grid_x": 43, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X15Y40", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y40": "SLICEM", + "SLICE_X21Y40": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y41": { + "bits": {}, + "grid_x": 43, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X15Y41", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y41": "SLICEM", + "SLICE_X21Y41": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y42": { + "bits": {}, + "grid_x": 43, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X15Y42", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y42": "SLICEM", + "SLICE_X21Y42": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y43": { + "bits": {}, + "grid_x": 43, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X15Y43", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y43": "SLICEM", + "SLICE_X21Y43": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y44": { + "bits": {}, + "grid_x": 43, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X15Y44", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y44": "SLICEM", + "SLICE_X21Y44": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y45": { + "bits": {}, + "grid_x": 43, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X15Y45", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y45": "SLICEM", + "SLICE_X21Y45": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y46": { + "bits": {}, + "grid_x": 43, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X15Y46", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y46": "SLICEM", + "SLICE_X21Y46": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y47": { + "bits": {}, + "grid_x": 43, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X15Y47", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y47": "SLICEM", + "SLICE_X21Y47": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y48": { + "bits": {}, + "grid_x": 43, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X15Y48", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y48": "SLICEM", + "SLICE_X21Y48": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y49": { + "bits": {}, + "grid_x": 43, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X15Y49", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y49": "SLICEM", + "SLICE_X21Y49": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y5": { + "bits": {}, + "grid_x": 43, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X15Y5", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y5": "SLICEM", + "SLICE_X21Y5": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y50": { + "bits": {}, + "grid_x": 43, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X15Y50", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y50": "SLICEM", + "SLICE_X21Y50": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y51": { + "bits": {}, + "grid_x": 43, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X15Y51", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y51": "SLICEM", + "SLICE_X21Y51": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y52": { + "bits": {}, + "grid_x": 43, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X15Y52", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y52": "SLICEM", + "SLICE_X21Y52": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y53": { + "bits": {}, + "grid_x": 43, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X15Y53", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y53": "SLICEM", + "SLICE_X21Y53": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y54": { + "bits": {}, + "grid_x": 43, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X15Y54", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y54": "SLICEM", + "SLICE_X21Y54": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y55": { + "bits": {}, + "grid_x": 43, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X15Y55", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y55": "SLICEM", + "SLICE_X21Y55": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y56": { + "bits": {}, + "grid_x": 43, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X15Y56", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y56": "SLICEM", + "SLICE_X21Y56": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y57": { + "bits": {}, + "grid_x": 43, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X15Y57", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y57": "SLICEM", + "SLICE_X21Y57": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y58": { + "bits": {}, + "grid_x": 43, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X15Y58", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y58": "SLICEM", + "SLICE_X21Y58": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y59": { + "bits": {}, + "grid_x": 43, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X15Y59", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y59": "SLICEM", + "SLICE_X21Y59": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y6": { + "bits": {}, + "grid_x": 43, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X15Y6", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y6": "SLICEM", + "SLICE_X21Y6": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y60": { + "bits": {}, + "grid_x": 43, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X15Y60", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y60": "SLICEM", + "SLICE_X21Y60": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y61": { + "bits": {}, + "grid_x": 43, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X15Y61", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y61": "SLICEM", + "SLICE_X21Y61": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y62": { + "bits": {}, + "grid_x": 43, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X15Y62", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y62": "SLICEM", + "SLICE_X21Y62": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y63": { + "bits": {}, + "grid_x": 43, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X15Y63", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y63": "SLICEM", + "SLICE_X21Y63": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y64": { + "bits": {}, + "grid_x": 43, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X15Y64", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y64": "SLICEM", + "SLICE_X21Y64": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y65": { + "bits": {}, + "grid_x": 43, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X15Y65", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y65": "SLICEM", + "SLICE_X21Y65": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y66": { + "bits": {}, + "grid_x": 43, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X15Y66", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y66": "SLICEM", + "SLICE_X21Y66": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y67": { + "bits": {}, + "grid_x": 43, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X15Y67", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y67": "SLICEM", + "SLICE_X21Y67": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y68": { + "bits": {}, + "grid_x": 43, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X15Y68", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y68": "SLICEM", + "SLICE_X21Y68": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y69": { + "bits": {}, + "grid_x": 43, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X15Y69", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y69": "SLICEM", + "SLICE_X21Y69": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y7": { + "bits": {}, + "grid_x": 43, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X15Y7", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y7": "SLICEM", + "SLICE_X21Y7": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y70": { + "bits": {}, + "grid_x": 43, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X15Y70", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y70": "SLICEM", + "SLICE_X21Y70": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y71": { + "bits": {}, + "grid_x": 43, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X15Y71", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y71": "SLICEM", + "SLICE_X21Y71": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y72": { + "bits": {}, + "grid_x": 43, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X15Y72", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y72": "SLICEM", + "SLICE_X21Y72": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y73": { + "bits": {}, + "grid_x": 43, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X15Y73", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y73": "SLICEM", + "SLICE_X21Y73": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y74": { + "bits": {}, + "grid_x": 43, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X15Y74", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y74": "SLICEM", + "SLICE_X21Y74": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y75": { + "bits": {}, + "grid_x": 43, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X15Y75", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y75": "SLICEM", + "SLICE_X21Y75": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y76": { + "bits": {}, + "grid_x": 43, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X15Y76", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y76": "SLICEM", + "SLICE_X21Y76": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y77": { + "bits": {}, + "grid_x": 43, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X15Y77", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y77": "SLICEM", + "SLICE_X21Y77": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y78": { + "bits": {}, + "grid_x": 43, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X15Y78", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y78": "SLICEM", + "SLICE_X21Y78": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y79": { + "bits": {}, + "grid_x": 43, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X15Y79", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y79": "SLICEM", + "SLICE_X21Y79": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y8": { + "bits": {}, + "grid_x": 43, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X15Y8", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y8": "SLICEM", + "SLICE_X21Y8": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y80": { + "bits": {}, + "grid_x": 43, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X15Y80", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y80": "SLICEM", + "SLICE_X21Y80": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y81": { + "bits": {}, + "grid_x": 43, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X15Y81", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y81": "SLICEM", + "SLICE_X21Y81": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y82": { + "bits": {}, + "grid_x": 43, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X15Y82", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y82": "SLICEM", + "SLICE_X21Y82": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y83": { + "bits": {}, + "grid_x": 43, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X15Y83", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y83": "SLICEM", + "SLICE_X21Y83": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y84": { + "bits": {}, + "grid_x": 43, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X15Y84", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y84": "SLICEM", + "SLICE_X21Y84": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y85": { + "bits": {}, + "grid_x": 43, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X15Y85", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y85": "SLICEM", + "SLICE_X21Y85": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y86": { + "bits": {}, + "grid_x": 43, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X15Y86", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y86": "SLICEM", + "SLICE_X21Y86": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y87": { + "bits": {}, + "grid_x": 43, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X15Y87", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y87": "SLICEM", + "SLICE_X21Y87": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y88": { + "bits": {}, + "grid_x": 43, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X15Y88", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y88": "SLICEM", + "SLICE_X21Y88": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y89": { + "bits": {}, + "grid_x": 43, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X15Y89", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y89": "SLICEM", + "SLICE_X21Y89": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y9": { + "bits": {}, + "grid_x": 43, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X15Y9", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y9": "SLICEM", + "SLICE_X21Y9": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y90": { + "bits": {}, + "grid_x": 43, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X15Y90", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y90": "SLICEM", + "SLICE_X21Y90": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y91": { + "bits": {}, + "grid_x": 43, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X15Y91", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y91": "SLICEM", + "SLICE_X21Y91": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y92": { + "bits": {}, + "grid_x": 43, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X15Y92", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y92": "SLICEM", + "SLICE_X21Y92": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y93": { + "bits": {}, + "grid_x": 43, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X15Y93", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y93": "SLICEM", + "SLICE_X21Y93": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y94": { + "bits": {}, + "grid_x": 43, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X15Y94", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y94": "SLICEM", + "SLICE_X21Y94": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y95": { + "bits": {}, + "grid_x": 43, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X15Y95", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y95": "SLICEM", + "SLICE_X21Y95": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y96": { + "bits": {}, + "grid_x": 43, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X15Y96", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y96": "SLICEM", + "SLICE_X21Y96": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y97": { + "bits": {}, + "grid_x": 43, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X15Y97", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y97": "SLICEM", + "SLICE_X21Y97": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y98": { + "bits": {}, + "grid_x": 43, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X15Y98", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y98": "SLICEM", + "SLICE_X21Y98": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X15Y99": { + "bits": {}, + "grid_x": 43, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X15Y99", + "segment_type": "clblm_r", + "sites": { + "SLICE_X20Y99": "SLICEM", + "SLICE_X21Y99": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y0": { + "bits": {}, + "grid_x": 72, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X27Y0", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y0": "SLICEM", + "SLICE_X39Y0": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y1": { + "bits": {}, + "grid_x": 72, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X27Y1", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y1": "SLICEM", + "SLICE_X39Y1": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y10": { + "bits": {}, + "grid_x": 72, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X27Y10", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y10": "SLICEM", + "SLICE_X39Y10": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y11": { + "bits": {}, + "grid_x": 72, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X27Y11", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y11": "SLICEM", + "SLICE_X39Y11": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y12": { + "bits": {}, + "grid_x": 72, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X27Y12", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y12": "SLICEM", + "SLICE_X39Y12": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y125": { + "bits": {}, + "grid_x": 72, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X27Y125", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y125": "SLICEM", + "SLICE_X39Y125": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y126": { + "bits": {}, + "grid_x": 72, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X27Y126", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y126": "SLICEM", + "SLICE_X39Y126": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y127": { + "bits": {}, + "grid_x": 72, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X27Y127", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y127": "SLICEM", + "SLICE_X39Y127": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y128": { + "bits": {}, + "grid_x": 72, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X27Y128", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y128": "SLICEM", + "SLICE_X39Y128": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y129": { + "bits": {}, + "grid_x": 72, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X27Y129", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y129": "SLICEM", + "SLICE_X39Y129": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y13": { + "bits": {}, + "grid_x": 72, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X27Y13", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y13": "SLICEM", + "SLICE_X39Y13": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y130": { + "bits": {}, + "grid_x": 72, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X27Y130", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y130": "SLICEM", + "SLICE_X39Y130": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y131": { + "bits": {}, + "grid_x": 72, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X27Y131", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y131": "SLICEM", + "SLICE_X39Y131": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y132": { + "bits": {}, + "grid_x": 72, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X27Y132", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y132": "SLICEM", + "SLICE_X39Y132": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y133": { + "bits": {}, + "grid_x": 72, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X27Y133", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y133": "SLICEM", + "SLICE_X39Y133": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y134": { + "bits": {}, + "grid_x": 72, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X27Y134", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y134": "SLICEM", + "SLICE_X39Y134": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y135": { + "bits": {}, + "grid_x": 72, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X27Y135", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y135": "SLICEM", + "SLICE_X39Y135": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y136": { + "bits": {}, + "grid_x": 72, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X27Y136", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y136": "SLICEM", + "SLICE_X39Y136": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y137": { + "bits": {}, + "grid_x": 72, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X27Y137", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y137": "SLICEM", + "SLICE_X39Y137": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y138": { + "bits": {}, + "grid_x": 72, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X27Y138", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y138": "SLICEM", + "SLICE_X39Y138": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y139": { + "bits": {}, + "grid_x": 72, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X27Y139", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y139": "SLICEM", + "SLICE_X39Y139": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y14": { + "bits": {}, + "grid_x": 72, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X27Y14", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y14": "SLICEM", + "SLICE_X39Y14": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y140": { + "bits": {}, + "grid_x": 72, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X27Y140", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y140": "SLICEM", + "SLICE_X39Y140": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y141": { + "bits": {}, + "grid_x": 72, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X27Y141", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y141": "SLICEM", + "SLICE_X39Y141": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y142": { + "bits": {}, + "grid_x": 72, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X27Y142", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y142": "SLICEM", + "SLICE_X39Y142": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y143": { + "bits": {}, + "grid_x": 72, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X27Y143", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y143": "SLICEM", + "SLICE_X39Y143": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y144": { + "bits": {}, + "grid_x": 72, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X27Y144", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y144": "SLICEM", + "SLICE_X39Y144": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y145": { + "bits": {}, + "grid_x": 72, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X27Y145", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y145": "SLICEM", + "SLICE_X39Y145": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y146": { + "bits": {}, + "grid_x": 72, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X27Y146", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y146": "SLICEM", + "SLICE_X39Y146": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y147": { + "bits": {}, + "grid_x": 72, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X27Y147", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y147": "SLICEM", + "SLICE_X39Y147": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y148": { + "bits": {}, + "grid_x": 72, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X27Y148", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y148": "SLICEM", + "SLICE_X39Y148": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y149": { + "bits": {}, + "grid_x": 72, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X27Y149", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y149": "SLICEM", + "SLICE_X39Y149": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y15": { + "bits": {}, + "grid_x": 72, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X27Y15", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y15": "SLICEM", + "SLICE_X39Y15": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y150": { + "bits": {}, + "grid_x": 72, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X27Y150", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y150": "SLICEM", + "SLICE_X39Y150": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y151": { + "bits": {}, + "grid_x": 72, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X27Y151", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y151": "SLICEM", + "SLICE_X39Y151": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y152": { + "bits": {}, + "grid_x": 72, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X27Y152", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y152": "SLICEM", + "SLICE_X39Y152": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y153": { + "bits": {}, + "grid_x": 72, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X27Y153", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y153": "SLICEM", + "SLICE_X39Y153": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y154": { + "bits": {}, + "grid_x": 72, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X27Y154", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y154": "SLICEM", + "SLICE_X39Y154": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y155": { + "bits": {}, + "grid_x": 72, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X27Y155", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y155": "SLICEM", + "SLICE_X39Y155": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y156": { + "bits": {}, + "grid_x": 72, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X27Y156", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y156": "SLICEM", + "SLICE_X39Y156": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y157": { + "bits": {}, + "grid_x": 72, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X27Y157", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y157": "SLICEM", + "SLICE_X39Y157": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y158": { + "bits": {}, + "grid_x": 72, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X27Y158", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y158": "SLICEM", + "SLICE_X39Y158": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y159": { + "bits": {}, + "grid_x": 72, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X27Y159", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y159": "SLICEM", + "SLICE_X39Y159": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y16": { + "bits": {}, + "grid_x": 72, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X27Y16", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y16": "SLICEM", + "SLICE_X39Y16": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y160": { + "bits": {}, + "grid_x": 72, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X27Y160", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y160": "SLICEM", + "SLICE_X39Y160": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y161": { + "bits": {}, + "grid_x": 72, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X27Y161", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y161": "SLICEM", + "SLICE_X39Y161": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y162": { + "bits": {}, + "grid_x": 72, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X27Y162", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y162": "SLICEM", + "SLICE_X39Y162": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y163": { + "bits": {}, + "grid_x": 72, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X27Y163", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y163": "SLICEM", + "SLICE_X39Y163": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y164": { + "bits": {}, + "grid_x": 72, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X27Y164", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y164": "SLICEM", + "SLICE_X39Y164": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y165": { + "bits": {}, + "grid_x": 72, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X27Y165", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y165": "SLICEM", + "SLICE_X39Y165": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y166": { + "bits": {}, + "grid_x": 72, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X27Y166", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y166": "SLICEM", + "SLICE_X39Y166": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y167": { + "bits": {}, + "grid_x": 72, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X27Y167", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y167": "SLICEM", + "SLICE_X39Y167": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y168": { + "bits": {}, + "grid_x": 72, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X27Y168", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y168": "SLICEM", + "SLICE_X39Y168": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y169": { + "bits": {}, + "grid_x": 72, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X27Y169", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y169": "SLICEM", + "SLICE_X39Y169": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y17": { + "bits": {}, + "grid_x": 72, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X27Y17", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y17": "SLICEM", + "SLICE_X39Y17": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y170": { + "bits": {}, + "grid_x": 72, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X27Y170", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y170": "SLICEM", + "SLICE_X39Y170": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y171": { + "bits": {}, + "grid_x": 72, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X27Y171", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y171": "SLICEM", + "SLICE_X39Y171": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y172": { + "bits": {}, + "grid_x": 72, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X27Y172", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y172": "SLICEM", + "SLICE_X39Y172": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y173": { + "bits": {}, + "grid_x": 72, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X27Y173", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y173": "SLICEM", + "SLICE_X39Y173": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y174": { + "bits": {}, + "grid_x": 72, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X27Y174", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y174": "SLICEM", + "SLICE_X39Y174": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y175": { + "bits": {}, + "grid_x": 72, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X27Y175", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y175": "SLICEM", + "SLICE_X39Y175": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y176": { + "bits": {}, + "grid_x": 72, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X27Y176", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y176": "SLICEM", + "SLICE_X39Y176": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y177": { + "bits": {}, + "grid_x": 72, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X27Y177", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y177": "SLICEM", + "SLICE_X39Y177": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y178": { + "bits": {}, + "grid_x": 72, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X27Y178", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y178": "SLICEM", + "SLICE_X39Y178": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y179": { + "bits": {}, + "grid_x": 72, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X27Y179", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y179": "SLICEM", + "SLICE_X39Y179": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y18": { + "bits": {}, + "grid_x": 72, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X27Y18", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y18": "SLICEM", + "SLICE_X39Y18": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y180": { + "bits": {}, + "grid_x": 72, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X27Y180", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y180": "SLICEM", + "SLICE_X39Y180": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y181": { + "bits": {}, + "grid_x": 72, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X27Y181", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y181": "SLICEM", + "SLICE_X39Y181": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y182": { + "bits": {}, + "grid_x": 72, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X27Y182", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y182": "SLICEM", + "SLICE_X39Y182": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y183": { + "bits": {}, + "grid_x": 72, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X27Y183", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y183": "SLICEM", + "SLICE_X39Y183": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y184": { + "bits": {}, + "grid_x": 72, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X27Y184", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y184": "SLICEM", + "SLICE_X39Y184": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y185": { + "bits": {}, + "grid_x": 72, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X27Y185", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y185": "SLICEM", + "SLICE_X39Y185": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y186": { + "bits": {}, + "grid_x": 72, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X27Y186", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y186": "SLICEM", + "SLICE_X39Y186": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y187": { + "bits": {}, + "grid_x": 72, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X27Y187", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y187": "SLICEM", + "SLICE_X39Y187": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y188": { + "bits": {}, + "grid_x": 72, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X27Y188", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y188": "SLICEM", + "SLICE_X39Y188": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y189": { + "bits": {}, + "grid_x": 72, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X27Y189", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y189": "SLICEM", + "SLICE_X39Y189": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y19": { + "bits": {}, + "grid_x": 72, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X27Y19", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y19": "SLICEM", + "SLICE_X39Y19": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y190": { + "bits": {}, + "grid_x": 72, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X27Y190", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y190": "SLICEM", + "SLICE_X39Y190": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y191": { + "bits": {}, + "grid_x": 72, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X27Y191", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y191": "SLICEM", + "SLICE_X39Y191": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y192": { + "bits": {}, + "grid_x": 72, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X27Y192", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y192": "SLICEM", + "SLICE_X39Y192": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y193": { + "bits": {}, + "grid_x": 72, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X27Y193", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y193": "SLICEM", + "SLICE_X39Y193": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y194": { + "bits": {}, + "grid_x": 72, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X27Y194", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y194": "SLICEM", + "SLICE_X39Y194": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y195": { + "bits": {}, + "grid_x": 72, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X27Y195", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y195": "SLICEM", + "SLICE_X39Y195": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y196": { + "bits": {}, + "grid_x": 72, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X27Y196", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y196": "SLICEM", + "SLICE_X39Y196": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y197": { + "bits": {}, + "grid_x": 72, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X27Y197", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y197": "SLICEM", + "SLICE_X39Y197": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y198": { + "bits": {}, + "grid_x": 72, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X27Y198", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y198": "SLICEM", + "SLICE_X39Y198": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y199": { + "bits": {}, + "grid_x": 72, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X27Y199", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y199": "SLICEM", + "SLICE_X39Y199": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y2": { + "bits": {}, + "grid_x": 72, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X27Y2", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y2": "SLICEM", + "SLICE_X39Y2": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y20": { + "bits": {}, + "grid_x": 72, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X27Y20", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y20": "SLICEM", + "SLICE_X39Y20": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y21": { + "bits": {}, + "grid_x": 72, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X27Y21", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y21": "SLICEM", + "SLICE_X39Y21": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y22": { + "bits": {}, + "grid_x": 72, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X27Y22", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y22": "SLICEM", + "SLICE_X39Y22": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y23": { + "bits": {}, + "grid_x": 72, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X27Y23", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y23": "SLICEM", + "SLICE_X39Y23": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y24": { + "bits": {}, + "grid_x": 72, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X27Y24", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y24": "SLICEM", + "SLICE_X39Y24": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y25": { + "bits": {}, + "grid_x": 72, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X27Y25", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y25": "SLICEM", + "SLICE_X39Y25": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y26": { + "bits": {}, + "grid_x": 72, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X27Y26", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y26": "SLICEM", + "SLICE_X39Y26": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y27": { + "bits": {}, + "grid_x": 72, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X27Y27", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y27": "SLICEM", + "SLICE_X39Y27": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y28": { + "bits": {}, + "grid_x": 72, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X27Y28", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y28": "SLICEM", + "SLICE_X39Y28": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y29": { + "bits": {}, + "grid_x": 72, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X27Y29", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y29": "SLICEM", + "SLICE_X39Y29": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y3": { + "bits": {}, + "grid_x": 72, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X27Y3", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y3": "SLICEM", + "SLICE_X39Y3": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y30": { + "bits": {}, + "grid_x": 72, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X27Y30", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y30": "SLICEM", + "SLICE_X39Y30": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y31": { + "bits": {}, + "grid_x": 72, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X27Y31", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y31": "SLICEM", + "SLICE_X39Y31": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y32": { + "bits": {}, + "grid_x": 72, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X27Y32", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y32": "SLICEM", + "SLICE_X39Y32": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y33": { + "bits": {}, + "grid_x": 72, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X27Y33", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y33": "SLICEM", + "SLICE_X39Y33": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y34": { + "bits": {}, + "grid_x": 72, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X27Y34", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y34": "SLICEM", + "SLICE_X39Y34": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y35": { + "bits": {}, + "grid_x": 72, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X27Y35", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y35": "SLICEM", + "SLICE_X39Y35": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y36": { + "bits": {}, + "grid_x": 72, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X27Y36", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y36": "SLICEM", + "SLICE_X39Y36": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y37": { + "bits": {}, + "grid_x": 72, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X27Y37", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y37": "SLICEM", + "SLICE_X39Y37": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y38": { + "bits": {}, + "grid_x": 72, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X27Y38", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y38": "SLICEM", + "SLICE_X39Y38": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y39": { + "bits": {}, + "grid_x": 72, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X27Y39", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y39": "SLICEM", + "SLICE_X39Y39": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y4": { + "bits": {}, + "grid_x": 72, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X27Y4", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y4": "SLICEM", + "SLICE_X39Y4": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y40": { + "bits": {}, + "grid_x": 72, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X27Y40", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y40": "SLICEM", + "SLICE_X39Y40": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y41": { + "bits": {}, + "grid_x": 72, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X27Y41", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y41": "SLICEM", + "SLICE_X39Y41": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y42": { + "bits": {}, + "grid_x": 72, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X27Y42", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y42": "SLICEM", + "SLICE_X39Y42": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y43": { + "bits": {}, + "grid_x": 72, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X27Y43", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y43": "SLICEM", + "SLICE_X39Y43": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y44": { + "bits": {}, + "grid_x": 72, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X27Y44", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y44": "SLICEM", + "SLICE_X39Y44": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y45": { + "bits": {}, + "grid_x": 72, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X27Y45", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y45": "SLICEM", + "SLICE_X39Y45": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y46": { + "bits": {}, + "grid_x": 72, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X27Y46", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y46": "SLICEM", + "SLICE_X39Y46": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y47": { + "bits": {}, + "grid_x": 72, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X27Y47", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y47": "SLICEM", + "SLICE_X39Y47": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y48": { + "bits": {}, + "grid_x": 72, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X27Y48", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y48": "SLICEM", + "SLICE_X39Y48": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y49": { + "bits": {}, + "grid_x": 72, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X27Y49", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y49": "SLICEM", + "SLICE_X39Y49": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y5": { + "bits": {}, + "grid_x": 72, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X27Y5", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y5": "SLICEM", + "SLICE_X39Y5": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y50": { + "bits": {}, + "grid_x": 72, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X27Y50", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y50": "SLICEM", + "SLICE_X39Y50": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y51": { + "bits": {}, + "grid_x": 72, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X27Y51", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y51": "SLICEM", + "SLICE_X39Y51": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y52": { + "bits": {}, + "grid_x": 72, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X27Y52", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y52": "SLICEM", + "SLICE_X39Y52": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y53": { + "bits": {}, + "grid_x": 72, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X27Y53", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y53": "SLICEM", + "SLICE_X39Y53": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y54": { + "bits": {}, + "grid_x": 72, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X27Y54", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y54": "SLICEM", + "SLICE_X39Y54": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y55": { + "bits": {}, + "grid_x": 72, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X27Y55", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y55": "SLICEM", + "SLICE_X39Y55": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y56": { + "bits": {}, + "grid_x": 72, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X27Y56", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y56": "SLICEM", + "SLICE_X39Y56": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y57": { + "bits": {}, + "grid_x": 72, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X27Y57", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y57": "SLICEM", + "SLICE_X39Y57": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y58": { + "bits": {}, + "grid_x": 72, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X27Y58", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y58": "SLICEM", + "SLICE_X39Y58": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y59": { + "bits": {}, + "grid_x": 72, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X27Y59", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y59": "SLICEM", + "SLICE_X39Y59": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y6": { + "bits": {}, + "grid_x": 72, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X27Y6", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y6": "SLICEM", + "SLICE_X39Y6": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y60": { + "bits": {}, + "grid_x": 72, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X27Y60", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y60": "SLICEM", + "SLICE_X39Y60": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y61": { + "bits": {}, + "grid_x": 72, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X27Y61", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y61": "SLICEM", + "SLICE_X39Y61": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y62": { + "bits": {}, + "grid_x": 72, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X27Y62", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y62": "SLICEM", + "SLICE_X39Y62": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y63": { + "bits": {}, + "grid_x": 72, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X27Y63", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y63": "SLICEM", + "SLICE_X39Y63": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y64": { + "bits": {}, + "grid_x": 72, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X27Y64", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y64": "SLICEM", + "SLICE_X39Y64": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y65": { + "bits": {}, + "grid_x": 72, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X27Y65", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y65": "SLICEM", + "SLICE_X39Y65": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y66": { + "bits": {}, + "grid_x": 72, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X27Y66", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y66": "SLICEM", + "SLICE_X39Y66": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y67": { + "bits": {}, + "grid_x": 72, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X27Y67", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y67": "SLICEM", + "SLICE_X39Y67": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y68": { + "bits": {}, + "grid_x": 72, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X27Y68", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y68": "SLICEM", + "SLICE_X39Y68": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y69": { + "bits": {}, + "grid_x": 72, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X27Y69", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y69": "SLICEM", + "SLICE_X39Y69": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y7": { + "bits": {}, + "grid_x": 72, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X27Y7", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y7": "SLICEM", + "SLICE_X39Y7": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y70": { + "bits": {}, + "grid_x": 72, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X27Y70", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y70": "SLICEM", + "SLICE_X39Y70": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y71": { + "bits": {}, + "grid_x": 72, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X27Y71", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y71": "SLICEM", + "SLICE_X39Y71": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y72": { + "bits": {}, + "grid_x": 72, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X27Y72", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y72": "SLICEM", + "SLICE_X39Y72": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y73": { + "bits": {}, + "grid_x": 72, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X27Y73", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y73": "SLICEM", + "SLICE_X39Y73": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y74": { + "bits": {}, + "grid_x": 72, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X27Y74", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y74": "SLICEM", + "SLICE_X39Y74": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y75": { + "bits": {}, + "grid_x": 72, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X27Y75", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y75": "SLICEM", + "SLICE_X39Y75": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y76": { + "bits": {}, + "grid_x": 72, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X27Y76", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y76": "SLICEM", + "SLICE_X39Y76": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y77": { + "bits": {}, + "grid_x": 72, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X27Y77", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y77": "SLICEM", + "SLICE_X39Y77": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y78": { + "bits": {}, + "grid_x": 72, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X27Y78", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y78": "SLICEM", + "SLICE_X39Y78": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y79": { + "bits": {}, + "grid_x": 72, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X27Y79", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y79": "SLICEM", + "SLICE_X39Y79": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y8": { + "bits": {}, + "grid_x": 72, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X27Y8", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y8": "SLICEM", + "SLICE_X39Y8": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y80": { + "bits": {}, + "grid_x": 72, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X27Y80", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y80": "SLICEM", + "SLICE_X39Y80": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y81": { + "bits": {}, + "grid_x": 72, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X27Y81", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y81": "SLICEM", + "SLICE_X39Y81": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y82": { + "bits": {}, + "grid_x": 72, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X27Y82", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y82": "SLICEM", + "SLICE_X39Y82": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y83": { + "bits": {}, + "grid_x": 72, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X27Y83", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y83": "SLICEM", + "SLICE_X39Y83": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y84": { + "bits": {}, + "grid_x": 72, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X27Y84", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y84": "SLICEM", + "SLICE_X39Y84": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y85": { + "bits": {}, + "grid_x": 72, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X27Y85", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y85": "SLICEM", + "SLICE_X39Y85": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y86": { + "bits": {}, + "grid_x": 72, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X27Y86", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y86": "SLICEM", + "SLICE_X39Y86": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y87": { + "bits": {}, + "grid_x": 72, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X27Y87", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y87": "SLICEM", + "SLICE_X39Y87": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y88": { + "bits": {}, + "grid_x": 72, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X27Y88", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y88": "SLICEM", + "SLICE_X39Y88": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y89": { + "bits": {}, + "grid_x": 72, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X27Y89", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y89": "SLICEM", + "SLICE_X39Y89": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y9": { + "bits": {}, + "grid_x": 72, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X27Y9", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y9": "SLICEM", + "SLICE_X39Y9": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y90": { + "bits": {}, + "grid_x": 72, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X27Y90", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y90": "SLICEM", + "SLICE_X39Y90": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y91": { + "bits": {}, + "grid_x": 72, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X27Y91", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y91": "SLICEM", + "SLICE_X39Y91": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y92": { + "bits": {}, + "grid_x": 72, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X27Y92", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y92": "SLICEM", + "SLICE_X39Y92": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y93": { + "bits": {}, + "grid_x": 72, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X27Y93", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y93": "SLICEM", + "SLICE_X39Y93": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y94": { + "bits": {}, + "grid_x": 72, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X27Y94", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y94": "SLICEM", + "SLICE_X39Y94": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y95": { + "bits": {}, + "grid_x": 72, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X27Y95", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y95": "SLICEM", + "SLICE_X39Y95": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y96": { + "bits": {}, + "grid_x": 72, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X27Y96", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y96": "SLICEM", + "SLICE_X39Y96": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y97": { + "bits": {}, + "grid_x": 72, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X27Y97", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y97": "SLICEM", + "SLICE_X39Y97": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y98": { + "bits": {}, + "grid_x": 72, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X27Y98", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y98": "SLICEM", + "SLICE_X39Y98": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X27Y99": { + "bits": {}, + "grid_x": 72, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X27Y99", + "segment_type": "clblm_r", + "sites": { + "SLICE_X38Y99": "SLICEM", + "SLICE_X39Y99": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y0": { + "bits": {}, + "grid_x": 76, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X29Y0", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y0": "SLICEM", + "SLICE_X43Y0": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y1": { + "bits": {}, + "grid_x": 76, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X29Y1", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y1": "SLICEM", + "SLICE_X43Y1": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y10": { + "bits": {}, + "grid_x": 76, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X29Y10", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y10": "SLICEM", + "SLICE_X43Y10": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y11": { + "bits": {}, + "grid_x": 76, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X29Y11", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y11": "SLICEM", + "SLICE_X43Y11": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y12": { + "bits": {}, + "grid_x": 76, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X29Y12", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y12": "SLICEM", + "SLICE_X43Y12": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y125": { + "bits": {}, + "grid_x": 76, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X29Y125", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y125": "SLICEM", + "SLICE_X43Y125": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y126": { + "bits": {}, + "grid_x": 76, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X29Y126", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y126": "SLICEM", + "SLICE_X43Y126": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y127": { + "bits": {}, + "grid_x": 76, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X29Y127", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y127": "SLICEM", + "SLICE_X43Y127": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y128": { + "bits": {}, + "grid_x": 76, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X29Y128", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y128": "SLICEM", + "SLICE_X43Y128": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y129": { + "bits": {}, + "grid_x": 76, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X29Y129", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y129": "SLICEM", + "SLICE_X43Y129": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y13": { + "bits": {}, + "grid_x": 76, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X29Y13", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y13": "SLICEM", + "SLICE_X43Y13": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y130": { + "bits": {}, + "grid_x": 76, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X29Y130", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y130": "SLICEM", + "SLICE_X43Y130": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y131": { + "bits": {}, + "grid_x": 76, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X29Y131", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y131": "SLICEM", + "SLICE_X43Y131": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y132": { + "bits": {}, + "grid_x": 76, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X29Y132", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y132": "SLICEM", + "SLICE_X43Y132": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y133": { + "bits": {}, + "grid_x": 76, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X29Y133", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y133": "SLICEM", + "SLICE_X43Y133": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y134": { + "bits": {}, + "grid_x": 76, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X29Y134", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y134": "SLICEM", + "SLICE_X43Y134": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y135": { + "bits": {}, + "grid_x": 76, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X29Y135", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y135": "SLICEM", + "SLICE_X43Y135": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y136": { + "bits": {}, + "grid_x": 76, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X29Y136", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y136": "SLICEM", + "SLICE_X43Y136": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y137": { + "bits": {}, + "grid_x": 76, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X29Y137", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y137": "SLICEM", + "SLICE_X43Y137": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y138": { + "bits": {}, + "grid_x": 76, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X29Y138", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y138": "SLICEM", + "SLICE_X43Y138": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y139": { + "bits": {}, + "grid_x": 76, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X29Y139", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y139": "SLICEM", + "SLICE_X43Y139": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y14": { + "bits": {}, + "grid_x": 76, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X29Y14", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y14": "SLICEM", + "SLICE_X43Y14": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y140": { + "bits": {}, + "grid_x": 76, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X29Y140", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y140": "SLICEM", + "SLICE_X43Y140": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y141": { + "bits": {}, + "grid_x": 76, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X29Y141", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y141": "SLICEM", + "SLICE_X43Y141": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y142": { + "bits": {}, + "grid_x": 76, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X29Y142", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y142": "SLICEM", + "SLICE_X43Y142": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y143": { + "bits": {}, + "grid_x": 76, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X29Y143", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y143": "SLICEM", + "SLICE_X43Y143": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y144": { + "bits": {}, + "grid_x": 76, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X29Y144", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y144": "SLICEM", + "SLICE_X43Y144": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y145": { + "bits": {}, + "grid_x": 76, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X29Y145", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y145": "SLICEM", + "SLICE_X43Y145": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y146": { + "bits": {}, + "grid_x": 76, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X29Y146", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y146": "SLICEM", + "SLICE_X43Y146": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y147": { + "bits": {}, + "grid_x": 76, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X29Y147", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y147": "SLICEM", + "SLICE_X43Y147": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y148": { + "bits": {}, + "grid_x": 76, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X29Y148", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y148": "SLICEM", + "SLICE_X43Y148": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y149": { + "bits": {}, + "grid_x": 76, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X29Y149", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y149": "SLICEM", + "SLICE_X43Y149": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y15": { + "bits": {}, + "grid_x": 76, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X29Y15", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y15": "SLICEM", + "SLICE_X43Y15": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y150": { + "bits": {}, + "grid_x": 76, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X29Y150", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y150": "SLICEM", + "SLICE_X43Y150": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y151": { + "bits": {}, + "grid_x": 76, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X29Y151", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y151": "SLICEM", + "SLICE_X43Y151": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y152": { + "bits": {}, + "grid_x": 76, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X29Y152", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y152": "SLICEM", + "SLICE_X43Y152": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y153": { + "bits": {}, + "grid_x": 76, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X29Y153", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y153": "SLICEM", + "SLICE_X43Y153": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y154": { + "bits": {}, + "grid_x": 76, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X29Y154", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y154": "SLICEM", + "SLICE_X43Y154": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y155": { + "bits": {}, + "grid_x": 76, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X29Y155", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y155": "SLICEM", + "SLICE_X43Y155": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y156": { + "bits": {}, + "grid_x": 76, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X29Y156", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y156": "SLICEM", + "SLICE_X43Y156": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y157": { + "bits": {}, + "grid_x": 76, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X29Y157", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y157": "SLICEM", + "SLICE_X43Y157": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y158": { + "bits": {}, + "grid_x": 76, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X29Y158", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y158": "SLICEM", + "SLICE_X43Y158": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y159": { + "bits": {}, + "grid_x": 76, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X29Y159", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y159": "SLICEM", + "SLICE_X43Y159": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y16": { + "bits": {}, + "grid_x": 76, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X29Y16", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y16": "SLICEM", + "SLICE_X43Y16": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y160": { + "bits": {}, + "grid_x": 76, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X29Y160", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y160": "SLICEM", + "SLICE_X43Y160": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y161": { + "bits": {}, + "grid_x": 76, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X29Y161", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y161": "SLICEM", + "SLICE_X43Y161": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y162": { + "bits": {}, + "grid_x": 76, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X29Y162", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y162": "SLICEM", + "SLICE_X43Y162": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y163": { + "bits": {}, + "grid_x": 76, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X29Y163", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y163": "SLICEM", + "SLICE_X43Y163": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y164": { + "bits": {}, + "grid_x": 76, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X29Y164", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y164": "SLICEM", + "SLICE_X43Y164": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y165": { + "bits": {}, + "grid_x": 76, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X29Y165", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y165": "SLICEM", + "SLICE_X43Y165": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y166": { + "bits": {}, + "grid_x": 76, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X29Y166", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y166": "SLICEM", + "SLICE_X43Y166": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y167": { + "bits": {}, + "grid_x": 76, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X29Y167", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y167": "SLICEM", + "SLICE_X43Y167": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y168": { + "bits": {}, + "grid_x": 76, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X29Y168", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y168": "SLICEM", + "SLICE_X43Y168": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y169": { + "bits": {}, + "grid_x": 76, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X29Y169", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y169": "SLICEM", + "SLICE_X43Y169": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y17": { + "bits": {}, + "grid_x": 76, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X29Y17", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y17": "SLICEM", + "SLICE_X43Y17": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y170": { + "bits": {}, + "grid_x": 76, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X29Y170", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y170": "SLICEM", + "SLICE_X43Y170": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y171": { + "bits": {}, + "grid_x": 76, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X29Y171", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y171": "SLICEM", + "SLICE_X43Y171": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y172": { + "bits": {}, + "grid_x": 76, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X29Y172", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y172": "SLICEM", + "SLICE_X43Y172": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y173": { + "bits": {}, + "grid_x": 76, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X29Y173", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y173": "SLICEM", + "SLICE_X43Y173": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y174": { + "bits": {}, + "grid_x": 76, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X29Y174", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y174": "SLICEM", + "SLICE_X43Y174": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y175": { + "bits": {}, + "grid_x": 76, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X29Y175", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y175": "SLICEM", + "SLICE_X43Y175": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y176": { + "bits": {}, + "grid_x": 76, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X29Y176", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y176": "SLICEM", + "SLICE_X43Y176": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y177": { + "bits": {}, + "grid_x": 76, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X29Y177", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y177": "SLICEM", + "SLICE_X43Y177": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y178": { + "bits": {}, + "grid_x": 76, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X29Y178", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y178": "SLICEM", + "SLICE_X43Y178": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y179": { + "bits": {}, + "grid_x": 76, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X29Y179", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y179": "SLICEM", + "SLICE_X43Y179": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y18": { + "bits": {}, + "grid_x": 76, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X29Y18", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y18": "SLICEM", + "SLICE_X43Y18": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y180": { + "bits": {}, + "grid_x": 76, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X29Y180", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y180": "SLICEM", + "SLICE_X43Y180": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y181": { + "bits": {}, + "grid_x": 76, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X29Y181", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y181": "SLICEM", + "SLICE_X43Y181": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y182": { + "bits": {}, + "grid_x": 76, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X29Y182", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y182": "SLICEM", + "SLICE_X43Y182": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y183": { + "bits": {}, + "grid_x": 76, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X29Y183", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y183": "SLICEM", + "SLICE_X43Y183": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y184": { + "bits": {}, + "grid_x": 76, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X29Y184", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y184": "SLICEM", + "SLICE_X43Y184": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y185": { + "bits": {}, + "grid_x": 76, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X29Y185", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y185": "SLICEM", + "SLICE_X43Y185": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y186": { + "bits": {}, + "grid_x": 76, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X29Y186", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y186": "SLICEM", + "SLICE_X43Y186": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y187": { + "bits": {}, + "grid_x": 76, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X29Y187", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y187": "SLICEM", + "SLICE_X43Y187": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y188": { + "bits": {}, + "grid_x": 76, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X29Y188", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y188": "SLICEM", + "SLICE_X43Y188": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y189": { + "bits": {}, + "grid_x": 76, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X29Y189", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y189": "SLICEM", + "SLICE_X43Y189": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y19": { + "bits": {}, + "grid_x": 76, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X29Y19", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y19": "SLICEM", + "SLICE_X43Y19": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y190": { + "bits": {}, + "grid_x": 76, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X29Y190", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y190": "SLICEM", + "SLICE_X43Y190": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y191": { + "bits": {}, + "grid_x": 76, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X29Y191", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y191": "SLICEM", + "SLICE_X43Y191": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y192": { + "bits": {}, + "grid_x": 76, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X29Y192", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y192": "SLICEM", + "SLICE_X43Y192": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y193": { + "bits": {}, + "grid_x": 76, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X29Y193", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y193": "SLICEM", + "SLICE_X43Y193": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y194": { + "bits": {}, + "grid_x": 76, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X29Y194", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y194": "SLICEM", + "SLICE_X43Y194": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y195": { + "bits": {}, + "grid_x": 76, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X29Y195", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y195": "SLICEM", + "SLICE_X43Y195": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y196": { + "bits": {}, + "grid_x": 76, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X29Y196", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y196": "SLICEM", + "SLICE_X43Y196": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y197": { + "bits": {}, + "grid_x": 76, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X29Y197", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y197": "SLICEM", + "SLICE_X43Y197": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y198": { + "bits": {}, + "grid_x": 76, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X29Y198", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y198": "SLICEM", + "SLICE_X43Y198": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y199": { + "bits": {}, + "grid_x": 76, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X29Y199", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y199": "SLICEM", + "SLICE_X43Y199": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y2": { + "bits": {}, + "grid_x": 76, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X29Y2", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y2": "SLICEM", + "SLICE_X43Y2": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y20": { + "bits": {}, + "grid_x": 76, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X29Y20", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y20": "SLICEM", + "SLICE_X43Y20": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y21": { + "bits": {}, + "grid_x": 76, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X29Y21", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y21": "SLICEM", + "SLICE_X43Y21": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y22": { + "bits": {}, + "grid_x": 76, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X29Y22", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y22": "SLICEM", + "SLICE_X43Y22": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y23": { + "bits": {}, + "grid_x": 76, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X29Y23", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y23": "SLICEM", + "SLICE_X43Y23": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y24": { + "bits": {}, + "grid_x": 76, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X29Y24", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y24": "SLICEM", + "SLICE_X43Y24": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y25": { + "bits": {}, + "grid_x": 76, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X29Y25", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y25": "SLICEM", + "SLICE_X43Y25": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y26": { + "bits": {}, + "grid_x": 76, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X29Y26", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y26": "SLICEM", + "SLICE_X43Y26": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y27": { + "bits": {}, + "grid_x": 76, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X29Y27", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y27": "SLICEM", + "SLICE_X43Y27": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y28": { + "bits": {}, + "grid_x": 76, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X29Y28", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y28": "SLICEM", + "SLICE_X43Y28": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y29": { + "bits": {}, + "grid_x": 76, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X29Y29", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y29": "SLICEM", + "SLICE_X43Y29": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y3": { + "bits": {}, + "grid_x": 76, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X29Y3", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y3": "SLICEM", + "SLICE_X43Y3": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y30": { + "bits": {}, + "grid_x": 76, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X29Y30", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y30": "SLICEM", + "SLICE_X43Y30": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y31": { + "bits": {}, + "grid_x": 76, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X29Y31", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y31": "SLICEM", + "SLICE_X43Y31": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y32": { + "bits": {}, + "grid_x": 76, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X29Y32", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y32": "SLICEM", + "SLICE_X43Y32": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y33": { + "bits": {}, + "grid_x": 76, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X29Y33", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y33": "SLICEM", + "SLICE_X43Y33": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y34": { + "bits": {}, + "grid_x": 76, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X29Y34", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y34": "SLICEM", + "SLICE_X43Y34": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y35": { + "bits": {}, + "grid_x": 76, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X29Y35", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y35": "SLICEM", + "SLICE_X43Y35": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y36": { + "bits": {}, + "grid_x": 76, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X29Y36", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y36": "SLICEM", + "SLICE_X43Y36": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y37": { + "bits": {}, + "grid_x": 76, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X29Y37", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y37": "SLICEM", + "SLICE_X43Y37": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y38": { + "bits": {}, + "grid_x": 76, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X29Y38", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y38": "SLICEM", + "SLICE_X43Y38": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y39": { + "bits": {}, + "grid_x": 76, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X29Y39", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y39": "SLICEM", + "SLICE_X43Y39": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y4": { + "bits": {}, + "grid_x": 76, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X29Y4", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y4": "SLICEM", + "SLICE_X43Y4": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y40": { + "bits": {}, + "grid_x": 76, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X29Y40", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y40": "SLICEM", + "SLICE_X43Y40": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y41": { + "bits": {}, + "grid_x": 76, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X29Y41", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y41": "SLICEM", + "SLICE_X43Y41": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y42": { + "bits": {}, + "grid_x": 76, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X29Y42", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y42": "SLICEM", + "SLICE_X43Y42": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y43": { + "bits": {}, + "grid_x": 76, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X29Y43", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y43": "SLICEM", + "SLICE_X43Y43": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y44": { + "bits": {}, + "grid_x": 76, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X29Y44", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y44": "SLICEM", + "SLICE_X43Y44": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y45": { + "bits": {}, + "grid_x": 76, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X29Y45", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y45": "SLICEM", + "SLICE_X43Y45": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y46": { + "bits": {}, + "grid_x": 76, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X29Y46", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y46": "SLICEM", + "SLICE_X43Y46": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y47": { + "bits": {}, + "grid_x": 76, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X29Y47", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y47": "SLICEM", + "SLICE_X43Y47": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y48": { + "bits": {}, + "grid_x": 76, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X29Y48", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y48": "SLICEM", + "SLICE_X43Y48": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y49": { + "bits": {}, + "grid_x": 76, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X29Y49", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y49": "SLICEM", + "SLICE_X43Y49": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y5": { + "bits": {}, + "grid_x": 76, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X29Y5", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y5": "SLICEM", + "SLICE_X43Y5": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y50": { + "bits": {}, + "grid_x": 76, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X29Y50", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y50": "SLICEM", + "SLICE_X43Y50": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y51": { + "bits": {}, + "grid_x": 76, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X29Y51", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y51": "SLICEM", + "SLICE_X43Y51": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y52": { + "bits": {}, + "grid_x": 76, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X29Y52", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y52": "SLICEM", + "SLICE_X43Y52": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y53": { + "bits": {}, + "grid_x": 76, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X29Y53", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y53": "SLICEM", + "SLICE_X43Y53": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y54": { + "bits": {}, + "grid_x": 76, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X29Y54", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y54": "SLICEM", + "SLICE_X43Y54": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y55": { + "bits": {}, + "grid_x": 76, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X29Y55", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y55": "SLICEM", + "SLICE_X43Y55": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y56": { + "bits": {}, + "grid_x": 76, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X29Y56", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y56": "SLICEM", + "SLICE_X43Y56": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y57": { + "bits": {}, + "grid_x": 76, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X29Y57", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y57": "SLICEM", + "SLICE_X43Y57": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y58": { + "bits": {}, + "grid_x": 76, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X29Y58", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y58": "SLICEM", + "SLICE_X43Y58": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y59": { + "bits": {}, + "grid_x": 76, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X29Y59", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y59": "SLICEM", + "SLICE_X43Y59": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y6": { + "bits": {}, + "grid_x": 76, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X29Y6", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y6": "SLICEM", + "SLICE_X43Y6": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y60": { + "bits": {}, + "grid_x": 76, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X29Y60", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y60": "SLICEM", + "SLICE_X43Y60": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y61": { + "bits": {}, + "grid_x": 76, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X29Y61", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y61": "SLICEM", + "SLICE_X43Y61": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y62": { + "bits": {}, + "grid_x": 76, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X29Y62", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y62": "SLICEM", + "SLICE_X43Y62": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y63": { + "bits": {}, + "grid_x": 76, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X29Y63", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y63": "SLICEM", + "SLICE_X43Y63": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y64": { + "bits": {}, + "grid_x": 76, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X29Y64", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y64": "SLICEM", + "SLICE_X43Y64": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y65": { + "bits": {}, + "grid_x": 76, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X29Y65", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y65": "SLICEM", + "SLICE_X43Y65": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y66": { + "bits": {}, + "grid_x": 76, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X29Y66", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y66": "SLICEM", + "SLICE_X43Y66": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y67": { + "bits": {}, + "grid_x": 76, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X29Y67", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y67": "SLICEM", + "SLICE_X43Y67": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y68": { + "bits": {}, + "grid_x": 76, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X29Y68", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y68": "SLICEM", + "SLICE_X43Y68": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y69": { + "bits": {}, + "grid_x": 76, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X29Y69", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y69": "SLICEM", + "SLICE_X43Y69": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y7": { + "bits": {}, + "grid_x": 76, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X29Y7", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y7": "SLICEM", + "SLICE_X43Y7": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y70": { + "bits": {}, + "grid_x": 76, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X29Y70", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y70": "SLICEM", + "SLICE_X43Y70": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y71": { + "bits": {}, + "grid_x": 76, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X29Y71", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y71": "SLICEM", + "SLICE_X43Y71": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y72": { + "bits": {}, + "grid_x": 76, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X29Y72", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y72": "SLICEM", + "SLICE_X43Y72": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y73": { + "bits": {}, + "grid_x": 76, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X29Y73", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y73": "SLICEM", + "SLICE_X43Y73": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y74": { + "bits": {}, + "grid_x": 76, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X29Y74", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y74": "SLICEM", + "SLICE_X43Y74": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y75": { + "bits": {}, + "grid_x": 76, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X29Y75", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y75": "SLICEM", + "SLICE_X43Y75": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y76": { + "bits": {}, + "grid_x": 76, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X29Y76", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y76": "SLICEM", + "SLICE_X43Y76": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y77": { + "bits": {}, + "grid_x": 76, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X29Y77", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y77": "SLICEM", + "SLICE_X43Y77": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y78": { + "bits": {}, + "grid_x": 76, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X29Y78", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y78": "SLICEM", + "SLICE_X43Y78": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y79": { + "bits": {}, + "grid_x": 76, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X29Y79", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y79": "SLICEM", + "SLICE_X43Y79": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y8": { + "bits": {}, + "grid_x": 76, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X29Y8", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y8": "SLICEM", + "SLICE_X43Y8": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y80": { + "bits": {}, + "grid_x": 76, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X29Y80", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y80": "SLICEM", + "SLICE_X43Y80": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y81": { + "bits": {}, + "grid_x": 76, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X29Y81", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y81": "SLICEM", + "SLICE_X43Y81": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y82": { + "bits": {}, + "grid_x": 76, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X29Y82", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y82": "SLICEM", + "SLICE_X43Y82": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y83": { + "bits": {}, + "grid_x": 76, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X29Y83", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y83": "SLICEM", + "SLICE_X43Y83": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y84": { + "bits": {}, + "grid_x": 76, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X29Y84", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y84": "SLICEM", + "SLICE_X43Y84": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y85": { + "bits": {}, + "grid_x": 76, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X29Y85", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y85": "SLICEM", + "SLICE_X43Y85": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y86": { + "bits": {}, + "grid_x": 76, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X29Y86", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y86": "SLICEM", + "SLICE_X43Y86": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y87": { + "bits": {}, + "grid_x": 76, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X29Y87", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y87": "SLICEM", + "SLICE_X43Y87": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y88": { + "bits": {}, + "grid_x": 76, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X29Y88", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y88": "SLICEM", + "SLICE_X43Y88": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y89": { + "bits": {}, + "grid_x": 76, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X29Y89", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y89": "SLICEM", + "SLICE_X43Y89": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y9": { + "bits": {}, + "grid_x": 76, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X29Y9", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y9": "SLICEM", + "SLICE_X43Y9": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y90": { + "bits": {}, + "grid_x": 76, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X29Y90", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y90": "SLICEM", + "SLICE_X43Y90": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y91": { + "bits": {}, + "grid_x": 76, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X29Y91", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y91": "SLICEM", + "SLICE_X43Y91": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y92": { + "bits": {}, + "grid_x": 76, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X29Y92", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y92": "SLICEM", + "SLICE_X43Y92": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y93": { + "bits": {}, + "grid_x": 76, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X29Y93", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y93": "SLICEM", + "SLICE_X43Y93": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y94": { + "bits": {}, + "grid_x": 76, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X29Y94", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y94": "SLICEM", + "SLICE_X43Y94": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y95": { + "bits": {}, + "grid_x": 76, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X29Y95", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y95": "SLICEM", + "SLICE_X43Y95": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y96": { + "bits": {}, + "grid_x": 76, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X29Y96", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y96": "SLICEM", + "SLICE_X43Y96": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y97": { + "bits": {}, + "grid_x": 76, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X29Y97", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y97": "SLICEM", + "SLICE_X43Y97": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y98": { + "bits": {}, + "grid_x": 76, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X29Y98", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y98": "SLICEM", + "SLICE_X43Y98": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X29Y99": { + "bits": {}, + "grid_x": 76, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X29Y99", + "segment_type": "clblm_r", + "sites": { + "SLICE_X42Y99": "SLICEM", + "SLICE_X43Y99": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y0": { + "bits": {}, + "grid_x": 81, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X31Y0", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y0": "SLICEM", + "SLICE_X45Y0": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y1": { + "bits": {}, + "grid_x": 81, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X31Y1", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y1": "SLICEM", + "SLICE_X45Y1": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y10": { + "bits": {}, + "grid_x": 81, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X31Y10", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y10": "SLICEM", + "SLICE_X45Y10": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y100": { + "bits": {}, + "grid_x": 81, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X31Y100", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y100": "SLICEM", + "SLICE_X45Y100": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y101": { + "bits": {}, + "grid_x": 81, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X31Y101", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y101": "SLICEM", + "SLICE_X45Y101": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y102": { + "bits": {}, + "grid_x": 81, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X31Y102", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y102": "SLICEM", + "SLICE_X45Y102": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y103": { + "bits": {}, + "grid_x": 81, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X31Y103", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y103": "SLICEM", + "SLICE_X45Y103": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y104": { + "bits": {}, + "grid_x": 81, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X31Y104", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y104": "SLICEM", + "SLICE_X45Y104": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y105": { + "bits": {}, + "grid_x": 81, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X31Y105", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y105": "SLICEM", + "SLICE_X45Y105": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y106": { + "bits": {}, + "grid_x": 81, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X31Y106", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y106": "SLICEM", + "SLICE_X45Y106": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y107": { + "bits": {}, + "grid_x": 81, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X31Y107", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y107": "SLICEM", + "SLICE_X45Y107": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y108": { + "bits": {}, + "grid_x": 81, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X31Y108", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y108": "SLICEM", + "SLICE_X45Y108": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y109": { + "bits": {}, + "grid_x": 81, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X31Y109", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y109": "SLICEM", + "SLICE_X45Y109": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y11": { + "bits": {}, + "grid_x": 81, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X31Y11", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y11": "SLICEM", + "SLICE_X45Y11": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y110": { + "bits": {}, + "grid_x": 81, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X31Y110", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y110": "SLICEM", + "SLICE_X45Y110": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y111": { + "bits": {}, + "grid_x": 81, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X31Y111", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y111": "SLICEM", + "SLICE_X45Y111": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y112": { + "bits": {}, + "grid_x": 81, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X31Y112", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y112": "SLICEM", + "SLICE_X45Y112": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y113": { + "bits": {}, + "grid_x": 81, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X31Y113", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y113": "SLICEM", + "SLICE_X45Y113": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y114": { + "bits": {}, + "grid_x": 81, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X31Y114", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y114": "SLICEM", + "SLICE_X45Y114": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y115": { + "bits": {}, + "grid_x": 81, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X31Y115", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y115": "SLICEM", + "SLICE_X45Y115": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y116": { + "bits": {}, + "grid_x": 81, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X31Y116", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y116": "SLICEM", + "SLICE_X45Y116": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y117": { + "bits": {}, + "grid_x": 81, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X31Y117", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y117": "SLICEM", + "SLICE_X45Y117": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y118": { + "bits": {}, + "grid_x": 81, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X31Y118", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y118": "SLICEM", + "SLICE_X45Y118": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y119": { + "bits": {}, + "grid_x": 81, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X31Y119", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y119": "SLICEM", + "SLICE_X45Y119": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y12": { + "bits": {}, + "grid_x": 81, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X31Y12", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y12": "SLICEM", + "SLICE_X45Y12": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y120": { + "bits": {}, + "grid_x": 81, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X31Y120", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y120": "SLICEM", + "SLICE_X45Y120": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y121": { + "bits": {}, + "grid_x": 81, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X31Y121", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y121": "SLICEM", + "SLICE_X45Y121": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y122": { + "bits": {}, + "grid_x": 81, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X31Y122", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y122": "SLICEM", + "SLICE_X45Y122": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y123": { + "bits": {}, + "grid_x": 81, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X31Y123", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y123": "SLICEM", + "SLICE_X45Y123": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y124": { + "bits": {}, + "grid_x": 81, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X31Y124", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y124": "SLICEM", + "SLICE_X45Y124": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y125": { + "bits": {}, + "grid_x": 81, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X31Y125", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y125": "SLICEM", + "SLICE_X45Y125": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y126": { + "bits": {}, + "grid_x": 81, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X31Y126", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y126": "SLICEM", + "SLICE_X45Y126": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y127": { + "bits": {}, + "grid_x": 81, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X31Y127", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y127": "SLICEM", + "SLICE_X45Y127": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y128": { + "bits": {}, + "grid_x": 81, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X31Y128", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y128": "SLICEM", + "SLICE_X45Y128": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y129": { + "bits": {}, + "grid_x": 81, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X31Y129", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y129": "SLICEM", + "SLICE_X45Y129": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y13": { + "bits": {}, + "grid_x": 81, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X31Y13", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y13": "SLICEM", + "SLICE_X45Y13": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y130": { + "bits": {}, + "grid_x": 81, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X31Y130", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y130": "SLICEM", + "SLICE_X45Y130": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y131": { + "bits": {}, + "grid_x": 81, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X31Y131", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y131": "SLICEM", + "SLICE_X45Y131": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y132": { + "bits": {}, + "grid_x": 81, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X31Y132", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y132": "SLICEM", + "SLICE_X45Y132": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y133": { + "bits": {}, + "grid_x": 81, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X31Y133", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y133": "SLICEM", + "SLICE_X45Y133": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y134": { + "bits": {}, + "grid_x": 81, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X31Y134", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y134": "SLICEM", + "SLICE_X45Y134": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y135": { + "bits": {}, + "grid_x": 81, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X31Y135", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y135": "SLICEM", + "SLICE_X45Y135": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y136": { + "bits": {}, + "grid_x": 81, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X31Y136", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y136": "SLICEM", + "SLICE_X45Y136": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y137": { + "bits": {}, + "grid_x": 81, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X31Y137", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y137": "SLICEM", + "SLICE_X45Y137": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y138": { + "bits": {}, + "grid_x": 81, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X31Y138", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y138": "SLICEM", + "SLICE_X45Y138": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y139": { + "bits": {}, + "grid_x": 81, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X31Y139", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y139": "SLICEM", + "SLICE_X45Y139": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y14": { + "bits": {}, + "grid_x": 81, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X31Y14", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y14": "SLICEM", + "SLICE_X45Y14": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y140": { + "bits": {}, + "grid_x": 81, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X31Y140", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y140": "SLICEM", + "SLICE_X45Y140": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y141": { + "bits": {}, + "grid_x": 81, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X31Y141", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y141": "SLICEM", + "SLICE_X45Y141": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y142": { + "bits": {}, + "grid_x": 81, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X31Y142", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y142": "SLICEM", + "SLICE_X45Y142": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y143": { + "bits": {}, + "grid_x": 81, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X31Y143", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y143": "SLICEM", + "SLICE_X45Y143": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y144": { + "bits": {}, + "grid_x": 81, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X31Y144", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y144": "SLICEM", + "SLICE_X45Y144": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y145": { + "bits": {}, + "grid_x": 81, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X31Y145", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y145": "SLICEM", + "SLICE_X45Y145": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y146": { + "bits": {}, + "grid_x": 81, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X31Y146", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y146": "SLICEM", + "SLICE_X45Y146": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y147": { + "bits": {}, + "grid_x": 81, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X31Y147", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y147": "SLICEM", + "SLICE_X45Y147": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y148": { + "bits": {}, + "grid_x": 81, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X31Y148", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y148": "SLICEM", + "SLICE_X45Y148": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y149": { + "bits": {}, + "grid_x": 81, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X31Y149", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y149": "SLICEM", + "SLICE_X45Y149": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y15": { + "bits": {}, + "grid_x": 81, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X31Y15", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y15": "SLICEM", + "SLICE_X45Y15": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y150": { + "bits": {}, + "grid_x": 81, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X31Y150", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y150": "SLICEM", + "SLICE_X45Y150": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y151": { + "bits": {}, + "grid_x": 81, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X31Y151", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y151": "SLICEM", + "SLICE_X45Y151": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y152": { + "bits": {}, + "grid_x": 81, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X31Y152", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y152": "SLICEM", + "SLICE_X45Y152": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y153": { + "bits": {}, + "grid_x": 81, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X31Y153", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y153": "SLICEM", + "SLICE_X45Y153": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y154": { + "bits": {}, + "grid_x": 81, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X31Y154", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y154": "SLICEM", + "SLICE_X45Y154": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y155": { + "bits": {}, + "grid_x": 81, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X31Y155", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y155": "SLICEM", + "SLICE_X45Y155": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y156": { + "bits": {}, + "grid_x": 81, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X31Y156", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y156": "SLICEM", + "SLICE_X45Y156": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y157": { + "bits": {}, + "grid_x": 81, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X31Y157", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y157": "SLICEM", + "SLICE_X45Y157": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y158": { + "bits": {}, + "grid_x": 81, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X31Y158", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y158": "SLICEM", + "SLICE_X45Y158": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y159": { + "bits": {}, + "grid_x": 81, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X31Y159", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y159": "SLICEM", + "SLICE_X45Y159": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y16": { + "bits": {}, + "grid_x": 81, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X31Y16", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y16": "SLICEM", + "SLICE_X45Y16": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y160": { + "bits": {}, + "grid_x": 81, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X31Y160", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y160": "SLICEM", + "SLICE_X45Y160": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y161": { + "bits": {}, + "grid_x": 81, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X31Y161", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y161": "SLICEM", + "SLICE_X45Y161": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y162": { + "bits": {}, + "grid_x": 81, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X31Y162", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y162": "SLICEM", + "SLICE_X45Y162": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y163": { + "bits": {}, + "grid_x": 81, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X31Y163", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y163": "SLICEM", + "SLICE_X45Y163": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y164": { + "bits": {}, + "grid_x": 81, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X31Y164", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y164": "SLICEM", + "SLICE_X45Y164": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y165": { + "bits": {}, + "grid_x": 81, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X31Y165", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y165": "SLICEM", + "SLICE_X45Y165": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y166": { + "bits": {}, + "grid_x": 81, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X31Y166", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y166": "SLICEM", + "SLICE_X45Y166": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y167": { + "bits": {}, + "grid_x": 81, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X31Y167", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y167": "SLICEM", + "SLICE_X45Y167": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y168": { + "bits": {}, + "grid_x": 81, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X31Y168", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y168": "SLICEM", + "SLICE_X45Y168": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y169": { + "bits": {}, + "grid_x": 81, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X31Y169", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y169": "SLICEM", + "SLICE_X45Y169": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y17": { + "bits": {}, + "grid_x": 81, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X31Y17", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y17": "SLICEM", + "SLICE_X45Y17": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y170": { + "bits": {}, + "grid_x": 81, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X31Y170", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y170": "SLICEM", + "SLICE_X45Y170": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y171": { + "bits": {}, + "grid_x": 81, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X31Y171", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y171": "SLICEM", + "SLICE_X45Y171": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y172": { + "bits": {}, + "grid_x": 81, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X31Y172", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y172": "SLICEM", + "SLICE_X45Y172": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y173": { + "bits": {}, + "grid_x": 81, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X31Y173", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y173": "SLICEM", + "SLICE_X45Y173": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y174": { + "bits": {}, + "grid_x": 81, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X31Y174", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y174": "SLICEM", + "SLICE_X45Y174": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y175": { + "bits": {}, + "grid_x": 81, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X31Y175", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y175": "SLICEM", + "SLICE_X45Y175": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y176": { + "bits": {}, + "grid_x": 81, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X31Y176", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y176": "SLICEM", + "SLICE_X45Y176": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y177": { + "bits": {}, + "grid_x": 81, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X31Y177", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y177": "SLICEM", + "SLICE_X45Y177": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y178": { + "bits": {}, + "grid_x": 81, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X31Y178", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y178": "SLICEM", + "SLICE_X45Y178": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y179": { + "bits": {}, + "grid_x": 81, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X31Y179", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y179": "SLICEM", + "SLICE_X45Y179": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y18": { + "bits": {}, + "grid_x": 81, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X31Y18", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y18": "SLICEM", + "SLICE_X45Y18": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y180": { + "bits": {}, + "grid_x": 81, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X31Y180", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y180": "SLICEM", + "SLICE_X45Y180": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y181": { + "bits": {}, + "grid_x": 81, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X31Y181", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y181": "SLICEM", + "SLICE_X45Y181": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y182": { + "bits": {}, + "grid_x": 81, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X31Y182", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y182": "SLICEM", + "SLICE_X45Y182": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y183": { + "bits": {}, + "grid_x": 81, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X31Y183", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y183": "SLICEM", + "SLICE_X45Y183": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y184": { + "bits": {}, + "grid_x": 81, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X31Y184", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y184": "SLICEM", + "SLICE_X45Y184": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y185": { + "bits": {}, + "grid_x": 81, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X31Y185", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y185": "SLICEM", + "SLICE_X45Y185": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y186": { + "bits": {}, + "grid_x": 81, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X31Y186", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y186": "SLICEM", + "SLICE_X45Y186": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y187": { + "bits": {}, + "grid_x": 81, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X31Y187", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y187": "SLICEM", + "SLICE_X45Y187": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y188": { + "bits": {}, + "grid_x": 81, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X31Y188", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y188": "SLICEM", + "SLICE_X45Y188": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y189": { + "bits": {}, + "grid_x": 81, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X31Y189", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y189": "SLICEM", + "SLICE_X45Y189": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y19": { + "bits": {}, + "grid_x": 81, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X31Y19", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y19": "SLICEM", + "SLICE_X45Y19": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y190": { + "bits": {}, + "grid_x": 81, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X31Y190", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y190": "SLICEM", + "SLICE_X45Y190": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y191": { + "bits": {}, + "grid_x": 81, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X31Y191", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y191": "SLICEM", + "SLICE_X45Y191": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y192": { + "bits": {}, + "grid_x": 81, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X31Y192", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y192": "SLICEM", + "SLICE_X45Y192": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y193": { + "bits": {}, + "grid_x": 81, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X31Y193", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y193": "SLICEM", + "SLICE_X45Y193": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y194": { + "bits": {}, + "grid_x": 81, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X31Y194", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y194": "SLICEM", + "SLICE_X45Y194": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y195": { + "bits": {}, + "grid_x": 81, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X31Y195", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y195": "SLICEM", + "SLICE_X45Y195": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y196": { + "bits": {}, + "grid_x": 81, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X31Y196", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y196": "SLICEM", + "SLICE_X45Y196": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y197": { + "bits": {}, + "grid_x": 81, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X31Y197", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y197": "SLICEM", + "SLICE_X45Y197": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y198": { + "bits": {}, + "grid_x": 81, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X31Y198", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y198": "SLICEM", + "SLICE_X45Y198": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y199": { + "bits": {}, + "grid_x": 81, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X31Y199", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y199": "SLICEM", + "SLICE_X45Y199": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y2": { + "bits": {}, + "grid_x": 81, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X31Y2", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y2": "SLICEM", + "SLICE_X45Y2": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y20": { + "bits": {}, + "grid_x": 81, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X31Y20", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y20": "SLICEM", + "SLICE_X45Y20": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y21": { + "bits": {}, + "grid_x": 81, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X31Y21", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y21": "SLICEM", + "SLICE_X45Y21": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y22": { + "bits": {}, + "grid_x": 81, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X31Y22", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y22": "SLICEM", + "SLICE_X45Y22": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y23": { + "bits": {}, + "grid_x": 81, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X31Y23", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y23": "SLICEM", + "SLICE_X45Y23": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y24": { + "bits": {}, + "grid_x": 81, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X31Y24", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y24": "SLICEM", + "SLICE_X45Y24": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y25": { + "bits": {}, + "grid_x": 81, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X31Y25", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y25": "SLICEM", + "SLICE_X45Y25": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y26": { + "bits": {}, + "grid_x": 81, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X31Y26", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y26": "SLICEM", + "SLICE_X45Y26": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y27": { + "bits": {}, + "grid_x": 81, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X31Y27", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y27": "SLICEM", + "SLICE_X45Y27": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y28": { + "bits": {}, + "grid_x": 81, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X31Y28", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y28": "SLICEM", + "SLICE_X45Y28": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y29": { + "bits": {}, + "grid_x": 81, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X31Y29", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y29": "SLICEM", + "SLICE_X45Y29": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y3": { + "bits": {}, + "grid_x": 81, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X31Y3", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y3": "SLICEM", + "SLICE_X45Y3": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y30": { + "bits": {}, + "grid_x": 81, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X31Y30", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y30": "SLICEM", + "SLICE_X45Y30": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y31": { + "bits": {}, + "grid_x": 81, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X31Y31", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y31": "SLICEM", + "SLICE_X45Y31": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y32": { + "bits": {}, + "grid_x": 81, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X31Y32", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y32": "SLICEM", + "SLICE_X45Y32": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y33": { + "bits": {}, + "grid_x": 81, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X31Y33", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y33": "SLICEM", + "SLICE_X45Y33": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y34": { + "bits": {}, + "grid_x": 81, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X31Y34", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y34": "SLICEM", + "SLICE_X45Y34": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y35": { + "bits": {}, + "grid_x": 81, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X31Y35", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y35": "SLICEM", + "SLICE_X45Y35": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y36": { + "bits": {}, + "grid_x": 81, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X31Y36", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y36": "SLICEM", + "SLICE_X45Y36": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y37": { + "bits": {}, + "grid_x": 81, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X31Y37", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y37": "SLICEM", + "SLICE_X45Y37": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y38": { + "bits": {}, + "grid_x": 81, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X31Y38", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y38": "SLICEM", + "SLICE_X45Y38": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y39": { + "bits": {}, + "grid_x": 81, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X31Y39", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y39": "SLICEM", + "SLICE_X45Y39": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y4": { + "bits": {}, + "grid_x": 81, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X31Y4", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y4": "SLICEM", + "SLICE_X45Y4": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y40": { + "bits": {}, + "grid_x": 81, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X31Y40", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y40": "SLICEM", + "SLICE_X45Y40": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y41": { + "bits": {}, + "grid_x": 81, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X31Y41", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y41": "SLICEM", + "SLICE_X45Y41": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y42": { + "bits": {}, + "grid_x": 81, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X31Y42", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y42": "SLICEM", + "SLICE_X45Y42": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y43": { + "bits": {}, + "grid_x": 81, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X31Y43", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y43": "SLICEM", + "SLICE_X45Y43": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y44": { + "bits": {}, + "grid_x": 81, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X31Y44", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y44": "SLICEM", + "SLICE_X45Y44": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y45": { + "bits": {}, + "grid_x": 81, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X31Y45", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y45": "SLICEM", + "SLICE_X45Y45": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y46": { + "bits": {}, + "grid_x": 81, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X31Y46", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y46": "SLICEM", + "SLICE_X45Y46": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y47": { + "bits": {}, + "grid_x": 81, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X31Y47", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y47": "SLICEM", + "SLICE_X45Y47": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y48": { + "bits": {}, + "grid_x": 81, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X31Y48", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y48": "SLICEM", + "SLICE_X45Y48": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y49": { + "bits": {}, + "grid_x": 81, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X31Y49", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y49": "SLICEM", + "SLICE_X45Y49": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y5": { + "bits": {}, + "grid_x": 81, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X31Y5", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y5": "SLICEM", + "SLICE_X45Y5": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y50": { + "bits": {}, + "grid_x": 81, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X31Y50", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y50": "SLICEM", + "SLICE_X45Y50": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y51": { + "bits": {}, + "grid_x": 81, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X31Y51", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y51": "SLICEM", + "SLICE_X45Y51": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y52": { + "bits": {}, + "grid_x": 81, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X31Y52", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y52": "SLICEM", + "SLICE_X45Y52": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y53": { + "bits": {}, + "grid_x": 81, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X31Y53", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y53": "SLICEM", + "SLICE_X45Y53": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y54": { + "bits": {}, + "grid_x": 81, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X31Y54", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y54": "SLICEM", + "SLICE_X45Y54": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y55": { + "bits": {}, + "grid_x": 81, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X31Y55", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y55": "SLICEM", + "SLICE_X45Y55": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y56": { + "bits": {}, + "grid_x": 81, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X31Y56", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y56": "SLICEM", + "SLICE_X45Y56": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y57": { + "bits": {}, + "grid_x": 81, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X31Y57", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y57": "SLICEM", + "SLICE_X45Y57": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y58": { + "bits": {}, + "grid_x": 81, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X31Y58", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y58": "SLICEM", + "SLICE_X45Y58": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y59": { + "bits": {}, + "grid_x": 81, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X31Y59", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y59": "SLICEM", + "SLICE_X45Y59": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y6": { + "bits": {}, + "grid_x": 81, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X31Y6", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y6": "SLICEM", + "SLICE_X45Y6": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y60": { + "bits": {}, + "grid_x": 81, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X31Y60", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y60": "SLICEM", + "SLICE_X45Y60": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y61": { + "bits": {}, + "grid_x": 81, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X31Y61", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y61": "SLICEM", + "SLICE_X45Y61": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y62": { + "bits": {}, + "grid_x": 81, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X31Y62", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y62": "SLICEM", + "SLICE_X45Y62": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y63": { + "bits": {}, + "grid_x": 81, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X31Y63", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y63": "SLICEM", + "SLICE_X45Y63": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y64": { + "bits": {}, + "grid_x": 81, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X31Y64", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y64": "SLICEM", + "SLICE_X45Y64": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y65": { + "bits": {}, + "grid_x": 81, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X31Y65", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y65": "SLICEM", + "SLICE_X45Y65": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y66": { + "bits": {}, + "grid_x": 81, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X31Y66", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y66": "SLICEM", + "SLICE_X45Y66": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y67": { + "bits": {}, + "grid_x": 81, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X31Y67", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y67": "SLICEM", + "SLICE_X45Y67": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y68": { + "bits": {}, + "grid_x": 81, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X31Y68", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y68": "SLICEM", + "SLICE_X45Y68": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y69": { + "bits": {}, + "grid_x": 81, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X31Y69", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y69": "SLICEM", + "SLICE_X45Y69": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y7": { + "bits": {}, + "grid_x": 81, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X31Y7", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y7": "SLICEM", + "SLICE_X45Y7": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y70": { + "bits": {}, + "grid_x": 81, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X31Y70", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y70": "SLICEM", + "SLICE_X45Y70": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y71": { + "bits": {}, + "grid_x": 81, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X31Y71", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y71": "SLICEM", + "SLICE_X45Y71": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y72": { + "bits": {}, + "grid_x": 81, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X31Y72", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y72": "SLICEM", + "SLICE_X45Y72": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y73": { + "bits": {}, + "grid_x": 81, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X31Y73", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y73": "SLICEM", + "SLICE_X45Y73": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y74": { + "bits": {}, + "grid_x": 81, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X31Y74", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y74": "SLICEM", + "SLICE_X45Y74": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y75": { + "bits": {}, + "grid_x": 81, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X31Y75", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y75": "SLICEM", + "SLICE_X45Y75": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y76": { + "bits": {}, + "grid_x": 81, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X31Y76", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y76": "SLICEM", + "SLICE_X45Y76": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y77": { + "bits": {}, + "grid_x": 81, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X31Y77", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y77": "SLICEM", + "SLICE_X45Y77": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y78": { + "bits": {}, + "grid_x": 81, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X31Y78", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y78": "SLICEM", + "SLICE_X45Y78": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y79": { + "bits": {}, + "grid_x": 81, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X31Y79", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y79": "SLICEM", + "SLICE_X45Y79": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y8": { + "bits": {}, + "grid_x": 81, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X31Y8", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y8": "SLICEM", + "SLICE_X45Y8": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y80": { + "bits": {}, + "grid_x": 81, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X31Y80", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y80": "SLICEM", + "SLICE_X45Y80": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y81": { + "bits": {}, + "grid_x": 81, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X31Y81", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y81": "SLICEM", + "SLICE_X45Y81": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y82": { + "bits": {}, + "grid_x": 81, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X31Y82", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y82": "SLICEM", + "SLICE_X45Y82": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y83": { + "bits": {}, + "grid_x": 81, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X31Y83", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y83": "SLICEM", + "SLICE_X45Y83": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y84": { + "bits": {}, + "grid_x": 81, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X31Y84", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y84": "SLICEM", + "SLICE_X45Y84": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y85": { + "bits": {}, + "grid_x": 81, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X31Y85", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y85": "SLICEM", + "SLICE_X45Y85": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y86": { + "bits": {}, + "grid_x": 81, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X31Y86", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y86": "SLICEM", + "SLICE_X45Y86": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y87": { + "bits": {}, + "grid_x": 81, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X31Y87", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y87": "SLICEM", + "SLICE_X45Y87": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y88": { + "bits": {}, + "grid_x": 81, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X31Y88", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y88": "SLICEM", + "SLICE_X45Y88": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y89": { + "bits": {}, + "grid_x": 81, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X31Y89", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y89": "SLICEM", + "SLICE_X45Y89": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y9": { + "bits": {}, + "grid_x": 81, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X31Y9", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y9": "SLICEM", + "SLICE_X45Y9": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y90": { + "bits": {}, + "grid_x": 81, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X31Y90", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y90": "SLICEM", + "SLICE_X45Y90": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y91": { + "bits": {}, + "grid_x": 81, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X31Y91", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y91": "SLICEM", + "SLICE_X45Y91": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y92": { + "bits": {}, + "grid_x": 81, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X31Y92", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y92": "SLICEM", + "SLICE_X45Y92": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y93": { + "bits": {}, + "grid_x": 81, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X31Y93", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y93": "SLICEM", + "SLICE_X45Y93": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y94": { + "bits": {}, + "grid_x": 81, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X31Y94", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y94": "SLICEM", + "SLICE_X45Y94": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y95": { + "bits": {}, + "grid_x": 81, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X31Y95", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y95": "SLICEM", + "SLICE_X45Y95": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y96": { + "bits": {}, + "grid_x": 81, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X31Y96", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y96": "SLICEM", + "SLICE_X45Y96": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y97": { + "bits": {}, + "grid_x": 81, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X31Y97", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y97": "SLICEM", + "SLICE_X45Y97": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y98": { + "bits": {}, + "grid_x": 81, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X31Y98", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y98": "SLICEM", + "SLICE_X45Y98": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X31Y99": { + "bits": {}, + "grid_x": 81, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X31Y99", + "segment_type": "clblm_r", + "sites": { + "SLICE_X44Y99": "SLICEM", + "SLICE_X45Y99": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y0": { + "bits": {}, + "grid_x": 91, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X35Y0", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y0": "SLICEM", + "SLICE_X51Y0": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y1": { + "bits": {}, + "grid_x": 91, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X35Y1", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y1": "SLICEM", + "SLICE_X51Y1": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y10": { + "bits": {}, + "grid_x": 91, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X35Y10", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y10": "SLICEM", + "SLICE_X51Y10": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y100": { + "bits": {}, + "grid_x": 91, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X35Y100", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y100": "SLICEM", + "SLICE_X51Y100": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y101": { + "bits": {}, + "grid_x": 91, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X35Y101", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y101": "SLICEM", + "SLICE_X51Y101": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y102": { + "bits": {}, + "grid_x": 91, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X35Y102", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y102": "SLICEM", + "SLICE_X51Y102": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y103": { + "bits": {}, + "grid_x": 91, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X35Y103", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y103": "SLICEM", + "SLICE_X51Y103": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y104": { + "bits": {}, + "grid_x": 91, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X35Y104", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y104": "SLICEM", + "SLICE_X51Y104": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y105": { + "bits": {}, + "grid_x": 91, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X35Y105", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y105": "SLICEM", + "SLICE_X51Y105": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y106": { + "bits": {}, + "grid_x": 91, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X35Y106", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y106": "SLICEM", + "SLICE_X51Y106": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y107": { + "bits": {}, + "grid_x": 91, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X35Y107", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y107": "SLICEM", + "SLICE_X51Y107": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y108": { + "bits": {}, + "grid_x": 91, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X35Y108", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y108": "SLICEM", + "SLICE_X51Y108": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y109": { + "bits": {}, + "grid_x": 91, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X35Y109", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y109": "SLICEM", + "SLICE_X51Y109": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y11": { + "bits": {}, + "grid_x": 91, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X35Y11", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y11": "SLICEM", + "SLICE_X51Y11": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y110": { + "bits": {}, + "grid_x": 91, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X35Y110", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y110": "SLICEM", + "SLICE_X51Y110": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y111": { + "bits": {}, + "grid_x": 91, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X35Y111", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y111": "SLICEM", + "SLICE_X51Y111": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y112": { + "bits": {}, + "grid_x": 91, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X35Y112", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y112": "SLICEM", + "SLICE_X51Y112": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y113": { + "bits": {}, + "grid_x": 91, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X35Y113", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y113": "SLICEM", + "SLICE_X51Y113": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y114": { + "bits": {}, + "grid_x": 91, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X35Y114", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y114": "SLICEM", + "SLICE_X51Y114": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y115": { + "bits": {}, + "grid_x": 91, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X35Y115", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y115": "SLICEM", + "SLICE_X51Y115": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y116": { + "bits": {}, + "grid_x": 91, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X35Y116", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y116": "SLICEM", + "SLICE_X51Y116": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y117": { + "bits": {}, + "grid_x": 91, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X35Y117", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y117": "SLICEM", + "SLICE_X51Y117": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y118": { + "bits": {}, + "grid_x": 91, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X35Y118", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y118": "SLICEM", + "SLICE_X51Y118": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y119": { + "bits": {}, + "grid_x": 91, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X35Y119", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y119": "SLICEM", + "SLICE_X51Y119": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y12": { + "bits": {}, + "grid_x": 91, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X35Y12", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y12": "SLICEM", + "SLICE_X51Y12": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y120": { + "bits": {}, + "grid_x": 91, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X35Y120", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y120": "SLICEM", + "SLICE_X51Y120": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y121": { + "bits": {}, + "grid_x": 91, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X35Y121", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y121": "SLICEM", + "SLICE_X51Y121": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y122": { + "bits": {}, + "grid_x": 91, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X35Y122", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y122": "SLICEM", + "SLICE_X51Y122": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y123": { + "bits": {}, + "grid_x": 91, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X35Y123", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y123": "SLICEM", + "SLICE_X51Y123": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y124": { + "bits": {}, + "grid_x": 91, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X35Y124", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y124": "SLICEM", + "SLICE_X51Y124": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y125": { + "bits": {}, + "grid_x": 91, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X35Y125", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y125": "SLICEM", + "SLICE_X51Y125": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y126": { + "bits": {}, + "grid_x": 91, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X35Y126", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y126": "SLICEM", + "SLICE_X51Y126": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y127": { + "bits": {}, + "grid_x": 91, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X35Y127", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y127": "SLICEM", + "SLICE_X51Y127": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y128": { + "bits": {}, + "grid_x": 91, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X35Y128", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y128": "SLICEM", + "SLICE_X51Y128": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y129": { + "bits": {}, + "grid_x": 91, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X35Y129", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y129": "SLICEM", + "SLICE_X51Y129": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y13": { + "bits": {}, + "grid_x": 91, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X35Y13", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y13": "SLICEM", + "SLICE_X51Y13": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y130": { + "bits": {}, + "grid_x": 91, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X35Y130", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y130": "SLICEM", + "SLICE_X51Y130": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y131": { + "bits": {}, + "grid_x": 91, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X35Y131", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y131": "SLICEM", + "SLICE_X51Y131": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y132": { + "bits": {}, + "grid_x": 91, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X35Y132", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y132": "SLICEM", + "SLICE_X51Y132": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y133": { + "bits": {}, + "grid_x": 91, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X35Y133", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y133": "SLICEM", + "SLICE_X51Y133": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y134": { + "bits": {}, + "grid_x": 91, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X35Y134", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y134": "SLICEM", + "SLICE_X51Y134": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y135": { + "bits": {}, + "grid_x": 91, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X35Y135", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y135": "SLICEM", + "SLICE_X51Y135": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y136": { + "bits": {}, + "grid_x": 91, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X35Y136", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y136": "SLICEM", + "SLICE_X51Y136": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y137": { + "bits": {}, + "grid_x": 91, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X35Y137", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y137": "SLICEM", + "SLICE_X51Y137": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y138": { + "bits": {}, + "grid_x": 91, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X35Y138", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y138": "SLICEM", + "SLICE_X51Y138": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y139": { + "bits": {}, + "grid_x": 91, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X35Y139", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y139": "SLICEM", + "SLICE_X51Y139": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y14": { + "bits": {}, + "grid_x": 91, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X35Y14", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y14": "SLICEM", + "SLICE_X51Y14": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y140": { + "bits": {}, + "grid_x": 91, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X35Y140", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y140": "SLICEM", + "SLICE_X51Y140": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y141": { + "bits": {}, + "grid_x": 91, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X35Y141", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y141": "SLICEM", + "SLICE_X51Y141": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y142": { + "bits": {}, + "grid_x": 91, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X35Y142", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y142": "SLICEM", + "SLICE_X51Y142": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y143": { + "bits": {}, + "grid_x": 91, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X35Y143", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y143": "SLICEM", + "SLICE_X51Y143": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y144": { + "bits": {}, + "grid_x": 91, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X35Y144", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y144": "SLICEM", + "SLICE_X51Y144": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y145": { + "bits": {}, + "grid_x": 91, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X35Y145", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y145": "SLICEM", + "SLICE_X51Y145": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y146": { + "bits": {}, + "grid_x": 91, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X35Y146", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y146": "SLICEM", + "SLICE_X51Y146": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y147": { + "bits": {}, + "grid_x": 91, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X35Y147", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y147": "SLICEM", + "SLICE_X51Y147": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y148": { + "bits": {}, + "grid_x": 91, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X35Y148", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y148": "SLICEM", + "SLICE_X51Y148": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y149": { + "bits": {}, + "grid_x": 91, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X35Y149", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y149": "SLICEM", + "SLICE_X51Y149": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y15": { + "bits": {}, + "grid_x": 91, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X35Y15", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y15": "SLICEM", + "SLICE_X51Y15": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y150": { + "bits": {}, + "grid_x": 91, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X35Y150", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y150": "SLICEM", + "SLICE_X51Y150": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y151": { + "bits": {}, + "grid_x": 91, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X35Y151", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y151": "SLICEM", + "SLICE_X51Y151": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y152": { + "bits": {}, + "grid_x": 91, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X35Y152", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y152": "SLICEM", + "SLICE_X51Y152": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y153": { + "bits": {}, + "grid_x": 91, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X35Y153", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y153": "SLICEM", + "SLICE_X51Y153": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y154": { + "bits": {}, + "grid_x": 91, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X35Y154", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y154": "SLICEM", + "SLICE_X51Y154": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y155": { + "bits": {}, + "grid_x": 91, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X35Y155", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y155": "SLICEM", + "SLICE_X51Y155": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y156": { + "bits": {}, + "grid_x": 91, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X35Y156", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y156": "SLICEM", + "SLICE_X51Y156": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y157": { + "bits": {}, + "grid_x": 91, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X35Y157", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y157": "SLICEM", + "SLICE_X51Y157": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y158": { + "bits": {}, + "grid_x": 91, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X35Y158", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y158": "SLICEM", + "SLICE_X51Y158": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y159": { + "bits": {}, + "grid_x": 91, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X35Y159", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y159": "SLICEM", + "SLICE_X51Y159": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y16": { + "bits": {}, + "grid_x": 91, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X35Y16", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y16": "SLICEM", + "SLICE_X51Y16": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y160": { + "bits": {}, + "grid_x": 91, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X35Y160", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y160": "SLICEM", + "SLICE_X51Y160": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y161": { + "bits": {}, + "grid_x": 91, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X35Y161", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y161": "SLICEM", + "SLICE_X51Y161": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y162": { + "bits": {}, + "grid_x": 91, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X35Y162", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y162": "SLICEM", + "SLICE_X51Y162": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y163": { + "bits": {}, + "grid_x": 91, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X35Y163", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y163": "SLICEM", + "SLICE_X51Y163": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y164": { + "bits": {}, + "grid_x": 91, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X35Y164", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y164": "SLICEM", + "SLICE_X51Y164": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y165": { + "bits": {}, + "grid_x": 91, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X35Y165", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y165": "SLICEM", + "SLICE_X51Y165": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y166": { + "bits": {}, + "grid_x": 91, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X35Y166", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y166": "SLICEM", + "SLICE_X51Y166": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y167": { + "bits": {}, + "grid_x": 91, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X35Y167", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y167": "SLICEM", + "SLICE_X51Y167": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y168": { + "bits": {}, + "grid_x": 91, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X35Y168", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y168": "SLICEM", + "SLICE_X51Y168": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y169": { + "bits": {}, + "grid_x": 91, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X35Y169", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y169": "SLICEM", + "SLICE_X51Y169": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y17": { + "bits": {}, + "grid_x": 91, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X35Y17", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y17": "SLICEM", + "SLICE_X51Y17": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y170": { + "bits": {}, + "grid_x": 91, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X35Y170", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y170": "SLICEM", + "SLICE_X51Y170": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y171": { + "bits": {}, + "grid_x": 91, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X35Y171", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y171": "SLICEM", + "SLICE_X51Y171": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y172": { + "bits": {}, + "grid_x": 91, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X35Y172", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y172": "SLICEM", + "SLICE_X51Y172": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y173": { + "bits": {}, + "grid_x": 91, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X35Y173", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y173": "SLICEM", + "SLICE_X51Y173": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y174": { + "bits": {}, + "grid_x": 91, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X35Y174", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y174": "SLICEM", + "SLICE_X51Y174": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y175": { + "bits": {}, + "grid_x": 91, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X35Y175", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y175": "SLICEM", + "SLICE_X51Y175": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y176": { + "bits": {}, + "grid_x": 91, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X35Y176", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y176": "SLICEM", + "SLICE_X51Y176": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y177": { + "bits": {}, + "grid_x": 91, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X35Y177", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y177": "SLICEM", + "SLICE_X51Y177": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y178": { + "bits": {}, + "grid_x": 91, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X35Y178", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y178": "SLICEM", + "SLICE_X51Y178": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y179": { + "bits": {}, + "grid_x": 91, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X35Y179", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y179": "SLICEM", + "SLICE_X51Y179": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y18": { + "bits": {}, + "grid_x": 91, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X35Y18", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y18": "SLICEM", + "SLICE_X51Y18": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y180": { + "bits": {}, + "grid_x": 91, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X35Y180", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y180": "SLICEM", + "SLICE_X51Y180": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y181": { + "bits": {}, + "grid_x": 91, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X35Y181", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y181": "SLICEM", + "SLICE_X51Y181": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y182": { + "bits": {}, + "grid_x": 91, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X35Y182", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y182": "SLICEM", + "SLICE_X51Y182": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y183": { + "bits": {}, + "grid_x": 91, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X35Y183", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y183": "SLICEM", + "SLICE_X51Y183": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y184": { + "bits": {}, + "grid_x": 91, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X35Y184", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y184": "SLICEM", + "SLICE_X51Y184": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y185": { + "bits": {}, + "grid_x": 91, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X35Y185", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y185": "SLICEM", + "SLICE_X51Y185": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y186": { + "bits": {}, + "grid_x": 91, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X35Y186", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y186": "SLICEM", + "SLICE_X51Y186": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y187": { + "bits": {}, + "grid_x": 91, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X35Y187", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y187": "SLICEM", + "SLICE_X51Y187": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y188": { + "bits": {}, + "grid_x": 91, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X35Y188", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y188": "SLICEM", + "SLICE_X51Y188": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y189": { + "bits": {}, + "grid_x": 91, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X35Y189", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y189": "SLICEM", + "SLICE_X51Y189": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y19": { + "bits": {}, + "grid_x": 91, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X35Y19", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y19": "SLICEM", + "SLICE_X51Y19": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y190": { + "bits": {}, + "grid_x": 91, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X35Y190", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y190": "SLICEM", + "SLICE_X51Y190": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y191": { + "bits": {}, + "grid_x": 91, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X35Y191", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y191": "SLICEM", + "SLICE_X51Y191": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y192": { + "bits": {}, + "grid_x": 91, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X35Y192", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y192": "SLICEM", + "SLICE_X51Y192": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y193": { + "bits": {}, + "grid_x": 91, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X35Y193", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y193": "SLICEM", + "SLICE_X51Y193": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y194": { + "bits": {}, + "grid_x": 91, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X35Y194", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y194": "SLICEM", + "SLICE_X51Y194": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y195": { + "bits": {}, + "grid_x": 91, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X35Y195", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y195": "SLICEM", + "SLICE_X51Y195": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y196": { + "bits": {}, + "grid_x": 91, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X35Y196", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y196": "SLICEM", + "SLICE_X51Y196": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y197": { + "bits": {}, + "grid_x": 91, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X35Y197", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y197": "SLICEM", + "SLICE_X51Y197": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y198": { + "bits": {}, + "grid_x": 91, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X35Y198", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y198": "SLICEM", + "SLICE_X51Y198": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y199": { + "bits": {}, + "grid_x": 91, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X35Y199", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y199": "SLICEM", + "SLICE_X51Y199": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y2": { + "bits": {}, + "grid_x": 91, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X35Y2", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y2": "SLICEM", + "SLICE_X51Y2": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y20": { + "bits": {}, + "grid_x": 91, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X35Y20", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y20": "SLICEM", + "SLICE_X51Y20": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y21": { + "bits": {}, + "grid_x": 91, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X35Y21", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y21": "SLICEM", + "SLICE_X51Y21": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y22": { + "bits": {}, + "grid_x": 91, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X35Y22", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y22": "SLICEM", + "SLICE_X51Y22": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y23": { + "bits": {}, + "grid_x": 91, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X35Y23", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y23": "SLICEM", + "SLICE_X51Y23": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y24": { + "bits": {}, + "grid_x": 91, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X35Y24", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y24": "SLICEM", + "SLICE_X51Y24": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y25": { + "bits": {}, + "grid_x": 91, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X35Y25", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y25": "SLICEM", + "SLICE_X51Y25": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y26": { + "bits": {}, + "grid_x": 91, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X35Y26", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y26": "SLICEM", + "SLICE_X51Y26": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y27": { + "bits": {}, + "grid_x": 91, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X35Y27", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y27": "SLICEM", + "SLICE_X51Y27": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y28": { + "bits": {}, + "grid_x": 91, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X35Y28", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y28": "SLICEM", + "SLICE_X51Y28": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y29": { + "bits": {}, + "grid_x": 91, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X35Y29", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y29": "SLICEM", + "SLICE_X51Y29": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y3": { + "bits": {}, + "grid_x": 91, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X35Y3", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y3": "SLICEM", + "SLICE_X51Y3": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y30": { + "bits": {}, + "grid_x": 91, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X35Y30", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y30": "SLICEM", + "SLICE_X51Y30": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y31": { + "bits": {}, + "grid_x": 91, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X35Y31", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y31": "SLICEM", + "SLICE_X51Y31": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y32": { + "bits": {}, + "grid_x": 91, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X35Y32", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y32": "SLICEM", + "SLICE_X51Y32": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y33": { + "bits": {}, + "grid_x": 91, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X35Y33", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y33": "SLICEM", + "SLICE_X51Y33": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y34": { + "bits": {}, + "grid_x": 91, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X35Y34", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y34": "SLICEM", + "SLICE_X51Y34": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y35": { + "bits": {}, + "grid_x": 91, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X35Y35", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y35": "SLICEM", + "SLICE_X51Y35": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y36": { + "bits": {}, + "grid_x": 91, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X35Y36", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y36": "SLICEM", + "SLICE_X51Y36": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y37": { + "bits": {}, + "grid_x": 91, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X35Y37", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y37": "SLICEM", + "SLICE_X51Y37": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y38": { + "bits": {}, + "grid_x": 91, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X35Y38", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y38": "SLICEM", + "SLICE_X51Y38": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y39": { + "bits": {}, + "grid_x": 91, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X35Y39", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y39": "SLICEM", + "SLICE_X51Y39": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y4": { + "bits": {}, + "grid_x": 91, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X35Y4", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y4": "SLICEM", + "SLICE_X51Y4": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y40": { + "bits": {}, + "grid_x": 91, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X35Y40", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y40": "SLICEM", + "SLICE_X51Y40": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y41": { + "bits": {}, + "grid_x": 91, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X35Y41", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y41": "SLICEM", + "SLICE_X51Y41": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y42": { + "bits": {}, + "grid_x": 91, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X35Y42", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y42": "SLICEM", + "SLICE_X51Y42": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y43": { + "bits": {}, + "grid_x": 91, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X35Y43", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y43": "SLICEM", + "SLICE_X51Y43": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y44": { + "bits": {}, + "grid_x": 91, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X35Y44", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y44": "SLICEM", + "SLICE_X51Y44": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y45": { + "bits": {}, + "grid_x": 91, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X35Y45", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y45": "SLICEM", + "SLICE_X51Y45": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y46": { + "bits": {}, + "grid_x": 91, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X35Y46", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y46": "SLICEM", + "SLICE_X51Y46": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y47": { + "bits": {}, + "grid_x": 91, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X35Y47", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y47": "SLICEM", + "SLICE_X51Y47": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y48": { + "bits": {}, + "grid_x": 91, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X35Y48", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y48": "SLICEM", + "SLICE_X51Y48": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y49": { + "bits": {}, + "grid_x": 91, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X35Y49", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y49": "SLICEM", + "SLICE_X51Y49": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y5": { + "bits": {}, + "grid_x": 91, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X35Y5", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y5": "SLICEM", + "SLICE_X51Y5": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y50": { + "bits": {}, + "grid_x": 91, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X35Y50", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y50": "SLICEM", + "SLICE_X51Y50": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y51": { + "bits": {}, + "grid_x": 91, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X35Y51", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y51": "SLICEM", + "SLICE_X51Y51": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y52": { + "bits": {}, + "grid_x": 91, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X35Y52", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y52": "SLICEM", + "SLICE_X51Y52": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y53": { + "bits": {}, + "grid_x": 91, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X35Y53", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y53": "SLICEM", + "SLICE_X51Y53": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y54": { + "bits": {}, + "grid_x": 91, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X35Y54", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y54": "SLICEM", + "SLICE_X51Y54": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y55": { + "bits": {}, + "grid_x": 91, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X35Y55", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y55": "SLICEM", + "SLICE_X51Y55": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y56": { + "bits": {}, + "grid_x": 91, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X35Y56", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y56": "SLICEM", + "SLICE_X51Y56": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y57": { + "bits": {}, + "grid_x": 91, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X35Y57", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y57": "SLICEM", + "SLICE_X51Y57": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y58": { + "bits": {}, + "grid_x": 91, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X35Y58", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y58": "SLICEM", + "SLICE_X51Y58": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y59": { + "bits": {}, + "grid_x": 91, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X35Y59", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y59": "SLICEM", + "SLICE_X51Y59": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y6": { + "bits": {}, + "grid_x": 91, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X35Y6", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y6": "SLICEM", + "SLICE_X51Y6": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y60": { + "bits": {}, + "grid_x": 91, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X35Y60", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y60": "SLICEM", + "SLICE_X51Y60": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y61": { + "bits": {}, + "grid_x": 91, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X35Y61", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y61": "SLICEM", + "SLICE_X51Y61": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y62": { + "bits": {}, + "grid_x": 91, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X35Y62", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y62": "SLICEM", + "SLICE_X51Y62": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y63": { + "bits": {}, + "grid_x": 91, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X35Y63", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y63": "SLICEM", + "SLICE_X51Y63": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y64": { + "bits": {}, + "grid_x": 91, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X35Y64", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y64": "SLICEM", + "SLICE_X51Y64": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y65": { + "bits": {}, + "grid_x": 91, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X35Y65", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y65": "SLICEM", + "SLICE_X51Y65": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y66": { + "bits": {}, + "grid_x": 91, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X35Y66", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y66": "SLICEM", + "SLICE_X51Y66": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y67": { + "bits": {}, + "grid_x": 91, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X35Y67", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y67": "SLICEM", + "SLICE_X51Y67": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y68": { + "bits": {}, + "grid_x": 91, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X35Y68", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y68": "SLICEM", + "SLICE_X51Y68": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y69": { + "bits": {}, + "grid_x": 91, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X35Y69", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y69": "SLICEM", + "SLICE_X51Y69": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y7": { + "bits": {}, + "grid_x": 91, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X35Y7", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y7": "SLICEM", + "SLICE_X51Y7": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y70": { + "bits": {}, + "grid_x": 91, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X35Y70", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y70": "SLICEM", + "SLICE_X51Y70": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y71": { + "bits": {}, + "grid_x": 91, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X35Y71", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y71": "SLICEM", + "SLICE_X51Y71": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y72": { + "bits": {}, + "grid_x": 91, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X35Y72", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y72": "SLICEM", + "SLICE_X51Y72": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y73": { + "bits": {}, + "grid_x": 91, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X35Y73", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y73": "SLICEM", + "SLICE_X51Y73": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y74": { + "bits": {}, + "grid_x": 91, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X35Y74", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y74": "SLICEM", + "SLICE_X51Y74": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y75": { + "bits": {}, + "grid_x": 91, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X35Y75", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y75": "SLICEM", + "SLICE_X51Y75": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y76": { + "bits": {}, + "grid_x": 91, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X35Y76", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y76": "SLICEM", + "SLICE_X51Y76": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y77": { + "bits": {}, + "grid_x": 91, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X35Y77", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y77": "SLICEM", + "SLICE_X51Y77": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y78": { + "bits": {}, + "grid_x": 91, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X35Y78", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y78": "SLICEM", + "SLICE_X51Y78": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y79": { + "bits": {}, + "grid_x": 91, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X35Y79", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y79": "SLICEM", + "SLICE_X51Y79": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y8": { + "bits": {}, + "grid_x": 91, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X35Y8", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y8": "SLICEM", + "SLICE_X51Y8": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y80": { + "bits": {}, + "grid_x": 91, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X35Y80", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y80": "SLICEM", + "SLICE_X51Y80": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y81": { + "bits": {}, + "grid_x": 91, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X35Y81", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y81": "SLICEM", + "SLICE_X51Y81": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y82": { + "bits": {}, + "grid_x": 91, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X35Y82", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y82": "SLICEM", + "SLICE_X51Y82": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y83": { + "bits": {}, + "grid_x": 91, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X35Y83", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y83": "SLICEM", + "SLICE_X51Y83": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y84": { + "bits": {}, + "grid_x": 91, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X35Y84", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y84": "SLICEM", + "SLICE_X51Y84": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y85": { + "bits": {}, + "grid_x": 91, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X35Y85", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y85": "SLICEM", + "SLICE_X51Y85": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y86": { + "bits": {}, + "grid_x": 91, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X35Y86", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y86": "SLICEM", + "SLICE_X51Y86": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y87": { + "bits": {}, + "grid_x": 91, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X35Y87", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y87": "SLICEM", + "SLICE_X51Y87": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y88": { + "bits": {}, + "grid_x": 91, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X35Y88", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y88": "SLICEM", + "SLICE_X51Y88": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y89": { + "bits": {}, + "grid_x": 91, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X35Y89", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y89": "SLICEM", + "SLICE_X51Y89": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y9": { + "bits": {}, + "grid_x": 91, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X35Y9", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y9": "SLICEM", + "SLICE_X51Y9": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y90": { + "bits": {}, + "grid_x": 91, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X35Y90", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y90": "SLICEM", + "SLICE_X51Y90": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y91": { + "bits": {}, + "grid_x": 91, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X35Y91", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y91": "SLICEM", + "SLICE_X51Y91": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y92": { + "bits": {}, + "grid_x": 91, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X35Y92", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y92": "SLICEM", + "SLICE_X51Y92": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y93": { + "bits": {}, + "grid_x": 91, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X35Y93", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y93": "SLICEM", + "SLICE_X51Y93": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y94": { + "bits": {}, + "grid_x": 91, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X35Y94", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y94": "SLICEM", + "SLICE_X51Y94": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y95": { + "bits": {}, + "grid_x": 91, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X35Y95", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y95": "SLICEM", + "SLICE_X51Y95": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y96": { + "bits": {}, + "grid_x": 91, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X35Y96", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y96": "SLICEM", + "SLICE_X51Y96": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y97": { + "bits": {}, + "grid_x": 91, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X35Y97", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y97": "SLICEM", + "SLICE_X51Y97": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y98": { + "bits": {}, + "grid_x": 91, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X35Y98", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y98": "SLICEM", + "SLICE_X51Y98": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X35Y99": { + "bits": {}, + "grid_x": 91, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X35Y99", + "segment_type": "clblm_r", + "sites": { + "SLICE_X50Y99": "SLICEM", + "SLICE_X51Y99": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y0": { + "bits": {}, + "grid_x": 102, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X39Y0", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y0": "SLICEM", + "SLICE_X57Y0": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y1": { + "bits": {}, + "grid_x": 102, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X39Y1", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y1": "SLICEM", + "SLICE_X57Y1": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y10": { + "bits": {}, + "grid_x": 102, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X39Y10", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y10": "SLICEM", + "SLICE_X57Y10": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y11": { + "bits": {}, + "grid_x": 102, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X39Y11", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y11": "SLICEM", + "SLICE_X57Y11": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y12": { + "bits": {}, + "grid_x": 102, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X39Y12", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y12": "SLICEM", + "SLICE_X57Y12": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y13": { + "bits": {}, + "grid_x": 102, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X39Y13", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y13": "SLICEM", + "SLICE_X57Y13": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y14": { + "bits": {}, + "grid_x": 102, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X39Y14", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y14": "SLICEM", + "SLICE_X57Y14": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y15": { + "bits": {}, + "grid_x": 102, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X39Y15", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y15": "SLICEM", + "SLICE_X57Y15": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y16": { + "bits": {}, + "grid_x": 102, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X39Y16", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y16": "SLICEM", + "SLICE_X57Y16": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y17": { + "bits": {}, + "grid_x": 102, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X39Y17", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y17": "SLICEM", + "SLICE_X57Y17": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y18": { + "bits": {}, + "grid_x": 102, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X39Y18", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y18": "SLICEM", + "SLICE_X57Y18": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y19": { + "bits": {}, + "grid_x": 102, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X39Y19", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y19": "SLICEM", + "SLICE_X57Y19": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y2": { + "bits": {}, + "grid_x": 102, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X39Y2", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y2": "SLICEM", + "SLICE_X57Y2": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y20": { + "bits": {}, + "grid_x": 102, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X39Y20", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y20": "SLICEM", + "SLICE_X57Y20": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y21": { + "bits": {}, + "grid_x": 102, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X39Y21", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y21": "SLICEM", + "SLICE_X57Y21": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y22": { + "bits": {}, + "grid_x": 102, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X39Y22", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y22": "SLICEM", + "SLICE_X57Y22": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y23": { + "bits": {}, + "grid_x": 102, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X39Y23", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y23": "SLICEM", + "SLICE_X57Y23": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y24": { + "bits": {}, + "grid_x": 102, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X39Y24", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y24": "SLICEM", + "SLICE_X57Y24": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y25": { + "bits": {}, + "grid_x": 102, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X39Y25", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y25": "SLICEM", + "SLICE_X57Y25": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y26": { + "bits": {}, + "grid_x": 102, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X39Y26", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y26": "SLICEM", + "SLICE_X57Y26": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y27": { + "bits": {}, + "grid_x": 102, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X39Y27", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y27": "SLICEM", + "SLICE_X57Y27": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y28": { + "bits": {}, + "grid_x": 102, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X39Y28", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y28": "SLICEM", + "SLICE_X57Y28": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y29": { + "bits": {}, + "grid_x": 102, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X39Y29", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y29": "SLICEM", + "SLICE_X57Y29": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y3": { + "bits": {}, + "grid_x": 102, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X39Y3", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y3": "SLICEM", + "SLICE_X57Y3": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y30": { + "bits": {}, + "grid_x": 102, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X39Y30", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y30": "SLICEM", + "SLICE_X57Y30": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y31": { + "bits": {}, + "grid_x": 102, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X39Y31", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y31": "SLICEM", + "SLICE_X57Y31": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y32": { + "bits": {}, + "grid_x": 102, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X39Y32", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y32": "SLICEM", + "SLICE_X57Y32": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y33": { + "bits": {}, + "grid_x": 102, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X39Y33", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y33": "SLICEM", + "SLICE_X57Y33": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y34": { + "bits": {}, + "grid_x": 102, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X39Y34", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y34": "SLICEM", + "SLICE_X57Y34": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y35": { + "bits": {}, + "grid_x": 102, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X39Y35", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y35": "SLICEM", + "SLICE_X57Y35": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y36": { + "bits": {}, + "grid_x": 102, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X39Y36", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y36": "SLICEM", + "SLICE_X57Y36": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y37": { + "bits": {}, + "grid_x": 102, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X39Y37", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y37": "SLICEM", + "SLICE_X57Y37": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y38": { + "bits": {}, + "grid_x": 102, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X39Y38", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y38": "SLICEM", + "SLICE_X57Y38": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y39": { + "bits": {}, + "grid_x": 102, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X39Y39", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y39": "SLICEM", + "SLICE_X57Y39": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y4": { + "bits": {}, + "grid_x": 102, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X39Y4", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y4": "SLICEM", + "SLICE_X57Y4": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y40": { + "bits": {}, + "grid_x": 102, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X39Y40", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y40": "SLICEM", + "SLICE_X57Y40": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y41": { + "bits": {}, + "grid_x": 102, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X39Y41", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y41": "SLICEM", + "SLICE_X57Y41": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y42": { + "bits": {}, + "grid_x": 102, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X39Y42", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y42": "SLICEM", + "SLICE_X57Y42": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y43": { + "bits": {}, + "grid_x": 102, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X39Y43", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y43": "SLICEM", + "SLICE_X57Y43": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y44": { + "bits": {}, + "grid_x": 102, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X39Y44", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y44": "SLICEM", + "SLICE_X57Y44": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y45": { + "bits": {}, + "grid_x": 102, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X39Y45", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y45": "SLICEM", + "SLICE_X57Y45": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y46": { + "bits": {}, + "grid_x": 102, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X39Y46", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y46": "SLICEM", + "SLICE_X57Y46": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y47": { + "bits": {}, + "grid_x": 102, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X39Y47", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y47": "SLICEM", + "SLICE_X57Y47": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y48": { + "bits": {}, + "grid_x": 102, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X39Y48", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y48": "SLICEM", + "SLICE_X57Y48": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y49": { + "bits": {}, + "grid_x": 102, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X39Y49", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y49": "SLICEM", + "SLICE_X57Y49": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y5": { + "bits": {}, + "grid_x": 102, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X39Y5", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y5": "SLICEM", + "SLICE_X57Y5": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y50": { + "bits": {}, + "grid_x": 102, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X39Y50", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y50": "SLICEM", + "SLICE_X57Y50": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y51": { + "bits": {}, + "grid_x": 102, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X39Y51", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y51": "SLICEM", + "SLICE_X57Y51": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y52": { + "bits": {}, + "grid_x": 102, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X39Y52", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y52": "SLICEM", + "SLICE_X57Y52": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y53": { + "bits": {}, + "grid_x": 102, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X39Y53", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y53": "SLICEM", + "SLICE_X57Y53": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y54": { + "bits": {}, + "grid_x": 102, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X39Y54", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y54": "SLICEM", + "SLICE_X57Y54": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y55": { + "bits": {}, + "grid_x": 102, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X39Y55", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y55": "SLICEM", + "SLICE_X57Y55": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y56": { + "bits": {}, + "grid_x": 102, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X39Y56", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y56": "SLICEM", + "SLICE_X57Y56": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y57": { + "bits": {}, + "grid_x": 102, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X39Y57", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y57": "SLICEM", + "SLICE_X57Y57": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y58": { + "bits": {}, + "grid_x": 102, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X39Y58", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y58": "SLICEM", + "SLICE_X57Y58": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y59": { + "bits": {}, + "grid_x": 102, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X39Y59", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y59": "SLICEM", + "SLICE_X57Y59": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y6": { + "bits": {}, + "grid_x": 102, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X39Y6", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y6": "SLICEM", + "SLICE_X57Y6": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y60": { + "bits": {}, + "grid_x": 102, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X39Y60", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y60": "SLICEM", + "SLICE_X57Y60": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y61": { + "bits": {}, + "grid_x": 102, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X39Y61", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y61": "SLICEM", + "SLICE_X57Y61": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y62": { + "bits": {}, + "grid_x": 102, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X39Y62", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y62": "SLICEM", + "SLICE_X57Y62": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y63": { + "bits": {}, + "grid_x": 102, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X39Y63", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y63": "SLICEM", + "SLICE_X57Y63": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y64": { + "bits": {}, + "grid_x": 102, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X39Y64", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y64": "SLICEM", + "SLICE_X57Y64": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y65": { + "bits": {}, + "grid_x": 102, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X39Y65", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y65": "SLICEM", + "SLICE_X57Y65": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y66": { + "bits": {}, + "grid_x": 102, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X39Y66", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y66": "SLICEM", + "SLICE_X57Y66": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y67": { + "bits": {}, + "grid_x": 102, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X39Y67", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y67": "SLICEM", + "SLICE_X57Y67": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y68": { + "bits": {}, + "grid_x": 102, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X39Y68", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y68": "SLICEM", + "SLICE_X57Y68": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y69": { + "bits": {}, + "grid_x": 102, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X39Y69", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y69": "SLICEM", + "SLICE_X57Y69": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y7": { + "bits": {}, + "grid_x": 102, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X39Y7", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y7": "SLICEM", + "SLICE_X57Y7": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y70": { + "bits": {}, + "grid_x": 102, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X39Y70", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y70": "SLICEM", + "SLICE_X57Y70": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y71": { + "bits": {}, + "grid_x": 102, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X39Y71", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y71": "SLICEM", + "SLICE_X57Y71": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y72": { + "bits": {}, + "grid_x": 102, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X39Y72", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y72": "SLICEM", + "SLICE_X57Y72": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y73": { + "bits": {}, + "grid_x": 102, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X39Y73", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y73": "SLICEM", + "SLICE_X57Y73": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y74": { + "bits": {}, + "grid_x": 102, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X39Y74", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y74": "SLICEM", + "SLICE_X57Y74": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y75": { + "bits": {}, + "grid_x": 102, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X39Y75", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y75": "SLICEM", + "SLICE_X57Y75": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y76": { + "bits": {}, + "grid_x": 102, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X39Y76", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y76": "SLICEM", + "SLICE_X57Y76": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y77": { + "bits": {}, + "grid_x": 102, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X39Y77", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y77": "SLICEM", + "SLICE_X57Y77": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y78": { + "bits": {}, + "grid_x": 102, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X39Y78", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y78": "SLICEM", + "SLICE_X57Y78": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y79": { + "bits": {}, + "grid_x": 102, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X39Y79", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y79": "SLICEM", + "SLICE_X57Y79": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y8": { + "bits": {}, + "grid_x": 102, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X39Y8", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y8": "SLICEM", + "SLICE_X57Y8": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y80": { + "bits": {}, + "grid_x": 102, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X39Y80", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y80": "SLICEM", + "SLICE_X57Y80": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y81": { + "bits": {}, + "grid_x": 102, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X39Y81", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y81": "SLICEM", + "SLICE_X57Y81": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y82": { + "bits": {}, + "grid_x": 102, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X39Y82", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y82": "SLICEM", + "SLICE_X57Y82": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y83": { + "bits": {}, + "grid_x": 102, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X39Y83", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y83": "SLICEM", + "SLICE_X57Y83": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y84": { + "bits": {}, + "grid_x": 102, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X39Y84", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y84": "SLICEM", + "SLICE_X57Y84": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y85": { + "bits": {}, + "grid_x": 102, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X39Y85", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y85": "SLICEM", + "SLICE_X57Y85": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y86": { + "bits": {}, + "grid_x": 102, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X39Y86", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y86": "SLICEM", + "SLICE_X57Y86": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y87": { + "bits": {}, + "grid_x": 102, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X39Y87", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y87": "SLICEM", + "SLICE_X57Y87": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y88": { + "bits": {}, + "grid_x": 102, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X39Y88", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y88": "SLICEM", + "SLICE_X57Y88": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y89": { + "bits": {}, + "grid_x": 102, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X39Y89", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y89": "SLICEM", + "SLICE_X57Y89": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y9": { + "bits": {}, + "grid_x": 102, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X39Y9", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y9": "SLICEM", + "SLICE_X57Y9": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y90": { + "bits": {}, + "grid_x": 102, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X39Y90", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y90": "SLICEM", + "SLICE_X57Y90": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y91": { + "bits": {}, + "grid_x": 102, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X39Y91", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y91": "SLICEM", + "SLICE_X57Y91": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y92": { + "bits": {}, + "grid_x": 102, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X39Y92", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y92": "SLICEM", + "SLICE_X57Y92": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y93": { + "bits": {}, + "grid_x": 102, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X39Y93", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y93": "SLICEM", + "SLICE_X57Y93": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y94": { + "bits": {}, + "grid_x": 102, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X39Y94", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y94": "SLICEM", + "SLICE_X57Y94": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y95": { + "bits": {}, + "grid_x": 102, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X39Y95", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y95": "SLICEM", + "SLICE_X57Y95": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y96": { + "bits": {}, + "grid_x": 102, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X39Y96", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y96": "SLICEM", + "SLICE_X57Y96": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y97": { + "bits": {}, + "grid_x": 102, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X39Y97", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y97": "SLICEM", + "SLICE_X57Y97": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y98": { + "bits": {}, + "grid_x": 102, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X39Y98", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y98": "SLICEM", + "SLICE_X57Y98": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X39Y99": { + "bits": {}, + "grid_x": 102, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X39Y99", + "segment_type": "clblm_r", + "sites": { + "SLICE_X56Y99": "SLICEM", + "SLICE_X57Y99": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y0": { + "bits": {}, + "grid_x": 13, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X3Y0", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y0": "SLICEM", + "SLICE_X3Y0": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y1": { + "bits": {}, + "grid_x": 13, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X3Y1", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y1": "SLICEM", + "SLICE_X3Y1": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y10": { + "bits": {}, + "grid_x": 13, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X3Y10", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y10": "SLICEM", + "SLICE_X3Y10": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y100": { + "bits": {}, + "grid_x": 13, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X3Y100", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y100": "SLICEM", + "SLICE_X3Y100": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y101": { + "bits": {}, + "grid_x": 13, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X3Y101", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y101": "SLICEM", + "SLICE_X3Y101": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y102": { + "bits": {}, + "grid_x": 13, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X3Y102", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y102": "SLICEM", + "SLICE_X3Y102": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y103": { + "bits": {}, + "grid_x": 13, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X3Y103", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y103": "SLICEM", + "SLICE_X3Y103": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y104": { + "bits": {}, + "grid_x": 13, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X3Y104", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y104": "SLICEM", + "SLICE_X3Y104": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y105": { + "bits": {}, + "grid_x": 13, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X3Y105", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y105": "SLICEM", + "SLICE_X3Y105": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y106": { + "bits": {}, + "grid_x": 13, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X3Y106", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y106": "SLICEM", + "SLICE_X3Y106": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y107": { + "bits": {}, + "grid_x": 13, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X3Y107", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y107": "SLICEM", + "SLICE_X3Y107": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y108": { + "bits": {}, + "grid_x": 13, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X3Y108", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y108": "SLICEM", + "SLICE_X3Y108": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y109": { + "bits": {}, + "grid_x": 13, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X3Y109", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y109": "SLICEM", + "SLICE_X3Y109": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y11": { + "bits": {}, + "grid_x": 13, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X3Y11", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y11": "SLICEM", + "SLICE_X3Y11": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y110": { + "bits": {}, + "grid_x": 13, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X3Y110", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y110": "SLICEM", + "SLICE_X3Y110": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y111": { + "bits": {}, + "grid_x": 13, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X3Y111", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y111": "SLICEM", + "SLICE_X3Y111": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y112": { + "bits": {}, + "grid_x": 13, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X3Y112", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y112": "SLICEM", + "SLICE_X3Y112": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y113": { + "bits": {}, + "grid_x": 13, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X3Y113", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y113": "SLICEM", + "SLICE_X3Y113": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y114": { + "bits": {}, + "grid_x": 13, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X3Y114", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y114": "SLICEM", + "SLICE_X3Y114": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y115": { + "bits": {}, + "grid_x": 13, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X3Y115", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y115": "SLICEM", + "SLICE_X3Y115": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y116": { + "bits": {}, + "grid_x": 13, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X3Y116", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y116": "SLICEM", + "SLICE_X3Y116": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y117": { + "bits": {}, + "grid_x": 13, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X3Y117", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y117": "SLICEM", + "SLICE_X3Y117": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y118": { + "bits": {}, + "grid_x": 13, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X3Y118", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y118": "SLICEM", + "SLICE_X3Y118": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y119": { + "bits": {}, + "grid_x": 13, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X3Y119", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y119": "SLICEM", + "SLICE_X3Y119": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y12": { + "bits": {}, + "grid_x": 13, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X3Y12", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y12": "SLICEM", + "SLICE_X3Y12": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y120": { + "bits": {}, + "grid_x": 13, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X3Y120", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y120": "SLICEM", + "SLICE_X3Y120": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y121": { + "bits": {}, + "grid_x": 13, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X3Y121", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y121": "SLICEM", + "SLICE_X3Y121": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y122": { + "bits": {}, + "grid_x": 13, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X3Y122", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y122": "SLICEM", + "SLICE_X3Y122": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y123": { + "bits": {}, + "grid_x": 13, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X3Y123", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y123": "SLICEM", + "SLICE_X3Y123": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y124": { + "bits": {}, + "grid_x": 13, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X3Y124", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y124": "SLICEM", + "SLICE_X3Y124": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y125": { + "bits": {}, + "grid_x": 13, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X3Y125", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y125": "SLICEM", + "SLICE_X3Y125": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y126": { + "bits": {}, + "grid_x": 13, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X3Y126", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y126": "SLICEM", + "SLICE_X3Y126": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y127": { + "bits": {}, + "grid_x": 13, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X3Y127", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y127": "SLICEM", + "SLICE_X3Y127": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y128": { + "bits": {}, + "grid_x": 13, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X3Y128", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y128": "SLICEM", + "SLICE_X3Y128": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y129": { + "bits": {}, + "grid_x": 13, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X3Y129", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y129": "SLICEM", + "SLICE_X3Y129": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y13": { + "bits": {}, + "grid_x": 13, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X3Y13", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y13": "SLICEM", + "SLICE_X3Y13": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y130": { + "bits": {}, + "grid_x": 13, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X3Y130", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y130": "SLICEM", + "SLICE_X3Y130": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y131": { + "bits": {}, + "grid_x": 13, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X3Y131", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y131": "SLICEM", + "SLICE_X3Y131": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y132": { + "bits": {}, + "grid_x": 13, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X3Y132", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y132": "SLICEM", + "SLICE_X3Y132": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y133": { + "bits": {}, + "grid_x": 13, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X3Y133", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y133": "SLICEM", + "SLICE_X3Y133": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y134": { + "bits": {}, + "grid_x": 13, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X3Y134", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y134": "SLICEM", + "SLICE_X3Y134": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y135": { + "bits": {}, + "grid_x": 13, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X3Y135", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y135": "SLICEM", + "SLICE_X3Y135": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y136": { + "bits": {}, + "grid_x": 13, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X3Y136", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y136": "SLICEM", + "SLICE_X3Y136": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y137": { + "bits": {}, + "grid_x": 13, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X3Y137", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y137": "SLICEM", + "SLICE_X3Y137": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y138": { + "bits": {}, + "grid_x": 13, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X3Y138", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y138": "SLICEM", + "SLICE_X3Y138": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y139": { + "bits": {}, + "grid_x": 13, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X3Y139", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y139": "SLICEM", + "SLICE_X3Y139": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y14": { + "bits": {}, + "grid_x": 13, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X3Y14", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y14": "SLICEM", + "SLICE_X3Y14": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y140": { + "bits": {}, + "grid_x": 13, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X3Y140", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y140": "SLICEM", + "SLICE_X3Y140": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y141": { + "bits": {}, + "grid_x": 13, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X3Y141", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y141": "SLICEM", + "SLICE_X3Y141": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y142": { + "bits": {}, + "grid_x": 13, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X3Y142", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y142": "SLICEM", + "SLICE_X3Y142": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y143": { + "bits": {}, + "grid_x": 13, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X3Y143", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y143": "SLICEM", + "SLICE_X3Y143": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y144": { + "bits": {}, + "grid_x": 13, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X3Y144", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y144": "SLICEM", + "SLICE_X3Y144": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y145": { + "bits": {}, + "grid_x": 13, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X3Y145", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y145": "SLICEM", + "SLICE_X3Y145": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y146": { + "bits": {}, + "grid_x": 13, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X3Y146", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y146": "SLICEM", + "SLICE_X3Y146": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y147": { + "bits": {}, + "grid_x": 13, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X3Y147", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y147": "SLICEM", + "SLICE_X3Y147": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y148": { + "bits": {}, + "grid_x": 13, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X3Y148", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y148": "SLICEM", + "SLICE_X3Y148": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y149": { + "bits": {}, + "grid_x": 13, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X3Y149", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y149": "SLICEM", + "SLICE_X3Y149": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y15": { + "bits": {}, + "grid_x": 13, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X3Y15", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y15": "SLICEM", + "SLICE_X3Y15": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y150": { + "bits": {}, + "grid_x": 13, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X3Y150", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y150": "SLICEM", + "SLICE_X3Y150": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y151": { + "bits": {}, + "grid_x": 13, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X3Y151", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y151": "SLICEM", + "SLICE_X3Y151": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y152": { + "bits": {}, + "grid_x": 13, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X3Y152", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y152": "SLICEM", + "SLICE_X3Y152": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y153": { + "bits": {}, + "grid_x": 13, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X3Y153", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y153": "SLICEM", + "SLICE_X3Y153": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y154": { + "bits": {}, + "grid_x": 13, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X3Y154", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y154": "SLICEM", + "SLICE_X3Y154": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y155": { + "bits": {}, + "grid_x": 13, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X3Y155", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y155": "SLICEM", + "SLICE_X3Y155": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y156": { + "bits": {}, + "grid_x": 13, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X3Y156", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y156": "SLICEM", + "SLICE_X3Y156": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y157": { + "bits": {}, + "grid_x": 13, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X3Y157", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y157": "SLICEM", + "SLICE_X3Y157": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y158": { + "bits": {}, + "grid_x": 13, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X3Y158", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y158": "SLICEM", + "SLICE_X3Y158": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y159": { + "bits": {}, + "grid_x": 13, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X3Y159", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y159": "SLICEM", + "SLICE_X3Y159": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y16": { + "bits": {}, + "grid_x": 13, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X3Y16", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y16": "SLICEM", + "SLICE_X3Y16": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y160": { + "bits": {}, + "grid_x": 13, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X3Y160", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y160": "SLICEM", + "SLICE_X3Y160": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y161": { + "bits": {}, + "grid_x": 13, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X3Y161", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y161": "SLICEM", + "SLICE_X3Y161": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y162": { + "bits": {}, + "grid_x": 13, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X3Y162", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y162": "SLICEM", + "SLICE_X3Y162": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y163": { + "bits": {}, + "grid_x": 13, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X3Y163", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y163": "SLICEM", + "SLICE_X3Y163": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y164": { + "bits": {}, + "grid_x": 13, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X3Y164", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y164": "SLICEM", + "SLICE_X3Y164": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y165": { + "bits": {}, + "grid_x": 13, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X3Y165", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y165": "SLICEM", + "SLICE_X3Y165": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y166": { + "bits": {}, + "grid_x": 13, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X3Y166", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y166": "SLICEM", + "SLICE_X3Y166": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y167": { + "bits": {}, + "grid_x": 13, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X3Y167", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y167": "SLICEM", + "SLICE_X3Y167": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y168": { + "bits": {}, + "grid_x": 13, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X3Y168", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y168": "SLICEM", + "SLICE_X3Y168": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y169": { + "bits": {}, + "grid_x": 13, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X3Y169", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y169": "SLICEM", + "SLICE_X3Y169": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y17": { + "bits": {}, + "grid_x": 13, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X3Y17", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y17": "SLICEM", + "SLICE_X3Y17": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y170": { + "bits": {}, + "grid_x": 13, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X3Y170", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y170": "SLICEM", + "SLICE_X3Y170": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y171": { + "bits": {}, + "grid_x": 13, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X3Y171", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y171": "SLICEM", + "SLICE_X3Y171": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y172": { + "bits": {}, + "grid_x": 13, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X3Y172", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y172": "SLICEM", + "SLICE_X3Y172": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y173": { + "bits": {}, + "grid_x": 13, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X3Y173", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y173": "SLICEM", + "SLICE_X3Y173": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y174": { + "bits": {}, + "grid_x": 13, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X3Y174", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y174": "SLICEM", + "SLICE_X3Y174": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y175": { + "bits": {}, + "grid_x": 13, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X3Y175", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y175": "SLICEM", + "SLICE_X3Y175": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y176": { + "bits": {}, + "grid_x": 13, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X3Y176", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y176": "SLICEM", + "SLICE_X3Y176": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y177": { + "bits": {}, + "grid_x": 13, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X3Y177", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y177": "SLICEM", + "SLICE_X3Y177": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y178": { + "bits": {}, + "grid_x": 13, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X3Y178", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y178": "SLICEM", + "SLICE_X3Y178": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y179": { + "bits": {}, + "grid_x": 13, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X3Y179", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y179": "SLICEM", + "SLICE_X3Y179": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y18": { + "bits": {}, + "grid_x": 13, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X3Y18", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y18": "SLICEM", + "SLICE_X3Y18": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y180": { + "bits": {}, + "grid_x": 13, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X3Y180", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y180": "SLICEM", + "SLICE_X3Y180": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y181": { + "bits": {}, + "grid_x": 13, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X3Y181", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y181": "SLICEM", + "SLICE_X3Y181": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y182": { + "bits": {}, + "grid_x": 13, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X3Y182", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y182": "SLICEM", + "SLICE_X3Y182": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y183": { + "bits": {}, + "grid_x": 13, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X3Y183", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y183": "SLICEM", + "SLICE_X3Y183": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y184": { + "bits": {}, + "grid_x": 13, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X3Y184", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y184": "SLICEM", + "SLICE_X3Y184": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y185": { + "bits": {}, + "grid_x": 13, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X3Y185", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y185": "SLICEM", + "SLICE_X3Y185": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y186": { + "bits": {}, + "grid_x": 13, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X3Y186", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y186": "SLICEM", + "SLICE_X3Y186": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y187": { + "bits": {}, + "grid_x": 13, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X3Y187", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y187": "SLICEM", + "SLICE_X3Y187": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y188": { + "bits": {}, + "grid_x": 13, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X3Y188", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y188": "SLICEM", + "SLICE_X3Y188": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y189": { + "bits": {}, + "grid_x": 13, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X3Y189", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y189": "SLICEM", + "SLICE_X3Y189": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y19": { + "bits": {}, + "grid_x": 13, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X3Y19", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y19": "SLICEM", + "SLICE_X3Y19": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y190": { + "bits": {}, + "grid_x": 13, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X3Y190", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y190": "SLICEM", + "SLICE_X3Y190": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y191": { + "bits": {}, + "grid_x": 13, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X3Y191", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y191": "SLICEM", + "SLICE_X3Y191": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y192": { + "bits": {}, + "grid_x": 13, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X3Y192", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y192": "SLICEM", + "SLICE_X3Y192": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y193": { + "bits": {}, + "grid_x": 13, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X3Y193", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y193": "SLICEM", + "SLICE_X3Y193": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y194": { + "bits": {}, + "grid_x": 13, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X3Y194", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y194": "SLICEM", + "SLICE_X3Y194": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y195": { + "bits": {}, + "grid_x": 13, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X3Y195", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y195": "SLICEM", + "SLICE_X3Y195": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y196": { + "bits": {}, + "grid_x": 13, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X3Y196", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y196": "SLICEM", + "SLICE_X3Y196": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y197": { + "bits": {}, + "grid_x": 13, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X3Y197", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y197": "SLICEM", + "SLICE_X3Y197": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y198": { + "bits": {}, + "grid_x": 13, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X3Y198", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y198": "SLICEM", + "SLICE_X3Y198": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y199": { + "bits": {}, + "grid_x": 13, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X3Y199", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y199": "SLICEM", + "SLICE_X3Y199": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y2": { + "bits": {}, + "grid_x": 13, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X3Y2", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y2": "SLICEM", + "SLICE_X3Y2": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y20": { + "bits": {}, + "grid_x": 13, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X3Y20", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y20": "SLICEM", + "SLICE_X3Y20": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y21": { + "bits": {}, + "grid_x": 13, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X3Y21", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y21": "SLICEM", + "SLICE_X3Y21": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y22": { + "bits": {}, + "grid_x": 13, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X3Y22", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y22": "SLICEM", + "SLICE_X3Y22": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y23": { + "bits": {}, + "grid_x": 13, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X3Y23", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y23": "SLICEM", + "SLICE_X3Y23": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y24": { + "bits": {}, + "grid_x": 13, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X3Y24", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y24": "SLICEM", + "SLICE_X3Y24": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y25": { + "bits": {}, + "grid_x": 13, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X3Y25", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y25": "SLICEM", + "SLICE_X3Y25": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y26": { + "bits": {}, + "grid_x": 13, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X3Y26", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y26": "SLICEM", + "SLICE_X3Y26": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y27": { + "bits": {}, + "grid_x": 13, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X3Y27", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y27": "SLICEM", + "SLICE_X3Y27": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y28": { + "bits": {}, + "grid_x": 13, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X3Y28", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y28": "SLICEM", + "SLICE_X3Y28": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y29": { + "bits": {}, + "grid_x": 13, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X3Y29", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y29": "SLICEM", + "SLICE_X3Y29": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y3": { + "bits": {}, + "grid_x": 13, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X3Y3", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y3": "SLICEM", + "SLICE_X3Y3": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y30": { + "bits": {}, + "grid_x": 13, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X3Y30", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y30": "SLICEM", + "SLICE_X3Y30": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y31": { + "bits": {}, + "grid_x": 13, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X3Y31", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y31": "SLICEM", + "SLICE_X3Y31": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y32": { + "bits": {}, + "grid_x": 13, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X3Y32", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y32": "SLICEM", + "SLICE_X3Y32": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y33": { + "bits": {}, + "grid_x": 13, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X3Y33", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y33": "SLICEM", + "SLICE_X3Y33": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y34": { + "bits": {}, + "grid_x": 13, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X3Y34", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y34": "SLICEM", + "SLICE_X3Y34": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y35": { + "bits": {}, + "grid_x": 13, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X3Y35", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y35": "SLICEM", + "SLICE_X3Y35": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y36": { + "bits": {}, + "grid_x": 13, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X3Y36", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y36": "SLICEM", + "SLICE_X3Y36": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y37": { + "bits": {}, + "grid_x": 13, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X3Y37", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y37": "SLICEM", + "SLICE_X3Y37": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y38": { + "bits": {}, + "grid_x": 13, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X3Y38", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y38": "SLICEM", + "SLICE_X3Y38": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y39": { + "bits": {}, + "grid_x": 13, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X3Y39", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y39": "SLICEM", + "SLICE_X3Y39": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y4": { + "bits": {}, + "grid_x": 13, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X3Y4", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y4": "SLICEM", + "SLICE_X3Y4": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y40": { + "bits": {}, + "grid_x": 13, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X3Y40", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y40": "SLICEM", + "SLICE_X3Y40": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y41": { + "bits": {}, + "grid_x": 13, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X3Y41", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y41": "SLICEM", + "SLICE_X3Y41": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y42": { + "bits": {}, + "grid_x": 13, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X3Y42", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y42": "SLICEM", + "SLICE_X3Y42": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y43": { + "bits": {}, + "grid_x": 13, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X3Y43", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y43": "SLICEM", + "SLICE_X3Y43": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y44": { + "bits": {}, + "grid_x": 13, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X3Y44", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y44": "SLICEM", + "SLICE_X3Y44": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y45": { + "bits": {}, + "grid_x": 13, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X3Y45", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y45": "SLICEM", + "SLICE_X3Y45": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y46": { + "bits": {}, + "grid_x": 13, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X3Y46", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y46": "SLICEM", + "SLICE_X3Y46": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y47": { + "bits": {}, + "grid_x": 13, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X3Y47", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y47": "SLICEM", + "SLICE_X3Y47": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y48": { + "bits": {}, + "grid_x": 13, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X3Y48", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y48": "SLICEM", + "SLICE_X3Y48": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y49": { + "bits": {}, + "grid_x": 13, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X3Y49", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y49": "SLICEM", + "SLICE_X3Y49": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y5": { + "bits": {}, + "grid_x": 13, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X3Y5", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y5": "SLICEM", + "SLICE_X3Y5": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X3Y50", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y50": "SLICEM", + "SLICE_X3Y50": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X3Y51", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y51": "SLICEM", + "SLICE_X3Y51": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X3Y52", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y52": "SLICEM", + "SLICE_X3Y52": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X3Y53", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y53": "SLICEM", + "SLICE_X3Y53": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X3Y54", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y54": "SLICEM", + "SLICE_X3Y54": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X3Y55", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y55": "SLICEM", + "SLICE_X3Y55": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X3Y56", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y56": "SLICEM", + "SLICE_X3Y56": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X3Y57", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y57": "SLICEM", + "SLICE_X3Y57": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X3Y58", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y58": "SLICEM", + "SLICE_X3Y58": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X3Y59", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y59": "SLICEM", + "SLICE_X3Y59": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y6": { + "bits": {}, + "grid_x": 13, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X3Y6", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y6": "SLICEM", + "SLICE_X3Y6": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X3Y60", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y60": "SLICEM", + "SLICE_X3Y60": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X3Y61", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y61": "SLICEM", + "SLICE_X3Y61": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X3Y62", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y62": "SLICEM", + "SLICE_X3Y62": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X3Y63", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y63": "SLICEM", + "SLICE_X3Y63": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X3Y64", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y64": "SLICEM", + "SLICE_X3Y64": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X3Y65", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y65": "SLICEM", + "SLICE_X3Y65": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X3Y66", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y66": "SLICEM", + "SLICE_X3Y66": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X3Y67", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y67": "SLICEM", + "SLICE_X3Y67": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X3Y68", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y68": "SLICEM", + "SLICE_X3Y68": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X3Y69", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y69": "SLICEM", + "SLICE_X3Y69": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y7": { + "bits": {}, + "grid_x": 13, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X3Y7", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y7": "SLICEM", + "SLICE_X3Y7": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X3Y70", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y70": "SLICEM", + "SLICE_X3Y70": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X3Y71", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y71": "SLICEM", + "SLICE_X3Y71": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X3Y72", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y72": "SLICEM", + "SLICE_X3Y72": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X3Y73", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y73": "SLICEM", + "SLICE_X3Y73": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X3Y74", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y74": "SLICEM", + "SLICE_X3Y74": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X3Y75", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y75": "SLICEM", + "SLICE_X3Y75": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X3Y76", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y76": "SLICEM", + "SLICE_X3Y76": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X3Y77", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y77": "SLICEM", + "SLICE_X3Y77": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X3Y78", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y78": "SLICEM", + "SLICE_X3Y78": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X3Y79", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y79": "SLICEM", + "SLICE_X3Y79": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y8": { + "bits": {}, + "grid_x": 13, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X3Y8", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y8": "SLICEM", + "SLICE_X3Y8": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X3Y80", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y80": "SLICEM", + "SLICE_X3Y80": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X3Y81", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y81": "SLICEM", + "SLICE_X3Y81": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X3Y82", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y82": "SLICEM", + "SLICE_X3Y82": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X3Y83", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y83": "SLICEM", + "SLICE_X3Y83": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X3Y84", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y84": "SLICEM", + "SLICE_X3Y84": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X3Y85", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y85": "SLICEM", + "SLICE_X3Y85": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X3Y86", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y86": "SLICEM", + "SLICE_X3Y86": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X3Y87", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y87": "SLICEM", + "SLICE_X3Y87": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X3Y88", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y88": "SLICEM", + "SLICE_X3Y88": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X3Y89", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y89": "SLICEM", + "SLICE_X3Y89": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y9": { + "bits": {}, + "grid_x": 13, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X3Y9", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y9": "SLICEM", + "SLICE_X3Y9": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X3Y90", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y90": "SLICEM", + "SLICE_X3Y90": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X3Y91", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y91": "SLICEM", + "SLICE_X3Y91": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X3Y92", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y92": "SLICEM", + "SLICE_X3Y92": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X3Y93", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y93": "SLICEM", + "SLICE_X3Y93": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X3Y94", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y94": "SLICEM", + "SLICE_X3Y94": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X3Y95", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y95": "SLICEM", + "SLICE_X3Y95": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X3Y96", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y96": "SLICEM", + "SLICE_X3Y96": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X3Y97", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y97": "SLICEM", + "SLICE_X3Y97": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X3Y98", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y98": "SLICEM", + "SLICE_X3Y98": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X3Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 36, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 13, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X3Y99", + "segment_type": "clblm_r", + "sites": { + "SLICE_X2Y99": "SLICEM", + "SLICE_X3Y99": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y0": { + "bits": {}, + "grid_x": 106, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X41Y0", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y0": "SLICEM", + "SLICE_X61Y0": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y1": { + "bits": {}, + "grid_x": 106, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X41Y1", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y1": "SLICEM", + "SLICE_X61Y1": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y10": { + "bits": {}, + "grid_x": 106, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X41Y10", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y10": "SLICEM", + "SLICE_X61Y10": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y11": { + "bits": {}, + "grid_x": 106, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X41Y11", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y11": "SLICEM", + "SLICE_X61Y11": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y12": { + "bits": {}, + "grid_x": 106, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X41Y12", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y12": "SLICEM", + "SLICE_X61Y12": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y13": { + "bits": {}, + "grid_x": 106, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X41Y13", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y13": "SLICEM", + "SLICE_X61Y13": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y14": { + "bits": {}, + "grid_x": 106, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X41Y14", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y14": "SLICEM", + "SLICE_X61Y14": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y15": { + "bits": {}, + "grid_x": 106, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X41Y15", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y15": "SLICEM", + "SLICE_X61Y15": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y16": { + "bits": {}, + "grid_x": 106, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X41Y16", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y16": "SLICEM", + "SLICE_X61Y16": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y17": { + "bits": {}, + "grid_x": 106, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X41Y17", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y17": "SLICEM", + "SLICE_X61Y17": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y18": { + "bits": {}, + "grid_x": 106, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X41Y18", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y18": "SLICEM", + "SLICE_X61Y18": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y19": { + "bits": {}, + "grid_x": 106, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X41Y19", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y19": "SLICEM", + "SLICE_X61Y19": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y2": { + "bits": {}, + "grid_x": 106, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X41Y2", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y2": "SLICEM", + "SLICE_X61Y2": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y20": { + "bits": {}, + "grid_x": 106, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X41Y20", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y20": "SLICEM", + "SLICE_X61Y20": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y21": { + "bits": {}, + "grid_x": 106, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X41Y21", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y21": "SLICEM", + "SLICE_X61Y21": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y22": { + "bits": {}, + "grid_x": 106, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X41Y22", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y22": "SLICEM", + "SLICE_X61Y22": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y23": { + "bits": {}, + "grid_x": 106, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X41Y23", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y23": "SLICEM", + "SLICE_X61Y23": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y24": { + "bits": {}, + "grid_x": 106, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X41Y24", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y24": "SLICEM", + "SLICE_X61Y24": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y25": { + "bits": {}, + "grid_x": 106, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X41Y25", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y25": "SLICEM", + "SLICE_X61Y25": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y26": { + "bits": {}, + "grid_x": 106, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X41Y26", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y26": "SLICEM", + "SLICE_X61Y26": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y27": { + "bits": {}, + "grid_x": 106, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X41Y27", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y27": "SLICEM", + "SLICE_X61Y27": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y28": { + "bits": {}, + "grid_x": 106, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X41Y28", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y28": "SLICEM", + "SLICE_X61Y28": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y29": { + "bits": {}, + "grid_x": 106, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X41Y29", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y29": "SLICEM", + "SLICE_X61Y29": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y3": { + "bits": {}, + "grid_x": 106, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X41Y3", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y3": "SLICEM", + "SLICE_X61Y3": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y30": { + "bits": {}, + "grid_x": 106, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X41Y30", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y30": "SLICEM", + "SLICE_X61Y30": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y31": { + "bits": {}, + "grid_x": 106, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X41Y31", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y31": "SLICEM", + "SLICE_X61Y31": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y32": { + "bits": {}, + "grid_x": 106, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X41Y32", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y32": "SLICEM", + "SLICE_X61Y32": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y33": { + "bits": {}, + "grid_x": 106, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X41Y33", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y33": "SLICEM", + "SLICE_X61Y33": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y34": { + "bits": {}, + "grid_x": 106, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X41Y34", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y34": "SLICEM", + "SLICE_X61Y34": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y35": { + "bits": {}, + "grid_x": 106, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X41Y35", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y35": "SLICEM", + "SLICE_X61Y35": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y36": { + "bits": {}, + "grid_x": 106, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X41Y36", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y36": "SLICEM", + "SLICE_X61Y36": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y37": { + "bits": {}, + "grid_x": 106, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X41Y37", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y37": "SLICEM", + "SLICE_X61Y37": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y38": { + "bits": {}, + "grid_x": 106, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X41Y38", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y38": "SLICEM", + "SLICE_X61Y38": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y39": { + "bits": {}, + "grid_x": 106, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X41Y39", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y39": "SLICEM", + "SLICE_X61Y39": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y4": { + "bits": {}, + "grid_x": 106, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X41Y4", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y4": "SLICEM", + "SLICE_X61Y4": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y40": { + "bits": {}, + "grid_x": 106, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X41Y40", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y40": "SLICEM", + "SLICE_X61Y40": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y41": { + "bits": {}, + "grid_x": 106, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X41Y41", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y41": "SLICEM", + "SLICE_X61Y41": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y42": { + "bits": {}, + "grid_x": 106, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X41Y42", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y42": "SLICEM", + "SLICE_X61Y42": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y43": { + "bits": {}, + "grid_x": 106, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X41Y43", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y43": "SLICEM", + "SLICE_X61Y43": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y44": { + "bits": {}, + "grid_x": 106, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X41Y44", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y44": "SLICEM", + "SLICE_X61Y44": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y45": { + "bits": {}, + "grid_x": 106, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X41Y45", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y45": "SLICEM", + "SLICE_X61Y45": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y46": { + "bits": {}, + "grid_x": 106, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X41Y46", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y46": "SLICEM", + "SLICE_X61Y46": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y47": { + "bits": {}, + "grid_x": 106, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X41Y47", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y47": "SLICEM", + "SLICE_X61Y47": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y48": { + "bits": {}, + "grid_x": 106, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X41Y48", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y48": "SLICEM", + "SLICE_X61Y48": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y49": { + "bits": {}, + "grid_x": 106, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X41Y49", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y49": "SLICEM", + "SLICE_X61Y49": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y5": { + "bits": {}, + "grid_x": 106, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X41Y5", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y5": "SLICEM", + "SLICE_X61Y5": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y50": { + "bits": {}, + "grid_x": 106, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X41Y50", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y50": "SLICEM", + "SLICE_X61Y50": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y51": { + "bits": {}, + "grid_x": 106, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X41Y51", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y51": "SLICEM", + "SLICE_X61Y51": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y52": { + "bits": {}, + "grid_x": 106, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X41Y52", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y52": "SLICEM", + "SLICE_X61Y52": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y53": { + "bits": {}, + "grid_x": 106, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X41Y53", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y53": "SLICEM", + "SLICE_X61Y53": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y54": { + "bits": {}, + "grid_x": 106, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X41Y54", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y54": "SLICEM", + "SLICE_X61Y54": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y55": { + "bits": {}, + "grid_x": 106, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X41Y55", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y55": "SLICEM", + "SLICE_X61Y55": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y56": { + "bits": {}, + "grid_x": 106, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X41Y56", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y56": "SLICEM", + "SLICE_X61Y56": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y57": { + "bits": {}, + "grid_x": 106, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X41Y57", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y57": "SLICEM", + "SLICE_X61Y57": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y58": { + "bits": {}, + "grid_x": 106, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X41Y58", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y58": "SLICEM", + "SLICE_X61Y58": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y59": { + "bits": {}, + "grid_x": 106, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X41Y59", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y59": "SLICEM", + "SLICE_X61Y59": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y6": { + "bits": {}, + "grid_x": 106, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X41Y6", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y6": "SLICEM", + "SLICE_X61Y6": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y60": { + "bits": {}, + "grid_x": 106, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X41Y60", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y60": "SLICEM", + "SLICE_X61Y60": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y61": { + "bits": {}, + "grid_x": 106, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X41Y61", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y61": "SLICEM", + "SLICE_X61Y61": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y62": { + "bits": {}, + "grid_x": 106, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X41Y62", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y62": "SLICEM", + "SLICE_X61Y62": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y63": { + "bits": {}, + "grid_x": 106, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X41Y63", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y63": "SLICEM", + "SLICE_X61Y63": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y64": { + "bits": {}, + "grid_x": 106, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X41Y64", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y64": "SLICEM", + "SLICE_X61Y64": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y65": { + "bits": {}, + "grid_x": 106, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X41Y65", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y65": "SLICEM", + "SLICE_X61Y65": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y66": { + "bits": {}, + "grid_x": 106, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X41Y66", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y66": "SLICEM", + "SLICE_X61Y66": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y67": { + "bits": {}, + "grid_x": 106, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X41Y67", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y67": "SLICEM", + "SLICE_X61Y67": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y68": { + "bits": {}, + "grid_x": 106, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X41Y68", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y68": "SLICEM", + "SLICE_X61Y68": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y69": { + "bits": {}, + "grid_x": 106, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X41Y69", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y69": "SLICEM", + "SLICE_X61Y69": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y7": { + "bits": {}, + "grid_x": 106, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X41Y7", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y7": "SLICEM", + "SLICE_X61Y7": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y70": { + "bits": {}, + "grid_x": 106, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X41Y70", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y70": "SLICEM", + "SLICE_X61Y70": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y71": { + "bits": {}, + "grid_x": 106, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X41Y71", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y71": "SLICEM", + "SLICE_X61Y71": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y72": { + "bits": {}, + "grid_x": 106, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X41Y72", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y72": "SLICEM", + "SLICE_X61Y72": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y73": { + "bits": {}, + "grid_x": 106, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X41Y73", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y73": "SLICEM", + "SLICE_X61Y73": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y74": { + "bits": {}, + "grid_x": 106, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X41Y74", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y74": "SLICEM", + "SLICE_X61Y74": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y75": { + "bits": {}, + "grid_x": 106, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X41Y75", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y75": "SLICEM", + "SLICE_X61Y75": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y76": { + "bits": {}, + "grid_x": 106, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X41Y76", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y76": "SLICEM", + "SLICE_X61Y76": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y77": { + "bits": {}, + "grid_x": 106, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X41Y77", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y77": "SLICEM", + "SLICE_X61Y77": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y78": { + "bits": {}, + "grid_x": 106, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X41Y78", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y78": "SLICEM", + "SLICE_X61Y78": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y79": { + "bits": {}, + "grid_x": 106, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X41Y79", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y79": "SLICEM", + "SLICE_X61Y79": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y8": { + "bits": {}, + "grid_x": 106, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X41Y8", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y8": "SLICEM", + "SLICE_X61Y8": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y80": { + "bits": {}, + "grid_x": 106, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X41Y80", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y80": "SLICEM", + "SLICE_X61Y80": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y81": { + "bits": {}, + "grid_x": 106, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X41Y81", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y81": "SLICEM", + "SLICE_X61Y81": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y82": { + "bits": {}, + "grid_x": 106, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X41Y82", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y82": "SLICEM", + "SLICE_X61Y82": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y83": { + "bits": {}, + "grid_x": 106, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X41Y83", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y83": "SLICEM", + "SLICE_X61Y83": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y84": { + "bits": {}, + "grid_x": 106, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X41Y84", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y84": "SLICEM", + "SLICE_X61Y84": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y85": { + "bits": {}, + "grid_x": 106, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X41Y85", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y85": "SLICEM", + "SLICE_X61Y85": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y86": { + "bits": {}, + "grid_x": 106, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X41Y86", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y86": "SLICEM", + "SLICE_X61Y86": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y87": { + "bits": {}, + "grid_x": 106, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X41Y87", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y87": "SLICEM", + "SLICE_X61Y87": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y88": { + "bits": {}, + "grid_x": 106, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X41Y88", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y88": "SLICEM", + "SLICE_X61Y88": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y89": { + "bits": {}, + "grid_x": 106, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X41Y89", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y89": "SLICEM", + "SLICE_X61Y89": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y9": { + "bits": {}, + "grid_x": 106, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X41Y9", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y9": "SLICEM", + "SLICE_X61Y9": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y90": { + "bits": {}, + "grid_x": 106, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X41Y90", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y90": "SLICEM", + "SLICE_X61Y90": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y91": { + "bits": {}, + "grid_x": 106, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X41Y91", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y91": "SLICEM", + "SLICE_X61Y91": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y92": { + "bits": {}, + "grid_x": 106, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X41Y92", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y92": "SLICEM", + "SLICE_X61Y92": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y93": { + "bits": {}, + "grid_x": 106, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X41Y93", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y93": "SLICEM", + "SLICE_X61Y93": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y94": { + "bits": {}, + "grid_x": 106, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X41Y94", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y94": "SLICEM", + "SLICE_X61Y94": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y95": { + "bits": {}, + "grid_x": 106, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X41Y95", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y95": "SLICEM", + "SLICE_X61Y95": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y96": { + "bits": {}, + "grid_x": 106, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X41Y96", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y96": "SLICEM", + "SLICE_X61Y96": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y97": { + "bits": {}, + "grid_x": 106, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X41Y97", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y97": "SLICEM", + "SLICE_X61Y97": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y98": { + "bits": {}, + "grid_x": 106, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X41Y98", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y98": "SLICEM", + "SLICE_X61Y98": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X41Y99": { + "bits": {}, + "grid_x": 106, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X41Y99", + "segment_type": "clblm_r", + "sites": { + "SLICE_X60Y99": "SLICEM", + "SLICE_X61Y99": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y0": { + "bits": {}, + "grid_x": 17, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X5Y0", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y0": "SLICEM", + "SLICE_X7Y0": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y1": { + "bits": {}, + "grid_x": 17, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X5Y1", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y1": "SLICEM", + "SLICE_X7Y1": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y10": { + "bits": {}, + "grid_x": 17, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X5Y10", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y10": "SLICEM", + "SLICE_X7Y10": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y100": { + "bits": {}, + "grid_x": 17, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X5Y100", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y100": "SLICEM", + "SLICE_X7Y100": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y101": { + "bits": {}, + "grid_x": 17, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X5Y101", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y101": "SLICEM", + "SLICE_X7Y101": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y102": { + "bits": {}, + "grid_x": 17, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X5Y102", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y102": "SLICEM", + "SLICE_X7Y102": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y103": { + "bits": {}, + "grid_x": 17, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X5Y103", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y103": "SLICEM", + "SLICE_X7Y103": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y104": { + "bits": {}, + "grid_x": 17, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X5Y104", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y104": "SLICEM", + "SLICE_X7Y104": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y105": { + "bits": {}, + "grid_x": 17, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X5Y105", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y105": "SLICEM", + "SLICE_X7Y105": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y106": { + "bits": {}, + "grid_x": 17, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X5Y106", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y106": "SLICEM", + "SLICE_X7Y106": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y107": { + "bits": {}, + "grid_x": 17, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X5Y107", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y107": "SLICEM", + "SLICE_X7Y107": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y108": { + "bits": {}, + "grid_x": 17, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X5Y108", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y108": "SLICEM", + "SLICE_X7Y108": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y109": { + "bits": {}, + "grid_x": 17, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X5Y109", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y109": "SLICEM", + "SLICE_X7Y109": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y11": { + "bits": {}, + "grid_x": 17, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X5Y11", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y11": "SLICEM", + "SLICE_X7Y11": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y110": { + "bits": {}, + "grid_x": 17, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X5Y110", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y110": "SLICEM", + "SLICE_X7Y110": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y111": { + "bits": {}, + "grid_x": 17, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X5Y111", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y111": "SLICEM", + "SLICE_X7Y111": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y112": { + "bits": {}, + "grid_x": 17, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X5Y112", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y112": "SLICEM", + "SLICE_X7Y112": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y113": { + "bits": {}, + "grid_x": 17, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X5Y113", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y113": "SLICEM", + "SLICE_X7Y113": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y114": { + "bits": {}, + "grid_x": 17, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X5Y114", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y114": "SLICEM", + "SLICE_X7Y114": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y115": { + "bits": {}, + "grid_x": 17, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X5Y115", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y115": "SLICEM", + "SLICE_X7Y115": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y116": { + "bits": {}, + "grid_x": 17, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X5Y116", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y116": "SLICEM", + "SLICE_X7Y116": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y117": { + "bits": {}, + "grid_x": 17, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X5Y117", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y117": "SLICEM", + "SLICE_X7Y117": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y118": { + "bits": {}, + "grid_x": 17, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X5Y118", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y118": "SLICEM", + "SLICE_X7Y118": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y119": { + "bits": {}, + "grid_x": 17, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X5Y119", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y119": "SLICEM", + "SLICE_X7Y119": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y12": { + "bits": {}, + "grid_x": 17, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X5Y12", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y12": "SLICEM", + "SLICE_X7Y12": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y120": { + "bits": {}, + "grid_x": 17, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X5Y120", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y120": "SLICEM", + "SLICE_X7Y120": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y121": { + "bits": {}, + "grid_x": 17, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X5Y121", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y121": "SLICEM", + "SLICE_X7Y121": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y122": { + "bits": {}, + "grid_x": 17, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X5Y122", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y122": "SLICEM", + "SLICE_X7Y122": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y123": { + "bits": {}, + "grid_x": 17, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X5Y123", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y123": "SLICEM", + "SLICE_X7Y123": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y124": { + "bits": {}, + "grid_x": 17, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X5Y124", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y124": "SLICEM", + "SLICE_X7Y124": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y125": { + "bits": {}, + "grid_x": 17, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X5Y125", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y125": "SLICEM", + "SLICE_X7Y125": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y126": { + "bits": {}, + "grid_x": 17, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X5Y126", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y126": "SLICEM", + "SLICE_X7Y126": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y127": { + "bits": {}, + "grid_x": 17, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X5Y127", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y127": "SLICEM", + "SLICE_X7Y127": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y128": { + "bits": {}, + "grid_x": 17, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X5Y128", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y128": "SLICEM", + "SLICE_X7Y128": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y129": { + "bits": {}, + "grid_x": 17, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X5Y129", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y129": "SLICEM", + "SLICE_X7Y129": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y13": { + "bits": {}, + "grid_x": 17, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X5Y13", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y13": "SLICEM", + "SLICE_X7Y13": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y130": { + "bits": {}, + "grid_x": 17, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X5Y130", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y130": "SLICEM", + "SLICE_X7Y130": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y131": { + "bits": {}, + "grid_x": 17, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X5Y131", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y131": "SLICEM", + "SLICE_X7Y131": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y132": { + "bits": {}, + "grid_x": 17, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X5Y132", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y132": "SLICEM", + "SLICE_X7Y132": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y133": { + "bits": {}, + "grid_x": 17, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X5Y133", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y133": "SLICEM", + "SLICE_X7Y133": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y134": { + "bits": {}, + "grid_x": 17, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X5Y134", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y134": "SLICEM", + "SLICE_X7Y134": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y135": { + "bits": {}, + "grid_x": 17, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X5Y135", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y135": "SLICEM", + "SLICE_X7Y135": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y136": { + "bits": {}, + "grid_x": 17, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X5Y136", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y136": "SLICEM", + "SLICE_X7Y136": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y137": { + "bits": {}, + "grid_x": 17, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X5Y137", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y137": "SLICEM", + "SLICE_X7Y137": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y138": { + "bits": {}, + "grid_x": 17, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X5Y138", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y138": "SLICEM", + "SLICE_X7Y138": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y139": { + "bits": {}, + "grid_x": 17, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X5Y139", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y139": "SLICEM", + "SLICE_X7Y139": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y14": { + "bits": {}, + "grid_x": 17, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X5Y14", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y14": "SLICEM", + "SLICE_X7Y14": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y140": { + "bits": {}, + "grid_x": 17, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X5Y140", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y140": "SLICEM", + "SLICE_X7Y140": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y141": { + "bits": {}, + "grid_x": 17, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X5Y141", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y141": "SLICEM", + "SLICE_X7Y141": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y142": { + "bits": {}, + "grid_x": 17, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X5Y142", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y142": "SLICEM", + "SLICE_X7Y142": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y143": { + "bits": {}, + "grid_x": 17, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X5Y143", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y143": "SLICEM", + "SLICE_X7Y143": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y144": { + "bits": {}, + "grid_x": 17, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X5Y144", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y144": "SLICEM", + "SLICE_X7Y144": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y145": { + "bits": {}, + "grid_x": 17, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X5Y145", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y145": "SLICEM", + "SLICE_X7Y145": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y146": { + "bits": {}, + "grid_x": 17, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X5Y146", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y146": "SLICEM", + "SLICE_X7Y146": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y147": { + "bits": {}, + "grid_x": 17, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X5Y147", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y147": "SLICEM", + "SLICE_X7Y147": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y148": { + "bits": {}, + "grid_x": 17, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X5Y148", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y148": "SLICEM", + "SLICE_X7Y148": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y149": { + "bits": {}, + "grid_x": 17, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X5Y149", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y149": "SLICEM", + "SLICE_X7Y149": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y15": { + "bits": {}, + "grid_x": 17, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X5Y15", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y15": "SLICEM", + "SLICE_X7Y15": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y150": { + "bits": {}, + "grid_x": 17, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X5Y150", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y150": "SLICEM", + "SLICE_X7Y150": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y151": { + "bits": {}, + "grid_x": 17, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X5Y151", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y151": "SLICEM", + "SLICE_X7Y151": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y152": { + "bits": {}, + "grid_x": 17, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X5Y152", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y152": "SLICEM", + "SLICE_X7Y152": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y153": { + "bits": {}, + "grid_x": 17, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X5Y153", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y153": "SLICEM", + "SLICE_X7Y153": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y154": { + "bits": {}, + "grid_x": 17, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X5Y154", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y154": "SLICEM", + "SLICE_X7Y154": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y155": { + "bits": {}, + "grid_x": 17, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X5Y155", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y155": "SLICEM", + "SLICE_X7Y155": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y156": { + "bits": {}, + "grid_x": 17, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X5Y156", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y156": "SLICEM", + "SLICE_X7Y156": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y157": { + "bits": {}, + "grid_x": 17, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X5Y157", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y157": "SLICEM", + "SLICE_X7Y157": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y158": { + "bits": {}, + "grid_x": 17, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X5Y158", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y158": "SLICEM", + "SLICE_X7Y158": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y159": { + "bits": {}, + "grid_x": 17, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X5Y159", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y159": "SLICEM", + "SLICE_X7Y159": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y16": { + "bits": {}, + "grid_x": 17, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X5Y16", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y16": "SLICEM", + "SLICE_X7Y16": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y160": { + "bits": {}, + "grid_x": 17, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X5Y160", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y160": "SLICEM", + "SLICE_X7Y160": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y161": { + "bits": {}, + "grid_x": 17, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X5Y161", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y161": "SLICEM", + "SLICE_X7Y161": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y162": { + "bits": {}, + "grid_x": 17, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X5Y162", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y162": "SLICEM", + "SLICE_X7Y162": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y163": { + "bits": {}, + "grid_x": 17, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X5Y163", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y163": "SLICEM", + "SLICE_X7Y163": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y164": { + "bits": {}, + "grid_x": 17, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X5Y164", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y164": "SLICEM", + "SLICE_X7Y164": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y165": { + "bits": {}, + "grid_x": 17, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X5Y165", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y165": "SLICEM", + "SLICE_X7Y165": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y166": { + "bits": {}, + "grid_x": 17, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X5Y166", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y166": "SLICEM", + "SLICE_X7Y166": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y167": { + "bits": {}, + "grid_x": 17, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X5Y167", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y167": "SLICEM", + "SLICE_X7Y167": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y168": { + "bits": {}, + "grid_x": 17, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X5Y168", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y168": "SLICEM", + "SLICE_X7Y168": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y169": { + "bits": {}, + "grid_x": 17, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X5Y169", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y169": "SLICEM", + "SLICE_X7Y169": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y17": { + "bits": {}, + "grid_x": 17, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X5Y17", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y17": "SLICEM", + "SLICE_X7Y17": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y170": { + "bits": {}, + "grid_x": 17, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X5Y170", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y170": "SLICEM", + "SLICE_X7Y170": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y171": { + "bits": {}, + "grid_x": 17, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X5Y171", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y171": "SLICEM", + "SLICE_X7Y171": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y172": { + "bits": {}, + "grid_x": 17, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X5Y172", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y172": "SLICEM", + "SLICE_X7Y172": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y173": { + "bits": {}, + "grid_x": 17, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X5Y173", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y173": "SLICEM", + "SLICE_X7Y173": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y174": { + "bits": {}, + "grid_x": 17, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X5Y174", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y174": "SLICEM", + "SLICE_X7Y174": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y175": { + "bits": {}, + "grid_x": 17, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X5Y175", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y175": "SLICEM", + "SLICE_X7Y175": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y176": { + "bits": {}, + "grid_x": 17, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X5Y176", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y176": "SLICEM", + "SLICE_X7Y176": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y177": { + "bits": {}, + "grid_x": 17, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X5Y177", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y177": "SLICEM", + "SLICE_X7Y177": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y178": { + "bits": {}, + "grid_x": 17, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X5Y178", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y178": "SLICEM", + "SLICE_X7Y178": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y179": { + "bits": {}, + "grid_x": 17, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X5Y179", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y179": "SLICEM", + "SLICE_X7Y179": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y18": { + "bits": {}, + "grid_x": 17, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X5Y18", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y18": "SLICEM", + "SLICE_X7Y18": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y180": { + "bits": {}, + "grid_x": 17, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X5Y180", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y180": "SLICEM", + "SLICE_X7Y180": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y181": { + "bits": {}, + "grid_x": 17, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X5Y181", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y181": "SLICEM", + "SLICE_X7Y181": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y182": { + "bits": {}, + "grid_x": 17, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X5Y182", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y182": "SLICEM", + "SLICE_X7Y182": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y183": { + "bits": {}, + "grid_x": 17, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X5Y183", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y183": "SLICEM", + "SLICE_X7Y183": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y184": { + "bits": {}, + "grid_x": 17, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X5Y184", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y184": "SLICEM", + "SLICE_X7Y184": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y185": { + "bits": {}, + "grid_x": 17, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X5Y185", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y185": "SLICEM", + "SLICE_X7Y185": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y186": { + "bits": {}, + "grid_x": 17, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X5Y186", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y186": "SLICEM", + "SLICE_X7Y186": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y187": { + "bits": {}, + "grid_x": 17, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X5Y187", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y187": "SLICEM", + "SLICE_X7Y187": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y188": { + "bits": {}, + "grid_x": 17, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X5Y188", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y188": "SLICEM", + "SLICE_X7Y188": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y189": { + "bits": {}, + "grid_x": 17, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X5Y189", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y189": "SLICEM", + "SLICE_X7Y189": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y19": { + "bits": {}, + "grid_x": 17, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X5Y19", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y19": "SLICEM", + "SLICE_X7Y19": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y190": { + "bits": {}, + "grid_x": 17, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X5Y190", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y190": "SLICEM", + "SLICE_X7Y190": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y191": { + "bits": {}, + "grid_x": 17, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X5Y191", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y191": "SLICEM", + "SLICE_X7Y191": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y192": { + "bits": {}, + "grid_x": 17, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X5Y192", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y192": "SLICEM", + "SLICE_X7Y192": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y193": { + "bits": {}, + "grid_x": 17, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X5Y193", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y193": "SLICEM", + "SLICE_X7Y193": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y194": { + "bits": {}, + "grid_x": 17, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X5Y194", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y194": "SLICEM", + "SLICE_X7Y194": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y195": { + "bits": {}, + "grid_x": 17, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X5Y195", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y195": "SLICEM", + "SLICE_X7Y195": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y196": { + "bits": {}, + "grid_x": 17, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X5Y196", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y196": "SLICEM", + "SLICE_X7Y196": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y197": { + "bits": {}, + "grid_x": 17, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X5Y197", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y197": "SLICEM", + "SLICE_X7Y197": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y198": { + "bits": {}, + "grid_x": 17, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X5Y198", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y198": "SLICEM", + "SLICE_X7Y198": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y199": { + "bits": {}, + "grid_x": 17, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X5Y199", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y199": "SLICEM", + "SLICE_X7Y199": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y2": { + "bits": {}, + "grid_x": 17, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X5Y2", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y2": "SLICEM", + "SLICE_X7Y2": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y20": { + "bits": {}, + "grid_x": 17, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X5Y20", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y20": "SLICEM", + "SLICE_X7Y20": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y21": { + "bits": {}, + "grid_x": 17, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X5Y21", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y21": "SLICEM", + "SLICE_X7Y21": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y22": { + "bits": {}, + "grid_x": 17, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X5Y22", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y22": "SLICEM", + "SLICE_X7Y22": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y23": { + "bits": {}, + "grid_x": 17, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X5Y23", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y23": "SLICEM", + "SLICE_X7Y23": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y24": { + "bits": {}, + "grid_x": 17, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X5Y24", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y24": "SLICEM", + "SLICE_X7Y24": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y25": { + "bits": {}, + "grid_x": 17, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X5Y25", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y25": "SLICEM", + "SLICE_X7Y25": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y26": { + "bits": {}, + "grid_x": 17, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X5Y26", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y26": "SLICEM", + "SLICE_X7Y26": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y27": { + "bits": {}, + "grid_x": 17, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X5Y27", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y27": "SLICEM", + "SLICE_X7Y27": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y28": { + "bits": {}, + "grid_x": 17, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X5Y28", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y28": "SLICEM", + "SLICE_X7Y28": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y29": { + "bits": {}, + "grid_x": 17, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X5Y29", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y29": "SLICEM", + "SLICE_X7Y29": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y3": { + "bits": {}, + "grid_x": 17, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X5Y3", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y3": "SLICEM", + "SLICE_X7Y3": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y30": { + "bits": {}, + "grid_x": 17, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X5Y30", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y30": "SLICEM", + "SLICE_X7Y30": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y31": { + "bits": {}, + "grid_x": 17, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X5Y31", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y31": "SLICEM", + "SLICE_X7Y31": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y32": { + "bits": {}, + "grid_x": 17, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X5Y32", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y32": "SLICEM", + "SLICE_X7Y32": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y33": { + "bits": {}, + "grid_x": 17, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X5Y33", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y33": "SLICEM", + "SLICE_X7Y33": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y34": { + "bits": {}, + "grid_x": 17, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X5Y34", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y34": "SLICEM", + "SLICE_X7Y34": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y35": { + "bits": {}, + "grid_x": 17, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X5Y35", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y35": "SLICEM", + "SLICE_X7Y35": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y36": { + "bits": {}, + "grid_x": 17, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X5Y36", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y36": "SLICEM", + "SLICE_X7Y36": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y37": { + "bits": {}, + "grid_x": 17, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X5Y37", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y37": "SLICEM", + "SLICE_X7Y37": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y38": { + "bits": {}, + "grid_x": 17, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X5Y38", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y38": "SLICEM", + "SLICE_X7Y38": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y39": { + "bits": {}, + "grid_x": 17, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X5Y39", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y39": "SLICEM", + "SLICE_X7Y39": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y4": { + "bits": {}, + "grid_x": 17, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X5Y4", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y4": "SLICEM", + "SLICE_X7Y4": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y40": { + "bits": {}, + "grid_x": 17, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X5Y40", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y40": "SLICEM", + "SLICE_X7Y40": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y41": { + "bits": {}, + "grid_x": 17, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X5Y41", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y41": "SLICEM", + "SLICE_X7Y41": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y42": { + "bits": {}, + "grid_x": 17, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X5Y42", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y42": "SLICEM", + "SLICE_X7Y42": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y43": { + "bits": {}, + "grid_x": 17, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X5Y43", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y43": "SLICEM", + "SLICE_X7Y43": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y44": { + "bits": {}, + "grid_x": 17, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X5Y44", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y44": "SLICEM", + "SLICE_X7Y44": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y45": { + "bits": {}, + "grid_x": 17, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X5Y45", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y45": "SLICEM", + "SLICE_X7Y45": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y46": { + "bits": {}, + "grid_x": 17, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X5Y46", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y46": "SLICEM", + "SLICE_X7Y46": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y47": { + "bits": {}, + "grid_x": 17, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X5Y47", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y47": "SLICEM", + "SLICE_X7Y47": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y48": { + "bits": {}, + "grid_x": 17, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X5Y48", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y48": "SLICEM", + "SLICE_X7Y48": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y49": { + "bits": {}, + "grid_x": 17, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X5Y49", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y49": "SLICEM", + "SLICE_X7Y49": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y5": { + "bits": {}, + "grid_x": 17, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X5Y5", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y5": "SLICEM", + "SLICE_X7Y5": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X5Y50", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y50": "SLICEM", + "SLICE_X7Y50": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X5Y51", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y51": "SLICEM", + "SLICE_X7Y51": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X5Y52", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y52": "SLICEM", + "SLICE_X7Y52": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X5Y53", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y53": "SLICEM", + "SLICE_X7Y53": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X5Y54", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y54": "SLICEM", + "SLICE_X7Y54": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X5Y55", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y55": "SLICEM", + "SLICE_X7Y55": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X5Y56", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y56": "SLICEM", + "SLICE_X7Y56": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X5Y57", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y57": "SLICEM", + "SLICE_X7Y57": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X5Y58", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y58": "SLICEM", + "SLICE_X7Y58": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X5Y59", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y59": "SLICEM", + "SLICE_X7Y59": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y6": { + "bits": {}, + "grid_x": 17, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X5Y6", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y6": "SLICEM", + "SLICE_X7Y6": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X5Y60", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y60": "SLICEM", + "SLICE_X7Y60": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X5Y61", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y61": "SLICEM", + "SLICE_X7Y61": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X5Y62", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y62": "SLICEM", + "SLICE_X7Y62": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X5Y63", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y63": "SLICEM", + "SLICE_X7Y63": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X5Y64", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y64": "SLICEM", + "SLICE_X7Y64": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X5Y65", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y65": "SLICEM", + "SLICE_X7Y65": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X5Y66", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y66": "SLICEM", + "SLICE_X7Y66": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X5Y67", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y67": "SLICEM", + "SLICE_X7Y67": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X5Y68", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y68": "SLICEM", + "SLICE_X7Y68": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X5Y69", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y69": "SLICEM", + "SLICE_X7Y69": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y7": { + "bits": {}, + "grid_x": 17, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X5Y7", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y7": "SLICEM", + "SLICE_X7Y7": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X5Y70", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y70": "SLICEM", + "SLICE_X7Y70": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X5Y71", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y71": "SLICEM", + "SLICE_X7Y71": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X5Y72", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y72": "SLICEM", + "SLICE_X7Y72": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X5Y73", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y73": "SLICEM", + "SLICE_X7Y73": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X5Y74", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y74": "SLICEM", + "SLICE_X7Y74": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X5Y75", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y75": "SLICEM", + "SLICE_X7Y75": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X5Y76", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y76": "SLICEM", + "SLICE_X7Y76": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X5Y77", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y77": "SLICEM", + "SLICE_X7Y77": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X5Y78", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y78": "SLICEM", + "SLICE_X7Y78": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X5Y79", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y79": "SLICEM", + "SLICE_X7Y79": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y8": { + "bits": {}, + "grid_x": 17, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X5Y8", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y8": "SLICEM", + "SLICE_X7Y8": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X5Y80", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y80": "SLICEM", + "SLICE_X7Y80": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X5Y81", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y81": "SLICEM", + "SLICE_X7Y81": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X5Y82", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y82": "SLICEM", + "SLICE_X7Y82": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X5Y83", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y83": "SLICEM", + "SLICE_X7Y83": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X5Y84", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y84": "SLICEM", + "SLICE_X7Y84": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X5Y85", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y85": "SLICEM", + "SLICE_X7Y85": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X5Y86", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y86": "SLICEM", + "SLICE_X7Y86": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X5Y87", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y87": "SLICEM", + "SLICE_X7Y87": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X5Y88", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y88": "SLICEM", + "SLICE_X7Y88": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X5Y89", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y89": "SLICEM", + "SLICE_X7Y89": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y9": { + "bits": {}, + "grid_x": 17, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X5Y9", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y9": "SLICEM", + "SLICE_X7Y9": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X5Y90", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y90": "SLICEM", + "SLICE_X7Y90": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X5Y91", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y91": "SLICEM", + "SLICE_X7Y91": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X5Y92", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y92": "SLICEM", + "SLICE_X7Y92": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X5Y93", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y93": "SLICEM", + "SLICE_X7Y93": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X5Y94", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y94": "SLICEM", + "SLICE_X7Y94": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X5Y95", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y95": "SLICEM", + "SLICE_X7Y95": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X5Y96", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y96": "SLICEM", + "SLICE_X7Y96": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X5Y97", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y97": "SLICEM", + "SLICE_X7Y97": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X5Y98", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y98": "SLICEM", + "SLICE_X7Y98": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X5Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 36, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 17, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X5Y99", + "segment_type": "clblm_r", + "sites": { + "SLICE_X6Y99": "SLICEM", + "SLICE_X7Y99": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y0": { + "bits": {}, + "grid_x": 23, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X7Y0", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y0": "SLICEM", + "SLICE_X9Y0": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y1": { + "bits": {}, + "grid_x": 23, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X7Y1", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y1": "SLICEM", + "SLICE_X9Y1": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y10": { + "bits": {}, + "grid_x": 23, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X7Y10", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y10": "SLICEM", + "SLICE_X9Y10": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y100": { + "bits": {}, + "grid_x": 23, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X7Y100", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y100": "SLICEM", + "SLICE_X9Y100": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y101": { + "bits": {}, + "grid_x": 23, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X7Y101", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y101": "SLICEM", + "SLICE_X9Y101": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y102": { + "bits": {}, + "grid_x": 23, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X7Y102", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y102": "SLICEM", + "SLICE_X9Y102": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y103": { + "bits": {}, + "grid_x": 23, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X7Y103", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y103": "SLICEM", + "SLICE_X9Y103": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y104": { + "bits": {}, + "grid_x": 23, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X7Y104", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y104": "SLICEM", + "SLICE_X9Y104": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y105": { + "bits": {}, + "grid_x": 23, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X7Y105", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y105": "SLICEM", + "SLICE_X9Y105": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y106": { + "bits": {}, + "grid_x": 23, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X7Y106", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y106": "SLICEM", + "SLICE_X9Y106": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y107": { + "bits": {}, + "grid_x": 23, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X7Y107", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y107": "SLICEM", + "SLICE_X9Y107": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y108": { + "bits": {}, + "grid_x": 23, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X7Y108", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y108": "SLICEM", + "SLICE_X9Y108": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y109": { + "bits": {}, + "grid_x": 23, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X7Y109", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y109": "SLICEM", + "SLICE_X9Y109": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y11": { + "bits": {}, + "grid_x": 23, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X7Y11", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y11": "SLICEM", + "SLICE_X9Y11": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y110": { + "bits": {}, + "grid_x": 23, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X7Y110", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y110": "SLICEM", + "SLICE_X9Y110": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y111": { + "bits": {}, + "grid_x": 23, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X7Y111", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y111": "SLICEM", + "SLICE_X9Y111": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y112": { + "bits": {}, + "grid_x": 23, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X7Y112", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y112": "SLICEM", + "SLICE_X9Y112": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y113": { + "bits": {}, + "grid_x": 23, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X7Y113", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y113": "SLICEM", + "SLICE_X9Y113": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y114": { + "bits": {}, + "grid_x": 23, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X7Y114", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y114": "SLICEM", + "SLICE_X9Y114": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y115": { + "bits": {}, + "grid_x": 23, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X7Y115", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y115": "SLICEM", + "SLICE_X9Y115": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y116": { + "bits": {}, + "grid_x": 23, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X7Y116", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y116": "SLICEM", + "SLICE_X9Y116": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y117": { + "bits": {}, + "grid_x": 23, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X7Y117", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y117": "SLICEM", + "SLICE_X9Y117": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y118": { + "bits": {}, + "grid_x": 23, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X7Y118", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y118": "SLICEM", + "SLICE_X9Y118": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y119": { + "bits": {}, + "grid_x": 23, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X7Y119", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y119": "SLICEM", + "SLICE_X9Y119": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y12": { + "bits": {}, + "grid_x": 23, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X7Y12", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y12": "SLICEM", + "SLICE_X9Y12": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y120": { + "bits": {}, + "grid_x": 23, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X7Y120", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y120": "SLICEM", + "SLICE_X9Y120": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y121": { + "bits": {}, + "grid_x": 23, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X7Y121", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y121": "SLICEM", + "SLICE_X9Y121": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y122": { + "bits": {}, + "grid_x": 23, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X7Y122", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y122": "SLICEM", + "SLICE_X9Y122": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y123": { + "bits": {}, + "grid_x": 23, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X7Y123", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y123": "SLICEM", + "SLICE_X9Y123": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y124": { + "bits": {}, + "grid_x": 23, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X7Y124", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y124": "SLICEM", + "SLICE_X9Y124": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y125": { + "bits": {}, + "grid_x": 23, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X7Y125", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y125": "SLICEM", + "SLICE_X9Y125": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y126": { + "bits": {}, + "grid_x": 23, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X7Y126", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y126": "SLICEM", + "SLICE_X9Y126": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y127": { + "bits": {}, + "grid_x": 23, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X7Y127", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y127": "SLICEM", + "SLICE_X9Y127": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y128": { + "bits": {}, + "grid_x": 23, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X7Y128", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y128": "SLICEM", + "SLICE_X9Y128": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y129": { + "bits": {}, + "grid_x": 23, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X7Y129", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y129": "SLICEM", + "SLICE_X9Y129": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y13": { + "bits": {}, + "grid_x": 23, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X7Y13", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y13": "SLICEM", + "SLICE_X9Y13": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y130": { + "bits": {}, + "grid_x": 23, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X7Y130", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y130": "SLICEM", + "SLICE_X9Y130": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y131": { + "bits": {}, + "grid_x": 23, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X7Y131", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y131": "SLICEM", + "SLICE_X9Y131": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y132": { + "bits": {}, + "grid_x": 23, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X7Y132", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y132": "SLICEM", + "SLICE_X9Y132": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y133": { + "bits": {}, + "grid_x": 23, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X7Y133", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y133": "SLICEM", + "SLICE_X9Y133": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y134": { + "bits": {}, + "grid_x": 23, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X7Y134", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y134": "SLICEM", + "SLICE_X9Y134": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y135": { + "bits": {}, + "grid_x": 23, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X7Y135", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y135": "SLICEM", + "SLICE_X9Y135": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y136": { + "bits": {}, + "grid_x": 23, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X7Y136", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y136": "SLICEM", + "SLICE_X9Y136": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y137": { + "bits": {}, + "grid_x": 23, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X7Y137", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y137": "SLICEM", + "SLICE_X9Y137": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y138": { + "bits": {}, + "grid_x": 23, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X7Y138", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y138": "SLICEM", + "SLICE_X9Y138": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y139": { + "bits": {}, + "grid_x": 23, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X7Y139", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y139": "SLICEM", + "SLICE_X9Y139": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y14": { + "bits": {}, + "grid_x": 23, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X7Y14", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y14": "SLICEM", + "SLICE_X9Y14": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y140": { + "bits": {}, + "grid_x": 23, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X7Y140", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y140": "SLICEM", + "SLICE_X9Y140": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y141": { + "bits": {}, + "grid_x": 23, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X7Y141", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y141": "SLICEM", + "SLICE_X9Y141": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y142": { + "bits": {}, + "grid_x": 23, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X7Y142", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y142": "SLICEM", + "SLICE_X9Y142": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y143": { + "bits": {}, + "grid_x": 23, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X7Y143", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y143": "SLICEM", + "SLICE_X9Y143": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y144": { + "bits": {}, + "grid_x": 23, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X7Y144", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y144": "SLICEM", + "SLICE_X9Y144": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y145": { + "bits": {}, + "grid_x": 23, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X7Y145", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y145": "SLICEM", + "SLICE_X9Y145": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y146": { + "bits": {}, + "grid_x": 23, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X7Y146", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y146": "SLICEM", + "SLICE_X9Y146": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y147": { + "bits": {}, + "grid_x": 23, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X7Y147", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y147": "SLICEM", + "SLICE_X9Y147": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y148": { + "bits": {}, + "grid_x": 23, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X7Y148", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y148": "SLICEM", + "SLICE_X9Y148": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y149": { + "bits": {}, + "grid_x": 23, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X7Y149", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y149": "SLICEM", + "SLICE_X9Y149": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y15": { + "bits": {}, + "grid_x": 23, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X7Y15", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y15": "SLICEM", + "SLICE_X9Y15": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y150": { + "bits": {}, + "grid_x": 23, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X7Y150", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y150": "SLICEM", + "SLICE_X9Y150": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y151": { + "bits": {}, + "grid_x": 23, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X7Y151", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y151": "SLICEM", + "SLICE_X9Y151": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y152": { + "bits": {}, + "grid_x": 23, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X7Y152", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y152": "SLICEM", + "SLICE_X9Y152": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y153": { + "bits": {}, + "grid_x": 23, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X7Y153", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y153": "SLICEM", + "SLICE_X9Y153": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y154": { + "bits": {}, + "grid_x": 23, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X7Y154", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y154": "SLICEM", + "SLICE_X9Y154": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y155": { + "bits": {}, + "grid_x": 23, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X7Y155", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y155": "SLICEM", + "SLICE_X9Y155": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y156": { + "bits": {}, + "grid_x": 23, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X7Y156", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y156": "SLICEM", + "SLICE_X9Y156": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y157": { + "bits": {}, + "grid_x": 23, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X7Y157", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y157": "SLICEM", + "SLICE_X9Y157": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y158": { + "bits": {}, + "grid_x": 23, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X7Y158", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y158": "SLICEM", + "SLICE_X9Y158": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y159": { + "bits": {}, + "grid_x": 23, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X7Y159", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y159": "SLICEM", + "SLICE_X9Y159": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y16": { + "bits": {}, + "grid_x": 23, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X7Y16", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y16": "SLICEM", + "SLICE_X9Y16": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y160": { + "bits": {}, + "grid_x": 23, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X7Y160", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y160": "SLICEM", + "SLICE_X9Y160": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y161": { + "bits": {}, + "grid_x": 23, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X7Y161", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y161": "SLICEM", + "SLICE_X9Y161": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y162": { + "bits": {}, + "grid_x": 23, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X7Y162", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y162": "SLICEM", + "SLICE_X9Y162": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y163": { + "bits": {}, + "grid_x": 23, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X7Y163", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y163": "SLICEM", + "SLICE_X9Y163": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y164": { + "bits": {}, + "grid_x": 23, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X7Y164", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y164": "SLICEM", + "SLICE_X9Y164": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y165": { + "bits": {}, + "grid_x": 23, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X7Y165", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y165": "SLICEM", + "SLICE_X9Y165": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y166": { + "bits": {}, + "grid_x": 23, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X7Y166", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y166": "SLICEM", + "SLICE_X9Y166": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y167": { + "bits": {}, + "grid_x": 23, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X7Y167", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y167": "SLICEM", + "SLICE_X9Y167": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y168": { + "bits": {}, + "grid_x": 23, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X7Y168", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y168": "SLICEM", + "SLICE_X9Y168": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y169": { + "bits": {}, + "grid_x": 23, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X7Y169", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y169": "SLICEM", + "SLICE_X9Y169": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y17": { + "bits": {}, + "grid_x": 23, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X7Y17", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y17": "SLICEM", + "SLICE_X9Y17": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y170": { + "bits": {}, + "grid_x": 23, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X7Y170", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y170": "SLICEM", + "SLICE_X9Y170": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y171": { + "bits": {}, + "grid_x": 23, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X7Y171", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y171": "SLICEM", + "SLICE_X9Y171": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y172": { + "bits": {}, + "grid_x": 23, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X7Y172", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y172": "SLICEM", + "SLICE_X9Y172": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y173": { + "bits": {}, + "grid_x": 23, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X7Y173", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y173": "SLICEM", + "SLICE_X9Y173": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y174": { + "bits": {}, + "grid_x": 23, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X7Y174", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y174": "SLICEM", + "SLICE_X9Y174": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y175": { + "bits": {}, + "grid_x": 23, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X7Y175", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y175": "SLICEM", + "SLICE_X9Y175": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y176": { + "bits": {}, + "grid_x": 23, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X7Y176", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y176": "SLICEM", + "SLICE_X9Y176": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y177": { + "bits": {}, + "grid_x": 23, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X7Y177", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y177": "SLICEM", + "SLICE_X9Y177": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y178": { + "bits": {}, + "grid_x": 23, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X7Y178", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y178": "SLICEM", + "SLICE_X9Y178": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y179": { + "bits": {}, + "grid_x": 23, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X7Y179", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y179": "SLICEM", + "SLICE_X9Y179": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y18": { + "bits": {}, + "grid_x": 23, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X7Y18", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y18": "SLICEM", + "SLICE_X9Y18": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y180": { + "bits": {}, + "grid_x": 23, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X7Y180", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y180": "SLICEM", + "SLICE_X9Y180": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y181": { + "bits": {}, + "grid_x": 23, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X7Y181", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y181": "SLICEM", + "SLICE_X9Y181": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y182": { + "bits": {}, + "grid_x": 23, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X7Y182", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y182": "SLICEM", + "SLICE_X9Y182": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y183": { + "bits": {}, + "grid_x": 23, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X7Y183", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y183": "SLICEM", + "SLICE_X9Y183": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y184": { + "bits": {}, + "grid_x": 23, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X7Y184", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y184": "SLICEM", + "SLICE_X9Y184": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y185": { + "bits": {}, + "grid_x": 23, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X7Y185", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y185": "SLICEM", + "SLICE_X9Y185": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y186": { + "bits": {}, + "grid_x": 23, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X7Y186", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y186": "SLICEM", + "SLICE_X9Y186": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y187": { + "bits": {}, + "grid_x": 23, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X7Y187", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y187": "SLICEM", + "SLICE_X9Y187": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y188": { + "bits": {}, + "grid_x": 23, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X7Y188", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y188": "SLICEM", + "SLICE_X9Y188": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y189": { + "bits": {}, + "grid_x": 23, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X7Y189", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y189": "SLICEM", + "SLICE_X9Y189": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y19": { + "bits": {}, + "grid_x": 23, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X7Y19", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y19": "SLICEM", + "SLICE_X9Y19": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y190": { + "bits": {}, + "grid_x": 23, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X7Y190", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y190": "SLICEM", + "SLICE_X9Y190": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y191": { + "bits": {}, + "grid_x": 23, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X7Y191", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y191": "SLICEM", + "SLICE_X9Y191": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y192": { + "bits": {}, + "grid_x": 23, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X7Y192", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y192": "SLICEM", + "SLICE_X9Y192": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y193": { + "bits": {}, + "grid_x": 23, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X7Y193", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y193": "SLICEM", + "SLICE_X9Y193": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y194": { + "bits": {}, + "grid_x": 23, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X7Y194", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y194": "SLICEM", + "SLICE_X9Y194": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y195": { + "bits": {}, + "grid_x": 23, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X7Y195", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y195": "SLICEM", + "SLICE_X9Y195": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y196": { + "bits": {}, + "grid_x": 23, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X7Y196", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y196": "SLICEM", + "SLICE_X9Y196": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y197": { + "bits": {}, + "grid_x": 23, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X7Y197", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y197": "SLICEM", + "SLICE_X9Y197": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y198": { + "bits": {}, + "grid_x": 23, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X7Y198", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y198": "SLICEM", + "SLICE_X9Y198": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y199": { + "bits": {}, + "grid_x": 23, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X7Y199", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y199": "SLICEM", + "SLICE_X9Y199": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y2": { + "bits": {}, + "grid_x": 23, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X7Y2", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y2": "SLICEM", + "SLICE_X9Y2": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y20": { + "bits": {}, + "grid_x": 23, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X7Y20", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y20": "SLICEM", + "SLICE_X9Y20": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y21": { + "bits": {}, + "grid_x": 23, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X7Y21", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y21": "SLICEM", + "SLICE_X9Y21": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y22": { + "bits": {}, + "grid_x": 23, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X7Y22", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y22": "SLICEM", + "SLICE_X9Y22": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y23": { + "bits": {}, + "grid_x": 23, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X7Y23", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y23": "SLICEM", + "SLICE_X9Y23": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y24": { + "bits": {}, + "grid_x": 23, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X7Y24", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y24": "SLICEM", + "SLICE_X9Y24": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y25": { + "bits": {}, + "grid_x": 23, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X7Y25", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y25": "SLICEM", + "SLICE_X9Y25": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y26": { + "bits": {}, + "grid_x": 23, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X7Y26", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y26": "SLICEM", + "SLICE_X9Y26": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y27": { + "bits": {}, + "grid_x": 23, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X7Y27", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y27": "SLICEM", + "SLICE_X9Y27": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y28": { + "bits": {}, + "grid_x": 23, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X7Y28", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y28": "SLICEM", + "SLICE_X9Y28": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y29": { + "bits": {}, + "grid_x": 23, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X7Y29", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y29": "SLICEM", + "SLICE_X9Y29": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y3": { + "bits": {}, + "grid_x": 23, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X7Y3", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y3": "SLICEM", + "SLICE_X9Y3": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y30": { + "bits": {}, + "grid_x": 23, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X7Y30", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y30": "SLICEM", + "SLICE_X9Y30": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y31": { + "bits": {}, + "grid_x": 23, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X7Y31", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y31": "SLICEM", + "SLICE_X9Y31": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y32": { + "bits": {}, + "grid_x": 23, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X7Y32", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y32": "SLICEM", + "SLICE_X9Y32": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y33": { + "bits": {}, + "grid_x": 23, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X7Y33", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y33": "SLICEM", + "SLICE_X9Y33": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y34": { + "bits": {}, + "grid_x": 23, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X7Y34", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y34": "SLICEM", + "SLICE_X9Y34": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y35": { + "bits": {}, + "grid_x": 23, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X7Y35", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y35": "SLICEM", + "SLICE_X9Y35": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y36": { + "bits": {}, + "grid_x": 23, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X7Y36", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y36": "SLICEM", + "SLICE_X9Y36": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y37": { + "bits": {}, + "grid_x": 23, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X7Y37", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y37": "SLICEM", + "SLICE_X9Y37": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y38": { + "bits": {}, + "grid_x": 23, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X7Y38", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y38": "SLICEM", + "SLICE_X9Y38": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y39": { + "bits": {}, + "grid_x": 23, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X7Y39", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y39": "SLICEM", + "SLICE_X9Y39": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y4": { + "bits": {}, + "grid_x": 23, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X7Y4", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y4": "SLICEM", + "SLICE_X9Y4": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y40": { + "bits": {}, + "grid_x": 23, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X7Y40", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y40": "SLICEM", + "SLICE_X9Y40": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y41": { + "bits": {}, + "grid_x": 23, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X7Y41", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y41": "SLICEM", + "SLICE_X9Y41": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y42": { + "bits": {}, + "grid_x": 23, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X7Y42", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y42": "SLICEM", + "SLICE_X9Y42": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y43": { + "bits": {}, + "grid_x": 23, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X7Y43", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y43": "SLICEM", + "SLICE_X9Y43": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y44": { + "bits": {}, + "grid_x": 23, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X7Y44", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y44": "SLICEM", + "SLICE_X9Y44": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y45": { + "bits": {}, + "grid_x": 23, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X7Y45", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y45": "SLICEM", + "SLICE_X9Y45": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y46": { + "bits": {}, + "grid_x": 23, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X7Y46", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y46": "SLICEM", + "SLICE_X9Y46": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y47": { + "bits": {}, + "grid_x": 23, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X7Y47", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y47": "SLICEM", + "SLICE_X9Y47": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y48": { + "bits": {}, + "grid_x": 23, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X7Y48", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y48": "SLICEM", + "SLICE_X9Y48": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y49": { + "bits": {}, + "grid_x": 23, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X7Y49", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y49": "SLICEM", + "SLICE_X9Y49": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y5": { + "bits": {}, + "grid_x": 23, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X7Y5", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y5": "SLICEM", + "SLICE_X9Y5": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X7Y50", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y50": "SLICEM", + "SLICE_X9Y50": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X7Y51", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y51": "SLICEM", + "SLICE_X9Y51": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X7Y52", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y52": "SLICEM", + "SLICE_X9Y52": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X7Y53", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y53": "SLICEM", + "SLICE_X9Y53": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X7Y54", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y54": "SLICEM", + "SLICE_X9Y54": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X7Y55", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y55": "SLICEM", + "SLICE_X9Y55": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X7Y56", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y56": "SLICEM", + "SLICE_X9Y56": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X7Y57", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y57": "SLICEM", + "SLICE_X9Y57": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X7Y58", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y58": "SLICEM", + "SLICE_X9Y58": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X7Y59", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y59": "SLICEM", + "SLICE_X9Y59": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y6": { + "bits": {}, + "grid_x": 23, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X7Y6", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y6": "SLICEM", + "SLICE_X9Y6": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X7Y60", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y60": "SLICEM", + "SLICE_X9Y60": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X7Y61", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y61": "SLICEM", + "SLICE_X9Y61": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X7Y62", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y62": "SLICEM", + "SLICE_X9Y62": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X7Y63", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y63": "SLICEM", + "SLICE_X9Y63": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X7Y64", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y64": "SLICEM", + "SLICE_X9Y64": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X7Y65", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y65": "SLICEM", + "SLICE_X9Y65": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X7Y66", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y66": "SLICEM", + "SLICE_X9Y66": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X7Y67", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y67": "SLICEM", + "SLICE_X9Y67": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X7Y68", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y68": "SLICEM", + "SLICE_X9Y68": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X7Y69", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y69": "SLICEM", + "SLICE_X9Y69": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y7": { + "bits": {}, + "grid_x": 23, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X7Y7", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y7": "SLICEM", + "SLICE_X9Y7": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X7Y70", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y70": "SLICEM", + "SLICE_X9Y70": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X7Y71", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y71": "SLICEM", + "SLICE_X9Y71": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X7Y72", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y72": "SLICEM", + "SLICE_X9Y72": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X7Y73", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y73": "SLICEM", + "SLICE_X9Y73": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X7Y74", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y74": "SLICEM", + "SLICE_X9Y74": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X7Y75", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y75": "SLICEM", + "SLICE_X9Y75": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X7Y76", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y76": "SLICEM", + "SLICE_X9Y76": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X7Y77", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y77": "SLICEM", + "SLICE_X9Y77": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X7Y78", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y78": "SLICEM", + "SLICE_X9Y78": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X7Y79", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y79": "SLICEM", + "SLICE_X9Y79": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y8": { + "bits": {}, + "grid_x": 23, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X7Y8", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y8": "SLICEM", + "SLICE_X9Y8": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X7Y80", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y80": "SLICEM", + "SLICE_X9Y80": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X7Y81", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y81": "SLICEM", + "SLICE_X9Y81": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X7Y82", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y82": "SLICEM", + "SLICE_X9Y82": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X7Y83", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y83": "SLICEM", + "SLICE_X9Y83": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X7Y84", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y84": "SLICEM", + "SLICE_X9Y84": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X7Y85", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y85": "SLICEM", + "SLICE_X9Y85": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X7Y86", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y86": "SLICEM", + "SLICE_X9Y86": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X7Y87", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y87": "SLICEM", + "SLICE_X9Y87": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X7Y88", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y88": "SLICEM", + "SLICE_X9Y88": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X7Y89", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y89": "SLICEM", + "SLICE_X9Y89": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y9": { + "bits": {}, + "grid_x": 23, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X7Y9", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y9": "SLICEM", + "SLICE_X9Y9": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X7Y90", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y90": "SLICEM", + "SLICE_X9Y90": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X7Y91", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y91": "SLICEM", + "SLICE_X9Y91": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X7Y92", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y92": "SLICEM", + "SLICE_X9Y92": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X7Y93", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y93": "SLICEM", + "SLICE_X9Y93": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X7Y94", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y94": "SLICEM", + "SLICE_X9Y94": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X7Y95", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y95": "SLICEM", + "SLICE_X9Y95": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X7Y96", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y96": "SLICEM", + "SLICE_X9Y96": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X7Y97", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y97": "SLICEM", + "SLICE_X9Y97": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X7Y98", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y98": "SLICEM", + "SLICE_X9Y98": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 36, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 23, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X7Y99", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y99": "SLICEM", + "SLICE_X9Y99": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLK_BUFG_BOT_R_X67Y100": { + "bits": {}, + "grid_x": 67, + "grid_y": 108, + "sites": { + "BUFGCTRL_X0Y0": "BUFGCTRL", + "BUFGCTRL_X0Y1": "BUFGCTRL", + "BUFGCTRL_X0Y10": "BUFGCTRL", + "BUFGCTRL_X0Y11": "BUFGCTRL", + "BUFGCTRL_X0Y12": "BUFGCTRL", + "BUFGCTRL_X0Y13": "BUFGCTRL", + "BUFGCTRL_X0Y14": "BUFGCTRL", + "BUFGCTRL_X0Y15": "BUFGCTRL", + "BUFGCTRL_X0Y2": "BUFGCTRL", + "BUFGCTRL_X0Y3": "BUFGCTRL", + "BUFGCTRL_X0Y4": "BUFGCTRL", + "BUFGCTRL_X0Y5": "BUFGCTRL", + "BUFGCTRL_X0Y6": "BUFGCTRL", + "BUFGCTRL_X0Y7": "BUFGCTRL", + "BUFGCTRL_X0Y8": "BUFGCTRL", + "BUFGCTRL_X0Y9": "BUFGCTRL" + }, + "type": "CLK_BUFG_BOT_R" + }, + "CLK_BUFG_REBUF_X67Y117": { + "bits": {}, + "grid_x": 67, + "grid_y": 91, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_REBUF_X67Y13": { + "bits": {}, + "grid_x": 67, + "grid_y": 195, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_REBUF_X67Y142": { + "bits": {}, + "grid_x": 67, + "grid_y": 66, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_REBUF_X67Y169": { + "bits": {}, + "grid_x": 67, + "grid_y": 39, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_REBUF_X67Y194": { + "bits": {}, + "grid_x": 67, + "grid_y": 14, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_REBUF_X67Y38": { + "bits": {}, + "grid_x": 67, + "grid_y": 170, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_REBUF_X67Y65": { + "bits": {}, + "grid_x": 67, + "grid_y": 143, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_REBUF_X67Y90": { + "bits": {}, + "grid_x": 67, + "grid_y": 118, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_TOP_R_X67Y105": { + "bits": {}, + "grid_x": 67, + "grid_y": 103, + "sites": { + "BUFGCTRL_X0Y16": "BUFGCTRL", + "BUFGCTRL_X0Y17": "BUFGCTRL", + "BUFGCTRL_X0Y18": "BUFGCTRL", + "BUFGCTRL_X0Y19": "BUFGCTRL", + "BUFGCTRL_X0Y20": "BUFGCTRL", + "BUFGCTRL_X0Y21": "BUFGCTRL", + "BUFGCTRL_X0Y22": "BUFGCTRL", + "BUFGCTRL_X0Y23": "BUFGCTRL", + "BUFGCTRL_X0Y24": "BUFGCTRL", + "BUFGCTRL_X0Y25": "BUFGCTRL", + "BUFGCTRL_X0Y26": "BUFGCTRL", + "BUFGCTRL_X0Y27": "BUFGCTRL", + "BUFGCTRL_X0Y28": "BUFGCTRL", + "BUFGCTRL_X0Y29": "BUFGCTRL", + "BUFGCTRL_X0Y30": "BUFGCTRL", + "BUFGCTRL_X0Y31": "BUFGCTRL" + }, + "type": "CLK_BUFG_TOP_R" + }, + "CLK_FEED_X67Y1": { + "bits": {}, + "grid_x": 67, + "grid_y": 207, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y10": { + "bits": {}, + "grid_x": 67, + "grid_y": 198, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y109": { + "bits": {}, + "grid_x": 67, + "grid_y": 99, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y11": { + "bits": {}, + "grid_x": 67, + "grid_y": 197, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y110": { + "bits": {}, + "grid_x": 67, + "grid_y": 98, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y111": { + "bits": {}, + "grid_x": 67, + "grid_y": 97, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y112": { + "bits": {}, + "grid_x": 67, + "grid_y": 96, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y113": { + "bits": {}, + "grid_x": 67, + "grid_y": 95, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y114": { + "bits": {}, + "grid_x": 67, + "grid_y": 94, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y115": { + "bits": {}, + "grid_x": 67, + "grid_y": 93, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y116": { + "bits": {}, + "grid_x": 67, + "grid_y": 92, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y119": { + "bits": {}, + "grid_x": 67, + "grid_y": 89, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y12": { + "bits": {}, + "grid_x": 67, + "grid_y": 196, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y120": { + "bits": {}, + "grid_x": 67, + "grid_y": 88, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y121": { + "bits": {}, + "grid_x": 67, + "grid_y": 87, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y122": { + "bits": {}, + "grid_x": 67, + "grid_y": 86, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y123": { + "bits": {}, + "grid_x": 67, + "grid_y": 85, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y124": { + "bits": {}, + "grid_x": 67, + "grid_y": 84, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y125": { + "bits": {}, + "grid_x": 67, + "grid_y": 83, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y135": { + "bits": {}, + "grid_x": 67, + "grid_y": 73, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y136": { + "bits": {}, + "grid_x": 67, + "grid_y": 72, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y137": { + "bits": {}, + "grid_x": 67, + "grid_y": 71, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y138": { + "bits": {}, + "grid_x": 67, + "grid_y": 70, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y139": { + "bits": {}, + "grid_x": 67, + "grid_y": 69, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y140": { + "bits": {}, + "grid_x": 67, + "grid_y": 68, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y141": { + "bits": {}, + "grid_x": 67, + "grid_y": 67, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y144": { + "bits": {}, + "grid_x": 67, + "grid_y": 64, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y145": { + "bits": {}, + "grid_x": 67, + "grid_y": 63, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y146": { + "bits": {}, + "grid_x": 67, + "grid_y": 62, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y147": { + "bits": {}, + "grid_x": 67, + "grid_y": 61, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y148": { + "bits": {}, + "grid_x": 67, + "grid_y": 60, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y149": { + "bits": {}, + "grid_x": 67, + "grid_y": 59, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y15": { + "bits": {}, + "grid_x": 67, + "grid_y": 193, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y150": { + "bits": {}, + "grid_x": 67, + "grid_y": 58, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y151": { + "bits": {}, + "grid_x": 67, + "grid_y": 57, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y152": { + "bits": {}, + "grid_x": 67, + "grid_y": 56, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y153": { + "bits": {}, + "grid_x": 67, + "grid_y": 55, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y154": { + "bits": {}, + "grid_x": 67, + "grid_y": 54, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y155": { + "bits": {}, + "grid_x": 67, + "grid_y": 53, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y157": { + "bits": {}, + "grid_x": 67, + "grid_y": 51, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y158": { + "bits": {}, + "grid_x": 67, + "grid_y": 50, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y159": { + "bits": {}, + "grid_x": 67, + "grid_y": 49, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y16": { + "bits": {}, + "grid_x": 67, + "grid_y": 192, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y160": { + "bits": {}, + "grid_x": 67, + "grid_y": 48, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y161": { + "bits": {}, + "grid_x": 67, + "grid_y": 47, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y162": { + "bits": {}, + "grid_x": 67, + "grid_y": 46, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y163": { + "bits": {}, + "grid_x": 67, + "grid_y": 45, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y164": { + "bits": {}, + "grid_x": 67, + "grid_y": 44, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y165": { + "bits": {}, + "grid_x": 67, + "grid_y": 43, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y166": { + "bits": {}, + "grid_x": 67, + "grid_y": 42, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y167": { + "bits": {}, + "grid_x": 67, + "grid_y": 41, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y168": { + "bits": {}, + "grid_x": 67, + "grid_y": 40, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y17": { + "bits": {}, + "grid_x": 67, + "grid_y": 191, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y171": { + "bits": {}, + "grid_x": 67, + "grid_y": 37, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y172": { + "bits": {}, + "grid_x": 67, + "grid_y": 36, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y173": { + "bits": {}, + "grid_x": 67, + "grid_y": 35, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y174": { + "bits": {}, + "grid_x": 67, + "grid_y": 34, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y175": { + "bits": {}, + "grid_x": 67, + "grid_y": 33, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y176": { + "bits": {}, + "grid_x": 67, + "grid_y": 32, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y177": { + "bits": {}, + "grid_x": 67, + "grid_y": 31, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y18": { + "bits": {}, + "grid_x": 67, + "grid_y": 190, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y187": { + "bits": {}, + "grid_x": 67, + "grid_y": 21, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y188": { + "bits": {}, + "grid_x": 67, + "grid_y": 20, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y189": { + "bits": {}, + "grid_x": 67, + "grid_y": 19, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y19": { + "bits": {}, + "grid_x": 67, + "grid_y": 189, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y190": { + "bits": {}, + "grid_x": 67, + "grid_y": 18, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y191": { + "bits": {}, + "grid_x": 67, + "grid_y": 17, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y192": { + "bits": {}, + "grid_x": 67, + "grid_y": 16, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y193": { + "bits": {}, + "grid_x": 67, + "grid_y": 15, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y196": { + "bits": {}, + "grid_x": 67, + "grid_y": 12, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y197": { + "bits": {}, + "grid_x": 67, + "grid_y": 11, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y198": { + "bits": {}, + "grid_x": 67, + "grid_y": 10, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y199": { + "bits": {}, + "grid_x": 67, + "grid_y": 9, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y2": { + "bits": {}, + "grid_x": 67, + "grid_y": 206, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y20": { + "bits": {}, + "grid_x": 67, + "grid_y": 188, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y200": { + "bits": {}, + "grid_x": 67, + "grid_y": 8, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y201": { + "bits": {}, + "grid_x": 67, + "grid_y": 7, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y202": { + "bits": {}, + "grid_x": 67, + "grid_y": 6, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y203": { + "bits": {}, + "grid_x": 67, + "grid_y": 5, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y204": { + "bits": {}, + "grid_x": 67, + "grid_y": 4, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y205": { + "bits": {}, + "grid_x": 67, + "grid_y": 3, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y206": { + "bits": {}, + "grid_x": 67, + "grid_y": 2, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y207": { + "bits": {}, + "grid_x": 67, + "grid_y": 1, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y21": { + "bits": {}, + "grid_x": 67, + "grid_y": 187, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y3": { + "bits": {}, + "grid_x": 67, + "grid_y": 205, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y31": { + "bits": {}, + "grid_x": 67, + "grid_y": 177, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y32": { + "bits": {}, + "grid_x": 67, + "grid_y": 176, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y33": { + "bits": {}, + "grid_x": 67, + "grid_y": 175, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y34": { + "bits": {}, + "grid_x": 67, + "grid_y": 174, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y35": { + "bits": {}, + "grid_x": 67, + "grid_y": 173, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y36": { + "bits": {}, + "grid_x": 67, + "grid_y": 172, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y37": { + "bits": {}, + "grid_x": 67, + "grid_y": 171, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y4": { + "bits": {}, + "grid_x": 67, + "grid_y": 204, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y40": { + "bits": {}, + "grid_x": 67, + "grid_y": 168, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y41": { + "bits": {}, + "grid_x": 67, + "grid_y": 167, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y42": { + "bits": {}, + "grid_x": 67, + "grid_y": 166, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y43": { + "bits": {}, + "grid_x": 67, + "grid_y": 165, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y44": { + "bits": {}, + "grid_x": 67, + "grid_y": 164, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y45": { + "bits": {}, + "grid_x": 67, + "grid_y": 163, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y46": { + "bits": {}, + "grid_x": 67, + "grid_y": 162, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y47": { + "bits": {}, + "grid_x": 67, + "grid_y": 161, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y48": { + "bits": {}, + "grid_x": 67, + "grid_y": 160, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y49": { + "bits": {}, + "grid_x": 67, + "grid_y": 159, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y5": { + "bits": {}, + "grid_x": 67, + "grid_y": 203, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y50": { + "bits": {}, + "grid_x": 67, + "grid_y": 158, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y51": { + "bits": {}, + "grid_x": 67, + "grid_y": 157, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y53": { + "bits": {}, + "grid_x": 67, + "grid_y": 155, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y6": { + "bits": {}, + "grid_x": 67, + "grid_y": 202, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y61": { + "bits": {}, + "grid_x": 67, + "grid_y": 147, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y62": { + "bits": {}, + "grid_x": 67, + "grid_y": 146, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y63": { + "bits": {}, + "grid_x": 67, + "grid_y": 145, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y64": { + "bits": {}, + "grid_x": 67, + "grid_y": 144, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y67": { + "bits": {}, + "grid_x": 67, + "grid_y": 141, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y68": { + "bits": {}, + "grid_x": 67, + "grid_y": 140, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y69": { + "bits": {}, + "grid_x": 67, + "grid_y": 139, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y7": { + "bits": {}, + "grid_x": 67, + "grid_y": 201, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y71": { + "bits": {}, + "grid_x": 67, + "grid_y": 137, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y72": { + "bits": {}, + "grid_x": 67, + "grid_y": 136, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y73": { + "bits": {}, + "grid_x": 67, + "grid_y": 135, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y8": { + "bits": {}, + "grid_x": 67, + "grid_y": 200, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y83": { + "bits": {}, + "grid_x": 67, + "grid_y": 125, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y84": { + "bits": {}, + "grid_x": 67, + "grid_y": 124, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y85": { + "bits": {}, + "grid_x": 67, + "grid_y": 123, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y87": { + "bits": {}, + "grid_x": 67, + "grid_y": 121, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y88": { + "bits": {}, + "grid_x": 67, + "grid_y": 120, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y89": { + "bits": {}, + "grid_x": 67, + "grid_y": 119, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y9": { + "bits": {}, + "grid_x": 67, + "grid_y": 199, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y92": { + "bits": {}, + "grid_x": 67, + "grid_y": 116, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y93": { + "bits": {}, + "grid_x": 67, + "grid_y": 115, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y94": { + "bits": {}, + "grid_x": 67, + "grid_y": 114, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y96": { + "bits": {}, + "grid_x": 67, + "grid_y": 112, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y97": { + "bits": {}, + "grid_x": 67, + "grid_y": 111, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X67Y98": { + "bits": {}, + "grid_x": 67, + "grid_y": 110, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_HROW_BOT_R_X67Y26": { + "bits": {}, + "grid_x": 67, + "grid_y": 182, + "sites": { + "BUFHCE_X0Y0": "BUFHCE", + "BUFHCE_X0Y1": "BUFHCE", + "BUFHCE_X0Y10": "BUFHCE", + "BUFHCE_X0Y11": "BUFHCE", + "BUFHCE_X0Y2": "BUFHCE", + "BUFHCE_X0Y3": "BUFHCE", + "BUFHCE_X0Y4": "BUFHCE", + "BUFHCE_X0Y5": "BUFHCE", + "BUFHCE_X0Y6": "BUFHCE", + "BUFHCE_X0Y7": "BUFHCE", + "BUFHCE_X0Y8": "BUFHCE", + "BUFHCE_X0Y9": "BUFHCE", + "BUFHCE_X1Y0": "BUFHCE", + "BUFHCE_X1Y1": "BUFHCE", + "BUFHCE_X1Y10": "BUFHCE", + "BUFHCE_X1Y11": "BUFHCE", + "BUFHCE_X1Y2": "BUFHCE", + "BUFHCE_X1Y3": "BUFHCE", + "BUFHCE_X1Y4": "BUFHCE", + "BUFHCE_X1Y5": "BUFHCE", + "BUFHCE_X1Y6": "BUFHCE", + "BUFHCE_X1Y7": "BUFHCE", + "BUFHCE_X1Y8": "BUFHCE", + "BUFHCE_X1Y9": "BUFHCE" + }, + "type": "CLK_HROW_BOT_R" + }, + "CLK_HROW_BOT_R_X67Y78": { + "bits": {}, + "grid_x": 67, + "grid_y": 130, + "sites": { + "BUFHCE_X0Y12": "BUFHCE", + "BUFHCE_X0Y13": "BUFHCE", + "BUFHCE_X0Y14": "BUFHCE", + "BUFHCE_X0Y15": "BUFHCE", + "BUFHCE_X0Y16": "BUFHCE", + "BUFHCE_X0Y17": "BUFHCE", + "BUFHCE_X0Y18": "BUFHCE", + "BUFHCE_X0Y19": "BUFHCE", + "BUFHCE_X0Y20": "BUFHCE", + "BUFHCE_X0Y21": "BUFHCE", + "BUFHCE_X0Y22": "BUFHCE", + "BUFHCE_X0Y23": "BUFHCE", + "BUFHCE_X1Y12": "BUFHCE", + "BUFHCE_X1Y13": "BUFHCE", + "BUFHCE_X1Y14": "BUFHCE", + "BUFHCE_X1Y15": "BUFHCE", + "BUFHCE_X1Y16": "BUFHCE", + "BUFHCE_X1Y17": "BUFHCE", + "BUFHCE_X1Y18": "BUFHCE", + "BUFHCE_X1Y19": "BUFHCE", + "BUFHCE_X1Y20": "BUFHCE", + "BUFHCE_X1Y21": "BUFHCE", + "BUFHCE_X1Y22": "BUFHCE", + "BUFHCE_X1Y23": "BUFHCE" + }, + "type": "CLK_HROW_BOT_R" + }, + "CLK_HROW_TOP_R_X67Y130": { + "bits": {}, + "grid_x": 67, + "grid_y": 78, + "sites": { + "BUFHCE_X0Y24": "BUFHCE", + "BUFHCE_X0Y25": "BUFHCE", + "BUFHCE_X0Y26": "BUFHCE", + "BUFHCE_X0Y27": "BUFHCE", + "BUFHCE_X0Y28": "BUFHCE", + "BUFHCE_X0Y29": "BUFHCE", + "BUFHCE_X0Y30": "BUFHCE", + "BUFHCE_X0Y31": "BUFHCE", + "BUFHCE_X0Y32": "BUFHCE", + "BUFHCE_X0Y33": "BUFHCE", + "BUFHCE_X0Y34": "BUFHCE", + "BUFHCE_X0Y35": "BUFHCE", + "BUFHCE_X1Y24": "BUFHCE", + "BUFHCE_X1Y25": "BUFHCE", + "BUFHCE_X1Y26": "BUFHCE", + "BUFHCE_X1Y27": "BUFHCE", + "BUFHCE_X1Y28": "BUFHCE", + "BUFHCE_X1Y29": "BUFHCE", + "BUFHCE_X1Y30": "BUFHCE", + "BUFHCE_X1Y31": "BUFHCE", + "BUFHCE_X1Y32": "BUFHCE", + "BUFHCE_X1Y33": "BUFHCE", + "BUFHCE_X1Y34": "BUFHCE", + "BUFHCE_X1Y35": "BUFHCE" + }, + "type": "CLK_HROW_TOP_R" + }, + "CLK_HROW_TOP_R_X67Y182": { + "bits": {}, + "grid_x": 67, + "grid_y": 26, + "sites": { + "BUFHCE_X0Y36": "BUFHCE", + "BUFHCE_X0Y37": "BUFHCE", + "BUFHCE_X0Y38": "BUFHCE", + "BUFHCE_X0Y39": "BUFHCE", + "BUFHCE_X0Y40": "BUFHCE", + "BUFHCE_X0Y41": "BUFHCE", + "BUFHCE_X0Y42": "BUFHCE", + "BUFHCE_X0Y43": "BUFHCE", + "BUFHCE_X0Y44": "BUFHCE", + "BUFHCE_X0Y45": "BUFHCE", + "BUFHCE_X0Y46": "BUFHCE", + "BUFHCE_X0Y47": "BUFHCE", + "BUFHCE_X1Y36": "BUFHCE", + "BUFHCE_X1Y37": "BUFHCE", + "BUFHCE_X1Y38": "BUFHCE", + "BUFHCE_X1Y39": "BUFHCE", + "BUFHCE_X1Y40": "BUFHCE", + "BUFHCE_X1Y41": "BUFHCE", + "BUFHCE_X1Y42": "BUFHCE", + "BUFHCE_X1Y43": "BUFHCE", + "BUFHCE_X1Y44": "BUFHCE", + "BUFHCE_X1Y45": "BUFHCE", + "BUFHCE_X1Y46": "BUFHCE", + "BUFHCE_X1Y47": "BUFHCE" + }, + "type": "CLK_HROW_TOP_R" + }, + "CLK_MTBF2_X67Y99": { + "bits": {}, + "grid_x": 67, + "grid_y": 109, + "sites": {}, + "type": "CLK_MTBF2" + }, + "CLK_PMV2_SVT_X67Y86": { + "bits": {}, + "grid_x": 67, + "grid_y": 122, + "sites": {}, + "type": "CLK_PMV2_SVT" + }, + "CLK_PMV2_X67Y95": { + "bits": {}, + "grid_x": 67, + "grid_y": 113, + "sites": { + "PMV_X0Y2": "PMV2" + }, + "type": "CLK_PMV2" + }, + "CLK_PMVIOB_X67Y70": { + "bits": {}, + "grid_x": 67, + "grid_y": 138, + "sites": {}, + "type": "CLK_PMVIOB" + }, + "CLK_PMV_X67Y54": { + "bits": {}, + "grid_x": 67, + "grid_y": 154, + "sites": {}, + "type": "CLK_PMV" + }, + "CLK_TERM_X67Y0": { + "bits": {}, + "grid_x": 67, + "grid_y": 208, + "sites": {}, + "type": "CLK_TERM" + }, + "CLK_TERM_X67Y208": { + "bits": {}, + "grid_x": 67, + "grid_y": 0, + "sites": {}, + "type": "CLK_TERM" + }, + "CMT_FIFO_L_X109Y20": { + "bits": {}, + "grid_x": 109, + "grid_y": 188, + "sites": { + "IN_FIFO_X1Y1": "IN_FIFO", + "OUT_FIFO_X1Y1": "OUT_FIFO" + }, + "type": "CMT_FIFO_L" + }, + "CMT_FIFO_L_X109Y33": { + "bits": {}, + "grid_x": 109, + "grid_y": 175, + "sites": { + "IN_FIFO_X1Y2": "IN_FIFO", + "OUT_FIFO_X1Y2": "OUT_FIFO" + }, + "type": "CMT_FIFO_L" + }, + "CMT_FIFO_L_X109Y45": { + "bits": {}, + "grid_x": 109, + "grid_y": 163, + "sites": { + "IN_FIFO_X1Y3": "IN_FIFO", + "OUT_FIFO_X1Y3": "OUT_FIFO" + }, + "type": "CMT_FIFO_L" + }, + "CMT_FIFO_L_X109Y60": { + "bits": {}, + "grid_x": 109, + "grid_y": 148, + "sites": { + "IN_FIFO_X1Y4": "IN_FIFO", + "OUT_FIFO_X1Y4": "OUT_FIFO" + }, + "type": "CMT_FIFO_L" + }, + "CMT_FIFO_L_X109Y72": { + "bits": {}, + "grid_x": 109, + "grid_y": 136, + "sites": { + "IN_FIFO_X1Y5": "IN_FIFO", + "OUT_FIFO_X1Y5": "OUT_FIFO" + }, + "type": "CMT_FIFO_L" + }, + "CMT_FIFO_L_X109Y8": { + "bits": {}, + "grid_x": 109, + "grid_y": 200, + "sites": { + "IN_FIFO_X1Y0": "IN_FIFO", + "OUT_FIFO_X1Y0": "OUT_FIFO" + }, + "type": "CMT_FIFO_L" + }, + "CMT_FIFO_L_X109Y85": { + "bits": {}, + "grid_x": 109, + "grid_y": 123, + "sites": { + "IN_FIFO_X1Y6": "IN_FIFO", + "OUT_FIFO_X1Y6": "OUT_FIFO" + }, + "type": "CMT_FIFO_L" + }, + "CMT_FIFO_L_X109Y97": { + "bits": {}, + "grid_x": 109, + "grid_y": 111, + "sites": { + "IN_FIFO_X1Y7": "IN_FIFO", + "OUT_FIFO_X1Y7": "OUT_FIFO" + }, + "type": "CMT_FIFO_L" + }, + "CMT_FIFO_R_X7Y112": { + "bits": {}, + "grid_x": 7, + "grid_y": 96, + "sites": { + "IN_FIFO_X0Y8": "IN_FIFO", + "OUT_FIFO_X0Y8": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y124": { + "bits": {}, + "grid_x": 7, + "grid_y": 84, + "sites": { + "IN_FIFO_X0Y9": "IN_FIFO", + "OUT_FIFO_X0Y9": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y137": { + "bits": {}, + "grid_x": 7, + "grid_y": 71, + "sites": { + "IN_FIFO_X0Y10": "IN_FIFO", + "OUT_FIFO_X0Y10": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y149": { + "bits": {}, + "grid_x": 7, + "grid_y": 59, + "sites": { + "IN_FIFO_X0Y11": "IN_FIFO", + "OUT_FIFO_X0Y11": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y164": { + "bits": {}, + "grid_x": 7, + "grid_y": 44, + "sites": { + "IN_FIFO_X0Y12": "IN_FIFO", + "OUT_FIFO_X0Y12": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y176": { + "bits": {}, + "grid_x": 7, + "grid_y": 32, + "sites": { + "IN_FIFO_X0Y13": "IN_FIFO", + "OUT_FIFO_X0Y13": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y189": { + "bits": {}, + "grid_x": 7, + "grid_y": 19, + "sites": { + "IN_FIFO_X0Y14": "IN_FIFO", + "OUT_FIFO_X0Y14": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y20": { + "bits": {}, + "grid_x": 7, + "grid_y": 188, + "sites": { + "IN_FIFO_X0Y1": "IN_FIFO", + "OUT_FIFO_X0Y1": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y201": { + "bits": {}, + "grid_x": 7, + "grid_y": 7, + "sites": { + "IN_FIFO_X0Y15": "IN_FIFO", + "OUT_FIFO_X0Y15": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y33": { + "bits": {}, + "grid_x": 7, + "grid_y": 175, + "sites": { + "IN_FIFO_X0Y2": "IN_FIFO", + "OUT_FIFO_X0Y2": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y45": { + "bits": {}, + "grid_x": 7, + "grid_y": 163, + "sites": { + "IN_FIFO_X0Y3": "IN_FIFO", + "OUT_FIFO_X0Y3": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y60": { + "bits": {}, + "grid_x": 7, + "grid_y": 148, + "sites": { + "IN_FIFO_X0Y4": "IN_FIFO", + "OUT_FIFO_X0Y4": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y72": { + "bits": {}, + "grid_x": 7, + "grid_y": 136, + "sites": { + "IN_FIFO_X0Y5": "IN_FIFO", + "OUT_FIFO_X0Y5": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y8": { + "bits": {}, + "grid_x": 7, + "grid_y": 200, + "sites": { + "IN_FIFO_X0Y0": "IN_FIFO", + "OUT_FIFO_X0Y0": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y85": { + "bits": {}, + "grid_x": 7, + "grid_y": 123, + "sites": { + "IN_FIFO_X0Y6": "IN_FIFO", + "OUT_FIFO_X0Y6": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_FIFO_R_X7Y97": { + "bits": {}, + "grid_x": 7, + "grid_y": 111, + "sites": { + "IN_FIFO_X0Y7": "IN_FIFO", + "OUT_FIFO_X0Y7": "OUT_FIFO" + }, + "type": "CMT_FIFO_R" + }, + "CMT_PMV_L_X109Y1": { + "bits": {}, + "grid_x": 109, + "grid_y": 207, + "sites": {}, + "type": "CMT_PMV_L" + }, + "CMT_PMV_L_X109Y103": { + "bits": {}, + "grid_x": 109, + "grid_y": 105, + "sites": {}, + "type": "CMT_PMV_L" + }, + "CMT_PMV_L_X109Y51": { + "bits": {}, + "grid_x": 109, + "grid_y": 157, + "sites": {}, + "type": "CMT_PMV_L" + }, + "CMT_PMV_L_X109Y53": { + "bits": {}, + "grid_x": 109, + "grid_y": 155, + "sites": {}, + "type": "CMT_PMV_L" + }, + "CMT_PMV_X7Y1": { + "bits": {}, + "grid_x": 7, + "grid_y": 207, + "sites": {}, + "type": "CMT_PMV" + }, + "CMT_PMV_X7Y103": { + "bits": {}, + "grid_x": 7, + "grid_y": 105, + "sites": {}, + "type": "CMT_PMV" + }, + "CMT_PMV_X7Y105": { + "bits": {}, + "grid_x": 7, + "grid_y": 103, + "sites": {}, + "type": "CMT_PMV" + }, + "CMT_PMV_X7Y155": { + "bits": {}, + "grid_x": 7, + "grid_y": 53, + "sites": {}, + "type": "CMT_PMV" + }, + "CMT_PMV_X7Y157": { + "bits": {}, + "grid_x": 7, + "grid_y": 51, + "sites": {}, + "type": "CMT_PMV" + }, + "CMT_PMV_X7Y207": { + "bits": {}, + "grid_x": 7, + "grid_y": 1, + "sites": {}, + "type": "CMT_PMV" + }, + "CMT_PMV_X7Y51": { + "bits": {}, + "grid_x": 7, + "grid_y": 157, + "sites": {}, + "type": "CMT_PMV" + }, + "CMT_PMV_X7Y53": { + "bits": {}, + "grid_x": 7, + "grid_y": 155, + "sites": {}, + "type": "CMT_PMV" + }, + "CMT_TOP_L_LOWER_B_X108Y61": { + "bits": {}, + "grid_x": 108, + "grid_y": 147, + "sites": { + "MMCME2_ADV_X1Y1": "MMCME2_ADV" + }, + "type": "CMT_TOP_L_LOWER_B" + }, + "CMT_TOP_L_LOWER_B_X108Y9": { + "bits": {}, + "grid_x": 108, + "grid_y": 199, + "sites": { + "MMCME2_ADV_X1Y0": "MMCME2_ADV" + }, + "type": "CMT_TOP_L_LOWER_B" + }, + "CMT_TOP_L_LOWER_T_X108Y18": { + "bits": {}, + "grid_x": 108, + "grid_y": 190, + "sites": { + "PHASER_IN_PHY_X1Y0": "PHASER_IN_PHY", + "PHASER_IN_PHY_X1Y1": "PHASER_IN_PHY", + "PHASER_OUT_PHY_X1Y0": "PHASER_OUT_PHY", + "PHASER_OUT_PHY_X1Y1": "PHASER_OUT_PHY" + }, + "type": "CMT_TOP_L_LOWER_T" + }, + "CMT_TOP_L_LOWER_T_X108Y70": { + "bits": {}, + "grid_x": 108, + "grid_y": 138, + "sites": { + "PHASER_IN_PHY_X1Y4": "PHASER_IN_PHY", + "PHASER_IN_PHY_X1Y5": "PHASER_IN_PHY", + "PHASER_OUT_PHY_X1Y4": "PHASER_OUT_PHY", + "PHASER_OUT_PHY_X1Y5": "PHASER_OUT_PHY" + }, + "type": "CMT_TOP_L_LOWER_T" + }, + "CMT_TOP_L_UPPER_B_X108Y31": { + "bits": {}, + "grid_x": 108, + "grid_y": 177, + "sites": { + "PHASER_IN_PHY_X1Y2": "PHASER_IN_PHY", + "PHASER_IN_PHY_X1Y3": "PHASER_IN_PHY", + "PHASER_OUT_PHY_X1Y2": "PHASER_OUT_PHY", + "PHASER_OUT_PHY_X1Y3": "PHASER_OUT_PHY", + "PHASER_REF_X1Y0": "PHASER_REF", + "PHY_CONTROL_X1Y0": "PHY_CONTROL" + }, + "type": "CMT_TOP_L_UPPER_B" + }, + "CMT_TOP_L_UPPER_B_X108Y83": { + "bits": {}, + "grid_x": 108, + "grid_y": 125, + "sites": { + "PHASER_IN_PHY_X1Y6": "PHASER_IN_PHY", + "PHASER_IN_PHY_X1Y7": "PHASER_IN_PHY", + "PHASER_OUT_PHY_X1Y6": "PHASER_OUT_PHY", + "PHASER_OUT_PHY_X1Y7": "PHASER_OUT_PHY", + "PHASER_REF_X1Y1": "PHASER_REF", + "PHY_CONTROL_X1Y1": "PHY_CONTROL" + }, + "type": "CMT_TOP_L_UPPER_B" + }, + "CMT_TOP_L_UPPER_T_X108Y44": { + "bits": {}, + "grid_x": 108, + "grid_y": 164, + "sites": { + "PLLE2_ADV_X1Y0": "PLLE2_ADV" + }, + "type": "CMT_TOP_L_UPPER_T" + }, + "CMT_TOP_L_UPPER_T_X108Y96": { + "bits": {}, + "grid_x": 108, + "grid_y": 112, + "sites": { + "PLLE2_ADV_X1Y1": "PLLE2_ADV" + }, + "type": "CMT_TOP_L_UPPER_T" + }, + "CMT_TOP_R_LOWER_B_X8Y113": { + "bits": {}, + "grid_x": 8, + "grid_y": 95, + "sites": { + "MMCME2_ADV_X0Y2": "MMCME2_ADV" + }, + "type": "CMT_TOP_R_LOWER_B" + }, + "CMT_TOP_R_LOWER_B_X8Y165": { + "bits": {}, + "grid_x": 8, + "grid_y": 43, + "sites": { + "MMCME2_ADV_X0Y3": "MMCME2_ADV" + }, + "type": "CMT_TOP_R_LOWER_B" + }, + "CMT_TOP_R_LOWER_B_X8Y61": { + "bits": {}, + "grid_x": 8, + "grid_y": 147, + "sites": { + "MMCME2_ADV_X0Y1": "MMCME2_ADV" + }, + "type": "CMT_TOP_R_LOWER_B" + }, + "CMT_TOP_R_LOWER_B_X8Y9": { + "bits": {}, + "grid_x": 8, + "grid_y": 199, + "sites": { + "MMCME2_ADV_X0Y0": "MMCME2_ADV" + }, + "type": "CMT_TOP_R_LOWER_B" + }, + "CMT_TOP_R_LOWER_T_X8Y122": { + "bits": {}, + "grid_x": 8, + "grid_y": 86, + "sites": { + "PHASER_IN_PHY_X0Y8": "PHASER_IN_PHY", + "PHASER_IN_PHY_X0Y9": "PHASER_IN_PHY", + "PHASER_OUT_PHY_X0Y8": "PHASER_OUT_PHY", + "PHASER_OUT_PHY_X0Y9": "PHASER_OUT_PHY" + }, + "type": "CMT_TOP_R_LOWER_T" + }, + "CMT_TOP_R_LOWER_T_X8Y174": { + "bits": {}, + "grid_x": 8, + "grid_y": 34, + "sites": { + "PHASER_IN_PHY_X0Y12": "PHASER_IN_PHY", + "PHASER_IN_PHY_X0Y13": "PHASER_IN_PHY", + "PHASER_OUT_PHY_X0Y12": "PHASER_OUT_PHY", + "PHASER_OUT_PHY_X0Y13": "PHASER_OUT_PHY" + }, + "type": "CMT_TOP_R_LOWER_T" + }, + "CMT_TOP_R_LOWER_T_X8Y18": { + "bits": {}, + "grid_x": 8, + "grid_y": 190, + "sites": { + "PHASER_IN_PHY_X0Y0": "PHASER_IN_PHY", + "PHASER_IN_PHY_X0Y1": "PHASER_IN_PHY", + "PHASER_OUT_PHY_X0Y0": "PHASER_OUT_PHY", + "PHASER_OUT_PHY_X0Y1": "PHASER_OUT_PHY" + }, + "type": "CMT_TOP_R_LOWER_T" + }, + "CMT_TOP_R_LOWER_T_X8Y70": { + "bits": {}, + "grid_x": 8, + "grid_y": 138, + "sites": { + "PHASER_IN_PHY_X0Y4": "PHASER_IN_PHY", + "PHASER_IN_PHY_X0Y5": "PHASER_IN_PHY", + "PHASER_OUT_PHY_X0Y4": "PHASER_OUT_PHY", + "PHASER_OUT_PHY_X0Y5": "PHASER_OUT_PHY" + }, + "type": "CMT_TOP_R_LOWER_T" + }, + "CMT_TOP_R_UPPER_B_X8Y135": { + "bits": {}, + "grid_x": 8, + "grid_y": 73, + "sites": { + "PHASER_IN_PHY_X0Y10": "PHASER_IN_PHY", + "PHASER_IN_PHY_X0Y11": "PHASER_IN_PHY", + "PHASER_OUT_PHY_X0Y10": "PHASER_OUT_PHY", + "PHASER_OUT_PHY_X0Y11": "PHASER_OUT_PHY", + "PHASER_REF_X0Y2": "PHASER_REF", + "PHY_CONTROL_X0Y2": "PHY_CONTROL" + }, + "type": "CMT_TOP_R_UPPER_B" + }, + "CMT_TOP_R_UPPER_B_X8Y187": { + "bits": {}, + "grid_x": 8, + "grid_y": 21, + "sites": { + "PHASER_IN_PHY_X0Y14": "PHASER_IN_PHY", + "PHASER_IN_PHY_X0Y15": "PHASER_IN_PHY", + "PHASER_OUT_PHY_X0Y14": "PHASER_OUT_PHY", + "PHASER_OUT_PHY_X0Y15": "PHASER_OUT_PHY", + "PHASER_REF_X0Y3": "PHASER_REF", + "PHY_CONTROL_X0Y3": "PHY_CONTROL" + }, + "type": "CMT_TOP_R_UPPER_B" + }, + "CMT_TOP_R_UPPER_B_X8Y31": { + "bits": {}, + "grid_x": 8, + "grid_y": 177, + "sites": { + "PHASER_IN_PHY_X0Y2": "PHASER_IN_PHY", + "PHASER_IN_PHY_X0Y3": "PHASER_IN_PHY", + "PHASER_OUT_PHY_X0Y2": "PHASER_OUT_PHY", + "PHASER_OUT_PHY_X0Y3": "PHASER_OUT_PHY", + "PHASER_REF_X0Y0": "PHASER_REF", + "PHY_CONTROL_X0Y0": "PHY_CONTROL" + }, + "type": "CMT_TOP_R_UPPER_B" + }, + "CMT_TOP_R_UPPER_B_X8Y83": { + "bits": {}, + "grid_x": 8, + "grid_y": 125, + "sites": { + "PHASER_IN_PHY_X0Y6": "PHASER_IN_PHY", + "PHASER_IN_PHY_X0Y7": "PHASER_IN_PHY", + "PHASER_OUT_PHY_X0Y6": "PHASER_OUT_PHY", + "PHASER_OUT_PHY_X0Y7": "PHASER_OUT_PHY", + "PHASER_REF_X0Y1": "PHASER_REF", + "PHY_CONTROL_X0Y1": "PHY_CONTROL" + }, + "type": "CMT_TOP_R_UPPER_B" + }, + "CMT_TOP_R_UPPER_T_X8Y148": { + "bits": {}, + "grid_x": 8, + "grid_y": 60, + "sites": { + "PLLE2_ADV_X0Y2": "PLLE2_ADV" + }, + "type": "CMT_TOP_R_UPPER_T" + }, + "CMT_TOP_R_UPPER_T_X8Y200": { + "bits": {}, + "grid_x": 8, + "grid_y": 8, + "sites": { + "PLLE2_ADV_X0Y3": "PLLE2_ADV" + }, + "type": "CMT_TOP_R_UPPER_T" + }, + "CMT_TOP_R_UPPER_T_X8Y44": { + "bits": {}, + "grid_x": 8, + "grid_y": 164, + "sites": { + "PLLE2_ADV_X0Y0": "PLLE2_ADV" + }, + "type": "CMT_TOP_R_UPPER_T" + }, + "CMT_TOP_R_UPPER_T_X8Y96": { + "bits": {}, + "grid_x": 8, + "grid_y": 112, + "sites": { + "PLLE2_ADV_X0Y1": "PLLE2_ADV" + }, + "type": "CMT_TOP_R_UPPER_T" + }, + "DSP_L_X14Y0": { + "bits": {}, + "grid_x": 39, + "grid_y": 207, + "segment": "SEG_DSP0_L_X14Y0", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y0": "DSP48E1", + "DSP48_X1Y1": "DSP48E1", + "TIEOFF_X15Y0": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y10": { + "bits": {}, + "grid_x": 39, + "grid_y": 197, + "segment": "SEG_DSP0_L_X14Y10", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y4": "DSP48E1", + "DSP48_X1Y5": "DSP48E1", + "TIEOFF_X15Y10": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y100": { + "bits": {}, + "grid_x": 39, + "grid_y": 103, + "segment": "SEG_DSP0_L_X14Y100", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y40": "DSP48E1", + "DSP48_X1Y41": "DSP48E1", + "TIEOFF_X15Y100": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y105": { + "bits": {}, + "grid_x": 39, + "grid_y": 98, + "segment": "SEG_DSP0_L_X14Y105", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y42": "DSP48E1", + "DSP48_X1Y43": "DSP48E1", + "TIEOFF_X15Y105": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y110": { + "bits": {}, + "grid_x": 39, + "grid_y": 93, + "segment": "SEG_DSP0_L_X14Y110", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y44": "DSP48E1", + "DSP48_X1Y45": "DSP48E1", + "TIEOFF_X15Y110": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y115": { + "bits": {}, + "grid_x": 39, + "grid_y": 88, + "segment": "SEG_DSP0_L_X14Y115", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y46": "DSP48E1", + "DSP48_X1Y47": "DSP48E1", + "TIEOFF_X15Y115": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y120": { + "bits": {}, + "grid_x": 39, + "grid_y": 83, + "segment": "SEG_DSP0_L_X14Y120", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y48": "DSP48E1", + "DSP48_X1Y49": "DSP48E1", + "TIEOFF_X15Y120": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y125": { + "bits": {}, + "grid_x": 39, + "grid_y": 77, + "segment": "SEG_DSP0_L_X14Y125", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y50": "DSP48E1", + "DSP48_X1Y51": "DSP48E1", + "TIEOFF_X15Y125": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y130": { + "bits": {}, + "grid_x": 39, + "grid_y": 72, + "segment": "SEG_DSP0_L_X14Y130", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y52": "DSP48E1", + "DSP48_X1Y53": "DSP48E1", + "TIEOFF_X15Y130": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y135": { + "bits": {}, + "grid_x": 39, + "grid_y": 67, + "segment": "SEG_DSP0_L_X14Y135", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y54": "DSP48E1", + "DSP48_X1Y55": "DSP48E1", + "TIEOFF_X15Y135": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y140": { + "bits": {}, + "grid_x": 39, + "grid_y": 62, + "segment": "SEG_DSP0_L_X14Y140", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y56": "DSP48E1", + "DSP48_X1Y57": "DSP48E1", + "TIEOFF_X15Y140": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y145": { + "bits": {}, + "grid_x": 39, + "grid_y": 57, + "segment": "SEG_DSP0_L_X14Y145", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y58": "DSP48E1", + "DSP48_X1Y59": "DSP48E1", + "TIEOFF_X15Y145": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y15": { + "bits": {}, + "grid_x": 39, + "grid_y": 192, + "segment": "SEG_DSP0_L_X14Y15", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y6": "DSP48E1", + "DSP48_X1Y7": "DSP48E1", + "TIEOFF_X15Y15": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y150": { + "bits": {}, + "grid_x": 39, + "grid_y": 51, + "segment": "SEG_DSP0_L_X14Y150", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y60": "DSP48E1", + "DSP48_X1Y61": "DSP48E1", + "TIEOFF_X15Y150": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y155": { + "bits": {}, + "grid_x": 39, + "grid_y": 46, + "segment": "SEG_DSP0_L_X14Y155", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y62": "DSP48E1", + "DSP48_X1Y63": "DSP48E1", + "TIEOFF_X15Y155": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y160": { + "bits": {}, + "grid_x": 39, + "grid_y": 41, + "segment": "SEG_DSP0_L_X14Y160", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y64": "DSP48E1", + "DSP48_X1Y65": "DSP48E1", + "TIEOFF_X15Y160": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y165": { + "bits": {}, + "grid_x": 39, + "grid_y": 36, + "segment": "SEG_DSP0_L_X14Y165", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y66": "DSP48E1", + "DSP48_X1Y67": "DSP48E1", + "TIEOFF_X15Y165": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y170": { + "bits": {}, + "grid_x": 39, + "grid_y": 31, + "segment": "SEG_DSP0_L_X14Y170", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y68": "DSP48E1", + "DSP48_X1Y69": "DSP48E1", + "TIEOFF_X15Y170": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y175": { + "bits": {}, + "grid_x": 39, + "grid_y": 25, + "segment": "SEG_DSP0_L_X14Y175", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y70": "DSP48E1", + "DSP48_X1Y71": "DSP48E1", + "TIEOFF_X15Y175": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y180": { + "bits": {}, + "grid_x": 39, + "grid_y": 20, + "segment": "SEG_DSP0_L_X14Y180", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y72": "DSP48E1", + "DSP48_X1Y73": "DSP48E1", + "TIEOFF_X15Y180": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y185": { + "bits": {}, + "grid_x": 39, + "grid_y": 15, + "segment": "SEG_DSP0_L_X14Y185", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y74": "DSP48E1", + "DSP48_X1Y75": "DSP48E1", + "TIEOFF_X15Y185": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y190": { + "bits": {}, + "grid_x": 39, + "grid_y": 10, + "segment": "SEG_DSP0_L_X14Y190", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y76": "DSP48E1", + "DSP48_X1Y77": "DSP48E1", + "TIEOFF_X15Y190": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y195": { + "bits": {}, + "grid_x": 39, + "grid_y": 5, + "segment": "SEG_DSP0_L_X14Y195", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y78": "DSP48E1", + "DSP48_X1Y79": "DSP48E1", + "TIEOFF_X15Y195": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y20": { + "bits": {}, + "grid_x": 39, + "grid_y": 187, + "segment": "SEG_DSP0_L_X14Y20", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y8": "DSP48E1", + "DSP48_X1Y9": "DSP48E1", + "TIEOFF_X15Y20": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y25": { + "bits": {}, + "grid_x": 39, + "grid_y": 181, + "segment": "SEG_DSP0_L_X14Y25", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y10": "DSP48E1", + "DSP48_X1Y11": "DSP48E1", + "TIEOFF_X15Y25": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y30": { + "bits": {}, + "grid_x": 39, + "grid_y": 176, + "segment": "SEG_DSP0_L_X14Y30", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y12": "DSP48E1", + "DSP48_X1Y13": "DSP48E1", + "TIEOFF_X15Y30": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y35": { + "bits": {}, + "grid_x": 39, + "grid_y": 171, + "segment": "SEG_DSP0_L_X14Y35", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y14": "DSP48E1", + "DSP48_X1Y15": "DSP48E1", + "TIEOFF_X15Y35": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y40": { + "bits": {}, + "grid_x": 39, + "grid_y": 166, + "segment": "SEG_DSP0_L_X14Y40", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y16": "DSP48E1", + "DSP48_X1Y17": "DSP48E1", + "TIEOFF_X15Y40": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y45": { + "bits": {}, + "grid_x": 39, + "grid_y": 161, + "segment": "SEG_DSP0_L_X14Y45", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y18": "DSP48E1", + "DSP48_X1Y19": "DSP48E1", + "TIEOFF_X15Y45": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y5": { + "bits": {}, + "grid_x": 39, + "grid_y": 202, + "segment": "SEG_DSP0_L_X14Y5", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y2": "DSP48E1", + "DSP48_X1Y3": "DSP48E1", + "TIEOFF_X15Y5": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y50": { + "bits": {}, + "grid_x": 39, + "grid_y": 155, + "segment": "SEG_DSP0_L_X14Y50", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y20": "DSP48E1", + "DSP48_X1Y21": "DSP48E1", + "TIEOFF_X15Y50": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y55": { + "bits": {}, + "grid_x": 39, + "grid_y": 150, + "segment": "SEG_DSP0_L_X14Y55", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y22": "DSP48E1", + "DSP48_X1Y23": "DSP48E1", + "TIEOFF_X15Y55": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y60": { + "bits": {}, + "grid_x": 39, + "grid_y": 145, + "segment": "SEG_DSP0_L_X14Y60", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y24": "DSP48E1", + "DSP48_X1Y25": "DSP48E1", + "TIEOFF_X15Y60": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y65": { + "bits": {}, + "grid_x": 39, + "grid_y": 140, + "segment": "SEG_DSP0_L_X14Y65", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y26": "DSP48E1", + "DSP48_X1Y27": "DSP48E1", + "TIEOFF_X15Y65": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y70": { + "bits": {}, + "grid_x": 39, + "grid_y": 135, + "segment": "SEG_DSP0_L_X14Y70", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y28": "DSP48E1", + "DSP48_X1Y29": "DSP48E1", + "TIEOFF_X15Y70": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y75": { + "bits": {}, + "grid_x": 39, + "grid_y": 129, + "segment": "SEG_DSP0_L_X14Y75", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y30": "DSP48E1", + "DSP48_X1Y31": "DSP48E1", + "TIEOFF_X15Y75": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y80": { + "bits": {}, + "grid_x": 39, + "grid_y": 124, + "segment": "SEG_DSP0_L_X14Y80", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y32": "DSP48E1", + "DSP48_X1Y33": "DSP48E1", + "TIEOFF_X15Y80": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y85": { + "bits": {}, + "grid_x": 39, + "grid_y": 119, + "segment": "SEG_DSP0_L_X14Y85", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y34": "DSP48E1", + "DSP48_X1Y35": "DSP48E1", + "TIEOFF_X15Y85": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y90": { + "bits": {}, + "grid_x": 39, + "grid_y": 114, + "segment": "SEG_DSP0_L_X14Y90", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y36": "DSP48E1", + "DSP48_X1Y37": "DSP48E1", + "TIEOFF_X15Y90": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_L_X14Y95": { + "bits": {}, + "grid_x": 39, + "grid_y": 109, + "segment": "SEG_DSP0_L_X14Y95", + "segment_type": "dsp0_l", + "sites": { + "DSP48_X1Y38": "DSP48E1", + "DSP48_X1Y39": "DSP48E1", + "TIEOFF_X15Y95": "TIEOFF" + }, + "type": "DSP_L" + }, + "DSP_R_X33Y0": { + "bits": {}, + "grid_x": 87, + "grid_y": 207, + "segment": "SEG_DSP0_R_X33Y0", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y0": "DSP48E1", + "DSP48_X2Y1": "DSP48E1", + "TIEOFF_X36Y0": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y10": { + "bits": {}, + "grid_x": 87, + "grid_y": 197, + "segment": "SEG_DSP0_R_X33Y10", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y4": "DSP48E1", + "DSP48_X2Y5": "DSP48E1", + "TIEOFF_X36Y10": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y100": { + "bits": {}, + "grid_x": 87, + "grid_y": 103, + "segment": "SEG_DSP0_R_X33Y100", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y40": "DSP48E1", + "DSP48_X2Y41": "DSP48E1", + "TIEOFF_X36Y100": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y105": { + "bits": {}, + "grid_x": 87, + "grid_y": 98, + "segment": "SEG_DSP0_R_X33Y105", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y42": "DSP48E1", + "DSP48_X2Y43": "DSP48E1", + "TIEOFF_X36Y105": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y110": { + "bits": {}, + "grid_x": 87, + "grid_y": 93, + "segment": "SEG_DSP0_R_X33Y110", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y44": "DSP48E1", + "DSP48_X2Y45": "DSP48E1", + "TIEOFF_X36Y110": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y115": { + "bits": {}, + "grid_x": 87, + "grid_y": 88, + "segment": "SEG_DSP0_R_X33Y115", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y46": "DSP48E1", + "DSP48_X2Y47": "DSP48E1", + "TIEOFF_X36Y115": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y120": { + "bits": {}, + "grid_x": 87, + "grid_y": 83, + "segment": "SEG_DSP0_R_X33Y120", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y48": "DSP48E1", + "DSP48_X2Y49": "DSP48E1", + "TIEOFF_X36Y120": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y125": { + "bits": {}, + "grid_x": 87, + "grid_y": 77, + "segment": "SEG_DSP0_R_X33Y125", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y50": "DSP48E1", + "DSP48_X2Y51": "DSP48E1", + "TIEOFF_X36Y125": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y130": { + "bits": {}, + "grid_x": 87, + "grid_y": 72, + "segment": "SEG_DSP0_R_X33Y130", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y52": "DSP48E1", + "DSP48_X2Y53": "DSP48E1", + "TIEOFF_X36Y130": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y135": { + "bits": {}, + "grid_x": 87, + "grid_y": 67, + "segment": "SEG_DSP0_R_X33Y135", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y54": "DSP48E1", + "DSP48_X2Y55": "DSP48E1", + "TIEOFF_X36Y135": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y140": { + "bits": {}, + "grid_x": 87, + "grid_y": 62, + "segment": "SEG_DSP0_R_X33Y140", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y56": "DSP48E1", + "DSP48_X2Y57": "DSP48E1", + "TIEOFF_X36Y140": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y145": { + "bits": {}, + "grid_x": 87, + "grid_y": 57, + "segment": "SEG_DSP0_R_X33Y145", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y58": "DSP48E1", + "DSP48_X2Y59": "DSP48E1", + "TIEOFF_X36Y145": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y15": { + "bits": {}, + "grid_x": 87, + "grid_y": 192, + "segment": "SEG_DSP0_R_X33Y15", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y6": "DSP48E1", + "DSP48_X2Y7": "DSP48E1", + "TIEOFF_X36Y15": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y150": { + "bits": {}, + "grid_x": 87, + "grid_y": 51, + "segment": "SEG_DSP0_R_X33Y150", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y60": "DSP48E1", + "DSP48_X2Y61": "DSP48E1", + "TIEOFF_X36Y150": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y155": { + "bits": {}, + "grid_x": 87, + "grid_y": 46, + "segment": "SEG_DSP0_R_X33Y155", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y62": "DSP48E1", + "DSP48_X2Y63": "DSP48E1", + "TIEOFF_X36Y155": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y160": { + "bits": {}, + "grid_x": 87, + "grid_y": 41, + "segment": "SEG_DSP0_R_X33Y160", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y64": "DSP48E1", + "DSP48_X2Y65": "DSP48E1", + "TIEOFF_X36Y160": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y165": { + "bits": {}, + "grid_x": 87, + "grid_y": 36, + "segment": "SEG_DSP0_R_X33Y165", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y66": "DSP48E1", + "DSP48_X2Y67": "DSP48E1", + "TIEOFF_X36Y165": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y170": { + "bits": {}, + "grid_x": 87, + "grid_y": 31, + "segment": "SEG_DSP0_R_X33Y170", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y68": "DSP48E1", + "DSP48_X2Y69": "DSP48E1", + "TIEOFF_X36Y170": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y175": { + "bits": {}, + "grid_x": 87, + "grid_y": 25, + "segment": "SEG_DSP0_R_X33Y175", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y70": "DSP48E1", + "DSP48_X2Y71": "DSP48E1", + "TIEOFF_X36Y175": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y180": { + "bits": {}, + "grid_x": 87, + "grid_y": 20, + "segment": "SEG_DSP0_R_X33Y180", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y72": "DSP48E1", + "DSP48_X2Y73": "DSP48E1", + "TIEOFF_X36Y180": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y185": { + "bits": {}, + "grid_x": 87, + "grid_y": 15, + "segment": "SEG_DSP0_R_X33Y185", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y74": "DSP48E1", + "DSP48_X2Y75": "DSP48E1", + "TIEOFF_X36Y185": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y190": { + "bits": {}, + "grid_x": 87, + "grid_y": 10, + "segment": "SEG_DSP0_R_X33Y190", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y76": "DSP48E1", + "DSP48_X2Y77": "DSP48E1", + "TIEOFF_X36Y190": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y195": { + "bits": {}, + "grid_x": 87, + "grid_y": 5, + "segment": "SEG_DSP0_R_X33Y195", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y78": "DSP48E1", + "DSP48_X2Y79": "DSP48E1", + "TIEOFF_X36Y195": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y20": { + "bits": {}, + "grid_x": 87, + "grid_y": 187, + "segment": "SEG_DSP0_R_X33Y20", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y8": "DSP48E1", + "DSP48_X2Y9": "DSP48E1", + "TIEOFF_X36Y20": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y25": { + "bits": {}, + "grid_x": 87, + "grid_y": 181, + "segment": "SEG_DSP0_R_X33Y25", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y10": "DSP48E1", + "DSP48_X2Y11": "DSP48E1", + "TIEOFF_X36Y25": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y30": { + "bits": {}, + "grid_x": 87, + "grid_y": 176, + "segment": "SEG_DSP0_R_X33Y30", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y12": "DSP48E1", + "DSP48_X2Y13": "DSP48E1", + "TIEOFF_X36Y30": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y35": { + "bits": {}, + "grid_x": 87, + "grid_y": 171, + "segment": "SEG_DSP0_R_X33Y35", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y14": "DSP48E1", + "DSP48_X2Y15": "DSP48E1", + "TIEOFF_X36Y35": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y40": { + "bits": {}, + "grid_x": 87, + "grid_y": 166, + "segment": "SEG_DSP0_R_X33Y40", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y16": "DSP48E1", + "DSP48_X2Y17": "DSP48E1", + "TIEOFF_X36Y40": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y45": { + "bits": {}, + "grid_x": 87, + "grid_y": 161, + "segment": "SEG_DSP0_R_X33Y45", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y18": "DSP48E1", + "DSP48_X2Y19": "DSP48E1", + "TIEOFF_X36Y45": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y5": { + "bits": {}, + "grid_x": 87, + "grid_y": 202, + "segment": "SEG_DSP0_R_X33Y5", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y2": "DSP48E1", + "DSP48_X2Y3": "DSP48E1", + "TIEOFF_X36Y5": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y50": { + "bits": {}, + "grid_x": 87, + "grid_y": 155, + "segment": "SEG_DSP0_R_X33Y50", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y20": "DSP48E1", + "DSP48_X2Y21": "DSP48E1", + "TIEOFF_X36Y50": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y55": { + "bits": {}, + "grid_x": 87, + "grid_y": 150, + "segment": "SEG_DSP0_R_X33Y55", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y22": "DSP48E1", + "DSP48_X2Y23": "DSP48E1", + "TIEOFF_X36Y55": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y60": { + "bits": {}, + "grid_x": 87, + "grid_y": 145, + "segment": "SEG_DSP0_R_X33Y60", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y24": "DSP48E1", + "DSP48_X2Y25": "DSP48E1", + "TIEOFF_X36Y60": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y65": { + "bits": {}, + "grid_x": 87, + "grid_y": 140, + "segment": "SEG_DSP0_R_X33Y65", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y26": "DSP48E1", + "DSP48_X2Y27": "DSP48E1", + "TIEOFF_X36Y65": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y70": { + "bits": {}, + "grid_x": 87, + "grid_y": 135, + "segment": "SEG_DSP0_R_X33Y70", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y28": "DSP48E1", + "DSP48_X2Y29": "DSP48E1", + "TIEOFF_X36Y70": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y75": { + "bits": {}, + "grid_x": 87, + "grid_y": 129, + "segment": "SEG_DSP0_R_X33Y75", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y30": "DSP48E1", + "DSP48_X2Y31": "DSP48E1", + "TIEOFF_X36Y75": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y80": { + "bits": {}, + "grid_x": 87, + "grid_y": 124, + "segment": "SEG_DSP0_R_X33Y80", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y32": "DSP48E1", + "DSP48_X2Y33": "DSP48E1", + "TIEOFF_X36Y80": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y85": { + "bits": {}, + "grid_x": 87, + "grid_y": 119, + "segment": "SEG_DSP0_R_X33Y85", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y34": "DSP48E1", + "DSP48_X2Y35": "DSP48E1", + "TIEOFF_X36Y85": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y90": { + "bits": {}, + "grid_x": 87, + "grid_y": 114, + "segment": "SEG_DSP0_R_X33Y90", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y36": "DSP48E1", + "DSP48_X2Y37": "DSP48E1", + "TIEOFF_X36Y90": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X33Y95": { + "bits": {}, + "grid_x": 87, + "grid_y": 109, + "segment": "SEG_DSP0_R_X33Y95", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X2Y38": "DSP48E1", + "DSP48_X2Y39": "DSP48E1", + "TIEOFF_X36Y95": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y0": { + "bits": {}, + "grid_x": 28, + "grid_y": 207, + "segment": "SEG_DSP0_R_X9Y0", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y0": "DSP48E1", + "DSP48_X0Y1": "DSP48E1", + "TIEOFF_X10Y0": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y10": { + "bits": {}, + "grid_x": 28, + "grid_y": 197, + "segment": "SEG_DSP0_R_X9Y10", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y4": "DSP48E1", + "DSP48_X0Y5": "DSP48E1", + "TIEOFF_X10Y10": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y100": { + "bits": {}, + "grid_x": 28, + "grid_y": 103, + "segment": "SEG_DSP0_R_X9Y100", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y40": "DSP48E1", + "DSP48_X0Y41": "DSP48E1", + "TIEOFF_X10Y100": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y105": { + "bits": {}, + "grid_x": 28, + "grid_y": 98, + "segment": "SEG_DSP0_R_X9Y105", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y42": "DSP48E1", + "DSP48_X0Y43": "DSP48E1", + "TIEOFF_X10Y105": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y110": { + "bits": {}, + "grid_x": 28, + "grid_y": 93, + "segment": "SEG_DSP0_R_X9Y110", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y44": "DSP48E1", + "DSP48_X0Y45": "DSP48E1", + "TIEOFF_X10Y110": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y115": { + "bits": {}, + "grid_x": 28, + "grid_y": 88, + "segment": "SEG_DSP0_R_X9Y115", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y46": "DSP48E1", + "DSP48_X0Y47": "DSP48E1", + "TIEOFF_X10Y115": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y120": { + "bits": {}, + "grid_x": 28, + "grid_y": 83, + "segment": "SEG_DSP0_R_X9Y120", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y48": "DSP48E1", + "DSP48_X0Y49": "DSP48E1", + "TIEOFF_X10Y120": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y125": { + "bits": {}, + "grid_x": 28, + "grid_y": 77, + "segment": "SEG_DSP0_R_X9Y125", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y50": "DSP48E1", + "DSP48_X0Y51": "DSP48E1", + "TIEOFF_X10Y125": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y130": { + "bits": {}, + "grid_x": 28, + "grid_y": 72, + "segment": "SEG_DSP0_R_X9Y130", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y52": "DSP48E1", + "DSP48_X0Y53": "DSP48E1", + "TIEOFF_X10Y130": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y135": { + "bits": {}, + "grid_x": 28, + "grid_y": 67, + "segment": "SEG_DSP0_R_X9Y135", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y54": "DSP48E1", + "DSP48_X0Y55": "DSP48E1", + "TIEOFF_X10Y135": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y140": { + "bits": {}, + "grid_x": 28, + "grid_y": 62, + "segment": "SEG_DSP0_R_X9Y140", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y56": "DSP48E1", + "DSP48_X0Y57": "DSP48E1", + "TIEOFF_X10Y140": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y145": { + "bits": {}, + "grid_x": 28, + "grid_y": 57, + "segment": "SEG_DSP0_R_X9Y145", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y58": "DSP48E1", + "DSP48_X0Y59": "DSP48E1", + "TIEOFF_X10Y145": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y15": { + "bits": {}, + "grid_x": 28, + "grid_y": 192, + "segment": "SEG_DSP0_R_X9Y15", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y6": "DSP48E1", + "DSP48_X0Y7": "DSP48E1", + "TIEOFF_X10Y15": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y150": { + "bits": {}, + "grid_x": 28, + "grid_y": 51, + "segment": "SEG_DSP0_R_X9Y150", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y60": "DSP48E1", + "DSP48_X0Y61": "DSP48E1", + "TIEOFF_X10Y150": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y155": { + "bits": {}, + "grid_x": 28, + "grid_y": 46, + "segment": "SEG_DSP0_R_X9Y155", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y62": "DSP48E1", + "DSP48_X0Y63": "DSP48E1", + "TIEOFF_X10Y155": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y160": { + "bits": {}, + "grid_x": 28, + "grid_y": 41, + "segment": "SEG_DSP0_R_X9Y160", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y64": "DSP48E1", + "DSP48_X0Y65": "DSP48E1", + "TIEOFF_X10Y160": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y165": { + "bits": {}, + "grid_x": 28, + "grid_y": 36, + "segment": "SEG_DSP0_R_X9Y165", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y66": "DSP48E1", + "DSP48_X0Y67": "DSP48E1", + "TIEOFF_X10Y165": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y170": { + "bits": {}, + "grid_x": 28, + "grid_y": 31, + "segment": "SEG_DSP0_R_X9Y170", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y68": "DSP48E1", + "DSP48_X0Y69": "DSP48E1", + "TIEOFF_X10Y170": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y175": { + "bits": {}, + "grid_x": 28, + "grid_y": 25, + "segment": "SEG_DSP0_R_X9Y175", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y70": "DSP48E1", + "DSP48_X0Y71": "DSP48E1", + "TIEOFF_X10Y175": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y180": { + "bits": {}, + "grid_x": 28, + "grid_y": 20, + "segment": "SEG_DSP0_R_X9Y180", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y72": "DSP48E1", + "DSP48_X0Y73": "DSP48E1", + "TIEOFF_X10Y180": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y185": { + "bits": {}, + "grid_x": 28, + "grid_y": 15, + "segment": "SEG_DSP0_R_X9Y185", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y74": "DSP48E1", + "DSP48_X0Y75": "DSP48E1", + "TIEOFF_X10Y185": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y190": { + "bits": {}, + "grid_x": 28, + "grid_y": 10, + "segment": "SEG_DSP0_R_X9Y190", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y76": "DSP48E1", + "DSP48_X0Y77": "DSP48E1", + "TIEOFF_X10Y190": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y195": { + "bits": {}, + "grid_x": 28, + "grid_y": 5, + "segment": "SEG_DSP0_R_X9Y195", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y78": "DSP48E1", + "DSP48_X0Y79": "DSP48E1", + "TIEOFF_X10Y195": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y20": { + "bits": {}, + "grid_x": 28, + "grid_y": 187, + "segment": "SEG_DSP0_R_X9Y20", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y8": "DSP48E1", + "DSP48_X0Y9": "DSP48E1", + "TIEOFF_X10Y20": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y25": { + "bits": {}, + "grid_x": 28, + "grid_y": 181, + "segment": "SEG_DSP0_R_X9Y25", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y10": "DSP48E1", + "DSP48_X0Y11": "DSP48E1", + "TIEOFF_X10Y25": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y30": { + "bits": {}, + "grid_x": 28, + "grid_y": 176, + "segment": "SEG_DSP0_R_X9Y30", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y12": "DSP48E1", + "DSP48_X0Y13": "DSP48E1", + "TIEOFF_X10Y30": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y35": { + "bits": {}, + "grid_x": 28, + "grid_y": 171, + "segment": "SEG_DSP0_R_X9Y35", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y14": "DSP48E1", + "DSP48_X0Y15": "DSP48E1", + "TIEOFF_X10Y35": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y40": { + "bits": {}, + "grid_x": 28, + "grid_y": 166, + "segment": "SEG_DSP0_R_X9Y40", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y16": "DSP48E1", + "DSP48_X0Y17": "DSP48E1", + "TIEOFF_X10Y40": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y45": { + "bits": {}, + "grid_x": 28, + "grid_y": 161, + "segment": "SEG_DSP0_R_X9Y45", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y18": "DSP48E1", + "DSP48_X0Y19": "DSP48E1", + "TIEOFF_X10Y45": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y5": { + "bits": {}, + "grid_x": 28, + "grid_y": 202, + "segment": "SEG_DSP0_R_X9Y5", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y2": "DSP48E1", + "DSP48_X0Y3": "DSP48E1", + "TIEOFF_X10Y5": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 10, + "offset": 0, + "words": 2 + } + }, + "grid_x": 28, + "grid_y": 155, + "segment": "SEG_DSP0_R_X9Y50", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y20": "DSP48E1", + "DSP48_X0Y21": "DSP48E1", + "TIEOFF_X10Y50": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 10, + "offset": 10, + "words": 2 + } + }, + "grid_x": 28, + "grid_y": 150, + "segment": "SEG_DSP0_R_X9Y55", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y22": "DSP48E1", + "DSP48_X0Y23": "DSP48E1", + "TIEOFF_X10Y55": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 10, + "offset": 20, + "words": 2 + } + }, + "grid_x": 28, + "grid_y": 145, + "segment": "SEG_DSP0_R_X9Y60", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y24": "DSP48E1", + "DSP48_X0Y25": "DSP48E1", + "TIEOFF_X10Y60": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 10, + "offset": 30, + "words": 2 + } + }, + "grid_x": 28, + "grid_y": 140, + "segment": "SEG_DSP0_R_X9Y65", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y26": "DSP48E1", + "DSP48_X0Y27": "DSP48E1", + "TIEOFF_X10Y65": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 10, + "offset": 40, + "words": 2 + } + }, + "grid_x": 28, + "grid_y": 135, + "segment": "SEG_DSP0_R_X9Y70", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y28": "DSP48E1", + "DSP48_X0Y29": "DSP48E1", + "TIEOFF_X10Y70": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 10, + "offset": 51, + "words": 2 + } + }, + "grid_x": 28, + "grid_y": 129, + "segment": "SEG_DSP0_R_X9Y75", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y30": "DSP48E1", + "DSP48_X0Y31": "DSP48E1", + "TIEOFF_X10Y75": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 10, + "offset": 61, + "words": 2 + } + }, + "grid_x": 28, + "grid_y": 124, + "segment": "SEG_DSP0_R_X9Y80", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y32": "DSP48E1", + "DSP48_X0Y33": "DSP48E1", + "TIEOFF_X10Y80": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 10, + "offset": 71, + "words": 2 + } + }, + "grid_x": 28, + "grid_y": 119, + "segment": "SEG_DSP0_R_X9Y85", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y34": "DSP48E1", + "DSP48_X0Y35": "DSP48E1", + "TIEOFF_X10Y85": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 10, + "offset": 81, + "words": 2 + } + }, + "grid_x": 28, + "grid_y": 114, + "segment": "SEG_DSP0_R_X9Y90", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y36": "DSP48E1", + "DSP48_X0Y37": "DSP48E1", + "TIEOFF_X10Y90": "TIEOFF" + }, + "type": "DSP_R" + }, + "DSP_R_X9Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 10, + "offset": 91, + "words": 2 + } + }, + "grid_x": 28, + "grid_y": 109, + "segment": "SEG_DSP0_R_X9Y95", + "segment_type": "dsp0_r", + "sites": { + "DSP48_X0Y38": "DSP48E1", + "DSP48_X0Y39": "DSP48E1", + "TIEOFF_X10Y95": "TIEOFF" + }, + "type": "DSP_R" + }, + "GTX_CHANNEL_0_X99Y110": { + "bits": {}, + "grid_x": 99, + "grid_y": 98, + "sites": { + "GTXE2_CHANNEL_X0Y0": "GTXE2_CHANNEL", + "IPAD_X0Y0": "IPAD", + "IPAD_X0Y1": "IPAD", + "OPAD_X0Y0": "OPAD", + "OPAD_X0Y1": "OPAD" + }, + "type": "GTX_CHANNEL_0" + }, + "GTX_CHANNEL_0_X99Y162": { + "bits": {}, + "grid_x": 99, + "grid_y": 46, + "sites": { + "GTXE2_CHANNEL_X0Y4": "GTXE2_CHANNEL", + "IPAD_X0Y30": "IPAD", + "IPAD_X0Y31": "IPAD", + "OPAD_X0Y8": "OPAD", + "OPAD_X0Y9": "OPAD" + }, + "type": "GTX_CHANNEL_0" + }, + "GTX_CHANNEL_1_X99Y121": { + "bits": {}, + "grid_x": 99, + "grid_y": 87, + "sites": { + "GTXE2_CHANNEL_X0Y1": "GTXE2_CHANNEL", + "IPAD_X0Y6": "IPAD", + "IPAD_X0Y7": "IPAD", + "OPAD_X0Y2": "OPAD", + "OPAD_X0Y3": "OPAD" + }, + "type": "GTX_CHANNEL_1" + }, + "GTX_CHANNEL_1_X99Y173": { + "bits": {}, + "grid_x": 99, + "grid_y": 35, + "sites": { + "GTXE2_CHANNEL_X0Y5": "GTXE2_CHANNEL", + "IPAD_X0Y36": "IPAD", + "IPAD_X0Y37": "IPAD", + "OPAD_X0Y10": "OPAD", + "OPAD_X0Y11": "OPAD" + }, + "type": "GTX_CHANNEL_1" + }, + "GTX_CHANNEL_2_X99Y139": { + "bits": {}, + "grid_x": 99, + "grid_y": 69, + "sites": { + "GTXE2_CHANNEL_X0Y2": "GTXE2_CHANNEL", + "IPAD_X0Y18": "IPAD", + "IPAD_X0Y19": "IPAD", + "OPAD_X0Y4": "OPAD", + "OPAD_X0Y5": "OPAD" + }, + "type": "GTX_CHANNEL_2" + }, + "GTX_CHANNEL_2_X99Y191": { + "bits": {}, + "grid_x": 99, + "grid_y": 17, + "sites": { + "GTXE2_CHANNEL_X0Y6": "GTXE2_CHANNEL", + "IPAD_X0Y48": "IPAD", + "IPAD_X0Y49": "IPAD", + "OPAD_X0Y12": "OPAD", + "OPAD_X0Y13": "OPAD" + }, + "type": "GTX_CHANNEL_2" + }, + "GTX_CHANNEL_3_X99Y150": { + "bits": {}, + "grid_x": 99, + "grid_y": 58, + "sites": { + "GTXE2_CHANNEL_X0Y3": "GTXE2_CHANNEL", + "IPAD_X0Y24": "IPAD", + "IPAD_X0Y25": "IPAD", + "OPAD_X0Y6": "OPAD", + "OPAD_X0Y7": "OPAD" + }, + "type": "GTX_CHANNEL_3" + }, + "GTX_CHANNEL_3_X99Y202": { + "bits": {}, + "grid_x": 99, + "grid_y": 6, + "sites": { + "GTXE2_CHANNEL_X0Y7": "GTXE2_CHANNEL", + "IPAD_X0Y54": "IPAD", + "IPAD_X0Y55": "IPAD", + "OPAD_X0Y14": "OPAD", + "OPAD_X0Y15": "OPAD" + }, + "type": "GTX_CHANNEL_3" + }, + "GTX_COMMON_X99Y127": { + "bits": {}, + "grid_x": 99, + "grid_y": 81, + "sites": { + "GTXE2_COMMON_X0Y0": "GTXE2_COMMON", + "IBUFDS_GTE2_X0Y0": "IBUFDS_GTE2", + "IBUFDS_GTE2_X0Y1": "IBUFDS_GTE2", + "IPAD_X0Y10": "IPAD", + "IPAD_X0Y11": "IPAD", + "IPAD_X0Y8": "IPAD", + "IPAD_X0Y9": "IPAD" + }, + "type": "GTX_COMMON" + }, + "GTX_COMMON_X99Y179": { + "bits": {}, + "grid_x": 99, + "grid_y": 29, + "sites": { + "GTXE2_COMMON_X0Y1": "GTXE2_COMMON", + "IBUFDS_GTE2_X0Y2": "IBUFDS_GTE2", + "IBUFDS_GTE2_X0Y3": "IBUFDS_GTE2", + "IPAD_X0Y38": "IPAD", + "IPAD_X0Y39": "IPAD", + "IPAD_X0Y40": "IPAD", + "IPAD_X0Y41": "IPAD" + }, + "type": "GTX_COMMON" + }, + "GTX_INT_INTERFACE_X37Y100": { + "bits": {}, + "grid_x": 96, + "grid_y": 103, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y101": { + "bits": {}, + "grid_x": 96, + "grid_y": 102, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y102": { + "bits": {}, + "grid_x": 96, + "grid_y": 101, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y103": { + "bits": {}, + "grid_x": 96, + "grid_y": 100, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y104": { + "bits": {}, + "grid_x": 96, + "grid_y": 99, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y105": { + "bits": {}, + "grid_x": 96, + "grid_y": 98, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y106": { + "bits": {}, + "grid_x": 96, + "grid_y": 97, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y107": { + "bits": {}, + "grid_x": 96, + "grid_y": 96, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y108": { + "bits": {}, + "grid_x": 96, + "grid_y": 95, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y109": { + "bits": {}, + "grid_x": 96, + "grid_y": 94, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y110": { + "bits": {}, + "grid_x": 96, + "grid_y": 93, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y111": { + "bits": {}, + "grid_x": 96, + "grid_y": 92, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y112": { + "bits": {}, + "grid_x": 96, + "grid_y": 91, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y113": { + "bits": {}, + "grid_x": 96, + "grid_y": 90, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y114": { + "bits": {}, + "grid_x": 96, + "grid_y": 89, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y115": { + "bits": {}, + "grid_x": 96, + "grid_y": 88, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y116": { + "bits": {}, + "grid_x": 96, + "grid_y": 87, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y117": { + "bits": {}, + "grid_x": 96, + "grid_y": 86, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y118": { + "bits": {}, + "grid_x": 96, + "grid_y": 85, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y119": { + "bits": {}, + "grid_x": 96, + "grid_y": 84, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y120": { + "bits": {}, + "grid_x": 96, + "grid_y": 83, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y121": { + "bits": {}, + "grid_x": 96, + "grid_y": 82, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y122": { + "bits": {}, + "grid_x": 96, + "grid_y": 81, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y123": { + "bits": {}, + "grid_x": 96, + "grid_y": 80, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y124": { + "bits": {}, + "grid_x": 96, + "grid_y": 79, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y125": { + "bits": {}, + "grid_x": 96, + "grid_y": 77, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y126": { + "bits": {}, + "grid_x": 96, + "grid_y": 76, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y127": { + "bits": {}, + "grid_x": 96, + "grid_y": 75, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y128": { + "bits": {}, + "grid_x": 96, + "grid_y": 74, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y129": { + "bits": {}, + "grid_x": 96, + "grid_y": 73, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y130": { + "bits": {}, + "grid_x": 96, + "grid_y": 72, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y131": { + "bits": {}, + "grid_x": 96, + "grid_y": 71, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y132": { + "bits": {}, + "grid_x": 96, + "grid_y": 70, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y133": { + "bits": {}, + "grid_x": 96, + "grid_y": 69, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y134": { + "bits": {}, + "grid_x": 96, + "grid_y": 68, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y135": { + "bits": {}, + "grid_x": 96, + "grid_y": 67, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y136": { + "bits": {}, + "grid_x": 96, + "grid_y": 66, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y137": { + "bits": {}, + "grid_x": 96, + "grid_y": 65, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y138": { + "bits": {}, + "grid_x": 96, + "grid_y": 64, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y139": { + "bits": {}, + "grid_x": 96, + "grid_y": 63, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y140": { + "bits": {}, + "grid_x": 96, + "grid_y": 62, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y141": { + "bits": {}, + "grid_x": 96, + "grid_y": 61, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y142": { + "bits": {}, + "grid_x": 96, + "grid_y": 60, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y143": { + "bits": {}, + "grid_x": 96, + "grid_y": 59, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y144": { + "bits": {}, + "grid_x": 96, + "grid_y": 58, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y145": { + "bits": {}, + "grid_x": 96, + "grid_y": 57, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y146": { + "bits": {}, + "grid_x": 96, + "grid_y": 56, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y147": { + "bits": {}, + "grid_x": 96, + "grid_y": 55, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y148": { + "bits": {}, + "grid_x": 96, + "grid_y": 54, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y149": { + "bits": {}, + "grid_x": 96, + "grid_y": 53, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y150": { + "bits": {}, + "grid_x": 96, + "grid_y": 51, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y151": { + "bits": {}, + "grid_x": 96, + "grid_y": 50, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y152": { + "bits": {}, + "grid_x": 96, + "grid_y": 49, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y153": { + "bits": {}, + "grid_x": 96, + "grid_y": 48, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y154": { + "bits": {}, + "grid_x": 96, + "grid_y": 47, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y155": { + "bits": {}, + "grid_x": 96, + "grid_y": 46, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y156": { + "bits": {}, + "grid_x": 96, + "grid_y": 45, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y157": { + "bits": {}, + "grid_x": 96, + "grid_y": 44, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y158": { + "bits": {}, + "grid_x": 96, + "grid_y": 43, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y159": { + "bits": {}, + "grid_x": 96, + "grid_y": 42, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y160": { + "bits": {}, + "grid_x": 96, + "grid_y": 41, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y161": { + "bits": {}, + "grid_x": 96, + "grid_y": 40, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y162": { + "bits": {}, + "grid_x": 96, + "grid_y": 39, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y163": { + "bits": {}, + "grid_x": 96, + "grid_y": 38, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y164": { + "bits": {}, + "grid_x": 96, + "grid_y": 37, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y165": { + "bits": {}, + "grid_x": 96, + "grid_y": 36, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y166": { + "bits": {}, + "grid_x": 96, + "grid_y": 35, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y167": { + "bits": {}, + "grid_x": 96, + "grid_y": 34, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y168": { + "bits": {}, + "grid_x": 96, + "grid_y": 33, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y169": { + "bits": {}, + "grid_x": 96, + "grid_y": 32, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y170": { + "bits": {}, + "grid_x": 96, + "grid_y": 31, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y171": { + "bits": {}, + "grid_x": 96, + "grid_y": 30, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y172": { + "bits": {}, + "grid_x": 96, + "grid_y": 29, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y173": { + "bits": {}, + "grid_x": 96, + "grid_y": 28, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y174": { + "bits": {}, + "grid_x": 96, + "grid_y": 27, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y175": { + "bits": {}, + "grid_x": 96, + "grid_y": 25, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y176": { + "bits": {}, + "grid_x": 96, + "grid_y": 24, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y177": { + "bits": {}, + "grid_x": 96, + "grid_y": 23, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y178": { + "bits": {}, + "grid_x": 96, + "grid_y": 22, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y179": { + "bits": {}, + "grid_x": 96, + "grid_y": 21, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y180": { + "bits": {}, + "grid_x": 96, + "grid_y": 20, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y181": { + "bits": {}, + "grid_x": 96, + "grid_y": 19, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y182": { + "bits": {}, + "grid_x": 96, + "grid_y": 18, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y183": { + "bits": {}, + "grid_x": 96, + "grid_y": 17, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y184": { + "bits": {}, + "grid_x": 96, + "grid_y": 16, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y185": { + "bits": {}, + "grid_x": 96, + "grid_y": 15, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y186": { + "bits": {}, + "grid_x": 96, + "grid_y": 14, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y187": { + "bits": {}, + "grid_x": 96, + "grid_y": 13, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y188": { + "bits": {}, + "grid_x": 96, + "grid_y": 12, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y189": { + "bits": {}, + "grid_x": 96, + "grid_y": 11, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y190": { + "bits": {}, + "grid_x": 96, + "grid_y": 10, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y191": { + "bits": {}, + "grid_x": 96, + "grid_y": 9, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y192": { + "bits": {}, + "grid_x": 96, + "grid_y": 8, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y193": { + "bits": {}, + "grid_x": 96, + "grid_y": 7, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y194": { + "bits": {}, + "grid_x": 96, + "grid_y": 6, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y195": { + "bits": {}, + "grid_x": 96, + "grid_y": 5, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y196": { + "bits": {}, + "grid_x": 96, + "grid_y": 4, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y197": { + "bits": {}, + "grid_x": 96, + "grid_y": 3, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y198": { + "bits": {}, + "grid_x": 96, + "grid_y": 2, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "GTX_INT_INTERFACE_X37Y199": { + "bits": {}, + "grid_x": 96, + "grid_y": 1, + "sites": {}, + "type": "GTX_INT_INTERFACE" + }, + "HCLK_BRAM_X19Y130": { + "bits": {}, + "grid_x": 19, + "grid_y": 78, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_BRAM_X19Y182": { + "bits": {}, + "grid_x": 19, + "grid_y": 26, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_BRAM_X19Y26": { + "bits": {}, + "grid_x": 19, + "grid_y": 182, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_BRAM_X19Y78": { + "bits": {}, + "grid_x": 19, + "grid_y": 130, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_BRAM_X48Y130": { + "bits": {}, + "grid_x": 48, + "grid_y": 78, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_BRAM_X48Y182": { + "bits": {}, + "grid_x": 48, + "grid_y": 26, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_BRAM_X48Y26": { + "bits": {}, + "grid_x": 48, + "grid_y": 182, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_BRAM_X48Y78": { + "bits": {}, + "grid_x": 48, + "grid_y": 130, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_BRAM_X77Y130": { + "bits": {}, + "grid_x": 77, + "grid_y": 78, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_BRAM_X77Y182": { + "bits": {}, + "grid_x": 77, + "grid_y": 26, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_BRAM_X77Y26": { + "bits": {}, + "grid_x": 77, + "grid_y": 182, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_BRAM_X77Y78": { + "bits": {}, + "grid_x": 77, + "grid_y": 130, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_BRAM_X97Y26": { + "bits": {}, + "grid_x": 97, + "grid_y": 182, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_BRAM_X97Y78": { + "bits": {}, + "grid_x": 97, + "grid_y": 130, + "sites": {}, + "type": "HCLK_BRAM" + }, + "HCLK_CLB_X102Y26": { + "bits": {}, + "grid_x": 102, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X102Y78": { + "bits": {}, + "grid_x": 102, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X103Y26": { + "bits": {}, + "grid_x": 103, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X103Y78": { + "bits": {}, + "grid_x": 103, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X106Y26": { + "bits": {}, + "grid_x": 106, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X106Y78": { + "bits": {}, + "grid_x": 106, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X10Y130": { + "bits": {}, + "grid_x": 10, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X10Y182": { + "bits": {}, + "grid_x": 10, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X10Y26": { + "bits": {}, + "grid_x": 10, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X10Y78": { + "bits": {}, + "grid_x": 10, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X13Y130": { + "bits": {}, + "grid_x": 13, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X13Y182": { + "bits": {}, + "grid_x": 13, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X13Y26": { + "bits": {}, + "grid_x": 13, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X13Y78": { + "bits": {}, + "grid_x": 13, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X14Y130": { + "bits": {}, + "grid_x": 14, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X14Y182": { + "bits": {}, + "grid_x": 14, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X14Y26": { + "bits": {}, + "grid_x": 14, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X14Y78": { + "bits": {}, + "grid_x": 14, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X17Y130": { + "bits": {}, + "grid_x": 17, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X17Y182": { + "bits": {}, + "grid_x": 17, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X17Y26": { + "bits": {}, + "grid_x": 17, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X17Y78": { + "bits": {}, + "grid_x": 17, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X23Y130": { + "bits": {}, + "grid_x": 23, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X23Y182": { + "bits": {}, + "grid_x": 23, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X23Y26": { + "bits": {}, + "grid_x": 23, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X23Y78": { + "bits": {}, + "grid_x": 23, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X24Y130": { + "bits": {}, + "grid_x": 24, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X24Y182": { + "bits": {}, + "grid_x": 24, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X24Y26": { + "bits": {}, + "grid_x": 24, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X24Y78": { + "bits": {}, + "grid_x": 24, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X30Y130": { + "bits": {}, + "grid_x": 30, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X30Y182": { + "bits": {}, + "grid_x": 30, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X30Y26": { + "bits": {}, + "grid_x": 30, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X30Y78": { + "bits": {}, + "grid_x": 30, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X33Y130": { + "bits": {}, + "grid_x": 33, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X33Y182": { + "bits": {}, + "grid_x": 33, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X33Y26": { + "bits": {}, + "grid_x": 33, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X33Y78": { + "bits": {}, + "grid_x": 33, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X34Y130": { + "bits": {}, + "grid_x": 34, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X34Y182": { + "bits": {}, + "grid_x": 34, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X34Y26": { + "bits": {}, + "grid_x": 34, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X34Y78": { + "bits": {}, + "grid_x": 34, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X37Y130": { + "bits": {}, + "grid_x": 37, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X37Y182": { + "bits": {}, + "grid_x": 37, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X37Y26": { + "bits": {}, + "grid_x": 37, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X37Y78": { + "bits": {}, + "grid_x": 37, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X43Y130": { + "bits": {}, + "grid_x": 43, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X43Y182": { + "bits": {}, + "grid_x": 43, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X43Y26": { + "bits": {}, + "grid_x": 43, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X43Y78": { + "bits": {}, + "grid_x": 43, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X44Y130": { + "bits": {}, + "grid_x": 44, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X44Y182": { + "bits": {}, + "grid_x": 44, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X44Y26": { + "bits": {}, + "grid_x": 44, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X44Y78": { + "bits": {}, + "grid_x": 44, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X50Y182": { + "bits": {}, + "grid_x": 50, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X50Y26": { + "bits": {}, + "grid_x": 50, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X53Y182": { + "bits": {}, + "grid_x": 53, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X53Y26": { + "bits": {}, + "grid_x": 53, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X54Y182": { + "bits": {}, + "grid_x": 54, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X54Y26": { + "bits": {}, + "grid_x": 54, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X57Y182": { + "bits": {}, + "grid_x": 57, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X57Y26": { + "bits": {}, + "grid_x": 57, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X58Y182": { + "bits": {}, + "grid_x": 58, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X58Y26": { + "bits": {}, + "grid_x": 58, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X61Y182": { + "bits": {}, + "grid_x": 61, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X61Y26": { + "bits": {}, + "grid_x": 61, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X69Y130": { + "bits": {}, + "grid_x": 69, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X69Y182": { + "bits": {}, + "grid_x": 69, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X69Y26": { + "bits": {}, + "grid_x": 69, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X69Y78": { + "bits": {}, + "grid_x": 69, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X72Y130": { + "bits": {}, + "grid_x": 72, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X72Y182": { + "bits": {}, + "grid_x": 72, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X72Y26": { + "bits": {}, + "grid_x": 72, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X72Y78": { + "bits": {}, + "grid_x": 72, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X73Y130": { + "bits": {}, + "grid_x": 73, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X73Y182": { + "bits": {}, + "grid_x": 73, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X73Y26": { + "bits": {}, + "grid_x": 73, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X73Y78": { + "bits": {}, + "grid_x": 73, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X76Y130": { + "bits": {}, + "grid_x": 76, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X76Y182": { + "bits": {}, + "grid_x": 76, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X76Y26": { + "bits": {}, + "grid_x": 76, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X76Y78": { + "bits": {}, + "grid_x": 76, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X81Y130": { + "bits": {}, + "grid_x": 81, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X81Y182": { + "bits": {}, + "grid_x": 81, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X81Y26": { + "bits": {}, + "grid_x": 81, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X81Y78": { + "bits": {}, + "grid_x": 81, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X83Y130": { + "bits": {}, + "grid_x": 83, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X83Y182": { + "bits": {}, + "grid_x": 83, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X83Y26": { + "bits": {}, + "grid_x": 83, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X83Y78": { + "bits": {}, + "grid_x": 83, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X88Y130": { + "bits": {}, + "grid_x": 88, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X88Y182": { + "bits": {}, + "grid_x": 88, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X88Y26": { + "bits": {}, + "grid_x": 88, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X88Y78": { + "bits": {}, + "grid_x": 88, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X91Y130": { + "bits": {}, + "grid_x": 91, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X91Y182": { + "bits": {}, + "grid_x": 91, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X91Y26": { + "bits": {}, + "grid_x": 91, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X91Y78": { + "bits": {}, + "grid_x": 91, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X93Y130": { + "bits": {}, + "grid_x": 93, + "grid_y": 78, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X93Y182": { + "bits": {}, + "grid_x": 93, + "grid_y": 26, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X93Y26": { + "bits": {}, + "grid_x": 93, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X93Y78": { + "bits": {}, + "grid_x": 93, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X99Y26": { + "bits": {}, + "grid_x": 99, + "grid_y": 182, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CLB_X99Y78": { + "bits": {}, + "grid_x": 99, + "grid_y": 130, + "sites": {}, + "type": "HCLK_CLB" + }, + "HCLK_CMT_L_X108Y26": { + "bits": {}, + "grid_x": 108, + "grid_y": 182, + "sites": { + "BUFMRCE_X1Y0": "BUFMRCE", + "BUFMRCE_X1Y1": "BUFMRCE" + }, + "type": "HCLK_CMT_L" + }, + "HCLK_CMT_L_X108Y78": { + "bits": {}, + "grid_x": 108, + "grid_y": 130, + "sites": { + "BUFMRCE_X1Y2": "BUFMRCE", + "BUFMRCE_X1Y3": "BUFMRCE" + }, + "type": "HCLK_CMT_L" + }, + "HCLK_CMT_X8Y130": { + "bits": {}, + "grid_x": 8, + "grid_y": 78, + "sites": { + "BUFMRCE_X0Y4": "BUFMRCE", + "BUFMRCE_X0Y5": "BUFMRCE" + }, + "type": "HCLK_CMT" + }, + "HCLK_CMT_X8Y182": { + "bits": {}, + "grid_x": 8, + "grid_y": 26, + "sites": { + "BUFMRCE_X0Y6": "BUFMRCE", + "BUFMRCE_X0Y7": "BUFMRCE" + }, + "type": "HCLK_CMT" + }, + "HCLK_CMT_X8Y26": { + "bits": {}, + "grid_x": 8, + "grid_y": 182, + "sites": { + "BUFMRCE_X0Y0": "BUFMRCE", + "BUFMRCE_X0Y1": "BUFMRCE" + }, + "type": "HCLK_CMT" + }, + "HCLK_CMT_X8Y78": { + "bits": {}, + "grid_x": 8, + "grid_y": 130, + "sites": { + "BUFMRCE_X0Y2": "BUFMRCE", + "BUFMRCE_X0Y3": "BUFMRCE" + }, + "type": "HCLK_CMT" + }, + "HCLK_DSP_L_X39Y130": { + "bits": {}, + "grid_x": 39, + "grid_y": 78, + "sites": {}, + "type": "HCLK_DSP_L" + }, + "HCLK_DSP_L_X39Y182": { + "bits": {}, + "grid_x": 39, + "grid_y": 26, + "sites": {}, + "type": "HCLK_DSP_L" + }, + "HCLK_DSP_L_X39Y26": { + "bits": {}, + "grid_x": 39, + "grid_y": 182, + "sites": {}, + "type": "HCLK_DSP_L" + }, + "HCLK_DSP_L_X39Y78": { + "bits": {}, + "grid_x": 39, + "grid_y": 130, + "sites": {}, + "type": "HCLK_DSP_L" + }, + "HCLK_DSP_R_X28Y130": { + "bits": {}, + "grid_x": 28, + "grid_y": 78, + "sites": {}, + "type": "HCLK_DSP_R" + }, + "HCLK_DSP_R_X28Y182": { + "bits": {}, + "grid_x": 28, + "grid_y": 26, + "sites": {}, + "type": "HCLK_DSP_R" + }, + "HCLK_DSP_R_X28Y26": { + "bits": {}, + "grid_x": 28, + "grid_y": 182, + "sites": {}, + "type": "HCLK_DSP_R" + }, + "HCLK_DSP_R_X28Y78": { + "bits": {}, + "grid_x": 28, + "grid_y": 130, + "sites": {}, + "type": "HCLK_DSP_R" + }, + "HCLK_DSP_R_X87Y130": { + "bits": {}, + "grid_x": 87, + "grid_y": 78, + "sites": {}, + "type": "HCLK_DSP_R" + }, + "HCLK_DSP_R_X87Y182": { + "bits": {}, + "grid_x": 87, + "grid_y": 26, + "sites": {}, + "type": "HCLK_DSP_R" + }, + "HCLK_DSP_R_X87Y26": { + "bits": {}, + "grid_x": 87, + "grid_y": 182, + "sites": {}, + "type": "HCLK_DSP_R" + }, + "HCLK_DSP_R_X87Y78": { + "bits": {}, + "grid_x": 87, + "grid_y": 130, + "sites": {}, + "type": "HCLK_DSP_R" + }, + "HCLK_FEEDTHRU_1_X50Y130": { + "bits": {}, + "grid_x": 50, + "grid_y": 78, + "sites": {}, + "type": "HCLK_FEEDTHRU_1" + }, + "HCLK_FEEDTHRU_1_X50Y78": { + "bits": {}, + "grid_x": 50, + "grid_y": 130, + "sites": {}, + "type": "HCLK_FEEDTHRU_1" + }, + "HCLK_FEEDTHRU_1_X53Y130": { + "bits": {}, + "grid_x": 53, + "grid_y": 78, + "sites": {}, + "type": "HCLK_FEEDTHRU_1" + }, + "HCLK_FEEDTHRU_1_X53Y78": { + "bits": {}, + "grid_x": 53, + "grid_y": 130, + "sites": {}, + "type": "HCLK_FEEDTHRU_1" + }, + "HCLK_FEEDTHRU_1_X54Y130": { + "bits": {}, + "grid_x": 54, + "grid_y": 78, + "sites": {}, + "type": "HCLK_FEEDTHRU_1" + }, + "HCLK_FEEDTHRU_1_X54Y78": { + "bits": {}, + "grid_x": 54, + "grid_y": 130, + "sites": {}, + "type": "HCLK_FEEDTHRU_1" + }, + "HCLK_FEEDTHRU_1_X57Y130": { + "bits": {}, + "grid_x": 57, + "grid_y": 78, + "sites": {}, + "type": "HCLK_FEEDTHRU_1" + }, + "HCLK_FEEDTHRU_1_X57Y78": { + "bits": {}, + "grid_x": 57, + "grid_y": 130, + "sites": {}, + "type": "HCLK_FEEDTHRU_1" + }, + "HCLK_FEEDTHRU_1_X58Y130": { + "bits": {}, + "grid_x": 58, + "grid_y": 78, + "sites": {}, + "type": "HCLK_FEEDTHRU_1" + }, + "HCLK_FEEDTHRU_1_X58Y78": { + "bits": {}, + "grid_x": 58, + "grid_y": 130, + "sites": {}, + "type": "HCLK_FEEDTHRU_1" + }, + "HCLK_FEEDTHRU_1_X61Y130": { + "bits": {}, + "grid_x": 61, + "grid_y": 78, + "sites": {}, + "type": "HCLK_FEEDTHRU_1" + }, + "HCLK_FEEDTHRU_2_X51Y130": { + "bits": {}, + "grid_x": 51, + "grid_y": 78, + "sites": {}, + "type": "HCLK_FEEDTHRU_2" + }, + "HCLK_FEEDTHRU_2_X51Y78": { + "bits": {}, + "grid_x": 51, + "grid_y": 130, + "sites": {}, + "type": "HCLK_FEEDTHRU_2" + }, + "HCLK_FEEDTHRU_2_X52Y130": { + "bits": {}, + "grid_x": 52, + "grid_y": 78, + "sites": {}, + "type": "HCLK_FEEDTHRU_2" + }, + "HCLK_FEEDTHRU_2_X52Y78": { + "bits": {}, + "grid_x": 52, + "grid_y": 130, + "sites": {}, + "type": "HCLK_FEEDTHRU_2" + }, + "HCLK_FEEDTHRU_2_X55Y130": { + "bits": {}, + "grid_x": 55, + "grid_y": 78, + "sites": {}, + "type": "HCLK_FEEDTHRU_2" + }, + "HCLK_FEEDTHRU_2_X55Y78": { + "bits": {}, + "grid_x": 55, + "grid_y": 130, + "sites": {}, + "type": "HCLK_FEEDTHRU_2" + }, + "HCLK_FEEDTHRU_2_X56Y130": { + "bits": {}, + "grid_x": 56, + "grid_y": 78, + "sites": {}, + "type": "HCLK_FEEDTHRU_2" + }, + "HCLK_FEEDTHRU_2_X56Y78": { + "bits": {}, + "grid_x": 56, + "grid_y": 130, + "sites": {}, + "type": "HCLK_FEEDTHRU_2" + }, + "HCLK_FEEDTHRU_2_X59Y130": { + "bits": {}, + "grid_x": 59, + "grid_y": 78, + "sites": {}, + "type": "HCLK_FEEDTHRU_2" + }, + "HCLK_FEEDTHRU_2_X59Y78": { + "bits": {}, + "grid_x": 59, + "grid_y": 130, + "sites": {}, + "type": "HCLK_FEEDTHRU_2" + }, + "HCLK_FEEDTHRU_2_X60Y130": { + "bits": {}, + "grid_x": 60, + "grid_y": 78, + "sites": {}, + "type": "HCLK_FEEDTHRU_2" + }, + "HCLK_FEEDTHRU_2_X60Y78": { + "bits": {}, + "grid_x": 60, + "grid_y": 130, + "sites": {}, + "type": "HCLK_FEEDTHRU_2" + }, + "HCLK_FIFO_L_X109Y26": { + "bits": {}, + "grid_x": 109, + "grid_y": 182, + "sites": {}, + "type": "HCLK_FIFO_L" + }, + "HCLK_FIFO_L_X109Y78": { + "bits": {}, + "grid_x": 109, + "grid_y": 130, + "sites": {}, + "type": "HCLK_FIFO_L" + }, + "HCLK_FIFO_L_X7Y130": { + "bits": {}, + "grid_x": 7, + "grid_y": 78, + "sites": {}, + "type": "HCLK_FIFO_L" + }, + "HCLK_FIFO_L_X7Y182": { + "bits": {}, + "grid_x": 7, + "grid_y": 26, + "sites": {}, + "type": "HCLK_FIFO_L" + }, + "HCLK_FIFO_L_X7Y26": { + "bits": {}, + "grid_x": 7, + "grid_y": 182, + "sites": {}, + "type": "HCLK_FIFO_L" + }, + "HCLK_FIFO_L_X7Y78": { + "bits": {}, + "grid_x": 7, + "grid_y": 130, + "sites": {}, + "type": "HCLK_FIFO_L" + }, + "HCLK_GTX_X97Y130": { + "bits": {}, + "grid_x": 97, + "grid_y": 78, + "sites": {}, + "type": "HCLK_GTX" + }, + "HCLK_GTX_X97Y182": { + "bits": {}, + "grid_x": 97, + "grid_y": 26, + "sites": {}, + "type": "HCLK_GTX" + }, + "HCLK_INT_INTERFACE_X110Y26": { + "bits": {}, + "grid_x": 110, + "grid_y": 182, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X110Y78": { + "bits": {}, + "grid_x": 110, + "grid_y": 130, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X113Y26": { + "bits": {}, + "grid_x": 113, + "grid_y": 182, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X113Y78": { + "bits": {}, + "grid_x": 113, + "grid_y": 130, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X20Y130": { + "bits": {}, + "grid_x": 20, + "grid_y": 78, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X20Y182": { + "bits": {}, + "grid_x": 20, + "grid_y": 26, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X20Y26": { + "bits": {}, + "grid_x": 20, + "grid_y": 182, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X20Y78": { + "bits": {}, + "grid_x": 20, + "grid_y": 130, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X27Y130": { + "bits": {}, + "grid_x": 27, + "grid_y": 78, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X27Y182": { + "bits": {}, + "grid_x": 27, + "grid_y": 26, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X27Y26": { + "bits": {}, + "grid_x": 27, + "grid_y": 182, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X27Y78": { + "bits": {}, + "grid_x": 27, + "grid_y": 130, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X3Y130": { + "bits": {}, + "grid_x": 3, + "grid_y": 78, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X3Y182": { + "bits": {}, + "grid_x": 3, + "grid_y": 26, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X3Y26": { + "bits": {}, + "grid_x": 3, + "grid_y": 182, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X3Y78": { + "bits": {}, + "grid_x": 3, + "grid_y": 130, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X40Y130": { + "bits": {}, + "grid_x": 40, + "grid_y": 78, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X40Y182": { + "bits": {}, + "grid_x": 40, + "grid_y": 26, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X40Y26": { + "bits": {}, + "grid_x": 40, + "grid_y": 182, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X40Y78": { + "bits": {}, + "grid_x": 40, + "grid_y": 130, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X47Y130": { + "bits": {}, + "grid_x": 47, + "grid_y": 78, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X47Y182": { + "bits": {}, + "grid_x": 47, + "grid_y": 26, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X47Y26": { + "bits": {}, + "grid_x": 47, + "grid_y": 182, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X47Y78": { + "bits": {}, + "grid_x": 47, + "grid_y": 130, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X63Y130": { + "bits": {}, + "grid_x": 63, + "grid_y": 78, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X63Y182": { + "bits": {}, + "grid_x": 63, + "grid_y": 26, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X63Y26": { + "bits": {}, + "grid_x": 63, + "grid_y": 182, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X63Y78": { + "bits": {}, + "grid_x": 63, + "grid_y": 130, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X66Y130": { + "bits": {}, + "grid_x": 66, + "grid_y": 78, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X66Y182": { + "bits": {}, + "grid_x": 66, + "grid_y": 26, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X66Y26": { + "bits": {}, + "grid_x": 66, + "grid_y": 182, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X66Y78": { + "bits": {}, + "grid_x": 66, + "grid_y": 130, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X6Y130": { + "bits": {}, + "grid_x": 6, + "grid_y": 78, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X6Y182": { + "bits": {}, + "grid_x": 6, + "grid_y": 26, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X6Y26": { + "bits": {}, + "grid_x": 6, + "grid_y": 182, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X6Y78": { + "bits": {}, + "grid_x": 6, + "grid_y": 130, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X78Y130": { + "bits": {}, + "grid_x": 78, + "grid_y": 78, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X78Y182": { + "bits": {}, + "grid_x": 78, + "grid_y": 26, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X78Y26": { + "bits": {}, + "grid_x": 78, + "grid_y": 182, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X78Y78": { + "bits": {}, + "grid_x": 78, + "grid_y": 130, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X86Y130": { + "bits": {}, + "grid_x": 86, + "grid_y": 78, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X86Y182": { + "bits": {}, + "grid_x": 86, + "grid_y": 26, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X86Y26": { + "bits": {}, + "grid_x": 86, + "grid_y": 182, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X86Y78": { + "bits": {}, + "grid_x": 86, + "grid_y": 130, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X96Y130": { + "bits": {}, + "grid_x": 96, + "grid_y": 78, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X96Y182": { + "bits": {}, + "grid_x": 96, + "grid_y": 26, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X96Y26": { + "bits": {}, + "grid_x": 96, + "grid_y": 182, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_INT_INTERFACE_X96Y78": { + "bits": {}, + "grid_x": 96, + "grid_y": 130, + "sites": {}, + "type": "HCLK_INT_INTERFACE" + }, + "HCLK_IOB_X0Y130": { + "bits": {}, + "grid_x": 0, + "grid_y": 78, + "sites": {}, + "type": "HCLK_IOB" + }, + "HCLK_IOB_X0Y182": { + "bits": {}, + "grid_x": 0, + "grid_y": 26, + "sites": {}, + "type": "HCLK_IOB" + }, + "HCLK_IOB_X0Y26": { + "bits": {}, + "grid_x": 0, + "grid_y": 182, + "sites": {}, + "type": "HCLK_IOB" + }, + "HCLK_IOB_X0Y78": { + "bits": {}, + "grid_x": 0, + "grid_y": 130, + "sites": {}, + "type": "HCLK_IOB" + }, + "HCLK_IOB_X116Y26": { + "bits": {}, + "grid_x": 116, + "grid_y": 182, + "sites": {}, + "type": "HCLK_IOB" + }, + "HCLK_IOB_X116Y78": { + "bits": {}, + "grid_x": 116, + "grid_y": 130, + "sites": {}, + "type": "HCLK_IOB" + }, + "HCLK_IOI3_X1Y130": { + "bits": {}, + "grid_x": 1, + "grid_y": 78, + "sites": { + "BUFIO_X0Y10": "BUFIO", + "BUFIO_X0Y11": "BUFIO", + "BUFIO_X0Y8": "BUFIO", + "BUFIO_X0Y9": "BUFIO", + "BUFR_X0Y10": "BUFR", + "BUFR_X0Y11": "BUFR", + "BUFR_X0Y8": "BUFR", + "BUFR_X0Y9": "BUFR", + "IDELAYCTRL_X0Y2": "IDELAYCTRL" + }, + "type": "HCLK_IOI3" + }, + "HCLK_IOI3_X1Y182": { + "bits": {}, + "grid_x": 1, + "grid_y": 26, + "sites": { + "BUFIO_X0Y12": "BUFIO", + "BUFIO_X0Y13": "BUFIO", + "BUFIO_X0Y14": "BUFIO", + "BUFIO_X0Y15": "BUFIO", + "BUFR_X0Y12": "BUFR", + "BUFR_X0Y13": "BUFR", + "BUFR_X0Y14": "BUFR", + "BUFR_X0Y15": "BUFR", + "IDELAYCTRL_X0Y3": "IDELAYCTRL" + }, + "type": "HCLK_IOI3" + }, + "HCLK_IOI3_X1Y26": { + "bits": {}, + "grid_x": 1, + "grid_y": 182, + "sites": { + "BUFIO_X0Y0": "BUFIO", + "BUFIO_X0Y1": "BUFIO", + "BUFIO_X0Y2": "BUFIO", + "BUFIO_X0Y3": "BUFIO", + "BUFR_X0Y0": "BUFR", + "BUFR_X0Y1": "BUFR", + "BUFR_X0Y2": "BUFR", + "BUFR_X0Y3": "BUFR", + "IDELAYCTRL_X0Y0": "IDELAYCTRL" + }, + "type": "HCLK_IOI3" + }, + "HCLK_IOI3_X1Y78": { + "bits": {}, + "grid_x": 1, + "grid_y": 130, + "sites": { + "BUFIO_X0Y4": "BUFIO", + "BUFIO_X0Y5": "BUFIO", + "BUFIO_X0Y6": "BUFIO", + "BUFIO_X0Y7": "BUFIO", + "BUFR_X0Y4": "BUFR", + "BUFR_X0Y5": "BUFR", + "BUFR_X0Y6": "BUFR", + "BUFR_X0Y7": "BUFR", + "IDELAYCTRL_X0Y1": "IDELAYCTRL" + }, + "type": "HCLK_IOI3" + }, + "HCLK_IOI_X115Y26": { + "bits": {}, + "grid_x": 115, + "grid_y": 182, + "sites": { + "BUFIO_X1Y0": "BUFIO", + "BUFIO_X1Y1": "BUFIO", + "BUFIO_X1Y2": "BUFIO", + "BUFIO_X1Y3": "BUFIO", + "BUFR_X1Y0": "BUFR", + "BUFR_X1Y1": "BUFR", + "BUFR_X1Y2": "BUFR", + "BUFR_X1Y3": "BUFR", + "IDELAYCTRL_X1Y0": "IDELAYCTRL" + }, + "type": "HCLK_IOI" + }, + "HCLK_IOI_X115Y78": { + "bits": {}, + "grid_x": 115, + "grid_y": 130, + "sites": { + "BUFIO_X1Y4": "BUFIO", + "BUFIO_X1Y5": "BUFIO", + "BUFIO_X1Y6": "BUFIO", + "BUFIO_X1Y7": "BUFIO", + "BUFR_X1Y4": "BUFR", + "BUFR_X1Y5": "BUFR", + "BUFR_X1Y6": "BUFR", + "BUFR_X1Y7": "BUFR", + "IDELAYCTRL_X1Y1": "IDELAYCTRL" + }, + "type": "HCLK_IOI" + }, + "HCLK_L_BOT_UTURN_X74Y130": { + "bits": {}, + "grid_x": 74, + "grid_y": 78, + "sites": {}, + "type": "HCLK_L_BOT_UTURN" + }, + "HCLK_L_X100Y26": { + "bits": {}, + "grid_x": 100, + "grid_y": 182, + "segment": "SEG_HCLK_L_X100Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X100Y78": { + "bits": {}, + "grid_x": 100, + "grid_y": 130, + "segment": "SEG_HCLK_L_X100Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X104Y26": { + "bits": {}, + "grid_x": 104, + "grid_y": 182, + "segment": "SEG_HCLK_L_X104Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X104Y78": { + "bits": {}, + "grid_x": 104, + "grid_y": 130, + "segment": "SEG_HCLK_L_X104Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X111Y26": { + "bits": {}, + "grid_x": 111, + "grid_y": 182, + "segment": "SEG_HCLK_L_X111Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X111Y78": { + "bits": {}, + "grid_x": 111, + "grid_y": 130, + "segment": "SEG_HCLK_L_X111Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X11Y130": { + "bits": {}, + "grid_x": 11, + "grid_y": 78, + "segment": "SEG_HCLK_L_X11Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X11Y182": { + "bits": {}, + "grid_x": 11, + "grid_y": 26, + "segment": "SEG_HCLK_L_X11Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X11Y26": { + "bits": {}, + "grid_x": 11, + "grid_y": 182, + "segment": "SEG_HCLK_L_X11Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X11Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 11, + "grid_y": 130, + "segment": "SEG_HCLK_L_X11Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X15Y130": { + "bits": {}, + "grid_x": 15, + "grid_y": 78, + "segment": "SEG_HCLK_L_X15Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X15Y182": { + "bits": {}, + "grid_x": 15, + "grid_y": 26, + "segment": "SEG_HCLK_L_X15Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X15Y26": { + "bits": {}, + "grid_x": 15, + "grid_y": 182, + "segment": "SEG_HCLK_L_X15Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X15Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 15, + "grid_y": 130, + "segment": "SEG_HCLK_L_X15Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X21Y130": { + "bits": {}, + "grid_x": 21, + "grid_y": 78, + "segment": "SEG_HCLK_L_X21Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X21Y182": { + "bits": {}, + "grid_x": 21, + "grid_y": 26, + "segment": "SEG_HCLK_L_X21Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X21Y26": { + "bits": {}, + "grid_x": 21, + "grid_y": 182, + "segment": "SEG_HCLK_L_X21Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X21Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 21, + "grid_y": 130, + "segment": "SEG_HCLK_L_X21Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X25Y130": { + "bits": {}, + "grid_x": 25, + "grid_y": 78, + "segment": "SEG_HCLK_L_X25Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X25Y182": { + "bits": {}, + "grid_x": 25, + "grid_y": 26, + "segment": "SEG_HCLK_L_X25Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X25Y26": { + "bits": {}, + "grid_x": 25, + "grid_y": 182, + "segment": "SEG_HCLK_L_X25Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X25Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 25, + "grid_y": 130, + "segment": "SEG_HCLK_L_X25Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X31Y130": { + "bits": {}, + "grid_x": 31, + "grid_y": 78, + "segment": "SEG_HCLK_L_X31Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X31Y182": { + "bits": {}, + "grid_x": 31, + "grid_y": 26, + "segment": "SEG_HCLK_L_X31Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X31Y26": { + "bits": {}, + "grid_x": 31, + "grid_y": 182, + "segment": "SEG_HCLK_L_X31Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X31Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 31, + "grid_y": 130, + "segment": "SEG_HCLK_L_X31Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X35Y130": { + "bits": {}, + "grid_x": 35, + "grid_y": 78, + "segment": "SEG_HCLK_L_X35Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X35Y182": { + "bits": {}, + "grid_x": 35, + "grid_y": 26, + "segment": "SEG_HCLK_L_X35Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X35Y26": { + "bits": {}, + "grid_x": 35, + "grid_y": 182, + "segment": "SEG_HCLK_L_X35Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X35Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 35, + "grid_y": 130, + "segment": "SEG_HCLK_L_X35Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X41Y130": { + "bits": {}, + "grid_x": 41, + "grid_y": 78, + "segment": "SEG_HCLK_L_X41Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X41Y182": { + "bits": {}, + "grid_x": 41, + "grid_y": 26, + "segment": "SEG_HCLK_L_X41Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X41Y26": { + "bits": {}, + "grid_x": 41, + "grid_y": 182, + "segment": "SEG_HCLK_L_X41Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X41Y78": { + "bits": {}, + "grid_x": 41, + "grid_y": 130, + "segment": "SEG_HCLK_L_X41Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X45Y130": { + "bits": {}, + "grid_x": 45, + "grid_y": 78, + "segment": "SEG_HCLK_L_X45Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X45Y182": { + "bits": {}, + "grid_x": 45, + "grid_y": 26, + "segment": "SEG_HCLK_L_X45Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X45Y26": { + "bits": {}, + "grid_x": 45, + "grid_y": 182, + "segment": "SEG_HCLK_L_X45Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X45Y78": { + "bits": {}, + "grid_x": 45, + "grid_y": 130, + "segment": "SEG_HCLK_L_X45Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X4Y130": { + "bits": {}, + "grid_x": 4, + "grid_y": 78, + "segment": "SEG_HCLK_L_X4Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X4Y182": { + "bits": {}, + "grid_x": 4, + "grid_y": 26, + "segment": "SEG_HCLK_L_X4Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X4Y26": { + "bits": {}, + "grid_x": 4, + "grid_y": 182, + "segment": "SEG_HCLK_L_X4Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X4Y78": { + "bits": {}, + "grid_x": 4, + "grid_y": 130, + "segment": "SEG_HCLK_L_X4Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X51Y182": { + "bits": {}, + "grid_x": 51, + "grid_y": 26, + "segment": "SEG_HCLK_L_X51Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X51Y26": { + "bits": {}, + "grid_x": 51, + "grid_y": 182, + "segment": "SEG_HCLK_L_X51Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X55Y182": { + "bits": {}, + "grid_x": 55, + "grid_y": 26, + "segment": "SEG_HCLK_L_X55Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X55Y26": { + "bits": {}, + "grid_x": 55, + "grid_y": 182, + "segment": "SEG_HCLK_L_X55Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X59Y182": { + "bits": {}, + "grid_x": 59, + "grid_y": 26, + "segment": "SEG_HCLK_L_X59Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X59Y26": { + "bits": {}, + "grid_x": 59, + "grid_y": 182, + "segment": "SEG_HCLK_L_X59Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X64Y130": { + "bits": {}, + "grid_x": 64, + "grid_y": 78, + "segment": "SEG_HCLK_L_X64Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X64Y182": { + "bits": {}, + "grid_x": 64, + "grid_y": 26, + "segment": "SEG_HCLK_L_X64Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X64Y26": { + "bits": {}, + "grid_x": 64, + "grid_y": 182, + "segment": "SEG_HCLK_L_X64Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X64Y78": { + "bits": {}, + "grid_x": 64, + "grid_y": 130, + "segment": "SEG_HCLK_L_X64Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X70Y130": { + "bits": {}, + "grid_x": 70, + "grid_y": 78, + "segment": "SEG_HCLK_L_X70Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X70Y182": { + "bits": {}, + "grid_x": 70, + "grid_y": 26, + "segment": "SEG_HCLK_L_X70Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X70Y26": { + "bits": {}, + "grid_x": 70, + "grid_y": 182, + "segment": "SEG_HCLK_L_X70Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X70Y78": { + "bits": {}, + "grid_x": 70, + "grid_y": 130, + "segment": "SEG_HCLK_L_X70Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X74Y182": { + "bits": {}, + "grid_x": 74, + "grid_y": 26, + "segment": "SEG_HCLK_L_X74Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X74Y26": { + "bits": {}, + "grid_x": 74, + "grid_y": 182, + "segment": "SEG_HCLK_L_X74Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X74Y78": { + "bits": {}, + "grid_x": 74, + "grid_y": 130, + "segment": "SEG_HCLK_L_X74Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X79Y130": { + "bits": {}, + "grid_x": 79, + "grid_y": 78, + "segment": "SEG_HCLK_L_X79Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X79Y182": { + "bits": {}, + "grid_x": 79, + "grid_y": 26, + "segment": "SEG_HCLK_L_X79Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X79Y26": { + "bits": {}, + "grid_x": 79, + "grid_y": 182, + "segment": "SEG_HCLK_L_X79Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X79Y78": { + "bits": {}, + "grid_x": 79, + "grid_y": 130, + "segment": "SEG_HCLK_L_X79Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X84Y130": { + "bits": {}, + "grid_x": 84, + "grid_y": 78, + "segment": "SEG_HCLK_L_X84Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X84Y182": { + "bits": {}, + "grid_x": 84, + "grid_y": 26, + "segment": "SEG_HCLK_L_X84Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X84Y26": { + "bits": {}, + "grid_x": 84, + "grid_y": 182, + "segment": "SEG_HCLK_L_X84Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X84Y78": { + "bits": {}, + "grid_x": 84, + "grid_y": 130, + "segment": "SEG_HCLK_L_X84Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X89Y130": { + "bits": {}, + "grid_x": 89, + "grid_y": 78, + "segment": "SEG_HCLK_L_X89Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X89Y182": { + "bits": {}, + "grid_x": 89, + "grid_y": 26, + "segment": "SEG_HCLK_L_X89Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X89Y26": { + "bits": {}, + "grid_x": 89, + "grid_y": 182, + "segment": "SEG_HCLK_L_X89Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X89Y78": { + "bits": {}, + "grid_x": 89, + "grid_y": 130, + "segment": "SEG_HCLK_L_X89Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X94Y130": { + "bits": {}, + "grid_x": 94, + "grid_y": 78, + "segment": "SEG_HCLK_L_X94Y130", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X94Y182": { + "bits": {}, + "grid_x": 94, + "grid_y": 26, + "segment": "SEG_HCLK_L_X94Y182", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X94Y26": { + "bits": {}, + "grid_x": 94, + "grid_y": 182, + "segment": "SEG_HCLK_L_X94Y26", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_L_X94Y78": { + "bits": {}, + "grid_x": 94, + "grid_y": 130, + "segment": "SEG_HCLK_L_X94Y78", + "segment_type": "hclk_l", + "sites": {}, + "type": "HCLK_L" + }, + "HCLK_R_BOT_UTURN_X75Y130": { + "bits": {}, + "grid_x": 75, + "grid_y": 78, + "sites": {}, + "type": "HCLK_R_BOT_UTURN" + }, + "HCLK_R_X101Y26": { + "bits": {}, + "grid_x": 101, + "grid_y": 182, + "segment": "SEG_HCLK_R_X101Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X101Y78": { + "bits": {}, + "grid_x": 101, + "grid_y": 130, + "segment": "SEG_HCLK_R_X101Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X105Y26": { + "bits": {}, + "grid_x": 105, + "grid_y": 182, + "segment": "SEG_HCLK_R_X105Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X105Y78": { + "bits": {}, + "grid_x": 105, + "grid_y": 130, + "segment": "SEG_HCLK_R_X105Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X112Y26": { + "bits": {}, + "grid_x": 112, + "grid_y": 182, + "segment": "SEG_HCLK_R_X112Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X112Y78": { + "bits": {}, + "grid_x": 112, + "grid_y": 130, + "segment": "SEG_HCLK_R_X112Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X12Y130": { + "bits": {}, + "grid_x": 12, + "grid_y": 78, + "segment": "SEG_HCLK_R_X12Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X12Y182": { + "bits": {}, + "grid_x": 12, + "grid_y": 26, + "segment": "SEG_HCLK_R_X12Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X12Y26": { + "bits": {}, + "grid_x": 12, + "grid_y": 182, + "segment": "SEG_HCLK_R_X12Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X12Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 12, + "grid_y": 130, + "segment": "SEG_HCLK_R_X12Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X16Y130": { + "bits": {}, + "grid_x": 16, + "grid_y": 78, + "segment": "SEG_HCLK_R_X16Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X16Y182": { + "bits": {}, + "grid_x": 16, + "grid_y": 26, + "segment": "SEG_HCLK_R_X16Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X16Y26": { + "bits": {}, + "grid_x": 16, + "grid_y": 182, + "segment": "SEG_HCLK_R_X16Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X16Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 16, + "grid_y": 130, + "segment": "SEG_HCLK_R_X16Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X22Y130": { + "bits": {}, + "grid_x": 22, + "grid_y": 78, + "segment": "SEG_HCLK_R_X22Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X22Y182": { + "bits": {}, + "grid_x": 22, + "grid_y": 26, + "segment": "SEG_HCLK_R_X22Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X22Y26": { + "bits": {}, + "grid_x": 22, + "grid_y": 182, + "segment": "SEG_HCLK_R_X22Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X22Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 22, + "grid_y": 130, + "segment": "SEG_HCLK_R_X22Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X26Y130": { + "bits": {}, + "grid_x": 26, + "grid_y": 78, + "segment": "SEG_HCLK_R_X26Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X26Y182": { + "bits": {}, + "grid_x": 26, + "grid_y": 26, + "segment": "SEG_HCLK_R_X26Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X26Y26": { + "bits": {}, + "grid_x": 26, + "grid_y": 182, + "segment": "SEG_HCLK_R_X26Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X26Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 26, + "grid_y": 130, + "segment": "SEG_HCLK_R_X26Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X32Y130": { + "bits": {}, + "grid_x": 32, + "grid_y": 78, + "segment": "SEG_HCLK_R_X32Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X32Y182": { + "bits": {}, + "grid_x": 32, + "grid_y": 26, + "segment": "SEG_HCLK_R_X32Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X32Y26": { + "bits": {}, + "grid_x": 32, + "grid_y": 182, + "segment": "SEG_HCLK_R_X32Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X32Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 32, + "grid_y": 130, + "segment": "SEG_HCLK_R_X32Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X36Y130": { + "bits": {}, + "grid_x": 36, + "grid_y": 78, + "segment": "SEG_HCLK_R_X36Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X36Y182": { + "bits": {}, + "grid_x": 36, + "grid_y": 26, + "segment": "SEG_HCLK_R_X36Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X36Y26": { + "bits": {}, + "grid_x": 36, + "grid_y": 182, + "segment": "SEG_HCLK_R_X36Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X36Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 36, + "grid_y": 130, + "segment": "SEG_HCLK_R_X36Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X42Y130": { + "bits": {}, + "grid_x": 42, + "grid_y": 78, + "segment": "SEG_HCLK_R_X42Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X42Y182": { + "bits": {}, + "grid_x": 42, + "grid_y": 26, + "segment": "SEG_HCLK_R_X42Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X42Y26": { + "bits": {}, + "grid_x": 42, + "grid_y": 182, + "segment": "SEG_HCLK_R_X42Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X42Y78": { + "bits": {}, + "grid_x": 42, + "grid_y": 130, + "segment": "SEG_HCLK_R_X42Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X46Y130": { + "bits": {}, + "grid_x": 46, + "grid_y": 78, + "segment": "SEG_HCLK_R_X46Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X46Y182": { + "bits": {}, + "grid_x": 46, + "grid_y": 26, + "segment": "SEG_HCLK_R_X46Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X46Y26": { + "bits": {}, + "grid_x": 46, + "grid_y": 182, + "segment": "SEG_HCLK_R_X46Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X46Y78": { + "bits": {}, + "grid_x": 46, + "grid_y": 130, + "segment": "SEG_HCLK_R_X46Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X52Y182": { + "bits": {}, + "grid_x": 52, + "grid_y": 26, + "segment": "SEG_HCLK_R_X52Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X52Y26": { + "bits": {}, + "grid_x": 52, + "grid_y": 182, + "segment": "SEG_HCLK_R_X52Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X56Y182": { + "bits": {}, + "grid_x": 56, + "grid_y": 26, + "segment": "SEG_HCLK_R_X56Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X56Y26": { + "bits": {}, + "grid_x": 56, + "grid_y": 182, + "segment": "SEG_HCLK_R_X56Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X5Y130": { + "bits": {}, + "grid_x": 5, + "grid_y": 78, + "segment": "SEG_HCLK_R_X5Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X5Y182": { + "bits": {}, + "grid_x": 5, + "grid_y": 26, + "segment": "SEG_HCLK_R_X5Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X5Y26": { + "bits": {}, + "grid_x": 5, + "grid_y": 182, + "segment": "SEG_HCLK_R_X5Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X5Y78": { + "bits": {}, + "grid_x": 5, + "grid_y": 130, + "segment": "SEG_HCLK_R_X5Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X60Y182": { + "bits": {}, + "grid_x": 60, + "grid_y": 26, + "segment": "SEG_HCLK_R_X60Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X60Y26": { + "bits": {}, + "grid_x": 60, + "grid_y": 182, + "segment": "SEG_HCLK_R_X60Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X65Y130": { + "bits": {}, + "grid_x": 65, + "grid_y": 78, + "segment": "SEG_HCLK_R_X65Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X65Y182": { + "bits": {}, + "grid_x": 65, + "grid_y": 26, + "segment": "SEG_HCLK_R_X65Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X65Y26": { + "bits": {}, + "grid_x": 65, + "grid_y": 182, + "segment": "SEG_HCLK_R_X65Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X65Y78": { + "bits": {}, + "grid_x": 65, + "grid_y": 130, + "segment": "SEG_HCLK_R_X65Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X71Y130": { + "bits": {}, + "grid_x": 71, + "grid_y": 78, + "segment": "SEG_HCLK_R_X71Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X71Y182": { + "bits": {}, + "grid_x": 71, + "grid_y": 26, + "segment": "SEG_HCLK_R_X71Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X71Y26": { + "bits": {}, + "grid_x": 71, + "grid_y": 182, + "segment": "SEG_HCLK_R_X71Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X71Y78": { + "bits": {}, + "grid_x": 71, + "grid_y": 130, + "segment": "SEG_HCLK_R_X71Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X75Y182": { + "bits": {}, + "grid_x": 75, + "grid_y": 26, + "segment": "SEG_HCLK_R_X75Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X75Y26": { + "bits": {}, + "grid_x": 75, + "grid_y": 182, + "segment": "SEG_HCLK_R_X75Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X75Y78": { + "bits": {}, + "grid_x": 75, + "grid_y": 130, + "segment": "SEG_HCLK_R_X75Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X80Y130": { + "bits": {}, + "grid_x": 80, + "grid_y": 78, + "segment": "SEG_HCLK_R_X80Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X80Y182": { + "bits": {}, + "grid_x": 80, + "grid_y": 26, + "segment": "SEG_HCLK_R_X80Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X80Y26": { + "bits": {}, + "grid_x": 80, + "grid_y": 182, + "segment": "SEG_HCLK_R_X80Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X80Y78": { + "bits": {}, + "grid_x": 80, + "grid_y": 130, + "segment": "SEG_HCLK_R_X80Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X85Y130": { + "bits": {}, + "grid_x": 85, + "grid_y": 78, + "segment": "SEG_HCLK_R_X85Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X85Y182": { + "bits": {}, + "grid_x": 85, + "grid_y": 26, + "segment": "SEG_HCLK_R_X85Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X85Y26": { + "bits": {}, + "grid_x": 85, + "grid_y": 182, + "segment": "SEG_HCLK_R_X85Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X85Y78": { + "bits": {}, + "grid_x": 85, + "grid_y": 130, + "segment": "SEG_HCLK_R_X85Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X90Y130": { + "bits": {}, + "grid_x": 90, + "grid_y": 78, + "segment": "SEG_HCLK_R_X90Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X90Y182": { + "bits": {}, + "grid_x": 90, + "grid_y": 26, + "segment": "SEG_HCLK_R_X90Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X90Y26": { + "bits": {}, + "grid_x": 90, + "grid_y": 182, + "segment": "SEG_HCLK_R_X90Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X90Y78": { + "bits": {}, + "grid_x": 90, + "grid_y": 130, + "segment": "SEG_HCLK_R_X90Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X95Y130": { + "bits": {}, + "grid_x": 95, + "grid_y": 78, + "segment": "SEG_HCLK_R_X95Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X95Y182": { + "bits": {}, + "grid_x": 95, + "grid_y": 26, + "segment": "SEG_HCLK_R_X95Y182", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X95Y26": { + "bits": {}, + "grid_x": 95, + "grid_y": 182, + "segment": "SEG_HCLK_R_X95Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X95Y78": { + "bits": {}, + "grid_x": 95, + "grid_y": 130, + "segment": "SEG_HCLK_R_X95Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_TERM_GTX_X98Y130": { + "bits": {}, + "grid_x": 98, + "grid_y": 78, + "sites": {}, + "type": "HCLK_TERM_GTX" + }, + "HCLK_TERM_GTX_X98Y182": { + "bits": {}, + "grid_x": 98, + "grid_y": 26, + "sites": {}, + "type": "HCLK_TERM_GTX" + }, + "HCLK_TERM_X114Y26": { + "bits": {}, + "grid_x": 114, + "grid_y": 182, + "sites": {}, + "type": "HCLK_TERM" + }, + "HCLK_TERM_X114Y78": { + "bits": {}, + "grid_x": 114, + "grid_y": 130, + "sites": {}, + "type": "HCLK_TERM" + }, + "HCLK_TERM_X2Y130": { + "bits": {}, + "grid_x": 2, + "grid_y": 78, + "sites": {}, + "type": "HCLK_TERM" + }, + "HCLK_TERM_X2Y182": { + "bits": {}, + "grid_x": 2, + "grid_y": 26, + "sites": {}, + "type": "HCLK_TERM" + }, + "HCLK_TERM_X2Y26": { + "bits": {}, + "grid_x": 2, + "grid_y": 182, + "sites": {}, + "type": "HCLK_TERM" + }, + "HCLK_TERM_X2Y78": { + "bits": {}, + "grid_x": 2, + "grid_y": 130, + "sites": {}, + "type": "HCLK_TERM" + }, + "HCLK_VBRK_X107Y26": { + "bits": {}, + "grid_x": 107, + "grid_y": 182, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X107Y78": { + "bits": {}, + "grid_x": 107, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X18Y130": { + "bits": {}, + "grid_x": 18, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X18Y182": { + "bits": {}, + "grid_x": 18, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X18Y26": { + "bits": {}, + "grid_x": 18, + "grid_y": 182, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X18Y78": { + "bits": {}, + "grid_x": 18, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X29Y130": { + "bits": {}, + "grid_x": 29, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X29Y182": { + "bits": {}, + "grid_x": 29, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X29Y26": { + "bits": {}, + "grid_x": 29, + "grid_y": 182, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X29Y78": { + "bits": {}, + "grid_x": 29, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X38Y130": { + "bits": {}, + "grid_x": 38, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X38Y182": { + "bits": {}, + "grid_x": 38, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X38Y26": { + "bits": {}, + "grid_x": 38, + "grid_y": 182, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X38Y78": { + "bits": {}, + "grid_x": 38, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X49Y130": { + "bits": {}, + "grid_x": 49, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X49Y182": { + "bits": {}, + "grid_x": 49, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X49Y26": { + "bits": {}, + "grid_x": 49, + "grid_y": 182, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X49Y78": { + "bits": {}, + "grid_x": 49, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X68Y130": { + "bits": {}, + "grid_x": 68, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X68Y182": { + "bits": {}, + "grid_x": 68, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X68Y26": { + "bits": {}, + "grid_x": 68, + "grid_y": 182, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X68Y78": { + "bits": {}, + "grid_x": 68, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X82Y130": { + "bits": {}, + "grid_x": 82, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X82Y182": { + "bits": {}, + "grid_x": 82, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X82Y26": { + "bits": {}, + "grid_x": 82, + "grid_y": 182, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X82Y78": { + "bits": {}, + "grid_x": 82, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X92Y130": { + "bits": {}, + "grid_x": 92, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X92Y182": { + "bits": {}, + "grid_x": 92, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X92Y26": { + "bits": {}, + "grid_x": 92, + "grid_y": 182, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X92Y78": { + "bits": {}, + "grid_x": 92, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X98Y26": { + "bits": {}, + "grid_x": 98, + "grid_y": 182, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X98Y78": { + "bits": {}, + "grid_x": 98, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X9Y130": { + "bits": {}, + "grid_x": 9, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X9Y182": { + "bits": {}, + "grid_x": 9, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X9Y26": { + "bits": {}, + "grid_x": 9, + "grid_y": 182, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X9Y78": { + "bits": {}, + "grid_x": 9, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VFRAME_X62Y130": { + "bits": {}, + "grid_x": 62, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VFRAME" + }, + "HCLK_VFRAME_X62Y182": { + "bits": {}, + "grid_x": 62, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VFRAME" + }, + "HCLK_VFRAME_X62Y26": { + "bits": {}, + "grid_x": 62, + "grid_y": 182, + "sites": {}, + "type": "HCLK_VFRAME" + }, + "HCLK_VFRAME_X62Y78": { + "bits": {}, + "grid_x": 62, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VFRAME" + }, + "INT_FEEDTHRU_1_X50Y100": { + "bits": {}, + "grid_x": 50, + "grid_y": 108, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y101": { + "bits": {}, + "grid_x": 50, + "grid_y": 107, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y102": { + "bits": {}, + "grid_x": 50, + "grid_y": 106, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y103": { + "bits": {}, + "grid_x": 50, + "grid_y": 105, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y105": { + "bits": {}, + "grid_x": 50, + "grid_y": 103, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y106": { + "bits": {}, + "grid_x": 50, + "grid_y": 102, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y107": { + "bits": {}, + "grid_x": 50, + "grid_y": 101, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y108": { + "bits": {}, + "grid_x": 50, + "grid_y": 100, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y109": { + "bits": {}, + "grid_x": 50, + "grid_y": 99, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y110": { + "bits": {}, + "grid_x": 50, + "grid_y": 98, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y111": { + "bits": {}, + "grid_x": 50, + "grid_y": 97, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y112": { + "bits": {}, + "grid_x": 50, + "grid_y": 96, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y113": { + "bits": {}, + "grid_x": 50, + "grid_y": 95, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y114": { + "bits": {}, + "grid_x": 50, + "grid_y": 94, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y115": { + "bits": {}, + "grid_x": 50, + "grid_y": 93, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y116": { + "bits": {}, + "grid_x": 50, + "grid_y": 92, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y117": { + "bits": {}, + "grid_x": 50, + "grid_y": 91, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y118": { + "bits": {}, + "grid_x": 50, + "grid_y": 90, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y119": { + "bits": {}, + "grid_x": 50, + "grid_y": 89, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y120": { + "bits": {}, + "grid_x": 50, + "grid_y": 88, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y121": { + "bits": {}, + "grid_x": 50, + "grid_y": 87, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y122": { + "bits": {}, + "grid_x": 50, + "grid_y": 86, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y123": { + "bits": {}, + "grid_x": 50, + "grid_y": 85, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y124": { + "bits": {}, + "grid_x": 50, + "grid_y": 84, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y125": { + "bits": {}, + "grid_x": 50, + "grid_y": 83, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y126": { + "bits": {}, + "grid_x": 50, + "grid_y": 82, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y127": { + "bits": {}, + "grid_x": 50, + "grid_y": 81, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y128": { + "bits": {}, + "grid_x": 50, + "grid_y": 80, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y129": { + "bits": {}, + "grid_x": 50, + "grid_y": 79, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y131": { + "bits": {}, + "grid_x": 50, + "grid_y": 77, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y132": { + "bits": {}, + "grid_x": 50, + "grid_y": 76, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y133": { + "bits": {}, + "grid_x": 50, + "grid_y": 75, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y134": { + "bits": {}, + "grid_x": 50, + "grid_y": 74, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y135": { + "bits": {}, + "grid_x": 50, + "grid_y": 73, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y136": { + "bits": {}, + "grid_x": 50, + "grid_y": 72, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y137": { + "bits": {}, + "grid_x": 50, + "grid_y": 71, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y138": { + "bits": {}, + "grid_x": 50, + "grid_y": 70, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y139": { + "bits": {}, + "grid_x": 50, + "grid_y": 69, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y140": { + "bits": {}, + "grid_x": 50, + "grid_y": 68, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y141": { + "bits": {}, + "grid_x": 50, + "grid_y": 67, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y142": { + "bits": {}, + "grid_x": 50, + "grid_y": 66, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y143": { + "bits": {}, + "grid_x": 50, + "grid_y": 65, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y144": { + "bits": {}, + "grid_x": 50, + "grid_y": 64, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y145": { + "bits": {}, + "grid_x": 50, + "grid_y": 63, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y146": { + "bits": {}, + "grid_x": 50, + "grid_y": 62, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y147": { + "bits": {}, + "grid_x": 50, + "grid_y": 61, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y148": { + "bits": {}, + "grid_x": 50, + "grid_y": 60, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y149": { + "bits": {}, + "grid_x": 50, + "grid_y": 59, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y150": { + "bits": {}, + "grid_x": 50, + "grid_y": 58, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y151": { + "bits": {}, + "grid_x": 50, + "grid_y": 57, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y152": { + "bits": {}, + "grid_x": 50, + "grid_y": 56, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y153": { + "bits": {}, + "grid_x": 50, + "grid_y": 55, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y154": { + "bits": {}, + "grid_x": 50, + "grid_y": 54, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y155": { + "bits": {}, + "grid_x": 50, + "grid_y": 53, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y53": { + "bits": {}, + "grid_x": 50, + "grid_y": 155, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y54": { + "bits": {}, + "grid_x": 50, + "grid_y": 154, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y55": { + "bits": {}, + "grid_x": 50, + "grid_y": 153, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y56": { + "bits": {}, + "grid_x": 50, + "grid_y": 152, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y57": { + "bits": {}, + "grid_x": 50, + "grid_y": 151, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y58": { + "bits": {}, + "grid_x": 50, + "grid_y": 150, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y59": { + "bits": {}, + "grid_x": 50, + "grid_y": 149, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y60": { + "bits": {}, + "grid_x": 50, + "grid_y": 148, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y61": { + "bits": {}, + "grid_x": 50, + "grid_y": 147, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y62": { + "bits": {}, + "grid_x": 50, + "grid_y": 146, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y63": { + "bits": {}, + "grid_x": 50, + "grid_y": 145, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y64": { + "bits": {}, + "grid_x": 50, + "grid_y": 144, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y65": { + "bits": {}, + "grid_x": 50, + "grid_y": 143, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y66": { + "bits": {}, + "grid_x": 50, + "grid_y": 142, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y67": { + "bits": {}, + "grid_x": 50, + "grid_y": 141, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y68": { + "bits": {}, + "grid_x": 50, + "grid_y": 140, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y69": { + "bits": {}, + "grid_x": 50, + "grid_y": 139, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y70": { + "bits": {}, + "grid_x": 50, + "grid_y": 138, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y71": { + "bits": {}, + "grid_x": 50, + "grid_y": 137, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y72": { + "bits": {}, + "grid_x": 50, + "grid_y": 136, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y73": { + "bits": {}, + "grid_x": 50, + "grid_y": 135, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y74": { + "bits": {}, + "grid_x": 50, + "grid_y": 134, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y75": { + "bits": {}, + "grid_x": 50, + "grid_y": 133, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y76": { + "bits": {}, + "grid_x": 50, + "grid_y": 132, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y77": { + "bits": {}, + "grid_x": 50, + "grid_y": 131, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y79": { + "bits": {}, + "grid_x": 50, + "grid_y": 129, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y80": { + "bits": {}, + "grid_x": 50, + "grid_y": 128, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y81": { + "bits": {}, + "grid_x": 50, + "grid_y": 127, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y82": { + "bits": {}, + "grid_x": 50, + "grid_y": 126, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y83": { + "bits": {}, + "grid_x": 50, + "grid_y": 125, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y84": { + "bits": {}, + "grid_x": 50, + "grid_y": 124, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y85": { + "bits": {}, + "grid_x": 50, + "grid_y": 123, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y86": { + "bits": {}, + "grid_x": 50, + "grid_y": 122, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y87": { + "bits": {}, + "grid_x": 50, + "grid_y": 121, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y88": { + "bits": {}, + "grid_x": 50, + "grid_y": 120, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y89": { + "bits": {}, + "grid_x": 50, + "grid_y": 119, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y90": { + "bits": {}, + "grid_x": 50, + "grid_y": 118, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y91": { + "bits": {}, + "grid_x": 50, + "grid_y": 117, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y92": { + "bits": {}, + "grid_x": 50, + "grid_y": 116, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y93": { + "bits": {}, + "grid_x": 50, + "grid_y": 115, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y94": { + "bits": {}, + "grid_x": 50, + "grid_y": 114, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y95": { + "bits": {}, + "grid_x": 50, + "grid_y": 113, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y96": { + "bits": {}, + "grid_x": 50, + "grid_y": 112, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y97": { + "bits": {}, + "grid_x": 50, + "grid_y": 111, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y98": { + "bits": {}, + "grid_x": 50, + "grid_y": 110, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X50Y99": { + "bits": {}, + "grid_x": 50, + "grid_y": 109, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y100": { + "bits": {}, + "grid_x": 53, + "grid_y": 108, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y101": { + "bits": {}, + "grid_x": 53, + "grid_y": 107, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y102": { + "bits": {}, + "grid_x": 53, + "grid_y": 106, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y103": { + "bits": {}, + "grid_x": 53, + "grid_y": 105, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y105": { + "bits": {}, + "grid_x": 53, + "grid_y": 103, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y106": { + "bits": {}, + "grid_x": 53, + "grid_y": 102, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y107": { + "bits": {}, + "grid_x": 53, + "grid_y": 101, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y108": { + "bits": {}, + "grid_x": 53, + "grid_y": 100, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y109": { + "bits": {}, + "grid_x": 53, + "grid_y": 99, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y110": { + "bits": {}, + "grid_x": 53, + "grid_y": 98, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y111": { + "bits": {}, + "grid_x": 53, + "grid_y": 97, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y112": { + "bits": {}, + "grid_x": 53, + "grid_y": 96, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y113": { + "bits": {}, + "grid_x": 53, + "grid_y": 95, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y114": { + "bits": {}, + "grid_x": 53, + "grid_y": 94, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y115": { + "bits": {}, + "grid_x": 53, + "grid_y": 93, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y116": { + "bits": {}, + "grid_x": 53, + "grid_y": 92, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y117": { + "bits": {}, + "grid_x": 53, + "grid_y": 91, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y118": { + "bits": {}, + "grid_x": 53, + "grid_y": 90, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y119": { + "bits": {}, + "grid_x": 53, + "grid_y": 89, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y120": { + "bits": {}, + "grid_x": 53, + "grid_y": 88, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y121": { + "bits": {}, + "grid_x": 53, + "grid_y": 87, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y122": { + "bits": {}, + "grid_x": 53, + "grid_y": 86, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y123": { + "bits": {}, + "grid_x": 53, + "grid_y": 85, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y124": { + "bits": {}, + "grid_x": 53, + "grid_y": 84, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y125": { + "bits": {}, + "grid_x": 53, + "grid_y": 83, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y126": { + "bits": {}, + "grid_x": 53, + "grid_y": 82, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y127": { + "bits": {}, + "grid_x": 53, + "grid_y": 81, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y128": { + "bits": {}, + "grid_x": 53, + "grid_y": 80, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y129": { + "bits": {}, + "grid_x": 53, + "grid_y": 79, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y131": { + "bits": {}, + "grid_x": 53, + "grid_y": 77, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y132": { + "bits": {}, + "grid_x": 53, + "grid_y": 76, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y133": { + "bits": {}, + "grid_x": 53, + "grid_y": 75, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y134": { + "bits": {}, + "grid_x": 53, + "grid_y": 74, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y135": { + "bits": {}, + "grid_x": 53, + "grid_y": 73, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y136": { + "bits": {}, + "grid_x": 53, + "grid_y": 72, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y137": { + "bits": {}, + "grid_x": 53, + "grid_y": 71, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y138": { + "bits": {}, + "grid_x": 53, + "grid_y": 70, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y139": { + "bits": {}, + "grid_x": 53, + "grid_y": 69, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y140": { + "bits": {}, + "grid_x": 53, + "grid_y": 68, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y141": { + "bits": {}, + "grid_x": 53, + "grid_y": 67, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y142": { + "bits": {}, + "grid_x": 53, + "grid_y": 66, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y143": { + "bits": {}, + "grid_x": 53, + "grid_y": 65, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y144": { + "bits": {}, + "grid_x": 53, + "grid_y": 64, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y145": { + "bits": {}, + "grid_x": 53, + "grid_y": 63, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y146": { + "bits": {}, + "grid_x": 53, + "grid_y": 62, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y147": { + "bits": {}, + "grid_x": 53, + "grid_y": 61, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y148": { + "bits": {}, + "grid_x": 53, + "grid_y": 60, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y149": { + "bits": {}, + "grid_x": 53, + "grid_y": 59, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y150": { + "bits": {}, + "grid_x": 53, + "grid_y": 58, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y151": { + "bits": {}, + "grid_x": 53, + "grid_y": 57, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y152": { + "bits": {}, + "grid_x": 53, + "grid_y": 56, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y153": { + "bits": {}, + "grid_x": 53, + "grid_y": 55, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y154": { + "bits": {}, + "grid_x": 53, + "grid_y": 54, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y155": { + "bits": {}, + "grid_x": 53, + "grid_y": 53, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y53": { + "bits": {}, + "grid_x": 53, + "grid_y": 155, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y54": { + "bits": {}, + "grid_x": 53, + "grid_y": 154, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y55": { + "bits": {}, + "grid_x": 53, + "grid_y": 153, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y56": { + "bits": {}, + "grid_x": 53, + "grid_y": 152, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y57": { + "bits": {}, + "grid_x": 53, + "grid_y": 151, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y58": { + "bits": {}, + "grid_x": 53, + "grid_y": 150, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y59": { + "bits": {}, + "grid_x": 53, + "grid_y": 149, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y60": { + "bits": {}, + "grid_x": 53, + "grid_y": 148, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y61": { + "bits": {}, + "grid_x": 53, + "grid_y": 147, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y62": { + "bits": {}, + "grid_x": 53, + "grid_y": 146, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y63": { + "bits": {}, + "grid_x": 53, + "grid_y": 145, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y64": { + "bits": {}, + "grid_x": 53, + "grid_y": 144, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y65": { + "bits": {}, + "grid_x": 53, + "grid_y": 143, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y66": { + "bits": {}, + "grid_x": 53, + "grid_y": 142, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y67": { + "bits": {}, + "grid_x": 53, + "grid_y": 141, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y68": { + "bits": {}, + "grid_x": 53, + "grid_y": 140, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y69": { + "bits": {}, + "grid_x": 53, + "grid_y": 139, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y70": { + "bits": {}, + "grid_x": 53, + "grid_y": 138, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y71": { + "bits": {}, + "grid_x": 53, + "grid_y": 137, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y72": { + "bits": {}, + "grid_x": 53, + "grid_y": 136, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y73": { + "bits": {}, + "grid_x": 53, + "grid_y": 135, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y74": { + "bits": {}, + "grid_x": 53, + "grid_y": 134, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y75": { + "bits": {}, + "grid_x": 53, + "grid_y": 133, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y76": { + "bits": {}, + "grid_x": 53, + "grid_y": 132, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y77": { + "bits": {}, + "grid_x": 53, + "grid_y": 131, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y79": { + "bits": {}, + "grid_x": 53, + "grid_y": 129, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y80": { + "bits": {}, + "grid_x": 53, + "grid_y": 128, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y81": { + "bits": {}, + "grid_x": 53, + "grid_y": 127, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y82": { + "bits": {}, + "grid_x": 53, + "grid_y": 126, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y83": { + "bits": {}, + "grid_x": 53, + "grid_y": 125, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y84": { + "bits": {}, + "grid_x": 53, + "grid_y": 124, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y85": { + "bits": {}, + "grid_x": 53, + "grid_y": 123, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y86": { + "bits": {}, + "grid_x": 53, + "grid_y": 122, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y87": { + "bits": {}, + "grid_x": 53, + "grid_y": 121, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y88": { + "bits": {}, + "grid_x": 53, + "grid_y": 120, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y89": { + "bits": {}, + "grid_x": 53, + "grid_y": 119, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y90": { + "bits": {}, + "grid_x": 53, + "grid_y": 118, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y91": { + "bits": {}, + "grid_x": 53, + "grid_y": 117, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y92": { + "bits": {}, + "grid_x": 53, + "grid_y": 116, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y93": { + "bits": {}, + "grid_x": 53, + "grid_y": 115, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y94": { + "bits": {}, + "grid_x": 53, + "grid_y": 114, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y95": { + "bits": {}, + "grid_x": 53, + "grid_y": 113, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y96": { + "bits": {}, + "grid_x": 53, + "grid_y": 112, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y97": { + "bits": {}, + "grid_x": 53, + "grid_y": 111, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y98": { + "bits": {}, + "grid_x": 53, + "grid_y": 110, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X53Y99": { + "bits": {}, + "grid_x": 53, + "grid_y": 109, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y100": { + "bits": {}, + "grid_x": 54, + "grid_y": 108, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y101": { + "bits": {}, + "grid_x": 54, + "grid_y": 107, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y102": { + "bits": {}, + "grid_x": 54, + "grid_y": 106, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y103": { + "bits": {}, + "grid_x": 54, + "grid_y": 105, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y105": { + "bits": {}, + "grid_x": 54, + "grid_y": 103, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y106": { + "bits": {}, + "grid_x": 54, + "grid_y": 102, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y107": { + "bits": {}, + "grid_x": 54, + "grid_y": 101, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y108": { + "bits": {}, + "grid_x": 54, + "grid_y": 100, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y109": { + "bits": {}, + "grid_x": 54, + "grid_y": 99, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y110": { + "bits": {}, + "grid_x": 54, + "grid_y": 98, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y111": { + "bits": {}, + "grid_x": 54, + "grid_y": 97, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y112": { + "bits": {}, + "grid_x": 54, + "grid_y": 96, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y113": { + "bits": {}, + "grid_x": 54, + "grid_y": 95, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y114": { + "bits": {}, + "grid_x": 54, + "grid_y": 94, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y115": { + "bits": {}, + "grid_x": 54, + "grid_y": 93, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y116": { + "bits": {}, + "grid_x": 54, + "grid_y": 92, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y117": { + "bits": {}, + "grid_x": 54, + "grid_y": 91, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y118": { + "bits": {}, + "grid_x": 54, + "grid_y": 90, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y119": { + "bits": {}, + "grid_x": 54, + "grid_y": 89, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y120": { + "bits": {}, + "grid_x": 54, + "grid_y": 88, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y121": { + "bits": {}, + "grid_x": 54, + "grid_y": 87, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y122": { + "bits": {}, + "grid_x": 54, + "grid_y": 86, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y123": { + "bits": {}, + "grid_x": 54, + "grid_y": 85, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y124": { + "bits": {}, + "grid_x": 54, + "grid_y": 84, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y125": { + "bits": {}, + "grid_x": 54, + "grid_y": 83, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y126": { + "bits": {}, + "grid_x": 54, + "grid_y": 82, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y127": { + "bits": {}, + "grid_x": 54, + "grid_y": 81, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y128": { + "bits": {}, + "grid_x": 54, + "grid_y": 80, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y129": { + "bits": {}, + "grid_x": 54, + "grid_y": 79, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y131": { + "bits": {}, + "grid_x": 54, + "grid_y": 77, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y132": { + "bits": {}, + "grid_x": 54, + "grid_y": 76, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y133": { + "bits": {}, + "grid_x": 54, + "grid_y": 75, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y134": { + "bits": {}, + "grid_x": 54, + "grid_y": 74, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y135": { + "bits": {}, + "grid_x": 54, + "grid_y": 73, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y136": { + "bits": {}, + "grid_x": 54, + "grid_y": 72, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y137": { + "bits": {}, + "grid_x": 54, + "grid_y": 71, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y138": { + "bits": {}, + "grid_x": 54, + "grid_y": 70, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y139": { + "bits": {}, + "grid_x": 54, + "grid_y": 69, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y140": { + "bits": {}, + "grid_x": 54, + "grid_y": 68, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y141": { + "bits": {}, + "grid_x": 54, + "grid_y": 67, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y142": { + "bits": {}, + "grid_x": 54, + "grid_y": 66, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y143": { + "bits": {}, + "grid_x": 54, + "grid_y": 65, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y144": { + "bits": {}, + "grid_x": 54, + "grid_y": 64, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y145": { + "bits": {}, + "grid_x": 54, + "grid_y": 63, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y146": { + "bits": {}, + "grid_x": 54, + "grid_y": 62, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y147": { + "bits": {}, + "grid_x": 54, + "grid_y": 61, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y148": { + "bits": {}, + "grid_x": 54, + "grid_y": 60, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y149": { + "bits": {}, + "grid_x": 54, + "grid_y": 59, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y150": { + "bits": {}, + "grid_x": 54, + "grid_y": 58, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y151": { + "bits": {}, + "grid_x": 54, + "grid_y": 57, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y152": { + "bits": {}, + "grid_x": 54, + "grid_y": 56, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y153": { + "bits": {}, + "grid_x": 54, + "grid_y": 55, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y154": { + "bits": {}, + "grid_x": 54, + "grid_y": 54, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y155": { + "bits": {}, + "grid_x": 54, + "grid_y": 53, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y53": { + "bits": {}, + "grid_x": 54, + "grid_y": 155, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y54": { + "bits": {}, + "grid_x": 54, + "grid_y": 154, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y55": { + "bits": {}, + "grid_x": 54, + "grid_y": 153, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y56": { + "bits": {}, + "grid_x": 54, + "grid_y": 152, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y57": { + "bits": {}, + "grid_x": 54, + "grid_y": 151, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y58": { + "bits": {}, + "grid_x": 54, + "grid_y": 150, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y59": { + "bits": {}, + "grid_x": 54, + "grid_y": 149, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y60": { + "bits": {}, + "grid_x": 54, + "grid_y": 148, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y61": { + "bits": {}, + "grid_x": 54, + "grid_y": 147, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y62": { + "bits": {}, + "grid_x": 54, + "grid_y": 146, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y63": { + "bits": {}, + "grid_x": 54, + "grid_y": 145, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y64": { + "bits": {}, + "grid_x": 54, + "grid_y": 144, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y65": { + "bits": {}, + "grid_x": 54, + "grid_y": 143, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y66": { + "bits": {}, + "grid_x": 54, + "grid_y": 142, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y67": { + "bits": {}, + "grid_x": 54, + "grid_y": 141, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y68": { + "bits": {}, + "grid_x": 54, + "grid_y": 140, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y69": { + "bits": {}, + "grid_x": 54, + "grid_y": 139, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y70": { + "bits": {}, + "grid_x": 54, + "grid_y": 138, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y71": { + "bits": {}, + "grid_x": 54, + "grid_y": 137, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y72": { + "bits": {}, + "grid_x": 54, + "grid_y": 136, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y73": { + "bits": {}, + "grid_x": 54, + "grid_y": 135, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y74": { + "bits": {}, + "grid_x": 54, + "grid_y": 134, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y75": { + "bits": {}, + "grid_x": 54, + "grid_y": 133, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y76": { + "bits": {}, + "grid_x": 54, + "grid_y": 132, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y77": { + "bits": {}, + "grid_x": 54, + "grid_y": 131, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y79": { + "bits": {}, + "grid_x": 54, + "grid_y": 129, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y80": { + "bits": {}, + "grid_x": 54, + "grid_y": 128, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y81": { + "bits": {}, + "grid_x": 54, + "grid_y": 127, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y82": { + "bits": {}, + "grid_x": 54, + "grid_y": 126, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y83": { + "bits": {}, + "grid_x": 54, + "grid_y": 125, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y84": { + "bits": {}, + "grid_x": 54, + "grid_y": 124, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y85": { + "bits": {}, + "grid_x": 54, + "grid_y": 123, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y86": { + "bits": {}, + "grid_x": 54, + "grid_y": 122, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y87": { + "bits": {}, + "grid_x": 54, + "grid_y": 121, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y88": { + "bits": {}, + "grid_x": 54, + "grid_y": 120, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y89": { + "bits": {}, + "grid_x": 54, + "grid_y": 119, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y90": { + "bits": {}, + "grid_x": 54, + "grid_y": 118, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y91": { + "bits": {}, + "grid_x": 54, + "grid_y": 117, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y92": { + "bits": {}, + "grid_x": 54, + "grid_y": 116, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y93": { + "bits": {}, + "grid_x": 54, + "grid_y": 115, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y94": { + "bits": {}, + "grid_x": 54, + "grid_y": 114, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y95": { + "bits": {}, + "grid_x": 54, + "grid_y": 113, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y96": { + "bits": {}, + "grid_x": 54, + "grid_y": 112, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y97": { + "bits": {}, + "grid_x": 54, + "grid_y": 111, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y98": { + "bits": {}, + "grid_x": 54, + "grid_y": 110, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X54Y99": { + "bits": {}, + "grid_x": 54, + "grid_y": 109, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y100": { + "bits": {}, + "grid_x": 57, + "grid_y": 108, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y101": { + "bits": {}, + "grid_x": 57, + "grid_y": 107, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y102": { + "bits": {}, + "grid_x": 57, + "grid_y": 106, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y103": { + "bits": {}, + "grid_x": 57, + "grid_y": 105, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y105": { + "bits": {}, + "grid_x": 57, + "grid_y": 103, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y106": { + "bits": {}, + "grid_x": 57, + "grid_y": 102, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y107": { + "bits": {}, + "grid_x": 57, + "grid_y": 101, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y108": { + "bits": {}, + "grid_x": 57, + "grid_y": 100, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y109": { + "bits": {}, + "grid_x": 57, + "grid_y": 99, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y110": { + "bits": {}, + "grid_x": 57, + "grid_y": 98, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y111": { + "bits": {}, + "grid_x": 57, + "grid_y": 97, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y112": { + "bits": {}, + "grid_x": 57, + "grid_y": 96, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y113": { + "bits": {}, + "grid_x": 57, + "grid_y": 95, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y114": { + "bits": {}, + "grid_x": 57, + "grid_y": 94, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y115": { + "bits": {}, + "grid_x": 57, + "grid_y": 93, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y116": { + "bits": {}, + "grid_x": 57, + "grid_y": 92, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y117": { + "bits": {}, + "grid_x": 57, + "grid_y": 91, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y118": { + "bits": {}, + "grid_x": 57, + "grid_y": 90, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y119": { + "bits": {}, + "grid_x": 57, + "grid_y": 89, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y120": { + "bits": {}, + "grid_x": 57, + "grid_y": 88, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y121": { + "bits": {}, + "grid_x": 57, + "grid_y": 87, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y122": { + "bits": {}, + "grid_x": 57, + "grid_y": 86, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y123": { + "bits": {}, + "grid_x": 57, + "grid_y": 85, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y124": { + "bits": {}, + "grid_x": 57, + "grid_y": 84, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y125": { + "bits": {}, + "grid_x": 57, + "grid_y": 83, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y126": { + "bits": {}, + "grid_x": 57, + "grid_y": 82, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y127": { + "bits": {}, + "grid_x": 57, + "grid_y": 81, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y128": { + "bits": {}, + "grid_x": 57, + "grid_y": 80, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y129": { + "bits": {}, + "grid_x": 57, + "grid_y": 79, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y131": { + "bits": {}, + "grid_x": 57, + "grid_y": 77, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y132": { + "bits": {}, + "grid_x": 57, + "grid_y": 76, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y133": { + "bits": {}, + "grid_x": 57, + "grid_y": 75, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y134": { + "bits": {}, + "grid_x": 57, + "grid_y": 74, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y135": { + "bits": {}, + "grid_x": 57, + "grid_y": 73, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y136": { + "bits": {}, + "grid_x": 57, + "grid_y": 72, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y137": { + "bits": {}, + "grid_x": 57, + "grid_y": 71, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y138": { + "bits": {}, + "grid_x": 57, + "grid_y": 70, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y139": { + "bits": {}, + "grid_x": 57, + "grid_y": 69, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y140": { + "bits": {}, + "grid_x": 57, + "grid_y": 68, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y141": { + "bits": {}, + "grid_x": 57, + "grid_y": 67, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y142": { + "bits": {}, + "grid_x": 57, + "grid_y": 66, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y143": { + "bits": {}, + "grid_x": 57, + "grid_y": 65, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y144": { + "bits": {}, + "grid_x": 57, + "grid_y": 64, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y145": { + "bits": {}, + "grid_x": 57, + "grid_y": 63, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y146": { + "bits": {}, + "grid_x": 57, + "grid_y": 62, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y147": { + "bits": {}, + "grid_x": 57, + "grid_y": 61, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y148": { + "bits": {}, + "grid_x": 57, + "grid_y": 60, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y149": { + "bits": {}, + "grid_x": 57, + "grid_y": 59, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y150": { + "bits": {}, + "grid_x": 57, + "grid_y": 58, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y151": { + "bits": {}, + "grid_x": 57, + "grid_y": 57, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y152": { + "bits": {}, + "grid_x": 57, + "grid_y": 56, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y153": { + "bits": {}, + "grid_x": 57, + "grid_y": 55, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y154": { + "bits": {}, + "grid_x": 57, + "grid_y": 54, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y155": { + "bits": {}, + "grid_x": 57, + "grid_y": 53, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y53": { + "bits": {}, + "grid_x": 57, + "grid_y": 155, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y54": { + "bits": {}, + "grid_x": 57, + "grid_y": 154, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y55": { + "bits": {}, + "grid_x": 57, + "grid_y": 153, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y56": { + "bits": {}, + "grid_x": 57, + "grid_y": 152, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y57": { + "bits": {}, + "grid_x": 57, + "grid_y": 151, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y58": { + "bits": {}, + "grid_x": 57, + "grid_y": 150, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y59": { + "bits": {}, + "grid_x": 57, + "grid_y": 149, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y60": { + "bits": {}, + "grid_x": 57, + "grid_y": 148, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y61": { + "bits": {}, + "grid_x": 57, + "grid_y": 147, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y62": { + "bits": {}, + "grid_x": 57, + "grid_y": 146, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y63": { + "bits": {}, + "grid_x": 57, + "grid_y": 145, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y64": { + "bits": {}, + "grid_x": 57, + "grid_y": 144, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y65": { + "bits": {}, + "grid_x": 57, + "grid_y": 143, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y66": { + "bits": {}, + "grid_x": 57, + "grid_y": 142, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y67": { + "bits": {}, + "grid_x": 57, + "grid_y": 141, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y68": { + "bits": {}, + "grid_x": 57, + "grid_y": 140, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y69": { + "bits": {}, + "grid_x": 57, + "grid_y": 139, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y70": { + "bits": {}, + "grid_x": 57, + "grid_y": 138, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y71": { + "bits": {}, + "grid_x": 57, + "grid_y": 137, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y72": { + "bits": {}, + "grid_x": 57, + "grid_y": 136, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y73": { + "bits": {}, + "grid_x": 57, + "grid_y": 135, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y74": { + "bits": {}, + "grid_x": 57, + "grid_y": 134, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y75": { + "bits": {}, + "grid_x": 57, + "grid_y": 133, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y76": { + "bits": {}, + "grid_x": 57, + "grid_y": 132, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y77": { + "bits": {}, + "grid_x": 57, + "grid_y": 131, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y79": { + "bits": {}, + "grid_x": 57, + "grid_y": 129, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y80": { + "bits": {}, + "grid_x": 57, + "grid_y": 128, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y81": { + "bits": {}, + "grid_x": 57, + "grid_y": 127, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y82": { + "bits": {}, + "grid_x": 57, + "grid_y": 126, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y83": { + "bits": {}, + "grid_x": 57, + "grid_y": 125, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y84": { + "bits": {}, + "grid_x": 57, + "grid_y": 124, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y85": { + "bits": {}, + "grid_x": 57, + "grid_y": 123, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y86": { + "bits": {}, + "grid_x": 57, + "grid_y": 122, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y87": { + "bits": {}, + "grid_x": 57, + "grid_y": 121, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y88": { + "bits": {}, + "grid_x": 57, + "grid_y": 120, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y89": { + "bits": {}, + "grid_x": 57, + "grid_y": 119, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y90": { + "bits": {}, + "grid_x": 57, + "grid_y": 118, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y91": { + "bits": {}, + "grid_x": 57, + "grid_y": 117, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y92": { + "bits": {}, + "grid_x": 57, + "grid_y": 116, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y93": { + "bits": {}, + "grid_x": 57, + "grid_y": 115, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y94": { + "bits": {}, + "grid_x": 57, + "grid_y": 114, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y95": { + "bits": {}, + "grid_x": 57, + "grid_y": 113, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y96": { + "bits": {}, + "grid_x": 57, + "grid_y": 112, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y97": { + "bits": {}, + "grid_x": 57, + "grid_y": 111, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y98": { + "bits": {}, + "grid_x": 57, + "grid_y": 110, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X57Y99": { + "bits": {}, + "grid_x": 57, + "grid_y": 109, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y100": { + "bits": {}, + "grid_x": 58, + "grid_y": 108, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y101": { + "bits": {}, + "grid_x": 58, + "grid_y": 107, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y102": { + "bits": {}, + "grid_x": 58, + "grid_y": 106, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y103": { + "bits": {}, + "grid_x": 58, + "grid_y": 105, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y105": { + "bits": {}, + "grid_x": 58, + "grid_y": 103, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y106": { + "bits": {}, + "grid_x": 58, + "grid_y": 102, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y107": { + "bits": {}, + "grid_x": 58, + "grid_y": 101, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y108": { + "bits": {}, + "grid_x": 58, + "grid_y": 100, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y109": { + "bits": {}, + "grid_x": 58, + "grid_y": 99, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y110": { + "bits": {}, + "grid_x": 58, + "grid_y": 98, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y111": { + "bits": {}, + "grid_x": 58, + "grid_y": 97, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y112": { + "bits": {}, + "grid_x": 58, + "grid_y": 96, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y113": { + "bits": {}, + "grid_x": 58, + "grid_y": 95, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y114": { + "bits": {}, + "grid_x": 58, + "grid_y": 94, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y115": { + "bits": {}, + "grid_x": 58, + "grid_y": 93, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y116": { + "bits": {}, + "grid_x": 58, + "grid_y": 92, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y117": { + "bits": {}, + "grid_x": 58, + "grid_y": 91, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y118": { + "bits": {}, + "grid_x": 58, + "grid_y": 90, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y119": { + "bits": {}, + "grid_x": 58, + "grid_y": 89, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y120": { + "bits": {}, + "grid_x": 58, + "grid_y": 88, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y121": { + "bits": {}, + "grid_x": 58, + "grid_y": 87, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y122": { + "bits": {}, + "grid_x": 58, + "grid_y": 86, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y123": { + "bits": {}, + "grid_x": 58, + "grid_y": 85, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y124": { + "bits": {}, + "grid_x": 58, + "grid_y": 84, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y125": { + "bits": {}, + "grid_x": 58, + "grid_y": 83, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y126": { + "bits": {}, + "grid_x": 58, + "grid_y": 82, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y127": { + "bits": {}, + "grid_x": 58, + "grid_y": 81, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y128": { + "bits": {}, + "grid_x": 58, + "grid_y": 80, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y129": { + "bits": {}, + "grid_x": 58, + "grid_y": 79, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y131": { + "bits": {}, + "grid_x": 58, + "grid_y": 77, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y132": { + "bits": {}, + "grid_x": 58, + "grid_y": 76, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y133": { + "bits": {}, + "grid_x": 58, + "grid_y": 75, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y134": { + "bits": {}, + "grid_x": 58, + "grid_y": 74, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y135": { + "bits": {}, + "grid_x": 58, + "grid_y": 73, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y136": { + "bits": {}, + "grid_x": 58, + "grid_y": 72, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y137": { + "bits": {}, + "grid_x": 58, + "grid_y": 71, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y138": { + "bits": {}, + "grid_x": 58, + "grid_y": 70, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y139": { + "bits": {}, + "grid_x": 58, + "grid_y": 69, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y140": { + "bits": {}, + "grid_x": 58, + "grid_y": 68, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y141": { + "bits": {}, + "grid_x": 58, + "grid_y": 67, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y142": { + "bits": {}, + "grid_x": 58, + "grid_y": 66, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y143": { + "bits": {}, + "grid_x": 58, + "grid_y": 65, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y144": { + "bits": {}, + "grid_x": 58, + "grid_y": 64, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y145": { + "bits": {}, + "grid_x": 58, + "grid_y": 63, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y146": { + "bits": {}, + "grid_x": 58, + "grid_y": 62, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y147": { + "bits": {}, + "grid_x": 58, + "grid_y": 61, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y148": { + "bits": {}, + "grid_x": 58, + "grid_y": 60, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y149": { + "bits": {}, + "grid_x": 58, + "grid_y": 59, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y150": { + "bits": {}, + "grid_x": 58, + "grid_y": 58, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y151": { + "bits": {}, + "grid_x": 58, + "grid_y": 57, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y152": { + "bits": {}, + "grid_x": 58, + "grid_y": 56, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y153": { + "bits": {}, + "grid_x": 58, + "grid_y": 55, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y154": { + "bits": {}, + "grid_x": 58, + "grid_y": 54, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y155": { + "bits": {}, + "grid_x": 58, + "grid_y": 53, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y53": { + "bits": {}, + "grid_x": 58, + "grid_y": 155, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y54": { + "bits": {}, + "grid_x": 58, + "grid_y": 154, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y55": { + "bits": {}, + "grid_x": 58, + "grid_y": 153, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y56": { + "bits": {}, + "grid_x": 58, + "grid_y": 152, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y57": { + "bits": {}, + "grid_x": 58, + "grid_y": 151, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y58": { + "bits": {}, + "grid_x": 58, + "grid_y": 150, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y59": { + "bits": {}, + "grid_x": 58, + "grid_y": 149, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y60": { + "bits": {}, + "grid_x": 58, + "grid_y": 148, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y61": { + "bits": {}, + "grid_x": 58, + "grid_y": 147, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y62": { + "bits": {}, + "grid_x": 58, + "grid_y": 146, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y63": { + "bits": {}, + "grid_x": 58, + "grid_y": 145, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y64": { + "bits": {}, + "grid_x": 58, + "grid_y": 144, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y65": { + "bits": {}, + "grid_x": 58, + "grid_y": 143, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y66": { + "bits": {}, + "grid_x": 58, + "grid_y": 142, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y67": { + "bits": {}, + "grid_x": 58, + "grid_y": 141, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y68": { + "bits": {}, + "grid_x": 58, + "grid_y": 140, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y69": { + "bits": {}, + "grid_x": 58, + "grid_y": 139, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y70": { + "bits": {}, + "grid_x": 58, + "grid_y": 138, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y71": { + "bits": {}, + "grid_x": 58, + "grid_y": 137, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y72": { + "bits": {}, + "grid_x": 58, + "grid_y": 136, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y73": { + "bits": {}, + "grid_x": 58, + "grid_y": 135, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y74": { + "bits": {}, + "grid_x": 58, + "grid_y": 134, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y75": { + "bits": {}, + "grid_x": 58, + "grid_y": 133, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y76": { + "bits": {}, + "grid_x": 58, + "grid_y": 132, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y77": { + "bits": {}, + "grid_x": 58, + "grid_y": 131, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y79": { + "bits": {}, + "grid_x": 58, + "grid_y": 129, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y80": { + "bits": {}, + "grid_x": 58, + "grid_y": 128, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y81": { + "bits": {}, + "grid_x": 58, + "grid_y": 127, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y82": { + "bits": {}, + "grid_x": 58, + "grid_y": 126, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y83": { + "bits": {}, + "grid_x": 58, + "grid_y": 125, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y84": { + "bits": {}, + "grid_x": 58, + "grid_y": 124, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y85": { + "bits": {}, + "grid_x": 58, + "grid_y": 123, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y86": { + "bits": {}, + "grid_x": 58, + "grid_y": 122, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y87": { + "bits": {}, + "grid_x": 58, + "grid_y": 121, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y88": { + "bits": {}, + "grid_x": 58, + "grid_y": 120, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y89": { + "bits": {}, + "grid_x": 58, + "grid_y": 119, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y90": { + "bits": {}, + "grid_x": 58, + "grid_y": 118, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y91": { + "bits": {}, + "grid_x": 58, + "grid_y": 117, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y92": { + "bits": {}, + "grid_x": 58, + "grid_y": 116, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y93": { + "bits": {}, + "grid_x": 58, + "grid_y": 115, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y94": { + "bits": {}, + "grid_x": 58, + "grid_y": 114, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y95": { + "bits": {}, + "grid_x": 58, + "grid_y": 113, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y96": { + "bits": {}, + "grid_x": 58, + "grid_y": 112, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y97": { + "bits": {}, + "grid_x": 58, + "grid_y": 111, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y98": { + "bits": {}, + "grid_x": 58, + "grid_y": 110, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X58Y99": { + "bits": {}, + "grid_x": 58, + "grid_y": 109, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y105": { + "bits": {}, + "grid_x": 61, + "grid_y": 103, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y106": { + "bits": {}, + "grid_x": 61, + "grid_y": 102, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y107": { + "bits": {}, + "grid_x": 61, + "grid_y": 101, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y108": { + "bits": {}, + "grid_x": 61, + "grid_y": 100, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y109": { + "bits": {}, + "grid_x": 61, + "grid_y": 99, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y110": { + "bits": {}, + "grid_x": 61, + "grid_y": 98, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y111": { + "bits": {}, + "grid_x": 61, + "grid_y": 97, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y112": { + "bits": {}, + "grid_x": 61, + "grid_y": 96, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y113": { + "bits": {}, + "grid_x": 61, + "grid_y": 95, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y114": { + "bits": {}, + "grid_x": 61, + "grid_y": 94, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y115": { + "bits": {}, + "grid_x": 61, + "grid_y": 93, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y116": { + "bits": {}, + "grid_x": 61, + "grid_y": 92, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y117": { + "bits": {}, + "grid_x": 61, + "grid_y": 91, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y118": { + "bits": {}, + "grid_x": 61, + "grid_y": 90, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y119": { + "bits": {}, + "grid_x": 61, + "grid_y": 89, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y120": { + "bits": {}, + "grid_x": 61, + "grid_y": 88, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y121": { + "bits": {}, + "grid_x": 61, + "grid_y": 87, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y122": { + "bits": {}, + "grid_x": 61, + "grid_y": 86, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y123": { + "bits": {}, + "grid_x": 61, + "grid_y": 85, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y124": { + "bits": {}, + "grid_x": 61, + "grid_y": 84, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y125": { + "bits": {}, + "grid_x": 61, + "grid_y": 83, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y126": { + "bits": {}, + "grid_x": 61, + "grid_y": 82, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y127": { + "bits": {}, + "grid_x": 61, + "grid_y": 81, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y128": { + "bits": {}, + "grid_x": 61, + "grid_y": 80, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_1_X61Y129": { + "bits": {}, + "grid_x": 61, + "grid_y": 79, + "sites": {}, + "type": "INT_FEEDTHRU_1" + }, + "INT_FEEDTHRU_2_X51Y100": { + "bits": {}, + "grid_x": 51, + "grid_y": 108, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y101": { + "bits": {}, + "grid_x": 51, + "grid_y": 107, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y102": { + "bits": {}, + "grid_x": 51, + "grid_y": 106, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y103": { + "bits": {}, + "grid_x": 51, + "grid_y": 105, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y105": { + "bits": {}, + "grid_x": 51, + "grid_y": 103, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y106": { + "bits": {}, + "grid_x": 51, + "grid_y": 102, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y107": { + "bits": {}, + "grid_x": 51, + "grid_y": 101, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y108": { + "bits": {}, + "grid_x": 51, + "grid_y": 100, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y109": { + "bits": {}, + "grid_x": 51, + "grid_y": 99, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y110": { + "bits": {}, + "grid_x": 51, + "grid_y": 98, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y111": { + "bits": {}, + "grid_x": 51, + "grid_y": 97, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y112": { + "bits": {}, + "grid_x": 51, + "grid_y": 96, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y113": { + "bits": {}, + "grid_x": 51, + "grid_y": 95, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y114": { + "bits": {}, + "grid_x": 51, + "grid_y": 94, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y115": { + "bits": {}, + "grid_x": 51, + "grid_y": 93, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y116": { + "bits": {}, + "grid_x": 51, + "grid_y": 92, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y117": { + "bits": {}, + "grid_x": 51, + "grid_y": 91, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y118": { + "bits": {}, + "grid_x": 51, + "grid_y": 90, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y119": { + "bits": {}, + "grid_x": 51, + "grid_y": 89, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y120": { + "bits": {}, + "grid_x": 51, + "grid_y": 88, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y121": { + "bits": {}, + "grid_x": 51, + "grid_y": 87, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y122": { + "bits": {}, + "grid_x": 51, + "grid_y": 86, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y123": { + "bits": {}, + "grid_x": 51, + "grid_y": 85, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y124": { + "bits": {}, + "grid_x": 51, + "grid_y": 84, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y125": { + "bits": {}, + "grid_x": 51, + "grid_y": 83, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y126": { + "bits": {}, + "grid_x": 51, + "grid_y": 82, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y127": { + "bits": {}, + "grid_x": 51, + "grid_y": 81, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y128": { + "bits": {}, + "grid_x": 51, + "grid_y": 80, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y129": { + "bits": {}, + "grid_x": 51, + "grid_y": 79, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y131": { + "bits": {}, + "grid_x": 51, + "grid_y": 77, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y132": { + "bits": {}, + "grid_x": 51, + "grid_y": 76, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y133": { + "bits": {}, + "grid_x": 51, + "grid_y": 75, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y134": { + "bits": {}, + "grid_x": 51, + "grid_y": 74, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y135": { + "bits": {}, + "grid_x": 51, + "grid_y": 73, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y136": { + "bits": {}, + "grid_x": 51, + "grid_y": 72, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y137": { + "bits": {}, + "grid_x": 51, + "grid_y": 71, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y138": { + "bits": {}, + "grid_x": 51, + "grid_y": 70, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y139": { + "bits": {}, + "grid_x": 51, + "grid_y": 69, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y140": { + "bits": {}, + "grid_x": 51, + "grid_y": 68, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y141": { + "bits": {}, + "grid_x": 51, + "grid_y": 67, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y142": { + "bits": {}, + "grid_x": 51, + "grid_y": 66, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y143": { + "bits": {}, + "grid_x": 51, + "grid_y": 65, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y144": { + "bits": {}, + "grid_x": 51, + "grid_y": 64, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y145": { + "bits": {}, + "grid_x": 51, + "grid_y": 63, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y146": { + "bits": {}, + "grid_x": 51, + "grid_y": 62, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y147": { + "bits": {}, + "grid_x": 51, + "grid_y": 61, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y148": { + "bits": {}, + "grid_x": 51, + "grid_y": 60, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y149": { + "bits": {}, + "grid_x": 51, + "grid_y": 59, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y150": { + "bits": {}, + "grid_x": 51, + "grid_y": 58, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y151": { + "bits": {}, + "grid_x": 51, + "grid_y": 57, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y152": { + "bits": {}, + "grid_x": 51, + "grid_y": 56, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y153": { + "bits": {}, + "grid_x": 51, + "grid_y": 55, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y154": { + "bits": {}, + "grid_x": 51, + "grid_y": 54, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y155": { + "bits": {}, + "grid_x": 51, + "grid_y": 53, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y53": { + "bits": {}, + "grid_x": 51, + "grid_y": 155, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y54": { + "bits": {}, + "grid_x": 51, + "grid_y": 154, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y55": { + "bits": {}, + "grid_x": 51, + "grid_y": 153, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y56": { + "bits": {}, + "grid_x": 51, + "grid_y": 152, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y57": { + "bits": {}, + "grid_x": 51, + "grid_y": 151, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y58": { + "bits": {}, + "grid_x": 51, + "grid_y": 150, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y59": { + "bits": {}, + "grid_x": 51, + "grid_y": 149, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y60": { + "bits": {}, + "grid_x": 51, + "grid_y": 148, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y61": { + "bits": {}, + "grid_x": 51, + "grid_y": 147, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y62": { + "bits": {}, + "grid_x": 51, + "grid_y": 146, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y63": { + "bits": {}, + "grid_x": 51, + "grid_y": 145, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y64": { + "bits": {}, + "grid_x": 51, + "grid_y": 144, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y65": { + "bits": {}, + "grid_x": 51, + "grid_y": 143, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y66": { + "bits": {}, + "grid_x": 51, + "grid_y": 142, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y67": { + "bits": {}, + "grid_x": 51, + "grid_y": 141, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y68": { + "bits": {}, + "grid_x": 51, + "grid_y": 140, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y69": { + "bits": {}, + "grid_x": 51, + "grid_y": 139, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y70": { + "bits": {}, + "grid_x": 51, + "grid_y": 138, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y71": { + "bits": {}, + "grid_x": 51, + "grid_y": 137, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y72": { + "bits": {}, + "grid_x": 51, + "grid_y": 136, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y73": { + "bits": {}, + "grid_x": 51, + "grid_y": 135, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y74": { + "bits": {}, + "grid_x": 51, + "grid_y": 134, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y75": { + "bits": {}, + "grid_x": 51, + "grid_y": 133, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y76": { + "bits": {}, + "grid_x": 51, + "grid_y": 132, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y77": { + "bits": {}, + "grid_x": 51, + "grid_y": 131, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y79": { + "bits": {}, + "grid_x": 51, + "grid_y": 129, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y80": { + "bits": {}, + "grid_x": 51, + "grid_y": 128, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y81": { + "bits": {}, + "grid_x": 51, + "grid_y": 127, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y82": { + "bits": {}, + "grid_x": 51, + "grid_y": 126, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y83": { + "bits": {}, + "grid_x": 51, + "grid_y": 125, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y84": { + "bits": {}, + "grid_x": 51, + "grid_y": 124, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y85": { + "bits": {}, + "grid_x": 51, + "grid_y": 123, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y86": { + "bits": {}, + "grid_x": 51, + "grid_y": 122, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y87": { + "bits": {}, + "grid_x": 51, + "grid_y": 121, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y88": { + "bits": {}, + "grid_x": 51, + "grid_y": 120, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y89": { + "bits": {}, + "grid_x": 51, + "grid_y": 119, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y90": { + "bits": {}, + "grid_x": 51, + "grid_y": 118, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y91": { + "bits": {}, + "grid_x": 51, + "grid_y": 117, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y92": { + "bits": {}, + "grid_x": 51, + "grid_y": 116, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y93": { + "bits": {}, + "grid_x": 51, + "grid_y": 115, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y94": { + "bits": {}, + "grid_x": 51, + "grid_y": 114, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y95": { + "bits": {}, + "grid_x": 51, + "grid_y": 113, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y96": { + "bits": {}, + "grid_x": 51, + "grid_y": 112, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y97": { + "bits": {}, + "grid_x": 51, + "grid_y": 111, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y98": { + "bits": {}, + "grid_x": 51, + "grid_y": 110, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X51Y99": { + "bits": {}, + "grid_x": 51, + "grid_y": 109, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y100": { + "bits": {}, + "grid_x": 52, + "grid_y": 108, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y101": { + "bits": {}, + "grid_x": 52, + "grid_y": 107, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y102": { + "bits": {}, + "grid_x": 52, + "grid_y": 106, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y103": { + "bits": {}, + "grid_x": 52, + "grid_y": 105, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y105": { + "bits": {}, + "grid_x": 52, + "grid_y": 103, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y106": { + "bits": {}, + "grid_x": 52, + "grid_y": 102, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y107": { + "bits": {}, + "grid_x": 52, + "grid_y": 101, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y108": { + "bits": {}, + "grid_x": 52, + "grid_y": 100, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y109": { + "bits": {}, + "grid_x": 52, + "grid_y": 99, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y110": { + "bits": {}, + "grid_x": 52, + "grid_y": 98, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y111": { + "bits": {}, + "grid_x": 52, + "grid_y": 97, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y112": { + "bits": {}, + "grid_x": 52, + "grid_y": 96, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y113": { + "bits": {}, + "grid_x": 52, + "grid_y": 95, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y114": { + "bits": {}, + "grid_x": 52, + "grid_y": 94, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y115": { + "bits": {}, + "grid_x": 52, + "grid_y": 93, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y116": { + "bits": {}, + "grid_x": 52, + "grid_y": 92, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y117": { + "bits": {}, + "grid_x": 52, + "grid_y": 91, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y118": { + "bits": {}, + "grid_x": 52, + "grid_y": 90, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y119": { + "bits": {}, + "grid_x": 52, + "grid_y": 89, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y120": { + "bits": {}, + "grid_x": 52, + "grid_y": 88, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y121": { + "bits": {}, + "grid_x": 52, + "grid_y": 87, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y122": { + "bits": {}, + "grid_x": 52, + "grid_y": 86, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y123": { + "bits": {}, + "grid_x": 52, + "grid_y": 85, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y124": { + "bits": {}, + "grid_x": 52, + "grid_y": 84, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y125": { + "bits": {}, + "grid_x": 52, + "grid_y": 83, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y126": { + "bits": {}, + "grid_x": 52, + "grid_y": 82, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y127": { + "bits": {}, + "grid_x": 52, + "grid_y": 81, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y128": { + "bits": {}, + "grid_x": 52, + "grid_y": 80, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y129": { + "bits": {}, + "grid_x": 52, + "grid_y": 79, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y131": { + "bits": {}, + "grid_x": 52, + "grid_y": 77, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y132": { + "bits": {}, + "grid_x": 52, + "grid_y": 76, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y133": { + "bits": {}, + "grid_x": 52, + "grid_y": 75, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y134": { + "bits": {}, + "grid_x": 52, + "grid_y": 74, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y135": { + "bits": {}, + "grid_x": 52, + "grid_y": 73, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y136": { + "bits": {}, + "grid_x": 52, + "grid_y": 72, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y137": { + "bits": {}, + "grid_x": 52, + "grid_y": 71, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y138": { + "bits": {}, + "grid_x": 52, + "grid_y": 70, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y139": { + "bits": {}, + "grid_x": 52, + "grid_y": 69, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y140": { + "bits": {}, + "grid_x": 52, + "grid_y": 68, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y141": { + "bits": {}, + "grid_x": 52, + "grid_y": 67, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y142": { + "bits": {}, + "grid_x": 52, + "grid_y": 66, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y143": { + "bits": {}, + "grid_x": 52, + "grid_y": 65, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y144": { + "bits": {}, + "grid_x": 52, + "grid_y": 64, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y145": { + "bits": {}, + "grid_x": 52, + "grid_y": 63, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y146": { + "bits": {}, + "grid_x": 52, + "grid_y": 62, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y147": { + "bits": {}, + "grid_x": 52, + "grid_y": 61, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y148": { + "bits": {}, + "grid_x": 52, + "grid_y": 60, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y149": { + "bits": {}, + "grid_x": 52, + "grid_y": 59, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y150": { + "bits": {}, + "grid_x": 52, + "grid_y": 58, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y151": { + "bits": {}, + "grid_x": 52, + "grid_y": 57, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y152": { + "bits": {}, + "grid_x": 52, + "grid_y": 56, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y153": { + "bits": {}, + "grid_x": 52, + "grid_y": 55, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y154": { + "bits": {}, + "grid_x": 52, + "grid_y": 54, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y155": { + "bits": {}, + "grid_x": 52, + "grid_y": 53, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y53": { + "bits": {}, + "grid_x": 52, + "grid_y": 155, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y54": { + "bits": {}, + "grid_x": 52, + "grid_y": 154, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y55": { + "bits": {}, + "grid_x": 52, + "grid_y": 153, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y56": { + "bits": {}, + "grid_x": 52, + "grid_y": 152, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y57": { + "bits": {}, + "grid_x": 52, + "grid_y": 151, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y58": { + "bits": {}, + "grid_x": 52, + "grid_y": 150, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y59": { + "bits": {}, + "grid_x": 52, + "grid_y": 149, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y60": { + "bits": {}, + "grid_x": 52, + "grid_y": 148, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y61": { + "bits": {}, + "grid_x": 52, + "grid_y": 147, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y62": { + "bits": {}, + "grid_x": 52, + "grid_y": 146, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y63": { + "bits": {}, + "grid_x": 52, + "grid_y": 145, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y64": { + "bits": {}, + "grid_x": 52, + "grid_y": 144, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y65": { + "bits": {}, + "grid_x": 52, + "grid_y": 143, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y66": { + "bits": {}, + "grid_x": 52, + "grid_y": 142, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y67": { + "bits": {}, + "grid_x": 52, + "grid_y": 141, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y68": { + "bits": {}, + "grid_x": 52, + "grid_y": 140, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y69": { + "bits": {}, + "grid_x": 52, + "grid_y": 139, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y70": { + "bits": {}, + "grid_x": 52, + "grid_y": 138, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y71": { + "bits": {}, + "grid_x": 52, + "grid_y": 137, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y72": { + "bits": {}, + "grid_x": 52, + "grid_y": 136, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y73": { + "bits": {}, + "grid_x": 52, + "grid_y": 135, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y74": { + "bits": {}, + "grid_x": 52, + "grid_y": 134, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y75": { + "bits": {}, + "grid_x": 52, + "grid_y": 133, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y76": { + "bits": {}, + "grid_x": 52, + "grid_y": 132, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y77": { + "bits": {}, + "grid_x": 52, + "grid_y": 131, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y79": { + "bits": {}, + "grid_x": 52, + "grid_y": 129, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y80": { + "bits": {}, + "grid_x": 52, + "grid_y": 128, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y81": { + "bits": {}, + "grid_x": 52, + "grid_y": 127, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y82": { + "bits": {}, + "grid_x": 52, + "grid_y": 126, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y83": { + "bits": {}, + "grid_x": 52, + "grid_y": 125, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y84": { + "bits": {}, + "grid_x": 52, + "grid_y": 124, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y85": { + "bits": {}, + "grid_x": 52, + "grid_y": 123, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y86": { + "bits": {}, + "grid_x": 52, + "grid_y": 122, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y87": { + "bits": {}, + "grid_x": 52, + "grid_y": 121, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y88": { + "bits": {}, + "grid_x": 52, + "grid_y": 120, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y89": { + "bits": {}, + "grid_x": 52, + "grid_y": 119, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y90": { + "bits": {}, + "grid_x": 52, + "grid_y": 118, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y91": { + "bits": {}, + "grid_x": 52, + "grid_y": 117, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y92": { + "bits": {}, + "grid_x": 52, + "grid_y": 116, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y93": { + "bits": {}, + "grid_x": 52, + "grid_y": 115, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y94": { + "bits": {}, + "grid_x": 52, + "grid_y": 114, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y95": { + "bits": {}, + "grid_x": 52, + "grid_y": 113, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y96": { + "bits": {}, + "grid_x": 52, + "grid_y": 112, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y97": { + "bits": {}, + "grid_x": 52, + "grid_y": 111, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y98": { + "bits": {}, + "grid_x": 52, + "grid_y": 110, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X52Y99": { + "bits": {}, + "grid_x": 52, + "grid_y": 109, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y100": { + "bits": {}, + "grid_x": 55, + "grid_y": 108, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y101": { + "bits": {}, + "grid_x": 55, + "grid_y": 107, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y102": { + "bits": {}, + "grid_x": 55, + "grid_y": 106, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y103": { + "bits": {}, + "grid_x": 55, + "grid_y": 105, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y105": { + "bits": {}, + "grid_x": 55, + "grid_y": 103, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y106": { + "bits": {}, + "grid_x": 55, + "grid_y": 102, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y107": { + "bits": {}, + "grid_x": 55, + "grid_y": 101, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y108": { + "bits": {}, + "grid_x": 55, + "grid_y": 100, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y109": { + "bits": {}, + "grid_x": 55, + "grid_y": 99, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y110": { + "bits": {}, + "grid_x": 55, + "grid_y": 98, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y111": { + "bits": {}, + "grid_x": 55, + "grid_y": 97, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y112": { + "bits": {}, + "grid_x": 55, + "grid_y": 96, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y113": { + "bits": {}, + "grid_x": 55, + "grid_y": 95, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y114": { + "bits": {}, + "grid_x": 55, + "grid_y": 94, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y115": { + "bits": {}, + "grid_x": 55, + "grid_y": 93, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y116": { + "bits": {}, + "grid_x": 55, + "grid_y": 92, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y117": { + "bits": {}, + "grid_x": 55, + "grid_y": 91, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y118": { + "bits": {}, + "grid_x": 55, + "grid_y": 90, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y119": { + "bits": {}, + "grid_x": 55, + "grid_y": 89, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y120": { + "bits": {}, + "grid_x": 55, + "grid_y": 88, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y121": { + "bits": {}, + "grid_x": 55, + "grid_y": 87, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y122": { + "bits": {}, + "grid_x": 55, + "grid_y": 86, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y123": { + "bits": {}, + "grid_x": 55, + "grid_y": 85, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y124": { + "bits": {}, + "grid_x": 55, + "grid_y": 84, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y125": { + "bits": {}, + "grid_x": 55, + "grid_y": 83, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y126": { + "bits": {}, + "grid_x": 55, + "grid_y": 82, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y127": { + "bits": {}, + "grid_x": 55, + "grid_y": 81, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y128": { + "bits": {}, + "grid_x": 55, + "grid_y": 80, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y129": { + "bits": {}, + "grid_x": 55, + "grid_y": 79, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y131": { + "bits": {}, + "grid_x": 55, + "grid_y": 77, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y132": { + "bits": {}, + "grid_x": 55, + "grid_y": 76, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y133": { + "bits": {}, + "grid_x": 55, + "grid_y": 75, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y134": { + "bits": {}, + "grid_x": 55, + "grid_y": 74, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y135": { + "bits": {}, + "grid_x": 55, + "grid_y": 73, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y136": { + "bits": {}, + "grid_x": 55, + "grid_y": 72, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y137": { + "bits": {}, + "grid_x": 55, + "grid_y": 71, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y138": { + "bits": {}, + "grid_x": 55, + "grid_y": 70, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y139": { + "bits": {}, + "grid_x": 55, + "grid_y": 69, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y140": { + "bits": {}, + "grid_x": 55, + "grid_y": 68, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y141": { + "bits": {}, + "grid_x": 55, + "grid_y": 67, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y142": { + "bits": {}, + "grid_x": 55, + "grid_y": 66, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y143": { + "bits": {}, + "grid_x": 55, + "grid_y": 65, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y144": { + "bits": {}, + "grid_x": 55, + "grid_y": 64, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y145": { + "bits": {}, + "grid_x": 55, + "grid_y": 63, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y146": { + "bits": {}, + "grid_x": 55, + "grid_y": 62, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y147": { + "bits": {}, + "grid_x": 55, + "grid_y": 61, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y148": { + "bits": {}, + "grid_x": 55, + "grid_y": 60, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y149": { + "bits": {}, + "grid_x": 55, + "grid_y": 59, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y150": { + "bits": {}, + "grid_x": 55, + "grid_y": 58, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y151": { + "bits": {}, + "grid_x": 55, + "grid_y": 57, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y152": { + "bits": {}, + "grid_x": 55, + "grid_y": 56, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y153": { + "bits": {}, + "grid_x": 55, + "grid_y": 55, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y154": { + "bits": {}, + "grid_x": 55, + "grid_y": 54, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y155": { + "bits": {}, + "grid_x": 55, + "grid_y": 53, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y53": { + "bits": {}, + "grid_x": 55, + "grid_y": 155, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y54": { + "bits": {}, + "grid_x": 55, + "grid_y": 154, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y55": { + "bits": {}, + "grid_x": 55, + "grid_y": 153, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y56": { + "bits": {}, + "grid_x": 55, + "grid_y": 152, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y57": { + "bits": {}, + "grid_x": 55, + "grid_y": 151, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y58": { + "bits": {}, + "grid_x": 55, + "grid_y": 150, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y59": { + "bits": {}, + "grid_x": 55, + "grid_y": 149, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y60": { + "bits": {}, + "grid_x": 55, + "grid_y": 148, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y61": { + "bits": {}, + "grid_x": 55, + "grid_y": 147, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y62": { + "bits": {}, + "grid_x": 55, + "grid_y": 146, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y63": { + "bits": {}, + "grid_x": 55, + "grid_y": 145, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y64": { + "bits": {}, + "grid_x": 55, + "grid_y": 144, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y65": { + "bits": {}, + "grid_x": 55, + "grid_y": 143, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y66": { + "bits": {}, + "grid_x": 55, + "grid_y": 142, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y67": { + "bits": {}, + "grid_x": 55, + "grid_y": 141, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y68": { + "bits": {}, + "grid_x": 55, + "grid_y": 140, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y69": { + "bits": {}, + "grid_x": 55, + "grid_y": 139, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y70": { + "bits": {}, + "grid_x": 55, + "grid_y": 138, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y71": { + "bits": {}, + "grid_x": 55, + "grid_y": 137, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y72": { + "bits": {}, + "grid_x": 55, + "grid_y": 136, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y73": { + "bits": {}, + "grid_x": 55, + "grid_y": 135, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y74": { + "bits": {}, + "grid_x": 55, + "grid_y": 134, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y75": { + "bits": {}, + "grid_x": 55, + "grid_y": 133, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y76": { + "bits": {}, + "grid_x": 55, + "grid_y": 132, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y77": { + "bits": {}, + "grid_x": 55, + "grid_y": 131, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y79": { + "bits": {}, + "grid_x": 55, + "grid_y": 129, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y80": { + "bits": {}, + "grid_x": 55, + "grid_y": 128, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y81": { + "bits": {}, + "grid_x": 55, + "grid_y": 127, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y82": { + "bits": {}, + "grid_x": 55, + "grid_y": 126, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y83": { + "bits": {}, + "grid_x": 55, + "grid_y": 125, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y84": { + "bits": {}, + "grid_x": 55, + "grid_y": 124, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y85": { + "bits": {}, + "grid_x": 55, + "grid_y": 123, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y86": { + "bits": {}, + "grid_x": 55, + "grid_y": 122, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y87": { + "bits": {}, + "grid_x": 55, + "grid_y": 121, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y88": { + "bits": {}, + "grid_x": 55, + "grid_y": 120, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y89": { + "bits": {}, + "grid_x": 55, + "grid_y": 119, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y90": { + "bits": {}, + "grid_x": 55, + "grid_y": 118, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y91": { + "bits": {}, + "grid_x": 55, + "grid_y": 117, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y92": { + "bits": {}, + "grid_x": 55, + "grid_y": 116, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y93": { + "bits": {}, + "grid_x": 55, + "grid_y": 115, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y94": { + "bits": {}, + "grid_x": 55, + "grid_y": 114, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y95": { + "bits": {}, + "grid_x": 55, + "grid_y": 113, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y96": { + "bits": {}, + "grid_x": 55, + "grid_y": 112, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y97": { + "bits": {}, + "grid_x": 55, + "grid_y": 111, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y98": { + "bits": {}, + "grid_x": 55, + "grid_y": 110, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X55Y99": { + "bits": {}, + "grid_x": 55, + "grid_y": 109, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y100": { + "bits": {}, + "grid_x": 56, + "grid_y": 108, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y101": { + "bits": {}, + "grid_x": 56, + "grid_y": 107, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y102": { + "bits": {}, + "grid_x": 56, + "grid_y": 106, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y103": { + "bits": {}, + "grid_x": 56, + "grid_y": 105, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y105": { + "bits": {}, + "grid_x": 56, + "grid_y": 103, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y106": { + "bits": {}, + "grid_x": 56, + "grid_y": 102, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y107": { + "bits": {}, + "grid_x": 56, + "grid_y": 101, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y108": { + "bits": {}, + "grid_x": 56, + "grid_y": 100, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y109": { + "bits": {}, + "grid_x": 56, + "grid_y": 99, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y110": { + "bits": {}, + "grid_x": 56, + "grid_y": 98, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y111": { + "bits": {}, + "grid_x": 56, + "grid_y": 97, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y112": { + "bits": {}, + "grid_x": 56, + "grid_y": 96, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y113": { + "bits": {}, + "grid_x": 56, + "grid_y": 95, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y114": { + "bits": {}, + "grid_x": 56, + "grid_y": 94, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y115": { + "bits": {}, + "grid_x": 56, + "grid_y": 93, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y116": { + "bits": {}, + "grid_x": 56, + "grid_y": 92, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y117": { + "bits": {}, + "grid_x": 56, + "grid_y": 91, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y118": { + "bits": {}, + "grid_x": 56, + "grid_y": 90, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y119": { + "bits": {}, + "grid_x": 56, + "grid_y": 89, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y120": { + "bits": {}, + "grid_x": 56, + "grid_y": 88, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y121": { + "bits": {}, + "grid_x": 56, + "grid_y": 87, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y122": { + "bits": {}, + "grid_x": 56, + "grid_y": 86, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y123": { + "bits": {}, + "grid_x": 56, + "grid_y": 85, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y124": { + "bits": {}, + "grid_x": 56, + "grid_y": 84, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y125": { + "bits": {}, + "grid_x": 56, + "grid_y": 83, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y126": { + "bits": {}, + "grid_x": 56, + "grid_y": 82, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y127": { + "bits": {}, + "grid_x": 56, + "grid_y": 81, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y128": { + "bits": {}, + "grid_x": 56, + "grid_y": 80, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y129": { + "bits": {}, + "grid_x": 56, + "grid_y": 79, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y131": { + "bits": {}, + "grid_x": 56, + "grid_y": 77, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y132": { + "bits": {}, + "grid_x": 56, + "grid_y": 76, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y133": { + "bits": {}, + "grid_x": 56, + "grid_y": 75, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y134": { + "bits": {}, + "grid_x": 56, + "grid_y": 74, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y135": { + "bits": {}, + "grid_x": 56, + "grid_y": 73, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y136": { + "bits": {}, + "grid_x": 56, + "grid_y": 72, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y137": { + "bits": {}, + "grid_x": 56, + "grid_y": 71, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y138": { + "bits": {}, + "grid_x": 56, + "grid_y": 70, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y139": { + "bits": {}, + "grid_x": 56, + "grid_y": 69, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y140": { + "bits": {}, + "grid_x": 56, + "grid_y": 68, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y141": { + "bits": {}, + "grid_x": 56, + "grid_y": 67, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y142": { + "bits": {}, + "grid_x": 56, + "grid_y": 66, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y143": { + "bits": {}, + "grid_x": 56, + "grid_y": 65, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y144": { + "bits": {}, + "grid_x": 56, + "grid_y": 64, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y145": { + "bits": {}, + "grid_x": 56, + "grid_y": 63, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y146": { + "bits": {}, + "grid_x": 56, + "grid_y": 62, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y147": { + "bits": {}, + "grid_x": 56, + "grid_y": 61, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y148": { + "bits": {}, + "grid_x": 56, + "grid_y": 60, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y149": { + "bits": {}, + "grid_x": 56, + "grid_y": 59, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y150": { + "bits": {}, + "grid_x": 56, + "grid_y": 58, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y151": { + "bits": {}, + "grid_x": 56, + "grid_y": 57, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y152": { + "bits": {}, + "grid_x": 56, + "grid_y": 56, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y153": { + "bits": {}, + "grid_x": 56, + "grid_y": 55, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y154": { + "bits": {}, + "grid_x": 56, + "grid_y": 54, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y155": { + "bits": {}, + "grid_x": 56, + "grid_y": 53, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y53": { + "bits": {}, + "grid_x": 56, + "grid_y": 155, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y54": { + "bits": {}, + "grid_x": 56, + "grid_y": 154, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y55": { + "bits": {}, + "grid_x": 56, + "grid_y": 153, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y56": { + "bits": {}, + "grid_x": 56, + "grid_y": 152, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y57": { + "bits": {}, + "grid_x": 56, + "grid_y": 151, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y58": { + "bits": {}, + "grid_x": 56, + "grid_y": 150, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y59": { + "bits": {}, + "grid_x": 56, + "grid_y": 149, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y60": { + "bits": {}, + "grid_x": 56, + "grid_y": 148, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y61": { + "bits": {}, + "grid_x": 56, + "grid_y": 147, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y62": { + "bits": {}, + "grid_x": 56, + "grid_y": 146, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y63": { + "bits": {}, + "grid_x": 56, + "grid_y": 145, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y64": { + "bits": {}, + "grid_x": 56, + "grid_y": 144, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y65": { + "bits": {}, + "grid_x": 56, + "grid_y": 143, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y66": { + "bits": {}, + "grid_x": 56, + "grid_y": 142, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y67": { + "bits": {}, + "grid_x": 56, + "grid_y": 141, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y68": { + "bits": {}, + "grid_x": 56, + "grid_y": 140, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y69": { + "bits": {}, + "grid_x": 56, + "grid_y": 139, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y70": { + "bits": {}, + "grid_x": 56, + "grid_y": 138, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y71": { + "bits": {}, + "grid_x": 56, + "grid_y": 137, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y72": { + "bits": {}, + "grid_x": 56, + "grid_y": 136, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y73": { + "bits": {}, + "grid_x": 56, + "grid_y": 135, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y74": { + "bits": {}, + "grid_x": 56, + "grid_y": 134, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y75": { + "bits": {}, + "grid_x": 56, + "grid_y": 133, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y76": { + "bits": {}, + "grid_x": 56, + "grid_y": 132, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y77": { + "bits": {}, + "grid_x": 56, + "grid_y": 131, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y79": { + "bits": {}, + "grid_x": 56, + "grid_y": 129, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y80": { + "bits": {}, + "grid_x": 56, + "grid_y": 128, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y81": { + "bits": {}, + "grid_x": 56, + "grid_y": 127, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y82": { + "bits": {}, + "grid_x": 56, + "grid_y": 126, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y83": { + "bits": {}, + "grid_x": 56, + "grid_y": 125, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y84": { + "bits": {}, + "grid_x": 56, + "grid_y": 124, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y85": { + "bits": {}, + "grid_x": 56, + "grid_y": 123, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y86": { + "bits": {}, + "grid_x": 56, + "grid_y": 122, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y87": { + "bits": {}, + "grid_x": 56, + "grid_y": 121, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y88": { + "bits": {}, + "grid_x": 56, + "grid_y": 120, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y89": { + "bits": {}, + "grid_x": 56, + "grid_y": 119, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y90": { + "bits": {}, + "grid_x": 56, + "grid_y": 118, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y91": { + "bits": {}, + "grid_x": 56, + "grid_y": 117, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y92": { + "bits": {}, + "grid_x": 56, + "grid_y": 116, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y93": { + "bits": {}, + "grid_x": 56, + "grid_y": 115, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y94": { + "bits": {}, + "grid_x": 56, + "grid_y": 114, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y95": { + "bits": {}, + "grid_x": 56, + "grid_y": 113, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y96": { + "bits": {}, + "grid_x": 56, + "grid_y": 112, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y97": { + "bits": {}, + "grid_x": 56, + "grid_y": 111, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y98": { + "bits": {}, + "grid_x": 56, + "grid_y": 110, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X56Y99": { + "bits": {}, + "grid_x": 56, + "grid_y": 109, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y100": { + "bits": {}, + "grid_x": 59, + "grid_y": 108, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y101": { + "bits": {}, + "grid_x": 59, + "grid_y": 107, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y102": { + "bits": {}, + "grid_x": 59, + "grid_y": 106, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y103": { + "bits": {}, + "grid_x": 59, + "grid_y": 105, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y105": { + "bits": {}, + "grid_x": 59, + "grid_y": 103, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y106": { + "bits": {}, + "grid_x": 59, + "grid_y": 102, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y107": { + "bits": {}, + "grid_x": 59, + "grid_y": 101, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y108": { + "bits": {}, + "grid_x": 59, + "grid_y": 100, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y109": { + "bits": {}, + "grid_x": 59, + "grid_y": 99, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y110": { + "bits": {}, + "grid_x": 59, + "grid_y": 98, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y111": { + "bits": {}, + "grid_x": 59, + "grid_y": 97, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y112": { + "bits": {}, + "grid_x": 59, + "grid_y": 96, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y113": { + "bits": {}, + "grid_x": 59, + "grid_y": 95, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y114": { + "bits": {}, + "grid_x": 59, + "grid_y": 94, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y115": { + "bits": {}, + "grid_x": 59, + "grid_y": 93, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y116": { + "bits": {}, + "grid_x": 59, + "grid_y": 92, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y117": { + "bits": {}, + "grid_x": 59, + "grid_y": 91, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y118": { + "bits": {}, + "grid_x": 59, + "grid_y": 90, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y119": { + "bits": {}, + "grid_x": 59, + "grid_y": 89, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y120": { + "bits": {}, + "grid_x": 59, + "grid_y": 88, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y121": { + "bits": {}, + "grid_x": 59, + "grid_y": 87, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y122": { + "bits": {}, + "grid_x": 59, + "grid_y": 86, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y123": { + "bits": {}, + "grid_x": 59, + "grid_y": 85, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y124": { + "bits": {}, + "grid_x": 59, + "grid_y": 84, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y125": { + "bits": {}, + "grid_x": 59, + "grid_y": 83, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y126": { + "bits": {}, + "grid_x": 59, + "grid_y": 82, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y127": { + "bits": {}, + "grid_x": 59, + "grid_y": 81, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y128": { + "bits": {}, + "grid_x": 59, + "grid_y": 80, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y129": { + "bits": {}, + "grid_x": 59, + "grid_y": 79, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y131": { + "bits": {}, + "grid_x": 59, + "grid_y": 77, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y132": { + "bits": {}, + "grid_x": 59, + "grid_y": 76, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y133": { + "bits": {}, + "grid_x": 59, + "grid_y": 75, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y134": { + "bits": {}, + "grid_x": 59, + "grid_y": 74, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y135": { + "bits": {}, + "grid_x": 59, + "grid_y": 73, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y136": { + "bits": {}, + "grid_x": 59, + "grid_y": 72, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y137": { + "bits": {}, + "grid_x": 59, + "grid_y": 71, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y138": { + "bits": {}, + "grid_x": 59, + "grid_y": 70, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y139": { + "bits": {}, + "grid_x": 59, + "grid_y": 69, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y140": { + "bits": {}, + "grid_x": 59, + "grid_y": 68, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y141": { + "bits": {}, + "grid_x": 59, + "grid_y": 67, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y142": { + "bits": {}, + "grid_x": 59, + "grid_y": 66, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y143": { + "bits": {}, + "grid_x": 59, + "grid_y": 65, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y144": { + "bits": {}, + "grid_x": 59, + "grid_y": 64, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y145": { + "bits": {}, + "grid_x": 59, + "grid_y": 63, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y146": { + "bits": {}, + "grid_x": 59, + "grid_y": 62, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y147": { + "bits": {}, + "grid_x": 59, + "grid_y": 61, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y148": { + "bits": {}, + "grid_x": 59, + "grid_y": 60, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y149": { + "bits": {}, + "grid_x": 59, + "grid_y": 59, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y150": { + "bits": {}, + "grid_x": 59, + "grid_y": 58, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y151": { + "bits": {}, + "grid_x": 59, + "grid_y": 57, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y152": { + "bits": {}, + "grid_x": 59, + "grid_y": 56, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y153": { + "bits": {}, + "grid_x": 59, + "grid_y": 55, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y154": { + "bits": {}, + "grid_x": 59, + "grid_y": 54, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y155": { + "bits": {}, + "grid_x": 59, + "grid_y": 53, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y53": { + "bits": {}, + "grid_x": 59, + "grid_y": 155, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y54": { + "bits": {}, + "grid_x": 59, + "grid_y": 154, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y55": { + "bits": {}, + "grid_x": 59, + "grid_y": 153, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y56": { + "bits": {}, + "grid_x": 59, + "grid_y": 152, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y57": { + "bits": {}, + "grid_x": 59, + "grid_y": 151, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y58": { + "bits": {}, + "grid_x": 59, + "grid_y": 150, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y59": { + "bits": {}, + "grid_x": 59, + "grid_y": 149, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y60": { + "bits": {}, + "grid_x": 59, + "grid_y": 148, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y61": { + "bits": {}, + "grid_x": 59, + "grid_y": 147, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y62": { + "bits": {}, + "grid_x": 59, + "grid_y": 146, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y63": { + "bits": {}, + "grid_x": 59, + "grid_y": 145, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y64": { + "bits": {}, + "grid_x": 59, + "grid_y": 144, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y65": { + "bits": {}, + "grid_x": 59, + "grid_y": 143, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y66": { + "bits": {}, + "grid_x": 59, + "grid_y": 142, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y67": { + "bits": {}, + "grid_x": 59, + "grid_y": 141, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y68": { + "bits": {}, + "grid_x": 59, + "grid_y": 140, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y69": { + "bits": {}, + "grid_x": 59, + "grid_y": 139, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y70": { + "bits": {}, + "grid_x": 59, + "grid_y": 138, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y71": { + "bits": {}, + "grid_x": 59, + "grid_y": 137, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y72": { + "bits": {}, + "grid_x": 59, + "grid_y": 136, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y73": { + "bits": {}, + "grid_x": 59, + "grid_y": 135, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y74": { + "bits": {}, + "grid_x": 59, + "grid_y": 134, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y75": { + "bits": {}, + "grid_x": 59, + "grid_y": 133, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y76": { + "bits": {}, + "grid_x": 59, + "grid_y": 132, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y77": { + "bits": {}, + "grid_x": 59, + "grid_y": 131, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y79": { + "bits": {}, + "grid_x": 59, + "grid_y": 129, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y80": { + "bits": {}, + "grid_x": 59, + "grid_y": 128, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y81": { + "bits": {}, + "grid_x": 59, + "grid_y": 127, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y82": { + "bits": {}, + "grid_x": 59, + "grid_y": 126, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y83": { + "bits": {}, + "grid_x": 59, + "grid_y": 125, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y84": { + "bits": {}, + "grid_x": 59, + "grid_y": 124, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y85": { + "bits": {}, + "grid_x": 59, + "grid_y": 123, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y86": { + "bits": {}, + "grid_x": 59, + "grid_y": 122, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y87": { + "bits": {}, + "grid_x": 59, + "grid_y": 121, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y88": { + "bits": {}, + "grid_x": 59, + "grid_y": 120, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y89": { + "bits": {}, + "grid_x": 59, + "grid_y": 119, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y90": { + "bits": {}, + "grid_x": 59, + "grid_y": 118, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y91": { + "bits": {}, + "grid_x": 59, + "grid_y": 117, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y92": { + "bits": {}, + "grid_x": 59, + "grid_y": 116, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y93": { + "bits": {}, + "grid_x": 59, + "grid_y": 115, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y94": { + "bits": {}, + "grid_x": 59, + "grid_y": 114, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y95": { + "bits": {}, + "grid_x": 59, + "grid_y": 113, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y96": { + "bits": {}, + "grid_x": 59, + "grid_y": 112, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y97": { + "bits": {}, + "grid_x": 59, + "grid_y": 111, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y98": { + "bits": {}, + "grid_x": 59, + "grid_y": 110, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X59Y99": { + "bits": {}, + "grid_x": 59, + "grid_y": 109, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y100": { + "bits": {}, + "grid_x": 60, + "grid_y": 108, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y101": { + "bits": {}, + "grid_x": 60, + "grid_y": 107, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y102": { + "bits": {}, + "grid_x": 60, + "grid_y": 106, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y103": { + "bits": {}, + "grid_x": 60, + "grid_y": 105, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y105": { + "bits": {}, + "grid_x": 60, + "grid_y": 103, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y106": { + "bits": {}, + "grid_x": 60, + "grid_y": 102, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y107": { + "bits": {}, + "grid_x": 60, + "grid_y": 101, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y108": { + "bits": {}, + "grid_x": 60, + "grid_y": 100, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y109": { + "bits": {}, + "grid_x": 60, + "grid_y": 99, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y110": { + "bits": {}, + "grid_x": 60, + "grid_y": 98, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y111": { + "bits": {}, + "grid_x": 60, + "grid_y": 97, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y112": { + "bits": {}, + "grid_x": 60, + "grid_y": 96, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y113": { + "bits": {}, + "grid_x": 60, + "grid_y": 95, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y114": { + "bits": {}, + "grid_x": 60, + "grid_y": 94, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y115": { + "bits": {}, + "grid_x": 60, + "grid_y": 93, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y116": { + "bits": {}, + "grid_x": 60, + "grid_y": 92, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y117": { + "bits": {}, + "grid_x": 60, + "grid_y": 91, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y118": { + "bits": {}, + "grid_x": 60, + "grid_y": 90, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y119": { + "bits": {}, + "grid_x": 60, + "grid_y": 89, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y120": { + "bits": {}, + "grid_x": 60, + "grid_y": 88, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y121": { + "bits": {}, + "grid_x": 60, + "grid_y": 87, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y122": { + "bits": {}, + "grid_x": 60, + "grid_y": 86, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y123": { + "bits": {}, + "grid_x": 60, + "grid_y": 85, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y124": { + "bits": {}, + "grid_x": 60, + "grid_y": 84, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y125": { + "bits": {}, + "grid_x": 60, + "grid_y": 83, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y126": { + "bits": {}, + "grid_x": 60, + "grid_y": 82, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y127": { + "bits": {}, + "grid_x": 60, + "grid_y": 81, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y128": { + "bits": {}, + "grid_x": 60, + "grid_y": 80, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y129": { + "bits": {}, + "grid_x": 60, + "grid_y": 79, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y131": { + "bits": {}, + "grid_x": 60, + "grid_y": 77, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y132": { + "bits": {}, + "grid_x": 60, + "grid_y": 76, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y133": { + "bits": {}, + "grid_x": 60, + "grid_y": 75, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y134": { + "bits": {}, + "grid_x": 60, + "grid_y": 74, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y135": { + "bits": {}, + "grid_x": 60, + "grid_y": 73, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y136": { + "bits": {}, + "grid_x": 60, + "grid_y": 72, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y137": { + "bits": {}, + "grid_x": 60, + "grid_y": 71, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y138": { + "bits": {}, + "grid_x": 60, + "grid_y": 70, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y139": { + "bits": {}, + "grid_x": 60, + "grid_y": 69, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y140": { + "bits": {}, + "grid_x": 60, + "grid_y": 68, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y141": { + "bits": {}, + "grid_x": 60, + "grid_y": 67, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y142": { + "bits": {}, + "grid_x": 60, + "grid_y": 66, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y143": { + "bits": {}, + "grid_x": 60, + "grid_y": 65, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y144": { + "bits": {}, + "grid_x": 60, + "grid_y": 64, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y145": { + "bits": {}, + "grid_x": 60, + "grid_y": 63, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y146": { + "bits": {}, + "grid_x": 60, + "grid_y": 62, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y147": { + "bits": {}, + "grid_x": 60, + "grid_y": 61, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y148": { + "bits": {}, + "grid_x": 60, + "grid_y": 60, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y149": { + "bits": {}, + "grid_x": 60, + "grid_y": 59, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y150": { + "bits": {}, + "grid_x": 60, + "grid_y": 58, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y151": { + "bits": {}, + "grid_x": 60, + "grid_y": 57, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y152": { + "bits": {}, + "grid_x": 60, + "grid_y": 56, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y153": { + "bits": {}, + "grid_x": 60, + "grid_y": 55, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y154": { + "bits": {}, + "grid_x": 60, + "grid_y": 54, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y155": { + "bits": {}, + "grid_x": 60, + "grid_y": 53, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y53": { + "bits": {}, + "grid_x": 60, + "grid_y": 155, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y54": { + "bits": {}, + "grid_x": 60, + "grid_y": 154, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y55": { + "bits": {}, + "grid_x": 60, + "grid_y": 153, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y56": { + "bits": {}, + "grid_x": 60, + "grid_y": 152, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y57": { + "bits": {}, + "grid_x": 60, + "grid_y": 151, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y58": { + "bits": {}, + "grid_x": 60, + "grid_y": 150, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y59": { + "bits": {}, + "grid_x": 60, + "grid_y": 149, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y60": { + "bits": {}, + "grid_x": 60, + "grid_y": 148, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y61": { + "bits": {}, + "grid_x": 60, + "grid_y": 147, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y62": { + "bits": {}, + "grid_x": 60, + "grid_y": 146, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y63": { + "bits": {}, + "grid_x": 60, + "grid_y": 145, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y64": { + "bits": {}, + "grid_x": 60, + "grid_y": 144, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y65": { + "bits": {}, + "grid_x": 60, + "grid_y": 143, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y66": { + "bits": {}, + "grid_x": 60, + "grid_y": 142, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y67": { + "bits": {}, + "grid_x": 60, + "grid_y": 141, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y68": { + "bits": {}, + "grid_x": 60, + "grid_y": 140, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y69": { + "bits": {}, + "grid_x": 60, + "grid_y": 139, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y70": { + "bits": {}, + "grid_x": 60, + "grid_y": 138, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y71": { + "bits": {}, + "grid_x": 60, + "grid_y": 137, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y72": { + "bits": {}, + "grid_x": 60, + "grid_y": 136, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y73": { + "bits": {}, + "grid_x": 60, + "grid_y": 135, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y74": { + "bits": {}, + "grid_x": 60, + "grid_y": 134, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y75": { + "bits": {}, + "grid_x": 60, + "grid_y": 133, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y76": { + "bits": {}, + "grid_x": 60, + "grid_y": 132, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y77": { + "bits": {}, + "grid_x": 60, + "grid_y": 131, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y79": { + "bits": {}, + "grid_x": 60, + "grid_y": 129, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y80": { + "bits": {}, + "grid_x": 60, + "grid_y": 128, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y81": { + "bits": {}, + "grid_x": 60, + "grid_y": 127, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y82": { + "bits": {}, + "grid_x": 60, + "grid_y": 126, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y83": { + "bits": {}, + "grid_x": 60, + "grid_y": 125, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y84": { + "bits": {}, + "grid_x": 60, + "grid_y": 124, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y85": { + "bits": {}, + "grid_x": 60, + "grid_y": 123, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y86": { + "bits": {}, + "grid_x": 60, + "grid_y": 122, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y87": { + "bits": {}, + "grid_x": 60, + "grid_y": 121, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y88": { + "bits": {}, + "grid_x": 60, + "grid_y": 120, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y89": { + "bits": {}, + "grid_x": 60, + "grid_y": 119, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y90": { + "bits": {}, + "grid_x": 60, + "grid_y": 118, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y91": { + "bits": {}, + "grid_x": 60, + "grid_y": 117, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y92": { + "bits": {}, + "grid_x": 60, + "grid_y": 116, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y93": { + "bits": {}, + "grid_x": 60, + "grid_y": 115, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y94": { + "bits": {}, + "grid_x": 60, + "grid_y": 114, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y95": { + "bits": {}, + "grid_x": 60, + "grid_y": 113, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y96": { + "bits": {}, + "grid_x": 60, + "grid_y": 112, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y97": { + "bits": {}, + "grid_x": 60, + "grid_y": 111, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y98": { + "bits": {}, + "grid_x": 60, + "grid_y": 110, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_FEEDTHRU_2_X60Y99": { + "bits": {}, + "grid_x": 60, + "grid_y": 109, + "sites": {}, + "type": "INT_FEEDTHRU_2" + }, + "INT_INTERFACE_L_X14Y0": { + "bits": {}, + "grid_x": 40, + "grid_y": 207, + "segment": "SEG_DSP0_L_X14Y0", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y1": { + "bits": {}, + "grid_x": 40, + "grid_y": 206, + "segment": "SEG_DSP1_L_X14Y0", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y10": { + "bits": {}, + "grid_x": 40, + "grid_y": 197, + "segment": "SEG_DSP0_L_X14Y10", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y100": { + "bits": {}, + "grid_x": 40, + "grid_y": 103, + "segment": "SEG_DSP0_L_X14Y100", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y101": { + "bits": {}, + "grid_x": 40, + "grid_y": 102, + "segment": "SEG_DSP1_L_X14Y100", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y102": { + "bits": {}, + "grid_x": 40, + "grid_y": 101, + "segment": "SEG_DSP2_L_X14Y100", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y103": { + "bits": {}, + "grid_x": 40, + "grid_y": 100, + "segment": "SEG_DSP3_L_X14Y100", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y104": { + "bits": {}, + "grid_x": 40, + "grid_y": 99, + "segment": "SEG_DSP4_L_X14Y100", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y105": { + "bits": {}, + "grid_x": 40, + "grid_y": 98, + "segment": "SEG_DSP0_L_X14Y105", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y106": { + "bits": {}, + "grid_x": 40, + "grid_y": 97, + "segment": "SEG_DSP1_L_X14Y105", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y107": { + "bits": {}, + "grid_x": 40, + "grid_y": 96, + "segment": "SEG_DSP2_L_X14Y105", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y108": { + "bits": {}, + "grid_x": 40, + "grid_y": 95, + "segment": "SEG_DSP3_L_X14Y105", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y109": { + "bits": {}, + "grid_x": 40, + "grid_y": 94, + "segment": "SEG_DSP4_L_X14Y105", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y11": { + "bits": {}, + "grid_x": 40, + "grid_y": 196, + "segment": "SEG_DSP1_L_X14Y10", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y110": { + "bits": {}, + "grid_x": 40, + "grid_y": 93, + "segment": "SEG_DSP0_L_X14Y110", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y111": { + "bits": {}, + "grid_x": 40, + "grid_y": 92, + "segment": "SEG_DSP1_L_X14Y110", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y112": { + "bits": {}, + "grid_x": 40, + "grid_y": 91, + "segment": "SEG_DSP2_L_X14Y110", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y113": { + "bits": {}, + "grid_x": 40, + "grid_y": 90, + "segment": "SEG_DSP3_L_X14Y110", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y114": { + "bits": {}, + "grid_x": 40, + "grid_y": 89, + "segment": "SEG_DSP4_L_X14Y110", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y115": { + "bits": {}, + "grid_x": 40, + "grid_y": 88, + "segment": "SEG_DSP0_L_X14Y115", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y116": { + "bits": {}, + "grid_x": 40, + "grid_y": 87, + "segment": "SEG_DSP1_L_X14Y115", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y117": { + "bits": {}, + "grid_x": 40, + "grid_y": 86, + "segment": "SEG_DSP2_L_X14Y115", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y118": { + "bits": {}, + "grid_x": 40, + "grid_y": 85, + "segment": "SEG_DSP3_L_X14Y115", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y119": { + "bits": {}, + "grid_x": 40, + "grid_y": 84, + "segment": "SEG_DSP4_L_X14Y115", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y12": { + "bits": {}, + "grid_x": 40, + "grid_y": 195, + "segment": "SEG_DSP2_L_X14Y10", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y120": { + "bits": {}, + "grid_x": 40, + "grid_y": 83, + "segment": "SEG_DSP0_L_X14Y120", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y121": { + "bits": {}, + "grid_x": 40, + "grid_y": 82, + "segment": "SEG_DSP1_L_X14Y120", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y122": { + "bits": {}, + "grid_x": 40, + "grid_y": 81, + "segment": "SEG_DSP2_L_X14Y120", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y123": { + "bits": {}, + "grid_x": 40, + "grid_y": 80, + "segment": "SEG_DSP3_L_X14Y120", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y124": { + "bits": {}, + "grid_x": 40, + "grid_y": 79, + "segment": "SEG_DSP4_L_X14Y120", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y125": { + "bits": {}, + "grid_x": 40, + "grid_y": 77, + "segment": "SEG_DSP0_L_X14Y125", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y126": { + "bits": {}, + "grid_x": 40, + "grid_y": 76, + "segment": "SEG_DSP1_L_X14Y125", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y127": { + "bits": {}, + "grid_x": 40, + "grid_y": 75, + "segment": "SEG_DSP2_L_X14Y125", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y128": { + "bits": {}, + "grid_x": 40, + "grid_y": 74, + "segment": "SEG_DSP3_L_X14Y125", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y129": { + "bits": {}, + "grid_x": 40, + "grid_y": 73, + "segment": "SEG_DSP4_L_X14Y125", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y13": { + "bits": {}, + "grid_x": 40, + "grid_y": 194, + "segment": "SEG_DSP3_L_X14Y10", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y130": { + "bits": {}, + "grid_x": 40, + "grid_y": 72, + "segment": "SEG_DSP0_L_X14Y130", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y131": { + "bits": {}, + "grid_x": 40, + "grid_y": 71, + "segment": "SEG_DSP1_L_X14Y130", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y132": { + "bits": {}, + "grid_x": 40, + "grid_y": 70, + "segment": "SEG_DSP2_L_X14Y130", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y133": { + "bits": {}, + "grid_x": 40, + "grid_y": 69, + "segment": "SEG_DSP3_L_X14Y130", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y134": { + "bits": {}, + "grid_x": 40, + "grid_y": 68, + "segment": "SEG_DSP4_L_X14Y130", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y135": { + "bits": {}, + "grid_x": 40, + "grid_y": 67, + "segment": "SEG_DSP0_L_X14Y135", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y136": { + "bits": {}, + "grid_x": 40, + "grid_y": 66, + "segment": "SEG_DSP1_L_X14Y135", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y137": { + "bits": {}, + "grid_x": 40, + "grid_y": 65, + "segment": "SEG_DSP2_L_X14Y135", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y138": { + "bits": {}, + "grid_x": 40, + "grid_y": 64, + "segment": "SEG_DSP3_L_X14Y135", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y139": { + "bits": {}, + "grid_x": 40, + "grid_y": 63, + "segment": "SEG_DSP4_L_X14Y135", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y14": { + "bits": {}, + "grid_x": 40, + "grid_y": 193, + "segment": "SEG_DSP4_L_X14Y10", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y140": { + "bits": {}, + "grid_x": 40, + "grid_y": 62, + "segment": "SEG_DSP0_L_X14Y140", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y141": { + "bits": {}, + "grid_x": 40, + "grid_y": 61, + "segment": "SEG_DSP1_L_X14Y140", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y142": { + "bits": {}, + "grid_x": 40, + "grid_y": 60, + "segment": "SEG_DSP2_L_X14Y140", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y143": { + "bits": {}, + "grid_x": 40, + "grid_y": 59, + "segment": "SEG_DSP3_L_X14Y140", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y144": { + "bits": {}, + "grid_x": 40, + "grid_y": 58, + "segment": "SEG_DSP4_L_X14Y140", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y145": { + "bits": {}, + "grid_x": 40, + "grid_y": 57, + "segment": "SEG_DSP0_L_X14Y145", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y146": { + "bits": {}, + "grid_x": 40, + "grid_y": 56, + "segment": "SEG_DSP1_L_X14Y145", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y147": { + "bits": {}, + "grid_x": 40, + "grid_y": 55, + "segment": "SEG_DSP2_L_X14Y145", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y148": { + "bits": {}, + "grid_x": 40, + "grid_y": 54, + "segment": "SEG_DSP3_L_X14Y145", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y149": { + "bits": {}, + "grid_x": 40, + "grid_y": 53, + "segment": "SEG_DSP4_L_X14Y145", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y15": { + "bits": {}, + "grid_x": 40, + "grid_y": 192, + "segment": "SEG_DSP0_L_X14Y15", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y150": { + "bits": {}, + "grid_x": 40, + "grid_y": 51, + "segment": "SEG_DSP0_L_X14Y150", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y151": { + "bits": {}, + "grid_x": 40, + "grid_y": 50, + "segment": "SEG_DSP1_L_X14Y150", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y152": { + "bits": {}, + "grid_x": 40, + "grid_y": 49, + "segment": "SEG_DSP2_L_X14Y150", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y153": { + "bits": {}, + "grid_x": 40, + "grid_y": 48, + "segment": "SEG_DSP3_L_X14Y150", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y154": { + "bits": {}, + "grid_x": 40, + "grid_y": 47, + "segment": "SEG_DSP4_L_X14Y150", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y155": { + "bits": {}, + "grid_x": 40, + "grid_y": 46, + "segment": "SEG_DSP0_L_X14Y155", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y156": { + "bits": {}, + "grid_x": 40, + "grid_y": 45, + "segment": "SEG_DSP1_L_X14Y155", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y157": { + "bits": {}, + "grid_x": 40, + "grid_y": 44, + "segment": "SEG_DSP2_L_X14Y155", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y158": { + "bits": {}, + "grid_x": 40, + "grid_y": 43, + "segment": "SEG_DSP3_L_X14Y155", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y159": { + "bits": {}, + "grid_x": 40, + "grid_y": 42, + "segment": "SEG_DSP4_L_X14Y155", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y16": { + "bits": {}, + "grid_x": 40, + "grid_y": 191, + "segment": "SEG_DSP1_L_X14Y15", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y160": { + "bits": {}, + "grid_x": 40, + "grid_y": 41, + "segment": "SEG_DSP0_L_X14Y160", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y161": { + "bits": {}, + "grid_x": 40, + "grid_y": 40, + "segment": "SEG_DSP1_L_X14Y160", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y162": { + "bits": {}, + "grid_x": 40, + "grid_y": 39, + "segment": "SEG_DSP2_L_X14Y160", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y163": { + "bits": {}, + "grid_x": 40, + "grid_y": 38, + "segment": "SEG_DSP3_L_X14Y160", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y164": { + "bits": {}, + "grid_x": 40, + "grid_y": 37, + "segment": "SEG_DSP4_L_X14Y160", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y165": { + "bits": {}, + "grid_x": 40, + "grid_y": 36, + "segment": "SEG_DSP0_L_X14Y165", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y166": { + "bits": {}, + "grid_x": 40, + "grid_y": 35, + "segment": "SEG_DSP1_L_X14Y165", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y167": { + "bits": {}, + "grid_x": 40, + "grid_y": 34, + "segment": "SEG_DSP2_L_X14Y165", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y168": { + "bits": {}, + "grid_x": 40, + "grid_y": 33, + "segment": "SEG_DSP3_L_X14Y165", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y169": { + "bits": {}, + "grid_x": 40, + "grid_y": 32, + "segment": "SEG_DSP4_L_X14Y165", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y17": { + "bits": {}, + "grid_x": 40, + "grid_y": 190, + "segment": "SEG_DSP2_L_X14Y15", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y170": { + "bits": {}, + "grid_x": 40, + "grid_y": 31, + "segment": "SEG_DSP0_L_X14Y170", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y171": { + "bits": {}, + "grid_x": 40, + "grid_y": 30, + "segment": "SEG_DSP1_L_X14Y170", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y172": { + "bits": {}, + "grid_x": 40, + "grid_y": 29, + "segment": "SEG_DSP2_L_X14Y170", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y173": { + "bits": {}, + "grid_x": 40, + "grid_y": 28, + "segment": "SEG_DSP3_L_X14Y170", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y174": { + "bits": {}, + "grid_x": 40, + "grid_y": 27, + "segment": "SEG_DSP4_L_X14Y170", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y175": { + "bits": {}, + "grid_x": 40, + "grid_y": 25, + "segment": "SEG_DSP0_L_X14Y175", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y176": { + "bits": {}, + "grid_x": 40, + "grid_y": 24, + "segment": "SEG_DSP1_L_X14Y175", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y177": { + "bits": {}, + "grid_x": 40, + "grid_y": 23, + "segment": "SEG_DSP2_L_X14Y175", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y178": { + "bits": {}, + "grid_x": 40, + "grid_y": 22, + "segment": "SEG_DSP3_L_X14Y175", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y179": { + "bits": {}, + "grid_x": 40, + "grid_y": 21, + "segment": "SEG_DSP4_L_X14Y175", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y18": { + "bits": {}, + "grid_x": 40, + "grid_y": 189, + "segment": "SEG_DSP3_L_X14Y15", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y180": { + "bits": {}, + "grid_x": 40, + "grid_y": 20, + "segment": "SEG_DSP0_L_X14Y180", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y181": { + "bits": {}, + "grid_x": 40, + "grid_y": 19, + "segment": "SEG_DSP1_L_X14Y180", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y182": { + "bits": {}, + "grid_x": 40, + "grid_y": 18, + "segment": "SEG_DSP2_L_X14Y180", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y183": { + "bits": {}, + "grid_x": 40, + "grid_y": 17, + "segment": "SEG_DSP3_L_X14Y180", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y184": { + "bits": {}, + "grid_x": 40, + "grid_y": 16, + "segment": "SEG_DSP4_L_X14Y180", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y185": { + "bits": {}, + "grid_x": 40, + "grid_y": 15, + "segment": "SEG_DSP0_L_X14Y185", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y186": { + "bits": {}, + "grid_x": 40, + "grid_y": 14, + "segment": "SEG_DSP1_L_X14Y185", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y187": { + "bits": {}, + "grid_x": 40, + "grid_y": 13, + "segment": "SEG_DSP2_L_X14Y185", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y188": { + "bits": {}, + "grid_x": 40, + "grid_y": 12, + "segment": "SEG_DSP3_L_X14Y185", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y189": { + "bits": {}, + "grid_x": 40, + "grid_y": 11, + "segment": "SEG_DSP4_L_X14Y185", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y19": { + "bits": {}, + "grid_x": 40, + "grid_y": 188, + "segment": "SEG_DSP4_L_X14Y15", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y190": { + "bits": {}, + "grid_x": 40, + "grid_y": 10, + "segment": "SEG_DSP0_L_X14Y190", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y191": { + "bits": {}, + "grid_x": 40, + "grid_y": 9, + "segment": "SEG_DSP1_L_X14Y190", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y192": { + "bits": {}, + "grid_x": 40, + "grid_y": 8, + "segment": "SEG_DSP2_L_X14Y190", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y193": { + "bits": {}, + "grid_x": 40, + "grid_y": 7, + "segment": "SEG_DSP3_L_X14Y190", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y194": { + "bits": {}, + "grid_x": 40, + "grid_y": 6, + "segment": "SEG_DSP4_L_X14Y190", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y195": { + "bits": {}, + "grid_x": 40, + "grid_y": 5, + "segment": "SEG_DSP0_L_X14Y195", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y196": { + "bits": {}, + "grid_x": 40, + "grid_y": 4, + "segment": "SEG_DSP1_L_X14Y195", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y197": { + "bits": {}, + "grid_x": 40, + "grid_y": 3, + "segment": "SEG_DSP2_L_X14Y195", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y198": { + "bits": {}, + "grid_x": 40, + "grid_y": 2, + "segment": "SEG_DSP3_L_X14Y195", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y199": { + "bits": {}, + "grid_x": 40, + "grid_y": 1, + "segment": "SEG_DSP4_L_X14Y195", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y2": { + "bits": {}, + "grid_x": 40, + "grid_y": 205, + "segment": "SEG_DSP2_L_X14Y0", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y20": { + "bits": {}, + "grid_x": 40, + "grid_y": 187, + "segment": "SEG_DSP0_L_X14Y20", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y21": { + "bits": {}, + "grid_x": 40, + "grid_y": 186, + "segment": "SEG_DSP1_L_X14Y20", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y22": { + "bits": {}, + "grid_x": 40, + "grid_y": 185, + "segment": "SEG_DSP2_L_X14Y20", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y23": { + "bits": {}, + "grid_x": 40, + "grid_y": 184, + "segment": "SEG_DSP3_L_X14Y20", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y24": { + "bits": {}, + "grid_x": 40, + "grid_y": 183, + "segment": "SEG_DSP4_L_X14Y20", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y25": { + "bits": {}, + "grid_x": 40, + "grid_y": 181, + "segment": "SEG_DSP0_L_X14Y25", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y26": { + "bits": {}, + "grid_x": 40, + "grid_y": 180, + "segment": "SEG_DSP1_L_X14Y25", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y27": { + "bits": {}, + "grid_x": 40, + "grid_y": 179, + "segment": "SEG_DSP2_L_X14Y25", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y28": { + "bits": {}, + "grid_x": 40, + "grid_y": 178, + "segment": "SEG_DSP3_L_X14Y25", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y29": { + "bits": {}, + "grid_x": 40, + "grid_y": 177, + "segment": "SEG_DSP4_L_X14Y25", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y3": { + "bits": {}, + "grid_x": 40, + "grid_y": 204, + "segment": "SEG_DSP3_L_X14Y0", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y30": { + "bits": {}, + "grid_x": 40, + "grid_y": 176, + "segment": "SEG_DSP0_L_X14Y30", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y31": { + "bits": {}, + "grid_x": 40, + "grid_y": 175, + "segment": "SEG_DSP1_L_X14Y30", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y32": { + "bits": {}, + "grid_x": 40, + "grid_y": 174, + "segment": "SEG_DSP2_L_X14Y30", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y33": { + "bits": {}, + "grid_x": 40, + "grid_y": 173, + "segment": "SEG_DSP3_L_X14Y30", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y34": { + "bits": {}, + "grid_x": 40, + "grid_y": 172, + "segment": "SEG_DSP4_L_X14Y30", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y35": { + "bits": {}, + "grid_x": 40, + "grid_y": 171, + "segment": "SEG_DSP0_L_X14Y35", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y36": { + "bits": {}, + "grid_x": 40, + "grid_y": 170, + "segment": "SEG_DSP1_L_X14Y35", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y37": { + "bits": {}, + "grid_x": 40, + "grid_y": 169, + "segment": "SEG_DSP2_L_X14Y35", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y38": { + "bits": {}, + "grid_x": 40, + "grid_y": 168, + "segment": "SEG_DSP3_L_X14Y35", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y39": { + "bits": {}, + "grid_x": 40, + "grid_y": 167, + "segment": "SEG_DSP4_L_X14Y35", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y4": { + "bits": {}, + "grid_x": 40, + "grid_y": 203, + "segment": "SEG_DSP4_L_X14Y0", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y40": { + "bits": {}, + "grid_x": 40, + "grid_y": 166, + "segment": "SEG_DSP0_L_X14Y40", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y41": { + "bits": {}, + "grid_x": 40, + "grid_y": 165, + "segment": "SEG_DSP1_L_X14Y40", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y42": { + "bits": {}, + "grid_x": 40, + "grid_y": 164, + "segment": "SEG_DSP2_L_X14Y40", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y43": { + "bits": {}, + "grid_x": 40, + "grid_y": 163, + "segment": "SEG_DSP3_L_X14Y40", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y44": { + "bits": {}, + "grid_x": 40, + "grid_y": 162, + "segment": "SEG_DSP4_L_X14Y40", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y45": { + "bits": {}, + "grid_x": 40, + "grid_y": 161, + "segment": "SEG_DSP0_L_X14Y45", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y46": { + "bits": {}, + "grid_x": 40, + "grid_y": 160, + "segment": "SEG_DSP1_L_X14Y45", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y47": { + "bits": {}, + "grid_x": 40, + "grid_y": 159, + "segment": "SEG_DSP2_L_X14Y45", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y48": { + "bits": {}, + "grid_x": 40, + "grid_y": 158, + "segment": "SEG_DSP3_L_X14Y45", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y49": { + "bits": {}, + "grid_x": 40, + "grid_y": 157, + "segment": "SEG_DSP4_L_X14Y45", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y5": { + "bits": {}, + "grid_x": 40, + "grid_y": 202, + "segment": "SEG_DSP0_L_X14Y5", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y50": { + "bits": {}, + "grid_x": 40, + "grid_y": 155, + "segment": "SEG_DSP0_L_X14Y50", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y51": { + "bits": {}, + "grid_x": 40, + "grid_y": 154, + "segment": "SEG_DSP1_L_X14Y50", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y52": { + "bits": {}, + "grid_x": 40, + "grid_y": 153, + "segment": "SEG_DSP2_L_X14Y50", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y53": { + "bits": {}, + "grid_x": 40, + "grid_y": 152, + "segment": "SEG_DSP3_L_X14Y50", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y54": { + "bits": {}, + "grid_x": 40, + "grid_y": 151, + "segment": "SEG_DSP4_L_X14Y50", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y55": { + "bits": {}, + "grid_x": 40, + "grid_y": 150, + "segment": "SEG_DSP0_L_X14Y55", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y56": { + "bits": {}, + "grid_x": 40, + "grid_y": 149, + "segment": "SEG_DSP1_L_X14Y55", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y57": { + "bits": {}, + "grid_x": 40, + "grid_y": 148, + "segment": "SEG_DSP2_L_X14Y55", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y58": { + "bits": {}, + "grid_x": 40, + "grid_y": 147, + "segment": "SEG_DSP3_L_X14Y55", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y59": { + "bits": {}, + "grid_x": 40, + "grid_y": 146, + "segment": "SEG_DSP4_L_X14Y55", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y6": { + "bits": {}, + "grid_x": 40, + "grid_y": 201, + "segment": "SEG_DSP1_L_X14Y5", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y60": { + "bits": {}, + "grid_x": 40, + "grid_y": 145, + "segment": "SEG_DSP0_L_X14Y60", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y61": { + "bits": {}, + "grid_x": 40, + "grid_y": 144, + "segment": "SEG_DSP1_L_X14Y60", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y62": { + "bits": {}, + "grid_x": 40, + "grid_y": 143, + "segment": "SEG_DSP2_L_X14Y60", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y63": { + "bits": {}, + "grid_x": 40, + "grid_y": 142, + "segment": "SEG_DSP3_L_X14Y60", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y64": { + "bits": {}, + "grid_x": 40, + "grid_y": 141, + "segment": "SEG_DSP4_L_X14Y60", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y65": { + "bits": {}, + "grid_x": 40, + "grid_y": 140, + "segment": "SEG_DSP0_L_X14Y65", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y66": { + "bits": {}, + "grid_x": 40, + "grid_y": 139, + "segment": "SEG_DSP1_L_X14Y65", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y67": { + "bits": {}, + "grid_x": 40, + "grid_y": 138, + "segment": "SEG_DSP2_L_X14Y65", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y68": { + "bits": {}, + "grid_x": 40, + "grid_y": 137, + "segment": "SEG_DSP3_L_X14Y65", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y69": { + "bits": {}, + "grid_x": 40, + "grid_y": 136, + "segment": "SEG_DSP4_L_X14Y65", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y7": { + "bits": {}, + "grid_x": 40, + "grid_y": 200, + "segment": "SEG_DSP2_L_X14Y5", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y70": { + "bits": {}, + "grid_x": 40, + "grid_y": 135, + "segment": "SEG_DSP0_L_X14Y70", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y71": { + "bits": {}, + "grid_x": 40, + "grid_y": 134, + "segment": "SEG_DSP1_L_X14Y70", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y72": { + "bits": {}, + "grid_x": 40, + "grid_y": 133, + "segment": "SEG_DSP2_L_X14Y70", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y73": { + "bits": {}, + "grid_x": 40, + "grid_y": 132, + "segment": "SEG_DSP3_L_X14Y70", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y74": { + "bits": {}, + "grid_x": 40, + "grid_y": 131, + "segment": "SEG_DSP4_L_X14Y70", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y75": { + "bits": {}, + "grid_x": 40, + "grid_y": 129, + "segment": "SEG_DSP0_L_X14Y75", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y76": { + "bits": {}, + "grid_x": 40, + "grid_y": 128, + "segment": "SEG_DSP1_L_X14Y75", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y77": { + "bits": {}, + "grid_x": 40, + "grid_y": 127, + "segment": "SEG_DSP2_L_X14Y75", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y78": { + "bits": {}, + "grid_x": 40, + "grid_y": 126, + "segment": "SEG_DSP3_L_X14Y75", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y79": { + "bits": {}, + "grid_x": 40, + "grid_y": 125, + "segment": "SEG_DSP4_L_X14Y75", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y8": { + "bits": {}, + "grid_x": 40, + "grid_y": 199, + "segment": "SEG_DSP3_L_X14Y5", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y80": { + "bits": {}, + "grid_x": 40, + "grid_y": 124, + "segment": "SEG_DSP0_L_X14Y80", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y81": { + "bits": {}, + "grid_x": 40, + "grid_y": 123, + "segment": "SEG_DSP1_L_X14Y80", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y82": { + "bits": {}, + "grid_x": 40, + "grid_y": 122, + "segment": "SEG_DSP2_L_X14Y80", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y83": { + "bits": {}, + "grid_x": 40, + "grid_y": 121, + "segment": "SEG_DSP3_L_X14Y80", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y84": { + "bits": {}, + "grid_x": 40, + "grid_y": 120, + "segment": "SEG_DSP4_L_X14Y80", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y85": { + "bits": {}, + "grid_x": 40, + "grid_y": 119, + "segment": "SEG_DSP0_L_X14Y85", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y86": { + "bits": {}, + "grid_x": 40, + "grid_y": 118, + "segment": "SEG_DSP1_L_X14Y85", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y87": { + "bits": {}, + "grid_x": 40, + "grid_y": 117, + "segment": "SEG_DSP2_L_X14Y85", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y88": { + "bits": {}, + "grid_x": 40, + "grid_y": 116, + "segment": "SEG_DSP3_L_X14Y85", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y89": { + "bits": {}, + "grid_x": 40, + "grid_y": 115, + "segment": "SEG_DSP4_L_X14Y85", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y9": { + "bits": {}, + "grid_x": 40, + "grid_y": 198, + "segment": "SEG_DSP4_L_X14Y5", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y90": { + "bits": {}, + "grid_x": 40, + "grid_y": 114, + "segment": "SEG_DSP0_L_X14Y90", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y91": { + "bits": {}, + "grid_x": 40, + "grid_y": 113, + "segment": "SEG_DSP1_L_X14Y90", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y92": { + "bits": {}, + "grid_x": 40, + "grid_y": 112, + "segment": "SEG_DSP2_L_X14Y90", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y93": { + "bits": {}, + "grid_x": 40, + "grid_y": 111, + "segment": "SEG_DSP3_L_X14Y90", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y94": { + "bits": {}, + "grid_x": 40, + "grid_y": 110, + "segment": "SEG_DSP4_L_X14Y90", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y95": { + "bits": {}, + "grid_x": 40, + "grid_y": 109, + "segment": "SEG_DSP0_L_X14Y95", + "segment_type": "dsp0_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y96": { + "bits": {}, + "grid_x": 40, + "grid_y": 108, + "segment": "SEG_DSP1_L_X14Y95", + "segment_type": "dsp1_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y97": { + "bits": {}, + "grid_x": 40, + "grid_y": 107, + "segment": "SEG_DSP2_L_X14Y95", + "segment_type": "dsp2_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y98": { + "bits": {}, + "grid_x": 40, + "grid_y": 106, + "segment": "SEG_DSP3_L_X14Y95", + "segment_type": "dsp3_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X14Y99": { + "bits": {}, + "grid_x": 40, + "grid_y": 105, + "segment": "SEG_DSP4_L_X14Y95", + "segment_type": "dsp4_l", + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y0": { + "bits": {}, + "grid_x": 63, + "grid_y": 207, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y1": { + "bits": {}, + "grid_x": 63, + "grid_y": 206, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y10": { + "bits": {}, + "grid_x": 63, + "grid_y": 197, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y100": { + "bits": {}, + "grid_x": 63, + "grid_y": 103, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y101": { + "bits": {}, + "grid_x": 63, + "grid_y": 102, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y102": { + "bits": {}, + "grid_x": 63, + "grid_y": 101, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y103": { + "bits": {}, + "grid_x": 63, + "grid_y": 100, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y104": { + "bits": {}, + "grid_x": 63, + "grid_y": 99, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y105": { + "bits": {}, + "grid_x": 63, + "grid_y": 98, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y106": { + "bits": {}, + "grid_x": 63, + "grid_y": 97, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y107": { + "bits": {}, + "grid_x": 63, + "grid_y": 96, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y108": { + "bits": {}, + "grid_x": 63, + "grid_y": 95, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y109": { + "bits": {}, + "grid_x": 63, + "grid_y": 94, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y11": { + "bits": {}, + "grid_x": 63, + "grid_y": 196, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y110": { + "bits": {}, + "grid_x": 63, + "grid_y": 93, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y111": { + "bits": {}, + "grid_x": 63, + "grid_y": 92, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y112": { + "bits": {}, + "grid_x": 63, + "grid_y": 91, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y113": { + "bits": {}, + "grid_x": 63, + "grid_y": 90, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y114": { + "bits": {}, + "grid_x": 63, + "grid_y": 89, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y115": { + "bits": {}, + "grid_x": 63, + "grid_y": 88, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y116": { + "bits": {}, + "grid_x": 63, + "grid_y": 87, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y117": { + "bits": {}, + "grid_x": 63, + "grid_y": 86, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y118": { + "bits": {}, + "grid_x": 63, + "grid_y": 85, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y119": { + "bits": {}, + "grid_x": 63, + "grid_y": 84, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y12": { + "bits": {}, + "grid_x": 63, + "grid_y": 195, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y120": { + "bits": {}, + "grid_x": 63, + "grid_y": 83, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y121": { + "bits": {}, + "grid_x": 63, + "grid_y": 82, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y122": { + "bits": {}, + "grid_x": 63, + "grid_y": 81, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y123": { + "bits": {}, + "grid_x": 63, + "grid_y": 80, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y124": { + "bits": {}, + "grid_x": 63, + "grid_y": 79, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y125": { + "bits": {}, + "grid_x": 63, + "grid_y": 77, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y126": { + "bits": {}, + "grid_x": 63, + "grid_y": 76, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y127": { + "bits": {}, + "grid_x": 63, + "grid_y": 75, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y128": { + "bits": {}, + "grid_x": 63, + "grid_y": 74, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y129": { + "bits": {}, + "grid_x": 63, + "grid_y": 73, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y13": { + "bits": {}, + "grid_x": 63, + "grid_y": 194, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y130": { + "bits": {}, + "grid_x": 63, + "grid_y": 72, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y131": { + "bits": {}, + "grid_x": 63, + "grid_y": 71, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y132": { + "bits": {}, + "grid_x": 63, + "grid_y": 70, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y133": { + "bits": {}, + "grid_x": 63, + "grid_y": 69, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y134": { + "bits": {}, + "grid_x": 63, + "grid_y": 68, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y135": { + "bits": {}, + "grid_x": 63, + "grid_y": 67, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y136": { + "bits": {}, + "grid_x": 63, + "grid_y": 66, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y137": { + "bits": {}, + "grid_x": 63, + "grid_y": 65, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y138": { + "bits": {}, + "grid_x": 63, + "grid_y": 64, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y139": { + "bits": {}, + "grid_x": 63, + "grid_y": 63, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y14": { + "bits": {}, + "grid_x": 63, + "grid_y": 193, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y140": { + "bits": {}, + "grid_x": 63, + "grid_y": 62, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y141": { + "bits": {}, + "grid_x": 63, + "grid_y": 61, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y142": { + "bits": {}, + "grid_x": 63, + "grid_y": 60, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y143": { + "bits": {}, + "grid_x": 63, + "grid_y": 59, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y144": { + "bits": {}, + "grid_x": 63, + "grid_y": 58, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y145": { + "bits": {}, + "grid_x": 63, + "grid_y": 57, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y146": { + "bits": {}, + "grid_x": 63, + "grid_y": 56, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y147": { + "bits": {}, + "grid_x": 63, + "grid_y": 55, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y148": { + "bits": {}, + "grid_x": 63, + "grid_y": 54, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y149": { + "bits": {}, + "grid_x": 63, + "grid_y": 53, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y15": { + "bits": {}, + "grid_x": 63, + "grid_y": 192, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y150": { + "bits": {}, + "grid_x": 63, + "grid_y": 51, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y151": { + "bits": {}, + "grid_x": 63, + "grid_y": 50, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y152": { + "bits": {}, + "grid_x": 63, + "grid_y": 49, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y153": { + "bits": {}, + "grid_x": 63, + "grid_y": 48, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y154": { + "bits": {}, + "grid_x": 63, + "grid_y": 47, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y155": { + "bits": {}, + "grid_x": 63, + "grid_y": 46, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y156": { + "bits": {}, + "grid_x": 63, + "grid_y": 45, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y157": { + "bits": {}, + "grid_x": 63, + "grid_y": 44, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y158": { + "bits": {}, + "grid_x": 63, + "grid_y": 43, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y159": { + "bits": {}, + "grid_x": 63, + "grid_y": 42, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y16": { + "bits": {}, + "grid_x": 63, + "grid_y": 191, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y160": { + "bits": {}, + "grid_x": 63, + "grid_y": 41, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y161": { + "bits": {}, + "grid_x": 63, + "grid_y": 40, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y162": { + "bits": {}, + "grid_x": 63, + "grid_y": 39, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y163": { + "bits": {}, + "grid_x": 63, + "grid_y": 38, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y164": { + "bits": {}, + "grid_x": 63, + "grid_y": 37, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y165": { + "bits": {}, + "grid_x": 63, + "grid_y": 36, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y166": { + "bits": {}, + "grid_x": 63, + "grid_y": 35, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y167": { + "bits": {}, + "grid_x": 63, + "grid_y": 34, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y168": { + "bits": {}, + "grid_x": 63, + "grid_y": 33, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y169": { + "bits": {}, + "grid_x": 63, + "grid_y": 32, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y17": { + "bits": {}, + "grid_x": 63, + "grid_y": 190, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y170": { + "bits": {}, + "grid_x": 63, + "grid_y": 31, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y171": { + "bits": {}, + "grid_x": 63, + "grid_y": 30, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y172": { + "bits": {}, + "grid_x": 63, + "grid_y": 29, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y173": { + "bits": {}, + "grid_x": 63, + "grid_y": 28, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y174": { + "bits": {}, + "grid_x": 63, + "grid_y": 27, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y175": { + "bits": {}, + "grid_x": 63, + "grid_y": 25, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y176": { + "bits": {}, + "grid_x": 63, + "grid_y": 24, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y177": { + "bits": {}, + "grid_x": 63, + "grid_y": 23, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y178": { + "bits": {}, + "grid_x": 63, + "grid_y": 22, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y179": { + "bits": {}, + "grid_x": 63, + "grid_y": 21, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y18": { + "bits": {}, + "grid_x": 63, + "grid_y": 189, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y180": { + "bits": {}, + "grid_x": 63, + "grid_y": 20, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y181": { + "bits": {}, + "grid_x": 63, + "grid_y": 19, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y182": { + "bits": {}, + "grid_x": 63, + "grid_y": 18, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y183": { + "bits": {}, + "grid_x": 63, + "grid_y": 17, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y184": { + "bits": {}, + "grid_x": 63, + "grid_y": 16, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y185": { + "bits": {}, + "grid_x": 63, + "grid_y": 15, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y186": { + "bits": {}, + "grid_x": 63, + "grid_y": 14, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y187": { + "bits": {}, + "grid_x": 63, + "grid_y": 13, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y188": { + "bits": {}, + "grid_x": 63, + "grid_y": 12, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y189": { + "bits": {}, + "grid_x": 63, + "grid_y": 11, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y19": { + "bits": {}, + "grid_x": 63, + "grid_y": 188, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y190": { + "bits": {}, + "grid_x": 63, + "grid_y": 10, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y191": { + "bits": {}, + "grid_x": 63, + "grid_y": 9, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y192": { + "bits": {}, + "grid_x": 63, + "grid_y": 8, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y193": { + "bits": {}, + "grid_x": 63, + "grid_y": 7, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y194": { + "bits": {}, + "grid_x": 63, + "grid_y": 6, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y195": { + "bits": {}, + "grid_x": 63, + "grid_y": 5, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y196": { + "bits": {}, + "grid_x": 63, + "grid_y": 4, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y197": { + "bits": {}, + "grid_x": 63, + "grid_y": 3, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y198": { + "bits": {}, + "grid_x": 63, + "grid_y": 2, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y199": { + "bits": {}, + "grid_x": 63, + "grid_y": 1, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y2": { + "bits": {}, + "grid_x": 63, + "grid_y": 205, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y20": { + "bits": {}, + "grid_x": 63, + "grid_y": 187, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y21": { + "bits": {}, + "grid_x": 63, + "grid_y": 186, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y22": { + "bits": {}, + "grid_x": 63, + "grid_y": 185, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y23": { + "bits": {}, + "grid_x": 63, + "grid_y": 184, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y24": { + "bits": {}, + "grid_x": 63, + "grid_y": 183, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y25": { + "bits": {}, + "grid_x": 63, + "grid_y": 181, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y26": { + "bits": {}, + "grid_x": 63, + "grid_y": 180, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y27": { + "bits": {}, + "grid_x": 63, + "grid_y": 179, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y28": { + "bits": {}, + "grid_x": 63, + "grid_y": 178, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y29": { + "bits": {}, + "grid_x": 63, + "grid_y": 177, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y3": { + "bits": {}, + "grid_x": 63, + "grid_y": 204, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y30": { + "bits": {}, + "grid_x": 63, + "grid_y": 176, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y31": { + "bits": {}, + "grid_x": 63, + "grid_y": 175, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y32": { + "bits": {}, + "grid_x": 63, + "grid_y": 174, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y33": { + "bits": {}, + "grid_x": 63, + "grid_y": 173, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y34": { + "bits": {}, + "grid_x": 63, + "grid_y": 172, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y35": { + "bits": {}, + "grid_x": 63, + "grid_y": 171, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y36": { + "bits": {}, + "grid_x": 63, + "grid_y": 170, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y37": { + "bits": {}, + "grid_x": 63, + "grid_y": 169, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y38": { + "bits": {}, + "grid_x": 63, + "grid_y": 168, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y39": { + "bits": {}, + "grid_x": 63, + "grid_y": 167, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y4": { + "bits": {}, + "grid_x": 63, + "grid_y": 203, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y40": { + "bits": {}, + "grid_x": 63, + "grid_y": 166, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y41": { + "bits": {}, + "grid_x": 63, + "grid_y": 165, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y42": { + "bits": {}, + "grid_x": 63, + "grid_y": 164, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y43": { + "bits": {}, + "grid_x": 63, + "grid_y": 163, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y44": { + "bits": {}, + "grid_x": 63, + "grid_y": 162, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y45": { + "bits": {}, + "grid_x": 63, + "grid_y": 161, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y46": { + "bits": {}, + "grid_x": 63, + "grid_y": 160, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y47": { + "bits": {}, + "grid_x": 63, + "grid_y": 159, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y48": { + "bits": {}, + "grid_x": 63, + "grid_y": 158, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y49": { + "bits": {}, + "grid_x": 63, + "grid_y": 157, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y5": { + "bits": {}, + "grid_x": 63, + "grid_y": 202, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y50": { + "bits": {}, + "grid_x": 63, + "grid_y": 155, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y51": { + "bits": {}, + "grid_x": 63, + "grid_y": 154, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y52": { + "bits": {}, + "grid_x": 63, + "grid_y": 153, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y53": { + "bits": {}, + "grid_x": 63, + "grid_y": 152, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y54": { + "bits": {}, + "grid_x": 63, + "grid_y": 151, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y55": { + "bits": {}, + "grid_x": 63, + "grid_y": 150, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y56": { + "bits": {}, + "grid_x": 63, + "grid_y": 149, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y57": { + "bits": {}, + "grid_x": 63, + "grid_y": 148, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y58": { + "bits": {}, + "grid_x": 63, + "grid_y": 147, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y59": { + "bits": {}, + "grid_x": 63, + "grid_y": 146, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y6": { + "bits": {}, + "grid_x": 63, + "grid_y": 201, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y60": { + "bits": {}, + "grid_x": 63, + "grid_y": 145, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y61": { + "bits": {}, + "grid_x": 63, + "grid_y": 144, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y62": { + "bits": {}, + "grid_x": 63, + "grid_y": 143, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y63": { + "bits": {}, + "grid_x": 63, + "grid_y": 142, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y64": { + "bits": {}, + "grid_x": 63, + "grid_y": 141, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y65": { + "bits": {}, + "grid_x": 63, + "grid_y": 140, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y66": { + "bits": {}, + "grid_x": 63, + "grid_y": 139, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y67": { + "bits": {}, + "grid_x": 63, + "grid_y": 138, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y68": { + "bits": {}, + "grid_x": 63, + "grid_y": 137, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y69": { + "bits": {}, + "grid_x": 63, + "grid_y": 136, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y7": { + "bits": {}, + "grid_x": 63, + "grid_y": 200, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y70": { + "bits": {}, + "grid_x": 63, + "grid_y": 135, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y71": { + "bits": {}, + "grid_x": 63, + "grid_y": 134, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y72": { + "bits": {}, + "grid_x": 63, + "grid_y": 133, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y73": { + "bits": {}, + "grid_x": 63, + "grid_y": 132, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y74": { + "bits": {}, + "grid_x": 63, + "grid_y": 131, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y75": { + "bits": {}, + "grid_x": 63, + "grid_y": 129, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y76": { + "bits": {}, + "grid_x": 63, + "grid_y": 128, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y77": { + "bits": {}, + "grid_x": 63, + "grid_y": 127, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y78": { + "bits": {}, + "grid_x": 63, + "grid_y": 126, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y79": { + "bits": {}, + "grid_x": 63, + "grid_y": 125, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y8": { + "bits": {}, + "grid_x": 63, + "grid_y": 199, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y80": { + "bits": {}, + "grid_x": 63, + "grid_y": 124, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y81": { + "bits": {}, + "grid_x": 63, + "grid_y": 123, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y82": { + "bits": {}, + "grid_x": 63, + "grid_y": 122, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y83": { + "bits": {}, + "grid_x": 63, + "grid_y": 121, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y84": { + "bits": {}, + "grid_x": 63, + "grid_y": 120, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y85": { + "bits": {}, + "grid_x": 63, + "grid_y": 119, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y86": { + "bits": {}, + "grid_x": 63, + "grid_y": 118, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y87": { + "bits": {}, + "grid_x": 63, + "grid_y": 117, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y88": { + "bits": {}, + "grid_x": 63, + "grid_y": 116, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y89": { + "bits": {}, + "grid_x": 63, + "grid_y": 115, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y9": { + "bits": {}, + "grid_x": 63, + "grid_y": 198, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y90": { + "bits": {}, + "grid_x": 63, + "grid_y": 114, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y91": { + "bits": {}, + "grid_x": 63, + "grid_y": 113, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y92": { + "bits": {}, + "grid_x": 63, + "grid_y": 112, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y93": { + "bits": {}, + "grid_x": 63, + "grid_y": 111, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y94": { + "bits": {}, + "grid_x": 63, + "grid_y": 110, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y95": { + "bits": {}, + "grid_x": 63, + "grid_y": 109, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y96": { + "bits": {}, + "grid_x": 63, + "grid_y": 108, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y97": { + "bits": {}, + "grid_x": 63, + "grid_y": 107, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y98": { + "bits": {}, + "grid_x": 63, + "grid_y": 106, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X24Y99": { + "bits": {}, + "grid_x": 63, + "grid_y": 105, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y0": { + "bits": {}, + "grid_x": 110, + "grid_y": 207, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y1": { + "bits": {}, + "grid_x": 110, + "grid_y": 206, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y10": { + "bits": {}, + "grid_x": 110, + "grid_y": 197, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y11": { + "bits": {}, + "grid_x": 110, + "grid_y": 196, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y12": { + "bits": {}, + "grid_x": 110, + "grid_y": 195, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y13": { + "bits": {}, + "grid_x": 110, + "grid_y": 194, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y14": { + "bits": {}, + "grid_x": 110, + "grid_y": 193, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y15": { + "bits": {}, + "grid_x": 110, + "grid_y": 192, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y16": { + "bits": {}, + "grid_x": 110, + "grid_y": 191, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y17": { + "bits": {}, + "grid_x": 110, + "grid_y": 190, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y18": { + "bits": {}, + "grid_x": 110, + "grid_y": 189, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y19": { + "bits": {}, + "grid_x": 110, + "grid_y": 188, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y2": { + "bits": {}, + "grid_x": 110, + "grid_y": 205, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y20": { + "bits": {}, + "grid_x": 110, + "grid_y": 187, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y21": { + "bits": {}, + "grid_x": 110, + "grid_y": 186, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y22": { + "bits": {}, + "grid_x": 110, + "grid_y": 185, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y23": { + "bits": {}, + "grid_x": 110, + "grid_y": 184, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y24": { + "bits": {}, + "grid_x": 110, + "grid_y": 183, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y25": { + "bits": {}, + "grid_x": 110, + "grid_y": 181, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y26": { + "bits": {}, + "grid_x": 110, + "grid_y": 180, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y27": { + "bits": {}, + "grid_x": 110, + "grid_y": 179, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y28": { + "bits": {}, + "grid_x": 110, + "grid_y": 178, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y29": { + "bits": {}, + "grid_x": 110, + "grid_y": 177, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y3": { + "bits": {}, + "grid_x": 110, + "grid_y": 204, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y30": { + "bits": {}, + "grid_x": 110, + "grid_y": 176, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y31": { + "bits": {}, + "grid_x": 110, + "grid_y": 175, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y32": { + "bits": {}, + "grid_x": 110, + "grid_y": 174, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y33": { + "bits": {}, + "grid_x": 110, + "grid_y": 173, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y34": { + "bits": {}, + "grid_x": 110, + "grid_y": 172, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y35": { + "bits": {}, + "grid_x": 110, + "grid_y": 171, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y36": { + "bits": {}, + "grid_x": 110, + "grid_y": 170, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y37": { + "bits": {}, + "grid_x": 110, + "grid_y": 169, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y38": { + "bits": {}, + "grid_x": 110, + "grid_y": 168, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y39": { + "bits": {}, + "grid_x": 110, + "grid_y": 167, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y4": { + "bits": {}, + "grid_x": 110, + "grid_y": 203, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y40": { + "bits": {}, + "grid_x": 110, + "grid_y": 166, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y41": { + "bits": {}, + "grid_x": 110, + "grid_y": 165, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y42": { + "bits": {}, + "grid_x": 110, + "grid_y": 164, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y43": { + "bits": {}, + "grid_x": 110, + "grid_y": 163, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y44": { + "bits": {}, + "grid_x": 110, + "grid_y": 162, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y45": { + "bits": {}, + "grid_x": 110, + "grid_y": 161, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y46": { + "bits": {}, + "grid_x": 110, + "grid_y": 160, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y47": { + "bits": {}, + "grid_x": 110, + "grid_y": 159, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y48": { + "bits": {}, + "grid_x": 110, + "grid_y": 158, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y49": { + "bits": {}, + "grid_x": 110, + "grid_y": 157, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y5": { + "bits": {}, + "grid_x": 110, + "grid_y": 202, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y50": { + "bits": {}, + "grid_x": 110, + "grid_y": 155, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y51": { + "bits": {}, + "grid_x": 110, + "grid_y": 154, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y52": { + "bits": {}, + "grid_x": 110, + "grid_y": 153, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y53": { + "bits": {}, + "grid_x": 110, + "grid_y": 152, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y54": { + "bits": {}, + "grid_x": 110, + "grid_y": 151, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y55": { + "bits": {}, + "grid_x": 110, + "grid_y": 150, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y56": { + "bits": {}, + "grid_x": 110, + "grid_y": 149, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y57": { + "bits": {}, + "grid_x": 110, + "grid_y": 148, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y58": { + "bits": {}, + "grid_x": 110, + "grid_y": 147, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y59": { + "bits": {}, + "grid_x": 110, + "grid_y": 146, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y6": { + "bits": {}, + "grid_x": 110, + "grid_y": 201, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y60": { + "bits": {}, + "grid_x": 110, + "grid_y": 145, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y61": { + "bits": {}, + "grid_x": 110, + "grid_y": 144, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y62": { + "bits": {}, + "grid_x": 110, + "grid_y": 143, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y63": { + "bits": {}, + "grid_x": 110, + "grid_y": 142, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y64": { + "bits": {}, + "grid_x": 110, + "grid_y": 141, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y65": { + "bits": {}, + "grid_x": 110, + "grid_y": 140, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y66": { + "bits": {}, + "grid_x": 110, + "grid_y": 139, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y67": { + "bits": {}, + "grid_x": 110, + "grid_y": 138, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y68": { + "bits": {}, + "grid_x": 110, + "grid_y": 137, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y69": { + "bits": {}, + "grid_x": 110, + "grid_y": 136, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y7": { + "bits": {}, + "grid_x": 110, + "grid_y": 200, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y70": { + "bits": {}, + "grid_x": 110, + "grid_y": 135, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y71": { + "bits": {}, + "grid_x": 110, + "grid_y": 134, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y72": { + "bits": {}, + "grid_x": 110, + "grid_y": 133, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y73": { + "bits": {}, + "grid_x": 110, + "grid_y": 132, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y74": { + "bits": {}, + "grid_x": 110, + "grid_y": 131, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y75": { + "bits": {}, + "grid_x": 110, + "grid_y": 129, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y76": { + "bits": {}, + "grid_x": 110, + "grid_y": 128, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y77": { + "bits": {}, + "grid_x": 110, + "grid_y": 127, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y78": { + "bits": {}, + "grid_x": 110, + "grid_y": 126, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y79": { + "bits": {}, + "grid_x": 110, + "grid_y": 125, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y8": { + "bits": {}, + "grid_x": 110, + "grid_y": 199, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y80": { + "bits": {}, + "grid_x": 110, + "grid_y": 124, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y81": { + "bits": {}, + "grid_x": 110, + "grid_y": 123, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y82": { + "bits": {}, + "grid_x": 110, + "grid_y": 122, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y83": { + "bits": {}, + "grid_x": 110, + "grid_y": 121, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y84": { + "bits": {}, + "grid_x": 110, + "grid_y": 120, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y85": { + "bits": {}, + "grid_x": 110, + "grid_y": 119, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y86": { + "bits": {}, + "grid_x": 110, + "grid_y": 118, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y87": { + "bits": {}, + "grid_x": 110, + "grid_y": 117, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y88": { + "bits": {}, + "grid_x": 110, + "grid_y": 116, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y89": { + "bits": {}, + "grid_x": 110, + "grid_y": 115, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y9": { + "bits": {}, + "grid_x": 110, + "grid_y": 198, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y90": { + "bits": {}, + "grid_x": 110, + "grid_y": 114, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y91": { + "bits": {}, + "grid_x": 110, + "grid_y": 113, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y92": { + "bits": {}, + "grid_x": 110, + "grid_y": 112, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y93": { + "bits": {}, + "grid_x": 110, + "grid_y": 111, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y94": { + "bits": {}, + "grid_x": 110, + "grid_y": 110, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y95": { + "bits": {}, + "grid_x": 110, + "grid_y": 109, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y96": { + "bits": {}, + "grid_x": 110, + "grid_y": 108, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y97": { + "bits": {}, + "grid_x": 110, + "grid_y": 107, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y98": { + "bits": {}, + "grid_x": 110, + "grid_y": 106, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_L_X42Y99": { + "bits": {}, + "grid_x": 110, + "grid_y": 105, + "sites": {}, + "type": "INT_INTERFACE_L" + }, + "INT_INTERFACE_R_X1Y0": { + "bits": {}, + "grid_x": 6, + "grid_y": 207, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y1": { + "bits": {}, + "grid_x": 6, + "grid_y": 206, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y10": { + "bits": {}, + "grid_x": 6, + "grid_y": 197, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y100": { + "bits": {}, + "grid_x": 6, + "grid_y": 103, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y101": { + "bits": {}, + "grid_x": 6, + "grid_y": 102, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y102": { + "bits": {}, + "grid_x": 6, + "grid_y": 101, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y103": { + "bits": {}, + "grid_x": 6, + "grid_y": 100, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y104": { + "bits": {}, + "grid_x": 6, + "grid_y": 99, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y105": { + "bits": {}, + "grid_x": 6, + "grid_y": 98, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y106": { + "bits": {}, + "grid_x": 6, + "grid_y": 97, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y107": { + "bits": {}, + "grid_x": 6, + "grid_y": 96, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y108": { + "bits": {}, + "grid_x": 6, + "grid_y": 95, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y109": { + "bits": {}, + "grid_x": 6, + "grid_y": 94, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y11": { + "bits": {}, + "grid_x": 6, + "grid_y": 196, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y110": { + "bits": {}, + "grid_x": 6, + "grid_y": 93, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y111": { + "bits": {}, + "grid_x": 6, + "grid_y": 92, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y112": { + "bits": {}, + "grid_x": 6, + "grid_y": 91, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y113": { + "bits": {}, + "grid_x": 6, + "grid_y": 90, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y114": { + "bits": {}, + "grid_x": 6, + "grid_y": 89, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y115": { + "bits": {}, + "grid_x": 6, + "grid_y": 88, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y116": { + "bits": {}, + "grid_x": 6, + "grid_y": 87, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y117": { + "bits": {}, + "grid_x": 6, + "grid_y": 86, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y118": { + "bits": {}, + "grid_x": 6, + "grid_y": 85, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y119": { + "bits": {}, + "grid_x": 6, + "grid_y": 84, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y12": { + "bits": {}, + "grid_x": 6, + "grid_y": 195, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y120": { + "bits": {}, + "grid_x": 6, + "grid_y": 83, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y121": { + "bits": {}, + "grid_x": 6, + "grid_y": 82, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y122": { + "bits": {}, + "grid_x": 6, + "grid_y": 81, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y123": { + "bits": {}, + "grid_x": 6, + "grid_y": 80, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y124": { + "bits": {}, + "grid_x": 6, + "grid_y": 79, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y125": { + "bits": {}, + "grid_x": 6, + "grid_y": 77, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y126": { + "bits": {}, + "grid_x": 6, + "grid_y": 76, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y127": { + "bits": {}, + "grid_x": 6, + "grid_y": 75, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y128": { + "bits": {}, + "grid_x": 6, + "grid_y": 74, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y129": { + "bits": {}, + "grid_x": 6, + "grid_y": 73, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y13": { + "bits": {}, + "grid_x": 6, + "grid_y": 194, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y130": { + "bits": {}, + "grid_x": 6, + "grid_y": 72, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y131": { + "bits": {}, + "grid_x": 6, + "grid_y": 71, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y132": { + "bits": {}, + "grid_x": 6, + "grid_y": 70, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y133": { + "bits": {}, + "grid_x": 6, + "grid_y": 69, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y134": { + "bits": {}, + "grid_x": 6, + "grid_y": 68, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y135": { + "bits": {}, + "grid_x": 6, + "grid_y": 67, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y136": { + "bits": {}, + "grid_x": 6, + "grid_y": 66, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y137": { + "bits": {}, + "grid_x": 6, + "grid_y": 65, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y138": { + "bits": {}, + "grid_x": 6, + "grid_y": 64, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y139": { + "bits": {}, + "grid_x": 6, + "grid_y": 63, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y14": { + "bits": {}, + "grid_x": 6, + "grid_y": 193, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y140": { + "bits": {}, + "grid_x": 6, + "grid_y": 62, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y141": { + "bits": {}, + "grid_x": 6, + "grid_y": 61, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y142": { + "bits": {}, + "grid_x": 6, + "grid_y": 60, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y143": { + "bits": {}, + "grid_x": 6, + "grid_y": 59, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y144": { + "bits": {}, + "grid_x": 6, + "grid_y": 58, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y145": { + "bits": {}, + "grid_x": 6, + "grid_y": 57, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y146": { + "bits": {}, + "grid_x": 6, + "grid_y": 56, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y147": { + "bits": {}, + "grid_x": 6, + "grid_y": 55, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y148": { + "bits": {}, + "grid_x": 6, + "grid_y": 54, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y149": { + "bits": {}, + "grid_x": 6, + "grid_y": 53, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y15": { + "bits": {}, + "grid_x": 6, + "grid_y": 192, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y150": { + "bits": {}, + "grid_x": 6, + "grid_y": 51, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y151": { + "bits": {}, + "grid_x": 6, + "grid_y": 50, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y152": { + "bits": {}, + "grid_x": 6, + "grid_y": 49, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y153": { + "bits": {}, + "grid_x": 6, + "grid_y": 48, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y154": { + "bits": {}, + "grid_x": 6, + "grid_y": 47, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y155": { + "bits": {}, + "grid_x": 6, + "grid_y": 46, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y156": { + "bits": {}, + "grid_x": 6, + "grid_y": 45, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y157": { + "bits": {}, + "grid_x": 6, + "grid_y": 44, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y158": { + "bits": {}, + "grid_x": 6, + "grid_y": 43, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y159": { + "bits": {}, + "grid_x": 6, + "grid_y": 42, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y16": { + "bits": {}, + "grid_x": 6, + "grid_y": 191, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y160": { + "bits": {}, + "grid_x": 6, + "grid_y": 41, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y161": { + "bits": {}, + "grid_x": 6, + "grid_y": 40, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y162": { + "bits": {}, + "grid_x": 6, + "grid_y": 39, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y163": { + "bits": {}, + "grid_x": 6, + "grid_y": 38, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y164": { + "bits": {}, + "grid_x": 6, + "grid_y": 37, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y165": { + "bits": {}, + "grid_x": 6, + "grid_y": 36, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y166": { + "bits": {}, + "grid_x": 6, + "grid_y": 35, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y167": { + "bits": {}, + "grid_x": 6, + "grid_y": 34, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y168": { + "bits": {}, + "grid_x": 6, + "grid_y": 33, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y169": { + "bits": {}, + "grid_x": 6, + "grid_y": 32, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y17": { + "bits": {}, + "grid_x": 6, + "grid_y": 190, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y170": { + "bits": {}, + "grid_x": 6, + "grid_y": 31, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y171": { + "bits": {}, + "grid_x": 6, + "grid_y": 30, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y172": { + "bits": {}, + "grid_x": 6, + "grid_y": 29, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y173": { + "bits": {}, + "grid_x": 6, + "grid_y": 28, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y174": { + "bits": {}, + "grid_x": 6, + "grid_y": 27, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y175": { + "bits": {}, + "grid_x": 6, + "grid_y": 25, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y176": { + "bits": {}, + "grid_x": 6, + "grid_y": 24, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y177": { + "bits": {}, + "grid_x": 6, + "grid_y": 23, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y178": { + "bits": {}, + "grid_x": 6, + "grid_y": 22, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y179": { + "bits": {}, + "grid_x": 6, + "grid_y": 21, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y18": { + "bits": {}, + "grid_x": 6, + "grid_y": 189, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y180": { + "bits": {}, + "grid_x": 6, + "grid_y": 20, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y181": { + "bits": {}, + "grid_x": 6, + "grid_y": 19, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y182": { + "bits": {}, + "grid_x": 6, + "grid_y": 18, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y183": { + "bits": {}, + "grid_x": 6, + "grid_y": 17, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y184": { + "bits": {}, + "grid_x": 6, + "grid_y": 16, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y185": { + "bits": {}, + "grid_x": 6, + "grid_y": 15, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y186": { + "bits": {}, + "grid_x": 6, + "grid_y": 14, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y187": { + "bits": {}, + "grid_x": 6, + "grid_y": 13, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y188": { + "bits": {}, + "grid_x": 6, + "grid_y": 12, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y189": { + "bits": {}, + "grid_x": 6, + "grid_y": 11, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y19": { + "bits": {}, + "grid_x": 6, + "grid_y": 188, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y190": { + "bits": {}, + "grid_x": 6, + "grid_y": 10, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y191": { + "bits": {}, + "grid_x": 6, + "grid_y": 9, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y192": { + "bits": {}, + "grid_x": 6, + "grid_y": 8, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y193": { + "bits": {}, + "grid_x": 6, + "grid_y": 7, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y194": { + "bits": {}, + "grid_x": 6, + "grid_y": 6, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y195": { + "bits": {}, + "grid_x": 6, + "grid_y": 5, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y196": { + "bits": {}, + "grid_x": 6, + "grid_y": 4, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y197": { + "bits": {}, + "grid_x": 6, + "grid_y": 3, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y198": { + "bits": {}, + "grid_x": 6, + "grid_y": 2, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y199": { + "bits": {}, + "grid_x": 6, + "grid_y": 1, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y2": { + "bits": {}, + "grid_x": 6, + "grid_y": 205, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y20": { + "bits": {}, + "grid_x": 6, + "grid_y": 187, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y21": { + "bits": {}, + "grid_x": 6, + "grid_y": 186, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y22": { + "bits": {}, + "grid_x": 6, + "grid_y": 185, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y23": { + "bits": {}, + "grid_x": 6, + "grid_y": 184, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y24": { + "bits": {}, + "grid_x": 6, + "grid_y": 183, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y25": { + "bits": {}, + "grid_x": 6, + "grid_y": 181, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y26": { + "bits": {}, + "grid_x": 6, + "grid_y": 180, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y27": { + "bits": {}, + "grid_x": 6, + "grid_y": 179, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y28": { + "bits": {}, + "grid_x": 6, + "grid_y": 178, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y29": { + "bits": {}, + "grid_x": 6, + "grid_y": 177, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y3": { + "bits": {}, + "grid_x": 6, + "grid_y": 204, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y30": { + "bits": {}, + "grid_x": 6, + "grid_y": 176, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y31": { + "bits": {}, + "grid_x": 6, + "grid_y": 175, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y32": { + "bits": {}, + "grid_x": 6, + "grid_y": 174, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y33": { + "bits": {}, + "grid_x": 6, + "grid_y": 173, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y34": { + "bits": {}, + "grid_x": 6, + "grid_y": 172, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y35": { + "bits": {}, + "grid_x": 6, + "grid_y": 171, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y36": { + "bits": {}, + "grid_x": 6, + "grid_y": 170, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y37": { + "bits": {}, + "grid_x": 6, + "grid_y": 169, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y38": { + "bits": {}, + "grid_x": 6, + "grid_y": 168, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y39": { + "bits": {}, + "grid_x": 6, + "grid_y": 167, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y4": { + "bits": {}, + "grid_x": 6, + "grid_y": 203, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y40": { + "bits": {}, + "grid_x": 6, + "grid_y": 166, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y41": { + "bits": {}, + "grid_x": 6, + "grid_y": 165, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y42": { + "bits": {}, + "grid_x": 6, + "grid_y": 164, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y43": { + "bits": {}, + "grid_x": 6, + "grid_y": 163, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y44": { + "bits": {}, + "grid_x": 6, + "grid_y": 162, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y45": { + "bits": {}, + "grid_x": 6, + "grid_y": 161, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y46": { + "bits": {}, + "grid_x": 6, + "grid_y": 160, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y47": { + "bits": {}, + "grid_x": 6, + "grid_y": 159, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y48": { + "bits": {}, + "grid_x": 6, + "grid_y": 158, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y49": { + "bits": {}, + "grid_x": 6, + "grid_y": 157, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y5": { + "bits": {}, + "grid_x": 6, + "grid_y": 202, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y50": { + "bits": {}, + "grid_x": 6, + "grid_y": 155, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y51": { + "bits": {}, + "grid_x": 6, + "grid_y": 154, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y52": { + "bits": {}, + "grid_x": 6, + "grid_y": 153, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y53": { + "bits": {}, + "grid_x": 6, + "grid_y": 152, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y54": { + "bits": {}, + "grid_x": 6, + "grid_y": 151, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y55": { + "bits": {}, + "grid_x": 6, + "grid_y": 150, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y56": { + "bits": {}, + "grid_x": 6, + "grid_y": 149, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y57": { + "bits": {}, + "grid_x": 6, + "grid_y": 148, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y58": { + "bits": {}, + "grid_x": 6, + "grid_y": 147, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y59": { + "bits": {}, + "grid_x": 6, + "grid_y": 146, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y6": { + "bits": {}, + "grid_x": 6, + "grid_y": 201, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y60": { + "bits": {}, + "grid_x": 6, + "grid_y": 145, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y61": { + "bits": {}, + "grid_x": 6, + "grid_y": 144, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y62": { + "bits": {}, + "grid_x": 6, + "grid_y": 143, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y63": { + "bits": {}, + "grid_x": 6, + "grid_y": 142, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y64": { + "bits": {}, + "grid_x": 6, + "grid_y": 141, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y65": { + "bits": {}, + "grid_x": 6, + "grid_y": 140, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y66": { + "bits": {}, + "grid_x": 6, + "grid_y": 139, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y67": { + "bits": {}, + "grid_x": 6, + "grid_y": 138, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y68": { + "bits": {}, + "grid_x": 6, + "grid_y": 137, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y69": { + "bits": {}, + "grid_x": 6, + "grid_y": 136, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y7": { + "bits": {}, + "grid_x": 6, + "grid_y": 200, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y70": { + "bits": {}, + "grid_x": 6, + "grid_y": 135, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y71": { + "bits": {}, + "grid_x": 6, + "grid_y": 134, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y72": { + "bits": {}, + "grid_x": 6, + "grid_y": 133, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y73": { + "bits": {}, + "grid_x": 6, + "grid_y": 132, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y74": { + "bits": {}, + "grid_x": 6, + "grid_y": 131, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y75": { + "bits": {}, + "grid_x": 6, + "grid_y": 129, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y76": { + "bits": {}, + "grid_x": 6, + "grid_y": 128, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y77": { + "bits": {}, + "grid_x": 6, + "grid_y": 127, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y78": { + "bits": {}, + "grid_x": 6, + "grid_y": 126, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y79": { + "bits": {}, + "grid_x": 6, + "grid_y": 125, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y8": { + "bits": {}, + "grid_x": 6, + "grid_y": 199, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y80": { + "bits": {}, + "grid_x": 6, + "grid_y": 124, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y81": { + "bits": {}, + "grid_x": 6, + "grid_y": 123, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y82": { + "bits": {}, + "grid_x": 6, + "grid_y": 122, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y83": { + "bits": {}, + "grid_x": 6, + "grid_y": 121, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y84": { + "bits": {}, + "grid_x": 6, + "grid_y": 120, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y85": { + "bits": {}, + "grid_x": 6, + "grid_y": 119, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y86": { + "bits": {}, + "grid_x": 6, + "grid_y": 118, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y87": { + "bits": {}, + "grid_x": 6, + "grid_y": 117, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y88": { + "bits": {}, + "grid_x": 6, + "grid_y": 116, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y89": { + "bits": {}, + "grid_x": 6, + "grid_y": 115, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y9": { + "bits": {}, + "grid_x": 6, + "grid_y": 198, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y90": { + "bits": {}, + "grid_x": 6, + "grid_y": 114, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y91": { + "bits": {}, + "grid_x": 6, + "grid_y": 113, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y92": { + "bits": {}, + "grid_x": 6, + "grid_y": 112, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y93": { + "bits": {}, + "grid_x": 6, + "grid_y": 111, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y94": { + "bits": {}, + "grid_x": 6, + "grid_y": 110, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y95": { + "bits": {}, + "grid_x": 6, + "grid_y": 109, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y96": { + "bits": {}, + "grid_x": 6, + "grid_y": 108, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y97": { + "bits": {}, + "grid_x": 6, + "grid_y": 107, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y98": { + "bits": {}, + "grid_x": 6, + "grid_y": 106, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X1Y99": { + "bits": {}, + "grid_x": 6, + "grid_y": 105, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y0": { + "bits": {}, + "grid_x": 66, + "grid_y": 207, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y1": { + "bits": {}, + "grid_x": 66, + "grid_y": 206, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y10": { + "bits": {}, + "grid_x": 66, + "grid_y": 197, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y100": { + "bits": {}, + "grid_x": 66, + "grid_y": 103, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y101": { + "bits": {}, + "grid_x": 66, + "grid_y": 102, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y102": { + "bits": {}, + "grid_x": 66, + "grid_y": 101, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y103": { + "bits": {}, + "grid_x": 66, + "grid_y": 100, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y104": { + "bits": {}, + "grid_x": 66, + "grid_y": 99, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y105": { + "bits": {}, + "grid_x": 66, + "grid_y": 98, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y106": { + "bits": {}, + "grid_x": 66, + "grid_y": 97, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y107": { + "bits": {}, + "grid_x": 66, + "grid_y": 96, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y108": { + "bits": {}, + "grid_x": 66, + "grid_y": 95, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y109": { + "bits": {}, + "grid_x": 66, + "grid_y": 94, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y11": { + "bits": {}, + "grid_x": 66, + "grid_y": 196, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y110": { + "bits": {}, + "grid_x": 66, + "grid_y": 93, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y111": { + "bits": {}, + "grid_x": 66, + "grid_y": 92, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y112": { + "bits": {}, + "grid_x": 66, + "grid_y": 91, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y113": { + "bits": {}, + "grid_x": 66, + "grid_y": 90, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y114": { + "bits": {}, + "grid_x": 66, + "grid_y": 89, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y115": { + "bits": {}, + "grid_x": 66, + "grid_y": 88, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y116": { + "bits": {}, + "grid_x": 66, + "grid_y": 87, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y117": { + "bits": {}, + "grid_x": 66, + "grid_y": 86, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y118": { + "bits": {}, + "grid_x": 66, + "grid_y": 85, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y119": { + "bits": {}, + "grid_x": 66, + "grid_y": 84, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y12": { + "bits": {}, + "grid_x": 66, + "grid_y": 195, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y120": { + "bits": {}, + "grid_x": 66, + "grid_y": 83, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y121": { + "bits": {}, + "grid_x": 66, + "grid_y": 82, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y122": { + "bits": {}, + "grid_x": 66, + "grid_y": 81, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y123": { + "bits": {}, + "grid_x": 66, + "grid_y": 80, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y124": { + "bits": {}, + "grid_x": 66, + "grid_y": 79, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y125": { + "bits": {}, + "grid_x": 66, + "grid_y": 77, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y126": { + "bits": {}, + "grid_x": 66, + "grid_y": 76, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y127": { + "bits": {}, + "grid_x": 66, + "grid_y": 75, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y128": { + "bits": {}, + "grid_x": 66, + "grid_y": 74, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y129": { + "bits": {}, + "grid_x": 66, + "grid_y": 73, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y13": { + "bits": {}, + "grid_x": 66, + "grid_y": 194, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y130": { + "bits": {}, + "grid_x": 66, + "grid_y": 72, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y131": { + "bits": {}, + "grid_x": 66, + "grid_y": 71, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y132": { + "bits": {}, + "grid_x": 66, + "grid_y": 70, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y133": { + "bits": {}, + "grid_x": 66, + "grid_y": 69, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y134": { + "bits": {}, + "grid_x": 66, + "grid_y": 68, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y135": { + "bits": {}, + "grid_x": 66, + "grid_y": 67, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y136": { + "bits": {}, + "grid_x": 66, + "grid_y": 66, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y137": { + "bits": {}, + "grid_x": 66, + "grid_y": 65, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y138": { + "bits": {}, + "grid_x": 66, + "grid_y": 64, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y139": { + "bits": {}, + "grid_x": 66, + "grid_y": 63, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y14": { + "bits": {}, + "grid_x": 66, + "grid_y": 193, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y140": { + "bits": {}, + "grid_x": 66, + "grid_y": 62, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y141": { + "bits": {}, + "grid_x": 66, + "grid_y": 61, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y142": { + "bits": {}, + "grid_x": 66, + "grid_y": 60, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y143": { + "bits": {}, + "grid_x": 66, + "grid_y": 59, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y144": { + "bits": {}, + "grid_x": 66, + "grid_y": 58, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y145": { + "bits": {}, + "grid_x": 66, + "grid_y": 57, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y146": { + "bits": {}, + "grid_x": 66, + "grid_y": 56, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y147": { + "bits": {}, + "grid_x": 66, + "grid_y": 55, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y148": { + "bits": {}, + "grid_x": 66, + "grid_y": 54, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y149": { + "bits": {}, + "grid_x": 66, + "grid_y": 53, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y15": { + "bits": {}, + "grid_x": 66, + "grid_y": 192, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y150": { + "bits": {}, + "grid_x": 66, + "grid_y": 51, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y151": { + "bits": {}, + "grid_x": 66, + "grid_y": 50, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y152": { + "bits": {}, + "grid_x": 66, + "grid_y": 49, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y153": { + "bits": {}, + "grid_x": 66, + "grid_y": 48, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y154": { + "bits": {}, + "grid_x": 66, + "grid_y": 47, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y155": { + "bits": {}, + "grid_x": 66, + "grid_y": 46, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y156": { + "bits": {}, + "grid_x": 66, + "grid_y": 45, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y157": { + "bits": {}, + "grid_x": 66, + "grid_y": 44, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y158": { + "bits": {}, + "grid_x": 66, + "grid_y": 43, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y159": { + "bits": {}, + "grid_x": 66, + "grid_y": 42, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y16": { + "bits": {}, + "grid_x": 66, + "grid_y": 191, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y160": { + "bits": {}, + "grid_x": 66, + "grid_y": 41, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y161": { + "bits": {}, + "grid_x": 66, + "grid_y": 40, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y162": { + "bits": {}, + "grid_x": 66, + "grid_y": 39, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y163": { + "bits": {}, + "grid_x": 66, + "grid_y": 38, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y164": { + "bits": {}, + "grid_x": 66, + "grid_y": 37, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y165": { + "bits": {}, + "grid_x": 66, + "grid_y": 36, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y166": { + "bits": {}, + "grid_x": 66, + "grid_y": 35, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y167": { + "bits": {}, + "grid_x": 66, + "grid_y": 34, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y168": { + "bits": {}, + "grid_x": 66, + "grid_y": 33, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y169": { + "bits": {}, + "grid_x": 66, + "grid_y": 32, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y17": { + "bits": {}, + "grid_x": 66, + "grid_y": 190, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y170": { + "bits": {}, + "grid_x": 66, + "grid_y": 31, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y171": { + "bits": {}, + "grid_x": 66, + "grid_y": 30, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y172": { + "bits": {}, + "grid_x": 66, + "grid_y": 29, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y173": { + "bits": {}, + "grid_x": 66, + "grid_y": 28, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y174": { + "bits": {}, + "grid_x": 66, + "grid_y": 27, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y175": { + "bits": {}, + "grid_x": 66, + "grid_y": 25, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y176": { + "bits": {}, + "grid_x": 66, + "grid_y": 24, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y177": { + "bits": {}, + "grid_x": 66, + "grid_y": 23, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y178": { + "bits": {}, + "grid_x": 66, + "grid_y": 22, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y179": { + "bits": {}, + "grid_x": 66, + "grid_y": 21, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y18": { + "bits": {}, + "grid_x": 66, + "grid_y": 189, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y180": { + "bits": {}, + "grid_x": 66, + "grid_y": 20, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y181": { + "bits": {}, + "grid_x": 66, + "grid_y": 19, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y182": { + "bits": {}, + "grid_x": 66, + "grid_y": 18, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y183": { + "bits": {}, + "grid_x": 66, + "grid_y": 17, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y184": { + "bits": {}, + "grid_x": 66, + "grid_y": 16, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y185": { + "bits": {}, + "grid_x": 66, + "grid_y": 15, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y186": { + "bits": {}, + "grid_x": 66, + "grid_y": 14, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y187": { + "bits": {}, + "grid_x": 66, + "grid_y": 13, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y188": { + "bits": {}, + "grid_x": 66, + "grid_y": 12, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y189": { + "bits": {}, + "grid_x": 66, + "grid_y": 11, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y19": { + "bits": {}, + "grid_x": 66, + "grid_y": 188, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y190": { + "bits": {}, + "grid_x": 66, + "grid_y": 10, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y191": { + "bits": {}, + "grid_x": 66, + "grid_y": 9, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y192": { + "bits": {}, + "grid_x": 66, + "grid_y": 8, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y193": { + "bits": {}, + "grid_x": 66, + "grid_y": 7, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y194": { + "bits": {}, + "grid_x": 66, + "grid_y": 6, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y195": { + "bits": {}, + "grid_x": 66, + "grid_y": 5, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y196": { + "bits": {}, + "grid_x": 66, + "grid_y": 4, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y197": { + "bits": {}, + "grid_x": 66, + "grid_y": 3, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y198": { + "bits": {}, + "grid_x": 66, + "grid_y": 2, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y199": { + "bits": {}, + "grid_x": 66, + "grid_y": 1, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y2": { + "bits": {}, + "grid_x": 66, + "grid_y": 205, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y20": { + "bits": {}, + "grid_x": 66, + "grid_y": 187, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y21": { + "bits": {}, + "grid_x": 66, + "grid_y": 186, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y22": { + "bits": {}, + "grid_x": 66, + "grid_y": 185, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y23": { + "bits": {}, + "grid_x": 66, + "grid_y": 184, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y24": { + "bits": {}, + "grid_x": 66, + "grid_y": 183, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y25": { + "bits": {}, + "grid_x": 66, + "grid_y": 181, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y26": { + "bits": {}, + "grid_x": 66, + "grid_y": 180, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y27": { + "bits": {}, + "grid_x": 66, + "grid_y": 179, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y28": { + "bits": {}, + "grid_x": 66, + "grid_y": 178, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y29": { + "bits": {}, + "grid_x": 66, + "grid_y": 177, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y3": { + "bits": {}, + "grid_x": 66, + "grid_y": 204, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y30": { + "bits": {}, + "grid_x": 66, + "grid_y": 176, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y31": { + "bits": {}, + "grid_x": 66, + "grid_y": 175, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y32": { + "bits": {}, + "grid_x": 66, + "grid_y": 174, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y33": { + "bits": {}, + "grid_x": 66, + "grid_y": 173, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y34": { + "bits": {}, + "grid_x": 66, + "grid_y": 172, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y35": { + "bits": {}, + "grid_x": 66, + "grid_y": 171, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y36": { + "bits": {}, + "grid_x": 66, + "grid_y": 170, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y37": { + "bits": {}, + "grid_x": 66, + "grid_y": 169, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y38": { + "bits": {}, + "grid_x": 66, + "grid_y": 168, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y39": { + "bits": {}, + "grid_x": 66, + "grid_y": 167, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y4": { + "bits": {}, + "grid_x": 66, + "grid_y": 203, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y40": { + "bits": {}, + "grid_x": 66, + "grid_y": 166, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y41": { + "bits": {}, + "grid_x": 66, + "grid_y": 165, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y42": { + "bits": {}, + "grid_x": 66, + "grid_y": 164, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y43": { + "bits": {}, + "grid_x": 66, + "grid_y": 163, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y44": { + "bits": {}, + "grid_x": 66, + "grid_y": 162, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y45": { + "bits": {}, + "grid_x": 66, + "grid_y": 161, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y46": { + "bits": {}, + "grid_x": 66, + "grid_y": 160, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y47": { + "bits": {}, + "grid_x": 66, + "grid_y": 159, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y48": { + "bits": {}, + "grid_x": 66, + "grid_y": 158, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y49": { + "bits": {}, + "grid_x": 66, + "grid_y": 157, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y5": { + "bits": {}, + "grid_x": 66, + "grid_y": 202, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y50": { + "bits": {}, + "grid_x": 66, + "grid_y": 155, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y51": { + "bits": {}, + "grid_x": 66, + "grid_y": 154, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y52": { + "bits": {}, + "grid_x": 66, + "grid_y": 153, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y53": { + "bits": {}, + "grid_x": 66, + "grid_y": 152, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y54": { + "bits": {}, + "grid_x": 66, + "grid_y": 151, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y55": { + "bits": {}, + "grid_x": 66, + "grid_y": 150, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y56": { + "bits": {}, + "grid_x": 66, + "grid_y": 149, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y57": { + "bits": {}, + "grid_x": 66, + "grid_y": 148, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y58": { + "bits": {}, + "grid_x": 66, + "grid_y": 147, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y59": { + "bits": {}, + "grid_x": 66, + "grid_y": 146, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y6": { + "bits": {}, + "grid_x": 66, + "grid_y": 201, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y60": { + "bits": {}, + "grid_x": 66, + "grid_y": 145, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y61": { + "bits": {}, + "grid_x": 66, + "grid_y": 144, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y62": { + "bits": {}, + "grid_x": 66, + "grid_y": 143, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y63": { + "bits": {}, + "grid_x": 66, + "grid_y": 142, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y64": { + "bits": {}, + "grid_x": 66, + "grid_y": 141, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y65": { + "bits": {}, + "grid_x": 66, + "grid_y": 140, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y66": { + "bits": {}, + "grid_x": 66, + "grid_y": 139, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y67": { + "bits": {}, + "grid_x": 66, + "grid_y": 138, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y68": { + "bits": {}, + "grid_x": 66, + "grid_y": 137, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y69": { + "bits": {}, + "grid_x": 66, + "grid_y": 136, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y7": { + "bits": {}, + "grid_x": 66, + "grid_y": 200, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y70": { + "bits": {}, + "grid_x": 66, + "grid_y": 135, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y71": { + "bits": {}, + "grid_x": 66, + "grid_y": 134, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y72": { + "bits": {}, + "grid_x": 66, + "grid_y": 133, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y73": { + "bits": {}, + "grid_x": 66, + "grid_y": 132, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y74": { + "bits": {}, + "grid_x": 66, + "grid_y": 131, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y75": { + "bits": {}, + "grid_x": 66, + "grid_y": 129, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y76": { + "bits": {}, + "grid_x": 66, + "grid_y": 128, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y77": { + "bits": {}, + "grid_x": 66, + "grid_y": 127, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y78": { + "bits": {}, + "grid_x": 66, + "grid_y": 126, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y79": { + "bits": {}, + "grid_x": 66, + "grid_y": 125, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y8": { + "bits": {}, + "grid_x": 66, + "grid_y": 199, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y80": { + "bits": {}, + "grid_x": 66, + "grid_y": 124, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y81": { + "bits": {}, + "grid_x": 66, + "grid_y": 123, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y82": { + "bits": {}, + "grid_x": 66, + "grid_y": 122, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y83": { + "bits": {}, + "grid_x": 66, + "grid_y": 121, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y84": { + "bits": {}, + "grid_x": 66, + "grid_y": 120, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y85": { + "bits": {}, + "grid_x": 66, + "grid_y": 119, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y86": { + "bits": {}, + "grid_x": 66, + "grid_y": 118, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y87": { + "bits": {}, + "grid_x": 66, + "grid_y": 117, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y88": { + "bits": {}, + "grid_x": 66, + "grid_y": 116, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y89": { + "bits": {}, + "grid_x": 66, + "grid_y": 115, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y9": { + "bits": {}, + "grid_x": 66, + "grid_y": 198, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y90": { + "bits": {}, + "grid_x": 66, + "grid_y": 114, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y91": { + "bits": {}, + "grid_x": 66, + "grid_y": 113, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y92": { + "bits": {}, + "grid_x": 66, + "grid_y": 112, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y93": { + "bits": {}, + "grid_x": 66, + "grid_y": 111, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y94": { + "bits": {}, + "grid_x": 66, + "grid_y": 110, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y95": { + "bits": {}, + "grid_x": 66, + "grid_y": 109, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y96": { + "bits": {}, + "grid_x": 66, + "grid_y": 108, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y97": { + "bits": {}, + "grid_x": 66, + "grid_y": 107, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y98": { + "bits": {}, + "grid_x": 66, + "grid_y": 106, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X25Y99": { + "bits": {}, + "grid_x": 66, + "grid_y": 105, + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y0": { + "bits": {}, + "grid_x": 86, + "grid_y": 207, + "segment": "SEG_DSP0_R_X33Y0", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y1": { + "bits": {}, + "grid_x": 86, + "grid_y": 206, + "segment": "SEG_DSP1_R_X33Y0", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y10": { + "bits": {}, + "grid_x": 86, + "grid_y": 197, + "segment": "SEG_DSP0_R_X33Y10", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y100": { + "bits": {}, + "grid_x": 86, + "grid_y": 103, + "segment": "SEG_DSP0_R_X33Y100", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y101": { + "bits": {}, + "grid_x": 86, + "grid_y": 102, + "segment": "SEG_DSP1_R_X33Y100", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y102": { + "bits": {}, + "grid_x": 86, + "grid_y": 101, + "segment": "SEG_DSP2_R_X33Y100", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y103": { + "bits": {}, + "grid_x": 86, + "grid_y": 100, + "segment": "SEG_DSP3_R_X33Y100", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y104": { + "bits": {}, + "grid_x": 86, + "grid_y": 99, + "segment": "SEG_DSP4_R_X33Y100", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y105": { + "bits": {}, + "grid_x": 86, + "grid_y": 98, + "segment": "SEG_DSP0_R_X33Y105", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y106": { + "bits": {}, + "grid_x": 86, + "grid_y": 97, + "segment": "SEG_DSP1_R_X33Y105", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y107": { + "bits": {}, + "grid_x": 86, + "grid_y": 96, + "segment": "SEG_DSP2_R_X33Y105", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y108": { + "bits": {}, + "grid_x": 86, + "grid_y": 95, + "segment": "SEG_DSP3_R_X33Y105", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y109": { + "bits": {}, + "grid_x": 86, + "grid_y": 94, + "segment": "SEG_DSP4_R_X33Y105", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y11": { + "bits": {}, + "grid_x": 86, + "grid_y": 196, + "segment": "SEG_DSP1_R_X33Y10", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y110": { + "bits": {}, + "grid_x": 86, + "grid_y": 93, + "segment": "SEG_DSP0_R_X33Y110", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y111": { + "bits": {}, + "grid_x": 86, + "grid_y": 92, + "segment": "SEG_DSP1_R_X33Y110", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y112": { + "bits": {}, + "grid_x": 86, + "grid_y": 91, + "segment": "SEG_DSP2_R_X33Y110", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y113": { + "bits": {}, + "grid_x": 86, + "grid_y": 90, + "segment": "SEG_DSP3_R_X33Y110", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y114": { + "bits": {}, + "grid_x": 86, + "grid_y": 89, + "segment": "SEG_DSP4_R_X33Y110", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y115": { + "bits": {}, + "grid_x": 86, + "grid_y": 88, + "segment": "SEG_DSP0_R_X33Y115", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y116": { + "bits": {}, + "grid_x": 86, + "grid_y": 87, + "segment": "SEG_DSP1_R_X33Y115", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y117": { + "bits": {}, + "grid_x": 86, + "grid_y": 86, + "segment": "SEG_DSP2_R_X33Y115", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y118": { + "bits": {}, + "grid_x": 86, + "grid_y": 85, + "segment": "SEG_DSP3_R_X33Y115", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y119": { + "bits": {}, + "grid_x": 86, + "grid_y": 84, + "segment": "SEG_DSP4_R_X33Y115", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y12": { + "bits": {}, + "grid_x": 86, + "grid_y": 195, + "segment": "SEG_DSP2_R_X33Y10", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y120": { + "bits": {}, + "grid_x": 86, + "grid_y": 83, + "segment": "SEG_DSP0_R_X33Y120", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y121": { + "bits": {}, + "grid_x": 86, + "grid_y": 82, + "segment": "SEG_DSP1_R_X33Y120", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y122": { + "bits": {}, + "grid_x": 86, + "grid_y": 81, + "segment": "SEG_DSP2_R_X33Y120", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y123": { + "bits": {}, + "grid_x": 86, + "grid_y": 80, + "segment": "SEG_DSP3_R_X33Y120", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y124": { + "bits": {}, + "grid_x": 86, + "grid_y": 79, + "segment": "SEG_DSP4_R_X33Y120", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y125": { + "bits": {}, + "grid_x": 86, + "grid_y": 77, + "segment": "SEG_DSP0_R_X33Y125", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y126": { + "bits": {}, + "grid_x": 86, + "grid_y": 76, + "segment": "SEG_DSP1_R_X33Y125", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y127": { + "bits": {}, + "grid_x": 86, + "grid_y": 75, + "segment": "SEG_DSP2_R_X33Y125", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y128": { + "bits": {}, + "grid_x": 86, + "grid_y": 74, + "segment": "SEG_DSP3_R_X33Y125", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y129": { + "bits": {}, + "grid_x": 86, + "grid_y": 73, + "segment": "SEG_DSP4_R_X33Y125", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y13": { + "bits": {}, + "grid_x": 86, + "grid_y": 194, + "segment": "SEG_DSP3_R_X33Y10", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y130": { + "bits": {}, + "grid_x": 86, + "grid_y": 72, + "segment": "SEG_DSP0_R_X33Y130", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y131": { + "bits": {}, + "grid_x": 86, + "grid_y": 71, + "segment": "SEG_DSP1_R_X33Y130", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y132": { + "bits": {}, + "grid_x": 86, + "grid_y": 70, + "segment": "SEG_DSP2_R_X33Y130", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y133": { + "bits": {}, + "grid_x": 86, + "grid_y": 69, + "segment": "SEG_DSP3_R_X33Y130", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y134": { + "bits": {}, + "grid_x": 86, + "grid_y": 68, + "segment": "SEG_DSP4_R_X33Y130", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y135": { + "bits": {}, + "grid_x": 86, + "grid_y": 67, + "segment": "SEG_DSP0_R_X33Y135", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y136": { + "bits": {}, + "grid_x": 86, + "grid_y": 66, + "segment": "SEG_DSP1_R_X33Y135", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y137": { + "bits": {}, + "grid_x": 86, + "grid_y": 65, + "segment": "SEG_DSP2_R_X33Y135", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y138": { + "bits": {}, + "grid_x": 86, + "grid_y": 64, + "segment": "SEG_DSP3_R_X33Y135", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y139": { + "bits": {}, + "grid_x": 86, + "grid_y": 63, + "segment": "SEG_DSP4_R_X33Y135", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y14": { + "bits": {}, + "grid_x": 86, + "grid_y": 193, + "segment": "SEG_DSP4_R_X33Y10", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y140": { + "bits": {}, + "grid_x": 86, + "grid_y": 62, + "segment": "SEG_DSP0_R_X33Y140", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y141": { + "bits": {}, + "grid_x": 86, + "grid_y": 61, + "segment": "SEG_DSP1_R_X33Y140", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y142": { + "bits": {}, + "grid_x": 86, + "grid_y": 60, + "segment": "SEG_DSP2_R_X33Y140", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y143": { + "bits": {}, + "grid_x": 86, + "grid_y": 59, + "segment": "SEG_DSP3_R_X33Y140", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y144": { + "bits": {}, + "grid_x": 86, + "grid_y": 58, + "segment": "SEG_DSP4_R_X33Y140", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y145": { + "bits": {}, + "grid_x": 86, + "grid_y": 57, + "segment": "SEG_DSP0_R_X33Y145", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y146": { + "bits": {}, + "grid_x": 86, + "grid_y": 56, + "segment": "SEG_DSP1_R_X33Y145", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y147": { + "bits": {}, + "grid_x": 86, + "grid_y": 55, + "segment": "SEG_DSP2_R_X33Y145", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y148": { + "bits": {}, + "grid_x": 86, + "grid_y": 54, + "segment": "SEG_DSP3_R_X33Y145", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y149": { + "bits": {}, + "grid_x": 86, + "grid_y": 53, + "segment": "SEG_DSP4_R_X33Y145", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y15": { + "bits": {}, + "grid_x": 86, + "grid_y": 192, + "segment": "SEG_DSP0_R_X33Y15", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y150": { + "bits": {}, + "grid_x": 86, + "grid_y": 51, + "segment": "SEG_DSP0_R_X33Y150", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y151": { + "bits": {}, + "grid_x": 86, + "grid_y": 50, + "segment": "SEG_DSP1_R_X33Y150", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y152": { + "bits": {}, + "grid_x": 86, + "grid_y": 49, + "segment": "SEG_DSP2_R_X33Y150", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y153": { + "bits": {}, + "grid_x": 86, + "grid_y": 48, + "segment": "SEG_DSP3_R_X33Y150", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y154": { + "bits": {}, + "grid_x": 86, + "grid_y": 47, + "segment": "SEG_DSP4_R_X33Y150", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y155": { + "bits": {}, + "grid_x": 86, + "grid_y": 46, + "segment": "SEG_DSP0_R_X33Y155", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y156": { + "bits": {}, + "grid_x": 86, + "grid_y": 45, + "segment": "SEG_DSP1_R_X33Y155", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y157": { + "bits": {}, + "grid_x": 86, + "grid_y": 44, + "segment": "SEG_DSP2_R_X33Y155", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y158": { + "bits": {}, + "grid_x": 86, + "grid_y": 43, + "segment": "SEG_DSP3_R_X33Y155", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y159": { + "bits": {}, + "grid_x": 86, + "grid_y": 42, + "segment": "SEG_DSP4_R_X33Y155", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y16": { + "bits": {}, + "grid_x": 86, + "grid_y": 191, + "segment": "SEG_DSP1_R_X33Y15", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y160": { + "bits": {}, + "grid_x": 86, + "grid_y": 41, + "segment": "SEG_DSP0_R_X33Y160", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y161": { + "bits": {}, + "grid_x": 86, + "grid_y": 40, + "segment": "SEG_DSP1_R_X33Y160", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y162": { + "bits": {}, + "grid_x": 86, + "grid_y": 39, + "segment": "SEG_DSP2_R_X33Y160", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y163": { + "bits": {}, + "grid_x": 86, + "grid_y": 38, + "segment": "SEG_DSP3_R_X33Y160", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y164": { + "bits": {}, + "grid_x": 86, + "grid_y": 37, + "segment": "SEG_DSP4_R_X33Y160", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y165": { + "bits": {}, + "grid_x": 86, + "grid_y": 36, + "segment": "SEG_DSP0_R_X33Y165", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y166": { + "bits": {}, + "grid_x": 86, + "grid_y": 35, + "segment": "SEG_DSP1_R_X33Y165", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y167": { + "bits": {}, + "grid_x": 86, + "grid_y": 34, + "segment": "SEG_DSP2_R_X33Y165", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y168": { + "bits": {}, + "grid_x": 86, + "grid_y": 33, + "segment": "SEG_DSP3_R_X33Y165", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y169": { + "bits": {}, + "grid_x": 86, + "grid_y": 32, + "segment": "SEG_DSP4_R_X33Y165", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y17": { + "bits": {}, + "grid_x": 86, + "grid_y": 190, + "segment": "SEG_DSP2_R_X33Y15", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y170": { + "bits": {}, + "grid_x": 86, + "grid_y": 31, + "segment": "SEG_DSP0_R_X33Y170", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y171": { + "bits": {}, + "grid_x": 86, + "grid_y": 30, + "segment": "SEG_DSP1_R_X33Y170", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y172": { + "bits": {}, + "grid_x": 86, + "grid_y": 29, + "segment": "SEG_DSP2_R_X33Y170", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y173": { + "bits": {}, + "grid_x": 86, + "grid_y": 28, + "segment": "SEG_DSP3_R_X33Y170", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y174": { + "bits": {}, + "grid_x": 86, + "grid_y": 27, + "segment": "SEG_DSP4_R_X33Y170", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y175": { + "bits": {}, + "grid_x": 86, + "grid_y": 25, + "segment": "SEG_DSP0_R_X33Y175", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y176": { + "bits": {}, + "grid_x": 86, + "grid_y": 24, + "segment": "SEG_DSP1_R_X33Y175", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y177": { + "bits": {}, + "grid_x": 86, + "grid_y": 23, + "segment": "SEG_DSP2_R_X33Y175", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y178": { + "bits": {}, + "grid_x": 86, + "grid_y": 22, + "segment": "SEG_DSP3_R_X33Y175", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y179": { + "bits": {}, + "grid_x": 86, + "grid_y": 21, + "segment": "SEG_DSP4_R_X33Y175", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y18": { + "bits": {}, + "grid_x": 86, + "grid_y": 189, + "segment": "SEG_DSP3_R_X33Y15", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y180": { + "bits": {}, + "grid_x": 86, + "grid_y": 20, + "segment": "SEG_DSP0_R_X33Y180", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y181": { + "bits": {}, + "grid_x": 86, + "grid_y": 19, + "segment": "SEG_DSP1_R_X33Y180", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y182": { + "bits": {}, + "grid_x": 86, + "grid_y": 18, + "segment": "SEG_DSP2_R_X33Y180", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y183": { + "bits": {}, + "grid_x": 86, + "grid_y": 17, + "segment": "SEG_DSP3_R_X33Y180", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y184": { + "bits": {}, + "grid_x": 86, + "grid_y": 16, + "segment": "SEG_DSP4_R_X33Y180", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y185": { + "bits": {}, + "grid_x": 86, + "grid_y": 15, + "segment": "SEG_DSP0_R_X33Y185", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y186": { + "bits": {}, + "grid_x": 86, + "grid_y": 14, + "segment": "SEG_DSP1_R_X33Y185", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y187": { + "bits": {}, + "grid_x": 86, + "grid_y": 13, + "segment": "SEG_DSP2_R_X33Y185", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y188": { + "bits": {}, + "grid_x": 86, + "grid_y": 12, + "segment": "SEG_DSP3_R_X33Y185", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y189": { + "bits": {}, + "grid_x": 86, + "grid_y": 11, + "segment": "SEG_DSP4_R_X33Y185", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y19": { + "bits": {}, + "grid_x": 86, + "grid_y": 188, + "segment": "SEG_DSP4_R_X33Y15", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y190": { + "bits": {}, + "grid_x": 86, + "grid_y": 10, + "segment": "SEG_DSP0_R_X33Y190", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y191": { + "bits": {}, + "grid_x": 86, + "grid_y": 9, + "segment": "SEG_DSP1_R_X33Y190", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y192": { + "bits": {}, + "grid_x": 86, + "grid_y": 8, + "segment": "SEG_DSP2_R_X33Y190", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y193": { + "bits": {}, + "grid_x": 86, + "grid_y": 7, + "segment": "SEG_DSP3_R_X33Y190", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y194": { + "bits": {}, + "grid_x": 86, + "grid_y": 6, + "segment": "SEG_DSP4_R_X33Y190", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y195": { + "bits": {}, + "grid_x": 86, + "grid_y": 5, + "segment": "SEG_DSP0_R_X33Y195", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y196": { + "bits": {}, + "grid_x": 86, + "grid_y": 4, + "segment": "SEG_DSP1_R_X33Y195", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y197": { + "bits": {}, + "grid_x": 86, + "grid_y": 3, + "segment": "SEG_DSP2_R_X33Y195", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y198": { + "bits": {}, + "grid_x": 86, + "grid_y": 2, + "segment": "SEG_DSP3_R_X33Y195", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y199": { + "bits": {}, + "grid_x": 86, + "grid_y": 1, + "segment": "SEG_DSP4_R_X33Y195", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y2": { + "bits": {}, + "grid_x": 86, + "grid_y": 205, + "segment": "SEG_DSP2_R_X33Y0", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y20": { + "bits": {}, + "grid_x": 86, + "grid_y": 187, + "segment": "SEG_DSP0_R_X33Y20", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y21": { + "bits": {}, + "grid_x": 86, + "grid_y": 186, + "segment": "SEG_DSP1_R_X33Y20", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y22": { + "bits": {}, + "grid_x": 86, + "grid_y": 185, + "segment": "SEG_DSP2_R_X33Y20", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y23": { + "bits": {}, + "grid_x": 86, + "grid_y": 184, + "segment": "SEG_DSP3_R_X33Y20", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y24": { + "bits": {}, + "grid_x": 86, + "grid_y": 183, + "segment": "SEG_DSP4_R_X33Y20", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y25": { + "bits": {}, + "grid_x": 86, + "grid_y": 181, + "segment": "SEG_DSP0_R_X33Y25", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y26": { + "bits": {}, + "grid_x": 86, + "grid_y": 180, + "segment": "SEG_DSP1_R_X33Y25", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y27": { + "bits": {}, + "grid_x": 86, + "grid_y": 179, + "segment": "SEG_DSP2_R_X33Y25", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y28": { + "bits": {}, + "grid_x": 86, + "grid_y": 178, + "segment": "SEG_DSP3_R_X33Y25", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y29": { + "bits": {}, + "grid_x": 86, + "grid_y": 177, + "segment": "SEG_DSP4_R_X33Y25", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y3": { + "bits": {}, + "grid_x": 86, + "grid_y": 204, + "segment": "SEG_DSP3_R_X33Y0", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y30": { + "bits": {}, + "grid_x": 86, + "grid_y": 176, + "segment": "SEG_DSP0_R_X33Y30", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y31": { + "bits": {}, + "grid_x": 86, + "grid_y": 175, + "segment": "SEG_DSP1_R_X33Y30", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y32": { + "bits": {}, + "grid_x": 86, + "grid_y": 174, + "segment": "SEG_DSP2_R_X33Y30", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y33": { + "bits": {}, + "grid_x": 86, + "grid_y": 173, + "segment": "SEG_DSP3_R_X33Y30", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y34": { + "bits": {}, + "grid_x": 86, + "grid_y": 172, + "segment": "SEG_DSP4_R_X33Y30", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y35": { + "bits": {}, + "grid_x": 86, + "grid_y": 171, + "segment": "SEG_DSP0_R_X33Y35", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y36": { + "bits": {}, + "grid_x": 86, + "grid_y": 170, + "segment": "SEG_DSP1_R_X33Y35", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y37": { + "bits": {}, + "grid_x": 86, + "grid_y": 169, + "segment": "SEG_DSP2_R_X33Y35", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y38": { + "bits": {}, + "grid_x": 86, + "grid_y": 168, + "segment": "SEG_DSP3_R_X33Y35", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y39": { + "bits": {}, + "grid_x": 86, + "grid_y": 167, + "segment": "SEG_DSP4_R_X33Y35", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y4": { + "bits": {}, + "grid_x": 86, + "grid_y": 203, + "segment": "SEG_DSP4_R_X33Y0", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y40": { + "bits": {}, + "grid_x": 86, + "grid_y": 166, + "segment": "SEG_DSP0_R_X33Y40", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y41": { + "bits": {}, + "grid_x": 86, + "grid_y": 165, + "segment": "SEG_DSP1_R_X33Y40", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y42": { + "bits": {}, + "grid_x": 86, + "grid_y": 164, + "segment": "SEG_DSP2_R_X33Y40", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y43": { + "bits": {}, + "grid_x": 86, + "grid_y": 163, + "segment": "SEG_DSP3_R_X33Y40", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y44": { + "bits": {}, + "grid_x": 86, + "grid_y": 162, + "segment": "SEG_DSP4_R_X33Y40", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y45": { + "bits": {}, + "grid_x": 86, + "grid_y": 161, + "segment": "SEG_DSP0_R_X33Y45", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y46": { + "bits": {}, + "grid_x": 86, + "grid_y": 160, + "segment": "SEG_DSP1_R_X33Y45", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y47": { + "bits": {}, + "grid_x": 86, + "grid_y": 159, + "segment": "SEG_DSP2_R_X33Y45", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y48": { + "bits": {}, + "grid_x": 86, + "grid_y": 158, + "segment": "SEG_DSP3_R_X33Y45", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y49": { + "bits": {}, + "grid_x": 86, + "grid_y": 157, + "segment": "SEG_DSP4_R_X33Y45", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y5": { + "bits": {}, + "grid_x": 86, + "grid_y": 202, + "segment": "SEG_DSP0_R_X33Y5", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y50": { + "bits": {}, + "grid_x": 86, + "grid_y": 155, + "segment": "SEG_DSP0_R_X33Y50", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y51": { + "bits": {}, + "grid_x": 86, + "grid_y": 154, + "segment": "SEG_DSP1_R_X33Y50", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y52": { + "bits": {}, + "grid_x": 86, + "grid_y": 153, + "segment": "SEG_DSP2_R_X33Y50", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y53": { + "bits": {}, + "grid_x": 86, + "grid_y": 152, + "segment": "SEG_DSP3_R_X33Y50", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y54": { + "bits": {}, + "grid_x": 86, + "grid_y": 151, + "segment": "SEG_DSP4_R_X33Y50", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y55": { + "bits": {}, + "grid_x": 86, + "grid_y": 150, + "segment": "SEG_DSP0_R_X33Y55", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y56": { + "bits": {}, + "grid_x": 86, + "grid_y": 149, + "segment": "SEG_DSP1_R_X33Y55", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y57": { + "bits": {}, + "grid_x": 86, + "grid_y": 148, + "segment": "SEG_DSP2_R_X33Y55", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y58": { + "bits": {}, + "grid_x": 86, + "grid_y": 147, + "segment": "SEG_DSP3_R_X33Y55", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y59": { + "bits": {}, + "grid_x": 86, + "grid_y": 146, + "segment": "SEG_DSP4_R_X33Y55", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y6": { + "bits": {}, + "grid_x": 86, + "grid_y": 201, + "segment": "SEG_DSP1_R_X33Y5", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y60": { + "bits": {}, + "grid_x": 86, + "grid_y": 145, + "segment": "SEG_DSP0_R_X33Y60", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y61": { + "bits": {}, + "grid_x": 86, + "grid_y": 144, + "segment": "SEG_DSP1_R_X33Y60", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y62": { + "bits": {}, + "grid_x": 86, + "grid_y": 143, + "segment": "SEG_DSP2_R_X33Y60", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y63": { + "bits": {}, + "grid_x": 86, + "grid_y": 142, + "segment": "SEG_DSP3_R_X33Y60", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y64": { + "bits": {}, + "grid_x": 86, + "grid_y": 141, + "segment": "SEG_DSP4_R_X33Y60", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y65": { + "bits": {}, + "grid_x": 86, + "grid_y": 140, + "segment": "SEG_DSP0_R_X33Y65", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y66": { + "bits": {}, + "grid_x": 86, + "grid_y": 139, + "segment": "SEG_DSP1_R_X33Y65", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y67": { + "bits": {}, + "grid_x": 86, + "grid_y": 138, + "segment": "SEG_DSP2_R_X33Y65", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y68": { + "bits": {}, + "grid_x": 86, + "grid_y": 137, + "segment": "SEG_DSP3_R_X33Y65", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y69": { + "bits": {}, + "grid_x": 86, + "grid_y": 136, + "segment": "SEG_DSP4_R_X33Y65", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y7": { + "bits": {}, + "grid_x": 86, + "grid_y": 200, + "segment": "SEG_DSP2_R_X33Y5", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y70": { + "bits": {}, + "grid_x": 86, + "grid_y": 135, + "segment": "SEG_DSP0_R_X33Y70", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y71": { + "bits": {}, + "grid_x": 86, + "grid_y": 134, + "segment": "SEG_DSP1_R_X33Y70", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y72": { + "bits": {}, + "grid_x": 86, + "grid_y": 133, + "segment": "SEG_DSP2_R_X33Y70", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y73": { + "bits": {}, + "grid_x": 86, + "grid_y": 132, + "segment": "SEG_DSP3_R_X33Y70", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y74": { + "bits": {}, + "grid_x": 86, + "grid_y": 131, + "segment": "SEG_DSP4_R_X33Y70", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y75": { + "bits": {}, + "grid_x": 86, + "grid_y": 129, + "segment": "SEG_DSP0_R_X33Y75", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y76": { + "bits": {}, + "grid_x": 86, + "grid_y": 128, + "segment": "SEG_DSP1_R_X33Y75", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y77": { + "bits": {}, + "grid_x": 86, + "grid_y": 127, + "segment": "SEG_DSP2_R_X33Y75", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y78": { + "bits": {}, + "grid_x": 86, + "grid_y": 126, + "segment": "SEG_DSP3_R_X33Y75", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y79": { + "bits": {}, + "grid_x": 86, + "grid_y": 125, + "segment": "SEG_DSP4_R_X33Y75", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y8": { + "bits": {}, + "grid_x": 86, + "grid_y": 199, + "segment": "SEG_DSP3_R_X33Y5", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y80": { + "bits": {}, + "grid_x": 86, + "grid_y": 124, + "segment": "SEG_DSP0_R_X33Y80", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y81": { + "bits": {}, + "grid_x": 86, + "grid_y": 123, + "segment": "SEG_DSP1_R_X33Y80", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y82": { + "bits": {}, + "grid_x": 86, + "grid_y": 122, + "segment": "SEG_DSP2_R_X33Y80", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y83": { + "bits": {}, + "grid_x": 86, + "grid_y": 121, + "segment": "SEG_DSP3_R_X33Y80", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y84": { + "bits": {}, + "grid_x": 86, + "grid_y": 120, + "segment": "SEG_DSP4_R_X33Y80", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y85": { + "bits": {}, + "grid_x": 86, + "grid_y": 119, + "segment": "SEG_DSP0_R_X33Y85", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y86": { + "bits": {}, + "grid_x": 86, + "grid_y": 118, + "segment": "SEG_DSP1_R_X33Y85", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y87": { + "bits": {}, + "grid_x": 86, + "grid_y": 117, + "segment": "SEG_DSP2_R_X33Y85", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y88": { + "bits": {}, + "grid_x": 86, + "grid_y": 116, + "segment": "SEG_DSP3_R_X33Y85", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y89": { + "bits": {}, + "grid_x": 86, + "grid_y": 115, + "segment": "SEG_DSP4_R_X33Y85", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y9": { + "bits": {}, + "grid_x": 86, + "grid_y": 198, + "segment": "SEG_DSP4_R_X33Y5", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y90": { + "bits": {}, + "grid_x": 86, + "grid_y": 114, + "segment": "SEG_DSP0_R_X33Y90", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y91": { + "bits": {}, + "grid_x": 86, + "grid_y": 113, + "segment": "SEG_DSP1_R_X33Y90", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y92": { + "bits": {}, + "grid_x": 86, + "grid_y": 112, + "segment": "SEG_DSP2_R_X33Y90", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y93": { + "bits": {}, + "grid_x": 86, + "grid_y": 111, + "segment": "SEG_DSP3_R_X33Y90", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y94": { + "bits": {}, + "grid_x": 86, + "grid_y": 110, + "segment": "SEG_DSP4_R_X33Y90", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y95": { + "bits": {}, + "grid_x": 86, + "grid_y": 109, + "segment": "SEG_DSP0_R_X33Y95", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y96": { + "bits": {}, + "grid_x": 86, + "grid_y": 108, + "segment": "SEG_DSP1_R_X33Y95", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y97": { + "bits": {}, + "grid_x": 86, + "grid_y": 107, + "segment": "SEG_DSP2_R_X33Y95", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y98": { + "bits": {}, + "grid_x": 86, + "grid_y": 106, + "segment": "SEG_DSP3_R_X33Y95", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X33Y99": { + "bits": {}, + "grid_x": 86, + "grid_y": 105, + "segment": "SEG_DSP4_R_X33Y95", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y0": { + "bits": {}, + "grid_x": 27, + "grid_y": 207, + "segment": "SEG_DSP0_R_X9Y0", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y1": { + "bits": {}, + "grid_x": 27, + "grid_y": 206, + "segment": "SEG_DSP1_R_X9Y0", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y10": { + "bits": {}, + "grid_x": 27, + "grid_y": 197, + "segment": "SEG_DSP0_R_X9Y10", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y100": { + "bits": {}, + "grid_x": 27, + "grid_y": 103, + "segment": "SEG_DSP0_R_X9Y100", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y101": { + "bits": {}, + "grid_x": 27, + "grid_y": 102, + "segment": "SEG_DSP1_R_X9Y100", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y102": { + "bits": {}, + "grid_x": 27, + "grid_y": 101, + "segment": "SEG_DSP2_R_X9Y100", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y103": { + "bits": {}, + "grid_x": 27, + "grid_y": 100, + "segment": "SEG_DSP3_R_X9Y100", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y104": { + "bits": {}, + "grid_x": 27, + "grid_y": 99, + "segment": "SEG_DSP4_R_X9Y100", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y105": { + "bits": {}, + "grid_x": 27, + "grid_y": 98, + "segment": "SEG_DSP0_R_X9Y105", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y106": { + "bits": {}, + "grid_x": 27, + "grid_y": 97, + "segment": "SEG_DSP1_R_X9Y105", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y107": { + "bits": {}, + "grid_x": 27, + "grid_y": 96, + "segment": "SEG_DSP2_R_X9Y105", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y108": { + "bits": {}, + "grid_x": 27, + "grid_y": 95, + "segment": "SEG_DSP3_R_X9Y105", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y109": { + "bits": {}, + "grid_x": 27, + "grid_y": 94, + "segment": "SEG_DSP4_R_X9Y105", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y11": { + "bits": {}, + "grid_x": 27, + "grid_y": 196, + "segment": "SEG_DSP1_R_X9Y10", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y110": { + "bits": {}, + "grid_x": 27, + "grid_y": 93, + "segment": "SEG_DSP0_R_X9Y110", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y111": { + "bits": {}, + "grid_x": 27, + "grid_y": 92, + "segment": "SEG_DSP1_R_X9Y110", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y112": { + "bits": {}, + "grid_x": 27, + "grid_y": 91, + "segment": "SEG_DSP2_R_X9Y110", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y113": { + "bits": {}, + "grid_x": 27, + "grid_y": 90, + "segment": "SEG_DSP3_R_X9Y110", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y114": { + "bits": {}, + "grid_x": 27, + "grid_y": 89, + "segment": "SEG_DSP4_R_X9Y110", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y115": { + "bits": {}, + "grid_x": 27, + "grid_y": 88, + "segment": "SEG_DSP0_R_X9Y115", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y116": { + "bits": {}, + "grid_x": 27, + "grid_y": 87, + "segment": "SEG_DSP1_R_X9Y115", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y117": { + "bits": {}, + "grid_x": 27, + "grid_y": 86, + "segment": "SEG_DSP2_R_X9Y115", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y118": { + "bits": {}, + "grid_x": 27, + "grid_y": 85, + "segment": "SEG_DSP3_R_X9Y115", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y119": { + "bits": {}, + "grid_x": 27, + "grid_y": 84, + "segment": "SEG_DSP4_R_X9Y115", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y12": { + "bits": {}, + "grid_x": 27, + "grid_y": 195, + "segment": "SEG_DSP2_R_X9Y10", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y120": { + "bits": {}, + "grid_x": 27, + "grid_y": 83, + "segment": "SEG_DSP0_R_X9Y120", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y121": { + "bits": {}, + "grid_x": 27, + "grid_y": 82, + "segment": "SEG_DSP1_R_X9Y120", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y122": { + "bits": {}, + "grid_x": 27, + "grid_y": 81, + "segment": "SEG_DSP2_R_X9Y120", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y123": { + "bits": {}, + "grid_x": 27, + "grid_y": 80, + "segment": "SEG_DSP3_R_X9Y120", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y124": { + "bits": {}, + "grid_x": 27, + "grid_y": 79, + "segment": "SEG_DSP4_R_X9Y120", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y125": { + "bits": {}, + "grid_x": 27, + "grid_y": 77, + "segment": "SEG_DSP0_R_X9Y125", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y126": { + "bits": {}, + "grid_x": 27, + "grid_y": 76, + "segment": "SEG_DSP1_R_X9Y125", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y127": { + "bits": {}, + "grid_x": 27, + "grid_y": 75, + "segment": "SEG_DSP2_R_X9Y125", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y128": { + "bits": {}, + "grid_x": 27, + "grid_y": 74, + "segment": "SEG_DSP3_R_X9Y125", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y129": { + "bits": {}, + "grid_x": 27, + "grid_y": 73, + "segment": "SEG_DSP4_R_X9Y125", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y13": { + "bits": {}, + "grid_x": 27, + "grid_y": 194, + "segment": "SEG_DSP3_R_X9Y10", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y130": { + "bits": {}, + "grid_x": 27, + "grid_y": 72, + "segment": "SEG_DSP0_R_X9Y130", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y131": { + "bits": {}, + "grid_x": 27, + "grid_y": 71, + "segment": "SEG_DSP1_R_X9Y130", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y132": { + "bits": {}, + "grid_x": 27, + "grid_y": 70, + "segment": "SEG_DSP2_R_X9Y130", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y133": { + "bits": {}, + "grid_x": 27, + "grid_y": 69, + "segment": "SEG_DSP3_R_X9Y130", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y134": { + "bits": {}, + "grid_x": 27, + "grid_y": 68, + "segment": "SEG_DSP4_R_X9Y130", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y135": { + "bits": {}, + "grid_x": 27, + "grid_y": 67, + "segment": "SEG_DSP0_R_X9Y135", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y136": { + "bits": {}, + "grid_x": 27, + "grid_y": 66, + "segment": "SEG_DSP1_R_X9Y135", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y137": { + "bits": {}, + "grid_x": 27, + "grid_y": 65, + "segment": "SEG_DSP2_R_X9Y135", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y138": { + "bits": {}, + "grid_x": 27, + "grid_y": 64, + "segment": "SEG_DSP3_R_X9Y135", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y139": { + "bits": {}, + "grid_x": 27, + "grid_y": 63, + "segment": "SEG_DSP4_R_X9Y135", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y14": { + "bits": {}, + "grid_x": 27, + "grid_y": 193, + "segment": "SEG_DSP4_R_X9Y10", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y140": { + "bits": {}, + "grid_x": 27, + "grid_y": 62, + "segment": "SEG_DSP0_R_X9Y140", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y141": { + "bits": {}, + "grid_x": 27, + "grid_y": 61, + "segment": "SEG_DSP1_R_X9Y140", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y142": { + "bits": {}, + "grid_x": 27, + "grid_y": 60, + "segment": "SEG_DSP2_R_X9Y140", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y143": { + "bits": {}, + "grid_x": 27, + "grid_y": 59, + "segment": "SEG_DSP3_R_X9Y140", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y144": { + "bits": {}, + "grid_x": 27, + "grid_y": 58, + "segment": "SEG_DSP4_R_X9Y140", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y145": { + "bits": {}, + "grid_x": 27, + "grid_y": 57, + "segment": "SEG_DSP0_R_X9Y145", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y146": { + "bits": {}, + "grid_x": 27, + "grid_y": 56, + "segment": "SEG_DSP1_R_X9Y145", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y147": { + "bits": {}, + "grid_x": 27, + "grid_y": 55, + "segment": "SEG_DSP2_R_X9Y145", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y148": { + "bits": {}, + "grid_x": 27, + "grid_y": 54, + "segment": "SEG_DSP3_R_X9Y145", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y149": { + "bits": {}, + "grid_x": 27, + "grid_y": 53, + "segment": "SEG_DSP4_R_X9Y145", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y15": { + "bits": {}, + "grid_x": 27, + "grid_y": 192, + "segment": "SEG_DSP0_R_X9Y15", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y150": { + "bits": {}, + "grid_x": 27, + "grid_y": 51, + "segment": "SEG_DSP0_R_X9Y150", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y151": { + "bits": {}, + "grid_x": 27, + "grid_y": 50, + "segment": "SEG_DSP1_R_X9Y150", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y152": { + "bits": {}, + "grid_x": 27, + "grid_y": 49, + "segment": "SEG_DSP2_R_X9Y150", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y153": { + "bits": {}, + "grid_x": 27, + "grid_y": 48, + "segment": "SEG_DSP3_R_X9Y150", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y154": { + "bits": {}, + "grid_x": 27, + "grid_y": 47, + "segment": "SEG_DSP4_R_X9Y150", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y155": { + "bits": {}, + "grid_x": 27, + "grid_y": 46, + "segment": "SEG_DSP0_R_X9Y155", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y156": { + "bits": {}, + "grid_x": 27, + "grid_y": 45, + "segment": "SEG_DSP1_R_X9Y155", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y157": { + "bits": {}, + "grid_x": 27, + "grid_y": 44, + "segment": "SEG_DSP2_R_X9Y155", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y158": { + "bits": {}, + "grid_x": 27, + "grid_y": 43, + "segment": "SEG_DSP3_R_X9Y155", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y159": { + "bits": {}, + "grid_x": 27, + "grid_y": 42, + "segment": "SEG_DSP4_R_X9Y155", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y16": { + "bits": {}, + "grid_x": 27, + "grid_y": 191, + "segment": "SEG_DSP1_R_X9Y15", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y160": { + "bits": {}, + "grid_x": 27, + "grid_y": 41, + "segment": "SEG_DSP0_R_X9Y160", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y161": { + "bits": {}, + "grid_x": 27, + "grid_y": 40, + "segment": "SEG_DSP1_R_X9Y160", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y162": { + "bits": {}, + "grid_x": 27, + "grid_y": 39, + "segment": "SEG_DSP2_R_X9Y160", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y163": { + "bits": {}, + "grid_x": 27, + "grid_y": 38, + "segment": "SEG_DSP3_R_X9Y160", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y164": { + "bits": {}, + "grid_x": 27, + "grid_y": 37, + "segment": "SEG_DSP4_R_X9Y160", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y165": { + "bits": {}, + "grid_x": 27, + "grid_y": 36, + "segment": "SEG_DSP0_R_X9Y165", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y166": { + "bits": {}, + "grid_x": 27, + "grid_y": 35, + "segment": "SEG_DSP1_R_X9Y165", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y167": { + "bits": {}, + "grid_x": 27, + "grid_y": 34, + "segment": "SEG_DSP2_R_X9Y165", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y168": { + "bits": {}, + "grid_x": 27, + "grid_y": 33, + "segment": "SEG_DSP3_R_X9Y165", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y169": { + "bits": {}, + "grid_x": 27, + "grid_y": 32, + "segment": "SEG_DSP4_R_X9Y165", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y17": { + "bits": {}, + "grid_x": 27, + "grid_y": 190, + "segment": "SEG_DSP2_R_X9Y15", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y170": { + "bits": {}, + "grid_x": 27, + "grid_y": 31, + "segment": "SEG_DSP0_R_X9Y170", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y171": { + "bits": {}, + "grid_x": 27, + "grid_y": 30, + "segment": "SEG_DSP1_R_X9Y170", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y172": { + "bits": {}, + "grid_x": 27, + "grid_y": 29, + "segment": "SEG_DSP2_R_X9Y170", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y173": { + "bits": {}, + "grid_x": 27, + "grid_y": 28, + "segment": "SEG_DSP3_R_X9Y170", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y174": { + "bits": {}, + "grid_x": 27, + "grid_y": 27, + "segment": "SEG_DSP4_R_X9Y170", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y175": { + "bits": {}, + "grid_x": 27, + "grid_y": 25, + "segment": "SEG_DSP0_R_X9Y175", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y176": { + "bits": {}, + "grid_x": 27, + "grid_y": 24, + "segment": "SEG_DSP1_R_X9Y175", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y177": { + "bits": {}, + "grid_x": 27, + "grid_y": 23, + "segment": "SEG_DSP2_R_X9Y175", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y178": { + "bits": {}, + "grid_x": 27, + "grid_y": 22, + "segment": "SEG_DSP3_R_X9Y175", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y179": { + "bits": {}, + "grid_x": 27, + "grid_y": 21, + "segment": "SEG_DSP4_R_X9Y175", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y18": { + "bits": {}, + "grid_x": 27, + "grid_y": 189, + "segment": "SEG_DSP3_R_X9Y15", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y180": { + "bits": {}, + "grid_x": 27, + "grid_y": 20, + "segment": "SEG_DSP0_R_X9Y180", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y181": { + "bits": {}, + "grid_x": 27, + "grid_y": 19, + "segment": "SEG_DSP1_R_X9Y180", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y182": { + "bits": {}, + "grid_x": 27, + "grid_y": 18, + "segment": "SEG_DSP2_R_X9Y180", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y183": { + "bits": {}, + "grid_x": 27, + "grid_y": 17, + "segment": "SEG_DSP3_R_X9Y180", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y184": { + "bits": {}, + "grid_x": 27, + "grid_y": 16, + "segment": "SEG_DSP4_R_X9Y180", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y185": { + "bits": {}, + "grid_x": 27, + "grid_y": 15, + "segment": "SEG_DSP0_R_X9Y185", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y186": { + "bits": {}, + "grid_x": 27, + "grid_y": 14, + "segment": "SEG_DSP1_R_X9Y185", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y187": { + "bits": {}, + "grid_x": 27, + "grid_y": 13, + "segment": "SEG_DSP2_R_X9Y185", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y188": { + "bits": {}, + "grid_x": 27, + "grid_y": 12, + "segment": "SEG_DSP3_R_X9Y185", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y189": { + "bits": {}, + "grid_x": 27, + "grid_y": 11, + "segment": "SEG_DSP4_R_X9Y185", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y19": { + "bits": {}, + "grid_x": 27, + "grid_y": 188, + "segment": "SEG_DSP4_R_X9Y15", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y190": { + "bits": {}, + "grid_x": 27, + "grid_y": 10, + "segment": "SEG_DSP0_R_X9Y190", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y191": { + "bits": {}, + "grid_x": 27, + "grid_y": 9, + "segment": "SEG_DSP1_R_X9Y190", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y192": { + "bits": {}, + "grid_x": 27, + "grid_y": 8, + "segment": "SEG_DSP2_R_X9Y190", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y193": { + "bits": {}, + "grid_x": 27, + "grid_y": 7, + "segment": "SEG_DSP3_R_X9Y190", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y194": { + "bits": {}, + "grid_x": 27, + "grid_y": 6, + "segment": "SEG_DSP4_R_X9Y190", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y195": { + "bits": {}, + "grid_x": 27, + "grid_y": 5, + "segment": "SEG_DSP0_R_X9Y195", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y196": { + "bits": {}, + "grid_x": 27, + "grid_y": 4, + "segment": "SEG_DSP1_R_X9Y195", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y197": { + "bits": {}, + "grid_x": 27, + "grid_y": 3, + "segment": "SEG_DSP2_R_X9Y195", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y198": { + "bits": {}, + "grid_x": 27, + "grid_y": 2, + "segment": "SEG_DSP3_R_X9Y195", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y199": { + "bits": {}, + "grid_x": 27, + "grid_y": 1, + "segment": "SEG_DSP4_R_X9Y195", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y2": { + "bits": {}, + "grid_x": 27, + "grid_y": 205, + "segment": "SEG_DSP2_R_X9Y0", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y20": { + "bits": {}, + "grid_x": 27, + "grid_y": 187, + "segment": "SEG_DSP0_R_X9Y20", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y21": { + "bits": {}, + "grid_x": 27, + "grid_y": 186, + "segment": "SEG_DSP1_R_X9Y20", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y22": { + "bits": {}, + "grid_x": 27, + "grid_y": 185, + "segment": "SEG_DSP2_R_X9Y20", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y23": { + "bits": {}, + "grid_x": 27, + "grid_y": 184, + "segment": "SEG_DSP3_R_X9Y20", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y24": { + "bits": {}, + "grid_x": 27, + "grid_y": 183, + "segment": "SEG_DSP4_R_X9Y20", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y25": { + "bits": {}, + "grid_x": 27, + "grid_y": 181, + "segment": "SEG_DSP0_R_X9Y25", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y26": { + "bits": {}, + "grid_x": 27, + "grid_y": 180, + "segment": "SEG_DSP1_R_X9Y25", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y27": { + "bits": {}, + "grid_x": 27, + "grid_y": 179, + "segment": "SEG_DSP2_R_X9Y25", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y28": { + "bits": {}, + "grid_x": 27, + "grid_y": 178, + "segment": "SEG_DSP3_R_X9Y25", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y29": { + "bits": {}, + "grid_x": 27, + "grid_y": 177, + "segment": "SEG_DSP4_R_X9Y25", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y3": { + "bits": {}, + "grid_x": 27, + "grid_y": 204, + "segment": "SEG_DSP3_R_X9Y0", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y30": { + "bits": {}, + "grid_x": 27, + "grid_y": 176, + "segment": "SEG_DSP0_R_X9Y30", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y31": { + "bits": {}, + "grid_x": 27, + "grid_y": 175, + "segment": "SEG_DSP1_R_X9Y30", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y32": { + "bits": {}, + "grid_x": 27, + "grid_y": 174, + "segment": "SEG_DSP2_R_X9Y30", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y33": { + "bits": {}, + "grid_x": 27, + "grid_y": 173, + "segment": "SEG_DSP3_R_X9Y30", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y34": { + "bits": {}, + "grid_x": 27, + "grid_y": 172, + "segment": "SEG_DSP4_R_X9Y30", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y35": { + "bits": {}, + "grid_x": 27, + "grid_y": 171, + "segment": "SEG_DSP0_R_X9Y35", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y36": { + "bits": {}, + "grid_x": 27, + "grid_y": 170, + "segment": "SEG_DSP1_R_X9Y35", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y37": { + "bits": {}, + "grid_x": 27, + "grid_y": 169, + "segment": "SEG_DSP2_R_X9Y35", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y38": { + "bits": {}, + "grid_x": 27, + "grid_y": 168, + "segment": "SEG_DSP3_R_X9Y35", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y39": { + "bits": {}, + "grid_x": 27, + "grid_y": 167, + "segment": "SEG_DSP4_R_X9Y35", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y4": { + "bits": {}, + "grid_x": 27, + "grid_y": 203, + "segment": "SEG_DSP4_R_X9Y0", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y40": { + "bits": {}, + "grid_x": 27, + "grid_y": 166, + "segment": "SEG_DSP0_R_X9Y40", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y41": { + "bits": {}, + "grid_x": 27, + "grid_y": 165, + "segment": "SEG_DSP1_R_X9Y40", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y42": { + "bits": {}, + "grid_x": 27, + "grid_y": 164, + "segment": "SEG_DSP2_R_X9Y40", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y43": { + "bits": {}, + "grid_x": 27, + "grid_y": 163, + "segment": "SEG_DSP3_R_X9Y40", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y44": { + "bits": {}, + "grid_x": 27, + "grid_y": 162, + "segment": "SEG_DSP4_R_X9Y40", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y45": { + "bits": {}, + "grid_x": 27, + "grid_y": 161, + "segment": "SEG_DSP0_R_X9Y45", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y46": { + "bits": {}, + "grid_x": 27, + "grid_y": 160, + "segment": "SEG_DSP1_R_X9Y45", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y47": { + "bits": {}, + "grid_x": 27, + "grid_y": 159, + "segment": "SEG_DSP2_R_X9Y45", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y48": { + "bits": {}, + "grid_x": 27, + "grid_y": 158, + "segment": "SEG_DSP3_R_X9Y45", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y49": { + "bits": {}, + "grid_x": 27, + "grid_y": 157, + "segment": "SEG_DSP4_R_X9Y45", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y5": { + "bits": {}, + "grid_x": 27, + "grid_y": 202, + "segment": "SEG_DSP0_R_X9Y5", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 155, + "segment": "SEG_DSP0_R_X9Y50", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 154, + "segment": "SEG_DSP1_R_X9Y50", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 153, + "segment": "SEG_DSP2_R_X9Y50", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 152, + "segment": "SEG_DSP3_R_X9Y50", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 151, + "segment": "SEG_DSP4_R_X9Y50", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 150, + "segment": "SEG_DSP0_R_X9Y55", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 149, + "segment": "SEG_DSP1_R_X9Y55", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 148, + "segment": "SEG_DSP2_R_X9Y55", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 147, + "segment": "SEG_DSP3_R_X9Y55", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 146, + "segment": "SEG_DSP4_R_X9Y55", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y6": { + "bits": {}, + "grid_x": 27, + "grid_y": 201, + "segment": "SEG_DSP1_R_X9Y5", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 145, + "segment": "SEG_DSP0_R_X9Y60", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 144, + "segment": "SEG_DSP1_R_X9Y60", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 143, + "segment": "SEG_DSP2_R_X9Y60", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 142, + "segment": "SEG_DSP3_R_X9Y60", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 141, + "segment": "SEG_DSP4_R_X9Y60", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 140, + "segment": "SEG_DSP0_R_X9Y65", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 139, + "segment": "SEG_DSP1_R_X9Y65", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 138, + "segment": "SEG_DSP2_R_X9Y65", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 137, + "segment": "SEG_DSP3_R_X9Y65", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 136, + "segment": "SEG_DSP4_R_X9Y65", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y7": { + "bits": {}, + "grid_x": 27, + "grid_y": 200, + "segment": "SEG_DSP2_R_X9Y5", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 135, + "segment": "SEG_DSP0_R_X9Y70", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 134, + "segment": "SEG_DSP1_R_X9Y70", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 133, + "segment": "SEG_DSP2_R_X9Y70", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 132, + "segment": "SEG_DSP3_R_X9Y70", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 131, + "segment": "SEG_DSP4_R_X9Y70", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 129, + "segment": "SEG_DSP0_R_X9Y75", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 128, + "segment": "SEG_DSP1_R_X9Y75", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 127, + "segment": "SEG_DSP2_R_X9Y75", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 126, + "segment": "SEG_DSP3_R_X9Y75", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 125, + "segment": "SEG_DSP4_R_X9Y75", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y8": { + "bits": {}, + "grid_x": 27, + "grid_y": 199, + "segment": "SEG_DSP3_R_X9Y5", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 124, + "segment": "SEG_DSP0_R_X9Y80", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 123, + "segment": "SEG_DSP1_R_X9Y80", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 122, + "segment": "SEG_DSP2_R_X9Y80", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 121, + "segment": "SEG_DSP3_R_X9Y80", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 120, + "segment": "SEG_DSP4_R_X9Y80", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 119, + "segment": "SEG_DSP0_R_X9Y85", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 118, + "segment": "SEG_DSP1_R_X9Y85", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 117, + "segment": "SEG_DSP2_R_X9Y85", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 116, + "segment": "SEG_DSP3_R_X9Y85", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 115, + "segment": "SEG_DSP4_R_X9Y85", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y9": { + "bits": {}, + "grid_x": 27, + "grid_y": 198, + "segment": "SEG_DSP4_R_X9Y5", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 114, + "segment": "SEG_DSP0_R_X9Y90", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 113, + "segment": "SEG_DSP1_R_X9Y90", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 112, + "segment": "SEG_DSP2_R_X9Y90", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 111, + "segment": "SEG_DSP3_R_X9Y90", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 110, + "segment": "SEG_DSP4_R_X9Y90", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 109, + "segment": "SEG_DSP0_R_X9Y95", + "segment_type": "dsp0_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 108, + "segment": "SEG_DSP1_R_X9Y95", + "segment_type": "dsp1_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 107, + "segment": "SEG_DSP2_R_X9Y95", + "segment_type": "dsp2_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 106, + "segment": "SEG_DSP3_R_X9Y95", + "segment_type": "dsp3_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_INTERFACE_R_X9Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 27, + "grid_y": 105, + "segment": "SEG_DSP4_R_X9Y95", + "segment_type": "dsp4_r", + "sites": {}, + "type": "INT_INTERFACE_R" + }, + "INT_L_X0Y0": { + "bits": {}, + "grid_x": 4, + "grid_y": 207, + "sites": { + "TIEOFF_X0Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y1": { + "bits": {}, + "grid_x": 4, + "grid_y": 206, + "sites": { + "TIEOFF_X0Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y10": { + "bits": {}, + "grid_x": 4, + "grid_y": 197, + "sites": { + "TIEOFF_X0Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y100": { + "bits": {}, + "grid_x": 4, + "grid_y": 103, + "sites": { + "TIEOFF_X0Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y101": { + "bits": {}, + "grid_x": 4, + "grid_y": 102, + "sites": { + "TIEOFF_X0Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y102": { + "bits": {}, + "grid_x": 4, + "grid_y": 101, + "sites": { + "TIEOFF_X0Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y103": { + "bits": {}, + "grid_x": 4, + "grid_y": 100, + "sites": { + "TIEOFF_X0Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y104": { + "bits": {}, + "grid_x": 4, + "grid_y": 99, + "sites": { + "TIEOFF_X0Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y105": { + "bits": {}, + "grid_x": 4, + "grid_y": 98, + "sites": { + "TIEOFF_X0Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y106": { + "bits": {}, + "grid_x": 4, + "grid_y": 97, + "sites": { + "TIEOFF_X0Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y107": { + "bits": {}, + "grid_x": 4, + "grid_y": 96, + "sites": { + "TIEOFF_X0Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y108": { + "bits": {}, + "grid_x": 4, + "grid_y": 95, + "sites": { + "TIEOFF_X0Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y109": { + "bits": {}, + "grid_x": 4, + "grid_y": 94, + "sites": { + "TIEOFF_X0Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y11": { + "bits": {}, + "grid_x": 4, + "grid_y": 196, + "sites": { + "TIEOFF_X0Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y110": { + "bits": {}, + "grid_x": 4, + "grid_y": 93, + "sites": { + "TIEOFF_X0Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y111": { + "bits": {}, + "grid_x": 4, + "grid_y": 92, + "sites": { + "TIEOFF_X0Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y112": { + "bits": {}, + "grid_x": 4, + "grid_y": 91, + "sites": { + "TIEOFF_X0Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y113": { + "bits": {}, + "grid_x": 4, + "grid_y": 90, + "sites": { + "TIEOFF_X0Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y114": { + "bits": {}, + "grid_x": 4, + "grid_y": 89, + "sites": { + "TIEOFF_X0Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y115": { + "bits": {}, + "grid_x": 4, + "grid_y": 88, + "sites": { + "TIEOFF_X0Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y116": { + "bits": {}, + "grid_x": 4, + "grid_y": 87, + "sites": { + "TIEOFF_X0Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y117": { + "bits": {}, + "grid_x": 4, + "grid_y": 86, + "sites": { + "TIEOFF_X0Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y118": { + "bits": {}, + "grid_x": 4, + "grid_y": 85, + "sites": { + "TIEOFF_X0Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y119": { + "bits": {}, + "grid_x": 4, + "grid_y": 84, + "sites": { + "TIEOFF_X0Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y12": { + "bits": {}, + "grid_x": 4, + "grid_y": 195, + "sites": { + "TIEOFF_X0Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y120": { + "bits": {}, + "grid_x": 4, + "grid_y": 83, + "sites": { + "TIEOFF_X0Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y121": { + "bits": {}, + "grid_x": 4, + "grid_y": 82, + "sites": { + "TIEOFF_X0Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y122": { + "bits": {}, + "grid_x": 4, + "grid_y": 81, + "sites": { + "TIEOFF_X0Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y123": { + "bits": {}, + "grid_x": 4, + "grid_y": 80, + "sites": { + "TIEOFF_X0Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y124": { + "bits": {}, + "grid_x": 4, + "grid_y": 79, + "sites": { + "TIEOFF_X0Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y125": { + "bits": {}, + "grid_x": 4, + "grid_y": 77, + "sites": { + "TIEOFF_X0Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y126": { + "bits": {}, + "grid_x": 4, + "grid_y": 76, + "sites": { + "TIEOFF_X0Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y127": { + "bits": {}, + "grid_x": 4, + "grid_y": 75, + "sites": { + "TIEOFF_X0Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y128": { + "bits": {}, + "grid_x": 4, + "grid_y": 74, + "sites": { + "TIEOFF_X0Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y129": { + "bits": {}, + "grid_x": 4, + "grid_y": 73, + "sites": { + "TIEOFF_X0Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y13": { + "bits": {}, + "grid_x": 4, + "grid_y": 194, + "sites": { + "TIEOFF_X0Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y130": { + "bits": {}, + "grid_x": 4, + "grid_y": 72, + "sites": { + "TIEOFF_X0Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y131": { + "bits": {}, + "grid_x": 4, + "grid_y": 71, + "sites": { + "TIEOFF_X0Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y132": { + "bits": {}, + "grid_x": 4, + "grid_y": 70, + "sites": { + "TIEOFF_X0Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y133": { + "bits": {}, + "grid_x": 4, + "grid_y": 69, + "sites": { + "TIEOFF_X0Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y134": { + "bits": {}, + "grid_x": 4, + "grid_y": 68, + "sites": { + "TIEOFF_X0Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y135": { + "bits": {}, + "grid_x": 4, + "grid_y": 67, + "sites": { + "TIEOFF_X0Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y136": { + "bits": {}, + "grid_x": 4, + "grid_y": 66, + "sites": { + "TIEOFF_X0Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y137": { + "bits": {}, + "grid_x": 4, + "grid_y": 65, + "sites": { + "TIEOFF_X0Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y138": { + "bits": {}, + "grid_x": 4, + "grid_y": 64, + "sites": { + "TIEOFF_X0Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y139": { + "bits": {}, + "grid_x": 4, + "grid_y": 63, + "sites": { + "TIEOFF_X0Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y14": { + "bits": {}, + "grid_x": 4, + "grid_y": 193, + "sites": { + "TIEOFF_X0Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y140": { + "bits": {}, + "grid_x": 4, + "grid_y": 62, + "sites": { + "TIEOFF_X0Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y141": { + "bits": {}, + "grid_x": 4, + "grid_y": 61, + "sites": { + "TIEOFF_X0Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y142": { + "bits": {}, + "grid_x": 4, + "grid_y": 60, + "sites": { + "TIEOFF_X0Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y143": { + "bits": {}, + "grid_x": 4, + "grid_y": 59, + "sites": { + "TIEOFF_X0Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y144": { + "bits": {}, + "grid_x": 4, + "grid_y": 58, + "sites": { + "TIEOFF_X0Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y145": { + "bits": {}, + "grid_x": 4, + "grid_y": 57, + "sites": { + "TIEOFF_X0Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y146": { + "bits": {}, + "grid_x": 4, + "grid_y": 56, + "sites": { + "TIEOFF_X0Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y147": { + "bits": {}, + "grid_x": 4, + "grid_y": 55, + "sites": { + "TIEOFF_X0Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y148": { + "bits": {}, + "grid_x": 4, + "grid_y": 54, + "sites": { + "TIEOFF_X0Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y149": { + "bits": {}, + "grid_x": 4, + "grid_y": 53, + "sites": { + "TIEOFF_X0Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y15": { + "bits": {}, + "grid_x": 4, + "grid_y": 192, + "sites": { + "TIEOFF_X0Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y150": { + "bits": {}, + "grid_x": 4, + "grid_y": 51, + "sites": { + "TIEOFF_X0Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y151": { + "bits": {}, + "grid_x": 4, + "grid_y": 50, + "sites": { + "TIEOFF_X0Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y152": { + "bits": {}, + "grid_x": 4, + "grid_y": 49, + "sites": { + "TIEOFF_X0Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y153": { + "bits": {}, + "grid_x": 4, + "grid_y": 48, + "sites": { + "TIEOFF_X0Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y154": { + "bits": {}, + "grid_x": 4, + "grid_y": 47, + "sites": { + "TIEOFF_X0Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y155": { + "bits": {}, + "grid_x": 4, + "grid_y": 46, + "sites": { + "TIEOFF_X0Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y156": { + "bits": {}, + "grid_x": 4, + "grid_y": 45, + "sites": { + "TIEOFF_X0Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y157": { + "bits": {}, + "grid_x": 4, + "grid_y": 44, + "sites": { + "TIEOFF_X0Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y158": { + "bits": {}, + "grid_x": 4, + "grid_y": 43, + "sites": { + "TIEOFF_X0Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y159": { + "bits": {}, + "grid_x": 4, + "grid_y": 42, + "sites": { + "TIEOFF_X0Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y16": { + "bits": {}, + "grid_x": 4, + "grid_y": 191, + "sites": { + "TIEOFF_X0Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y160": { + "bits": {}, + "grid_x": 4, + "grid_y": 41, + "sites": { + "TIEOFF_X0Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y161": { + "bits": {}, + "grid_x": 4, + "grid_y": 40, + "sites": { + "TIEOFF_X0Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y162": { + "bits": {}, + "grid_x": 4, + "grid_y": 39, + "sites": { + "TIEOFF_X0Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y163": { + "bits": {}, + "grid_x": 4, + "grid_y": 38, + "sites": { + "TIEOFF_X0Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y164": { + "bits": {}, + "grid_x": 4, + "grid_y": 37, + "sites": { + "TIEOFF_X0Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y165": { + "bits": {}, + "grid_x": 4, + "grid_y": 36, + "sites": { + "TIEOFF_X0Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y166": { + "bits": {}, + "grid_x": 4, + "grid_y": 35, + "sites": { + "TIEOFF_X0Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y167": { + "bits": {}, + "grid_x": 4, + "grid_y": 34, + "sites": { + "TIEOFF_X0Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y168": { + "bits": {}, + "grid_x": 4, + "grid_y": 33, + "sites": { + "TIEOFF_X0Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y169": { + "bits": {}, + "grid_x": 4, + "grid_y": 32, + "sites": { + "TIEOFF_X0Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y17": { + "bits": {}, + "grid_x": 4, + "grid_y": 190, + "sites": { + "TIEOFF_X0Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y170": { + "bits": {}, + "grid_x": 4, + "grid_y": 31, + "sites": { + "TIEOFF_X0Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y171": { + "bits": {}, + "grid_x": 4, + "grid_y": 30, + "sites": { + "TIEOFF_X0Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y172": { + "bits": {}, + "grid_x": 4, + "grid_y": 29, + "sites": { + "TIEOFF_X0Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y173": { + "bits": {}, + "grid_x": 4, + "grid_y": 28, + "sites": { + "TIEOFF_X0Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y174": { + "bits": {}, + "grid_x": 4, + "grid_y": 27, + "sites": { + "TIEOFF_X0Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y175": { + "bits": {}, + "grid_x": 4, + "grid_y": 25, + "sites": { + "TIEOFF_X0Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y176": { + "bits": {}, + "grid_x": 4, + "grid_y": 24, + "sites": { + "TIEOFF_X0Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y177": { + "bits": {}, + "grid_x": 4, + "grid_y": 23, + "sites": { + "TIEOFF_X0Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y178": { + "bits": {}, + "grid_x": 4, + "grid_y": 22, + "sites": { + "TIEOFF_X0Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y179": { + "bits": {}, + "grid_x": 4, + "grid_y": 21, + "sites": { + "TIEOFF_X0Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y18": { + "bits": {}, + "grid_x": 4, + "grid_y": 189, + "sites": { + "TIEOFF_X0Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y180": { + "bits": {}, + "grid_x": 4, + "grid_y": 20, + "sites": { + "TIEOFF_X0Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y181": { + "bits": {}, + "grid_x": 4, + "grid_y": 19, + "sites": { + "TIEOFF_X0Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y182": { + "bits": {}, + "grid_x": 4, + "grid_y": 18, + "sites": { + "TIEOFF_X0Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y183": { + "bits": {}, + "grid_x": 4, + "grid_y": 17, + "sites": { + "TIEOFF_X0Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y184": { + "bits": {}, + "grid_x": 4, + "grid_y": 16, + "sites": { + "TIEOFF_X0Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y185": { + "bits": {}, + "grid_x": 4, + "grid_y": 15, + "sites": { + "TIEOFF_X0Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y186": { + "bits": {}, + "grid_x": 4, + "grid_y": 14, + "sites": { + "TIEOFF_X0Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y187": { + "bits": {}, + "grid_x": 4, + "grid_y": 13, + "sites": { + "TIEOFF_X0Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y188": { + "bits": {}, + "grid_x": 4, + "grid_y": 12, + "sites": { + "TIEOFF_X0Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y189": { + "bits": {}, + "grid_x": 4, + "grid_y": 11, + "sites": { + "TIEOFF_X0Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y19": { + "bits": {}, + "grid_x": 4, + "grid_y": 188, + "sites": { + "TIEOFF_X0Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y190": { + "bits": {}, + "grid_x": 4, + "grid_y": 10, + "sites": { + "TIEOFF_X0Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y191": { + "bits": {}, + "grid_x": 4, + "grid_y": 9, + "sites": { + "TIEOFF_X0Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y192": { + "bits": {}, + "grid_x": 4, + "grid_y": 8, + "sites": { + "TIEOFF_X0Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y193": { + "bits": {}, + "grid_x": 4, + "grid_y": 7, + "sites": { + "TIEOFF_X0Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y194": { + "bits": {}, + "grid_x": 4, + "grid_y": 6, + "sites": { + "TIEOFF_X0Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y195": { + "bits": {}, + "grid_x": 4, + "grid_y": 5, + "sites": { + "TIEOFF_X0Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y196": { + "bits": {}, + "grid_x": 4, + "grid_y": 4, + "sites": { + "TIEOFF_X0Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y197": { + "bits": {}, + "grid_x": 4, + "grid_y": 3, + "sites": { + "TIEOFF_X0Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y198": { + "bits": {}, + "grid_x": 4, + "grid_y": 2, + "sites": { + "TIEOFF_X0Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y199": { + "bits": {}, + "grid_x": 4, + "grid_y": 1, + "sites": { + "TIEOFF_X0Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y2": { + "bits": {}, + "grid_x": 4, + "grid_y": 205, + "sites": { + "TIEOFF_X0Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y20": { + "bits": {}, + "grid_x": 4, + "grid_y": 187, + "sites": { + "TIEOFF_X0Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y21": { + "bits": {}, + "grid_x": 4, + "grid_y": 186, + "sites": { + "TIEOFF_X0Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y22": { + "bits": {}, + "grid_x": 4, + "grid_y": 185, + "sites": { + "TIEOFF_X0Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y23": { + "bits": {}, + "grid_x": 4, + "grid_y": 184, + "sites": { + "TIEOFF_X0Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y24": { + "bits": {}, + "grid_x": 4, + "grid_y": 183, + "sites": { + "TIEOFF_X0Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y25": { + "bits": {}, + "grid_x": 4, + "grid_y": 181, + "sites": { + "TIEOFF_X0Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y26": { + "bits": {}, + "grid_x": 4, + "grid_y": 180, + "sites": { + "TIEOFF_X0Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y27": { + "bits": {}, + "grid_x": 4, + "grid_y": 179, + "sites": { + "TIEOFF_X0Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y28": { + "bits": {}, + "grid_x": 4, + "grid_y": 178, + "sites": { + "TIEOFF_X0Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y29": { + "bits": {}, + "grid_x": 4, + "grid_y": 177, + "sites": { + "TIEOFF_X0Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y3": { + "bits": {}, + "grid_x": 4, + "grid_y": 204, + "sites": { + "TIEOFF_X0Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y30": { + "bits": {}, + "grid_x": 4, + "grid_y": 176, + "sites": { + "TIEOFF_X0Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y31": { + "bits": {}, + "grid_x": 4, + "grid_y": 175, + "sites": { + "TIEOFF_X0Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y32": { + "bits": {}, + "grid_x": 4, + "grid_y": 174, + "sites": { + "TIEOFF_X0Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y33": { + "bits": {}, + "grid_x": 4, + "grid_y": 173, + "sites": { + "TIEOFF_X0Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y34": { + "bits": {}, + "grid_x": 4, + "grid_y": 172, + "sites": { + "TIEOFF_X0Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y35": { + "bits": {}, + "grid_x": 4, + "grid_y": 171, + "sites": { + "TIEOFF_X0Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y36": { + "bits": {}, + "grid_x": 4, + "grid_y": 170, + "sites": { + "TIEOFF_X0Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y37": { + "bits": {}, + "grid_x": 4, + "grid_y": 169, + "sites": { + "TIEOFF_X0Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y38": { + "bits": {}, + "grid_x": 4, + "grid_y": 168, + "sites": { + "TIEOFF_X0Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y39": { + "bits": {}, + "grid_x": 4, + "grid_y": 167, + "sites": { + "TIEOFF_X0Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y4": { + "bits": {}, + "grid_x": 4, + "grid_y": 203, + "sites": { + "TIEOFF_X0Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y40": { + "bits": {}, + "grid_x": 4, + "grid_y": 166, + "sites": { + "TIEOFF_X0Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y41": { + "bits": {}, + "grid_x": 4, + "grid_y": 165, + "sites": { + "TIEOFF_X0Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y42": { + "bits": {}, + "grid_x": 4, + "grid_y": 164, + "sites": { + "TIEOFF_X0Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y43": { + "bits": {}, + "grid_x": 4, + "grid_y": 163, + "sites": { + "TIEOFF_X0Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y44": { + "bits": {}, + "grid_x": 4, + "grid_y": 162, + "sites": { + "TIEOFF_X0Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y45": { + "bits": {}, + "grid_x": 4, + "grid_y": 161, + "sites": { + "TIEOFF_X0Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y46": { + "bits": {}, + "grid_x": 4, + "grid_y": 160, + "sites": { + "TIEOFF_X0Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y47": { + "bits": {}, + "grid_x": 4, + "grid_y": 159, + "sites": { + "TIEOFF_X0Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y48": { + "bits": {}, + "grid_x": 4, + "grid_y": 158, + "sites": { + "TIEOFF_X0Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y49": { + "bits": {}, + "grid_x": 4, + "grid_y": 157, + "sites": { + "TIEOFF_X0Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y5": { + "bits": {}, + "grid_x": 4, + "grid_y": 202, + "sites": { + "TIEOFF_X0Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y50": { + "bits": {}, + "grid_x": 4, + "grid_y": 155, + "sites": { + "TIEOFF_X0Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y51": { + "bits": {}, + "grid_x": 4, + "grid_y": 154, + "sites": { + "TIEOFF_X0Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y52": { + "bits": {}, + "grid_x": 4, + "grid_y": 153, + "sites": { + "TIEOFF_X0Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y53": { + "bits": {}, + "grid_x": 4, + "grid_y": 152, + "sites": { + "TIEOFF_X0Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y54": { + "bits": {}, + "grid_x": 4, + "grid_y": 151, + "sites": { + "TIEOFF_X0Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y55": { + "bits": {}, + "grid_x": 4, + "grid_y": 150, + "sites": { + "TIEOFF_X0Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y56": { + "bits": {}, + "grid_x": 4, + "grid_y": 149, + "sites": { + "TIEOFF_X0Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y57": { + "bits": {}, + "grid_x": 4, + "grid_y": 148, + "sites": { + "TIEOFF_X0Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y58": { + "bits": {}, + "grid_x": 4, + "grid_y": 147, + "sites": { + "TIEOFF_X0Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y59": { + "bits": {}, + "grid_x": 4, + "grid_y": 146, + "sites": { + "TIEOFF_X0Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y6": { + "bits": {}, + "grid_x": 4, + "grid_y": 201, + "sites": { + "TIEOFF_X0Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y60": { + "bits": {}, + "grid_x": 4, + "grid_y": 145, + "sites": { + "TIEOFF_X0Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y61": { + "bits": {}, + "grid_x": 4, + "grid_y": 144, + "sites": { + "TIEOFF_X0Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y62": { + "bits": {}, + "grid_x": 4, + "grid_y": 143, + "sites": { + "TIEOFF_X0Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y63": { + "bits": {}, + "grid_x": 4, + "grid_y": 142, + "sites": { + "TIEOFF_X0Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y64": { + "bits": {}, + "grid_x": 4, + "grid_y": 141, + "sites": { + "TIEOFF_X0Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y65": { + "bits": {}, + "grid_x": 4, + "grid_y": 140, + "sites": { + "TIEOFF_X0Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y66": { + "bits": {}, + "grid_x": 4, + "grid_y": 139, + "sites": { + "TIEOFF_X0Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y67": { + "bits": {}, + "grid_x": 4, + "grid_y": 138, + "sites": { + "TIEOFF_X0Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y68": { + "bits": {}, + "grid_x": 4, + "grid_y": 137, + "sites": { + "TIEOFF_X0Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y69": { + "bits": {}, + "grid_x": 4, + "grid_y": 136, + "sites": { + "TIEOFF_X0Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y7": { + "bits": {}, + "grid_x": 4, + "grid_y": 200, + "sites": { + "TIEOFF_X0Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y70": { + "bits": {}, + "grid_x": 4, + "grid_y": 135, + "sites": { + "TIEOFF_X0Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y71": { + "bits": {}, + "grid_x": 4, + "grid_y": 134, + "sites": { + "TIEOFF_X0Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y72": { + "bits": {}, + "grid_x": 4, + "grid_y": 133, + "sites": { + "TIEOFF_X0Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y73": { + "bits": {}, + "grid_x": 4, + "grid_y": 132, + "sites": { + "TIEOFF_X0Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y74": { + "bits": {}, + "grid_x": 4, + "grid_y": 131, + "sites": { + "TIEOFF_X0Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y75": { + "bits": {}, + "grid_x": 4, + "grid_y": 129, + "sites": { + "TIEOFF_X0Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y76": { + "bits": {}, + "grid_x": 4, + "grid_y": 128, + "sites": { + "TIEOFF_X0Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y77": { + "bits": {}, + "grid_x": 4, + "grid_y": 127, + "sites": { + "TIEOFF_X0Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y78": { + "bits": {}, + "grid_x": 4, + "grid_y": 126, + "sites": { + "TIEOFF_X0Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y79": { + "bits": {}, + "grid_x": 4, + "grid_y": 125, + "sites": { + "TIEOFF_X0Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y8": { + "bits": {}, + "grid_x": 4, + "grid_y": 199, + "sites": { + "TIEOFF_X0Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y80": { + "bits": {}, + "grid_x": 4, + "grid_y": 124, + "sites": { + "TIEOFF_X0Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y81": { + "bits": {}, + "grid_x": 4, + "grid_y": 123, + "sites": { + "TIEOFF_X0Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y82": { + "bits": {}, + "grid_x": 4, + "grid_y": 122, + "sites": { + "TIEOFF_X0Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y83": { + "bits": {}, + "grid_x": 4, + "grid_y": 121, + "sites": { + "TIEOFF_X0Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y84": { + "bits": {}, + "grid_x": 4, + "grid_y": 120, + "sites": { + "TIEOFF_X0Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y85": { + "bits": {}, + "grid_x": 4, + "grid_y": 119, + "sites": { + "TIEOFF_X0Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y86": { + "bits": {}, + "grid_x": 4, + "grid_y": 118, + "sites": { + "TIEOFF_X0Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y87": { + "bits": {}, + "grid_x": 4, + "grid_y": 117, + "sites": { + "TIEOFF_X0Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y88": { + "bits": {}, + "grid_x": 4, + "grid_y": 116, + "sites": { + "TIEOFF_X0Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y89": { + "bits": {}, + "grid_x": 4, + "grid_y": 115, + "sites": { + "TIEOFF_X0Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y9": { + "bits": {}, + "grid_x": 4, + "grid_y": 198, + "sites": { + "TIEOFF_X0Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y90": { + "bits": {}, + "grid_x": 4, + "grid_y": 114, + "sites": { + "TIEOFF_X0Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y91": { + "bits": {}, + "grid_x": 4, + "grid_y": 113, + "sites": { + "TIEOFF_X0Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y92": { + "bits": {}, + "grid_x": 4, + "grid_y": 112, + "sites": { + "TIEOFF_X0Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y93": { + "bits": {}, + "grid_x": 4, + "grid_y": 111, + "sites": { + "TIEOFF_X0Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y94": { + "bits": {}, + "grid_x": 4, + "grid_y": 110, + "sites": { + "TIEOFF_X0Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y95": { + "bits": {}, + "grid_x": 4, + "grid_y": 109, + "sites": { + "TIEOFF_X0Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y96": { + "bits": {}, + "grid_x": 4, + "grid_y": 108, + "sites": { + "TIEOFF_X0Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y97": { + "bits": {}, + "grid_x": 4, + "grid_y": 107, + "sites": { + "TIEOFF_X0Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y98": { + "bits": {}, + "grid_x": 4, + "grid_y": 106, + "sites": { + "TIEOFF_X0Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X0Y99": { + "bits": {}, + "grid_x": 4, + "grid_y": 105, + "sites": { + "TIEOFF_X0Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y0": { + "bits": {}, + "grid_x": 31, + "grid_y": 207, + "segment": "SEG_CLBLM_L_X10Y0", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y1": { + "bits": {}, + "grid_x": 31, + "grid_y": 206, + "segment": "SEG_CLBLM_L_X10Y1", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y10": { + "bits": {}, + "grid_x": 31, + "grid_y": 197, + "segment": "SEG_CLBLM_L_X10Y10", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y100": { + "bits": {}, + "grid_x": 31, + "grid_y": 103, + "segment": "SEG_CLBLM_L_X10Y100", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y101": { + "bits": {}, + "grid_x": 31, + "grid_y": 102, + "segment": "SEG_CLBLM_L_X10Y101", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y102": { + "bits": {}, + "grid_x": 31, + "grid_y": 101, + "segment": "SEG_CLBLM_L_X10Y102", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y103": { + "bits": {}, + "grid_x": 31, + "grid_y": 100, + "segment": "SEG_CLBLM_L_X10Y103", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y104": { + "bits": {}, + "grid_x": 31, + "grid_y": 99, + "segment": "SEG_CLBLM_L_X10Y104", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y105": { + "bits": {}, + "grid_x": 31, + "grid_y": 98, + "segment": "SEG_CLBLM_L_X10Y105", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y106": { + "bits": {}, + "grid_x": 31, + "grid_y": 97, + "segment": "SEG_CLBLM_L_X10Y106", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y107": { + "bits": {}, + "grid_x": 31, + "grid_y": 96, + "segment": "SEG_CLBLM_L_X10Y107", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y108": { + "bits": {}, + "grid_x": 31, + "grid_y": 95, + "segment": "SEG_CLBLM_L_X10Y108", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y109": { + "bits": {}, + "grid_x": 31, + "grid_y": 94, + "segment": "SEG_CLBLM_L_X10Y109", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y11": { + "bits": {}, + "grid_x": 31, + "grid_y": 196, + "segment": "SEG_CLBLM_L_X10Y11", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y110": { + "bits": {}, + "grid_x": 31, + "grid_y": 93, + "segment": "SEG_CLBLM_L_X10Y110", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y111": { + "bits": {}, + "grid_x": 31, + "grid_y": 92, + "segment": "SEG_CLBLM_L_X10Y111", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y112": { + "bits": {}, + "grid_x": 31, + "grid_y": 91, + "segment": "SEG_CLBLM_L_X10Y112", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y113": { + "bits": {}, + "grid_x": 31, + "grid_y": 90, + "segment": "SEG_CLBLM_L_X10Y113", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y114": { + "bits": {}, + "grid_x": 31, + "grid_y": 89, + "segment": "SEG_CLBLM_L_X10Y114", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y115": { + "bits": {}, + "grid_x": 31, + "grid_y": 88, + "segment": "SEG_CLBLM_L_X10Y115", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y116": { + "bits": {}, + "grid_x": 31, + "grid_y": 87, + "segment": "SEG_CLBLM_L_X10Y116", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y117": { + "bits": {}, + "grid_x": 31, + "grid_y": 86, + "segment": "SEG_CLBLM_L_X10Y117", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y118": { + "bits": {}, + "grid_x": 31, + "grid_y": 85, + "segment": "SEG_CLBLM_L_X10Y118", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y119": { + "bits": {}, + "grid_x": 31, + "grid_y": 84, + "segment": "SEG_CLBLM_L_X10Y119", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y12": { + "bits": {}, + "grid_x": 31, + "grid_y": 195, + "segment": "SEG_CLBLM_L_X10Y12", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y120": { + "bits": {}, + "grid_x": 31, + "grid_y": 83, + "segment": "SEG_CLBLM_L_X10Y120", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y121": { + "bits": {}, + "grid_x": 31, + "grid_y": 82, + "segment": "SEG_CLBLM_L_X10Y121", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y122": { + "bits": {}, + "grid_x": 31, + "grid_y": 81, + "segment": "SEG_CLBLM_L_X10Y122", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y123": { + "bits": {}, + "grid_x": 31, + "grid_y": 80, + "segment": "SEG_CLBLM_L_X10Y123", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y124": { + "bits": {}, + "grid_x": 31, + "grid_y": 79, + "segment": "SEG_CLBLM_L_X10Y124", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y125": { + "bits": {}, + "grid_x": 31, + "grid_y": 77, + "segment": "SEG_CLBLM_L_X10Y125", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y126": { + "bits": {}, + "grid_x": 31, + "grid_y": 76, + "segment": "SEG_CLBLM_L_X10Y126", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y127": { + "bits": {}, + "grid_x": 31, + "grid_y": 75, + "segment": "SEG_CLBLM_L_X10Y127", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y128": { + "bits": {}, + "grid_x": 31, + "grid_y": 74, + "segment": "SEG_CLBLM_L_X10Y128", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y129": { + "bits": {}, + "grid_x": 31, + "grid_y": 73, + "segment": "SEG_CLBLM_L_X10Y129", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y13": { + "bits": {}, + "grid_x": 31, + "grid_y": 194, + "segment": "SEG_CLBLM_L_X10Y13", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y130": { + "bits": {}, + "grid_x": 31, + "grid_y": 72, + "segment": "SEG_CLBLM_L_X10Y130", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y131": { + "bits": {}, + "grid_x": 31, + "grid_y": 71, + "segment": "SEG_CLBLM_L_X10Y131", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y132": { + "bits": {}, + "grid_x": 31, + "grid_y": 70, + "segment": "SEG_CLBLM_L_X10Y132", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y133": { + "bits": {}, + "grid_x": 31, + "grid_y": 69, + "segment": "SEG_CLBLM_L_X10Y133", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y134": { + "bits": {}, + "grid_x": 31, + "grid_y": 68, + "segment": "SEG_CLBLM_L_X10Y134", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y135": { + "bits": {}, + "grid_x": 31, + "grid_y": 67, + "segment": "SEG_CLBLM_L_X10Y135", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y136": { + "bits": {}, + "grid_x": 31, + "grid_y": 66, + "segment": "SEG_CLBLM_L_X10Y136", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y137": { + "bits": {}, + "grid_x": 31, + "grid_y": 65, + "segment": "SEG_CLBLM_L_X10Y137", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y138": { + "bits": {}, + "grid_x": 31, + "grid_y": 64, + "segment": "SEG_CLBLM_L_X10Y138", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y139": { + "bits": {}, + "grid_x": 31, + "grid_y": 63, + "segment": "SEG_CLBLM_L_X10Y139", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y14": { + "bits": {}, + "grid_x": 31, + "grid_y": 193, + "segment": "SEG_CLBLM_L_X10Y14", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y140": { + "bits": {}, + "grid_x": 31, + "grid_y": 62, + "segment": "SEG_CLBLM_L_X10Y140", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y141": { + "bits": {}, + "grid_x": 31, + "grid_y": 61, + "segment": "SEG_CLBLM_L_X10Y141", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y142": { + "bits": {}, + "grid_x": 31, + "grid_y": 60, + "segment": "SEG_CLBLM_L_X10Y142", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y143": { + "bits": {}, + "grid_x": 31, + "grid_y": 59, + "segment": "SEG_CLBLM_L_X10Y143", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y144": { + "bits": {}, + "grid_x": 31, + "grid_y": 58, + "segment": "SEG_CLBLM_L_X10Y144", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y145": { + "bits": {}, + "grid_x": 31, + "grid_y": 57, + "segment": "SEG_CLBLM_L_X10Y145", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y146": { + "bits": {}, + "grid_x": 31, + "grid_y": 56, + "segment": "SEG_CLBLM_L_X10Y146", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y147": { + "bits": {}, + "grid_x": 31, + "grid_y": 55, + "segment": "SEG_CLBLM_L_X10Y147", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y148": { + "bits": {}, + "grid_x": 31, + "grid_y": 54, + "segment": "SEG_CLBLM_L_X10Y148", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y149": { + "bits": {}, + "grid_x": 31, + "grid_y": 53, + "segment": "SEG_CLBLM_L_X10Y149", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y15": { + "bits": {}, + "grid_x": 31, + "grid_y": 192, + "segment": "SEG_CLBLM_L_X10Y15", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y150": { + "bits": {}, + "grid_x": 31, + "grid_y": 51, + "segment": "SEG_CLBLM_L_X10Y150", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y151": { + "bits": {}, + "grid_x": 31, + "grid_y": 50, + "segment": "SEG_CLBLM_L_X10Y151", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y152": { + "bits": {}, + "grid_x": 31, + "grid_y": 49, + "segment": "SEG_CLBLM_L_X10Y152", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y153": { + "bits": {}, + "grid_x": 31, + "grid_y": 48, + "segment": "SEG_CLBLM_L_X10Y153", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y154": { + "bits": {}, + "grid_x": 31, + "grid_y": 47, + "segment": "SEG_CLBLM_L_X10Y154", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y155": { + "bits": {}, + "grid_x": 31, + "grid_y": 46, + "segment": "SEG_CLBLM_L_X10Y155", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y156": { + "bits": {}, + "grid_x": 31, + "grid_y": 45, + "segment": "SEG_CLBLM_L_X10Y156", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y157": { + "bits": {}, + "grid_x": 31, + "grid_y": 44, + "segment": "SEG_CLBLM_L_X10Y157", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y158": { + "bits": {}, + "grid_x": 31, + "grid_y": 43, + "segment": "SEG_CLBLM_L_X10Y158", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y159": { + "bits": {}, + "grid_x": 31, + "grid_y": 42, + "segment": "SEG_CLBLM_L_X10Y159", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y16": { + "bits": {}, + "grid_x": 31, + "grid_y": 191, + "segment": "SEG_CLBLM_L_X10Y16", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y160": { + "bits": {}, + "grid_x": 31, + "grid_y": 41, + "segment": "SEG_CLBLM_L_X10Y160", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y161": { + "bits": {}, + "grid_x": 31, + "grid_y": 40, + "segment": "SEG_CLBLM_L_X10Y161", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y162": { + "bits": {}, + "grid_x": 31, + "grid_y": 39, + "segment": "SEG_CLBLM_L_X10Y162", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y163": { + "bits": {}, + "grid_x": 31, + "grid_y": 38, + "segment": "SEG_CLBLM_L_X10Y163", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y164": { + "bits": {}, + "grid_x": 31, + "grid_y": 37, + "segment": "SEG_CLBLM_L_X10Y164", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y165": { + "bits": {}, + "grid_x": 31, + "grid_y": 36, + "segment": "SEG_CLBLM_L_X10Y165", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y166": { + "bits": {}, + "grid_x": 31, + "grid_y": 35, + "segment": "SEG_CLBLM_L_X10Y166", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y167": { + "bits": {}, + "grid_x": 31, + "grid_y": 34, + "segment": "SEG_CLBLM_L_X10Y167", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y168": { + "bits": {}, + "grid_x": 31, + "grid_y": 33, + "segment": "SEG_CLBLM_L_X10Y168", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y169": { + "bits": {}, + "grid_x": 31, + "grid_y": 32, + "segment": "SEG_CLBLM_L_X10Y169", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y17": { + "bits": {}, + "grid_x": 31, + "grid_y": 190, + "segment": "SEG_CLBLM_L_X10Y17", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y170": { + "bits": {}, + "grid_x": 31, + "grid_y": 31, + "segment": "SEG_CLBLM_L_X10Y170", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y171": { + "bits": {}, + "grid_x": 31, + "grid_y": 30, + "segment": "SEG_CLBLM_L_X10Y171", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y172": { + "bits": {}, + "grid_x": 31, + "grid_y": 29, + "segment": "SEG_CLBLM_L_X10Y172", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y173": { + "bits": {}, + "grid_x": 31, + "grid_y": 28, + "segment": "SEG_CLBLM_L_X10Y173", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y174": { + "bits": {}, + "grid_x": 31, + "grid_y": 27, + "segment": "SEG_CLBLM_L_X10Y174", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y175": { + "bits": {}, + "grid_x": 31, + "grid_y": 25, + "segment": "SEG_CLBLM_L_X10Y175", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y176": { + "bits": {}, + "grid_x": 31, + "grid_y": 24, + "segment": "SEG_CLBLM_L_X10Y176", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y177": { + "bits": {}, + "grid_x": 31, + "grid_y": 23, + "segment": "SEG_CLBLM_L_X10Y177", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y178": { + "bits": {}, + "grid_x": 31, + "grid_y": 22, + "segment": "SEG_CLBLM_L_X10Y178", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y179": { + "bits": {}, + "grid_x": 31, + "grid_y": 21, + "segment": "SEG_CLBLM_L_X10Y179", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y18": { + "bits": {}, + "grid_x": 31, + "grid_y": 189, + "segment": "SEG_CLBLM_L_X10Y18", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y180": { + "bits": {}, + "grid_x": 31, + "grid_y": 20, + "segment": "SEG_CLBLM_L_X10Y180", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y181": { + "bits": {}, + "grid_x": 31, + "grid_y": 19, + "segment": "SEG_CLBLM_L_X10Y181", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y182": { + "bits": {}, + "grid_x": 31, + "grid_y": 18, + "segment": "SEG_CLBLM_L_X10Y182", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y183": { + "bits": {}, + "grid_x": 31, + "grid_y": 17, + "segment": "SEG_CLBLM_L_X10Y183", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y184": { + "bits": {}, + "grid_x": 31, + "grid_y": 16, + "segment": "SEG_CLBLM_L_X10Y184", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y185": { + "bits": {}, + "grid_x": 31, + "grid_y": 15, + "segment": "SEG_CLBLM_L_X10Y185", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y186": { + "bits": {}, + "grid_x": 31, + "grid_y": 14, + "segment": "SEG_CLBLM_L_X10Y186", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y187": { + "bits": {}, + "grid_x": 31, + "grid_y": 13, + "segment": "SEG_CLBLM_L_X10Y187", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y188": { + "bits": {}, + "grid_x": 31, + "grid_y": 12, + "segment": "SEG_CLBLM_L_X10Y188", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y189": { + "bits": {}, + "grid_x": 31, + "grid_y": 11, + "segment": "SEG_CLBLM_L_X10Y189", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y19": { + "bits": {}, + "grid_x": 31, + "grid_y": 188, + "segment": "SEG_CLBLM_L_X10Y19", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y190": { + "bits": {}, + "grid_x": 31, + "grid_y": 10, + "segment": "SEG_CLBLM_L_X10Y190", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y191": { + "bits": {}, + "grid_x": 31, + "grid_y": 9, + "segment": "SEG_CLBLM_L_X10Y191", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y192": { + "bits": {}, + "grid_x": 31, + "grid_y": 8, + "segment": "SEG_CLBLM_L_X10Y192", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y193": { + "bits": {}, + "grid_x": 31, + "grid_y": 7, + "segment": "SEG_CLBLM_L_X10Y193", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y194": { + "bits": {}, + "grid_x": 31, + "grid_y": 6, + "segment": "SEG_CLBLM_L_X10Y194", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y195": { + "bits": {}, + "grid_x": 31, + "grid_y": 5, + "segment": "SEG_CLBLM_L_X10Y195", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y196": { + "bits": {}, + "grid_x": 31, + "grid_y": 4, + "segment": "SEG_CLBLM_L_X10Y196", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y197": { + "bits": {}, + "grid_x": 31, + "grid_y": 3, + "segment": "SEG_CLBLM_L_X10Y197", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y198": { + "bits": {}, + "grid_x": 31, + "grid_y": 2, + "segment": "SEG_CLBLM_L_X10Y198", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y199": { + "bits": {}, + "grid_x": 31, + "grid_y": 1, + "segment": "SEG_CLBLM_L_X10Y199", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y2": { + "bits": {}, + "grid_x": 31, + "grid_y": 205, + "segment": "SEG_CLBLM_L_X10Y2", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y20": { + "bits": {}, + "grid_x": 31, + "grid_y": 187, + "segment": "SEG_CLBLM_L_X10Y20", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y21": { + "bits": {}, + "grid_x": 31, + "grid_y": 186, + "segment": "SEG_CLBLM_L_X10Y21", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y22": { + "bits": {}, + "grid_x": 31, + "grid_y": 185, + "segment": "SEG_CLBLM_L_X10Y22", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y23": { + "bits": {}, + "grid_x": 31, + "grid_y": 184, + "segment": "SEG_CLBLM_L_X10Y23", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y24": { + "bits": {}, + "grid_x": 31, + "grid_y": 183, + "segment": "SEG_CLBLM_L_X10Y24", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y25": { + "bits": {}, + "grid_x": 31, + "grid_y": 181, + "segment": "SEG_CLBLM_L_X10Y25", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y26": { + "bits": {}, + "grid_x": 31, + "grid_y": 180, + "segment": "SEG_CLBLM_L_X10Y26", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y27": { + "bits": {}, + "grid_x": 31, + "grid_y": 179, + "segment": "SEG_CLBLM_L_X10Y27", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y28": { + "bits": {}, + "grid_x": 31, + "grid_y": 178, + "segment": "SEG_CLBLM_L_X10Y28", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y29": { + "bits": {}, + "grid_x": 31, + "grid_y": 177, + "segment": "SEG_CLBLM_L_X10Y29", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y3": { + "bits": {}, + "grid_x": 31, + "grid_y": 204, + "segment": "SEG_CLBLM_L_X10Y3", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y30": { + "bits": {}, + "grid_x": 31, + "grid_y": 176, + "segment": "SEG_CLBLM_L_X10Y30", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y31": { + "bits": {}, + "grid_x": 31, + "grid_y": 175, + "segment": "SEG_CLBLM_L_X10Y31", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y32": { + "bits": {}, + "grid_x": 31, + "grid_y": 174, + "segment": "SEG_CLBLM_L_X10Y32", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y33": { + "bits": {}, + "grid_x": 31, + "grid_y": 173, + "segment": "SEG_CLBLM_L_X10Y33", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y34": { + "bits": {}, + "grid_x": 31, + "grid_y": 172, + "segment": "SEG_CLBLM_L_X10Y34", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y35": { + "bits": {}, + "grid_x": 31, + "grid_y": 171, + "segment": "SEG_CLBLM_L_X10Y35", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y36": { + "bits": {}, + "grid_x": 31, + "grid_y": 170, + "segment": "SEG_CLBLM_L_X10Y36", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y37": { + "bits": {}, + "grid_x": 31, + "grid_y": 169, + "segment": "SEG_CLBLM_L_X10Y37", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y38": { + "bits": {}, + "grid_x": 31, + "grid_y": 168, + "segment": "SEG_CLBLM_L_X10Y38", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y39": { + "bits": {}, + "grid_x": 31, + "grid_y": 167, + "segment": "SEG_CLBLM_L_X10Y39", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y4": { + "bits": {}, + "grid_x": 31, + "grid_y": 203, + "segment": "SEG_CLBLM_L_X10Y4", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y40": { + "bits": {}, + "grid_x": 31, + "grid_y": 166, + "segment": "SEG_CLBLM_L_X10Y40", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y41": { + "bits": {}, + "grid_x": 31, + "grid_y": 165, + "segment": "SEG_CLBLM_L_X10Y41", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y42": { + "bits": {}, + "grid_x": 31, + "grid_y": 164, + "segment": "SEG_CLBLM_L_X10Y42", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y43": { + "bits": {}, + "grid_x": 31, + "grid_y": 163, + "segment": "SEG_CLBLM_L_X10Y43", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y44": { + "bits": {}, + "grid_x": 31, + "grid_y": 162, + "segment": "SEG_CLBLM_L_X10Y44", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y45": { + "bits": {}, + "grid_x": 31, + "grid_y": 161, + "segment": "SEG_CLBLM_L_X10Y45", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y46": { + "bits": {}, + "grid_x": 31, + "grid_y": 160, + "segment": "SEG_CLBLM_L_X10Y46", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y47": { + "bits": {}, + "grid_x": 31, + "grid_y": 159, + "segment": "SEG_CLBLM_L_X10Y47", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y48": { + "bits": {}, + "grid_x": 31, + "grid_y": 158, + "segment": "SEG_CLBLM_L_X10Y48", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y49": { + "bits": {}, + "grid_x": 31, + "grid_y": 157, + "segment": "SEG_CLBLM_L_X10Y49", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y5": { + "bits": {}, + "grid_x": 31, + "grid_y": 202, + "segment": "SEG_CLBLM_L_X10Y5", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 155, + "segment": "SEG_CLBLM_L_X10Y50", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 154, + "segment": "SEG_CLBLM_L_X10Y51", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 153, + "segment": "SEG_CLBLM_L_X10Y52", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 152, + "segment": "SEG_CLBLM_L_X10Y53", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 151, + "segment": "SEG_CLBLM_L_X10Y54", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 150, + "segment": "SEG_CLBLM_L_X10Y55", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 149, + "segment": "SEG_CLBLM_L_X10Y56", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 148, + "segment": "SEG_CLBLM_L_X10Y57", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 147, + "segment": "SEG_CLBLM_L_X10Y58", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 146, + "segment": "SEG_CLBLM_L_X10Y59", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y6": { + "bits": {}, + "grid_x": 31, + "grid_y": 201, + "segment": "SEG_CLBLM_L_X10Y6", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 145, + "segment": "SEG_CLBLM_L_X10Y60", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 144, + "segment": "SEG_CLBLM_L_X10Y61", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 143, + "segment": "SEG_CLBLM_L_X10Y62", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 142, + "segment": "SEG_CLBLM_L_X10Y63", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 141, + "segment": "SEG_CLBLM_L_X10Y64", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 140, + "segment": "SEG_CLBLM_L_X10Y65", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 139, + "segment": "SEG_CLBLM_L_X10Y66", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 138, + "segment": "SEG_CLBLM_L_X10Y67", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 137, + "segment": "SEG_CLBLM_L_X10Y68", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 136, + "segment": "SEG_CLBLM_L_X10Y69", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y7": { + "bits": {}, + "grid_x": 31, + "grid_y": 200, + "segment": "SEG_CLBLM_L_X10Y7", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 135, + "segment": "SEG_CLBLM_L_X10Y70", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 134, + "segment": "SEG_CLBLM_L_X10Y71", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 133, + "segment": "SEG_CLBLM_L_X10Y72", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 132, + "segment": "SEG_CLBLM_L_X10Y73", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 131, + "segment": "SEG_CLBLM_L_X10Y74", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 129, + "segment": "SEG_CLBLM_L_X10Y75", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 128, + "segment": "SEG_CLBLM_L_X10Y76", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 127, + "segment": "SEG_CLBLM_L_X10Y77", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 126, + "segment": "SEG_CLBLM_L_X10Y78", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 125, + "segment": "SEG_CLBLM_L_X10Y79", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y8": { + "bits": {}, + "grid_x": 31, + "grid_y": 199, + "segment": "SEG_CLBLM_L_X10Y8", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 124, + "segment": "SEG_CLBLM_L_X10Y80", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 123, + "segment": "SEG_CLBLM_L_X10Y81", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 122, + "segment": "SEG_CLBLM_L_X10Y82", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 121, + "segment": "SEG_CLBLM_L_X10Y83", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 120, + "segment": "SEG_CLBLM_L_X10Y84", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 119, + "segment": "SEG_CLBLM_L_X10Y85", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 118, + "segment": "SEG_CLBLM_L_X10Y86", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 117, + "segment": "SEG_CLBLM_L_X10Y87", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 116, + "segment": "SEG_CLBLM_L_X10Y88", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 115, + "segment": "SEG_CLBLM_L_X10Y89", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y9": { + "bits": {}, + "grid_x": 31, + "grid_y": 198, + "segment": "SEG_CLBLM_L_X10Y9", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 114, + "segment": "SEG_CLBLM_L_X10Y90", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 113, + "segment": "SEG_CLBLM_L_X10Y91", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 112, + "segment": "SEG_CLBLM_L_X10Y92", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 111, + "segment": "SEG_CLBLM_L_X10Y93", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 110, + "segment": "SEG_CLBLM_L_X10Y94", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 109, + "segment": "SEG_CLBLM_L_X10Y95", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 108, + "segment": "SEG_CLBLM_L_X10Y96", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 107, + "segment": "SEG_CLBLM_L_X10Y97", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 106, + "segment": "SEG_CLBLM_L_X10Y98", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X10Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400500", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 31, + "grid_y": 105, + "segment": "SEG_CLBLM_L_X10Y99", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X11Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y0": { + "bits": {}, + "grid_x": 35, + "grid_y": 207, + "segment": "SEG_CLBLM_L_X12Y0", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y1": { + "bits": {}, + "grid_x": 35, + "grid_y": 206, + "segment": "SEG_CLBLM_L_X12Y1", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y10": { + "bits": {}, + "grid_x": 35, + "grid_y": 197, + "segment": "SEG_CLBLM_L_X12Y10", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y100": { + "bits": {}, + "grid_x": 35, + "grid_y": 103, + "segment": "SEG_CLBLM_L_X12Y100", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y101": { + "bits": {}, + "grid_x": 35, + "grid_y": 102, + "segment": "SEG_CLBLM_L_X12Y101", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y102": { + "bits": {}, + "grid_x": 35, + "grid_y": 101, + "segment": "SEG_CLBLM_L_X12Y102", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y103": { + "bits": {}, + "grid_x": 35, + "grid_y": 100, + "segment": "SEG_CLBLM_L_X12Y103", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y104": { + "bits": {}, + "grid_x": 35, + "grid_y": 99, + "segment": "SEG_CLBLM_L_X12Y104", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y105": { + "bits": {}, + "grid_x": 35, + "grid_y": 98, + "segment": "SEG_CLBLM_L_X12Y105", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y106": { + "bits": {}, + "grid_x": 35, + "grid_y": 97, + "segment": "SEG_CLBLM_L_X12Y106", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y107": { + "bits": {}, + "grid_x": 35, + "grid_y": 96, + "segment": "SEG_CLBLM_L_X12Y107", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y108": { + "bits": {}, + "grid_x": 35, + "grid_y": 95, + "segment": "SEG_CLBLM_L_X12Y108", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y109": { + "bits": {}, + "grid_x": 35, + "grid_y": 94, + "segment": "SEG_CLBLM_L_X12Y109", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y11": { + "bits": {}, + "grid_x": 35, + "grid_y": 196, + "segment": "SEG_CLBLM_L_X12Y11", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y110": { + "bits": {}, + "grid_x": 35, + "grid_y": 93, + "segment": "SEG_CLBLM_L_X12Y110", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y111": { + "bits": {}, + "grid_x": 35, + "grid_y": 92, + "segment": "SEG_CLBLM_L_X12Y111", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y112": { + "bits": {}, + "grid_x": 35, + "grid_y": 91, + "segment": "SEG_CLBLM_L_X12Y112", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y113": { + "bits": {}, + "grid_x": 35, + "grid_y": 90, + "segment": "SEG_CLBLM_L_X12Y113", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y114": { + "bits": {}, + "grid_x": 35, + "grid_y": 89, + "segment": "SEG_CLBLM_L_X12Y114", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y115": { + "bits": {}, + "grid_x": 35, + "grid_y": 88, + "segment": "SEG_CLBLM_L_X12Y115", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y116": { + "bits": {}, + "grid_x": 35, + "grid_y": 87, + "segment": "SEG_CLBLM_L_X12Y116", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y117": { + "bits": {}, + "grid_x": 35, + "grid_y": 86, + "segment": "SEG_CLBLM_L_X12Y117", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y118": { + "bits": {}, + "grid_x": 35, + "grid_y": 85, + "segment": "SEG_CLBLM_L_X12Y118", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y119": { + "bits": {}, + "grid_x": 35, + "grid_y": 84, + "segment": "SEG_CLBLM_L_X12Y119", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y12": { + "bits": {}, + "grid_x": 35, + "grid_y": 195, + "segment": "SEG_CLBLM_L_X12Y12", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y120": { + "bits": {}, + "grid_x": 35, + "grid_y": 83, + "segment": "SEG_CLBLM_L_X12Y120", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y121": { + "bits": {}, + "grid_x": 35, + "grid_y": 82, + "segment": "SEG_CLBLM_L_X12Y121", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y122": { + "bits": {}, + "grid_x": 35, + "grid_y": 81, + "segment": "SEG_CLBLM_L_X12Y122", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y123": { + "bits": {}, + "grid_x": 35, + "grid_y": 80, + "segment": "SEG_CLBLM_L_X12Y123", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y124": { + "bits": {}, + "grid_x": 35, + "grid_y": 79, + "segment": "SEG_CLBLM_L_X12Y124", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y125": { + "bits": {}, + "grid_x": 35, + "grid_y": 77, + "segment": "SEG_CLBLM_L_X12Y125", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y126": { + "bits": {}, + "grid_x": 35, + "grid_y": 76, + "segment": "SEG_CLBLM_L_X12Y126", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y127": { + "bits": {}, + "grid_x": 35, + "grid_y": 75, + "segment": "SEG_CLBLM_L_X12Y127", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y128": { + "bits": {}, + "grid_x": 35, + "grid_y": 74, + "segment": "SEG_CLBLM_L_X12Y128", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y129": { + "bits": {}, + "grid_x": 35, + "grid_y": 73, + "segment": "SEG_CLBLM_L_X12Y129", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y13": { + "bits": {}, + "grid_x": 35, + "grid_y": 194, + "segment": "SEG_CLBLM_L_X12Y13", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y130": { + "bits": {}, + "grid_x": 35, + "grid_y": 72, + "segment": "SEG_CLBLM_L_X12Y130", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y131": { + "bits": {}, + "grid_x": 35, + "grid_y": 71, + "segment": "SEG_CLBLM_L_X12Y131", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y132": { + "bits": {}, + "grid_x": 35, + "grid_y": 70, + "segment": "SEG_CLBLM_L_X12Y132", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y133": { + "bits": {}, + "grid_x": 35, + "grid_y": 69, + "segment": "SEG_CLBLM_L_X12Y133", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y134": { + "bits": {}, + "grid_x": 35, + "grid_y": 68, + "segment": "SEG_CLBLM_L_X12Y134", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y135": { + "bits": {}, + "grid_x": 35, + "grid_y": 67, + "segment": "SEG_CLBLM_L_X12Y135", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y136": { + "bits": {}, + "grid_x": 35, + "grid_y": 66, + "segment": "SEG_CLBLM_L_X12Y136", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y137": { + "bits": {}, + "grid_x": 35, + "grid_y": 65, + "segment": "SEG_CLBLM_L_X12Y137", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y138": { + "bits": {}, + "grid_x": 35, + "grid_y": 64, + "segment": "SEG_CLBLM_L_X12Y138", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y139": { + "bits": {}, + "grid_x": 35, + "grid_y": 63, + "segment": "SEG_CLBLM_L_X12Y139", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y14": { + "bits": {}, + "grid_x": 35, + "grid_y": 193, + "segment": "SEG_CLBLM_L_X12Y14", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y140": { + "bits": {}, + "grid_x": 35, + "grid_y": 62, + "segment": "SEG_CLBLM_L_X12Y140", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y141": { + "bits": {}, + "grid_x": 35, + "grid_y": 61, + "segment": "SEG_CLBLM_L_X12Y141", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y142": { + "bits": {}, + "grid_x": 35, + "grid_y": 60, + "segment": "SEG_CLBLM_L_X12Y142", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y143": { + "bits": {}, + "grid_x": 35, + "grid_y": 59, + "segment": "SEG_CLBLM_L_X12Y143", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y144": { + "bits": {}, + "grid_x": 35, + "grid_y": 58, + "segment": "SEG_CLBLM_L_X12Y144", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y145": { + "bits": {}, + "grid_x": 35, + "grid_y": 57, + "segment": "SEG_CLBLM_L_X12Y145", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y146": { + "bits": {}, + "grid_x": 35, + "grid_y": 56, + "segment": "SEG_CLBLM_L_X12Y146", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y147": { + "bits": {}, + "grid_x": 35, + "grid_y": 55, + "segment": "SEG_CLBLM_L_X12Y147", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y148": { + "bits": {}, + "grid_x": 35, + "grid_y": 54, + "segment": "SEG_CLBLM_L_X12Y148", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y149": { + "bits": {}, + "grid_x": 35, + "grid_y": 53, + "segment": "SEG_CLBLM_L_X12Y149", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y15": { + "bits": {}, + "grid_x": 35, + "grid_y": 192, + "segment": "SEG_CLBLM_L_X12Y15", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y150": { + "bits": {}, + "grid_x": 35, + "grid_y": 51, + "segment": "SEG_CLBLM_L_X12Y150", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y151": { + "bits": {}, + "grid_x": 35, + "grid_y": 50, + "segment": "SEG_CLBLM_L_X12Y151", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y152": { + "bits": {}, + "grid_x": 35, + "grid_y": 49, + "segment": "SEG_CLBLM_L_X12Y152", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y153": { + "bits": {}, + "grid_x": 35, + "grid_y": 48, + "segment": "SEG_CLBLM_L_X12Y153", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y154": { + "bits": {}, + "grid_x": 35, + "grid_y": 47, + "segment": "SEG_CLBLM_L_X12Y154", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y155": { + "bits": {}, + "grid_x": 35, + "grid_y": 46, + "segment": "SEG_CLBLM_L_X12Y155", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y156": { + "bits": {}, + "grid_x": 35, + "grid_y": 45, + "segment": "SEG_CLBLM_L_X12Y156", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y157": { + "bits": {}, + "grid_x": 35, + "grid_y": 44, + "segment": "SEG_CLBLM_L_X12Y157", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y158": { + "bits": {}, + "grid_x": 35, + "grid_y": 43, + "segment": "SEG_CLBLM_L_X12Y158", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y159": { + "bits": {}, + "grid_x": 35, + "grid_y": 42, + "segment": "SEG_CLBLM_L_X12Y159", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y16": { + "bits": {}, + "grid_x": 35, + "grid_y": 191, + "segment": "SEG_CLBLM_L_X12Y16", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y160": { + "bits": {}, + "grid_x": 35, + "grid_y": 41, + "segment": "SEG_CLBLM_L_X12Y160", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y161": { + "bits": {}, + "grid_x": 35, + "grid_y": 40, + "segment": "SEG_CLBLM_L_X12Y161", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y162": { + "bits": {}, + "grid_x": 35, + "grid_y": 39, + "segment": "SEG_CLBLM_L_X12Y162", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y163": { + "bits": {}, + "grid_x": 35, + "grid_y": 38, + "segment": "SEG_CLBLM_L_X12Y163", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y164": { + "bits": {}, + "grid_x": 35, + "grid_y": 37, + "segment": "SEG_CLBLM_L_X12Y164", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y165": { + "bits": {}, + "grid_x": 35, + "grid_y": 36, + "segment": "SEG_CLBLM_L_X12Y165", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y166": { + "bits": {}, + "grid_x": 35, + "grid_y": 35, + "segment": "SEG_CLBLM_L_X12Y166", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y167": { + "bits": {}, + "grid_x": 35, + "grid_y": 34, + "segment": "SEG_CLBLM_L_X12Y167", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y168": { + "bits": {}, + "grid_x": 35, + "grid_y": 33, + "segment": "SEG_CLBLM_L_X12Y168", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y169": { + "bits": {}, + "grid_x": 35, + "grid_y": 32, + "segment": "SEG_CLBLM_L_X12Y169", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y17": { + "bits": {}, + "grid_x": 35, + "grid_y": 190, + "segment": "SEG_CLBLM_L_X12Y17", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y170": { + "bits": {}, + "grid_x": 35, + "grid_y": 31, + "segment": "SEG_CLBLM_L_X12Y170", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y171": { + "bits": {}, + "grid_x": 35, + "grid_y": 30, + "segment": "SEG_CLBLM_L_X12Y171", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y172": { + "bits": {}, + "grid_x": 35, + "grid_y": 29, + "segment": "SEG_CLBLM_L_X12Y172", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y173": { + "bits": {}, + "grid_x": 35, + "grid_y": 28, + "segment": "SEG_CLBLM_L_X12Y173", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y174": { + "bits": {}, + "grid_x": 35, + "grid_y": 27, + "segment": "SEG_CLBLM_L_X12Y174", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y175": { + "bits": {}, + "grid_x": 35, + "grid_y": 25, + "segment": "SEG_CLBLM_L_X12Y175", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y176": { + "bits": {}, + "grid_x": 35, + "grid_y": 24, + "segment": "SEG_CLBLM_L_X12Y176", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y177": { + "bits": {}, + "grid_x": 35, + "grid_y": 23, + "segment": "SEG_CLBLM_L_X12Y177", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y178": { + "bits": {}, + "grid_x": 35, + "grid_y": 22, + "segment": "SEG_CLBLM_L_X12Y178", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y179": { + "bits": {}, + "grid_x": 35, + "grid_y": 21, + "segment": "SEG_CLBLM_L_X12Y179", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y18": { + "bits": {}, + "grid_x": 35, + "grid_y": 189, + "segment": "SEG_CLBLM_L_X12Y18", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y180": { + "bits": {}, + "grid_x": 35, + "grid_y": 20, + "segment": "SEG_CLBLM_L_X12Y180", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y181": { + "bits": {}, + "grid_x": 35, + "grid_y": 19, + "segment": "SEG_CLBLM_L_X12Y181", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y182": { + "bits": {}, + "grid_x": 35, + "grid_y": 18, + "segment": "SEG_CLBLM_L_X12Y182", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y183": { + "bits": {}, + "grid_x": 35, + "grid_y": 17, + "segment": "SEG_CLBLM_L_X12Y183", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y184": { + "bits": {}, + "grid_x": 35, + "grid_y": 16, + "segment": "SEG_CLBLM_L_X12Y184", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y185": { + "bits": {}, + "grid_x": 35, + "grid_y": 15, + "segment": "SEG_CLBLM_L_X12Y185", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y186": { + "bits": {}, + "grid_x": 35, + "grid_y": 14, + "segment": "SEG_CLBLM_L_X12Y186", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y187": { + "bits": {}, + "grid_x": 35, + "grid_y": 13, + "segment": "SEG_CLBLM_L_X12Y187", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y188": { + "bits": {}, + "grid_x": 35, + "grid_y": 12, + "segment": "SEG_CLBLM_L_X12Y188", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y189": { + "bits": {}, + "grid_x": 35, + "grid_y": 11, + "segment": "SEG_CLBLM_L_X12Y189", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y19": { + "bits": {}, + "grid_x": 35, + "grid_y": 188, + "segment": "SEG_CLBLM_L_X12Y19", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y190": { + "bits": {}, + "grid_x": 35, + "grid_y": 10, + "segment": "SEG_CLBLM_L_X12Y190", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y191": { + "bits": {}, + "grid_x": 35, + "grid_y": 9, + "segment": "SEG_CLBLM_L_X12Y191", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y192": { + "bits": {}, + "grid_x": 35, + "grid_y": 8, + "segment": "SEG_CLBLM_L_X12Y192", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y193": { + "bits": {}, + "grid_x": 35, + "grid_y": 7, + "segment": "SEG_CLBLM_L_X12Y193", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y194": { + "bits": {}, + "grid_x": 35, + "grid_y": 6, + "segment": "SEG_CLBLM_L_X12Y194", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y195": { + "bits": {}, + "grid_x": 35, + "grid_y": 5, + "segment": "SEG_CLBLM_L_X12Y195", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y196": { + "bits": {}, + "grid_x": 35, + "grid_y": 4, + "segment": "SEG_CLBLM_L_X12Y196", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y197": { + "bits": {}, + "grid_x": 35, + "grid_y": 3, + "segment": "SEG_CLBLM_L_X12Y197", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y198": { + "bits": {}, + "grid_x": 35, + "grid_y": 2, + "segment": "SEG_CLBLM_L_X12Y198", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y199": { + "bits": {}, + "grid_x": 35, + "grid_y": 1, + "segment": "SEG_CLBLM_L_X12Y199", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y2": { + "bits": {}, + "grid_x": 35, + "grid_y": 205, + "segment": "SEG_CLBLM_L_X12Y2", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y20": { + "bits": {}, + "grid_x": 35, + "grid_y": 187, + "segment": "SEG_CLBLM_L_X12Y20", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y21": { + "bits": {}, + "grid_x": 35, + "grid_y": 186, + "segment": "SEG_CLBLM_L_X12Y21", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y22": { + "bits": {}, + "grid_x": 35, + "grid_y": 185, + "segment": "SEG_CLBLM_L_X12Y22", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y23": { + "bits": {}, + "grid_x": 35, + "grid_y": 184, + "segment": "SEG_CLBLM_L_X12Y23", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y24": { + "bits": {}, + "grid_x": 35, + "grid_y": 183, + "segment": "SEG_CLBLM_L_X12Y24", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y25": { + "bits": {}, + "grid_x": 35, + "grid_y": 181, + "segment": "SEG_CLBLM_L_X12Y25", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y26": { + "bits": {}, + "grid_x": 35, + "grid_y": 180, + "segment": "SEG_CLBLM_L_X12Y26", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y27": { + "bits": {}, + "grid_x": 35, + "grid_y": 179, + "segment": "SEG_CLBLM_L_X12Y27", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y28": { + "bits": {}, + "grid_x": 35, + "grid_y": 178, + "segment": "SEG_CLBLM_L_X12Y28", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y29": { + "bits": {}, + "grid_x": 35, + "grid_y": 177, + "segment": "SEG_CLBLM_L_X12Y29", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y3": { + "bits": {}, + "grid_x": 35, + "grid_y": 204, + "segment": "SEG_CLBLM_L_X12Y3", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y30": { + "bits": {}, + "grid_x": 35, + "grid_y": 176, + "segment": "SEG_CLBLM_L_X12Y30", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y31": { + "bits": {}, + "grid_x": 35, + "grid_y": 175, + "segment": "SEG_CLBLM_L_X12Y31", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y32": { + "bits": {}, + "grid_x": 35, + "grid_y": 174, + "segment": "SEG_CLBLM_L_X12Y32", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y33": { + "bits": {}, + "grid_x": 35, + "grid_y": 173, + "segment": "SEG_CLBLM_L_X12Y33", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y34": { + "bits": {}, + "grid_x": 35, + "grid_y": 172, + "segment": "SEG_CLBLM_L_X12Y34", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y35": { + "bits": {}, + "grid_x": 35, + "grid_y": 171, + "segment": "SEG_CLBLM_L_X12Y35", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y36": { + "bits": {}, + "grid_x": 35, + "grid_y": 170, + "segment": "SEG_CLBLM_L_X12Y36", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y37": { + "bits": {}, + "grid_x": 35, + "grid_y": 169, + "segment": "SEG_CLBLM_L_X12Y37", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y38": { + "bits": {}, + "grid_x": 35, + "grid_y": 168, + "segment": "SEG_CLBLM_L_X12Y38", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y39": { + "bits": {}, + "grid_x": 35, + "grid_y": 167, + "segment": "SEG_CLBLM_L_X12Y39", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y4": { + "bits": {}, + "grid_x": 35, + "grid_y": 203, + "segment": "SEG_CLBLM_L_X12Y4", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y40": { + "bits": {}, + "grid_x": 35, + "grid_y": 166, + "segment": "SEG_CLBLM_L_X12Y40", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y41": { + "bits": {}, + "grid_x": 35, + "grid_y": 165, + "segment": "SEG_CLBLM_L_X12Y41", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y42": { + "bits": {}, + "grid_x": 35, + "grid_y": 164, + "segment": "SEG_CLBLM_L_X12Y42", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y43": { + "bits": {}, + "grid_x": 35, + "grid_y": 163, + "segment": "SEG_CLBLM_L_X12Y43", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y44": { + "bits": {}, + "grid_x": 35, + "grid_y": 162, + "segment": "SEG_CLBLM_L_X12Y44", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y45": { + "bits": {}, + "grid_x": 35, + "grid_y": 161, + "segment": "SEG_CLBLM_L_X12Y45", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y46": { + "bits": {}, + "grid_x": 35, + "grid_y": 160, + "segment": "SEG_CLBLM_L_X12Y46", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y47": { + "bits": {}, + "grid_x": 35, + "grid_y": 159, + "segment": "SEG_CLBLM_L_X12Y47", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y48": { + "bits": {}, + "grid_x": 35, + "grid_y": 158, + "segment": "SEG_CLBLM_L_X12Y48", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y49": { + "bits": {}, + "grid_x": 35, + "grid_y": 157, + "segment": "SEG_CLBLM_L_X12Y49", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y5": { + "bits": {}, + "grid_x": 35, + "grid_y": 202, + "segment": "SEG_CLBLM_L_X12Y5", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 155, + "segment": "SEG_CLBLM_L_X12Y50", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 154, + "segment": "SEG_CLBLM_L_X12Y51", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 153, + "segment": "SEG_CLBLM_L_X12Y52", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 152, + "segment": "SEG_CLBLM_L_X12Y53", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 151, + "segment": "SEG_CLBLM_L_X12Y54", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 150, + "segment": "SEG_CLBLM_L_X12Y55", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 149, + "segment": "SEG_CLBLM_L_X12Y56", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 148, + "segment": "SEG_CLBLM_L_X12Y57", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 147, + "segment": "SEG_CLBLM_L_X12Y58", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 146, + "segment": "SEG_CLBLM_L_X12Y59", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y6": { + "bits": {}, + "grid_x": 35, + "grid_y": 201, + "segment": "SEG_CLBLM_L_X12Y6", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 145, + "segment": "SEG_CLBLM_L_X12Y60", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 144, + "segment": "SEG_CLBLM_L_X12Y61", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 143, + "segment": "SEG_CLBLM_L_X12Y62", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 142, + "segment": "SEG_CLBLM_L_X12Y63", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 141, + "segment": "SEG_CLBLM_L_X12Y64", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 140, + "segment": "SEG_CLBLM_L_X12Y65", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 139, + "segment": "SEG_CLBLM_L_X12Y66", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 138, + "segment": "SEG_CLBLM_L_X12Y67", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 137, + "segment": "SEG_CLBLM_L_X12Y68", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 136, + "segment": "SEG_CLBLM_L_X12Y69", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y7": { + "bits": {}, + "grid_x": 35, + "grid_y": 200, + "segment": "SEG_CLBLM_L_X12Y7", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 135, + "segment": "SEG_CLBLM_L_X12Y70", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 134, + "segment": "SEG_CLBLM_L_X12Y71", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 133, + "segment": "SEG_CLBLM_L_X12Y72", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 132, + "segment": "SEG_CLBLM_L_X12Y73", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 131, + "segment": "SEG_CLBLM_L_X12Y74", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 129, + "segment": "SEG_CLBLM_L_X12Y75", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 128, + "segment": "SEG_CLBLM_L_X12Y76", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 127, + "segment": "SEG_CLBLM_L_X12Y77", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 126, + "segment": "SEG_CLBLM_L_X12Y78", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 125, + "segment": "SEG_CLBLM_L_X12Y79", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y8": { + "bits": {}, + "grid_x": 35, + "grid_y": 199, + "segment": "SEG_CLBLM_L_X12Y8", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 124, + "segment": "SEG_CLBLM_L_X12Y80", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 123, + "segment": "SEG_CLBLM_L_X12Y81", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 122, + "segment": "SEG_CLBLM_L_X12Y82", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 121, + "segment": "SEG_CLBLM_L_X12Y83", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 120, + "segment": "SEG_CLBLM_L_X12Y84", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 119, + "segment": "SEG_CLBLM_L_X12Y85", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 118, + "segment": "SEG_CLBLM_L_X12Y86", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 117, + "segment": "SEG_CLBLM_L_X12Y87", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 116, + "segment": "SEG_CLBLM_L_X12Y88", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 115, + "segment": "SEG_CLBLM_L_X12Y89", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y9": { + "bits": {}, + "grid_x": 35, + "grid_y": 198, + "segment": "SEG_CLBLM_L_X12Y9", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 114, + "segment": "SEG_CLBLM_L_X12Y90", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 113, + "segment": "SEG_CLBLM_L_X12Y91", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 112, + "segment": "SEG_CLBLM_L_X12Y92", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 111, + "segment": "SEG_CLBLM_L_X12Y93", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 110, + "segment": "SEG_CLBLM_L_X12Y94", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 109, + "segment": "SEG_CLBLM_L_X12Y95", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 108, + "segment": "SEG_CLBLM_L_X12Y96", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 107, + "segment": "SEG_CLBLM_L_X12Y97", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 106, + "segment": "SEG_CLBLM_L_X12Y98", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X12Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400600", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 35, + "grid_y": 105, + "segment": "SEG_CLBLM_L_X12Y99", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X13Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y0": { + "bits": {}, + "grid_x": 41, + "grid_y": 207, + "segment": "SEG_DSP0_L_X14Y0", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y1": { + "bits": {}, + "grid_x": 41, + "grid_y": 206, + "segment": "SEG_DSP1_L_X14Y0", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y10": { + "bits": {}, + "grid_x": 41, + "grid_y": 197, + "segment": "SEG_DSP0_L_X14Y10", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y100": { + "bits": {}, + "grid_x": 41, + "grid_y": 103, + "segment": "SEG_DSP0_L_X14Y100", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y101": { + "bits": {}, + "grid_x": 41, + "grid_y": 102, + "segment": "SEG_DSP1_L_X14Y100", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y102": { + "bits": {}, + "grid_x": 41, + "grid_y": 101, + "segment": "SEG_DSP2_L_X14Y100", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y103": { + "bits": {}, + "grid_x": 41, + "grid_y": 100, + "segment": "SEG_DSP3_L_X14Y100", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y104": { + "bits": {}, + "grid_x": 41, + "grid_y": 99, + "segment": "SEG_DSP4_L_X14Y100", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y105": { + "bits": {}, + "grid_x": 41, + "grid_y": 98, + "segment": "SEG_DSP0_L_X14Y105", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y106": { + "bits": {}, + "grid_x": 41, + "grid_y": 97, + "segment": "SEG_DSP1_L_X14Y105", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y107": { + "bits": {}, + "grid_x": 41, + "grid_y": 96, + "segment": "SEG_DSP2_L_X14Y105", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y108": { + "bits": {}, + "grid_x": 41, + "grid_y": 95, + "segment": "SEG_DSP3_L_X14Y105", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y109": { + "bits": {}, + "grid_x": 41, + "grid_y": 94, + "segment": "SEG_DSP4_L_X14Y105", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y11": { + "bits": {}, + "grid_x": 41, + "grid_y": 196, + "segment": "SEG_DSP1_L_X14Y10", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y110": { + "bits": {}, + "grid_x": 41, + "grid_y": 93, + "segment": "SEG_DSP0_L_X14Y110", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y111": { + "bits": {}, + "grid_x": 41, + "grid_y": 92, + "segment": "SEG_DSP1_L_X14Y110", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y112": { + "bits": {}, + "grid_x": 41, + "grid_y": 91, + "segment": "SEG_DSP2_L_X14Y110", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y113": { + "bits": {}, + "grid_x": 41, + "grid_y": 90, + "segment": "SEG_DSP3_L_X14Y110", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y114": { + "bits": {}, + "grid_x": 41, + "grid_y": 89, + "segment": "SEG_DSP4_L_X14Y110", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y115": { + "bits": {}, + "grid_x": 41, + "grid_y": 88, + "segment": "SEG_DSP0_L_X14Y115", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y116": { + "bits": {}, + "grid_x": 41, + "grid_y": 87, + "segment": "SEG_DSP1_L_X14Y115", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y117": { + "bits": {}, + "grid_x": 41, + "grid_y": 86, + "segment": "SEG_DSP2_L_X14Y115", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y118": { + "bits": {}, + "grid_x": 41, + "grid_y": 85, + "segment": "SEG_DSP3_L_X14Y115", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y119": { + "bits": {}, + "grid_x": 41, + "grid_y": 84, + "segment": "SEG_DSP4_L_X14Y115", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y12": { + "bits": {}, + "grid_x": 41, + "grid_y": 195, + "segment": "SEG_DSP2_L_X14Y10", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y120": { + "bits": {}, + "grid_x": 41, + "grid_y": 83, + "segment": "SEG_DSP0_L_X14Y120", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y121": { + "bits": {}, + "grid_x": 41, + "grid_y": 82, + "segment": "SEG_DSP1_L_X14Y120", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y122": { + "bits": {}, + "grid_x": 41, + "grid_y": 81, + "segment": "SEG_DSP2_L_X14Y120", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y123": { + "bits": {}, + "grid_x": 41, + "grid_y": 80, + "segment": "SEG_DSP3_L_X14Y120", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y124": { + "bits": {}, + "grid_x": 41, + "grid_y": 79, + "segment": "SEG_DSP4_L_X14Y120", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y125": { + "bits": {}, + "grid_x": 41, + "grid_y": 77, + "segment": "SEG_DSP0_L_X14Y125", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y126": { + "bits": {}, + "grid_x": 41, + "grid_y": 76, + "segment": "SEG_DSP1_L_X14Y125", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y127": { + "bits": {}, + "grid_x": 41, + "grid_y": 75, + "segment": "SEG_DSP2_L_X14Y125", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y128": { + "bits": {}, + "grid_x": 41, + "grid_y": 74, + "segment": "SEG_DSP3_L_X14Y125", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y129": { + "bits": {}, + "grid_x": 41, + "grid_y": 73, + "segment": "SEG_DSP4_L_X14Y125", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y13": { + "bits": {}, + "grid_x": 41, + "grid_y": 194, + "segment": "SEG_DSP3_L_X14Y10", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y130": { + "bits": {}, + "grid_x": 41, + "grid_y": 72, + "segment": "SEG_DSP0_L_X14Y130", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y131": { + "bits": {}, + "grid_x": 41, + "grid_y": 71, + "segment": "SEG_DSP1_L_X14Y130", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y132": { + "bits": {}, + "grid_x": 41, + "grid_y": 70, + "segment": "SEG_DSP2_L_X14Y130", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y133": { + "bits": {}, + "grid_x": 41, + "grid_y": 69, + "segment": "SEG_DSP3_L_X14Y130", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y134": { + "bits": {}, + "grid_x": 41, + "grid_y": 68, + "segment": "SEG_DSP4_L_X14Y130", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y135": { + "bits": {}, + "grid_x": 41, + "grid_y": 67, + "segment": "SEG_DSP0_L_X14Y135", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y136": { + "bits": {}, + "grid_x": 41, + "grid_y": 66, + "segment": "SEG_DSP1_L_X14Y135", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y137": { + "bits": {}, + "grid_x": 41, + "grid_y": 65, + "segment": "SEG_DSP2_L_X14Y135", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y138": { + "bits": {}, + "grid_x": 41, + "grid_y": 64, + "segment": "SEG_DSP3_L_X14Y135", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y139": { + "bits": {}, + "grid_x": 41, + "grid_y": 63, + "segment": "SEG_DSP4_L_X14Y135", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y14": { + "bits": {}, + "grid_x": 41, + "grid_y": 193, + "segment": "SEG_DSP4_L_X14Y10", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y140": { + "bits": {}, + "grid_x": 41, + "grid_y": 62, + "segment": "SEG_DSP0_L_X14Y140", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y141": { + "bits": {}, + "grid_x": 41, + "grid_y": 61, + "segment": "SEG_DSP1_L_X14Y140", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y142": { + "bits": {}, + "grid_x": 41, + "grid_y": 60, + "segment": "SEG_DSP2_L_X14Y140", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y143": { + "bits": {}, + "grid_x": 41, + "grid_y": 59, + "segment": "SEG_DSP3_L_X14Y140", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y144": { + "bits": {}, + "grid_x": 41, + "grid_y": 58, + "segment": "SEG_DSP4_L_X14Y140", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y145": { + "bits": {}, + "grid_x": 41, + "grid_y": 57, + "segment": "SEG_DSP0_L_X14Y145", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y146": { + "bits": {}, + "grid_x": 41, + "grid_y": 56, + "segment": "SEG_DSP1_L_X14Y145", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y147": { + "bits": {}, + "grid_x": 41, + "grid_y": 55, + "segment": "SEG_DSP2_L_X14Y145", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y148": { + "bits": {}, + "grid_x": 41, + "grid_y": 54, + "segment": "SEG_DSP3_L_X14Y145", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y149": { + "bits": {}, + "grid_x": 41, + "grid_y": 53, + "segment": "SEG_DSP4_L_X14Y145", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y15": { + "bits": {}, + "grid_x": 41, + "grid_y": 192, + "segment": "SEG_DSP0_L_X14Y15", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y150": { + "bits": {}, + "grid_x": 41, + "grid_y": 51, + "segment": "SEG_DSP0_L_X14Y150", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y151": { + "bits": {}, + "grid_x": 41, + "grid_y": 50, + "segment": "SEG_DSP1_L_X14Y150", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y152": { + "bits": {}, + "grid_x": 41, + "grid_y": 49, + "segment": "SEG_DSP2_L_X14Y150", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y153": { + "bits": {}, + "grid_x": 41, + "grid_y": 48, + "segment": "SEG_DSP3_L_X14Y150", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y154": { + "bits": {}, + "grid_x": 41, + "grid_y": 47, + "segment": "SEG_DSP4_L_X14Y150", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y155": { + "bits": {}, + "grid_x": 41, + "grid_y": 46, + "segment": "SEG_DSP0_L_X14Y155", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y156": { + "bits": {}, + "grid_x": 41, + "grid_y": 45, + "segment": "SEG_DSP1_L_X14Y155", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y157": { + "bits": {}, + "grid_x": 41, + "grid_y": 44, + "segment": "SEG_DSP2_L_X14Y155", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y158": { + "bits": {}, + "grid_x": 41, + "grid_y": 43, + "segment": "SEG_DSP3_L_X14Y155", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y159": { + "bits": {}, + "grid_x": 41, + "grid_y": 42, + "segment": "SEG_DSP4_L_X14Y155", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y16": { + "bits": {}, + "grid_x": 41, + "grid_y": 191, + "segment": "SEG_DSP1_L_X14Y15", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y160": { + "bits": {}, + "grid_x": 41, + "grid_y": 41, + "segment": "SEG_DSP0_L_X14Y160", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y161": { + "bits": {}, + "grid_x": 41, + "grid_y": 40, + "segment": "SEG_DSP1_L_X14Y160", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y162": { + "bits": {}, + "grid_x": 41, + "grid_y": 39, + "segment": "SEG_DSP2_L_X14Y160", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y163": { + "bits": {}, + "grid_x": 41, + "grid_y": 38, + "segment": "SEG_DSP3_L_X14Y160", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y164": { + "bits": {}, + "grid_x": 41, + "grid_y": 37, + "segment": "SEG_DSP4_L_X14Y160", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y165": { + "bits": {}, + "grid_x": 41, + "grid_y": 36, + "segment": "SEG_DSP0_L_X14Y165", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y166": { + "bits": {}, + "grid_x": 41, + "grid_y": 35, + "segment": "SEG_DSP1_L_X14Y165", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y167": { + "bits": {}, + "grid_x": 41, + "grid_y": 34, + "segment": "SEG_DSP2_L_X14Y165", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y168": { + "bits": {}, + "grid_x": 41, + "grid_y": 33, + "segment": "SEG_DSP3_L_X14Y165", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y169": { + "bits": {}, + "grid_x": 41, + "grid_y": 32, + "segment": "SEG_DSP4_L_X14Y165", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y17": { + "bits": {}, + "grid_x": 41, + "grid_y": 190, + "segment": "SEG_DSP2_L_X14Y15", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y170": { + "bits": {}, + "grid_x": 41, + "grid_y": 31, + "segment": "SEG_DSP0_L_X14Y170", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y171": { + "bits": {}, + "grid_x": 41, + "grid_y": 30, + "segment": "SEG_DSP1_L_X14Y170", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y172": { + "bits": {}, + "grid_x": 41, + "grid_y": 29, + "segment": "SEG_DSP2_L_X14Y170", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y173": { + "bits": {}, + "grid_x": 41, + "grid_y": 28, + "segment": "SEG_DSP3_L_X14Y170", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y174": { + "bits": {}, + "grid_x": 41, + "grid_y": 27, + "segment": "SEG_DSP4_L_X14Y170", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y175": { + "bits": {}, + "grid_x": 41, + "grid_y": 25, + "segment": "SEG_DSP0_L_X14Y175", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y176": { + "bits": {}, + "grid_x": 41, + "grid_y": 24, + "segment": "SEG_DSP1_L_X14Y175", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y177": { + "bits": {}, + "grid_x": 41, + "grid_y": 23, + "segment": "SEG_DSP2_L_X14Y175", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y178": { + "bits": {}, + "grid_x": 41, + "grid_y": 22, + "segment": "SEG_DSP3_L_X14Y175", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y179": { + "bits": {}, + "grid_x": 41, + "grid_y": 21, + "segment": "SEG_DSP4_L_X14Y175", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y18": { + "bits": {}, + "grid_x": 41, + "grid_y": 189, + "segment": "SEG_DSP3_L_X14Y15", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y180": { + "bits": {}, + "grid_x": 41, + "grid_y": 20, + "segment": "SEG_DSP0_L_X14Y180", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y181": { + "bits": {}, + "grid_x": 41, + "grid_y": 19, + "segment": "SEG_DSP1_L_X14Y180", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y182": { + "bits": {}, + "grid_x": 41, + "grid_y": 18, + "segment": "SEG_DSP2_L_X14Y180", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y183": { + "bits": {}, + "grid_x": 41, + "grid_y": 17, + "segment": "SEG_DSP3_L_X14Y180", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y184": { + "bits": {}, + "grid_x": 41, + "grid_y": 16, + "segment": "SEG_DSP4_L_X14Y180", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y185": { + "bits": {}, + "grid_x": 41, + "grid_y": 15, + "segment": "SEG_DSP0_L_X14Y185", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y186": { + "bits": {}, + "grid_x": 41, + "grid_y": 14, + "segment": "SEG_DSP1_L_X14Y185", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y187": { + "bits": {}, + "grid_x": 41, + "grid_y": 13, + "segment": "SEG_DSP2_L_X14Y185", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y188": { + "bits": {}, + "grid_x": 41, + "grid_y": 12, + "segment": "SEG_DSP3_L_X14Y185", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y189": { + "bits": {}, + "grid_x": 41, + "grid_y": 11, + "segment": "SEG_DSP4_L_X14Y185", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y19": { + "bits": {}, + "grid_x": 41, + "grid_y": 188, + "segment": "SEG_DSP4_L_X14Y15", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y190": { + "bits": {}, + "grid_x": 41, + "grid_y": 10, + "segment": "SEG_DSP0_L_X14Y190", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y191": { + "bits": {}, + "grid_x": 41, + "grid_y": 9, + "segment": "SEG_DSP1_L_X14Y190", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y192": { + "bits": {}, + "grid_x": 41, + "grid_y": 8, + "segment": "SEG_DSP2_L_X14Y190", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y193": { + "bits": {}, + "grid_x": 41, + "grid_y": 7, + "segment": "SEG_DSP3_L_X14Y190", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y194": { + "bits": {}, + "grid_x": 41, + "grid_y": 6, + "segment": "SEG_DSP4_L_X14Y190", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y195": { + "bits": {}, + "grid_x": 41, + "grid_y": 5, + "segment": "SEG_DSP0_L_X14Y195", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y196": { + "bits": {}, + "grid_x": 41, + "grid_y": 4, + "segment": "SEG_DSP1_L_X14Y195", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y197": { + "bits": {}, + "grid_x": 41, + "grid_y": 3, + "segment": "SEG_DSP2_L_X14Y195", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y198": { + "bits": {}, + "grid_x": 41, + "grid_y": 2, + "segment": "SEG_DSP3_L_X14Y195", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y199": { + "bits": {}, + "grid_x": 41, + "grid_y": 1, + "segment": "SEG_DSP4_L_X14Y195", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y2": { + "bits": {}, + "grid_x": 41, + "grid_y": 205, + "segment": "SEG_DSP2_L_X14Y0", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y20": { + "bits": {}, + "grid_x": 41, + "grid_y": 187, + "segment": "SEG_DSP0_L_X14Y20", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y21": { + "bits": {}, + "grid_x": 41, + "grid_y": 186, + "segment": "SEG_DSP1_L_X14Y20", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y22": { + "bits": {}, + "grid_x": 41, + "grid_y": 185, + "segment": "SEG_DSP2_L_X14Y20", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y23": { + "bits": {}, + "grid_x": 41, + "grid_y": 184, + "segment": "SEG_DSP3_L_X14Y20", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y24": { + "bits": {}, + "grid_x": 41, + "grid_y": 183, + "segment": "SEG_DSP4_L_X14Y20", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y25": { + "bits": {}, + "grid_x": 41, + "grid_y": 181, + "segment": "SEG_DSP0_L_X14Y25", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y26": { + "bits": {}, + "grid_x": 41, + "grid_y": 180, + "segment": "SEG_DSP1_L_X14Y25", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y27": { + "bits": {}, + "grid_x": 41, + "grid_y": 179, + "segment": "SEG_DSP2_L_X14Y25", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y28": { + "bits": {}, + "grid_x": 41, + "grid_y": 178, + "segment": "SEG_DSP3_L_X14Y25", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y29": { + "bits": {}, + "grid_x": 41, + "grid_y": 177, + "segment": "SEG_DSP4_L_X14Y25", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y3": { + "bits": {}, + "grid_x": 41, + "grid_y": 204, + "segment": "SEG_DSP3_L_X14Y0", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y30": { + "bits": {}, + "grid_x": 41, + "grid_y": 176, + "segment": "SEG_DSP0_L_X14Y30", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y31": { + "bits": {}, + "grid_x": 41, + "grid_y": 175, + "segment": "SEG_DSP1_L_X14Y30", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y32": { + "bits": {}, + "grid_x": 41, + "grid_y": 174, + "segment": "SEG_DSP2_L_X14Y30", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y33": { + "bits": {}, + "grid_x": 41, + "grid_y": 173, + "segment": "SEG_DSP3_L_X14Y30", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y34": { + "bits": {}, + "grid_x": 41, + "grid_y": 172, + "segment": "SEG_DSP4_L_X14Y30", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y35": { + "bits": {}, + "grid_x": 41, + "grid_y": 171, + "segment": "SEG_DSP0_L_X14Y35", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y36": { + "bits": {}, + "grid_x": 41, + "grid_y": 170, + "segment": "SEG_DSP1_L_X14Y35", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y37": { + "bits": {}, + "grid_x": 41, + "grid_y": 169, + "segment": "SEG_DSP2_L_X14Y35", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y38": { + "bits": {}, + "grid_x": 41, + "grid_y": 168, + "segment": "SEG_DSP3_L_X14Y35", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y39": { + "bits": {}, + "grid_x": 41, + "grid_y": 167, + "segment": "SEG_DSP4_L_X14Y35", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y4": { + "bits": {}, + "grid_x": 41, + "grid_y": 203, + "segment": "SEG_DSP4_L_X14Y0", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y40": { + "bits": {}, + "grid_x": 41, + "grid_y": 166, + "segment": "SEG_DSP0_L_X14Y40", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y41": { + "bits": {}, + "grid_x": 41, + "grid_y": 165, + "segment": "SEG_DSP1_L_X14Y40", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y42": { + "bits": {}, + "grid_x": 41, + "grid_y": 164, + "segment": "SEG_DSP2_L_X14Y40", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y43": { + "bits": {}, + "grid_x": 41, + "grid_y": 163, + "segment": "SEG_DSP3_L_X14Y40", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y44": { + "bits": {}, + "grid_x": 41, + "grid_y": 162, + "segment": "SEG_DSP4_L_X14Y40", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y45": { + "bits": {}, + "grid_x": 41, + "grid_y": 161, + "segment": "SEG_DSP0_L_X14Y45", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y46": { + "bits": {}, + "grid_x": 41, + "grid_y": 160, + "segment": "SEG_DSP1_L_X14Y45", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y47": { + "bits": {}, + "grid_x": 41, + "grid_y": 159, + "segment": "SEG_DSP2_L_X14Y45", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y48": { + "bits": {}, + "grid_x": 41, + "grid_y": 158, + "segment": "SEG_DSP3_L_X14Y45", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y49": { + "bits": {}, + "grid_x": 41, + "grid_y": 157, + "segment": "SEG_DSP4_L_X14Y45", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y5": { + "bits": {}, + "grid_x": 41, + "grid_y": 202, + "segment": "SEG_DSP0_L_X14Y5", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y50": { + "bits": {}, + "grid_x": 41, + "grid_y": 155, + "segment": "SEG_DSP0_L_X14Y50", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y51": { + "bits": {}, + "grid_x": 41, + "grid_y": 154, + "segment": "SEG_DSP1_L_X14Y50", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y52": { + "bits": {}, + "grid_x": 41, + "grid_y": 153, + "segment": "SEG_DSP2_L_X14Y50", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y53": { + "bits": {}, + "grid_x": 41, + "grid_y": 152, + "segment": "SEG_DSP3_L_X14Y50", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y54": { + "bits": {}, + "grid_x": 41, + "grid_y": 151, + "segment": "SEG_DSP4_L_X14Y50", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y55": { + "bits": {}, + "grid_x": 41, + "grid_y": 150, + "segment": "SEG_DSP0_L_X14Y55", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y56": { + "bits": {}, + "grid_x": 41, + "grid_y": 149, + "segment": "SEG_DSP1_L_X14Y55", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y57": { + "bits": {}, + "grid_x": 41, + "grid_y": 148, + "segment": "SEG_DSP2_L_X14Y55", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y58": { + "bits": {}, + "grid_x": 41, + "grid_y": 147, + "segment": "SEG_DSP3_L_X14Y55", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y59": { + "bits": {}, + "grid_x": 41, + "grid_y": 146, + "segment": "SEG_DSP4_L_X14Y55", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y6": { + "bits": {}, + "grid_x": 41, + "grid_y": 201, + "segment": "SEG_DSP1_L_X14Y5", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y60": { + "bits": {}, + "grid_x": 41, + "grid_y": 145, + "segment": "SEG_DSP0_L_X14Y60", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y61": { + "bits": {}, + "grid_x": 41, + "grid_y": 144, + "segment": "SEG_DSP1_L_X14Y60", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y62": { + "bits": {}, + "grid_x": 41, + "grid_y": 143, + "segment": "SEG_DSP2_L_X14Y60", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y63": { + "bits": {}, + "grid_x": 41, + "grid_y": 142, + "segment": "SEG_DSP3_L_X14Y60", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y64": { + "bits": {}, + "grid_x": 41, + "grid_y": 141, + "segment": "SEG_DSP4_L_X14Y60", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y65": { + "bits": {}, + "grid_x": 41, + "grid_y": 140, + "segment": "SEG_DSP0_L_X14Y65", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y66": { + "bits": {}, + "grid_x": 41, + "grid_y": 139, + "segment": "SEG_DSP1_L_X14Y65", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y67": { + "bits": {}, + "grid_x": 41, + "grid_y": 138, + "segment": "SEG_DSP2_L_X14Y65", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y68": { + "bits": {}, + "grid_x": 41, + "grid_y": 137, + "segment": "SEG_DSP3_L_X14Y65", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y69": { + "bits": {}, + "grid_x": 41, + "grid_y": 136, + "segment": "SEG_DSP4_L_X14Y65", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y7": { + "bits": {}, + "grid_x": 41, + "grid_y": 200, + "segment": "SEG_DSP2_L_X14Y5", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y70": { + "bits": {}, + "grid_x": 41, + "grid_y": 135, + "segment": "SEG_DSP0_L_X14Y70", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y71": { + "bits": {}, + "grid_x": 41, + "grid_y": 134, + "segment": "SEG_DSP1_L_X14Y70", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y72": { + "bits": {}, + "grid_x": 41, + "grid_y": 133, + "segment": "SEG_DSP2_L_X14Y70", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y73": { + "bits": {}, + "grid_x": 41, + "grid_y": 132, + "segment": "SEG_DSP3_L_X14Y70", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y74": { + "bits": {}, + "grid_x": 41, + "grid_y": 131, + "segment": "SEG_DSP4_L_X14Y70", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y75": { + "bits": {}, + "grid_x": 41, + "grid_y": 129, + "segment": "SEG_DSP0_L_X14Y75", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y76": { + "bits": {}, + "grid_x": 41, + "grid_y": 128, + "segment": "SEG_DSP1_L_X14Y75", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y77": { + "bits": {}, + "grid_x": 41, + "grid_y": 127, + "segment": "SEG_DSP2_L_X14Y75", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y78": { + "bits": {}, + "grid_x": 41, + "grid_y": 126, + "segment": "SEG_DSP3_L_X14Y75", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y79": { + "bits": {}, + "grid_x": 41, + "grid_y": 125, + "segment": "SEG_DSP4_L_X14Y75", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y8": { + "bits": {}, + "grid_x": 41, + "grid_y": 199, + "segment": "SEG_DSP3_L_X14Y5", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y80": { + "bits": {}, + "grid_x": 41, + "grid_y": 124, + "segment": "SEG_DSP0_L_X14Y80", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y81": { + "bits": {}, + "grid_x": 41, + "grid_y": 123, + "segment": "SEG_DSP1_L_X14Y80", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y82": { + "bits": {}, + "grid_x": 41, + "grid_y": 122, + "segment": "SEG_DSP2_L_X14Y80", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y83": { + "bits": {}, + "grid_x": 41, + "grid_y": 121, + "segment": "SEG_DSP3_L_X14Y80", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y84": { + "bits": {}, + "grid_x": 41, + "grid_y": 120, + "segment": "SEG_DSP4_L_X14Y80", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y85": { + "bits": {}, + "grid_x": 41, + "grid_y": 119, + "segment": "SEG_DSP0_L_X14Y85", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y86": { + "bits": {}, + "grid_x": 41, + "grid_y": 118, + "segment": "SEG_DSP1_L_X14Y85", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y87": { + "bits": {}, + "grid_x": 41, + "grid_y": 117, + "segment": "SEG_DSP2_L_X14Y85", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y88": { + "bits": {}, + "grid_x": 41, + "grid_y": 116, + "segment": "SEG_DSP3_L_X14Y85", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y89": { + "bits": {}, + "grid_x": 41, + "grid_y": 115, + "segment": "SEG_DSP4_L_X14Y85", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y9": { + "bits": {}, + "grid_x": 41, + "grid_y": 198, + "segment": "SEG_DSP4_L_X14Y5", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y90": { + "bits": {}, + "grid_x": 41, + "grid_y": 114, + "segment": "SEG_DSP0_L_X14Y90", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y91": { + "bits": {}, + "grid_x": 41, + "grid_y": 113, + "segment": "SEG_DSP1_L_X14Y90", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y92": { + "bits": {}, + "grid_x": 41, + "grid_y": 112, + "segment": "SEG_DSP2_L_X14Y90", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y93": { + "bits": {}, + "grid_x": 41, + "grid_y": 111, + "segment": "SEG_DSP3_L_X14Y90", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y94": { + "bits": {}, + "grid_x": 41, + "grid_y": 110, + "segment": "SEG_DSP4_L_X14Y90", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y95": { + "bits": {}, + "grid_x": 41, + "grid_y": 109, + "segment": "SEG_DSP0_L_X14Y95", + "segment_type": "dsp0_l", + "sites": { + "TIEOFF_X16Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y96": { + "bits": {}, + "grid_x": 41, + "grid_y": 108, + "segment": "SEG_DSP1_L_X14Y95", + "segment_type": "dsp1_l", + "sites": { + "TIEOFF_X16Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y97": { + "bits": {}, + "grid_x": 41, + "grid_y": 107, + "segment": "SEG_DSP2_L_X14Y95", + "segment_type": "dsp2_l", + "sites": { + "TIEOFF_X16Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y98": { + "bits": {}, + "grid_x": 41, + "grid_y": 106, + "segment": "SEG_DSP3_L_X14Y95", + "segment_type": "dsp3_l", + "sites": { + "TIEOFF_X16Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X14Y99": { + "bits": {}, + "grid_x": 41, + "grid_y": 105, + "segment": "SEG_DSP4_L_X14Y95", + "segment_type": "dsp4_l", + "sites": { + "TIEOFF_X16Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y0": { + "bits": {}, + "grid_x": 45, + "grid_y": 207, + "segment": "SEG_CLBLM_L_X16Y0", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y1": { + "bits": {}, + "grid_x": 45, + "grid_y": 206, + "segment": "SEG_CLBLM_L_X16Y1", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y10": { + "bits": {}, + "grid_x": 45, + "grid_y": 197, + "segment": "SEG_CLBLM_L_X16Y10", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y100": { + "bits": {}, + "grid_x": 45, + "grid_y": 103, + "segment": "SEG_CLBLM_L_X16Y100", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y101": { + "bits": {}, + "grid_x": 45, + "grid_y": 102, + "segment": "SEG_CLBLM_L_X16Y101", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y102": { + "bits": {}, + "grid_x": 45, + "grid_y": 101, + "segment": "SEG_CLBLM_L_X16Y102", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y103": { + "bits": {}, + "grid_x": 45, + "grid_y": 100, + "segment": "SEG_CLBLM_L_X16Y103", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y104": { + "bits": {}, + "grid_x": 45, + "grid_y": 99, + "segment": "SEG_CLBLM_L_X16Y104", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y105": { + "bits": {}, + "grid_x": 45, + "grid_y": 98, + "segment": "SEG_CLBLM_L_X16Y105", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y106": { + "bits": {}, + "grid_x": 45, + "grid_y": 97, + "segment": "SEG_CLBLM_L_X16Y106", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y107": { + "bits": {}, + "grid_x": 45, + "grid_y": 96, + "segment": "SEG_CLBLM_L_X16Y107", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y108": { + "bits": {}, + "grid_x": 45, + "grid_y": 95, + "segment": "SEG_CLBLM_L_X16Y108", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y109": { + "bits": {}, + "grid_x": 45, + "grid_y": 94, + "segment": "SEG_CLBLM_L_X16Y109", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y11": { + "bits": {}, + "grid_x": 45, + "grid_y": 196, + "segment": "SEG_CLBLM_L_X16Y11", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y110": { + "bits": {}, + "grid_x": 45, + "grid_y": 93, + "segment": "SEG_CLBLM_L_X16Y110", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y111": { + "bits": {}, + "grid_x": 45, + "grid_y": 92, + "segment": "SEG_CLBLM_L_X16Y111", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y112": { + "bits": {}, + "grid_x": 45, + "grid_y": 91, + "segment": "SEG_CLBLM_L_X16Y112", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y113": { + "bits": {}, + "grid_x": 45, + "grid_y": 90, + "segment": "SEG_CLBLM_L_X16Y113", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y114": { + "bits": {}, + "grid_x": 45, + "grid_y": 89, + "segment": "SEG_CLBLM_L_X16Y114", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y115": { + "bits": {}, + "grid_x": 45, + "grid_y": 88, + "segment": "SEG_CLBLM_L_X16Y115", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y116": { + "bits": {}, + "grid_x": 45, + "grid_y": 87, + "segment": "SEG_CLBLM_L_X16Y116", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y117": { + "bits": {}, + "grid_x": 45, + "grid_y": 86, + "segment": "SEG_CLBLM_L_X16Y117", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y118": { + "bits": {}, + "grid_x": 45, + "grid_y": 85, + "segment": "SEG_CLBLM_L_X16Y118", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y119": { + "bits": {}, + "grid_x": 45, + "grid_y": 84, + "segment": "SEG_CLBLM_L_X16Y119", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y12": { + "bits": {}, + "grid_x": 45, + "grid_y": 195, + "segment": "SEG_CLBLM_L_X16Y12", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y120": { + "bits": {}, + "grid_x": 45, + "grid_y": 83, + "segment": "SEG_CLBLM_L_X16Y120", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y121": { + "bits": {}, + "grid_x": 45, + "grid_y": 82, + "segment": "SEG_CLBLM_L_X16Y121", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y122": { + "bits": {}, + "grid_x": 45, + "grid_y": 81, + "segment": "SEG_CLBLM_L_X16Y122", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y123": { + "bits": {}, + "grid_x": 45, + "grid_y": 80, + "segment": "SEG_CLBLM_L_X16Y123", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y124": { + "bits": {}, + "grid_x": 45, + "grid_y": 79, + "segment": "SEG_CLBLM_L_X16Y124", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y125": { + "bits": {}, + "grid_x": 45, + "grid_y": 77, + "segment": "SEG_CLBLM_L_X16Y125", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y126": { + "bits": {}, + "grid_x": 45, + "grid_y": 76, + "segment": "SEG_CLBLM_L_X16Y126", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y127": { + "bits": {}, + "grid_x": 45, + "grid_y": 75, + "segment": "SEG_CLBLM_L_X16Y127", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y128": { + "bits": {}, + "grid_x": 45, + "grid_y": 74, + "segment": "SEG_CLBLM_L_X16Y128", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y129": { + "bits": {}, + "grid_x": 45, + "grid_y": 73, + "segment": "SEG_CLBLM_L_X16Y129", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y13": { + "bits": {}, + "grid_x": 45, + "grid_y": 194, + "segment": "SEG_CLBLM_L_X16Y13", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y130": { + "bits": {}, + "grid_x": 45, + "grid_y": 72, + "segment": "SEG_CLBLM_L_X16Y130", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y131": { + "bits": {}, + "grid_x": 45, + "grid_y": 71, + "segment": "SEG_CLBLM_L_X16Y131", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y132": { + "bits": {}, + "grid_x": 45, + "grid_y": 70, + "segment": "SEG_CLBLM_L_X16Y132", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y133": { + "bits": {}, + "grid_x": 45, + "grid_y": 69, + "segment": "SEG_CLBLM_L_X16Y133", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y134": { + "bits": {}, + "grid_x": 45, + "grid_y": 68, + "segment": "SEG_CLBLM_L_X16Y134", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y135": { + "bits": {}, + "grid_x": 45, + "grid_y": 67, + "segment": "SEG_CLBLM_L_X16Y135", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y136": { + "bits": {}, + "grid_x": 45, + "grid_y": 66, + "segment": "SEG_CLBLM_L_X16Y136", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y137": { + "bits": {}, + "grid_x": 45, + "grid_y": 65, + "segment": "SEG_CLBLM_L_X16Y137", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y138": { + "bits": {}, + "grid_x": 45, + "grid_y": 64, + "segment": "SEG_CLBLM_L_X16Y138", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y139": { + "bits": {}, + "grid_x": 45, + "grid_y": 63, + "segment": "SEG_CLBLM_L_X16Y139", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y14": { + "bits": {}, + "grid_x": 45, + "grid_y": 193, + "segment": "SEG_CLBLM_L_X16Y14", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y140": { + "bits": {}, + "grid_x": 45, + "grid_y": 62, + "segment": "SEG_CLBLM_L_X16Y140", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y141": { + "bits": {}, + "grid_x": 45, + "grid_y": 61, + "segment": "SEG_CLBLM_L_X16Y141", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y142": { + "bits": {}, + "grid_x": 45, + "grid_y": 60, + "segment": "SEG_CLBLM_L_X16Y142", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y143": { + "bits": {}, + "grid_x": 45, + "grid_y": 59, + "segment": "SEG_CLBLM_L_X16Y143", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y144": { + "bits": {}, + "grid_x": 45, + "grid_y": 58, + "segment": "SEG_CLBLM_L_X16Y144", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y145": { + "bits": {}, + "grid_x": 45, + "grid_y": 57, + "segment": "SEG_CLBLM_L_X16Y145", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y146": { + "bits": {}, + "grid_x": 45, + "grid_y": 56, + "segment": "SEG_CLBLM_L_X16Y146", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y147": { + "bits": {}, + "grid_x": 45, + "grid_y": 55, + "segment": "SEG_CLBLM_L_X16Y147", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y148": { + "bits": {}, + "grid_x": 45, + "grid_y": 54, + "segment": "SEG_CLBLM_L_X16Y148", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y149": { + "bits": {}, + "grid_x": 45, + "grid_y": 53, + "segment": "SEG_CLBLM_L_X16Y149", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y15": { + "bits": {}, + "grid_x": 45, + "grid_y": 192, + "segment": "SEG_CLBLM_L_X16Y15", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y150": { + "bits": {}, + "grid_x": 45, + "grid_y": 51, + "segment": "SEG_CLBLM_L_X16Y150", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y151": { + "bits": {}, + "grid_x": 45, + "grid_y": 50, + "segment": "SEG_CLBLM_L_X16Y151", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y152": { + "bits": {}, + "grid_x": 45, + "grid_y": 49, + "segment": "SEG_CLBLM_L_X16Y152", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y153": { + "bits": {}, + "grid_x": 45, + "grid_y": 48, + "segment": "SEG_CLBLM_L_X16Y153", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y154": { + "bits": {}, + "grid_x": 45, + "grid_y": 47, + "segment": "SEG_CLBLM_L_X16Y154", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y155": { + "bits": {}, + "grid_x": 45, + "grid_y": 46, + "segment": "SEG_CLBLM_L_X16Y155", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y156": { + "bits": {}, + "grid_x": 45, + "grid_y": 45, + "segment": "SEG_CLBLM_L_X16Y156", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y157": { + "bits": {}, + "grid_x": 45, + "grid_y": 44, + "segment": "SEG_CLBLM_L_X16Y157", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y158": { + "bits": {}, + "grid_x": 45, + "grid_y": 43, + "segment": "SEG_CLBLM_L_X16Y158", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y159": { + "bits": {}, + "grid_x": 45, + "grid_y": 42, + "segment": "SEG_CLBLM_L_X16Y159", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y16": { + "bits": {}, + "grid_x": 45, + "grid_y": 191, + "segment": "SEG_CLBLM_L_X16Y16", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y160": { + "bits": {}, + "grid_x": 45, + "grid_y": 41, + "segment": "SEG_CLBLM_L_X16Y160", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y161": { + "bits": {}, + "grid_x": 45, + "grid_y": 40, + "segment": "SEG_CLBLM_L_X16Y161", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y162": { + "bits": {}, + "grid_x": 45, + "grid_y": 39, + "segment": "SEG_CLBLM_L_X16Y162", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y163": { + "bits": {}, + "grid_x": 45, + "grid_y": 38, + "segment": "SEG_CLBLM_L_X16Y163", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y164": { + "bits": {}, + "grid_x": 45, + "grid_y": 37, + "segment": "SEG_CLBLM_L_X16Y164", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y165": { + "bits": {}, + "grid_x": 45, + "grid_y": 36, + "segment": "SEG_CLBLM_L_X16Y165", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y166": { + "bits": {}, + "grid_x": 45, + "grid_y": 35, + "segment": "SEG_CLBLM_L_X16Y166", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y167": { + "bits": {}, + "grid_x": 45, + "grid_y": 34, + "segment": "SEG_CLBLM_L_X16Y167", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y168": { + "bits": {}, + "grid_x": 45, + "grid_y": 33, + "segment": "SEG_CLBLM_L_X16Y168", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y169": { + "bits": {}, + "grid_x": 45, + "grid_y": 32, + "segment": "SEG_CLBLM_L_X16Y169", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y17": { + "bits": {}, + "grid_x": 45, + "grid_y": 190, + "segment": "SEG_CLBLM_L_X16Y17", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y170": { + "bits": {}, + "grid_x": 45, + "grid_y": 31, + "segment": "SEG_CLBLM_L_X16Y170", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y171": { + "bits": {}, + "grid_x": 45, + "grid_y": 30, + "segment": "SEG_CLBLM_L_X16Y171", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y172": { + "bits": {}, + "grid_x": 45, + "grid_y": 29, + "segment": "SEG_CLBLM_L_X16Y172", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y173": { + "bits": {}, + "grid_x": 45, + "grid_y": 28, + "segment": "SEG_CLBLM_L_X16Y173", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y174": { + "bits": {}, + "grid_x": 45, + "grid_y": 27, + "segment": "SEG_CLBLM_L_X16Y174", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y175": { + "bits": {}, + "grid_x": 45, + "grid_y": 25, + "segment": "SEG_CLBLM_L_X16Y175", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y176": { + "bits": {}, + "grid_x": 45, + "grid_y": 24, + "segment": "SEG_CLBLM_L_X16Y176", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y177": { + "bits": {}, + "grid_x": 45, + "grid_y": 23, + "segment": "SEG_CLBLM_L_X16Y177", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y178": { + "bits": {}, + "grid_x": 45, + "grid_y": 22, + "segment": "SEG_CLBLM_L_X16Y178", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y179": { + "bits": {}, + "grid_x": 45, + "grid_y": 21, + "segment": "SEG_CLBLM_L_X16Y179", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y18": { + "bits": {}, + "grid_x": 45, + "grid_y": 189, + "segment": "SEG_CLBLM_L_X16Y18", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y180": { + "bits": {}, + "grid_x": 45, + "grid_y": 20, + "segment": "SEG_CLBLM_L_X16Y180", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y181": { + "bits": {}, + "grid_x": 45, + "grid_y": 19, + "segment": "SEG_CLBLM_L_X16Y181", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y182": { + "bits": {}, + "grid_x": 45, + "grid_y": 18, + "segment": "SEG_CLBLM_L_X16Y182", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y183": { + "bits": {}, + "grid_x": 45, + "grid_y": 17, + "segment": "SEG_CLBLM_L_X16Y183", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y184": { + "bits": {}, + "grid_x": 45, + "grid_y": 16, + "segment": "SEG_CLBLM_L_X16Y184", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y185": { + "bits": {}, + "grid_x": 45, + "grid_y": 15, + "segment": "SEG_CLBLM_L_X16Y185", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y186": { + "bits": {}, + "grid_x": 45, + "grid_y": 14, + "segment": "SEG_CLBLM_L_X16Y186", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y187": { + "bits": {}, + "grid_x": 45, + "grid_y": 13, + "segment": "SEG_CLBLM_L_X16Y187", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y188": { + "bits": {}, + "grid_x": 45, + "grid_y": 12, + "segment": "SEG_CLBLM_L_X16Y188", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y189": { + "bits": {}, + "grid_x": 45, + "grid_y": 11, + "segment": "SEG_CLBLM_L_X16Y189", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y19": { + "bits": {}, + "grid_x": 45, + "grid_y": 188, + "segment": "SEG_CLBLM_L_X16Y19", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y190": { + "bits": {}, + "grid_x": 45, + "grid_y": 10, + "segment": "SEG_CLBLM_L_X16Y190", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y191": { + "bits": {}, + "grid_x": 45, + "grid_y": 9, + "segment": "SEG_CLBLM_L_X16Y191", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y192": { + "bits": {}, + "grid_x": 45, + "grid_y": 8, + "segment": "SEG_CLBLM_L_X16Y192", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y193": { + "bits": {}, + "grid_x": 45, + "grid_y": 7, + "segment": "SEG_CLBLM_L_X16Y193", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y194": { + "bits": {}, + "grid_x": 45, + "grid_y": 6, + "segment": "SEG_CLBLM_L_X16Y194", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y195": { + "bits": {}, + "grid_x": 45, + "grid_y": 5, + "segment": "SEG_CLBLM_L_X16Y195", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y196": { + "bits": {}, + "grid_x": 45, + "grid_y": 4, + "segment": "SEG_CLBLM_L_X16Y196", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y197": { + "bits": {}, + "grid_x": 45, + "grid_y": 3, + "segment": "SEG_CLBLM_L_X16Y197", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y198": { + "bits": {}, + "grid_x": 45, + "grid_y": 2, + "segment": "SEG_CLBLM_L_X16Y198", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y199": { + "bits": {}, + "grid_x": 45, + "grid_y": 1, + "segment": "SEG_CLBLM_L_X16Y199", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y2": { + "bits": {}, + "grid_x": 45, + "grid_y": 205, + "segment": "SEG_CLBLM_L_X16Y2", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y20": { + "bits": {}, + "grid_x": 45, + "grid_y": 187, + "segment": "SEG_CLBLM_L_X16Y20", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y21": { + "bits": {}, + "grid_x": 45, + "grid_y": 186, + "segment": "SEG_CLBLM_L_X16Y21", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y22": { + "bits": {}, + "grid_x": 45, + "grid_y": 185, + "segment": "SEG_CLBLM_L_X16Y22", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y23": { + "bits": {}, + "grid_x": 45, + "grid_y": 184, + "segment": "SEG_CLBLM_L_X16Y23", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y24": { + "bits": {}, + "grid_x": 45, + "grid_y": 183, + "segment": "SEG_CLBLM_L_X16Y24", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y25": { + "bits": {}, + "grid_x": 45, + "grid_y": 181, + "segment": "SEG_CLBLM_L_X16Y25", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y26": { + "bits": {}, + "grid_x": 45, + "grid_y": 180, + "segment": "SEG_CLBLM_L_X16Y26", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y27": { + "bits": {}, + "grid_x": 45, + "grid_y": 179, + "segment": "SEG_CLBLM_L_X16Y27", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y28": { + "bits": {}, + "grid_x": 45, + "grid_y": 178, + "segment": "SEG_CLBLM_L_X16Y28", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y29": { + "bits": {}, + "grid_x": 45, + "grid_y": 177, + "segment": "SEG_CLBLM_L_X16Y29", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y3": { + "bits": {}, + "grid_x": 45, + "grid_y": 204, + "segment": "SEG_CLBLM_L_X16Y3", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y30": { + "bits": {}, + "grid_x": 45, + "grid_y": 176, + "segment": "SEG_CLBLM_L_X16Y30", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y31": { + "bits": {}, + "grid_x": 45, + "grid_y": 175, + "segment": "SEG_CLBLM_L_X16Y31", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y32": { + "bits": {}, + "grid_x": 45, + "grid_y": 174, + "segment": "SEG_CLBLM_L_X16Y32", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y33": { + "bits": {}, + "grid_x": 45, + "grid_y": 173, + "segment": "SEG_CLBLM_L_X16Y33", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y34": { + "bits": {}, + "grid_x": 45, + "grid_y": 172, + "segment": "SEG_CLBLM_L_X16Y34", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y35": { + "bits": {}, + "grid_x": 45, + "grid_y": 171, + "segment": "SEG_CLBLM_L_X16Y35", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y36": { + "bits": {}, + "grid_x": 45, + "grid_y": 170, + "segment": "SEG_CLBLM_L_X16Y36", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y37": { + "bits": {}, + "grid_x": 45, + "grid_y": 169, + "segment": "SEG_CLBLM_L_X16Y37", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y38": { + "bits": {}, + "grid_x": 45, + "grid_y": 168, + "segment": "SEG_CLBLM_L_X16Y38", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y39": { + "bits": {}, + "grid_x": 45, + "grid_y": 167, + "segment": "SEG_CLBLM_L_X16Y39", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y4": { + "bits": {}, + "grid_x": 45, + "grid_y": 203, + "segment": "SEG_CLBLM_L_X16Y4", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y40": { + "bits": {}, + "grid_x": 45, + "grid_y": 166, + "segment": "SEG_CLBLM_L_X16Y40", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y41": { + "bits": {}, + "grid_x": 45, + "grid_y": 165, + "segment": "SEG_CLBLM_L_X16Y41", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y42": { + "bits": {}, + "grid_x": 45, + "grid_y": 164, + "segment": "SEG_CLBLM_L_X16Y42", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y43": { + "bits": {}, + "grid_x": 45, + "grid_y": 163, + "segment": "SEG_CLBLM_L_X16Y43", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y44": { + "bits": {}, + "grid_x": 45, + "grid_y": 162, + "segment": "SEG_CLBLM_L_X16Y44", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y45": { + "bits": {}, + "grid_x": 45, + "grid_y": 161, + "segment": "SEG_CLBLM_L_X16Y45", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y46": { + "bits": {}, + "grid_x": 45, + "grid_y": 160, + "segment": "SEG_CLBLM_L_X16Y46", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y47": { + "bits": {}, + "grid_x": 45, + "grid_y": 159, + "segment": "SEG_CLBLM_L_X16Y47", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y48": { + "bits": {}, + "grid_x": 45, + "grid_y": 158, + "segment": "SEG_CLBLM_L_X16Y48", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y49": { + "bits": {}, + "grid_x": 45, + "grid_y": 157, + "segment": "SEG_CLBLM_L_X16Y49", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y5": { + "bits": {}, + "grid_x": 45, + "grid_y": 202, + "segment": "SEG_CLBLM_L_X16Y5", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y50": { + "bits": {}, + "grid_x": 45, + "grid_y": 155, + "segment": "SEG_CLBLM_L_X16Y50", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y51": { + "bits": {}, + "grid_x": 45, + "grid_y": 154, + "segment": "SEG_CLBLM_L_X16Y51", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y52": { + "bits": {}, + "grid_x": 45, + "grid_y": 153, + "segment": "SEG_CLBLM_L_X16Y52", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y53": { + "bits": {}, + "grid_x": 45, + "grid_y": 152, + "segment": "SEG_CLBLM_L_X16Y53", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y54": { + "bits": {}, + "grid_x": 45, + "grid_y": 151, + "segment": "SEG_CLBLM_L_X16Y54", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y55": { + "bits": {}, + "grid_x": 45, + "grid_y": 150, + "segment": "SEG_CLBLM_L_X16Y55", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y56": { + "bits": {}, + "grid_x": 45, + "grid_y": 149, + "segment": "SEG_CLBLM_L_X16Y56", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y57": { + "bits": {}, + "grid_x": 45, + "grid_y": 148, + "segment": "SEG_CLBLM_L_X16Y57", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y58": { + "bits": {}, + "grid_x": 45, + "grid_y": 147, + "segment": "SEG_CLBLM_L_X16Y58", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y59": { + "bits": {}, + "grid_x": 45, + "grid_y": 146, + "segment": "SEG_CLBLM_L_X16Y59", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y6": { + "bits": {}, + "grid_x": 45, + "grid_y": 201, + "segment": "SEG_CLBLM_L_X16Y6", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y60": { + "bits": {}, + "grid_x": 45, + "grid_y": 145, + "segment": "SEG_CLBLM_L_X16Y60", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y61": { + "bits": {}, + "grid_x": 45, + "grid_y": 144, + "segment": "SEG_CLBLM_L_X16Y61", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y62": { + "bits": {}, + "grid_x": 45, + "grid_y": 143, + "segment": "SEG_CLBLM_L_X16Y62", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y63": { + "bits": {}, + "grid_x": 45, + "grid_y": 142, + "segment": "SEG_CLBLM_L_X16Y63", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y64": { + "bits": {}, + "grid_x": 45, + "grid_y": 141, + "segment": "SEG_CLBLM_L_X16Y64", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y65": { + "bits": {}, + "grid_x": 45, + "grid_y": 140, + "segment": "SEG_CLBLM_L_X16Y65", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y66": { + "bits": {}, + "grid_x": 45, + "grid_y": 139, + "segment": "SEG_CLBLM_L_X16Y66", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y67": { + "bits": {}, + "grid_x": 45, + "grid_y": 138, + "segment": "SEG_CLBLM_L_X16Y67", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y68": { + "bits": {}, + "grid_x": 45, + "grid_y": 137, + "segment": "SEG_CLBLM_L_X16Y68", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y69": { + "bits": {}, + "grid_x": 45, + "grid_y": 136, + "segment": "SEG_CLBLM_L_X16Y69", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y7": { + "bits": {}, + "grid_x": 45, + "grid_y": 200, + "segment": "SEG_CLBLM_L_X16Y7", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y70": { + "bits": {}, + "grid_x": 45, + "grid_y": 135, + "segment": "SEG_CLBLM_L_X16Y70", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y71": { + "bits": {}, + "grid_x": 45, + "grid_y": 134, + "segment": "SEG_CLBLM_L_X16Y71", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y72": { + "bits": {}, + "grid_x": 45, + "grid_y": 133, + "segment": "SEG_CLBLM_L_X16Y72", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y73": { + "bits": {}, + "grid_x": 45, + "grid_y": 132, + "segment": "SEG_CLBLM_L_X16Y73", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y74": { + "bits": {}, + "grid_x": 45, + "grid_y": 131, + "segment": "SEG_CLBLM_L_X16Y74", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y75": { + "bits": {}, + "grid_x": 45, + "grid_y": 129, + "segment": "SEG_CLBLM_L_X16Y75", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y76": { + "bits": {}, + "grid_x": 45, + "grid_y": 128, + "segment": "SEG_CLBLM_L_X16Y76", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y77": { + "bits": {}, + "grid_x": 45, + "grid_y": 127, + "segment": "SEG_CLBLM_L_X16Y77", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y78": { + "bits": {}, + "grid_x": 45, + "grid_y": 126, + "segment": "SEG_CLBLM_L_X16Y78", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y79": { + "bits": {}, + "grid_x": 45, + "grid_y": 125, + "segment": "SEG_CLBLM_L_X16Y79", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y8": { + "bits": {}, + "grid_x": 45, + "grid_y": 199, + "segment": "SEG_CLBLM_L_X16Y8", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y80": { + "bits": {}, + "grid_x": 45, + "grid_y": 124, + "segment": "SEG_CLBLM_L_X16Y80", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y81": { + "bits": {}, + "grid_x": 45, + "grid_y": 123, + "segment": "SEG_CLBLM_L_X16Y81", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y82": { + "bits": {}, + "grid_x": 45, + "grid_y": 122, + "segment": "SEG_CLBLM_L_X16Y82", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y83": { + "bits": {}, + "grid_x": 45, + "grid_y": 121, + "segment": "SEG_CLBLM_L_X16Y83", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y84": { + "bits": {}, + "grid_x": 45, + "grid_y": 120, + "segment": "SEG_CLBLM_L_X16Y84", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y85": { + "bits": {}, + "grid_x": 45, + "grid_y": 119, + "segment": "SEG_CLBLM_L_X16Y85", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y86": { + "bits": {}, + "grid_x": 45, + "grid_y": 118, + "segment": "SEG_CLBLM_L_X16Y86", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y87": { + "bits": {}, + "grid_x": 45, + "grid_y": 117, + "segment": "SEG_CLBLM_L_X16Y87", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y88": { + "bits": {}, + "grid_x": 45, + "grid_y": 116, + "segment": "SEG_CLBLM_L_X16Y88", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y89": { + "bits": {}, + "grid_x": 45, + "grid_y": 115, + "segment": "SEG_CLBLM_L_X16Y89", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y9": { + "bits": {}, + "grid_x": 45, + "grid_y": 198, + "segment": "SEG_CLBLM_L_X16Y9", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y90": { + "bits": {}, + "grid_x": 45, + "grid_y": 114, + "segment": "SEG_CLBLM_L_X16Y90", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y91": { + "bits": {}, + "grid_x": 45, + "grid_y": 113, + "segment": "SEG_CLBLM_L_X16Y91", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y92": { + "bits": {}, + "grid_x": 45, + "grid_y": 112, + "segment": "SEG_CLBLM_L_X16Y92", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y93": { + "bits": {}, + "grid_x": 45, + "grid_y": 111, + "segment": "SEG_CLBLM_L_X16Y93", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y94": { + "bits": {}, + "grid_x": 45, + "grid_y": 110, + "segment": "SEG_CLBLM_L_X16Y94", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y95": { + "bits": {}, + "grid_x": 45, + "grid_y": 109, + "segment": "SEG_CLBLM_L_X16Y95", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y96": { + "bits": {}, + "grid_x": 45, + "grid_y": 108, + "segment": "SEG_CLBLM_L_X16Y96", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y97": { + "bits": {}, + "grid_x": 45, + "grid_y": 107, + "segment": "SEG_CLBLM_L_X16Y97", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y98": { + "bits": {}, + "grid_x": 45, + "grid_y": 106, + "segment": "SEG_CLBLM_L_X16Y98", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X16Y99": { + "bits": {}, + "grid_x": 45, + "grid_y": 105, + "segment": "SEG_CLBLM_L_X16Y99", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X18Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y0": { + "bits": {}, + "grid_x": 51, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X18Y0", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y1": { + "bits": {}, + "grid_x": 51, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X18Y1", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y10": { + "bits": {}, + "grid_x": 51, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X18Y10", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y11": { + "bits": {}, + "grid_x": 51, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X18Y11", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y12": { + "bits": {}, + "grid_x": 51, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X18Y12", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y13": { + "bits": {}, + "grid_x": 51, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X18Y13", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y14": { + "bits": {}, + "grid_x": 51, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X18Y14", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y15": { + "bits": {}, + "grid_x": 51, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X18Y15", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y150": { + "bits": {}, + "grid_x": 51, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X18Y150", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y151": { + "bits": {}, + "grid_x": 51, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X18Y151", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y152": { + "bits": {}, + "grid_x": 51, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X18Y152", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y153": { + "bits": {}, + "grid_x": 51, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X18Y153", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y154": { + "bits": {}, + "grid_x": 51, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X18Y154", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y155": { + "bits": {}, + "grid_x": 51, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X18Y155", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y156": { + "bits": {}, + "grid_x": 51, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X18Y156", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y157": { + "bits": {}, + "grid_x": 51, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X18Y157", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y158": { + "bits": {}, + "grid_x": 51, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X18Y158", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y159": { + "bits": {}, + "grid_x": 51, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X18Y159", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y16": { + "bits": {}, + "grid_x": 51, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X18Y16", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y160": { + "bits": {}, + "grid_x": 51, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X18Y160", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y161": { + "bits": {}, + "grid_x": 51, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X18Y161", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y162": { + "bits": {}, + "grid_x": 51, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X18Y162", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y163": { + "bits": {}, + "grid_x": 51, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X18Y163", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y164": { + "bits": {}, + "grid_x": 51, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X18Y164", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y165": { + "bits": {}, + "grid_x": 51, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X18Y165", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y166": { + "bits": {}, + "grid_x": 51, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X18Y166", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y167": { + "bits": {}, + "grid_x": 51, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X18Y167", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y168": { + "bits": {}, + "grid_x": 51, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X18Y168", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y169": { + "bits": {}, + "grid_x": 51, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X18Y169", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y17": { + "bits": {}, + "grid_x": 51, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X18Y17", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y170": { + "bits": {}, + "grid_x": 51, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X18Y170", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y171": { + "bits": {}, + "grid_x": 51, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X18Y171", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y172": { + "bits": {}, + "grid_x": 51, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X18Y172", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y173": { + "bits": {}, + "grid_x": 51, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X18Y173", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y174": { + "bits": {}, + "grid_x": 51, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X18Y174", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y175": { + "bits": {}, + "grid_x": 51, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X18Y175", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y176": { + "bits": {}, + "grid_x": 51, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X18Y176", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y177": { + "bits": {}, + "grid_x": 51, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X18Y177", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y178": { + "bits": {}, + "grid_x": 51, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X18Y178", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y179": { + "bits": {}, + "grid_x": 51, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X18Y179", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y18": { + "bits": {}, + "grid_x": 51, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X18Y18", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y180": { + "bits": {}, + "grid_x": 51, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X18Y180", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y181": { + "bits": {}, + "grid_x": 51, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X18Y181", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y182": { + "bits": {}, + "grid_x": 51, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X18Y182", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y183": { + "bits": {}, + "grid_x": 51, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X18Y183", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y184": { + "bits": {}, + "grid_x": 51, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X18Y184", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y185": { + "bits": {}, + "grid_x": 51, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X18Y185", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y186": { + "bits": {}, + "grid_x": 51, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X18Y186", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y187": { + "bits": {}, + "grid_x": 51, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X18Y187", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y188": { + "bits": {}, + "grid_x": 51, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X18Y188", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y189": { + "bits": {}, + "grid_x": 51, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X18Y189", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y19": { + "bits": {}, + "grid_x": 51, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X18Y19", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y190": { + "bits": {}, + "grid_x": 51, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X18Y190", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y191": { + "bits": {}, + "grid_x": 51, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X18Y191", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y192": { + "bits": {}, + "grid_x": 51, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X18Y192", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y193": { + "bits": {}, + "grid_x": 51, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X18Y193", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y194": { + "bits": {}, + "grid_x": 51, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X18Y194", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y195": { + "bits": {}, + "grid_x": 51, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X18Y195", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y196": { + "bits": {}, + "grid_x": 51, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X18Y196", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y197": { + "bits": {}, + "grid_x": 51, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X18Y197", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y198": { + "bits": {}, + "grid_x": 51, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X18Y198", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y199": { + "bits": {}, + "grid_x": 51, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X18Y199", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y2": { + "bits": {}, + "grid_x": 51, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X18Y2", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y20": { + "bits": {}, + "grid_x": 51, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X18Y20", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y21": { + "bits": {}, + "grid_x": 51, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X18Y21", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y22": { + "bits": {}, + "grid_x": 51, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X18Y22", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y23": { + "bits": {}, + "grid_x": 51, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X18Y23", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y24": { + "bits": {}, + "grid_x": 51, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X18Y24", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y25": { + "bits": {}, + "grid_x": 51, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X18Y25", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y26": { + "bits": {}, + "grid_x": 51, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X18Y26", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y27": { + "bits": {}, + "grid_x": 51, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X18Y27", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y28": { + "bits": {}, + "grid_x": 51, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X18Y28", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y29": { + "bits": {}, + "grid_x": 51, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X18Y29", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y3": { + "bits": {}, + "grid_x": 51, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X18Y3", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y30": { + "bits": {}, + "grid_x": 51, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X18Y30", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y31": { + "bits": {}, + "grid_x": 51, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X18Y31", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y32": { + "bits": {}, + "grid_x": 51, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X18Y32", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y33": { + "bits": {}, + "grid_x": 51, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X18Y33", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y34": { + "bits": {}, + "grid_x": 51, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X18Y34", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y35": { + "bits": {}, + "grid_x": 51, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X18Y35", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y36": { + "bits": {}, + "grid_x": 51, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X18Y36", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y37": { + "bits": {}, + "grid_x": 51, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X18Y37", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y38": { + "bits": {}, + "grid_x": 51, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X18Y38", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y39": { + "bits": {}, + "grid_x": 51, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X18Y39", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y4": { + "bits": {}, + "grid_x": 51, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X18Y4", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y40": { + "bits": {}, + "grid_x": 51, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X18Y40", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y41": { + "bits": {}, + "grid_x": 51, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X18Y41", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y42": { + "bits": {}, + "grid_x": 51, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X18Y42", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y43": { + "bits": {}, + "grid_x": 51, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X18Y43", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y44": { + "bits": {}, + "grid_x": 51, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X18Y44", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y45": { + "bits": {}, + "grid_x": 51, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X18Y45", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y46": { + "bits": {}, + "grid_x": 51, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X18Y46", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y47": { + "bits": {}, + "grid_x": 51, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X18Y47", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y48": { + "bits": {}, + "grid_x": 51, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X18Y48", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y49": { + "bits": {}, + "grid_x": 51, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X18Y49", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y5": { + "bits": {}, + "grid_x": 51, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X18Y5", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y6": { + "bits": {}, + "grid_x": 51, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X18Y6", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y7": { + "bits": {}, + "grid_x": 51, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X18Y7", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y8": { + "bits": {}, + "grid_x": 51, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X18Y8", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X18Y9": { + "bits": {}, + "grid_x": 51, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X18Y9", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X20Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y0": { + "bits": {}, + "grid_x": 55, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X20Y0", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y1": { + "bits": {}, + "grid_x": 55, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X20Y1", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y10": { + "bits": {}, + "grid_x": 55, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X20Y10", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y11": { + "bits": {}, + "grid_x": 55, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X20Y11", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y12": { + "bits": {}, + "grid_x": 55, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X20Y12", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y13": { + "bits": {}, + "grid_x": 55, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X20Y13", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y14": { + "bits": {}, + "grid_x": 55, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X20Y14", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y15": { + "bits": {}, + "grid_x": 55, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X20Y15", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y150": { + "bits": {}, + "grid_x": 55, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X20Y150", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y151": { + "bits": {}, + "grid_x": 55, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X20Y151", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y152": { + "bits": {}, + "grid_x": 55, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X20Y152", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y153": { + "bits": {}, + "grid_x": 55, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X20Y153", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y154": { + "bits": {}, + "grid_x": 55, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X20Y154", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y155": { + "bits": {}, + "grid_x": 55, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X20Y155", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y156": { + "bits": {}, + "grid_x": 55, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X20Y156", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y157": { + "bits": {}, + "grid_x": 55, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X20Y157", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y158": { + "bits": {}, + "grid_x": 55, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X20Y158", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y159": { + "bits": {}, + "grid_x": 55, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X20Y159", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y16": { + "bits": {}, + "grid_x": 55, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X20Y16", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y160": { + "bits": {}, + "grid_x": 55, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X20Y160", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y161": { + "bits": {}, + "grid_x": 55, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X20Y161", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y162": { + "bits": {}, + "grid_x": 55, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X20Y162", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y163": { + "bits": {}, + "grid_x": 55, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X20Y163", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y164": { + "bits": {}, + "grid_x": 55, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X20Y164", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y165": { + "bits": {}, + "grid_x": 55, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X20Y165", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y166": { + "bits": {}, + "grid_x": 55, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X20Y166", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y167": { + "bits": {}, + "grid_x": 55, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X20Y167", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y168": { + "bits": {}, + "grid_x": 55, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X20Y168", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y169": { + "bits": {}, + "grid_x": 55, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X20Y169", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y17": { + "bits": {}, + "grid_x": 55, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X20Y17", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y170": { + "bits": {}, + "grid_x": 55, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X20Y170", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y171": { + "bits": {}, + "grid_x": 55, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X20Y171", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y172": { + "bits": {}, + "grid_x": 55, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X20Y172", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y173": { + "bits": {}, + "grid_x": 55, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X20Y173", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y174": { + "bits": {}, + "grid_x": 55, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X20Y174", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y175": { + "bits": {}, + "grid_x": 55, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X20Y175", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y176": { + "bits": {}, + "grid_x": 55, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X20Y176", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y177": { + "bits": {}, + "grid_x": 55, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X20Y177", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y178": { + "bits": {}, + "grid_x": 55, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X20Y178", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y179": { + "bits": {}, + "grid_x": 55, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X20Y179", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y18": { + "bits": {}, + "grid_x": 55, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X20Y18", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y180": { + "bits": {}, + "grid_x": 55, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X20Y180", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y181": { + "bits": {}, + "grid_x": 55, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X20Y181", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y182": { + "bits": {}, + "grid_x": 55, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X20Y182", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y183": { + "bits": {}, + "grid_x": 55, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X20Y183", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y184": { + "bits": {}, + "grid_x": 55, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X20Y184", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y185": { + "bits": {}, + "grid_x": 55, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X20Y185", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y186": { + "bits": {}, + "grid_x": 55, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X20Y186", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y187": { + "bits": {}, + "grid_x": 55, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X20Y187", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y188": { + "bits": {}, + "grid_x": 55, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X20Y188", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y189": { + "bits": {}, + "grid_x": 55, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X20Y189", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y19": { + "bits": {}, + "grid_x": 55, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X20Y19", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y190": { + "bits": {}, + "grid_x": 55, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X20Y190", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y191": { + "bits": {}, + "grid_x": 55, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X20Y191", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y192": { + "bits": {}, + "grid_x": 55, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X20Y192", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y193": { + "bits": {}, + "grid_x": 55, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X20Y193", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y194": { + "bits": {}, + "grid_x": 55, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X20Y194", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y195": { + "bits": {}, + "grid_x": 55, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X20Y195", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y196": { + "bits": {}, + "grid_x": 55, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X20Y196", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y197": { + "bits": {}, + "grid_x": 55, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X20Y197", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y198": { + "bits": {}, + "grid_x": 55, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X20Y198", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y199": { + "bits": {}, + "grid_x": 55, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X20Y199", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y2": { + "bits": {}, + "grid_x": 55, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X20Y2", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y20": { + "bits": {}, + "grid_x": 55, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X20Y20", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y21": { + "bits": {}, + "grid_x": 55, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X20Y21", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y22": { + "bits": {}, + "grid_x": 55, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X20Y22", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y23": { + "bits": {}, + "grid_x": 55, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X20Y23", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y24": { + "bits": {}, + "grid_x": 55, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X20Y24", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y25": { + "bits": {}, + "grid_x": 55, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X20Y25", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y26": { + "bits": {}, + "grid_x": 55, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X20Y26", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y27": { + "bits": {}, + "grid_x": 55, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X20Y27", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y28": { + "bits": {}, + "grid_x": 55, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X20Y28", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y29": { + "bits": {}, + "grid_x": 55, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X20Y29", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y3": { + "bits": {}, + "grid_x": 55, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X20Y3", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y30": { + "bits": {}, + "grid_x": 55, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X20Y30", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y31": { + "bits": {}, + "grid_x": 55, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X20Y31", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y32": { + "bits": {}, + "grid_x": 55, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X20Y32", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y33": { + "bits": {}, + "grid_x": 55, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X20Y33", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y34": { + "bits": {}, + "grid_x": 55, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X20Y34", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y35": { + "bits": {}, + "grid_x": 55, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X20Y35", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y36": { + "bits": {}, + "grid_x": 55, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X20Y36", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y37": { + "bits": {}, + "grid_x": 55, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X20Y37", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y38": { + "bits": {}, + "grid_x": 55, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X20Y38", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y39": { + "bits": {}, + "grid_x": 55, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X20Y39", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y4": { + "bits": {}, + "grid_x": 55, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X20Y4", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y40": { + "bits": {}, + "grid_x": 55, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X20Y40", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y41": { + "bits": {}, + "grid_x": 55, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X20Y41", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y42": { + "bits": {}, + "grid_x": 55, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X20Y42", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y43": { + "bits": {}, + "grid_x": 55, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X20Y43", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y44": { + "bits": {}, + "grid_x": 55, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X20Y44", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y45": { + "bits": {}, + "grid_x": 55, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X20Y45", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y46": { + "bits": {}, + "grid_x": 55, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X20Y46", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y47": { + "bits": {}, + "grid_x": 55, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X20Y47", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y48": { + "bits": {}, + "grid_x": 55, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X20Y48", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y49": { + "bits": {}, + "grid_x": 55, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X20Y49", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y5": { + "bits": {}, + "grid_x": 55, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X20Y5", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y6": { + "bits": {}, + "grid_x": 55, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X20Y6", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y7": { + "bits": {}, + "grid_x": 55, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X20Y7", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y8": { + "bits": {}, + "grid_x": 55, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X20Y8", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X20Y9": { + "bits": {}, + "grid_x": 55, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X20Y9", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X22Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y0": { + "bits": {}, + "grid_x": 59, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X22Y0", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y1": { + "bits": {}, + "grid_x": 59, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X22Y1", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y10": { + "bits": {}, + "grid_x": 59, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X22Y10", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y11": { + "bits": {}, + "grid_x": 59, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X22Y11", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y12": { + "bits": {}, + "grid_x": 59, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X22Y12", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y13": { + "bits": {}, + "grid_x": 59, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X22Y13", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y14": { + "bits": {}, + "grid_x": 59, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X22Y14", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y15": { + "bits": {}, + "grid_x": 59, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X22Y15", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y150": { + "bits": {}, + "grid_x": 59, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X22Y150", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y151": { + "bits": {}, + "grid_x": 59, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X22Y151", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y152": { + "bits": {}, + "grid_x": 59, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X22Y152", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y153": { + "bits": {}, + "grid_x": 59, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X22Y153", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y154": { + "bits": {}, + "grid_x": 59, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X22Y154", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y155": { + "bits": {}, + "grid_x": 59, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X22Y155", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y156": { + "bits": {}, + "grid_x": 59, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X22Y156", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y157": { + "bits": {}, + "grid_x": 59, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X22Y157", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y158": { + "bits": {}, + "grid_x": 59, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X22Y158", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y159": { + "bits": {}, + "grid_x": 59, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X22Y159", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y16": { + "bits": {}, + "grid_x": 59, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X22Y16", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y160": { + "bits": {}, + "grid_x": 59, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X22Y160", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y161": { + "bits": {}, + "grid_x": 59, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X22Y161", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y162": { + "bits": {}, + "grid_x": 59, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X22Y162", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y163": { + "bits": {}, + "grid_x": 59, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X22Y163", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y164": { + "bits": {}, + "grid_x": 59, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X22Y164", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y165": { + "bits": {}, + "grid_x": 59, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X22Y165", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y166": { + "bits": {}, + "grid_x": 59, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X22Y166", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y167": { + "bits": {}, + "grid_x": 59, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X22Y167", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y168": { + "bits": {}, + "grid_x": 59, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X22Y168", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y169": { + "bits": {}, + "grid_x": 59, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X22Y169", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y17": { + "bits": {}, + "grid_x": 59, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X22Y17", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y170": { + "bits": {}, + "grid_x": 59, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X22Y170", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y171": { + "bits": {}, + "grid_x": 59, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X22Y171", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y172": { + "bits": {}, + "grid_x": 59, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X22Y172", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y173": { + "bits": {}, + "grid_x": 59, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X22Y173", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y174": { + "bits": {}, + "grid_x": 59, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X22Y174", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y175": { + "bits": {}, + "grid_x": 59, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X22Y175", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y176": { + "bits": {}, + "grid_x": 59, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X22Y176", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y177": { + "bits": {}, + "grid_x": 59, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X22Y177", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y178": { + "bits": {}, + "grid_x": 59, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X22Y178", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y179": { + "bits": {}, + "grid_x": 59, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X22Y179", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y18": { + "bits": {}, + "grid_x": 59, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X22Y18", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y180": { + "bits": {}, + "grid_x": 59, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X22Y180", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y181": { + "bits": {}, + "grid_x": 59, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X22Y181", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y182": { + "bits": {}, + "grid_x": 59, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X22Y182", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y183": { + "bits": {}, + "grid_x": 59, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X22Y183", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y184": { + "bits": {}, + "grid_x": 59, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X22Y184", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y185": { + "bits": {}, + "grid_x": 59, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X22Y185", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y186": { + "bits": {}, + "grid_x": 59, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X22Y186", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y187": { + "bits": {}, + "grid_x": 59, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X22Y187", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y188": { + "bits": {}, + "grid_x": 59, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X22Y188", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y189": { + "bits": {}, + "grid_x": 59, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X22Y189", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y19": { + "bits": {}, + "grid_x": 59, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X22Y19", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y190": { + "bits": {}, + "grid_x": 59, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X22Y190", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y191": { + "bits": {}, + "grid_x": 59, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X22Y191", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y192": { + "bits": {}, + "grid_x": 59, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X22Y192", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y193": { + "bits": {}, + "grid_x": 59, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X22Y193", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y194": { + "bits": {}, + "grid_x": 59, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X22Y194", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y195": { + "bits": {}, + "grid_x": 59, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X22Y195", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y196": { + "bits": {}, + "grid_x": 59, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X22Y196", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y197": { + "bits": {}, + "grid_x": 59, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X22Y197", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y198": { + "bits": {}, + "grid_x": 59, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X22Y198", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y199": { + "bits": {}, + "grid_x": 59, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X22Y199", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y2": { + "bits": {}, + "grid_x": 59, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X22Y2", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y20": { + "bits": {}, + "grid_x": 59, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X22Y20", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y21": { + "bits": {}, + "grid_x": 59, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X22Y21", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y22": { + "bits": {}, + "grid_x": 59, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X22Y22", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y23": { + "bits": {}, + "grid_x": 59, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X22Y23", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y24": { + "bits": {}, + "grid_x": 59, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X22Y24", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y25": { + "bits": {}, + "grid_x": 59, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X22Y25", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y26": { + "bits": {}, + "grid_x": 59, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X22Y26", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y27": { + "bits": {}, + "grid_x": 59, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X22Y27", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y28": { + "bits": {}, + "grid_x": 59, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X22Y28", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y29": { + "bits": {}, + "grid_x": 59, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X22Y29", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y3": { + "bits": {}, + "grid_x": 59, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X22Y3", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y30": { + "bits": {}, + "grid_x": 59, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X22Y30", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y31": { + "bits": {}, + "grid_x": 59, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X22Y31", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y32": { + "bits": {}, + "grid_x": 59, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X22Y32", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y33": { + "bits": {}, + "grid_x": 59, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X22Y33", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y34": { + "bits": {}, + "grid_x": 59, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X22Y34", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y35": { + "bits": {}, + "grid_x": 59, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X22Y35", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y36": { + "bits": {}, + "grid_x": 59, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X22Y36", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y37": { + "bits": {}, + "grid_x": 59, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X22Y37", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y38": { + "bits": {}, + "grid_x": 59, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X22Y38", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y39": { + "bits": {}, + "grid_x": 59, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X22Y39", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y4": { + "bits": {}, + "grid_x": 59, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X22Y4", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y40": { + "bits": {}, + "grid_x": 59, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X22Y40", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y41": { + "bits": {}, + "grid_x": 59, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X22Y41", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y42": { + "bits": {}, + "grid_x": 59, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X22Y42", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y43": { + "bits": {}, + "grid_x": 59, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X22Y43", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y44": { + "bits": {}, + "grid_x": 59, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X22Y44", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y45": { + "bits": {}, + "grid_x": 59, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X22Y45", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y46": { + "bits": {}, + "grid_x": 59, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X22Y46", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y47": { + "bits": {}, + "grid_x": 59, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X22Y47", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y48": { + "bits": {}, + "grid_x": 59, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X22Y48", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y49": { + "bits": {}, + "grid_x": 59, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X22Y49", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y5": { + "bits": {}, + "grid_x": 59, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X22Y5", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y6": { + "bits": {}, + "grid_x": 59, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X22Y6", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y7": { + "bits": {}, + "grid_x": 59, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X22Y7", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y8": { + "bits": {}, + "grid_x": 59, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X22Y8", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X22Y9": { + "bits": {}, + "grid_x": 59, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X22Y9", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X24Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y0": { + "bits": {}, + "grid_x": 64, + "grid_y": 207, + "sites": { + "TIEOFF_X26Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y1": { + "bits": {}, + "grid_x": 64, + "grid_y": 206, + "sites": { + "TIEOFF_X26Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y10": { + "bits": {}, + "grid_x": 64, + "grid_y": 197, + "sites": { + "TIEOFF_X26Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y100": { + "bits": {}, + "grid_x": 64, + "grid_y": 103, + "sites": { + "TIEOFF_X26Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y101": { + "bits": {}, + "grid_x": 64, + "grid_y": 102, + "sites": { + "TIEOFF_X26Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y102": { + "bits": {}, + "grid_x": 64, + "grid_y": 101, + "sites": { + "TIEOFF_X26Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y103": { + "bits": {}, + "grid_x": 64, + "grid_y": 100, + "sites": { + "TIEOFF_X26Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y104": { + "bits": {}, + "grid_x": 64, + "grid_y": 99, + "sites": { + "TIEOFF_X26Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y105": { + "bits": {}, + "grid_x": 64, + "grid_y": 98, + "sites": { + "TIEOFF_X26Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y106": { + "bits": {}, + "grid_x": 64, + "grid_y": 97, + "sites": { + "TIEOFF_X26Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y107": { + "bits": {}, + "grid_x": 64, + "grid_y": 96, + "sites": { + "TIEOFF_X26Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y108": { + "bits": {}, + "grid_x": 64, + "grid_y": 95, + "sites": { + "TIEOFF_X26Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y109": { + "bits": {}, + "grid_x": 64, + "grid_y": 94, + "sites": { + "TIEOFF_X26Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y11": { + "bits": {}, + "grid_x": 64, + "grid_y": 196, + "sites": { + "TIEOFF_X26Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y110": { + "bits": {}, + "grid_x": 64, + "grid_y": 93, + "sites": { + "TIEOFF_X26Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y111": { + "bits": {}, + "grid_x": 64, + "grid_y": 92, + "sites": { + "TIEOFF_X26Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y112": { + "bits": {}, + "grid_x": 64, + "grid_y": 91, + "sites": { + "TIEOFF_X26Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y113": { + "bits": {}, + "grid_x": 64, + "grid_y": 90, + "sites": { + "TIEOFF_X26Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y114": { + "bits": {}, + "grid_x": 64, + "grid_y": 89, + "sites": { + "TIEOFF_X26Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y115": { + "bits": {}, + "grid_x": 64, + "grid_y": 88, + "sites": { + "TIEOFF_X26Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y116": { + "bits": {}, + "grid_x": 64, + "grid_y": 87, + "sites": { + "TIEOFF_X26Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y117": { + "bits": {}, + "grid_x": 64, + "grid_y": 86, + "sites": { + "TIEOFF_X26Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y118": { + "bits": {}, + "grid_x": 64, + "grid_y": 85, + "sites": { + "TIEOFF_X26Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y119": { + "bits": {}, + "grid_x": 64, + "grid_y": 84, + "sites": { + "TIEOFF_X26Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y12": { + "bits": {}, + "grid_x": 64, + "grid_y": 195, + "sites": { + "TIEOFF_X26Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y120": { + "bits": {}, + "grid_x": 64, + "grid_y": 83, + "sites": { + "TIEOFF_X26Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y121": { + "bits": {}, + "grid_x": 64, + "grid_y": 82, + "sites": { + "TIEOFF_X26Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y122": { + "bits": {}, + "grid_x": 64, + "grid_y": 81, + "sites": { + "TIEOFF_X26Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y123": { + "bits": {}, + "grid_x": 64, + "grid_y": 80, + "sites": { + "TIEOFF_X26Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y124": { + "bits": {}, + "grid_x": 64, + "grid_y": 79, + "sites": { + "TIEOFF_X26Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y125": { + "bits": {}, + "grid_x": 64, + "grid_y": 77, + "sites": { + "TIEOFF_X26Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y126": { + "bits": {}, + "grid_x": 64, + "grid_y": 76, + "sites": { + "TIEOFF_X26Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y127": { + "bits": {}, + "grid_x": 64, + "grid_y": 75, + "sites": { + "TIEOFF_X26Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y128": { + "bits": {}, + "grid_x": 64, + "grid_y": 74, + "sites": { + "TIEOFF_X26Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y129": { + "bits": {}, + "grid_x": 64, + "grid_y": 73, + "sites": { + "TIEOFF_X26Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y13": { + "bits": {}, + "grid_x": 64, + "grid_y": 194, + "sites": { + "TIEOFF_X26Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y130": { + "bits": {}, + "grid_x": 64, + "grid_y": 72, + "sites": { + "TIEOFF_X26Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y131": { + "bits": {}, + "grid_x": 64, + "grid_y": 71, + "sites": { + "TIEOFF_X26Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y132": { + "bits": {}, + "grid_x": 64, + "grid_y": 70, + "sites": { + "TIEOFF_X26Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y133": { + "bits": {}, + "grid_x": 64, + "grid_y": 69, + "sites": { + "TIEOFF_X26Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y134": { + "bits": {}, + "grid_x": 64, + "grid_y": 68, + "sites": { + "TIEOFF_X26Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y135": { + "bits": {}, + "grid_x": 64, + "grid_y": 67, + "sites": { + "TIEOFF_X26Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y136": { + "bits": {}, + "grid_x": 64, + "grid_y": 66, + "sites": { + "TIEOFF_X26Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y137": { + "bits": {}, + "grid_x": 64, + "grid_y": 65, + "sites": { + "TIEOFF_X26Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y138": { + "bits": {}, + "grid_x": 64, + "grid_y": 64, + "sites": { + "TIEOFF_X26Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y139": { + "bits": {}, + "grid_x": 64, + "grid_y": 63, + "sites": { + "TIEOFF_X26Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y14": { + "bits": {}, + "grid_x": 64, + "grid_y": 193, + "sites": { + "TIEOFF_X26Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y140": { + "bits": {}, + "grid_x": 64, + "grid_y": 62, + "sites": { + "TIEOFF_X26Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y141": { + "bits": {}, + "grid_x": 64, + "grid_y": 61, + "sites": { + "TIEOFF_X26Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y142": { + "bits": {}, + "grid_x": 64, + "grid_y": 60, + "sites": { + "TIEOFF_X26Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y143": { + "bits": {}, + "grid_x": 64, + "grid_y": 59, + "sites": { + "TIEOFF_X26Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y144": { + "bits": {}, + "grid_x": 64, + "grid_y": 58, + "sites": { + "TIEOFF_X26Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y145": { + "bits": {}, + "grid_x": 64, + "grid_y": 57, + "sites": { + "TIEOFF_X26Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y146": { + "bits": {}, + "grid_x": 64, + "grid_y": 56, + "sites": { + "TIEOFF_X26Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y147": { + "bits": {}, + "grid_x": 64, + "grid_y": 55, + "sites": { + "TIEOFF_X26Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y148": { + "bits": {}, + "grid_x": 64, + "grid_y": 54, + "sites": { + "TIEOFF_X26Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y149": { + "bits": {}, + "grid_x": 64, + "grid_y": 53, + "sites": { + "TIEOFF_X26Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y15": { + "bits": {}, + "grid_x": 64, + "grid_y": 192, + "sites": { + "TIEOFF_X26Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y150": { + "bits": {}, + "grid_x": 64, + "grid_y": 51, + "sites": { + "TIEOFF_X26Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y151": { + "bits": {}, + "grid_x": 64, + "grid_y": 50, + "sites": { + "TIEOFF_X26Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y152": { + "bits": {}, + "grid_x": 64, + "grid_y": 49, + "sites": { + "TIEOFF_X26Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y153": { + "bits": {}, + "grid_x": 64, + "grid_y": 48, + "sites": { + "TIEOFF_X26Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y154": { + "bits": {}, + "grid_x": 64, + "grid_y": 47, + "sites": { + "TIEOFF_X26Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y155": { + "bits": {}, + "grid_x": 64, + "grid_y": 46, + "sites": { + "TIEOFF_X26Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y156": { + "bits": {}, + "grid_x": 64, + "grid_y": 45, + "sites": { + "TIEOFF_X26Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y157": { + "bits": {}, + "grid_x": 64, + "grid_y": 44, + "sites": { + "TIEOFF_X26Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y158": { + "bits": {}, + "grid_x": 64, + "grid_y": 43, + "sites": { + "TIEOFF_X26Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y159": { + "bits": {}, + "grid_x": 64, + "grid_y": 42, + "sites": { + "TIEOFF_X26Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y16": { + "bits": {}, + "grid_x": 64, + "grid_y": 191, + "sites": { + "TIEOFF_X26Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y160": { + "bits": {}, + "grid_x": 64, + "grid_y": 41, + "sites": { + "TIEOFF_X26Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y161": { + "bits": {}, + "grid_x": 64, + "grid_y": 40, + "sites": { + "TIEOFF_X26Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y162": { + "bits": {}, + "grid_x": 64, + "grid_y": 39, + "sites": { + "TIEOFF_X26Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y163": { + "bits": {}, + "grid_x": 64, + "grid_y": 38, + "sites": { + "TIEOFF_X26Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y164": { + "bits": {}, + "grid_x": 64, + "grid_y": 37, + "sites": { + "TIEOFF_X26Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y165": { + "bits": {}, + "grid_x": 64, + "grid_y": 36, + "sites": { + "TIEOFF_X26Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y166": { + "bits": {}, + "grid_x": 64, + "grid_y": 35, + "sites": { + "TIEOFF_X26Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y167": { + "bits": {}, + "grid_x": 64, + "grid_y": 34, + "sites": { + "TIEOFF_X26Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y168": { + "bits": {}, + "grid_x": 64, + "grid_y": 33, + "sites": { + "TIEOFF_X26Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y169": { + "bits": {}, + "grid_x": 64, + "grid_y": 32, + "sites": { + "TIEOFF_X26Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y17": { + "bits": {}, + "grid_x": 64, + "grid_y": 190, + "sites": { + "TIEOFF_X26Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y170": { + "bits": {}, + "grid_x": 64, + "grid_y": 31, + "sites": { + "TIEOFF_X26Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y171": { + "bits": {}, + "grid_x": 64, + "grid_y": 30, + "sites": { + "TIEOFF_X26Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y172": { + "bits": {}, + "grid_x": 64, + "grid_y": 29, + "sites": { + "TIEOFF_X26Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y173": { + "bits": {}, + "grid_x": 64, + "grid_y": 28, + "sites": { + "TIEOFF_X26Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y174": { + "bits": {}, + "grid_x": 64, + "grid_y": 27, + "sites": { + "TIEOFF_X26Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y175": { + "bits": {}, + "grid_x": 64, + "grid_y": 25, + "sites": { + "TIEOFF_X26Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y176": { + "bits": {}, + "grid_x": 64, + "grid_y": 24, + "sites": { + "TIEOFF_X26Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y177": { + "bits": {}, + "grid_x": 64, + "grid_y": 23, + "sites": { + "TIEOFF_X26Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y178": { + "bits": {}, + "grid_x": 64, + "grid_y": 22, + "sites": { + "TIEOFF_X26Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y179": { + "bits": {}, + "grid_x": 64, + "grid_y": 21, + "sites": { + "TIEOFF_X26Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y18": { + "bits": {}, + "grid_x": 64, + "grid_y": 189, + "sites": { + "TIEOFF_X26Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y180": { + "bits": {}, + "grid_x": 64, + "grid_y": 20, + "sites": { + "TIEOFF_X26Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y181": { + "bits": {}, + "grid_x": 64, + "grid_y": 19, + "sites": { + "TIEOFF_X26Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y182": { + "bits": {}, + "grid_x": 64, + "grid_y": 18, + "sites": { + "TIEOFF_X26Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y183": { + "bits": {}, + "grid_x": 64, + "grid_y": 17, + "sites": { + "TIEOFF_X26Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y184": { + "bits": {}, + "grid_x": 64, + "grid_y": 16, + "sites": { + "TIEOFF_X26Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y185": { + "bits": {}, + "grid_x": 64, + "grid_y": 15, + "sites": { + "TIEOFF_X26Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y186": { + "bits": {}, + "grid_x": 64, + "grid_y": 14, + "sites": { + "TIEOFF_X26Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y187": { + "bits": {}, + "grid_x": 64, + "grid_y": 13, + "sites": { + "TIEOFF_X26Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y188": { + "bits": {}, + "grid_x": 64, + "grid_y": 12, + "sites": { + "TIEOFF_X26Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y189": { + "bits": {}, + "grid_x": 64, + "grid_y": 11, + "sites": { + "TIEOFF_X26Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y19": { + "bits": {}, + "grid_x": 64, + "grid_y": 188, + "sites": { + "TIEOFF_X26Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y190": { + "bits": {}, + "grid_x": 64, + "grid_y": 10, + "sites": { + "TIEOFF_X26Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y191": { + "bits": {}, + "grid_x": 64, + "grid_y": 9, + "sites": { + "TIEOFF_X26Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y192": { + "bits": {}, + "grid_x": 64, + "grid_y": 8, + "sites": { + "TIEOFF_X26Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y193": { + "bits": {}, + "grid_x": 64, + "grid_y": 7, + "sites": { + "TIEOFF_X26Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y194": { + "bits": {}, + "grid_x": 64, + "grid_y": 6, + "sites": { + "TIEOFF_X26Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y195": { + "bits": {}, + "grid_x": 64, + "grid_y": 5, + "sites": { + "TIEOFF_X26Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y196": { + "bits": {}, + "grid_x": 64, + "grid_y": 4, + "sites": { + "TIEOFF_X26Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y197": { + "bits": {}, + "grid_x": 64, + "grid_y": 3, + "sites": { + "TIEOFF_X26Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y198": { + "bits": {}, + "grid_x": 64, + "grid_y": 2, + "sites": { + "TIEOFF_X26Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y199": { + "bits": {}, + "grid_x": 64, + "grid_y": 1, + "sites": { + "TIEOFF_X26Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y2": { + "bits": {}, + "grid_x": 64, + "grid_y": 205, + "sites": { + "TIEOFF_X26Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y20": { + "bits": {}, + "grid_x": 64, + "grid_y": 187, + "sites": { + "TIEOFF_X26Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y21": { + "bits": {}, + "grid_x": 64, + "grid_y": 186, + "sites": { + "TIEOFF_X26Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y22": { + "bits": {}, + "grid_x": 64, + "grid_y": 185, + "sites": { + "TIEOFF_X26Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y23": { + "bits": {}, + "grid_x": 64, + "grid_y": 184, + "sites": { + "TIEOFF_X26Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y24": { + "bits": {}, + "grid_x": 64, + "grid_y": 183, + "sites": { + "TIEOFF_X26Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y25": { + "bits": {}, + "grid_x": 64, + "grid_y": 181, + "sites": { + "TIEOFF_X26Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y26": { + "bits": {}, + "grid_x": 64, + "grid_y": 180, + "sites": { + "TIEOFF_X26Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y27": { + "bits": {}, + "grid_x": 64, + "grid_y": 179, + "sites": { + "TIEOFF_X26Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y28": { + "bits": {}, + "grid_x": 64, + "grid_y": 178, + "sites": { + "TIEOFF_X26Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y29": { + "bits": {}, + "grid_x": 64, + "grid_y": 177, + "sites": { + "TIEOFF_X26Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y3": { + "bits": {}, + "grid_x": 64, + "grid_y": 204, + "sites": { + "TIEOFF_X26Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y30": { + "bits": {}, + "grid_x": 64, + "grid_y": 176, + "sites": { + "TIEOFF_X26Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y31": { + "bits": {}, + "grid_x": 64, + "grid_y": 175, + "sites": { + "TIEOFF_X26Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y32": { + "bits": {}, + "grid_x": 64, + "grid_y": 174, + "sites": { + "TIEOFF_X26Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y33": { + "bits": {}, + "grid_x": 64, + "grid_y": 173, + "sites": { + "TIEOFF_X26Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y34": { + "bits": {}, + "grid_x": 64, + "grid_y": 172, + "sites": { + "TIEOFF_X26Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y35": { + "bits": {}, + "grid_x": 64, + "grid_y": 171, + "sites": { + "TIEOFF_X26Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y36": { + "bits": {}, + "grid_x": 64, + "grid_y": 170, + "sites": { + "TIEOFF_X26Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y37": { + "bits": {}, + "grid_x": 64, + "grid_y": 169, + "sites": { + "TIEOFF_X26Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y38": { + "bits": {}, + "grid_x": 64, + "grid_y": 168, + "sites": { + "TIEOFF_X26Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y39": { + "bits": {}, + "grid_x": 64, + "grid_y": 167, + "sites": { + "TIEOFF_X26Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y4": { + "bits": {}, + "grid_x": 64, + "grid_y": 203, + "sites": { + "TIEOFF_X26Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y40": { + "bits": {}, + "grid_x": 64, + "grid_y": 166, + "sites": { + "TIEOFF_X26Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y41": { + "bits": {}, + "grid_x": 64, + "grid_y": 165, + "sites": { + "TIEOFF_X26Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y42": { + "bits": {}, + "grid_x": 64, + "grid_y": 164, + "sites": { + "TIEOFF_X26Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y43": { + "bits": {}, + "grid_x": 64, + "grid_y": 163, + "sites": { + "TIEOFF_X26Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y44": { + "bits": {}, + "grid_x": 64, + "grid_y": 162, + "sites": { + "TIEOFF_X26Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y45": { + "bits": {}, + "grid_x": 64, + "grid_y": 161, + "sites": { + "TIEOFF_X26Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y46": { + "bits": {}, + "grid_x": 64, + "grid_y": 160, + "sites": { + "TIEOFF_X26Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y47": { + "bits": {}, + "grid_x": 64, + "grid_y": 159, + "sites": { + "TIEOFF_X26Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y48": { + "bits": {}, + "grid_x": 64, + "grid_y": 158, + "sites": { + "TIEOFF_X26Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y49": { + "bits": {}, + "grid_x": 64, + "grid_y": 157, + "sites": { + "TIEOFF_X26Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y5": { + "bits": {}, + "grid_x": 64, + "grid_y": 202, + "sites": { + "TIEOFF_X26Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y50": { + "bits": {}, + "grid_x": 64, + "grid_y": 155, + "sites": { + "TIEOFF_X26Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y51": { + "bits": {}, + "grid_x": 64, + "grid_y": 154, + "sites": { + "TIEOFF_X26Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y52": { + "bits": {}, + "grid_x": 64, + "grid_y": 153, + "sites": { + "TIEOFF_X26Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y53": { + "bits": {}, + "grid_x": 64, + "grid_y": 152, + "sites": { + "TIEOFF_X26Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y54": { + "bits": {}, + "grid_x": 64, + "grid_y": 151, + "sites": { + "TIEOFF_X26Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y55": { + "bits": {}, + "grid_x": 64, + "grid_y": 150, + "sites": { + "TIEOFF_X26Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y56": { + "bits": {}, + "grid_x": 64, + "grid_y": 149, + "sites": { + "TIEOFF_X26Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y57": { + "bits": {}, + "grid_x": 64, + "grid_y": 148, + "sites": { + "TIEOFF_X26Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y58": { + "bits": {}, + "grid_x": 64, + "grid_y": 147, + "sites": { + "TIEOFF_X26Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y59": { + "bits": {}, + "grid_x": 64, + "grid_y": 146, + "sites": { + "TIEOFF_X26Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y6": { + "bits": {}, + "grid_x": 64, + "grid_y": 201, + "sites": { + "TIEOFF_X26Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y60": { + "bits": {}, + "grid_x": 64, + "grid_y": 145, + "sites": { + "TIEOFF_X26Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y61": { + "bits": {}, + "grid_x": 64, + "grid_y": 144, + "sites": { + "TIEOFF_X26Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y62": { + "bits": {}, + "grid_x": 64, + "grid_y": 143, + "sites": { + "TIEOFF_X26Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y63": { + "bits": {}, + "grid_x": 64, + "grid_y": 142, + "sites": { + "TIEOFF_X26Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y64": { + "bits": {}, + "grid_x": 64, + "grid_y": 141, + "sites": { + "TIEOFF_X26Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y65": { + "bits": {}, + "grid_x": 64, + "grid_y": 140, + "sites": { + "TIEOFF_X26Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y66": { + "bits": {}, + "grid_x": 64, + "grid_y": 139, + "sites": { + "TIEOFF_X26Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y67": { + "bits": {}, + "grid_x": 64, + "grid_y": 138, + "sites": { + "TIEOFF_X26Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y68": { + "bits": {}, + "grid_x": 64, + "grid_y": 137, + "sites": { + "TIEOFF_X26Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y69": { + "bits": {}, + "grid_x": 64, + "grid_y": 136, + "sites": { + "TIEOFF_X26Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y7": { + "bits": {}, + "grid_x": 64, + "grid_y": 200, + "sites": { + "TIEOFF_X26Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y70": { + "bits": {}, + "grid_x": 64, + "grid_y": 135, + "sites": { + "TIEOFF_X26Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y71": { + "bits": {}, + "grid_x": 64, + "grid_y": 134, + "sites": { + "TIEOFF_X26Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y72": { + "bits": {}, + "grid_x": 64, + "grid_y": 133, + "sites": { + "TIEOFF_X26Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y73": { + "bits": {}, + "grid_x": 64, + "grid_y": 132, + "sites": { + "TIEOFF_X26Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y74": { + "bits": {}, + "grid_x": 64, + "grid_y": 131, + "sites": { + "TIEOFF_X26Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y75": { + "bits": {}, + "grid_x": 64, + "grid_y": 129, + "sites": { + "TIEOFF_X26Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y76": { + "bits": {}, + "grid_x": 64, + "grid_y": 128, + "sites": { + "TIEOFF_X26Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y77": { + "bits": {}, + "grid_x": 64, + "grid_y": 127, + "sites": { + "TIEOFF_X26Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y78": { + "bits": {}, + "grid_x": 64, + "grid_y": 126, + "sites": { + "TIEOFF_X26Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y79": { + "bits": {}, + "grid_x": 64, + "grid_y": 125, + "sites": { + "TIEOFF_X26Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y8": { + "bits": {}, + "grid_x": 64, + "grid_y": 199, + "sites": { + "TIEOFF_X26Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y80": { + "bits": {}, + "grid_x": 64, + "grid_y": 124, + "sites": { + "TIEOFF_X26Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y81": { + "bits": {}, + "grid_x": 64, + "grid_y": 123, + "sites": { + "TIEOFF_X26Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y82": { + "bits": {}, + "grid_x": 64, + "grid_y": 122, + "sites": { + "TIEOFF_X26Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y83": { + "bits": {}, + "grid_x": 64, + "grid_y": 121, + "sites": { + "TIEOFF_X26Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y84": { + "bits": {}, + "grid_x": 64, + "grid_y": 120, + "sites": { + "TIEOFF_X26Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y85": { + "bits": {}, + "grid_x": 64, + "grid_y": 119, + "sites": { + "TIEOFF_X26Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y86": { + "bits": {}, + "grid_x": 64, + "grid_y": 118, + "sites": { + "TIEOFF_X26Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y87": { + "bits": {}, + "grid_x": 64, + "grid_y": 117, + "sites": { + "TIEOFF_X26Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y88": { + "bits": {}, + "grid_x": 64, + "grid_y": 116, + "sites": { + "TIEOFF_X26Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y89": { + "bits": {}, + "grid_x": 64, + "grid_y": 115, + "sites": { + "TIEOFF_X26Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y9": { + "bits": {}, + "grid_x": 64, + "grid_y": 198, + "sites": { + "TIEOFF_X26Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y90": { + "bits": {}, + "grid_x": 64, + "grid_y": 114, + "sites": { + "TIEOFF_X26Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y91": { + "bits": {}, + "grid_x": 64, + "grid_y": 113, + "sites": { + "TIEOFF_X26Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y92": { + "bits": {}, + "grid_x": 64, + "grid_y": 112, + "sites": { + "TIEOFF_X26Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y93": { + "bits": {}, + "grid_x": 64, + "grid_y": 111, + "sites": { + "TIEOFF_X26Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y94": { + "bits": {}, + "grid_x": 64, + "grid_y": 110, + "sites": { + "TIEOFF_X26Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y95": { + "bits": {}, + "grid_x": 64, + "grid_y": 109, + "sites": { + "TIEOFF_X26Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y96": { + "bits": {}, + "grid_x": 64, + "grid_y": 108, + "sites": { + "TIEOFF_X26Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y97": { + "bits": {}, + "grid_x": 64, + "grid_y": 107, + "sites": { + "TIEOFF_X26Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y98": { + "bits": {}, + "grid_x": 64, + "grid_y": 106, + "sites": { + "TIEOFF_X26Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X24Y99": { + "bits": {}, + "grid_x": 64, + "grid_y": 105, + "sites": { + "TIEOFF_X26Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y0": { + "bits": {}, + "grid_x": 70, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X26Y0", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y1": { + "bits": {}, + "grid_x": 70, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X26Y1", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y10": { + "bits": {}, + "grid_x": 70, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X26Y10", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y100": { + "bits": {}, + "grid_x": 70, + "grid_y": 103, + "segment": "SEG_CLBLL_L_X26Y100", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y101": { + "bits": {}, + "grid_x": 70, + "grid_y": 102, + "segment": "SEG_CLBLL_L_X26Y101", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y102": { + "bits": {}, + "grid_x": 70, + "grid_y": 101, + "segment": "SEG_CLBLL_L_X26Y102", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y103": { + "bits": {}, + "grid_x": 70, + "grid_y": 100, + "segment": "SEG_CLBLL_L_X26Y103", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y104": { + "bits": {}, + "grid_x": 70, + "grid_y": 99, + "segment": "SEG_CLBLL_L_X26Y104", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y105": { + "bits": {}, + "grid_x": 70, + "grid_y": 98, + "segment": "SEG_CLBLL_L_X26Y105", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y106": { + "bits": {}, + "grid_x": 70, + "grid_y": 97, + "segment": "SEG_CLBLL_L_X26Y106", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y107": { + "bits": {}, + "grid_x": 70, + "grid_y": 96, + "segment": "SEG_CLBLL_L_X26Y107", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y108": { + "bits": {}, + "grid_x": 70, + "grid_y": 95, + "segment": "SEG_CLBLL_L_X26Y108", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y109": { + "bits": {}, + "grid_x": 70, + "grid_y": 94, + "segment": "SEG_CLBLL_L_X26Y109", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y11": { + "bits": {}, + "grid_x": 70, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X26Y11", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y110": { + "bits": {}, + "grid_x": 70, + "grid_y": 93, + "segment": "SEG_CLBLL_L_X26Y110", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y111": { + "bits": {}, + "grid_x": 70, + "grid_y": 92, + "segment": "SEG_CLBLL_L_X26Y111", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y112": { + "bits": {}, + "grid_x": 70, + "grid_y": 91, + "segment": "SEG_CLBLL_L_X26Y112", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y113": { + "bits": {}, + "grid_x": 70, + "grid_y": 90, + "segment": "SEG_CLBLL_L_X26Y113", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y114": { + "bits": {}, + "grid_x": 70, + "grid_y": 89, + "segment": "SEG_CLBLL_L_X26Y114", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y115": { + "bits": {}, + "grid_x": 70, + "grid_y": 88, + "segment": "SEG_CLBLL_L_X26Y115", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y116": { + "bits": {}, + "grid_x": 70, + "grid_y": 87, + "segment": "SEG_CLBLL_L_X26Y116", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y117": { + "bits": {}, + "grid_x": 70, + "grid_y": 86, + "segment": "SEG_CLBLL_L_X26Y117", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y118": { + "bits": {}, + "grid_x": 70, + "grid_y": 85, + "segment": "SEG_CLBLL_L_X26Y118", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y119": { + "bits": {}, + "grid_x": 70, + "grid_y": 84, + "segment": "SEG_CLBLL_L_X26Y119", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y12": { + "bits": {}, + "grid_x": 70, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X26Y12", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y120": { + "bits": {}, + "grid_x": 70, + "grid_y": 83, + "segment": "SEG_CLBLL_L_X26Y120", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y121": { + "bits": {}, + "grid_x": 70, + "grid_y": 82, + "segment": "SEG_CLBLL_L_X26Y121", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y122": { + "bits": {}, + "grid_x": 70, + "grid_y": 81, + "segment": "SEG_CLBLL_L_X26Y122", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y123": { + "bits": {}, + "grid_x": 70, + "grid_y": 80, + "segment": "SEG_CLBLL_L_X26Y123", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y124": { + "bits": {}, + "grid_x": 70, + "grid_y": 79, + "segment": "SEG_CLBLL_L_X26Y124", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y125": { + "bits": {}, + "grid_x": 70, + "grid_y": 77, + "segment": "SEG_CLBLL_L_X26Y125", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y126": { + "bits": {}, + "grid_x": 70, + "grid_y": 76, + "segment": "SEG_CLBLL_L_X26Y126", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y127": { + "bits": {}, + "grid_x": 70, + "grid_y": 75, + "segment": "SEG_CLBLL_L_X26Y127", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y128": { + "bits": {}, + "grid_x": 70, + "grid_y": 74, + "segment": "SEG_CLBLL_L_X26Y128", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y129": { + "bits": {}, + "grid_x": 70, + "grid_y": 73, + "segment": "SEG_CLBLL_L_X26Y129", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y13": { + "bits": {}, + "grid_x": 70, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X26Y13", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y130": { + "bits": {}, + "grid_x": 70, + "grid_y": 72, + "segment": "SEG_CLBLL_L_X26Y130", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y131": { + "bits": {}, + "grid_x": 70, + "grid_y": 71, + "segment": "SEG_CLBLL_L_X26Y131", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y132": { + "bits": {}, + "grid_x": 70, + "grid_y": 70, + "segment": "SEG_CLBLL_L_X26Y132", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y133": { + "bits": {}, + "grid_x": 70, + "grid_y": 69, + "segment": "SEG_CLBLL_L_X26Y133", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y134": { + "bits": {}, + "grid_x": 70, + "grid_y": 68, + "segment": "SEG_CLBLL_L_X26Y134", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y135": { + "bits": {}, + "grid_x": 70, + "grid_y": 67, + "segment": "SEG_CLBLL_L_X26Y135", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y136": { + "bits": {}, + "grid_x": 70, + "grid_y": 66, + "segment": "SEG_CLBLL_L_X26Y136", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y137": { + "bits": {}, + "grid_x": 70, + "grid_y": 65, + "segment": "SEG_CLBLL_L_X26Y137", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y138": { + "bits": {}, + "grid_x": 70, + "grid_y": 64, + "segment": "SEG_CLBLL_L_X26Y138", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y139": { + "bits": {}, + "grid_x": 70, + "grid_y": 63, + "segment": "SEG_CLBLL_L_X26Y139", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y14": { + "bits": {}, + "grid_x": 70, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X26Y14", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y140": { + "bits": {}, + "grid_x": 70, + "grid_y": 62, + "segment": "SEG_CLBLL_L_X26Y140", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y141": { + "bits": {}, + "grid_x": 70, + "grid_y": 61, + "segment": "SEG_CLBLL_L_X26Y141", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y142": { + "bits": {}, + "grid_x": 70, + "grid_y": 60, + "segment": "SEG_CLBLL_L_X26Y142", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y143": { + "bits": {}, + "grid_x": 70, + "grid_y": 59, + "segment": "SEG_CLBLL_L_X26Y143", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y144": { + "bits": {}, + "grid_x": 70, + "grid_y": 58, + "segment": "SEG_CLBLL_L_X26Y144", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y145": { + "bits": {}, + "grid_x": 70, + "grid_y": 57, + "segment": "SEG_CLBLL_L_X26Y145", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y146": { + "bits": {}, + "grid_x": 70, + "grid_y": 56, + "segment": "SEG_CLBLL_L_X26Y146", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y147": { + "bits": {}, + "grid_x": 70, + "grid_y": 55, + "segment": "SEG_CLBLL_L_X26Y147", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y148": { + "bits": {}, + "grid_x": 70, + "grid_y": 54, + "segment": "SEG_CLBLL_L_X26Y148", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y149": { + "bits": {}, + "grid_x": 70, + "grid_y": 53, + "segment": "SEG_CLBLL_L_X26Y149", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y15": { + "bits": {}, + "grid_x": 70, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X26Y15", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y150": { + "bits": {}, + "grid_x": 70, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X26Y150", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y151": { + "bits": {}, + "grid_x": 70, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X26Y151", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y152": { + "bits": {}, + "grid_x": 70, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X26Y152", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y153": { + "bits": {}, + "grid_x": 70, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X26Y153", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y154": { + "bits": {}, + "grid_x": 70, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X26Y154", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y155": { + "bits": {}, + "grid_x": 70, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X26Y155", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y156": { + "bits": {}, + "grid_x": 70, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X26Y156", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y157": { + "bits": {}, + "grid_x": 70, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X26Y157", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y158": { + "bits": {}, + "grid_x": 70, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X26Y158", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y159": { + "bits": {}, + "grid_x": 70, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X26Y159", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y16": { + "bits": {}, + "grid_x": 70, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X26Y16", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y160": { + "bits": {}, + "grid_x": 70, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X26Y160", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y161": { + "bits": {}, + "grid_x": 70, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X26Y161", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y162": { + "bits": {}, + "grid_x": 70, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X26Y162", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y163": { + "bits": {}, + "grid_x": 70, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X26Y163", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y164": { + "bits": {}, + "grid_x": 70, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X26Y164", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y165": { + "bits": {}, + "grid_x": 70, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X26Y165", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y166": { + "bits": {}, + "grid_x": 70, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X26Y166", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y167": { + "bits": {}, + "grid_x": 70, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X26Y167", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y168": { + "bits": {}, + "grid_x": 70, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X26Y168", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y169": { + "bits": {}, + "grid_x": 70, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X26Y169", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y17": { + "bits": {}, + "grid_x": 70, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X26Y17", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y170": { + "bits": {}, + "grid_x": 70, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X26Y170", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y171": { + "bits": {}, + "grid_x": 70, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X26Y171", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y172": { + "bits": {}, + "grid_x": 70, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X26Y172", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y173": { + "bits": {}, + "grid_x": 70, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X26Y173", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y174": { + "bits": {}, + "grid_x": 70, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X26Y174", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y175": { + "bits": {}, + "grid_x": 70, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X26Y175", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y176": { + "bits": {}, + "grid_x": 70, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X26Y176", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y177": { + "bits": {}, + "grid_x": 70, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X26Y177", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y178": { + "bits": {}, + "grid_x": 70, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X26Y178", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y179": { + "bits": {}, + "grid_x": 70, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X26Y179", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y18": { + "bits": {}, + "grid_x": 70, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X26Y18", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y180": { + "bits": {}, + "grid_x": 70, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X26Y180", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y181": { + "bits": {}, + "grid_x": 70, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X26Y181", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y182": { + "bits": {}, + "grid_x": 70, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X26Y182", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y183": { + "bits": {}, + "grid_x": 70, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X26Y183", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y184": { + "bits": {}, + "grid_x": 70, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X26Y184", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y185": { + "bits": {}, + "grid_x": 70, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X26Y185", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y186": { + "bits": {}, + "grid_x": 70, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X26Y186", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y187": { + "bits": {}, + "grid_x": 70, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X26Y187", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y188": { + "bits": {}, + "grid_x": 70, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X26Y188", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y189": { + "bits": {}, + "grid_x": 70, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X26Y189", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y19": { + "bits": {}, + "grid_x": 70, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X26Y19", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y190": { + "bits": {}, + "grid_x": 70, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X26Y190", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y191": { + "bits": {}, + "grid_x": 70, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X26Y191", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y192": { + "bits": {}, + "grid_x": 70, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X26Y192", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y193": { + "bits": {}, + "grid_x": 70, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X26Y193", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y194": { + "bits": {}, + "grid_x": 70, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X26Y194", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y195": { + "bits": {}, + "grid_x": 70, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X26Y195", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y196": { + "bits": {}, + "grid_x": 70, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X26Y196", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y197": { + "bits": {}, + "grid_x": 70, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X26Y197", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y198": { + "bits": {}, + "grid_x": 70, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X26Y198", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y199": { + "bits": {}, + "grid_x": 70, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X26Y199", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y2": { + "bits": {}, + "grid_x": 70, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X26Y2", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y20": { + "bits": {}, + "grid_x": 70, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X26Y20", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y21": { + "bits": {}, + "grid_x": 70, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X26Y21", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y22": { + "bits": {}, + "grid_x": 70, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X26Y22", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y23": { + "bits": {}, + "grid_x": 70, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X26Y23", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y24": { + "bits": {}, + "grid_x": 70, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X26Y24", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y25": { + "bits": {}, + "grid_x": 70, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X26Y25", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y26": { + "bits": {}, + "grid_x": 70, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X26Y26", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y27": { + "bits": {}, + "grid_x": 70, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X26Y27", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y28": { + "bits": {}, + "grid_x": 70, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X26Y28", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y29": { + "bits": {}, + "grid_x": 70, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X26Y29", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y3": { + "bits": {}, + "grid_x": 70, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X26Y3", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y30": { + "bits": {}, + "grid_x": 70, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X26Y30", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y31": { + "bits": {}, + "grid_x": 70, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X26Y31", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y32": { + "bits": {}, + "grid_x": 70, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X26Y32", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y33": { + "bits": {}, + "grid_x": 70, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X26Y33", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y34": { + "bits": {}, + "grid_x": 70, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X26Y34", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y35": { + "bits": {}, + "grid_x": 70, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X26Y35", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y36": { + "bits": {}, + "grid_x": 70, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X26Y36", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y37": { + "bits": {}, + "grid_x": 70, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X26Y37", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y38": { + "bits": {}, + "grid_x": 70, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X26Y38", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y39": { + "bits": {}, + "grid_x": 70, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X26Y39", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y4": { + "bits": {}, + "grid_x": 70, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X26Y4", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y40": { + "bits": {}, + "grid_x": 70, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X26Y40", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y41": { + "bits": {}, + "grid_x": 70, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X26Y41", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y42": { + "bits": {}, + "grid_x": 70, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X26Y42", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y43": { + "bits": {}, + "grid_x": 70, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X26Y43", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y44": { + "bits": {}, + "grid_x": 70, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X26Y44", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y45": { + "bits": {}, + "grid_x": 70, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X26Y45", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y46": { + "bits": {}, + "grid_x": 70, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X26Y46", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y47": { + "bits": {}, + "grid_x": 70, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X26Y47", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y48": { + "bits": {}, + "grid_x": 70, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X26Y48", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y49": { + "bits": {}, + "grid_x": 70, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X26Y49", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y5": { + "bits": {}, + "grid_x": 70, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X26Y5", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y50": { + "bits": {}, + "grid_x": 70, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X26Y50", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y51": { + "bits": {}, + "grid_x": 70, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X26Y51", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y52": { + "bits": {}, + "grid_x": 70, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X26Y52", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y53": { + "bits": {}, + "grid_x": 70, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X26Y53", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y54": { + "bits": {}, + "grid_x": 70, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X26Y54", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y55": { + "bits": {}, + "grid_x": 70, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X26Y55", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y56": { + "bits": {}, + "grid_x": 70, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X26Y56", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y57": { + "bits": {}, + "grid_x": 70, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X26Y57", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y58": { + "bits": {}, + "grid_x": 70, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X26Y58", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y59": { + "bits": {}, + "grid_x": 70, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X26Y59", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y6": { + "bits": {}, + "grid_x": 70, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X26Y6", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y60": { + "bits": {}, + "grid_x": 70, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X26Y60", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y61": { + "bits": {}, + "grid_x": 70, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X26Y61", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y62": { + "bits": {}, + "grid_x": 70, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X26Y62", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y63": { + "bits": {}, + "grid_x": 70, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X26Y63", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y64": { + "bits": {}, + "grid_x": 70, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X26Y64", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y65": { + "bits": {}, + "grid_x": 70, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X26Y65", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y66": { + "bits": {}, + "grid_x": 70, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X26Y66", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y67": { + "bits": {}, + "grid_x": 70, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X26Y67", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y68": { + "bits": {}, + "grid_x": 70, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X26Y68", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y69": { + "bits": {}, + "grid_x": 70, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X26Y69", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y7": { + "bits": {}, + "grid_x": 70, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X26Y7", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y70": { + "bits": {}, + "grid_x": 70, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X26Y70", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y71": { + "bits": {}, + "grid_x": 70, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X26Y71", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y72": { + "bits": {}, + "grid_x": 70, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X26Y72", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y73": { + "bits": {}, + "grid_x": 70, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X26Y73", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y74": { + "bits": {}, + "grid_x": 70, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X26Y74", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y75": { + "bits": {}, + "grid_x": 70, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X26Y75", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y76": { + "bits": {}, + "grid_x": 70, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X26Y76", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y77": { + "bits": {}, + "grid_x": 70, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X26Y77", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y78": { + "bits": {}, + "grid_x": 70, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X26Y78", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y79": { + "bits": {}, + "grid_x": 70, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X26Y79", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y8": { + "bits": {}, + "grid_x": 70, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X26Y8", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y80": { + "bits": {}, + "grid_x": 70, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X26Y80", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y81": { + "bits": {}, + "grid_x": 70, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X26Y81", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y82": { + "bits": {}, + "grid_x": 70, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X26Y82", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y83": { + "bits": {}, + "grid_x": 70, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X26Y83", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y84": { + "bits": {}, + "grid_x": 70, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X26Y84", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y85": { + "bits": {}, + "grid_x": 70, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X26Y85", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y86": { + "bits": {}, + "grid_x": 70, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X26Y86", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y87": { + "bits": {}, + "grid_x": 70, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X26Y87", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y88": { + "bits": {}, + "grid_x": 70, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X26Y88", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y89": { + "bits": {}, + "grid_x": 70, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X26Y89", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y9": { + "bits": {}, + "grid_x": 70, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X26Y9", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y90": { + "bits": {}, + "grid_x": 70, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X26Y90", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y91": { + "bits": {}, + "grid_x": 70, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X26Y91", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y92": { + "bits": {}, + "grid_x": 70, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X26Y92", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y93": { + "bits": {}, + "grid_x": 70, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X26Y93", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y94": { + "bits": {}, + "grid_x": 70, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X26Y94", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y95": { + "bits": {}, + "grid_x": 70, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X26Y95", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y96": { + "bits": {}, + "grid_x": 70, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X26Y96", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y97": { + "bits": {}, + "grid_x": 70, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X26Y97", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y98": { + "bits": {}, + "grid_x": 70, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X26Y98", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X26Y99": { + "bits": {}, + "grid_x": 70, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X26Y99", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X28Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y0": { + "bits": {}, + "grid_x": 74, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X28Y0", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y1": { + "bits": {}, + "grid_x": 74, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X28Y1", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y10": { + "bits": {}, + "grid_x": 74, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X28Y10", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y11": { + "bits": {}, + "grid_x": 74, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X28Y11", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y12": { + "bits": {}, + "grid_x": 74, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X28Y12", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y125": { + "bits": {}, + "grid_x": 74, + "grid_y": 77, + "segment": "SEG_CLBLL_L_X28Y125", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y126": { + "bits": {}, + "grid_x": 74, + "grid_y": 76, + "segment": "SEG_CLBLL_L_X28Y126", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y127": { + "bits": {}, + "grid_x": 74, + "grid_y": 75, + "segment": "SEG_CLBLL_L_X28Y127", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y128": { + "bits": {}, + "grid_x": 74, + "grid_y": 74, + "segment": "SEG_CLBLL_L_X28Y128", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y129": { + "bits": {}, + "grid_x": 74, + "grid_y": 73, + "segment": "SEG_CLBLL_L_X28Y129", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y13": { + "bits": {}, + "grid_x": 74, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X28Y13", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y130": { + "bits": {}, + "grid_x": 74, + "grid_y": 72, + "segment": "SEG_CLBLL_L_X28Y130", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y131": { + "bits": {}, + "grid_x": 74, + "grid_y": 71, + "segment": "SEG_CLBLL_L_X28Y131", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y132": { + "bits": {}, + "grid_x": 74, + "grid_y": 70, + "segment": "SEG_CLBLL_L_X28Y132", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y133": { + "bits": {}, + "grid_x": 74, + "grid_y": 69, + "segment": "SEG_CLBLL_L_X28Y133", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y134": { + "bits": {}, + "grid_x": 74, + "grid_y": 68, + "segment": "SEG_CLBLL_L_X28Y134", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y135": { + "bits": {}, + "grid_x": 74, + "grid_y": 67, + "segment": "SEG_CLBLL_L_X28Y135", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y136": { + "bits": {}, + "grid_x": 74, + "grid_y": 66, + "segment": "SEG_CLBLL_L_X28Y136", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y137": { + "bits": {}, + "grid_x": 74, + "grid_y": 65, + "segment": "SEG_CLBLL_L_X28Y137", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y138": { + "bits": {}, + "grid_x": 74, + "grid_y": 64, + "segment": "SEG_CLBLL_L_X28Y138", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y139": { + "bits": {}, + "grid_x": 74, + "grid_y": 63, + "segment": "SEG_CLBLL_L_X28Y139", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y14": { + "bits": {}, + "grid_x": 74, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X28Y14", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y140": { + "bits": {}, + "grid_x": 74, + "grid_y": 62, + "segment": "SEG_CLBLL_L_X28Y140", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y141": { + "bits": {}, + "grid_x": 74, + "grid_y": 61, + "segment": "SEG_CLBLL_L_X28Y141", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y142": { + "bits": {}, + "grid_x": 74, + "grid_y": 60, + "segment": "SEG_CLBLL_L_X28Y142", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y143": { + "bits": {}, + "grid_x": 74, + "grid_y": 59, + "segment": "SEG_CLBLL_L_X28Y143", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y144": { + "bits": {}, + "grid_x": 74, + "grid_y": 58, + "segment": "SEG_CLBLL_L_X28Y144", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y145": { + "bits": {}, + "grid_x": 74, + "grid_y": 57, + "segment": "SEG_CLBLL_L_X28Y145", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y146": { + "bits": {}, + "grid_x": 74, + "grid_y": 56, + "segment": "SEG_CLBLL_L_X28Y146", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y147": { + "bits": {}, + "grid_x": 74, + "grid_y": 55, + "segment": "SEG_CLBLL_L_X28Y147", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y148": { + "bits": {}, + "grid_x": 74, + "grid_y": 54, + "segment": "SEG_CLBLL_L_X28Y148", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y149": { + "bits": {}, + "grid_x": 74, + "grid_y": 53, + "segment": "SEG_CLBLL_L_X28Y149", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y15": { + "bits": {}, + "grid_x": 74, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X28Y15", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y150": { + "bits": {}, + "grid_x": 74, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X28Y150", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y151": { + "bits": {}, + "grid_x": 74, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X28Y151", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y152": { + "bits": {}, + "grid_x": 74, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X28Y152", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y153": { + "bits": {}, + "grid_x": 74, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X28Y153", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y154": { + "bits": {}, + "grid_x": 74, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X28Y154", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y155": { + "bits": {}, + "grid_x": 74, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X28Y155", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y156": { + "bits": {}, + "grid_x": 74, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X28Y156", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y157": { + "bits": {}, + "grid_x": 74, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X28Y157", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y158": { + "bits": {}, + "grid_x": 74, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X28Y158", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y159": { + "bits": {}, + "grid_x": 74, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X28Y159", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y16": { + "bits": {}, + "grid_x": 74, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X28Y16", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y160": { + "bits": {}, + "grid_x": 74, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X28Y160", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y161": { + "bits": {}, + "grid_x": 74, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X28Y161", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y162": { + "bits": {}, + "grid_x": 74, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X28Y162", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y163": { + "bits": {}, + "grid_x": 74, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X28Y163", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y164": { + "bits": {}, + "grid_x": 74, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X28Y164", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y165": { + "bits": {}, + "grid_x": 74, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X28Y165", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y166": { + "bits": {}, + "grid_x": 74, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X28Y166", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y167": { + "bits": {}, + "grid_x": 74, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X28Y167", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y168": { + "bits": {}, + "grid_x": 74, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X28Y168", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y169": { + "bits": {}, + "grid_x": 74, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X28Y169", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y17": { + "bits": {}, + "grid_x": 74, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X28Y17", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y170": { + "bits": {}, + "grid_x": 74, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X28Y170", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y171": { + "bits": {}, + "grid_x": 74, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X28Y171", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y172": { + "bits": {}, + "grid_x": 74, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X28Y172", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y173": { + "bits": {}, + "grid_x": 74, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X28Y173", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y174": { + "bits": {}, + "grid_x": 74, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X28Y174", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y175": { + "bits": {}, + "grid_x": 74, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X28Y175", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y176": { + "bits": {}, + "grid_x": 74, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X28Y176", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y177": { + "bits": {}, + "grid_x": 74, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X28Y177", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y178": { + "bits": {}, + "grid_x": 74, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X28Y178", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y179": { + "bits": {}, + "grid_x": 74, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X28Y179", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y18": { + "bits": {}, + "grid_x": 74, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X28Y18", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y180": { + "bits": {}, + "grid_x": 74, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X28Y180", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y181": { + "bits": {}, + "grid_x": 74, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X28Y181", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y182": { + "bits": {}, + "grid_x": 74, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X28Y182", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y183": { + "bits": {}, + "grid_x": 74, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X28Y183", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y184": { + "bits": {}, + "grid_x": 74, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X28Y184", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y185": { + "bits": {}, + "grid_x": 74, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X28Y185", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y186": { + "bits": {}, + "grid_x": 74, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X28Y186", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y187": { + "bits": {}, + "grid_x": 74, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X28Y187", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y188": { + "bits": {}, + "grid_x": 74, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X28Y188", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y189": { + "bits": {}, + "grid_x": 74, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X28Y189", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y19": { + "bits": {}, + "grid_x": 74, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X28Y19", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y190": { + "bits": {}, + "grid_x": 74, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X28Y190", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y191": { + "bits": {}, + "grid_x": 74, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X28Y191", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y192": { + "bits": {}, + "grid_x": 74, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X28Y192", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y193": { + "bits": {}, + "grid_x": 74, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X28Y193", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y194": { + "bits": {}, + "grid_x": 74, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X28Y194", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y195": { + "bits": {}, + "grid_x": 74, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X28Y195", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y196": { + "bits": {}, + "grid_x": 74, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X28Y196", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y197": { + "bits": {}, + "grid_x": 74, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X28Y197", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y198": { + "bits": {}, + "grid_x": 74, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X28Y198", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y199": { + "bits": {}, + "grid_x": 74, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X28Y199", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y2": { + "bits": {}, + "grid_x": 74, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X28Y2", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y20": { + "bits": {}, + "grid_x": 74, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X28Y20", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y21": { + "bits": {}, + "grid_x": 74, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X28Y21", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y22": { + "bits": {}, + "grid_x": 74, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X28Y22", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y23": { + "bits": {}, + "grid_x": 74, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X28Y23", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y24": { + "bits": {}, + "grid_x": 74, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X28Y24", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y25": { + "bits": {}, + "grid_x": 74, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X28Y25", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y26": { + "bits": {}, + "grid_x": 74, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X28Y26", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y27": { + "bits": {}, + "grid_x": 74, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X28Y27", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y28": { + "bits": {}, + "grid_x": 74, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X28Y28", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y29": { + "bits": {}, + "grid_x": 74, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X28Y29", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y3": { + "bits": {}, + "grid_x": 74, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X28Y3", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y30": { + "bits": {}, + "grid_x": 74, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X28Y30", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y31": { + "bits": {}, + "grid_x": 74, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X28Y31", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y32": { + "bits": {}, + "grid_x": 74, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X28Y32", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y33": { + "bits": {}, + "grid_x": 74, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X28Y33", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y34": { + "bits": {}, + "grid_x": 74, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X28Y34", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y35": { + "bits": {}, + "grid_x": 74, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X28Y35", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y36": { + "bits": {}, + "grid_x": 74, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X28Y36", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y37": { + "bits": {}, + "grid_x": 74, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X28Y37", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y38": { + "bits": {}, + "grid_x": 74, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X28Y38", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y39": { + "bits": {}, + "grid_x": 74, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X28Y39", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y4": { + "bits": {}, + "grid_x": 74, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X28Y4", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y40": { + "bits": {}, + "grid_x": 74, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X28Y40", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y41": { + "bits": {}, + "grid_x": 74, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X28Y41", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y42": { + "bits": {}, + "grid_x": 74, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X28Y42", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y43": { + "bits": {}, + "grid_x": 74, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X28Y43", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y44": { + "bits": {}, + "grid_x": 74, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X28Y44", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y45": { + "bits": {}, + "grid_x": 74, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X28Y45", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y46": { + "bits": {}, + "grid_x": 74, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X28Y46", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y47": { + "bits": {}, + "grid_x": 74, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X28Y47", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y48": { + "bits": {}, + "grid_x": 74, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X28Y48", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y49": { + "bits": {}, + "grid_x": 74, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X28Y49", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y5": { + "bits": {}, + "grid_x": 74, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X28Y5", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y50": { + "bits": {}, + "grid_x": 74, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X28Y50", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y51": { + "bits": {}, + "grid_x": 74, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X28Y51", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y52": { + "bits": {}, + "grid_x": 74, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X28Y52", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y53": { + "bits": {}, + "grid_x": 74, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X28Y53", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y54": { + "bits": {}, + "grid_x": 74, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X28Y54", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y55": { + "bits": {}, + "grid_x": 74, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X28Y55", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y56": { + "bits": {}, + "grid_x": 74, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X28Y56", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y57": { + "bits": {}, + "grid_x": 74, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X28Y57", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y58": { + "bits": {}, + "grid_x": 74, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X28Y58", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y59": { + "bits": {}, + "grid_x": 74, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X28Y59", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y6": { + "bits": {}, + "grid_x": 74, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X28Y6", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y60": { + "bits": {}, + "grid_x": 74, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X28Y60", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y61": { + "bits": {}, + "grid_x": 74, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X28Y61", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y62": { + "bits": {}, + "grid_x": 74, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X28Y62", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y63": { + "bits": {}, + "grid_x": 74, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X28Y63", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y64": { + "bits": {}, + "grid_x": 74, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X28Y64", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y65": { + "bits": {}, + "grid_x": 74, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X28Y65", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y66": { + "bits": {}, + "grid_x": 74, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X28Y66", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y67": { + "bits": {}, + "grid_x": 74, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X28Y67", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y68": { + "bits": {}, + "grid_x": 74, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X28Y68", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y69": { + "bits": {}, + "grid_x": 74, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X28Y69", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y7": { + "bits": {}, + "grid_x": 74, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X28Y7", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y70": { + "bits": {}, + "grid_x": 74, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X28Y70", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y71": { + "bits": {}, + "grid_x": 74, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X28Y71", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y72": { + "bits": {}, + "grid_x": 74, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X28Y72", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y73": { + "bits": {}, + "grid_x": 74, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X28Y73", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y74": { + "bits": {}, + "grid_x": 74, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X28Y74", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y75": { + "bits": {}, + "grid_x": 74, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X28Y75", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y76": { + "bits": {}, + "grid_x": 74, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X28Y76", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y77": { + "bits": {}, + "grid_x": 74, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X28Y77", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y78": { + "bits": {}, + "grid_x": 74, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X28Y78", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y79": { + "bits": {}, + "grid_x": 74, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X28Y79", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y8": { + "bits": {}, + "grid_x": 74, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X28Y8", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y80": { + "bits": {}, + "grid_x": 74, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X28Y80", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y81": { + "bits": {}, + "grid_x": 74, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X28Y81", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y82": { + "bits": {}, + "grid_x": 74, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X28Y82", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y83": { + "bits": {}, + "grid_x": 74, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X28Y83", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y84": { + "bits": {}, + "grid_x": 74, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X28Y84", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y85": { + "bits": {}, + "grid_x": 74, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X28Y85", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y86": { + "bits": {}, + "grid_x": 74, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X28Y86", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y87": { + "bits": {}, + "grid_x": 74, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X28Y87", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y88": { + "bits": {}, + "grid_x": 74, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X28Y88", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y89": { + "bits": {}, + "grid_x": 74, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X28Y89", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y9": { + "bits": {}, + "grid_x": 74, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X28Y9", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y90": { + "bits": {}, + "grid_x": 74, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X28Y90", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y91": { + "bits": {}, + "grid_x": 74, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X28Y91", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y92": { + "bits": {}, + "grid_x": 74, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X28Y92", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y93": { + "bits": {}, + "grid_x": 74, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X28Y93", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y94": { + "bits": {}, + "grid_x": 74, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X28Y94", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y95": { + "bits": {}, + "grid_x": 74, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X28Y95", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y96": { + "bits": {}, + "grid_x": 74, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X28Y96", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y97": { + "bits": {}, + "grid_x": 74, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X28Y97", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y98": { + "bits": {}, + "grid_x": 74, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X28Y98", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X28Y99": { + "bits": {}, + "grid_x": 74, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X28Y99", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X30Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y0": { + "bits": {}, + "grid_x": 11, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X2Y0", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y1": { + "bits": {}, + "grid_x": 11, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X2Y1", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y10": { + "bits": {}, + "grid_x": 11, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X2Y10", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y100": { + "bits": {}, + "grid_x": 11, + "grid_y": 103, + "segment": "SEG_CLBLL_L_X2Y100", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y101": { + "bits": {}, + "grid_x": 11, + "grid_y": 102, + "segment": "SEG_CLBLL_L_X2Y101", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y102": { + "bits": {}, + "grid_x": 11, + "grid_y": 101, + "segment": "SEG_CLBLL_L_X2Y102", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y103": { + "bits": {}, + "grid_x": 11, + "grid_y": 100, + "segment": "SEG_CLBLL_L_X2Y103", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y104": { + "bits": {}, + "grid_x": 11, + "grid_y": 99, + "segment": "SEG_CLBLL_L_X2Y104", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y105": { + "bits": {}, + "grid_x": 11, + "grid_y": 98, + "segment": "SEG_CLBLL_L_X2Y105", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y106": { + "bits": {}, + "grid_x": 11, + "grid_y": 97, + "segment": "SEG_CLBLL_L_X2Y106", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y107": { + "bits": {}, + "grid_x": 11, + "grid_y": 96, + "segment": "SEG_CLBLL_L_X2Y107", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y108": { + "bits": {}, + "grid_x": 11, + "grid_y": 95, + "segment": "SEG_CLBLL_L_X2Y108", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y109": { + "bits": {}, + "grid_x": 11, + "grid_y": 94, + "segment": "SEG_CLBLL_L_X2Y109", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y11": { + "bits": {}, + "grid_x": 11, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X2Y11", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y110": { + "bits": {}, + "grid_x": 11, + "grid_y": 93, + "segment": "SEG_CLBLL_L_X2Y110", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y111": { + "bits": {}, + "grid_x": 11, + "grid_y": 92, + "segment": "SEG_CLBLL_L_X2Y111", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y112": { + "bits": {}, + "grid_x": 11, + "grid_y": 91, + "segment": "SEG_CLBLL_L_X2Y112", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y113": { + "bits": {}, + "grid_x": 11, + "grid_y": 90, + "segment": "SEG_CLBLL_L_X2Y113", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y114": { + "bits": {}, + "grid_x": 11, + "grid_y": 89, + "segment": "SEG_CLBLL_L_X2Y114", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y115": { + "bits": {}, + "grid_x": 11, + "grid_y": 88, + "segment": "SEG_CLBLL_L_X2Y115", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y116": { + "bits": {}, + "grid_x": 11, + "grid_y": 87, + "segment": "SEG_CLBLL_L_X2Y116", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y117": { + "bits": {}, + "grid_x": 11, + "grid_y": 86, + "segment": "SEG_CLBLL_L_X2Y117", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y118": { + "bits": {}, + "grid_x": 11, + "grid_y": 85, + "segment": "SEG_CLBLL_L_X2Y118", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y119": { + "bits": {}, + "grid_x": 11, + "grid_y": 84, + "segment": "SEG_CLBLL_L_X2Y119", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y12": { + "bits": {}, + "grid_x": 11, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X2Y12", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y120": { + "bits": {}, + "grid_x": 11, + "grid_y": 83, + "segment": "SEG_CLBLL_L_X2Y120", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y121": { + "bits": {}, + "grid_x": 11, + "grid_y": 82, + "segment": "SEG_CLBLL_L_X2Y121", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y122": { + "bits": {}, + "grid_x": 11, + "grid_y": 81, + "segment": "SEG_CLBLL_L_X2Y122", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y123": { + "bits": {}, + "grid_x": 11, + "grid_y": 80, + "segment": "SEG_CLBLL_L_X2Y123", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y124": { + "bits": {}, + "grid_x": 11, + "grid_y": 79, + "segment": "SEG_CLBLL_L_X2Y124", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y125": { + "bits": {}, + "grid_x": 11, + "grid_y": 77, + "segment": "SEG_CLBLL_L_X2Y125", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y126": { + "bits": {}, + "grid_x": 11, + "grid_y": 76, + "segment": "SEG_CLBLL_L_X2Y126", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y127": { + "bits": {}, + "grid_x": 11, + "grid_y": 75, + "segment": "SEG_CLBLL_L_X2Y127", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y128": { + "bits": {}, + "grid_x": 11, + "grid_y": 74, + "segment": "SEG_CLBLL_L_X2Y128", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y129": { + "bits": {}, + "grid_x": 11, + "grid_y": 73, + "segment": "SEG_CLBLL_L_X2Y129", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y13": { + "bits": {}, + "grid_x": 11, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X2Y13", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y130": { + "bits": {}, + "grid_x": 11, + "grid_y": 72, + "segment": "SEG_CLBLL_L_X2Y130", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y131": { + "bits": {}, + "grid_x": 11, + "grid_y": 71, + "segment": "SEG_CLBLL_L_X2Y131", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y132": { + "bits": {}, + "grid_x": 11, + "grid_y": 70, + "segment": "SEG_CLBLL_L_X2Y132", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y133": { + "bits": {}, + "grid_x": 11, + "grid_y": 69, + "segment": "SEG_CLBLL_L_X2Y133", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y134": { + "bits": {}, + "grid_x": 11, + "grid_y": 68, + "segment": "SEG_CLBLL_L_X2Y134", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y135": { + "bits": {}, + "grid_x": 11, + "grid_y": 67, + "segment": "SEG_CLBLL_L_X2Y135", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y136": { + "bits": {}, + "grid_x": 11, + "grid_y": 66, + "segment": "SEG_CLBLL_L_X2Y136", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y137": { + "bits": {}, + "grid_x": 11, + "grid_y": 65, + "segment": "SEG_CLBLL_L_X2Y137", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y138": { + "bits": {}, + "grid_x": 11, + "grid_y": 64, + "segment": "SEG_CLBLL_L_X2Y138", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y139": { + "bits": {}, + "grid_x": 11, + "grid_y": 63, + "segment": "SEG_CLBLL_L_X2Y139", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y14": { + "bits": {}, + "grid_x": 11, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X2Y14", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y140": { + "bits": {}, + "grid_x": 11, + "grid_y": 62, + "segment": "SEG_CLBLL_L_X2Y140", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y141": { + "bits": {}, + "grid_x": 11, + "grid_y": 61, + "segment": "SEG_CLBLL_L_X2Y141", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y142": { + "bits": {}, + "grid_x": 11, + "grid_y": 60, + "segment": "SEG_CLBLL_L_X2Y142", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y143": { + "bits": {}, + "grid_x": 11, + "grid_y": 59, + "segment": "SEG_CLBLL_L_X2Y143", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y144": { + "bits": {}, + "grid_x": 11, + "grid_y": 58, + "segment": "SEG_CLBLL_L_X2Y144", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y145": { + "bits": {}, + "grid_x": 11, + "grid_y": 57, + "segment": "SEG_CLBLL_L_X2Y145", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y146": { + "bits": {}, + "grid_x": 11, + "grid_y": 56, + "segment": "SEG_CLBLL_L_X2Y146", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y147": { + "bits": {}, + "grid_x": 11, + "grid_y": 55, + "segment": "SEG_CLBLL_L_X2Y147", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y148": { + "bits": {}, + "grid_x": 11, + "grid_y": 54, + "segment": "SEG_CLBLL_L_X2Y148", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y149": { + "bits": {}, + "grid_x": 11, + "grid_y": 53, + "segment": "SEG_CLBLL_L_X2Y149", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y15": { + "bits": {}, + "grid_x": 11, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X2Y15", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y150": { + "bits": {}, + "grid_x": 11, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X2Y150", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y151": { + "bits": {}, + "grid_x": 11, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X2Y151", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y152": { + "bits": {}, + "grid_x": 11, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X2Y152", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y153": { + "bits": {}, + "grid_x": 11, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X2Y153", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y154": { + "bits": {}, + "grid_x": 11, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X2Y154", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y155": { + "bits": {}, + "grid_x": 11, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X2Y155", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y156": { + "bits": {}, + "grid_x": 11, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X2Y156", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y157": { + "bits": {}, + "grid_x": 11, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X2Y157", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y158": { + "bits": {}, + "grid_x": 11, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X2Y158", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y159": { + "bits": {}, + "grid_x": 11, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X2Y159", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y16": { + "bits": {}, + "grid_x": 11, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X2Y16", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y160": { + "bits": {}, + "grid_x": 11, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X2Y160", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y161": { + "bits": {}, + "grid_x": 11, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X2Y161", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y162": { + "bits": {}, + "grid_x": 11, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X2Y162", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y163": { + "bits": {}, + "grid_x": 11, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X2Y163", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y164": { + "bits": {}, + "grid_x": 11, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X2Y164", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y165": { + "bits": {}, + "grid_x": 11, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X2Y165", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y166": { + "bits": {}, + "grid_x": 11, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X2Y166", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y167": { + "bits": {}, + "grid_x": 11, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X2Y167", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y168": { + "bits": {}, + "grid_x": 11, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X2Y168", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y169": { + "bits": {}, + "grid_x": 11, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X2Y169", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y17": { + "bits": {}, + "grid_x": 11, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X2Y17", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y170": { + "bits": {}, + "grid_x": 11, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X2Y170", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y171": { + "bits": {}, + "grid_x": 11, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X2Y171", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y172": { + "bits": {}, + "grid_x": 11, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X2Y172", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y173": { + "bits": {}, + "grid_x": 11, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X2Y173", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y174": { + "bits": {}, + "grid_x": 11, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X2Y174", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y175": { + "bits": {}, + "grid_x": 11, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X2Y175", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y176": { + "bits": {}, + "grid_x": 11, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X2Y176", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y177": { + "bits": {}, + "grid_x": 11, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X2Y177", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y178": { + "bits": {}, + "grid_x": 11, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X2Y178", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y179": { + "bits": {}, + "grid_x": 11, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X2Y179", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y18": { + "bits": {}, + "grid_x": 11, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X2Y18", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y180": { + "bits": {}, + "grid_x": 11, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X2Y180", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y181": { + "bits": {}, + "grid_x": 11, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X2Y181", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y182": { + "bits": {}, + "grid_x": 11, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X2Y182", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y183": { + "bits": {}, + "grid_x": 11, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X2Y183", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y184": { + "bits": {}, + "grid_x": 11, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X2Y184", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y185": { + "bits": {}, + "grid_x": 11, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X2Y185", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y186": { + "bits": {}, + "grid_x": 11, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X2Y186", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y187": { + "bits": {}, + "grid_x": 11, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X2Y187", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y188": { + "bits": {}, + "grid_x": 11, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X2Y188", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y189": { + "bits": {}, + "grid_x": 11, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X2Y189", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y19": { + "bits": {}, + "grid_x": 11, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X2Y19", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y190": { + "bits": {}, + "grid_x": 11, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X2Y190", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y191": { + "bits": {}, + "grid_x": 11, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X2Y191", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y192": { + "bits": {}, + "grid_x": 11, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X2Y192", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y193": { + "bits": {}, + "grid_x": 11, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X2Y193", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y194": { + "bits": {}, + "grid_x": 11, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X2Y194", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y195": { + "bits": {}, + "grid_x": 11, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X2Y195", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y196": { + "bits": {}, + "grid_x": 11, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X2Y196", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y197": { + "bits": {}, + "grid_x": 11, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X2Y197", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y198": { + "bits": {}, + "grid_x": 11, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X2Y198", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y199": { + "bits": {}, + "grid_x": 11, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X2Y199", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y2": { + "bits": {}, + "grid_x": 11, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X2Y2", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y20": { + "bits": {}, + "grid_x": 11, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X2Y20", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y21": { + "bits": {}, + "grid_x": 11, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X2Y21", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y22": { + "bits": {}, + "grid_x": 11, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X2Y22", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y23": { + "bits": {}, + "grid_x": 11, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X2Y23", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y24": { + "bits": {}, + "grid_x": 11, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X2Y24", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y25": { + "bits": {}, + "grid_x": 11, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X2Y25", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y26": { + "bits": {}, + "grid_x": 11, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X2Y26", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y27": { + "bits": {}, + "grid_x": 11, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X2Y27", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y28": { + "bits": {}, + "grid_x": 11, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X2Y28", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y29": { + "bits": {}, + "grid_x": 11, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X2Y29", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y3": { + "bits": {}, + "grid_x": 11, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X2Y3", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y30": { + "bits": {}, + "grid_x": 11, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X2Y30", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y31": { + "bits": {}, + "grid_x": 11, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X2Y31", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y32": { + "bits": {}, + "grid_x": 11, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X2Y32", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y33": { + "bits": {}, + "grid_x": 11, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X2Y33", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y34": { + "bits": {}, + "grid_x": 11, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X2Y34", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y35": { + "bits": {}, + "grid_x": 11, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X2Y35", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y36": { + "bits": {}, + "grid_x": 11, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X2Y36", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y37": { + "bits": {}, + "grid_x": 11, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X2Y37", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y38": { + "bits": {}, + "grid_x": 11, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X2Y38", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y39": { + "bits": {}, + "grid_x": 11, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X2Y39", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y4": { + "bits": {}, + "grid_x": 11, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X2Y4", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y40": { + "bits": {}, + "grid_x": 11, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X2Y40", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y41": { + "bits": {}, + "grid_x": 11, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X2Y41", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y42": { + "bits": {}, + "grid_x": 11, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X2Y42", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y43": { + "bits": {}, + "grid_x": 11, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X2Y43", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y44": { + "bits": {}, + "grid_x": 11, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X2Y44", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y45": { + "bits": {}, + "grid_x": 11, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X2Y45", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y46": { + "bits": {}, + "grid_x": 11, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X2Y46", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y47": { + "bits": {}, + "grid_x": 11, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X2Y47", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y48": { + "bits": {}, + "grid_x": 11, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X2Y48", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y49": { + "bits": {}, + "grid_x": 11, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X2Y49", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y5": { + "bits": {}, + "grid_x": 11, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X2Y5", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X2Y50", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X2Y51", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X2Y52", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X2Y53", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X2Y54", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X2Y55", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X2Y56", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X2Y57", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X2Y58", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X2Y59", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y6": { + "bits": {}, + "grid_x": 11, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X2Y6", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X2Y60", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X2Y61", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X2Y62", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X2Y63", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X2Y64", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X2Y65", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X2Y66", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X2Y67", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X2Y68", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X2Y69", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y7": { + "bits": {}, + "grid_x": 11, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X2Y7", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X2Y70", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X2Y71", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X2Y72", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X2Y73", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X2Y74", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X2Y75", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X2Y76", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X2Y77", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X2Y78", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X2Y79", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y8": { + "bits": {}, + "grid_x": 11, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X2Y8", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X2Y80", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X2Y81", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X2Y82", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X2Y83", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X2Y84", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X2Y85", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X2Y86", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X2Y87", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X2Y88", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X2Y89", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y9": { + "bits": {}, + "grid_x": 11, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X2Y9", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X2Y90", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X2Y91", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X2Y92", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X2Y93", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X2Y94", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X2Y95", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X2Y96", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X2Y97", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X2Y98", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X2Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400100", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 11, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X2Y99", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X2Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y0": { + "bits": {}, + "grid_x": 79, + "grid_y": 207, + "segment": "SEG_BRAM0_L_X30Y0", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y1": { + "bits": {}, + "grid_x": 79, + "grid_y": 206, + "segment": "SEG_BRAM1_L_X30Y0", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y10": { + "bits": {}, + "grid_x": 79, + "grid_y": 197, + "segment": "SEG_BRAM0_L_X30Y10", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y100": { + "bits": {}, + "grid_x": 79, + "grid_y": 103, + "sites": { + "TIEOFF_X32Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y101": { + "bits": {}, + "grid_x": 79, + "grid_y": 102, + "sites": { + "TIEOFF_X32Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y102": { + "bits": {}, + "grid_x": 79, + "grid_y": 101, + "sites": { + "TIEOFF_X32Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y103": { + "bits": {}, + "grid_x": 79, + "grid_y": 100, + "sites": { + "TIEOFF_X32Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y104": { + "bits": {}, + "grid_x": 79, + "grid_y": 99, + "sites": { + "TIEOFF_X32Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y105": { + "bits": {}, + "grid_x": 79, + "grid_y": 98, + "sites": { + "TIEOFF_X32Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y106": { + "bits": {}, + "grid_x": 79, + "grid_y": 97, + "sites": { + "TIEOFF_X32Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y107": { + "bits": {}, + "grid_x": 79, + "grid_y": 96, + "sites": { + "TIEOFF_X32Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y108": { + "bits": {}, + "grid_x": 79, + "grid_y": 95, + "sites": { + "TIEOFF_X32Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y109": { + "bits": {}, + "grid_x": 79, + "grid_y": 94, + "sites": { + "TIEOFF_X32Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y11": { + "bits": {}, + "grid_x": 79, + "grid_y": 196, + "segment": "SEG_BRAM1_L_X30Y10", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y110": { + "bits": {}, + "grid_x": 79, + "grid_y": 93, + "sites": { + "TIEOFF_X32Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y111": { + "bits": {}, + "grid_x": 79, + "grid_y": 92, + "sites": { + "TIEOFF_X32Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y112": { + "bits": {}, + "grid_x": 79, + "grid_y": 91, + "sites": { + "TIEOFF_X32Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y113": { + "bits": {}, + "grid_x": 79, + "grid_y": 90, + "sites": { + "TIEOFF_X32Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y114": { + "bits": {}, + "grid_x": 79, + "grid_y": 89, + "sites": { + "TIEOFF_X32Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y115": { + "bits": {}, + "grid_x": 79, + "grid_y": 88, + "sites": { + "TIEOFF_X32Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y116": { + "bits": {}, + "grid_x": 79, + "grid_y": 87, + "sites": { + "TIEOFF_X32Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y117": { + "bits": {}, + "grid_x": 79, + "grid_y": 86, + "sites": { + "TIEOFF_X32Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y118": { + "bits": {}, + "grid_x": 79, + "grid_y": 85, + "sites": { + "TIEOFF_X32Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y119": { + "bits": {}, + "grid_x": 79, + "grid_y": 84, + "sites": { + "TIEOFF_X32Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y12": { + "bits": {}, + "grid_x": 79, + "grid_y": 195, + "segment": "SEG_BRAM2_L_X30Y10", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y120": { + "bits": {}, + "grid_x": 79, + "grid_y": 83, + "sites": { + "TIEOFF_X32Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y121": { + "bits": {}, + "grid_x": 79, + "grid_y": 82, + "sites": { + "TIEOFF_X32Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y122": { + "bits": {}, + "grid_x": 79, + "grid_y": 81, + "sites": { + "TIEOFF_X32Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y123": { + "bits": {}, + "grid_x": 79, + "grid_y": 80, + "sites": { + "TIEOFF_X32Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y124": { + "bits": {}, + "grid_x": 79, + "grid_y": 79, + "sites": { + "TIEOFF_X32Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y125": { + "bits": {}, + "grid_x": 79, + "grid_y": 77, + "segment": "SEG_BRAM0_L_X30Y125", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y126": { + "bits": {}, + "grid_x": 79, + "grid_y": 76, + "segment": "SEG_BRAM1_L_X30Y125", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y127": { + "bits": {}, + "grid_x": 79, + "grid_y": 75, + "segment": "SEG_BRAM2_L_X30Y125", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y128": { + "bits": {}, + "grid_x": 79, + "grid_y": 74, + "segment": "SEG_BRAM3_L_X30Y125", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y129": { + "bits": {}, + "grid_x": 79, + "grid_y": 73, + "segment": "SEG_BRAM4_L_X30Y125", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y13": { + "bits": {}, + "grid_x": 79, + "grid_y": 194, + "segment": "SEG_BRAM3_L_X30Y10", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y130": { + "bits": {}, + "grid_x": 79, + "grid_y": 72, + "segment": "SEG_BRAM0_L_X30Y130", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y131": { + "bits": {}, + "grid_x": 79, + "grid_y": 71, + "segment": "SEG_BRAM1_L_X30Y130", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y132": { + "bits": {}, + "grid_x": 79, + "grid_y": 70, + "segment": "SEG_BRAM2_L_X30Y130", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y133": { + "bits": {}, + "grid_x": 79, + "grid_y": 69, + "segment": "SEG_BRAM3_L_X30Y130", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y134": { + "bits": {}, + "grid_x": 79, + "grid_y": 68, + "segment": "SEG_BRAM4_L_X30Y130", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y135": { + "bits": {}, + "grid_x": 79, + "grid_y": 67, + "segment": "SEG_BRAM0_L_X30Y135", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y136": { + "bits": {}, + "grid_x": 79, + "grid_y": 66, + "segment": "SEG_BRAM1_L_X30Y135", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y137": { + "bits": {}, + "grid_x": 79, + "grid_y": 65, + "segment": "SEG_BRAM2_L_X30Y135", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y138": { + "bits": {}, + "grid_x": 79, + "grid_y": 64, + "segment": "SEG_BRAM3_L_X30Y135", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y139": { + "bits": {}, + "grid_x": 79, + "grid_y": 63, + "segment": "SEG_BRAM4_L_X30Y135", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y14": { + "bits": {}, + "grid_x": 79, + "grid_y": 193, + "segment": "SEG_BRAM4_L_X30Y10", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y140": { + "bits": {}, + "grid_x": 79, + "grid_y": 62, + "segment": "SEG_BRAM0_L_X30Y140", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y141": { + "bits": {}, + "grid_x": 79, + "grid_y": 61, + "segment": "SEG_BRAM1_L_X30Y140", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y142": { + "bits": {}, + "grid_x": 79, + "grid_y": 60, + "segment": "SEG_BRAM2_L_X30Y140", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y143": { + "bits": {}, + "grid_x": 79, + "grid_y": 59, + "segment": "SEG_BRAM3_L_X30Y140", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y144": { + "bits": {}, + "grid_x": 79, + "grid_y": 58, + "segment": "SEG_BRAM4_L_X30Y140", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y145": { + "bits": {}, + "grid_x": 79, + "grid_y": 57, + "segment": "SEG_BRAM0_L_X30Y145", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y146": { + "bits": {}, + "grid_x": 79, + "grid_y": 56, + "segment": "SEG_BRAM1_L_X30Y145", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y147": { + "bits": {}, + "grid_x": 79, + "grid_y": 55, + "segment": "SEG_BRAM2_L_X30Y145", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y148": { + "bits": {}, + "grid_x": 79, + "grid_y": 54, + "segment": "SEG_BRAM3_L_X30Y145", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y149": { + "bits": {}, + "grid_x": 79, + "grid_y": 53, + "segment": "SEG_BRAM4_L_X30Y145", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y15": { + "bits": {}, + "grid_x": 79, + "grid_y": 192, + "segment": "SEG_BRAM0_L_X30Y15", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y150": { + "bits": {}, + "grid_x": 79, + "grid_y": 51, + "segment": "SEG_BRAM0_L_X30Y150", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y151": { + "bits": {}, + "grid_x": 79, + "grid_y": 50, + "segment": "SEG_BRAM1_L_X30Y150", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y152": { + "bits": {}, + "grid_x": 79, + "grid_y": 49, + "segment": "SEG_BRAM2_L_X30Y150", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y153": { + "bits": {}, + "grid_x": 79, + "grid_y": 48, + "segment": "SEG_BRAM3_L_X30Y150", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y154": { + "bits": {}, + "grid_x": 79, + "grid_y": 47, + "segment": "SEG_BRAM4_L_X30Y150", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y155": { + "bits": {}, + "grid_x": 79, + "grid_y": 46, + "segment": "SEG_BRAM0_L_X30Y155", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y156": { + "bits": {}, + "grid_x": 79, + "grid_y": 45, + "segment": "SEG_BRAM1_L_X30Y155", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y157": { + "bits": {}, + "grid_x": 79, + "grid_y": 44, + "segment": "SEG_BRAM2_L_X30Y155", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y158": { + "bits": {}, + "grid_x": 79, + "grid_y": 43, + "segment": "SEG_BRAM3_L_X30Y155", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y159": { + "bits": {}, + "grid_x": 79, + "grid_y": 42, + "segment": "SEG_BRAM4_L_X30Y155", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y16": { + "bits": {}, + "grid_x": 79, + "grid_y": 191, + "segment": "SEG_BRAM1_L_X30Y15", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y160": { + "bits": {}, + "grid_x": 79, + "grid_y": 41, + "segment": "SEG_BRAM0_L_X30Y160", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y161": { + "bits": {}, + "grid_x": 79, + "grid_y": 40, + "segment": "SEG_BRAM1_L_X30Y160", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y162": { + "bits": {}, + "grid_x": 79, + "grid_y": 39, + "segment": "SEG_BRAM2_L_X30Y160", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y163": { + "bits": {}, + "grid_x": 79, + "grid_y": 38, + "segment": "SEG_BRAM3_L_X30Y160", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y164": { + "bits": {}, + "grid_x": 79, + "grid_y": 37, + "segment": "SEG_BRAM4_L_X30Y160", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y165": { + "bits": {}, + "grid_x": 79, + "grid_y": 36, + "segment": "SEG_BRAM0_L_X30Y165", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y166": { + "bits": {}, + "grid_x": 79, + "grid_y": 35, + "segment": "SEG_BRAM1_L_X30Y165", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y167": { + "bits": {}, + "grid_x": 79, + "grid_y": 34, + "segment": "SEG_BRAM2_L_X30Y165", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y168": { + "bits": {}, + "grid_x": 79, + "grid_y": 33, + "segment": "SEG_BRAM3_L_X30Y165", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y169": { + "bits": {}, + "grid_x": 79, + "grid_y": 32, + "segment": "SEG_BRAM4_L_X30Y165", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y17": { + "bits": {}, + "grid_x": 79, + "grid_y": 190, + "segment": "SEG_BRAM2_L_X30Y15", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y170": { + "bits": {}, + "grid_x": 79, + "grid_y": 31, + "segment": "SEG_BRAM0_L_X30Y170", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y171": { + "bits": {}, + "grid_x": 79, + "grid_y": 30, + "segment": "SEG_BRAM1_L_X30Y170", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y172": { + "bits": {}, + "grid_x": 79, + "grid_y": 29, + "segment": "SEG_BRAM2_L_X30Y170", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y173": { + "bits": {}, + "grid_x": 79, + "grid_y": 28, + "segment": "SEG_BRAM3_L_X30Y170", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y174": { + "bits": {}, + "grid_x": 79, + "grid_y": 27, + "segment": "SEG_BRAM4_L_X30Y170", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y175": { + "bits": {}, + "grid_x": 79, + "grid_y": 25, + "segment": "SEG_BRAM0_L_X30Y175", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y176": { + "bits": {}, + "grid_x": 79, + "grid_y": 24, + "segment": "SEG_BRAM1_L_X30Y175", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y177": { + "bits": {}, + "grid_x": 79, + "grid_y": 23, + "segment": "SEG_BRAM2_L_X30Y175", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y178": { + "bits": {}, + "grid_x": 79, + "grid_y": 22, + "segment": "SEG_BRAM3_L_X30Y175", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y179": { + "bits": {}, + "grid_x": 79, + "grid_y": 21, + "segment": "SEG_BRAM4_L_X30Y175", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y18": { + "bits": {}, + "grid_x": 79, + "grid_y": 189, + "segment": "SEG_BRAM3_L_X30Y15", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y180": { + "bits": {}, + "grid_x": 79, + "grid_y": 20, + "segment": "SEG_BRAM0_L_X30Y180", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y181": { + "bits": {}, + "grid_x": 79, + "grid_y": 19, + "segment": "SEG_BRAM1_L_X30Y180", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y182": { + "bits": {}, + "grid_x": 79, + "grid_y": 18, + "segment": "SEG_BRAM2_L_X30Y180", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y183": { + "bits": {}, + "grid_x": 79, + "grid_y": 17, + "segment": "SEG_BRAM3_L_X30Y180", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y184": { + "bits": {}, + "grid_x": 79, + "grid_y": 16, + "segment": "SEG_BRAM4_L_X30Y180", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y185": { + "bits": {}, + "grid_x": 79, + "grid_y": 15, + "segment": "SEG_BRAM0_L_X30Y185", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y186": { + "bits": {}, + "grid_x": 79, + "grid_y": 14, + "segment": "SEG_BRAM1_L_X30Y185", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y187": { + "bits": {}, + "grid_x": 79, + "grid_y": 13, + "segment": "SEG_BRAM2_L_X30Y185", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y188": { + "bits": {}, + "grid_x": 79, + "grid_y": 12, + "segment": "SEG_BRAM3_L_X30Y185", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y189": { + "bits": {}, + "grid_x": 79, + "grid_y": 11, + "segment": "SEG_BRAM4_L_X30Y185", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y19": { + "bits": {}, + "grid_x": 79, + "grid_y": 188, + "segment": "SEG_BRAM4_L_X30Y15", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y190": { + "bits": {}, + "grid_x": 79, + "grid_y": 10, + "segment": "SEG_BRAM0_L_X30Y190", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y191": { + "bits": {}, + "grid_x": 79, + "grid_y": 9, + "segment": "SEG_BRAM1_L_X30Y190", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y192": { + "bits": {}, + "grid_x": 79, + "grid_y": 8, + "segment": "SEG_BRAM2_L_X30Y190", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y193": { + "bits": {}, + "grid_x": 79, + "grid_y": 7, + "segment": "SEG_BRAM3_L_X30Y190", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y194": { + "bits": {}, + "grid_x": 79, + "grid_y": 6, + "segment": "SEG_BRAM4_L_X30Y190", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y195": { + "bits": {}, + "grid_x": 79, + "grid_y": 5, + "segment": "SEG_BRAM0_L_X30Y195", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y196": { + "bits": {}, + "grid_x": 79, + "grid_y": 4, + "segment": "SEG_BRAM1_L_X30Y195", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y197": { + "bits": {}, + "grid_x": 79, + "grid_y": 3, + "segment": "SEG_BRAM2_L_X30Y195", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y198": { + "bits": {}, + "grid_x": 79, + "grid_y": 2, + "segment": "SEG_BRAM3_L_X30Y195", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y199": { + "bits": {}, + "grid_x": 79, + "grid_y": 1, + "segment": "SEG_BRAM4_L_X30Y195", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y2": { + "bits": {}, + "grid_x": 79, + "grid_y": 205, + "segment": "SEG_BRAM2_L_X30Y0", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y20": { + "bits": {}, + "grid_x": 79, + "grid_y": 187, + "segment": "SEG_BRAM0_L_X30Y20", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y21": { + "bits": {}, + "grid_x": 79, + "grid_y": 186, + "segment": "SEG_BRAM1_L_X30Y20", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y22": { + "bits": {}, + "grid_x": 79, + "grid_y": 185, + "segment": "SEG_BRAM2_L_X30Y20", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y23": { + "bits": {}, + "grid_x": 79, + "grid_y": 184, + "segment": "SEG_BRAM3_L_X30Y20", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y24": { + "bits": {}, + "grid_x": 79, + "grid_y": 183, + "segment": "SEG_BRAM4_L_X30Y20", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y25": { + "bits": {}, + "grid_x": 79, + "grid_y": 181, + "segment": "SEG_BRAM0_L_X30Y25", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y26": { + "bits": {}, + "grid_x": 79, + "grid_y": 180, + "segment": "SEG_BRAM1_L_X30Y25", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y27": { + "bits": {}, + "grid_x": 79, + "grid_y": 179, + "segment": "SEG_BRAM2_L_X30Y25", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y28": { + "bits": {}, + "grid_x": 79, + "grid_y": 178, + "segment": "SEG_BRAM3_L_X30Y25", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y29": { + "bits": {}, + "grid_x": 79, + "grid_y": 177, + "segment": "SEG_BRAM4_L_X30Y25", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y3": { + "bits": {}, + "grid_x": 79, + "grid_y": 204, + "segment": "SEG_BRAM3_L_X30Y0", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y30": { + "bits": {}, + "grid_x": 79, + "grid_y": 176, + "segment": "SEG_BRAM0_L_X30Y30", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y31": { + "bits": {}, + "grid_x": 79, + "grid_y": 175, + "segment": "SEG_BRAM1_L_X30Y30", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y32": { + "bits": {}, + "grid_x": 79, + "grid_y": 174, + "segment": "SEG_BRAM2_L_X30Y30", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y33": { + "bits": {}, + "grid_x": 79, + "grid_y": 173, + "segment": "SEG_BRAM3_L_X30Y30", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y34": { + "bits": {}, + "grid_x": 79, + "grid_y": 172, + "segment": "SEG_BRAM4_L_X30Y30", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y35": { + "bits": {}, + "grid_x": 79, + "grid_y": 171, + "segment": "SEG_BRAM0_L_X30Y35", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y36": { + "bits": {}, + "grid_x": 79, + "grid_y": 170, + "segment": "SEG_BRAM1_L_X30Y35", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y37": { + "bits": {}, + "grid_x": 79, + "grid_y": 169, + "segment": "SEG_BRAM2_L_X30Y35", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y38": { + "bits": {}, + "grid_x": 79, + "grid_y": 168, + "segment": "SEG_BRAM3_L_X30Y35", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y39": { + "bits": {}, + "grid_x": 79, + "grid_y": 167, + "segment": "SEG_BRAM4_L_X30Y35", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y4": { + "bits": {}, + "grid_x": 79, + "grid_y": 203, + "segment": "SEG_BRAM4_L_X30Y0", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y40": { + "bits": {}, + "grid_x": 79, + "grid_y": 166, + "segment": "SEG_BRAM0_L_X30Y40", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y41": { + "bits": {}, + "grid_x": 79, + "grid_y": 165, + "segment": "SEG_BRAM1_L_X30Y40", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y42": { + "bits": {}, + "grid_x": 79, + "grid_y": 164, + "segment": "SEG_BRAM2_L_X30Y40", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y43": { + "bits": {}, + "grid_x": 79, + "grid_y": 163, + "segment": "SEG_BRAM3_L_X30Y40", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y44": { + "bits": {}, + "grid_x": 79, + "grid_y": 162, + "segment": "SEG_BRAM4_L_X30Y40", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y45": { + "bits": {}, + "grid_x": 79, + "grid_y": 161, + "segment": "SEG_BRAM0_L_X30Y45", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y46": { + "bits": {}, + "grid_x": 79, + "grid_y": 160, + "segment": "SEG_BRAM1_L_X30Y45", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y47": { + "bits": {}, + "grid_x": 79, + "grid_y": 159, + "segment": "SEG_BRAM2_L_X30Y45", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y48": { + "bits": {}, + "grid_x": 79, + "grid_y": 158, + "segment": "SEG_BRAM3_L_X30Y45", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y49": { + "bits": {}, + "grid_x": 79, + "grid_y": 157, + "segment": "SEG_BRAM4_L_X30Y45", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y5": { + "bits": {}, + "grid_x": 79, + "grid_y": 202, + "segment": "SEG_BRAM0_L_X30Y5", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y50": { + "bits": {}, + "grid_x": 79, + "grid_y": 155, + "segment": "SEG_BRAM0_L_X30Y50", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y51": { + "bits": {}, + "grid_x": 79, + "grid_y": 154, + "segment": "SEG_BRAM1_L_X30Y50", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y52": { + "bits": {}, + "grid_x": 79, + "grid_y": 153, + "segment": "SEG_BRAM2_L_X30Y50", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y53": { + "bits": {}, + "grid_x": 79, + "grid_y": 152, + "segment": "SEG_BRAM3_L_X30Y50", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y54": { + "bits": {}, + "grid_x": 79, + "grid_y": 151, + "segment": "SEG_BRAM4_L_X30Y50", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y55": { + "bits": {}, + "grid_x": 79, + "grid_y": 150, + "segment": "SEG_BRAM0_L_X30Y55", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y56": { + "bits": {}, + "grid_x": 79, + "grid_y": 149, + "segment": "SEG_BRAM1_L_X30Y55", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y57": { + "bits": {}, + "grid_x": 79, + "grid_y": 148, + "segment": "SEG_BRAM2_L_X30Y55", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y58": { + "bits": {}, + "grid_x": 79, + "grid_y": 147, + "segment": "SEG_BRAM3_L_X30Y55", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y59": { + "bits": {}, + "grid_x": 79, + "grid_y": 146, + "segment": "SEG_BRAM4_L_X30Y55", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y6": { + "bits": {}, + "grid_x": 79, + "grid_y": 201, + "segment": "SEG_BRAM1_L_X30Y5", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y60": { + "bits": {}, + "grid_x": 79, + "grid_y": 145, + "segment": "SEG_BRAM0_L_X30Y60", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y61": { + "bits": {}, + "grid_x": 79, + "grid_y": 144, + "segment": "SEG_BRAM1_L_X30Y60", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y62": { + "bits": {}, + "grid_x": 79, + "grid_y": 143, + "segment": "SEG_BRAM2_L_X30Y60", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y63": { + "bits": {}, + "grid_x": 79, + "grid_y": 142, + "segment": "SEG_BRAM3_L_X30Y60", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y64": { + "bits": {}, + "grid_x": 79, + "grid_y": 141, + "segment": "SEG_BRAM4_L_X30Y60", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y65": { + "bits": {}, + "grid_x": 79, + "grid_y": 140, + "segment": "SEG_BRAM0_L_X30Y65", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y66": { + "bits": {}, + "grid_x": 79, + "grid_y": 139, + "segment": "SEG_BRAM1_L_X30Y65", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y67": { + "bits": {}, + "grid_x": 79, + "grid_y": 138, + "segment": "SEG_BRAM2_L_X30Y65", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y68": { + "bits": {}, + "grid_x": 79, + "grid_y": 137, + "segment": "SEG_BRAM3_L_X30Y65", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y69": { + "bits": {}, + "grid_x": 79, + "grid_y": 136, + "segment": "SEG_BRAM4_L_X30Y65", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y7": { + "bits": {}, + "grid_x": 79, + "grid_y": 200, + "segment": "SEG_BRAM2_L_X30Y5", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y70": { + "bits": {}, + "grid_x": 79, + "grid_y": 135, + "segment": "SEG_BRAM0_L_X30Y70", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y71": { + "bits": {}, + "grid_x": 79, + "grid_y": 134, + "segment": "SEG_BRAM1_L_X30Y70", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y72": { + "bits": {}, + "grid_x": 79, + "grid_y": 133, + "segment": "SEG_BRAM2_L_X30Y70", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y73": { + "bits": {}, + "grid_x": 79, + "grid_y": 132, + "segment": "SEG_BRAM3_L_X30Y70", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y74": { + "bits": {}, + "grid_x": 79, + "grid_y": 131, + "segment": "SEG_BRAM4_L_X30Y70", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y75": { + "bits": {}, + "grid_x": 79, + "grid_y": 129, + "segment": "SEG_BRAM0_L_X30Y75", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y76": { + "bits": {}, + "grid_x": 79, + "grid_y": 128, + "segment": "SEG_BRAM1_L_X30Y75", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y77": { + "bits": {}, + "grid_x": 79, + "grid_y": 127, + "segment": "SEG_BRAM2_L_X30Y75", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y78": { + "bits": {}, + "grid_x": 79, + "grid_y": 126, + "segment": "SEG_BRAM3_L_X30Y75", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y79": { + "bits": {}, + "grid_x": 79, + "grid_y": 125, + "segment": "SEG_BRAM4_L_X30Y75", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y8": { + "bits": {}, + "grid_x": 79, + "grid_y": 199, + "segment": "SEG_BRAM3_L_X30Y5", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y80": { + "bits": {}, + "grid_x": 79, + "grid_y": 124, + "segment": "SEG_BRAM0_L_X30Y80", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y81": { + "bits": {}, + "grid_x": 79, + "grid_y": 123, + "segment": "SEG_BRAM1_L_X30Y80", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y82": { + "bits": {}, + "grid_x": 79, + "grid_y": 122, + "segment": "SEG_BRAM2_L_X30Y80", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y83": { + "bits": {}, + "grid_x": 79, + "grid_y": 121, + "segment": "SEG_BRAM3_L_X30Y80", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y84": { + "bits": {}, + "grid_x": 79, + "grid_y": 120, + "segment": "SEG_BRAM4_L_X30Y80", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y85": { + "bits": {}, + "grid_x": 79, + "grid_y": 119, + "segment": "SEG_BRAM0_L_X30Y85", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y86": { + "bits": {}, + "grid_x": 79, + "grid_y": 118, + "segment": "SEG_BRAM1_L_X30Y85", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y87": { + "bits": {}, + "grid_x": 79, + "grid_y": 117, + "segment": "SEG_BRAM2_L_X30Y85", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y88": { + "bits": {}, + "grid_x": 79, + "grid_y": 116, + "segment": "SEG_BRAM3_L_X30Y85", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y89": { + "bits": {}, + "grid_x": 79, + "grid_y": 115, + "segment": "SEG_BRAM4_L_X30Y85", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y9": { + "bits": {}, + "grid_x": 79, + "grid_y": 198, + "segment": "SEG_BRAM4_L_X30Y5", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y90": { + "bits": {}, + "grid_x": 79, + "grid_y": 114, + "segment": "SEG_BRAM0_L_X30Y90", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y91": { + "bits": {}, + "grid_x": 79, + "grid_y": 113, + "segment": "SEG_BRAM1_L_X30Y90", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y92": { + "bits": {}, + "grid_x": 79, + "grid_y": 112, + "segment": "SEG_BRAM2_L_X30Y90", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y93": { + "bits": {}, + "grid_x": 79, + "grid_y": 111, + "segment": "SEG_BRAM3_L_X30Y90", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y94": { + "bits": {}, + "grid_x": 79, + "grid_y": 110, + "segment": "SEG_BRAM4_L_X30Y90", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y95": { + "bits": {}, + "grid_x": 79, + "grid_y": 109, + "segment": "SEG_BRAM0_L_X30Y95", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X32Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y96": { + "bits": {}, + "grid_x": 79, + "grid_y": 108, + "segment": "SEG_BRAM1_L_X30Y95", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X32Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y97": { + "bits": {}, + "grid_x": 79, + "grid_y": 107, + "segment": "SEG_BRAM2_L_X30Y95", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X32Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y98": { + "bits": {}, + "grid_x": 79, + "grid_y": 106, + "segment": "SEG_BRAM3_L_X30Y95", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X32Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X30Y99": { + "bits": {}, + "grid_x": 79, + "grid_y": 105, + "segment": "SEG_BRAM4_L_X30Y95", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X32Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y0": { + "bits": {}, + "grid_x": 84, + "grid_y": 207, + "segment": "SEG_CLBLM_L_X32Y0", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y1": { + "bits": {}, + "grid_x": 84, + "grid_y": 206, + "segment": "SEG_CLBLM_L_X32Y1", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y10": { + "bits": {}, + "grid_x": 84, + "grid_y": 197, + "segment": "SEG_CLBLM_L_X32Y10", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y100": { + "bits": {}, + "grid_x": 84, + "grid_y": 103, + "segment": "SEG_CLBLM_L_X32Y100", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y101": { + "bits": {}, + "grid_x": 84, + "grid_y": 102, + "segment": "SEG_CLBLM_L_X32Y101", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y102": { + "bits": {}, + "grid_x": 84, + "grid_y": 101, + "segment": "SEG_CLBLM_L_X32Y102", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y103": { + "bits": {}, + "grid_x": 84, + "grid_y": 100, + "segment": "SEG_CLBLM_L_X32Y103", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y104": { + "bits": {}, + "grid_x": 84, + "grid_y": 99, + "segment": "SEG_CLBLM_L_X32Y104", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y105": { + "bits": {}, + "grid_x": 84, + "grid_y": 98, + "segment": "SEG_CLBLM_L_X32Y105", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y106": { + "bits": {}, + "grid_x": 84, + "grid_y": 97, + "segment": "SEG_CLBLM_L_X32Y106", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y107": { + "bits": {}, + "grid_x": 84, + "grid_y": 96, + "segment": "SEG_CLBLM_L_X32Y107", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y108": { + "bits": {}, + "grid_x": 84, + "grid_y": 95, + "segment": "SEG_CLBLM_L_X32Y108", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y109": { + "bits": {}, + "grid_x": 84, + "grid_y": 94, + "segment": "SEG_CLBLM_L_X32Y109", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y11": { + "bits": {}, + "grid_x": 84, + "grid_y": 196, + "segment": "SEG_CLBLM_L_X32Y11", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y110": { + "bits": {}, + "grid_x": 84, + "grid_y": 93, + "segment": "SEG_CLBLM_L_X32Y110", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y111": { + "bits": {}, + "grid_x": 84, + "grid_y": 92, + "segment": "SEG_CLBLM_L_X32Y111", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y112": { + "bits": {}, + "grid_x": 84, + "grid_y": 91, + "segment": "SEG_CLBLM_L_X32Y112", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y113": { + "bits": {}, + "grid_x": 84, + "grid_y": 90, + "segment": "SEG_CLBLM_L_X32Y113", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y114": { + "bits": {}, + "grid_x": 84, + "grid_y": 89, + "segment": "SEG_CLBLM_L_X32Y114", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y115": { + "bits": {}, + "grid_x": 84, + "grid_y": 88, + "segment": "SEG_CLBLM_L_X32Y115", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y116": { + "bits": {}, + "grid_x": 84, + "grid_y": 87, + "segment": "SEG_CLBLM_L_X32Y116", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y117": { + "bits": {}, + "grid_x": 84, + "grid_y": 86, + "segment": "SEG_CLBLM_L_X32Y117", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y118": { + "bits": {}, + "grid_x": 84, + "grid_y": 85, + "segment": "SEG_CLBLM_L_X32Y118", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y119": { + "bits": {}, + "grid_x": 84, + "grid_y": 84, + "segment": "SEG_CLBLM_L_X32Y119", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y12": { + "bits": {}, + "grid_x": 84, + "grid_y": 195, + "segment": "SEG_CLBLM_L_X32Y12", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y120": { + "bits": {}, + "grid_x": 84, + "grid_y": 83, + "segment": "SEG_CLBLM_L_X32Y120", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y121": { + "bits": {}, + "grid_x": 84, + "grid_y": 82, + "segment": "SEG_CLBLM_L_X32Y121", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y122": { + "bits": {}, + "grid_x": 84, + "grid_y": 81, + "segment": "SEG_CLBLM_L_X32Y122", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y123": { + "bits": {}, + "grid_x": 84, + "grid_y": 80, + "segment": "SEG_CLBLM_L_X32Y123", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y124": { + "bits": {}, + "grid_x": 84, + "grid_y": 79, + "segment": "SEG_CLBLM_L_X32Y124", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y125": { + "bits": {}, + "grid_x": 84, + "grid_y": 77, + "segment": "SEG_CLBLM_L_X32Y125", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y126": { + "bits": {}, + "grid_x": 84, + "grid_y": 76, + "segment": "SEG_CLBLM_L_X32Y126", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y127": { + "bits": {}, + "grid_x": 84, + "grid_y": 75, + "segment": "SEG_CLBLM_L_X32Y127", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y128": { + "bits": {}, + "grid_x": 84, + "grid_y": 74, + "segment": "SEG_CLBLM_L_X32Y128", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y129": { + "bits": {}, + "grid_x": 84, + "grid_y": 73, + "segment": "SEG_CLBLM_L_X32Y129", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y13": { + "bits": {}, + "grid_x": 84, + "grid_y": 194, + "segment": "SEG_CLBLM_L_X32Y13", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y130": { + "bits": {}, + "grid_x": 84, + "grid_y": 72, + "segment": "SEG_CLBLM_L_X32Y130", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y131": { + "bits": {}, + "grid_x": 84, + "grid_y": 71, + "segment": "SEG_CLBLM_L_X32Y131", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y132": { + "bits": {}, + "grid_x": 84, + "grid_y": 70, + "segment": "SEG_CLBLM_L_X32Y132", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y133": { + "bits": {}, + "grid_x": 84, + "grid_y": 69, + "segment": "SEG_CLBLM_L_X32Y133", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y134": { + "bits": {}, + "grid_x": 84, + "grid_y": 68, + "segment": "SEG_CLBLM_L_X32Y134", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y135": { + "bits": {}, + "grid_x": 84, + "grid_y": 67, + "segment": "SEG_CLBLM_L_X32Y135", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y136": { + "bits": {}, + "grid_x": 84, + "grid_y": 66, + "segment": "SEG_CLBLM_L_X32Y136", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y137": { + "bits": {}, + "grid_x": 84, + "grid_y": 65, + "segment": "SEG_CLBLM_L_X32Y137", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y138": { + "bits": {}, + "grid_x": 84, + "grid_y": 64, + "segment": "SEG_CLBLM_L_X32Y138", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y139": { + "bits": {}, + "grid_x": 84, + "grid_y": 63, + "segment": "SEG_CLBLM_L_X32Y139", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y14": { + "bits": {}, + "grid_x": 84, + "grid_y": 193, + "segment": "SEG_CLBLM_L_X32Y14", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y140": { + "bits": {}, + "grid_x": 84, + "grid_y": 62, + "segment": "SEG_CLBLM_L_X32Y140", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y141": { + "bits": {}, + "grid_x": 84, + "grid_y": 61, + "segment": "SEG_CLBLM_L_X32Y141", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y142": { + "bits": {}, + "grid_x": 84, + "grid_y": 60, + "segment": "SEG_CLBLM_L_X32Y142", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y143": { + "bits": {}, + "grid_x": 84, + "grid_y": 59, + "segment": "SEG_CLBLM_L_X32Y143", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y144": { + "bits": {}, + "grid_x": 84, + "grid_y": 58, + "segment": "SEG_CLBLM_L_X32Y144", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y145": { + "bits": {}, + "grid_x": 84, + "grid_y": 57, + "segment": "SEG_CLBLM_L_X32Y145", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y146": { + "bits": {}, + "grid_x": 84, + "grid_y": 56, + "segment": "SEG_CLBLM_L_X32Y146", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y147": { + "bits": {}, + "grid_x": 84, + "grid_y": 55, + "segment": "SEG_CLBLM_L_X32Y147", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y148": { + "bits": {}, + "grid_x": 84, + "grid_y": 54, + "segment": "SEG_CLBLM_L_X32Y148", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y149": { + "bits": {}, + "grid_x": 84, + "grid_y": 53, + "segment": "SEG_CLBLM_L_X32Y149", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y15": { + "bits": {}, + "grid_x": 84, + "grid_y": 192, + "segment": "SEG_CLBLM_L_X32Y15", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y150": { + "bits": {}, + "grid_x": 84, + "grid_y": 51, + "segment": "SEG_CLBLM_L_X32Y150", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y151": { + "bits": {}, + "grid_x": 84, + "grid_y": 50, + "segment": "SEG_CLBLM_L_X32Y151", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y152": { + "bits": {}, + "grid_x": 84, + "grid_y": 49, + "segment": "SEG_CLBLM_L_X32Y152", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y153": { + "bits": {}, + "grid_x": 84, + "grid_y": 48, + "segment": "SEG_CLBLM_L_X32Y153", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y154": { + "bits": {}, + "grid_x": 84, + "grid_y": 47, + "segment": "SEG_CLBLM_L_X32Y154", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y155": { + "bits": {}, + "grid_x": 84, + "grid_y": 46, + "segment": "SEG_CLBLM_L_X32Y155", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y156": { + "bits": {}, + "grid_x": 84, + "grid_y": 45, + "segment": "SEG_CLBLM_L_X32Y156", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y157": { + "bits": {}, + "grid_x": 84, + "grid_y": 44, + "segment": "SEG_CLBLM_L_X32Y157", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y158": { + "bits": {}, + "grid_x": 84, + "grid_y": 43, + "segment": "SEG_CLBLM_L_X32Y158", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y159": { + "bits": {}, + "grid_x": 84, + "grid_y": 42, + "segment": "SEG_CLBLM_L_X32Y159", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y16": { + "bits": {}, + "grid_x": 84, + "grid_y": 191, + "segment": "SEG_CLBLM_L_X32Y16", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y160": { + "bits": {}, + "grid_x": 84, + "grid_y": 41, + "segment": "SEG_CLBLM_L_X32Y160", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y161": { + "bits": {}, + "grid_x": 84, + "grid_y": 40, + "segment": "SEG_CLBLM_L_X32Y161", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y162": { + "bits": {}, + "grid_x": 84, + "grid_y": 39, + "segment": "SEG_CLBLM_L_X32Y162", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y163": { + "bits": {}, + "grid_x": 84, + "grid_y": 38, + "segment": "SEG_CLBLM_L_X32Y163", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y164": { + "bits": {}, + "grid_x": 84, + "grid_y": 37, + "segment": "SEG_CLBLM_L_X32Y164", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y165": { + "bits": {}, + "grid_x": 84, + "grid_y": 36, + "segment": "SEG_CLBLM_L_X32Y165", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y166": { + "bits": {}, + "grid_x": 84, + "grid_y": 35, + "segment": "SEG_CLBLM_L_X32Y166", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y167": { + "bits": {}, + "grid_x": 84, + "grid_y": 34, + "segment": "SEG_CLBLM_L_X32Y167", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y168": { + "bits": {}, + "grid_x": 84, + "grid_y": 33, + "segment": "SEG_CLBLM_L_X32Y168", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y169": { + "bits": {}, + "grid_x": 84, + "grid_y": 32, + "segment": "SEG_CLBLM_L_X32Y169", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y17": { + "bits": {}, + "grid_x": 84, + "grid_y": 190, + "segment": "SEG_CLBLM_L_X32Y17", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y170": { + "bits": {}, + "grid_x": 84, + "grid_y": 31, + "segment": "SEG_CLBLM_L_X32Y170", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y171": { + "bits": {}, + "grid_x": 84, + "grid_y": 30, + "segment": "SEG_CLBLM_L_X32Y171", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y172": { + "bits": {}, + "grid_x": 84, + "grid_y": 29, + "segment": "SEG_CLBLM_L_X32Y172", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y173": { + "bits": {}, + "grid_x": 84, + "grid_y": 28, + "segment": "SEG_CLBLM_L_X32Y173", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y174": { + "bits": {}, + "grid_x": 84, + "grid_y": 27, + "segment": "SEG_CLBLM_L_X32Y174", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y175": { + "bits": {}, + "grid_x": 84, + "grid_y": 25, + "segment": "SEG_CLBLM_L_X32Y175", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y176": { + "bits": {}, + "grid_x": 84, + "grid_y": 24, + "segment": "SEG_CLBLM_L_X32Y176", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y177": { + "bits": {}, + "grid_x": 84, + "grid_y": 23, + "segment": "SEG_CLBLM_L_X32Y177", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y178": { + "bits": {}, + "grid_x": 84, + "grid_y": 22, + "segment": "SEG_CLBLM_L_X32Y178", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y179": { + "bits": {}, + "grid_x": 84, + "grid_y": 21, + "segment": "SEG_CLBLM_L_X32Y179", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y18": { + "bits": {}, + "grid_x": 84, + "grid_y": 189, + "segment": "SEG_CLBLM_L_X32Y18", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y180": { + "bits": {}, + "grid_x": 84, + "grid_y": 20, + "segment": "SEG_CLBLM_L_X32Y180", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y181": { + "bits": {}, + "grid_x": 84, + "grid_y": 19, + "segment": "SEG_CLBLM_L_X32Y181", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y182": { + "bits": {}, + "grid_x": 84, + "grid_y": 18, + "segment": "SEG_CLBLM_L_X32Y182", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y183": { + "bits": {}, + "grid_x": 84, + "grid_y": 17, + "segment": "SEG_CLBLM_L_X32Y183", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y184": { + "bits": {}, + "grid_x": 84, + "grid_y": 16, + "segment": "SEG_CLBLM_L_X32Y184", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y185": { + "bits": {}, + "grid_x": 84, + "grid_y": 15, + "segment": "SEG_CLBLM_L_X32Y185", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y186": { + "bits": {}, + "grid_x": 84, + "grid_y": 14, + "segment": "SEG_CLBLM_L_X32Y186", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y187": { + "bits": {}, + "grid_x": 84, + "grid_y": 13, + "segment": "SEG_CLBLM_L_X32Y187", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y188": { + "bits": {}, + "grid_x": 84, + "grid_y": 12, + "segment": "SEG_CLBLM_L_X32Y188", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y189": { + "bits": {}, + "grid_x": 84, + "grid_y": 11, + "segment": "SEG_CLBLM_L_X32Y189", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y19": { + "bits": {}, + "grid_x": 84, + "grid_y": 188, + "segment": "SEG_CLBLM_L_X32Y19", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y190": { + "bits": {}, + "grid_x": 84, + "grid_y": 10, + "segment": "SEG_CLBLM_L_X32Y190", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y191": { + "bits": {}, + "grid_x": 84, + "grid_y": 9, + "segment": "SEG_CLBLM_L_X32Y191", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y192": { + "bits": {}, + "grid_x": 84, + "grid_y": 8, + "segment": "SEG_CLBLM_L_X32Y192", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y193": { + "bits": {}, + "grid_x": 84, + "grid_y": 7, + "segment": "SEG_CLBLM_L_X32Y193", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y194": { + "bits": {}, + "grid_x": 84, + "grid_y": 6, + "segment": "SEG_CLBLM_L_X32Y194", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y195": { + "bits": {}, + "grid_x": 84, + "grid_y": 5, + "segment": "SEG_CLBLM_L_X32Y195", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y196": { + "bits": {}, + "grid_x": 84, + "grid_y": 4, + "segment": "SEG_CLBLM_L_X32Y196", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y197": { + "bits": {}, + "grid_x": 84, + "grid_y": 3, + "segment": "SEG_CLBLM_L_X32Y197", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y198": { + "bits": {}, + "grid_x": 84, + "grid_y": 2, + "segment": "SEG_CLBLM_L_X32Y198", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y199": { + "bits": {}, + "grid_x": 84, + "grid_y": 1, + "segment": "SEG_CLBLM_L_X32Y199", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y2": { + "bits": {}, + "grid_x": 84, + "grid_y": 205, + "segment": "SEG_CLBLM_L_X32Y2", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y20": { + "bits": {}, + "grid_x": 84, + "grid_y": 187, + "segment": "SEG_CLBLM_L_X32Y20", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y21": { + "bits": {}, + "grid_x": 84, + "grid_y": 186, + "segment": "SEG_CLBLM_L_X32Y21", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y22": { + "bits": {}, + "grid_x": 84, + "grid_y": 185, + "segment": "SEG_CLBLM_L_X32Y22", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y23": { + "bits": {}, + "grid_x": 84, + "grid_y": 184, + "segment": "SEG_CLBLM_L_X32Y23", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y24": { + "bits": {}, + "grid_x": 84, + "grid_y": 183, + "segment": "SEG_CLBLM_L_X32Y24", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y25": { + "bits": {}, + "grid_x": 84, + "grid_y": 181, + "segment": "SEG_CLBLM_L_X32Y25", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y26": { + "bits": {}, + "grid_x": 84, + "grid_y": 180, + "segment": "SEG_CLBLM_L_X32Y26", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y27": { + "bits": {}, + "grid_x": 84, + "grid_y": 179, + "segment": "SEG_CLBLM_L_X32Y27", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y28": { + "bits": {}, + "grid_x": 84, + "grid_y": 178, + "segment": "SEG_CLBLM_L_X32Y28", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y29": { + "bits": {}, + "grid_x": 84, + "grid_y": 177, + "segment": "SEG_CLBLM_L_X32Y29", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y3": { + "bits": {}, + "grid_x": 84, + "grid_y": 204, + "segment": "SEG_CLBLM_L_X32Y3", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y30": { + "bits": {}, + "grid_x": 84, + "grid_y": 176, + "segment": "SEG_CLBLM_L_X32Y30", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y31": { + "bits": {}, + "grid_x": 84, + "grid_y": 175, + "segment": "SEG_CLBLM_L_X32Y31", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y32": { + "bits": {}, + "grid_x": 84, + "grid_y": 174, + "segment": "SEG_CLBLM_L_X32Y32", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y33": { + "bits": {}, + "grid_x": 84, + "grid_y": 173, + "segment": "SEG_CLBLM_L_X32Y33", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y34": { + "bits": {}, + "grid_x": 84, + "grid_y": 172, + "segment": "SEG_CLBLM_L_X32Y34", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y35": { + "bits": {}, + "grid_x": 84, + "grid_y": 171, + "segment": "SEG_CLBLM_L_X32Y35", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y36": { + "bits": {}, + "grid_x": 84, + "grid_y": 170, + "segment": "SEG_CLBLM_L_X32Y36", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y37": { + "bits": {}, + "grid_x": 84, + "grid_y": 169, + "segment": "SEG_CLBLM_L_X32Y37", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y38": { + "bits": {}, + "grid_x": 84, + "grid_y": 168, + "segment": "SEG_CLBLM_L_X32Y38", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y39": { + "bits": {}, + "grid_x": 84, + "grid_y": 167, + "segment": "SEG_CLBLM_L_X32Y39", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y4": { + "bits": {}, + "grid_x": 84, + "grid_y": 203, + "segment": "SEG_CLBLM_L_X32Y4", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y40": { + "bits": {}, + "grid_x": 84, + "grid_y": 166, + "segment": "SEG_CLBLM_L_X32Y40", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y41": { + "bits": {}, + "grid_x": 84, + "grid_y": 165, + "segment": "SEG_CLBLM_L_X32Y41", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y42": { + "bits": {}, + "grid_x": 84, + "grid_y": 164, + "segment": "SEG_CLBLM_L_X32Y42", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y43": { + "bits": {}, + "grid_x": 84, + "grid_y": 163, + "segment": "SEG_CLBLM_L_X32Y43", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y44": { + "bits": {}, + "grid_x": 84, + "grid_y": 162, + "segment": "SEG_CLBLM_L_X32Y44", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y45": { + "bits": {}, + "grid_x": 84, + "grid_y": 161, + "segment": "SEG_CLBLM_L_X32Y45", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y46": { + "bits": {}, + "grid_x": 84, + "grid_y": 160, + "segment": "SEG_CLBLM_L_X32Y46", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y47": { + "bits": {}, + "grid_x": 84, + "grid_y": 159, + "segment": "SEG_CLBLM_L_X32Y47", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y48": { + "bits": {}, + "grid_x": 84, + "grid_y": 158, + "segment": "SEG_CLBLM_L_X32Y48", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y49": { + "bits": {}, + "grid_x": 84, + "grid_y": 157, + "segment": "SEG_CLBLM_L_X32Y49", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y5": { + "bits": {}, + "grid_x": 84, + "grid_y": 202, + "segment": "SEG_CLBLM_L_X32Y5", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y50": { + "bits": {}, + "grid_x": 84, + "grid_y": 155, + "segment": "SEG_CLBLM_L_X32Y50", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y51": { + "bits": {}, + "grid_x": 84, + "grid_y": 154, + "segment": "SEG_CLBLM_L_X32Y51", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y52": { + "bits": {}, + "grid_x": 84, + "grid_y": 153, + "segment": "SEG_CLBLM_L_X32Y52", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y53": { + "bits": {}, + "grid_x": 84, + "grid_y": 152, + "segment": "SEG_CLBLM_L_X32Y53", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y54": { + "bits": {}, + "grid_x": 84, + "grid_y": 151, + "segment": "SEG_CLBLM_L_X32Y54", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y55": { + "bits": {}, + "grid_x": 84, + "grid_y": 150, + "segment": "SEG_CLBLM_L_X32Y55", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y56": { + "bits": {}, + "grid_x": 84, + "grid_y": 149, + "segment": "SEG_CLBLM_L_X32Y56", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y57": { + "bits": {}, + "grid_x": 84, + "grid_y": 148, + "segment": "SEG_CLBLM_L_X32Y57", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y58": { + "bits": {}, + "grid_x": 84, + "grid_y": 147, + "segment": "SEG_CLBLM_L_X32Y58", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y59": { + "bits": {}, + "grid_x": 84, + "grid_y": 146, + "segment": "SEG_CLBLM_L_X32Y59", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y6": { + "bits": {}, + "grid_x": 84, + "grid_y": 201, + "segment": "SEG_CLBLM_L_X32Y6", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y60": { + "bits": {}, + "grid_x": 84, + "grid_y": 145, + "segment": "SEG_CLBLM_L_X32Y60", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y61": { + "bits": {}, + "grid_x": 84, + "grid_y": 144, + "segment": "SEG_CLBLM_L_X32Y61", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y62": { + "bits": {}, + "grid_x": 84, + "grid_y": 143, + "segment": "SEG_CLBLM_L_X32Y62", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y63": { + "bits": {}, + "grid_x": 84, + "grid_y": 142, + "segment": "SEG_CLBLM_L_X32Y63", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y64": { + "bits": {}, + "grid_x": 84, + "grid_y": 141, + "segment": "SEG_CLBLM_L_X32Y64", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y65": { + "bits": {}, + "grid_x": 84, + "grid_y": 140, + "segment": "SEG_CLBLM_L_X32Y65", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y66": { + "bits": {}, + "grid_x": 84, + "grid_y": 139, + "segment": "SEG_CLBLM_L_X32Y66", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y67": { + "bits": {}, + "grid_x": 84, + "grid_y": 138, + "segment": "SEG_CLBLM_L_X32Y67", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y68": { + "bits": {}, + "grid_x": 84, + "grid_y": 137, + "segment": "SEG_CLBLM_L_X32Y68", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y69": { + "bits": {}, + "grid_x": 84, + "grid_y": 136, + "segment": "SEG_CLBLM_L_X32Y69", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y7": { + "bits": {}, + "grid_x": 84, + "grid_y": 200, + "segment": "SEG_CLBLM_L_X32Y7", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y70": { + "bits": {}, + "grid_x": 84, + "grid_y": 135, + "segment": "SEG_CLBLM_L_X32Y70", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y71": { + "bits": {}, + "grid_x": 84, + "grid_y": 134, + "segment": "SEG_CLBLM_L_X32Y71", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y72": { + "bits": {}, + "grid_x": 84, + "grid_y": 133, + "segment": "SEG_CLBLM_L_X32Y72", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y73": { + "bits": {}, + "grid_x": 84, + "grid_y": 132, + "segment": "SEG_CLBLM_L_X32Y73", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y74": { + "bits": {}, + "grid_x": 84, + "grid_y": 131, + "segment": "SEG_CLBLM_L_X32Y74", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y75": { + "bits": {}, + "grid_x": 84, + "grid_y": 129, + "segment": "SEG_CLBLM_L_X32Y75", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y76": { + "bits": {}, + "grid_x": 84, + "grid_y": 128, + "segment": "SEG_CLBLM_L_X32Y76", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y77": { + "bits": {}, + "grid_x": 84, + "grid_y": 127, + "segment": "SEG_CLBLM_L_X32Y77", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y78": { + "bits": {}, + "grid_x": 84, + "grid_y": 126, + "segment": "SEG_CLBLM_L_X32Y78", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y79": { + "bits": {}, + "grid_x": 84, + "grid_y": 125, + "segment": "SEG_CLBLM_L_X32Y79", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y8": { + "bits": {}, + "grid_x": 84, + "grid_y": 199, + "segment": "SEG_CLBLM_L_X32Y8", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y80": { + "bits": {}, + "grid_x": 84, + "grid_y": 124, + "segment": "SEG_CLBLM_L_X32Y80", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y81": { + "bits": {}, + "grid_x": 84, + "grid_y": 123, + "segment": "SEG_CLBLM_L_X32Y81", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y82": { + "bits": {}, + "grid_x": 84, + "grid_y": 122, + "segment": "SEG_CLBLM_L_X32Y82", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y83": { + "bits": {}, + "grid_x": 84, + "grid_y": 121, + "segment": "SEG_CLBLM_L_X32Y83", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y84": { + "bits": {}, + "grid_x": 84, + "grid_y": 120, + "segment": "SEG_CLBLM_L_X32Y84", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y85": { + "bits": {}, + "grid_x": 84, + "grid_y": 119, + "segment": "SEG_CLBLM_L_X32Y85", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y86": { + "bits": {}, + "grid_x": 84, + "grid_y": 118, + "segment": "SEG_CLBLM_L_X32Y86", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y87": { + "bits": {}, + "grid_x": 84, + "grid_y": 117, + "segment": "SEG_CLBLM_L_X32Y87", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y88": { + "bits": {}, + "grid_x": 84, + "grid_y": 116, + "segment": "SEG_CLBLM_L_X32Y88", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y89": { + "bits": {}, + "grid_x": 84, + "grid_y": 115, + "segment": "SEG_CLBLM_L_X32Y89", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y9": { + "bits": {}, + "grid_x": 84, + "grid_y": 198, + "segment": "SEG_CLBLM_L_X32Y9", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y90": { + "bits": {}, + "grid_x": 84, + "grid_y": 114, + "segment": "SEG_CLBLM_L_X32Y90", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y91": { + "bits": {}, + "grid_x": 84, + "grid_y": 113, + "segment": "SEG_CLBLM_L_X32Y91", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y92": { + "bits": {}, + "grid_x": 84, + "grid_y": 112, + "segment": "SEG_CLBLM_L_X32Y92", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y93": { + "bits": {}, + "grid_x": 84, + "grid_y": 111, + "segment": "SEG_CLBLM_L_X32Y93", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y94": { + "bits": {}, + "grid_x": 84, + "grid_y": 110, + "segment": "SEG_CLBLM_L_X32Y94", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y95": { + "bits": {}, + "grid_x": 84, + "grid_y": 109, + "segment": "SEG_CLBLM_L_X32Y95", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y96": { + "bits": {}, + "grid_x": 84, + "grid_y": 108, + "segment": "SEG_CLBLM_L_X32Y96", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y97": { + "bits": {}, + "grid_x": 84, + "grid_y": 107, + "segment": "SEG_CLBLM_L_X32Y97", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y98": { + "bits": {}, + "grid_x": 84, + "grid_y": 106, + "segment": "SEG_CLBLM_L_X32Y98", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X32Y99": { + "bits": {}, + "grid_x": 84, + "grid_y": 105, + "segment": "SEG_CLBLM_L_X32Y99", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X34Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y0": { + "bits": {}, + "grid_x": 89, + "grid_y": 207, + "segment": "SEG_CLBLM_L_X34Y0", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y1": { + "bits": {}, + "grid_x": 89, + "grid_y": 206, + "segment": "SEG_CLBLM_L_X34Y1", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y10": { + "bits": {}, + "grid_x": 89, + "grid_y": 197, + "segment": "SEG_CLBLM_L_X34Y10", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y100": { + "bits": {}, + "grid_x": 89, + "grid_y": 103, + "segment": "SEG_CLBLM_L_X34Y100", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y101": { + "bits": {}, + "grid_x": 89, + "grid_y": 102, + "segment": "SEG_CLBLM_L_X34Y101", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y102": { + "bits": {}, + "grid_x": 89, + "grid_y": 101, + "segment": "SEG_CLBLM_L_X34Y102", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y103": { + "bits": {}, + "grid_x": 89, + "grid_y": 100, + "segment": "SEG_CLBLM_L_X34Y103", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y104": { + "bits": {}, + "grid_x": 89, + "grid_y": 99, + "segment": "SEG_CLBLM_L_X34Y104", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y105": { + "bits": {}, + "grid_x": 89, + "grid_y": 98, + "segment": "SEG_CLBLM_L_X34Y105", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y106": { + "bits": {}, + "grid_x": 89, + "grid_y": 97, + "segment": "SEG_CLBLM_L_X34Y106", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y107": { + "bits": {}, + "grid_x": 89, + "grid_y": 96, + "segment": "SEG_CLBLM_L_X34Y107", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y108": { + "bits": {}, + "grid_x": 89, + "grid_y": 95, + "segment": "SEG_CLBLM_L_X34Y108", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y109": { + "bits": {}, + "grid_x": 89, + "grid_y": 94, + "segment": "SEG_CLBLM_L_X34Y109", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y11": { + "bits": {}, + "grid_x": 89, + "grid_y": 196, + "segment": "SEG_CLBLM_L_X34Y11", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y110": { + "bits": {}, + "grid_x": 89, + "grid_y": 93, + "segment": "SEG_CLBLM_L_X34Y110", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y111": { + "bits": {}, + "grid_x": 89, + "grid_y": 92, + "segment": "SEG_CLBLM_L_X34Y111", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y112": { + "bits": {}, + "grid_x": 89, + "grid_y": 91, + "segment": "SEG_CLBLM_L_X34Y112", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y113": { + "bits": {}, + "grid_x": 89, + "grid_y": 90, + "segment": "SEG_CLBLM_L_X34Y113", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y114": { + "bits": {}, + "grid_x": 89, + "grid_y": 89, + "segment": "SEG_CLBLM_L_X34Y114", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y115": { + "bits": {}, + "grid_x": 89, + "grid_y": 88, + "segment": "SEG_CLBLM_L_X34Y115", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y116": { + "bits": {}, + "grid_x": 89, + "grid_y": 87, + "segment": "SEG_CLBLM_L_X34Y116", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y117": { + "bits": {}, + "grid_x": 89, + "grid_y": 86, + "segment": "SEG_CLBLM_L_X34Y117", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y118": { + "bits": {}, + "grid_x": 89, + "grid_y": 85, + "segment": "SEG_CLBLM_L_X34Y118", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y119": { + "bits": {}, + "grid_x": 89, + "grid_y": 84, + "segment": "SEG_CLBLM_L_X34Y119", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y12": { + "bits": {}, + "grid_x": 89, + "grid_y": 195, + "segment": "SEG_CLBLM_L_X34Y12", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y120": { + "bits": {}, + "grid_x": 89, + "grid_y": 83, + "segment": "SEG_CLBLM_L_X34Y120", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y121": { + "bits": {}, + "grid_x": 89, + "grid_y": 82, + "segment": "SEG_CLBLM_L_X34Y121", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y122": { + "bits": {}, + "grid_x": 89, + "grid_y": 81, + "segment": "SEG_CLBLM_L_X34Y122", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y123": { + "bits": {}, + "grid_x": 89, + "grid_y": 80, + "segment": "SEG_CLBLM_L_X34Y123", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y124": { + "bits": {}, + "grid_x": 89, + "grid_y": 79, + "segment": "SEG_CLBLM_L_X34Y124", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y125": { + "bits": {}, + "grid_x": 89, + "grid_y": 77, + "segment": "SEG_CLBLM_L_X34Y125", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y126": { + "bits": {}, + "grid_x": 89, + "grid_y": 76, + "segment": "SEG_CLBLM_L_X34Y126", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y127": { + "bits": {}, + "grid_x": 89, + "grid_y": 75, + "segment": "SEG_CLBLM_L_X34Y127", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y128": { + "bits": {}, + "grid_x": 89, + "grid_y": 74, + "segment": "SEG_CLBLM_L_X34Y128", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y129": { + "bits": {}, + "grid_x": 89, + "grid_y": 73, + "segment": "SEG_CLBLM_L_X34Y129", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y13": { + "bits": {}, + "grid_x": 89, + "grid_y": 194, + "segment": "SEG_CLBLM_L_X34Y13", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y130": { + "bits": {}, + "grid_x": 89, + "grid_y": 72, + "segment": "SEG_CLBLM_L_X34Y130", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y131": { + "bits": {}, + "grid_x": 89, + "grid_y": 71, + "segment": "SEG_CLBLM_L_X34Y131", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y132": { + "bits": {}, + "grid_x": 89, + "grid_y": 70, + "segment": "SEG_CLBLM_L_X34Y132", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y133": { + "bits": {}, + "grid_x": 89, + "grid_y": 69, + "segment": "SEG_CLBLM_L_X34Y133", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y134": { + "bits": {}, + "grid_x": 89, + "grid_y": 68, + "segment": "SEG_CLBLM_L_X34Y134", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y135": { + "bits": {}, + "grid_x": 89, + "grid_y": 67, + "segment": "SEG_CLBLM_L_X34Y135", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y136": { + "bits": {}, + "grid_x": 89, + "grid_y": 66, + "segment": "SEG_CLBLM_L_X34Y136", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y137": { + "bits": {}, + "grid_x": 89, + "grid_y": 65, + "segment": "SEG_CLBLM_L_X34Y137", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y138": { + "bits": {}, + "grid_x": 89, + "grid_y": 64, + "segment": "SEG_CLBLM_L_X34Y138", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y139": { + "bits": {}, + "grid_x": 89, + "grid_y": 63, + "segment": "SEG_CLBLM_L_X34Y139", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y14": { + "bits": {}, + "grid_x": 89, + "grid_y": 193, + "segment": "SEG_CLBLM_L_X34Y14", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y140": { + "bits": {}, + "grid_x": 89, + "grid_y": 62, + "segment": "SEG_CLBLM_L_X34Y140", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y141": { + "bits": {}, + "grid_x": 89, + "grid_y": 61, + "segment": "SEG_CLBLM_L_X34Y141", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y142": { + "bits": {}, + "grid_x": 89, + "grid_y": 60, + "segment": "SEG_CLBLM_L_X34Y142", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y143": { + "bits": {}, + "grid_x": 89, + "grid_y": 59, + "segment": "SEG_CLBLM_L_X34Y143", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y144": { + "bits": {}, + "grid_x": 89, + "grid_y": 58, + "segment": "SEG_CLBLM_L_X34Y144", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y145": { + "bits": {}, + "grid_x": 89, + "grid_y": 57, + "segment": "SEG_CLBLM_L_X34Y145", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y146": { + "bits": {}, + "grid_x": 89, + "grid_y": 56, + "segment": "SEG_CLBLM_L_X34Y146", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y147": { + "bits": {}, + "grid_x": 89, + "grid_y": 55, + "segment": "SEG_CLBLM_L_X34Y147", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y148": { + "bits": {}, + "grid_x": 89, + "grid_y": 54, + "segment": "SEG_CLBLM_L_X34Y148", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y149": { + "bits": {}, + "grid_x": 89, + "grid_y": 53, + "segment": "SEG_CLBLM_L_X34Y149", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y15": { + "bits": {}, + "grid_x": 89, + "grid_y": 192, + "segment": "SEG_CLBLM_L_X34Y15", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y150": { + "bits": {}, + "grid_x": 89, + "grid_y": 51, + "segment": "SEG_CLBLM_L_X34Y150", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y151": { + "bits": {}, + "grid_x": 89, + "grid_y": 50, + "segment": "SEG_CLBLM_L_X34Y151", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y152": { + "bits": {}, + "grid_x": 89, + "grid_y": 49, + "segment": "SEG_CLBLM_L_X34Y152", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y153": { + "bits": {}, + "grid_x": 89, + "grid_y": 48, + "segment": "SEG_CLBLM_L_X34Y153", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y154": { + "bits": {}, + "grid_x": 89, + "grid_y": 47, + "segment": "SEG_CLBLM_L_X34Y154", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y155": { + "bits": {}, + "grid_x": 89, + "grid_y": 46, + "segment": "SEG_CLBLM_L_X34Y155", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y156": { + "bits": {}, + "grid_x": 89, + "grid_y": 45, + "segment": "SEG_CLBLM_L_X34Y156", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y157": { + "bits": {}, + "grid_x": 89, + "grid_y": 44, + "segment": "SEG_CLBLM_L_X34Y157", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y158": { + "bits": {}, + "grid_x": 89, + "grid_y": 43, + "segment": "SEG_CLBLM_L_X34Y158", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y159": { + "bits": {}, + "grid_x": 89, + "grid_y": 42, + "segment": "SEG_CLBLM_L_X34Y159", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y16": { + "bits": {}, + "grid_x": 89, + "grid_y": 191, + "segment": "SEG_CLBLM_L_X34Y16", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y160": { + "bits": {}, + "grid_x": 89, + "grid_y": 41, + "segment": "SEG_CLBLM_L_X34Y160", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y161": { + "bits": {}, + "grid_x": 89, + "grid_y": 40, + "segment": "SEG_CLBLM_L_X34Y161", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y162": { + "bits": {}, + "grid_x": 89, + "grid_y": 39, + "segment": "SEG_CLBLM_L_X34Y162", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y163": { + "bits": {}, + "grid_x": 89, + "grid_y": 38, + "segment": "SEG_CLBLM_L_X34Y163", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y164": { + "bits": {}, + "grid_x": 89, + "grid_y": 37, + "segment": "SEG_CLBLM_L_X34Y164", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y165": { + "bits": {}, + "grid_x": 89, + "grid_y": 36, + "segment": "SEG_CLBLM_L_X34Y165", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y166": { + "bits": {}, + "grid_x": 89, + "grid_y": 35, + "segment": "SEG_CLBLM_L_X34Y166", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y167": { + "bits": {}, + "grid_x": 89, + "grid_y": 34, + "segment": "SEG_CLBLM_L_X34Y167", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y168": { + "bits": {}, + "grid_x": 89, + "grid_y": 33, + "segment": "SEG_CLBLM_L_X34Y168", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y169": { + "bits": {}, + "grid_x": 89, + "grid_y": 32, + "segment": "SEG_CLBLM_L_X34Y169", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y17": { + "bits": {}, + "grid_x": 89, + "grid_y": 190, + "segment": "SEG_CLBLM_L_X34Y17", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y170": { + "bits": {}, + "grid_x": 89, + "grid_y": 31, + "segment": "SEG_CLBLM_L_X34Y170", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y171": { + "bits": {}, + "grid_x": 89, + "grid_y": 30, + "segment": "SEG_CLBLM_L_X34Y171", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y172": { + "bits": {}, + "grid_x": 89, + "grid_y": 29, + "segment": "SEG_CLBLM_L_X34Y172", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y173": { + "bits": {}, + "grid_x": 89, + "grid_y": 28, + "segment": "SEG_CLBLM_L_X34Y173", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y174": { + "bits": {}, + "grid_x": 89, + "grid_y": 27, + "segment": "SEG_CLBLM_L_X34Y174", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y175": { + "bits": {}, + "grid_x": 89, + "grid_y": 25, + "segment": "SEG_CLBLM_L_X34Y175", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y176": { + "bits": {}, + "grid_x": 89, + "grid_y": 24, + "segment": "SEG_CLBLM_L_X34Y176", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y177": { + "bits": {}, + "grid_x": 89, + "grid_y": 23, + "segment": "SEG_CLBLM_L_X34Y177", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y178": { + "bits": {}, + "grid_x": 89, + "grid_y": 22, + "segment": "SEG_CLBLM_L_X34Y178", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y179": { + "bits": {}, + "grid_x": 89, + "grid_y": 21, + "segment": "SEG_CLBLM_L_X34Y179", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y18": { + "bits": {}, + "grid_x": 89, + "grid_y": 189, + "segment": "SEG_CLBLM_L_X34Y18", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y180": { + "bits": {}, + "grid_x": 89, + "grid_y": 20, + "segment": "SEG_CLBLM_L_X34Y180", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y181": { + "bits": {}, + "grid_x": 89, + "grid_y": 19, + "segment": "SEG_CLBLM_L_X34Y181", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y182": { + "bits": {}, + "grid_x": 89, + "grid_y": 18, + "segment": "SEG_CLBLM_L_X34Y182", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y183": { + "bits": {}, + "grid_x": 89, + "grid_y": 17, + "segment": "SEG_CLBLM_L_X34Y183", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y184": { + "bits": {}, + "grid_x": 89, + "grid_y": 16, + "segment": "SEG_CLBLM_L_X34Y184", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y185": { + "bits": {}, + "grid_x": 89, + "grid_y": 15, + "segment": "SEG_CLBLM_L_X34Y185", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y186": { + "bits": {}, + "grid_x": 89, + "grid_y": 14, + "segment": "SEG_CLBLM_L_X34Y186", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y187": { + "bits": {}, + "grid_x": 89, + "grid_y": 13, + "segment": "SEG_CLBLM_L_X34Y187", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y188": { + "bits": {}, + "grid_x": 89, + "grid_y": 12, + "segment": "SEG_CLBLM_L_X34Y188", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y189": { + "bits": {}, + "grid_x": 89, + "grid_y": 11, + "segment": "SEG_CLBLM_L_X34Y189", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y19": { + "bits": {}, + "grid_x": 89, + "grid_y": 188, + "segment": "SEG_CLBLM_L_X34Y19", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y190": { + "bits": {}, + "grid_x": 89, + "grid_y": 10, + "segment": "SEG_CLBLM_L_X34Y190", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y191": { + "bits": {}, + "grid_x": 89, + "grid_y": 9, + "segment": "SEG_CLBLM_L_X34Y191", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y192": { + "bits": {}, + "grid_x": 89, + "grid_y": 8, + "segment": "SEG_CLBLM_L_X34Y192", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y193": { + "bits": {}, + "grid_x": 89, + "grid_y": 7, + "segment": "SEG_CLBLM_L_X34Y193", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y194": { + "bits": {}, + "grid_x": 89, + "grid_y": 6, + "segment": "SEG_CLBLM_L_X34Y194", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y195": { + "bits": {}, + "grid_x": 89, + "grid_y": 5, + "segment": "SEG_CLBLM_L_X34Y195", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y196": { + "bits": {}, + "grid_x": 89, + "grid_y": 4, + "segment": "SEG_CLBLM_L_X34Y196", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y197": { + "bits": {}, + "grid_x": 89, + "grid_y": 3, + "segment": "SEG_CLBLM_L_X34Y197", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y198": { + "bits": {}, + "grid_x": 89, + "grid_y": 2, + "segment": "SEG_CLBLM_L_X34Y198", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y199": { + "bits": {}, + "grid_x": 89, + "grid_y": 1, + "segment": "SEG_CLBLM_L_X34Y199", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y2": { + "bits": {}, + "grid_x": 89, + "grid_y": 205, + "segment": "SEG_CLBLM_L_X34Y2", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y20": { + "bits": {}, + "grid_x": 89, + "grid_y": 187, + "segment": "SEG_CLBLM_L_X34Y20", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y21": { + "bits": {}, + "grid_x": 89, + "grid_y": 186, + "segment": "SEG_CLBLM_L_X34Y21", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y22": { + "bits": {}, + "grid_x": 89, + "grid_y": 185, + "segment": "SEG_CLBLM_L_X34Y22", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y23": { + "bits": {}, + "grid_x": 89, + "grid_y": 184, + "segment": "SEG_CLBLM_L_X34Y23", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y24": { + "bits": {}, + "grid_x": 89, + "grid_y": 183, + "segment": "SEG_CLBLM_L_X34Y24", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y25": { + "bits": {}, + "grid_x": 89, + "grid_y": 181, + "segment": "SEG_CLBLM_L_X34Y25", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y26": { + "bits": {}, + "grid_x": 89, + "grid_y": 180, + "segment": "SEG_CLBLM_L_X34Y26", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y27": { + "bits": {}, + "grid_x": 89, + "grid_y": 179, + "segment": "SEG_CLBLM_L_X34Y27", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y28": { + "bits": {}, + "grid_x": 89, + "grid_y": 178, + "segment": "SEG_CLBLM_L_X34Y28", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y29": { + "bits": {}, + "grid_x": 89, + "grid_y": 177, + "segment": "SEG_CLBLM_L_X34Y29", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y3": { + "bits": {}, + "grid_x": 89, + "grid_y": 204, + "segment": "SEG_CLBLM_L_X34Y3", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y30": { + "bits": {}, + "grid_x": 89, + "grid_y": 176, + "segment": "SEG_CLBLM_L_X34Y30", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y31": { + "bits": {}, + "grid_x": 89, + "grid_y": 175, + "segment": "SEG_CLBLM_L_X34Y31", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y32": { + "bits": {}, + "grid_x": 89, + "grid_y": 174, + "segment": "SEG_CLBLM_L_X34Y32", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y33": { + "bits": {}, + "grid_x": 89, + "grid_y": 173, + "segment": "SEG_CLBLM_L_X34Y33", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y34": { + "bits": {}, + "grid_x": 89, + "grid_y": 172, + "segment": "SEG_CLBLM_L_X34Y34", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y35": { + "bits": {}, + "grid_x": 89, + "grid_y": 171, + "segment": "SEG_CLBLM_L_X34Y35", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y36": { + "bits": {}, + "grid_x": 89, + "grid_y": 170, + "segment": "SEG_CLBLM_L_X34Y36", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y37": { + "bits": {}, + "grid_x": 89, + "grid_y": 169, + "segment": "SEG_CLBLM_L_X34Y37", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y38": { + "bits": {}, + "grid_x": 89, + "grid_y": 168, + "segment": "SEG_CLBLM_L_X34Y38", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y39": { + "bits": {}, + "grid_x": 89, + "grid_y": 167, + "segment": "SEG_CLBLM_L_X34Y39", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y4": { + "bits": {}, + "grid_x": 89, + "grid_y": 203, + "segment": "SEG_CLBLM_L_X34Y4", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y40": { + "bits": {}, + "grid_x": 89, + "grid_y": 166, + "segment": "SEG_CLBLM_L_X34Y40", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y41": { + "bits": {}, + "grid_x": 89, + "grid_y": 165, + "segment": "SEG_CLBLM_L_X34Y41", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y42": { + "bits": {}, + "grid_x": 89, + "grid_y": 164, + "segment": "SEG_CLBLM_L_X34Y42", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y43": { + "bits": {}, + "grid_x": 89, + "grid_y": 163, + "segment": "SEG_CLBLM_L_X34Y43", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y44": { + "bits": {}, + "grid_x": 89, + "grid_y": 162, + "segment": "SEG_CLBLM_L_X34Y44", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y45": { + "bits": {}, + "grid_x": 89, + "grid_y": 161, + "segment": "SEG_CLBLM_L_X34Y45", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y46": { + "bits": {}, + "grid_x": 89, + "grid_y": 160, + "segment": "SEG_CLBLM_L_X34Y46", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y47": { + "bits": {}, + "grid_x": 89, + "grid_y": 159, + "segment": "SEG_CLBLM_L_X34Y47", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y48": { + "bits": {}, + "grid_x": 89, + "grid_y": 158, + "segment": "SEG_CLBLM_L_X34Y48", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y49": { + "bits": {}, + "grid_x": 89, + "grid_y": 157, + "segment": "SEG_CLBLM_L_X34Y49", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y5": { + "bits": {}, + "grid_x": 89, + "grid_y": 202, + "segment": "SEG_CLBLM_L_X34Y5", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y50": { + "bits": {}, + "grid_x": 89, + "grid_y": 155, + "segment": "SEG_CLBLM_L_X34Y50", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y51": { + "bits": {}, + "grid_x": 89, + "grid_y": 154, + "segment": "SEG_CLBLM_L_X34Y51", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y52": { + "bits": {}, + "grid_x": 89, + "grid_y": 153, + "segment": "SEG_CLBLM_L_X34Y52", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y53": { + "bits": {}, + "grid_x": 89, + "grid_y": 152, + "segment": "SEG_CLBLM_L_X34Y53", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y54": { + "bits": {}, + "grid_x": 89, + "grid_y": 151, + "segment": "SEG_CLBLM_L_X34Y54", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y55": { + "bits": {}, + "grid_x": 89, + "grid_y": 150, + "segment": "SEG_CLBLM_L_X34Y55", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y56": { + "bits": {}, + "grid_x": 89, + "grid_y": 149, + "segment": "SEG_CLBLM_L_X34Y56", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y57": { + "bits": {}, + "grid_x": 89, + "grid_y": 148, + "segment": "SEG_CLBLM_L_X34Y57", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y58": { + "bits": {}, + "grid_x": 89, + "grid_y": 147, + "segment": "SEG_CLBLM_L_X34Y58", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y59": { + "bits": {}, + "grid_x": 89, + "grid_y": 146, + "segment": "SEG_CLBLM_L_X34Y59", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y6": { + "bits": {}, + "grid_x": 89, + "grid_y": 201, + "segment": "SEG_CLBLM_L_X34Y6", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y60": { + "bits": {}, + "grid_x": 89, + "grid_y": 145, + "segment": "SEG_CLBLM_L_X34Y60", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y61": { + "bits": {}, + "grid_x": 89, + "grid_y": 144, + "segment": "SEG_CLBLM_L_X34Y61", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y62": { + "bits": {}, + "grid_x": 89, + "grid_y": 143, + "segment": "SEG_CLBLM_L_X34Y62", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y63": { + "bits": {}, + "grid_x": 89, + "grid_y": 142, + "segment": "SEG_CLBLM_L_X34Y63", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y64": { + "bits": {}, + "grid_x": 89, + "grid_y": 141, + "segment": "SEG_CLBLM_L_X34Y64", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y65": { + "bits": {}, + "grid_x": 89, + "grid_y": 140, + "segment": "SEG_CLBLM_L_X34Y65", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y66": { + "bits": {}, + "grid_x": 89, + "grid_y": 139, + "segment": "SEG_CLBLM_L_X34Y66", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y67": { + "bits": {}, + "grid_x": 89, + "grid_y": 138, + "segment": "SEG_CLBLM_L_X34Y67", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y68": { + "bits": {}, + "grid_x": 89, + "grid_y": 137, + "segment": "SEG_CLBLM_L_X34Y68", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y69": { + "bits": {}, + "grid_x": 89, + "grid_y": 136, + "segment": "SEG_CLBLM_L_X34Y69", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y7": { + "bits": {}, + "grid_x": 89, + "grid_y": 200, + "segment": "SEG_CLBLM_L_X34Y7", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y70": { + "bits": {}, + "grid_x": 89, + "grid_y": 135, + "segment": "SEG_CLBLM_L_X34Y70", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y71": { + "bits": {}, + "grid_x": 89, + "grid_y": 134, + "segment": "SEG_CLBLM_L_X34Y71", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y72": { + "bits": {}, + "grid_x": 89, + "grid_y": 133, + "segment": "SEG_CLBLM_L_X34Y72", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y73": { + "bits": {}, + "grid_x": 89, + "grid_y": 132, + "segment": "SEG_CLBLM_L_X34Y73", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y74": { + "bits": {}, + "grid_x": 89, + "grid_y": 131, + "segment": "SEG_CLBLM_L_X34Y74", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y75": { + "bits": {}, + "grid_x": 89, + "grid_y": 129, + "segment": "SEG_CLBLM_L_X34Y75", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y76": { + "bits": {}, + "grid_x": 89, + "grid_y": 128, + "segment": "SEG_CLBLM_L_X34Y76", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y77": { + "bits": {}, + "grid_x": 89, + "grid_y": 127, + "segment": "SEG_CLBLM_L_X34Y77", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y78": { + "bits": {}, + "grid_x": 89, + "grid_y": 126, + "segment": "SEG_CLBLM_L_X34Y78", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y79": { + "bits": {}, + "grid_x": 89, + "grid_y": 125, + "segment": "SEG_CLBLM_L_X34Y79", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y8": { + "bits": {}, + "grid_x": 89, + "grid_y": 199, + "segment": "SEG_CLBLM_L_X34Y8", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y80": { + "bits": {}, + "grid_x": 89, + "grid_y": 124, + "segment": "SEG_CLBLM_L_X34Y80", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y81": { + "bits": {}, + "grid_x": 89, + "grid_y": 123, + "segment": "SEG_CLBLM_L_X34Y81", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y82": { + "bits": {}, + "grid_x": 89, + "grid_y": 122, + "segment": "SEG_CLBLM_L_X34Y82", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y83": { + "bits": {}, + "grid_x": 89, + "grid_y": 121, + "segment": "SEG_CLBLM_L_X34Y83", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y84": { + "bits": {}, + "grid_x": 89, + "grid_y": 120, + "segment": "SEG_CLBLM_L_X34Y84", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y85": { + "bits": {}, + "grid_x": 89, + "grid_y": 119, + "segment": "SEG_CLBLM_L_X34Y85", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y86": { + "bits": {}, + "grid_x": 89, + "grid_y": 118, + "segment": "SEG_CLBLM_L_X34Y86", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y87": { + "bits": {}, + "grid_x": 89, + "grid_y": 117, + "segment": "SEG_CLBLM_L_X34Y87", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y88": { + "bits": {}, + "grid_x": 89, + "grid_y": 116, + "segment": "SEG_CLBLM_L_X34Y88", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y89": { + "bits": {}, + "grid_x": 89, + "grid_y": 115, + "segment": "SEG_CLBLM_L_X34Y89", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y9": { + "bits": {}, + "grid_x": 89, + "grid_y": 198, + "segment": "SEG_CLBLM_L_X34Y9", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y90": { + "bits": {}, + "grid_x": 89, + "grid_y": 114, + "segment": "SEG_CLBLM_L_X34Y90", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y91": { + "bits": {}, + "grid_x": 89, + "grid_y": 113, + "segment": "SEG_CLBLM_L_X34Y91", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y92": { + "bits": {}, + "grid_x": 89, + "grid_y": 112, + "segment": "SEG_CLBLM_L_X34Y92", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y93": { + "bits": {}, + "grid_x": 89, + "grid_y": 111, + "segment": "SEG_CLBLM_L_X34Y93", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y94": { + "bits": {}, + "grid_x": 89, + "grid_y": 110, + "segment": "SEG_CLBLM_L_X34Y94", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y95": { + "bits": {}, + "grid_x": 89, + "grid_y": 109, + "segment": "SEG_CLBLM_L_X34Y95", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y96": { + "bits": {}, + "grid_x": 89, + "grid_y": 108, + "segment": "SEG_CLBLM_L_X34Y96", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y97": { + "bits": {}, + "grid_x": 89, + "grid_y": 107, + "segment": "SEG_CLBLM_L_X34Y97", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y98": { + "bits": {}, + "grid_x": 89, + "grid_y": 106, + "segment": "SEG_CLBLM_L_X34Y98", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X34Y99": { + "bits": {}, + "grid_x": 89, + "grid_y": 105, + "segment": "SEG_CLBLM_L_X34Y99", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X37Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y0": { + "bits": {}, + "grid_x": 94, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X36Y0", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y1": { + "bits": {}, + "grid_x": 94, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X36Y1", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y10": { + "bits": {}, + "grid_x": 94, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X36Y10", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y100": { + "bits": {}, + "grid_x": 94, + "grid_y": 103, + "segment": "SEG_CLBLL_L_X36Y100", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y101": { + "bits": {}, + "grid_x": 94, + "grid_y": 102, + "segment": "SEG_CLBLL_L_X36Y101", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y102": { + "bits": {}, + "grid_x": 94, + "grid_y": 101, + "segment": "SEG_CLBLL_L_X36Y102", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y103": { + "bits": {}, + "grid_x": 94, + "grid_y": 100, + "segment": "SEG_CLBLL_L_X36Y103", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y104": { + "bits": {}, + "grid_x": 94, + "grid_y": 99, + "segment": "SEG_CLBLL_L_X36Y104", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y105": { + "bits": {}, + "grid_x": 94, + "grid_y": 98, + "segment": "SEG_CLBLL_L_X36Y105", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y106": { + "bits": {}, + "grid_x": 94, + "grid_y": 97, + "segment": "SEG_CLBLL_L_X36Y106", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y107": { + "bits": {}, + "grid_x": 94, + "grid_y": 96, + "segment": "SEG_CLBLL_L_X36Y107", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y108": { + "bits": {}, + "grid_x": 94, + "grid_y": 95, + "segment": "SEG_CLBLL_L_X36Y108", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y109": { + "bits": {}, + "grid_x": 94, + "grid_y": 94, + "segment": "SEG_CLBLL_L_X36Y109", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y11": { + "bits": {}, + "grid_x": 94, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X36Y11", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y110": { + "bits": {}, + "grid_x": 94, + "grid_y": 93, + "segment": "SEG_CLBLL_L_X36Y110", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y111": { + "bits": {}, + "grid_x": 94, + "grid_y": 92, + "segment": "SEG_CLBLL_L_X36Y111", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y112": { + "bits": {}, + "grid_x": 94, + "grid_y": 91, + "segment": "SEG_CLBLL_L_X36Y112", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y113": { + "bits": {}, + "grid_x": 94, + "grid_y": 90, + "segment": "SEG_CLBLL_L_X36Y113", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y114": { + "bits": {}, + "grid_x": 94, + "grid_y": 89, + "segment": "SEG_CLBLL_L_X36Y114", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y115": { + "bits": {}, + "grid_x": 94, + "grid_y": 88, + "segment": "SEG_CLBLL_L_X36Y115", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y116": { + "bits": {}, + "grid_x": 94, + "grid_y": 87, + "segment": "SEG_CLBLL_L_X36Y116", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y117": { + "bits": {}, + "grid_x": 94, + "grid_y": 86, + "segment": "SEG_CLBLL_L_X36Y117", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y118": { + "bits": {}, + "grid_x": 94, + "grid_y": 85, + "segment": "SEG_CLBLL_L_X36Y118", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y119": { + "bits": {}, + "grid_x": 94, + "grid_y": 84, + "segment": "SEG_CLBLL_L_X36Y119", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y12": { + "bits": {}, + "grid_x": 94, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X36Y12", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y120": { + "bits": {}, + "grid_x": 94, + "grid_y": 83, + "segment": "SEG_CLBLL_L_X36Y120", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y121": { + "bits": {}, + "grid_x": 94, + "grid_y": 82, + "segment": "SEG_CLBLL_L_X36Y121", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y122": { + "bits": {}, + "grid_x": 94, + "grid_y": 81, + "segment": "SEG_CLBLL_L_X36Y122", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y123": { + "bits": {}, + "grid_x": 94, + "grid_y": 80, + "segment": "SEG_CLBLL_L_X36Y123", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y124": { + "bits": {}, + "grid_x": 94, + "grid_y": 79, + "segment": "SEG_CLBLL_L_X36Y124", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y125": { + "bits": {}, + "grid_x": 94, + "grid_y": 77, + "segment": "SEG_CLBLL_L_X36Y125", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y126": { + "bits": {}, + "grid_x": 94, + "grid_y": 76, + "segment": "SEG_CLBLL_L_X36Y126", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y127": { + "bits": {}, + "grid_x": 94, + "grid_y": 75, + "segment": "SEG_CLBLL_L_X36Y127", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y128": { + "bits": {}, + "grid_x": 94, + "grid_y": 74, + "segment": "SEG_CLBLL_L_X36Y128", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y129": { + "bits": {}, + "grid_x": 94, + "grid_y": 73, + "segment": "SEG_CLBLL_L_X36Y129", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y13": { + "bits": {}, + "grid_x": 94, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X36Y13", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y130": { + "bits": {}, + "grid_x": 94, + "grid_y": 72, + "segment": "SEG_CLBLL_L_X36Y130", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y131": { + "bits": {}, + "grid_x": 94, + "grid_y": 71, + "segment": "SEG_CLBLL_L_X36Y131", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y132": { + "bits": {}, + "grid_x": 94, + "grid_y": 70, + "segment": "SEG_CLBLL_L_X36Y132", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y133": { + "bits": {}, + "grid_x": 94, + "grid_y": 69, + "segment": "SEG_CLBLL_L_X36Y133", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y134": { + "bits": {}, + "grid_x": 94, + "grid_y": 68, + "segment": "SEG_CLBLL_L_X36Y134", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y135": { + "bits": {}, + "grid_x": 94, + "grid_y": 67, + "segment": "SEG_CLBLL_L_X36Y135", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y136": { + "bits": {}, + "grid_x": 94, + "grid_y": 66, + "segment": "SEG_CLBLL_L_X36Y136", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y137": { + "bits": {}, + "grid_x": 94, + "grid_y": 65, + "segment": "SEG_CLBLL_L_X36Y137", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y138": { + "bits": {}, + "grid_x": 94, + "grid_y": 64, + "segment": "SEG_CLBLL_L_X36Y138", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y139": { + "bits": {}, + "grid_x": 94, + "grid_y": 63, + "segment": "SEG_CLBLL_L_X36Y139", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y14": { + "bits": {}, + "grid_x": 94, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X36Y14", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y140": { + "bits": {}, + "grid_x": 94, + "grid_y": 62, + "segment": "SEG_CLBLL_L_X36Y140", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y141": { + "bits": {}, + "grid_x": 94, + "grid_y": 61, + "segment": "SEG_CLBLL_L_X36Y141", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y142": { + "bits": {}, + "grid_x": 94, + "grid_y": 60, + "segment": "SEG_CLBLL_L_X36Y142", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y143": { + "bits": {}, + "grid_x": 94, + "grid_y": 59, + "segment": "SEG_CLBLL_L_X36Y143", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y144": { + "bits": {}, + "grid_x": 94, + "grid_y": 58, + "segment": "SEG_CLBLL_L_X36Y144", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y145": { + "bits": {}, + "grid_x": 94, + "grid_y": 57, + "segment": "SEG_CLBLL_L_X36Y145", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y146": { + "bits": {}, + "grid_x": 94, + "grid_y": 56, + "segment": "SEG_CLBLL_L_X36Y146", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y147": { + "bits": {}, + "grid_x": 94, + "grid_y": 55, + "segment": "SEG_CLBLL_L_X36Y147", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y148": { + "bits": {}, + "grid_x": 94, + "grid_y": 54, + "segment": "SEG_CLBLL_L_X36Y148", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y149": { + "bits": {}, + "grid_x": 94, + "grid_y": 53, + "segment": "SEG_CLBLL_L_X36Y149", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y15": { + "bits": {}, + "grid_x": 94, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X36Y15", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y150": { + "bits": {}, + "grid_x": 94, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X36Y150", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y151": { + "bits": {}, + "grid_x": 94, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X36Y151", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y152": { + "bits": {}, + "grid_x": 94, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X36Y152", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y153": { + "bits": {}, + "grid_x": 94, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X36Y153", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y154": { + "bits": {}, + "grid_x": 94, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X36Y154", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y155": { + "bits": {}, + "grid_x": 94, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X36Y155", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y156": { + "bits": {}, + "grid_x": 94, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X36Y156", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y157": { + "bits": {}, + "grid_x": 94, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X36Y157", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y158": { + "bits": {}, + "grid_x": 94, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X36Y158", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y159": { + "bits": {}, + "grid_x": 94, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X36Y159", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y16": { + "bits": {}, + "grid_x": 94, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X36Y16", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y160": { + "bits": {}, + "grid_x": 94, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X36Y160", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y161": { + "bits": {}, + "grid_x": 94, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X36Y161", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y162": { + "bits": {}, + "grid_x": 94, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X36Y162", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y163": { + "bits": {}, + "grid_x": 94, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X36Y163", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y164": { + "bits": {}, + "grid_x": 94, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X36Y164", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y165": { + "bits": {}, + "grid_x": 94, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X36Y165", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y166": { + "bits": {}, + "grid_x": 94, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X36Y166", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y167": { + "bits": {}, + "grid_x": 94, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X36Y167", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y168": { + "bits": {}, + "grid_x": 94, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X36Y168", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y169": { + "bits": {}, + "grid_x": 94, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X36Y169", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y17": { + "bits": {}, + "grid_x": 94, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X36Y17", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y170": { + "bits": {}, + "grid_x": 94, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X36Y170", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y171": { + "bits": {}, + "grid_x": 94, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X36Y171", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y172": { + "bits": {}, + "grid_x": 94, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X36Y172", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y173": { + "bits": {}, + "grid_x": 94, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X36Y173", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y174": { + "bits": {}, + "grid_x": 94, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X36Y174", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y175": { + "bits": {}, + "grid_x": 94, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X36Y175", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y176": { + "bits": {}, + "grid_x": 94, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X36Y176", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y177": { + "bits": {}, + "grid_x": 94, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X36Y177", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y178": { + "bits": {}, + "grid_x": 94, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X36Y178", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y179": { + "bits": {}, + "grid_x": 94, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X36Y179", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y18": { + "bits": {}, + "grid_x": 94, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X36Y18", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y180": { + "bits": {}, + "grid_x": 94, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X36Y180", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y181": { + "bits": {}, + "grid_x": 94, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X36Y181", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y182": { + "bits": {}, + "grid_x": 94, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X36Y182", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y183": { + "bits": {}, + "grid_x": 94, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X36Y183", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y184": { + "bits": {}, + "grid_x": 94, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X36Y184", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y185": { + "bits": {}, + "grid_x": 94, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X36Y185", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y186": { + "bits": {}, + "grid_x": 94, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X36Y186", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y187": { + "bits": {}, + "grid_x": 94, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X36Y187", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y188": { + "bits": {}, + "grid_x": 94, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X36Y188", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y189": { + "bits": {}, + "grid_x": 94, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X36Y189", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y19": { + "bits": {}, + "grid_x": 94, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X36Y19", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y190": { + "bits": {}, + "grid_x": 94, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X36Y190", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y191": { + "bits": {}, + "grid_x": 94, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X36Y191", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y192": { + "bits": {}, + "grid_x": 94, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X36Y192", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y193": { + "bits": {}, + "grid_x": 94, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X36Y193", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y194": { + "bits": {}, + "grid_x": 94, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X36Y194", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y195": { + "bits": {}, + "grid_x": 94, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X36Y195", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y196": { + "bits": {}, + "grid_x": 94, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X36Y196", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y197": { + "bits": {}, + "grid_x": 94, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X36Y197", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y198": { + "bits": {}, + "grid_x": 94, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X36Y198", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y199": { + "bits": {}, + "grid_x": 94, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X36Y199", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y2": { + "bits": {}, + "grid_x": 94, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X36Y2", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y20": { + "bits": {}, + "grid_x": 94, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X36Y20", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y21": { + "bits": {}, + "grid_x": 94, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X36Y21", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y22": { + "bits": {}, + "grid_x": 94, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X36Y22", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y23": { + "bits": {}, + "grid_x": 94, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X36Y23", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y24": { + "bits": {}, + "grid_x": 94, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X36Y24", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y25": { + "bits": {}, + "grid_x": 94, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X36Y25", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y26": { + "bits": {}, + "grid_x": 94, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X36Y26", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y27": { + "bits": {}, + "grid_x": 94, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X36Y27", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y28": { + "bits": {}, + "grid_x": 94, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X36Y28", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y29": { + "bits": {}, + "grid_x": 94, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X36Y29", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y3": { + "bits": {}, + "grid_x": 94, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X36Y3", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y30": { + "bits": {}, + "grid_x": 94, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X36Y30", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y31": { + "bits": {}, + "grid_x": 94, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X36Y31", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y32": { + "bits": {}, + "grid_x": 94, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X36Y32", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y33": { + "bits": {}, + "grid_x": 94, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X36Y33", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y34": { + "bits": {}, + "grid_x": 94, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X36Y34", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y35": { + "bits": {}, + "grid_x": 94, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X36Y35", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y36": { + "bits": {}, + "grid_x": 94, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X36Y36", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y37": { + "bits": {}, + "grid_x": 94, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X36Y37", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y38": { + "bits": {}, + "grid_x": 94, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X36Y38", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y39": { + "bits": {}, + "grid_x": 94, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X36Y39", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y4": { + "bits": {}, + "grid_x": 94, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X36Y4", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y40": { + "bits": {}, + "grid_x": 94, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X36Y40", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y41": { + "bits": {}, + "grid_x": 94, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X36Y41", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y42": { + "bits": {}, + "grid_x": 94, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X36Y42", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y43": { + "bits": {}, + "grid_x": 94, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X36Y43", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y44": { + "bits": {}, + "grid_x": 94, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X36Y44", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y45": { + "bits": {}, + "grid_x": 94, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X36Y45", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y46": { + "bits": {}, + "grid_x": 94, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X36Y46", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y47": { + "bits": {}, + "grid_x": 94, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X36Y47", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y48": { + "bits": {}, + "grid_x": 94, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X36Y48", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y49": { + "bits": {}, + "grid_x": 94, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X36Y49", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y5": { + "bits": {}, + "grid_x": 94, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X36Y5", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y50": { + "bits": {}, + "grid_x": 94, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X36Y50", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y51": { + "bits": {}, + "grid_x": 94, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X36Y51", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y52": { + "bits": {}, + "grid_x": 94, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X36Y52", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y53": { + "bits": {}, + "grid_x": 94, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X36Y53", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y54": { + "bits": {}, + "grid_x": 94, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X36Y54", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y55": { + "bits": {}, + "grid_x": 94, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X36Y55", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y56": { + "bits": {}, + "grid_x": 94, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X36Y56", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y57": { + "bits": {}, + "grid_x": 94, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X36Y57", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y58": { + "bits": {}, + "grid_x": 94, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X36Y58", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y59": { + "bits": {}, + "grid_x": 94, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X36Y59", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y6": { + "bits": {}, + "grid_x": 94, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X36Y6", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y60": { + "bits": {}, + "grid_x": 94, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X36Y60", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y61": { + "bits": {}, + "grid_x": 94, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X36Y61", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y62": { + "bits": {}, + "grid_x": 94, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X36Y62", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y63": { + "bits": {}, + "grid_x": 94, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X36Y63", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y64": { + "bits": {}, + "grid_x": 94, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X36Y64", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y65": { + "bits": {}, + "grid_x": 94, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X36Y65", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y66": { + "bits": {}, + "grid_x": 94, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X36Y66", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y67": { + "bits": {}, + "grid_x": 94, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X36Y67", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y68": { + "bits": {}, + "grid_x": 94, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X36Y68", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y69": { + "bits": {}, + "grid_x": 94, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X36Y69", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y7": { + "bits": {}, + "grid_x": 94, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X36Y7", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y70": { + "bits": {}, + "grid_x": 94, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X36Y70", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y71": { + "bits": {}, + "grid_x": 94, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X36Y71", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y72": { + "bits": {}, + "grid_x": 94, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X36Y72", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y73": { + "bits": {}, + "grid_x": 94, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X36Y73", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y74": { + "bits": {}, + "grid_x": 94, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X36Y74", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y75": { + "bits": {}, + "grid_x": 94, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X36Y75", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y76": { + "bits": {}, + "grid_x": 94, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X36Y76", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y77": { + "bits": {}, + "grid_x": 94, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X36Y77", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y78": { + "bits": {}, + "grid_x": 94, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X36Y78", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y79": { + "bits": {}, + "grid_x": 94, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X36Y79", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y8": { + "bits": {}, + "grid_x": 94, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X36Y8", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y80": { + "bits": {}, + "grid_x": 94, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X36Y80", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y81": { + "bits": {}, + "grid_x": 94, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X36Y81", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y82": { + "bits": {}, + "grid_x": 94, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X36Y82", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y83": { + "bits": {}, + "grid_x": 94, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X36Y83", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y84": { + "bits": {}, + "grid_x": 94, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X36Y84", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y85": { + "bits": {}, + "grid_x": 94, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X36Y85", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y86": { + "bits": {}, + "grid_x": 94, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X36Y86", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y87": { + "bits": {}, + "grid_x": 94, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X36Y87", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y88": { + "bits": {}, + "grid_x": 94, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X36Y88", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y89": { + "bits": {}, + "grid_x": 94, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X36Y89", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y9": { + "bits": {}, + "grid_x": 94, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X36Y9", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y90": { + "bits": {}, + "grid_x": 94, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X36Y90", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y91": { + "bits": {}, + "grid_x": 94, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X36Y91", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y92": { + "bits": {}, + "grid_x": 94, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X36Y92", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y93": { + "bits": {}, + "grid_x": 94, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X36Y93", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y94": { + "bits": {}, + "grid_x": 94, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X36Y94", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y95": { + "bits": {}, + "grid_x": 94, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X36Y95", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y96": { + "bits": {}, + "grid_x": 94, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X36Y96", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y97": { + "bits": {}, + "grid_x": 94, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X36Y97", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y98": { + "bits": {}, + "grid_x": 94, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X36Y98", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X36Y99": { + "bits": {}, + "grid_x": 94, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X36Y99", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X39Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y0": { + "bits": {}, + "grid_x": 100, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X38Y0", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y1": { + "bits": {}, + "grid_x": 100, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X38Y1", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y10": { + "bits": {}, + "grid_x": 100, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X38Y10", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y11": { + "bits": {}, + "grid_x": 100, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X38Y11", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y12": { + "bits": {}, + "grid_x": 100, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X38Y12", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y13": { + "bits": {}, + "grid_x": 100, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X38Y13", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y14": { + "bits": {}, + "grid_x": 100, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X38Y14", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y15": { + "bits": {}, + "grid_x": 100, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X38Y15", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y16": { + "bits": {}, + "grid_x": 100, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X38Y16", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y17": { + "bits": {}, + "grid_x": 100, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X38Y17", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y18": { + "bits": {}, + "grid_x": 100, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X38Y18", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y19": { + "bits": {}, + "grid_x": 100, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X38Y19", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y2": { + "bits": {}, + "grid_x": 100, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X38Y2", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y20": { + "bits": {}, + "grid_x": 100, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X38Y20", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y21": { + "bits": {}, + "grid_x": 100, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X38Y21", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y22": { + "bits": {}, + "grid_x": 100, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X38Y22", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y23": { + "bits": {}, + "grid_x": 100, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X38Y23", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y24": { + "bits": {}, + "grid_x": 100, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X38Y24", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y25": { + "bits": {}, + "grid_x": 100, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X38Y25", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y26": { + "bits": {}, + "grid_x": 100, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X38Y26", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y27": { + "bits": {}, + "grid_x": 100, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X38Y27", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y28": { + "bits": {}, + "grid_x": 100, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X38Y28", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y29": { + "bits": {}, + "grid_x": 100, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X38Y29", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y3": { + "bits": {}, + "grid_x": 100, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X38Y3", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y30": { + "bits": {}, + "grid_x": 100, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X38Y30", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y31": { + "bits": {}, + "grid_x": 100, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X38Y31", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y32": { + "bits": {}, + "grid_x": 100, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X38Y32", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y33": { + "bits": {}, + "grid_x": 100, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X38Y33", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y34": { + "bits": {}, + "grid_x": 100, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X38Y34", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y35": { + "bits": {}, + "grid_x": 100, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X38Y35", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y36": { + "bits": {}, + "grid_x": 100, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X38Y36", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y37": { + "bits": {}, + "grid_x": 100, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X38Y37", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y38": { + "bits": {}, + "grid_x": 100, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X38Y38", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y39": { + "bits": {}, + "grid_x": 100, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X38Y39", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y4": { + "bits": {}, + "grid_x": 100, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X38Y4", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y40": { + "bits": {}, + "grid_x": 100, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X38Y40", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y41": { + "bits": {}, + "grid_x": 100, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X38Y41", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y42": { + "bits": {}, + "grid_x": 100, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X38Y42", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y43": { + "bits": {}, + "grid_x": 100, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X38Y43", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y44": { + "bits": {}, + "grid_x": 100, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X38Y44", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y45": { + "bits": {}, + "grid_x": 100, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X38Y45", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y46": { + "bits": {}, + "grid_x": 100, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X38Y46", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y47": { + "bits": {}, + "grid_x": 100, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X38Y47", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y48": { + "bits": {}, + "grid_x": 100, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X38Y48", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y49": { + "bits": {}, + "grid_x": 100, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X38Y49", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y5": { + "bits": {}, + "grid_x": 100, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X38Y5", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y50": { + "bits": {}, + "grid_x": 100, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X38Y50", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y51": { + "bits": {}, + "grid_x": 100, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X38Y51", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y52": { + "bits": {}, + "grid_x": 100, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X38Y52", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y53": { + "bits": {}, + "grid_x": 100, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X38Y53", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y54": { + "bits": {}, + "grid_x": 100, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X38Y54", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y55": { + "bits": {}, + "grid_x": 100, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X38Y55", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y56": { + "bits": {}, + "grid_x": 100, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X38Y56", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y57": { + "bits": {}, + "grid_x": 100, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X38Y57", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y58": { + "bits": {}, + "grid_x": 100, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X38Y58", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y59": { + "bits": {}, + "grid_x": 100, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X38Y59", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y6": { + "bits": {}, + "grid_x": 100, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X38Y6", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y60": { + "bits": {}, + "grid_x": 100, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X38Y60", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y61": { + "bits": {}, + "grid_x": 100, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X38Y61", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y62": { + "bits": {}, + "grid_x": 100, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X38Y62", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y63": { + "bits": {}, + "grid_x": 100, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X38Y63", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y64": { + "bits": {}, + "grid_x": 100, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X38Y64", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y65": { + "bits": {}, + "grid_x": 100, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X38Y65", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y66": { + "bits": {}, + "grid_x": 100, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X38Y66", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y67": { + "bits": {}, + "grid_x": 100, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X38Y67", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y68": { + "bits": {}, + "grid_x": 100, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X38Y68", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y69": { + "bits": {}, + "grid_x": 100, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X38Y69", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y7": { + "bits": {}, + "grid_x": 100, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X38Y7", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y70": { + "bits": {}, + "grid_x": 100, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X38Y70", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y71": { + "bits": {}, + "grid_x": 100, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X38Y71", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y72": { + "bits": {}, + "grid_x": 100, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X38Y72", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y73": { + "bits": {}, + "grid_x": 100, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X38Y73", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y74": { + "bits": {}, + "grid_x": 100, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X38Y74", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y75": { + "bits": {}, + "grid_x": 100, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X38Y75", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y76": { + "bits": {}, + "grid_x": 100, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X38Y76", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y77": { + "bits": {}, + "grid_x": 100, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X38Y77", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y78": { + "bits": {}, + "grid_x": 100, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X38Y78", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y79": { + "bits": {}, + "grid_x": 100, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X38Y79", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y8": { + "bits": {}, + "grid_x": 100, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X38Y8", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y80": { + "bits": {}, + "grid_x": 100, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X38Y80", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y81": { + "bits": {}, + "grid_x": 100, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X38Y81", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y82": { + "bits": {}, + "grid_x": 100, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X38Y82", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y83": { + "bits": {}, + "grid_x": 100, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X38Y83", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y84": { + "bits": {}, + "grid_x": 100, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X38Y84", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y85": { + "bits": {}, + "grid_x": 100, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X38Y85", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y86": { + "bits": {}, + "grid_x": 100, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X38Y86", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y87": { + "bits": {}, + "grid_x": 100, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X38Y87", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y88": { + "bits": {}, + "grid_x": 100, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X38Y88", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y89": { + "bits": {}, + "grid_x": 100, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X38Y89", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y9": { + "bits": {}, + "grid_x": 100, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X38Y9", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y90": { + "bits": {}, + "grid_x": 100, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X38Y90", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y91": { + "bits": {}, + "grid_x": 100, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X38Y91", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y92": { + "bits": {}, + "grid_x": 100, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X38Y92", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y93": { + "bits": {}, + "grid_x": 100, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X38Y93", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y94": { + "bits": {}, + "grid_x": 100, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X38Y94", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y95": { + "bits": {}, + "grid_x": 100, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X38Y95", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y96": { + "bits": {}, + "grid_x": 100, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X38Y96", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y97": { + "bits": {}, + "grid_x": 100, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X38Y97", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y98": { + "bits": {}, + "grid_x": 100, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X38Y98", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X38Y99": { + "bits": {}, + "grid_x": 100, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X38Y99", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X41Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y0": { + "bits": {}, + "grid_x": 104, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X40Y0", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y1": { + "bits": {}, + "grid_x": 104, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X40Y1", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y10": { + "bits": {}, + "grid_x": 104, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X40Y10", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y11": { + "bits": {}, + "grid_x": 104, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X40Y11", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y12": { + "bits": {}, + "grid_x": 104, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X40Y12", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y13": { + "bits": {}, + "grid_x": 104, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X40Y13", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y14": { + "bits": {}, + "grid_x": 104, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X40Y14", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y15": { + "bits": {}, + "grid_x": 104, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X40Y15", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y16": { + "bits": {}, + "grid_x": 104, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X40Y16", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y17": { + "bits": {}, + "grid_x": 104, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X40Y17", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y18": { + "bits": {}, + "grid_x": 104, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X40Y18", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y19": { + "bits": {}, + "grid_x": 104, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X40Y19", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y2": { + "bits": {}, + "grid_x": 104, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X40Y2", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y20": { + "bits": {}, + "grid_x": 104, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X40Y20", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y21": { + "bits": {}, + "grid_x": 104, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X40Y21", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y22": { + "bits": {}, + "grid_x": 104, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X40Y22", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y23": { + "bits": {}, + "grid_x": 104, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X40Y23", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y24": { + "bits": {}, + "grid_x": 104, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X40Y24", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y25": { + "bits": {}, + "grid_x": 104, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X40Y25", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y26": { + "bits": {}, + "grid_x": 104, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X40Y26", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y27": { + "bits": {}, + "grid_x": 104, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X40Y27", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y28": { + "bits": {}, + "grid_x": 104, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X40Y28", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y29": { + "bits": {}, + "grid_x": 104, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X40Y29", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y3": { + "bits": {}, + "grid_x": 104, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X40Y3", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y30": { + "bits": {}, + "grid_x": 104, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X40Y30", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y31": { + "bits": {}, + "grid_x": 104, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X40Y31", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y32": { + "bits": {}, + "grid_x": 104, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X40Y32", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y33": { + "bits": {}, + "grid_x": 104, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X40Y33", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y34": { + "bits": {}, + "grid_x": 104, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X40Y34", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y35": { + "bits": {}, + "grid_x": 104, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X40Y35", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y36": { + "bits": {}, + "grid_x": 104, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X40Y36", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y37": { + "bits": {}, + "grid_x": 104, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X40Y37", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y38": { + "bits": {}, + "grid_x": 104, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X40Y38", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y39": { + "bits": {}, + "grid_x": 104, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X40Y39", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y4": { + "bits": {}, + "grid_x": 104, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X40Y4", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y40": { + "bits": {}, + "grid_x": 104, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X40Y40", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y41": { + "bits": {}, + "grid_x": 104, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X40Y41", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y42": { + "bits": {}, + "grid_x": 104, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X40Y42", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y43": { + "bits": {}, + "grid_x": 104, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X40Y43", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y44": { + "bits": {}, + "grid_x": 104, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X40Y44", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y45": { + "bits": {}, + "grid_x": 104, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X40Y45", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y46": { + "bits": {}, + "grid_x": 104, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X40Y46", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y47": { + "bits": {}, + "grid_x": 104, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X40Y47", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y48": { + "bits": {}, + "grid_x": 104, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X40Y48", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y49": { + "bits": {}, + "grid_x": 104, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X40Y49", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y5": { + "bits": {}, + "grid_x": 104, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X40Y5", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y50": { + "bits": {}, + "grid_x": 104, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X40Y50", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y51": { + "bits": {}, + "grid_x": 104, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X40Y51", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y52": { + "bits": {}, + "grid_x": 104, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X40Y52", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y53": { + "bits": {}, + "grid_x": 104, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X40Y53", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y54": { + "bits": {}, + "grid_x": 104, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X40Y54", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y55": { + "bits": {}, + "grid_x": 104, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X40Y55", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y56": { + "bits": {}, + "grid_x": 104, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X40Y56", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y57": { + "bits": {}, + "grid_x": 104, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X40Y57", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y58": { + "bits": {}, + "grid_x": 104, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X40Y58", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y59": { + "bits": {}, + "grid_x": 104, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X40Y59", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y6": { + "bits": {}, + "grid_x": 104, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X40Y6", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y60": { + "bits": {}, + "grid_x": 104, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X40Y60", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y61": { + "bits": {}, + "grid_x": 104, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X40Y61", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y62": { + "bits": {}, + "grid_x": 104, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X40Y62", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y63": { + "bits": {}, + "grid_x": 104, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X40Y63", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y64": { + "bits": {}, + "grid_x": 104, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X40Y64", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y65": { + "bits": {}, + "grid_x": 104, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X40Y65", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y66": { + "bits": {}, + "grid_x": 104, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X40Y66", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y67": { + "bits": {}, + "grid_x": 104, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X40Y67", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y68": { + "bits": {}, + "grid_x": 104, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X40Y68", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y69": { + "bits": {}, + "grid_x": 104, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X40Y69", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y7": { + "bits": {}, + "grid_x": 104, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X40Y7", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y70": { + "bits": {}, + "grid_x": 104, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X40Y70", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y71": { + "bits": {}, + "grid_x": 104, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X40Y71", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y72": { + "bits": {}, + "grid_x": 104, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X40Y72", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y73": { + "bits": {}, + "grid_x": 104, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X40Y73", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y74": { + "bits": {}, + "grid_x": 104, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X40Y74", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y75": { + "bits": {}, + "grid_x": 104, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X40Y75", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y76": { + "bits": {}, + "grid_x": 104, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X40Y76", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y77": { + "bits": {}, + "grid_x": 104, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X40Y77", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y78": { + "bits": {}, + "grid_x": 104, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X40Y78", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y79": { + "bits": {}, + "grid_x": 104, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X40Y79", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y8": { + "bits": {}, + "grid_x": 104, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X40Y8", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y80": { + "bits": {}, + "grid_x": 104, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X40Y80", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y81": { + "bits": {}, + "grid_x": 104, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X40Y81", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y82": { + "bits": {}, + "grid_x": 104, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X40Y82", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y83": { + "bits": {}, + "grid_x": 104, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X40Y83", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y84": { + "bits": {}, + "grid_x": 104, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X40Y84", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y85": { + "bits": {}, + "grid_x": 104, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X40Y85", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y86": { + "bits": {}, + "grid_x": 104, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X40Y86", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y87": { + "bits": {}, + "grid_x": 104, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X40Y87", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y88": { + "bits": {}, + "grid_x": 104, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X40Y88", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y89": { + "bits": {}, + "grid_x": 104, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X40Y89", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y9": { + "bits": {}, + "grid_x": 104, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X40Y9", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y90": { + "bits": {}, + "grid_x": 104, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X40Y90", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y91": { + "bits": {}, + "grid_x": 104, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X40Y91", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y92": { + "bits": {}, + "grid_x": 104, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X40Y92", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y93": { + "bits": {}, + "grid_x": 104, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X40Y93", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y94": { + "bits": {}, + "grid_x": 104, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X40Y94", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y95": { + "bits": {}, + "grid_x": 104, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X40Y95", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y96": { + "bits": {}, + "grid_x": 104, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X40Y96", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y97": { + "bits": {}, + "grid_x": 104, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X40Y97", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y98": { + "bits": {}, + "grid_x": 104, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X40Y98", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X40Y99": { + "bits": {}, + "grid_x": 104, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X40Y99", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X43Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y0": { + "bits": {}, + "grid_x": 111, + "grid_y": 207, + "sites": { + "TIEOFF_X45Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y1": { + "bits": {}, + "grid_x": 111, + "grid_y": 206, + "sites": { + "TIEOFF_X45Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y10": { + "bits": {}, + "grid_x": 111, + "grid_y": 197, + "sites": { + "TIEOFF_X45Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y11": { + "bits": {}, + "grid_x": 111, + "grid_y": 196, + "sites": { + "TIEOFF_X45Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y12": { + "bits": {}, + "grid_x": 111, + "grid_y": 195, + "sites": { + "TIEOFF_X45Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y13": { + "bits": {}, + "grid_x": 111, + "grid_y": 194, + "sites": { + "TIEOFF_X45Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y14": { + "bits": {}, + "grid_x": 111, + "grid_y": 193, + "sites": { + "TIEOFF_X45Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y15": { + "bits": {}, + "grid_x": 111, + "grid_y": 192, + "sites": { + "TIEOFF_X45Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y16": { + "bits": {}, + "grid_x": 111, + "grid_y": 191, + "sites": { + "TIEOFF_X45Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y17": { + "bits": {}, + "grid_x": 111, + "grid_y": 190, + "sites": { + "TIEOFF_X45Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y18": { + "bits": {}, + "grid_x": 111, + "grid_y": 189, + "sites": { + "TIEOFF_X45Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y19": { + "bits": {}, + "grid_x": 111, + "grid_y": 188, + "sites": { + "TIEOFF_X45Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y2": { + "bits": {}, + "grid_x": 111, + "grid_y": 205, + "sites": { + "TIEOFF_X45Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y20": { + "bits": {}, + "grid_x": 111, + "grid_y": 187, + "sites": { + "TIEOFF_X45Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y21": { + "bits": {}, + "grid_x": 111, + "grid_y": 186, + "sites": { + "TIEOFF_X45Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y22": { + "bits": {}, + "grid_x": 111, + "grid_y": 185, + "sites": { + "TIEOFF_X45Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y23": { + "bits": {}, + "grid_x": 111, + "grid_y": 184, + "sites": { + "TIEOFF_X45Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y24": { + "bits": {}, + "grid_x": 111, + "grid_y": 183, + "sites": { + "TIEOFF_X45Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y25": { + "bits": {}, + "grid_x": 111, + "grid_y": 181, + "sites": { + "TIEOFF_X45Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y26": { + "bits": {}, + "grid_x": 111, + "grid_y": 180, + "sites": { + "TIEOFF_X45Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y27": { + "bits": {}, + "grid_x": 111, + "grid_y": 179, + "sites": { + "TIEOFF_X45Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y28": { + "bits": {}, + "grid_x": 111, + "grid_y": 178, + "sites": { + "TIEOFF_X45Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y29": { + "bits": {}, + "grid_x": 111, + "grid_y": 177, + "sites": { + "TIEOFF_X45Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y3": { + "bits": {}, + "grid_x": 111, + "grid_y": 204, + "sites": { + "TIEOFF_X45Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y30": { + "bits": {}, + "grid_x": 111, + "grid_y": 176, + "sites": { + "TIEOFF_X45Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y31": { + "bits": {}, + "grid_x": 111, + "grid_y": 175, + "sites": { + "TIEOFF_X45Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y32": { + "bits": {}, + "grid_x": 111, + "grid_y": 174, + "sites": { + "TIEOFF_X45Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y33": { + "bits": {}, + "grid_x": 111, + "grid_y": 173, + "sites": { + "TIEOFF_X45Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y34": { + "bits": {}, + "grid_x": 111, + "grid_y": 172, + "sites": { + "TIEOFF_X45Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y35": { + "bits": {}, + "grid_x": 111, + "grid_y": 171, + "sites": { + "TIEOFF_X45Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y36": { + "bits": {}, + "grid_x": 111, + "grid_y": 170, + "sites": { + "TIEOFF_X45Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y37": { + "bits": {}, + "grid_x": 111, + "grid_y": 169, + "sites": { + "TIEOFF_X45Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y38": { + "bits": {}, + "grid_x": 111, + "grid_y": 168, + "sites": { + "TIEOFF_X45Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y39": { + "bits": {}, + "grid_x": 111, + "grid_y": 167, + "sites": { + "TIEOFF_X45Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y4": { + "bits": {}, + "grid_x": 111, + "grid_y": 203, + "sites": { + "TIEOFF_X45Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y40": { + "bits": {}, + "grid_x": 111, + "grid_y": 166, + "sites": { + "TIEOFF_X45Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y41": { + "bits": {}, + "grid_x": 111, + "grid_y": 165, + "sites": { + "TIEOFF_X45Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y42": { + "bits": {}, + "grid_x": 111, + "grid_y": 164, + "sites": { + "TIEOFF_X45Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y43": { + "bits": {}, + "grid_x": 111, + "grid_y": 163, + "sites": { + "TIEOFF_X45Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y44": { + "bits": {}, + "grid_x": 111, + "grid_y": 162, + "sites": { + "TIEOFF_X45Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y45": { + "bits": {}, + "grid_x": 111, + "grid_y": 161, + "sites": { + "TIEOFF_X45Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y46": { + "bits": {}, + "grid_x": 111, + "grid_y": 160, + "sites": { + "TIEOFF_X45Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y47": { + "bits": {}, + "grid_x": 111, + "grid_y": 159, + "sites": { + "TIEOFF_X45Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y48": { + "bits": {}, + "grid_x": 111, + "grid_y": 158, + "sites": { + "TIEOFF_X45Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y49": { + "bits": {}, + "grid_x": 111, + "grid_y": 157, + "sites": { + "TIEOFF_X45Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y5": { + "bits": {}, + "grid_x": 111, + "grid_y": 202, + "sites": { + "TIEOFF_X45Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y50": { + "bits": {}, + "grid_x": 111, + "grid_y": 155, + "sites": { + "TIEOFF_X45Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y51": { + "bits": {}, + "grid_x": 111, + "grid_y": 154, + "sites": { + "TIEOFF_X45Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y52": { + "bits": {}, + "grid_x": 111, + "grid_y": 153, + "sites": { + "TIEOFF_X45Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y53": { + "bits": {}, + "grid_x": 111, + "grid_y": 152, + "sites": { + "TIEOFF_X45Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y54": { + "bits": {}, + "grid_x": 111, + "grid_y": 151, + "sites": { + "TIEOFF_X45Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y55": { + "bits": {}, + "grid_x": 111, + "grid_y": 150, + "sites": { + "TIEOFF_X45Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y56": { + "bits": {}, + "grid_x": 111, + "grid_y": 149, + "sites": { + "TIEOFF_X45Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y57": { + "bits": {}, + "grid_x": 111, + "grid_y": 148, + "sites": { + "TIEOFF_X45Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y58": { + "bits": {}, + "grid_x": 111, + "grid_y": 147, + "sites": { + "TIEOFF_X45Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y59": { + "bits": {}, + "grid_x": 111, + "grid_y": 146, + "sites": { + "TIEOFF_X45Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y6": { + "bits": {}, + "grid_x": 111, + "grid_y": 201, + "sites": { + "TIEOFF_X45Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y60": { + "bits": {}, + "grid_x": 111, + "grid_y": 145, + "sites": { + "TIEOFF_X45Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y61": { + "bits": {}, + "grid_x": 111, + "grid_y": 144, + "sites": { + "TIEOFF_X45Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y62": { + "bits": {}, + "grid_x": 111, + "grid_y": 143, + "sites": { + "TIEOFF_X45Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y63": { + "bits": {}, + "grid_x": 111, + "grid_y": 142, + "sites": { + "TIEOFF_X45Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y64": { + "bits": {}, + "grid_x": 111, + "grid_y": 141, + "sites": { + "TIEOFF_X45Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y65": { + "bits": {}, + "grid_x": 111, + "grid_y": 140, + "sites": { + "TIEOFF_X45Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y66": { + "bits": {}, + "grid_x": 111, + "grid_y": 139, + "sites": { + "TIEOFF_X45Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y67": { + "bits": {}, + "grid_x": 111, + "grid_y": 138, + "sites": { + "TIEOFF_X45Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y68": { + "bits": {}, + "grid_x": 111, + "grid_y": 137, + "sites": { + "TIEOFF_X45Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y69": { + "bits": {}, + "grid_x": 111, + "grid_y": 136, + "sites": { + "TIEOFF_X45Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y7": { + "bits": {}, + "grid_x": 111, + "grid_y": 200, + "sites": { + "TIEOFF_X45Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y70": { + "bits": {}, + "grid_x": 111, + "grid_y": 135, + "sites": { + "TIEOFF_X45Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y71": { + "bits": {}, + "grid_x": 111, + "grid_y": 134, + "sites": { + "TIEOFF_X45Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y72": { + "bits": {}, + "grid_x": 111, + "grid_y": 133, + "sites": { + "TIEOFF_X45Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y73": { + "bits": {}, + "grid_x": 111, + "grid_y": 132, + "sites": { + "TIEOFF_X45Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y74": { + "bits": {}, + "grid_x": 111, + "grid_y": 131, + "sites": { + "TIEOFF_X45Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y75": { + "bits": {}, + "grid_x": 111, + "grid_y": 129, + "sites": { + "TIEOFF_X45Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y76": { + "bits": {}, + "grid_x": 111, + "grid_y": 128, + "sites": { + "TIEOFF_X45Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y77": { + "bits": {}, + "grid_x": 111, + "grid_y": 127, + "sites": { + "TIEOFF_X45Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y78": { + "bits": {}, + "grid_x": 111, + "grid_y": 126, + "sites": { + "TIEOFF_X45Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y79": { + "bits": {}, + "grid_x": 111, + "grid_y": 125, + "sites": { + "TIEOFF_X45Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y8": { + "bits": {}, + "grid_x": 111, + "grid_y": 199, + "sites": { + "TIEOFF_X45Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y80": { + "bits": {}, + "grid_x": 111, + "grid_y": 124, + "sites": { + "TIEOFF_X45Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y81": { + "bits": {}, + "grid_x": 111, + "grid_y": 123, + "sites": { + "TIEOFF_X45Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y82": { + "bits": {}, + "grid_x": 111, + "grid_y": 122, + "sites": { + "TIEOFF_X45Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y83": { + "bits": {}, + "grid_x": 111, + "grid_y": 121, + "sites": { + "TIEOFF_X45Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y84": { + "bits": {}, + "grid_x": 111, + "grid_y": 120, + "sites": { + "TIEOFF_X45Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y85": { + "bits": {}, + "grid_x": 111, + "grid_y": 119, + "sites": { + "TIEOFF_X45Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y86": { + "bits": {}, + "grid_x": 111, + "grid_y": 118, + "sites": { + "TIEOFF_X45Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y87": { + "bits": {}, + "grid_x": 111, + "grid_y": 117, + "sites": { + "TIEOFF_X45Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y88": { + "bits": {}, + "grid_x": 111, + "grid_y": 116, + "sites": { + "TIEOFF_X45Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y89": { + "bits": {}, + "grid_x": 111, + "grid_y": 115, + "sites": { + "TIEOFF_X45Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y9": { + "bits": {}, + "grid_x": 111, + "grid_y": 198, + "sites": { + "TIEOFF_X45Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y90": { + "bits": {}, + "grid_x": 111, + "grid_y": 114, + "sites": { + "TIEOFF_X45Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y91": { + "bits": {}, + "grid_x": 111, + "grid_y": 113, + "sites": { + "TIEOFF_X45Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y92": { + "bits": {}, + "grid_x": 111, + "grid_y": 112, + "sites": { + "TIEOFF_X45Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y93": { + "bits": {}, + "grid_x": 111, + "grid_y": 111, + "sites": { + "TIEOFF_X45Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y94": { + "bits": {}, + "grid_x": 111, + "grid_y": 110, + "sites": { + "TIEOFF_X45Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y95": { + "bits": {}, + "grid_x": 111, + "grid_y": 109, + "sites": { + "TIEOFF_X45Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y96": { + "bits": {}, + "grid_x": 111, + "grid_y": 108, + "sites": { + "TIEOFF_X45Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y97": { + "bits": {}, + "grid_x": 111, + "grid_y": 107, + "sites": { + "TIEOFF_X45Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y98": { + "bits": {}, + "grid_x": 111, + "grid_y": 106, + "sites": { + "TIEOFF_X45Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X42Y99": { + "bits": {}, + "grid_x": 111, + "grid_y": 105, + "sites": { + "TIEOFF_X45Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y0": { + "bits": {}, + "grid_x": 15, + "grid_y": 207, + "segment": "SEG_CLBLL_L_X4Y0", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y1": { + "bits": {}, + "grid_x": 15, + "grid_y": 206, + "segment": "SEG_CLBLL_L_X4Y1", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y10": { + "bits": {}, + "grid_x": 15, + "grid_y": 197, + "segment": "SEG_CLBLL_L_X4Y10", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y100": { + "bits": {}, + "grid_x": 15, + "grid_y": 103, + "segment": "SEG_CLBLL_L_X4Y100", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y101": { + "bits": {}, + "grid_x": 15, + "grid_y": 102, + "segment": "SEG_CLBLL_L_X4Y101", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y102": { + "bits": {}, + "grid_x": 15, + "grid_y": 101, + "segment": "SEG_CLBLL_L_X4Y102", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y103": { + "bits": {}, + "grid_x": 15, + "grid_y": 100, + "segment": "SEG_CLBLL_L_X4Y103", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y104": { + "bits": {}, + "grid_x": 15, + "grid_y": 99, + "segment": "SEG_CLBLL_L_X4Y104", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y105": { + "bits": {}, + "grid_x": 15, + "grid_y": 98, + "segment": "SEG_CLBLL_L_X4Y105", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y106": { + "bits": {}, + "grid_x": 15, + "grid_y": 97, + "segment": "SEG_CLBLL_L_X4Y106", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y107": { + "bits": {}, + "grid_x": 15, + "grid_y": 96, + "segment": "SEG_CLBLL_L_X4Y107", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y108": { + "bits": {}, + "grid_x": 15, + "grid_y": 95, + "segment": "SEG_CLBLL_L_X4Y108", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y109": { + "bits": {}, + "grid_x": 15, + "grid_y": 94, + "segment": "SEG_CLBLL_L_X4Y109", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y11": { + "bits": {}, + "grid_x": 15, + "grid_y": 196, + "segment": "SEG_CLBLL_L_X4Y11", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y110": { + "bits": {}, + "grid_x": 15, + "grid_y": 93, + "segment": "SEG_CLBLL_L_X4Y110", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y111": { + "bits": {}, + "grid_x": 15, + "grid_y": 92, + "segment": "SEG_CLBLL_L_X4Y111", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y112": { + "bits": {}, + "grid_x": 15, + "grid_y": 91, + "segment": "SEG_CLBLL_L_X4Y112", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y113": { + "bits": {}, + "grid_x": 15, + "grid_y": 90, + "segment": "SEG_CLBLL_L_X4Y113", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y114": { + "bits": {}, + "grid_x": 15, + "grid_y": 89, + "segment": "SEG_CLBLL_L_X4Y114", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y115": { + "bits": {}, + "grid_x": 15, + "grid_y": 88, + "segment": "SEG_CLBLL_L_X4Y115", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y116": { + "bits": {}, + "grid_x": 15, + "grid_y": 87, + "segment": "SEG_CLBLL_L_X4Y116", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y117": { + "bits": {}, + "grid_x": 15, + "grid_y": 86, + "segment": "SEG_CLBLL_L_X4Y117", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y118": { + "bits": {}, + "grid_x": 15, + "grid_y": 85, + "segment": "SEG_CLBLL_L_X4Y118", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y119": { + "bits": {}, + "grid_x": 15, + "grid_y": 84, + "segment": "SEG_CLBLL_L_X4Y119", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y12": { + "bits": {}, + "grid_x": 15, + "grid_y": 195, + "segment": "SEG_CLBLL_L_X4Y12", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y120": { + "bits": {}, + "grid_x": 15, + "grid_y": 83, + "segment": "SEG_CLBLL_L_X4Y120", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y121": { + "bits": {}, + "grid_x": 15, + "grid_y": 82, + "segment": "SEG_CLBLL_L_X4Y121", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y122": { + "bits": {}, + "grid_x": 15, + "grid_y": 81, + "segment": "SEG_CLBLL_L_X4Y122", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y123": { + "bits": {}, + "grid_x": 15, + "grid_y": 80, + "segment": "SEG_CLBLL_L_X4Y123", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y124": { + "bits": {}, + "grid_x": 15, + "grid_y": 79, + "segment": "SEG_CLBLL_L_X4Y124", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y125": { + "bits": {}, + "grid_x": 15, + "grid_y": 77, + "segment": "SEG_CLBLL_L_X4Y125", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y126": { + "bits": {}, + "grid_x": 15, + "grid_y": 76, + "segment": "SEG_CLBLL_L_X4Y126", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y127": { + "bits": {}, + "grid_x": 15, + "grid_y": 75, + "segment": "SEG_CLBLL_L_X4Y127", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y128": { + "bits": {}, + "grid_x": 15, + "grid_y": 74, + "segment": "SEG_CLBLL_L_X4Y128", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y129": { + "bits": {}, + "grid_x": 15, + "grid_y": 73, + "segment": "SEG_CLBLL_L_X4Y129", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y13": { + "bits": {}, + "grid_x": 15, + "grid_y": 194, + "segment": "SEG_CLBLL_L_X4Y13", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y130": { + "bits": {}, + "grid_x": 15, + "grid_y": 72, + "segment": "SEG_CLBLL_L_X4Y130", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y131": { + "bits": {}, + "grid_x": 15, + "grid_y": 71, + "segment": "SEG_CLBLL_L_X4Y131", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y132": { + "bits": {}, + "grid_x": 15, + "grid_y": 70, + "segment": "SEG_CLBLL_L_X4Y132", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y133": { + "bits": {}, + "grid_x": 15, + "grid_y": 69, + "segment": "SEG_CLBLL_L_X4Y133", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y134": { + "bits": {}, + "grid_x": 15, + "grid_y": 68, + "segment": "SEG_CLBLL_L_X4Y134", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y135": { + "bits": {}, + "grid_x": 15, + "grid_y": 67, + "segment": "SEG_CLBLL_L_X4Y135", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y136": { + "bits": {}, + "grid_x": 15, + "grid_y": 66, + "segment": "SEG_CLBLL_L_X4Y136", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y137": { + "bits": {}, + "grid_x": 15, + "grid_y": 65, + "segment": "SEG_CLBLL_L_X4Y137", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y138": { + "bits": {}, + "grid_x": 15, + "grid_y": 64, + "segment": "SEG_CLBLL_L_X4Y138", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y139": { + "bits": {}, + "grid_x": 15, + "grid_y": 63, + "segment": "SEG_CLBLL_L_X4Y139", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y14": { + "bits": {}, + "grid_x": 15, + "grid_y": 193, + "segment": "SEG_CLBLL_L_X4Y14", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y140": { + "bits": {}, + "grid_x": 15, + "grid_y": 62, + "segment": "SEG_CLBLL_L_X4Y140", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y141": { + "bits": {}, + "grid_x": 15, + "grid_y": 61, + "segment": "SEG_CLBLL_L_X4Y141", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y142": { + "bits": {}, + "grid_x": 15, + "grid_y": 60, + "segment": "SEG_CLBLL_L_X4Y142", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y143": { + "bits": {}, + "grid_x": 15, + "grid_y": 59, + "segment": "SEG_CLBLL_L_X4Y143", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y144": { + "bits": {}, + "grid_x": 15, + "grid_y": 58, + "segment": "SEG_CLBLL_L_X4Y144", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y145": { + "bits": {}, + "grid_x": 15, + "grid_y": 57, + "segment": "SEG_CLBLL_L_X4Y145", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y146": { + "bits": {}, + "grid_x": 15, + "grid_y": 56, + "segment": "SEG_CLBLL_L_X4Y146", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y147": { + "bits": {}, + "grid_x": 15, + "grid_y": 55, + "segment": "SEG_CLBLL_L_X4Y147", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y148": { + "bits": {}, + "grid_x": 15, + "grid_y": 54, + "segment": "SEG_CLBLL_L_X4Y148", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y149": { + "bits": {}, + "grid_x": 15, + "grid_y": 53, + "segment": "SEG_CLBLL_L_X4Y149", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y15": { + "bits": {}, + "grid_x": 15, + "grid_y": 192, + "segment": "SEG_CLBLL_L_X4Y15", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y150": { + "bits": {}, + "grid_x": 15, + "grid_y": 51, + "segment": "SEG_CLBLL_L_X4Y150", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y151": { + "bits": {}, + "grid_x": 15, + "grid_y": 50, + "segment": "SEG_CLBLL_L_X4Y151", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y152": { + "bits": {}, + "grid_x": 15, + "grid_y": 49, + "segment": "SEG_CLBLL_L_X4Y152", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y153": { + "bits": {}, + "grid_x": 15, + "grid_y": 48, + "segment": "SEG_CLBLL_L_X4Y153", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y154": { + "bits": {}, + "grid_x": 15, + "grid_y": 47, + "segment": "SEG_CLBLL_L_X4Y154", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y155": { + "bits": {}, + "grid_x": 15, + "grid_y": 46, + "segment": "SEG_CLBLL_L_X4Y155", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y156": { + "bits": {}, + "grid_x": 15, + "grid_y": 45, + "segment": "SEG_CLBLL_L_X4Y156", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y157": { + "bits": {}, + "grid_x": 15, + "grid_y": 44, + "segment": "SEG_CLBLL_L_X4Y157", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y158": { + "bits": {}, + "grid_x": 15, + "grid_y": 43, + "segment": "SEG_CLBLL_L_X4Y158", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y159": { + "bits": {}, + "grid_x": 15, + "grid_y": 42, + "segment": "SEG_CLBLL_L_X4Y159", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y16": { + "bits": {}, + "grid_x": 15, + "grid_y": 191, + "segment": "SEG_CLBLL_L_X4Y16", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y160": { + "bits": {}, + "grid_x": 15, + "grid_y": 41, + "segment": "SEG_CLBLL_L_X4Y160", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y161": { + "bits": {}, + "grid_x": 15, + "grid_y": 40, + "segment": "SEG_CLBLL_L_X4Y161", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y162": { + "bits": {}, + "grid_x": 15, + "grid_y": 39, + "segment": "SEG_CLBLL_L_X4Y162", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y163": { + "bits": {}, + "grid_x": 15, + "grid_y": 38, + "segment": "SEG_CLBLL_L_X4Y163", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y164": { + "bits": {}, + "grid_x": 15, + "grid_y": 37, + "segment": "SEG_CLBLL_L_X4Y164", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y165": { + "bits": {}, + "grid_x": 15, + "grid_y": 36, + "segment": "SEG_CLBLL_L_X4Y165", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y166": { + "bits": {}, + "grid_x": 15, + "grid_y": 35, + "segment": "SEG_CLBLL_L_X4Y166", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y167": { + "bits": {}, + "grid_x": 15, + "grid_y": 34, + "segment": "SEG_CLBLL_L_X4Y167", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y168": { + "bits": {}, + "grid_x": 15, + "grid_y": 33, + "segment": "SEG_CLBLL_L_X4Y168", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y169": { + "bits": {}, + "grid_x": 15, + "grid_y": 32, + "segment": "SEG_CLBLL_L_X4Y169", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y17": { + "bits": {}, + "grid_x": 15, + "grid_y": 190, + "segment": "SEG_CLBLL_L_X4Y17", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y170": { + "bits": {}, + "grid_x": 15, + "grid_y": 31, + "segment": "SEG_CLBLL_L_X4Y170", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y171": { + "bits": {}, + "grid_x": 15, + "grid_y": 30, + "segment": "SEG_CLBLL_L_X4Y171", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y172": { + "bits": {}, + "grid_x": 15, + "grid_y": 29, + "segment": "SEG_CLBLL_L_X4Y172", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y173": { + "bits": {}, + "grid_x": 15, + "grid_y": 28, + "segment": "SEG_CLBLL_L_X4Y173", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y174": { + "bits": {}, + "grid_x": 15, + "grid_y": 27, + "segment": "SEG_CLBLL_L_X4Y174", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y175": { + "bits": {}, + "grid_x": 15, + "grid_y": 25, + "segment": "SEG_CLBLL_L_X4Y175", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y176": { + "bits": {}, + "grid_x": 15, + "grid_y": 24, + "segment": "SEG_CLBLL_L_X4Y176", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y177": { + "bits": {}, + "grid_x": 15, + "grid_y": 23, + "segment": "SEG_CLBLL_L_X4Y177", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y178": { + "bits": {}, + "grid_x": 15, + "grid_y": 22, + "segment": "SEG_CLBLL_L_X4Y178", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y179": { + "bits": {}, + "grid_x": 15, + "grid_y": 21, + "segment": "SEG_CLBLL_L_X4Y179", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y18": { + "bits": {}, + "grid_x": 15, + "grid_y": 189, + "segment": "SEG_CLBLL_L_X4Y18", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y180": { + "bits": {}, + "grid_x": 15, + "grid_y": 20, + "segment": "SEG_CLBLL_L_X4Y180", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y181": { + "bits": {}, + "grid_x": 15, + "grid_y": 19, + "segment": "SEG_CLBLL_L_X4Y181", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y182": { + "bits": {}, + "grid_x": 15, + "grid_y": 18, + "segment": "SEG_CLBLL_L_X4Y182", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y183": { + "bits": {}, + "grid_x": 15, + "grid_y": 17, + "segment": "SEG_CLBLL_L_X4Y183", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y184": { + "bits": {}, + "grid_x": 15, + "grid_y": 16, + "segment": "SEG_CLBLL_L_X4Y184", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y185": { + "bits": {}, + "grid_x": 15, + "grid_y": 15, + "segment": "SEG_CLBLL_L_X4Y185", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y186": { + "bits": {}, + "grid_x": 15, + "grid_y": 14, + "segment": "SEG_CLBLL_L_X4Y186", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y187": { + "bits": {}, + "grid_x": 15, + "grid_y": 13, + "segment": "SEG_CLBLL_L_X4Y187", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y188": { + "bits": {}, + "grid_x": 15, + "grid_y": 12, + "segment": "SEG_CLBLL_L_X4Y188", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y189": { + "bits": {}, + "grid_x": 15, + "grid_y": 11, + "segment": "SEG_CLBLL_L_X4Y189", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y19": { + "bits": {}, + "grid_x": 15, + "grid_y": 188, + "segment": "SEG_CLBLL_L_X4Y19", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y190": { + "bits": {}, + "grid_x": 15, + "grid_y": 10, + "segment": "SEG_CLBLL_L_X4Y190", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y191": { + "bits": {}, + "grid_x": 15, + "grid_y": 9, + "segment": "SEG_CLBLL_L_X4Y191", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y192": { + "bits": {}, + "grid_x": 15, + "grid_y": 8, + "segment": "SEG_CLBLL_L_X4Y192", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y193": { + "bits": {}, + "grid_x": 15, + "grid_y": 7, + "segment": "SEG_CLBLL_L_X4Y193", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y194": { + "bits": {}, + "grid_x": 15, + "grid_y": 6, + "segment": "SEG_CLBLL_L_X4Y194", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y195": { + "bits": {}, + "grid_x": 15, + "grid_y": 5, + "segment": "SEG_CLBLL_L_X4Y195", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y196": { + "bits": {}, + "grid_x": 15, + "grid_y": 4, + "segment": "SEG_CLBLL_L_X4Y196", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y197": { + "bits": {}, + "grid_x": 15, + "grid_y": 3, + "segment": "SEG_CLBLL_L_X4Y197", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y198": { + "bits": {}, + "grid_x": 15, + "grid_y": 2, + "segment": "SEG_CLBLL_L_X4Y198", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y199": { + "bits": {}, + "grid_x": 15, + "grid_y": 1, + "segment": "SEG_CLBLL_L_X4Y199", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y2": { + "bits": {}, + "grid_x": 15, + "grid_y": 205, + "segment": "SEG_CLBLL_L_X4Y2", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y20": { + "bits": {}, + "grid_x": 15, + "grid_y": 187, + "segment": "SEG_CLBLL_L_X4Y20", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y21": { + "bits": {}, + "grid_x": 15, + "grid_y": 186, + "segment": "SEG_CLBLL_L_X4Y21", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y22": { + "bits": {}, + "grid_x": 15, + "grid_y": 185, + "segment": "SEG_CLBLL_L_X4Y22", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y23": { + "bits": {}, + "grid_x": 15, + "grid_y": 184, + "segment": "SEG_CLBLL_L_X4Y23", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y24": { + "bits": {}, + "grid_x": 15, + "grid_y": 183, + "segment": "SEG_CLBLL_L_X4Y24", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y25": { + "bits": {}, + "grid_x": 15, + "grid_y": 181, + "segment": "SEG_CLBLL_L_X4Y25", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y26": { + "bits": {}, + "grid_x": 15, + "grid_y": 180, + "segment": "SEG_CLBLL_L_X4Y26", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y27": { + "bits": {}, + "grid_x": 15, + "grid_y": 179, + "segment": "SEG_CLBLL_L_X4Y27", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y28": { + "bits": {}, + "grid_x": 15, + "grid_y": 178, + "segment": "SEG_CLBLL_L_X4Y28", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y29": { + "bits": {}, + "grid_x": 15, + "grid_y": 177, + "segment": "SEG_CLBLL_L_X4Y29", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y3": { + "bits": {}, + "grid_x": 15, + "grid_y": 204, + "segment": "SEG_CLBLL_L_X4Y3", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y30": { + "bits": {}, + "grid_x": 15, + "grid_y": 176, + "segment": "SEG_CLBLL_L_X4Y30", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y31": { + "bits": {}, + "grid_x": 15, + "grid_y": 175, + "segment": "SEG_CLBLL_L_X4Y31", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y32": { + "bits": {}, + "grid_x": 15, + "grid_y": 174, + "segment": "SEG_CLBLL_L_X4Y32", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y33": { + "bits": {}, + "grid_x": 15, + "grid_y": 173, + "segment": "SEG_CLBLL_L_X4Y33", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y34": { + "bits": {}, + "grid_x": 15, + "grid_y": 172, + "segment": "SEG_CLBLL_L_X4Y34", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y35": { + "bits": {}, + "grid_x": 15, + "grid_y": 171, + "segment": "SEG_CLBLL_L_X4Y35", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y36": { + "bits": {}, + "grid_x": 15, + "grid_y": 170, + "segment": "SEG_CLBLL_L_X4Y36", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y37": { + "bits": {}, + "grid_x": 15, + "grid_y": 169, + "segment": "SEG_CLBLL_L_X4Y37", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y38": { + "bits": {}, + "grid_x": 15, + "grid_y": 168, + "segment": "SEG_CLBLL_L_X4Y38", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y39": { + "bits": {}, + "grid_x": 15, + "grid_y": 167, + "segment": "SEG_CLBLL_L_X4Y39", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y4": { + "bits": {}, + "grid_x": 15, + "grid_y": 203, + "segment": "SEG_CLBLL_L_X4Y4", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y40": { + "bits": {}, + "grid_x": 15, + "grid_y": 166, + "segment": "SEG_CLBLL_L_X4Y40", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y41": { + "bits": {}, + "grid_x": 15, + "grid_y": 165, + "segment": "SEG_CLBLL_L_X4Y41", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y42": { + "bits": {}, + "grid_x": 15, + "grid_y": 164, + "segment": "SEG_CLBLL_L_X4Y42", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y43": { + "bits": {}, + "grid_x": 15, + "grid_y": 163, + "segment": "SEG_CLBLL_L_X4Y43", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y44": { + "bits": {}, + "grid_x": 15, + "grid_y": 162, + "segment": "SEG_CLBLL_L_X4Y44", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y45": { + "bits": {}, + "grid_x": 15, + "grid_y": 161, + "segment": "SEG_CLBLL_L_X4Y45", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y46": { + "bits": {}, + "grid_x": 15, + "grid_y": 160, + "segment": "SEG_CLBLL_L_X4Y46", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y47": { + "bits": {}, + "grid_x": 15, + "grid_y": 159, + "segment": "SEG_CLBLL_L_X4Y47", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y48": { + "bits": {}, + "grid_x": 15, + "grid_y": 158, + "segment": "SEG_CLBLL_L_X4Y48", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y49": { + "bits": {}, + "grid_x": 15, + "grid_y": 157, + "segment": "SEG_CLBLL_L_X4Y49", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y5": { + "bits": {}, + "grid_x": 15, + "grid_y": 202, + "segment": "SEG_CLBLL_L_X4Y5", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 155, + "segment": "SEG_CLBLL_L_X4Y50", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 154, + "segment": "SEG_CLBLL_L_X4Y51", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 153, + "segment": "SEG_CLBLL_L_X4Y52", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 152, + "segment": "SEG_CLBLL_L_X4Y53", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 151, + "segment": "SEG_CLBLL_L_X4Y54", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 150, + "segment": "SEG_CLBLL_L_X4Y55", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 149, + "segment": "SEG_CLBLL_L_X4Y56", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 148, + "segment": "SEG_CLBLL_L_X4Y57", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 147, + "segment": "SEG_CLBLL_L_X4Y58", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 146, + "segment": "SEG_CLBLL_L_X4Y59", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y6": { + "bits": {}, + "grid_x": 15, + "grid_y": 201, + "segment": "SEG_CLBLL_L_X4Y6", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 145, + "segment": "SEG_CLBLL_L_X4Y60", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 144, + "segment": "SEG_CLBLL_L_X4Y61", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 143, + "segment": "SEG_CLBLL_L_X4Y62", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 142, + "segment": "SEG_CLBLL_L_X4Y63", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 141, + "segment": "SEG_CLBLL_L_X4Y64", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 140, + "segment": "SEG_CLBLL_L_X4Y65", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 139, + "segment": "SEG_CLBLL_L_X4Y66", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 138, + "segment": "SEG_CLBLL_L_X4Y67", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 137, + "segment": "SEG_CLBLL_L_X4Y68", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 136, + "segment": "SEG_CLBLL_L_X4Y69", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y7": { + "bits": {}, + "grid_x": 15, + "grid_y": 200, + "segment": "SEG_CLBLL_L_X4Y7", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 135, + "segment": "SEG_CLBLL_L_X4Y70", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 134, + "segment": "SEG_CLBLL_L_X4Y71", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 133, + "segment": "SEG_CLBLL_L_X4Y72", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 132, + "segment": "SEG_CLBLL_L_X4Y73", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 131, + "segment": "SEG_CLBLL_L_X4Y74", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 129, + "segment": "SEG_CLBLL_L_X4Y75", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 128, + "segment": "SEG_CLBLL_L_X4Y76", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 127, + "segment": "SEG_CLBLL_L_X4Y77", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 126, + "segment": "SEG_CLBLL_L_X4Y78", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 125, + "segment": "SEG_CLBLL_L_X4Y79", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y8": { + "bits": {}, + "grid_x": 15, + "grid_y": 199, + "segment": "SEG_CLBLL_L_X4Y8", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 124, + "segment": "SEG_CLBLL_L_X4Y80", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 123, + "segment": "SEG_CLBLL_L_X4Y81", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 122, + "segment": "SEG_CLBLL_L_X4Y82", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 121, + "segment": "SEG_CLBLL_L_X4Y83", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 120, + "segment": "SEG_CLBLL_L_X4Y84", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 119, + "segment": "SEG_CLBLL_L_X4Y85", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 118, + "segment": "SEG_CLBLL_L_X4Y86", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 117, + "segment": "SEG_CLBLL_L_X4Y87", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 116, + "segment": "SEG_CLBLL_L_X4Y88", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 115, + "segment": "SEG_CLBLL_L_X4Y89", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y9": { + "bits": {}, + "grid_x": 15, + "grid_y": 198, + "segment": "SEG_CLBLL_L_X4Y9", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 114, + "segment": "SEG_CLBLL_L_X4Y90", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 113, + "segment": "SEG_CLBLL_L_X4Y91", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 112, + "segment": "SEG_CLBLL_L_X4Y92", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 111, + "segment": "SEG_CLBLL_L_X4Y93", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 110, + "segment": "SEG_CLBLL_L_X4Y94", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 109, + "segment": "SEG_CLBLL_L_X4Y95", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 108, + "segment": "SEG_CLBLL_L_X4Y96", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 107, + "segment": "SEG_CLBLL_L_X4Y97", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 106, + "segment": "SEG_CLBLL_L_X4Y98", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X4Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400200", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 15, + "grid_y": 105, + "segment": "SEG_CLBLL_L_X4Y99", + "segment_type": "clbll_l", + "sites": { + "TIEOFF_X4Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y0": { + "bits": {}, + "grid_x": 21, + "grid_y": 207, + "segment": "SEG_BRAM0_L_X6Y0", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y1": { + "bits": {}, + "grid_x": 21, + "grid_y": 206, + "segment": "SEG_BRAM1_L_X6Y0", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y10": { + "bits": {}, + "grid_x": 21, + "grid_y": 197, + "segment": "SEG_BRAM0_L_X6Y10", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y100": { + "bits": {}, + "grid_x": 21, + "grid_y": 103, + "segment": "SEG_BRAM0_L_X6Y100", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y101": { + "bits": {}, + "grid_x": 21, + "grid_y": 102, + "segment": "SEG_BRAM1_L_X6Y100", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y102": { + "bits": {}, + "grid_x": 21, + "grid_y": 101, + "segment": "SEG_BRAM2_L_X6Y100", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y103": { + "bits": {}, + "grid_x": 21, + "grid_y": 100, + "segment": "SEG_BRAM3_L_X6Y100", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y104": { + "bits": {}, + "grid_x": 21, + "grid_y": 99, + "segment": "SEG_BRAM4_L_X6Y100", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y105": { + "bits": {}, + "grid_x": 21, + "grid_y": 98, + "segment": "SEG_BRAM0_L_X6Y105", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y106": { + "bits": {}, + "grid_x": 21, + "grid_y": 97, + "segment": "SEG_BRAM1_L_X6Y105", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y107": { + "bits": {}, + "grid_x": 21, + "grid_y": 96, + "segment": "SEG_BRAM2_L_X6Y105", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y108": { + "bits": {}, + "grid_x": 21, + "grid_y": 95, + "segment": "SEG_BRAM3_L_X6Y105", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y109": { + "bits": {}, + "grid_x": 21, + "grid_y": 94, + "segment": "SEG_BRAM4_L_X6Y105", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y11": { + "bits": {}, + "grid_x": 21, + "grid_y": 196, + "segment": "SEG_BRAM1_L_X6Y10", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y110": { + "bits": {}, + "grid_x": 21, + "grid_y": 93, + "segment": "SEG_BRAM0_L_X6Y110", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y111": { + "bits": {}, + "grid_x": 21, + "grid_y": 92, + "segment": "SEG_BRAM1_L_X6Y110", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y112": { + "bits": {}, + "grid_x": 21, + "grid_y": 91, + "segment": "SEG_BRAM2_L_X6Y110", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y113": { + "bits": {}, + "grid_x": 21, + "grid_y": 90, + "segment": "SEG_BRAM3_L_X6Y110", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y114": { + "bits": {}, + "grid_x": 21, + "grid_y": 89, + "segment": "SEG_BRAM4_L_X6Y110", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y115": { + "bits": {}, + "grid_x": 21, + "grid_y": 88, + "segment": "SEG_BRAM0_L_X6Y115", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y116": { + "bits": {}, + "grid_x": 21, + "grid_y": 87, + "segment": "SEG_BRAM1_L_X6Y115", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y117": { + "bits": {}, + "grid_x": 21, + "grid_y": 86, + "segment": "SEG_BRAM2_L_X6Y115", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y118": { + "bits": {}, + "grid_x": 21, + "grid_y": 85, + "segment": "SEG_BRAM3_L_X6Y115", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y119": { + "bits": {}, + "grid_x": 21, + "grid_y": 84, + "segment": "SEG_BRAM4_L_X6Y115", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y12": { + "bits": {}, + "grid_x": 21, + "grid_y": 195, + "segment": "SEG_BRAM2_L_X6Y10", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y120": { + "bits": {}, + "grid_x": 21, + "grid_y": 83, + "segment": "SEG_BRAM0_L_X6Y120", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y121": { + "bits": {}, + "grid_x": 21, + "grid_y": 82, + "segment": "SEG_BRAM1_L_X6Y120", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y122": { + "bits": {}, + "grid_x": 21, + "grid_y": 81, + "segment": "SEG_BRAM2_L_X6Y120", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y123": { + "bits": {}, + "grid_x": 21, + "grid_y": 80, + "segment": "SEG_BRAM3_L_X6Y120", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y124": { + "bits": {}, + "grid_x": 21, + "grid_y": 79, + "segment": "SEG_BRAM4_L_X6Y120", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y125": { + "bits": {}, + "grid_x": 21, + "grid_y": 77, + "segment": "SEG_BRAM0_L_X6Y125", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y126": { + "bits": {}, + "grid_x": 21, + "grid_y": 76, + "segment": "SEG_BRAM1_L_X6Y125", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y127": { + "bits": {}, + "grid_x": 21, + "grid_y": 75, + "segment": "SEG_BRAM2_L_X6Y125", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y128": { + "bits": {}, + "grid_x": 21, + "grid_y": 74, + "segment": "SEG_BRAM3_L_X6Y125", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y129": { + "bits": {}, + "grid_x": 21, + "grid_y": 73, + "segment": "SEG_BRAM4_L_X6Y125", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y13": { + "bits": {}, + "grid_x": 21, + "grid_y": 194, + "segment": "SEG_BRAM3_L_X6Y10", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y130": { + "bits": {}, + "grid_x": 21, + "grid_y": 72, + "segment": "SEG_BRAM0_L_X6Y130", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y131": { + "bits": {}, + "grid_x": 21, + "grid_y": 71, + "segment": "SEG_BRAM1_L_X6Y130", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y132": { + "bits": {}, + "grid_x": 21, + "grid_y": 70, + "segment": "SEG_BRAM2_L_X6Y130", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y133": { + "bits": {}, + "grid_x": 21, + "grid_y": 69, + "segment": "SEG_BRAM3_L_X6Y130", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y134": { + "bits": {}, + "grid_x": 21, + "grid_y": 68, + "segment": "SEG_BRAM4_L_X6Y130", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y135": { + "bits": {}, + "grid_x": 21, + "grid_y": 67, + "segment": "SEG_BRAM0_L_X6Y135", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y136": { + "bits": {}, + "grid_x": 21, + "grid_y": 66, + "segment": "SEG_BRAM1_L_X6Y135", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y137": { + "bits": {}, + "grid_x": 21, + "grid_y": 65, + "segment": "SEG_BRAM2_L_X6Y135", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y138": { + "bits": {}, + "grid_x": 21, + "grid_y": 64, + "segment": "SEG_BRAM3_L_X6Y135", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y139": { + "bits": {}, + "grid_x": 21, + "grid_y": 63, + "segment": "SEG_BRAM4_L_X6Y135", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y14": { + "bits": {}, + "grid_x": 21, + "grid_y": 193, + "segment": "SEG_BRAM4_L_X6Y10", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y140": { + "bits": {}, + "grid_x": 21, + "grid_y": 62, + "segment": "SEG_BRAM0_L_X6Y140", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y141": { + "bits": {}, + "grid_x": 21, + "grid_y": 61, + "segment": "SEG_BRAM1_L_X6Y140", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y142": { + "bits": {}, + "grid_x": 21, + "grid_y": 60, + "segment": "SEG_BRAM2_L_X6Y140", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y143": { + "bits": {}, + "grid_x": 21, + "grid_y": 59, + "segment": "SEG_BRAM3_L_X6Y140", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y144": { + "bits": {}, + "grid_x": 21, + "grid_y": 58, + "segment": "SEG_BRAM4_L_X6Y140", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y145": { + "bits": {}, + "grid_x": 21, + "grid_y": 57, + "segment": "SEG_BRAM0_L_X6Y145", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y146": { + "bits": {}, + "grid_x": 21, + "grid_y": 56, + "segment": "SEG_BRAM1_L_X6Y145", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y147": { + "bits": {}, + "grid_x": 21, + "grid_y": 55, + "segment": "SEG_BRAM2_L_X6Y145", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y148": { + "bits": {}, + "grid_x": 21, + "grid_y": 54, + "segment": "SEG_BRAM3_L_X6Y145", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y149": { + "bits": {}, + "grid_x": 21, + "grid_y": 53, + "segment": "SEG_BRAM4_L_X6Y145", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y15": { + "bits": {}, + "grid_x": 21, + "grid_y": 192, + "segment": "SEG_BRAM0_L_X6Y15", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y150": { + "bits": {}, + "grid_x": 21, + "grid_y": 51, + "segment": "SEG_BRAM0_L_X6Y150", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y151": { + "bits": {}, + "grid_x": 21, + "grid_y": 50, + "segment": "SEG_BRAM1_L_X6Y150", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y152": { + "bits": {}, + "grid_x": 21, + "grid_y": 49, + "segment": "SEG_BRAM2_L_X6Y150", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y153": { + "bits": {}, + "grid_x": 21, + "grid_y": 48, + "segment": "SEG_BRAM3_L_X6Y150", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y154": { + "bits": {}, + "grid_x": 21, + "grid_y": 47, + "segment": "SEG_BRAM4_L_X6Y150", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y155": { + "bits": {}, + "grid_x": 21, + "grid_y": 46, + "segment": "SEG_BRAM0_L_X6Y155", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y156": { + "bits": {}, + "grid_x": 21, + "grid_y": 45, + "segment": "SEG_BRAM1_L_X6Y155", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y157": { + "bits": {}, + "grid_x": 21, + "grid_y": 44, + "segment": "SEG_BRAM2_L_X6Y155", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y158": { + "bits": {}, + "grid_x": 21, + "grid_y": 43, + "segment": "SEG_BRAM3_L_X6Y155", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y159": { + "bits": {}, + "grid_x": 21, + "grid_y": 42, + "segment": "SEG_BRAM4_L_X6Y155", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y16": { + "bits": {}, + "grid_x": 21, + "grid_y": 191, + "segment": "SEG_BRAM1_L_X6Y15", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y160": { + "bits": {}, + "grid_x": 21, + "grid_y": 41, + "segment": "SEG_BRAM0_L_X6Y160", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y161": { + "bits": {}, + "grid_x": 21, + "grid_y": 40, + "segment": "SEG_BRAM1_L_X6Y160", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y162": { + "bits": {}, + "grid_x": 21, + "grid_y": 39, + "segment": "SEG_BRAM2_L_X6Y160", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y163": { + "bits": {}, + "grid_x": 21, + "grid_y": 38, + "segment": "SEG_BRAM3_L_X6Y160", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y164": { + "bits": {}, + "grid_x": 21, + "grid_y": 37, + "segment": "SEG_BRAM4_L_X6Y160", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y165": { + "bits": {}, + "grid_x": 21, + "grid_y": 36, + "segment": "SEG_BRAM0_L_X6Y165", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y166": { + "bits": {}, + "grid_x": 21, + "grid_y": 35, + "segment": "SEG_BRAM1_L_X6Y165", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y167": { + "bits": {}, + "grid_x": 21, + "grid_y": 34, + "segment": "SEG_BRAM2_L_X6Y165", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y168": { + "bits": {}, + "grid_x": 21, + "grid_y": 33, + "segment": "SEG_BRAM3_L_X6Y165", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y169": { + "bits": {}, + "grid_x": 21, + "grid_y": 32, + "segment": "SEG_BRAM4_L_X6Y165", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y17": { + "bits": {}, + "grid_x": 21, + "grid_y": 190, + "segment": "SEG_BRAM2_L_X6Y15", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y170": { + "bits": {}, + "grid_x": 21, + "grid_y": 31, + "segment": "SEG_BRAM0_L_X6Y170", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y171": { + "bits": {}, + "grid_x": 21, + "grid_y": 30, + "segment": "SEG_BRAM1_L_X6Y170", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y172": { + "bits": {}, + "grid_x": 21, + "grid_y": 29, + "segment": "SEG_BRAM2_L_X6Y170", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y173": { + "bits": {}, + "grid_x": 21, + "grid_y": 28, + "segment": "SEG_BRAM3_L_X6Y170", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y174": { + "bits": {}, + "grid_x": 21, + "grid_y": 27, + "segment": "SEG_BRAM4_L_X6Y170", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y175": { + "bits": {}, + "grid_x": 21, + "grid_y": 25, + "segment": "SEG_BRAM0_L_X6Y175", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y176": { + "bits": {}, + "grid_x": 21, + "grid_y": 24, + "segment": "SEG_BRAM1_L_X6Y175", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y177": { + "bits": {}, + "grid_x": 21, + "grid_y": 23, + "segment": "SEG_BRAM2_L_X6Y175", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y178": { + "bits": {}, + "grid_x": 21, + "grid_y": 22, + "segment": "SEG_BRAM3_L_X6Y175", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y179": { + "bits": {}, + "grid_x": 21, + "grid_y": 21, + "segment": "SEG_BRAM4_L_X6Y175", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y18": { + "bits": {}, + "grid_x": 21, + "grid_y": 189, + "segment": "SEG_BRAM3_L_X6Y15", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y180": { + "bits": {}, + "grid_x": 21, + "grid_y": 20, + "segment": "SEG_BRAM0_L_X6Y180", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y181": { + "bits": {}, + "grid_x": 21, + "grid_y": 19, + "segment": "SEG_BRAM1_L_X6Y180", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y182": { + "bits": {}, + "grid_x": 21, + "grid_y": 18, + "segment": "SEG_BRAM2_L_X6Y180", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y183": { + "bits": {}, + "grid_x": 21, + "grid_y": 17, + "segment": "SEG_BRAM3_L_X6Y180", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y184": { + "bits": {}, + "grid_x": 21, + "grid_y": 16, + "segment": "SEG_BRAM4_L_X6Y180", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y185": { + "bits": {}, + "grid_x": 21, + "grid_y": 15, + "segment": "SEG_BRAM0_L_X6Y185", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y186": { + "bits": {}, + "grid_x": 21, + "grid_y": 14, + "segment": "SEG_BRAM1_L_X6Y185", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y187": { + "bits": {}, + "grid_x": 21, + "grid_y": 13, + "segment": "SEG_BRAM2_L_X6Y185", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y188": { + "bits": {}, + "grid_x": 21, + "grid_y": 12, + "segment": "SEG_BRAM3_L_X6Y185", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y189": { + "bits": {}, + "grid_x": 21, + "grid_y": 11, + "segment": "SEG_BRAM4_L_X6Y185", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y19": { + "bits": {}, + "grid_x": 21, + "grid_y": 188, + "segment": "SEG_BRAM4_L_X6Y15", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y190": { + "bits": {}, + "grid_x": 21, + "grid_y": 10, + "segment": "SEG_BRAM0_L_X6Y190", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y191": { + "bits": {}, + "grid_x": 21, + "grid_y": 9, + "segment": "SEG_BRAM1_L_X6Y190", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y192": { + "bits": {}, + "grid_x": 21, + "grid_y": 8, + "segment": "SEG_BRAM2_L_X6Y190", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y193": { + "bits": {}, + "grid_x": 21, + "grid_y": 7, + "segment": "SEG_BRAM3_L_X6Y190", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y194": { + "bits": {}, + "grid_x": 21, + "grid_y": 6, + "segment": "SEG_BRAM4_L_X6Y190", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y195": { + "bits": {}, + "grid_x": 21, + "grid_y": 5, + "segment": "SEG_BRAM0_L_X6Y195", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y196": { + "bits": {}, + "grid_x": 21, + "grid_y": 4, + "segment": "SEG_BRAM1_L_X6Y195", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y197": { + "bits": {}, + "grid_x": 21, + "grid_y": 3, + "segment": "SEG_BRAM2_L_X6Y195", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y198": { + "bits": {}, + "grid_x": 21, + "grid_y": 2, + "segment": "SEG_BRAM3_L_X6Y195", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y199": { + "bits": {}, + "grid_x": 21, + "grid_y": 1, + "segment": "SEG_BRAM4_L_X6Y195", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y2": { + "bits": {}, + "grid_x": 21, + "grid_y": 205, + "segment": "SEG_BRAM2_L_X6Y0", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y20": { + "bits": {}, + "grid_x": 21, + "grid_y": 187, + "segment": "SEG_BRAM0_L_X6Y20", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y21": { + "bits": {}, + "grid_x": 21, + "grid_y": 186, + "segment": "SEG_BRAM1_L_X6Y20", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y22": { + "bits": {}, + "grid_x": 21, + "grid_y": 185, + "segment": "SEG_BRAM2_L_X6Y20", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y23": { + "bits": {}, + "grid_x": 21, + "grid_y": 184, + "segment": "SEG_BRAM3_L_X6Y20", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y24": { + "bits": {}, + "grid_x": 21, + "grid_y": 183, + "segment": "SEG_BRAM4_L_X6Y20", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y25": { + "bits": {}, + "grid_x": 21, + "grid_y": 181, + "segment": "SEG_BRAM0_L_X6Y25", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y26": { + "bits": {}, + "grid_x": 21, + "grid_y": 180, + "segment": "SEG_BRAM1_L_X6Y25", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y27": { + "bits": {}, + "grid_x": 21, + "grid_y": 179, + "segment": "SEG_BRAM2_L_X6Y25", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y28": { + "bits": {}, + "grid_x": 21, + "grid_y": 178, + "segment": "SEG_BRAM3_L_X6Y25", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y29": { + "bits": {}, + "grid_x": 21, + "grid_y": 177, + "segment": "SEG_BRAM4_L_X6Y25", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y3": { + "bits": {}, + "grid_x": 21, + "grid_y": 204, + "segment": "SEG_BRAM3_L_X6Y0", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y30": { + "bits": {}, + "grid_x": 21, + "grid_y": 176, + "segment": "SEG_BRAM0_L_X6Y30", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y31": { + "bits": {}, + "grid_x": 21, + "grid_y": 175, + "segment": "SEG_BRAM1_L_X6Y30", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y32": { + "bits": {}, + "grid_x": 21, + "grid_y": 174, + "segment": "SEG_BRAM2_L_X6Y30", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y33": { + "bits": {}, + "grid_x": 21, + "grid_y": 173, + "segment": "SEG_BRAM3_L_X6Y30", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y34": { + "bits": {}, + "grid_x": 21, + "grid_y": 172, + "segment": "SEG_BRAM4_L_X6Y30", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y35": { + "bits": {}, + "grid_x": 21, + "grid_y": 171, + "segment": "SEG_BRAM0_L_X6Y35", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y36": { + "bits": {}, + "grid_x": 21, + "grid_y": 170, + "segment": "SEG_BRAM1_L_X6Y35", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y37": { + "bits": {}, + "grid_x": 21, + "grid_y": 169, + "segment": "SEG_BRAM2_L_X6Y35", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y38": { + "bits": {}, + "grid_x": 21, + "grid_y": 168, + "segment": "SEG_BRAM3_L_X6Y35", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y39": { + "bits": {}, + "grid_x": 21, + "grid_y": 167, + "segment": "SEG_BRAM4_L_X6Y35", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y4": { + "bits": {}, + "grid_x": 21, + "grid_y": 203, + "segment": "SEG_BRAM4_L_X6Y0", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y40": { + "bits": {}, + "grid_x": 21, + "grid_y": 166, + "segment": "SEG_BRAM0_L_X6Y40", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y41": { + "bits": {}, + "grid_x": 21, + "grid_y": 165, + "segment": "SEG_BRAM1_L_X6Y40", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y42": { + "bits": {}, + "grid_x": 21, + "grid_y": 164, + "segment": "SEG_BRAM2_L_X6Y40", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y43": { + "bits": {}, + "grid_x": 21, + "grid_y": 163, + "segment": "SEG_BRAM3_L_X6Y40", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y44": { + "bits": {}, + "grid_x": 21, + "grid_y": 162, + "segment": "SEG_BRAM4_L_X6Y40", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y45": { + "bits": {}, + "grid_x": 21, + "grid_y": 161, + "segment": "SEG_BRAM0_L_X6Y45", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y46": { + "bits": {}, + "grid_x": 21, + "grid_y": 160, + "segment": "SEG_BRAM1_L_X6Y45", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y47": { + "bits": {}, + "grid_x": 21, + "grid_y": 159, + "segment": "SEG_BRAM2_L_X6Y45", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y48": { + "bits": {}, + "grid_x": 21, + "grid_y": 158, + "segment": "SEG_BRAM3_L_X6Y45", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y49": { + "bits": {}, + "grid_x": 21, + "grid_y": 157, + "segment": "SEG_BRAM4_L_X6Y45", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y5": { + "bits": {}, + "grid_x": 21, + "grid_y": 202, + "segment": "SEG_BRAM0_L_X6Y5", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 155, + "segment": "SEG_BRAM0_L_X6Y50", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 154, + "segment": "SEG_BRAM1_L_X6Y50", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 153, + "segment": "SEG_BRAM2_L_X6Y50", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 152, + "segment": "SEG_BRAM3_L_X6Y50", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 151, + "segment": "SEG_BRAM4_L_X6Y50", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 150, + "segment": "SEG_BRAM0_L_X6Y55", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 149, + "segment": "SEG_BRAM1_L_X6Y55", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 148, + "segment": "SEG_BRAM2_L_X6Y55", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 147, + "segment": "SEG_BRAM3_L_X6Y55", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 146, + "segment": "SEG_BRAM4_L_X6Y55", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y6": { + "bits": {}, + "grid_x": 21, + "grid_y": 201, + "segment": "SEG_BRAM1_L_X6Y5", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 145, + "segment": "SEG_BRAM0_L_X6Y60", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 144, + "segment": "SEG_BRAM1_L_X6Y60", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 143, + "segment": "SEG_BRAM2_L_X6Y60", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 142, + "segment": "SEG_BRAM3_L_X6Y60", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 141, + "segment": "SEG_BRAM4_L_X6Y60", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 140, + "segment": "SEG_BRAM0_L_X6Y65", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 139, + "segment": "SEG_BRAM1_L_X6Y65", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 138, + "segment": "SEG_BRAM2_L_X6Y65", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 137, + "segment": "SEG_BRAM3_L_X6Y65", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 136, + "segment": "SEG_BRAM4_L_X6Y65", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y7": { + "bits": {}, + "grid_x": 21, + "grid_y": 200, + "segment": "SEG_BRAM2_L_X6Y5", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 135, + "segment": "SEG_BRAM0_L_X6Y70", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 134, + "segment": "SEG_BRAM1_L_X6Y70", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 133, + "segment": "SEG_BRAM2_L_X6Y70", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 132, + "segment": "SEG_BRAM3_L_X6Y70", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 131, + "segment": "SEG_BRAM4_L_X6Y70", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 129, + "segment": "SEG_BRAM0_L_X6Y75", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 128, + "segment": "SEG_BRAM1_L_X6Y75", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 127, + "segment": "SEG_BRAM2_L_X6Y75", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 126, + "segment": "SEG_BRAM3_L_X6Y75", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 125, + "segment": "SEG_BRAM4_L_X6Y75", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y8": { + "bits": {}, + "grid_x": 21, + "grid_y": 199, + "segment": "SEG_BRAM3_L_X6Y5", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 124, + "segment": "SEG_BRAM0_L_X6Y80", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 123, + "segment": "SEG_BRAM1_L_X6Y80", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 122, + "segment": "SEG_BRAM2_L_X6Y80", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 121, + "segment": "SEG_BRAM3_L_X6Y80", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 120, + "segment": "SEG_BRAM4_L_X6Y80", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 119, + "segment": "SEG_BRAM0_L_X6Y85", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 118, + "segment": "SEG_BRAM1_L_X6Y85", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 117, + "segment": "SEG_BRAM2_L_X6Y85", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 116, + "segment": "SEG_BRAM3_L_X6Y85", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 115, + "segment": "SEG_BRAM4_L_X6Y85", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y9": { + "bits": {}, + "grid_x": 21, + "grid_y": 198, + "segment": "SEG_BRAM4_L_X6Y5", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 114, + "segment": "SEG_BRAM0_L_X6Y90", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 113, + "segment": "SEG_BRAM1_L_X6Y90", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 112, + "segment": "SEG_BRAM2_L_X6Y90", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 111, + "segment": "SEG_BRAM3_L_X6Y90", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 110, + "segment": "SEG_BRAM4_L_X6Y90", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 109, + "segment": "SEG_BRAM0_L_X6Y95", + "segment_type": "bram0_l", + "sites": { + "TIEOFF_X6Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 108, + "segment": "SEG_BRAM1_L_X6Y95", + "segment_type": "bram1_l", + "sites": { + "TIEOFF_X6Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 107, + "segment": "SEG_BRAM2_L_X6Y95", + "segment_type": "bram2_l", + "sites": { + "TIEOFF_X6Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 106, + "segment": "SEG_BRAM3_L_X6Y95", + "segment_type": "bram3_l", + "sites": { + "TIEOFF_X6Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X6Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400300", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 21, + "grid_y": 105, + "segment": "SEG_BRAM4_L_X6Y95", + "segment_type": "bram4_l", + "sites": { + "TIEOFF_X6Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y0": { + "bits": {}, + "grid_x": 25, + "grid_y": 207, + "segment": "SEG_CLBLM_L_X8Y0", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y0": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y1": { + "bits": {}, + "grid_x": 25, + "grid_y": 206, + "segment": "SEG_CLBLM_L_X8Y1", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y1": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y10": { + "bits": {}, + "grid_x": 25, + "grid_y": 197, + "segment": "SEG_CLBLM_L_X8Y10", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y10": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y100": { + "bits": {}, + "grid_x": 25, + "grid_y": 103, + "segment": "SEG_CLBLM_L_X8Y100", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y100": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y101": { + "bits": {}, + "grid_x": 25, + "grid_y": 102, + "segment": "SEG_CLBLM_L_X8Y101", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y101": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y102": { + "bits": {}, + "grid_x": 25, + "grid_y": 101, + "segment": "SEG_CLBLM_L_X8Y102", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y102": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y103": { + "bits": {}, + "grid_x": 25, + "grid_y": 100, + "segment": "SEG_CLBLM_L_X8Y103", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y103": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y104": { + "bits": {}, + "grid_x": 25, + "grid_y": 99, + "segment": "SEG_CLBLM_L_X8Y104", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y104": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y105": { + "bits": {}, + "grid_x": 25, + "grid_y": 98, + "segment": "SEG_CLBLM_L_X8Y105", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y105": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y106": { + "bits": {}, + "grid_x": 25, + "grid_y": 97, + "segment": "SEG_CLBLM_L_X8Y106", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y106": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y107": { + "bits": {}, + "grid_x": 25, + "grid_y": 96, + "segment": "SEG_CLBLM_L_X8Y107", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y107": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y108": { + "bits": {}, + "grid_x": 25, + "grid_y": 95, + "segment": "SEG_CLBLM_L_X8Y108", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y108": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y109": { + "bits": {}, + "grid_x": 25, + "grid_y": 94, + "segment": "SEG_CLBLM_L_X8Y109", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y109": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y11": { + "bits": {}, + "grid_x": 25, + "grid_y": 196, + "segment": "SEG_CLBLM_L_X8Y11", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y11": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y110": { + "bits": {}, + "grid_x": 25, + "grid_y": 93, + "segment": "SEG_CLBLM_L_X8Y110", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y110": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y111": { + "bits": {}, + "grid_x": 25, + "grid_y": 92, + "segment": "SEG_CLBLM_L_X8Y111", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y111": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y112": { + "bits": {}, + "grid_x": 25, + "grid_y": 91, + "segment": "SEG_CLBLM_L_X8Y112", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y112": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y113": { + "bits": {}, + "grid_x": 25, + "grid_y": 90, + "segment": "SEG_CLBLM_L_X8Y113", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y113": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y114": { + "bits": {}, + "grid_x": 25, + "grid_y": 89, + "segment": "SEG_CLBLM_L_X8Y114", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y114": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y115": { + "bits": {}, + "grid_x": 25, + "grid_y": 88, + "segment": "SEG_CLBLM_L_X8Y115", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y115": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y116": { + "bits": {}, + "grid_x": 25, + "grid_y": 87, + "segment": "SEG_CLBLM_L_X8Y116", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y116": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y117": { + "bits": {}, + "grid_x": 25, + "grid_y": 86, + "segment": "SEG_CLBLM_L_X8Y117", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y117": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y118": { + "bits": {}, + "grid_x": 25, + "grid_y": 85, + "segment": "SEG_CLBLM_L_X8Y118", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y118": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y119": { + "bits": {}, + "grid_x": 25, + "grid_y": 84, + "segment": "SEG_CLBLM_L_X8Y119", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y119": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y12": { + "bits": {}, + "grid_x": 25, + "grid_y": 195, + "segment": "SEG_CLBLM_L_X8Y12", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y12": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y120": { + "bits": {}, + "grid_x": 25, + "grid_y": 83, + "segment": "SEG_CLBLM_L_X8Y120", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y120": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y121": { + "bits": {}, + "grid_x": 25, + "grid_y": 82, + "segment": "SEG_CLBLM_L_X8Y121", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y121": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y122": { + "bits": {}, + "grid_x": 25, + "grid_y": 81, + "segment": "SEG_CLBLM_L_X8Y122", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y122": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y123": { + "bits": {}, + "grid_x": 25, + "grid_y": 80, + "segment": "SEG_CLBLM_L_X8Y123", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y123": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y124": { + "bits": {}, + "grid_x": 25, + "grid_y": 79, + "segment": "SEG_CLBLM_L_X8Y124", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y124": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y125": { + "bits": {}, + "grid_x": 25, + "grid_y": 77, + "segment": "SEG_CLBLM_L_X8Y125", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y125": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y126": { + "bits": {}, + "grid_x": 25, + "grid_y": 76, + "segment": "SEG_CLBLM_L_X8Y126", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y126": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y127": { + "bits": {}, + "grid_x": 25, + "grid_y": 75, + "segment": "SEG_CLBLM_L_X8Y127", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y127": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y128": { + "bits": {}, + "grid_x": 25, + "grid_y": 74, + "segment": "SEG_CLBLM_L_X8Y128", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y128": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y129": { + "bits": {}, + "grid_x": 25, + "grid_y": 73, + "segment": "SEG_CLBLM_L_X8Y129", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y129": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y13": { + "bits": {}, + "grid_x": 25, + "grid_y": 194, + "segment": "SEG_CLBLM_L_X8Y13", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y13": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y130": { + "bits": {}, + "grid_x": 25, + "grid_y": 72, + "segment": "SEG_CLBLM_L_X8Y130", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y130": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y131": { + "bits": {}, + "grid_x": 25, + "grid_y": 71, + "segment": "SEG_CLBLM_L_X8Y131", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y131": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y132": { + "bits": {}, + "grid_x": 25, + "grid_y": 70, + "segment": "SEG_CLBLM_L_X8Y132", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y132": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y133": { + "bits": {}, + "grid_x": 25, + "grid_y": 69, + "segment": "SEG_CLBLM_L_X8Y133", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y133": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y134": { + "bits": {}, + "grid_x": 25, + "grid_y": 68, + "segment": "SEG_CLBLM_L_X8Y134", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y134": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y135": { + "bits": {}, + "grid_x": 25, + "grid_y": 67, + "segment": "SEG_CLBLM_L_X8Y135", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y135": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y136": { + "bits": {}, + "grid_x": 25, + "grid_y": 66, + "segment": "SEG_CLBLM_L_X8Y136", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y136": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y137": { + "bits": {}, + "grid_x": 25, + "grid_y": 65, + "segment": "SEG_CLBLM_L_X8Y137", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y137": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y138": { + "bits": {}, + "grid_x": 25, + "grid_y": 64, + "segment": "SEG_CLBLM_L_X8Y138", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y138": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y139": { + "bits": {}, + "grid_x": 25, + "grid_y": 63, + "segment": "SEG_CLBLM_L_X8Y139", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y139": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y14": { + "bits": {}, + "grid_x": 25, + "grid_y": 193, + "segment": "SEG_CLBLM_L_X8Y14", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y14": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y140": { + "bits": {}, + "grid_x": 25, + "grid_y": 62, + "segment": "SEG_CLBLM_L_X8Y140", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y140": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y141": { + "bits": {}, + "grid_x": 25, + "grid_y": 61, + "segment": "SEG_CLBLM_L_X8Y141", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y141": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y142": { + "bits": {}, + "grid_x": 25, + "grid_y": 60, + "segment": "SEG_CLBLM_L_X8Y142", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y142": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y143": { + "bits": {}, + "grid_x": 25, + "grid_y": 59, + "segment": "SEG_CLBLM_L_X8Y143", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y143": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y144": { + "bits": {}, + "grid_x": 25, + "grid_y": 58, + "segment": "SEG_CLBLM_L_X8Y144", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y144": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y145": { + "bits": {}, + "grid_x": 25, + "grid_y": 57, + "segment": "SEG_CLBLM_L_X8Y145", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y145": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y146": { + "bits": {}, + "grid_x": 25, + "grid_y": 56, + "segment": "SEG_CLBLM_L_X8Y146", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y146": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y147": { + "bits": {}, + "grid_x": 25, + "grid_y": 55, + "segment": "SEG_CLBLM_L_X8Y147", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y147": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y148": { + "bits": {}, + "grid_x": 25, + "grid_y": 54, + "segment": "SEG_CLBLM_L_X8Y148", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y148": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y149": { + "bits": {}, + "grid_x": 25, + "grid_y": 53, + "segment": "SEG_CLBLM_L_X8Y149", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y149": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y15": { + "bits": {}, + "grid_x": 25, + "grid_y": 192, + "segment": "SEG_CLBLM_L_X8Y15", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y15": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y150": { + "bits": {}, + "grid_x": 25, + "grid_y": 51, + "segment": "SEG_CLBLM_L_X8Y150", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y150": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y151": { + "bits": {}, + "grid_x": 25, + "grid_y": 50, + "segment": "SEG_CLBLM_L_X8Y151", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y151": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y152": { + "bits": {}, + "grid_x": 25, + "grid_y": 49, + "segment": "SEG_CLBLM_L_X8Y152", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y152": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y153": { + "bits": {}, + "grid_x": 25, + "grid_y": 48, + "segment": "SEG_CLBLM_L_X8Y153", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y153": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y154": { + "bits": {}, + "grid_x": 25, + "grid_y": 47, + "segment": "SEG_CLBLM_L_X8Y154", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y154": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y155": { + "bits": {}, + "grid_x": 25, + "grid_y": 46, + "segment": "SEG_CLBLM_L_X8Y155", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y155": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y156": { + "bits": {}, + "grid_x": 25, + "grid_y": 45, + "segment": "SEG_CLBLM_L_X8Y156", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y156": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y157": { + "bits": {}, + "grid_x": 25, + "grid_y": 44, + "segment": "SEG_CLBLM_L_X8Y157", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y157": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y158": { + "bits": {}, + "grid_x": 25, + "grid_y": 43, + "segment": "SEG_CLBLM_L_X8Y158", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y158": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y159": { + "bits": {}, + "grid_x": 25, + "grid_y": 42, + "segment": "SEG_CLBLM_L_X8Y159", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y159": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y16": { + "bits": {}, + "grid_x": 25, + "grid_y": 191, + "segment": "SEG_CLBLM_L_X8Y16", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y16": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y160": { + "bits": {}, + "grid_x": 25, + "grid_y": 41, + "segment": "SEG_CLBLM_L_X8Y160", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y160": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y161": { + "bits": {}, + "grid_x": 25, + "grid_y": 40, + "segment": "SEG_CLBLM_L_X8Y161", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y161": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y162": { + "bits": {}, + "grid_x": 25, + "grid_y": 39, + "segment": "SEG_CLBLM_L_X8Y162", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y162": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y163": { + "bits": {}, + "grid_x": 25, + "grid_y": 38, + "segment": "SEG_CLBLM_L_X8Y163", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y163": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y164": { + "bits": {}, + "grid_x": 25, + "grid_y": 37, + "segment": "SEG_CLBLM_L_X8Y164", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y164": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y165": { + "bits": {}, + "grid_x": 25, + "grid_y": 36, + "segment": "SEG_CLBLM_L_X8Y165", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y165": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y166": { + "bits": {}, + "grid_x": 25, + "grid_y": 35, + "segment": "SEG_CLBLM_L_X8Y166", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y166": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y167": { + "bits": {}, + "grid_x": 25, + "grid_y": 34, + "segment": "SEG_CLBLM_L_X8Y167", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y167": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y168": { + "bits": {}, + "grid_x": 25, + "grid_y": 33, + "segment": "SEG_CLBLM_L_X8Y168", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y168": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y169": { + "bits": {}, + "grid_x": 25, + "grid_y": 32, + "segment": "SEG_CLBLM_L_X8Y169", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y169": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y17": { + "bits": {}, + "grid_x": 25, + "grid_y": 190, + "segment": "SEG_CLBLM_L_X8Y17", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y17": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y170": { + "bits": {}, + "grid_x": 25, + "grid_y": 31, + "segment": "SEG_CLBLM_L_X8Y170", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y170": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y171": { + "bits": {}, + "grid_x": 25, + "grid_y": 30, + "segment": "SEG_CLBLM_L_X8Y171", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y171": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y172": { + "bits": {}, + "grid_x": 25, + "grid_y": 29, + "segment": "SEG_CLBLM_L_X8Y172", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y172": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y173": { + "bits": {}, + "grid_x": 25, + "grid_y": 28, + "segment": "SEG_CLBLM_L_X8Y173", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y173": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y174": { + "bits": {}, + "grid_x": 25, + "grid_y": 27, + "segment": "SEG_CLBLM_L_X8Y174", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y174": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y175": { + "bits": {}, + "grid_x": 25, + "grid_y": 25, + "segment": "SEG_CLBLM_L_X8Y175", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y175": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y176": { + "bits": {}, + "grid_x": 25, + "grid_y": 24, + "segment": "SEG_CLBLM_L_X8Y176", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y176": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y177": { + "bits": {}, + "grid_x": 25, + "grid_y": 23, + "segment": "SEG_CLBLM_L_X8Y177", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y177": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y178": { + "bits": {}, + "grid_x": 25, + "grid_y": 22, + "segment": "SEG_CLBLM_L_X8Y178", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y178": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y179": { + "bits": {}, + "grid_x": 25, + "grid_y": 21, + "segment": "SEG_CLBLM_L_X8Y179", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y179": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y18": { + "bits": {}, + "grid_x": 25, + "grid_y": 189, + "segment": "SEG_CLBLM_L_X8Y18", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y18": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y180": { + "bits": {}, + "grid_x": 25, + "grid_y": 20, + "segment": "SEG_CLBLM_L_X8Y180", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y180": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y181": { + "bits": {}, + "grid_x": 25, + "grid_y": 19, + "segment": "SEG_CLBLM_L_X8Y181", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y181": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y182": { + "bits": {}, + "grid_x": 25, + "grid_y": 18, + "segment": "SEG_CLBLM_L_X8Y182", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y182": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y183": { + "bits": {}, + "grid_x": 25, + "grid_y": 17, + "segment": "SEG_CLBLM_L_X8Y183", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y183": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y184": { + "bits": {}, + "grid_x": 25, + "grid_y": 16, + "segment": "SEG_CLBLM_L_X8Y184", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y184": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y185": { + "bits": {}, + "grid_x": 25, + "grid_y": 15, + "segment": "SEG_CLBLM_L_X8Y185", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y185": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y186": { + "bits": {}, + "grid_x": 25, + "grid_y": 14, + "segment": "SEG_CLBLM_L_X8Y186", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y186": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y187": { + "bits": {}, + "grid_x": 25, + "grid_y": 13, + "segment": "SEG_CLBLM_L_X8Y187", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y187": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y188": { + "bits": {}, + "grid_x": 25, + "grid_y": 12, + "segment": "SEG_CLBLM_L_X8Y188", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y188": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y189": { + "bits": {}, + "grid_x": 25, + "grid_y": 11, + "segment": "SEG_CLBLM_L_X8Y189", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y189": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y19": { + "bits": {}, + "grid_x": 25, + "grid_y": 188, + "segment": "SEG_CLBLM_L_X8Y19", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y19": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y190": { + "bits": {}, + "grid_x": 25, + "grid_y": 10, + "segment": "SEG_CLBLM_L_X8Y190", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y190": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y191": { + "bits": {}, + "grid_x": 25, + "grid_y": 9, + "segment": "SEG_CLBLM_L_X8Y191", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y191": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y192": { + "bits": {}, + "grid_x": 25, + "grid_y": 8, + "segment": "SEG_CLBLM_L_X8Y192", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y192": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y193": { + "bits": {}, + "grid_x": 25, + "grid_y": 7, + "segment": "SEG_CLBLM_L_X8Y193", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y193": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y194": { + "bits": {}, + "grid_x": 25, + "grid_y": 6, + "segment": "SEG_CLBLM_L_X8Y194", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y194": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y195": { + "bits": {}, + "grid_x": 25, + "grid_y": 5, + "segment": "SEG_CLBLM_L_X8Y195", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y195": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y196": { + "bits": {}, + "grid_x": 25, + "grid_y": 4, + "segment": "SEG_CLBLM_L_X8Y196", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y196": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y197": { + "bits": {}, + "grid_x": 25, + "grid_y": 3, + "segment": "SEG_CLBLM_L_X8Y197", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y197": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y198": { + "bits": {}, + "grid_x": 25, + "grid_y": 2, + "segment": "SEG_CLBLM_L_X8Y198", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y198": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y199": { + "bits": {}, + "grid_x": 25, + "grid_y": 1, + "segment": "SEG_CLBLM_L_X8Y199", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y199": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y2": { + "bits": {}, + "grid_x": 25, + "grid_y": 205, + "segment": "SEG_CLBLM_L_X8Y2", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y2": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y20": { + "bits": {}, + "grid_x": 25, + "grid_y": 187, + "segment": "SEG_CLBLM_L_X8Y20", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y20": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y21": { + "bits": {}, + "grid_x": 25, + "grid_y": 186, + "segment": "SEG_CLBLM_L_X8Y21", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y21": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y22": { + "bits": {}, + "grid_x": 25, + "grid_y": 185, + "segment": "SEG_CLBLM_L_X8Y22", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y22": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y23": { + "bits": {}, + "grid_x": 25, + "grid_y": 184, + "segment": "SEG_CLBLM_L_X8Y23", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y23": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y24": { + "bits": {}, + "grid_x": 25, + "grid_y": 183, + "segment": "SEG_CLBLM_L_X8Y24", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y24": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y25": { + "bits": {}, + "grid_x": 25, + "grid_y": 181, + "segment": "SEG_CLBLM_L_X8Y25", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y25": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y26": { + "bits": {}, + "grid_x": 25, + "grid_y": 180, + "segment": "SEG_CLBLM_L_X8Y26", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y26": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y27": { + "bits": {}, + "grid_x": 25, + "grid_y": 179, + "segment": "SEG_CLBLM_L_X8Y27", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y27": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y28": { + "bits": {}, + "grid_x": 25, + "grid_y": 178, + "segment": "SEG_CLBLM_L_X8Y28", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y28": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y29": { + "bits": {}, + "grid_x": 25, + "grid_y": 177, + "segment": "SEG_CLBLM_L_X8Y29", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y29": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y3": { + "bits": {}, + "grid_x": 25, + "grid_y": 204, + "segment": "SEG_CLBLM_L_X8Y3", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y3": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y30": { + "bits": {}, + "grid_x": 25, + "grid_y": 176, + "segment": "SEG_CLBLM_L_X8Y30", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y30": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y31": { + "bits": {}, + "grid_x": 25, + "grid_y": 175, + "segment": "SEG_CLBLM_L_X8Y31", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y31": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y32": { + "bits": {}, + "grid_x": 25, + "grid_y": 174, + "segment": "SEG_CLBLM_L_X8Y32", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y32": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y33": { + "bits": {}, + "grid_x": 25, + "grid_y": 173, + "segment": "SEG_CLBLM_L_X8Y33", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y33": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y34": { + "bits": {}, + "grid_x": 25, + "grid_y": 172, + "segment": "SEG_CLBLM_L_X8Y34", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y34": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y35": { + "bits": {}, + "grid_x": 25, + "grid_y": 171, + "segment": "SEG_CLBLM_L_X8Y35", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y35": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y36": { + "bits": {}, + "grid_x": 25, + "grid_y": 170, + "segment": "SEG_CLBLM_L_X8Y36", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y36": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y37": { + "bits": {}, + "grid_x": 25, + "grid_y": 169, + "segment": "SEG_CLBLM_L_X8Y37", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y37": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y38": { + "bits": {}, + "grid_x": 25, + "grid_y": 168, + "segment": "SEG_CLBLM_L_X8Y38", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y38": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y39": { + "bits": {}, + "grid_x": 25, + "grid_y": 167, + "segment": "SEG_CLBLM_L_X8Y39", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y39": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y4": { + "bits": {}, + "grid_x": 25, + "grid_y": 203, + "segment": "SEG_CLBLM_L_X8Y4", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y4": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y40": { + "bits": {}, + "grid_x": 25, + "grid_y": 166, + "segment": "SEG_CLBLM_L_X8Y40", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y40": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y41": { + "bits": {}, + "grid_x": 25, + "grid_y": 165, + "segment": "SEG_CLBLM_L_X8Y41", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y41": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y42": { + "bits": {}, + "grid_x": 25, + "grid_y": 164, + "segment": "SEG_CLBLM_L_X8Y42", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y42": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y43": { + "bits": {}, + "grid_x": 25, + "grid_y": 163, + "segment": "SEG_CLBLM_L_X8Y43", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y43": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y44": { + "bits": {}, + "grid_x": 25, + "grid_y": 162, + "segment": "SEG_CLBLM_L_X8Y44", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y44": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y45": { + "bits": {}, + "grid_x": 25, + "grid_y": 161, + "segment": "SEG_CLBLM_L_X8Y45", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y45": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y46": { + "bits": {}, + "grid_x": 25, + "grid_y": 160, + "segment": "SEG_CLBLM_L_X8Y46", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y46": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y47": { + "bits": {}, + "grid_x": 25, + "grid_y": 159, + "segment": "SEG_CLBLM_L_X8Y47", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y47": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y48": { + "bits": {}, + "grid_x": 25, + "grid_y": 158, + "segment": "SEG_CLBLM_L_X8Y48", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y48": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y49": { + "bits": {}, + "grid_x": 25, + "grid_y": 157, + "segment": "SEG_CLBLM_L_X8Y49", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y49": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y5": { + "bits": {}, + "grid_x": 25, + "grid_y": 202, + "segment": "SEG_CLBLM_L_X8Y5", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y5": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 155, + "segment": "SEG_CLBLM_L_X8Y50", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y50": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 154, + "segment": "SEG_CLBLM_L_X8Y51", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y51": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 153, + "segment": "SEG_CLBLM_L_X8Y52", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y52": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 152, + "segment": "SEG_CLBLM_L_X8Y53", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y53": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 151, + "segment": "SEG_CLBLM_L_X8Y54", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y54": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 150, + "segment": "SEG_CLBLM_L_X8Y55", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y55": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 149, + "segment": "SEG_CLBLM_L_X8Y56", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y56": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 148, + "segment": "SEG_CLBLM_L_X8Y57", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y57": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 147, + "segment": "SEG_CLBLM_L_X8Y58", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y58": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 146, + "segment": "SEG_CLBLM_L_X8Y59", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y59": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y6": { + "bits": {}, + "grid_x": 25, + "grid_y": 201, + "segment": "SEG_CLBLM_L_X8Y6", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y6": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 145, + "segment": "SEG_CLBLM_L_X8Y60", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y60": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 144, + "segment": "SEG_CLBLM_L_X8Y61", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y61": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 143, + "segment": "SEG_CLBLM_L_X8Y62", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y62": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 142, + "segment": "SEG_CLBLM_L_X8Y63", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y63": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 141, + "segment": "SEG_CLBLM_L_X8Y64", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y64": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 140, + "segment": "SEG_CLBLM_L_X8Y65", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y65": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 139, + "segment": "SEG_CLBLM_L_X8Y66", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y66": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 138, + "segment": "SEG_CLBLM_L_X8Y67", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y67": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 137, + "segment": "SEG_CLBLM_L_X8Y68", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y68": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 136, + "segment": "SEG_CLBLM_L_X8Y69", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y69": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y7": { + "bits": {}, + "grid_x": 25, + "grid_y": 200, + "segment": "SEG_CLBLM_L_X8Y7", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y7": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 135, + "segment": "SEG_CLBLM_L_X8Y70", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y70": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 134, + "segment": "SEG_CLBLM_L_X8Y71", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y71": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 133, + "segment": "SEG_CLBLM_L_X8Y72", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y72": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 132, + "segment": "SEG_CLBLM_L_X8Y73", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y73": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 131, + "segment": "SEG_CLBLM_L_X8Y74", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y74": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 129, + "segment": "SEG_CLBLM_L_X8Y75", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y75": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 128, + "segment": "SEG_CLBLM_L_X8Y76", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y76": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 127, + "segment": "SEG_CLBLM_L_X8Y77", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y77": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 126, + "segment": "SEG_CLBLM_L_X8Y78", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y78": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 125, + "segment": "SEG_CLBLM_L_X8Y79", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y79": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y8": { + "bits": {}, + "grid_x": 25, + "grid_y": 199, + "segment": "SEG_CLBLM_L_X8Y8", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y8": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 124, + "segment": "SEG_CLBLM_L_X8Y80", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y80": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 123, + "segment": "SEG_CLBLM_L_X8Y81", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y81": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 122, + "segment": "SEG_CLBLM_L_X8Y82", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y82": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 121, + "segment": "SEG_CLBLM_L_X8Y83", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y83": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 120, + "segment": "SEG_CLBLM_L_X8Y84", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y84": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 119, + "segment": "SEG_CLBLM_L_X8Y85", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y85": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 118, + "segment": "SEG_CLBLM_L_X8Y86", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y86": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 117, + "segment": "SEG_CLBLM_L_X8Y87", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y87": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 116, + "segment": "SEG_CLBLM_L_X8Y88", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y88": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 115, + "segment": "SEG_CLBLM_L_X8Y89", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y89": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y9": { + "bits": {}, + "grid_x": 25, + "grid_y": 198, + "segment": "SEG_CLBLM_L_X8Y9", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y9": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 114, + "segment": "SEG_CLBLM_L_X8Y90", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y90": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 113, + "segment": "SEG_CLBLM_L_X8Y91", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y91": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 112, + "segment": "SEG_CLBLM_L_X8Y92", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y92": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 111, + "segment": "SEG_CLBLM_L_X8Y93", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y93": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 110, + "segment": "SEG_CLBLM_L_X8Y94", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y94": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 109, + "segment": "SEG_CLBLM_L_X8Y95", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y95": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 108, + "segment": "SEG_CLBLM_L_X8Y96", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y96": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 107, + "segment": "SEG_CLBLM_L_X8Y97", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y97": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 106, + "segment": "SEG_CLBLM_L_X8Y98", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y98": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_L_X8Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400400", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 25, + "grid_y": 105, + "segment": "SEG_CLBLM_L_X8Y99", + "segment_type": "clblm_l", + "sites": { + "TIEOFF_X8Y99": "TIEOFF" + }, + "type": "INT_L" + }, + "INT_R_X11Y0": { + "bits": {}, + "grid_x": 32, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X11Y0", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y1": { + "bits": {}, + "grid_x": 32, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X11Y1", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y10": { + "bits": {}, + "grid_x": 32, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X11Y10", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y100": { + "bits": {}, + "grid_x": 32, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X11Y100", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y101": { + "bits": {}, + "grid_x": 32, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X11Y101", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y102": { + "bits": {}, + "grid_x": 32, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X11Y102", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y103": { + "bits": {}, + "grid_x": 32, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X11Y103", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y104": { + "bits": {}, + "grid_x": 32, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X11Y104", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y105": { + "bits": {}, + "grid_x": 32, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X11Y105", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y106": { + "bits": {}, + "grid_x": 32, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X11Y106", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y107": { + "bits": {}, + "grid_x": 32, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X11Y107", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y108": { + "bits": {}, + "grid_x": 32, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X11Y108", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y109": { + "bits": {}, + "grid_x": 32, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X11Y109", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y11": { + "bits": {}, + "grid_x": 32, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X11Y11", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y110": { + "bits": {}, + "grid_x": 32, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X11Y110", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y111": { + "bits": {}, + "grid_x": 32, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X11Y111", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y112": { + "bits": {}, + "grid_x": 32, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X11Y112", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y113": { + "bits": {}, + "grid_x": 32, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X11Y113", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y114": { + "bits": {}, + "grid_x": 32, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X11Y114", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y115": { + "bits": {}, + "grid_x": 32, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X11Y115", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y116": { + "bits": {}, + "grid_x": 32, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X11Y116", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y117": { + "bits": {}, + "grid_x": 32, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X11Y117", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y118": { + "bits": {}, + "grid_x": 32, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X11Y118", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y119": { + "bits": {}, + "grid_x": 32, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X11Y119", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y12": { + "bits": {}, + "grid_x": 32, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X11Y12", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y120": { + "bits": {}, + "grid_x": 32, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X11Y120", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y121": { + "bits": {}, + "grid_x": 32, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X11Y121", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y122": { + "bits": {}, + "grid_x": 32, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X11Y122", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y123": { + "bits": {}, + "grid_x": 32, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X11Y123", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y124": { + "bits": {}, + "grid_x": 32, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X11Y124", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y125": { + "bits": {}, + "grid_x": 32, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X11Y125", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y126": { + "bits": {}, + "grid_x": 32, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X11Y126", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y127": { + "bits": {}, + "grid_x": 32, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X11Y127", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y128": { + "bits": {}, + "grid_x": 32, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X11Y128", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y129": { + "bits": {}, + "grid_x": 32, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X11Y129", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y13": { + "bits": {}, + "grid_x": 32, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X11Y13", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y130": { + "bits": {}, + "grid_x": 32, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X11Y130", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y131": { + "bits": {}, + "grid_x": 32, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X11Y131", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y132": { + "bits": {}, + "grid_x": 32, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X11Y132", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y133": { + "bits": {}, + "grid_x": 32, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X11Y133", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y134": { + "bits": {}, + "grid_x": 32, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X11Y134", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y135": { + "bits": {}, + "grid_x": 32, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X11Y135", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y136": { + "bits": {}, + "grid_x": 32, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X11Y136", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y137": { + "bits": {}, + "grid_x": 32, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X11Y137", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y138": { + "bits": {}, + "grid_x": 32, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X11Y138", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y139": { + "bits": {}, + "grid_x": 32, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X11Y139", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y14": { + "bits": {}, + "grid_x": 32, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X11Y14", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y140": { + "bits": {}, + "grid_x": 32, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X11Y140", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y141": { + "bits": {}, + "grid_x": 32, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X11Y141", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y142": { + "bits": {}, + "grid_x": 32, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X11Y142", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y143": { + "bits": {}, + "grid_x": 32, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X11Y143", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y144": { + "bits": {}, + "grid_x": 32, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X11Y144", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y145": { + "bits": {}, + "grid_x": 32, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X11Y145", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y146": { + "bits": {}, + "grid_x": 32, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X11Y146", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y147": { + "bits": {}, + "grid_x": 32, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X11Y147", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y148": { + "bits": {}, + "grid_x": 32, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X11Y148", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y149": { + "bits": {}, + "grid_x": 32, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X11Y149", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y15": { + "bits": {}, + "grid_x": 32, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X11Y15", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y150": { + "bits": {}, + "grid_x": 32, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X11Y150", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y151": { + "bits": {}, + "grid_x": 32, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X11Y151", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y152": { + "bits": {}, + "grid_x": 32, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X11Y152", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y153": { + "bits": {}, + "grid_x": 32, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X11Y153", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y154": { + "bits": {}, + "grid_x": 32, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X11Y154", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y155": { + "bits": {}, + "grid_x": 32, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X11Y155", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y156": { + "bits": {}, + "grid_x": 32, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X11Y156", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y157": { + "bits": {}, + "grid_x": 32, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X11Y157", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y158": { + "bits": {}, + "grid_x": 32, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X11Y158", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y159": { + "bits": {}, + "grid_x": 32, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X11Y159", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y16": { + "bits": {}, + "grid_x": 32, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X11Y16", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y160": { + "bits": {}, + "grid_x": 32, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X11Y160", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y161": { + "bits": {}, + "grid_x": 32, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X11Y161", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y162": { + "bits": {}, + "grid_x": 32, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X11Y162", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y163": { + "bits": {}, + "grid_x": 32, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X11Y163", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y164": { + "bits": {}, + "grid_x": 32, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X11Y164", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y165": { + "bits": {}, + "grid_x": 32, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X11Y165", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y166": { + "bits": {}, + "grid_x": 32, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X11Y166", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y167": { + "bits": {}, + "grid_x": 32, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X11Y167", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y168": { + "bits": {}, + "grid_x": 32, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X11Y168", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y169": { + "bits": {}, + "grid_x": 32, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X11Y169", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y17": { + "bits": {}, + "grid_x": 32, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X11Y17", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y170": { + "bits": {}, + "grid_x": 32, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X11Y170", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y171": { + "bits": {}, + "grid_x": 32, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X11Y171", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y172": { + "bits": {}, + "grid_x": 32, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X11Y172", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y173": { + "bits": {}, + "grid_x": 32, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X11Y173", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y174": { + "bits": {}, + "grid_x": 32, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X11Y174", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y175": { + "bits": {}, + "grid_x": 32, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X11Y175", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y176": { + "bits": {}, + "grid_x": 32, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X11Y176", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y177": { + "bits": {}, + "grid_x": 32, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X11Y177", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y178": { + "bits": {}, + "grid_x": 32, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X11Y178", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y179": { + "bits": {}, + "grid_x": 32, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X11Y179", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y18": { + "bits": {}, + "grid_x": 32, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X11Y18", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y180": { + "bits": {}, + "grid_x": 32, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X11Y180", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y181": { + "bits": {}, + "grid_x": 32, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X11Y181", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y182": { + "bits": {}, + "grid_x": 32, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X11Y182", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y183": { + "bits": {}, + "grid_x": 32, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X11Y183", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y184": { + "bits": {}, + "grid_x": 32, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X11Y184", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y185": { + "bits": {}, + "grid_x": 32, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X11Y185", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y186": { + "bits": {}, + "grid_x": 32, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X11Y186", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y187": { + "bits": {}, + "grid_x": 32, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X11Y187", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y188": { + "bits": {}, + "grid_x": 32, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X11Y188", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y189": { + "bits": {}, + "grid_x": 32, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X11Y189", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y19": { + "bits": {}, + "grid_x": 32, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X11Y19", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y190": { + "bits": {}, + "grid_x": 32, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X11Y190", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y191": { + "bits": {}, + "grid_x": 32, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X11Y191", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y192": { + "bits": {}, + "grid_x": 32, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X11Y192", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y193": { + "bits": {}, + "grid_x": 32, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X11Y193", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y194": { + "bits": {}, + "grid_x": 32, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X11Y194", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y195": { + "bits": {}, + "grid_x": 32, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X11Y195", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y196": { + "bits": {}, + "grid_x": 32, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X11Y196", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y197": { + "bits": {}, + "grid_x": 32, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X11Y197", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y198": { + "bits": {}, + "grid_x": 32, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X11Y198", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y199": { + "bits": {}, + "grid_x": 32, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X11Y199", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y2": { + "bits": {}, + "grid_x": 32, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X11Y2", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y20": { + "bits": {}, + "grid_x": 32, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X11Y20", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y21": { + "bits": {}, + "grid_x": 32, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X11Y21", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y22": { + "bits": {}, + "grid_x": 32, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X11Y22", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y23": { + "bits": {}, + "grid_x": 32, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X11Y23", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y24": { + "bits": {}, + "grid_x": 32, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X11Y24", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y25": { + "bits": {}, + "grid_x": 32, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X11Y25", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y26": { + "bits": {}, + "grid_x": 32, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X11Y26", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y27": { + "bits": {}, + "grid_x": 32, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X11Y27", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y28": { + "bits": {}, + "grid_x": 32, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X11Y28", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y29": { + "bits": {}, + "grid_x": 32, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X11Y29", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y3": { + "bits": {}, + "grid_x": 32, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X11Y3", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y30": { + "bits": {}, + "grid_x": 32, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X11Y30", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y31": { + "bits": {}, + "grid_x": 32, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X11Y31", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y32": { + "bits": {}, + "grid_x": 32, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X11Y32", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y33": { + "bits": {}, + "grid_x": 32, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X11Y33", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y34": { + "bits": {}, + "grid_x": 32, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X11Y34", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y35": { + "bits": {}, + "grid_x": 32, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X11Y35", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y36": { + "bits": {}, + "grid_x": 32, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X11Y36", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y37": { + "bits": {}, + "grid_x": 32, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X11Y37", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y38": { + "bits": {}, + "grid_x": 32, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X11Y38", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y39": { + "bits": {}, + "grid_x": 32, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X11Y39", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y4": { + "bits": {}, + "grid_x": 32, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X11Y4", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y40": { + "bits": {}, + "grid_x": 32, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X11Y40", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y41": { + "bits": {}, + "grid_x": 32, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X11Y41", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y42": { + "bits": {}, + "grid_x": 32, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X11Y42", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y43": { + "bits": {}, + "grid_x": 32, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X11Y43", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y44": { + "bits": {}, + "grid_x": 32, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X11Y44", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y45": { + "bits": {}, + "grid_x": 32, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X11Y45", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y46": { + "bits": {}, + "grid_x": 32, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X11Y46", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y47": { + "bits": {}, + "grid_x": 32, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X11Y47", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y48": { + "bits": {}, + "grid_x": 32, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X11Y48", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y49": { + "bits": {}, + "grid_x": 32, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X11Y49", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y5": { + "bits": {}, + "grid_x": 32, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X11Y5", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X11Y50", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X11Y51", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X11Y52", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X11Y53", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X11Y54", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X11Y55", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X11Y56", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X11Y57", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X11Y58", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X11Y59", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y6": { + "bits": {}, + "grid_x": 32, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X11Y6", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X11Y60", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X11Y61", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X11Y62", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X11Y63", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X11Y64", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X11Y65", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X11Y66", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X11Y67", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X11Y68", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X11Y69", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y7": { + "bits": {}, + "grid_x": 32, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X11Y7", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X11Y70", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X11Y71", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X11Y72", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X11Y73", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X11Y74", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X11Y75", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X11Y76", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X11Y77", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X11Y78", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X11Y79", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y8": { + "bits": {}, + "grid_x": 32, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X11Y8", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X11Y80", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X11Y81", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X11Y82", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X11Y83", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X11Y84", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X11Y85", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X11Y86", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X11Y87", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X11Y88", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X11Y89", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y9": { + "bits": {}, + "grid_x": 32, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X11Y9", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X11Y90", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X11Y91", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X11Y92", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X11Y93", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X11Y94", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X11Y95", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X11Y96", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X11Y97", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X11Y98", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X11Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400580", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 32, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X11Y99", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X12Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y0": { + "bits": {}, + "grid_x": 36, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X13Y0", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y1": { + "bits": {}, + "grid_x": 36, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X13Y1", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y10": { + "bits": {}, + "grid_x": 36, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X13Y10", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y100": { + "bits": {}, + "grid_x": 36, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X13Y100", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y101": { + "bits": {}, + "grid_x": 36, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X13Y101", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y102": { + "bits": {}, + "grid_x": 36, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X13Y102", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y103": { + "bits": {}, + "grid_x": 36, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X13Y103", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y104": { + "bits": {}, + "grid_x": 36, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X13Y104", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y105": { + "bits": {}, + "grid_x": 36, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X13Y105", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y106": { + "bits": {}, + "grid_x": 36, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X13Y106", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y107": { + "bits": {}, + "grid_x": 36, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X13Y107", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y108": { + "bits": {}, + "grid_x": 36, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X13Y108", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y109": { + "bits": {}, + "grid_x": 36, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X13Y109", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y11": { + "bits": {}, + "grid_x": 36, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X13Y11", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y110": { + "bits": {}, + "grid_x": 36, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X13Y110", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y111": { + "bits": {}, + "grid_x": 36, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X13Y111", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y112": { + "bits": {}, + "grid_x": 36, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X13Y112", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y113": { + "bits": {}, + "grid_x": 36, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X13Y113", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y114": { + "bits": {}, + "grid_x": 36, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X13Y114", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y115": { + "bits": {}, + "grid_x": 36, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X13Y115", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y116": { + "bits": {}, + "grid_x": 36, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X13Y116", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y117": { + "bits": {}, + "grid_x": 36, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X13Y117", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y118": { + "bits": {}, + "grid_x": 36, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X13Y118", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y119": { + "bits": {}, + "grid_x": 36, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X13Y119", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y12": { + "bits": {}, + "grid_x": 36, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X13Y12", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y120": { + "bits": {}, + "grid_x": 36, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X13Y120", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y121": { + "bits": {}, + "grid_x": 36, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X13Y121", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y122": { + "bits": {}, + "grid_x": 36, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X13Y122", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y123": { + "bits": {}, + "grid_x": 36, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X13Y123", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y124": { + "bits": {}, + "grid_x": 36, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X13Y124", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y125": { + "bits": {}, + "grid_x": 36, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X13Y125", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y126": { + "bits": {}, + "grid_x": 36, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X13Y126", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y127": { + "bits": {}, + "grid_x": 36, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X13Y127", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y128": { + "bits": {}, + "grid_x": 36, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X13Y128", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y129": { + "bits": {}, + "grid_x": 36, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X13Y129", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y13": { + "bits": {}, + "grid_x": 36, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X13Y13", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y130": { + "bits": {}, + "grid_x": 36, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X13Y130", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y131": { + "bits": {}, + "grid_x": 36, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X13Y131", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y132": { + "bits": {}, + "grid_x": 36, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X13Y132", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y133": { + "bits": {}, + "grid_x": 36, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X13Y133", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y134": { + "bits": {}, + "grid_x": 36, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X13Y134", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y135": { + "bits": {}, + "grid_x": 36, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X13Y135", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y136": { + "bits": {}, + "grid_x": 36, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X13Y136", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y137": { + "bits": {}, + "grid_x": 36, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X13Y137", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y138": { + "bits": {}, + "grid_x": 36, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X13Y138", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y139": { + "bits": {}, + "grid_x": 36, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X13Y139", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y14": { + "bits": {}, + "grid_x": 36, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X13Y14", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y140": { + "bits": {}, + "grid_x": 36, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X13Y140", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y141": { + "bits": {}, + "grid_x": 36, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X13Y141", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y142": { + "bits": {}, + "grid_x": 36, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X13Y142", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y143": { + "bits": {}, + "grid_x": 36, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X13Y143", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y144": { + "bits": {}, + "grid_x": 36, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X13Y144", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y145": { + "bits": {}, + "grid_x": 36, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X13Y145", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y146": { + "bits": {}, + "grid_x": 36, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X13Y146", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y147": { + "bits": {}, + "grid_x": 36, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X13Y147", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y148": { + "bits": {}, + "grid_x": 36, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X13Y148", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y149": { + "bits": {}, + "grid_x": 36, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X13Y149", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y15": { + "bits": {}, + "grid_x": 36, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X13Y15", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y150": { + "bits": {}, + "grid_x": 36, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X13Y150", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y151": { + "bits": {}, + "grid_x": 36, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X13Y151", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y152": { + "bits": {}, + "grid_x": 36, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X13Y152", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y153": { + "bits": {}, + "grid_x": 36, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X13Y153", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y154": { + "bits": {}, + "grid_x": 36, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X13Y154", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y155": { + "bits": {}, + "grid_x": 36, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X13Y155", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y156": { + "bits": {}, + "grid_x": 36, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X13Y156", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y157": { + "bits": {}, + "grid_x": 36, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X13Y157", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y158": { + "bits": {}, + "grid_x": 36, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X13Y158", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y159": { + "bits": {}, + "grid_x": 36, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X13Y159", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y16": { + "bits": {}, + "grid_x": 36, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X13Y16", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y160": { + "bits": {}, + "grid_x": 36, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X13Y160", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y161": { + "bits": {}, + "grid_x": 36, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X13Y161", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y162": { + "bits": {}, + "grid_x": 36, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X13Y162", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y163": { + "bits": {}, + "grid_x": 36, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X13Y163", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y164": { + "bits": {}, + "grid_x": 36, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X13Y164", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y165": { + "bits": {}, + "grid_x": 36, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X13Y165", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y166": { + "bits": {}, + "grid_x": 36, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X13Y166", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y167": { + "bits": {}, + "grid_x": 36, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X13Y167", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y168": { + "bits": {}, + "grid_x": 36, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X13Y168", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y169": { + "bits": {}, + "grid_x": 36, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X13Y169", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y17": { + "bits": {}, + "grid_x": 36, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X13Y17", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y170": { + "bits": {}, + "grid_x": 36, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X13Y170", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y171": { + "bits": {}, + "grid_x": 36, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X13Y171", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y172": { + "bits": {}, + "grid_x": 36, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X13Y172", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y173": { + "bits": {}, + "grid_x": 36, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X13Y173", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y174": { + "bits": {}, + "grid_x": 36, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X13Y174", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y175": { + "bits": {}, + "grid_x": 36, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X13Y175", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y176": { + "bits": {}, + "grid_x": 36, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X13Y176", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y177": { + "bits": {}, + "grid_x": 36, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X13Y177", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y178": { + "bits": {}, + "grid_x": 36, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X13Y178", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y179": { + "bits": {}, + "grid_x": 36, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X13Y179", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y18": { + "bits": {}, + "grid_x": 36, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X13Y18", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y180": { + "bits": {}, + "grid_x": 36, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X13Y180", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y181": { + "bits": {}, + "grid_x": 36, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X13Y181", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y182": { + "bits": {}, + "grid_x": 36, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X13Y182", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y183": { + "bits": {}, + "grid_x": 36, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X13Y183", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y184": { + "bits": {}, + "grid_x": 36, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X13Y184", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y185": { + "bits": {}, + "grid_x": 36, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X13Y185", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y186": { + "bits": {}, + "grid_x": 36, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X13Y186", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y187": { + "bits": {}, + "grid_x": 36, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X13Y187", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y188": { + "bits": {}, + "grid_x": 36, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X13Y188", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y189": { + "bits": {}, + "grid_x": 36, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X13Y189", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y19": { + "bits": {}, + "grid_x": 36, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X13Y19", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y190": { + "bits": {}, + "grid_x": 36, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X13Y190", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y191": { + "bits": {}, + "grid_x": 36, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X13Y191", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y192": { + "bits": {}, + "grid_x": 36, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X13Y192", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y193": { + "bits": {}, + "grid_x": 36, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X13Y193", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y194": { + "bits": {}, + "grid_x": 36, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X13Y194", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y195": { + "bits": {}, + "grid_x": 36, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X13Y195", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y196": { + "bits": {}, + "grid_x": 36, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X13Y196", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y197": { + "bits": {}, + "grid_x": 36, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X13Y197", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y198": { + "bits": {}, + "grid_x": 36, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X13Y198", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y199": { + "bits": {}, + "grid_x": 36, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X13Y199", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y2": { + "bits": {}, + "grid_x": 36, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X13Y2", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y20": { + "bits": {}, + "grid_x": 36, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X13Y20", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y21": { + "bits": {}, + "grid_x": 36, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X13Y21", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y22": { + "bits": {}, + "grid_x": 36, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X13Y22", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y23": { + "bits": {}, + "grid_x": 36, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X13Y23", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y24": { + "bits": {}, + "grid_x": 36, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X13Y24", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y25": { + "bits": {}, + "grid_x": 36, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X13Y25", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y26": { + "bits": {}, + "grid_x": 36, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X13Y26", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y27": { + "bits": {}, + "grid_x": 36, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X13Y27", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y28": { + "bits": {}, + "grid_x": 36, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X13Y28", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y29": { + "bits": {}, + "grid_x": 36, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X13Y29", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y3": { + "bits": {}, + "grid_x": 36, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X13Y3", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y30": { + "bits": {}, + "grid_x": 36, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X13Y30", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y31": { + "bits": {}, + "grid_x": 36, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X13Y31", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y32": { + "bits": {}, + "grid_x": 36, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X13Y32", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y33": { + "bits": {}, + "grid_x": 36, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X13Y33", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y34": { + "bits": {}, + "grid_x": 36, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X13Y34", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y35": { + "bits": {}, + "grid_x": 36, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X13Y35", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y36": { + "bits": {}, + "grid_x": 36, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X13Y36", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y37": { + "bits": {}, + "grid_x": 36, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X13Y37", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y38": { + "bits": {}, + "grid_x": 36, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X13Y38", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y39": { + "bits": {}, + "grid_x": 36, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X13Y39", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y4": { + "bits": {}, + "grid_x": 36, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X13Y4", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y40": { + "bits": {}, + "grid_x": 36, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X13Y40", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y41": { + "bits": {}, + "grid_x": 36, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X13Y41", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y42": { + "bits": {}, + "grid_x": 36, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X13Y42", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y43": { + "bits": {}, + "grid_x": 36, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X13Y43", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y44": { + "bits": {}, + "grid_x": 36, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X13Y44", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y45": { + "bits": {}, + "grid_x": 36, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X13Y45", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y46": { + "bits": {}, + "grid_x": 36, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X13Y46", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y47": { + "bits": {}, + "grid_x": 36, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X13Y47", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y48": { + "bits": {}, + "grid_x": 36, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X13Y48", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y49": { + "bits": {}, + "grid_x": 36, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X13Y49", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y5": { + "bits": {}, + "grid_x": 36, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X13Y5", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X13Y50", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X13Y51", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X13Y52", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X13Y53", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X13Y54", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X13Y55", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X13Y56", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X13Y57", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X13Y58", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X13Y59", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y6": { + "bits": {}, + "grid_x": 36, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X13Y6", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X13Y60", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X13Y61", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X13Y62", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X13Y63", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X13Y64", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X13Y65", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X13Y66", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X13Y67", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X13Y68", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X13Y69", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y7": { + "bits": {}, + "grid_x": 36, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X13Y7", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X13Y70", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X13Y71", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X13Y72", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X13Y73", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X13Y74", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X13Y75", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X13Y76", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X13Y77", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X13Y78", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X13Y79", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y8": { + "bits": {}, + "grid_x": 36, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X13Y8", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X13Y80", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X13Y81", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X13Y82", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X13Y83", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X13Y84", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X13Y85", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X13Y86", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X13Y87", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X13Y88", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X13Y89", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y9": { + "bits": {}, + "grid_x": 36, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X13Y9", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X13Y90", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X13Y91", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X13Y92", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X13Y93", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X13Y94", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X13Y95", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X13Y96", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X13Y97", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X13Y98", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X13Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400680", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 36, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X13Y99", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X14Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y0": { + "bits": {}, + "grid_x": 42, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X15Y0", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y1": { + "bits": {}, + "grid_x": 42, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X15Y1", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y10": { + "bits": {}, + "grid_x": 42, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X15Y10", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y100": { + "bits": {}, + "grid_x": 42, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X15Y100", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y101": { + "bits": {}, + "grid_x": 42, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X15Y101", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y102": { + "bits": {}, + "grid_x": 42, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X15Y102", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y103": { + "bits": {}, + "grid_x": 42, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X15Y103", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y104": { + "bits": {}, + "grid_x": 42, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X15Y104", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y105": { + "bits": {}, + "grid_x": 42, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X15Y105", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y106": { + "bits": {}, + "grid_x": 42, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X15Y106", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y107": { + "bits": {}, + "grid_x": 42, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X15Y107", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y108": { + "bits": {}, + "grid_x": 42, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X15Y108", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y109": { + "bits": {}, + "grid_x": 42, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X15Y109", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y11": { + "bits": {}, + "grid_x": 42, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X15Y11", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y110": { + "bits": {}, + "grid_x": 42, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X15Y110", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y111": { + "bits": {}, + "grid_x": 42, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X15Y111", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y112": { + "bits": {}, + "grid_x": 42, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X15Y112", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y113": { + "bits": {}, + "grid_x": 42, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X15Y113", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y114": { + "bits": {}, + "grid_x": 42, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X15Y114", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y115": { + "bits": {}, + "grid_x": 42, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X15Y115", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y116": { + "bits": {}, + "grid_x": 42, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X15Y116", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y117": { + "bits": {}, + "grid_x": 42, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X15Y117", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y118": { + "bits": {}, + "grid_x": 42, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X15Y118", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y119": { + "bits": {}, + "grid_x": 42, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X15Y119", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y12": { + "bits": {}, + "grid_x": 42, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X15Y12", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y120": { + "bits": {}, + "grid_x": 42, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X15Y120", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y121": { + "bits": {}, + "grid_x": 42, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X15Y121", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y122": { + "bits": {}, + "grid_x": 42, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X15Y122", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y123": { + "bits": {}, + "grid_x": 42, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X15Y123", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y124": { + "bits": {}, + "grid_x": 42, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X15Y124", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y125": { + "bits": {}, + "grid_x": 42, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X15Y125", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y126": { + "bits": {}, + "grid_x": 42, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X15Y126", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y127": { + "bits": {}, + "grid_x": 42, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X15Y127", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y128": { + "bits": {}, + "grid_x": 42, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X15Y128", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y129": { + "bits": {}, + "grid_x": 42, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X15Y129", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y13": { + "bits": {}, + "grid_x": 42, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X15Y13", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y130": { + "bits": {}, + "grid_x": 42, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X15Y130", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y131": { + "bits": {}, + "grid_x": 42, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X15Y131", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y132": { + "bits": {}, + "grid_x": 42, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X15Y132", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y133": { + "bits": {}, + "grid_x": 42, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X15Y133", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y134": { + "bits": {}, + "grid_x": 42, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X15Y134", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y135": { + "bits": {}, + "grid_x": 42, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X15Y135", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y136": { + "bits": {}, + "grid_x": 42, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X15Y136", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y137": { + "bits": {}, + "grid_x": 42, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X15Y137", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y138": { + "bits": {}, + "grid_x": 42, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X15Y138", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y139": { + "bits": {}, + "grid_x": 42, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X15Y139", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y14": { + "bits": {}, + "grid_x": 42, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X15Y14", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y140": { + "bits": {}, + "grid_x": 42, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X15Y140", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y141": { + "bits": {}, + "grid_x": 42, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X15Y141", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y142": { + "bits": {}, + "grid_x": 42, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X15Y142", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y143": { + "bits": {}, + "grid_x": 42, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X15Y143", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y144": { + "bits": {}, + "grid_x": 42, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X15Y144", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y145": { + "bits": {}, + "grid_x": 42, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X15Y145", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y146": { + "bits": {}, + "grid_x": 42, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X15Y146", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y147": { + "bits": {}, + "grid_x": 42, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X15Y147", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y148": { + "bits": {}, + "grid_x": 42, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X15Y148", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y149": { + "bits": {}, + "grid_x": 42, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X15Y149", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y15": { + "bits": {}, + "grid_x": 42, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X15Y15", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y150": { + "bits": {}, + "grid_x": 42, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X15Y150", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y151": { + "bits": {}, + "grid_x": 42, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X15Y151", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y152": { + "bits": {}, + "grid_x": 42, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X15Y152", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y153": { + "bits": {}, + "grid_x": 42, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X15Y153", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y154": { + "bits": {}, + "grid_x": 42, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X15Y154", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y155": { + "bits": {}, + "grid_x": 42, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X15Y155", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y156": { + "bits": {}, + "grid_x": 42, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X15Y156", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y157": { + "bits": {}, + "grid_x": 42, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X15Y157", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y158": { + "bits": {}, + "grid_x": 42, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X15Y158", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y159": { + "bits": {}, + "grid_x": 42, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X15Y159", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y16": { + "bits": {}, + "grid_x": 42, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X15Y16", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y160": { + "bits": {}, + "grid_x": 42, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X15Y160", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y161": { + "bits": {}, + "grid_x": 42, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X15Y161", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y162": { + "bits": {}, + "grid_x": 42, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X15Y162", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y163": { + "bits": {}, + "grid_x": 42, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X15Y163", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y164": { + "bits": {}, + "grid_x": 42, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X15Y164", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y165": { + "bits": {}, + "grid_x": 42, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X15Y165", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y166": { + "bits": {}, + "grid_x": 42, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X15Y166", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y167": { + "bits": {}, + "grid_x": 42, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X15Y167", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y168": { + "bits": {}, + "grid_x": 42, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X15Y168", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y169": { + "bits": {}, + "grid_x": 42, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X15Y169", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y17": { + "bits": {}, + "grid_x": 42, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X15Y17", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y170": { + "bits": {}, + "grid_x": 42, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X15Y170", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y171": { + "bits": {}, + "grid_x": 42, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X15Y171", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y172": { + "bits": {}, + "grid_x": 42, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X15Y172", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y173": { + "bits": {}, + "grid_x": 42, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X15Y173", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y174": { + "bits": {}, + "grid_x": 42, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X15Y174", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y175": { + "bits": {}, + "grid_x": 42, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X15Y175", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y176": { + "bits": {}, + "grid_x": 42, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X15Y176", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y177": { + "bits": {}, + "grid_x": 42, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X15Y177", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y178": { + "bits": {}, + "grid_x": 42, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X15Y178", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y179": { + "bits": {}, + "grid_x": 42, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X15Y179", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y18": { + "bits": {}, + "grid_x": 42, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X15Y18", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y180": { + "bits": {}, + "grid_x": 42, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X15Y180", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y181": { + "bits": {}, + "grid_x": 42, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X15Y181", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y182": { + "bits": {}, + "grid_x": 42, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X15Y182", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y183": { + "bits": {}, + "grid_x": 42, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X15Y183", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y184": { + "bits": {}, + "grid_x": 42, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X15Y184", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y185": { + "bits": {}, + "grid_x": 42, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X15Y185", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y186": { + "bits": {}, + "grid_x": 42, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X15Y186", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y187": { + "bits": {}, + "grid_x": 42, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X15Y187", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y188": { + "bits": {}, + "grid_x": 42, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X15Y188", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y189": { + "bits": {}, + "grid_x": 42, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X15Y189", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y19": { + "bits": {}, + "grid_x": 42, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X15Y19", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y190": { + "bits": {}, + "grid_x": 42, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X15Y190", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y191": { + "bits": {}, + "grid_x": 42, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X15Y191", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y192": { + "bits": {}, + "grid_x": 42, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X15Y192", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y193": { + "bits": {}, + "grid_x": 42, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X15Y193", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y194": { + "bits": {}, + "grid_x": 42, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X15Y194", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y195": { + "bits": {}, + "grid_x": 42, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X15Y195", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y196": { + "bits": {}, + "grid_x": 42, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X15Y196", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y197": { + "bits": {}, + "grid_x": 42, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X15Y197", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y198": { + "bits": {}, + "grid_x": 42, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X15Y198", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y199": { + "bits": {}, + "grid_x": 42, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X15Y199", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y2": { + "bits": {}, + "grid_x": 42, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X15Y2", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y20": { + "bits": {}, + "grid_x": 42, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X15Y20", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y21": { + "bits": {}, + "grid_x": 42, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X15Y21", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y22": { + "bits": {}, + "grid_x": 42, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X15Y22", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y23": { + "bits": {}, + "grid_x": 42, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X15Y23", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y24": { + "bits": {}, + "grid_x": 42, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X15Y24", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y25": { + "bits": {}, + "grid_x": 42, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X15Y25", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y26": { + "bits": {}, + "grid_x": 42, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X15Y26", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y27": { + "bits": {}, + "grid_x": 42, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X15Y27", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y28": { + "bits": {}, + "grid_x": 42, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X15Y28", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y29": { + "bits": {}, + "grid_x": 42, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X15Y29", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y3": { + "bits": {}, + "grid_x": 42, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X15Y3", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y30": { + "bits": {}, + "grid_x": 42, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X15Y30", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y31": { + "bits": {}, + "grid_x": 42, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X15Y31", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y32": { + "bits": {}, + "grid_x": 42, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X15Y32", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y33": { + "bits": {}, + "grid_x": 42, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X15Y33", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y34": { + "bits": {}, + "grid_x": 42, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X15Y34", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y35": { + "bits": {}, + "grid_x": 42, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X15Y35", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y36": { + "bits": {}, + "grid_x": 42, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X15Y36", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y37": { + "bits": {}, + "grid_x": 42, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X15Y37", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y38": { + "bits": {}, + "grid_x": 42, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X15Y38", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y39": { + "bits": {}, + "grid_x": 42, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X15Y39", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y4": { + "bits": {}, + "grid_x": 42, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X15Y4", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y40": { + "bits": {}, + "grid_x": 42, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X15Y40", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y41": { + "bits": {}, + "grid_x": 42, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X15Y41", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y42": { + "bits": {}, + "grid_x": 42, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X15Y42", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y43": { + "bits": {}, + "grid_x": 42, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X15Y43", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y44": { + "bits": {}, + "grid_x": 42, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X15Y44", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y45": { + "bits": {}, + "grid_x": 42, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X15Y45", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y46": { + "bits": {}, + "grid_x": 42, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X15Y46", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y47": { + "bits": {}, + "grid_x": 42, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X15Y47", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y48": { + "bits": {}, + "grid_x": 42, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X15Y48", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y49": { + "bits": {}, + "grid_x": 42, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X15Y49", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y5": { + "bits": {}, + "grid_x": 42, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X15Y5", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y50": { + "bits": {}, + "grid_x": 42, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X15Y50", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y51": { + "bits": {}, + "grid_x": 42, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X15Y51", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y52": { + "bits": {}, + "grid_x": 42, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X15Y52", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y53": { + "bits": {}, + "grid_x": 42, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X15Y53", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y54": { + "bits": {}, + "grid_x": 42, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X15Y54", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y55": { + "bits": {}, + "grid_x": 42, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X15Y55", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y56": { + "bits": {}, + "grid_x": 42, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X15Y56", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y57": { + "bits": {}, + "grid_x": 42, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X15Y57", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y58": { + "bits": {}, + "grid_x": 42, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X15Y58", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y59": { + "bits": {}, + "grid_x": 42, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X15Y59", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y6": { + "bits": {}, + "grid_x": 42, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X15Y6", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y60": { + "bits": {}, + "grid_x": 42, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X15Y60", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y61": { + "bits": {}, + "grid_x": 42, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X15Y61", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y62": { + "bits": {}, + "grid_x": 42, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X15Y62", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y63": { + "bits": {}, + "grid_x": 42, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X15Y63", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y64": { + "bits": {}, + "grid_x": 42, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X15Y64", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y65": { + "bits": {}, + "grid_x": 42, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X15Y65", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y66": { + "bits": {}, + "grid_x": 42, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X15Y66", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y67": { + "bits": {}, + "grid_x": 42, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X15Y67", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y68": { + "bits": {}, + "grid_x": 42, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X15Y68", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y69": { + "bits": {}, + "grid_x": 42, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X15Y69", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y7": { + "bits": {}, + "grid_x": 42, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X15Y7", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y70": { + "bits": {}, + "grid_x": 42, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X15Y70", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y71": { + "bits": {}, + "grid_x": 42, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X15Y71", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y72": { + "bits": {}, + "grid_x": 42, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X15Y72", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y73": { + "bits": {}, + "grid_x": 42, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X15Y73", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y74": { + "bits": {}, + "grid_x": 42, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X15Y74", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y75": { + "bits": {}, + "grid_x": 42, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X15Y75", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y76": { + "bits": {}, + "grid_x": 42, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X15Y76", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y77": { + "bits": {}, + "grid_x": 42, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X15Y77", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y78": { + "bits": {}, + "grid_x": 42, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X15Y78", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y79": { + "bits": {}, + "grid_x": 42, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X15Y79", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y8": { + "bits": {}, + "grid_x": 42, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X15Y8", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y80": { + "bits": {}, + "grid_x": 42, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X15Y80", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y81": { + "bits": {}, + "grid_x": 42, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X15Y81", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y82": { + "bits": {}, + "grid_x": 42, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X15Y82", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y83": { + "bits": {}, + "grid_x": 42, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X15Y83", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y84": { + "bits": {}, + "grid_x": 42, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X15Y84", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y85": { + "bits": {}, + "grid_x": 42, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X15Y85", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y86": { + "bits": {}, + "grid_x": 42, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X15Y86", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y87": { + "bits": {}, + "grid_x": 42, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X15Y87", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y88": { + "bits": {}, + "grid_x": 42, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X15Y88", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y89": { + "bits": {}, + "grid_x": 42, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X15Y89", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y9": { + "bits": {}, + "grid_x": 42, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X15Y9", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y90": { + "bits": {}, + "grid_x": 42, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X15Y90", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y91": { + "bits": {}, + "grid_x": 42, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X15Y91", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y92": { + "bits": {}, + "grid_x": 42, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X15Y92", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y93": { + "bits": {}, + "grid_x": 42, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X15Y93", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y94": { + "bits": {}, + "grid_x": 42, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X15Y94", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y95": { + "bits": {}, + "grid_x": 42, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X15Y95", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y96": { + "bits": {}, + "grid_x": 42, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X15Y96", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y97": { + "bits": {}, + "grid_x": 42, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X15Y97", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y98": { + "bits": {}, + "grid_x": 42, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X15Y98", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X15Y99": { + "bits": {}, + "grid_x": 42, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X15Y99", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X17Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y0": { + "bits": {}, + "grid_x": 46, + "grid_y": 207, + "segment": "SEG_BRAM0_R_X17Y0", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y1": { + "bits": {}, + "grid_x": 46, + "grid_y": 206, + "segment": "SEG_BRAM1_R_X17Y0", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y10": { + "bits": {}, + "grid_x": 46, + "grid_y": 197, + "segment": "SEG_BRAM0_R_X17Y10", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y100": { + "bits": {}, + "grid_x": 46, + "grid_y": 103, + "segment": "SEG_BRAM0_R_X17Y100", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y101": { + "bits": {}, + "grid_x": 46, + "grid_y": 102, + "segment": "SEG_BRAM1_R_X17Y100", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y102": { + "bits": {}, + "grid_x": 46, + "grid_y": 101, + "segment": "SEG_BRAM2_R_X17Y100", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y103": { + "bits": {}, + "grid_x": 46, + "grid_y": 100, + "segment": "SEG_BRAM3_R_X17Y100", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y104": { + "bits": {}, + "grid_x": 46, + "grid_y": 99, + "segment": "SEG_BRAM4_R_X17Y100", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y105": { + "bits": {}, + "grid_x": 46, + "grid_y": 98, + "segment": "SEG_BRAM0_R_X17Y105", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y106": { + "bits": {}, + "grid_x": 46, + "grid_y": 97, + "segment": "SEG_BRAM1_R_X17Y105", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y107": { + "bits": {}, + "grid_x": 46, + "grid_y": 96, + "segment": "SEG_BRAM2_R_X17Y105", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y108": { + "bits": {}, + "grid_x": 46, + "grid_y": 95, + "segment": "SEG_BRAM3_R_X17Y105", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y109": { + "bits": {}, + "grid_x": 46, + "grid_y": 94, + "segment": "SEG_BRAM4_R_X17Y105", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y11": { + "bits": {}, + "grid_x": 46, + "grid_y": 196, + "segment": "SEG_BRAM1_R_X17Y10", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y110": { + "bits": {}, + "grid_x": 46, + "grid_y": 93, + "segment": "SEG_BRAM0_R_X17Y110", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y111": { + "bits": {}, + "grid_x": 46, + "grid_y": 92, + "segment": "SEG_BRAM1_R_X17Y110", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y112": { + "bits": {}, + "grid_x": 46, + "grid_y": 91, + "segment": "SEG_BRAM2_R_X17Y110", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y113": { + "bits": {}, + "grid_x": 46, + "grid_y": 90, + "segment": "SEG_BRAM3_R_X17Y110", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y114": { + "bits": {}, + "grid_x": 46, + "grid_y": 89, + "segment": "SEG_BRAM4_R_X17Y110", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y115": { + "bits": {}, + "grid_x": 46, + "grid_y": 88, + "segment": "SEG_BRAM0_R_X17Y115", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y116": { + "bits": {}, + "grid_x": 46, + "grid_y": 87, + "segment": "SEG_BRAM1_R_X17Y115", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y117": { + "bits": {}, + "grid_x": 46, + "grid_y": 86, + "segment": "SEG_BRAM2_R_X17Y115", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y118": { + "bits": {}, + "grid_x": 46, + "grid_y": 85, + "segment": "SEG_BRAM3_R_X17Y115", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y119": { + "bits": {}, + "grid_x": 46, + "grid_y": 84, + "segment": "SEG_BRAM4_R_X17Y115", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y12": { + "bits": {}, + "grid_x": 46, + "grid_y": 195, + "segment": "SEG_BRAM2_R_X17Y10", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y120": { + "bits": {}, + "grid_x": 46, + "grid_y": 83, + "segment": "SEG_BRAM0_R_X17Y120", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y121": { + "bits": {}, + "grid_x": 46, + "grid_y": 82, + "segment": "SEG_BRAM1_R_X17Y120", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y122": { + "bits": {}, + "grid_x": 46, + "grid_y": 81, + "segment": "SEG_BRAM2_R_X17Y120", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y123": { + "bits": {}, + "grid_x": 46, + "grid_y": 80, + "segment": "SEG_BRAM3_R_X17Y120", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y124": { + "bits": {}, + "grid_x": 46, + "grid_y": 79, + "segment": "SEG_BRAM4_R_X17Y120", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y125": { + "bits": {}, + "grid_x": 46, + "grid_y": 77, + "segment": "SEG_BRAM0_R_X17Y125", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y126": { + "bits": {}, + "grid_x": 46, + "grid_y": 76, + "segment": "SEG_BRAM1_R_X17Y125", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y127": { + "bits": {}, + "grid_x": 46, + "grid_y": 75, + "segment": "SEG_BRAM2_R_X17Y125", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y128": { + "bits": {}, + "grid_x": 46, + "grid_y": 74, + "segment": "SEG_BRAM3_R_X17Y125", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y129": { + "bits": {}, + "grid_x": 46, + "grid_y": 73, + "segment": "SEG_BRAM4_R_X17Y125", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y13": { + "bits": {}, + "grid_x": 46, + "grid_y": 194, + "segment": "SEG_BRAM3_R_X17Y10", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y130": { + "bits": {}, + "grid_x": 46, + "grid_y": 72, + "segment": "SEG_BRAM0_R_X17Y130", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y131": { + "bits": {}, + "grid_x": 46, + "grid_y": 71, + "segment": "SEG_BRAM1_R_X17Y130", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y132": { + "bits": {}, + "grid_x": 46, + "grid_y": 70, + "segment": "SEG_BRAM2_R_X17Y130", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y133": { + "bits": {}, + "grid_x": 46, + "grid_y": 69, + "segment": "SEG_BRAM3_R_X17Y130", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y134": { + "bits": {}, + "grid_x": 46, + "grid_y": 68, + "segment": "SEG_BRAM4_R_X17Y130", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y135": { + "bits": {}, + "grid_x": 46, + "grid_y": 67, + "segment": "SEG_BRAM0_R_X17Y135", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y136": { + "bits": {}, + "grid_x": 46, + "grid_y": 66, + "segment": "SEG_BRAM1_R_X17Y135", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y137": { + "bits": {}, + "grid_x": 46, + "grid_y": 65, + "segment": "SEG_BRAM2_R_X17Y135", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y138": { + "bits": {}, + "grid_x": 46, + "grid_y": 64, + "segment": "SEG_BRAM3_R_X17Y135", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y139": { + "bits": {}, + "grid_x": 46, + "grid_y": 63, + "segment": "SEG_BRAM4_R_X17Y135", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y14": { + "bits": {}, + "grid_x": 46, + "grid_y": 193, + "segment": "SEG_BRAM4_R_X17Y10", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y140": { + "bits": {}, + "grid_x": 46, + "grid_y": 62, + "segment": "SEG_BRAM0_R_X17Y140", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y141": { + "bits": {}, + "grid_x": 46, + "grid_y": 61, + "segment": "SEG_BRAM1_R_X17Y140", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y142": { + "bits": {}, + "grid_x": 46, + "grid_y": 60, + "segment": "SEG_BRAM2_R_X17Y140", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y143": { + "bits": {}, + "grid_x": 46, + "grid_y": 59, + "segment": "SEG_BRAM3_R_X17Y140", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y144": { + "bits": {}, + "grid_x": 46, + "grid_y": 58, + "segment": "SEG_BRAM4_R_X17Y140", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y145": { + "bits": {}, + "grid_x": 46, + "grid_y": 57, + "segment": "SEG_BRAM0_R_X17Y145", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y146": { + "bits": {}, + "grid_x": 46, + "grid_y": 56, + "segment": "SEG_BRAM1_R_X17Y145", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y147": { + "bits": {}, + "grid_x": 46, + "grid_y": 55, + "segment": "SEG_BRAM2_R_X17Y145", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y148": { + "bits": {}, + "grid_x": 46, + "grid_y": 54, + "segment": "SEG_BRAM3_R_X17Y145", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y149": { + "bits": {}, + "grid_x": 46, + "grid_y": 53, + "segment": "SEG_BRAM4_R_X17Y145", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y15": { + "bits": {}, + "grid_x": 46, + "grid_y": 192, + "segment": "SEG_BRAM0_R_X17Y15", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y150": { + "bits": {}, + "grid_x": 46, + "grid_y": 51, + "segment": "SEG_BRAM0_R_X17Y150", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y151": { + "bits": {}, + "grid_x": 46, + "grid_y": 50, + "segment": "SEG_BRAM1_R_X17Y150", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y152": { + "bits": {}, + "grid_x": 46, + "grid_y": 49, + "segment": "SEG_BRAM2_R_X17Y150", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y153": { + "bits": {}, + "grid_x": 46, + "grid_y": 48, + "segment": "SEG_BRAM3_R_X17Y150", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y154": { + "bits": {}, + "grid_x": 46, + "grid_y": 47, + "segment": "SEG_BRAM4_R_X17Y150", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y155": { + "bits": {}, + "grid_x": 46, + "grid_y": 46, + "segment": "SEG_BRAM0_R_X17Y155", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y156": { + "bits": {}, + "grid_x": 46, + "grid_y": 45, + "segment": "SEG_BRAM1_R_X17Y155", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y157": { + "bits": {}, + "grid_x": 46, + "grid_y": 44, + "segment": "SEG_BRAM2_R_X17Y155", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y158": { + "bits": {}, + "grid_x": 46, + "grid_y": 43, + "segment": "SEG_BRAM3_R_X17Y155", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y159": { + "bits": {}, + "grid_x": 46, + "grid_y": 42, + "segment": "SEG_BRAM4_R_X17Y155", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y16": { + "bits": {}, + "grid_x": 46, + "grid_y": 191, + "segment": "SEG_BRAM1_R_X17Y15", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y160": { + "bits": {}, + "grid_x": 46, + "grid_y": 41, + "segment": "SEG_BRAM0_R_X17Y160", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y161": { + "bits": {}, + "grid_x": 46, + "grid_y": 40, + "segment": "SEG_BRAM1_R_X17Y160", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y162": { + "bits": {}, + "grid_x": 46, + "grid_y": 39, + "segment": "SEG_BRAM2_R_X17Y160", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y163": { + "bits": {}, + "grid_x": 46, + "grid_y": 38, + "segment": "SEG_BRAM3_R_X17Y160", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y164": { + "bits": {}, + "grid_x": 46, + "grid_y": 37, + "segment": "SEG_BRAM4_R_X17Y160", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y165": { + "bits": {}, + "grid_x": 46, + "grid_y": 36, + "segment": "SEG_BRAM0_R_X17Y165", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y166": { + "bits": {}, + "grid_x": 46, + "grid_y": 35, + "segment": "SEG_BRAM1_R_X17Y165", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y167": { + "bits": {}, + "grid_x": 46, + "grid_y": 34, + "segment": "SEG_BRAM2_R_X17Y165", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y168": { + "bits": {}, + "grid_x": 46, + "grid_y": 33, + "segment": "SEG_BRAM3_R_X17Y165", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y169": { + "bits": {}, + "grid_x": 46, + "grid_y": 32, + "segment": "SEG_BRAM4_R_X17Y165", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y17": { + "bits": {}, + "grid_x": 46, + "grid_y": 190, + "segment": "SEG_BRAM2_R_X17Y15", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y170": { + "bits": {}, + "grid_x": 46, + "grid_y": 31, + "segment": "SEG_BRAM0_R_X17Y170", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y171": { + "bits": {}, + "grid_x": 46, + "grid_y": 30, + "segment": "SEG_BRAM1_R_X17Y170", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y172": { + "bits": {}, + "grid_x": 46, + "grid_y": 29, + "segment": "SEG_BRAM2_R_X17Y170", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y173": { + "bits": {}, + "grid_x": 46, + "grid_y": 28, + "segment": "SEG_BRAM3_R_X17Y170", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y174": { + "bits": {}, + "grid_x": 46, + "grid_y": 27, + "segment": "SEG_BRAM4_R_X17Y170", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y175": { + "bits": {}, + "grid_x": 46, + "grid_y": 25, + "segment": "SEG_BRAM0_R_X17Y175", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y176": { + "bits": {}, + "grid_x": 46, + "grid_y": 24, + "segment": "SEG_BRAM1_R_X17Y175", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y177": { + "bits": {}, + "grid_x": 46, + "grid_y": 23, + "segment": "SEG_BRAM2_R_X17Y175", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y178": { + "bits": {}, + "grid_x": 46, + "grid_y": 22, + "segment": "SEG_BRAM3_R_X17Y175", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y179": { + "bits": {}, + "grid_x": 46, + "grid_y": 21, + "segment": "SEG_BRAM4_R_X17Y175", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y18": { + "bits": {}, + "grid_x": 46, + "grid_y": 189, + "segment": "SEG_BRAM3_R_X17Y15", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y180": { + "bits": {}, + "grid_x": 46, + "grid_y": 20, + "segment": "SEG_BRAM0_R_X17Y180", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y181": { + "bits": {}, + "grid_x": 46, + "grid_y": 19, + "segment": "SEG_BRAM1_R_X17Y180", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y182": { + "bits": {}, + "grid_x": 46, + "grid_y": 18, + "segment": "SEG_BRAM2_R_X17Y180", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y183": { + "bits": {}, + "grid_x": 46, + "grid_y": 17, + "segment": "SEG_BRAM3_R_X17Y180", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y184": { + "bits": {}, + "grid_x": 46, + "grid_y": 16, + "segment": "SEG_BRAM4_R_X17Y180", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y185": { + "bits": {}, + "grid_x": 46, + "grid_y": 15, + "segment": "SEG_BRAM0_R_X17Y185", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y186": { + "bits": {}, + "grid_x": 46, + "grid_y": 14, + "segment": "SEG_BRAM1_R_X17Y185", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y187": { + "bits": {}, + "grid_x": 46, + "grid_y": 13, + "segment": "SEG_BRAM2_R_X17Y185", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y188": { + "bits": {}, + "grid_x": 46, + "grid_y": 12, + "segment": "SEG_BRAM3_R_X17Y185", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y189": { + "bits": {}, + "grid_x": 46, + "grid_y": 11, + "segment": "SEG_BRAM4_R_X17Y185", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y19": { + "bits": {}, + "grid_x": 46, + "grid_y": 188, + "segment": "SEG_BRAM4_R_X17Y15", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y190": { + "bits": {}, + "grid_x": 46, + "grid_y": 10, + "segment": "SEG_BRAM0_R_X17Y190", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y191": { + "bits": {}, + "grid_x": 46, + "grid_y": 9, + "segment": "SEG_BRAM1_R_X17Y190", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y192": { + "bits": {}, + "grid_x": 46, + "grid_y": 8, + "segment": "SEG_BRAM2_R_X17Y190", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y193": { + "bits": {}, + "grid_x": 46, + "grid_y": 7, + "segment": "SEG_BRAM3_R_X17Y190", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y194": { + "bits": {}, + "grid_x": 46, + "grid_y": 6, + "segment": "SEG_BRAM4_R_X17Y190", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y195": { + "bits": {}, + "grid_x": 46, + "grid_y": 5, + "segment": "SEG_BRAM0_R_X17Y195", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y196": { + "bits": {}, + "grid_x": 46, + "grid_y": 4, + "segment": "SEG_BRAM1_R_X17Y195", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y197": { + "bits": {}, + "grid_x": 46, + "grid_y": 3, + "segment": "SEG_BRAM2_R_X17Y195", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y198": { + "bits": {}, + "grid_x": 46, + "grid_y": 2, + "segment": "SEG_BRAM3_R_X17Y195", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y199": { + "bits": {}, + "grid_x": 46, + "grid_y": 1, + "segment": "SEG_BRAM4_R_X17Y195", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y2": { + "bits": {}, + "grid_x": 46, + "grid_y": 205, + "segment": "SEG_BRAM2_R_X17Y0", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y20": { + "bits": {}, + "grid_x": 46, + "grid_y": 187, + "segment": "SEG_BRAM0_R_X17Y20", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y21": { + "bits": {}, + "grid_x": 46, + "grid_y": 186, + "segment": "SEG_BRAM1_R_X17Y20", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y22": { + "bits": {}, + "grid_x": 46, + "grid_y": 185, + "segment": "SEG_BRAM2_R_X17Y20", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y23": { + "bits": {}, + "grid_x": 46, + "grid_y": 184, + "segment": "SEG_BRAM3_R_X17Y20", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y24": { + "bits": {}, + "grid_x": 46, + "grid_y": 183, + "segment": "SEG_BRAM4_R_X17Y20", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y25": { + "bits": {}, + "grid_x": 46, + "grid_y": 181, + "segment": "SEG_BRAM0_R_X17Y25", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y26": { + "bits": {}, + "grid_x": 46, + "grid_y": 180, + "segment": "SEG_BRAM1_R_X17Y25", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y27": { + "bits": {}, + "grid_x": 46, + "grid_y": 179, + "segment": "SEG_BRAM2_R_X17Y25", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y28": { + "bits": {}, + "grid_x": 46, + "grid_y": 178, + "segment": "SEG_BRAM3_R_X17Y25", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y29": { + "bits": {}, + "grid_x": 46, + "grid_y": 177, + "segment": "SEG_BRAM4_R_X17Y25", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y3": { + "bits": {}, + "grid_x": 46, + "grid_y": 204, + "segment": "SEG_BRAM3_R_X17Y0", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y30": { + "bits": {}, + "grid_x": 46, + "grid_y": 176, + "segment": "SEG_BRAM0_R_X17Y30", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y31": { + "bits": {}, + "grid_x": 46, + "grid_y": 175, + "segment": "SEG_BRAM1_R_X17Y30", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y32": { + "bits": {}, + "grid_x": 46, + "grid_y": 174, + "segment": "SEG_BRAM2_R_X17Y30", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y33": { + "bits": {}, + "grid_x": 46, + "grid_y": 173, + "segment": "SEG_BRAM3_R_X17Y30", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y34": { + "bits": {}, + "grid_x": 46, + "grid_y": 172, + "segment": "SEG_BRAM4_R_X17Y30", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y35": { + "bits": {}, + "grid_x": 46, + "grid_y": 171, + "segment": "SEG_BRAM0_R_X17Y35", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y36": { + "bits": {}, + "grid_x": 46, + "grid_y": 170, + "segment": "SEG_BRAM1_R_X17Y35", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y37": { + "bits": {}, + "grid_x": 46, + "grid_y": 169, + "segment": "SEG_BRAM2_R_X17Y35", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y38": { + "bits": {}, + "grid_x": 46, + "grid_y": 168, + "segment": "SEG_BRAM3_R_X17Y35", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y39": { + "bits": {}, + "grid_x": 46, + "grid_y": 167, + "segment": "SEG_BRAM4_R_X17Y35", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y4": { + "bits": {}, + "grid_x": 46, + "grid_y": 203, + "segment": "SEG_BRAM4_R_X17Y0", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y40": { + "bits": {}, + "grid_x": 46, + "grid_y": 166, + "segment": "SEG_BRAM0_R_X17Y40", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y41": { + "bits": {}, + "grid_x": 46, + "grid_y": 165, + "segment": "SEG_BRAM1_R_X17Y40", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y42": { + "bits": {}, + "grid_x": 46, + "grid_y": 164, + "segment": "SEG_BRAM2_R_X17Y40", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y43": { + "bits": {}, + "grid_x": 46, + "grid_y": 163, + "segment": "SEG_BRAM3_R_X17Y40", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y44": { + "bits": {}, + "grid_x": 46, + "grid_y": 162, + "segment": "SEG_BRAM4_R_X17Y40", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y45": { + "bits": {}, + "grid_x": 46, + "grid_y": 161, + "segment": "SEG_BRAM0_R_X17Y45", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y46": { + "bits": {}, + "grid_x": 46, + "grid_y": 160, + "segment": "SEG_BRAM1_R_X17Y45", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y47": { + "bits": {}, + "grid_x": 46, + "grid_y": 159, + "segment": "SEG_BRAM2_R_X17Y45", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y48": { + "bits": {}, + "grid_x": 46, + "grid_y": 158, + "segment": "SEG_BRAM3_R_X17Y45", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y49": { + "bits": {}, + "grid_x": 46, + "grid_y": 157, + "segment": "SEG_BRAM4_R_X17Y45", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y5": { + "bits": {}, + "grid_x": 46, + "grid_y": 202, + "segment": "SEG_BRAM0_R_X17Y5", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y50": { + "bits": {}, + "grid_x": 46, + "grid_y": 155, + "segment": "SEG_BRAM0_R_X17Y50", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y51": { + "bits": {}, + "grid_x": 46, + "grid_y": 154, + "segment": "SEG_BRAM1_R_X17Y50", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y52": { + "bits": {}, + "grid_x": 46, + "grid_y": 153, + "segment": "SEG_BRAM2_R_X17Y50", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y53": { + "bits": {}, + "grid_x": 46, + "grid_y": 152, + "segment": "SEG_BRAM3_R_X17Y50", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y54": { + "bits": {}, + "grid_x": 46, + "grid_y": 151, + "segment": "SEG_BRAM4_R_X17Y50", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y55": { + "bits": {}, + "grid_x": 46, + "grid_y": 150, + "segment": "SEG_BRAM0_R_X17Y55", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y56": { + "bits": {}, + "grid_x": 46, + "grid_y": 149, + "segment": "SEG_BRAM1_R_X17Y55", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y57": { + "bits": {}, + "grid_x": 46, + "grid_y": 148, + "segment": "SEG_BRAM2_R_X17Y55", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y58": { + "bits": {}, + "grid_x": 46, + "grid_y": 147, + "segment": "SEG_BRAM3_R_X17Y55", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y59": { + "bits": {}, + "grid_x": 46, + "grid_y": 146, + "segment": "SEG_BRAM4_R_X17Y55", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y6": { + "bits": {}, + "grid_x": 46, + "grid_y": 201, + "segment": "SEG_BRAM1_R_X17Y5", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y60": { + "bits": {}, + "grid_x": 46, + "grid_y": 145, + "segment": "SEG_BRAM0_R_X17Y60", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y61": { + "bits": {}, + "grid_x": 46, + "grid_y": 144, + "segment": "SEG_BRAM1_R_X17Y60", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y62": { + "bits": {}, + "grid_x": 46, + "grid_y": 143, + "segment": "SEG_BRAM2_R_X17Y60", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y63": { + "bits": {}, + "grid_x": 46, + "grid_y": 142, + "segment": "SEG_BRAM3_R_X17Y60", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y64": { + "bits": {}, + "grid_x": 46, + "grid_y": 141, + "segment": "SEG_BRAM4_R_X17Y60", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y65": { + "bits": {}, + "grid_x": 46, + "grid_y": 140, + "segment": "SEG_BRAM0_R_X17Y65", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y66": { + "bits": {}, + "grid_x": 46, + "grid_y": 139, + "segment": "SEG_BRAM1_R_X17Y65", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y67": { + "bits": {}, + "grid_x": 46, + "grid_y": 138, + "segment": "SEG_BRAM2_R_X17Y65", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y68": { + "bits": {}, + "grid_x": 46, + "grid_y": 137, + "segment": "SEG_BRAM3_R_X17Y65", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y69": { + "bits": {}, + "grid_x": 46, + "grid_y": 136, + "segment": "SEG_BRAM4_R_X17Y65", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y7": { + "bits": {}, + "grid_x": 46, + "grid_y": 200, + "segment": "SEG_BRAM2_R_X17Y5", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y70": { + "bits": {}, + "grid_x": 46, + "grid_y": 135, + "segment": "SEG_BRAM0_R_X17Y70", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y71": { + "bits": {}, + "grid_x": 46, + "grid_y": 134, + "segment": "SEG_BRAM1_R_X17Y70", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y72": { + "bits": {}, + "grid_x": 46, + "grid_y": 133, + "segment": "SEG_BRAM2_R_X17Y70", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y73": { + "bits": {}, + "grid_x": 46, + "grid_y": 132, + "segment": "SEG_BRAM3_R_X17Y70", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y74": { + "bits": {}, + "grid_x": 46, + "grid_y": 131, + "segment": "SEG_BRAM4_R_X17Y70", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y75": { + "bits": {}, + "grid_x": 46, + "grid_y": 129, + "segment": "SEG_BRAM0_R_X17Y75", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y76": { + "bits": {}, + "grid_x": 46, + "grid_y": 128, + "segment": "SEG_BRAM1_R_X17Y75", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y77": { + "bits": {}, + "grid_x": 46, + "grid_y": 127, + "segment": "SEG_BRAM2_R_X17Y75", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y78": { + "bits": {}, + "grid_x": 46, + "grid_y": 126, + "segment": "SEG_BRAM3_R_X17Y75", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y79": { + "bits": {}, + "grid_x": 46, + "grid_y": 125, + "segment": "SEG_BRAM4_R_X17Y75", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y8": { + "bits": {}, + "grid_x": 46, + "grid_y": 199, + "segment": "SEG_BRAM3_R_X17Y5", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y80": { + "bits": {}, + "grid_x": 46, + "grid_y": 124, + "segment": "SEG_BRAM0_R_X17Y80", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y81": { + "bits": {}, + "grid_x": 46, + "grid_y": 123, + "segment": "SEG_BRAM1_R_X17Y80", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y82": { + "bits": {}, + "grid_x": 46, + "grid_y": 122, + "segment": "SEG_BRAM2_R_X17Y80", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y83": { + "bits": {}, + "grid_x": 46, + "grid_y": 121, + "segment": "SEG_BRAM3_R_X17Y80", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y84": { + "bits": {}, + "grid_x": 46, + "grid_y": 120, + "segment": "SEG_BRAM4_R_X17Y80", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y85": { + "bits": {}, + "grid_x": 46, + "grid_y": 119, + "segment": "SEG_BRAM0_R_X17Y85", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y86": { + "bits": {}, + "grid_x": 46, + "grid_y": 118, + "segment": "SEG_BRAM1_R_X17Y85", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y87": { + "bits": {}, + "grid_x": 46, + "grid_y": 117, + "segment": "SEG_BRAM2_R_X17Y85", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y88": { + "bits": {}, + "grid_x": 46, + "grid_y": 116, + "segment": "SEG_BRAM3_R_X17Y85", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y89": { + "bits": {}, + "grid_x": 46, + "grid_y": 115, + "segment": "SEG_BRAM4_R_X17Y85", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y9": { + "bits": {}, + "grid_x": 46, + "grid_y": 198, + "segment": "SEG_BRAM4_R_X17Y5", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y90": { + "bits": {}, + "grid_x": 46, + "grid_y": 114, + "segment": "SEG_BRAM0_R_X17Y90", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y91": { + "bits": {}, + "grid_x": 46, + "grid_y": 113, + "segment": "SEG_BRAM1_R_X17Y90", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y92": { + "bits": {}, + "grid_x": 46, + "grid_y": 112, + "segment": "SEG_BRAM2_R_X17Y90", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y93": { + "bits": {}, + "grid_x": 46, + "grid_y": 111, + "segment": "SEG_BRAM3_R_X17Y90", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y94": { + "bits": {}, + "grid_x": 46, + "grid_y": 110, + "segment": "SEG_BRAM4_R_X17Y90", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y95": { + "bits": {}, + "grid_x": 46, + "grid_y": 109, + "segment": "SEG_BRAM0_R_X17Y95", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X19Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y96": { + "bits": {}, + "grid_x": 46, + "grid_y": 108, + "segment": "SEG_BRAM1_R_X17Y95", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X19Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y97": { + "bits": {}, + "grid_x": 46, + "grid_y": 107, + "segment": "SEG_BRAM2_R_X17Y95", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X19Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y98": { + "bits": {}, + "grid_x": 46, + "grid_y": 106, + "segment": "SEG_BRAM3_R_X17Y95", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X19Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X17Y99": { + "bits": {}, + "grid_x": 46, + "grid_y": 105, + "segment": "SEG_BRAM4_R_X17Y95", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X19Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y0": { + "bits": {}, + "grid_x": 52, + "grid_y": 207, + "segment": "SEG_CLBLL_R_X19Y0", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y1": { + "bits": {}, + "grid_x": 52, + "grid_y": 206, + "segment": "SEG_CLBLL_R_X19Y1", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y10": { + "bits": {}, + "grid_x": 52, + "grid_y": 197, + "segment": "SEG_CLBLL_R_X19Y10", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y11": { + "bits": {}, + "grid_x": 52, + "grid_y": 196, + "segment": "SEG_CLBLL_R_X19Y11", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y12": { + "bits": {}, + "grid_x": 52, + "grid_y": 195, + "segment": "SEG_CLBLL_R_X19Y12", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y13": { + "bits": {}, + "grid_x": 52, + "grid_y": 194, + "segment": "SEG_CLBLL_R_X19Y13", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y14": { + "bits": {}, + "grid_x": 52, + "grid_y": 193, + "segment": "SEG_CLBLL_R_X19Y14", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y15": { + "bits": {}, + "grid_x": 52, + "grid_y": 192, + "segment": "SEG_CLBLL_R_X19Y15", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y150": { + "bits": {}, + "grid_x": 52, + "grid_y": 51, + "segment": "SEG_CLBLL_R_X19Y150", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y151": { + "bits": {}, + "grid_x": 52, + "grid_y": 50, + "segment": "SEG_CLBLL_R_X19Y151", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y152": { + "bits": {}, + "grid_x": 52, + "grid_y": 49, + "segment": "SEG_CLBLL_R_X19Y152", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y153": { + "bits": {}, + "grid_x": 52, + "grid_y": 48, + "segment": "SEG_CLBLL_R_X19Y153", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y154": { + "bits": {}, + "grid_x": 52, + "grid_y": 47, + "segment": "SEG_CLBLL_R_X19Y154", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y155": { + "bits": {}, + "grid_x": 52, + "grid_y": 46, + "segment": "SEG_CLBLL_R_X19Y155", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y156": { + "bits": {}, + "grid_x": 52, + "grid_y": 45, + "segment": "SEG_CLBLL_R_X19Y156", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y157": { + "bits": {}, + "grid_x": 52, + "grid_y": 44, + "segment": "SEG_CLBLL_R_X19Y157", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y158": { + "bits": {}, + "grid_x": 52, + "grid_y": 43, + "segment": "SEG_CLBLL_R_X19Y158", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y159": { + "bits": {}, + "grid_x": 52, + "grid_y": 42, + "segment": "SEG_CLBLL_R_X19Y159", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y16": { + "bits": {}, + "grid_x": 52, + "grid_y": 191, + "segment": "SEG_CLBLL_R_X19Y16", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y160": { + "bits": {}, + "grid_x": 52, + "grid_y": 41, + "segment": "SEG_CLBLL_R_X19Y160", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y161": { + "bits": {}, + "grid_x": 52, + "grid_y": 40, + "segment": "SEG_CLBLL_R_X19Y161", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y162": { + "bits": {}, + "grid_x": 52, + "grid_y": 39, + "segment": "SEG_CLBLL_R_X19Y162", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y163": { + "bits": {}, + "grid_x": 52, + "grid_y": 38, + "segment": "SEG_CLBLL_R_X19Y163", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y164": { + "bits": {}, + "grid_x": 52, + "grid_y": 37, + "segment": "SEG_CLBLL_R_X19Y164", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y165": { + "bits": {}, + "grid_x": 52, + "grid_y": 36, + "segment": "SEG_CLBLL_R_X19Y165", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y166": { + "bits": {}, + "grid_x": 52, + "grid_y": 35, + "segment": "SEG_CLBLL_R_X19Y166", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y167": { + "bits": {}, + "grid_x": 52, + "grid_y": 34, + "segment": "SEG_CLBLL_R_X19Y167", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y168": { + "bits": {}, + "grid_x": 52, + "grid_y": 33, + "segment": "SEG_CLBLL_R_X19Y168", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y169": { + "bits": {}, + "grid_x": 52, + "grid_y": 32, + "segment": "SEG_CLBLL_R_X19Y169", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y17": { + "bits": {}, + "grid_x": 52, + "grid_y": 190, + "segment": "SEG_CLBLL_R_X19Y17", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y170": { + "bits": {}, + "grid_x": 52, + "grid_y": 31, + "segment": "SEG_CLBLL_R_X19Y170", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y171": { + "bits": {}, + "grid_x": 52, + "grid_y": 30, + "segment": "SEG_CLBLL_R_X19Y171", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y172": { + "bits": {}, + "grid_x": 52, + "grid_y": 29, + "segment": "SEG_CLBLL_R_X19Y172", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y173": { + "bits": {}, + "grid_x": 52, + "grid_y": 28, + "segment": "SEG_CLBLL_R_X19Y173", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y174": { + "bits": {}, + "grid_x": 52, + "grid_y": 27, + "segment": "SEG_CLBLL_R_X19Y174", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y175": { + "bits": {}, + "grid_x": 52, + "grid_y": 25, + "segment": "SEG_CLBLL_R_X19Y175", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y176": { + "bits": {}, + "grid_x": 52, + "grid_y": 24, + "segment": "SEG_CLBLL_R_X19Y176", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y177": { + "bits": {}, + "grid_x": 52, + "grid_y": 23, + "segment": "SEG_CLBLL_R_X19Y177", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y178": { + "bits": {}, + "grid_x": 52, + "grid_y": 22, + "segment": "SEG_CLBLL_R_X19Y178", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y179": { + "bits": {}, + "grid_x": 52, + "grid_y": 21, + "segment": "SEG_CLBLL_R_X19Y179", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y18": { + "bits": {}, + "grid_x": 52, + "grid_y": 189, + "segment": "SEG_CLBLL_R_X19Y18", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y180": { + "bits": {}, + "grid_x": 52, + "grid_y": 20, + "segment": "SEG_CLBLL_R_X19Y180", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y181": { + "bits": {}, + "grid_x": 52, + "grid_y": 19, + "segment": "SEG_CLBLL_R_X19Y181", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y182": { + "bits": {}, + "grid_x": 52, + "grid_y": 18, + "segment": "SEG_CLBLL_R_X19Y182", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y183": { + "bits": {}, + "grid_x": 52, + "grid_y": 17, + "segment": "SEG_CLBLL_R_X19Y183", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y184": { + "bits": {}, + "grid_x": 52, + "grid_y": 16, + "segment": "SEG_CLBLL_R_X19Y184", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y185": { + "bits": {}, + "grid_x": 52, + "grid_y": 15, + "segment": "SEG_CLBLL_R_X19Y185", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y186": { + "bits": {}, + "grid_x": 52, + "grid_y": 14, + "segment": "SEG_CLBLL_R_X19Y186", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y187": { + "bits": {}, + "grid_x": 52, + "grid_y": 13, + "segment": "SEG_CLBLL_R_X19Y187", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y188": { + "bits": {}, + "grid_x": 52, + "grid_y": 12, + "segment": "SEG_CLBLL_R_X19Y188", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y189": { + "bits": {}, + "grid_x": 52, + "grid_y": 11, + "segment": "SEG_CLBLL_R_X19Y189", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y19": { + "bits": {}, + "grid_x": 52, + "grid_y": 188, + "segment": "SEG_CLBLL_R_X19Y19", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y190": { + "bits": {}, + "grid_x": 52, + "grid_y": 10, + "segment": "SEG_CLBLL_R_X19Y190", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y191": { + "bits": {}, + "grid_x": 52, + "grid_y": 9, + "segment": "SEG_CLBLL_R_X19Y191", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y192": { + "bits": {}, + "grid_x": 52, + "grid_y": 8, + "segment": "SEG_CLBLL_R_X19Y192", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y193": { + "bits": {}, + "grid_x": 52, + "grid_y": 7, + "segment": "SEG_CLBLL_R_X19Y193", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y194": { + "bits": {}, + "grid_x": 52, + "grid_y": 6, + "segment": "SEG_CLBLL_R_X19Y194", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y195": { + "bits": {}, + "grid_x": 52, + "grid_y": 5, + "segment": "SEG_CLBLL_R_X19Y195", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y196": { + "bits": {}, + "grid_x": 52, + "grid_y": 4, + "segment": "SEG_CLBLL_R_X19Y196", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y197": { + "bits": {}, + "grid_x": 52, + "grid_y": 3, + "segment": "SEG_CLBLL_R_X19Y197", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y198": { + "bits": {}, + "grid_x": 52, + "grid_y": 2, + "segment": "SEG_CLBLL_R_X19Y198", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y199": { + "bits": {}, + "grid_x": 52, + "grid_y": 1, + "segment": "SEG_CLBLL_R_X19Y199", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y2": { + "bits": {}, + "grid_x": 52, + "grid_y": 205, + "segment": "SEG_CLBLL_R_X19Y2", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y20": { + "bits": {}, + "grid_x": 52, + "grid_y": 187, + "segment": "SEG_CLBLL_R_X19Y20", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y21": { + "bits": {}, + "grid_x": 52, + "grid_y": 186, + "segment": "SEG_CLBLL_R_X19Y21", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y22": { + "bits": {}, + "grid_x": 52, + "grid_y": 185, + "segment": "SEG_CLBLL_R_X19Y22", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y23": { + "bits": {}, + "grid_x": 52, + "grid_y": 184, + "segment": "SEG_CLBLL_R_X19Y23", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y24": { + "bits": {}, + "grid_x": 52, + "grid_y": 183, + "segment": "SEG_CLBLL_R_X19Y24", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y25": { + "bits": {}, + "grid_x": 52, + "grid_y": 181, + "segment": "SEG_CLBLL_R_X19Y25", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y26": { + "bits": {}, + "grid_x": 52, + "grid_y": 180, + "segment": "SEG_CLBLL_R_X19Y26", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y27": { + "bits": {}, + "grid_x": 52, + "grid_y": 179, + "segment": "SEG_CLBLL_R_X19Y27", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y28": { + "bits": {}, + "grid_x": 52, + "grid_y": 178, + "segment": "SEG_CLBLL_R_X19Y28", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y29": { + "bits": {}, + "grid_x": 52, + "grid_y": 177, + "segment": "SEG_CLBLL_R_X19Y29", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y3": { + "bits": {}, + "grid_x": 52, + "grid_y": 204, + "segment": "SEG_CLBLL_R_X19Y3", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y30": { + "bits": {}, + "grid_x": 52, + "grid_y": 176, + "segment": "SEG_CLBLL_R_X19Y30", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y31": { + "bits": {}, + "grid_x": 52, + "grid_y": 175, + "segment": "SEG_CLBLL_R_X19Y31", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y32": { + "bits": {}, + "grid_x": 52, + "grid_y": 174, + "segment": "SEG_CLBLL_R_X19Y32", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y33": { + "bits": {}, + "grid_x": 52, + "grid_y": 173, + "segment": "SEG_CLBLL_R_X19Y33", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y34": { + "bits": {}, + "grid_x": 52, + "grid_y": 172, + "segment": "SEG_CLBLL_R_X19Y34", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y35": { + "bits": {}, + "grid_x": 52, + "grid_y": 171, + "segment": "SEG_CLBLL_R_X19Y35", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y36": { + "bits": {}, + "grid_x": 52, + "grid_y": 170, + "segment": "SEG_CLBLL_R_X19Y36", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y37": { + "bits": {}, + "grid_x": 52, + "grid_y": 169, + "segment": "SEG_CLBLL_R_X19Y37", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y38": { + "bits": {}, + "grid_x": 52, + "grid_y": 168, + "segment": "SEG_CLBLL_R_X19Y38", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y39": { + "bits": {}, + "grid_x": 52, + "grid_y": 167, + "segment": "SEG_CLBLL_R_X19Y39", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y4": { + "bits": {}, + "grid_x": 52, + "grid_y": 203, + "segment": "SEG_CLBLL_R_X19Y4", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y40": { + "bits": {}, + "grid_x": 52, + "grid_y": 166, + "segment": "SEG_CLBLL_R_X19Y40", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y41": { + "bits": {}, + "grid_x": 52, + "grid_y": 165, + "segment": "SEG_CLBLL_R_X19Y41", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y42": { + "bits": {}, + "grid_x": 52, + "grid_y": 164, + "segment": "SEG_CLBLL_R_X19Y42", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y43": { + "bits": {}, + "grid_x": 52, + "grid_y": 163, + "segment": "SEG_CLBLL_R_X19Y43", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y44": { + "bits": {}, + "grid_x": 52, + "grid_y": 162, + "segment": "SEG_CLBLL_R_X19Y44", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y45": { + "bits": {}, + "grid_x": 52, + "grid_y": 161, + "segment": "SEG_CLBLL_R_X19Y45", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y46": { + "bits": {}, + "grid_x": 52, + "grid_y": 160, + "segment": "SEG_CLBLL_R_X19Y46", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y47": { + "bits": {}, + "grid_x": 52, + "grid_y": 159, + "segment": "SEG_CLBLL_R_X19Y47", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y48": { + "bits": {}, + "grid_x": 52, + "grid_y": 158, + "segment": "SEG_CLBLL_R_X19Y48", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y49": { + "bits": {}, + "grid_x": 52, + "grid_y": 157, + "segment": "SEG_CLBLL_R_X19Y49", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y5": { + "bits": {}, + "grid_x": 52, + "grid_y": 202, + "segment": "SEG_CLBLL_R_X19Y5", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y6": { + "bits": {}, + "grid_x": 52, + "grid_y": 201, + "segment": "SEG_CLBLL_R_X19Y6", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y7": { + "bits": {}, + "grid_x": 52, + "grid_y": 200, + "segment": "SEG_CLBLL_R_X19Y7", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y8": { + "bits": {}, + "grid_x": 52, + "grid_y": 199, + "segment": "SEG_CLBLL_R_X19Y8", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X19Y9": { + "bits": {}, + "grid_x": 52, + "grid_y": 198, + "segment": "SEG_CLBLL_R_X19Y9", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X21Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y0": { + "bits": {}, + "grid_x": 5, + "grid_y": 207, + "sites": { + "TIEOFF_X1Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y1": { + "bits": {}, + "grid_x": 5, + "grid_y": 206, + "sites": { + "TIEOFF_X1Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y10": { + "bits": {}, + "grid_x": 5, + "grid_y": 197, + "sites": { + "TIEOFF_X1Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y100": { + "bits": {}, + "grid_x": 5, + "grid_y": 103, + "sites": { + "TIEOFF_X1Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y101": { + "bits": {}, + "grid_x": 5, + "grid_y": 102, + "sites": { + "TIEOFF_X1Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y102": { + "bits": {}, + "grid_x": 5, + "grid_y": 101, + "sites": { + "TIEOFF_X1Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y103": { + "bits": {}, + "grid_x": 5, + "grid_y": 100, + "sites": { + "TIEOFF_X1Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y104": { + "bits": {}, + "grid_x": 5, + "grid_y": 99, + "sites": { + "TIEOFF_X1Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y105": { + "bits": {}, + "grid_x": 5, + "grid_y": 98, + "sites": { + "TIEOFF_X1Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y106": { + "bits": {}, + "grid_x": 5, + "grid_y": 97, + "sites": { + "TIEOFF_X1Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y107": { + "bits": {}, + "grid_x": 5, + "grid_y": 96, + "sites": { + "TIEOFF_X1Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y108": { + "bits": {}, + "grid_x": 5, + "grid_y": 95, + "sites": { + "TIEOFF_X1Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y109": { + "bits": {}, + "grid_x": 5, + "grid_y": 94, + "sites": { + "TIEOFF_X1Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y11": { + "bits": {}, + "grid_x": 5, + "grid_y": 196, + "sites": { + "TIEOFF_X1Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y110": { + "bits": {}, + "grid_x": 5, + "grid_y": 93, + "sites": { + "TIEOFF_X1Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y111": { + "bits": {}, + "grid_x": 5, + "grid_y": 92, + "sites": { + "TIEOFF_X1Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y112": { + "bits": {}, + "grid_x": 5, + "grid_y": 91, + "sites": { + "TIEOFF_X1Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y113": { + "bits": {}, + "grid_x": 5, + "grid_y": 90, + "sites": { + "TIEOFF_X1Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y114": { + "bits": {}, + "grid_x": 5, + "grid_y": 89, + "sites": { + "TIEOFF_X1Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y115": { + "bits": {}, + "grid_x": 5, + "grid_y": 88, + "sites": { + "TIEOFF_X1Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y116": { + "bits": {}, + "grid_x": 5, + "grid_y": 87, + "sites": { + "TIEOFF_X1Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y117": { + "bits": {}, + "grid_x": 5, + "grid_y": 86, + "sites": { + "TIEOFF_X1Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y118": { + "bits": {}, + "grid_x": 5, + "grid_y": 85, + "sites": { + "TIEOFF_X1Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y119": { + "bits": {}, + "grid_x": 5, + "grid_y": 84, + "sites": { + "TIEOFF_X1Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y12": { + "bits": {}, + "grid_x": 5, + "grid_y": 195, + "sites": { + "TIEOFF_X1Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y120": { + "bits": {}, + "grid_x": 5, + "grid_y": 83, + "sites": { + "TIEOFF_X1Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y121": { + "bits": {}, + "grid_x": 5, + "grid_y": 82, + "sites": { + "TIEOFF_X1Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y122": { + "bits": {}, + "grid_x": 5, + "grid_y": 81, + "sites": { + "TIEOFF_X1Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y123": { + "bits": {}, + "grid_x": 5, + "grid_y": 80, + "sites": { + "TIEOFF_X1Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y124": { + "bits": {}, + "grid_x": 5, + "grid_y": 79, + "sites": { + "TIEOFF_X1Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y125": { + "bits": {}, + "grid_x": 5, + "grid_y": 77, + "sites": { + "TIEOFF_X1Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y126": { + "bits": {}, + "grid_x": 5, + "grid_y": 76, + "sites": { + "TIEOFF_X1Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y127": { + "bits": {}, + "grid_x": 5, + "grid_y": 75, + "sites": { + "TIEOFF_X1Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y128": { + "bits": {}, + "grid_x": 5, + "grid_y": 74, + "sites": { + "TIEOFF_X1Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y129": { + "bits": {}, + "grid_x": 5, + "grid_y": 73, + "sites": { + "TIEOFF_X1Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y13": { + "bits": {}, + "grid_x": 5, + "grid_y": 194, + "sites": { + "TIEOFF_X1Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y130": { + "bits": {}, + "grid_x": 5, + "grid_y": 72, + "sites": { + "TIEOFF_X1Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y131": { + "bits": {}, + "grid_x": 5, + "grid_y": 71, + "sites": { + "TIEOFF_X1Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y132": { + "bits": {}, + "grid_x": 5, + "grid_y": 70, + "sites": { + "TIEOFF_X1Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y133": { + "bits": {}, + "grid_x": 5, + "grid_y": 69, + "sites": { + "TIEOFF_X1Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y134": { + "bits": {}, + "grid_x": 5, + "grid_y": 68, + "sites": { + "TIEOFF_X1Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y135": { + "bits": {}, + "grid_x": 5, + "grid_y": 67, + "sites": { + "TIEOFF_X1Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y136": { + "bits": {}, + "grid_x": 5, + "grid_y": 66, + "sites": { + "TIEOFF_X1Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y137": { + "bits": {}, + "grid_x": 5, + "grid_y": 65, + "sites": { + "TIEOFF_X1Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y138": { + "bits": {}, + "grid_x": 5, + "grid_y": 64, + "sites": { + "TIEOFF_X1Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y139": { + "bits": {}, + "grid_x": 5, + "grid_y": 63, + "sites": { + "TIEOFF_X1Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y14": { + "bits": {}, + "grid_x": 5, + "grid_y": 193, + "sites": { + "TIEOFF_X1Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y140": { + "bits": {}, + "grid_x": 5, + "grid_y": 62, + "sites": { + "TIEOFF_X1Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y141": { + "bits": {}, + "grid_x": 5, + "grid_y": 61, + "sites": { + "TIEOFF_X1Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y142": { + "bits": {}, + "grid_x": 5, + "grid_y": 60, + "sites": { + "TIEOFF_X1Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y143": { + "bits": {}, + "grid_x": 5, + "grid_y": 59, + "sites": { + "TIEOFF_X1Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y144": { + "bits": {}, + "grid_x": 5, + "grid_y": 58, + "sites": { + "TIEOFF_X1Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y145": { + "bits": {}, + "grid_x": 5, + "grid_y": 57, + "sites": { + "TIEOFF_X1Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y146": { + "bits": {}, + "grid_x": 5, + "grid_y": 56, + "sites": { + "TIEOFF_X1Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y147": { + "bits": {}, + "grid_x": 5, + "grid_y": 55, + "sites": { + "TIEOFF_X1Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y148": { + "bits": {}, + "grid_x": 5, + "grid_y": 54, + "sites": { + "TIEOFF_X1Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y149": { + "bits": {}, + "grid_x": 5, + "grid_y": 53, + "sites": { + "TIEOFF_X1Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y15": { + "bits": {}, + "grid_x": 5, + "grid_y": 192, + "sites": { + "TIEOFF_X1Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y150": { + "bits": {}, + "grid_x": 5, + "grid_y": 51, + "sites": { + "TIEOFF_X1Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y151": { + "bits": {}, + "grid_x": 5, + "grid_y": 50, + "sites": { + "TIEOFF_X1Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y152": { + "bits": {}, + "grid_x": 5, + "grid_y": 49, + "sites": { + "TIEOFF_X1Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y153": { + "bits": {}, + "grid_x": 5, + "grid_y": 48, + "sites": { + "TIEOFF_X1Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y154": { + "bits": {}, + "grid_x": 5, + "grid_y": 47, + "sites": { + "TIEOFF_X1Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y155": { + "bits": {}, + "grid_x": 5, + "grid_y": 46, + "sites": { + "TIEOFF_X1Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y156": { + "bits": {}, + "grid_x": 5, + "grid_y": 45, + "sites": { + "TIEOFF_X1Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y157": { + "bits": {}, + "grid_x": 5, + "grid_y": 44, + "sites": { + "TIEOFF_X1Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y158": { + "bits": {}, + "grid_x": 5, + "grid_y": 43, + "sites": { + "TIEOFF_X1Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y159": { + "bits": {}, + "grid_x": 5, + "grid_y": 42, + "sites": { + "TIEOFF_X1Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y16": { + "bits": {}, + "grid_x": 5, + "grid_y": 191, + "sites": { + "TIEOFF_X1Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y160": { + "bits": {}, + "grid_x": 5, + "grid_y": 41, + "sites": { + "TIEOFF_X1Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y161": { + "bits": {}, + "grid_x": 5, + "grid_y": 40, + "sites": { + "TIEOFF_X1Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y162": { + "bits": {}, + "grid_x": 5, + "grid_y": 39, + "sites": { + "TIEOFF_X1Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y163": { + "bits": {}, + "grid_x": 5, + "grid_y": 38, + "sites": { + "TIEOFF_X1Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y164": { + "bits": {}, + "grid_x": 5, + "grid_y": 37, + "sites": { + "TIEOFF_X1Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y165": { + "bits": {}, + "grid_x": 5, + "grid_y": 36, + "sites": { + "TIEOFF_X1Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y166": { + "bits": {}, + "grid_x": 5, + "grid_y": 35, + "sites": { + "TIEOFF_X1Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y167": { + "bits": {}, + "grid_x": 5, + "grid_y": 34, + "sites": { + "TIEOFF_X1Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y168": { + "bits": {}, + "grid_x": 5, + "grid_y": 33, + "sites": { + "TIEOFF_X1Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y169": { + "bits": {}, + "grid_x": 5, + "grid_y": 32, + "sites": { + "TIEOFF_X1Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y17": { + "bits": {}, + "grid_x": 5, + "grid_y": 190, + "sites": { + "TIEOFF_X1Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y170": { + "bits": {}, + "grid_x": 5, + "grid_y": 31, + "sites": { + "TIEOFF_X1Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y171": { + "bits": {}, + "grid_x": 5, + "grid_y": 30, + "sites": { + "TIEOFF_X1Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y172": { + "bits": {}, + "grid_x": 5, + "grid_y": 29, + "sites": { + "TIEOFF_X1Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y173": { + "bits": {}, + "grid_x": 5, + "grid_y": 28, + "sites": { + "TIEOFF_X1Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y174": { + "bits": {}, + "grid_x": 5, + "grid_y": 27, + "sites": { + "TIEOFF_X1Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y175": { + "bits": {}, + "grid_x": 5, + "grid_y": 25, + "sites": { + "TIEOFF_X1Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y176": { + "bits": {}, + "grid_x": 5, + "grid_y": 24, + "sites": { + "TIEOFF_X1Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y177": { + "bits": {}, + "grid_x": 5, + "grid_y": 23, + "sites": { + "TIEOFF_X1Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y178": { + "bits": {}, + "grid_x": 5, + "grid_y": 22, + "sites": { + "TIEOFF_X1Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y179": { + "bits": {}, + "grid_x": 5, + "grid_y": 21, + "sites": { + "TIEOFF_X1Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y18": { + "bits": {}, + "grid_x": 5, + "grid_y": 189, + "sites": { + "TIEOFF_X1Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y180": { + "bits": {}, + "grid_x": 5, + "grid_y": 20, + "sites": { + "TIEOFF_X1Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y181": { + "bits": {}, + "grid_x": 5, + "grid_y": 19, + "sites": { + "TIEOFF_X1Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y182": { + "bits": {}, + "grid_x": 5, + "grid_y": 18, + "sites": { + "TIEOFF_X1Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y183": { + "bits": {}, + "grid_x": 5, + "grid_y": 17, + "sites": { + "TIEOFF_X1Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y184": { + "bits": {}, + "grid_x": 5, + "grid_y": 16, + "sites": { + "TIEOFF_X1Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y185": { + "bits": {}, + "grid_x": 5, + "grid_y": 15, + "sites": { + "TIEOFF_X1Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y186": { + "bits": {}, + "grid_x": 5, + "grid_y": 14, + "sites": { + "TIEOFF_X1Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y187": { + "bits": {}, + "grid_x": 5, + "grid_y": 13, + "sites": { + "TIEOFF_X1Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y188": { + "bits": {}, + "grid_x": 5, + "grid_y": 12, + "sites": { + "TIEOFF_X1Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y189": { + "bits": {}, + "grid_x": 5, + "grid_y": 11, + "sites": { + "TIEOFF_X1Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y19": { + "bits": {}, + "grid_x": 5, + "grid_y": 188, + "sites": { + "TIEOFF_X1Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y190": { + "bits": {}, + "grid_x": 5, + "grid_y": 10, + "sites": { + "TIEOFF_X1Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y191": { + "bits": {}, + "grid_x": 5, + "grid_y": 9, + "sites": { + "TIEOFF_X1Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y192": { + "bits": {}, + "grid_x": 5, + "grid_y": 8, + "sites": { + "TIEOFF_X1Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y193": { + "bits": {}, + "grid_x": 5, + "grid_y": 7, + "sites": { + "TIEOFF_X1Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y194": { + "bits": {}, + "grid_x": 5, + "grid_y": 6, + "sites": { + "TIEOFF_X1Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y195": { + "bits": {}, + "grid_x": 5, + "grid_y": 5, + "sites": { + "TIEOFF_X1Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y196": { + "bits": {}, + "grid_x": 5, + "grid_y": 4, + "sites": { + "TIEOFF_X1Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y197": { + "bits": {}, + "grid_x": 5, + "grid_y": 3, + "sites": { + "TIEOFF_X1Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y198": { + "bits": {}, + "grid_x": 5, + "grid_y": 2, + "sites": { + "TIEOFF_X1Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y199": { + "bits": {}, + "grid_x": 5, + "grid_y": 1, + "sites": { + "TIEOFF_X1Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y2": { + "bits": {}, + "grid_x": 5, + "grid_y": 205, + "sites": { + "TIEOFF_X1Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y20": { + "bits": {}, + "grid_x": 5, + "grid_y": 187, + "sites": { + "TIEOFF_X1Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y21": { + "bits": {}, + "grid_x": 5, + "grid_y": 186, + "sites": { + "TIEOFF_X1Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y22": { + "bits": {}, + "grid_x": 5, + "grid_y": 185, + "sites": { + "TIEOFF_X1Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y23": { + "bits": {}, + "grid_x": 5, + "grid_y": 184, + "sites": { + "TIEOFF_X1Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y24": { + "bits": {}, + "grid_x": 5, + "grid_y": 183, + "sites": { + "TIEOFF_X1Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y25": { + "bits": {}, + "grid_x": 5, + "grid_y": 181, + "sites": { + "TIEOFF_X1Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y26": { + "bits": {}, + "grid_x": 5, + "grid_y": 180, + "sites": { + "TIEOFF_X1Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y27": { + "bits": {}, + "grid_x": 5, + "grid_y": 179, + "sites": { + "TIEOFF_X1Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y28": { + "bits": {}, + "grid_x": 5, + "grid_y": 178, + "sites": { + "TIEOFF_X1Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y29": { + "bits": {}, + "grid_x": 5, + "grid_y": 177, + "sites": { + "TIEOFF_X1Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y3": { + "bits": {}, + "grid_x": 5, + "grid_y": 204, + "sites": { + "TIEOFF_X1Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y30": { + "bits": {}, + "grid_x": 5, + "grid_y": 176, + "sites": { + "TIEOFF_X1Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y31": { + "bits": {}, + "grid_x": 5, + "grid_y": 175, + "sites": { + "TIEOFF_X1Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y32": { + "bits": {}, + "grid_x": 5, + "grid_y": 174, + "sites": { + "TIEOFF_X1Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y33": { + "bits": {}, + "grid_x": 5, + "grid_y": 173, + "sites": { + "TIEOFF_X1Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y34": { + "bits": {}, + "grid_x": 5, + "grid_y": 172, + "sites": { + "TIEOFF_X1Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y35": { + "bits": {}, + "grid_x": 5, + "grid_y": 171, + "sites": { + "TIEOFF_X1Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y36": { + "bits": {}, + "grid_x": 5, + "grid_y": 170, + "sites": { + "TIEOFF_X1Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y37": { + "bits": {}, + "grid_x": 5, + "grid_y": 169, + "sites": { + "TIEOFF_X1Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y38": { + "bits": {}, + "grid_x": 5, + "grid_y": 168, + "sites": { + "TIEOFF_X1Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y39": { + "bits": {}, + "grid_x": 5, + "grid_y": 167, + "sites": { + "TIEOFF_X1Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y4": { + "bits": {}, + "grid_x": 5, + "grid_y": 203, + "sites": { + "TIEOFF_X1Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y40": { + "bits": {}, + "grid_x": 5, + "grid_y": 166, + "sites": { + "TIEOFF_X1Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y41": { + "bits": {}, + "grid_x": 5, + "grid_y": 165, + "sites": { + "TIEOFF_X1Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y42": { + "bits": {}, + "grid_x": 5, + "grid_y": 164, + "sites": { + "TIEOFF_X1Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y43": { + "bits": {}, + "grid_x": 5, + "grid_y": 163, + "sites": { + "TIEOFF_X1Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y44": { + "bits": {}, + "grid_x": 5, + "grid_y": 162, + "sites": { + "TIEOFF_X1Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y45": { + "bits": {}, + "grid_x": 5, + "grid_y": 161, + "sites": { + "TIEOFF_X1Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y46": { + "bits": {}, + "grid_x": 5, + "grid_y": 160, + "sites": { + "TIEOFF_X1Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y47": { + "bits": {}, + "grid_x": 5, + "grid_y": 159, + "sites": { + "TIEOFF_X1Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y48": { + "bits": {}, + "grid_x": 5, + "grid_y": 158, + "sites": { + "TIEOFF_X1Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y49": { + "bits": {}, + "grid_x": 5, + "grid_y": 157, + "sites": { + "TIEOFF_X1Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y5": { + "bits": {}, + "grid_x": 5, + "grid_y": 202, + "sites": { + "TIEOFF_X1Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y50": { + "bits": {}, + "grid_x": 5, + "grid_y": 155, + "sites": { + "TIEOFF_X1Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y51": { + "bits": {}, + "grid_x": 5, + "grid_y": 154, + "sites": { + "TIEOFF_X1Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y52": { + "bits": {}, + "grid_x": 5, + "grid_y": 153, + "sites": { + "TIEOFF_X1Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y53": { + "bits": {}, + "grid_x": 5, + "grid_y": 152, + "sites": { + "TIEOFF_X1Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y54": { + "bits": {}, + "grid_x": 5, + "grid_y": 151, + "sites": { + "TIEOFF_X1Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y55": { + "bits": {}, + "grid_x": 5, + "grid_y": 150, + "sites": { + "TIEOFF_X1Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y56": { + "bits": {}, + "grid_x": 5, + "grid_y": 149, + "sites": { + "TIEOFF_X1Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y57": { + "bits": {}, + "grid_x": 5, + "grid_y": 148, + "sites": { + "TIEOFF_X1Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y58": { + "bits": {}, + "grid_x": 5, + "grid_y": 147, + "sites": { + "TIEOFF_X1Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y59": { + "bits": {}, + "grid_x": 5, + "grid_y": 146, + "sites": { + "TIEOFF_X1Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y6": { + "bits": {}, + "grid_x": 5, + "grid_y": 201, + "sites": { + "TIEOFF_X1Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y60": { + "bits": {}, + "grid_x": 5, + "grid_y": 145, + "sites": { + "TIEOFF_X1Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y61": { + "bits": {}, + "grid_x": 5, + "grid_y": 144, + "sites": { + "TIEOFF_X1Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y62": { + "bits": {}, + "grid_x": 5, + "grid_y": 143, + "sites": { + "TIEOFF_X1Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y63": { + "bits": {}, + "grid_x": 5, + "grid_y": 142, + "sites": { + "TIEOFF_X1Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y64": { + "bits": {}, + "grid_x": 5, + "grid_y": 141, + "sites": { + "TIEOFF_X1Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y65": { + "bits": {}, + "grid_x": 5, + "grid_y": 140, + "sites": { + "TIEOFF_X1Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y66": { + "bits": {}, + "grid_x": 5, + "grid_y": 139, + "sites": { + "TIEOFF_X1Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y67": { + "bits": {}, + "grid_x": 5, + "grid_y": 138, + "sites": { + "TIEOFF_X1Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y68": { + "bits": {}, + "grid_x": 5, + "grid_y": 137, + "sites": { + "TIEOFF_X1Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y69": { + "bits": {}, + "grid_x": 5, + "grid_y": 136, + "sites": { + "TIEOFF_X1Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y7": { + "bits": {}, + "grid_x": 5, + "grid_y": 200, + "sites": { + "TIEOFF_X1Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y70": { + "bits": {}, + "grid_x": 5, + "grid_y": 135, + "sites": { + "TIEOFF_X1Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y71": { + "bits": {}, + "grid_x": 5, + "grid_y": 134, + "sites": { + "TIEOFF_X1Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y72": { + "bits": {}, + "grid_x": 5, + "grid_y": 133, + "sites": { + "TIEOFF_X1Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y73": { + "bits": {}, + "grid_x": 5, + "grid_y": 132, + "sites": { + "TIEOFF_X1Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y74": { + "bits": {}, + "grid_x": 5, + "grid_y": 131, + "sites": { + "TIEOFF_X1Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y75": { + "bits": {}, + "grid_x": 5, + "grid_y": 129, + "sites": { + "TIEOFF_X1Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y76": { + "bits": {}, + "grid_x": 5, + "grid_y": 128, + "sites": { + "TIEOFF_X1Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y77": { + "bits": {}, + "grid_x": 5, + "grid_y": 127, + "sites": { + "TIEOFF_X1Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y78": { + "bits": {}, + "grid_x": 5, + "grid_y": 126, + "sites": { + "TIEOFF_X1Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y79": { + "bits": {}, + "grid_x": 5, + "grid_y": 125, + "sites": { + "TIEOFF_X1Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y8": { + "bits": {}, + "grid_x": 5, + "grid_y": 199, + "sites": { + "TIEOFF_X1Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y80": { + "bits": {}, + "grid_x": 5, + "grid_y": 124, + "sites": { + "TIEOFF_X1Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y81": { + "bits": {}, + "grid_x": 5, + "grid_y": 123, + "sites": { + "TIEOFF_X1Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y82": { + "bits": {}, + "grid_x": 5, + "grid_y": 122, + "sites": { + "TIEOFF_X1Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y83": { + "bits": {}, + "grid_x": 5, + "grid_y": 121, + "sites": { + "TIEOFF_X1Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y84": { + "bits": {}, + "grid_x": 5, + "grid_y": 120, + "sites": { + "TIEOFF_X1Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y85": { + "bits": {}, + "grid_x": 5, + "grid_y": 119, + "sites": { + "TIEOFF_X1Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y86": { + "bits": {}, + "grid_x": 5, + "grid_y": 118, + "sites": { + "TIEOFF_X1Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y87": { + "bits": {}, + "grid_x": 5, + "grid_y": 117, + "sites": { + "TIEOFF_X1Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y88": { + "bits": {}, + "grid_x": 5, + "grid_y": 116, + "sites": { + "TIEOFF_X1Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y89": { + "bits": {}, + "grid_x": 5, + "grid_y": 115, + "sites": { + "TIEOFF_X1Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y9": { + "bits": {}, + "grid_x": 5, + "grid_y": 198, + "sites": { + "TIEOFF_X1Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y90": { + "bits": {}, + "grid_x": 5, + "grid_y": 114, + "sites": { + "TIEOFF_X1Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y91": { + "bits": {}, + "grid_x": 5, + "grid_y": 113, + "sites": { + "TIEOFF_X1Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y92": { + "bits": {}, + "grid_x": 5, + "grid_y": 112, + "sites": { + "TIEOFF_X1Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y93": { + "bits": {}, + "grid_x": 5, + "grid_y": 111, + "sites": { + "TIEOFF_X1Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y94": { + "bits": {}, + "grid_x": 5, + "grid_y": 110, + "sites": { + "TIEOFF_X1Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y95": { + "bits": {}, + "grid_x": 5, + "grid_y": 109, + "sites": { + "TIEOFF_X1Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y96": { + "bits": {}, + "grid_x": 5, + "grid_y": 108, + "sites": { + "TIEOFF_X1Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y97": { + "bits": {}, + "grid_x": 5, + "grid_y": 107, + "sites": { + "TIEOFF_X1Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y98": { + "bits": {}, + "grid_x": 5, + "grid_y": 106, + "sites": { + "TIEOFF_X1Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X1Y99": { + "bits": {}, + "grid_x": 5, + "grid_y": 105, + "sites": { + "TIEOFF_X1Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y0": { + "bits": {}, + "grid_x": 56, + "grid_y": 207, + "segment": "SEG_CLBLL_R_X21Y0", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y1": { + "bits": {}, + "grid_x": 56, + "grid_y": 206, + "segment": "SEG_CLBLL_R_X21Y1", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y10": { + "bits": {}, + "grid_x": 56, + "grid_y": 197, + "segment": "SEG_CLBLL_R_X21Y10", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y11": { + "bits": {}, + "grid_x": 56, + "grid_y": 196, + "segment": "SEG_CLBLL_R_X21Y11", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y12": { + "bits": {}, + "grid_x": 56, + "grid_y": 195, + "segment": "SEG_CLBLL_R_X21Y12", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y13": { + "bits": {}, + "grid_x": 56, + "grid_y": 194, + "segment": "SEG_CLBLL_R_X21Y13", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y14": { + "bits": {}, + "grid_x": 56, + "grid_y": 193, + "segment": "SEG_CLBLL_R_X21Y14", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y15": { + "bits": {}, + "grid_x": 56, + "grid_y": 192, + "segment": "SEG_CLBLL_R_X21Y15", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y150": { + "bits": {}, + "grid_x": 56, + "grid_y": 51, + "segment": "SEG_CLBLL_R_X21Y150", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y151": { + "bits": {}, + "grid_x": 56, + "grid_y": 50, + "segment": "SEG_CLBLL_R_X21Y151", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y152": { + "bits": {}, + "grid_x": 56, + "grid_y": 49, + "segment": "SEG_CLBLL_R_X21Y152", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y153": { + "bits": {}, + "grid_x": 56, + "grid_y": 48, + "segment": "SEG_CLBLL_R_X21Y153", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y154": { + "bits": {}, + "grid_x": 56, + "grid_y": 47, + "segment": "SEG_CLBLL_R_X21Y154", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y155": { + "bits": {}, + "grid_x": 56, + "grid_y": 46, + "segment": "SEG_CLBLL_R_X21Y155", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y156": { + "bits": {}, + "grid_x": 56, + "grid_y": 45, + "segment": "SEG_CLBLL_R_X21Y156", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y157": { + "bits": {}, + "grid_x": 56, + "grid_y": 44, + "segment": "SEG_CLBLL_R_X21Y157", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y158": { + "bits": {}, + "grid_x": 56, + "grid_y": 43, + "segment": "SEG_CLBLL_R_X21Y158", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y159": { + "bits": {}, + "grid_x": 56, + "grid_y": 42, + "segment": "SEG_CLBLL_R_X21Y159", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y16": { + "bits": {}, + "grid_x": 56, + "grid_y": 191, + "segment": "SEG_CLBLL_R_X21Y16", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y160": { + "bits": {}, + "grid_x": 56, + "grid_y": 41, + "segment": "SEG_CLBLL_R_X21Y160", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y161": { + "bits": {}, + "grid_x": 56, + "grid_y": 40, + "segment": "SEG_CLBLL_R_X21Y161", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y162": { + "bits": {}, + "grid_x": 56, + "grid_y": 39, + "segment": "SEG_CLBLL_R_X21Y162", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y163": { + "bits": {}, + "grid_x": 56, + "grid_y": 38, + "segment": "SEG_CLBLL_R_X21Y163", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y164": { + "bits": {}, + "grid_x": 56, + "grid_y": 37, + "segment": "SEG_CLBLL_R_X21Y164", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y165": { + "bits": {}, + "grid_x": 56, + "grid_y": 36, + "segment": "SEG_CLBLL_R_X21Y165", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y166": { + "bits": {}, + "grid_x": 56, + "grid_y": 35, + "segment": "SEG_CLBLL_R_X21Y166", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y167": { + "bits": {}, + "grid_x": 56, + "grid_y": 34, + "segment": "SEG_CLBLL_R_X21Y167", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y168": { + "bits": {}, + "grid_x": 56, + "grid_y": 33, + "segment": "SEG_CLBLL_R_X21Y168", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y169": { + "bits": {}, + "grid_x": 56, + "grid_y": 32, + "segment": "SEG_CLBLL_R_X21Y169", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y17": { + "bits": {}, + "grid_x": 56, + "grid_y": 190, + "segment": "SEG_CLBLL_R_X21Y17", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y170": { + "bits": {}, + "grid_x": 56, + "grid_y": 31, + "segment": "SEG_CLBLL_R_X21Y170", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y171": { + "bits": {}, + "grid_x": 56, + "grid_y": 30, + "segment": "SEG_CLBLL_R_X21Y171", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y172": { + "bits": {}, + "grid_x": 56, + "grid_y": 29, + "segment": "SEG_CLBLL_R_X21Y172", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y173": { + "bits": {}, + "grid_x": 56, + "grid_y": 28, + "segment": "SEG_CLBLL_R_X21Y173", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y174": { + "bits": {}, + "grid_x": 56, + "grid_y": 27, + "segment": "SEG_CLBLL_R_X21Y174", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y175": { + "bits": {}, + "grid_x": 56, + "grid_y": 25, + "segment": "SEG_CLBLL_R_X21Y175", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y176": { + "bits": {}, + "grid_x": 56, + "grid_y": 24, + "segment": "SEG_CLBLL_R_X21Y176", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y177": { + "bits": {}, + "grid_x": 56, + "grid_y": 23, + "segment": "SEG_CLBLL_R_X21Y177", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y178": { + "bits": {}, + "grid_x": 56, + "grid_y": 22, + "segment": "SEG_CLBLL_R_X21Y178", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y179": { + "bits": {}, + "grid_x": 56, + "grid_y": 21, + "segment": "SEG_CLBLL_R_X21Y179", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y18": { + "bits": {}, + "grid_x": 56, + "grid_y": 189, + "segment": "SEG_CLBLL_R_X21Y18", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y180": { + "bits": {}, + "grid_x": 56, + "grid_y": 20, + "segment": "SEG_CLBLL_R_X21Y180", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y181": { + "bits": {}, + "grid_x": 56, + "grid_y": 19, + "segment": "SEG_CLBLL_R_X21Y181", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y182": { + "bits": {}, + "grid_x": 56, + "grid_y": 18, + "segment": "SEG_CLBLL_R_X21Y182", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y183": { + "bits": {}, + "grid_x": 56, + "grid_y": 17, + "segment": "SEG_CLBLL_R_X21Y183", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y184": { + "bits": {}, + "grid_x": 56, + "grid_y": 16, + "segment": "SEG_CLBLL_R_X21Y184", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y185": { + "bits": {}, + "grid_x": 56, + "grid_y": 15, + "segment": "SEG_CLBLL_R_X21Y185", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y186": { + "bits": {}, + "grid_x": 56, + "grid_y": 14, + "segment": "SEG_CLBLL_R_X21Y186", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y187": { + "bits": {}, + "grid_x": 56, + "grid_y": 13, + "segment": "SEG_CLBLL_R_X21Y187", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y188": { + "bits": {}, + "grid_x": 56, + "grid_y": 12, + "segment": "SEG_CLBLL_R_X21Y188", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y189": { + "bits": {}, + "grid_x": 56, + "grid_y": 11, + "segment": "SEG_CLBLL_R_X21Y189", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y19": { + "bits": {}, + "grid_x": 56, + "grid_y": 188, + "segment": "SEG_CLBLL_R_X21Y19", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y190": { + "bits": {}, + "grid_x": 56, + "grid_y": 10, + "segment": "SEG_CLBLL_R_X21Y190", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y191": { + "bits": {}, + "grid_x": 56, + "grid_y": 9, + "segment": "SEG_CLBLL_R_X21Y191", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y192": { + "bits": {}, + "grid_x": 56, + "grid_y": 8, + "segment": "SEG_CLBLL_R_X21Y192", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y193": { + "bits": {}, + "grid_x": 56, + "grid_y": 7, + "segment": "SEG_CLBLL_R_X21Y193", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y194": { + "bits": {}, + "grid_x": 56, + "grid_y": 6, + "segment": "SEG_CLBLL_R_X21Y194", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y195": { + "bits": {}, + "grid_x": 56, + "grid_y": 5, + "segment": "SEG_CLBLL_R_X21Y195", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y196": { + "bits": {}, + "grid_x": 56, + "grid_y": 4, + "segment": "SEG_CLBLL_R_X21Y196", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y197": { + "bits": {}, + "grid_x": 56, + "grid_y": 3, + "segment": "SEG_CLBLL_R_X21Y197", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y198": { + "bits": {}, + "grid_x": 56, + "grid_y": 2, + "segment": "SEG_CLBLL_R_X21Y198", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y199": { + "bits": {}, + "grid_x": 56, + "grid_y": 1, + "segment": "SEG_CLBLL_R_X21Y199", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y2": { + "bits": {}, + "grid_x": 56, + "grid_y": 205, + "segment": "SEG_CLBLL_R_X21Y2", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y20": { + "bits": {}, + "grid_x": 56, + "grid_y": 187, + "segment": "SEG_CLBLL_R_X21Y20", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y21": { + "bits": {}, + "grid_x": 56, + "grid_y": 186, + "segment": "SEG_CLBLL_R_X21Y21", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y22": { + "bits": {}, + "grid_x": 56, + "grid_y": 185, + "segment": "SEG_CLBLL_R_X21Y22", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y23": { + "bits": {}, + "grid_x": 56, + "grid_y": 184, + "segment": "SEG_CLBLL_R_X21Y23", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y24": { + "bits": {}, + "grid_x": 56, + "grid_y": 183, + "segment": "SEG_CLBLL_R_X21Y24", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y25": { + "bits": {}, + "grid_x": 56, + "grid_y": 181, + "segment": "SEG_CLBLL_R_X21Y25", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y26": { + "bits": {}, + "grid_x": 56, + "grid_y": 180, + "segment": "SEG_CLBLL_R_X21Y26", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y27": { + "bits": {}, + "grid_x": 56, + "grid_y": 179, + "segment": "SEG_CLBLL_R_X21Y27", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y28": { + "bits": {}, + "grid_x": 56, + "grid_y": 178, + "segment": "SEG_CLBLL_R_X21Y28", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y29": { + "bits": {}, + "grid_x": 56, + "grid_y": 177, + "segment": "SEG_CLBLL_R_X21Y29", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y3": { + "bits": {}, + "grid_x": 56, + "grid_y": 204, + "segment": "SEG_CLBLL_R_X21Y3", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y30": { + "bits": {}, + "grid_x": 56, + "grid_y": 176, + "segment": "SEG_CLBLL_R_X21Y30", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y31": { + "bits": {}, + "grid_x": 56, + "grid_y": 175, + "segment": "SEG_CLBLL_R_X21Y31", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y32": { + "bits": {}, + "grid_x": 56, + "grid_y": 174, + "segment": "SEG_CLBLL_R_X21Y32", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y33": { + "bits": {}, + "grid_x": 56, + "grid_y": 173, + "segment": "SEG_CLBLL_R_X21Y33", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y34": { + "bits": {}, + "grid_x": 56, + "grid_y": 172, + "segment": "SEG_CLBLL_R_X21Y34", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y35": { + "bits": {}, + "grid_x": 56, + "grid_y": 171, + "segment": "SEG_CLBLL_R_X21Y35", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y36": { + "bits": {}, + "grid_x": 56, + "grid_y": 170, + "segment": "SEG_CLBLL_R_X21Y36", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y37": { + "bits": {}, + "grid_x": 56, + "grid_y": 169, + "segment": "SEG_CLBLL_R_X21Y37", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y38": { + "bits": {}, + "grid_x": 56, + "grid_y": 168, + "segment": "SEG_CLBLL_R_X21Y38", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y39": { + "bits": {}, + "grid_x": 56, + "grid_y": 167, + "segment": "SEG_CLBLL_R_X21Y39", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y4": { + "bits": {}, + "grid_x": 56, + "grid_y": 203, + "segment": "SEG_CLBLL_R_X21Y4", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y40": { + "bits": {}, + "grid_x": 56, + "grid_y": 166, + "segment": "SEG_CLBLL_R_X21Y40", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y41": { + "bits": {}, + "grid_x": 56, + "grid_y": 165, + "segment": "SEG_CLBLL_R_X21Y41", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y42": { + "bits": {}, + "grid_x": 56, + "grid_y": 164, + "segment": "SEG_CLBLL_R_X21Y42", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y43": { + "bits": {}, + "grid_x": 56, + "grid_y": 163, + "segment": "SEG_CLBLL_R_X21Y43", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y44": { + "bits": {}, + "grid_x": 56, + "grid_y": 162, + "segment": "SEG_CLBLL_R_X21Y44", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y45": { + "bits": {}, + "grid_x": 56, + "grid_y": 161, + "segment": "SEG_CLBLL_R_X21Y45", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y46": { + "bits": {}, + "grid_x": 56, + "grid_y": 160, + "segment": "SEG_CLBLL_R_X21Y46", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y47": { + "bits": {}, + "grid_x": 56, + "grid_y": 159, + "segment": "SEG_CLBLL_R_X21Y47", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y48": { + "bits": {}, + "grid_x": 56, + "grid_y": 158, + "segment": "SEG_CLBLL_R_X21Y48", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y49": { + "bits": {}, + "grid_x": 56, + "grid_y": 157, + "segment": "SEG_CLBLL_R_X21Y49", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y5": { + "bits": {}, + "grid_x": 56, + "grid_y": 202, + "segment": "SEG_CLBLL_R_X21Y5", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y6": { + "bits": {}, + "grid_x": 56, + "grid_y": 201, + "segment": "SEG_CLBLL_R_X21Y6", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y7": { + "bits": {}, + "grid_x": 56, + "grid_y": 200, + "segment": "SEG_CLBLL_R_X21Y7", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y8": { + "bits": {}, + "grid_x": 56, + "grid_y": 199, + "segment": "SEG_CLBLL_R_X21Y8", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X21Y9": { + "bits": {}, + "grid_x": 56, + "grid_y": 198, + "segment": "SEG_CLBLL_R_X21Y9", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X23Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y0": { + "bits": {}, + "grid_x": 60, + "grid_y": 207, + "segment": "SEG_CLBLL_R_X23Y0", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y1": { + "bits": {}, + "grid_x": 60, + "grid_y": 206, + "segment": "SEG_CLBLL_R_X23Y1", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y10": { + "bits": {}, + "grid_x": 60, + "grid_y": 197, + "segment": "SEG_CLBLL_R_X23Y10", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y11": { + "bits": {}, + "grid_x": 60, + "grid_y": 196, + "segment": "SEG_CLBLL_R_X23Y11", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y12": { + "bits": {}, + "grid_x": 60, + "grid_y": 195, + "segment": "SEG_CLBLL_R_X23Y12", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y13": { + "bits": {}, + "grid_x": 60, + "grid_y": 194, + "segment": "SEG_CLBLL_R_X23Y13", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y14": { + "bits": {}, + "grid_x": 60, + "grid_y": 193, + "segment": "SEG_CLBLL_R_X23Y14", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y15": { + "bits": {}, + "grid_x": 60, + "grid_y": 192, + "segment": "SEG_CLBLL_R_X23Y15", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y150": { + "bits": {}, + "grid_x": 60, + "grid_y": 51, + "segment": "SEG_CLBLL_R_X23Y150", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y151": { + "bits": {}, + "grid_x": 60, + "grid_y": 50, + "segment": "SEG_CLBLL_R_X23Y151", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y152": { + "bits": {}, + "grid_x": 60, + "grid_y": 49, + "segment": "SEG_CLBLL_R_X23Y152", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y153": { + "bits": {}, + "grid_x": 60, + "grid_y": 48, + "segment": "SEG_CLBLL_R_X23Y153", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y154": { + "bits": {}, + "grid_x": 60, + "grid_y": 47, + "segment": "SEG_CLBLL_R_X23Y154", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y155": { + "bits": {}, + "grid_x": 60, + "grid_y": 46, + "segment": "SEG_CLBLL_R_X23Y155", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y156": { + "bits": {}, + "grid_x": 60, + "grid_y": 45, + "segment": "SEG_CLBLL_R_X23Y156", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y157": { + "bits": {}, + "grid_x": 60, + "grid_y": 44, + "segment": "SEG_CLBLL_R_X23Y157", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y158": { + "bits": {}, + "grid_x": 60, + "grid_y": 43, + "segment": "SEG_CLBLL_R_X23Y158", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y159": { + "bits": {}, + "grid_x": 60, + "grid_y": 42, + "segment": "SEG_CLBLL_R_X23Y159", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y16": { + "bits": {}, + "grid_x": 60, + "grid_y": 191, + "segment": "SEG_CLBLL_R_X23Y16", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y160": { + "bits": {}, + "grid_x": 60, + "grid_y": 41, + "segment": "SEG_CLBLL_R_X23Y160", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y161": { + "bits": {}, + "grid_x": 60, + "grid_y": 40, + "segment": "SEG_CLBLL_R_X23Y161", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y162": { + "bits": {}, + "grid_x": 60, + "grid_y": 39, + "segment": "SEG_CLBLL_R_X23Y162", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y163": { + "bits": {}, + "grid_x": 60, + "grid_y": 38, + "segment": "SEG_CLBLL_R_X23Y163", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y164": { + "bits": {}, + "grid_x": 60, + "grid_y": 37, + "segment": "SEG_CLBLL_R_X23Y164", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y165": { + "bits": {}, + "grid_x": 60, + "grid_y": 36, + "segment": "SEG_CLBLL_R_X23Y165", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y166": { + "bits": {}, + "grid_x": 60, + "grid_y": 35, + "segment": "SEG_CLBLL_R_X23Y166", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y167": { + "bits": {}, + "grid_x": 60, + "grid_y": 34, + "segment": "SEG_CLBLL_R_X23Y167", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y168": { + "bits": {}, + "grid_x": 60, + "grid_y": 33, + "segment": "SEG_CLBLL_R_X23Y168", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y169": { + "bits": {}, + "grid_x": 60, + "grid_y": 32, + "segment": "SEG_CLBLL_R_X23Y169", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y17": { + "bits": {}, + "grid_x": 60, + "grid_y": 190, + "segment": "SEG_CLBLL_R_X23Y17", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y170": { + "bits": {}, + "grid_x": 60, + "grid_y": 31, + "segment": "SEG_CLBLL_R_X23Y170", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y171": { + "bits": {}, + "grid_x": 60, + "grid_y": 30, + "segment": "SEG_CLBLL_R_X23Y171", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y172": { + "bits": {}, + "grid_x": 60, + "grid_y": 29, + "segment": "SEG_CLBLL_R_X23Y172", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y173": { + "bits": {}, + "grid_x": 60, + "grid_y": 28, + "segment": "SEG_CLBLL_R_X23Y173", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y174": { + "bits": {}, + "grid_x": 60, + "grid_y": 27, + "segment": "SEG_CLBLL_R_X23Y174", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y175": { + "bits": {}, + "grid_x": 60, + "grid_y": 25, + "segment": "SEG_CLBLL_R_X23Y175", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y176": { + "bits": {}, + "grid_x": 60, + "grid_y": 24, + "segment": "SEG_CLBLL_R_X23Y176", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y177": { + "bits": {}, + "grid_x": 60, + "grid_y": 23, + "segment": "SEG_CLBLL_R_X23Y177", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y178": { + "bits": {}, + "grid_x": 60, + "grid_y": 22, + "segment": "SEG_CLBLL_R_X23Y178", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y179": { + "bits": {}, + "grid_x": 60, + "grid_y": 21, + "segment": "SEG_CLBLL_R_X23Y179", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y18": { + "bits": {}, + "grid_x": 60, + "grid_y": 189, + "segment": "SEG_CLBLL_R_X23Y18", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y180": { + "bits": {}, + "grid_x": 60, + "grid_y": 20, + "segment": "SEG_CLBLL_R_X23Y180", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y181": { + "bits": {}, + "grid_x": 60, + "grid_y": 19, + "segment": "SEG_CLBLL_R_X23Y181", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y182": { + "bits": {}, + "grid_x": 60, + "grid_y": 18, + "segment": "SEG_CLBLL_R_X23Y182", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y183": { + "bits": {}, + "grid_x": 60, + "grid_y": 17, + "segment": "SEG_CLBLL_R_X23Y183", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y184": { + "bits": {}, + "grid_x": 60, + "grid_y": 16, + "segment": "SEG_CLBLL_R_X23Y184", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y185": { + "bits": {}, + "grid_x": 60, + "grid_y": 15, + "segment": "SEG_CLBLL_R_X23Y185", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y186": { + "bits": {}, + "grid_x": 60, + "grid_y": 14, + "segment": "SEG_CLBLL_R_X23Y186", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y187": { + "bits": {}, + "grid_x": 60, + "grid_y": 13, + "segment": "SEG_CLBLL_R_X23Y187", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y188": { + "bits": {}, + "grid_x": 60, + "grid_y": 12, + "segment": "SEG_CLBLL_R_X23Y188", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y189": { + "bits": {}, + "grid_x": 60, + "grid_y": 11, + "segment": "SEG_CLBLL_R_X23Y189", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y19": { + "bits": {}, + "grid_x": 60, + "grid_y": 188, + "segment": "SEG_CLBLL_R_X23Y19", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y190": { + "bits": {}, + "grid_x": 60, + "grid_y": 10, + "segment": "SEG_CLBLL_R_X23Y190", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y191": { + "bits": {}, + "grid_x": 60, + "grid_y": 9, + "segment": "SEG_CLBLL_R_X23Y191", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y192": { + "bits": {}, + "grid_x": 60, + "grid_y": 8, + "segment": "SEG_CLBLL_R_X23Y192", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y193": { + "bits": {}, + "grid_x": 60, + "grid_y": 7, + "segment": "SEG_CLBLL_R_X23Y193", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y194": { + "bits": {}, + "grid_x": 60, + "grid_y": 6, + "segment": "SEG_CLBLL_R_X23Y194", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y195": { + "bits": {}, + "grid_x": 60, + "grid_y": 5, + "segment": "SEG_CLBLL_R_X23Y195", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y196": { + "bits": {}, + "grid_x": 60, + "grid_y": 4, + "segment": "SEG_CLBLL_R_X23Y196", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y197": { + "bits": {}, + "grid_x": 60, + "grid_y": 3, + "segment": "SEG_CLBLL_R_X23Y197", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y198": { + "bits": {}, + "grid_x": 60, + "grid_y": 2, + "segment": "SEG_CLBLL_R_X23Y198", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y199": { + "bits": {}, + "grid_x": 60, + "grid_y": 1, + "segment": "SEG_CLBLL_R_X23Y199", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y2": { + "bits": {}, + "grid_x": 60, + "grid_y": 205, + "segment": "SEG_CLBLL_R_X23Y2", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y20": { + "bits": {}, + "grid_x": 60, + "grid_y": 187, + "segment": "SEG_CLBLL_R_X23Y20", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y21": { + "bits": {}, + "grid_x": 60, + "grid_y": 186, + "segment": "SEG_CLBLL_R_X23Y21", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y22": { + "bits": {}, + "grid_x": 60, + "grid_y": 185, + "segment": "SEG_CLBLL_R_X23Y22", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y23": { + "bits": {}, + "grid_x": 60, + "grid_y": 184, + "segment": "SEG_CLBLL_R_X23Y23", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y24": { + "bits": {}, + "grid_x": 60, + "grid_y": 183, + "segment": "SEG_CLBLL_R_X23Y24", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y25": { + "bits": {}, + "grid_x": 60, + "grid_y": 181, + "segment": "SEG_CLBLL_R_X23Y25", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y26": { + "bits": {}, + "grid_x": 60, + "grid_y": 180, + "segment": "SEG_CLBLL_R_X23Y26", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y27": { + "bits": {}, + "grid_x": 60, + "grid_y": 179, + "segment": "SEG_CLBLL_R_X23Y27", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y28": { + "bits": {}, + "grid_x": 60, + "grid_y": 178, + "segment": "SEG_CLBLL_R_X23Y28", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y29": { + "bits": {}, + "grid_x": 60, + "grid_y": 177, + "segment": "SEG_CLBLL_R_X23Y29", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y3": { + "bits": {}, + "grid_x": 60, + "grid_y": 204, + "segment": "SEG_CLBLL_R_X23Y3", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y30": { + "bits": {}, + "grid_x": 60, + "grid_y": 176, + "segment": "SEG_CLBLL_R_X23Y30", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y31": { + "bits": {}, + "grid_x": 60, + "grid_y": 175, + "segment": "SEG_CLBLL_R_X23Y31", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y32": { + "bits": {}, + "grid_x": 60, + "grid_y": 174, + "segment": "SEG_CLBLL_R_X23Y32", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y33": { + "bits": {}, + "grid_x": 60, + "grid_y": 173, + "segment": "SEG_CLBLL_R_X23Y33", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y34": { + "bits": {}, + "grid_x": 60, + "grid_y": 172, + "segment": "SEG_CLBLL_R_X23Y34", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y35": { + "bits": {}, + "grid_x": 60, + "grid_y": 171, + "segment": "SEG_CLBLL_R_X23Y35", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y36": { + "bits": {}, + "grid_x": 60, + "grid_y": 170, + "segment": "SEG_CLBLL_R_X23Y36", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y37": { + "bits": {}, + "grid_x": 60, + "grid_y": 169, + "segment": "SEG_CLBLL_R_X23Y37", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y38": { + "bits": {}, + "grid_x": 60, + "grid_y": 168, + "segment": "SEG_CLBLL_R_X23Y38", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y39": { + "bits": {}, + "grid_x": 60, + "grid_y": 167, + "segment": "SEG_CLBLL_R_X23Y39", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y4": { + "bits": {}, + "grid_x": 60, + "grid_y": 203, + "segment": "SEG_CLBLL_R_X23Y4", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y40": { + "bits": {}, + "grid_x": 60, + "grid_y": 166, + "segment": "SEG_CLBLL_R_X23Y40", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y41": { + "bits": {}, + "grid_x": 60, + "grid_y": 165, + "segment": "SEG_CLBLL_R_X23Y41", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y42": { + "bits": {}, + "grid_x": 60, + "grid_y": 164, + "segment": "SEG_CLBLL_R_X23Y42", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y43": { + "bits": {}, + "grid_x": 60, + "grid_y": 163, + "segment": "SEG_CLBLL_R_X23Y43", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y44": { + "bits": {}, + "grid_x": 60, + "grid_y": 162, + "segment": "SEG_CLBLL_R_X23Y44", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y45": { + "bits": {}, + "grid_x": 60, + "grid_y": 161, + "segment": "SEG_CLBLL_R_X23Y45", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y46": { + "bits": {}, + "grid_x": 60, + "grid_y": 160, + "segment": "SEG_CLBLL_R_X23Y46", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y47": { + "bits": {}, + "grid_x": 60, + "grid_y": 159, + "segment": "SEG_CLBLL_R_X23Y47", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y48": { + "bits": {}, + "grid_x": 60, + "grid_y": 158, + "segment": "SEG_CLBLL_R_X23Y48", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y49": { + "bits": {}, + "grid_x": 60, + "grid_y": 157, + "segment": "SEG_CLBLL_R_X23Y49", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y5": { + "bits": {}, + "grid_x": 60, + "grid_y": 202, + "segment": "SEG_CLBLL_R_X23Y5", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y6": { + "bits": {}, + "grid_x": 60, + "grid_y": 201, + "segment": "SEG_CLBLL_R_X23Y6", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y7": { + "bits": {}, + "grid_x": 60, + "grid_y": 200, + "segment": "SEG_CLBLL_R_X23Y7", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y8": { + "bits": {}, + "grid_x": 60, + "grid_y": 199, + "segment": "SEG_CLBLL_R_X23Y8", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X23Y9": { + "bits": {}, + "grid_x": 60, + "grid_y": 198, + "segment": "SEG_CLBLL_R_X23Y9", + "segment_type": "clbll_r", + "sites": { + "TIEOFF_X25Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y0": { + "bits": {}, + "grid_x": 65, + "grid_y": 207, + "sites": { + "TIEOFF_X27Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y1": { + "bits": {}, + "grid_x": 65, + "grid_y": 206, + "sites": { + "TIEOFF_X27Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y10": { + "bits": {}, + "grid_x": 65, + "grid_y": 197, + "sites": { + "TIEOFF_X27Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y100": { + "bits": {}, + "grid_x": 65, + "grid_y": 103, + "sites": { + "TIEOFF_X27Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y101": { + "bits": {}, + "grid_x": 65, + "grid_y": 102, + "sites": { + "TIEOFF_X27Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y102": { + "bits": {}, + "grid_x": 65, + "grid_y": 101, + "sites": { + "TIEOFF_X27Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y103": { + "bits": {}, + "grid_x": 65, + "grid_y": 100, + "sites": { + "TIEOFF_X27Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y104": { + "bits": {}, + "grid_x": 65, + "grid_y": 99, + "sites": { + "TIEOFF_X27Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y105": { + "bits": {}, + "grid_x": 65, + "grid_y": 98, + "sites": { + "TIEOFF_X27Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y106": { + "bits": {}, + "grid_x": 65, + "grid_y": 97, + "sites": { + "TIEOFF_X27Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y107": { + "bits": {}, + "grid_x": 65, + "grid_y": 96, + "sites": { + "TIEOFF_X27Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y108": { + "bits": {}, + "grid_x": 65, + "grid_y": 95, + "sites": { + "TIEOFF_X27Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y109": { + "bits": {}, + "grid_x": 65, + "grid_y": 94, + "sites": { + "TIEOFF_X27Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y11": { + "bits": {}, + "grid_x": 65, + "grid_y": 196, + "sites": { + "TIEOFF_X27Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y110": { + "bits": {}, + "grid_x": 65, + "grid_y": 93, + "sites": { + "TIEOFF_X27Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y111": { + "bits": {}, + "grid_x": 65, + "grid_y": 92, + "sites": { + "TIEOFF_X27Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y112": { + "bits": {}, + "grid_x": 65, + "grid_y": 91, + "sites": { + "TIEOFF_X27Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y113": { + "bits": {}, + "grid_x": 65, + "grid_y": 90, + "sites": { + "TIEOFF_X27Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y114": { + "bits": {}, + "grid_x": 65, + "grid_y": 89, + "sites": { + "TIEOFF_X27Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y115": { + "bits": {}, + "grid_x": 65, + "grid_y": 88, + "sites": { + "TIEOFF_X27Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y116": { + "bits": {}, + "grid_x": 65, + "grid_y": 87, + "sites": { + "TIEOFF_X27Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y117": { + "bits": {}, + "grid_x": 65, + "grid_y": 86, + "sites": { + "TIEOFF_X27Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y118": { + "bits": {}, + "grid_x": 65, + "grid_y": 85, + "sites": { + "TIEOFF_X27Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y119": { + "bits": {}, + "grid_x": 65, + "grid_y": 84, + "sites": { + "TIEOFF_X27Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y12": { + "bits": {}, + "grid_x": 65, + "grid_y": 195, + "sites": { + "TIEOFF_X27Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y120": { + "bits": {}, + "grid_x": 65, + "grid_y": 83, + "sites": { + "TIEOFF_X27Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y121": { + "bits": {}, + "grid_x": 65, + "grid_y": 82, + "sites": { + "TIEOFF_X27Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y122": { + "bits": {}, + "grid_x": 65, + "grid_y": 81, + "sites": { + "TIEOFF_X27Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y123": { + "bits": {}, + "grid_x": 65, + "grid_y": 80, + "sites": { + "TIEOFF_X27Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y124": { + "bits": {}, + "grid_x": 65, + "grid_y": 79, + "sites": { + "TIEOFF_X27Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y125": { + "bits": {}, + "grid_x": 65, + "grid_y": 77, + "sites": { + "TIEOFF_X27Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y126": { + "bits": {}, + "grid_x": 65, + "grid_y": 76, + "sites": { + "TIEOFF_X27Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y127": { + "bits": {}, + "grid_x": 65, + "grid_y": 75, + "sites": { + "TIEOFF_X27Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y128": { + "bits": {}, + "grid_x": 65, + "grid_y": 74, + "sites": { + "TIEOFF_X27Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y129": { + "bits": {}, + "grid_x": 65, + "grid_y": 73, + "sites": { + "TIEOFF_X27Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y13": { + "bits": {}, + "grid_x": 65, + "grid_y": 194, + "sites": { + "TIEOFF_X27Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y130": { + "bits": {}, + "grid_x": 65, + "grid_y": 72, + "sites": { + "TIEOFF_X27Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y131": { + "bits": {}, + "grid_x": 65, + "grid_y": 71, + "sites": { + "TIEOFF_X27Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y132": { + "bits": {}, + "grid_x": 65, + "grid_y": 70, + "sites": { + "TIEOFF_X27Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y133": { + "bits": {}, + "grid_x": 65, + "grid_y": 69, + "sites": { + "TIEOFF_X27Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y134": { + "bits": {}, + "grid_x": 65, + "grid_y": 68, + "sites": { + "TIEOFF_X27Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y135": { + "bits": {}, + "grid_x": 65, + "grid_y": 67, + "sites": { + "TIEOFF_X27Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y136": { + "bits": {}, + "grid_x": 65, + "grid_y": 66, + "sites": { + "TIEOFF_X27Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y137": { + "bits": {}, + "grid_x": 65, + "grid_y": 65, + "sites": { + "TIEOFF_X27Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y138": { + "bits": {}, + "grid_x": 65, + "grid_y": 64, + "sites": { + "TIEOFF_X27Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y139": { + "bits": {}, + "grid_x": 65, + "grid_y": 63, + "sites": { + "TIEOFF_X27Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y14": { + "bits": {}, + "grid_x": 65, + "grid_y": 193, + "sites": { + "TIEOFF_X27Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y140": { + "bits": {}, + "grid_x": 65, + "grid_y": 62, + "sites": { + "TIEOFF_X27Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y141": { + "bits": {}, + "grid_x": 65, + "grid_y": 61, + "sites": { + "TIEOFF_X27Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y142": { + "bits": {}, + "grid_x": 65, + "grid_y": 60, + "sites": { + "TIEOFF_X27Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y143": { + "bits": {}, + "grid_x": 65, + "grid_y": 59, + "sites": { + "TIEOFF_X27Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y144": { + "bits": {}, + "grid_x": 65, + "grid_y": 58, + "sites": { + "TIEOFF_X27Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y145": { + "bits": {}, + "grid_x": 65, + "grid_y": 57, + "sites": { + "TIEOFF_X27Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y146": { + "bits": {}, + "grid_x": 65, + "grid_y": 56, + "sites": { + "TIEOFF_X27Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y147": { + "bits": {}, + "grid_x": 65, + "grid_y": 55, + "sites": { + "TIEOFF_X27Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y148": { + "bits": {}, + "grid_x": 65, + "grid_y": 54, + "sites": { + "TIEOFF_X27Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y149": { + "bits": {}, + "grid_x": 65, + "grid_y": 53, + "sites": { + "TIEOFF_X27Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y15": { + "bits": {}, + "grid_x": 65, + "grid_y": 192, + "sites": { + "TIEOFF_X27Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y150": { + "bits": {}, + "grid_x": 65, + "grid_y": 51, + "sites": { + "TIEOFF_X27Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y151": { + "bits": {}, + "grid_x": 65, + "grid_y": 50, + "sites": { + "TIEOFF_X27Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y152": { + "bits": {}, + "grid_x": 65, + "grid_y": 49, + "sites": { + "TIEOFF_X27Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y153": { + "bits": {}, + "grid_x": 65, + "grid_y": 48, + "sites": { + "TIEOFF_X27Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y154": { + "bits": {}, + "grid_x": 65, + "grid_y": 47, + "sites": { + "TIEOFF_X27Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y155": { + "bits": {}, + "grid_x": 65, + "grid_y": 46, + "sites": { + "TIEOFF_X27Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y156": { + "bits": {}, + "grid_x": 65, + "grid_y": 45, + "sites": { + "TIEOFF_X27Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y157": { + "bits": {}, + "grid_x": 65, + "grid_y": 44, + "sites": { + "TIEOFF_X27Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y158": { + "bits": {}, + "grid_x": 65, + "grid_y": 43, + "sites": { + "TIEOFF_X27Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y159": { + "bits": {}, + "grid_x": 65, + "grid_y": 42, + "sites": { + "TIEOFF_X27Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y16": { + "bits": {}, + "grid_x": 65, + "grid_y": 191, + "sites": { + "TIEOFF_X27Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y160": { + "bits": {}, + "grid_x": 65, + "grid_y": 41, + "sites": { + "TIEOFF_X27Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y161": { + "bits": {}, + "grid_x": 65, + "grid_y": 40, + "sites": { + "TIEOFF_X27Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y162": { + "bits": {}, + "grid_x": 65, + "grid_y": 39, + "sites": { + "TIEOFF_X27Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y163": { + "bits": {}, + "grid_x": 65, + "grid_y": 38, + "sites": { + "TIEOFF_X27Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y164": { + "bits": {}, + "grid_x": 65, + "grid_y": 37, + "sites": { + "TIEOFF_X27Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y165": { + "bits": {}, + "grid_x": 65, + "grid_y": 36, + "sites": { + "TIEOFF_X27Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y166": { + "bits": {}, + "grid_x": 65, + "grid_y": 35, + "sites": { + "TIEOFF_X27Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y167": { + "bits": {}, + "grid_x": 65, + "grid_y": 34, + "sites": { + "TIEOFF_X27Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y168": { + "bits": {}, + "grid_x": 65, + "grid_y": 33, + "sites": { + "TIEOFF_X27Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y169": { + "bits": {}, + "grid_x": 65, + "grid_y": 32, + "sites": { + "TIEOFF_X27Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y17": { + "bits": {}, + "grid_x": 65, + "grid_y": 190, + "sites": { + "TIEOFF_X27Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y170": { + "bits": {}, + "grid_x": 65, + "grid_y": 31, + "sites": { + "TIEOFF_X27Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y171": { + "bits": {}, + "grid_x": 65, + "grid_y": 30, + "sites": { + "TIEOFF_X27Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y172": { + "bits": {}, + "grid_x": 65, + "grid_y": 29, + "sites": { + "TIEOFF_X27Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y173": { + "bits": {}, + "grid_x": 65, + "grid_y": 28, + "sites": { + "TIEOFF_X27Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y174": { + "bits": {}, + "grid_x": 65, + "grid_y": 27, + "sites": { + "TIEOFF_X27Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y175": { + "bits": {}, + "grid_x": 65, + "grid_y": 25, + "sites": { + "TIEOFF_X27Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y176": { + "bits": {}, + "grid_x": 65, + "grid_y": 24, + "sites": { + "TIEOFF_X27Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y177": { + "bits": {}, + "grid_x": 65, + "grid_y": 23, + "sites": { + "TIEOFF_X27Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y178": { + "bits": {}, + "grid_x": 65, + "grid_y": 22, + "sites": { + "TIEOFF_X27Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y179": { + "bits": {}, + "grid_x": 65, + "grid_y": 21, + "sites": { + "TIEOFF_X27Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y18": { + "bits": {}, + "grid_x": 65, + "grid_y": 189, + "sites": { + "TIEOFF_X27Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y180": { + "bits": {}, + "grid_x": 65, + "grid_y": 20, + "sites": { + "TIEOFF_X27Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y181": { + "bits": {}, + "grid_x": 65, + "grid_y": 19, + "sites": { + "TIEOFF_X27Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y182": { + "bits": {}, + "grid_x": 65, + "grid_y": 18, + "sites": { + "TIEOFF_X27Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y183": { + "bits": {}, + "grid_x": 65, + "grid_y": 17, + "sites": { + "TIEOFF_X27Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y184": { + "bits": {}, + "grid_x": 65, + "grid_y": 16, + "sites": { + "TIEOFF_X27Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y185": { + "bits": {}, + "grid_x": 65, + "grid_y": 15, + "sites": { + "TIEOFF_X27Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y186": { + "bits": {}, + "grid_x": 65, + "grid_y": 14, + "sites": { + "TIEOFF_X27Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y187": { + "bits": {}, + "grid_x": 65, + "grid_y": 13, + "sites": { + "TIEOFF_X27Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y188": { + "bits": {}, + "grid_x": 65, + "grid_y": 12, + "sites": { + "TIEOFF_X27Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y189": { + "bits": {}, + "grid_x": 65, + "grid_y": 11, + "sites": { + "TIEOFF_X27Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y19": { + "bits": {}, + "grid_x": 65, + "grid_y": 188, + "sites": { + "TIEOFF_X27Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y190": { + "bits": {}, + "grid_x": 65, + "grid_y": 10, + "sites": { + "TIEOFF_X27Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y191": { + "bits": {}, + "grid_x": 65, + "grid_y": 9, + "sites": { + "TIEOFF_X27Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y192": { + "bits": {}, + "grid_x": 65, + "grid_y": 8, + "sites": { + "TIEOFF_X27Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y193": { + "bits": {}, + "grid_x": 65, + "grid_y": 7, + "sites": { + "TIEOFF_X27Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y194": { + "bits": {}, + "grid_x": 65, + "grid_y": 6, + "sites": { + "TIEOFF_X27Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y195": { + "bits": {}, + "grid_x": 65, + "grid_y": 5, + "sites": { + "TIEOFF_X27Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y196": { + "bits": {}, + "grid_x": 65, + "grid_y": 4, + "sites": { + "TIEOFF_X27Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y197": { + "bits": {}, + "grid_x": 65, + "grid_y": 3, + "sites": { + "TIEOFF_X27Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y198": { + "bits": {}, + "grid_x": 65, + "grid_y": 2, + "sites": { + "TIEOFF_X27Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y199": { + "bits": {}, + "grid_x": 65, + "grid_y": 1, + "sites": { + "TIEOFF_X27Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y2": { + "bits": {}, + "grid_x": 65, + "grid_y": 205, + "sites": { + "TIEOFF_X27Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y20": { + "bits": {}, + "grid_x": 65, + "grid_y": 187, + "sites": { + "TIEOFF_X27Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y21": { + "bits": {}, + "grid_x": 65, + "grid_y": 186, + "sites": { + "TIEOFF_X27Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y22": { + "bits": {}, + "grid_x": 65, + "grid_y": 185, + "sites": { + "TIEOFF_X27Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y23": { + "bits": {}, + "grid_x": 65, + "grid_y": 184, + "sites": { + "TIEOFF_X27Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y24": { + "bits": {}, + "grid_x": 65, + "grid_y": 183, + "sites": { + "TIEOFF_X27Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y25": { + "bits": {}, + "grid_x": 65, + "grid_y": 181, + "sites": { + "TIEOFF_X27Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y26": { + "bits": {}, + "grid_x": 65, + "grid_y": 180, + "sites": { + "TIEOFF_X27Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y27": { + "bits": {}, + "grid_x": 65, + "grid_y": 179, + "sites": { + "TIEOFF_X27Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y28": { + "bits": {}, + "grid_x": 65, + "grid_y": 178, + "sites": { + "TIEOFF_X27Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y29": { + "bits": {}, + "grid_x": 65, + "grid_y": 177, + "sites": { + "TIEOFF_X27Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y3": { + "bits": {}, + "grid_x": 65, + "grid_y": 204, + "sites": { + "TIEOFF_X27Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y30": { + "bits": {}, + "grid_x": 65, + "grid_y": 176, + "sites": { + "TIEOFF_X27Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y31": { + "bits": {}, + "grid_x": 65, + "grid_y": 175, + "sites": { + "TIEOFF_X27Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y32": { + "bits": {}, + "grid_x": 65, + "grid_y": 174, + "sites": { + "TIEOFF_X27Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y33": { + "bits": {}, + "grid_x": 65, + "grid_y": 173, + "sites": { + "TIEOFF_X27Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y34": { + "bits": {}, + "grid_x": 65, + "grid_y": 172, + "sites": { + "TIEOFF_X27Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y35": { + "bits": {}, + "grid_x": 65, + "grid_y": 171, + "sites": { + "TIEOFF_X27Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y36": { + "bits": {}, + "grid_x": 65, + "grid_y": 170, + "sites": { + "TIEOFF_X27Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y37": { + "bits": {}, + "grid_x": 65, + "grid_y": 169, + "sites": { + "TIEOFF_X27Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y38": { + "bits": {}, + "grid_x": 65, + "grid_y": 168, + "sites": { + "TIEOFF_X27Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y39": { + "bits": {}, + "grid_x": 65, + "grid_y": 167, + "sites": { + "TIEOFF_X27Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y4": { + "bits": {}, + "grid_x": 65, + "grid_y": 203, + "sites": { + "TIEOFF_X27Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y40": { + "bits": {}, + "grid_x": 65, + "grid_y": 166, + "sites": { + "TIEOFF_X27Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y41": { + "bits": {}, + "grid_x": 65, + "grid_y": 165, + "sites": { + "TIEOFF_X27Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y42": { + "bits": {}, + "grid_x": 65, + "grid_y": 164, + "sites": { + "TIEOFF_X27Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y43": { + "bits": {}, + "grid_x": 65, + "grid_y": 163, + "sites": { + "TIEOFF_X27Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y44": { + "bits": {}, + "grid_x": 65, + "grid_y": 162, + "sites": { + "TIEOFF_X27Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y45": { + "bits": {}, + "grid_x": 65, + "grid_y": 161, + "sites": { + "TIEOFF_X27Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y46": { + "bits": {}, + "grid_x": 65, + "grid_y": 160, + "sites": { + "TIEOFF_X27Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y47": { + "bits": {}, + "grid_x": 65, + "grid_y": 159, + "sites": { + "TIEOFF_X27Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y48": { + "bits": {}, + "grid_x": 65, + "grid_y": 158, + "sites": { + "TIEOFF_X27Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y49": { + "bits": {}, + "grid_x": 65, + "grid_y": 157, + "sites": { + "TIEOFF_X27Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y5": { + "bits": {}, + "grid_x": 65, + "grid_y": 202, + "sites": { + "TIEOFF_X27Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y50": { + "bits": {}, + "grid_x": 65, + "grid_y": 155, + "sites": { + "TIEOFF_X27Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y51": { + "bits": {}, + "grid_x": 65, + "grid_y": 154, + "sites": { + "TIEOFF_X27Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y52": { + "bits": {}, + "grid_x": 65, + "grid_y": 153, + "sites": { + "TIEOFF_X27Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y53": { + "bits": {}, + "grid_x": 65, + "grid_y": 152, + "sites": { + "TIEOFF_X27Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y54": { + "bits": {}, + "grid_x": 65, + "grid_y": 151, + "sites": { + "TIEOFF_X27Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y55": { + "bits": {}, + "grid_x": 65, + "grid_y": 150, + "sites": { + "TIEOFF_X27Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y56": { + "bits": {}, + "grid_x": 65, + "grid_y": 149, + "sites": { + "TIEOFF_X27Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y57": { + "bits": {}, + "grid_x": 65, + "grid_y": 148, + "sites": { + "TIEOFF_X27Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y58": { + "bits": {}, + "grid_x": 65, + "grid_y": 147, + "sites": { + "TIEOFF_X27Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y59": { + "bits": {}, + "grid_x": 65, + "grid_y": 146, + "sites": { + "TIEOFF_X27Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y6": { + "bits": {}, + "grid_x": 65, + "grid_y": 201, + "sites": { + "TIEOFF_X27Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y60": { + "bits": {}, + "grid_x": 65, + "grid_y": 145, + "sites": { + "TIEOFF_X27Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y61": { + "bits": {}, + "grid_x": 65, + "grid_y": 144, + "sites": { + "TIEOFF_X27Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y62": { + "bits": {}, + "grid_x": 65, + "grid_y": 143, + "sites": { + "TIEOFF_X27Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y63": { + "bits": {}, + "grid_x": 65, + "grid_y": 142, + "sites": { + "TIEOFF_X27Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y64": { + "bits": {}, + "grid_x": 65, + "grid_y": 141, + "sites": { + "TIEOFF_X27Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y65": { + "bits": {}, + "grid_x": 65, + "grid_y": 140, + "sites": { + "TIEOFF_X27Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y66": { + "bits": {}, + "grid_x": 65, + "grid_y": 139, + "sites": { + "TIEOFF_X27Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y67": { + "bits": {}, + "grid_x": 65, + "grid_y": 138, + "sites": { + "TIEOFF_X27Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y68": { + "bits": {}, + "grid_x": 65, + "grid_y": 137, + "sites": { + "TIEOFF_X27Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y69": { + "bits": {}, + "grid_x": 65, + "grid_y": 136, + "sites": { + "TIEOFF_X27Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y7": { + "bits": {}, + "grid_x": 65, + "grid_y": 200, + "sites": { + "TIEOFF_X27Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y70": { + "bits": {}, + "grid_x": 65, + "grid_y": 135, + "sites": { + "TIEOFF_X27Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y71": { + "bits": {}, + "grid_x": 65, + "grid_y": 134, + "sites": { + "TIEOFF_X27Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y72": { + "bits": {}, + "grid_x": 65, + "grid_y": 133, + "sites": { + "TIEOFF_X27Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y73": { + "bits": {}, + "grid_x": 65, + "grid_y": 132, + "sites": { + "TIEOFF_X27Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y74": { + "bits": {}, + "grid_x": 65, + "grid_y": 131, + "sites": { + "TIEOFF_X27Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y75": { + "bits": {}, + "grid_x": 65, + "grid_y": 129, + "sites": { + "TIEOFF_X27Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y76": { + "bits": {}, + "grid_x": 65, + "grid_y": 128, + "sites": { + "TIEOFF_X27Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y77": { + "bits": {}, + "grid_x": 65, + "grid_y": 127, + "sites": { + "TIEOFF_X27Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y78": { + "bits": {}, + "grid_x": 65, + "grid_y": 126, + "sites": { + "TIEOFF_X27Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y79": { + "bits": {}, + "grid_x": 65, + "grid_y": 125, + "sites": { + "TIEOFF_X27Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y8": { + "bits": {}, + "grid_x": 65, + "grid_y": 199, + "sites": { + "TIEOFF_X27Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y80": { + "bits": {}, + "grid_x": 65, + "grid_y": 124, + "sites": { + "TIEOFF_X27Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y81": { + "bits": {}, + "grid_x": 65, + "grid_y": 123, + "sites": { + "TIEOFF_X27Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y82": { + "bits": {}, + "grid_x": 65, + "grid_y": 122, + "sites": { + "TIEOFF_X27Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y83": { + "bits": {}, + "grid_x": 65, + "grid_y": 121, + "sites": { + "TIEOFF_X27Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y84": { + "bits": {}, + "grid_x": 65, + "grid_y": 120, + "sites": { + "TIEOFF_X27Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y85": { + "bits": {}, + "grid_x": 65, + "grid_y": 119, + "sites": { + "TIEOFF_X27Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y86": { + "bits": {}, + "grid_x": 65, + "grid_y": 118, + "sites": { + "TIEOFF_X27Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y87": { + "bits": {}, + "grid_x": 65, + "grid_y": 117, + "sites": { + "TIEOFF_X27Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y88": { + "bits": {}, + "grid_x": 65, + "grid_y": 116, + "sites": { + "TIEOFF_X27Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y89": { + "bits": {}, + "grid_x": 65, + "grid_y": 115, + "sites": { + "TIEOFF_X27Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y9": { + "bits": {}, + "grid_x": 65, + "grid_y": 198, + "sites": { + "TIEOFF_X27Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y90": { + "bits": {}, + "grid_x": 65, + "grid_y": 114, + "sites": { + "TIEOFF_X27Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y91": { + "bits": {}, + "grid_x": 65, + "grid_y": 113, + "sites": { + "TIEOFF_X27Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y92": { + "bits": {}, + "grid_x": 65, + "grid_y": 112, + "sites": { + "TIEOFF_X27Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y93": { + "bits": {}, + "grid_x": 65, + "grid_y": 111, + "sites": { + "TIEOFF_X27Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y94": { + "bits": {}, + "grid_x": 65, + "grid_y": 110, + "sites": { + "TIEOFF_X27Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y95": { + "bits": {}, + "grid_x": 65, + "grid_y": 109, + "sites": { + "TIEOFF_X27Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y96": { + "bits": {}, + "grid_x": 65, + "grid_y": 108, + "sites": { + "TIEOFF_X27Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y97": { + "bits": {}, + "grid_x": 65, + "grid_y": 107, + "sites": { + "TIEOFF_X27Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y98": { + "bits": {}, + "grid_x": 65, + "grid_y": 106, + "sites": { + "TIEOFF_X27Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X25Y99": { + "bits": {}, + "grid_x": 65, + "grid_y": 105, + "sites": { + "TIEOFF_X27Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y0": { + "bits": {}, + "grid_x": 71, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X27Y0", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y1": { + "bits": {}, + "grid_x": 71, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X27Y1", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y10": { + "bits": {}, + "grid_x": 71, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X27Y10", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y100": { + "bits": {}, + "grid_x": 71, + "grid_y": 103, + "sites": { + "TIEOFF_X29Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y101": { + "bits": {}, + "grid_x": 71, + "grid_y": 102, + "sites": { + "TIEOFF_X29Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y102": { + "bits": {}, + "grid_x": 71, + "grid_y": 101, + "sites": { + "TIEOFF_X29Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y103": { + "bits": {}, + "grid_x": 71, + "grid_y": 100, + "sites": { + "TIEOFF_X29Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y104": { + "bits": {}, + "grid_x": 71, + "grid_y": 99, + "sites": { + "TIEOFF_X29Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y105": { + "bits": {}, + "grid_x": 71, + "grid_y": 98, + "sites": { + "TIEOFF_X29Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y106": { + "bits": {}, + "grid_x": 71, + "grid_y": 97, + "sites": { + "TIEOFF_X29Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y107": { + "bits": {}, + "grid_x": 71, + "grid_y": 96, + "sites": { + "TIEOFF_X29Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y108": { + "bits": {}, + "grid_x": 71, + "grid_y": 95, + "sites": { + "TIEOFF_X29Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y109": { + "bits": {}, + "grid_x": 71, + "grid_y": 94, + "sites": { + "TIEOFF_X29Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y11": { + "bits": {}, + "grid_x": 71, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X27Y11", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y110": { + "bits": {}, + "grid_x": 71, + "grid_y": 93, + "sites": { + "TIEOFF_X29Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y111": { + "bits": {}, + "grid_x": 71, + "grid_y": 92, + "sites": { + "TIEOFF_X29Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y112": { + "bits": {}, + "grid_x": 71, + "grid_y": 91, + "sites": { + "TIEOFF_X29Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y113": { + "bits": {}, + "grid_x": 71, + "grid_y": 90, + "sites": { + "TIEOFF_X29Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y114": { + "bits": {}, + "grid_x": 71, + "grid_y": 89, + "sites": { + "TIEOFF_X29Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y115": { + "bits": {}, + "grid_x": 71, + "grid_y": 88, + "sites": { + "TIEOFF_X29Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y116": { + "bits": {}, + "grid_x": 71, + "grid_y": 87, + "sites": { + "TIEOFF_X29Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y117": { + "bits": {}, + "grid_x": 71, + "grid_y": 86, + "sites": { + "TIEOFF_X29Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y118": { + "bits": {}, + "grid_x": 71, + "grid_y": 85, + "sites": { + "TIEOFF_X29Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y119": { + "bits": {}, + "grid_x": 71, + "grid_y": 84, + "sites": { + "TIEOFF_X29Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y12": { + "bits": {}, + "grid_x": 71, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X27Y12", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y120": { + "bits": {}, + "grid_x": 71, + "grid_y": 83, + "sites": { + "TIEOFF_X29Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y121": { + "bits": {}, + "grid_x": 71, + "grid_y": 82, + "sites": { + "TIEOFF_X29Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y122": { + "bits": {}, + "grid_x": 71, + "grid_y": 81, + "sites": { + "TIEOFF_X29Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y123": { + "bits": {}, + "grid_x": 71, + "grid_y": 80, + "sites": { + "TIEOFF_X29Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y124": { + "bits": {}, + "grid_x": 71, + "grid_y": 79, + "sites": { + "TIEOFF_X29Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y125": { + "bits": {}, + "grid_x": 71, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X27Y125", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y126": { + "bits": {}, + "grid_x": 71, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X27Y126", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y127": { + "bits": {}, + "grid_x": 71, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X27Y127", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y128": { + "bits": {}, + "grid_x": 71, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X27Y128", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y129": { + "bits": {}, + "grid_x": 71, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X27Y129", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y13": { + "bits": {}, + "grid_x": 71, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X27Y13", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y130": { + "bits": {}, + "grid_x": 71, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X27Y130", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y131": { + "bits": {}, + "grid_x": 71, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X27Y131", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y132": { + "bits": {}, + "grid_x": 71, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X27Y132", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y133": { + "bits": {}, + "grid_x": 71, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X27Y133", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y134": { + "bits": {}, + "grid_x": 71, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X27Y134", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y135": { + "bits": {}, + "grid_x": 71, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X27Y135", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y136": { + "bits": {}, + "grid_x": 71, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X27Y136", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y137": { + "bits": {}, + "grid_x": 71, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X27Y137", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y138": { + "bits": {}, + "grid_x": 71, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X27Y138", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y139": { + "bits": {}, + "grid_x": 71, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X27Y139", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y14": { + "bits": {}, + "grid_x": 71, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X27Y14", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y140": { + "bits": {}, + "grid_x": 71, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X27Y140", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y141": { + "bits": {}, + "grid_x": 71, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X27Y141", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y142": { + "bits": {}, + "grid_x": 71, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X27Y142", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y143": { + "bits": {}, + "grid_x": 71, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X27Y143", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y144": { + "bits": {}, + "grid_x": 71, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X27Y144", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y145": { + "bits": {}, + "grid_x": 71, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X27Y145", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y146": { + "bits": {}, + "grid_x": 71, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X27Y146", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y147": { + "bits": {}, + "grid_x": 71, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X27Y147", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y148": { + "bits": {}, + "grid_x": 71, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X27Y148", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y149": { + "bits": {}, + "grid_x": 71, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X27Y149", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y15": { + "bits": {}, + "grid_x": 71, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X27Y15", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y150": { + "bits": {}, + "grid_x": 71, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X27Y150", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y151": { + "bits": {}, + "grid_x": 71, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X27Y151", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y152": { + "bits": {}, + "grid_x": 71, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X27Y152", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y153": { + "bits": {}, + "grid_x": 71, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X27Y153", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y154": { + "bits": {}, + "grid_x": 71, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X27Y154", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y155": { + "bits": {}, + "grid_x": 71, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X27Y155", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y156": { + "bits": {}, + "grid_x": 71, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X27Y156", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y157": { + "bits": {}, + "grid_x": 71, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X27Y157", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y158": { + "bits": {}, + "grid_x": 71, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X27Y158", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y159": { + "bits": {}, + "grid_x": 71, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X27Y159", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y16": { + "bits": {}, + "grid_x": 71, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X27Y16", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y160": { + "bits": {}, + "grid_x": 71, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X27Y160", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y161": { + "bits": {}, + "grid_x": 71, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X27Y161", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y162": { + "bits": {}, + "grid_x": 71, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X27Y162", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y163": { + "bits": {}, + "grid_x": 71, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X27Y163", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y164": { + "bits": {}, + "grid_x": 71, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X27Y164", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y165": { + "bits": {}, + "grid_x": 71, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X27Y165", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y166": { + "bits": {}, + "grid_x": 71, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X27Y166", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y167": { + "bits": {}, + "grid_x": 71, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X27Y167", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y168": { + "bits": {}, + "grid_x": 71, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X27Y168", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y169": { + "bits": {}, + "grid_x": 71, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X27Y169", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y17": { + "bits": {}, + "grid_x": 71, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X27Y17", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y170": { + "bits": {}, + "grid_x": 71, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X27Y170", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y171": { + "bits": {}, + "grid_x": 71, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X27Y171", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y172": { + "bits": {}, + "grid_x": 71, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X27Y172", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y173": { + "bits": {}, + "grid_x": 71, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X27Y173", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y174": { + "bits": {}, + "grid_x": 71, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X27Y174", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y175": { + "bits": {}, + "grid_x": 71, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X27Y175", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y176": { + "bits": {}, + "grid_x": 71, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X27Y176", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y177": { + "bits": {}, + "grid_x": 71, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X27Y177", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y178": { + "bits": {}, + "grid_x": 71, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X27Y178", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y179": { + "bits": {}, + "grid_x": 71, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X27Y179", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y18": { + "bits": {}, + "grid_x": 71, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X27Y18", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y180": { + "bits": {}, + "grid_x": 71, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X27Y180", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y181": { + "bits": {}, + "grid_x": 71, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X27Y181", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y182": { + "bits": {}, + "grid_x": 71, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X27Y182", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y183": { + "bits": {}, + "grid_x": 71, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X27Y183", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y184": { + "bits": {}, + "grid_x": 71, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X27Y184", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y185": { + "bits": {}, + "grid_x": 71, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X27Y185", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y186": { + "bits": {}, + "grid_x": 71, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X27Y186", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y187": { + "bits": {}, + "grid_x": 71, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X27Y187", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y188": { + "bits": {}, + "grid_x": 71, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X27Y188", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y189": { + "bits": {}, + "grid_x": 71, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X27Y189", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y19": { + "bits": {}, + "grid_x": 71, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X27Y19", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y190": { + "bits": {}, + "grid_x": 71, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X27Y190", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y191": { + "bits": {}, + "grid_x": 71, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X27Y191", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y192": { + "bits": {}, + "grid_x": 71, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X27Y192", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y193": { + "bits": {}, + "grid_x": 71, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X27Y193", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y194": { + "bits": {}, + "grid_x": 71, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X27Y194", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y195": { + "bits": {}, + "grid_x": 71, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X27Y195", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y196": { + "bits": {}, + "grid_x": 71, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X27Y196", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y197": { + "bits": {}, + "grid_x": 71, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X27Y197", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y198": { + "bits": {}, + "grid_x": 71, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X27Y198", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y199": { + "bits": {}, + "grid_x": 71, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X27Y199", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y2": { + "bits": {}, + "grid_x": 71, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X27Y2", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y20": { + "bits": {}, + "grid_x": 71, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X27Y20", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y21": { + "bits": {}, + "grid_x": 71, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X27Y21", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y22": { + "bits": {}, + "grid_x": 71, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X27Y22", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y23": { + "bits": {}, + "grid_x": 71, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X27Y23", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y24": { + "bits": {}, + "grid_x": 71, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X27Y24", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y25": { + "bits": {}, + "grid_x": 71, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X27Y25", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y26": { + "bits": {}, + "grid_x": 71, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X27Y26", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y27": { + "bits": {}, + "grid_x": 71, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X27Y27", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y28": { + "bits": {}, + "grid_x": 71, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X27Y28", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y29": { + "bits": {}, + "grid_x": 71, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X27Y29", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y3": { + "bits": {}, + "grid_x": 71, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X27Y3", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y30": { + "bits": {}, + "grid_x": 71, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X27Y30", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y31": { + "bits": {}, + "grid_x": 71, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X27Y31", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y32": { + "bits": {}, + "grid_x": 71, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X27Y32", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y33": { + "bits": {}, + "grid_x": 71, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X27Y33", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y34": { + "bits": {}, + "grid_x": 71, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X27Y34", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y35": { + "bits": {}, + "grid_x": 71, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X27Y35", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y36": { + "bits": {}, + "grid_x": 71, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X27Y36", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y37": { + "bits": {}, + "grid_x": 71, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X27Y37", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y38": { + "bits": {}, + "grid_x": 71, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X27Y38", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y39": { + "bits": {}, + "grid_x": 71, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X27Y39", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y4": { + "bits": {}, + "grid_x": 71, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X27Y4", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y40": { + "bits": {}, + "grid_x": 71, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X27Y40", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y41": { + "bits": {}, + "grid_x": 71, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X27Y41", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y42": { + "bits": {}, + "grid_x": 71, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X27Y42", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y43": { + "bits": {}, + "grid_x": 71, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X27Y43", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y44": { + "bits": {}, + "grid_x": 71, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X27Y44", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y45": { + "bits": {}, + "grid_x": 71, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X27Y45", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y46": { + "bits": {}, + "grid_x": 71, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X27Y46", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y47": { + "bits": {}, + "grid_x": 71, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X27Y47", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y48": { + "bits": {}, + "grid_x": 71, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X27Y48", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y49": { + "bits": {}, + "grid_x": 71, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X27Y49", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y5": { + "bits": {}, + "grid_x": 71, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X27Y5", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y50": { + "bits": {}, + "grid_x": 71, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X27Y50", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y51": { + "bits": {}, + "grid_x": 71, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X27Y51", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y52": { + "bits": {}, + "grid_x": 71, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X27Y52", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y53": { + "bits": {}, + "grid_x": 71, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X27Y53", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y54": { + "bits": {}, + "grid_x": 71, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X27Y54", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y55": { + "bits": {}, + "grid_x": 71, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X27Y55", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y56": { + "bits": {}, + "grid_x": 71, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X27Y56", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y57": { + "bits": {}, + "grid_x": 71, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X27Y57", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y58": { + "bits": {}, + "grid_x": 71, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X27Y58", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y59": { + "bits": {}, + "grid_x": 71, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X27Y59", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y6": { + "bits": {}, + "grid_x": 71, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X27Y6", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y60": { + "bits": {}, + "grid_x": 71, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X27Y60", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y61": { + "bits": {}, + "grid_x": 71, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X27Y61", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y62": { + "bits": {}, + "grid_x": 71, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X27Y62", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y63": { + "bits": {}, + "grid_x": 71, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X27Y63", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y64": { + "bits": {}, + "grid_x": 71, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X27Y64", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y65": { + "bits": {}, + "grid_x": 71, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X27Y65", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y66": { + "bits": {}, + "grid_x": 71, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X27Y66", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y67": { + "bits": {}, + "grid_x": 71, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X27Y67", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y68": { + "bits": {}, + "grid_x": 71, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X27Y68", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y69": { + "bits": {}, + "grid_x": 71, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X27Y69", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y7": { + "bits": {}, + "grid_x": 71, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X27Y7", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y70": { + "bits": {}, + "grid_x": 71, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X27Y70", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y71": { + "bits": {}, + "grid_x": 71, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X27Y71", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y72": { + "bits": {}, + "grid_x": 71, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X27Y72", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y73": { + "bits": {}, + "grid_x": 71, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X27Y73", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y74": { + "bits": {}, + "grid_x": 71, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X27Y74", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y75": { + "bits": {}, + "grid_x": 71, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X27Y75", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y76": { + "bits": {}, + "grid_x": 71, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X27Y76", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y77": { + "bits": {}, + "grid_x": 71, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X27Y77", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y78": { + "bits": {}, + "grid_x": 71, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X27Y78", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y79": { + "bits": {}, + "grid_x": 71, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X27Y79", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y8": { + "bits": {}, + "grid_x": 71, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X27Y8", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y80": { + "bits": {}, + "grid_x": 71, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X27Y80", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y81": { + "bits": {}, + "grid_x": 71, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X27Y81", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y82": { + "bits": {}, + "grid_x": 71, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X27Y82", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y83": { + "bits": {}, + "grid_x": 71, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X27Y83", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y84": { + "bits": {}, + "grid_x": 71, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X27Y84", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y85": { + "bits": {}, + "grid_x": 71, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X27Y85", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y86": { + "bits": {}, + "grid_x": 71, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X27Y86", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y87": { + "bits": {}, + "grid_x": 71, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X27Y87", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y88": { + "bits": {}, + "grid_x": 71, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X27Y88", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y89": { + "bits": {}, + "grid_x": 71, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X27Y89", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y9": { + "bits": {}, + "grid_x": 71, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X27Y9", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y90": { + "bits": {}, + "grid_x": 71, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X27Y90", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y91": { + "bits": {}, + "grid_x": 71, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X27Y91", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y92": { + "bits": {}, + "grid_x": 71, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X27Y92", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y93": { + "bits": {}, + "grid_x": 71, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X27Y93", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y94": { + "bits": {}, + "grid_x": 71, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X27Y94", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y95": { + "bits": {}, + "grid_x": 71, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X27Y95", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y96": { + "bits": {}, + "grid_x": 71, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X27Y96", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y97": { + "bits": {}, + "grid_x": 71, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X27Y97", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y98": { + "bits": {}, + "grid_x": 71, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X27Y98", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X27Y99": { + "bits": {}, + "grid_x": 71, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X27Y99", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X29Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y0": { + "bits": {}, + "grid_x": 75, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X29Y0", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y1": { + "bits": {}, + "grid_x": 75, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X29Y1", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y10": { + "bits": {}, + "grid_x": 75, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X29Y10", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y11": { + "bits": {}, + "grid_x": 75, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X29Y11", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y12": { + "bits": {}, + "grid_x": 75, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X29Y12", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y125": { + "bits": {}, + "grid_x": 75, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X29Y125", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y126": { + "bits": {}, + "grid_x": 75, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X29Y126", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y127": { + "bits": {}, + "grid_x": 75, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X29Y127", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y128": { + "bits": {}, + "grid_x": 75, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X29Y128", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y129": { + "bits": {}, + "grid_x": 75, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X29Y129", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y13": { + "bits": {}, + "grid_x": 75, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X29Y13", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y130": { + "bits": {}, + "grid_x": 75, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X29Y130", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y131": { + "bits": {}, + "grid_x": 75, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X29Y131", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y132": { + "bits": {}, + "grid_x": 75, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X29Y132", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y133": { + "bits": {}, + "grid_x": 75, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X29Y133", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y134": { + "bits": {}, + "grid_x": 75, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X29Y134", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y135": { + "bits": {}, + "grid_x": 75, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X29Y135", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y136": { + "bits": {}, + "grid_x": 75, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X29Y136", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y137": { + "bits": {}, + "grid_x": 75, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X29Y137", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y138": { + "bits": {}, + "grid_x": 75, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X29Y138", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y139": { + "bits": {}, + "grid_x": 75, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X29Y139", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y14": { + "bits": {}, + "grid_x": 75, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X29Y14", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y140": { + "bits": {}, + "grid_x": 75, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X29Y140", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y141": { + "bits": {}, + "grid_x": 75, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X29Y141", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y142": { + "bits": {}, + "grid_x": 75, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X29Y142", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y143": { + "bits": {}, + "grid_x": 75, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X29Y143", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y144": { + "bits": {}, + "grid_x": 75, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X29Y144", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y145": { + "bits": {}, + "grid_x": 75, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X29Y145", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y146": { + "bits": {}, + "grid_x": 75, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X29Y146", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y147": { + "bits": {}, + "grid_x": 75, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X29Y147", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y148": { + "bits": {}, + "grid_x": 75, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X29Y148", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y149": { + "bits": {}, + "grid_x": 75, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X29Y149", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y15": { + "bits": {}, + "grid_x": 75, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X29Y15", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y150": { + "bits": {}, + "grid_x": 75, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X29Y150", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y151": { + "bits": {}, + "grid_x": 75, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X29Y151", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y152": { + "bits": {}, + "grid_x": 75, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X29Y152", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y153": { + "bits": {}, + "grid_x": 75, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X29Y153", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y154": { + "bits": {}, + "grid_x": 75, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X29Y154", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y155": { + "bits": {}, + "grid_x": 75, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X29Y155", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y156": { + "bits": {}, + "grid_x": 75, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X29Y156", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y157": { + "bits": {}, + "grid_x": 75, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X29Y157", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y158": { + "bits": {}, + "grid_x": 75, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X29Y158", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y159": { + "bits": {}, + "grid_x": 75, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X29Y159", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y16": { + "bits": {}, + "grid_x": 75, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X29Y16", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y160": { + "bits": {}, + "grid_x": 75, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X29Y160", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y161": { + "bits": {}, + "grid_x": 75, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X29Y161", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y162": { + "bits": {}, + "grid_x": 75, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X29Y162", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y163": { + "bits": {}, + "grid_x": 75, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X29Y163", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y164": { + "bits": {}, + "grid_x": 75, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X29Y164", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y165": { + "bits": {}, + "grid_x": 75, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X29Y165", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y166": { + "bits": {}, + "grid_x": 75, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X29Y166", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y167": { + "bits": {}, + "grid_x": 75, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X29Y167", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y168": { + "bits": {}, + "grid_x": 75, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X29Y168", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y169": { + "bits": {}, + "grid_x": 75, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X29Y169", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y17": { + "bits": {}, + "grid_x": 75, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X29Y17", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y170": { + "bits": {}, + "grid_x": 75, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X29Y170", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y171": { + "bits": {}, + "grid_x": 75, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X29Y171", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y172": { + "bits": {}, + "grid_x": 75, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X29Y172", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y173": { + "bits": {}, + "grid_x": 75, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X29Y173", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y174": { + "bits": {}, + "grid_x": 75, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X29Y174", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y175": { + "bits": {}, + "grid_x": 75, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X29Y175", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y176": { + "bits": {}, + "grid_x": 75, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X29Y176", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y177": { + "bits": {}, + "grid_x": 75, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X29Y177", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y178": { + "bits": {}, + "grid_x": 75, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X29Y178", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y179": { + "bits": {}, + "grid_x": 75, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X29Y179", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y18": { + "bits": {}, + "grid_x": 75, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X29Y18", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y180": { + "bits": {}, + "grid_x": 75, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X29Y180", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y181": { + "bits": {}, + "grid_x": 75, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X29Y181", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y182": { + "bits": {}, + "grid_x": 75, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X29Y182", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y183": { + "bits": {}, + "grid_x": 75, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X29Y183", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y184": { + "bits": {}, + "grid_x": 75, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X29Y184", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y185": { + "bits": {}, + "grid_x": 75, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X29Y185", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y186": { + "bits": {}, + "grid_x": 75, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X29Y186", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y187": { + "bits": {}, + "grid_x": 75, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X29Y187", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y188": { + "bits": {}, + "grid_x": 75, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X29Y188", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y189": { + "bits": {}, + "grid_x": 75, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X29Y189", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y19": { + "bits": {}, + "grid_x": 75, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X29Y19", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y190": { + "bits": {}, + "grid_x": 75, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X29Y190", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y191": { + "bits": {}, + "grid_x": 75, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X29Y191", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y192": { + "bits": {}, + "grid_x": 75, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X29Y192", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y193": { + "bits": {}, + "grid_x": 75, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X29Y193", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y194": { + "bits": {}, + "grid_x": 75, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X29Y194", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y195": { + "bits": {}, + "grid_x": 75, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X29Y195", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y196": { + "bits": {}, + "grid_x": 75, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X29Y196", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y197": { + "bits": {}, + "grid_x": 75, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X29Y197", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y198": { + "bits": {}, + "grid_x": 75, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X29Y198", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y199": { + "bits": {}, + "grid_x": 75, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X29Y199", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y2": { + "bits": {}, + "grid_x": 75, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X29Y2", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y20": { + "bits": {}, + "grid_x": 75, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X29Y20", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y21": { + "bits": {}, + "grid_x": 75, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X29Y21", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y22": { + "bits": {}, + "grid_x": 75, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X29Y22", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y23": { + "bits": {}, + "grid_x": 75, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X29Y23", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y24": { + "bits": {}, + "grid_x": 75, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X29Y24", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y25": { + "bits": {}, + "grid_x": 75, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X29Y25", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y26": { + "bits": {}, + "grid_x": 75, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X29Y26", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y27": { + "bits": {}, + "grid_x": 75, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X29Y27", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y28": { + "bits": {}, + "grid_x": 75, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X29Y28", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y29": { + "bits": {}, + "grid_x": 75, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X29Y29", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y3": { + "bits": {}, + "grid_x": 75, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X29Y3", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y30": { + "bits": {}, + "grid_x": 75, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X29Y30", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y31": { + "bits": {}, + "grid_x": 75, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X29Y31", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y32": { + "bits": {}, + "grid_x": 75, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X29Y32", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y33": { + "bits": {}, + "grid_x": 75, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X29Y33", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y34": { + "bits": {}, + "grid_x": 75, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X29Y34", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y35": { + "bits": {}, + "grid_x": 75, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X29Y35", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y36": { + "bits": {}, + "grid_x": 75, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X29Y36", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y37": { + "bits": {}, + "grid_x": 75, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X29Y37", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y38": { + "bits": {}, + "grid_x": 75, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X29Y38", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y39": { + "bits": {}, + "grid_x": 75, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X29Y39", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y4": { + "bits": {}, + "grid_x": 75, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X29Y4", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y40": { + "bits": {}, + "grid_x": 75, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X29Y40", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y41": { + "bits": {}, + "grid_x": 75, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X29Y41", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y42": { + "bits": {}, + "grid_x": 75, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X29Y42", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y43": { + "bits": {}, + "grid_x": 75, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X29Y43", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y44": { + "bits": {}, + "grid_x": 75, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X29Y44", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y45": { + "bits": {}, + "grid_x": 75, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X29Y45", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y46": { + "bits": {}, + "grid_x": 75, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X29Y46", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y47": { + "bits": {}, + "grid_x": 75, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X29Y47", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y48": { + "bits": {}, + "grid_x": 75, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X29Y48", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y49": { + "bits": {}, + "grid_x": 75, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X29Y49", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y5": { + "bits": {}, + "grid_x": 75, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X29Y5", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y50": { + "bits": {}, + "grid_x": 75, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X29Y50", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y51": { + "bits": {}, + "grid_x": 75, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X29Y51", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y52": { + "bits": {}, + "grid_x": 75, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X29Y52", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y53": { + "bits": {}, + "grid_x": 75, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X29Y53", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y54": { + "bits": {}, + "grid_x": 75, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X29Y54", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y55": { + "bits": {}, + "grid_x": 75, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X29Y55", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y56": { + "bits": {}, + "grid_x": 75, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X29Y56", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y57": { + "bits": {}, + "grid_x": 75, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X29Y57", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y58": { + "bits": {}, + "grid_x": 75, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X29Y58", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y59": { + "bits": {}, + "grid_x": 75, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X29Y59", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y6": { + "bits": {}, + "grid_x": 75, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X29Y6", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y60": { + "bits": {}, + "grid_x": 75, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X29Y60", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y61": { + "bits": {}, + "grid_x": 75, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X29Y61", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y62": { + "bits": {}, + "grid_x": 75, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X29Y62", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y63": { + "bits": {}, + "grid_x": 75, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X29Y63", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y64": { + "bits": {}, + "grid_x": 75, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X29Y64", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y65": { + "bits": {}, + "grid_x": 75, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X29Y65", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y66": { + "bits": {}, + "grid_x": 75, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X29Y66", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y67": { + "bits": {}, + "grid_x": 75, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X29Y67", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y68": { + "bits": {}, + "grid_x": 75, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X29Y68", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y69": { + "bits": {}, + "grid_x": 75, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X29Y69", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y7": { + "bits": {}, + "grid_x": 75, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X29Y7", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y70": { + "bits": {}, + "grid_x": 75, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X29Y70", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y71": { + "bits": {}, + "grid_x": 75, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X29Y71", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y72": { + "bits": {}, + "grid_x": 75, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X29Y72", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y73": { + "bits": {}, + "grid_x": 75, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X29Y73", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y74": { + "bits": {}, + "grid_x": 75, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X29Y74", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y75": { + "bits": {}, + "grid_x": 75, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X29Y75", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y76": { + "bits": {}, + "grid_x": 75, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X29Y76", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y77": { + "bits": {}, + "grid_x": 75, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X29Y77", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y78": { + "bits": {}, + "grid_x": 75, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X29Y78", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y79": { + "bits": {}, + "grid_x": 75, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X29Y79", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y8": { + "bits": {}, + "grid_x": 75, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X29Y8", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y80": { + "bits": {}, + "grid_x": 75, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X29Y80", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y81": { + "bits": {}, + "grid_x": 75, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X29Y81", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y82": { + "bits": {}, + "grid_x": 75, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X29Y82", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y83": { + "bits": {}, + "grid_x": 75, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X29Y83", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y84": { + "bits": {}, + "grid_x": 75, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X29Y84", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y85": { + "bits": {}, + "grid_x": 75, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X29Y85", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y86": { + "bits": {}, + "grid_x": 75, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X29Y86", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y87": { + "bits": {}, + "grid_x": 75, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X29Y87", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y88": { + "bits": {}, + "grid_x": 75, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X29Y88", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y89": { + "bits": {}, + "grid_x": 75, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X29Y89", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y9": { + "bits": {}, + "grid_x": 75, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X29Y9", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y90": { + "bits": {}, + "grid_x": 75, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X29Y90", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y91": { + "bits": {}, + "grid_x": 75, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X29Y91", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y92": { + "bits": {}, + "grid_x": 75, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X29Y92", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y93": { + "bits": {}, + "grid_x": 75, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X29Y93", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y94": { + "bits": {}, + "grid_x": 75, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X29Y94", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y95": { + "bits": {}, + "grid_x": 75, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X29Y95", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y96": { + "bits": {}, + "grid_x": 75, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X29Y96", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y97": { + "bits": {}, + "grid_x": 75, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X29Y97", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y98": { + "bits": {}, + "grid_x": 75, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X29Y98", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X29Y99": { + "bits": {}, + "grid_x": 75, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X29Y99", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X31Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y0": { + "bits": {}, + "grid_x": 80, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X31Y0", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y1": { + "bits": {}, + "grid_x": 80, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X31Y1", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y10": { + "bits": {}, + "grid_x": 80, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X31Y10", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y100": { + "bits": {}, + "grid_x": 80, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X31Y100", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y101": { + "bits": {}, + "grid_x": 80, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X31Y101", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y102": { + "bits": {}, + "grid_x": 80, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X31Y102", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y103": { + "bits": {}, + "grid_x": 80, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X31Y103", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y104": { + "bits": {}, + "grid_x": 80, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X31Y104", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y105": { + "bits": {}, + "grid_x": 80, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X31Y105", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y106": { + "bits": {}, + "grid_x": 80, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X31Y106", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y107": { + "bits": {}, + "grid_x": 80, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X31Y107", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y108": { + "bits": {}, + "grid_x": 80, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X31Y108", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y109": { + "bits": {}, + "grid_x": 80, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X31Y109", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y11": { + "bits": {}, + "grid_x": 80, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X31Y11", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y110": { + "bits": {}, + "grid_x": 80, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X31Y110", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y111": { + "bits": {}, + "grid_x": 80, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X31Y111", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y112": { + "bits": {}, + "grid_x": 80, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X31Y112", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y113": { + "bits": {}, + "grid_x": 80, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X31Y113", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y114": { + "bits": {}, + "grid_x": 80, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X31Y114", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y115": { + "bits": {}, + "grid_x": 80, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X31Y115", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y116": { + "bits": {}, + "grid_x": 80, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X31Y116", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y117": { + "bits": {}, + "grid_x": 80, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X31Y117", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y118": { + "bits": {}, + "grid_x": 80, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X31Y118", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y119": { + "bits": {}, + "grid_x": 80, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X31Y119", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y12": { + "bits": {}, + "grid_x": 80, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X31Y12", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y120": { + "bits": {}, + "grid_x": 80, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X31Y120", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y121": { + "bits": {}, + "grid_x": 80, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X31Y121", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y122": { + "bits": {}, + "grid_x": 80, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X31Y122", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y123": { + "bits": {}, + "grid_x": 80, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X31Y123", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y124": { + "bits": {}, + "grid_x": 80, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X31Y124", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y125": { + "bits": {}, + "grid_x": 80, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X31Y125", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y126": { + "bits": {}, + "grid_x": 80, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X31Y126", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y127": { + "bits": {}, + "grid_x": 80, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X31Y127", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y128": { + "bits": {}, + "grid_x": 80, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X31Y128", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y129": { + "bits": {}, + "grid_x": 80, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X31Y129", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y13": { + "bits": {}, + "grid_x": 80, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X31Y13", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y130": { + "bits": {}, + "grid_x": 80, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X31Y130", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y131": { + "bits": {}, + "grid_x": 80, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X31Y131", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y132": { + "bits": {}, + "grid_x": 80, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X31Y132", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y133": { + "bits": {}, + "grid_x": 80, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X31Y133", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y134": { + "bits": {}, + "grid_x": 80, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X31Y134", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y135": { + "bits": {}, + "grid_x": 80, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X31Y135", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y136": { + "bits": {}, + "grid_x": 80, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X31Y136", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y137": { + "bits": {}, + "grid_x": 80, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X31Y137", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y138": { + "bits": {}, + "grid_x": 80, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X31Y138", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y139": { + "bits": {}, + "grid_x": 80, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X31Y139", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y14": { + "bits": {}, + "grid_x": 80, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X31Y14", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y140": { + "bits": {}, + "grid_x": 80, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X31Y140", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y141": { + "bits": {}, + "grid_x": 80, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X31Y141", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y142": { + "bits": {}, + "grid_x": 80, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X31Y142", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y143": { + "bits": {}, + "grid_x": 80, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X31Y143", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y144": { + "bits": {}, + "grid_x": 80, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X31Y144", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y145": { + "bits": {}, + "grid_x": 80, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X31Y145", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y146": { + "bits": {}, + "grid_x": 80, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X31Y146", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y147": { + "bits": {}, + "grid_x": 80, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X31Y147", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y148": { + "bits": {}, + "grid_x": 80, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X31Y148", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y149": { + "bits": {}, + "grid_x": 80, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X31Y149", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y15": { + "bits": {}, + "grid_x": 80, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X31Y15", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y150": { + "bits": {}, + "grid_x": 80, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X31Y150", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y151": { + "bits": {}, + "grid_x": 80, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X31Y151", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y152": { + "bits": {}, + "grid_x": 80, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X31Y152", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y153": { + "bits": {}, + "grid_x": 80, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X31Y153", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y154": { + "bits": {}, + "grid_x": 80, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X31Y154", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y155": { + "bits": {}, + "grid_x": 80, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X31Y155", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y156": { + "bits": {}, + "grid_x": 80, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X31Y156", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y157": { + "bits": {}, + "grid_x": 80, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X31Y157", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y158": { + "bits": {}, + "grid_x": 80, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X31Y158", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y159": { + "bits": {}, + "grid_x": 80, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X31Y159", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y16": { + "bits": {}, + "grid_x": 80, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X31Y16", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y160": { + "bits": {}, + "grid_x": 80, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X31Y160", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y161": { + "bits": {}, + "grid_x": 80, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X31Y161", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y162": { + "bits": {}, + "grid_x": 80, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X31Y162", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y163": { + "bits": {}, + "grid_x": 80, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X31Y163", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y164": { + "bits": {}, + "grid_x": 80, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X31Y164", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y165": { + "bits": {}, + "grid_x": 80, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X31Y165", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y166": { + "bits": {}, + "grid_x": 80, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X31Y166", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y167": { + "bits": {}, + "grid_x": 80, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X31Y167", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y168": { + "bits": {}, + "grid_x": 80, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X31Y168", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y169": { + "bits": {}, + "grid_x": 80, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X31Y169", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y17": { + "bits": {}, + "grid_x": 80, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X31Y17", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y170": { + "bits": {}, + "grid_x": 80, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X31Y170", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y171": { + "bits": {}, + "grid_x": 80, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X31Y171", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y172": { + "bits": {}, + "grid_x": 80, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X31Y172", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y173": { + "bits": {}, + "grid_x": 80, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X31Y173", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y174": { + "bits": {}, + "grid_x": 80, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X31Y174", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y175": { + "bits": {}, + "grid_x": 80, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X31Y175", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y176": { + "bits": {}, + "grid_x": 80, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X31Y176", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y177": { + "bits": {}, + "grid_x": 80, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X31Y177", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y178": { + "bits": {}, + "grid_x": 80, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X31Y178", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y179": { + "bits": {}, + "grid_x": 80, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X31Y179", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y18": { + "bits": {}, + "grid_x": 80, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X31Y18", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y180": { + "bits": {}, + "grid_x": 80, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X31Y180", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y181": { + "bits": {}, + "grid_x": 80, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X31Y181", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y182": { + "bits": {}, + "grid_x": 80, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X31Y182", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y183": { + "bits": {}, + "grid_x": 80, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X31Y183", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y184": { + "bits": {}, + "grid_x": 80, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X31Y184", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y185": { + "bits": {}, + "grid_x": 80, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X31Y185", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y186": { + "bits": {}, + "grid_x": 80, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X31Y186", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y187": { + "bits": {}, + "grid_x": 80, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X31Y187", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y188": { + "bits": {}, + "grid_x": 80, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X31Y188", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y189": { + "bits": {}, + "grid_x": 80, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X31Y189", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y19": { + "bits": {}, + "grid_x": 80, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X31Y19", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y190": { + "bits": {}, + "grid_x": 80, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X31Y190", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y191": { + "bits": {}, + "grid_x": 80, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X31Y191", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y192": { + "bits": {}, + "grid_x": 80, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X31Y192", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y193": { + "bits": {}, + "grid_x": 80, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X31Y193", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y194": { + "bits": {}, + "grid_x": 80, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X31Y194", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y195": { + "bits": {}, + "grid_x": 80, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X31Y195", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y196": { + "bits": {}, + "grid_x": 80, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X31Y196", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y197": { + "bits": {}, + "grid_x": 80, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X31Y197", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y198": { + "bits": {}, + "grid_x": 80, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X31Y198", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y199": { + "bits": {}, + "grid_x": 80, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X31Y199", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y2": { + "bits": {}, + "grid_x": 80, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X31Y2", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y20": { + "bits": {}, + "grid_x": 80, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X31Y20", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y21": { + "bits": {}, + "grid_x": 80, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X31Y21", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y22": { + "bits": {}, + "grid_x": 80, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X31Y22", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y23": { + "bits": {}, + "grid_x": 80, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X31Y23", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y24": { + "bits": {}, + "grid_x": 80, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X31Y24", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y25": { + "bits": {}, + "grid_x": 80, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X31Y25", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y26": { + "bits": {}, + "grid_x": 80, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X31Y26", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y27": { + "bits": {}, + "grid_x": 80, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X31Y27", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y28": { + "bits": {}, + "grid_x": 80, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X31Y28", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y29": { + "bits": {}, + "grid_x": 80, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X31Y29", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y3": { + "bits": {}, + "grid_x": 80, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X31Y3", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y30": { + "bits": {}, + "grid_x": 80, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X31Y30", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y31": { + "bits": {}, + "grid_x": 80, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X31Y31", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y32": { + "bits": {}, + "grid_x": 80, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X31Y32", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y33": { + "bits": {}, + "grid_x": 80, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X31Y33", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y34": { + "bits": {}, + "grid_x": 80, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X31Y34", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y35": { + "bits": {}, + "grid_x": 80, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X31Y35", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y36": { + "bits": {}, + "grid_x": 80, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X31Y36", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y37": { + "bits": {}, + "grid_x": 80, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X31Y37", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y38": { + "bits": {}, + "grid_x": 80, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X31Y38", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y39": { + "bits": {}, + "grid_x": 80, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X31Y39", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y4": { + "bits": {}, + "grid_x": 80, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X31Y4", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y40": { + "bits": {}, + "grid_x": 80, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X31Y40", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y41": { + "bits": {}, + "grid_x": 80, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X31Y41", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y42": { + "bits": {}, + "grid_x": 80, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X31Y42", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y43": { + "bits": {}, + "grid_x": 80, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X31Y43", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y44": { + "bits": {}, + "grid_x": 80, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X31Y44", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y45": { + "bits": {}, + "grid_x": 80, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X31Y45", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y46": { + "bits": {}, + "grid_x": 80, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X31Y46", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y47": { + "bits": {}, + "grid_x": 80, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X31Y47", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y48": { + "bits": {}, + "grid_x": 80, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X31Y48", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y49": { + "bits": {}, + "grid_x": 80, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X31Y49", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y5": { + "bits": {}, + "grid_x": 80, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X31Y5", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y50": { + "bits": {}, + "grid_x": 80, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X31Y50", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y51": { + "bits": {}, + "grid_x": 80, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X31Y51", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y52": { + "bits": {}, + "grid_x": 80, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X31Y52", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y53": { + "bits": {}, + "grid_x": 80, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X31Y53", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y54": { + "bits": {}, + "grid_x": 80, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X31Y54", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y55": { + "bits": {}, + "grid_x": 80, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X31Y55", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y56": { + "bits": {}, + "grid_x": 80, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X31Y56", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y57": { + "bits": {}, + "grid_x": 80, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X31Y57", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y58": { + "bits": {}, + "grid_x": 80, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X31Y58", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y59": { + "bits": {}, + "grid_x": 80, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X31Y59", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y6": { + "bits": {}, + "grid_x": 80, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X31Y6", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y60": { + "bits": {}, + "grid_x": 80, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X31Y60", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y61": { + "bits": {}, + "grid_x": 80, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X31Y61", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y62": { + "bits": {}, + "grid_x": 80, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X31Y62", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y63": { + "bits": {}, + "grid_x": 80, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X31Y63", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y64": { + "bits": {}, + "grid_x": 80, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X31Y64", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y65": { + "bits": {}, + "grid_x": 80, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X31Y65", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y66": { + "bits": {}, + "grid_x": 80, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X31Y66", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y67": { + "bits": {}, + "grid_x": 80, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X31Y67", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y68": { + "bits": {}, + "grid_x": 80, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X31Y68", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y69": { + "bits": {}, + "grid_x": 80, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X31Y69", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y7": { + "bits": {}, + "grid_x": 80, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X31Y7", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y70": { + "bits": {}, + "grid_x": 80, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X31Y70", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y71": { + "bits": {}, + "grid_x": 80, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X31Y71", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y72": { + "bits": {}, + "grid_x": 80, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X31Y72", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y73": { + "bits": {}, + "grid_x": 80, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X31Y73", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y74": { + "bits": {}, + "grid_x": 80, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X31Y74", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y75": { + "bits": {}, + "grid_x": 80, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X31Y75", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y76": { + "bits": {}, + "grid_x": 80, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X31Y76", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y77": { + "bits": {}, + "grid_x": 80, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X31Y77", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y78": { + "bits": {}, + "grid_x": 80, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X31Y78", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y79": { + "bits": {}, + "grid_x": 80, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X31Y79", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y8": { + "bits": {}, + "grid_x": 80, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X31Y8", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y80": { + "bits": {}, + "grid_x": 80, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X31Y80", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y81": { + "bits": {}, + "grid_x": 80, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X31Y81", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y82": { + "bits": {}, + "grid_x": 80, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X31Y82", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y83": { + "bits": {}, + "grid_x": 80, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X31Y83", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y84": { + "bits": {}, + "grid_x": 80, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X31Y84", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y85": { + "bits": {}, + "grid_x": 80, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X31Y85", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y86": { + "bits": {}, + "grid_x": 80, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X31Y86", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y87": { + "bits": {}, + "grid_x": 80, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X31Y87", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y88": { + "bits": {}, + "grid_x": 80, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X31Y88", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y89": { + "bits": {}, + "grid_x": 80, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X31Y89", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y9": { + "bits": {}, + "grid_x": 80, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X31Y9", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y90": { + "bits": {}, + "grid_x": 80, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X31Y90", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y91": { + "bits": {}, + "grid_x": 80, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X31Y91", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y92": { + "bits": {}, + "grid_x": 80, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X31Y92", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y93": { + "bits": {}, + "grid_x": 80, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X31Y93", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y94": { + "bits": {}, + "grid_x": 80, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X31Y94", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y95": { + "bits": {}, + "grid_x": 80, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X31Y95", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y96": { + "bits": {}, + "grid_x": 80, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X31Y96", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y97": { + "bits": {}, + "grid_x": 80, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X31Y97", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y98": { + "bits": {}, + "grid_x": 80, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X31Y98", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X31Y99": { + "bits": {}, + "grid_x": 80, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X31Y99", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X33Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y0": { + "bits": {}, + "grid_x": 85, + "grid_y": 207, + "segment": "SEG_DSP0_R_X33Y0", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y1": { + "bits": {}, + "grid_x": 85, + "grid_y": 206, + "segment": "SEG_DSP1_R_X33Y0", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y10": { + "bits": {}, + "grid_x": 85, + "grid_y": 197, + "segment": "SEG_DSP0_R_X33Y10", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y100": { + "bits": {}, + "grid_x": 85, + "grid_y": 103, + "segment": "SEG_DSP0_R_X33Y100", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y101": { + "bits": {}, + "grid_x": 85, + "grid_y": 102, + "segment": "SEG_DSP1_R_X33Y100", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y102": { + "bits": {}, + "grid_x": 85, + "grid_y": 101, + "segment": "SEG_DSP2_R_X33Y100", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y103": { + "bits": {}, + "grid_x": 85, + "grid_y": 100, + "segment": "SEG_DSP3_R_X33Y100", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y104": { + "bits": {}, + "grid_x": 85, + "grid_y": 99, + "segment": "SEG_DSP4_R_X33Y100", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y105": { + "bits": {}, + "grid_x": 85, + "grid_y": 98, + "segment": "SEG_DSP0_R_X33Y105", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y106": { + "bits": {}, + "grid_x": 85, + "grid_y": 97, + "segment": "SEG_DSP1_R_X33Y105", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y107": { + "bits": {}, + "grid_x": 85, + "grid_y": 96, + "segment": "SEG_DSP2_R_X33Y105", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y108": { + "bits": {}, + "grid_x": 85, + "grid_y": 95, + "segment": "SEG_DSP3_R_X33Y105", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y109": { + "bits": {}, + "grid_x": 85, + "grid_y": 94, + "segment": "SEG_DSP4_R_X33Y105", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y11": { + "bits": {}, + "grid_x": 85, + "grid_y": 196, + "segment": "SEG_DSP1_R_X33Y10", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y110": { + "bits": {}, + "grid_x": 85, + "grid_y": 93, + "segment": "SEG_DSP0_R_X33Y110", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y111": { + "bits": {}, + "grid_x": 85, + "grid_y": 92, + "segment": "SEG_DSP1_R_X33Y110", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y112": { + "bits": {}, + "grid_x": 85, + "grid_y": 91, + "segment": "SEG_DSP2_R_X33Y110", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y113": { + "bits": {}, + "grid_x": 85, + "grid_y": 90, + "segment": "SEG_DSP3_R_X33Y110", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y114": { + "bits": {}, + "grid_x": 85, + "grid_y": 89, + "segment": "SEG_DSP4_R_X33Y110", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y115": { + "bits": {}, + "grid_x": 85, + "grid_y": 88, + "segment": "SEG_DSP0_R_X33Y115", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y116": { + "bits": {}, + "grid_x": 85, + "grid_y": 87, + "segment": "SEG_DSP1_R_X33Y115", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y117": { + "bits": {}, + "grid_x": 85, + "grid_y": 86, + "segment": "SEG_DSP2_R_X33Y115", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y118": { + "bits": {}, + "grid_x": 85, + "grid_y": 85, + "segment": "SEG_DSP3_R_X33Y115", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y119": { + "bits": {}, + "grid_x": 85, + "grid_y": 84, + "segment": "SEG_DSP4_R_X33Y115", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y12": { + "bits": {}, + "grid_x": 85, + "grid_y": 195, + "segment": "SEG_DSP2_R_X33Y10", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y120": { + "bits": {}, + "grid_x": 85, + "grid_y": 83, + "segment": "SEG_DSP0_R_X33Y120", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y121": { + "bits": {}, + "grid_x": 85, + "grid_y": 82, + "segment": "SEG_DSP1_R_X33Y120", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y122": { + "bits": {}, + "grid_x": 85, + "grid_y": 81, + "segment": "SEG_DSP2_R_X33Y120", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y123": { + "bits": {}, + "grid_x": 85, + "grid_y": 80, + "segment": "SEG_DSP3_R_X33Y120", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y124": { + "bits": {}, + "grid_x": 85, + "grid_y": 79, + "segment": "SEG_DSP4_R_X33Y120", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y125": { + "bits": {}, + "grid_x": 85, + "grid_y": 77, + "segment": "SEG_DSP0_R_X33Y125", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y126": { + "bits": {}, + "grid_x": 85, + "grid_y": 76, + "segment": "SEG_DSP1_R_X33Y125", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y127": { + "bits": {}, + "grid_x": 85, + "grid_y": 75, + "segment": "SEG_DSP2_R_X33Y125", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y128": { + "bits": {}, + "grid_x": 85, + "grid_y": 74, + "segment": "SEG_DSP3_R_X33Y125", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y129": { + "bits": {}, + "grid_x": 85, + "grid_y": 73, + "segment": "SEG_DSP4_R_X33Y125", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y13": { + "bits": {}, + "grid_x": 85, + "grid_y": 194, + "segment": "SEG_DSP3_R_X33Y10", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y130": { + "bits": {}, + "grid_x": 85, + "grid_y": 72, + "segment": "SEG_DSP0_R_X33Y130", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y131": { + "bits": {}, + "grid_x": 85, + "grid_y": 71, + "segment": "SEG_DSP1_R_X33Y130", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y132": { + "bits": {}, + "grid_x": 85, + "grid_y": 70, + "segment": "SEG_DSP2_R_X33Y130", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y133": { + "bits": {}, + "grid_x": 85, + "grid_y": 69, + "segment": "SEG_DSP3_R_X33Y130", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y134": { + "bits": {}, + "grid_x": 85, + "grid_y": 68, + "segment": "SEG_DSP4_R_X33Y130", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y135": { + "bits": {}, + "grid_x": 85, + "grid_y": 67, + "segment": "SEG_DSP0_R_X33Y135", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y136": { + "bits": {}, + "grid_x": 85, + "grid_y": 66, + "segment": "SEG_DSP1_R_X33Y135", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y137": { + "bits": {}, + "grid_x": 85, + "grid_y": 65, + "segment": "SEG_DSP2_R_X33Y135", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y138": { + "bits": {}, + "grid_x": 85, + "grid_y": 64, + "segment": "SEG_DSP3_R_X33Y135", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y139": { + "bits": {}, + "grid_x": 85, + "grid_y": 63, + "segment": "SEG_DSP4_R_X33Y135", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y14": { + "bits": {}, + "grid_x": 85, + "grid_y": 193, + "segment": "SEG_DSP4_R_X33Y10", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y140": { + "bits": {}, + "grid_x": 85, + "grid_y": 62, + "segment": "SEG_DSP0_R_X33Y140", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y141": { + "bits": {}, + "grid_x": 85, + "grid_y": 61, + "segment": "SEG_DSP1_R_X33Y140", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y142": { + "bits": {}, + "grid_x": 85, + "grid_y": 60, + "segment": "SEG_DSP2_R_X33Y140", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y143": { + "bits": {}, + "grid_x": 85, + "grid_y": 59, + "segment": "SEG_DSP3_R_X33Y140", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y144": { + "bits": {}, + "grid_x": 85, + "grid_y": 58, + "segment": "SEG_DSP4_R_X33Y140", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y145": { + "bits": {}, + "grid_x": 85, + "grid_y": 57, + "segment": "SEG_DSP0_R_X33Y145", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y146": { + "bits": {}, + "grid_x": 85, + "grid_y": 56, + "segment": "SEG_DSP1_R_X33Y145", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y147": { + "bits": {}, + "grid_x": 85, + "grid_y": 55, + "segment": "SEG_DSP2_R_X33Y145", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y148": { + "bits": {}, + "grid_x": 85, + "grid_y": 54, + "segment": "SEG_DSP3_R_X33Y145", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y149": { + "bits": {}, + "grid_x": 85, + "grid_y": 53, + "segment": "SEG_DSP4_R_X33Y145", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y15": { + "bits": {}, + "grid_x": 85, + "grid_y": 192, + "segment": "SEG_DSP0_R_X33Y15", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y150": { + "bits": {}, + "grid_x": 85, + "grid_y": 51, + "segment": "SEG_DSP0_R_X33Y150", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y151": { + "bits": {}, + "grid_x": 85, + "grid_y": 50, + "segment": "SEG_DSP1_R_X33Y150", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y152": { + "bits": {}, + "grid_x": 85, + "grid_y": 49, + "segment": "SEG_DSP2_R_X33Y150", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y153": { + "bits": {}, + "grid_x": 85, + "grid_y": 48, + "segment": "SEG_DSP3_R_X33Y150", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y154": { + "bits": {}, + "grid_x": 85, + "grid_y": 47, + "segment": "SEG_DSP4_R_X33Y150", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y155": { + "bits": {}, + "grid_x": 85, + "grid_y": 46, + "segment": "SEG_DSP0_R_X33Y155", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y156": { + "bits": {}, + "grid_x": 85, + "grid_y": 45, + "segment": "SEG_DSP1_R_X33Y155", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y157": { + "bits": {}, + "grid_x": 85, + "grid_y": 44, + "segment": "SEG_DSP2_R_X33Y155", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y158": { + "bits": {}, + "grid_x": 85, + "grid_y": 43, + "segment": "SEG_DSP3_R_X33Y155", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y159": { + "bits": {}, + "grid_x": 85, + "grid_y": 42, + "segment": "SEG_DSP4_R_X33Y155", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y16": { + "bits": {}, + "grid_x": 85, + "grid_y": 191, + "segment": "SEG_DSP1_R_X33Y15", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y160": { + "bits": {}, + "grid_x": 85, + "grid_y": 41, + "segment": "SEG_DSP0_R_X33Y160", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y161": { + "bits": {}, + "grid_x": 85, + "grid_y": 40, + "segment": "SEG_DSP1_R_X33Y160", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y162": { + "bits": {}, + "grid_x": 85, + "grid_y": 39, + "segment": "SEG_DSP2_R_X33Y160", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y163": { + "bits": {}, + "grid_x": 85, + "grid_y": 38, + "segment": "SEG_DSP3_R_X33Y160", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y164": { + "bits": {}, + "grid_x": 85, + "grid_y": 37, + "segment": "SEG_DSP4_R_X33Y160", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y165": { + "bits": {}, + "grid_x": 85, + "grid_y": 36, + "segment": "SEG_DSP0_R_X33Y165", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y166": { + "bits": {}, + "grid_x": 85, + "grid_y": 35, + "segment": "SEG_DSP1_R_X33Y165", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y167": { + "bits": {}, + "grid_x": 85, + "grid_y": 34, + "segment": "SEG_DSP2_R_X33Y165", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y168": { + "bits": {}, + "grid_x": 85, + "grid_y": 33, + "segment": "SEG_DSP3_R_X33Y165", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y169": { + "bits": {}, + "grid_x": 85, + "grid_y": 32, + "segment": "SEG_DSP4_R_X33Y165", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y17": { + "bits": {}, + "grid_x": 85, + "grid_y": 190, + "segment": "SEG_DSP2_R_X33Y15", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y170": { + "bits": {}, + "grid_x": 85, + "grid_y": 31, + "segment": "SEG_DSP0_R_X33Y170", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y171": { + "bits": {}, + "grid_x": 85, + "grid_y": 30, + "segment": "SEG_DSP1_R_X33Y170", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y172": { + "bits": {}, + "grid_x": 85, + "grid_y": 29, + "segment": "SEG_DSP2_R_X33Y170", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y173": { + "bits": {}, + "grid_x": 85, + "grid_y": 28, + "segment": "SEG_DSP3_R_X33Y170", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y174": { + "bits": {}, + "grid_x": 85, + "grid_y": 27, + "segment": "SEG_DSP4_R_X33Y170", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y175": { + "bits": {}, + "grid_x": 85, + "grid_y": 25, + "segment": "SEG_DSP0_R_X33Y175", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y176": { + "bits": {}, + "grid_x": 85, + "grid_y": 24, + "segment": "SEG_DSP1_R_X33Y175", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y177": { + "bits": {}, + "grid_x": 85, + "grid_y": 23, + "segment": "SEG_DSP2_R_X33Y175", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y178": { + "bits": {}, + "grid_x": 85, + "grid_y": 22, + "segment": "SEG_DSP3_R_X33Y175", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y179": { + "bits": {}, + "grid_x": 85, + "grid_y": 21, + "segment": "SEG_DSP4_R_X33Y175", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y18": { + "bits": {}, + "grid_x": 85, + "grid_y": 189, + "segment": "SEG_DSP3_R_X33Y15", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y180": { + "bits": {}, + "grid_x": 85, + "grid_y": 20, + "segment": "SEG_DSP0_R_X33Y180", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y181": { + "bits": {}, + "grid_x": 85, + "grid_y": 19, + "segment": "SEG_DSP1_R_X33Y180", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y182": { + "bits": {}, + "grid_x": 85, + "grid_y": 18, + "segment": "SEG_DSP2_R_X33Y180", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y183": { + "bits": {}, + "grid_x": 85, + "grid_y": 17, + "segment": "SEG_DSP3_R_X33Y180", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y184": { + "bits": {}, + "grid_x": 85, + "grid_y": 16, + "segment": "SEG_DSP4_R_X33Y180", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y185": { + "bits": {}, + "grid_x": 85, + "grid_y": 15, + "segment": "SEG_DSP0_R_X33Y185", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y186": { + "bits": {}, + "grid_x": 85, + "grid_y": 14, + "segment": "SEG_DSP1_R_X33Y185", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y187": { + "bits": {}, + "grid_x": 85, + "grid_y": 13, + "segment": "SEG_DSP2_R_X33Y185", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y188": { + "bits": {}, + "grid_x": 85, + "grid_y": 12, + "segment": "SEG_DSP3_R_X33Y185", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y189": { + "bits": {}, + "grid_x": 85, + "grid_y": 11, + "segment": "SEG_DSP4_R_X33Y185", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y19": { + "bits": {}, + "grid_x": 85, + "grid_y": 188, + "segment": "SEG_DSP4_R_X33Y15", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y190": { + "bits": {}, + "grid_x": 85, + "grid_y": 10, + "segment": "SEG_DSP0_R_X33Y190", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y191": { + "bits": {}, + "grid_x": 85, + "grid_y": 9, + "segment": "SEG_DSP1_R_X33Y190", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y192": { + "bits": {}, + "grid_x": 85, + "grid_y": 8, + "segment": "SEG_DSP2_R_X33Y190", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y193": { + "bits": {}, + "grid_x": 85, + "grid_y": 7, + "segment": "SEG_DSP3_R_X33Y190", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y194": { + "bits": {}, + "grid_x": 85, + "grid_y": 6, + "segment": "SEG_DSP4_R_X33Y190", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y195": { + "bits": {}, + "grid_x": 85, + "grid_y": 5, + "segment": "SEG_DSP0_R_X33Y195", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y196": { + "bits": {}, + "grid_x": 85, + "grid_y": 4, + "segment": "SEG_DSP1_R_X33Y195", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y197": { + "bits": {}, + "grid_x": 85, + "grid_y": 3, + "segment": "SEG_DSP2_R_X33Y195", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y198": { + "bits": {}, + "grid_x": 85, + "grid_y": 2, + "segment": "SEG_DSP3_R_X33Y195", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y199": { + "bits": {}, + "grid_x": 85, + "grid_y": 1, + "segment": "SEG_DSP4_R_X33Y195", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y2": { + "bits": {}, + "grid_x": 85, + "grid_y": 205, + "segment": "SEG_DSP2_R_X33Y0", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y20": { + "bits": {}, + "grid_x": 85, + "grid_y": 187, + "segment": "SEG_DSP0_R_X33Y20", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y21": { + "bits": {}, + "grid_x": 85, + "grid_y": 186, + "segment": "SEG_DSP1_R_X33Y20", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y22": { + "bits": {}, + "grid_x": 85, + "grid_y": 185, + "segment": "SEG_DSP2_R_X33Y20", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y23": { + "bits": {}, + "grid_x": 85, + "grid_y": 184, + "segment": "SEG_DSP3_R_X33Y20", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y24": { + "bits": {}, + "grid_x": 85, + "grid_y": 183, + "segment": "SEG_DSP4_R_X33Y20", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y25": { + "bits": {}, + "grid_x": 85, + "grid_y": 181, + "segment": "SEG_DSP0_R_X33Y25", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y26": { + "bits": {}, + "grid_x": 85, + "grid_y": 180, + "segment": "SEG_DSP1_R_X33Y25", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y27": { + "bits": {}, + "grid_x": 85, + "grid_y": 179, + "segment": "SEG_DSP2_R_X33Y25", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y28": { + "bits": {}, + "grid_x": 85, + "grid_y": 178, + "segment": "SEG_DSP3_R_X33Y25", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y29": { + "bits": {}, + "grid_x": 85, + "grid_y": 177, + "segment": "SEG_DSP4_R_X33Y25", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y3": { + "bits": {}, + "grid_x": 85, + "grid_y": 204, + "segment": "SEG_DSP3_R_X33Y0", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y30": { + "bits": {}, + "grid_x": 85, + "grid_y": 176, + "segment": "SEG_DSP0_R_X33Y30", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y31": { + "bits": {}, + "grid_x": 85, + "grid_y": 175, + "segment": "SEG_DSP1_R_X33Y30", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y32": { + "bits": {}, + "grid_x": 85, + "grid_y": 174, + "segment": "SEG_DSP2_R_X33Y30", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y33": { + "bits": {}, + "grid_x": 85, + "grid_y": 173, + "segment": "SEG_DSP3_R_X33Y30", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y34": { + "bits": {}, + "grid_x": 85, + "grid_y": 172, + "segment": "SEG_DSP4_R_X33Y30", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y35": { + "bits": {}, + "grid_x": 85, + "grid_y": 171, + "segment": "SEG_DSP0_R_X33Y35", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y36": { + "bits": {}, + "grid_x": 85, + "grid_y": 170, + "segment": "SEG_DSP1_R_X33Y35", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y37": { + "bits": {}, + "grid_x": 85, + "grid_y": 169, + "segment": "SEG_DSP2_R_X33Y35", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y38": { + "bits": {}, + "grid_x": 85, + "grid_y": 168, + "segment": "SEG_DSP3_R_X33Y35", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y39": { + "bits": {}, + "grid_x": 85, + "grid_y": 167, + "segment": "SEG_DSP4_R_X33Y35", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y4": { + "bits": {}, + "grid_x": 85, + "grid_y": 203, + "segment": "SEG_DSP4_R_X33Y0", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y40": { + "bits": {}, + "grid_x": 85, + "grid_y": 166, + "segment": "SEG_DSP0_R_X33Y40", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y41": { + "bits": {}, + "grid_x": 85, + "grid_y": 165, + "segment": "SEG_DSP1_R_X33Y40", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y42": { + "bits": {}, + "grid_x": 85, + "grid_y": 164, + "segment": "SEG_DSP2_R_X33Y40", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y43": { + "bits": {}, + "grid_x": 85, + "grid_y": 163, + "segment": "SEG_DSP3_R_X33Y40", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y44": { + "bits": {}, + "grid_x": 85, + "grid_y": 162, + "segment": "SEG_DSP4_R_X33Y40", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y45": { + "bits": {}, + "grid_x": 85, + "grid_y": 161, + "segment": "SEG_DSP0_R_X33Y45", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y46": { + "bits": {}, + "grid_x": 85, + "grid_y": 160, + "segment": "SEG_DSP1_R_X33Y45", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y47": { + "bits": {}, + "grid_x": 85, + "grid_y": 159, + "segment": "SEG_DSP2_R_X33Y45", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y48": { + "bits": {}, + "grid_x": 85, + "grid_y": 158, + "segment": "SEG_DSP3_R_X33Y45", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y49": { + "bits": {}, + "grid_x": 85, + "grid_y": 157, + "segment": "SEG_DSP4_R_X33Y45", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y5": { + "bits": {}, + "grid_x": 85, + "grid_y": 202, + "segment": "SEG_DSP0_R_X33Y5", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y50": { + "bits": {}, + "grid_x": 85, + "grid_y": 155, + "segment": "SEG_DSP0_R_X33Y50", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y51": { + "bits": {}, + "grid_x": 85, + "grid_y": 154, + "segment": "SEG_DSP1_R_X33Y50", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y52": { + "bits": {}, + "grid_x": 85, + "grid_y": 153, + "segment": "SEG_DSP2_R_X33Y50", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y53": { + "bits": {}, + "grid_x": 85, + "grid_y": 152, + "segment": "SEG_DSP3_R_X33Y50", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y54": { + "bits": {}, + "grid_x": 85, + "grid_y": 151, + "segment": "SEG_DSP4_R_X33Y50", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y55": { + "bits": {}, + "grid_x": 85, + "grid_y": 150, + "segment": "SEG_DSP0_R_X33Y55", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y56": { + "bits": {}, + "grid_x": 85, + "grid_y": 149, + "segment": "SEG_DSP1_R_X33Y55", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y57": { + "bits": {}, + "grid_x": 85, + "grid_y": 148, + "segment": "SEG_DSP2_R_X33Y55", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y58": { + "bits": {}, + "grid_x": 85, + "grid_y": 147, + "segment": "SEG_DSP3_R_X33Y55", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y59": { + "bits": {}, + "grid_x": 85, + "grid_y": 146, + "segment": "SEG_DSP4_R_X33Y55", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y6": { + "bits": {}, + "grid_x": 85, + "grid_y": 201, + "segment": "SEG_DSP1_R_X33Y5", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y60": { + "bits": {}, + "grid_x": 85, + "grid_y": 145, + "segment": "SEG_DSP0_R_X33Y60", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y61": { + "bits": {}, + "grid_x": 85, + "grid_y": 144, + "segment": "SEG_DSP1_R_X33Y60", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y62": { + "bits": {}, + "grid_x": 85, + "grid_y": 143, + "segment": "SEG_DSP2_R_X33Y60", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y63": { + "bits": {}, + "grid_x": 85, + "grid_y": 142, + "segment": "SEG_DSP3_R_X33Y60", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y64": { + "bits": {}, + "grid_x": 85, + "grid_y": 141, + "segment": "SEG_DSP4_R_X33Y60", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y65": { + "bits": {}, + "grid_x": 85, + "grid_y": 140, + "segment": "SEG_DSP0_R_X33Y65", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y66": { + "bits": {}, + "grid_x": 85, + "grid_y": 139, + "segment": "SEG_DSP1_R_X33Y65", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y67": { + "bits": {}, + "grid_x": 85, + "grid_y": 138, + "segment": "SEG_DSP2_R_X33Y65", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y68": { + "bits": {}, + "grid_x": 85, + "grid_y": 137, + "segment": "SEG_DSP3_R_X33Y65", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y69": { + "bits": {}, + "grid_x": 85, + "grid_y": 136, + "segment": "SEG_DSP4_R_X33Y65", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y7": { + "bits": {}, + "grid_x": 85, + "grid_y": 200, + "segment": "SEG_DSP2_R_X33Y5", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y70": { + "bits": {}, + "grid_x": 85, + "grid_y": 135, + "segment": "SEG_DSP0_R_X33Y70", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y71": { + "bits": {}, + "grid_x": 85, + "grid_y": 134, + "segment": "SEG_DSP1_R_X33Y70", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y72": { + "bits": {}, + "grid_x": 85, + "grid_y": 133, + "segment": "SEG_DSP2_R_X33Y70", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y73": { + "bits": {}, + "grid_x": 85, + "grid_y": 132, + "segment": "SEG_DSP3_R_X33Y70", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y74": { + "bits": {}, + "grid_x": 85, + "grid_y": 131, + "segment": "SEG_DSP4_R_X33Y70", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y75": { + "bits": {}, + "grid_x": 85, + "grid_y": 129, + "segment": "SEG_DSP0_R_X33Y75", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y76": { + "bits": {}, + "grid_x": 85, + "grid_y": 128, + "segment": "SEG_DSP1_R_X33Y75", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y77": { + "bits": {}, + "grid_x": 85, + "grid_y": 127, + "segment": "SEG_DSP2_R_X33Y75", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y78": { + "bits": {}, + "grid_x": 85, + "grid_y": 126, + "segment": "SEG_DSP3_R_X33Y75", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y79": { + "bits": {}, + "grid_x": 85, + "grid_y": 125, + "segment": "SEG_DSP4_R_X33Y75", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y8": { + "bits": {}, + "grid_x": 85, + "grid_y": 199, + "segment": "SEG_DSP3_R_X33Y5", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y80": { + "bits": {}, + "grid_x": 85, + "grid_y": 124, + "segment": "SEG_DSP0_R_X33Y80", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y81": { + "bits": {}, + "grid_x": 85, + "grid_y": 123, + "segment": "SEG_DSP1_R_X33Y80", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y82": { + "bits": {}, + "grid_x": 85, + "grid_y": 122, + "segment": "SEG_DSP2_R_X33Y80", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y83": { + "bits": {}, + "grid_x": 85, + "grid_y": 121, + "segment": "SEG_DSP3_R_X33Y80", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y84": { + "bits": {}, + "grid_x": 85, + "grid_y": 120, + "segment": "SEG_DSP4_R_X33Y80", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y85": { + "bits": {}, + "grid_x": 85, + "grid_y": 119, + "segment": "SEG_DSP0_R_X33Y85", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y86": { + "bits": {}, + "grid_x": 85, + "grid_y": 118, + "segment": "SEG_DSP1_R_X33Y85", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y87": { + "bits": {}, + "grid_x": 85, + "grid_y": 117, + "segment": "SEG_DSP2_R_X33Y85", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y88": { + "bits": {}, + "grid_x": 85, + "grid_y": 116, + "segment": "SEG_DSP3_R_X33Y85", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y89": { + "bits": {}, + "grid_x": 85, + "grid_y": 115, + "segment": "SEG_DSP4_R_X33Y85", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y9": { + "bits": {}, + "grid_x": 85, + "grid_y": 198, + "segment": "SEG_DSP4_R_X33Y5", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y90": { + "bits": {}, + "grid_x": 85, + "grid_y": 114, + "segment": "SEG_DSP0_R_X33Y90", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y91": { + "bits": {}, + "grid_x": 85, + "grid_y": 113, + "segment": "SEG_DSP1_R_X33Y90", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y92": { + "bits": {}, + "grid_x": 85, + "grid_y": 112, + "segment": "SEG_DSP2_R_X33Y90", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y93": { + "bits": {}, + "grid_x": 85, + "grid_y": 111, + "segment": "SEG_DSP3_R_X33Y90", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y94": { + "bits": {}, + "grid_x": 85, + "grid_y": 110, + "segment": "SEG_DSP4_R_X33Y90", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y95": { + "bits": {}, + "grid_x": 85, + "grid_y": 109, + "segment": "SEG_DSP0_R_X33Y95", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X35Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y96": { + "bits": {}, + "grid_x": 85, + "grid_y": 108, + "segment": "SEG_DSP1_R_X33Y95", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X35Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y97": { + "bits": {}, + "grid_x": 85, + "grid_y": 107, + "segment": "SEG_DSP2_R_X33Y95", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X35Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y98": { + "bits": {}, + "grid_x": 85, + "grid_y": 106, + "segment": "SEG_DSP3_R_X33Y95", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X35Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X33Y99": { + "bits": {}, + "grid_x": 85, + "grid_y": 105, + "segment": "SEG_DSP4_R_X33Y95", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X35Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y0": { + "bits": {}, + "grid_x": 90, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X35Y0", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y1": { + "bits": {}, + "grid_x": 90, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X35Y1", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y10": { + "bits": {}, + "grid_x": 90, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X35Y10", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y100": { + "bits": {}, + "grid_x": 90, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X35Y100", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y101": { + "bits": {}, + "grid_x": 90, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X35Y101", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y102": { + "bits": {}, + "grid_x": 90, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X35Y102", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y103": { + "bits": {}, + "grid_x": 90, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X35Y103", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y104": { + "bits": {}, + "grid_x": 90, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X35Y104", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y105": { + "bits": {}, + "grid_x": 90, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X35Y105", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y106": { + "bits": {}, + "grid_x": 90, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X35Y106", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y107": { + "bits": {}, + "grid_x": 90, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X35Y107", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y108": { + "bits": {}, + "grid_x": 90, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X35Y108", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y109": { + "bits": {}, + "grid_x": 90, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X35Y109", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y11": { + "bits": {}, + "grid_x": 90, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X35Y11", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y110": { + "bits": {}, + "grid_x": 90, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X35Y110", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y111": { + "bits": {}, + "grid_x": 90, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X35Y111", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y112": { + "bits": {}, + "grid_x": 90, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X35Y112", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y113": { + "bits": {}, + "grid_x": 90, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X35Y113", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y114": { + "bits": {}, + "grid_x": 90, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X35Y114", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y115": { + "bits": {}, + "grid_x": 90, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X35Y115", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y116": { + "bits": {}, + "grid_x": 90, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X35Y116", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y117": { + "bits": {}, + "grid_x": 90, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X35Y117", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y118": { + "bits": {}, + "grid_x": 90, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X35Y118", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y119": { + "bits": {}, + "grid_x": 90, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X35Y119", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y12": { + "bits": {}, + "grid_x": 90, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X35Y12", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y120": { + "bits": {}, + "grid_x": 90, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X35Y120", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y121": { + "bits": {}, + "grid_x": 90, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X35Y121", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y122": { + "bits": {}, + "grid_x": 90, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X35Y122", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y123": { + "bits": {}, + "grid_x": 90, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X35Y123", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y124": { + "bits": {}, + "grid_x": 90, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X35Y124", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y125": { + "bits": {}, + "grid_x": 90, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X35Y125", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y126": { + "bits": {}, + "grid_x": 90, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X35Y126", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y127": { + "bits": {}, + "grid_x": 90, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X35Y127", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y128": { + "bits": {}, + "grid_x": 90, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X35Y128", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y129": { + "bits": {}, + "grid_x": 90, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X35Y129", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y13": { + "bits": {}, + "grid_x": 90, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X35Y13", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y130": { + "bits": {}, + "grid_x": 90, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X35Y130", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y131": { + "bits": {}, + "grid_x": 90, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X35Y131", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y132": { + "bits": {}, + "grid_x": 90, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X35Y132", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y133": { + "bits": {}, + "grid_x": 90, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X35Y133", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y134": { + "bits": {}, + "grid_x": 90, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X35Y134", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y135": { + "bits": {}, + "grid_x": 90, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X35Y135", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y136": { + "bits": {}, + "grid_x": 90, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X35Y136", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y137": { + "bits": {}, + "grid_x": 90, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X35Y137", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y138": { + "bits": {}, + "grid_x": 90, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X35Y138", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y139": { + "bits": {}, + "grid_x": 90, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X35Y139", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y14": { + "bits": {}, + "grid_x": 90, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X35Y14", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y140": { + "bits": {}, + "grid_x": 90, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X35Y140", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y141": { + "bits": {}, + "grid_x": 90, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X35Y141", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y142": { + "bits": {}, + "grid_x": 90, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X35Y142", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y143": { + "bits": {}, + "grid_x": 90, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X35Y143", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y144": { + "bits": {}, + "grid_x": 90, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X35Y144", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y145": { + "bits": {}, + "grid_x": 90, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X35Y145", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y146": { + "bits": {}, + "grid_x": 90, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X35Y146", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y147": { + "bits": {}, + "grid_x": 90, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X35Y147", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y148": { + "bits": {}, + "grid_x": 90, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X35Y148", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y149": { + "bits": {}, + "grid_x": 90, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X35Y149", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y15": { + "bits": {}, + "grid_x": 90, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X35Y15", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y150": { + "bits": {}, + "grid_x": 90, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X35Y150", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y151": { + "bits": {}, + "grid_x": 90, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X35Y151", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y152": { + "bits": {}, + "grid_x": 90, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X35Y152", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y153": { + "bits": {}, + "grid_x": 90, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X35Y153", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y154": { + "bits": {}, + "grid_x": 90, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X35Y154", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y155": { + "bits": {}, + "grid_x": 90, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X35Y155", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y156": { + "bits": {}, + "grid_x": 90, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X35Y156", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y157": { + "bits": {}, + "grid_x": 90, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X35Y157", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y158": { + "bits": {}, + "grid_x": 90, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X35Y158", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y159": { + "bits": {}, + "grid_x": 90, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X35Y159", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y16": { + "bits": {}, + "grid_x": 90, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X35Y16", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y160": { + "bits": {}, + "grid_x": 90, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X35Y160", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y161": { + "bits": {}, + "grid_x": 90, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X35Y161", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y162": { + "bits": {}, + "grid_x": 90, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X35Y162", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y163": { + "bits": {}, + "grid_x": 90, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X35Y163", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y164": { + "bits": {}, + "grid_x": 90, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X35Y164", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y165": { + "bits": {}, + "grid_x": 90, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X35Y165", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y166": { + "bits": {}, + "grid_x": 90, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X35Y166", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y167": { + "bits": {}, + "grid_x": 90, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X35Y167", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y168": { + "bits": {}, + "grid_x": 90, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X35Y168", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y169": { + "bits": {}, + "grid_x": 90, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X35Y169", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y17": { + "bits": {}, + "grid_x": 90, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X35Y17", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y170": { + "bits": {}, + "grid_x": 90, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X35Y170", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y171": { + "bits": {}, + "grid_x": 90, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X35Y171", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y172": { + "bits": {}, + "grid_x": 90, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X35Y172", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y173": { + "bits": {}, + "grid_x": 90, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X35Y173", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y174": { + "bits": {}, + "grid_x": 90, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X35Y174", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y175": { + "bits": {}, + "grid_x": 90, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X35Y175", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y176": { + "bits": {}, + "grid_x": 90, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X35Y176", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y177": { + "bits": {}, + "grid_x": 90, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X35Y177", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y178": { + "bits": {}, + "grid_x": 90, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X35Y178", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y179": { + "bits": {}, + "grid_x": 90, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X35Y179", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y18": { + "bits": {}, + "grid_x": 90, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X35Y18", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y180": { + "bits": {}, + "grid_x": 90, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X35Y180", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y181": { + "bits": {}, + "grid_x": 90, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X35Y181", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y182": { + "bits": {}, + "grid_x": 90, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X35Y182", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y183": { + "bits": {}, + "grid_x": 90, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X35Y183", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y184": { + "bits": {}, + "grid_x": 90, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X35Y184", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y185": { + "bits": {}, + "grid_x": 90, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X35Y185", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y186": { + "bits": {}, + "grid_x": 90, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X35Y186", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y187": { + "bits": {}, + "grid_x": 90, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X35Y187", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y188": { + "bits": {}, + "grid_x": 90, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X35Y188", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y189": { + "bits": {}, + "grid_x": 90, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X35Y189", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y19": { + "bits": {}, + "grid_x": 90, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X35Y19", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y190": { + "bits": {}, + "grid_x": 90, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X35Y190", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y191": { + "bits": {}, + "grid_x": 90, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X35Y191", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y192": { + "bits": {}, + "grid_x": 90, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X35Y192", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y193": { + "bits": {}, + "grid_x": 90, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X35Y193", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y194": { + "bits": {}, + "grid_x": 90, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X35Y194", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y195": { + "bits": {}, + "grid_x": 90, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X35Y195", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y196": { + "bits": {}, + "grid_x": 90, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X35Y196", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y197": { + "bits": {}, + "grid_x": 90, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X35Y197", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y198": { + "bits": {}, + "grid_x": 90, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X35Y198", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y199": { + "bits": {}, + "grid_x": 90, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X35Y199", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y2": { + "bits": {}, + "grid_x": 90, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X35Y2", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y20": { + "bits": {}, + "grid_x": 90, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X35Y20", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y21": { + "bits": {}, + "grid_x": 90, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X35Y21", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y22": { + "bits": {}, + "grid_x": 90, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X35Y22", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y23": { + "bits": {}, + "grid_x": 90, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X35Y23", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y24": { + "bits": {}, + "grid_x": 90, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X35Y24", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y25": { + "bits": {}, + "grid_x": 90, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X35Y25", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y26": { + "bits": {}, + "grid_x": 90, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X35Y26", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y27": { + "bits": {}, + "grid_x": 90, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X35Y27", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y28": { + "bits": {}, + "grid_x": 90, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X35Y28", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y29": { + "bits": {}, + "grid_x": 90, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X35Y29", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y3": { + "bits": {}, + "grid_x": 90, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X35Y3", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y30": { + "bits": {}, + "grid_x": 90, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X35Y30", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y31": { + "bits": {}, + "grid_x": 90, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X35Y31", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y32": { + "bits": {}, + "grid_x": 90, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X35Y32", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y33": { + "bits": {}, + "grid_x": 90, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X35Y33", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y34": { + "bits": {}, + "grid_x": 90, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X35Y34", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y35": { + "bits": {}, + "grid_x": 90, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X35Y35", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y36": { + "bits": {}, + "grid_x": 90, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X35Y36", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y37": { + "bits": {}, + "grid_x": 90, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X35Y37", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y38": { + "bits": {}, + "grid_x": 90, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X35Y38", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y39": { + "bits": {}, + "grid_x": 90, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X35Y39", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y4": { + "bits": {}, + "grid_x": 90, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X35Y4", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y40": { + "bits": {}, + "grid_x": 90, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X35Y40", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y41": { + "bits": {}, + "grid_x": 90, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X35Y41", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y42": { + "bits": {}, + "grid_x": 90, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X35Y42", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y43": { + "bits": {}, + "grid_x": 90, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X35Y43", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y44": { + "bits": {}, + "grid_x": 90, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X35Y44", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y45": { + "bits": {}, + "grid_x": 90, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X35Y45", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y46": { + "bits": {}, + "grid_x": 90, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X35Y46", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y47": { + "bits": {}, + "grid_x": 90, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X35Y47", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y48": { + "bits": {}, + "grid_x": 90, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X35Y48", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y49": { + "bits": {}, + "grid_x": 90, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X35Y49", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y5": { + "bits": {}, + "grid_x": 90, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X35Y5", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y50": { + "bits": {}, + "grid_x": 90, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X35Y50", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y51": { + "bits": {}, + "grid_x": 90, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X35Y51", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y52": { + "bits": {}, + "grid_x": 90, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X35Y52", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y53": { + "bits": {}, + "grid_x": 90, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X35Y53", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y54": { + "bits": {}, + "grid_x": 90, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X35Y54", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y55": { + "bits": {}, + "grid_x": 90, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X35Y55", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y56": { + "bits": {}, + "grid_x": 90, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X35Y56", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y57": { + "bits": {}, + "grid_x": 90, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X35Y57", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y58": { + "bits": {}, + "grid_x": 90, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X35Y58", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y59": { + "bits": {}, + "grid_x": 90, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X35Y59", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y6": { + "bits": {}, + "grid_x": 90, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X35Y6", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y60": { + "bits": {}, + "grid_x": 90, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X35Y60", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y61": { + "bits": {}, + "grid_x": 90, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X35Y61", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y62": { + "bits": {}, + "grid_x": 90, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X35Y62", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y63": { + "bits": {}, + "grid_x": 90, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X35Y63", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y64": { + "bits": {}, + "grid_x": 90, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X35Y64", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y65": { + "bits": {}, + "grid_x": 90, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X35Y65", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y66": { + "bits": {}, + "grid_x": 90, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X35Y66", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y67": { + "bits": {}, + "grid_x": 90, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X35Y67", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y68": { + "bits": {}, + "grid_x": 90, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X35Y68", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y69": { + "bits": {}, + "grid_x": 90, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X35Y69", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y7": { + "bits": {}, + "grid_x": 90, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X35Y7", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y70": { + "bits": {}, + "grid_x": 90, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X35Y70", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y71": { + "bits": {}, + "grid_x": 90, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X35Y71", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y72": { + "bits": {}, + "grid_x": 90, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X35Y72", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y73": { + "bits": {}, + "grid_x": 90, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X35Y73", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y74": { + "bits": {}, + "grid_x": 90, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X35Y74", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y75": { + "bits": {}, + "grid_x": 90, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X35Y75", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y76": { + "bits": {}, + "grid_x": 90, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X35Y76", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y77": { + "bits": {}, + "grid_x": 90, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X35Y77", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y78": { + "bits": {}, + "grid_x": 90, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X35Y78", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y79": { + "bits": {}, + "grid_x": 90, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X35Y79", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y8": { + "bits": {}, + "grid_x": 90, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X35Y8", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y80": { + "bits": {}, + "grid_x": 90, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X35Y80", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y81": { + "bits": {}, + "grid_x": 90, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X35Y81", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y82": { + "bits": {}, + "grid_x": 90, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X35Y82", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y83": { + "bits": {}, + "grid_x": 90, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X35Y83", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y84": { + "bits": {}, + "grid_x": 90, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X35Y84", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y85": { + "bits": {}, + "grid_x": 90, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X35Y85", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y86": { + "bits": {}, + "grid_x": 90, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X35Y86", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y87": { + "bits": {}, + "grid_x": 90, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X35Y87", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y88": { + "bits": {}, + "grid_x": 90, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X35Y88", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y89": { + "bits": {}, + "grid_x": 90, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X35Y89", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y9": { + "bits": {}, + "grid_x": 90, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X35Y9", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y90": { + "bits": {}, + "grid_x": 90, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X35Y90", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y91": { + "bits": {}, + "grid_x": 90, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X35Y91", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y92": { + "bits": {}, + "grid_x": 90, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X35Y92", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y93": { + "bits": {}, + "grid_x": 90, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X35Y93", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y94": { + "bits": {}, + "grid_x": 90, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X35Y94", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y95": { + "bits": {}, + "grid_x": 90, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X35Y95", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y96": { + "bits": {}, + "grid_x": 90, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X35Y96", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y97": { + "bits": {}, + "grid_x": 90, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X35Y97", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y98": { + "bits": {}, + "grid_x": 90, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X35Y98", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X35Y99": { + "bits": {}, + "grid_x": 90, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X35Y99", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X38Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y0": { + "bits": {}, + "grid_x": 95, + "grid_y": 207, + "segment": "SEG_BRAM0_R_X37Y0", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y1": { + "bits": {}, + "grid_x": 95, + "grid_y": 206, + "segment": "SEG_BRAM1_R_X37Y0", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y10": { + "bits": {}, + "grid_x": 95, + "grid_y": 197, + "segment": "SEG_BRAM0_R_X37Y10", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y100": { + "bits": {}, + "grid_x": 95, + "grid_y": 103, + "sites": { + "TIEOFF_X40Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y101": { + "bits": {}, + "grid_x": 95, + "grid_y": 102, + "sites": { + "TIEOFF_X40Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y102": { + "bits": {}, + "grid_x": 95, + "grid_y": 101, + "sites": { + "TIEOFF_X40Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y103": { + "bits": {}, + "grid_x": 95, + "grid_y": 100, + "sites": { + "TIEOFF_X40Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y104": { + "bits": {}, + "grid_x": 95, + "grid_y": 99, + "sites": { + "TIEOFF_X40Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y105": { + "bits": {}, + "grid_x": 95, + "grid_y": 98, + "sites": { + "TIEOFF_X40Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y106": { + "bits": {}, + "grid_x": 95, + "grid_y": 97, + "sites": { + "TIEOFF_X40Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y107": { + "bits": {}, + "grid_x": 95, + "grid_y": 96, + "sites": { + "TIEOFF_X40Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y108": { + "bits": {}, + "grid_x": 95, + "grid_y": 95, + "sites": { + "TIEOFF_X40Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y109": { + "bits": {}, + "grid_x": 95, + "grid_y": 94, + "sites": { + "TIEOFF_X40Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y11": { + "bits": {}, + "grid_x": 95, + "grid_y": 196, + "segment": "SEG_BRAM1_R_X37Y10", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y110": { + "bits": {}, + "grid_x": 95, + "grid_y": 93, + "sites": { + "TIEOFF_X40Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y111": { + "bits": {}, + "grid_x": 95, + "grid_y": 92, + "sites": { + "TIEOFF_X40Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y112": { + "bits": {}, + "grid_x": 95, + "grid_y": 91, + "sites": { + "TIEOFF_X40Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y113": { + "bits": {}, + "grid_x": 95, + "grid_y": 90, + "sites": { + "TIEOFF_X40Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y114": { + "bits": {}, + "grid_x": 95, + "grid_y": 89, + "sites": { + "TIEOFF_X40Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y115": { + "bits": {}, + "grid_x": 95, + "grid_y": 88, + "sites": { + "TIEOFF_X40Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y116": { + "bits": {}, + "grid_x": 95, + "grid_y": 87, + "sites": { + "TIEOFF_X40Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y117": { + "bits": {}, + "grid_x": 95, + "grid_y": 86, + "sites": { + "TIEOFF_X40Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y118": { + "bits": {}, + "grid_x": 95, + "grid_y": 85, + "sites": { + "TIEOFF_X40Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y119": { + "bits": {}, + "grid_x": 95, + "grid_y": 84, + "sites": { + "TIEOFF_X40Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y12": { + "bits": {}, + "grid_x": 95, + "grid_y": 195, + "segment": "SEG_BRAM2_R_X37Y10", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y120": { + "bits": {}, + "grid_x": 95, + "grid_y": 83, + "sites": { + "TIEOFF_X40Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y121": { + "bits": {}, + "grid_x": 95, + "grid_y": 82, + "sites": { + "TIEOFF_X40Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y122": { + "bits": {}, + "grid_x": 95, + "grid_y": 81, + "sites": { + "TIEOFF_X40Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y123": { + "bits": {}, + "grid_x": 95, + "grid_y": 80, + "sites": { + "TIEOFF_X40Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y124": { + "bits": {}, + "grid_x": 95, + "grid_y": 79, + "sites": { + "TIEOFF_X40Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y125": { + "bits": {}, + "grid_x": 95, + "grid_y": 77, + "sites": { + "TIEOFF_X40Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y126": { + "bits": {}, + "grid_x": 95, + "grid_y": 76, + "sites": { + "TIEOFF_X40Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y127": { + "bits": {}, + "grid_x": 95, + "grid_y": 75, + "sites": { + "TIEOFF_X40Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y128": { + "bits": {}, + "grid_x": 95, + "grid_y": 74, + "sites": { + "TIEOFF_X40Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y129": { + "bits": {}, + "grid_x": 95, + "grid_y": 73, + "sites": { + "TIEOFF_X40Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y13": { + "bits": {}, + "grid_x": 95, + "grid_y": 194, + "segment": "SEG_BRAM3_R_X37Y10", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y130": { + "bits": {}, + "grid_x": 95, + "grid_y": 72, + "sites": { + "TIEOFF_X40Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y131": { + "bits": {}, + "grid_x": 95, + "grid_y": 71, + "sites": { + "TIEOFF_X40Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y132": { + "bits": {}, + "grid_x": 95, + "grid_y": 70, + "sites": { + "TIEOFF_X40Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y133": { + "bits": {}, + "grid_x": 95, + "grid_y": 69, + "sites": { + "TIEOFF_X40Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y134": { + "bits": {}, + "grid_x": 95, + "grid_y": 68, + "sites": { + "TIEOFF_X40Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y135": { + "bits": {}, + "grid_x": 95, + "grid_y": 67, + "sites": { + "TIEOFF_X40Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y136": { + "bits": {}, + "grid_x": 95, + "grid_y": 66, + "sites": { + "TIEOFF_X40Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y137": { + "bits": {}, + "grid_x": 95, + "grid_y": 65, + "sites": { + "TIEOFF_X40Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y138": { + "bits": {}, + "grid_x": 95, + "grid_y": 64, + "sites": { + "TIEOFF_X40Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y139": { + "bits": {}, + "grid_x": 95, + "grid_y": 63, + "sites": { + "TIEOFF_X40Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y14": { + "bits": {}, + "grid_x": 95, + "grid_y": 193, + "segment": "SEG_BRAM4_R_X37Y10", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y140": { + "bits": {}, + "grid_x": 95, + "grid_y": 62, + "sites": { + "TIEOFF_X40Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y141": { + "bits": {}, + "grid_x": 95, + "grid_y": 61, + "sites": { + "TIEOFF_X40Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y142": { + "bits": {}, + "grid_x": 95, + "grid_y": 60, + "sites": { + "TIEOFF_X40Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y143": { + "bits": {}, + "grid_x": 95, + "grid_y": 59, + "sites": { + "TIEOFF_X40Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y144": { + "bits": {}, + "grid_x": 95, + "grid_y": 58, + "sites": { + "TIEOFF_X40Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y145": { + "bits": {}, + "grid_x": 95, + "grid_y": 57, + "sites": { + "TIEOFF_X40Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y146": { + "bits": {}, + "grid_x": 95, + "grid_y": 56, + "sites": { + "TIEOFF_X40Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y147": { + "bits": {}, + "grid_x": 95, + "grid_y": 55, + "sites": { + "TIEOFF_X40Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y148": { + "bits": {}, + "grid_x": 95, + "grid_y": 54, + "sites": { + "TIEOFF_X40Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y149": { + "bits": {}, + "grid_x": 95, + "grid_y": 53, + "sites": { + "TIEOFF_X40Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y15": { + "bits": {}, + "grid_x": 95, + "grid_y": 192, + "segment": "SEG_BRAM0_R_X37Y15", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y150": { + "bits": {}, + "grid_x": 95, + "grid_y": 51, + "sites": { + "TIEOFF_X40Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y151": { + "bits": {}, + "grid_x": 95, + "grid_y": 50, + "sites": { + "TIEOFF_X40Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y152": { + "bits": {}, + "grid_x": 95, + "grid_y": 49, + "sites": { + "TIEOFF_X40Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y153": { + "bits": {}, + "grid_x": 95, + "grid_y": 48, + "sites": { + "TIEOFF_X40Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y154": { + "bits": {}, + "grid_x": 95, + "grid_y": 47, + "sites": { + "TIEOFF_X40Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y155": { + "bits": {}, + "grid_x": 95, + "grid_y": 46, + "sites": { + "TIEOFF_X40Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y156": { + "bits": {}, + "grid_x": 95, + "grid_y": 45, + "sites": { + "TIEOFF_X40Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y157": { + "bits": {}, + "grid_x": 95, + "grid_y": 44, + "sites": { + "TIEOFF_X40Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y158": { + "bits": {}, + "grid_x": 95, + "grid_y": 43, + "sites": { + "TIEOFF_X40Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y159": { + "bits": {}, + "grid_x": 95, + "grid_y": 42, + "sites": { + "TIEOFF_X40Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y16": { + "bits": {}, + "grid_x": 95, + "grid_y": 191, + "segment": "SEG_BRAM1_R_X37Y15", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y160": { + "bits": {}, + "grid_x": 95, + "grid_y": 41, + "sites": { + "TIEOFF_X40Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y161": { + "bits": {}, + "grid_x": 95, + "grid_y": 40, + "sites": { + "TIEOFF_X40Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y162": { + "bits": {}, + "grid_x": 95, + "grid_y": 39, + "sites": { + "TIEOFF_X40Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y163": { + "bits": {}, + "grid_x": 95, + "grid_y": 38, + "sites": { + "TIEOFF_X40Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y164": { + "bits": {}, + "grid_x": 95, + "grid_y": 37, + "sites": { + "TIEOFF_X40Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y165": { + "bits": {}, + "grid_x": 95, + "grid_y": 36, + "sites": { + "TIEOFF_X40Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y166": { + "bits": {}, + "grid_x": 95, + "grid_y": 35, + "sites": { + "TIEOFF_X40Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y167": { + "bits": {}, + "grid_x": 95, + "grid_y": 34, + "sites": { + "TIEOFF_X40Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y168": { + "bits": {}, + "grid_x": 95, + "grid_y": 33, + "sites": { + "TIEOFF_X40Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y169": { + "bits": {}, + "grid_x": 95, + "grid_y": 32, + "sites": { + "TIEOFF_X40Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y17": { + "bits": {}, + "grid_x": 95, + "grid_y": 190, + "segment": "SEG_BRAM2_R_X37Y15", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y170": { + "bits": {}, + "grid_x": 95, + "grid_y": 31, + "sites": { + "TIEOFF_X40Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y171": { + "bits": {}, + "grid_x": 95, + "grid_y": 30, + "sites": { + "TIEOFF_X40Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y172": { + "bits": {}, + "grid_x": 95, + "grid_y": 29, + "sites": { + "TIEOFF_X40Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y173": { + "bits": {}, + "grid_x": 95, + "grid_y": 28, + "sites": { + "TIEOFF_X40Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y174": { + "bits": {}, + "grid_x": 95, + "grid_y": 27, + "sites": { + "TIEOFF_X40Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y175": { + "bits": {}, + "grid_x": 95, + "grid_y": 25, + "sites": { + "TIEOFF_X40Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y176": { + "bits": {}, + "grid_x": 95, + "grid_y": 24, + "sites": { + "TIEOFF_X40Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y177": { + "bits": {}, + "grid_x": 95, + "grid_y": 23, + "sites": { + "TIEOFF_X40Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y178": { + "bits": {}, + "grid_x": 95, + "grid_y": 22, + "sites": { + "TIEOFF_X40Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y179": { + "bits": {}, + "grid_x": 95, + "grid_y": 21, + "sites": { + "TIEOFF_X40Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y18": { + "bits": {}, + "grid_x": 95, + "grid_y": 189, + "segment": "SEG_BRAM3_R_X37Y15", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y180": { + "bits": {}, + "grid_x": 95, + "grid_y": 20, + "sites": { + "TIEOFF_X40Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y181": { + "bits": {}, + "grid_x": 95, + "grid_y": 19, + "sites": { + "TIEOFF_X40Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y182": { + "bits": {}, + "grid_x": 95, + "grid_y": 18, + "sites": { + "TIEOFF_X40Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y183": { + "bits": {}, + "grid_x": 95, + "grid_y": 17, + "sites": { + "TIEOFF_X40Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y184": { + "bits": {}, + "grid_x": 95, + "grid_y": 16, + "sites": { + "TIEOFF_X40Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y185": { + "bits": {}, + "grid_x": 95, + "grid_y": 15, + "sites": { + "TIEOFF_X40Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y186": { + "bits": {}, + "grid_x": 95, + "grid_y": 14, + "sites": { + "TIEOFF_X40Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y187": { + "bits": {}, + "grid_x": 95, + "grid_y": 13, + "sites": { + "TIEOFF_X40Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y188": { + "bits": {}, + "grid_x": 95, + "grid_y": 12, + "sites": { + "TIEOFF_X40Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y189": { + "bits": {}, + "grid_x": 95, + "grid_y": 11, + "sites": { + "TIEOFF_X40Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y19": { + "bits": {}, + "grid_x": 95, + "grid_y": 188, + "segment": "SEG_BRAM4_R_X37Y15", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y190": { + "bits": {}, + "grid_x": 95, + "grid_y": 10, + "sites": { + "TIEOFF_X40Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y191": { + "bits": {}, + "grid_x": 95, + "grid_y": 9, + "sites": { + "TIEOFF_X40Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y192": { + "bits": {}, + "grid_x": 95, + "grid_y": 8, + "sites": { + "TIEOFF_X40Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y193": { + "bits": {}, + "grid_x": 95, + "grid_y": 7, + "sites": { + "TIEOFF_X40Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y194": { + "bits": {}, + "grid_x": 95, + "grid_y": 6, + "sites": { + "TIEOFF_X40Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y195": { + "bits": {}, + "grid_x": 95, + "grid_y": 5, + "sites": { + "TIEOFF_X40Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y196": { + "bits": {}, + "grid_x": 95, + "grid_y": 4, + "sites": { + "TIEOFF_X40Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y197": { + "bits": {}, + "grid_x": 95, + "grid_y": 3, + "sites": { + "TIEOFF_X40Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y198": { + "bits": {}, + "grid_x": 95, + "grid_y": 2, + "sites": { + "TIEOFF_X40Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y199": { + "bits": {}, + "grid_x": 95, + "grid_y": 1, + "sites": { + "TIEOFF_X40Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y2": { + "bits": {}, + "grid_x": 95, + "grid_y": 205, + "segment": "SEG_BRAM2_R_X37Y0", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y20": { + "bits": {}, + "grid_x": 95, + "grid_y": 187, + "segment": "SEG_BRAM0_R_X37Y20", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y21": { + "bits": {}, + "grid_x": 95, + "grid_y": 186, + "segment": "SEG_BRAM1_R_X37Y20", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y22": { + "bits": {}, + "grid_x": 95, + "grid_y": 185, + "segment": "SEG_BRAM2_R_X37Y20", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y23": { + "bits": {}, + "grid_x": 95, + "grid_y": 184, + "segment": "SEG_BRAM3_R_X37Y20", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y24": { + "bits": {}, + "grid_x": 95, + "grid_y": 183, + "segment": "SEG_BRAM4_R_X37Y20", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y25": { + "bits": {}, + "grid_x": 95, + "grid_y": 181, + "segment": "SEG_BRAM0_R_X37Y25", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y26": { + "bits": {}, + "grid_x": 95, + "grid_y": 180, + "segment": "SEG_BRAM1_R_X37Y25", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y27": { + "bits": {}, + "grid_x": 95, + "grid_y": 179, + "segment": "SEG_BRAM2_R_X37Y25", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y28": { + "bits": {}, + "grid_x": 95, + "grid_y": 178, + "segment": "SEG_BRAM3_R_X37Y25", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y29": { + "bits": {}, + "grid_x": 95, + "grid_y": 177, + "segment": "SEG_BRAM4_R_X37Y25", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y3": { + "bits": {}, + "grid_x": 95, + "grid_y": 204, + "segment": "SEG_BRAM3_R_X37Y0", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y30": { + "bits": {}, + "grid_x": 95, + "grid_y": 176, + "segment": "SEG_BRAM0_R_X37Y30", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y31": { + "bits": {}, + "grid_x": 95, + "grid_y": 175, + "segment": "SEG_BRAM1_R_X37Y30", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y32": { + "bits": {}, + "grid_x": 95, + "grid_y": 174, + "segment": "SEG_BRAM2_R_X37Y30", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y33": { + "bits": {}, + "grid_x": 95, + "grid_y": 173, + "segment": "SEG_BRAM3_R_X37Y30", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y34": { + "bits": {}, + "grid_x": 95, + "grid_y": 172, + "segment": "SEG_BRAM4_R_X37Y30", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y35": { + "bits": {}, + "grid_x": 95, + "grid_y": 171, + "segment": "SEG_BRAM0_R_X37Y35", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y36": { + "bits": {}, + "grid_x": 95, + "grid_y": 170, + "segment": "SEG_BRAM1_R_X37Y35", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y37": { + "bits": {}, + "grid_x": 95, + "grid_y": 169, + "segment": "SEG_BRAM2_R_X37Y35", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y38": { + "bits": {}, + "grid_x": 95, + "grid_y": 168, + "segment": "SEG_BRAM3_R_X37Y35", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y39": { + "bits": {}, + "grid_x": 95, + "grid_y": 167, + "segment": "SEG_BRAM4_R_X37Y35", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y4": { + "bits": {}, + "grid_x": 95, + "grid_y": 203, + "segment": "SEG_BRAM4_R_X37Y0", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y40": { + "bits": {}, + "grid_x": 95, + "grid_y": 166, + "segment": "SEG_BRAM0_R_X37Y40", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y41": { + "bits": {}, + "grid_x": 95, + "grid_y": 165, + "segment": "SEG_BRAM1_R_X37Y40", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y42": { + "bits": {}, + "grid_x": 95, + "grid_y": 164, + "segment": "SEG_BRAM2_R_X37Y40", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y43": { + "bits": {}, + "grid_x": 95, + "grid_y": 163, + "segment": "SEG_BRAM3_R_X37Y40", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y44": { + "bits": {}, + "grid_x": 95, + "grid_y": 162, + "segment": "SEG_BRAM4_R_X37Y40", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y45": { + "bits": {}, + "grid_x": 95, + "grid_y": 161, + "segment": "SEG_BRAM0_R_X37Y45", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y46": { + "bits": {}, + "grid_x": 95, + "grid_y": 160, + "segment": "SEG_BRAM1_R_X37Y45", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y47": { + "bits": {}, + "grid_x": 95, + "grid_y": 159, + "segment": "SEG_BRAM2_R_X37Y45", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y48": { + "bits": {}, + "grid_x": 95, + "grid_y": 158, + "segment": "SEG_BRAM3_R_X37Y45", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y49": { + "bits": {}, + "grid_x": 95, + "grid_y": 157, + "segment": "SEG_BRAM4_R_X37Y45", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y5": { + "bits": {}, + "grid_x": 95, + "grid_y": 202, + "segment": "SEG_BRAM0_R_X37Y5", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y50": { + "bits": {}, + "grid_x": 95, + "grid_y": 155, + "segment": "SEG_BRAM0_R_X37Y50", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y51": { + "bits": {}, + "grid_x": 95, + "grid_y": 154, + "segment": "SEG_BRAM1_R_X37Y50", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y52": { + "bits": {}, + "grid_x": 95, + "grid_y": 153, + "segment": "SEG_BRAM2_R_X37Y50", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y53": { + "bits": {}, + "grid_x": 95, + "grid_y": 152, + "segment": "SEG_BRAM3_R_X37Y50", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y54": { + "bits": {}, + "grid_x": 95, + "grid_y": 151, + "segment": "SEG_BRAM4_R_X37Y50", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y55": { + "bits": {}, + "grid_x": 95, + "grid_y": 150, + "segment": "SEG_BRAM0_R_X37Y55", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y56": { + "bits": {}, + "grid_x": 95, + "grid_y": 149, + "segment": "SEG_BRAM1_R_X37Y55", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y57": { + "bits": {}, + "grid_x": 95, + "grid_y": 148, + "segment": "SEG_BRAM2_R_X37Y55", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y58": { + "bits": {}, + "grid_x": 95, + "grid_y": 147, + "segment": "SEG_BRAM3_R_X37Y55", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y59": { + "bits": {}, + "grid_x": 95, + "grid_y": 146, + "segment": "SEG_BRAM4_R_X37Y55", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y6": { + "bits": {}, + "grid_x": 95, + "grid_y": 201, + "segment": "SEG_BRAM1_R_X37Y5", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y60": { + "bits": {}, + "grid_x": 95, + "grid_y": 145, + "segment": "SEG_BRAM0_R_X37Y60", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y61": { + "bits": {}, + "grid_x": 95, + "grid_y": 144, + "segment": "SEG_BRAM1_R_X37Y60", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y62": { + "bits": {}, + "grid_x": 95, + "grid_y": 143, + "segment": "SEG_BRAM2_R_X37Y60", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y63": { + "bits": {}, + "grid_x": 95, + "grid_y": 142, + "segment": "SEG_BRAM3_R_X37Y60", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y64": { + "bits": {}, + "grid_x": 95, + "grid_y": 141, + "segment": "SEG_BRAM4_R_X37Y60", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y65": { + "bits": {}, + "grid_x": 95, + "grid_y": 140, + "segment": "SEG_BRAM0_R_X37Y65", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y66": { + "bits": {}, + "grid_x": 95, + "grid_y": 139, + "segment": "SEG_BRAM1_R_X37Y65", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y67": { + "bits": {}, + "grid_x": 95, + "grid_y": 138, + "segment": "SEG_BRAM2_R_X37Y65", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y68": { + "bits": {}, + "grid_x": 95, + "grid_y": 137, + "segment": "SEG_BRAM3_R_X37Y65", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y69": { + "bits": {}, + "grid_x": 95, + "grid_y": 136, + "segment": "SEG_BRAM4_R_X37Y65", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y7": { + "bits": {}, + "grid_x": 95, + "grid_y": 200, + "segment": "SEG_BRAM2_R_X37Y5", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y70": { + "bits": {}, + "grid_x": 95, + "grid_y": 135, + "segment": "SEG_BRAM0_R_X37Y70", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y71": { + "bits": {}, + "grid_x": 95, + "grid_y": 134, + "segment": "SEG_BRAM1_R_X37Y70", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y72": { + "bits": {}, + "grid_x": 95, + "grid_y": 133, + "segment": "SEG_BRAM2_R_X37Y70", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y73": { + "bits": {}, + "grid_x": 95, + "grid_y": 132, + "segment": "SEG_BRAM3_R_X37Y70", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y74": { + "bits": {}, + "grid_x": 95, + "grid_y": 131, + "segment": "SEG_BRAM4_R_X37Y70", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y75": { + "bits": {}, + "grid_x": 95, + "grid_y": 129, + "segment": "SEG_BRAM0_R_X37Y75", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y76": { + "bits": {}, + "grid_x": 95, + "grid_y": 128, + "segment": "SEG_BRAM1_R_X37Y75", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y77": { + "bits": {}, + "grid_x": 95, + "grid_y": 127, + "segment": "SEG_BRAM2_R_X37Y75", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y78": { + "bits": {}, + "grid_x": 95, + "grid_y": 126, + "segment": "SEG_BRAM3_R_X37Y75", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y79": { + "bits": {}, + "grid_x": 95, + "grid_y": 125, + "segment": "SEG_BRAM4_R_X37Y75", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y8": { + "bits": {}, + "grid_x": 95, + "grid_y": 199, + "segment": "SEG_BRAM3_R_X37Y5", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y80": { + "bits": {}, + "grid_x": 95, + "grid_y": 124, + "segment": "SEG_BRAM0_R_X37Y80", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y81": { + "bits": {}, + "grid_x": 95, + "grid_y": 123, + "segment": "SEG_BRAM1_R_X37Y80", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y82": { + "bits": {}, + "grid_x": 95, + "grid_y": 122, + "segment": "SEG_BRAM2_R_X37Y80", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y83": { + "bits": {}, + "grid_x": 95, + "grid_y": 121, + "segment": "SEG_BRAM3_R_X37Y80", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y84": { + "bits": {}, + "grid_x": 95, + "grid_y": 120, + "segment": "SEG_BRAM4_R_X37Y80", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y85": { + "bits": {}, + "grid_x": 95, + "grid_y": 119, + "segment": "SEG_BRAM0_R_X37Y85", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y86": { + "bits": {}, + "grid_x": 95, + "grid_y": 118, + "segment": "SEG_BRAM1_R_X37Y85", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y87": { + "bits": {}, + "grid_x": 95, + "grid_y": 117, + "segment": "SEG_BRAM2_R_X37Y85", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y88": { + "bits": {}, + "grid_x": 95, + "grid_y": 116, + "segment": "SEG_BRAM3_R_X37Y85", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y89": { + "bits": {}, + "grid_x": 95, + "grid_y": 115, + "segment": "SEG_BRAM4_R_X37Y85", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y9": { + "bits": {}, + "grid_x": 95, + "grid_y": 198, + "segment": "SEG_BRAM4_R_X37Y5", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y90": { + "bits": {}, + "grid_x": 95, + "grid_y": 114, + "segment": "SEG_BRAM0_R_X37Y90", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y91": { + "bits": {}, + "grid_x": 95, + "grid_y": 113, + "segment": "SEG_BRAM1_R_X37Y90", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y92": { + "bits": {}, + "grid_x": 95, + "grid_y": 112, + "segment": "SEG_BRAM2_R_X37Y90", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y93": { + "bits": {}, + "grid_x": 95, + "grid_y": 111, + "segment": "SEG_BRAM3_R_X37Y90", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y94": { + "bits": {}, + "grid_x": 95, + "grid_y": 110, + "segment": "SEG_BRAM4_R_X37Y90", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y95": { + "bits": {}, + "grid_x": 95, + "grid_y": 109, + "segment": "SEG_BRAM0_R_X37Y95", + "segment_type": "bram0_r", + "sites": { + "TIEOFF_X40Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y96": { + "bits": {}, + "grid_x": 95, + "grid_y": 108, + "segment": "SEG_BRAM1_R_X37Y95", + "segment_type": "bram1_r", + "sites": { + "TIEOFF_X40Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y97": { + "bits": {}, + "grid_x": 95, + "grid_y": 107, + "segment": "SEG_BRAM2_R_X37Y95", + "segment_type": "bram2_r", + "sites": { + "TIEOFF_X40Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y98": { + "bits": {}, + "grid_x": 95, + "grid_y": 106, + "segment": "SEG_BRAM3_R_X37Y95", + "segment_type": "bram3_r", + "sites": { + "TIEOFF_X40Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X37Y99": { + "bits": {}, + "grid_x": 95, + "grid_y": 105, + "segment": "SEG_BRAM4_R_X37Y95", + "segment_type": "bram4_r", + "sites": { + "TIEOFF_X40Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y0": { + "bits": {}, + "grid_x": 101, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X39Y0", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y1": { + "bits": {}, + "grid_x": 101, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X39Y1", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y10": { + "bits": {}, + "grid_x": 101, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X39Y10", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y11": { + "bits": {}, + "grid_x": 101, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X39Y11", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y12": { + "bits": {}, + "grid_x": 101, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X39Y12", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y13": { + "bits": {}, + "grid_x": 101, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X39Y13", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y14": { + "bits": {}, + "grid_x": 101, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X39Y14", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y15": { + "bits": {}, + "grid_x": 101, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X39Y15", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y16": { + "bits": {}, + "grid_x": 101, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X39Y16", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y17": { + "bits": {}, + "grid_x": 101, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X39Y17", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y18": { + "bits": {}, + "grid_x": 101, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X39Y18", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y19": { + "bits": {}, + "grid_x": 101, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X39Y19", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y2": { + "bits": {}, + "grid_x": 101, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X39Y2", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y20": { + "bits": {}, + "grid_x": 101, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X39Y20", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y21": { + "bits": {}, + "grid_x": 101, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X39Y21", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y22": { + "bits": {}, + "grid_x": 101, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X39Y22", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y23": { + "bits": {}, + "grid_x": 101, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X39Y23", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y24": { + "bits": {}, + "grid_x": 101, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X39Y24", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y25": { + "bits": {}, + "grid_x": 101, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X39Y25", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y26": { + "bits": {}, + "grid_x": 101, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X39Y26", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y27": { + "bits": {}, + "grid_x": 101, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X39Y27", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y28": { + "bits": {}, + "grid_x": 101, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X39Y28", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y29": { + "bits": {}, + "grid_x": 101, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X39Y29", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y3": { + "bits": {}, + "grid_x": 101, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X39Y3", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y30": { + "bits": {}, + "grid_x": 101, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X39Y30", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y31": { + "bits": {}, + "grid_x": 101, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X39Y31", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y32": { + "bits": {}, + "grid_x": 101, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X39Y32", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y33": { + "bits": {}, + "grid_x": 101, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X39Y33", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y34": { + "bits": {}, + "grid_x": 101, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X39Y34", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y35": { + "bits": {}, + "grid_x": 101, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X39Y35", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y36": { + "bits": {}, + "grid_x": 101, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X39Y36", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y37": { + "bits": {}, + "grid_x": 101, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X39Y37", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y38": { + "bits": {}, + "grid_x": 101, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X39Y38", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y39": { + "bits": {}, + "grid_x": 101, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X39Y39", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y4": { + "bits": {}, + "grid_x": 101, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X39Y4", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y40": { + "bits": {}, + "grid_x": 101, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X39Y40", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y41": { + "bits": {}, + "grid_x": 101, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X39Y41", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y42": { + "bits": {}, + "grid_x": 101, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X39Y42", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y43": { + "bits": {}, + "grid_x": 101, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X39Y43", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y44": { + "bits": {}, + "grid_x": 101, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X39Y44", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y45": { + "bits": {}, + "grid_x": 101, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X39Y45", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y46": { + "bits": {}, + "grid_x": 101, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X39Y46", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y47": { + "bits": {}, + "grid_x": 101, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X39Y47", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y48": { + "bits": {}, + "grid_x": 101, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X39Y48", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y49": { + "bits": {}, + "grid_x": 101, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X39Y49", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y5": { + "bits": {}, + "grid_x": 101, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X39Y5", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y50": { + "bits": {}, + "grid_x": 101, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X39Y50", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y51": { + "bits": {}, + "grid_x": 101, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X39Y51", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y52": { + "bits": {}, + "grid_x": 101, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X39Y52", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y53": { + "bits": {}, + "grid_x": 101, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X39Y53", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y54": { + "bits": {}, + "grid_x": 101, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X39Y54", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y55": { + "bits": {}, + "grid_x": 101, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X39Y55", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y56": { + "bits": {}, + "grid_x": 101, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X39Y56", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y57": { + "bits": {}, + "grid_x": 101, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X39Y57", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y58": { + "bits": {}, + "grid_x": 101, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X39Y58", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y59": { + "bits": {}, + "grid_x": 101, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X39Y59", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y6": { + "bits": {}, + "grid_x": 101, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X39Y6", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y60": { + "bits": {}, + "grid_x": 101, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X39Y60", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y61": { + "bits": {}, + "grid_x": 101, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X39Y61", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y62": { + "bits": {}, + "grid_x": 101, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X39Y62", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y63": { + "bits": {}, + "grid_x": 101, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X39Y63", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y64": { + "bits": {}, + "grid_x": 101, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X39Y64", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y65": { + "bits": {}, + "grid_x": 101, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X39Y65", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y66": { + "bits": {}, + "grid_x": 101, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X39Y66", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y67": { + "bits": {}, + "grid_x": 101, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X39Y67", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y68": { + "bits": {}, + "grid_x": 101, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X39Y68", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y69": { + "bits": {}, + "grid_x": 101, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X39Y69", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y7": { + "bits": {}, + "grid_x": 101, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X39Y7", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y70": { + "bits": {}, + "grid_x": 101, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X39Y70", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y71": { + "bits": {}, + "grid_x": 101, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X39Y71", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y72": { + "bits": {}, + "grid_x": 101, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X39Y72", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y73": { + "bits": {}, + "grid_x": 101, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X39Y73", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y74": { + "bits": {}, + "grid_x": 101, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X39Y74", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y75": { + "bits": {}, + "grid_x": 101, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X39Y75", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y76": { + "bits": {}, + "grid_x": 101, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X39Y76", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y77": { + "bits": {}, + "grid_x": 101, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X39Y77", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y78": { + "bits": {}, + "grid_x": 101, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X39Y78", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y79": { + "bits": {}, + "grid_x": 101, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X39Y79", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y8": { + "bits": {}, + "grid_x": 101, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X39Y8", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y80": { + "bits": {}, + "grid_x": 101, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X39Y80", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y81": { + "bits": {}, + "grid_x": 101, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X39Y81", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y82": { + "bits": {}, + "grid_x": 101, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X39Y82", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y83": { + "bits": {}, + "grid_x": 101, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X39Y83", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y84": { + "bits": {}, + "grid_x": 101, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X39Y84", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y85": { + "bits": {}, + "grid_x": 101, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X39Y85", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y86": { + "bits": {}, + "grid_x": 101, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X39Y86", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y87": { + "bits": {}, + "grid_x": 101, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X39Y87", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y88": { + "bits": {}, + "grid_x": 101, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X39Y88", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y89": { + "bits": {}, + "grid_x": 101, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X39Y89", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y9": { + "bits": {}, + "grid_x": 101, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X39Y9", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y90": { + "bits": {}, + "grid_x": 101, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X39Y90", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y91": { + "bits": {}, + "grid_x": 101, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X39Y91", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y92": { + "bits": {}, + "grid_x": 101, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X39Y92", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y93": { + "bits": {}, + "grid_x": 101, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X39Y93", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y94": { + "bits": {}, + "grid_x": 101, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X39Y94", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y95": { + "bits": {}, + "grid_x": 101, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X39Y95", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y96": { + "bits": {}, + "grid_x": 101, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X39Y96", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y97": { + "bits": {}, + "grid_x": 101, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X39Y97", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y98": { + "bits": {}, + "grid_x": 101, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X39Y98", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X39Y99": { + "bits": {}, + "grid_x": 101, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X39Y99", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X42Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y0": { + "bits": {}, + "grid_x": 12, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X3Y0", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y1": { + "bits": {}, + "grid_x": 12, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X3Y1", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y10": { + "bits": {}, + "grid_x": 12, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X3Y10", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y100": { + "bits": {}, + "grid_x": 12, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X3Y100", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y101": { + "bits": {}, + "grid_x": 12, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X3Y101", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y102": { + "bits": {}, + "grid_x": 12, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X3Y102", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y103": { + "bits": {}, + "grid_x": 12, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X3Y103", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y104": { + "bits": {}, + "grid_x": 12, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X3Y104", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y105": { + "bits": {}, + "grid_x": 12, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X3Y105", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y106": { + "bits": {}, + "grid_x": 12, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X3Y106", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y107": { + "bits": {}, + "grid_x": 12, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X3Y107", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y108": { + "bits": {}, + "grid_x": 12, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X3Y108", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y109": { + "bits": {}, + "grid_x": 12, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X3Y109", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y11": { + "bits": {}, + "grid_x": 12, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X3Y11", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y110": { + "bits": {}, + "grid_x": 12, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X3Y110", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y111": { + "bits": {}, + "grid_x": 12, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X3Y111", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y112": { + "bits": {}, + "grid_x": 12, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X3Y112", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y113": { + "bits": {}, + "grid_x": 12, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X3Y113", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y114": { + "bits": {}, + "grid_x": 12, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X3Y114", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y115": { + "bits": {}, + "grid_x": 12, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X3Y115", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y116": { + "bits": {}, + "grid_x": 12, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X3Y116", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y117": { + "bits": {}, + "grid_x": 12, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X3Y117", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y118": { + "bits": {}, + "grid_x": 12, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X3Y118", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y119": { + "bits": {}, + "grid_x": 12, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X3Y119", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y12": { + "bits": {}, + "grid_x": 12, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X3Y12", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y120": { + "bits": {}, + "grid_x": 12, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X3Y120", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y121": { + "bits": {}, + "grid_x": 12, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X3Y121", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y122": { + "bits": {}, + "grid_x": 12, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X3Y122", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y123": { + "bits": {}, + "grid_x": 12, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X3Y123", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y124": { + "bits": {}, + "grid_x": 12, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X3Y124", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y125": { + "bits": {}, + "grid_x": 12, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X3Y125", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y126": { + "bits": {}, + "grid_x": 12, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X3Y126", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y127": { + "bits": {}, + "grid_x": 12, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X3Y127", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y128": { + "bits": {}, + "grid_x": 12, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X3Y128", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y129": { + "bits": {}, + "grid_x": 12, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X3Y129", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y13": { + "bits": {}, + "grid_x": 12, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X3Y13", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y130": { + "bits": {}, + "grid_x": 12, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X3Y130", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y131": { + "bits": {}, + "grid_x": 12, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X3Y131", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y132": { + "bits": {}, + "grid_x": 12, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X3Y132", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y133": { + "bits": {}, + "grid_x": 12, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X3Y133", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y134": { + "bits": {}, + "grid_x": 12, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X3Y134", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y135": { + "bits": {}, + "grid_x": 12, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X3Y135", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y136": { + "bits": {}, + "grid_x": 12, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X3Y136", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y137": { + "bits": {}, + "grid_x": 12, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X3Y137", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y138": { + "bits": {}, + "grid_x": 12, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X3Y138", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y139": { + "bits": {}, + "grid_x": 12, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X3Y139", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y14": { + "bits": {}, + "grid_x": 12, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X3Y14", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y140": { + "bits": {}, + "grid_x": 12, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X3Y140", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y141": { + "bits": {}, + "grid_x": 12, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X3Y141", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y142": { + "bits": {}, + "grid_x": 12, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X3Y142", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y143": { + "bits": {}, + "grid_x": 12, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X3Y143", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y144": { + "bits": {}, + "grid_x": 12, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X3Y144", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y145": { + "bits": {}, + "grid_x": 12, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X3Y145", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y146": { + "bits": {}, + "grid_x": 12, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X3Y146", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y147": { + "bits": {}, + "grid_x": 12, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X3Y147", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y148": { + "bits": {}, + "grid_x": 12, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X3Y148", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y149": { + "bits": {}, + "grid_x": 12, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X3Y149", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y15": { + "bits": {}, + "grid_x": 12, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X3Y15", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y150": { + "bits": {}, + "grid_x": 12, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X3Y150", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y151": { + "bits": {}, + "grid_x": 12, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X3Y151", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y152": { + "bits": {}, + "grid_x": 12, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X3Y152", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y153": { + "bits": {}, + "grid_x": 12, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X3Y153", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y154": { + "bits": {}, + "grid_x": 12, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X3Y154", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y155": { + "bits": {}, + "grid_x": 12, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X3Y155", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y156": { + "bits": {}, + "grid_x": 12, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X3Y156", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y157": { + "bits": {}, + "grid_x": 12, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X3Y157", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y158": { + "bits": {}, + "grid_x": 12, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X3Y158", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y159": { + "bits": {}, + "grid_x": 12, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X3Y159", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y16": { + "bits": {}, + "grid_x": 12, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X3Y16", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y160": { + "bits": {}, + "grid_x": 12, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X3Y160", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y161": { + "bits": {}, + "grid_x": 12, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X3Y161", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y162": { + "bits": {}, + "grid_x": 12, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X3Y162", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y163": { + "bits": {}, + "grid_x": 12, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X3Y163", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y164": { + "bits": {}, + "grid_x": 12, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X3Y164", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y165": { + "bits": {}, + "grid_x": 12, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X3Y165", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y166": { + "bits": {}, + "grid_x": 12, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X3Y166", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y167": { + "bits": {}, + "grid_x": 12, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X3Y167", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y168": { + "bits": {}, + "grid_x": 12, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X3Y168", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y169": { + "bits": {}, + "grid_x": 12, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X3Y169", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y17": { + "bits": {}, + "grid_x": 12, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X3Y17", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y170": { + "bits": {}, + "grid_x": 12, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X3Y170", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y171": { + "bits": {}, + "grid_x": 12, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X3Y171", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y172": { + "bits": {}, + "grid_x": 12, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X3Y172", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y173": { + "bits": {}, + "grid_x": 12, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X3Y173", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y174": { + "bits": {}, + "grid_x": 12, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X3Y174", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y175": { + "bits": {}, + "grid_x": 12, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X3Y175", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y176": { + "bits": {}, + "grid_x": 12, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X3Y176", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y177": { + "bits": {}, + "grid_x": 12, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X3Y177", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y178": { + "bits": {}, + "grid_x": 12, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X3Y178", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y179": { + "bits": {}, + "grid_x": 12, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X3Y179", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y18": { + "bits": {}, + "grid_x": 12, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X3Y18", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y180": { + "bits": {}, + "grid_x": 12, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X3Y180", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y181": { + "bits": {}, + "grid_x": 12, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X3Y181", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y182": { + "bits": {}, + "grid_x": 12, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X3Y182", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y183": { + "bits": {}, + "grid_x": 12, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X3Y183", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y184": { + "bits": {}, + "grid_x": 12, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X3Y184", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y185": { + "bits": {}, + "grid_x": 12, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X3Y185", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y186": { + "bits": {}, + "grid_x": 12, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X3Y186", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y187": { + "bits": {}, + "grid_x": 12, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X3Y187", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y188": { + "bits": {}, + "grid_x": 12, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X3Y188", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y189": { + "bits": {}, + "grid_x": 12, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X3Y189", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y19": { + "bits": {}, + "grid_x": 12, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X3Y19", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y190": { + "bits": {}, + "grid_x": 12, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X3Y190", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y191": { + "bits": {}, + "grid_x": 12, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X3Y191", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y192": { + "bits": {}, + "grid_x": 12, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X3Y192", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y193": { + "bits": {}, + "grid_x": 12, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X3Y193", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y194": { + "bits": {}, + "grid_x": 12, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X3Y194", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y195": { + "bits": {}, + "grid_x": 12, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X3Y195", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y196": { + "bits": {}, + "grid_x": 12, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X3Y196", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y197": { + "bits": {}, + "grid_x": 12, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X3Y197", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y198": { + "bits": {}, + "grid_x": 12, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X3Y198", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y199": { + "bits": {}, + "grid_x": 12, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X3Y199", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y2": { + "bits": {}, + "grid_x": 12, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X3Y2", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y20": { + "bits": {}, + "grid_x": 12, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X3Y20", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y21": { + "bits": {}, + "grid_x": 12, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X3Y21", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y22": { + "bits": {}, + "grid_x": 12, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X3Y22", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y23": { + "bits": {}, + "grid_x": 12, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X3Y23", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y24": { + "bits": {}, + "grid_x": 12, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X3Y24", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y25": { + "bits": {}, + "grid_x": 12, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X3Y25", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y26": { + "bits": {}, + "grid_x": 12, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X3Y26", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y27": { + "bits": {}, + "grid_x": 12, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X3Y27", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y28": { + "bits": {}, + "grid_x": 12, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X3Y28", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y29": { + "bits": {}, + "grid_x": 12, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X3Y29", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y3": { + "bits": {}, + "grid_x": 12, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X3Y3", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y30": { + "bits": {}, + "grid_x": 12, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X3Y30", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y31": { + "bits": {}, + "grid_x": 12, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X3Y31", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y32": { + "bits": {}, + "grid_x": 12, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X3Y32", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y33": { + "bits": {}, + "grid_x": 12, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X3Y33", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y34": { + "bits": {}, + "grid_x": 12, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X3Y34", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y35": { + "bits": {}, + "grid_x": 12, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X3Y35", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y36": { + "bits": {}, + "grid_x": 12, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X3Y36", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y37": { + "bits": {}, + "grid_x": 12, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X3Y37", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y38": { + "bits": {}, + "grid_x": 12, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X3Y38", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y39": { + "bits": {}, + "grid_x": 12, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X3Y39", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y4": { + "bits": {}, + "grid_x": 12, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X3Y4", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y40": { + "bits": {}, + "grid_x": 12, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X3Y40", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y41": { + "bits": {}, + "grid_x": 12, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X3Y41", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y42": { + "bits": {}, + "grid_x": 12, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X3Y42", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y43": { + "bits": {}, + "grid_x": 12, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X3Y43", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y44": { + "bits": {}, + "grid_x": 12, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X3Y44", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y45": { + "bits": {}, + "grid_x": 12, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X3Y45", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y46": { + "bits": {}, + "grid_x": 12, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X3Y46", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y47": { + "bits": {}, + "grid_x": 12, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X3Y47", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y48": { + "bits": {}, + "grid_x": 12, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X3Y48", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y49": { + "bits": {}, + "grid_x": 12, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X3Y49", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y5": { + "bits": {}, + "grid_x": 12, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X3Y5", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X3Y50", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X3Y51", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X3Y52", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X3Y53", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X3Y54", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X3Y55", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X3Y56", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X3Y57", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X3Y58", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X3Y59", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y6": { + "bits": {}, + "grid_x": 12, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X3Y6", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X3Y60", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X3Y61", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X3Y62", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X3Y63", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X3Y64", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X3Y65", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X3Y66", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X3Y67", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X3Y68", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X3Y69", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y7": { + "bits": {}, + "grid_x": 12, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X3Y7", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X3Y70", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X3Y71", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X3Y72", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X3Y73", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X3Y74", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X3Y75", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X3Y76", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X3Y77", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X3Y78", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X3Y79", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y8": { + "bits": {}, + "grid_x": 12, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X3Y8", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X3Y80", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X3Y81", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X3Y82", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X3Y83", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X3Y84", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X3Y85", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X3Y86", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X3Y87", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X3Y88", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X3Y89", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y9": { + "bits": {}, + "grid_x": 12, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X3Y9", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X3Y90", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X3Y91", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X3Y92", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X3Y93", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X3Y94", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X3Y95", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X3Y96", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X3Y97", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X3Y98", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X3Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400180", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 12, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X3Y99", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X3Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y0": { + "bits": {}, + "grid_x": 105, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X41Y0", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y1": { + "bits": {}, + "grid_x": 105, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X41Y1", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y10": { + "bits": {}, + "grid_x": 105, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X41Y10", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y11": { + "bits": {}, + "grid_x": 105, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X41Y11", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y12": { + "bits": {}, + "grid_x": 105, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X41Y12", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y13": { + "bits": {}, + "grid_x": 105, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X41Y13", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y14": { + "bits": {}, + "grid_x": 105, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X41Y14", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y15": { + "bits": {}, + "grid_x": 105, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X41Y15", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y16": { + "bits": {}, + "grid_x": 105, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X41Y16", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y17": { + "bits": {}, + "grid_x": 105, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X41Y17", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y18": { + "bits": {}, + "grid_x": 105, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X41Y18", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y19": { + "bits": {}, + "grid_x": 105, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X41Y19", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y2": { + "bits": {}, + "grid_x": 105, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X41Y2", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y20": { + "bits": {}, + "grid_x": 105, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X41Y20", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y21": { + "bits": {}, + "grid_x": 105, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X41Y21", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y22": { + "bits": {}, + "grid_x": 105, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X41Y22", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y23": { + "bits": {}, + "grid_x": 105, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X41Y23", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y24": { + "bits": {}, + "grid_x": 105, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X41Y24", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y25": { + "bits": {}, + "grid_x": 105, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X41Y25", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y26": { + "bits": {}, + "grid_x": 105, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X41Y26", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y27": { + "bits": {}, + "grid_x": 105, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X41Y27", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y28": { + "bits": {}, + "grid_x": 105, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X41Y28", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y29": { + "bits": {}, + "grid_x": 105, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X41Y29", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y3": { + "bits": {}, + "grid_x": 105, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X41Y3", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y30": { + "bits": {}, + "grid_x": 105, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X41Y30", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y31": { + "bits": {}, + "grid_x": 105, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X41Y31", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y32": { + "bits": {}, + "grid_x": 105, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X41Y32", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y33": { + "bits": {}, + "grid_x": 105, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X41Y33", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y34": { + "bits": {}, + "grid_x": 105, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X41Y34", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y35": { + "bits": {}, + "grid_x": 105, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X41Y35", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y36": { + "bits": {}, + "grid_x": 105, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X41Y36", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y37": { + "bits": {}, + "grid_x": 105, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X41Y37", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y38": { + "bits": {}, + "grid_x": 105, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X41Y38", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y39": { + "bits": {}, + "grid_x": 105, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X41Y39", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y4": { + "bits": {}, + "grid_x": 105, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X41Y4", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y40": { + "bits": {}, + "grid_x": 105, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X41Y40", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y41": { + "bits": {}, + "grid_x": 105, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X41Y41", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y42": { + "bits": {}, + "grid_x": 105, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X41Y42", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y43": { + "bits": {}, + "grid_x": 105, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X41Y43", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y44": { + "bits": {}, + "grid_x": 105, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X41Y44", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y45": { + "bits": {}, + "grid_x": 105, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X41Y45", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y46": { + "bits": {}, + "grid_x": 105, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X41Y46", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y47": { + "bits": {}, + "grid_x": 105, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X41Y47", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y48": { + "bits": {}, + "grid_x": 105, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X41Y48", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y49": { + "bits": {}, + "grid_x": 105, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X41Y49", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y5": { + "bits": {}, + "grid_x": 105, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X41Y5", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y50": { + "bits": {}, + "grid_x": 105, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X41Y50", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y51": { + "bits": {}, + "grid_x": 105, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X41Y51", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y52": { + "bits": {}, + "grid_x": 105, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X41Y52", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y53": { + "bits": {}, + "grid_x": 105, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X41Y53", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y54": { + "bits": {}, + "grid_x": 105, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X41Y54", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y55": { + "bits": {}, + "grid_x": 105, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X41Y55", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y56": { + "bits": {}, + "grid_x": 105, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X41Y56", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y57": { + "bits": {}, + "grid_x": 105, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X41Y57", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y58": { + "bits": {}, + "grid_x": 105, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X41Y58", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y59": { + "bits": {}, + "grid_x": 105, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X41Y59", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y6": { + "bits": {}, + "grid_x": 105, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X41Y6", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y60": { + "bits": {}, + "grid_x": 105, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X41Y60", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y61": { + "bits": {}, + "grid_x": 105, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X41Y61", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y62": { + "bits": {}, + "grid_x": 105, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X41Y62", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y63": { + "bits": {}, + "grid_x": 105, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X41Y63", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y64": { + "bits": {}, + "grid_x": 105, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X41Y64", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y65": { + "bits": {}, + "grid_x": 105, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X41Y65", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y66": { + "bits": {}, + "grid_x": 105, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X41Y66", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y67": { + "bits": {}, + "grid_x": 105, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X41Y67", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y68": { + "bits": {}, + "grid_x": 105, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X41Y68", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y69": { + "bits": {}, + "grid_x": 105, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X41Y69", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y7": { + "bits": {}, + "grid_x": 105, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X41Y7", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y70": { + "bits": {}, + "grid_x": 105, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X41Y70", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y71": { + "bits": {}, + "grid_x": 105, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X41Y71", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y72": { + "bits": {}, + "grid_x": 105, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X41Y72", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y73": { + "bits": {}, + "grid_x": 105, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X41Y73", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y74": { + "bits": {}, + "grid_x": 105, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X41Y74", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y75": { + "bits": {}, + "grid_x": 105, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X41Y75", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y76": { + "bits": {}, + "grid_x": 105, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X41Y76", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y77": { + "bits": {}, + "grid_x": 105, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X41Y77", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y78": { + "bits": {}, + "grid_x": 105, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X41Y78", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y79": { + "bits": {}, + "grid_x": 105, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X41Y79", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y8": { + "bits": {}, + "grid_x": 105, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X41Y8", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y80": { + "bits": {}, + "grid_x": 105, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X41Y80", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y81": { + "bits": {}, + "grid_x": 105, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X41Y81", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y82": { + "bits": {}, + "grid_x": 105, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X41Y82", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y83": { + "bits": {}, + "grid_x": 105, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X41Y83", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y84": { + "bits": {}, + "grid_x": 105, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X41Y84", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y85": { + "bits": {}, + "grid_x": 105, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X41Y85", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y86": { + "bits": {}, + "grid_x": 105, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X41Y86", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y87": { + "bits": {}, + "grid_x": 105, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X41Y87", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y88": { + "bits": {}, + "grid_x": 105, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X41Y88", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y89": { + "bits": {}, + "grid_x": 105, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X41Y89", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y9": { + "bits": {}, + "grid_x": 105, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X41Y9", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y90": { + "bits": {}, + "grid_x": 105, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X41Y90", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y91": { + "bits": {}, + "grid_x": 105, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X41Y91", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y92": { + "bits": {}, + "grid_x": 105, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X41Y92", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y93": { + "bits": {}, + "grid_x": 105, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X41Y93", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y94": { + "bits": {}, + "grid_x": 105, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X41Y94", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y95": { + "bits": {}, + "grid_x": 105, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X41Y95", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y96": { + "bits": {}, + "grid_x": 105, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X41Y96", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y97": { + "bits": {}, + "grid_x": 105, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X41Y97", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y98": { + "bits": {}, + "grid_x": 105, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X41Y98", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X41Y99": { + "bits": {}, + "grid_x": 105, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X41Y99", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X44Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y0": { + "bits": {}, + "grid_x": 112, + "grid_y": 207, + "sites": { + "TIEOFF_X46Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y1": { + "bits": {}, + "grid_x": 112, + "grid_y": 206, + "sites": { + "TIEOFF_X46Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y10": { + "bits": {}, + "grid_x": 112, + "grid_y": 197, + "sites": { + "TIEOFF_X46Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y11": { + "bits": {}, + "grid_x": 112, + "grid_y": 196, + "sites": { + "TIEOFF_X46Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y12": { + "bits": {}, + "grid_x": 112, + "grid_y": 195, + "sites": { + "TIEOFF_X46Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y13": { + "bits": {}, + "grid_x": 112, + "grid_y": 194, + "sites": { + "TIEOFF_X46Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y14": { + "bits": {}, + "grid_x": 112, + "grid_y": 193, + "sites": { + "TIEOFF_X46Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y15": { + "bits": {}, + "grid_x": 112, + "grid_y": 192, + "sites": { + "TIEOFF_X46Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y16": { + "bits": {}, + "grid_x": 112, + "grid_y": 191, + "sites": { + "TIEOFF_X46Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y17": { + "bits": {}, + "grid_x": 112, + "grid_y": 190, + "sites": { + "TIEOFF_X46Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y18": { + "bits": {}, + "grid_x": 112, + "grid_y": 189, + "sites": { + "TIEOFF_X46Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y19": { + "bits": {}, + "grid_x": 112, + "grid_y": 188, + "sites": { + "TIEOFF_X46Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y2": { + "bits": {}, + "grid_x": 112, + "grid_y": 205, + "sites": { + "TIEOFF_X46Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y20": { + "bits": {}, + "grid_x": 112, + "grid_y": 187, + "sites": { + "TIEOFF_X46Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y21": { + "bits": {}, + "grid_x": 112, + "grid_y": 186, + "sites": { + "TIEOFF_X46Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y22": { + "bits": {}, + "grid_x": 112, + "grid_y": 185, + "sites": { + "TIEOFF_X46Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y23": { + "bits": {}, + "grid_x": 112, + "grid_y": 184, + "sites": { + "TIEOFF_X46Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y24": { + "bits": {}, + "grid_x": 112, + "grid_y": 183, + "sites": { + "TIEOFF_X46Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y25": { + "bits": {}, + "grid_x": 112, + "grid_y": 181, + "sites": { + "TIEOFF_X46Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y26": { + "bits": {}, + "grid_x": 112, + "grid_y": 180, + "sites": { + "TIEOFF_X46Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y27": { + "bits": {}, + "grid_x": 112, + "grid_y": 179, + "sites": { + "TIEOFF_X46Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y28": { + "bits": {}, + "grid_x": 112, + "grid_y": 178, + "sites": { + "TIEOFF_X46Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y29": { + "bits": {}, + "grid_x": 112, + "grid_y": 177, + "sites": { + "TIEOFF_X46Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y3": { + "bits": {}, + "grid_x": 112, + "grid_y": 204, + "sites": { + "TIEOFF_X46Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y30": { + "bits": {}, + "grid_x": 112, + "grid_y": 176, + "sites": { + "TIEOFF_X46Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y31": { + "bits": {}, + "grid_x": 112, + "grid_y": 175, + "sites": { + "TIEOFF_X46Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y32": { + "bits": {}, + "grid_x": 112, + "grid_y": 174, + "sites": { + "TIEOFF_X46Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y33": { + "bits": {}, + "grid_x": 112, + "grid_y": 173, + "sites": { + "TIEOFF_X46Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y34": { + "bits": {}, + "grid_x": 112, + "grid_y": 172, + "sites": { + "TIEOFF_X46Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y35": { + "bits": {}, + "grid_x": 112, + "grid_y": 171, + "sites": { + "TIEOFF_X46Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y36": { + "bits": {}, + "grid_x": 112, + "grid_y": 170, + "sites": { + "TIEOFF_X46Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y37": { + "bits": {}, + "grid_x": 112, + "grid_y": 169, + "sites": { + "TIEOFF_X46Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y38": { + "bits": {}, + "grid_x": 112, + "grid_y": 168, + "sites": { + "TIEOFF_X46Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y39": { + "bits": {}, + "grid_x": 112, + "grid_y": 167, + "sites": { + "TIEOFF_X46Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y4": { + "bits": {}, + "grid_x": 112, + "grid_y": 203, + "sites": { + "TIEOFF_X46Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y40": { + "bits": {}, + "grid_x": 112, + "grid_y": 166, + "sites": { + "TIEOFF_X46Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y41": { + "bits": {}, + "grid_x": 112, + "grid_y": 165, + "sites": { + "TIEOFF_X46Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y42": { + "bits": {}, + "grid_x": 112, + "grid_y": 164, + "sites": { + "TIEOFF_X46Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y43": { + "bits": {}, + "grid_x": 112, + "grid_y": 163, + "sites": { + "TIEOFF_X46Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y44": { + "bits": {}, + "grid_x": 112, + "grid_y": 162, + "sites": { + "TIEOFF_X46Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y45": { + "bits": {}, + "grid_x": 112, + "grid_y": 161, + "sites": { + "TIEOFF_X46Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y46": { + "bits": {}, + "grid_x": 112, + "grid_y": 160, + "sites": { + "TIEOFF_X46Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y47": { + "bits": {}, + "grid_x": 112, + "grid_y": 159, + "sites": { + "TIEOFF_X46Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y48": { + "bits": {}, + "grid_x": 112, + "grid_y": 158, + "sites": { + "TIEOFF_X46Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y49": { + "bits": {}, + "grid_x": 112, + "grid_y": 157, + "sites": { + "TIEOFF_X46Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y5": { + "bits": {}, + "grid_x": 112, + "grid_y": 202, + "sites": { + "TIEOFF_X46Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y50": { + "bits": {}, + "grid_x": 112, + "grid_y": 155, + "sites": { + "TIEOFF_X46Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y51": { + "bits": {}, + "grid_x": 112, + "grid_y": 154, + "sites": { + "TIEOFF_X46Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y52": { + "bits": {}, + "grid_x": 112, + "grid_y": 153, + "sites": { + "TIEOFF_X46Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y53": { + "bits": {}, + "grid_x": 112, + "grid_y": 152, + "sites": { + "TIEOFF_X46Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y54": { + "bits": {}, + "grid_x": 112, + "grid_y": 151, + "sites": { + "TIEOFF_X46Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y55": { + "bits": {}, + "grid_x": 112, + "grid_y": 150, + "sites": { + "TIEOFF_X46Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y56": { + "bits": {}, + "grid_x": 112, + "grid_y": 149, + "sites": { + "TIEOFF_X46Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y57": { + "bits": {}, + "grid_x": 112, + "grid_y": 148, + "sites": { + "TIEOFF_X46Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y58": { + "bits": {}, + "grid_x": 112, + "grid_y": 147, + "sites": { + "TIEOFF_X46Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y59": { + "bits": {}, + "grid_x": 112, + "grid_y": 146, + "sites": { + "TIEOFF_X46Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y6": { + "bits": {}, + "grid_x": 112, + "grid_y": 201, + "sites": { + "TIEOFF_X46Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y60": { + "bits": {}, + "grid_x": 112, + "grid_y": 145, + "sites": { + "TIEOFF_X46Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y61": { + "bits": {}, + "grid_x": 112, + "grid_y": 144, + "sites": { + "TIEOFF_X46Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y62": { + "bits": {}, + "grid_x": 112, + "grid_y": 143, + "sites": { + "TIEOFF_X46Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y63": { + "bits": {}, + "grid_x": 112, + "grid_y": 142, + "sites": { + "TIEOFF_X46Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y64": { + "bits": {}, + "grid_x": 112, + "grid_y": 141, + "sites": { + "TIEOFF_X46Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y65": { + "bits": {}, + "grid_x": 112, + "grid_y": 140, + "sites": { + "TIEOFF_X46Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y66": { + "bits": {}, + "grid_x": 112, + "grid_y": 139, + "sites": { + "TIEOFF_X46Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y67": { + "bits": {}, + "grid_x": 112, + "grid_y": 138, + "sites": { + "TIEOFF_X46Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y68": { + "bits": {}, + "grid_x": 112, + "grid_y": 137, + "sites": { + "TIEOFF_X46Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y69": { + "bits": {}, + "grid_x": 112, + "grid_y": 136, + "sites": { + "TIEOFF_X46Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y7": { + "bits": {}, + "grid_x": 112, + "grid_y": 200, + "sites": { + "TIEOFF_X46Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y70": { + "bits": {}, + "grid_x": 112, + "grid_y": 135, + "sites": { + "TIEOFF_X46Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y71": { + "bits": {}, + "grid_x": 112, + "grid_y": 134, + "sites": { + "TIEOFF_X46Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y72": { + "bits": {}, + "grid_x": 112, + "grid_y": 133, + "sites": { + "TIEOFF_X46Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y73": { + "bits": {}, + "grid_x": 112, + "grid_y": 132, + "sites": { + "TIEOFF_X46Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y74": { + "bits": {}, + "grid_x": 112, + "grid_y": 131, + "sites": { + "TIEOFF_X46Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y75": { + "bits": {}, + "grid_x": 112, + "grid_y": 129, + "sites": { + "TIEOFF_X46Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y76": { + "bits": {}, + "grid_x": 112, + "grid_y": 128, + "sites": { + "TIEOFF_X46Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y77": { + "bits": {}, + "grid_x": 112, + "grid_y": 127, + "sites": { + "TIEOFF_X46Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y78": { + "bits": {}, + "grid_x": 112, + "grid_y": 126, + "sites": { + "TIEOFF_X46Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y79": { + "bits": {}, + "grid_x": 112, + "grid_y": 125, + "sites": { + "TIEOFF_X46Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y8": { + "bits": {}, + "grid_x": 112, + "grid_y": 199, + "sites": { + "TIEOFF_X46Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y80": { + "bits": {}, + "grid_x": 112, + "grid_y": 124, + "sites": { + "TIEOFF_X46Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y81": { + "bits": {}, + "grid_x": 112, + "grid_y": 123, + "sites": { + "TIEOFF_X46Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y82": { + "bits": {}, + "grid_x": 112, + "grid_y": 122, + "sites": { + "TIEOFF_X46Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y83": { + "bits": {}, + "grid_x": 112, + "grid_y": 121, + "sites": { + "TIEOFF_X46Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y84": { + "bits": {}, + "grid_x": 112, + "grid_y": 120, + "sites": { + "TIEOFF_X46Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y85": { + "bits": {}, + "grid_x": 112, + "grid_y": 119, + "sites": { + "TIEOFF_X46Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y86": { + "bits": {}, + "grid_x": 112, + "grid_y": 118, + "sites": { + "TIEOFF_X46Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y87": { + "bits": {}, + "grid_x": 112, + "grid_y": 117, + "sites": { + "TIEOFF_X46Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y88": { + "bits": {}, + "grid_x": 112, + "grid_y": 116, + "sites": { + "TIEOFF_X46Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y89": { + "bits": {}, + "grid_x": 112, + "grid_y": 115, + "sites": { + "TIEOFF_X46Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y9": { + "bits": {}, + "grid_x": 112, + "grid_y": 198, + "sites": { + "TIEOFF_X46Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y90": { + "bits": {}, + "grid_x": 112, + "grid_y": 114, + "sites": { + "TIEOFF_X46Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y91": { + "bits": {}, + "grid_x": 112, + "grid_y": 113, + "sites": { + "TIEOFF_X46Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y92": { + "bits": {}, + "grid_x": 112, + "grid_y": 112, + "sites": { + "TIEOFF_X46Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y93": { + "bits": {}, + "grid_x": 112, + "grid_y": 111, + "sites": { + "TIEOFF_X46Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y94": { + "bits": {}, + "grid_x": 112, + "grid_y": 110, + "sites": { + "TIEOFF_X46Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y95": { + "bits": {}, + "grid_x": 112, + "grid_y": 109, + "sites": { + "TIEOFF_X46Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y96": { + "bits": {}, + "grid_x": 112, + "grid_y": 108, + "sites": { + "TIEOFF_X46Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y97": { + "bits": {}, + "grid_x": 112, + "grid_y": 107, + "sites": { + "TIEOFF_X46Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y98": { + "bits": {}, + "grid_x": 112, + "grid_y": 106, + "sites": { + "TIEOFF_X46Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X43Y99": { + "bits": {}, + "grid_x": 112, + "grid_y": 105, + "sites": { + "TIEOFF_X46Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y0": { + "bits": {}, + "grid_x": 16, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X5Y0", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y1": { + "bits": {}, + "grid_x": 16, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X5Y1", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y10": { + "bits": {}, + "grid_x": 16, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X5Y10", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y100": { + "bits": {}, + "grid_x": 16, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X5Y100", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y101": { + "bits": {}, + "grid_x": 16, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X5Y101", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y102": { + "bits": {}, + "grid_x": 16, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X5Y102", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y103": { + "bits": {}, + "grid_x": 16, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X5Y103", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y104": { + "bits": {}, + "grid_x": 16, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X5Y104", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y105": { + "bits": {}, + "grid_x": 16, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X5Y105", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y106": { + "bits": {}, + "grid_x": 16, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X5Y106", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y107": { + "bits": {}, + "grid_x": 16, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X5Y107", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y108": { + "bits": {}, + "grid_x": 16, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X5Y108", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y109": { + "bits": {}, + "grid_x": 16, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X5Y109", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y11": { + "bits": {}, + "grid_x": 16, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X5Y11", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y110": { + "bits": {}, + "grid_x": 16, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X5Y110", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y111": { + "bits": {}, + "grid_x": 16, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X5Y111", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y112": { + "bits": {}, + "grid_x": 16, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X5Y112", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y113": { + "bits": {}, + "grid_x": 16, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X5Y113", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y114": { + "bits": {}, + "grid_x": 16, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X5Y114", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y115": { + "bits": {}, + "grid_x": 16, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X5Y115", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y116": { + "bits": {}, + "grid_x": 16, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X5Y116", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y117": { + "bits": {}, + "grid_x": 16, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X5Y117", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y118": { + "bits": {}, + "grid_x": 16, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X5Y118", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y119": { + "bits": {}, + "grid_x": 16, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X5Y119", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y12": { + "bits": {}, + "grid_x": 16, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X5Y12", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y120": { + "bits": {}, + "grid_x": 16, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X5Y120", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y121": { + "bits": {}, + "grid_x": 16, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X5Y121", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y122": { + "bits": {}, + "grid_x": 16, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X5Y122", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y123": { + "bits": {}, + "grid_x": 16, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X5Y123", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y124": { + "bits": {}, + "grid_x": 16, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X5Y124", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y125": { + "bits": {}, + "grid_x": 16, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X5Y125", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y126": { + "bits": {}, + "grid_x": 16, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X5Y126", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y127": { + "bits": {}, + "grid_x": 16, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X5Y127", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y128": { + "bits": {}, + "grid_x": 16, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X5Y128", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y129": { + "bits": {}, + "grid_x": 16, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X5Y129", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y13": { + "bits": {}, + "grid_x": 16, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X5Y13", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y130": { + "bits": {}, + "grid_x": 16, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X5Y130", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y131": { + "bits": {}, + "grid_x": 16, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X5Y131", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y132": { + "bits": {}, + "grid_x": 16, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X5Y132", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y133": { + "bits": {}, + "grid_x": 16, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X5Y133", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y134": { + "bits": {}, + "grid_x": 16, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X5Y134", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y135": { + "bits": {}, + "grid_x": 16, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X5Y135", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y136": { + "bits": {}, + "grid_x": 16, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X5Y136", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y137": { + "bits": {}, + "grid_x": 16, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X5Y137", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y138": { + "bits": {}, + "grid_x": 16, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X5Y138", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y139": { + "bits": {}, + "grid_x": 16, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X5Y139", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y14": { + "bits": {}, + "grid_x": 16, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X5Y14", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y140": { + "bits": {}, + "grid_x": 16, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X5Y140", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y141": { + "bits": {}, + "grid_x": 16, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X5Y141", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y142": { + "bits": {}, + "grid_x": 16, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X5Y142", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y143": { + "bits": {}, + "grid_x": 16, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X5Y143", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y144": { + "bits": {}, + "grid_x": 16, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X5Y144", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y145": { + "bits": {}, + "grid_x": 16, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X5Y145", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y146": { + "bits": {}, + "grid_x": 16, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X5Y146", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y147": { + "bits": {}, + "grid_x": 16, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X5Y147", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y148": { + "bits": {}, + "grid_x": 16, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X5Y148", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y149": { + "bits": {}, + "grid_x": 16, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X5Y149", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y15": { + "bits": {}, + "grid_x": 16, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X5Y15", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y150": { + "bits": {}, + "grid_x": 16, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X5Y150", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y151": { + "bits": {}, + "grid_x": 16, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X5Y151", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y152": { + "bits": {}, + "grid_x": 16, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X5Y152", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y153": { + "bits": {}, + "grid_x": 16, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X5Y153", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y154": { + "bits": {}, + "grid_x": 16, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X5Y154", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y155": { + "bits": {}, + "grid_x": 16, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X5Y155", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y156": { + "bits": {}, + "grid_x": 16, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X5Y156", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y157": { + "bits": {}, + "grid_x": 16, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X5Y157", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y158": { + "bits": {}, + "grid_x": 16, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X5Y158", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y159": { + "bits": {}, + "grid_x": 16, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X5Y159", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y16": { + "bits": {}, + "grid_x": 16, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X5Y16", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y160": { + "bits": {}, + "grid_x": 16, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X5Y160", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y161": { + "bits": {}, + "grid_x": 16, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X5Y161", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y162": { + "bits": {}, + "grid_x": 16, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X5Y162", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y163": { + "bits": {}, + "grid_x": 16, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X5Y163", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y164": { + "bits": {}, + "grid_x": 16, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X5Y164", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y165": { + "bits": {}, + "grid_x": 16, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X5Y165", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y166": { + "bits": {}, + "grid_x": 16, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X5Y166", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y167": { + "bits": {}, + "grid_x": 16, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X5Y167", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y168": { + "bits": {}, + "grid_x": 16, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X5Y168", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y169": { + "bits": {}, + "grid_x": 16, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X5Y169", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y17": { + "bits": {}, + "grid_x": 16, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X5Y17", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y170": { + "bits": {}, + "grid_x": 16, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X5Y170", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y171": { + "bits": {}, + "grid_x": 16, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X5Y171", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y172": { + "bits": {}, + "grid_x": 16, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X5Y172", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y173": { + "bits": {}, + "grid_x": 16, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X5Y173", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y174": { + "bits": {}, + "grid_x": 16, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X5Y174", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y175": { + "bits": {}, + "grid_x": 16, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X5Y175", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y176": { + "bits": {}, + "grid_x": 16, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X5Y176", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y177": { + "bits": {}, + "grid_x": 16, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X5Y177", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y178": { + "bits": {}, + "grid_x": 16, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X5Y178", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y179": { + "bits": {}, + "grid_x": 16, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X5Y179", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y18": { + "bits": {}, + "grid_x": 16, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X5Y18", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y180": { + "bits": {}, + "grid_x": 16, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X5Y180", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y181": { + "bits": {}, + "grid_x": 16, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X5Y181", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y182": { + "bits": {}, + "grid_x": 16, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X5Y182", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y183": { + "bits": {}, + "grid_x": 16, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X5Y183", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y184": { + "bits": {}, + "grid_x": 16, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X5Y184", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y185": { + "bits": {}, + "grid_x": 16, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X5Y185", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y186": { + "bits": {}, + "grid_x": 16, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X5Y186", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y187": { + "bits": {}, + "grid_x": 16, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X5Y187", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y188": { + "bits": {}, + "grid_x": 16, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X5Y188", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y189": { + "bits": {}, + "grid_x": 16, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X5Y189", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y19": { + "bits": {}, + "grid_x": 16, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X5Y19", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y190": { + "bits": {}, + "grid_x": 16, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X5Y190", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y191": { + "bits": {}, + "grid_x": 16, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X5Y191", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y192": { + "bits": {}, + "grid_x": 16, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X5Y192", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y193": { + "bits": {}, + "grid_x": 16, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X5Y193", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y194": { + "bits": {}, + "grid_x": 16, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X5Y194", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y195": { + "bits": {}, + "grid_x": 16, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X5Y195", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y196": { + "bits": {}, + "grid_x": 16, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X5Y196", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y197": { + "bits": {}, + "grid_x": 16, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X5Y197", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y198": { + "bits": {}, + "grid_x": 16, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X5Y198", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y199": { + "bits": {}, + "grid_x": 16, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X5Y199", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y2": { + "bits": {}, + "grid_x": 16, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X5Y2", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y20": { + "bits": {}, + "grid_x": 16, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X5Y20", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y21": { + "bits": {}, + "grid_x": 16, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X5Y21", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y22": { + "bits": {}, + "grid_x": 16, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X5Y22", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y23": { + "bits": {}, + "grid_x": 16, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X5Y23", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y24": { + "bits": {}, + "grid_x": 16, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X5Y24", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y25": { + "bits": {}, + "grid_x": 16, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X5Y25", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y26": { + "bits": {}, + "grid_x": 16, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X5Y26", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y27": { + "bits": {}, + "grid_x": 16, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X5Y27", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y28": { + "bits": {}, + "grid_x": 16, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X5Y28", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y29": { + "bits": {}, + "grid_x": 16, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X5Y29", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y3": { + "bits": {}, + "grid_x": 16, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X5Y3", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y30": { + "bits": {}, + "grid_x": 16, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X5Y30", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y31": { + "bits": {}, + "grid_x": 16, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X5Y31", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y32": { + "bits": {}, + "grid_x": 16, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X5Y32", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y33": { + "bits": {}, + "grid_x": 16, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X5Y33", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y34": { + "bits": {}, + "grid_x": 16, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X5Y34", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y35": { + "bits": {}, + "grid_x": 16, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X5Y35", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y36": { + "bits": {}, + "grid_x": 16, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X5Y36", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y37": { + "bits": {}, + "grid_x": 16, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X5Y37", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y38": { + "bits": {}, + "grid_x": 16, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X5Y38", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y39": { + "bits": {}, + "grid_x": 16, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X5Y39", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y4": { + "bits": {}, + "grid_x": 16, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X5Y4", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y40": { + "bits": {}, + "grid_x": 16, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X5Y40", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y41": { + "bits": {}, + "grid_x": 16, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X5Y41", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y42": { + "bits": {}, + "grid_x": 16, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X5Y42", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y43": { + "bits": {}, + "grid_x": 16, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X5Y43", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y44": { + "bits": {}, + "grid_x": 16, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X5Y44", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y45": { + "bits": {}, + "grid_x": 16, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X5Y45", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y46": { + "bits": {}, + "grid_x": 16, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X5Y46", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y47": { + "bits": {}, + "grid_x": 16, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X5Y47", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y48": { + "bits": {}, + "grid_x": 16, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X5Y48", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y49": { + "bits": {}, + "grid_x": 16, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X5Y49", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y5": { + "bits": {}, + "grid_x": 16, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X5Y5", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X5Y50", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X5Y51", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X5Y52", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X5Y53", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X5Y54", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X5Y55", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X5Y56", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X5Y57", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X5Y58", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X5Y59", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y6": { + "bits": {}, + "grid_x": 16, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X5Y6", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X5Y60", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X5Y61", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X5Y62", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X5Y63", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X5Y64", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X5Y65", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X5Y66", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X5Y67", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X5Y68", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X5Y69", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y7": { + "bits": {}, + "grid_x": 16, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X5Y7", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X5Y70", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X5Y71", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X5Y72", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X5Y73", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X5Y74", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X5Y75", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X5Y76", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X5Y77", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X5Y78", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X5Y79", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y8": { + "bits": {}, + "grid_x": 16, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X5Y8", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X5Y80", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X5Y81", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X5Y82", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X5Y83", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X5Y84", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X5Y85", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X5Y86", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X5Y87", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X5Y88", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X5Y89", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y9": { + "bits": {}, + "grid_x": 16, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X5Y9", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X5Y90", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X5Y91", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X5Y92", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X5Y93", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X5Y94", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X5Y95", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X5Y96", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X5Y97", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X5Y98", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X5Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400280", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 16, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X5Y99", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X5Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y0": { + "bits": {}, + "grid_x": 22, + "grid_y": 207, + "segment": "SEG_CLBLM_R_X7Y0", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y1": { + "bits": {}, + "grid_x": 22, + "grid_y": 206, + "segment": "SEG_CLBLM_R_X7Y1", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y10": { + "bits": {}, + "grid_x": 22, + "grid_y": 197, + "segment": "SEG_CLBLM_R_X7Y10", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y100": { + "bits": {}, + "grid_x": 22, + "grid_y": 103, + "segment": "SEG_CLBLM_R_X7Y100", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y101": { + "bits": {}, + "grid_x": 22, + "grid_y": 102, + "segment": "SEG_CLBLM_R_X7Y101", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y102": { + "bits": {}, + "grid_x": 22, + "grid_y": 101, + "segment": "SEG_CLBLM_R_X7Y102", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y103": { + "bits": {}, + "grid_x": 22, + "grid_y": 100, + "segment": "SEG_CLBLM_R_X7Y103", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y104": { + "bits": {}, + "grid_x": 22, + "grid_y": 99, + "segment": "SEG_CLBLM_R_X7Y104", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y105": { + "bits": {}, + "grid_x": 22, + "grid_y": 98, + "segment": "SEG_CLBLM_R_X7Y105", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y106": { + "bits": {}, + "grid_x": 22, + "grid_y": 97, + "segment": "SEG_CLBLM_R_X7Y106", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y107": { + "bits": {}, + "grid_x": 22, + "grid_y": 96, + "segment": "SEG_CLBLM_R_X7Y107", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y108": { + "bits": {}, + "grid_x": 22, + "grid_y": 95, + "segment": "SEG_CLBLM_R_X7Y108", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y109": { + "bits": {}, + "grid_x": 22, + "grid_y": 94, + "segment": "SEG_CLBLM_R_X7Y109", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y11": { + "bits": {}, + "grid_x": 22, + "grid_y": 196, + "segment": "SEG_CLBLM_R_X7Y11", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y110": { + "bits": {}, + "grid_x": 22, + "grid_y": 93, + "segment": "SEG_CLBLM_R_X7Y110", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y111": { + "bits": {}, + "grid_x": 22, + "grid_y": 92, + "segment": "SEG_CLBLM_R_X7Y111", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y112": { + "bits": {}, + "grid_x": 22, + "grid_y": 91, + "segment": "SEG_CLBLM_R_X7Y112", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y113": { + "bits": {}, + "grid_x": 22, + "grid_y": 90, + "segment": "SEG_CLBLM_R_X7Y113", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y114": { + "bits": {}, + "grid_x": 22, + "grid_y": 89, + "segment": "SEG_CLBLM_R_X7Y114", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y115": { + "bits": {}, + "grid_x": 22, + "grid_y": 88, + "segment": "SEG_CLBLM_R_X7Y115", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y116": { + "bits": {}, + "grid_x": 22, + "grid_y": 87, + "segment": "SEG_CLBLM_R_X7Y116", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y117": { + "bits": {}, + "grid_x": 22, + "grid_y": 86, + "segment": "SEG_CLBLM_R_X7Y117", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y118": { + "bits": {}, + "grid_x": 22, + "grid_y": 85, + "segment": "SEG_CLBLM_R_X7Y118", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y119": { + "bits": {}, + "grid_x": 22, + "grid_y": 84, + "segment": "SEG_CLBLM_R_X7Y119", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y12": { + "bits": {}, + "grid_x": 22, + "grid_y": 195, + "segment": "SEG_CLBLM_R_X7Y12", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y120": { + "bits": {}, + "grid_x": 22, + "grid_y": 83, + "segment": "SEG_CLBLM_R_X7Y120", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y121": { + "bits": {}, + "grid_x": 22, + "grid_y": 82, + "segment": "SEG_CLBLM_R_X7Y121", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y122": { + "bits": {}, + "grid_x": 22, + "grid_y": 81, + "segment": "SEG_CLBLM_R_X7Y122", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y123": { + "bits": {}, + "grid_x": 22, + "grid_y": 80, + "segment": "SEG_CLBLM_R_X7Y123", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y124": { + "bits": {}, + "grid_x": 22, + "grid_y": 79, + "segment": "SEG_CLBLM_R_X7Y124", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y125": { + "bits": {}, + "grid_x": 22, + "grid_y": 77, + "segment": "SEG_CLBLM_R_X7Y125", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y126": { + "bits": {}, + "grid_x": 22, + "grid_y": 76, + "segment": "SEG_CLBLM_R_X7Y126", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y127": { + "bits": {}, + "grid_x": 22, + "grid_y": 75, + "segment": "SEG_CLBLM_R_X7Y127", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y128": { + "bits": {}, + "grid_x": 22, + "grid_y": 74, + "segment": "SEG_CLBLM_R_X7Y128", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y129": { + "bits": {}, + "grid_x": 22, + "grid_y": 73, + "segment": "SEG_CLBLM_R_X7Y129", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y13": { + "bits": {}, + "grid_x": 22, + "grid_y": 194, + "segment": "SEG_CLBLM_R_X7Y13", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y130": { + "bits": {}, + "grid_x": 22, + "grid_y": 72, + "segment": "SEG_CLBLM_R_X7Y130", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y131": { + "bits": {}, + "grid_x": 22, + "grid_y": 71, + "segment": "SEG_CLBLM_R_X7Y131", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y132": { + "bits": {}, + "grid_x": 22, + "grid_y": 70, + "segment": "SEG_CLBLM_R_X7Y132", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y133": { + "bits": {}, + "grid_x": 22, + "grid_y": 69, + "segment": "SEG_CLBLM_R_X7Y133", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y134": { + "bits": {}, + "grid_x": 22, + "grid_y": 68, + "segment": "SEG_CLBLM_R_X7Y134", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y135": { + "bits": {}, + "grid_x": 22, + "grid_y": 67, + "segment": "SEG_CLBLM_R_X7Y135", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y136": { + "bits": {}, + "grid_x": 22, + "grid_y": 66, + "segment": "SEG_CLBLM_R_X7Y136", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y137": { + "bits": {}, + "grid_x": 22, + "grid_y": 65, + "segment": "SEG_CLBLM_R_X7Y137", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y138": { + "bits": {}, + "grid_x": 22, + "grid_y": 64, + "segment": "SEG_CLBLM_R_X7Y138", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y139": { + "bits": {}, + "grid_x": 22, + "grid_y": 63, + "segment": "SEG_CLBLM_R_X7Y139", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y14": { + "bits": {}, + "grid_x": 22, + "grid_y": 193, + "segment": "SEG_CLBLM_R_X7Y14", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y140": { + "bits": {}, + "grid_x": 22, + "grid_y": 62, + "segment": "SEG_CLBLM_R_X7Y140", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y141": { + "bits": {}, + "grid_x": 22, + "grid_y": 61, + "segment": "SEG_CLBLM_R_X7Y141", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y142": { + "bits": {}, + "grid_x": 22, + "grid_y": 60, + "segment": "SEG_CLBLM_R_X7Y142", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y143": { + "bits": {}, + "grid_x": 22, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X7Y143", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y144": { + "bits": {}, + "grid_x": 22, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X7Y144", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y145": { + "bits": {}, + "grid_x": 22, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X7Y145", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y146": { + "bits": {}, + "grid_x": 22, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X7Y146", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y147": { + "bits": {}, + "grid_x": 22, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X7Y147", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y148": { + "bits": {}, + "grid_x": 22, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X7Y148", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y149": { + "bits": {}, + "grid_x": 22, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X7Y149", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y15": { + "bits": {}, + "grid_x": 22, + "grid_y": 192, + "segment": "SEG_CLBLM_R_X7Y15", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y150": { + "bits": {}, + "grid_x": 22, + "grid_y": 51, + "segment": "SEG_CLBLM_R_X7Y150", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y151": { + "bits": {}, + "grid_x": 22, + "grid_y": 50, + "segment": "SEG_CLBLM_R_X7Y151", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y152": { + "bits": {}, + "grid_x": 22, + "grid_y": 49, + "segment": "SEG_CLBLM_R_X7Y152", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y153": { + "bits": {}, + "grid_x": 22, + "grid_y": 48, + "segment": "SEG_CLBLM_R_X7Y153", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y154": { + "bits": {}, + "grid_x": 22, + "grid_y": 47, + "segment": "SEG_CLBLM_R_X7Y154", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y155": { + "bits": {}, + "grid_x": 22, + "grid_y": 46, + "segment": "SEG_CLBLM_R_X7Y155", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y156": { + "bits": {}, + "grid_x": 22, + "grid_y": 45, + "segment": "SEG_CLBLM_R_X7Y156", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y157": { + "bits": {}, + "grid_x": 22, + "grid_y": 44, + "segment": "SEG_CLBLM_R_X7Y157", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y158": { + "bits": {}, + "grid_x": 22, + "grid_y": 43, + "segment": "SEG_CLBLM_R_X7Y158", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y159": { + "bits": {}, + "grid_x": 22, + "grid_y": 42, + "segment": "SEG_CLBLM_R_X7Y159", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y16": { + "bits": {}, + "grid_x": 22, + "grid_y": 191, + "segment": "SEG_CLBLM_R_X7Y16", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y160": { + "bits": {}, + "grid_x": 22, + "grid_y": 41, + "segment": "SEG_CLBLM_R_X7Y160", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y161": { + "bits": {}, + "grid_x": 22, + "grid_y": 40, + "segment": "SEG_CLBLM_R_X7Y161", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y162": { + "bits": {}, + "grid_x": 22, + "grid_y": 39, + "segment": "SEG_CLBLM_R_X7Y162", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y163": { + "bits": {}, + "grid_x": 22, + "grid_y": 38, + "segment": "SEG_CLBLM_R_X7Y163", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y164": { + "bits": {}, + "grid_x": 22, + "grid_y": 37, + "segment": "SEG_CLBLM_R_X7Y164", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y165": { + "bits": {}, + "grid_x": 22, + "grid_y": 36, + "segment": "SEG_CLBLM_R_X7Y165", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y166": { + "bits": {}, + "grid_x": 22, + "grid_y": 35, + "segment": "SEG_CLBLM_R_X7Y166", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y167": { + "bits": {}, + "grid_x": 22, + "grid_y": 34, + "segment": "SEG_CLBLM_R_X7Y167", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y168": { + "bits": {}, + "grid_x": 22, + "grid_y": 33, + "segment": "SEG_CLBLM_R_X7Y168", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y169": { + "bits": {}, + "grid_x": 22, + "grid_y": 32, + "segment": "SEG_CLBLM_R_X7Y169", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y17": { + "bits": {}, + "grid_x": 22, + "grid_y": 190, + "segment": "SEG_CLBLM_R_X7Y17", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y170": { + "bits": {}, + "grid_x": 22, + "grid_y": 31, + "segment": "SEG_CLBLM_R_X7Y170", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y171": { + "bits": {}, + "grid_x": 22, + "grid_y": 30, + "segment": "SEG_CLBLM_R_X7Y171", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y172": { + "bits": {}, + "grid_x": 22, + "grid_y": 29, + "segment": "SEG_CLBLM_R_X7Y172", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y173": { + "bits": {}, + "grid_x": 22, + "grid_y": 28, + "segment": "SEG_CLBLM_R_X7Y173", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y174": { + "bits": {}, + "grid_x": 22, + "grid_y": 27, + "segment": "SEG_CLBLM_R_X7Y174", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y175": { + "bits": {}, + "grid_x": 22, + "grid_y": 25, + "segment": "SEG_CLBLM_R_X7Y175", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y176": { + "bits": {}, + "grid_x": 22, + "grid_y": 24, + "segment": "SEG_CLBLM_R_X7Y176", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y177": { + "bits": {}, + "grid_x": 22, + "grid_y": 23, + "segment": "SEG_CLBLM_R_X7Y177", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y178": { + "bits": {}, + "grid_x": 22, + "grid_y": 22, + "segment": "SEG_CLBLM_R_X7Y178", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y179": { + "bits": {}, + "grid_x": 22, + "grid_y": 21, + "segment": "SEG_CLBLM_R_X7Y179", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y18": { + "bits": {}, + "grid_x": 22, + "grid_y": 189, + "segment": "SEG_CLBLM_R_X7Y18", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y180": { + "bits": {}, + "grid_x": 22, + "grid_y": 20, + "segment": "SEG_CLBLM_R_X7Y180", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y181": { + "bits": {}, + "grid_x": 22, + "grid_y": 19, + "segment": "SEG_CLBLM_R_X7Y181", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y182": { + "bits": {}, + "grid_x": 22, + "grid_y": 18, + "segment": "SEG_CLBLM_R_X7Y182", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y183": { + "bits": {}, + "grid_x": 22, + "grid_y": 17, + "segment": "SEG_CLBLM_R_X7Y183", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y184": { + "bits": {}, + "grid_x": 22, + "grid_y": 16, + "segment": "SEG_CLBLM_R_X7Y184", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y185": { + "bits": {}, + "grid_x": 22, + "grid_y": 15, + "segment": "SEG_CLBLM_R_X7Y185", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y186": { + "bits": {}, + "grid_x": 22, + "grid_y": 14, + "segment": "SEG_CLBLM_R_X7Y186", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y187": { + "bits": {}, + "grid_x": 22, + "grid_y": 13, + "segment": "SEG_CLBLM_R_X7Y187", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y188": { + "bits": {}, + "grid_x": 22, + "grid_y": 12, + "segment": "SEG_CLBLM_R_X7Y188", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y189": { + "bits": {}, + "grid_x": 22, + "grid_y": 11, + "segment": "SEG_CLBLM_R_X7Y189", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y19": { + "bits": {}, + "grid_x": 22, + "grid_y": 188, + "segment": "SEG_CLBLM_R_X7Y19", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y190": { + "bits": {}, + "grid_x": 22, + "grid_y": 10, + "segment": "SEG_CLBLM_R_X7Y190", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y191": { + "bits": {}, + "grid_x": 22, + "grid_y": 9, + "segment": "SEG_CLBLM_R_X7Y191", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y192": { + "bits": {}, + "grid_x": 22, + "grid_y": 8, + "segment": "SEG_CLBLM_R_X7Y192", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y193": { + "bits": {}, + "grid_x": 22, + "grid_y": 7, + "segment": "SEG_CLBLM_R_X7Y193", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y194": { + "bits": {}, + "grid_x": 22, + "grid_y": 6, + "segment": "SEG_CLBLM_R_X7Y194", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y195": { + "bits": {}, + "grid_x": 22, + "grid_y": 5, + "segment": "SEG_CLBLM_R_X7Y195", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y196": { + "bits": {}, + "grid_x": 22, + "grid_y": 4, + "segment": "SEG_CLBLM_R_X7Y196", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y197": { + "bits": {}, + "grid_x": 22, + "grid_y": 3, + "segment": "SEG_CLBLM_R_X7Y197", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y198": { + "bits": {}, + "grid_x": 22, + "grid_y": 2, + "segment": "SEG_CLBLM_R_X7Y198", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y199": { + "bits": {}, + "grid_x": 22, + "grid_y": 1, + "segment": "SEG_CLBLM_R_X7Y199", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y2": { + "bits": {}, + "grid_x": 22, + "grid_y": 205, + "segment": "SEG_CLBLM_R_X7Y2", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y20": { + "bits": {}, + "grid_x": 22, + "grid_y": 187, + "segment": "SEG_CLBLM_R_X7Y20", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y21": { + "bits": {}, + "grid_x": 22, + "grid_y": 186, + "segment": "SEG_CLBLM_R_X7Y21", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y22": { + "bits": {}, + "grid_x": 22, + "grid_y": 185, + "segment": "SEG_CLBLM_R_X7Y22", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y23": { + "bits": {}, + "grid_x": 22, + "grid_y": 184, + "segment": "SEG_CLBLM_R_X7Y23", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y24": { + "bits": {}, + "grid_x": 22, + "grid_y": 183, + "segment": "SEG_CLBLM_R_X7Y24", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y25": { + "bits": {}, + "grid_x": 22, + "grid_y": 181, + "segment": "SEG_CLBLM_R_X7Y25", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y26": { + "bits": {}, + "grid_x": 22, + "grid_y": 180, + "segment": "SEG_CLBLM_R_X7Y26", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y27": { + "bits": {}, + "grid_x": 22, + "grid_y": 179, + "segment": "SEG_CLBLM_R_X7Y27", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y28": { + "bits": {}, + "grid_x": 22, + "grid_y": 178, + "segment": "SEG_CLBLM_R_X7Y28", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y29": { + "bits": {}, + "grid_x": 22, + "grid_y": 177, + "segment": "SEG_CLBLM_R_X7Y29", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y3": { + "bits": {}, + "grid_x": 22, + "grid_y": 204, + "segment": "SEG_CLBLM_R_X7Y3", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y30": { + "bits": {}, + "grid_x": 22, + "grid_y": 176, + "segment": "SEG_CLBLM_R_X7Y30", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y31": { + "bits": {}, + "grid_x": 22, + "grid_y": 175, + "segment": "SEG_CLBLM_R_X7Y31", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y32": { + "bits": {}, + "grid_x": 22, + "grid_y": 174, + "segment": "SEG_CLBLM_R_X7Y32", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y33": { + "bits": {}, + "grid_x": 22, + "grid_y": 173, + "segment": "SEG_CLBLM_R_X7Y33", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y34": { + "bits": {}, + "grid_x": 22, + "grid_y": 172, + "segment": "SEG_CLBLM_R_X7Y34", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y35": { + "bits": {}, + "grid_x": 22, + "grid_y": 171, + "segment": "SEG_CLBLM_R_X7Y35", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y36": { + "bits": {}, + "grid_x": 22, + "grid_y": 170, + "segment": "SEG_CLBLM_R_X7Y36", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y37": { + "bits": {}, + "grid_x": 22, + "grid_y": 169, + "segment": "SEG_CLBLM_R_X7Y37", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y38": { + "bits": {}, + "grid_x": 22, + "grid_y": 168, + "segment": "SEG_CLBLM_R_X7Y38", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y39": { + "bits": {}, + "grid_x": 22, + "grid_y": 167, + "segment": "SEG_CLBLM_R_X7Y39", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y4": { + "bits": {}, + "grid_x": 22, + "grid_y": 203, + "segment": "SEG_CLBLM_R_X7Y4", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y40": { + "bits": {}, + "grid_x": 22, + "grid_y": 166, + "segment": "SEG_CLBLM_R_X7Y40", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y41": { + "bits": {}, + "grid_x": 22, + "grid_y": 165, + "segment": "SEG_CLBLM_R_X7Y41", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y42": { + "bits": {}, + "grid_x": 22, + "grid_y": 164, + "segment": "SEG_CLBLM_R_X7Y42", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y43": { + "bits": {}, + "grid_x": 22, + "grid_y": 163, + "segment": "SEG_CLBLM_R_X7Y43", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y44": { + "bits": {}, + "grid_x": 22, + "grid_y": 162, + "segment": "SEG_CLBLM_R_X7Y44", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y45": { + "bits": {}, + "grid_x": 22, + "grid_y": 161, + "segment": "SEG_CLBLM_R_X7Y45", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y46": { + "bits": {}, + "grid_x": 22, + "grid_y": 160, + "segment": "SEG_CLBLM_R_X7Y46", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y47": { + "bits": {}, + "grid_x": 22, + "grid_y": 159, + "segment": "SEG_CLBLM_R_X7Y47", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y48": { + "bits": {}, + "grid_x": 22, + "grid_y": 158, + "segment": "SEG_CLBLM_R_X7Y48", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y49": { + "bits": {}, + "grid_x": 22, + "grid_y": 157, + "segment": "SEG_CLBLM_R_X7Y49", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y5": { + "bits": {}, + "grid_x": 22, + "grid_y": 202, + "segment": "SEG_CLBLM_R_X7Y5", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 155, + "segment": "SEG_CLBLM_R_X7Y50", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 154, + "segment": "SEG_CLBLM_R_X7Y51", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 153, + "segment": "SEG_CLBLM_R_X7Y52", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 152, + "segment": "SEG_CLBLM_R_X7Y53", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 151, + "segment": "SEG_CLBLM_R_X7Y54", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 150, + "segment": "SEG_CLBLM_R_X7Y55", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 149, + "segment": "SEG_CLBLM_R_X7Y56", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 148, + "segment": "SEG_CLBLM_R_X7Y57", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 147, + "segment": "SEG_CLBLM_R_X7Y58", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 146, + "segment": "SEG_CLBLM_R_X7Y59", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y6": { + "bits": {}, + "grid_x": 22, + "grid_y": 201, + "segment": "SEG_CLBLM_R_X7Y6", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 145, + "segment": "SEG_CLBLM_R_X7Y60", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 144, + "segment": "SEG_CLBLM_R_X7Y61", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 143, + "segment": "SEG_CLBLM_R_X7Y62", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 142, + "segment": "SEG_CLBLM_R_X7Y63", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 141, + "segment": "SEG_CLBLM_R_X7Y64", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 140, + "segment": "SEG_CLBLM_R_X7Y65", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 139, + "segment": "SEG_CLBLM_R_X7Y66", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 138, + "segment": "SEG_CLBLM_R_X7Y67", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 137, + "segment": "SEG_CLBLM_R_X7Y68", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 136, + "segment": "SEG_CLBLM_R_X7Y69", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y7": { + "bits": {}, + "grid_x": 22, + "grid_y": 200, + "segment": "SEG_CLBLM_R_X7Y7", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 135, + "segment": "SEG_CLBLM_R_X7Y70", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 134, + "segment": "SEG_CLBLM_R_X7Y71", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 133, + "segment": "SEG_CLBLM_R_X7Y72", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 132, + "segment": "SEG_CLBLM_R_X7Y73", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 131, + "segment": "SEG_CLBLM_R_X7Y74", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 129, + "segment": "SEG_CLBLM_R_X7Y75", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 128, + "segment": "SEG_CLBLM_R_X7Y76", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 127, + "segment": "SEG_CLBLM_R_X7Y77", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 126, + "segment": "SEG_CLBLM_R_X7Y78", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 125, + "segment": "SEG_CLBLM_R_X7Y79", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y8": { + "bits": {}, + "grid_x": 22, + "grid_y": 199, + "segment": "SEG_CLBLM_R_X7Y8", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 124, + "segment": "SEG_CLBLM_R_X7Y80", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 123, + "segment": "SEG_CLBLM_R_X7Y81", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 122, + "segment": "SEG_CLBLM_R_X7Y82", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 121, + "segment": "SEG_CLBLM_R_X7Y83", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 120, + "segment": "SEG_CLBLM_R_X7Y84", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 119, + "segment": "SEG_CLBLM_R_X7Y85", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 118, + "segment": "SEG_CLBLM_R_X7Y86", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 117, + "segment": "SEG_CLBLM_R_X7Y87", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 116, + "segment": "SEG_CLBLM_R_X7Y88", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 115, + "segment": "SEG_CLBLM_R_X7Y89", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y9": { + "bits": {}, + "grid_x": 22, + "grid_y": 198, + "segment": "SEG_CLBLM_R_X7Y9", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 114, + "segment": "SEG_CLBLM_R_X7Y90", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 113, + "segment": "SEG_CLBLM_R_X7Y91", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 112, + "segment": "SEG_CLBLM_R_X7Y92", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 111, + "segment": "SEG_CLBLM_R_X7Y93", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 110, + "segment": "SEG_CLBLM_R_X7Y94", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 109, + "segment": "SEG_CLBLM_R_X7Y95", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 108, + "segment": "SEG_CLBLM_R_X7Y96", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 107, + "segment": "SEG_CLBLM_R_X7Y97", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 106, + "segment": "SEG_CLBLM_R_X7Y98", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X7Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400380", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 22, + "grid_y": 105, + "segment": "SEG_CLBLM_R_X7Y99", + "segment_type": "clblm_r", + "sites": { + "TIEOFF_X7Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y0": { + "bits": {}, + "grid_x": 26, + "grid_y": 207, + "segment": "SEG_DSP0_R_X9Y0", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y0": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y1": { + "bits": {}, + "grid_x": 26, + "grid_y": 206, + "segment": "SEG_DSP1_R_X9Y0", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y1": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y10": { + "bits": {}, + "grid_x": 26, + "grid_y": 197, + "segment": "SEG_DSP0_R_X9Y10", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y10": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y100": { + "bits": {}, + "grid_x": 26, + "grid_y": 103, + "segment": "SEG_DSP0_R_X9Y100", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y100": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y101": { + "bits": {}, + "grid_x": 26, + "grid_y": 102, + "segment": "SEG_DSP1_R_X9Y100", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y101": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y102": { + "bits": {}, + "grid_x": 26, + "grid_y": 101, + "segment": "SEG_DSP2_R_X9Y100", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y102": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y103": { + "bits": {}, + "grid_x": 26, + "grid_y": 100, + "segment": "SEG_DSP3_R_X9Y100", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y103": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y104": { + "bits": {}, + "grid_x": 26, + "grid_y": 99, + "segment": "SEG_DSP4_R_X9Y100", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y104": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y105": { + "bits": {}, + "grid_x": 26, + "grid_y": 98, + "segment": "SEG_DSP0_R_X9Y105", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y105": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y106": { + "bits": {}, + "grid_x": 26, + "grid_y": 97, + "segment": "SEG_DSP1_R_X9Y105", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y106": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y107": { + "bits": {}, + "grid_x": 26, + "grid_y": 96, + "segment": "SEG_DSP2_R_X9Y105", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y107": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y108": { + "bits": {}, + "grid_x": 26, + "grid_y": 95, + "segment": "SEG_DSP3_R_X9Y105", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y108": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y109": { + "bits": {}, + "grid_x": 26, + "grid_y": 94, + "segment": "SEG_DSP4_R_X9Y105", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y109": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y11": { + "bits": {}, + "grid_x": 26, + "grid_y": 196, + "segment": "SEG_DSP1_R_X9Y10", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y11": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y110": { + "bits": {}, + "grid_x": 26, + "grid_y": 93, + "segment": "SEG_DSP0_R_X9Y110", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y110": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y111": { + "bits": {}, + "grid_x": 26, + "grid_y": 92, + "segment": "SEG_DSP1_R_X9Y110", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y111": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y112": { + "bits": {}, + "grid_x": 26, + "grid_y": 91, + "segment": "SEG_DSP2_R_X9Y110", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y112": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y113": { + "bits": {}, + "grid_x": 26, + "grid_y": 90, + "segment": "SEG_DSP3_R_X9Y110", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y113": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y114": { + "bits": {}, + "grid_x": 26, + "grid_y": 89, + "segment": "SEG_DSP4_R_X9Y110", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y114": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y115": { + "bits": {}, + "grid_x": 26, + "grid_y": 88, + "segment": "SEG_DSP0_R_X9Y115", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y115": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y116": { + "bits": {}, + "grid_x": 26, + "grid_y": 87, + "segment": "SEG_DSP1_R_X9Y115", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y116": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y117": { + "bits": {}, + "grid_x": 26, + "grid_y": 86, + "segment": "SEG_DSP2_R_X9Y115", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y117": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y118": { + "bits": {}, + "grid_x": 26, + "grid_y": 85, + "segment": "SEG_DSP3_R_X9Y115", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y118": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y119": { + "bits": {}, + "grid_x": 26, + "grid_y": 84, + "segment": "SEG_DSP4_R_X9Y115", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y119": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y12": { + "bits": {}, + "grid_x": 26, + "grid_y": 195, + "segment": "SEG_DSP2_R_X9Y10", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y12": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y120": { + "bits": {}, + "grid_x": 26, + "grid_y": 83, + "segment": "SEG_DSP0_R_X9Y120", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y120": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y121": { + "bits": {}, + "grid_x": 26, + "grid_y": 82, + "segment": "SEG_DSP1_R_X9Y120", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y121": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y122": { + "bits": {}, + "grid_x": 26, + "grid_y": 81, + "segment": "SEG_DSP2_R_X9Y120", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y122": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y123": { + "bits": {}, + "grid_x": 26, + "grid_y": 80, + "segment": "SEG_DSP3_R_X9Y120", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y123": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y124": { + "bits": {}, + "grid_x": 26, + "grid_y": 79, + "segment": "SEG_DSP4_R_X9Y120", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y124": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y125": { + "bits": {}, + "grid_x": 26, + "grid_y": 77, + "segment": "SEG_DSP0_R_X9Y125", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y125": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y126": { + "bits": {}, + "grid_x": 26, + "grid_y": 76, + "segment": "SEG_DSP1_R_X9Y125", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y126": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y127": { + "bits": {}, + "grid_x": 26, + "grid_y": 75, + "segment": "SEG_DSP2_R_X9Y125", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y127": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y128": { + "bits": {}, + "grid_x": 26, + "grid_y": 74, + "segment": "SEG_DSP3_R_X9Y125", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y128": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y129": { + "bits": {}, + "grid_x": 26, + "grid_y": 73, + "segment": "SEG_DSP4_R_X9Y125", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y129": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y13": { + "bits": {}, + "grid_x": 26, + "grid_y": 194, + "segment": "SEG_DSP3_R_X9Y10", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y13": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y130": { + "bits": {}, + "grid_x": 26, + "grid_y": 72, + "segment": "SEG_DSP0_R_X9Y130", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y130": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y131": { + "bits": {}, + "grid_x": 26, + "grid_y": 71, + "segment": "SEG_DSP1_R_X9Y130", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y131": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y132": { + "bits": {}, + "grid_x": 26, + "grid_y": 70, + "segment": "SEG_DSP2_R_X9Y130", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y132": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y133": { + "bits": {}, + "grid_x": 26, + "grid_y": 69, + "segment": "SEG_DSP3_R_X9Y130", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y133": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y134": { + "bits": {}, + "grid_x": 26, + "grid_y": 68, + "segment": "SEG_DSP4_R_X9Y130", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y134": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y135": { + "bits": {}, + "grid_x": 26, + "grid_y": 67, + "segment": "SEG_DSP0_R_X9Y135", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y135": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y136": { + "bits": {}, + "grid_x": 26, + "grid_y": 66, + "segment": "SEG_DSP1_R_X9Y135", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y136": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y137": { + "bits": {}, + "grid_x": 26, + "grid_y": 65, + "segment": "SEG_DSP2_R_X9Y135", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y137": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y138": { + "bits": {}, + "grid_x": 26, + "grid_y": 64, + "segment": "SEG_DSP3_R_X9Y135", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y138": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y139": { + "bits": {}, + "grid_x": 26, + "grid_y": 63, + "segment": "SEG_DSP4_R_X9Y135", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y139": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y14": { + "bits": {}, + "grid_x": 26, + "grid_y": 193, + "segment": "SEG_DSP4_R_X9Y10", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y14": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y140": { + "bits": {}, + "grid_x": 26, + "grid_y": 62, + "segment": "SEG_DSP0_R_X9Y140", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y140": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y141": { + "bits": {}, + "grid_x": 26, + "grid_y": 61, + "segment": "SEG_DSP1_R_X9Y140", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y141": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y142": { + "bits": {}, + "grid_x": 26, + "grid_y": 60, + "segment": "SEG_DSP2_R_X9Y140", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y142": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y143": { + "bits": {}, + "grid_x": 26, + "grid_y": 59, + "segment": "SEG_DSP3_R_X9Y140", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y143": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y144": { + "bits": {}, + "grid_x": 26, + "grid_y": 58, + "segment": "SEG_DSP4_R_X9Y140", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y144": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y145": { + "bits": {}, + "grid_x": 26, + "grid_y": 57, + "segment": "SEG_DSP0_R_X9Y145", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y145": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y146": { + "bits": {}, + "grid_x": 26, + "grid_y": 56, + "segment": "SEG_DSP1_R_X9Y145", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y146": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y147": { + "bits": {}, + "grid_x": 26, + "grid_y": 55, + "segment": "SEG_DSP2_R_X9Y145", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y147": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y148": { + "bits": {}, + "grid_x": 26, + "grid_y": 54, + "segment": "SEG_DSP3_R_X9Y145", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y148": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y149": { + "bits": {}, + "grid_x": 26, + "grid_y": 53, + "segment": "SEG_DSP4_R_X9Y145", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y149": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y15": { + "bits": {}, + "grid_x": 26, + "grid_y": 192, + "segment": "SEG_DSP0_R_X9Y15", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y15": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y150": { + "bits": {}, + "grid_x": 26, + "grid_y": 51, + "segment": "SEG_DSP0_R_X9Y150", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y150": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y151": { + "bits": {}, + "grid_x": 26, + "grid_y": 50, + "segment": "SEG_DSP1_R_X9Y150", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y151": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y152": { + "bits": {}, + "grid_x": 26, + "grid_y": 49, + "segment": "SEG_DSP2_R_X9Y150", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y152": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y153": { + "bits": {}, + "grid_x": 26, + "grid_y": 48, + "segment": "SEG_DSP3_R_X9Y150", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y153": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y154": { + "bits": {}, + "grid_x": 26, + "grid_y": 47, + "segment": "SEG_DSP4_R_X9Y150", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y154": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y155": { + "bits": {}, + "grid_x": 26, + "grid_y": 46, + "segment": "SEG_DSP0_R_X9Y155", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y155": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y156": { + "bits": {}, + "grid_x": 26, + "grid_y": 45, + "segment": "SEG_DSP1_R_X9Y155", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y156": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y157": { + "bits": {}, + "grid_x": 26, + "grid_y": 44, + "segment": "SEG_DSP2_R_X9Y155", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y157": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y158": { + "bits": {}, + "grid_x": 26, + "grid_y": 43, + "segment": "SEG_DSP3_R_X9Y155", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y158": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y159": { + "bits": {}, + "grid_x": 26, + "grid_y": 42, + "segment": "SEG_DSP4_R_X9Y155", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y159": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y16": { + "bits": {}, + "grid_x": 26, + "grid_y": 191, + "segment": "SEG_DSP1_R_X9Y15", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y16": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y160": { + "bits": {}, + "grid_x": 26, + "grid_y": 41, + "segment": "SEG_DSP0_R_X9Y160", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y160": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y161": { + "bits": {}, + "grid_x": 26, + "grid_y": 40, + "segment": "SEG_DSP1_R_X9Y160", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y161": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y162": { + "bits": {}, + "grid_x": 26, + "grid_y": 39, + "segment": "SEG_DSP2_R_X9Y160", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y162": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y163": { + "bits": {}, + "grid_x": 26, + "grid_y": 38, + "segment": "SEG_DSP3_R_X9Y160", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y163": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y164": { + "bits": {}, + "grid_x": 26, + "grid_y": 37, + "segment": "SEG_DSP4_R_X9Y160", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y164": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y165": { + "bits": {}, + "grid_x": 26, + "grid_y": 36, + "segment": "SEG_DSP0_R_X9Y165", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y165": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y166": { + "bits": {}, + "grid_x": 26, + "grid_y": 35, + "segment": "SEG_DSP1_R_X9Y165", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y166": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y167": { + "bits": {}, + "grid_x": 26, + "grid_y": 34, + "segment": "SEG_DSP2_R_X9Y165", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y167": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y168": { + "bits": {}, + "grid_x": 26, + "grid_y": 33, + "segment": "SEG_DSP3_R_X9Y165", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y168": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y169": { + "bits": {}, + "grid_x": 26, + "grid_y": 32, + "segment": "SEG_DSP4_R_X9Y165", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y169": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y17": { + "bits": {}, + "grid_x": 26, + "grid_y": 190, + "segment": "SEG_DSP2_R_X9Y15", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y17": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y170": { + "bits": {}, + "grid_x": 26, + "grid_y": 31, + "segment": "SEG_DSP0_R_X9Y170", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y170": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y171": { + "bits": {}, + "grid_x": 26, + "grid_y": 30, + "segment": "SEG_DSP1_R_X9Y170", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y171": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y172": { + "bits": {}, + "grid_x": 26, + "grid_y": 29, + "segment": "SEG_DSP2_R_X9Y170", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y172": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y173": { + "bits": {}, + "grid_x": 26, + "grid_y": 28, + "segment": "SEG_DSP3_R_X9Y170", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y173": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y174": { + "bits": {}, + "grid_x": 26, + "grid_y": 27, + "segment": "SEG_DSP4_R_X9Y170", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y174": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y175": { + "bits": {}, + "grid_x": 26, + "grid_y": 25, + "segment": "SEG_DSP0_R_X9Y175", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y175": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y176": { + "bits": {}, + "grid_x": 26, + "grid_y": 24, + "segment": "SEG_DSP1_R_X9Y175", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y176": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y177": { + "bits": {}, + "grid_x": 26, + "grid_y": 23, + "segment": "SEG_DSP2_R_X9Y175", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y177": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y178": { + "bits": {}, + "grid_x": 26, + "grid_y": 22, + "segment": "SEG_DSP3_R_X9Y175", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y178": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y179": { + "bits": {}, + "grid_x": 26, + "grid_y": 21, + "segment": "SEG_DSP4_R_X9Y175", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y179": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y18": { + "bits": {}, + "grid_x": 26, + "grid_y": 189, + "segment": "SEG_DSP3_R_X9Y15", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y18": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y180": { + "bits": {}, + "grid_x": 26, + "grid_y": 20, + "segment": "SEG_DSP0_R_X9Y180", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y180": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y181": { + "bits": {}, + "grid_x": 26, + "grid_y": 19, + "segment": "SEG_DSP1_R_X9Y180", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y181": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y182": { + "bits": {}, + "grid_x": 26, + "grid_y": 18, + "segment": "SEG_DSP2_R_X9Y180", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y182": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y183": { + "bits": {}, + "grid_x": 26, + "grid_y": 17, + "segment": "SEG_DSP3_R_X9Y180", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y183": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y184": { + "bits": {}, + "grid_x": 26, + "grid_y": 16, + "segment": "SEG_DSP4_R_X9Y180", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y184": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y185": { + "bits": {}, + "grid_x": 26, + "grid_y": 15, + "segment": "SEG_DSP0_R_X9Y185", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y185": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y186": { + "bits": {}, + "grid_x": 26, + "grid_y": 14, + "segment": "SEG_DSP1_R_X9Y185", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y186": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y187": { + "bits": {}, + "grid_x": 26, + "grid_y": 13, + "segment": "SEG_DSP2_R_X9Y185", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y187": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y188": { + "bits": {}, + "grid_x": 26, + "grid_y": 12, + "segment": "SEG_DSP3_R_X9Y185", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y188": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y189": { + "bits": {}, + "grid_x": 26, + "grid_y": 11, + "segment": "SEG_DSP4_R_X9Y185", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y189": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y19": { + "bits": {}, + "grid_x": 26, + "grid_y": 188, + "segment": "SEG_DSP4_R_X9Y15", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y19": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y190": { + "bits": {}, + "grid_x": 26, + "grid_y": 10, + "segment": "SEG_DSP0_R_X9Y190", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y190": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y191": { + "bits": {}, + "grid_x": 26, + "grid_y": 9, + "segment": "SEG_DSP1_R_X9Y190", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y191": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y192": { + "bits": {}, + "grid_x": 26, + "grid_y": 8, + "segment": "SEG_DSP2_R_X9Y190", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y192": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y193": { + "bits": {}, + "grid_x": 26, + "grid_y": 7, + "segment": "SEG_DSP3_R_X9Y190", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y193": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y194": { + "bits": {}, + "grid_x": 26, + "grid_y": 6, + "segment": "SEG_DSP4_R_X9Y190", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y194": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y195": { + "bits": {}, + "grid_x": 26, + "grid_y": 5, + "segment": "SEG_DSP0_R_X9Y195", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y195": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y196": { + "bits": {}, + "grid_x": 26, + "grid_y": 4, + "segment": "SEG_DSP1_R_X9Y195", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y196": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y197": { + "bits": {}, + "grid_x": 26, + "grid_y": 3, + "segment": "SEG_DSP2_R_X9Y195", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y197": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y198": { + "bits": {}, + "grid_x": 26, + "grid_y": 2, + "segment": "SEG_DSP3_R_X9Y195", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y198": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y199": { + "bits": {}, + "grid_x": 26, + "grid_y": 1, + "segment": "SEG_DSP4_R_X9Y195", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y199": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y2": { + "bits": {}, + "grid_x": 26, + "grid_y": 205, + "segment": "SEG_DSP2_R_X9Y0", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y2": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y20": { + "bits": {}, + "grid_x": 26, + "grid_y": 187, + "segment": "SEG_DSP0_R_X9Y20", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y20": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y21": { + "bits": {}, + "grid_x": 26, + "grid_y": 186, + "segment": "SEG_DSP1_R_X9Y20", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y21": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y22": { + "bits": {}, + "grid_x": 26, + "grid_y": 185, + "segment": "SEG_DSP2_R_X9Y20", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y22": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y23": { + "bits": {}, + "grid_x": 26, + "grid_y": 184, + "segment": "SEG_DSP3_R_X9Y20", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y23": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y24": { + "bits": {}, + "grid_x": 26, + "grid_y": 183, + "segment": "SEG_DSP4_R_X9Y20", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y24": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y25": { + "bits": {}, + "grid_x": 26, + "grid_y": 181, + "segment": "SEG_DSP0_R_X9Y25", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y25": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y26": { + "bits": {}, + "grid_x": 26, + "grid_y": 180, + "segment": "SEG_DSP1_R_X9Y25", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y26": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y27": { + "bits": {}, + "grid_x": 26, + "grid_y": 179, + "segment": "SEG_DSP2_R_X9Y25", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y27": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y28": { + "bits": {}, + "grid_x": 26, + "grid_y": 178, + "segment": "SEG_DSP3_R_X9Y25", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y28": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y29": { + "bits": {}, + "grid_x": 26, + "grid_y": 177, + "segment": "SEG_DSP4_R_X9Y25", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y29": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y3": { + "bits": {}, + "grid_x": 26, + "grid_y": 204, + "segment": "SEG_DSP3_R_X9Y0", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y3": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y30": { + "bits": {}, + "grid_x": 26, + "grid_y": 176, + "segment": "SEG_DSP0_R_X9Y30", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y30": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y31": { + "bits": {}, + "grid_x": 26, + "grid_y": 175, + "segment": "SEG_DSP1_R_X9Y30", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y31": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y32": { + "bits": {}, + "grid_x": 26, + "grid_y": 174, + "segment": "SEG_DSP2_R_X9Y30", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y32": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y33": { + "bits": {}, + "grid_x": 26, + "grid_y": 173, + "segment": "SEG_DSP3_R_X9Y30", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y33": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y34": { + "bits": {}, + "grid_x": 26, + "grid_y": 172, + "segment": "SEG_DSP4_R_X9Y30", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y34": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y35": { + "bits": {}, + "grid_x": 26, + "grid_y": 171, + "segment": "SEG_DSP0_R_X9Y35", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y35": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y36": { + "bits": {}, + "grid_x": 26, + "grid_y": 170, + "segment": "SEG_DSP1_R_X9Y35", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y36": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y37": { + "bits": {}, + "grid_x": 26, + "grid_y": 169, + "segment": "SEG_DSP2_R_X9Y35", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y37": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y38": { + "bits": {}, + "grid_x": 26, + "grid_y": 168, + "segment": "SEG_DSP3_R_X9Y35", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y38": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y39": { + "bits": {}, + "grid_x": 26, + "grid_y": 167, + "segment": "SEG_DSP4_R_X9Y35", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y39": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y4": { + "bits": {}, + "grid_x": 26, + "grid_y": 203, + "segment": "SEG_DSP4_R_X9Y0", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y4": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y40": { + "bits": {}, + "grid_x": 26, + "grid_y": 166, + "segment": "SEG_DSP0_R_X9Y40", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y40": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y41": { + "bits": {}, + "grid_x": 26, + "grid_y": 165, + "segment": "SEG_DSP1_R_X9Y40", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y41": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y42": { + "bits": {}, + "grid_x": 26, + "grid_y": 164, + "segment": "SEG_DSP2_R_X9Y40", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y42": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y43": { + "bits": {}, + "grid_x": 26, + "grid_y": 163, + "segment": "SEG_DSP3_R_X9Y40", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y43": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y44": { + "bits": {}, + "grid_x": 26, + "grid_y": 162, + "segment": "SEG_DSP4_R_X9Y40", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y44": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y45": { + "bits": {}, + "grid_x": 26, + "grid_y": 161, + "segment": "SEG_DSP0_R_X9Y45", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y45": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y46": { + "bits": {}, + "grid_x": 26, + "grid_y": 160, + "segment": "SEG_DSP1_R_X9Y45", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y46": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y47": { + "bits": {}, + "grid_x": 26, + "grid_y": 159, + "segment": "SEG_DSP2_R_X9Y45", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y47": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y48": { + "bits": {}, + "grid_x": 26, + "grid_y": 158, + "segment": "SEG_DSP3_R_X9Y45", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y48": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y49": { + "bits": {}, + "grid_x": 26, + "grid_y": 157, + "segment": "SEG_DSP4_R_X9Y45", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y49": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y5": { + "bits": {}, + "grid_x": 26, + "grid_y": 202, + "segment": "SEG_DSP0_R_X9Y5", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y5": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y50": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 0, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 155, + "segment": "SEG_DSP0_R_X9Y50", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y50": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y51": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 2, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 154, + "segment": "SEG_DSP1_R_X9Y50", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y51": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y52": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 4, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 153, + "segment": "SEG_DSP2_R_X9Y50", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y52": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y53": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 6, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 152, + "segment": "SEG_DSP3_R_X9Y50", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y53": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y54": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 8, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 151, + "segment": "SEG_DSP4_R_X9Y50", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y54": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y55": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 10, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 150, + "segment": "SEG_DSP0_R_X9Y55", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y55": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y56": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 12, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 149, + "segment": "SEG_DSP1_R_X9Y55", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y56": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y57": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 14, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 148, + "segment": "SEG_DSP2_R_X9Y55", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y57": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y58": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 16, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 147, + "segment": "SEG_DSP3_R_X9Y55", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y58": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y59": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 18, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 146, + "segment": "SEG_DSP4_R_X9Y55", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y59": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y6": { + "bits": {}, + "grid_x": 26, + "grid_y": 201, + "segment": "SEG_DSP1_R_X9Y5", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y6": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y60": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 20, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 145, + "segment": "SEG_DSP0_R_X9Y60", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y60": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y61": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 22, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 144, + "segment": "SEG_DSP1_R_X9Y60", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y61": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y62": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 24, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 143, + "segment": "SEG_DSP2_R_X9Y60", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y62": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y63": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 26, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 142, + "segment": "SEG_DSP3_R_X9Y60", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y63": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y64": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 28, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 141, + "segment": "SEG_DSP4_R_X9Y60", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y64": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y65": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 30, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 140, + "segment": "SEG_DSP0_R_X9Y65", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y65": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y66": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 32, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 139, + "segment": "SEG_DSP1_R_X9Y65", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y66": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y67": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 34, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 138, + "segment": "SEG_DSP2_R_X9Y65", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y67": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y68": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 36, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 137, + "segment": "SEG_DSP3_R_X9Y65", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y68": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y69": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 38, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 136, + "segment": "SEG_DSP4_R_X9Y65", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y69": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y7": { + "bits": {}, + "grid_x": 26, + "grid_y": 200, + "segment": "SEG_DSP2_R_X9Y5", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y7": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y70": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 40, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 135, + "segment": "SEG_DSP0_R_X9Y70", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y70": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y71": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 42, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 134, + "segment": "SEG_DSP1_R_X9Y70", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y71": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y72": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 44, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 133, + "segment": "SEG_DSP2_R_X9Y70", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y72": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y73": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 46, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 132, + "segment": "SEG_DSP3_R_X9Y70", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y73": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y74": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 48, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 131, + "segment": "SEG_DSP4_R_X9Y70", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y74": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y75": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 51, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 129, + "segment": "SEG_DSP0_R_X9Y75", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y75": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y76": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 53, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 128, + "segment": "SEG_DSP1_R_X9Y75", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y76": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y77": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 55, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 127, + "segment": "SEG_DSP2_R_X9Y75", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y77": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y78": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 57, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 126, + "segment": "SEG_DSP3_R_X9Y75", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y78": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y79": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 59, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 125, + "segment": "SEG_DSP4_R_X9Y75", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y79": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y8": { + "bits": {}, + "grid_x": 26, + "grid_y": 199, + "segment": "SEG_DSP3_R_X9Y5", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y8": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y80": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 61, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 124, + "segment": "SEG_DSP0_R_X9Y80", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y80": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y81": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 63, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 123, + "segment": "SEG_DSP1_R_X9Y80", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y81": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y82": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 65, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 122, + "segment": "SEG_DSP2_R_X9Y80", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y82": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y83": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 67, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 121, + "segment": "SEG_DSP3_R_X9Y80", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y83": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y84": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 69, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 120, + "segment": "SEG_DSP4_R_X9Y80", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y84": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y85": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 71, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 119, + "segment": "SEG_DSP0_R_X9Y85", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y85": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y86": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 73, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 118, + "segment": "SEG_DSP1_R_X9Y85", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y86": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y87": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 75, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 117, + "segment": "SEG_DSP2_R_X9Y85", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y87": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y88": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 77, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 116, + "segment": "SEG_DSP3_R_X9Y85", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y88": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y89": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 79, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 115, + "segment": "SEG_DSP4_R_X9Y85", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y89": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y9": { + "bits": {}, + "grid_x": 26, + "grid_y": 198, + "segment": "SEG_DSP4_R_X9Y5", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y9": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y90": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 81, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 114, + "segment": "SEG_DSP0_R_X9Y90", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y90": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y91": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 83, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 113, + "segment": "SEG_DSP1_R_X9Y90", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y91": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y92": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 85, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 112, + "segment": "SEG_DSP2_R_X9Y90", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y92": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y93": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 87, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 111, + "segment": "SEG_DSP3_R_X9Y90", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y93": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y94": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 89, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 110, + "segment": "SEG_DSP4_R_X9Y90", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y94": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y95": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 91, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 109, + "segment": "SEG_DSP0_R_X9Y95", + "segment_type": "dsp0_r", + "sites": { + "TIEOFF_X9Y95": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y96": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 93, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 108, + "segment": "SEG_DSP1_R_X9Y95", + "segment_type": "dsp1_r", + "sites": { + "TIEOFF_X9Y96": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y97": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 95, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 107, + "segment": "SEG_DSP2_R_X9Y95", + "segment_type": "dsp2_r", + "sites": { + "TIEOFF_X9Y97": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y98": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 97, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 106, + "segment": "SEG_DSP3_R_X9Y95", + "segment_type": "dsp3_r", + "sites": { + "TIEOFF_X9Y98": "TIEOFF" + }, + "type": "INT_R" + }, + "INT_R_X9Y99": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00400480", + "frames": 28, + "height": 2, + "offset": 99, + "words": 2 + } + }, + "grid_x": 26, + "grid_y": 105, + "segment": "SEG_DSP4_R_X9Y95", + "segment_type": "dsp4_r", + "sites": { + "TIEOFF_X9Y99": "TIEOFF" + }, + "type": "INT_R" + }, + "IO_INT_INTERFACE_L_X0Y0": { + "bits": {}, + "grid_x": 3, + "grid_y": 207, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y1": { + "bits": {}, + "grid_x": 3, + "grid_y": 206, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y10": { + "bits": {}, + "grid_x": 3, + "grid_y": 197, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y100": { + "bits": {}, + "grid_x": 3, + "grid_y": 103, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y101": { + "bits": {}, + "grid_x": 3, + "grid_y": 102, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y102": { + "bits": {}, + "grid_x": 3, + "grid_y": 101, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y103": { + "bits": {}, + "grid_x": 3, + "grid_y": 100, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y104": { + "bits": {}, + "grid_x": 3, + "grid_y": 99, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y105": { + "bits": {}, + "grid_x": 3, + "grid_y": 98, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y106": { + "bits": {}, + "grid_x": 3, + "grid_y": 97, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y107": { + "bits": {}, + "grid_x": 3, + "grid_y": 96, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y108": { + "bits": {}, + "grid_x": 3, + "grid_y": 95, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y109": { + "bits": {}, + "grid_x": 3, + "grid_y": 94, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y11": { + "bits": {}, + "grid_x": 3, + "grid_y": 196, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y110": { + "bits": {}, + "grid_x": 3, + "grid_y": 93, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y111": { + "bits": {}, + "grid_x": 3, + "grid_y": 92, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y112": { + "bits": {}, + "grid_x": 3, + "grid_y": 91, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y113": { + "bits": {}, + "grid_x": 3, + "grid_y": 90, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y114": { + "bits": {}, + "grid_x": 3, + "grid_y": 89, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y115": { + "bits": {}, + "grid_x": 3, + "grid_y": 88, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y116": { + "bits": {}, + "grid_x": 3, + "grid_y": 87, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y117": { + "bits": {}, + "grid_x": 3, + "grid_y": 86, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y118": { + "bits": {}, + "grid_x": 3, + "grid_y": 85, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y119": { + "bits": {}, + "grid_x": 3, + "grid_y": 84, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y12": { + "bits": {}, + "grid_x": 3, + "grid_y": 195, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y120": { + "bits": {}, + "grid_x": 3, + "grid_y": 83, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y121": { + "bits": {}, + "grid_x": 3, + "grid_y": 82, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y122": { + "bits": {}, + "grid_x": 3, + "grid_y": 81, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y123": { + "bits": {}, + "grid_x": 3, + "grid_y": 80, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y124": { + "bits": {}, + "grid_x": 3, + "grid_y": 79, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y125": { + "bits": {}, + "grid_x": 3, + "grid_y": 77, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y126": { + "bits": {}, + "grid_x": 3, + "grid_y": 76, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y127": { + "bits": {}, + "grid_x": 3, + "grid_y": 75, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y128": { + "bits": {}, + "grid_x": 3, + "grid_y": 74, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y129": { + "bits": {}, + "grid_x": 3, + "grid_y": 73, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y13": { + "bits": {}, + "grid_x": 3, + "grid_y": 194, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y130": { + "bits": {}, + "grid_x": 3, + "grid_y": 72, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y131": { + "bits": {}, + "grid_x": 3, + "grid_y": 71, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y132": { + "bits": {}, + "grid_x": 3, + "grid_y": 70, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y133": { + "bits": {}, + "grid_x": 3, + "grid_y": 69, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y134": { + "bits": {}, + "grid_x": 3, + "grid_y": 68, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y135": { + "bits": {}, + "grid_x": 3, + "grid_y": 67, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y136": { + "bits": {}, + "grid_x": 3, + "grid_y": 66, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y137": { + "bits": {}, + "grid_x": 3, + "grid_y": 65, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y138": { + "bits": {}, + "grid_x": 3, + "grid_y": 64, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y139": { + "bits": {}, + "grid_x": 3, + "grid_y": 63, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y14": { + "bits": {}, + "grid_x": 3, + "grid_y": 193, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y140": { + "bits": {}, + "grid_x": 3, + "grid_y": 62, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y141": { + "bits": {}, + "grid_x": 3, + "grid_y": 61, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y142": { + "bits": {}, + "grid_x": 3, + "grid_y": 60, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y143": { + "bits": {}, + "grid_x": 3, + "grid_y": 59, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y144": { + "bits": {}, + "grid_x": 3, + "grid_y": 58, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y145": { + "bits": {}, + "grid_x": 3, + "grid_y": 57, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y146": { + "bits": {}, + "grid_x": 3, + "grid_y": 56, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y147": { + "bits": {}, + "grid_x": 3, + "grid_y": 55, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y148": { + "bits": {}, + "grid_x": 3, + "grid_y": 54, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y149": { + "bits": {}, + "grid_x": 3, + "grid_y": 53, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y15": { + "bits": {}, + "grid_x": 3, + "grid_y": 192, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y150": { + "bits": {}, + "grid_x": 3, + "grid_y": 51, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y151": { + "bits": {}, + "grid_x": 3, + "grid_y": 50, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y152": { + "bits": {}, + "grid_x": 3, + "grid_y": 49, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y153": { + "bits": {}, + "grid_x": 3, + "grid_y": 48, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y154": { + "bits": {}, + "grid_x": 3, + "grid_y": 47, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y155": { + "bits": {}, + "grid_x": 3, + "grid_y": 46, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y156": { + "bits": {}, + "grid_x": 3, + "grid_y": 45, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y157": { + "bits": {}, + "grid_x": 3, + "grid_y": 44, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y158": { + "bits": {}, + "grid_x": 3, + "grid_y": 43, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y159": { + "bits": {}, + "grid_x": 3, + "grid_y": 42, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y16": { + "bits": {}, + "grid_x": 3, + "grid_y": 191, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y160": { + "bits": {}, + "grid_x": 3, + "grid_y": 41, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y161": { + "bits": {}, + "grid_x": 3, + "grid_y": 40, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y162": { + "bits": {}, + "grid_x": 3, + "grid_y": 39, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y163": { + "bits": {}, + "grid_x": 3, + "grid_y": 38, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y164": { + "bits": {}, + "grid_x": 3, + "grid_y": 37, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y165": { + "bits": {}, + "grid_x": 3, + "grid_y": 36, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y166": { + "bits": {}, + "grid_x": 3, + "grid_y": 35, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y167": { + "bits": {}, + "grid_x": 3, + "grid_y": 34, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y168": { + "bits": {}, + "grid_x": 3, + "grid_y": 33, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y169": { + "bits": {}, + "grid_x": 3, + "grid_y": 32, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y17": { + "bits": {}, + "grid_x": 3, + "grid_y": 190, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y170": { + "bits": {}, + "grid_x": 3, + "grid_y": 31, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y171": { + "bits": {}, + "grid_x": 3, + "grid_y": 30, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y172": { + "bits": {}, + "grid_x": 3, + "grid_y": 29, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y173": { + "bits": {}, + "grid_x": 3, + "grid_y": 28, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y174": { + "bits": {}, + "grid_x": 3, + "grid_y": 27, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y175": { + "bits": {}, + "grid_x": 3, + "grid_y": 25, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y176": { + "bits": {}, + "grid_x": 3, + "grid_y": 24, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y177": { + "bits": {}, + "grid_x": 3, + "grid_y": 23, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y178": { + "bits": {}, + "grid_x": 3, + "grid_y": 22, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y179": { + "bits": {}, + "grid_x": 3, + "grid_y": 21, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y18": { + "bits": {}, + "grid_x": 3, + "grid_y": 189, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y180": { + "bits": {}, + "grid_x": 3, + "grid_y": 20, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y181": { + "bits": {}, + "grid_x": 3, + "grid_y": 19, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y182": { + "bits": {}, + "grid_x": 3, + "grid_y": 18, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y183": { + "bits": {}, + "grid_x": 3, + "grid_y": 17, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y184": { + "bits": {}, + "grid_x": 3, + "grid_y": 16, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y185": { + "bits": {}, + "grid_x": 3, + "grid_y": 15, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y186": { + "bits": {}, + "grid_x": 3, + "grid_y": 14, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y187": { + "bits": {}, + "grid_x": 3, + "grid_y": 13, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y188": { + "bits": {}, + "grid_x": 3, + "grid_y": 12, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y189": { + "bits": {}, + "grid_x": 3, + "grid_y": 11, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y19": { + "bits": {}, + "grid_x": 3, + "grid_y": 188, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y190": { + "bits": {}, + "grid_x": 3, + "grid_y": 10, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y191": { + "bits": {}, + "grid_x": 3, + "grid_y": 9, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y192": { + "bits": {}, + "grid_x": 3, + "grid_y": 8, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y193": { + "bits": {}, + "grid_x": 3, + "grid_y": 7, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y194": { + "bits": {}, + "grid_x": 3, + "grid_y": 6, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y195": { + "bits": {}, + "grid_x": 3, + "grid_y": 5, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y196": { + "bits": {}, + "grid_x": 3, + "grid_y": 4, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y197": { + "bits": {}, + "grid_x": 3, + "grid_y": 3, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y198": { + "bits": {}, + "grid_x": 3, + "grid_y": 2, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y199": { + "bits": {}, + "grid_x": 3, + "grid_y": 1, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y2": { + "bits": {}, + "grid_x": 3, + "grid_y": 205, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y20": { + "bits": {}, + "grid_x": 3, + "grid_y": 187, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y21": { + "bits": {}, + "grid_x": 3, + "grid_y": 186, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y22": { + "bits": {}, + "grid_x": 3, + "grid_y": 185, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y23": { + "bits": {}, + "grid_x": 3, + "grid_y": 184, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y24": { + "bits": {}, + "grid_x": 3, + "grid_y": 183, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y25": { + "bits": {}, + "grid_x": 3, + "grid_y": 181, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y26": { + "bits": {}, + "grid_x": 3, + "grid_y": 180, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y27": { + "bits": {}, + "grid_x": 3, + "grid_y": 179, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y28": { + "bits": {}, + "grid_x": 3, + "grid_y": 178, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y29": { + "bits": {}, + "grid_x": 3, + "grid_y": 177, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y3": { + "bits": {}, + "grid_x": 3, + "grid_y": 204, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y30": { + "bits": {}, + "grid_x": 3, + "grid_y": 176, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y31": { + "bits": {}, + "grid_x": 3, + "grid_y": 175, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y32": { + "bits": {}, + "grid_x": 3, + "grid_y": 174, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y33": { + "bits": {}, + "grid_x": 3, + "grid_y": 173, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y34": { + "bits": {}, + "grid_x": 3, + "grid_y": 172, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y35": { + "bits": {}, + "grid_x": 3, + "grid_y": 171, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y36": { + "bits": {}, + "grid_x": 3, + "grid_y": 170, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y37": { + "bits": {}, + "grid_x": 3, + "grid_y": 169, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y38": { + "bits": {}, + "grid_x": 3, + "grid_y": 168, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y39": { + "bits": {}, + "grid_x": 3, + "grid_y": 167, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y4": { + "bits": {}, + "grid_x": 3, + "grid_y": 203, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y40": { + "bits": {}, + "grid_x": 3, + "grid_y": 166, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y41": { + "bits": {}, + "grid_x": 3, + "grid_y": 165, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y42": { + "bits": {}, + "grid_x": 3, + "grid_y": 164, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y43": { + "bits": {}, + "grid_x": 3, + "grid_y": 163, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y44": { + "bits": {}, + "grid_x": 3, + "grid_y": 162, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y45": { + "bits": {}, + "grid_x": 3, + "grid_y": 161, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y46": { + "bits": {}, + "grid_x": 3, + "grid_y": 160, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y47": { + "bits": {}, + "grid_x": 3, + "grid_y": 159, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y48": { + "bits": {}, + "grid_x": 3, + "grid_y": 158, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y49": { + "bits": {}, + "grid_x": 3, + "grid_y": 157, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y5": { + "bits": {}, + "grid_x": 3, + "grid_y": 202, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y50": { + "bits": {}, + "grid_x": 3, + "grid_y": 155, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y51": { + "bits": {}, + "grid_x": 3, + "grid_y": 154, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y52": { + "bits": {}, + "grid_x": 3, + "grid_y": 153, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y53": { + "bits": {}, + "grid_x": 3, + "grid_y": 152, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y54": { + "bits": {}, + "grid_x": 3, + "grid_y": 151, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y55": { + "bits": {}, + "grid_x": 3, + "grid_y": 150, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y56": { + "bits": {}, + "grid_x": 3, + "grid_y": 149, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y57": { + "bits": {}, + "grid_x": 3, + "grid_y": 148, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y58": { + "bits": {}, + "grid_x": 3, + "grid_y": 147, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y59": { + "bits": {}, + "grid_x": 3, + "grid_y": 146, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y6": { + "bits": {}, + "grid_x": 3, + "grid_y": 201, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y60": { + "bits": {}, + "grid_x": 3, + "grid_y": 145, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y61": { + "bits": {}, + "grid_x": 3, + "grid_y": 144, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y62": { + "bits": {}, + "grid_x": 3, + "grid_y": 143, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y63": { + "bits": {}, + "grid_x": 3, + "grid_y": 142, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y64": { + "bits": {}, + "grid_x": 3, + "grid_y": 141, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y65": { + "bits": {}, + "grid_x": 3, + "grid_y": 140, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y66": { + "bits": {}, + "grid_x": 3, + "grid_y": 139, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y67": { + "bits": {}, + "grid_x": 3, + "grid_y": 138, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y68": { + "bits": {}, + "grid_x": 3, + "grid_y": 137, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y69": { + "bits": {}, + "grid_x": 3, + "grid_y": 136, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y7": { + "bits": {}, + "grid_x": 3, + "grid_y": 200, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y70": { + "bits": {}, + "grid_x": 3, + "grid_y": 135, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y71": { + "bits": {}, + "grid_x": 3, + "grid_y": 134, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y72": { + "bits": {}, + "grid_x": 3, + "grid_y": 133, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y73": { + "bits": {}, + "grid_x": 3, + "grid_y": 132, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y74": { + "bits": {}, + "grid_x": 3, + "grid_y": 131, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y75": { + "bits": {}, + "grid_x": 3, + "grid_y": 129, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y76": { + "bits": {}, + "grid_x": 3, + "grid_y": 128, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y77": { + "bits": {}, + "grid_x": 3, + "grid_y": 127, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y78": { + "bits": {}, + "grid_x": 3, + "grid_y": 126, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y79": { + "bits": {}, + "grid_x": 3, + "grid_y": 125, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y8": { + "bits": {}, + "grid_x": 3, + "grid_y": 199, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y80": { + "bits": {}, + "grid_x": 3, + "grid_y": 124, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y81": { + "bits": {}, + "grid_x": 3, + "grid_y": 123, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y82": { + "bits": {}, + "grid_x": 3, + "grid_y": 122, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y83": { + "bits": {}, + "grid_x": 3, + "grid_y": 121, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y84": { + "bits": {}, + "grid_x": 3, + "grid_y": 120, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y85": { + "bits": {}, + "grid_x": 3, + "grid_y": 119, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y86": { + "bits": {}, + "grid_x": 3, + "grid_y": 118, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y87": { + "bits": {}, + "grid_x": 3, + "grid_y": 117, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y88": { + "bits": {}, + "grid_x": 3, + "grid_y": 116, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y89": { + "bits": {}, + "grid_x": 3, + "grid_y": 115, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y9": { + "bits": {}, + "grid_x": 3, + "grid_y": 198, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y90": { + "bits": {}, + "grid_x": 3, + "grid_y": 114, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y91": { + "bits": {}, + "grid_x": 3, + "grid_y": 113, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y92": { + "bits": {}, + "grid_x": 3, + "grid_y": 112, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y93": { + "bits": {}, + "grid_x": 3, + "grid_y": 111, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y94": { + "bits": {}, + "grid_x": 3, + "grid_y": 110, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y95": { + "bits": {}, + "grid_x": 3, + "grid_y": 109, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y96": { + "bits": {}, + "grid_x": 3, + "grid_y": 108, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y97": { + "bits": {}, + "grid_x": 3, + "grid_y": 107, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y98": { + "bits": {}, + "grid_x": 3, + "grid_y": 106, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_L_X0Y99": { + "bits": {}, + "grid_x": 3, + "grid_y": 105, + "sites": {}, + "type": "IO_INT_INTERFACE_L" + }, + "IO_INT_INTERFACE_R_X43Y0": { + "bits": {}, + "grid_x": 113, + "grid_y": 207, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y1": { + "bits": {}, + "grid_x": 113, + "grid_y": 206, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y10": { + "bits": {}, + "grid_x": 113, + "grid_y": 197, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y11": { + "bits": {}, + "grid_x": 113, + "grid_y": 196, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y12": { + "bits": {}, + "grid_x": 113, + "grid_y": 195, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y13": { + "bits": {}, + "grid_x": 113, + "grid_y": 194, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y14": { + "bits": {}, + "grid_x": 113, + "grid_y": 193, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y15": { + "bits": {}, + "grid_x": 113, + "grid_y": 192, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y16": { + "bits": {}, + "grid_x": 113, + "grid_y": 191, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y17": { + "bits": {}, + "grid_x": 113, + "grid_y": 190, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y18": { + "bits": {}, + "grid_x": 113, + "grid_y": 189, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y19": { + "bits": {}, + "grid_x": 113, + "grid_y": 188, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y2": { + "bits": {}, + "grid_x": 113, + "grid_y": 205, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y20": { + "bits": {}, + "grid_x": 113, + "grid_y": 187, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y21": { + "bits": {}, + "grid_x": 113, + "grid_y": 186, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y22": { + "bits": {}, + "grid_x": 113, + "grid_y": 185, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y23": { + "bits": {}, + "grid_x": 113, + "grid_y": 184, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y24": { + "bits": {}, + "grid_x": 113, + "grid_y": 183, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y25": { + "bits": {}, + "grid_x": 113, + "grid_y": 181, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y26": { + "bits": {}, + "grid_x": 113, + "grid_y": 180, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y27": { + "bits": {}, + "grid_x": 113, + "grid_y": 179, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y28": { + "bits": {}, + "grid_x": 113, + "grid_y": 178, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y29": { + "bits": {}, + "grid_x": 113, + "grid_y": 177, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y3": { + "bits": {}, + "grid_x": 113, + "grid_y": 204, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y30": { + "bits": {}, + "grid_x": 113, + "grid_y": 176, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y31": { + "bits": {}, + "grid_x": 113, + "grid_y": 175, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y32": { + "bits": {}, + "grid_x": 113, + "grid_y": 174, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y33": { + "bits": {}, + "grid_x": 113, + "grid_y": 173, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y34": { + "bits": {}, + "grid_x": 113, + "grid_y": 172, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y35": { + "bits": {}, + "grid_x": 113, + "grid_y": 171, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y36": { + "bits": {}, + "grid_x": 113, + "grid_y": 170, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y37": { + "bits": {}, + "grid_x": 113, + "grid_y": 169, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y38": { + "bits": {}, + "grid_x": 113, + "grid_y": 168, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y39": { + "bits": {}, + "grid_x": 113, + "grid_y": 167, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y4": { + "bits": {}, + "grid_x": 113, + "grid_y": 203, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y40": { + "bits": {}, + "grid_x": 113, + "grid_y": 166, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y41": { + "bits": {}, + "grid_x": 113, + "grid_y": 165, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y42": { + "bits": {}, + "grid_x": 113, + "grid_y": 164, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y43": { + "bits": {}, + "grid_x": 113, + "grid_y": 163, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y44": { + "bits": {}, + "grid_x": 113, + "grid_y": 162, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y45": { + "bits": {}, + "grid_x": 113, + "grid_y": 161, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y46": { + "bits": {}, + "grid_x": 113, + "grid_y": 160, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y47": { + "bits": {}, + "grid_x": 113, + "grid_y": 159, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y48": { + "bits": {}, + "grid_x": 113, + "grid_y": 158, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y49": { + "bits": {}, + "grid_x": 113, + "grid_y": 157, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y5": { + "bits": {}, + "grid_x": 113, + "grid_y": 202, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y50": { + "bits": {}, + "grid_x": 113, + "grid_y": 155, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y51": { + "bits": {}, + "grid_x": 113, + "grid_y": 154, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y52": { + "bits": {}, + "grid_x": 113, + "grid_y": 153, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y53": { + "bits": {}, + "grid_x": 113, + "grid_y": 152, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y54": { + "bits": {}, + "grid_x": 113, + "grid_y": 151, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y55": { + "bits": {}, + "grid_x": 113, + "grid_y": 150, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y56": { + "bits": {}, + "grid_x": 113, + "grid_y": 149, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y57": { + "bits": {}, + "grid_x": 113, + "grid_y": 148, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y58": { + "bits": {}, + "grid_x": 113, + "grid_y": 147, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y59": { + "bits": {}, + "grid_x": 113, + "grid_y": 146, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y6": { + "bits": {}, + "grid_x": 113, + "grid_y": 201, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y60": { + "bits": {}, + "grid_x": 113, + "grid_y": 145, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y61": { + "bits": {}, + "grid_x": 113, + "grid_y": 144, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y62": { + "bits": {}, + "grid_x": 113, + "grid_y": 143, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y63": { + "bits": {}, + "grid_x": 113, + "grid_y": 142, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y64": { + "bits": {}, + "grid_x": 113, + "grid_y": 141, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y65": { + "bits": {}, + "grid_x": 113, + "grid_y": 140, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y66": { + "bits": {}, + "grid_x": 113, + "grid_y": 139, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y67": { + "bits": {}, + "grid_x": 113, + "grid_y": 138, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y68": { + "bits": {}, + "grid_x": 113, + "grid_y": 137, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y69": { + "bits": {}, + "grid_x": 113, + "grid_y": 136, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y7": { + "bits": {}, + "grid_x": 113, + "grid_y": 200, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y70": { + "bits": {}, + "grid_x": 113, + "grid_y": 135, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y71": { + "bits": {}, + "grid_x": 113, + "grid_y": 134, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y72": { + "bits": {}, + "grid_x": 113, + "grid_y": 133, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y73": { + "bits": {}, + "grid_x": 113, + "grid_y": 132, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y74": { + "bits": {}, + "grid_x": 113, + "grid_y": 131, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y75": { + "bits": {}, + "grid_x": 113, + "grid_y": 129, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y76": { + "bits": {}, + "grid_x": 113, + "grid_y": 128, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y77": { + "bits": {}, + "grid_x": 113, + "grid_y": 127, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y78": { + "bits": {}, + "grid_x": 113, + "grid_y": 126, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y79": { + "bits": {}, + "grid_x": 113, + "grid_y": 125, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y8": { + "bits": {}, + "grid_x": 113, + "grid_y": 199, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y80": { + "bits": {}, + "grid_x": 113, + "grid_y": 124, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y81": { + "bits": {}, + "grid_x": 113, + "grid_y": 123, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y82": { + "bits": {}, + "grid_x": 113, + "grid_y": 122, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y83": { + "bits": {}, + "grid_x": 113, + "grid_y": 121, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y84": { + "bits": {}, + "grid_x": 113, + "grid_y": 120, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y85": { + "bits": {}, + "grid_x": 113, + "grid_y": 119, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y86": { + "bits": {}, + "grid_x": 113, + "grid_y": 118, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y87": { + "bits": {}, + "grid_x": 113, + "grid_y": 117, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y88": { + "bits": {}, + "grid_x": 113, + "grid_y": 116, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y89": { + "bits": {}, + "grid_x": 113, + "grid_y": 115, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y9": { + "bits": {}, + "grid_x": 113, + "grid_y": 198, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y90": { + "bits": {}, + "grid_x": 113, + "grid_y": 114, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y91": { + "bits": {}, + "grid_x": 113, + "grid_y": 113, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y92": { + "bits": {}, + "grid_x": 113, + "grid_y": 112, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y93": { + "bits": {}, + "grid_x": 113, + "grid_y": 111, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y94": { + "bits": {}, + "grid_x": 113, + "grid_y": 110, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y95": { + "bits": {}, + "grid_x": 113, + "grid_y": 109, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y96": { + "bits": {}, + "grid_x": 113, + "grid_y": 108, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y97": { + "bits": {}, + "grid_x": 113, + "grid_y": 107, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y98": { + "bits": {}, + "grid_x": 113, + "grid_y": 106, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "IO_INT_INTERFACE_R_X43Y99": { + "bits": {}, + "grid_x": 113, + "grid_y": 105, + "sites": {}, + "type": "IO_INT_INTERFACE_R" + }, + "LIOB33_SING_X0Y0": { + "bits": {}, + "grid_x": 0, + "grid_y": 207, + "sites": { + "IOB_X0Y0": "IOB33" + }, + "type": "LIOB33_SING" + }, + "LIOB33_SING_X0Y100": { + "bits": {}, + "grid_x": 0, + "grid_y": 103, + "sites": { + "IOB_X0Y100": "IOB33" + }, + "type": "LIOB33_SING" + }, + "LIOB33_SING_X0Y149": { + "bits": {}, + "grid_x": 0, + "grid_y": 53, + "sites": { + "IOB_X0Y149": "IOB33" + }, + "type": "LIOB33_SING" + }, + "LIOB33_SING_X0Y150": { + "bits": {}, + "grid_x": 0, + "grid_y": 51, + "sites": { + "IOB_X0Y150": "IOB33" + }, + "type": "LIOB33_SING" + }, + "LIOB33_SING_X0Y199": { + "bits": {}, + "grid_x": 0, + "grid_y": 1, + "sites": { + "IOB_X0Y199": "IOB33" + }, + "type": "LIOB33_SING" + }, + "LIOB33_SING_X0Y49": { + "bits": {}, + "grid_x": 0, + "grid_y": 157, + "sites": { + "IOB_X0Y49": "IOB33" + }, + "type": "LIOB33_SING" + }, + "LIOB33_SING_X0Y50": { + "bits": {}, + "grid_x": 0, + "grid_y": 155, + "sites": { + "IOB_X0Y50": "IOB33" + }, + "type": "LIOB33_SING" + }, + "LIOB33_SING_X0Y99": { + "bits": {}, + "grid_x": 0, + "grid_y": 105, + "sites": { + "IOB_X0Y99": "IOB33" + }, + "type": "LIOB33_SING" + }, + "LIOB33_X0Y1": { + "bits": {}, + "grid_x": 0, + "grid_y": 206, + "sites": { + "IOB_X0Y1": "IOB33S", + "IOB_X0Y2": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y101": { + "bits": {}, + "grid_x": 0, + "grid_y": 102, + "sites": { + "IOB_X0Y101": "IOB33S", + "IOB_X0Y102": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y103": { + "bits": {}, + "grid_x": 0, + "grid_y": 100, + "sites": { + "IOB_X0Y103": "IOB33S", + "IOB_X0Y104": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y105": { + "bits": {}, + "grid_x": 0, + "grid_y": 98, + "sites": { + "IOB_X0Y105": "IOB33S", + "IOB_X0Y106": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y107": { + "bits": {}, + "grid_x": 0, + "grid_y": 96, + "sites": { + "IOB_X0Y107": "IOB33S", + "IOB_X0Y108": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y109": { + "bits": {}, + "grid_x": 0, + "grid_y": 94, + "sites": { + "IOB_X0Y109": "IOB33S", + "IOB_X0Y110": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y11": { + "bits": {}, + "grid_x": 0, + "grid_y": 196, + "sites": { + "IOB_X0Y11": "IOB33S", + "IOB_X0Y12": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y111": { + "bits": {}, + "grid_x": 0, + "grid_y": 92, + "sites": { + "IOB_X0Y111": "IOB33S", + "IOB_X0Y112": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y113": { + "bits": {}, + "grid_x": 0, + "grid_y": 90, + "sites": { + "IOB_X0Y113": "IOB33S", + "IOB_X0Y114": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y115": { + "bits": {}, + "grid_x": 0, + "grid_y": 88, + "sites": { + "IOB_X0Y115": "IOB33S", + "IOB_X0Y116": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y117": { + "bits": {}, + "grid_x": 0, + "grid_y": 86, + "sites": { + "IOB_X0Y117": "IOB33S", + "IOB_X0Y118": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y119": { + "bits": {}, + "grid_x": 0, + "grid_y": 84, + "sites": { + "IOB_X0Y119": "IOB33S", + "IOB_X0Y120": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y121": { + "bits": {}, + "grid_x": 0, + "grid_y": 82, + "sites": { + "IOB_X0Y121": "IOB33S", + "IOB_X0Y122": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y123": { + "bits": {}, + "grid_x": 0, + "grid_y": 80, + "sites": { + "IOB_X0Y123": "IOB33S", + "IOB_X0Y124": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y125": { + "bits": {}, + "grid_x": 0, + "grid_y": 77, + "sites": { + "IOB_X0Y125": "IOB33S", + "IOB_X0Y126": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y127": { + "bits": {}, + "grid_x": 0, + "grid_y": 75, + "sites": { + "IOB_X0Y127": "IOB33S", + "IOB_X0Y128": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y129": { + "bits": {}, + "grid_x": 0, + "grid_y": 73, + "sites": { + "IOB_X0Y129": "IOB33S", + "IOB_X0Y130": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y13": { + "bits": {}, + "grid_x": 0, + "grid_y": 194, + "sites": { + "IOB_X0Y13": "IOB33S", + "IOB_X0Y14": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y131": { + "bits": {}, + "grid_x": 0, + "grid_y": 71, + "sites": { + "IOB_X0Y131": "IOB33S", + "IOB_X0Y132": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y133": { + "bits": {}, + "grid_x": 0, + "grid_y": 69, + "sites": { + "IOB_X0Y133": "IOB33S", + "IOB_X0Y134": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y135": { + "bits": {}, + "grid_x": 0, + "grid_y": 67, + "sites": { + "IOB_X0Y135": "IOB33S", + "IOB_X0Y136": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y137": { + "bits": {}, + "grid_x": 0, + "grid_y": 65, + "sites": { + "IOB_X0Y137": "IOB33S", + "IOB_X0Y138": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y139": { + "bits": {}, + "grid_x": 0, + "grid_y": 63, + "sites": { + "IOB_X0Y139": "IOB33S", + "IOB_X0Y140": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y141": { + "bits": {}, + "grid_x": 0, + "grid_y": 61, + "sites": { + "IOB_X0Y141": "IOB33S", + "IOB_X0Y142": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y143": { + "bits": {}, + "grid_x": 0, + "grid_y": 59, + "sites": { + "IOB_X0Y143": "IOB33S", + "IOB_X0Y144": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y145": { + "bits": {}, + "grid_x": 0, + "grid_y": 57, + "sites": { + "IOB_X0Y145": "IOB33S", + "IOB_X0Y146": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y147": { + "bits": {}, + "grid_x": 0, + "grid_y": 55, + "sites": { + "IOB_X0Y147": "IOB33S", + "IOB_X0Y148": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y15": { + "bits": {}, + "grid_x": 0, + "grid_y": 192, + "sites": { + "IOB_X0Y15": "IOB33S", + "IOB_X0Y16": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y151": { + "bits": {}, + "grid_x": 0, + "grid_y": 50, + "sites": { + "IOB_X0Y151": "IOB33S", + "IOB_X0Y152": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y153": { + "bits": {}, + "grid_x": 0, + "grid_y": 48, + "sites": { + "IOB_X0Y153": "IOB33S", + "IOB_X0Y154": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y155": { + "bits": {}, + "grid_x": 0, + "grid_y": 46, + "sites": { + "IOB_X0Y155": "IOB33S", + "IOB_X0Y156": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y157": { + "bits": {}, + "grid_x": 0, + "grid_y": 44, + "sites": { + "IOB_X0Y157": "IOB33S", + "IOB_X0Y158": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y159": { + "bits": {}, + "grid_x": 0, + "grid_y": 42, + "sites": { + "IOB_X0Y159": "IOB33S", + "IOB_X0Y160": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y161": { + "bits": {}, + "grid_x": 0, + "grid_y": 40, + "sites": { + "IOB_X0Y161": "IOB33S", + "IOB_X0Y162": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y163": { + "bits": {}, + "grid_x": 0, + "grid_y": 38, + "sites": { + "IOB_X0Y163": "IOB33S", + "IOB_X0Y164": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y165": { + "bits": {}, + "grid_x": 0, + "grid_y": 36, + "sites": { + "IOB_X0Y165": "IOB33S", + "IOB_X0Y166": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y167": { + "bits": {}, + "grid_x": 0, + "grid_y": 34, + "sites": { + "IOB_X0Y167": "IOB33S", + "IOB_X0Y168": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y169": { + "bits": {}, + "grid_x": 0, + "grid_y": 32, + "sites": { + "IOB_X0Y169": "IOB33S", + "IOB_X0Y170": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y17": { + "bits": {}, + "grid_x": 0, + "grid_y": 190, + "sites": { + "IOB_X0Y17": "IOB33S", + "IOB_X0Y18": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y171": { + "bits": {}, + "grid_x": 0, + "grid_y": 30, + "sites": { + "IOB_X0Y171": "IOB33S", + "IOB_X0Y172": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y173": { + "bits": {}, + "grid_x": 0, + "grid_y": 28, + "sites": { + "IOB_X0Y173": "IOB33S", + "IOB_X0Y174": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y175": { + "bits": {}, + "grid_x": 0, + "grid_y": 25, + "sites": { + "IOB_X0Y175": "IOB33S", + "IOB_X0Y176": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y177": { + "bits": {}, + "grid_x": 0, + "grid_y": 23, + "sites": { + "IOB_X0Y177": "IOB33S", + "IOB_X0Y178": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y179": { + "bits": {}, + "grid_x": 0, + "grid_y": 21, + "sites": { + "IOB_X0Y179": "IOB33S", + "IOB_X0Y180": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y181": { + "bits": {}, + "grid_x": 0, + "grid_y": 19, + "sites": { + "IOB_X0Y181": "IOB33S", + "IOB_X0Y182": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y183": { + "bits": {}, + "grid_x": 0, + "grid_y": 17, + "sites": { + "IOB_X0Y183": "IOB33S", + "IOB_X0Y184": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y185": { + "bits": {}, + "grid_x": 0, + "grid_y": 15, + "sites": { + "IOB_X0Y185": "IOB33S", + "IOB_X0Y186": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y187": { + "bits": {}, + "grid_x": 0, + "grid_y": 13, + "sites": { + "IOB_X0Y187": "IOB33S", + "IOB_X0Y188": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y189": { + "bits": {}, + "grid_x": 0, + "grid_y": 11, + "sites": { + "IOB_X0Y189": "IOB33S", + "IOB_X0Y190": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y19": { + "bits": {}, + "grid_x": 0, + "grid_y": 188, + "sites": { + "IOB_X0Y19": "IOB33S", + "IOB_X0Y20": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y191": { + "bits": {}, + "grid_x": 0, + "grid_y": 9, + "sites": { + "IOB_X0Y191": "IOB33S", + "IOB_X0Y192": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y193": { + "bits": {}, + "grid_x": 0, + "grid_y": 7, + "sites": { + "IOB_X0Y193": "IOB33S", + "IOB_X0Y194": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y195": { + "bits": {}, + "grid_x": 0, + "grid_y": 5, + "sites": { + "IOB_X0Y195": "IOB33S", + "IOB_X0Y196": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y197": { + "bits": {}, + "grid_x": 0, + "grid_y": 3, + "sites": { + "IOB_X0Y197": "IOB33S", + "IOB_X0Y198": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y21": { + "bits": {}, + "grid_x": 0, + "grid_y": 186, + "sites": { + "IOB_X0Y21": "IOB33S", + "IOB_X0Y22": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y23": { + "bits": {}, + "grid_x": 0, + "grid_y": 184, + "sites": { + "IOB_X0Y23": "IOB33S", + "IOB_X0Y24": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y25": { + "bits": {}, + "grid_x": 0, + "grid_y": 181, + "sites": { + "IOB_X0Y25": "IOB33S", + "IOB_X0Y26": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y27": { + "bits": {}, + "grid_x": 0, + "grid_y": 179, + "sites": { + "IOB_X0Y27": "IOB33S", + "IOB_X0Y28": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y29": { + "bits": {}, + "grid_x": 0, + "grid_y": 177, + "sites": { + "IOB_X0Y29": "IOB33S", + "IOB_X0Y30": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y3": { + "bits": {}, + "grid_x": 0, + "grid_y": 204, + "sites": { + "IOB_X0Y3": "IOB33S", + "IOB_X0Y4": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y31": { + "bits": {}, + "grid_x": 0, + "grid_y": 175, + "sites": { + "IOB_X0Y31": "IOB33S", + "IOB_X0Y32": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y33": { + "bits": {}, + "grid_x": 0, + "grid_y": 173, + "sites": { + "IOB_X0Y33": "IOB33S", + "IOB_X0Y34": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y35": { + "bits": {}, + "grid_x": 0, + "grid_y": 171, + "sites": { + "IOB_X0Y35": "IOB33S", + "IOB_X0Y36": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y37": { + "bits": {}, + "grid_x": 0, + "grid_y": 169, + "sites": { + "IOB_X0Y37": "IOB33S", + "IOB_X0Y38": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y39": { + "bits": {}, + "grid_x": 0, + "grid_y": 167, + "sites": { + "IOB_X0Y39": "IOB33S", + "IOB_X0Y40": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y41": { + "bits": {}, + "grid_x": 0, + "grid_y": 165, + "sites": { + "IOB_X0Y41": "IOB33S", + "IOB_X0Y42": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y43": { + "bits": {}, + "grid_x": 0, + "grid_y": 163, + "sites": { + "IOB_X0Y43": "IOB33S", + "IOB_X0Y44": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y45": { + "bits": {}, + "grid_x": 0, + "grid_y": 161, + "sites": { + "IOB_X0Y45": "IOB33S", + "IOB_X0Y46": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y47": { + "bits": {}, + "grid_x": 0, + "grid_y": 159, + "sites": { + "IOB_X0Y47": "IOB33S", + "IOB_X0Y48": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y5": { + "bits": {}, + "grid_x": 0, + "grid_y": 202, + "sites": { + "IOB_X0Y5": "IOB33S", + "IOB_X0Y6": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y51": { + "bits": {}, + "grid_x": 0, + "grid_y": 154, + "sites": { + "IOB_X0Y51": "IOB33S", + "IOB_X0Y52": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y53": { + "bits": {}, + "grid_x": 0, + "grid_y": 152, + "sites": { + "IOB_X0Y53": "IOB33S", + "IOB_X0Y54": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y55": { + "bits": {}, + "grid_x": 0, + "grid_y": 150, + "sites": { + "IOB_X0Y55": "IOB33S", + "IOB_X0Y56": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y57": { + "bits": {}, + "grid_x": 0, + "grid_y": 148, + "sites": { + "IOB_X0Y57": "IOB33S", + "IOB_X0Y58": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y59": { + "bits": {}, + "grid_x": 0, + "grid_y": 146, + "sites": { + "IOB_X0Y59": "IOB33S", + "IOB_X0Y60": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y61": { + "bits": {}, + "grid_x": 0, + "grid_y": 144, + "sites": { + "IOB_X0Y61": "IOB33S", + "IOB_X0Y62": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y63": { + "bits": {}, + "grid_x": 0, + "grid_y": 142, + "sites": { + "IOB_X0Y63": "IOB33S", + "IOB_X0Y64": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y65": { + "bits": {}, + "grid_x": 0, + "grid_y": 140, + "sites": { + "IOB_X0Y65": "IOB33S", + "IOB_X0Y66": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y67": { + "bits": {}, + "grid_x": 0, + "grid_y": 138, + "sites": { + "IOB_X0Y67": "IOB33S", + "IOB_X0Y68": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y69": { + "bits": {}, + "grid_x": 0, + "grid_y": 136, + "sites": { + "IOB_X0Y69": "IOB33S", + "IOB_X0Y70": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y7": { + "bits": {}, + "grid_x": 0, + "grid_y": 200, + "sites": { + "IOB_X0Y7": "IOB33S", + "IOB_X0Y8": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y71": { + "bits": {}, + "grid_x": 0, + "grid_y": 134, + "sites": { + "IOB_X0Y71": "IOB33S", + "IOB_X0Y72": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y73": { + "bits": {}, + "grid_x": 0, + "grid_y": 132, + "sites": { + "IOB_X0Y73": "IOB33S", + "IOB_X0Y74": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y75": { + "bits": {}, + "grid_x": 0, + "grid_y": 129, + "sites": { + "IOB_X0Y75": "IOB33S", + "IOB_X0Y76": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y77": { + "bits": {}, + "grid_x": 0, + "grid_y": 127, + "sites": { + "IOB_X0Y77": "IOB33S", + "IOB_X0Y78": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y79": { + "bits": {}, + "grid_x": 0, + "grid_y": 125, + "sites": { + "IOB_X0Y79": "IOB33S", + "IOB_X0Y80": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y81": { + "bits": {}, + "grid_x": 0, + "grid_y": 123, + "sites": { + "IOB_X0Y81": "IOB33S", + "IOB_X0Y82": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y83": { + "bits": {}, + "grid_x": 0, + "grid_y": 121, + "sites": { + "IOB_X0Y83": "IOB33S", + "IOB_X0Y84": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y85": { + "bits": {}, + "grid_x": 0, + "grid_y": 119, + "sites": { + "IOB_X0Y85": "IOB33S", + "IOB_X0Y86": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y87": { + "bits": {}, + "grid_x": 0, + "grid_y": 117, + "sites": { + "IOB_X0Y87": "IOB33S", + "IOB_X0Y88": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y89": { + "bits": {}, + "grid_x": 0, + "grid_y": 115, + "sites": { + "IOB_X0Y89": "IOB33S", + "IOB_X0Y90": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y9": { + "bits": {}, + "grid_x": 0, + "grid_y": 198, + "sites": { + "IOB_X0Y10": "IOB33M", + "IOB_X0Y9": "IOB33S" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y91": { + "bits": {}, + "grid_x": 0, + "grid_y": 113, + "sites": { + "IOB_X0Y91": "IOB33S", + "IOB_X0Y92": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y93": { + "bits": {}, + "grid_x": 0, + "grid_y": 111, + "sites": { + "IOB_X0Y93": "IOB33S", + "IOB_X0Y94": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y95": { + "bits": {}, + "grid_x": 0, + "grid_y": 109, + "sites": { + "IOB_X0Y95": "IOB33S", + "IOB_X0Y96": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOB33_X0Y97": { + "bits": {}, + "grid_x": 0, + "grid_y": 107, + "sites": { + "IOB_X0Y97": "IOB33S", + "IOB_X0Y98": "IOB33M" + }, + "type": "LIOB33" + }, + "LIOI3_SING_X0Y0": { + "bits": {}, + "grid_x": 1, + "grid_y": 207, + "sites": { + "IDELAY_X0Y0": "IDELAYE2", + "ILOGIC_X0Y0": "ILOGICE3", + "OLOGIC_X0Y0": "OLOGICE3" + }, + "type": "LIOI3_SING" + }, + "LIOI3_SING_X0Y100": { + "bits": {}, + "grid_x": 1, + "grid_y": 103, + "sites": { + "IDELAY_X0Y100": "IDELAYE2", + "ILOGIC_X0Y100": "ILOGICE3", + "OLOGIC_X0Y100": "OLOGICE3" + }, + "type": "LIOI3_SING" + }, + "LIOI3_SING_X0Y149": { + "bits": {}, + "grid_x": 1, + "grid_y": 53, + "sites": { + "IDELAY_X0Y149": "IDELAYE2", + "ILOGIC_X0Y149": "ILOGICE3", + "OLOGIC_X0Y149": "OLOGICE3" + }, + "type": "LIOI3_SING" + }, + "LIOI3_SING_X0Y150": { + "bits": {}, + "grid_x": 1, + "grid_y": 51, + "sites": { + "IDELAY_X0Y150": "IDELAYE2", + "ILOGIC_X0Y150": "ILOGICE3", + "OLOGIC_X0Y150": "OLOGICE3" + }, + "type": "LIOI3_SING" + }, + "LIOI3_SING_X0Y199": { + "bits": {}, + "grid_x": 1, + "grid_y": 1, + "sites": { + "IDELAY_X0Y199": "IDELAYE2", + "ILOGIC_X0Y199": "ILOGICE3", + "OLOGIC_X0Y199": "OLOGICE3" + }, + "type": "LIOI3_SING" + }, + "LIOI3_SING_X0Y49": { + "bits": {}, + "grid_x": 1, + "grid_y": 157, + "sites": { + "IDELAY_X0Y49": "IDELAYE2", + "ILOGIC_X0Y49": "ILOGICE3", + "OLOGIC_X0Y49": "OLOGICE3" + }, + "type": "LIOI3_SING" + }, + "LIOI3_SING_X0Y50": { + "bits": {}, + "grid_x": 1, + "grid_y": 155, + "sites": { + "IDELAY_X0Y50": "IDELAYE2", + "ILOGIC_X0Y50": "ILOGICE3", + "OLOGIC_X0Y50": "OLOGICE3" + }, + "type": "LIOI3_SING" + }, + "LIOI3_SING_X0Y99": { + "bits": {}, + "grid_x": 1, + "grid_y": 105, + "sites": { + "IDELAY_X0Y99": "IDELAYE2", + "ILOGIC_X0Y99": "ILOGICE3", + "OLOGIC_X0Y99": "OLOGICE3" + }, + "type": "LIOI3_SING" + }, + "LIOI3_TBYTESRC_X0Y107": { + "bits": {}, + "grid_x": 1, + "grid_y": 96, + "sites": { + "IDELAY_X0Y107": "IDELAYE2", + "IDELAY_X0Y108": "IDELAYE2", + "ILOGIC_X0Y107": "ILOGICE3", + "ILOGIC_X0Y108": "ILOGICE3", + "OLOGIC_X0Y107": "OLOGICE3", + "OLOGIC_X0Y108": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y119": { + "bits": {}, + "grid_x": 1, + "grid_y": 84, + "sites": { + "IDELAY_X0Y119": "IDELAYE2", + "IDELAY_X0Y120": "IDELAYE2", + "ILOGIC_X0Y119": "ILOGICE3", + "ILOGIC_X0Y120": "ILOGICE3", + "OLOGIC_X0Y119": "OLOGICE3", + "OLOGIC_X0Y120": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y131": { + "bits": {}, + "grid_x": 1, + "grid_y": 71, + "sites": { + "IDELAY_X0Y131": "IDELAYE2", + "IDELAY_X0Y132": "IDELAYE2", + "ILOGIC_X0Y131": "ILOGICE3", + "ILOGIC_X0Y132": "ILOGICE3", + "OLOGIC_X0Y131": "OLOGICE3", + "OLOGIC_X0Y132": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y143": { + "bits": {}, + "grid_x": 1, + "grid_y": 59, + "sites": { + "IDELAY_X0Y143": "IDELAYE2", + "IDELAY_X0Y144": "IDELAYE2", + "ILOGIC_X0Y143": "ILOGICE3", + "ILOGIC_X0Y144": "ILOGICE3", + "OLOGIC_X0Y143": "OLOGICE3", + "OLOGIC_X0Y144": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y157": { + "bits": {}, + "grid_x": 1, + "grid_y": 44, + "sites": { + "IDELAY_X0Y157": "IDELAYE2", + "IDELAY_X0Y158": "IDELAYE2", + "ILOGIC_X0Y157": "ILOGICE3", + "ILOGIC_X0Y158": "ILOGICE3", + "OLOGIC_X0Y157": "OLOGICE3", + "OLOGIC_X0Y158": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y169": { + "bits": {}, + "grid_x": 1, + "grid_y": 32, + "sites": { + "IDELAY_X0Y169": "IDELAYE2", + "IDELAY_X0Y170": "IDELAYE2", + "ILOGIC_X0Y169": "ILOGICE3", + "ILOGIC_X0Y170": "ILOGICE3", + "OLOGIC_X0Y169": "OLOGICE3", + "OLOGIC_X0Y170": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y181": { + "bits": {}, + "grid_x": 1, + "grid_y": 19, + "sites": { + "IDELAY_X0Y181": "IDELAYE2", + "IDELAY_X0Y182": "IDELAYE2", + "ILOGIC_X0Y181": "ILOGICE3", + "ILOGIC_X0Y182": "ILOGICE3", + "OLOGIC_X0Y181": "OLOGICE3", + "OLOGIC_X0Y182": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y19": { + "bits": {}, + "grid_x": 1, + "grid_y": 188, + "sites": { + "IDELAY_X0Y19": "IDELAYE2", + "IDELAY_X0Y20": "IDELAYE2", + "ILOGIC_X0Y19": "ILOGICE3", + "ILOGIC_X0Y20": "ILOGICE3", + "OLOGIC_X0Y19": "OLOGICE3", + "OLOGIC_X0Y20": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y193": { + "bits": {}, + "grid_x": 1, + "grid_y": 7, + "sites": { + "IDELAY_X0Y193": "IDELAYE2", + "IDELAY_X0Y194": "IDELAYE2", + "ILOGIC_X0Y193": "ILOGICE3", + "ILOGIC_X0Y194": "ILOGICE3", + "OLOGIC_X0Y193": "OLOGICE3", + "OLOGIC_X0Y194": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y31": { + "bits": {}, + "grid_x": 1, + "grid_y": 175, + "sites": { + "IDELAY_X0Y31": "IDELAYE2", + "IDELAY_X0Y32": "IDELAYE2", + "ILOGIC_X0Y31": "ILOGICE3", + "ILOGIC_X0Y32": "ILOGICE3", + "OLOGIC_X0Y31": "OLOGICE3", + "OLOGIC_X0Y32": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y43": { + "bits": {}, + "grid_x": 1, + "grid_y": 163, + "sites": { + "IDELAY_X0Y43": "IDELAYE2", + "IDELAY_X0Y44": "IDELAYE2", + "ILOGIC_X0Y43": "ILOGICE3", + "ILOGIC_X0Y44": "ILOGICE3", + "OLOGIC_X0Y43": "OLOGICE3", + "OLOGIC_X0Y44": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y57": { + "bits": {}, + "grid_x": 1, + "grid_y": 148, + "sites": { + "IDELAY_X0Y57": "IDELAYE2", + "IDELAY_X0Y58": "IDELAYE2", + "ILOGIC_X0Y57": "ILOGICE3", + "ILOGIC_X0Y58": "ILOGICE3", + "OLOGIC_X0Y57": "OLOGICE3", + "OLOGIC_X0Y58": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y69": { + "bits": {}, + "grid_x": 1, + "grid_y": 136, + "sites": { + "IDELAY_X0Y69": "IDELAYE2", + "IDELAY_X0Y70": "IDELAYE2", + "ILOGIC_X0Y69": "ILOGICE3", + "ILOGIC_X0Y70": "ILOGICE3", + "OLOGIC_X0Y69": "OLOGICE3", + "OLOGIC_X0Y70": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y7": { + "bits": {}, + "grid_x": 1, + "grid_y": 200, + "sites": { + "IDELAY_X0Y7": "IDELAYE2", + "IDELAY_X0Y8": "IDELAYE2", + "ILOGIC_X0Y7": "ILOGICE3", + "ILOGIC_X0Y8": "ILOGICE3", + "OLOGIC_X0Y7": "OLOGICE3", + "OLOGIC_X0Y8": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y81": { + "bits": {}, + "grid_x": 1, + "grid_y": 123, + "sites": { + "IDELAY_X0Y81": "IDELAYE2", + "IDELAY_X0Y82": "IDELAYE2", + "ILOGIC_X0Y81": "ILOGICE3", + "ILOGIC_X0Y82": "ILOGICE3", + "OLOGIC_X0Y81": "OLOGICE3", + "OLOGIC_X0Y82": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTESRC_X0Y93": { + "bits": {}, + "grid_x": 1, + "grid_y": 111, + "sites": { + "IDELAY_X0Y93": "IDELAYE2", + "IDELAY_X0Y94": "IDELAYE2", + "ILOGIC_X0Y93": "ILOGICE3", + "ILOGIC_X0Y94": "ILOGICE3", + "OLOGIC_X0Y93": "OLOGICE3", + "OLOGIC_X0Y94": "OLOGICE3" + }, + "type": "LIOI3_TBYTESRC" + }, + "LIOI3_TBYTETERM_X0Y113": { + "bits": {}, + "grid_x": 1, + "grid_y": 90, + "sites": { + "IDELAY_X0Y113": "IDELAYE2", + "IDELAY_X0Y114": "IDELAYE2", + "ILOGIC_X0Y113": "ILOGICE3", + "ILOGIC_X0Y114": "ILOGICE3", + "OLOGIC_X0Y113": "OLOGICE3", + "OLOGIC_X0Y114": "OLOGICE3" + }, + "type": "LIOI3_TBYTETERM" + }, + "LIOI3_TBYTETERM_X0Y13": { + "bits": {}, + "grid_x": 1, + "grid_y": 194, + "sites": { + "IDELAY_X0Y13": "IDELAYE2", + "IDELAY_X0Y14": "IDELAYE2", + "ILOGIC_X0Y13": "ILOGICE3", + "ILOGIC_X0Y14": "ILOGICE3", + "OLOGIC_X0Y13": "OLOGICE3", + "OLOGIC_X0Y14": "OLOGICE3" + }, + "type": "LIOI3_TBYTETERM" + }, + "LIOI3_TBYTETERM_X0Y137": { + "bits": {}, + "grid_x": 1, + "grid_y": 65, + "sites": { + "IDELAY_X0Y137": "IDELAYE2", + "IDELAY_X0Y138": "IDELAYE2", + "ILOGIC_X0Y137": "ILOGICE3", + "ILOGIC_X0Y138": "ILOGICE3", + "OLOGIC_X0Y137": "OLOGICE3", + "OLOGIC_X0Y138": "OLOGICE3" + }, + "type": "LIOI3_TBYTETERM" + }, + "LIOI3_TBYTETERM_X0Y163": { + "bits": {}, + "grid_x": 1, + "grid_y": 38, + "sites": { + "IDELAY_X0Y163": "IDELAYE2", + "IDELAY_X0Y164": "IDELAYE2", + "ILOGIC_X0Y163": "ILOGICE3", + "ILOGIC_X0Y164": "ILOGICE3", + "OLOGIC_X0Y163": "OLOGICE3", + "OLOGIC_X0Y164": "OLOGICE3" + }, + "type": "LIOI3_TBYTETERM" + }, + "LIOI3_TBYTETERM_X0Y187": { + "bits": {}, + "grid_x": 1, + "grid_y": 13, + "sites": { + "IDELAY_X0Y187": "IDELAYE2", + "IDELAY_X0Y188": "IDELAYE2", + "ILOGIC_X0Y187": "ILOGICE3", + "ILOGIC_X0Y188": "ILOGICE3", + "OLOGIC_X0Y187": "OLOGICE3", + "OLOGIC_X0Y188": "OLOGICE3" + }, + "type": "LIOI3_TBYTETERM" + }, + "LIOI3_TBYTETERM_X0Y37": { + "bits": {}, + "grid_x": 1, + "grid_y": 169, + "sites": { + "IDELAY_X0Y37": "IDELAYE2", + "IDELAY_X0Y38": "IDELAYE2", + "ILOGIC_X0Y37": "ILOGICE3", + "ILOGIC_X0Y38": "ILOGICE3", + "OLOGIC_X0Y37": "OLOGICE3", + "OLOGIC_X0Y38": "OLOGICE3" + }, + "type": "LIOI3_TBYTETERM" + }, + "LIOI3_TBYTETERM_X0Y63": { + "bits": {}, + "grid_x": 1, + "grid_y": 142, + "sites": { + "IDELAY_X0Y63": "IDELAYE2", + "IDELAY_X0Y64": "IDELAYE2", + "ILOGIC_X0Y63": "ILOGICE3", + "ILOGIC_X0Y64": "ILOGICE3", + "OLOGIC_X0Y63": "OLOGICE3", + "OLOGIC_X0Y64": "OLOGICE3" + }, + "type": "LIOI3_TBYTETERM" + }, + "LIOI3_TBYTETERM_X0Y87": { + "bits": {}, + "grid_x": 1, + "grid_y": 117, + "sites": { + "IDELAY_X0Y87": "IDELAYE2", + "IDELAY_X0Y88": "IDELAYE2", + "ILOGIC_X0Y87": "ILOGICE3", + "ILOGIC_X0Y88": "ILOGICE3", + "OLOGIC_X0Y87": "OLOGICE3", + "OLOGIC_X0Y88": "OLOGICE3" + }, + "type": "LIOI3_TBYTETERM" + }, + "LIOI3_X0Y1": { + "bits": {}, + "grid_x": 1, + "grid_y": 206, + "sites": { + "IDELAY_X0Y1": "IDELAYE2", + "IDELAY_X0Y2": "IDELAYE2", + "ILOGIC_X0Y1": "ILOGICE3", + "ILOGIC_X0Y2": "ILOGICE3", + "OLOGIC_X0Y1": "OLOGICE3", + "OLOGIC_X0Y2": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y101": { + "bits": {}, + "grid_x": 1, + "grid_y": 102, + "sites": { + "IDELAY_X0Y101": "IDELAYE2", + "IDELAY_X0Y102": "IDELAYE2", + "ILOGIC_X0Y101": "ILOGICE3", + "ILOGIC_X0Y102": "ILOGICE3", + "OLOGIC_X0Y101": "OLOGICE3", + "OLOGIC_X0Y102": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y103": { + "bits": {}, + "grid_x": 1, + "grid_y": 100, + "sites": { + "IDELAY_X0Y103": "IDELAYE2", + "IDELAY_X0Y104": "IDELAYE2", + "ILOGIC_X0Y103": "ILOGICE3", + "ILOGIC_X0Y104": "ILOGICE3", + "OLOGIC_X0Y103": "OLOGICE3", + "OLOGIC_X0Y104": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y105": { + "bits": {}, + "grid_x": 1, + "grid_y": 98, + "sites": { + "IDELAY_X0Y105": "IDELAYE2", + "IDELAY_X0Y106": "IDELAYE2", + "ILOGIC_X0Y105": "ILOGICE3", + "ILOGIC_X0Y106": "ILOGICE3", + "OLOGIC_X0Y105": "OLOGICE3", + "OLOGIC_X0Y106": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y109": { + "bits": {}, + "grid_x": 1, + "grid_y": 94, + "sites": { + "IDELAY_X0Y109": "IDELAYE2", + "IDELAY_X0Y110": "IDELAYE2", + "ILOGIC_X0Y109": "ILOGICE3", + "ILOGIC_X0Y110": "ILOGICE3", + "OLOGIC_X0Y109": "OLOGICE3", + "OLOGIC_X0Y110": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y11": { + "bits": {}, + "grid_x": 1, + "grid_y": 196, + "sites": { + "IDELAY_X0Y11": "IDELAYE2", + "IDELAY_X0Y12": "IDELAYE2", + "ILOGIC_X0Y11": "ILOGICE3", + "ILOGIC_X0Y12": "ILOGICE3", + "OLOGIC_X0Y11": "OLOGICE3", + "OLOGIC_X0Y12": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y111": { + "bits": {}, + "grid_x": 1, + "grid_y": 92, + "sites": { + "IDELAY_X0Y111": "IDELAYE2", + "IDELAY_X0Y112": "IDELAYE2", + "ILOGIC_X0Y111": "ILOGICE3", + "ILOGIC_X0Y112": "ILOGICE3", + "OLOGIC_X0Y111": "OLOGICE3", + "OLOGIC_X0Y112": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y115": { + "bits": {}, + "grid_x": 1, + "grid_y": 88, + "sites": { + "IDELAY_X0Y115": "IDELAYE2", + "IDELAY_X0Y116": "IDELAYE2", + "ILOGIC_X0Y115": "ILOGICE3", + "ILOGIC_X0Y116": "ILOGICE3", + "OLOGIC_X0Y115": "OLOGICE3", + "OLOGIC_X0Y116": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y117": { + "bits": {}, + "grid_x": 1, + "grid_y": 86, + "sites": { + "IDELAY_X0Y117": "IDELAYE2", + "IDELAY_X0Y118": "IDELAYE2", + "ILOGIC_X0Y117": "ILOGICE3", + "ILOGIC_X0Y118": "ILOGICE3", + "OLOGIC_X0Y117": "OLOGICE3", + "OLOGIC_X0Y118": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y121": { + "bits": {}, + "grid_x": 1, + "grid_y": 82, + "sites": { + "IDELAY_X0Y121": "IDELAYE2", + "IDELAY_X0Y122": "IDELAYE2", + "ILOGIC_X0Y121": "ILOGICE3", + "ILOGIC_X0Y122": "ILOGICE3", + "OLOGIC_X0Y121": "OLOGICE3", + "OLOGIC_X0Y122": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y123": { + "bits": {}, + "grid_x": 1, + "grid_y": 80, + "sites": { + "IDELAY_X0Y123": "IDELAYE2", + "IDELAY_X0Y124": "IDELAYE2", + "ILOGIC_X0Y123": "ILOGICE3", + "ILOGIC_X0Y124": "ILOGICE3", + "OLOGIC_X0Y123": "OLOGICE3", + "OLOGIC_X0Y124": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y125": { + "bits": {}, + "grid_x": 1, + "grid_y": 77, + "sites": { + "IDELAY_X0Y125": "IDELAYE2", + "IDELAY_X0Y126": "IDELAYE2", + "ILOGIC_X0Y125": "ILOGICE3", + "ILOGIC_X0Y126": "ILOGICE3", + "OLOGIC_X0Y125": "OLOGICE3", + "OLOGIC_X0Y126": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y127": { + "bits": {}, + "grid_x": 1, + "grid_y": 75, + "sites": { + "IDELAY_X0Y127": "IDELAYE2", + "IDELAY_X0Y128": "IDELAYE2", + "ILOGIC_X0Y127": "ILOGICE3", + "ILOGIC_X0Y128": "ILOGICE3", + "OLOGIC_X0Y127": "OLOGICE3", + "OLOGIC_X0Y128": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y129": { + "bits": {}, + "grid_x": 1, + "grid_y": 73, + "sites": { + "IDELAY_X0Y129": "IDELAYE2", + "IDELAY_X0Y130": "IDELAYE2", + "ILOGIC_X0Y129": "ILOGICE3", + "ILOGIC_X0Y130": "ILOGICE3", + "OLOGIC_X0Y129": "OLOGICE3", + "OLOGIC_X0Y130": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y133": { + "bits": {}, + "grid_x": 1, + "grid_y": 69, + "sites": { + "IDELAY_X0Y133": "IDELAYE2", + "IDELAY_X0Y134": "IDELAYE2", + "ILOGIC_X0Y133": "ILOGICE3", + "ILOGIC_X0Y134": "ILOGICE3", + "OLOGIC_X0Y133": "OLOGICE3", + "OLOGIC_X0Y134": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y135": { + "bits": {}, + "grid_x": 1, + "grid_y": 67, + "sites": { + "IDELAY_X0Y135": "IDELAYE2", + "IDELAY_X0Y136": "IDELAYE2", + "ILOGIC_X0Y135": "ILOGICE3", + "ILOGIC_X0Y136": "ILOGICE3", + "OLOGIC_X0Y135": "OLOGICE3", + "OLOGIC_X0Y136": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y139": { + "bits": {}, + "grid_x": 1, + "grid_y": 63, + "sites": { + "IDELAY_X0Y139": "IDELAYE2", + "IDELAY_X0Y140": "IDELAYE2", + "ILOGIC_X0Y139": "ILOGICE3", + "ILOGIC_X0Y140": "ILOGICE3", + "OLOGIC_X0Y139": "OLOGICE3", + "OLOGIC_X0Y140": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y141": { + "bits": {}, + "grid_x": 1, + "grid_y": 61, + "sites": { + "IDELAY_X0Y141": "IDELAYE2", + "IDELAY_X0Y142": "IDELAYE2", + "ILOGIC_X0Y141": "ILOGICE3", + "ILOGIC_X0Y142": "ILOGICE3", + "OLOGIC_X0Y141": "OLOGICE3", + "OLOGIC_X0Y142": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y145": { + "bits": {}, + "grid_x": 1, + "grid_y": 57, + "sites": { + "IDELAY_X0Y145": "IDELAYE2", + "IDELAY_X0Y146": "IDELAYE2", + "ILOGIC_X0Y145": "ILOGICE3", + "ILOGIC_X0Y146": "ILOGICE3", + "OLOGIC_X0Y145": "OLOGICE3", + "OLOGIC_X0Y146": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y147": { + "bits": {}, + "grid_x": 1, + "grid_y": 55, + "sites": { + "IDELAY_X0Y147": "IDELAYE2", + "IDELAY_X0Y148": "IDELAYE2", + "ILOGIC_X0Y147": "ILOGICE3", + "ILOGIC_X0Y148": "ILOGICE3", + "OLOGIC_X0Y147": "OLOGICE3", + "OLOGIC_X0Y148": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y15": { + "bits": {}, + "grid_x": 1, + "grid_y": 192, + "sites": { + "IDELAY_X0Y15": "IDELAYE2", + "IDELAY_X0Y16": "IDELAYE2", + "ILOGIC_X0Y15": "ILOGICE3", + "ILOGIC_X0Y16": "ILOGICE3", + "OLOGIC_X0Y15": "OLOGICE3", + "OLOGIC_X0Y16": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y151": { + "bits": {}, + "grid_x": 1, + "grid_y": 50, + "sites": { + "IDELAY_X0Y151": "IDELAYE2", + "IDELAY_X0Y152": "IDELAYE2", + "ILOGIC_X0Y151": "ILOGICE3", + "ILOGIC_X0Y152": "ILOGICE3", + "OLOGIC_X0Y151": "OLOGICE3", + "OLOGIC_X0Y152": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y153": { + "bits": {}, + "grid_x": 1, + "grid_y": 48, + "sites": { + "IDELAY_X0Y153": "IDELAYE2", + "IDELAY_X0Y154": "IDELAYE2", + "ILOGIC_X0Y153": "ILOGICE3", + "ILOGIC_X0Y154": "ILOGICE3", + "OLOGIC_X0Y153": "OLOGICE3", + "OLOGIC_X0Y154": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y155": { + "bits": {}, + "grid_x": 1, + "grid_y": 46, + "sites": { + "IDELAY_X0Y155": "IDELAYE2", + "IDELAY_X0Y156": "IDELAYE2", + "ILOGIC_X0Y155": "ILOGICE3", + "ILOGIC_X0Y156": "ILOGICE3", + "OLOGIC_X0Y155": "OLOGICE3", + "OLOGIC_X0Y156": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y159": { + "bits": {}, + "grid_x": 1, + "grid_y": 42, + "sites": { + "IDELAY_X0Y159": "IDELAYE2", + "IDELAY_X0Y160": "IDELAYE2", + "ILOGIC_X0Y159": "ILOGICE3", + "ILOGIC_X0Y160": "ILOGICE3", + "OLOGIC_X0Y159": "OLOGICE3", + "OLOGIC_X0Y160": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y161": { + "bits": {}, + "grid_x": 1, + "grid_y": 40, + "sites": { + "IDELAY_X0Y161": "IDELAYE2", + "IDELAY_X0Y162": "IDELAYE2", + "ILOGIC_X0Y161": "ILOGICE3", + "ILOGIC_X0Y162": "ILOGICE3", + "OLOGIC_X0Y161": "OLOGICE3", + "OLOGIC_X0Y162": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y165": { + "bits": {}, + "grid_x": 1, + "grid_y": 36, + "sites": { + "IDELAY_X0Y165": "IDELAYE2", + "IDELAY_X0Y166": "IDELAYE2", + "ILOGIC_X0Y165": "ILOGICE3", + "ILOGIC_X0Y166": "ILOGICE3", + "OLOGIC_X0Y165": "OLOGICE3", + "OLOGIC_X0Y166": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y167": { + "bits": {}, + "grid_x": 1, + "grid_y": 34, + "sites": { + "IDELAY_X0Y167": "IDELAYE2", + "IDELAY_X0Y168": "IDELAYE2", + "ILOGIC_X0Y167": "ILOGICE3", + "ILOGIC_X0Y168": "ILOGICE3", + "OLOGIC_X0Y167": "OLOGICE3", + "OLOGIC_X0Y168": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y17": { + "bits": {}, + "grid_x": 1, + "grid_y": 190, + "sites": { + "IDELAY_X0Y17": "IDELAYE2", + "IDELAY_X0Y18": "IDELAYE2", + "ILOGIC_X0Y17": "ILOGICE3", + "ILOGIC_X0Y18": "ILOGICE3", + "OLOGIC_X0Y17": "OLOGICE3", + "OLOGIC_X0Y18": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y171": { + "bits": {}, + "grid_x": 1, + "grid_y": 30, + "sites": { + "IDELAY_X0Y171": "IDELAYE2", + "IDELAY_X0Y172": "IDELAYE2", + "ILOGIC_X0Y171": "ILOGICE3", + "ILOGIC_X0Y172": "ILOGICE3", + "OLOGIC_X0Y171": "OLOGICE3", + "OLOGIC_X0Y172": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y173": { + "bits": {}, + "grid_x": 1, + "grid_y": 28, + "sites": { + "IDELAY_X0Y173": "IDELAYE2", + "IDELAY_X0Y174": "IDELAYE2", + "ILOGIC_X0Y173": "ILOGICE3", + "ILOGIC_X0Y174": "ILOGICE3", + "OLOGIC_X0Y173": "OLOGICE3", + "OLOGIC_X0Y174": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y175": { + "bits": {}, + "grid_x": 1, + "grid_y": 25, + "sites": { + "IDELAY_X0Y175": "IDELAYE2", + "IDELAY_X0Y176": "IDELAYE2", + "ILOGIC_X0Y175": "ILOGICE3", + "ILOGIC_X0Y176": "ILOGICE3", + "OLOGIC_X0Y175": "OLOGICE3", + "OLOGIC_X0Y176": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y177": { + "bits": {}, + "grid_x": 1, + "grid_y": 23, + "sites": { + "IDELAY_X0Y177": "IDELAYE2", + "IDELAY_X0Y178": "IDELAYE2", + "ILOGIC_X0Y177": "ILOGICE3", + "ILOGIC_X0Y178": "ILOGICE3", + "OLOGIC_X0Y177": "OLOGICE3", + "OLOGIC_X0Y178": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y179": { + "bits": {}, + "grid_x": 1, + "grid_y": 21, + "sites": { + "IDELAY_X0Y179": "IDELAYE2", + "IDELAY_X0Y180": "IDELAYE2", + "ILOGIC_X0Y179": "ILOGICE3", + "ILOGIC_X0Y180": "ILOGICE3", + "OLOGIC_X0Y179": "OLOGICE3", + "OLOGIC_X0Y180": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y183": { + "bits": {}, + "grid_x": 1, + "grid_y": 17, + "sites": { + "IDELAY_X0Y183": "IDELAYE2", + "IDELAY_X0Y184": "IDELAYE2", + "ILOGIC_X0Y183": "ILOGICE3", + "ILOGIC_X0Y184": "ILOGICE3", + "OLOGIC_X0Y183": "OLOGICE3", + "OLOGIC_X0Y184": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y185": { + "bits": {}, + "grid_x": 1, + "grid_y": 15, + "sites": { + "IDELAY_X0Y185": "IDELAYE2", + "IDELAY_X0Y186": "IDELAYE2", + "ILOGIC_X0Y185": "ILOGICE3", + "ILOGIC_X0Y186": "ILOGICE3", + "OLOGIC_X0Y185": "OLOGICE3", + "OLOGIC_X0Y186": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y189": { + "bits": {}, + "grid_x": 1, + "grid_y": 11, + "sites": { + "IDELAY_X0Y189": "IDELAYE2", + "IDELAY_X0Y190": "IDELAYE2", + "ILOGIC_X0Y189": "ILOGICE3", + "ILOGIC_X0Y190": "ILOGICE3", + "OLOGIC_X0Y189": "OLOGICE3", + "OLOGIC_X0Y190": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y191": { + "bits": {}, + "grid_x": 1, + "grid_y": 9, + "sites": { + "IDELAY_X0Y191": "IDELAYE2", + "IDELAY_X0Y192": "IDELAYE2", + "ILOGIC_X0Y191": "ILOGICE3", + "ILOGIC_X0Y192": "ILOGICE3", + "OLOGIC_X0Y191": "OLOGICE3", + "OLOGIC_X0Y192": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y195": { + "bits": {}, + "grid_x": 1, + "grid_y": 5, + "sites": { + "IDELAY_X0Y195": "IDELAYE2", + "IDELAY_X0Y196": "IDELAYE2", + "ILOGIC_X0Y195": "ILOGICE3", + "ILOGIC_X0Y196": "ILOGICE3", + "OLOGIC_X0Y195": "OLOGICE3", + "OLOGIC_X0Y196": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y197": { + "bits": {}, + "grid_x": 1, + "grid_y": 3, + "sites": { + "IDELAY_X0Y197": "IDELAYE2", + "IDELAY_X0Y198": "IDELAYE2", + "ILOGIC_X0Y197": "ILOGICE3", + "ILOGIC_X0Y198": "ILOGICE3", + "OLOGIC_X0Y197": "OLOGICE3", + "OLOGIC_X0Y198": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y21": { + "bits": {}, + "grid_x": 1, + "grid_y": 186, + "sites": { + "IDELAY_X0Y21": "IDELAYE2", + "IDELAY_X0Y22": "IDELAYE2", + "ILOGIC_X0Y21": "ILOGICE3", + "ILOGIC_X0Y22": "ILOGICE3", + "OLOGIC_X0Y21": "OLOGICE3", + "OLOGIC_X0Y22": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y23": { + "bits": {}, + "grid_x": 1, + "grid_y": 184, + "sites": { + "IDELAY_X0Y23": "IDELAYE2", + "IDELAY_X0Y24": "IDELAYE2", + "ILOGIC_X0Y23": "ILOGICE3", + "ILOGIC_X0Y24": "ILOGICE3", + "OLOGIC_X0Y23": "OLOGICE3", + "OLOGIC_X0Y24": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y25": { + "bits": {}, + "grid_x": 1, + "grid_y": 181, + "sites": { + "IDELAY_X0Y25": "IDELAYE2", + "IDELAY_X0Y26": "IDELAYE2", + "ILOGIC_X0Y25": "ILOGICE3", + "ILOGIC_X0Y26": "ILOGICE3", + "OLOGIC_X0Y25": "OLOGICE3", + "OLOGIC_X0Y26": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y27": { + "bits": {}, + "grid_x": 1, + "grid_y": 179, + "sites": { + "IDELAY_X0Y27": "IDELAYE2", + "IDELAY_X0Y28": "IDELAYE2", + "ILOGIC_X0Y27": "ILOGICE3", + "ILOGIC_X0Y28": "ILOGICE3", + "OLOGIC_X0Y27": "OLOGICE3", + "OLOGIC_X0Y28": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y29": { + "bits": {}, + "grid_x": 1, + "grid_y": 177, + "sites": { + "IDELAY_X0Y29": "IDELAYE2", + "IDELAY_X0Y30": "IDELAYE2", + "ILOGIC_X0Y29": "ILOGICE3", + "ILOGIC_X0Y30": "ILOGICE3", + "OLOGIC_X0Y29": "OLOGICE3", + "OLOGIC_X0Y30": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y3": { + "bits": {}, + "grid_x": 1, + "grid_y": 204, + "sites": { + "IDELAY_X0Y3": "IDELAYE2", + "IDELAY_X0Y4": "IDELAYE2", + "ILOGIC_X0Y3": "ILOGICE3", + "ILOGIC_X0Y4": "ILOGICE3", + "OLOGIC_X0Y3": "OLOGICE3", + "OLOGIC_X0Y4": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y33": { + "bits": {}, + "grid_x": 1, + "grid_y": 173, + "sites": { + "IDELAY_X0Y33": "IDELAYE2", + "IDELAY_X0Y34": "IDELAYE2", + "ILOGIC_X0Y33": "ILOGICE3", + "ILOGIC_X0Y34": "ILOGICE3", + "OLOGIC_X0Y33": "OLOGICE3", + "OLOGIC_X0Y34": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y35": { + "bits": {}, + "grid_x": 1, + "grid_y": 171, + "sites": { + "IDELAY_X0Y35": "IDELAYE2", + "IDELAY_X0Y36": "IDELAYE2", + "ILOGIC_X0Y35": "ILOGICE3", + "ILOGIC_X0Y36": "ILOGICE3", + "OLOGIC_X0Y35": "OLOGICE3", + "OLOGIC_X0Y36": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y39": { + "bits": {}, + "grid_x": 1, + "grid_y": 167, + "sites": { + "IDELAY_X0Y39": "IDELAYE2", + "IDELAY_X0Y40": "IDELAYE2", + "ILOGIC_X0Y39": "ILOGICE3", + "ILOGIC_X0Y40": "ILOGICE3", + "OLOGIC_X0Y39": "OLOGICE3", + "OLOGIC_X0Y40": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y41": { + "bits": {}, + "grid_x": 1, + "grid_y": 165, + "sites": { + "IDELAY_X0Y41": "IDELAYE2", + "IDELAY_X0Y42": "IDELAYE2", + "ILOGIC_X0Y41": "ILOGICE3", + "ILOGIC_X0Y42": "ILOGICE3", + "OLOGIC_X0Y41": "OLOGICE3", + "OLOGIC_X0Y42": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y45": { + "bits": {}, + "grid_x": 1, + "grid_y": 161, + "sites": { + "IDELAY_X0Y45": "IDELAYE2", + "IDELAY_X0Y46": "IDELAYE2", + "ILOGIC_X0Y45": "ILOGICE3", + "ILOGIC_X0Y46": "ILOGICE3", + "OLOGIC_X0Y45": "OLOGICE3", + "OLOGIC_X0Y46": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y47": { + "bits": {}, + "grid_x": 1, + "grid_y": 159, + "sites": { + "IDELAY_X0Y47": "IDELAYE2", + "IDELAY_X0Y48": "IDELAYE2", + "ILOGIC_X0Y47": "ILOGICE3", + "ILOGIC_X0Y48": "ILOGICE3", + "OLOGIC_X0Y47": "OLOGICE3", + "OLOGIC_X0Y48": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y5": { + "bits": {}, + "grid_x": 1, + "grid_y": 202, + "sites": { + "IDELAY_X0Y5": "IDELAYE2", + "IDELAY_X0Y6": "IDELAYE2", + "ILOGIC_X0Y5": "ILOGICE3", + "ILOGIC_X0Y6": "ILOGICE3", + "OLOGIC_X0Y5": "OLOGICE3", + "OLOGIC_X0Y6": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y51": { + "bits": {}, + "grid_x": 1, + "grid_y": 154, + "sites": { + "IDELAY_X0Y51": "IDELAYE2", + "IDELAY_X0Y52": "IDELAYE2", + "ILOGIC_X0Y51": "ILOGICE3", + "ILOGIC_X0Y52": "ILOGICE3", + "OLOGIC_X0Y51": "OLOGICE3", + "OLOGIC_X0Y52": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y53": { + "bits": {}, + "grid_x": 1, + "grid_y": 152, + "sites": { + "IDELAY_X0Y53": "IDELAYE2", + "IDELAY_X0Y54": "IDELAYE2", + "ILOGIC_X0Y53": "ILOGICE3", + "ILOGIC_X0Y54": "ILOGICE3", + "OLOGIC_X0Y53": "OLOGICE3", + "OLOGIC_X0Y54": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y55": { + "bits": {}, + "grid_x": 1, + "grid_y": 150, + "sites": { + "IDELAY_X0Y55": "IDELAYE2", + "IDELAY_X0Y56": "IDELAYE2", + "ILOGIC_X0Y55": "ILOGICE3", + "ILOGIC_X0Y56": "ILOGICE3", + "OLOGIC_X0Y55": "OLOGICE3", + "OLOGIC_X0Y56": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y59": { + "bits": {}, + "grid_x": 1, + "grid_y": 146, + "sites": { + "IDELAY_X0Y59": "IDELAYE2", + "IDELAY_X0Y60": "IDELAYE2", + "ILOGIC_X0Y59": "ILOGICE3", + "ILOGIC_X0Y60": "ILOGICE3", + "OLOGIC_X0Y59": "OLOGICE3", + "OLOGIC_X0Y60": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y61": { + "bits": {}, + "grid_x": 1, + "grid_y": 144, + "sites": { + "IDELAY_X0Y61": "IDELAYE2", + "IDELAY_X0Y62": "IDELAYE2", + "ILOGIC_X0Y61": "ILOGICE3", + "ILOGIC_X0Y62": "ILOGICE3", + "OLOGIC_X0Y61": "OLOGICE3", + "OLOGIC_X0Y62": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y65": { + "bits": {}, + "grid_x": 1, + "grid_y": 140, + "sites": { + "IDELAY_X0Y65": "IDELAYE2", + "IDELAY_X0Y66": "IDELAYE2", + "ILOGIC_X0Y65": "ILOGICE3", + "ILOGIC_X0Y66": "ILOGICE3", + "OLOGIC_X0Y65": "OLOGICE3", + "OLOGIC_X0Y66": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y67": { + "bits": {}, + "grid_x": 1, + "grid_y": 138, + "sites": { + "IDELAY_X0Y67": "IDELAYE2", + "IDELAY_X0Y68": "IDELAYE2", + "ILOGIC_X0Y67": "ILOGICE3", + "ILOGIC_X0Y68": "ILOGICE3", + "OLOGIC_X0Y67": "OLOGICE3", + "OLOGIC_X0Y68": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y71": { + "bits": {}, + "grid_x": 1, + "grid_y": 134, + "sites": { + "IDELAY_X0Y71": "IDELAYE2", + "IDELAY_X0Y72": "IDELAYE2", + "ILOGIC_X0Y71": "ILOGICE3", + "ILOGIC_X0Y72": "ILOGICE3", + "OLOGIC_X0Y71": "OLOGICE3", + "OLOGIC_X0Y72": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y73": { + "bits": {}, + "grid_x": 1, + "grid_y": 132, + "sites": { + "IDELAY_X0Y73": "IDELAYE2", + "IDELAY_X0Y74": "IDELAYE2", + "ILOGIC_X0Y73": "ILOGICE3", + "ILOGIC_X0Y74": "ILOGICE3", + "OLOGIC_X0Y73": "OLOGICE3", + "OLOGIC_X0Y74": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y75": { + "bits": {}, + "grid_x": 1, + "grid_y": 129, + "sites": { + "IDELAY_X0Y75": "IDELAYE2", + "IDELAY_X0Y76": "IDELAYE2", + "ILOGIC_X0Y75": "ILOGICE3", + "ILOGIC_X0Y76": "ILOGICE3", + "OLOGIC_X0Y75": "OLOGICE3", + "OLOGIC_X0Y76": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y77": { + "bits": {}, + "grid_x": 1, + "grid_y": 127, + "sites": { + "IDELAY_X0Y77": "IDELAYE2", + "IDELAY_X0Y78": "IDELAYE2", + "ILOGIC_X0Y77": "ILOGICE3", + "ILOGIC_X0Y78": "ILOGICE3", + "OLOGIC_X0Y77": "OLOGICE3", + "OLOGIC_X0Y78": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y79": { + "bits": {}, + "grid_x": 1, + "grid_y": 125, + "sites": { + "IDELAY_X0Y79": "IDELAYE2", + "IDELAY_X0Y80": "IDELAYE2", + "ILOGIC_X0Y79": "ILOGICE3", + "ILOGIC_X0Y80": "ILOGICE3", + "OLOGIC_X0Y79": "OLOGICE3", + "OLOGIC_X0Y80": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y83": { + "bits": {}, + "grid_x": 1, + "grid_y": 121, + "sites": { + "IDELAY_X0Y83": "IDELAYE2", + "IDELAY_X0Y84": "IDELAYE2", + "ILOGIC_X0Y83": "ILOGICE3", + "ILOGIC_X0Y84": "ILOGICE3", + "OLOGIC_X0Y83": "OLOGICE3", + "OLOGIC_X0Y84": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y85": { + "bits": {}, + "grid_x": 1, + "grid_y": 119, + "sites": { + "IDELAY_X0Y85": "IDELAYE2", + "IDELAY_X0Y86": "IDELAYE2", + "ILOGIC_X0Y85": "ILOGICE3", + "ILOGIC_X0Y86": "ILOGICE3", + "OLOGIC_X0Y85": "OLOGICE3", + "OLOGIC_X0Y86": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y89": { + "bits": {}, + "grid_x": 1, + "grid_y": 115, + "sites": { + "IDELAY_X0Y89": "IDELAYE2", + "IDELAY_X0Y90": "IDELAYE2", + "ILOGIC_X0Y89": "ILOGICE3", + "ILOGIC_X0Y90": "ILOGICE3", + "OLOGIC_X0Y89": "OLOGICE3", + "OLOGIC_X0Y90": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y9": { + "bits": {}, + "grid_x": 1, + "grid_y": 198, + "sites": { + "IDELAY_X0Y10": "IDELAYE2", + "IDELAY_X0Y9": "IDELAYE2", + "ILOGIC_X0Y10": "ILOGICE3", + "ILOGIC_X0Y9": "ILOGICE3", + "OLOGIC_X0Y10": "OLOGICE3", + "OLOGIC_X0Y9": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y91": { + "bits": {}, + "grid_x": 1, + "grid_y": 113, + "sites": { + "IDELAY_X0Y91": "IDELAYE2", + "IDELAY_X0Y92": "IDELAYE2", + "ILOGIC_X0Y91": "ILOGICE3", + "ILOGIC_X0Y92": "ILOGICE3", + "OLOGIC_X0Y91": "OLOGICE3", + "OLOGIC_X0Y92": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y95": { + "bits": {}, + "grid_x": 1, + "grid_y": 109, + "sites": { + "IDELAY_X0Y95": "IDELAYE2", + "IDELAY_X0Y96": "IDELAYE2", + "ILOGIC_X0Y95": "ILOGICE3", + "ILOGIC_X0Y96": "ILOGICE3", + "OLOGIC_X0Y95": "OLOGICE3", + "OLOGIC_X0Y96": "OLOGICE3" + }, + "type": "LIOI3" + }, + "LIOI3_X0Y97": { + "bits": {}, + "grid_x": 1, + "grid_y": 107, + "sites": { + "IDELAY_X0Y97": "IDELAYE2", + "IDELAY_X0Y98": "IDELAYE2", + "ILOGIC_X0Y97": "ILOGICE3", + "ILOGIC_X0Y98": "ILOGICE3", + "OLOGIC_X0Y97": "OLOGICE3", + "OLOGIC_X0Y98": "OLOGICE3" + }, + "type": "LIOI3" + }, + "L_TERM_INT_X2Y1": { + "bits": {}, + "grid_x": 2, + "grid_y": 207, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y10": { + "bits": {}, + "grid_x": 2, + "grid_y": 198, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y100": { + "bits": {}, + "grid_x": 2, + "grid_y": 108, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y101": { + "bits": {}, + "grid_x": 2, + "grid_y": 107, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y102": { + "bits": {}, + "grid_x": 2, + "grid_y": 106, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y103": { + "bits": {}, + "grid_x": 2, + "grid_y": 105, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y105": { + "bits": {}, + "grid_x": 2, + "grid_y": 103, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y106": { + "bits": {}, + "grid_x": 2, + "grid_y": 102, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y107": { + "bits": {}, + "grid_x": 2, + "grid_y": 101, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y108": { + "bits": {}, + "grid_x": 2, + "grid_y": 100, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y109": { + "bits": {}, + "grid_x": 2, + "grid_y": 99, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y11": { + "bits": {}, + "grid_x": 2, + "grid_y": 197, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y110": { + "bits": {}, + "grid_x": 2, + "grid_y": 98, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y111": { + "bits": {}, + "grid_x": 2, + "grid_y": 97, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y112": { + "bits": {}, + "grid_x": 2, + "grid_y": 96, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y113": { + "bits": {}, + "grid_x": 2, + "grid_y": 95, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y114": { + "bits": {}, + "grid_x": 2, + "grid_y": 94, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y115": { + "bits": {}, + "grid_x": 2, + "grid_y": 93, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y116": { + "bits": {}, + "grid_x": 2, + "grid_y": 92, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y117": { + "bits": {}, + "grid_x": 2, + "grid_y": 91, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y118": { + "bits": {}, + "grid_x": 2, + "grid_y": 90, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y119": { + "bits": {}, + "grid_x": 2, + "grid_y": 89, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y12": { + "bits": {}, + "grid_x": 2, + "grid_y": 196, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y120": { + "bits": {}, + "grid_x": 2, + "grid_y": 88, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y121": { + "bits": {}, + "grid_x": 2, + "grid_y": 87, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y122": { + "bits": {}, + "grid_x": 2, + "grid_y": 86, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y123": { + "bits": {}, + "grid_x": 2, + "grid_y": 85, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y124": { + "bits": {}, + "grid_x": 2, + "grid_y": 84, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y125": { + "bits": {}, + "grid_x": 2, + "grid_y": 83, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y126": { + "bits": {}, + "grid_x": 2, + "grid_y": 82, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y127": { + "bits": {}, + "grid_x": 2, + "grid_y": 81, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y128": { + "bits": {}, + "grid_x": 2, + "grid_y": 80, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y129": { + "bits": {}, + "grid_x": 2, + "grid_y": 79, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y13": { + "bits": {}, + "grid_x": 2, + "grid_y": 195, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y131": { + "bits": {}, + "grid_x": 2, + "grid_y": 77, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y132": { + "bits": {}, + "grid_x": 2, + "grid_y": 76, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y133": { + "bits": {}, + "grid_x": 2, + "grid_y": 75, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y134": { + "bits": {}, + "grid_x": 2, + "grid_y": 74, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y135": { + "bits": {}, + "grid_x": 2, + "grid_y": 73, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y136": { + "bits": {}, + "grid_x": 2, + "grid_y": 72, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y137": { + "bits": {}, + "grid_x": 2, + "grid_y": 71, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y138": { + "bits": {}, + "grid_x": 2, + "grid_y": 70, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y139": { + "bits": {}, + "grid_x": 2, + "grid_y": 69, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y14": { + "bits": {}, + "grid_x": 2, + "grid_y": 194, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y140": { + "bits": {}, + "grid_x": 2, + "grid_y": 68, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y141": { + "bits": {}, + "grid_x": 2, + "grid_y": 67, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y142": { + "bits": {}, + "grid_x": 2, + "grid_y": 66, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y143": { + "bits": {}, + "grid_x": 2, + "grid_y": 65, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y144": { + "bits": {}, + "grid_x": 2, + "grid_y": 64, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y145": { + "bits": {}, + "grid_x": 2, + "grid_y": 63, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y146": { + "bits": {}, + "grid_x": 2, + "grid_y": 62, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y147": { + "bits": {}, + "grid_x": 2, + "grid_y": 61, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y148": { + "bits": {}, + "grid_x": 2, + "grid_y": 60, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y149": { + "bits": {}, + "grid_x": 2, + "grid_y": 59, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y15": { + "bits": {}, + "grid_x": 2, + "grid_y": 193, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y150": { + "bits": {}, + "grid_x": 2, + "grid_y": 58, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y151": { + "bits": {}, + "grid_x": 2, + "grid_y": 57, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y152": { + "bits": {}, + "grid_x": 2, + "grid_y": 56, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y153": { + "bits": {}, + "grid_x": 2, + "grid_y": 55, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y154": { + "bits": {}, + "grid_x": 2, + "grid_y": 54, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y155": { + "bits": {}, + "grid_x": 2, + "grid_y": 53, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y157": { + "bits": {}, + "grid_x": 2, + "grid_y": 51, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y158": { + "bits": {}, + "grid_x": 2, + "grid_y": 50, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y159": { + "bits": {}, + "grid_x": 2, + "grid_y": 49, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y16": { + "bits": {}, + "grid_x": 2, + "grid_y": 192, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y160": { + "bits": {}, + "grid_x": 2, + "grid_y": 48, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y161": { + "bits": {}, + "grid_x": 2, + "grid_y": 47, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y162": { + "bits": {}, + "grid_x": 2, + "grid_y": 46, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y163": { + "bits": {}, + "grid_x": 2, + "grid_y": 45, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y164": { + "bits": {}, + "grid_x": 2, + "grid_y": 44, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y165": { + "bits": {}, + "grid_x": 2, + "grid_y": 43, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y166": { + "bits": {}, + "grid_x": 2, + "grid_y": 42, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y167": { + "bits": {}, + "grid_x": 2, + "grid_y": 41, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y168": { + "bits": {}, + "grid_x": 2, + "grid_y": 40, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y169": { + "bits": {}, + "grid_x": 2, + "grid_y": 39, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y17": { + "bits": {}, + "grid_x": 2, + "grid_y": 191, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y170": { + "bits": {}, + "grid_x": 2, + "grid_y": 38, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y171": { + "bits": {}, + "grid_x": 2, + "grid_y": 37, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y172": { + "bits": {}, + "grid_x": 2, + "grid_y": 36, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y173": { + "bits": {}, + "grid_x": 2, + "grid_y": 35, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y174": { + "bits": {}, + "grid_x": 2, + "grid_y": 34, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y175": { + "bits": {}, + "grid_x": 2, + "grid_y": 33, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y176": { + "bits": {}, + "grid_x": 2, + "grid_y": 32, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y177": { + "bits": {}, + "grid_x": 2, + "grid_y": 31, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y178": { + "bits": {}, + "grid_x": 2, + "grid_y": 30, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y179": { + "bits": {}, + "grid_x": 2, + "grid_y": 29, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y18": { + "bits": {}, + "grid_x": 2, + "grid_y": 190, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y180": { + "bits": {}, + "grid_x": 2, + "grid_y": 28, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y181": { + "bits": {}, + "grid_x": 2, + "grid_y": 27, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y183": { + "bits": {}, + "grid_x": 2, + "grid_y": 25, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y184": { + "bits": {}, + "grid_x": 2, + "grid_y": 24, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y185": { + "bits": {}, + "grid_x": 2, + "grid_y": 23, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y186": { + "bits": {}, + "grid_x": 2, + "grid_y": 22, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y187": { + "bits": {}, + "grid_x": 2, + "grid_y": 21, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y188": { + "bits": {}, + "grid_x": 2, + "grid_y": 20, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y189": { + "bits": {}, + "grid_x": 2, + "grid_y": 19, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y19": { + "bits": {}, + "grid_x": 2, + "grid_y": 189, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y190": { + "bits": {}, + "grid_x": 2, + "grid_y": 18, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y191": { + "bits": {}, + "grid_x": 2, + "grid_y": 17, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y192": { + "bits": {}, + "grid_x": 2, + "grid_y": 16, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y193": { + "bits": {}, + "grid_x": 2, + "grid_y": 15, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y194": { + "bits": {}, + "grid_x": 2, + "grid_y": 14, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y195": { + "bits": {}, + "grid_x": 2, + "grid_y": 13, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y196": { + "bits": {}, + "grid_x": 2, + "grid_y": 12, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y197": { + "bits": {}, + "grid_x": 2, + "grid_y": 11, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y198": { + "bits": {}, + "grid_x": 2, + "grid_y": 10, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y199": { + "bits": {}, + "grid_x": 2, + "grid_y": 9, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y2": { + "bits": {}, + "grid_x": 2, + "grid_y": 206, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y20": { + "bits": {}, + "grid_x": 2, + "grid_y": 188, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y200": { + "bits": {}, + "grid_x": 2, + "grid_y": 8, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y201": { + "bits": {}, + "grid_x": 2, + "grid_y": 7, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y202": { + "bits": {}, + "grid_x": 2, + "grid_y": 6, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y203": { + "bits": {}, + "grid_x": 2, + "grid_y": 5, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y204": { + "bits": {}, + "grid_x": 2, + "grid_y": 4, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y205": { + "bits": {}, + "grid_x": 2, + "grid_y": 3, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y206": { + "bits": {}, + "grid_x": 2, + "grid_y": 2, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y207": { + "bits": {}, + "grid_x": 2, + "grid_y": 1, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y21": { + "bits": {}, + "grid_x": 2, + "grid_y": 187, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y22": { + "bits": {}, + "grid_x": 2, + "grid_y": 186, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y23": { + "bits": {}, + "grid_x": 2, + "grid_y": 185, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y24": { + "bits": {}, + "grid_x": 2, + "grid_y": 184, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y25": { + "bits": {}, + "grid_x": 2, + "grid_y": 183, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y27": { + "bits": {}, + "grid_x": 2, + "grid_y": 181, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y28": { + "bits": {}, + "grid_x": 2, + "grid_y": 180, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y29": { + "bits": {}, + "grid_x": 2, + "grid_y": 179, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y3": { + "bits": {}, + "grid_x": 2, + "grid_y": 205, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y30": { + "bits": {}, + "grid_x": 2, + "grid_y": 178, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y31": { + "bits": {}, + "grid_x": 2, + "grid_y": 177, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y32": { + "bits": {}, + "grid_x": 2, + "grid_y": 176, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y33": { + "bits": {}, + "grid_x": 2, + "grid_y": 175, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y34": { + "bits": {}, + "grid_x": 2, + "grid_y": 174, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y35": { + "bits": {}, + "grid_x": 2, + "grid_y": 173, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y36": { + "bits": {}, + "grid_x": 2, + "grid_y": 172, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y37": { + "bits": {}, + "grid_x": 2, + "grid_y": 171, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y38": { + "bits": {}, + "grid_x": 2, + "grid_y": 170, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y39": { + "bits": {}, + "grid_x": 2, + "grid_y": 169, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y4": { + "bits": {}, + "grid_x": 2, + "grid_y": 204, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y40": { + "bits": {}, + "grid_x": 2, + "grid_y": 168, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y41": { + "bits": {}, + "grid_x": 2, + "grid_y": 167, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y42": { + "bits": {}, + "grid_x": 2, + "grid_y": 166, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y43": { + "bits": {}, + "grid_x": 2, + "grid_y": 165, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y44": { + "bits": {}, + "grid_x": 2, + "grid_y": 164, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y45": { + "bits": {}, + "grid_x": 2, + "grid_y": 163, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y46": { + "bits": {}, + "grid_x": 2, + "grid_y": 162, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y47": { + "bits": {}, + "grid_x": 2, + "grid_y": 161, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y48": { + "bits": {}, + "grid_x": 2, + "grid_y": 160, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y49": { + "bits": {}, + "grid_x": 2, + "grid_y": 159, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y5": { + "bits": {}, + "grid_x": 2, + "grid_y": 203, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y50": { + "bits": {}, + "grid_x": 2, + "grid_y": 158, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y51": { + "bits": {}, + "grid_x": 2, + "grid_y": 157, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y53": { + "bits": {}, + "grid_x": 2, + "grid_y": 155, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y54": { + "bits": {}, + "grid_x": 2, + "grid_y": 154, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y55": { + "bits": {}, + "grid_x": 2, + "grid_y": 153, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y56": { + "bits": {}, + "grid_x": 2, + "grid_y": 152, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y57": { + "bits": {}, + "grid_x": 2, + "grid_y": 151, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y58": { + "bits": {}, + "grid_x": 2, + "grid_y": 150, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y59": { + "bits": {}, + "grid_x": 2, + "grid_y": 149, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y6": { + "bits": {}, + "grid_x": 2, + "grid_y": 202, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y60": { + "bits": {}, + "grid_x": 2, + "grid_y": 148, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y61": { + "bits": {}, + "grid_x": 2, + "grid_y": 147, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y62": { + "bits": {}, + "grid_x": 2, + "grid_y": 146, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y63": { + "bits": {}, + "grid_x": 2, + "grid_y": 145, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y64": { + "bits": {}, + "grid_x": 2, + "grid_y": 144, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y65": { + "bits": {}, + "grid_x": 2, + "grid_y": 143, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y66": { + "bits": {}, + "grid_x": 2, + "grid_y": 142, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y67": { + "bits": {}, + "grid_x": 2, + "grid_y": 141, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y68": { + "bits": {}, + "grid_x": 2, + "grid_y": 140, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y69": { + "bits": {}, + "grid_x": 2, + "grid_y": 139, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y7": { + "bits": {}, + "grid_x": 2, + "grid_y": 201, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y70": { + "bits": {}, + "grid_x": 2, + "grid_y": 138, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y71": { + "bits": {}, + "grid_x": 2, + "grid_y": 137, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y72": { + "bits": {}, + "grid_x": 2, + "grid_y": 136, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y73": { + "bits": {}, + "grid_x": 2, + "grid_y": 135, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y74": { + "bits": {}, + "grid_x": 2, + "grid_y": 134, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y75": { + "bits": {}, + "grid_x": 2, + "grid_y": 133, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y76": { + "bits": {}, + "grid_x": 2, + "grid_y": 132, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y77": { + "bits": {}, + "grid_x": 2, + "grid_y": 131, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y79": { + "bits": {}, + "grid_x": 2, + "grid_y": 129, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y8": { + "bits": {}, + "grid_x": 2, + "grid_y": 200, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y80": { + "bits": {}, + "grid_x": 2, + "grid_y": 128, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y81": { + "bits": {}, + "grid_x": 2, + "grid_y": 127, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y82": { + "bits": {}, + "grid_x": 2, + "grid_y": 126, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y83": { + "bits": {}, + "grid_x": 2, + "grid_y": 125, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y84": { + "bits": {}, + "grid_x": 2, + "grid_y": 124, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y85": { + "bits": {}, + "grid_x": 2, + "grid_y": 123, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y86": { + "bits": {}, + "grid_x": 2, + "grid_y": 122, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y87": { + "bits": {}, + "grid_x": 2, + "grid_y": 121, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y88": { + "bits": {}, + "grid_x": 2, + "grid_y": 120, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y89": { + "bits": {}, + "grid_x": 2, + "grid_y": 119, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y9": { + "bits": {}, + "grid_x": 2, + "grid_y": 199, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y90": { + "bits": {}, + "grid_x": 2, + "grid_y": 118, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y91": { + "bits": {}, + "grid_x": 2, + "grid_y": 117, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y92": { + "bits": {}, + "grid_x": 2, + "grid_y": 116, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y93": { + "bits": {}, + "grid_x": 2, + "grid_y": 115, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y94": { + "bits": {}, + "grid_x": 2, + "grid_y": 114, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y95": { + "bits": {}, + "grid_x": 2, + "grid_y": 113, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y96": { + "bits": {}, + "grid_x": 2, + "grid_y": 112, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y97": { + "bits": {}, + "grid_x": 2, + "grid_y": 111, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y98": { + "bits": {}, + "grid_x": 2, + "grid_y": 110, + "sites": {}, + "type": "L_TERM_INT" + }, + "L_TERM_INT_X2Y99": { + "bits": {}, + "grid_x": 2, + "grid_y": 109, + "sites": {}, + "type": "L_TERM_INT" + }, + "MONITOR_BOT_FUJI2_X61Y131": { + "bits": {}, + "grid_x": 61, + "grid_y": 77, + "sites": { + "IPAD_X0Y66": "IPAD", + "IPAD_X0Y67": "IPAD", + "XADC_X0Y0": "XADC" + }, + "type": "MONITOR_BOT_FUJI2" + }, + "MONITOR_MID_FUJI2_X61Y141": { + "bits": {}, + "grid_x": 61, + "grid_y": 67, + "sites": {}, + "type": "MONITOR_MID_FUJI2" + }, + "MONITOR_TOP_FUJI2_X61Y151": { + "bits": {}, + "grid_x": 61, + "grid_y": 57, + "sites": {}, + "type": "MONITOR_TOP_FUJI2" + }, + "NULL_X0Y0": { + "bits": {}, + "grid_x": 0, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y100": { + "bits": {}, + "grid_x": 0, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y102": { + "bits": {}, + "grid_x": 0, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y104": { + "bits": {}, + "grid_x": 0, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y107": { + "bits": {}, + "grid_x": 0, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y109": { + "bits": {}, + "grid_x": 0, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y11": { + "bits": {}, + "grid_x": 0, + "grid_y": 197, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y111": { + "bits": {}, + "grid_x": 0, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y113": { + "bits": {}, + "grid_x": 0, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y115": { + "bits": {}, + "grid_x": 0, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y117": { + "bits": {}, + "grid_x": 0, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y119": { + "bits": {}, + "grid_x": 0, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y121": { + "bits": {}, + "grid_x": 0, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y123": { + "bits": {}, + "grid_x": 0, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y125": { + "bits": {}, + "grid_x": 0, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y127": { + "bits": {}, + "grid_x": 0, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y129": { + "bits": {}, + "grid_x": 0, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y13": { + "bits": {}, + "grid_x": 0, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y132": { + "bits": {}, + "grid_x": 0, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y134": { + "bits": {}, + "grid_x": 0, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y136": { + "bits": {}, + "grid_x": 0, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y138": { + "bits": {}, + "grid_x": 0, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y140": { + "bits": {}, + "grid_x": 0, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y142": { + "bits": {}, + "grid_x": 0, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y144": { + "bits": {}, + "grid_x": 0, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y146": { + "bits": {}, + "grid_x": 0, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y148": { + "bits": {}, + "grid_x": 0, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y15": { + "bits": {}, + "grid_x": 0, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y150": { + "bits": {}, + "grid_x": 0, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y152": { + "bits": {}, + "grid_x": 0, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y154": { + "bits": {}, + "grid_x": 0, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y156": { + "bits": {}, + "grid_x": 0, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y159": { + "bits": {}, + "grid_x": 0, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y161": { + "bits": {}, + "grid_x": 0, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y163": { + "bits": {}, + "grid_x": 0, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y165": { + "bits": {}, + "grid_x": 0, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y167": { + "bits": {}, + "grid_x": 0, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y169": { + "bits": {}, + "grid_x": 0, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y17": { + "bits": {}, + "grid_x": 0, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y171": { + "bits": {}, + "grid_x": 0, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y173": { + "bits": {}, + "grid_x": 0, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y175": { + "bits": {}, + "grid_x": 0, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y177": { + "bits": {}, + "grid_x": 0, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y179": { + "bits": {}, + "grid_x": 0, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y181": { + "bits": {}, + "grid_x": 0, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y184": { + "bits": {}, + "grid_x": 0, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y186": { + "bits": {}, + "grid_x": 0, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y188": { + "bits": {}, + "grid_x": 0, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y19": { + "bits": {}, + "grid_x": 0, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y190": { + "bits": {}, + "grid_x": 0, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y192": { + "bits": {}, + "grid_x": 0, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y194": { + "bits": {}, + "grid_x": 0, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y196": { + "bits": {}, + "grid_x": 0, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y198": { + "bits": {}, + "grid_x": 0, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y200": { + "bits": {}, + "grid_x": 0, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y202": { + "bits": {}, + "grid_x": 0, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y204": { + "bits": {}, + "grid_x": 0, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y206": { + "bits": {}, + "grid_x": 0, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y208": { + "bits": {}, + "grid_x": 0, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y21": { + "bits": {}, + "grid_x": 0, + "grid_y": 187, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y23": { + "bits": {}, + "grid_x": 0, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y25": { + "bits": {}, + "grid_x": 0, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y28": { + "bits": {}, + "grid_x": 0, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y3": { + "bits": {}, + "grid_x": 0, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y30": { + "bits": {}, + "grid_x": 0, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y32": { + "bits": {}, + "grid_x": 0, + "grid_y": 176, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y34": { + "bits": {}, + "grid_x": 0, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y36": { + "bits": {}, + "grid_x": 0, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y38": { + "bits": {}, + "grid_x": 0, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y40": { + "bits": {}, + "grid_x": 0, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y42": { + "bits": {}, + "grid_x": 0, + "grid_y": 166, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y44": { + "bits": {}, + "grid_x": 0, + "grid_y": 164, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y46": { + "bits": {}, + "grid_x": 0, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y48": { + "bits": {}, + "grid_x": 0, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y5": { + "bits": {}, + "grid_x": 0, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y50": { + "bits": {}, + "grid_x": 0, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y52": { + "bits": {}, + "grid_x": 0, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y55": { + "bits": {}, + "grid_x": 0, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y57": { + "bits": {}, + "grid_x": 0, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y59": { + "bits": {}, + "grid_x": 0, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y61": { + "bits": {}, + "grid_x": 0, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y63": { + "bits": {}, + "grid_x": 0, + "grid_y": 145, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y65": { + "bits": {}, + "grid_x": 0, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y67": { + "bits": {}, + "grid_x": 0, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y69": { + "bits": {}, + "grid_x": 0, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y7": { + "bits": {}, + "grid_x": 0, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y71": { + "bits": {}, + "grid_x": 0, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y73": { + "bits": {}, + "grid_x": 0, + "grid_y": 135, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y75": { + "bits": {}, + "grid_x": 0, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y77": { + "bits": {}, + "grid_x": 0, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y80": { + "bits": {}, + "grid_x": 0, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y82": { + "bits": {}, + "grid_x": 0, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y84": { + "bits": {}, + "grid_x": 0, + "grid_y": 124, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y86": { + "bits": {}, + "grid_x": 0, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y88": { + "bits": {}, + "grid_x": 0, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y9": { + "bits": {}, + "grid_x": 0, + "grid_y": 199, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y90": { + "bits": {}, + "grid_x": 0, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y92": { + "bits": {}, + "grid_x": 0, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y94": { + "bits": {}, + "grid_x": 0, + "grid_y": 114, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y96": { + "bits": {}, + "grid_x": 0, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X0Y98": { + "bits": {}, + "grid_x": 0, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y105": { + "bits": {}, + "grid_x": 100, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y106": { + "bits": {}, + "grid_x": 100, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y107": { + "bits": {}, + "grid_x": 100, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y108": { + "bits": {}, + "grid_x": 100, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y109": { + "bits": {}, + "grid_x": 100, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y110": { + "bits": {}, + "grid_x": 100, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y111": { + "bits": {}, + "grid_x": 100, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y112": { + "bits": {}, + "grid_x": 100, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y113": { + "bits": {}, + "grid_x": 100, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y114": { + "bits": {}, + "grid_x": 100, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y115": { + "bits": {}, + "grid_x": 100, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y116": { + "bits": {}, + "grid_x": 100, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y117": { + "bits": {}, + "grid_x": 100, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y118": { + "bits": {}, + "grid_x": 100, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y119": { + "bits": {}, + "grid_x": 100, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y120": { + "bits": {}, + "grid_x": 100, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y121": { + "bits": {}, + "grid_x": 100, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y122": { + "bits": {}, + "grid_x": 100, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y123": { + "bits": {}, + "grid_x": 100, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y124": { + "bits": {}, + "grid_x": 100, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y125": { + "bits": {}, + "grid_x": 100, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y126": { + "bits": {}, + "grid_x": 100, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y127": { + "bits": {}, + "grid_x": 100, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y128": { + "bits": {}, + "grid_x": 100, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y129": { + "bits": {}, + "grid_x": 100, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y130": { + "bits": {}, + "grid_x": 100, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y131": { + "bits": {}, + "grid_x": 100, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y132": { + "bits": {}, + "grid_x": 100, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y133": { + "bits": {}, + "grid_x": 100, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y134": { + "bits": {}, + "grid_x": 100, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y135": { + "bits": {}, + "grid_x": 100, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y136": { + "bits": {}, + "grid_x": 100, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y137": { + "bits": {}, + "grid_x": 100, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y138": { + "bits": {}, + "grid_x": 100, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y139": { + "bits": {}, + "grid_x": 100, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y140": { + "bits": {}, + "grid_x": 100, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y141": { + "bits": {}, + "grid_x": 100, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y142": { + "bits": {}, + "grid_x": 100, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y143": { + "bits": {}, + "grid_x": 100, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y144": { + "bits": {}, + "grid_x": 100, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y145": { + "bits": {}, + "grid_x": 100, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y146": { + "bits": {}, + "grid_x": 100, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y147": { + "bits": {}, + "grid_x": 100, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y148": { + "bits": {}, + "grid_x": 100, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y149": { + "bits": {}, + "grid_x": 100, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y150": { + "bits": {}, + "grid_x": 100, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y151": { + "bits": {}, + "grid_x": 100, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y152": { + "bits": {}, + "grid_x": 100, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y153": { + "bits": {}, + "grid_x": 100, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y154": { + "bits": {}, + "grid_x": 100, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y155": { + "bits": {}, + "grid_x": 100, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y156": { + "bits": {}, + "grid_x": 100, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y157": { + "bits": {}, + "grid_x": 100, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y158": { + "bits": {}, + "grid_x": 100, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y159": { + "bits": {}, + "grid_x": 100, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y160": { + "bits": {}, + "grid_x": 100, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y161": { + "bits": {}, + "grid_x": 100, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y162": { + "bits": {}, + "grid_x": 100, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y163": { + "bits": {}, + "grid_x": 100, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y164": { + "bits": {}, + "grid_x": 100, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y165": { + "bits": {}, + "grid_x": 100, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y166": { + "bits": {}, + "grid_x": 100, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y167": { + "bits": {}, + "grid_x": 100, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y168": { + "bits": {}, + "grid_x": 100, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y169": { + "bits": {}, + "grid_x": 100, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y170": { + "bits": {}, + "grid_x": 100, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y171": { + "bits": {}, + "grid_x": 100, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y172": { + "bits": {}, + "grid_x": 100, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y173": { + "bits": {}, + "grid_x": 100, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y174": { + "bits": {}, + "grid_x": 100, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y175": { + "bits": {}, + "grid_x": 100, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y176": { + "bits": {}, + "grid_x": 100, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y177": { + "bits": {}, + "grid_x": 100, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y178": { + "bits": {}, + "grid_x": 100, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y179": { + "bits": {}, + "grid_x": 100, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y180": { + "bits": {}, + "grid_x": 100, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y181": { + "bits": {}, + "grid_x": 100, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y182": { + "bits": {}, + "grid_x": 100, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y183": { + "bits": {}, + "grid_x": 100, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y184": { + "bits": {}, + "grid_x": 100, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y185": { + "bits": {}, + "grid_x": 100, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y186": { + "bits": {}, + "grid_x": 100, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y187": { + "bits": {}, + "grid_x": 100, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y188": { + "bits": {}, + "grid_x": 100, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y189": { + "bits": {}, + "grid_x": 100, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y190": { + "bits": {}, + "grid_x": 100, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y191": { + "bits": {}, + "grid_x": 100, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y192": { + "bits": {}, + "grid_x": 100, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y193": { + "bits": {}, + "grid_x": 100, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y194": { + "bits": {}, + "grid_x": 100, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y195": { + "bits": {}, + "grid_x": 100, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y196": { + "bits": {}, + "grid_x": 100, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y197": { + "bits": {}, + "grid_x": 100, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y198": { + "bits": {}, + "grid_x": 100, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y199": { + "bits": {}, + "grid_x": 100, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y200": { + "bits": {}, + "grid_x": 100, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y201": { + "bits": {}, + "grid_x": 100, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y202": { + "bits": {}, + "grid_x": 100, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y203": { + "bits": {}, + "grid_x": 100, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y204": { + "bits": {}, + "grid_x": 100, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y205": { + "bits": {}, + "grid_x": 100, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y206": { + "bits": {}, + "grid_x": 100, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y207": { + "bits": {}, + "grid_x": 100, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X100Y208": { + "bits": {}, + "grid_x": 100, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y105": { + "bits": {}, + "grid_x": 101, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y106": { + "bits": {}, + "grid_x": 101, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y107": { + "bits": {}, + "grid_x": 101, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y108": { + "bits": {}, + "grid_x": 101, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y109": { + "bits": {}, + "grid_x": 101, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y110": { + "bits": {}, + "grid_x": 101, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y111": { + "bits": {}, + "grid_x": 101, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y112": { + "bits": {}, + "grid_x": 101, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y113": { + "bits": {}, + "grid_x": 101, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y114": { + "bits": {}, + "grid_x": 101, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y115": { + "bits": {}, + "grid_x": 101, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y116": { + "bits": {}, + "grid_x": 101, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y117": { + "bits": {}, + "grid_x": 101, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y118": { + "bits": {}, + "grid_x": 101, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y119": { + "bits": {}, + "grid_x": 101, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y120": { + "bits": {}, + "grid_x": 101, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y121": { + "bits": {}, + "grid_x": 101, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y122": { + "bits": {}, + "grid_x": 101, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y123": { + "bits": {}, + "grid_x": 101, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y124": { + "bits": {}, + "grid_x": 101, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y125": { + "bits": {}, + "grid_x": 101, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y126": { + "bits": {}, + "grid_x": 101, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y127": { + "bits": {}, + "grid_x": 101, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y128": { + "bits": {}, + "grid_x": 101, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y129": { + "bits": {}, + "grid_x": 101, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y130": { + "bits": {}, + "grid_x": 101, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y131": { + "bits": {}, + "grid_x": 101, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y132": { + "bits": {}, + "grid_x": 101, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y133": { + "bits": {}, + "grid_x": 101, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y134": { + "bits": {}, + "grid_x": 101, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y135": { + "bits": {}, + "grid_x": 101, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y136": { + "bits": {}, + "grid_x": 101, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y137": { + "bits": {}, + "grid_x": 101, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y138": { + "bits": {}, + "grid_x": 101, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y139": { + "bits": {}, + "grid_x": 101, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y140": { + "bits": {}, + "grid_x": 101, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y141": { + "bits": {}, + "grid_x": 101, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y142": { + "bits": {}, + "grid_x": 101, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y143": { + "bits": {}, + "grid_x": 101, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y144": { + "bits": {}, + "grid_x": 101, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y145": { + "bits": {}, + "grid_x": 101, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y146": { + "bits": {}, + "grid_x": 101, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y147": { + "bits": {}, + "grid_x": 101, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y148": { + "bits": {}, + "grid_x": 101, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y149": { + "bits": {}, + "grid_x": 101, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y150": { + "bits": {}, + "grid_x": 101, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y151": { + "bits": {}, + "grid_x": 101, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y152": { + "bits": {}, + "grid_x": 101, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y153": { + "bits": {}, + "grid_x": 101, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y154": { + "bits": {}, + "grid_x": 101, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y155": { + "bits": {}, + "grid_x": 101, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y156": { + "bits": {}, + "grid_x": 101, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y157": { + "bits": {}, + "grid_x": 101, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y158": { + "bits": {}, + "grid_x": 101, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y159": { + "bits": {}, + "grid_x": 101, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y160": { + "bits": {}, + "grid_x": 101, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y161": { + "bits": {}, + "grid_x": 101, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y162": { + "bits": {}, + "grid_x": 101, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y163": { + "bits": {}, + "grid_x": 101, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y164": { + "bits": {}, + "grid_x": 101, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y165": { + "bits": {}, + "grid_x": 101, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y166": { + "bits": {}, + "grid_x": 101, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y167": { + "bits": {}, + "grid_x": 101, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y168": { + "bits": {}, + "grid_x": 101, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y169": { + "bits": {}, + "grid_x": 101, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y170": { + "bits": {}, + "grid_x": 101, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y171": { + "bits": {}, + "grid_x": 101, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y172": { + "bits": {}, + "grid_x": 101, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y173": { + "bits": {}, + "grid_x": 101, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y174": { + "bits": {}, + "grid_x": 101, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y175": { + "bits": {}, + "grid_x": 101, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y176": { + "bits": {}, + "grid_x": 101, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y177": { + "bits": {}, + "grid_x": 101, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y178": { + "bits": {}, + "grid_x": 101, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y179": { + "bits": {}, + "grid_x": 101, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y180": { + "bits": {}, + "grid_x": 101, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y181": { + "bits": {}, + "grid_x": 101, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y182": { + "bits": {}, + "grid_x": 101, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y183": { + "bits": {}, + "grid_x": 101, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y184": { + "bits": {}, + "grid_x": 101, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y185": { + "bits": {}, + "grid_x": 101, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y186": { + "bits": {}, + "grid_x": 101, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y187": { + "bits": {}, + "grid_x": 101, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y188": { + "bits": {}, + "grid_x": 101, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y189": { + "bits": {}, + "grid_x": 101, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y190": { + "bits": {}, + "grid_x": 101, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y191": { + "bits": {}, + "grid_x": 101, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y192": { + "bits": {}, + "grid_x": 101, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y193": { + "bits": {}, + "grid_x": 101, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y194": { + "bits": {}, + "grid_x": 101, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y195": { + "bits": {}, + "grid_x": 101, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y196": { + "bits": {}, + "grid_x": 101, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y197": { + "bits": {}, + "grid_x": 101, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y198": { + "bits": {}, + "grid_x": 101, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y199": { + "bits": {}, + "grid_x": 101, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y200": { + "bits": {}, + "grid_x": 101, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y201": { + "bits": {}, + "grid_x": 101, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y202": { + "bits": {}, + "grid_x": 101, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y203": { + "bits": {}, + "grid_x": 101, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y204": { + "bits": {}, + "grid_x": 101, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y205": { + "bits": {}, + "grid_x": 101, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y206": { + "bits": {}, + "grid_x": 101, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y207": { + "bits": {}, + "grid_x": 101, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X101Y208": { + "bits": {}, + "grid_x": 101, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y0": { + "bits": {}, + "grid_x": 102, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y104": { + "bits": {}, + "grid_x": 102, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y105": { + "bits": {}, + "grid_x": 102, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y106": { + "bits": {}, + "grid_x": 102, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y107": { + "bits": {}, + "grid_x": 102, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y108": { + "bits": {}, + "grid_x": 102, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y109": { + "bits": {}, + "grid_x": 102, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y110": { + "bits": {}, + "grid_x": 102, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y111": { + "bits": {}, + "grid_x": 102, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y112": { + "bits": {}, + "grid_x": 102, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y113": { + "bits": {}, + "grid_x": 102, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y114": { + "bits": {}, + "grid_x": 102, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y115": { + "bits": {}, + "grid_x": 102, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y116": { + "bits": {}, + "grid_x": 102, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y117": { + "bits": {}, + "grid_x": 102, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y118": { + "bits": {}, + "grid_x": 102, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y119": { + "bits": {}, + "grid_x": 102, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y120": { + "bits": {}, + "grid_x": 102, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y121": { + "bits": {}, + "grid_x": 102, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y122": { + "bits": {}, + "grid_x": 102, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y123": { + "bits": {}, + "grid_x": 102, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y124": { + "bits": {}, + "grid_x": 102, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y125": { + "bits": {}, + "grid_x": 102, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y126": { + "bits": {}, + "grid_x": 102, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y127": { + "bits": {}, + "grid_x": 102, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y128": { + "bits": {}, + "grid_x": 102, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y129": { + "bits": {}, + "grid_x": 102, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y130": { + "bits": {}, + "grid_x": 102, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y131": { + "bits": {}, + "grid_x": 102, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y132": { + "bits": {}, + "grid_x": 102, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y133": { + "bits": {}, + "grid_x": 102, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y134": { + "bits": {}, + "grid_x": 102, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y135": { + "bits": {}, + "grid_x": 102, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y136": { + "bits": {}, + "grid_x": 102, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y137": { + "bits": {}, + "grid_x": 102, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y138": { + "bits": {}, + "grid_x": 102, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y139": { + "bits": {}, + "grid_x": 102, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y140": { + "bits": {}, + "grid_x": 102, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y141": { + "bits": {}, + "grid_x": 102, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y142": { + "bits": {}, + "grid_x": 102, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y143": { + "bits": {}, + "grid_x": 102, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y144": { + "bits": {}, + "grid_x": 102, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y145": { + "bits": {}, + "grid_x": 102, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y146": { + "bits": {}, + "grid_x": 102, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y147": { + "bits": {}, + "grid_x": 102, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y148": { + "bits": {}, + "grid_x": 102, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y149": { + "bits": {}, + "grid_x": 102, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y150": { + "bits": {}, + "grid_x": 102, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y151": { + "bits": {}, + "grid_x": 102, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y152": { + "bits": {}, + "grid_x": 102, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y153": { + "bits": {}, + "grid_x": 102, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y154": { + "bits": {}, + "grid_x": 102, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y155": { + "bits": {}, + "grid_x": 102, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y156": { + "bits": {}, + "grid_x": 102, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y157": { + "bits": {}, + "grid_x": 102, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y158": { + "bits": {}, + "grid_x": 102, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y159": { + "bits": {}, + "grid_x": 102, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y160": { + "bits": {}, + "grid_x": 102, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y161": { + "bits": {}, + "grid_x": 102, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y162": { + "bits": {}, + "grid_x": 102, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y163": { + "bits": {}, + "grid_x": 102, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y164": { + "bits": {}, + "grid_x": 102, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y165": { + "bits": {}, + "grid_x": 102, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y166": { + "bits": {}, + "grid_x": 102, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y167": { + "bits": {}, + "grid_x": 102, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y168": { + "bits": {}, + "grid_x": 102, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y169": { + "bits": {}, + "grid_x": 102, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y170": { + "bits": {}, + "grid_x": 102, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y171": { + "bits": {}, + "grid_x": 102, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y172": { + "bits": {}, + "grid_x": 102, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y173": { + "bits": {}, + "grid_x": 102, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y174": { + "bits": {}, + "grid_x": 102, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y175": { + "bits": {}, + "grid_x": 102, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y176": { + "bits": {}, + "grid_x": 102, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y177": { + "bits": {}, + "grid_x": 102, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y178": { + "bits": {}, + "grid_x": 102, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y179": { + "bits": {}, + "grid_x": 102, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y180": { + "bits": {}, + "grid_x": 102, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y181": { + "bits": {}, + "grid_x": 102, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y182": { + "bits": {}, + "grid_x": 102, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y183": { + "bits": {}, + "grid_x": 102, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y184": { + "bits": {}, + "grid_x": 102, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y185": { + "bits": {}, + "grid_x": 102, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y186": { + "bits": {}, + "grid_x": 102, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y187": { + "bits": {}, + "grid_x": 102, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y188": { + "bits": {}, + "grid_x": 102, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y189": { + "bits": {}, + "grid_x": 102, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y190": { + "bits": {}, + "grid_x": 102, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y191": { + "bits": {}, + "grid_x": 102, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y192": { + "bits": {}, + "grid_x": 102, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y193": { + "bits": {}, + "grid_x": 102, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y194": { + "bits": {}, + "grid_x": 102, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y195": { + "bits": {}, + "grid_x": 102, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y196": { + "bits": {}, + "grid_x": 102, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y197": { + "bits": {}, + "grid_x": 102, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y198": { + "bits": {}, + "grid_x": 102, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y199": { + "bits": {}, + "grid_x": 102, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y200": { + "bits": {}, + "grid_x": 102, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y201": { + "bits": {}, + "grid_x": 102, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y202": { + "bits": {}, + "grid_x": 102, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y203": { + "bits": {}, + "grid_x": 102, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y204": { + "bits": {}, + "grid_x": 102, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y205": { + "bits": {}, + "grid_x": 102, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y206": { + "bits": {}, + "grid_x": 102, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y207": { + "bits": {}, + "grid_x": 102, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X102Y208": { + "bits": {}, + "grid_x": 102, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y0": { + "bits": {}, + "grid_x": 103, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y104": { + "bits": {}, + "grid_x": 103, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y105": { + "bits": {}, + "grid_x": 103, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y106": { + "bits": {}, + "grid_x": 103, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y107": { + "bits": {}, + "grid_x": 103, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y108": { + "bits": {}, + "grid_x": 103, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y109": { + "bits": {}, + "grid_x": 103, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y110": { + "bits": {}, + "grid_x": 103, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y111": { + "bits": {}, + "grid_x": 103, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y112": { + "bits": {}, + "grid_x": 103, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y113": { + "bits": {}, + "grid_x": 103, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y114": { + "bits": {}, + "grid_x": 103, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y115": { + "bits": {}, + "grid_x": 103, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y116": { + "bits": {}, + "grid_x": 103, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y117": { + "bits": {}, + "grid_x": 103, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y118": { + "bits": {}, + "grid_x": 103, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y119": { + "bits": {}, + "grid_x": 103, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y120": { + "bits": {}, + "grid_x": 103, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y121": { + "bits": {}, + "grid_x": 103, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y122": { + "bits": {}, + "grid_x": 103, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y123": { + "bits": {}, + "grid_x": 103, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y124": { + "bits": {}, + "grid_x": 103, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y125": { + "bits": {}, + "grid_x": 103, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y126": { + "bits": {}, + "grid_x": 103, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y127": { + "bits": {}, + "grid_x": 103, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y128": { + "bits": {}, + "grid_x": 103, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y129": { + "bits": {}, + "grid_x": 103, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y130": { + "bits": {}, + "grid_x": 103, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y131": { + "bits": {}, + "grid_x": 103, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y132": { + "bits": {}, + "grid_x": 103, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y133": { + "bits": {}, + "grid_x": 103, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y134": { + "bits": {}, + "grid_x": 103, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y135": { + "bits": {}, + "grid_x": 103, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y136": { + "bits": {}, + "grid_x": 103, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y137": { + "bits": {}, + "grid_x": 103, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y138": { + "bits": {}, + "grid_x": 103, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y139": { + "bits": {}, + "grid_x": 103, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y140": { + "bits": {}, + "grid_x": 103, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y141": { + "bits": {}, + "grid_x": 103, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y142": { + "bits": {}, + "grid_x": 103, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y143": { + "bits": {}, + "grid_x": 103, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y144": { + "bits": {}, + "grid_x": 103, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y145": { + "bits": {}, + "grid_x": 103, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y146": { + "bits": {}, + "grid_x": 103, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y147": { + "bits": {}, + "grid_x": 103, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y148": { + "bits": {}, + "grid_x": 103, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y149": { + "bits": {}, + "grid_x": 103, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y150": { + "bits": {}, + "grid_x": 103, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y151": { + "bits": {}, + "grid_x": 103, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y152": { + "bits": {}, + "grid_x": 103, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y153": { + "bits": {}, + "grid_x": 103, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y154": { + "bits": {}, + "grid_x": 103, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y155": { + "bits": {}, + "grid_x": 103, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y156": { + "bits": {}, + "grid_x": 103, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y157": { + "bits": {}, + "grid_x": 103, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y158": { + "bits": {}, + "grid_x": 103, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y159": { + "bits": {}, + "grid_x": 103, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y160": { + "bits": {}, + "grid_x": 103, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y161": { + "bits": {}, + "grid_x": 103, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y162": { + "bits": {}, + "grid_x": 103, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y163": { + "bits": {}, + "grid_x": 103, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y164": { + "bits": {}, + "grid_x": 103, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y165": { + "bits": {}, + "grid_x": 103, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y166": { + "bits": {}, + "grid_x": 103, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y167": { + "bits": {}, + "grid_x": 103, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y168": { + "bits": {}, + "grid_x": 103, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y169": { + "bits": {}, + "grid_x": 103, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y170": { + "bits": {}, + "grid_x": 103, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y171": { + "bits": {}, + "grid_x": 103, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y172": { + "bits": {}, + "grid_x": 103, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y173": { + "bits": {}, + "grid_x": 103, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y174": { + "bits": {}, + "grid_x": 103, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y175": { + "bits": {}, + "grid_x": 103, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y176": { + "bits": {}, + "grid_x": 103, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y177": { + "bits": {}, + "grid_x": 103, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y178": { + "bits": {}, + "grid_x": 103, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y179": { + "bits": {}, + "grid_x": 103, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y180": { + "bits": {}, + "grid_x": 103, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y181": { + "bits": {}, + "grid_x": 103, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y182": { + "bits": {}, + "grid_x": 103, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y183": { + "bits": {}, + "grid_x": 103, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y184": { + "bits": {}, + "grid_x": 103, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y185": { + "bits": {}, + "grid_x": 103, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y186": { + "bits": {}, + "grid_x": 103, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y187": { + "bits": {}, + "grid_x": 103, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y188": { + "bits": {}, + "grid_x": 103, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y189": { + "bits": {}, + "grid_x": 103, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y190": { + "bits": {}, + "grid_x": 103, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y191": { + "bits": {}, + "grid_x": 103, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y192": { + "bits": {}, + "grid_x": 103, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y193": { + "bits": {}, + "grid_x": 103, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y194": { + "bits": {}, + "grid_x": 103, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y195": { + "bits": {}, + "grid_x": 103, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y196": { + "bits": {}, + "grid_x": 103, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y197": { + "bits": {}, + "grid_x": 103, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y198": { + "bits": {}, + "grid_x": 103, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y199": { + "bits": {}, + "grid_x": 103, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y200": { + "bits": {}, + "grid_x": 103, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y201": { + "bits": {}, + "grid_x": 103, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y202": { + "bits": {}, + "grid_x": 103, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y203": { + "bits": {}, + "grid_x": 103, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y204": { + "bits": {}, + "grid_x": 103, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y205": { + "bits": {}, + "grid_x": 103, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y206": { + "bits": {}, + "grid_x": 103, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y207": { + "bits": {}, + "grid_x": 103, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X103Y208": { + "bits": {}, + "grid_x": 103, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y105": { + "bits": {}, + "grid_x": 104, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y106": { + "bits": {}, + "grid_x": 104, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y107": { + "bits": {}, + "grid_x": 104, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y108": { + "bits": {}, + "grid_x": 104, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y109": { + "bits": {}, + "grid_x": 104, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y110": { + "bits": {}, + "grid_x": 104, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y111": { + "bits": {}, + "grid_x": 104, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y112": { + "bits": {}, + "grid_x": 104, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y113": { + "bits": {}, + "grid_x": 104, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y114": { + "bits": {}, + "grid_x": 104, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y115": { + "bits": {}, + "grid_x": 104, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y116": { + "bits": {}, + "grid_x": 104, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y117": { + "bits": {}, + "grid_x": 104, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y118": { + "bits": {}, + "grid_x": 104, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y119": { + "bits": {}, + "grid_x": 104, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y120": { + "bits": {}, + "grid_x": 104, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y121": { + "bits": {}, + "grid_x": 104, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y122": { + "bits": {}, + "grid_x": 104, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y123": { + "bits": {}, + "grid_x": 104, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y124": { + "bits": {}, + "grid_x": 104, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y125": { + "bits": {}, + "grid_x": 104, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y126": { + "bits": {}, + "grid_x": 104, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y127": { + "bits": {}, + "grid_x": 104, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y128": { + "bits": {}, + "grid_x": 104, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y129": { + "bits": {}, + "grid_x": 104, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y130": { + "bits": {}, + "grid_x": 104, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y131": { + "bits": {}, + "grid_x": 104, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y132": { + "bits": {}, + "grid_x": 104, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y133": { + "bits": {}, + "grid_x": 104, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y134": { + "bits": {}, + "grid_x": 104, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y135": { + "bits": {}, + "grid_x": 104, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y136": { + "bits": {}, + "grid_x": 104, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y137": { + "bits": {}, + "grid_x": 104, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y138": { + "bits": {}, + "grid_x": 104, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y139": { + "bits": {}, + "grid_x": 104, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y140": { + "bits": {}, + "grid_x": 104, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y141": { + "bits": {}, + "grid_x": 104, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y142": { + "bits": {}, + "grid_x": 104, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y143": { + "bits": {}, + "grid_x": 104, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y144": { + "bits": {}, + "grid_x": 104, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y145": { + "bits": {}, + "grid_x": 104, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y146": { + "bits": {}, + "grid_x": 104, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y147": { + "bits": {}, + "grid_x": 104, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y148": { + "bits": {}, + "grid_x": 104, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y149": { + "bits": {}, + "grid_x": 104, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y150": { + "bits": {}, + "grid_x": 104, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y151": { + "bits": {}, + "grid_x": 104, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y152": { + "bits": {}, + "grid_x": 104, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y153": { + "bits": {}, + "grid_x": 104, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y154": { + "bits": {}, + "grid_x": 104, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y155": { + "bits": {}, + "grid_x": 104, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y156": { + "bits": {}, + "grid_x": 104, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y157": { + "bits": {}, + "grid_x": 104, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y158": { + "bits": {}, + "grid_x": 104, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y159": { + "bits": {}, + "grid_x": 104, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y160": { + "bits": {}, + "grid_x": 104, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y161": { + "bits": {}, + "grid_x": 104, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y162": { + "bits": {}, + "grid_x": 104, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y163": { + "bits": {}, + "grid_x": 104, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y164": { + "bits": {}, + "grid_x": 104, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y165": { + "bits": {}, + "grid_x": 104, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y166": { + "bits": {}, + "grid_x": 104, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y167": { + "bits": {}, + "grid_x": 104, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y168": { + "bits": {}, + "grid_x": 104, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y169": { + "bits": {}, + "grid_x": 104, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y170": { + "bits": {}, + "grid_x": 104, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y171": { + "bits": {}, + "grid_x": 104, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y172": { + "bits": {}, + "grid_x": 104, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y173": { + "bits": {}, + "grid_x": 104, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y174": { + "bits": {}, + "grid_x": 104, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y175": { + "bits": {}, + "grid_x": 104, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y176": { + "bits": {}, + "grid_x": 104, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y177": { + "bits": {}, + "grid_x": 104, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y178": { + "bits": {}, + "grid_x": 104, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y179": { + "bits": {}, + "grid_x": 104, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y180": { + "bits": {}, + "grid_x": 104, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y181": { + "bits": {}, + "grid_x": 104, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y182": { + "bits": {}, + "grid_x": 104, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y183": { + "bits": {}, + "grid_x": 104, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y184": { + "bits": {}, + "grid_x": 104, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y185": { + "bits": {}, + "grid_x": 104, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y186": { + "bits": {}, + "grid_x": 104, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y187": { + "bits": {}, + "grid_x": 104, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y188": { + "bits": {}, + "grid_x": 104, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y189": { + "bits": {}, + "grid_x": 104, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y190": { + "bits": {}, + "grid_x": 104, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y191": { + "bits": {}, + "grid_x": 104, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y192": { + "bits": {}, + "grid_x": 104, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y193": { + "bits": {}, + "grid_x": 104, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y194": { + "bits": {}, + "grid_x": 104, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y195": { + "bits": {}, + "grid_x": 104, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y196": { + "bits": {}, + "grid_x": 104, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y197": { + "bits": {}, + "grid_x": 104, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y198": { + "bits": {}, + "grid_x": 104, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y199": { + "bits": {}, + "grid_x": 104, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y200": { + "bits": {}, + "grid_x": 104, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y201": { + "bits": {}, + "grid_x": 104, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y202": { + "bits": {}, + "grid_x": 104, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y203": { + "bits": {}, + "grid_x": 104, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y204": { + "bits": {}, + "grid_x": 104, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y205": { + "bits": {}, + "grid_x": 104, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y206": { + "bits": {}, + "grid_x": 104, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y207": { + "bits": {}, + "grid_x": 104, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X104Y208": { + "bits": {}, + "grid_x": 104, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y105": { + "bits": {}, + "grid_x": 105, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y106": { + "bits": {}, + "grid_x": 105, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y107": { + "bits": {}, + "grid_x": 105, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y108": { + "bits": {}, + "grid_x": 105, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y109": { + "bits": {}, + "grid_x": 105, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y110": { + "bits": {}, + "grid_x": 105, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y111": { + "bits": {}, + "grid_x": 105, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y112": { + "bits": {}, + "grid_x": 105, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y113": { + "bits": {}, + "grid_x": 105, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y114": { + "bits": {}, + "grid_x": 105, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y115": { + "bits": {}, + "grid_x": 105, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y116": { + "bits": {}, + "grid_x": 105, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y117": { + "bits": {}, + "grid_x": 105, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y118": { + "bits": {}, + "grid_x": 105, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y119": { + "bits": {}, + "grid_x": 105, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y120": { + "bits": {}, + "grid_x": 105, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y121": { + "bits": {}, + "grid_x": 105, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y122": { + "bits": {}, + "grid_x": 105, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y123": { + "bits": {}, + "grid_x": 105, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y124": { + "bits": {}, + "grid_x": 105, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y125": { + "bits": {}, + "grid_x": 105, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y126": { + "bits": {}, + "grid_x": 105, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y127": { + "bits": {}, + "grid_x": 105, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y128": { + "bits": {}, + "grid_x": 105, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y129": { + "bits": {}, + "grid_x": 105, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y130": { + "bits": {}, + "grid_x": 105, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y131": { + "bits": {}, + "grid_x": 105, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y132": { + "bits": {}, + "grid_x": 105, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y133": { + "bits": {}, + "grid_x": 105, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y134": { + "bits": {}, + "grid_x": 105, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y135": { + "bits": {}, + "grid_x": 105, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y136": { + "bits": {}, + "grid_x": 105, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y137": { + "bits": {}, + "grid_x": 105, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y138": { + "bits": {}, + "grid_x": 105, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y139": { + "bits": {}, + "grid_x": 105, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y140": { + "bits": {}, + "grid_x": 105, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y141": { + "bits": {}, + "grid_x": 105, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y142": { + "bits": {}, + "grid_x": 105, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y143": { + "bits": {}, + "grid_x": 105, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y144": { + "bits": {}, + "grid_x": 105, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y145": { + "bits": {}, + "grid_x": 105, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y146": { + "bits": {}, + "grid_x": 105, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y147": { + "bits": {}, + "grid_x": 105, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y148": { + "bits": {}, + "grid_x": 105, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y149": { + "bits": {}, + "grid_x": 105, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y150": { + "bits": {}, + "grid_x": 105, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y151": { + "bits": {}, + "grid_x": 105, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y152": { + "bits": {}, + "grid_x": 105, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y153": { + "bits": {}, + "grid_x": 105, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y154": { + "bits": {}, + "grid_x": 105, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y155": { + "bits": {}, + "grid_x": 105, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y156": { + "bits": {}, + "grid_x": 105, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y157": { + "bits": {}, + "grid_x": 105, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y158": { + "bits": {}, + "grid_x": 105, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y159": { + "bits": {}, + "grid_x": 105, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y160": { + "bits": {}, + "grid_x": 105, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y161": { + "bits": {}, + "grid_x": 105, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y162": { + "bits": {}, + "grid_x": 105, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y163": { + "bits": {}, + "grid_x": 105, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y164": { + "bits": {}, + "grid_x": 105, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y165": { + "bits": {}, + "grid_x": 105, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y166": { + "bits": {}, + "grid_x": 105, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y167": { + "bits": {}, + "grid_x": 105, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y168": { + "bits": {}, + "grid_x": 105, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y169": { + "bits": {}, + "grid_x": 105, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y170": { + "bits": {}, + "grid_x": 105, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y171": { + "bits": {}, + "grid_x": 105, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y172": { + "bits": {}, + "grid_x": 105, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y173": { + "bits": {}, + "grid_x": 105, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y174": { + "bits": {}, + "grid_x": 105, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y175": { + "bits": {}, + "grid_x": 105, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y176": { + "bits": {}, + "grid_x": 105, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y177": { + "bits": {}, + "grid_x": 105, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y178": { + "bits": {}, + "grid_x": 105, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y179": { + "bits": {}, + "grid_x": 105, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y180": { + "bits": {}, + "grid_x": 105, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y181": { + "bits": {}, + "grid_x": 105, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y182": { + "bits": {}, + "grid_x": 105, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y183": { + "bits": {}, + "grid_x": 105, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y184": { + "bits": {}, + "grid_x": 105, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y185": { + "bits": {}, + "grid_x": 105, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y186": { + "bits": {}, + "grid_x": 105, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y187": { + "bits": {}, + "grid_x": 105, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y188": { + "bits": {}, + "grid_x": 105, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y189": { + "bits": {}, + "grid_x": 105, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y190": { + "bits": {}, + "grid_x": 105, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y191": { + "bits": {}, + "grid_x": 105, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y192": { + "bits": {}, + "grid_x": 105, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y193": { + "bits": {}, + "grid_x": 105, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y194": { + "bits": {}, + "grid_x": 105, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y195": { + "bits": {}, + "grid_x": 105, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y196": { + "bits": {}, + "grid_x": 105, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y197": { + "bits": {}, + "grid_x": 105, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y198": { + "bits": {}, + "grid_x": 105, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y199": { + "bits": {}, + "grid_x": 105, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y200": { + "bits": {}, + "grid_x": 105, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y201": { + "bits": {}, + "grid_x": 105, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y202": { + "bits": {}, + "grid_x": 105, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y203": { + "bits": {}, + "grid_x": 105, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y204": { + "bits": {}, + "grid_x": 105, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y205": { + "bits": {}, + "grid_x": 105, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y206": { + "bits": {}, + "grid_x": 105, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y207": { + "bits": {}, + "grid_x": 105, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X105Y208": { + "bits": {}, + "grid_x": 105, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y0": { + "bits": {}, + "grid_x": 106, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y104": { + "bits": {}, + "grid_x": 106, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y105": { + "bits": {}, + "grid_x": 106, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y106": { + "bits": {}, + "grid_x": 106, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y107": { + "bits": {}, + "grid_x": 106, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y108": { + "bits": {}, + "grid_x": 106, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y109": { + "bits": {}, + "grid_x": 106, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y110": { + "bits": {}, + "grid_x": 106, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y111": { + "bits": {}, + "grid_x": 106, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y112": { + "bits": {}, + "grid_x": 106, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y113": { + "bits": {}, + "grid_x": 106, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y114": { + "bits": {}, + "grid_x": 106, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y115": { + "bits": {}, + "grid_x": 106, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y116": { + "bits": {}, + "grid_x": 106, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y117": { + "bits": {}, + "grid_x": 106, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y118": { + "bits": {}, + "grid_x": 106, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y119": { + "bits": {}, + "grid_x": 106, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y120": { + "bits": {}, + "grid_x": 106, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y121": { + "bits": {}, + "grid_x": 106, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y122": { + "bits": {}, + "grid_x": 106, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y123": { + "bits": {}, + "grid_x": 106, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y124": { + "bits": {}, + "grid_x": 106, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y125": { + "bits": {}, + "grid_x": 106, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y126": { + "bits": {}, + "grid_x": 106, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y127": { + "bits": {}, + "grid_x": 106, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y128": { + "bits": {}, + "grid_x": 106, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y129": { + "bits": {}, + "grid_x": 106, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y130": { + "bits": {}, + "grid_x": 106, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y131": { + "bits": {}, + "grid_x": 106, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y132": { + "bits": {}, + "grid_x": 106, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y133": { + "bits": {}, + "grid_x": 106, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y134": { + "bits": {}, + "grid_x": 106, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y135": { + "bits": {}, + "grid_x": 106, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y136": { + "bits": {}, + "grid_x": 106, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y137": { + "bits": {}, + "grid_x": 106, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y138": { + "bits": {}, + "grid_x": 106, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y139": { + "bits": {}, + "grid_x": 106, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y140": { + "bits": {}, + "grid_x": 106, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y141": { + "bits": {}, + "grid_x": 106, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y142": { + "bits": {}, + "grid_x": 106, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y143": { + "bits": {}, + "grid_x": 106, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y144": { + "bits": {}, + "grid_x": 106, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y145": { + "bits": {}, + "grid_x": 106, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y146": { + "bits": {}, + "grid_x": 106, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y147": { + "bits": {}, + "grid_x": 106, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y148": { + "bits": {}, + "grid_x": 106, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y149": { + "bits": {}, + "grid_x": 106, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y150": { + "bits": {}, + "grid_x": 106, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y151": { + "bits": {}, + "grid_x": 106, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y152": { + "bits": {}, + "grid_x": 106, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y153": { + "bits": {}, + "grid_x": 106, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y154": { + "bits": {}, + "grid_x": 106, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y155": { + "bits": {}, + "grid_x": 106, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y156": { + "bits": {}, + "grid_x": 106, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y157": { + "bits": {}, + "grid_x": 106, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y158": { + "bits": {}, + "grid_x": 106, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y159": { + "bits": {}, + "grid_x": 106, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y160": { + "bits": {}, + "grid_x": 106, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y161": { + "bits": {}, + "grid_x": 106, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y162": { + "bits": {}, + "grid_x": 106, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y163": { + "bits": {}, + "grid_x": 106, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y164": { + "bits": {}, + "grid_x": 106, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y165": { + "bits": {}, + "grid_x": 106, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y166": { + "bits": {}, + "grid_x": 106, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y167": { + "bits": {}, + "grid_x": 106, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y168": { + "bits": {}, + "grid_x": 106, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y169": { + "bits": {}, + "grid_x": 106, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y170": { + "bits": {}, + "grid_x": 106, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y171": { + "bits": {}, + "grid_x": 106, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y172": { + "bits": {}, + "grid_x": 106, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y173": { + "bits": {}, + "grid_x": 106, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y174": { + "bits": {}, + "grid_x": 106, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y175": { + "bits": {}, + "grid_x": 106, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y176": { + "bits": {}, + "grid_x": 106, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y177": { + "bits": {}, + "grid_x": 106, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y178": { + "bits": {}, + "grid_x": 106, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y179": { + "bits": {}, + "grid_x": 106, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y180": { + "bits": {}, + "grid_x": 106, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y181": { + "bits": {}, + "grid_x": 106, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y182": { + "bits": {}, + "grid_x": 106, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y183": { + "bits": {}, + "grid_x": 106, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y184": { + "bits": {}, + "grid_x": 106, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y185": { + "bits": {}, + "grid_x": 106, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y186": { + "bits": {}, + "grid_x": 106, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y187": { + "bits": {}, + "grid_x": 106, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y188": { + "bits": {}, + "grid_x": 106, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y189": { + "bits": {}, + "grid_x": 106, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y190": { + "bits": {}, + "grid_x": 106, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y191": { + "bits": {}, + "grid_x": 106, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y192": { + "bits": {}, + "grid_x": 106, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y193": { + "bits": {}, + "grid_x": 106, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y194": { + "bits": {}, + "grid_x": 106, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y195": { + "bits": {}, + "grid_x": 106, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y196": { + "bits": {}, + "grid_x": 106, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y197": { + "bits": {}, + "grid_x": 106, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y198": { + "bits": {}, + "grid_x": 106, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y199": { + "bits": {}, + "grid_x": 106, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y200": { + "bits": {}, + "grid_x": 106, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y201": { + "bits": {}, + "grid_x": 106, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y202": { + "bits": {}, + "grid_x": 106, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y203": { + "bits": {}, + "grid_x": 106, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y204": { + "bits": {}, + "grid_x": 106, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y205": { + "bits": {}, + "grid_x": 106, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y206": { + "bits": {}, + "grid_x": 106, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y207": { + "bits": {}, + "grid_x": 106, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X106Y208": { + "bits": {}, + "grid_x": 106, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y0": { + "bits": {}, + "grid_x": 107, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y104": { + "bits": {}, + "grid_x": 107, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y105": { + "bits": {}, + "grid_x": 107, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y106": { + "bits": {}, + "grid_x": 107, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y107": { + "bits": {}, + "grid_x": 107, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y108": { + "bits": {}, + "grid_x": 107, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y109": { + "bits": {}, + "grid_x": 107, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y110": { + "bits": {}, + "grid_x": 107, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y111": { + "bits": {}, + "grid_x": 107, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y112": { + "bits": {}, + "grid_x": 107, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y113": { + "bits": {}, + "grid_x": 107, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y114": { + "bits": {}, + "grid_x": 107, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y115": { + "bits": {}, + "grid_x": 107, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y116": { + "bits": {}, + "grid_x": 107, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y117": { + "bits": {}, + "grid_x": 107, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y118": { + "bits": {}, + "grid_x": 107, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y119": { + "bits": {}, + "grid_x": 107, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y120": { + "bits": {}, + "grid_x": 107, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y121": { + "bits": {}, + "grid_x": 107, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y122": { + "bits": {}, + "grid_x": 107, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y123": { + "bits": {}, + "grid_x": 107, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y124": { + "bits": {}, + "grid_x": 107, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y125": { + "bits": {}, + "grid_x": 107, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y126": { + "bits": {}, + "grid_x": 107, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y127": { + "bits": {}, + "grid_x": 107, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y128": { + "bits": {}, + "grid_x": 107, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y129": { + "bits": {}, + "grid_x": 107, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y130": { + "bits": {}, + "grid_x": 107, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y131": { + "bits": {}, + "grid_x": 107, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y132": { + "bits": {}, + "grid_x": 107, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y133": { + "bits": {}, + "grid_x": 107, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y134": { + "bits": {}, + "grid_x": 107, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y135": { + "bits": {}, + "grid_x": 107, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y136": { + "bits": {}, + "grid_x": 107, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y137": { + "bits": {}, + "grid_x": 107, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y138": { + "bits": {}, + "grid_x": 107, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y139": { + "bits": {}, + "grid_x": 107, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y140": { + "bits": {}, + "grid_x": 107, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y141": { + "bits": {}, + "grid_x": 107, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y142": { + "bits": {}, + "grid_x": 107, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y143": { + "bits": {}, + "grid_x": 107, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y144": { + "bits": {}, + "grid_x": 107, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y145": { + "bits": {}, + "grid_x": 107, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y146": { + "bits": {}, + "grid_x": 107, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y147": { + "bits": {}, + "grid_x": 107, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y148": { + "bits": {}, + "grid_x": 107, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y149": { + "bits": {}, + "grid_x": 107, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y150": { + "bits": {}, + "grid_x": 107, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y151": { + "bits": {}, + "grid_x": 107, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y152": { + "bits": {}, + "grid_x": 107, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y153": { + "bits": {}, + "grid_x": 107, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y154": { + "bits": {}, + "grid_x": 107, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y155": { + "bits": {}, + "grid_x": 107, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y156": { + "bits": {}, + "grid_x": 107, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y157": { + "bits": {}, + "grid_x": 107, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y158": { + "bits": {}, + "grid_x": 107, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y159": { + "bits": {}, + "grid_x": 107, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y160": { + "bits": {}, + "grid_x": 107, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y161": { + "bits": {}, + "grid_x": 107, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y162": { + "bits": {}, + "grid_x": 107, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y163": { + "bits": {}, + "grid_x": 107, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y164": { + "bits": {}, + "grid_x": 107, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y165": { + "bits": {}, + "grid_x": 107, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y166": { + "bits": {}, + "grid_x": 107, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y167": { + "bits": {}, + "grid_x": 107, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y168": { + "bits": {}, + "grid_x": 107, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y169": { + "bits": {}, + "grid_x": 107, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y170": { + "bits": {}, + "grid_x": 107, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y171": { + "bits": {}, + "grid_x": 107, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y172": { + "bits": {}, + "grid_x": 107, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y173": { + "bits": {}, + "grid_x": 107, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y174": { + "bits": {}, + "grid_x": 107, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y175": { + "bits": {}, + "grid_x": 107, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y176": { + "bits": {}, + "grid_x": 107, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y177": { + "bits": {}, + "grid_x": 107, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y178": { + "bits": {}, + "grid_x": 107, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y179": { + "bits": {}, + "grid_x": 107, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y180": { + "bits": {}, + "grid_x": 107, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y181": { + "bits": {}, + "grid_x": 107, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y182": { + "bits": {}, + "grid_x": 107, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y183": { + "bits": {}, + "grid_x": 107, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y184": { + "bits": {}, + "grid_x": 107, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y185": { + "bits": {}, + "grid_x": 107, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y186": { + "bits": {}, + "grid_x": 107, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y187": { + "bits": {}, + "grid_x": 107, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y188": { + "bits": {}, + "grid_x": 107, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y189": { + "bits": {}, + "grid_x": 107, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y190": { + "bits": {}, + "grid_x": 107, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y191": { + "bits": {}, + "grid_x": 107, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y192": { + "bits": {}, + "grid_x": 107, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y193": { + "bits": {}, + "grid_x": 107, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y194": { + "bits": {}, + "grid_x": 107, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y195": { + "bits": {}, + "grid_x": 107, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y196": { + "bits": {}, + "grid_x": 107, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y197": { + "bits": {}, + "grid_x": 107, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y198": { + "bits": {}, + "grid_x": 107, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y199": { + "bits": {}, + "grid_x": 107, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y200": { + "bits": {}, + "grid_x": 107, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y201": { + "bits": {}, + "grid_x": 107, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y202": { + "bits": {}, + "grid_x": 107, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y203": { + "bits": {}, + "grid_x": 107, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y204": { + "bits": {}, + "grid_x": 107, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y205": { + "bits": {}, + "grid_x": 107, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y206": { + "bits": {}, + "grid_x": 107, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y207": { + "bits": {}, + "grid_x": 107, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y208": { + "bits": {}, + "grid_x": 107, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X107Y52": { + "bits": {}, + "grid_x": 107, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y1": { + "bits": {}, + "grid_x": 108, + "grid_y": 207, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y10": { + "bits": {}, + "grid_x": 108, + "grid_y": 198, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y100": { + "bits": {}, + "grid_x": 108, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y101": { + "bits": {}, + "grid_x": 108, + "grid_y": 107, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y102": { + "bits": {}, + "grid_x": 108, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y103": { + "bits": {}, + "grid_x": 108, + "grid_y": 105, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y104": { + "bits": {}, + "grid_x": 108, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y105": { + "bits": {}, + "grid_x": 108, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y106": { + "bits": {}, + "grid_x": 108, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y107": { + "bits": {}, + "grid_x": 108, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y108": { + "bits": {}, + "grid_x": 108, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y109": { + "bits": {}, + "grid_x": 108, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y11": { + "bits": {}, + "grid_x": 108, + "grid_y": 197, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y110": { + "bits": {}, + "grid_x": 108, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y111": { + "bits": {}, + "grid_x": 108, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y112": { + "bits": {}, + "grid_x": 108, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y113": { + "bits": {}, + "grid_x": 108, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y114": { + "bits": {}, + "grid_x": 108, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y115": { + "bits": {}, + "grid_x": 108, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y116": { + "bits": {}, + "grid_x": 108, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y117": { + "bits": {}, + "grid_x": 108, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y118": { + "bits": {}, + "grid_x": 108, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y119": { + "bits": {}, + "grid_x": 108, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y12": { + "bits": {}, + "grid_x": 108, + "grid_y": 196, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y120": { + "bits": {}, + "grid_x": 108, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y121": { + "bits": {}, + "grid_x": 108, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y122": { + "bits": {}, + "grid_x": 108, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y123": { + "bits": {}, + "grid_x": 108, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y124": { + "bits": {}, + "grid_x": 108, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y125": { + "bits": {}, + "grid_x": 108, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y126": { + "bits": {}, + "grid_x": 108, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y127": { + "bits": {}, + "grid_x": 108, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y128": { + "bits": {}, + "grid_x": 108, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y129": { + "bits": {}, + "grid_x": 108, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y13": { + "bits": {}, + "grid_x": 108, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y130": { + "bits": {}, + "grid_x": 108, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y131": { + "bits": {}, + "grid_x": 108, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y132": { + "bits": {}, + "grid_x": 108, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y133": { + "bits": {}, + "grid_x": 108, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y134": { + "bits": {}, + "grid_x": 108, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y135": { + "bits": {}, + "grid_x": 108, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y136": { + "bits": {}, + "grid_x": 108, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y137": { + "bits": {}, + "grid_x": 108, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y138": { + "bits": {}, + "grid_x": 108, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y139": { + "bits": {}, + "grid_x": 108, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y14": { + "bits": {}, + "grid_x": 108, + "grid_y": 194, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y140": { + "bits": {}, + "grid_x": 108, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y141": { + "bits": {}, + "grid_x": 108, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y142": { + "bits": {}, + "grid_x": 108, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y143": { + "bits": {}, + "grid_x": 108, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y144": { + "bits": {}, + "grid_x": 108, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y145": { + "bits": {}, + "grid_x": 108, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y146": { + "bits": {}, + "grid_x": 108, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y147": { + "bits": {}, + "grid_x": 108, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y148": { + "bits": {}, + "grid_x": 108, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y149": { + "bits": {}, + "grid_x": 108, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y15": { + "bits": {}, + "grid_x": 108, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y150": { + "bits": {}, + "grid_x": 108, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y151": { + "bits": {}, + "grid_x": 108, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y152": { + "bits": {}, + "grid_x": 108, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y153": { + "bits": {}, + "grid_x": 108, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y154": { + "bits": {}, + "grid_x": 108, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y155": { + "bits": {}, + "grid_x": 108, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y156": { + "bits": {}, + "grid_x": 108, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y157": { + "bits": {}, + "grid_x": 108, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y158": { + "bits": {}, + "grid_x": 108, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y159": { + "bits": {}, + "grid_x": 108, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y16": { + "bits": {}, + "grid_x": 108, + "grid_y": 192, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y160": { + "bits": {}, + "grid_x": 108, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y161": { + "bits": {}, + "grid_x": 108, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y162": { + "bits": {}, + "grid_x": 108, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y163": { + "bits": {}, + "grid_x": 108, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y164": { + "bits": {}, + "grid_x": 108, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y165": { + "bits": {}, + "grid_x": 108, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y166": { + "bits": {}, + "grid_x": 108, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y167": { + "bits": {}, + "grid_x": 108, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y168": { + "bits": {}, + "grid_x": 108, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y169": { + "bits": {}, + "grid_x": 108, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y17": { + "bits": {}, + "grid_x": 108, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y170": { + "bits": {}, + "grid_x": 108, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y171": { + "bits": {}, + "grid_x": 108, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y172": { + "bits": {}, + "grid_x": 108, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y173": { + "bits": {}, + "grid_x": 108, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y174": { + "bits": {}, + "grid_x": 108, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y175": { + "bits": {}, + "grid_x": 108, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y176": { + "bits": {}, + "grid_x": 108, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y177": { + "bits": {}, + "grid_x": 108, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y178": { + "bits": {}, + "grid_x": 108, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y179": { + "bits": {}, + "grid_x": 108, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y180": { + "bits": {}, + "grid_x": 108, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y181": { + "bits": {}, + "grid_x": 108, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y182": { + "bits": {}, + "grid_x": 108, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y183": { + "bits": {}, + "grid_x": 108, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y184": { + "bits": {}, + "grid_x": 108, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y185": { + "bits": {}, + "grid_x": 108, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y186": { + "bits": {}, + "grid_x": 108, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y187": { + "bits": {}, + "grid_x": 108, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y188": { + "bits": {}, + "grid_x": 108, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y189": { + "bits": {}, + "grid_x": 108, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y19": { + "bits": {}, + "grid_x": 108, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y190": { + "bits": {}, + "grid_x": 108, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y191": { + "bits": {}, + "grid_x": 108, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y192": { + "bits": {}, + "grid_x": 108, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y193": { + "bits": {}, + "grid_x": 108, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y194": { + "bits": {}, + "grid_x": 108, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y195": { + "bits": {}, + "grid_x": 108, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y196": { + "bits": {}, + "grid_x": 108, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y197": { + "bits": {}, + "grid_x": 108, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y198": { + "bits": {}, + "grid_x": 108, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y199": { + "bits": {}, + "grid_x": 108, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y2": { + "bits": {}, + "grid_x": 108, + "grid_y": 206, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y20": { + "bits": {}, + "grid_x": 108, + "grid_y": 188, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y200": { + "bits": {}, + "grid_x": 108, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y201": { + "bits": {}, + "grid_x": 108, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y202": { + "bits": {}, + "grid_x": 108, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y203": { + "bits": {}, + "grid_x": 108, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y204": { + "bits": {}, + "grid_x": 108, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y205": { + "bits": {}, + "grid_x": 108, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y206": { + "bits": {}, + "grid_x": 108, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y207": { + "bits": {}, + "grid_x": 108, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y208": { + "bits": {}, + "grid_x": 108, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y21": { + "bits": {}, + "grid_x": 108, + "grid_y": 187, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y22": { + "bits": {}, + "grid_x": 108, + "grid_y": 186, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y23": { + "bits": {}, + "grid_x": 108, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y24": { + "bits": {}, + "grid_x": 108, + "grid_y": 184, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y25": { + "bits": {}, + "grid_x": 108, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y27": { + "bits": {}, + "grid_x": 108, + "grid_y": 181, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y28": { + "bits": {}, + "grid_x": 108, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y29": { + "bits": {}, + "grid_x": 108, + "grid_y": 179, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y3": { + "bits": {}, + "grid_x": 108, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y30": { + "bits": {}, + "grid_x": 108, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y32": { + "bits": {}, + "grid_x": 108, + "grid_y": 176, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y33": { + "bits": {}, + "grid_x": 108, + "grid_y": 175, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y34": { + "bits": {}, + "grid_x": 108, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y35": { + "bits": {}, + "grid_x": 108, + "grid_y": 173, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y36": { + "bits": {}, + "grid_x": 108, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y37": { + "bits": {}, + "grid_x": 108, + "grid_y": 171, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y38": { + "bits": {}, + "grid_x": 108, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y39": { + "bits": {}, + "grid_x": 108, + "grid_y": 169, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y4": { + "bits": {}, + "grid_x": 108, + "grid_y": 204, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y40": { + "bits": {}, + "grid_x": 108, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y41": { + "bits": {}, + "grid_x": 108, + "grid_y": 167, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y42": { + "bits": {}, + "grid_x": 108, + "grid_y": 166, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y43": { + "bits": {}, + "grid_x": 108, + "grid_y": 165, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y45": { + "bits": {}, + "grid_x": 108, + "grid_y": 163, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y46": { + "bits": {}, + "grid_x": 108, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y47": { + "bits": {}, + "grid_x": 108, + "grid_y": 161, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y48": { + "bits": {}, + "grid_x": 108, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y49": { + "bits": {}, + "grid_x": 108, + "grid_y": 159, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y5": { + "bits": {}, + "grid_x": 108, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y50": { + "bits": {}, + "grid_x": 108, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y51": { + "bits": {}, + "grid_x": 108, + "grid_y": 157, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y53": { + "bits": {}, + "grid_x": 108, + "grid_y": 155, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y54": { + "bits": {}, + "grid_x": 108, + "grid_y": 154, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y55": { + "bits": {}, + "grid_x": 108, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y56": { + "bits": {}, + "grid_x": 108, + "grid_y": 152, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y57": { + "bits": {}, + "grid_x": 108, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y58": { + "bits": {}, + "grid_x": 108, + "grid_y": 150, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y59": { + "bits": {}, + "grid_x": 108, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y6": { + "bits": {}, + "grid_x": 108, + "grid_y": 202, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y60": { + "bits": {}, + "grid_x": 108, + "grid_y": 148, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y62": { + "bits": {}, + "grid_x": 108, + "grid_y": 146, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y63": { + "bits": {}, + "grid_x": 108, + "grid_y": 145, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y64": { + "bits": {}, + "grid_x": 108, + "grid_y": 144, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y65": { + "bits": {}, + "grid_x": 108, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y66": { + "bits": {}, + "grid_x": 108, + "grid_y": 142, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y67": { + "bits": {}, + "grid_x": 108, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y68": { + "bits": {}, + "grid_x": 108, + "grid_y": 140, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y69": { + "bits": {}, + "grid_x": 108, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y7": { + "bits": {}, + "grid_x": 108, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y71": { + "bits": {}, + "grid_x": 108, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y72": { + "bits": {}, + "grid_x": 108, + "grid_y": 136, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y73": { + "bits": {}, + "grid_x": 108, + "grid_y": 135, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y74": { + "bits": {}, + "grid_x": 108, + "grid_y": 134, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y75": { + "bits": {}, + "grid_x": 108, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y76": { + "bits": {}, + "grid_x": 108, + "grid_y": 132, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y77": { + "bits": {}, + "grid_x": 108, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y79": { + "bits": {}, + "grid_x": 108, + "grid_y": 129, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y8": { + "bits": {}, + "grid_x": 108, + "grid_y": 200, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y80": { + "bits": {}, + "grid_x": 108, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y81": { + "bits": {}, + "grid_x": 108, + "grid_y": 127, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y82": { + "bits": {}, + "grid_x": 108, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y84": { + "bits": {}, + "grid_x": 108, + "grid_y": 124, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y85": { + "bits": {}, + "grid_x": 108, + "grid_y": 123, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y86": { + "bits": {}, + "grid_x": 108, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y87": { + "bits": {}, + "grid_x": 108, + "grid_y": 121, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y88": { + "bits": {}, + "grid_x": 108, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y89": { + "bits": {}, + "grid_x": 108, + "grid_y": 119, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y90": { + "bits": {}, + "grid_x": 108, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y91": { + "bits": {}, + "grid_x": 108, + "grid_y": 117, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y92": { + "bits": {}, + "grid_x": 108, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y93": { + "bits": {}, + "grid_x": 108, + "grid_y": 115, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y94": { + "bits": {}, + "grid_x": 108, + "grid_y": 114, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y95": { + "bits": {}, + "grid_x": 108, + "grid_y": 113, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y97": { + "bits": {}, + "grid_x": 108, + "grid_y": 111, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y98": { + "bits": {}, + "grid_x": 108, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X108Y99": { + "bits": {}, + "grid_x": 108, + "grid_y": 109, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y0": { + "bits": {}, + "grid_x": 109, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y10": { + "bits": {}, + "grid_x": 109, + "grid_y": 198, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y100": { + "bits": {}, + "grid_x": 109, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y101": { + "bits": {}, + "grid_x": 109, + "grid_y": 107, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y102": { + "bits": {}, + "grid_x": 109, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y104": { + "bits": {}, + "grid_x": 109, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y105": { + "bits": {}, + "grid_x": 109, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y106": { + "bits": {}, + "grid_x": 109, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y107": { + "bits": {}, + "grid_x": 109, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y108": { + "bits": {}, + "grid_x": 109, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y109": { + "bits": {}, + "grid_x": 109, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y11": { + "bits": {}, + "grid_x": 109, + "grid_y": 197, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y110": { + "bits": {}, + "grid_x": 109, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y111": { + "bits": {}, + "grid_x": 109, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y112": { + "bits": {}, + "grid_x": 109, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y113": { + "bits": {}, + "grid_x": 109, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y114": { + "bits": {}, + "grid_x": 109, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y115": { + "bits": {}, + "grid_x": 109, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y116": { + "bits": {}, + "grid_x": 109, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y117": { + "bits": {}, + "grid_x": 109, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y118": { + "bits": {}, + "grid_x": 109, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y119": { + "bits": {}, + "grid_x": 109, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y12": { + "bits": {}, + "grid_x": 109, + "grid_y": 196, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y120": { + "bits": {}, + "grid_x": 109, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y121": { + "bits": {}, + "grid_x": 109, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y122": { + "bits": {}, + "grid_x": 109, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y123": { + "bits": {}, + "grid_x": 109, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y124": { + "bits": {}, + "grid_x": 109, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y125": { + "bits": {}, + "grid_x": 109, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y126": { + "bits": {}, + "grid_x": 109, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y127": { + "bits": {}, + "grid_x": 109, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y128": { + "bits": {}, + "grid_x": 109, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y129": { + "bits": {}, + "grid_x": 109, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y13": { + "bits": {}, + "grid_x": 109, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y130": { + "bits": {}, + "grid_x": 109, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y131": { + "bits": {}, + "grid_x": 109, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y132": { + "bits": {}, + "grid_x": 109, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y133": { + "bits": {}, + "grid_x": 109, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y134": { + "bits": {}, + "grid_x": 109, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y135": { + "bits": {}, + "grid_x": 109, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y136": { + "bits": {}, + "grid_x": 109, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y137": { + "bits": {}, + "grid_x": 109, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y138": { + "bits": {}, + "grid_x": 109, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y139": { + "bits": {}, + "grid_x": 109, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y14": { + "bits": {}, + "grid_x": 109, + "grid_y": 194, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y140": { + "bits": {}, + "grid_x": 109, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y141": { + "bits": {}, + "grid_x": 109, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y142": { + "bits": {}, + "grid_x": 109, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y143": { + "bits": {}, + "grid_x": 109, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y144": { + "bits": {}, + "grid_x": 109, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y145": { + "bits": {}, + "grid_x": 109, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y146": { + "bits": {}, + "grid_x": 109, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y147": { + "bits": {}, + "grid_x": 109, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y148": { + "bits": {}, + "grid_x": 109, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y149": { + "bits": {}, + "grid_x": 109, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y15": { + "bits": {}, + "grid_x": 109, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y150": { + "bits": {}, + "grid_x": 109, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y151": { + "bits": {}, + "grid_x": 109, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y152": { + "bits": {}, + "grid_x": 109, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y153": { + "bits": {}, + "grid_x": 109, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y154": { + "bits": {}, + "grid_x": 109, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y155": { + "bits": {}, + "grid_x": 109, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y156": { + "bits": {}, + "grid_x": 109, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y157": { + "bits": {}, + "grid_x": 109, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y158": { + "bits": {}, + "grid_x": 109, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y159": { + "bits": {}, + "grid_x": 109, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y16": { + "bits": {}, + "grid_x": 109, + "grid_y": 192, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y160": { + "bits": {}, + "grid_x": 109, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y161": { + "bits": {}, + "grid_x": 109, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y162": { + "bits": {}, + "grid_x": 109, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y163": { + "bits": {}, + "grid_x": 109, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y164": { + "bits": {}, + "grid_x": 109, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y165": { + "bits": {}, + "grid_x": 109, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y166": { + "bits": {}, + "grid_x": 109, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y167": { + "bits": {}, + "grid_x": 109, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y168": { + "bits": {}, + "grid_x": 109, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y169": { + "bits": {}, + "grid_x": 109, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y17": { + "bits": {}, + "grid_x": 109, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y170": { + "bits": {}, + "grid_x": 109, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y171": { + "bits": {}, + "grid_x": 109, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y172": { + "bits": {}, + "grid_x": 109, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y173": { + "bits": {}, + "grid_x": 109, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y174": { + "bits": {}, + "grid_x": 109, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y175": { + "bits": {}, + "grid_x": 109, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y176": { + "bits": {}, + "grid_x": 109, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y177": { + "bits": {}, + "grid_x": 109, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y178": { + "bits": {}, + "grid_x": 109, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y179": { + "bits": {}, + "grid_x": 109, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y18": { + "bits": {}, + "grid_x": 109, + "grid_y": 190, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y180": { + "bits": {}, + "grid_x": 109, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y181": { + "bits": {}, + "grid_x": 109, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y182": { + "bits": {}, + "grid_x": 109, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y183": { + "bits": {}, + "grid_x": 109, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y184": { + "bits": {}, + "grid_x": 109, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y185": { + "bits": {}, + "grid_x": 109, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y186": { + "bits": {}, + "grid_x": 109, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y187": { + "bits": {}, + "grid_x": 109, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y188": { + "bits": {}, + "grid_x": 109, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y189": { + "bits": {}, + "grid_x": 109, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y19": { + "bits": {}, + "grid_x": 109, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y190": { + "bits": {}, + "grid_x": 109, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y191": { + "bits": {}, + "grid_x": 109, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y192": { + "bits": {}, + "grid_x": 109, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y193": { + "bits": {}, + "grid_x": 109, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y194": { + "bits": {}, + "grid_x": 109, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y195": { + "bits": {}, + "grid_x": 109, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y196": { + "bits": {}, + "grid_x": 109, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y197": { + "bits": {}, + "grid_x": 109, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y198": { + "bits": {}, + "grid_x": 109, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y199": { + "bits": {}, + "grid_x": 109, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y2": { + "bits": {}, + "grid_x": 109, + "grid_y": 206, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y200": { + "bits": {}, + "grid_x": 109, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y201": { + "bits": {}, + "grid_x": 109, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y202": { + "bits": {}, + "grid_x": 109, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y203": { + "bits": {}, + "grid_x": 109, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y204": { + "bits": {}, + "grid_x": 109, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y205": { + "bits": {}, + "grid_x": 109, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y206": { + "bits": {}, + "grid_x": 109, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y207": { + "bits": {}, + "grid_x": 109, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y208": { + "bits": {}, + "grid_x": 109, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y21": { + "bits": {}, + "grid_x": 109, + "grid_y": 187, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y22": { + "bits": {}, + "grid_x": 109, + "grid_y": 186, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y23": { + "bits": {}, + "grid_x": 109, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y24": { + "bits": {}, + "grid_x": 109, + "grid_y": 184, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y25": { + "bits": {}, + "grid_x": 109, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y27": { + "bits": {}, + "grid_x": 109, + "grid_y": 181, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y28": { + "bits": {}, + "grid_x": 109, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y29": { + "bits": {}, + "grid_x": 109, + "grid_y": 179, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y3": { + "bits": {}, + "grid_x": 109, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y30": { + "bits": {}, + "grid_x": 109, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y31": { + "bits": {}, + "grid_x": 109, + "grid_y": 177, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y32": { + "bits": {}, + "grid_x": 109, + "grid_y": 176, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y34": { + "bits": {}, + "grid_x": 109, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y35": { + "bits": {}, + "grid_x": 109, + "grid_y": 173, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y36": { + "bits": {}, + "grid_x": 109, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y37": { + "bits": {}, + "grid_x": 109, + "grid_y": 171, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y38": { + "bits": {}, + "grid_x": 109, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y39": { + "bits": {}, + "grid_x": 109, + "grid_y": 169, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y4": { + "bits": {}, + "grid_x": 109, + "grid_y": 204, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y40": { + "bits": {}, + "grid_x": 109, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y41": { + "bits": {}, + "grid_x": 109, + "grid_y": 167, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y42": { + "bits": {}, + "grid_x": 109, + "grid_y": 166, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y43": { + "bits": {}, + "grid_x": 109, + "grid_y": 165, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y44": { + "bits": {}, + "grid_x": 109, + "grid_y": 164, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y46": { + "bits": {}, + "grid_x": 109, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y47": { + "bits": {}, + "grid_x": 109, + "grid_y": 161, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y48": { + "bits": {}, + "grid_x": 109, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y49": { + "bits": {}, + "grid_x": 109, + "grid_y": 159, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y5": { + "bits": {}, + "grid_x": 109, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y50": { + "bits": {}, + "grid_x": 109, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y52": { + "bits": {}, + "grid_x": 109, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y54": { + "bits": {}, + "grid_x": 109, + "grid_y": 154, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y55": { + "bits": {}, + "grid_x": 109, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y56": { + "bits": {}, + "grid_x": 109, + "grid_y": 152, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y57": { + "bits": {}, + "grid_x": 109, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y58": { + "bits": {}, + "grid_x": 109, + "grid_y": 150, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y59": { + "bits": {}, + "grid_x": 109, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y6": { + "bits": {}, + "grid_x": 109, + "grid_y": 202, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y61": { + "bits": {}, + "grid_x": 109, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y62": { + "bits": {}, + "grid_x": 109, + "grid_y": 146, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y63": { + "bits": {}, + "grid_x": 109, + "grid_y": 145, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y64": { + "bits": {}, + "grid_x": 109, + "grid_y": 144, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y65": { + "bits": {}, + "grid_x": 109, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y66": { + "bits": {}, + "grid_x": 109, + "grid_y": 142, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y67": { + "bits": {}, + "grid_x": 109, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y68": { + "bits": {}, + "grid_x": 109, + "grid_y": 140, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y69": { + "bits": {}, + "grid_x": 109, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y7": { + "bits": {}, + "grid_x": 109, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y70": { + "bits": {}, + "grid_x": 109, + "grid_y": 138, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y71": { + "bits": {}, + "grid_x": 109, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y73": { + "bits": {}, + "grid_x": 109, + "grid_y": 135, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y74": { + "bits": {}, + "grid_x": 109, + "grid_y": 134, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y75": { + "bits": {}, + "grid_x": 109, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y76": { + "bits": {}, + "grid_x": 109, + "grid_y": 132, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y77": { + "bits": {}, + "grid_x": 109, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y79": { + "bits": {}, + "grid_x": 109, + "grid_y": 129, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y80": { + "bits": {}, + "grid_x": 109, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y81": { + "bits": {}, + "grid_x": 109, + "grid_y": 127, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y82": { + "bits": {}, + "grid_x": 109, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y83": { + "bits": {}, + "grid_x": 109, + "grid_y": 125, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y84": { + "bits": {}, + "grid_x": 109, + "grid_y": 124, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y86": { + "bits": {}, + "grid_x": 109, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y87": { + "bits": {}, + "grid_x": 109, + "grid_y": 121, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y88": { + "bits": {}, + "grid_x": 109, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y89": { + "bits": {}, + "grid_x": 109, + "grid_y": 119, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y9": { + "bits": {}, + "grid_x": 109, + "grid_y": 199, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y90": { + "bits": {}, + "grid_x": 109, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y91": { + "bits": {}, + "grid_x": 109, + "grid_y": 117, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y92": { + "bits": {}, + "grid_x": 109, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y93": { + "bits": {}, + "grid_x": 109, + "grid_y": 115, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y94": { + "bits": {}, + "grid_x": 109, + "grid_y": 114, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y95": { + "bits": {}, + "grid_x": 109, + "grid_y": 113, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y96": { + "bits": {}, + "grid_x": 109, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y98": { + "bits": {}, + "grid_x": 109, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X109Y99": { + "bits": {}, + "grid_x": 109, + "grid_y": 109, + "sites": {}, + "type": "NULL" + }, + "NULL_X10Y0": { + "bits": {}, + "grid_x": 10, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X10Y208": { + "bits": {}, + "grid_x": 10, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y0": { + "bits": {}, + "grid_x": 110, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y104": { + "bits": {}, + "grid_x": 110, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y105": { + "bits": {}, + "grid_x": 110, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y106": { + "bits": {}, + "grid_x": 110, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y107": { + "bits": {}, + "grid_x": 110, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y108": { + "bits": {}, + "grid_x": 110, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y109": { + "bits": {}, + "grid_x": 110, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y110": { + "bits": {}, + "grid_x": 110, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y111": { + "bits": {}, + "grid_x": 110, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y112": { + "bits": {}, + "grid_x": 110, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y113": { + "bits": {}, + "grid_x": 110, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y114": { + "bits": {}, + "grid_x": 110, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y115": { + "bits": {}, + "grid_x": 110, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y116": { + "bits": {}, + "grid_x": 110, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y117": { + "bits": {}, + "grid_x": 110, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y118": { + "bits": {}, + "grid_x": 110, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y119": { + "bits": {}, + "grid_x": 110, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y120": { + "bits": {}, + "grid_x": 110, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y121": { + "bits": {}, + "grid_x": 110, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y122": { + "bits": {}, + "grid_x": 110, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y123": { + "bits": {}, + "grid_x": 110, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y124": { + "bits": {}, + "grid_x": 110, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y125": { + "bits": {}, + "grid_x": 110, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y126": { + "bits": {}, + "grid_x": 110, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y127": { + "bits": {}, + "grid_x": 110, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y128": { + "bits": {}, + "grid_x": 110, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y129": { + "bits": {}, + "grid_x": 110, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y130": { + "bits": {}, + "grid_x": 110, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y131": { + "bits": {}, + "grid_x": 110, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y132": { + "bits": {}, + "grid_x": 110, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y133": { + "bits": {}, + "grid_x": 110, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y134": { + "bits": {}, + "grid_x": 110, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y135": { + "bits": {}, + "grid_x": 110, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y136": { + "bits": {}, + "grid_x": 110, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y137": { + "bits": {}, + "grid_x": 110, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y138": { + "bits": {}, + "grid_x": 110, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y139": { + "bits": {}, + "grid_x": 110, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y140": { + "bits": {}, + "grid_x": 110, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y141": { + "bits": {}, + "grid_x": 110, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y142": { + "bits": {}, + "grid_x": 110, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y143": { + "bits": {}, + "grid_x": 110, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y144": { + "bits": {}, + "grid_x": 110, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y145": { + "bits": {}, + "grid_x": 110, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y146": { + "bits": {}, + "grid_x": 110, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y147": { + "bits": {}, + "grid_x": 110, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y148": { + "bits": {}, + "grid_x": 110, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y149": { + "bits": {}, + "grid_x": 110, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y150": { + "bits": {}, + "grid_x": 110, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y151": { + "bits": {}, + "grid_x": 110, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y152": { + "bits": {}, + "grid_x": 110, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y153": { + "bits": {}, + "grid_x": 110, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y154": { + "bits": {}, + "grid_x": 110, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y155": { + "bits": {}, + "grid_x": 110, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y156": { + "bits": {}, + "grid_x": 110, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y157": { + "bits": {}, + "grid_x": 110, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y158": { + "bits": {}, + "grid_x": 110, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y159": { + "bits": {}, + "grid_x": 110, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y160": { + "bits": {}, + "grid_x": 110, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y161": { + "bits": {}, + "grid_x": 110, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y162": { + "bits": {}, + "grid_x": 110, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y163": { + "bits": {}, + "grid_x": 110, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y164": { + "bits": {}, + "grid_x": 110, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y165": { + "bits": {}, + "grid_x": 110, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y166": { + "bits": {}, + "grid_x": 110, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y167": { + "bits": {}, + "grid_x": 110, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y168": { + "bits": {}, + "grid_x": 110, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y169": { + "bits": {}, + "grid_x": 110, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y170": { + "bits": {}, + "grid_x": 110, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y171": { + "bits": {}, + "grid_x": 110, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y172": { + "bits": {}, + "grid_x": 110, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y173": { + "bits": {}, + "grid_x": 110, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y174": { + "bits": {}, + "grid_x": 110, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y175": { + "bits": {}, + "grid_x": 110, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y176": { + "bits": {}, + "grid_x": 110, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y177": { + "bits": {}, + "grid_x": 110, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y178": { + "bits": {}, + "grid_x": 110, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y179": { + "bits": {}, + "grid_x": 110, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y180": { + "bits": {}, + "grid_x": 110, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y181": { + "bits": {}, + "grid_x": 110, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y182": { + "bits": {}, + "grid_x": 110, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y183": { + "bits": {}, + "grid_x": 110, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y184": { + "bits": {}, + "grid_x": 110, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y185": { + "bits": {}, + "grid_x": 110, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y186": { + "bits": {}, + "grid_x": 110, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y187": { + "bits": {}, + "grid_x": 110, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y188": { + "bits": {}, + "grid_x": 110, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y189": { + "bits": {}, + "grid_x": 110, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y190": { + "bits": {}, + "grid_x": 110, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y191": { + "bits": {}, + "grid_x": 110, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y192": { + "bits": {}, + "grid_x": 110, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y193": { + "bits": {}, + "grid_x": 110, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y194": { + "bits": {}, + "grid_x": 110, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y195": { + "bits": {}, + "grid_x": 110, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y196": { + "bits": {}, + "grid_x": 110, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y197": { + "bits": {}, + "grid_x": 110, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y198": { + "bits": {}, + "grid_x": 110, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y199": { + "bits": {}, + "grid_x": 110, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y200": { + "bits": {}, + "grid_x": 110, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y201": { + "bits": {}, + "grid_x": 110, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y202": { + "bits": {}, + "grid_x": 110, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y203": { + "bits": {}, + "grid_x": 110, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y204": { + "bits": {}, + "grid_x": 110, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y205": { + "bits": {}, + "grid_x": 110, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y206": { + "bits": {}, + "grid_x": 110, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y207": { + "bits": {}, + "grid_x": 110, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y208": { + "bits": {}, + "grid_x": 110, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X110Y52": { + "bits": {}, + "grid_x": 110, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y105": { + "bits": {}, + "grid_x": 111, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y106": { + "bits": {}, + "grid_x": 111, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y107": { + "bits": {}, + "grid_x": 111, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y108": { + "bits": {}, + "grid_x": 111, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y109": { + "bits": {}, + "grid_x": 111, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y110": { + "bits": {}, + "grid_x": 111, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y111": { + "bits": {}, + "grid_x": 111, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y112": { + "bits": {}, + "grid_x": 111, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y113": { + "bits": {}, + "grid_x": 111, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y114": { + "bits": {}, + "grid_x": 111, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y115": { + "bits": {}, + "grid_x": 111, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y116": { + "bits": {}, + "grid_x": 111, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y117": { + "bits": {}, + "grid_x": 111, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y118": { + "bits": {}, + "grid_x": 111, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y119": { + "bits": {}, + "grid_x": 111, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y120": { + "bits": {}, + "grid_x": 111, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y121": { + "bits": {}, + "grid_x": 111, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y122": { + "bits": {}, + "grid_x": 111, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y123": { + "bits": {}, + "grid_x": 111, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y124": { + "bits": {}, + "grid_x": 111, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y125": { + "bits": {}, + "grid_x": 111, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y126": { + "bits": {}, + "grid_x": 111, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y127": { + "bits": {}, + "grid_x": 111, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y128": { + "bits": {}, + "grid_x": 111, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y129": { + "bits": {}, + "grid_x": 111, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y130": { + "bits": {}, + "grid_x": 111, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y131": { + "bits": {}, + "grid_x": 111, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y132": { + "bits": {}, + "grid_x": 111, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y133": { + "bits": {}, + "grid_x": 111, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y134": { + "bits": {}, + "grid_x": 111, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y135": { + "bits": {}, + "grid_x": 111, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y136": { + "bits": {}, + "grid_x": 111, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y137": { + "bits": {}, + "grid_x": 111, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y138": { + "bits": {}, + "grid_x": 111, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y139": { + "bits": {}, + "grid_x": 111, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y140": { + "bits": {}, + "grid_x": 111, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y141": { + "bits": {}, + "grid_x": 111, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y142": { + "bits": {}, + "grid_x": 111, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y143": { + "bits": {}, + "grid_x": 111, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y144": { + "bits": {}, + "grid_x": 111, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y145": { + "bits": {}, + "grid_x": 111, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y146": { + "bits": {}, + "grid_x": 111, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y147": { + "bits": {}, + "grid_x": 111, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y148": { + "bits": {}, + "grid_x": 111, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y149": { + "bits": {}, + "grid_x": 111, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y150": { + "bits": {}, + "grid_x": 111, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y151": { + "bits": {}, + "grid_x": 111, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y152": { + "bits": {}, + "grid_x": 111, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y153": { + "bits": {}, + "grid_x": 111, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y154": { + "bits": {}, + "grid_x": 111, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y155": { + "bits": {}, + "grid_x": 111, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y156": { + "bits": {}, + "grid_x": 111, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y157": { + "bits": {}, + "grid_x": 111, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y158": { + "bits": {}, + "grid_x": 111, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y159": { + "bits": {}, + "grid_x": 111, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y160": { + "bits": {}, + "grid_x": 111, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y161": { + "bits": {}, + "grid_x": 111, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y162": { + "bits": {}, + "grid_x": 111, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y163": { + "bits": {}, + "grid_x": 111, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y164": { + "bits": {}, + "grid_x": 111, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y165": { + "bits": {}, + "grid_x": 111, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y166": { + "bits": {}, + "grid_x": 111, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y167": { + "bits": {}, + "grid_x": 111, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y168": { + "bits": {}, + "grid_x": 111, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y169": { + "bits": {}, + "grid_x": 111, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y170": { + "bits": {}, + "grid_x": 111, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y171": { + "bits": {}, + "grid_x": 111, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y172": { + "bits": {}, + "grid_x": 111, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y173": { + "bits": {}, + "grid_x": 111, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y174": { + "bits": {}, + "grid_x": 111, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y175": { + "bits": {}, + "grid_x": 111, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y176": { + "bits": {}, + "grid_x": 111, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y177": { + "bits": {}, + "grid_x": 111, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y178": { + "bits": {}, + "grid_x": 111, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y179": { + "bits": {}, + "grid_x": 111, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y180": { + "bits": {}, + "grid_x": 111, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y181": { + "bits": {}, + "grid_x": 111, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y182": { + "bits": {}, + "grid_x": 111, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y183": { + "bits": {}, + "grid_x": 111, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y184": { + "bits": {}, + "grid_x": 111, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y185": { + "bits": {}, + "grid_x": 111, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y186": { + "bits": {}, + "grid_x": 111, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y187": { + "bits": {}, + "grid_x": 111, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y188": { + "bits": {}, + "grid_x": 111, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y189": { + "bits": {}, + "grid_x": 111, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y190": { + "bits": {}, + "grid_x": 111, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y191": { + "bits": {}, + "grid_x": 111, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y192": { + "bits": {}, + "grid_x": 111, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y193": { + "bits": {}, + "grid_x": 111, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y194": { + "bits": {}, + "grid_x": 111, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y195": { + "bits": {}, + "grid_x": 111, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y196": { + "bits": {}, + "grid_x": 111, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y197": { + "bits": {}, + "grid_x": 111, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y198": { + "bits": {}, + "grid_x": 111, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y199": { + "bits": {}, + "grid_x": 111, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y200": { + "bits": {}, + "grid_x": 111, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y201": { + "bits": {}, + "grid_x": 111, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y202": { + "bits": {}, + "grid_x": 111, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y203": { + "bits": {}, + "grid_x": 111, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y204": { + "bits": {}, + "grid_x": 111, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y205": { + "bits": {}, + "grid_x": 111, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y206": { + "bits": {}, + "grid_x": 111, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y207": { + "bits": {}, + "grid_x": 111, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X111Y208": { + "bits": {}, + "grid_x": 111, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y105": { + "bits": {}, + "grid_x": 112, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y106": { + "bits": {}, + "grid_x": 112, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y107": { + "bits": {}, + "grid_x": 112, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y108": { + "bits": {}, + "grid_x": 112, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y109": { + "bits": {}, + "grid_x": 112, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y110": { + "bits": {}, + "grid_x": 112, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y111": { + "bits": {}, + "grid_x": 112, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y112": { + "bits": {}, + "grid_x": 112, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y113": { + "bits": {}, + "grid_x": 112, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y114": { + "bits": {}, + "grid_x": 112, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y115": { + "bits": {}, + "grid_x": 112, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y116": { + "bits": {}, + "grid_x": 112, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y117": { + "bits": {}, + "grid_x": 112, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y118": { + "bits": {}, + "grid_x": 112, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y119": { + "bits": {}, + "grid_x": 112, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y120": { + "bits": {}, + "grid_x": 112, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y121": { + "bits": {}, + "grid_x": 112, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y122": { + "bits": {}, + "grid_x": 112, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y123": { + "bits": {}, + "grid_x": 112, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y124": { + "bits": {}, + "grid_x": 112, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y125": { + "bits": {}, + "grid_x": 112, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y126": { + "bits": {}, + "grid_x": 112, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y127": { + "bits": {}, + "grid_x": 112, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y128": { + "bits": {}, + "grid_x": 112, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y129": { + "bits": {}, + "grid_x": 112, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y130": { + "bits": {}, + "grid_x": 112, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y131": { + "bits": {}, + "grid_x": 112, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y132": { + "bits": {}, + "grid_x": 112, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y133": { + "bits": {}, + "grid_x": 112, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y134": { + "bits": {}, + "grid_x": 112, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y135": { + "bits": {}, + "grid_x": 112, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y136": { + "bits": {}, + "grid_x": 112, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y137": { + "bits": {}, + "grid_x": 112, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y138": { + "bits": {}, + "grid_x": 112, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y139": { + "bits": {}, + "grid_x": 112, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y140": { + "bits": {}, + "grid_x": 112, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y141": { + "bits": {}, + "grid_x": 112, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y142": { + "bits": {}, + "grid_x": 112, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y143": { + "bits": {}, + "grid_x": 112, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y144": { + "bits": {}, + "grid_x": 112, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y145": { + "bits": {}, + "grid_x": 112, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y146": { + "bits": {}, + "grid_x": 112, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y147": { + "bits": {}, + "grid_x": 112, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y148": { + "bits": {}, + "grid_x": 112, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y149": { + "bits": {}, + "grid_x": 112, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y150": { + "bits": {}, + "grid_x": 112, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y151": { + "bits": {}, + "grid_x": 112, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y152": { + "bits": {}, + "grid_x": 112, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y153": { + "bits": {}, + "grid_x": 112, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y154": { + "bits": {}, + "grid_x": 112, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y155": { + "bits": {}, + "grid_x": 112, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y156": { + "bits": {}, + "grid_x": 112, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y157": { + "bits": {}, + "grid_x": 112, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y158": { + "bits": {}, + "grid_x": 112, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y159": { + "bits": {}, + "grid_x": 112, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y160": { + "bits": {}, + "grid_x": 112, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y161": { + "bits": {}, + "grid_x": 112, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y162": { + "bits": {}, + "grid_x": 112, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y163": { + "bits": {}, + "grid_x": 112, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y164": { + "bits": {}, + "grid_x": 112, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y165": { + "bits": {}, + "grid_x": 112, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y166": { + "bits": {}, + "grid_x": 112, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y167": { + "bits": {}, + "grid_x": 112, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y168": { + "bits": {}, + "grid_x": 112, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y169": { + "bits": {}, + "grid_x": 112, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y170": { + "bits": {}, + "grid_x": 112, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y171": { + "bits": {}, + "grid_x": 112, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y172": { + "bits": {}, + "grid_x": 112, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y173": { + "bits": {}, + "grid_x": 112, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y174": { + "bits": {}, + "grid_x": 112, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y175": { + "bits": {}, + "grid_x": 112, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y176": { + "bits": {}, + "grid_x": 112, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y177": { + "bits": {}, + "grid_x": 112, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y178": { + "bits": {}, + "grid_x": 112, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y179": { + "bits": {}, + "grid_x": 112, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y180": { + "bits": {}, + "grid_x": 112, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y181": { + "bits": {}, + "grid_x": 112, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y182": { + "bits": {}, + "grid_x": 112, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y183": { + "bits": {}, + "grid_x": 112, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y184": { + "bits": {}, + "grid_x": 112, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y185": { + "bits": {}, + "grid_x": 112, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y186": { + "bits": {}, + "grid_x": 112, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y187": { + "bits": {}, + "grid_x": 112, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y188": { + "bits": {}, + "grid_x": 112, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y189": { + "bits": {}, + "grid_x": 112, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y190": { + "bits": {}, + "grid_x": 112, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y191": { + "bits": {}, + "grid_x": 112, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y192": { + "bits": {}, + "grid_x": 112, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y193": { + "bits": {}, + "grid_x": 112, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y194": { + "bits": {}, + "grid_x": 112, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y195": { + "bits": {}, + "grid_x": 112, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y196": { + "bits": {}, + "grid_x": 112, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y197": { + "bits": {}, + "grid_x": 112, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y198": { + "bits": {}, + "grid_x": 112, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y199": { + "bits": {}, + "grid_x": 112, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y200": { + "bits": {}, + "grid_x": 112, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y201": { + "bits": {}, + "grid_x": 112, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y202": { + "bits": {}, + "grid_x": 112, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y203": { + "bits": {}, + "grid_x": 112, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y204": { + "bits": {}, + "grid_x": 112, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y205": { + "bits": {}, + "grid_x": 112, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y206": { + "bits": {}, + "grid_x": 112, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y207": { + "bits": {}, + "grid_x": 112, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X112Y208": { + "bits": {}, + "grid_x": 112, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y0": { + "bits": {}, + "grid_x": 113, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y104": { + "bits": {}, + "grid_x": 113, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y105": { + "bits": {}, + "grid_x": 113, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y106": { + "bits": {}, + "grid_x": 113, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y107": { + "bits": {}, + "grid_x": 113, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y108": { + "bits": {}, + "grid_x": 113, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y109": { + "bits": {}, + "grid_x": 113, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y110": { + "bits": {}, + "grid_x": 113, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y111": { + "bits": {}, + "grid_x": 113, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y112": { + "bits": {}, + "grid_x": 113, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y113": { + "bits": {}, + "grid_x": 113, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y114": { + "bits": {}, + "grid_x": 113, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y115": { + "bits": {}, + "grid_x": 113, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y116": { + "bits": {}, + "grid_x": 113, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y117": { + "bits": {}, + "grid_x": 113, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y118": { + "bits": {}, + "grid_x": 113, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y119": { + "bits": {}, + "grid_x": 113, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y120": { + "bits": {}, + "grid_x": 113, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y121": { + "bits": {}, + "grid_x": 113, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y122": { + "bits": {}, + "grid_x": 113, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y123": { + "bits": {}, + "grid_x": 113, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y124": { + "bits": {}, + "grid_x": 113, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y125": { + "bits": {}, + "grid_x": 113, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y126": { + "bits": {}, + "grid_x": 113, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y127": { + "bits": {}, + "grid_x": 113, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y128": { + "bits": {}, + "grid_x": 113, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y129": { + "bits": {}, + "grid_x": 113, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y130": { + "bits": {}, + "grid_x": 113, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y131": { + "bits": {}, + "grid_x": 113, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y132": { + "bits": {}, + "grid_x": 113, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y133": { + "bits": {}, + "grid_x": 113, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y134": { + "bits": {}, + "grid_x": 113, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y135": { + "bits": {}, + "grid_x": 113, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y136": { + "bits": {}, + "grid_x": 113, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y137": { + "bits": {}, + "grid_x": 113, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y138": { + "bits": {}, + "grid_x": 113, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y139": { + "bits": {}, + "grid_x": 113, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y140": { + "bits": {}, + "grid_x": 113, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y141": { + "bits": {}, + "grid_x": 113, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y142": { + "bits": {}, + "grid_x": 113, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y143": { + "bits": {}, + "grid_x": 113, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y144": { + "bits": {}, + "grid_x": 113, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y145": { + "bits": {}, + "grid_x": 113, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y146": { + "bits": {}, + "grid_x": 113, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y147": { + "bits": {}, + "grid_x": 113, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y148": { + "bits": {}, + "grid_x": 113, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y149": { + "bits": {}, + "grid_x": 113, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y150": { + "bits": {}, + "grid_x": 113, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y151": { + "bits": {}, + "grid_x": 113, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y152": { + "bits": {}, + "grid_x": 113, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y153": { + "bits": {}, + "grid_x": 113, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y154": { + "bits": {}, + "grid_x": 113, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y155": { + "bits": {}, + "grid_x": 113, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y156": { + "bits": {}, + "grid_x": 113, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y157": { + "bits": {}, + "grid_x": 113, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y158": { + "bits": {}, + "grid_x": 113, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y159": { + "bits": {}, + "grid_x": 113, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y160": { + "bits": {}, + "grid_x": 113, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y161": { + "bits": {}, + "grid_x": 113, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y162": { + "bits": {}, + "grid_x": 113, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y163": { + "bits": {}, + "grid_x": 113, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y164": { + "bits": {}, + "grid_x": 113, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y165": { + "bits": {}, + "grid_x": 113, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y166": { + "bits": {}, + "grid_x": 113, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y167": { + "bits": {}, + "grid_x": 113, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y168": { + "bits": {}, + "grid_x": 113, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y169": { + "bits": {}, + "grid_x": 113, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y170": { + "bits": {}, + "grid_x": 113, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y171": { + "bits": {}, + "grid_x": 113, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y172": { + "bits": {}, + "grid_x": 113, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y173": { + "bits": {}, + "grid_x": 113, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y174": { + "bits": {}, + "grid_x": 113, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y175": { + "bits": {}, + "grid_x": 113, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y176": { + "bits": {}, + "grid_x": 113, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y177": { + "bits": {}, + "grid_x": 113, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y178": { + "bits": {}, + "grid_x": 113, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y179": { + "bits": {}, + "grid_x": 113, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y180": { + "bits": {}, + "grid_x": 113, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y181": { + "bits": {}, + "grid_x": 113, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y182": { + "bits": {}, + "grid_x": 113, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y183": { + "bits": {}, + "grid_x": 113, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y184": { + "bits": {}, + "grid_x": 113, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y185": { + "bits": {}, + "grid_x": 113, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y186": { + "bits": {}, + "grid_x": 113, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y187": { + "bits": {}, + "grid_x": 113, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y188": { + "bits": {}, + "grid_x": 113, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y189": { + "bits": {}, + "grid_x": 113, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y190": { + "bits": {}, + "grid_x": 113, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y191": { + "bits": {}, + "grid_x": 113, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y192": { + "bits": {}, + "grid_x": 113, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y193": { + "bits": {}, + "grid_x": 113, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y194": { + "bits": {}, + "grid_x": 113, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y195": { + "bits": {}, + "grid_x": 113, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y196": { + "bits": {}, + "grid_x": 113, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y197": { + "bits": {}, + "grid_x": 113, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y198": { + "bits": {}, + "grid_x": 113, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y199": { + "bits": {}, + "grid_x": 113, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y200": { + "bits": {}, + "grid_x": 113, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y201": { + "bits": {}, + "grid_x": 113, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y202": { + "bits": {}, + "grid_x": 113, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y203": { + "bits": {}, + "grid_x": 113, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y204": { + "bits": {}, + "grid_x": 113, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y205": { + "bits": {}, + "grid_x": 113, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y206": { + "bits": {}, + "grid_x": 113, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y207": { + "bits": {}, + "grid_x": 113, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y208": { + "bits": {}, + "grid_x": 113, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X113Y52": { + "bits": {}, + "grid_x": 113, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y0": { + "bits": {}, + "grid_x": 114, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y104": { + "bits": {}, + "grid_x": 114, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y105": { + "bits": {}, + "grid_x": 114, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y106": { + "bits": {}, + "grid_x": 114, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y107": { + "bits": {}, + "grid_x": 114, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y108": { + "bits": {}, + "grid_x": 114, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y109": { + "bits": {}, + "grid_x": 114, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y110": { + "bits": {}, + "grid_x": 114, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y111": { + "bits": {}, + "grid_x": 114, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y112": { + "bits": {}, + "grid_x": 114, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y113": { + "bits": {}, + "grid_x": 114, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y114": { + "bits": {}, + "grid_x": 114, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y115": { + "bits": {}, + "grid_x": 114, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y116": { + "bits": {}, + "grid_x": 114, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y117": { + "bits": {}, + "grid_x": 114, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y118": { + "bits": {}, + "grid_x": 114, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y119": { + "bits": {}, + "grid_x": 114, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y120": { + "bits": {}, + "grid_x": 114, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y121": { + "bits": {}, + "grid_x": 114, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y122": { + "bits": {}, + "grid_x": 114, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y123": { + "bits": {}, + "grid_x": 114, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y124": { + "bits": {}, + "grid_x": 114, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y125": { + "bits": {}, + "grid_x": 114, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y126": { + "bits": {}, + "grid_x": 114, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y127": { + "bits": {}, + "grid_x": 114, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y128": { + "bits": {}, + "grid_x": 114, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y129": { + "bits": {}, + "grid_x": 114, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y130": { + "bits": {}, + "grid_x": 114, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y131": { + "bits": {}, + "grid_x": 114, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y132": { + "bits": {}, + "grid_x": 114, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y133": { + "bits": {}, + "grid_x": 114, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y134": { + "bits": {}, + "grid_x": 114, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y135": { + "bits": {}, + "grid_x": 114, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y136": { + "bits": {}, + "grid_x": 114, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y137": { + "bits": {}, + "grid_x": 114, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y138": { + "bits": {}, + "grid_x": 114, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y139": { + "bits": {}, + "grid_x": 114, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y140": { + "bits": {}, + "grid_x": 114, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y141": { + "bits": {}, + "grid_x": 114, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y142": { + "bits": {}, + "grid_x": 114, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y143": { + "bits": {}, + "grid_x": 114, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y144": { + "bits": {}, + "grid_x": 114, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y145": { + "bits": {}, + "grid_x": 114, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y146": { + "bits": {}, + "grid_x": 114, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y147": { + "bits": {}, + "grid_x": 114, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y148": { + "bits": {}, + "grid_x": 114, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y149": { + "bits": {}, + "grid_x": 114, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y150": { + "bits": {}, + "grid_x": 114, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y151": { + "bits": {}, + "grid_x": 114, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y152": { + "bits": {}, + "grid_x": 114, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y153": { + "bits": {}, + "grid_x": 114, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y154": { + "bits": {}, + "grid_x": 114, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y155": { + "bits": {}, + "grid_x": 114, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y156": { + "bits": {}, + "grid_x": 114, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y157": { + "bits": {}, + "grid_x": 114, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y158": { + "bits": {}, + "grid_x": 114, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y159": { + "bits": {}, + "grid_x": 114, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y160": { + "bits": {}, + "grid_x": 114, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y161": { + "bits": {}, + "grid_x": 114, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y162": { + "bits": {}, + "grid_x": 114, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y163": { + "bits": {}, + "grid_x": 114, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y164": { + "bits": {}, + "grid_x": 114, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y165": { + "bits": {}, + "grid_x": 114, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y166": { + "bits": {}, + "grid_x": 114, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y167": { + "bits": {}, + "grid_x": 114, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y168": { + "bits": {}, + "grid_x": 114, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y169": { + "bits": {}, + "grid_x": 114, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y170": { + "bits": {}, + "grid_x": 114, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y171": { + "bits": {}, + "grid_x": 114, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y172": { + "bits": {}, + "grid_x": 114, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y173": { + "bits": {}, + "grid_x": 114, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y174": { + "bits": {}, + "grid_x": 114, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y175": { + "bits": {}, + "grid_x": 114, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y176": { + "bits": {}, + "grid_x": 114, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y177": { + "bits": {}, + "grid_x": 114, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y178": { + "bits": {}, + "grid_x": 114, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y179": { + "bits": {}, + "grid_x": 114, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y180": { + "bits": {}, + "grid_x": 114, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y181": { + "bits": {}, + "grid_x": 114, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y182": { + "bits": {}, + "grid_x": 114, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y183": { + "bits": {}, + "grid_x": 114, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y184": { + "bits": {}, + "grid_x": 114, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y185": { + "bits": {}, + "grid_x": 114, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y186": { + "bits": {}, + "grid_x": 114, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y187": { + "bits": {}, + "grid_x": 114, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y188": { + "bits": {}, + "grid_x": 114, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y189": { + "bits": {}, + "grid_x": 114, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y190": { + "bits": {}, + "grid_x": 114, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y191": { + "bits": {}, + "grid_x": 114, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y192": { + "bits": {}, + "grid_x": 114, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y193": { + "bits": {}, + "grid_x": 114, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y194": { + "bits": {}, + "grid_x": 114, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y195": { + "bits": {}, + "grid_x": 114, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y196": { + "bits": {}, + "grid_x": 114, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y197": { + "bits": {}, + "grid_x": 114, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y198": { + "bits": {}, + "grid_x": 114, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y199": { + "bits": {}, + "grid_x": 114, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y200": { + "bits": {}, + "grid_x": 114, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y201": { + "bits": {}, + "grid_x": 114, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y202": { + "bits": {}, + "grid_x": 114, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y203": { + "bits": {}, + "grid_x": 114, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y204": { + "bits": {}, + "grid_x": 114, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y205": { + "bits": {}, + "grid_x": 114, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y206": { + "bits": {}, + "grid_x": 114, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y207": { + "bits": {}, + "grid_x": 114, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y208": { + "bits": {}, + "grid_x": 114, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X114Y52": { + "bits": {}, + "grid_x": 114, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y0": { + "bits": {}, + "grid_x": 115, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y100": { + "bits": {}, + "grid_x": 115, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y102": { + "bits": {}, + "grid_x": 115, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y104": { + "bits": {}, + "grid_x": 115, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y105": { + "bits": {}, + "grid_x": 115, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y106": { + "bits": {}, + "grid_x": 115, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y107": { + "bits": {}, + "grid_x": 115, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y108": { + "bits": {}, + "grid_x": 115, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y109": { + "bits": {}, + "grid_x": 115, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y11": { + "bits": {}, + "grid_x": 115, + "grid_y": 197, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y110": { + "bits": {}, + "grid_x": 115, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y111": { + "bits": {}, + "grid_x": 115, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y112": { + "bits": {}, + "grid_x": 115, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y113": { + "bits": {}, + "grid_x": 115, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y114": { + "bits": {}, + "grid_x": 115, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y115": { + "bits": {}, + "grid_x": 115, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y116": { + "bits": {}, + "grid_x": 115, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y117": { + "bits": {}, + "grid_x": 115, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y118": { + "bits": {}, + "grid_x": 115, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y119": { + "bits": {}, + "grid_x": 115, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y120": { + "bits": {}, + "grid_x": 115, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y121": { + "bits": {}, + "grid_x": 115, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y122": { + "bits": {}, + "grid_x": 115, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y123": { + "bits": {}, + "grid_x": 115, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y124": { + "bits": {}, + "grid_x": 115, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y125": { + "bits": {}, + "grid_x": 115, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y126": { + "bits": {}, + "grid_x": 115, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y127": { + "bits": {}, + "grid_x": 115, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y128": { + "bits": {}, + "grid_x": 115, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y129": { + "bits": {}, + "grid_x": 115, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y13": { + "bits": {}, + "grid_x": 115, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y130": { + "bits": {}, + "grid_x": 115, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y131": { + "bits": {}, + "grid_x": 115, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y132": { + "bits": {}, + "grid_x": 115, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y133": { + "bits": {}, + "grid_x": 115, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y134": { + "bits": {}, + "grid_x": 115, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y135": { + "bits": {}, + "grid_x": 115, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y136": { + "bits": {}, + "grid_x": 115, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y137": { + "bits": {}, + "grid_x": 115, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y138": { + "bits": {}, + "grid_x": 115, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y139": { + "bits": {}, + "grid_x": 115, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y140": { + "bits": {}, + "grid_x": 115, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y141": { + "bits": {}, + "grid_x": 115, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y142": { + "bits": {}, + "grid_x": 115, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y143": { + "bits": {}, + "grid_x": 115, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y144": { + "bits": {}, + "grid_x": 115, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y145": { + "bits": {}, + "grid_x": 115, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y146": { + "bits": {}, + "grid_x": 115, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y147": { + "bits": {}, + "grid_x": 115, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y148": { + "bits": {}, + "grid_x": 115, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y149": { + "bits": {}, + "grid_x": 115, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y15": { + "bits": {}, + "grid_x": 115, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y150": { + "bits": {}, + "grid_x": 115, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y151": { + "bits": {}, + "grid_x": 115, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y152": { + "bits": {}, + "grid_x": 115, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y153": { + "bits": {}, + "grid_x": 115, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y154": { + "bits": {}, + "grid_x": 115, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y155": { + "bits": {}, + "grid_x": 115, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y156": { + "bits": {}, + "grid_x": 115, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y157": { + "bits": {}, + "grid_x": 115, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y158": { + "bits": {}, + "grid_x": 115, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y159": { + "bits": {}, + "grid_x": 115, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y160": { + "bits": {}, + "grid_x": 115, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y161": { + "bits": {}, + "grid_x": 115, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y162": { + "bits": {}, + "grid_x": 115, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y163": { + "bits": {}, + "grid_x": 115, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y164": { + "bits": {}, + "grid_x": 115, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y165": { + "bits": {}, + "grid_x": 115, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y166": { + "bits": {}, + "grid_x": 115, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y167": { + "bits": {}, + "grid_x": 115, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y168": { + "bits": {}, + "grid_x": 115, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y169": { + "bits": {}, + "grid_x": 115, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y17": { + "bits": {}, + "grid_x": 115, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y170": { + "bits": {}, + "grid_x": 115, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y171": { + "bits": {}, + "grid_x": 115, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y172": { + "bits": {}, + "grid_x": 115, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y173": { + "bits": {}, + "grid_x": 115, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y174": { + "bits": {}, + "grid_x": 115, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y175": { + "bits": {}, + "grid_x": 115, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y176": { + "bits": {}, + "grid_x": 115, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y177": { + "bits": {}, + "grid_x": 115, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y178": { + "bits": {}, + "grid_x": 115, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y179": { + "bits": {}, + "grid_x": 115, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y180": { + "bits": {}, + "grid_x": 115, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y181": { + "bits": {}, + "grid_x": 115, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y182": { + "bits": {}, + "grid_x": 115, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y183": { + "bits": {}, + "grid_x": 115, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y184": { + "bits": {}, + "grid_x": 115, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y185": { + "bits": {}, + "grid_x": 115, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y186": { + "bits": {}, + "grid_x": 115, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y187": { + "bits": {}, + "grid_x": 115, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y188": { + "bits": {}, + "grid_x": 115, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y189": { + "bits": {}, + "grid_x": 115, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y19": { + "bits": {}, + "grid_x": 115, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y190": { + "bits": {}, + "grid_x": 115, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y191": { + "bits": {}, + "grid_x": 115, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y192": { + "bits": {}, + "grid_x": 115, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y193": { + "bits": {}, + "grid_x": 115, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y194": { + "bits": {}, + "grid_x": 115, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y195": { + "bits": {}, + "grid_x": 115, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y196": { + "bits": {}, + "grid_x": 115, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y197": { + "bits": {}, + "grid_x": 115, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y198": { + "bits": {}, + "grid_x": 115, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y199": { + "bits": {}, + "grid_x": 115, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y200": { + "bits": {}, + "grid_x": 115, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y201": { + "bits": {}, + "grid_x": 115, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y202": { + "bits": {}, + "grid_x": 115, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y203": { + "bits": {}, + "grid_x": 115, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y204": { + "bits": {}, + "grid_x": 115, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y205": { + "bits": {}, + "grid_x": 115, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y206": { + "bits": {}, + "grid_x": 115, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y207": { + "bits": {}, + "grid_x": 115, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y208": { + "bits": {}, + "grid_x": 115, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y21": { + "bits": {}, + "grid_x": 115, + "grid_y": 187, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y23": { + "bits": {}, + "grid_x": 115, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y25": { + "bits": {}, + "grid_x": 115, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y28": { + "bits": {}, + "grid_x": 115, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y3": { + "bits": {}, + "grid_x": 115, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y30": { + "bits": {}, + "grid_x": 115, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y32": { + "bits": {}, + "grid_x": 115, + "grid_y": 176, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y34": { + "bits": {}, + "grid_x": 115, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y36": { + "bits": {}, + "grid_x": 115, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y38": { + "bits": {}, + "grid_x": 115, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y40": { + "bits": {}, + "grid_x": 115, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y42": { + "bits": {}, + "grid_x": 115, + "grid_y": 166, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y44": { + "bits": {}, + "grid_x": 115, + "grid_y": 164, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y46": { + "bits": {}, + "grid_x": 115, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y48": { + "bits": {}, + "grid_x": 115, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y5": { + "bits": {}, + "grid_x": 115, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y50": { + "bits": {}, + "grid_x": 115, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y52": { + "bits": {}, + "grid_x": 115, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y55": { + "bits": {}, + "grid_x": 115, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y57": { + "bits": {}, + "grid_x": 115, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y59": { + "bits": {}, + "grid_x": 115, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y61": { + "bits": {}, + "grid_x": 115, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y63": { + "bits": {}, + "grid_x": 115, + "grid_y": 145, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y65": { + "bits": {}, + "grid_x": 115, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y67": { + "bits": {}, + "grid_x": 115, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y69": { + "bits": {}, + "grid_x": 115, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y7": { + "bits": {}, + "grid_x": 115, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y71": { + "bits": {}, + "grid_x": 115, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y73": { + "bits": {}, + "grid_x": 115, + "grid_y": 135, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y75": { + "bits": {}, + "grid_x": 115, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y77": { + "bits": {}, + "grid_x": 115, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y80": { + "bits": {}, + "grid_x": 115, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y82": { + "bits": {}, + "grid_x": 115, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y84": { + "bits": {}, + "grid_x": 115, + "grid_y": 124, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y86": { + "bits": {}, + "grid_x": 115, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y88": { + "bits": {}, + "grid_x": 115, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y9": { + "bits": {}, + "grid_x": 115, + "grid_y": 199, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y90": { + "bits": {}, + "grid_x": 115, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y92": { + "bits": {}, + "grid_x": 115, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y94": { + "bits": {}, + "grid_x": 115, + "grid_y": 114, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y96": { + "bits": {}, + "grid_x": 115, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X115Y98": { + "bits": {}, + "grid_x": 115, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y0": { + "bits": {}, + "grid_x": 116, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y100": { + "bits": {}, + "grid_x": 116, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y102": { + "bits": {}, + "grid_x": 116, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y104": { + "bits": {}, + "grid_x": 116, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y105": { + "bits": {}, + "grid_x": 116, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y106": { + "bits": {}, + "grid_x": 116, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y107": { + "bits": {}, + "grid_x": 116, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y108": { + "bits": {}, + "grid_x": 116, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y109": { + "bits": {}, + "grid_x": 116, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y11": { + "bits": {}, + "grid_x": 116, + "grid_y": 197, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y110": { + "bits": {}, + "grid_x": 116, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y111": { + "bits": {}, + "grid_x": 116, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y112": { + "bits": {}, + "grid_x": 116, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y113": { + "bits": {}, + "grid_x": 116, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y114": { + "bits": {}, + "grid_x": 116, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y115": { + "bits": {}, + "grid_x": 116, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y116": { + "bits": {}, + "grid_x": 116, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y117": { + "bits": {}, + "grid_x": 116, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y118": { + "bits": {}, + "grid_x": 116, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y119": { + "bits": {}, + "grid_x": 116, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y120": { + "bits": {}, + "grid_x": 116, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y121": { + "bits": {}, + "grid_x": 116, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y122": { + "bits": {}, + "grid_x": 116, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y123": { + "bits": {}, + "grid_x": 116, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y124": { + "bits": {}, + "grid_x": 116, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y125": { + "bits": {}, + "grid_x": 116, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y126": { + "bits": {}, + "grid_x": 116, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y127": { + "bits": {}, + "grid_x": 116, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y128": { + "bits": {}, + "grid_x": 116, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y129": { + "bits": {}, + "grid_x": 116, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y13": { + "bits": {}, + "grid_x": 116, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y130": { + "bits": {}, + "grid_x": 116, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y131": { + "bits": {}, + "grid_x": 116, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y132": { + "bits": {}, + "grid_x": 116, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y133": { + "bits": {}, + "grid_x": 116, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y134": { + "bits": {}, + "grid_x": 116, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y135": { + "bits": {}, + "grid_x": 116, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y136": { + "bits": {}, + "grid_x": 116, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y137": { + "bits": {}, + "grid_x": 116, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y138": { + "bits": {}, + "grid_x": 116, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y139": { + "bits": {}, + "grid_x": 116, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y140": { + "bits": {}, + "grid_x": 116, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y141": { + "bits": {}, + "grid_x": 116, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y142": { + "bits": {}, + "grid_x": 116, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y143": { + "bits": {}, + "grid_x": 116, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y144": { + "bits": {}, + "grid_x": 116, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y145": { + "bits": {}, + "grid_x": 116, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y146": { + "bits": {}, + "grid_x": 116, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y147": { + "bits": {}, + "grid_x": 116, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y148": { + "bits": {}, + "grid_x": 116, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y149": { + "bits": {}, + "grid_x": 116, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y15": { + "bits": {}, + "grid_x": 116, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y150": { + "bits": {}, + "grid_x": 116, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y151": { + "bits": {}, + "grid_x": 116, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y152": { + "bits": {}, + "grid_x": 116, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y153": { + "bits": {}, + "grid_x": 116, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y154": { + "bits": {}, + "grid_x": 116, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y155": { + "bits": {}, + "grid_x": 116, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y156": { + "bits": {}, + "grid_x": 116, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y157": { + "bits": {}, + "grid_x": 116, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y158": { + "bits": {}, + "grid_x": 116, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y159": { + "bits": {}, + "grid_x": 116, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y160": { + "bits": {}, + "grid_x": 116, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y161": { + "bits": {}, + "grid_x": 116, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y162": { + "bits": {}, + "grid_x": 116, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y163": { + "bits": {}, + "grid_x": 116, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y164": { + "bits": {}, + "grid_x": 116, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y165": { + "bits": {}, + "grid_x": 116, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y166": { + "bits": {}, + "grid_x": 116, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y167": { + "bits": {}, + "grid_x": 116, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y168": { + "bits": {}, + "grid_x": 116, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y169": { + "bits": {}, + "grid_x": 116, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y17": { + "bits": {}, + "grid_x": 116, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y170": { + "bits": {}, + "grid_x": 116, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y171": { + "bits": {}, + "grid_x": 116, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y172": { + "bits": {}, + "grid_x": 116, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y173": { + "bits": {}, + "grid_x": 116, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y174": { + "bits": {}, + "grid_x": 116, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y175": { + "bits": {}, + "grid_x": 116, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y176": { + "bits": {}, + "grid_x": 116, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y177": { + "bits": {}, + "grid_x": 116, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y178": { + "bits": {}, + "grid_x": 116, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y179": { + "bits": {}, + "grid_x": 116, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y180": { + "bits": {}, + "grid_x": 116, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y181": { + "bits": {}, + "grid_x": 116, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y182": { + "bits": {}, + "grid_x": 116, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y183": { + "bits": {}, + "grid_x": 116, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y184": { + "bits": {}, + "grid_x": 116, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y185": { + "bits": {}, + "grid_x": 116, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y186": { + "bits": {}, + "grid_x": 116, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y187": { + "bits": {}, + "grid_x": 116, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y188": { + "bits": {}, + "grid_x": 116, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y189": { + "bits": {}, + "grid_x": 116, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y19": { + "bits": {}, + "grid_x": 116, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y190": { + "bits": {}, + "grid_x": 116, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y191": { + "bits": {}, + "grid_x": 116, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y192": { + "bits": {}, + "grid_x": 116, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y193": { + "bits": {}, + "grid_x": 116, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y194": { + "bits": {}, + "grid_x": 116, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y195": { + "bits": {}, + "grid_x": 116, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y196": { + "bits": {}, + "grid_x": 116, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y197": { + "bits": {}, + "grid_x": 116, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y198": { + "bits": {}, + "grid_x": 116, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y199": { + "bits": {}, + "grid_x": 116, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y200": { + "bits": {}, + "grid_x": 116, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y201": { + "bits": {}, + "grid_x": 116, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y202": { + "bits": {}, + "grid_x": 116, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y203": { + "bits": {}, + "grid_x": 116, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y204": { + "bits": {}, + "grid_x": 116, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y205": { + "bits": {}, + "grid_x": 116, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y206": { + "bits": {}, + "grid_x": 116, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y207": { + "bits": {}, + "grid_x": 116, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y208": { + "bits": {}, + "grid_x": 116, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y21": { + "bits": {}, + "grid_x": 116, + "grid_y": 187, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y23": { + "bits": {}, + "grid_x": 116, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y25": { + "bits": {}, + "grid_x": 116, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y28": { + "bits": {}, + "grid_x": 116, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y3": { + "bits": {}, + "grid_x": 116, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y30": { + "bits": {}, + "grid_x": 116, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y32": { + "bits": {}, + "grid_x": 116, + "grid_y": 176, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y34": { + "bits": {}, + "grid_x": 116, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y36": { + "bits": {}, + "grid_x": 116, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y38": { + "bits": {}, + "grid_x": 116, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y40": { + "bits": {}, + "grid_x": 116, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y42": { + "bits": {}, + "grid_x": 116, + "grid_y": 166, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y44": { + "bits": {}, + "grid_x": 116, + "grid_y": 164, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y46": { + "bits": {}, + "grid_x": 116, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y48": { + "bits": {}, + "grid_x": 116, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y5": { + "bits": {}, + "grid_x": 116, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y50": { + "bits": {}, + "grid_x": 116, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y52": { + "bits": {}, + "grid_x": 116, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y55": { + "bits": {}, + "grid_x": 116, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y57": { + "bits": {}, + "grid_x": 116, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y59": { + "bits": {}, + "grid_x": 116, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y61": { + "bits": {}, + "grid_x": 116, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y63": { + "bits": {}, + "grid_x": 116, + "grid_y": 145, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y65": { + "bits": {}, + "grid_x": 116, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y67": { + "bits": {}, + "grid_x": 116, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y69": { + "bits": {}, + "grid_x": 116, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y7": { + "bits": {}, + "grid_x": 116, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y71": { + "bits": {}, + "grid_x": 116, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y73": { + "bits": {}, + "grid_x": 116, + "grid_y": 135, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y75": { + "bits": {}, + "grid_x": 116, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y77": { + "bits": {}, + "grid_x": 116, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y80": { + "bits": {}, + "grid_x": 116, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y82": { + "bits": {}, + "grid_x": 116, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y84": { + "bits": {}, + "grid_x": 116, + "grid_y": 124, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y86": { + "bits": {}, + "grid_x": 116, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y88": { + "bits": {}, + "grid_x": 116, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y9": { + "bits": {}, + "grid_x": 116, + "grid_y": 199, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y90": { + "bits": {}, + "grid_x": 116, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y92": { + "bits": {}, + "grid_x": 116, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y94": { + "bits": {}, + "grid_x": 116, + "grid_y": 114, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y96": { + "bits": {}, + "grid_x": 116, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X116Y98": { + "bits": {}, + "grid_x": 116, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X13Y0": { + "bits": {}, + "grid_x": 13, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X13Y208": { + "bits": {}, + "grid_x": 13, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X14Y0": { + "bits": {}, + "grid_x": 14, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X14Y208": { + "bits": {}, + "grid_x": 14, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X17Y0": { + "bits": {}, + "grid_x": 17, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X17Y208": { + "bits": {}, + "grid_x": 17, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X18Y0": { + "bits": {}, + "grid_x": 18, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X18Y104": { + "bits": {}, + "grid_x": 18, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X18Y156": { + "bits": {}, + "grid_x": 18, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X18Y208": { + "bits": {}, + "grid_x": 18, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X18Y52": { + "bits": {}, + "grid_x": 18, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y0": { + "bits": {}, + "grid_x": 19, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y10": { + "bits": {}, + "grid_x": 19, + "grid_y": 198, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y100": { + "bits": {}, + "grid_x": 19, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y101": { + "bits": {}, + "grid_x": 19, + "grid_y": 107, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y102": { + "bits": {}, + "grid_x": 19, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y103": { + "bits": {}, + "grid_x": 19, + "grid_y": 105, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y106": { + "bits": {}, + "grid_x": 19, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y107": { + "bits": {}, + "grid_x": 19, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y108": { + "bits": {}, + "grid_x": 19, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y109": { + "bits": {}, + "grid_x": 19, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y111": { + "bits": {}, + "grid_x": 19, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y112": { + "bits": {}, + "grid_x": 19, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y113": { + "bits": {}, + "grid_x": 19, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y114": { + "bits": {}, + "grid_x": 19, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y116": { + "bits": {}, + "grid_x": 19, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y117": { + "bits": {}, + "grid_x": 19, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y118": { + "bits": {}, + "grid_x": 19, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y119": { + "bits": {}, + "grid_x": 19, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y12": { + "bits": {}, + "grid_x": 19, + "grid_y": 196, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y121": { + "bits": {}, + "grid_x": 19, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y122": { + "bits": {}, + "grid_x": 19, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y123": { + "bits": {}, + "grid_x": 19, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y124": { + "bits": {}, + "grid_x": 19, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y126": { + "bits": {}, + "grid_x": 19, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y127": { + "bits": {}, + "grid_x": 19, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y128": { + "bits": {}, + "grid_x": 19, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y129": { + "bits": {}, + "grid_x": 19, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y13": { + "bits": {}, + "grid_x": 19, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y132": { + "bits": {}, + "grid_x": 19, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y133": { + "bits": {}, + "grid_x": 19, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y134": { + "bits": {}, + "grid_x": 19, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y135": { + "bits": {}, + "grid_x": 19, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y137": { + "bits": {}, + "grid_x": 19, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y138": { + "bits": {}, + "grid_x": 19, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y139": { + "bits": {}, + "grid_x": 19, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y14": { + "bits": {}, + "grid_x": 19, + "grid_y": 194, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y140": { + "bits": {}, + "grid_x": 19, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y142": { + "bits": {}, + "grid_x": 19, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y143": { + "bits": {}, + "grid_x": 19, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y144": { + "bits": {}, + "grid_x": 19, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y145": { + "bits": {}, + "grid_x": 19, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y147": { + "bits": {}, + "grid_x": 19, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y148": { + "bits": {}, + "grid_x": 19, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y149": { + "bits": {}, + "grid_x": 19, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y15": { + "bits": {}, + "grid_x": 19, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y150": { + "bits": {}, + "grid_x": 19, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y152": { + "bits": {}, + "grid_x": 19, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y153": { + "bits": {}, + "grid_x": 19, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y154": { + "bits": {}, + "grid_x": 19, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y155": { + "bits": {}, + "grid_x": 19, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y158": { + "bits": {}, + "grid_x": 19, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y159": { + "bits": {}, + "grid_x": 19, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y160": { + "bits": {}, + "grid_x": 19, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y161": { + "bits": {}, + "grid_x": 19, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y163": { + "bits": {}, + "grid_x": 19, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y164": { + "bits": {}, + "grid_x": 19, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y165": { + "bits": {}, + "grid_x": 19, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y166": { + "bits": {}, + "grid_x": 19, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y168": { + "bits": {}, + "grid_x": 19, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y169": { + "bits": {}, + "grid_x": 19, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y17": { + "bits": {}, + "grid_x": 19, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y170": { + "bits": {}, + "grid_x": 19, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y171": { + "bits": {}, + "grid_x": 19, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y173": { + "bits": {}, + "grid_x": 19, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y174": { + "bits": {}, + "grid_x": 19, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y175": { + "bits": {}, + "grid_x": 19, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y176": { + "bits": {}, + "grid_x": 19, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y178": { + "bits": {}, + "grid_x": 19, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y179": { + "bits": {}, + "grid_x": 19, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y18": { + "bits": {}, + "grid_x": 19, + "grid_y": 190, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y180": { + "bits": {}, + "grid_x": 19, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y181": { + "bits": {}, + "grid_x": 19, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y184": { + "bits": {}, + "grid_x": 19, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y185": { + "bits": {}, + "grid_x": 19, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y186": { + "bits": {}, + "grid_x": 19, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y187": { + "bits": {}, + "grid_x": 19, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y189": { + "bits": {}, + "grid_x": 19, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y19": { + "bits": {}, + "grid_x": 19, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y190": { + "bits": {}, + "grid_x": 19, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y191": { + "bits": {}, + "grid_x": 19, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y192": { + "bits": {}, + "grid_x": 19, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y194": { + "bits": {}, + "grid_x": 19, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y195": { + "bits": {}, + "grid_x": 19, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y196": { + "bits": {}, + "grid_x": 19, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y197": { + "bits": {}, + "grid_x": 19, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y199": { + "bits": {}, + "grid_x": 19, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y2": { + "bits": {}, + "grid_x": 19, + "grid_y": 206, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y20": { + "bits": {}, + "grid_x": 19, + "grid_y": 188, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y200": { + "bits": {}, + "grid_x": 19, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y201": { + "bits": {}, + "grid_x": 19, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y202": { + "bits": {}, + "grid_x": 19, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y204": { + "bits": {}, + "grid_x": 19, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y205": { + "bits": {}, + "grid_x": 19, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y206": { + "bits": {}, + "grid_x": 19, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y207": { + "bits": {}, + "grid_x": 19, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y208": { + "bits": {}, + "grid_x": 19, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y22": { + "bits": {}, + "grid_x": 19, + "grid_y": 186, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y23": { + "bits": {}, + "grid_x": 19, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y24": { + "bits": {}, + "grid_x": 19, + "grid_y": 184, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y25": { + "bits": {}, + "grid_x": 19, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y28": { + "bits": {}, + "grid_x": 19, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y29": { + "bits": {}, + "grid_x": 19, + "grid_y": 179, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y3": { + "bits": {}, + "grid_x": 19, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y30": { + "bits": {}, + "grid_x": 19, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y31": { + "bits": {}, + "grid_x": 19, + "grid_y": 177, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y33": { + "bits": {}, + "grid_x": 19, + "grid_y": 175, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y34": { + "bits": {}, + "grid_x": 19, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y35": { + "bits": {}, + "grid_x": 19, + "grid_y": 173, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y36": { + "bits": {}, + "grid_x": 19, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y38": { + "bits": {}, + "grid_x": 19, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y39": { + "bits": {}, + "grid_x": 19, + "grid_y": 169, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y4": { + "bits": {}, + "grid_x": 19, + "grid_y": 204, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y40": { + "bits": {}, + "grid_x": 19, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y41": { + "bits": {}, + "grid_x": 19, + "grid_y": 167, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y43": { + "bits": {}, + "grid_x": 19, + "grid_y": 165, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y44": { + "bits": {}, + "grid_x": 19, + "grid_y": 164, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y45": { + "bits": {}, + "grid_x": 19, + "grid_y": 163, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y46": { + "bits": {}, + "grid_x": 19, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y48": { + "bits": {}, + "grid_x": 19, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y49": { + "bits": {}, + "grid_x": 19, + "grid_y": 159, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y5": { + "bits": {}, + "grid_x": 19, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y50": { + "bits": {}, + "grid_x": 19, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y51": { + "bits": {}, + "grid_x": 19, + "grid_y": 157, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y54": { + "bits": {}, + "grid_x": 19, + "grid_y": 154, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y55": { + "bits": {}, + "grid_x": 19, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y56": { + "bits": {}, + "grid_x": 19, + "grid_y": 152, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y57": { + "bits": {}, + "grid_x": 19, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y59": { + "bits": {}, + "grid_x": 19, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y60": { + "bits": {}, + "grid_x": 19, + "grid_y": 148, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y61": { + "bits": {}, + "grid_x": 19, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y62": { + "bits": {}, + "grid_x": 19, + "grid_y": 146, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y64": { + "bits": {}, + "grid_x": 19, + "grid_y": 144, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y65": { + "bits": {}, + "grid_x": 19, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y66": { + "bits": {}, + "grid_x": 19, + "grid_y": 142, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y67": { + "bits": {}, + "grid_x": 19, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y69": { + "bits": {}, + "grid_x": 19, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y7": { + "bits": {}, + "grid_x": 19, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y70": { + "bits": {}, + "grid_x": 19, + "grid_y": 138, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y71": { + "bits": {}, + "grid_x": 19, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y72": { + "bits": {}, + "grid_x": 19, + "grid_y": 136, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y74": { + "bits": {}, + "grid_x": 19, + "grid_y": 134, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y75": { + "bits": {}, + "grid_x": 19, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y76": { + "bits": {}, + "grid_x": 19, + "grid_y": 132, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y77": { + "bits": {}, + "grid_x": 19, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y8": { + "bits": {}, + "grid_x": 19, + "grid_y": 200, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y80": { + "bits": {}, + "grid_x": 19, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y81": { + "bits": {}, + "grid_x": 19, + "grid_y": 127, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y82": { + "bits": {}, + "grid_x": 19, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y83": { + "bits": {}, + "grid_x": 19, + "grid_y": 125, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y85": { + "bits": {}, + "grid_x": 19, + "grid_y": 123, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y86": { + "bits": {}, + "grid_x": 19, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y87": { + "bits": {}, + "grid_x": 19, + "grid_y": 121, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y88": { + "bits": {}, + "grid_x": 19, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y9": { + "bits": {}, + "grid_x": 19, + "grid_y": 199, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y90": { + "bits": {}, + "grid_x": 19, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y91": { + "bits": {}, + "grid_x": 19, + "grid_y": 117, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y92": { + "bits": {}, + "grid_x": 19, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y93": { + "bits": {}, + "grid_x": 19, + "grid_y": 115, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y95": { + "bits": {}, + "grid_x": 19, + "grid_y": 113, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y96": { + "bits": {}, + "grid_x": 19, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y97": { + "bits": {}, + "grid_x": 19, + "grid_y": 111, + "sites": {}, + "type": "NULL" + }, + "NULL_X19Y98": { + "bits": {}, + "grid_x": 19, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y0": { + "bits": {}, + "grid_x": 1, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y100": { + "bits": {}, + "grid_x": 1, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y102": { + "bits": {}, + "grid_x": 1, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y104": { + "bits": {}, + "grid_x": 1, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y107": { + "bits": {}, + "grid_x": 1, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y109": { + "bits": {}, + "grid_x": 1, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y11": { + "bits": {}, + "grid_x": 1, + "grid_y": 197, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y111": { + "bits": {}, + "grid_x": 1, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y113": { + "bits": {}, + "grid_x": 1, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y115": { + "bits": {}, + "grid_x": 1, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y117": { + "bits": {}, + "grid_x": 1, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y119": { + "bits": {}, + "grid_x": 1, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y121": { + "bits": {}, + "grid_x": 1, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y123": { + "bits": {}, + "grid_x": 1, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y125": { + "bits": {}, + "grid_x": 1, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y127": { + "bits": {}, + "grid_x": 1, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y129": { + "bits": {}, + "grid_x": 1, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y13": { + "bits": {}, + "grid_x": 1, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y132": { + "bits": {}, + "grid_x": 1, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y134": { + "bits": {}, + "grid_x": 1, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y136": { + "bits": {}, + "grid_x": 1, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y138": { + "bits": {}, + "grid_x": 1, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y140": { + "bits": {}, + "grid_x": 1, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y142": { + "bits": {}, + "grid_x": 1, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y144": { + "bits": {}, + "grid_x": 1, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y146": { + "bits": {}, + "grid_x": 1, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y148": { + "bits": {}, + "grid_x": 1, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y15": { + "bits": {}, + "grid_x": 1, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y150": { + "bits": {}, + "grid_x": 1, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y152": { + "bits": {}, + "grid_x": 1, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y154": { + "bits": {}, + "grid_x": 1, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y156": { + "bits": {}, + "grid_x": 1, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y159": { + "bits": {}, + "grid_x": 1, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y161": { + "bits": {}, + "grid_x": 1, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y163": { + "bits": {}, + "grid_x": 1, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y165": { + "bits": {}, + "grid_x": 1, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y167": { + "bits": {}, + "grid_x": 1, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y169": { + "bits": {}, + "grid_x": 1, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y17": { + "bits": {}, + "grid_x": 1, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y171": { + "bits": {}, + "grid_x": 1, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y173": { + "bits": {}, + "grid_x": 1, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y175": { + "bits": {}, + "grid_x": 1, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y177": { + "bits": {}, + "grid_x": 1, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y179": { + "bits": {}, + "grid_x": 1, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y181": { + "bits": {}, + "grid_x": 1, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y184": { + "bits": {}, + "grid_x": 1, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y186": { + "bits": {}, + "grid_x": 1, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y188": { + "bits": {}, + "grid_x": 1, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y19": { + "bits": {}, + "grid_x": 1, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y190": { + "bits": {}, + "grid_x": 1, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y192": { + "bits": {}, + "grid_x": 1, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y194": { + "bits": {}, + "grid_x": 1, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y196": { + "bits": {}, + "grid_x": 1, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y198": { + "bits": {}, + "grid_x": 1, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y200": { + "bits": {}, + "grid_x": 1, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y202": { + "bits": {}, + "grid_x": 1, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y204": { + "bits": {}, + "grid_x": 1, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y206": { + "bits": {}, + "grid_x": 1, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y208": { + "bits": {}, + "grid_x": 1, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y21": { + "bits": {}, + "grid_x": 1, + "grid_y": 187, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y23": { + "bits": {}, + "grid_x": 1, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y25": { + "bits": {}, + "grid_x": 1, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y28": { + "bits": {}, + "grid_x": 1, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y3": { + "bits": {}, + "grid_x": 1, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y30": { + "bits": {}, + "grid_x": 1, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y32": { + "bits": {}, + "grid_x": 1, + "grid_y": 176, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y34": { + "bits": {}, + "grid_x": 1, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y36": { + "bits": {}, + "grid_x": 1, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y38": { + "bits": {}, + "grid_x": 1, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y40": { + "bits": {}, + "grid_x": 1, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y42": { + "bits": {}, + "grid_x": 1, + "grid_y": 166, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y44": { + "bits": {}, + "grid_x": 1, + "grid_y": 164, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y46": { + "bits": {}, + "grid_x": 1, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y48": { + "bits": {}, + "grid_x": 1, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y5": { + "bits": {}, + "grid_x": 1, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y50": { + "bits": {}, + "grid_x": 1, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y52": { + "bits": {}, + "grid_x": 1, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y55": { + "bits": {}, + "grid_x": 1, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y57": { + "bits": {}, + "grid_x": 1, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y59": { + "bits": {}, + "grid_x": 1, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y61": { + "bits": {}, + "grid_x": 1, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y63": { + "bits": {}, + "grid_x": 1, + "grid_y": 145, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y65": { + "bits": {}, + "grid_x": 1, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y67": { + "bits": {}, + "grid_x": 1, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y69": { + "bits": {}, + "grid_x": 1, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y7": { + "bits": {}, + "grid_x": 1, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y71": { + "bits": {}, + "grid_x": 1, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y73": { + "bits": {}, + "grid_x": 1, + "grid_y": 135, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y75": { + "bits": {}, + "grid_x": 1, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y77": { + "bits": {}, + "grid_x": 1, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y80": { + "bits": {}, + "grid_x": 1, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y82": { + "bits": {}, + "grid_x": 1, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y84": { + "bits": {}, + "grid_x": 1, + "grid_y": 124, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y86": { + "bits": {}, + "grid_x": 1, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y88": { + "bits": {}, + "grid_x": 1, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y9": { + "bits": {}, + "grid_x": 1, + "grid_y": 199, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y90": { + "bits": {}, + "grid_x": 1, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y92": { + "bits": {}, + "grid_x": 1, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y94": { + "bits": {}, + "grid_x": 1, + "grid_y": 114, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y96": { + "bits": {}, + "grid_x": 1, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X1Y98": { + "bits": {}, + "grid_x": 1, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X20Y0": { + "bits": {}, + "grid_x": 20, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X20Y104": { + "bits": {}, + "grid_x": 20, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X20Y156": { + "bits": {}, + "grid_x": 20, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X20Y208": { + "bits": {}, + "grid_x": 20, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X20Y52": { + "bits": {}, + "grid_x": 20, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X23Y0": { + "bits": {}, + "grid_x": 23, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X23Y208": { + "bits": {}, + "grid_x": 23, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X24Y0": { + "bits": {}, + "grid_x": 24, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X24Y208": { + "bits": {}, + "grid_x": 24, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X27Y0": { + "bits": {}, + "grid_x": 27, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X27Y104": { + "bits": {}, + "grid_x": 27, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X27Y156": { + "bits": {}, + "grid_x": 27, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X27Y208": { + "bits": {}, + "grid_x": 27, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X27Y52": { + "bits": {}, + "grid_x": 27, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y0": { + "bits": {}, + "grid_x": 28, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y10": { + "bits": {}, + "grid_x": 28, + "grid_y": 198, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y100": { + "bits": {}, + "grid_x": 28, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y101": { + "bits": {}, + "grid_x": 28, + "grid_y": 107, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y102": { + "bits": {}, + "grid_x": 28, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y103": { + "bits": {}, + "grid_x": 28, + "grid_y": 105, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y106": { + "bits": {}, + "grid_x": 28, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y107": { + "bits": {}, + "grid_x": 28, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y108": { + "bits": {}, + "grid_x": 28, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y109": { + "bits": {}, + "grid_x": 28, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y111": { + "bits": {}, + "grid_x": 28, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y112": { + "bits": {}, + "grid_x": 28, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y113": { + "bits": {}, + "grid_x": 28, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y114": { + "bits": {}, + "grid_x": 28, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y116": { + "bits": {}, + "grid_x": 28, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y117": { + "bits": {}, + "grid_x": 28, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y118": { + "bits": {}, + "grid_x": 28, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y119": { + "bits": {}, + "grid_x": 28, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y12": { + "bits": {}, + "grid_x": 28, + "grid_y": 196, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y121": { + "bits": {}, + "grid_x": 28, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y122": { + "bits": {}, + "grid_x": 28, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y123": { + "bits": {}, + "grid_x": 28, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y124": { + "bits": {}, + "grid_x": 28, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y126": { + "bits": {}, + "grid_x": 28, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y127": { + "bits": {}, + "grid_x": 28, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y128": { + "bits": {}, + "grid_x": 28, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y129": { + "bits": {}, + "grid_x": 28, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y13": { + "bits": {}, + "grid_x": 28, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y132": { + "bits": {}, + "grid_x": 28, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y133": { + "bits": {}, + "grid_x": 28, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y134": { + "bits": {}, + "grid_x": 28, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y135": { + "bits": {}, + "grid_x": 28, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y137": { + "bits": {}, + "grid_x": 28, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y138": { + "bits": {}, + "grid_x": 28, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y139": { + "bits": {}, + "grid_x": 28, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y14": { + "bits": {}, + "grid_x": 28, + "grid_y": 194, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y140": { + "bits": {}, + "grid_x": 28, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y142": { + "bits": {}, + "grid_x": 28, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y143": { + "bits": {}, + "grid_x": 28, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y144": { + "bits": {}, + "grid_x": 28, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y145": { + "bits": {}, + "grid_x": 28, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y147": { + "bits": {}, + "grid_x": 28, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y148": { + "bits": {}, + "grid_x": 28, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y149": { + "bits": {}, + "grid_x": 28, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y15": { + "bits": {}, + "grid_x": 28, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y150": { + "bits": {}, + "grid_x": 28, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y152": { + "bits": {}, + "grid_x": 28, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y153": { + "bits": {}, + "grid_x": 28, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y154": { + "bits": {}, + "grid_x": 28, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y155": { + "bits": {}, + "grid_x": 28, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y158": { + "bits": {}, + "grid_x": 28, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y159": { + "bits": {}, + "grid_x": 28, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y160": { + "bits": {}, + "grid_x": 28, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y161": { + "bits": {}, + "grid_x": 28, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y163": { + "bits": {}, + "grid_x": 28, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y164": { + "bits": {}, + "grid_x": 28, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y165": { + "bits": {}, + "grid_x": 28, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y166": { + "bits": {}, + "grid_x": 28, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y168": { + "bits": {}, + "grid_x": 28, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y169": { + "bits": {}, + "grid_x": 28, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y17": { + "bits": {}, + "grid_x": 28, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y170": { + "bits": {}, + "grid_x": 28, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y171": { + "bits": {}, + "grid_x": 28, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y173": { + "bits": {}, + "grid_x": 28, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y174": { + "bits": {}, + "grid_x": 28, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y175": { + "bits": {}, + "grid_x": 28, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y176": { + "bits": {}, + "grid_x": 28, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y178": { + "bits": {}, + "grid_x": 28, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y179": { + "bits": {}, + "grid_x": 28, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y18": { + "bits": {}, + "grid_x": 28, + "grid_y": 190, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y180": { + "bits": {}, + "grid_x": 28, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y181": { + "bits": {}, + "grid_x": 28, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y184": { + "bits": {}, + "grid_x": 28, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y185": { + "bits": {}, + "grid_x": 28, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y186": { + "bits": {}, + "grid_x": 28, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y187": { + "bits": {}, + "grid_x": 28, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y189": { + "bits": {}, + "grid_x": 28, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y19": { + "bits": {}, + "grid_x": 28, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y190": { + "bits": {}, + "grid_x": 28, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y191": { + "bits": {}, + "grid_x": 28, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y192": { + "bits": {}, + "grid_x": 28, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y194": { + "bits": {}, + "grid_x": 28, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y195": { + "bits": {}, + "grid_x": 28, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y196": { + "bits": {}, + "grid_x": 28, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y197": { + "bits": {}, + "grid_x": 28, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y199": { + "bits": {}, + "grid_x": 28, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y2": { + "bits": {}, + "grid_x": 28, + "grid_y": 206, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y20": { + "bits": {}, + "grid_x": 28, + "grid_y": 188, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y200": { + "bits": {}, + "grid_x": 28, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y201": { + "bits": {}, + "grid_x": 28, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y202": { + "bits": {}, + "grid_x": 28, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y204": { + "bits": {}, + "grid_x": 28, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y205": { + "bits": {}, + "grid_x": 28, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y206": { + "bits": {}, + "grid_x": 28, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y207": { + "bits": {}, + "grid_x": 28, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y208": { + "bits": {}, + "grid_x": 28, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y22": { + "bits": {}, + "grid_x": 28, + "grid_y": 186, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y23": { + "bits": {}, + "grid_x": 28, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y24": { + "bits": {}, + "grid_x": 28, + "grid_y": 184, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y25": { + "bits": {}, + "grid_x": 28, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y28": { + "bits": {}, + "grid_x": 28, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y29": { + "bits": {}, + "grid_x": 28, + "grid_y": 179, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y3": { + "bits": {}, + "grid_x": 28, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y30": { + "bits": {}, + "grid_x": 28, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y31": { + "bits": {}, + "grid_x": 28, + "grid_y": 177, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y33": { + "bits": {}, + "grid_x": 28, + "grid_y": 175, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y34": { + "bits": {}, + "grid_x": 28, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y35": { + "bits": {}, + "grid_x": 28, + "grid_y": 173, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y36": { + "bits": {}, + "grid_x": 28, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y38": { + "bits": {}, + "grid_x": 28, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y39": { + "bits": {}, + "grid_x": 28, + "grid_y": 169, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y4": { + "bits": {}, + "grid_x": 28, + "grid_y": 204, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y40": { + "bits": {}, + "grid_x": 28, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y41": { + "bits": {}, + "grid_x": 28, + "grid_y": 167, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y43": { + "bits": {}, + "grid_x": 28, + "grid_y": 165, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y44": { + "bits": {}, + "grid_x": 28, + "grid_y": 164, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y45": { + "bits": {}, + "grid_x": 28, + "grid_y": 163, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y46": { + "bits": {}, + "grid_x": 28, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y48": { + "bits": {}, + "grid_x": 28, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y49": { + "bits": {}, + "grid_x": 28, + "grid_y": 159, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y5": { + "bits": {}, + "grid_x": 28, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y50": { + "bits": {}, + "grid_x": 28, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y51": { + "bits": {}, + "grid_x": 28, + "grid_y": 157, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y54": { + "bits": {}, + "grid_x": 28, + "grid_y": 154, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y55": { + "bits": {}, + "grid_x": 28, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y56": { + "bits": {}, + "grid_x": 28, + "grid_y": 152, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y57": { + "bits": {}, + "grid_x": 28, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y59": { + "bits": {}, + "grid_x": 28, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y60": { + "bits": {}, + "grid_x": 28, + "grid_y": 148, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y61": { + "bits": {}, + "grid_x": 28, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y62": { + "bits": {}, + "grid_x": 28, + "grid_y": 146, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y64": { + "bits": {}, + "grid_x": 28, + "grid_y": 144, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y65": { + "bits": {}, + "grid_x": 28, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y66": { + "bits": {}, + "grid_x": 28, + "grid_y": 142, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y67": { + "bits": {}, + "grid_x": 28, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y69": { + "bits": {}, + "grid_x": 28, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y7": { + "bits": {}, + "grid_x": 28, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y70": { + "bits": {}, + "grid_x": 28, + "grid_y": 138, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y71": { + "bits": {}, + "grid_x": 28, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y72": { + "bits": {}, + "grid_x": 28, + "grid_y": 136, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y74": { + "bits": {}, + "grid_x": 28, + "grid_y": 134, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y75": { + "bits": {}, + "grid_x": 28, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y76": { + "bits": {}, + "grid_x": 28, + "grid_y": 132, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y77": { + "bits": {}, + "grid_x": 28, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y8": { + "bits": {}, + "grid_x": 28, + "grid_y": 200, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y80": { + "bits": {}, + "grid_x": 28, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y81": { + "bits": {}, + "grid_x": 28, + "grid_y": 127, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y82": { + "bits": {}, + "grid_x": 28, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y83": { + "bits": {}, + "grid_x": 28, + "grid_y": 125, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y85": { + "bits": {}, + "grid_x": 28, + "grid_y": 123, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y86": { + "bits": {}, + "grid_x": 28, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y87": { + "bits": {}, + "grid_x": 28, + "grid_y": 121, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y88": { + "bits": {}, + "grid_x": 28, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y9": { + "bits": {}, + "grid_x": 28, + "grid_y": 199, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y90": { + "bits": {}, + "grid_x": 28, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y91": { + "bits": {}, + "grid_x": 28, + "grid_y": 117, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y92": { + "bits": {}, + "grid_x": 28, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y93": { + "bits": {}, + "grid_x": 28, + "grid_y": 115, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y95": { + "bits": {}, + "grid_x": 28, + "grid_y": 113, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y96": { + "bits": {}, + "grid_x": 28, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y97": { + "bits": {}, + "grid_x": 28, + "grid_y": 111, + "sites": {}, + "type": "NULL" + }, + "NULL_X28Y98": { + "bits": {}, + "grid_x": 28, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X29Y0": { + "bits": {}, + "grid_x": 29, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X29Y104": { + "bits": {}, + "grid_x": 29, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X29Y156": { + "bits": {}, + "grid_x": 29, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X29Y208": { + "bits": {}, + "grid_x": 29, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X29Y52": { + "bits": {}, + "grid_x": 29, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X2Y0": { + "bits": {}, + "grid_x": 2, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X2Y104": { + "bits": {}, + "grid_x": 2, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X2Y156": { + "bits": {}, + "grid_x": 2, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X2Y208": { + "bits": {}, + "grid_x": 2, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X2Y52": { + "bits": {}, + "grid_x": 2, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X30Y0": { + "bits": {}, + "grid_x": 30, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X30Y208": { + "bits": {}, + "grid_x": 30, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X33Y0": { + "bits": {}, + "grid_x": 33, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X33Y208": { + "bits": {}, + "grid_x": 33, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X34Y0": { + "bits": {}, + "grid_x": 34, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X34Y208": { + "bits": {}, + "grid_x": 34, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X37Y0": { + "bits": {}, + "grid_x": 37, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X37Y208": { + "bits": {}, + "grid_x": 37, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X38Y0": { + "bits": {}, + "grid_x": 38, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X38Y104": { + "bits": {}, + "grid_x": 38, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X38Y156": { + "bits": {}, + "grid_x": 38, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X38Y208": { + "bits": {}, + "grid_x": 38, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X38Y52": { + "bits": {}, + "grid_x": 38, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y0": { + "bits": {}, + "grid_x": 39, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y10": { + "bits": {}, + "grid_x": 39, + "grid_y": 198, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y100": { + "bits": {}, + "grid_x": 39, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y101": { + "bits": {}, + "grid_x": 39, + "grid_y": 107, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y102": { + "bits": {}, + "grid_x": 39, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y103": { + "bits": {}, + "grid_x": 39, + "grid_y": 105, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y106": { + "bits": {}, + "grid_x": 39, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y107": { + "bits": {}, + "grid_x": 39, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y108": { + "bits": {}, + "grid_x": 39, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y109": { + "bits": {}, + "grid_x": 39, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y111": { + "bits": {}, + "grid_x": 39, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y112": { + "bits": {}, + "grid_x": 39, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y113": { + "bits": {}, + "grid_x": 39, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y114": { + "bits": {}, + "grid_x": 39, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y116": { + "bits": {}, + "grid_x": 39, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y117": { + "bits": {}, + "grid_x": 39, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y118": { + "bits": {}, + "grid_x": 39, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y119": { + "bits": {}, + "grid_x": 39, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y12": { + "bits": {}, + "grid_x": 39, + "grid_y": 196, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y121": { + "bits": {}, + "grid_x": 39, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y122": { + "bits": {}, + "grid_x": 39, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y123": { + "bits": {}, + "grid_x": 39, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y124": { + "bits": {}, + "grid_x": 39, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y126": { + "bits": {}, + "grid_x": 39, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y127": { + "bits": {}, + "grid_x": 39, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y128": { + "bits": {}, + "grid_x": 39, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y129": { + "bits": {}, + "grid_x": 39, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y13": { + "bits": {}, + "grid_x": 39, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y132": { + "bits": {}, + "grid_x": 39, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y133": { + "bits": {}, + "grid_x": 39, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y134": { + "bits": {}, + "grid_x": 39, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y135": { + "bits": {}, + "grid_x": 39, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y137": { + "bits": {}, + "grid_x": 39, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y138": { + "bits": {}, + "grid_x": 39, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y139": { + "bits": {}, + "grid_x": 39, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y14": { + "bits": {}, + "grid_x": 39, + "grid_y": 194, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y140": { + "bits": {}, + "grid_x": 39, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y142": { + "bits": {}, + "grid_x": 39, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y143": { + "bits": {}, + "grid_x": 39, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y144": { + "bits": {}, + "grid_x": 39, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y145": { + "bits": {}, + "grid_x": 39, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y147": { + "bits": {}, + "grid_x": 39, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y148": { + "bits": {}, + "grid_x": 39, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y149": { + "bits": {}, + "grid_x": 39, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y15": { + "bits": {}, + "grid_x": 39, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y150": { + "bits": {}, + "grid_x": 39, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y152": { + "bits": {}, + "grid_x": 39, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y153": { + "bits": {}, + "grid_x": 39, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y154": { + "bits": {}, + "grid_x": 39, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y155": { + "bits": {}, + "grid_x": 39, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y158": { + "bits": {}, + "grid_x": 39, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y159": { + "bits": {}, + "grid_x": 39, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y160": { + "bits": {}, + "grid_x": 39, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y161": { + "bits": {}, + "grid_x": 39, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y163": { + "bits": {}, + "grid_x": 39, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y164": { + "bits": {}, + "grid_x": 39, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y165": { + "bits": {}, + "grid_x": 39, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y166": { + "bits": {}, + "grid_x": 39, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y168": { + "bits": {}, + "grid_x": 39, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y169": { + "bits": {}, + "grid_x": 39, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y17": { + "bits": {}, + "grid_x": 39, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y170": { + "bits": {}, + "grid_x": 39, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y171": { + "bits": {}, + "grid_x": 39, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y173": { + "bits": {}, + "grid_x": 39, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y174": { + "bits": {}, + "grid_x": 39, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y175": { + "bits": {}, + "grid_x": 39, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y176": { + "bits": {}, + "grid_x": 39, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y178": { + "bits": {}, + "grid_x": 39, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y179": { + "bits": {}, + "grid_x": 39, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y18": { + "bits": {}, + "grid_x": 39, + "grid_y": 190, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y180": { + "bits": {}, + "grid_x": 39, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y181": { + "bits": {}, + "grid_x": 39, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y184": { + "bits": {}, + "grid_x": 39, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y185": { + "bits": {}, + "grid_x": 39, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y186": { + "bits": {}, + "grid_x": 39, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y187": { + "bits": {}, + "grid_x": 39, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y189": { + "bits": {}, + "grid_x": 39, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y19": { + "bits": {}, + "grid_x": 39, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y190": { + "bits": {}, + "grid_x": 39, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y191": { + "bits": {}, + "grid_x": 39, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y192": { + "bits": {}, + "grid_x": 39, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y194": { + "bits": {}, + "grid_x": 39, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y195": { + "bits": {}, + "grid_x": 39, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y196": { + "bits": {}, + "grid_x": 39, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y197": { + "bits": {}, + "grid_x": 39, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y199": { + "bits": {}, + "grid_x": 39, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y2": { + "bits": {}, + "grid_x": 39, + "grid_y": 206, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y20": { + "bits": {}, + "grid_x": 39, + "grid_y": 188, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y200": { + "bits": {}, + "grid_x": 39, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y201": { + "bits": {}, + "grid_x": 39, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y202": { + "bits": {}, + "grid_x": 39, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y204": { + "bits": {}, + "grid_x": 39, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y205": { + "bits": {}, + "grid_x": 39, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y206": { + "bits": {}, + "grid_x": 39, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y207": { + "bits": {}, + "grid_x": 39, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y208": { + "bits": {}, + "grid_x": 39, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y22": { + "bits": {}, + "grid_x": 39, + "grid_y": 186, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y23": { + "bits": {}, + "grid_x": 39, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y24": { + "bits": {}, + "grid_x": 39, + "grid_y": 184, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y25": { + "bits": {}, + "grid_x": 39, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y28": { + "bits": {}, + "grid_x": 39, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y29": { + "bits": {}, + "grid_x": 39, + "grid_y": 179, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y3": { + "bits": {}, + "grid_x": 39, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y30": { + "bits": {}, + "grid_x": 39, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y31": { + "bits": {}, + "grid_x": 39, + "grid_y": 177, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y33": { + "bits": {}, + "grid_x": 39, + "grid_y": 175, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y34": { + "bits": {}, + "grid_x": 39, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y35": { + "bits": {}, + "grid_x": 39, + "grid_y": 173, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y36": { + "bits": {}, + "grid_x": 39, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y38": { + "bits": {}, + "grid_x": 39, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y39": { + "bits": {}, + "grid_x": 39, + "grid_y": 169, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y4": { + "bits": {}, + "grid_x": 39, + "grid_y": 204, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y40": { + "bits": {}, + "grid_x": 39, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y41": { + "bits": {}, + "grid_x": 39, + "grid_y": 167, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y43": { + "bits": {}, + "grid_x": 39, + "grid_y": 165, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y44": { + "bits": {}, + "grid_x": 39, + "grid_y": 164, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y45": { + "bits": {}, + "grid_x": 39, + "grid_y": 163, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y46": { + "bits": {}, + "grid_x": 39, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y48": { + "bits": {}, + "grid_x": 39, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y49": { + "bits": {}, + "grid_x": 39, + "grid_y": 159, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y5": { + "bits": {}, + "grid_x": 39, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y50": { + "bits": {}, + "grid_x": 39, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y51": { + "bits": {}, + "grid_x": 39, + "grid_y": 157, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y54": { + "bits": {}, + "grid_x": 39, + "grid_y": 154, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y55": { + "bits": {}, + "grid_x": 39, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y56": { + "bits": {}, + "grid_x": 39, + "grid_y": 152, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y57": { + "bits": {}, + "grid_x": 39, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y59": { + "bits": {}, + "grid_x": 39, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y60": { + "bits": {}, + "grid_x": 39, + "grid_y": 148, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y61": { + "bits": {}, + "grid_x": 39, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y62": { + "bits": {}, + "grid_x": 39, + "grid_y": 146, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y64": { + "bits": {}, + "grid_x": 39, + "grid_y": 144, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y65": { + "bits": {}, + "grid_x": 39, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y66": { + "bits": {}, + "grid_x": 39, + "grid_y": 142, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y67": { + "bits": {}, + "grid_x": 39, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y69": { + "bits": {}, + "grid_x": 39, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y7": { + "bits": {}, + "grid_x": 39, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y70": { + "bits": {}, + "grid_x": 39, + "grid_y": 138, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y71": { + "bits": {}, + "grid_x": 39, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y72": { + "bits": {}, + "grid_x": 39, + "grid_y": 136, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y74": { + "bits": {}, + "grid_x": 39, + "grid_y": 134, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y75": { + "bits": {}, + "grid_x": 39, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y76": { + "bits": {}, + "grid_x": 39, + "grid_y": 132, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y77": { + "bits": {}, + "grid_x": 39, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y8": { + "bits": {}, + "grid_x": 39, + "grid_y": 200, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y80": { + "bits": {}, + "grid_x": 39, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y81": { + "bits": {}, + "grid_x": 39, + "grid_y": 127, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y82": { + "bits": {}, + "grid_x": 39, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y83": { + "bits": {}, + "grid_x": 39, + "grid_y": 125, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y85": { + "bits": {}, + "grid_x": 39, + "grid_y": 123, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y86": { + "bits": {}, + "grid_x": 39, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y87": { + "bits": {}, + "grid_x": 39, + "grid_y": 121, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y88": { + "bits": {}, + "grid_x": 39, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y9": { + "bits": {}, + "grid_x": 39, + "grid_y": 199, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y90": { + "bits": {}, + "grid_x": 39, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y91": { + "bits": {}, + "grid_x": 39, + "grid_y": 117, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y92": { + "bits": {}, + "grid_x": 39, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y93": { + "bits": {}, + "grid_x": 39, + "grid_y": 115, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y95": { + "bits": {}, + "grid_x": 39, + "grid_y": 113, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y96": { + "bits": {}, + "grid_x": 39, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y97": { + "bits": {}, + "grid_x": 39, + "grid_y": 111, + "sites": {}, + "type": "NULL" + }, + "NULL_X39Y98": { + "bits": {}, + "grid_x": 39, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X3Y0": { + "bits": {}, + "grid_x": 3, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X3Y104": { + "bits": {}, + "grid_x": 3, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X3Y156": { + "bits": {}, + "grid_x": 3, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X3Y208": { + "bits": {}, + "grid_x": 3, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X3Y52": { + "bits": {}, + "grid_x": 3, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X40Y0": { + "bits": {}, + "grid_x": 40, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X40Y104": { + "bits": {}, + "grid_x": 40, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X40Y156": { + "bits": {}, + "grid_x": 40, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X40Y208": { + "bits": {}, + "grid_x": 40, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X40Y52": { + "bits": {}, + "grid_x": 40, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X43Y0": { + "bits": {}, + "grid_x": 43, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X43Y208": { + "bits": {}, + "grid_x": 43, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X44Y0": { + "bits": {}, + "grid_x": 44, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X44Y208": { + "bits": {}, + "grid_x": 44, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X47Y0": { + "bits": {}, + "grid_x": 47, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X47Y104": { + "bits": {}, + "grid_x": 47, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X47Y156": { + "bits": {}, + "grid_x": 47, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X47Y208": { + "bits": {}, + "grid_x": 47, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X47Y52": { + "bits": {}, + "grid_x": 47, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y0": { + "bits": {}, + "grid_x": 48, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y10": { + "bits": {}, + "grid_x": 48, + "grid_y": 198, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y100": { + "bits": {}, + "grid_x": 48, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y101": { + "bits": {}, + "grid_x": 48, + "grid_y": 107, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y102": { + "bits": {}, + "grid_x": 48, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y103": { + "bits": {}, + "grid_x": 48, + "grid_y": 105, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y106": { + "bits": {}, + "grid_x": 48, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y107": { + "bits": {}, + "grid_x": 48, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y108": { + "bits": {}, + "grid_x": 48, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y109": { + "bits": {}, + "grid_x": 48, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y111": { + "bits": {}, + "grid_x": 48, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y112": { + "bits": {}, + "grid_x": 48, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y113": { + "bits": {}, + "grid_x": 48, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y114": { + "bits": {}, + "grid_x": 48, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y116": { + "bits": {}, + "grid_x": 48, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y117": { + "bits": {}, + "grid_x": 48, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y118": { + "bits": {}, + "grid_x": 48, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y119": { + "bits": {}, + "grid_x": 48, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y12": { + "bits": {}, + "grid_x": 48, + "grid_y": 196, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y121": { + "bits": {}, + "grid_x": 48, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y122": { + "bits": {}, + "grid_x": 48, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y123": { + "bits": {}, + "grid_x": 48, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y124": { + "bits": {}, + "grid_x": 48, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y126": { + "bits": {}, + "grid_x": 48, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y127": { + "bits": {}, + "grid_x": 48, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y128": { + "bits": {}, + "grid_x": 48, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y129": { + "bits": {}, + "grid_x": 48, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y13": { + "bits": {}, + "grid_x": 48, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y132": { + "bits": {}, + "grid_x": 48, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y133": { + "bits": {}, + "grid_x": 48, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y134": { + "bits": {}, + "grid_x": 48, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y135": { + "bits": {}, + "grid_x": 48, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y137": { + "bits": {}, + "grid_x": 48, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y138": { + "bits": {}, + "grid_x": 48, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y139": { + "bits": {}, + "grid_x": 48, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y14": { + "bits": {}, + "grid_x": 48, + "grid_y": 194, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y140": { + "bits": {}, + "grid_x": 48, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y142": { + "bits": {}, + "grid_x": 48, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y143": { + "bits": {}, + "grid_x": 48, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y144": { + "bits": {}, + "grid_x": 48, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y145": { + "bits": {}, + "grid_x": 48, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y147": { + "bits": {}, + "grid_x": 48, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y148": { + "bits": {}, + "grid_x": 48, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y149": { + "bits": {}, + "grid_x": 48, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y15": { + "bits": {}, + "grid_x": 48, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y150": { + "bits": {}, + "grid_x": 48, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y152": { + "bits": {}, + "grid_x": 48, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y153": { + "bits": {}, + "grid_x": 48, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y154": { + "bits": {}, + "grid_x": 48, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y155": { + "bits": {}, + "grid_x": 48, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y158": { + "bits": {}, + "grid_x": 48, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y159": { + "bits": {}, + "grid_x": 48, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y160": { + "bits": {}, + "grid_x": 48, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y161": { + "bits": {}, + "grid_x": 48, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y163": { + "bits": {}, + "grid_x": 48, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y164": { + "bits": {}, + "grid_x": 48, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y165": { + "bits": {}, + "grid_x": 48, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y166": { + "bits": {}, + "grid_x": 48, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y168": { + "bits": {}, + "grid_x": 48, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y169": { + "bits": {}, + "grid_x": 48, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y17": { + "bits": {}, + "grid_x": 48, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y170": { + "bits": {}, + "grid_x": 48, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y171": { + "bits": {}, + "grid_x": 48, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y173": { + "bits": {}, + "grid_x": 48, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y174": { + "bits": {}, + "grid_x": 48, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y175": { + "bits": {}, + "grid_x": 48, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y176": { + "bits": {}, + "grid_x": 48, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y178": { + "bits": {}, + "grid_x": 48, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y179": { + "bits": {}, + "grid_x": 48, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y18": { + "bits": {}, + "grid_x": 48, + "grid_y": 190, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y180": { + "bits": {}, + "grid_x": 48, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y181": { + "bits": {}, + "grid_x": 48, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y184": { + "bits": {}, + "grid_x": 48, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y185": { + "bits": {}, + "grid_x": 48, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y186": { + "bits": {}, + "grid_x": 48, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y187": { + "bits": {}, + "grid_x": 48, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y189": { + "bits": {}, + "grid_x": 48, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y19": { + "bits": {}, + "grid_x": 48, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y190": { + "bits": {}, + "grid_x": 48, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y191": { + "bits": {}, + "grid_x": 48, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y192": { + "bits": {}, + "grid_x": 48, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y194": { + "bits": {}, + "grid_x": 48, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y195": { + "bits": {}, + "grid_x": 48, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y196": { + "bits": {}, + "grid_x": 48, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y197": { + "bits": {}, + "grid_x": 48, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y199": { + "bits": {}, + "grid_x": 48, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y2": { + "bits": {}, + "grid_x": 48, + "grid_y": 206, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y20": { + "bits": {}, + "grid_x": 48, + "grid_y": 188, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y200": { + "bits": {}, + "grid_x": 48, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y201": { + "bits": {}, + "grid_x": 48, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y202": { + "bits": {}, + "grid_x": 48, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y204": { + "bits": {}, + "grid_x": 48, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y205": { + "bits": {}, + "grid_x": 48, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y206": { + "bits": {}, + "grid_x": 48, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y207": { + "bits": {}, + "grid_x": 48, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y208": { + "bits": {}, + "grid_x": 48, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y22": { + "bits": {}, + "grid_x": 48, + "grid_y": 186, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y23": { + "bits": {}, + "grid_x": 48, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y24": { + "bits": {}, + "grid_x": 48, + "grid_y": 184, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y25": { + "bits": {}, + "grid_x": 48, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y28": { + "bits": {}, + "grid_x": 48, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y29": { + "bits": {}, + "grid_x": 48, + "grid_y": 179, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y3": { + "bits": {}, + "grid_x": 48, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y30": { + "bits": {}, + "grid_x": 48, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y31": { + "bits": {}, + "grid_x": 48, + "grid_y": 177, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y33": { + "bits": {}, + "grid_x": 48, + "grid_y": 175, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y34": { + "bits": {}, + "grid_x": 48, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y35": { + "bits": {}, + "grid_x": 48, + "grid_y": 173, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y36": { + "bits": {}, + "grid_x": 48, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y38": { + "bits": {}, + "grid_x": 48, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y39": { + "bits": {}, + "grid_x": 48, + "grid_y": 169, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y4": { + "bits": {}, + "grid_x": 48, + "grid_y": 204, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y40": { + "bits": {}, + "grid_x": 48, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y41": { + "bits": {}, + "grid_x": 48, + "grid_y": 167, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y43": { + "bits": {}, + "grid_x": 48, + "grid_y": 165, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y44": { + "bits": {}, + "grid_x": 48, + "grid_y": 164, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y45": { + "bits": {}, + "grid_x": 48, + "grid_y": 163, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y46": { + "bits": {}, + "grid_x": 48, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y48": { + "bits": {}, + "grid_x": 48, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y49": { + "bits": {}, + "grid_x": 48, + "grid_y": 159, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y5": { + "bits": {}, + "grid_x": 48, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y50": { + "bits": {}, + "grid_x": 48, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y51": { + "bits": {}, + "grid_x": 48, + "grid_y": 157, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y54": { + "bits": {}, + "grid_x": 48, + "grid_y": 154, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y55": { + "bits": {}, + "grid_x": 48, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y56": { + "bits": {}, + "grid_x": 48, + "grid_y": 152, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y57": { + "bits": {}, + "grid_x": 48, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y59": { + "bits": {}, + "grid_x": 48, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y60": { + "bits": {}, + "grid_x": 48, + "grid_y": 148, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y61": { + "bits": {}, + "grid_x": 48, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y62": { + "bits": {}, + "grid_x": 48, + "grid_y": 146, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y64": { + "bits": {}, + "grid_x": 48, + "grid_y": 144, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y65": { + "bits": {}, + "grid_x": 48, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y66": { + "bits": {}, + "grid_x": 48, + "grid_y": 142, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y67": { + "bits": {}, + "grid_x": 48, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y69": { + "bits": {}, + "grid_x": 48, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y7": { + "bits": {}, + "grid_x": 48, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y70": { + "bits": {}, + "grid_x": 48, + "grid_y": 138, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y71": { + "bits": {}, + "grid_x": 48, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y72": { + "bits": {}, + "grid_x": 48, + "grid_y": 136, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y74": { + "bits": {}, + "grid_x": 48, + "grid_y": 134, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y75": { + "bits": {}, + "grid_x": 48, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y76": { + "bits": {}, + "grid_x": 48, + "grid_y": 132, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y77": { + "bits": {}, + "grid_x": 48, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y8": { + "bits": {}, + "grid_x": 48, + "grid_y": 200, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y80": { + "bits": {}, + "grid_x": 48, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y81": { + "bits": {}, + "grid_x": 48, + "grid_y": 127, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y82": { + "bits": {}, + "grid_x": 48, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y83": { + "bits": {}, + "grid_x": 48, + "grid_y": 125, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y85": { + "bits": {}, + "grid_x": 48, + "grid_y": 123, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y86": { + "bits": {}, + "grid_x": 48, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y87": { + "bits": {}, + "grid_x": 48, + "grid_y": 121, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y88": { + "bits": {}, + "grid_x": 48, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y9": { + "bits": {}, + "grid_x": 48, + "grid_y": 199, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y90": { + "bits": {}, + "grid_x": 48, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y91": { + "bits": {}, + "grid_x": 48, + "grid_y": 117, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y92": { + "bits": {}, + "grid_x": 48, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y93": { + "bits": {}, + "grid_x": 48, + "grid_y": 115, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y95": { + "bits": {}, + "grid_x": 48, + "grid_y": 113, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y96": { + "bits": {}, + "grid_x": 48, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y97": { + "bits": {}, + "grid_x": 48, + "grid_y": 111, + "sites": {}, + "type": "NULL" + }, + "NULL_X48Y98": { + "bits": {}, + "grid_x": 48, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X49Y0": { + "bits": {}, + "grid_x": 49, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X49Y104": { + "bits": {}, + "grid_x": 49, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X49Y156": { + "bits": {}, + "grid_x": 49, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X49Y208": { + "bits": {}, + "grid_x": 49, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X49Y52": { + "bits": {}, + "grid_x": 49, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X50Y0": { + "bits": {}, + "grid_x": 50, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X50Y104": { + "bits": {}, + "grid_x": 50, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X50Y156": { + "bits": {}, + "grid_x": 50, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X50Y208": { + "bits": {}, + "grid_x": 50, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X50Y52": { + "bits": {}, + "grid_x": 50, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X51Y104": { + "bits": {}, + "grid_x": 51, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X52Y104": { + "bits": {}, + "grid_x": 52, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X53Y0": { + "bits": {}, + "grid_x": 53, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X53Y104": { + "bits": {}, + "grid_x": 53, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X53Y156": { + "bits": {}, + "grid_x": 53, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X53Y208": { + "bits": {}, + "grid_x": 53, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X53Y52": { + "bits": {}, + "grid_x": 53, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X54Y0": { + "bits": {}, + "grid_x": 54, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X54Y104": { + "bits": {}, + "grid_x": 54, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X54Y156": { + "bits": {}, + "grid_x": 54, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X54Y208": { + "bits": {}, + "grid_x": 54, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X54Y52": { + "bits": {}, + "grid_x": 54, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X55Y104": { + "bits": {}, + "grid_x": 55, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X56Y104": { + "bits": {}, + "grid_x": 56, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X57Y0": { + "bits": {}, + "grid_x": 57, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X57Y104": { + "bits": {}, + "grid_x": 57, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X57Y156": { + "bits": {}, + "grid_x": 57, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X57Y208": { + "bits": {}, + "grid_x": 57, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X57Y52": { + "bits": {}, + "grid_x": 57, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X58Y0": { + "bits": {}, + "grid_x": 58, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X58Y104": { + "bits": {}, + "grid_x": 58, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X58Y156": { + "bits": {}, + "grid_x": 58, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X58Y208": { + "bits": {}, + "grid_x": 58, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X58Y52": { + "bits": {}, + "grid_x": 58, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X59Y104": { + "bits": {}, + "grid_x": 59, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X60Y104": { + "bits": {}, + "grid_x": 60, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y0": { + "bits": {}, + "grid_x": 61, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y100": { + "bits": {}, + "grid_x": 61, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y101": { + "bits": {}, + "grid_x": 61, + "grid_y": 107, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y102": { + "bits": {}, + "grid_x": 61, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y103": { + "bits": {}, + "grid_x": 61, + "grid_y": 105, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y104": { + "bits": {}, + "grid_x": 61, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y132": { + "bits": {}, + "grid_x": 61, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y133": { + "bits": {}, + "grid_x": 61, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y134": { + "bits": {}, + "grid_x": 61, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y135": { + "bits": {}, + "grid_x": 61, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y136": { + "bits": {}, + "grid_x": 61, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y137": { + "bits": {}, + "grid_x": 61, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y138": { + "bits": {}, + "grid_x": 61, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y139": { + "bits": {}, + "grid_x": 61, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y140": { + "bits": {}, + "grid_x": 61, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y142": { + "bits": {}, + "grid_x": 61, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y143": { + "bits": {}, + "grid_x": 61, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y144": { + "bits": {}, + "grid_x": 61, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y145": { + "bits": {}, + "grid_x": 61, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y146": { + "bits": {}, + "grid_x": 61, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y147": { + "bits": {}, + "grid_x": 61, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y148": { + "bits": {}, + "grid_x": 61, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y149": { + "bits": {}, + "grid_x": 61, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y150": { + "bits": {}, + "grid_x": 61, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y152": { + "bits": {}, + "grid_x": 61, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y153": { + "bits": {}, + "grid_x": 61, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y154": { + "bits": {}, + "grid_x": 61, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y155": { + "bits": {}, + "grid_x": 61, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y156": { + "bits": {}, + "grid_x": 61, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y208": { + "bits": {}, + "grid_x": 61, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y52": { + "bits": {}, + "grid_x": 61, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y53": { + "bits": {}, + "grid_x": 61, + "grid_y": 155, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y54": { + "bits": {}, + "grid_x": 61, + "grid_y": 154, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y55": { + "bits": {}, + "grid_x": 61, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y56": { + "bits": {}, + "grid_x": 61, + "grid_y": 152, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y57": { + "bits": {}, + "grid_x": 61, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y58": { + "bits": {}, + "grid_x": 61, + "grid_y": 150, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y59": { + "bits": {}, + "grid_x": 61, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y60": { + "bits": {}, + "grid_x": 61, + "grid_y": 148, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y61": { + "bits": {}, + "grid_x": 61, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y62": { + "bits": {}, + "grid_x": 61, + "grid_y": 146, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y64": { + "bits": {}, + "grid_x": 61, + "grid_y": 144, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y65": { + "bits": {}, + "grid_x": 61, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y66": { + "bits": {}, + "grid_x": 61, + "grid_y": 142, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y67": { + "bits": {}, + "grid_x": 61, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y68": { + "bits": {}, + "grid_x": 61, + "grid_y": 140, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y69": { + "bits": {}, + "grid_x": 61, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y70": { + "bits": {}, + "grid_x": 61, + "grid_y": 138, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y71": { + "bits": {}, + "grid_x": 61, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y72": { + "bits": {}, + "grid_x": 61, + "grid_y": 136, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y73": { + "bits": {}, + "grid_x": 61, + "grid_y": 135, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y74": { + "bits": {}, + "grid_x": 61, + "grid_y": 134, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y75": { + "bits": {}, + "grid_x": 61, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y76": { + "bits": {}, + "grid_x": 61, + "grid_y": 132, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y77": { + "bits": {}, + "grid_x": 61, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y78": { + "bits": {}, + "grid_x": 61, + "grid_y": 130, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y79": { + "bits": {}, + "grid_x": 61, + "grid_y": 129, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y80": { + "bits": {}, + "grid_x": 61, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y81": { + "bits": {}, + "grid_x": 61, + "grid_y": 127, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y82": { + "bits": {}, + "grid_x": 61, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y83": { + "bits": {}, + "grid_x": 61, + "grid_y": 125, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y85": { + "bits": {}, + "grid_x": 61, + "grid_y": 123, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y86": { + "bits": {}, + "grid_x": 61, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y87": { + "bits": {}, + "grid_x": 61, + "grid_y": 121, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y88": { + "bits": {}, + "grid_x": 61, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y89": { + "bits": {}, + "grid_x": 61, + "grid_y": 119, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y90": { + "bits": {}, + "grid_x": 61, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y91": { + "bits": {}, + "grid_x": 61, + "grid_y": 117, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y92": { + "bits": {}, + "grid_x": 61, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y93": { + "bits": {}, + "grid_x": 61, + "grid_y": 115, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y95": { + "bits": {}, + "grid_x": 61, + "grid_y": 113, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y96": { + "bits": {}, + "grid_x": 61, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y97": { + "bits": {}, + "grid_x": 61, + "grid_y": 111, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y98": { + "bits": {}, + "grid_x": 61, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X61Y99": { + "bits": {}, + "grid_x": 61, + "grid_y": 109, + "sites": {}, + "type": "NULL" + }, + "NULL_X62Y0": { + "bits": {}, + "grid_x": 62, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X62Y104": { + "bits": {}, + "grid_x": 62, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X62Y156": { + "bits": {}, + "grid_x": 62, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X62Y208": { + "bits": {}, + "grid_x": 62, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X62Y52": { + "bits": {}, + "grid_x": 62, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X63Y0": { + "bits": {}, + "grid_x": 63, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X63Y104": { + "bits": {}, + "grid_x": 63, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X63Y156": { + "bits": {}, + "grid_x": 63, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X63Y208": { + "bits": {}, + "grid_x": 63, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X63Y52": { + "bits": {}, + "grid_x": 63, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X66Y0": { + "bits": {}, + "grid_x": 66, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X66Y104": { + "bits": {}, + "grid_x": 66, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X66Y156": { + "bits": {}, + "grid_x": 66, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X66Y208": { + "bits": {}, + "grid_x": 66, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X66Y52": { + "bits": {}, + "grid_x": 66, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y101": { + "bits": {}, + "grid_x": 67, + "grid_y": 107, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y102": { + "bits": {}, + "grid_x": 67, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y103": { + "bits": {}, + "grid_x": 67, + "grid_y": 105, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y106": { + "bits": {}, + "grid_x": 67, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y107": { + "bits": {}, + "grid_x": 67, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y108": { + "bits": {}, + "grid_x": 67, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y118": { + "bits": {}, + "grid_x": 67, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y126": { + "bits": {}, + "grid_x": 67, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y127": { + "bits": {}, + "grid_x": 67, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y128": { + "bits": {}, + "grid_x": 67, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y129": { + "bits": {}, + "grid_x": 67, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y131": { + "bits": {}, + "grid_x": 67, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y132": { + "bits": {}, + "grid_x": 67, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y133": { + "bits": {}, + "grid_x": 67, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y134": { + "bits": {}, + "grid_x": 67, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y14": { + "bits": {}, + "grid_x": 67, + "grid_y": 194, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y143": { + "bits": {}, + "grid_x": 67, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y170": { + "bits": {}, + "grid_x": 67, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y178": { + "bits": {}, + "grid_x": 67, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y179": { + "bits": {}, + "grid_x": 67, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y180": { + "bits": {}, + "grid_x": 67, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y181": { + "bits": {}, + "grid_x": 67, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y183": { + "bits": {}, + "grid_x": 67, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y184": { + "bits": {}, + "grid_x": 67, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y185": { + "bits": {}, + "grid_x": 67, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y186": { + "bits": {}, + "grid_x": 67, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y195": { + "bits": {}, + "grid_x": 67, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y22": { + "bits": {}, + "grid_x": 67, + "grid_y": 186, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y23": { + "bits": {}, + "grid_x": 67, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y24": { + "bits": {}, + "grid_x": 67, + "grid_y": 184, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y25": { + "bits": {}, + "grid_x": 67, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y27": { + "bits": {}, + "grid_x": 67, + "grid_y": 181, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y28": { + "bits": {}, + "grid_x": 67, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y29": { + "bits": {}, + "grid_x": 67, + "grid_y": 179, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y30": { + "bits": {}, + "grid_x": 67, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y39": { + "bits": {}, + "grid_x": 67, + "grid_y": 169, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y55": { + "bits": {}, + "grid_x": 67, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y56": { + "bits": {}, + "grid_x": 67, + "grid_y": 152, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y57": { + "bits": {}, + "grid_x": 67, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y58": { + "bits": {}, + "grid_x": 67, + "grid_y": 150, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y59": { + "bits": {}, + "grid_x": 67, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y60": { + "bits": {}, + "grid_x": 67, + "grid_y": 148, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y66": { + "bits": {}, + "grid_x": 67, + "grid_y": 142, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y74": { + "bits": {}, + "grid_x": 67, + "grid_y": 134, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y75": { + "bits": {}, + "grid_x": 67, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y76": { + "bits": {}, + "grid_x": 67, + "grid_y": 132, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y77": { + "bits": {}, + "grid_x": 67, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y79": { + "bits": {}, + "grid_x": 67, + "grid_y": 129, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y80": { + "bits": {}, + "grid_x": 67, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y81": { + "bits": {}, + "grid_x": 67, + "grid_y": 127, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y82": { + "bits": {}, + "grid_x": 67, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X67Y91": { + "bits": {}, + "grid_x": 67, + "grid_y": 117, + "sites": {}, + "type": "NULL" + }, + "NULL_X68Y0": { + "bits": {}, + "grid_x": 68, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X68Y104": { + "bits": {}, + "grid_x": 68, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X68Y156": { + "bits": {}, + "grid_x": 68, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X68Y208": { + "bits": {}, + "grid_x": 68, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X68Y52": { + "bits": {}, + "grid_x": 68, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X69Y0": { + "bits": {}, + "grid_x": 69, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X69Y208": { + "bits": {}, + "grid_x": 69, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X6Y0": { + "bits": {}, + "grid_x": 6, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X6Y104": { + "bits": {}, + "grid_x": 6, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X6Y156": { + "bits": {}, + "grid_x": 6, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X6Y208": { + "bits": {}, + "grid_x": 6, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X6Y52": { + "bits": {}, + "grid_x": 6, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X72Y0": { + "bits": {}, + "grid_x": 72, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X72Y104": { + "bits": {}, + "grid_x": 72, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X72Y208": { + "bits": {}, + "grid_x": 72, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X73Y0": { + "bits": {}, + "grid_x": 73, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X73Y104": { + "bits": {}, + "grid_x": 73, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X73Y208": { + "bits": {}, + "grid_x": 73, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X76Y0": { + "bits": {}, + "grid_x": 76, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X76Y104": { + "bits": {}, + "grid_x": 76, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X76Y208": { + "bits": {}, + "grid_x": 76, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y0": { + "bits": {}, + "grid_x": 77, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y10": { + "bits": {}, + "grid_x": 77, + "grid_y": 198, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y100": { + "bits": {}, + "grid_x": 77, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y101": { + "bits": {}, + "grid_x": 77, + "grid_y": 107, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y102": { + "bits": {}, + "grid_x": 77, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y103": { + "bits": {}, + "grid_x": 77, + "grid_y": 105, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y104": { + "bits": {}, + "grid_x": 77, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y12": { + "bits": {}, + "grid_x": 77, + "grid_y": 196, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y13": { + "bits": {}, + "grid_x": 77, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y132": { + "bits": {}, + "grid_x": 77, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y133": { + "bits": {}, + "grid_x": 77, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y134": { + "bits": {}, + "grid_x": 77, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y135": { + "bits": {}, + "grid_x": 77, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y137": { + "bits": {}, + "grid_x": 77, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y138": { + "bits": {}, + "grid_x": 77, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y139": { + "bits": {}, + "grid_x": 77, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y14": { + "bits": {}, + "grid_x": 77, + "grid_y": 194, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y140": { + "bits": {}, + "grid_x": 77, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y142": { + "bits": {}, + "grid_x": 77, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y143": { + "bits": {}, + "grid_x": 77, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y144": { + "bits": {}, + "grid_x": 77, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y145": { + "bits": {}, + "grid_x": 77, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y147": { + "bits": {}, + "grid_x": 77, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y148": { + "bits": {}, + "grid_x": 77, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y149": { + "bits": {}, + "grid_x": 77, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y15": { + "bits": {}, + "grid_x": 77, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y150": { + "bits": {}, + "grid_x": 77, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y152": { + "bits": {}, + "grid_x": 77, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y153": { + "bits": {}, + "grid_x": 77, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y154": { + "bits": {}, + "grid_x": 77, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y155": { + "bits": {}, + "grid_x": 77, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y158": { + "bits": {}, + "grid_x": 77, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y159": { + "bits": {}, + "grid_x": 77, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y160": { + "bits": {}, + "grid_x": 77, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y161": { + "bits": {}, + "grid_x": 77, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y163": { + "bits": {}, + "grid_x": 77, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y164": { + "bits": {}, + "grid_x": 77, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y165": { + "bits": {}, + "grid_x": 77, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y166": { + "bits": {}, + "grid_x": 77, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y168": { + "bits": {}, + "grid_x": 77, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y169": { + "bits": {}, + "grid_x": 77, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y17": { + "bits": {}, + "grid_x": 77, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y170": { + "bits": {}, + "grid_x": 77, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y171": { + "bits": {}, + "grid_x": 77, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y173": { + "bits": {}, + "grid_x": 77, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y174": { + "bits": {}, + "grid_x": 77, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y175": { + "bits": {}, + "grid_x": 77, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y176": { + "bits": {}, + "grid_x": 77, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y178": { + "bits": {}, + "grid_x": 77, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y179": { + "bits": {}, + "grid_x": 77, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y18": { + "bits": {}, + "grid_x": 77, + "grid_y": 190, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y180": { + "bits": {}, + "grid_x": 77, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y181": { + "bits": {}, + "grid_x": 77, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y184": { + "bits": {}, + "grid_x": 77, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y185": { + "bits": {}, + "grid_x": 77, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y186": { + "bits": {}, + "grid_x": 77, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y187": { + "bits": {}, + "grid_x": 77, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y189": { + "bits": {}, + "grid_x": 77, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y19": { + "bits": {}, + "grid_x": 77, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y190": { + "bits": {}, + "grid_x": 77, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y191": { + "bits": {}, + "grid_x": 77, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y192": { + "bits": {}, + "grid_x": 77, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y194": { + "bits": {}, + "grid_x": 77, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y195": { + "bits": {}, + "grid_x": 77, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y196": { + "bits": {}, + "grid_x": 77, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y197": { + "bits": {}, + "grid_x": 77, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y199": { + "bits": {}, + "grid_x": 77, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y2": { + "bits": {}, + "grid_x": 77, + "grid_y": 206, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y20": { + "bits": {}, + "grid_x": 77, + "grid_y": 188, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y200": { + "bits": {}, + "grid_x": 77, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y201": { + "bits": {}, + "grid_x": 77, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y202": { + "bits": {}, + "grid_x": 77, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y204": { + "bits": {}, + "grid_x": 77, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y205": { + "bits": {}, + "grid_x": 77, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y206": { + "bits": {}, + "grid_x": 77, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y207": { + "bits": {}, + "grid_x": 77, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y208": { + "bits": {}, + "grid_x": 77, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y22": { + "bits": {}, + "grid_x": 77, + "grid_y": 186, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y23": { + "bits": {}, + "grid_x": 77, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y24": { + "bits": {}, + "grid_x": 77, + "grid_y": 184, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y25": { + "bits": {}, + "grid_x": 77, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y28": { + "bits": {}, + "grid_x": 77, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y29": { + "bits": {}, + "grid_x": 77, + "grid_y": 179, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y3": { + "bits": {}, + "grid_x": 77, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y30": { + "bits": {}, + "grid_x": 77, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y31": { + "bits": {}, + "grid_x": 77, + "grid_y": 177, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y33": { + "bits": {}, + "grid_x": 77, + "grid_y": 175, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y34": { + "bits": {}, + "grid_x": 77, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y35": { + "bits": {}, + "grid_x": 77, + "grid_y": 173, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y36": { + "bits": {}, + "grid_x": 77, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y38": { + "bits": {}, + "grid_x": 77, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y39": { + "bits": {}, + "grid_x": 77, + "grid_y": 169, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y4": { + "bits": {}, + "grid_x": 77, + "grid_y": 204, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y40": { + "bits": {}, + "grid_x": 77, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y41": { + "bits": {}, + "grid_x": 77, + "grid_y": 167, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y43": { + "bits": {}, + "grid_x": 77, + "grid_y": 165, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y44": { + "bits": {}, + "grid_x": 77, + "grid_y": 164, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y45": { + "bits": {}, + "grid_x": 77, + "grid_y": 163, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y46": { + "bits": {}, + "grid_x": 77, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y48": { + "bits": {}, + "grid_x": 77, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y49": { + "bits": {}, + "grid_x": 77, + "grid_y": 159, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y5": { + "bits": {}, + "grid_x": 77, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y50": { + "bits": {}, + "grid_x": 77, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y51": { + "bits": {}, + "grid_x": 77, + "grid_y": 157, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y54": { + "bits": {}, + "grid_x": 77, + "grid_y": 154, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y55": { + "bits": {}, + "grid_x": 77, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y56": { + "bits": {}, + "grid_x": 77, + "grid_y": 152, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y57": { + "bits": {}, + "grid_x": 77, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y59": { + "bits": {}, + "grid_x": 77, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y60": { + "bits": {}, + "grid_x": 77, + "grid_y": 148, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y61": { + "bits": {}, + "grid_x": 77, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y62": { + "bits": {}, + "grid_x": 77, + "grid_y": 146, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y64": { + "bits": {}, + "grid_x": 77, + "grid_y": 144, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y65": { + "bits": {}, + "grid_x": 77, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y66": { + "bits": {}, + "grid_x": 77, + "grid_y": 142, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y67": { + "bits": {}, + "grid_x": 77, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y69": { + "bits": {}, + "grid_x": 77, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y7": { + "bits": {}, + "grid_x": 77, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y70": { + "bits": {}, + "grid_x": 77, + "grid_y": 138, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y71": { + "bits": {}, + "grid_x": 77, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y72": { + "bits": {}, + "grid_x": 77, + "grid_y": 136, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y74": { + "bits": {}, + "grid_x": 77, + "grid_y": 134, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y75": { + "bits": {}, + "grid_x": 77, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y76": { + "bits": {}, + "grid_x": 77, + "grid_y": 132, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y77": { + "bits": {}, + "grid_x": 77, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y8": { + "bits": {}, + "grid_x": 77, + "grid_y": 200, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y80": { + "bits": {}, + "grid_x": 77, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y81": { + "bits": {}, + "grid_x": 77, + "grid_y": 127, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y82": { + "bits": {}, + "grid_x": 77, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y83": { + "bits": {}, + "grid_x": 77, + "grid_y": 125, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y85": { + "bits": {}, + "grid_x": 77, + "grid_y": 123, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y86": { + "bits": {}, + "grid_x": 77, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y87": { + "bits": {}, + "grid_x": 77, + "grid_y": 121, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y88": { + "bits": {}, + "grid_x": 77, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y9": { + "bits": {}, + "grid_x": 77, + "grid_y": 199, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y90": { + "bits": {}, + "grid_x": 77, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y91": { + "bits": {}, + "grid_x": 77, + "grid_y": 117, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y92": { + "bits": {}, + "grid_x": 77, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y93": { + "bits": {}, + "grid_x": 77, + "grid_y": 115, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y95": { + "bits": {}, + "grid_x": 77, + "grid_y": 113, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y96": { + "bits": {}, + "grid_x": 77, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y97": { + "bits": {}, + "grid_x": 77, + "grid_y": 111, + "sites": {}, + "type": "NULL" + }, + "NULL_X77Y98": { + "bits": {}, + "grid_x": 77, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X78Y0": { + "bits": {}, + "grid_x": 78, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X78Y104": { + "bits": {}, + "grid_x": 78, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X78Y156": { + "bits": {}, + "grid_x": 78, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X78Y208": { + "bits": {}, + "grid_x": 78, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X78Y52": { + "bits": {}, + "grid_x": 78, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y0": { + "bits": {}, + "grid_x": 7, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y10": { + "bits": {}, + "grid_x": 7, + "grid_y": 198, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y100": { + "bits": {}, + "grid_x": 7, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y101": { + "bits": {}, + "grid_x": 7, + "grid_y": 107, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y102": { + "bits": {}, + "grid_x": 7, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y104": { + "bits": {}, + "grid_x": 7, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y106": { + "bits": {}, + "grid_x": 7, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y107": { + "bits": {}, + "grid_x": 7, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y108": { + "bits": {}, + "grid_x": 7, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y109": { + "bits": {}, + "grid_x": 7, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y11": { + "bits": {}, + "grid_x": 7, + "grid_y": 197, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y110": { + "bits": {}, + "grid_x": 7, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y111": { + "bits": {}, + "grid_x": 7, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y113": { + "bits": {}, + "grid_x": 7, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y114": { + "bits": {}, + "grid_x": 7, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y115": { + "bits": {}, + "grid_x": 7, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y116": { + "bits": {}, + "grid_x": 7, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y117": { + "bits": {}, + "grid_x": 7, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y118": { + "bits": {}, + "grid_x": 7, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y119": { + "bits": {}, + "grid_x": 7, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y12": { + "bits": {}, + "grid_x": 7, + "grid_y": 196, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y120": { + "bits": {}, + "grid_x": 7, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y121": { + "bits": {}, + "grid_x": 7, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y122": { + "bits": {}, + "grid_x": 7, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y123": { + "bits": {}, + "grid_x": 7, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y125": { + "bits": {}, + "grid_x": 7, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y126": { + "bits": {}, + "grid_x": 7, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y127": { + "bits": {}, + "grid_x": 7, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y128": { + "bits": {}, + "grid_x": 7, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y129": { + "bits": {}, + "grid_x": 7, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y13": { + "bits": {}, + "grid_x": 7, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y131": { + "bits": {}, + "grid_x": 7, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y132": { + "bits": {}, + "grid_x": 7, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y133": { + "bits": {}, + "grid_x": 7, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y134": { + "bits": {}, + "grid_x": 7, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y135": { + "bits": {}, + "grid_x": 7, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y136": { + "bits": {}, + "grid_x": 7, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y138": { + "bits": {}, + "grid_x": 7, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y139": { + "bits": {}, + "grid_x": 7, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y14": { + "bits": {}, + "grid_x": 7, + "grid_y": 194, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y140": { + "bits": {}, + "grid_x": 7, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y141": { + "bits": {}, + "grid_x": 7, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y142": { + "bits": {}, + "grid_x": 7, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y143": { + "bits": {}, + "grid_x": 7, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y144": { + "bits": {}, + "grid_x": 7, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y145": { + "bits": {}, + "grid_x": 7, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y146": { + "bits": {}, + "grid_x": 7, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y147": { + "bits": {}, + "grid_x": 7, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y148": { + "bits": {}, + "grid_x": 7, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y15": { + "bits": {}, + "grid_x": 7, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y150": { + "bits": {}, + "grid_x": 7, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y151": { + "bits": {}, + "grid_x": 7, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y152": { + "bits": {}, + "grid_x": 7, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y153": { + "bits": {}, + "grid_x": 7, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y154": { + "bits": {}, + "grid_x": 7, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y156": { + "bits": {}, + "grid_x": 7, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y158": { + "bits": {}, + "grid_x": 7, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y159": { + "bits": {}, + "grid_x": 7, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y16": { + "bits": {}, + "grid_x": 7, + "grid_y": 192, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y160": { + "bits": {}, + "grid_x": 7, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y161": { + "bits": {}, + "grid_x": 7, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y162": { + "bits": {}, + "grid_x": 7, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y163": { + "bits": {}, + "grid_x": 7, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y165": { + "bits": {}, + "grid_x": 7, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y166": { + "bits": {}, + "grid_x": 7, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y167": { + "bits": {}, + "grid_x": 7, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y168": { + "bits": {}, + "grid_x": 7, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y169": { + "bits": {}, + "grid_x": 7, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y17": { + "bits": {}, + "grid_x": 7, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y170": { + "bits": {}, + "grid_x": 7, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y171": { + "bits": {}, + "grid_x": 7, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y172": { + "bits": {}, + "grid_x": 7, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y173": { + "bits": {}, + "grid_x": 7, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y174": { + "bits": {}, + "grid_x": 7, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y175": { + "bits": {}, + "grid_x": 7, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y177": { + "bits": {}, + "grid_x": 7, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y178": { + "bits": {}, + "grid_x": 7, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y179": { + "bits": {}, + "grid_x": 7, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y18": { + "bits": {}, + "grid_x": 7, + "grid_y": 190, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y180": { + "bits": {}, + "grid_x": 7, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y181": { + "bits": {}, + "grid_x": 7, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y183": { + "bits": {}, + "grid_x": 7, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y184": { + "bits": {}, + "grid_x": 7, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y185": { + "bits": {}, + "grid_x": 7, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y186": { + "bits": {}, + "grid_x": 7, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y187": { + "bits": {}, + "grid_x": 7, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y188": { + "bits": {}, + "grid_x": 7, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y19": { + "bits": {}, + "grid_x": 7, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y190": { + "bits": {}, + "grid_x": 7, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y191": { + "bits": {}, + "grid_x": 7, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y192": { + "bits": {}, + "grid_x": 7, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y193": { + "bits": {}, + "grid_x": 7, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y194": { + "bits": {}, + "grid_x": 7, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y195": { + "bits": {}, + "grid_x": 7, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y196": { + "bits": {}, + "grid_x": 7, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y197": { + "bits": {}, + "grid_x": 7, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y198": { + "bits": {}, + "grid_x": 7, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y199": { + "bits": {}, + "grid_x": 7, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y2": { + "bits": {}, + "grid_x": 7, + "grid_y": 206, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y200": { + "bits": {}, + "grid_x": 7, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y202": { + "bits": {}, + "grid_x": 7, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y203": { + "bits": {}, + "grid_x": 7, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y204": { + "bits": {}, + "grid_x": 7, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y205": { + "bits": {}, + "grid_x": 7, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y206": { + "bits": {}, + "grid_x": 7, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y208": { + "bits": {}, + "grid_x": 7, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y21": { + "bits": {}, + "grid_x": 7, + "grid_y": 187, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y22": { + "bits": {}, + "grid_x": 7, + "grid_y": 186, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y23": { + "bits": {}, + "grid_x": 7, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y24": { + "bits": {}, + "grid_x": 7, + "grid_y": 184, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y25": { + "bits": {}, + "grid_x": 7, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y27": { + "bits": {}, + "grid_x": 7, + "grid_y": 181, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y28": { + "bits": {}, + "grid_x": 7, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y29": { + "bits": {}, + "grid_x": 7, + "grid_y": 179, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y3": { + "bits": {}, + "grid_x": 7, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y30": { + "bits": {}, + "grid_x": 7, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y31": { + "bits": {}, + "grid_x": 7, + "grid_y": 177, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y32": { + "bits": {}, + "grid_x": 7, + "grid_y": 176, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y34": { + "bits": {}, + "grid_x": 7, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y35": { + "bits": {}, + "grid_x": 7, + "grid_y": 173, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y36": { + "bits": {}, + "grid_x": 7, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y37": { + "bits": {}, + "grid_x": 7, + "grid_y": 171, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y38": { + "bits": {}, + "grid_x": 7, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y39": { + "bits": {}, + "grid_x": 7, + "grid_y": 169, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y4": { + "bits": {}, + "grid_x": 7, + "grid_y": 204, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y40": { + "bits": {}, + "grid_x": 7, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y41": { + "bits": {}, + "grid_x": 7, + "grid_y": 167, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y42": { + "bits": {}, + "grid_x": 7, + "grid_y": 166, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y43": { + "bits": {}, + "grid_x": 7, + "grid_y": 165, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y44": { + "bits": {}, + "grid_x": 7, + "grid_y": 164, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y46": { + "bits": {}, + "grid_x": 7, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y47": { + "bits": {}, + "grid_x": 7, + "grid_y": 161, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y48": { + "bits": {}, + "grid_x": 7, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y49": { + "bits": {}, + "grid_x": 7, + "grid_y": 159, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y5": { + "bits": {}, + "grid_x": 7, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y50": { + "bits": {}, + "grid_x": 7, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y52": { + "bits": {}, + "grid_x": 7, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y54": { + "bits": {}, + "grid_x": 7, + "grid_y": 154, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y55": { + "bits": {}, + "grid_x": 7, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y56": { + "bits": {}, + "grid_x": 7, + "grid_y": 152, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y57": { + "bits": {}, + "grid_x": 7, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y58": { + "bits": {}, + "grid_x": 7, + "grid_y": 150, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y59": { + "bits": {}, + "grid_x": 7, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y6": { + "bits": {}, + "grid_x": 7, + "grid_y": 202, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y61": { + "bits": {}, + "grid_x": 7, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y62": { + "bits": {}, + "grid_x": 7, + "grid_y": 146, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y63": { + "bits": {}, + "grid_x": 7, + "grid_y": 145, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y64": { + "bits": {}, + "grid_x": 7, + "grid_y": 144, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y65": { + "bits": {}, + "grid_x": 7, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y66": { + "bits": {}, + "grid_x": 7, + "grid_y": 142, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y67": { + "bits": {}, + "grid_x": 7, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y68": { + "bits": {}, + "grid_x": 7, + "grid_y": 140, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y69": { + "bits": {}, + "grid_x": 7, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y7": { + "bits": {}, + "grid_x": 7, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y70": { + "bits": {}, + "grid_x": 7, + "grid_y": 138, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y71": { + "bits": {}, + "grid_x": 7, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y73": { + "bits": {}, + "grid_x": 7, + "grid_y": 135, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y74": { + "bits": {}, + "grid_x": 7, + "grid_y": 134, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y75": { + "bits": {}, + "grid_x": 7, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y76": { + "bits": {}, + "grid_x": 7, + "grid_y": 132, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y77": { + "bits": {}, + "grid_x": 7, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y79": { + "bits": {}, + "grid_x": 7, + "grid_y": 129, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y80": { + "bits": {}, + "grid_x": 7, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y81": { + "bits": {}, + "grid_x": 7, + "grid_y": 127, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y82": { + "bits": {}, + "grid_x": 7, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y83": { + "bits": {}, + "grid_x": 7, + "grid_y": 125, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y84": { + "bits": {}, + "grid_x": 7, + "grid_y": 124, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y86": { + "bits": {}, + "grid_x": 7, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y87": { + "bits": {}, + "grid_x": 7, + "grid_y": 121, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y88": { + "bits": {}, + "grid_x": 7, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y89": { + "bits": {}, + "grid_x": 7, + "grid_y": 119, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y9": { + "bits": {}, + "grid_x": 7, + "grid_y": 199, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y90": { + "bits": {}, + "grid_x": 7, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y91": { + "bits": {}, + "grid_x": 7, + "grid_y": 117, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y92": { + "bits": {}, + "grid_x": 7, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y93": { + "bits": {}, + "grid_x": 7, + "grid_y": 115, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y94": { + "bits": {}, + "grid_x": 7, + "grid_y": 114, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y95": { + "bits": {}, + "grid_x": 7, + "grid_y": 113, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y96": { + "bits": {}, + "grid_x": 7, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y98": { + "bits": {}, + "grid_x": 7, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X7Y99": { + "bits": {}, + "grid_x": 7, + "grid_y": 109, + "sites": {}, + "type": "NULL" + }, + "NULL_X81Y0": { + "bits": {}, + "grid_x": 81, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X81Y208": { + "bits": {}, + "grid_x": 81, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X82Y0": { + "bits": {}, + "grid_x": 82, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X82Y104": { + "bits": {}, + "grid_x": 82, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X82Y156": { + "bits": {}, + "grid_x": 82, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X82Y208": { + "bits": {}, + "grid_x": 82, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X82Y52": { + "bits": {}, + "grid_x": 82, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X83Y0": { + "bits": {}, + "grid_x": 83, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X83Y208": { + "bits": {}, + "grid_x": 83, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X86Y0": { + "bits": {}, + "grid_x": 86, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X86Y104": { + "bits": {}, + "grid_x": 86, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X86Y156": { + "bits": {}, + "grid_x": 86, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X86Y208": { + "bits": {}, + "grid_x": 86, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X86Y52": { + "bits": {}, + "grid_x": 86, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y0": { + "bits": {}, + "grid_x": 87, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y10": { + "bits": {}, + "grid_x": 87, + "grid_y": 198, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y100": { + "bits": {}, + "grid_x": 87, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y101": { + "bits": {}, + "grid_x": 87, + "grid_y": 107, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y102": { + "bits": {}, + "grid_x": 87, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y103": { + "bits": {}, + "grid_x": 87, + "grid_y": 105, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y106": { + "bits": {}, + "grid_x": 87, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y107": { + "bits": {}, + "grid_x": 87, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y108": { + "bits": {}, + "grid_x": 87, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y109": { + "bits": {}, + "grid_x": 87, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y111": { + "bits": {}, + "grid_x": 87, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y112": { + "bits": {}, + "grid_x": 87, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y113": { + "bits": {}, + "grid_x": 87, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y114": { + "bits": {}, + "grid_x": 87, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y116": { + "bits": {}, + "grid_x": 87, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y117": { + "bits": {}, + "grid_x": 87, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y118": { + "bits": {}, + "grid_x": 87, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y119": { + "bits": {}, + "grid_x": 87, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y12": { + "bits": {}, + "grid_x": 87, + "grid_y": 196, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y121": { + "bits": {}, + "grid_x": 87, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y122": { + "bits": {}, + "grid_x": 87, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y123": { + "bits": {}, + "grid_x": 87, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y124": { + "bits": {}, + "grid_x": 87, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y126": { + "bits": {}, + "grid_x": 87, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y127": { + "bits": {}, + "grid_x": 87, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y128": { + "bits": {}, + "grid_x": 87, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y129": { + "bits": {}, + "grid_x": 87, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y13": { + "bits": {}, + "grid_x": 87, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y132": { + "bits": {}, + "grid_x": 87, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y133": { + "bits": {}, + "grid_x": 87, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y134": { + "bits": {}, + "grid_x": 87, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y135": { + "bits": {}, + "grid_x": 87, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y137": { + "bits": {}, + "grid_x": 87, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y138": { + "bits": {}, + "grid_x": 87, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y139": { + "bits": {}, + "grid_x": 87, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y14": { + "bits": {}, + "grid_x": 87, + "grid_y": 194, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y140": { + "bits": {}, + "grid_x": 87, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y142": { + "bits": {}, + "grid_x": 87, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y143": { + "bits": {}, + "grid_x": 87, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y144": { + "bits": {}, + "grid_x": 87, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y145": { + "bits": {}, + "grid_x": 87, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y147": { + "bits": {}, + "grid_x": 87, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y148": { + "bits": {}, + "grid_x": 87, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y149": { + "bits": {}, + "grid_x": 87, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y15": { + "bits": {}, + "grid_x": 87, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y150": { + "bits": {}, + "grid_x": 87, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y152": { + "bits": {}, + "grid_x": 87, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y153": { + "bits": {}, + "grid_x": 87, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y154": { + "bits": {}, + "grid_x": 87, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y155": { + "bits": {}, + "grid_x": 87, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y158": { + "bits": {}, + "grid_x": 87, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y159": { + "bits": {}, + "grid_x": 87, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y160": { + "bits": {}, + "grid_x": 87, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y161": { + "bits": {}, + "grid_x": 87, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y163": { + "bits": {}, + "grid_x": 87, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y164": { + "bits": {}, + "grid_x": 87, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y165": { + "bits": {}, + "grid_x": 87, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y166": { + "bits": {}, + "grid_x": 87, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y168": { + "bits": {}, + "grid_x": 87, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y169": { + "bits": {}, + "grid_x": 87, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y17": { + "bits": {}, + "grid_x": 87, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y170": { + "bits": {}, + "grid_x": 87, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y171": { + "bits": {}, + "grid_x": 87, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y173": { + "bits": {}, + "grid_x": 87, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y174": { + "bits": {}, + "grid_x": 87, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y175": { + "bits": {}, + "grid_x": 87, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y176": { + "bits": {}, + "grid_x": 87, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y178": { + "bits": {}, + "grid_x": 87, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y179": { + "bits": {}, + "grid_x": 87, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y18": { + "bits": {}, + "grid_x": 87, + "grid_y": 190, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y180": { + "bits": {}, + "grid_x": 87, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y181": { + "bits": {}, + "grid_x": 87, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y184": { + "bits": {}, + "grid_x": 87, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y185": { + "bits": {}, + "grid_x": 87, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y186": { + "bits": {}, + "grid_x": 87, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y187": { + "bits": {}, + "grid_x": 87, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y189": { + "bits": {}, + "grid_x": 87, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y19": { + "bits": {}, + "grid_x": 87, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y190": { + "bits": {}, + "grid_x": 87, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y191": { + "bits": {}, + "grid_x": 87, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y192": { + "bits": {}, + "grid_x": 87, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y194": { + "bits": {}, + "grid_x": 87, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y195": { + "bits": {}, + "grid_x": 87, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y196": { + "bits": {}, + "grid_x": 87, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y197": { + "bits": {}, + "grid_x": 87, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y199": { + "bits": {}, + "grid_x": 87, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y2": { + "bits": {}, + "grid_x": 87, + "grid_y": 206, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y20": { + "bits": {}, + "grid_x": 87, + "grid_y": 188, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y200": { + "bits": {}, + "grid_x": 87, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y201": { + "bits": {}, + "grid_x": 87, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y202": { + "bits": {}, + "grid_x": 87, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y204": { + "bits": {}, + "grid_x": 87, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y205": { + "bits": {}, + "grid_x": 87, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y206": { + "bits": {}, + "grid_x": 87, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y207": { + "bits": {}, + "grid_x": 87, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y208": { + "bits": {}, + "grid_x": 87, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y22": { + "bits": {}, + "grid_x": 87, + "grid_y": 186, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y23": { + "bits": {}, + "grid_x": 87, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y24": { + "bits": {}, + "grid_x": 87, + "grid_y": 184, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y25": { + "bits": {}, + "grid_x": 87, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y28": { + "bits": {}, + "grid_x": 87, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y29": { + "bits": {}, + "grid_x": 87, + "grid_y": 179, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y3": { + "bits": {}, + "grid_x": 87, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y30": { + "bits": {}, + "grid_x": 87, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y31": { + "bits": {}, + "grid_x": 87, + "grid_y": 177, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y33": { + "bits": {}, + "grid_x": 87, + "grid_y": 175, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y34": { + "bits": {}, + "grid_x": 87, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y35": { + "bits": {}, + "grid_x": 87, + "grid_y": 173, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y36": { + "bits": {}, + "grid_x": 87, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y38": { + "bits": {}, + "grid_x": 87, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y39": { + "bits": {}, + "grid_x": 87, + "grid_y": 169, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y4": { + "bits": {}, + "grid_x": 87, + "grid_y": 204, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y40": { + "bits": {}, + "grid_x": 87, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y41": { + "bits": {}, + "grid_x": 87, + "grid_y": 167, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y43": { + "bits": {}, + "grid_x": 87, + "grid_y": 165, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y44": { + "bits": {}, + "grid_x": 87, + "grid_y": 164, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y45": { + "bits": {}, + "grid_x": 87, + "grid_y": 163, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y46": { + "bits": {}, + "grid_x": 87, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y48": { + "bits": {}, + "grid_x": 87, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y49": { + "bits": {}, + "grid_x": 87, + "grid_y": 159, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y5": { + "bits": {}, + "grid_x": 87, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y50": { + "bits": {}, + "grid_x": 87, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y51": { + "bits": {}, + "grid_x": 87, + "grid_y": 157, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y54": { + "bits": {}, + "grid_x": 87, + "grid_y": 154, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y55": { + "bits": {}, + "grid_x": 87, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y56": { + "bits": {}, + "grid_x": 87, + "grid_y": 152, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y57": { + "bits": {}, + "grid_x": 87, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y59": { + "bits": {}, + "grid_x": 87, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y60": { + "bits": {}, + "grid_x": 87, + "grid_y": 148, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y61": { + "bits": {}, + "grid_x": 87, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y62": { + "bits": {}, + "grid_x": 87, + "grid_y": 146, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y64": { + "bits": {}, + "grid_x": 87, + "grid_y": 144, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y65": { + "bits": {}, + "grid_x": 87, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y66": { + "bits": {}, + "grid_x": 87, + "grid_y": 142, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y67": { + "bits": {}, + "grid_x": 87, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y69": { + "bits": {}, + "grid_x": 87, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y7": { + "bits": {}, + "grid_x": 87, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y70": { + "bits": {}, + "grid_x": 87, + "grid_y": 138, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y71": { + "bits": {}, + "grid_x": 87, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y72": { + "bits": {}, + "grid_x": 87, + "grid_y": 136, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y74": { + "bits": {}, + "grid_x": 87, + "grid_y": 134, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y75": { + "bits": {}, + "grid_x": 87, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y76": { + "bits": {}, + "grid_x": 87, + "grid_y": 132, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y77": { + "bits": {}, + "grid_x": 87, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y8": { + "bits": {}, + "grid_x": 87, + "grid_y": 200, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y80": { + "bits": {}, + "grid_x": 87, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y81": { + "bits": {}, + "grid_x": 87, + "grid_y": 127, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y82": { + "bits": {}, + "grid_x": 87, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y83": { + "bits": {}, + "grid_x": 87, + "grid_y": 125, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y85": { + "bits": {}, + "grid_x": 87, + "grid_y": 123, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y86": { + "bits": {}, + "grid_x": 87, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y87": { + "bits": {}, + "grid_x": 87, + "grid_y": 121, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y88": { + "bits": {}, + "grid_x": 87, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y9": { + "bits": {}, + "grid_x": 87, + "grid_y": 199, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y90": { + "bits": {}, + "grid_x": 87, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y91": { + "bits": {}, + "grid_x": 87, + "grid_y": 117, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y92": { + "bits": {}, + "grid_x": 87, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y93": { + "bits": {}, + "grid_x": 87, + "grid_y": 115, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y95": { + "bits": {}, + "grid_x": 87, + "grid_y": 113, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y96": { + "bits": {}, + "grid_x": 87, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y97": { + "bits": {}, + "grid_x": 87, + "grid_y": 111, + "sites": {}, + "type": "NULL" + }, + "NULL_X87Y98": { + "bits": {}, + "grid_x": 87, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X88Y0": { + "bits": {}, + "grid_x": 88, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X88Y208": { + "bits": {}, + "grid_x": 88, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y1": { + "bits": {}, + "grid_x": 8, + "grid_y": 207, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y10": { + "bits": {}, + "grid_x": 8, + "grid_y": 198, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y100": { + "bits": {}, + "grid_x": 8, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y101": { + "bits": {}, + "grid_x": 8, + "grid_y": 107, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y102": { + "bits": {}, + "grid_x": 8, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y103": { + "bits": {}, + "grid_x": 8, + "grid_y": 105, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y105": { + "bits": {}, + "grid_x": 8, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y106": { + "bits": {}, + "grid_x": 8, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y107": { + "bits": {}, + "grid_x": 8, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y108": { + "bits": {}, + "grid_x": 8, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y109": { + "bits": {}, + "grid_x": 8, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y11": { + "bits": {}, + "grid_x": 8, + "grid_y": 197, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y110": { + "bits": {}, + "grid_x": 8, + "grid_y": 98, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y111": { + "bits": {}, + "grid_x": 8, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y112": { + "bits": {}, + "grid_x": 8, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y114": { + "bits": {}, + "grid_x": 8, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y115": { + "bits": {}, + "grid_x": 8, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y116": { + "bits": {}, + "grid_x": 8, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y117": { + "bits": {}, + "grid_x": 8, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y118": { + "bits": {}, + "grid_x": 8, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y119": { + "bits": {}, + "grid_x": 8, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y12": { + "bits": {}, + "grid_x": 8, + "grid_y": 196, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y120": { + "bits": {}, + "grid_x": 8, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y121": { + "bits": {}, + "grid_x": 8, + "grid_y": 87, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y123": { + "bits": {}, + "grid_x": 8, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y124": { + "bits": {}, + "grid_x": 8, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y125": { + "bits": {}, + "grid_x": 8, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y126": { + "bits": {}, + "grid_x": 8, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y127": { + "bits": {}, + "grid_x": 8, + "grid_y": 81, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y128": { + "bits": {}, + "grid_x": 8, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y129": { + "bits": {}, + "grid_x": 8, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y13": { + "bits": {}, + "grid_x": 8, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y131": { + "bits": {}, + "grid_x": 8, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y132": { + "bits": {}, + "grid_x": 8, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y133": { + "bits": {}, + "grid_x": 8, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y134": { + "bits": {}, + "grid_x": 8, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y136": { + "bits": {}, + "grid_x": 8, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y137": { + "bits": {}, + "grid_x": 8, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y138": { + "bits": {}, + "grid_x": 8, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y139": { + "bits": {}, + "grid_x": 8, + "grid_y": 69, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y14": { + "bits": {}, + "grid_x": 8, + "grid_y": 194, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y140": { + "bits": {}, + "grid_x": 8, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y141": { + "bits": {}, + "grid_x": 8, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y142": { + "bits": {}, + "grid_x": 8, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y143": { + "bits": {}, + "grid_x": 8, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y144": { + "bits": {}, + "grid_x": 8, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y145": { + "bits": {}, + "grid_x": 8, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y146": { + "bits": {}, + "grid_x": 8, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y147": { + "bits": {}, + "grid_x": 8, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y149": { + "bits": {}, + "grid_x": 8, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y15": { + "bits": {}, + "grid_x": 8, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y150": { + "bits": {}, + "grid_x": 8, + "grid_y": 58, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y151": { + "bits": {}, + "grid_x": 8, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y152": { + "bits": {}, + "grid_x": 8, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y153": { + "bits": {}, + "grid_x": 8, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y154": { + "bits": {}, + "grid_x": 8, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y155": { + "bits": {}, + "grid_x": 8, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y157": { + "bits": {}, + "grid_x": 8, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y158": { + "bits": {}, + "grid_x": 8, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y159": { + "bits": {}, + "grid_x": 8, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y16": { + "bits": {}, + "grid_x": 8, + "grid_y": 192, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y160": { + "bits": {}, + "grid_x": 8, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y161": { + "bits": {}, + "grid_x": 8, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y162": { + "bits": {}, + "grid_x": 8, + "grid_y": 46, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y163": { + "bits": {}, + "grid_x": 8, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y164": { + "bits": {}, + "grid_x": 8, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y166": { + "bits": {}, + "grid_x": 8, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y167": { + "bits": {}, + "grid_x": 8, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y168": { + "bits": {}, + "grid_x": 8, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y169": { + "bits": {}, + "grid_x": 8, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y17": { + "bits": {}, + "grid_x": 8, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y170": { + "bits": {}, + "grid_x": 8, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y171": { + "bits": {}, + "grid_x": 8, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y172": { + "bits": {}, + "grid_x": 8, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y173": { + "bits": {}, + "grid_x": 8, + "grid_y": 35, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y175": { + "bits": {}, + "grid_x": 8, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y176": { + "bits": {}, + "grid_x": 8, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y177": { + "bits": {}, + "grid_x": 8, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y178": { + "bits": {}, + "grid_x": 8, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y179": { + "bits": {}, + "grid_x": 8, + "grid_y": 29, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y180": { + "bits": {}, + "grid_x": 8, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y181": { + "bits": {}, + "grid_x": 8, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y183": { + "bits": {}, + "grid_x": 8, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y184": { + "bits": {}, + "grid_x": 8, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y185": { + "bits": {}, + "grid_x": 8, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y186": { + "bits": {}, + "grid_x": 8, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y188": { + "bits": {}, + "grid_x": 8, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y189": { + "bits": {}, + "grid_x": 8, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y19": { + "bits": {}, + "grid_x": 8, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y190": { + "bits": {}, + "grid_x": 8, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y191": { + "bits": {}, + "grid_x": 8, + "grid_y": 17, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y192": { + "bits": {}, + "grid_x": 8, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y193": { + "bits": {}, + "grid_x": 8, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y194": { + "bits": {}, + "grid_x": 8, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y195": { + "bits": {}, + "grid_x": 8, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y196": { + "bits": {}, + "grid_x": 8, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y197": { + "bits": {}, + "grid_x": 8, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y198": { + "bits": {}, + "grid_x": 8, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y199": { + "bits": {}, + "grid_x": 8, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y2": { + "bits": {}, + "grid_x": 8, + "grid_y": 206, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y20": { + "bits": {}, + "grid_x": 8, + "grid_y": 188, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y201": { + "bits": {}, + "grid_x": 8, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y202": { + "bits": {}, + "grid_x": 8, + "grid_y": 6, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y203": { + "bits": {}, + "grid_x": 8, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y204": { + "bits": {}, + "grid_x": 8, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y205": { + "bits": {}, + "grid_x": 8, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y206": { + "bits": {}, + "grid_x": 8, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y207": { + "bits": {}, + "grid_x": 8, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y21": { + "bits": {}, + "grid_x": 8, + "grid_y": 187, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y22": { + "bits": {}, + "grid_x": 8, + "grid_y": 186, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y23": { + "bits": {}, + "grid_x": 8, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y24": { + "bits": {}, + "grid_x": 8, + "grid_y": 184, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y25": { + "bits": {}, + "grid_x": 8, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y27": { + "bits": {}, + "grid_x": 8, + "grid_y": 181, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y28": { + "bits": {}, + "grid_x": 8, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y29": { + "bits": {}, + "grid_x": 8, + "grid_y": 179, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y3": { + "bits": {}, + "grid_x": 8, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y30": { + "bits": {}, + "grid_x": 8, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y32": { + "bits": {}, + "grid_x": 8, + "grid_y": 176, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y33": { + "bits": {}, + "grid_x": 8, + "grid_y": 175, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y34": { + "bits": {}, + "grid_x": 8, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y35": { + "bits": {}, + "grid_x": 8, + "grid_y": 173, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y36": { + "bits": {}, + "grid_x": 8, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y37": { + "bits": {}, + "grid_x": 8, + "grid_y": 171, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y38": { + "bits": {}, + "grid_x": 8, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y39": { + "bits": {}, + "grid_x": 8, + "grid_y": 169, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y4": { + "bits": {}, + "grid_x": 8, + "grid_y": 204, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y40": { + "bits": {}, + "grid_x": 8, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y41": { + "bits": {}, + "grid_x": 8, + "grid_y": 167, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y42": { + "bits": {}, + "grid_x": 8, + "grid_y": 166, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y43": { + "bits": {}, + "grid_x": 8, + "grid_y": 165, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y45": { + "bits": {}, + "grid_x": 8, + "grid_y": 163, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y46": { + "bits": {}, + "grid_x": 8, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y47": { + "bits": {}, + "grid_x": 8, + "grid_y": 161, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y48": { + "bits": {}, + "grid_x": 8, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y49": { + "bits": {}, + "grid_x": 8, + "grid_y": 159, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y5": { + "bits": {}, + "grid_x": 8, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y50": { + "bits": {}, + "grid_x": 8, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y51": { + "bits": {}, + "grid_x": 8, + "grid_y": 157, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y53": { + "bits": {}, + "grid_x": 8, + "grid_y": 155, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y54": { + "bits": {}, + "grid_x": 8, + "grid_y": 154, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y55": { + "bits": {}, + "grid_x": 8, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y56": { + "bits": {}, + "grid_x": 8, + "grid_y": 152, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y57": { + "bits": {}, + "grid_x": 8, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y58": { + "bits": {}, + "grid_x": 8, + "grid_y": 150, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y59": { + "bits": {}, + "grid_x": 8, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y6": { + "bits": {}, + "grid_x": 8, + "grid_y": 202, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y60": { + "bits": {}, + "grid_x": 8, + "grid_y": 148, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y62": { + "bits": {}, + "grid_x": 8, + "grid_y": 146, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y63": { + "bits": {}, + "grid_x": 8, + "grid_y": 145, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y64": { + "bits": {}, + "grid_x": 8, + "grid_y": 144, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y65": { + "bits": {}, + "grid_x": 8, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y66": { + "bits": {}, + "grid_x": 8, + "grid_y": 142, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y67": { + "bits": {}, + "grid_x": 8, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y68": { + "bits": {}, + "grid_x": 8, + "grid_y": 140, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y69": { + "bits": {}, + "grid_x": 8, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y7": { + "bits": {}, + "grid_x": 8, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y71": { + "bits": {}, + "grid_x": 8, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y72": { + "bits": {}, + "grid_x": 8, + "grid_y": 136, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y73": { + "bits": {}, + "grid_x": 8, + "grid_y": 135, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y74": { + "bits": {}, + "grid_x": 8, + "grid_y": 134, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y75": { + "bits": {}, + "grid_x": 8, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y76": { + "bits": {}, + "grid_x": 8, + "grid_y": 132, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y77": { + "bits": {}, + "grid_x": 8, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y79": { + "bits": {}, + "grid_x": 8, + "grid_y": 129, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y8": { + "bits": {}, + "grid_x": 8, + "grid_y": 200, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y80": { + "bits": {}, + "grid_x": 8, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y81": { + "bits": {}, + "grid_x": 8, + "grid_y": 127, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y82": { + "bits": {}, + "grid_x": 8, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y84": { + "bits": {}, + "grid_x": 8, + "grid_y": 124, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y85": { + "bits": {}, + "grid_x": 8, + "grid_y": 123, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y86": { + "bits": {}, + "grid_x": 8, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y87": { + "bits": {}, + "grid_x": 8, + "grid_y": 121, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y88": { + "bits": {}, + "grid_x": 8, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y89": { + "bits": {}, + "grid_x": 8, + "grid_y": 119, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y90": { + "bits": {}, + "grid_x": 8, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y91": { + "bits": {}, + "grid_x": 8, + "grid_y": 117, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y92": { + "bits": {}, + "grid_x": 8, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y93": { + "bits": {}, + "grid_x": 8, + "grid_y": 115, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y94": { + "bits": {}, + "grid_x": 8, + "grid_y": 114, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y95": { + "bits": {}, + "grid_x": 8, + "grid_y": 113, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y97": { + "bits": {}, + "grid_x": 8, + "grid_y": 111, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y98": { + "bits": {}, + "grid_x": 8, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X8Y99": { + "bits": {}, + "grid_x": 8, + "grid_y": 109, + "sites": {}, + "type": "NULL" + }, + "NULL_X91Y0": { + "bits": {}, + "grid_x": 91, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X91Y208": { + "bits": {}, + "grid_x": 91, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X92Y0": { + "bits": {}, + "grid_x": 92, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X92Y104": { + "bits": {}, + "grid_x": 92, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X92Y156": { + "bits": {}, + "grid_x": 92, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X92Y208": { + "bits": {}, + "grid_x": 92, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X92Y52": { + "bits": {}, + "grid_x": 92, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X93Y0": { + "bits": {}, + "grid_x": 93, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X93Y208": { + "bits": {}, + "grid_x": 93, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X96Y0": { + "bits": {}, + "grid_x": 96, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X96Y104": { + "bits": {}, + "grid_x": 96, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X96Y156": { + "bits": {}, + "grid_x": 96, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X96Y208": { + "bits": {}, + "grid_x": 96, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X96Y52": { + "bits": {}, + "grid_x": 96, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y0": { + "bits": {}, + "grid_x": 97, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y10": { + "bits": {}, + "grid_x": 97, + "grid_y": 198, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y100": { + "bits": {}, + "grid_x": 97, + "grid_y": 108, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y101": { + "bits": {}, + "grid_x": 97, + "grid_y": 107, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y102": { + "bits": {}, + "grid_x": 97, + "grid_y": 106, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y103": { + "bits": {}, + "grid_x": 97, + "grid_y": 105, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y104": { + "bits": {}, + "grid_x": 97, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y12": { + "bits": {}, + "grid_x": 97, + "grid_y": 196, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y13": { + "bits": {}, + "grid_x": 97, + "grid_y": 195, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y14": { + "bits": {}, + "grid_x": 97, + "grid_y": 194, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y15": { + "bits": {}, + "grid_x": 97, + "grid_y": 193, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y156": { + "bits": {}, + "grid_x": 97, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y17": { + "bits": {}, + "grid_x": 97, + "grid_y": 191, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y18": { + "bits": {}, + "grid_x": 97, + "grid_y": 190, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y19": { + "bits": {}, + "grid_x": 97, + "grid_y": 189, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y2": { + "bits": {}, + "grid_x": 97, + "grid_y": 206, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y20": { + "bits": {}, + "grid_x": 97, + "grid_y": 188, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y208": { + "bits": {}, + "grid_x": 97, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y22": { + "bits": {}, + "grid_x": 97, + "grid_y": 186, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y23": { + "bits": {}, + "grid_x": 97, + "grid_y": 185, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y24": { + "bits": {}, + "grid_x": 97, + "grid_y": 184, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y25": { + "bits": {}, + "grid_x": 97, + "grid_y": 183, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y28": { + "bits": {}, + "grid_x": 97, + "grid_y": 180, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y29": { + "bits": {}, + "grid_x": 97, + "grid_y": 179, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y3": { + "bits": {}, + "grid_x": 97, + "grid_y": 205, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y30": { + "bits": {}, + "grid_x": 97, + "grid_y": 178, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y31": { + "bits": {}, + "grid_x": 97, + "grid_y": 177, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y33": { + "bits": {}, + "grid_x": 97, + "grid_y": 175, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y34": { + "bits": {}, + "grid_x": 97, + "grid_y": 174, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y35": { + "bits": {}, + "grid_x": 97, + "grid_y": 173, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y36": { + "bits": {}, + "grid_x": 97, + "grid_y": 172, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y38": { + "bits": {}, + "grid_x": 97, + "grid_y": 170, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y39": { + "bits": {}, + "grid_x": 97, + "grid_y": 169, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y4": { + "bits": {}, + "grid_x": 97, + "grid_y": 204, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y40": { + "bits": {}, + "grid_x": 97, + "grid_y": 168, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y41": { + "bits": {}, + "grid_x": 97, + "grid_y": 167, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y43": { + "bits": {}, + "grid_x": 97, + "grid_y": 165, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y44": { + "bits": {}, + "grid_x": 97, + "grid_y": 164, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y45": { + "bits": {}, + "grid_x": 97, + "grid_y": 163, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y46": { + "bits": {}, + "grid_x": 97, + "grid_y": 162, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y48": { + "bits": {}, + "grid_x": 97, + "grid_y": 160, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y49": { + "bits": {}, + "grid_x": 97, + "grid_y": 159, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y5": { + "bits": {}, + "grid_x": 97, + "grid_y": 203, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y50": { + "bits": {}, + "grid_x": 97, + "grid_y": 158, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y51": { + "bits": {}, + "grid_x": 97, + "grid_y": 157, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y54": { + "bits": {}, + "grid_x": 97, + "grid_y": 154, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y55": { + "bits": {}, + "grid_x": 97, + "grid_y": 153, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y56": { + "bits": {}, + "grid_x": 97, + "grid_y": 152, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y57": { + "bits": {}, + "grid_x": 97, + "grid_y": 151, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y59": { + "bits": {}, + "grid_x": 97, + "grid_y": 149, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y60": { + "bits": {}, + "grid_x": 97, + "grid_y": 148, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y61": { + "bits": {}, + "grid_x": 97, + "grid_y": 147, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y62": { + "bits": {}, + "grid_x": 97, + "grid_y": 146, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y64": { + "bits": {}, + "grid_x": 97, + "grid_y": 144, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y65": { + "bits": {}, + "grid_x": 97, + "grid_y": 143, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y66": { + "bits": {}, + "grid_x": 97, + "grid_y": 142, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y67": { + "bits": {}, + "grid_x": 97, + "grid_y": 141, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y69": { + "bits": {}, + "grid_x": 97, + "grid_y": 139, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y7": { + "bits": {}, + "grid_x": 97, + "grid_y": 201, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y70": { + "bits": {}, + "grid_x": 97, + "grid_y": 138, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y71": { + "bits": {}, + "grid_x": 97, + "grid_y": 137, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y72": { + "bits": {}, + "grid_x": 97, + "grid_y": 136, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y74": { + "bits": {}, + "grid_x": 97, + "grid_y": 134, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y75": { + "bits": {}, + "grid_x": 97, + "grid_y": 133, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y76": { + "bits": {}, + "grid_x": 97, + "grid_y": 132, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y77": { + "bits": {}, + "grid_x": 97, + "grid_y": 131, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y8": { + "bits": {}, + "grid_x": 97, + "grid_y": 200, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y80": { + "bits": {}, + "grid_x": 97, + "grid_y": 128, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y81": { + "bits": {}, + "grid_x": 97, + "grid_y": 127, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y82": { + "bits": {}, + "grid_x": 97, + "grid_y": 126, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y83": { + "bits": {}, + "grid_x": 97, + "grid_y": 125, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y85": { + "bits": {}, + "grid_x": 97, + "grid_y": 123, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y86": { + "bits": {}, + "grid_x": 97, + "grid_y": 122, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y87": { + "bits": {}, + "grid_x": 97, + "grid_y": 121, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y88": { + "bits": {}, + "grid_x": 97, + "grid_y": 120, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y9": { + "bits": {}, + "grid_x": 97, + "grid_y": 199, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y90": { + "bits": {}, + "grid_x": 97, + "grid_y": 118, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y91": { + "bits": {}, + "grid_x": 97, + "grid_y": 117, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y92": { + "bits": {}, + "grid_x": 97, + "grid_y": 116, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y93": { + "bits": {}, + "grid_x": 97, + "grid_y": 115, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y95": { + "bits": {}, + "grid_x": 97, + "grid_y": 113, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y96": { + "bits": {}, + "grid_x": 97, + "grid_y": 112, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y97": { + "bits": {}, + "grid_x": 97, + "grid_y": 111, + "sites": {}, + "type": "NULL" + }, + "NULL_X97Y98": { + "bits": {}, + "grid_x": 97, + "grid_y": 110, + "sites": {}, + "type": "NULL" + }, + "NULL_X98Y0": { + "bits": {}, + "grid_x": 98, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X98Y104": { + "bits": {}, + "grid_x": 98, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X98Y156": { + "bits": {}, + "grid_x": 98, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X98Y208": { + "bits": {}, + "grid_x": 98, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X98Y52": { + "bits": {}, + "grid_x": 98, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y0": { + "bits": {}, + "grid_x": 99, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y105": { + "bits": {}, + "grid_x": 99, + "grid_y": 103, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y106": { + "bits": {}, + "grid_x": 99, + "grid_y": 102, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y107": { + "bits": {}, + "grid_x": 99, + "grid_y": 101, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y108": { + "bits": {}, + "grid_x": 99, + "grid_y": 100, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y109": { + "bits": {}, + "grid_x": 99, + "grid_y": 99, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y111": { + "bits": {}, + "grid_x": 99, + "grid_y": 97, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y112": { + "bits": {}, + "grid_x": 99, + "grid_y": 96, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y113": { + "bits": {}, + "grid_x": 99, + "grid_y": 95, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y114": { + "bits": {}, + "grid_x": 99, + "grid_y": 94, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y115": { + "bits": {}, + "grid_x": 99, + "grid_y": 93, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y116": { + "bits": {}, + "grid_x": 99, + "grid_y": 92, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y117": { + "bits": {}, + "grid_x": 99, + "grid_y": 91, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y118": { + "bits": {}, + "grid_x": 99, + "grid_y": 90, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y119": { + "bits": {}, + "grid_x": 99, + "grid_y": 89, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y120": { + "bits": {}, + "grid_x": 99, + "grid_y": 88, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y122": { + "bits": {}, + "grid_x": 99, + "grid_y": 86, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y123": { + "bits": {}, + "grid_x": 99, + "grid_y": 85, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y124": { + "bits": {}, + "grid_x": 99, + "grid_y": 84, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y125": { + "bits": {}, + "grid_x": 99, + "grid_y": 83, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y126": { + "bits": {}, + "grid_x": 99, + "grid_y": 82, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y128": { + "bits": {}, + "grid_x": 99, + "grid_y": 80, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y129": { + "bits": {}, + "grid_x": 99, + "grid_y": 79, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y130": { + "bits": {}, + "grid_x": 99, + "grid_y": 78, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y131": { + "bits": {}, + "grid_x": 99, + "grid_y": 77, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y132": { + "bits": {}, + "grid_x": 99, + "grid_y": 76, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y133": { + "bits": {}, + "grid_x": 99, + "grid_y": 75, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y134": { + "bits": {}, + "grid_x": 99, + "grid_y": 74, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y135": { + "bits": {}, + "grid_x": 99, + "grid_y": 73, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y136": { + "bits": {}, + "grid_x": 99, + "grid_y": 72, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y137": { + "bits": {}, + "grid_x": 99, + "grid_y": 71, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y138": { + "bits": {}, + "grid_x": 99, + "grid_y": 70, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y140": { + "bits": {}, + "grid_x": 99, + "grid_y": 68, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y141": { + "bits": {}, + "grid_x": 99, + "grid_y": 67, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y142": { + "bits": {}, + "grid_x": 99, + "grid_y": 66, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y143": { + "bits": {}, + "grid_x": 99, + "grid_y": 65, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y144": { + "bits": {}, + "grid_x": 99, + "grid_y": 64, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y145": { + "bits": {}, + "grid_x": 99, + "grid_y": 63, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y146": { + "bits": {}, + "grid_x": 99, + "grid_y": 62, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y147": { + "bits": {}, + "grid_x": 99, + "grid_y": 61, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y148": { + "bits": {}, + "grid_x": 99, + "grid_y": 60, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y149": { + "bits": {}, + "grid_x": 99, + "grid_y": 59, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y151": { + "bits": {}, + "grid_x": 99, + "grid_y": 57, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y152": { + "bits": {}, + "grid_x": 99, + "grid_y": 56, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y153": { + "bits": {}, + "grid_x": 99, + "grid_y": 55, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y154": { + "bits": {}, + "grid_x": 99, + "grid_y": 54, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y155": { + "bits": {}, + "grid_x": 99, + "grid_y": 53, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y157": { + "bits": {}, + "grid_x": 99, + "grid_y": 51, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y158": { + "bits": {}, + "grid_x": 99, + "grid_y": 50, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y159": { + "bits": {}, + "grid_x": 99, + "grid_y": 49, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y160": { + "bits": {}, + "grid_x": 99, + "grid_y": 48, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y161": { + "bits": {}, + "grid_x": 99, + "grid_y": 47, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y163": { + "bits": {}, + "grid_x": 99, + "grid_y": 45, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y164": { + "bits": {}, + "grid_x": 99, + "grid_y": 44, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y165": { + "bits": {}, + "grid_x": 99, + "grid_y": 43, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y166": { + "bits": {}, + "grid_x": 99, + "grid_y": 42, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y167": { + "bits": {}, + "grid_x": 99, + "grid_y": 41, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y168": { + "bits": {}, + "grid_x": 99, + "grid_y": 40, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y169": { + "bits": {}, + "grid_x": 99, + "grid_y": 39, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y170": { + "bits": {}, + "grid_x": 99, + "grid_y": 38, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y171": { + "bits": {}, + "grid_x": 99, + "grid_y": 37, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y172": { + "bits": {}, + "grid_x": 99, + "grid_y": 36, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y174": { + "bits": {}, + "grid_x": 99, + "grid_y": 34, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y175": { + "bits": {}, + "grid_x": 99, + "grid_y": 33, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y176": { + "bits": {}, + "grid_x": 99, + "grid_y": 32, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y177": { + "bits": {}, + "grid_x": 99, + "grid_y": 31, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y178": { + "bits": {}, + "grid_x": 99, + "grid_y": 30, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y180": { + "bits": {}, + "grid_x": 99, + "grid_y": 28, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y181": { + "bits": {}, + "grid_x": 99, + "grid_y": 27, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y182": { + "bits": {}, + "grid_x": 99, + "grid_y": 26, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y183": { + "bits": {}, + "grid_x": 99, + "grid_y": 25, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y184": { + "bits": {}, + "grid_x": 99, + "grid_y": 24, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y185": { + "bits": {}, + "grid_x": 99, + "grid_y": 23, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y186": { + "bits": {}, + "grid_x": 99, + "grid_y": 22, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y187": { + "bits": {}, + "grid_x": 99, + "grid_y": 21, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y188": { + "bits": {}, + "grid_x": 99, + "grid_y": 20, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y189": { + "bits": {}, + "grid_x": 99, + "grid_y": 19, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y190": { + "bits": {}, + "grid_x": 99, + "grid_y": 18, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y192": { + "bits": {}, + "grid_x": 99, + "grid_y": 16, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y193": { + "bits": {}, + "grid_x": 99, + "grid_y": 15, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y194": { + "bits": {}, + "grid_x": 99, + "grid_y": 14, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y195": { + "bits": {}, + "grid_x": 99, + "grid_y": 13, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y196": { + "bits": {}, + "grid_x": 99, + "grid_y": 12, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y197": { + "bits": {}, + "grid_x": 99, + "grid_y": 11, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y198": { + "bits": {}, + "grid_x": 99, + "grid_y": 10, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y199": { + "bits": {}, + "grid_x": 99, + "grid_y": 9, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y200": { + "bits": {}, + "grid_x": 99, + "grid_y": 8, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y201": { + "bits": {}, + "grid_x": 99, + "grid_y": 7, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y203": { + "bits": {}, + "grid_x": 99, + "grid_y": 5, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y204": { + "bits": {}, + "grid_x": 99, + "grid_y": 4, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y205": { + "bits": {}, + "grid_x": 99, + "grid_y": 3, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y206": { + "bits": {}, + "grid_x": 99, + "grid_y": 2, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y207": { + "bits": {}, + "grid_x": 99, + "grid_y": 1, + "sites": {}, + "type": "NULL" + }, + "NULL_X99Y208": { + "bits": {}, + "grid_x": 99, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X9Y0": { + "bits": {}, + "grid_x": 9, + "grid_y": 208, + "sites": {}, + "type": "NULL" + }, + "NULL_X9Y104": { + "bits": {}, + "grid_x": 9, + "grid_y": 104, + "sites": {}, + "type": "NULL" + }, + "NULL_X9Y156": { + "bits": {}, + "grid_x": 9, + "grid_y": 52, + "sites": {}, + "type": "NULL" + }, + "NULL_X9Y208": { + "bits": {}, + "grid_x": 9, + "grid_y": 0, + "sites": {}, + "type": "NULL" + }, + "NULL_X9Y52": { + "bits": {}, + "grid_x": 9, + "grid_y": 156, + "sites": {}, + "type": "NULL" + }, + "PCIE_BOT_X73Y115": { + "bits": {}, + "grid_x": 73, + "grid_y": 93, + "sites": { + "PCIE_X0Y0": "PCIE_2_1" + }, + "type": "PCIE_BOT" + }, + "PCIE_INT_INTERFACE_L_X30Y100": { + "bits": {}, + "grid_x": 78, + "grid_y": 103, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y101": { + "bits": {}, + "grid_x": 78, + "grid_y": 102, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y102": { + "bits": {}, + "grid_x": 78, + "grid_y": 101, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y103": { + "bits": {}, + "grid_x": 78, + "grid_y": 100, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y104": { + "bits": {}, + "grid_x": 78, + "grid_y": 99, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y105": { + "bits": {}, + "grid_x": 78, + "grid_y": 98, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y106": { + "bits": {}, + "grid_x": 78, + "grid_y": 97, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y107": { + "bits": {}, + "grid_x": 78, + "grid_y": 96, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y108": { + "bits": {}, + "grid_x": 78, + "grid_y": 95, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y109": { + "bits": {}, + "grid_x": 78, + "grid_y": 94, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y110": { + "bits": {}, + "grid_x": 78, + "grid_y": 93, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y111": { + "bits": {}, + "grid_x": 78, + "grid_y": 92, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y112": { + "bits": {}, + "grid_x": 78, + "grid_y": 91, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y113": { + "bits": {}, + "grid_x": 78, + "grid_y": 90, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y114": { + "bits": {}, + "grid_x": 78, + "grid_y": 89, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y115": { + "bits": {}, + "grid_x": 78, + "grid_y": 88, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y116": { + "bits": {}, + "grid_x": 78, + "grid_y": 87, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y117": { + "bits": {}, + "grid_x": 78, + "grid_y": 86, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y118": { + "bits": {}, + "grid_x": 78, + "grid_y": 85, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y119": { + "bits": {}, + "grid_x": 78, + "grid_y": 84, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y120": { + "bits": {}, + "grid_x": 78, + "grid_y": 83, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y121": { + "bits": {}, + "grid_x": 78, + "grid_y": 82, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y122": { + "bits": {}, + "grid_x": 78, + "grid_y": 81, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y123": { + "bits": {}, + "grid_x": 78, + "grid_y": 80, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_L_X30Y124": { + "bits": {}, + "grid_x": 78, + "grid_y": 79, + "sites": {}, + "type": "PCIE_INT_INTERFACE_L" + }, + "PCIE_INT_INTERFACE_R_X27Y100": { + "bits": {}, + "grid_x": 72, + "grid_y": 103, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y101": { + "bits": {}, + "grid_x": 72, + "grid_y": 102, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y102": { + "bits": {}, + "grid_x": 72, + "grid_y": 101, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y103": { + "bits": {}, + "grid_x": 72, + "grid_y": 100, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y104": { + "bits": {}, + "grid_x": 72, + "grid_y": 99, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y105": { + "bits": {}, + "grid_x": 72, + "grid_y": 98, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y106": { + "bits": {}, + "grid_x": 72, + "grid_y": 97, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y107": { + "bits": {}, + "grid_x": 72, + "grid_y": 96, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y108": { + "bits": {}, + "grid_x": 72, + "grid_y": 95, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y109": { + "bits": {}, + "grid_x": 72, + "grid_y": 94, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y110": { + "bits": {}, + "grid_x": 72, + "grid_y": 93, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y111": { + "bits": {}, + "grid_x": 72, + "grid_y": 92, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y112": { + "bits": {}, + "grid_x": 72, + "grid_y": 91, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y113": { + "bits": {}, + "grid_x": 72, + "grid_y": 90, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y114": { + "bits": {}, + "grid_x": 72, + "grid_y": 89, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y115": { + "bits": {}, + "grid_x": 72, + "grid_y": 88, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y116": { + "bits": {}, + "grid_x": 72, + "grid_y": 87, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y117": { + "bits": {}, + "grid_x": 72, + "grid_y": 86, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y118": { + "bits": {}, + "grid_x": 72, + "grid_y": 85, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y119": { + "bits": {}, + "grid_x": 72, + "grid_y": 84, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y120": { + "bits": {}, + "grid_x": 72, + "grid_y": 83, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y121": { + "bits": {}, + "grid_x": 72, + "grid_y": 82, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y122": { + "bits": {}, + "grid_x": 72, + "grid_y": 81, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y123": { + "bits": {}, + "grid_x": 72, + "grid_y": 80, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_INT_INTERFACE_R_X27Y124": { + "bits": {}, + "grid_x": 72, + "grid_y": 79, + "sites": {}, + "type": "PCIE_INT_INTERFACE_R" + }, + "PCIE_NULL_X73Y105": { + "bits": {}, + "grid_x": 73, + "grid_y": 103, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y106": { + "bits": {}, + "grid_x": 73, + "grid_y": 102, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y107": { + "bits": {}, + "grid_x": 73, + "grid_y": 101, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y108": { + "bits": {}, + "grid_x": 73, + "grid_y": 100, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y109": { + "bits": {}, + "grid_x": 73, + "grid_y": 99, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y110": { + "bits": {}, + "grid_x": 73, + "grid_y": 98, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y111": { + "bits": {}, + "grid_x": 73, + "grid_y": 97, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y112": { + "bits": {}, + "grid_x": 73, + "grid_y": 96, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y113": { + "bits": {}, + "grid_x": 73, + "grid_y": 95, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y114": { + "bits": {}, + "grid_x": 73, + "grid_y": 94, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y116": { + "bits": {}, + "grid_x": 73, + "grid_y": 92, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y117": { + "bits": {}, + "grid_x": 73, + "grid_y": 91, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y118": { + "bits": {}, + "grid_x": 73, + "grid_y": 90, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y119": { + "bits": {}, + "grid_x": 73, + "grid_y": 89, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y120": { + "bits": {}, + "grid_x": 73, + "grid_y": 88, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y121": { + "bits": {}, + "grid_x": 73, + "grid_y": 87, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y122": { + "bits": {}, + "grid_x": 73, + "grid_y": 86, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y123": { + "bits": {}, + "grid_x": 73, + "grid_y": 85, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y124": { + "bits": {}, + "grid_x": 73, + "grid_y": 84, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y126": { + "bits": {}, + "grid_x": 73, + "grid_y": 82, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y127": { + "bits": {}, + "grid_x": 73, + "grid_y": 81, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y128": { + "bits": {}, + "grid_x": 73, + "grid_y": 80, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X73Y129": { + "bits": {}, + "grid_x": 73, + "grid_y": 79, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y105": { + "bits": {}, + "grid_x": 74, + "grid_y": 103, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y106": { + "bits": {}, + "grid_x": 74, + "grid_y": 102, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y107": { + "bits": {}, + "grid_x": 74, + "grid_y": 101, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y108": { + "bits": {}, + "grid_x": 74, + "grid_y": 100, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y109": { + "bits": {}, + "grid_x": 74, + "grid_y": 99, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y110": { + "bits": {}, + "grid_x": 74, + "grid_y": 98, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y111": { + "bits": {}, + "grid_x": 74, + "grid_y": 97, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y112": { + "bits": {}, + "grid_x": 74, + "grid_y": 96, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y113": { + "bits": {}, + "grid_x": 74, + "grid_y": 95, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y114": { + "bits": {}, + "grid_x": 74, + "grid_y": 94, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y115": { + "bits": {}, + "grid_x": 74, + "grid_y": 93, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y116": { + "bits": {}, + "grid_x": 74, + "grid_y": 92, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y117": { + "bits": {}, + "grid_x": 74, + "grid_y": 91, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y118": { + "bits": {}, + "grid_x": 74, + "grid_y": 90, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y119": { + "bits": {}, + "grid_x": 74, + "grid_y": 89, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y120": { + "bits": {}, + "grid_x": 74, + "grid_y": 88, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y121": { + "bits": {}, + "grid_x": 74, + "grid_y": 87, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y122": { + "bits": {}, + "grid_x": 74, + "grid_y": 86, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y123": { + "bits": {}, + "grid_x": 74, + "grid_y": 85, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y124": { + "bits": {}, + "grid_x": 74, + "grid_y": 84, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y125": { + "bits": {}, + "grid_x": 74, + "grid_y": 83, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y126": { + "bits": {}, + "grid_x": 74, + "grid_y": 82, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y127": { + "bits": {}, + "grid_x": 74, + "grid_y": 81, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y128": { + "bits": {}, + "grid_x": 74, + "grid_y": 80, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X74Y129": { + "bits": {}, + "grid_x": 74, + "grid_y": 79, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y105": { + "bits": {}, + "grid_x": 75, + "grid_y": 103, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y106": { + "bits": {}, + "grid_x": 75, + "grid_y": 102, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y107": { + "bits": {}, + "grid_x": 75, + "grid_y": 101, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y108": { + "bits": {}, + "grid_x": 75, + "grid_y": 100, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y109": { + "bits": {}, + "grid_x": 75, + "grid_y": 99, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y110": { + "bits": {}, + "grid_x": 75, + "grid_y": 98, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y111": { + "bits": {}, + "grid_x": 75, + "grid_y": 97, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y112": { + "bits": {}, + "grid_x": 75, + "grid_y": 96, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y113": { + "bits": {}, + "grid_x": 75, + "grid_y": 95, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y114": { + "bits": {}, + "grid_x": 75, + "grid_y": 94, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y115": { + "bits": {}, + "grid_x": 75, + "grid_y": 93, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y116": { + "bits": {}, + "grid_x": 75, + "grid_y": 92, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y117": { + "bits": {}, + "grid_x": 75, + "grid_y": 91, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y118": { + "bits": {}, + "grid_x": 75, + "grid_y": 90, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y119": { + "bits": {}, + "grid_x": 75, + "grid_y": 89, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y120": { + "bits": {}, + "grid_x": 75, + "grid_y": 88, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y121": { + "bits": {}, + "grid_x": 75, + "grid_y": 87, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y122": { + "bits": {}, + "grid_x": 75, + "grid_y": 86, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y123": { + "bits": {}, + "grid_x": 75, + "grid_y": 85, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y124": { + "bits": {}, + "grid_x": 75, + "grid_y": 84, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y125": { + "bits": {}, + "grid_x": 75, + "grid_y": 83, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y126": { + "bits": {}, + "grid_x": 75, + "grid_y": 82, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y127": { + "bits": {}, + "grid_x": 75, + "grid_y": 81, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y128": { + "bits": {}, + "grid_x": 75, + "grid_y": 80, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X75Y129": { + "bits": {}, + "grid_x": 75, + "grid_y": 79, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y105": { + "bits": {}, + "grid_x": 76, + "grid_y": 103, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y106": { + "bits": {}, + "grid_x": 76, + "grid_y": 102, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y107": { + "bits": {}, + "grid_x": 76, + "grid_y": 101, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y108": { + "bits": {}, + "grid_x": 76, + "grid_y": 100, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y109": { + "bits": {}, + "grid_x": 76, + "grid_y": 99, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y110": { + "bits": {}, + "grid_x": 76, + "grid_y": 98, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y111": { + "bits": {}, + "grid_x": 76, + "grid_y": 97, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y112": { + "bits": {}, + "grid_x": 76, + "grid_y": 96, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y113": { + "bits": {}, + "grid_x": 76, + "grid_y": 95, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y114": { + "bits": {}, + "grid_x": 76, + "grid_y": 94, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y115": { + "bits": {}, + "grid_x": 76, + "grid_y": 93, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y116": { + "bits": {}, + "grid_x": 76, + "grid_y": 92, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y117": { + "bits": {}, + "grid_x": 76, + "grid_y": 91, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y118": { + "bits": {}, + "grid_x": 76, + "grid_y": 90, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y119": { + "bits": {}, + "grid_x": 76, + "grid_y": 89, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y120": { + "bits": {}, + "grid_x": 76, + "grid_y": 88, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y121": { + "bits": {}, + "grid_x": 76, + "grid_y": 87, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y122": { + "bits": {}, + "grid_x": 76, + "grid_y": 86, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y123": { + "bits": {}, + "grid_x": 76, + "grid_y": 85, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y124": { + "bits": {}, + "grid_x": 76, + "grid_y": 84, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y125": { + "bits": {}, + "grid_x": 76, + "grid_y": 83, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y126": { + "bits": {}, + "grid_x": 76, + "grid_y": 82, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y127": { + "bits": {}, + "grid_x": 76, + "grid_y": 81, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y128": { + "bits": {}, + "grid_x": 76, + "grid_y": 80, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X76Y129": { + "bits": {}, + "grid_x": 76, + "grid_y": 79, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y105": { + "bits": {}, + "grid_x": 77, + "grid_y": 103, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y106": { + "bits": {}, + "grid_x": 77, + "grid_y": 102, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y107": { + "bits": {}, + "grid_x": 77, + "grid_y": 101, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y108": { + "bits": {}, + "grid_x": 77, + "grid_y": 100, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y109": { + "bits": {}, + "grid_x": 77, + "grid_y": 99, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y110": { + "bits": {}, + "grid_x": 77, + "grid_y": 98, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y111": { + "bits": {}, + "grid_x": 77, + "grid_y": 97, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y112": { + "bits": {}, + "grid_x": 77, + "grid_y": 96, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y113": { + "bits": {}, + "grid_x": 77, + "grid_y": 95, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y114": { + "bits": {}, + "grid_x": 77, + "grid_y": 94, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y115": { + "bits": {}, + "grid_x": 77, + "grid_y": 93, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y116": { + "bits": {}, + "grid_x": 77, + "grid_y": 92, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y117": { + "bits": {}, + "grid_x": 77, + "grid_y": 91, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y118": { + "bits": {}, + "grid_x": 77, + "grid_y": 90, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y119": { + "bits": {}, + "grid_x": 77, + "grid_y": 89, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y120": { + "bits": {}, + "grid_x": 77, + "grid_y": 88, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y121": { + "bits": {}, + "grid_x": 77, + "grid_y": 87, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y122": { + "bits": {}, + "grid_x": 77, + "grid_y": 86, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y123": { + "bits": {}, + "grid_x": 77, + "grid_y": 85, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y124": { + "bits": {}, + "grid_x": 77, + "grid_y": 84, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y125": { + "bits": {}, + "grid_x": 77, + "grid_y": 83, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y126": { + "bits": {}, + "grid_x": 77, + "grid_y": 82, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y127": { + "bits": {}, + "grid_x": 77, + "grid_y": 81, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y128": { + "bits": {}, + "grid_x": 77, + "grid_y": 80, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_NULL_X77Y129": { + "bits": {}, + "grid_x": 77, + "grid_y": 79, + "sites": {}, + "type": "PCIE_NULL" + }, + "PCIE_TOP_X73Y125": { + "bits": {}, + "grid_x": 73, + "grid_y": 83, + "sites": {}, + "type": "PCIE_TOP" + }, + "RIOB18_SING_X43Y0": { + "bits": {}, + "grid_x": 116, + "grid_y": 207, + "sites": { + "IOB_X1Y0": "IOB18" + }, + "type": "RIOB18_SING" + }, + "RIOB18_SING_X43Y49": { + "bits": {}, + "grid_x": 116, + "grid_y": 157, + "sites": { + "IOB_X1Y49": "IOB18" + }, + "type": "RIOB18_SING" + }, + "RIOB18_SING_X43Y50": { + "bits": {}, + "grid_x": 116, + "grid_y": 155, + "sites": { + "IOB_X1Y50": "IOB18" + }, + "type": "RIOB18_SING" + }, + "RIOB18_SING_X43Y99": { + "bits": {}, + "grid_x": 116, + "grid_y": 105, + "sites": { + "IOB_X1Y99": "IOB18" + }, + "type": "RIOB18_SING" + }, + "RIOB18_X43Y1": { + "bits": {}, + "grid_x": 116, + "grid_y": 206, + "sites": { + "IOB_X1Y1": "IOB18S", + "IOB_X1Y2": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y11": { + "bits": {}, + "grid_x": 116, + "grid_y": 196, + "sites": { + "IOB_X1Y11": "IOB18S", + "IOB_X1Y12": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y13": { + "bits": {}, + "grid_x": 116, + "grid_y": 194, + "sites": { + "IOB_X1Y13": "IOB18S", + "IOB_X1Y14": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y15": { + "bits": {}, + "grid_x": 116, + "grid_y": 192, + "sites": { + "IOB_X1Y15": "IOB18S", + "IOB_X1Y16": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y17": { + "bits": {}, + "grid_x": 116, + "grid_y": 190, + "sites": { + "IOB_X1Y17": "IOB18S", + "IOB_X1Y18": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y19": { + "bits": {}, + "grid_x": 116, + "grid_y": 188, + "sites": { + "IOB_X1Y19": "IOB18S", + "IOB_X1Y20": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y21": { + "bits": {}, + "grid_x": 116, + "grid_y": 186, + "sites": { + "IOB_X1Y21": "IOB18S", + "IOB_X1Y22": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y23": { + "bits": {}, + "grid_x": 116, + "grid_y": 184, + "sites": { + "IOB_X1Y23": "IOB18S", + "IOB_X1Y24": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y25": { + "bits": {}, + "grid_x": 116, + "grid_y": 181, + "sites": { + "IOB_X1Y25": "IOB18S", + "IOB_X1Y26": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y27": { + "bits": {}, + "grid_x": 116, + "grid_y": 179, + "sites": { + "IOB_X1Y27": "IOB18S", + "IOB_X1Y28": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y29": { + "bits": {}, + "grid_x": 116, + "grid_y": 177, + "sites": { + "IOB_X1Y29": "IOB18S", + "IOB_X1Y30": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y3": { + "bits": {}, + "grid_x": 116, + "grid_y": 204, + "sites": { + "IOB_X1Y3": "IOB18S", + "IOB_X1Y4": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y31": { + "bits": {}, + "grid_x": 116, + "grid_y": 175, + "sites": { + "IOB_X1Y31": "IOB18S", + "IOB_X1Y32": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y33": { + "bits": {}, + "grid_x": 116, + "grid_y": 173, + "sites": { + "IOB_X1Y33": "IOB18S", + "IOB_X1Y34": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y35": { + "bits": {}, + "grid_x": 116, + "grid_y": 171, + "sites": { + "IOB_X1Y35": "IOB18S", + "IOB_X1Y36": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y37": { + "bits": {}, + "grid_x": 116, + "grid_y": 169, + "sites": { + "IOB_X1Y37": "IOB18S", + "IOB_X1Y38": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y39": { + "bits": {}, + "grid_x": 116, + "grid_y": 167, + "sites": { + "IOB_X1Y39": "IOB18S", + "IOB_X1Y40": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y41": { + "bits": {}, + "grid_x": 116, + "grid_y": 165, + "sites": { + "IOB_X1Y41": "IOB18S", + "IOB_X1Y42": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y43": { + "bits": {}, + "grid_x": 116, + "grid_y": 163, + "sites": { + "IOB_X1Y43": "IOB18S", + "IOB_X1Y44": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y45": { + "bits": {}, + "grid_x": 116, + "grid_y": 161, + "sites": { + "IOB_X1Y45": "IOB18S", + "IOB_X1Y46": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y47": { + "bits": {}, + "grid_x": 116, + "grid_y": 159, + "sites": { + "IOB_X1Y47": "IOB18S", + "IOB_X1Y48": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y5": { + "bits": {}, + "grid_x": 116, + "grid_y": 202, + "sites": { + "IOB_X1Y5": "IOB18S", + "IOB_X1Y6": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y51": { + "bits": {}, + "grid_x": 116, + "grid_y": 154, + "sites": { + "IOB_X1Y51": "IOB18S", + "IOB_X1Y52": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y53": { + "bits": {}, + "grid_x": 116, + "grid_y": 152, + "sites": { + "IOB_X1Y53": "IOB18S", + "IOB_X1Y54": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y55": { + "bits": {}, + "grid_x": 116, + "grid_y": 150, + "sites": { + "IOB_X1Y55": "IOB18S", + "IOB_X1Y56": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y57": { + "bits": {}, + "grid_x": 116, + "grid_y": 148, + "sites": { + "IOB_X1Y57": "IOB18S", + "IOB_X1Y58": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y59": { + "bits": {}, + "grid_x": 116, + "grid_y": 146, + "sites": { + "IOB_X1Y59": "IOB18S", + "IOB_X1Y60": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y61": { + "bits": {}, + "grid_x": 116, + "grid_y": 144, + "sites": { + "IOB_X1Y61": "IOB18S", + "IOB_X1Y62": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y63": { + "bits": {}, + "grid_x": 116, + "grid_y": 142, + "sites": { + "IOB_X1Y63": "IOB18S", + "IOB_X1Y64": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y65": { + "bits": {}, + "grid_x": 116, + "grid_y": 140, + "sites": { + "IOB_X1Y65": "IOB18S", + "IOB_X1Y66": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y67": { + "bits": {}, + "grid_x": 116, + "grid_y": 138, + "sites": { + "IOB_X1Y67": "IOB18S", + "IOB_X1Y68": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y69": { + "bits": {}, + "grid_x": 116, + "grid_y": 136, + "sites": { + "IOB_X1Y69": "IOB18S", + "IOB_X1Y70": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y7": { + "bits": {}, + "grid_x": 116, + "grid_y": 200, + "sites": { + "IOB_X1Y7": "IOB18S", + "IOB_X1Y8": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y71": { + "bits": {}, + "grid_x": 116, + "grid_y": 134, + "sites": { + "IOB_X1Y71": "IOB18S", + "IOB_X1Y72": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y73": { + "bits": {}, + "grid_x": 116, + "grid_y": 132, + "sites": { + "IOB_X1Y73": "IOB18S", + "IOB_X1Y74": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y75": { + "bits": {}, + "grid_x": 116, + "grid_y": 129, + "sites": { + "IOB_X1Y75": "IOB18S", + "IOB_X1Y76": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y77": { + "bits": {}, + "grid_x": 116, + "grid_y": 127, + "sites": { + "IOB_X1Y77": "IOB18S", + "IOB_X1Y78": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y79": { + "bits": {}, + "grid_x": 116, + "grid_y": 125, + "sites": { + "IOB_X1Y79": "IOB18S", + "IOB_X1Y80": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y81": { + "bits": {}, + "grid_x": 116, + "grid_y": 123, + "sites": { + "IOB_X1Y81": "IOB18S", + "IOB_X1Y82": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y83": { + "bits": {}, + "grid_x": 116, + "grid_y": 121, + "sites": { + "IOB_X1Y83": "IOB18S", + "IOB_X1Y84": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y85": { + "bits": {}, + "grid_x": 116, + "grid_y": 119, + "sites": { + "IOB_X1Y85": "IOB18S", + "IOB_X1Y86": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y87": { + "bits": {}, + "grid_x": 116, + "grid_y": 117, + "sites": { + "IOB_X1Y87": "IOB18S", + "IOB_X1Y88": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y89": { + "bits": {}, + "grid_x": 116, + "grid_y": 115, + "sites": { + "IOB_X1Y89": "IOB18S", + "IOB_X1Y90": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y9": { + "bits": {}, + "grid_x": 116, + "grid_y": 198, + "sites": { + "IOB_X1Y10": "IOB18M", + "IOB_X1Y9": "IOB18S" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y91": { + "bits": {}, + "grid_x": 116, + "grid_y": 113, + "sites": { + "IOB_X1Y91": "IOB18S", + "IOB_X1Y92": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y93": { + "bits": {}, + "grid_x": 116, + "grid_y": 111, + "sites": { + "IOB_X1Y93": "IOB18S", + "IOB_X1Y94": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y95": { + "bits": {}, + "grid_x": 116, + "grid_y": 109, + "sites": { + "IOB_X1Y95": "IOB18S", + "IOB_X1Y96": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOB18_X43Y97": { + "bits": {}, + "grid_x": 116, + "grid_y": 107, + "sites": { + "IOB_X1Y97": "IOB18S", + "IOB_X1Y98": "IOB18M" + }, + "type": "RIOB18" + }, + "RIOI_SING_X43Y0": { + "bits": {}, + "grid_x": 115, + "grid_y": 207, + "sites": { + "IDELAY_X1Y0": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y0": "ILOGICE2", + "ODELAY_X1Y0": "ODELAYE2", + "OLOGIC_X1Y0": "OLOGICE2" + }, + "type": "RIOI_SING" + }, + "RIOI_SING_X43Y49": { + "bits": {}, + "grid_x": 115, + "grid_y": 157, + "sites": { + "IDELAY_X1Y49": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y49": "ILOGICE2", + "ODELAY_X1Y49": "ODELAYE2", + "OLOGIC_X1Y49": "OLOGICE2" + }, + "type": "RIOI_SING" + }, + "RIOI_SING_X43Y50": { + "bits": {}, + "grid_x": 115, + "grid_y": 155, + "sites": { + "IDELAY_X1Y50": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y50": "ILOGICE2", + "ODELAY_X1Y50": "ODELAYE2", + "OLOGIC_X1Y50": "OLOGICE2" + }, + "type": "RIOI_SING" + }, + "RIOI_SING_X43Y99": { + "bits": {}, + "grid_x": 115, + "grid_y": 105, + "sites": { + "IDELAY_X1Y99": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y99": "ILOGICE2", + "ODELAY_X1Y99": "ODELAYE2", + "OLOGIC_X1Y99": "OLOGICE2" + }, + "type": "RIOI_SING" + }, + "RIOI_TBYTESRC_X43Y19": { + "bits": {}, + "grid_x": 115, + "grid_y": 188, + "sites": { + "IDELAY_X1Y19": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y20": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y19": "ILOGICE2", + "ILOGIC_X1Y20": "ILOGICE2", + "ODELAY_X1Y19": "ODELAYE2", + "ODELAY_X1Y20": "ODELAYE2", + "OLOGIC_X1Y19": "OLOGICE2", + "OLOGIC_X1Y20": "OLOGICE2" + }, + "type": "RIOI_TBYTESRC" + }, + "RIOI_TBYTESRC_X43Y31": { + "bits": {}, + "grid_x": 115, + "grid_y": 175, + "sites": { + "IDELAY_X1Y31": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y32": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y31": "ILOGICE2", + "ILOGIC_X1Y32": "ILOGICE2", + "ODELAY_X1Y31": "ODELAYE2", + "ODELAY_X1Y32": "ODELAYE2", + "OLOGIC_X1Y31": "OLOGICE2", + "OLOGIC_X1Y32": "OLOGICE2" + }, + "type": "RIOI_TBYTESRC" + }, + "RIOI_TBYTESRC_X43Y43": { + "bits": {}, + "grid_x": 115, + "grid_y": 163, + "sites": { + "IDELAY_X1Y43": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y44": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y43": "ILOGICE2", + "ILOGIC_X1Y44": "ILOGICE2", + "ODELAY_X1Y43": "ODELAYE2", + "ODELAY_X1Y44": "ODELAYE2", + "OLOGIC_X1Y43": "OLOGICE2", + "OLOGIC_X1Y44": "OLOGICE2" + }, + "type": "RIOI_TBYTESRC" + }, + "RIOI_TBYTESRC_X43Y57": { + "bits": {}, + "grid_x": 115, + "grid_y": 148, + "sites": { + "IDELAY_X1Y57": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y58": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y57": "ILOGICE2", + "ILOGIC_X1Y58": "ILOGICE2", + "ODELAY_X1Y57": "ODELAYE2", + "ODELAY_X1Y58": "ODELAYE2", + "OLOGIC_X1Y57": "OLOGICE2", + "OLOGIC_X1Y58": "OLOGICE2" + }, + "type": "RIOI_TBYTESRC" + }, + "RIOI_TBYTESRC_X43Y69": { + "bits": {}, + "grid_x": 115, + "grid_y": 136, + "sites": { + "IDELAY_X1Y69": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y70": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y69": "ILOGICE2", + "ILOGIC_X1Y70": "ILOGICE2", + "ODELAY_X1Y69": "ODELAYE2", + "ODELAY_X1Y70": "ODELAYE2", + "OLOGIC_X1Y69": "OLOGICE2", + "OLOGIC_X1Y70": "OLOGICE2" + }, + "type": "RIOI_TBYTESRC" + }, + "RIOI_TBYTESRC_X43Y7": { + "bits": {}, + "grid_x": 115, + "grid_y": 200, + "sites": { + "IDELAY_X1Y7": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y8": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y7": "ILOGICE2", + "ILOGIC_X1Y8": "ILOGICE2", + "ODELAY_X1Y7": "ODELAYE2", + "ODELAY_X1Y8": "ODELAYE2", + "OLOGIC_X1Y7": "OLOGICE2", + "OLOGIC_X1Y8": "OLOGICE2" + }, + "type": "RIOI_TBYTESRC" + }, + "RIOI_TBYTESRC_X43Y81": { + "bits": {}, + "grid_x": 115, + "grid_y": 123, + "sites": { + "IDELAY_X1Y81": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y82": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y81": "ILOGICE2", + "ILOGIC_X1Y82": "ILOGICE2", + "ODELAY_X1Y81": "ODELAYE2", + "ODELAY_X1Y82": "ODELAYE2", + "OLOGIC_X1Y81": "OLOGICE2", + "OLOGIC_X1Y82": "OLOGICE2" + }, + "type": "RIOI_TBYTESRC" + }, + "RIOI_TBYTESRC_X43Y93": { + "bits": {}, + "grid_x": 115, + "grid_y": 111, + "sites": { + "IDELAY_X1Y93": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y94": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y93": "ILOGICE2", + "ILOGIC_X1Y94": "ILOGICE2", + "ODELAY_X1Y93": "ODELAYE2", + "ODELAY_X1Y94": "ODELAYE2", + "OLOGIC_X1Y93": "OLOGICE2", + "OLOGIC_X1Y94": "OLOGICE2" + }, + "type": "RIOI_TBYTESRC" + }, + "RIOI_TBYTETERM_X43Y13": { + "bits": {}, + "grid_x": 115, + "grid_y": 194, + "sites": { + "IDELAY_X1Y13": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y14": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y13": "ILOGICE2", + "ILOGIC_X1Y14": "ILOGICE2", + "ODELAY_X1Y13": "ODELAYE2", + "ODELAY_X1Y14": "ODELAYE2", + "OLOGIC_X1Y13": "OLOGICE2", + "OLOGIC_X1Y14": "OLOGICE2" + }, + "type": "RIOI_TBYTETERM" + }, + "RIOI_TBYTETERM_X43Y37": { + "bits": {}, + "grid_x": 115, + "grid_y": 169, + "sites": { + "IDELAY_X1Y37": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y38": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y37": "ILOGICE2", + "ILOGIC_X1Y38": "ILOGICE2", + "ODELAY_X1Y37": "ODELAYE2", + "ODELAY_X1Y38": "ODELAYE2", + "OLOGIC_X1Y37": "OLOGICE2", + "OLOGIC_X1Y38": "OLOGICE2" + }, + "type": "RIOI_TBYTETERM" + }, + "RIOI_TBYTETERM_X43Y63": { + "bits": {}, + "grid_x": 115, + "grid_y": 142, + "sites": { + "IDELAY_X1Y63": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y64": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y63": "ILOGICE2", + "ILOGIC_X1Y64": "ILOGICE2", + "ODELAY_X1Y63": "ODELAYE2", + "ODELAY_X1Y64": "ODELAYE2", + "OLOGIC_X1Y63": "OLOGICE2", + "OLOGIC_X1Y64": "OLOGICE2" + }, + "type": "RIOI_TBYTETERM" + }, + "RIOI_TBYTETERM_X43Y87": { + "bits": {}, + "grid_x": 115, + "grid_y": 117, + "sites": { + "IDELAY_X1Y87": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y88": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y87": "ILOGICE2", + "ILOGIC_X1Y88": "ILOGICE2", + "ODELAY_X1Y87": "ODELAYE2", + "ODELAY_X1Y88": "ODELAYE2", + "OLOGIC_X1Y87": "OLOGICE2", + "OLOGIC_X1Y88": "OLOGICE2" + }, + "type": "RIOI_TBYTETERM" + }, + "RIOI_X43Y1": { + "bits": {}, + "grid_x": 115, + "grid_y": 206, + "sites": { + "IDELAY_X1Y1": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y2": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y1": "ILOGICE2", + "ILOGIC_X1Y2": "ILOGICE2", + "ODELAY_X1Y1": "ODELAYE2", + "ODELAY_X1Y2": "ODELAYE2", + "OLOGIC_X1Y1": "OLOGICE2", + "OLOGIC_X1Y2": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y11": { + "bits": {}, + "grid_x": 115, + "grid_y": 196, + "sites": { + "IDELAY_X1Y11": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y12": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y11": "ILOGICE2", + "ILOGIC_X1Y12": "ILOGICE2", + "ODELAY_X1Y11": "ODELAYE2", + "ODELAY_X1Y12": "ODELAYE2", + "OLOGIC_X1Y11": "OLOGICE2", + "OLOGIC_X1Y12": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y15": { + "bits": {}, + "grid_x": 115, + "grid_y": 192, + "sites": { + "IDELAY_X1Y15": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y16": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y15": "ILOGICE2", + "ILOGIC_X1Y16": "ILOGICE2", + "ODELAY_X1Y15": "ODELAYE2", + "ODELAY_X1Y16": "ODELAYE2", + "OLOGIC_X1Y15": "OLOGICE2", + "OLOGIC_X1Y16": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y17": { + "bits": {}, + "grid_x": 115, + "grid_y": 190, + "sites": { + "IDELAY_X1Y17": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y18": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y17": "ILOGICE2", + "ILOGIC_X1Y18": "ILOGICE2", + "ODELAY_X1Y17": "ODELAYE2", + "ODELAY_X1Y18": "ODELAYE2", + "OLOGIC_X1Y17": "OLOGICE2", + "OLOGIC_X1Y18": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y21": { + "bits": {}, + "grid_x": 115, + "grid_y": 186, + "sites": { + "IDELAY_X1Y21": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y22": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y21": "ILOGICE2", + "ILOGIC_X1Y22": "ILOGICE2", + "ODELAY_X1Y21": "ODELAYE2", + "ODELAY_X1Y22": "ODELAYE2", + "OLOGIC_X1Y21": "OLOGICE2", + "OLOGIC_X1Y22": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y23": { + "bits": {}, + "grid_x": 115, + "grid_y": 184, + "sites": { + "IDELAY_X1Y23": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y24": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y23": "ILOGICE2", + "ILOGIC_X1Y24": "ILOGICE2", + "ODELAY_X1Y23": "ODELAYE2", + "ODELAY_X1Y24": "ODELAYE2", + "OLOGIC_X1Y23": "OLOGICE2", + "OLOGIC_X1Y24": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y25": { + "bits": {}, + "grid_x": 115, + "grid_y": 181, + "sites": { + "IDELAY_X1Y25": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y26": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y25": "ILOGICE2", + "ILOGIC_X1Y26": "ILOGICE2", + "ODELAY_X1Y25": "ODELAYE2", + "ODELAY_X1Y26": "ODELAYE2", + "OLOGIC_X1Y25": "OLOGICE2", + "OLOGIC_X1Y26": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y27": { + "bits": {}, + "grid_x": 115, + "grid_y": 179, + "sites": { + "IDELAY_X1Y27": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y28": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y27": "ILOGICE2", + "ILOGIC_X1Y28": "ILOGICE2", + "ODELAY_X1Y27": "ODELAYE2", + "ODELAY_X1Y28": "ODELAYE2", + "OLOGIC_X1Y27": "OLOGICE2", + "OLOGIC_X1Y28": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y29": { + "bits": {}, + "grid_x": 115, + "grid_y": 177, + "sites": { + "IDELAY_X1Y29": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y30": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y29": "ILOGICE2", + "ILOGIC_X1Y30": "ILOGICE2", + "ODELAY_X1Y29": "ODELAYE2", + "ODELAY_X1Y30": "ODELAYE2", + "OLOGIC_X1Y29": "OLOGICE2", + "OLOGIC_X1Y30": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y3": { + "bits": {}, + "grid_x": 115, + "grid_y": 204, + "sites": { + "IDELAY_X1Y3": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y4": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y3": "ILOGICE2", + "ILOGIC_X1Y4": "ILOGICE2", + "ODELAY_X1Y3": "ODELAYE2", + "ODELAY_X1Y4": "ODELAYE2", + "OLOGIC_X1Y3": "OLOGICE2", + "OLOGIC_X1Y4": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y33": { + "bits": {}, + "grid_x": 115, + "grid_y": 173, + "sites": { + "IDELAY_X1Y33": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y34": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y33": "ILOGICE2", + "ILOGIC_X1Y34": "ILOGICE2", + "ODELAY_X1Y33": "ODELAYE2", + "ODELAY_X1Y34": "ODELAYE2", + "OLOGIC_X1Y33": "OLOGICE2", + "OLOGIC_X1Y34": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y35": { + "bits": {}, + "grid_x": 115, + "grid_y": 171, + "sites": { + "IDELAY_X1Y35": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y36": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y35": "ILOGICE2", + "ILOGIC_X1Y36": "ILOGICE2", + "ODELAY_X1Y35": "ODELAYE2", + "ODELAY_X1Y36": "ODELAYE2", + "OLOGIC_X1Y35": "OLOGICE2", + "OLOGIC_X1Y36": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y39": { + "bits": {}, + "grid_x": 115, + "grid_y": 167, + "sites": { + "IDELAY_X1Y39": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y40": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y39": "ILOGICE2", + "ILOGIC_X1Y40": "ILOGICE2", + "ODELAY_X1Y39": "ODELAYE2", + "ODELAY_X1Y40": "ODELAYE2", + "OLOGIC_X1Y39": "OLOGICE2", + "OLOGIC_X1Y40": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y41": { + "bits": {}, + "grid_x": 115, + "grid_y": 165, + "sites": { + "IDELAY_X1Y41": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y42": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y41": "ILOGICE2", + "ILOGIC_X1Y42": "ILOGICE2", + "ODELAY_X1Y41": "ODELAYE2", + "ODELAY_X1Y42": "ODELAYE2", + "OLOGIC_X1Y41": "OLOGICE2", + "OLOGIC_X1Y42": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y45": { + "bits": {}, + "grid_x": 115, + "grid_y": 161, + "sites": { + "IDELAY_X1Y45": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y46": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y45": "ILOGICE2", + "ILOGIC_X1Y46": "ILOGICE2", + "ODELAY_X1Y45": "ODELAYE2", + "ODELAY_X1Y46": "ODELAYE2", + "OLOGIC_X1Y45": "OLOGICE2", + "OLOGIC_X1Y46": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y47": { + "bits": {}, + "grid_x": 115, + "grid_y": 159, + "sites": { + "IDELAY_X1Y47": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y48": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y47": "ILOGICE2", + "ILOGIC_X1Y48": "ILOGICE2", + "ODELAY_X1Y47": "ODELAYE2", + "ODELAY_X1Y48": "ODELAYE2", + "OLOGIC_X1Y47": "OLOGICE2", + "OLOGIC_X1Y48": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y5": { + "bits": {}, + "grid_x": 115, + "grid_y": 202, + "sites": { + "IDELAY_X1Y5": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y6": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y5": "ILOGICE2", + "ILOGIC_X1Y6": "ILOGICE2", + "ODELAY_X1Y5": "ODELAYE2", + "ODELAY_X1Y6": "ODELAYE2", + "OLOGIC_X1Y5": "OLOGICE2", + "OLOGIC_X1Y6": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y51": { + "bits": {}, + "grid_x": 115, + "grid_y": 154, + "sites": { + "IDELAY_X1Y51": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y52": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y51": "ILOGICE2", + "ILOGIC_X1Y52": "ILOGICE2", + "ODELAY_X1Y51": "ODELAYE2", + "ODELAY_X1Y52": "ODELAYE2", + "OLOGIC_X1Y51": "OLOGICE2", + "OLOGIC_X1Y52": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y53": { + "bits": {}, + "grid_x": 115, + "grid_y": 152, + "sites": { + "IDELAY_X1Y53": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y54": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y53": "ILOGICE2", + "ILOGIC_X1Y54": "ILOGICE2", + "ODELAY_X1Y53": "ODELAYE2", + "ODELAY_X1Y54": "ODELAYE2", + "OLOGIC_X1Y53": "OLOGICE2", + "OLOGIC_X1Y54": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y55": { + "bits": {}, + "grid_x": 115, + "grid_y": 150, + "sites": { + "IDELAY_X1Y55": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y56": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y55": "ILOGICE2", + "ILOGIC_X1Y56": "ILOGICE2", + "ODELAY_X1Y55": "ODELAYE2", + "ODELAY_X1Y56": "ODELAYE2", + "OLOGIC_X1Y55": "OLOGICE2", + "OLOGIC_X1Y56": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y59": { + "bits": {}, + "grid_x": 115, + "grid_y": 146, + "sites": { + "IDELAY_X1Y59": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y60": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y59": "ILOGICE2", + "ILOGIC_X1Y60": "ILOGICE2", + "ODELAY_X1Y59": "ODELAYE2", + "ODELAY_X1Y60": "ODELAYE2", + "OLOGIC_X1Y59": "OLOGICE2", + "OLOGIC_X1Y60": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y61": { + "bits": {}, + "grid_x": 115, + "grid_y": 144, + "sites": { + "IDELAY_X1Y61": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y62": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y61": "ILOGICE2", + "ILOGIC_X1Y62": "ILOGICE2", + "ODELAY_X1Y61": "ODELAYE2", + "ODELAY_X1Y62": "ODELAYE2", + "OLOGIC_X1Y61": "OLOGICE2", + "OLOGIC_X1Y62": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y65": { + "bits": {}, + "grid_x": 115, + "grid_y": 140, + "sites": { + "IDELAY_X1Y65": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y66": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y65": "ILOGICE2", + "ILOGIC_X1Y66": "ILOGICE2", + "ODELAY_X1Y65": "ODELAYE2", + "ODELAY_X1Y66": "ODELAYE2", + "OLOGIC_X1Y65": "OLOGICE2", + "OLOGIC_X1Y66": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y67": { + "bits": {}, + "grid_x": 115, + "grid_y": 138, + "sites": { + "IDELAY_X1Y67": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y68": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y67": "ILOGICE2", + "ILOGIC_X1Y68": "ILOGICE2", + "ODELAY_X1Y67": "ODELAYE2", + "ODELAY_X1Y68": "ODELAYE2", + "OLOGIC_X1Y67": "OLOGICE2", + "OLOGIC_X1Y68": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y71": { + "bits": {}, + "grid_x": 115, + "grid_y": 134, + "sites": { + "IDELAY_X1Y71": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y72": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y71": "ILOGICE2", + "ILOGIC_X1Y72": "ILOGICE2", + "ODELAY_X1Y71": "ODELAYE2", + "ODELAY_X1Y72": "ODELAYE2", + "OLOGIC_X1Y71": "OLOGICE2", + "OLOGIC_X1Y72": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y73": { + "bits": {}, + "grid_x": 115, + "grid_y": 132, + "sites": { + "IDELAY_X1Y73": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y74": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y73": "ILOGICE2", + "ILOGIC_X1Y74": "ILOGICE2", + "ODELAY_X1Y73": "ODELAYE2", + "ODELAY_X1Y74": "ODELAYE2", + "OLOGIC_X1Y73": "OLOGICE2", + "OLOGIC_X1Y74": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y75": { + "bits": {}, + "grid_x": 115, + "grid_y": 129, + "sites": { + "IDELAY_X1Y75": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y76": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y75": "ILOGICE2", + "ILOGIC_X1Y76": "ILOGICE2", + "ODELAY_X1Y75": "ODELAYE2", + "ODELAY_X1Y76": "ODELAYE2", + "OLOGIC_X1Y75": "OLOGICE2", + "OLOGIC_X1Y76": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y77": { + "bits": {}, + "grid_x": 115, + "grid_y": 127, + "sites": { + "IDELAY_X1Y77": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y78": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y77": "ILOGICE2", + "ILOGIC_X1Y78": "ILOGICE2", + "ODELAY_X1Y77": "ODELAYE2", + "ODELAY_X1Y78": "ODELAYE2", + "OLOGIC_X1Y77": "OLOGICE2", + "OLOGIC_X1Y78": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y79": { + "bits": {}, + "grid_x": 115, + "grid_y": 125, + "sites": { + "IDELAY_X1Y79": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y80": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y79": "ILOGICE2", + "ILOGIC_X1Y80": "ILOGICE2", + "ODELAY_X1Y79": "ODELAYE2", + "ODELAY_X1Y80": "ODELAYE2", + "OLOGIC_X1Y79": "OLOGICE2", + "OLOGIC_X1Y80": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y83": { + "bits": {}, + "grid_x": 115, + "grid_y": 121, + "sites": { + "IDELAY_X1Y83": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y84": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y83": "ILOGICE2", + "ILOGIC_X1Y84": "ILOGICE2", + "ODELAY_X1Y83": "ODELAYE2", + "ODELAY_X1Y84": "ODELAYE2", + "OLOGIC_X1Y83": "OLOGICE2", + "OLOGIC_X1Y84": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y85": { + "bits": {}, + "grid_x": 115, + "grid_y": 119, + "sites": { + "IDELAY_X1Y85": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y86": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y85": "ILOGICE2", + "ILOGIC_X1Y86": "ILOGICE2", + "ODELAY_X1Y85": "ODELAYE2", + "ODELAY_X1Y86": "ODELAYE2", + "OLOGIC_X1Y85": "OLOGICE2", + "OLOGIC_X1Y86": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y89": { + "bits": {}, + "grid_x": 115, + "grid_y": 115, + "sites": { + "IDELAY_X1Y89": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y90": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y89": "ILOGICE2", + "ILOGIC_X1Y90": "ILOGICE2", + "ODELAY_X1Y89": "ODELAYE2", + "ODELAY_X1Y90": "ODELAYE2", + "OLOGIC_X1Y89": "OLOGICE2", + "OLOGIC_X1Y90": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y9": { + "bits": {}, + "grid_x": 115, + "grid_y": 198, + "sites": { + "IDELAY_X1Y10": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y9": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y10": "ILOGICE2", + "ILOGIC_X1Y9": "ILOGICE2", + "ODELAY_X1Y10": "ODELAYE2", + "ODELAY_X1Y9": "ODELAYE2", + "OLOGIC_X1Y10": "OLOGICE2", + "OLOGIC_X1Y9": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y91": { + "bits": {}, + "grid_x": 115, + "grid_y": 113, + "sites": { + "IDELAY_X1Y91": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y92": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y91": "ILOGICE2", + "ILOGIC_X1Y92": "ILOGICE2", + "ODELAY_X1Y91": "ODELAYE2", + "ODELAY_X1Y92": "ODELAYE2", + "OLOGIC_X1Y91": "OLOGICE2", + "OLOGIC_X1Y92": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y95": { + "bits": {}, + "grid_x": 115, + "grid_y": 109, + "sites": { + "IDELAY_X1Y95": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y96": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y95": "ILOGICE2", + "ILOGIC_X1Y96": "ILOGICE2", + "ODELAY_X1Y95": "ODELAYE2", + "ODELAY_X1Y96": "ODELAYE2", + "OLOGIC_X1Y95": "OLOGICE2", + "OLOGIC_X1Y96": "OLOGICE2" + }, + "type": "RIOI" + }, + "RIOI_X43Y97": { + "bits": {}, + "grid_x": 115, + "grid_y": 107, + "sites": { + "IDELAY_X1Y97": "IDELAYE2_FINEDELAY", + "IDELAY_X1Y98": "IDELAYE2_FINEDELAY", + "ILOGIC_X1Y97": "ILOGICE2", + "ILOGIC_X1Y98": "ILOGICE2", + "ODELAY_X1Y97": "ODELAYE2", + "ODELAY_X1Y98": "ODELAYE2", + "OLOGIC_X1Y97": "OLOGICE2", + "OLOGIC_X1Y98": "OLOGICE2" + }, + "type": "RIOI" + }, + "R_TERM_INT_GTX_X97Y105": { + "bits": {}, + "grid_x": 97, + "grid_y": 103, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y106": { + "bits": {}, + "grid_x": 97, + "grid_y": 102, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y107": { + "bits": {}, + "grid_x": 97, + "grid_y": 101, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y108": { + "bits": {}, + "grid_x": 97, + "grid_y": 100, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y109": { + "bits": {}, + "grid_x": 97, + "grid_y": 99, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y110": { + "bits": {}, + "grid_x": 97, + "grid_y": 98, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y111": { + "bits": {}, + "grid_x": 97, + "grid_y": 97, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y112": { + "bits": {}, + "grid_x": 97, + "grid_y": 96, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y113": { + "bits": {}, + "grid_x": 97, + "grid_y": 95, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y114": { + "bits": {}, + "grid_x": 97, + "grid_y": 94, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y115": { + "bits": {}, + "grid_x": 97, + "grid_y": 93, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y116": { + "bits": {}, + "grid_x": 97, + "grid_y": 92, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y117": { + "bits": {}, + "grid_x": 97, + "grid_y": 91, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y118": { + "bits": {}, + "grid_x": 97, + "grid_y": 90, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y119": { + "bits": {}, + "grid_x": 97, + "grid_y": 89, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y120": { + "bits": {}, + "grid_x": 97, + "grid_y": 88, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y121": { + "bits": {}, + "grid_x": 97, + "grid_y": 87, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y122": { + "bits": {}, + "grid_x": 97, + "grid_y": 86, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y123": { + "bits": {}, + "grid_x": 97, + "grid_y": 85, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y124": { + "bits": {}, + "grid_x": 97, + "grid_y": 84, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y125": { + "bits": {}, + "grid_x": 97, + "grid_y": 83, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y126": { + "bits": {}, + "grid_x": 97, + "grid_y": 82, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y127": { + "bits": {}, + "grid_x": 97, + "grid_y": 81, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y128": { + "bits": {}, + "grid_x": 97, + "grid_y": 80, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y129": { + "bits": {}, + "grid_x": 97, + "grid_y": 79, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y131": { + "bits": {}, + "grid_x": 97, + "grid_y": 77, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y132": { + "bits": {}, + "grid_x": 97, + "grid_y": 76, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y133": { + "bits": {}, + "grid_x": 97, + "grid_y": 75, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y134": { + "bits": {}, + "grid_x": 97, + "grid_y": 74, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y135": { + "bits": {}, + "grid_x": 97, + "grid_y": 73, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y136": { + "bits": {}, + "grid_x": 97, + "grid_y": 72, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y137": { + "bits": {}, + "grid_x": 97, + "grid_y": 71, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y138": { + "bits": {}, + "grid_x": 97, + "grid_y": 70, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y139": { + "bits": {}, + "grid_x": 97, + "grid_y": 69, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y140": { + "bits": {}, + "grid_x": 97, + "grid_y": 68, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y141": { + "bits": {}, + "grid_x": 97, + "grid_y": 67, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y142": { + "bits": {}, + "grid_x": 97, + "grid_y": 66, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y143": { + "bits": {}, + "grid_x": 97, + "grid_y": 65, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y144": { + "bits": {}, + "grid_x": 97, + "grid_y": 64, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y145": { + "bits": {}, + "grid_x": 97, + "grid_y": 63, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y146": { + "bits": {}, + "grid_x": 97, + "grid_y": 62, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y147": { + "bits": {}, + "grid_x": 97, + "grid_y": 61, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y148": { + "bits": {}, + "grid_x": 97, + "grid_y": 60, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y149": { + "bits": {}, + "grid_x": 97, + "grid_y": 59, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y150": { + "bits": {}, + "grid_x": 97, + "grid_y": 58, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y151": { + "bits": {}, + "grid_x": 97, + "grid_y": 57, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y152": { + "bits": {}, + "grid_x": 97, + "grid_y": 56, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y153": { + "bits": {}, + "grid_x": 97, + "grid_y": 55, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y154": { + "bits": {}, + "grid_x": 97, + "grid_y": 54, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y155": { + "bits": {}, + "grid_x": 97, + "grid_y": 53, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y157": { + "bits": {}, + "grid_x": 97, + "grid_y": 51, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y158": { + "bits": {}, + "grid_x": 97, + "grid_y": 50, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y159": { + "bits": {}, + "grid_x": 97, + "grid_y": 49, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y160": { + "bits": {}, + "grid_x": 97, + "grid_y": 48, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y161": { + "bits": {}, + "grid_x": 97, + "grid_y": 47, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y162": { + "bits": {}, + "grid_x": 97, + "grid_y": 46, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y163": { + "bits": {}, + "grid_x": 97, + "grid_y": 45, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y164": { + "bits": {}, + "grid_x": 97, + "grid_y": 44, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y165": { + "bits": {}, + "grid_x": 97, + "grid_y": 43, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y166": { + "bits": {}, + "grid_x": 97, + "grid_y": 42, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y167": { + "bits": {}, + "grid_x": 97, + "grid_y": 41, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y168": { + "bits": {}, + "grid_x": 97, + "grid_y": 40, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y169": { + "bits": {}, + "grid_x": 97, + "grid_y": 39, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y170": { + "bits": {}, + "grid_x": 97, + "grid_y": 38, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y171": { + "bits": {}, + "grid_x": 97, + "grid_y": 37, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y172": { + "bits": {}, + "grid_x": 97, + "grid_y": 36, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y173": { + "bits": {}, + "grid_x": 97, + "grid_y": 35, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y174": { + "bits": {}, + "grid_x": 97, + "grid_y": 34, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y175": { + "bits": {}, + "grid_x": 97, + "grid_y": 33, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y176": { + "bits": {}, + "grid_x": 97, + "grid_y": 32, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y177": { + "bits": {}, + "grid_x": 97, + "grid_y": 31, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y178": { + "bits": {}, + "grid_x": 97, + "grid_y": 30, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y179": { + "bits": {}, + "grid_x": 97, + "grid_y": 29, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y180": { + "bits": {}, + "grid_x": 97, + "grid_y": 28, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y181": { + "bits": {}, + "grid_x": 97, + "grid_y": 27, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y183": { + "bits": {}, + "grid_x": 97, + "grid_y": 25, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y184": { + "bits": {}, + "grid_x": 97, + "grid_y": 24, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y185": { + "bits": {}, + "grid_x": 97, + "grid_y": 23, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y186": { + "bits": {}, + "grid_x": 97, + "grid_y": 22, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y187": { + "bits": {}, + "grid_x": 97, + "grid_y": 21, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y188": { + "bits": {}, + "grid_x": 97, + "grid_y": 20, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y189": { + "bits": {}, + "grid_x": 97, + "grid_y": 19, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y190": { + "bits": {}, + "grid_x": 97, + "grid_y": 18, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y191": { + "bits": {}, + "grid_x": 97, + "grid_y": 17, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y192": { + "bits": {}, + "grid_x": 97, + "grid_y": 16, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y193": { + "bits": {}, + "grid_x": 97, + "grid_y": 15, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y194": { + "bits": {}, + "grid_x": 97, + "grid_y": 14, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y195": { + "bits": {}, + "grid_x": 97, + "grid_y": 13, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y196": { + "bits": {}, + "grid_x": 97, + "grid_y": 12, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y197": { + "bits": {}, + "grid_x": 97, + "grid_y": 11, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y198": { + "bits": {}, + "grid_x": 97, + "grid_y": 10, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y199": { + "bits": {}, + "grid_x": 97, + "grid_y": 9, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y200": { + "bits": {}, + "grid_x": 97, + "grid_y": 8, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y201": { + "bits": {}, + "grid_x": 97, + "grid_y": 7, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y202": { + "bits": {}, + "grid_x": 97, + "grid_y": 6, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y203": { + "bits": {}, + "grid_x": 97, + "grid_y": 5, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y204": { + "bits": {}, + "grid_x": 97, + "grid_y": 4, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y205": { + "bits": {}, + "grid_x": 97, + "grid_y": 3, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y206": { + "bits": {}, + "grid_x": 97, + "grid_y": 2, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_GTX_X97Y207": { + "bits": {}, + "grid_x": 97, + "grid_y": 1, + "sites": {}, + "type": "R_TERM_INT_GTX" + }, + "R_TERM_INT_X114Y1": { + "bits": {}, + "grid_x": 114, + "grid_y": 207, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y10": { + "bits": {}, + "grid_x": 114, + "grid_y": 198, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y100": { + "bits": {}, + "grid_x": 114, + "grid_y": 108, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y101": { + "bits": {}, + "grid_x": 114, + "grid_y": 107, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y102": { + "bits": {}, + "grid_x": 114, + "grid_y": 106, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y103": { + "bits": {}, + "grid_x": 114, + "grid_y": 105, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y11": { + "bits": {}, + "grid_x": 114, + "grid_y": 197, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y12": { + "bits": {}, + "grid_x": 114, + "grid_y": 196, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y13": { + "bits": {}, + "grid_x": 114, + "grid_y": 195, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y14": { + "bits": {}, + "grid_x": 114, + "grid_y": 194, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y15": { + "bits": {}, + "grid_x": 114, + "grid_y": 193, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y16": { + "bits": {}, + "grid_x": 114, + "grid_y": 192, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y17": { + "bits": {}, + "grid_x": 114, + "grid_y": 191, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y18": { + "bits": {}, + "grid_x": 114, + "grid_y": 190, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y19": { + "bits": {}, + "grid_x": 114, + "grid_y": 189, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y2": { + "bits": {}, + "grid_x": 114, + "grid_y": 206, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y20": { + "bits": {}, + "grid_x": 114, + "grid_y": 188, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y21": { + "bits": {}, + "grid_x": 114, + "grid_y": 187, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y22": { + "bits": {}, + "grid_x": 114, + "grid_y": 186, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y23": { + "bits": {}, + "grid_x": 114, + "grid_y": 185, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y24": { + "bits": {}, + "grid_x": 114, + "grid_y": 184, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y25": { + "bits": {}, + "grid_x": 114, + "grid_y": 183, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y27": { + "bits": {}, + "grid_x": 114, + "grid_y": 181, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y28": { + "bits": {}, + "grid_x": 114, + "grid_y": 180, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y29": { + "bits": {}, + "grid_x": 114, + "grid_y": 179, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y3": { + "bits": {}, + "grid_x": 114, + "grid_y": 205, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y30": { + "bits": {}, + "grid_x": 114, + "grid_y": 178, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y31": { + "bits": {}, + "grid_x": 114, + "grid_y": 177, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y32": { + "bits": {}, + "grid_x": 114, + "grid_y": 176, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y33": { + "bits": {}, + "grid_x": 114, + "grid_y": 175, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y34": { + "bits": {}, + "grid_x": 114, + "grid_y": 174, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y35": { + "bits": {}, + "grid_x": 114, + "grid_y": 173, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y36": { + "bits": {}, + "grid_x": 114, + "grid_y": 172, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y37": { + "bits": {}, + "grid_x": 114, + "grid_y": 171, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y38": { + "bits": {}, + "grid_x": 114, + "grid_y": 170, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y39": { + "bits": {}, + "grid_x": 114, + "grid_y": 169, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y4": { + "bits": {}, + "grid_x": 114, + "grid_y": 204, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y40": { + "bits": {}, + "grid_x": 114, + "grid_y": 168, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y41": { + "bits": {}, + "grid_x": 114, + "grid_y": 167, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y42": { + "bits": {}, + "grid_x": 114, + "grid_y": 166, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y43": { + "bits": {}, + "grid_x": 114, + "grid_y": 165, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y44": { + "bits": {}, + "grid_x": 114, + "grid_y": 164, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y45": { + "bits": {}, + "grid_x": 114, + "grid_y": 163, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y46": { + "bits": {}, + "grid_x": 114, + "grid_y": 162, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y47": { + "bits": {}, + "grid_x": 114, + "grid_y": 161, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y48": { + "bits": {}, + "grid_x": 114, + "grid_y": 160, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y49": { + "bits": {}, + "grid_x": 114, + "grid_y": 159, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y5": { + "bits": {}, + "grid_x": 114, + "grid_y": 203, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y50": { + "bits": {}, + "grid_x": 114, + "grid_y": 158, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y51": { + "bits": {}, + "grid_x": 114, + "grid_y": 157, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y53": { + "bits": {}, + "grid_x": 114, + "grid_y": 155, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y54": { + "bits": {}, + "grid_x": 114, + "grid_y": 154, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y55": { + "bits": {}, + "grid_x": 114, + "grid_y": 153, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y56": { + "bits": {}, + "grid_x": 114, + "grid_y": 152, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y57": { + "bits": {}, + "grid_x": 114, + "grid_y": 151, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y58": { + "bits": {}, + "grid_x": 114, + "grid_y": 150, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y59": { + "bits": {}, + "grid_x": 114, + "grid_y": 149, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y6": { + "bits": {}, + "grid_x": 114, + "grid_y": 202, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y60": { + "bits": {}, + "grid_x": 114, + "grid_y": 148, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y61": { + "bits": {}, + "grid_x": 114, + "grid_y": 147, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y62": { + "bits": {}, + "grid_x": 114, + "grid_y": 146, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y63": { + "bits": {}, + "grid_x": 114, + "grid_y": 145, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y64": { + "bits": {}, + "grid_x": 114, + "grid_y": 144, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y65": { + "bits": {}, + "grid_x": 114, + "grid_y": 143, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y66": { + "bits": {}, + "grid_x": 114, + "grid_y": 142, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y67": { + "bits": {}, + "grid_x": 114, + "grid_y": 141, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y68": { + "bits": {}, + "grid_x": 114, + "grid_y": 140, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y69": { + "bits": {}, + "grid_x": 114, + "grid_y": 139, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y7": { + "bits": {}, + "grid_x": 114, + "grid_y": 201, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y70": { + "bits": {}, + "grid_x": 114, + "grid_y": 138, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y71": { + "bits": {}, + "grid_x": 114, + "grid_y": 137, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y72": { + "bits": {}, + "grid_x": 114, + "grid_y": 136, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y73": { + "bits": {}, + "grid_x": 114, + "grid_y": 135, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y74": { + "bits": {}, + "grid_x": 114, + "grid_y": 134, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y75": { + "bits": {}, + "grid_x": 114, + "grid_y": 133, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y76": { + "bits": {}, + "grid_x": 114, + "grid_y": 132, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y77": { + "bits": {}, + "grid_x": 114, + "grid_y": 131, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y79": { + "bits": {}, + "grid_x": 114, + "grid_y": 129, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y8": { + "bits": {}, + "grid_x": 114, + "grid_y": 200, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y80": { + "bits": {}, + "grid_x": 114, + "grid_y": 128, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y81": { + "bits": {}, + "grid_x": 114, + "grid_y": 127, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y82": { + "bits": {}, + "grid_x": 114, + "grid_y": 126, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y83": { + "bits": {}, + "grid_x": 114, + "grid_y": 125, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y84": { + "bits": {}, + "grid_x": 114, + "grid_y": 124, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y85": { + "bits": {}, + "grid_x": 114, + "grid_y": 123, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y86": { + "bits": {}, + "grid_x": 114, + "grid_y": 122, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y87": { + "bits": {}, + "grid_x": 114, + "grid_y": 121, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y88": { + "bits": {}, + "grid_x": 114, + "grid_y": 120, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y89": { + "bits": {}, + "grid_x": 114, + "grid_y": 119, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y9": { + "bits": {}, + "grid_x": 114, + "grid_y": 199, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y90": { + "bits": {}, + "grid_x": 114, + "grid_y": 118, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y91": { + "bits": {}, + "grid_x": 114, + "grid_y": 117, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y92": { + "bits": {}, + "grid_x": 114, + "grid_y": 116, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y93": { + "bits": {}, + "grid_x": 114, + "grid_y": 115, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y94": { + "bits": {}, + "grid_x": 114, + "grid_y": 114, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y95": { + "bits": {}, + "grid_x": 114, + "grid_y": 113, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y96": { + "bits": {}, + "grid_x": 114, + "grid_y": 112, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y97": { + "bits": {}, + "grid_x": 114, + "grid_y": 111, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y98": { + "bits": {}, + "grid_x": 114, + "grid_y": 110, + "sites": {}, + "type": "R_TERM_INT" + }, + "R_TERM_INT_X114Y99": { + "bits": {}, + "grid_x": 114, + "grid_y": 109, + "sites": {}, + "type": "R_TERM_INT" + }, + "TERM_CMT_X108Y0": { + "bits": {}, + "grid_x": 108, + "grid_y": 208, + "sites": {}, + "type": "TERM_CMT" + }, + "TERM_CMT_X8Y0": { + "bits": {}, + "grid_x": 8, + "grid_y": 208, + "sites": {}, + "type": "TERM_CMT" + }, + "TERM_CMT_X8Y208": { + "bits": {}, + "grid_x": 8, + "grid_y": 0, + "sites": {}, + "type": "TERM_CMT" + }, + "T_TERM_INT_X11Y208": { + "bits": {}, + "grid_x": 11, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X12Y208": { + "bits": {}, + "grid_x": 12, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X15Y208": { + "bits": {}, + "grid_x": 15, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X16Y208": { + "bits": {}, + "grid_x": 16, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X21Y208": { + "bits": {}, + "grid_x": 21, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X22Y208": { + "bits": {}, + "grid_x": 22, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X25Y208": { + "bits": {}, + "grid_x": 25, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X26Y208": { + "bits": {}, + "grid_x": 26, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X31Y208": { + "bits": {}, + "grid_x": 31, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X32Y208": { + "bits": {}, + "grid_x": 32, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X35Y208": { + "bits": {}, + "grid_x": 35, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X36Y208": { + "bits": {}, + "grid_x": 36, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X41Y208": { + "bits": {}, + "grid_x": 41, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X42Y208": { + "bits": {}, + "grid_x": 42, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X45Y208": { + "bits": {}, + "grid_x": 45, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X46Y208": { + "bits": {}, + "grid_x": 46, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X4Y208": { + "bits": {}, + "grid_x": 4, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X51Y208": { + "bits": {}, + "grid_x": 51, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X52Y208": { + "bits": {}, + "grid_x": 52, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X55Y208": { + "bits": {}, + "grid_x": 55, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X56Y208": { + "bits": {}, + "grid_x": 56, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X59Y208": { + "bits": {}, + "grid_x": 59, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X5Y208": { + "bits": {}, + "grid_x": 5, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X60Y208": { + "bits": {}, + "grid_x": 60, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X64Y208": { + "bits": {}, + "grid_x": 64, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X65Y208": { + "bits": {}, + "grid_x": 65, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X70Y208": { + "bits": {}, + "grid_x": 70, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X71Y208": { + "bits": {}, + "grid_x": 71, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X74Y208": { + "bits": {}, + "grid_x": 74, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X75Y208": { + "bits": {}, + "grid_x": 75, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X79Y208": { + "bits": {}, + "grid_x": 79, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X80Y208": { + "bits": {}, + "grid_x": 80, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X84Y208": { + "bits": {}, + "grid_x": 84, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X85Y208": { + "bits": {}, + "grid_x": 85, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X89Y208": { + "bits": {}, + "grid_x": 89, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X90Y208": { + "bits": {}, + "grid_x": 90, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X94Y208": { + "bits": {}, + "grid_x": 94, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "T_TERM_INT_X95Y208": { + "bits": {}, + "grid_x": 95, + "grid_y": 0, + "sites": {}, + "type": "T_TERM_INT" + }, + "VBRK_EXT_X98Y105": { + "bits": {}, + "grid_x": 98, + "grid_y": 103, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y106": { + "bits": {}, + "grid_x": 98, + "grid_y": 102, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y107": { + "bits": {}, + "grid_x": 98, + "grid_y": 101, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y108": { + "bits": {}, + "grid_x": 98, + "grid_y": 100, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y109": { + "bits": {}, + "grid_x": 98, + "grid_y": 99, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y110": { + "bits": {}, + "grid_x": 98, + "grid_y": 98, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y111": { + "bits": {}, + "grid_x": 98, + "grid_y": 97, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y112": { + "bits": {}, + "grid_x": 98, + "grid_y": 96, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y113": { + "bits": {}, + "grid_x": 98, + "grid_y": 95, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y114": { + "bits": {}, + "grid_x": 98, + "grid_y": 94, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y115": { + "bits": {}, + "grid_x": 98, + "grid_y": 93, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y116": { + "bits": {}, + "grid_x": 98, + "grid_y": 92, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y117": { + "bits": {}, + "grid_x": 98, + "grid_y": 91, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y118": { + "bits": {}, + "grid_x": 98, + "grid_y": 90, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y119": { + "bits": {}, + "grid_x": 98, + "grid_y": 89, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y120": { + "bits": {}, + "grid_x": 98, + "grid_y": 88, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y121": { + "bits": {}, + "grid_x": 98, + "grid_y": 87, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y122": { + "bits": {}, + "grid_x": 98, + "grid_y": 86, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y123": { + "bits": {}, + "grid_x": 98, + "grid_y": 85, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y124": { + "bits": {}, + "grid_x": 98, + "grid_y": 84, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y125": { + "bits": {}, + "grid_x": 98, + "grid_y": 83, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y126": { + "bits": {}, + "grid_x": 98, + "grid_y": 82, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y127": { + "bits": {}, + "grid_x": 98, + "grid_y": 81, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y128": { + "bits": {}, + "grid_x": 98, + "grid_y": 80, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y129": { + "bits": {}, + "grid_x": 98, + "grid_y": 79, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y131": { + "bits": {}, + "grid_x": 98, + "grid_y": 77, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y132": { + "bits": {}, + "grid_x": 98, + "grid_y": 76, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y133": { + "bits": {}, + "grid_x": 98, + "grid_y": 75, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y134": { + "bits": {}, + "grid_x": 98, + "grid_y": 74, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y135": { + "bits": {}, + "grid_x": 98, + "grid_y": 73, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y136": { + "bits": {}, + "grid_x": 98, + "grid_y": 72, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y137": { + "bits": {}, + "grid_x": 98, + "grid_y": 71, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y138": { + "bits": {}, + "grid_x": 98, + "grid_y": 70, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y139": { + "bits": {}, + "grid_x": 98, + "grid_y": 69, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y140": { + "bits": {}, + "grid_x": 98, + "grid_y": 68, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y141": { + "bits": {}, + "grid_x": 98, + "grid_y": 67, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y142": { + "bits": {}, + "grid_x": 98, + "grid_y": 66, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y143": { + "bits": {}, + "grid_x": 98, + "grid_y": 65, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y144": { + "bits": {}, + "grid_x": 98, + "grid_y": 64, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y145": { + "bits": {}, + "grid_x": 98, + "grid_y": 63, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y146": { + "bits": {}, + "grid_x": 98, + "grid_y": 62, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y147": { + "bits": {}, + "grid_x": 98, + "grid_y": 61, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y148": { + "bits": {}, + "grid_x": 98, + "grid_y": 60, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y149": { + "bits": {}, + "grid_x": 98, + "grid_y": 59, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y150": { + "bits": {}, + "grid_x": 98, + "grid_y": 58, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y151": { + "bits": {}, + "grid_x": 98, + "grid_y": 57, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y152": { + "bits": {}, + "grid_x": 98, + "grid_y": 56, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y153": { + "bits": {}, + "grid_x": 98, + "grid_y": 55, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y154": { + "bits": {}, + "grid_x": 98, + "grid_y": 54, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y155": { + "bits": {}, + "grid_x": 98, + "grid_y": 53, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y157": { + "bits": {}, + "grid_x": 98, + "grid_y": 51, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y158": { + "bits": {}, + "grid_x": 98, + "grid_y": 50, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y159": { + "bits": {}, + "grid_x": 98, + "grid_y": 49, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y160": { + "bits": {}, + "grid_x": 98, + "grid_y": 48, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y161": { + "bits": {}, + "grid_x": 98, + "grid_y": 47, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y162": { + "bits": {}, + "grid_x": 98, + "grid_y": 46, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y163": { + "bits": {}, + "grid_x": 98, + "grid_y": 45, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y164": { + "bits": {}, + "grid_x": 98, + "grid_y": 44, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y165": { + "bits": {}, + "grid_x": 98, + "grid_y": 43, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y166": { + "bits": {}, + "grid_x": 98, + "grid_y": 42, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y167": { + "bits": {}, + "grid_x": 98, + "grid_y": 41, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y168": { + "bits": {}, + "grid_x": 98, + "grid_y": 40, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y169": { + "bits": {}, + "grid_x": 98, + "grid_y": 39, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y170": { + "bits": {}, + "grid_x": 98, + "grid_y": 38, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y171": { + "bits": {}, + "grid_x": 98, + "grid_y": 37, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y172": { + "bits": {}, + "grid_x": 98, + "grid_y": 36, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y173": { + "bits": {}, + "grid_x": 98, + "grid_y": 35, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y174": { + "bits": {}, + "grid_x": 98, + "grid_y": 34, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y175": { + "bits": {}, + "grid_x": 98, + "grid_y": 33, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y176": { + "bits": {}, + "grid_x": 98, + "grid_y": 32, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y177": { + "bits": {}, + "grid_x": 98, + "grid_y": 31, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y178": { + "bits": {}, + "grid_x": 98, + "grid_y": 30, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y179": { + "bits": {}, + "grid_x": 98, + "grid_y": 29, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y180": { + "bits": {}, + "grid_x": 98, + "grid_y": 28, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y181": { + "bits": {}, + "grid_x": 98, + "grid_y": 27, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y183": { + "bits": {}, + "grid_x": 98, + "grid_y": 25, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y184": { + "bits": {}, + "grid_x": 98, + "grid_y": 24, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y185": { + "bits": {}, + "grid_x": 98, + "grid_y": 23, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y186": { + "bits": {}, + "grid_x": 98, + "grid_y": 22, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y187": { + "bits": {}, + "grid_x": 98, + "grid_y": 21, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y188": { + "bits": {}, + "grid_x": 98, + "grid_y": 20, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y189": { + "bits": {}, + "grid_x": 98, + "grid_y": 19, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y190": { + "bits": {}, + "grid_x": 98, + "grid_y": 18, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y191": { + "bits": {}, + "grid_x": 98, + "grid_y": 17, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y192": { + "bits": {}, + "grid_x": 98, + "grid_y": 16, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y193": { + "bits": {}, + "grid_x": 98, + "grid_y": 15, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y194": { + "bits": {}, + "grid_x": 98, + "grid_y": 14, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y195": { + "bits": {}, + "grid_x": 98, + "grid_y": 13, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y196": { + "bits": {}, + "grid_x": 98, + "grid_y": 12, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y197": { + "bits": {}, + "grid_x": 98, + "grid_y": 11, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y198": { + "bits": {}, + "grid_x": 98, + "grid_y": 10, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y199": { + "bits": {}, + "grid_x": 98, + "grid_y": 9, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y200": { + "bits": {}, + "grid_x": 98, + "grid_y": 8, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y201": { + "bits": {}, + "grid_x": 98, + "grid_y": 7, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y202": { + "bits": {}, + "grid_x": 98, + "grid_y": 6, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y203": { + "bits": {}, + "grid_x": 98, + "grid_y": 5, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y204": { + "bits": {}, + "grid_x": 98, + "grid_y": 4, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y205": { + "bits": {}, + "grid_x": 98, + "grid_y": 3, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y206": { + "bits": {}, + "grid_x": 98, + "grid_y": 2, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_EXT_X98Y207": { + "bits": {}, + "grid_x": 98, + "grid_y": 1, + "sites": {}, + "type": "VBRK_EXT" + }, + "VBRK_X107Y1": { + "bits": {}, + "grid_x": 107, + "grid_y": 207, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y10": { + "bits": {}, + "grid_x": 107, + "grid_y": 198, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y100": { + "bits": {}, + "grid_x": 107, + "grid_y": 108, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y101": { + "bits": {}, + "grid_x": 107, + "grid_y": 107, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y102": { + "bits": {}, + "grid_x": 107, + "grid_y": 106, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y103": { + "bits": {}, + "grid_x": 107, + "grid_y": 105, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y11": { + "bits": {}, + "grid_x": 107, + "grid_y": 197, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y12": { + "bits": {}, + "grid_x": 107, + "grid_y": 196, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y13": { + "bits": {}, + "grid_x": 107, + "grid_y": 195, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y14": { + "bits": {}, + "grid_x": 107, + "grid_y": 194, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y15": { + "bits": {}, + "grid_x": 107, + "grid_y": 193, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y16": { + "bits": {}, + "grid_x": 107, + "grid_y": 192, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y17": { + "bits": {}, + "grid_x": 107, + "grid_y": 191, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y18": { + "bits": {}, + "grid_x": 107, + "grid_y": 190, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y19": { + "bits": {}, + "grid_x": 107, + "grid_y": 189, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y2": { + "bits": {}, + "grid_x": 107, + "grid_y": 206, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y20": { + "bits": {}, + "grid_x": 107, + "grid_y": 188, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y21": { + "bits": {}, + "grid_x": 107, + "grid_y": 187, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y22": { + "bits": {}, + "grid_x": 107, + "grid_y": 186, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y23": { + "bits": {}, + "grid_x": 107, + "grid_y": 185, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y24": { + "bits": {}, + "grid_x": 107, + "grid_y": 184, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y25": { + "bits": {}, + "grid_x": 107, + "grid_y": 183, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y27": { + "bits": {}, + "grid_x": 107, + "grid_y": 181, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y28": { + "bits": {}, + "grid_x": 107, + "grid_y": 180, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y29": { + "bits": {}, + "grid_x": 107, + "grid_y": 179, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y3": { + "bits": {}, + "grid_x": 107, + "grid_y": 205, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y30": { + "bits": {}, + "grid_x": 107, + "grid_y": 178, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y31": { + "bits": {}, + "grid_x": 107, + "grid_y": 177, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y32": { + "bits": {}, + "grid_x": 107, + "grid_y": 176, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y33": { + "bits": {}, + "grid_x": 107, + "grid_y": 175, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y34": { + "bits": {}, + "grid_x": 107, + "grid_y": 174, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y35": { + "bits": {}, + "grid_x": 107, + "grid_y": 173, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y36": { + "bits": {}, + "grid_x": 107, + "grid_y": 172, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y37": { + "bits": {}, + "grid_x": 107, + "grid_y": 171, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y38": { + "bits": {}, + "grid_x": 107, + "grid_y": 170, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y39": { + "bits": {}, + "grid_x": 107, + "grid_y": 169, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y4": { + "bits": {}, + "grid_x": 107, + "grid_y": 204, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y40": { + "bits": {}, + "grid_x": 107, + "grid_y": 168, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y41": { + "bits": {}, + "grid_x": 107, + "grid_y": 167, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y42": { + "bits": {}, + "grid_x": 107, + "grid_y": 166, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y43": { + "bits": {}, + "grid_x": 107, + "grid_y": 165, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y44": { + "bits": {}, + "grid_x": 107, + "grid_y": 164, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y45": { + "bits": {}, + "grid_x": 107, + "grid_y": 163, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y46": { + "bits": {}, + "grid_x": 107, + "grid_y": 162, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y47": { + "bits": {}, + "grid_x": 107, + "grid_y": 161, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y48": { + "bits": {}, + "grid_x": 107, + "grid_y": 160, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y49": { + "bits": {}, + "grid_x": 107, + "grid_y": 159, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y5": { + "bits": {}, + "grid_x": 107, + "grid_y": 203, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y50": { + "bits": {}, + "grid_x": 107, + "grid_y": 158, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y51": { + "bits": {}, + "grid_x": 107, + "grid_y": 157, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y53": { + "bits": {}, + "grid_x": 107, + "grid_y": 155, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y54": { + "bits": {}, + "grid_x": 107, + "grid_y": 154, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y55": { + "bits": {}, + "grid_x": 107, + "grid_y": 153, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y56": { + "bits": {}, + "grid_x": 107, + "grid_y": 152, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y57": { + "bits": {}, + "grid_x": 107, + "grid_y": 151, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y58": { + "bits": {}, + "grid_x": 107, + "grid_y": 150, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y59": { + "bits": {}, + "grid_x": 107, + "grid_y": 149, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y6": { + "bits": {}, + "grid_x": 107, + "grid_y": 202, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y60": { + "bits": {}, + "grid_x": 107, + "grid_y": 148, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y61": { + "bits": {}, + "grid_x": 107, + "grid_y": 147, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y62": { + "bits": {}, + "grid_x": 107, + "grid_y": 146, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y63": { + "bits": {}, + "grid_x": 107, + "grid_y": 145, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y64": { + "bits": {}, + "grid_x": 107, + "grid_y": 144, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y65": { + "bits": {}, + "grid_x": 107, + "grid_y": 143, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y66": { + "bits": {}, + "grid_x": 107, + "grid_y": 142, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y67": { + "bits": {}, + "grid_x": 107, + "grid_y": 141, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y68": { + "bits": {}, + "grid_x": 107, + "grid_y": 140, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y69": { + "bits": {}, + "grid_x": 107, + "grid_y": 139, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y7": { + "bits": {}, + "grid_x": 107, + "grid_y": 201, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y70": { + "bits": {}, + "grid_x": 107, + "grid_y": 138, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y71": { + "bits": {}, + "grid_x": 107, + "grid_y": 137, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y72": { + "bits": {}, + "grid_x": 107, + "grid_y": 136, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y73": { + "bits": {}, + "grid_x": 107, + "grid_y": 135, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y74": { + "bits": {}, + "grid_x": 107, + "grid_y": 134, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y75": { + "bits": {}, + "grid_x": 107, + "grid_y": 133, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y76": { + "bits": {}, + "grid_x": 107, + "grid_y": 132, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y77": { + "bits": {}, + "grid_x": 107, + "grid_y": 131, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y79": { + "bits": {}, + "grid_x": 107, + "grid_y": 129, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y8": { + "bits": {}, + "grid_x": 107, + "grid_y": 200, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y80": { + "bits": {}, + "grid_x": 107, + "grid_y": 128, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y81": { + "bits": {}, + "grid_x": 107, + "grid_y": 127, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y82": { + "bits": {}, + "grid_x": 107, + "grid_y": 126, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y83": { + "bits": {}, + "grid_x": 107, + "grid_y": 125, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y84": { + "bits": {}, + "grid_x": 107, + "grid_y": 124, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y85": { + "bits": {}, + "grid_x": 107, + "grid_y": 123, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y86": { + "bits": {}, + "grid_x": 107, + "grid_y": 122, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y87": { + "bits": {}, + "grid_x": 107, + "grid_y": 121, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y88": { + "bits": {}, + "grid_x": 107, + "grid_y": 120, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y89": { + "bits": {}, + "grid_x": 107, + "grid_y": 119, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y9": { + "bits": {}, + "grid_x": 107, + "grid_y": 199, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y90": { + "bits": {}, + "grid_x": 107, + "grid_y": 118, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y91": { + "bits": {}, + "grid_x": 107, + "grid_y": 117, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y92": { + "bits": {}, + "grid_x": 107, + "grid_y": 116, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y93": { + "bits": {}, + "grid_x": 107, + "grid_y": 115, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y94": { + "bits": {}, + "grid_x": 107, + "grid_y": 114, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y95": { + "bits": {}, + "grid_x": 107, + "grid_y": 113, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y96": { + "bits": {}, + "grid_x": 107, + "grid_y": 112, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y97": { + "bits": {}, + "grid_x": 107, + "grid_y": 111, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y98": { + "bits": {}, + "grid_x": 107, + "grid_y": 110, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X107Y99": { + "bits": {}, + "grid_x": 107, + "grid_y": 109, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y1": { + "bits": {}, + "grid_x": 18, + "grid_y": 207, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y10": { + "bits": {}, + "grid_x": 18, + "grid_y": 198, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y100": { + "bits": {}, + "grid_x": 18, + "grid_y": 108, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y101": { + "bits": {}, + "grid_x": 18, + "grid_y": 107, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y102": { + "bits": {}, + "grid_x": 18, + "grid_y": 106, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y103": { + "bits": {}, + "grid_x": 18, + "grid_y": 105, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y105": { + "bits": {}, + "grid_x": 18, + "grid_y": 103, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y106": { + "bits": {}, + "grid_x": 18, + "grid_y": 102, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y107": { + "bits": {}, + "grid_x": 18, + "grid_y": 101, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y108": { + "bits": {}, + "grid_x": 18, + "grid_y": 100, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y109": { + "bits": {}, + "grid_x": 18, + "grid_y": 99, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y11": { + "bits": {}, + "grid_x": 18, + "grid_y": 197, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y110": { + "bits": {}, + "grid_x": 18, + "grid_y": 98, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y111": { + "bits": {}, + "grid_x": 18, + "grid_y": 97, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y112": { + "bits": {}, + "grid_x": 18, + "grid_y": 96, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y113": { + "bits": {}, + "grid_x": 18, + "grid_y": 95, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y114": { + "bits": {}, + "grid_x": 18, + "grid_y": 94, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y115": { + "bits": {}, + "grid_x": 18, + "grid_y": 93, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y116": { + "bits": {}, + "grid_x": 18, + "grid_y": 92, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y117": { + "bits": {}, + "grid_x": 18, + "grid_y": 91, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y118": { + "bits": {}, + "grid_x": 18, + "grid_y": 90, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y119": { + "bits": {}, + "grid_x": 18, + "grid_y": 89, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y12": { + "bits": {}, + "grid_x": 18, + "grid_y": 196, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y120": { + "bits": {}, + "grid_x": 18, + "grid_y": 88, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y121": { + "bits": {}, + "grid_x": 18, + "grid_y": 87, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y122": { + "bits": {}, + "grid_x": 18, + "grid_y": 86, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y123": { + "bits": {}, + "grid_x": 18, + "grid_y": 85, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y124": { + "bits": {}, + "grid_x": 18, + "grid_y": 84, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y125": { + "bits": {}, + "grid_x": 18, + "grid_y": 83, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y126": { + "bits": {}, + "grid_x": 18, + "grid_y": 82, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y127": { + "bits": {}, + "grid_x": 18, + "grid_y": 81, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y128": { + "bits": {}, + "grid_x": 18, + "grid_y": 80, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y129": { + "bits": {}, + "grid_x": 18, + "grid_y": 79, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y13": { + "bits": {}, + "grid_x": 18, + "grid_y": 195, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y131": { + "bits": {}, + "grid_x": 18, + "grid_y": 77, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y132": { + "bits": {}, + "grid_x": 18, + "grid_y": 76, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y133": { + "bits": {}, + "grid_x": 18, + "grid_y": 75, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y134": { + "bits": {}, + "grid_x": 18, + "grid_y": 74, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y135": { + "bits": {}, + "grid_x": 18, + "grid_y": 73, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y136": { + "bits": {}, + "grid_x": 18, + "grid_y": 72, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y137": { + "bits": {}, + "grid_x": 18, + "grid_y": 71, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y138": { + "bits": {}, + "grid_x": 18, + "grid_y": 70, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y139": { + "bits": {}, + "grid_x": 18, + "grid_y": 69, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y14": { + "bits": {}, + "grid_x": 18, + "grid_y": 194, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y140": { + "bits": {}, + "grid_x": 18, + "grid_y": 68, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y141": { + "bits": {}, + "grid_x": 18, + "grid_y": 67, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y142": { + "bits": {}, + "grid_x": 18, + "grid_y": 66, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y143": { + "bits": {}, + "grid_x": 18, + "grid_y": 65, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y144": { + "bits": {}, + "grid_x": 18, + "grid_y": 64, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y145": { + "bits": {}, + "grid_x": 18, + "grid_y": 63, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y146": { + "bits": {}, + "grid_x": 18, + "grid_y": 62, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y147": { + "bits": {}, + "grid_x": 18, + "grid_y": 61, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y148": { + "bits": {}, + "grid_x": 18, + "grid_y": 60, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y149": { + "bits": {}, + "grid_x": 18, + "grid_y": 59, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y15": { + "bits": {}, + "grid_x": 18, + "grid_y": 193, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y150": { + "bits": {}, + "grid_x": 18, + "grid_y": 58, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y151": { + "bits": {}, + "grid_x": 18, + "grid_y": 57, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y152": { + "bits": {}, + "grid_x": 18, + "grid_y": 56, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y153": { + "bits": {}, + "grid_x": 18, + "grid_y": 55, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y154": { + "bits": {}, + "grid_x": 18, + "grid_y": 54, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y155": { + "bits": {}, + "grid_x": 18, + "grid_y": 53, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y157": { + "bits": {}, + "grid_x": 18, + "grid_y": 51, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y158": { + "bits": {}, + "grid_x": 18, + "grid_y": 50, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y159": { + "bits": {}, + "grid_x": 18, + "grid_y": 49, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y16": { + "bits": {}, + "grid_x": 18, + "grid_y": 192, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y160": { + "bits": {}, + "grid_x": 18, + "grid_y": 48, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y161": { + "bits": {}, + "grid_x": 18, + "grid_y": 47, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y162": { + "bits": {}, + "grid_x": 18, + "grid_y": 46, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y163": { + "bits": {}, + "grid_x": 18, + "grid_y": 45, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y164": { + "bits": {}, + "grid_x": 18, + "grid_y": 44, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y165": { + "bits": {}, + "grid_x": 18, + "grid_y": 43, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y166": { + "bits": {}, + "grid_x": 18, + "grid_y": 42, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y167": { + "bits": {}, + "grid_x": 18, + "grid_y": 41, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y168": { + "bits": {}, + "grid_x": 18, + "grid_y": 40, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y169": { + "bits": {}, + "grid_x": 18, + "grid_y": 39, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y17": { + "bits": {}, + "grid_x": 18, + "grid_y": 191, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y170": { + "bits": {}, + "grid_x": 18, + "grid_y": 38, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y171": { + "bits": {}, + "grid_x": 18, + "grid_y": 37, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y172": { + "bits": {}, + "grid_x": 18, + "grid_y": 36, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y173": { + "bits": {}, + "grid_x": 18, + "grid_y": 35, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y174": { + "bits": {}, + "grid_x": 18, + "grid_y": 34, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y175": { + "bits": {}, + "grid_x": 18, + "grid_y": 33, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y176": { + "bits": {}, + "grid_x": 18, + "grid_y": 32, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y177": { + "bits": {}, + "grid_x": 18, + "grid_y": 31, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y178": { + "bits": {}, + "grid_x": 18, + "grid_y": 30, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y179": { + "bits": {}, + "grid_x": 18, + "grid_y": 29, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y18": { + "bits": {}, + "grid_x": 18, + "grid_y": 190, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y180": { + "bits": {}, + "grid_x": 18, + "grid_y": 28, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y181": { + "bits": {}, + "grid_x": 18, + "grid_y": 27, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y183": { + "bits": {}, + "grid_x": 18, + "grid_y": 25, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y184": { + "bits": {}, + "grid_x": 18, + "grid_y": 24, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y185": { + "bits": {}, + "grid_x": 18, + "grid_y": 23, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y186": { + "bits": {}, + "grid_x": 18, + "grid_y": 22, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y187": { + "bits": {}, + "grid_x": 18, + "grid_y": 21, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y188": { + "bits": {}, + "grid_x": 18, + "grid_y": 20, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y189": { + "bits": {}, + "grid_x": 18, + "grid_y": 19, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y19": { + "bits": {}, + "grid_x": 18, + "grid_y": 189, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y190": { + "bits": {}, + "grid_x": 18, + "grid_y": 18, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y191": { + "bits": {}, + "grid_x": 18, + "grid_y": 17, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y192": { + "bits": {}, + "grid_x": 18, + "grid_y": 16, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y193": { + "bits": {}, + "grid_x": 18, + "grid_y": 15, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y194": { + "bits": {}, + "grid_x": 18, + "grid_y": 14, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y195": { + "bits": {}, + "grid_x": 18, + "grid_y": 13, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y196": { + "bits": {}, + "grid_x": 18, + "grid_y": 12, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y197": { + "bits": {}, + "grid_x": 18, + "grid_y": 11, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y198": { + "bits": {}, + "grid_x": 18, + "grid_y": 10, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y199": { + "bits": {}, + "grid_x": 18, + "grid_y": 9, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y2": { + "bits": {}, + "grid_x": 18, + "grid_y": 206, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y20": { + "bits": {}, + "grid_x": 18, + "grid_y": 188, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y200": { + "bits": {}, + "grid_x": 18, + "grid_y": 8, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y201": { + "bits": {}, + "grid_x": 18, + "grid_y": 7, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y202": { + "bits": {}, + "grid_x": 18, + "grid_y": 6, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y203": { + "bits": {}, + "grid_x": 18, + "grid_y": 5, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y204": { + "bits": {}, + "grid_x": 18, + "grid_y": 4, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y205": { + "bits": {}, + "grid_x": 18, + "grid_y": 3, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y206": { + "bits": {}, + "grid_x": 18, + "grid_y": 2, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y207": { + "bits": {}, + "grid_x": 18, + "grid_y": 1, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y21": { + "bits": {}, + "grid_x": 18, + "grid_y": 187, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y22": { + "bits": {}, + "grid_x": 18, + "grid_y": 186, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y23": { + "bits": {}, + "grid_x": 18, + "grid_y": 185, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y24": { + "bits": {}, + "grid_x": 18, + "grid_y": 184, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y25": { + "bits": {}, + "grid_x": 18, + "grid_y": 183, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y27": { + "bits": {}, + "grid_x": 18, + "grid_y": 181, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y28": { + "bits": {}, + "grid_x": 18, + "grid_y": 180, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y29": { + "bits": {}, + "grid_x": 18, + "grid_y": 179, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y3": { + "bits": {}, + "grid_x": 18, + "grid_y": 205, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y30": { + "bits": {}, + "grid_x": 18, + "grid_y": 178, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y31": { + "bits": {}, + "grid_x": 18, + "grid_y": 177, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y32": { + "bits": {}, + "grid_x": 18, + "grid_y": 176, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y33": { + "bits": {}, + "grid_x": 18, + "grid_y": 175, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y34": { + "bits": {}, + "grid_x": 18, + "grid_y": 174, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y35": { + "bits": {}, + "grid_x": 18, + "grid_y": 173, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y36": { + "bits": {}, + "grid_x": 18, + "grid_y": 172, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y37": { + "bits": {}, + "grid_x": 18, + "grid_y": 171, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y38": { + "bits": {}, + "grid_x": 18, + "grid_y": 170, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y39": { + "bits": {}, + "grid_x": 18, + "grid_y": 169, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y4": { + "bits": {}, + "grid_x": 18, + "grid_y": 204, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y40": { + "bits": {}, + "grid_x": 18, + "grid_y": 168, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y41": { + "bits": {}, + "grid_x": 18, + "grid_y": 167, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y42": { + "bits": {}, + "grid_x": 18, + "grid_y": 166, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y43": { + "bits": {}, + "grid_x": 18, + "grid_y": 165, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y44": { + "bits": {}, + "grid_x": 18, + "grid_y": 164, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y45": { + "bits": {}, + "grid_x": 18, + "grid_y": 163, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y46": { + "bits": {}, + "grid_x": 18, + "grid_y": 162, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y47": { + "bits": {}, + "grid_x": 18, + "grid_y": 161, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y48": { + "bits": {}, + "grid_x": 18, + "grid_y": 160, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y49": { + "bits": {}, + "grid_x": 18, + "grid_y": 159, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y5": { + "bits": {}, + "grid_x": 18, + "grid_y": 203, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y50": { + "bits": {}, + "grid_x": 18, + "grid_y": 158, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y51": { + "bits": {}, + "grid_x": 18, + "grid_y": 157, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y53": { + "bits": {}, + "grid_x": 18, + "grid_y": 155, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y54": { + "bits": {}, + "grid_x": 18, + "grid_y": 154, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y55": { + "bits": {}, + "grid_x": 18, + "grid_y": 153, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y56": { + "bits": {}, + "grid_x": 18, + "grid_y": 152, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y57": { + "bits": {}, + "grid_x": 18, + "grid_y": 151, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y58": { + "bits": {}, + "grid_x": 18, + "grid_y": 150, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y59": { + "bits": {}, + "grid_x": 18, + "grid_y": 149, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y6": { + "bits": {}, + "grid_x": 18, + "grid_y": 202, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y60": { + "bits": {}, + "grid_x": 18, + "grid_y": 148, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y61": { + "bits": {}, + "grid_x": 18, + "grid_y": 147, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y62": { + "bits": {}, + "grid_x": 18, + "grid_y": 146, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y63": { + "bits": {}, + "grid_x": 18, + "grid_y": 145, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y64": { + "bits": {}, + "grid_x": 18, + "grid_y": 144, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y65": { + "bits": {}, + "grid_x": 18, + "grid_y": 143, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y66": { + "bits": {}, + "grid_x": 18, + "grid_y": 142, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y67": { + "bits": {}, + "grid_x": 18, + "grid_y": 141, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y68": { + "bits": {}, + "grid_x": 18, + "grid_y": 140, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y69": { + "bits": {}, + "grid_x": 18, + "grid_y": 139, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y7": { + "bits": {}, + "grid_x": 18, + "grid_y": 201, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y70": { + "bits": {}, + "grid_x": 18, + "grid_y": 138, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y71": { + "bits": {}, + "grid_x": 18, + "grid_y": 137, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y72": { + "bits": {}, + "grid_x": 18, + "grid_y": 136, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y73": { + "bits": {}, + "grid_x": 18, + "grid_y": 135, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y74": { + "bits": {}, + "grid_x": 18, + "grid_y": 134, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y75": { + "bits": {}, + "grid_x": 18, + "grid_y": 133, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y76": { + "bits": {}, + "grid_x": 18, + "grid_y": 132, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y77": { + "bits": {}, + "grid_x": 18, + "grid_y": 131, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y79": { + "bits": {}, + "grid_x": 18, + "grid_y": 129, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y8": { + "bits": {}, + "grid_x": 18, + "grid_y": 200, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y80": { + "bits": {}, + "grid_x": 18, + "grid_y": 128, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y81": { + "bits": {}, + "grid_x": 18, + "grid_y": 127, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y82": { + "bits": {}, + "grid_x": 18, + "grid_y": 126, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y83": { + "bits": {}, + "grid_x": 18, + "grid_y": 125, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y84": { + "bits": {}, + "grid_x": 18, + "grid_y": 124, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y85": { + "bits": {}, + "grid_x": 18, + "grid_y": 123, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y86": { + "bits": {}, + "grid_x": 18, + "grid_y": 122, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y87": { + "bits": {}, + "grid_x": 18, + "grid_y": 121, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y88": { + "bits": {}, + "grid_x": 18, + "grid_y": 120, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y89": { + "bits": {}, + "grid_x": 18, + "grid_y": 119, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y9": { + "bits": {}, + "grid_x": 18, + "grid_y": 199, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y90": { + "bits": {}, + "grid_x": 18, + "grid_y": 118, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y91": { + "bits": {}, + "grid_x": 18, + "grid_y": 117, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y92": { + "bits": {}, + "grid_x": 18, + "grid_y": 116, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y93": { + "bits": {}, + "grid_x": 18, + "grid_y": 115, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y94": { + "bits": {}, + "grid_x": 18, + "grid_y": 114, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y95": { + "bits": {}, + "grid_x": 18, + "grid_y": 113, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y96": { + "bits": {}, + "grid_x": 18, + "grid_y": 112, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y97": { + "bits": {}, + "grid_x": 18, + "grid_y": 111, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y98": { + "bits": {}, + "grid_x": 18, + "grid_y": 110, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X18Y99": { + "bits": {}, + "grid_x": 18, + "grid_y": 109, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y1": { + "bits": {}, + "grid_x": 29, + "grid_y": 207, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y10": { + "bits": {}, + "grid_x": 29, + "grid_y": 198, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y100": { + "bits": {}, + "grid_x": 29, + "grid_y": 108, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y101": { + "bits": {}, + "grid_x": 29, + "grid_y": 107, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y102": { + "bits": {}, + "grid_x": 29, + "grid_y": 106, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y103": { + "bits": {}, + "grid_x": 29, + "grid_y": 105, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y105": { + "bits": {}, + "grid_x": 29, + "grid_y": 103, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y106": { + "bits": {}, + "grid_x": 29, + "grid_y": 102, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y107": { + "bits": {}, + "grid_x": 29, + "grid_y": 101, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y108": { + "bits": {}, + "grid_x": 29, + "grid_y": 100, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y109": { + "bits": {}, + "grid_x": 29, + "grid_y": 99, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y11": { + "bits": {}, + "grid_x": 29, + "grid_y": 197, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y110": { + "bits": {}, + "grid_x": 29, + "grid_y": 98, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y111": { + "bits": {}, + "grid_x": 29, + "grid_y": 97, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y112": { + "bits": {}, + "grid_x": 29, + "grid_y": 96, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y113": { + "bits": {}, + "grid_x": 29, + "grid_y": 95, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y114": { + "bits": {}, + "grid_x": 29, + "grid_y": 94, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y115": { + "bits": {}, + "grid_x": 29, + "grid_y": 93, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y116": { + "bits": {}, + "grid_x": 29, + "grid_y": 92, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y117": { + "bits": {}, + "grid_x": 29, + "grid_y": 91, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y118": { + "bits": {}, + "grid_x": 29, + "grid_y": 90, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y119": { + "bits": {}, + "grid_x": 29, + "grid_y": 89, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y12": { + "bits": {}, + "grid_x": 29, + "grid_y": 196, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y120": { + "bits": {}, + "grid_x": 29, + "grid_y": 88, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y121": { + "bits": {}, + "grid_x": 29, + "grid_y": 87, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y122": { + "bits": {}, + "grid_x": 29, + "grid_y": 86, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y123": { + "bits": {}, + "grid_x": 29, + "grid_y": 85, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y124": { + "bits": {}, + "grid_x": 29, + "grid_y": 84, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y125": { + "bits": {}, + "grid_x": 29, + "grid_y": 83, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y126": { + "bits": {}, + "grid_x": 29, + "grid_y": 82, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y127": { + "bits": {}, + "grid_x": 29, + "grid_y": 81, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y128": { + "bits": {}, + "grid_x": 29, + "grid_y": 80, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y129": { + "bits": {}, + "grid_x": 29, + "grid_y": 79, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y13": { + "bits": {}, + "grid_x": 29, + "grid_y": 195, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y131": { + "bits": {}, + "grid_x": 29, + "grid_y": 77, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y132": { + "bits": {}, + "grid_x": 29, + "grid_y": 76, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y133": { + "bits": {}, + "grid_x": 29, + "grid_y": 75, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y134": { + "bits": {}, + "grid_x": 29, + "grid_y": 74, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y135": { + "bits": {}, + "grid_x": 29, + "grid_y": 73, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y136": { + "bits": {}, + "grid_x": 29, + "grid_y": 72, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y137": { + "bits": {}, + "grid_x": 29, + "grid_y": 71, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y138": { + "bits": {}, + "grid_x": 29, + "grid_y": 70, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y139": { + "bits": {}, + "grid_x": 29, + "grid_y": 69, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y14": { + "bits": {}, + "grid_x": 29, + "grid_y": 194, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y140": { + "bits": {}, + "grid_x": 29, + "grid_y": 68, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y141": { + "bits": {}, + "grid_x": 29, + "grid_y": 67, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y142": { + "bits": {}, + "grid_x": 29, + "grid_y": 66, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y143": { + "bits": {}, + "grid_x": 29, + "grid_y": 65, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y144": { + "bits": {}, + "grid_x": 29, + "grid_y": 64, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y145": { + "bits": {}, + "grid_x": 29, + "grid_y": 63, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y146": { + "bits": {}, + "grid_x": 29, + "grid_y": 62, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y147": { + "bits": {}, + "grid_x": 29, + "grid_y": 61, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y148": { + "bits": {}, + "grid_x": 29, + "grid_y": 60, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y149": { + "bits": {}, + "grid_x": 29, + "grid_y": 59, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y15": { + "bits": {}, + "grid_x": 29, + "grid_y": 193, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y150": { + "bits": {}, + "grid_x": 29, + "grid_y": 58, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y151": { + "bits": {}, + "grid_x": 29, + "grid_y": 57, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y152": { + "bits": {}, + "grid_x": 29, + "grid_y": 56, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y153": { + "bits": {}, + "grid_x": 29, + "grid_y": 55, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y154": { + "bits": {}, + "grid_x": 29, + "grid_y": 54, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y155": { + "bits": {}, + "grid_x": 29, + "grid_y": 53, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y157": { + "bits": {}, + "grid_x": 29, + "grid_y": 51, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y158": { + "bits": {}, + "grid_x": 29, + "grid_y": 50, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y159": { + "bits": {}, + "grid_x": 29, + "grid_y": 49, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y16": { + "bits": {}, + "grid_x": 29, + "grid_y": 192, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y160": { + "bits": {}, + "grid_x": 29, + "grid_y": 48, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y161": { + "bits": {}, + "grid_x": 29, + "grid_y": 47, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y162": { + "bits": {}, + "grid_x": 29, + "grid_y": 46, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y163": { + "bits": {}, + "grid_x": 29, + "grid_y": 45, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y164": { + "bits": {}, + "grid_x": 29, + "grid_y": 44, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y165": { + "bits": {}, + "grid_x": 29, + "grid_y": 43, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y166": { + "bits": {}, + "grid_x": 29, + "grid_y": 42, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y167": { + "bits": {}, + "grid_x": 29, + "grid_y": 41, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y168": { + "bits": {}, + "grid_x": 29, + "grid_y": 40, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y169": { + "bits": {}, + "grid_x": 29, + "grid_y": 39, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y17": { + "bits": {}, + "grid_x": 29, + "grid_y": 191, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y170": { + "bits": {}, + "grid_x": 29, + "grid_y": 38, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y171": { + "bits": {}, + "grid_x": 29, + "grid_y": 37, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y172": { + "bits": {}, + "grid_x": 29, + "grid_y": 36, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y173": { + "bits": {}, + "grid_x": 29, + "grid_y": 35, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y174": { + "bits": {}, + "grid_x": 29, + "grid_y": 34, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y175": { + "bits": {}, + "grid_x": 29, + "grid_y": 33, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y176": { + "bits": {}, + "grid_x": 29, + "grid_y": 32, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y177": { + "bits": {}, + "grid_x": 29, + "grid_y": 31, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y178": { + "bits": {}, + "grid_x": 29, + "grid_y": 30, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y179": { + "bits": {}, + "grid_x": 29, + "grid_y": 29, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y18": { + "bits": {}, + "grid_x": 29, + "grid_y": 190, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y180": { + "bits": {}, + "grid_x": 29, + "grid_y": 28, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y181": { + "bits": {}, + "grid_x": 29, + "grid_y": 27, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y183": { + "bits": {}, + "grid_x": 29, + "grid_y": 25, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y184": { + "bits": {}, + "grid_x": 29, + "grid_y": 24, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y185": { + "bits": {}, + "grid_x": 29, + "grid_y": 23, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y186": { + "bits": {}, + "grid_x": 29, + "grid_y": 22, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y187": { + "bits": {}, + "grid_x": 29, + "grid_y": 21, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y188": { + "bits": {}, + "grid_x": 29, + "grid_y": 20, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y189": { + "bits": {}, + "grid_x": 29, + "grid_y": 19, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y19": { + "bits": {}, + "grid_x": 29, + "grid_y": 189, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y190": { + "bits": {}, + "grid_x": 29, + "grid_y": 18, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y191": { + "bits": {}, + "grid_x": 29, + "grid_y": 17, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y192": { + "bits": {}, + "grid_x": 29, + "grid_y": 16, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y193": { + "bits": {}, + "grid_x": 29, + "grid_y": 15, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y194": { + "bits": {}, + "grid_x": 29, + "grid_y": 14, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y195": { + "bits": {}, + "grid_x": 29, + "grid_y": 13, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y196": { + "bits": {}, + "grid_x": 29, + "grid_y": 12, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y197": { + "bits": {}, + "grid_x": 29, + "grid_y": 11, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y198": { + "bits": {}, + "grid_x": 29, + "grid_y": 10, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y199": { + "bits": {}, + "grid_x": 29, + "grid_y": 9, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y2": { + "bits": {}, + "grid_x": 29, + "grid_y": 206, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y20": { + "bits": {}, + "grid_x": 29, + "grid_y": 188, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y200": { + "bits": {}, + "grid_x": 29, + "grid_y": 8, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y201": { + "bits": {}, + "grid_x": 29, + "grid_y": 7, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y202": { + "bits": {}, + "grid_x": 29, + "grid_y": 6, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y203": { + "bits": {}, + "grid_x": 29, + "grid_y": 5, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y204": { + "bits": {}, + "grid_x": 29, + "grid_y": 4, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y205": { + "bits": {}, + "grid_x": 29, + "grid_y": 3, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y206": { + "bits": {}, + "grid_x": 29, + "grid_y": 2, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y207": { + "bits": {}, + "grid_x": 29, + "grid_y": 1, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y21": { + "bits": {}, + "grid_x": 29, + "grid_y": 187, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y22": { + "bits": {}, + "grid_x": 29, + "grid_y": 186, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y23": { + "bits": {}, + "grid_x": 29, + "grid_y": 185, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y24": { + "bits": {}, + "grid_x": 29, + "grid_y": 184, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y25": { + "bits": {}, + "grid_x": 29, + "grid_y": 183, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y27": { + "bits": {}, + "grid_x": 29, + "grid_y": 181, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y28": { + "bits": {}, + "grid_x": 29, + "grid_y": 180, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y29": { + "bits": {}, + "grid_x": 29, + "grid_y": 179, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y3": { + "bits": {}, + "grid_x": 29, + "grid_y": 205, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y30": { + "bits": {}, + "grid_x": 29, + "grid_y": 178, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y31": { + "bits": {}, + "grid_x": 29, + "grid_y": 177, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y32": { + "bits": {}, + "grid_x": 29, + "grid_y": 176, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y33": { + "bits": {}, + "grid_x": 29, + "grid_y": 175, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y34": { + "bits": {}, + "grid_x": 29, + "grid_y": 174, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y35": { + "bits": {}, + "grid_x": 29, + "grid_y": 173, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y36": { + "bits": {}, + "grid_x": 29, + "grid_y": 172, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y37": { + "bits": {}, + "grid_x": 29, + "grid_y": 171, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y38": { + "bits": {}, + "grid_x": 29, + "grid_y": 170, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y39": { + "bits": {}, + "grid_x": 29, + "grid_y": 169, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y4": { + "bits": {}, + "grid_x": 29, + "grid_y": 204, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y40": { + "bits": {}, + "grid_x": 29, + "grid_y": 168, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y41": { + "bits": {}, + "grid_x": 29, + "grid_y": 167, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y42": { + "bits": {}, + "grid_x": 29, + "grid_y": 166, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y43": { + "bits": {}, + "grid_x": 29, + "grid_y": 165, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y44": { + "bits": {}, + "grid_x": 29, + "grid_y": 164, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y45": { + "bits": {}, + "grid_x": 29, + "grid_y": 163, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y46": { + "bits": {}, + "grid_x": 29, + "grid_y": 162, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y47": { + "bits": {}, + "grid_x": 29, + "grid_y": 161, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y48": { + "bits": {}, + "grid_x": 29, + "grid_y": 160, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y49": { + "bits": {}, + "grid_x": 29, + "grid_y": 159, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y5": { + "bits": {}, + "grid_x": 29, + "grid_y": 203, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y50": { + "bits": {}, + "grid_x": 29, + "grid_y": 158, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y51": { + "bits": {}, + "grid_x": 29, + "grid_y": 157, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y53": { + "bits": {}, + "grid_x": 29, + "grid_y": 155, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y54": { + "bits": {}, + "grid_x": 29, + "grid_y": 154, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y55": { + "bits": {}, + "grid_x": 29, + "grid_y": 153, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y56": { + "bits": {}, + "grid_x": 29, + "grid_y": 152, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y57": { + "bits": {}, + "grid_x": 29, + "grid_y": 151, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y58": { + "bits": {}, + "grid_x": 29, + "grid_y": 150, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y59": { + "bits": {}, + "grid_x": 29, + "grid_y": 149, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y6": { + "bits": {}, + "grid_x": 29, + "grid_y": 202, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y60": { + "bits": {}, + "grid_x": 29, + "grid_y": 148, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y61": { + "bits": {}, + "grid_x": 29, + "grid_y": 147, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y62": { + "bits": {}, + "grid_x": 29, + "grid_y": 146, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y63": { + "bits": {}, + "grid_x": 29, + "grid_y": 145, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y64": { + "bits": {}, + "grid_x": 29, + "grid_y": 144, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y65": { + "bits": {}, + "grid_x": 29, + "grid_y": 143, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y66": { + "bits": {}, + "grid_x": 29, + "grid_y": 142, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y67": { + "bits": {}, + "grid_x": 29, + "grid_y": 141, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y68": { + "bits": {}, + "grid_x": 29, + "grid_y": 140, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y69": { + "bits": {}, + "grid_x": 29, + "grid_y": 139, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y7": { + "bits": {}, + "grid_x": 29, + "grid_y": 201, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y70": { + "bits": {}, + "grid_x": 29, + "grid_y": 138, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y71": { + "bits": {}, + "grid_x": 29, + "grid_y": 137, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y72": { + "bits": {}, + "grid_x": 29, + "grid_y": 136, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y73": { + "bits": {}, + "grid_x": 29, + "grid_y": 135, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y74": { + "bits": {}, + "grid_x": 29, + "grid_y": 134, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y75": { + "bits": {}, + "grid_x": 29, + "grid_y": 133, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y76": { + "bits": {}, + "grid_x": 29, + "grid_y": 132, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y77": { + "bits": {}, + "grid_x": 29, + "grid_y": 131, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y79": { + "bits": {}, + "grid_x": 29, + "grid_y": 129, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y8": { + "bits": {}, + "grid_x": 29, + "grid_y": 200, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y80": { + "bits": {}, + "grid_x": 29, + "grid_y": 128, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y81": { + "bits": {}, + "grid_x": 29, + "grid_y": 127, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y82": { + "bits": {}, + "grid_x": 29, + "grid_y": 126, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y83": { + "bits": {}, + "grid_x": 29, + "grid_y": 125, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y84": { + "bits": {}, + "grid_x": 29, + "grid_y": 124, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y85": { + "bits": {}, + "grid_x": 29, + "grid_y": 123, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y86": { + "bits": {}, + "grid_x": 29, + "grid_y": 122, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y87": { + "bits": {}, + "grid_x": 29, + "grid_y": 121, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y88": { + "bits": {}, + "grid_x": 29, + "grid_y": 120, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y89": { + "bits": {}, + "grid_x": 29, + "grid_y": 119, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y9": { + "bits": {}, + "grid_x": 29, + "grid_y": 199, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y90": { + "bits": {}, + "grid_x": 29, + "grid_y": 118, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y91": { + "bits": {}, + "grid_x": 29, + "grid_y": 117, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y92": { + "bits": {}, + "grid_x": 29, + "grid_y": 116, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y93": { + "bits": {}, + "grid_x": 29, + "grid_y": 115, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y94": { + "bits": {}, + "grid_x": 29, + "grid_y": 114, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y95": { + "bits": {}, + "grid_x": 29, + "grid_y": 113, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y96": { + "bits": {}, + "grid_x": 29, + "grid_y": 112, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y97": { + "bits": {}, + "grid_x": 29, + "grid_y": 111, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y98": { + "bits": {}, + "grid_x": 29, + "grid_y": 110, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X29Y99": { + "bits": {}, + "grid_x": 29, + "grid_y": 109, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y1": { + "bits": {}, + "grid_x": 38, + "grid_y": 207, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y10": { + "bits": {}, + "grid_x": 38, + "grid_y": 198, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y100": { + "bits": {}, + "grid_x": 38, + "grid_y": 108, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y101": { + "bits": {}, + "grid_x": 38, + "grid_y": 107, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y102": { + "bits": {}, + "grid_x": 38, + "grid_y": 106, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y103": { + "bits": {}, + "grid_x": 38, + "grid_y": 105, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y105": { + "bits": {}, + "grid_x": 38, + "grid_y": 103, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y106": { + "bits": {}, + "grid_x": 38, + "grid_y": 102, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y107": { + "bits": {}, + "grid_x": 38, + "grid_y": 101, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y108": { + "bits": {}, + "grid_x": 38, + "grid_y": 100, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y109": { + "bits": {}, + "grid_x": 38, + "grid_y": 99, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y11": { + "bits": {}, + "grid_x": 38, + "grid_y": 197, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y110": { + "bits": {}, + "grid_x": 38, + "grid_y": 98, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y111": { + "bits": {}, + "grid_x": 38, + "grid_y": 97, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y112": { + "bits": {}, + "grid_x": 38, + "grid_y": 96, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y113": { + "bits": {}, + "grid_x": 38, + "grid_y": 95, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y114": { + "bits": {}, + "grid_x": 38, + "grid_y": 94, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y115": { + "bits": {}, + "grid_x": 38, + "grid_y": 93, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y116": { + "bits": {}, + "grid_x": 38, + "grid_y": 92, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y117": { + "bits": {}, + "grid_x": 38, + "grid_y": 91, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y118": { + "bits": {}, + "grid_x": 38, + "grid_y": 90, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y119": { + "bits": {}, + "grid_x": 38, + "grid_y": 89, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y12": { + "bits": {}, + "grid_x": 38, + "grid_y": 196, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y120": { + "bits": {}, + "grid_x": 38, + "grid_y": 88, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y121": { + "bits": {}, + "grid_x": 38, + "grid_y": 87, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y122": { + "bits": {}, + "grid_x": 38, + "grid_y": 86, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y123": { + "bits": {}, + "grid_x": 38, + "grid_y": 85, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y124": { + "bits": {}, + "grid_x": 38, + "grid_y": 84, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y125": { + "bits": {}, + "grid_x": 38, + "grid_y": 83, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y126": { + "bits": {}, + "grid_x": 38, + "grid_y": 82, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y127": { + "bits": {}, + "grid_x": 38, + "grid_y": 81, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y128": { + "bits": {}, + "grid_x": 38, + "grid_y": 80, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y129": { + "bits": {}, + "grid_x": 38, + "grid_y": 79, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y13": { + "bits": {}, + "grid_x": 38, + "grid_y": 195, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y131": { + "bits": {}, + "grid_x": 38, + "grid_y": 77, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y132": { + "bits": {}, + "grid_x": 38, + "grid_y": 76, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y133": { + "bits": {}, + "grid_x": 38, + "grid_y": 75, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y134": { + "bits": {}, + "grid_x": 38, + "grid_y": 74, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y135": { + "bits": {}, + "grid_x": 38, + "grid_y": 73, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y136": { + "bits": {}, + "grid_x": 38, + "grid_y": 72, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y137": { + "bits": {}, + "grid_x": 38, + "grid_y": 71, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y138": { + "bits": {}, + "grid_x": 38, + "grid_y": 70, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y139": { + "bits": {}, + "grid_x": 38, + "grid_y": 69, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y14": { + "bits": {}, + "grid_x": 38, + "grid_y": 194, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y140": { + "bits": {}, + "grid_x": 38, + "grid_y": 68, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y141": { + "bits": {}, + "grid_x": 38, + "grid_y": 67, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y142": { + "bits": {}, + "grid_x": 38, + "grid_y": 66, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y143": { + "bits": {}, + "grid_x": 38, + "grid_y": 65, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y144": { + "bits": {}, + "grid_x": 38, + "grid_y": 64, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y145": { + "bits": {}, + "grid_x": 38, + "grid_y": 63, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y146": { + "bits": {}, + "grid_x": 38, + "grid_y": 62, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y147": { + "bits": {}, + "grid_x": 38, + "grid_y": 61, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y148": { + "bits": {}, + "grid_x": 38, + "grid_y": 60, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y149": { + "bits": {}, + "grid_x": 38, + "grid_y": 59, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y15": { + "bits": {}, + "grid_x": 38, + "grid_y": 193, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y150": { + "bits": {}, + "grid_x": 38, + "grid_y": 58, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y151": { + "bits": {}, + "grid_x": 38, + "grid_y": 57, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y152": { + "bits": {}, + "grid_x": 38, + "grid_y": 56, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y153": { + "bits": {}, + "grid_x": 38, + "grid_y": 55, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y154": { + "bits": {}, + "grid_x": 38, + "grid_y": 54, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y155": { + "bits": {}, + "grid_x": 38, + "grid_y": 53, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y157": { + "bits": {}, + "grid_x": 38, + "grid_y": 51, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y158": { + "bits": {}, + "grid_x": 38, + "grid_y": 50, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y159": { + "bits": {}, + "grid_x": 38, + "grid_y": 49, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y16": { + "bits": {}, + "grid_x": 38, + "grid_y": 192, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y160": { + "bits": {}, + "grid_x": 38, + "grid_y": 48, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y161": { + "bits": {}, + "grid_x": 38, + "grid_y": 47, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y162": { + "bits": {}, + "grid_x": 38, + "grid_y": 46, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y163": { + "bits": {}, + "grid_x": 38, + "grid_y": 45, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y164": { + "bits": {}, + "grid_x": 38, + "grid_y": 44, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y165": { + "bits": {}, + "grid_x": 38, + "grid_y": 43, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y166": { + "bits": {}, + "grid_x": 38, + "grid_y": 42, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y167": { + "bits": {}, + "grid_x": 38, + "grid_y": 41, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y168": { + "bits": {}, + "grid_x": 38, + "grid_y": 40, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y169": { + "bits": {}, + "grid_x": 38, + "grid_y": 39, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y17": { + "bits": {}, + "grid_x": 38, + "grid_y": 191, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y170": { + "bits": {}, + "grid_x": 38, + "grid_y": 38, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y171": { + "bits": {}, + "grid_x": 38, + "grid_y": 37, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y172": { + "bits": {}, + "grid_x": 38, + "grid_y": 36, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y173": { + "bits": {}, + "grid_x": 38, + "grid_y": 35, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y174": { + "bits": {}, + "grid_x": 38, + "grid_y": 34, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y175": { + "bits": {}, + "grid_x": 38, + "grid_y": 33, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y176": { + "bits": {}, + "grid_x": 38, + "grid_y": 32, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y177": { + "bits": {}, + "grid_x": 38, + "grid_y": 31, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y178": { + "bits": {}, + "grid_x": 38, + "grid_y": 30, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y179": { + "bits": {}, + "grid_x": 38, + "grid_y": 29, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y18": { + "bits": {}, + "grid_x": 38, + "grid_y": 190, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y180": { + "bits": {}, + "grid_x": 38, + "grid_y": 28, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y181": { + "bits": {}, + "grid_x": 38, + "grid_y": 27, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y183": { + "bits": {}, + "grid_x": 38, + "grid_y": 25, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y184": { + "bits": {}, + "grid_x": 38, + "grid_y": 24, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y185": { + "bits": {}, + "grid_x": 38, + "grid_y": 23, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y186": { + "bits": {}, + "grid_x": 38, + "grid_y": 22, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y187": { + "bits": {}, + "grid_x": 38, + "grid_y": 21, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y188": { + "bits": {}, + "grid_x": 38, + "grid_y": 20, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y189": { + "bits": {}, + "grid_x": 38, + "grid_y": 19, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y19": { + "bits": {}, + "grid_x": 38, + "grid_y": 189, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y190": { + "bits": {}, + "grid_x": 38, + "grid_y": 18, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y191": { + "bits": {}, + "grid_x": 38, + "grid_y": 17, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y192": { + "bits": {}, + "grid_x": 38, + "grid_y": 16, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y193": { + "bits": {}, + "grid_x": 38, + "grid_y": 15, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y194": { + "bits": {}, + "grid_x": 38, + "grid_y": 14, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y195": { + "bits": {}, + "grid_x": 38, + "grid_y": 13, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y196": { + "bits": {}, + "grid_x": 38, + "grid_y": 12, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y197": { + "bits": {}, + "grid_x": 38, + "grid_y": 11, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y198": { + "bits": {}, + "grid_x": 38, + "grid_y": 10, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y199": { + "bits": {}, + "grid_x": 38, + "grid_y": 9, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y2": { + "bits": {}, + "grid_x": 38, + "grid_y": 206, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y20": { + "bits": {}, + "grid_x": 38, + "grid_y": 188, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y200": { + "bits": {}, + "grid_x": 38, + "grid_y": 8, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y201": { + "bits": {}, + "grid_x": 38, + "grid_y": 7, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y202": { + "bits": {}, + "grid_x": 38, + "grid_y": 6, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y203": { + "bits": {}, + "grid_x": 38, + "grid_y": 5, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y204": { + "bits": {}, + "grid_x": 38, + "grid_y": 4, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y205": { + "bits": {}, + "grid_x": 38, + "grid_y": 3, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y206": { + "bits": {}, + "grid_x": 38, + "grid_y": 2, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y207": { + "bits": {}, + "grid_x": 38, + "grid_y": 1, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y21": { + "bits": {}, + "grid_x": 38, + "grid_y": 187, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y22": { + "bits": {}, + "grid_x": 38, + "grid_y": 186, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y23": { + "bits": {}, + "grid_x": 38, + "grid_y": 185, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y24": { + "bits": {}, + "grid_x": 38, + "grid_y": 184, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y25": { + "bits": {}, + "grid_x": 38, + "grid_y": 183, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y27": { + "bits": {}, + "grid_x": 38, + "grid_y": 181, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y28": { + "bits": {}, + "grid_x": 38, + "grid_y": 180, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y29": { + "bits": {}, + "grid_x": 38, + "grid_y": 179, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y3": { + "bits": {}, + "grid_x": 38, + "grid_y": 205, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y30": { + "bits": {}, + "grid_x": 38, + "grid_y": 178, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y31": { + "bits": {}, + "grid_x": 38, + "grid_y": 177, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y32": { + "bits": {}, + "grid_x": 38, + "grid_y": 176, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y33": { + "bits": {}, + "grid_x": 38, + "grid_y": 175, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y34": { + "bits": {}, + "grid_x": 38, + "grid_y": 174, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y35": { + "bits": {}, + "grid_x": 38, + "grid_y": 173, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y36": { + "bits": {}, + "grid_x": 38, + "grid_y": 172, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y37": { + "bits": {}, + "grid_x": 38, + "grid_y": 171, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y38": { + "bits": {}, + "grid_x": 38, + "grid_y": 170, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y39": { + "bits": {}, + "grid_x": 38, + "grid_y": 169, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y4": { + "bits": {}, + "grid_x": 38, + "grid_y": 204, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y40": { + "bits": {}, + "grid_x": 38, + "grid_y": 168, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y41": { + "bits": {}, + "grid_x": 38, + "grid_y": 167, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y42": { + "bits": {}, + "grid_x": 38, + "grid_y": 166, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y43": { + "bits": {}, + "grid_x": 38, + "grid_y": 165, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y44": { + "bits": {}, + "grid_x": 38, + "grid_y": 164, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y45": { + "bits": {}, + "grid_x": 38, + "grid_y": 163, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y46": { + "bits": {}, + "grid_x": 38, + "grid_y": 162, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y47": { + "bits": {}, + "grid_x": 38, + "grid_y": 161, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y48": { + "bits": {}, + "grid_x": 38, + "grid_y": 160, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y49": { + "bits": {}, + "grid_x": 38, + "grid_y": 159, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y5": { + "bits": {}, + "grid_x": 38, + "grid_y": 203, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y50": { + "bits": {}, + "grid_x": 38, + "grid_y": 158, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y51": { + "bits": {}, + "grid_x": 38, + "grid_y": 157, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y53": { + "bits": {}, + "grid_x": 38, + "grid_y": 155, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y54": { + "bits": {}, + "grid_x": 38, + "grid_y": 154, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y55": { + "bits": {}, + "grid_x": 38, + "grid_y": 153, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y56": { + "bits": {}, + "grid_x": 38, + "grid_y": 152, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y57": { + "bits": {}, + "grid_x": 38, + "grid_y": 151, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y58": { + "bits": {}, + "grid_x": 38, + "grid_y": 150, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y59": { + "bits": {}, + "grid_x": 38, + "grid_y": 149, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y6": { + "bits": {}, + "grid_x": 38, + "grid_y": 202, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y60": { + "bits": {}, + "grid_x": 38, + "grid_y": 148, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y61": { + "bits": {}, + "grid_x": 38, + "grid_y": 147, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y62": { + "bits": {}, + "grid_x": 38, + "grid_y": 146, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y63": { + "bits": {}, + "grid_x": 38, + "grid_y": 145, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y64": { + "bits": {}, + "grid_x": 38, + "grid_y": 144, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y65": { + "bits": {}, + "grid_x": 38, + "grid_y": 143, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y66": { + "bits": {}, + "grid_x": 38, + "grid_y": 142, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y67": { + "bits": {}, + "grid_x": 38, + "grid_y": 141, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y68": { + "bits": {}, + "grid_x": 38, + "grid_y": 140, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y69": { + "bits": {}, + "grid_x": 38, + "grid_y": 139, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y7": { + "bits": {}, + "grid_x": 38, + "grid_y": 201, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y70": { + "bits": {}, + "grid_x": 38, + "grid_y": 138, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y71": { + "bits": {}, + "grid_x": 38, + "grid_y": 137, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y72": { + "bits": {}, + "grid_x": 38, + "grid_y": 136, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y73": { + "bits": {}, + "grid_x": 38, + "grid_y": 135, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y74": { + "bits": {}, + "grid_x": 38, + "grid_y": 134, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y75": { + "bits": {}, + "grid_x": 38, + "grid_y": 133, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y76": { + "bits": {}, + "grid_x": 38, + "grid_y": 132, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y77": { + "bits": {}, + "grid_x": 38, + "grid_y": 131, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y79": { + "bits": {}, + "grid_x": 38, + "grid_y": 129, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y8": { + "bits": {}, + "grid_x": 38, + "grid_y": 200, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y80": { + "bits": {}, + "grid_x": 38, + "grid_y": 128, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y81": { + "bits": {}, + "grid_x": 38, + "grid_y": 127, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y82": { + "bits": {}, + "grid_x": 38, + "grid_y": 126, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y83": { + "bits": {}, + "grid_x": 38, + "grid_y": 125, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y84": { + "bits": {}, + "grid_x": 38, + "grid_y": 124, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y85": { + "bits": {}, + "grid_x": 38, + "grid_y": 123, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y86": { + "bits": {}, + "grid_x": 38, + "grid_y": 122, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y87": { + "bits": {}, + "grid_x": 38, + "grid_y": 121, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y88": { + "bits": {}, + "grid_x": 38, + "grid_y": 120, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y89": { + "bits": {}, + "grid_x": 38, + "grid_y": 119, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y9": { + "bits": {}, + "grid_x": 38, + "grid_y": 199, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y90": { + "bits": {}, + "grid_x": 38, + "grid_y": 118, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y91": { + "bits": {}, + "grid_x": 38, + "grid_y": 117, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y92": { + "bits": {}, + "grid_x": 38, + "grid_y": 116, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y93": { + "bits": {}, + "grid_x": 38, + "grid_y": 115, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y94": { + "bits": {}, + "grid_x": 38, + "grid_y": 114, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y95": { + "bits": {}, + "grid_x": 38, + "grid_y": 113, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y96": { + "bits": {}, + "grid_x": 38, + "grid_y": 112, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y97": { + "bits": {}, + "grid_x": 38, + "grid_y": 111, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y98": { + "bits": {}, + "grid_x": 38, + "grid_y": 110, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X38Y99": { + "bits": {}, + "grid_x": 38, + "grid_y": 109, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y1": { + "bits": {}, + "grid_x": 49, + "grid_y": 207, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y10": { + "bits": {}, + "grid_x": 49, + "grid_y": 198, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y100": { + "bits": {}, + "grid_x": 49, + "grid_y": 108, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y101": { + "bits": {}, + "grid_x": 49, + "grid_y": 107, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y102": { + "bits": {}, + "grid_x": 49, + "grid_y": 106, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y103": { + "bits": {}, + "grid_x": 49, + "grid_y": 105, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y105": { + "bits": {}, + "grid_x": 49, + "grid_y": 103, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y106": { + "bits": {}, + "grid_x": 49, + "grid_y": 102, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y107": { + "bits": {}, + "grid_x": 49, + "grid_y": 101, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y108": { + "bits": {}, + "grid_x": 49, + "grid_y": 100, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y109": { + "bits": {}, + "grid_x": 49, + "grid_y": 99, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y11": { + "bits": {}, + "grid_x": 49, + "grid_y": 197, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y110": { + "bits": {}, + "grid_x": 49, + "grid_y": 98, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y111": { + "bits": {}, + "grid_x": 49, + "grid_y": 97, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y112": { + "bits": {}, + "grid_x": 49, + "grid_y": 96, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y113": { + "bits": {}, + "grid_x": 49, + "grid_y": 95, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y114": { + "bits": {}, + "grid_x": 49, + "grid_y": 94, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y115": { + "bits": {}, + "grid_x": 49, + "grid_y": 93, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y116": { + "bits": {}, + "grid_x": 49, + "grid_y": 92, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y117": { + "bits": {}, + "grid_x": 49, + "grid_y": 91, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y118": { + "bits": {}, + "grid_x": 49, + "grid_y": 90, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y119": { + "bits": {}, + "grid_x": 49, + "grid_y": 89, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y12": { + "bits": {}, + "grid_x": 49, + "grid_y": 196, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y120": { + "bits": {}, + "grid_x": 49, + "grid_y": 88, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y121": { + "bits": {}, + "grid_x": 49, + "grid_y": 87, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y122": { + "bits": {}, + "grid_x": 49, + "grid_y": 86, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y123": { + "bits": {}, + "grid_x": 49, + "grid_y": 85, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y124": { + "bits": {}, + "grid_x": 49, + "grid_y": 84, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y125": { + "bits": {}, + "grid_x": 49, + "grid_y": 83, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y126": { + "bits": {}, + "grid_x": 49, + "grid_y": 82, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y127": { + "bits": {}, + "grid_x": 49, + "grid_y": 81, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y128": { + "bits": {}, + "grid_x": 49, + "grid_y": 80, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y129": { + "bits": {}, + "grid_x": 49, + "grid_y": 79, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y13": { + "bits": {}, + "grid_x": 49, + "grid_y": 195, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y131": { + "bits": {}, + "grid_x": 49, + "grid_y": 77, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y132": { + "bits": {}, + "grid_x": 49, + "grid_y": 76, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y133": { + "bits": {}, + "grid_x": 49, + "grid_y": 75, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y134": { + "bits": {}, + "grid_x": 49, + "grid_y": 74, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y135": { + "bits": {}, + "grid_x": 49, + "grid_y": 73, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y136": { + "bits": {}, + "grid_x": 49, + "grid_y": 72, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y137": { + "bits": {}, + "grid_x": 49, + "grid_y": 71, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y138": { + "bits": {}, + "grid_x": 49, + "grid_y": 70, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y139": { + "bits": {}, + "grid_x": 49, + "grid_y": 69, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y14": { + "bits": {}, + "grid_x": 49, + "grid_y": 194, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y140": { + "bits": {}, + "grid_x": 49, + "grid_y": 68, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y141": { + "bits": {}, + "grid_x": 49, + "grid_y": 67, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y142": { + "bits": {}, + "grid_x": 49, + "grid_y": 66, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y143": { + "bits": {}, + "grid_x": 49, + "grid_y": 65, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y144": { + "bits": {}, + "grid_x": 49, + "grid_y": 64, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y145": { + "bits": {}, + "grid_x": 49, + "grid_y": 63, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y146": { + "bits": {}, + "grid_x": 49, + "grid_y": 62, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y147": { + "bits": {}, + "grid_x": 49, + "grid_y": 61, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y148": { + "bits": {}, + "grid_x": 49, + "grid_y": 60, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y149": { + "bits": {}, + "grid_x": 49, + "grid_y": 59, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y15": { + "bits": {}, + "grid_x": 49, + "grid_y": 193, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y150": { + "bits": {}, + "grid_x": 49, + "grid_y": 58, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y151": { + "bits": {}, + "grid_x": 49, + "grid_y": 57, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y152": { + "bits": {}, + "grid_x": 49, + "grid_y": 56, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y153": { + "bits": {}, + "grid_x": 49, + "grid_y": 55, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y154": { + "bits": {}, + "grid_x": 49, + "grid_y": 54, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y155": { + "bits": {}, + "grid_x": 49, + "grid_y": 53, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y157": { + "bits": {}, + "grid_x": 49, + "grid_y": 51, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y158": { + "bits": {}, + "grid_x": 49, + "grid_y": 50, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y159": { + "bits": {}, + "grid_x": 49, + "grid_y": 49, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y16": { + "bits": {}, + "grid_x": 49, + "grid_y": 192, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y160": { + "bits": {}, + "grid_x": 49, + "grid_y": 48, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y161": { + "bits": {}, + "grid_x": 49, + "grid_y": 47, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y162": { + "bits": {}, + "grid_x": 49, + "grid_y": 46, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y163": { + "bits": {}, + "grid_x": 49, + "grid_y": 45, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y164": { + "bits": {}, + "grid_x": 49, + "grid_y": 44, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y165": { + "bits": {}, + "grid_x": 49, + "grid_y": 43, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y166": { + "bits": {}, + "grid_x": 49, + "grid_y": 42, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y167": { + "bits": {}, + "grid_x": 49, + "grid_y": 41, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y168": { + "bits": {}, + "grid_x": 49, + "grid_y": 40, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y169": { + "bits": {}, + "grid_x": 49, + "grid_y": 39, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y17": { + "bits": {}, + "grid_x": 49, + "grid_y": 191, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y170": { + "bits": {}, + "grid_x": 49, + "grid_y": 38, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y171": { + "bits": {}, + "grid_x": 49, + "grid_y": 37, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y172": { + "bits": {}, + "grid_x": 49, + "grid_y": 36, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y173": { + "bits": {}, + "grid_x": 49, + "grid_y": 35, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y174": { + "bits": {}, + "grid_x": 49, + "grid_y": 34, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y175": { + "bits": {}, + "grid_x": 49, + "grid_y": 33, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y176": { + "bits": {}, + "grid_x": 49, + "grid_y": 32, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y177": { + "bits": {}, + "grid_x": 49, + "grid_y": 31, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y178": { + "bits": {}, + "grid_x": 49, + "grid_y": 30, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y179": { + "bits": {}, + "grid_x": 49, + "grid_y": 29, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y18": { + "bits": {}, + "grid_x": 49, + "grid_y": 190, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y180": { + "bits": {}, + "grid_x": 49, + "grid_y": 28, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y181": { + "bits": {}, + "grid_x": 49, + "grid_y": 27, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y183": { + "bits": {}, + "grid_x": 49, + "grid_y": 25, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y184": { + "bits": {}, + "grid_x": 49, + "grid_y": 24, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y185": { + "bits": {}, + "grid_x": 49, + "grid_y": 23, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y186": { + "bits": {}, + "grid_x": 49, + "grid_y": 22, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y187": { + "bits": {}, + "grid_x": 49, + "grid_y": 21, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y188": { + "bits": {}, + "grid_x": 49, + "grid_y": 20, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y189": { + "bits": {}, + "grid_x": 49, + "grid_y": 19, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y19": { + "bits": {}, + "grid_x": 49, + "grid_y": 189, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y190": { + "bits": {}, + "grid_x": 49, + "grid_y": 18, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y191": { + "bits": {}, + "grid_x": 49, + "grid_y": 17, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y192": { + "bits": {}, + "grid_x": 49, + "grid_y": 16, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y193": { + "bits": {}, + "grid_x": 49, + "grid_y": 15, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y194": { + "bits": {}, + "grid_x": 49, + "grid_y": 14, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y195": { + "bits": {}, + "grid_x": 49, + "grid_y": 13, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y196": { + "bits": {}, + "grid_x": 49, + "grid_y": 12, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y197": { + "bits": {}, + "grid_x": 49, + "grid_y": 11, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y198": { + "bits": {}, + "grid_x": 49, + "grid_y": 10, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y199": { + "bits": {}, + "grid_x": 49, + "grid_y": 9, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y2": { + "bits": {}, + "grid_x": 49, + "grid_y": 206, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y20": { + "bits": {}, + "grid_x": 49, + "grid_y": 188, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y200": { + "bits": {}, + "grid_x": 49, + "grid_y": 8, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y201": { + "bits": {}, + "grid_x": 49, + "grid_y": 7, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y202": { + "bits": {}, + "grid_x": 49, + "grid_y": 6, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y203": { + "bits": {}, + "grid_x": 49, + "grid_y": 5, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y204": { + "bits": {}, + "grid_x": 49, + "grid_y": 4, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y205": { + "bits": {}, + "grid_x": 49, + "grid_y": 3, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y206": { + "bits": {}, + "grid_x": 49, + "grid_y": 2, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y207": { + "bits": {}, + "grid_x": 49, + "grid_y": 1, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y21": { + "bits": {}, + "grid_x": 49, + "grid_y": 187, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y22": { + "bits": {}, + "grid_x": 49, + "grid_y": 186, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y23": { + "bits": {}, + "grid_x": 49, + "grid_y": 185, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y24": { + "bits": {}, + "grid_x": 49, + "grid_y": 184, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y25": { + "bits": {}, + "grid_x": 49, + "grid_y": 183, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y27": { + "bits": {}, + "grid_x": 49, + "grid_y": 181, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y28": { + "bits": {}, + "grid_x": 49, + "grid_y": 180, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y29": { + "bits": {}, + "grid_x": 49, + "grid_y": 179, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y3": { + "bits": {}, + "grid_x": 49, + "grid_y": 205, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y30": { + "bits": {}, + "grid_x": 49, + "grid_y": 178, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y31": { + "bits": {}, + "grid_x": 49, + "grid_y": 177, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y32": { + "bits": {}, + "grid_x": 49, + "grid_y": 176, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y33": { + "bits": {}, + "grid_x": 49, + "grid_y": 175, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y34": { + "bits": {}, + "grid_x": 49, + "grid_y": 174, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y35": { + "bits": {}, + "grid_x": 49, + "grid_y": 173, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y36": { + "bits": {}, + "grid_x": 49, + "grid_y": 172, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y37": { + "bits": {}, + "grid_x": 49, + "grid_y": 171, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y38": { + "bits": {}, + "grid_x": 49, + "grid_y": 170, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y39": { + "bits": {}, + "grid_x": 49, + "grid_y": 169, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y4": { + "bits": {}, + "grid_x": 49, + "grid_y": 204, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y40": { + "bits": {}, + "grid_x": 49, + "grid_y": 168, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y41": { + "bits": {}, + "grid_x": 49, + "grid_y": 167, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y42": { + "bits": {}, + "grid_x": 49, + "grid_y": 166, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y43": { + "bits": {}, + "grid_x": 49, + "grid_y": 165, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y44": { + "bits": {}, + "grid_x": 49, + "grid_y": 164, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y45": { + "bits": {}, + "grid_x": 49, + "grid_y": 163, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y46": { + "bits": {}, + "grid_x": 49, + "grid_y": 162, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y47": { + "bits": {}, + "grid_x": 49, + "grid_y": 161, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y48": { + "bits": {}, + "grid_x": 49, + "grid_y": 160, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y49": { + "bits": {}, + "grid_x": 49, + "grid_y": 159, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y5": { + "bits": {}, + "grid_x": 49, + "grid_y": 203, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y50": { + "bits": {}, + "grid_x": 49, + "grid_y": 158, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y51": { + "bits": {}, + "grid_x": 49, + "grid_y": 157, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y53": { + "bits": {}, + "grid_x": 49, + "grid_y": 155, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y54": { + "bits": {}, + "grid_x": 49, + "grid_y": 154, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y55": { + "bits": {}, + "grid_x": 49, + "grid_y": 153, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y56": { + "bits": {}, + "grid_x": 49, + "grid_y": 152, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y57": { + "bits": {}, + "grid_x": 49, + "grid_y": 151, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y58": { + "bits": {}, + "grid_x": 49, + "grid_y": 150, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y59": { + "bits": {}, + "grid_x": 49, + "grid_y": 149, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y6": { + "bits": {}, + "grid_x": 49, + "grid_y": 202, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y60": { + "bits": {}, + "grid_x": 49, + "grid_y": 148, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y61": { + "bits": {}, + "grid_x": 49, + "grid_y": 147, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y62": { + "bits": {}, + "grid_x": 49, + "grid_y": 146, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y63": { + "bits": {}, + "grid_x": 49, + "grid_y": 145, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y64": { + "bits": {}, + "grid_x": 49, + "grid_y": 144, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y65": { + "bits": {}, + "grid_x": 49, + "grid_y": 143, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y66": { + "bits": {}, + "grid_x": 49, + "grid_y": 142, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y67": { + "bits": {}, + "grid_x": 49, + "grid_y": 141, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y68": { + "bits": {}, + "grid_x": 49, + "grid_y": 140, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y69": { + "bits": {}, + "grid_x": 49, + "grid_y": 139, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y7": { + "bits": {}, + "grid_x": 49, + "grid_y": 201, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y70": { + "bits": {}, + "grid_x": 49, + "grid_y": 138, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y71": { + "bits": {}, + "grid_x": 49, + "grid_y": 137, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y72": { + "bits": {}, + "grid_x": 49, + "grid_y": 136, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y73": { + "bits": {}, + "grid_x": 49, + "grid_y": 135, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y74": { + "bits": {}, + "grid_x": 49, + "grid_y": 134, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y75": { + "bits": {}, + "grid_x": 49, + "grid_y": 133, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y76": { + "bits": {}, + "grid_x": 49, + "grid_y": 132, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y77": { + "bits": {}, + "grid_x": 49, + "grid_y": 131, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y79": { + "bits": {}, + "grid_x": 49, + "grid_y": 129, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y8": { + "bits": {}, + "grid_x": 49, + "grid_y": 200, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y80": { + "bits": {}, + "grid_x": 49, + "grid_y": 128, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y81": { + "bits": {}, + "grid_x": 49, + "grid_y": 127, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y82": { + "bits": {}, + "grid_x": 49, + "grid_y": 126, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y83": { + "bits": {}, + "grid_x": 49, + "grid_y": 125, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y84": { + "bits": {}, + "grid_x": 49, + "grid_y": 124, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y85": { + "bits": {}, + "grid_x": 49, + "grid_y": 123, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y86": { + "bits": {}, + "grid_x": 49, + "grid_y": 122, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y87": { + "bits": {}, + "grid_x": 49, + "grid_y": 121, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y88": { + "bits": {}, + "grid_x": 49, + "grid_y": 120, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y89": { + "bits": {}, + "grid_x": 49, + "grid_y": 119, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y9": { + "bits": {}, + "grid_x": 49, + "grid_y": 199, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y90": { + "bits": {}, + "grid_x": 49, + "grid_y": 118, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y91": { + "bits": {}, + "grid_x": 49, + "grid_y": 117, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y92": { + "bits": {}, + "grid_x": 49, + "grid_y": 116, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y93": { + "bits": {}, + "grid_x": 49, + "grid_y": 115, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y94": { + "bits": {}, + "grid_x": 49, + "grid_y": 114, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y95": { + "bits": {}, + "grid_x": 49, + "grid_y": 113, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y96": { + "bits": {}, + "grid_x": 49, + "grid_y": 112, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y97": { + "bits": {}, + "grid_x": 49, + "grid_y": 111, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y98": { + "bits": {}, + "grid_x": 49, + "grid_y": 110, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X49Y99": { + "bits": {}, + "grid_x": 49, + "grid_y": 109, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y1": { + "bits": {}, + "grid_x": 68, + "grid_y": 207, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y10": { + "bits": {}, + "grid_x": 68, + "grid_y": 198, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y100": { + "bits": {}, + "grid_x": 68, + "grid_y": 108, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y101": { + "bits": {}, + "grid_x": 68, + "grid_y": 107, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y102": { + "bits": {}, + "grid_x": 68, + "grid_y": 106, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y103": { + "bits": {}, + "grid_x": 68, + "grid_y": 105, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y105": { + "bits": {}, + "grid_x": 68, + "grid_y": 103, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y106": { + "bits": {}, + "grid_x": 68, + "grid_y": 102, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y107": { + "bits": {}, + "grid_x": 68, + "grid_y": 101, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y108": { + "bits": {}, + "grid_x": 68, + "grid_y": 100, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y109": { + "bits": {}, + "grid_x": 68, + "grid_y": 99, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y11": { + "bits": {}, + "grid_x": 68, + "grid_y": 197, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y110": { + "bits": {}, + "grid_x": 68, + "grid_y": 98, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y111": { + "bits": {}, + "grid_x": 68, + "grid_y": 97, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y112": { + "bits": {}, + "grid_x": 68, + "grid_y": 96, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y113": { + "bits": {}, + "grid_x": 68, + "grid_y": 95, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y114": { + "bits": {}, + "grid_x": 68, + "grid_y": 94, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y115": { + "bits": {}, + "grid_x": 68, + "grid_y": 93, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y116": { + "bits": {}, + "grid_x": 68, + "grid_y": 92, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y117": { + "bits": {}, + "grid_x": 68, + "grid_y": 91, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y118": { + "bits": {}, + "grid_x": 68, + "grid_y": 90, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y119": { + "bits": {}, + "grid_x": 68, + "grid_y": 89, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y12": { + "bits": {}, + "grid_x": 68, + "grid_y": 196, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y120": { + "bits": {}, + "grid_x": 68, + "grid_y": 88, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y121": { + "bits": {}, + "grid_x": 68, + "grid_y": 87, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y122": { + "bits": {}, + "grid_x": 68, + "grid_y": 86, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y123": { + "bits": {}, + "grid_x": 68, + "grid_y": 85, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y124": { + "bits": {}, + "grid_x": 68, + "grid_y": 84, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y125": { + "bits": {}, + "grid_x": 68, + "grid_y": 83, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y126": { + "bits": {}, + "grid_x": 68, + "grid_y": 82, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y127": { + "bits": {}, + "grid_x": 68, + "grid_y": 81, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y128": { + "bits": {}, + "grid_x": 68, + "grid_y": 80, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y129": { + "bits": {}, + "grid_x": 68, + "grid_y": 79, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y13": { + "bits": {}, + "grid_x": 68, + "grid_y": 195, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y131": { + "bits": {}, + "grid_x": 68, + "grid_y": 77, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y132": { + "bits": {}, + "grid_x": 68, + "grid_y": 76, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y133": { + "bits": {}, + "grid_x": 68, + "grid_y": 75, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y134": { + "bits": {}, + "grid_x": 68, + "grid_y": 74, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y135": { + "bits": {}, + "grid_x": 68, + "grid_y": 73, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y136": { + "bits": {}, + "grid_x": 68, + "grid_y": 72, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y137": { + "bits": {}, + "grid_x": 68, + "grid_y": 71, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y138": { + "bits": {}, + "grid_x": 68, + "grid_y": 70, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y139": { + "bits": {}, + "grid_x": 68, + "grid_y": 69, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y14": { + "bits": {}, + "grid_x": 68, + "grid_y": 194, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y140": { + "bits": {}, + "grid_x": 68, + "grid_y": 68, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y141": { + "bits": {}, + "grid_x": 68, + "grid_y": 67, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y142": { + "bits": {}, + "grid_x": 68, + "grid_y": 66, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y143": { + "bits": {}, + "grid_x": 68, + "grid_y": 65, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y144": { + "bits": {}, + "grid_x": 68, + "grid_y": 64, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y145": { + "bits": {}, + "grid_x": 68, + "grid_y": 63, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y146": { + "bits": {}, + "grid_x": 68, + "grid_y": 62, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y147": { + "bits": {}, + "grid_x": 68, + "grid_y": 61, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y148": { + "bits": {}, + "grid_x": 68, + "grid_y": 60, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y149": { + "bits": {}, + "grid_x": 68, + "grid_y": 59, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y15": { + "bits": {}, + "grid_x": 68, + "grid_y": 193, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y150": { + "bits": {}, + "grid_x": 68, + "grid_y": 58, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y151": { + "bits": {}, + "grid_x": 68, + "grid_y": 57, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y152": { + "bits": {}, + "grid_x": 68, + "grid_y": 56, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y153": { + "bits": {}, + "grid_x": 68, + "grid_y": 55, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y154": { + "bits": {}, + "grid_x": 68, + "grid_y": 54, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y155": { + "bits": {}, + "grid_x": 68, + "grid_y": 53, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y157": { + "bits": {}, + "grid_x": 68, + "grid_y": 51, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y158": { + "bits": {}, + "grid_x": 68, + "grid_y": 50, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y159": { + "bits": {}, + "grid_x": 68, + "grid_y": 49, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y16": { + "bits": {}, + "grid_x": 68, + "grid_y": 192, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y160": { + "bits": {}, + "grid_x": 68, + "grid_y": 48, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y161": { + "bits": {}, + "grid_x": 68, + "grid_y": 47, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y162": { + "bits": {}, + "grid_x": 68, + "grid_y": 46, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y163": { + "bits": {}, + "grid_x": 68, + "grid_y": 45, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y164": { + "bits": {}, + "grid_x": 68, + "grid_y": 44, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y165": { + "bits": {}, + "grid_x": 68, + "grid_y": 43, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y166": { + "bits": {}, + "grid_x": 68, + "grid_y": 42, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y167": { + "bits": {}, + "grid_x": 68, + "grid_y": 41, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y168": { + "bits": {}, + "grid_x": 68, + "grid_y": 40, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y169": { + "bits": {}, + "grid_x": 68, + "grid_y": 39, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y17": { + "bits": {}, + "grid_x": 68, + "grid_y": 191, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y170": { + "bits": {}, + "grid_x": 68, + "grid_y": 38, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y171": { + "bits": {}, + "grid_x": 68, + "grid_y": 37, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y172": { + "bits": {}, + "grid_x": 68, + "grid_y": 36, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y173": { + "bits": {}, + "grid_x": 68, + "grid_y": 35, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y174": { + "bits": {}, + "grid_x": 68, + "grid_y": 34, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y175": { + "bits": {}, + "grid_x": 68, + "grid_y": 33, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y176": { + "bits": {}, + "grid_x": 68, + "grid_y": 32, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y177": { + "bits": {}, + "grid_x": 68, + "grid_y": 31, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y178": { + "bits": {}, + "grid_x": 68, + "grid_y": 30, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y179": { + "bits": {}, + "grid_x": 68, + "grid_y": 29, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y18": { + "bits": {}, + "grid_x": 68, + "grid_y": 190, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y180": { + "bits": {}, + "grid_x": 68, + "grid_y": 28, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y181": { + "bits": {}, + "grid_x": 68, + "grid_y": 27, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y183": { + "bits": {}, + "grid_x": 68, + "grid_y": 25, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y184": { + "bits": {}, + "grid_x": 68, + "grid_y": 24, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y185": { + "bits": {}, + "grid_x": 68, + "grid_y": 23, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y186": { + "bits": {}, + "grid_x": 68, + "grid_y": 22, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y187": { + "bits": {}, + "grid_x": 68, + "grid_y": 21, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y188": { + "bits": {}, + "grid_x": 68, + "grid_y": 20, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y189": { + "bits": {}, + "grid_x": 68, + "grid_y": 19, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y19": { + "bits": {}, + "grid_x": 68, + "grid_y": 189, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y190": { + "bits": {}, + "grid_x": 68, + "grid_y": 18, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y191": { + "bits": {}, + "grid_x": 68, + "grid_y": 17, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y192": { + "bits": {}, + "grid_x": 68, + "grid_y": 16, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y193": { + "bits": {}, + "grid_x": 68, + "grid_y": 15, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y194": { + "bits": {}, + "grid_x": 68, + "grid_y": 14, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y195": { + "bits": {}, + "grid_x": 68, + "grid_y": 13, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y196": { + "bits": {}, + "grid_x": 68, + "grid_y": 12, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y197": { + "bits": {}, + "grid_x": 68, + "grid_y": 11, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y198": { + "bits": {}, + "grid_x": 68, + "grid_y": 10, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y199": { + "bits": {}, + "grid_x": 68, + "grid_y": 9, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y2": { + "bits": {}, + "grid_x": 68, + "grid_y": 206, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y20": { + "bits": {}, + "grid_x": 68, + "grid_y": 188, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y200": { + "bits": {}, + "grid_x": 68, + "grid_y": 8, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y201": { + "bits": {}, + "grid_x": 68, + "grid_y": 7, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y202": { + "bits": {}, + "grid_x": 68, + "grid_y": 6, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y203": { + "bits": {}, + "grid_x": 68, + "grid_y": 5, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y204": { + "bits": {}, + "grid_x": 68, + "grid_y": 4, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y205": { + "bits": {}, + "grid_x": 68, + "grid_y": 3, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y206": { + "bits": {}, + "grid_x": 68, + "grid_y": 2, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y207": { + "bits": {}, + "grid_x": 68, + "grid_y": 1, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y21": { + "bits": {}, + "grid_x": 68, + "grid_y": 187, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y22": { + "bits": {}, + "grid_x": 68, + "grid_y": 186, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y23": { + "bits": {}, + "grid_x": 68, + "grid_y": 185, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y24": { + "bits": {}, + "grid_x": 68, + "grid_y": 184, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y25": { + "bits": {}, + "grid_x": 68, + "grid_y": 183, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y27": { + "bits": {}, + "grid_x": 68, + "grid_y": 181, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y28": { + "bits": {}, + "grid_x": 68, + "grid_y": 180, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y29": { + "bits": {}, + "grid_x": 68, + "grid_y": 179, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y3": { + "bits": {}, + "grid_x": 68, + "grid_y": 205, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y30": { + "bits": {}, + "grid_x": 68, + "grid_y": 178, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y31": { + "bits": {}, + "grid_x": 68, + "grid_y": 177, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y32": { + "bits": {}, + "grid_x": 68, + "grid_y": 176, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y33": { + "bits": {}, + "grid_x": 68, + "grid_y": 175, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y34": { + "bits": {}, + "grid_x": 68, + "grid_y": 174, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y35": { + "bits": {}, + "grid_x": 68, + "grid_y": 173, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y36": { + "bits": {}, + "grid_x": 68, + "grid_y": 172, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y37": { + "bits": {}, + "grid_x": 68, + "grid_y": 171, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y38": { + "bits": {}, + "grid_x": 68, + "grid_y": 170, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y39": { + "bits": {}, + "grid_x": 68, + "grid_y": 169, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y4": { + "bits": {}, + "grid_x": 68, + "grid_y": 204, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y40": { + "bits": {}, + "grid_x": 68, + "grid_y": 168, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y41": { + "bits": {}, + "grid_x": 68, + "grid_y": 167, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y42": { + "bits": {}, + "grid_x": 68, + "grid_y": 166, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y43": { + "bits": {}, + "grid_x": 68, + "grid_y": 165, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y44": { + "bits": {}, + "grid_x": 68, + "grid_y": 164, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y45": { + "bits": {}, + "grid_x": 68, + "grid_y": 163, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y46": { + "bits": {}, + "grid_x": 68, + "grid_y": 162, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y47": { + "bits": {}, + "grid_x": 68, + "grid_y": 161, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y48": { + "bits": {}, + "grid_x": 68, + "grid_y": 160, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y49": { + "bits": {}, + "grid_x": 68, + "grid_y": 159, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y5": { + "bits": {}, + "grid_x": 68, + "grid_y": 203, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y50": { + "bits": {}, + "grid_x": 68, + "grid_y": 158, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y51": { + "bits": {}, + "grid_x": 68, + "grid_y": 157, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y53": { + "bits": {}, + "grid_x": 68, + "grid_y": 155, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y54": { + "bits": {}, + "grid_x": 68, + "grid_y": 154, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y55": { + "bits": {}, + "grid_x": 68, + "grid_y": 153, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y56": { + "bits": {}, + "grid_x": 68, + "grid_y": 152, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y57": { + "bits": {}, + "grid_x": 68, + "grid_y": 151, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y58": { + "bits": {}, + "grid_x": 68, + "grid_y": 150, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y59": { + "bits": {}, + "grid_x": 68, + "grid_y": 149, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y6": { + "bits": {}, + "grid_x": 68, + "grid_y": 202, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y60": { + "bits": {}, + "grid_x": 68, + "grid_y": 148, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y61": { + "bits": {}, + "grid_x": 68, + "grid_y": 147, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y62": { + "bits": {}, + "grid_x": 68, + "grid_y": 146, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y63": { + "bits": {}, + "grid_x": 68, + "grid_y": 145, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y64": { + "bits": {}, + "grid_x": 68, + "grid_y": 144, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y65": { + "bits": {}, + "grid_x": 68, + "grid_y": 143, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y66": { + "bits": {}, + "grid_x": 68, + "grid_y": 142, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y67": { + "bits": {}, + "grid_x": 68, + "grid_y": 141, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y68": { + "bits": {}, + "grid_x": 68, + "grid_y": 140, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y69": { + "bits": {}, + "grid_x": 68, + "grid_y": 139, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y7": { + "bits": {}, + "grid_x": 68, + "grid_y": 201, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y70": { + "bits": {}, + "grid_x": 68, + "grid_y": 138, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y71": { + "bits": {}, + "grid_x": 68, + "grid_y": 137, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y72": { + "bits": {}, + "grid_x": 68, + "grid_y": 136, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y73": { + "bits": {}, + "grid_x": 68, + "grid_y": 135, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y74": { + "bits": {}, + "grid_x": 68, + "grid_y": 134, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y75": { + "bits": {}, + "grid_x": 68, + "grid_y": 133, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y76": { + "bits": {}, + "grid_x": 68, + "grid_y": 132, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y77": { + "bits": {}, + "grid_x": 68, + "grid_y": 131, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y79": { + "bits": {}, + "grid_x": 68, + "grid_y": 129, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y8": { + "bits": {}, + "grid_x": 68, + "grid_y": 200, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y80": { + "bits": {}, + "grid_x": 68, + "grid_y": 128, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y81": { + "bits": {}, + "grid_x": 68, + "grid_y": 127, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y82": { + "bits": {}, + "grid_x": 68, + "grid_y": 126, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y83": { + "bits": {}, + "grid_x": 68, + "grid_y": 125, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y84": { + "bits": {}, + "grid_x": 68, + "grid_y": 124, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y85": { + "bits": {}, + "grid_x": 68, + "grid_y": 123, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y86": { + "bits": {}, + "grid_x": 68, + "grid_y": 122, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y87": { + "bits": {}, + "grid_x": 68, + "grid_y": 121, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y88": { + "bits": {}, + "grid_x": 68, + "grid_y": 120, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y89": { + "bits": {}, + "grid_x": 68, + "grid_y": 119, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y9": { + "bits": {}, + "grid_x": 68, + "grid_y": 199, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y90": { + "bits": {}, + "grid_x": 68, + "grid_y": 118, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y91": { + "bits": {}, + "grid_x": 68, + "grid_y": 117, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y92": { + "bits": {}, + "grid_x": 68, + "grid_y": 116, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y93": { + "bits": {}, + "grid_x": 68, + "grid_y": 115, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y94": { + "bits": {}, + "grid_x": 68, + "grid_y": 114, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y95": { + "bits": {}, + "grid_x": 68, + "grid_y": 113, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y96": { + "bits": {}, + "grid_x": 68, + "grid_y": 112, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y97": { + "bits": {}, + "grid_x": 68, + "grid_y": 111, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y98": { + "bits": {}, + "grid_x": 68, + "grid_y": 110, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X68Y99": { + "bits": {}, + "grid_x": 68, + "grid_y": 109, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y1": { + "bits": {}, + "grid_x": 82, + "grid_y": 207, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y10": { + "bits": {}, + "grid_x": 82, + "grid_y": 198, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y100": { + "bits": {}, + "grid_x": 82, + "grid_y": 108, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y101": { + "bits": {}, + "grid_x": 82, + "grid_y": 107, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y102": { + "bits": {}, + "grid_x": 82, + "grid_y": 106, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y103": { + "bits": {}, + "grid_x": 82, + "grid_y": 105, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y105": { + "bits": {}, + "grid_x": 82, + "grid_y": 103, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y106": { + "bits": {}, + "grid_x": 82, + "grid_y": 102, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y107": { + "bits": {}, + "grid_x": 82, + "grid_y": 101, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y108": { + "bits": {}, + "grid_x": 82, + "grid_y": 100, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y109": { + "bits": {}, + "grid_x": 82, + "grid_y": 99, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y11": { + "bits": {}, + "grid_x": 82, + "grid_y": 197, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y110": { + "bits": {}, + "grid_x": 82, + "grid_y": 98, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y111": { + "bits": {}, + "grid_x": 82, + "grid_y": 97, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y112": { + "bits": {}, + "grid_x": 82, + "grid_y": 96, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y113": { + "bits": {}, + "grid_x": 82, + "grid_y": 95, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y114": { + "bits": {}, + "grid_x": 82, + "grid_y": 94, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y115": { + "bits": {}, + "grid_x": 82, + "grid_y": 93, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y116": { + "bits": {}, + "grid_x": 82, + "grid_y": 92, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y117": { + "bits": {}, + "grid_x": 82, + "grid_y": 91, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y118": { + "bits": {}, + "grid_x": 82, + "grid_y": 90, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y119": { + "bits": {}, + "grid_x": 82, + "grid_y": 89, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y12": { + "bits": {}, + "grid_x": 82, + "grid_y": 196, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y120": { + "bits": {}, + "grid_x": 82, + "grid_y": 88, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y121": { + "bits": {}, + "grid_x": 82, + "grid_y": 87, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y122": { + "bits": {}, + "grid_x": 82, + "grid_y": 86, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y123": { + "bits": {}, + "grid_x": 82, + "grid_y": 85, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y124": { + "bits": {}, + "grid_x": 82, + "grid_y": 84, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y125": { + "bits": {}, + "grid_x": 82, + "grid_y": 83, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y126": { + "bits": {}, + "grid_x": 82, + "grid_y": 82, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y127": { + "bits": {}, + "grid_x": 82, + "grid_y": 81, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y128": { + "bits": {}, + "grid_x": 82, + "grid_y": 80, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y129": { + "bits": {}, + "grid_x": 82, + "grid_y": 79, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y13": { + "bits": {}, + "grid_x": 82, + "grid_y": 195, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y131": { + "bits": {}, + "grid_x": 82, + "grid_y": 77, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y132": { + "bits": {}, + "grid_x": 82, + "grid_y": 76, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y133": { + "bits": {}, + "grid_x": 82, + "grid_y": 75, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y134": { + "bits": {}, + "grid_x": 82, + "grid_y": 74, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y135": { + "bits": {}, + "grid_x": 82, + "grid_y": 73, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y136": { + "bits": {}, + "grid_x": 82, + "grid_y": 72, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y137": { + "bits": {}, + "grid_x": 82, + "grid_y": 71, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y138": { + "bits": {}, + "grid_x": 82, + "grid_y": 70, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y139": { + "bits": {}, + "grid_x": 82, + "grid_y": 69, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y14": { + "bits": {}, + "grid_x": 82, + "grid_y": 194, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y140": { + "bits": {}, + "grid_x": 82, + "grid_y": 68, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y141": { + "bits": {}, + "grid_x": 82, + "grid_y": 67, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y142": { + "bits": {}, + "grid_x": 82, + "grid_y": 66, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y143": { + "bits": {}, + "grid_x": 82, + "grid_y": 65, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y144": { + "bits": {}, + "grid_x": 82, + "grid_y": 64, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y145": { + "bits": {}, + "grid_x": 82, + "grid_y": 63, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y146": { + "bits": {}, + "grid_x": 82, + "grid_y": 62, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y147": { + "bits": {}, + "grid_x": 82, + "grid_y": 61, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y148": { + "bits": {}, + "grid_x": 82, + "grid_y": 60, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y149": { + "bits": {}, + "grid_x": 82, + "grid_y": 59, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y15": { + "bits": {}, + "grid_x": 82, + "grid_y": 193, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y150": { + "bits": {}, + "grid_x": 82, + "grid_y": 58, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y151": { + "bits": {}, + "grid_x": 82, + "grid_y": 57, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y152": { + "bits": {}, + "grid_x": 82, + "grid_y": 56, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y153": { + "bits": {}, + "grid_x": 82, + "grid_y": 55, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y154": { + "bits": {}, + "grid_x": 82, + "grid_y": 54, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y155": { + "bits": {}, + "grid_x": 82, + "grid_y": 53, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y157": { + "bits": {}, + "grid_x": 82, + "grid_y": 51, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y158": { + "bits": {}, + "grid_x": 82, + "grid_y": 50, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y159": { + "bits": {}, + "grid_x": 82, + "grid_y": 49, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y16": { + "bits": {}, + "grid_x": 82, + "grid_y": 192, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y160": { + "bits": {}, + "grid_x": 82, + "grid_y": 48, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y161": { + "bits": {}, + "grid_x": 82, + "grid_y": 47, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y162": { + "bits": {}, + "grid_x": 82, + "grid_y": 46, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y163": { + "bits": {}, + "grid_x": 82, + "grid_y": 45, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y164": { + "bits": {}, + "grid_x": 82, + "grid_y": 44, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y165": { + "bits": {}, + "grid_x": 82, + "grid_y": 43, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y166": { + "bits": {}, + "grid_x": 82, + "grid_y": 42, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y167": { + "bits": {}, + "grid_x": 82, + "grid_y": 41, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y168": { + "bits": {}, + "grid_x": 82, + "grid_y": 40, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y169": { + "bits": {}, + "grid_x": 82, + "grid_y": 39, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y17": { + "bits": {}, + "grid_x": 82, + "grid_y": 191, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y170": { + "bits": {}, + "grid_x": 82, + "grid_y": 38, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y171": { + "bits": {}, + "grid_x": 82, + "grid_y": 37, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y172": { + "bits": {}, + "grid_x": 82, + "grid_y": 36, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y173": { + "bits": {}, + "grid_x": 82, + "grid_y": 35, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y174": { + "bits": {}, + "grid_x": 82, + "grid_y": 34, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y175": { + "bits": {}, + "grid_x": 82, + "grid_y": 33, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y176": { + "bits": {}, + "grid_x": 82, + "grid_y": 32, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y177": { + "bits": {}, + "grid_x": 82, + "grid_y": 31, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y178": { + "bits": {}, + "grid_x": 82, + "grid_y": 30, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y179": { + "bits": {}, + "grid_x": 82, + "grid_y": 29, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y18": { + "bits": {}, + "grid_x": 82, + "grid_y": 190, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y180": { + "bits": {}, + "grid_x": 82, + "grid_y": 28, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y181": { + "bits": {}, + "grid_x": 82, + "grid_y": 27, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y183": { + "bits": {}, + "grid_x": 82, + "grid_y": 25, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y184": { + "bits": {}, + "grid_x": 82, + "grid_y": 24, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y185": { + "bits": {}, + "grid_x": 82, + "grid_y": 23, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y186": { + "bits": {}, + "grid_x": 82, + "grid_y": 22, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y187": { + "bits": {}, + "grid_x": 82, + "grid_y": 21, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y188": { + "bits": {}, + "grid_x": 82, + "grid_y": 20, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y189": { + "bits": {}, + "grid_x": 82, + "grid_y": 19, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y19": { + "bits": {}, + "grid_x": 82, + "grid_y": 189, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y190": { + "bits": {}, + "grid_x": 82, + "grid_y": 18, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y191": { + "bits": {}, + "grid_x": 82, + "grid_y": 17, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y192": { + "bits": {}, + "grid_x": 82, + "grid_y": 16, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y193": { + "bits": {}, + "grid_x": 82, + "grid_y": 15, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y194": { + "bits": {}, + "grid_x": 82, + "grid_y": 14, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y195": { + "bits": {}, + "grid_x": 82, + "grid_y": 13, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y196": { + "bits": {}, + "grid_x": 82, + "grid_y": 12, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y197": { + "bits": {}, + "grid_x": 82, + "grid_y": 11, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y198": { + "bits": {}, + "grid_x": 82, + "grid_y": 10, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y199": { + "bits": {}, + "grid_x": 82, + "grid_y": 9, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y2": { + "bits": {}, + "grid_x": 82, + "grid_y": 206, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y20": { + "bits": {}, + "grid_x": 82, + "grid_y": 188, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y200": { + "bits": {}, + "grid_x": 82, + "grid_y": 8, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y201": { + "bits": {}, + "grid_x": 82, + "grid_y": 7, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y202": { + "bits": {}, + "grid_x": 82, + "grid_y": 6, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y203": { + "bits": {}, + "grid_x": 82, + "grid_y": 5, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y204": { + "bits": {}, + "grid_x": 82, + "grid_y": 4, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y205": { + "bits": {}, + "grid_x": 82, + "grid_y": 3, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y206": { + "bits": {}, + "grid_x": 82, + "grid_y": 2, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y207": { + "bits": {}, + "grid_x": 82, + "grid_y": 1, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y21": { + "bits": {}, + "grid_x": 82, + "grid_y": 187, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y22": { + "bits": {}, + "grid_x": 82, + "grid_y": 186, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y23": { + "bits": {}, + "grid_x": 82, + "grid_y": 185, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y24": { + "bits": {}, + "grid_x": 82, + "grid_y": 184, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y25": { + "bits": {}, + "grid_x": 82, + "grid_y": 183, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y27": { + "bits": {}, + "grid_x": 82, + "grid_y": 181, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y28": { + "bits": {}, + "grid_x": 82, + "grid_y": 180, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y29": { + "bits": {}, + "grid_x": 82, + "grid_y": 179, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y3": { + "bits": {}, + "grid_x": 82, + "grid_y": 205, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y30": { + "bits": {}, + "grid_x": 82, + "grid_y": 178, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y31": { + "bits": {}, + "grid_x": 82, + "grid_y": 177, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y32": { + "bits": {}, + "grid_x": 82, + "grid_y": 176, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y33": { + "bits": {}, + "grid_x": 82, + "grid_y": 175, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y34": { + "bits": {}, + "grid_x": 82, + "grid_y": 174, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y35": { + "bits": {}, + "grid_x": 82, + "grid_y": 173, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y36": { + "bits": {}, + "grid_x": 82, + "grid_y": 172, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y37": { + "bits": {}, + "grid_x": 82, + "grid_y": 171, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y38": { + "bits": {}, + "grid_x": 82, + "grid_y": 170, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y39": { + "bits": {}, + "grid_x": 82, + "grid_y": 169, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y4": { + "bits": {}, + "grid_x": 82, + "grid_y": 204, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y40": { + "bits": {}, + "grid_x": 82, + "grid_y": 168, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y41": { + "bits": {}, + "grid_x": 82, + "grid_y": 167, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y42": { + "bits": {}, + "grid_x": 82, + "grid_y": 166, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y43": { + "bits": {}, + "grid_x": 82, + "grid_y": 165, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y44": { + "bits": {}, + "grid_x": 82, + "grid_y": 164, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y45": { + "bits": {}, + "grid_x": 82, + "grid_y": 163, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y46": { + "bits": {}, + "grid_x": 82, + "grid_y": 162, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y47": { + "bits": {}, + "grid_x": 82, + "grid_y": 161, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y48": { + "bits": {}, + "grid_x": 82, + "grid_y": 160, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y49": { + "bits": {}, + "grid_x": 82, + "grid_y": 159, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y5": { + "bits": {}, + "grid_x": 82, + "grid_y": 203, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y50": { + "bits": {}, + "grid_x": 82, + "grid_y": 158, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y51": { + "bits": {}, + "grid_x": 82, + "grid_y": 157, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y53": { + "bits": {}, + "grid_x": 82, + "grid_y": 155, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y54": { + "bits": {}, + "grid_x": 82, + "grid_y": 154, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y55": { + "bits": {}, + "grid_x": 82, + "grid_y": 153, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y56": { + "bits": {}, + "grid_x": 82, + "grid_y": 152, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y57": { + "bits": {}, + "grid_x": 82, + "grid_y": 151, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y58": { + "bits": {}, + "grid_x": 82, + "grid_y": 150, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y59": { + "bits": {}, + "grid_x": 82, + "grid_y": 149, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y6": { + "bits": {}, + "grid_x": 82, + "grid_y": 202, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y60": { + "bits": {}, + "grid_x": 82, + "grid_y": 148, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y61": { + "bits": {}, + "grid_x": 82, + "grid_y": 147, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y62": { + "bits": {}, + "grid_x": 82, + "grid_y": 146, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y63": { + "bits": {}, + "grid_x": 82, + "grid_y": 145, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y64": { + "bits": {}, + "grid_x": 82, + "grid_y": 144, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y65": { + "bits": {}, + "grid_x": 82, + "grid_y": 143, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y66": { + "bits": {}, + "grid_x": 82, + "grid_y": 142, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y67": { + "bits": {}, + "grid_x": 82, + "grid_y": 141, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y68": { + "bits": {}, + "grid_x": 82, + "grid_y": 140, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y69": { + "bits": {}, + "grid_x": 82, + "grid_y": 139, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y7": { + "bits": {}, + "grid_x": 82, + "grid_y": 201, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y70": { + "bits": {}, + "grid_x": 82, + "grid_y": 138, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y71": { + "bits": {}, + "grid_x": 82, + "grid_y": 137, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y72": { + "bits": {}, + "grid_x": 82, + "grid_y": 136, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y73": { + "bits": {}, + "grid_x": 82, + "grid_y": 135, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y74": { + "bits": {}, + "grid_x": 82, + "grid_y": 134, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y75": { + "bits": {}, + "grid_x": 82, + "grid_y": 133, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y76": { + "bits": {}, + "grid_x": 82, + "grid_y": 132, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y77": { + "bits": {}, + "grid_x": 82, + "grid_y": 131, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y79": { + "bits": {}, + "grid_x": 82, + "grid_y": 129, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y8": { + "bits": {}, + "grid_x": 82, + "grid_y": 200, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y80": { + "bits": {}, + "grid_x": 82, + "grid_y": 128, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y81": { + "bits": {}, + "grid_x": 82, + "grid_y": 127, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y82": { + "bits": {}, + "grid_x": 82, + "grid_y": 126, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y83": { + "bits": {}, + "grid_x": 82, + "grid_y": 125, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y84": { + "bits": {}, + "grid_x": 82, + "grid_y": 124, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y85": { + "bits": {}, + "grid_x": 82, + "grid_y": 123, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y86": { + "bits": {}, + "grid_x": 82, + "grid_y": 122, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y87": { + "bits": {}, + "grid_x": 82, + "grid_y": 121, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y88": { + "bits": {}, + "grid_x": 82, + "grid_y": 120, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y89": { + "bits": {}, + "grid_x": 82, + "grid_y": 119, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y9": { + "bits": {}, + "grid_x": 82, + "grid_y": 199, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y90": { + "bits": {}, + "grid_x": 82, + "grid_y": 118, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y91": { + "bits": {}, + "grid_x": 82, + "grid_y": 117, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y92": { + "bits": {}, + "grid_x": 82, + "grid_y": 116, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y93": { + "bits": {}, + "grid_x": 82, + "grid_y": 115, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y94": { + "bits": {}, + "grid_x": 82, + "grid_y": 114, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y95": { + "bits": {}, + "grid_x": 82, + "grid_y": 113, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y96": { + "bits": {}, + "grid_x": 82, + "grid_y": 112, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y97": { + "bits": {}, + "grid_x": 82, + "grid_y": 111, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y98": { + "bits": {}, + "grid_x": 82, + "grid_y": 110, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X82Y99": { + "bits": {}, + "grid_x": 82, + "grid_y": 109, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y1": { + "bits": {}, + "grid_x": 92, + "grid_y": 207, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y10": { + "bits": {}, + "grid_x": 92, + "grid_y": 198, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y100": { + "bits": {}, + "grid_x": 92, + "grid_y": 108, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y101": { + "bits": {}, + "grid_x": 92, + "grid_y": 107, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y102": { + "bits": {}, + "grid_x": 92, + "grid_y": 106, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y103": { + "bits": {}, + "grid_x": 92, + "grid_y": 105, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y105": { + "bits": {}, + "grid_x": 92, + "grid_y": 103, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y106": { + "bits": {}, + "grid_x": 92, + "grid_y": 102, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y107": { + "bits": {}, + "grid_x": 92, + "grid_y": 101, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y108": { + "bits": {}, + "grid_x": 92, + "grid_y": 100, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y109": { + "bits": {}, + "grid_x": 92, + "grid_y": 99, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y11": { + "bits": {}, + "grid_x": 92, + "grid_y": 197, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y110": { + "bits": {}, + "grid_x": 92, + "grid_y": 98, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y111": { + "bits": {}, + "grid_x": 92, + "grid_y": 97, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y112": { + "bits": {}, + "grid_x": 92, + "grid_y": 96, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y113": { + "bits": {}, + "grid_x": 92, + "grid_y": 95, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y114": { + "bits": {}, + "grid_x": 92, + "grid_y": 94, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y115": { + "bits": {}, + "grid_x": 92, + "grid_y": 93, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y116": { + "bits": {}, + "grid_x": 92, + "grid_y": 92, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y117": { + "bits": {}, + "grid_x": 92, + "grid_y": 91, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y118": { + "bits": {}, + "grid_x": 92, + "grid_y": 90, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y119": { + "bits": {}, + "grid_x": 92, + "grid_y": 89, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y12": { + "bits": {}, + "grid_x": 92, + "grid_y": 196, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y120": { + "bits": {}, + "grid_x": 92, + "grid_y": 88, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y121": { + "bits": {}, + "grid_x": 92, + "grid_y": 87, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y122": { + "bits": {}, + "grid_x": 92, + "grid_y": 86, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y123": { + "bits": {}, + "grid_x": 92, + "grid_y": 85, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y124": { + "bits": {}, + "grid_x": 92, + "grid_y": 84, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y125": { + "bits": {}, + "grid_x": 92, + "grid_y": 83, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y126": { + "bits": {}, + "grid_x": 92, + "grid_y": 82, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y127": { + "bits": {}, + "grid_x": 92, + "grid_y": 81, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y128": { + "bits": {}, + "grid_x": 92, + "grid_y": 80, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y129": { + "bits": {}, + "grid_x": 92, + "grid_y": 79, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y13": { + "bits": {}, + "grid_x": 92, + "grid_y": 195, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y131": { + "bits": {}, + "grid_x": 92, + "grid_y": 77, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y132": { + "bits": {}, + "grid_x": 92, + "grid_y": 76, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y133": { + "bits": {}, + "grid_x": 92, + "grid_y": 75, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y134": { + "bits": {}, + "grid_x": 92, + "grid_y": 74, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y135": { + "bits": {}, + "grid_x": 92, + "grid_y": 73, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y136": { + "bits": {}, + "grid_x": 92, + "grid_y": 72, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y137": { + "bits": {}, + "grid_x": 92, + "grid_y": 71, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y138": { + "bits": {}, + "grid_x": 92, + "grid_y": 70, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y139": { + "bits": {}, + "grid_x": 92, + "grid_y": 69, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y14": { + "bits": {}, + "grid_x": 92, + "grid_y": 194, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y140": { + "bits": {}, + "grid_x": 92, + "grid_y": 68, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y141": { + "bits": {}, + "grid_x": 92, + "grid_y": 67, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y142": { + "bits": {}, + "grid_x": 92, + "grid_y": 66, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y143": { + "bits": {}, + "grid_x": 92, + "grid_y": 65, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y144": { + "bits": {}, + "grid_x": 92, + "grid_y": 64, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y145": { + "bits": {}, + "grid_x": 92, + "grid_y": 63, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y146": { + "bits": {}, + "grid_x": 92, + "grid_y": 62, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y147": { + "bits": {}, + "grid_x": 92, + "grid_y": 61, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y148": { + "bits": {}, + "grid_x": 92, + "grid_y": 60, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y149": { + "bits": {}, + "grid_x": 92, + "grid_y": 59, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y15": { + "bits": {}, + "grid_x": 92, + "grid_y": 193, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y150": { + "bits": {}, + "grid_x": 92, + "grid_y": 58, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y151": { + "bits": {}, + "grid_x": 92, + "grid_y": 57, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y152": { + "bits": {}, + "grid_x": 92, + "grid_y": 56, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y153": { + "bits": {}, + "grid_x": 92, + "grid_y": 55, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y154": { + "bits": {}, + "grid_x": 92, + "grid_y": 54, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y155": { + "bits": {}, + "grid_x": 92, + "grid_y": 53, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y157": { + "bits": {}, + "grid_x": 92, + "grid_y": 51, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y158": { + "bits": {}, + "grid_x": 92, + "grid_y": 50, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y159": { + "bits": {}, + "grid_x": 92, + "grid_y": 49, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y16": { + "bits": {}, + "grid_x": 92, + "grid_y": 192, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y160": { + "bits": {}, + "grid_x": 92, + "grid_y": 48, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y161": { + "bits": {}, + "grid_x": 92, + "grid_y": 47, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y162": { + "bits": {}, + "grid_x": 92, + "grid_y": 46, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y163": { + "bits": {}, + "grid_x": 92, + "grid_y": 45, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y164": { + "bits": {}, + "grid_x": 92, + "grid_y": 44, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y165": { + "bits": {}, + "grid_x": 92, + "grid_y": 43, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y166": { + "bits": {}, + "grid_x": 92, + "grid_y": 42, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y167": { + "bits": {}, + "grid_x": 92, + "grid_y": 41, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y168": { + "bits": {}, + "grid_x": 92, + "grid_y": 40, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y169": { + "bits": {}, + "grid_x": 92, + "grid_y": 39, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y17": { + "bits": {}, + "grid_x": 92, + "grid_y": 191, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y170": { + "bits": {}, + "grid_x": 92, + "grid_y": 38, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y171": { + "bits": {}, + "grid_x": 92, + "grid_y": 37, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y172": { + "bits": {}, + "grid_x": 92, + "grid_y": 36, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y173": { + "bits": {}, + "grid_x": 92, + "grid_y": 35, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y174": { + "bits": {}, + "grid_x": 92, + "grid_y": 34, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y175": { + "bits": {}, + "grid_x": 92, + "grid_y": 33, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y176": { + "bits": {}, + "grid_x": 92, + "grid_y": 32, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y177": { + "bits": {}, + "grid_x": 92, + "grid_y": 31, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y178": { + "bits": {}, + "grid_x": 92, + "grid_y": 30, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y179": { + "bits": {}, + "grid_x": 92, + "grid_y": 29, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y18": { + "bits": {}, + "grid_x": 92, + "grid_y": 190, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y180": { + "bits": {}, + "grid_x": 92, + "grid_y": 28, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y181": { + "bits": {}, + "grid_x": 92, + "grid_y": 27, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y183": { + "bits": {}, + "grid_x": 92, + "grid_y": 25, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y184": { + "bits": {}, + "grid_x": 92, + "grid_y": 24, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y185": { + "bits": {}, + "grid_x": 92, + "grid_y": 23, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y186": { + "bits": {}, + "grid_x": 92, + "grid_y": 22, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y187": { + "bits": {}, + "grid_x": 92, + "grid_y": 21, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y188": { + "bits": {}, + "grid_x": 92, + "grid_y": 20, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y189": { + "bits": {}, + "grid_x": 92, + "grid_y": 19, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y19": { + "bits": {}, + "grid_x": 92, + "grid_y": 189, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y190": { + "bits": {}, + "grid_x": 92, + "grid_y": 18, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y191": { + "bits": {}, + "grid_x": 92, + "grid_y": 17, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y192": { + "bits": {}, + "grid_x": 92, + "grid_y": 16, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y193": { + "bits": {}, + "grid_x": 92, + "grid_y": 15, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y194": { + "bits": {}, + "grid_x": 92, + "grid_y": 14, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y195": { + "bits": {}, + "grid_x": 92, + "grid_y": 13, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y196": { + "bits": {}, + "grid_x": 92, + "grid_y": 12, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y197": { + "bits": {}, + "grid_x": 92, + "grid_y": 11, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y198": { + "bits": {}, + "grid_x": 92, + "grid_y": 10, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y199": { + "bits": {}, + "grid_x": 92, + "grid_y": 9, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y2": { + "bits": {}, + "grid_x": 92, + "grid_y": 206, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y20": { + "bits": {}, + "grid_x": 92, + "grid_y": 188, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y200": { + "bits": {}, + "grid_x": 92, + "grid_y": 8, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y201": { + "bits": {}, + "grid_x": 92, + "grid_y": 7, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y202": { + "bits": {}, + "grid_x": 92, + "grid_y": 6, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y203": { + "bits": {}, + "grid_x": 92, + "grid_y": 5, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y204": { + "bits": {}, + "grid_x": 92, + "grid_y": 4, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y205": { + "bits": {}, + "grid_x": 92, + "grid_y": 3, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y206": { + "bits": {}, + "grid_x": 92, + "grid_y": 2, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y207": { + "bits": {}, + "grid_x": 92, + "grid_y": 1, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y21": { + "bits": {}, + "grid_x": 92, + "grid_y": 187, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y22": { + "bits": {}, + "grid_x": 92, + "grid_y": 186, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y23": { + "bits": {}, + "grid_x": 92, + "grid_y": 185, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y24": { + "bits": {}, + "grid_x": 92, + "grid_y": 184, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y25": { + "bits": {}, + "grid_x": 92, + "grid_y": 183, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y27": { + "bits": {}, + "grid_x": 92, + "grid_y": 181, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y28": { + "bits": {}, + "grid_x": 92, + "grid_y": 180, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y29": { + "bits": {}, + "grid_x": 92, + "grid_y": 179, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y3": { + "bits": {}, + "grid_x": 92, + "grid_y": 205, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y30": { + "bits": {}, + "grid_x": 92, + "grid_y": 178, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y31": { + "bits": {}, + "grid_x": 92, + "grid_y": 177, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y32": { + "bits": {}, + "grid_x": 92, + "grid_y": 176, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y33": { + "bits": {}, + "grid_x": 92, + "grid_y": 175, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y34": { + "bits": {}, + "grid_x": 92, + "grid_y": 174, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y35": { + "bits": {}, + "grid_x": 92, + "grid_y": 173, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y36": { + "bits": {}, + "grid_x": 92, + "grid_y": 172, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y37": { + "bits": {}, + "grid_x": 92, + "grid_y": 171, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y38": { + "bits": {}, + "grid_x": 92, + "grid_y": 170, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y39": { + "bits": {}, + "grid_x": 92, + "grid_y": 169, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y4": { + "bits": {}, + "grid_x": 92, + "grid_y": 204, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y40": { + "bits": {}, + "grid_x": 92, + "grid_y": 168, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y41": { + "bits": {}, + "grid_x": 92, + "grid_y": 167, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y42": { + "bits": {}, + "grid_x": 92, + "grid_y": 166, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y43": { + "bits": {}, + "grid_x": 92, + "grid_y": 165, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y44": { + "bits": {}, + "grid_x": 92, + "grid_y": 164, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y45": { + "bits": {}, + "grid_x": 92, + "grid_y": 163, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y46": { + "bits": {}, + "grid_x": 92, + "grid_y": 162, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y47": { + "bits": {}, + "grid_x": 92, + "grid_y": 161, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y48": { + "bits": {}, + "grid_x": 92, + "grid_y": 160, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y49": { + "bits": {}, + "grid_x": 92, + "grid_y": 159, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y5": { + "bits": {}, + "grid_x": 92, + "grid_y": 203, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y50": { + "bits": {}, + "grid_x": 92, + "grid_y": 158, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y51": { + "bits": {}, + "grid_x": 92, + "grid_y": 157, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y53": { + "bits": {}, + "grid_x": 92, + "grid_y": 155, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y54": { + "bits": {}, + "grid_x": 92, + "grid_y": 154, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y55": { + "bits": {}, + "grid_x": 92, + "grid_y": 153, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y56": { + "bits": {}, + "grid_x": 92, + "grid_y": 152, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y57": { + "bits": {}, + "grid_x": 92, + "grid_y": 151, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y58": { + "bits": {}, + "grid_x": 92, + "grid_y": 150, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y59": { + "bits": {}, + "grid_x": 92, + "grid_y": 149, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y6": { + "bits": {}, + "grid_x": 92, + "grid_y": 202, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y60": { + "bits": {}, + "grid_x": 92, + "grid_y": 148, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y61": { + "bits": {}, + "grid_x": 92, + "grid_y": 147, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y62": { + "bits": {}, + "grid_x": 92, + "grid_y": 146, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y63": { + "bits": {}, + "grid_x": 92, + "grid_y": 145, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y64": { + "bits": {}, + "grid_x": 92, + "grid_y": 144, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y65": { + "bits": {}, + "grid_x": 92, + "grid_y": 143, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y66": { + "bits": {}, + "grid_x": 92, + "grid_y": 142, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y67": { + "bits": {}, + "grid_x": 92, + "grid_y": 141, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y68": { + "bits": {}, + "grid_x": 92, + "grid_y": 140, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y69": { + "bits": {}, + "grid_x": 92, + "grid_y": 139, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y7": { + "bits": {}, + "grid_x": 92, + "grid_y": 201, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y70": { + "bits": {}, + "grid_x": 92, + "grid_y": 138, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y71": { + "bits": {}, + "grid_x": 92, + "grid_y": 137, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y72": { + "bits": {}, + "grid_x": 92, + "grid_y": 136, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y73": { + "bits": {}, + "grid_x": 92, + "grid_y": 135, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y74": { + "bits": {}, + "grid_x": 92, + "grid_y": 134, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y75": { + "bits": {}, + "grid_x": 92, + "grid_y": 133, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y76": { + "bits": {}, + "grid_x": 92, + "grid_y": 132, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y77": { + "bits": {}, + "grid_x": 92, + "grid_y": 131, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y79": { + "bits": {}, + "grid_x": 92, + "grid_y": 129, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y8": { + "bits": {}, + "grid_x": 92, + "grid_y": 200, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y80": { + "bits": {}, + "grid_x": 92, + "grid_y": 128, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y81": { + "bits": {}, + "grid_x": 92, + "grid_y": 127, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y82": { + "bits": {}, + "grid_x": 92, + "grid_y": 126, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y83": { + "bits": {}, + "grid_x": 92, + "grid_y": 125, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y84": { + "bits": {}, + "grid_x": 92, + "grid_y": 124, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y85": { + "bits": {}, + "grid_x": 92, + "grid_y": 123, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y86": { + "bits": {}, + "grid_x": 92, + "grid_y": 122, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y87": { + "bits": {}, + "grid_x": 92, + "grid_y": 121, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y88": { + "bits": {}, + "grid_x": 92, + "grid_y": 120, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y89": { + "bits": {}, + "grid_x": 92, + "grid_y": 119, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y9": { + "bits": {}, + "grid_x": 92, + "grid_y": 199, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y90": { + "bits": {}, + "grid_x": 92, + "grid_y": 118, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y91": { + "bits": {}, + "grid_x": 92, + "grid_y": 117, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y92": { + "bits": {}, + "grid_x": 92, + "grid_y": 116, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y93": { + "bits": {}, + "grid_x": 92, + "grid_y": 115, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y94": { + "bits": {}, + "grid_x": 92, + "grid_y": 114, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y95": { + "bits": {}, + "grid_x": 92, + "grid_y": 113, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y96": { + "bits": {}, + "grid_x": 92, + "grid_y": 112, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y97": { + "bits": {}, + "grid_x": 92, + "grid_y": 111, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y98": { + "bits": {}, + "grid_x": 92, + "grid_y": 110, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X92Y99": { + "bits": {}, + "grid_x": 92, + "grid_y": 109, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y1": { + "bits": {}, + "grid_x": 98, + "grid_y": 207, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y10": { + "bits": {}, + "grid_x": 98, + "grid_y": 198, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y100": { + "bits": {}, + "grid_x": 98, + "grid_y": 108, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y101": { + "bits": {}, + "grid_x": 98, + "grid_y": 107, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y102": { + "bits": {}, + "grid_x": 98, + "grid_y": 106, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y103": { + "bits": {}, + "grid_x": 98, + "grid_y": 105, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y11": { + "bits": {}, + "grid_x": 98, + "grid_y": 197, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y12": { + "bits": {}, + "grid_x": 98, + "grid_y": 196, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y13": { + "bits": {}, + "grid_x": 98, + "grid_y": 195, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y14": { + "bits": {}, + "grid_x": 98, + "grid_y": 194, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y15": { + "bits": {}, + "grid_x": 98, + "grid_y": 193, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y16": { + "bits": {}, + "grid_x": 98, + "grid_y": 192, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y17": { + "bits": {}, + "grid_x": 98, + "grid_y": 191, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y18": { + "bits": {}, + "grid_x": 98, + "grid_y": 190, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y19": { + "bits": {}, + "grid_x": 98, + "grid_y": 189, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y2": { + "bits": {}, + "grid_x": 98, + "grid_y": 206, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y20": { + "bits": {}, + "grid_x": 98, + "grid_y": 188, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y21": { + "bits": {}, + "grid_x": 98, + "grid_y": 187, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y22": { + "bits": {}, + "grid_x": 98, + "grid_y": 186, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y23": { + "bits": {}, + "grid_x": 98, + "grid_y": 185, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y24": { + "bits": {}, + "grid_x": 98, + "grid_y": 184, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y25": { + "bits": {}, + "grid_x": 98, + "grid_y": 183, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y27": { + "bits": {}, + "grid_x": 98, + "grid_y": 181, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y28": { + "bits": {}, + "grid_x": 98, + "grid_y": 180, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y29": { + "bits": {}, + "grid_x": 98, + "grid_y": 179, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y3": { + "bits": {}, + "grid_x": 98, + "grid_y": 205, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y30": { + "bits": {}, + "grid_x": 98, + "grid_y": 178, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y31": { + "bits": {}, + "grid_x": 98, + "grid_y": 177, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y32": { + "bits": {}, + "grid_x": 98, + "grid_y": 176, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y33": { + "bits": {}, + "grid_x": 98, + "grid_y": 175, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y34": { + "bits": {}, + "grid_x": 98, + "grid_y": 174, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y35": { + "bits": {}, + "grid_x": 98, + "grid_y": 173, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y36": { + "bits": {}, + "grid_x": 98, + "grid_y": 172, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y37": { + "bits": {}, + "grid_x": 98, + "grid_y": 171, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y38": { + "bits": {}, + "grid_x": 98, + "grid_y": 170, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y39": { + "bits": {}, + "grid_x": 98, + "grid_y": 169, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y4": { + "bits": {}, + "grid_x": 98, + "grid_y": 204, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y40": { + "bits": {}, + "grid_x": 98, + "grid_y": 168, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y41": { + "bits": {}, + "grid_x": 98, + "grid_y": 167, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y42": { + "bits": {}, + "grid_x": 98, + "grid_y": 166, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y43": { + "bits": {}, + "grid_x": 98, + "grid_y": 165, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y44": { + "bits": {}, + "grid_x": 98, + "grid_y": 164, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y45": { + "bits": {}, + "grid_x": 98, + "grid_y": 163, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y46": { + "bits": {}, + "grid_x": 98, + "grid_y": 162, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y47": { + "bits": {}, + "grid_x": 98, + "grid_y": 161, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y48": { + "bits": {}, + "grid_x": 98, + "grid_y": 160, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y49": { + "bits": {}, + "grid_x": 98, + "grid_y": 159, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y5": { + "bits": {}, + "grid_x": 98, + "grid_y": 203, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y50": { + "bits": {}, + "grid_x": 98, + "grid_y": 158, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y51": { + "bits": {}, + "grid_x": 98, + "grid_y": 157, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y53": { + "bits": {}, + "grid_x": 98, + "grid_y": 155, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y54": { + "bits": {}, + "grid_x": 98, + "grid_y": 154, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y55": { + "bits": {}, + "grid_x": 98, + "grid_y": 153, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y56": { + "bits": {}, + "grid_x": 98, + "grid_y": 152, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y57": { + "bits": {}, + "grid_x": 98, + "grid_y": 151, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y58": { + "bits": {}, + "grid_x": 98, + "grid_y": 150, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y59": { + "bits": {}, + "grid_x": 98, + "grid_y": 149, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y6": { + "bits": {}, + "grid_x": 98, + "grid_y": 202, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y60": { + "bits": {}, + "grid_x": 98, + "grid_y": 148, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y61": { + "bits": {}, + "grid_x": 98, + "grid_y": 147, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y62": { + "bits": {}, + "grid_x": 98, + "grid_y": 146, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y63": { + "bits": {}, + "grid_x": 98, + "grid_y": 145, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y64": { + "bits": {}, + "grid_x": 98, + "grid_y": 144, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y65": { + "bits": {}, + "grid_x": 98, + "grid_y": 143, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y66": { + "bits": {}, + "grid_x": 98, + "grid_y": 142, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y67": { + "bits": {}, + "grid_x": 98, + "grid_y": 141, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y68": { + "bits": {}, + "grid_x": 98, + "grid_y": 140, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y69": { + "bits": {}, + "grid_x": 98, + "grid_y": 139, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y7": { + "bits": {}, + "grid_x": 98, + "grid_y": 201, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y70": { + "bits": {}, + "grid_x": 98, + "grid_y": 138, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y71": { + "bits": {}, + "grid_x": 98, + "grid_y": 137, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y72": { + "bits": {}, + "grid_x": 98, + "grid_y": 136, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y73": { + "bits": {}, + "grid_x": 98, + "grid_y": 135, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y74": { + "bits": {}, + "grid_x": 98, + "grid_y": 134, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y75": { + "bits": {}, + "grid_x": 98, + "grid_y": 133, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y76": { + "bits": {}, + "grid_x": 98, + "grid_y": 132, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y77": { + "bits": {}, + "grid_x": 98, + "grid_y": 131, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y79": { + "bits": {}, + "grid_x": 98, + "grid_y": 129, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y8": { + "bits": {}, + "grid_x": 98, + "grid_y": 200, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y80": { + "bits": {}, + "grid_x": 98, + "grid_y": 128, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y81": { + "bits": {}, + "grid_x": 98, + "grid_y": 127, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y82": { + "bits": {}, + "grid_x": 98, + "grid_y": 126, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y83": { + "bits": {}, + "grid_x": 98, + "grid_y": 125, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y84": { + "bits": {}, + "grid_x": 98, + "grid_y": 124, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y85": { + "bits": {}, + "grid_x": 98, + "grid_y": 123, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y86": { + "bits": {}, + "grid_x": 98, + "grid_y": 122, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y87": { + "bits": {}, + "grid_x": 98, + "grid_y": 121, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y88": { + "bits": {}, + "grid_x": 98, + "grid_y": 120, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y89": { + "bits": {}, + "grid_x": 98, + "grid_y": 119, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y9": { + "bits": {}, + "grid_x": 98, + "grid_y": 199, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y90": { + "bits": {}, + "grid_x": 98, + "grid_y": 118, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y91": { + "bits": {}, + "grid_x": 98, + "grid_y": 117, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y92": { + "bits": {}, + "grid_x": 98, + "grid_y": 116, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y93": { + "bits": {}, + "grid_x": 98, + "grid_y": 115, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y94": { + "bits": {}, + "grid_x": 98, + "grid_y": 114, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y95": { + "bits": {}, + "grid_x": 98, + "grid_y": 113, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y96": { + "bits": {}, + "grid_x": 98, + "grid_y": 112, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y97": { + "bits": {}, + "grid_x": 98, + "grid_y": 111, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y98": { + "bits": {}, + "grid_x": 98, + "grid_y": 110, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X98Y99": { + "bits": {}, + "grid_x": 98, + "grid_y": 109, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y1": { + "bits": {}, + "grid_x": 9, + "grid_y": 207, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y10": { + "bits": {}, + "grid_x": 9, + "grid_y": 198, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y100": { + "bits": {}, + "grid_x": 9, + "grid_y": 108, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y101": { + "bits": {}, + "grid_x": 9, + "grid_y": 107, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y102": { + "bits": {}, + "grid_x": 9, + "grid_y": 106, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y103": { + "bits": {}, + "grid_x": 9, + "grid_y": 105, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y105": { + "bits": {}, + "grid_x": 9, + "grid_y": 103, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y106": { + "bits": {}, + "grid_x": 9, + "grid_y": 102, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y107": { + "bits": {}, + "grid_x": 9, + "grid_y": 101, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y108": { + "bits": {}, + "grid_x": 9, + "grid_y": 100, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y109": { + "bits": {}, + "grid_x": 9, + "grid_y": 99, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y11": { + "bits": {}, + "grid_x": 9, + "grid_y": 197, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y110": { + "bits": {}, + "grid_x": 9, + "grid_y": 98, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y111": { + "bits": {}, + "grid_x": 9, + "grid_y": 97, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y112": { + "bits": {}, + "grid_x": 9, + "grid_y": 96, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y113": { + "bits": {}, + "grid_x": 9, + "grid_y": 95, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y114": { + "bits": {}, + "grid_x": 9, + "grid_y": 94, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y115": { + "bits": {}, + "grid_x": 9, + "grid_y": 93, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y116": { + "bits": {}, + "grid_x": 9, + "grid_y": 92, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y117": { + "bits": {}, + "grid_x": 9, + "grid_y": 91, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y118": { + "bits": {}, + "grid_x": 9, + "grid_y": 90, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y119": { + "bits": {}, + "grid_x": 9, + "grid_y": 89, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y12": { + "bits": {}, + "grid_x": 9, + "grid_y": 196, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y120": { + "bits": {}, + "grid_x": 9, + "grid_y": 88, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y121": { + "bits": {}, + "grid_x": 9, + "grid_y": 87, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y122": { + "bits": {}, + "grid_x": 9, + "grid_y": 86, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y123": { + "bits": {}, + "grid_x": 9, + "grid_y": 85, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y124": { + "bits": {}, + "grid_x": 9, + "grid_y": 84, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y125": { + "bits": {}, + "grid_x": 9, + "grid_y": 83, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y126": { + "bits": {}, + "grid_x": 9, + "grid_y": 82, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y127": { + "bits": {}, + "grid_x": 9, + "grid_y": 81, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y128": { + "bits": {}, + "grid_x": 9, + "grid_y": 80, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y129": { + "bits": {}, + "grid_x": 9, + "grid_y": 79, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y13": { + "bits": {}, + "grid_x": 9, + "grid_y": 195, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y131": { + "bits": {}, + "grid_x": 9, + "grid_y": 77, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y132": { + "bits": {}, + "grid_x": 9, + "grid_y": 76, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y133": { + "bits": {}, + "grid_x": 9, + "grid_y": 75, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y134": { + "bits": {}, + "grid_x": 9, + "grid_y": 74, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y135": { + "bits": {}, + "grid_x": 9, + "grid_y": 73, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y136": { + "bits": {}, + "grid_x": 9, + "grid_y": 72, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y137": { + "bits": {}, + "grid_x": 9, + "grid_y": 71, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y138": { + "bits": {}, + "grid_x": 9, + "grid_y": 70, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y139": { + "bits": {}, + "grid_x": 9, + "grid_y": 69, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y14": { + "bits": {}, + "grid_x": 9, + "grid_y": 194, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y140": { + "bits": {}, + "grid_x": 9, + "grid_y": 68, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y141": { + "bits": {}, + "grid_x": 9, + "grid_y": 67, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y142": { + "bits": {}, + "grid_x": 9, + "grid_y": 66, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y143": { + "bits": {}, + "grid_x": 9, + "grid_y": 65, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y144": { + "bits": {}, + "grid_x": 9, + "grid_y": 64, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y145": { + "bits": {}, + "grid_x": 9, + "grid_y": 63, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y146": { + "bits": {}, + "grid_x": 9, + "grid_y": 62, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y147": { + "bits": {}, + "grid_x": 9, + "grid_y": 61, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y148": { + "bits": {}, + "grid_x": 9, + "grid_y": 60, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y149": { + "bits": {}, + "grid_x": 9, + "grid_y": 59, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y15": { + "bits": {}, + "grid_x": 9, + "grid_y": 193, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y150": { + "bits": {}, + "grid_x": 9, + "grid_y": 58, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y151": { + "bits": {}, + "grid_x": 9, + "grid_y": 57, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y152": { + "bits": {}, + "grid_x": 9, + "grid_y": 56, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y153": { + "bits": {}, + "grid_x": 9, + "grid_y": 55, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y154": { + "bits": {}, + "grid_x": 9, + "grid_y": 54, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y155": { + "bits": {}, + "grid_x": 9, + "grid_y": 53, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y157": { + "bits": {}, + "grid_x": 9, + "grid_y": 51, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y158": { + "bits": {}, + "grid_x": 9, + "grid_y": 50, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y159": { + "bits": {}, + "grid_x": 9, + "grid_y": 49, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y16": { + "bits": {}, + "grid_x": 9, + "grid_y": 192, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y160": { + "bits": {}, + "grid_x": 9, + "grid_y": 48, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y161": { + "bits": {}, + "grid_x": 9, + "grid_y": 47, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y162": { + "bits": {}, + "grid_x": 9, + "grid_y": 46, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y163": { + "bits": {}, + "grid_x": 9, + "grid_y": 45, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y164": { + "bits": {}, + "grid_x": 9, + "grid_y": 44, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y165": { + "bits": {}, + "grid_x": 9, + "grid_y": 43, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y166": { + "bits": {}, + "grid_x": 9, + "grid_y": 42, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y167": { + "bits": {}, + "grid_x": 9, + "grid_y": 41, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y168": { + "bits": {}, + "grid_x": 9, + "grid_y": 40, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y169": { + "bits": {}, + "grid_x": 9, + "grid_y": 39, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y17": { + "bits": {}, + "grid_x": 9, + "grid_y": 191, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y170": { + "bits": {}, + "grid_x": 9, + "grid_y": 38, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y171": { + "bits": {}, + "grid_x": 9, + "grid_y": 37, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y172": { + "bits": {}, + "grid_x": 9, + "grid_y": 36, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y173": { + "bits": {}, + "grid_x": 9, + "grid_y": 35, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y174": { + "bits": {}, + "grid_x": 9, + "grid_y": 34, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y175": { + "bits": {}, + "grid_x": 9, + "grid_y": 33, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y176": { + "bits": {}, + "grid_x": 9, + "grid_y": 32, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y177": { + "bits": {}, + "grid_x": 9, + "grid_y": 31, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y178": { + "bits": {}, + "grid_x": 9, + "grid_y": 30, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y179": { + "bits": {}, + "grid_x": 9, + "grid_y": 29, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y18": { + "bits": {}, + "grid_x": 9, + "grid_y": 190, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y180": { + "bits": {}, + "grid_x": 9, + "grid_y": 28, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y181": { + "bits": {}, + "grid_x": 9, + "grid_y": 27, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y183": { + "bits": {}, + "grid_x": 9, + "grid_y": 25, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y184": { + "bits": {}, + "grid_x": 9, + "grid_y": 24, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y185": { + "bits": {}, + "grid_x": 9, + "grid_y": 23, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y186": { + "bits": {}, + "grid_x": 9, + "grid_y": 22, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y187": { + "bits": {}, + "grid_x": 9, + "grid_y": 21, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y188": { + "bits": {}, + "grid_x": 9, + "grid_y": 20, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y189": { + "bits": {}, + "grid_x": 9, + "grid_y": 19, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y19": { + "bits": {}, + "grid_x": 9, + "grid_y": 189, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y190": { + "bits": {}, + "grid_x": 9, + "grid_y": 18, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y191": { + "bits": {}, + "grid_x": 9, + "grid_y": 17, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y192": { + "bits": {}, + "grid_x": 9, + "grid_y": 16, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y193": { + "bits": {}, + "grid_x": 9, + "grid_y": 15, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y194": { + "bits": {}, + "grid_x": 9, + "grid_y": 14, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y195": { + "bits": {}, + "grid_x": 9, + "grid_y": 13, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y196": { + "bits": {}, + "grid_x": 9, + "grid_y": 12, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y197": { + "bits": {}, + "grid_x": 9, + "grid_y": 11, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y198": { + "bits": {}, + "grid_x": 9, + "grid_y": 10, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y199": { + "bits": {}, + "grid_x": 9, + "grid_y": 9, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y2": { + "bits": {}, + "grid_x": 9, + "grid_y": 206, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y20": { + "bits": {}, + "grid_x": 9, + "grid_y": 188, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y200": { + "bits": {}, + "grid_x": 9, + "grid_y": 8, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y201": { + "bits": {}, + "grid_x": 9, + "grid_y": 7, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y202": { + "bits": {}, + "grid_x": 9, + "grid_y": 6, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y203": { + "bits": {}, + "grid_x": 9, + "grid_y": 5, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y204": { + "bits": {}, + "grid_x": 9, + "grid_y": 4, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y205": { + "bits": {}, + "grid_x": 9, + "grid_y": 3, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y206": { + "bits": {}, + "grid_x": 9, + "grid_y": 2, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y207": { + "bits": {}, + "grid_x": 9, + "grid_y": 1, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y21": { + "bits": {}, + "grid_x": 9, + "grid_y": 187, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y22": { + "bits": {}, + "grid_x": 9, + "grid_y": 186, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y23": { + "bits": {}, + "grid_x": 9, + "grid_y": 185, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y24": { + "bits": {}, + "grid_x": 9, + "grid_y": 184, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y25": { + "bits": {}, + "grid_x": 9, + "grid_y": 183, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y27": { + "bits": {}, + "grid_x": 9, + "grid_y": 181, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y28": { + "bits": {}, + "grid_x": 9, + "grid_y": 180, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y29": { + "bits": {}, + "grid_x": 9, + "grid_y": 179, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y3": { + "bits": {}, + "grid_x": 9, + "grid_y": 205, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y30": { + "bits": {}, + "grid_x": 9, + "grid_y": 178, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y31": { + "bits": {}, + "grid_x": 9, + "grid_y": 177, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y32": { + "bits": {}, + "grid_x": 9, + "grid_y": 176, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y33": { + "bits": {}, + "grid_x": 9, + "grid_y": 175, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y34": { + "bits": {}, + "grid_x": 9, + "grid_y": 174, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y35": { + "bits": {}, + "grid_x": 9, + "grid_y": 173, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y36": { + "bits": {}, + "grid_x": 9, + "grid_y": 172, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y37": { + "bits": {}, + "grid_x": 9, + "grid_y": 171, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y38": { + "bits": {}, + "grid_x": 9, + "grid_y": 170, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y39": { + "bits": {}, + "grid_x": 9, + "grid_y": 169, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y4": { + "bits": {}, + "grid_x": 9, + "grid_y": 204, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y40": { + "bits": {}, + "grid_x": 9, + "grid_y": 168, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y41": { + "bits": {}, + "grid_x": 9, + "grid_y": 167, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y42": { + "bits": {}, + "grid_x": 9, + "grid_y": 166, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y43": { + "bits": {}, + "grid_x": 9, + "grid_y": 165, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y44": { + "bits": {}, + "grid_x": 9, + "grid_y": 164, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y45": { + "bits": {}, + "grid_x": 9, + "grid_y": 163, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y46": { + "bits": {}, + "grid_x": 9, + "grid_y": 162, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y47": { + "bits": {}, + "grid_x": 9, + "grid_y": 161, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y48": { + "bits": {}, + "grid_x": 9, + "grid_y": 160, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y49": { + "bits": {}, + "grid_x": 9, + "grid_y": 159, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y5": { + "bits": {}, + "grid_x": 9, + "grid_y": 203, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y50": { + "bits": {}, + "grid_x": 9, + "grid_y": 158, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y51": { + "bits": {}, + "grid_x": 9, + "grid_y": 157, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y53": { + "bits": {}, + "grid_x": 9, + "grid_y": 155, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y54": { + "bits": {}, + "grid_x": 9, + "grid_y": 154, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y55": { + "bits": {}, + "grid_x": 9, + "grid_y": 153, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y56": { + "bits": {}, + "grid_x": 9, + "grid_y": 152, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y57": { + "bits": {}, + "grid_x": 9, + "grid_y": 151, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y58": { + "bits": {}, + "grid_x": 9, + "grid_y": 150, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y59": { + "bits": {}, + "grid_x": 9, + "grid_y": 149, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y6": { + "bits": {}, + "grid_x": 9, + "grid_y": 202, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y60": { + "bits": {}, + "grid_x": 9, + "grid_y": 148, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y61": { + "bits": {}, + "grid_x": 9, + "grid_y": 147, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y62": { + "bits": {}, + "grid_x": 9, + "grid_y": 146, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y63": { + "bits": {}, + "grid_x": 9, + "grid_y": 145, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y64": { + "bits": {}, + "grid_x": 9, + "grid_y": 144, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y65": { + "bits": {}, + "grid_x": 9, + "grid_y": 143, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y66": { + "bits": {}, + "grid_x": 9, + "grid_y": 142, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y67": { + "bits": {}, + "grid_x": 9, + "grid_y": 141, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y68": { + "bits": {}, + "grid_x": 9, + "grid_y": 140, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y69": { + "bits": {}, + "grid_x": 9, + "grid_y": 139, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y7": { + "bits": {}, + "grid_x": 9, + "grid_y": 201, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y70": { + "bits": {}, + "grid_x": 9, + "grid_y": 138, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y71": { + "bits": {}, + "grid_x": 9, + "grid_y": 137, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y72": { + "bits": {}, + "grid_x": 9, + "grid_y": 136, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y73": { + "bits": {}, + "grid_x": 9, + "grid_y": 135, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y74": { + "bits": {}, + "grid_x": 9, + "grid_y": 134, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y75": { + "bits": {}, + "grid_x": 9, + "grid_y": 133, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y76": { + "bits": {}, + "grid_x": 9, + "grid_y": 132, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y77": { + "bits": {}, + "grid_x": 9, + "grid_y": 131, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y79": { + "bits": {}, + "grid_x": 9, + "grid_y": 129, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y8": { + "bits": {}, + "grid_x": 9, + "grid_y": 200, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y80": { + "bits": {}, + "grid_x": 9, + "grid_y": 128, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y81": { + "bits": {}, + "grid_x": 9, + "grid_y": 127, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y82": { + "bits": {}, + "grid_x": 9, + "grid_y": 126, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y83": { + "bits": {}, + "grid_x": 9, + "grid_y": 125, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y84": { + "bits": {}, + "grid_x": 9, + "grid_y": 124, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y85": { + "bits": {}, + "grid_x": 9, + "grid_y": 123, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y86": { + "bits": {}, + "grid_x": 9, + "grid_y": 122, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y87": { + "bits": {}, + "grid_x": 9, + "grid_y": 121, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y88": { + "bits": {}, + "grid_x": 9, + "grid_y": 120, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y89": { + "bits": {}, + "grid_x": 9, + "grid_y": 119, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y9": { + "bits": {}, + "grid_x": 9, + "grid_y": 199, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y90": { + "bits": {}, + "grid_x": 9, + "grid_y": 118, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y91": { + "bits": {}, + "grid_x": 9, + "grid_y": 117, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y92": { + "bits": {}, + "grid_x": 9, + "grid_y": 116, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y93": { + "bits": {}, + "grid_x": 9, + "grid_y": 115, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y94": { + "bits": {}, + "grid_x": 9, + "grid_y": 114, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y95": { + "bits": {}, + "grid_x": 9, + "grid_y": 113, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y96": { + "bits": {}, + "grid_x": 9, + "grid_y": 112, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y97": { + "bits": {}, + "grid_x": 9, + "grid_y": 111, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y98": { + "bits": {}, + "grid_x": 9, + "grid_y": 110, + "sites": {}, + "type": "VBRK" + }, + "VBRK_X9Y99": { + "bits": {}, + "grid_x": 9, + "grid_y": 109, + "sites": {}, + "type": "VBRK" + }, + "VFRAME_X62Y1": { + "bits": {}, + "grid_x": 62, + "grid_y": 207, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y10": { + "bits": {}, + "grid_x": 62, + "grid_y": 198, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y100": { + "bits": {}, + "grid_x": 62, + "grid_y": 108, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y101": { + "bits": {}, + "grid_x": 62, + "grid_y": 107, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y102": { + "bits": {}, + "grid_x": 62, + "grid_y": 106, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y103": { + "bits": {}, + "grid_x": 62, + "grid_y": 105, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y105": { + "bits": {}, + "grid_x": 62, + "grid_y": 103, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y106": { + "bits": {}, + "grid_x": 62, + "grid_y": 102, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y107": { + "bits": {}, + "grid_x": 62, + "grid_y": 101, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y108": { + "bits": {}, + "grid_x": 62, + "grid_y": 100, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y109": { + "bits": {}, + "grid_x": 62, + "grid_y": 99, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y11": { + "bits": {}, + "grid_x": 62, + "grid_y": 197, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y110": { + "bits": {}, + "grid_x": 62, + "grid_y": 98, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y111": { + "bits": {}, + "grid_x": 62, + "grid_y": 97, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y112": { + "bits": {}, + "grid_x": 62, + "grid_y": 96, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y113": { + "bits": {}, + "grid_x": 62, + "grid_y": 95, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y114": { + "bits": {}, + "grid_x": 62, + "grid_y": 94, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y115": { + "bits": {}, + "grid_x": 62, + "grid_y": 93, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y116": { + "bits": {}, + "grid_x": 62, + "grid_y": 92, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y117": { + "bits": {}, + "grid_x": 62, + "grid_y": 91, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y118": { + "bits": {}, + "grid_x": 62, + "grid_y": 90, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y119": { + "bits": {}, + "grid_x": 62, + "grid_y": 89, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y12": { + "bits": {}, + "grid_x": 62, + "grid_y": 196, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y120": { + "bits": {}, + "grid_x": 62, + "grid_y": 88, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y121": { + "bits": {}, + "grid_x": 62, + "grid_y": 87, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y122": { + "bits": {}, + "grid_x": 62, + "grid_y": 86, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y123": { + "bits": {}, + "grid_x": 62, + "grid_y": 85, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y124": { + "bits": {}, + "grid_x": 62, + "grid_y": 84, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y125": { + "bits": {}, + "grid_x": 62, + "grid_y": 83, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y126": { + "bits": {}, + "grid_x": 62, + "grid_y": 82, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y127": { + "bits": {}, + "grid_x": 62, + "grid_y": 81, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y128": { + "bits": {}, + "grid_x": 62, + "grid_y": 80, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y129": { + "bits": {}, + "grid_x": 62, + "grid_y": 79, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y13": { + "bits": {}, + "grid_x": 62, + "grid_y": 195, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y131": { + "bits": {}, + "grid_x": 62, + "grid_y": 77, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y132": { + "bits": {}, + "grid_x": 62, + "grid_y": 76, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y133": { + "bits": {}, + "grid_x": 62, + "grid_y": 75, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y134": { + "bits": {}, + "grid_x": 62, + "grid_y": 74, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y135": { + "bits": {}, + "grid_x": 62, + "grid_y": 73, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y136": { + "bits": {}, + "grid_x": 62, + "grid_y": 72, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y137": { + "bits": {}, + "grid_x": 62, + "grid_y": 71, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y138": { + "bits": {}, + "grid_x": 62, + "grid_y": 70, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y139": { + "bits": {}, + "grid_x": 62, + "grid_y": 69, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y14": { + "bits": {}, + "grid_x": 62, + "grid_y": 194, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y140": { + "bits": {}, + "grid_x": 62, + "grid_y": 68, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y141": { + "bits": {}, + "grid_x": 62, + "grid_y": 67, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y142": { + "bits": {}, + "grid_x": 62, + "grid_y": 66, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y143": { + "bits": {}, + "grid_x": 62, + "grid_y": 65, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y144": { + "bits": {}, + "grid_x": 62, + "grid_y": 64, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y145": { + "bits": {}, + "grid_x": 62, + "grid_y": 63, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y146": { + "bits": {}, + "grid_x": 62, + "grid_y": 62, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y147": { + "bits": {}, + "grid_x": 62, + "grid_y": 61, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y148": { + "bits": {}, + "grid_x": 62, + "grid_y": 60, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y149": { + "bits": {}, + "grid_x": 62, + "grid_y": 59, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y15": { + "bits": {}, + "grid_x": 62, + "grid_y": 193, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y150": { + "bits": {}, + "grid_x": 62, + "grid_y": 58, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y151": { + "bits": {}, + "grid_x": 62, + "grid_y": 57, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y152": { + "bits": {}, + "grid_x": 62, + "grid_y": 56, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y153": { + "bits": {}, + "grid_x": 62, + "grid_y": 55, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y154": { + "bits": {}, + "grid_x": 62, + "grid_y": 54, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y155": { + "bits": {}, + "grid_x": 62, + "grid_y": 53, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y157": { + "bits": {}, + "grid_x": 62, + "grid_y": 51, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y158": { + "bits": {}, + "grid_x": 62, + "grid_y": 50, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y159": { + "bits": {}, + "grid_x": 62, + "grid_y": 49, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y16": { + "bits": {}, + "grid_x": 62, + "grid_y": 192, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y160": { + "bits": {}, + "grid_x": 62, + "grid_y": 48, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y161": { + "bits": {}, + "grid_x": 62, + "grid_y": 47, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y162": { + "bits": {}, + "grid_x": 62, + "grid_y": 46, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y163": { + "bits": {}, + "grid_x": 62, + "grid_y": 45, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y164": { + "bits": {}, + "grid_x": 62, + "grid_y": 44, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y165": { + "bits": {}, + "grid_x": 62, + "grid_y": 43, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y166": { + "bits": {}, + "grid_x": 62, + "grid_y": 42, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y167": { + "bits": {}, + "grid_x": 62, + "grid_y": 41, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y168": { + "bits": {}, + "grid_x": 62, + "grid_y": 40, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y169": { + "bits": {}, + "grid_x": 62, + "grid_y": 39, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y17": { + "bits": {}, + "grid_x": 62, + "grid_y": 191, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y170": { + "bits": {}, + "grid_x": 62, + "grid_y": 38, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y171": { + "bits": {}, + "grid_x": 62, + "grid_y": 37, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y172": { + "bits": {}, + "grid_x": 62, + "grid_y": 36, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y173": { + "bits": {}, + "grid_x": 62, + "grid_y": 35, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y174": { + "bits": {}, + "grid_x": 62, + "grid_y": 34, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y175": { + "bits": {}, + "grid_x": 62, + "grid_y": 33, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y176": { + "bits": {}, + "grid_x": 62, + "grid_y": 32, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y177": { + "bits": {}, + "grid_x": 62, + "grid_y": 31, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y178": { + "bits": {}, + "grid_x": 62, + "grid_y": 30, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y179": { + "bits": {}, + "grid_x": 62, + "grid_y": 29, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y18": { + "bits": {}, + "grid_x": 62, + "grid_y": 190, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y180": { + "bits": {}, + "grid_x": 62, + "grid_y": 28, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y181": { + "bits": {}, + "grid_x": 62, + "grid_y": 27, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y183": { + "bits": {}, + "grid_x": 62, + "grid_y": 25, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y184": { + "bits": {}, + "grid_x": 62, + "grid_y": 24, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y185": { + "bits": {}, + "grid_x": 62, + "grid_y": 23, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y186": { + "bits": {}, + "grid_x": 62, + "grid_y": 22, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y187": { + "bits": {}, + "grid_x": 62, + "grid_y": 21, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y188": { + "bits": {}, + "grid_x": 62, + "grid_y": 20, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y189": { + "bits": {}, + "grid_x": 62, + "grid_y": 19, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y19": { + "bits": {}, + "grid_x": 62, + "grid_y": 189, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y190": { + "bits": {}, + "grid_x": 62, + "grid_y": 18, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y191": { + "bits": {}, + "grid_x": 62, + "grid_y": 17, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y192": { + "bits": {}, + "grid_x": 62, + "grid_y": 16, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y193": { + "bits": {}, + "grid_x": 62, + "grid_y": 15, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y194": { + "bits": {}, + "grid_x": 62, + "grid_y": 14, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y195": { + "bits": {}, + "grid_x": 62, + "grid_y": 13, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y196": { + "bits": {}, + "grid_x": 62, + "grid_y": 12, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y197": { + "bits": {}, + "grid_x": 62, + "grid_y": 11, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y198": { + "bits": {}, + "grid_x": 62, + "grid_y": 10, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y199": { + "bits": {}, + "grid_x": 62, + "grid_y": 9, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y2": { + "bits": {}, + "grid_x": 62, + "grid_y": 206, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y20": { + "bits": {}, + "grid_x": 62, + "grid_y": 188, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y200": { + "bits": {}, + "grid_x": 62, + "grid_y": 8, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y201": { + "bits": {}, + "grid_x": 62, + "grid_y": 7, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y202": { + "bits": {}, + "grid_x": 62, + "grid_y": 6, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y203": { + "bits": {}, + "grid_x": 62, + "grid_y": 5, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y204": { + "bits": {}, + "grid_x": 62, + "grid_y": 4, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y205": { + "bits": {}, + "grid_x": 62, + "grid_y": 3, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y206": { + "bits": {}, + "grid_x": 62, + "grid_y": 2, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y207": { + "bits": {}, + "grid_x": 62, + "grid_y": 1, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y21": { + "bits": {}, + "grid_x": 62, + "grid_y": 187, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y22": { + "bits": {}, + "grid_x": 62, + "grid_y": 186, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y23": { + "bits": {}, + "grid_x": 62, + "grid_y": 185, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y24": { + "bits": {}, + "grid_x": 62, + "grid_y": 184, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y25": { + "bits": {}, + "grid_x": 62, + "grid_y": 183, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y27": { + "bits": {}, + "grid_x": 62, + "grid_y": 181, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y28": { + "bits": {}, + "grid_x": 62, + "grid_y": 180, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y29": { + "bits": {}, + "grid_x": 62, + "grid_y": 179, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y3": { + "bits": {}, + "grid_x": 62, + "grid_y": 205, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y30": { + "bits": {}, + "grid_x": 62, + "grid_y": 178, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y31": { + "bits": {}, + "grid_x": 62, + "grid_y": 177, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y32": { + "bits": {}, + "grid_x": 62, + "grid_y": 176, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y33": { + "bits": {}, + "grid_x": 62, + "grid_y": 175, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y34": { + "bits": {}, + "grid_x": 62, + "grid_y": 174, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y35": { + "bits": {}, + "grid_x": 62, + "grid_y": 173, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y36": { + "bits": {}, + "grid_x": 62, + "grid_y": 172, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y37": { + "bits": {}, + "grid_x": 62, + "grid_y": 171, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y38": { + "bits": {}, + "grid_x": 62, + "grid_y": 170, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y39": { + "bits": {}, + "grid_x": 62, + "grid_y": 169, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y4": { + "bits": {}, + "grid_x": 62, + "grid_y": 204, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y40": { + "bits": {}, + "grid_x": 62, + "grid_y": 168, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y41": { + "bits": {}, + "grid_x": 62, + "grid_y": 167, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y42": { + "bits": {}, + "grid_x": 62, + "grid_y": 166, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y43": { + "bits": {}, + "grid_x": 62, + "grid_y": 165, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y44": { + "bits": {}, + "grid_x": 62, + "grid_y": 164, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y45": { + "bits": {}, + "grid_x": 62, + "grid_y": 163, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y46": { + "bits": {}, + "grid_x": 62, + "grid_y": 162, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y47": { + "bits": {}, + "grid_x": 62, + "grid_y": 161, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y48": { + "bits": {}, + "grid_x": 62, + "grid_y": 160, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y49": { + "bits": {}, + "grid_x": 62, + "grid_y": 159, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y5": { + "bits": {}, + "grid_x": 62, + "grid_y": 203, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y50": { + "bits": {}, + "grid_x": 62, + "grid_y": 158, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y51": { + "bits": {}, + "grid_x": 62, + "grid_y": 157, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y53": { + "bits": {}, + "grid_x": 62, + "grid_y": 155, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y54": { + "bits": {}, + "grid_x": 62, + "grid_y": 154, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y55": { + "bits": {}, + "grid_x": 62, + "grid_y": 153, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y56": { + "bits": {}, + "grid_x": 62, + "grid_y": 152, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y57": { + "bits": {}, + "grid_x": 62, + "grid_y": 151, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y58": { + "bits": {}, + "grid_x": 62, + "grid_y": 150, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y59": { + "bits": {}, + "grid_x": 62, + "grid_y": 149, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y6": { + "bits": {}, + "grid_x": 62, + "grid_y": 202, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y60": { + "bits": {}, + "grid_x": 62, + "grid_y": 148, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y61": { + "bits": {}, + "grid_x": 62, + "grid_y": 147, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y62": { + "bits": {}, + "grid_x": 62, + "grid_y": 146, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y63": { + "bits": {}, + "grid_x": 62, + "grid_y": 145, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y64": { + "bits": {}, + "grid_x": 62, + "grid_y": 144, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y65": { + "bits": {}, + "grid_x": 62, + "grid_y": 143, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y66": { + "bits": {}, + "grid_x": 62, + "grid_y": 142, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y67": { + "bits": {}, + "grid_x": 62, + "grid_y": 141, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y68": { + "bits": {}, + "grid_x": 62, + "grid_y": 140, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y69": { + "bits": {}, + "grid_x": 62, + "grid_y": 139, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y7": { + "bits": {}, + "grid_x": 62, + "grid_y": 201, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y70": { + "bits": {}, + "grid_x": 62, + "grid_y": 138, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y71": { + "bits": {}, + "grid_x": 62, + "grid_y": 137, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y72": { + "bits": {}, + "grid_x": 62, + "grid_y": 136, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y73": { + "bits": {}, + "grid_x": 62, + "grid_y": 135, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y74": { + "bits": {}, + "grid_x": 62, + "grid_y": 134, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y75": { + "bits": {}, + "grid_x": 62, + "grid_y": 133, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y76": { + "bits": {}, + "grid_x": 62, + "grid_y": 132, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y77": { + "bits": {}, + "grid_x": 62, + "grid_y": 131, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y79": { + "bits": {}, + "grid_x": 62, + "grid_y": 129, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y8": { + "bits": {}, + "grid_x": 62, + "grid_y": 200, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y80": { + "bits": {}, + "grid_x": 62, + "grid_y": 128, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y81": { + "bits": {}, + "grid_x": 62, + "grid_y": 127, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y82": { + "bits": {}, + "grid_x": 62, + "grid_y": 126, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y83": { + "bits": {}, + "grid_x": 62, + "grid_y": 125, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y84": { + "bits": {}, + "grid_x": 62, + "grid_y": 124, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y85": { + "bits": {}, + "grid_x": 62, + "grid_y": 123, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y86": { + "bits": {}, + "grid_x": 62, + "grid_y": 122, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y87": { + "bits": {}, + "grid_x": 62, + "grid_y": 121, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y88": { + "bits": {}, + "grid_x": 62, + "grid_y": 120, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y89": { + "bits": {}, + "grid_x": 62, + "grid_y": 119, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y9": { + "bits": {}, + "grid_x": 62, + "grid_y": 199, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y90": { + "bits": {}, + "grid_x": 62, + "grid_y": 118, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y91": { + "bits": {}, + "grid_x": 62, + "grid_y": 117, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y92": { + "bits": {}, + "grid_x": 62, + "grid_y": 116, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y93": { + "bits": {}, + "grid_x": 62, + "grid_y": 115, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y94": { + "bits": {}, + "grid_x": 62, + "grid_y": 114, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y95": { + "bits": {}, + "grid_x": 62, + "grid_y": 113, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y96": { + "bits": {}, + "grid_x": 62, + "grid_y": 112, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y97": { + "bits": {}, + "grid_x": 62, + "grid_y": 111, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y98": { + "bits": {}, + "grid_x": 62, + "grid_y": 110, + "sites": {}, + "type": "VFRAME" + }, + "VFRAME_X62Y99": { + "bits": {}, + "grid_x": 62, + "grid_y": 109, + "sites": {}, + "type": "VFRAME" + } +} \ No newline at end of file diff --git a/kintex7/xc7k70tfbg676-2.yaml b/kintex7/xc7k70tfbg676-2.yaml index 0587985..0293099 100644 --- a/kintex7/xc7k70tfbg676-2.yaml +++ b/kintex7/xc7k70tfbg676-2.yaml @@ -1,2187 +1,387 @@ ! idcode: 0x3647093 -configuration_ranges: - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 0 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 0 - minor: 42 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 1 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 1 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 2 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 2 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 3 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 3 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 4 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 4 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 5 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 5 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 6 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 6 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 7 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 7 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 8 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 8 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 9 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 9 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 10 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 10 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 11 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 11 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 12 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 12 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 13 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 13 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 14 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 14 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 15 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 15 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 16 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 16 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 17 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 17 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 18 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 18 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 19 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 19 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 20 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 20 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 21 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 21 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 22 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 22 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 23 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 23 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 24 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 24 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 25 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 25 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 26 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 26 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 27 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 27 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 28 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 28 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 29 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 29 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 30 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 30 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 31 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 31 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 32 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 32 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 33 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 33 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 34 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 34 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 35 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 35 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 36 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 36 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 37 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 0 - column: 37 - minor: 32 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 0 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 0 - minor: 42 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 1 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 1 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 2 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 2 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 3 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 3 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 4 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 4 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 5 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 5 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 6 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 6 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 7 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 7 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 8 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 8 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 9 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 9 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 10 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 10 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 11 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 11 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 12 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 12 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 13 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 13 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 14 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 14 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 15 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 15 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 16 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 16 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 17 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 17 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 18 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 18 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 19 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 19 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 20 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 20 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 21 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 21 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 22 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 22 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 23 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 23 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 24 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 24 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 25 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 25 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 26 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 26 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 27 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 27 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 28 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 28 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 29 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 29 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 30 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 30 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 31 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 31 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 32 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 32 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 33 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 33 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 34 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 34 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 35 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 35 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 36 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 36 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 37 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: top - row: 1 - column: 37 - minor: 32 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 0 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 0 - minor: 42 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 1 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 1 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 2 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 2 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 3 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 3 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 4 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 4 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 5 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 5 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 6 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 6 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 7 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 7 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 8 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 8 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 9 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 9 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 10 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 10 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 11 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 11 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 12 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 12 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 13 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 13 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 14 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 14 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 15 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 15 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 16 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 16 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 17 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 17 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 18 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 18 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 19 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 19 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 20 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 20 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 21 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 21 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 22 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 22 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 23 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 23 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 24 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 24 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 25 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 25 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 26 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 26 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 27 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 27 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 28 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 28 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 29 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 29 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 30 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 30 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 31 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 31 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 32 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 32 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 33 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 33 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 34 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 34 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 35 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 35 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 36 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 36 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 37 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 37 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 38 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 38 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 39 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 39 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 40 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 40 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 41 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 41 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 42 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 42 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 43 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 0 - column: 43 - minor: 42 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 0 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 0 - minor: 42 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 1 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 1 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 2 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 2 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 3 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 3 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 4 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 4 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 5 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 5 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 6 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 6 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 7 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 7 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 8 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 8 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 9 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 9 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 10 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 10 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 11 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 11 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 12 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 12 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 13 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 13 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 14 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 14 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 15 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 15 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 16 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 16 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 17 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 17 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 18 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 18 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 19 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 19 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 20 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 20 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 21 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 21 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 22 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 22 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 23 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 23 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 24 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 24 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 25 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 25 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 26 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 26 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 27 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 27 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 28 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 28 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 29 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 29 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 30 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 30 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 31 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 31 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 32 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 32 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 33 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 33 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 34 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 34 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 35 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 35 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 36 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 36 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 37 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 37 - minor: 28 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 38 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 38 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 39 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 39 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 40 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 40 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 41 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 41 - minor: 36 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 42 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 42 - minor: 30 - - ! - begin: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 43 - minor: 0 - end: ! - block_type: CLB_IO_CLK - row_half: bottom - row: 1 - column: 43 - minor: 42 - - ! - begin: ! - block_type: BLOCK_RAM - row_half: top - row: 0 - column: 0 - minor: 0 - end: ! - block_type: BLOCK_RAM - row_half: top - row: 0 - column: 3 - minor: 0 - - ! - begin: ! - block_type: BLOCK_RAM - row_half: top - row: 1 - column: 0 - minor: 0 - end: ! - block_type: BLOCK_RAM - row_half: top - row: 1 - column: 3 - minor: 0 - - ! - begin: ! - block_type: BLOCK_RAM - row_half: bottom - row: 0 - column: 0 - minor: 0 - end: ! - block_type: BLOCK_RAM - row_half: bottom - row: 0 - column: 4 - minor: 0 - - ! - begin: ! - block_type: BLOCK_RAM - row_half: bottom - row: 1 - column: 0 - minor: 0 - end: ! - block_type: BLOCK_RAM - row_half: bottom - row: 1 - column: 4 - minor: 0 +global_clock_regions: + top: ! + rows: + 0: ! + configuration_buses: + CLB_IO_CLK: ! + configuration_columns: + 0: ! + frame_count: 42 + 1: ! + frame_count: 30 + 2: ! + frame_count: 36 + 3: ! + frame_count: 36 + 4: ! + frame_count: 36 + 5: ! + frame_count: 36 + 6: ! + frame_count: 28 + 7: ! + frame_count: 36 + 8: ! + frame_count: 36 + 9: ! + frame_count: 28 + 10: ! + frame_count: 36 + 11: ! + frame_count: 36 + 12: ! + frame_count: 36 + 13: ! + frame_count: 36 + 14: ! + frame_count: 28 + 15: ! + frame_count: 36 + 16: ! + frame_count: 36 + 17: ! + frame_count: 28 + 18: ! + frame_count: 36 + 19: ! + frame_count: 36 + 20: ! + frame_count: 36 + 21: ! + frame_count: 36 + 22: ! + frame_count: 36 + 23: ! + frame_count: 36 + 24: ! + frame_count: 30 + 25: ! + frame_count: 30 + 26: ! + frame_count: 36 + 27: ! + frame_count: 36 + 28: ! + frame_count: 36 + 29: ! + frame_count: 36 + 30: ! + frame_count: 28 + 31: ! + frame_count: 36 + 32: ! + frame_count: 36 + 33: ! + frame_count: 28 + 34: ! + frame_count: 36 + 35: ! + frame_count: 36 + 36: ! + frame_count: 36 + 37: ! + frame_count: 32 + BLOCK_RAM: ! + configuration_columns: + 0: ! + frame_count: 128 + 1: ! + frame_count: 128 + 2: ! + frame_count: 128 + 1: ! + configuration_buses: + CLB_IO_CLK: ! + configuration_columns: + 0: ! + frame_count: 42 + 1: ! + frame_count: 30 + 2: ! + frame_count: 36 + 3: ! + frame_count: 36 + 4: ! + frame_count: 36 + 5: ! + frame_count: 36 + 6: ! + frame_count: 28 + 7: ! + frame_count: 36 + 8: ! + frame_count: 36 + 9: ! + frame_count: 28 + 10: ! + frame_count: 36 + 11: ! + frame_count: 36 + 12: ! + frame_count: 36 + 13: ! + frame_count: 36 + 14: ! + frame_count: 28 + 15: ! + frame_count: 36 + 16: ! + frame_count: 36 + 17: ! + frame_count: 28 + 18: ! + frame_count: 36 + 19: ! + frame_count: 36 + 20: ! + frame_count: 36 + 21: ! + frame_count: 36 + 22: ! + frame_count: 36 + 23: ! + frame_count: 36 + 24: ! + frame_count: 30 + 25: ! + frame_count: 30 + 26: ! + frame_count: 36 + 27: ! + frame_count: 36 + 28: ! + frame_count: 36 + 29: ! + frame_count: 36 + 30: ! + frame_count: 28 + 31: ! + frame_count: 36 + 32: ! + frame_count: 36 + 33: ! + frame_count: 28 + 34: ! + frame_count: 36 + 35: ! + frame_count: 36 + 36: ! + frame_count: 36 + 37: ! + frame_count: 32 + BLOCK_RAM: ! + configuration_columns: + 0: ! + frame_count: 128 + 1: ! + frame_count: 128 + 2: ! + frame_count: 128 + bottom: ! + rows: + 0: ! + configuration_buses: + CLB_IO_CLK: ! + configuration_columns: + 0: ! + frame_count: 42 + 1: ! + frame_count: 30 + 2: ! + frame_count: 36 + 3: ! + frame_count: 36 + 4: ! + frame_count: 36 + 5: ! + frame_count: 36 + 6: ! + frame_count: 28 + 7: ! + frame_count: 36 + 8: ! + frame_count: 36 + 9: ! + frame_count: 28 + 10: ! + frame_count: 36 + 11: ! + frame_count: 36 + 12: ! + frame_count: 36 + 13: ! + frame_count: 36 + 14: ! + frame_count: 28 + 15: ! + frame_count: 36 + 16: ! + frame_count: 36 + 17: ! + frame_count: 28 + 18: ! + frame_count: 36 + 19: ! + frame_count: 36 + 20: ! + frame_count: 36 + 21: ! + frame_count: 36 + 22: ! + frame_count: 36 + 23: ! + frame_count: 36 + 24: ! + frame_count: 30 + 25: ! + frame_count: 30 + 26: ! + frame_count: 36 + 27: ! + frame_count: 36 + 28: ! + frame_count: 36 + 29: ! + frame_count: 36 + 30: ! + frame_count: 28 + 31: ! + frame_count: 36 + 32: ! + frame_count: 36 + 33: ! + frame_count: 28 + 34: ! + frame_count: 36 + 35: ! + frame_count: 36 + 36: ! + frame_count: 36 + 37: ! + frame_count: 28 + 38: ! + frame_count: 36 + 39: ! + frame_count: 36 + 40: ! + frame_count: 36 + 41: ! + frame_count: 36 + 42: ! + frame_count: 30 + 43: ! + frame_count: 42 + BLOCK_RAM: ! + configuration_columns: + 0: ! + frame_count: 128 + 1: ! + frame_count: 128 + 2: ! + frame_count: 128 + 3: ! + frame_count: 128 + 1: ! + configuration_buses: + CLB_IO_CLK: ! + configuration_columns: + 0: ! + frame_count: 42 + 1: ! + frame_count: 30 + 2: ! + frame_count: 36 + 3: ! + frame_count: 36 + 4: ! + frame_count: 36 + 5: ! + frame_count: 36 + 6: ! + frame_count: 28 + 7: ! + frame_count: 36 + 8: ! + frame_count: 36 + 9: ! + frame_count: 28 + 10: ! + frame_count: 36 + 11: ! + frame_count: 36 + 12: ! + frame_count: 36 + 13: ! + frame_count: 36 + 14: ! + frame_count: 28 + 15: ! + frame_count: 36 + 16: ! + frame_count: 36 + 17: ! + frame_count: 28 + 18: ! + frame_count: 36 + 19: ! + frame_count: 36 + 20: ! + frame_count: 36 + 21: ! + frame_count: 36 + 22: ! + frame_count: 36 + 23: ! + frame_count: 36 + 24: ! + frame_count: 30 + 25: ! + frame_count: 30 + 26: ! + frame_count: 36 + 27: ! + frame_count: 36 + 28: ! + frame_count: 36 + 29: ! + frame_count: 36 + 30: ! + frame_count: 28 + 31: ! + frame_count: 36 + 32: ! + frame_count: 36 + 33: ! + frame_count: 28 + 34: ! + frame_count: 36 + 35: ! + frame_count: 36 + 36: ! + frame_count: 36 + 37: ! + frame_count: 28 + 38: ! + frame_count: 36 + 39: ! + frame_count: 36 + 40: ! + frame_count: 36 + 41: ! + frame_count: 36 + 42: ! + frame_count: 30 + 43: ! + frame_count: 42 + BLOCK_RAM: ! + configuration_columns: + 0: ! + frame_count: 128 + 1: ! + frame_count: 128 + 2: ! + frame_count: 128 + 3: ! + frame_count: 128